From shawn.guo at linaro.org  Wed Aug  1 00:50:12 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 12:50:12 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801033559.GB2323@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120731205300.GA25721@roeck-us.net>
 <201208010431.04399.marex@denx.de>
 <20120801035333.GB1672@S2100-06.ap.freescale.net>
 <20120801033559.GB2323@roeck-us.net>
Message-ID: <20120801045010.GC1672@S2100-06.ap.freescale.net>

On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
> I think the call to spi_master_put() triggers the call to spi_master_release().
> If so, kfree() would not be needed at all, and the documentation is wrong.
> 
Also those drivers calling kfree in probe.

Regards,
Shawn



From bryan.wu at canonical.com  Wed Aug  1 00:48:10 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Wed, 1 Aug 2012 12:48:10 +0800
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
Message-ID: <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>

On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> Russell, Arnd and Olof,
>

I felt very sorry about this issue, the email was archived
automatically in my Gmail account. I found the root cause of the issue
Russell met and actually that code about trigger_data is totally
useless, which was removed just now. I pushed an update version again
to the same branch of my git tree. Please consider a pull. If I did
something bad, please let me know, I will fix it as soon as possible.

The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:

  Linux 3.5 (2012-07-21 13:58:29 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git
for-arm-soc

for you to fetch changes up to fa8bbb13ab49e77c00fa09e5504ec25b7176fb4b:

  ARM: use new LEDS CPU trigger stub to replace old one (2012-08-01
11:22:14 +0800)

----------------------------------------------------------------
Bryan Wu (18):
      led-triggers: create a trigger for CPU activity
      ARM: at91: convert old leds drivers to gpio_led and led_trigger drivers
      ARM: mach-realview and mach-versatile: retire custom LED code
      ARM: mach-ks8695: remove leds driver, since nobody use it
      ARM: mach-shark: retire custom LED code
      ARM: mach-orion5x: convert custom LED code to gpio_led and LED CPU trigger
      ARM: mach-integrator: move CM_CTRL to header file for accessing
by other functions
      ARM: mach-integrator: retire custom LED code
      ARM: mach-clps711x: retire custom LED code of P720T machine
      ARM: mach-ebsa110: retire custom LED code
      ARM: mach-footbridge: retire custom LED code
      char: nwflash: remove old led event code
      ARM: mach-pxa: retire custom LED code
      ARM: plat-samsung: remove including old leds event API header file
      ARM: mach-pnx4008: remove including old leds event API header file
      ARM: mach-omap1: retire custom LED code
      ARM: mach-sa1100: retire custom LED code
      ARM: use new LEDS CPU trigger stub to replace old one

 arch/arm/Kconfig                             |  53 -----
 arch/arm/include/asm/leds.h                  |  50 -----
 arch/arm/kernel/Makefile                     |   1 -
 arch/arm/kernel/leds.c                       | 121 -----------
 arch/arm/kernel/process.c                    |   6 +-
 arch/arm/kernel/time.c                       |  17 --
 arch/arm/mach-at91/board-csb337.c            |   2 -
 arch/arm/mach-at91/board-ecbat91.c           |  18 +-
 arch/arm/mach-at91/board-eco920.c            |  22 +-
 arch/arm/mach-at91/board-kafa.c              |  17 +-
 arch/arm/mach-at91/board-kb9202.c            |  23 ++-
 arch/arm/mach-at91/board-rm9200dk.c          |   3 -
 arch/arm/mach-at91/board-rm9200ek.c          |   3 -
 arch/arm/mach-at91/board-rsi-ews.c           |   3 -
 arch/arm/mach-at91/board-sam9-l9260.c        |  23 ++-
 arch/arm/mach-at91/board-sam9261ek.c         |   3 -
 arch/arm/mach-at91/board-yl-9200.c           |   3 -
 arch/arm/mach-at91/include/mach/board.h      |   1 -
 arch/arm/mach-at91/leds.c                    | 105 ----------
 arch/arm/mach-clps711x/Makefile              |   2 -
 arch/arm/mach-clps711x/common.c              |   1 -
 arch/arm/mach-clps711x/p720t-leds.c          |  63 ------
 arch/arm/mach-clps711x/p720t.c               |  61 ++++++
 arch/arm/mach-ebsa110/Makefile               |   4 +-
 arch/arm/mach-ebsa110/leds.c                 |  81 +++++---
 arch/arm/mach-footbridge/Makefile            |   4 -
 arch/arm/mach-footbridge/ebsa285-leds.c      | 138 -------------
 arch/arm/mach-footbridge/ebsa285.c           |  81 ++++++++
 arch/arm/mach-footbridge/netwinder-hw.c      | 112 ++++++++--
 arch/arm/mach-footbridge/netwinder-leds.c    | 138 -------------
 arch/arm/mach-integrator/Makefile            |   3 +-
 arch/arm/mach-integrator/core.c              |   3 -
 arch/arm/mach-integrator/include/mach/cm.h   |   2 +
 arch/arm/mach-integrator/leds.c              | 161 +++++++++------
 arch/arm/mach-ks8695/Makefile                |   3 -
 arch/arm/mach-ks8695/devices.c               |  21 --
 arch/arm/mach-ks8695/include/mach/devices.h  |   5 -
 arch/arm/mach-ks8695/leds.c                  |  92 ---------
 arch/arm/mach-omap1/Makefile                 |   8 -
 arch/arm/mach-omap1/board-h2.c               |  32 +++
 arch/arm/mach-omap1/board-h3.c               |  32 +++
 arch/arm/mach-omap1/board-osk.c              |  33 +++
 arch/arm/mach-omap1/leds-h2p2-debug.c        | 166 ---------------
 arch/arm/mach-omap1/leds-innovator.c         |  98 ---------
 arch/arm/mach-omap1/leds-osk.c               | 113 -----------
 arch/arm/mach-omap1/leds.c                   |  69 -------
 arch/arm/mach-omap1/leds.h                   |   3 -
 arch/arm/mach-omap1/time.c                   |   1 -
 arch/arm/mach-omap1/timer32k.c               |   1 -
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |   1 -
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c  |   1 -
 arch/arm/mach-orion5x/rd88f5182-setup.c      |  72 ++-----
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c |   1 -
 arch/arm/mach-pnx4008/time.c                 |   1 -
 arch/arm/mach-pxa/Makefile                   |   8 -
 arch/arm/mach-pxa/idp.c                      |  81 ++++++++
 arch/arm/mach-pxa/leds-idp.c                 | 115 -----------
 arch/arm/mach-pxa/leds-lubbock.c             | 124 ------------
 arch/arm/mach-pxa/leds-mainstone.c           | 119 -----------
 arch/arm/mach-pxa/leds.c                     |  32 ---
 arch/arm/mach-pxa/leds.h                     |  13 --
 arch/arm/mach-pxa/lubbock.c                  |  95 +++++++++
 arch/arm/mach-pxa/mainstone.c                |  94 +++++++++
 arch/arm/mach-realview/core.c                |  39 ----
 arch/arm/mach-realview/core.h                |   2 -
 arch/arm/mach-realview/realview_eb.c         |   5 -
 arch/arm/mach-realview/realview_pb1176.c     |   5 -
 arch/arm/mach-realview/realview_pb11mp.c     |   5 -
 arch/arm/mach-realview/realview_pba8.c       |   5 -
 arch/arm/mach-realview/realview_pbx.c        |   5 -
 arch/arm/mach-sa1100/Makefile                |   9 -
 arch/arm/mach-sa1100/assabet.c               |  85 ++++++++
 arch/arm/mach-sa1100/badge4.c                |  30 +++
 arch/arm/mach-sa1100/cerf.c                  |  42 ++++
 arch/arm/mach-sa1100/hackkit.c               |  32 +++
 arch/arm/mach-sa1100/lart.c                  |  26 +++
 arch/arm/mach-sa1100/leds-assabet.c          | 113 -----------
 arch/arm/mach-sa1100/leds-badge4.c           | 110 ----------
 arch/arm/mach-sa1100/leds-cerf.c             | 109 ----------
 arch/arm/mach-sa1100/leds-hackkit.c          | 111 ----------
 arch/arm/mach-sa1100/leds-lart.c             | 100 ---------
 arch/arm/mach-sa1100/leds.c                  |  50 -----
 arch/arm/mach-sa1100/leds.h                  |  13 --
 arch/arm/mach-shark/Makefile                 |   4 +-
 arch/arm/mach-shark/core.c                   |   1 -
 arch/arm/mach-shark/leds.c                   | 220 ++++++++------------
 arch/arm/mach-versatile/core.c               |   5 -
 arch/arm/plat-omap/Kconfig                   |   3 +-
 arch/arm/plat-omap/debug-leds.c              | 293 ++++++---------------------
 arch/arm/plat-samsung/time.c                 |   1 -
 arch/arm/plat-versatile/Kconfig              |   4 +-
 arch/arm/plat-versatile/leds.c               |   8 +-
 drivers/char/nwflash.c                       |  34 ----
 drivers/leds/Kconfig                         |  10 +
 drivers/leds/Makefile                        |   1 +
 drivers/leds/ledtrig-cpu.c                   | 163 +++++++++++++++
 include/linux/leds.h                         |  16 ++
 97 files changed, 1440 insertions(+), 2981 deletions(-)
 delete mode 100644 arch/arm/include/asm/leds.h
 delete mode 100644 arch/arm/kernel/leds.c
 delete mode 100644 arch/arm/mach-clps711x/p720t-leds.c
 delete mode 100644 arch/arm/mach-footbridge/ebsa285-leds.c
 delete mode 100644 arch/arm/mach-footbridge/netwinder-leds.c
 delete mode 100644 arch/arm/mach-ks8695/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds-h2p2-debug.c
 delete mode 100644 arch/arm/mach-omap1/leds-innovator.c
 delete mode 100644 arch/arm/mach-omap1/leds-osk.c
 delete mode 100644 arch/arm/mach-omap1/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds.h
 delete mode 100644 arch/arm/mach-pxa/leds-idp.c
 delete mode 100644 arch/arm/mach-pxa/leds-lubbock.c
 delete mode 100644 arch/arm/mach-pxa/leds-mainstone.c
 delete mode 100644 arch/arm/mach-pxa/leds.c
 delete mode 100644 arch/arm/mach-pxa/leds.h
 delete mode 100644 arch/arm/mach-sa1100/leds-assabet.c
 delete mode 100644 arch/arm/mach-sa1100/leds-badge4.c
 delete mode 100644 arch/arm/mach-sa1100/leds-cerf.c
 delete mode 100644 arch/arm/mach-sa1100/leds-hackkit.c
 delete mode 100644 arch/arm/mach-sa1100/leds-lart.c
 delete mode 100644 arch/arm/mach-sa1100/leds.c
 delete mode 100644 arch/arm/mach-sa1100/leds.h
 create mode 100644 drivers/leds/ledtrig-cpu.c

--
Thanks,
-Bryan


From marex at denx.de  Wed Aug  1 00:48:05 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 1 Aug 2012 06:48:05 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801035333.GB1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010431.04399.marex@denx.de>
 <20120801035333.GB1672@S2100-06.ap.freescale.net>
Message-ID: <201208010648.05325.marex@denx.de>

Dear Shawn Guo,

> On Wed, Aug 01, 2012 at 04:31:04AM +0200, Marek Vasut wrote:
> > > Couple of reasons for asking: No other SPI master driver calls it in
> > > the remove function (unless I missed it), most drivers don't call it
> > > in the probe function error path, and if I call it in the remove
> > > function in a SPI master driver I am working on, and load/unload the
> > > module several times in a row, I get a nasty kernel crash.
> > 
> > It seems the spi_master class takes care of that kfree() in
> > spi.c:spi_master_release() . Good catch, thanks!
> 
> I do not hardware setup to confirm that right away.  When
> spi_master_release will be called exactly?  The time that
> spi_master_put gets called?  I'm trying to understand if the kfree
> is not needed only in remove function, or both probe and remove.

I checked, it's called in both cases ... (if .probe() crashes, release() is 
called, so kfree() is unneeded)

> Regards,
> Shawn

Best regards,
Marek Vasut


From olof at lixom.net  Wed Aug  1 00:55:38 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 31 Jul 2012 21:55:38 -0700
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
Message-ID: <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>

On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> Russell, Arnd and Olof,
>>
>
> I felt very sorry about this issue, the email was archived
> automatically in my Gmail account. I found the root cause of the issue
> Russell met and actually that code about trigger_data is totally
> useless, which was removed just now. I pushed an update version again
> to the same branch of my git tree. Please consider a pull. If I did
> something bad, please let me know, I will fix it as soon as possible.

Hi,

We'll pull this in for staging again once the merge window is done.
It's definitely not 3.6 material at this time.


-Olof


From bryan.wu at canonical.com  Wed Aug  1 00:59:09 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Wed, 1 Aug 2012 12:59:09 +0800
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
Message-ID: <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>

On Wed, Aug 1, 2012 at 12:55 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>>> Russell, Arnd and Olof,
>>>
>>
>> I felt very sorry about this issue, the email was archived
>> automatically in my Gmail account. I found the root cause of the issue
>> Russell met and actually that code about trigger_data is totally
>> useless, which was removed just now. I pushed an update version again
>> to the same branch of my git tree. Please consider a pull. If I did
>> something bad, please let me know, I will fix it as soon as possible.
>
> Hi,
>
> We'll pull this in for staging again once the merge window is done.
> It's definitely not 3.6 material at this time.
>

OK, I will rebase to 3.6-rc1 after merge window close and send out
pull request again.

Thanks,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer    +86.186-168-78255 Mobile
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From marex at denx.de  Wed Aug  1 01:00:54 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 1 Aug 2012 07:00:54 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801045010.GC1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
Message-ID: <201208010700.54829.marex@denx.de>

Dear Shawn Guo,

> On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
> > I think the call to spi_master_put() triggers the call to
> > spi_master_release(). If so, kfree() would not be needed at all, and the
> > documentation is wrong.
> 
> Also those drivers calling kfree in probe.

Looks like that to me ...

> Regards,
> Shawn

Best regards,
Marek Vasut


From shawn.guo at linaro.org  Wed Aug  1 01:24:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 13:24:26 +0800
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED
 Controller
In-Reply-To: <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120801052424.GD1672@S2100-06.ap.freescale.net>

On Tue, Jul 31, 2012 at 12:29:33PM +0200, Maxime Ripard wrote:
> +Optional properties:
> +  - oled-reset-active-low: Is the reset gpio is active on physical low?

You may want to take a look at commit c1cb438 (bindings: update imx and
mxs #gpio-cells) which got merged recently.  In case the driver will
only work on mxs, this optional property can just be dropped.

Regards,
Shawn



From olof at lixom.net  Wed Aug  1 01:10:55 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 31 Jul 2012 22:10:55 -0700
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
 <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
Message-ID: <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>

On Tue, Jul 31, 2012 at 9:59 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> On Wed, Aug 1, 2012 at 12:55 PM, Olof Johansson <olof at lixom.net> wrote:
>> On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>>> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>>>> Russell, Arnd and Olof,
>>>>
>>>
>>> I felt very sorry about this issue, the email was archived
>>> automatically in my Gmail account. I found the root cause of the issue
>>> Russell met and actually that code about trigger_data is totally
>>> useless, which was removed just now. I pushed an update version again
>>> to the same branch of my git tree. Please consider a pull. If I did
>>> something bad, please let me know, I will fix it as soon as possible.
>>
>> Hi,
>>
>> We'll pull this in for staging again once the merge window is done.
>> It's definitely not 3.6 material at this time.
>>
>
> OK, I will rebase to 3.6-rc1 after merge window close and send out
> pull request again.

No need to rebase unless there are large merge conflicts.


-Olof


From linux at roeck-us.net  Wed Aug  1 01:29:47 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 22:29:47 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208010700.54829.marex@denx.de>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
Message-ID: <20120801052947.GA2400@roeck-us.net>

On Wed, Aug 01, 2012 at 07:00:54AM +0200, Marek Vasut wrote:
> Dear Shawn Guo,
> 
> > On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
> > > I think the call to spi_master_put() triggers the call to
> > > spi_master_release(). If so, kfree() would not be needed at all, and the
> > > documentation is wrong.
> > 
> > Also those drivers calling kfree in probe.
> 
> Looks like that to me ...
> 
Doesn't seem to be far spread, fortunately. Only spi-davinci.c, spi-imx.c, and
spi-omap2-mcspi.c as far as I can see, plus the misleading comment in spi.c.

Anyone up for writing some patches ? If not, I'll do it.

Thanks,
Guenter


From shawn.guo at linaro.org  Wed Aug  1 01:58:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 13:58:56 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801052947.GA2400@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
Message-ID: <20120801055854.GE1672@S2100-06.ap.freescale.net>

On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> Anyone up for writing some patches ? If not, I'll do it.
> 
Go ahead.

Regards,
Shawn



From linux at roeck-us.net  Wed Aug  1 01:42:28 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 22:42:28 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801055854.GE1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
 <20120801055854.GE1672@S2100-06.ap.freescale.net>
Message-ID: <20120801054228.GA2645@roeck-us.net>

On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > Anyone up for writing some patches ? If not, I'll do it.
> > 
> Go ahead.
> 
Ok, will do. It isn't that simple, actually, since at least some of the drivers
also call spi_master_get(), and thus need two calls to spi_master_put() (or a
call to spi_master_put and a call to kfree).

Guenter


From jg1.han at samsung.com  Wed Aug  1 01:44:16 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 01 Aug 2012 14:44:16 +0900
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED
 Controller
In-Reply-To: <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <004701cd6fa8$b08e0a20$11aa1e60$%han@samsung.com>

On Tuesday, July 31, 2012 7:30 PM Maxime Ripard wrote:
> 
> This patch adds support for the Solomon SSD1307 OLED
> controller found on the Crystalfontz CFA10036 board.
> 
> This controller can drive a display with a resolution up
> to 128x39 and can operate over I2C or SPI.
> 
> The current driver has only been tested on the CFA-10036,
> that is using this controller over I2C to driver a 96x16
> OLED screen.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Cc: Brian Lilly <brian at crystalfontz.com>
> ---
>  .../devicetree/bindings/video/ssd1307fb.txt        |   24 ++
>  drivers/video/Kconfig                              |   14 +
>  drivers/video/Makefile                             |    1 +
>  drivers/video/ssd1307fb.c                          |  418 ++++++++++++++++++++
>  4 files changed, 457 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/video/ssd1307fb.txt
>  create mode 100644 drivers/video/ssd1307fb.c
> 
> diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt
> b/Documentation/devicetree/bindings/video/ssd1307fb.txt
> new file mode 100644
> index 0000000..791e14f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt
> @@ -0,0 +1,24 @@
> +* Solomon SSD1307 Framebuffer Driver
> +
> +Required properties:
> +  - compatible: Should be "solomon,ssd1307fb-<bus>". The only supported bus for
> +    now is i2c.
> +  - reg: Should contain address of the controller on the I2C bus. Most likely
> +         0x3c or 0x3d
> +  - pwm: Should contain the pwm to use according to the OF device tree PWM
> +         specification [0]
> +  - oled-reset-gpio: Should contain the GPIO used to reset the OLED display
> +
> +Optional properties:
> +  - oled-reset-active-low: Is the reset gpio is active on physical low?
> +
> +[0]: Documentation/devicetree/bindings/pwm/pwm.txt
> +
> +Examples:
> +ssd1307: oled at 3c {
> +        compatible = "solomon,ssd1307fb-i2c";
> +        reg = <0x3c>;
> +        pwms = <&pwm 4 3000>;
> +        oled-reset-gpio = <&gpio2 7 1>;
> +        oled-reset-active-low;
> +};
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 0217f74..21ae6dd 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -2469,4 +2469,18 @@ config FB_SH_MOBILE_MERAM
>  	  Up to 4 memory channels can be configured, allowing 4 RGB or
>  	  2 YCbCr framebuffers to be configured.
> 
> +

Please remove redundant line.

> +config FB_SSD1307
> +	tristate "Solomon SSD1307 framebuffer support"
> +	depends on FB && I2C
> +	select FB_SYS_FOPS
> +	select FB_SYS_FILLRECT
> +	select FB_SYS_COPYAREA
> +	select FB_SYS_IMAGEBLIT
> +	select FB_DEFERRED_IO
> +	select PWM
> +	help
> +	  This driver implements support for the Solomon SSD1307
> +	  OLED controller over I2C.
> +
>  endmenu
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index ee8dafb..6bbb72c 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -164,6 +164,7 @@ obj-$(CONFIG_FB_BFIN_7393)        += bfin_adv7393fb.o
>  obj-$(CONFIG_FB_MX3)		  += mx3fb.o
>  obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
>  obj-$(CONFIG_FB_MXS)		  += mxsfb.o
> +obj-$(CONFIG_FB_SSD1307)	  += ssd1307fb.o
> 
>  # the test framebuffer is last
>  obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
> diff --git a/drivers/video/ssd1307fb.c b/drivers/video/ssd1307fb.c
> new file mode 100644
> index 0000000..c705ab4
> --- /dev/null
> +++ b/drivers/video/ssd1307fb.c
> @@ -0,0 +1,418 @@
> +/*
> + * Driver for the Solomon SSD1307 OLED controler
> + *
> + * Copyright 2012 Free Electrons
> + *
> + * Licensed under the GPLv2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/i2c.h>
> +#include <linux/fb.h>
> +#include <linux/uaccess.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/pwm.h>
> +#include <linux/delay.h>
> +
> +#define SSD1307FB_WIDTH			96
> +#define SSD1307FB_HEIGHT		16
> +
> +#define SSD1307FB_DATA			0x40
> +#define SSD1307FB_COMMAND		0x80
> +
> +#define SSD1307FB_CONTRAST		0x81
> +#define SSD1307FB_SEG_REMAP_ON		0xa1
> +#define SSD1307FB_DISPLAY_OFF		0xae
> +#define SSD1307FB_DISPLAY_ON		0xaf
> +#define SSD1307FB_START_PAGE_ADDRESS	0xb0
> +
> +struct ssd1307fb_par {
> +	struct i2c_client *client;
> +	struct fb_info *info;
> +	struct pwm_device *pwm;
> +	u32 pwm_period;
> +	int reset;
> +};
> +
> +static struct fb_fix_screeninfo ssd1307fb_fix __devinitdata = {
> +	.id		= "Solomon SSD1307",
> +	.type		= FB_TYPE_PACKED_PIXELS,
> +	.visual		= FB_VISUAL_MONO10,
> +	.xpanstep	= 0,
> +	.ypanstep	= 0,
> +	.ywrapstep	= 0,
> +	.line_length	= SSD1307FB_WIDTH / 8,
> +	.accel		= FB_ACCEL_NONE,
> +};
> +
> +static struct fb_var_screeninfo ssd1307fb_var __devinitdata = {
> +	.xres		= SSD1307FB_WIDTH,
> +	.yres		= SSD1307FB_HEIGHT,
> +	.xres_virtual	= SSD1307FB_WIDTH,
> +	.yres_virtual	= SSD1307FB_HEIGHT,
> +	.bits_per_pixel	= 1,
> +};
> +
> +static int ssd1307fb_write_array(struct i2c_client *client, u8 type, u8* cmd, u32 len)
> +{
> +	u8 *buf;
> +	int ret = 0;
> +
> +	buf = kzalloc(len + 1, GFP_KERNEL);
> +	if (!buf) {
> +		dev_err(&client->dev, "Couldn't allocate sending buffer.\n");
> +		ret = -ENOMEM;
> +		goto out;
> +	}

How about using returning - ENOMEM without goto.
It is simpler.

	if (!buf) {
		dev_err(&client->dev, "Couldn't allocate sending buffer.\n");
		return -ENOMEM;
	}


> +
> +	buf[0] = type;
> +	memcpy(buf + 1, cmd, len);
> +
> +	ret = i2c_master_send(client, buf, len + 1);
> +	if (ret != len + 1) {
> +		dev_err(&client->dev, "Couldn't send I2C command.\n");
> +		goto error;
> +	}
> +
> +error:
> +	kfree(buf);
> +out:
> +	return ret;

Please refer to above comment.
If goto out is not used, it would be simpler.

+error:
+	kfree(buf);
+	return ret;


> +}
> +
> +static inline int ssd1307fb_write_cmd_array(struct i2c_client *client, u8* cmd, u32 len)
> +{
> +	return ssd1307fb_write_array(client, SSD1307FB_COMMAND, cmd, len);
> +}
> +
> +static inline int ssd1307fb_write_cmd(struct i2c_client *client, u8 cmd)
> +{
> +	return ssd1307fb_write_cmd_array(client, &cmd, 1);
> +}
> +
> +static inline int ssd1307fb_write_data_array(struct i2c_client *client, u8* cmd, u32 len)
> +{
> +	return ssd1307fb_write_array(client, SSD1307FB_DATA, cmd, len);
> +}
> +
> +static inline int ssd1307fb_write_data(struct i2c_client *client, u8 data)
> +{
> +	return ssd1307fb_write_data_array(client, &data, 1);
> +}
> +
> +static int ssd1307fb_set(struct i2c_client *client, u8 value)
> +{
> +	int i, j, ret;
> +
> +	for (i = 1; i <= (SSD1307FB_HEIGHT / 8); i++) {
> +		ret = ssd1307fb_write_cmd(client, SSD1307FB_START_PAGE_ADDRESS + i);
> +		if (ret < 0)
> +			goto i2c_error;
> +
> +		ret = ssd1307fb_write_cmd(client, 0x00);
> +		if (ret < 0)
> +			goto i2c_error;
> +
> +		ret = ssd1307fb_write_cmd(client, 0x10);
> +		if (ret < 0)
> +			goto i2c_error;
> +
> +		for (j = 0; j < SSD1307FB_WIDTH; j++)
> +			ssd1307fb_write_data(client, value);
> +	}
> +
> +	return 0;
> +
> +i2c_error:
> +	dev_err(&client->dev, "Couldn't send i2c command: %d\n", ret);
> +	return ret;
> +}
> +
> +static void ssd1307fb_update_display(struct ssd1307fb_par *par)
> +{
> +	u8 *vmem = par->info->screen_base;
> +	int i, j, k;
> +
> +	/*
> +	 * The screen is divided in pages, each having a height of 8
> +	 * pixels, and the width of the screen. When sending a byte of
> +	 * data to the controller, it gives the 8 bits for the current
> +	 * column. I.e, the first byte are the 8 bits of the first
> +	 * column, then the 8 bits for the second column, etc.
> +	 *
> +	 *
> +	 * Representation of the screen, assuming it is 5 bits
> +	 * wide. Each letter-number combination is a bit that controls
> +	 * one pixel.
> +	 *
> +	 * A0 A1 A2 A3 A4
> +	 * B0 B1 B2 B3 B4
> +	 * C0 C1 C2 C3 C4
> +	 * D0 D1 D2 D3 D4
> +	 * E0 E1 E2 E3 E4
> +	 * F0 F1 F2 F3 F4
> +	 * G0 G1 G2 G3 G4
> +	 * H0 H1 H2 H3 H4
> +	 *
> +	 * If you want to update this screen, you need to send 5 bytes:
> +	 *  (1) A0 B0 C0 D0 E0 F0 G0 H0
> +	 *  (2) A1 B1 C1 D1 E1 F1 G1 H1
> +	 *  (3) A2 B2 C2 D2 E2 F2 G2 H2
> +	 *  (4) A3 B3 C3 D3 E3 F3 G3 H3
> +	 *  (5) A4 B4 C4 D4 E4 F4 G4 H4
> +	 */
> +
> +	for (i = 0; i < (SSD1307FB_HEIGHT / 8); i++) {
> +		ssd1307fb_write_cmd(par->client, SSD1307FB_START_PAGE_ADDRESS + (i + 1));
> +		ssd1307fb_write_cmd(par->client, 0x00);
> +		ssd1307fb_write_cmd(par->client, 0x10);
> +
> +		for (j = 0; j < SSD1307FB_WIDTH; j++) {
> +			u8 buf = 0;
> +			for (k = 0; k < 8; k++) {
> +				u32 page_length = SSD1307FB_WIDTH * i;
> +				u32 index = page_length + (SSD1307FB_WIDTH * k + j) / 8;
> +				u8 byte = *(vmem + index);
> +				u8 bit = byte & (1 << (7 - (j % 8)));
> +				bit = bit >> (7 - (j % 8));
> +				buf |= bit << k;
> +			}
> +			ssd1307fb_write_data(par->client, buf);
> +		}
> +	}
> +
> +	return;
> +}
> +
> +

Please remove unnecessary line.

> +static ssize_t ssd1307fb_write(struct fb_info *info, const char __user *buf,
> +		size_t count, loff_t *ppos)
> +{
> +	struct ssd1307fb_par *par = info->par;
> +	unsigned long p = *ppos;
> +	void *dst;
> +	int err = 0;
> +
> +	dst = (void __force *) (info->screen_base + p);
> +
> +	if (copy_from_user(dst, buf, count))
> +		err = -EFAULT;
> +
> +	if  (!err)
> +		*ppos += count;
> +
> +	ssd1307fb_update_display(par);
> +
> +	return (err) ? err : count;
> +}
> +
> +static void ssd1307fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
> +{
> +	struct ssd1307fb_par *par = info->par;
> +	sys_fillrect(info, rect);
> +	ssd1307fb_update_display(par);
> +}
> +
> +static void ssd1307fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
> +{
> +	struct ssd1307fb_par *par = info->par;
> +	sys_copyarea(info, area);
> +	ssd1307fb_update_display(par);
> +}
> +
> +static void ssd1307fb_imageblit(struct fb_info *info, const struct fb_image *image)
> +{
> +	struct ssd1307fb_par *par = info->par;
> +	sys_imageblit(info, image);
> +	ssd1307fb_update_display(par);
> +}
> +
> +static struct fb_ops ssd1307fb_ops = {
> +	.owner		= THIS_MODULE,
> +	.fb_read	= fb_sys_read,
> +	.fb_write	= ssd1307fb_write,
> +	.fb_fillrect	= ssd1307fb_fillrect,
> +	.fb_copyarea	= ssd1307fb_copyarea,
> +	.fb_imageblit	= ssd1307fb_imageblit,
> +};
> +
> +static void ssd1307fb_deferred_io(struct fb_info *info,
> +				struct list_head *pagelist)
> +{
> +	ssd1307fb_update_display(info->par);
> +}
> +
> +static struct fb_deferred_io ssd1307fb_defio = {
> +	.delay		= HZ,
> +	.deferred_io	= ssd1307fb_deferred_io,
> +};
> +
> +static int __devinit ssd1307fb_probe(struct i2c_client *client, const struct i2c_device_id *id)
> +{
> +	struct fb_info *info;
> +	u32 vmem_size = SSD1307FB_WIDTH * SSD1307FB_HEIGHT / 8;
> +	struct ssd1307fb_par *par;
> +	u8 *vmem;
> +	int ret;
> +
> +	if (!client->dev.of_node) {
> +		dev_err(&client->dev, "No device tree data found!\n");
> +		ret = -EINVAL;
> +		goto generic_error;
> +	}

How about using returning -EINVAL without goto.
It is simpler.

	if (!client->dev.of_node) {
		dev_err(&client->dev, "No device tree data found!\n");
		return -EINVAL;
	}


> +
> +	info = framebuffer_alloc(sizeof(struct ssd1307fb_par), &client->dev);
> +	if (!info) {
> +		ret = -ENOMEM;
> +		goto generic_error;
> +	}


Ditto.


> +
> +	vmem = devm_kzalloc(&client->dev, vmem_size, GFP_KERNEL);
> +	if (!vmem) {
> +		dev_err(&client->dev, "Couldn't allocate graphical memory.\n");
> +		ret = -ENOMEM;
> +		goto generic_error;
> +	}

Please fix this 'goto generic_error'. goto generic_error cannot call
framebuffer_release(). If framebuffer_alloc() is already called,
framebuffer_release() should be called when error happens.


> +
> +	info->fbops = &ssd1307fb_ops;
> +	info->fix = ssd1307fb_fix;
> +	info->fbdefio = &ssd1307fb_defio;
> +
> +	info->var = ssd1307fb_var;
> +	info->var.red.length = 1;
> +	info->var.red.offset = 0;
> +	info->var.green.length = 1;
> +	info->var.green.offset = 0;
> +	info->var.blue.length = 1;
> +	info->var.blue.offset = 0;
> +
> +	info->screen_base = (u8 __force __iomem *)vmem;
> +	info->fix.smem_start = (unsigned long)vmem;
> +	info->fix.smem_len = vmem_size;
> +
> +	fb_deferred_io_init(info);
> +
> +	par = info->par;
> +	par->info = info;
> +	par->client = client;
> +
> +	par->reset = of_get_named_gpio(client->dev.of_node,
> +					 "oled-reset-gpio", 0);
> +	if (gpio_is_valid(par->reset)) {
> +		int flags = GPIOF_OUT_INIT_HIGH;
> +		if (of_get_property(client->dev.of_node,
> +				    "oled-reset-active-low", NULL))
> +			flags = GPIOF_OUT_INIT_LOW;
> +		ret = devm_gpio_request_one(&client->dev, par->reset,
> +					    flags, "oled-reset");
> +		if (ret) {
> +			dev_err(&client->dev,
> +				"failed to request gpio %d: %d\n",
> +				par->reset, ret);
> +			goto reset_oled_error;
> +		}
> +	}
> +
> +	par->pwm = pwm_get(&client->dev, NULL);
> +	if (IS_ERR(par->pwm)) {
> +		dev_err(&client->dev, "Could not get PWM from device tree!\n");
> +		ret = PTR_ERR(par->pwm);
> +		goto pwm_error;
> +	}
> +
> +	par->pwm_period = pwm_get_period(par->pwm);
> +
> +	dev_dbg(&client->dev, "Using PWM%d with a %dns period.\n", par->pwm->pwm, par->pwm_period);
> +
> +	ret = register_framebuffer(info);
> +	if (ret) {
> +		dev_err(&client->dev, "Couldn't register the framebuffer\n");
> +		goto fbreg_error;
> +	}
> +
> +	i2c_set_clientdata(client, info);
> +
> +	/* Reset the screen */
> +	gpio_set_value(par->reset, 1);
> +	udelay(4);
> +	gpio_set_value(par->reset, 0);
> +	udelay(4);
> +
> +	/* Enable the PWM */
> +	pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period);
> +	pwm_enable(par->pwm);
> +
> +	/* Map column 127 of the OLED to segment 0 */
> +	ret = ssd1307fb_write_cmd(client, SSD1307FB_SEG_REMAP_ON);
> +	if (ret < 0) {
> +		dev_err(&client->dev, "Couldn't remap the screen.\n");
> +		goto remap_error;
> +	}
> +
> +	/* Turn on the display */
> +	ret = ssd1307fb_write_cmd(client, SSD1307FB_DISPLAY_ON);
> +	if (ret < 0) {
> +		dev_err(&client->dev, "Couldn't turn the display on.\n");
> +		goto remap_error;
> +	}
> +
> +	dev_info(&client->dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n",
> info->node, info->fix.id, vmem_size);
> +
> +	return 0;
> +
> +remap_error:
> +	unregister_framebuffer(info);
> +	pwm_disable(par->pwm);
> +fbreg_error:
> +	pwm_put(par->pwm);
> +pwm_error:
> +reset_oled_error:
> +	fb_deferred_io_cleanup(info);
> +	framebuffer_release(info);
> +generic_error:
> +	return ret;
> +}
> +
> +static int __devexit ssd1307fb_remove(struct i2c_client *client)
> +{
> +	struct fb_info *info = i2c_get_clientdata(client);
> +	struct ssd1307fb_par *par = info->par;


How about insert new line between variables and functions
to enhance the readability?


> +	unregister_framebuffer(info);
> +	pwm_disable(par->pwm);
> +	pwm_put(par->pwm);
> +	fb_deferred_io_cleanup(info);
> +	framebuffer_release(info);
> +
> +	return 0;
> +}
> +
> +static const struct i2c_device_id ssd1307fb_i2c_id[] = {
> +	{ "ssd1307fb", 0 },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(i2c, ssd1307fb_i2c_id);
> +
> +static const struct of_device_id ssd1307fb_of_match[] = {
> +	{ .compatible = "solomon,ssd1307fb-i2c" },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, ssd1307fb_of_match);
> +
> +static struct i2c_driver ssd1307fb_driver = {
> +	.probe = ssd1307fb_probe,
> +	.remove = __devexit_p(ssd1307fb_remove),
> +	.id_table = ssd1307fb_i2c_id,
> +	.driver = {
> +		.name = "ssd1307fb",
> +		.of_match_table = of_match_ptr(ssd1307fb_of_match),
> +		.owner = THIS_MODULE,
> +	},
> +};
> +
> +module_i2c_driver(ssd1307fb_driver);
> +
> +MODULE_DESCRIPTION("FB driver for the Solomon SSD1307 OLED controler");
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
> +MODULE_LICENSE("GPL");
> --
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From omaplinuxkernel at gmail.com  Wed Aug  1 01:46:15 2012
From: omaplinuxkernel at gmail.com (Shubhrajyoti Datta)
Date: Wed, 1 Aug 2012 11:16:15 +0530
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801052947.GA2400@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
Message-ID: <CAM=Q2csm1m8DCd8__NAUCmk6AN=Czg_=nm4c3ervAgOhOtoMTw@mail.gmail.com>

On Wed, Aug 1, 2012 at 10:59 AM, Guenter Roeck <linux at roeck-us.net> wrote:
> On Wed, Aug 01, 2012 at 07:00:54AM +0200, Marek Vasut wrote:
>> Dear Shawn Guo,
>>
>> > On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
>> > > I think the call to spi_master_put() triggers the call to
>> > > spi_master_release(). If so, kfree() would not be needed at all, and the
>> > > documentation is wrong.
>> >
>> > Also those drivers calling kfree in probe.
>>
>> Looks like that to me ...
>>
> Doesn't seem to be far spread, fortunately. Only spi-davinci.c, spi-imx.c, and
> spi-omap2-mcspi.c

I have a  omapsdp I could patch spi-omap2-mcspi.c  file thanks for the catch.

>as far as I can see, plus the misleading comment in spi.c.
>
> Anyone up for writing some patches ? If not, I'll do it.
>
> Thanks,
> Guenter
>
> ------------------------------------------------------------------------------
> Live Security Virtual Conference
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> threat landscape has changed and how IT managers can respond. Discussions
> will include endpoint security, mobile security and the latest in malware
> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
> _______________________________________________
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> spi-devel-general at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/spi-devel-general


From shawn.guo at linaro.org  Wed Aug  1 02:28:40 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 14:28:40 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801054228.GA2645@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
 <20120801055854.GE1672@S2100-06.ap.freescale.net>
 <20120801054228.GA2645@roeck-us.net>
Message-ID: <20120801062838.GF1672@S2100-06.ap.freescale.net>

On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > Anyone up for writing some patches ? If not, I'll do it.
> > > 
> > Go ahead.
> > 
> Ok, will do. It isn't that simple, actually, since at least some of the drivers
> also call spi_master_get(), and thus need two calls to spi_master_put() (or a
> call to spi_master_put and a call to kfree).
> 
Hmm, are you saying that there must be a spi_master_put call matching
spi_alloc_master?  I think we only need to have spi_master_get and
spi_master_put matched.

Regards,
Shawn



From marex at denx.de  Wed Aug  1 02:10:37 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 1 Aug 2012 08:10:37 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801062838.GF1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801054228.GA2645@roeck-us.net>
 <20120801062838.GF1672@S2100-06.ap.freescale.net>
Message-ID: <201208010810.37652.marex@denx.de>

Dear Shawn Guo,

> On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > Anyone up for writing some patches ? If not, I'll do it.
> > > 
> > > Go ahead.
> > 
> > Ok, will do. It isn't that simple, actually, since at least some of the
> > drivers also call spi_master_get(), and thus need two calls to
> > spi_master_put() (or a call to spi_master_put and a call to kfree).
> 
> Hmm, are you saying that there must be a spi_master_put call matching
> spi_alloc_master?  I think we only need to have spi_master_get and
> spi_master_put matched.

Naw, spi_master_get() does refcounting, spi_alloc_master() doesnt. You don't 
need to match spi_alloc_master() with spi_master_put()

> Regards,
> Shawn

Best regards,
Marek Vasut


From marex at denx.de  Wed Aug  1 02:29:19 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 1 Aug 2012 08:29:19 +0200
Subject: [PATCH 08/10 V2] spi: Add DMA support into SPI driver
In-Reply-To: <1341555449-17507-8-git-send-email-marex@denx.de>
References: <1341555449-17507-1-git-send-email-marex@denx.de>
 <1341555449-17507-8-git-send-email-marex@denx.de>
Message-ID: <201208010829.19404.marex@denx.de>

Dear Marek Vasut,

[...]

> -out_host_free:
> +out_free_dma:
> +	dma_release_channel(ssp->dmach);
>  	clk_disable_unprepare(ssp->clk);
> +out_host_free:
>  	spi_master_put(host);
>  	kfree(host);
> +

Please remove this newline.

>  	return ret;
>  }

Missing dma_release_channel() in .remove!

Best regards,
Marek Vasut


From linux at roeck-us.net  Wed Aug  1 02:33:26 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 23:33:26 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801062838.GF1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
 <20120801055854.GE1672@S2100-06.ap.freescale.net>
 <20120801054228.GA2645@roeck-us.net>
 <20120801062838.GF1672@S2100-06.ap.freescale.net>
Message-ID: <20120801063326.GA2764@roeck-us.net>

On Wed, Aug 01, 2012 at 02:28:40PM +0800, Shawn Guo wrote:
> On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > Anyone up for writing some patches ? If not, I'll do it.
> > > > 
> > > Go ahead.
> > > 
> > Ok, will do. It isn't that simple, actually, since at least some of the drivers
> > also call spi_master_get(), and thus need two calls to spi_master_put() (or a
> > call to spi_master_put and a call to kfree).
> > 
> Hmm, are you saying that there must be a spi_master_put call matching
> spi_alloc_master?  I think we only need to have spi_master_get and
> spi_master_put matched.
> 
Yes, I think that may be so. Of course, I may be wrong, but ultimately that is
what almost all drivers do in the probe error path. Some of the drivers do it in
the remove path as well, though many don't. I suspect that all drivers using
spi_alloc_master() which do not call spi_master_put() in the remove function may
have a memory leak.

Someone who knows the spi infrastructure better than I should have a closer
look, though. The question is really quite simple: For example, in spi-atmel.c,
how is the allocated master freed in the _remove function ? If it doesn't need
the call to spi_master_put(), why do, for example, spi-stmp.c or spi-mpc52xx.c
call it ?

On the other side, I must admit I am getting more and more confused after
looking into the code. For example, the probe function error path in spi-mpc52xx.c
accesses the master's devdata after the call to spi_master_put(). If
spi_master_put() frees the memory as we think it does, the code would access
freed memory. The same happens in the remove path. And spi_master_put() is not
always called, meaning there is either a memory leak or I am completely confused.

Thanks,
Guenter


From thierry.reding at avionic-design.de  Wed Aug  1 02:35:45 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 1 Aug 2012 08:35:45 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <50180547.9040603@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50180547.9040603@wwwdotorg.org>
Message-ID: <20120801063545.GA26791@avionic-0098.adnet.avionic-design.de>

On Tue, Jul 31, 2012 at 10:18:15AM -0600, Stephen Warren wrote:
> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> > This patch series adds support for device tree based probing of the PCIe
> > controller found on Tegra SoCs.
> 
> Thierry,
> 
> I think one thing that would help here would be to split up this series
> into one per subsystem, and to get all the dependencies merged by the
> respective maintainers. Preferably, each subsystem would export a stable
> branch (perhaps consisting of just these patches) that I can then merge
> into the Tegra tree and use as a basis for the PCIe driver itself.
> Hopefully this approach will get more traction on all the non-Tegra
> changes. Does that sound like a good plan?

I don't understand. The series is already split up into per-subsystem
patches. I just didn't want to post them separately so everybody on Cc
would be able to see the big picture and the reason why the patch was
required.

> Or, I can just take it all through the Tegra tree, but I'll definitely
> need acks on all/most of the non-Tegra patches, since although the
> patches themselves are quite small, I'd like to be sure that maintainers
> are OK with the conceptual changes, like initializing PCI controllers
> later than at present etc.

Taking the patches through the individual trees should be fine. Only so
far other subsystem maintainers haven't commented on this.

As to when the PCI controller is initialized, there really aren't many
options. On Harmony (and TEC, which in this respect, and others, is very
similar) the VDD is supplied by a GPIO of the PMU, so it is currently
necessary to probe it at least after the PMU. And unless we want to
work around these issues using different initcall ordering we need to
rely on deferred probing, which turns out to be done after the init
phase often (always?).

Also I had been toying with making the Tegra PCIe driver work as a
module, but that doesn't work currently with MSI support. However it
might be nice to allow MSI controllers to register at runtime generally,
which wouldn't be all that difficult to do I think. Of course somebody
more knowledgeable may disagree.

Thierry
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From s.hauer at pengutronix.de  Wed Aug  1 02:34:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 1 Aug 2012 08:34:37 +0200
Subject: [PATCH v4 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <1343789469-26821-2-git-send-email-richard.zhao@freescale.com>
References: <1343789469-26821-1-git-send-email-richard.zhao@freescale.com>
 <1343789469-26821-2-git-send-email-richard.zhao@freescale.com>
Message-ID: <20120801063437.GF30009@pengutronix.de>

On Wed, Aug 01, 2012 at 10:51:07AM +0800, Richard Zhao wrote:
> i.MX usb controllers shares non-core registers, which may include
> SoC specific controls. We take it as a usbmisc device and usbmisc
> driver set operations needed by ci13xxx_imx driver.
> 
> For example, Sabrelite board has bad over-current design, we can
> usbmisc to disable over-current detect.
> 
> Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> ---
>  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
>  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
>  drivers/usb/chipidea/Makefile                      |    2 +-
>  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
>  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
>  5 files changed, 246 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
>  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> index 2c29041..5778b9c 100644
> --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> @@ -7,7 +7,10 @@ Required properties:
>  
>  Optional properties:
>  - fsl,usbphy: phandler of usb phy that connects to the only one port
> +- fsl,usbmisc: phandler of non-core register device, with one argument
> +  that indicate usb controller index
>  - vbus-supply: regulator for vbus
> +- disable-over-current: disable over current detect
>  
>  Examples:
>  usb at 02184000 { /* USB OTG */
> @@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
>  	reg = <0x02184000 0x200>;
>  	interrupts = <0 43 0x04>;
>  	fsl,usbphy = <&usbphy1>;
> +	fsl,usbmisc = <&usbmisc 0>;
> +	disable-over-current;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> new file mode 100644
> index 0000000..97ce94e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> @@ -0,0 +1,14 @@
> +* Freescale i.MX non-core registers
> +
> +Required properties:
> +- #index-cells: Cells used to descibe usb controller index. Should be <1>
> +- compatible: Should be one of below:
> +	"fsl,imx6q-usbmisc" for imx6q
> +- reg: Should contain registers location and length
> +
> +Examples:
> +usbmisc at 02184800 {
> +	#index-cells = <1>;
> +	compatible = "fsl,imx6q-usbmisc";
> +	reg = <0x02184800 0x200>;
> +};
> diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
> index 5c66d9c..57e510f 100644
> --- a/drivers/usb/chipidea/Makefile
> +++ b/drivers/usb/chipidea/Makefile
> @@ -15,5 +15,5 @@ ifneq ($(CONFIG_PCI),)
>  endif
>  
>  ifneq ($(CONFIG_OF_DEVICE),)
> -	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o
> +	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o usbmisc_imx6q.o
>  endif
> diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
> index ef60d06..05cd0ae 100644
> --- a/drivers/usb/chipidea/ci13xxx_imx.c
> +++ b/drivers/usb/chipidea/ci13xxx_imx.c
> @@ -22,6 +22,7 @@
>  #include <linux/regulator/consumer.h>
>  
>  #include "ci.h"
> +#include "ci13xxx_imx.h"
>  
>  #define pdev_to_phy(pdev) \
>  	((struct usb_phy *)platform_get_drvdata(pdev))
> @@ -34,6 +35,55 @@ struct ci13xxx_imx_data {
>  	struct regulator *reg_vbus;
>  };
>  
> +static const struct usbmisc_ops *usbmisc_ops;
> +
> +/* Common functions shared by usbmisc drivers */
> +
> +int usbmisc_set_ops(const struct usbmisc_ops *ops)
> +{
> +	if (usbmisc_ops)
> +		return -EBUSY;
> +
> +	usbmisc_ops = ops;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_set_ops);
> +
> +void usbmisc_unset_ops(const struct usbmisc_ops *ops)
> +{
> +	usbmisc_ops = NULL;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
> +
> +int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct of_phandle_args args;
> +	int ret;
> +
> +	usbdev->dev = dev;
> +
> +	ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
> +					0, &args);
> +	if (ret) {
> +		dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
> +			ret);
> +		memset(usbdev, 0, sizeof(*usbdev));
> +		return ret;
> +	}
> +	usbdev->index = args.args[0];
> +	of_node_put(args.np);
> +
> +	if (of_find_property(np, "disable-over-current", NULL))
> +		usbdev->disable_oc = 1;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
> +
> +/* End of common functions shared by usbmisc drivers*/
> +
>  static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
>  	.name			= "ci13xxx_imx",
>  	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
> @@ -51,6 +101,10 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
>  	struct regulator *reg_vbus;
>  	int ret;
>  
> +	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
> +		&& !usbmisc_ops)
> +		return -EPROBE_DEFER;
> +
>  	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
>  	if (!data) {
>  		dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
> @@ -120,6 +174,16 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
>  		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
>  		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
>  	}
> +
> +	if (usbmisc_ops && usbmisc_ops->init) {
> +		ret = usbmisc_ops->init(&pdev->dev);
> +		if (ret) {
> +			dev_err(&pdev->dev,
> +				"usbmisc init failed, ret=%d\n", ret);
> +			return ret;
> +		}
> +	}
> +
>  	plat_ci = ci13xxx_add_device(&pdev->dev,
>  				pdev->resource, pdev->num_resources,
>  				&ci13xxx_imx_platdata);
> diff --git a/drivers/usb/chipidea/usbmisc_imx6q.c b/drivers/usb/chipidea/usbmisc_imx6q.c
> new file mode 100644
> index 0000000..416e3fc
> --- /dev/null
> +++ b/drivers/usb/chipidea/usbmisc_imx6q.c
> @@ -0,0 +1,162 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +
> +#include "ci13xxx_imx.h"
> +
> +#define USB_DEV_MAX 4
> +
> +#define BM_OVER_CUR_DIS		BIT(7)
> +
> +struct imx6q_usbmisc {
> +	void __iomem *base;
> +	spinlock_t lock;
> +	struct clk *clk;
> +	struct usbmisc_usb_device usbdev[USB_DEV_MAX];

Could it be that something is missing in this patch? I don't see struct
usbmisc_usb_device defined anywhere in this patch.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at roeck-us.net  Wed Aug  1 02:36:39 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 23:36:39 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <CAM=Q2csm1m8DCd8__NAUCmk6AN=Czg_=nm4c3ervAgOhOtoMTw@mail.gmail.com>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801033559.GB2323@roeck-us.net>
 <20120801045010.GC1672@S2100-06.ap.freescale.net>
 <201208010700.54829.marex@denx.de>
 <20120801052947.GA2400@roeck-us.net>
 <CAM=Q2csm1m8DCd8__NAUCmk6AN=Czg_=nm4c3ervAgOhOtoMTw@mail.gmail.com>
Message-ID: <20120801063639.GB2764@roeck-us.net>

On Wed, Aug 01, 2012 at 11:16:15AM +0530, Shubhrajyoti Datta wrote:
> On Wed, Aug 1, 2012 at 10:59 AM, Guenter Roeck <linux at roeck-us.net> wrote:
> > On Wed, Aug 01, 2012 at 07:00:54AM +0200, Marek Vasut wrote:
> >> Dear Shawn Guo,
> >>
> >> > On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
> >> > > I think the call to spi_master_put() triggers the call to
> >> > > spi_master_release(). If so, kfree() would not be needed at all, and the
> >> > > documentation is wrong.
> >> >
> >> > Also those drivers calling kfree in probe.
> >>
> >> Looks like that to me ...
> >>
> > Doesn't seem to be far spread, fortunately. Only spi-davinci.c, spi-imx.c, and
> > spi-omap2-mcspi.c
> 
> I have a  omapsdp I could patch spi-omap2-mcspi.c  file thanks for the catch.
>
For that it would be good to determine if there is a memory leak when removing
the driver (I don't see where the memory allocated with spi_alloc_master is
removed).

Thanks,
Guenter


From linux at roeck-us.net  Wed Aug  1 02:39:36 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 23:39:36 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208010810.37652.marex@denx.de>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801054228.GA2645@roeck-us.net>
 <20120801062838.GF1672@S2100-06.ap.freescale.net>
 <201208010810.37652.marex@denx.de>
Message-ID: <20120801063936.GC2764@roeck-us.net>

On Wed, Aug 01, 2012 at 08:10:37AM +0200, Marek Vasut wrote:
> Dear Shawn Guo,
> 
> > On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > > Anyone up for writing some patches ? If not, I'll do it.
> > > > 
> > > > Go ahead.
> > > 
> > > Ok, will do. It isn't that simple, actually, since at least some of the
> > > drivers also call spi_master_get(), and thus need two calls to
> > > spi_master_put() (or a call to spi_master_put and a call to kfree).
> > 
> > Hmm, are you saying that there must be a spi_master_put call matching
> > spi_alloc_master?  I think we only need to have spi_master_get and
> > spi_master_put matched.
> 
> Naw, spi_master_get() does refcounting, spi_alloc_master() doesnt. You don't 
> need to match spi_alloc_master() with spi_master_put()
> 
I must be missing something.  Why do almost all spi drivers call it in the error
path, even if there is no call to spi_master_get ?

Thanks,
Guenter


From marex at denx.de  Wed Aug  1 02:40:47 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 1 Aug 2012 08:40:47 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801063326.GA2764@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <20120801062838.GF1672@S2100-06.ap.freescale.net>
 <20120801063326.GA2764@roeck-us.net>
Message-ID: <201208010840.48145.marex@denx.de>

Dear Guenter Roeck,

> On Wed, Aug 01, 2012 at 02:28:40PM +0800, Shawn Guo wrote:
> > On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > > Anyone up for writing some patches ? If not, I'll do it.
> > > > 
> > > > Go ahead.
> > > 
> > > Ok, will do. It isn't that simple, actually, since at least some of the
> > > drivers also call spi_master_get(), and thus need two calls to
> > > spi_master_put() (or a call to spi_master_put and a call to kfree).
> > 
> > Hmm, are you saying that there must be a spi_master_put call matching
> > spi_alloc_master?  I think we only need to have spi_master_get and
> > spi_master_put matched.
> 
> Yes, I think that may be so. Of course, I may be wrong, but ultimately that
> is what almost all drivers do in the probe error path. Some of the drivers
> do it in the remove path as well, though many don't. I suspect that all
> drivers using spi_alloc_master() which do not call spi_master_put() in the
> remove function may have a memory leak.

CCing Mark.

> Someone who knows the spi infrastructure better than I should have a closer
> look, though. The question is really quite simple: For example, in
> spi-atmel.c, how is the allocated master freed in the _remove function ?
> If it doesn't need the call to spi_master_put(), why do, for example,
> spi-stmp.c or spi-mpc52xx.c call it ?
> 
> On the other side, I must admit I am getting more and more confused after
> looking into the code. For example, the probe function error path in
> spi-mpc52xx.c accesses the master's devdata after the call to
> spi_master_put(). If spi_master_put() frees the memory as we think it
> does, the code would access freed memory. The same happens in the remove
> path. And spi_master_put() is not always called, meaning there is either a
> memory leak or I am completely confused.

I'll poke through the stuff later if you won't get your answers (later == around 
tomorrow)

> Thanks,
> Guenter

Best regards,
Marek Vasut


From marek.vasut at gmail.com  Wed Aug  1 02:41:34 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 1 Aug 2012 08:41:34 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801063639.GB2764@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <CAM=Q2csm1m8DCd8__NAUCmk6AN=Czg_=nm4c3ervAgOhOtoMTw@mail.gmail.com>
 <20120801063639.GB2764@roeck-us.net>
Message-ID: <201208010841.34805.marex@denx.de>

Dear Guenter Roeck,

> On Wed, Aug 01, 2012 at 11:16:15AM +0530, Shubhrajyoti Datta wrote:
> > On Wed, Aug 1, 2012 at 10:59 AM, Guenter Roeck <linux at roeck-us.net> wrote:
> > > On Wed, Aug 01, 2012 at 07:00:54AM +0200, Marek Vasut wrote:
> > >> Dear Shawn Guo,
> > >> 
> > >> > On Tue, Jul 31, 2012 at 08:35:59PM -0700, Guenter Roeck wrote:
> > >> > > I think the call to spi_master_put() triggers the call to
> > >> > > spi_master_release(). If so, kfree() would not be needed at all,
> > >> > > and the documentation is wrong.
> > >> > 
> > >> > Also those drivers calling kfree in probe.
> > >> 
> > >> Looks like that to me ...
> > > 
> > > Doesn't seem to be far spread, fortunately. Only spi-davinci.c,
> > > spi-imx.c, and spi-omap2-mcspi.c
> > 
> > I have a  omapsdp I could patch spi-omap2-mcspi.c  file thanks for the
> > catch.
> 
> For that it would be good to determine if there is a memory leak when
> removing the driver (I don't see where the memory allocated with
> spi_alloc_master is removed).

When the refcounting for the device reaches 0, it's deallocated. (Aka _put long 
enough and it'll disappear)

> Thanks,
> Guenter

Best regards,
Marek Vasut


From richard.zhao at freescale.com  Wed Aug  1 02:42:31 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 1 Aug 2012 14:42:31 +0800
Subject: [PATCH v4 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <20120801063437.GF30009@pengutronix.de>
References: <1343789469-26821-1-git-send-email-richard.zhao@freescale.com>
 <1343789469-26821-2-git-send-email-richard.zhao@freescale.com>
 <20120801063437.GF30009@pengutronix.de>
Message-ID: <20120801064230.GA29944@b20223-02.ap.freescale.net>

> Could it be that something is missing in this patch? I don't see struct
> usbmisc_usb_device defined anywhere in this patch.
ah, Sorry I missed the header file. I'll send a new version.

Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From marek.vasut at gmail.com  Wed Aug  1 02:45:19 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 1 Aug 2012 08:45:19 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801063936.GC2764@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de> <20120801063936.GC2764@roeck-us.net>
Message-ID: <201208010845.19361.marex@denx.de>

Dear Guenter Roeck,

> On Wed, Aug 01, 2012 at 08:10:37AM +0200, Marek Vasut wrote:
> > Dear Shawn Guo,
> > 
> > > On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > > > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > > > Anyone up for writing some patches ? If not, I'll do it.
> > > > > 
> > > > > Go ahead.
> > > > 
> > > > Ok, will do. It isn't that simple, actually, since at least some of
> > > > the drivers also call spi_master_get(), and thus need two calls to
> > > > spi_master_put() (or a call to spi_master_put and a call to kfree).
> > > 
> > > Hmm, are you saying that there must be a spi_master_put call matching
> > > spi_alloc_master?  I think we only need to have spi_master_get and
> > > spi_master_put matched.
> > 
> > Naw, spi_master_get() does refcounting, spi_alloc_master() doesnt. You
> > don't need to match spi_alloc_master() with spi_master_put()
> 
> I must be missing something.  Why do almost all spi drivers call it in the
> error path, even if there is no call to spi_master_get ?

To push the refcounting to 0, to deallocate the device, I'd say ...

Best regards,
Marek Vasut


From karl.beldan at gmail.com  Wed Aug  1 02:50:24 2012
From: karl.beldan at gmail.com (Karl Beldan)
Date: Wed, 1 Aug 2012 08:50:24 +0200
Subject: About dma_sync_single_for_{cpu,device}
In-Reply-To: <20120731200855.GC10335@n2100.arm.linux.org.uk>
References: <20120730202401.GA4947@gobelin> <20120731064557.GA4676@gobelin>
 <20120731090931.GP6802@n2100.arm.linux.org.uk>
 <CACYmx9MnEn_XOosBn2-YJ=ny9FiLPADMNa6okwG08xrSpCUSpA@mail.gmail.com>
 <20120731200855.GC10335@n2100.arm.linux.org.uk>
Message-ID: <CACYmx9OBhp+8XF3AxVeW2cnVKkTtRsMwf5U-oiFxnJV2Vbzoug@mail.gmail.com>

On 7/31/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Tue, Jul 31, 2012 at 09:31:13PM +0200, Karl Beldan wrote:
>> On 7/31/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
>> > On Tue, Jul 31, 2012 at 08:45:57AM +0200, Karl Beldan wrote:
>> >> I was expecting the following to work:
>> >> 	addr = dma_map_single(dev, buffer, size, DMA_TO_DEVICE);
>> >> 	dma_sync_single_for_device(dev, buffer, pattern_size,
>> >> DMA_FROM_DEVICE);
>> >> 	dev_send(buffer);
>> >> 	// wait for irq (don't peek in the buffer) ... got irq
>> >> 	dma_sync_single_for_cpu(dev, buffer, pattern_size, DMA_FROM_DEVICE);
>> >> 	if (!xfer_done(buffer)) // not RAM value
>> >> 		dma_sync_single_for_device(dev, buffer, pattern_size,
>> >> DMA_FROM_DEVICE);
>> >> 	[...]
>> >
>>
>> Hi Russell,
>>
>>
>> > First point is that you clearly do not understand the DMA API at all.
>> > The
>> > DMA API has the idea of buffer ownership.  Only the owner may access
>> > the
>> > buffer:
>> >
>> Are you saying that this scenario does not work ?
>> We are taking some liberties with the DMA API, we're more using some
>> of its funcs rather than _using_ it ;).
>> The question was not whether this was a proper usage of the API, but
>> why that scenario would not lead to the expected results .. and now
>> I've found the culprit peek I am happy.
>
> If you abuse the API don't expect your stuff to work in future kernel
> versions.
>
Of course.

> It seems that the overall tone of your reply is "what we have now works,
> we don't care if it's correct, sod you."
>
Not at all : {
On 7/31/12, Karl Beldan <karl.beldan at gmail.com> wrote:
> I might use something different in a not so distant future, yet, for
> the time being, this way of doing as its advantages.
} and during this time I might stick to the API.
I am not at ease telling people how they should take things,
especially if I asked for their help, all the more when they put
efforts within the exchange while being expert on the matter, yet
please, do not assume I did not care for your advices, which I deem of
the most valuable, as, needless to say, do the community.

> Fine, I won't spend any more time on this.  Just don't ever think about
> merging it into mainline, thanks.
>
Merge submission while taking such liberties .. that I would not dare
;) this really was a down to the ground technical question not the
start of a disguised start of a merging request.

I am sure that taking such liberties and feeling its limits before
sticking to a super safe API is not a bad thing, e.g it might trigger
easierly nasty hidden bugs, it is often beneficial to me at least.

Thanks for your feedback,

Karl


From thierry.reding at avionic-design.de  Wed Aug  1 02:54:37 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 1 Aug 2012 08:54:37 +0200
Subject: [PATCH v3 09/10] of: Add of_pci_parse_ranges()
In-Reply-To: <50183B03.2090809@gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-10-git-send-email-thierry.reding@avionic-design.de>
 <50183B03.2090809@gmail.com>
Message-ID: <20120801065437.GB26791@avionic-0098.adnet.avionic-design.de>

On Tue, Jul 31, 2012 at 03:07:31PM -0500, Rob Herring wrote:
> On 07/26/2012 02:55 PM, Thierry Reding wrote:
> > This new function parses the ranges property of PCI device nodes into
> > an array of struct resource elements. It is useful in multiple-port PCI
> > host controller drivers to collect information about the ranges that it
> > needs to forward to the respective ports.
> 
> It seems to me that some of the DT PCI code in arch/powerpc/kernel/pci*
> like pci_process_bridge_OF_ranges() should apply for ARM as well.
> 
> Each arch defining their own pci controller structs complicates this,
> but I would think at least the DT parsing can be common.

Yes, there's quite a lot of room for refactoring. When I first started
work on this there had been some discussion about whether it would make
sense to move PCI controller drivers into a common location to make it
easier to refactor but the consensus at the time was that this should
not be done.

I still think this might be worthwhile, but I have other things that I
need to finish first.

> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v3:
> > - new patch
> > 
> >  drivers/of/of_pci.c    | 84 +++++++++++++++++++++++++++++++++++++++++++++++++-
> >  include/linux/of_pci.h |  2 ++
> >  2 files changed, 85 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
> > index 13e37e2..bcff301 100644
> > --- a/drivers/of/of_pci.c
> > +++ b/drivers/of/of_pci.c
> > @@ -1,7 +1,8 @@
> >  #include <linux/kernel.h>
> >  #include <linux/export.h>
> > -#include <linux/of.h>
> > +#include <linux/of_address.h>
> >  #include <linux/of_pci.h>
> > +#include <linux/slab.h>
> >  #include <asm/prom.h>
> >  
> >  static inline int __of_pci_pci_compare(struct device_node *node,
> > @@ -40,3 +41,84 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
> >  	return NULL;
> >  }
> >  EXPORT_SYMBOL_GPL(of_pci_find_child_device);
> > +
> > +struct resource *of_pci_parse_ranges(struct device_node *node,
> > +				     unsigned int *countp)
> > +{
> > +	unsigned int count, i = 0;
> > +	struct resource *ranges;
> 
> I think res or pci_res would be clearer than ranges that this is a
> struct resource.

"range" is the term used by the PCI specifications to denote these
regions. I don't see what's wrong with using it as a variable name.

Thierry
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From linux at roeck-us.net  Wed Aug  1 02:56:50 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 31 Jul 2012 23:56:50 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208010845.19361.marex@denx.de>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
Message-ID: <20120801065650.GA2928@roeck-us.net>

On Wed, Aug 01, 2012 at 08:45:19AM +0200, Marek Vasut wrote:
> Dear Guenter Roeck,
> 
> > On Wed, Aug 01, 2012 at 08:10:37AM +0200, Marek Vasut wrote:
> > > Dear Shawn Guo,
> > > 
> > > > On Tue, Jul 31, 2012 at 10:42:28PM -0700, Guenter Roeck wrote:
> > > > > On Wed, Aug 01, 2012 at 01:58:56PM +0800, Shawn Guo wrote:
> > > > > > On Tue, Jul 31, 2012 at 10:29:47PM -0700, Guenter Roeck wrote:
> > > > > > > Anyone up for writing some patches ? If not, I'll do it.
> > > > > > 
> > > > > > Go ahead.
> > > > > 
> > > > > Ok, will do. It isn't that simple, actually, since at least some of
> > > > > the drivers also call spi_master_get(), and thus need two calls to
> > > > > spi_master_put() (or a call to spi_master_put and a call to kfree).
> > > > 
> > > > Hmm, are you saying that there must be a spi_master_put call matching
> > > > spi_alloc_master?  I think we only need to have spi_master_get and
> > > > spi_master_put matched.
> > > 
> > > Naw, spi_master_get() does refcounting, spi_alloc_master() doesnt. You
> > > don't need to match spi_alloc_master() with spi_master_put()
> > 
> > I must be missing something.  Why do almost all spi drivers call it in the
> > error path, even if there is no call to spi_master_get ?
> 
> To push the refcounting to 0, to deallocate the device, I'd say ...
> 

Guess we are in violent agreement. The sequence would then either be
	master = spi_alloc_device();
	...
	spi_master_put(master);
or
	master = spi_alloc_device();
	...
	kfree(master);

which makes sense to me. Question still is why most drivers neither call kfree()
nor spi_master_put() in the remove function.

Thanks,
Guenter


From g.liakhovetski at gmx.de  Wed Aug  1 03:02:52 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 1 Aug 2012 09:02:52 +0200 (CEST)
Subject: [PATCH 4/4] media: mx2_camera: Fix clock handling for i.MX27.
In-Reply-To: <20120731174901.GD30009@pengutronix.de>
References: <1343301637-19676-1-git-send-email-javier.martin@vista-silicon.com>
 <1343301637-19676-5-git-send-email-javier.martin@vista-silicon.com>
 <Pine.LNX.4.64.1207311644590.27888@axis700.grange>
 <20120731174901.GD30009@pengutronix.de>
Message-ID: <Pine.LNX.4.64.1208010850110.5406@axis700.grange>

Hi Sascha

On Tue, 31 Jul 2012, Sascha Hauer wrote:

> Hi Guennadi,
> 
> On Tue, Jul 31, 2012 at 05:14:25PM +0200, Guennadi Liakhovetski wrote:
> > Hi Javier
> > 
> > > @@ -436,7 +436,8 @@ static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
> > >  {
> > >  	unsigned long flags;
> > >  
> > > -	clk_disable(pcdev->clk_csi);
> > > +	if (cpu_is_mx27())
> > > +		clk_disable_unprepare(pcdev->clk_csi);
> > 
> > This tells me, there are already 2 things going on here:
> > 
> > 1. add clock-(un)prepare operations to enable / disable. Is this a problem 
> > atm? is the driver non-functional without this change or is it just an API 
> > correctness change? I thought you replied to this already, but 
> > unfortunately I couldn't find that your reply again, sorry.
> 
> Since the common clock framework clk_prepare is mandatory.

Good, thanks for the clarification. So, this is not a functional, but a 
correctness fix. I think, such fixes are acceptable after -rc1 until 
something like -rc5, but maybe not after that. So, I'd try to push this 
some time within the next couple of weeks, once I get this fix as a 
separate patch.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From richard.zhao at freescale.com  Wed Aug  1 03:12:20 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 1 Aug 2012 15:12:20 +0800
Subject: [PATCH v5 2/3] ARM: imx6q: clk_register_clkdev usbmisc clock
In-Reply-To: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
References: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1343805141-5872-3-git-send-email-richard.zhao@freescale.com>

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520..660fcbb 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -405,6 +405,7 @@ int __init mx6q_clocks_init(void)
 	clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
 	clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
 	clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
+	clk_register_clkdev(clk[usboh3], NULL, "2184800.usbmisc");
 	clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
 	clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
 	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-- 
1.7.9.5




From richard.zhao at freescale.com  Wed Aug  1 03:12:18 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 1 Aug 2012 15:12:18 +0800
Subject: [PATCH v5 0/3] imx: add usbmisc support
Message-ID: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>

usbmisc driver handles the SoC specific non-core usb registers.

Changes since last version:
 - add missing ci13xxx_imx.h

Changes v3 -> v4:
 - rebase onto torvalds latest git tree
 - use phandle linke usb controllers and usbmisc device.
   It also make usbmisc driver possible to be kernel modules.

Richard Zhao (3):
  USB: chipidea: add imx usbmisc support
  ARM: imx6q: clk_register_clkdev usbmisc clock
  ARM: dts: imx6q-sabrelite: add usbmisc device

 .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
 .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |   10 ++
 arch/arm/mach-imx/clk-imx6q.c                      |    1 +
 drivers/usb/chipidea/Makefile                      |    2 +-
 drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
 drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
 drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
 9 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
 create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
 create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c

-- 
1.7.9.5




From richard.zhao at freescale.com  Wed Aug  1 03:12:19 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 1 Aug 2012 15:12:19 +0800
Subject: [PATCH v5 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
References: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1343805141-5872-2-git-send-email-richard.zhao@freescale.com>

i.MX usb controllers shares non-core registers, which may include
SoC specific controls. We take it as a usbmisc device and usbmisc
driver set operations needed by ci13xxx_imx driver.

For example, Sabrelite board has bad over-current design, we can
usbmisc to disable over-current detect.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
 .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
 drivers/usb/chipidea/Makefile                      |    2 +-
 drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
 drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
 drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
 6 files changed, 274 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
 create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
 create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c

diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
index 2c29041..5778b9c 100644
--- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
@@ -7,7 +7,10 @@ Required properties:
 
 Optional properties:
 - fsl,usbphy: phandler of usb phy that connects to the only one port
+- fsl,usbmisc: phandler of non-core register device, with one argument
+  that indicate usb controller index
 - vbus-supply: regulator for vbus
+- disable-over-current: disable over current detect
 
 Examples:
 usb at 02184000 { /* USB OTG */
@@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
 	reg = <0x02184000 0x200>;
 	interrupts = <0 43 0x04>;
 	fsl,usbphy = <&usbphy1>;
+	fsl,usbmisc = <&usbmisc 0>;
+	disable-over-current;
 };
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
new file mode 100644
index 0000000..97ce94e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
@@ -0,0 +1,14 @@
+* Freescale i.MX non-core registers
+
+Required properties:
+- #index-cells: Cells used to descibe usb controller index. Should be <1>
+- compatible: Should be one of below:
+	"fsl,imx6q-usbmisc" for imx6q
+- reg: Should contain registers location and length
+
+Examples:
+usbmisc at 02184800 {
+	#index-cells = <1>;
+	compatible = "fsl,imx6q-usbmisc";
+	reg = <0x02184800 0x200>;
+};
diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
index 5c66d9c..57e510f 100644
--- a/drivers/usb/chipidea/Makefile
+++ b/drivers/usb/chipidea/Makefile
@@ -15,5 +15,5 @@ ifneq ($(CONFIG_PCI),)
 endif
 
 ifneq ($(CONFIG_OF_DEVICE),)
-	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o
+	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o usbmisc_imx6q.o
 endif
diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index ef60d06..05cd0ae 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -22,6 +22,7 @@
 #include <linux/regulator/consumer.h>
 
 #include "ci.h"
+#include "ci13xxx_imx.h"
 
 #define pdev_to_phy(pdev) \
 	((struct usb_phy *)platform_get_drvdata(pdev))
@@ -34,6 +35,55 @@ struct ci13xxx_imx_data {
 	struct regulator *reg_vbus;
 };
 
+static const struct usbmisc_ops *usbmisc_ops;
+
+/* Common functions shared by usbmisc drivers */
+
+int usbmisc_set_ops(const struct usbmisc_ops *ops)
+{
+	if (usbmisc_ops)
+		return -EBUSY;
+
+	usbmisc_ops = ops;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(usbmisc_set_ops);
+
+void usbmisc_unset_ops(const struct usbmisc_ops *ops)
+{
+	usbmisc_ops = NULL;
+}
+EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
+
+int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args args;
+	int ret;
+
+	usbdev->dev = dev;
+
+	ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
+					0, &args);
+	if (ret) {
+		dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
+			ret);
+		memset(usbdev, 0, sizeof(*usbdev));
+		return ret;
+	}
+	usbdev->index = args.args[0];
+	of_node_put(args.np);
+
+	if (of_find_property(np, "disable-over-current", NULL))
+		usbdev->disable_oc = 1;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
+
+/* End of common functions shared by usbmisc drivers*/
+
 static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
 	.name			= "ci13xxx_imx",
 	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
@@ -51,6 +101,10 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 	struct regulator *reg_vbus;
 	int ret;
 
+	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
+		&& !usbmisc_ops)
+		return -EPROBE_DEFER;
+
 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 	if (!data) {
 		dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
@@ -120,6 +174,16 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
 		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
 	}
+
+	if (usbmisc_ops && usbmisc_ops->init) {
+		ret = usbmisc_ops->init(&pdev->dev);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"usbmisc init failed, ret=%d\n", ret);
+			return ret;
+		}
+	}
+
 	plat_ci = ci13xxx_add_device(&pdev->dev,
 				pdev->resource, pdev->num_resources,
 				&ci13xxx_imx_platdata);
diff --git a/drivers/usb/chipidea/ci13xxx_imx.h b/drivers/usb/chipidea/ci13xxx_imx.h
new file mode 100644
index 0000000..2e88acc
--- /dev/null
+++ b/drivers/usb/chipidea/ci13xxx_imx.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* Used to set SoC specific callbacks */
+struct usbmisc_ops {
+	/* It's called once when probe a usb device */
+	int (*init)(struct device *dev);
+};
+
+struct usbmisc_usb_device {
+	struct device *dev; /* usb controller device */
+	int index;
+
+	int disable_oc:1; /* over current detect disabled */
+};
+
+int usbmisc_set_ops(const struct usbmisc_ops *ops);
+void usbmisc_unset_ops(const struct usbmisc_ops *ops);
+int
+usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev);
diff --git a/drivers/usb/chipidea/usbmisc_imx6q.c b/drivers/usb/chipidea/usbmisc_imx6q.c
new file mode 100644
index 0000000..416e3fc
--- /dev/null
+++ b/drivers/usb/chipidea/usbmisc_imx6q.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "ci13xxx_imx.h"
+
+#define USB_DEV_MAX 4
+
+#define BM_OVER_CUR_DIS		BIT(7)
+
+struct imx6q_usbmisc {
+	void __iomem *base;
+	spinlock_t lock;
+	struct clk *clk;
+	struct usbmisc_usb_device usbdev[USB_DEV_MAX];
+};
+
+static struct imx6q_usbmisc *usbmisc;
+
+static struct usbmisc_usb_device *get_usbdev(struct device *dev)
+{
+	int i, ret;
+
+	for (i = 0; i < USB_DEV_MAX; i++) {
+		if (usbmisc->usbdev[i].dev == dev)
+			return &usbmisc->usbdev[i];
+		else if (!usbmisc->usbdev[i].dev)
+			break;
+	}
+
+	if (i >= USB_DEV_MAX)
+		return ERR_PTR(-EBUSY);
+
+	ret = usbmisc_get_init_data(dev, &usbmisc->usbdev[i]);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return &usbmisc->usbdev[i];
+}
+
+static int usbmisc_imx6q_init(struct device *dev)
+{
+
+	struct usbmisc_usb_device *usbdev;
+	unsigned long flags;
+	u32 reg;
+
+	usbdev = get_usbdev(dev);
+	if (IS_ERR(usbdev))
+		return PTR_ERR(usbdev);
+
+	if (usbdev->disable_oc) {
+		spin_lock_irqsave(&usbmisc->lock, flags);
+		reg = readl(usbmisc->base + usbdev->index * 4);
+		writel(reg | BM_OVER_CUR_DIS,
+			usbmisc->base + usbdev->index * 4);
+		spin_unlock_irqrestore(&usbmisc->lock, flags);
+	}
+
+	return 0;
+}
+
+static const struct usbmisc_ops imx6q_usbmisc_ops = {
+	.init = usbmisc_imx6q_init,
+};
+
+static const struct of_device_id usbmisc_imx6q_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-usbmisc"},
+	{ /* sentinel */ }
+};
+
+static int __devinit usbmisc_imx6q_probe(struct platform_device *pdev)
+{
+	struct resource	*res;
+	struct imx6q_usbmisc *data;
+	int ret;
+
+	if (usbmisc)
+		return -EBUSY;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	spin_lock_init(&data->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!data->base)
+		return -EADDRNOTAVAIL;
+
+	data->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(data->clk)) {
+		dev_err(&pdev->dev,
+			"failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+		return PTR_ERR(data->clk);
+	}
+
+	ret = clk_prepare_enable(data->clk);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"clk_prepare_enable failed, err=%d\n", ret);
+		return ret;
+	}
+
+	ret = usbmisc_set_ops(&imx6q_usbmisc_ops);
+	if (ret) {
+		clk_disable_unprepare(data->clk);
+		return ret;
+	}
+
+	usbmisc = data;
+
+	return 0;
+}
+
+static int __devexit usbmisc_imx6q_remove(struct platform_device *pdev)
+{
+	usbmisc_unset_ops(&imx6q_usbmisc_ops);
+	clk_disable_unprepare(usbmisc->clk);
+	return 0;
+}
+
+static struct platform_driver usbmisc_imx6q_driver = {
+	.probe = usbmisc_imx6q_probe,
+	.remove = __devexit_p(usbmisc_imx6q_remove),
+	.driver = {
+		.name = "usbmisc_imx6q",
+		.owner = THIS_MODULE,
+		.of_match_table = usbmisc_imx6q_dt_ids,
+	 },
+};
+
+int __init usbmisc_imx6q_drv_init(void)
+{
+	return platform_driver_register(&usbmisc_imx6q_driver);
+}
+subsys_initcall(usbmisc_imx6q_drv_init);
+
+void __exit usbmisc_imx6q_drv_exit(void)
+{
+	platform_driver_unregister(&usbmisc_imx6q_driver);
+}
+module_exit(usbmisc_imx6q_drv_exit);
+
+MODULE_ALIAS("platform:usbmisc-imx6q");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("driver for imx6q usb non-core registers");
+MODULE_AUTHOR("Richard Zhao <richard.zhao at freescale.com>");
-- 
1.7.9.5




From richard.zhao at freescale.com  Wed Aug  1 03:12:21 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 1 Aug 2012 15:12:21 +0800
Subject: [PATCH v5 3/3] ARM: dts: imx6q-sabrelite: add usbmisc device
In-Reply-To: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
References: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1343805141-5872-4-git-send-email-richard.zhao@freescale.com>

- add usbmisc device
- set property fsl,usbmisc for usb controllers
- set disable-over-current for imx6q-sabrelite usb otg

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
 arch/arm/boot/dts/imx6q.dtsi          |   10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d42e851..b32ebfc 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -62,6 +62,7 @@
 		aips-bus at 02100000 { /* AIPS2 */
 			usb at 02184000 { /* USB OTG */
 				vbus-supply = <&reg_usb_otg_vbus>;
+				disable-over-current;
 				status = "okay";
 			};
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d3c64b..a6e1816 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -629,6 +629,7 @@
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 0x04>;
 				fsl,usbphy = <&usbphy1>;
+				fsl,usbmisc = <&usbmisc 0>;
 				status = "disabled";
 			};
 
@@ -637,6 +638,7 @@
 				reg = <0x02184200 0x200>;
 				interrupts = <0 40 0x04>;
 				fsl,usbphy = <&usbphy2>;
+				fsl,usbmisc = <&usbmisc 1>;
 				status = "disabled";
 			};
 
@@ -644,6 +646,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184400 0x200>;
 				interrupts = <0 41 0x04>;
+				fsl,usbmisc = <&usbmisc 2>;
 				status = "disabled";
 			};
 
@@ -651,9 +654,16 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184600 0x200>;
 				interrupts = <0 42 0x04>;
+				fsl,usbmisc = <&usbmisc 3>;
 				status = "disabled";
 			};
 
+			usbmisc: usbmisc at 02184800 {
+				#index-cells = <1>;
+				compatible = "fsl,imx6q-usbmisc";
+				reg = <0x02184800 0x200>;
+			};
+
 			ethernet at 02188000 {
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
-- 
1.7.9.5




From lee.jones at linaro.org  Wed Aug  1 03:19:28 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 08:19:28 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <20120731151819.GC4468@opensource.wolfsonmicro.com>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
 <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
Message-ID: <5018D880.5090306@linaro.org>

On 31/07/12 16:18, Mark Brown wrote:
>>> It's certainly totally inappropriate for an "urgent" bugfix.
>
>> Well it just means that audio won't work for the ux500 for this
>> kernel release, but as we're waiting on clocks, this isn't a big
>> issue for us. If you do take it (with or without the return code),
>> feel free to add it to for-next instead of the -rc:s
>
> I'm not going to apply this patch.  This isn't a vendor BSP, we
> shouldn't be putting random hacks like this in core code.

BSP kernel or otherwise, it still seems wrong to me to fail and entire 
audio driver just because of a broken link.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Wed Aug  1 03:40:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 15:40:53 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208010845.19361.marex@denx.de>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
Message-ID: <20120801074051.GG1672@S2100-06.ap.freescale.net>

On Wed, Aug 01, 2012 at 08:45:19AM +0200, Marek Vasut wrote:
> > I must be missing something.  Why do almost all spi drivers call it in the
> > error path, even if there is no call to spi_master_get ?
> 
> To push the refcounting to 0, to deallocate the device, I'd say ...
> 
It's not going to work if spi_master_put is called without
spi_master_get being called before that.

Regards,
Shawn



From shawn.guo at linaro.org  Wed Aug  1 03:47:31 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 15:47:31 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801074051.GG1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
 <20120801074051.GG1672@S2100-06.ap.freescale.net>
Message-ID: <20120801074729.GH1672@S2100-06.ap.freescale.net>

On Wed, Aug 01, 2012 at 03:40:53PM +0800, Shawn Guo wrote:
> On Wed, Aug 01, 2012 at 08:45:19AM +0200, Marek Vasut wrote:
> > > I must be missing something.  Why do almost all spi drivers call it in the
> > > error path, even if there is no call to spi_master_get ?
> > 
> > To push the refcounting to 0, to deallocate the device, I'd say ...
> > 
> It's not going to work if spi_master_put is called without
> spi_master_get being called before that.
> 
I'm saying that kref_put on a kref that is never called on by kref_get
will not trigger the release.

Regards,
Shawn



From shawn.guo at linaro.org  Wed Aug  1 03:50:12 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 15:50:12 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801065650.GA2928@roeck-us.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
 <20120801065650.GA2928@roeck-us.net>
Message-ID: <20120801075010.GI1672@S2100-06.ap.freescale.net>

On Tue, Jul 31, 2012 at 11:56:50PM -0700, Guenter Roeck wrote:
> Guess we are in violent agreement. The sequence would then either be
> 	master = spi_alloc_device();

The discussion is around spi_alloc_master rather than spi_alloc_device,
isn't it?

Regards,
Shawn

> 	...
> 	spi_master_put(master);
> or
> 	master = spi_alloc_device();
> 	...
> 	kfree(master);
> 
> which makes sense to me. Question still is why most drivers neither call kfree()
> nor spi_master_put() in the remove function.



From andreas.devel at googlemail.com  Wed Aug  1 03:33:12 2012
From: andreas.devel at googlemail.com (=?UTF-8?B?QW5kcmVhcyBCaWXDn21hbm4=?=)
Date: Wed, 01 Aug 2012 09:33:12 +0200
Subject: [PATCH] arm:gemini: fix irq.c
In-Reply-To: <4FEE13C0.10505@biessmann.de>
References: <1338981778-19938-1-git-send-email-andreas@biessmann.de>
 <4FEE13C0.10505@biessmann.de>
Message-ID: <5018DBB8.2070004@googlemail.com>

ping

On 29.06.12 22:44, Andreas Bie?mann wrote:
> On 06.06.12 13:22, Andreas Bie?mann wrote:
>> Commit 9f97da78bf018206fb623cd351d454af2f105fe0 moved disable_hlt() from
>> arch/arm/include/asm/system.h to arch/arm/include/asm/system_misc.h but missed
>> to change arch/arm/mach-gemini/irq.c.
>>
>> This patch fixes following error:
>>
>> ---8<---
>> arch/arm/mach-gemini/irq.c: In function 'gemini_init_irq':
>> arch/arm/mach-gemini/irq.c:79:2: error: implicit declaration of function 'disable_hlt' [-Werror=implicit-function-declaration]
>> --->8---
>>
>> Signed-off-by: Andreas Bie?mann <andreas at biessmann.de>
>> cc: Hans Ulli Kroll <ulli.kroll at googlemail.com> 
>> cc: Russell King <linux at arm.linux.org.uk>
>> cc: linux-arm-kernel at lists.infradead.org
>> ---
>> Note: this is broken since 3.4 release, 3.3 is sane.
> 
> ping
> 
>>
>>  arch/arm/mach-gemini/irq.c |    1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
>> index ca70e5f..020852d 100644
>> --- a/arch/arm/mach-gemini/irq.c
>> +++ b/arch/arm/mach-gemini/irq.c
>> @@ -17,6 +17,7 @@
>>  #include <linux/sched.h>
>>  #include <asm/irq.h>
>>  #include <asm/mach/irq.h>
>> +#include <asm/system_misc.h>
>>  #include <mach/hardware.h>
>>  
>>  #define IRQ_SOURCE(base_addr)	(base_addr + 0x00)
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 


From lee.jones at linaro.org  Wed Aug  1 03:34:06 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 08:34:06 +0100
Subject: [PATCH 5/6] ARM: ux500: Ensure probing of Audio devices when
 Device Tree is enabled
In-Reply-To: <201207312054.13818.arnd@arndb.de>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-11-git-send-email-lee.jones@linaro.org>
 <201207312054.13818.arnd@arndb.de>
Message-ID: <5018DBEE.9090203@linaro.org>

On 31/07/12 21:54, Arnd Bergmann wrote:
> On Tuesday 31 July 2012, Lee Jones wrote:
>> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
>> index e641003..87a5cd7 100644
>> --- a/arch/arm/mach-ux500/board-mop500.c
>> +++ b/arch/arm/mach-ux500/board-mop500.c
>> @@ -794,6 +794,7 @@ static void __init u8500_init_machine(void)
>>                                  ARRAY_SIZE(mop500_platform_devs));
>>
>>                  mop500_sdi_init(parent);
>> +               mop500_msp_init(parent);
>>                  i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>>                  i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>>                  i2c_register_board_info(2, mop500_i2c2_devices,
>> @@ -801,6 +802,8 @@ static void __init u8500_init_machine(void)
>>
>>                  mop500_uib_init();
>>
>> +       } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
>> +               mop500_of_msp_init(parent);
>>          } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
>>                  /*
>>                   * The HREFv60 board removed a GPIO expander and routed
>> @@ -812,6 +815,7 @@ static void __init u8500_init_machine(void)
>>                                  ARRAY_SIZE(mop500_platform_devs));
>>
>>                  hrefv60_sdi_init(parent);
>> +               mop500_msp_init(parent);
>>
>>                  i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>>                  i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
>
>
> Looks like you're adding the same call to each of the three cases:
> mop500, snowball and hrefv60+. How about moving it before or after
> the if/elseif block?

The Snowball one is different 'mop500_msp_init' -> 'mop500_of_msp_init'.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed Aug  1 03:37:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 08:37:03 +0100
Subject: [PATCH 3/6] ARM: ux500: Fix merge error,
 so such struct 'snd_soc_u8500'
In-Reply-To: <50180BF6.6080908@mvista.com>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-6-git-send-email-lee.jones@linaro.org>
 <50180BF6.6080908@mvista.com>
Message-ID: <5018DC9F.30502@linaro.org>

On 31/07/12 17:46, Sergei Shtylyov wrote:
> Hello.
> 
> On 07/31/2012 05:31 PM, Lee Jones wrote:
> 
>    Subject doesn't parse for me...
> 
>> The platform attempts to register platform device 'snd_soc_u8500'
>> which doesn't actually exist. Here we change the reference to the
>> correct one 'snd_soc_mop500'.
> 
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Actually, it does make sense?

As a sentence: "This patch fixes merge error: so such structure 'struct snd_soc_u8500'.


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From LW at KARO-electronics.de  Wed Aug  1 03:38:07 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Wed, 1 Aug 2012 09:38:07 +0200
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801074051.GG1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
 <20120801074051.GG1672@S2100-06.ap.freescale.net>
Message-ID: <20504.56543.699097.320114@ipc1.ka-ro>

Shawn Guo writes:
> On Wed, Aug 01, 2012 at 08:45:19AM +0200, Marek Vasut wrote:
> > > I must be missing something.  Why do almost all spi drivers call it in the
> > > error path, even if there is no call to spi_master_get ?
> > 
> > To push the refcounting to 0, to deallocate the device, I'd say ...
> > 
> It's not going to work if spi_master_put is called without
> spi_master_get being called before that.
> 
spi_alloc_master() calls device_initialize() which resuires a
device_put() (called from spi_master_put()) to free the device.

Thus each call of either spi_alloc_master() or spi_master_get() must
be paired with an spi_master_put() call to free the resources.

The kfree() is taken care of by the spi_master_release() function that
is called once the last reference to the underlying struct device has
been released. Thus kfree() must not be called after
spi_alloc_master().


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From lee.jones at linaro.org  Wed Aug  1 03:56:14 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 08:56:14 +0100
Subject: [PATCH 5/6] ARM: ux500: Enable HIGHMEM on all mop500 platforms
In-Reply-To: <20120731220145.GD10335@n2100.arm.linux.org.uk>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <5017EBDC.6010005@linaro.org> <20120731143732.GS6802@n2100.arm.linux.org.uk>
 <201207312050.03113.arnd@arndb.de>
 <20120731220145.GD10335@n2100.arm.linux.org.uk>
Message-ID: <5018E11E.7080907@linaro.org>

On 31/07/12 23:01, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2012 at 08:50:02PM +0000, Arnd Bergmann wrote:
>> On Tuesday 31 July 2012, Russell King - ARM Linux wrote:
>>> I still fail to see how not having highmem enabled would ever cause memory
>>> corruption errors (unless something dealing with memory in a very very
>>> wrong way - iow, not using one of the reservation or memory allocation
>>> methods provided by the kernel.)
>>
>> The problem is that all users of ux500 systems pass a command line like
>>
>> vmalloc=256M mem=128M at 0 mali.mali_mem=32M at 128M hwmem=168M at 160M mem=48M at 328M mem_issw=1M at 383M mem=640M at 384M
>>
>> This is of course totally bogus and should not be done. If I understand
>> Lee correctly, one of the issues resulting from passing a command
>> line like this without enabling highmem is memory corruption.
>
> But the question is _why_ does that corruption happen.
>
>  From the above, we will end up with the kernel getting:
>
> 0x00000000 - 0x07ffffff (128M @ 0)
> 0x14800000 - 0x177fffff (48M  @ 328M)
> 0x18000000 - 0x3fffffff (640M @ 384M)
>
> with:
>
> 0x08000000 - 0x081fffff used for mali
> 0x0a000000 - 0x147fffff used for hwmem
> 0x17f00000 - 0x17ffffff used for mem_issw
>
> Now, with highmem disabled, the kernel should still map exactly the
> regions: 0x00000000 - 0x07ffffff, 0x14800000 - 0x177fffff, into the
> direct mapped region, and truncate the 0x18000000 - 0x3fffffff
> region appropriately, reducing the amount of memory available such
> that it won't overlap the vmalloc area (which you've specified to be
> a minimum of 256M.)
>
> This should _NOT_ cause any memory corruption.
>
> So, come on guys.  Debugging is *mandatory* for this kind of problem.
> Papering over it is obscene.

Actually I didn't go any further with it, as I changed to another 
identical piece of hardware and couldn't reproduce the issue.

FYI, here's the boot log from the broken board:

http://paste.ubuntu.com/1102017/

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Wed Aug  1 04:20:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 1 Aug 2012 16:20:26 +0800
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20504.56543.699097.320114@ipc1.ka-ro>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
 <20120801074051.GG1672@S2100-06.ap.freescale.net>
 <20504.56543.699097.320114@ipc1.ka-ro>
Message-ID: <20120801082024.GJ1672@S2100-06.ap.freescale.net>

On Wed, Aug 01, 2012 at 09:38:07AM +0200, Lothar Wa?mann wrote:
> Shawn Guo writes:
> > On Wed, Aug 01, 2012 at 08:45:19AM +0200, Marek Vasut wrote:
> > > > I must be missing something.  Why do almost all spi drivers call it in the
> > > > error path, even if there is no call to spi_master_get ?
> > > 
> > > To push the refcounting to 0, to deallocate the device, I'd say ...
> > > 
> > It's not going to work if spi_master_put is called without
> > spi_master_get being called before that.
> > 
> spi_alloc_master() calls device_initialize() which resuires a
> device_put() (called from spi_master_put()) to free the device.
> 
Ah, indeed.  I missed that kref_init() will initialize the refcount
to 1.

Thanks,
Shawn



From b29396 at freescale.com  Wed Aug  1 03:49:53 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 1 Aug 2012 15:49:53 +0800
Subject: [RFC PATCH 1/1] ASoC: soc-dapm: warn if no avaiable path found
 for widget kcontrol
In-Reply-To: <20120729202219.GA4384@opensource.wolfsonmicro.com>
References: <1343387941-25266-1-git-send-email-b29396@freescale.com>
 <20120729202219.GA4384@opensource.wolfsonmicro.com>
Message-ID: <20120801074952.GC30492@shlinux2.ap.freescale.net>

On Mon, Jul 30, 2012 at 04:22:19AM +0800, Mark Brown wrote:
> On Fri, Jul 27, 2012 at 07:19:01PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > This could help people know what's wrong going on if the required
> > path is not registered.
> 
> This isn't a good idea, it's fairly common for widgets to have a "None"
> option which isn't expected to have an input.
> 

What i changed is mux widgets, i'm wondering is it possible or correct
the mux widget has no input path?
If i understand correct, we may need set correct input path
for mux widget, or why we still need a mux?

Or can you help give an example that no input needed for mux widget?

Regards
Dong Aisheng



From lee.jones at linaro.org  Wed Aug  1 04:19:34 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 09:19:34 +0100
Subject: [PATCH 3/6] ARM: ux500: Fix merge error,
 so such struct 'snd_soc_u8500'
In-Reply-To: <5018DC9F.30502@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-6-git-send-email-lee.jones@linaro.org>
 <50180BF6.6080908@mvista.com> <5018DC9F.30502@linaro.org>
Message-ID: <5018E696.9000305@linaro.org>

On 01/08/12 08:37, Lee Jones wrote:
> On 31/07/12 17:46, Sergei Shtylyov wrote:
>> Hello.
>>
>> On 07/31/2012 05:31 PM, Lee Jones wrote:
>>
>>     Subject doesn't parse for me...
>>
>>> The platform attempts to register platform device 'snd_soc_u8500'
>>> which doesn't actually exist. Here we change the reference to the
>>> correct one 'snd_soc_mop500'.
>>
>>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
> Actually, it does make sense?
>
> As a sentence: "This patch fixes merge error: so such structure 'struct snd_soc_u8500'.

That's interesting. Not only when I read it did it seem correct, I also 
wrote it wrong "as a sentence". Of course "so" should be "no".


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From sbkim73 at samsung.com  Wed Aug  1 04:29:37 2012
From: sbkim73 at samsung.com (Sangbeom Kim)
Date: Wed, 01 Aug 2012 17:29:37 +0900
Subject: [alsa-devel] [PATCH 1/2] ASOC: SAMSUNG: Add DT support for i2s
In-Reply-To: <1343218170-30483-2-git-send-email-padma.v@samsung.com>
References: <1343218170-30483-1-git-send-email-padma.v@samsung.com>
 <1343218170-30483-2-git-send-email-padma.v@samsung.com>
Message-ID: <08da01cd6fbf$cd9b5c00$68d21400$@com>

Hi,
On Wednesday, July 25, 2012 9:09 PM, Padmavathi Venna wrote:

> Add support for device based discovery.
> 
Currently, I'm reviewing your patch set.
Your patch can support device tree for Samsung's i2s.
But I wonder that Your patch can support non-dt too,
So, Please test your patch on non-dt environment.
It looks unclear handling of clock source.
After code review, I will give you more detail comments,

Thanks,
Sangbeom.



From linux at arm.linux.org.uk  Wed Aug  1 04:41:27 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 1 Aug 2012 09:41:27 +0100
Subject: [PATCH 5/6] ARM: ux500: Enable HIGHMEM on all mop500 platforms
In-Reply-To: <5018E11E.7080907@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <5017EBDC.6010005@linaro.org> <20120731143732.GS6802@n2100.arm.linux.org.uk>
 <201207312050.03113.arnd@arndb.de>
 <20120731220145.GD10335@n2100.arm.linux.org.uk> <5018E11E.7080907@linaro.org>
Message-ID: <20120801084127.GT6802@n2100.arm.linux.org.uk>

On Wed, Aug 01, 2012 at 08:56:14AM +0100, Lee Jones wrote:
> On 31/07/12 23:01, Russell King - ARM Linux wrote:
>> On Tue, Jul 31, 2012 at 08:50:02PM +0000, Arnd Bergmann wrote:
>>> On Tuesday 31 July 2012, Russell King - ARM Linux wrote:
>>>> I still fail to see how not having highmem enabled would ever cause memory
>>>> corruption errors (unless something dealing with memory in a very very
>>>> wrong way - iow, not using one of the reservation or memory allocation
>>>> methods provided by the kernel.)
>>>
>>> The problem is that all users of ux500 systems pass a command line like
>>>
>>> vmalloc=256M mem=128M at 0 mali.mali_mem=32M at 128M hwmem=168M at 160M mem=48M at 328M mem_issw=1M at 383M mem=640M at 384M
>>>
>>> This is of course totally bogus and should not be done. If I understand
>>> Lee correctly, one of the issues resulting from passing a command
>>> line like this without enabling highmem is memory corruption.
>>
>> But the question is _why_ does that corruption happen.
>>
>>  From the above, we will end up with the kernel getting:
>>
>> 0x00000000 - 0x07ffffff (128M @ 0)
>> 0x14800000 - 0x177fffff (48M  @ 328M)
>> 0x18000000 - 0x3fffffff (640M @ 384M)
>>
>> with:
>>
>> 0x08000000 - 0x081fffff used for mali
>> 0x0a000000 - 0x147fffff used for hwmem
>> 0x17f00000 - 0x17ffffff used for mem_issw
>>
>> Now, with highmem disabled, the kernel should still map exactly the
>> regions: 0x00000000 - 0x07ffffff, 0x14800000 - 0x177fffff, into the
>> direct mapped region, and truncate the 0x18000000 - 0x3fffffff
>> region appropriately, reducing the amount of memory available such
>> that it won't overlap the vmalloc area (which you've specified to be
>> a minimum of 256M.)
>>
>> This should _NOT_ cause any memory corruption.
>>
>> So, come on guys.  Debugging is *mandatory* for this kind of problem.
>> Papering over it is obscene.
>
> Actually I didn't go any further with it, as I changed to another  
> identical piece of hardware and couldn't reproduce the issue.
>
> FYI, here's the boot log from the broken board:
>
> http://paste.ubuntu.com/1102017/

Well, the good thing is this:

   8 Truncating RAM at 18000000-3fffffff to -2c3fffff (vmalloc region overlap).

which means the RAM was properly truncated before it is passed to
memblock, etc.

That oops dump looks very much like an ASoC problem, where
dapm_widget_power_check() recurses into dapm_supply_check_power()
which then recurses back into dapm_widget_power_check(), and it
eventually overflows the kernel stack, corrupting the thread_info
and the pages below.

Given the address of the stack pointer (ebc480a8) I don't think
we can be too sure where it was supposed to be, and where the top
of stack should have been, so we don't know how many pages have
been stomped on and corrupted.

Stopping that recursion is the first thing that needs to be done
so that the cause of it can then be properly debugged without the
kernel itself corrupting memory below the kernel stack.


From lee.jones at linaro.org  Wed Aug  1 04:46:15 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 09:46:15 +0100
Subject: [PATCH 3/6 v2] ARM: ux500: Fix merge error, no matching driver
 name for, 'snd_soc_u8500'
In-Reply-To: <1343741493-17671-6-git-send-email-lee.jones@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-6-git-send-email-lee.jones@linaro.org>
Message-ID: <5018ECD7.5030005@linaro.org>

From: Lee Jones <lee.jones at linaro.org>
Date: Fri, 27 Jul 2012 13:10:52 +0100
Subject: [PATCH 1/1] ARM: ux500: Fix merge error, no matching driver name for
 'snd_soc_u8500'

The platform attempts to register platform device 'snd_soc_u8500'
which doesn't actually exist. Here we change the reference to the
correct one 'snd_soc_mop500'.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 9960480..df15646 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 	return pdev;
 }
 
-/* Platform device for ASoC U8500 machine */
-static struct platform_device snd_soc_u8500 = {
-		.name = "snd-soc-u8500",
+/* Platform device for ASoC MOP500 machine */
+static struct platform_device snd_soc_mop500 = {
+		.name = "snd-soc-mop500",
 		.id = 0,
 		.dev = {
 			.platform_data = NULL,
@@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent)
 {
 	struct platform_device *msp1;
 
-	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
-	platform_device_register(&snd_soc_u8500);
+	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
 
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-- 
1.7.9.5



From lee.jones at linaro.org  Wed Aug  1 04:48:25 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 09:48:25 +0100
Subject: [PATCH 5/6] ARM: ux500: Enable HIGHMEM on all mop500 platforms
In-Reply-To: <20120801084127.GT6802@n2100.arm.linux.org.uk>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <5017EBDC.6010005@linaro.org> <20120731143732.GS6802@n2100.arm.linux.org.uk>
 <201207312050.03113.arnd@arndb.de>
 <20120731220145.GD10335@n2100.arm.linux.org.uk> <5018E11E.7080907@linaro.org>
 <20120801084127.GT6802@n2100.arm.linux.org.uk>
Message-ID: <5018ED59.2020205@linaro.org>

On 01/08/12 09:41, Russell King - ARM Linux wrote:
> On Wed, Aug 01, 2012 at 08:56:14AM +0100, Lee Jones wrote:
>> On 31/07/12 23:01, Russell King - ARM Linux wrote:
>>> On Tue, Jul 31, 2012 at 08:50:02PM +0000, Arnd Bergmann wrote:
>>>> On Tuesday 31 July 2012, Russell King - ARM Linux wrote:
>>>>> I still fail to see how not having highmem enabled would ever cause memory
>>>>> corruption errors (unless something dealing with memory in a very very
>>>>> wrong way - iow, not using one of the reservation or memory allocation
>>>>> methods provided by the kernel.)
>>>>
>>>> The problem is that all users of ux500 systems pass a command line like
>>>>
>>>> vmalloc=256M mem=128M at 0 mali.mali_mem=32M at 128M hwmem=168M at 160M mem=48M at 328M mem_issw=1M at 383M mem=640M at 384M
>>>>
>>>> This is of course totally bogus and should not be done. If I understand
>>>> Lee correctly, one of the issues resulting from passing a command
>>>> line like this without enabling highmem is memory corruption.
>>>
>>> But the question is _why_ does that corruption happen.
>>>
>>>   From the above, we will end up with the kernel getting:
>>>
>>> 0x00000000 - 0x07ffffff (128M @ 0)
>>> 0x14800000 - 0x177fffff (48M  @ 328M)
>>> 0x18000000 - 0x3fffffff (640M @ 384M)
>>>
>>> with:
>>>
>>> 0x08000000 - 0x081fffff used for mali
>>> 0x0a000000 - 0x147fffff used for hwmem
>>> 0x17f00000 - 0x17ffffff used for mem_issw
>>>
>>> Now, with highmem disabled, the kernel should still map exactly the
>>> regions: 0x00000000 - 0x07ffffff, 0x14800000 - 0x177fffff, into the
>>> direct mapped region, and truncate the 0x18000000 - 0x3fffffff
>>> region appropriately, reducing the amount of memory available such
>>> that it won't overlap the vmalloc area (which you've specified to be
>>> a minimum of 256M.)
>>>
>>> This should _NOT_ cause any memory corruption.
>>>
>>> So, come on guys.  Debugging is *mandatory* for this kind of problem.
>>> Papering over it is obscene.
>>
>> Actually I didn't go any further with it, as I changed to another
>> identical piece of hardware and couldn't reproduce the issue.
>>
>> FYI, here's the boot log from the broken board:
>>
>> http://paste.ubuntu.com/1102017/
>
> Well, the good thing is this:
>
>     8 Truncating RAM at 18000000-3fffffff to -2c3fffff (vmalloc region overlap).
>
> which means the RAM was properly truncated before it is passed to
> memblock, etc.
>
> That oops dump looks very much like an ASoC problem, where
> dapm_widget_power_check() recurses into dapm_supply_check_power()
> which then recurses back into dapm_widget_power_check(), and it
> eventually overflows the kernel stack, corrupting the thread_info
> and the pages below.
>
> Given the address of the stack pointer (ebc480a8) I don't think
> we can be too sure where it was supposed to be, and where the top
> of stack should have been, so we don't know how many pages have
> been stomped on and corrupted.
>
> Stopping that recursion is the first thing that needs to be done
> so that the cause of it can then be properly debugged without the
> kernel itself corrupting memory below the kernel stack.

Those were my thoughts.

Here was my cry for help: https://lkml.org/lkml/2012/7/23/181

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From ian.molton at codethink.co.uk  Wed Aug  1 04:50:57 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Wed, 01 Aug 2012 09:50:57 +0100
Subject: [PATCH v2 3/6] mv643xx.c: Add basic device tree support.
In-Reply-To: <20120731164652.GD28852@lunn.ch>
References: <1343749529-17571-1-git-send-email-ian.molton@codethink.co.uk>
 <1343749529-17571-4-git-send-email-ian.molton@codethink.co.uk>
 <20120731164652.GD28852@lunn.ch>
Message-ID: <5018EDF1.40709@codethink.co.uk>

On 31/07/12 17:46, Andrew Lunn wrote:
> Hi Ian
>
> Probably the driver change will get upstream by netdev. The rest will
> go via the Orion maintainers into arm-soc. So you should probably move
> this board-dt.c change into a patch of its own, or make it part of:
>
> csb1724: Enable device tree based mv643xx ethernet support.
Its not csb1724 specific; I've merged it into

kirkwood: Add a clock setup helper for mv643xx ethernet.

and renamed it to:

kirkwood: Add fixups for DT based mv643xx ethernet.

As this described its purpose better. Hopefully in time, we can
pass something in DT that will allow us to remove that code.

-Ian


From kgene.kim at samsung.com  Wed Aug  1 05:39:17 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 01 Aug 2012 18:39:17 +0900
Subject: [PATCH V2 5/5] arm: samsung: delete frame buffer header files from
 platform
In-Reply-To: <CAL1wa8cShB7zDj-CPvfEncX+Up7enKM9MJOt-488dThj_tXbMA@mail.gmail.com>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <1343737385-23337-6-git-send-email-l.krishna@samsung.com>
 <02ee01cd6f89$f218b2c0$d64a1840$%kim@samsung.com>
 <CAL1wa8cShB7zDj-CPvfEncX+Up7enKM9MJOt-488dThj_tXbMA@mail.gmail.com>
Message-ID: <037101cd6fc9$85386e30$8fa94a90$%kim@samsung.com>

Leela Krishna Amudala wrote:
> 
> Hello Kgene,
> 
> On Wed, Aug 1, 2012 at 7:34 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Leela Krishna Amudala wrote:
> >>
> >> The FIMD register headers are moved to include/video/
> >> hence, deleting these files from platform side
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
> >> ---
> >>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h |  159 ---------
> >>  arch/arm/plat-samsung/include/plat/regs-fb.h    |  403
> > -------------------
> >> ----
> >>  2 files changed, 0 insertions(+), 562 deletions(-)
> >>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> >>
> > No. This should be squashed into first patch on this series. See below.
> >
> >  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
> > --------------------
> >  .../plat/regs-fb.h => include/video/samsung_fimd.h |  145
> > ++++++++++++++++--
> >  2 files changed, 134 insertions(+), 170 deletions(-)
> >  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >  rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
> > include/video/samsung_fimd.h (74%)
> >
> 
> If I squash it with the first patch and if somebody set that as a head
> commit, it will break the build. Hence, splitted it up from the first
> patch.
> 
NACK. your changes are not adding just moving. So should be squashed. If
required, you could create just one patch for moving them, probably, 1st,
3rd, 4th and 5th patches into one patch.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> Thank you Sylwester for suggesting this split up change.
> 
> Regards,
> Leela Krishna



From kgene.kim at samsung.com  Wed Aug  1 05:42:28 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 01 Aug 2012 18:42:28 +0900
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <5016D03D.8010607@codeaurora.org>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
Message-ID: <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>

Stephen Boyd wrote:
> 
> On 07/10/12 23:34, Kukjin Kim wrote:
> > Stephen Boyd wrote:
> >> Great. Kukjin Kim, can exynos use SGI0? It looks like exynos is the
> only
> >> one left to move to SGI0.
> >>
> > Yeah, EXYNOS can use SGI0 instead of SGI1 :)
> >
> >
> 
> Russell, can we apply something like this?
> 
Please feel free to add my ack on following change.

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-
> exynos/platsmp.c
> index 36c3984..090e32b 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -139,7 +139,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
> task_struct *idle)
> 
>  		__raw_writel(virt_to_phys(exynos4_secondary_startup),
>  			CPU1_BOOT_REG);
> -		gic_raise_softirq(cpumask_of(cpu), 1);
> +		gic_raise_softirq(cpumask_of(cpu), 0);
> 
>  		if (pen_release == -1)
>  			break;
> 
> 
> I see we have another user of SGI1. Magnus/Rafael, can we move
> smp-emev2.c to use SGI0 instead of SGI1?
> 
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From maxime.ripard at free-electrons.com  Wed Aug  1 05:46:45 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 01 Aug 2012 11:46:45 +0200
Subject: [PATCH 2/4] ARM: dts: mxs: Add alternative I2C muxing options
 for imx28
In-Reply-To: <CAOMZO5AaLB5m7TYPC03wTSFTDUTFrtV4Xr6gHrvKuGnpyUsf8Q@mail.gmail.com>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-3-git-send-email-maxime.ripard@free-electrons.com>
 <CAOMZO5AaLB5m7TYPC03wTSFTDUTFrtV4Xr6gHrvKuGnpyUsf8Q@mail.gmail.com>
Message-ID: <5018FB05.3020902@free-electrons.com>

Hi,

Le 31/07/2012 14:02, Fabio Estevam a ?crit :
> On Tue, Jul 31, 2012 at 7:29 AM, Maxime Ripard
> <maxime.ripard at free-electrons.com> wrote:
> 
>> +                               i2c0_pins_b: i2c0 at 1 {
>> +                                       reg = <1>;
>> +                                       fsl,pinmux-ids = <0x3001 0x3011>;
> 
> Can you please also list the name of the pin as comment (just like you
> did for pwm4)?
> 
> This would allow us to quickly identify the muxing option without the
> need of looking at the mxs pinctrl doc.

You're right, this will be in the next version.

Thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From FlorianSchandinat at gmx.de  Wed Aug  1 05:59:18 2012
From: FlorianSchandinat at gmx.de (Florian Tobias Schandinat)
Date: Wed, 01 Aug 2012 09:59:18 +0000
Subject: [PATCH V2 0/5] arm: samsung: Move FIMD headers to include/video/
In-Reply-To: <02f701cd6f8d$5ca3e850$15ebb8f0$%kim@samsung.com>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <02f701cd6f8d$5ca3e850$15ebb8f0$%kim@samsung.com>
Message-ID: <5018FDF6.4020205@gmx.de>

On 08/01/2012 02:28 AM, Kukjin Kim wrote:
> Leela Krishna Amudala wrote:
>>
>> This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch
>> side
>> to include/video/samsung_fimd.h
>>
>> This patchset is created and rebased against master branch of torvalds
>> tree.
>> Tested on smdk5250 board, build tested for other boards.
>>
> (Cc'ed Florian Tobias Schandinat)
> 
> Yeah, since it's merge window, this series could be created against on
> mainline. And IMO, would be helpful to us if this series could be sent to
> upstream via samsung tree after reviewing, because this touches too many
> files in samsung tree and just adds include/video/samsung_fimd.h. But I'm
> not sure the added inclusion will be used in other file of drivers/video. If
> so, I can provide some topic branch can be merged into Florian's tree.
> Florian, how about?

Using a topic branch to merge it in both trees sounds like a good plan
to me.


Best regards,

Florian Tobias Schandinat

> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
>> Changes from version 1:
>> 	- Split the patches as per Sylwester comments
>> 	- Changed FIMD_V8_xxx macro to EXYNOS5_xxx
>>
>> Leela Krishna Amudala (5):
>>   include/video: Add samsung FIMD register header
>>   include/video: Add Exynos5 specific FIMD register offsets
>>   arm: samsung: Include the modified FIMD header file
>>   driver: Include the modified FIMD header file
>>   arm: samsung: delete frame buffer header files from platform
>>
>>  arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
>>  arch/arm/mach-exynos/mach-origen.c                 |    2 +-
>>  arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
>>  arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
>>  arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
>>  arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
>>  arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
>>  arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
>>  arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
>>  arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
>>  arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
>>  arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
>>  arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
>>  arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
>>  arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
>>  arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
>>  arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
>>  arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
>>  arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
>>  arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
>>  arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
>>  arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
> ----------------
>> ----
>>  drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
>>  drivers/video/s3c-fb.c                             |    2 +-
>>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  152
>> +++++++++++++++++--
>>  26 files changed, 165 insertions(+), 194 deletions(-)
>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>  rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
>> include/video/samsung_fimd.h (74%)
> 
> 



From s.nawrocki at samsung.com  Wed Aug  1 06:00:08 2012
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 01 Aug 2012 12:00:08 +0200
Subject: [PATCH V2 5/5] arm: samsung: delete frame buffer header files from
 platform
In-Reply-To: <037101cd6fc9$85386e30$8fa94a90$%kim@samsung.com>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <1343737385-23337-6-git-send-email-l.krishna@samsung.com>
 <02ee01cd6f89$f218b2c0$d64a1840$%kim@samsung.com>
 <CAL1wa8cShB7zDj-CPvfEncX+Up7enKM9MJOt-488dThj_tXbMA@mail.gmail.com>
 <037101cd6fc9$85386e30$8fa94a90$%kim@samsung.com>
Message-ID: <5018FE28.8070907@samsung.com>

Hi,

On 08/01/2012 11:39 AM, Kukjin Kim wrote:
> Leela Krishna Amudala wrote:
>> On Wed, Aug 1, 2012 at 7:34 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>>> Leela Krishna Amudala wrote:
>>>>
>>>> The FIMD register headers are moved to include/video/
>>>> hence, deleting these files from platform side
>>>>
>>>> Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
>>>> ---
>>>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h |  159 ---------
>>>>  arch/arm/plat-samsung/include/plat/regs-fb.h    |  403
>>> -------------------
>>>> ----
>>>>  2 files changed, 0 insertions(+), 562 deletions(-)
>>>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
>>>>
>>> No. This should be squashed into first patch on this series. See below.
>>>
>>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
>>> --------------------
>>>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  145
>>> ++++++++++++++++--
>>>  2 files changed, 134 insertions(+), 170 deletions(-)
>>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>>>  rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
>>> include/video/samsung_fimd.h (74%)
>>>
>>
>> If I squash it with the first patch and if somebody set that as a head
>> commit, it will break the build. Hence, splitted it up from the first
>> patch.
>>
> NACK. your changes are not adding just moving. So should be squashed. If
> required, you could create just one patch for moving them, probably, 1st,
> 3rd, 4th and 5th patches into one patch.

Yes, this patch series is mainly moving files around. But to avoid git
bisect breakage, it should be split as it is done now, or the whole
series should be squashed into one patch. The latter might be even easier
to handle, but having a single patch touching arch/arm/ and drivers/
might not be a good idea. If you're fine handling that, then we just
need to squash this series into single patch.
It just need to be ensured, IMO, there is no bisection breakage.

--

Regards,
Sylwester


From kgene.kim at samsung.com  Wed Aug  1 06:03:55 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 01 Aug 2012 19:03:55 +0900
Subject: [PATCH V2 0/5] arm: samsung: Move FIMD headers to include/video/
In-Reply-To: <5018FDF6.4020205@gmx.de>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <02f701cd6f8d$5ca3e850$15ebb8f0$%kim@samsung.com> <5018FDF6.4020205@gmx.de>
Message-ID: <037c01cd6fcc$f5cb10f0$e16132d0$%kim@samsung.com>

Florian Tobias Schandinat wrote:
> 
> On 08/01/2012 02:28 AM, Kukjin Kim wrote:
> > Leela Krishna Amudala wrote:
> >>
> >> This patchset moves the contents of regs-fb-v4.h and regs-fb.h from
> arch
> >> side
> >> to include/video/samsung_fimd.h
> >>
> >> This patchset is created and rebased against master branch of torvalds
> >> tree.
> >> Tested on smdk5250 board, build tested for other boards.
> >>
> > (Cc'ed Florian Tobias Schandinat)
> >
> > Yeah, since it's merge window, this series could be created against on
> > mainline. And IMO, would be helpful to us if this series could be sent
> to
> > upstream via samsung tree after reviewing, because this touches too many
> > files in samsung tree and just adds include/video/samsung_fimd.h. But
> I'm
> > not sure the added inclusion will be used in other file of
drivers/video.
> If
> > so, I can provide some topic branch can be merged into Florian's tree.
> > Florian, how about?
> 
> Using a topic branch to merge it in both trees sounds like a good plan
> to me.
> 
Sure, if this change is ready, I will create topic branch then let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Wed Aug  1 06:09:01 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 01 Aug 2012 19:09:01 +0900
Subject: [PATCH V2 5/5] arm: samsung: delete frame buffer header files from
 platform
In-Reply-To: <5018FE28.8070907@samsung.com>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <1343737385-23337-6-git-send-email-l.krishna@samsung.com>
 <02ee01cd6f89$f218b2c0$d64a1840$%kim@samsung.com>
 <CAL1wa8cShB7zDj-CPvfEncX+Up7enKM9MJOt-488dThj_tXbMA@mail.gmail.com>
 <037101cd6fc9$85386e30$8fa94a90$%kim@samsung.com>
 <5018FE28.8070907@samsung.com>
Message-ID: <037d01cd6fcd$ac64d300$052e7900$%kim@samsung.com>

Sylwester Nawrocki wrote:
> 
> Hi,
> 
> On 08/01/2012 11:39 AM, Kukjin Kim wrote:
> > Leela Krishna Amudala wrote:
> >> On Wed, Aug 1, 2012 at 7:34 AM, Kukjin Kim <kgene.kim at samsung.com>
> wrote:
> >>> Leela Krishna Amudala wrote:
> >>>>
> >>>> The FIMD register headers are moved to include/video/
> >>>> hence, deleting these files from platform side
> >>>>
> >>>> Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
> >>>> ---
> >>>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h |  159 ---------
> >>>>  arch/arm/plat-samsung/include/plat/regs-fb.h    |  403
> >>> -------------------
> >>>> ----
> >>>>  2 files changed, 0 insertions(+), 562 deletions(-)
> >>>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> >>>>
> >>> No. This should be squashed into first patch on this series. See
below.
> >>>
> >>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
> >>> --------------------
> >>>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  145
> >>> ++++++++++++++++--
> >>>  2 files changed, 134 insertions(+), 170 deletions(-)
> >>>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >>>  rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
> >>> include/video/samsung_fimd.h (74%)
> >>>
> >>
> >> If I squash it with the first patch and if somebody set that as a head
> >> commit, it will break the build. Hence, splitted it up from the first
> >> patch.
> >>
> > NACK. your changes are not adding just moving. So should be squashed. If
> > required, you could create just one patch for moving them, probably,
1st,
> > 3rd, 4th and 5th patches into one patch.
> 
> Yes, this patch series is mainly moving files around. But to avoid git
> bisect breakage, it should be split as it is done now, or the whole
> series should be squashed into one patch. The latter might be even easier
> to handle, but having a single patch touching arch/arm/ and drivers/
> might not be a good idea. If you're fine handling that, then we just
> need to squash this series into single patch.
> It just need to be ensured, IMO, there is no bisection breakage.
> 
I know you meant. But we don't need to keep the changes 'adding and
removing' for just moving on this.

I commented on 0/5 patch in this series before, if this is ready, I will
create topic branch so that it could be merged into both mine and Florian's.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From maxime.ripard at free-electrons.com  Wed Aug  1 06:28:27 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 01 Aug 2012 12:28:27 +0200
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED
 Controller
In-Reply-To: <20120801052424.GD1672@S2100-06.ap.freescale.net>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
 <20120801052424.GD1672@S2100-06.ap.freescale.net>
Message-ID: <501904CB.9040104@free-electrons.com>

Hi Shawn,

Le 01/08/2012 07:24, Shawn Guo a ?crit :
> On Tue, Jul 31, 2012 at 12:29:33PM +0200, Maxime Ripard wrote:
>> +Optional properties:
>> +  - oled-reset-active-low: Is the reset gpio is active on physical low?
> 
> You may want to take a look at commit c1cb438 (bindings: update imx and
> mxs #gpio-cells) which got merged recently.  In case the driver will
> only work on mxs, this optional property can just be dropped.

Thanks for the tip.
However, I'm not sure this device will be mxs specific, since this
controller is used on some other devices as well (I know for example
that some uses it with the Arduino, even though it's not related to
Linux), so relying on mxs-specific capabilities here might not be that
great.

But since it's only for a mxs board for now, maybe we can rely on this
and add a dt parameter if we need it in the future. I don't know, both
make sense I guess.

Maxime

-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From javier.martin at vista-silicon.com  Wed Aug  1 06:45:38 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  1 Aug 2012 12:45:38 +0200
Subject: [PATCH] Visstrim SM10: Use mo_version to decide board video mode.
Message-ID: <1343817938-21905-1-git-send-email-javier.martin@vista-silicon.com>

If the mother board version number is odd, emmaprp() for
format conversion + UVC camera will be used.

Otherwise mx2_camera and m2m-deinterlacer will be registered.

For both cases Coda video codec is registered.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   52 ++++++++++++++++++++++++---
 1 file changed, 47 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 176533e..5de9335 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -49,6 +49,10 @@
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
 
+#define VERSION_MASK		0x7
+#define MOTHERBOARD_SHIFT	4
+#define EXPBOARD_SHIFT		0
+
 #define MOTHERBOARD_BIT2	(GPIO_PORTD + 31)
 #define MOTHERBOARD_BIT1	(GPIO_PORTD + 30)
 #define MOTHERBOARD_BIT0	(GPIO_PORTD + 29)
@@ -205,7 +209,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
 static phys_addr_t mx2_camera_base __initdata;
 #define MX2_CAMERA_BUF_SIZE SZ_8M
 
-static void __init visstrim_camera_init(void)
+static void __init visstrim_analog_camera_init(void)
 {
 	struct platform_device *pdev;
 	int dma;
@@ -442,6 +446,27 @@ static void __init visstrim_deinterlace_init(void)
 		return;
 }
 
+/* Emma-PrP for format conversion */
+static void __init visstrim_emmaprp_init(void)
+{
+	struct platform_device *pdev;
+	int dma;
+
+	pdev = imx27_add_mx2_emmaprp();
+	if (IS_ERR(pdev))
+		return;
+
+	/*
+	 * Use the same memory area as the analog camera since both
+	 * devices are, by nature, exclusive.
+	 */
+	dma = dma_declare_coherent_memory(&pdev->dev,
+				mx2_camera_base, mx2_camera_base,
+				MX2_CAMERA_BUF_SIZE,
+				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+	if (!(dma & DMA_MEMORY_MAP))
+		return;
+}
 
 static void __init visstrim_m10_revision(void)
 {
@@ -467,13 +492,14 @@ static void __init visstrim_m10_revision(void)
 	mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
 
 	system_rev = 0x27000;
-	system_rev |= (mo_version << 4);
-	system_rev |= exp_version;
+	system_rev |= (mo_version << MOTHERBOARD_SHIFT);
+	system_rev |= (exp_version << EXPBOARD_SHIFT);
 }
 
 static void __init visstrim_m10_board_init(void)
 {
 	int ret;
+	int mo_version;
 
 	imx27_soc_init();
 	visstrim_m10_revision();
@@ -505,8 +531,24 @@ static void __init visstrim_m10_board_init(void)
 	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
 				      &iclink_tvp5150, sizeof(iclink_tvp5150));
 	gpio_led_register_device(0, &visstrim_m10_led_data);
-	visstrim_deinterlace_init();
-	visstrim_camera_init();
+
+	/* Use mother board version to decide what video devices we shall use */
+	mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
+	if (mo_version & 0x1) {
+		visstrim_emmaprp_init();
+
+		/*
+		 * Despite not being used, tvp5150 must be
+		 * powered on to avoid I2C problems. To minimize
+		 * power consupmtion keep reset enabled.
+		 */
+		gpio_set_value(TVP5150_PWDN, 1);
+		ndelay(1);
+		gpio_set_value(TVP5150_RSTN, 0);
+	} else {
+		visstrim_deinterlace_init();
+		visstrim_analog_camera_init();
+	}
 	visstrim_coda_init();
 }
 
-- 
1.7.9.5



From konrad.wilk at oracle.com  Wed Aug  1 06:42:37 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 06:42:37 -0400
Subject: [Xen-devel] [PATCH 01/24] arm: initial Xen support
In-Reply-To: <alpine.DEB.2.02.1207271246080.26163@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120726163020.GB9222@phenom.dumpdata.com>
 <alpine.DEB.2.02.1207271246080.26163@kaball.uk.xensource.com>
Message-ID: <20120801104237.GB7227@phenom.dumpdata.com>

> > > +struct pvclock_wall_clock {
> > > +	u32   version;
> > > +	u32   sec;
> > > +	u32   nsec;
> > > +} __attribute__((__packed__));
> > 
> > That is weird. It is 4+4+4 = 12 bytes? Don't you want it to be 16 bytes?
> 
> I agree that 16 bytes would be a better choice, but it needs to match
> the struct in Xen that is defined as follow:
> 
>     uint32_t wc_version;      /* Version counter: see vcpu_time_info_t. */
>     uint32_t wc_sec;          /* Secs  00:00:00 UTC, Jan 1, 1970.  */
>     uint32_t wc_nsec;         /* Nsecs 00:00:00 UTC, Jan 1, 1970.  */

Would it make sense to add some paddigin then at least? In both
cases? Or is it too late for this?


From baruch at tkos.co.il  Wed Aug  1 07:02:27 2012
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 1 Aug 2012 14:02:27 +0300
Subject: [PATCH] Visstrim SM10: Use mo_version to decide board video mode.
In-Reply-To: <1343817938-21905-1-git-send-email-javier.martin@vista-silicon.com>
References: <1343817938-21905-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120801110227.GF29843@sapphire.tkos.co.il>

Hi Javier,

On Wed, Aug 01, 2012 at 12:45:38PM +0200, Javier Martin wrote:
> If the mother board version number is odd, emmaprp() for
> format conversion + UVC camera will be used.
> 
> Otherwise mx2_camera and m2m-deinterlacer will be registered.
> 
> For both cases Coda video codec is registered.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---

[snip]

> @@ -442,6 +446,27 @@ static void __init visstrim_deinterlace_init(void)
>  		return;
>  }
>  
> +/* Emma-PrP for format conversion */
> +static void __init visstrim_emmaprp_init(void)
> +{
> +	struct platform_device *pdev;
> +	int dma;
> +
> +	pdev = imx27_add_mx2_emmaprp();
> +	if (IS_ERR(pdev))
> +		return;
> +
> +	/*
> +	 * Use the same memory area as the analog camera since both
> +	 * devices are, by nature, exclusive.
> +	 */
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +				mx2_camera_base, mx2_camera_base,
> +				MX2_CAMERA_BUF_SIZE,
> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +	if (!(dma & DMA_MEMORY_MAP))
> +		return;

What's the point of these two lines at the end of a void function? Maybe print 
an error?

baruch

> +}

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From sshtylyov at mvista.com  Wed Aug  1 08:08:38 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 01 Aug 2012 16:08:38 +0400
Subject: [PATCH 06/22] ARM: LPAE: use phys_addr_t in alloc_init_pud()
In-Reply-To: <1343775898-28345-7-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-7-git-send-email-cyril@ti.com>
Message-ID: <50191C46.4090902@mvista.com>

Hello.

On 01-08-2012 3:04, Cyril Chemparathy wrote:

> From: Vitaly Andrianov <vitalya at ti.com>

> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
> unsigned long when passing in the phys argument.

> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a, which

    Please also specify that commit's summary in parens.

> applied similar changes elsewhere in the ARM memory management code.

> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

WBR, Sergei



From B37400 at freescale.com  Wed Aug  1 08:13:19 2012
From: B37400 at freescale.com (Singh Sandeep-B37400)
Date: Wed, 1 Aug 2012 12:13:19 +0000
Subject: [2/3][PATCH][v2] TDM Framework
In-Reply-To: <20120730160146.GB28703@kroah.com>
References: <1343397940-12975-1-git-send-email-sandeep@freescale.com>
 <20120727152542.GB1613@electric-eye.fr.zoreil.com>
 <3F1D9DCAAB49B94D88DBE05911FA4E6E511121@039-SN1MPN1-006.039d.mgd.msft.net>
 <20120730160146.GB28703@kroah.com>
Message-ID: <3F1D9DCAAB49B94D88DBE05911FA4E6E515F98@039-SN1MPN1-001.039d.mgd.msft.net>




> -----Original Message-----
> From: Greg KH [mailto:greg at kroah.com]
> Sent: Monday, July 30, 2012 9:32 PM
> To: Singh Sandeep-B37400
> Cc: Francois Romieu; devel at driverdev.osuosl.org; linuxppc-
> dev at lists.ozlabs.org; galak at kernel.crashing.org; linux-arm-
> kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> Subject: Re: [2/3][PATCH][v2] TDM Framework
> 
> On Mon, Jul 30, 2012 at 09:50:57AM +0000, Singh Sandeep-B37400 wrote:
> > 1. You should send some kernel mode TDM clients. Without those the
> framework
> >    is pretty useless.
> > [Sandeep] We do have a test client but not good enough to be pushed in
> > open source, should we add it to documentation??
> 
> Then how do you know if the framework is "correct" and good enough for
> real clients?  We don't add frameworks, or apis, to the kernel without
> users, so you will have to come up with some users before we can accept
> it.
We can only say that this framework is available in FSL BSPs and being used by VoIP companies.
But running a complete voice stack itself is beyond the scope of Freescale.
So vendors integrate their solutions with FSL solution.
To test the framework we have a small application in our BSP (this is a very basic test client) which tests the TDM driver and the SLIC interface from voice  transfer perspective.
We can get this added in the Linux codebase in some test directory. What could be a good place for this?

Regards
Sandeep




From broonie at opensource.wolfsonmicro.com  Wed Aug  1 08:15:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 13:15:16 +0100
Subject: [RFC PATCH 1/1] ASoC: soc-dapm: warn if no avaiable path found
 for widget kcontrol
In-Reply-To: <20120801074952.GC30492@shlinux2.ap.freescale.net>
References: <1343387941-25266-1-git-send-email-b29396@freescale.com>
 <20120729202219.GA4384@opensource.wolfsonmicro.com>
 <20120801074952.GC30492@shlinux2.ap.freescale.net>
Message-ID: <20120801121516.GO11892@opensource.wolfsonmicro.com>

On Wed, Aug 01, 2012 at 03:49:53PM +0800, Dong Aisheng wrote:
> On Mon, Jul 30, 2012 at 04:22:19AM +0800, Mark Brown wrote:

> > This isn't a good idea, it's fairly common for widgets to have a "None"
> > option which isn't expected to have an input.

> What i changed is mux widgets, i'm wondering is it possible or correct
> the mux widget has no input path?
> If i understand correct, we may need set correct input path
> for mux widget, or why we still need a mux?

> Or can you help give an example that no input needed for mux widget?

The above is the most common example - one of the inputs to a mux being
a "no input" option which shouldn't be connected to anything.  A mux
with no inputs at all would be silly, but having one (or sometimes a
couple for various reasons) that isn't connected isn't unusual.


From hvaibhav at ti.com  Wed Aug  1 08:20:16 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 1 Aug 2012 17:50:16 +0530
Subject: omap_device: query on "fck" clk alias created
Message-ID: <50191F00.1040501@ti.com>

Hi,

In OMAP world, we have omap_device layer, which exports api's like
omap_device_build() to create and register platform_device to the
kernel. This layer understands hwmod infrastructure and parses all the
platform specific information from it.
Now with DT migration, the same thing is achieved using a notifier,
which in turn omap_device_build_from_dt(), which in turn does same thing.

One of the thing which is happening in both execution path is, creating
alias for functional clock (hwmod_data->main_clk) for each device
getting created with the con_id = "fck".

Now the problem with this is,

The clk_get() api will not work, unless we pass both the arguments (dev,
con_id) properly. Now expecting driver to always label con_id with "fck"
is undesirable, as the same driver can be reused on multiple platforms,
which can be non-omap and/or non-ti platforms.
Also we have multiple examples where driver simply calls (which is right)

clk = clk_get(&pdev->dev, NULL);

This would fail on OMAP platforms, unless you modify clockxxx_data.c
file with,

CLK("<device>",  NULL,           &xxx_fck,    CK_34XX),


Devices specially with only one clock source always prefer not to
specify con_id.
And it seems wrong thing, as across platforms IP integration can be very
different and you can not expect to change the clock-tree table always.

So the option here we have is,

1. Instead of creating alias with "fck", create an alias only with dev
pointer, that means con_id = NULL.
I have already tested this and it works on AM33xx platform.

2. Add a new flag inside hwmod or omap_device, so that it can be read at
omap_device layer and based on that we can decide whether to add con_id
or not while invoking clkdev_alloc().
This may be required to support legacy drivers which are not migrated to
runtime_pm and still calls clk_get() for both "fck" and "ick", so here
we need "fck" clk alias.


Any comments or opinion on this? Based on the feedback I can create the
changes and submit it to the list.

Thanks,
Vaibhav


From greg at kroah.com  Wed Aug  1 08:37:38 2012
From: greg at kroah.com (Greg KH)
Date: Wed, 1 Aug 2012 05:37:38 -0700
Subject: [2/3][PATCH][v2] TDM Framework
In-Reply-To: <3F1D9DCAAB49B94D88DBE05911FA4E6E515F98@039-SN1MPN1-001.039d.mgd.msft.net>
References: <1343397940-12975-1-git-send-email-sandeep@freescale.com>
 <20120727152542.GB1613@electric-eye.fr.zoreil.com>
 <3F1D9DCAAB49B94D88DBE05911FA4E6E511121@039-SN1MPN1-006.039d.mgd.msft.net>
 <20120730160146.GB28703@kroah.com>
 <3F1D9DCAAB49B94D88DBE05911FA4E6E515F98@039-SN1MPN1-001.039d.mgd.msft.net>
Message-ID: <20120801123738.GA28291@kroah.com>

On Wed, Aug 01, 2012 at 12:13:19PM +0000, Singh Sandeep-B37400 wrote:
> > On Mon, Jul 30, 2012 at 09:50:57AM +0000, Singh Sandeep-B37400 wrote:
> > > 1. You should send some kernel mode TDM clients. Without those the
> > framework
> > >    is pretty useless.
> > > [Sandeep] We do have a test client but not good enough to be pushed in
> > > open source, should we add it to documentation??
> > 
> > Then how do you know if the framework is "correct" and good enough for
> > real clients?  We don't add frameworks, or apis, to the kernel without
> > users, so you will have to come up with some users before we can accept
> > it.
> We can only say that this framework is available in FSL BSPs and being used by VoIP companies.
> But running a complete voice stack itself is beyond the scope of Freescale.
> So vendors integrate their solutions with FSL solution.
> To test the framework we have a small application in our BSP (this is a very basic test client) which tests the TDM driver and the SLIC interface from voice  transfer perspective.
> We can get this added in the Linux codebase in some test directory. What could be a good place for this?

tools/ is a good place for that.

And sorry, I was thinking you had kernel drivers that attached to this
framework, not userspace programs.  Actually, what is the user/kernel
interface for this framework, I seem to have missed that entirely.  You
will have to document that quite well, and run it by the linux-api
mailing list.

thanks,

greg k-h


From p.paneri at samsung.com  Wed Aug  1 09:05:46 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:46 +0530
Subject: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for samsung
 SoCs
Message-ID: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>

This patch set introduces a phy driver for samsung SoCs. It uses the existing
transceiver infrastructure to provide phy control functions. Use of this driver
can be extended for usb host phy as well. Over the period of time all the phy
related code for most of the samsung SoCs can be integrated here.
Removing the existing phy code from mach-s3c64xx but not from other machine 
code.This driver is tested with smdk6410 and Exynos4210(with DT).

Praveen Paneri (5):
  usb: phy: samsung: Introducing usb phy driver for hsotg
  usb: s3c-hsotg: Adding phy driver support
  ARM: S3C64XX: Removing old phy setup code
  ARM: S3C64XX: Enabling sec_usbphy driver
  ARM: Exynos4210: Enabling sec_usbphy driver

 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
 arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    5 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |    6 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    5 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
 arch/arm/plat-samsung/devs.c                       |   32 ++
 arch/arm/plat-samsung/include/plat/devs.h          |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 drivers/usb/gadget/s3c-hsotg.c                     |   38 ++-
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/sec_usbphy.c                       |  354 ++++++++++++++++++++
 drivers/usb/phy/sec_usbphy.h                       |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 19 files changed, 533 insertions(+), 88 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/sec_usbphy.c
 create mode 100644 drivers/usb/phy/sec_usbphy.h



From p.paneri at samsung.com  Wed Aug  1 09:05:47 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:47 +0530
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1343826351-8756-2-git-send-email-p.paneri@samsung.com>

This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable phy. Tested with
smdk6410 and smdkv310. More SoCs can be brought under later.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/sec_usbphy.c                       |  354 ++++++++++++++++++++
 drivers/usb/phy/sec_usbphy.h                       |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 6 files changed, 425 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/sec_usbphy.c
 create mode 100644 drivers/usb/phy/sec_usbphy.h

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 0000000..fefd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,9 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..abbebe2 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -15,3 +15,11 @@ config USB_ISP1301
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1301.
+
+config SEC_USBPHY
+       bool "Samsung USB PHY controller Driver"
+       depends on USB_S3C_HSOTG
+       select USB_OTG_UTILS
+       help
+         Enable this to support Samsung USB phy controller for samsung
+         SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..6bb66f0 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_SEC_USBPHY)		+= sec_usbphy.o
diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
new file mode 100644
index 0000000..33119eb
--- /dev/null
+++ b/drivers/usb/phy/sec_usbphy.c
@@ -0,0 +1,354 @@
+/* linux/drivers/usb/phy/sec_usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/s3c-hsotg.h>
+
+#include "sec_usbphy.h"
+
+enum sec_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_EXYNOS4210,
+};
+
+/*
+ * struct sec_usbphy - transceiver driver state
+ * @phy: transceiver structure
+ * @plat: platform data
+ * @dev: The parent device supplied to the probe function
+ * @clk: usb phy clock
+ * @regs: usb phy register memory base
+ * @cpu_type: machine identifier
+ */
+struct sec_usbphy {
+	struct usb_phy	phy;
+	struct s3c_usbphy_plat *plat;
+	struct device	*dev;
+	struct clk	*clk;
+	void __iomem	*regs;
+	int		cpu_type;
+};
+
+#define phy_to_sec(x)		container_of((x), struct sec_usbphy, phy)
+
+/*
+ * Enables or disables the phy clock
+ * returns 0 on success else the error
+ */
+static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
+{
+	if (on) {
+		if (!sec->clk) {
+			sec->clk = clk_get(sec->dev, "otg");
+			if (IS_ERR(sec->clk)) {
+				dev_err(sec->dev, "Failed to get otg clock\n");
+				return PTR_ERR(sec->clk);
+			}
+		}
+		clk_enable(sec->clk);
+	} else {
+		clk_disable(sec->clk);
+		clk_put(sec->clk);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns reference clock frequency
+ */
+static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
+{
+	struct clk *ref_clk;
+	int refclk_freq = 0;
+
+	ref_clk = clk_get(sec->dev, "xusbxti");
+	if (IS_ERR(ref_clk)) {
+		dev_err(sec->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	switch (clk_get_rate(ref_clk)) {
+	case 12 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+		break;
+	default:
+	case 48 * MHZ:
+		/* default reference clock */
+		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+		break;
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void sec_usbphy_enable(struct sec_usbphy *sec)
+{
+	void __iomem *regs = sec->regs;
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	/* set clock frequency for PLL */
+	phyclk = sec_usbphy_get_refclk_freq(sec);
+	phypwr = readl(regs + S3C_PHYPWR);
+	rstcon = readl(regs + S3C_RSTCON);
+
+	switch (sec->cpu_type) {
+	case TYPE_S3C64XX:
+		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
+		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+	default:
+		break;
+	}
+
+	writel(phyclk, regs + S3C_PHYCLK);
+	/* set to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+	/* reset all ports of PHY and Link */
+	writel(rstcon, regs + S3C_RSTCON);
+	udelay(10);
+	rstcon &= ~S3C_RSTCON_PHY;
+	writel(rstcon, regs + S3C_RSTCON);
+}
+
+static void sec_usbphy_disable(struct sec_usbphy *sec)
+{
+	void __iomem *regs = sec->regs;
+	u32 phypwr;
+
+	phypwr = readl(regs + S3C_PHYPWR);
+
+	switch (sec->cpu_type) {
+	case TYPE_S3C64XX:
+		phypwr |= S3C_PHYPWR_NORMAL_MASK;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
+	default:
+		break;
+	}
+
+	/* unset to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int sec_usbphy_init(struct usb_phy *phy)
+{
+	struct sec_usbphy *sec;
+	int ret = 0;
+
+	sec = phy_to_sec(phy);
+
+	/* Enable the phy clock */
+	ret = sec_usbphy_clk_control(sec, true);
+	if (ret) {
+		dev_err(sec->dev, "phy clock enable failed\n");
+		return ret;
+	}
+
+	/* Disable phy isolation */
+	if (sec->plat && sec->plat->pmu_isolation)
+		sec->plat->pmu_isolation(false);
+
+	/* Initialize usb phy registers */
+	sec_usbphy_enable(sec);
+	return ret;
+}
+
+/*
+ * The function passed to the usb driver for phy shutdown
+ */
+static void sec_usbphy_shutdown(struct usb_phy *phy)
+{
+	struct sec_usbphy *sec;
+
+	sec = phy_to_sec(phy);
+
+	/* De-initialize usb phy registers */
+	sec_usbphy_disable(sec);
+
+	/* Enable phy isolation */
+	if (sec->plat && sec->plat->pmu_isolation)
+		sec->plat->pmu_isolation(true);
+
+	/* Disable the phy clock */
+	sec_usbphy_clk_control(sec, false);
+}
+
+static const struct of_device_id sec_usbphy_dt_match[];
+
+static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	int data;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
+		data = (int) match->data;
+		return data;
+	}
+#endif
+	return platform_get_device_id(pdev)->driver_data;
+}
+
+static int __devinit sec_usbphy_probe(struct platform_device *pdev)
+{
+	struct sec_usbphy *sec;
+	struct s3c_usbphy_plat *pdata;
+	struct device *dev = &pdev->dev;
+	struct resource *phy_mem;
+	void __iomem	*phy_base;
+	int	ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
+		return -EINVAL;
+	}
+
+	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!phy_mem) {
+		dev_err(dev, "%s: missing mem resource\n", __func__);
+		return -ENODEV;
+	}
+
+	phy_base = devm_request_and_ioremap(dev, phy_mem);
+	if (!phy_base) {
+		dev_err(dev, "%s: register mapping failed\n", __func__);
+		return -ENXIO;
+	}
+
+	sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
+	if (!sec)
+		return -ENOMEM;
+
+	sec->dev		= &pdev->dev;
+	sec->plat		= pdata;
+	sec->regs		= phy_base;
+	sec->phy.dev		= sec->dev;
+	sec->phy.label		= "sec-usbphy";
+	sec->phy.init		= sec_usbphy_init;
+	sec->phy.shutdown	= sec_usbphy_shutdown;
+	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);
+
+	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, sec);
+
+	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
+err:
+	return ret;
+}
+
+static int __exit sec_usbphy_remove(struct platform_device *pdev)
+{
+	struct sec_usbphy *sec = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&sec->phy);
+
+	if (sec->clk) {
+		clk_put(sec->clk);
+		sec->clk = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id sec_usbphy_dt_match[] = {
+	{
+		.compatible = "samsung,s3c64xx-usbphy",
+		.data = (void *)TYPE_S3C64XX,
+	}, {
+		.compatible = "samsung,exynos4210-usbphy",
+		.data = (void *)TYPE_EXYNOS4210,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
+#else
+#define sec_usbphy_dt_match NULL
+#endif
+
+static struct platform_device_id sec_usbphy_driver_ids[] = {
+	{
+		.name		= "s3c64xx-usbphy",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "exynos4210-usbphy",
+		.driver_data	= TYPE_EXYNOS4210,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
+
+static struct platform_driver sec_usbphy_driver = {
+	.probe		= sec_usbphy_probe,
+	.remove		= __devexit_p(sec_usbphy_remove),
+	.id_table	= sec_usbphy_driver_ids,
+	.driver		= {
+		.name	= "sec-usbphy",
+		.owner	= THIS_MODULE,
+		.of_match_table = sec_usbphy_dt_match,
+	},
+};
+
+static int __init sec_usbphy_driver_init(void)
+{
+	return platform_driver_register(&sec_usbphy_driver);
+}
+subsys_initcall(sec_usbphy_driver_init);
+
+static void __exit sec_usbphy_driver_exit(void)
+{
+	return platform_driver_unregister(&sec_usbphy_driver);
+}
+module_exit(sec_usbphy_driver_exit);
+
+MODULE_DESCRIPTION("Samsung USB phy controller");
+MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sec-usbphy");
diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
new file mode 100644
index 0000000..06e81d4
--- /dev/null
+++ b/drivers/usb/phy/sec_usbphy.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SEC_USBPHY_H
+#define __SEC_USBPHY_H
+
+#define S3C_PHYPWR				(0x00)
+
+#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
+#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
+#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
+
+#define S3C_PHYCLK				(0x04)
+
+#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
+#define S3C_PHYCLK_EXT_OSC			(1 << 5)
+#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
+#define S3C_PHYCLK_ID_PULL			(1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
+#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
+
+#define S3C_RSTCON				(0x08)
+
+#define S3C_RSTCON_PHYCLK			(1 << 2)
+#define S3C_RSTCON_HCLK				(1 << 1)
+#define S3C_RSTCON_PHY				(1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#endif /* __SEC_USBPHY_H */
diff --git a/include/linux/platform_data/s3c-hsotg.h b/include/linux/platform_data/s3c-hsotg.h
index 8b79e09..25ed31e 100644
--- a/include/linux/platform_data/s3c-hsotg.h
+++ b/include/linux/platform_data/s3c-hsotg.h
@@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
 	int (*phy_exit)(struct platform_device *pdev, int type);
 };
 
+struct s3c_usbphy_plat {
+	void (*pmu_isolation)(int on);
+};
+
 extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
+extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
 
 #endif /* __LINUX_USB_S3C_HSOTG_H */
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  1 09:05:48 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:48 +0530
Subject: [PATCH 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1343826351-8756-3-git-send-email-p.paneri@samsung.com>

Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 drivers/usb/gadget/s3c-hsotg.c |   38 ++++++++++++++++++++++++++++----------
 1 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b13e0bb..f4ba9a3 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <mach/map.h>
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
  * struct s3c_hsotg - driver state.
  * @dev: The parent device supplied to the probe function
  * @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transeiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
  * @regs: The memory area mapped for accessing registers.
  * @irq: The IRQ number we are using
  * @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
+	struct usb_phy		*phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
-	if (hsotg->plat->phy_init)
+
+	if (hsotg->phy)
+		usb_phy_init(hsotg->phy);
+	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
 
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 {
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
-	if (hsotg->plat->phy_exit)
+	if (hsotg->phy)
+		usb_phy_shutdown(hsotg->phy);
+	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
 
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+	struct usb_phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,25 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 	int ret;
 	int i;
 
-	plat = pdev->dev.platform_data;
-	if (!plat) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
-
 	hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
 	if (!hsotg) {
 		dev_err(dev, "cannot get memory\n");
 		return -ENOMEM;
 	}
 
+	phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+	if (!phy) {
+		/* Fallback for platform data */
+		plat = pdev->dev.platform_data;
+		if (!plat) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -ENODEV;
+		} else
+			hsotg->plat = plat;
+	} else
+		hsotg->phy = phy;
+
 	hsotg->dev = dev;
-	hsotg->plat = plat;
 
 	hsotg->clk = clk_get(&pdev->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
@@ -3689,6 +3704,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
 	s3c_hsotg_phy_disable(hsotg);
 	regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
 
+	if (hsotg->phy)
+		devm_usb_put_phy(&pdev->dev, hsotg->phy);
+
 	clk_disable_unprepare(hsotg->clk);
 	clk_put(hsotg->clk);
 
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  1 09:05:49 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:49 +0530
Subject: [PATCH 3/5] ARM: S3C64XX: Removing old phy setup code
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1343826351-8756-4-git-send-email-p.paneri@samsung.com>

This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |    2 -
 arch/arm/mach-s3c64xx/mach-smartq.c   |    2 -
 arch/arm/mach-s3c64xx/mach-smdk6410.c |    2 -
 arch/arm/mach-s3c64xx/setup-usb-phy.c |   79 ---------------------------------
 4 files changed, 0 insertions(+), 85 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d..984146e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -767,7 +767,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -793,7 +792,6 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de..3647202 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,7 +187,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
 	},
 };
 
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
 
 static int __init smartq_lcd_setup_gpio(void)
 {
@@ -385,7 +384,6 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
-	s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index df3103d..ceec1a9 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -628,7 +628,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -658,7 +657,6 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
  *
  */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <mach/regs-sys.h>
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
-	struct clk *xusbxti;
-	u32 phyclk;
-
-	writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	/* set clock frequency for PLL */
-	phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-	xusbxti = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti && !IS_ERR(xusbxti)) {
-		switch (clk_get_rate(xusbxti)) {
-		case 12 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
-		}
-		clk_put(xusbxti);
-	}
-
-	/* TODO: select external clock/oscillator */
-	writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-	/* set to normal OTG PHY */
-	writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-	mdelay(1);
-
-	/* reset OTG PHY and Link */
-	writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-			S3C_RSTCON);
-	udelay(20);	/* at-least 10uS */
-	writel(0, S3C_RSTCON);
-
-	return 0;
-}
-
-static int s3c_usb_otgphy_exit(struct platform_device *pdev)
-{
-	writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-				S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-	writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_init(pdev);
-
-	return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_exit(pdev);
-
-	return -EINVAL;
-}
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  1 09:05:50 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:50 +0530
Subject: [PATCH 4/5] ARM: S3C64XX: Enabling sec_usbphy driver
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1343826351-8756-5-git-send-email-p.paneri@samsung.com>

Adding platform device for sec_usbphy driver. Enabling it for s3c64xx
based machines using s3c-hsotg.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c        |    3 ++
 arch/arm/mach-s3c64xx/mach-smartq.c          |    4 +++
 arch/arm/mach-s3c64xx/mach-smdk6410.c        |    3 ++
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
 arch/arm/plat-samsung/devs.c                 |   32 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h    |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
 8 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
 
 #define S3C64XX_PA_NAND		(0x70200000)
 #define S3C64XX_PA_FB		(0x77100000)
+#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
@@ -113,6 +114,7 @@
 #define S3C_PA_FB		S3C64XX_PA_FB
 #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
 #define S3C_PA_RTC		S3C64XX_PA_RTC
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 #define S3C_PA_SPI0		S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 984146e..88c4671 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -337,6 +337,7 @@ static struct platform_device wallvdd_device = {
 };
 
 static struct platform_device *crag6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc2,
 	&s3c_device_i2c0,
@@ -767,6 +768,7 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
+static struct s3c_usbphy_plat crag6410_usbphy_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -792,6 +794,7 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&crag6410_usbphy_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 3647202..97751d5 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -235,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata = {
 };
 
 static struct platform_device *smartq_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
 	&s3c_device_hsmmc0,	/* ... then the external SD card */
 	&s3c_device_hsmmc2,
@@ -381,9 +382,12 @@ void __init smartq_map_io(void)
 	smartq_lcd_mode_set();
 }
 
+static struct s3c_usbphy_plat smartq_usbphy_pdata;
+
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
+	s3c_usbphy_set_platdata(&smartq_usbphy_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ceec1a9..c5ea838 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -264,6 +264,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 #ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
 #endif
@@ -628,6 +629,7 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
+static struct s3c_usbphy_plat smdk6410_usbphy_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -657,6 +659,7 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&smdk6410_usbphy_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 7a09553..3aee778 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,3 +9,17 @@
  *
  */
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	} else {
+		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	}
+}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 6303974..77a35f1 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1343,6 +1343,35 @@ struct platform_device s5p_device_mixer = {
 
 /* USB */
 
+#ifdef CONFIG_S3C_DEV_USB_HSOTG
+/* USB PHY*/
+static struct resource s3c_usbphy_resource[] = {
+	[0] = {
+		.start = S3C_PA_USB_PHY,
+		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device s3c_device_usbphy = {
+	.name		= "s3c64xx-usbphy",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(s3c_usbphy_resource),
+	.resource	= s3c_usbphy_resource,
+};
+
+void __init s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd)
+{
+	struct s3c_usbphy_plat *npd;
+
+	npd = s3c_set_platdata(pd, sizeof(struct s3c_usbphy_plat),
+			&s3c_device_usbphy);
+
+	if (!npd->pmu_isolation)
+		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
+}
+#endif
+
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
 	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
@@ -1449,6 +1478,8 @@ struct platform_device s3c_device_usb_hsotg = {
 	},
 };
 
+#ifndef CONFIG_ARCH_S3C64XX
+/* TODO: To be removed later. Currently only S3C64XX is platform data free */
 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 {
 	struct s3c_hsotg_plat *npd;
@@ -1461,6 +1492,7 @@ void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 	if (!npd->phy_exit)
 		npd->phy_exit = s5p_usb_phy_exit;
 }
+#endif
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 61ca2f3..cbb079a 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -71,6 +71,7 @@ extern struct platform_device s3c_device_spi1;
 extern struct platform_device s3c_device_ts;
 extern struct platform_device s3c_device_timer[];
 extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usbphy;
 extern struct platform_device s3c_device_usb_hsotg;
 extern struct platform_device s3c_device_usb_hsudc;
 extern struct platform_device s3c_device_wdt;
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..165ffe7 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern void s5p_usb_phy_pmu_isolation(int on);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  1 09:05:51 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 01 Aug 2012 18:35:51 +0530
Subject: [PATCH 5/5] ARM: Exynos4210: Enabling sec_usbphy driver
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1343826351-8756-6-git-send-email-p.paneri@samsung.com>

Adding usbphy node for Exynos4210 along with the platform data.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi       |    5 +++++
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c  |    8 ++++++++
 arch/arm/mach-exynos/setup-usb-phy.c    |   13 +++++++++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee..fc9e00f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -45,6 +45,11 @@
 		interrupts = <0 44 0>, <0 45 0>;
 	};
 
+	usbphy at 125B0000 {
+		compatible = "samsung,exynos4210-usbphy";
+		reg = <0x125B0000 0x100>;
+	};
+
 	keypad at 100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89..a265634 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -231,6 +231,7 @@
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG		EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY			EXYNOS4_PA_HSPHY
 
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e7e9743..9126637 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -20,9 +21,14 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct s3c_usbphy_plat exynos4_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -57,6 +63,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 				"s3c2440-i2c.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+			"s3c-usbphy", &exynos4_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f..3fca203 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -193,3 +193,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 	return -EINVAL;
 }
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			& ~S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	} else {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			| S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	}
+}
-- 
1.7.1



From padma.kvr at gmail.com  Wed Aug  1 09:09:44 2012
From: padma.kvr at gmail.com (Padma Venkat)
Date: Wed, 1 Aug 2012 18:39:44 +0530
Subject: [PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
In-Reply-To: <031501cd6f98$dd67c550$98374ff0$%kim@samsung.com>
References: <1343218056-30432-1-git-send-email-padma.v@samsung.com>
 <031501cd6f98$dd67c550$98374ff0$%kim@samsung.com>
Message-ID: <CAAgF-Bdp817_RD3n6Sdo9zi=OrB4-Uiu5PDt4UB1BL-f0M4aJg@mail.gmail.com>

Hi,

On Wed, Aug 1, 2012 at 9:21 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Padmavathi Venna wrote:
>>
>> Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
>> board specific. So this patch adds a function to set the required
>> audio codec clk frequency from machine file.
>>
>> This patch also adds all the required clock instances for audio
>> subsystem and adds the clock alias names for i2sclk and busclk.
>>
>> Signed-off-by: Taylor Hutt <thutt at chromium.org>
>> Signed-off-by: sangsu4u.park <sangsu4u.park at samsung.com>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>  arch/arm/mach-exynos/clock-exynos5.c           |  129
>> ++++++++++++++++++++++++
>>  arch/arm/mach-exynos/common.h                  |    1 +
>>  arch/arm/mach-exynos/include/mach/regs-audss.h |   12 ++
>>  arch/arm/mach-exynos/mach-exynos5-dt.c         |    1 +
>>  4 files changed, 143 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
>> exynos/clock-exynos5.c
>> index 774533c..681450a 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -20,10 +20,13 @@
>>  #include <plat/pll.h>
>>  #include <plat/s5p-clock.h>
>>  #include <plat/clock-clksrc.h>
>> +#include <plat/devs.h>
>
> Why do we need above on this patch?
It's by mistake. I will remove this line in the next patch set.
>
>>  #include <plat/pm.h>
>> +#include <plat/cpu.h>
>
> Same as above.
It's by mistake. I will remove this line in the next patch set.
>
>>
>>  #include <mach/map.h>
>>  #include <mach/regs-clock.h>
>> +#include <mach/regs-audss.h>
>
> See below my comment.
>
>>  #include <mach/sysmmu.h>
>>
>>  #include "common.h"
>> @@ -106,6 +109,16 @@ static struct clk exynos5_clk_sclk_usbphy = {
>>       .rate           = 48000000,
>>  };
>>
>> +struct clk exynos5_clk_audiocdclk0 = {
>> +     .id = -1,
>> +     .name   = "audiocdclk",
>> +};
>> +
>> +void exynos5_set_audiocdclk_rate(unsigned long rate)
>> +{
>> +     clk_default_setrate(&exynos5_clk_audiocdclk0, rate);
>> +}
>> +
>>  static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
>>  {
>>       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
>> @@ -171,6 +184,16 @@ static int exynos5_clk_ip_gps_ctrl(struct clk *clk,
>> int enable)
>>       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
>>  }
>>
>> +static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
>> +{
>> +     return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable);
>> +}
>> +
>> +static int exynos5_clk_audss_ctrl(struct clk *clk, int enable)
>> +{
>> +     return s5p_gatectrl(EXYNOS_CLKGATE_AUDSS, clk, enable);
>> +}
>> +
>>  static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
>>  {
>>       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
>> @@ -635,6 +658,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>               .ctrlbit        = (1 << 3),
>>       }, {
>>               .name           = "iis",
>> +             .devname        = "samsung-i2s.0",
>> +             .enable         = exynos5_clk_audss_ctrl,
>> +             .ctrlbit        = (3 << 2),
>> +     }, {
>> +             .name           = "iis",
>>               .devname        = "samsung-i2s.1",
>>               .enable         = exynos5_clk_ip_peric_ctrl,
>>               .ctrlbit        = (1 << 20),
>> @@ -645,6 +673,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>               .ctrlbit        = (1 << 21),
>>       }, {
>>               .name           = "pcm",
>> +             .devname        = "samsung-pcm.0",
>> +             .enable         = exynos5_clk_audss_ctrl,
>> +             .ctrlbit        = (3 << 4),
>> +     }, {
>> +             .name           = "pcm",
>>               .devname        = "samsung-pcm.1",
>>               .enable         = exynos5_clk_ip_peric_ctrl,
>>               .ctrlbit        = (1 << 22),
>> @@ -870,6 +903,95 @@ static struct clk exynos5_init_clocks_on[] = {
>>       }
>>  };
>>
>> +static struct clk *clkset_sclk_audio0_list[] = {
>> +     [0] = &exynos5_clk_audiocdclk0,
>> +     [1] = &clk_ext_xtal_mux,
>> +     [2] = &exynos5_clk_sclk_hdmi27m,
>> +     [3] = &exynos5_clk_sclk_dptxphy,
>> +     [4] = &exynos5_clk_sclk_usbphy,
>> +     [5] = &exynos5_clk_sclk_hdmiphy,
>> +     [6] = &exynos5_clk_mout_mpll.clk,
>> +     [7] = &exynos5_clk_mout_epll.clk,
>> +     [8] = &exynos5_clk_sclk_vpll.clk,
>> +     [9] = &exynos5_clk_mout_cpll.clk,
>> +};
>> +
>> +static struct clksrc_sources exynos5_clkset_sclk_audio0 = {
>> +     .sources        = clkset_sclk_audio0_list,
>> +     .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
>> +};
>> +
>> +static struct clksrc_clk exynos5_clk_sclk_audio0 = {
>> +     .clk    = {
>> +             .name           = "audio-bus",
>
> sclk_audio?
Yes. The name of this clock instance can be changed to sclk_audio for
better understanding.
>
>> +             .enable         = exynos5_clksrc_mask_maudio_ctrl,
>> +             .ctrlbit        = (1 << 0),
>> +     },
>> +     .sources = &exynos5_clkset_sclk_audio0,
>> +     .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
>> +     .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
>> +};
>> +
>> +static struct clk *exynos5_clkset_mout_audss_list[] = {
>> +     &clk_ext_xtal_mux,
>> +     &clk_fout_epll,
>> +};
>> +
>> +static struct clksrc_sources clkset_mout_audss = {
>> +     .sources        = exynos5_clkset_mout_audss_list,
>> +     .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_audss_list),
>> +};
>> +
>> +static struct clksrc_clk exynos5_clk_mout_audss = {
>> +     .clk    = {
>> +             .name           = "mout_audss",
>> +     },
>> +     .sources = &clkset_mout_audss,
>> +     .reg_src = { .reg = EXYNOS_CLKSRC_AUDSS, .shift = 0, .size = 1 },
>> +};
>> +
>> +static struct clk *exynos5_clkset_sclk_audss_list[] = {
>> +     &exynos5_clk_mout_audss.clk,
>> +     &exynos5_clk_audiocdclk0,
>> +     &exynos5_clk_sclk_audio0.clk,
>> +};
>> +
>> +static struct clksrc_sources exynos5_clkset_sclk_audss = {
>> +     .sources        = exynos5_clkset_sclk_audss_list,
>> +     .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_audss_list),
>> +};
>> +
>> +static struct clksrc_clk exynos5_clk_sclk_audss_i2s = {
>
> exynos5_clk_sclk_i2s?
As these clock instances are from AudioSS clock controller, these are
named like that. If not looking good, I will change this to
exynos5_clk_sclk_i2s0
>
>> +     .clk            = {
>> +             .name           = "i2sclk",
>
> sclk_i2s?
hmm, as per the user manual the instance of this clock in clock
controller of AudioSS has the name "i2sclk". So this clock is named
like that.
>
>> +             .devname        = "samsung-i2s.0",
>> +             .enable         = exynos5_clk_audss_ctrl,
>> +             .ctrlbit        = (1 << 3),
>> +     },
>> +     .sources = &exynos5_clkset_sclk_audss,
>> +     .reg_src = { .reg = EXYNOS_CLKSRC_AUDSS, .shift = 2, .size = 2 },
>
> The parent of sclk_i2s0 is sclk_audio0? So why do we need above?
No. The parent of this clock is not only sclk_audio0. It has 3 source
mux. one is MOUTASS,IISCDCLK0,SCLK_AUDIO0.
>
>> +     .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 8, .size = 4 },
>> +};
>> +
>> +static struct clksrc_clk exynos5_clk_dout_audss_srp = {
>
> exynos5_clk_dout_srp?
As it is instance in audio sub system clock controller it is named like that.
>
>> +     .clk    = {
>> +             .name           = "dout_srp",
>> +             .parent         = &exynos5_clk_mout_audss.clk,
>> +     },
>> +     .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 0, .size = 4 },
>> +};
>> +
>> +static struct clksrc_clk exynos5_clk_sclk_audss_bus = {
>
> exynos5_clk_sclk_bus?
Same as above.
>
>> +     .clk    = {
>> +             .name           = "busclk",
>
> sclk_bus?
As per the user manual the instance of this clock in clock controller
of AudioSS has the name "busclk". So this clock is named like that.
>
>> +             .devname        = "samsung-i2s.0",
>> +             .parent         = &exynos5_clk_dout_audss_srp.clk,
>> +             .enable         = exynos5_clk_audss_ctrl,
>> +             .ctrlbit        = (1 << 2),
>> +     },
>> +     .reg_div = { .reg = EXYNOS_CLKDIV_AUDSS, .shift = 4, .size = 4 },
>> +};
>> +
>>  static struct clk exynos5_clk_pdma0 = {
>>       .name           = "dma",
>>       .devname        = "dma-pl330.0",
>> @@ -1240,6 +1362,9 @@ static struct clksrc_clk *exynos5_sysclks[] = {
>>       &exynos5_clk_mdout_spi0,
>>       &exynos5_clk_mdout_spi1,
>>       &exynos5_clk_mdout_spi2,
>> +     &exynos5_clk_mout_audss,
>> +     &exynos5_clk_dout_audss_srp,
>> +     &exynos5_clk_sclk_audio0,
>>  };
>>
>>  static struct clk *exynos5_clk_cdev[] = {
>> @@ -1257,6 +1382,8 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = {
>>       &exynos5_clk_sclk_mmc1,
>>       &exynos5_clk_sclk_mmc2,
>>       &exynos5_clk_sclk_mmc3,
>> +     &exynos5_clk_sclk_audss_bus,
>> +     &exynos5_clk_sclk_audss_i2s,
>>  };
>>
>>  static struct clk_lookup exynos5_clk_lookup[] = {
>> @@ -1274,6 +1401,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
>>       CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
>>       CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
>>       CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
>> +     CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0",
>> &exynos5_clk_sclk_audss_i2s.clk),
>> +     CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1",
>> &exynos5_clk_sclk_audss_bus.clk),
>
> Maybe 'samsung-i2s.1' ?
No. I2S controller 0 has mux for RCLK source clocks. These are the
alias names for source clks of RCLK in I2S controller0. So it should
be 'samsung-i2s.0'.
>
> +       CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1",
> &exynos5_clk_sclk_audss_bus.clk),
>
>>  };
>>
>>  static unsigned long exynos5_epll_get_rate(struct clk *clk)
>> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
>> index aed2eeb..1bf25a5 100644
>> --- a/arch/arm/mach-exynos/common.h
>> +++ b/arch/arm/mach-exynos/common.h
>> @@ -13,6 +13,7 @@
>>  #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
>>
>>  extern struct sys_timer exynos4_timer;
>> +extern void exynos5_set_audiocdclk_rate(unsigned long rate);
>>
>>  void exynos_init_io(struct map_desc *mach_desc, int size);
>>  void exynos4_init_irq(void);
>> diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h
>> b/arch/arm/mach-exynos/include/mach/regs-audss.h
>> index ca5a8b6..4bc9bf9 100644
>> --- a/arch/arm/mach-exynos/include/mach/regs-audss.h
>> +++ b/arch/arm/mach-exynos/include/mach/regs-audss.h
>> @@ -15,4 +15,16 @@
>>
>>  #define EXYNOS4_AUDSS_INT_MEM        (0x03000000)
>>
>> +#define EXYNOS_AUDSSREG(x)           (S5P_VA_AUDSS + (x))
>> +
>> +#define EXYNOS_CLKSRC_AUDSS_OFFSET   0x0
>> +#define EXYNOS_CLKDIV_AUDSS_OFFSET   0x4
>> +#define EXYNOS_CLKGATE_AUDSS_OFFSET  0x8
>> +
>> +#define EXYNOS_CLKSRC_AUDSS          (EXYNOS_AUDSSREG \
>> +                                     (EXYNOS_CLKSRC_AUDSS_OFFSET))
>> +#define EXYNOS_CLKDIV_AUDSS          (EXYNOS_AUDSSREG \
>> +                                     (EXYNOS_CLKDIV_AUDSS_OFFSET))
>> +#define EXYNOS_CLKGATE_AUDSS         (EXYNOS_AUDSSREG \
>> +                                     (EXYNOS_CLKGATE_AUDSS_OFFSET))
>
> Firstly, I don't know why we need to define XXX_OFFSET, how about just use
> the value directly?
Yes. I will remove the XXX_OFFSET definitions.
>
> And you said, above definitions would be in mach/regs-clock.h or regarding
> clock header file if they are for clock.
As these are related to AUDSS clock controller a seperate file is
created for that. If not required I will add these definitions in
regs-clock.h.
>
>>  #endif /* _PLAT_REGS_AUDSS_H */
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-
>> exynos/mach-exynos5-dt.c
>> index ef770bc..c334eea 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -69,6 +69,7 @@ static void __init exynos5250_dt_machine_init(void)
>>  {
>>       of_platform_populate(NULL, of_default_bus_match_table,
>>                               exynos5250_auxdata_lookup, NULL);
>> +     exynos5_set_audiocdclk_rate(16934400);
>
> As you commented, the value of clock can be changed according to the board,
> and this file, mach-exynos5-dt.c is not only for smdk5250, now there is no
> board for exynos5250 though.
Please suggest me some file where I can call this function then.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.

Thanks for your review.

Best Regards
Padma
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From padma.kvr at gmail.com  Wed Aug  1 09:12:03 2012
From: padma.kvr at gmail.com (Padma Venkat)
Date: Wed, 1 Aug 2012 18:42:03 +0530
Subject: [alsa-devel] [PATCH 1/2] ASOC: SAMSUNG: Add DT support for i2s
In-Reply-To: <08da01cd6fbf$cd9b5c00$68d21400$@com>
References: <1343218170-30483-1-git-send-email-padma.v@samsung.com>
 <1343218170-30483-2-git-send-email-padma.v@samsung.com>
 <08da01cd6fbf$cd9b5c00$68d21400$@com>
Message-ID: <CAAgF-Bf7kJeA6gdy7Ri_bA8AHxSWwp5i8Tv0pWSXumebM5NX7g@mail.gmail.com>

Hi,
On Wed, Aug 1, 2012 at 1:59 PM, Sangbeom Kim <sbkim73 at samsung.com> wrote:
> Hi,
> On Wednesday, July 25, 2012 9:09 PM, Padmavathi Venna wrote:
>
>> Add support for device based discovery.
>>
> Currently, I'm reviewing your patch set.
> Your patch can support device tree for Samsung's i2s.
> But I wonder that Your patch can support non-dt too,
> So, Please test your patch on non-dt environment.
> It looks unclear handling of clock source.
> After code review, I will give you more detail comments,
Okey. I will test these patches in non-dt environment.
>
> Thanks,
> Sangbeom.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From padma.kvr at gmail.com  Wed Aug  1 09:15:20 2012
From: padma.kvr at gmail.com (Padma Venkat)
Date: Wed, 1 Aug 2012 18:45:20 +0530
Subject: [PATCH] ARM: EXYNOS: Add static mapping for EXYNOS Audio Subsystem
In-Reply-To: <030e01cd6f95$68272ae0$387580a0$%kim@samsung.com>
References: <1343218009-30400-1-git-send-email-padma.v@samsung.com>
 <030e01cd6f95$68272ae0$387580a0$%kim@samsung.com>
Message-ID: <CAAgF-BcoSoUGjPaFaa2Jd=j+8DYSZk0u7dY65dBWzvnHF0fR9g@mail.gmail.com>

On Wed, Aug 1, 2012 at 8:56 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Padmavathi Venna wrote:
>>
>> The CMU of EXYNOS can't control Audio Subsystem's clocks because
>> AUDSS SFRs aren't located in CMU. But AUDSS is a kind of CMU for
>> Audio Subsystem and need to use clock framework. This mapping
>> address will be used for AUDSS clock control.
>>
>> Signed-off-by: sangsu4u.park <sangsu4u.park at samsung.com>
>
> Maybe Sangsu Park?
>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>  arch/arm/mach-exynos/common.c                |    5 +++++
>>  arch/arm/mach-exynos/include/mach/map.h      |    1 +
>>  arch/arm/plat-samsung/include/plat/map-s5p.h |    2 ++
>>  3 files changed, 8 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
>> index 4eb39cd..4070c79 100644
>> --- a/arch/arm/mach-exynos/common.c
>> +++ b/arch/arm/mach-exynos/common.c
>> @@ -109,6 +109,11 @@ static struct map_desc exynos_iodesc[] __initdata = {
>>               .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
>>               .length         = SZ_4K,
>>               .type           = MT_DEVICE,
>> +     }, {
>> +             .virtual        = (unsigned long)S5P_VA_AUDSS,
>> +             .pfn            = __phys_to_pfn(EXYNOS_PA_AUDSS),
>> +             .length         = SZ_4K,
>> +             .type           = MT_DEVICE,
>>       },
>>  };
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
>> exynos/include/mach/map.h
>> index 5cf7d91..9c044a0 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -39,6 +39,7 @@
>>
>>  #define EXYNOS4_PA_G2D                       0x12800000
>>
>> +#define EXYNOS_PA_AUDSS                      0x03810000
>>  #define EXYNOS_PA_I2S0                       0x03830000
>>  #define EXYNOS4_PA_I2S1                      0xE2100000
>>  #define EXYNOS4_PA_I2S2                      0xE2A00000
>> diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-
>> samsung/include/plat/map-s5p.h
>> index c2d7bda..3558277 100644
>> --- a/arch/arm/plat-samsung/include/plat/map-s5p.h
>> +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
>> @@ -40,6 +40,8 @@
>>  #define S5P_VA_GIC_CPU               S3C_ADDR(0x02810000)
>>  #define S5P_VA_GIC_DIST              S3C_ADDR(0x02820000)
>>
>> +#define S5P_VA_AUDSS         S3C_ADDR(0x02910000)
>
> Is there any reason to use the offset, 0x02910000?
>
> [...]
>
> And I think, this patch should be patch-set with your '[PATCH] ARM: EXYNOS:
> Add clocks for EXYNOS Audio Subsystem.'
Okay. In the next version I will send it along with clock support for audio.
>
> Thanks.
>
> Best regards,
> Kgene.

Thanks&Regards
Padma
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From broonie at opensource.wolfsonmicro.com  Wed Aug  1 09:20:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 14:20:23 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <5018D880.5090306@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
 <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
Message-ID: <20120801132022.GS11892@opensource.wolfsonmicro.com>

On Wed, Aug 01, 2012 at 08:19:28AM +0100, Lee Jones wrote:
> On 31/07/12 16:18, Mark Brown wrote:

> >I'm not going to apply this patch.  This isn't a vendor BSP, we
> >shouldn't be putting random hacks like this in core code.

> BSP kernel or otherwise, it still seems wrong to me to fail and
> entire audio driver just because of a broken link.

No, really.  Random disconnections in the DAPM graph are just endless
pain from a support and debug point of view.  This isn't something that
randomly breaks on specific hardware where we'd expect random errors at
runtime, it's something that will never have worked - it seems clear
nobody tested the mainline submission.

It's very disappointing to see such an error exist, and even more
disappointing that there's no interest in fixing the driver.


From padma.kvr at gmail.com  Wed Aug  1 09:21:20 2012
From: padma.kvr at gmail.com (Padma Venkat)
Date: Wed, 1 Aug 2012 18:51:20 +0530
Subject: [PATCH] ARM: EXYNOS: Add I2S SFR base addresses
In-Reply-To: <030801cd6f92$55370570$ffa51050$%kim@samsung.com>
References: <0M7R00MY1GHTPK20@ms14.samsung.com>
 <030801cd6f92$55370570$ffa51050$%kim@samsung.com>
Message-ID: <CAAgF-Bd+R=a_AxE+CCBqT25Bzt5zMzqR0U3Jz60dRVO90MOcwA@mail.gmail.com>

On Wed, Aug 1, 2012 at 8:34 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> PADMAVATHI VENNA wrote:
>
> Padma, don't post with html styled :(
Sorry for the inconvenience. I will take care.
>
> And you need to check the regarding addresses as per Sachin commented.
Okay.
>
> Thanks.
>
> Best regards,
> Kgene.

Thanks&Regards
Padma
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> ------- Original Message -------
> Sender : Sachin Kamat<sachin.kamat at linaro.org>
> Date : Jul 26, 2012 13:41 (GMT+09:00)
> Title : Re: [PATCH] ARM: EXYNOS: Add I2S SFR base addresses
>
> On 25 July 2012 17:35, Padmavathi Venna wrote:
>> The base address of I2S 0 controller is similar in exynos4 and exynos5
>> platforms. So this patch defines a common macro for the I2S controller
>> 0 base address in both the platforms and use the same macro.
>>
>> This patch also defines the I2S controller 1,2 base addresses in exynos5
>> and correct the I2S controller 1 base address in exynos4
>>
>> Signed-off-by: Padmavathi Venna
>> ---
>>  arch/arm/mach-exynos/dev-audio.c        |    2 +-
>>  arch/arm/mach-exynos/include/mach/map.h |    6 ++++--
>>  2 files changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/dev-audio.c
> b/arch/arm/mach-exynos/dev-audio.c
>> index b33a5b6..5dbc9a2 100644
>> --- a/arch/arm/mach-exynos/dev-audio.c
>> +++ b/arch/arm/mach-exynos/dev-audio.c
>> @@ -62,7 +62,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
>>  };
>>
>>  static struct resource exynos4_i2s0_resource[] = {
>> -       [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
>> +       [0] = DEFINE_RES_MEM(EXYNOS_PA_I2S0, SZ_256),
>>         [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
>>         [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
>>         [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
>> index c72b675..5cf7d91 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -39,9 +39,11 @@
>>
>>  #define EXYNOS4_PA_G2D                 0x12800000
>>
>> -#define EXYNOS4_PA_I2S0                        0x03830000
>> -#define EXYNOS4_PA_I2S1                        0xE3100000
>> +#define EXYNOS_PA_I2S0                 0x03830000
>> +#define EXYNOS4_PA_I2S1                        0xE2100000
>>  #define EXYNOS4_PA_I2S2                        0xE2A00000
>
> As per the TRM, these addresses (I2S1 and I2S2) are 0x13960000 and
> 0x13970000 respectively on Exynos4412 SoC.
> Please verify.
> I didn't verify Exynos4412 before. I will send a new patch for this.
>
>
>> +#define EXYNOS5_PA_I2S1                        0x12D60000
>> +#define EXYNOS5_PA_I2S2                        0x12D70000
>>
>>  #define EXYNOS4_PA_PCM0                        0x03840000
>>  #define EXYNOS4_PA_PCM1                        0x13980000
>> --
>> 1.7.4.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
> linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From padma.kvr at gmail.com  Wed Aug  1 09:31:28 2012
From: padma.kvr at gmail.com (Padma Venkat)
Date: Wed, 1 Aug 2012 19:01:28 +0530
Subject: [PATCH] ASoC: Samsung: Update Kconfig for Exynos5250 and
 Exynos4412
In-Reply-To: <030901cd6f92$b5fc6da0$21f548e0$%kim@samsung.com>
References: <1343218351-30577-1-git-send-email-padma.v@samsung.com>
 <030901cd6f92$b5fc6da0$21f548e0$%kim@samsung.com>
Message-ID: <CAAgF-BfmVfiPZozRd_d5h0DHCypDrmk-5kN2N9un_UEN=qQmDQ@mail.gmail.com>

Hi,

On Wed, Aug 1, 2012 at 8:36 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Padmavathi Venna wrote:
>>
>> Update Kconfig file to support the Exynos5250 and Exynos4412
>>
>> Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>
>> Signed-off-by: Sangbeom Kim <sbkim73 at samsung.com>
>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>> ---
>>  sound/soc/samsung/Kconfig |    8 ++++----
>>  1 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
>> index fe3995c..d54e400 100644
>> --- a/sound/soc/samsung/Kconfig
>> +++ b/sound/soc/samsung/Kconfig
>> @@ -1,6 +1,6 @@
>>  config SND_SOC_SAMSUNG
>>       tristate "ASoC support for Samsung"
>> -     depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 ||
>> ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_EXYNOS4
>> +     depends on PLAT_SAMSUNG
>>       select S3C64XX_DMA if ARCH_S3C64XX
>>       select S3C2410_DMA if ARCH_S3C24XX
>>       help
>> @@ -63,7 +63,7 @@ config SND_SOC_SAMSUNG_SMDK_WM8580
>>
>>  config SND_SOC_SAMSUNG_SMDK_WM8994
>>       tristate "SoC I2S Audio support for WM8994 on SMDK"
>> -     depends on SND_SOC_SAMSUNG && (MACH_SMDKV310 || MACH_SMDKC210 ||
>> MACH_SMDK4212)
>> +     depends on SND_SOC_SAMSUNG && (MACH_SMDKV310 || MACH_SMDKC210 ||
>> MACH_SMDK4212 || MACH_SMDK4412 || SOC_EXYNOS5250)
>
> Well, do you think _really_ all board which has a EXYNOS5250 SoC is needed
> this config?
>
> I don't think so?
Yes. It is not required on all boards which has EXYNOS5250 SoC. I will
change this.
>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From arnd at arndb.de  Wed Aug  1 09:32:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 1 Aug 2012 13:32:01 +0000
Subject: [PATCH 5/6] ARM: ux500: Ensure probing of Audio devices when
 Device Tree is enabled
In-Reply-To: <5018DBEE.9090203@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <201207312054.13818.arnd@arndb.de> <5018DBEE.9090203@linaro.org>
Message-ID: <201208011332.02500.arnd@arndb.de>

On Wednesday 01 August 2012, Lee Jones wrote:
> > Looks like you're adding the same call to each of the three cases:
> > mop500, snowball and hrefv60+. How about moving it before or after
> > the if/elseif block?
> 
> The Snowball one is different 'mop500_msp_init' -> 'mop500_of_msp_init'.

Ah, I see. Is there a problem in always using mop500_of_msp_init then?
I would guess that this just means you'd have to put the msp into the
device tree files, which don't yet exist for mop500 and hrefv60.

	Arnd


From b-cousson at ti.com  Wed Aug  1 09:42:59 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 1 Aug 2012 15:42:59 +0200
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <50191F00.1040501@ti.com>
References: <50191F00.1040501@ti.com>
Message-ID: <50193263.8070907@ti.com>

Hi Vaibhav,

On 08/01/2012 02:20 PM, Vaibhav Hiremath wrote:
> Hi,
> 
> In OMAP world, we have omap_device layer, which exports api's like
> omap_device_build() to create and register platform_device to the
> kernel. This layer understands hwmod infrastructure and parses all the
> platform specific information from it.
> Now with DT migration, the same thing is achieved using a notifier,
> which in turn omap_device_build_from_dt(), which in turn does same thing.
> 
> One of the thing which is happening in both execution path is, creating
> alias for functional clock (hwmod_data->main_clk) for each device
> getting created with the con_id = "fck".
> 
> Now the problem with this is,
> 
> The clk_get() api will not work, unless we pass both the arguments (dev,
> con_id) properly. Now expecting driver to always label con_id with "fck"
> is undesirable, as the same driver can be reused on multiple platforms,
> which can be non-omap and/or non-ti platforms.
> Also we have multiple examples where driver simply calls (which is right)
> 
> clk = clk_get(&pdev->dev, NULL);

Mmm, I don't know, but even if this is right, shouldn't we avoid such
usage. It might be better to be explicit than assuming that the IP will
always have an unique clock.
Some IP does have several inputs that might or not be connected
depending or the integration or on the version. So even if only one
clock is useful at some point it will not always be true.
We had similar issue with the IRQ lines in the past.

> This would fail on OMAP platforms, unless you modify clockxxx_data.c
> file with,
> 
> CLK("<device>",  NULL,           &xxx_fck,    CK_34XX),
> 
> 
> Devices specially with only one clock source always prefer not to
> specify con_id.

How many devices do you have with only one clock source? Could you
provide the list of drivers that assume that?

Most IPs in OMAP does have a fck and an ick so that does not seems nice
or even consistent to me to do a clk_get(&pdev->dev, NULL) for "fck" and
clk_get(&pdev->dev, "ick") for the ick.

> And it seems wrong thing, as across platforms IP integration can be very
> different and you can not expect to change the clock-tree table always.

FWIW, that table is done for that exact purpose. And we introduced the
automatic "fck" alias creation mainly to make things easier, but that
method is still very valid, and if the default alias is not good enough
for the driver nothing should prevent you to create a new one.

> So the option here we have is,
> 
> 1. Instead of creating alias with "fck", create an alias only with dev
> pointer, that means con_id = NULL.
> I have already tested this and it works on AM33xx platform.

Do you mean assuming that the fck is always the clock with a NULL
con_id? And any other clocks for that device will have thus to use a
explicit name?

> 2. Add a new flag inside hwmod or omap_device, so that it can be read at
> omap_device layer and based on that we can decide whether to add con_id
> or not while invoking clkdev_alloc().

hwmod is supposed to contain only HW related information. In that case
it will be Linux driver dependent and not really HW dependent.
That one is thus not really acceptable.

> This may be required to support legacy drivers which are not migrated to
> runtime_pm and still calls clk_get() for both "fck" and "ick", so here
> we need "fck" clk alias.

We can use "fck" even with runtime_pm. Just because sometime you need to
get the clock rate of the main clock.

> Any comments or opinion on this? Based on the feedback I can create the
> changes and submit it to the list.

Well, a #3 suggestion might be to enforce the usage of fck alias in the
drivers instead of assuming that the "NULL" entry is the proper one.

And a #4 will be to create a extra entry in the clkdev like you have done.

For my point of view, the #4 seems to be the one that will minimize the
overall change in the drivers and is probably the best one.

That being said, since the DT clock binding is merged now, the whole
automatic alias creation might disappear as soon as we will have DT boot
on all the platforms... OK, we are not really there still :-)

Regards,
Benoit



From lee.jones at linaro.org  Wed Aug  1 09:50:32 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 14:50:32 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <20120801132022.GS11892@opensource.wolfsonmicro.com>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
 <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
Message-ID: <50193428.5000708@linaro.org>

On 01/08/12 14:20, Mark Brown wrote:
> On Wed, Aug 01, 2012 at 08:19:28AM +0100, Lee Jones wrote:
>> On 31/07/12 16:18, Mark Brown wrote:
>
>>> I'm not going to apply this patch.  This isn't a vendor BSP, we
>>> shouldn't be putting random hacks like this in core code.
>
>> BSP kernel or otherwise, it still seems wrong to me to fail and
>> entire audio driver just because of a broken link.
>
> No, really.  Random disconnections in the DAPM graph are just endless
> pain from a support and debug point of view.  This isn't something that
> randomly breaks on specific hardware where we'd expect random errors at
> runtime, it's something that will never have worked - it seems clear
> nobody tested the mainline submission.

I am under the impression that it was tested. Perhaps before it was 
rebased, but tests were completed. Ola was very surprised when I told 
him there were link failures. The only issue is that I only found out 
and told him a day before he was due to take his Summer leave.

> It's very disappointing to see such an error exist, and even more
> disappointing that there's no interest in fixing the driver.

This is incorrect. I'm sure the driver will be fixed post-haste when Ola 
returns back from vacation. If I can find some time I might dabble in 
the mean-time also.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed Aug  1 09:55:58 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 01 Aug 2012 14:55:58 +0100
Subject: [PATCH 5/6] ARM: ux500: Ensure probing of Audio devices when
 Device Tree is enabled
In-Reply-To: <201208011332.02500.arnd@arndb.de>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <201207312054.13818.arnd@arndb.de> <5018DBEE.9090203@linaro.org>
 <201208011332.02500.arnd@arndb.de>
Message-ID: <5019356E.6020407@linaro.org>

On 01/08/12 14:32, Arnd Bergmann wrote:
> On Wednesday 01 August 2012, Lee Jones wrote:
>>> Looks like you're adding the same call to each of the three cases:
>>> mop500, snowball and hrefv60+. How about moving it before or after
>>> the if/elseif block?
>>
>> The Snowball one is different 'mop500_msp_init' -> 'mop500_of_msp_init'.
>
> Ah, I see. Is there a problem in always using mop500_of_msp_init then?
> I would guess that this just means you'd have to put the msp into the
> device tree files, which don't yet exist for mop500 and hrefv60.

Although that is true, it's only part of the issue.

mop500_of_msp_init is only a temporary solution to aid in step-by-step 
enablement of DT for audio. By the end of the patch-set it has been 
removed (along with the call to it if 'of_machine_is_compatible 
("calaosystems,snowball-a9500")'. What I can do it write a patch to 
consolidate the calls _after_ "ARM: ux500: Remove platform registration 
of MSP devices", as a bolt-on.


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linux at arm.linux.org.uk  Wed Aug  1 10:14:14 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 1 Aug 2012 15:14:14 +0100
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <50191F00.1040501@ti.com>
References: <50191F00.1040501@ti.com>
Message-ID: <20120801141414.GM7405@n2100.arm.linux.org.uk>

On Wed, Aug 01, 2012 at 05:50:16PM +0530, Vaibhav Hiremath wrote:
> The clk_get() api will not work, unless we pass both the arguments (dev,
> con_id) properly. Now expecting driver to always label con_id with "fck"
> is undesirable, as the same driver can be reused on multiple platforms,
> which can be non-omap and/or non-ti platforms.

Why not?

The connection ID is defined by the driver, and the platform stuff is
expected to provide drivers with what they require.  It's not the other
way around (platforms don't tell drivers what they require.)

In other words, if the device has two clocks, one called ick and one called
fck, then the device _should_ use clk_get() specifying "ick" for one, and
"fck" for the other.

And platforms better provide an "ick" and a "fck" for the device, even if
they have no respresentation for one or other of them (in which case you
supply a dummy clock.)


From konrad.wilk at oracle.com  Wed Aug  1 10:16:24 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:16:24 -0400
Subject: [PATCH 05/24] xen/arm: empty implementation of grant_table arch
 specific functions
In-Reply-To: <1343316846-25860-5-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-5-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801141624.GD7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:47PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/Makefile      |    2 +-
>  arch/arm/xen/grant-table.c |   53 ++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 54 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/xen/grant-table.c
> 
> diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> index b9d6acc..4384103 100644
> --- a/arch/arm/xen/Makefile
> +++ b/arch/arm/xen/Makefile
> @@ -1 +1 @@
> -obj-y		:= enlighten.o hypercall.o
> +obj-y		:= enlighten.o hypercall.o grant-table.o
> diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
> new file mode 100644
> index 0000000..0a4ee80
> --- /dev/null
> +++ b/arch/arm/xen/grant-table.c
> @@ -0,0 +1,53 @@
> +/******************************************************************************
> + * grant_table.c
> + * ARM specific part
> + *
> + * Granting foreign access to our memory reservation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation; or, when distributed
> + * separately from the Linux kernel or incorporated into other
> + * software packages, subject to the following license:
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this source file (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use, copy, modify,
> + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> + * and to permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include <xen/interface/xen.h>
> +#include <xen/page.h>
> +#include <xen/grant_table.h>
> +
> +int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
> +			   unsigned long max_nr_gframes,
> +			   void **__shared)
> +{
> +	return -1;

-ENOSYS
> +}
> +
> +void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
> +{
> +	return;
> +}
> +
> +int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
> +			   unsigned long max_nr_gframes,
> +			   grant_status_t **__shared)
> +{
> +	return -1;

Same here -ENOSYS
> +}
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:19:59 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:19:59 -0400
Subject: [PATCH 07/24] xen/arm: Xen detection and shared_info page mapping
In-Reply-To: <1343316846-25860-7-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-7-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801141959.GE7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:49PM +0100, Stefano Stabellini wrote:
> Check for a "/xen" node in the device tree, if it is present set
> xen_domain_type to XEN_HVM_DOMAIN and continue initialization.
> 
> Map the real shared info page using XENMEM_add_to_physmap with
> XENMAPSPACE_shared_info.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   56 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 56 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index d27c2a6..8c923af 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -5,6 +5,9 @@
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
>  
>  struct start_info _xen_start_info;
>  struct start_info *xen_start_info = &_xen_start_info;
> @@ -33,3 +36,56 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  	return -ENOSYS;
>  }
>  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> +
> +/*
> + * == Xen Device Tree format ==
> + * - /xen node;
> + * - compatible "arm,xen";
> + * - one interrupt for Xen event notifications;
> + * - one memory region to map the grant_table.
> + */
> +static int __init xen_guest_init(void)
> +{
> +	int cpu;
> +	struct xen_add_to_physmap xatp;
> +	static struct shared_info *shared_info_page = 0;
> +	struct device_node *node;
> +
> +	node = of_find_compatible_node(NULL, NULL, "arm,xen");
> +	if (!node) {
> +		pr_info("No Xen support\n");

I don't think the pr_info is appropiate here?
> +		return 0;

Should this be -ENODEV?

> +	}
> +	xen_domain_type = XEN_HVM_DOMAIN;
> +
> +	if (!shared_info_page)
> +		shared_info_page = (struct shared_info *)
> +			get_zeroed_page(GFP_KERNEL);
> +	if (!shared_info_page) {
> +		pr_err("not enough memory");

\n

> +		return -ENOMEM;
> +	}
> +	xatp.domid = DOMID_SELF;
> +	xatp.idx = 0;
> +	xatp.space = XENMAPSPACE_shared_info;
> +	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
> +	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
> +		BUG();
> +
> +	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
> +
> +	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
> +	 * page, we use it in the event channel upcall and in some pvclock
> +	 * related functions. We don't need the vcpu_info placement
> +	 * optimizations because we don't use any pv_mmu or pv_irq op on
> +	 * HVM.
> +	 * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
> +	 * online but xen_hvm_init_shared_info is run at resume time too and
> +	 * in that case multiple vcpus might be online. */
> +	for_each_online_cpu(cpu) {
> +		per_cpu(xen_vcpu, cpu) =
> +			&HYPERVISOR_shared_info->vcpu_info[cpu];
> +	}
> +	return 0;

This above looks stringly similar to the x86 one. Could it be
abstracted away to share the same code? Or is that something that
ought to be done later on when there is more meat on the bone?


> +}
> +core_initcall(xen_guest_init);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:22:49 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:22:49 -0400
Subject: [PATCH 08/24] xen/arm: Introduce xen_pfn_t for pfn and mfn types
In-Reply-To: <1343316846-25860-8-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-8-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801142249.GF7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:50PM +0100, Stefano Stabellini wrote:
> All the original Xen headers have xen_pfn_t as mfn and pfn type, however
> when they have been imported in Linux, xen_pfn_t has been replaced with
> unsigned long. That might work for x86 and ia64 but it does not for arm.

How come?
> Bring back xen_pfn_t and let each architecture define xen_pfn_t as they
> see fit.

I am OK with this as long as your include a comment in both of the
interface.h saying why this is needed. I am curious why 'unsinged long'
won't work? Is it b/c on ARM you always want a 64-bit type?

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/interface.h  |    2 ++
>  arch/ia64/include/asm/xen/interface.h |    2 +-
>  arch/x86/include/asm/xen/interface.h  |    2 ++
>  include/xen/interface/grant_table.h   |    4 ++--
>  include/xen/interface/memory.h        |    6 +++---
>  include/xen/interface/platform.h      |    4 ++--
>  include/xen/interface/xen.h           |    6 +++---
>  include/xen/privcmd.h                 |    2 --
>  8 files changed, 15 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
> index 6c3ab59..76b1ebe 100644
> --- a/arch/arm/include/asm/xen/interface.h
> +++ b/arch/arm/include/asm/xen/interface.h
> @@ -25,6 +25,7 @@
>  	} while (0)
>  
>  #ifndef __ASSEMBLY__
> +typedef uint64_t xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> @@ -35,6 +36,7 @@ DEFINE_GUEST_HANDLE(long);
>  DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
> +DEFINE_GUEST_HANDLE(xen_pfn_t);
>  
>  /* Maximum number of virtual CPUs in multi-processor guests. */
>  #define MAX_VIRT_CPUS 1
> diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
> index 09d5f7f..9efa068 100644
> --- a/arch/ia64/include/asm/xen/interface.h
> +++ b/arch/ia64/include/asm/xen/interface.h
> @@ -67,6 +67,7 @@
>  #define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
>  
>  #ifndef __ASSEMBLY__
> +typedef unsigned long xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint, unsigned int);
> @@ -79,7 +80,6 @@ DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
>  
> -typedef unsigned long xen_pfn_t;
>  DEFINE_GUEST_HANDLE(xen_pfn_t);
>  #define PRI_xen_pfn	"lx"
>  #endif
> diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> index cbf0c9d..24c1b07 100644
> --- a/arch/x86/include/asm/xen/interface.h
> +++ b/arch/x86/include/asm/xen/interface.h
> @@ -47,6 +47,7 @@
>  #endif
>  
>  #ifndef __ASSEMBLY__
> +typedef unsigned long xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> @@ -57,6 +58,7 @@ DEFINE_GUEST_HANDLE(long);
>  DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
> +DEFINE_GUEST_HANDLE(xen_pfn_t);
>  #endif
>  
>  #ifndef HYPERVISOR_VIRT_START
> diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h
> index a17d844..7da811b 100644
> --- a/include/xen/interface/grant_table.h
> +++ b/include/xen/interface/grant_table.h
> @@ -338,7 +338,7 @@ DEFINE_GUEST_HANDLE_STRUCT(gnttab_dump_table);
>  #define GNTTABOP_transfer                4
>  struct gnttab_transfer {
>      /* IN parameters. */
> -    unsigned long mfn;
> +    xen_pfn_t mfn;
>      domid_t       domid;
>      grant_ref_t   ref;
>      /* OUT parameters. */
> @@ -375,7 +375,7 @@ struct gnttab_copy {
>  	struct {
>  		union {
>  			grant_ref_t ref;
> -			unsigned long   gmfn;
> +			xen_pfn_t   gmfn;
>  		} u;
>  		domid_t  domid;
>  		uint16_t offset;
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index eac3ce1..abbbff0 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -31,7 +31,7 @@ struct xen_memory_reservation {
>       *   OUT: GMFN bases of extents that were allocated
>       *   (NB. This command also updates the mach_to_phys translation table)
>       */
> -    GUEST_HANDLE(ulong) extent_start;
> +    GUEST_HANDLE(xen_pfn_t) extent_start;
>  
>      /* Number of extents, and size/alignment of each (2^extent_order pages). */
>      unsigned long  nr_extents;
> @@ -130,7 +130,7 @@ struct xen_machphys_mfn_list {
>       * any large discontiguities in the machine address space, 2MB gaps in
>       * the machphys table will be represented by an MFN base of zero.
>       */
> -    GUEST_HANDLE(ulong) extent_start;
> +    GUEST_HANDLE(xen_pfn_t) extent_start;
>  
>      /*
>       * Number of extents written to the above array. This will be smaller
> @@ -172,7 +172,7 @@ struct xen_add_to_physmap {
>      unsigned long idx;
>  
>      /* GPFN where the source mapping page should appear. */
> -    unsigned long gpfn;
> +    xen_pfn_t gpfn;
>  };
>  DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap);
>  
> diff --git a/include/xen/interface/platform.h b/include/xen/interface/platform.h
> index 486653f..0bea470 100644
> --- a/include/xen/interface/platform.h
> +++ b/include/xen/interface/platform.h
> @@ -54,7 +54,7 @@ DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime_t);
>  #define XENPF_add_memtype         31
>  struct xenpf_add_memtype {
>  	/* IN variables. */
> -	unsigned long mfn;
> +	xen_pfn_t mfn;
>  	uint64_t nr_mfns;
>  	uint32_t type;
>  	/* OUT variables. */
> @@ -84,7 +84,7 @@ struct xenpf_read_memtype {
>  	/* IN variables. */
>  	uint32_t reg;
>  	/* OUT variables. */
> -	unsigned long mfn;
> +	xen_pfn_t mfn;
>  	uint64_t nr_mfns;
>  	uint32_t type;
>  };
> diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> index 4f29f33..d59a991 100644
> --- a/include/xen/interface/xen.h
> +++ b/include/xen/interface/xen.h
> @@ -192,7 +192,7 @@ struct mmuext_op {
>  	unsigned int cmd;
>  	union {
>  		/* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR */
> -		unsigned long mfn;
> +		xen_pfn_t mfn;
>  		/* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
>  		unsigned long linear_addr;
>  	} arg1;
> @@ -432,11 +432,11 @@ struct start_info {
>  	unsigned long nr_pages;     /* Total pages allocated to this domain.  */
>  	unsigned long shared_info;  /* MACHINE address of shared info struct. */
>  	uint32_t flags;             /* SIF_xxx flags.                         */
> -	unsigned long store_mfn;    /* MACHINE page number of shared page.    */
> +	xen_pfn_t store_mfn;        /* MACHINE page number of shared page.    */
>  	uint32_t store_evtchn;      /* Event channel for store communication. */
>  	union {
>  		struct {
> -			unsigned long mfn;  /* MACHINE page number of console page.   */
> +			xen_pfn_t mfn;      /* MACHINE page number of console page.   */
>  			uint32_t  evtchn;   /* Event channel for console page.        */
>  		} domU;
>  		struct {
> diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
> index 4d58881..45c1aa1 100644
> --- a/include/xen/privcmd.h
> +++ b/include/xen/privcmd.h
> @@ -37,8 +37,6 @@
>  #include <linux/compiler.h>
>  #include <xen/interface/xen.h>
>  
> -typedef unsigned long xen_pfn_t;
> -
>  struct privcmd_hypercall {
>  	__u64 op;
>  	__u64 arg[5];
> -- 
> 1.7.2.5


From arnd at arndb.de  Wed Aug  1 10:32:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 1 Aug 2012 14:32:01 +0000
Subject: [PATCH 5/6] ARM: ux500: Ensure probing of Audio devices when
 Device Tree is enabled
In-Reply-To: <5019356E.6020407@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <201208011332.02500.arnd@arndb.de> <5019356E.6020407@linaro.org>
Message-ID: <201208011432.02398.arnd@arndb.de>

On Wednesday 01 August 2012, Lee Jones wrote:
> 
> On 01/08/12 14:32, Arnd Bergmann wrote:
> > On Wednesday 01 August 2012, Lee Jones wrote:
> >>> Looks like you're adding the same call to each of the three cases:
> >>> mop500, snowball and hrefv60+. How about moving it before or after
> >>> the if/elseif block?
> >>
> >> The Snowball one is different 'mop500_msp_init' -> 'mop500_of_msp_init'.
> >
> > Ah, I see. Is there a problem in always using mop500_of_msp_init then?
> > I would guess that this just means you'd have to put the msp into the
> > device tree files, which don't yet exist for mop500 and hrefv60.
> 
> Although that is true, it's only part of the issue.
> 
> mop500_of_msp_init is only a temporary solution to aid in step-by-step 
> enablement of DT for audio. By the end of the patch-set it has been 
> removed (along with the call to it if 'of_machine_is_compatible 
> ("calaosystems,snowball-a9500")'. What I can do it write a patch to 
> consolidate the calls after "ARM: ux500: Remove platform registration 
> of MSP devices", as a bolt-on.

I see. Your solution looks fine then.

	Arnd


From konrad.wilk at oracle.com  Wed Aug  1 10:28:40 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:28:40 -0400
Subject: [PATCH 09/24] xen/arm: compile and run xenbus
In-Reply-To: <1343316846-25860-9-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-9-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801142840.GG7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:51PM +0100, Stefano Stabellini wrote:
> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> an error.
> 
> If Linux is running as an HVM domain and is running as Dom0, use
> xenstored_local_init to initialize the xenstore page and event channel.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
>  drivers/xen/xenbus/xenbus_probe.c |   27 +++++++++++++++++----------
>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
>  3 files changed, 19 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> index 52fe7ad..c5aa55c 100644
> --- a/drivers/xen/xenbus/xenbus_comms.c
> +++ b/drivers/xen/xenbus/xenbus_comms.c
> @@ -224,7 +224,7 @@ int xb_init_comms(void)
>  		int err;
>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
>  						0, "xenbus", &xb_waitq);
> -		if (err <= 0) {
> +		if (err < 0) {
>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
>  			return err;
>  		}
> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> index b793723..3ae47c2 100644
> --- a/drivers/xen/xenbus/xenbus_probe.c
> +++ b/drivers/xen/xenbus/xenbus_probe.c
> @@ -729,16 +729,23 @@ static int __init xenbus_init(void)
>  	xenbus_ring_ops_init();
>  
>  	if (xen_hvm_domain()) {
> -		uint64_t v = 0;
> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> -		if (err)
> -			goto out_error;
> -		xen_store_evtchn = (int)v;
> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> -		if (err)
> -			goto out_error;
> -		xen_store_mfn = (unsigned long)v;
> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> +		if (xen_initial_domain()) {
> +			err = xenstored_local_init();
> +			xen_store_interface =
> +				phys_to_virt(xen_store_mfn << PAGE_SHIFT);
> +		} else {
> +			uint64_t v = 0;
> +			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> +			if (err)
> +				goto out_error;
> +			xen_store_evtchn = (int)v;
> +			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> +			if (err)
> +				goto out_error;
> +			xen_store_mfn = (unsigned long)v;
> +			xen_store_interface =
> +				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> +		}

This, and along with the Hybrid PV dom0 (not yet posted, but it was doing
similar manipulation here) is getting more and more like a rat-mess.


Any chance we can just abstract the three different XenStore access
ways and just have something like this:

	enum {
		USE_UNKNOWN
		USE_HVM,
		USE_PV,
		USE_LOCAL
		USE_ALREADY_INIT
	};
	int usage = USE_UNKNOWN;
	if (xen_pv_domain())
		usage = USE_PV;
	if (xen_hvm_domain())
		usage = USE_HVM;
	if (xen_initial_domain())
		usage = USE_LOCAL;

	if (xen_start_info->store_evtchn)
		usage = USE_ALREADY_INIT;
	
	.. other overwrites..

	switch (usage) {
		.. blah blah.
	}


>  		xen_store_evtchn = xen_start_info->store_evtchn;
>  		xen_store_mfn = xen_start_info->store_mfn;
> diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
> index d1c217b..f7feb3d 100644
> --- a/drivers/xen/xenbus/xenbus_xs.c
> +++ b/drivers/xen/xenbus/xenbus_xs.c
> @@ -44,6 +44,7 @@
>  #include <linux/rwsem.h>
>  #include <linux/module.h>
>  #include <linux/mutex.h>
> +#include <asm/xen/hypervisor.h>
>  #include <xen/xenbus.h>
>  #include <xen/xen.h>
>  #include "xenbus_comms.h"
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:34:59 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:34:59 -0400
Subject: [Xen-devel] [PATCH 11/24] xen/arm: introduce CONFIG_XEN on ARM
In-Reply-To: <1343316846-25860-11-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-11-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801143459.GH7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:53PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/Kconfig |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a91009c..9c54cb4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -2228,6 +2228,16 @@ config NEON
>  	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
>  	  Extension.
>  
> +config XEN_DOM0
> +	def_bool y

What is the benefit of this ? I was hoping at some point to rip out all of those
XEN_DOM0 and just have, mostly,
	CONFIG_XEN_BACKEND_SUPPORT
		(which would compile whatever is needed for HVM or PV guests to run
		blkback/netback/grant/grantalloc/etc)
	CONFIG_XEN_FRONTEND_SUPPORT
		(the vice-versa)

	CONFIG_XEN_PCI
		which would have the PCI support, the ACPI routing (which is
		predomaintaly most of the dom0 support), VGA text support, and
		whatever else is in there.

In that fashion you could compile a kernel with CONFIG_XEN_BACKEND_SUPPORT
without any CONFIG_XEN_PCI and drop it in as an HVM device driver domain.
Thought maybe that wouldn't really work as if you do PCI passthrough to such
domain, you are going to need the PCI support and ACPI routing. The VGA text
maybe not...

OK, never mind - we should brainstorm it and figure out how to make this
nicely work. In the meantime this is OK.

> +
> +config XEN
> +	bool "Xen guest support on ARM"
> +	depends on ARM && OF
> +	select XEN_DOM0
> +	help
> +	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
> +
>  endmenu
>  
>  menu "Userspace binary formats"
> -- 
> 1.7.2.5
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel at lists.xen.org
> http://lists.xen.org/xen-devel


From konrad.wilk at oracle.com  Wed Aug  1 10:35:51 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:35:51 -0400
Subject: [Xen-devel] [PATCH 04/24] xen/arm: sync_bitops
In-Reply-To: <1343381305.6812.116.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120726163759.GE9222@phenom.dumpdata.com>
 <1343381305.6812.116.camel@zakaz.uk.xensource.com>
Message-ID: <20120801143551.GI7227@phenom.dumpdata.com>

On Fri, Jul 27, 2012 at 10:28:25AM +0100, Ian Campbell wrote:
> On Thu, 2012-07-26 at 17:37 +0100, Konrad Rzeszutek Wilk wrote:
> > On Thu, Jul 26, 2012 at 04:33:46PM +0100, Stefano Stabellini wrote:
> > > sync_bitops functions are equivalent to the SMP implementation of the
> > > original functions, independently from CONFIG_SMP being defined.
> > 
> > So why can't the code be changed to use that? Is it that
> > the _set_bit, _clear_bit, etc are not available with !CONFIG_SMP?
> 
> _set_bit etc are not SMP safe if !CONFIG_SMP. But under Xen you might be
> communicating with a completely external entity who might be on another
> CPU (e.g. two uniprocessor guests communicating via event channels and
> grant tables). So we need a variant of the bit ops which are SMP safe
> even on a UP kernel.
> 
> The users are common code and the sync_foo vs foo distinction matters on
> some platforms (e.g. x86 where a UP kernel would omit the LOCK prefix
> for the normal ones).

OK, that makes sense. Stefano can you include that comment in the git
commit description and in the sync_bitops.h file please?
> 
> > 
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  arch/arm/include/asm/sync_bitops.h |   17 +++++++++++++++++
> > >  1 files changed, 17 insertions(+), 0 deletions(-)
> > >  create mode 100644 arch/arm/include/asm/sync_bitops.h
> > > 
> > > diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
> > > new file mode 100644
> > > index 0000000..d975092903
> > > --- /dev/null
> > > +++ b/arch/arm/include/asm/sync_bitops.h
> > > @@ -0,0 +1,17 @@
> > > +#ifndef __ASM_SYNC_BITOPS_H__
> > > +#define __ASM_SYNC_BITOPS_H__
> > > +
> > > +#include <asm/bitops.h>
> > > +#include <asm/system.h>
> > > +
> > > +#define sync_set_bit(nr, p)		_set_bit(nr, p)
> > > +#define sync_clear_bit(nr, p)		_clear_bit(nr, p)
> > > +#define sync_change_bit(nr, p)		_change_bit(nr, p)
> > > +#define sync_test_and_set_bit(nr, p)	_test_and_set_bit(nr, p)
> > > +#define sync_test_and_clear_bit(nr, p)	_test_and_clear_bit(nr, p)
> > > +#define sync_test_and_change_bit(nr, p)	_test_and_change_bit(nr, p)
> > > +#define sync_test_bit(nr, addr)		test_bit(nr, addr)
> > > +#define sync_cmpxchg			cmpxchg
> > > +
> > > +
> > > +#endif
> > > -- 
> > > 1.7.2.5
> > > 
> > > 
> > > _______________________________________________
> > > Xen-devel mailing list
> > > Xen-devel at lists.xen.org
> > > http://lists.xen.org/xen-devel
> 


From konrad.wilk at oracle.com  Wed Aug  1 10:38:22 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:38:22 -0400
Subject: [PATCH 12/24] xen/arm: Introduce xen_guest_init
In-Reply-To: <1343316846-25860-12-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-12-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801143822.GJ7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:54PM +0100, Stefano Stabellini wrote:
> We used to rely on a core_initcall to initialize Xen on ARM, however
> core_initcalls are actually called after early consoles are initialized.
> That means that hvc_xen.c is going to be initialized before Xen.
> 
> Given the lack of a better alternative, just call a new Xen
> initialization function (xen_guest_init) from xen_cons_init.
> 
> xen_guest_init has to be arch independent, so write both an ARM and an
> x86 implementation. The x86 implementation is currently empty because we
> can be sure that xen_hvm_guest_init is called early enough.

Should the arm version then not be anymore on the core_initcall then?

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c  |    7 ++++++-
>  arch/x86/xen/enlighten.c  |    8 ++++++++
>  drivers/tty/hvc/hvc_xen.c |    7 ++++++-
>  include/xen/xen.h         |    2 ++
>  4 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 8c923af..dc68074 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -44,7 +44,7 @@ EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
>   * - one interrupt for Xen event notifications;
>   * - one memory region to map the grant_table.
>   */
> -static int __init xen_guest_init(void)
> +int __init xen_guest_init(void)
>  {
>  	int cpu;
>  	struct xen_add_to_physmap xatp;
> @@ -58,6 +58,10 @@ static int __init xen_guest_init(void)
>  	}
>  	xen_domain_type = XEN_HVM_DOMAIN;
>  
> +	/* already setup */
> +	if (shared_info_page != 0 && HYPERVISOR_shared_info == shared_info_page)
> +		return 0;
> +
>  	if (!shared_info_page)
>  		shared_info_page = (struct shared_info *)
>  			get_zeroed_page(GFP_KERNEL);
> @@ -88,4 +92,5 @@ static int __init xen_guest_init(void)
>  	}
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(xen_guest_init);

Why the export symbols?

>  core_initcall(xen_guest_init);
> diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
> index ff962d4..6131d43 100644
> --- a/arch/x86/xen/enlighten.c
> +++ b/arch/x86/xen/enlighten.c
> @@ -1567,4 +1567,12 @@ const struct hypervisor_x86 x86_hyper_xen_hvm __refconst = {
>  	.init_platform		= xen_hvm_guest_init,
>  };
>  EXPORT_SYMBOL(x86_hyper_xen_hvm);
> +
> +int __init xen_guest_init(void)
> +{
> +	/* do nothing: rely on x86_hyper_xen_hvm for the initialization */
> +	return 0;
> +	
> +}
> +EXPORT_SYMBOL_GPL(xen_guest_init);
>  #endif
> diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
> index dc07f56..3c04fb8 100644
> --- a/drivers/tty/hvc/hvc_xen.c
> +++ b/drivers/tty/hvc/hvc_xen.c
> @@ -577,6 +577,12 @@ static void __exit xen_hvc_fini(void)
>  static int xen_cons_init(void)
>  {
>  	const struct hv_ops *ops;
> +	int r;
> +
> +	/* retrieve xen infos  */
> +	r = xen_guest_init();
> +	if (r < 0)
> +		return r;
>  
>  	if (!xen_domain())
>  		return 0;
> @@ -584,7 +590,6 @@ static int xen_cons_init(void)
>  	if (xen_initial_domain())
>  		ops = &dom0_hvc_ops;
>  	else {
> -		int r;
>  		ops = &domU_hvc_ops;
>  
>  		if (xen_hvm_domain())
> diff --git a/include/xen/xen.h b/include/xen/xen.h
> index 2c0d3a5..792a4d2 100644
> --- a/include/xen/xen.h
> +++ b/include/xen/xen.h
> @@ -9,8 +9,10 @@ enum xen_domain_type {
>  
>  #ifdef CONFIG_XEN
>  extern enum xen_domain_type xen_domain_type;
> +int xen_guest_init(void);
>  #else
>  #define xen_domain_type		XEN_NATIVE
> +static inline int xen_guest_init(void) { return 0; }
>  #endif
>  
>  #define xen_domain()		(xen_domain_type != XEN_NATIVE)
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:39:46 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:39:46 -0400
Subject: [PATCH 13/24] xen/arm: get privilege status
In-Reply-To: <1343399630.25096.4.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-13-git-send-email-stefano.stabellini@eu.citrix.com>
 <1343382276.6812.126.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1207271514140.26163@kaball.uk.xensource.com>
 <1343399630.25096.4.camel@zakaz.uk.xensource.com>
Message-ID: <20120801143946.GK7227@phenom.dumpdata.com>

On Fri, Jul 27, 2012 at 03:33:50PM +0100, Ian Campbell wrote:
> On Fri, 2012-07-27 at 15:25 +0100, Stefano Stabellini wrote:
> > On Fri, 27 Jul 2012, Ian Campbell wrote:
> > > On Thu, 2012-07-26 at 16:33 +0100, Stefano Stabellini wrote:
> > > > Use Xen features to figure out if we are privileged.
> > > > 
> > > > XENFEAT_dom0 was introduced by 23735 in xen-unstable.hg.
> > > > 
> > > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > > ---
> > > >  arch/arm/xen/enlighten.c         |    7 +++++++
> > > >  include/xen/interface/features.h |    3 +++
> > > >  2 files changed, 10 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > > index dc68074..2e013cf 100644
> > > > --- a/arch/arm/xen/enlighten.c
> > > > +++ b/arch/arm/xen/enlighten.c
> > > > @@ -2,6 +2,7 @@
> > > >  #include <xen/interface/xen.h>
> > > >  #include <xen/interface/memory.h>
> > > >  #include <xen/platform_pci.h>
> > > > +#include <xen/features.h>
> > > >  #include <asm/xen/hypervisor.h>
> > > >  #include <asm/xen/hypercall.h>
> > > >  #include <linux/module.h>
> > > > @@ -58,6 +59,12 @@ int __init xen_guest_init(void)
> > > >  	}
> > > >  	xen_domain_type = XEN_HVM_DOMAIN;
> > > >  
> > > > +	xen_setup_features();
> > > > +	if (xen_feature(XENFEAT_dom0))
> > > > +		xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
> > > > +	else
> > > > +		xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
> > > 
> > > What happens here on platforms prior to hypervisor changeset 23735?
> > 
> > It wouldn't work.
> > Considering that we are certainly not going to backport ARM support to
> > Xen 4.1, and that both ARM and XENFEAT_dom0 will be present in Xen 4.2,
> > do we really need to support the Xen unstable changesets between ARM was
> > introduced and XENFEAT_dom0 appeared?

So should it just panic and say "AAAAAAH"?

> 
> Sorry, I missed the "arm" in the path.
> 
> Ian.
> 
> 


From konrad.wilk at oracle.com  Wed Aug  1 10:40:59 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:40:59 -0400
Subject: [PATCH 14/24] xen/arm: initialize grant_table on ARM
In-Reply-To: <1343316846-25860-14-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-14-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801144059.GL7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:56PM +0100, Stefano Stabellini wrote:
> Initialize the grant table mapping at the address specified at index 0
> in the DT under the /xen node.

Is it always index 0? If so, should it have a #define for the
other index values?

> After the grant table is initialized, call xenbus_probe (if not dom0).
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c  |   13 +++++++++++++
>  drivers/xen/grant-table.c |    2 +-
>  2 files changed, 14 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 2e013cf..854af1e 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -1,8 +1,12 @@
>  #include <xen/xen.h>
>  #include <xen/interface/xen.h>
>  #include <xen/interface/memory.h>
> +#include <xen/interface/hvm/params.h>
>  #include <xen/platform_pci.h>
>  #include <xen/features.h>
> +#include <xen/grant_table.h>
> +#include <xen/hvm.h>
> +#include <xen/xenbus.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include <linux/module.h>
> @@ -51,12 +55,16 @@ int __init xen_guest_init(void)
>  	struct xen_add_to_physmap xatp;
>  	static struct shared_info *shared_info_page = 0;
>  	struct device_node *node;
> +	struct resource res;
>  
>  	node = of_find_compatible_node(NULL, NULL, "arm,xen");
>  	if (!node) {
>  		pr_info("No Xen support\n");
>  		return 0;
>  	}
> +	if (of_address_to_resource(node, 0, &res))
> +		return -EINVAL;
> +	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
>  	xen_domain_type = XEN_HVM_DOMAIN;
>  
>  	xen_setup_features();
> @@ -97,6 +105,11 @@ int __init xen_guest_init(void)
>  		per_cpu(xen_vcpu, cpu) =
>  			&HYPERVISOR_shared_info->vcpu_info[cpu];
>  	}
> +
> +	gnttab_init();
> +	if (!xen_initial_domain())
> +		xenbus_probe(NULL);
> +
>  	return 0;
>  }
>  EXPORT_SYMBOL_GPL(xen_guest_init);
> diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
> index 1d0d95e..fd2137a 100644
> --- a/drivers/xen/grant-table.c
> +++ b/drivers/xen/grant-table.c
> @@ -62,7 +62,7 @@
>  
>  static grant_ref_t **gnttab_list;
>  static unsigned int nr_grant_frames;
> -static unsigned int boot_max_nr_grant_frames;
> +static unsigned int boot_max_nr_grant_frames = 1;

Is this going to impact x86 version?

>  static int gnttab_free_count;
>  static grant_ref_t gnttab_free_head;
>  static DEFINE_SPINLOCK(gnttab_list_lock);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:44:18 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:44:18 -0400
Subject: [PATCH 15/24] xen/arm: receive Xen events on ARM
In-Reply-To: <1343316846-25860-15-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-15-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801144418.GM7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:33:57PM +0100, Stefano Stabellini wrote:
> Compile events.c on ARM.
> Parse, map and enable the IRQ to get event notifications from the device
> tree (node "/xen").
> 
> On ARM Linux irqs are not enabled by default:
> 
> - call enable_percpu_irq for xen_events_irq (drivers are supposed
> to call enable_irq after request_irq);
> 
> - reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
> default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
> irq_startup, that is responsible for calling irq_unmask at startup time.
> As a result event channels remain masked.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   33 +++++++++++++++++++++++++++++++++
>  arch/x86/xen/enlighten.c |    1 +
>  arch/x86/xen/irq.c       |    1 +
>  arch/x86/xen/xen-ops.h   |    1 -
>  drivers/xen/events.c     |   18 +++++++++++++++---
>  include/xen/events.h     |    2 ++
>  6 files changed, 52 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 854af1e..60d6d36 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -7,8 +7,11 @@
>  #include <xen/grant_table.h>
>  #include <xen/hvm.h>
>  #include <xen/xenbus.h>
> +#include <xen/events.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqreturn.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_irq.h>
> @@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
>  int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
>  EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
>  
> +static __read_mostly int xen_events_irq = -1;
> +
>  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  			       unsigned long addr,
>  			       unsigned long mfn, int nr,
> @@ -65,6 +70,9 @@ int __init xen_guest_init(void)
>  	if (of_address_to_resource(node, 0, &res))
>  		return -EINVAL;
>  	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
> +	xen_events_irq = irq_of_parse_and_map(node, 0);
> +	pr_info("Xen support found, events_irq=%d gnttab_frame_pfn=%lx\n",
> +			xen_events_irq, xen_hvm_resume_frames);
>  	xen_domain_type = XEN_HVM_DOMAIN;
>  
>  	xen_setup_features();
> @@ -114,3 +122,28 @@ int __init xen_guest_init(void)
>  }
>  EXPORT_SYMBOL_GPL(xen_guest_init);
>  core_initcall(xen_guest_init);
> +
> +static irqreturn_t xen_arm_callback(int irq, void *arg)
> +{
> +	xen_hvm_evtchn_do_upcall();
> +	return 0;

Um, IRQ_HANDLED?

> +}
> +
> +static int __init xen_init_events(void)
> +{
> +	if (!xen_domain() || xen_events_irq < 0)
> +		return -ENODEV;
> +
> +	xen_init_IRQ();
> +
> +	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
> +			"events", xen_vcpu)) {
> +		pr_err("Error requesting IRQ %d\n", xen_events_irq);
> +		return -EINVAL;
> +	}
> +
> +	enable_percpu_irq(xen_events_irq, 0);
> +
> +	return 0;
> +}
> +postcore_initcall(xen_init_events);
> diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
> index 6131d43..5a30502 100644
> --- a/arch/x86/xen/enlighten.c
> +++ b/arch/x86/xen/enlighten.c
> @@ -33,6 +33,7 @@
>  #include <linux/memblock.h>
>  
>  #include <xen/xen.h>
> +#include <xen/events.h>
>  #include <xen/interface/xen.h>
>  #include <xen/interface/version.h>
>  #include <xen/interface/physdev.h>
> diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
> index 1573376..01a4dc0 100644
> --- a/arch/x86/xen/irq.c
> +++ b/arch/x86/xen/irq.c
> @@ -5,6 +5,7 @@
>  #include <xen/interface/xen.h>
>  #include <xen/interface/sched.h>
>  #include <xen/interface/vcpu.h>
> +#include <xen/events.h>
>  
>  #include <asm/xen/hypercall.h>
>  #include <asm/xen/hypervisor.h>
> diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
> index 202d4c1..2368295 100644
> --- a/arch/x86/xen/xen-ops.h
> +++ b/arch/x86/xen/xen-ops.h
> @@ -35,7 +35,6 @@ void xen_set_pat(u64);
>  
>  char * __init xen_memory_setup(void);
>  void __init xen_arch_setup(void);
> -void __init xen_init_IRQ(void);
>  void xen_enable_sysenter(void);
>  void xen_enable_syscall(void);
>  void xen_vcpu_restore(void);
> diff --git a/drivers/xen/events.c b/drivers/xen/events.c
> index 7da65d3..9b506b2 100644
> --- a/drivers/xen/events.c
> +++ b/drivers/xen/events.c
> @@ -31,14 +31,16 @@
>  #include <linux/irqnr.h>
>  #include <linux/pci.h>
>  
> +#ifdef CONFIG_X86
>  #include <asm/desc.h>
>  #include <asm/ptrace.h>
>  #include <asm/irq.h>
>  #include <asm/idle.h>
>  #include <asm/io_apic.h>
> -#include <asm/sync_bitops.h>
>  #include <asm/xen/page.h>
>  #include <asm/xen/pci.h>
> +#endif
> +#include <asm/sync_bitops.h>
>  #include <asm/xen/hypercall.h>
>  #include <asm/xen/hypervisor.h>
>  
> @@ -50,6 +52,9 @@
>  #include <xen/interface/event_channel.h>
>  #include <xen/interface/hvm/hvm_op.h>
>  #include <xen/interface/hvm/params.h>
> +#include <xen/interface/physdev.h>
> +#include <xen/interface/sched.h>
> +#include <asm/hw_irq.h>
>  
>  /*
>   * This lock protects updates to the following mapping and reference-count
> @@ -834,6 +839,7 @@ int bind_evtchn_to_irq(unsigned int evtchn)
>  		struct irq_info *info = info_for_irq(irq);
>  		WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
>  	}
> +	irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);

I feel that this should be its own commit by itself. I am not certain
of the implication of this on x86 and I think it deserves some explanation.


>  
>  out:
>  	mutex_unlock(&irq_mapping_update_lock);
> @@ -1377,7 +1383,9 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
>  {
>  	struct pt_regs *old_regs = set_irq_regs(regs);
>  
> +#ifdef CONFIG_X86
>  	exit_idle();
> +#endif

Doesn't exist? Or is that it does not need it?

>  	irq_enter();
>  
>  	__xen_evtchn_do_upcall();
> @@ -1786,9 +1794,9 @@ void xen_callback_vector(void)
>  void xen_callback_vector(void) {}
>  #endif
>  
> -void __init xen_init_IRQ(void)
> +void xen_init_IRQ(void)
>  {
> -	int i, rc;
> +	int i;
>  
>  	evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
>  				    GFP_KERNEL);
> @@ -1804,6 +1812,7 @@ void __init xen_init_IRQ(void)
>  
>  	pirq_needs_eoi = pirq_needs_eoi_flag;
>  
> +#ifdef CONFIG_X86
>  	if (xen_hvm_domain()) {
>  		xen_callback_vector();
>  		native_init_IRQ();
> @@ -1811,6 +1820,7 @@ void __init xen_init_IRQ(void)
>  		 * __acpi_register_gsi can point at the right function */
>  		pci_xen_hvm_init();
>  	} else {
> +		int rc;
>  		struct physdev_pirq_eoi_gmfn eoi_gmfn;
>  
>  		irq_ctx_init(smp_processor_id());
> @@ -1826,4 +1836,6 @@ void __init xen_init_IRQ(void)
>  		} else
>  			pirq_needs_eoi = pirq_check_eoi_map;
>  	}
> +#endif
>  }
> +EXPORT_SYMBOL_GPL(xen_init_IRQ);
> diff --git a/include/xen/events.h b/include/xen/events.h
> index 04399b2..c6bfe01 100644
> --- a/include/xen/events.h
> +++ b/include/xen/events.h
> @@ -109,4 +109,6 @@ int xen_irq_from_gsi(unsigned gsi);
>  /* Determine whether to ignore this IRQ if it is passed to a guest. */
>  int xen_test_irq_shared(int irq);
>  
> +/* initialize Xen IRQ subsystem */
> +void xen_init_IRQ(void);
>  #endif	/* _XEN_EVENTS_H */
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:47:51 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:47:51 -0400
Subject: [Xen-devel] [PATCH 17/24] xen: allow privcmd for HVM guests
In-Reply-To: <alpine.DEB.2.02.1207271502480.26163@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-17-git-send-email-stefano.stabellini@eu.citrix.com>
 <5012598C0200007800090DB9@nat28.tlf.novell.com>
 <alpine.DEB.2.02.1207271502480.26163@kaball.uk.xensource.com>
Message-ID: <20120801144751.GN7227@phenom.dumpdata.com>

On Fri, Jul 27, 2012 at 03:10:13PM +0100, Stefano Stabellini wrote:
> On Fri, 27 Jul 2012, Jan Beulich wrote:
> > >>> On 26.07.12 at 17:33, Stefano Stabellini <stefano.stabellini at eu.citrix.com> wrote:
> > > In order for privcmd mmap to work correctly, xen_remap_domain_mfn_range
> > > needs to be implemented for HVM guests.
> > > If it is not, mmap is going to fail later on.
> > 
> > Somehow, for me at least, this description doesn't connect to the
> > actual change.
> 
> We can remove the "return -ENOSYS" from privcmd_mmap but the actual mmap
> is still not going to work unless xen_remap_domain_mfn_range is
> implemented correctly.
> The x86 implementation of xen_remap_domain_mfn_range is PV only so it is
> not going to work for HVM or auto_translated_physmap guests.
> As a result mmap_batch_fn is going to fail.

So what you are saying is that this check is redundant and that earlier
on in the call stack this check is made?

I am not seeing it? I am seeing an:

289         if (!xen_initial_domain())
290                 return -EPERM;

But that would still work.

Perhaps adding an:

	if (xen_hvm_domain())
		return -ENOSYS

is more appropiate in privcmd_ioctl_mmap_batch?

Irrespective of HVM guests, I recall that it is possible to run PV guests
with XENFEAT_auto_translated_physmap? How will this be impacted?

> 
> 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  drivers/xen/privcmd.c |    4 ----
> > >  1 files changed, 0 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
> > > index ccee0f1..85226cb 100644
> > > --- a/drivers/xen/privcmd.c
> > > +++ b/drivers/xen/privcmd.c
> > > @@ -380,10 +380,6 @@ static struct vm_operations_struct privcmd_vm_ops = {
> > >  
> > >  static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
> > >  {
> > > -	/* Unsupported for auto-translate guests. */
> > > -	if (xen_feature(XENFEAT_auto_translated_physmap))
> > > -		return -ENOSYS;
> > > -
> > 
> > Is this safe on x86?
> > 
> 
> It is safe in the sense that is not going to crash dom0 or the
> hypervisor, but it is not going to work.
> 
> Actually in order for it to be safe we need this additional change:
> 
> diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
> index 3a73785..885a223 100644
> --- a/arch/x86/xen/mmu.c
> +++ b/arch/x86/xen/mmu.c
> @@ -2310,6 +2310,9 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  	unsigned long range;
>  	int err = 0;
>  
> +	if (xen_feature(XENFEAT_auto_translated_physmap))
> +		return -EINVAL;
> +
>  	prot = __pgprot(pgprot_val(prot) | _PAGE_IOMAP);
>  
>  	BUG_ON(!((vma->vm_flags & (VM_PFNMAP | VM_RESERVED | VM_IO)) ==
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel at lists.xen.org
> http://lists.xen.org/xen-devel


From konrad.wilk at oracle.com  Wed Aug  1 10:48:18 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:48:18 -0400
Subject: [PATCH 18/24] xen/arm: compile blkfront and blkback
In-Reply-To: <1343316846-25860-18-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-18-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801144818.GO7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:34:00PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/block/xen-blkback/blkback.c  |    1 +
>  include/xen/interface/io/protocols.h |    3 +++
>  2 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
> index 73f196c..63dd5b9 100644
> --- a/drivers/block/xen-blkback/blkback.c
> +++ b/drivers/block/xen-blkback/blkback.c
> @@ -42,6 +42,7 @@
>  
>  #include <xen/events.h>
>  #include <xen/page.h>
> +#include <xen/xen.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include "common.h"
> diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
> index 01fc8ae..0eafaf2 100644
> --- a/include/xen/interface/io/protocols.h
> +++ b/include/xen/interface/io/protocols.h
> @@ -5,6 +5,7 @@
>  #define XEN_IO_PROTO_ABI_X86_64     "x86_64-abi"
>  #define XEN_IO_PROTO_ABI_IA64       "ia64-abi"
>  #define XEN_IO_PROTO_ABI_POWERPC64  "powerpc64-abi"
> +#define XEN_IO_PROTO_ABI_ARM        "arm-abi"

So one that has all of the 32/64 issues worked out? Nice.

>  
>  #if defined(__i386__)
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
> @@ -14,6 +15,8 @@
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
>  #elif defined(__powerpc64__)
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
> +#elif defined(__arm__)
> +# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
>  #else
>  # error arch fixup needed here
>  #endif
> -- 
> 1.7.2.5


From linux at roeck-us.net  Wed Aug  1 10:58:37 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Wed, 1 Aug 2012 07:58:37 -0700
Subject: [06/10,V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801075010.GI1672@S2100-06.ap.freescale.net>
References: <1341555449-17507-6-git-send-email-marex@denx.de>
 <201208010810.37652.marex@denx.de>
 <20120801063936.GC2764@roeck-us.net>
 <201208010845.19361.marex@denx.de>
 <20120801065650.GA2928@roeck-us.net>
 <20120801075010.GI1672@S2100-06.ap.freescale.net>
Message-ID: <20120801145837.GA15630@roeck-us.net>

On Wed, Aug 01, 2012 at 03:50:12PM +0800, Shawn Guo wrote:
> On Tue, Jul 31, 2012 at 11:56:50PM -0700, Guenter Roeck wrote:
> > Guess we are in violent agreement. The sequence would then either be
> > 	master = spi_alloc_device();
> 
> The discussion is around spi_alloc_master rather than spi_alloc_device,
> isn't it?
> 
Yes, sorry. Too late at night, too tired :(.

Guenter

> Regards,
> Shawn
> 
> > 	...
> > 	spi_master_put(master);
> > or
> > 	master = spi_alloc_device();
> > 	...
> > 	kfree(master);
> > 
> > which makes sense to me. Question still is why most drivers neither call kfree()
> > nor spi_master_put() in the remove function.
> 
> 


From konrad.wilk at oracle.com  Wed Aug  1 10:52:15 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:52:15 -0400
Subject: [PATCH 20/24] xen: update xen_add_to_physmap interface
In-Reply-To: <1343316846-25860-20-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-20-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801145215.GP7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:34:02PM +0100, Stefano Stabellini wrote:
> Update struct xen_add_to_physmap to be in sync with Xen's version of the
> structure.
> The size field was introduced by:
> 
> changeset:   24164:707d27fe03e7
> user:        Jean Guyader <jean.guyader at eu.citrix.com>
> date:        Fri Nov 18 13:42:08 2011 +0000
> summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range
> 
> According to the comment:
> 
> "This new field .size is located in the 16 bits padding between .domid
> and .space in struct xen_add_to_physmap to stay compatible with older
> versions."
> 
> This is not true on ARM where there is not padding, but it is valid on
> X86, so introducing size is safe on X86 and it is going to fix the
> interace for ARM.

Has this been checked actually for backwards compatibility? It sounds
like it should work just fine with Xen 4.0 right?

I believe this also helps Mukesh's patches, so CC-ing him here for
his Ack.

I can put this in right now in tree if we are 100% sure its compatiblie with 4.0.

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  include/xen/interface/memory.h |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index abbbff0..d8e33a9 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -163,6 +163,9 @@ struct xen_add_to_physmap {
>      /* Which domain to change the mapping for. */
>      domid_t domid;
>  
> +    /* Number of pages to go through for gmfn_range */
> +    uint16_t    size;
> +
>      /* Source mapping space. */
>  #define XENMAPSPACE_shared_info 0 /* shared info page */
>  #define XENMAPSPACE_grant_table 1 /* grant table page */
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:52:58 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:52:58 -0400
Subject: [PATCH 21/24] arm/v2m: initialize arch_timers even if v2m_timer
 is not present
In-Reply-To: <1343316846-25860-21-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-21-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801145257.GQ7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:34:03PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Should the maintainer of the v2m be CC-ed here?
This looks like a bug-fix of itself?

> ---
>  arch/arm/mach-vexpress/v2m.c |   11 ++++++-----
>  1 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> index fde26ad..dee1451 100644
> --- a/arch/arm/mach-vexpress/v2m.c
> +++ b/arch/arm/mach-vexpress/v2m.c
> @@ -637,16 +637,17 @@ static void __init v2m_dt_timer_init(void)
>  	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
>  	v2m_sysctl_init(of_iomap(node, 0));
>  
> -	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
> -	if (WARN_ON(err))
> -		return;
> -	node = of_find_node_by_path(path);
> -	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
>  	if (arch_timer_of_register() != 0)
>  		twd_local_timer_of_register();
>  
>  	if (arch_timer_sched_clock_init() != 0)
>  		versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> +
> +	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
> +	if (WARN_ON(err))
> +		return;
> +	node = of_find_node_by_path(path);
> +	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
>  }
>  
>  static struct sys_timer v2m_dt_timer = {
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:54:13 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:54:13 -0400
Subject: [PATCH 23/24] hvc_xen: allow dom0_write_console for HVM guests
In-Reply-To: <1343316846-25860-23-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-23-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801145413.GR7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:34:05PM +0100, Stefano Stabellini wrote:
> On ARM all guests are HVM guests, including Dom0.
> Allow dom0_write_console to be called by an HVM domain.

Um, but xen_hvm_domain() != xen_pv_domain() so won't this return without
printing anything?

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/tty/hvc/hvc_xen.c |    5 +----
>  1 files changed, 1 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
> index 3c04fb8..949edc2 100644
> --- a/drivers/tty/hvc/hvc_xen.c
> +++ b/drivers/tty/hvc/hvc_xen.c
> @@ -616,12 +616,9 @@ static void xenboot_write_console(struct console *console, const char *string,
>  	unsigned int linelen, off = 0;
>  	const char *pos;
>  
> -	if (!xen_pv_domain())
> -		return;
> -
>  	dom0_write_console(0, string, len);
>  
> -	if (xen_initial_domain())
> +	if (!xen_pv_domain())
>  		return;
>  
>  	domU_write_console(0, "(early) ", 8);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Wed Aug  1 10:56:10 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Wed, 1 Aug 2012 10:56:10 -0400
Subject: [PATCH 24/24] [HACK] xen/arm: implement xen_remap_domain_mfn_range
In-Reply-To: <1343316846-25860-24-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-24-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120801145610.GS7227@phenom.dumpdata.com>

On Thu, Jul 26, 2012 at 04:34:06PM +0100, Stefano Stabellini wrote:
> From: Ian Campbell <Ian.Campbell at citrix.com>
> 
> Do not apply!

Mukesh, I believe this is similar to what you had in mind.

> 
> This is a simple, hacky implementation of xen_remap_domain_mfn_range,
> using XENMAPSPACE_gmfn_foreign.
> 
> It should use same interface as hybrid x86.

Yeah.. We should get this done irrespective of this ARM patchset as
it will certainly benefit the HVM domains.

So  what is with the 0x9000 values?

> 
> Signed-off-by: Ian Campbell <Ian.Campbell at citrix.com>
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c       |   79 +++++++++++++++++++++++++++++++++++++++-
>  drivers/xen/privcmd.c          |   16 +++++----
>  drivers/xen/xenfs/super.c      |    7 ++++
>  include/xen/interface/memory.h |   10 ++++--
>  4 files changed, 101 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 1476b0b..7092015 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -16,6 +16,10 @@
>  #include <linux/of.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_address.h>
> +#include <linux/mm.h>
> +#include <linux/ioport.h>
> +
> +#include <asm/pgtable.h>
>  
>  struct start_info _xen_start_info;
>  struct start_info *xen_start_info = &_xen_start_info;
> @@ -38,12 +42,85 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
>  
>  static __read_mostly int xen_events_irq = -1;
>  
> +#define FOREIGN_MAP_BUFFER 0x90000000UL
> +#define FOREIGN_MAP_BUFFER_SIZE 0x10000000UL
> +struct resource foreign_map_resource = {
> +	.start = FOREIGN_MAP_BUFFER,
> +	.end = FOREIGN_MAP_BUFFER + FOREIGN_MAP_BUFFER_SIZE,
> +	.name = "Xen foreign map buffer",
> +	.flags = 0,
> +};
> +
> +static unsigned long foreign_map_buffer_pfn = FOREIGN_MAP_BUFFER >> PAGE_SHIFT;
> +
> +struct remap_data {
> +	struct mm_struct *mm;
> +	unsigned long mfn;
> +	pgprot_t prot;
> +};
> +
> +static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
> +				 unsigned long addr, void *data)
> +{
> +	struct remap_data *rmd = data;
> +	pte_t pte = pfn_pte(rmd->mfn, rmd->prot);
> +
> +	if (rmd->mfn < 0x90010)
> +		pr_crit("%s: ptep %p addr %#lx => %#x / %#lx\n",
> +		       __func__, ptep, addr, pte_val(pte), rmd->mfn);
> +
> +	set_pte_at(rmd->mm, addr, ptep, pte);
> +
> +	rmd->mfn++;
> +	return 0;
> +}
> +
>  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  			       unsigned long addr,
>  			       unsigned long mfn, int nr,
>  			       pgprot_t prot, unsigned domid)
>  {
> -	return -ENOSYS;
> +	int i, rc = 0;
> +	struct remap_data rmd = {
> +		.mm = vma->vm_mm,
> +		.prot = prot,
> +	};
> +	struct xen_add_to_physmap xatp = {
> +		.domid = DOMID_SELF,
> +		.space = XENMAPSPACE_gmfn_foreign,
> +
> +		.foreign_domid = domid,
> +	};
> +
> +	if (foreign_map_buffer_pfn + nr > ((FOREIGN_MAP_BUFFER +
> +					FOREIGN_MAP_BUFFER_SIZE)>>PAGE_SHIFT)) {
> +		pr_crit("RAM out of foreign map buffers...\n");
> +		return -EBUSY;
> +	}
> +
> +	for (i = 0; i < nr; i++) {
> +		xatp.idx = mfn + i;
> +		xatp.gpfn = foreign_map_buffer_pfn + i;
> +		rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
> +		if (rc != 0) {
> +			pr_crit("foreign map add_to_physmap failed, err=%d\n", rc);
> +			goto out;
> +		}
> +	}
> +
> +	rmd.mfn = foreign_map_buffer_pfn;
> +	rc = apply_to_page_range(vma->vm_mm,
> +				 addr,
> +				 (unsigned long)nr << PAGE_SHIFT,
> +				 remap_area_mfn_pte_fn, &rmd);
> +	if (rc != 0) {
> +		pr_crit("apply_to_page_range failed rc=%d\n", rc);
> +		goto out;
> +	}
> +
> +	foreign_map_buffer_pfn += nr;
> +out:
> +	return rc;
>  }
>  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
>  
> diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
> index 85226cb..3e15c22 100644
> --- a/drivers/xen/privcmd.c
> +++ b/drivers/xen/privcmd.c
> @@ -20,6 +20,8 @@
>  #include <linux/pagemap.h>
>  #include <linux/seq_file.h>
>  #include <linux/miscdevice.h>
> +#include <linux/resource.h>
> +#include <linux/ioport.h>
>  
>  #include <asm/pgalloc.h>
>  #include <asm/pgtable.h>
> @@ -196,9 +198,6 @@ static long privcmd_ioctl_mmap(void __user *udata)
>  	LIST_HEAD(pagelist);
>  	struct mmap_mfn_state state;
>  
> -	if (!xen_initial_domain())
> -		return -EPERM;
> -
>  	if (copy_from_user(&mmapcmd, udata, sizeof(mmapcmd)))
>  		return -EFAULT;
>  
> @@ -286,9 +285,6 @@ static long privcmd_ioctl_mmap_batch(void __user *udata)
>  	LIST_HEAD(pagelist);
>  	struct mmap_batch_state state;
>  
> -	if (!xen_initial_domain())
> -		return -EPERM;
> -
>  	if (copy_from_user(&m, udata, sizeof(m)))
>  		return -EFAULT;
>  
> @@ -365,6 +361,11 @@ static long privcmd_ioctl(struct file *file,
>  	return ret;
>  }
>  
> +static void privcmd_close(struct vm_area_struct *vma)
> +{
> +	/* TODO: unmap VMA */
> +}
> +
>  static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
>  {
>  	printk(KERN_DEBUG "privcmd_fault: vma=%p %lx-%lx, pgoff=%lx, uv=%p\n",
> @@ -375,7 +376,8 @@ static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
>  }
>  
>  static struct vm_operations_struct privcmd_vm_ops = {
> -	.fault = privcmd_fault
> +	.fault = privcmd_fault,
> +	.close = privcmd_close,
>  };
>  
>  static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
> diff --git a/drivers/xen/xenfs/super.c b/drivers/xen/xenfs/super.c
> index a84b53c..edbe22f 100644
> --- a/drivers/xen/xenfs/super.c
> +++ b/drivers/xen/xenfs/super.c
> @@ -12,6 +12,7 @@
>  #include <linux/module.h>
>  #include <linux/fs.h>
>  #include <linux/magic.h>
> +#include <linux/ioport.h>
>  
>  #include <xen/xen.h>
>  
> @@ -80,6 +81,8 @@ static const struct file_operations capabilities_file_ops = {
>  	.llseek = default_llseek,
>  };
>  
> +extern struct resource foreign_map_resource;
> +
>  static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
>  {
>  	static struct tree_descr xenfs_files[] = {
> @@ -100,6 +103,10 @@ static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
>  				  &xsd_kva_file_ops, NULL, S_IRUSR|S_IWUSR);
>  		xenfs_create_file(sb, sb->s_root, "xsd_port",
>  				  &xsd_port_file_ops, NULL, S_IRUSR|S_IWUSR);
> +		rc = request_resource(&iomem_resource, &foreign_map_resource);
> +		if (rc < 0)
> +			pr_crit("failed to register foreign map resource\n");
> +		rc = 0; /* ignore */
>  	}
>  
>  	return rc;
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index d8e33a9..ec68945 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -167,9 +167,13 @@ struct xen_add_to_physmap {
>      uint16_t    size;
>  
>      /* Source mapping space. */
> -#define XENMAPSPACE_shared_info 0 /* shared info page */
> -#define XENMAPSPACE_grant_table 1 /* grant table page */
> -    unsigned int space;
> +#define XENMAPSPACE_shared_info  0 /* shared info page */
> +#define XENMAPSPACE_grant_table  1 /* grant table page */
> +#define XENMAPSPACE_gmfn         2 /* GMFN */
> +#define XENMAPSPACE_gmfn_range   3 /* GMFN range */
> +#define XENMAPSPACE_gmfn_foreign 4 /* GMFN from another guest */
> +    uint16_t space;
> +    domid_t foreign_domid; /* IFF gmfn_foreign */
>  
>      /* Index into source mapping space. */
>      unsigned long idx;
> -- 
> 1.7.2.5


From paul at pwsan.com  Wed Aug  1 11:08:59 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 1 Aug 2012 09:08:59 -0600 (MDT)
Subject: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain
 transitioning to OFF when in-use
In-Reply-To: <50187644.40308@ti.com>
References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com>
 <1339104132-26885-9-git-send-email-jon-hunter@ti.com>
 <alpine.DEB.2.00.1207111441300.25585@utopia.booyaka.com>
 <500028B3.1040309@ti.com>
 <alpine.DEB.2.00.1207131418500.25585@utopia.booyaka.com>
 <50045D17.9050704@ti.com>
 <alpine.DEB.2.00.1207161228470.28834@utopia.booyaka.com>
 <50171841.40309@ti.com> <501760BF.8070801@ti.com> <5018210A.1040902@ti.com>
 <50187644.40308@ti.com>
Message-ID: <alpine.DEB.2.00.1208010906470.21488@utopia.booyaka.com>

Hi Jon,

On Tue, 31 Jul 2012, Jon Hunter wrote:

> Sorry for all the emails. However, I wanted to get this out to you as
> I am due to be out for a couple weeks. 
> 
> So I have updated your patch [1] with the following changes ...
> 
> 1. Re-based on top of your omap3 clock domain fix [2]
> 2. Modified the above change I mentioned to check for
>    CLKDM_MISSING_IDLE_REPORTING in omap_pm_clkdms_setup() instead of
>    the omap2_clkdm_clk_enable(). This is to prevent the clock domain
>    being placed in HW_AUTO on boot if enabled early.
> 3. Made the other change I mentioned earlier [3].
> 
> This is now working well for me on OMAP3/4.

Your changes look good to me.  Do you have a strong preference as to 
whether that patch should go in as part of 3.6-rc or 3.7?  I'd be inclined 
to queue it for 3.7 based on the size of the patch.


- Paul


From festevam at gmail.com  Wed Aug  1 11:10:36 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  1 Aug 2012 12:10:36 -0300
Subject: [RFC] ARM: imx6q-sabrelite: Add CLKO IOMUX
Message-ID: <1343833836-14287-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

In order to have audio functional on mx6qsabrelite, it is necessary to setup
the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO and MX6Q_PAD_GPIO_3__CCM_CLKO2 pins.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Dirk,

Not tested. If you have a chance to try it, please let me know.

 arch/arm/boot/dts/imx6q-sabrelite.dts |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d42e851..f22c089 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -53,6 +53,8 @@
 						fsl,pins = <
 							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
 							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+							   953  0x00000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */
+							   979  0x00000004	/* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
 							   >;
 					};
 				};
-- 
1.7.1



From arnd at arndb.de  Wed Aug  1 11:20:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 1 Aug 2012 15:20:01 +0000
Subject: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
Message-ID: <201208011520.02353.arnd@arndb.de>

On Wednesday 01 August 2012, Praveen Paneri wrote:
> This patch set introduces a phy driver for samsung SoCs. It uses the existing
> transceiver infrastructure to provide phy control functions. Use of this driver
> can be extended for usb host phy as well. Over the period of time all the phy
> related code for most of the samsung SoCs can be integrated here.
> Removing the existing phy code from mach-s3c64xx but not from other machine 
> code.This driver is tested with smdk6410 and Exynos4210(with DT).

This looks very nice overall, great work!

We will still have to take care of the pmu isolation callback in the
long run, when we get to the point of removing all auxdata. Do you
have a plan on how to do that? If yes, it would be good to mention
that in the changelog.

My guess is that the PMU code should be moved into a higher-level
abstraction. I don't know if you would use one of those we already
have or whether you'd introduce a new subsystem for those. Apparently
other platforms have similar issues, so I'd suggest you leave the
callback for now, but we should at some point discuss what to to
about it.

	Arnd


From paul at pwsan.com  Wed Aug  1 11:36:13 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 1 Aug 2012 09:36:13 -0600 (MDT)
Subject: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain
 transitioning to OFF when in-use
In-Reply-To: <50187644.40308@ti.com>
References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com>
 <1339104132-26885-9-git-send-email-jon-hunter@ti.com>
 <alpine.DEB.2.00.1207111441300.25585@utopia.booyaka.com>
 <500028B3.1040309@ti.com>
 <alpine.DEB.2.00.1207131418500.25585@utopia.booyaka.com>
 <50045D17.9050704@ti.com>
 <alpine.DEB.2.00.1207161228470.28834@utopia.booyaka.com>
 <50171841.40309@ti.com> <501760BF.8070801@ti.com> <5018210A.1040902@ti.com>
 <50187644.40308@ti.com>
Message-ID: <alpine.DEB.2.00.1208010932270.21488@utopia.booyaka.com>

Hi Jon et al,

Here's what I'm planning to queue here.  The only changes from what Jon
posted are the patch changelog and some checkpatch fixes.  If anyone
has any final comments, please let me know.


- Paul

From: Paul Walmsley <paul at pwsan.com>
Date: Wed, 1 Aug 2012 09:11:20 -0600
Subject: [PATCH] ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU
 clockdomain idle problems

The idle status of the IP blocks and clocks inside the EMU clockdomain
isn't taken into account by the PRCM hardware when deciding whether
the clockdomain is idle.  Add a workaround flag in the clockdomain
code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
the code necessary to support it.

If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
clockdomain will be forced active whenever an IP block inside that
clockdomain is in use, even if the clockdomain supports
hardware-supervised idle.  When the kernel indicates that the last
active IP block inside the clockdomain is no longer used, the
clockdomain will be forced idle, or, if that mode is not supported in
the hardware, it will be placed into hardware-supervised idle.

This patch is an equal collaboration with Jon Hunter
<jon-hunter at ti.com>.  Ming Lei <ming.lei at canonical.com>, Will Deacon
<will.deacon at arm.com>, Madhav Vij <mvij at ti.com>, Kevin Hilman
<khilman at ti.com>, Beno?t Cousson <b-cousson at ti.com>, and Santosh
Shilimkar <santosh.shilimkar at ti.com> all made essential contributions
to the understanding of EMU clockdomain power management on OMAP.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Jon Hunter <jon-hunter at ti.com>
Cc: Ming Lei <ming.lei at canonical.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Madhav Vij <mvij at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/clockdomain.c           |   17 +++++++++++++++++
 arch/arm/mach-omap2/clockdomain.h           |   20 +++++++++++++++++---
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c  |   22 ++++++++++++++++++++++
 arch/arm/mach-omap2/clockdomain44xx.c       |   11 +++++++++++
 arch/arm/mach-omap2/clockdomains3xxx_data.c |    7 ++-----
 arch/arm/mach-omap2/clockdomains44xx_data.c |    3 ++-
 arch/arm/mach-omap2/omap_hwmod.c            |    3 ++-
 arch/arm/mach-omap2/pm.c                    |    3 ++-
 8 files changed, 75 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index b851ba4..17b1d32 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -914,6 +914,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
 	return ret;
 }
 
+/**
+ * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm has the
+ * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
+ * null.  More information is available in the documentation for the
+ * CLKDM_MISSING_IDLE_REPORTING macro.
+ */
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
+{
+	if (!clkdm)
+		return false;
+
+	return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
+}
+
 /* Clockdomain-to-clock/hwmod framework interface code */
 
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 7b3c1d2..fb5d37f 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
  * OMAP2/3 clockdomain framework functions
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Paul Walmsley
@@ -34,6 +32,20 @@
  * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
  *     active whenever the MPU is active.  True for interconnects and
  *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
  */
 #define CLKDM_CAN_FORCE_SLEEP			(1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP			(1 << 1)
@@ -41,6 +53,7 @@
 #define CLKDM_CAN_DISABLE_AUTO			(1 << 3)
 #define CLKDM_NO_AUTODEPS			(1 << 4)
 #define CLKDM_ACTIVE_WITH_MPU			(1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING		(1 << 6)
 
 #define CLKDM_CAN_HWSUP		(CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP		(CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -188,6 +201,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
 
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f99e65c..3f4b04b 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -248,6 +248,17 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
 	if (!clkdm->clktrctrl_mask)
 		return 0;
 
+	/*
+	 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+	 * more details on the unpleasant problem this is working
+	 * around
+	 */
+	if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+	    (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+		omap3_clkdm_wakeup(clkdm);
+		return 0;
+	}
+
 	hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 				clkdm->clktrctrl_mask);
 
@@ -271,6 +282,17 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
 	if (!clkdm->clktrctrl_mask)
 		return 0;
 
+	/*
+	 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+	 * more details on the unpleasant problem this is working
+	 * around
+	 */
+	if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+	    !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+		_enable_hwsup(clkdm);
+		return 0;
+	}
+
 	hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 				clkdm->clktrctrl_mask);
 
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 762f2cc..6fc6155 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
 	if (!clkdm->prcm_partition)
 		return 0;
 
+	/*
+	 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+	 * more details on the unpleasant problem this is working
+	 * around
+	 */
+	if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+	    !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+		omap4_clkdm_allow_idle(clkdm);
+		return 0;
+	}
+
 	hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
 					clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 56089c4..933a35c 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
 	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
 static struct clockdomain emu_clkdm = {
 	.name		= "emu_clkdm",
 	.pwrdm		= { .name = "emu_pwrdm" },
-	.flags		= /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+	.flags		= (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
+			   CLKDM_MISSING_IDLE_REPORTING),
 	.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 63d60a7..b56d06b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
 	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,
 	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
-	.flags		  = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
+	.flags		  = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
+			     CLKDM_MISSING_IDLE_REPORTING),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..36f0603 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1857,7 +1857,8 @@ static int _enable(struct omap_hwmod *oh)
 		 * completely the module. The clockdomain can be set
 		 * in HW_AUTO only when the module become ready.
 		 */
-		hwsup = clkdm_in_hwsup(oh->clkdm);
+		hwsup = clkdm_in_hwsup(oh->clkdm) &&
+			!clkdm_missing_idle_reporting(oh->clkdm);
 		r = clkdm_hwmod_enable(oh->clkdm, oh);
 		if (r) {
 			WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..4182564 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -80,7 +80,8 @@ static void __init omap2_init_processor_devices(void)
 
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+	if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
+	    !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
 		clkdm_allow_idle(clkdm);
 	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 		 atomic_read(&clkdm->usecount) == 0)
-- 
1.7.10.4

From cyril at ti.com  Wed Aug  1 11:41:08 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Wed, 1 Aug 2012 11:41:08 -0400
Subject: [RFC 20/22] ARM: keystone: introducing TI Keystone platform
In-Reply-To: <201207312316.19592.arnd@arndb.de>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-21-git-send-email-cyril@ti.com>
 <201207312316.19592.arnd@arndb.de>
Message-ID: <50194E14.4070301@ti.com>

On 7/31/2012 7:16 PM, Arnd Bergmann wrote:
> On Tuesday 31 July 2012, Cyril Chemparathy wrote:
>> Texas Instruments Keystone family of multicore devices now includes an
>> upcoming slew of Cortex A15 based devices.  This patch adds basic definitions
>> for a new Keystone sub-architecture in ARM.
>>
>> Subsequent patches in this series will extend support to include SMP and take
>> advantage of the large physical memory addressing capabilities via LPAE.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
>

Thanks for taking a look, Arnd.

Any inputs on the other patches in this series?  I'd ideally like to 
have the LPAE fixes, and code patching changes merged in sooner than the 
Keystone machine specific stuff.

> And some nitpicking:
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 debug earlyprintk lpj=50000 rdinit=/bin/ash rw root=/dev/ram0 initrd=0x85000000,9M";
>> +	};
>
> This command line should not really be here. Most of what you put in it is not
> generic to the platform at all.
>
> In order to select the console, use an alias for the serial device.
>

Agreed.  The DTS in general needs quite a bit of work.

>> +
>> +static void __init keystone_map_io(void)
>> +{
>> +	iotable_init(io_desc, sizeof(io_desc)/sizeof(struct map_desc));
>> +}
>
> Use the ARRAY_SIZE macro here.
>

Thanks.  I've fixed this in the code, and this will show up in the next rev.

> 	Arnd
>

-- 
Thanks
- Cyril


From cyril at ti.com  Wed Aug  1 11:42:12 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Wed, 1 Aug 2012 11:42:12 -0400
Subject: [PATCH 06/22] ARM: LPAE: use phys_addr_t in alloc_init_pud()
In-Reply-To: <50191C46.4090902@mvista.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-7-git-send-email-cyril@ti.com>
 <50191C46.4090902@mvista.com>
Message-ID: <50194E54.5040909@ti.com>

On 8/1/2012 8:08 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 01-08-2012 3:04, Cyril Chemparathy wrote:
>
>> From: Vitaly Andrianov <vitalya at ti.com>
>
>> This patch fixes the alloc_init_pud() function to use phys_addr_t
>> instead of
>> unsigned long when passing in the phys argument.
>
>> This is an extension to commit
>> 97092e0c56830457af0639f6bd904537a150ea4a, which
>
>     Please also specify that commit's summary in parens.

Thanks Sergei.  Will do so.  I'm assuming you meant headline and not 
summary.

>
>> applied similar changes elsewhere in the ARM memory management code.
>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> WBR, Sergei
>

-- 
Thanks
- Cyril


From stefano.stabellini at eu.citrix.com  Wed Aug  1 11:45:40 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 16:45:40 +0100
Subject: [PATCH 07/24] xen/arm: Xen detection and shared_info page mapping
In-Reply-To: <20120801141959.GE7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-7-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801141959.GE7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011641410.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:49PM +0100, Stefano Stabellini wrote:
> > Check for a "/xen" node in the device tree, if it is present set
> > xen_domain_type to XEN_HVM_DOMAIN and continue initialization.
> > 
> > Map the real shared info page using XENMEM_add_to_physmap with
> > XENMAPSPACE_shared_info.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/enlighten.c |   56 ++++++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 56 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index d27c2a6..8c923af 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -5,6 +5,9 @@
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> >  #include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> >  
> >  struct start_info _xen_start_info;
> >  struct start_info *xen_start_info = &_xen_start_info;
> > @@ -33,3 +36,56 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
> >  	return -ENOSYS;
> >  }
> >  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> > +
> > +/*
> > + * == Xen Device Tree format ==
> > + * - /xen node;
> > + * - compatible "arm,xen";
> > + * - one interrupt for Xen event notifications;
> > + * - one memory region to map the grant_table.
> > + */
> > +static int __init xen_guest_init(void)
> > +{
> > +	int cpu;
> > +	struct xen_add_to_physmap xatp;
> > +	static struct shared_info *shared_info_page = 0;
> > +	struct device_node *node;
> > +
> > +	node = of_find_compatible_node(NULL, NULL, "arm,xen");
> > +	if (!node) {
> > +		pr_info("No Xen support\n");
> 
> I don't think the pr_info is appropiate here?

Yes, you are right. In fact I had already turned it into a pr_debug.

> > +		return 0;
> 
> Should this be -ENODEV?

Considering that xen_guest_init is called by a core_initcall, I didn't
want to return an error just because Xen is not present on the platform.


> > +	}
> > +	xen_domain_type = XEN_HVM_DOMAIN;
> > +
> > +	if (!shared_info_page)
> > +		shared_info_page = (struct shared_info *)
> > +			get_zeroed_page(GFP_KERNEL);
> > +	if (!shared_info_page) {
> > +		pr_err("not enough memory");
> 
> \n

OK

> > +		return -ENOMEM;
> > +	}
> > +	xatp.domid = DOMID_SELF;
> > +	xatp.idx = 0;
> > +	xatp.space = XENMAPSPACE_shared_info;
> > +	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
> > +	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
> > +		BUG();
> > +
> > +	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
> > +
> > +	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
> > +	 * page, we use it in the event channel upcall and in some pvclock
> > +	 * related functions. We don't need the vcpu_info placement
> > +	 * optimizations because we don't use any pv_mmu or pv_irq op on
> > +	 * HVM.
> > +	 * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
> > +	 * online but xen_hvm_init_shared_info is run at resume time too and
> > +	 * in that case multiple vcpus might be online. */
> > +	for_each_online_cpu(cpu) {
> > +		per_cpu(xen_vcpu, cpu) =
> > +			&HYPERVISOR_shared_info->vcpu_info[cpu];
> > +	}
> > +	return 0;
> 
> This above looks stringly similar to the x86 one. Could it be
> abstracted away to share the same code? Or is that something that
> ought to be done later on when there is more meat on the bone?

Actually I had to remove these three lines because on ARM we are going
to have just one vcpu_info struct in the shared_info page and then rely
on VCPUOP_register_vcpu_info.


From stefano.stabellini at eu.citrix.com  Wed Aug  1 11:46:02 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 16:46:02 +0100
Subject: [PATCH 05/24] xen/arm: empty implementation of grant_table arch
 specific functions
In-Reply-To: <20120801141624.GD7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-5-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801141624.GD7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011641110.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:47PM +0100, Stefano Stabellini wrote:
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/Makefile      |    2 +-
> >  arch/arm/xen/grant-table.c |   53 ++++++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 54 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/xen/grant-table.c
> > 
> > diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> > index b9d6acc..4384103 100644
> > --- a/arch/arm/xen/Makefile
> > +++ b/arch/arm/xen/Makefile
> > @@ -1 +1 @@
> > -obj-y		:= enlighten.o hypercall.o
> > +obj-y		:= enlighten.o hypercall.o grant-table.o
> > diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
> > new file mode 100644
> > index 0000000..0a4ee80
> > --- /dev/null
> > +++ b/arch/arm/xen/grant-table.c
> > @@ -0,0 +1,53 @@
> > +/******************************************************************************
> > + * grant_table.c
> > + * ARM specific part
> > + *
> > + * Granting foreign access to our memory reservation.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation; or, when distributed
> > + * separately from the Linux kernel or incorporated into other
> > + * software packages, subject to the following license:
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > + * of this source file (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use, copy, modify,
> > + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> > + * and to permit persons to whom the Software is furnished to do so, subject to
> > + * the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> > + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include <xen/interface/xen.h>
> > +#include <xen/page.h>
> > +#include <xen/grant_table.h>
> > +
> > +int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
> > +			   unsigned long max_nr_gframes,
> > +			   void **__shared)
> > +{
> > +	return -1;
> 
> -ENOSYS
> > +}
> > +
> > +void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
> > +{
> > +	return;
> > +}
> > +
> > +int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
> > +			   unsigned long max_nr_gframes,
> > +			   grant_status_t **__shared)
> > +{
> > +	return -1;
> 
> Same here -ENOSYS

OK, I'll do that


From stefano.stabellini at eu.citrix.com  Wed Aug  1 11:50:59 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 16:50:59 +0100
Subject: [PATCH 08/24] xen/arm: Introduce xen_pfn_t for pfn and mfn types
In-Reply-To: <20120801142249.GF7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-8-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801142249.GF7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011646560.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:50PM +0100, Stefano Stabellini wrote:
> > All the original Xen headers have xen_pfn_t as mfn and pfn type, however
> > when they have been imported in Linux, xen_pfn_t has been replaced with
> > unsigned long. That might work for x86 and ia64 but it does not for arm.
> 
> How come?

see below

> > Bring back xen_pfn_t and let each architecture define xen_pfn_t as they
> > see fit.
> 
> I am OK with this as long as your include a comment in both of the
> interface.h saying why this is needed. I am curious why 'unsinged long'
> won't work? Is it b/c on ARM you always want a 64-bit type?

Yes, we would like to make the same interface work for 32 and 64
bit guests, without any need for a "compat layer" as we currently have
on x86.
In fact I am going to add another patch to explicitly size all the
other unsigned long that we have in the public interface.


From liuj97 at gmail.com  Wed Aug  1 11:54:17 2012
From: liuj97 at gmail.com (Jiang Liu)
Date: Wed,  1 Aug 2012 23:54:17 +0800
Subject: [PATCH v3 12/32] PCI/ARM: use PCIe capabilities access functions to
 simplify implementation
In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
Message-ID: <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>

From: Jiang Liu <jiang.liu at huawei.com>

Use PCIe capabilities access functions to simplify PCIe ARM implementation.

Signed-off-by: Jiang Liu <liuj97 at gmail.com>
---
 arch/arm/mach-tegra/pcie.c |   13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 0e09137..5f99d33 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -367,17 +367,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
 /* Tegra PCIE requires relaxed ordering */
 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
 {
-	u16 val16;
-	int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-
-	if (pos <= 0) {
-		dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
-		return;
-	}
-
-	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
-	val16 |= PCI_EXP_DEVCTL_RELAX_EN;
-	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
+	pci_pcie_capability_change_word(dev, PCI_EXP_DEVCTL,
+					PCI_EXP_DEVCTL_RELAX_EN, 0);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
 
-- 
1.7.9.5



From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:04:45 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:04:45 +0100
Subject: [PATCH 23/24] hvc_xen: allow dom0_write_console for HVM guests
In-Reply-To: <20120801145413.GR7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-23-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801145413.GR7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011704000.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:34:05PM +0100, Stefano Stabellini wrote:
> > On ARM all guests are HVM guests, including Dom0.
> > Allow dom0_write_console to be called by an HVM domain.
> 
> Um, but xen_hvm_domain() != xen_pv_domain() so won't this return without
> printing anything?

Nope, it would call dom0_write_console that issues a console hypercall.
However I am going to remove this patch and rely on the simple serial
emulator we have in Xen for early_printk stuff

> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  drivers/tty/hvc/hvc_xen.c |    5 +----
> >  1 files changed, 1 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
> > index 3c04fb8..949edc2 100644
> > --- a/drivers/tty/hvc/hvc_xen.c
> > +++ b/drivers/tty/hvc/hvc_xen.c
> > @@ -616,12 +616,9 @@ static void xenboot_write_console(struct console *console, const char *string,
> >  	unsigned int linelen, off = 0;
> >  	const char *pos;
> >  
> > -	if (!xen_pv_domain())
> > -		return;
> > -
> >  	dom0_write_console(0, string, len);
> >  
> > -	if (xen_initial_domain())
> > +	if (!xen_pv_domain())
> >  		return;
> >  
> >  	domU_write_console(0, "(early) ", 8);
> > -- 
> > 1.7.2.5
> 


From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:06:42 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:06:42 +0100
Subject: [PATCH 21/24] arm/v2m: initialize arch_timers even if v2m_timer
 is not present
In-Reply-To: <20120801145257.GQ7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-21-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801145257.GQ7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011705100.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:34:03PM +0100, Stefano Stabellini wrote:
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> 
> Should the maintainer of the v2m be CC-ed here?
> This looks like a bug-fix of itself?

I think so. I'll CC Russell King next time.

> > ---
> >  arch/arm/mach-vexpress/v2m.c |   11 ++++++-----
> >  1 files changed, 6 insertions(+), 5 deletions(-)
> > 
> > diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
> > index fde26ad..dee1451 100644
> > --- a/arch/arm/mach-vexpress/v2m.c
> > +++ b/arch/arm/mach-vexpress/v2m.c
> > @@ -637,16 +637,17 @@ static void __init v2m_dt_timer_init(void)
> >  	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
> >  	v2m_sysctl_init(of_iomap(node, 0));
> >  
> > -	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
> > -	if (WARN_ON(err))
> > -		return;
> > -	node = of_find_node_by_path(path);
> > -	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
> >  	if (arch_timer_of_register() != 0)
> >  		twd_local_timer_of_register();
> >  
> >  	if (arch_timer_sched_clock_init() != 0)
> >  		versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
> > +
> > +	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
> > +	if (WARN_ON(err))
> > +		return;
> > +	node = of_find_node_by_path(path);
> > +	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
> >  }
> >  
> >  static struct sys_timer v2m_dt_timer = {
> > -- 
> > 1.7.2.5
> 


From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:07:42 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:07:42 +0100
Subject: [Xen-devel] [PATCH 04/24] xen/arm: sync_bitops
In-Reply-To: <20120801143551.GI7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-4-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120726163759.GE9222@phenom.dumpdata.com>
 <1343381305.6812.116.camel@zakaz.uk.xensource.com>
 <20120801143551.GI7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011707280.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Fri, Jul 27, 2012 at 10:28:25AM +0100, Ian Campbell wrote:
> > On Thu, 2012-07-26 at 17:37 +0100, Konrad Rzeszutek Wilk wrote:
> > > On Thu, Jul 26, 2012 at 04:33:46PM +0100, Stefano Stabellini wrote:
> > > > sync_bitops functions are equivalent to the SMP implementation of the
> > > > original functions, independently from CONFIG_SMP being defined.
> > > 
> > > So why can't the code be changed to use that? Is it that
> > > the _set_bit, _clear_bit, etc are not available with !CONFIG_SMP?
> > 
> > _set_bit etc are not SMP safe if !CONFIG_SMP. But under Xen you might be
> > communicating with a completely external entity who might be on another
> > CPU (e.g. two uniprocessor guests communicating via event channels and
> > grant tables). So we need a variant of the bit ops which are SMP safe
> > even on a UP kernel.
> > 
> > The users are common code and the sync_foo vs foo distinction matters on
> > some platforms (e.g. x86 where a UP kernel would omit the LOCK prefix
> > for the normal ones).
> 
> OK, that makes sense. Stefano can you include that comment in the git
> commit description and in the sync_bitops.h file please?

Yep, I'll do that.



From broonie at opensource.wolfsonmicro.com  Wed Aug  1 12:08:24 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 17:08:24 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <50193428.5000708@linaro.org>
References: <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
Message-ID: <20120801160824.GB11892@opensource.wolfsonmicro.com>

On Wed, Aug 01, 2012 at 02:50:32PM +0100, Lee Jones wrote:

> I am under the impression that it was tested. Perhaps before it was
> rebased, but tests were completed. Ola was very surprised when I
> told him there were link failures. The only issue is that I only
> found out and told him a day before he was due to take his Summer
> leave.

That's really surprising.  What are the actual issues here, you've never
shown the actual errors?

> >It's very disappointing to see such an error exist, and even more
> >disappointing that there's no interest in fixing the driver.

> This is incorrect. I'm sure the driver will be fixed post-haste when
> Ola returns back from vacation. If I can find some time I might
> dabble in the mean-time also.

It may not be what you're intending but it's unfortuantely what's I'm
seeing.


From swarren at wwwdotorg.org  Wed Aug  1 12:07:27 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 01 Aug 2012 10:07:27 -0600
Subject: [PATCH v3 09/10] of: Add of_pci_parse_ranges()
In-Reply-To: <20120801065437.GB26791@avionic-0098.adnet.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-10-git-send-email-thierry.reding@avionic-design.de>
 <50183B03.2090809@gmail.com>
 <20120801065437.GB26791@avionic-0098.adnet.avionic-design.de>
Message-ID: <5019543F.3080601@wwwdotorg.org>

On 08/01/2012 12:54 AM, Thierry Reding wrote:
> On Tue, Jul 31, 2012 at 03:07:31PM -0500, Rob Herring wrote:
>> On 07/26/2012 02:55 PM, Thierry Reding wrote:
>>> This new function parses the ranges property of PCI device
>>> nodes into an array of struct resource elements. It is useful
>>> in multiple-port PCI host controller drivers to collect
>>> information about the ranges that it needs to forward to the
>>> respective ports.
>> 
>> It seems to me that some of the DT PCI code in
>> arch/powerpc/kernel/pci* like pci_process_bridge_OF_ranges()
>> should apply for ARM as well.
>> 
>> Each arch defining their own pci controller structs complicates
>> this, but I would think at least the DT parsing can be common.
> 
> Yes, there's quite a lot of room for refactoring. When I first
> started work on this there had been some discussion about whether
> it would make sense to move PCI controller drivers into a common
> location to make it easier to refactor but the consensus at the
> time was that this should not be done.

In the long term, if we end up with a separate arch/aarch64/, I think
we'll have to move the PCIe (and any other) drivers to a common
location. Still, I imagine there is plenty of time until that's mandatory.


From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:18:29 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:18:29 +0100
Subject: [PATCH 20/24] xen: update xen_add_to_physmap interface
In-Reply-To: <20120801145215.GP7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-20-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801145215.GP7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011716040.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:34:02PM +0100, Stefano Stabellini wrote:
> > Update struct xen_add_to_physmap to be in sync with Xen's version of the
> > structure.
> > The size field was introduced by:
> > 
> > changeset:   24164:707d27fe03e7
> > user:        Jean Guyader <jean.guyader at eu.citrix.com>
> > date:        Fri Nov 18 13:42:08 2011 +0000
> > summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range
> > 
> > According to the comment:
> > 
> > "This new field .size is located in the 16 bits padding between .domid
> > and .space in struct xen_add_to_physmap to stay compatible with older
> > versions."
> > 
> > This is not true on ARM where there is not padding, but it is valid on
> > X86, so introducing size is safe on X86 and it is going to fix the
> > interace for ARM.
> 
> Has this been checked actually for backwards compatibility? It sounds
> like it should work just fine with Xen 4.0 right?
> 
> I believe this also helps Mukesh's patches, so CC-ing him here for
> his Ack.
> 
> I can put this in right now in tree if we are 100% sure its compatiblie with 4.0.

Yes, it is: 4 bytes integers are 4-byte aligned on 32 bit and 64 bit
on x86.


From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:19:26 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:19:26 +0100
Subject: [PATCH 18/24] xen/arm: compile blkfront and blkback
In-Reply-To: <20120801144818.GO7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-18-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801144818.GO7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011719050.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:34:00PM +0100, Stefano Stabellini wrote:
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  drivers/block/xen-blkback/blkback.c  |    1 +
> >  include/xen/interface/io/protocols.h |    3 +++
> >  2 files changed, 4 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
> > index 73f196c..63dd5b9 100644
> > --- a/drivers/block/xen-blkback/blkback.c
> > +++ b/drivers/block/xen-blkback/blkback.c
> > @@ -42,6 +42,7 @@
> >  
> >  #include <xen/events.h>
> >  #include <xen/page.h>
> > +#include <xen/xen.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> >  #include "common.h"
> > diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
> > index 01fc8ae..0eafaf2 100644
> > --- a/include/xen/interface/io/protocols.h
> > +++ b/include/xen/interface/io/protocols.h
> > @@ -5,6 +5,7 @@
> >  #define XEN_IO_PROTO_ABI_X86_64     "x86_64-abi"
> >  #define XEN_IO_PROTO_ABI_IA64       "ia64-abi"
> >  #define XEN_IO_PROTO_ABI_POWERPC64  "powerpc64-abi"
> > +#define XEN_IO_PROTO_ABI_ARM        "arm-abi"
> 
> So one that has all of the 32/64 issues worked out? Nice.

Yes, that is the idea, but it needs another patch to actually achieve
the goal :)

> >  
> >  #if defined(__i386__)
> >  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
> > @@ -14,6 +15,8 @@
> >  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
> >  #elif defined(__powerpc64__)
> >  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
> > +#elif defined(__arm__)
> > +# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
> >  #else
> >  # error arch fixup needed here
> >  #endif
> > -- 
> > 1.7.2.5
> 


From stefano.stabellini at eu.citrix.com  Wed Aug  1 12:21:00 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 17:21:00 +0100
Subject: [PATCH 13/24] xen/arm: get privilege status
In-Reply-To: <20120801143946.GK7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-13-git-send-email-stefano.stabellini@eu.citrix.com>
 <1343382276.6812.126.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.02.1207271514140.26163@kaball.uk.xensource.com>
 <1343399630.25096.4.camel@zakaz.uk.xensource.com>
 <20120801143946.GK7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011719570.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Fri, Jul 27, 2012 at 03:33:50PM +0100, Ian Campbell wrote:
> > On Fri, 2012-07-27 at 15:25 +0100, Stefano Stabellini wrote:
> > > On Fri, 27 Jul 2012, Ian Campbell wrote:
> > > > On Thu, 2012-07-26 at 16:33 +0100, Stefano Stabellini wrote:
> > > > > Use Xen features to figure out if we are privileged.
> > > > > 
> > > > > XENFEAT_dom0 was introduced by 23735 in xen-unstable.hg.
> > > > > 
> > > > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > > > ---
> > > > >  arch/arm/xen/enlighten.c         |    7 +++++++
> > > > >  include/xen/interface/features.h |    3 +++
> > > > >  2 files changed, 10 insertions(+), 0 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > > > > index dc68074..2e013cf 100644
> > > > > --- a/arch/arm/xen/enlighten.c
> > > > > +++ b/arch/arm/xen/enlighten.c
> > > > > @@ -2,6 +2,7 @@
> > > > >  #include <xen/interface/xen.h>
> > > > >  #include <xen/interface/memory.h>
> > > > >  #include <xen/platform_pci.h>
> > > > > +#include <xen/features.h>
> > > > >  #include <asm/xen/hypervisor.h>
> > > > >  #include <asm/xen/hypercall.h>
> > > > >  #include <linux/module.h>
> > > > > @@ -58,6 +59,12 @@ int __init xen_guest_init(void)
> > > > >  	}
> > > > >  	xen_domain_type = XEN_HVM_DOMAIN;
> > > > >  
> > > > > +	xen_setup_features();
> > > > > +	if (xen_feature(XENFEAT_dom0))
> > > > > +		xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
> > > > > +	else
> > > > > +		xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
> > > > 
> > > > What happens here on platforms prior to hypervisor changeset 23735?
> > > 
> > > It wouldn't work.
> > > Considering that we are certainly not going to backport ARM support to
> > > Xen 4.1, and that both ARM and XENFEAT_dom0 will be present in Xen 4.2,
> > > do we really need to support the Xen unstable changesets between ARM was
> > > introduced and XENFEAT_dom0 appeared?
> 
> So should it just panic and say "AAAAAAH"?

I could panic if I find out that XENFEAT_dom0 is unimplemented but
actually I only get to know if it is available...


From swarren at wwwdotorg.org  Wed Aug  1 13:02:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 01 Aug 2012 11:02:18 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <20120801063545.GA26791@avionic-0098.adnet.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50180547.9040603@wwwdotorg.org>
 <20120801063545.GA26791@avionic-0098.adnet.avionic-design.de>
Message-ID: <5019611A.2060804@wwwdotorg.org>

On 08/01/2012 12:35 AM, Thierry Reding wrote:
> On Tue, Jul 31, 2012 at 10:18:15AM -0600, Stephen Warren wrote:
>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
>>> This patch series adds support for device tree based probing of
>>> the PCIe controller found on Tegra SoCs.
>> 
>> Thierry,
>> 
>> I think one thing that would help here would be to split up this
>> series into one per subsystem, and to get all the dependencies
>> merged by the respective maintainers. Preferably, each subsystem
>> would export a stable branch (perhaps consisting of just these
>> patches) that I can then merge into the Tegra tree and use as a
>> basis for the PCIe driver itself. Hopefully this approach will
>> get more traction on all the non-Tegra changes. Does that sound
>> like a good plan?
> 
> I don't understand. The series is already split up into
> per-subsystem patches. I just didn't want to post them separately
> so everybody on Cc would be able to see the big picture and the
> reason why the patch was required.

There are separate patches that touch the different subsystems, but
they're all scattered throughout the one series, rather than having e.g.:

* a series for the PCI tree
* a series for the ARM core tree
* a series for the OF/DT tree
* a series for the Tegra tree, which indicates it depends on all of those.

I'm wondering if the reason you haven't seen much discussion/Acks from
the maintainers of the non-Tegra trees is because this is a big scary
series that touches a lot of stuff, and it's not necessarily clear for
people unfamiliar with it why they're being CCd on it.


From stefano.stabellini at eu.citrix.com  Wed Aug  1 13:08:50 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 1 Aug 2012 18:08:50 +0100
Subject: [PATCH 14/24] xen/arm: initialize grant_table on ARM
In-Reply-To: <20120801144059.GL7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-14-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801144059.GL7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208011752020.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:56PM +0100, Stefano Stabellini wrote:
> > Initialize the grant table mapping at the address specified at index 0
> > in the DT under the /xen node.
> 
> Is it always index 0? If so, should it have a #define for the
> other index values?

There are no other values at the moment but I'll add an #define.


> > After the grant table is initialized, call xenbus_probe (if not dom0).
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/enlighten.c  |   13 +++++++++++++
> >  drivers/xen/grant-table.c |    2 +-
> >  2 files changed, 14 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index 2e013cf..854af1e 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -1,8 +1,12 @@
> >  #include <xen/xen.h>
> >  #include <xen/interface/xen.h>
> >  #include <xen/interface/memory.h>
> > +#include <xen/interface/hvm/params.h>
> >  #include <xen/platform_pci.h>
> >  #include <xen/features.h>
> > +#include <xen/grant_table.h>
> > +#include <xen/hvm.h>
> > +#include <xen/xenbus.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> >  #include <linux/module.h>
> > @@ -51,12 +55,16 @@ int __init xen_guest_init(void)
> >  	struct xen_add_to_physmap xatp;
> >  	static struct shared_info *shared_info_page = 0;
> >  	struct device_node *node;
> > +	struct resource res;
> >  
> >  	node = of_find_compatible_node(NULL, NULL, "arm,xen");
> >  	if (!node) {
> >  		pr_info("No Xen support\n");
> >  		return 0;
> >  	}
> > +	if (of_address_to_resource(node, 0, &res))
> > +		return -EINVAL;
> > +	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
> >  	xen_domain_type = XEN_HVM_DOMAIN;
> >  
> >  	xen_setup_features();
> > @@ -97,6 +105,11 @@ int __init xen_guest_init(void)
> >  		per_cpu(xen_vcpu, cpu) =
> >  			&HYPERVISOR_shared_info->vcpu_info[cpu];
> >  	}
> > +
> > +	gnttab_init();
> > +	if (!xen_initial_domain())
> > +		xenbus_probe(NULL);
> > +
> >  	return 0;
> >  }
> >  EXPORT_SYMBOL_GPL(xen_guest_init);
> > diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
> > index 1d0d95e..fd2137a 100644
> > --- a/drivers/xen/grant-table.c
> > +++ b/drivers/xen/grant-table.c
> > @@ -62,7 +62,7 @@
> >  
> >  static grant_ref_t **gnttab_list;
> >  static unsigned int nr_grant_frames;
> > -static unsigned int boot_max_nr_grant_frames;
> > +static unsigned int boot_max_nr_grant_frames = 1;
> 
> Is this going to impact x86 version?

It is not needed so I'll remove this change


From swarren at wwwdotorg.org  Wed Aug  1 13:20:13 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 01 Aug 2012 11:20:13 -0600
Subject: [PATCH v3 12/32] PCI/ARM: use PCIe capabilities access functions
 to simplify implementation
In-Reply-To: <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>
References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
 <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>
Message-ID: <5019654D.2000408@wwwdotorg.org>

On 08/01/2012 09:54 AM, Jiang Liu wrote:
> From: Jiang Liu <jiang.liu at huawei.com>
> 
> Use PCIe capabilities access functions to simplify PCIe ARM implementation.
> 
> Signed-off-by: Jiang Liu <liuj97 at gmail.com>

This is probably fine from my perspective assuming the underlying PCI
API implementation is OKd by relevant people.

Thierry, can you comment on whether this will conflict with your Tegra
PCIe driver series? If it doesn't, this patch can go through any
relevant PCI tree. If it does, we may have to take this through the
Tegra tree after merging the dependencies, or defer it to later.


From matt at genesi-usa.com  Wed Aug  1 13:49:29 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed,  1 Aug 2012 12:49:29 -0500
Subject: [PATCH 2/4] efikamx: remove Genesi Efika MX from the i.MX v6/v7
 defconfig
In-Reply-To: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
References: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1343843371-14143-3-git-send-email-matt@genesi-usa.com>

No need to have Efika MX listed in the defconfig if it can't be built.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
 arch/arm/configs/imx_v6_v7_defconfig |    2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b1d3675..0becdbe 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -31,8 +31,6 @@ CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_MX51_EFIKAMX=y
-CONFIG_MACH_MX51_EFIKASB=y
 CONFIG_MACH_IMX53_DT=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
-- 
1.7.9.5



From matt at genesi-usa.com  Wed Aug  1 13:49:28 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed,  1 Aug 2012 12:49:28 -0500
Subject: [PATCH 1/4] efikamx: remove support for Genesi Efika MX from the build
In-Reply-To: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
References: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1343843371-14143-2-git-send-email-matt@genesi-usa.com>

Disable building for Efika MX boards by not having any configuration or
object file definitions.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
 arch/arm/mach-imx/Kconfig  |   26 --------------------------
 arch/arm/mach-imx/Makefile |    3 ---
 2 files changed, 29 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eff4db5..a8051fe 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -728,32 +728,6 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-config MX51_EFIKA_COMMON
-	bool
-	select SOC_IMX51
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_MXC_EHCI
-	select IMX_HAVE_PLATFORM_PATA_IMX
-	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-	select IMX_HAVE_PLATFORM_SPI_IMX
-	select MXC_ULPI if USB_ULPI
-
-config MACH_MX51_EFIKAMX
-	bool "Support MX51 Genesi Efika MX nettop"
-	select LEDS_GPIO_REGISTER
-	select MX51_EFIKA_COMMON
-	help
-	  Include support for Genesi Efika MX nettop. This includes specific
-	  configurations for the board and its peripherals.
-
-config MACH_MX51_EFIKASB
-	bool "Support MX51 Genesi Efika Smartbook"
-	select LEDS_GPIO_REGISTER
-	select MX51_EFIKA_COMMON
-	help
-	  Include support for Genesi Efika Smartbook. This includes specific
-	  configurations for the board and its peripherals.
-
 comment "i.MX53 machines:"
 
 config MACH_IMX53_DT
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ff29421..ff6725d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -88,9 +88,6 @@ obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
 obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-- 
1.7.9.5



From matt at genesi-usa.com  Wed Aug  1 13:49:27 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed,  1 Aug 2012 12:49:27 -0500
Subject: [PATCH 0/4] Remove Genesi Efika MX support
Message-ID: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>

In an effort to start afresh we are removing the "legacy" Efika MX support
from the tree in this patch series so as to break ties with any non-device-tree
code and minimize the possibility that there are two ways to build for our
boards.

Patches to support the board again with FDT (along with a matching U-Boot)
are not ready for submission, but that doesn't block *this* submission. The
number of users of 3.5 kernels on Genesi platforms is generally thought of
as zero and no significant work or support has been committed to the platform
in a long time. In our opinion, all efforts by external developers wishing to
run modern kernels on Genesi Efika MX boards should be directed at device tree
support for the MX51 platforms.

Matt Sealey (4):
  efikamx: remove support for Genesi Efika MX from the build
  efikamx: remove Genesi Efika MX from the i.MX v6/v7 defconfig
  efikamx: remove Genesi Efika MX platform files from the tree
  efikamx: remove Efika MX-specific CHRGVBUS hack from the USB driver

 arch/arm/configs/imx_v6_v7_defconfig  |    2 -
 arch/arm/mach-imx/Kconfig             |   26 --
 arch/arm/mach-imx/Makefile            |    3 -
 arch/arm/mach-imx/efika.h             |   10 -
 arch/arm/mach-imx/mach-mx51_efikamx.c |  300 ----------------
 arch/arm/mach-imx/mach-mx51_efikasb.c |  296 ---------------
 arch/arm/mach-imx/mx51_efika.c        |  632 ---------------------------------
 drivers/usb/host/ehci-mxc.c           |   20 --
 8 files changed, 1289 deletions(-)
 delete mode 100644 arch/arm/mach-imx/efika.h
 delete mode 100644 arch/arm/mach-imx/mach-mx51_efikamx.c
 delete mode 100644 arch/arm/mach-imx/mach-mx51_efikasb.c
 delete mode 100644 arch/arm/mach-imx/mx51_efika.c

-- 
1.7.9.5



From matt at genesi-usa.com  Wed Aug  1 13:49:31 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed,  1 Aug 2012 12:49:31 -0500
Subject: [PATCH 4/4] efikamx: remove Efika MX-specific CHRGVBUS hack from the
 USB driver
In-Reply-To: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
References: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1343843371-14143-5-git-send-email-matt@genesi-usa.com>

Since we're removing Efika MX support from the tree (for now), remove
the hack present in the USB host driver since it will never run and
isn't useful on any other systems.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
 drivers/usb/host/ehci-mxc.c |   20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index c778ffe..062f871 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -118,7 +118,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	struct usb_hcd *hcd;
 	struct resource *res;
 	int irq, ret;
-	unsigned int flags;
 	struct ehci_mxc_priv *priv;
 	struct device *dev = &pdev->dev;
 	struct ehci_hcd *ehci;
@@ -235,25 +234,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_add;
 
-	if (pdata->otg) {
-		/*
-		 * efikamx and efikasb have some hardware bug which is
-		 * preventing usb to work unless CHRGVBUS is set.
-		 * It's in violation of USB specs
-		 */
-		if (machine_is_mx51_efikamx() || machine_is_mx51_efikasb()) {
-			flags = usb_phy_io_read(pdata->otg,
-							ULPI_OTG_CTRL);
-			flags |= ULPI_OTG_CTRL_CHRGVBUS;
-			ret = usb_phy_io_write(pdata->otg, flags,
-							ULPI_OTG_CTRL);
-			if (ret) {
-				dev_err(dev, "unable to set CHRVBUS\n");
-				goto err_add;
-			}
-		}
-	}
-
 	return 0;
 
 err_add:
-- 
1.7.9.5



From matt at genesi-usa.com  Wed Aug  1 13:49:30 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed,  1 Aug 2012 12:49:30 -0500
Subject: [PATCH 3/4] efikamx: remove Genesi Efika MX platform files from the
 tree
In-Reply-To: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
References: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1343843371-14143-4-git-send-email-matt@genesi-usa.com>

Delete the files that can no longer be built.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
 arch/arm/mach-imx/efika.h             |   10 -
 arch/arm/mach-imx/mach-mx51_efikamx.c |  300 ----------------
 arch/arm/mach-imx/mach-mx51_efikasb.c |  296 ---------------
 arch/arm/mach-imx/mx51_efika.c        |  632 ---------------------------------
 4 files changed, 1238 deletions(-)
 delete mode 100644 arch/arm/mach-imx/efika.h
 delete mode 100644 arch/arm/mach-imx/mach-mx51_efikamx.c
 delete mode 100644 arch/arm/mach-imx/mach-mx51_efikasb.c
 delete mode 100644 arch/arm/mach-imx/mx51_efika.c

diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa98..0000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _EFIKA_H
-#define _EFIKA_H
-
-#define EFIKA_WLAN_EN		IMX_GPIO_NR(2, 16)
-#define EFIKA_WLAN_RESET	IMX_GPIO_NR(2, 10)
-#define EFIKA_USB_PHY_RESET	IMX_GPIO_NR(2, 9)
-
-void __init efika_board_common_init(void);
-
-#endif
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c01..0000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKAMX_PCBID0		IMX_GPIO_NR(3, 16)
-#define EFIKAMX_PCBID1		IMX_GPIO_NR(3, 17)
-#define EFIKAMX_PCBID2		IMX_GPIO_NR(3, 11)
-
-#define EFIKAMX_BLUE_LED	IMX_GPIO_NR(3, 13)
-#define EFIKAMX_GREEN_LED	IMX_GPIO_NR(3, 14)
-#define EFIKAMX_RED_LED		IMX_GPIO_NR(3, 15)
-
-#define EFIKAMX_POWER_KEY	IMX_GPIO_NR(2, 31)
-
-/* board 1.1 doesn't have same reset gpio */
-#define EFIKAMX_RESET1_1	IMX_GPIO_NR(3, 2)
-#define EFIKAMX_RESET		IMX_GPIO_NR(1, 4)
-
-#define EFIKAMX_POWEROFF	IMX_GPIO_NR(4, 13)
-
-#define EFIKAMX_PMIC		IMX_GPIO_NR(1, 6)
-
-/* the pci ids pin have pull up. they're driven low according to board id */
-#define MX51_PAD_PCBID0	IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID1	IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID2	IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PWRKEY	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
-	/* board id */
-	MX51_PAD_PCBID0,
-	MX51_PAD_PCBID1,
-	MX51_PAD_PCBID2,
-
-	/* leds */
-	MX51_PAD_CSI1_D9__GPIO3_13,
-	MX51_PAD_CSI1_VSYNC__GPIO3_14,
-	MX51_PAD_CSI1_HSYNC__GPIO3_15,
-
-	/* power key */
-	MX51_PAD_PWRKEY,
-
-	/* reset */
-	MX51_PAD_DI1_PIN13__GPIO3_2,
-	MX51_PAD_GPIO1_4__GPIO1_4,
-
-	/* power off */
-	MX51_PAD_CSI2_VSYNC__GPIO4_13,
-};
-
-/*   PCBID2  PCBID1 PCBID0  STATE
-	1       1      1    ER1:rev1.1
-	1       1      0    ER2:rev1.2
-	1       0      1    ER3:rev1.3
-	1       0      0    ER4:rev1.4
-*/
-static void __init mx51_efikamx_board_id(void)
-{
-	int id;
-
-	/* things are taking time to settle */
-	msleep(150);
-
-	gpio_request(EFIKAMX_PCBID0, "pcbid0");
-	gpio_direction_input(EFIKAMX_PCBID0);
-	gpio_request(EFIKAMX_PCBID1, "pcbid1");
-	gpio_direction_input(EFIKAMX_PCBID1);
-	gpio_request(EFIKAMX_PCBID2, "pcbid2");
-	gpio_direction_input(EFIKAMX_PCBID2);
-
-	id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
-	id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
-	id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
-
-	switch (id) {
-	case 7:
-		system_rev = 0x11;
-		break;
-	case 6:
-		system_rev = 0x12;
-		break;
-	case 5:
-		system_rev = 0x13;
-		break;
-	case 4:
-		system_rev = 0x14;
-		break;
-	default:
-		system_rev = 0x10;
-		break;
-	}
-
-	if ((system_rev == 0x10)
-		|| (system_rev == 0x12)
-		|| (system_rev == 0x14)) {
-		printk(KERN_WARNING
-			"EfikaMX: Unsupported board revision 1.%u!\n",
-			system_rev & 0xf);
-	}
-}
-
-static struct gpio_led mx51_efikamx_leds[] __initdata = {
-	{
-		.name = "efikamx:green",
-		.default_trigger = "default-on",
-		.gpio = EFIKAMX_GREEN_LED,
-	},
-	{
-		.name = "efikamx:red",
-		.default_trigger = "ide-disk",
-		.gpio = EFIKAMX_RED_LED,
-	},
-	{
-		.name = "efikamx:blue",
-		.default_trigger = "mmc0",
-		.gpio = EFIKAMX_BLUE_LED,
-	},
-};
-
-static const struct gpio_led_platform_data
-		mx51_efikamx_leds_data __initconst = {
-	.leds = mx51_efikamx_leds,
-	.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
-};
-
-static struct esdhc_platform_data sd_pdata = {
-	.cd_type = ESDHC_CD_CONTROLLER,
-	.wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct gpio_keys_button mx51_efikamx_powerkey[] = {
-	{
-		.code = KEY_POWER,
-		.gpio = EFIKAMX_POWER_KEY,
-		.type = EV_PWR,
-		.desc = "Power Button (CM)",
-		.wakeup = 1,
-		.debounce_interval = 10, /* ms */
-	},
-};
-
-static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
-	.buttons = mx51_efikamx_powerkey,
-	.nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
-};
-
-static void mx51_efikamx_restart(char mode, const char *cmd)
-{
-	if (system_rev == 0x11)
-		gpio_direction_output(EFIKAMX_RESET1_1, 0);
-	else
-		gpio_direction_output(EFIKAMX_RESET, 0);
-}
-
-static struct regulator *pwgt1, *pwgt2, *coincell;
-
-static void mx51_efikamx_power_off(void)
-{
-	if (!IS_ERR(coincell))
-		regulator_disable(coincell);
-
-	if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-		regulator_disable(pwgt2);
-		regulator_disable(pwgt1);
-	}
-	gpio_direction_output(EFIKAMX_POWEROFF, 1);
-}
-
-static int __init mx51_efikamx_power_init(void)
-{
-	pwgt1 = regulator_get(NULL, "pwgt1");
-	pwgt2 = regulator_get(NULL, "pwgt2");
-	if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-		regulator_enable(pwgt1);
-		regulator_enable(pwgt2);
-	}
-	gpio_request(EFIKAMX_POWEROFF, "poweroff");
-	pm_power_off = mx51_efikamx_power_off;
-
-	/* enable coincell charger. maybe need a small power driver ? */
-	coincell = regulator_get(NULL, "coincell");
-	if (!IS_ERR(coincell)) {
-		regulator_set_voltage(coincell, 3000000, 3000000);
-		regulator_enable(coincell);
-	}
-
-	regulator_has_full_constraints();
-
-	return 0;
-}
-
-static void __init mx51_efikamx_init_late(void)
-{
-	imx51_init_late();
-	mx51_efikamx_power_init();
-}
-
-static void __init mx51_efikamx_init(void)
-{
-	imx51_soc_init();
-
-	mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
-					ARRAY_SIZE(mx51efikamx_pads));
-	efika_board_common_init();
-
-	mx51_efikamx_board_id();
-
-	/* on < 1.2 boards both SD controllers are used */
-	if (system_rev < 0x12) {
-		imx51_add_sdhci_esdhc_imx(0, NULL);
-		imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
-		mx51_efikamx_leds[2].default_trigger = "mmc1";
-	} else
-		imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
-
-	gpio_led_register_device(-1, &mx51_efikamx_leds_data);
-	imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
-
-	if (system_rev == 0x11) {
-		gpio_request(EFIKAMX_RESET1_1, "reset");
-		gpio_direction_output(EFIKAMX_RESET1_1, 1);
-	} else {
-		gpio_request(EFIKAMX_RESET, "reset");
-		gpio_direction_output(EFIKAMX_RESET, 1);
-	}
-
-	/*
-	 * enable wifi by default only on mx
-	 * sb and mx have same wlan pin but the value to enable it are
-	 * different :/
-	 */
-	gpio_request(EFIKA_WLAN_EN, "wlan_en");
-	gpio_direction_output(EFIKA_WLAN_EN, 0);
-	msleep(10);
-
-	gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
-	gpio_direction_output(EFIKA_WLAN_RESET, 0);
-	msleep(10);
-	gpio_set_value(EFIKA_WLAN_RESET, 1);
-}
-
-static void __init mx51_efikamx_timer_init(void)
-{
-	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikamx_timer = {
-	.init = mx51_efikamx_timer_init,
-};
-
-MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
-	.atag_offset = 0x100,
-	.map_io = mx51_map_io,
-	.init_early = imx51_init_early,
-	.init_irq = mx51_init_irq,
-	.handle_irq = imx51_handle_irq,
-	.timer = &mx51_efikamx_timer,
-	.init_machine = mx51_efikamx_init,
-	.init_late = mx51_efikamx_init_late,
-	.restart = mx51_efikamx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181..0000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (C) Arnaud Patard <arnaud.patard at rtp-net.org>
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKASB_USBH2_STP	IMX_GPIO_NR(2, 20)
-#define EFIKASB_GREEN_LED	IMX_GPIO_NR(1, 3)
-#define EFIKASB_WHITE_LED	IMX_GPIO_NR(2, 25)
-#define EFIKASB_PCBID0		IMX_GPIO_NR(2, 28)
-#define EFIKASB_PCBID1		IMX_GPIO_NR(2, 29)
-#define EFIKASB_PWRKEY		IMX_GPIO_NR(2, 31)
-#define EFIKASB_LID		IMX_GPIO_NR(3, 14)
-#define EFIKASB_POWEROFF	IMX_GPIO_NR(4, 13)
-#define EFIKASB_RFKILL		IMX_GPIO_NR(3, 1)
-
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-#define MX51_PAD_SD1_CD	IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
-	/* USB HOST2 */
-	MX51_PAD_EIM_D16__USBH2_DATA0,
-	MX51_PAD_EIM_D17__USBH2_DATA1,
-	MX51_PAD_EIM_D18__USBH2_DATA2,
-	MX51_PAD_EIM_D19__USBH2_DATA3,
-	MX51_PAD_EIM_D20__USBH2_DATA4,
-	MX51_PAD_EIM_D21__USBH2_DATA5,
-	MX51_PAD_EIM_D22__USBH2_DATA6,
-	MX51_PAD_EIM_D23__USBH2_DATA7,
-	MX51_PAD_EIM_A24__USBH2_CLK,
-	MX51_PAD_EIM_A25__USBH2_DIR,
-	MX51_PAD_EIM_A26__USBH2_STP,
-	MX51_PAD_EIM_A27__USBH2_NXT,
-
-	/* leds */
-	MX51_PAD_EIM_CS0__GPIO2_25,
-	MX51_PAD_GPIO1_3__GPIO1_3,
-
-	/* pcb id */
-	MX51_PAD_EIM_CS3__GPIO2_28,
-	MX51_PAD_EIM_CS4__GPIO2_29,
-
-	/* lid */
-	MX51_PAD_CSI1_VSYNC__GPIO3_14,
-
-	/* power key*/
-	MX51_PAD_PWRKEY,
-
-	/* wifi/bt button */
-	MX51_PAD_DI1_PIN12__GPIO3_1,
-
-	/* power off */
-	MX51_PAD_CSI2_VSYNC__GPIO4_13,
-
-	/* wdog reset */
-	MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
-
-	/* BT */
-	MX51_PAD_EIM_A17__GPIO2_11,
-
-	MX51_PAD_SD1_CD,
-};
-
-static int initialize_usbh2_port(struct platform_device *pdev)
-{
-	iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
-	iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
-
-	mxc_iomux_v3_setup_pad(usbh2gpio);
-	gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
-	gpio_direction_output(EFIKASB_USBH2_STP, 0);
-	msleep(1);
-	gpio_set_value(EFIKASB_USBH2_STP, 1);
-	msleep(1);
-
-	gpio_free(EFIKASB_USBH2_STP);
-	mxc_iomux_v3_setup_pad(usbh2stp);
-
-	mdelay(10);
-
-	return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh2_config __initdata = {
-	.init   = initialize_usbh2_port,
-	.portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void __init mx51_efikasb_usb(void)
-{
-	usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-			ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-	if (usbh2_config.otg)
-		imx51_add_mxc_ehci_hs(2, &usbh2_config);
-}
-
-static const struct gpio_led mx51_efikasb_leds[] __initconst = {
-	{
-		.name = "efikasb:green",
-		.default_trigger = "default-on",
-		.gpio = EFIKASB_GREEN_LED,
-		.active_low = 1,
-	},
-	{
-		.name = "efikasb:white",
-		.default_trigger = "caps",
-		.gpio = EFIKASB_WHITE_LED,
-	},
-};
-
-static const struct gpio_led_platform_data
-		mx51_efikasb_leds_data __initconst = {
-	.leds = mx51_efikasb_leds,
-	.num_leds = ARRAY_SIZE(mx51_efikasb_leds),
-};
-
-static struct gpio_keys_button mx51_efikasb_keys[] = {
-	{
-		.code = KEY_POWER,
-		.gpio = EFIKASB_PWRKEY,
-		.type = EV_KEY,
-		.desc = "Power Button",
-		.wakeup = 1,
-		.active_low = 1,
-	},
-	{
-		.code = SW_LID,
-		.gpio = EFIKASB_LID,
-		.type = EV_SW,
-		.desc = "Lid Switch",
-		.active_low = 1,
-	},
-	{
-		.code = KEY_RFKILL,
-		.gpio = EFIKASB_RFKILL,
-		.type = EV_KEY,
-		.desc = "rfkill",
-		.active_low = 1,
-	},
-};
-
-static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
-	.buttons = mx51_efikasb_keys,
-	.nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
-};
-
-static struct esdhc_platform_data sd0_pdata = {
-#define EFIKASB_SD1_CD	IMX_GPIO_NR(2, 27)
-	.cd_gpio = EFIKASB_SD1_CD,
-	.cd_type = ESDHC_CD_GPIO,
-	.wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
-	.cd_type = ESDHC_CD_CONTROLLER,
-	.wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct regulator *pwgt1, *pwgt2;
-
-static void mx51_efikasb_power_off(void)
-{
-	gpio_set_value(EFIKA_USB_PHY_RESET, 0);
-
-	if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-		regulator_disable(pwgt2);
-		regulator_disable(pwgt1);
-	}
-	gpio_direction_output(EFIKASB_POWEROFF, 1);
-}
-
-static int __init mx51_efikasb_power_init(void)
-{
-	pwgt1 = regulator_get(NULL, "pwgt1");
-	pwgt2 = regulator_get(NULL, "pwgt2");
-	if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-		regulator_enable(pwgt1);
-		regulator_enable(pwgt2);
-	}
-	gpio_request(EFIKASB_POWEROFF, "poweroff");
-	pm_power_off = mx51_efikasb_power_off;
-
-	regulator_has_full_constraints();
-
-	return 0;
-}
-
-static void __init mx51_efikasb_init_late(void)
-{
-	imx51_init_late();
-	mx51_efikasb_power_init();
-}
-
-/* 01     R1.3 board
-   10     R2.0 board */
-static void __init mx51_efikasb_board_id(void)
-{
-	int id;
-
-	gpio_request(EFIKASB_PCBID0, "pcb id0");
-	gpio_direction_input(EFIKASB_PCBID0);
-	gpio_request(EFIKASB_PCBID1, "pcb id1");
-	gpio_direction_input(EFIKASB_PCBID1);
-
-	id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
-	id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
-
-	switch (id) {
-	default:
-		break;
-	case 1:
-		system_rev = 0x13;
-		break;
-	case 2:
-		system_rev = 0x20;
-		break;
-	}
-}
-
-static void __init efikasb_board_init(void)
-{
-	imx51_soc_init();
-
-	mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
-					ARRAY_SIZE(mx51efikasb_pads));
-	efika_board_common_init();
-
-	mx51_efikasb_board_id();
-	mx51_efikasb_usb();
-	imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
-	imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
-
-	gpio_led_register_device(-1, &mx51_efikasb_leds_data);
-	imx_add_gpio_keys(&mx51_efikasb_keys_data);
-}
-
-static void __init mx51_efikasb_timer_init(void)
-{
-	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikasb_timer = {
-	.init	= mx51_efikasb_timer_init,
-};
-
-MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
-	.atag_offset = 0x100,
-	.map_io = mx51_map_io,
-	.init_early = imx51_init_early,
-	.init_irq = mx51_init_irq,
-	.handle_irq = imx51_handle_irq,
-	.init_machine =  efikasb_board_init,
-	.init_late = mx51_efikasb_init_late,
-	.timer = &mx51_efikasb_timer,
-	.restart	= mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ec6ca91..0000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-#include "cpu_op-mx51.h"
-
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
-
-#define EFIKAMX_USB_HUB_RESET	IMX_GPIO_NR(1, 5)
-#define EFIKAMX_USBH1_STP	IMX_GPIO_NR(1, 27)
-
-#define EFIKAMX_SPI_CS0		IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1		IMX_GPIO_NR(4, 25)
-
-#define EFIKAMX_PMIC		IMX_GPIO_NR(1, 6)
-
-static iomux_v3_cfg_t mx51efika_pads[] = {
-	/* UART1 */
-	MX51_PAD_UART1_RXD__UART1_RXD,
-	MX51_PAD_UART1_TXD__UART1_TXD,
-	MX51_PAD_UART1_RTS__UART1_RTS,
-	MX51_PAD_UART1_CTS__UART1_CTS,
-
-	/* SD 1 */
-	MX51_PAD_SD1_CMD__SD1_CMD,
-	MX51_PAD_SD1_CLK__SD1_CLK,
-	MX51_PAD_SD1_DATA0__SD1_DATA0,
-	MX51_PAD_SD1_DATA1__SD1_DATA1,
-	MX51_PAD_SD1_DATA2__SD1_DATA2,
-	MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-	/* SD 2 */
-	MX51_PAD_SD2_CMD__SD2_CMD,
-	MX51_PAD_SD2_CLK__SD2_CLK,
-	MX51_PAD_SD2_DATA0__SD2_DATA0,
-	MX51_PAD_SD2_DATA1__SD2_DATA1,
-	MX51_PAD_SD2_DATA2__SD2_DATA2,
-	MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-	/* SD/MMC WP/CD */
-	MX51_PAD_GPIO1_0__SD1_CD,
-	MX51_PAD_GPIO1_1__SD1_WP,
-	MX51_PAD_GPIO1_7__SD2_WP,
-	MX51_PAD_GPIO1_8__SD2_CD,
-
-	/* spi */
-	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-	MX51_PAD_CSPI1_SS0__GPIO4_24,
-	MX51_PAD_CSPI1_SS1__GPIO4_25,
-	MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-	MX51_PAD_GPIO1_6__GPIO1_6,
-
-	/* USB HOST1 */
-	MX51_PAD_USBH1_CLK__USBH1_CLK,
-	MX51_PAD_USBH1_DIR__USBH1_DIR,
-	MX51_PAD_USBH1_NXT__USBH1_NXT,
-	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-	/* USB HUB RESET */
-	MX51_PAD_GPIO1_5__GPIO1_5,
-
-	/* WLAN */
-	MX51_PAD_EIM_A22__GPIO2_16,
-	MX51_PAD_EIM_A16__GPIO2_10,
-
-	/* USB PHY RESET */
-	MX51_PAD_EIM_D27__GPIO2_9,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-	u32 v;
-	void __iomem *usb_base;
-	void __iomem *usbother_base;
-	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-	if (!usb_base)
-		return -ENOMEM;
-	usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-	/* Set the PHY clock to 19.2MHz */
-	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-	v |= MX51_USB_PLL_DIV_19_2_MHZ;
-	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-	iounmap(usb_base);
-
-	mdelay(10);
-
-	return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-	.init   = initialize_otg_port,
-	.portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-	iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-	iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-	u32 v;
-	void __iomem *usb_base;
-	void __iomem *socregs_base;
-
-	mxc_iomux_v3_setup_pad(usbh1gpio);
-	gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
-	gpio_direction_output(EFIKAMX_USBH1_STP, 0);
-	msleep(1);
-	gpio_set_value(EFIKAMX_USBH1_STP, 1);
-	msleep(1);
-
-	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-	socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-	/* The clock for the USBH1 ULPI port will come externally */
-	/* from the PHY. */
-	v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
-	__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-			socregs_base + MX51_USB_CTRL_1_OFFSET);
-
-	iounmap(usb_base);
-
-	gpio_free(EFIKAMX_USBH1_STP);
-	mxc_iomux_v3_setup_pad(usbh1stp);
-
-	mdelay(10);
-
-	return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh1_config __initdata = {
-	.init   = initialize_usbh1_port,
-	.portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void mx51_efika_hubreset(void)
-{
-	gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
-	gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
-	msleep(1);
-	gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
-	msleep(1);
-	gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
-}
-
-static void __init mx51_efika_usb(void)
-{
-	mx51_efika_hubreset();
-
-	/* pulling it low, means no USB at all... */
-	gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
-	gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
-	msleep(1);
-	gpio_set_value(EFIKA_USB_PHY_RESET, 1);
-
-	usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-			ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-
-	imx51_add_mxc_ehci_otg(&dr_utmi_config);
-	if (usbh1_config.otg)
-		imx51_add_mxc_ehci_hs(1, &usbh1_config);
-}
-
-static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
-	{
-	 .name = "u-boot",
-	 .offset = 0,
-	 .size = SZ_256K,
-	},
-	{
-	  .name = "config",
-	  .offset = MTDPART_OFS_APPEND,
-	  .size = SZ_64K,
-	},
-};
-
-static struct flash_platform_data mx51_efika_spi_flash_data = {
-	.name		= "spi_flash",
-	.parts		= mx51_efika_spi_nor_partitions,
-	.nr_parts	= ARRAY_SIZE(mx51_efika_spi_nor_partitions),
-	.type		= "sst25vf032b",
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
-	{
-		.supply = "cpu_vcc",
-	}
-};
-
-static struct regulator_consumer_supply vdig_consumers[] = {
-	/* sgtl5000 */
-	REGULATOR_SUPPLY("VDDA", "1-000a"),
-	REGULATOR_SUPPLY("VDDD", "1-000a"),
-};
-
-static struct regulator_consumer_supply vvideo_consumers[] = {
-	/* sgtl5000 */
-	REGULATOR_SUPPLY("VDDIO", "1-000a"),
-};
-
-static struct regulator_consumer_supply vsd_consumers[] = {
-	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
-	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
-};
-
-static struct regulator_consumer_supply pwgt1_consumer[] = {
-	{
-		.supply = "pwgt1",
-	}
-};
-
-static struct regulator_consumer_supply pwgt2_consumer[] = {
-	{
-		.supply = "pwgt2",
-	}
-};
-
-static struct regulator_consumer_supply coincell_consumer[] = {
-	{
-		.supply = "coincell",
-	}
-};
-
-static struct regulator_init_data sw1_init = {
-	.constraints = {
-		.name = "SW1",
-		.min_uV = 600000,
-		.max_uV = 1375000,
-		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.valid_modes_mask = 0,
-		.always_on = 1,
-		.boot_on = 1,
-		.state_mem = {
-			.uV = 850000,
-			.mode = REGULATOR_MODE_NORMAL,
-			.enabled = 1,
-		},
-	},
-	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-	.consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
-	.constraints = {
-		.name = "SW2",
-		.min_uV = 900000,
-		.max_uV = 1850000,
-		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.always_on = 1,
-		.boot_on = 1,
-		.state_mem = {
-			.uV = 950000,
-			.mode = REGULATOR_MODE_NORMAL,
-			.enabled = 1,
-		},
-	}
-};
-
-static struct regulator_init_data sw3_init = {
-	.constraints = {
-		.name = "SW3",
-		.min_uV = 1100000,
-		.max_uV = 1850000,
-		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.always_on = 1,
-		.boot_on = 1,
-	}
-};
-
-static struct regulator_init_data sw4_init = {
-	.constraints = {
-		.name = "SW4",
-		.min_uV = 1100000,
-		.max_uV = 1850000,
-		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.always_on = 1,
-		.boot_on = 1,
-	}
-};
-
-static struct regulator_init_data viohi_init = {
-	.constraints = {
-		.name = "VIOHI",
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data vusb_init = {
-	.constraints = {
-		.name = "VUSB",
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data swbst_init = {
-	.constraints = {
-		.name = "SWBST",
-	}
-};
-
-static struct regulator_init_data vdig_init = {
-	.constraints = {
-		.name = "VDIG",
-		.min_uV = 1050000,
-		.max_uV = 1800000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.always_on = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
-	.consumer_supplies = vdig_consumers,
-};
-
-static struct regulator_init_data vpll_init = {
-	.constraints = {
-		.name = "VPLL",
-		.min_uV = 1050000,
-		.max_uV = 1800000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data vusb2_init = {
-	.constraints = {
-		.name = "VUSB2",
-		.min_uV = 2400000,
-		.max_uV = 2775000,
-		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data vvideo_init = {
-	.constraints = {
-		.name = "VVIDEO",
-		.min_uV = 2775000,
-		.max_uV = 2775000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.apply_uV = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
-	.consumer_supplies = vvideo_consumers,
-};
-
-static struct regulator_init_data vaudio_init = {
-	.constraints = {
-		.name = "VAUDIO",
-		.min_uV = 2300000,
-		.max_uV = 3000000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-	}
-};
-
-static struct regulator_init_data vsd_init = {
-	.constraints = {
-		.name = "VSD",
-		.min_uV = 1800000,
-		.max_uV = 3150000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE,
-		.boot_on = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
-	.consumer_supplies = vsd_consumers,
-};
-
-static struct regulator_init_data vcam_init = {
-	.constraints = {
-		.name = "VCAM",
-		.min_uV = 2500000,
-		.max_uV = 3000000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE |
-			REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-		.boot_on = 1,
-	}
-};
-
-static struct regulator_init_data vgen1_init = {
-	.constraints = {
-		.name = "VGEN1",
-		.min_uV = 1200000,
-		.max_uV = 3150000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data vgen2_init = {
-	.constraints = {
-		.name = "VGEN2",
-		.min_uV = 1200000,
-		.max_uV = 3150000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data vgen3_init = {
-	.constraints = {
-		.name = "VGEN3",
-		.min_uV = 1800000,
-		.max_uV = 2900000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-		.boot_on = 1,
-		.always_on = 1,
-	}
-};
-
-static struct regulator_init_data gpo1_init = {
-	.constraints = {
-		.name = "GPO1",
-	}
-};
-
-static struct regulator_init_data gpo2_init = {
-	.constraints = {
-		.name = "GPO2",
-	}
-};
-
-static struct regulator_init_data gpo3_init = {
-	.constraints = {
-		.name = "GPO3",
-	}
-};
-
-static struct regulator_init_data gpo4_init = {
-	.constraints = {
-		.name = "GPO4",
-	}
-};
-
-static struct regulator_init_data pwgt1_init = {
-	.constraints = {
-		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-		.boot_on        = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
-	.consumer_supplies = pwgt1_consumer,
-};
-
-static struct regulator_init_data pwgt2_init = {
-	.constraints = {
-		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
-		.boot_on        = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
-	.consumer_supplies = pwgt2_consumer,
-};
-
-static struct regulator_init_data vcoincell_init = {
-	.constraints = {
-		.name = "COINCELL",
-		.min_uV = 3000000,
-		.max_uV = 3000000,
-		.valid_ops_mask =
-			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
-	.consumer_supplies = coincell_consumer,
-};
-
-static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
-	{ .id = MC13892_SW1,		.init_data =  &sw1_init },
-	{ .id = MC13892_SW2,		.init_data =  &sw2_init },
-	{ .id = MC13892_SW3,		.init_data =  &sw3_init },
-	{ .id = MC13892_SW4,		.init_data =  &sw4_init },
-	{ .id = MC13892_SWBST,		.init_data =  &swbst_init },
-	{ .id = MC13892_VIOHI,		.init_data =  &viohi_init },
-	{ .id = MC13892_VPLL,		.init_data =  &vpll_init },
-	{ .id = MC13892_VDIG,		.init_data =  &vdig_init },
-	{ .id = MC13892_VSD,		.init_data =  &vsd_init },
-	{ .id = MC13892_VUSB2,		.init_data =  &vusb2_init },
-	{ .id = MC13892_VVIDEO,		.init_data =  &vvideo_init },
-	{ .id = MC13892_VAUDIO,		.init_data =  &vaudio_init },
-	{ .id = MC13892_VCAM,		.init_data =  &vcam_init },
-	{ .id = MC13892_VGEN1,		.init_data =  &vgen1_init },
-	{ .id = MC13892_VGEN2,		.init_data =  &vgen2_init },
-	{ .id = MC13892_VGEN3,		.init_data =  &vgen3_init },
-	{ .id = MC13892_VUSB,		.init_data =  &vusb_init },
-	{ .id = MC13892_GPO1,		.init_data =  &gpo1_init },
-	{ .id = MC13892_GPO2,		.init_data =  &gpo2_init },
-	{ .id = MC13892_GPO3,		.init_data =  &gpo3_init },
-	{ .id = MC13892_GPO4,		.init_data =  &gpo4_init },
-	{ .id = MC13892_PWGT1SPI,	.init_data = &pwgt1_init },
-	{ .id = MC13892_PWGT2SPI,	.init_data = &pwgt2_init },
-	{ .id = MC13892_VCOINCELL,	.init_data = &vcoincell_init },
-};
-
-static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
-	.flags = MC13XXX_USE_RTC,
-	.regulators = {
-		.num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-		.regulators = mx51_efika_regulators,
-	},
-};
-
-static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
-	{
-		.modalias = "m25p80",
-		.max_speed_hz = 25000000,
-		.bus_num = 0,
-		.chip_select = 1,
-		.platform_data = &mx51_efika_spi_flash_data,
-		.irq = -1,
-	},
-	{
-		.modalias = "mc13892",
-		.max_speed_hz = 1000000,
-		.bus_num = 0,
-		.chip_select = 0,
-		.platform_data = &mx51_efika_mc13892_data,
-		.irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
-	},
-};
-
-static int mx51_efika_spi_cs[] = {
-	EFIKAMX_SPI_CS0,
-	EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
-	.chipselect     = mx51_efika_spi_cs,
-	.num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
-};
-
-void __init efika_board_common_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
-					ARRAY_SIZE(mx51efika_pads));
-	imx51_add_imx_uart(0, &uart_pdata);
-	mx51_efika_usb();
-
-	/* FIXME: comes from original code. check this. */
-	if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-		sw2_init.constraints.state_mem.uV = 1100000;
-	else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
-		sw2_init.constraints.state_mem.uV = 1250000;
-		sw1_init.constraints.state_mem.uV = 1000000;
-	}
-	if (machine_is_mx51_efikasb())
-		vgen1_init.constraints.max_uV = 1200000;
-
-	gpio_request(EFIKAMX_PMIC, "pmic irq");
-	gpio_direction_input(EFIKAMX_PMIC);
-	spi_register_board_info(mx51_efika_spi_board_info,
-		ARRAY_SIZE(mx51_efika_spi_board_info));
-	imx51_add_ecspi(0, &mx51_efika_spi_pdata);
-
-	imx51_add_pata_imx();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-	get_cpu_op = mx51_get_cpu_op;
-#endif
-}
-- 
1.7.9.5



From jon-hunter at ti.com  Wed Aug  1 14:17:55 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 1 Aug 2012 13:17:55 -0500
Subject: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain
 transitioning to OFF when in-use
In-Reply-To: <alpine.DEB.2.00.1208010906470.21488@utopia.booyaka.com>
References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com>
 <1339104132-26885-9-git-send-email-jon-hunter@ti.com>
 <alpine.DEB.2.00.1207111441300.25585@utopia.booyaka.com>
 <500028B3.1040309@ti.com>
 <alpine.DEB.2.00.1207131418500.25585@utopia.booyaka.com>
 <50045D17.9050704@ti.com>
 <alpine.DEB.2.00.1207161228470.28834@utopia.booyaka.com>
 <50171841.40309@ti.com> <501760BF.8070801@ti.com> <5018210A.1040902@ti.com>
 <50187644.40308@ti.com>
 <alpine.DEB.2.00.1208010906470.21488@utopia.booyaka.com>
Message-ID: <501972D3.7070606@ti.com>

Hi Paul,

On 08/01/2012 10:08 AM, Paul Walmsley wrote:
> Hi Jon,
> 
> On Tue, 31 Jul 2012, Jon Hunter wrote:
> 
>> Sorry for all the emails. However, I wanted to get this out to you as
>> I am due to be out for a couple weeks. 
>>
>> So I have updated your patch [1] with the following changes ...
>>
>> 1. Re-based on top of your omap3 clock domain fix [2]
>> 2. Modified the above change I mentioned to check for
>>    CLKDM_MISSING_IDLE_REPORTING in omap_pm_clkdms_setup() instead of
>>    the omap2_clkdm_clk_enable(). This is to prevent the clock domain
>>    being placed in HW_AUTO on boot if enabled early.
>> 3. Made the other change I mentioned earlier [3].
>>
>> This is now working well for me on OMAP3/4.
> 
> Your changes look good to me.  Do you have a strong preference as to 
> whether that patch should go in as part of 3.6-rc or 3.7?  I'd be inclined 
> to queue it for 3.7 based on the size of the patch.

Thanks for the feedback. 3.7 is fine with me, I don't expect the PMU
changes I have will be in before that.

Cheers
Jon


From mukesh.rathor at oracle.com  Wed Aug  1 14:19:37 2012
From: mukesh.rathor at oracle.com (Mukesh Rathor)
Date: Wed, 1 Aug 2012 11:19:37 -0700
Subject: [PATCH 20/24] xen: update xen_add_to_physmap interface
In-Reply-To: <20120801145215.GP7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-20-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801145215.GP7227@phenom.dumpdata.com>
Message-ID: <20120801111937.4c9b3702@mantra.us.oracle.com>

On Wed, 1 Aug 2012 10:52:15 -0400
Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> wrote:

> On Thu, Jul 26, 2012 at 04:34:02PM +0100, Stefano Stabellini wrote:
> > Update struct xen_add_to_physmap to be in sync with Xen's version
> > of the structure.
> > The size field was introduced by:
> > 
> > changeset:   24164:707d27fe03e7
> > user:        Jean Guyader <jean.guyader at eu.citrix.com>
> > date:        Fri Nov 18 13:42:08 2011 +0000
> > summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range
> > 
> > According to the comment:
> > 
> > "This new field .size is located in the 16 bits padding
> > between .domid and .space in struct xen_add_to_physmap to stay
> > compatible with older versions."
> > 
> > This is not true on ARM where there is not padding, but it is valid
> > on X86, so introducing size is safe on X86 and it is going to fix
> > the interace for ARM.
> 
> Has this been checked actually for backwards compatibility? It sounds
> like it should work just fine with Xen 4.0 right?
> 
> I believe this also helps Mukesh's patches, so CC-ing him here for
> his Ack.

Yup, I already had that change in my tree.

thanks,
Mukesh




From robherring2 at gmail.com  Wed Aug  1 14:27:51 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 01 Aug 2012 13:27:51 -0500
Subject: [PATCH 01/24] arm: initial Xen support
In-Reply-To: <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <50197527.3070007@gmail.com>

On 07/26/2012 10:33 AM, Stefano Stabellini wrote:
> - Basic hypervisor.h and interface.h definitions.
> - Skelethon enlighten.c, set xen_start_info to an empty struct.
> - Do not limit xen_initial_domain to PV guests.
> 
> The new code only compiles when CONFIG_XEN is set, that is going to be
> added to arch/arm/Kconfig in a later patch.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/Makefile                     |    1 +
>  arch/arm/include/asm/hypervisor.h     |    6 +++
>  arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
>  arch/arm/include/asm/xen/interface.h  |   64 +++++++++++++++++++++++++++++++++

These headers don't seem particularly ARM specific. Could they be moved
to asm-generic or include/linux?

Rob

>  arch/arm/xen/Makefile                 |    1 +
>  arch/arm/xen/enlighten.c              |   35 ++++++++++++++++++
>  include/xen/xen.h                     |    2 +-
>  7 files changed, 127 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/include/asm/hypervisor.h
>  create mode 100644 arch/arm/include/asm/xen/hypervisor.h
>  create mode 100644 arch/arm/include/asm/xen/interface.h
>  create mode 100644 arch/arm/xen/Makefile
>  create mode 100644 arch/arm/xen/enlighten.c
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 0298b00..70aaa82 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -246,6 +246,7 @@ endif
>  core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
>  core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)
>  core-$(CONFIG_VFP)		+= arch/arm/vfp/
> +core-$(CONFIG_XEN)		+= arch/arm/xen/
>  
>  # If we have a machine-specific directory, then include it in the build.
>  core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
> diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
> new file mode 100644
> index 0000000..b90d9e5
> --- /dev/null
> +++ b/arch/arm/include/asm/hypervisor.h
> @@ -0,0 +1,6 @@
> +#ifndef _ASM_ARM_HYPERVISOR_H
> +#define _ASM_ARM_HYPERVISOR_H
> +
> +#include <asm/xen/hypervisor.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
> new file mode 100644
> index 0000000..d7ab99a
> --- /dev/null
> +++ b/arch/arm/include/asm/xen/hypervisor.h
> @@ -0,0 +1,19 @@
> +#ifndef _ASM_ARM_XEN_HYPERVISOR_H
> +#define _ASM_ARM_XEN_HYPERVISOR_H
> +
> +extern struct shared_info *HYPERVISOR_shared_info;
> +extern struct start_info *xen_start_info;
> +
> +/* Lazy mode for batching updates / context switch */
> +enum paravirt_lazy_mode {
> +	PARAVIRT_LAZY_NONE,
> +	PARAVIRT_LAZY_MMU,
> +	PARAVIRT_LAZY_CPU,
> +};
> +
> +static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
> +{
> +	return PARAVIRT_LAZY_NONE;
> +}
> +
> +#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
> diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
> new file mode 100644
> index 0000000..6c3ab59
> --- /dev/null
> +++ b/arch/arm/include/asm/xen/interface.h
> @@ -0,0 +1,64 @@
> +/******************************************************************************
> + * Guest OS interface to ARM Xen.
> + *
> + * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2011
> + */
> +
> +#ifndef _ASM_ARM_XEN_INTERFACE_H
> +#define _ASM_ARM_XEN_INTERFACE_H
> +
> +#include <linux/types.h>
> +
> +#define __DEFINE_GUEST_HANDLE(name, type) \
> +	typedef type * __guest_handle_ ## name
> +
> +#define DEFINE_GUEST_HANDLE_STRUCT(name) \
> +	__DEFINE_GUEST_HANDLE(name, struct name)
> +#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
> +#define GUEST_HANDLE(name)        __guest_handle_ ## name
> +
> +#define set_xen_guest_handle(hnd, val)			\
> +	do {						\
> +		if (sizeof(hnd) == 8)			\
> +			*(uint64_t *)&(hnd) = 0;	\
> +		(hnd) = val;				\
> +	} while (0)
> +
> +#ifndef __ASSEMBLY__
> +/* Guest handles for primitive C types. */
> +__DEFINE_GUEST_HANDLE(uchar, unsigned char);
> +__DEFINE_GUEST_HANDLE(uint,  unsigned int);
> +__DEFINE_GUEST_HANDLE(ulong, unsigned long);
> +DEFINE_GUEST_HANDLE(char);
> +DEFINE_GUEST_HANDLE(int);
> +DEFINE_GUEST_HANDLE(long);
> +DEFINE_GUEST_HANDLE(void);
> +DEFINE_GUEST_HANDLE(uint64_t);
> +DEFINE_GUEST_HANDLE(uint32_t);
> +
> +/* Maximum number of virtual CPUs in multi-processor guests. */
> +#define MAX_VIRT_CPUS 1
> +
> +struct arch_vcpu_info { };
> +struct arch_shared_info { };
> +
> +/* XXX: Move pvclock definitions some place arch independent */
> +struct pvclock_vcpu_time_info {
> +	u32   version;
> +	u32   pad0;
> +	u64   tsc_timestamp;
> +	u64   system_time;
> +	u32   tsc_to_system_mul;
> +	s8    tsc_shift;
> +	u8    flags;
> +	u8    pad[2];
> +} __attribute__((__packed__)); /* 32 bytes */
> +
> +struct pvclock_wall_clock {
> +	u32   version;
> +	u32   sec;
> +	u32   nsec;
> +} __attribute__((__packed__));
> +#endif
> +
> +#endif /* _ASM_ARM_XEN_INTERFACE_H */
> diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> new file mode 100644
> index 0000000..0bad594
> --- /dev/null
> +++ b/arch/arm/xen/Makefile
> @@ -0,0 +1 @@
> +obj-y		:= enlighten.o
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> new file mode 100644
> index 0000000..d27c2a6
> --- /dev/null
> +++ b/arch/arm/xen/enlighten.c
> @@ -0,0 +1,35 @@
> +#include <xen/xen.h>
> +#include <xen/interface/xen.h>
> +#include <xen/interface/memory.h>
> +#include <xen/platform_pci.h>
> +#include <asm/xen/hypervisor.h>
> +#include <asm/xen/hypercall.h>
> +#include <linux/module.h>
> +
> +struct start_info _xen_start_info;
> +struct start_info *xen_start_info = &_xen_start_info;
> +EXPORT_SYMBOL_GPL(xen_start_info);
> +
> +enum xen_domain_type xen_domain_type = XEN_NATIVE;
> +EXPORT_SYMBOL_GPL(xen_domain_type);
> +
> +struct shared_info xen_dummy_shared_info;
> +struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
> +
> +DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
> +
> +/* XXX: to be removed */
> +__read_mostly int xen_have_vector_callback;
> +EXPORT_SYMBOL_GPL(xen_have_vector_callback);
> +
> +int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
> +EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
> +
> +int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
> +			       unsigned long addr,
> +			       unsigned long mfn, int nr,
> +			       pgprot_t prot, unsigned domid)
> +{
> +	return -ENOSYS;
> +}
> +EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> diff --git a/include/xen/xen.h b/include/xen/xen.h
> index a164024..2c0d3a5 100644
> --- a/include/xen/xen.h
> +++ b/include/xen/xen.h
> @@ -23,7 +23,7 @@ extern enum xen_domain_type xen_domain_type;
>  #include <xen/interface/xen.h>
>  #include <asm/xen/hypervisor.h>
>  
> -#define xen_initial_domain()	(xen_pv_domain() && \
> +#define xen_initial_domain()	(xen_domain() && \
>  				 xen_start_info->flags & SIF_INITDOMAIN)
>  #else  /* !CONFIG_XEN_DOM0 */
>  #define xen_initial_domain()	(0)
> 



From jon-hunter at ti.com  Wed Aug  1 15:41:34 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 1 Aug 2012 14:41:34 -0500
Subject: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain
 transitioning to OFF when in-use
In-Reply-To: <alpine.DEB.2.00.1208010932270.21488@utopia.booyaka.com>
References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com>
 <1339104132-26885-9-git-send-email-jon-hunter@ti.com>
 <alpine.DEB.2.00.1207111441300.25585@utopia.booyaka.com>
 <500028B3.1040309@ti.com>
 <alpine.DEB.2.00.1207131418500.25585@utopia.booyaka.com>
 <50045D17.9050704@ti.com>
 <alpine.DEB.2.00.1207161228470.28834@utopia.booyaka.com>
 <50171841.40309@ti.com> <501760BF.8070801@ti.com> <5018210A.1040902@ti.com>
 <50187644.40308@ti.com>
 <alpine.DEB.2.00.1208010932270.21488@utopia.booyaka.com>
Message-ID: <5019866E.3000100@ti.com>

Hi Paul,

On 08/01/2012 10:36 AM, Paul Walmsley wrote:
> Hi Jon et al,
> 
> Here's what I'm planning to queue here.  The only changes from what Jon
> posted are the patch changelog and some checkpatch fixes.  If anyone
> has any final comments, please let me know.
> 
> 
> - Paul
> 
> From: Paul Walmsley <paul at pwsan.com>
> Date: Wed, 1 Aug 2012 09:11:20 -0600
> Subject: [PATCH] ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU
>  clockdomain idle problems
> 
> The idle status of the IP blocks and clocks inside the EMU clockdomain
> isn't taken into account by the PRCM hardware when deciding whether
> the clockdomain is idle.  Add a workaround flag in the clockdomain
> code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
> the code necessary to support it.
> 
> If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
> clockdomain will be forced active whenever an IP block inside that
> clockdomain is in use, even if the clockdomain supports
> hardware-supervised idle.  When the kernel indicates that the last
> active IP block inside the clockdomain is no longer used, the
> clockdomain will be forced idle, or, if that mode is not supported in
> the hardware, it will be placed into hardware-supervised idle.
> 
> This patch is an equal collaboration with Jon Hunter
> <jon-hunter at ti.com>.  Ming Lei <ming.lei at canonical.com>, Will Deacon
> <will.deacon at arm.com>, Madhav Vij <mvij at ti.com>, Kevin Hilman
> <khilman at ti.com>, Beno?t Cousson <b-cousson at ti.com>, and Santosh
> Shilimkar <santosh.shilimkar at ti.com> all made essential contributions
> to the understanding of EMU clockdomain power management on OMAP.
> 
> Signed-off-by: Paul Walmsley <paul at pwsan.com>

Thanks for sending out. You can add my ...

Tested-by: Jon Hunter <jon-hunter at ti.com>

I have tested this on omap3430 (beagle), omap4430 (blaze) and omap4460
(panda) with perf and my PMU series [1]. I have verified that the EMU
power domain is transitioning correctly on these platforms. For OMAP3430
I checked that CORE retention is still being achieved with this change.

Cheers
Jon

[1] git at gitorious.org:linux-omap-dev/linux-omap-dev.git -b dev-pmu


From broonie at opensource.wolfsonmicro.com  Wed Aug  1 15:41:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 20:41:34 +0100
Subject: [alsa-devel] [PATCH 1/6] ASoC: dapm: If one widget fails, do
 not force all subsequent widgets to fail too
In-Reply-To: <20120801160824.GB11892@opensource.wolfsonmicro.com>
References: <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
 <20120801160824.GB11892@opensource.wolfsonmicro.com>
Message-ID: <20120801194134.GA4103@sirena.org.uk>

On Wed, Aug 01, 2012 at 05:08:24PM +0100, Mark Brown wrote:
> On Wed, Aug 01, 2012 at 02:50:32PM +0100, Lee Jones wrote:

> > >It's very disappointing to see such an error exist, and even more
> > >disappointing that there's no interest in fixing the driver.

> > This is incorrect. I'm sure the driver will be fixed post-haste when
> > Ola returns back from vacation. If I can find some time I might
> > dabble in the mean-time also.

> It may not be what you're intending but it's unfortuantely what's I'm
> seeing.

Just to expand on this a bit since I've found myself pushing back in
this sort of way far too often with these recent serieses and it's
making everyone grumpy:

What I'm seeing here is a lot of patches getting sent with problems that
I'd really not expect from someone sending such a high volume of
patches.  Things like the lack of documentation for the DT bindings for
example, it's something that's mandatory and which people doing lots of
device tree work really ought to be aware of.  There's also noticable
pushback with fixing some of these issues, and like I say this happens
often enough to be really noticeable.

This isn't awesome from a review point of view, it's not nice to find
issues in things and when it happens a lot for the wrong sort of thing
it ends up seeming like the time spent doing the reviews isn't valued.


From festevam at gmail.com  Wed Aug  1 16:17:57 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 1 Aug 2012 17:17:57 -0300
Subject: [RFC] ARM: imx6q-sabrelite: Add CLKO IOMUX
In-Reply-To: <1343833836-14287-1-git-send-email-festevam@gmail.com>
References: <1343833836-14287-1-git-send-email-festevam@gmail.com>
Message-ID: <CAOMZO5A2g+UCFuiP7yqYkFQ36F=2yrqJA3ssujeYXE_Q0Sz5nQ@mail.gmail.com>

On Wed, Aug 1, 2012 at 12:10 PM, Fabio Estevam <festevam at gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
>
> In order to have audio functional on mx6qsabrelite, it is necessary to setup
> the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO and MX6Q_PAD_GPIO_3__CCM_CLKO2 pins.
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> Dirk,
>
> Not tested. If you have a chance to try it, please let me know.

I managed to get a board and tried it with current Linus' tree and
also linux-next. Both result in:

sgtl5000 0-000a: Device with ID register ffff is not a sgtl5000
sgtl5000 0-000a: asoc: failed to probe CODEC sgtl5000.0-000a: -19
asoc: failed to instantiate card imx6q-sabrelite-sgtl5000: -19
imx-sgtl5000 sound.11: snd_soc_register_card failed (-19)

Any ideas?

Thanks,

Fabio Estevam


From broonie at opensource.wolfsonmicro.com  Wed Aug  1 16:31:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 21:31:07 +0100
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <1343076052-27312-7-git-send-email-marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
Message-ID: <20120801203106.GW4483@opensource.wolfsonmicro.com>

On Mon, Jul 23, 2012 at 10:40:48PM +0200, Marek Vasut wrote:

> This is slightly reworked version of the SPI driver.
> Support for DT has been added and it's been converted
> to queued API.

Looks reasonable overall.

> +	bits_per_word = dev->bits_per_word;
> +	if (t && t->bits_per_word)
> +		bits_per_word = t->bits_per_word;
> +
> +	if (bits_per_word != 8) {
> +		dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
> +					__func__, bits_per_word);
> +		return -EINVAL;
> +	}

> +	if (dev->max_speed_hz)
> +		hz = dev->max_speed_hz;
> +	if (t && t->speed_hz)
> +		hz = t->speed_hz;
> +	if (hz == 0) {
> +		dev_err(&dev->dev, "Cannot continue with zero clock\n");
> +		return -EINVAL;
> +	}

These two blocks use a different style (the first does the first assign
unconditionally, the second uses initialisation with declaration).  I
prefer the first style but YMMV and it doesn't matter.

For the missing clock rate might it make sense to just use whatever the
clock happens to come out as?

> +static void mxs_spi_cleanup(struct spi_device *dev)
> +{
> +	return;
> +}

Empty functions are generally a warning sign...  why do we need this
one?

> +static int __devexit mxs_spi_remove(struct platform_device *pdev)
> +{

> +	clk_disable_unprepare(ssp->clk);

It'd be nice to only keep the clocks enabled while doing transfers but
again totally non-essential.


From broonie at opensource.wolfsonmicro.com  Wed Aug  1 16:34:48 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 1 Aug 2012 21:34:48 +0100
Subject: [PATCH 08/10 RESEND] spi: Add DMA support into SPI driver
In-Reply-To: <1343076052-27312-9-git-send-email-marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-9-git-send-email-marex@denx.de>
Message-ID: <20120801203448.GX4483@opensource.wolfsonmicro.com>

On Mon, Jul 23, 2012 at 10:40:50PM +0200, Marek Vasut wrote:

> +		/*
> +		 * Small blocks can be transfered via PIO.
> +		 * Measured by empiric means:
> +		 *
> +		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
> +		 *
> +		 * DMA only: 2.164808 seconds, 473.0KB/s
> +		 * Combined: 1.676276 seconds, 610.9KB/s
> +		 */

I've seen other devices end up using the FIFO length as the decision
point here which makes intuitive sense to me unless the FIFO is
extremely deep.

Not reviewed this properly yet but it looks OK from a first read
through.


From troy.kisky at boundarydevices.com  Wed Aug  1 16:35:17 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Wed, 01 Aug 2012 13:35:17 -0700
Subject: [RFC] ARM: imx6q-sabrelite: Add CLKO IOMUX
In-Reply-To: <CAOMZO5A2g+UCFuiP7yqYkFQ36F=2yrqJA3ssujeYXE_Q0Sz5nQ@mail.gmail.com>
References: <1343833836-14287-1-git-send-email-festevam@gmail.com>
 <CAOMZO5A2g+UCFuiP7yqYkFQ36F=2yrqJA3ssujeYXE_Q0Sz5nQ@mail.gmail.com>
Message-ID: <50199305.60802@boundarydevices.com>

On 8/1/2012 1:17 PM, Fabio Estevam wrote:
> On Wed, Aug 1, 2012 at 12:10 PM, Fabio Estevam <festevam at gmail.com> wrote:
>> From: Fabio Estevam <fabio.estevam at freescale.com>
>>
>> In order to have audio functional on mx6qsabrelite, it is necessary to setup
>> the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO and MX6Q_PAD_GPIO_3__CCM_CLKO2 pins.
>>
>> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>> ---
>> Dirk,
>>
>> Not tested. If you have a chance to try it, please let me know.
> I managed to get a board and tried it with current Linus' tree and
> also linux-next. Both result in:
>
> sgtl5000 0-000a: Device with ID register ffff is not a sgtl5000
> sgtl5000 0-000a: asoc: failed to probe CODEC sgtl5000.0-000a: -19
> asoc: failed to instantiate card imx6q-sabrelite-sgtl5000: -19
> imx-sgtl5000 sound.11: snd_soc_register_card failed (-19)
>
> Any ideas?
>
> Thanks,
>
> Fabio Estevam
>
No idea, but a comment.

GPIO_0 is needed for SGTL500 - sys_mclk
GPIO_3 is needed for Camera mclk, no audio dependency.

Troy



From jon-hunter at ti.com  Wed Aug  1 16:43:02 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 1 Aug 2012 15:43:02 -0500
Subject: [PATCH V3 1/2] of: Add generic device tree DMA helpers
In-Reply-To: <1343733132.1726.14418.camel@vkoul-udesk3>
References: <1335820679-28721-1-git-send-email-jon-hunter@ti.com>
 <201207171924.33756.arnd@arndb.de> <1342756850.1726.74.camel@vkoul-udesk3>
 <201207200839.24259.arnd@arndb.de> <1342777047.1726.435.camel@vkoul-udesk3>
 <500EF27F.6050905@ti.com> <1343284960.1726.8978.camel@vkoul-udesk3>
 <501181C3.1020301@ti.com> <1343733132.1726.14418.camel@vkoul-udesk3>
Message-ID: <501994D6.6070508@ti.com>

Hi Vinod,

On 07/31/2012 06:12 AM, Vinod Koul wrote:
> On Thu, 2012-07-26 at 12:43 -0500, Jon Hunter wrote:
>>>> So yes I can see that a channel itself could be configured to
>> support a
>>>> given direction, but when we ask for a channel via
>> dma_request_channel()
>>>> we are going to get a channel that matches the criteria we pass
>> using
>>>> the filter parameter. So here the thinking was that "flags" is a
>> filter
>>>> parameter that the user could specify and one example being
>> direction
>>>> but it could be something else too.
>>> Yes that can be done, but I am leaning towards clients not have to
>> do
>>> anything :) DMAEngine needs to know mapping and when
>>> dma_request_channel() is called it _always_ gives you the right
>> channel.
>>
>> Ok, so are you proposing to remove the filter function and parameter
>> from the dma_request_channel()?
> No. But add a new request call, dma_request_slave_channel() which is
> exclusive for slave usages and takes into account the mapping to be done
> for channels
>>
>>> Maybe for slave case we need to create dma_request_slave_channel()
>> which
>>> has additional arguments for dmaengine to do the filtering.
> Yup
>>
>> Ok, so what is not clear to me is if you envision that
>> dma_request_slave_channel() is using a mapping table based look-up or
>> the DT scheme or both.
> The API should not worry about it. It would be good to have DT/ other be
> behind this API, so it is transparent to users. They just request a
> slave channel.

So would you envision something like (copying from Guennadi's API but
changing direction to flags) ...

struct dma_chan *dma_request_slave_channel(struct device *dev,
					char *name, unsigned int flags)
{
	/* If device-tree is present get slave info from here */
	if (dev->of_node)
		return of_dma_request_slave_channel(dev, name, flags);

	return NULL;
}

Ok, so right now the above is nothing more than a simple wrapper around
a DT dma function to extract the slave info. However, it would allow us
to add another means for getting the slave info in the future if
necessary by adding an else part to the above.

Cheers
Jon


From will.deacon at arm.com  Wed Aug  1 16:47:31 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 1 Aug 2012 21:47:31 +0100
Subject: [PATCH V2 01/10] ARM: PMU: Add runtime PM Support
In-Reply-To: <50186524.6060903@ti.com>
References: <4FD7C597.7060501@ti.com>
 <20120702095539.GD22239@mudshark.cambridge.arm.com>
 <4FF1D15E.7040301@ti.com>
 <20120702220117.GD25234@mudshark.cambridge.arm.com>
 <4FF6340A.6020409@ti.com> <50109233.3090302@ti.com>
 <20120726150534.GD6382@mudshark.cambridge.arm.com>
 <50115F3F.7050705@ti.com>
 <20120731151446.GK3903@mudshark.cambridge.arm.com>
 <50186524.6060903@ti.com>
Message-ID: <20120801204731.GA9080@mudshark.cambridge.arm.com>

On Wed, Aug 01, 2012 at 12:07:16AM +0100, Jon Hunter wrote:
> I have just updated my pmu branch for omap3/4. You can pull my latest
> patches from [1].

Great, thanks for that. I've pushed out to perf/omap4 and I've also
included your runtime PM hooks in my perf/updates branch. I have a fair
amount of cleanup sitting in there as well, so I'll post that to the list
at -rc1 as a candidate for -next. I'll obviously leave the omap-specific
bits for others to handle, although I'll continue maintaining my branch
until that's hit mainline.

> In the latest series I have:
> 1. Pulled in an omap3 clock domain fix from Paul [2]
> 2. Rebased Paul's patch [3] on top of [2]. I have also made a couple
>    updates to this patch and I need to get Paul's feedback.
> 3. I have removed the OMAP3 PMU dependency on ETM from the Kconfig.

Fantastic! I actually already removed the OMAP3 Kconfig dependency in my
perf/updates branch as part of removing CPU_HAS_PMU entirely, so you
probably don't need to pursue that patch.

> I will probably send out the series once I align with Paul on the above
> changes and the HWMOD stuff I have added for OMAP3 with Benoit.

Okey doke. If you need me to update my copy of your runtime PM patch,
please shout (that seems to be a done deal afaict).

Will


From anton.vorontsov at linaro.org  Wed Aug  1 16:52:18 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Wed, 1 Aug 2012 13:52:18 -0700
Subject: [PATCH 07/11] ARM: Add KGDB/KDB FIQ debugger generic code
In-Reply-To: <20120730140724.GI6802@n2100.arm.linux.org.uk>
References: <20120730115719.GA5742@lizard>
 <1343649500-18491-7-git-send-email-anton.vorontsov@linaro.org>
 <20120730140724.GI6802@n2100.arm.linux.org.uk>
Message-ID: <20120801205218.GA20714@lizard>

On Mon, Jul 30, 2012 at 03:07:24PM +0100, Russell King - ARM Linux wrote:
[....]
> Now the thing here is that even if we did preserve SPSR_svc, with the
> above exit sequence, there is _no_ way to preserve the value of SPSR_svc.
> Normally, this doesn't matter because we know that the regions we care
> about this have IRQs disabled.

Wow, that is quite subtle. Indeed, now I clearly see that we do mangle
SVC's SPSR.

Thanks!

[...]
> So, maybe something like this for the svc return path:
> 
> 	cpsid	f
> 	ldr	r1, [saved_spsr_svc]
> 	mov	r0, sp
> 	mrs	spsr_cxsf, r1
> 	ldmib	r0, {r1 - r14}
> 	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
...
>       ldmia   r7, {pc}^

Yup, I got the idea: we have to restore the SPSR in SVC mode, but
then we switch to FIQ mode and exit the exception while being in
the FIQ mode, that way CPU won't change our restored SPSR_svc.

As for "saved_spsr_svc", I think the easiest way to get it, is to
switch to FIQ mode temporary, and read it from the stack.

(Plus, cpsid is not available for older CPUs, but the thing is that
we don't touch global enable/disable FIQs/IRQs flags, so I guess
I don't actually need it.)

So, that's what I've applied on top:

@@ -33,7 +33,20 @@
 __fiq_svc:
 	svc_entry
 	fiq_handler
-	svc_exit r5				@ return from exception
+	mrs	r4, cpsr
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	ldr	r1, [sp, #8]
+	msr	cpsr_c, r4
+	msr	spsr_cxsf, r1
+	mov	r0, sp
+	ldmib	r0, {r1 - r14}
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	add	r8, r0, #S_PC
+	ldr	r9, [r0, #S_PSR]
+	msr	spsr_cxsf, r9
+	ldr	r0, [r0, #S_R0]
+	ldmia	r8, {pc}^


And the whole fixed up patch is down below:

- - - -
From: Anton Vorontsov <anton.vorontsov at linaro.org>
Subject: ARM: Add KGDB/KDB FIQ debugger generic code

The FIQ debugger may be used to debug situations when the kernel stuck
in uninterruptable sections, e.g. the kernel infinitely loops or
deadlocked in an interrupt or with interrupts disabled.

By default KGDB FIQ is disabled in runtime, but can be enabled with
kgdb_fiq.enable=1 kernel command line option.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/Kconfig                 |   18 +++++++
 arch/arm/include/asm/kgdb.h      |    8 +++
 arch/arm/kernel/Makefile         |    1 +
 arch/arm/kernel/kgdb_fiq.c       |  101 ++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/kgdb_fiq_entry.S |   92 ++++++++++++++++++++++++++++++++++
 5 files changed, 220 insertions(+)
 create mode 100644 arch/arm/kernel/kgdb_fiq.c
 create mode 100644 arch/arm/kernel/kgdb_fiq_entry.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c..ae6ddf1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -172,6 +172,24 @@ config GENERIC_ISA_DMA
 config FIQ
 	bool
 
+config ARCH_MIGHT_HAVE_FIQ
+	bool
+
+config KGDB_FIQ
+	bool "KGDB/KDB FIQ debugger"
+	depends on KGDB_KDB && ARCH_MIGHT_HAVE_FIQ && !THUMB2_KERNEL
+	select FIQ
+	help
+	  The FIQ debugger may be used to debug situations when the
+	  kernel stuck in uninterruptable sections, e.g. the kernel
+	  infinitely loops or deadlocked in an interrupt or with
+	  interrupts disabled.
+
+	  By default KGDB FIQ is disabled in runtime, but can be
+	  enabled with kgdb_fiq.enable=1 kernel command line option.
+
+	  If unsure, say N.
+
 config NEED_RET_TO_USER
 	bool
 
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 48066ce..807e547 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -11,6 +11,8 @@
 #define __ARM_KGDB_H__
 
 #include <linux/ptrace.h>
+#include <linux/linkage.h>
+#include <asm/exception.h>
 
 /*
  * GDB assumes that we're a user process being debugged, so
@@ -47,6 +49,12 @@ static inline void arch_kgdb_breakpoint(void)
 extern void kgdb_handle_bus_error(void);
 extern int kgdb_fault_expected;
 
+extern char kgdb_fiq_handler;
+extern char kgdb_fiq_handler_end;
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs);
+extern int __init kgdb_register_fiq(unsigned int mach_kgdb_fiq,
+		     void (*mach_kgdb_enable_fiq)(unsigned int irq, bool on),
+		     bool (*mach_is_kgdb_fiq)(unsigned int irq));
 #endif /* !__ASSEMBLY__ */
 
 /*
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..5aa079b 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_ATAGS_PROC)	+= atags.o
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
+obj-$(CONFIG_KGDB_FIQ)		+= kgdb_fiq_entry.o kgdb_fiq.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
 obj-$(CONFIG_OF)		+= devtree.o
diff --git a/arch/arm/kernel/kgdb_fiq.c b/arch/arm/kernel/kgdb_fiq.c
new file mode 100644
index 0000000..72a62c7
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq.c
@@ -0,0 +1,101 @@
+/*
+ * KGDB FIQ entry
+ *
+ * Copyright 2010 Google, Inc.
+ *		  Arve Hj?nnev?g <arve at android.com>
+ *		  Colin Cross <ccross at android.com>
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/hardirq.h>
+#include <linux/kgdb.h>
+#include <asm/fiq.h>
+#include <asm/exception.h>
+
+static int kgdb_fiq_enabled;
+module_param_named(enable, kgdb_fiq_enabled, int, 0600);
+MODULE_PARM_DESC(enable, "set to 1 to enable FIQ KGDB");
+
+static unsigned int kgdb_fiq;
+static void (*kgdb_enable_fiq)(unsigned int irq, bool on);
+static bool (*is_kgdb_fiq)(unsigned int irq);
+
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs)
+{
+	if (!is_kgdb_fiq(kgdb_fiq))
+		return;
+	dbg_io_ops->clear_irqs();
+
+	nmi_enter();
+	kgdb_handle_exception(1, 0, 0, regs);
+	nmi_exit();
+}
+
+static struct fiq_handler kgdb_fiq_desc = {
+	.name = "kgdb",
+};
+
+static long kgdb_fiq_setup_stack(void *info)
+{
+	struct pt_regs regs;
+
+	regs.ARM_sp = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER) +
+			THREAD_START_SP;
+	WARN_ON(!regs.ARM_sp);
+
+	set_fiq_regs(&regs);
+	return 0;
+}
+
+int kgdb_arch_enable_nmi(bool on)
+{
+	static int cnt;
+
+	if (cnt > 0 && on)
+		return cnt;
+	cnt += on ? 1 : -1;
+	kgdb_enable_fiq(kgdb_fiq, cnt > 0);
+	return cnt;
+}
+
+int __init kgdb_register_fiq(unsigned int mach_kgdb_fiq,
+		void (*mach_kgdb_enable_fiq)(unsigned int irq, bool on),
+		bool (*mach_is_kgdb_fiq)(unsigned int irq))
+{
+	int err;
+	int cpu;
+
+	if (!kgdb_fiq_enabled)
+		return -ENODEV;
+	if (kgdb_fiq)
+		return -EBUSY;
+
+	kgdb_fiq = mach_kgdb_fiq;
+	kgdb_enable_fiq = mach_kgdb_enable_fiq;
+	is_kgdb_fiq = mach_is_kgdb_fiq;
+
+	err = claim_fiq(&kgdb_fiq_desc);
+	if (err) {
+		pr_warn("%s: unable to claim fiq", __func__);
+		return err;
+	}
+
+	for_each_possible_cpu(cpu)
+		work_on_cpu(cpu, kgdb_fiq_setup_stack, NULL);
+
+	set_fiq_handler(&kgdb_fiq_handler,
+			&kgdb_fiq_handler_end - &kgdb_fiq_handler);
+
+	kgdb_arch_enable_nmi(1);
+	return 0;
+}
diff --git a/arch/arm/kernel/kgdb_fiq_entry.S b/arch/arm/kernel/kgdb_fiq_entry.S
new file mode 100644
index 0000000..a6a1ad1
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq_entry.S
@@ -0,0 +1,92 @@
+/*
+ * KGDB FIQ entry
+ *
+ * Copyright 1996,1997,1998 Russell King.
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/unwind.h>
+#include "entry-header.S"
+
+	.text
+
+@ This is needed for usr_entry/alignment_trap
+.LCcralign:
+	.long	cr_alignment
+.LCdohandle:
+	.long	kgdb_fiq_do_handle
+
+	.macro	fiq_handler
+	ldr	r1, =.LCdohandle
+	mov	r0, sp
+	adr	lr, BSYM(9997f)
+	ldr	pc, [r1]
+9997:
+	.endm
+
+	.align	5
+__fiq_svc:
+	svc_entry
+	fiq_handler
+	mrs	r4, cpsr
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	ldr	r1, [sp, #8]
+	msr	cpsr_c, r4
+	msr	spsr_cxsf, r1
+	mov	r0, sp
+	ldmib	r0, {r1 - r14}
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	add	r8, r0, #S_PC
+	ldr	r9, [r0, #S_PSR]
+	msr	spsr_cxsf, r9
+	ldr	r0, [r0, #S_R0]
+	ldmia	r8, {pc}^
+
+ UNWIND(.fnend		)
+ENDPROC(__fiq_svc)
+	.ltorg
+
+	.align	5
+__fiq_usr:
+	usr_entry
+	kuser_cmpxchg_check
+	fiq_handler
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user_from_irq
+ UNWIND(.fnend		)
+ENDPROC(__fiq_usr)
+	.ltorg
+
+	.global kgdb_fiq_handler
+kgdb_fiq_handler:
+
+	vector_stub	fiq, FIQ_MODE, 4
+
+	.long	__fiq_usr			@  0  (USR_26 / USR_32)
+	.long	__fiq_svc			@  1  (FIQ_26 / FIQ_32)
+	.long	__fiq_svc			@  2  (IRQ_26 / IRQ_32)
+	.long	__fiq_svc			@  3  (SVC_26 / SVC_32)
+	.long	__fiq_svc			@  4
+	.long	__fiq_svc			@  5
+	.long	__fiq_svc			@  6
+	.long	__fiq_svc			@  7
+	.long	__fiq_svc			@  8
+	.long	__fiq_svc			@  9
+	.long	__fiq_svc			@  a
+	.long	__fiq_svc			@  b
+	.long	__fiq_svc			@  c
+	.long	__fiq_svc			@  d
+	.long	__fiq_svc			@  e
+	.long	__fiq_svc			@  f
+
+	.global kgdb_fiq_handler_end
+kgdb_fiq_handler_end:
-- 
1.7.10.4



From cbouatmailru at gmail.com  Wed Aug  1 16:53:06 2012
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Wed, 1 Aug 2012 13:53:06 -0700
Subject: [PATCH 11/11] ARM: Get rid of .LCcralign local label usage in
 alignment_trap macro
In-Reply-To: <20120730141544.GJ6802@n2100.arm.linux.org.uk>
References: <20120730115719.GA5742@lizard>
 <1343649500-18491-11-git-send-email-anton.vorontsov@linaro.org>
 <20120730141544.GJ6802@n2100.arm.linux.org.uk>
Message-ID: <20120801205306.GB20714@lizard>

On Mon, Jul 30, 2012 at 03:15:44PM +0100, Russell King - ARM Linux wrote:
> On Mon, Jul 30, 2012 at 04:58:20AM -0700, Anton Vorontsov wrote:
> > This makes the code more izolated.
> > 
> > The downside of this is that we now have an additional branch and the
> > code itself is 8 bytes longer. But on the bright side, this new layout
> > can be more cache friendly since cr_alignment address might be already
> > in the cache line (not that I measured anything, it's just fun to think
> > about it).
> 
> The caches are harvard, so mixing data and code together does not increase
> performance.  Having data which is used by the same code in the same cache
> line results in better performance.
> 
> The additional branch will also cause a pipeline stall on older CPUs.
> 
> So no, I don't see any way that this is a performance improvement.  Please
> leave this as is.

Sure, will drop it.

Thanks!

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From anton.vorontsov at linaro.org  Wed Aug  1 17:02:31 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Wed, 1 Aug 2012 14:02:31 -0700
Subject: [PATCH 03/11] kdb: Implement disable_nmi command
In-Reply-To: <CAMbhsRS1cOf1T8k7K6CFmRA7M52AGPZ2TqmEnpZqDGYnbyetbw@mail.gmail.com>
References: <20120730115719.GA5742@lizard>
 <1343649500-18491-3-git-send-email-anton.vorontsov@linaro.org>
 <CAMbhsRS1cOf1T8k7K6CFmRA7M52AGPZ2TqmEnpZqDGYnbyetbw@mail.gmail.com>
Message-ID: <20120801210231.GC20714@lizard>

On Mon, Jul 30, 2012 at 10:33:34AM -0700, Colin Cross wrote:
> On Mon, Jul 30, 2012 at 4:58 AM, Anton Vorontsov
> <anton.vorontsov at linaro.org> wrote:
> > This command disables NMI-entry. If NMI source was previously shared with
> > a serial console ("debug port"), this effectively releases the port from
> > KDB exclusive use, and makes the console available for normal use.
> >
> > Of course, NMI can be reenabled, enable_nmi modparam is used for that:
> >
> >         echo 1 > /sys/module/kdb/parameters/enable_nmi
> 
> This is very different behavior from the FIQ debugger "console"
> command you are trying to replace.  In the FIQ debugger, everything
> goes through the FIQ/NMI, even when in console mode.  That means that
> the user can always get back to FIQ debugger/KDB mode using a special
> sequence (we use a break character).  With your implementation, if you
> switch from KDB to console to see if the console is working, and find
> that it is not working, you can never get back into KDB.

Ah, I see. But with disable_nmi, in addition to kernel console,
applications can use /dev/ttyXX as normal, and with 'console' command
that is not possible (at least w/o modifying applications to escape
magic sequence). So, I think we should have both commands, each would
handle its own use case.

(Initially I just tried to avoid adding another console driver, but
it seems there is no other way, heh.)

Thanks!

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From jon-hunter at ti.com  Wed Aug  1 18:34:19 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 1 Aug 2012 17:34:19 -0500
Subject: [PATCH V2 01/10] ARM: PMU: Add runtime PM Support
In-Reply-To: <20120801204731.GA9080@mudshark.cambridge.arm.com>
References: <4FD7C597.7060501@ti.com>
 <20120702095539.GD22239@mudshark.cambridge.arm.com> <4FF1D15E.7040301@ti.com>
 <20120702220117.GD25234@mudshark.cambridge.arm.com> <4FF6340A.6020409@ti.com>
 <50109233.3090302@ti.com> <20120726150534.GD6382@mudshark.cambridge.arm.com>
 <50115F3F.7050705@ti.com> <20120731151446.GK3903@mudshark.cambridge.arm.com>
 <50186524.6060903@ti.com> <20120801204731.GA9080@mudshark.cambridge.arm.com>
Message-ID: <5019AEEB.7010807@ti.com>


On 08/01/2012 03:47 PM, Will Deacon wrote:
> On Wed, Aug 01, 2012 at 12:07:16AM +0100, Jon Hunter wrote:
>> I have just updated my pmu branch for omap3/4. You can pull my latest
>> patches from [1].
> 
> Great, thanks for that. I've pushed out to perf/omap4 and I've also
> included your runtime PM hooks in my perf/updates branch. I have a fair
> amount of cleanup sitting in there as well, so I'll post that to the list
> at -rc1 as a candidate for -next. I'll obviously leave the omap-specific
> bits for others to handle, although I'll continue maintaining my branch
> until that's hit mainline.

I just updated today with Paul's latest patch he sent. I don't think
much changed from what I had in there yesterday.

>> In the latest series I have:
>> 1. Pulled in an omap3 clock domain fix from Paul [2]
>> 2. Rebased Paul's patch [3] on top of [2]. I have also made a couple
>>    updates to this patch and I need to get Paul's feedback.
>> 3. I have removed the OMAP3 PMU dependency on ETM from the Kconfig.
> 
> Fantastic! I actually already removed the OMAP3 Kconfig dependency in my
> perf/updates branch as part of removing CPU_HAS_PMU entirely, so you
> probably don't need to pursue that patch.

Great! Glad I don't have to worry about that.

>> I will probably send out the series once I align with Paul on the above
>> changes and the HWMOD stuff I have added for OMAP3 with Benoit.
> 
> Okey doke. If you need me to update my copy of your runtime PM patch,
> please shout (that seems to be a done deal afaict).

Yes it is good as far as I am concerned.

I am going to be out for a couple weeks, but when I get back I will get
the OMAP stuff out. I should probably doing some testing on -next too
with your latest changes.

Cheers
Jon




From shawn.guo at linaro.org  Wed Aug  1 20:34:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 08:34:25 +0800
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED
 Controller
In-Reply-To: <501904CB.9040104@free-electrons.com>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
 <20120801052424.GD1672@S2100-06.ap.freescale.net>
 <501904CB.9040104@free-electrons.com>
Message-ID: <20120802003422.GA2253@S2101-09.ap.freescale.net>

On Wed, Aug 01, 2012 at 12:28:27PM +0200, Maxime Ripard wrote:
> Thanks for the tip.
> However, I'm not sure this device will be mxs specific, since this
> controller is used on some other devices as well (I know for example
> that some uses it with the Arduino, even though it's not related to
> Linux), so relying on mxs-specific capabilities here might not be that
> great.
> 
Ok, agreed.  In that case, putting "1" in last cell of oled-reset-gpio
does not make any point then.

+Examples:
+ssd1307: oled at 3c {
+        compatible = "solomon,ssd1307fb-i2c";
+        reg = <0x3c>;
+        pwms = <&pwm 4 3000>;
+        oled-reset-gpio = <&gpio2 7 1>;
+        oled-reset-active-low;
+};

-- 
Regards,
Shawn



From festevam at gmail.com  Wed Aug  1 21:11:08 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  1 Aug 2012 22:11:08 -0300
Subject: [PATCH] ARM: imx6q-sabrelite: Setup CLKO IOMUX
Message-ID: <1343869868-29490-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

In order to have audio functional on mx6qsabrelite, it is necessary to setup
the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO pins as it provides the audio clock.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d42e851..1769f44 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -53,6 +53,7 @@
 						fsl,pins = <
 							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
 							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */		
 							   >;
 					};
 				};
-- 
1.7.1



From festevam at gmail.com  Wed Aug  1 21:16:44 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 1 Aug 2012 22:16:44 -0300
Subject: [RFC] ARM: imx6q-sabrelite: Add CLKO IOMUX
In-Reply-To: <CAOMZO5A2g+UCFuiP7yqYkFQ36F=2yrqJA3ssujeYXE_Q0Sz5nQ@mail.gmail.com>
References: <1343833836-14287-1-git-send-email-festevam@gmail.com>
 <CAOMZO5A2g+UCFuiP7yqYkFQ36F=2yrqJA3ssujeYXE_Q0Sz5nQ@mail.gmail.com>
Message-ID: <CAOMZO5AOfc675749bEqrZCxte6FTXm5VWob7hSDNmM3Q4Dj+QA@mail.gmail.com>

On Wed, Aug 1, 2012 at 5:17 PM, Fabio Estevam <festevam at gmail.com> wrote:

> I managed to get a board and tried it with current Linus' tree and
> also linux-next. Both result in:
>
> sgtl5000 0-000a: Device with ID register ffff is not a sgtl5000
> sgtl5000 0-000a: asoc: failed to probe CODEC sgtl5000.0-000a: -19
> asoc: failed to instantiate card imx6q-sabrelite-sgtl5000: -19
> imx-sgtl5000 sound.11: snd_soc_register_card failed (-19)
>
> Any ideas?

Ok, I sent a new patch that fixes this problem.

Also, I learned from Richard Zhao that audio can only be probed
correctly if we power off/on the board. Pressing the reset button
makes the audio probe to fail.


From shawn.guo at linaro.org  Wed Aug  1 21:40:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 09:40:00 +0800
Subject: [PATCH] ARM: imx6q-sabrelite: Setup CLKO IOMUX
In-Reply-To: <1343869868-29490-1-git-send-email-festevam@gmail.com>
References: <1343869868-29490-1-git-send-email-festevam@gmail.com>
Message-ID: <20120802013958.GB2253@S2101-09.ap.freescale.net>

On Wed, Aug 01, 2012 at 10:11:08PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> In order to have audio functional on mx6qsabrelite, it is necessary to setup
> the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO pins as it provides the audio clock.
> 
The commit messages should generally be wrapped at column 72.  I fixed
it up and queued the patch for 3.6-rc.  Thanks.

-- 
Regards,
Shawn

> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index d42e851..1769f44 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -53,6 +53,7 @@
>  						fsl,pins = <
>  							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
>  							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
> +							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */		
>  							   >;
>  					};
>  				};
> -- 
> 1.7.1
> 



From festevam at gmail.com  Wed Aug  1 21:43:39 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 1 Aug 2012 22:43:39 -0300
Subject: [PATCH] ARM: imx6q-sabrelite: Setup CLKO IOMUX
In-Reply-To: <20120802013958.GB2253@S2101-09.ap.freescale.net>
References: <1343869868-29490-1-git-send-email-festevam@gmail.com>
 <20120802013958.GB2253@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5BS-exRtxH8gkVtAki1AnY007uPB3oKcz56mnoaJ+EZGg@mail.gmail.com>

On Wed, Aug 1, 2012 at 10:40 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Wed, Aug 01, 2012 at 10:11:08PM -0300, Fabio Estevam wrote:
>> From: Fabio Estevam <fabio.estevam at freescale.com>
>>
>> In order to have audio functional on mx6qsabrelite, it is necessary to setup
>> the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO pins as it provides the audio clock.
>>
> The commit messages should generally be wrapped at column 72.  I fixed
> it up and queued the patch for 3.6-rc.  Thanks.

Ok, thanks.

With this patch applied audio is probed correctly now:

sgtl5000 0-000a: Using internal LDO instead of VDDD
sgtl5000 0-000a: sgtl5000 revision 0x11
imx-sgtl5000 sound.11:  sgtl5000 <-> 2028000.ssi mapping ok

,but I get error during aplay:

root at freescale /home$ aplay audio48k16S.wav
Playing WAVE 'audio48k16S.wav' : Signed 16 bit Little Endian,
Raimx-pcm-audio imx-pcm-audio: imx-pcm-audio hw params failed: -22
te 48000 Hz, Stereo
aplay: set_params:959: Unable to install hw params:
ACCESS:  RW_INTERLEAVED
FORMAT:  S16_LE
SUBFORMAT:  STD
SAMPLE_BITS: 16
FRAME_BITS: 32
CHANNELS: 2
RATE: 48000
PERIOD_TIME: (85333 85334)
PERIOD_SIZE: 4096
PERIOD_BYTES: 16384
PERIODS: 4
BUFFER_TIME: (341333 341334)
BUFFER_SIZE: 16384
BUFFER_BYTES: 65536
TICK_TIME: 0
root at freescale /home$

,and I guess this happens because of the missing mx6 sdma firmware.

Where can I get the mx6 sdma firmware binary from?

Thanks,

Fabio Estevam


From shawn.guo at linaro.org  Wed Aug  1 21:55:36 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 09:55:36 +0800
Subject: [PATCH] ARM: imx6q-sabrelite: Setup CLKO IOMUX
In-Reply-To: <CAOMZO5BS-exRtxH8gkVtAki1AnY007uPB3oKcz56mnoaJ+EZGg@mail.gmail.com>
References: <1343869868-29490-1-git-send-email-festevam@gmail.com>
 <20120802013958.GB2253@S2101-09.ap.freescale.net>
 <CAOMZO5BS-exRtxH8gkVtAki1AnY007uPB3oKcz56mnoaJ+EZGg@mail.gmail.com>
Message-ID: <20120802015535.GC2253@S2101-09.ap.freescale.net>

On Wed, Aug 01, 2012 at 10:43:39PM -0300, Fabio Estevam wrote:
> Where can I get the mx6 sdma firmware binary from?
> 
FSL tree, I think.

-- 
Regards,
Shawn



From minggr at gmail.com  Wed Aug  1 23:03:31 2012
From: minggr at gmail.com (Lin Ming)
Date: Thu, 2 Aug 2012 11:03:31 +0800
Subject: How to debug hard lockup issue
Message-ID: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>

Hi list,

I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
There is no any message output since it is hard lockup.

I tried watchdog, but watchdog can only reset the board. I still can't
get any info.

The hard lockup is possibly because kernel blocked/looped with
interrupts disabled.

Is there any non-maskable interrupt I can use to dump the kernel stack?
Or any other hint?

Thanks,
Lin Ming


From p.paneri at samsung.com  Thu Aug  2 01:44:13 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Thu, 2 Aug 2012 11:14:13 +0530
Subject: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <201208011520.02353.arnd@arndb.de>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <201208011520.02353.arnd@arndb.de>
Message-ID: <CAD6zSYN-prJO=dp8tJT8+4qcC3TxCXyVTU6-Xf5p20650Zb-ow@mail.gmail.com>

Hi Arnd,

On Wed, Aug 1, 2012 at 8:50 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 01 August 2012, Praveen Paneri wrote:
>> This patch set introduces a phy driver for samsung SoCs. It uses the existing
>> transceiver infrastructure to provide phy control functions. Use of this driver
>> can be extended for usb host phy as well. Over the period of time all the phy
>> related code for most of the samsung SoCs can be integrated here.
>> Removing the existing phy code from mach-s3c64xx but not from other machine
>> code.This driver is tested with smdk6410 and Exynos4210(with DT).
>
> This looks very nice overall, great work!
Thank you!
>
> We will still have to take care of the pmu isolation callback in the
> long run, when we get to the point of removing all auxdata. Do you
> have a plan on how to do that? If yes, it would be good to mention
> that in the changelog.
Yes! I understand this problem and this is the reason these patches
were sitting in my system for couple of weeks. In a  discussion with
Thomas an idea of using the existing regulator framework to
enable/disable numerous PHYs came up. For example the PMU unit
of Exynos4210 has a register set dedicated just to control USBD_PHY,
HDMI_PHY, MIPI_PHY, DAC_PHY and more. If a regulator with
each phy control register as LDO is written, the phy driver becomes a
static consumer and will modify as below.

diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
index 33119eb..4f69675 100644
--- a/drivers/usb/phy/sec_usbphy.c
+++ b/drivers/usb/phy/sec_usbphy.c
@@ -28,8 +28,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/regulator/consumer.h>
 #include <linux/usb/otg.h>
-#include <linux/platform_data/s3c-hsotg.h>

 #include "sec_usbphy.h"

@@ -41,7 +41,7 @@ enum sec_cpu_type {
 /*
  * struct sec_usbphy - transceiver driver state
  * @phy: transceiver structure
- * @plat: platform data
+ * @vusbphy: PMU regulator for usb phy
  * @dev: The parent device supplied to the probe function
  * @clk: usb phy clock
  * @regs: usb phy register memory base
@@ -49,7 +49,7 @@ enum sec_cpu_type {
  */
 struct sec_usbphy {
 	struct usb_phy	phy;
-	struct s3c_usbphy_plat *plat;
+	struct regulator *vusbphy;
 	struct device	*dev;
 	struct clk	*clk;
 	void __iomem	*regs;
@@ -187,8 +187,11 @@ static int sec_usbphy_init(struct usb_phy *phy)
 	}

 	/* Disable phy isolation */
-	if (sec->plat && sec->plat->pmu_isolation)
-		sec->plat->pmu_isolation(false);
+	ret = regulator_enable(sec->vusbphy);
+	if (ret) {
+		dev_err(sec->dev, "Failed to enable regulator for USBPHY\n");
+		return ret;
+	}

 	/* Initialize usb phy registers */
 	sec_usbphy_enable(sec);
@@ -208,8 +211,8 @@ static void sec_usbphy_shutdown(struct usb_phy *phy)
 	sec_usbphy_disable(sec);

 	/* Enable phy isolation */
-	if (sec->plat && sec->plat->pmu_isolation)
-		sec->plat->pmu_isolation(true);
+	if (regulator_disable(sec->vusbphy))
+		dev_err(sec->dev, "Failed to disable regulator for USBPHY\n");

 	/* Disable the phy clock */
 	sec_usbphy_clk_control(sec, false);
@@ -263,7 +266,6 @@ static int __devinit sec_usbphy_probe(struct
platform_device *pdev)
 		return -ENOMEM;

 	sec->dev		= &pdev->dev;
-	sec->plat		= pdata;
 	sec->regs		= phy_base;
 	sec->phy.dev		= sec->dev;
 	sec->phy.label		= "sec-usbphy";
@@ -271,6 +273,14 @@ static int __devinit sec_usbphy_probe(struct
platform_device *pdev)
 	sec->phy.shutdown	= sec_usbphy_shutdown;
 	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);

+	/* acquire regulator */
+	sec->vusbphy = regulator_get(sec->dev, "usbdphy");
+	if (IS_ERR_OR_NULL(sec->vusbphy)) {
+		dev_err(dev, "failed to get regulator 'usbdphy'\n");
+		ret = -ENXIO;
+		goto err;
+	}
+
 	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
 	if (ret)
 		goto err;
@@ -292,6 +302,7 @@ static int __exit sec_usbphy_remove(struct
platform_device *pdev)
 		clk_put(sec->clk);
 		sec->clk = NULL;
 	}
+	regulator_put(sec->vusbphy);

 	return 0;
 }

This kind of regulator, if generalised can be useful.
Please comment.
>
> My guess is that the PMU code should be moved into a higher-level
> abstraction. I don't know if you would use one of those we already
Could you please point out the location of the code.
> have or whether you'd introduce a new subsystem for those. Apparently.
Havent thought about it. Trying to work it out with the existing infra of the
kernel.
> other platforms have similar issues, so I'd suggest you leave the
> callback for now, but we should at some point discuss what to to
> about it.
>
>         Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Praveen


From olalilja at yahoo.se  Thu Aug  2 01:58:24 2012
From: olalilja at yahoo.se (Ola Lilja)
Date: Thu, 2 Aug 2012 07:58:24 +0200
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails,
 do not force all subsequent widgets to fail too
In-Reply-To: <20120801132022.GS11892@opensource.wolfsonmicro.com>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
 <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
Message-ID: <003901cd7073$d49cacc0$7dd60640$@se>

> -----Original Message-----
> From: Mark Brown [mailto:broonie at opensource.wolfsonmicro.com]
> Sent: den 1 augusti 2012 15:20
> To: Lee Jones
> Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> STEricsson_nomadik_linux at list.st.com; linus.walleij at stericsson.com;
> arnd at arndb.de; olalilja at yahoo.se; ola.o.lilja at stericsson.com; alsa-
> devel at alsa-project.org; lrg at ti.com
> Subject: Re: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force
> all subsequent widgets to fail too
> 
> On Wed, Aug 01, 2012 at 08:19:28AM +0100, Lee Jones wrote:
> > On 31/07/12 16:18, Mark Brown wrote:
> 
> > >I'm not going to apply this patch.  This isn't a vendor BSP, we
> > >shouldn't be putting random hacks like this in core code.
> 
> > BSP kernel or otherwise, it still seems wrong to me to fail and
> entire
> > audio driver just because of a broken link.
> 
> No, really.  Random disconnections in the DAPM graph are just endless
> pain from a support and debug point of view.  This isn't something that
> randomly breaks on specific hardware where we'd expect random errors at
> runtime, it's something that will never have worked - it seems clear
> nobody tested the mainline submission.
> 
> It's very disappointing to see such an error exist, and even more
> disappointing that there's no interest in fixing the driver.

(Yes, I know this mailer isn't configured correctly, but I'm on vacation
and have no Linux-computer/community-mailer available. However I find it
important to answer this)
Mark, you very well know that I have put in a lot of effort in getting our
Ux500-driver mainlined. This is something I have driven without really
getting sanctioned directly at working, rendering it even harder to find
time for it.
Accusing me of having "no interest in fixing the driver" is just absurd
regarding the time I've spent on this. I'm also still driving for
mainlining our upcoming drivers, so there is no lack of interest, nor lack
of activity at our side. I really think you could afford a bit more polite
attitude when doing reviews. It is not easy to fulfill every single aspect
of mainlining directly and there is (most likely) no one that purposely do
break any community rules. At least not from my side.

Regarding the problem with the failing DAPM-widget I can probably guess
What is going wrong when Lee is trying it out. There will be two failing
clock-supply widgets due to the fact that on the mainline-code these
clocks simply is not there yet. I have, of course, tested this driver
before submitting it, and I wouldn't dream on submitting a driver where
there were failing widgets/routes. Internally, I have put a patch with our
clock-tree for Ux500 on, but this is not mainline-quality code and that is
why it is not submitted with the other patches I sent. The clocks are in
the moment of writing being worked on by other persons in ST-Ericsson, and
I would not have had any time to be doing all this which is not in the
scope of my responsibilities (which is the audio-domain).
Before you told me to create the clock-supply widget-type, I had only
warnings for these failing clocks, as an intermediate solution, before
the clock-tree was submitted, but now they are implemented with the clock-
supply-type and there will be route-errors instead.
Linus W. could probably shed some light of when the missing clocks are to
be submitted.

Regards,
Ola



From thierry.reding at avionic-design.de  Thu Aug  2 01:58:39 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 2 Aug 2012 07:58:39 +0200
Subject: [PATCH v3 12/32] PCI/ARM: use PCIe capabilities access functions
 to simplify implementation
In-Reply-To: <5019654D.2000408@wwwdotorg.org>
References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
 <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>
 <5019654D.2000408@wwwdotorg.org>
Message-ID: <20120802055839.GA12241@avionic-0098.adnet.avionic-design.de>

On Wed, Aug 01, 2012 at 11:20:13AM -0600, Stephen Warren wrote:
> On 08/01/2012 09:54 AM, Jiang Liu wrote:
> > From: Jiang Liu <jiang.liu at huawei.com>
> > 
> > Use PCIe capabilities access functions to simplify PCIe ARM implementation.
> > 
> > Signed-off-by: Jiang Liu <liuj97 at gmail.com>
> 
> This is probably fine from my perspective assuming the underlying PCI
> API implementation is OKd by relevant people.
> 
> Thierry, can you comment on whether this will conflict with your Tegra
> PCIe driver series? If it doesn't, this patch can go through any
> relevant PCI tree. If it does, we may have to take this through the
> Tegra tree after merging the dependencies, or defer it to later.

I haven't touched those lines. tegra_pcie_relax_enable() only uses
generic PCI functions so I don't expect any conflicts. git blame
confirms that those lines haven't been changed in about 2 years.

Thierry
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From thierry.reding at avionic-design.de  Thu Aug  2 02:15:20 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 2 Aug 2012 08:15:20 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <5019611A.2060804@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50180547.9040603@wwwdotorg.org>
 <20120801063545.GA26791@avionic-0098.adnet.avionic-design.de>
 <5019611A.2060804@wwwdotorg.org>
Message-ID: <20120802061520.GE12241@avionic-0098.adnet.avionic-design.de>

On Wed, Aug 01, 2012 at 11:02:18AM -0600, Stephen Warren wrote:
> On 08/01/2012 12:35 AM, Thierry Reding wrote:
> > On Tue, Jul 31, 2012 at 10:18:15AM -0600, Stephen Warren wrote:
> >> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> >>> This patch series adds support for device tree based probing of
> >>> the PCIe controller found on Tegra SoCs.
> >> 
> >> Thierry,
> >> 
> >> I think one thing that would help here would be to split up this
> >> series into one per subsystem, and to get all the dependencies
> >> merged by the respective maintainers. Preferably, each subsystem
> >> would export a stable branch (perhaps consisting of just these
> >> patches) that I can then merge into the Tegra tree and use as a
> >> basis for the PCIe driver itself. Hopefully this approach will
> >> get more traction on all the non-Tegra changes. Does that sound
> >> like a good plan?
> > 
> > I don't understand. The series is already split up into
> > per-subsystem patches. I just didn't want to post them separately
> > so everybody on Cc would be able to see the big picture and the
> > reason why the patch was required.
> 
> There are separate patches that touch the different subsystems, but
> they're all scattered throughout the one series, rather than having e.g.:
> 
> * a series for the PCI tree
> * a series for the ARM core tree
> * a series for the OF/DT tree
> * a series for the Tegra tree, which indicates it depends on all of those.
> 
> I'm wondering if the reason you haven't seen much discussion/Acks from
> the maintainers of the non-Tegra trees is because this is a big scary
> series that touches a lot of stuff, and it's not necessarily clear for
> people unfamiliar with it why they're being CCd on it.

I see. If you think it'll help I can certainly split them up as you
suggested. I just thought it might be useful for everybody to know the
context. At least from my own experience I get annoyed when I'm Cc'ed
on a single patch in a larger series because it means I need to look
through other archives for the context.

Thierry
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From u.kleine-koenig at pengutronix.de  Thu Aug  2 03:15:30 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 2 Aug 2012 09:15:30 +0200
Subject: How to debug hard lockup issue
In-Reply-To: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
Message-ID: <20120802071530.GG10670@pengutronix.de>

Hello,

On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
> There is no any message output since it is hard lockup.
> 
> I tried watchdog, but watchdog can only reset the board. I still can't
> get any info.
> 
> The hard lockup is possibly because kernel blocked/looped with
> interrupts disabled.
> 
> Is there any non-maskable interrupt I can use to dump the kernel stack?
> Or any other hint?
Try enabling various debug options. The following come to (my) mind:

CONFIG_DETECT_HUNG_TASK
CONFIG_PROVE_LOCKING
CONFIG_DEBUG_ATOMIC_SLEEP
CONFIG_MAGIC_SYSRQ

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From b29396 at freescale.com  Thu Aug  2 03:08:10 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 2 Aug 2012 15:08:10 +0800
Subject: [RFC PATCH 1/1] ASoC: soc-dapm: warn if no avaiable path found
 for widget kcontrol
In-Reply-To: <20120801121516.GO11892@opensource.wolfsonmicro.com>
References: <1343387941-25266-1-git-send-email-b29396@freescale.com>
 <20120729202219.GA4384@opensource.wolfsonmicro.com>
 <20120801074952.GC30492@shlinux2.ap.freescale.net>
 <20120801121516.GO11892@opensource.wolfsonmicro.com>
Message-ID: <20120802070809.GD30492@shlinux2.ap.freescale.net>

On Wed, Aug 01, 2012 at 08:15:16PM +0800, Mark Brown wrote:
> On Wed, Aug 01, 2012 at 03:49:53PM +0800, Dong Aisheng wrote:
> > On Mon, Jul 30, 2012 at 04:22:19AM +0800, Mark Brown wrote:
> 
> > > This isn't a good idea, it's fairly common for widgets to have a "None"
> > > option which isn't expected to have an input.
> 
> > What i changed is mux widgets, i'm wondering is it possible or correct
> > the mux widget has no input path?
> > If i understand correct, we may need set correct input path
> > for mux widget, or why we still need a mux?
> 
> > Or can you help give an example that no input needed for mux widget?
> 
> The above is the most common example - one of the inputs to a mux being
> a "no input" option which shouldn't be connected to anything.  A mux
> with no inputs at all would be silly, but having one (or sometimes a
> couple for various reasons) that isn't connected isn't unusual.
> 

Understand.
Thanks for the info.

Regards
Dong Aisheng



From xiechao.mail at gmail.com  Thu Aug  2 03:24:44 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 2 Aug 2012 15:24:44 +0800
Subject: [PATCH 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <201207311154.42866.arnd@arndb.de>
References: <1343716792-10399-1-git-send-email-xiechao.mail@gmail.com>
 <1343716792-10399-2-git-send-email-xiechao.mail@gmail.com>
 <201207311154.42866.arnd@arndb.de>
Message-ID: <CADApbegvdRQ5swDrO-Y631K4AhsTigAG4=Mm82mT-smSA7XzJw@mail.gmail.com>

On Tue, Jul 31, 2012 at 7:54 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 31 July 2012, Chao Xie wrote:
>> +#define APBC_RTC       APBC_REG(0x28)
>> +#define APBC_TWSI0     APBC_REG(0x2c)
>> +#define APBC_KPC       APBC_REG(0x30)
>> +#define APBC_UART0     APBC_REG(0x00)
>> +#define APBC_UART1     APBC_REG(0x04)
>> +#define APBC_GPIO      APBC_REG(0x08)
>> +#define APBC_PWM0      APBC_REG(0x0c)
>> +#define APBC_PWM1      APBC_REG(0x10)
>> +#define APBC_PWM2      APBC_REG(0x14)
>> +#define APBC_PWM3      APBC_REG(0x18)
>> +#define APBC_SSP0      APBC_REG(0x81c)
>> +#define APBC_SSP1      APBC_REG(0x820)
>> +#define APBC_SSP2      APBC_REG(0x84c)
>> +#define APBC_SSP3      APBC_REG(0x858)
>> +#define APBC_SSP4      APBC_REG(0x85c)
>> +#define APBC_TWSI1     APBC_REG(0x6c)
>> +#define APBC_UART2     APBC_REG(0x70)
>> +
>> +#define APMU_SDH0      APMU_REG(0x54)
>> +#define APMU_SDH1      APMU_REG(0x58)
>> +#define APMU_USB       APMU_REG(0x5c)
>> +#define APMU_DISP0     APMU_REG(0x4c)
>> +#define APMU_CCIC0     APMU_REG(0x50)
>> +#define APMU_DFC       APMU_REG(0x60)
>
> Same comment as for patch 1: get the address from the device tree and just
> define those macros to the offset, like:
>
> #define APBC_RTC       0x28
>
> apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
> clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");
>
>         Arnd
>
hi
I would like to keep the mmp_clk_register_apbc to receive the "reg
base" not "reg offset".
It will be aligned with other kind of clock register APIs.
To read out APBC base register from device tree can be added at the
clock-pxa168.c, and it can map the registers and pass to the
mmp_clk_register_apbc.
Now, i have talked to Haojian who is doing device tree maintainer in
pxa/mmp. This kind of support is not added.
I suggest that after device tree support in clock can be added later
after other functionality of the clock framework is fine.


From santosh.shilimkar at ti.com  Thu Aug  2 03:34:25 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 2 Aug 2012 13:04:25 +0530
Subject: [PATCH V2 08/10] ARM: OMAP4: Prevent EMU power domain
 transitioning to OFF when in-use
In-Reply-To: <alpine.DEB.2.00.1208010932270.21488@utopia.booyaka.com>
References: <1339104132-26885-1-git-send-email-jon-hunter@ti.com>
 <1339104132-26885-9-git-send-email-jon-hunter@ti.com>
 <alpine.DEB.2.00.1207111441300.25585@utopia.booyaka.com>
 <500028B3.1040309@ti.com>
 <alpine.DEB.2.00.1207131418500.25585@utopia.booyaka.com>
 <50045D17.9050704@ti.com>
 <alpine.DEB.2.00.1207161228470.28834@utopia.booyaka.com>
 <50171841.40309@ti.com> <501760BF.8070801@ti.com> <5018210A.1040902@ti.com>
 <50187644.40308@ti.com>
 <alpine.DEB.2.00.1208010932270.21488@utopia.booyaka.com>
Message-ID: <CAMQu2gx_E2eZASK-Zj0A6D4tq0VMJXCPK5QMsp7w3GHVChAkXg@mail.gmail.com>

On Wed, Aug 1, 2012 at 9:06 PM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Hi Jon et al,
>
> Here's what I'm planning to queue here.  The only changes from what Jon
> posted are the patch changelog and some checkpatch fixes.  If anyone
> has any final comments, please let me know.
>
>
> - Paul
>
> From: Paul Walmsley <paul at pwsan.com>
> Date: Wed, 1 Aug 2012 09:11:20 -0600
> Subject: [PATCH] ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU
>  clockdomain idle problems
>
> The idle status of the IP blocks and clocks inside the EMU clockdomain
> isn't taken into account by the PRCM hardware when deciding whether
> the clockdomain is idle.  Add a workaround flag in the clockdomain
> code, CLKDM_MISSING_IDLE_REPORTING, to deal with this problem, and add
> the code necessary to support it.
>
> If CLKDM_MISSING_IDLE_REPORTING is set on a clockdomain, the
> clockdomain will be forced active whenever an IP block inside that
> clockdomain is in use, even if the clockdomain supports
> hardware-supervised idle.  When the kernel indicates that the last
> active IP block inside the clockdomain is no longer used, the
> clockdomain will be forced idle, or, if that mode is not supported in
> the hardware, it will be placed into hardware-supervised idle.
>
> This patch is an equal collaboration with Jon Hunter
> <jon-hunter at ti.com>.  Ming Lei <ming.lei at canonical.com>, Will Deacon
> <will.deacon at arm.com>, Madhav Vij <mvij at ti.com>, Kevin Hilman
> <khilman at ti.com>, Beno?t Cousson <b-cousson at ti.com>, and Santosh
> Shilimkar <santosh.shilimkar at ti.com> all made essential contributions
> to the understanding of EMU clockdomain power management on OMAP.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Jon Hunter <jon-hunter at ti.com>
> Cc: Ming Lei <ming.lei at canonical.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Cc: Madhav Vij <mvij at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Beno?t Cousson <b-cousson at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From Ian.Campbell at citrix.com  Thu Aug  2 03:35:51 2012
From: Ian.Campbell at citrix.com (Ian Campbell)
Date: Thu, 2 Aug 2012 08:35:51 +0100
Subject: [PATCH 01/24] arm: initial Xen support
In-Reply-To: <50197527.3070007@gmail.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <50197527.3070007@gmail.com>
Message-ID: <1343892951.7571.50.camel@dagon.hellion.org.uk>

On Wed, 2012-08-01 at 19:27 +0100, Rob Herring wrote:
> On 07/26/2012 10:33 AM, Stefano Stabellini wrote:
> > - Basic hypervisor.h and interface.h definitions.
> > - Skelethon enlighten.c, set xen_start_info to an empty struct.
> > - Do not limit xen_initial_domain to PV guests.
> > 
> > The new code only compiles when CONFIG_XEN is set, that is going to be
> > added to arch/arm/Kconfig in a later patch.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/Makefile                     |    1 +
> >  arch/arm/include/asm/hypervisor.h     |    6 +++
> >  arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
> >  arch/arm/include/asm/xen/interface.h  |   64 +++++++++++++++++++++++++++++++++
> 
> These headers don't seem particularly ARM specific. Could they be moved
> to asm-generic or include/linux?

Or perhaps include/xen.

A bunch of it also looks like x86 specific stuff which has crept in.
e.g. PARAVIRT_LAZY_FOO and paravirt_get_lazy_mode() are arch/x86
specific and shouldn't be called from common code (and aren't, AFAICT).





From marek.vasut at gmail.com  Thu Aug  2 03:39:50 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 2 Aug 2012 09:39:50 +0200
Subject: MMAP_MIN_ADDR problem/question
Message-ID: <201208020939.50225.marek.vasut@gmail.com>

Hi guys,

Me and a coleague of mine recently ran into the issue [1]. The problem is, that 
I set mmap_min_addr to 65536, making it unable for "su - user" command to work, 
it crashes with SIGKILL. I now at least see a solution (set it to 32768). Though 
I don't understand why. Can someone please exaplain me why it has to be 32768 an 
not more?

[1] http://ubuntu.5.n6.nabble.com/PATCH-DEFAULT-MMAP-MIN-ADDR-32768-for-arm-
td1604723.html

Thanks in advance!

Best regards,
Marek Vasut


From paul at pwsan.com  Thu Aug  2 03:43:45 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 2 Aug 2012 01:43:45 -0600 (MDT)
Subject: [PATCH 3/3] ARM: OMAP: omap_device: expose hwmod assert/deassert
 to omap devices
In-Reply-To: <1342466485-1050-4-git-send-email-omar.luna@linaro.org>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-4-git-send-email-omar.luna@linaro.org>
Message-ID: <alpine.DEB.2.00.1208020141140.4177@utopia.booyaka.com>

Hi Omar

On Mon, 16 Jul 2012, Omar Ramirez Luna wrote:

> This APIs are meant to be an interface to hwmod assert/deassert
> function, omap devices can call them through their platform data
> to control their reset lines, they are expected to know the name
> of the reset line they are trying to control.
> 
> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>

This one has been queued for 3.7 with a few changes. Some more detail was 
added to the function documentationrovement.  Also the multiple 
assignments were removed per Documentation/CodingStyle chapter 1:

"Don't put multiple assignments on a single line either."

Please let me know if you have any comments.


- Paul

From: Omar Ramirez Luna <omar.luna at linaro.org>
Date: Mon, 16 Jul 2012 14:21:25 -0500
Subject: [PATCH] ARM: OMAP2+: omap_device: expose hwmod assert/deassert to
 omap devices

This API is meant to be an interface to hwmod assert/deassert
function, omap devices can call them through their platform data to
control their reset lines, they are expected to know the name of the
reset line they are trying to control.

Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
[paul at pwsan.com: tweaked some documentation; fixed CodingStyle issue]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/plat-omap/include/plat/omap_device.h |    4 ++
 arch/arm/plat-omap/omap_device.c              |   55 +++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c..27bcc24 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -118,6 +118,10 @@ int omap_device_get_context_loss_count(struct platform_device *pdev);
 
 /* Other */
 
+int omap_device_assert_hardreset(struct platform_device *pdev,
+				 const char *name);
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+				 const char *name);
 int omap_device_idle_hwmods(struct omap_device *od);
 int omap_device_enable_hwmods(struct omap_device *od);
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..3b02312 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -925,6 +925,61 @@ int omap_device_shutdown(struct platform_device *pdev)
 }
 
 /**
+ * omap_device_assert_hardreset - set a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Set the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return value
+ * of omap_hwmod_assert_hardreset() in the event of any failure, or
+ * returns 0 upon success.
+ */
+int omap_device_assert_hardreset(struct platform_device *pdev, const char *name)
+{
+	struct omap_device *od = to_omap_device(pdev);
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < od->hwmods_cnt; i++) {
+		ret = omap_hwmod_assert_hardreset(od->hwmods[i], name);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+/**
+ * omap_device_deassert_hardreset - release a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Release the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return
+ * value of omap_hwmod_deassert_hardreset() in the event of any
+ * failure, or returns 0 upon success.
+ */
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+				   const char *name)
+{
+	struct omap_device *od = to_omap_device(pdev);
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < od->hwmods_cnt; i++) {
+		ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+/**
  * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
  * @od: struct omap_device *
  *
-- 
1.7.10.4



From ljkenny at gmail.com  Thu Aug  2 03:45:18 2012
From: ljkenny at gmail.com (Lee Jones)
Date: Thu, 2 Aug 2012 08:45:18 +0100
Subject: [alsa-devel] [PATCH 1/6] ASoC: dapm: If one widget fails, do not
 force all subsequent widgets to fail too
In-Reply-To: <20120801194134.GA4103@sirena.org.uk>
References: <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
 <20120801160824.GB11892@opensource.wolfsonmicro.com>
 <20120801194134.GA4103@sirena.org.uk>
Message-ID: <20120802074517.GA19231@gmail.com>

On Wed, Aug 01, 2012 at 08:41:34PM +0100, Mark Brown wrote:
> On Wed, Aug 01, 2012 at 05:08:24PM +0100, Mark Brown wrote:
> > On Wed, Aug 01, 2012 at 02:50:32PM +0100, Lee Jones wrote:
> 
> > > >It's very disappointing to see such an error exist, and even more
> > > >disappointing that there's no interest in fixing the driver.
> 
> > > This is incorrect. I'm sure the driver will be fixed post-haste when
> > > Ola returns back from vacation. If I can find some time I might
> > > dabble in the mean-time also.
> 
> > It may not be what you're intending but it's unfortuantely what's I'm
> > seeing.
> 
> Just to expand on this a bit since I've found myself pushing back in
> this sort of way far too often with these recent serieses and it's
> making everyone grumpy:
> 
> What I'm seeing here is a lot of patches getting sent with problems that
> I'd really not expect from someone sending such a high volume of
> patches.  Things like the lack of documentation for the DT bindings for
> example, it's something that's mandatory and which people doing lots of
> device tree work really ought to be aware of.  There's also noticable
> pushback with fixing some of these issues, and like I say this happens
> often enough to be really noticeable.
> 
> This isn't awesome from a review point of view, it's not nice to find
> issues in things and when it happens a lot for the wrong sort of thing
> it ends up seeming like the time spent doing the reviews isn't valued.

Okay, seeing as we're lying our cards on the table, here's my hand:

I'm in a very difficult position here. My initial task was to enable
Device Tree on all drivers associated with the Snowball low-cost 
development board. I was working very closely with Arnd, who was regularly
requesting code restructuring, both within the drivers and in platform
code. Something I was only too pleased to do. Then some of the original
authors noticed the restructuring and I subsequently spent a great deal of
time defending my actions. Now we have some systems in place to keep
everyone informed and happy.

Over time, the requests for Maintainers have Snowballed (pun intended). My 
task now seems to be enabling drivers for Device Tree _and_ fix all 
associated driver bugs, including any requested restructuring and API
adoption. What you fail to notice is that I am only one person, and hopping
all over the code-base trying to do everyone's bidding is no mean feat. In
reality I am no more obliged to fix driver bugs than you are. In fact as
the Maintainer of some of these subsystems, perhaps you could even help out
a bit?

With regards to the documentation, I am perfectly aware that any new binding
needs to be documented. Leaving it out was intentional until we can agree on
the bindings. After you told me you review the documentation rather than
the code bindings themselves ( pffft... ;) ) I added the documentation to
the patch-set. I always had every intention of writing them!

On your last point about feeling undervalued, that's not the case at all. I
do respect your opinion and value your reviews. They are always completed
quickly and are very thorough. If I had one complaint it's that you are
_too_ stringent. Some of this stuff really doesn't matter.

We are all trying to do good things here. Please try not to be too over-
critical. We all know Mainlining is a good thing. Perhaps less people
would be so frightened of it, thus more people would do it if the reviews
weren't such a ball-ache ( for want of a better expression :) ).


From dirk.behme at de.bosch.com  Thu Aug  2 03:44:34 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 2 Aug 2012 09:44:34 +0200
Subject: [PATCH] ARM: imx6q-sabrelite: Setup CLKO IOMUX
In-Reply-To: <1343869868-29490-1-git-send-email-festevam@gmail.com>
References: <1343869868-29490-1-git-send-email-festevam@gmail.com>
Message-ID: <501A2FE2.3030608@de.bosch.com>

On 02.08.2012 03:11, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> In order to have audio functional on mx6qsabrelite, it is necessary to setup
> the IOMUX for MX6Q_PAD_GPIO_0__CCM_CLKO pins as it provides the audio clock.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Tested-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk

> ---
>  arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index d42e851..1769f44 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -53,6 +53,7 @@
>  						fsl,pins = <
>  							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
>  							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
> +							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */		
>  							   >;
>  					};
>  				};


From paul at pwsan.com  Thu Aug  2 03:52:49 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 2 Aug 2012 01:52:49 -0600 (MDT)
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
Message-ID: <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>

Hello OMar,

On Mon, 16 Jul 2012, Omar Ramirez Luna wrote:

> For a reset sequence to complete cleanly, a module needs its
> associated clocks to be enabled, otherwise the timeout check
> in prcm code can print a false failure (failed to hardreset)
> that occurs because the clocks aren't powered ON and the status
> bit checked can't transition without them.
> 
> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>

Is enabling the clocks sufficient?  Or do we also need to enable the 
IP block, e.g. by calling

	if (soc_ops.enable_module)
		soc_ops.enable_module(oh);

as we do on OMAP4+ in _enable() ?


- Paul


From minggr at gmail.com  Thu Aug  2 03:59:36 2012
From: minggr at gmail.com (Lin Ming)
Date: Thu, 2 Aug 2012 15:59:36 +0800
Subject: How to debug hard lockup issue
In-Reply-To: <20120802071530.GG10670@pengutronix.de>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
 <20120802071530.GG10670@pengutronix.de>
Message-ID: <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>

On Thu, Aug 2, 2012 at 3:15 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> Hello,
>
> On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
>> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
>> There is no any message output since it is hard lockup.
>>
>> I tried watchdog, but watchdog can only reset the board. I still can't
>> get any info.
>>
>> The hard lockup is possibly because kernel blocked/looped with
>> interrupts disabled.
>>
>> Is there any non-maskable interrupt I can use to dump the kernel stack?
>> Or any other hint?
> Try enabling various debug options. The following come to (my) mind:
>
> CONFIG_DETECT_HUNG_TASK
> CONFIG_PROVE_LOCKING
> CONFIG_DEBUG_ATOMIC_SLEEP
> CONFIG_MAGIC_SYSRQ

These debug options are already enabled.
But it doesn't help.

Thanks.


From jaswinder.singh at linaro.org  Thu Aug  2 04:28:07 2012
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Thu, 2 Aug 2012 13:58:07 +0530
Subject: How to debug hard lockup issue
In-Reply-To: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
Message-ID: <CAJe_ZheUy_sFx-0M2Y36NAyOf3fPYM86pneY9vg03fvAE2KKFQ@mail.gmail.com>

On 2 August 2012 08:33, Lin Ming <minggr at gmail.com> wrote:
> Hi list,
>
> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
> There is no any message output since it is hard lockup.
>
> I tried watchdog, but watchdog can only reset the board. I still can't
> get any info.
>
Maybe take hint from http://www.denx.de/wiki/DULG/LinuxPostMortemAnalysis


From u.kleine-koenig at pengutronix.de  Thu Aug  2 04:34:13 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 2 Aug 2012 10:34:13 +0200
Subject: How to debug hard lockup issue
In-Reply-To: <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
 <20120802071530.GG10670@pengutronix.de>
 <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>
Message-ID: <20120802083413.GH10670@pengutronix.de>

On Thu, Aug 02, 2012 at 03:59:36PM +0800, Lin Ming wrote:
> On Thu, Aug 2, 2012 at 3:15 PM, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
> > Hello,
> >
> > On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
> >> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
> >> There is no any message output since it is hard lockup.
> >>
> >> I tried watchdog, but watchdog can only reset the board. I still can't
> >> get any info.
> >>
> >> The hard lockup is possibly because kernel blocked/looped with
> >> interrupts disabled.
> >>
> >> Is there any non-maskable interrupt I can use to dump the kernel stack?
> >> Or any other hint?
> > Try enabling various debug options. The following come to (my) mind:
> >
> > CONFIG_DETECT_HUNG_TASK
> > CONFIG_PROVE_LOCKING
> > CONFIG_DEBUG_ATOMIC_SLEEP
> > CONFIG_MAGIC_SYSRQ
> 
> These debug options are already enabled.
> But it doesn't help.
then if you don't have a hardware debugger handy you can try

	https://lkml.org/lkml/2012/5/26/83

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From g.liakhovetski at gmx.de  Thu Aug  2 05:11:16 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 2 Aug 2012 11:11:16 +0200 (CEST)
Subject: [PATCH/RFC 1/4] dma: add a function to request a DMA channel
 for a specific client
In-Reply-To: <1343284293.1726.8966.camel@vkoul-udesk3>
References: <Pine.LNX.4.64.1207171201550.11241@axis700.grange> 
 <Pine.LNX.4.64.1207171242230.17060@axis700.grange>
 <1343284293.1726.8966.camel@vkoul-udesk3>
Message-ID: <Pine.LNX.4.64.1208021101350.11412@axis700.grange>

Hi Vinod

Thanks for your review and sorry for a delayed reply.

On Thu, 26 Jul 2012, Vinod Koul wrote:

> On Tue, 2012-07-17 at 12:53 +0200, Guennadi Liakhovetski wrote:
> > Add a new channel-request function, that uses a device pointer and a
> > transfer direction to locate the required client DMA request line. Devices,
> > that require DMA channels exceeding the traditional Tx / Rx scheme, can use
> > the optional "name" parameter.
> > 
> > This new function uses a new DMA multiplexer interface. The new DMA request
> > line routing concept declares, that client DMA request lines are always
> > statically connected to a DMA provider. If a client is directly connected
> > to a DMAC, such a statical connection results in a 1-to-1 relationship
> > between client DMA request lines and DMAC DMA channels. A more flexible
> > configuration includes a multiplexer between clients and DMAC instances. In
> > these cases it is the multiplexer, that controls the routing. The initial
> > DMA multiplexer API consists of only one call-back: .request_chan(), that
> > finds the next free (physical or virtual) DMA channel, that can be routed
> > to the requested slave DMA interface. The actual routing, if required,
> > should be performed as a part of the dmaengine_slave_config() processing.
> > 
> > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> > ---
> >  drivers/dma/dmaengine.c   |   73 +++++++++++++++++++++++++++++++++++++++++++++
> >  include/linux/dmaengine.h |    9 +++++
> >  2 files changed, 82 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> > index 2397f6f..4fb927c 100644
> > --- a/drivers/dma/dmaengine.c
> > +++ b/drivers/dma/dmaengine.c
> > @@ -542,6 +542,79 @@ struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, v
> >  }
> >  EXPORT_SYMBOL_GPL(__dma_request_channel);
> >  
> > +/**
> > + * dma_request_slave_channel() - try to allocate an exclusive channel for device
> > + * @dev:	client device, for which a channel should be allocated
> > + * @direction:	transfer direction
> > + * @name:	optional name of the channel, used, when the direction is not
> > + *		sufficient to uniquely identify the DMA request
> > + */
> > +struct dma_chan *dma_request_slave_channel(struct device *dev,
> > +		enum dma_transfer_direction direction, const char *name)
> > +{
> > +	struct dma_device *device, *_d;
> > +	struct dma_chan *chan = NULL;
> > +	dma_cap_mask_t mask;
> > +	int err;
> > +
> > +	dma_cap_zero(mask);
> > +	dma_cap_set(DMA_SLAVE, mask);
> > +
> > +	/* Find a channel */
> > +	mutex_lock(&dma_list_mutex);
> > +	list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
> > +		if (!device->mux || !device->mux->request_chan)
> > +			continue;
> > +
> > +		if (!dma_device_satisfies_mask(device, mask)) {
> > +			pr_info("%s: wrong capabilities\n", __func__);
> > +			continue;
> > +		}
> > +
> > +		/* ensure that all channels are either private or public. */
> > +		if (!dma_has_cap(DMA_PRIVATE, device->cap_mask)) {
> > +			bool public = false;
> > +			list_for_each_entry(chan, &device->channels, device_node) {
> > +				/* some channels are already publicly allocated */
> > +				if (chan->client_count) {
> > +					public = true;
> > +					break;
> > +				}
> > +			}
> > +			if (public)
> > +				continue;
> > +		}
> > +
> > +		chan = device->mux->request_chan(device, dev, direction, name);
> NAK
> 
> 1. We dont want dmacs to have anything to do with filtering and
> allocating. That is role of dmaengien and we need to add stuff there
> only.
> 2. Even if we start using optional name argument here we still don't
> know out of 4 channels dmac supports which one to allocate.

I don't think we can be generic enough in the dmaengine core to identify 
which channels are suitable for all slave requests. This is why I proposed 
a concept of a DMA channel multiplexer driver, and this is exactly what 
this callback is. I tried to explain this in the patch description above. 
I thought we discussed this earlier in this thread and agreed, that a 
multiplexer API is the way to go with channel allocation. I think, I 
mentioned in one of my mails, that in the beginning I wanted to implement 
multiplexers as a proper (platform) device, but at least one problem with 
this is, that at least on my hardware the multiplexer and the DMAC share 
registers, and an MFD seems an overkill for this, but we can discuss this. 
I don't know, whether there are systems, where multiplexers are really 
separate hardware blocks, if there are, we can think of a way to handle 
those nicely too.

Thanks
Guennadi

> 
> > +		if (chan) {
> > +			dma_cap_set(DMA_PRIVATE, device->cap_mask);
> > +			device->privatecnt++;
> > +			err = dma_chan_get(chan);
> > +			if (!err)
> > +				break;
> > +			if (err == -ENODEV) {
> > +				pr_debug("%s: %s module removed\n", __func__,
> > +					 dma_chan_name(chan));
> > +				list_del_rcu(&device->global_node);
> > +			} else
> > +				pr_debug("%s: failed to get %s: (%d)\n",
> > +					 __func__, dma_chan_name(chan), err);
> > +
> > +			if (--device->privatecnt == 0)
> > +				dma_cap_clear(DMA_PRIVATE, device->cap_mask);
> > +
> > +			chan = NULL;
> > +		}
> > +	}
> > +	mutex_unlock(&dma_list_mutex);
> > +
> > +	pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
> > +		 chan ? dma_chan_name(chan) : NULL);
> > +
> > +	return chan;
> > +}
> > +EXPORT_SYMBOL_GPL(dma_request_slave_channel);
> > +
> >  void dma_release_channel(struct dma_chan *chan)
> >  {
> >  	mutex_lock(&dma_list_mutex);
> > diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> > index ccec62f..19b96d9 100644
> > --- a/include/linux/dmaengine.h
> > +++ b/include/linux/dmaengine.h
> > @@ -482,6 +482,11 @@ static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descr
> >  }
> >  #endif
> >  
> > +struct dma_multiplexer {
> > +	struct dma_chan *(*request_chan)(struct dma_device *, struct device *,
> > +				enum dma_transfer_direction, const char *);
> > +};
> > +
> >  /**
> >   * struct dma_tx_state - filled in to report the status of
> >   * a transfer.
> > @@ -553,6 +558,8 @@ struct dma_device {
> >  	int dev_id;
> >  	struct device *dev;
> >  
> > +	const struct dma_multiplexer *mux;
> > +
> >  	int (*device_alloc_chan_resources)(struct dma_chan *chan);
> >  	void (*device_free_chan_resources)(struct dma_chan *chan);
> >  
> > @@ -994,6 +1001,8 @@ void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
> >  struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
> >  struct dma_chan *net_dma_find_channel(void);
> >  #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
> > +struct dma_chan *dma_request_slave_channel(struct device *dev,
> > +		enum dma_transfer_direction direction, const char *name);
> >  
> >  /* --- Helper iov-locking functions --- */
> >  
> 
> 
> -- 
> ~Vinod
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From minggr at gmail.com  Thu Aug  2 05:30:28 2012
From: minggr at gmail.com (Lin Ming)
Date: Thu, 2 Aug 2012 17:30:28 +0800
Subject: How to debug hard lockup issue
In-Reply-To: <20120802083413.GH10670@pengutronix.de>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
 <20120802071530.GG10670@pengutronix.de>
 <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>
 <20120802083413.GH10670@pengutronix.de>
Message-ID: <CAF1ivSbbPtr0F3dWPXZMcWrzubGCg4mudcLQ1DKHe_HX5HqQbg@mail.gmail.com>

On Thu, Aug 2, 2012 at 4:34 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> On Thu, Aug 02, 2012 at 03:59:36PM +0800, Lin Ming wrote:
>> On Thu, Aug 2, 2012 at 3:15 PM, Uwe Kleine-K?nig
>> <u.kleine-koenig at pengutronix.de> wrote:
>> > Hello,
>> >
>> > On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
>> >> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
>> >> There is no any message output since it is hard lockup.
>> >>
>> >> I tried watchdog, but watchdog can only reset the board. I still can't
>> >> get any info.
>> >>
>> >> The hard lockup is possibly because kernel blocked/looped with
>> >> interrupts disabled.
>> >>
>> >> Is there any non-maskable interrupt I can use to dump the kernel stack?
>> >> Or any other hint?
>> > Try enabling various debug options. The following come to (my) mind:
>> >
>> > CONFIG_DETECT_HUNG_TASK
>> > CONFIG_PROVE_LOCKING
>> > CONFIG_DEBUG_ATOMIC_SLEEP
>> > CONFIG_MAGIC_SYSRQ
>>
>> These debug options are already enabled.
>> But it doesn't help.
> then if you don't have a hardware debugger handy you can try
>
>         https://lkml.org/lkml/2012/5/26/83

Will try pstore and PostMortem.

Thanks.


From jaswinder.singh at linaro.org  Thu Aug  2 05:40:16 2012
From: jaswinder.singh at linaro.org (Jassi Brar)
Date: Thu, 2 Aug 2012 15:10:16 +0530
Subject: How to debug hard lockup issue
In-Reply-To: <CAF1ivSbbPtr0F3dWPXZMcWrzubGCg4mudcLQ1DKHe_HX5HqQbg@mail.gmail.com>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
 <20120802071530.GG10670@pengutronix.de>
 <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>
 <20120802083413.GH10670@pengutronix.de>
 <CAF1ivSbbPtr0F3dWPXZMcWrzubGCg4mudcLQ1DKHe_HX5HqQbg@mail.gmail.com>
Message-ID: <CAJe_ZhezzWUOUNXx=nUx8BqTwcyy6C0Cq7FcNcSg-i0Q9otOKA@mail.gmail.com>

On 2 August 2012 15:00, Lin Ming <minggr at gmail.com> wrote:
> On Thu, Aug 2, 2012 at 4:34 PM, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
>> On Thu, Aug 02, 2012 at 03:59:36PM +0800, Lin Ming wrote:
>>> On Thu, Aug 2, 2012 at 3:15 PM, Uwe Kleine-K?nig
>>> <u.kleine-koenig at pengutronix.de> wrote:
>>> > Hello,
>>> >
>>> > On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
>>> >> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
>>> >> There is no any message output since it is hard lockup.
>>> >>
>>> >> I tried watchdog, but watchdog can only reset the board. I still can't
>>> >> get any info.
>>> >>
>>> >> The hard lockup is possibly because kernel blocked/looped with
>>> >> interrupts disabled.
>>> >>
>>> >> Is there any non-maskable interrupt I can use to dump the kernel stack?
>>> >> Or any other hint?
>>> > Try enabling various debug options. The following come to (my) mind:
>>> >
>>> > CONFIG_DETECT_HUNG_TASK
>>> > CONFIG_PROVE_LOCKING
>>> > CONFIG_DEBUG_ATOMIC_SLEEP
>>> > CONFIG_MAGIC_SYSRQ
>>>
>>> These debug options are already enabled.
>>> But it doesn't help.
>> then if you don't have a hardware debugger handy you can try
>>
>>         https://lkml.org/lkml/2012/5/26/83
>
> Will try pstore and PostMortem.
>
If the hang is after bootup, pstore is a better option. If the hang is
consistent and during boot, dumping __log_buf is the only option.


From broonie at opensource.wolfsonmicro.com  Thu Aug  2 05:59:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 2 Aug 2012 10:59:00 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <003901cd7073$d49cacc0$7dd60640$@se>
References: <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <003901cd7073$d49cacc0$7dd60640$@se>
Message-ID: <20120802095900.GC29157@opensource.wolfsonmicro.com>

On Thu, Aug 02, 2012 at 07:58:24AM +0200, Ola Lilja wrote:

> Accusing me of having "no interest in fixing the driver" is just absurd
> regarding the time I've spent on this. I'm also still driving for

Sorry, this is more directed at the current round of fixes that are
being sent than the driver itself - the patches to bodge around the
issue are being pushed fairly aggressively as an urgent fix without
even mentioning what the issue is.  I don't have any concerns with
the driver, only with the way it's being fixed.

> Regarding the problem with the failing DAPM-widget I can probably guess
> What is going wrong when Lee is trying it out. There will be two failing
> clock-supply widgets due to the fact that on the mainline-code these
> clocks simply is not there yet. I have, of course, tested this driver
> before submitting it, and I wouldn't dream on submitting a driver where
> there were failing widgets/routes. Internally, I have put a patch with our
> clock-tree for Ux500 on, but this is not mainline-quality code and that is

This sort of reliance on out of tree patches which any real user of the
device would be expected to have sounds like exactly the sort of thing
I'd expect to have caused an issue like this, and obviously the fix here
is to get the clocks in place (even if just as stubs, though I'd expect
there to be a major impact on the functionality of the device if it's
not clocked...) rather than to just bodge out the error checking.

It does also suggest that the DT binding for this device will need to
include the setup of these clocks (I believe the clock bindings for DT
have just gone into mainline this merge window but I'd need to check).


From arnd at arndb.de  Thu Aug  2 06:30:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 Aug 2012 10:30:19 +0000
Subject: [PATCH 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <CADApbegvdRQ5swDrO-Y631K4AhsTigAG4=Mm82mT-smSA7XzJw@mail.gmail.com>
References: <1343716792-10399-1-git-send-email-xiechao.mail@gmail.com>
 <201207311154.42866.arnd@arndb.de>
 <CADApbegvdRQ5swDrO-Y631K4AhsTigAG4=Mm82mT-smSA7XzJw@mail.gmail.com>
Message-ID: <201208021030.19986.arnd@arndb.de>

On Thursday 02 August 2012, Chao Xie wrote:
> > #define APBC_RTC       0x28
> >
> > apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
> > clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");
> >
> >         Arnd
> >
> hi
> I would like to keep the mmp_clk_register_apbc to receive the "reg
> base" not "reg offset".
> It will be aligned with other kind of clock register APIs.
> To read out APBC base register from device tree can be added at the
> clock-pxa168.c, and it can map the registers and pass to the
> mmp_clk_register_apbc.

Right, my mistake.

The above should have been something like

#define APBC_RTC       0x28
apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, clock_base + APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");

instead, with clock_base pointing to the __iomem token for the clock controller.

> Now, i have talked to Haojian who is doing device tree maintainer in
> pxa/mmp. This kind of support is not added.
> I suggest that after device tree support in clock can be added later
> after other functionality of the clock framework is fine.

You can do device tree support as a second step, but in this first step, you
should already start using ioremap to get the virtual address of the
clock controller, rather than hardcoding it.

	Arnd


From alexeev6 at yahoo.com  Thu Aug  2 07:07:27 2012
From: alexeev6 at yahoo.com (Dmitriy Alekseev)
Date: Thu, 2 Aug 2012 04:07:27 -0700 (PDT)
Subject: Enable messages during kernel boot on kernels v 3.*
Message-ID: <1343905647.34107.YahooMailNeo@web160601.mail.bf1.yahoo.com>

Hello!

I migrated with my embedded board from 2.6.33 to 3.5. Working with board via its ttyS0.
Since powering the device after message about?uncompressing Linux?and booting the kernel I can see nothing until welcome to command line message appeared. Copied whole .config from early kernel, which was much more talkative...
Please, tell, what is could be?

Config file attached.

Best regards,
Dmitriy Alekseev
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From arnd at arndb.de  Thu Aug  2 07:26:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 Aug 2012 11:26:52 +0000
Subject: [PATCH 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <CAD6zSYN-prJO=dp8tJT8+4qcC3TxCXyVTU6-Xf5p20650Zb-ow@mail.gmail.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <201208011520.02353.arnd@arndb.de>
 <CAD6zSYN-prJO=dp8tJT8+4qcC3TxCXyVTU6-Xf5p20650Zb-ow@mail.gmail.com>
Message-ID: <201208021126.52307.arnd@arndb.de>

On Thursday 02 August 2012, Praveen Paneri wrote:
> Yes! I understand this problem and this is the reason these patches
> were sitting in my system for couple of weeks. In a  discussion with
> Thomas an idea of using the existing regulator framework to
> enable/disable numerous PHYs came up. For example the PMU unit
> of Exynos4210 has a register set dedicated just to control USBD_PHY,
> HDMI_PHY, MIPI_PHY, DAC_PHY and more. If a regulator with
> each phy control register as LDO is written, the phy driver becomes a
> static consumer and will modify as below.

This is roughly what I had in mind, yes. The part I'm not sure about
is the subsystem to use. One could obviously express the same logic
using the clock or gpio framework, which would work but be conceptually
wrong.

Some other parts of the PMU functionality are provided through
pm-domains rather than regulators and I guess in theory it could
all be controlled through pm-domains. Maybe someone else has a better
understanding than me what the tradeoffs are here and which subsystem
should be used for the PMU.

	Arnd


From lee.jones at linaro.org  Thu Aug  2 08:12:56 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 Aug 2012 13:12:56 +0100
Subject: [PATCH 17/19] Documentation: Define the MOP500 Audio Machine
 Driver Device Tree bindings
In-Reply-To: <20120731135337.GM4468@opensource.wolfsonmicro.com>
References: <1343741953-17828-1-git-send-email-lee.jones@linaro.org>
 <1343741953-17828-18-git-send-email-lee.jones@linaro.org>
 <20120731135337.GM4468@opensource.wolfsonmicro.com>
Message-ID: <20120802121255.GA22201@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Tue, 31 Jul 2012 11:56:51 +0100
Subject: [PATCH 1/1] Documentation: Define the MOP500 Audio Machine Driver
 Device Tree bindings

Here we add the required documentation for the new Device Tree
bindings pertaining to the MOP500 Audio Machine driver.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/sound/ux500-mop500.txt     |   39 ++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ux500-mop500.txt

diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
new file mode 100644
index 0000000..48e071c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
@@ -0,0 +1,39 @@
+* MOP500 Audio Machine Driver
+
+This node is responsible for linking together all ux500 Audio Driver components.
+
+Required properties:
+ - compatible              : "stericsson,snd-soc-mop500"
+
+Non-standard properties:
+ - stericsson,cpu-dai      : Phandle to the CPU-side DAI
+ - stericsson,audio-codec  : Phandle to the Audio CODEC
+ - stericsson,card-name    : Over-ride default card name
+
+Example:
+
+	sound {
+		compatible = "stericsson,snd-soc-mop500";
+
+		stericsson,cpu-dai = <&msp1 &msp3>;
+		stericsson,audio-codec = <&codec>;
+	};
+
+	msp1: msp at 80124000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80124000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	msp3: msp at 80125000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80125000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
-- 
1.7.9.5


From lee.jones at linaro.org  Thu Aug  2 08:21:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 2 Aug 2012 13:21:03 +0100
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20120802122101.GA22228@gmail.com>

Patch withdrawn.

On Tue, Jul 31, 2012 at 02:31:23PM +0100, Lee Jones wrote:
> If a list of widgets is provided and one of them fails to be added as
> a control, the present semantics fail all subsequent widgets. A better
> solution would be to only fail that widget, but pursue in attempting
> to add the rest of the list.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  sound/soc/soc-dapm.c |    2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
> index eded657..7d9c154 100644
> --- a/sound/soc/soc-dapm.c
> +++ b/sound/soc/soc-dapm.c
> @@ -3095,8 +3095,6 @@ int snd_soc_dapm_new_controls(struct snd_soc_dapm_context *dapm,
>  			dev_err(dapm->dev,
>  				"ASoC: Failed to create DAPM control %s\n",
>  				widget->name);
> -			ret = -ENOMEM;
> -			break;
>  		}
>  		widget++;
>  	}
> -- 
> 1.7.9.5
> 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Thu Aug  2 08:23:26 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu,  2 Aug 2012 13:23:26 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent versions
 of binutils
Message-ID: <1343910206-3684-1-git-send-email-will.deacon@arm.com>

Recent upstream versions of binutils fail to assembler compressed/head.S
when passed the -march=all option:

http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html

The recommended workaround from the tools folks is not to pass the
option, and instead let the assembler deduce the CPU type based on the
features used by the code.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/boot/compressed/Makefile |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index bb26756..0f7f3f4 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -126,7 +126,6 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
-- 
1.7.4.1



From lee.jones at linaro.org  Thu Aug  2 08:45:32 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 02 Aug 2012 13:45:32 +0100
Subject: [PATCH 18/19] Documentation: Define the MSP Driver Device Tree
 bindings
In-Reply-To: <20120731151024.GA4468@opensource.wolfsonmicro.com>
References: <1343741953-17828-1-git-send-email-lee.jones@linaro.org>
 <1343741953-17828-19-git-send-email-lee.jones@linaro.org>
 <20120731135539.GO4468@opensource.wolfsonmicro.com>
 <5017F2E2.4040100@linaro.org>
 <20120731151024.GA4468@opensource.wolfsonmicro.com>
Message-ID: <501A766C.1060502@linaro.org>

On 31/07/12 16:10, Mark Brown wrote:
> On Tue, Jul 31, 2012 at 03:59:46PM +0100, Lee Jones wrote:
>> On 31/07/12 14:55, Mark Brown wrote:
>
>>>> +Optional properties:
>>>> + - interrupts       : The interrupt outputs from the device.
>
>>> If there's more than one interrupt then how are they ordered?
>
>> It doesn't matter. If there are any more than one (which there
>> aren't in this case), we usually use the interrupt-names property
>> then request them by name in the driver.
>
> So the binding therefore needs to say "The interrupt output from the
> device" as there's only one output supported.  If we were using
> interrupt-names then we'd need to document what the supported names are.

Okay, I've changed 'outputs' to 'output'.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From hvaibhav at ti.com  Thu Aug  2 08:55:42 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 2 Aug 2012 12:55:42 +0000
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <50193263.8070907@ti.com>
References: <50191F00.1040501@ti.com> <50193263.8070907@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7DF32@DBDE01.ent.ti.com>

On Wed, Aug 01, 2012 at 19:12:59, Cousson, Benoit wrote:
> Hi Vaibhav,
> 
> On 08/01/2012 02:20 PM, Vaibhav Hiremath wrote:
> > Hi,
> > 
> > In OMAP world, we have omap_device layer, which exports api's like
> > omap_device_build() to create and register platform_device to the
> > kernel. This layer understands hwmod infrastructure and parses all the
> > platform specific information from it.
> > Now with DT migration, the same thing is achieved using a notifier,
> > which in turn omap_device_build_from_dt(), which in turn does same thing.
> > 
> > One of the thing which is happening in both execution path is, creating
> > alias for functional clock (hwmod_data->main_clk) for each device
> > getting created with the con_id = "fck".
> > 
> > Now the problem with this is,
> > 
> > The clk_get() api will not work, unless we pass both the arguments (dev,
> > con_id) properly. Now expecting driver to always label con_id with "fck"
> > is undesirable, as the same driver can be reused on multiple platforms,
> > which can be non-omap and/or non-ti platforms.
> > Also we have multiple examples where driver simply calls (which is right)
> > 
> > clk = clk_get(&pdev->dev, NULL);
> 
> Mmm, I don't know, but even if this is right, shouldn't we avoid such
> usage. It might be better to be explicit than assuming that the IP will
> always have an unique clock.

Isn't this IP specific and driver must know how many clocks he has to 
address? So I believe it will not be assumption, the driver is written
considering clocksources and in some cases IP is designed and meant to
receive only one clock input.

Let me bring a real example which I am dealing with now,

DCAN IP integrated in AM335X device, this IP is not from TI. This is Bosch
IP and doesn't follow any of the TI standards, like HighLander spec. Even it doesn't have SYSCONF register for that matter. The driver is generic, 
obviously used across non-ti devices already and driver is implemented with
Clk_get(dev, NULL);


> Some IP does have several inputs that might or not be connected
> depending or the integration or on the version. So even if only one
> clock is useful at some point it will not always be true.
> We had similar issue with the IRQ lines in the past.
> 
> > This would fail on OMAP platforms, unless you modify clockxxx_data.c
> > file with,
> > 
> > CLK("<device>",  NULL,           &xxx_fck,    CK_34XX),
> > 
> > 
> > Devices specially with only one clock source always prefer not to
> > specify con_id.
> 
> How many devices do you have with only one clock source? Could you
> provide the list of drivers that assume that?
>

I did simple grep on drivers/ directory and here is the output of it -


# grep -r clk_get drivers/* | grep -r ", NULL"

drivers/ata/pata_arasan_cf.c:   acdev->clk = clk_get(&pdev->dev, NULL);
drivers/ata/sata_mv.c:  hpriv->clk = clk_get(&pdev->dev, NULL);
drivers/ata/pata_imx.c: priv->clk = clk_get(&pdev->dev, NULL);
drivers/char/hw_random/nomadik-rng.c:   rng_clk = clk_get(&dev->dev, NULL);
drivers/char/hw_random/picoxcell-rng.c: rng_clk = clk_get(&pdev->dev, NULL);
drivers/char/hw_random/atmel-rng.c:     trng->clk = clk_get(&pdev->dev, NULL);
drivers/crypto/ux500/cryp/cryp_core.c:  device_data->clk = clk_get(&pdev->dev, NULL);
drivers/crypto/ux500/hash/hash_core.c:  device_data->clk = clk_get(dev, NULL);
drivers/crypto/mv_cesa.c:       cp->clk = clk_get(&pdev->dev, NULL);
drivers/dma/ipu/ipu_idmac.c:    ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
drivers/dma/mv_xor.c:   msp->clk = clk_get(&pdev->dev, NULL);
drivers/dma/mxs-dma.c:  mxs_dma->clk = clk_get(&pdev->dev, NULL);
drivers/dma/ste_dma40.c:        clk = clk_get(&pdev->dev, NULL);
drivers/gpio/gpio-pxa.c:        clk = clk_get(&pdev->dev, NULL);
drivers/gpio/gpio-stp-xway.c:   clk = clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-davinci.c:       dev->clk = clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-sirf.c:  clk = clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-designware-platdrv.c:    dev->clk = clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-nomadik.c:       dev->clk = clk_get(&adev->dev, NULL);
drivers/i2c/busses/i2c-nuc900.c:        i2c->clk = clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-tegra.c: clk = devm_clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-pxa.c:   i2c->clk = clk_get(&dev->dev, NULL);
drivers/i2c/busses/i2c-sh_mobile.c:     pd->clk = clk_get(&dev->dev, NULL);
drivers/i2c/busses/i2c-imx.c:   i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
drivers/i2c/busses/i2c-pnx.c:   alg_data->clk = clk_get(&pdev->dev, NULL);
drivers/ide/palm_bk3710.c:      clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/nomadik-ske-keypad.c:    keypad->clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/tnetv107x-keypad.c:      kp->clk = clk_get(dev, NULL);
drivers/input/keyboard/pxa27x_keypad.c: keypad->clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/tegra-kbc.c:     kbc->clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/spear-keyboard.c:        kbd->clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/ep93xx_keypad.c: keypad->clk = clk_get(&pdev->dev, NULL);
drivers/input/keyboard/w90p910_keypad.c:        keypad->clk = clk_get(&pdev->dev, NULL);
drivers/input/touchscreen/lpc32xx_ts.c: tsc->clk = clk_get(&pdev->dev, NULL);
drivers/input/touchscreen/w90p910_ts.c: w90p910_ts->clk = clk_get(&pdev->dev, NULL);
drivers/input/touchscreen/tnetv107x-ts.c:       ts->clk = clk_get(dev, NULL);
drivers/leds/leds-renesas-tpu.c:        p->clk = clk_get(&pdev->dev, NULL);
drivers/media/video/mx3_camera.c:       mx3_cam->clk = clk_get(&pdev->dev, NULL);
drivers/media/video/pxa_camera.c:       pcdev->clk = clk_get(&pdev->dev, NULL);
drivers/media/video/mx2_camera.c:       pcdev->clk_csi = clk_get(&pdev->dev, NULL);
drivers/media/video/mx2_emmaprp.c:      pcdev->clk_emma = clk_get(&pdev->dev, NULL);
drivers/mfd/davinci_voicecodec.c:       davinci_vc->clk = clk_get(&pdev->dev, NULL);
drivers/mfd/ti-ssp.c:   ssp->clk = clk_get(dev, NULL);
drivers/misc/spear13xx_pcie_gadget.c:           clk = clk_get_sys("pcie1", NULL);
drivers/misc/spear13xx_pcie_gadget.c:           clk = clk_get_sys("pcie2", NULL);
drivers/mmc/host/mxs-mmc.c:     host->clk = clk_get(&pdev->dev, NULL);
drivers/mmc/host/mvsdio.c:      host->clk = clk_get(&pdev->dev, NULL);
drivers/mmc/host/pxamci.c:      host->clk = clk_get(&pdev->dev, NULL);
drivers/mmc/host/sdhci-spear.c: sdhci->clk = clk_get(&pdev->dev, NULL);
drivers/mmc/host/sdhci-tegra.c: clk = clk_get(mmc_dev(host->mmc), NULL);
drivers/mmc/host/mmci.c:        host->clk = clk_get(&dev->dev, NULL);
drivers/mtd/devices/spear_smi.c:        dev->clk = clk_get(&pdev->dev, NULL);
drivers/mtd/nand/gpmi-nand/gpmi-nand.c: res->clock = clk_get(&this->pdev->dev, NULL);
drivers/mtd/nand/fsmc_nand.c:   host->clk = clk_get(&pdev->dev, NULL);
drivers/mtd/nand/nuc900_nand.c: nuc900_nand->clk = clk_get(&pdev->dev, NULL);
drivers/mtd/nand/orion_nand.c:  clk = clk_get(&pdev->dev, NULL);
drivers/mtd/nand/orion_nand.c:  clk = clk_get(&pdev->dev, NULL);
drivers/mtd/nand/pxa3xx_nand.c: info->clk = clk_get(&pdev->dev, NULL);
drivers/net/can/c_can/c_can_platform.c: clk = clk_get(&pdev->dev, NULL);
drivers/net/can/flexcan.c:              clk = clk_get(&pdev->dev, NULL);



 
> Most IPs in OMAP does have a fck and an ick so that does not seems nice
> or even consistent to me to do a clk_get(&pdev->dev, NULL) for "fck" and
> clk_get(&pdev->dev, "ick") for the ick.
> 

I completely agree from OMAP device perspective, but it may not be 
applicable for other architectures or devices, right?


> > And it seems wrong thing, as across platforms IP integration can be very
> > different and you can not expect to change the clock-tree table always.
> 
> FWIW, that table is done for that exact purpose. And we introduced the
> automatic "fck" alias creation mainly to make things easier, but that
> method is still very valid, and if the default alias is not good enough
> for the driver nothing should prevent you to create a new one.
> 
> > So the option here we have is,
> > 
> > 1. Instead of creating alias with "fck", create an alias only with dev
> > pointer, that means con_id = NULL.
> > I have already tested this and it works on AM33xx platform.
> 
> Do you mean assuming that the fck is always the clock with a NULL
> con_id? And any other clocks for that device will have thus to use a
> explicit name?
> 

Yes.

> > 2. Add a new flag inside hwmod or omap_device, so that it can be read at
> > omap_device layer and based on that we can decide whether to add con_id
> > or not while invoking clkdev_alloc().
> 
> hwmod is supposed to contain only HW related information. In that case
> it will be Linux driver dependent and not really HW dependent.
> That one is thus not really acceptable.
> 

Agreed, that was one of the options. What about omap_device???

> > This may be required to support legacy drivers which are not migrated to
> > runtime_pm and still calls clk_get() for both "fck" and "ick", so here
> > we need "fck" clk alias.
> 
> We can use "fck" even with runtime_pm. Just because sometime you need to
> get the clock rate of the main clock.
> 
> > Any comments or opinion on this? Based on the feedback I can create the
> > changes and submit it to the list.
> 
> Well, a #3 suggestion might be to enforce the usage of fck alias in the
> drivers instead of assuming that the "NULL" entry is the proper one.
> 

Can we??? Not sure whether we can really force this.

> And a #4 will be to create a extra entry in the clkdev like you have done.
> 

If nothing works out from above options, then this is the only option we 
have.
But the issue here is, how can we fix dev_id? With DT support I have to 
Really make use of "of_dev_auxdata" to fix dev id.


> For my point of view, the #4 seems to be the one that will minimize the
> overall change in the drivers and is probably the best one.
> 
> That being said, since the DT clock binding is merged now, the whole
> automatic alias creation might disappear as soon as we will have DT boot
> on all the platforms... OK, we are not really there still :-)
> 

Yeah, I know and understand. This is another issue we have. So we should not consider automatic aliases here.


Thanks,
Vaibhav



From hvaibhav at ti.com  Thu Aug  2 09:04:37 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 2 Aug 2012 13:04:37 +0000
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <20120801141414.GM7405@n2100.arm.linux.org.uk>
References: <50191F00.1040501@ti.com>
 <20120801141414.GM7405@n2100.arm.linux.org.uk>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7DF5C@DBDE01.ent.ti.com>

On Wed, Aug 01, 2012 at 19:44:14, Russell King - ARM Linux wrote:
> On Wed, Aug 01, 2012 at 05:50:16PM +0530, Vaibhav Hiremath wrote:
> > The clk_get() api will not work, unless we pass both the arguments (dev,
> > con_id) properly. Now expecting driver to always label con_id with "fck"
> > is undesirable, as the same driver can be reused on multiple platforms,
> > which can be non-omap and/or non-ti platforms.
> 
> Why not?
> 
> The connection ID is defined by the driver, and the platform stuff is
> expected to provide drivers with what they require.  It's not the other
> way around (platforms don't tell drivers what they require.)
> 
> In other words, if the device has two clocks, one called ick and one called
> fck, then the device _should_ use clk_get() specifying "ick" for one, and
> "fck" for the other.
> 
> And platforms better provide an "ick" and a "fck" for the device, even if
> they have no respresentation for one or other of them (in which case you
> supply a dummy clock.)
> 

Russell, I completely agree with you, infact I am on the same page.
Let me give you a real example, which I am dealing with now,

On AM335x device we have integrated DCAN, this IP is not from TI.
IP is from Bosch and doesn't follow any of the TI IP standards, like 
HighLander spec. The IP is just integrated with interconnect bus and given a 
required clocksource (in this case its one clock). 

The driver for this IP is generic, (drivers/net/can/c_can/c_can_platform.c) 
obviously used across non-ti devices already and driver is implemented with,
    clk_get(dev, NULL);


So in this context,

  1. Either I have to change the driver to specify con_id. Modifying a 
     generic driver.
OR
  2. Change the clock tree table to add an clock entry for this clock with 
     con_id = NULL, but I have to fix dev_id as well. I believe this I can 
     achieve using " of_dev_auxdata".
OR
  3. Create an alias at run time (omap is doing currently) with using 
     dynamic dev_id and con_id = NULL.


Thanks,
Vaibhav


From linux at arm.linux.org.uk  Thu Aug  2 09:04:11 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 14:04:11 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
Message-ID: <20120802130411.GU6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 01:23:26PM +0100, Will Deacon wrote:
> Recent upstream versions of binutils fail to assembler compressed/head.S
> when passed the -march=all option:
> 
> http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html
> 
> The recommended workaround from the tools folks is not to pass the
> option, and instead let the assembler deduce the CPU type based on the
> features used by the code.

That doesn't work for all binutils - binutils historically has had to be
told explicitly what architecture its building for and won't "deduce"
it from the code.

Maybe this needs to be a build-time test whether the assembler accepts it?


From andriy.shevchenko at linux.intel.com  Thu Aug  2 09:06:47 2012
From: andriy.shevchenko at linux.intel.com (Andy Shevchenko)
Date: Thu,  2 Aug 2012 16:06:47 +0300
Subject: [PATCH] mtd: use %*ph[CN] to dump small buffers
Message-ID: <1343912807-29355-1-git-send-email-andriy.shevchenko@linux.intel.com>

There is new format specified that helps to dump small buffers. It makes the
code simplier and nicer.

Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Jiandong Zheng <jdzheng at broadcom.com>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-samsung-soc at vger.kernel.org
---
 drivers/mtd/devices/doc2001plus.c |   14 +++-----------
 drivers/mtd/devices/docg3.c       |   12 +++---------
 drivers/mtd/nand/bcm_umi_bch.c    |   17 ++++-------------
 drivers/mtd/nand/s3c2410.c        |   11 ++++-------
 4 files changed, 14 insertions(+), 40 deletions(-)

diff --git a/drivers/mtd/devices/doc2001plus.c b/drivers/mtd/devices/doc2001plus.c
index 04eb2e4..753e50b 100644
--- a/drivers/mtd/devices/doc2001plus.c
+++ b/drivers/mtd/devices/doc2001plus.c
@@ -659,23 +659,15 @@ static int doc_read(struct mtd_info *mtd, loff_t from, size_t len,
 #ifdef ECC_DEBUG
 			printk("%s(%d): Millennium Plus ECC error (from=0x%x:\n",
 				__FILE__, __LINE__, (int)from);
-			printk("        syndrome= %02x:%02x:%02x:%02x:%02x:"
-				"%02x\n",
-				syndrome[0], syndrome[1], syndrome[2],
-				syndrome[3], syndrome[4], syndrome[5]);
-			printk("          eccbuf= %02x:%02x:%02x:%02x:%02x:"
-				"%02x\n",
-				eccbuf[0], eccbuf[1], eccbuf[2],
-				eccbuf[3], eccbuf[4], eccbuf[5]);
+			printk("        syndrome= %*phC\n", 6, syndrome);
+			printk("          eccbuf= %*phC\n", 6, eccbuf);
 #endif
 				ret = -EIO;
 		}
 	}
 
 #ifdef PSYCHO_DEBUG
-	printk("ECC DATA at %lx: %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n",
-	       (long)from, eccbuf[0], eccbuf[1], eccbuf[2], eccbuf[3],
-	       eccbuf[4], eccbuf[5]);
+	printk("ECC DATA at %lx: %*ph\n", (long)from, 6, eccbuf);
 #endif
 	/* disable the ECC engine */
 	WriteDOC(DOC_ECC_DIS, docptr , Mplus_ECCConf);
diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c
index f70854d..d34d83b 100644
--- a/drivers/mtd/devices/docg3.c
+++ b/drivers/mtd/devices/docg3.c
@@ -919,19 +919,13 @@ static int doc_read_oob(struct mtd_info *mtd, loff_t from,
 		eccconf1 = doc_register_readb(docg3, DOC_ECCCONF1);
 
 		if (nboob >= DOC_LAYOUT_OOB_SIZE) {
-			doc_dbg("OOB - INFO: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
-				oobbuf[0], oobbuf[1], oobbuf[2], oobbuf[3],
-				oobbuf[4], oobbuf[5], oobbuf[6]);
+			doc_dbg("OOB - INFO: %*phC\n", 7, oobbuf);
 			doc_dbg("OOB - HAMMING: %02x\n", oobbuf[7]);
-			doc_dbg("OOB - BCH_ECC: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
-				oobbuf[8], oobbuf[9], oobbuf[10], oobbuf[11],
-				oobbuf[12], oobbuf[13], oobbuf[14]);
+			doc_dbg("OOB - BCH_ECC: %*phC\n", 7, oobbuf + 8);
 			doc_dbg("OOB - UNUSED: %02x\n", oobbuf[15]);
 		}
 		doc_dbg("ECC checks: ECCConf1=%x\n", eccconf1);
-		doc_dbg("ECC HW_ECC: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
-			hwecc[0], hwecc[1], hwecc[2], hwecc[3], hwecc[4],
-			hwecc[5], hwecc[6]);
+		doc_dbg("ECC HW_ECC: %*phC\n", 7, hwecc);
 
 		ret = -EIO;
 		if (is_prot_seq_error(docg3))
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
index c8799a0..ce39c87 100644
--- a/drivers/mtd/nand/bcm_umi_bch.c
+++ b/drivers/mtd/nand/bcm_umi_bch.c
@@ -154,19 +154,10 @@ static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
 #if defined(NAND_BCM_UMI_DEBUG)
 			printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
 			       __func__, sectorIdx);
-			printk(KERN_WARNING
-			       "%s data %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x\n",
-			       __func__, datap[0], datap[1], datap[2], datap[3],
-			       datap[4], datap[5], datap[6], datap[7]);
-			printk(KERN_WARNING
-			       "%s ecc  %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x %02x %02x "
-					 "%02x %02x %02x\n",
-			       __func__, eccCalc[0], eccCalc[1], eccCalc[2],
-			       eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
-			       eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
-			       eccCalc[11], eccCalc[12]);
+			printk(KERN_WARNING "%s data %*ph\n",
+			       __func__, 8, datap);
+			printk(KERN_WARNING "%s ecc  %*ph\n",
+			       __func__, 13, eccCalc);
 			BUG();
 #endif
 			mtd->ecc_stats.failed++;
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 91121f3..7bc6f7d 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -463,10 +463,8 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 	diff1 = read_ecc[1] ^ calc_ecc[1];
 	diff2 = read_ecc[2] ^ calc_ecc[2];
 
-	pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
-		 __func__,
-		 read_ecc[0], read_ecc[1], read_ecc[2],
-		 calc_ecc[0], calc_ecc[1], calc_ecc[2],
+	pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
+		 __func__, 3, read_ecc, 3, calc_ecc,
 		 diff0, diff1, diff2);
 
 	if (diff0 == 0 && diff1 == 0 && diff2 == 0)
@@ -566,8 +564,7 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
 	ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 	ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 
-	pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
-		 ecc_code[0], ecc_code[1], ecc_code[2]);
+	pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 
 	return 0;
 }
@@ -581,7 +578,7 @@ static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
 	ecc_code[1] = ecc >> 8;
 	ecc_code[2] = ecc >> 16;
 
-	pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
+	pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
 
 	return 0;
 }
-- 
1.7.10.4



From linux at arm.linux.org.uk  Thu Aug  2 09:09:09 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 14:09:09 +0100
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7DF32@DBDE01.ent.ti.com>
References: <50191F00.1040501@ti.com> <50193263.8070907@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA7DF32@DBDE01.ent.ti.com>
Message-ID: <20120802130909.GN7405@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 12:55:42PM +0000, Hiremath, Vaibhav wrote:
> On Wed, Aug 01, 2012 at 19:12:59, Cousson, Benoit wrote:
> > Mmm, I don't know, but even if this is right, shouldn't we avoid such
> > usage. It might be better to be explicit than assuming that the IP will
> > always have an unique clock.
> 
> Isn't this IP specific and driver must know how many clocks he has to 
> address? So I believe it will not be assumption, the driver is written
> considering clocksources and in some cases IP is designed and meant to
> receive only one clock input.

Devices themselves define what clocks they need to operate.  Drivers
designed to be used with the clk API are supposed to obtain all clocks
that the device requires.  The device dictates what clocks are required.

This does not change the way drivers deal with clocks depending on how
they're integrated into a SoC: devices that need five clocks should
_always_ call clk_get() five times to get each of those five clocks.

Where a clock is not individually distinguishable or available in a SoC,
the SoC level must arrange to return a dummy clock to the device driver.

If a device only takes one single clock, then using a connection ID of
NULL is acceptable.  Otherwise, an explicit name must be used, which is
chosen either from the device IPs documentation (eg, the name of the
_clock_ _input_) or with a lack of that information, a name chosen by
the driver writer according to the function of the clock.

You must stop thinking about the picture you get when something gets
integrated into a SoC... and making driver code conditional on the view
presented by the SoC.


From linux at arm.linux.org.uk  Thu Aug  2 09:12:50 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 14:12:50 +0100
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7DF5C@DBDE01.ent.ti.com>
References: <50191F00.1040501@ti.com>
 <20120801141414.GM7405@n2100.arm.linux.org.uk>
 <79CD15C6BA57404B839C016229A409A83EA7DF5C@DBDE01.ent.ti.com>
Message-ID: <20120802131250.GO7405@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 01:04:37PM +0000, Hiremath, Vaibhav wrote:
> On Wed, Aug 01, 2012 at 19:44:14, Russell King - ARM Linux wrote:
> > On Wed, Aug 01, 2012 at 05:50:16PM +0530, Vaibhav Hiremath wrote:
> > > The clk_get() api will not work, unless we pass both the arguments (dev,
> > > con_id) properly. Now expecting driver to always label con_id with "fck"
> > > is undesirable, as the same driver can be reused on multiple platforms,
> > > which can be non-omap and/or non-ti platforms.
> > 
> > Why not?
> > 
> > The connection ID is defined by the driver, and the platform stuff is
> > expected to provide drivers with what they require.  It's not the other
> > way around (platforms don't tell drivers what they require.)
> > 
> > In other words, if the device has two clocks, one called ick and one called
> > fck, then the device _should_ use clk_get() specifying "ick" for one, and
> > "fck" for the other.
> > 
> > And platforms better provide an "ick" and a "fck" for the device, even if
> > they have no respresentation for one or other of them (in which case you
> > supply a dummy clock.)
> > 
> 
> Russell, I completely agree with you, infact I am on the same page.
> Let me give you a real example, which I am dealing with now,
> 
> On AM335x device we have integrated DCAN, this IP is not from TI.
> IP is from Bosch and doesn't follow any of the TI IP standards, like 
> HighLander spec. The IP is just integrated with interconnect bus and given a 
> required clocksource (in this case its one clock). 
> 
> The driver for this IP is generic, (drivers/net/can/c_can/c_can_platform.c) 
> obviously used across non-ti devices already and driver is implemented with,
>     clk_get(dev, NULL);

So, elsewhere it only has one clock.  Are there any other clocks it needs
on OMAP?

If the answer is no, then the driver is doing the right thing, and OMAP's
clk stuff needs to be adjusted to suit the drivers requirements.

I've said many times over the years that clock connection IDs are defined
by the device or driver and *nothing* else - they're certainly *not* source
names.

That's why, when I modified OMAP drivers to fix them, and they take an
interface and function clock, they end up asking for "ick" and "fck" not
"blah_ick" and "blah_fck".


From maxime.ripard at free-electrons.com  Thu Aug  2 09:35:22 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 02 Aug 2012 15:35:22 +0200
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED
 Controller
In-Reply-To: <20120802003422.GA2253@S2101-09.ap.freescale.net>
References: <1343730576-20494-1-git-send-email-maxime.ripard@free-electrons.com>
 <1343730576-20494-2-git-send-email-maxime.ripard@free-electrons.com>
 <20120801052424.GD1672@S2100-06.ap.freescale.net>
 <501904CB.9040104@free-electrons.com>
 <20120802003422.GA2253@S2101-09.ap.freescale.net>
Message-ID: <501A821A.2060209@free-electrons.com>

Le 02/08/2012 02:34, Shawn Guo a ?crit :
> On Wed, Aug 01, 2012 at 12:28:27PM +0200, Maxime Ripard wrote:
>> Thanks for the tip.
>> However, I'm not sure this device will be mxs specific, since this
>> controller is used on some other devices as well (I know for example
>> that some uses it with the Arduino, even though it's not related to
>> Linux), so relying on mxs-specific capabilities here might not be that
>> great.
>>
> Ok, agreed.  In that case, putting "1" in last cell of oled-reset-gpio
> does not make any point then.
> 
> +Examples:
> +ssd1307: oled at 3c {
> +        compatible = "solomon,ssd1307fb-i2c";
> +        reg = <0x3c>;
> +        pwms = <&pwm 4 3000>;
> +        oled-reset-gpio = <&gpio2 7 1>;
> +        oled-reset-active-low;
> +};
> 
Ok, I will do that then.

Maxime

-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From konrad.wilk at oracle.com  Thu Aug  2 10:13:41 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Thu, 2 Aug 2012 10:13:41 -0400
Subject: [Xen-devel] [PATCH 01/24] arm: initial Xen support
In-Reply-To: <1343892951.7571.50.camel@dagon.hellion.org.uk>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <50197527.3070007@gmail.com>
 <1343892951.7571.50.camel@dagon.hellion.org.uk>
Message-ID: <20120802141341.GE16749@phenom.dumpdata.com>

On Thu, Aug 02, 2012 at 08:35:51AM +0100, Ian Campbell wrote:
> On Wed, 2012-08-01 at 19:27 +0100, Rob Herring wrote:
> > On 07/26/2012 10:33 AM, Stefano Stabellini wrote:
> > > - Basic hypervisor.h and interface.h definitions.
> > > - Skelethon enlighten.c, set xen_start_info to an empty struct.
> > > - Do not limit xen_initial_domain to PV guests.
> > > 
> > > The new code only compiles when CONFIG_XEN is set, that is going to be
> > > added to arch/arm/Kconfig in a later patch.
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  arch/arm/Makefile                     |    1 +
> > >  arch/arm/include/asm/hypervisor.h     |    6 +++
> > >  arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
> > >  arch/arm/include/asm/xen/interface.h  |   64 +++++++++++++++++++++++++++++++++
> > 
> > These headers don't seem particularly ARM specific. Could they be moved
> > to asm-generic or include/linux?
> 
> Or perhaps include/xen.
> 
> A bunch of it also looks like x86 specific stuff which has crept in.
> e.g. PARAVIRT_LAZY_FOO and paravirt_get_lazy_mode() are arch/x86
> specific and shouldn't be called from common code (and aren't, AFAICT).

The could be moved out..


From shawn.guo at linaro.org  Thu Aug  2 10:23:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 22:23:54 +0800
Subject: [PATCH] ARM: dts: imx: fix gpio interrupts property
In-Reply-To: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
References: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
Message-ID: <1343917434-4358-1-git-send-email-shawn.guo@linaro.org>

Commit 88cde8b (ARM: dts: imx: update #interrupt-cells for gpio nodes)
changes gpio #interrupt-cells from 1 to 2 without updating the users.
It causes the gpio irq requesting call failing in client driver's probe
function.

Add the irq type cell for those gpio interrupt users to fix their
driver probe failure.

Reported-by: Fabio Estevam <festevam at gmail.com>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx51-babbage.dts |    2 +-
 arch/arm/boot/dts/imx53-ard.dts     |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index de065b5..cd86177 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -53,7 +53,7 @@
 						spi-max-frequency = <6000000>;
 						reg = <0>;
 						interrupt-parent = <&gpio1>;
-						interrupts = <8>;
+						interrupts = <8 0x4>;
 
 						regulators {
 							sw1_reg: sw1 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 5b8eafc..a02083a 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -64,7 +64,7 @@
 			reg = <0xf4000000 0x2000000>;
 			phy-mode = "mii";
 			interrupt-parent = <&gpio2>;
-			interrupts = <31>;
+			interrupts = <31 0x8>;
 			reg-io-width = <4>;
 			smsc,irq-push-pull;
 		};
-- 
1.7.5.4




From marex at denx.de  Thu Aug  2 10:58:38 2012
From: marex at denx.de (Marek Vasut)
Date: Thu, 2 Aug 2012 16:58:38 +0200
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120801203106.GW4483@opensource.wolfsonmicro.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
 <20120801203106.GW4483@opensource.wolfsonmicro.com>
Message-ID: <201208021658.38237.marex@denx.de>

Dear Mark Brown,

Thanks for the review!

> On Mon, Jul 23, 2012 at 10:40:48PM +0200, Marek Vasut wrote:
> > This is slightly reworked version of the SPI driver.
> > Support for DT has been added and it's been converted
> > to queued API.
> 
> Looks reasonable overall.
> 
> > +	bits_per_word = dev->bits_per_word;
> > +	if (t && t->bits_per_word)
> > +		bits_per_word = t->bits_per_word;
> > +
> > +	if (bits_per_word != 8) {
> > +		dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
> > +					__func__, bits_per_word);
> > +		return -EINVAL;
> > +	}
> > 
> > +	if (dev->max_speed_hz)
> > +		hz = dev->max_speed_hz;
> > +	if (t && t->speed_hz)
> > +		hz = t->speed_hz;
> > +	if (hz == 0) {
> > +		dev_err(&dev->dev, "Cannot continue with zero clock\n");
> > +		return -EINVAL;
> > +	}
> 
> These two blocks use a different style (the first does the first assign
> unconditionally, the second uses initialisation with declaration).  I
> prefer the first style but YMMV and it doesn't matter.
> 
> For the missing clock rate might it make sense to just use whatever the
> clock happens to come out as?

Hm, the max_speed_hz should be the cap for the transfer speed. I will change the 
function to this:

hz = dev->max_speed_hz;
if (t && t->speed_hz)
        hz = min(hz, t->speed_hz);

> > +static void mxs_spi_cleanup(struct spi_device *dev)
> > +{
> > +	return;
> > +}
> 
> Empty functions are generally a warning sign...  why do we need this
> one?

Good catch, thanks!

> > +static int __devexit mxs_spi_remove(struct platform_device *pdev)
> > +{
> > 
> > +	clk_disable_unprepare(ssp->clk);
> 
> It'd be nice to only keep the clocks enabled while doing transfers but
> again totally non-essential.

Hm, this is spread across mxs. Shawn, is there any plan for PM implementation 
for MXS ?

Best regards,
Marek Vasut


From marex at denx.de  Thu Aug  2 11:00:42 2012
From: marex at denx.de (Marek Vasut)
Date: Thu, 2 Aug 2012 17:00:42 +0200
Subject: [PATCH 08/10 RESEND] spi: Add DMA support into SPI driver
In-Reply-To: <20120801203448.GX4483@opensource.wolfsonmicro.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-9-git-send-email-marex@denx.de>
 <20120801203448.GX4483@opensource.wolfsonmicro.com>
Message-ID: <201208021700.43159.marex@denx.de>

Dear Mark Brown,

> On Mon, Jul 23, 2012 at 10:40:50PM +0200, Marek Vasut wrote:
> > +		/*
> > +		 * Small blocks can be transfered via PIO.
> > +		 * Measured by empiric means:
> > +		 *
> > +		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
> > +		 *
> > +		 * DMA only: 2.164808 seconds, 473.0KB/s
> > +		 * Combined: 1.676276 seconds, 610.9KB/s
> > +		 */
> 
> I've seen other devices end up using the FIFO length as the decision
> point here which makes intuitive sense to me unless the FIFO is
> extremely deep.

Yep, that's all good. This device has not too deep FIFO, but the reason I chose 
not to go that way is because the DMA allocations have some overhead too and 
this values seemed to be the best.

> Not reviewed this properly yet but it looks OK from a first read
> through.

Thanks!

Best regards,
Marek Vasut


From will.deacon at arm.com  Thu Aug  2 11:01:23 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 Aug 2012 16:01:23 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802130411.GU6802@n2100.arm.linux.org.uk>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
Message-ID: <20120802150123.GE9838@mudshark.cambridge.arm.com>

Hi Russell,

On Thu, Aug 02, 2012 at 02:04:11PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 02, 2012 at 01:23:26PM +0100, Will Deacon wrote:
> > Recent upstream versions of binutils fail to assembler compressed/head.S
> > when passed the -march=all option:
> > 
> > http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html
> > 
> > The recommended workaround from the tools folks is not to pass the
> > option, and instead let the assembler deduce the CPU type based on the
> > features used by the code.
> 
> That doesn't work for all binutils - binutils historically has had to be
> told explicitly what architecture its building for and won't "deduce"
> it from the code.

Damn. I thought there would be a reason why we passed the option in the
first place.

> Maybe this needs to be a build-time test whether the assembler accepts it?

That could be tricky since gas still accepts the option, but fails later
with:

arch/arm/boot/compressed/head.S: Assembler messages:
arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2'

How about grabbing the march from KBUILD_AFLAGS instead (see below)?

Will

---8<---

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index bb26756..3774f0d 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -126,7 +126,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all
+asflags-y := -Wa,$(lastword $(filter -march=%,$(KBUILD_AFLAGS)))
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \



From shawn.guo at linaro.org  Thu Aug  2 11:01:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 23:01:51 +0800
Subject: [PATCH 1/2] ARM: imx: enable emi_slow_gate clock for imx5
Message-ID: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>

The imx5 common clock migration causes a regression with smsc911x
driver on imx53-ard board, where a smsc lan9220 controller gets
connected on imx53 with EIM interface.  EIM needs clock emi_slow_gate
to be functional.  In the new imx5 clock driver, there is no use count
incremented for the clock by enabling it, so the framework closes the
clock at late init time and makes EIM stop working then.

Enable emi_slow_gate in clock driver initialization to fix the
regression.

Cc: stable at vger.kernel.org
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/clk-imx51-imx53.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index f608669..6eee32a 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_prepare_enable(clk[aips_tz2]); /* fec */
 	clk_prepare_enable(clk[spba]);
 	clk_prepare_enable(clk[emi_fast_gate]); /* fec */
+	clk_prepare_enable(clk[emi_slow_gate]);
 	clk_prepare_enable(clk[tmax1]);
 	clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
 	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
-- 
1.7.5.4




From shawn.guo at linaro.org  Thu Aug  2 11:01:52 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 23:01:52 +0800
Subject: [PATCH 2/2] ARM: dts: imx53-ard: add regulators for lan9220
In-Reply-To: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>
References: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1343919712-6240-2-git-send-email-shawn.guo@linaro.org>

Since commit c7e963f (net/smsc911x: Add regulator support), the lan9220
device tree probe fails on imx53-ard board, because the commit makes
VDD33A and VDDVARIO supplies mandatory for the driver.

Add a fixed dummy 3V3 supplying lan9220 to fix the regression.

Cc: stable at vger.kernel.org
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx53-ard.dts |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 5b8eafc..fa95f4a 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -66,10 +66,30 @@
 			interrupt-parent = <&gpio2>;
 			interrupts = <31>;
 			reg-io-width = <4>;
+			/*
+			 * VDD33A and VDDVARIO of LAN9220 are supplied by
+			 * SW4_3V3 of LTC3589.  Before the regulator driver
+			 * for this PMIC is available, we use a fixed dummy
+			 * 3V3 regulator to get LAN9220 driver probing work.
+			 */
+			vdd33a-supply = <&reg_3p3v>;
+			vddvario-supply = <&reg_3p3v>;
 			smsc,irq-push-pull;
 		};
 	};
 
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
-- 
1.7.5.4




From shawn.guo at linaro.org  Thu Aug  2 11:13:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 2 Aug 2012 23:13:00 +0800
Subject: [PATCH v2 1/1] ARM: mx28evk: add missed clkmux select for saif
In-Reply-To: <1343791216-22515-1-git-send-email-b29396@freescale.com>
References: <1343791216-22515-1-git-send-email-b29396@freescale.com>
Message-ID: <20120802151259.GB11136@S2101-09.ap.freescale.net>

On Wed, Aug 01, 2012 at 11:20:16AM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Added missed clkmux setting for mx28evk.
> 
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Wolfram Sang <w.sang at pengutronix.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>

Applied, thanks.

-- 
Regards,
Shawn



From thomas.petazzoni at free-electrons.com  Thu Aug  2 11:13:47 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Thu,  2 Aug 2012 17:13:47 +0200
Subject: [PATCH] arm: mvebu: fix typo in .dtsi comment for Armada XP SoCs
Message-ID: <1343920427-26128-1-git-send-email-thomas.petazzoni@free-electrons.com>

The comment was wrongly referring to Armada 370 while the file is
related to Armada XP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-xp.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index e1fa7e6..71d6b5d 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -12,7 +12,7 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  *
- * Contains definitions specific to the Armada 370 SoC that are not
+ * Contains definitions specific to the Armada XP SoC that are not
  * common to all Armada SoCs.
  */
 
-- 
1.7.9.5



From zonque at gmail.com  Thu Aug  2 11:30:36 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 17:30:36 +0200
Subject: Current state of AM33xx patches
In-Reply-To: <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
References: <4FD5BA4C.9070706@gmail.com> <4FE326A8.8090807@gmail.com>
 <4FE8AB37.7030907@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
Message-ID: <501A9D1C.8080305@gmail.com>

On 31.07.2012 21:29, Koen Kooi wrote:

> 2/3 of the way there:
> 
> http://patchwork.ozlabs.org/patch/174085/
> http://patchwork.ozlabs.org/patch/174086/
> 
> I keep failing to create a .dts that doesn't upset the dtc, so I don't have it working yet :(

Yes, that's because there are couple of sytax errors in the example
bindings. Mugunthan, could you repost these patches and at least copy
devicetree-discuss at lists.ozlabs.org and the ARM kernel mailing list? I
can't comment on the patches you sent to netdev at vger.kernel.org because
I'm not currently subscribed to that list.


Thanks,
Daniel



From linux at arm.linux.org.uk  Thu Aug  2 11:30:30 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 16:30:30 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802150123.GE9838@mudshark.cambridge.arm.com>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
Message-ID: <20120802153030.GV6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 04:01:23PM +0100, Will Deacon wrote:
> Hi Russell,
> 
> On Thu, Aug 02, 2012 at 02:04:11PM +0100, Russell King - ARM Linux wrote:
> > On Thu, Aug 02, 2012 at 01:23:26PM +0100, Will Deacon wrote:
> > > Recent upstream versions of binutils fail to assembler compressed/head.S
> > > when passed the -march=all option:
> > > 
> > > http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html
> > > 
> > > The recommended workaround from the tools folks is not to pass the
> > > option, and instead let the assembler deduce the CPU type based on the
> > > features used by the code.
> > 
> > That doesn't work for all binutils - binutils historically has had to be
> > told explicitly what architecture its building for and won't "deduce"
> > it from the code.
> 
> Damn. I thought there would be a reason why we passed the option in the
> first place.
> 
> > Maybe this needs to be a build-time test whether the assembler accepts it?
> 
> That could be tricky since gas still accepts the option, but fails later
> with:
> 
> arch/arm/boot/compressed/head.S: Assembler messages:
> arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2'
> 
> How about grabbing the march from KBUILD_AFLAGS instead (see below)?

It might just be easier to specify something like -march=armv4 or
something like that, and then use .arch armv6 where required.


From koen at dominion.thruhere.net  Thu Aug  2 11:37:51 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Thu, 2 Aug 2012 17:37:51 +0200
Subject: Current state of AM33xx patches
In-Reply-To: <501A9D1C.8080305@gmail.com>
References: <4FD5BA4C.9070706@gmail.com> <4FE326A8.8090807@gmail.com>
 <4FE8AB37.7030907@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
Message-ID: <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>


Op 2 aug. 2012, om 17:30 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:

> On 31.07.2012 21:29, Koen Kooi wrote:
> 
>> 2/3 of the way there:
>> 
>> http://patchwork.ozlabs.org/patch/174085/
>> http://patchwork.ozlabs.org/patch/174086/
>> 
>> I keep failing to create a .dts that doesn't upset the dtc, so I don't have it working yet :(
> 
> Yes, that's because there are couple of sytax errors in the example
> bindings.

Not only that, it's actually missing params and other params are wrong. See my non-constructive rant in the commit message: http://dominion.thruhere.net/koen/angstrom/beaglebone/0001-beaglebone-add-broken-cpsw-DT.patch

But I still can't get it working:

root at beaglebone:~# dmesg | grep -i cpsw
[   13.504425] net eth0: initializing cpsw version 1.12 (0)

root at beaglebone:~# dmesg | grep -i phy 
[    0.000000] Booting Linux on physical CPU 0
[    0.228496] nop_usb_xceiv phy.17: transceiver type USB2 PHY already exists
[   13.512056] libphy: PHY davinci_mdio-0:00 not found
[   13.517168] net eth0: phy davinci_mdio-0:00 not found on slave 0
[   13.523516] libphy: PHY davinci_mdio-0:01 not found
[   13.528675] net eth0: phy davinci_mdio-0:01 not found on slave 1

root at beaglebone:~# ifconfig -a | grep eth
eth0      Link encap:Ethernet  HWaddr 00:04:9F:01:1B:B8  

> Mugunthan, could you repost these patches and at least copy
> devicetree-discuss at lists.ozlabs.org and the ARM kernel mailing list? I
> can't comment on the patches you sent to netdev at vger.kernel.org because
> I'm not currently subscribed to that list.


Same here, I'm only on l-o, but I guess I'll need to subscribe dt-discuss in the near future :)

regards,

Koen

From will.deacon at arm.com  Thu Aug  2 11:51:41 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 Aug 2012 16:51:41 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802153030.GV6802@n2100.arm.linux.org.uk>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
 <20120802153030.GV6802@n2100.arm.linux.org.uk>
Message-ID: <20120802155140.GF9838@mudshark.cambridge.arm.com>

On Thu, Aug 02, 2012 at 04:30:30PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 02, 2012 at 04:01:23PM +0100, Will Deacon wrote:
> > On Thu, Aug 02, 2012 at 02:04:11PM +0100, Russell King - ARM Linux wrote:
> > > Maybe this needs to be a build-time test whether the assembler accepts it?
> > 
> > That could be tricky since gas still accepts the option, but fails later
> > with:
> > 
> > arch/arm/boot/compressed/head.S: Assembler messages:
> > arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> > arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> > arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2'
> > 
> > How about grabbing the march from KBUILD_AFLAGS instead (see below)?
> 
> It might just be easier to specify something like -march=armv4 or
> something like that, and then use .arch armv6 where required.

We could do that, but I worry that it will become very messy if/when people
start adding things like virtualisation instructions (hvc and co) to the
entry code. Using the same march flag for kernel and decompressor also keeps
everything consistent.

Will


From festevam at gmail.com  Thu Aug  2 11:52:27 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 2 Aug 2012 12:52:27 -0300
Subject: [PATCH 0/7] Add support for Freescale's mc34708 to mc13xxx driver
In-Reply-To: <1342087073-3892-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1342087073-3892-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CAOMZO5C0=eXYU8Vgnn0xGviXfLEjGgA0yn120NKpwL55m5rgbA@mail.gmail.com>

Hi Uwe,

On Thu, Jul 12, 2012 at 6:57 AM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> Hello,
>
> This series was tested on a Phytec pcm038 (mc13783 on spi) using
> traditional boot (i.e. not dt) and on a i.MX53 based machine (mc34708 on
> i2c) using dt boot.
>
> Philippe's patches are already in next, they are just included here for
> those who want to test the patches. The 'mfd/mc13xxx: drop modifying
> driver's id_table in probe' was already sent out yesterday and is
> included here because the last patch depends on it.

Would you have a git tree with all these patches applied so that I can
easily test it on a mx53loco board?

Thanks,

Fabio Estevam


From u.kleine-koenig at pengutronix.de  Thu Aug  2 11:56:25 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu,  2 Aug 2012 17:56:25 +0200
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
Message-ID: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>

From: Steffen Trumtrar <s.trumtrar at pengutronix.de>

This patch adds basic support for imx35-based devices to the kernel.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/dts/imx35.dtsi            |  246 +++++++++++++++++++++++++++++++
 arch/arm/configs/imx_v6_v7_defconfig    |    1 +
 arch/arm/mach-imx/Kconfig               |   13 ++
 arch/arm/mach-imx/Makefile              |    1 +
 arch/arm/mach-imx/imx35-dt.c            |  119 +++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 6 files changed, 382 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx35.dtsi
 create mode 100644 arch/arm/mach-imx/imx35-dt.c

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
new file mode 100644
index 0000000..d0c6456
--- /dev/null
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27.dtsi
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+	};
+
+	avic: avic-interrupt-controller at 68000000 {
+		compatible = "fsl,imx35-avic", "fsl,avic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x68000000 0x10000000>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ckil {
+			compatible = "fsl,imx-ckil", "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		osc {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "fsl,imx35", "arm,arm1136jfs";
+			reg = <0>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			bus-frequency = <0>;		// from bootloader
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&avic>;
+		ranges;
+
+		aips at 40000000 { /* AIPS1 */
+			compatible = "fsl,aips", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40000000 0x100000>;
+			ranges;
+
+			i2c1: i2c at 43f80000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f80000 0x4000>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 43f84000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f84000 0x4000>;
+				interrupts = <3>;
+				status = "disabled";
+			};
+
+			uart1: uart at 43f90000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x43f90000 0x4000>;
+				interrupts = <45>;
+				status = "disabled";
+			};
+
+			uart2: uart at 43f94000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x43f94000 0x4000>;
+				interrupts = <32>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 43f98000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f98000 0x4000>;
+				interrupts = <4>;
+				status = "disabled";
+			};
+			iomuxc at 43fac000 {
+				compatible = "fsl,imx35-iomuxc";
+				reg = <0x43fac000 0x4000>;
+
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <773 0x1c0 /* MX35_PAD_ATA_DATA12__I2C3_SCL */
+							777 0x1c0>; /* MX35_PAD_ATA_DATA13__I2C3_SDA */
+					};
+				};
+
+				can1 {
+					pinctrl_can1_1: can1grp-1 {
+						fsl,pins = <223 0x1c0 /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
+							228 0x1c0>; /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
+					};
+				};
+				can2 {
+					pinctrl_can2_1: can2grp-1 {
+						fsl,pins = <291 0x1c0 /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
+							298 0x1c0>; /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
+					};
+				};
+
+			};
+		};
+
+		spba at 50000000 {
+			compatible = "fsl,spba-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x50000000 0x100000>;
+			ranges;
+
+			uart3: uart at 5000c000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x5000c000 0x4000>;
+				interrupts = <18>;
+				status = "disabled";
+			};
+
+			fec: fec at 50038000 {
+				compatible = "fsl,imx35-fec", "fsl,imx27-fec";
+				reg = <0x50038000 0x4000>;
+				interrupts = <57>;
+				status = "disabled";
+			};
+		};
+
+		aips at 53f00000 { /* AIPS2 */
+			compatible = "fsl,aips", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x53f00000 0xffc0000>;
+			ranges;
+
+			gpio3: gpio at 0x53fa4000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fa4000 0x4000>;
+				interrupts = <56>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			esdhc1: esdhc at 53fb4000 {
+				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
+				reg = <0x53fb4000 0x4000>;
+				interrupts = <7>;
+				status = "disabled";
+			};
+
+			esdhc2: esdhc at 53fb8000 {
+				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
+				reg = <0x53fb8000 0x4000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			esdhc3: esdhc at 53fbc000 {
+				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
+				reg = <0x53fbc000 0x4000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			gpio1: gpio at 0x53fcc000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fcc000 0x4000>;
+				interrupts = <52>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			gpio2: gpio at 0x53fd0000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fd0000 0x4000>;
+				interrupts = <51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			wdog at 53fdc000 {
+				compatible = "fsl,imx35-wdt", "fsl,imx2-wdt";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <55>;
+				status = "disabled";
+			};
+
+			can at 53fe4000 {
+				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				reg = <0x53fe4000 0x1000>;
+				interrupts = <43>;
+				status = "disabled";
+			};
+			can at 53fe8000 {
+				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				reg = <0x53fe8000 0x1000>;
+				interrupts = <44>;
+				status = "disabled";
+			};
+		};
+		nand at bb000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			compatible = "fsl,imx35-nand", "fsl,imx25-nand";
+			reg = <0xbb000000 0x2000>;
+			interrupts = <33>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b1d3675..9389ab6 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -26,6 +26,7 @@ CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
+CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eff4db5..95f9d6a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -644,6 +644,19 @@ config MACH_VPR200
 	  Include support for VPR200 platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_IMX35_DT
+	bool "Support i.MX35 platforms from device tree"
+	select SOC_IMX35
+	select USE_OF
+	select HAVE_CAN_FLEXCAN if CAN
+	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select PINCTRL
+	help
+	  Include support for Freescale i.MX35 based platforms
+	  using the device tree for discovery
+
 comment "i.MX5 platforms:"
 
 config MACH_MX50_RDP
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ff29421..97d01b5 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
 
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
new file mode 100644
index 0000000..8b9cc84
--- /dev/null
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27-dt.c
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx35.h>
+
+static const struct of_dev_auxdata imx35_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-fec", MX35_FEC_BASE_ADDR, "imx27-fec.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-wdt", MX35_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx35.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx35.1", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx35.2", NULL),
+	OF_DEV_AUXDATA("fsl,imx35-nand", MX35_NFC_BASE_ADDR, "mxc_nand.0", NULL),
+	{ /* sentinel */ }
+};
+
+static int __init imx35_avic_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
+	return 0;
+}
+
+static int __init imx35_gpio_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
+
+	gpio_irq_base -= 32;
+	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
+				NULL);
+
+	return 0;
+}
+
+static const struct of_device_id imx35_irq_match[] __initconst = {
+	{ .compatible = "fsl,imx35-avic", .data = imx35_avic_add_irq_domain, },
+	{ .compatible = "fsl,imx35-gpio", .data = imx35_gpio_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static const struct of_device_id imx35_of_mixed_devices_match[] __initconst = {
+	{ /* END OF LIST */ }
+};
+
+static void __init of_mixed_device_hook(void)
+{
+	struct device_node *np;
+	const struct of_device_id *of_id;
+
+	np = of_find_matching_node(NULL, imx35_of_mixed_devices_match);
+	if (np) {
+		void (*func)(void);
+
+		of_id = of_match_node(imx35_of_mixed_devices_match, np);
+		func = of_id->data;
+		func();
+	}
+}
+
+static void __init imx35_dt_init(void)
+{
+	of_irq_init(imx35_irq_match);
+
+	/* Some mx35 have problems when the cache is not initialized
+	 * FIXME: ultimatly this belongs in the oftree definition
+	 */
+	imx3_init_l2x0();
+	pinctrl_provide_dummies();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     imx35_auxdata_lookup, NULL);
+
+	of_mixed_device_hook();
+}
+
+static void __init imx35_timer_init(void)
+{
+	mx35_clocks_init();
+}
+
+static struct sys_timer imx35_timer = {
+	.init = imx35_timer_init,
+};
+
+static const char *imx35_dt_board_compat[] __initdata = {
+	"fsl,imx35",
+	NULL
+};
+
+DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
+	.map_io		= mx35_map_io,
+	.init_early	= imx35_init_early,
+	.init_irq	= mx35_init_irq,
+	.handle_irq	= imx35_handle_irq,
+	.timer		= &imx35_timer,
+	.init_machine	= imx35_dt_init,
+	.dt_compat	= imx35_dt_board_compat,
+	.restart	= mxc_restart,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1..643b0aa 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -50,6 +50,7 @@ extern void imx25_soc_init(void);
 extern void imx27_soc_init(void);
 extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
+extern void imx3_init_l2x0(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx53_soc_init(void);
@@ -67,6 +68,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
 extern int mx27_clocks_init_dt(void);
+extern int mx35_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Thu Aug  2 11:56:26 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu,  2 Aug 2012 17:56:26 +0200
Subject: [PATCH 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1343922986-32469-2-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/dts/phytec-pcm043.dtsi |   49 ++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 arch/arm/boot/dts/phytec-pcm043.dtsi

diff --git a/arch/arm/boot/dts/phytec-pcm043.dtsi b/arch/arm/boot/dts/phytec-pcm043.dtsi
new file mode 100644
index 0000000..420627c
--- /dev/null
+++ b/arch/arm/boot/dts/phytec-pcm043.dtsi
@@ -0,0 +1,49 @@
+/include/ "imx35.dtsi"
+
+/ {
+	soc {
+		aips at 40000000 { /* AIPS1 */
+			i2c at 43f80000 {
+				status = "okay";
+
+				tempsens at 4a {
+					compatible = "maxim,ds75";
+					reg = <0x4a>;
+				};
+				rtc8564 at 51 {
+					compatible = "nxp,pcf8563";
+					reg = <0x51>;
+				};
+				at24 at 52 {
+					compatible = "at,24c32";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+			};
+			uart at 43f90000 {
+				status = "okay";
+			};
+			uart at 43f94000 {
+				status = "okay";
+			};
+		};
+		spba at 50000000 {
+			uart at 5000c000 {
+				status = "okay";
+			};
+			fec at 50038000 {
+				status = "okay";
+			};
+		};
+
+		nor at a0000000 {
+			compatible = "cfi-flash";
+			reg = <0xa0000000 0x2000000>;
+			bank-width = <2>;
+		};
+
+		nand at bb000000 {
+			status = "okay";
+		};
+	};
+};
-- 
1.7.10.4



From broonie at opensource.wolfsonmicro.com  Thu Aug  2 12:00:17 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 2 Aug 2012 17:00:17 +0100
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208021658.38237.marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
 <20120801203106.GW4483@opensource.wolfsonmicro.com>
 <201208021658.38237.marex@denx.de>
Message-ID: <20120802160016.GA4537@opensource.wolfsonmicro.com>

On Thu, Aug 02, 2012 at 04:58:38PM +0200, Marek Vasut wrote:

> > It'd be nice to only keep the clocks enabled while doing transfers but
> > again totally non-essential.

> Hm, this is spread across mxs. Shawn, is there any plan for PM implementation 
> for MXS ?

Take a look at s3c64xx - I did something with runtime PM for this, it's
something that can reasonably be implemented in drivers and as far as I
can tell most framework implementations end up using runtime PM anyway.


From marex at denx.de  Thu Aug  2 12:03:25 2012
From: marex at denx.de (Marek Vasut)
Date: Thu, 2 Aug 2012 18:03:25 +0200
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120802160016.GA4537@opensource.wolfsonmicro.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <201208021658.38237.marex@denx.de>
 <20120802160016.GA4537@opensource.wolfsonmicro.com>
Message-ID: <201208021803.25460.marex@denx.de>

Dear Mark Brown,

> On Thu, Aug 02, 2012 at 04:58:38PM +0200, Marek Vasut wrote:
> > > It'd be nice to only keep the clocks enabled while doing transfers but
> > > again totally non-essential.
> > 
> > Hm, this is spread across mxs. Shawn, is there any plan for PM
> > implementation for MXS ?
> 
> Take a look at s3c64xx - I did something with runtime PM for this, it's
> something that can reasonably be implemented in drivers and as far as I
> can tell most framework implementations end up using runtime PM anyway.

We don't even support runtime pm on mxs yet IIRC

Best regards,
Marek Vasut


From jdzheng at broadcom.com  Thu Aug  2 13:03:45 2012
From: jdzheng at broadcom.com (Jiandong Zheng)
Date: Thu, 2 Aug 2012 10:03:45 -0700
Subject: [PATCH] mtd: use %*ph[CN] to dump small buffers
In-Reply-To: <1343912807-29355-1-git-send-email-andriy.shevchenko@linux.intel.com>
References: <1343912807-29355-1-git-send-email-andriy.shevchenko@linux.intel.com>
Message-ID: <501AB2F1.6060101@broadcom.com>

On 8/2/2012 6:06 AM, Andy Shevchenko wrote:
> There is new format specified that helps to dump small buffers. It makes the
> code simplier and nicer.
>
> Signed-off-by: Andy Shevchenko<andriy.shevchenko at linux.intel.com>
> Cc: David Woodhouse<dwmw2 at infradead.org>
> Cc: Jiandong Zheng<jdzheng at broadcom.com>
> Cc: Ben Dooks<ben-linux at fluff.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-samsung-soc at vger.kernel.org
> ---

>   drivers/mtd/nand/bcm_umi_bch.c    |   17 ++++-------------
>
Acked-by: Jiandong Zheng <jdzheng at broadcom.com>



From olof at lixom.net  Thu Aug  2 13:11:49 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:11:49 -0700
Subject: [GIT PULL][for 3.6] pull request from board branch in pxa git tree
In-Reply-To: <CAN1soZxxZMy7iVx=r1XwaxfXVLAXBGd03t5rv7PM4A7dQm_HFA@mail.gmail.com>
References: <CAN1soZxxZMy7iVx=r1XwaxfXVLAXBGd03t5rv7PM4A7dQm_HFA@mail.gmail.com>
Message-ID: <20120802171149.GA26795@quad.lixom.net>

Hi,

On Tue, Jul 31, 2012 at 09:39:55AM +0800, Haojian Zhuang wrote:
> Hi Arnd & Olof,
> 
> Please help to pull these from board branch of pxa git tree for v3.6
> 
> Regards
> Haojian
> 
> The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:
> 
>   Linux 3.5 (2012-07-21 13:58:29 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/hzhuang1/linux.git board
> 

I'm not sure what to think of this branch. It contains one bugfix
(missing include) and one feature.

All features for a merge window should be in our tree by the time the
merge window opens.

I've pulled it in this time, but please don't send features this late
again -- queue them up for the next merge window instead.


-Olof



From olof at lixom.net  Thu Aug  2 13:12:18 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:12:18 -0700
Subject: [PATCH] ARM: PRIMA2: delete redundant codes to restore LATCHED
 when timer resumes
In-Reply-To: <1343626170-27831-1-git-send-email-Barry.Song@csr.com>
References: <1343626170-27831-1-git-send-email-Barry.Song@csr.com>
Message-ID: <20120802171218.GB26795@quad.lixom.net>

On Mon, Jul 30, 2012 at 01:29:30PM +0800, Barry Song wrote:
> From: Barry Song <Baohua.Song at csr.com>
> 
> The only way to write LATCHED registers to write LATCH_BIT to LATCH register,
> that will latch COUNTER into LATCHED.e.g.
> writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base +
> 	SIRFSOC_TIMER_LATCH);
> 
> Writing values to LATCHED registers directly is useless at all.
> 
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

Based on off-list email, applied to fixes.


Thanks,

-Olof


From olof at lixom.net  Thu Aug  2 13:13:09 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:13:09 -0700
Subject: [GIT PULL] [for 3.6] pull request from dt-pxa branch in pxa git
 tree
In-Reply-To: <CAN1soZxFsnhEnyn3=2PtCovfpWeD6Kb=z5eEGAjdEO+9qUTQfQ@mail.gmail.com>
References: <CAN1soZxFsnhEnyn3=2PtCovfpWeD6Kb=z5eEGAjdEO+9qUTQfQ@mail.gmail.com>
Message-ID: <20120802171309.GC26795@quad.lixom.net>

On Tue, Jul 31, 2012 at 09:42:38AM +0800, Haojian Zhuang wrote:
> Hi Arnd & Olof,
> 
> Please help to pull changes from dt-pxa branch in pxa git tree.

Hi,

This is 3.7 material by now. Please send a new pull request once -rc1
is out and we'll stage it for the next merge window.


Regards,

-Olof

> 
> Regards
> Haojian
> 
> The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:
> 
>   Linux 3.5 (2012-07-21 13:58:29 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/hzhuang1/linux.git dt-pxa
> 
> for you to fetch changes up to 98d0e7160c9ebd0caf61aac13fb5b63c53de9a59:
> 
>   ARM: dts: add pinctrl in PXA DT files (2012-07-31 09:24:53 +0800)
> 
> ----------------------------------------------------------------
> Daniel Mack (9):
>       RTC: add DT bindings to pxa-rtc
>       MMC: pxa-mci: add DT bindings
>       MTD: pxa3xx-nand: add devicetree bindings
>       GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
>       GPIO: gpio-pxa: fix devicetree functions
>       ARM: pxa: add devicetree code for irq handling
>       ARM: pxa3xx: skip default device initialization when booting via DT
>       ARM: pxa3xx: add generic DT machine code
>       ARM: pxa: add .dtsi files
> 
> Haojian Zhuang (6):
>       pinctrl: append new pins and groups in pxa910
>       pinctrl: add pinconf support in pxa3xx
>       pinctrl: support dt in pxa series
>       pinctrl: append new groups of mmp2
>       ARM: mmp: select pinctrl for boards with DT
>       ARM: dts: add pinctrl in PXA DT files
> 
>  Documentation/devicetree/bindings/mmc/pxa-mmc.txt  |   25 ++
>  .../devicetree/bindings/mtd/pxa3xx-nand.txt        |   31 ++
>  .../bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt       |   35 +++
>  Documentation/devicetree/bindings/rtc/pxa-rtc.txt  |   14 +
>  arch/arm/boot/dts/mmp2-brownstone.dts              |   51 +++
>  arch/arm/boot/dts/mmp2.dtsi                        |    5 +
>  arch/arm/boot/dts/pxa168.dtsi                      |    5 +
>  arch/arm/boot/dts/pxa27x.dtsi                      |   14 +
>  arch/arm/boot/dts/pxa2xx.dtsi                      |  132 ++++++++
>  arch/arm/boot/dts/pxa3xx.dtsi                      |   32 ++
>  arch/arm/boot/dts/pxa910-dkb.dts                   |   47 +++
>  arch/arm/boot/dts/pxa910.dtsi                      |    5 +
>  arch/arm/mach-mmp/Kconfig                          |    2 +
>  arch/arm/mach-pxa/Kconfig                          |   12 +
>  arch/arm/mach-pxa/Makefile                         |    3 +
>  arch/arm/mach-pxa/irq.c                            |  131 ++++++--
>  arch/arm/mach-pxa/pxa-dt.c                         |   63 ++++
>  arch/arm/mach-pxa/pxa3xx.c                         |   21 +-
>  drivers/gpio/gpio-pxa.c                            |   96 +++---
>  drivers/mmc/host/pxamci.c                          |   52 ++++
>  drivers/mtd/nand/pxa3xx_nand.c                     |   85 ++++-
>  drivers/pinctrl/pinctrl-mmp2.c                     |   18 +-
>  drivers/pinctrl/pinctrl-pxa168.c                   |   10 +-
>  drivers/pinctrl/pinctrl-pxa3xx.c                   |  325 ++++++++++++++++++++
>  drivers/pinctrl/pinctrl-pxa3xx.h                   |   17 +
>  drivers/pinctrl/pinctrl-pxa910.c                   |   16 +-
>  drivers/rtc/rtc-pxa.c                              |   11 +
>  27 files changed, 1160 insertions(+), 98 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/pxa-mmc.txt
>  create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
>  create mode 100644
> Documentation/devicetree/bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
>  create mode 100644 arch/arm/boot/dts/pxa27x.dtsi
>  create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
>  create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
>  create mode 100644 arch/arm/mach-pxa/pxa-dt.c


From olof at lixom.net  Thu Aug  2 13:13:28 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:13:28 -0700
Subject: [PATCH] arm: mvebu: fix typo in .dtsi comment for Armada XP SoCs
In-Reply-To: <1343920427-26128-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343920427-26128-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120802171328.GD26795@quad.lixom.net>

On Thu, Aug 02, 2012 at 05:13:47PM +0200, Thomas Petazzoni wrote:
> The comment was wrongly referring to Armada 370 while the file is
> related to Armada XP.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Applied to fixes.


Thanks,

-Olof


From olof at lixom.net  Thu Aug  2 13:17:04 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:17:04 -0700
Subject: [GIT PULL][for 3.6] pull request from board branch in pxa git tree
In-Reply-To: <20120802171149.GA26795@quad.lixom.net>
References: <CAN1soZxxZMy7iVx=r1XwaxfXVLAXBGd03t5rv7PM4A7dQm_HFA@mail.gmail.com>
 <20120802171149.GA26795@quad.lixom.net>
Message-ID: <CAOesGMhmCveAjGnbMic7HgW4CX_L4g+2tmmOP3UPEF=NwtfxXA@mail.gmail.com>

On Thu, Aug 2, 2012 at 10:11 AM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> On Tue, Jul 31, 2012 at 09:39:55AM +0800, Haojian Zhuang wrote:
>> Hi Arnd & Olof,
>>
>> Please help to pull these from board branch of pxa git tree for v3.6
>>
>> Regards
>> Haojian
>>
>> The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:
>>
>>   Linux 3.5 (2012-07-21 13:58:29 -0700)
>>
>> are available in the git repository at:
>>
>>   git://github.com/hzhuang1/linux.git board
>>
>
> I'm not sure what to think of this branch. It contains one bugfix
> (missing include) and one feature.
>
> All features for a merge window should be in our tree by the time the
> merge window opens.
>
> I've pulled it in this time, but please don't send features this late
> again -- queue them up for the next merge window instead.


Actually, on second throught (since I also noticed the second pull
request after sending this reply), I cherry-picked the IRQ fix out of
the branch instead. Please include the board platform_device change in
your branches for 3.7 instead.


-Olof


From zonque at gmail.com  Thu Aug  2 13:19:16 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 19:19:16 +0200
Subject: Current state of AM33xx patches
In-Reply-To: <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
References: <4FD5BA4C.9070706@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
 <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
Message-ID: <501AB694.5090304@gmail.com>

On 02.08.2012 17:37, Koen Kooi wrote:
> Not only that, it's actually missing params and other params are
> wrong. See my non-constructive rant in the commit message:
> http://dominion.thruhere.net/koen/angstrom/beaglebone/0001-beaglebone-add-broken-cpsw-DT.patch
>
>  But I still can't get it working:
> 
> root at beaglebone:~# dmesg | grep -i cpsw [   13.504425] net eth0:
> initializing cpsw version 1.12 (0)
> 
> root at beaglebone:~# dmesg | grep -i phy [    0.000000] Booting Linux
> on physical CPU 0 [    0.228496] nop_usb_xceiv phy.17: transceiver
> type USB2 PHY already exists [   13.512056] libphy: PHY
> davinci_mdio-0:00 not found [   13.517168] net eth0: phy
> davinci_mdio-0:00 not found on slave 0 [   13.523516] libphy: PHY
> davinci_mdio-0:01 not found [   13.528675] net eth0: phy
> davinci_mdio-0:01 not found on slave 1

That is because the davinci_mdio driver is not yet probed from DT. I
hooked up bindings to that driver and also had to augment the clock
definitions, but that's giving me an "external abort on non-linefetch"
at boot time. Most probably because there's something missing in the
clock setup. Not sure whether I should debug that any further or if
anyone has patches for that.

Mugunthan, how did you test your DT bindings? Could you push your entire
tree somewhere maybe for others to have a look at it? I have no problem
helping you in any way, I just want to know where we currently are.


Thanks for you work,
Daniel


From olof at lixom.net  Thu Aug  2 13:44:46 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:44:46 -0700
Subject: [GIT PULL 0/3] ARM: late-arrived arm-soc branches for 3.6
Message-ID: <CAOesGMgJjJd=69AgNZFSOWvEqjRO3=SspY5rUQxwVnWr5fe2uQ@mail.gmail.com>

Hi Linus,

The following 3 pull requests (well, the latter two) are for branches
that showed up late for this merge window but we staged anwyay, on a
best-effort basis.

2/3 is for grouped cpuidle updates on OMAP which missed 3.5 due to the
infrastructure not going in. Since it's well-contained to their
platform, and they are eager to see it go in, I picked it up and let
it sit in -next for about a week and I think it's good to go by now.

3/3 is device-tree updates for Marvell Orion. The maintainers and
developers on these platforms are mostly hobbyists so we're trying to
help them get used to the workflow, etc, and in this case it meant
they needed a little while to get the branches sorted out. The code is
reasonably well-contained and again has sat in linux-next for almost a
week.


That being said, we are flexing the rules a bit here and if you're
less than excited to pick these up at this time, let us know and we
can hold them until the 3.7 window instead.

Please do merge the first branch of fixes though.


Thanks!

-Olof


From olof at lixom.net  Thu Aug  2 13:45:11 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:45:11 -0700
Subject: [GIT PULL 1/3] ARM: SoC fixes
Message-ID: <CAOesGMiBPVtYwMN2o-e_vBC_XOdgjuDfrBs-ftAByvfdCsrB3w@mail.gmail.com>

A few fixes for merge window fallout, and a bugfix for timer resume
on PRIMA2.

----------------------------------------------------------------

The following changes since commit 1a9b4993b70fb1884716902774dc9025b457760d:

  Merge branch 'upstream' of
git://git.linux-mips.org/pub/scm/ralf/upstream-linus

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/fixes-for-linus

for you to fetch changes up to bac6f61550043195ee59e9cef0db67af23baf11e:

  ARM: mmp: add missing irqs.h

----------------------------------------------------------------

Barry Song (1):
      ARM: PRIMA2: delete redundant codes to restore LATCHED when timer resumes

Fabio Estevam (1):
      ARM: mxc: Include missing irqs.h header

Haojian Zhuang (1):
      ARM: mmp: add missing irqs.h

Thomas Petazzoni (1):
      arm: mvebu: fix typo in .dtsi comment for Armada XP SoCs


 arch/arm/boot/dts/armada-xp.dtsi | 2 +-
 arch/arm/mach-mmp/gplugd.c       | 1 +
 arch/arm/mach-prima2/timer.c     | 6 +++---
 arch/arm/plat-mxc/tzic.c         | 1 +
 4 files changed, 6 insertions(+), 4 deletions(-)


From olof at lixom.net  Thu Aug  2 13:45:48 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:45:48 -0700
Subject: [GIT PULL 2/3] ARM: arm-soc: cpuidle enablement for OMAP
Message-ID: <CAOesGMjpnTU=1PBT2PNJOVjNbFhGrwFB0ZskUqRs0TGdHbJ41A@mail.gmail.com>

Coupled cpuidle was meant to merge for 3.5 through Len Brown's tree, but
didn't go in because the pull request ended up rejected. So it just got
merged, and we got this staged branch that enables the coupled cpuidle
code on OMAP.

With a stable git workflow from the other maintainer we could have staged
this earlier, but that wasn't the case so we have had to merge it late.

The alternative is to hold it off until 3.7 but given that the code is
well-isolated to OMAP and they are eager to see it go in, I didn't push
back hard in that direction.

----------------------------------------------------------------

The following changes since commit 516b7ab0b42b6dfe765f04a397e499d519e93825:

  Merge branch 'fixes' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/pm2

for you to fetch changes up to 5c62202968d4aaf3bd50e19c421d66aec2e508e0:

  Merge branch 'for_3.6/pm/coupled-cpuidle' of
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm
into late2/pm

----------------------------------------------------------------

Kevin Hilman (1):
      ARM: OMAP4: CPUidle: add synchronization for coupled idle states

Olof Johansson (1):
      Merge branch 'for_3.6/pm/coupled-cpuidle' of
git://git.kernel.org/.../khilman/linux-omap-pm into late2/pm

Santosh Shilimkar (3):
      ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
      ARM: OMAP4: CPUidle: Use coupled cpuidle states to implement SMP cpuidle.
      ARM: OMAP4: CPUidle: Open broadcast clock-event device.


 arch/arm/mach-omap2/Kconfig       |   1 +
 arch/arm/mach-omap2/cpuidle44xx.c | 145 ++++++++++++++++++++++-----------
 arch/arm/mach-omap2/timer.c       |   4 +-
 3 files changed, 103 insertions(+), 47 deletions(-)


From olof at lixom.net  Thu Aug  2 13:46:31 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 2 Aug 2012 10:46:31 -0700
Subject: [GIT PULL 3/3] ARM: arm-soc Marvell Orion device-tree updates
Message-ID: <CAOesGMjc0PBLEf_Ar=z9TX4bjHEMOVeshxQSmYpp9P=3G6_D_Q@mail.gmail.com>

This branch contains a set of device-tree conversions for Marvell Orion
platforms that were staged early but took a few tries to get the branch
into a format where it was suitable for us to pick up.

Given that most people working on these platforms are hobbyists with
limited time, we were a bit more flexible with merging it even though
it came in late.

----------------------------------------------------------------

The following changes since commit 4695ce021de2a3abdd593155bee291496e735cbf:

  Merge tag 'pm2' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/dt2

for you to fetch changes up to 15a1e1bafe2c924db6d370ad892d7da6c7d83598:

  Merge branch 'marvell/dt' into late2/dt

----------------------------------------------------------------

Andrew Lunn (16):
      Merge tag 'spi-3.6' into v3.5-rc7-dt-v3
      Merge branch 'v3.5-rc7-fixes' into v3.5-rc7-dt-v3
      ARM: Orion: DT support for IRQ and GPIO Controllers
      ARM: Orion: Add arch support needed for I2C via DT.
      ARM: Orion: DTify the watchdog timer.
      ATA: sata_mv: Add device tree support
      ARM: Kirkwood: Add basic device tree support for QNAP TS219.
      ARM: Kirkwood: Use DT to configure SATA device.
      ARM: Kirkwood: Describe DNS325 temperature sensor in DT.
      ARM: Kirkwood: Describe IB62x0 gpio-keys in DT.
      ARM: Kirkwood: Describe IB62x0 LEDs in DT.
      ARM: Kirkwood: Describe iConnects temperature sensor in DT.
      ARM: Kirkwood: Describe iConnects LEDs in DT.
      ARM: Kirkwood: Describe Dreamplug LEDs in DT.
      ARM: Kirkwood: Describe GoFlex Net LEDs and SATA in DT.
      ARM: Kirkwood: Replace mrvl with marvell

Jamie Lentin (3):
      ARM: Kirkwood: Replace DNS-320/DNS-325 leds with dt bindings
      ARM: Kirkwood: Move common portions into a kirkwood-dnskw.dtsi
      ARM: Kirkwood: Describe DNS32? gpio-keys in DT.

Josh Coombs (1):
      ARM: Kirkwood: Initial DTS support for Kirkwood GoFlex Net

Michael Walle (3):
      ARM: kirkwood: use devicetree for orion-spi
      ARM: kirkwood: Add LS-XHL and LS-CHLv2 support
      ARM: kirkwood: use devicetree for SPI on dreamplug

Olof Johansson (1):
      Merge branch 'marvell/dt' into late2/dt


 .../devicetree/bindings/arm/mrvl/intc.txt       |  20 +++
 .../devicetree/bindings/ata/marvell.txt         |  16 ++
 .../devicetree/bindings/gpio/mrvl-gpio.txt      |  23 +++

 .../devicetree/bindings/watchdog/marvel.txt     |  14 ++
 arch/arm/Kconfig                                |   1 +
 arch/arm/boot/dts/kirkwood-dns320.dts           |  62 +++----
 arch/arm/boot/dts/kirkwood-dns325.dts           |  68 ++++----
 arch/arm/boot/dts/kirkwood-dnskw.dtsi           |  69 ++++++++
 arch/arm/boot/dts/kirkwood-dreamplug.dts        |  50 ++++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts        |  99 +++++++++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts           |  38 +++++
 arch/arm/boot/dts/kirkwood-iconnect.dts         |  42 +++++
 arch/arm/boot/dts/kirkwood-lschlv2.dts          |  20 +++
 arch/arm/boot/dts/kirkwood-lsxhl.dts            |  20 +++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi            |  95 +++++++++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts       |  21 +++
 arch/arm/boot/dts/kirkwood-ts219-6282.dts       |  21 +++
 arch/arm/boot/dts/kirkwood-ts219.dtsi           |  78 +++++++++
 arch/arm/boot/dts/kirkwood.dtsi                 |  60 +++++++
 arch/arm/mach-dove/irq.c                        |  58 +++----
 arch/arm/mach-kirkwood/Kconfig                  |  29 ++++
 arch/arm/mach-kirkwood/Makefile                 |   3 +
 arch/arm/mach-kirkwood/Makefile.boot            |   4 +
 arch/arm/mach-kirkwood/board-dnskw.c            | 143 ----------------
 arch/arm/mach-kirkwood/board-dreamplug.c        |  80 ---------
 arch/arm/mach-kirkwood/board-dt.c               |  29 +++-
 arch/arm/mach-kirkwood/board-goflexnet.c        |  71 ++++++++
 arch/arm/mach-kirkwood/board-ib62x0.c           |  72 --------
 arch/arm/mach-kirkwood/board-iconnect.c         |  56 -------
 arch/arm/mach-kirkwood/board-lsxl.c             | 135 +++++++++++++++
 arch/arm/mach-kirkwood/board-ts219.c            |  82 +++++++++
 arch/arm/mach-kirkwood/common.c                 |   2 +
 arch/arm/mach-kirkwood/common.h                 |  17 ++
 arch/arm/mach-kirkwood/irq.c                    |  38 ++---
 arch/arm/mach-mv78xx0/irq.c                     |  22 +--
 arch/arm/mach-orion5x/irq.c                     |  22 +--
 arch/arm/plat-orion/common.c                    |   1 +
 arch/arm/plat-orion/gpio.c                      | 166 ++++++++++++++-----
 arch/arm/plat-orion/include/plat/gpio.h         |  16 +-
 arch/arm/plat-orion/include/plat/irq.h          |   3 +-
 arch/arm/plat-orion/irq.c                       |  40 +++++
 drivers/ata/sata_mv.c                           |  42 +++--
 drivers/watchdog/orion_wdt.c                    |   8 +
 43 files changed, 1387 insertions(+), 569 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ata/marvell.txt
 create mode 100644 Documentation/devicetree/bindings/watchdog/marvel.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dnskw.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-goflexnet.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-lschlv2.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-lsxhl.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-lsxl.dtsi
 create mode 100644 arch/arm/boot/dts/kirkwood-ts219-6281.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-ts219-6282.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-ts219.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-goflexnet.c
 create mode 100644 arch/arm/mach-kirkwood/board-lsxl.c
 create mode 100644 arch/arm/mach-kirkwood/board-ts219.c


From broonie at opensource.wolfsonmicro.com  Thu Aug  2 13:56:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 2 Aug 2012 18:56:04 +0100
Subject: [alsa-devel] [PATCH 1/6] ASoC: dapm: If one widget fails, do not
 force all subsequent widgets to fail too
In-Reply-To: <20120802074517.GA19231@gmail.com>
References: <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
 <20120801160824.GB11892@opensource.wolfsonmicro.com>
 <20120801194134.GA4103@sirena.org.uk>
 <20120802074517.GA19231@gmail.com>
Message-ID: <20120802175604.GF4537@opensource.wolfsonmicro.com>

On Thu, Aug 02, 2012 at 08:45:18AM +0100, Lee Jones wrote:

> Over time, the requests for Maintainers have Snowballed (pun intended). My 
> task now seems to be enabling drivers for Device Tree _and_ fix all 
> associated driver bugs, including any requested restructuring and API

One thing to bear in mind with device tree is that it's all about
defining an ABI - it's supposed to be stable and OS agnostic so it puts
a lot of pressure on to really address quality problems that become
visible in the bindings.  This stuff is much less critical with platform
data, it's relatively easy to change.

> adoption. What you fail to notice is that I am only one person, and hopping
> all over the code-base trying to do everyone's bidding is no mean feat. In

It's fairly obvious that it's only you, or at least only you posting
stuff (I know sometimes there are bigger teams behind people) - the
pressure you're under to get something in is very clear.  A big part of
what I'm saying here is that it would be really helpful if could you
slow down a bit, discuss problems more and avoid cutting corners so
much.  This is likely to save you time overall, you'll have a much
higher success rate and you'll get much better feedback if it's clear
what's going on and that there's an interest in understanding the
issues.

If you need to focus on device tree enablement and there are underlying
problems in the subsystems you're looking at perhaps you need to push
back on whoever's asking you to do the work and say you need the domain
experts to pitch in and help you out.

> reality I am no more obliged to fix driver bugs than you are. In fact as
> the Maintainer of some of these subsystems, perhaps you could even help out
> a bit?

You're not telling us about the problems you see so it's very difficult
for anyone to help you.

For example with this patch the only information you've sent is the
patch and the fact that you're seeing the error you're ignoring going
off on the system you're working with (which I had to ask to find out
about...).  You've not shown the error message or provided any other
hint which would help anyone understand why the error might be occuring
and what a good solution to the problem is.  Ola's guess seems very
likely but nobody's got enough information to confirm that unless
there's been some off-list ST/Linaro communication.

Obviously with the stuff that's device specific you also have to contend
with the fact that you're working on hardware which just isn't all that
widely available and quite possibly has closed datasheets.

> We are all trying to do good things here. Please try not to be too over-
> critical. We all know Mainlining is a good thing. Perhaps less people
> would be so frightened of it, thus more people would do it if the reviews
> weren't such a ball-ache ( for want of a better expression :) ).

This is a two way thing - one of the tools that maintainers have to try
to drive up the quality of the code is to push back on poor quality
submissions and devote less bandwith to sources of those submissions.

It is true that there's a bunch of people who seem to view review as
being just an annoying obstacle to be dealt with with the minimum
possible effort but in practice all that does is make things more
painful for everyone, they do tend to be more noticable because
"applied, thanks" doesn't make for a big thread.


From omar.luna at linaro.org  Thu Aug  2 13:56:37 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Thu, 2 Aug 2012 12:56:37 -0500
Subject: [PATCH 3/3] ARM: OMAP: omap_device: expose hwmod assert/deassert
 to omap devices
In-Reply-To: <alpine.DEB.2.00.1208020141140.4177@utopia.booyaka.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-4-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020141140.4177@utopia.booyaka.com>
Message-ID: <CALLhW=7JL64qaXKSTFsyR8sXPe-PSMZp=d2Rrkno_peSYGyvEg@mail.gmail.com>

On 2 August 2012 02:43, Paul Walmsley <paul at pwsan.com> wrote:
>> This APIs are meant to be an interface to hwmod assert/deassert
>> function, omap devices can call them through their platform data
>> to control their reset lines, they are expected to know the name
>> of the reset line they are trying to control.
>>
>> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
>
> This one has been queued for 3.7 with a few changes. Some more detail was
> added to the function documentationrovement.  Also the multiple
> assignments were removed per Documentation/CodingStyle chapter 1:
>
> "Don't put multiple assignments on a single line either."
>
> Please let me know if you have any comments.

Agree.

Thanks,

Omar


From linux at arm.linux.org.uk  Thu Aug  2 14:18:10 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 19:18:10 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802155140.GF9838@mudshark.cambridge.arm.com>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
 <20120802153030.GV6802@n2100.arm.linux.org.uk>
 <20120802155140.GF9838@mudshark.cambridge.arm.com>
Message-ID: <20120802181810.GW6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 04:51:41PM +0100, Will Deacon wrote:
> On Thu, Aug 02, 2012 at 04:30:30PM +0100, Russell King - ARM Linux wrote:
> > On Thu, Aug 02, 2012 at 04:01:23PM +0100, Will Deacon wrote:
> > > On Thu, Aug 02, 2012 at 02:04:11PM +0100, Russell King - ARM Linux wrote:
> > > > Maybe this needs to be a build-time test whether the assembler accepts it?
> > > 
> > > That could be tricky since gas still accepts the option, but fails later
> > > with:
> > > 
> > > arch/arm/boot/compressed/head.S: Assembler messages:
> > > arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> > > arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr'
> > > arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2'
> > > 
> > > How about grabbing the march from KBUILD_AFLAGS instead (see below)?
> > 
> > It might just be easier to specify something like -march=armv4 or
> > something like that, and then use .arch armv6 where required.
> 
> We could do that, but I worry that it will become very messy if/when people
> start adding things like virtualisation instructions (hvc and co) to the
> entry code. Using the same march flag for kernel and decompressor also keeps
> everything consistent.

But you're missing a fundamental point: the decompressor is not designed
to be built like that, it is designed to be built in such a way that it
works unmodified on any CPU type we have to date, whether you're building
a kernel for ARMv4 or ARMv7.

So, the code sequences which are architecture specific are only executed
after we've checked the ID registers to determine what we should be doing
for a particular CPU.

Hence, even if you're building for ARMv4, the decompressor will _still_
contain all the support code for ARMv7 - and the assembler better accept
those instructions too.

The alternative is we scatter various places with lots of yucky ifdefs,
and it won't be pretty because quite a number of CPUs share the same code
(which leads to long #if defined(CPU_A) || defined(CPU_B) etc).


From swarren at wwwdotorg.org  Thu Aug  2 14:36:33 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu,  2 Aug 2012 12:36:33 -0600
Subject: [PATCH] ARM: dt: tegra: paz00: add regulators
Message-ID: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this.

Three data sources were used for the data encoded here:
* The HW defaults, as extracted from real HW.
* The schematic, which specifies a voltage for each rail in the signal
  names.
* The AC100 kernel used by the Ubuntu port:

  repo git://gitorious.org/~marvin24/ac100/marvin24s-kernel.git
  branch chromeos-ac100-3.0
  file arch/arm/mach-tegra/board-paz00-power.c

  For many rails, the constraints in that tree specified differing min
  and max voltages. In all cases, the min value was ignored, since
  there's no need currently to vary any of the voltages at run-time.
  DVFS might change this in the future.

In most cases these sources all matched. Differences are:

sm0: HW defaults and schematic match at 1.2v. marvin24's kernel had a max
of 1.3v, but this higher voltage was only applied to HW by DVFS code,
which isn't currently supported in mainline.

sm1: HW defaults and schematic match at 1.0v. marvin24's kernel had a max
of 1.125v, but this higher voltage was only applied to HW by DVFS code,
which isn't currently supported in mainline.

ldo3: The HW default is on. marvin24's kernel didn't specify always-on,
but since the board wasn't marked as having fully constrained regulators,
the rail was not turned off, so the difference had no effect. The rail
is needed for USB.

ldo6: The HW default is 2.85v. The schematics indicate 2.85v. However,
since this regulator is used for the same purpose as on other boards that
require 1.8v, this is set to 1.8v. Note that this regulator feeds the CRT
VDAC on Tegra, and so in practice is unlikely to be used, even though it
is actaully hooked up in HW.

Portions based on work by Laxman Dewangan <ldewangan at nvidia.com>

Signed-off-by: Stephen Warren <swarren at nvidia.com>
Tested-by: Marc Dietrich <marvin24 at gmx.de> # v2
---
Laxman, note that I have similar patches for Seaboard and Ventana too, but
since the structure of all 3 is basically the same, I figured I'd only send
1 for review first to get any issues sorted, then post the other 2 later.

v4:
* Added supply properties for all TPS6586x regulators.
* Made SM* supplied by the new SYS regulator.
* Removed ldo0 configuration, since it isn't used. Clarified ldo6 usage in
  commit description.
v3:
* Slight rewording of sm0/sm1 data source resolution description.
* Adjusted ldo6 to 1.8v to match other boards using it for the same thing.
* Enhanced all regulator-name properties to also list the Tegra20 pins
  driven by the regulators. Thus, the regulator-name properties mostly match
  Seaboard and Ventana. Note that the AC100 schematics don't actually name
  the signals themselves after the pins, like Seaboard/Ventana do.
* Added ldo_rtc regulator.
v2:
* Made all constraints specify a single voltage rather than different
  min/max, per description above.
* Removed vin-supply properties from LDO nodes; the driver and binding
  need to be updated to support specifying the parent regulators before
  we can put these into DT.
---
 arch/arm/boot/dts/tegra20-paz00.dts |  173 +++++++++++++++++++++++++++++++++++
 1 files changed, 173 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1..ddf287f 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
 		status = "okay";
 		clock-frequency = <400000>;
 
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&p5valw_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "+1.2vs_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "+1.0vs_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "+3.7vs_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "+1.1vs_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "+1.2vs_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator at 7 {
+					reg = <7>;
+					regulator-compatible = "ldo3";
+					regulator-name = "+3.3vs_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "+2.85vs_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					/*
+					 * Research indicates this should be
+					 * 1.8v; other boards that use this
+					 * rail for the same purpose need it
+					 * set to 1.8v. The schematic signal
+					 * name is incorrect; perhaps copied
+					 * from an incorrect NVIDIA reference.
+					 */
+					regulator-name = "+2.85vs_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "+3.3vs_rtc";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
 		adt7461 at 4c {
 			compatible = "adi,adt7461";
 			reg = <0x4c>;
 		};
 	};
 
+	pmc {
+		nvidia,invert-interrupt;
+	};
+
 	usb at c5000000 {
 		status = "okay";
 	};
@@ -325,6 +483,21 @@
 		};
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		p5valw_reg: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "+5valw";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-alc5632-paz00",
 			"nvidia,tegra-audio-alc5632";
-- 
1.7.0.4



From will.deacon at arm.com  Thu Aug  2 14:50:33 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 2 Aug 2012 19:50:33 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802181810.GW6802@n2100.arm.linux.org.uk>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
 <20120802153030.GV6802@n2100.arm.linux.org.uk>
 <20120802155140.GF9838@mudshark.cambridge.arm.com>
 <20120802181810.GW6802@n2100.arm.linux.org.uk>
Message-ID: <20120802185033.GA2725@mudshark.cambridge.arm.com>

On Thu, Aug 02, 2012 at 07:18:10PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 02, 2012 at 04:51:41PM +0100, Will Deacon wrote:
> > On Thu, Aug 02, 2012 at 04:30:30PM +0100, Russell King - ARM Linux wrote:
> > > It might just be easier to specify something like -march=armv4 or
> > > something like that, and then use .arch armv6 where required.
> > 
> > We could do that, but I worry that it will become very messy if/when people
> > start adding things like virtualisation instructions (hvc and co) to the
> > entry code. Using the same march flag for kernel and decompressor also keeps
> > everything consistent.
> 
> But you're missing a fundamental point: the decompressor is not designed
> to be built like that, it is designed to be built in such a way that it
> works unmodified on any CPU type we have to date, whether you're building
> a kernel for ARMv4 or ARMv7.
> 
> So, the code sequences which are architecture specific are only executed
> after we've checked the ID registers to determine what we should be doing
> for a particular CPU.

That's fine, *if* we can persuade the tools to build the thing for us. With
march=all, we got what we wanted but now that doesn't seem to work anymore.

> Hence, even if you're building for ARMv4, the decompressor will _still_
> contain all the support code for ARMv7 - and the assembler better accept
> those instructions too.

With recent tools, it looks like that's really hard to do... simply passing
the lowest common denominator of march=armv4 will cause the assembler to
barf on all the non-v4 code, which includes Thumb ("Error: selected processor
does not support THUMB opcodes"). It sounds like we want to pass the march
option corresponding to the highest architecture version supported by the
kernel being compiled (assuming we don't use anything that gets deprecated
by a later version of the architecture(!)).

Yuck.

> The alternative is we scatter various places with lots of yucky ifdefs,
> and it won't be pretty because quite a number of CPUs share the same code
> (which leads to long #if defined(CPU_A) || defined(CPU_B) etc).

That'll work, but let's keep it as a last resort. This is still a toolchain
issue we're dealing with here.

Will


From gilles.chanteperdrix at xenomai.org  Thu Aug  2 15:08:19 2012
From: gilles.chanteperdrix at xenomai.org (Gilles Chanteperdrix)
Date: Thu, 02 Aug 2012 21:08:19 +0200
Subject: doubts about switch_mm
Message-ID: <501AD023.3020204@xenomai.org>


Hi, 

I know that switch_mm has been like this for years, and that it seems 
to work, but still, something seems wrong:

switch_mm code, as of 3.5 contains:

1        if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {  
2                check_and_switch_context(next, tsk);                             
3                if (cache_is_vivt())                                             
4                        cpumask_clear_cpu(cpu, mm_cpumask(prev));                
5        }                                                                        

Line 1 seems to mean that maybe switch_mm is called with prev == next.
But then, what line 4 does is certainly wrong if prev == next.

Regards.

-- 
                                                                Gilles.


From arnaud.patard at rtp-net.org  Thu Aug  2 15:09:15 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Thu, 02 Aug 2012 21:09:15 +0200
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802185033.GA2725@mudshark.cambridge.arm.com> (Will Deacon's
 message of "Thu, 2 Aug 2012 19:50:33 +0100")
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
 <20120802153030.GV6802@n2100.arm.linux.org.uk>
 <20120802155140.GF9838@mudshark.cambridge.arm.com>
 <20120802181810.GW6802@n2100.arm.linux.org.uk>
 <20120802185033.GA2725@mudshark.cambridge.arm.com>
Message-ID: <87boit2js4.fsf@lebrac.rtp-net.org>

Will Deacon <will.deacon at arm.com> writes:

> On Thu, Aug 02, 2012 at 07:18:10PM +0100, Russell King - ARM Linux wrote:
>> On Thu, Aug 02, 2012 at 04:51:41PM +0100, Will Deacon wrote:
>> > On Thu, Aug 02, 2012 at 04:30:30PM +0100, Russell King - ARM Linux wrote:
>> > > It might just be easier to specify something like -march=armv4 or
>> > > something like that, and then use .arch armv6 where required.
>> > 
>> > We could do that, but I worry that it will become very messy if/when people
>> > start adding things like virtualisation instructions (hvc and co) to the
>> > entry code. Using the same march flag for kernel and decompressor also keeps
>> > everything consistent.
>> 
>> But you're missing a fundamental point: the decompressor is not designed
>> to be built like that, it is designed to be built in such a way that it
>> works unmodified on any CPU type we have to date, whether you're building
>> a kernel for ARMv4 or ARMv7.
>> 
>> So, the code sequences which are architecture specific are only executed
>> after we've checked the ID registers to determine what we should be doing
>> for a particular CPU.
>
> That's fine, *if* we can persuade the tools to build the thing for us. With
> march=all, we got what we wanted but now that doesn't seem to work anymore.
>

and we already had to fix -march=all in the past :
http://sourceware.org/bugzilla/show_bug.cgi?id=12698

So maybe would be easier to try to fix it instead of trying to
workaround it ?

Arnaud


From zonque at gmail.com  Thu Aug  2 15:43:36 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu,  2 Aug 2012 21:43:36 +0200
Subject: [PATCH 2/2] net: davinci_mdio: add DT bindings
In-Reply-To: <1343936616-29318-1-git-send-email-zonque@gmail.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
Message-ID: <1343936616-29318-2-git-send-email-zonque@gmail.com>

Signed-off-by: Daniel Mack <zonque at gmail.com>
---
 .../devicetree/bindings/net/davinci_mdio.txt       | 24 +++++++++++++
 drivers/net/ethernet/ti/davinci_mdio.c             | 39 ++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/davinci_mdio.txt

diff --git a/Documentation/devicetree/bindings/net/davinci_mdio.txt b/Documentation/devicetree/bindings/net/davinci_mdio.txt
new file mode 100644
index 0000000..03292a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davinci_mdio.txt
@@ -0,0 +1,24 @@
+Davinci MDIO DT bindings
+
+Required properties:
+
+ - compatible : should be "ti,davinci-mdio"
+
+Optional properties:
+
+ - bus-freq : an integer to specify the bus speed
+
+Examples:
+
+	mdio: davinci_mdio at 4a101000 {
+		compatible = "ti,davinci-mdio";
+		ti,hwmods = "davinci_mdio";
+	};
+
+ or
+
+	mdio: davinci_mdio at 4a101000 {
+		compatible = "ti,davinci-mdio";
+		reg = <0x4a101000 0x100>;
+	};
+
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index b4b6015..2640cae 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -36,6 +36,8 @@
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
 #include <linux/davinci_emac.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -289,6 +291,37 @@ static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id davinci_mdio_dt_ids[] = {
+	{ .compatible = "ti,davinci-mdio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, davinci_mdio_dt_ids);
+
+static inline int davinci_mdio_probe_dt(struct device *dev,
+					struct mdio_platform_data *pdata)
+{
+	struct device_node *np = dev->of_node;
+	const struct of_device_id *of_id =
+			of_match_device(davinci_mdio_dt_ids, dev);
+	u32 tmp;
+
+	if (!of_id)
+		return 0;
+
+	if (of_property_read_u32(np, "bus-freq", &tmp) == 0)
+		pdata->bus_freq = tmp;
+
+	return 0;
+}
+#else
+static inline int davinci_mdio_probe_dt(struct device *dev,
+					struct mdio_platform_data *pdata)
+{
+	return 0;
+}
+#endif
+
 static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 {
 	struct mdio_platform_data *pdata = pdev->dev.platform_data;
@@ -306,6 +339,10 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 
 	data->pdata = pdata ? (*pdata) : default_pdata;
 
+	ret = davinci_mdio_probe_dt(dev, pdata);
+	if (ret < 0)
+		goto free_mem;
+
 	data->bus = mdiobus_alloc();
 	if (!data->bus) {
 		dev_err(dev, "failed to alloc mii bus\n");
@@ -389,6 +426,7 @@ bail_out:
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 
+free_mem:
 	kfree(data);
 
 	return ret;
@@ -471,6 +509,7 @@ static struct platform_driver davinci_mdio_driver = {
 		.name	 = "davinci_mdio",
 		.owner	 = THIS_MODULE,
 		.pm	 = &davinci_mdio_pm_ops,
+		.of_match_table = of_match_ptr(davinci_mdio_dt_ids),
 	},
 	.probe = davinci_mdio_probe,
 	.remove = __devexit_p(davinci_mdio_remove),
-- 
1.7.11.2



From zonque at gmail.com  Thu Aug  2 15:43:35 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu,  2 Aug 2012 21:43:35 +0200
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
Message-ID: <1343936616-29318-1-git-send-email-zonque@gmail.com>

Make the driver control the device clocks. Appearantly, the Davinci
platform probes this driver with the clock all powered up, but on OMAP,
this isn't the case.

Signed-off-by: Daniel Mack <zonque at gmail.com>
---
 drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index cd7ee20..b4b6015 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 		goto bail_out;
 	}
 
+	clk_enable(data->clk);
+
 	dev_set_drvdata(dev, data);
 	data->dev = dev;
 	spin_lock_init(&data->lock);
@@ -379,8 +381,11 @@ bail_out:
 	if (data->bus)
 		mdiobus_free(data->bus);
 
-	if (data->clk)
+	if (data->clk) {
+		clk_disable(data->clk);
 		clk_put(data->clk);
+	}
+
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 
@@ -397,8 +402,11 @@ static int __devexit davinci_mdio_remove(struct platform_device *pdev)
 	if (data->bus)
 		mdiobus_free(data->bus);
 
-	if (data->clk)
+	if (data->clk) {
+		clk_disable(data->clk);
 		clk_put(data->clk);
+	}
+
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 
@@ -427,6 +435,8 @@ static int davinci_mdio_suspend(struct device *dev)
 	data->suspended = true;
 	spin_unlock(&data->lock);
 
+	clk_disable(data->clk);
+
 	return 0;
 }
 
@@ -435,6 +445,8 @@ static int davinci_mdio_resume(struct device *dev)
 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
 	u32 ctrl;
 
+	clk_enable(data->clk);
+
 	spin_lock(&data->lock);
 	pm_runtime_put_sync(data->dev);
 
-- 
1.7.11.2



From linux at arm.linux.org.uk  Thu Aug  2 15:44:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 20:44:53 +0100
Subject: [PATCH] ARM: makefile: work around toolchain bug in recent
 versions of binutils
In-Reply-To: <20120802185033.GA2725@mudshark.cambridge.arm.com>
References: <1343910206-3684-1-git-send-email-will.deacon@arm.com>
 <20120802130411.GU6802@n2100.arm.linux.org.uk>
 <20120802150123.GE9838@mudshark.cambridge.arm.com>
 <20120802153030.GV6802@n2100.arm.linux.org.uk>
 <20120802155140.GF9838@mudshark.cambridge.arm.com>
 <20120802181810.GW6802@n2100.arm.linux.org.uk>
 <20120802185033.GA2725@mudshark.cambridge.arm.com>
Message-ID: <20120802194453.GX6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 07:50:33PM +0100, Will Deacon wrote:
> With recent tools, it looks like that's really hard to do... simply passing
> the lowest common denominator of march=armv4 will cause the assembler to
> barf on all the non-v4 code, which includes Thumb ("Error: selected processor
> does not support THUMB opcodes"). It sounds like we want to pass the march
> option corresponding to the highest architecture version supported by the
> kernel being compiled (assuming we don't use anything that gets deprecated
> by a later version of the architecture(!)).

This is where having an option of "create opcodes exactly from the
assembly I specify in this file, I know what I'm doing, and I don't
care that some instructions aren't present on various CPUs" becomes a
requirement than a desire.

> > The alternative is we scatter various places with lots of yucky ifdefs,
> > and it won't be pretty because quite a number of CPUs share the same code
> > (which leads to long #if defined(CPU_A) || defined(CPU_B) etc).
> 
> That'll work, but let's keep it as a last resort. This is still a toolchain
> issue we're dealing with here.

Another possibility is to use .word for the instructions as refuses to
use for us, which is also yuck.

The more the binutils folk decide that they should be gods and rule what
code we can write, the more work-arounds we will have to find.  Maybe
that even gets to the point of having to write our own assembler...  It
wouldn't be the first time that something like that has been done because
a mainstream project imposed too many silly conditions on their users.


From festevam at gmail.com  Thu Aug  2 15:46:39 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 2 Aug 2012 16:46:39 -0300
Subject: [PATCH] ARM: dts: imx: fix gpio interrupts property
In-Reply-To: <1343917434-4358-1-git-send-email-shawn.guo@linaro.org>
References: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
 <1343917434-4358-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAOMZO5A3hRp1f-244cPPE15Ur-V6stANrQ2QrS5j58J3BMRnXQ@mail.gmail.com>

On Thu, Aug 2, 2012 at 11:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Commit 88cde8b (ARM: dts: imx: update #interrupt-cells for gpio nodes)
> changes gpio #interrupt-cells from 1 to 2 without updating the users.
> It causes the gpio irq requesting call failing in client driver's probe
> function.
>
> Add the irq type cell for those gpio interrupt users to fix their
> driver probe failure.
>
> Reported-by: Fabio Estevam <festevam at gmail.com>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Tested-by: Fabio Estevam <fabio.estevam at freescale.com>

Still see an issue with gpio-key, but I guess it is because
http://patches.linaro.org/2743/
is missing.

Thanks,

Fabio Estevam


From linux at arm.linux.org.uk  Thu Aug  2 15:49:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 20:49:31 +0100
Subject: doubts about switch_mm
In-Reply-To: <501AD023.3020204@xenomai.org>
References: <501AD023.3020204@xenomai.org>
Message-ID: <20120802194931.GY6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 09:08:19PM +0200, Gilles Chanteperdrix wrote:
> switch_mm code, as of 3.5 contains:
> 
> 1   if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {  
> 2           check_and_switch_context(next, tsk);                             
> 3           if (cache_is_vivt())                                             
> 4                   cpumask_clear_cpu(cpu, mm_cpumask(prev));                
> 5   }                                                                        
> 
> Line 1 seems to mean that maybe switch_mm is called with prev == next.
> But then, what line 4 does is certainly wrong if prev == next.

Look at it more carefully.

If prev == next, then we're already running with *this* mm.  The bit
in the CPU mask for this CPU will be set.

So, cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) will be true, and
because the condition is inverted, the first half of the if condition
is false.

The second half is false, because prev == next.  So lines 2-4 will not
be executed.


From zonque at gmail.com  Thu Aug  2 15:51:37 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu,  2 Aug 2012 21:51:37 +0200
Subject: [PATCH RFC] ARM: omap2/am33xx: add hwmod for davinci_mdio
Message-ID: <1343937097-30484-1-git-send-email-zonque@gmail.com>

Add a hwmod entry for the davinci_mdio hardware block. This aliases the
cpsw_125mhz_clkdm and re-uses am33xx_cpgmac0_hwmod_class.

Signed-off-by: Daniel Mack <zonque at gmail.com>
---

I'm still not totally confident with the hwmod environment, so I'm not
entirely sure whether sharing the hwmod_class is the right thing to do
here. However, I can at least get ethernet to work on my board now.

 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 31 ++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 5a4660b..637b6cc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -684,6 +684,19 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 	},
 };
 
+static struct omap_hwmod am33xx_cpsw_mdio_hwmod = {
+	.name		= "davinci_mdio",
+	.class		= &am33xx_cpgmac0_hwmod_class,
+	.clkdm_name	= "cpsw_125mhz_clkdm",
+	.main_clk	= "cpsw_125mhz_gclk",
+	.prcm		= {
+		.omap4	= {
+			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
 /*
  * dcan class
  */
@@ -2501,6 +2514,23 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space am33xx_cpsw_mdio_addr_space[] = {
+	{
+		.pa_start	= 0x4a101000,
+		.pa_end		= 0x4a101000 + SZ_256 - 1,
+		.flags		= ADDR_TYPE_RT,
+	},
+	{ }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpsw_mdio = {
+	.master		= &am33xx_l4_hs_hwmod,
+	.slave		= &am33xx_cpsw_mdio_hwmod,
+	.clk		= "cpsw_125mhz_gclk",
+	.addr		= am33xx_cpsw_mdio_addr_space,
+	.user		= OCP_USER_MPU,
+};
+
 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
 	{
 		.pa_start	= 0x48080000,
@@ -3371,6 +3401,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 	&am33xx_l3_main__tptc2,
 	&am33xx_l3_s__usbss,
 	&am33xx_l4_hs__cpgmac0,
+	&am33xx_l4_hs__cpsw_mdio,
 	NULL,
 };
 
-- 
1.7.11.2



From linux at arm.linux.org.uk  Thu Aug  2 15:53:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 2 Aug 2012 20:53:08 +0100
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <1343936616-29318-1-git-send-email-zonque@gmail.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
Message-ID: <20120802195308.GZ6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 09:43:35PM +0200, Daniel Mack wrote:
> Make the driver control the device clocks. Appearantly, the Davinci
> platform probes this driver with the clock all powered up, but on OMAP,
> this isn't the case.

Hmm, this looks like it could do with improvement, especially as we're
moving everything over to a common clk API.

1. This driver could do with clk_prepare()/clk_unprepare() calls.
2. This driver should not be making the assumption that NULL means
   it can avoid clk_* calls.  It should instead be using
	if (!IS_ERR(clk))

Thanks.


From zonque at gmail.com  Thu Aug  2 15:56:57 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 21:56:57 +0200
Subject: Current state of AM33xx patches
In-Reply-To: <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
References: <4FD5BA4C.9070706@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
 <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
Message-ID: <501ADB89.4030405@gmail.com>

On 02.08.2012 17:37, Koen Kooi wrote:
>  But I still can't get it working:
> 
> root at beaglebone:~# dmesg | grep -i cpsw [   13.504425] net eth0:
> initializing cpsw version 1.12 (0)
> 
> root at beaglebone:~# dmesg | grep -i phy [    0.000000] Booting Linux
> on physical CPU 0 [    0.228496] nop_usb_xceiv phy.17: transceiver
> type USB2 PHY already exists [   13.512056] libphy: PHY
> davinci_mdio-0:00 not found [   13.517168] net eth0: phy
> davinci_mdio-0:00 not found on slave 0 [   13.523516] libphy: PHY
> davinci_mdio-0:01 not found [   13.528675] net eth0: phy
> davinci_mdio-0:01 not found on slave 1
> 
> root at beaglebone:~# ifconfig -a | grep eth eth0      Link
> encap:Ethernet  HWaddr 00:04:9F:01:1B:B8

Ok, I got it up and and running now on my board using the two
davinci_mdio drivers and the hwmod addition I just posted.

With those applied on top of Mugunthan work, I can link my cpsw slave
with the phy id "davinci_mdio.18-:04", but the 18 is just the global
device counter which will change again once I add more devices. That
still needs some cleanup.

Anyway, at least I can boot into my NFS root now :) Koen, can you try
this on your board and see if that works for you as well?


Thanks,
Daniel



From gilles.chanteperdrix at xenomai.org  Thu Aug  2 16:02:05 2012
From: gilles.chanteperdrix at xenomai.org (Gilles Chanteperdrix)
Date: Thu, 02 Aug 2012 22:02:05 +0200
Subject: doubts about switch_mm
In-Reply-To: <20120802194931.GY6802@n2100.arm.linux.org.uk>
References: <501AD023.3020204@xenomai.org>
 <20120802194931.GY6802@n2100.arm.linux.org.uk>
Message-ID: <501ADCBD.20907@xenomai.org>

On 08/02/2012 09:49 PM, Russell King - ARM Linux wrote:

> On Thu, Aug 02, 2012 at 09:08:19PM +0200, Gilles Chanteperdrix wrote:
>> switch_mm code, as of 3.5 contains:
>>
>> 1   if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {  
>> 2           check_and_switch_context(next, tsk);                             
>> 3           if (cache_is_vivt())                                             
>> 4                   cpumask_clear_cpu(cpu, mm_cpumask(prev));                
>> 5   }                                                                        
>>
>> Line 1 seems to mean that maybe switch_mm is called with prev == next.
>> But then, what line 4 does is certainly wrong if prev == next.
> 
> Look at it more carefully.
> 
> If prev == next, then we're already running with *this* mm.  The bit
> in the CPU mask for this CPU will be set.
> 
> So, cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) will be true, and
> because the condition is inverted, the first half of the if condition
> is false.
> 
> The second half is false, because prev == next.  So lines 2-4 will not
> be executed.
>


So, prev != next on line 1 is useless ?


-- 
                                                                Gilles.


From gilles.chanteperdrix at xenomai.org  Thu Aug  2 16:05:16 2012
From: gilles.chanteperdrix at xenomai.org (Gilles Chanteperdrix)
Date: Thu, 02 Aug 2012 22:05:16 +0200
Subject: doubts about switch_mm
In-Reply-To: <501ADCBD.20907@xenomai.org>
References: <501AD023.3020204@xenomai.org>
 <20120802194931.GY6802@n2100.arm.linux.org.uk> <501ADCBD.20907@xenomai.org>
Message-ID: <501ADD7C.40607@xenomai.org>

On 08/02/2012 10:02 PM, Gilles Chanteperdrix wrote:

> On 08/02/2012 09:49 PM, Russell King - ARM Linux wrote:
> 
>> On Thu, Aug 02, 2012 at 09:08:19PM +0200, Gilles Chanteperdrix wrote:
>>> switch_mm code, as of 3.5 contains:
>>>
>>> 1   if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {  
>>> 2           check_and_switch_context(next, tsk);                             
>>> 3           if (cache_is_vivt())                                             
>>> 4                   cpumask_clear_cpu(cpu, mm_cpumask(prev));                
>>> 5   }                                                                        
>>>
>>> Line 1 seems to mean that maybe switch_mm is called with prev == next.
>>> But then, what line 4 does is certainly wrong if prev == next.
>>
>> Look at it more carefully.
>>
>> If prev == next, then we're already running with *this* mm.  The bit
>> in the CPU mask for this CPU will be set.
>>
>> So, cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) will be true, and
>> because the condition is inverted, the first half of the if condition
>> is false.
>>
>> The second half is false, because prev == next.  So lines 2-4 will not
>> be executed.
>>
> 
> 
> So, prev != next on line 1 is useless ?
> 
> 

Ok, got it, sorry for the noise.

-- 
                                                                Gilles.


From zonque at gmail.com  Thu Aug  2 16:17:56 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 22:17:56 +0200
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <20120802195308.GZ6802@n2100.arm.linux.org.uk>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
 <20120802195308.GZ6802@n2100.arm.linux.org.uk>
Message-ID: <501AE074.8090906@gmail.com>

On 02.08.2012 21:53, Russell King - ARM Linux wrote:
> On Thu, Aug 02, 2012 at 09:43:35PM +0200, Daniel Mack wrote:
>> Make the driver control the device clocks. Appearantly, the Davinci
>> platform probes this driver with the clock all powered up, but on OMAP,
>> this isn't the case.
> 
> Hmm, this looks like it could do with improvement, especially as we're
> moving everything over to a common clk API.
> 
> 1. This driver could do with clk_prepare()/clk_unprepare() calls.

Ok, done.

> 2. This driver should not be making the assumption that NULL means
>    it can avoid clk_* calls.  It should instead be using
> 	if (!IS_ERR(clk))

Well spotted. Amended patch below.


Thanks,
Daniel



-------------- next part --------------
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From koen at dominion.thruhere.net  Thu Aug  2 16:20:03 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Thu, 2 Aug 2012 22:20:03 +0200
Subject: Current state of AM33xx patches
In-Reply-To: <501ADB89.4030405@gmail.com>
References: <4FD5BA4C.9070706@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
 <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
 <501ADB89.4030405@gmail.com>
Message-ID: <CD3817A1-B8A3-4E13-816F-58DC02C4D28F@dominion.thruhere.net>


Op 2 aug. 2012, om 21:56 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:

> On 02.08.2012 17:37, Koen Kooi wrote:
>> But I still can't get it working:
>> 
>> root at beaglebone:~# dmesg | grep -i cpsw [   13.504425] net eth0:
>> initializing cpsw version 1.12 (0)
>> 
>> root at beaglebone:~# dmesg | grep -i phy [    0.000000] Booting Linux
>> on physical CPU 0 [    0.228496] nop_usb_xceiv phy.17: transceiver
>> type USB2 PHY already exists [   13.512056] libphy: PHY
>> davinci_mdio-0:00 not found [   13.517168] net eth0: phy
>> davinci_mdio-0:00 not found on slave 0 [   13.523516] libphy: PHY
>> davinci_mdio-0:01 not found [   13.528675] net eth0: phy
>> davinci_mdio-0:01 not found on slave 1
>> 
>> root at beaglebone:~# ifconfig -a | grep eth eth0      Link
>> encap:Ethernet  HWaddr 00:04:9F:01:1B:B8
> 
> Ok, I got it up and and running now on my board using the two
> davinci_mdio drivers and the hwmod addition I just posted.
> 
> With those applied on top of Mugunthan work, I can link my cpsw slave
> with the phy id "davinci_mdio.18-:04", but the 18 is just the global
> device counter which will change again once I add more devices. That
> still needs some cleanup.
> 
> Anyway, at least I can boot into my NFS root now :) Koen, can you try
> this on your board and see if that works for you as well?

[koen at Angstrom-F16-vm-rpm kernel]$ git diff
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index ac7fab5..c33a05d 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -33,6 +33,11 @@
                };
        };
 
+       mdio: davinci_mdio at 4a101000 {
+               compatible = "ti,davinci-mdio";
+               ti,hwmods = "davinci_mdio";
+       };
+
        mac: ethernet at 4A100000 {
                compatible = "ti,cpsw";
                ti,hwmods = "cpgmac0";
@@ -49,19 +54,13 @@
                no_bd_ram = <0>;
                rx_descs = <64>;
                mac_control = <0x20>;
-               slaves = <2>;
+               slaves = <1>;
                slave at 0 {
                        slave_reg_ofs = <0x208>;
                        sliver_reg_ofs = <0xd80>;
-                       phy_id = "davinci_mdio-0:00";
+                       phy_id = "davinci_mdio.21-:00";
                        mac-address = [00 04 9F 01 1B B8];
                };
-               slave at 1 {
-                       slave_reg_ofs = <0x308>;
-                       sliver_reg_ofs = <0xdc0>;
-                       phy_id = "davinci_mdio-0:01";
-                       mac-address = [00 04 9F 01 1B B9];
-               };
        };
 };


leads to:

[   14.127177] net eth0: initializing cpsw version 1.12 (0)
[   14.135038] net eth0: phy found : id is : 0x7c0f1
[   17.871215] libphy: davinci_mdio.21-:00 - Link is Up - 100/Full

So you can add my Tested-by: to the patches if you want :)

regards,

Koen

From paul at pwsan.com  Thu Aug  2 16:20:34 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 2 Aug 2012 14:20:34 -0600 (MDT)
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <1343936616-29318-1-git-send-email-zonque@gmail.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
Message-ID: <alpine.DEB.2.00.1208021416550.18867@utopia.booyaka.com>

Hi

On Thu, 2 Aug 2012, Daniel Mack wrote:

> Make the driver control the device clocks. Appearantly, the Davinci
> platform probes this driver with the clock all powered up, but on OMAP,
> this isn't the case.
> 
> Signed-off-by: Daniel Mack <zonque at gmail.com>

> ---
>  drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
> index cd7ee20..b4b6015 100644
> --- a/drivers/net/ethernet/ti/davinci_mdio.c
> +++ b/drivers/net/ethernet/ti/davinci_mdio.c
> @@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
>  		goto bail_out;
>  	}
>  
> +	clk_enable(data->clk);
> +

This doesn't look right.  This clock should be enabled by the
pm_runtime_get_sync() call just above this.  It shouldn't be necessary
to enable it again unless something isn't right with the integration
data. Likewise the pm_runtime_put_sync() calls should be superfluous.

What hwmod data/device tree file are you using with this?


- Paul


From zonque at gmail.com  Thu Aug  2 16:28:48 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 22:28:48 +0200
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <alpine.DEB.2.00.1208021416550.18867@utopia.booyaka.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
 <alpine.DEB.2.00.1208021416550.18867@utopia.booyaka.com>
Message-ID: <501AE300.2090707@gmail.com>

On 02.08.2012 22:20, Paul Walmsley wrote:
> Hi
> 
> On Thu, 2 Aug 2012, Daniel Mack wrote:
> 
>> Make the driver control the device clocks. Appearantly, the Davinci
>> platform probes this driver with the clock all powered up, but on OMAP,
>> this isn't the case.
>>
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
> 
>> ---
>>  drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
>>  1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
>> index cd7ee20..b4b6015 100644
>> --- a/drivers/net/ethernet/ti/davinci_mdio.c
>> +++ b/drivers/net/ethernet/ti/davinci_mdio.c
>> @@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
>>  		goto bail_out;
>>  	}
>>  
>> +	clk_enable(data->clk);
>> +
> 
> This doesn't look right.  This clock should be enabled by the
> pm_runtime_get_sync() call just above this.  It shouldn't be necessary
> to enable it again unless something isn't right with the integration
> data. Likewise the pm_runtime_put_sync() calls should be superfluous.

Aah, thanks for the heads-up. To explain, I first worked with a dirty
hack to alias the clock, and I definitely needed these extra calls then.

> What hwmod data/device tree file are you using with this?

Later, I added the hwmod to move away from these hacks, and indeed, that
lets the pm runtime code handle the clock enabling. With that in place,
the patch we're talking about here is in fact unnecessary.

The second one though (the one that adds DT bindings) should go in.

I will send a separate one later that fixes the IS_ERR(data->clk) error
that Russell spotted. But that's now unrelated.


Thanks for the review,
Daniel



From zonque at gmail.com  Thu Aug  2 16:32:06 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 02 Aug 2012 22:32:06 +0200
Subject: [alsa-devel] DT support for Davinci ASoC platform
In-Reply-To: <4FF5733E.6000604@gmail.com>
References: <1BAFE6F6C881BF42822005164F1491C33EA35352@DBDE01.ent.ti.com>
 <4FF5733E.6000604@gmail.com>
Message-ID: <501AE3C6.8040708@gmail.com>

On 05.07.2012 12:58, Daniel Mack wrote:
> Hi Gururaja,
> 
> On 04.07.2012 14:48, Hebbar, Gururaja wrote:
>> All,
>>
>> Are there any plans or work going on for providing Device Tree Support for Davinci
>> ASoC?
>>
>> I am planning to add DT support for TI AM335x (McASP) and I don't want to do duplicate
>> task.
> 
> That's good to know. But isn't there a dependency on the EDMA engine? Is
> that part ported yet?

May I ask whether you made any progress on that yet?


Thanks,
Daniel



From mturquette at ti.com  Thu Aug  2 17:20:25 2012
From: mturquette at ti.com (Mike Turquette)
Date: Thu, 2 Aug 2012 14:20:25 -0700
Subject: [PATCH] arm:davinci: clk - migrate to new common clock API
In-Reply-To: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
Message-ID: <20120802212025.GI29410@gmail.com>

On 20120802-12:53, Murali Karicheri wrote:
> As a first step towards migrating davinci platforms to use common clock
> framework, replace all instances of clk_enable() with clk_prepare_enable()
> and clk_disable() with clk_disable_unprepare(). Until the platform is
> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
> adds a might_sleep() call and would work without any issues.
> 
> This will make it easy later to switch to common clk based implementation
> of clk driver from DaVinci specific driver.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>

Murali,

The important thing to know about clk_prepare is that it might sleep.
All of the functions below look like initialization functions for code
that is never run in interrupt context.  If you can confirm that this is
true then feel free to add my,

Reviewed-by: Mike Turquette <mturquette at linaro.org>

Regards,
Mike

> ---
>  arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
>  arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
>  arch/arm/mach-davinci/board-dm365-evm.c     |    4 ++--
>  arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
>  arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
>  arch/arm/mach-davinci/devices-da8xx.c       |    6 +++---
>  arch/arm/mach-davinci/serial.c              |    2 +-
>  arch/arm/mach-davinci/time.c                |    4 ++--
>  8 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
> index 1c7b1f4..4821fba 100644
> --- a/arch/arm/mach-davinci/board-dm355-evm.c
> +++ b/arch/arm/mach-davinci/board-dm355-evm.c
> @@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
>  	if (IS_ERR(aemif))
>  		WARN("%s: unable to get AEMIF clock\n", __func__);
>  	else
> -		clk_enable(aemif);
> +		clk_prepare_enable(aemif);
>  
>  	platform_add_devices(davinci_evm_devices,
>  			     ARRAY_SIZE(davinci_evm_devices));
> diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
> index 8e77032..b754ccf 100644
> --- a/arch/arm/mach-davinci/board-dm355-leopard.c
> +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
> @@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
>  	if (IS_ERR(aemif))
>  		WARN("%s: unable to get AEMIF clock\n", __func__);
>  	else
> -		clk_enable(aemif);
> +		clk_prepare_enable(aemif);
>  
>  	platform_add_devices(davinci_leopard_devices,
>  			     ARRAY_SIZE(davinci_leopard_devices));
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
> index 2830692..3a4743b 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -481,7 +481,7 @@ static void __init evm_init_cpld(void)
>  	aemif_clk = clk_get(NULL, "aemif");
>  	if (IS_ERR(aemif_clk))
>  		return;
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
>  			"cpld") == NULL)
> @@ -492,7 +492,7 @@ static void __init evm_init_cpld(void)
>  				SECTION_SIZE);
>  fail:
>  		pr_err("ERROR: can't map CPLD\n");
> -		clk_disable(aemif_clk);
> +		clk_disable_unprepare(aemif_clk);
>  		return;
>  	}
>  
> diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
> index d34ed55..04ef708 100644
> --- a/arch/arm/mach-davinci/board-dm644x-evm.c
> +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
> @@ -775,7 +775,7 @@ static __init void davinci_evm_init(void)
>  	struct davinci_soc_info *soc_info = &davinci_soc_info;
>  
>  	aemif_clk = clk_get(NULL, "aemif");
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (HAS_ATA) {
>  		if (HAS_NAND || HAS_NOR)
> diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
> index 5de69f2..7fdd0a7b 100644
> --- a/arch/arm/mach-davinci/board-neuros-osd2.c
> +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
> @@ -221,7 +221,7 @@ static __init void davinci_ntosd2_init(void)
>  	int	status;
>  
>  	aemif_clk = clk_get(NULL, "aemif");
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (HAS_ATA) {
>  		if (HAS_NAND)
> diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
> index d1624a3..20141f5 100644
> --- a/arch/arm/mach-davinci/devices-da8xx.c
> +++ b/arch/arm/mach-davinci/devices-da8xx.c
> @@ -905,7 +905,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
>  	if (IS_ERR(da850_sata_clk))
>  		return PTR_ERR(da850_sata_clk);
>  
> -	ret = clk_enable(da850_sata_clk);
> +	ret = clk_prepare_enable(da850_sata_clk);
>  	if (ret)
>  		goto err0;
>  
> @@ -936,7 +936,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
>  	return 0;
>  
>  err1:
> -	clk_disable(da850_sata_clk);
> +	clk_disable_unprepare(da850_sata_clk);
>  err0:
>  	clk_put(da850_sata_clk);
>  	return ret;
> @@ -944,7 +944,7 @@ err0:
>  
>  static void da850_sata_exit(struct device *dev)
>  {
> -	clk_disable(da850_sata_clk);
> +	clk_disable_unprepare(da850_sata_clk);
>  	clk_put(da850_sata_clk);
>  }
>  
> diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
> index 1875740..24ddb0d 100644
> --- a/arch/arm/mach-davinci/serial.c
> +++ b/arch/arm/mach-davinci/serial.c
> @@ -95,7 +95,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
>  			continue;
>  		}
>  
> -		clk_enable(uart_clk);
> +		clk_prepare_enable(uart_clk);
>  		p->uartclk = clk_get_rate(uart_clk);
>  
>  		if (!p->membase && p->mapbase) {
> diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
> index 75da315..9847938 100644
> --- a/arch/arm/mach-davinci/time.c
> +++ b/arch/arm/mach-davinci/time.c
> @@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
>  
>  	timer_clk = clk_get(NULL, "timer0");
>  	BUG_ON(IS_ERR(timer_clk));
> -	clk_enable(timer_clk);
> +	clk_prepare_enable(timer_clk);
>  
>  	/* init timer hw */
>  	timer_init();
> @@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
>  	wd_clk = clk_get(&pdev->dev, NULL);
>  	if (WARN_ON(IS_ERR(wd_clk)))
>  		return;
> -	clk_enable(wd_clk);
> +	clk_prepare_enable(wd_clk);
>  
>  	/* disable, internal clock source */
>  	__raw_writel(0, base + TCR);
> -- 
> 1.7.9.5
> 


From mturquette at ti.com  Thu Aug  2 17:28:18 2012
From: mturquette at ti.com (Mike Turquette)
Date: Thu, 2 Aug 2012 14:28:18 -0700
Subject: [PATCH] arm:davinci: clk - migrate to new common clock API
In-Reply-To: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
Message-ID: <20120802212818.GJ29410@gmail.com>

On 20120802-12:53, Murali Karicheri wrote:
> As a first step towards migrating davinci platforms to use common clock
> framework, replace all instances of clk_enable() with clk_prepare_enable()
> and clk_disable() with clk_disable_unprepare(). Until the platform is
> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
> adds a might_sleep() call and would work without any issues.
> 
> This will make it easy later to switch to common clk based implementation
> of clk driver from DaVinci specific driver.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>

Murali,

The patch $subject is a bit misleading.  This patch is preparation for
converting davinci over to the common clk framework.  How about:

arm: davinci: clk: call clk_prepare_enable

Also, the important thing to know about clk_prepare is that it might
sleep.  All of the functions below look like initialization functions
for code that is never run in interrupt context.  If you can confirm
that this is true then feel free to add my,

Reviewed-by: Mike Turquette <mturquette at linaro.org>

Regards,
Mike

> ---
>  arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
>  arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
>  arch/arm/mach-davinci/board-dm365-evm.c     |    4 ++--
>  arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
>  arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
>  arch/arm/mach-davinci/devices-da8xx.c       |    6 +++---
>  arch/arm/mach-davinci/serial.c              |    2 +-
>  arch/arm/mach-davinci/time.c                |    4 ++--
>  8 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
> index 1c7b1f4..4821fba 100644
> --- a/arch/arm/mach-davinci/board-dm355-evm.c
> +++ b/arch/arm/mach-davinci/board-dm355-evm.c
> @@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
>  	if (IS_ERR(aemif))
>  		WARN("%s: unable to get AEMIF clock\n", __func__);
>  	else
> -		clk_enable(aemif);
> +		clk_prepare_enable(aemif);
>  
>  	platform_add_devices(davinci_evm_devices,
>  			     ARRAY_SIZE(davinci_evm_devices));
> diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
> index 8e77032..b754ccf 100644
> --- a/arch/arm/mach-davinci/board-dm355-leopard.c
> +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
> @@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
>  	if (IS_ERR(aemif))
>  		WARN("%s: unable to get AEMIF clock\n", __func__);
>  	else
> -		clk_enable(aemif);
> +		clk_prepare_enable(aemif);
>  
>  	platform_add_devices(davinci_leopard_devices,
>  			     ARRAY_SIZE(davinci_leopard_devices));
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
> index 2830692..3a4743b 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -481,7 +481,7 @@ static void __init evm_init_cpld(void)
>  	aemif_clk = clk_get(NULL, "aemif");
>  	if (IS_ERR(aemif_clk))
>  		return;
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
>  			"cpld") == NULL)
> @@ -492,7 +492,7 @@ static void __init evm_init_cpld(void)
>  				SECTION_SIZE);
>  fail:
>  		pr_err("ERROR: can't map CPLD\n");
> -		clk_disable(aemif_clk);
> +		clk_disable_unprepare(aemif_clk);
>  		return;
>  	}
>  
> diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
> index d34ed55..04ef708 100644
> --- a/arch/arm/mach-davinci/board-dm644x-evm.c
> +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
> @@ -775,7 +775,7 @@ static __init void davinci_evm_init(void)
>  	struct davinci_soc_info *soc_info = &davinci_soc_info;
>  
>  	aemif_clk = clk_get(NULL, "aemif");
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (HAS_ATA) {
>  		if (HAS_NAND || HAS_NOR)
> diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
> index 5de69f2..7fdd0a7b 100644
> --- a/arch/arm/mach-davinci/board-neuros-osd2.c
> +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
> @@ -221,7 +221,7 @@ static __init void davinci_ntosd2_init(void)
>  	int	status;
>  
>  	aemif_clk = clk_get(NULL, "aemif");
> -	clk_enable(aemif_clk);
> +	clk_prepare_enable(aemif_clk);
>  
>  	if (HAS_ATA) {
>  		if (HAS_NAND)
> diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
> index d1624a3..20141f5 100644
> --- a/arch/arm/mach-davinci/devices-da8xx.c
> +++ b/arch/arm/mach-davinci/devices-da8xx.c
> @@ -905,7 +905,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
>  	if (IS_ERR(da850_sata_clk))
>  		return PTR_ERR(da850_sata_clk);
>  
> -	ret = clk_enable(da850_sata_clk);
> +	ret = clk_prepare_enable(da850_sata_clk);
>  	if (ret)
>  		goto err0;
>  
> @@ -936,7 +936,7 @@ static int da850_sata_init(struct device *dev, void __iomem *addr)
>  	return 0;
>  
>  err1:
> -	clk_disable(da850_sata_clk);
> +	clk_disable_unprepare(da850_sata_clk);
>  err0:
>  	clk_put(da850_sata_clk);
>  	return ret;
> @@ -944,7 +944,7 @@ err0:
>  
>  static void da850_sata_exit(struct device *dev)
>  {
> -	clk_disable(da850_sata_clk);
> +	clk_disable_unprepare(da850_sata_clk);
>  	clk_put(da850_sata_clk);
>  }
>  
> diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
> index 1875740..24ddb0d 100644
> --- a/arch/arm/mach-davinci/serial.c
> +++ b/arch/arm/mach-davinci/serial.c
> @@ -95,7 +95,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
>  			continue;
>  		}
>  
> -		clk_enable(uart_clk);
> +		clk_prepare_enable(uart_clk);
>  		p->uartclk = clk_get_rate(uart_clk);
>  
>  		if (!p->membase && p->mapbase) {
> diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
> index 75da315..9847938 100644
> --- a/arch/arm/mach-davinci/time.c
> +++ b/arch/arm/mach-davinci/time.c
> @@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
>  
>  	timer_clk = clk_get(NULL, "timer0");
>  	BUG_ON(IS_ERR(timer_clk));
> -	clk_enable(timer_clk);
> +	clk_prepare_enable(timer_clk);
>  
>  	/* init timer hw */
>  	timer_init();
> @@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
>  	wd_clk = clk_get(&pdev->dev, NULL);
>  	if (WARN_ON(IS_ERR(wd_clk)))
>  		return;
> -	clk_enable(wd_clk);
> +	clk_prepare_enable(wd_clk);
>  
>  	/* disable, internal clock source */
>  	__raw_writel(0, base + TCR);
> -- 
> 1.7.9.5
> 


From omar.luna at linaro.org  Thu Aug  2 18:20:27 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Thu, 2 Aug 2012 17:20:27 -0500
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
Message-ID: <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>

Hi.

On 2 August 2012 02:52, Paul Walmsley <paul at pwsan.com> wrote:
> On Mon, 16 Jul 2012, Omar Ramirez Luna wrote:
>
>> For a reset sequence to complete cleanly, a module needs its
>> associated clocks to be enabled, otherwise the timeout check
>> in prcm code can print a false failure (failed to hardreset)
>> that occurs because the clocks aren't powered ON and the status
>> bit checked can't transition without them.
>>
>> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
>
> Is enabling the clocks sufficient?

During my testing it seemed enough, besides it looks clk framework is
doing the same as _omap4_enable_module.

> Or do we also need to enable the
> IP block, e.g. by calling
>
>         if (soc_ops.enable_module)
>                 soc_ops.enable_module(oh);
>
> as we do on OMAP4+ in _enable() ?

Basically this is a call to _omap4_enable_module, and the latter will
"Enable the modulemode inside CLKCTRL".

However, _enable_clocks path which ends calling omap2_dflt_clk_enable
does the same thing with its clk->enable_reg field.

So in _enable:

        _enable_clocks(oh);
        if (soc_ops.enable_module)
                soc_ops.enable_module(oh);

The enable_module part seems redundant to me, since the module should
be already enabled by the first call to _enable_clocks.

Regards,

Omar


From zonque at gmail.com  Thu Aug  2 18:58:34 2012
From: zonque at gmail.com (Daniel Mack)
Date: Fri, 03 Aug 2012 00:58:34 +0200
Subject: am33xx: default to status = "disabled"?
Message-ID: <501B061A.6080008@gmail.com>

Hi,

currently, all devices in arch/arm/boot/dts/am33xx.dtsi are enabled by
default. However, depending on the actual board dts, only some of the
devices should actually be initialized, given that they only make sense
if their pins are actually wired on the board.

On other platform, such devices are marked with status = "disabled", and
the board files re-enable those they really use by overriding that
status again. That approach seems to make sense - shouldn't the same be
done in am33xx.dtsi or am I missing something?


Daniel


From arnd at arndb.de  Thu Aug  2 19:28:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 2 Aug 2012 23:28:16 +0000
Subject: am33xx: default to status = "disabled"?
In-Reply-To: <501B061A.6080008@gmail.com>
References: <501B061A.6080008@gmail.com>
Message-ID: <201208022328.17095.arnd@arndb.de>

On Thursday 02 August 2012, Daniel Mack wrote:
> currently, all devices in arch/arm/boot/dts/am33xx.dtsi are enabled by
> default. However, depending on the actual board dts, only some of the
> devices should actually be initialized, given that they only make sense
> if their pins are actually wired on the board.
> 
> On other platform, such devices are marked with status = "disabled", and
> the board files re-enable those they really use by overriding that
> status again. That approach seems to make sense - shouldn't the same be
> done in am33xx.dtsi or am I missing something?

I agree, they should be disabled, at least the serial ports, and probably
also the i2c controllers.

	Arnd


From festevam at gmail.com  Thu Aug  2 20:00:51 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 2 Aug 2012 21:00:51 -0300
Subject: [PATCH] ARM: dts: imx: fix gpio interrupts property
In-Reply-To: <CAOMZO5A3hRp1f-244cPPE15Ur-V6stANrQ2QrS5j58J3BMRnXQ@mail.gmail.com>
References: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
 <1343917434-4358-1-git-send-email-shawn.guo@linaro.org>
 <CAOMZO5A3hRp1f-244cPPE15Ur-V6stANrQ2QrS5j58J3BMRnXQ@mail.gmail.com>
Message-ID: <CAOMZO5ABZzR=xkpvBt0oAt0b_po3SsDOFcG7--30ukwiqKiYWg@mail.gmail.com>

On Thu, Aug 2, 2012 at 4:46 PM, Fabio Estevam <festevam at gmail.com> wrote:

> Still see an issue with gpio-key, but I guess it is because
> http://patches.linaro.org/2743/
> is missing.

The gpio-key crash is caused by 30161f6b2e7d1 (Input: gpio_keys -
clean up device tree
parser ). If I revert it, the gpio-key is correctly probed.

I have reported this in linux-input list.

Regards,

Fabio Estevam


From festevam at gmail.com  Thu Aug  2 20:01:44 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 2 Aug 2012 21:01:44 -0300
Subject: Several crashes on imx_v6_v7_defconfig
In-Reply-To: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
References: <CAOMZO5D1oM0q2H=ZqNc3Jq9T5+kGypnDbFC8O1a5D6qQYy1ySA@mail.gmail.com>
Message-ID: <CAOMZO5Boc7mMePGYjJV4ChzNkM8=xp4kSqnxGY3gaU7G_4qp6Q@mail.gmail.com>

On Tue, Jul 31, 2012 at 11:39 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Hi,
>
> After manually fixing two build errors (patches already submitted, but
> they were not applied into linux-next yet) on imx_v6_v7_defconfig and
> booting a dt kernel on mx51evk I get:

Shawn's patch ([PATCH] ARM: dts: imx: fix gpio interrupts property)
fixed these issues.


From zhangfei.gao at gmail.com  Thu Aug  2 21:04:58 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Fri, 3 Aug 2012 09:04:58 +0800
Subject: [PATCH 0/4] dmaengine: add support mmp-pdma
In-Reply-To: <1343364382-16269-1-git-send-email-zhangfei.gao@marvell.com>
References: <1343364382-16269-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <CAMj5Bkjy4w76h2Mh3zMRwzjczSXRkTOya87_U=zTLZrYLuLxhw@mail.gmail.com>

On Fri, Jul 27, 2012 at 12:46 PM, Zhangfei Gao <zhangfei.gao at marvell.com> wrote:
> v0->v1
> Update dt member and desc according to Arnd's suggestion
> Use dma_slave_config.slave_id to transfer drcmr followed Vinod's suggestion
>
> Patch 4 is upload as example
> mtd: pxa3xx-nand: replace pxa_request_dma with dmaengine
> We would like hold this patch currently
> since pdma will grab irq and disable pxa_init_dma.
>
> Any attempt of replacing pxa_request_dma with dmaengine on pxa3xx platform are welcome
> Here are many replacing and verifying work to do.
>
>
> mmp-pdma is added under dmaengine framework.
> The final purpose is replacing arch/arm/plat-pxa/dma.c
>
> Test on pxa910 with pxa3xx-nand and dmatest.ko
>
> Zhangfei Gao (4):
>   dmaengine: mmp-pdma support
>   dmaengine: mmp_tdma: add dt support
>   dmatest: add dmaengine_slave_config for DMA_MEMCPY

Hi, Arnd & Vinod

Would you mind taking look at the updated mmp-pdma patch, thanks for the help.


From sboyd at codeaurora.org  Thu Aug  2 21:23:14 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu,  2 Aug 2012 18:23:14 -0700
Subject: [PATCH] ARM: Fix XIP build due to PHYS_OFFSET definition moving
Message-ID: <1343956994-27513-1-git-send-email-sboyd@codeaurora.org>

During the p2v changes, the PHYS_OFFSET #define moved into a
!__ASSEMBLY__ section. This causes a XIP build to fail with

 arch/arm/kernel/head.o: In function 'stext':
 arch/arm/kernel/head.S:146: undefined reference to 'PHYS_OFFSET'

Momentarily leave the #ifndef __ASSEMBLY__ section so we can
define PHYS_OFFSET for all compilation units.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

I don't know if it's worth stable, seems that nobody has compiled XIP for
a year (back to 2.6.39 days?).

 arch/arm/include/asm/memory.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index fcb5757..3299b2d 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -187,6 +187,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
 #endif
 #endif
+#endif /* __ASSEMBLY__ */
 
 #ifndef PHYS_OFFSET
 #ifdef PLAT_PHYS_OFFSET
@@ -196,6 +197,8 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #endif
 #endif
 
+#ifndef __ASSEMBLY__
+
 /*
  * PFNs are used to describe any physical page; this means
  * PFN 0 == physical address 0.
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From minggr at gmail.com  Thu Aug  2 21:23:30 2012
From: minggr at gmail.com (Lin Ming)
Date: Fri, 3 Aug 2012 09:23:30 +0800
Subject: How to debug hard lockup issue
In-Reply-To: <CAJe_ZhezzWUOUNXx=nUx8BqTwcyy6C0Cq7FcNcSg-i0Q9otOKA@mail.gmail.com>
References: <CAF1ivSY=HsqrRypru55cYMBoyY75umkwrjbz5U0F85nL5mh3tw@mail.gmail.com>
 <20120802071530.GG10670@pengutronix.de>
 <CAF1ivSZ=mHqPOks9vdWhb--gKduWpM6UM77-mMj=1gAf8P6MUA@mail.gmail.com>
 <20120802083413.GH10670@pengutronix.de>
 <CAF1ivSbbPtr0F3dWPXZMcWrzubGCg4mudcLQ1DKHe_HX5HqQbg@mail.gmail.com>
 <CAJe_ZhezzWUOUNXx=nUx8BqTwcyy6C0Cq7FcNcSg-i0Q9otOKA@mail.gmail.com>
Message-ID: <CAF1ivSbEqrgJPFt-9d+hAnfVW3tjG1PC92H-qcGYnJA2wN7d9w@mail.gmail.com>

On Thu, Aug 2, 2012 at 5:40 PM, Jassi Brar <jaswinder.singh at linaro.org> wrote:
> On 2 August 2012 15:00, Lin Ming <minggr at gmail.com> wrote:
>> On Thu, Aug 2, 2012 at 4:34 PM, Uwe Kleine-K?nig
>> <u.kleine-koenig at pengutronix.de> wrote:
>>> On Thu, Aug 02, 2012 at 03:59:36PM +0800, Lin Ming wrote:
>>>> On Thu, Aug 2, 2012 at 3:15 PM, Uwe Kleine-K?nig
>>>> <u.kleine-koenig at pengutronix.de> wrote:
>>>> > Hello,
>>>> >
>>>> > On Thu, Aug 02, 2012 at 11:03:31AM +0800, Lin Ming wrote:
>>>> >> I encountered a hard lockup on a armv5 board with 2.6.32 kernel.
>>>> >> There is no any message output since it is hard lockup.
>>>> >>
>>>> >> I tried watchdog, but watchdog can only reset the board. I still can't
>>>> >> get any info.
>>>> >>
>>>> >> The hard lockup is possibly because kernel blocked/looped with
>>>> >> interrupts disabled.
>>>> >>
>>>> >> Is there any non-maskable interrupt I can use to dump the kernel stack?
>>>> >> Or any other hint?
>>>> > Try enabling various debug options. The following come to (my) mind:
>>>> >
>>>> > CONFIG_DETECT_HUNG_TASK
>>>> > CONFIG_PROVE_LOCKING
>>>> > CONFIG_DEBUG_ATOMIC_SLEEP
>>>> > CONFIG_MAGIC_SYSRQ
>>>>
>>>> These debug options are already enabled.
>>>> But it doesn't help.
>>> then if you don't have a hardware debugger handy you can try
>>>
>>>         https://lkml.org/lkml/2012/5/26/83
>>
>> Will try pstore and PostMortem.
>>
> If the hang is after bootup, pstore is a better option. If the hang is
> consistent and during boot, dumping __log_buf is the only option.

It's after bootup.

After running about 1 day, the system is hard lockup.
That's possibly because kernel blocked/looped with interrupts
disabled(local_irq_disable).

So soft lockup detector won't help because timer interrupt(and all
other maskable interrupts) was disabled.
And unfortunately, armv5 seems don't support hard lockup detector.
Hard lockup detector needs non-maskable interrupt.

I'm going to try pstore to get the last function call when hard lockup happens.

Thanks,
Lin Ming


From ccross at android.com  Thu Aug  2 21:28:47 2012
From: ccross at android.com (Colin Cross)
Date: Thu, 2 Aug 2012 18:28:47 -0700
Subject: [RFC v2] ARM: sched_clock: update epoch_cyc on resume
In-Reply-To: <CAMbhsRQg4pETrM7cx+aSBzGn3S1LV_x7vo8X3A300vCWTjkFng@mail.gmail.com>
References: <1343184588-20239-1-git-send-email-ccross@android.com>
 <CACRpkdZv4p+QT3Y+=-xh5iJ=sr1_aahroxQ535QpzVD9e_ESJA@mail.gmail.com>
 <20120727233829.GB14835@n2100.arm.linux.org.uk>
 <CAMbhsRSGYmu=eyqik23cECsJPfpo6rUqZUa853nkY35XRo4Q_w@mail.gmail.com>
 <CAMbhsRQg4pETrM7cx+aSBzGn3S1LV_x7vo8X3A300vCWTjkFng@mail.gmail.com>
Message-ID: <CAMbhsRSboLABOD8eX4czk8FsG3QmT60RTr+znVCqwWR6ZGhgaw@mail.gmail.com>

On Fri, Jul 27, 2012 at 8:30 PM, Colin Cross <ccross at android.com> wrote:
> On Fri, Jul 27, 2012 at 6:15 PM, Colin Cross <ccross at android.com> wrote:
>> That patch was merged in 3.4, and my patch is on top of it.  Your
>> patch updates epoch_cyc and epoch_ns in suspend, but if the first call
>> to cyc_to_sched_clock after resume gets cyc = 0, cyc - epoch_cyc can
>> be negative, although it will be cast back to a large positive number.
>>
>> With my patch, epoch_cyc is updated in resume to whatever
>> read_sched_clock() returns, and epoch_ns is still set to the suspend
>> value, so it appears that sched_clock has not changed between
>> sched_clock_suspend and sched_clock_resume.  It will work with any
>> timer behavior (reset to 0, reset to random value, or continuing
>> counting).  The old setup_sched_clock function maintains the old
>> behavior to appease those who like their 32kHz sched clock to continue
>> ticking in suspend, although I think it is more correct for all sched
>> clocks to be faster than 32 kHz (when possible) and stop in suspend.
>
> I think the existing code can cause sched_clock to go backwards if the
> register read by the read function resets to 0 in suspend:
>
> In sched_clock_suspend epoch_cyc is updated to 0x00002000.
>
> The first sched_clock call after resume gets cyc = 0, returning
> epoch_ns + cyc_to_ns(0xffffe000)
>
> Later, sched_clock gets cyc = 0x5000, returning epoch_ns +
> cyc_to_ns(0x3000), which will be much smaller than the previous
> sched_clock value.

Russell, any update on this?  Should sched_clock.c handle read
functions that go backwards in suspend, or should I modify the read
function to track an offset in suspend and always return a
monotonically increasing value across suspend?


From shawn.guo at linaro.org  Thu Aug  2 21:29:07 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 09:29:07 +0800
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <201208021658.38237.marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
 <20120801203106.GW4483@opensource.wolfsonmicro.com>
 <201208021658.38237.marex@denx.de>
Message-ID: <20120803012905.GA20537@S2101-09.ap.freescale.net>

On Thu, Aug 02, 2012 at 04:58:38PM +0200, Marek Vasut wrote:
> Hm, this is spread across mxs. Shawn, is there any plan for PM implementation 
> for MXS ?
> 
Near term, no.  Long term, yes.

-- 
Regards,
Shawn



From hvaibhav at ti.com  Fri Aug  3 01:16:49 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 3 Aug 2012 10:46:49 +0530
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <1343936616-29318-1-git-send-email-zonque@gmail.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
Message-ID: <501B5EC1.7010304@ti.com>



On 8/3/2012 1:13 AM, Daniel Mack wrote:
> Make the driver control the device clocks. Appearantly, the Davinci
> platform probes this driver with the clock all powered up, but on OMAP,
> this isn't the case.
> 
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> ---
>  drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
> index cd7ee20..b4b6015 100644
> --- a/drivers/net/ethernet/ti/davinci_mdio.c
> +++ b/drivers/net/ethernet/ti/davinci_mdio.c
> @@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
>  		goto bail_out;
>  	}
>  
> +	clk_enable(data->clk);
> +
>  	dev_set_drvdata(dev, data);
>  	data->dev = dev;
>  	spin_lock_init(&data->lock);
> @@ -379,8 +381,11 @@ bail_out:
>  	if (data->bus)
>  		mdiobus_free(data->bus);
>  
> -	if (data->clk)
> +	if (data->clk) {
> +		clk_disable(data->clk);
>  		clk_put(data->clk);
> +	}
> +
>  	pm_runtime_put_sync(&pdev->dev);
>  	pm_runtime_disable(&pdev->dev);
>  
> @@ -397,8 +402,11 @@ static int __devexit davinci_mdio_remove(struct platform_device *pdev)
>  	if (data->bus)
>  		mdiobus_free(data->bus);
>  
> -	if (data->clk)
> +	if (data->clk) {
> +		clk_disable(data->clk);
>  		clk_put(data->clk);
> +	}
> +
>  	pm_runtime_put_sync(&pdev->dev);
>  	pm_runtime_disable(&pdev->dev);
>  
> @@ -427,6 +435,8 @@ static int davinci_mdio_suspend(struct device *dev)
>  	data->suspended = true;
>  	spin_unlock(&data->lock);
>  
> +	clk_disable(data->clk);
> +
>  	return 0;
>  }
>  
> @@ -435,6 +445,8 @@ static int davinci_mdio_resume(struct device *dev)
>  	struct davinci_mdio_data *data = dev_get_drvdata(dev);
>  	u32 ctrl;
>  
> +	clk_enable(data->clk);
> +

Danial,

I would request you to wait for this, its not that simple and straight.
And once you migrate to runtime PM you don't need clk_enable/disable,
this should get handled under runtime PM api's.

Also have you read my another email post -

http://comments.gmane.org/gmane.linux.ports.arm.omap/80796

Certainly, with respect to CPSW & MDIO, this patch is not enough and
requires further investigation. I have started looking at this and
hopefully will have some solution soon...

Thanks,
Vaibhav


From zonque at gmail.com  Fri Aug  3 01:22:40 2012
From: zonque at gmail.com (Daniel Mack)
Date: Fri, 03 Aug 2012 07:22:40 +0200
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <501B5EC1.7010304@ti.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
 <501B5EC1.7010304@ti.com>
Message-ID: <501B6020.7090502@gmail.com>

On 03.08.2012 07:16, Vaibhav Hiremath wrote:
> 
> 
> On 8/3/2012 1:13 AM, Daniel Mack wrote:
>> Make the driver control the device clocks. Appearantly, the Davinci
>> platform probes this driver with the clock all powered up, but on OMAP,
>> this isn't the case.
>>
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>> ---
>>  drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
>>  1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
>> index cd7ee20..b4b6015 100644
>> --- a/drivers/net/ethernet/ti/davinci_mdio.c
>> +++ b/drivers/net/ethernet/ti/davinci_mdio.c
>> @@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
>>  		goto bail_out;
>>  	}
>>  
>> +	clk_enable(data->clk);
>> +
>>  	dev_set_drvdata(dev, data);
>>  	data->dev = dev;
>>  	spin_lock_init(&data->lock);
>> @@ -379,8 +381,11 @@ bail_out:
>>  	if (data->bus)
>>  		mdiobus_free(data->bus);
>>  
>> -	if (data->clk)
>> +	if (data->clk) {
>> +		clk_disable(data->clk);
>>  		clk_put(data->clk);
>> +	}
>> +
>>  	pm_runtime_put_sync(&pdev->dev);
>>  	pm_runtime_disable(&pdev->dev);
>>  
>> @@ -397,8 +402,11 @@ static int __devexit davinci_mdio_remove(struct platform_device *pdev)
>>  	if (data->bus)
>>  		mdiobus_free(data->bus);
>>  
>> -	if (data->clk)
>> +	if (data->clk) {
>> +		clk_disable(data->clk);
>>  		clk_put(data->clk);
>> +	}
>> +
>>  	pm_runtime_put_sync(&pdev->dev);
>>  	pm_runtime_disable(&pdev->dev);
>>  
>> @@ -427,6 +435,8 @@ static int davinci_mdio_suspend(struct device *dev)
>>  	data->suspended = true;
>>  	spin_unlock(&data->lock);
>>  
>> +	clk_disable(data->clk);
>> +
>>  	return 0;
>>  }
>>  
>> @@ -435,6 +445,8 @@ static int davinci_mdio_resume(struct device *dev)
>>  	struct davinci_mdio_data *data = dev_get_drvdata(dev);
>>  	u32 ctrl;
>>  
>> +	clk_enable(data->clk);
>> +
> 
> Danial,
> 
> I would request you to wait for this, its not that simple and straight.
> And once you migrate to runtime PM you don't need clk_enable/disable,
> this should get handled under runtime PM api's.

As I said, it can be dropped.

> Also have you read my another email post -
> 
> http://comments.gmane.org/gmane.linux.ports.arm.omap/80796
> 
> Certainly, with respect to CPSW & MDIO, this patch is not enough and
> requires further investigation. I have started looking at this and
> hopefully will have some solution soon...

Ok, no problem. We certainly need the DT bindings for davinci_mdio. With
that applied, and the hwmod added (in the patch I posted yesterday), I
can at least mount the rootfs via NFS, which is all I currently need.


Best regards,
Daniel



From hvaibhav at ti.com  Fri Aug  3 01:24:47 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 3 Aug 2012 10:54:47 +0530
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
 <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>
Message-ID: <501B609F.9030403@ti.com>



On 8/3/2012 3:50 AM, Omar Ramirez Luna wrote:
> Hi.
> 
> On 2 August 2012 02:52, Paul Walmsley <paul at pwsan.com> wrote:
>> On Mon, 16 Jul 2012, Omar Ramirez Luna wrote:
>>
>>> For a reset sequence to complete cleanly, a module needs its
>>> associated clocks to be enabled, otherwise the timeout check
>>> in prcm code can print a false failure (failed to hardreset)
>>> that occurs because the clocks aren't powered ON and the status
>>> bit checked can't transition without them.
>>>
>>> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
>>
>> Is enabling the clocks sufficient?
> 
> During my testing it seemed enough, besides it looks clk framework is
> doing the same as _omap4_enable_module.
> 
>> Or do we also need to enable the
>> IP block, e.g. by calling
>>
>>         if (soc_ops.enable_module)
>>                 soc_ops.enable_module(oh);
>>
>> as we do on OMAP4+ in _enable() ?
> 
> Basically this is a call to _omap4_enable_module, and the latter will
> "Enable the modulemode inside CLKCTRL".
> 
> However, _enable_clocks path which ends calling omap2_dflt_clk_enable
> does the same thing with its clk->enable_reg field.
> 
> So in _enable:
> 
>         _enable_clocks(oh);
>         if (soc_ops.enable_module)
>                 soc_ops.enable_module(oh);
> 
> The enable_module part seems redundant to me, since the module should
> be already enabled by the first call to _enable_clocks.
> 

Yes they do same thing, I believe the plan is to get rid of all clock
leaf-nodes in the near future, and let hwmod handle module
enable/disable part.

Thanks,
Vaibhav

> Regards,
> 
> Omar
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From mugunthanvnm at ti.com  Fri Aug  3 01:25:47 2012
From: mugunthanvnm at ti.com (N, Mugunthan V)
Date: Fri, 3 Aug 2012 05:25:47 +0000
Subject: Current state of AM33xx patches
In-Reply-To: <501A9D1C.8080305@gmail.com>
References: <4FD5BA4C.9070706@gmail.com> <4FE326A8.8090807@gmail.com>
 <4FE8AB37.7030907@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
Message-ID: <EB1619762EAF8B4E97A227FB77B7E0293E9D393A@DBDE01.ent.ti.com>

> -----Original Message-----
> From: Daniel Mack [mailto:zonque at gmail.com]
> Sent: Thursday, August 02, 2012 9:01 PM
> To: Koen Kooi
> Cc: N, Mugunthan V; Hiremath, Vaibhav; Paul Walmsley; Nori, Sekhar;
> Jason Kridner; Tony Lindgren; Hilman, Kevin; Hernandez, Carlos; Maupin,
> Chase; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Kridner, Jason
> Subject: Re: Current state of AM33xx patches
> 
> On 31.07.2012 21:29, Koen Kooi wrote:
> 
> > 2/3 of the way there:
> >
> > http://patchwork.ozlabs.org/patch/174085/
> > http://patchwork.ozlabs.org/patch/174086/
> >
> > I keep failing to create a .dts that doesn't upset the dtc, so I
> don't have it working yet :(
> 
> Yes, that's because there are couple of sytax errors in the example
> bindings. Mugunthan, could you repost these patches and at least copy
> devicetree-discuss at lists.ozlabs.org and the ARM kernel mailing list? I
> can't comment on the patches you sent to netdev at vger.kernel.org because
> I'm not currently subscribed to that list.
> 
> 
> Thanks,
> Daniel

I will repost the patch set including the device tree and arm kernel mailing list today.

Regards
Mugunthan V N


From hvaibhav at ti.com  Fri Aug  3 01:53:37 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 05:53:37 +0000
Subject: [PATCH 1/2] net: davinci_mdio: enable and disable clock
In-Reply-To: <501B6020.7090502@gmail.com>
References: <1343936616-29318-1-git-send-email-zonque@gmail.com>
 <501B5EC1.7010304@ti.com> <501B6020.7090502@gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F04C@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 10:52:40, Daniel Mack wrote:
> On 03.08.2012 07:16, Vaibhav Hiremath wrote:
> > 
> > 
> > On 8/3/2012 1:13 AM, Daniel Mack wrote:
> >> Make the driver control the device clocks. Appearantly, the Davinci
> >> platform probes this driver with the clock all powered up, but on OMAP,
> >> this isn't the case.
> >>
> >> Signed-off-by: Daniel Mack <zonque at gmail.com>
> >> ---
> >>  drivers/net/ethernet/ti/davinci_mdio.c | 16 ++++++++++++++--
> >>  1 file changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
> >> index cd7ee20..b4b6015 100644
> >> --- a/drivers/net/ethernet/ti/davinci_mdio.c
> >> +++ b/drivers/net/ethernet/ti/davinci_mdio.c
> >> @@ -332,6 +332,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
> >>  		goto bail_out;
> >>  	}
> >>  
> >> +	clk_enable(data->clk);
> >> +
> >>  	dev_set_drvdata(dev, data);
> >>  	data->dev = dev;
> >>  	spin_lock_init(&data->lock);
> >> @@ -379,8 +381,11 @@ bail_out:
> >>  	if (data->bus)
> >>  		mdiobus_free(data->bus);
> >>  
> >> -	if (data->clk)
> >> +	if (data->clk) {
> >> +		clk_disable(data->clk);
> >>  		clk_put(data->clk);
> >> +	}
> >> +
> >>  	pm_runtime_put_sync(&pdev->dev);
> >>  	pm_runtime_disable(&pdev->dev);
> >>  
> >> @@ -397,8 +402,11 @@ static int __devexit davinci_mdio_remove(struct platform_device *pdev)
> >>  	if (data->bus)
> >>  		mdiobus_free(data->bus);
> >>  
> >> -	if (data->clk)
> >> +	if (data->clk) {
> >> +		clk_disable(data->clk);
> >>  		clk_put(data->clk);
> >> +	}
> >> +
> >>  	pm_runtime_put_sync(&pdev->dev);
> >>  	pm_runtime_disable(&pdev->dev);
> >>  
> >> @@ -427,6 +435,8 @@ static int davinci_mdio_suspend(struct device *dev)
> >>  	data->suspended = true;
> >>  	spin_unlock(&data->lock);
> >>  
> >> +	clk_disable(data->clk);
> >> +
> >>  	return 0;
> >>  }
> >>  
> >> @@ -435,6 +445,8 @@ static int davinci_mdio_resume(struct device *dev)
> >>  	struct davinci_mdio_data *data = dev_get_drvdata(dev);
> >>  	u32 ctrl;
> >>  
> >> +	clk_enable(data->clk);
> >> +
> > 
> > Danial,
> > 
> > I would request you to wait for this, its not that simple and straight.
> > And once you migrate to runtime PM you don't need clk_enable/disable,
> > this should get handled under runtime PM api's.
> 
> As I said, it can be dropped.
> 
> > Also have you read my another email post -
> > 
> > http://comments.gmane.org/gmane.linux.ports.arm.omap/80796
> > 
> > Certainly, with respect to CPSW & MDIO, this patch is not enough and
> > requires further investigation. I have started looking at this and
> > hopefully will have some solution soon...
> 
> Ok, no problem. We certainly need the DT bindings for davinci_mdio. With
> that applied, and the hwmod added (in the patch I posted yesterday), I
> can at least mount the rootfs via NFS, which is all I currently need.
> 
> 

I certainly understand your requirement here.

Actually this is not the only device we have, the same issue is applicable 
to PWM subsystem available in AM335x. Hopefully I should have something soon 
on this.


Thanks,
Vaibhav


From hvaibhav at ti.com  Fri Aug  3 02:26:24 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 06:26:24 +0000
Subject: omap_device: query on "fck" clk alias created
In-Reply-To: <20120802131250.GO7405@n2100.arm.linux.org.uk>
References: <50191F00.1040501@ti.com>
 <20120801141414.GM7405@n2100.arm.linux.org.uk>
 <79CD15C6BA57404B839C016229A409A83EA7DF5C@DBDE01.ent.ti.com>
 <20120802131250.GO7405@n2100.arm.linux.org.uk>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F0F2@DBDE01.ent.ti.com>

On Thu, Aug 02, 2012 at 18:42:50, Russell King - ARM Linux wrote:
> On Thu, Aug 02, 2012 at 01:04:37PM +0000, Hiremath, Vaibhav wrote:
> > On Wed, Aug 01, 2012 at 19:44:14, Russell King - ARM Linux wrote:
> > > On Wed, Aug 01, 2012 at 05:50:16PM +0530, Vaibhav Hiremath wrote:
> > > > The clk_get() api will not work, unless we pass both the arguments (dev,
> > > > con_id) properly. Now expecting driver to always label con_id with "fck"
> > > > is undesirable, as the same driver can be reused on multiple platforms,
> > > > which can be non-omap and/or non-ti platforms.
> > > 
> > > Why not?
> > > 
> > > The connection ID is defined by the driver, and the platform stuff is
> > > expected to provide drivers with what they require.  It's not the other
> > > way around (platforms don't tell drivers what they require.)
> > > 
> > > In other words, if the device has two clocks, one called ick and one called
> > > fck, then the device _should_ use clk_get() specifying "ick" for one, and
> > > "fck" for the other.
> > > 
> > > And platforms better provide an "ick" and a "fck" for the device, even if
> > > they have no respresentation for one or other of them (in which case you
> > > supply a dummy clock.)
> > > 
> > 
> > Russell, I completely agree with you, infact I am on the same page.
> > Let me give you a real example, which I am dealing with now,
> > 
> > On AM335x device we have integrated DCAN, this IP is not from TI.
> > IP is from Bosch and doesn't follow any of the TI IP standards, like 
> > HighLander spec. The IP is just integrated with interconnect bus and given a 
> > required clocksource (in this case its one clock). 
> > 
> > The driver for this IP is generic, (drivers/net/can/c_can/c_can_platform.c) 
> > obviously used across non-ti devices already and driver is implemented with,
> >     clk_get(dev, NULL);
> 
> So, elsewhere it only has one clock.  Are there any other clocks it needs
> on OMAP?
> 
> If the answer is no, then the driver is doing the right thing, and OMAP's
> clk stuff needs to be adjusted to suit the drivers requirements.
> 
> I've said many times over the years that clock connection IDs are defined
> by the device or driver and *nothing* else - they're certainly *not* source
> names.
> 
> That's why, when I modified OMAP drivers to fix them, and they take an
> interface and function clock, they end up asking for "ick" and "fck" not
> "blah_ick" and "blah_fck".
> 

I am in agreement with you and I believe I came to the solution for this 
issue, I used "of_dev_auxdata" to manipulate dev_id and updated clock-tree 
table with required clock entry and it works, I tried it on BeagleBone 
platform.

Can you please review it?




diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20..893cc0c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -37,11 +37,24 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
        { }
 };

+/*
+ * Lookup table for attaching a specific name and platform_data        pointer to
+ * devices as they get created by of_platform_populate().  Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name.
+ */
+static const struct of_dev_auxdata omap_auxdata_lookup[] __initconst = {
+       OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
+       OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
+       { },
+};
+
+
 static void __init omap_generic_init(void)
 {
        omap_sdrc_init(NULL, NULL);

-       of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
+       of_platform_populate(NULL, omap_dt_match_table, omap_auxdata_lookup, NULL);
}

 #ifdef CONFIG_SOC_OMAP2420
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index ae27de8..f061834 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1028,6 +1028,8 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+       CLK("d_can.0",  NULL,           &dcan0_fck,     CK_AM33XX),
+       CLK("d_can.1",  NULL,           &dcan1_fck,     CK_AM33XX),
        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
        CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),




From hvaibhav at ti.com  Fri Aug  3 02:28:41 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 3 Aug 2012 11:58:41 +0530
Subject: [PATCH v2 1/2] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <1343219012-19472-2-git-send-email-anilkumar@ti.com>
References: <1343219012-19472-1-git-send-email-anilkumar@ti.com>
 <1343219012-19472-2-git-send-email-anilkumar@ti.com>
Message-ID: <501B6F99.4020506@ti.com>



On 7/25/2012 5:53 PM, AnilKumar Ch wrote:
> Add Bosch D_CAN controller device tree data to AM33XX dtsi file
> by adding d_can device node with all the necessary parameters.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  arch/arm/boot/dts/am33xx.dtsi |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index 9b974dc..2db2ffb 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -163,5 +163,10 @@
>  			#size-cells = <0>;
>  			ti,hwmods = "i2c3";
>  		};
> +
> +		dcan1: d_can at 481D0000 {
> +			compatible = "bosch,d_can";
> +			ti,hwmods = "d_can1";
> +		};

Anil,

Any reason why we are only specifying dcan1 instance? Shouldn't we
specify dcan0 as well here?

Thanks,
Vaibhav


>  	};
>  };
> 


From haojian.zhuang at gmail.com  Fri Aug  3 02:51:45 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 3 Aug 2012 14:51:45 +0800
Subject: [GIT PULL] [for 3.6] pull request from dt-pxa branch in pxa git
 tree
In-Reply-To: <20120802171309.GC26795@quad.lixom.net>
References: <CAN1soZxFsnhEnyn3=2PtCovfpWeD6Kb=z5eEGAjdEO+9qUTQfQ@mail.gmail.com>
 <20120802171309.GC26795@quad.lixom.net>
Message-ID: <CAN1soZz3KFHZ-wFQUKT+Tn+MFsk8L5sOA=B8cu6=tj+YUsOw8w@mail.gmail.com>

On Fri, Aug 3, 2012 at 1:13 AM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, Jul 31, 2012 at 09:42:38AM +0800, Haojian Zhuang wrote:
>> Hi Arnd & Olof,
>>
>> Please help to pull changes from dt-pxa branch in pxa git tree.
>
> Hi,
>
> This is 3.7 material by now. Please send a new pull request once -rc1
> is out and we'll stage it for the next merge window.
>
>
OK. I'll send it for 3.7.


From haojian.zhuang at gmail.com  Fri Aug  3 02:53:18 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 3 Aug 2012 14:53:18 +0800
Subject: [GIT PULL][for 3.7] pull request from dt-mmp branch in pxa git tree
Message-ID: <CAN1soZy-FBmywNLn9a0yanx9ojfB-jnqzYyXwAYr6F1_Khvacg@mail.gmail.com>

Hi Olof & Arnd,

Please help to merge these patches from dt-mmp branch in pxa git tree.

Regards
Haojian

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git dt-mmp

for you to fetch changes up to c807e2a01b45aa921bb6e3bf68bf135fddaa538c:

  ARM: dts: add pinctrl in PXA DT files (2012-08-03 14:43:05 +0800)

----------------------------------------------------------------
Daniel Mack (9):
      RTC: add DT bindings to pxa-rtc
      MMC: pxa-mci: add DT bindings
      MTD: pxa3xx-nand: add devicetree bindings
      GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
      GPIO: gpio-pxa: fix devicetree functions
      ARM: pxa: add devicetree code for irq handling
      ARM: pxa3xx: skip default device initialization when booting via DT
      ARM: pxa3xx: add generic DT machine code
      ARM: pxa: add .dtsi files

Haojian Zhuang (6):
      pinctrl: append new pins and groups in pxa910
      pinctrl: add pinconf support in pxa3xx
      pinctrl: support dt in pxa series
      pinctrl: append new groups of mmp2
      ARM: mmp: select pinctrl for boards with DT
      ARM: dts: add pinctrl in PXA DT files

 Documentation/devicetree/bindings/mmc/pxa-mmc.txt  |   25 ++
 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |   31 ++
 .../bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt       |   35 +++
 Documentation/devicetree/bindings/rtc/pxa-rtc.txt  |   14 +
 arch/arm/boot/dts/mmp2-brownstone.dts              |   51 +++
 arch/arm/boot/dts/mmp2.dtsi                        |    5 +
 arch/arm/boot/dts/pxa168.dtsi                      |    5 +
 arch/arm/boot/dts/pxa27x.dtsi                      |   14 +
 arch/arm/boot/dts/pxa2xx.dtsi                      |  132 ++++++++
 arch/arm/boot/dts/pxa3xx.dtsi                      |   32 ++
 arch/arm/boot/dts/pxa910-dkb.dts                   |   47 +++
 arch/arm/boot/dts/pxa910.dtsi                      |    5 +
 arch/arm/mach-mmp/Kconfig                          |    2 +
 arch/arm/mach-pxa/Kconfig                          |   12 +
 arch/arm/mach-pxa/Makefile                         |    3 +
 arch/arm/mach-pxa/irq.c                            |  131 ++++++--
 arch/arm/mach-pxa/pxa-dt.c                         |   63 ++++
 arch/arm/mach-pxa/pxa3xx.c                         |   21 +-
 drivers/gpio/gpio-pxa.c                            |   96 +++---
 drivers/mmc/host/pxamci.c                          |   52 ++++
 drivers/mtd/nand/pxa3xx_nand.c                     |   85 ++++-
 drivers/pinctrl/pinctrl-mmp2.c                     |   18 +-
 drivers/pinctrl/pinctrl-pxa168.c                   |   10 +-
 drivers/pinctrl/pinctrl-pxa3xx.c                   |  325 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-pxa3xx.h                   |   17 +
 drivers/pinctrl/pinctrl-pxa910.c                   |   16 +-
 drivers/rtc/rtc-pxa.c                              |   11 +
 27 files changed, 1160 insertions(+), 98 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/pxa-mmc.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
 create mode 100644
Documentation/devicetree/bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
 create mode 100644 arch/arm/boot/dts/pxa27x.dtsi
 create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
 create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
 create mode 100644 arch/arm/mach-pxa/pxa-dt.c


From zonque at gmail.com  Fri Aug  3 03:16:54 2012
From: zonque at gmail.com (Daniel Mack)
Date: Fri, 03 Aug 2012 09:16:54 +0200
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <501B7AE6.8080405@gmail.com>

On 30.03.2012 15:27, Santosh Shilimkar wrote:
> For coupled cpuidle to work when both cpus are active, it needs a global timer
> that can handle events for both cpus.  This timer is used as the broadcast
> clock-event when the per-cpu timer hardware stop in low power states.
> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> set the irq to allow the clockevent core to determine the affinity of the
> timer.

These patches made it to mainline now, shortly befor 3.6-rc1, and it
breaks boot on my AM33xx board.

Once I revert 1/3, the board boots again but crashes with the Ooops
below. With the entire series reverted, everything works again as
expected. Any idea?

The upstream commit ids are

11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
both cpus"
5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."

> [    2.483556] net eth0: phy found : id is : 0x4dd072
> [    2.489176] Unable to handle kernel NULL pointer dereference at virtual address 00000004
> [    2.497666] pgd = c0004000
> [    2.500507] [00000004] *pgd=00000000
> [    2.504282] Internal error: Oops: 805 [#1] SMP ARM
> [    2.509309] Modules linked in:
> [    2.512530] CPU: 0    Not tainted  (3.6.0-rc1-00036-g6c4c4ee-dirty #152)
> [    2.519579] PC is at cache_alloc_refill+0x1b0/0x620
> [    2.524695] LR is at 0xc0
> [    2.527449] pc : [<c00fc0f0>]    lr : [<000000c0>]    psr: 60000093
> [    2.527449] sp : cf83dd70  ip : 00000014  fp : 00200200
> [    2.539478] r10: 00000028  r9 : c0df68c0  r8 : 00000028
> [    2.544957] r7 : cf928000  r6 : cf87f3c0  r5 : cf88d000  r4 : cf810740
> [    2.551800] r3 : 00100100  r2 : cf87f3c8  r1 : 00000000  r0 : 00000000
> [    2.558647] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
> [    2.566400] Control: 10c5387d  Table: 80004019  DAC: 00000017
> [    2.572425] Process swapper/0 (pid: 1, stack limit = 0xcf83c2f8)
> [    2.578723] Stack: (0xcf83dd70 to 0xcf83e000)
> [    2.583297] dd60:                                     00000000 00000000 cf83b3c0 cf87f3d0
> [    2.591875] dd80: cf87f3e4 00000020 00000000 00000000 00000077 cf810740 cfb2a000 00000020
> [    2.600453] dda0: 00000020 60000013 00000001 c03fdd40 cfb8d800 c00fd0f4 00000001 00000020
> [    2.609031] ddc0: cfb8d800 cfb8d800 cfb2a000 cfb2a000 00000700 00000700 cfb46500 c03fdd40
> [    2.617609] dde0: 00000000 cfb8d800 00000700 cfb2a000 cfb46500 00000001 cfb46500 c0400588
> [    2.626187] de00: cfb8de00 00000010 000000d0 c0316ae4 000000d0 c0964698 cfb8dea8 cfb8df28
> [    2.634766] de20: 76616c73 00302d65 00000000 cfb8d800 0000000d 0000016b 00001202 c04ce7c4
> [    2.643343] de40: cfb8d800 cfb8d800 c0502030 00000000 cfb8d82c c089aa80 0000016b 00001202
> [    2.651922] de60: c07ec0c0 c040bb6c c040bad0 cfb8d800 00001203 00001202 00000001 c040bd98
> [    2.660500] de80: 00000000 cfb8d800 00001202 00000003 c07e4154 c040bee4 cfb8d800 c07e416c
> [    2.669076] dea0: 00000003 c07cc3cc 00000001 00000000 00000002 00000000 00000000 00000000
> [    2.677653] dec0: 00000000 00000000 cf83c000 00000000 00000002 00000000 00000000 00000000
> [    2.686230] dee0: 00000000 00000000 c089d23c cf83c000 00000000 00000000 00000002 00000000
> [    2.694807] df00: 00000000 c008c454 00000002 00000000 00000000 c04526a8 00000000 c02aa9ac
> [    2.703385] df20: 60000013 c0851010 cf806440 c089d22c 00000002 cf83c000 00000000 0000009e
> [    2.711963] df40: c07e5dd0 c07ca394 c089d22c c08a35c0 cf83c000 c07d0ee8 c08a35c0 cf83c000
> [    2.720541] df60: 00000000 0000009e c07e5dd8 c07cc230 00000000 c00088ec 80000013 ffffffff
> [    2.729119] df80: c0776b54 c07cc230 0000009e c005c48c c06c904c c0776174 00000007 00000007
> [    2.737697] dfa0: 60000013 c07d0ee8 00000007 c07d0ec8 c08a35c0 0000009e c07e5dd8 c07a21c4
> [    2.746274] dfc0: 00000000 c07a28fc 00000007 00000007 c07a21c4 00000000 00000000 c07a2800
> [    2.754852] dfe0: c00149c0 00000013 00000000 00000000 00000000 c00149c0 55755555 75715555
> [    2.763444] [<c00fc0f0>] (cache_alloc_refill+0x1b0/0x620) from [<c00fd0f4>] (kmem_cache_alloc+0xfc/0x184)
> [    2.773496] [<c00fd0f4>] (kmem_cache_alloc+0xfc/0x184) from [<c03fdd40>] (build_skb+0x24/0xa0)
> [    2.782540] [<c03fdd40>] (build_skb+0x24/0xa0) from [<c0400588>] (__netdev_alloc_skb+0x94/0xdc)
> [    2.791681] [<c0400588>] (__netdev_alloc_skb+0x94/0xdc) from [<c0316ae4>] (cpsw_ndo_open+0x364/0x490)
> [    2.801366] [<c0316ae4>] (cpsw_ndo_open+0x364/0x490) from [<c040bb6c>] (__dev_open+0x9c/0xf8)
> [    2.810314] [<c040bb6c>] (__dev_open+0x9c/0xf8) from [<c040bd98>] (__dev_change_flags+0x78/0x13c)
> [    2.819628] [<c040bd98>] (__dev_change_flags+0x78/0x13c) from [<c040bee4>] (dev_change_flags+0x10/0x48)
> [    2.829493] [<c040bee4>] (dev_change_flags+0x10/0x48) from [<c07cc3cc>] (ip_auto_config+0x19c/0xfec)
> [    2.839079] [<c07cc3cc>] (ip_auto_config+0x19c/0xfec) from [<c00088ec>] (do_one_initcall+0x34/0x184)
> [    2.848679] [<c00088ec>] (do_one_initcall+0x34/0x184) from [<c07a28fc>] (kernel_init+0xfc/0x1c8)
> [    2.857914] [<c07a28fc>] (kernel_init+0xfc/0x1c8) from [<c00149c0>] (kernel_thread_exit+0x0/0x8)
> [    2.867131] Code: e1500001 3affffe9 e8970003 e1a0a008 (e5801004) 
> [    2.873538] ---[ end trace 1020ef2bbda0ff23 ]---



From koen at dominion.thruhere.net  Fri Aug  3 03:21:17 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 3 Aug 2012 09:21:17 +0200
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <501B7AE6.8080405@gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
Message-ID: <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>


Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:

> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>> that can handle events for both cpus.  This timer is used as the broadcast
>> clock-event when the per-cpu timer hardware stop in low power states.
>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>> set the irq to allow the clockevent core to determine the affinity of the
>> timer.
> 
> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> breaks boot on my AM33xx board.
> 
> Once I revert 1/3, the board boots again but crashes with the Ooops
> below. With the entire series reverted, everything works again as
> expected. Any idea?
> 
> The upstream commit ids are
> 
> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
> both cpus"
> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."

I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case? I'd really want cpufreq and cpuidle to work properly, but right now I'll settle for "it boots".

regards,

Koen

From haojian.zhuang at gmail.com  Fri Aug  3 03:22:29 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 3 Aug 2012 15:22:29 +0800
Subject: [GIT PULL][for 3.7] pull request from board branch in pxa git tree
Message-ID: <CAN1soZzRkozi3njrx5VJoXhP-o6H10knbDoWC=9xeQcjYNEbGw@mail.gmail.com>

Hi Olof & Arnd,

Please help to merge this board branch from pxa git tree.

Regards
Haojian


The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git board

for you to fetch changes up to 0f74da3f4bd91da4f8d3f79c9dc39a781cc7ae82:

  ARM: ttc_dkb: add nand support (2012-08-03 15:15:58 +0800)

----------------------------------------------------------------
Lei Wen (1):
      ARM: ttc_dkb: add nand support

 arch/arm/mach-mmp/ttc_dkb.c |   10 ++++++++++
 1 file changed, 10 insertions(+)


From u.kleine-koenig at pengutronix.de  Fri Aug  3 03:58:07 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 3 Aug 2012 09:58:07 +0200
Subject: [PATCH v5 0/3] Updated Cortex-M3 series
In-Reply-To: <1341512035-8173-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1341512035-8173-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803075807.GD2626@pengutronix.de>

Hello,

On Thu, Jul 05, 2012 at 08:13:52PM +0200, Uwe Kleine-K?nig wrote:
> Hello,
> 
> now that 3.5 is about to come I invested the time to update the
> beginning of the Cortex-M3 support.
> 
> Over all I rebased to v3.5-rc5 and addressed the comments by Russell.
> 
> It would be great to get these patches into next early after the merge
> window for 3.6 closes to get them into 3.7. But I won't argue if they
> made it into 3.6 ;-)
Now that v3.6-rc1 is out can these go into next for the next merge
window?

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From javier at dowhile0.org  Fri Aug  3 04:06:06 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Fri, 3 Aug 2012 10:06:06 +0200
Subject: [PATCH 1/1] ARM: OMAP3: igep0020: set GPIO mode for mux
 mcspi1_cs2 pin
In-Reply-To: <20120718072052.GK6522@atomide.com>
References: <1341885452-5372-1-git-send-email-javier@dowhile0.org>
 <CAFqH_511c6CyAYnbtU0ECZwzRNwJEdTqtcZ63nODCYZU4GC0aA@mail.gmail.com>
 <CABxcv=miEavW5Qf-Y+S4Nph+ah5gQ6QDpt-T44tdHLBxcP8pqQ@mail.gmail.com>
 <20120718072052.GK6522@atomide.com>
Message-ID: <CABxcv=kueP=UA6sQwS8Hs-s3vyAX+RhJgkHmyWWAVb668y-EOQ@mail.gmail.com>

On Wed, Jul 18, 2012 at 9:20 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Javier Martinez Canillas <javier at dowhile0.org> [120717 00:16]:
>>
>> Hi Tony,
>>
>> Just pinging to see if you have further comments on this patch or if
>> it can be applied. It solves a bug on IGEPv2 boards.
>>
>> I know the trend is to move away from board code. I'll start working
>> on an device tree for the IGEPv2 but it will take some time until is
>> ready (and I'm not sure if all the OMAP3 support is already present on
>> DT).
>>
>> So could you please take bug fixes for the board code in the meantime?
>
> Yes seems like something for the v3.6-rc series.
>
> Regards,
>
> Tony

Hi Tony,

I saw that Linus 3.6-rc1 has already been released and I didn't see
this patch on it.

So, this is a kindly reminder so you don't miss this patch :-)

Thanks a lot and best regards,
Javier


From hvaibhav at ti.com  Fri Aug  3 04:22:15 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 08:22:15 +0000
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <501B7AE6.8080405@gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F2F9@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 12:46:54, Daniel Mack wrote:
> On 30.03.2012 15:27, Santosh Shilimkar wrote:
> > For coupled cpuidle to work when both cpus are active, it needs a global timer
> > that can handle events for both cpus.  This timer is used as the broadcast
> > clock-event when the per-cpu timer hardware stop in low power states.
> > Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> > set the irq to allow the clockevent core to determine the affinity of the
> > timer.
> 
> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> breaks boot on my AM33xx board.
> 

Thanks Daniel for testing and reporting. I haven't tried 3.6-rc1 yet, as 
omap-linux/master has not yet migrated to it.
I am testing it now, and will let you know on the status.

Thanks,
Vaibhav




From lee.jones at linaro.org  Fri Aug  3 04:30:10 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 3 Aug 2012 09:30:10 +0100
Subject: [alsa-devel] [PATCH 1/6] ASoC: dapm: If one widget fails, do not
 force all subsequent widgets to fail too
In-Reply-To: <20120802175604.GF4537@opensource.wolfsonmicro.com>
References: <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
 <20120801160824.GB11892@opensource.wolfsonmicro.com>
 <20120801194134.GA4103@sirena.org.uk>
 <20120802074517.GA19231@gmail.com>
 <20120802175604.GF4537@opensource.wolfsonmicro.com>
Message-ID: <20120803083009.GC7416@gmail.com>

On Thu, Aug 02, 2012 at 06:56:04PM +0100, Mark Brown wrote:
> On Thu, Aug 02, 2012 at 08:45:18AM +0100, Lee Jones wrote:
> 
> > Over time, the requests for Maintainers have Snowballed (pun intended). My 
> > task now seems to be enabling drivers for Device Tree _and_ fix all 
> > associated driver bugs, including any requested restructuring and API
> 
> One thing to bear in mind with device tree is that it's all about
> defining an ABI - it's supposed to be stable and OS agnostic so it puts
> a lot of pressure on to really address quality problems that become
> visible in the bindings.  This stuff is much less critical with platform
> data, it's relatively easy to change.
>
> > adoption. What you fail to notice is that I am only one person, and hopping
> > all over the code-base trying to do everyone's bidding is no mean feat. In
> 
> It's fairly obvious that it's only you, or at least only you posting
> stuff (I know sometimes there are bigger teams behind people) - the
> pressure you're under to get something in is very clear.  A big part of
> what I'm saying here is that it would be really helpful if could you
> slow down a bit, discuss problems more and avoid cutting corners so
> much.  This is likely to save you time overall, you'll have a much
> higher success rate and you'll get much better feedback if it's clear
> what's going on and that there's an interest in understanding the
> issues.

I do agree that it should be correct, but the difference between getting
it 90% correct and absolutely perfect increases the effort at least x2.
With so much left to do, I think it would be better to get everything in
and functioning, then fix the minor issues as we come across them later.
This is what I've been doing from the start and it's actually looking
pretty good. I also agree that DT should be OS agnostic, but breaking up
MFDs into their functions shouldn't be an issue for other OSes. Either
they can choose to break them up and use the individual child compatible
strings, or only use the parent node.

My personal opinion is if we'd sat around discussing how it should look
prior to doing any work a) the project probably wouldn't have even got
off the ground yet and b) we would have most likely got it all wrong, as
most of our learning and knowledge has been done/gained by actually doing
the work. Instead I've been using the JFDI (Just Frickin' Do It) 
philosophy, and we've actually made some amazing headway. Being blocked
on minor issues and easy to change, orthogonal issues such as vendor
defined properties (i2c) isn't helpful to anyone.
 
> If you need to focus on device tree enablement and there are underlying
> problems in the subsystems you're looking at perhaps you need to push
> back on whoever's asking you to do the work and say you need the domain
> experts to pitch in and help you out.

If only it were that easy. We're not bursting at the seems with resources
here. I'm working in a very customer focused ecosystem. If they don't 
request it, or file a bug about it, there's no resource allocation to fix
it. However, the future is looking up from that point of view. We've just 
started a new project, which I'm hoping will attract some new resources. 
Watch this space.

> > reality I am no more obliged to fix driver bugs than you are. In fact as
> > the Maintainer of some of these subsystems, perhaps you could even help out
> > a bit?
> 
> You're not telling us about the problems you see so it's very difficult
> for anyone to help you.
> 
> For example with this patch the only information you've sent is the
> patch and the fact that you're seeing the error you're ignoring going
> off on the system you're working with (which I had to ask to find out
> about...).  You've not shown the error message or provided any other
> hint which would help anyone understand why the error might be occuring
> and what a good solution to the problem is.  Ola's guess seems very
> likely but nobody's got enough information to confirm that unless
> there's been some off-list ST/Linaro communication.

I only went off what I knew. Some objects (which wouldn't have
prevented playing audio) were failing. It seemed wrong to shut down the
entire audio system because for instance, 'headset mute' or the 'vibrator'
links were broken. As I said to you before, time is a big factor and I
have a massive TODO list. Fixing audio links a) isn't my subject of
expertise, so it would take me much longer to fix than someone with
a good knowledge of the system and b) isn't really my responsibility.
I've tested the DT stuff and it works well. Now I should move onto
something else, like providing the PRCMU with a IRQ Domain, which is
currently blocking the mainlining of other (i.e. thermal) drivers.

> Obviously with the stuff that's device specific you also have to contend
> with the fact that you're working on hardware which just isn't all that
> widely available and quite possibly has closed datasheets.
> 
> > We are all trying to do good things here. Please try not to be too over-
> > critical. We all know Mainlining is a good thing. Perhaps less people
> > would be so frightened of it, thus more people would do it if the reviews
> > weren't such a ball-ache ( for want of a better expression :) ).
> 
> This is a two way thing - one of the tools that maintainers have to try
> to drive up the quality of the code is to push back on poor quality
> submissions and devote less bandwith to sources of those submissions.
> 
> It is true that there's a bunch of people who seem to view review as
> being just an annoying obstacle to be dealt with with the minimum
> possible effort but in practice all that does is make things more
> painful for everyone, they do tend to be more noticable because
> "applied, thanks" doesn't make for a big thread.

Well I know my submissions are not always 100% perfect, but I hope 
you're not implying that they're poor quality. Writing code and fixing
things you view as bugs in code you have no prior knowledge of isn't the 
easiest task in the world. All I can do is attempt to fix the issues that
I see, which get things off the ground or make drivers work again and
submit the changes. If they're wrong they're wrong, but I don't think this
should be viewed as poor quality code!

I didn't say reviews in general. I personally think that reviews are a
very handy way of ensuring code is as the correct level for entry into
Mainline. It's also vital for the learning process, and is where most
of my knowledge has been gained. It's the type of review which defines
the experience. Some Maintainers say things like, "That's wrong. This
is wrong. Why are you doing this?" etc without explaining what the
issues are. That's not a good review, and will put people off trying
again. Equally being too overzealous and nit-picky about stuff that a)
really doesn't matter or b) can be changed really easily _if_ in the
rare case there's an issue. I've also submitted to some Maintainers
who are a pleasure to work with. They explain what's wrong and why
and encourage resubmission. I know Maintainers aren't school teachers,
or life coaches, but they should be encouraging more people to share
their good ( after some fixup ;) ) code and not playing the role of 
an incredibly hard to please boss, or impenetrable brick wall.

Let's just drop this now, or we'll be going round and round forever.
I need to move on to this PRCMU stuff, as it's blocking driver
submission. If you can lend a hand with the audioclk stubs that would
be grand. If not, me might just have to wait for Ola to come back from
his well earned vacation.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From koen at dominion.thruhere.net  Fri Aug  3 04:30:52 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 3 Aug 2012 10:30:52 +0200
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
Message-ID: <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>


Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:

> 
> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
> 
>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>>> that can handle events for both cpus.  This timer is used as the broadcast
>>> clock-event when the per-cpu timer hardware stop in low power states.
>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>>> set the irq to allow the clockevent core to determine the affinity of the
>>> timer.
>> 
>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>> breaks boot on my AM33xx board.
>> 
>> Once I revert 1/3, the board boots again but crashes with the Ooops
>> below. With the entire series reverted, everything works again as
>> expected. Any idea?
>> 
>> The upstream commit ids are
>> 
>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>> both cpus"
>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
> 
> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case? 

To answer my own question: No, the reverts aren't needed if you disable cpuidle.

From dirk.behme at de.bosch.com  Fri Aug  3 04:40:20 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 3 Aug 2012 10:40:20 +0200
Subject: [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select MXS_DMA
In-Reply-To: <1343215100-24005-3-git-send-email-festevam@gmail.com>
References: <1343215100-24005-1-git-send-email-festevam@gmail.com>
 <1343215100-24005-3-git-send-email-festevam@gmail.com>
Message-ID: <501B8E74.4030803@de.bosch.com>

On 25.07.2012 13:18, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Let MXS_DMA be selected by default.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> Changes since v1:
> - No changes. Newly introduced in this series
>  arch/arm/configs/imx_v6_v7_defconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..3c9f32f 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -192,6 +192,7 @@ CONFIG_RTC_DRV_MC13XXX=y
>  CONFIG_RTC_DRV_MXC=y
>  CONFIG_DMADEVICES=y
>  CONFIG_IMX_SDMA=y
> +CONFIG_MXS_DMA=y
>  CONFIG_COMMON_CLK_DEBUG=y
>  # CONFIG_IOMMU_SUPPORT is not set
>  CONFIG_EXT2_FS=y

Building mainline 3.6-rc1 with imx_v6_v7_defconfig this is still broken 
due to

drivers/built-in.o: In function `gpmi_dma_filter':
clk-fixed-factor.c:(.text+0xab170): undefined reference to `mxs_dma_is_apbh'

Is any fix for this on its way to mainline? Either the above or any 
other one?

Best regards

Dirk


From b32955 at freescale.com  Fri Aug  3 04:59:39 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 3 Aug 2012 16:59:39 +0800
Subject: [PATCH v2 3/3] ARM: imx_v6_v7_defconfig: Select MXS_DMA
In-Reply-To: <501B8E74.4030803@de.bosch.com>
References: <1343215100-24005-1-git-send-email-festevam@gmail.com>
 <1343215100-24005-3-git-send-email-festevam@gmail.com>
 <501B8E74.4030803@de.bosch.com>
Message-ID: <501B92FB.8040203@freescale.com>

? 2012?08?03? 16:40, Dirk Behme ??:
> On 25.07.2012 13:18, Fabio Estevam wrote:
>> From: Fabio Estevam <fabio.estevam at freescale.com>
>>
>> Let MXS_DMA be selected by default.
>>
>> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>> ---
>> Changes since v1:
>> - No changes. Newly introduced in this series
>> arch/arm/configs/imx_v6_v7_defconfig | 1 +
>> 1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/configs/imx_v6_v7_defconfig 
>> b/arch/arm/configs/imx_v6_v7_defconfig
>> index f725b96..3c9f32f 100644
>> --- a/arch/arm/configs/imx_v6_v7_defconfig
>> +++ b/arch/arm/configs/imx_v6_v7_defconfig
>> @@ -192,6 +192,7 @@ CONFIG_RTC_DRV_MC13XXX=y
>> CONFIG_RTC_DRV_MXC=y
>> CONFIG_DMADEVICES=y
>> CONFIG_IMX_SDMA=y
>> +CONFIG_MXS_DMA=y
>> CONFIG_COMMON_CLK_DEBUG=y
>> # CONFIG_IOMMU_SUPPORT is not set
>> CONFIG_EXT2_FS=y
>
> Building mainline 3.6-rc1 with imx_v6_v7_defconfig this is still 
> broken due to
>
> drivers/built-in.o: In function `gpmi_dma_filter':
> clk-fixed-factor.c:(.text+0xab170): undefined reference to 
> `mxs_dma_is_apbh'
>
> Is any fix for this on its way to mainline? Either the above or any 
> other one?
>
> Best regards
>
> Dirk
>
Since the gpmi has been enabled in the config file, I think it's better 
to select the mxs-dma in the config file too.

Acked-by: Huang Shijie <b32955 at freescale.com>

Huang Shijie



From will.deacon at arm.com  Fri Aug  3 05:02:35 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 3 Aug 2012 10:02:35 +0100
Subject: [PATCH v5 0/3] Updated Cortex-M3 series
In-Reply-To: <20120803075807.GD2626@pengutronix.de>
References: <1341512035-8173-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803075807.GD2626@pengutronix.de>
Message-ID: <20120803090235.GA26925@mudshark.cambridge.arm.com>

On Fri, Aug 03, 2012 at 08:58:07AM +0100, Uwe Kleine-K?nig wrote:
> Hello,

Hi Uwe,

> On Thu, Jul 05, 2012 at 08:13:52PM +0200, Uwe Kleine-K?nig wrote:
> > Hello,
> > 
> > now that 3.5 is about to come I invested the time to update the
> > beginning of the Cortex-M3 support.
> > 
> > Over all I rebased to v3.5-rc5 and addressed the comments by Russell.
> > 
> > It would be great to get these patches into next early after the merge
> > window for 3.6 closes to get them into 3.7. But I won't argue if they
> > made it into 3.6 ;-)
> Now that v3.6-rc1 is out can these go into next for the next merge
> window?

Last time I looked at the code, patch 3/3 was adding some fairly noisy debug
prints to various syscalls and pieces of signal handling. e.g.:


diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 76cbb05..ea207df 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -102,6 +102,7 @@ int kernel_execve(const char *filename,
 	 * We were successful.  We won't be returning to our caller, but
 	 * instead to user space by manipulating the kernel stack.
 	 */
+	pr_info("we were successful\n");
 	asm(	"add	r0, %0, %1\n\t"
 		"mov	r1, %2\n\t"
 		"mov	r2, %3\n\t"


Can we drop these bits please?

Will


From u.kleine-koenig at pengutronix.de  Fri Aug  3 05:04:52 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 3 Aug 2012 11:04:52 +0200
Subject: kernel entry for thumb2-only cpus
Message-ID: <20120803090452.GE2626@pengutronix.de>

Hello,

in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have

	.arm
 THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
 THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
 THUMB( .thumb                  )       @ switch to Thumb now.
 THUMB(1:                       )

as first instructions at the entry point. This is a problem for
thumb2-only cpus (e.g. Cortex-M3).

Up to now I commented out the first three lines for the Cortex-M3 port.
What should we do about that. There are two possibilities I see:

 a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
    first three lines out if it is given.
 b) expect the bootloader to directly jump to the label 1.

The downside of a) is that a boot loader on a cpu that is capable to
execute the tradtional instructions would need to detect if the switch
to thumb is there or not and react accordingly. (In fact it needs to
distringuish three cases:

 - traditional kernel
 - thumb2 kernel with ARM entry
 - thumb2 kernel without ARM entry

.) So I think b) is the more sensible option in the long run.

What do you think?

If so I'd expand the comment with this expectation.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From Barry.Song at csr.com  Fri Aug  3 05:08:12 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 3 Aug 2012 17:08:12 +0800
Subject: [PATCH v3 2/2] clk: prima2: move from arch/arm/mach to drivers/clk
In-Reply-To: <1343984892-13776-1-git-send-email-Barry.Song@csr.com>
References: <1343984892-13776-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1343984892-13776-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Signed-off-by: Barry Song <Baohua.Song at csr.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
 -v3: rebase againest 3.6-rc1;

 arch/arm/mach-prima2/Makefile |    1 -
 arch/arm/mach-prima2/clock.c  | 1171 -----------------------------------------
 drivers/clk/Makefile          |    1 +
 drivers/clk/clk-sirf.c        | 1171 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 1172 insertions(+), 1172 deletions(-)
 delete mode 100644 arch/arm/mach-prima2/clock.c
 create mode 100644 drivers/clk/clk-sirf.c

diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd160..841847d 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,6 +1,5 @@
 obj-y := timer.o
 obj-y += irq.o
-obj-y += clock.o
 obj-y += rstc.o
 obj-y += prima2.o
 obj-y += rtciobrg.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
deleted file mode 100644
index 74b99c8..0000000
--- a/arch/arm/mach-prima2/clock.c
+++ /dev/null
@@ -1,1171 +0,0 @@
-/*
- * Clock tree for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/syscore_ops.h>
-
-#define SIRFSOC_CLKC_CLK_EN0    0x0000
-#define SIRFSOC_CLKC_CLK_EN1    0x0004
-#define SIRFSOC_CLKC_REF_CFG    0x0014
-#define SIRFSOC_CLKC_CPU_CFG    0x0018
-#define SIRFSOC_CLKC_MEM_CFG    0x001c
-#define SIRFSOC_CLKC_SYS_CFG    0x0020
-#define SIRFSOC_CLKC_IO_CFG     0x0024
-#define SIRFSOC_CLKC_DSP_CFG    0x0028
-#define SIRFSOC_CLKC_GFX_CFG    0x002c
-#define SIRFSOC_CLKC_MM_CFG     0x0030
-#define SIRFSOC_CLKC_LCD_CFG     0x0034
-#define SIRFSOC_CLKC_MMC_CFG    0x0038
-#define SIRFSOC_CLKC_PLL1_CFG0  0x0040
-#define SIRFSOC_CLKC_PLL2_CFG0  0x0044
-#define SIRFSOC_CLKC_PLL3_CFG0  0x0048
-#define SIRFSOC_CLKC_PLL1_CFG1  0x004c
-#define SIRFSOC_CLKC_PLL2_CFG1  0x0050
-#define SIRFSOC_CLKC_PLL3_CFG1  0x0054
-#define SIRFSOC_CLKC_PLL1_CFG2  0x0058
-#define SIRFSOC_CLKC_PLL2_CFG2  0x005c
-#define SIRFSOC_CLKC_PLL3_CFG2  0x0060
-#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
-#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
-#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
-#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)
-
-static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
-
-#define KHZ     1000
-#define MHZ     (KHZ * KHZ)
-
-/*
- * SiRFprimaII clock controller
- * - 2 oscillators: osc-26MHz, rtc-32.768KHz
- * - 3 standard configurable plls: pll1, pll2 & pll3
- * - 2 exclusive plls: usb phy pll and sata phy pll
- * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
- *     display and sdphy.
- *     Each clock domain can select its own clock source from five clock sources,
- *     X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
- *     clock of the group clock.
- *     - dsp domain: gps, mf
- *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
- *     - sys domain: security
- */
-
-struct clk_pll {
-	struct clk_hw hw;
-	unsigned short regofs;  /* register offset */
-};
-
-#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
-
-struct clk_dmn {
-	struct clk_hw hw;
-	signed char enable_bit; /* enable bit: 0 ~ 63 */
-	unsigned short regofs;  /* register offset */
-};
-
-#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
-
-struct clk_std {
-	struct clk_hw hw;
-	signed char enable_bit; /* enable bit: 0 ~ 63 */
-};
-
-#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
-
-static int std_clk_is_enabled(struct clk_hw *hw);
-static int std_clk_enable(struct clk_hw *hw);
-static void std_clk_disable(struct clk_hw *hw);
-
-static inline unsigned long clkc_readl(unsigned reg)
-{
-	return readl(sirfsoc_clk_vbase + reg);
-}
-
-static inline void clkc_writel(u32 val, unsigned reg)
-{
-	writel(val, sirfsoc_clk_vbase + reg);
-}
-
-/*
- * std pll
- */
-
-static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
-	unsigned long parent_rate)
-{
-	unsigned long fin = parent_rate;
-	struct clk_pll *clk = to_pllclk(hw);
-	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
-		SIRFSOC_CLKC_PLL1_CFG0;
-
-	if (clkc_readl(regcfg2) & BIT(2)) {
-		/* pll bypass mode */
-		return fin;
-	} else {
-		/* fout = fin * nf / nr / od */
-		u32 cfg0 = clkc_readl(clk->regofs);
-		u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
-		u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
-		u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
-		WARN_ON(fin % MHZ);
-		return fin / MHZ * nf / nr / od * MHZ;
-	}
-}
-
-static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-	unsigned long *parent_rate)
-{
-	unsigned long fin, nf, nr, od;
-
-	/*
-	 * fout = fin * nf / (nr * od);
-	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
-	 */
-	rate = rate - rate % MHZ;
-
-	nf = rate / MHZ;
-	if (nf > BIT(13))
-		nf = BIT(13);
-	if (nf < 1)
-		nf = 1;
-
-	fin = *parent_rate;
-
-	nr = fin / MHZ;
-	if (nr > BIT(6))
-		nr = BIT(6);
-	od = 1;
-
-	return fin * nf / (nr * od);
-}
-
-static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-	unsigned long parent_rate)
-{
-	struct clk_pll *clk = to_pllclk(hw);
-	unsigned long fin, nf, nr, od, reg;
-
-	/*
-	 * fout = fin * nf / (nr * od);
-	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
-	 */
-
-	nf = rate / MHZ;
-	if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
-		return -EINVAL;
-
-	fin = parent_rate;
-	BUG_ON(fin < MHZ);
-
-	nr = fin / MHZ;
-	BUG_ON((fin % MHZ) || nr > BIT(6));
-
-	od = 1;
-
-	reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
-	clkc_writel(reg, clk->regofs);
-
-	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
-	clkc_writel((nf >> 1) - 1, reg);
-
-	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
-	while (!(clkc_readl(reg) & BIT(6)))
-		cpu_relax();
-
-	return 0;
-}
-
-static struct clk_ops std_pll_ops = {
-	.recalc_rate = pll_clk_recalc_rate,
-	.round_rate = pll_clk_round_rate,
-	.set_rate = pll_clk_set_rate,
-};
-
-static const char *pll_clk_parents[] = {
-	"osc",
-};
-
-static struct clk_init_data clk_pll1_init = {
-	.name = "pll1",
-	.ops = &std_pll_ops,
-	.parent_names = pll_clk_parents,
-	.num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-static struct clk_init_data clk_pll2_init = {
-	.name = "pll2",
-	.ops = &std_pll_ops,
-	.parent_names = pll_clk_parents,
-	.num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-static struct clk_init_data clk_pll3_init = {
-	.name = "pll3",
-	.ops = &std_pll_ops,
-	.parent_names = pll_clk_parents,
-	.num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-static struct clk_pll clk_pll1 = {
-	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
-	.hw = {
-		.init = &clk_pll1_init,
-	},
-};
-
-static struct clk_pll clk_pll2 = {
-	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
-	.hw = {
-		.init = &clk_pll2_init,
-	},
-};
-
-static struct clk_pll clk_pll3 = {
-	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
-	.hw = {
-		.init = &clk_pll3_init,
-	},
-};
-
-/*
- * usb uses specified pll
- */
-
-static int usb_pll_clk_enable(struct clk_hw *hw)
-{
-	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
-	reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
-	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
-	while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
-			SIRFSOC_USBPHY_PLL_LOCK))
-		cpu_relax();
-
-	return 0;
-}
-
-static void usb_pll_clk_disable(struct clk_hw *clk)
-{
-	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
-	reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
-	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
-}
-
-static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-{
-	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
-	return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
-}
-
-static struct clk_ops usb_pll_ops = {
-	.enable = usb_pll_clk_enable,
-	.disable = usb_pll_clk_disable,
-	.recalc_rate = usb_pll_clk_recalc_rate,
-};
-
-static struct clk_init_data clk_usb_pll_init = {
-	.name = "usb_pll",
-	.ops = &usb_pll_ops,
-	.parent_names = pll_clk_parents,
-	.num_parents = ARRAY_SIZE(pll_clk_parents),
-};
-
-static struct clk_hw usb_pll_clk_hw = {
-	.init = &clk_usb_pll_init,
-};
-
-/*
- * clock domains - cpu, mem, sys/io, dsp, gfx
- */
-
-static const char *dmn_clk_parents[] = {
-	"rtc",
-	"osc",
-	"pll1",
-	"pll2",
-	"pll3",
-};
-
-static u8 dmn_clk_get_parent(struct clk_hw *hw)
-{
-	struct clk_dmn *clk = to_dmnclk(hw);
-	u32 cfg = clkc_readl(clk->regofs);
-
-	/* parent of io domain can only be pll3 */
-	if (strcmp(hw->init->name, "io") == 0)
-		return 4;
-
-	WARN_ON((cfg & (BIT(3) - 1)) > 4);
-
-	return cfg & (BIT(3) - 1);
-}
-
-static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
-{
-	struct clk_dmn *clk = to_dmnclk(hw);
-	u32 cfg = clkc_readl(clk->regofs);
-
-	/* parent of io domain can only be pll3 */
-	if (strcmp(hw->init->name, "io") == 0)
-		return -EINVAL;
-
-	cfg &= ~(BIT(3) - 1);
-	clkc_writel(cfg | parent, clk->regofs);
-	/* BIT(3) - switching status: 1 - busy, 0 - done */
-	while (clkc_readl(clk->regofs) & BIT(3))
-		cpu_relax();
-
-	return 0;
-}
-
-static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
-	unsigned long parent_rate)
-
-{
-	unsigned long fin = parent_rate;
-	struct clk_dmn *clk = to_dmnclk(hw);
-
-	u32 cfg = clkc_readl(clk->regofs);
-
-	if (cfg & BIT(24)) {
-		/* fcd bypass mode */
-		return fin;
-	} else {
-		/*
-		 * wait count: bit[19:16], hold count: bit[23:20]
-		 */
-		u32 wait = (cfg >> 16) & (BIT(4) - 1);
-		u32 hold = (cfg >> 20) & (BIT(4) - 1);
-
-		return fin / (wait + hold + 2);
-	}
-}
-
-static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
-	unsigned long *parent_rate)
-{
-	unsigned long fin;
-	unsigned ratio, wait, hold;
-	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
-
-	fin = *parent_rate;
-	ratio = fin / rate;
-
-	if (ratio < 2)
-		ratio = 2;
-	if (ratio > BIT(bits + 1))
-		ratio = BIT(bits + 1);
-
-	wait = (ratio >> 1) - 1;
-	hold = ratio - wait - 2;
-
-	return fin / (wait + hold + 2);
-}
-
-static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
-	unsigned long parent_rate)
-{
-	struct clk_dmn *clk = to_dmnclk(hw);
-	unsigned long fin;
-	unsigned ratio, wait, hold, reg;
-	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
-
-	fin = parent_rate;
-	ratio = fin / rate;
-
-	if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
-		return -EINVAL;
-
-	WARN_ON(fin % rate);
-
-	wait = (ratio >> 1) - 1;
-	hold = ratio - wait - 2;
-
-	reg = clkc_readl(clk->regofs);
-	reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
-	reg |= (wait << 16) | (hold << 20) | BIT(25);
-	clkc_writel(reg, clk->regofs);
-
-	/* waiting FCD been effective */
-	while (clkc_readl(clk->regofs) & BIT(25))
-		cpu_relax();
-
-	return 0;
-}
-
-static struct clk_ops msi_ops = {
-	.set_rate = dmn_clk_set_rate,
-	.round_rate = dmn_clk_round_rate,
-	.recalc_rate = dmn_clk_recalc_rate,
-	.set_parent = dmn_clk_set_parent,
-	.get_parent = dmn_clk_get_parent,
-};
-
-static struct clk_init_data clk_mem_init = {
-	.name = "mem",
-	.ops = &msi_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_mem = {
-	.regofs = SIRFSOC_CLKC_MEM_CFG,
-	.hw = {
-		.init = &clk_mem_init,
-	},
-};
-
-static struct clk_init_data clk_sys_init = {
-	.name = "sys",
-	.ops = &msi_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-	.flags = CLK_SET_RATE_GATE,
-};
-
-static struct clk_dmn clk_sys = {
-	.regofs = SIRFSOC_CLKC_SYS_CFG,
-	.hw = {
-		.init = &clk_sys_init,
-	},
-};
-
-static struct clk_init_data clk_io_init = {
-	.name = "io",
-	.ops = &msi_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_io = {
-	.regofs = SIRFSOC_CLKC_IO_CFG,
-	.hw = {
-		.init = &clk_io_init,
-	},
-};
-
-static struct clk_ops cpu_ops = {
-	.set_parent = dmn_clk_set_parent,
-	.get_parent = dmn_clk_get_parent,
-};
-
-static struct clk_init_data clk_cpu_init = {
-	.name = "cpu",
-	.ops = &cpu_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-	.flags = CLK_SET_RATE_PARENT,
-};
-
-static struct clk_dmn clk_cpu = {
-	.regofs = SIRFSOC_CLKC_CPU_CFG,
-	.hw = {
-		.init = &clk_cpu_init,
-	},
-};
-
-static struct clk_ops dmn_ops = {
-	.is_enabled = std_clk_is_enabled,
-	.enable = std_clk_enable,
-	.disable = std_clk_disable,
-	.set_rate = dmn_clk_set_rate,
-	.round_rate = dmn_clk_round_rate,
-	.recalc_rate = dmn_clk_recalc_rate,
-	.set_parent = dmn_clk_set_parent,
-	.get_parent = dmn_clk_get_parent,
-};
-
-/* dsp, gfx, mm, lcd and vpp domain */
-
-static struct clk_init_data clk_dsp_init = {
-	.name = "dsp",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_dsp = {
-	.regofs = SIRFSOC_CLKC_DSP_CFG,
-	.enable_bit = 0,
-	.hw = {
-		.init = &clk_dsp_init,
-	},
-};
-
-static struct clk_init_data clk_gfx_init = {
-	.name = "gfx",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_gfx = {
-	.regofs = SIRFSOC_CLKC_GFX_CFG,
-	.enable_bit = 8,
-	.hw = {
-		.init = &clk_gfx_init,
-	},
-};
-
-static struct clk_init_data clk_mm_init = {
-	.name = "mm",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_mm = {
-	.regofs = SIRFSOC_CLKC_MM_CFG,
-	.enable_bit = 9,
-	.hw = {
-		.init = &clk_mm_init,
-	},
-};
-
-static struct clk_init_data clk_lcd_init = {
-	.name = "lcd",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_lcd = {
-	.regofs = SIRFSOC_CLKC_LCD_CFG,
-	.enable_bit = 10,
-	.hw = {
-		.init = &clk_lcd_init,
-	},
-};
-
-static struct clk_init_data clk_vpp_init = {
-	.name = "vpp",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_vpp = {
-	.regofs = SIRFSOC_CLKC_LCD_CFG,
-	.enable_bit = 11,
-	.hw = {
-		.init = &clk_vpp_init,
-	},
-};
-
-static struct clk_init_data clk_mmc01_init = {
-	.name = "mmc01",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_mmc01 = {
-	.regofs = SIRFSOC_CLKC_MMC_CFG,
-	.enable_bit = 59,
-	.hw = {
-		.init = &clk_mmc01_init,
-	},
-};
-
-static struct clk_init_data clk_mmc23_init = {
-	.name = "mmc23",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_mmc23 = {
-	.regofs = SIRFSOC_CLKC_MMC_CFG,
-	.enable_bit = 60,
-	.hw = {
-		.init = &clk_mmc23_init,
-	},
-};
-
-static struct clk_init_data clk_mmc45_init = {
-	.name = "mmc45",
-	.ops = &dmn_ops,
-	.parent_names = dmn_clk_parents,
-	.num_parents = ARRAY_SIZE(dmn_clk_parents),
-};
-
-static struct clk_dmn clk_mmc45 = {
-	.regofs = SIRFSOC_CLKC_MMC_CFG,
-	.enable_bit = 61,
-	.hw = {
-		.init = &clk_mmc45_init,
-	},
-};
-
-/*
- * peripheral controllers in io domain
- */
-
-static int std_clk_is_enabled(struct clk_hw *hw)
-{
-	u32 reg;
-	int bit;
-	struct clk_std *clk = to_stdclk(hw);
-
-	bit = clk->enable_bit % 32;
-	reg = clk->enable_bit / 32;
-	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
-
-	return !!(clkc_readl(reg) & BIT(bit));
-}
-
-static int std_clk_enable(struct clk_hw *hw)
-{
-	u32 val, reg;
-	int bit;
-	struct clk_std *clk = to_stdclk(hw);
-
-	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
-
-	bit = clk->enable_bit % 32;
-	reg = clk->enable_bit / 32;
-	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
-
-	val = clkc_readl(reg) | BIT(bit);
-	clkc_writel(val, reg);
-	return 0;
-}
-
-static void std_clk_disable(struct clk_hw *hw)
-{
-	u32 val, reg;
-	int bit;
-	struct clk_std *clk = to_stdclk(hw);
-
-	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
-
-	bit = clk->enable_bit % 32;
-	reg = clk->enable_bit / 32;
-	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
-
-	val = clkc_readl(reg) & ~BIT(bit);
-	clkc_writel(val, reg);
-}
-
-static const char *std_clk_io_parents[] = {
-	"io",
-};
-
-static struct clk_ops ios_ops = {
-	.is_enabled = std_clk_is_enabled,
-	.enable = std_clk_enable,
-	.disable = std_clk_disable,
-};
-
-static struct clk_init_data clk_dmac0_init = {
-	.name = "dmac0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_dmac0 = {
-	.enable_bit = 32,
-	.hw = {
-		.init = &clk_dmac0_init,
-	},
-};
-
-static struct clk_init_data clk_dmac1_init = {
-	.name = "dmac1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_dmac1 = {
-	.enable_bit = 33,
-	.hw = {
-		.init = &clk_dmac1_init,
-	},
-};
-
-static struct clk_init_data clk_nand_init = {
-	.name = "nand",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_nand = {
-	.enable_bit = 34,
-	.hw = {
-		.init = &clk_nand_init,
-	},
-};
-
-static struct clk_init_data clk_audio_init = {
-	.name = "audio",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_audio = {
-	.enable_bit = 35,
-	.hw = {
-		.init = &clk_audio_init,
-	},
-};
-
-static struct clk_init_data clk_uart0_init = {
-	.name = "uart0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_uart0 = {
-	.enable_bit = 36,
-	.hw = {
-		.init = &clk_uart0_init,
-	},
-};
-
-static struct clk_init_data clk_uart1_init = {
-	.name = "uart1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_uart1 = {
-	.enable_bit = 37,
-	.hw = {
-		.init = &clk_uart1_init,
-	},
-};
-
-static struct clk_init_data clk_uart2_init = {
-	.name = "uart2",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_uart2 = {
-	.enable_bit = 38,
-	.hw = {
-		.init = &clk_uart2_init,
-	},
-};
-
-static struct clk_init_data clk_usp0_init = {
-	.name = "usp0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_usp0 = {
-	.enable_bit = 39,
-	.hw = {
-		.init = &clk_usp0_init,
-	},
-};
-
-static struct clk_init_data clk_usp1_init = {
-	.name = "usp1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_usp1 = {
-	.enable_bit = 40,
-	.hw = {
-		.init = &clk_usp1_init,
-	},
-};
-
-static struct clk_init_data clk_usp2_init = {
-	.name = "usp2",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_usp2 = {
-	.enable_bit = 41,
-	.hw = {
-		.init = &clk_usp2_init,
-	},
-};
-
-static struct clk_init_data clk_vip_init = {
-	.name = "vip",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_vip = {
-	.enable_bit = 39,
-	.hw = {
-		.init = &clk_vip_init,
-	},
-};
-
-static struct clk_init_data clk_spi0_init = {
-	.name = "spi0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_spi0 = {
-	.enable_bit = 43,
-	.hw = {
-		.init = &clk_spi0_init,
-	},
-};
-
-static struct clk_init_data clk_spi1_init = {
-	.name = "spi1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_spi1 = {
-	.enable_bit = 44,
-	.hw = {
-		.init = &clk_spi1_init,
-	},
-};
-
-static struct clk_init_data clk_tsc_init = {
-	.name = "tsc",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_tsc = {
-	.enable_bit = 45,
-	.hw = {
-		.init = &clk_tsc_init,
-	},
-};
-
-static struct clk_init_data clk_i2c0_init = {
-	.name = "i2c0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_i2c0 = {
-	.enable_bit = 46,
-	.hw = {
-		.init = &clk_i2c0_init,
-	},
-};
-
-static struct clk_init_data clk_i2c1_init = {
-	.name = "i2c1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_i2c1 = {
-	.enable_bit = 47,
-	.hw = {
-		.init = &clk_i2c1_init,
-	},
-};
-
-static struct clk_init_data clk_pwmc_init = {
-	.name = "pwmc",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_pwmc = {
-	.enable_bit = 48,
-	.hw = {
-		.init = &clk_pwmc_init,
-	},
-};
-
-static struct clk_init_data clk_efuse_init = {
-	.name = "efuse",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_efuse = {
-	.enable_bit = 49,
-	.hw = {
-		.init = &clk_efuse_init,
-	},
-};
-
-static struct clk_init_data clk_pulse_init = {
-	.name = "pulse",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_pulse = {
-	.enable_bit = 50,
-	.hw = {
-		.init = &clk_pulse_init,
-	},
-};
-
-static const char *std_clk_dsp_parents[] = {
-	"dsp",
-};
-
-static struct clk_init_data clk_gps_init = {
-	.name = "gps",
-	.ops = &ios_ops,
-	.parent_names = std_clk_dsp_parents,
-	.num_parents = ARRAY_SIZE(std_clk_dsp_parents),
-};
-
-static struct clk_std clk_gps = {
-	.enable_bit = 1,
-	.hw = {
-		.init = &clk_gps_init,
-	},
-};
-
-static struct clk_init_data clk_mf_init = {
-	.name = "mf",
-	.ops = &ios_ops,
-	.parent_names = std_clk_io_parents,
-	.num_parents = ARRAY_SIZE(std_clk_io_parents),
-};
-
-static struct clk_std clk_mf = {
-	.enable_bit = 2,
-	.hw = {
-		.init = &clk_mf_init,
-	},
-};
-
-static const char *std_clk_sys_parents[] = {
-	"sys",
-};
-
-static struct clk_init_data clk_security_init = {
-	.name = "mf",
-	.ops = &ios_ops,
-	.parent_names = std_clk_sys_parents,
-	.num_parents = ARRAY_SIZE(std_clk_sys_parents),
-};
-
-static struct clk_std clk_security = {
-	.enable_bit = 19,
-	.hw = {
-		.init = &clk_security_init,
-	},
-};
-
-static const char *std_clk_usb_parents[] = {
-	"usb_pll",
-};
-
-static struct clk_init_data clk_usb0_init = {
-	.name = "usb0",
-	.ops = &ios_ops,
-	.parent_names = std_clk_usb_parents,
-	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
-};
-
-static struct clk_std clk_usb0 = {
-	.enable_bit = 16,
-	.hw = {
-		.init = &clk_usb0_init,
-	},
-};
-
-static struct clk_init_data clk_usb1_init = {
-	.name = "usb1",
-	.ops = &ios_ops,
-	.parent_names = std_clk_usb_parents,
-	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
-};
-
-static struct clk_std clk_usb1 = {
-	.enable_bit = 17,
-	.hw = {
-		.init = &clk_usb1_init,
-	},
-};
-
-static struct of_device_id clkc_ids[] = {
-	{ .compatible = "sirf,prima2-clkc" },
-	{},
-};
-
-static struct of_device_id rsc_ids[] = {
-	{ .compatible = "sirf,prima2-rsc" },
-	{},
-};
-
-void __init sirfsoc_of_clk_init(void)
-{
-	struct clk *clk;
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, clkc_ids);
-	if (!np)
-		panic("unable to find compatible clkc node in dtb\n");
-
-	sirfsoc_clk_vbase = of_iomap(np, 0);
-	if (!sirfsoc_clk_vbase)
-		panic("unable to map clkc registers\n");
-
-	of_node_put(np);
-
-	np = of_find_matching_node(NULL, rsc_ids);
-	if (!np)
-		panic("unable to find compatible rsc node in dtb\n");
-
-	sirfsoc_rsc_vbase = of_iomap(np, 0);
-	if (!sirfsoc_rsc_vbase)
-		panic("unable to map rsc registers\n");
-
-	of_node_put(np);
-
-
-	/* These are always available (RTC and 26MHz OSC)*/
-	clk = clk_register_fixed_rate(NULL, "rtc", NULL,
-		CLK_IS_ROOT, 32768);
-	BUG_ON(!clk);
-	clk = clk_register_fixed_rate(NULL, "osc", NULL,
-		CLK_IS_ROOT, 26000000);
-	BUG_ON(!clk);
-
-	clk = clk_register(NULL, &clk_pll1.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_pll2.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_pll3.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_mem.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_sys.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_security.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b8030000.security");
-	clk = clk_register(NULL, &clk_dsp.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_gps.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "a8010000.gps");
-	clk = clk_register(NULL, &clk_mf.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_io.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "io");
-	clk = clk_register(NULL, &clk_cpu.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "cpu");
-	clk = clk_register(NULL, &clk_uart0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0050000.uart");
-	clk = clk_register(NULL, &clk_uart1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0060000.uart");
-	clk = clk_register(NULL, &clk_uart2.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0070000.uart");
-	clk = clk_register(NULL, &clk_tsc.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0110000.tsc");
-	clk = clk_register(NULL, &clk_i2c0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00e0000.i2c");
-	clk = clk_register(NULL, &clk_i2c1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00f0000.i2c");
-	clk = clk_register(NULL, &clk_spi0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00d0000.spi");
-	clk = clk_register(NULL, &clk_spi1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0170000.spi");
-	clk = clk_register(NULL, &clk_pwmc.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0130000.pwm");
-	clk = clk_register(NULL, &clk_efuse.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0140000.efusesys");
-	clk = clk_register(NULL, &clk_pulse.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0150000.pulsec");
-	clk = clk_register(NULL, &clk_dmac0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
-	clk = clk_register(NULL, &clk_dmac1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
-	clk = clk_register(NULL, &clk_nand.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0030000.nand");
-	clk = clk_register(NULL, &clk_audio.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0040000.audio");
-	clk = clk_register(NULL, &clk_usp0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0080000.usp");
-	clk = clk_register(NULL, &clk_usp1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b0090000.usp");
-	clk = clk_register(NULL, &clk_usp2.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00a0000.usp");
-	clk = clk_register(NULL, &clk_vip.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00c0000.vip");
-	clk = clk_register(NULL, &clk_gfx.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "98000000.graphics");
-	clk = clk_register(NULL, &clk_mm.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "a0000000.multimedia");
-	clk = clk_register(NULL, &clk_lcd.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "90010000.display");
-	clk = clk_register(NULL, &clk_vpp.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "90020000.vpp");
-	clk = clk_register(NULL, &clk_mmc01.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_mmc23.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_mmc45.hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &usb_pll_clk_hw);
-	BUG_ON(!clk);
-	clk = clk_register(NULL, &clk_usb0.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00e0000.usb");
-	clk = clk_register(NULL, &clk_usb1.hw);
-	BUG_ON(!clk);
-	clk_register_clkdev(clk, NULL, "b00f0000.usb");
-}
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..614fed3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_ARCH_PRIMA2)      += clk-sirf.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-sirf.c b/drivers/clk/clk-sirf.c
new file mode 100644
index 0000000..74b99c8
--- /dev/null
+++ b/drivers/clk/clk-sirf.c
@@ -0,0 +1,1171 @@
+/*
+ * Clock tree for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#define SIRFSOC_CLKC_CLK_EN0    0x0000
+#define SIRFSOC_CLKC_CLK_EN1    0x0004
+#define SIRFSOC_CLKC_REF_CFG    0x0014
+#define SIRFSOC_CLKC_CPU_CFG    0x0018
+#define SIRFSOC_CLKC_MEM_CFG    0x001c
+#define SIRFSOC_CLKC_SYS_CFG    0x0020
+#define SIRFSOC_CLKC_IO_CFG     0x0024
+#define SIRFSOC_CLKC_DSP_CFG    0x0028
+#define SIRFSOC_CLKC_GFX_CFG    0x002c
+#define SIRFSOC_CLKC_MM_CFG     0x0030
+#define SIRFSOC_CLKC_LCD_CFG     0x0034
+#define SIRFSOC_CLKC_MMC_CFG    0x0038
+#define SIRFSOC_CLKC_PLL1_CFG0  0x0040
+#define SIRFSOC_CLKC_PLL2_CFG0  0x0044
+#define SIRFSOC_CLKC_PLL3_CFG0  0x0048
+#define SIRFSOC_CLKC_PLL1_CFG1  0x004c
+#define SIRFSOC_CLKC_PLL2_CFG1  0x0050
+#define SIRFSOC_CLKC_PLL3_CFG1  0x0054
+#define SIRFSOC_CLKC_PLL1_CFG2  0x0058
+#define SIRFSOC_CLKC_PLL2_CFG2  0x005c
+#define SIRFSOC_CLKC_PLL3_CFG2  0x0060
+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
+#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
+#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
+#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)
+
+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
+
+#define KHZ     1000
+#define MHZ     (KHZ * KHZ)
+
+/*
+ * SiRFprimaII clock controller
+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
+ * - 3 standard configurable plls: pll1, pll2 & pll3
+ * - 2 exclusive plls: usb phy pll and sata phy pll
+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
+ *     display and sdphy.
+ *     Each clock domain can select its own clock source from five clock sources,
+ *     X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
+ *     clock of the group clock.
+ *     - dsp domain: gps, mf
+ *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
+ *     - sys domain: security
+ */
+
+struct clk_pll {
+	struct clk_hw hw;
+	unsigned short regofs;  /* register offset */
+};
+
+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
+
+struct clk_dmn {
+	struct clk_hw hw;
+	signed char enable_bit; /* enable bit: 0 ~ 63 */
+	unsigned short regofs;  /* register offset */
+};
+
+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
+
+struct clk_std {
+	struct clk_hw hw;
+	signed char enable_bit; /* enable bit: 0 ~ 63 */
+};
+
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw);
+static int std_clk_enable(struct clk_hw *hw);
+static void std_clk_disable(struct clk_hw *hw);
+
+static inline unsigned long clkc_readl(unsigned reg)
+{
+	return readl(sirfsoc_clk_vbase + reg);
+}
+
+static inline void clkc_writel(u32 val, unsigned reg)
+{
+	writel(val, sirfsoc_clk_vbase + reg);
+}
+
+/*
+ * std pll
+ */
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
+{
+	unsigned long fin = parent_rate;
+	struct clk_pll *clk = to_pllclk(hw);
+	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
+		SIRFSOC_CLKC_PLL1_CFG0;
+
+	if (clkc_readl(regcfg2) & BIT(2)) {
+		/* pll bypass mode */
+		return fin;
+	} else {
+		/* fout = fin * nf / nr / od */
+		u32 cfg0 = clkc_readl(clk->regofs);
+		u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
+		u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
+		u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
+		WARN_ON(fin % MHZ);
+		return fin / MHZ * nf / nr / od * MHZ;
+	}
+}
+
+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin, nf, nr, od;
+
+	/*
+	 * fout = fin * nf / (nr * od);
+	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
+	 */
+	rate = rate - rate % MHZ;
+
+	nf = rate / MHZ;
+	if (nf > BIT(13))
+		nf = BIT(13);
+	if (nf < 1)
+		nf = 1;
+
+	fin = *parent_rate;
+
+	nr = fin / MHZ;
+	if (nr > BIT(6))
+		nr = BIT(6);
+	od = 1;
+
+	return fin * nf / (nr * od);
+}
+
+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
+{
+	struct clk_pll *clk = to_pllclk(hw);
+	unsigned long fin, nf, nr, od, reg;
+
+	/*
+	 * fout = fin * nf / (nr * od);
+	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
+	 */
+
+	nf = rate / MHZ;
+	if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
+		return -EINVAL;
+
+	fin = parent_rate;
+	BUG_ON(fin < MHZ);
+
+	nr = fin / MHZ;
+	BUG_ON((fin % MHZ) || nr > BIT(6));
+
+	od = 1;
+
+	reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
+	clkc_writel(reg, clk->regofs);
+
+	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
+	clkc_writel((nf >> 1) - 1, reg);
+
+	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
+	while (!(clkc_readl(reg) & BIT(6)))
+		cpu_relax();
+
+	return 0;
+}
+
+static struct clk_ops std_pll_ops = {
+	.recalc_rate = pll_clk_recalc_rate,
+	.round_rate = pll_clk_round_rate,
+	.set_rate = pll_clk_set_rate,
+};
+
+static const char *pll_clk_parents[] = {
+	"osc",
+};
+
+static struct clk_init_data clk_pll1_init = {
+	.name = "pll1",
+	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll2_init = {
+	.name = "pll2",
+	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll3_init = {
+	.name = "pll3",
+	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_pll clk_pll1 = {
+	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
+	.hw = {
+		.init = &clk_pll1_init,
+	},
+};
+
+static struct clk_pll clk_pll2 = {
+	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
+	.hw = {
+		.init = &clk_pll2_init,
+	},
+};
+
+static struct clk_pll clk_pll3 = {
+	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
+	.hw = {
+		.init = &clk_pll3_init,
+	},
+};
+
+/*
+ * usb uses specified pll
+ */
+
+static int usb_pll_clk_enable(struct clk_hw *hw)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
+			SIRFSOC_USBPHY_PLL_LOCK))
+		cpu_relax();
+
+	return 0;
+}
+
+static void usb_pll_clk_disable(struct clk_hw *clk)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+}
+
+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
+}
+
+static struct clk_ops usb_pll_ops = {
+	.enable = usb_pll_clk_enable,
+	.disable = usb_pll_clk_disable,
+	.recalc_rate = usb_pll_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_usb_pll_init = {
+	.name = "usb_pll",
+	.ops = &usb_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw usb_pll_clk_hw = {
+	.init = &clk_usb_pll_init,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io, dsp, gfx
+ */
+
+static const char *dmn_clk_parents[] = {
+	"rtc",
+	"osc",
+	"pll1",
+	"pll2",
+	"pll3",
+};
+
+static u8 dmn_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_dmn *clk = to_dmnclk(hw);
+	u32 cfg = clkc_readl(clk->regofs);
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return 4;
+
+	WARN_ON((cfg & (BIT(3) - 1)) > 4);
+
+	return cfg & (BIT(3) - 1);
+}
+
+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
+{
+	struct clk_dmn *clk = to_dmnclk(hw);
+	u32 cfg = clkc_readl(clk->regofs);
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return -EINVAL;
+
+	cfg &= ~(BIT(3) - 1);
+	clkc_writel(cfg | parent, clk->regofs);
+	/* BIT(3) - switching status: 1 - busy, 0 - done */
+	while (clkc_readl(clk->regofs) & BIT(3))
+		cpu_relax();
+
+	return 0;
+}
+
+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
+
+{
+	unsigned long fin = parent_rate;
+	struct clk_dmn *clk = to_dmnclk(hw);
+
+	u32 cfg = clkc_readl(clk->regofs);
+
+	if (cfg & BIT(24)) {
+		/* fcd bypass mode */
+		return fin;
+	} else {
+		/*
+		 * wait count: bit[19:16], hold count: bit[23:20]
+		 */
+		u32 wait = (cfg >> 16) & (BIT(4) - 1);
+		u32 hold = (cfg >> 20) & (BIT(4) - 1);
+
+		return fin / (wait + hold + 2);
+	}
+}
+
+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin;
+	unsigned ratio, wait, hold;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+	fin = *parent_rate;
+	ratio = fin / rate;
+
+	if (ratio < 2)
+		ratio = 2;
+	if (ratio > BIT(bits + 1))
+		ratio = BIT(bits + 1);
+
+	wait = (ratio >> 1) - 1;
+	hold = ratio - wait - 2;
+
+	return fin / (wait + hold + 2);
+}
+
+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
+{
+	struct clk_dmn *clk = to_dmnclk(hw);
+	unsigned long fin;
+	unsigned ratio, wait, hold, reg;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+	fin = parent_rate;
+	ratio = fin / rate;
+
+	if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
+		return -EINVAL;
+
+	WARN_ON(fin % rate);
+
+	wait = (ratio >> 1) - 1;
+	hold = ratio - wait - 2;
+
+	reg = clkc_readl(clk->regofs);
+	reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
+	reg |= (wait << 16) | (hold << 20) | BIT(25);
+	clkc_writel(reg, clk->regofs);
+
+	/* waiting FCD been effective */
+	while (clkc_readl(clk->regofs) & BIT(25))
+		cpu_relax();
+
+	return 0;
+}
+
+static struct clk_ops msi_ops = {
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_mem_init = {
+	.name = "mem",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mem = {
+	.regofs = SIRFSOC_CLKC_MEM_CFG,
+	.hw = {
+		.init = &clk_mem_init,
+	},
+};
+
+static struct clk_init_data clk_sys_init = {
+	.name = "sys",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_GATE,
+};
+
+static struct clk_dmn clk_sys = {
+	.regofs = SIRFSOC_CLKC_SYS_CFG,
+	.hw = {
+		.init = &clk_sys_init,
+	},
+};
+
+static struct clk_init_data clk_io_init = {
+	.name = "io",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_io = {
+	.regofs = SIRFSOC_CLKC_IO_CFG,
+	.hw = {
+		.init = &clk_io_init,
+	},
+};
+
+static struct clk_ops cpu_ops = {
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_cpu_init = {
+	.name = "cpu",
+	.ops = &cpu_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_PARENT,
+};
+
+static struct clk_dmn clk_cpu = {
+	.regofs = SIRFSOC_CLKC_CPU_CFG,
+	.hw = {
+		.init = &clk_cpu_init,
+	},
+};
+
+static struct clk_ops dmn_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
+};
+
+/* dsp, gfx, mm, lcd and vpp domain */
+
+static struct clk_init_data clk_dsp_init = {
+	.name = "dsp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_dsp = {
+	.regofs = SIRFSOC_CLKC_DSP_CFG,
+	.enable_bit = 0,
+	.hw = {
+		.init = &clk_dsp_init,
+	},
+};
+
+static struct clk_init_data clk_gfx_init = {
+	.name = "gfx",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_gfx = {
+	.regofs = SIRFSOC_CLKC_GFX_CFG,
+	.enable_bit = 8,
+	.hw = {
+		.init = &clk_gfx_init,
+	},
+};
+
+static struct clk_init_data clk_mm_init = {
+	.name = "mm",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mm = {
+	.regofs = SIRFSOC_CLKC_MM_CFG,
+	.enable_bit = 9,
+	.hw = {
+		.init = &clk_mm_init,
+	},
+};
+
+static struct clk_init_data clk_lcd_init = {
+	.name = "lcd",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_lcd = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 10,
+	.hw = {
+		.init = &clk_lcd_init,
+	},
+};
+
+static struct clk_init_data clk_vpp_init = {
+	.name = "vpp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_vpp = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 11,
+	.hw = {
+		.init = &clk_vpp_init,
+	},
+};
+
+static struct clk_init_data clk_mmc01_init = {
+	.name = "mmc01",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc01 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 59,
+	.hw = {
+		.init = &clk_mmc01_init,
+	},
+};
+
+static struct clk_init_data clk_mmc23_init = {
+	.name = "mmc23",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc23 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 60,
+	.hw = {
+		.init = &clk_mmc23_init,
+	},
+};
+
+static struct clk_init_data clk_mmc45_init = {
+	.name = "mmc45",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc45 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 61,
+	.hw = {
+		.init = &clk_mmc45_init,
+	},
+};
+
+/*
+ * peripheral controllers in io domain
+ */
+
+static int std_clk_is_enabled(struct clk_hw *hw)
+{
+	u32 reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
+
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+	return !!(clkc_readl(reg) & BIT(bit));
+}
+
+static int std_clk_enable(struct clk_hw *hw)
+{
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
+
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+	val = clkc_readl(reg) | BIT(bit);
+	clkc_writel(val, reg);
+	return 0;
+}
+
+static void std_clk_disable(struct clk_hw *hw)
+{
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
+
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+	val = clkc_readl(reg) & ~BIT(bit);
+	clkc_writel(val, reg);
+}
+
+static const char *std_clk_io_parents[] = {
+	"io",
+};
+
+static struct clk_ops ios_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+};
+
+static struct clk_init_data clk_dmac0_init = {
+	.name = "dmac0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac0 = {
+	.enable_bit = 32,
+	.hw = {
+		.init = &clk_dmac0_init,
+	},
+};
+
+static struct clk_init_data clk_dmac1_init = {
+	.name = "dmac1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac1 = {
+	.enable_bit = 33,
+	.hw = {
+		.init = &clk_dmac1_init,
+	},
+};
+
+static struct clk_init_data clk_nand_init = {
+	.name = "nand",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_nand = {
+	.enable_bit = 34,
+	.hw = {
+		.init = &clk_nand_init,
+	},
+};
+
+static struct clk_init_data clk_audio_init = {
+	.name = "audio",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_audio = {
+	.enable_bit = 35,
+	.hw = {
+		.init = &clk_audio_init,
+	},
+};
+
+static struct clk_init_data clk_uart0_init = {
+	.name = "uart0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart0 = {
+	.enable_bit = 36,
+	.hw = {
+		.init = &clk_uart0_init,
+	},
+};
+
+static struct clk_init_data clk_uart1_init = {
+	.name = "uart1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart1 = {
+	.enable_bit = 37,
+	.hw = {
+		.init = &clk_uart1_init,
+	},
+};
+
+static struct clk_init_data clk_uart2_init = {
+	.name = "uart2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart2 = {
+	.enable_bit = 38,
+	.hw = {
+		.init = &clk_uart2_init,
+	},
+};
+
+static struct clk_init_data clk_usp0_init = {
+	.name = "usp0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp0 = {
+	.enable_bit = 39,
+	.hw = {
+		.init = &clk_usp0_init,
+	},
+};
+
+static struct clk_init_data clk_usp1_init = {
+	.name = "usp1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp1 = {
+	.enable_bit = 40,
+	.hw = {
+		.init = &clk_usp1_init,
+	},
+};
+
+static struct clk_init_data clk_usp2_init = {
+	.name = "usp2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp2 = {
+	.enable_bit = 41,
+	.hw = {
+		.init = &clk_usp2_init,
+	},
+};
+
+static struct clk_init_data clk_vip_init = {
+	.name = "vip",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_vip = {
+	.enable_bit = 39,
+	.hw = {
+		.init = &clk_vip_init,
+	},
+};
+
+static struct clk_init_data clk_spi0_init = {
+	.name = "spi0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi0 = {
+	.enable_bit = 43,
+	.hw = {
+		.init = &clk_spi0_init,
+	},
+};
+
+static struct clk_init_data clk_spi1_init = {
+	.name = "spi1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi1 = {
+	.enable_bit = 44,
+	.hw = {
+		.init = &clk_spi1_init,
+	},
+};
+
+static struct clk_init_data clk_tsc_init = {
+	.name = "tsc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_tsc = {
+	.enable_bit = 45,
+	.hw = {
+		.init = &clk_tsc_init,
+	},
+};
+
+static struct clk_init_data clk_i2c0_init = {
+	.name = "i2c0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c0 = {
+	.enable_bit = 46,
+	.hw = {
+		.init = &clk_i2c0_init,
+	},
+};
+
+static struct clk_init_data clk_i2c1_init = {
+	.name = "i2c1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c1 = {
+	.enable_bit = 47,
+	.hw = {
+		.init = &clk_i2c1_init,
+	},
+};
+
+static struct clk_init_data clk_pwmc_init = {
+	.name = "pwmc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pwmc = {
+	.enable_bit = 48,
+	.hw = {
+		.init = &clk_pwmc_init,
+	},
+};
+
+static struct clk_init_data clk_efuse_init = {
+	.name = "efuse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_efuse = {
+	.enable_bit = 49,
+	.hw = {
+		.init = &clk_efuse_init,
+	},
+};
+
+static struct clk_init_data clk_pulse_init = {
+	.name = "pulse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pulse = {
+	.enable_bit = 50,
+	.hw = {
+		.init = &clk_pulse_init,
+	},
+};
+
+static const char *std_clk_dsp_parents[] = {
+	"dsp",
+};
+
+static struct clk_init_data clk_gps_init = {
+	.name = "gps",
+	.ops = &ios_ops,
+	.parent_names = std_clk_dsp_parents,
+	.num_parents = ARRAY_SIZE(std_clk_dsp_parents),
+};
+
+static struct clk_std clk_gps = {
+	.enable_bit = 1,
+	.hw = {
+		.init = &clk_gps_init,
+	},
+};
+
+static struct clk_init_data clk_mf_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_mf = {
+	.enable_bit = 2,
+	.hw = {
+		.init = &clk_mf_init,
+	},
+};
+
+static const char *std_clk_sys_parents[] = {
+	"sys",
+};
+
+static struct clk_init_data clk_security_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_sys_parents,
+	.num_parents = ARRAY_SIZE(std_clk_sys_parents),
+};
+
+static struct clk_std clk_security = {
+	.enable_bit = 19,
+	.hw = {
+		.init = &clk_security_init,
+	},
+};
+
+static const char *std_clk_usb_parents[] = {
+	"usb_pll",
+};
+
+static struct clk_init_data clk_usb0_init = {
+	.name = "usb0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb0 = {
+	.enable_bit = 16,
+	.hw = {
+		.init = &clk_usb0_init,
+	},
+};
+
+static struct clk_init_data clk_usb1_init = {
+	.name = "usb1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb1 = {
+	.enable_bit = 17,
+	.hw = {
+		.init = &clk_usb1_init,
+	},
+};
+
+static struct of_device_id clkc_ids[] = {
+	{ .compatible = "sirf,prima2-clkc" },
+	{},
+};
+
+static struct of_device_id rsc_ids[] = {
+	{ .compatible = "sirf,prima2-rsc" },
+	{},
+};
+
+void __init sirfsoc_of_clk_init(void)
+{
+	struct clk *clk;
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, clkc_ids);
+	if (!np)
+		panic("unable to find compatible clkc node in dtb\n");
+
+	sirfsoc_clk_vbase = of_iomap(np, 0);
+	if (!sirfsoc_clk_vbase)
+		panic("unable to map clkc registers\n");
+
+	of_node_put(np);
+
+	np = of_find_matching_node(NULL, rsc_ids);
+	if (!np)
+		panic("unable to find compatible rsc node in dtb\n");
+
+	sirfsoc_rsc_vbase = of_iomap(np, 0);
+	if (!sirfsoc_rsc_vbase)
+		panic("unable to map rsc registers\n");
+
+	of_node_put(np);
+
+
+	/* These are always available (RTC and 26MHz OSC)*/
+	clk = clk_register_fixed_rate(NULL, "rtc", NULL,
+		CLK_IS_ROOT, 32768);
+	BUG_ON(!clk);
+	clk = clk_register_fixed_rate(NULL, "osc", NULL,
+		CLK_IS_ROOT, 26000000);
+	BUG_ON(!clk);
+
+	clk = clk_register(NULL, &clk_pll1.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll2.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll3.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mem.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_sys.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_security.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b8030000.security");
+	clk = clk_register(NULL, &clk_dsp.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_gps.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a8010000.gps");
+	clk = clk_register(NULL, &clk_mf.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_io.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "io");
+	clk = clk_register(NULL, &clk_cpu.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "cpu");
+	clk = clk_register(NULL, &clk_uart0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0050000.uart");
+	clk = clk_register(NULL, &clk_uart1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0060000.uart");
+	clk = clk_register(NULL, &clk_uart2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0070000.uart");
+	clk = clk_register(NULL, &clk_tsc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0110000.tsc");
+	clk = clk_register(NULL, &clk_i2c0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.i2c");
+	clk = clk_register(NULL, &clk_i2c1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.i2c");
+	clk = clk_register(NULL, &clk_spi0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00d0000.spi");
+	clk = clk_register(NULL, &clk_spi1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0170000.spi");
+	clk = clk_register(NULL, &clk_pwmc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0130000.pwm");
+	clk = clk_register(NULL, &clk_efuse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0140000.efusesys");
+	clk = clk_register(NULL, &clk_pulse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0150000.pulsec");
+	clk = clk_register(NULL, &clk_dmac0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
+	clk = clk_register(NULL, &clk_dmac1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
+	clk = clk_register(NULL, &clk_nand.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0030000.nand");
+	clk = clk_register(NULL, &clk_audio.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0040000.audio");
+	clk = clk_register(NULL, &clk_usp0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0080000.usp");
+	clk = clk_register(NULL, &clk_usp1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0090000.usp");
+	clk = clk_register(NULL, &clk_usp2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00a0000.usp");
+	clk = clk_register(NULL, &clk_vip.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00c0000.vip");
+	clk = clk_register(NULL, &clk_gfx.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "98000000.graphics");
+	clk = clk_register(NULL, &clk_mm.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a0000000.multimedia");
+	clk = clk_register(NULL, &clk_lcd.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90010000.display");
+	clk = clk_register(NULL, &clk_vpp.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90020000.vpp");
+	clk = clk_register(NULL, &clk_mmc01.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc23.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc45.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &usb_pll_clk_hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_usb0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.usb");
+	clk = clk_register(NULL, &clk_usb1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.usb");
+}
-- 
1.7.1



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From Barry.Song at csr.com  Fri Aug  3 05:08:11 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 3 Aug 2012 17:08:11 +0800
Subject: [PATCH v3 1/2] ARM: PRIMA2: convert to common clk and finish full clk
 tree
Message-ID: <1343984892-13776-1-git-send-email-Barry.Song@csr.com>

From: Binghua Duan <Binghua.Duan at csr.com>

Commit 02c981c07bc95ac1e only implements a little part of primaII clk tree
due to common clk framework was not ready at that time.
This patch converts the old driver to common clk and finish the full clk
tree.

Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v3: rebase againest 3.6-rc1;

 arch/arm/Kconfig              |    2 +-
 arch/arm/mach-prima2/clock.c  | 1189 ++++++++++++++++++++++++++++++++---------
 arch/arm/mach-prima2/prima2.c |    1 -
 arch/arm/mach-prima2/timer.c  |    8 +-
 4 files changed, 933 insertions(+), 267 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..2cd53e4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -419,7 +419,7 @@ config ARCH_PRIMA2
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
+	select COMMON_CLK
 	select GENERIC_IRQ_CHIP
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index aebad7e..74b99c8 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -8,16 +8,12 @@
 
 #include <linux/module.h>
 #include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
 #include <linux/io.h>
-#include <linux/clkdev.h>
 #include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/of_address.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
+#include <linux/syscore_ops.h>
 
 #define SIRFSOC_CLKC_CLK_EN0    0x0000
 #define SIRFSOC_CLKC_CLK_EN1    0x0004
@@ -29,7 +25,7 @@
 #define SIRFSOC_CLKC_DSP_CFG    0x0028
 #define SIRFSOC_CLKC_GFX_CFG    0x002c
 #define SIRFSOC_CLKC_MM_CFG     0x0030
-#define SIRFSOC_LKC_LCD_CFG     0x0034
+#define SIRFSOC_CLKC_LCD_CFG     0x0034
 #define SIRFSOC_CLKC_MMC_CFG    0x0038
 #define SIRFSOC_CLKC_PLL1_CFG0  0x0040
 #define SIRFSOC_CLKC_PLL2_CFG0  0x0044
@@ -40,68 +36,82 @@
 #define SIRFSOC_CLKC_PLL1_CFG2  0x0058
 #define SIRFSOC_CLKC_PLL2_CFG2  0x005c
 #define SIRFSOC_CLKC_PLL3_CFG2  0x0060
+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
+#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
+#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
+#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)
 
-#define SIRFSOC_CLOCK_VA_BASE		SIRFSOC_VA(0x005000)
+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
 
 #define KHZ     1000
 #define MHZ     (KHZ * KHZ)
 
-struct clk_ops {
-	unsigned long (*get_rate)(struct clk *clk);
-	long (*round_rate)(struct clk *clk, unsigned long rate);
-	int (*set_rate)(struct clk *clk, unsigned long rate);
-	int (*enable)(struct clk *clk);
-	int (*disable)(struct clk *clk);
-	struct clk *(*get_parent)(struct clk *clk);
-	int (*set_parent)(struct clk *clk, struct clk *parent);
+/*
+ * SiRFprimaII clock controller
+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
+ * - 3 standard configurable plls: pll1, pll2 & pll3
+ * - 2 exclusive plls: usb phy pll and sata phy pll
+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
+ *     display and sdphy.
+ *     Each clock domain can select its own clock source from five clock sources,
+ *     X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
+ *     clock of the group clock.
+ *     - dsp domain: gps, mf
+ *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
+ *     - sys domain: security
+ */
+
+struct clk_pll {
+	struct clk_hw hw;
+	unsigned short regofs;  /* register offset */
 };
 
-struct clk {
-	struct clk *parent;     /* parent clk */
-	unsigned long rate;     /* clock rate in Hz */
-	signed char usage;      /* clock enable count */
+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
+
+struct clk_dmn {
+	struct clk_hw hw;
 	signed char enable_bit; /* enable bit: 0 ~ 63 */
 	unsigned short regofs;  /* register offset */
-	struct clk_ops *ops;    /* clock operation */
 };
 
-static DEFINE_SPINLOCK(clocks_lock);
+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
+
+struct clk_std {
+	struct clk_hw hw;
+	signed char enable_bit; /* enable bit: 0 ~ 63 */
+};
+
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw);
+static int std_clk_enable(struct clk_hw *hw);
+static void std_clk_disable(struct clk_hw *hw);
 
 static inline unsigned long clkc_readl(unsigned reg)
 {
-	return readl(SIRFSOC_CLOCK_VA_BASE + reg);
+	return readl(sirfsoc_clk_vbase + reg);
 }
 
 static inline void clkc_writel(u32 val, unsigned reg)
 {
-	writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
+	writel(val, sirfsoc_clk_vbase + reg);
 }
 
 /*
- * osc_rtc - real time oscillator - 32.768KHz
- * osc_sys - high speed oscillator - 26MHz
- */
-
-static struct clk clk_rtc = {
-	.rate = 32768,
-};
-
-static struct clk clk_osc = {
-	.rate = 26 * MHZ,
-};
-
-/*
  * std pll
  */
-static unsigned long std_pll_get_rate(struct clk *clk)
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
 {
-	unsigned long fin = clk_get_rate(clk->parent);
+	unsigned long fin = parent_rate;
+	struct clk_pll *clk = to_pllclk(hw);
 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
 		SIRFSOC_CLKC_PLL1_CFG0;
 
 	if (clkc_readl(regcfg2) & BIT(2)) {
 		/* pll bypass mode */
-		clk->rate = fin;
+		return fin;
 	} else {
 		/* fout = fin * nf / nr / od */
 		u32 cfg0 = clkc_readl(clk->regofs);
@@ -109,14 +119,41 @@ static unsigned long std_pll_get_rate(struct clk *clk)
 		u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
 		u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
 		WARN_ON(fin % MHZ);
-		clk->rate = fin / MHZ * nf / nr / od * MHZ;
+		return fin / MHZ * nf / nr / od * MHZ;
 	}
+}
+
+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin, nf, nr, od;
+
+	/*
+	 * fout = fin * nf / (nr * od);
+	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
+	 */
+	rate = rate - rate % MHZ;
+
+	nf = rate / MHZ;
+	if (nf > BIT(13))
+		nf = BIT(13);
+	if (nf < 1)
+		nf = 1;
 
-	return clk->rate;
+	fin = *parent_rate;
+
+	nr = fin / MHZ;
+	if (nr > BIT(6))
+		nr = BIT(6);
+	od = 1;
+
+	return fin * nf / (nr * od);
 }
 
-static int std_pll_set_rate(struct clk *clk, unsigned long rate)
+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
 {
+	struct clk_pll *clk = to_pllclk(hw);
 	unsigned long fin, nf, nr, od, reg;
 
 	/*
@@ -128,7 +165,7 @@ static int std_pll_set_rate(struct clk *clk, unsigned long rate)
 	if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
 		return -EINVAL;
 
-	fin = clk_get_rate(clk->parent);
+	fin = parent_rate;
 	BUG_ON(fin < MHZ);
 
 	nr = fin / MHZ;
@@ -146,76 +183,163 @@ static int std_pll_set_rate(struct clk *clk, unsigned long rate)
 	while (!(clkc_readl(reg) & BIT(6)))
 		cpu_relax();
 
-	clk->rate = 0; /* set to zero will force recalculation */
 	return 0;
 }
 
 static struct clk_ops std_pll_ops = {
-	.get_rate = std_pll_get_rate,
-	.set_rate = std_pll_set_rate,
+	.recalc_rate = pll_clk_recalc_rate,
+	.round_rate = pll_clk_round_rate,
+	.set_rate = pll_clk_set_rate,
 };
 
-static struct clk clk_pll1 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
+static const char *pll_clk_parents[] = {
+	"osc",
+};
+
+static struct clk_init_data clk_pll1_init = {
+	.name = "pll1",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
 };
 
-static struct clk clk_pll2 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
+static struct clk_init_data clk_pll2_init = {
+	.name = "pll2",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
 };
 
-static struct clk clk_pll3 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
+static struct clk_init_data clk_pll3_init = {
+	.name = "pll3",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_pll clk_pll1 = {
+	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
+	.hw = {
+		.init = &clk_pll1_init,
+	},
+};
+
+static struct clk_pll clk_pll2 = {
+	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
+	.hw = {
+		.init = &clk_pll2_init,
+	},
+};
+
+static struct clk_pll clk_pll3 = {
+	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
+	.hw = {
+		.init = &clk_pll3_init,
+	},
 };
 
 /*
- * clock domains - cpu, mem, sys/io
+ * usb uses specified pll
  */
 
-static struct clk clk_mem;
+static int usb_pll_clk_enable(struct clk_hw *hw)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
+			SIRFSOC_USBPHY_PLL_LOCK))
+		cpu_relax();
+
+	return 0;
+}
+
+static void usb_pll_clk_disable(struct clk_hw *clk)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+}
 
-static struct clk *dmn_get_parent(struct clk *clk)
+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
-	struct clk *clks[] = {
-		&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-	};
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
+}
+
+static struct clk_ops usb_pll_ops = {
+	.enable = usb_pll_clk_enable,
+	.disable = usb_pll_clk_disable,
+	.recalc_rate = usb_pll_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_usb_pll_init = {
+	.name = "usb_pll",
+	.ops = &usb_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw usb_pll_clk_hw = {
+	.init = &clk_usb_pll_init,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io, dsp, gfx
+ */
+
+static const char *dmn_clk_parents[] = {
+	"rtc",
+	"osc",
+	"pll1",
+	"pll2",
+	"pll3",
+};
+
+static u8 dmn_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_dmn *clk = to_dmnclk(hw);
 	u32 cfg = clkc_readl(clk->regofs);
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return 4;
+
 	WARN_ON((cfg & (BIT(3) - 1)) > 4);
-	return clks[cfg & (BIT(3) - 1)];
+
+	return cfg & (BIT(3) - 1);
 }
 
-static int dmn_set_parent(struct clk *clk, struct clk *parent)
+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
 {
-	const struct clk *clks[] = {
-		&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-	};
+	struct clk_dmn *clk = to_dmnclk(hw);
 	u32 cfg = clkc_readl(clk->regofs);
-	int i;
-	for (i = 0; i < ARRAY_SIZE(clks); i++) {
-		if (clks[i] == parent) {
-			cfg &= ~(BIT(3) - 1);
-			clkc_writel(cfg | i, clk->regofs);
-			/* BIT(3) - switching status: 1 - busy, 0 - done */
-			while (clkc_readl(clk->regofs) & BIT(3))
-				cpu_relax();
-			return 0;
-		}
-	}
-	return -EINVAL;
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return -EINVAL;
+
+	cfg &= ~(BIT(3) - 1);
+	clkc_writel(cfg | parent, clk->regofs);
+	/* BIT(3) - switching status: 1 - busy, 0 - done */
+	while (clkc_readl(clk->regofs) & BIT(3))
+		cpu_relax();
+
+	return 0;
 }
 
-static unsigned long dmn_get_rate(struct clk *clk)
+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
+
 {
-	unsigned long fin = clk_get_rate(clk->parent);
+	unsigned long fin = parent_rate;
+	struct clk_dmn *clk = to_dmnclk(hw);
+
 	u32 cfg = clkc_readl(clk->regofs);
+
 	if (cfg & BIT(24)) {
 		/* fcd bypass mode */
-		clk->rate = fin;
+		return fin;
 	} else {
 		/*
 		 * wait count: bit[19:16], hold count: bit[23:20]
@@ -223,19 +347,40 @@ static unsigned long dmn_get_rate(struct clk *clk)
 		u32 wait = (cfg >> 16) & (BIT(4) - 1);
 		u32 hold = (cfg >> 20) & (BIT(4) - 1);
 
-		clk->rate = fin / (wait + hold + 2);
+		return fin / (wait + hold + 2);
 	}
+}
+
+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin;
+	unsigned ratio, wait, hold;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+	fin = *parent_rate;
+	ratio = fin / rate;
+
+	if (ratio < 2)
+		ratio = 2;
+	if (ratio > BIT(bits + 1))
+		ratio = BIT(bits + 1);
 
-	return clk->rate;
+	wait = (ratio >> 1) - 1;
+	hold = ratio - wait - 2;
+
+	return fin / (wait + hold + 2);
 }
 
-static int dmn_set_rate(struct clk *clk, unsigned long rate)
+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
 {
+	struct clk_dmn *clk = to_dmnclk(hw);
 	unsigned long fin;
 	unsigned ratio, wait, hold, reg;
-	unsigned bits = (clk == &clk_mem) ? 3 : 4;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
 
-	fin = clk_get_rate(clk->parent);
+	fin = parent_rate;
 	ratio = fin / rate;
 
 	if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
@@ -255,256 +400,772 @@ static int dmn_set_rate(struct clk *clk, unsigned long rate)
 	while (clkc_readl(clk->regofs) & BIT(25))
 		cpu_relax();
 
-	clk->rate = 0; /* set to zero will force recalculation */
-
 	return 0;
 }
 
-/*
- * cpu clock has no FCD register in Prima2, can only change pll
- */
-static int cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret1, ret2;
-	struct clk *cur_parent, *tmp_parent;
+static struct clk_ops msi_ops = {
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
+};
 
-	cur_parent = dmn_get_parent(clk);
-	BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
+static struct clk_init_data clk_mem_init = {
+	.name = "mem",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	/* switch to tmp pll before setting parent clock's rate */
-	tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
-	ret1 = dmn_set_parent(clk, tmp_parent);
-	BUG_ON(ret1);
+static struct clk_dmn clk_mem = {
+	.regofs = SIRFSOC_CLKC_MEM_CFG,
+	.hw = {
+		.init = &clk_mem_init,
+	},
+};
 
-	ret2 = clk_set_rate(cur_parent, rate);
+static struct clk_init_data clk_sys_init = {
+	.name = "sys",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_GATE,
+};
 
-	ret1 = dmn_set_parent(clk, cur_parent);
+static struct clk_dmn clk_sys = {
+	.regofs = SIRFSOC_CLKC_SYS_CFG,
+	.hw = {
+		.init = &clk_sys_init,
+	},
+};
 
-	clk->rate = 0; /* set to zero will force recalculation */
+static struct clk_init_data clk_io_init = {
+	.name = "io",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	return ret2 ? ret2 : ret1;
-}
+static struct clk_dmn clk_io = {
+	.regofs = SIRFSOC_CLKC_IO_CFG,
+	.hw = {
+		.init = &clk_io_init,
+	},
+};
 
 static struct clk_ops cpu_ops = {
-	.get_parent = dmn_get_parent,
-	.set_parent = dmn_set_parent,
-	.set_rate = cpu_set_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
 };
 
-static struct clk clk_cpu = {
-	.parent = &clk_pll1,
-	.regofs = SIRFSOC_CLKC_CPU_CFG,
+static struct clk_init_data clk_cpu_init = {
+	.name = "cpu",
 	.ops = &cpu_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_PARENT,
 };
 
+static struct clk_dmn clk_cpu = {
+	.regofs = SIRFSOC_CLKC_CPU_CFG,
+	.hw = {
+		.init = &clk_cpu_init,
+	},
+};
 
-static struct clk_ops msi_ops = {
-	.set_rate = dmn_set_rate,
-	.get_rate = dmn_get_rate,
-	.set_parent = dmn_set_parent,
-	.get_parent = dmn_get_parent,
+static struct clk_ops dmn_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
 };
 
-static struct clk clk_mem = {
-	.parent = &clk_pll2,
-	.regofs = SIRFSOC_CLKC_MEM_CFG,
-	.ops = &msi_ops,
+/* dsp, gfx, mm, lcd and vpp domain */
+
+static struct clk_init_data clk_dsp_init = {
+	.name = "dsp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
 };
 
-static struct clk clk_sys = {
-	.parent = &clk_pll3,
-	.regofs = SIRFSOC_CLKC_SYS_CFG,
-	.ops = &msi_ops,
+static struct clk_dmn clk_dsp = {
+	.regofs = SIRFSOC_CLKC_DSP_CFG,
+	.enable_bit = 0,
+	.hw = {
+		.init = &clk_dsp_init,
+	},
 };
 
-static struct clk clk_io = {
-	.parent = &clk_pll3,
-	.regofs = SIRFSOC_CLKC_IO_CFG,
-	.ops = &msi_ops,
+static struct clk_init_data clk_gfx_init = {
+	.name = "gfx",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
 };
 
-/*
- * on-chip clock sets
- */
-static struct clk_lookup onchip_clks[] = {
-	{
-		.dev_id = "rtc",
-		.clk = &clk_rtc,
-	}, {
-		.dev_id = "osc",
-		.clk = &clk_osc,
-	}, {
-		.dev_id = "pll1",
-		.clk = &clk_pll1,
-	}, {
-		.dev_id = "pll2",
-		.clk = &clk_pll2,
-	}, {
-		.dev_id = "pll3",
-		.clk = &clk_pll3,
-	}, {
-		.dev_id = "cpu",
-		.clk = &clk_cpu,
-	}, {
-		.dev_id = "mem",
-		.clk = &clk_mem,
-	}, {
-		.dev_id = "sys",
-		.clk = &clk_sys,
-	}, {
-		.dev_id = "io",
-		.clk = &clk_io,
-	},
-};
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
+static struct clk_dmn clk_gfx = {
+	.regofs = SIRFSOC_CLKC_GFX_CFG,
+	.enable_bit = 8,
+	.hw = {
+		.init = &clk_gfx_init,
+	},
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+static struct clk_init_data clk_mm_init = {
+	.name = "mm",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->parent)
-		clk_enable(clk->parent);
+static struct clk_dmn clk_mm = {
+	.regofs = SIRFSOC_CLKC_MM_CFG,
+	.enable_bit = 9,
+	.hw = {
+		.init = &clk_mm_init,
+	},
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (!clk->usage++ && clk->ops && clk->ops->enable)
-		clk->ops->enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
+static struct clk_init_data clk_lcd_init = {
+	.name = "lcd",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
+static struct clk_dmn clk_lcd = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 10,
+	.hw = {
+		.init = &clk_lcd_init,
+	},
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return;
+static struct clk_init_data clk_vpp_init = {
+	.name = "vpp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	WARN_ON(!clk->usage);
+static struct clk_dmn clk_vpp = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 11,
+	.hw = {
+		.init = &clk_vpp_init,
+	},
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (--clk->usage == 0 && clk->ops && clk->ops->disable)
-		clk->ops->disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
+static struct clk_init_data clk_mmc01_init = {
+	.name = "mmc01",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->parent)
-		clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
+static struct clk_dmn clk_mmc01 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 59,
+	.hw = {
+		.init = &clk_mmc01_init,
+	},
+};
 
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return 0;
+static struct clk_init_data clk_mmc23_init = {
+	.name = "mmc23",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->rate)
-		return clk->rate;
+static struct clk_dmn clk_mmc23 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 60,
+	.hw = {
+		.init = &clk_mmc23_init,
+	},
+};
 
-	if (clk->ops && clk->ops->get_rate)
-		return clk->ops->get_rate(clk);
+static struct clk_init_data clk_mmc45_init = {
+	.name = "mmc45",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
+static struct clk_dmn clk_mmc45 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 61,
+	.hw = {
+		.init = &clk_mmc45_init,
+	},
+};
 
-long clk_round_rate(struct clk *clk, unsigned long rate)
+/*
+ * peripheral controllers in io domain
+ */
+
+static int std_clk_is_enabled(struct clk_hw *hw)
 {
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return 0;
+	u32 reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (clk->ops && clk->ops->round_rate)
-		return clk->ops->round_rate(clk, rate);
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	return 0;
+	return !!(clkc_readl(reg) & BIT(bit));
 }
-EXPORT_SYMBOL(clk_round_rate);
 
-int clk_set_rate(struct clk *clk, unsigned long rate)
+static int std_clk_enable(struct clk_hw *hw)
 {
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (!clk->ops || !clk->ops->set_rate)
-		return -EINVAL;
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	return clk->ops->set_rate(clk, rate);
+	val = clkc_readl(reg) | BIT(bit);
+	clkc_writel(val, reg);
+	return 0;
 }
-EXPORT_SYMBOL(clk_set_rate);
 
-int clk_set_parent(struct clk *clk, struct clk *parent)
+static void std_clk_disable(struct clk_hw *hw)
 {
-	int ret;
-	unsigned long flags;
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
 
-	if (!clk->ops || !clk->ops->set_parent)
-		return -EINVAL;
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	ret = clk->ops->set_parent(clk, parent);
-	if (!ret) {
-		parent->usage += clk->usage;
-		clk->parent->usage -= clk->usage;
-		BUG_ON(clk->parent->usage < 0);
-		clk->parent = parent;
-	}
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return ret;
+	val = clkc_readl(reg) & ~BIT(bit);
+	clkc_writel(val, reg);
 }
-EXPORT_SYMBOL(clk_set_parent);
 
-struct clk *clk_get_parent(struct clk *clk)
-{
-	unsigned long flags;
+static const char *std_clk_io_parents[] = {
+	"io",
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return NULL;
+static struct clk_ops ios_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+};
 
-	if (!clk->ops || !clk->ops->get_parent)
-		return clk->parent;
+static struct clk_init_data clk_dmac0_init = {
+	.name = "dmac0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	clk->parent = clk->ops->get_parent(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
+static struct clk_std clk_dmac0 = {
+	.enable_bit = 32,
+	.hw = {
+		.init = &clk_dmac0_init,
+	},
+};
 
-static void __init sirfsoc_clk_init(void)
-{
-	clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
-}
+static struct clk_init_data clk_dmac1_init = {
+	.name = "dmac1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac1 = {
+	.enable_bit = 33,
+	.hw = {
+		.init = &clk_dmac1_init,
+	},
+};
+
+static struct clk_init_data clk_nand_init = {
+	.name = "nand",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_nand = {
+	.enable_bit = 34,
+	.hw = {
+		.init = &clk_nand_init,
+	},
+};
+
+static struct clk_init_data clk_audio_init = {
+	.name = "audio",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_audio = {
+	.enable_bit = 35,
+	.hw = {
+		.init = &clk_audio_init,
+	},
+};
+
+static struct clk_init_data clk_uart0_init = {
+	.name = "uart0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart0 = {
+	.enable_bit = 36,
+	.hw = {
+		.init = &clk_uart0_init,
+	},
+};
+
+static struct clk_init_data clk_uart1_init = {
+	.name = "uart1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart1 = {
+	.enable_bit = 37,
+	.hw = {
+		.init = &clk_uart1_init,
+	},
+};
+
+static struct clk_init_data clk_uart2_init = {
+	.name = "uart2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart2 = {
+	.enable_bit = 38,
+	.hw = {
+		.init = &clk_uart2_init,
+	},
+};
+
+static struct clk_init_data clk_usp0_init = {
+	.name = "usp0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp0 = {
+	.enable_bit = 39,
+	.hw = {
+		.init = &clk_usp0_init,
+	},
+};
+
+static struct clk_init_data clk_usp1_init = {
+	.name = "usp1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp1 = {
+	.enable_bit = 40,
+	.hw = {
+		.init = &clk_usp1_init,
+	},
+};
+
+static struct clk_init_data clk_usp2_init = {
+	.name = "usp2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp2 = {
+	.enable_bit = 41,
+	.hw = {
+		.init = &clk_usp2_init,
+	},
+};
+
+static struct clk_init_data clk_vip_init = {
+	.name = "vip",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_vip = {
+	.enable_bit = 39,
+	.hw = {
+		.init = &clk_vip_init,
+	},
+};
+
+static struct clk_init_data clk_spi0_init = {
+	.name = "spi0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi0 = {
+	.enable_bit = 43,
+	.hw = {
+		.init = &clk_spi0_init,
+	},
+};
+
+static struct clk_init_data clk_spi1_init = {
+	.name = "spi1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi1 = {
+	.enable_bit = 44,
+	.hw = {
+		.init = &clk_spi1_init,
+	},
+};
+
+static struct clk_init_data clk_tsc_init = {
+	.name = "tsc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_tsc = {
+	.enable_bit = 45,
+	.hw = {
+		.init = &clk_tsc_init,
+	},
+};
+
+static struct clk_init_data clk_i2c0_init = {
+	.name = "i2c0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c0 = {
+	.enable_bit = 46,
+	.hw = {
+		.init = &clk_i2c0_init,
+	},
+};
+
+static struct clk_init_data clk_i2c1_init = {
+	.name = "i2c1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c1 = {
+	.enable_bit = 47,
+	.hw = {
+		.init = &clk_i2c1_init,
+	},
+};
+
+static struct clk_init_data clk_pwmc_init = {
+	.name = "pwmc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pwmc = {
+	.enable_bit = 48,
+	.hw = {
+		.init = &clk_pwmc_init,
+	},
+};
+
+static struct clk_init_data clk_efuse_init = {
+	.name = "efuse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_efuse = {
+	.enable_bit = 49,
+	.hw = {
+		.init = &clk_efuse_init,
+	},
+};
+
+static struct clk_init_data clk_pulse_init = {
+	.name = "pulse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pulse = {
+	.enable_bit = 50,
+	.hw = {
+		.init = &clk_pulse_init,
+	},
+};
+
+static const char *std_clk_dsp_parents[] = {
+	"dsp",
+};
+
+static struct clk_init_data clk_gps_init = {
+	.name = "gps",
+	.ops = &ios_ops,
+	.parent_names = std_clk_dsp_parents,
+	.num_parents = ARRAY_SIZE(std_clk_dsp_parents),
+};
+
+static struct clk_std clk_gps = {
+	.enable_bit = 1,
+	.hw = {
+		.init = &clk_gps_init,
+	},
+};
+
+static struct clk_init_data clk_mf_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_mf = {
+	.enable_bit = 2,
+	.hw = {
+		.init = &clk_mf_init,
+	},
+};
+
+static const char *std_clk_sys_parents[] = {
+	"sys",
+};
+
+static struct clk_init_data clk_security_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_sys_parents,
+	.num_parents = ARRAY_SIZE(std_clk_sys_parents),
+};
+
+static struct clk_std clk_security = {
+	.enable_bit = 19,
+	.hw = {
+		.init = &clk_security_init,
+	},
+};
+
+static const char *std_clk_usb_parents[] = {
+	"usb_pll",
+};
+
+static struct clk_init_data clk_usb0_init = {
+	.name = "usb0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb0 = {
+	.enable_bit = 16,
+	.hw = {
+		.init = &clk_usb0_init,
+	},
+};
+
+static struct clk_init_data clk_usb1_init = {
+	.name = "usb1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb1 = {
+	.enable_bit = 17,
+	.hw = {
+		.init = &clk_usb1_init,
+	},
+};
 
 static struct of_device_id clkc_ids[] = {
 	{ .compatible = "sirf,prima2-clkc" },
 	{},
 };
 
+static struct of_device_id rsc_ids[] = {
+	{ .compatible = "sirf,prima2-rsc" },
+	{},
+};
+
 void __init sirfsoc_of_clk_init(void)
 {
+	struct clk *clk;
 	struct device_node *np;
-	struct resource res;
-	struct map_desc sirfsoc_clkc_iodesc = {
-		.virtual = SIRFSOC_CLOCK_VA_BASE,
-		.type    = MT_DEVICE,
-	};
 
 	np = of_find_matching_node(NULL, clkc_ids);
 	if (!np)
 		panic("unable to find compatible clkc node in dtb\n");
 
-	if (of_address_to_resource(np, 0, &res))
-		panic("unable to find clkc range in dtb");
+	sirfsoc_clk_vbase = of_iomap(np, 0);
+	if (!sirfsoc_clk_vbase)
+		panic("unable to map clkc registers\n");
+
 	of_node_put(np);
 
-	sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
-	sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
+	np = of_find_matching_node(NULL, rsc_ids);
+	if (!np)
+		panic("unable to find compatible rsc node in dtb\n");
+
+	sirfsoc_rsc_vbase = of_iomap(np, 0);
+	if (!sirfsoc_rsc_vbase)
+		panic("unable to map rsc registers\n");
+
+	of_node_put(np);
 
-	iotable_init(&sirfsoc_clkc_iodesc, 1);
 
-	sirfsoc_clk_init();
+	/* These are always available (RTC and 26MHz OSC)*/
+	clk = clk_register_fixed_rate(NULL, "rtc", NULL,
+		CLK_IS_ROOT, 32768);
+	BUG_ON(!clk);
+	clk = clk_register_fixed_rate(NULL, "osc", NULL,
+		CLK_IS_ROOT, 26000000);
+	BUG_ON(!clk);
+
+	clk = clk_register(NULL, &clk_pll1.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll2.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll3.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mem.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_sys.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_security.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b8030000.security");
+	clk = clk_register(NULL, &clk_dsp.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_gps.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a8010000.gps");
+	clk = clk_register(NULL, &clk_mf.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_io.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "io");
+	clk = clk_register(NULL, &clk_cpu.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "cpu");
+	clk = clk_register(NULL, &clk_uart0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0050000.uart");
+	clk = clk_register(NULL, &clk_uart1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0060000.uart");
+	clk = clk_register(NULL, &clk_uart2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0070000.uart");
+	clk = clk_register(NULL, &clk_tsc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0110000.tsc");
+	clk = clk_register(NULL, &clk_i2c0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.i2c");
+	clk = clk_register(NULL, &clk_i2c1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.i2c");
+	clk = clk_register(NULL, &clk_spi0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00d0000.spi");
+	clk = clk_register(NULL, &clk_spi1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0170000.spi");
+	clk = clk_register(NULL, &clk_pwmc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0130000.pwm");
+	clk = clk_register(NULL, &clk_efuse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0140000.efusesys");
+	clk = clk_register(NULL, &clk_pulse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0150000.pulsec");
+	clk = clk_register(NULL, &clk_dmac0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
+	clk = clk_register(NULL, &clk_dmac1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
+	clk = clk_register(NULL, &clk_nand.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0030000.nand");
+	clk = clk_register(NULL, &clk_audio.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0040000.audio");
+	clk = clk_register(NULL, &clk_usp0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0080000.usp");
+	clk = clk_register(NULL, &clk_usp1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0090000.usp");
+	clk = clk_register(NULL, &clk_usp2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00a0000.usp");
+	clk = clk_register(NULL, &clk_vip.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00c0000.vip");
+	clk = clk_register(NULL, &clk_gfx.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "98000000.graphics");
+	clk = clk_register(NULL, &clk_mm.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a0000000.multimedia");
+	clk = clk_register(NULL, &clk_lcd.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90010000.display");
+	clk = clk_register(NULL, &clk_vpp.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90020000.vpp");
+	clk = clk_register(NULL, &clk_mmc01.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc23.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc45.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &usb_pll_clk_hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_usb0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.usb");
+	clk = clk_register(NULL, &clk_usb1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.usb");
 }
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index 8f0429d..e9a17ae 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -38,7 +38,6 @@ static const char *prima2cb_dt_match[] __initdata = {
 MACHINE_START(PRIMA2_EVB, "prima2cb")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.atag_offset	= 0x100,
-	.init_early     = sirfsoc_of_clk_init,
 	.map_io         = sirfsoc_map_lluart,
 	.init_irq	= sirfsoc_of_irq_init,
 	.timer		= &sirfsoc_timer,
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107..d95bf25 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+
 #define SIRFSOC_TIMER_COUNTER_LO	0x0000
 #define SIRFSOC_TIMER_COUNTER_HI	0x0004
 #define SIRFSOC_TIMER_MATCH_0		0x0008
@@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
 static void __init sirfsoc_timer_init(void)
 {
 	unsigned long rate;
+	struct clk *clk;
+
+	/* initialize clocking early, we want to set the OS timer */
+	sirfsoc_of_clk_init();
 
 	/* timer's input clock is io clock */
-	struct clk *clk = clk_get_sys("io", NULL);
+	clk = clk_get_sys("io", NULL);
 
 	BUG_ON(IS_ERR(clk));
 
-- 
1.7.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From nsekhar at ti.com  Fri Aug  3 05:09:32 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 3 Aug 2012 14:39:32 +0530
Subject: [alsa-devel] DT support for Davinci ASoC platform
In-Reply-To: <501AE3C6.8040708@gmail.com>
References: <1BAFE6F6C881BF42822005164F1491C33EA35352@DBDE01.ent.ti.com>
 <4FF5733E.6000604@gmail.com> <501AE3C6.8040708@gmail.com>
Message-ID: <501B954C.3070606@ti.com>

Hi Daniel,

On 8/3/2012 2:02 AM, Daniel Mack wrote:
> On 05.07.2012 12:58, Daniel Mack wrote:
>> Hi Gururaja,
>>
>> On 04.07.2012 14:48, Hebbar, Gururaja wrote:
>>> All,
>>>
>>> Are there any plans or work going on for providing Device Tree Support for Davinci
>>> ASoC?
>>>
>>> I am planning to add DT support for TI AM335x (McASP) and I don't want to do duplicate
>>> task.
>>
>> That's good to know. But isn't there a dependency on the EDMA engine? Is
>> that part ported yet?
> 
> May I ask whether you made any progress on that yet?

Matt Porter from TI is working on DMA engine migration. This would still
be some time away since there is a bunch of work involved here.

To make progress on Audio DT conversion Gururaja is doing an up port of
AM335x EDMA support from TI release to mainline kernel. If you are
interested in it, he can probably share that with you once he posts his
DT patches.

Thanks,
Sekhar


From hvaibhav at ti.com  Fri Aug  3 05:14:10 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 3 Aug 2012 14:44:10 +0530
Subject: [PATCH v2 1/2] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <50114069.7070605@mvista.com>
References: <1343219012-19472-1-git-send-email-anilkumar@ti.com>
 <1343219012-19472-2-git-send-email-anilkumar@ti.com>
 <500FE9FC.7070303@mvista.com> <501101A7.2030503@gmail.com>
 <50114069.7070605@mvista.com>
Message-ID: <501B9662.6000406@ti.com>



On 7/26/2012 6:34 PM, Sergei Shtylyov wrote:
> Hello.
> 
> On 26-07-2012 12:36, Daniel Mack wrote:
> 
>>>> Add Bosch D_CAN controller device tree data to AM33XX dtsi file
>>>> by adding d_can device node with all the necessary parameters.
> 
>>>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>>>> ---
>>>>    arch/arm/boot/dts/am33xx.dtsi |    5 +++++
>>>>    1 file changed, 5 insertions(+)
> 
>>>> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
>>>> index 9b974dc..2db2ffb 100644
>>>> --- a/arch/arm/boot/dts/am33xx.dtsi
>>>> +++ b/arch/arm/boot/dts/am33xx.dtsi
>>>> @@ -163,5 +163,10 @@
>>>>    			#size-cells = <0>;
>>>>    			ti,hwmods = "i2c3";
>>>>    		};
>>>> +
>>>> +		dcan1: d_can at 481D0000 {
>>>
>>>      Address postfix in the node name and no "reg" property?
> 
>> This still works due to the hwmod mappings OMAP relies on.
> 
>     I.e. the "reg" property is populated in runtime?
> 
>> I would still
>> put it there, so the switch to real DT definitions will be less painful.
> 
>     How it helps anything?
> 

This is required field if you want to use "of_dev_auxdata", without
"reg" property OF layer fails to create dev_id (name) bindings with what
you have specified as part of "of_dev_auxdata".

And with respect to CAN driver, even though we are using hwmod, I would
want to create dev_id = d_can.0 and d_can.1. And this is only possible
if Address and compatible string matches.

So this field is important and required in this case.

Thanks,
Vaibhav


From santosh.shilimkar at ti.com  Fri Aug  3 05:27:19 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 3 Aug 2012 14:57:19 +0530
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
Message-ID: <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>

On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>
> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>
>>
>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>>
>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>>>> that can handle events for both cpus.  This timer is used as the broadcast
>>>> clock-event when the per-cpu timer hardware stop in low power states.
>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>>>> set the irq to allow the clockevent core to determine the affinity of the
>>>> timer.
>>>
>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>>> breaks boot on my AM33xx board.
>>>
>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>>> below. With the entire series reverted, everything works again as
>>> expected. Any idea?
>>>
>>> The upstream commit ids are
>>>
>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>>> both cpus"
>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>>
>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>
> To answer my own question: No, the reverts aren't needed if you disable cpuidle.

This is really strange since CPUIDLE code is really OMAP4 specific.
obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o

May be omap2plus build some how the code gets executed on AMXX

Can you try below and see if the boot with CPUIDLE enabled goes away on
AMXX

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174..195e756 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;

+       if (!cpu_is_omap44xx())
+               return -ENODEV;
+
        if (omap_rev() == OMAP4430_REV_ES1_0) {
                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
                return -ENODEV;
Regards
Ssantosh


From hvaibhav at ti.com  Fri Aug  3 05:31:50 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 09:31:50 +0000
Subject: am33xx: default to status = "disabled"?
In-Reply-To: <201208022328.17095.arnd@arndb.de>
References: <501B061A.6080008@gmail.com> <201208022328.17095.arnd@arndb.de>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F557@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 04:58:16, Arnd Bergmann wrote:
> On Thursday 02 August 2012, Daniel Mack wrote:
> > currently, all devices in arch/arm/boot/dts/am33xx.dtsi are enabled by
> > default. However, depending on the actual board dts, only some of the
> > devices should actually be initialized, given that they only make sense
> > if their pins are actually wired on the board.
> > 
> > On other platform, such devices are marked with status = "disabled", and
> > the board files re-enable those they really use by overriding that
> > status again. That approach seems to make sense - shouldn't the same be
> > done in am33xx.dtsi or am I missing something?
> 
> I agree, they should be disabled, at least the serial ports, and probably
> also the i2c controllers.
> 

You are right, it needs to be disabled. I will create a patch and submit it.

Thanks,
Vaibhav




From u.kleine-koenig at pengutronix.de  Fri Aug  3 05:32:54 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 3 Aug 2012 11:32:54 +0200
Subject: [PATCH v5 0/3] Updated Cortex-M3 series
In-Reply-To: <20120803090235.GA26925@mudshark.cambridge.arm.com>
References: <1341512035-8173-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803075807.GD2626@pengutronix.de>
 <20120803090235.GA26925@mudshark.cambridge.arm.com>
Message-ID: <20120803093254.GF2626@pengutronix.de>

Hello Will,

On Fri, Aug 03, 2012 at 10:02:35AM +0100, Will Deacon wrote:
> On Fri, Aug 03, 2012 at 08:58:07AM +0100, Uwe Kleine-K?nig wrote:
> > On Thu, Jul 05, 2012 at 08:13:52PM +0200, Uwe Kleine-K?nig wrote:
> > > Hello,
> > > 
> > > now that 3.5 is about to come I invested the time to update the
> > > beginning of the Cortex-M3 support.
> > > 
> > > Over all I rebased to v3.5-rc5 and addressed the comments by Russell.
> > > 
> > > It would be great to get these patches into next early after the merge
> > > window for 3.6 closes to get them into 3.7. But I won't argue if they
> > > made it into 3.6 ;-)
> > Now that v3.6-rc1 is out can these go into next for the next merge
> > window?
> 
> Last time I looked at the code, patch 3/3 was adding some fairly noisy debug
> prints to various syscalls and pieces of signal handling. e.g.:
> 
> 
> diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
> index 76cbb05..ea207df 100644
> --- a/arch/arm/kernel/sys_arm.c
> +++ b/arch/arm/kernel/sys_arm.c
> @@ -102,6 +102,7 @@ int kernel_execve(const char *filename,
>  	 * We were successful.  We won't be returning to our caller, but
>  	 * instead to user space by manipulating the kernel stack.
>  	 */
> +	pr_info("we were successful\n");
>  	asm(	"add	r0, %0, %1\n\t"
>  		"mov	r1, %2\n\t"
>  		"mov	r2, %3\n\t"
Huh, I removed them from arch/arm/kernel/signal.c and
arch/arm/kernel/sys_arm.c now and will resend in a moment. Thanks for
catching that.
I saw them when testing on an arm11, but was sure they were introduced
in a later patch on the stack.

Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From koen at dominion.thruhere.net  Fri Aug  3 05:33:07 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 3 Aug 2012 11:33:07 +0200
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
Message-ID: <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>


Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:

> On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>> 
>> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>> 
>>> 
>>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>>> 
>>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>>>>> that can handle events for both cpus.  This timer is used as the broadcast
>>>>> clock-event when the per-cpu timer hardware stop in low power states.
>>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>>>>> set the irq to allow the clockevent core to determine the affinity of the
>>>>> timer.
>>>> 
>>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>>>> breaks boot on my AM33xx board.
>>>> 
>>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>>>> below. With the entire series reverted, everything works again as
>>>> expected. Any idea?
>>>> 
>>>> The upstream commit ids are
>>>> 
>>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>>>> both cpus"
>>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>>> 
>>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>> 
>> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
> 
> This is really strange since CPUIDLE code is really OMAP4 specific.
> obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
> 
> May be omap2plus build some how the code gets executed on AMXX
> 
> Can you try below and see if the boot with CPUIDLE enabled goes away on
> AMXX
> 
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index ea24174..195e756 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
>        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
> 
> +       if (!cpu_is_omap44xx())
> +               return -ENODEV;
> +
>        if (omap_rev() == OMAP4430_REV_ES1_0) {
>                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
>                return -ENODEV;

That does seem to fix it:

root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
root at beaglebone:~# zcat /proc/config.gz | grep -i omap4   
CONFIG_ARCH_OMAP4=y
CONFIG_MACH_OMAP4_PANDA=y
# CONFIG_OMAP4_ERRATA_I688 is not set
# CONFIG_KEYBOARD_OMAP4 is not set
CONFIG_OMAP4_DSS_HDMI=y

regards,

Koen

From hvaibhav at ti.com  Fri Aug  3 05:42:35 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 09:42:35 +0000
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
> 
> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
> 
> > On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
> >> 
> >> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
> >> 
> >>> 
> >>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
> >>> 
> >>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
> >>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
> >>>>> that can handle events for both cpus.  This timer is used as the broadcast
> >>>>> clock-event when the per-cpu timer hardware stop in low power states.
> >>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> >>>>> set the irq to allow the clockevent core to determine the affinity of the
> >>>>> timer.
> >>>> 
> >>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> >>>> breaks boot on my AM33xx board.
> >>>> 
> >>>> Once I revert 1/3, the board boots again but crashes with the Ooops
> >>>> below. With the entire series reverted, everything works again as
> >>>> expected. Any idea?
> >>>> 
> >>>> The upstream commit ids are
> >>>> 
> >>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
> >>>> both cpus"
> >>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
> >>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
> >>> 
> >>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
> >> 
> >> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
> > 
> > This is really strange since CPUIDLE code is really OMAP4 specific.
> > obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
> > 
> > May be omap2plus build some how the code gets executed on AMXX
> > 
> > Can you try below and see if the boot with CPUIDLE enabled goes away on
> > AMXX
> > 
> > diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> > index ea24174..195e756 100644
> > --- a/arch/arm/mach-omap2/pm44xx.c
> > +++ b/arch/arm/mach-omap2/pm44xx.c
> > @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
> >        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
> >        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
> > 
> > +       if (!cpu_is_omap44xx())
> > +               return -ENODEV;
> > +
> >        if (omap_rev() == OMAP4430_REV_ES1_0) {
> >                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
> >                return -ENODEV;
> 
> That does seem to fix it:
> 
> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
> CONFIG_CPU_IDLE=y
> CONFIG_CPU_IDLE_GOV_LADDER=y
> CONFIG_CPU_IDLE_GOV_MENU=y
> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4   
> CONFIG_ARCH_OMAP4=y
> CONFIG_MACH_OMAP4_PANDA=y
> # CONFIG_OMAP4_ERRATA_I688 is not set
> # CONFIG_KEYBOARD_OMAP4 is not set
> CONFIG_OMAP4_DSS_HDMI=y
> 

This patch is not required, Without this patch is works for me,

[root at arago /]# cat /proc/version
Linux version 3.6.0-rc1-next-20120803-00010-g5f6bf0f (a0393758 at psplinux064) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #1 SMP Fri Aug 3 15:06:57 IST 2012
[root at arago /]#



Do you have below patch??
ARM: OMAP: cpu: Make cpu_class_is_omap2 true for all non-omap1 platforms


Also I have pushed branch (based on linux-next/master) to 
https://github.com/hvaibhav/am335x-linux/tree/am335x-linux-next-master


Thanks,
Vaibhav



From santosh.shilimkar at ti.com  Fri Aug  3 05:48:15 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 3 Aug 2012 15:18:15 +0530
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gzgfbeB0D18fKhmOaKUkY8Q_px+k9dq+jKEHc3YEuMMVQ@mail.gmail.com>

On Fri, Aug 3, 2012 at 3:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
>>
>> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
>>
>> > On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>> >>
>> >> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>> >>
>> >>>
>> >>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>> >>>
>> >>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>> >>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>> >>>>> that can handle events for both cpus.  This timer is used as the broadcast
>> >>>>> clock-event when the per-cpu timer hardware stop in low power states.
>> >>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>> >>>>> set the irq to allow the clockevent core to determine the affinity of the
>> >>>>> timer.
>> >>>>
>> >>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>> >>>> breaks boot on my AM33xx board.
>> >>>>
>> >>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>> >>>> below. With the entire series reverted, everything works again as
>> >>>> expected. Any idea?
>> >>>>
>> >>>> The upstream commit ids are
>> >>>>
>> >>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>> >>>> both cpus"
>> >>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>> >>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>> >>>
>> >>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>> >>
>> >> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
>> >
>> > This is really strange since CPUIDLE code is really OMAP4 specific.
>> > obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
>> >
>> > May be omap2plus build some how the code gets executed on AMXX
>> >
>> > Can you try below and see if the boot with CPUIDLE enabled goes away on
>> > AMXX
>> >
>> > diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>> > index ea24174..195e756 100644
>> > --- a/arch/arm/mach-omap2/pm44xx.c
>> > +++ b/arch/arm/mach-omap2/pm44xx.c
>> > @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
>> >        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>> >        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
>> >
>> > +       if (!cpu_is_omap44xx())
>> > +               return -ENODEV;
>> > +
>> >        if (omap_rev() == OMAP4430_REV_ES1_0) {
>> >                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
>> >                return -ENODEV;
>>
>> That does seem to fix it:
>>
>> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
>> CONFIG_CPU_IDLE=y
>> CONFIG_CPU_IDLE_GOV_LADDER=y
>> CONFIG_CPU_IDLE_GOV_MENU=y
>> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
>> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4
>> CONFIG_ARCH_OMAP4=y
>> CONFIG_MACH_OMAP4_PANDA=y
>> # CONFIG_OMAP4_ERRATA_I688 is not set
>> # CONFIG_KEYBOARD_OMAP4 is not set
>> CONFIG_OMAP4_DSS_HDMI=y
>>
>
> This patch is not required, Without this patch is works for me,
>
Which is good news.Do you have CPUIDLE enabled in your build when you tested
it. Note that CPUIDLE is not enabled by-default in omap2plus build and as I see
from Koen's email, he did enable it in his testing.

Please confirm that 3.6-rc1 boots fine even with CPUIDLE enabled and
we don't need
the above mentioned patch. If it is not the case, I can post the fix.

Thanks for testing.

Regards
Santosh


From vinod.koul at linux.intel.com  Fri Aug  3 05:55:41 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Fri, 03 Aug 2012 15:25:41 +0530
Subject: [PATCH V3 1/2] of: Add generic device tree DMA helpers
In-Reply-To: <501994D6.6070508@ti.com>
References: <1335820679-28721-1-git-send-email-jon-hunter@ti.com>
 <201207171924.33756.arnd@arndb.de> <1342756850.1726.74.camel@vkoul-udesk3>
 <201207200839.24259.arnd@arndb.de> <1342777047.1726.435.camel@vkoul-udesk3>
 <500EF27F.6050905@ti.com> <1343284960.1726.8978.camel@vkoul-udesk3>
 <501181C3.1020301@ti.com> <1343733132.1726.14418.camel@vkoul-udesk3>
 <501994D6.6070508@ti.com>
Message-ID: <1343987741.1726.14420.camel@vkoul-udesk3>

On Wed, 2012-08-01 at 15:43 -0500, Jon Hunter wrote:
> Hi Vinod,
> 
> On 07/31/2012 06:12 AM, Vinod Koul wrote:
> > On Thu, 2012-07-26 at 12:43 -0500, Jon Hunter wrote:
> >>>> So yes I can see that a channel itself could be configured to
> >> support a
> >>>> given direction, but when we ask for a channel via
> >> dma_request_channel()
> >>>> we are going to get a channel that matches the criteria we pass
> >> using
> >>>> the filter parameter. So here the thinking was that "flags" is a
> >> filter
> >>>> parameter that the user could specify and one example being
> >> direction
> >>>> but it could be something else too.
> >>> Yes that can be done, but I am leaning towards clients not have to
> >> do
> >>> anything :) DMAEngine needs to know mapping and when
> >>> dma_request_channel() is called it _always_ gives you the right
> >> channel.
> >>
> >> Ok, so are you proposing to remove the filter function and parameter
> >> from the dma_request_channel()?
> > No. But add a new request call, dma_request_slave_channel() which is
> > exclusive for slave usages and takes into account the mapping to be done
> > for channels
> >>
> >>> Maybe for slave case we need to create dma_request_slave_channel()
> >> which
> >>> has additional arguments for dmaengine to do the filtering.
> > Yup
> >>
> >> Ok, so what is not clear to me is if you envision that
> >> dma_request_slave_channel() is using a mapping table based look-up or
> >> the DT scheme or both.
> > The API should not worry about it. It would be good to have DT/ other be
> > behind this API, so it is transparent to users. They just request a
> > slave channel.
> 
> So would you envision something like (copying from Guennadi's API but
> changing direction to flags) ...
> 
> struct dma_chan *dma_request_slave_channel(struct device *dev,
> 					char *name, unsigned int flags)
> {
> 	/* If device-tree is present get slave info from here */
> 	if (dev->of_node)
> 		return of_dma_request_slave_channel(dev, name, flags);
> 
> 	return NULL;
> }
> 
> Ok, so right now the above is nothing more than a simple wrapper around
> a DT dma function to extract the slave info. However, it would allow us
> to add another means for getting the slave info in the future if
> necessary by adding an else part to the above.
> 
Yup, something like above should work well. But without any dependency
from dmac's (unlike the RFC propsed)


-- 
~Vinod



From koen at dominion.thruhere.net  Fri Aug  3 06:04:25 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 3 Aug 2012 12:04:25 +0200
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
Message-ID: <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>


Op 3 aug. 2012, om 11:42 heeft "Hiremath, Vaibhav" <hvaibhav at ti.com> het volgende geschreven:

> On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
>> 
>> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
>> 
>>> On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>>>> 
>>>> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>>>> 
>>>>> 
>>>>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>>>>> 
>>>>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>>>>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>>>>>>> that can handle events for both cpus.  This timer is used as the broadcast
>>>>>>> clock-event when the per-cpu timer hardware stop in low power states.
>>>>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>>>>>>> set the irq to allow the clockevent core to determine the affinity of the
>>>>>>> timer.
>>>>>> 
>>>>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>>>>>> breaks boot on my AM33xx board.
>>>>>> 
>>>>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>>>>>> below. With the entire series reverted, everything works again as
>>>>>> expected. Any idea?
>>>>>> 
>>>>>> The upstream commit ids are
>>>>>> 
>>>>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>>>>>> both cpus"
>>>>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>>>>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>>>>> 
>>>>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>>>> 
>>>> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
>>> 
>>> This is really strange since CPUIDLE code is really OMAP4 specific.
>>> obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
>>> 
>>> May be omap2plus build some how the code gets executed on AMXX
>>> 
>>> Can you try below and see if the boot with CPUIDLE enabled goes away on
>>> AMXX
>>> 
>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>>> index ea24174..195e756 100644
>>> --- a/arch/arm/mach-omap2/pm44xx.c
>>> +++ b/arch/arm/mach-omap2/pm44xx.c
>>> @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
>>>       struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>>>       struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
>>> 
>>> +       if (!cpu_is_omap44xx())
>>> +               return -ENODEV;
>>> +
>>>       if (omap_rev() == OMAP4430_REV_ES1_0) {
>>>               WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
>>>               return -ENODEV;
>> 
>> That does seem to fix it:
>> 
>> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
>> CONFIG_CPU_IDLE=y
>> CONFIG_CPU_IDLE_GOV_LADDER=y
>> CONFIG_CPU_IDLE_GOV_MENU=y
>> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
>> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4   
>> CONFIG_ARCH_OMAP4=y
>> CONFIG_MACH_OMAP4_PANDA=y
>> # CONFIG_OMAP4_ERRATA_I688 is not set
>> # CONFIG_KEYBOARD_OMAP4 is not set
>> CONFIG_OMAP4_DSS_HDMI=y
>> 
> 
> This patch is not required, Without this patch is works for me,

I just retested and I don't need Santosh' patch, booting with cpuidle enable works now, after refreshing your patchset (and dropping the rtc commit, it conflicts with the other rtc patches out there).

> 
> [root at arago /]# cat /proc/version
> Linux version 3.6.0-rc1-next-20120803-00010-g5f6bf0f (a0393758 at psplinux064) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #1 SMP Fri Aug 3 15:06:57 IST 2012
> [root at arago /]#
> 
> 
> 
> Do you have below patch??
> ARM: OMAP: cpu: Make cpu_class_is_omap2 true for all non-omap1 platforms
> 
> 
> Also I have pushed branch (based on linux-next/master) to 
> https://github.com/hvaibhav/am335x-linux/tree/am335x-linux-next-master

Thanks! Ajays USB work and AnilKumar's pinctrl work are there as branches, any plans to add da8xx-fb, rtc and networking branches? As you can see from the cpsw patches, they were impossible to test because the davinci_mdio ones were missing.

regards,

Koen

From s.hauer at pengutronix.de  Fri Aug  3 06:07:11 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 12:07:11 +0200
Subject: [PATCH v2 2/3] mtd: nand: Let MTD_NAND_GPMI_NAND depend on MXS_DMA
In-Reply-To: <1343215100-24005-2-git-send-email-festevam@gmail.com>
References: <1343215100-24005-1-git-send-email-festevam@gmail.com>
 <1343215100-24005-2-git-send-email-festevam@gmail.com>
Message-ID: <20120803100711.GC24458@pengutronix.de>

On Wed, Jul 25, 2012 at 08:18:19AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> MTD_NAND_GPMI_NAND driver depends on MXS_DMA to be selected, otherwise the following error happens
> for imx_v6_v7_defconfig:
> 
> drivers/built-in.o: In function `gpmi_dma_filter':
> clk-fixed-factor.c:(.text+0xb124c): undefined reference to `mxs_dma_is_apbh'
> make: *** [vmlinux] Error 1
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

As mentioned elsewhere in this thread: We should not select user visible
options, so this patch is the only thing we can do atm (apart from
'fixing the tools' as David mentioned, but this is out of scope for an
-rc kernel)

Additionally the imx_v6_v7_defconfig should be adjusted so that the gpmi
nand driver actually gets built.

Sascha

> ---
> Changes since v1:
> - Use 'depends' rather than 'select'
>  drivers/mtd/nand/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index a5d8a1b..da52c7d 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -463,6 +463,7 @@ config MTD_NAND_NANDSIM
>  config MTD_NAND_GPMI_NAND
>          bool "GPMI NAND Flash Controller driver"
>          depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q)
> +	depends on MXS_DMA
>          help
>  	 Enables NAND Flash support for IMX23, IMX28 or IMX6.
>  	 The GPMI controller is very powerful, with the help of BCH
> -- 
> 1.7.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Aug  3 06:08:26 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 12:08:26 +0200
Subject: [PATCH v5 0/3] imx: add usbmisc support
In-Reply-To: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
References: <1343805141-5872-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <20120803100826.GL1451@pengutronix.de>

On Wed, Aug 01, 2012 at 03:12:18PM +0800, Richard Zhao wrote:
> usbmisc driver handles the SoC specific non-core usb registers.
> 
> Changes since last version:
>  - add missing ci13xxx_imx.h
> 
> Changes v3 -> v4:
>  - rebase onto torvalds latest git tree
>  - use phandle linke usb controllers and usbmisc device.
>    It also make usbmisc driver possible to be kernel modules.
> 
> Richard Zhao (3):
>   USB: chipidea: add imx usbmisc support
>   ARM: imx6q: clk_register_clkdev usbmisc clock
>   ARM: dts: imx6q-sabrelite: add usbmisc device

I think this is good enough to go now.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>


> 
>  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
>  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
>  arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
>  arch/arm/boot/dts/imx6q.dtsi                       |   10 ++
>  arch/arm/mach-imx/clk-imx6q.c                      |    1 +
>  drivers/usb/chipidea/Makefile                      |    2 +-
>  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
>  drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
>  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
>  9 files changed, 286 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
>  create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
>  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
> 
> -- 
> 1.7.9.5
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From u.kleine-koenig at pengutronix.de  Fri Aug  3 06:10:11 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri,  3 Aug 2012 12:10:11 +0200
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
Message-ID: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>

Hello,

the only changes compared to v5 (sent starting with Message-id:
1341512035-8173-1-git-send-email-u.kleine-koenig at pengutronix.de)
are that several debug pr_infos were dropped that I missed to remove
before. Thanks to Will Deacon for pointing out that problem.
Furthermore I rebased (trivially) to v3.5.

Best regards
Uwe

Catalin Marinas (1):
  Cortex-M3: Add base support for Cortex-M3

Uwe Kleine-K?nig (2):
  ARM: make cr_alignment read-only #ifndef CONFIG_CPU_CP15
  Cortex-M3: Add support for exception handling

 arch/arm/include/asm/assembler.h   |   13 ++-
 arch/arm/include/asm/cp15.h        |   11 ++-
 arch/arm/include/asm/cputype.h     |    3 +
 arch/arm/include/asm/glue-cache.h  |   24 ++++++
 arch/arm/include/asm/glue-df.h     |    8 ++
 arch/arm/include/asm/glue-proc.h   |    9 ++
 arch/arm/include/asm/irqflags.h    |   22 +++--
 arch/arm/include/asm/processor.h   |    7 ++
 arch/arm/include/asm/ptrace.h      |   44 ++++++++--
 arch/arm/include/asm/system_info.h |    1 +
 arch/arm/kernel/asm-offsets.c      |    3 +
 arch/arm/kernel/entry-common.S     |    4 +
 arch/arm/kernel/entry-header.S     |  148 +++++++++++++++++++++++++++++++++
 arch/arm/kernel/entry-v7m.S        |  134 ++++++++++++++++++++++++++++++
 arch/arm/kernel/head-common.S      |    9 +-
 arch/arm/kernel/head-nommu.S       |    9 +-
 arch/arm/kernel/process.c          |    8 ++
 arch/arm/kernel/ptrace.c           |    3 +
 arch/arm/kernel/setup.c            |   13 ++-
 arch/arm/kernel/traps.c            |    2 +
 arch/arm/mm/alignment.c            |    2 +
 arch/arm/mm/mmu.c                  |   17 ++++
 arch/arm/mm/nommu.c                |    2 +
 arch/arm/mm/proc-v7m.S             |  161 ++++++++++++++++++++++++++++++++++++
 24 files changed, 635 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/kernel/entry-v7m.S
 create mode 100644 arch/arm/mm/proc-v7m.S

-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Fri Aug  3 06:10:14 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri,  3 Aug 2012 12:10:14 +0200
Subject: [PATCH v6 3/3] Cortex-M3: Add support for exception handling
In-Reply-To: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1343988614-5508-4-git-send-email-u.kleine-koenig@pengutronix.de>

This patch implements the exception handling for the ARMv7-M
architecture (pretty different from the A or R profiles).

It bases on work done earlier by Catalin for 2.6.33 but was nearly
completely rewritten to use a pt_regs layout compatible to the A
profile.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Forwarded: id:1333573807-23709-3-git-send-email-u.kleine-koenig at pengutronix.de
---
 arch/arm/kernel/entry-common.S |    4 ++
 arch/arm/kernel/entry-header.S |  148 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/entry-v7m.S    |  134 ++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/process.c      |    8 +++
 arch/arm/kernel/ptrace.c       |    3 +
 5 files changed, 297 insertions(+)
 create mode 100644 arch/arm/kernel/entry-v7m.S

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 4afed88..62c4db6 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -341,6 +341,9 @@ ENDPROC(ftrace_stub)
 
 	.align	5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+	v7m_exception_entry
+#else
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0 - r12
  ARM(	add	r8, sp, #S_PC		)
@@ -351,6 +354,7 @@ ENTRY(vector_swi)
 	str	lr, [sp, #S_PC]			@ Save calling PC
 	str	r8, [sp, #S_PSR]		@ Save CPSR
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
+#endif
 	zero_fp
 
 	/*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531e..33d9900 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -44,6 +44,145 @@
 #endif
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_fast_exit is used when returning from interrupts.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+	.macro	v7m_exception_entry
+	@ determine the location of the registers saved by the core during
+	@ exception entry. Depending on the mode the cpu was in when the
+	@ exception happend that is either on the main or the process stack.
+	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+	@ was used.
+	tst	lr, #0x4
+	mrsne	r12, psp
+	moveq	r12, sp
+
+	@ we cannot rely on r0-r3 and r12 matching the value saved in the
+	@ exception frame because of tail-chaining. So these have to be
+	@ reloaded.
+	ldmia	r12!, {r0-r3}
+
+	@ Linux expects to have irqs off. Do it here before taking stack space
+	cpsid	i
+
+	sub	sp, #S_FRAME_SIZE-S_IP
+	stmdb	sp!, {r0-r11}
+
+	@ load saved r12, lr, return address and xPSR.
+	@ r0-r7 are used for signals and never touched from now on. Clobbering
+	@ r8-r12 is OK.
+	mov	r9, r12
+	ldmia	r9!, {r8, r10-r12}
+
+	@ calculate the original stack pointer value.
+	@ r9 currently points to the memory location just above the auto saved
+	@ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
+	@ then space was allocated for FP state. That is space for 18 32-bit
+	@ values. (If FP extension is unimplemented, bit 4 is 1.)
+	@ Additionally the cpu might automatically 8-byte align the stack. Bit 9
+	@ of the saved xPSR specifies if stack aligning took place. In this case
+	@ another 32-bit value is included in the stack.
+
+	tst	lr, #0x10
+	addeq	r9, r9, #576
+
+	tst	r12, 0x100
+	addne	r9, r9, #4
+
+	@ store saved r12 using str to have a register to hold the base for stm
+	str	r8, [sp, #S_IP]
+	add	r8, sp, #S_SP
+	@ store r13-r15, xPSR
+	stmia	r8!, {r9-r12}
+	@ store r0 once more and EXC_RETURN
+	stmia	r8, {r0, lr}
+	.endm
+
+	.macro	v7m_exception_fast_exit
+	@ registers r0-r3 and r12 are automatically restored on exception
+	@ return. r4-r7 were not clobbered in v7m_exception_entry so for
+	@ correctness they don't need to be restored. So only r8-r11 must be
+	@ restored here. The easiest way to do so is to restore r0-r7, too.
+	ldmia	sp!, {r0-r11}
+	add	sp, #S_FRAME_SIZE-S_IP
+	cpsie	i
+	bx	lr
+	.endm
+
+	.macro	v7m_exception_slow_exit ret_r0
+	cpsid	i
+	ldr	lr, [sp, #S_EXC_RET]	@ read exception LR
+	tst     lr, #0x8
+	bne	1f			@ go to thread mode using exception return
+
+	/*
+	 * return to kernel thread
+	 * sp is already set up (and might be unset in pt_regs), so only
+	 * restore r0-r12 and pc
+	 */
+	ldmia	sp, {r0-r12}
+	ldr	lr, [sp, #S_PC]
+	add	sp, sp, #S_FRAME_SIZE
+	cpsie	i
+	bx	lr
+
+1:	/*
+	 * return to userspace
+	 */
+
+	@ read original r12, sp, lr, pc and xPSR
+	add	r12, sp, #S_IP
+	ldmia	r12, {r1-r5}
+
+	@ handle stack aligning
+	tst	r5, #0x100
+	subne	r2, r2, #4
+
+	@ skip over stack space for fp saving
+	tst	lr, #0x10
+	subeq	r2, r2, #576
+
+	@ write basic exception frame
+	stmdb	r2!, {r1, r3-r5}
+	ldmia	sp, {r1, r3-r5}
+	.if	\ret_r0
+	stmdb	r2!, {r0, r3-r5}
+	.else
+	stmdb	r2!, {r1, r3-r5}
+	.endif
+
+	@ restore process sp
+	msr	psp, r2
+
+	@ restore original r4-r11
+	ldmia	sp!, {r0-r11}
+
+	@ restore main sp
+	add	sp, sp, #S_FRAME_SIZE-S_IP
+
+	cpsie	i
+	bx	lr
+	.endm
+#endif	/* CONFIG_CPU_V7M */
+
 	@
 	@ Store/load the USER SP and LR registers by switching to the SYS
 	@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -131,6 +270,14 @@
 	rfeia	sp!
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+	.macro	restore_user_regs, fast = 0, offset = 0
+	.if	\offset
+	add	sp, #\offset
+	.endif
+	v7m_exception_slow_exit ret_r0 = \fast
+	.endm
+#else	/* !CONFIG_CPU_V7M */
 	.macro	restore_user_regs, fast = 0, offset = 0
 	clrex					@ clear the exclusive monitor
 	mov	r2, sp
@@ -147,6 +294,7 @@
 	add	sp, sp, #S_FRAME_SIZE - S_SP
 	movs	pc, lr				@ return & move spsr_svc into cpsr
 	.endm
+#endif	/* CONFIG_CPU_V7M */
 
 	.macro	get_thread_info, rd
 	mov	\rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 0000000..a0991dc
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_PREEMPT
+#error "CONFIG_PREEMPT not supported on the current ARMv7M implementation"
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+	v7m_exception_entry
+	adr	r0, strerr
+	mrs	r1, ipsr
+	mov	r2, lr
+	bl	printk
+	mov	r0, sp
+	bl	show_regs
+1:	b	1b
+ENDPROC(__invalid_entry)
+
+strerr:	.asciz	"\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+	.align	2
+__irq_entry:
+	v7m_exception_entry
+
+	@
+	@ Invoke the IRQ handler
+	@
+	mrs	r0, ipsr
+	and	r0, #0xff
+	sub	r0, #16			@ IRQ number
+	mov	r1, sp
+	@ routine called with r0 = irq number, r1 = struct pt_regs *
+	bl	asm_do_IRQ
+
+	@
+	@ Check for any pending work if returning to user
+	@
+	ldr	lr, [sp, #S_EXC_RET]
+	tst	lr, #0x8		@ check the return stack
+	beq	2f			@ returning to handler mode
+	get_thread_info tsk
+	ldr	r1, [tsk, #TI_FLAGS]
+	tst	r1, #_TIF_WORK_MASK
+	beq	2f			@ no work pending
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 28		@ ICSR.PENDSVSET
+	str	r0, [r1]		@ raise PendSV
+
+2:
+	v7m_exception_fast_exit
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+	v7m_exception_entry
+
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 27		@ ICSR.PENDSVCLR
+	str	r0, [r1]		@ clear PendSV
+
+	@ execute the pending work, including reschedule
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+	.fnstart
+	.cantunwind
+	add	ip, r1, #TI_CPU_SAVE
+	stmia	ip!, {r4 - r11}		@ Store most regs on stack
+	str	sp, [ip], #4
+	str	lr, [ip], #4
+	mov	r5, r0
+	add	r4, r2, #TI_CPU_SAVE
+	ldr	r0, =thread_notify_head
+	mov	r1, #THREAD_NOTIFY_SWITCH
+	bl	atomic_notifier_call_chain
+	mov	ip, r4
+	mov	r0, r5
+	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
+	ldr	sp, [ip], #4
+	ldr	pc, [ip]
+	.fnend
+ENDPROC(__switch_to)
+
+	.data
+	.align	8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+	.long	0			@ 0 - Reset stack pointer
+	.long	__invalid_entry		@ 1 - Reset
+	.long	__invalid_entry		@ 2 - NMI
+	.long	__invalid_entry		@ 3 - HardFault
+	.long	__invalid_entry		@ 4 - MemManage
+	.long	__invalid_entry		@ 5 - BusFault
+	.long	__invalid_entry		@ 6 - UsageFault
+	.long	__invalid_entry		@ 7 - Reserved
+	.long	__invalid_entry		@ 8 - Reserved
+	.long	__invalid_entry		@ 9 - Reserved
+	.long	__invalid_entry		@ 10 - Reserved
+	.long	vector_swi		@ 11 - SVCall
+	.long	__invalid_entry		@ 12 - Debug Monitor
+	.long	__invalid_entry		@ 13 - Reserved
+	.long	__pendsv_entry		@ 14 - PendSV
+	.long	__invalid_entry		@ 15 - SysTick
+	.rept	64 - 16
+	.long	__irq_entry		@ 16..64 - External Interrupts
+	.endr
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 19c95ea6..204bbd0 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -434,7 +434,11 @@ asm(	".pushsection .text\n"
 #ifdef CONFIG_TRACE_IRQFLAGS
 "	bl	trace_hardirqs_on\n"
 #endif
+#ifdef CONFIG_CPU_V7M
+"	msr	primask, r7\n"
+#else
 "	msr	cpsr_c, r7\n"
+#endif
 "	mov	r0, r4\n"
 "	mov	lr, r6\n"
 "	mov	pc, r5\n"
@@ -473,6 +477,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 	regs.ARM_pc = (unsigned long)kernel_thread_helper;
 	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+#if defined CONFIG_CPU_V7M
+	/* Return to Handler mode */
+	regs.ARM_EXC_RET = 0xfffffff1L;
+#endif
 
 	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 14e3826..1f11ba2 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -83,6 +83,9 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(pc),
 	REG_OFFSET_NAME(cpsr),
 	REG_OFFSET_NAME(ORIG_r0),
+#ifdef CONFIG_CPU_V7M
+	REG_OFFSET_NAME(EXC_RET),
+#endif
 	REG_OFFSET_END,
 };
 
-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Fri Aug  3 06:10:12 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri,  3 Aug 2012 12:10:12 +0200
Subject: [PATCH v6 1/3] ARM: make cr_alignment read-only #ifndef
 CONFIG_CPU_CP15
In-Reply-To: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1343988614-5508-2-git-send-email-u.kleine-koenig@pengutronix.de>

This makes cr_alignment a constant 0 to break code that tries to modify
the value as it's likely that it's built on wrong assumption when
CONFIG_CPU_CP15 isn't defined. For code that is only reading the value 0
is more or less a fine value to report.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Forwarded: id:1333573807-23709-1-git-send-email-u.kleine-koenig at pengutronix.de
---
 arch/arm/include/asm/cp15.h   |   11 ++++++++++-
 arch/arm/kernel/head-common.S |    9 +++++++--
 arch/arm/mm/alignment.c       |    2 ++
 arch/arm/mm/mmu.c             |   17 +++++++++++++++++
 4 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 5ef4d80..d814435 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,6 +42,8 @@
 #define vectors_high()	(0)
 #endif
 
+#ifdef CONFIG_CPU_CP15
+
 extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
 extern unsigned long cr_alignment;	/* defined in entry-armv.S */
 
@@ -82,6 +84,13 @@ static inline void set_copro_access(unsigned int val)
 	isb();
 }
 
-#endif
+#else /* ifdef CONFIG_CPU_CP15 */
+
+#define cr_no_alignment	UL(0)
+#define cr_alignment	UL(0)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
+#endif /* ifndef __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 854bd22..2f560c5 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -98,8 +98,9 @@ __mmap_switched:
 	str	r9, [r4]			@ Save processor ID
 	str	r1, [r5]			@ Save machine type
 	str	r2, [r6]			@ Save atags pointer
-	bic	r4, r0, #CR_A			@ Clear 'A' bit
-	stmia	r7, {r0, r4}			@ Save control register values
+	cmp	r7, #0
+	bicne	r4, r0, #CR_A			@ Clear 'A' bit
+	stmneia	r7, {r0, r4}			@ Save control register values
 	b	start_kernel
 ENDPROC(__mmap_switched)
 
@@ -113,7 +114,11 @@ __mmap_switched_data:
 	.long	processor_id			@ r4
 	.long	__machine_arch_type		@ r5
 	.long	__atags_pointer			@ r6
+#ifdef CONFIG_CPU_CP15
 	.long	cr_alignment			@ r7
+#else
+	.long	0
+#endif
 	.long	init_thread_union + THREAD_START_SP @ sp
 	.size	__mmap_switched_data, . - __mmap_switched_data
 
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231..7df07d1 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -962,12 +962,14 @@ static int __init alignment_init(void)
 		return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
 	if (cpu_is_v6_unaligned()) {
 		cr_alignment &= ~CR_A;
 		cr_no_alignment &= ~CR_A;
 		set_cr(cr_alignment);
 		ai_usermode = safe_usermode(ai_usermode, false);
 	}
+#endif
 
 	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 			"alignment exception");
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d..7a390f2 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -96,6 +96,7 @@ static struct cachepolicy cache_policies[] __initdata = {
 	}
 };
 
+#ifdef CONFIG_CPU_CP15
 /*
  * These are useful for identifying cache coherency
  * problems by allowing the cache or the cache and
@@ -194,6 +195,22 @@ void adjust_cr(unsigned long mask, unsigned long set)
 }
 #endif
 
+#else
+
+static int __init early_cachepolicy(char *p)
+{
+	pr_warning("cachepolicy kernel parameter not supported without cp15\n");
+}
+early_param("cachepolicy", early_cachepolicy);
+
+static int __init noalign_setup(char *__unused)
+{
+	pr_warning("noalign kernel parameter not supported without cp15\n");
+}
+__setup("noalign", noalign_setup);
+
+#endif
+
 #define PROT_PTE_DEVICE		L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 #define PROT_SECT_DEVICE	PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 
-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Fri Aug  3 06:10:13 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri,  3 Aug 2012 12:10:13 +0200
Subject: [PATCH v6 2/3] Cortex-M3: Add base support for Cortex-M3
In-Reply-To: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1343988614-5508-3-git-send-email-u.kleine-koenig@pengutronix.de>

From: Catalin Marinas <catalin.marinas at arm.com>

This patch adds the base support for the Cortex-M3 processor (ARMv7-M
architecture). It consists of the corresponding arch/arm/mm/ files and
various #ifdef's around the kernel. Exception handling is implemented by
a subsequent patch.

[ukleinek: squash in some changes originating from commit

b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)

from the v2.6.33-arm1 patch stack, port to post 3.4, drop zImage
support, drop reorganisation of pt_regs, assert CONFIG_V7M doesn't leak
into installed headers and a few cosmetic changes]

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Changes since v4, id:1333573807-23709-2-git-send-email-u.kleine-koenig at pengutronix.de
 - simplify irq enable/disable ops as suggested by Russell
 - don't leak kernel config symbols into userspace headers and add some
   comments
---
 arch/arm/include/asm/assembler.h   |   13 ++-
 arch/arm/include/asm/cputype.h     |    3 +
 arch/arm/include/asm/glue-cache.h  |   24 ++++++
 arch/arm/include/asm/glue-df.h     |    8 ++
 arch/arm/include/asm/glue-proc.h   |    9 ++
 arch/arm/include/asm/irqflags.h    |   22 +++--
 arch/arm/include/asm/processor.h   |    7 ++
 arch/arm/include/asm/ptrace.h      |   44 ++++++++--
 arch/arm/include/asm/system_info.h |    1 +
 arch/arm/kernel/asm-offsets.c      |    3 +
 arch/arm/kernel/head-nommu.S       |    9 +-
 arch/arm/kernel/setup.c            |   13 ++-
 arch/arm/kernel/traps.c            |    2 +
 arch/arm/mm/nommu.c                |    2 +
 arch/arm/mm/proc-v7m.S             |  161 ++++++++++++++++++++++++++++++++++++
 15 files changed, 302 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mm/proc-v7m.S

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 03fb936..705d108 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -135,7 +135,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
 	.macro	save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	mrs	\oldcpsr, primask
+#else
 	mrs	\oldcpsr, cpsr
+#endif
 	disable_irq
 	.endm
 
@@ -149,7 +153,11 @@
  * guarantee that this will preserve the flags.
  */
 	.macro	restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	msr	primask, \oldcpsr
+#else
 	msr	cpsr_c, \oldcpsr
+#endif
 	.endm
 
 	.macro restore_irqs, oldcpsr
@@ -228,7 +236,10 @@
 #endif
 	.endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+	.macro	setmode, mode, reg
+	.endm
+#elif defined(CONFIG_THUMB2_KERNEL)
 	.macro	setmode, mode, reg
 	mov	\reg, #\mode
 	msr	cpsr_c, \reg
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb47d28..5bd8cb6 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -46,6 +46,9 @@ extern unsigned int processor_id;
 		    : "cc");						\
 		__val;							\
 	})
+#elif defined(CONFIG_CPU_V7M)
+#define read_cpuid(reg) (*(unsigned int *)0xe000ed00)
+#define read_cpuid_ext(reg) 0
 #else
 #define read_cpuid(reg) (processor_id)
 #define read_cpuid_ext(reg) 0
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874..a02fd01 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -125,10 +125,34 @@
 //# endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  error "Multi-cache not supported on ARMv7-M"
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a, unsigned long b, unsigned int c) { }
+
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline int nop_coherent_user_range(unsigned long a, unsigned long b) { return 0; }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 8cacbcd..1f2339c 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index ac1dd54..f2f39bc 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init			__glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca5..3b763d6 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
 /*
  * CPU interrupt mask handling.
  */
+#ifdef CONFIG_CPU_V7M
+#define IRQMASK_REG_NAME_R "primask"
+#define IRQMASK_REG_NAME_W "primask"
+#define IRQMASK_I_BIT	1
+#else
+#define IRQMASK_REG_NAME_R "cpsr"
+#define IRQMASK_REG_NAME_W "cpsr_c"
+#define IRQMASK_I_BIT	PSR_I_BIT
+#endif
+
 #if __LINUX_ARM_ARCH__ >= 6
 
 static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
 	unsigned long flags;
 
 	asm volatile(
-		"	mrs	%0, cpsr	@ arch_local_irq_save\n"
+		"	mrs	%0, " IRQMASK_REG_NAME_R "	@ arch_local_irq_save\n"
 		"	cpsid	i"
 		: "=r" (flags) : : "memory", "cc");
 	return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
 {
 	unsigned long flags;
 	asm volatile(
-		"	mrs	%0, cpsr	@ local_save_flags"
+		"	mrs	%0, " IRQMASK_REG_NAME_R "	@ local_save_flags"
 		: "=r" (flags) : : "memory", "cc");
 	return flags;
 }
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
 static inline void arch_local_irq_restore(unsigned long flags)
 {
 	asm volatile(
-		"	msr	cpsr_c, %0	@ local_irq_restore"
+		"	msr	" IRQMASK_REG_NAME_W ", %0	@ local_irq_restore"
 		:
 		: "r" (flags)
 		: "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
-	return flags & PSR_I_BIT;
+	return flags & IRQMASK_I_BIT;
 }
 
-#endif
-#endif
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 99afa74..dc82aa0 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -49,7 +49,14 @@ struct thread_struct {
 #ifdef CONFIG_MMU
 #define nommu_start_thread(regs) do { } while (0)
 #else
+#ifndef CONFIG_CPU_V7M
 #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
+#else
+#define nommu_start_thread(regs) do {					\
+	regs->ARM_r10 = current->mm->start_data;			\
+	regs->ARM_EXC_RET = 0xfffffffdL;				\
+} while (0)
+#endif
 #endif
 
 #define start_thread(regs,pc,sp)					\
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 355ece5..090fea7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -34,27 +34,46 @@
 
 /*
  * PSR bits
+ * Note on V7M there is no mode contained in the PSR
  */
 #define USR26_MODE	0x00000000
 #define FIQ26_MODE	0x00000001
 #define IRQ26_MODE	0x00000002
 #define SVC26_MODE	0x00000003
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+/*
+ * Use 0 here to get code right that creates a userspace
+ * or kernel space thread
+ */
+#define USR_MODE	0x00000000
+#define SVC_MODE	0x00000000
+#else
 #define USR_MODE	0x00000010
+#define SVC_MODE	0x00000013
+#endif
 #define FIQ_MODE	0x00000011
 #define IRQ_MODE	0x00000012
-#define SVC_MODE	0x00000013
 #define ABT_MODE	0x00000017
 #define UND_MODE	0x0000001b
 #define SYSTEM_MODE	0x0000001f
 #define MODE32_BIT	0x00000010
 #define MODE_MASK	0x0000001f
-#define PSR_T_BIT	0x00000020
-#define PSR_F_BIT	0x00000040
-#define PSR_I_BIT	0x00000080
-#define PSR_A_BIT	0x00000100
-#define PSR_E_BIT	0x00000200
-#define PSR_J_BIT	0x01000000
-#define PSR_Q_BIT	0x08000000
+
+#define V4_PSR_T_BIT	0x00000020	/* >= V4T, but not V7M */
+#define V7M_PSR_T_BIT	0x01000000
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+#define PSR_T_BIT	V7M_PSR_T_BIT
+#else
+/* for compatibility */
+#define PSR_T_BIT	V4_PSR_T_BIT
+#endif
+
+#define PSR_F_BIT	0x00000040	/* >= V4, but not V7M */
+#define PSR_I_BIT	0x00000080	/* >= V4, but not V7M */
+#define PSR_A_BIT	0x00000100	/* >= V6, but not V7M */
+#define PSR_E_BIT	0x00000200	/* >= V6, but not V7M */
+#define PSR_J_BIT	0x01000000	/* >= V5J, but not V7M */
+#define PSR_Q_BIT	0x08000000	/* >= V5E, including V7M */
 #define PSR_V_BIT	0x10000000
 #define PSR_C_BIT	0x20000000
 #define PSR_Z_BIT	0x40000000
@@ -106,7 +125,11 @@ struct pt_regs {
 };
 #else /* __KERNEL__ */
 struct pt_regs {
+#ifdef CONFIG_CPU_V7M
+	unsigned long uregs[20];
+#else
 	unsigned long uregs[18];
+#endif
 };
 #endif /* __KERNEL__ */
 
@@ -128,6 +151,7 @@ struct pt_regs {
 #define ARM_r1		uregs[1]
 #define ARM_r0		uregs[0]
 #define ARM_ORIG_r0	uregs[17]
+#define ARM_EXC_RET	uregs[18]
 
 /*
  * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
@@ -165,6 +189,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
 	/*
@@ -187,6 +212,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
 		regs->ARM_cpsr |= USR_MODE;
 
 	return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+	return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d..720ea03 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
 #define CPU_ARCH_ARMv5TEJ	7
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
+#define CPU_ARCH_ARMv7M		10
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d89..6f6b5b6 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -91,6 +91,9 @@ int main(void)
   DEFINE(S_PC,			offsetof(struct pt_regs, ARM_pc));
   DEFINE(S_PSR,			offsetof(struct pt_regs, ARM_cpsr));
   DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));
+#ifdef CONFIG_CPU_V7M
+  DEFINE(S_EXC_RET,		offsetof(struct pt_regs, ARM_EXC_RET));
+#endif
   DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
   BLANK();
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 278cfc1..c391c05 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -44,10 +44,13 @@ ENTRY(stext)
 
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-	ldr	r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
 	mrc	p15, 0, r9, c0, c0		@ get processor id
+#elif defined(CONFIG_CPU_V7M)
+	ldr	r9, =0xe000ed00			@ CPUID register address
+	ldr	r9, [r9]
+#else
+	ldr	r9, =CONFIG_PROCESSOR_ID
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e15d83b..e80ccab 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -135,7 +135,9 @@ struct stack {
 	u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -215,7 +217,7 @@ static const char *proc_arch[] = {
 	"5TEJ",
 	"6TEJ",
 	"7",
-	"?(11)",
+	"7M",
 	"?(12)",
 	"?(13)",
 	"?(14)",
@@ -224,6 +226,12 @@ static const char *proc_arch[] = {
 	"?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+	return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
 	int cpu_arch;
@@ -256,6 +264,7 @@ static int __get_cpu_architecture(void)
 
 	return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -383,6 +392,7 @@ static void __init feat_v6_fixup(void)
  */
 void cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned int cpu = smp_processor_id();
 	struct stack *stk = &stacks[cpu];
 
@@ -427,6 +437,7 @@ void cpu_init(void)
 	      "I" (offsetof(struct stack, und[0])),
 	      PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
 	    : "r14");
+#endif
 }
 
 int __cpu_logical_map[NR_CPUS];
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3647170..7c62282 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -792,6 +792,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void *vectors_base)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned long vectors = (unsigned long)vectors_base;
 	extern char __stubs_start[], __stubs_end[];
 	extern char __vectors_start[], __vectors_end[];
@@ -825,4 +826,5 @@ void __init early_trap_init(void *vectors_base)
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#endif
 }
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f..4bc8ae5 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -20,12 +20,14 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
 	/*
 	 * Register the exception vector page.
 	 * some architectures which the DRAM is the exception vector to trap,
 	 * alloc_page breaks with error, although it is not NULL, but "0."
 	 */
 	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
 }
 
 void __init sanity_check_meminfo(void)
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 0000000..2b8eb97
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,161 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(cpu_v7m_proc_init)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *	cpu_v7m_reset(loc)
+ *
+ *	Perform a soft reset of the system.  Put the CPU into the
+ *	same state as it would be if it had been reset, and branch
+ *	to what would be the reset vector.
+ *
+ *	- loc   - location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_v7m_reset)
+	mov	pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *	cpu_v7m_do_idle()
+ *
+ *	Idle the processor (eg, wait for interrupt).
+ *
+ *	IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+	wfi
+	mov	pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+	mov	pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+	mov	pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+cpu_v7m_name:
+	.ascii	"ARMv7-M Processor"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+/*
+ *	__v7m_setup
+ *
+ *	This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+	@ Configure the vector table base address
+	ldr	r0, =0xe000ed08		@ vector table base address
+	ldr	r12, =vector_table
+	str	r12, [r0]
+
+	@ Lower the priority of the SVC and PendSV exceptions
+	ldr	r0, =0xe000ed1c
+	mov	r5, #0x80000000
+	str	r5, [r0]		@ set SVC priority
+	ldr	r0, =0xe000ed20
+	mov	r5, #0x00800000
+	str	r5, [r0]		@ set PendSV priority
+
+	@ SVC to run the kernel in this mode
+	adr	r0, BSYM(1f)
+	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
+	str	r0, [r12, #11 * 4]	@ write the temporary SVC vector entry
+	mov	r6, lr			@ save LR
+	mov	r7, sp			@ save SP
+	ldr	sp, =__v7m_setup_stack_top
+	cpsie	i
+	svc	#0
+1:	cpsid	i
+	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
+	mov	lr, r6			@ restore LR
+	mov	sp, r7			@ restore SP
+
+	@ Special-purpose control register
+	mov	r0, #1
+	msr	control, r0		@ Thread mode has unpriviledged access
+
+	@ Configure the System Control Register
+	ldr	r0, =0xe000ed14		@ system control register
+	ldr	r12, [r0]
+	orr	r12, #1 << 9		@ STKALIGN
+	str	r12, [r0]
+	mov	pc, lr
+ENDPROC(__v7m_setup)
+
+	.align	2
+	.type	v7m_processor_functions, #object
+ENTRY(v7m_processor_functions)
+	.word	nommu_early_abort
+	.word	cpu_v7m_proc_init
+	.word	cpu_v7m_proc_fin
+	.word	cpu_v7m_reset
+	.word	cpu_v7m_do_idle
+	.word	cpu_v7m_dcache_clean_area
+	.word	cpu_v7m_switch_mm
+	.word	0			@ cpu_v7m_set_pte_ext
+	.word	legacy_pabort
+	.size	v7m_processor_functions, . - v7m_processor_functions
+
+	.type	cpu_arch_name, #object
+cpu_arch_name:
+	.asciz	"armv7m"
+	.size	cpu_arch_name, . - cpu_arch_name
+
+	.type	cpu_elf_name, #object
+cpu_elf_name:
+	.asciz	"v7m"
+	.size	cpu_elf_name, . - cpu_elf_name
+	.align
+
+	.section ".proc.info.init", #alloc, #execinstr
+
+	/*
+	 * Match any ARMv7-M processor core.
+	 */
+	.type	__v7m_proc_info, #object
+__v7m_proc_info:
+	.long	0x000f0000		@ Required ID value
+	.long	0x000f0000		@ Mask for ID
+	.long   0			@ proc_info_list.__cpu_mm_mmu_flags
+	.long   0			@ proc_info_list.__cpu_io_mmu_flags
+	b	__v7m_setup		@ proc_info_list.__cpu_flush
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long	cpu_v7m_name
+	.long	v7m_processor_functions	@ proc_info_list.proc
+	.long	0			@ proc_info_list.tlb
+	.long	0			@ proc_info_list.user
+	.long	0			@ proc_info_list.cache
+	.size	__v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+	.space	4 * 8				@ 8 registers
+__v7m_setup_stack_top:
-- 
1.7.10.4



From vinod.koul at linux.intel.com  Fri Aug  3 06:14:33 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Fri, 03 Aug 2012 15:44:33 +0530
Subject: [PATCH/RFC 1/4] dma: add a function to request a DMA channel
 for a specific client
In-Reply-To: <Pine.LNX.4.64.1208021101350.11412@axis700.grange>
References: <Pine.LNX.4.64.1207171201550.11241@axis700.grange>
 <Pine.LNX.4.64.1207171242230.17060@axis700.grange>
 <1343284293.1726.8966.camel@vkoul-udesk3>
 <Pine.LNX.4.64.1208021101350.11412@axis700.grange>
Message-ID: <1343988873.1726.14439.camel@vkoul-udesk3>

On Thu, 2012-08-02 at 11:11 +0200, Guennadi Liakhovetski wrote:
> > > +           chan = device->mux->request_chan(device, dev, direction, name);
> > NAK
> > 
> > 1. We dont want dmacs to have anything to do with filtering and
> > allocating. That is role of dmaengien and we need to add stuff there
> > only.
> > 2. Even if we start using optional name argument here we still don't
> > know out of 4 channels dmac supports which one to allocate.
> 
> I don't think we can be generic enough in the dmaengine core to identify 
> which channels are suitable for all slave requests. This is why I proposed 
> a concept of a DMA channel multiplexer driver, and this is exactly what 
> this callback is. I tried to explain this in the patch description above. 
> I thought we discussed this earlier in this thread and agreed, that a 
> multiplexer API is the way to go with channel allocation. I think, I 
> mentioned in one of my mails, that in the beginning I wanted to implement 
> multiplexers as a proper (platform) device, but at least one problem with 
> this is, that at least on my hardware the multiplexer and the DMAC share 
> registers, and an MFD seems an overkill for this, but we can discuss this. 
> I don't know, whether there are systems, where multiplexers are really 
> separate hardware blocks, if there are, we can think of a way to handle 
> those nicely too.
I would disagree.

As I have said in past, we need the mapping information to be available
with dmaengine for slave channels even before any slave allocation
occurs. This way dmaengine knows what to do with a channel.
I am planning to add the support in dmanegine for this...

The problem with this solution here is again how the hell will a dmac
know what to do with alloc request. It doesn't and any current way it
does is just a hack and nothing else. This also prevenrts us form
building genric dmac driver which should only know how to deal with dmac
only and nothing else.

-- 
~Vinod



From santosh.shilimkar at ti.com  Fri Aug  3 06:14:32 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 3 Aug 2012 15:44:32 +0530
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
Message-ID: <CAMQu2gz-93W9zWD_v3m1nQkqmnvFwcWKDTxNsf0v39y9_rhQPA@mail.gmail.com>

On Fri, Aug 3, 2012 at 3:34 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>
> Op 3 aug. 2012, om 11:42 heeft "Hiremath, Vaibhav" <hvaibhav at ti.com> het volgende geschreven:
>
>> On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
>>>
>>> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
>>>
>>>> On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>>>>>
>>>>> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>>>>>
>>>>>>
>>>>>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>>>>>>
>>>>>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>>>>>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>>>>>>>> that can handle events for both cpus.  This timer is used as the broadcast
>>>>>>>> clock-event when the per-cpu timer hardware stop in low power states.
>>>>>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>>>>>>>> set the irq to allow the clockevent core to determine the affinity of the
>>>>>>>> timer.
>>>>>>>
>>>>>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>>>>>>> breaks boot on my AM33xx board.
>>>>>>>
>>>>>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>>>>>>> below. With the entire series reverted, everything works again as
>>>>>>> expected. Any idea?
>>>>>>>
>>>>>>> The upstream commit ids are
>>>>>>>
>>>>>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>>>>>>> both cpus"
>>>>>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>>>>>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>>>>>>
>>>>>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>>>>>
>>>>> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
>>>>
>>>> This is really strange since CPUIDLE code is really OMAP4 specific.
>>>> obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
>>>>
>>>> May be omap2plus build some how the code gets executed on AMXX
>>>>
>>>> Can you try below and see if the boot with CPUIDLE enabled goes away on
>>>> AMXX
>>>>
>>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>>>> index ea24174..195e756 100644
>>>> --- a/arch/arm/mach-omap2/pm44xx.c
>>>> +++ b/arch/arm/mach-omap2/pm44xx.c
>>>> @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
>>>>       struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>>>>       struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
>>>>
>>>> +       if (!cpu_is_omap44xx())
>>>> +               return -ENODEV;
>>>> +
>>>>       if (omap_rev() == OMAP4430_REV_ES1_0) {
>>>>               WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
>>>>               return -ENODEV;
>>>
>>> That does seem to fix it:
>>>
>>> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
>>> CONFIG_CPU_IDLE=y
>>> CONFIG_CPU_IDLE_GOV_LADDER=y
>>> CONFIG_CPU_IDLE_GOV_MENU=y
>>> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
>>> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4
>>> CONFIG_ARCH_OMAP4=y
>>> CONFIG_MACH_OMAP4_PANDA=y
>>> # CONFIG_OMAP4_ERRATA_I688 is not set
>>> # CONFIG_KEYBOARD_OMAP4 is not set
>>> CONFIG_OMAP4_DSS_HDMI=y
>>>
>>
>> This patch is not required, Without this patch is works for me,
>
> I just retested and I don't need Santosh' patch, booting with cpuidle enable works now, after refreshing your patchset (and dropping the rtc commit, it conflicts with the other rtc patches out there).
>
Thanks Koen for confirming. That means the issues was coming from
additional patching on top of 3.6-rc1
where some patches were not refreshed for AMXX.

Regards
Santosh

Regards
Santosh


From mugunthanvnm at ti.com  Fri Aug  3 06:17:08 2012
From: mugunthanvnm at ti.com (N, Mugunthan V)
Date: Fri, 3 Aug 2012 10:17:08 +0000
Subject: Current state of AM33xx patches
In-Reply-To: <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
References: <4FD5BA4C.9070706@gmail.com> <4FE326A8.8090807@gmail.com>
 <4FE8AB37.7030907@gmail.com> <4FE9A00B.6010908@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA5B7FD@DBDE01.ent.ti.com>
 <4FEC7394.9030208@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA5FBC1@DBDE01.ent.ti.com>
 <4FEDF54D.4030609@gmail.com>
 <alpine.DEB.2.00.1206291938180.2338@utopia.booyaka.com>
 <4FEEC7F2.8070507@gmail.com>
 <alpine.DEB.2.00.1207040403010.6760@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA635DC@DBDE01.ent.ti.com>
 <4FF42761.2000701@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9C2548@DBDE01.ent.ti.com>
 <500CEF97.4050207@gmail.com>
 <EB1619762EAF8B4E97A227FB77B7E0293E9D04EB@DBDE01.ent.ti.com>
 <501159C3.3020109@gmail.com>
 <704C899A-606B-41A3-99E8-6D92C0EA5BC5@dominion.thruhere.net>
 <50116926.4060309@gmail.com>
 <587C7FB9-2DD3-48EE-B74D-BEBDF199BE23@dominion.thruhere.net>
 <50118272.1050209@gmail.com>
 <9F9237B3-55BD-471B-ADD1-1A18F3644387@dominion.thruhere.net>
 <501A9D1C.8080305@gmail.com>
 <98DC2F80-9AD6-4A65-8FA8-3B2AABF72692@dominion.thruhere.net>
Message-ID: <EB1619762EAF8B4E97A227FB77B7E0293E9D3BF8@DBDE01.ent.ti.com>

> -----Original Message-----
> From: Koen Kooi [mailto:koen at dominion.thruhere.net]
> Sent: Thursday, August 02, 2012 9:08 PM
> To: Daniel Mack
> Cc: N, Mugunthan V; Hiremath, Vaibhav; Paul Walmsley; Nori, Sekhar;
> Jason Kridner; Tony Lindgren; Hilman, Kevin; Hernandez, Carlos; Maupin,
> Chase; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Kridner, Jason
> Subject: Re: Current state of AM33xx patches
> 
> 
> Op 2 aug. 2012, om 17:30 heeft Daniel Mack <zonque at gmail.com> het
> volgende geschreven:
> 
> > On 31.07.2012 21:29, Koen Kooi wrote:
> >
> >> 2/3 of the way there:
> >>
> >> http://patchwork.ozlabs.org/patch/174085/
> >> http://patchwork.ozlabs.org/patch/174086/
> >>
> >> I keep failing to create a .dts that doesn't upset the dtc, so I
> don't have it working yet :(
> >
> > Yes, that's because there are couple of sytax errors in the example
> > bindings.
> 
> Not only that, it's actually missing params and other params are wrong.
> See my non-constructive rant in the commit message:
> http://dominion.thruhere.net/koen/angstrom/beaglebone/0001-beaglebone-
> add-broken-cpsw-DT.patch
> 
> But I still can't get it working:
> 
> root at beaglebone:~# dmesg | grep -i cpsw
> [   13.504425] net eth0: initializing cpsw version 1.12 (0)
> 
> root at beaglebone:~# dmesg | grep -i phy
> [    0.000000] Booting Linux on physical CPU 0
> [    0.228496] nop_usb_xceiv phy.17: transceiver type USB2 PHY already
> exists
> [   13.512056] libphy: PHY davinci_mdio-0:00 not found
> [   13.517168] net eth0: phy davinci_mdio-0:00 not found on slave 0
> [   13.523516] libphy: PHY davinci_mdio-0:01 not found
> [   13.528675] net eth0: phy davinci_mdio-0:01 not found on slave 1
> 
> root at beaglebone:~# ifconfig -a | grep eth
> eth0      Link encap:Ethernet  HWaddr 00:04:9F:01:1B:B8
> 
> > Mugunthan, could you repost these patches and at least copy
> > devicetree-discuss at lists.ozlabs.org and the ARM kernel mailing list?
> I
> > can't comment on the patches you sent to netdev at vger.kernel.org
> because
> > I'm not currently subscribed to that list.
> 
> 
> Same here, I'm only on l-o, but I guess I'll need to subscribe dt-
> discuss in the near future :)
> 
> regards,
> 
> Koen

I am not aware that the examples should simple be copy pastable and so had
a non compatible example. Will fix this in the next version and will be posting soon.

Regards
Mugunthan V N


From hvaibhav at ti.com  Fri Aug  3 06:23:25 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 10:23:25 +0000
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F664@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 15:34:25, Koen Kooi wrote:
> 
> Op 3 aug. 2012, om 11:42 heeft "Hiremath, Vaibhav" <hvaibhav at ti.com> het volgende geschreven:
> 
> > On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
> >> 
> >> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
> >> 
> >>> On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
> >>>> 
> >>>> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
> >>>> 
> >>>>> 
> >>>>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
> >>>>> 
> >>>>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
> >>>>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
> >>>>>>> that can handle events for both cpus.  This timer is used as the broadcast
> >>>>>>> clock-event when the per-cpu timer hardware stop in low power states.
> >>>>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> >>>>>>> set the irq to allow the clockevent core to determine the affinity of the
> >>>>>>> timer.
> >>>>>> 
> >>>>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> >>>>>> breaks boot on my AM33xx board.
> >>>>>> 
> >>>>>> Once I revert 1/3, the board boots again but crashes with the Ooops
> >>>>>> below. With the entire series reverted, everything works again as
> >>>>>> expected. Any idea?
> >>>>>> 
> >>>>>> The upstream commit ids are
> >>>>>> 
> >>>>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
> >>>>>> both cpus"
> >>>>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
> >>>>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
> >>>>> 
> >>>>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
> >>>> 
> >>>> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
> >>> 
> >>> This is really strange since CPUIDLE code is really OMAP4 specific.
> >>> obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
> >>> 
> >>> May be omap2plus build some how the code gets executed on AMXX
> >>> 
> >>> Can you try below and see if the boot with CPUIDLE enabled goes away on
> >>> AMXX
> >>> 
> >>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> >>> index ea24174..195e756 100644
> >>> --- a/arch/arm/mach-omap2/pm44xx.c
> >>> +++ b/arch/arm/mach-omap2/pm44xx.c
> >>> @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
> >>>       struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
> >>>       struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
> >>> 
> >>> +       if (!cpu_is_omap44xx())
> >>> +               return -ENODEV;
> >>> +
> >>>       if (omap_rev() == OMAP4430_REV_ES1_0) {
> >>>               WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
> >>>               return -ENODEV;
> >> 
> >> That does seem to fix it:
> >> 
> >> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
> >> CONFIG_CPU_IDLE=y
> >> CONFIG_CPU_IDLE_GOV_LADDER=y
> >> CONFIG_CPU_IDLE_GOV_MENU=y
> >> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
> >> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4   
> >> CONFIG_ARCH_OMAP4=y
> >> CONFIG_MACH_OMAP4_PANDA=y
> >> # CONFIG_OMAP4_ERRATA_I688 is not set
> >> # CONFIG_KEYBOARD_OMAP4 is not set
> >> CONFIG_OMAP4_DSS_HDMI=y
> >> 
> > 
> > This patch is not required, Without this patch is works for me,
> 
> I just retested and I don't need Santosh' patch, booting with cpuidle enable works now, after refreshing your patchset (and dropping the rtc commit, it conflicts with the other rtc patches out there).
> 

Thanks for conforming Koen.

> > 
> > [root at arago /]# cat /proc/version
> > Linux version 3.6.0-rc1-next-20120803-00010-g5f6bf0f (a0393758 at psplinux064) (gcc version 4.5.3 20110311 (prerelease) (GCC) ) #1 SMP Fri Aug 3 15:06:57 IST 2012
> > [root at arago /]#
> > 
> > 
> > 
> > Do you have below patch??
> > ARM: OMAP: cpu: Make cpu_class_is_omap2 true for all non-omap1 platforms
> > 
> > 
> > Also I have pushed branch (based on linux-next/master) to 
> > https://github.com/hvaibhav/am335x-linux/tree/am335x-linux-next-master
> 
> Thanks! Ajays USB work and AnilKumar's pinctrl work are there as branches, any plans to add da8xx-fb, rtc and networking branches? As you can see from the cpsw patches, they were impossible to test because the davinci_mdio ones were missing.
> 

Yes that's the plan, I am in the process of updating it.
Hopefully I will have branch for each major module.


Thanks,
Vaibhav



From hvaibhav at ti.com  Fri Aug  3 06:32:01 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 10:32:01 +0000
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <CAMQu2gzgfbeB0D18fKhmOaKUkY8Q_px+k9dq+jKEHc3YEuMMVQ@mail.gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <CAMQu2gzgfbeB0D18fKhmOaKUkY8Q_px+k9dq+jKEHc3YEuMMVQ@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F6AC@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 15:18:15, Shilimkar, Santosh wrote:
> On Fri, Aug 3, 2012 at 3:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
> >>
> >> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
> >>
> >> > On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
> >> >>
> >> >> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
> >> >>
> >> >>>
> >> >>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
> >> >>>
> >> >>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
> >> >>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
> >> >>>>> that can handle events for both cpus.  This timer is used as the broadcast
> >> >>>>> clock-event when the per-cpu timer hardware stop in low power states.
> >> >>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> >> >>>>> set the irq to allow the clockevent core to determine the affinity of the
> >> >>>>> timer.
> >> >>>>
> >> >>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> >> >>>> breaks boot on my AM33xx board.
> >> >>>>
> >> >>>> Once I revert 1/3, the board boots again but crashes with the Ooops
> >> >>>> below. With the entire series reverted, everything works again as
> >> >>>> expected. Any idea?
> >> >>>>
> >> >>>> The upstream commit ids are
> >> >>>>
> >> >>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
> >> >>>> both cpus"
> >> >>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
> >> >>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
> >> >>>
> >> >>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
> >> >>
> >> >> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
> >> >
> >> > This is really strange since CPUIDLE code is really OMAP4 specific.
> >> > obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
> >> >
> >> > May be omap2plus build some how the code gets executed on AMXX
> >> >
> >> > Can you try below and see if the boot with CPUIDLE enabled goes away on
> >> > AMXX
> >> >
> >> > diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> >> > index ea24174..195e756 100644
> >> > --- a/arch/arm/mach-omap2/pm44xx.c
> >> > +++ b/arch/arm/mach-omap2/pm44xx.c
> >> > @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
> >> >        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
> >> >        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
> >> >
> >> > +       if (!cpu_is_omap44xx())
> >> > +               return -ENODEV;
> >> > +
> >> >        if (omap_rev() == OMAP4430_REV_ES1_0) {
> >> >                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
> >> >                return -ENODEV;
> >>
> >> That does seem to fix it:
> >>
> >> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
> >> CONFIG_CPU_IDLE=y
> >> CONFIG_CPU_IDLE_GOV_LADDER=y
> >> CONFIG_CPU_IDLE_GOV_MENU=y
> >> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
> >> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4
> >> CONFIG_ARCH_OMAP4=y
> >> CONFIG_MACH_OMAP4_PANDA=y
> >> # CONFIG_OMAP4_ERRATA_I688 is not set
> >> # CONFIG_KEYBOARD_OMAP4 is not set
> >> CONFIG_OMAP4_DSS_HDMI=y
> >>
> >
> > This patch is not required, Without this patch is works for me,
> >
> Which is good news.Do you have CPUIDLE enabled in your build when you tested
> it. Note that CPUIDLE is not enabled by-default in omap2plus build and as I see
> from Koen's email, he did enable it in his testing.
> 
> Please confirm that 3.6-rc1 boots fine even with CPUIDLE enabled and
> we don't need
> the above mentioned patch. If it is not the case, I can post the fix.
> 

Just FYI, I have also tested with CPUIDLE enabled and it worked for me.

Thanks,
Vaibhav


From santosh.shilimkar at ti.com  Fri Aug  3 06:33:26 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 3 Aug 2012 16:03:26 +0530
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7F6AC@DBDE01.ent.ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <CAMQu2gzgfbeB0D18fKhmOaKUkY8Q_px+k9dq+jKEHc3YEuMMVQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA7F6AC@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gybwa13LU4rXGaXC-Q8NP4UwOwxkHSzxCg3kkEUD2wO6w@mail.gmail.com>

On Fri, Aug 3, 2012 at 4:02 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Fri, Aug 03, 2012 at 15:18:15, Shilimkar, Santosh wrote:
>> On Fri, Aug 3, 2012 at 3:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> > On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
>> >>
>> >> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
>> >>
>> >> > On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>> >> >>
>> >> >> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
>> >> >>
>> >> >>>
>> >> >>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
>> >> >>>
>> >> >>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
>> >> >>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
>> >> >>>>> that can handle events for both cpus.  This timer is used as the broadcast
>> >> >>>>> clock-event when the per-cpu timer hardware stop in low power states.
>> >> >>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
>> >> >>>>> set the irq to allow the clockevent core to determine the affinity of the
>> >> >>>>> timer.
>> >> >>>>
>> >> >>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
>> >> >>>> breaks boot on my AM33xx board.
>> >> >>>>
>> >> >>>> Once I revert 1/3, the board boots again but crashes with the Ooops
>> >> >>>> below. With the entire series reverted, everything works again as
>> >> >>>> expected. Any idea?
>> >> >>>>
>> >> >>>> The upstream commit ids are
>> >> >>>>
>> >> >>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
>> >> >>>> both cpus"
>> >> >>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
>> >> >>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
>> >> >>>
>> >> >>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
>> >> >>
>> >> >> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
>> >> >
>> >> > This is really strange since CPUIDLE code is really OMAP4 specific.
>> >> > obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
>> >> >
>> >> > May be omap2plus build some how the code gets executed on AMXX
>> >> >
>> >> > Can you try below and see if the boot with CPUIDLE enabled goes away on
>> >> > AMXX
>> >> >
>> >> > diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>> >> > index ea24174..195e756 100644
>> >> > --- a/arch/arm/mach-omap2/pm44xx.c
>> >> > +++ b/arch/arm/mach-omap2/pm44xx.c
>> >> > @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
>> >> >        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>> >> >        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
>> >> >
>> >> > +       if (!cpu_is_omap44xx())
>> >> > +               return -ENODEV;
>> >> > +
>> >> >        if (omap_rev() == OMAP4430_REV_ES1_0) {
>> >> >                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
>> >> >                return -ENODEV;
>> >>
>> >> That does seem to fix it:
>> >>
>> >> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
>> >> CONFIG_CPU_IDLE=y
>> >> CONFIG_CPU_IDLE_GOV_LADDER=y
>> >> CONFIG_CPU_IDLE_GOV_MENU=y
>> >> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
>> >> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4
>> >> CONFIG_ARCH_OMAP4=y
>> >> CONFIG_MACH_OMAP4_PANDA=y
>> >> # CONFIG_OMAP4_ERRATA_I688 is not set
>> >> # CONFIG_KEYBOARD_OMAP4 is not set
>> >> CONFIG_OMAP4_DSS_HDMI=y
>> >>
>> >
>> > This patch is not required, Without this patch is works for me,
>> >
>> Which is good news.Do you have CPUIDLE enabled in your build when you tested
>> it. Note that CPUIDLE is not enabled by-default in omap2plus build and as I see
>> from Koen's email, he did enable it in his testing.
>>
>> Please confirm that 3.6-rc1 boots fine even with CPUIDLE enabled and
>> we don't need
>> the above mentioned patch. If it is not the case, I can post the fix.
>>
>
> Just FYI, I have also tested with CPUIDLE enabled and it worked for me.
>
Thanks Vaibhav for update.

Regards
Santosh


From hvaibhav at ti.com  Fri Aug  3 06:34:28 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 3 Aug 2012 10:34:28 +0000
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <CAMQu2gz-93W9zWD_v3m1nQkqmnvFwcWKDTxNsf0v39y9_rhQPA@mail.gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
 <CAMQu2gz-93W9zWD_v3m1nQkqmnvFwcWKDTxNsf0v39y9_rhQPA@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA7F6C3@DBDE01.ent.ti.com>

On Fri, Aug 03, 2012 at 15:44:32, Shilimkar, Santosh wrote:
> On Fri, Aug 3, 2012 at 3:34 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
> >
> > Op 3 aug. 2012, om 11:42 heeft "Hiremath, Vaibhav" <hvaibhav at ti.com> het volgende geschreven:
> >
> >> On Fri, Aug 03, 2012 at 15:03:07, Koen Kooi wrote:
> >>>
> >>> Op 3 aug. 2012, om 11:27 heeft "Shilimkar, Santosh" <santosh.shilimkar at ti.com> het volgende geschreven:
> >>>
> >>>> On Fri, Aug 3, 2012 at 2:00 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
> >>>>>
> >>>>> Op 3 aug. 2012, om 09:21 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
> >>>>>
> >>>>>>
> >>>>>> Op 3 aug. 2012, om 09:16 heeft Daniel Mack <zonque at gmail.com> het volgende geschreven:
> >>>>>>
> >>>>>>> On 30.03.2012 15:27, Santosh Shilimkar wrote:
> >>>>>>>> For coupled cpuidle to work when both cpus are active, it needs a global timer
> >>>>>>>> that can handle events for both cpus.  This timer is used as the broadcast
> >>>>>>>> clock-event when the per-cpu timer hardware stop in low power states.
> >>>>>>>> Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
> >>>>>>>> set the irq to allow the clockevent core to determine the affinity of the
> >>>>>>>> timer.
> >>>>>>>
> >>>>>>> These patches made it to mainline now, shortly befor 3.6-rc1, and it
> >>>>>>> breaks boot on my AM33xx board.
> >>>>>>>
> >>>>>>> Once I revert 1/3, the board boots again but crashes with the Ooops
> >>>>>>> below. With the entire series reverted, everything works again as
> >>>>>>> expected. Any idea?
> >>>>>>>
> >>>>>>> The upstream commit ids are
> >>>>>>>
> >>>>>>> 11d6ec2e "ARM: OMAP: timer: allow gp timer clock-event to be used on
> >>>>>>> both cpus"
> >>>>>>> 5b4d5bcc "ARM: OMAP4: CPUidle: add synchronization for coupled idle states"
> >>>>>>> b93d70ae "ARM: OMAP4: CPUidle: Open broadcast clock-event device."
> >>>>>>
> >>>>>> I've had boot problems with cpuidle enabled as well, what happens if you disable it? Is the revert still needed in that case?
> >>>>>
> >>>>> To answer my own question: No, the reverts aren't needed if you disable cpuidle.
> >>>>
> >>>> This is really strange since CPUIDLE code is really OMAP4 specific.
> >>>> obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
> >>>>
> >>>> May be omap2plus build some how the code gets executed on AMXX
> >>>>
> >>>> Can you try below and see if the boot with CPUIDLE enabled goes away on
> >>>> AMXX
> >>>>
> >>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> >>>> index ea24174..195e756 100644
> >>>> --- a/arch/arm/mach-omap2/pm44xx.c
> >>>> +++ b/arch/arm/mach-omap2/pm44xx.c
> >>>> @@ -147,6 +147,9 @@ int __init omap4_pm_init(void)
> >>>>       struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
> >>>>       struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
> >>>>
> >>>> +       if (!cpu_is_omap44xx())
> >>>> +               return -ENODEV;
> >>>> +
> >>>>       if (omap_rev() == OMAP4430_REV_ES1_0) {
> >>>>               WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
> >>>>               return -ENODEV;
> >>>
> >>> That does seem to fix it:
> >>>
> >>> root at beaglebone:~# zcat /proc/config.gz | grep -i cpu_idle
> >>> CONFIG_CPU_IDLE=y
> >>> CONFIG_CPU_IDLE_GOV_LADDER=y
> >>> CONFIG_CPU_IDLE_GOV_MENU=y
> >>> CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
> >>> root at beaglebone:~# zcat /proc/config.gz | grep -i omap4
> >>> CONFIG_ARCH_OMAP4=y
> >>> CONFIG_MACH_OMAP4_PANDA=y
> >>> # CONFIG_OMAP4_ERRATA_I688 is not set
> >>> # CONFIG_KEYBOARD_OMAP4 is not set
> >>> CONFIG_OMAP4_DSS_HDMI=y
> >>>
> >>
> >> This patch is not required, Without this patch is works for me,
> >
> > I just retested and I don't need Santosh' patch, booting with cpuidle enable works now, after refreshing your patchset (and dropping the rtc commit, it conflicts with the other rtc patches out there).
> >
> Thanks Koen for confirming. That means the issues was coming from
> additional patching on top of 3.6-rc1
> where some patches were not refreshed for AMXX.
> 

Actually its not that.
AM335x needs to be added as part of cpu_class_is_omap2(), without this it 
gets into issues. 
The patch has been already submitted to the list, but still not merged by 
Tony.

Thanks,
Vaibhav


From g.liakhovetski at gmx.de  Fri Aug  3 06:35:37 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 3 Aug 2012 12:35:37 +0200 (CEST)
Subject: [PATCH/RFC 1/4] dma: add a function to request a DMA channel
 for a specific client
In-Reply-To: <1343988873.1726.14439.camel@vkoul-udesk3>
References: <Pine.LNX.4.64.1207171201550.11241@axis700.grange> 
 <Pine.LNX.4.64.1207171242230.17060@axis700.grange>
 <1343284293.1726.8966.camel@vkoul-udesk3>
 <Pine.LNX.4.64.1208021101350.11412@axis700.grange>
 <1343988873.1726.14439.camel@vkoul-udesk3>
Message-ID: <Pine.LNX.4.64.1208031220460.5170@axis700.grange>

On Fri, 3 Aug 2012, Vinod Koul wrote:

> On Thu, 2012-08-02 at 11:11 +0200, Guennadi Liakhovetski wrote:
> > > > +           chan = device->mux->request_chan(device, dev, direction, name);
> > > NAK
> > > 
> > > 1. We dont want dmacs to have anything to do with filtering and
> > > allocating. That is role of dmaengien and we need to add stuff there
> > > only.
> > > 2. Even if we start using optional name argument here we still don't
> > > know out of 4 channels dmac supports which one to allocate.
> > 
> > I don't think we can be generic enough in the dmaengine core to identify 
> > which channels are suitable for all slave requests. This is why I proposed 
> > a concept of a DMA channel multiplexer driver, and this is exactly what 
> > this callback is. I tried to explain this in the patch description above. 
> > I thought we discussed this earlier in this thread and agreed, that a 
> > multiplexer API is the way to go with channel allocation. I think, I 
> > mentioned in one of my mails, that in the beginning I wanted to implement 
> > multiplexers as a proper (platform) device, but at least one problem with 
> > this is, that at least on my hardware the multiplexer and the DMAC share 
> > registers, and an MFD seems an overkill for this, but we can discuss this. 
> > I don't know, whether there are systems, where multiplexers are really 
> > separate hardware blocks, if there are, we can think of a way to handle 
> > those nicely too.
> I would disagree.
> 
> As I have said in past, we need the mapping information to be available
> with dmaengine for slave channels even before any slave allocation
> occurs. This way dmaengine knows what to do with a channel.

I think, this depends on our interpretation of what struct dma_chan 
represents and who has control over it. If we think, that this is a 
purely software object, which at allocation time has absolutely no 
hardware association attached to it, then yes, only the dmaengine core 
should manage them at least at that time. If, however, we define, that 
struct dma_chan _can_ get hardware association already at allocation time 
in the context of DMAC's .alloc_chan_resources() function, then it's 
the DMAC that has to manage them.

And, I think, there is one important aspect to this, that tells us, that 
those channels cannot be absolutely hardware-agnostic: they are attached 
to DMAC instances. So, they intrinsically have some hardware association.

So, you have to take into account hardware limitations already at 
allocation time. You can do this by either asking the DMAC, whether a 
certain allocation can be performed (what we currently do with filters, 
and what this patch proposed to do with the multiplexer callback), or you 
can require some static information from DMACs, like a mapping that you 
propose.

Currently both approaches seem possible, however, a static mapping seems 
less flexible to me, I don't know whether it can describe all available 
hardware configurations. We shouldn't forget, that those mappings can be 
many-to-many, as in the sh-dma example. On sh-dma it would suffice and be 
optimal enough to have a pointer to a slave list in struct dma_chan. Would 
this also suit everyone else? Is this what you're thinking about?

Thanks
Guennadi

> I am planning to add the support in dmanegine for this...
> 
> The problem with this solution here is again how the hell will a dmac
> know what to do with alloc request. It doesn't and any current way it
> does is just a hack and nothing else. This also prevenrts us form
> building genric dmac driver which should only know how to deal with dmac
> only and nothing else.
> 
> -- 
> ~Vinod
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From will.deacon at arm.com  Fri Aug  3 07:45:32 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 3 Aug 2012 12:45:32 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120803090452.GE2626@pengutronix.de>
References: <20120803090452.GE2626@pengutronix.de>
Message-ID: <20120803114532.GB26925@mudshark.cambridge.arm.com>

On Fri, Aug 03, 2012 at 10:04:52AM +0100, Uwe Kleine-K?nig wrote:
> Hello,

Hi Uwe,

> in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have
> 
> 	.arm
>  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
>  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
>  THUMB( .thumb                  )       @ switch to Thumb now.
>  THUMB(1:                       )
> 
> as first instructions at the entry point. This is a problem for
> thumb2-only cpus (e.g. Cortex-M3).

Yup, Documentation/arm/Booting mentions this too.

> Up to now I commented out the first three lines for the Cortex-M3 port.
> What should we do about that. There are two possibilities I see:
> 
>  a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
>     first three lines out if it is given.
>  b) expect the bootloader to directly jump to the label 1.
> 
> The downside of a) is that a boot loader on a cpu that is capable to
> execute the tradtional instructions would need to detect if the switch
> to thumb is there or not and react accordingly. (In fact it needs to
> distringuish three cases:
> 
>  - traditional kernel
>  - thumb2 kernel with ARM entry
>  - thumb2 kernel without ARM entry
> 
> .) So I think b) is the more sensible option in the long run.
> 
> What do you think?

How about something like:


diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 835898e..9f07be2 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,7 @@
        __HEAD
 ENTRY(stext)
 
+ THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
  THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
  THUMB(        .thumb                  )       @ switch to Thumb now.


[thanks to Leif Lindholm for doing this in one instruction]

Will


From javier.martin at vista-silicon.com  Fri Aug  3 08:08:23 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  3 Aug 2012 14:08:23 +0200
Subject: [PATCH v2] Visstrim SM10: Use mo_version to decide board video mode.
Message-ID: <1343995703-13578-1-git-send-email-javier.martin@vista-silicon.com>

If the mother board version number is odd, emmaprp() for
format conversion + UVC camera will be used.

Otherwise mx2_camera and m2m-deinterlacer will be registered.

For both cases Coda video codec is registered.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
Changes since v1:
 - Add error message to emmaprp init function.

---
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   54 ++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 176533e..dbb344a 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -49,6 +49,10 @@
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
 
+#define VERSION_MASK		0x7
+#define MOTHERBOARD_SHIFT	4
+#define EXPBOARD_SHIFT		0
+
 #define MOTHERBOARD_BIT2	(GPIO_PORTD + 31)
 #define MOTHERBOARD_BIT1	(GPIO_PORTD + 30)
 #define MOTHERBOARD_BIT0	(GPIO_PORTD + 29)
@@ -205,7 +209,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
 static phys_addr_t mx2_camera_base __initdata;
 #define MX2_CAMERA_BUF_SIZE SZ_8M
 
-static void __init visstrim_camera_init(void)
+static void __init visstrim_analog_camera_init(void)
 {
 	struct platform_device *pdev;
 	int dma;
@@ -442,6 +446,29 @@ static void __init visstrim_deinterlace_init(void)
 		return;
 }
 
+/* Emma-PrP for format conversion */
+static void __init visstrim_emmaprp_init(void)
+{
+	struct platform_device *pdev;
+	int dma;
+
+	pdev = imx27_add_mx2_emmaprp();
+	if (IS_ERR(pdev))
+		return;
+
+	/*
+	 * Use the same memory area as the analog camera since both
+	 * devices are, by nature, exclusive.
+	 */
+	dma = dma_declare_coherent_memory(&pdev->dev,
+				mx2_camera_base, mx2_camera_base,
+				MX2_CAMERA_BUF_SIZE,
+				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+	if (!(dma & DMA_MEMORY_MAP)) {
+		pr_err("Failed to declare memory for emmaprp\n");
+		return;
+	}
+}
 
 static void __init visstrim_m10_revision(void)
 {
@@ -467,13 +494,14 @@ static void __init visstrim_m10_revision(void)
 	mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
 
 	system_rev = 0x27000;
-	system_rev |= (mo_version << 4);
-	system_rev |= exp_version;
+	system_rev |= (mo_version << MOTHERBOARD_SHIFT);
+	system_rev |= (exp_version << EXPBOARD_SHIFT);
 }
 
 static void __init visstrim_m10_board_init(void)
 {
 	int ret;
+	int mo_version;
 
 	imx27_soc_init();
 	visstrim_m10_revision();
@@ -505,8 +533,24 @@ static void __init visstrim_m10_board_init(void)
 	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
 				      &iclink_tvp5150, sizeof(iclink_tvp5150));
 	gpio_led_register_device(0, &visstrim_m10_led_data);
-	visstrim_deinterlace_init();
-	visstrim_camera_init();
+
+	/* Use mother board version to decide what video devices we shall use */
+	mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
+	if (mo_version & 0x1) {
+		visstrim_emmaprp_init();
+
+		/*
+		 * Despite not being used, tvp5150 must be
+		 * powered on to avoid I2C problems. To minimize
+		 * power consupmtion keep reset enabled.
+		 */
+		gpio_set_value(TVP5150_PWDN, 1);
+		ndelay(1);
+		gpio_set_value(TVP5150_RSTN, 0);
+	} else {
+		visstrim_deinterlace_init();
+		visstrim_analog_camera_init();
+	}
 	visstrim_coda_init();
 }
 
-- 
1.7.9.5



From shawn.guo at linaro.org  Fri Aug  3 08:25:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 20:25:18 +0800
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803122516.GA23791@S2101-09.ap.freescale.net>

On Thu, Aug 02, 2012 at 05:39:02PM +0200, Uwe Kleine-K?nig wrote:
> +enum imx35_pads {
> +	/* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */

I'm not sure we want to keep a reference to
arch/arm/plat-mxc/include/mach/iomux-mx35.h that is to be removed.

How about moving the comment into commit message?

-- 
Regards,
Shawn



From sourav.poddar at ti.com  Fri Aug  3 08:35:50 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:05:50 +0530
Subject: [PATCH] hwmon: tmp102: Add device tree support
Message-ID: <1343997350-676-1-git-send-email-sourav.poddar@ti.com>

update tmp102 temperature sensor to also use device tree.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/hwmon/tmp102.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c
index 0d466b9..a8a9060 100644
--- a/drivers/hwmon/tmp102.c
+++ b/drivers/hwmon/tmp102.c
@@ -26,6 +26,7 @@
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/device.h>
+#include <linux/of.h>
 
 #define	DRIVER_NAME "tmp102"
 
@@ -284,8 +285,19 @@ static const struct i2c_device_id tmp102_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, tmp102_id);
 
+#ifdef CONFIG_OF
+static const struct of_device_id temperature_dt_match[] = {
+	{ .compatible = "ti,tmp102" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, temperature_dt_match);
+#endif
+
 static struct i2c_driver tmp102_driver = {
-	.driver.name	= DRIVER_NAME,
+	.driver	= {
+		.name =	DRIVER_NAME,
+		.of_match_table = of_match_ptr(temperature_dt_match),
+	},
 	.driver.pm	= TMP102_DEV_PM_OPS,
 	.probe		= tmp102_probe,
 	.remove		= __devexit_p(tmp102_remove),
-- 
1.7.1



From sourav.poddar at ti.com  Fri Aug  3 08:38:02 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:08:02 +0530
Subject: [PATCH 0/4] Add device tree data for omap5  
Message-ID: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>

The following patch series add i2c support for omap5.
As well as enable I2C based devices like pressure and temperature
through device tree. Also add onchip keypad dts data.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>

Sourav Poddar (4):
  arm/dts: omap5-evm: Add I2C support
  arm/dts: omap5-evm: Add tmp102 sensor support
  arm/dts: omap5-evm: Add keypad data
  arm/dts: omap5-evm: Add bmp085 sensor support

 arch/arm/boot/dts/omap5-evm.dts |   30 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 0 deletions(-)



From sourav.poddar at ti.com  Fri Aug  3 08:38:03 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:08:03 +0530
Subject: [PATCH 1/4] arm/dts: omap5-evm: Add I2C support
In-Reply-To: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1343997486-710-2-git-send-email-sourav.poddar@ti.com>

Add I2C data node in omap5 device tree file.

Tested on omap5430 sdp.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..6b68dfe 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -145,6 +145,41 @@
 			#interrupt-cells = <1>;
 		};
 
+		i2c1: i2c at 48070000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c1";
+		};
+
+		i2c2: i2c at 48072000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c2";
+		};
+
+		i2c3: i2c at 48060000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c3";
+		};
+
+		i2c4: i2c at 4807A000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c4";
+		};
+
+		i2c5: i2c at 4807C000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c5";
+		};
+
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			ti,hwmods = "uart1";
-- 
1.7.1



From sourav.poddar at ti.com  Fri Aug  3 08:38:04 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:08:04 +0530
Subject: [PATCH 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1343997486-710-3-git-send-email-sourav.poddar@ti.com>

Add tmp102 temperature sensor data in omap5 evm dts file.

Tested on omap5430 sdp with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39a..45a8aeb 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -18,3 +18,12 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 };
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	tmp102 at 48{
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Fri Aug  3 08:38:06 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:08:06 +0530
Subject: [PATCH 4/4] arm/dts: omap5-evm: Add bmp085 sensor support
In-Reply-To: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1343997486-710-5-git-send-email-sourav.poddar@ti.com>

Add bmp085 pressure sensor data in omap5 evm dts file.

Tested on omap5430 sdp with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 09fe941..956eba0 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -39,3 +39,12 @@
 		reg = <0x48>;
 	};
 };
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	bmp085 at 77 {
+		compatible = "bosch,bmp085";
+		reg = <0x77>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Fri Aug  3 08:38:05 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 3 Aug 2012 18:08:05 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1343997486-710-4-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap5 device tree file.
Also fill the device tree binding parameters
with the required value in "omap5-evm" dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |    5 +++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 45a8aeb..09fe941 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,6 +17,18 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	keypad {
+		keypad,num-rows = <8>;
+		keypad,num-columns = <8>;
+		linux,keymap = < 0x02020073
+			0x02030072
+			0x020400e7
+			0x02050066
+			0x0206006b
+			0x020700d9 >;
+		linux,input-no-autorepeat;
+	};
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6b68dfe..c38b823 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -216,4 +216,9 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	keypad {
+		compatible = "ti,omap4-keypad";
+		ti,hwmods = "kbd";
+	};
 };
-- 
1.7.1



From javier.martin at vista-silicon.com  Fri Aug  3 08:48:12 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Fri, 3 Aug 2012 14:48:12 +0200
Subject: Vacations.
Message-ID: <CACKLOr1Q6_xVhaaoWiy-kf9hViTW98aSa6hd5M2z7ogL-uwNVQ@mail.gmail.com>

Hi,
I will be out of the office until August the 19th.

I just wanted to send a reminder of some patches that I have pending.

For Mauro 3.7:

[PULL] video_visstrim for 3.6
[PATCH] media: i.MX27: Fix mx2_emmaprp mem2mem driver clocks.

For Guennadi:

[PATCH 1/4] i.MX27: Fix emma-prp and csi clocks.
[PATCH 2/4] media: mx2_camera: Mark i.MX25 support as BROKEN.
[PATCH 3/4] Schedule removal of i.MX25 support in mx2_camera.c
[PATCH v2] media: mx2_camera: Fix clock handling for i.MX27.

For Sascha:

[PATCH v2] Visstrim SM10: Use mo_version to decide board video mode.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From koen at dominion.thruhere.net  Fri Aug  3 08:50:22 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 3 Aug 2012 14:50:22 +0200
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
Message-ID: <D32DBB77-844C-400A-9E3F-3F779431D1C7@dominion.thruhere.net>


Op 3 aug. 2012, om 14:38 heeft Sourav Poddar <sourav.poddar at ti.com> het volgende geschreven:

> Add keypad data node in omap5 device tree file.
> Also fill the device tree binding parameters
> with the required value in "omap5-evm" dts file.
> 
> Tested on omap5430 evm with 3.5 custom kernel.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
> arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
> arch/arm/boot/dts/omap5.dtsi    |    5 +++++
> 2 files changed, 17 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
> index 45a8aeb..09fe941 100644
> --- a/arch/arm/boot/dts/omap5-evm.dts
> +++ b/arch/arm/boot/dts/omap5-evm.dts
> @@ -17,6 +17,18 @@
> 		device_type = "memory";
> 		reg = <0x80000000 0x40000000>; /* 1 GB */
> 	};
> +
> +	keypad {
> +		keypad,num-rows = <8>;
> +		keypad,num-columns = <8>;
> +		linux,keymap = < 0x02020073
> +			0x02030072
> +			0x020400e7
> +			0x02050066
> +			0x0206006b
> +			0x020700d9 >;
> +		linux,input-no-autorepeat;
> +	};

This not a criticism on your patch, but a generic question about DT: Is there no way to have nice constants for keys like we have in the kernel, like KEY_POWER, KEY_UP, etc? If no, does DT allow comments so I can look at a dts and see which keycodes are mapped instead of having to dig up the sources?

regards,

Koen

From s.hauer at pengutronix.de  Fri Aug  3 09:05:09 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 15:05:09 +0200
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803130509.GO1451@pengutronix.de>

On Thu, Aug 02, 2012 at 05:56:25PM +0200, Uwe Kleine-K?nig wrote:
> From: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> 
> This patch adds basic support for imx35-based devices to the kernel.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/dts/imx35.dtsi            |  246 +++++++++++++++++++++++++++++++
>  arch/arm/configs/imx_v6_v7_defconfig    |    1 +
>  arch/arm/mach-imx/Kconfig               |   13 ++
>  arch/arm/mach-imx/Makefile              |    1 +
>  arch/arm/mach-imx/imx35-dt.c            |  119 +++++++++++++++
>  arch/arm/plat-mxc/include/mach/common.h |    2 +
>  6 files changed, 382 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx35.dtsi
>  create mode 100644 arch/arm/mach-imx/imx35-dt.c
> 

> diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
> new file mode 100644
> index 0000000..8b9cc84
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx35-dt.c
> @@ -0,0 +1,119 @@
> +/*
> + * Copyright 2012 Steffen Trumtrar, Pengutronix
> + *
> + * based on imx27-dt.c
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/pinctrl/machine.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +#include <mach/mx35.h>
> +
> +static const struct of_dev_auxdata imx35_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART1_BASE_ADDR, "imx21-uart.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART2_BASE_ADDR, "imx21-uart.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART3_BASE_ADDR, "imx21-uart.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-fec", MX35_FEC_BASE_ADDR, "imx27-fec.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-wdt", MX35_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx35.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx35.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx35.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-nand", MX35_NFC_BASE_ADDR, "mxc_nand.0", NULL),
> +	{ /* sentinel */ }
> +};
> +
> +static int __init imx35_avic_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
> +	return 0;
> +}
> +
> +static int __init imx35_gpio_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
> +
> +	gpio_irq_base -= 32;
> +	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
> +				NULL);
> +
> +	return 0;
> +}

The gpio/irq drivers now call irq_domain_add_legacy themselves.

> +
> +static const struct of_device_id imx35_irq_match[] __initconst = {
> +	{ .compatible = "fsl,imx35-avic", .data = imx35_avic_add_irq_domain, },
> +	{ .compatible = "fsl,imx35-gpio", .data = imx35_gpio_add_irq_domain, },
> +	{ /* sentinel */ }
> +};
> +
> +static const struct of_device_id imx35_of_mixed_devices_match[] __initconst = {
> +	{ /* END OF LIST */ }
> +};
> +
> +static void __init of_mixed_device_hook(void)
> +{
> +	struct device_node *np;
> +	const struct of_device_id *of_id;
> +
> +	np = of_find_matching_node(NULL, imx35_of_mixed_devices_match);
> +	if (np) {
> +		void (*func)(void);
> +
> +		of_id = of_match_node(imx35_of_mixed_devices_match, np);
> +		func = of_id->data;
> +		func();
> +	}
> +}

What is the intention of this? I suppose currently it does nothing,
right?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sourav.poddar at ti.com  Fri Aug  3 09:06:04 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Fri, 3 Aug 2012 18:36:04 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <D32DBB77-844C-400A-9E3F-3F779431D1C7@dominion.thruhere.net>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
 <D32DBB77-844C-400A-9E3F-3F779431D1C7@dominion.thruhere.net>
Message-ID: <CAKdam54HpC33Bk8gDjRRcB+9=O8Dh4UAKhY4mpHBdvk_uEj9uQ@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 6:20 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>
> Op 3 aug. 2012, om 14:38 heeft Sourav Poddar <sourav.poddar at ti.com> het volgende geschreven:
>
>> Add keypad data node in omap5 device tree file.
>> Also fill the device tree binding parameters
>> with the required value in "omap5-evm" dts file.
>>
>> Tested on omap5430 evm with 3.5 custom kernel.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Acked-by: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>> arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
>> arch/arm/boot/dts/omap5.dtsi    |    5 +++++
>> 2 files changed, 17 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
>> index 45a8aeb..09fe941 100644
>> --- a/arch/arm/boot/dts/omap5-evm.dts
>> +++ b/arch/arm/boot/dts/omap5-evm.dts
>> @@ -17,6 +17,18 @@
>>               device_type = "memory";
>>               reg = <0x80000000 0x40000000>; /* 1 GB */
>>       };
>> +
>> +     keypad {
>> +             keypad,num-rows = <8>;
>> +             keypad,num-columns = <8>;
>> +             linux,keymap = < 0x02020073
>> +                     0x02030072
>> +                     0x020400e7
>> +                     0x02050066
>> +                     0x0206006b
>> +                     0x020700d9 >;
>> +             linux,input-no-autorepeat;
>> +     };
>
> This not a criticism on your patch, but a generic question about DT: Is there no way to have nice constants for keys like we have in the kernel, like KEY_POWER, KEY_UP, etc?
There is way, something like this ..
               key_C {
                       keypad,row = <2>;
                       keypad,column = <1>;
                       linux,code = <46>;
               };
But its not the preferred approach mainly because of the fact that
it is too big. So suppose, if we have 100 key codes, we will have
400 -500 lines of code in our dts file for the mapping only.
 If no, does DT allow comments so I can look at a dts and see which
keycodes are mapped instead of having to dig up the sources?
Yes, comments are allowed and seems to be better option to do.

~Sourav
>
> regards,
>
> Koen


From s.hauer at pengutronix.de  Fri Aug  3 09:07:55 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 15:07:55 +0200
Subject: [PATCH 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1343922986-32469-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1343922986-32469-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803130755.GP1451@pengutronix.de>

On Thu, Aug 02, 2012 at 05:56:26PM +0200, Uwe Kleine-K?nig wrote:
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/dts/phytec-pcm043.dtsi |   49 ++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 arch/arm/boot/dts/phytec-pcm043.dtsi
> 
> diff --git a/arch/arm/boot/dts/phytec-pcm043.dtsi b/arch/arm/boot/dts/phytec-pcm043.dtsi
> new file mode 100644
> index 0000000..420627c
> --- /dev/null
> +++ b/arch/arm/boot/dts/phytec-pcm043.dtsi
> @@ -0,0 +1,49 @@
> +/include/ "imx35.dtsi"
> +
> +/ {
> +	soc {
> +		aips at 40000000 { /* AIPS1 */
> +			i2c at 43f80000 {
> +				status = "okay";
> +
> +				tempsens at 4a {
> +					compatible = "maxim,ds75";
> +					reg = <0x4a>;
> +				};
> +				rtc8564 at 51 {
> +					compatible = "nxp,pcf8563";
> +					reg = <0x51>;
> +				};
> +				at24 at 52 {
> +					compatible = "at,24c32";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};
> +			};
> +			uart at 43f90000 {
> +				status = "okay";
> +			};
> +			uart at 43f94000 {
> +				status = "okay";
> +			};
> +		};
> +		spba at 50000000 {
> +			uart at 5000c000 {
> +				status = "okay";
> +			};
> +			fec at 50038000 {
> +				status = "okay";
> +			};
> +		};
> +
> +		nor at a0000000 {
> +			compatible = "cfi-flash";
> +			reg = <0xa0000000 0x2000000>;
> +			bank-width = <2>;
> +		};
> +
> +		nand at bb000000 {
> +			status = "okay";
> +		};

Enable hardware ECC?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:10:26 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 15:10:26 +0200
Subject: arm: mvebu: Add basic address decoding support for Marvell 370/XP
Message-ID: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>

Andrew, Jason, Gr?gory,

Here is a small patch set that introduces basic support for address
decoding on Armada 370 and Armada XP. The aim of this basic support is
essentially to be able to configure a window to remap the BootROM,
which is needed to startup the secondary CPUs for the SMP support.

As we had discussed already, the address decoding configuration is not
described in the Device Tree, it is for now hardcoded on a per-SoC
basis. We might later discuss how to extend this to the Device Tree.

This patch set has four patches:

 (*) First patch introducing PLAT_ORION_LEGACY, which allows the
     Marvell 370/XP platforms to be part of PLAT_ORION, and therefore
     re-use the existing address decoding code.

 (*) Second patch making a small change to an address decoding
     structure so that we can define at runtime the virtual address of
     the configuration registers. This is needed as on Armada 370/XP
     the address decoding "controller" is declared in the Device Tree.

 (*) Third patch adding the 370/XP address decoding code itself. For
     now, it only maps the BootROM on Armada XP.

 (*) Fourth path adding the necessary DT code to instantiate the
     address decoding "controller".

Thanks,

Thomas Petazzoni



From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:10:27 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 15:10:27 +0200
Subject: [PATCH 1/4] arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
 config option
In-Reply-To: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1343999430-31816-2-git-send-email-thomas.petazzoni@free-electrons.com>

Until now, the PLAT_ORION configuration option was common to all the
Marvell EBU SoCs, and selecting this option had the effect of enabling
the MPP code, GPIO code, address decoding and PCIe code from
plat-orion, as well as providing access to driver-specific header
files from plat-orion/include.

However, the Armada 370 and XP SoCs will not use the MPP and GPIO code
(instead some proper pinctrl and gpio drivers are in preparation), and
generally, we want to move away from plat-orion and instead have
everything in mach-mvebu.

That said, in the mean time, we want to leverage the driver-specific
headers as well as the address decoding code, so we introduce
PLAT_ORION_LEGACY. The older Marvell SoCs need to select
PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select
PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it
automatically selects PLAT_ORION.

Then, with just PLAT_ORION, you have the address decoding code plus
the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you
gain the old MPP, GPIO and PCIe code.

Again, this is only a temporary solution until we make all Marvell EBU
platforms converge into the mach-mvebu directory. This solution avoids
duplicating the existing address decoding code into mach-mvebu.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/Kconfig             |   13 +++++++++----
 arch/arm/plat-orion/Makefile |    9 ++++-----
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7980873..fc36a93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PLAT_ORION
 	help
 	  Support for the Marvell SoC Family with device tree support
 
@@ -583,7 +584,7 @@ config ARCH_DOVE
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
@@ -594,7 +595,7 @@ config ARCH_KIRKWOOD
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.
@@ -621,7 +622,7 @@ config ARCH_MV78XX0
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.
@@ -634,7 +635,7 @@ config ARCH_ORION5X
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Orion 5x series SoCs:
 	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1153,6 +1154,10 @@ config PLAT_ORION
 	select GENERIC_IRQ_CHIP
 	select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+	bool
+	select PLAT_ORION
+
 config PLAT_PXA
 	bool
 
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f..1251e5b 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,9 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m	:=
-obj-n	:=
-obj-	:=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:10:28 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 15:10:28 +0200
Subject: [PATCH 2/4] arm: plat-orion: make bridge_virt_base non-const to
 support DT use case
In-Reply-To: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>

For the Armada 370 and XP SoCs where the DT is used, we need to fill
at runtime the bridge_virt_base field on the
orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this
field.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/plat-orion/include/plat/addr-map.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f7..aafdd79 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	const u32 bridge_virt_base;
+	u32 bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:10:29 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 15:10:29 +0200
Subject: [PATCH 3/4] arm: mvebu: add basic address decoding support to Armada
 370/XP
In-Reply-To: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1343999430-31816-4-git-send-email-thomas.petazzoni@free-electrons.com>

This commit adds basic support for address decoding configuration for
the Armada 370 and Armada XP SoCs, re-using the infrastructure
provided in plat-orion.

For now, only a BootROM window is configured on Armada XP, which is
needed to get the non-boot CPUs started and is therefore a requirement
for SMP support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-mvebu/Makefile   |    2 +-
 arch/arm/mach-mvebu/addr-map.c |  134 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mvebu/addr-map.c

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8..2143558 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,2 @@
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 0000000..7eeb438
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS	1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1		3
+#define ARMADA_XP_TARGET_PCIE_0_2	4
+#define ARMADA_XP_TARGET_ETH0		7
+#define ARMADA_XP_TARGET_PCIE_1_3	8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+	/*
+	 * Window for the BootROM, needed for SMP on Armada XP
+	 */
+	{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+	  ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+	{ .compatible = "marvell,armada-addr-decoding-controller" },
+	{ /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+	unsigned int offset;
+
+	/* The register layout is a bit annoying and the below code
+	 * tries to cope with it.
+	 * - At offset 0x0, there are the registers for the first 8
+	 *   windows, with 4 registers of 32 bits per window (ctrl,
+	 *   base, remap low, remap high)
+	 * - Then at offset 0x80, there is a hole of 0x10 bytes for
+	 *   the internal registers base address and internal units
+	 *   sync barrier register.
+	 * - Then at offset 0x90, there the registers for 12
+	 *   windows, with only 2 registers of 32 bits per window
+	 *   (ctrl, base).
+	 */
+	if (win < 8)
+		offset = (win << 4);
+	else
+		offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+	return (void __iomem *)(cfg->bridge_virt_base + offset);
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+	.num_wins = 20,
+	.remappable_wins = 8,
+	.win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+	struct device_node *np;
+	void __iomem *mbus_unit_addr_decoding_base;
+	void __iomem *sdram_addr_decoding_base;
+
+	np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+	if (!np)
+		return -ENODEV;
+
+	mbus_unit_addr_decoding_base = of_iomap(np, 0);
+	BUG_ON(!mbus_unit_addr_decoding_base);
+
+	sdram_addr_decoding_base =
+		mbus_unit_addr_decoding_base +
+		ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+	addr_map_cfg.bridge_virt_base = (u32) mbus_unit_addr_decoding_base;
+
+	/*
+	 * Disable, clear and configure windows.
+	 */
+	if (of_machine_is_compatible("marvell,armadaxp"))
+		orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+	else if (of_machine_is_compatible("marvell,armada370"))
+		orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+	else {
+		pr_err("Unsupported SoC\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (u32) sdram_addr_decoding_base);
+	return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:10:30 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 15:10:30 +0200
Subject: [PATCH 4/4] arm: mvebu: add address decoding controller to the DT
In-Reply-To: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1343999430-31816-5-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..16cc82c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+		addr-decoding at d0020000 {
+			compatible = "marvell,armada-addr-decoding-controller";
+			reg = <0xd0020000 0x258>;
+		};
 	};
 };
 
-- 
1.7.9.5



From shawn.guo at linaro.org  Fri Aug  3 09:12:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 21:12:32 +0800
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803131230.GB23791@S2101-09.ap.freescale.net>

On Thu, Aug 02, 2012 at 05:56:25PM +0200, Uwe Kleine-K?nig wrote:
> From: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> 
> This patch adds basic support for imx35-based devices to the kernel.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/dts/imx35.dtsi            |  246 +++++++++++++++++++++++++++++++
>  arch/arm/configs/imx_v6_v7_defconfig    |    1 +
>  arch/arm/mach-imx/Kconfig               |   13 ++
>  arch/arm/mach-imx/Makefile              |    1 +
>  arch/arm/mach-imx/imx35-dt.c            |  119 +++++++++++++++
>  arch/arm/plat-mxc/include/mach/common.h |    2 +
>  6 files changed, 382 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx35.dtsi
>  create mode 100644 arch/arm/mach-imx/imx35-dt.c
> 
> diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
> new file mode 100644
> index 0000000..d0c6456
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx35.dtsi
> @@ -0,0 +1,246 @@
> +/*
> + * Copyright 2012 Steffen Trumtrar, Pengutronix
> + *
> + * based on imx27.dtsi
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	aliases {
> +		serial0 = &uart1;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +	};
> +
> +	avic: avic-interrupt-controller at 68000000 {
> +		compatible = "fsl,imx35-avic", "fsl,avic";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		reg = <0x68000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ckil {
> +			compatible = "fsl,imx-ckil", "fixed-clock";
> +			clock-frequency = <32768>;
> +		};
> +
> +		osc {
> +			compatible = "fsl,imx-osc", "fixed-clock";
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		cpu at 0 {
> +			device_type = "cpu";

This is not really necessary, IIRC.

> +			compatible = "fsl,imx35", "arm,arm1136jfs";
> +			reg = <0>;
> +			d-cache-size = <0x4000>;	// L1, 16K
> +			i-cache-size = <0x4000>;	// L1, 16K

Are these two common bindings?  Documented in
Documentation/devicetree/bindings for somewhere?

> +			bus-frequency = <0>;		// from bootloader

Ditto.  I'm not even sure how this works.  Does your bootloader
really populates this property?  Which bus?

> +		};
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&avic>;
> +		ranges;
> +
> +		aips at 40000000 { /* AIPS1 */
> +			compatible = "fsl,aips", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x40000000 0x100000>;
> +			ranges;
> +
> +			i2c1: i2c at 43f80000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f80000 0x4000>;
> +				interrupts = <10>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c at 43f84000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f84000 0x4000>;
> +				interrupts = <3>;
> +				status = "disabled";
> +			};
> +
> +			uart1: uart at 43f90000 {

Name the node "serial".

> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x43f90000 0x4000>;
> +				interrupts = <45>;
> +				status = "disabled";
> +			};
> +
> +			uart2: uart at 43f94000 {
> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x43f94000 0x4000>;
> +				interrupts = <32>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c at 43f98000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f98000 0x4000>;
> +				interrupts = <4>;
> +				status = "disabled";
> +			};

We generally have a new line between nodes.

> +			iomuxc at 43fac000 {
> +				compatible = "fsl,imx35-iomuxc";
> +				reg = <0x43fac000 0x4000>;
> +
> +				i2c3 {
> +					pinctrl_i2c3_1: i2c3grp-1 {
> +						fsl,pins = <773 0x1c0 /* MX35_PAD_ATA_DATA12__I2C3_SCL */
> +							777 0x1c0>; /* MX35_PAD_ATA_DATA13__I2C3_SDA */
> +					};
> +				};
> +
> +				can1 {
> +					pinctrl_can1_1: can1grp-1 {
> +						fsl,pins = <223 0x1c0 /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
> +							228 0x1c0>; /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
> +					};
> +				};
> +				can2 {
> +					pinctrl_can2_1: can2grp-1 {
> +						fsl,pins = <291 0x1c0 /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
> +							298 0x1c0>; /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
> +					};
> +				};
> +
> +			};
> +		};
> +
> +		spba at 50000000 {
> +			compatible = "fsl,spba-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x50000000 0x100000>;
> +			ranges;
> +
> +			uart3: uart at 5000c000 {
> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x5000c000 0x4000>;
> +				interrupts = <18>;
> +				status = "disabled";
> +			};
> +
> +			fec: fec at 50038000 {
> +				compatible = "fsl,imx35-fec", "fsl,imx27-fec";
> +				reg = <0x50038000 0x4000>;
> +				interrupts = <57>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		aips at 53f00000 { /* AIPS2 */
> +			compatible = "fsl,aips", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x53f00000 0xffc0000>;
> +			ranges;
> +
> +			gpio3: gpio at 0x53fa4000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";

compatible = "fsl,imx35-gpio";

> +				reg = <0x53fa4000 0x4000>;
> +				interrupts = <56>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <1>;

It should be 2 now.

> +			};
> +
> +			esdhc1: esdhc at 53fb4000 {
> +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";

compatible = "fsl,imx35-esdhc";

> +				reg = <0x53fb4000 0x4000>;
> +				interrupts = <7>;
> +				status = "disabled";
> +			};
> +
> +			esdhc2: esdhc at 53fb8000 {
> +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
> +				reg = <0x53fb8000 0x4000>;
> +				interrupts = <8>;
> +				status = "disabled";
> +			};
> +
> +			esdhc3: esdhc at 53fbc000 {
> +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
> +				reg = <0x53fbc000 0x4000>;
> +				interrupts = <9>;
> +				status = "disabled";
> +			};
> +
> +			gpio1: gpio at 0x53fcc000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> +				reg = <0x53fcc000 0x4000>;
> +				interrupts = <52>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +
> +			gpio2: gpio at 0x53fd0000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> +				reg = <0x53fd0000 0x4000>;
> +				interrupts = <51>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +
> +			wdog at 53fdc000 {
> +				compatible = "fsl,imx35-wdt", "fsl,imx2-wdt";
> +				reg = <0x53fdc000 0x4000>;
> +				interrupts = <55>;
> +				status = "disabled";

Drop status to have wdog such completely SoC internal stuff enabled by
default.

> +			};
> +
> +			can at 53fe4000 {
> +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> +				reg = <0x53fe4000 0x1000>;
> +				interrupts = <43>;
> +				status = "disabled";
> +			};
> +			can at 53fe8000 {
> +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> +				reg = <0x53fe8000 0x1000>;
> +				interrupts = <44>;
> +				status = "disabled";
> +			};
> +		};
> +		nand at bb000000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			compatible = "fsl,imx35-nand", "fsl,imx25-nand";
> +			reg = <0xbb000000 0x2000>;
> +			interrupts = <33>;
> +			status = "disabled";
> +		};

Why nand device isn't under any bus but soc directly?

> +	};
> +};
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index b1d3675..9389ab6 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -26,6 +26,7 @@ CONFIG_MACH_ARMADILLO5X0=y
>  CONFIG_MACH_KZM_ARM11_01=y
>  CONFIG_MACH_PCM043=y
>  CONFIG_MACH_MX35_3DS=y
> +CONFIG_MACH_IMX35_DT=y
>  CONFIG_MACH_VPR200=y
>  CONFIG_MACH_IMX51_DT=y
>  CONFIG_MACH_MX51_3DS=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index eff4db5..95f9d6a 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -644,6 +644,19 @@ config MACH_VPR200
>  	  Include support for VPR200 platform. This includes specific
>  	  configurations for the board and its peripherals.
>  
> +config MACH_IMX35_DT
> +	bool "Support i.MX35 platforms from device tree"
> +	select SOC_IMX35
> +	select USE_OF

USE_OF is selected by ARCH_MXC now.

> +	select HAVE_CAN_FLEXCAN if CAN

Move it to "config SOC_IMX35".

> +	select IMX_HAVE_PLATFORM_MXC_NAND
> +	select IMX_HAVE_PLATFORM_SPI_IMX
> +	select IMX_HAVE_PLATFORM_IMX2_WDT

These are unreasonable.

> +	select PINCTRL

Need to select PINCTRL_IMX35 also?

And they should be under "config SOC_IMX35".

> +	help
> +	  Include support for Freescale i.MX35 based platforms
> +	  using the device tree for discovery
> +
>  comment "i.MX5 platforms:"
>  
>  config MACH_MX50_RDP
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index ff29421..97d01b5 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -64,6 +64,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
>  obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
>  obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
>  obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
> +obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
>  
>  obj-$(CONFIG_DEBUG_LL) += lluart.o
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
> new file mode 100644
> index 0000000..8b9cc84
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx35-dt.c
> @@ -0,0 +1,119 @@
> +/*
> + * Copyright 2012 Steffen Trumtrar, Pengutronix
> + *
> + * based on imx27-dt.c
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/pinctrl/machine.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +#include <mach/mx35.h>
> +
> +static const struct of_dev_auxdata imx35_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART1_BASE_ADDR, "imx21-uart.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART2_BASE_ADDR, "imx21-uart.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART3_BASE_ADDR, "imx21-uart.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-fec", MX35_FEC_BASE_ADDR, "imx27-fec.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-wdt", MX35_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx35.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx35.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx35.2", NULL),
> +	OF_DEV_AUXDATA("fsl,imx35-nand", MX35_NFC_BASE_ADDR, "mxc_nand.0", NULL),
> +	{ /* sentinel */ }
> +};

If these auxdata are here only for clk lookup, we can save them by
having DT specific clkdev lookup in clock driver.

> +
> +static int __init imx35_avic_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
> +	return 0;
> +}
> +
> +static int __init imx35_gpio_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
> +
> +	gpio_irq_base -= 32;
> +	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
> +				NULL);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id imx35_irq_match[] __initconst = {
> +	{ .compatible = "fsl,imx35-avic", .data = imx35_avic_add_irq_domain, },
> +	{ .compatible = "fsl,imx35-gpio", .data = imx35_gpio_add_irq_domain, },
> +	{ /* sentinel */ }
> +};

All these are not needed now.

> +
> +static const struct of_device_id imx35_of_mixed_devices_match[] __initconst = {
> +	{ /* END OF LIST */ }
> +};
> +
> +static void __init of_mixed_device_hook(void)
> +{
> +	struct device_node *np;
> +	const struct of_device_id *of_id;
> +
> +	np = of_find_matching_node(NULL, imx35_of_mixed_devices_match);
> +	if (np) {
> +		void (*func)(void);
> +
> +		of_id = of_match_node(imx35_of_mixed_devices_match, np);
> +		func = of_id->data;
> +		func();
> +	}
> +}

We have this on other imx DT machines for hooking the IOMUX setup done
in non-DT board files.  Since you have imx35 pinctrl support in place.
What is above hook for then?

> +
> +static void __init imx35_dt_init(void)
> +{
> +	of_irq_init(imx35_irq_match);
> +
> +	/* Some mx35 have problems when the cache is not initialized
> +	 * FIXME: ultimatly this belongs in the oftree definition
> +	 */
> +	imx3_init_l2x0();
> +	pinctrl_provide_dummies();
> +
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +			     imx35_auxdata_lookup, NULL);
> +
> +	of_mixed_device_hook();
> +}
> +
> +static void __init imx35_timer_init(void)
> +{
> +	mx35_clocks_init();
> +}
> +
> +static struct sys_timer imx35_timer = {
> +	.init = imx35_timer_init,
> +};
> +
> +static const char *imx35_dt_board_compat[] __initdata = {
> +	"fsl,imx35",
> +	NULL
> +};
> +
> +DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
> +	.map_io		= mx35_map_io,
> +	.init_early	= imx35_init_early,
> +	.init_irq	= mx35_init_irq,
> +	.handle_irq	= imx35_handle_irq,
> +	.timer		= &imx35_timer,
> +	.init_machine	= imx35_dt_init,
> +	.dt_compat	= imx35_dt_board_compat,
> +	.restart	= mxc_restart,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> index e429ca1..643b0aa 100644
> --- a/arch/arm/plat-mxc/include/mach/common.h
> +++ b/arch/arm/plat-mxc/include/mach/common.h
> @@ -50,6 +50,7 @@ extern void imx25_soc_init(void);
>  extern void imx27_soc_init(void);
>  extern void imx31_soc_init(void);
>  extern void imx35_soc_init(void);
> +extern void imx3_init_l2x0(void);
>  extern void imx50_soc_init(void);
>  extern void imx51_soc_init(void);
>  extern void imx53_soc_init(void);
> @@ -67,6 +68,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
>  extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
>  			unsigned long ckih1, unsigned long ckih2);
>  extern int mx27_clocks_init_dt(void);
> +extern int mx35_clocks_init_dt(void);

It does not necessarily belong this driver.

Regards,
Shawn

>  extern int mx51_clocks_init_dt(void);
>  extern int mx53_clocks_init_dt(void);
>  extern int mx6q_clocks_init(void);
> -- 
> 1.7.10.4
> 



From balbi at ti.com  Fri Aug  3 09:20:48 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:20:48 +0300
Subject: [PATCH v2 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <1342593039-7728-2-git-send-email-kishon@ti.com>
References: <1342593039-7728-1-git-send-email-kishon@ti.com>
 <1342593039-7728-2-git-send-email-kishon@ti.com>
Message-ID: <20120803132046.GA8269@arwen.pp.htv.fi>

Hi,

On Wed, Jul 18, 2012 at 12:00:38PM +0530, Kishon Vijay Abraham I wrote:
> Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
> creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
> USB2PHY is connected to ocp2scp.
> 
> This also includes device tree support for ocp2scp driver and
> the documentation with device tree binding information is updated.
> 
> Cc: Felipe Balbi <balbi at ti.com>

If you fix (or change my mind) on the comment below, you can add:

Acked-by: Felipe Balbi <balbi at ti.com>


Also, I wonder who should be the one to take this. Who will be queueing
patches on this directory to mainline ?

> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
>  .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 ++
>  drivers/Kconfig                                    |    2 +
>  drivers/Makefile                                   |    2 +
>  drivers/bus/Kconfig                                |   15 +++
>  drivers/bus/Makefile                               |    5 +
>  drivers/bus/omap-ocp2scp.c                         |   98 ++++++++++++++++++++
>  6 files changed, 132 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
>  create mode 100644 drivers/bus/Kconfig
>  create mode 100644 drivers/bus/Makefile
>  create mode 100644 drivers/bus/omap-ocp2scp.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
> new file mode 100644
> index 0000000..d2fe064
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
> @@ -0,0 +1,10 @@
> +* OMAP OCP2SCP - ocp interface to scp interface
> +
> +properties:
> +- compatible : Should be "ti,omap-ocp2scp"
> +- #address-cells, #size-cells : Must be present if the device has sub-nodes
> +- ranges : the child address space are mapped 1:1 onto the parent address space
> +- ti,hwmods : must be "ocp2scp_usb_phy"
> +
> +Sub-nodes:
> +All the devices connected to ocp2scp are described using sub-node to ocp2scp
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index bfc9186..4fe1e4c 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -2,6 +2,8 @@ menu "Device Drivers"
>  
>  source "drivers/base/Kconfig"
>  
> +source "drivers/bus/Kconfig"
> +
>  source "drivers/connector/Kconfig"
>  
>  source "drivers/mtd/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 2ba29ff..cac3819 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -5,6 +5,8 @@
>  # Rewritten to use lists instead of if-statements.
>  #
>  
> +obj-y				+= bus/
> +
>  # GPIO must come after pinctrl as gpios may need to mux pins etc
>  obj-y				+= pinctrl/
>  obj-y				+= gpio/
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> new file mode 100644
> index 0000000..6270415
> --- /dev/null
> +++ b/drivers/bus/Kconfig
> @@ -0,0 +1,15 @@
> +#
> +# Bus Devices
> +#
> +
> +menu "Bus devices"
> +
> +config OMAP_OCP2SCP
> +	tristate "OMAP OCP2SCP DRIVER"
> +	help
> +	  Driver to enable ocp2scp module which transforms ocp interface
> +	  protocol to scp protocol. In OMAP4, USB PHY is connected via
> +	  OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
> +	  OCP2SCP.
> +
> +endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> new file mode 100644
> index 0000000..0ec50bc
> --- /dev/null
> +++ b/drivers/bus/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for the bus drivers.
> +#
> +
> +obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
> diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
> new file mode 100644
> index 0000000..8c3db3a
> --- /dev/null
> +++ b/drivers/bus/omap-ocp2scp.c
> @@ -0,0 +1,98 @@
> +/*
> + * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Author: Kishon Vijay Abraham I <kishon at ti.com>
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +static int ocp2scp_remove_devices(struct device *dev, void *c)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +
> +	platform_device_unregister(pdev);
> +
> +	return 0;
> +}
> +
> +static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
> +{
> +	int			ret;
> +	struct device_node	*np = pdev->dev.of_node;
> +
> +	if (np) {
> +		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
> +		if (ret) {
> +			dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
> +			goto err0;
> +		}
> +	}
> +	pm_runtime_enable(&pdev->dev);
> +
> +	return 0;
> +
> +err0:
> +	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
> +
> +	return ret;
> +}
> +
> +static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
> +{
> +	pm_runtime_disable(&pdev->dev);
> +	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id omap_ocp2scp_id_table[] = {
> +	{ .compatible = "ti,omap-ocp2scp" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
> +#endif
> +
> +static struct platform_driver omap_ocp2scp_driver = {
> +	.probe		= omap_ocp2scp_probe,
> +	.remove		= __devexit_p(omap_ocp2scp_remove),
> +	.driver		= {
> +		.name	= "omap-ocp2scp",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),
> +	},
> +};
> +
> +static int __init omap_ocp2scp_init(void)
> +{
> +	return platform_driver_register(&omap_ocp2scp_driver);
> +}
> +arch_initcall(omap_ocp2scp_init);

I really think we should avoid this trickery and make dependent drivers
return -EPROBE_DEFER case this isn't ready yet.

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:21:39 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:21:39 +0300
Subject: [PATCH v2 2/2] arm/dts: omap4: Add ocp2scp data
In-Reply-To: <1342593039-7728-3-git-send-email-kishon@ti.com>
References: <1342593039-7728-1-git-send-email-kishon@ti.com>
 <1342593039-7728-3-git-send-email-kishon@ti.com>
Message-ID: <20120803132137.GB8269@arwen.pp.htv.fi>

On Wed, Jul 18, 2012 at 12:00:39PM +0530, Kishon Vijay Abraham I wrote:
> Add ocp2scp data node in omap4 device tree file.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/omap4.dtsi |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 359c497..29c6243 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -272,5 +272,13 @@
>  			ti,hwmods = "mmc5";
>  			ti,needs-special-reset;
>  		};
> +
> +		ocp2scp {
> +			compatible = "ti,omap-ocp2scp";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			ti,hwmods = "ocp2scp_usb_phy";
> +		};
>  	};
>  };
> -- 
> 1.7.5.4
> 

-- 
balbi
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From gregory.clement at free-electrons.com  Fri Aug  3 09:26:31 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 03 Aug 2012 15:26:31 +0200
Subject: [PATCH 1/4] arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
 config option
In-Reply-To: <1343999430-31816-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <501BD187.70901@free-electrons.com>

On 08/03/2012 03:10 PM, Thomas Petazzoni wrote:
> Until now, the PLAT_ORION configuration option was common to all the
> Marvell EBU SoCs, and selecting this option had the effect of enabling
> the MPP code, GPIO code, address decoding and PCIe code from
> plat-orion, as well as providing access to driver-specific header
> files from plat-orion/include.
> 
> However, the Armada 370 and XP SoCs will not use the MPP and GPIO code
> (instead some proper pinctrl and gpio drivers are in preparation), and
> generally, we want to move away from plat-orion and instead have
> everything in mach-mvebu.
> 
> That said, in the mean time, we want to leverage the driver-specific
> headers as well as the address decoding code, so we introduce
> PLAT_ORION_LEGACY. The older Marvell SoCs need to select
> PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select
> PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it
> automatically selects PLAT_ORION.
> 
> Then, with just PLAT_ORION, you have the address decoding code plus
> the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you
> gain the old MPP, GPIO and PCIe code.
> 
> Again, this is only a temporary solution until we make all Marvell EBU
> platforms converge into the mach-mvebu directory. This solution avoids
> duplicating the existing address decoding code into mach-mvebu.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

[...]

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Fri Aug  3 09:27:50 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 03 Aug 2012 15:27:50 +0200
Subject: [PATCH 2/4] arm: plat-orion: make bridge_virt_base non-const
 to support DT use case
In-Reply-To: <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <501BD1D6.3050908@free-electrons.com>

On 08/03/2012 03:10 PM, Thomas Petazzoni wrote:
> For the Armada 370 and XP SoCs where the DT is used, we need to fill
> at runtime the bridge_virt_base field on the
> orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this
> field.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

[...]


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Fri Aug  3 09:28:10 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 03 Aug 2012 15:28:10 +0200
Subject: [PATCH 3/4] arm: mvebu: add basic address decoding support to
 Armada 370/XP
In-Reply-To: <1343999430-31816-4-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-4-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <501BD1EA.4060300@free-electrons.com>

On 08/03/2012 03:10 PM, Thomas Petazzoni wrote:
> his commit adds basic support for address decoding configuration for
> the Armada 370 and Armada XP SoCs, re-using the infrastructure
> provided in plat-orion.
> 
> For now, only a BootROM window is configured on Armada XP, which is
> needed to get the non-boot CPUs started and is therefore a requirement
> for SMP support.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

[...]


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Fri Aug  3 09:29:10 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 03 Aug 2012 15:29:10 +0200
Subject: [PATCH 4/4] arm: mvebu: add address decoding controller to the DT
In-Reply-To: <1343999430-31816-5-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-5-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <501BD226.3020708@free-electrons.com>

On 08/03/2012 03:10 PM, Thomas Petazzoni wrote:
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>

> ---
>  arch/arm/boot/dts/armada-370-xp.dtsi |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
> index 6b6b932..16cc82c 100644
> --- a/arch/arm/boot/dts/armada-370-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
> @@ -63,6 +63,11 @@
>  			       reg = <0xd0020300 0x30>;
>  			       interrupts = <37>, <38>, <39>, <40>;
>  		};
> +
> +		addr-decoding at d0020000 {
> +			compatible = "marvell,armada-addr-decoding-controller";
> +			reg = <0xd0020000 0x258>;
> +		};
>  	};
>  };
>  
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From balbi at ti.com  Fri Aug  3 09:27:09 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:27:09 +0300
Subject: [PATCH v6 01/11] drivers: usb: otg: add a new driver for omap
 usb2 phy
In-Reply-To: <1343639400-28725-2-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-2-git-send-email-kishon@ti.com>
Message-ID: <20120803132708.GC8269@arwen.pp.htv.fi>

On Mon, Jul 30, 2012 at 02:39:50PM +0530, Kishon Vijay Abraham I wrote:
> All phy related programming like enabling/disabling the clocks, powering
> on/off the phy is taken care of by this driver. It is also used for OTG
> related functionality like srp.
> 
> This also includes device tree support for usb2 phy driver and
> the documentation with device tree binding information is updated.
> 
> Currently writing to control module register is taken care in this
> driver which will be removed once the control module driver is in place.
> 
> Cc: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
>  .../devicetree/bindings/bus/omap-ocp2scp.txt       |    3 +
>  Documentation/devicetree/bindings/usb/omap-usb.txt |   17 ++
>  drivers/usb/otg/Kconfig                            |   10 +
>  drivers/usb/otg/Makefile                           |    1 +
>  drivers/usb/otg/omap-usb2.c                        |  280 ++++++++++++++++++++

let's move this to drivers/usb/phy/. I'll prepare a patch moving all phy
drivers to that directory after the OTG state machine is ready ;-)

> diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
> new file mode 100644
> index 0000000..52f503b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
> @@ -0,0 +1,17 @@
> +OMAP USB PHY
> +
> +OMAP USB2 PHY
> +
> +Required properties:
> + - compatible: Should be "ti,omap-usb2"
> + - reg : Address and length of the register set for the device. Also
> +add the address of control module dev conf register until a driver for
> +control module is added
> +
> +This is usually a subnode of ocp2scp to which it is connected.
> +
> +usb2phy at 4a0ad080 {
> +	compatible = "ti,omap-usb2";
> +	reg = <0x4a0ad080 0x58>,
> +		<0x4a002300 0x1>;
> +};
> diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
> index 5c87db0..c751db7 100644
> --- a/drivers/usb/otg/Kconfig
> +++ b/drivers/usb/otg/Kconfig
> @@ -78,6 +78,16 @@ config TWL6030_USB
>  	  are hooked to this driver through platform_data structure.
>  	  The definition of internal PHY APIs are in the mach-omap2 layer.
>  
> +config OMAP_USB2
> +	tristate "OMAP USB2 PHY Driver"
> +	depends on OMAP_OCP2SCP
> +	select USB_OTG_UTILS
> +	help
> +	  Enable this to support the transceiver that is part of SOC. This
> +	  driver takes care of all the PHY functionality apart from comparator.
> +	  The USB OTG controller communicates with the comparator using this
> +	  driver.
> +
>  config NOP_USB_XCEIV
>  	tristate "NOP USB Transceiver Driver"
>  	select USB_OTG_UTILS
> diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
> index 41aa509..2c2a3ca 100644
> --- a/drivers/usb/otg/Makefile
> +++ b/drivers/usb/otg/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_USB_GPIO_VBUS)	+= gpio_vbus.o
>  obj-$(CONFIG_ISP1301_OMAP)	+= isp1301_omap.o
>  obj-$(CONFIG_TWL4030_USB)	+= twl4030-usb.o
>  obj-$(CONFIG_TWL6030_USB)	+= twl6030-usb.o
> +obj-$(CONFIG_OMAP_USB2)		+= omap-usb2.o
>  obj-$(CONFIG_NOP_USB_XCEIV)	+= nop-usb-xceiv.o
>  obj-$(CONFIG_USB_ULPI)		+= ulpi.o
>  obj-$(CONFIG_USB_ULPI_VIEWPORT)	+= ulpi_viewport.o
> diff --git a/drivers/usb/otg/omap-usb2.c b/drivers/usb/otg/omap-usb2.c
> new file mode 100644
> index 0000000..026cb3c
> --- /dev/null
> +++ b/drivers/usb/otg/omap-usb2.c
> @@ -0,0 +1,280 @@
> +/*
> + * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Author: Kishon Vijay Abraham I <kishon at ti.com>
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/io.h>
> +#include <linux/usb/omap_usb.h>
> +#include <linux/usb/phy_companion.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/delay.h>
> +
> +/**
> + * omap_usb2_set_comparator - links the comparator present in the sytem with
> + *	this phy
> + * @comparator - the companion phy(comparator) for this phy
> + *
> + * The phy companion driver should call this API passing the phy_companion
> + * filled with set_vbus and start_srp to be used by usb phy.
> + *
> + * For use by phy companion driver
> + */
> +void omap_usb2_set_comparator(struct phy_companion *comparator)
> +{
> +	struct omap_usb	*phy;
> +	struct usb_phy	*x = usb_get_phy(USB_PHY_TYPE_USB2);
> +
> +	if (x) {
> +		phy = phy_to_omapusb(x);
> +		phy->comparator = comparator;
> +	}
> +}
> +EXPORT_SYMBOL_GPL(omap_usb2_set_comparator);
> +
> +/**
> + * omap_usb_phy_power - power on/off the phy using control module reg
> + * @phy: struct omap_usb *
> + * @on: 0 or 1, based on powering on or off the PHY
> + *
> + * XXX: Remove this function once control module driver gets merged
> + */
> +static void omap_usb_phy_power(struct omap_usb *phy, int on)
> +{
> +	u32 val;
> +
> +	if (on) {
> +		val = readl(phy->control_dev);
> +		if (val & PHY_PD) {
> +			writel(~PHY_PD, phy->control_dev);
> +			/* XXX: add proper documentation for this delay */
> +			mdelay(200);
> +		}
> +	} else {
> +		writel(PHY_PD, phy->control_dev);
> +	}
> +}
> +
> +static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
> +{
> +	struct omap_usb *phy = phy_to_omapusb(otg->phy);
> +
> +	if (!phy->comparator)
> +		return -ENODEV;
> +
> +	return phy->comparator->set_vbus(phy->comparator, enabled);
> +}
> +
> +static int omap_usb_start_srp(struct usb_otg *otg)
> +{
> +	struct omap_usb *phy = phy_to_omapusb(otg->phy);
> +
> +	if (!phy->comparator)
> +		return -ENODEV;
> +
> +	return phy->comparator->start_srp(phy->comparator);
> +}
> +
> +static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
> +{
> +	struct usb_phy	*phy = otg->phy;
> +
> +	otg->host = host;
> +	if (!host)
> +		phy->state = OTG_STATE_UNDEFINED;
> +
> +	return 0;
> +}
> +
> +static int omap_usb_set_peripheral(struct usb_otg *otg,
> +		struct usb_gadget *gadget)
> +{
> +	struct usb_phy	*phy = otg->phy;
> +
> +	otg->gadget = gadget;
> +	if (!gadget)
> +		phy->state = OTG_STATE_UNDEFINED;
> +
> +	return 0;
> +}
> +
> +static int omap_usb2_suspend(struct usb_phy *x, int suspend)
> +{
> +	u32 ret;
> +	struct omap_usb *phy = phy_to_omapusb(x);
> +
> +	if (suspend && !phy->is_suspended) {
> +		omap_usb_phy_power(phy, 0);
> +		pm_runtime_put_sync(phy->dev);
> +		phy->is_suspended = 1;
> +	} else if (!suspend && phy->is_suspended) {
> +		ret = pm_runtime_get_sync(phy->dev);
> +		if (ret < 0) {
> +			dev_err(phy->dev, "get_sync failed with err %d\n",
> +									ret);
> +			return ret;
> +		}
> +		omap_usb_phy_power(phy, 1);
> +		phy->is_suspended = 0;
> +	}
> +
> +	return 0;
> +}
> +
> +static int __devinit omap_usb2_probe(struct platform_device *pdev)
> +{
> +	struct omap_usb			*phy;
> +	struct usb_otg			*otg;
> +	struct resource			*res;
> +
> +	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy) {
> +		dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
> +		return -ENOMEM;
> +	}
> +
> +	otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
> +	if (!otg) {
> +		dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
> +		return -ENOMEM;
> +	}
> +
> +	phy->dev		= &pdev->dev;
> +
> +	phy->phy.dev		= phy->dev;
> +	phy->phy.label		= "omap-usb2";
> +	phy->phy.set_suspend	= omap_usb2_suspend;
> +	phy->phy.otg		= otg;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +
> +	phy->control_dev = devm_request_and_ioremap(&pdev->dev, res);
> +	if (phy->control_dev == NULL) {
> +		dev_err(&pdev->dev, "Failed to obtain io memory\n");
> +		return -ENXIO;
> +	}
> +
> +	phy->is_suspended	= 1;
> +	omap_usb_phy_power(phy, 0);
> +
> +	otg->set_host		= omap_usb_set_host;
> +	otg->set_peripheral	= omap_usb_set_peripheral;
> +	otg->set_vbus		= omap_usb_set_vbus;
> +	otg->start_srp		= omap_usb_start_srp;
> +	otg->phy		= &phy->phy;
> +
> +	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
> +	if (IS_ERR(phy->wkupclk)) {
> +		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
> +		return PTR_ERR(phy->wkupclk);
> +	}
> +	clk_prepare(phy->wkupclk);
> +
> +	usb_add_phy(&phy->phy, USB_PHY_TYPE_USB2);
> +
> +	platform_set_drvdata(pdev, phy);
> +
> +	pm_runtime_enable(phy->dev);
> +
> +	return 0;
> +}
> +
> +static int __devexit omap_usb2_remove(struct platform_device *pdev)
> +{
> +	struct omap_usb	*phy = platform_get_drvdata(pdev);
> +
> +	clk_unprepare(phy->wkupclk);
> +	usb_remove_phy(&phy->phy);
> +	platform_set_drvdata(pdev, NULL);

this platform_set_drvdata() is unnecessary as the pdev object will be
destroyed.

> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM_RUNTIME
> +
> +static int omap_usb2_runtime_suspend(struct device *dev)
> +{
> +	struct platform_device	*pdev = to_platform_device(dev);
> +	struct omap_usb	*phy = platform_get_drvdata(pdev);
> +
> +	clk_disable(phy->wkupclk);

weird. I would expect the wakeup clock to be enabled on suspend and
disabled on resume. Isn't this causing any unbalanced disable warnings ?

> +
> +	return 0;
> +}
> +
> +static int omap_usb2_runtime_resume(struct device *dev)
> +{
> +	u32 ret = 0;
> +	struct platform_device	*pdev = to_platform_device(dev);
> +	struct omap_usb	*phy = platform_get_drvdata(pdev);
> +
> +	ret = clk_enable(phy->wkupclk);
> +	if (ret < 0)
> +		dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
> +
> +	return ret;
> +}
> +
> +static const struct dev_pm_ops omap_usb2_pm_ops = {
> +	SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
> +		NULL)

only runtime ? What about static suspend ? We need this to work also
after a traditional echo mem > /sys/power/state ;-)

> +#ifdef CONFIG_OF
> +static const struct of_device_id omap_usb2_id_table[] = {
> +	{ .compatible = "ti,omap-usb2" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
> +#endif
> +
> +static struct platform_driver omap_usb2_driver = {
> +	.probe		= omap_usb2_probe,
> +	.remove		= __devexit_p(omap_usb2_remove),
> +	.driver		= {
> +		.name	= "omap-usb2",
> +		.owner	= THIS_MODULE,
> +		.pm	= DEV_PM_OPS,
> +		.of_match_table = of_match_ptr(omap_usb2_id_table),
> +	},
> +};
> +
> +static int __init usb2_omap_init(void)
> +{
> +	return platform_driver_register(&omap_usb2_driver);
> +}
> +arch_initcall(usb2_omap_init);

I'd really like to see this converted into a module_platform_driver().
If you have dependencies, just make sure to return -EPROBE_DEFER so your
probe gets retried.

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:27:39 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:27:39 +0300
Subject: [PATCH v6 02/11] arm/dts: omap: Add omap-usb2 dt data
In-Reply-To: <1343639400-28725-3-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-3-git-send-email-kishon@ti.com>
Message-ID: <20120803132737.GD8269@arwen.pp.htv.fi>

On Mon, Jul 30, 2012 at 02:39:51PM +0530, Kishon Vijay Abraham I wrote:
> Add omap-usb2 data node in omap4 device tree file.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

looks good:

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/omap4.dtsi |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 29c6243..15f1890 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -279,6 +279,11 @@
>  			#size-cells = <1>;
>  			ranges;
>  			ti,hwmods = "ocp2scp_usb_phy";
> +			usb2phy at 4a0ad080 {
> +				compatible = "ti,omap-usb2";
> +				reg = <0x4a0ad080 0x58>,
> +				      <0x4a002300 0x1>;
> +			};
>  		};
>  	};
>  };
> -- 
> 1.7.9.5
> 

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:28:53 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:28:53 +0300
Subject: [PATCH v6 03/11] drivers: usb: otg: make twl6030_usb as a
 comparator driver to omap_usb2
In-Reply-To: <1343639400-28725-4-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-4-git-send-email-kishon@ti.com>
Message-ID: <20120803132852.GE8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:52PM +0530, Kishon Vijay Abraham I wrote:
> All the PHY configuration other than VBUS, ID GND and OTG SRP are removed
> from twl6030. The phy configurations are taken care by the dedicated
> usb2 phy driver. So twl6030 is made as comparator driver for VBUS and
> ID detection.
> 
> Writing to control module which is now handled in omap2430.c should be
> removed once a driver for control module is in place.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

This looks good for the time being. Do you think it has any hard
dependencies on your new phy drivers, or can I apply this without those
other patches ??

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:29:46 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:29:46 +0300
Subject: [PATCH v6 04/11] arm: omap: hwmod: add a new addr space in otg
 for writing to control module
In-Reply-To: <1343639400-28725-5-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-5-git-send-email-kishon@ti.com>
Message-ID: <20120803132945.GF8269@arwen.pp.htv.fi>

On Mon, Jul 30, 2012 at 02:39:53PM +0530, Kishon Vijay Abraham I wrote:
> The mailbox register for usb otg in omap is present in control module.
> On detection of any events VBUS or ID, this register should be written
> to send the notification to musb core.
> 
> Till we have a separate control module driver to write to control module,
> omap2430 will handle the register writes to control module by itself. So
> a new address space to represent this control module register is added
> to usb_otg_hs.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

this should come before previous patch, right ? Otherwise we will try to
ioremap a resource which isn't passed down to driver. No ?

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:31:23 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:31:23 +0300
Subject: [PATCH v6 05/11] drivers: usb: twl6030: Add dt support for
 twl6030 usb
In-Reply-To: <1343639400-28725-6-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-6-git-send-email-kishon@ti.com>
Message-ID: <20120803133122.GG8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:54PM +0530, Kishon Vijay Abraham I wrote:
> Add device tree support for twl6030 usb driver.
> Update the Documentation with device tree binding information.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

This looks great too. I can take this without any dependencies on the
rest of the series, I believe. Right ??

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:31:43 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:31:43 +0300
Subject: [PATCH v6 06/11] arm/dts: Add twl6030-usb data
In-Reply-To: <1343639400-28725-7-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-7-git-send-email-kishon@ti.com>
Message-ID: <20120803133142.GH8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:55PM +0530, Kishon Vijay Abraham I wrote:
> Add twl6030-usb data node in twl6030 device tree file
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/omap4-panda.dts |    4 ++++
>  arch/arm/boot/dts/omap4-sdp.dts   |    4 ++++
>  arch/arm/boot/dts/twl6030.dtsi    |    5 +++++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
> index 1efe0c5..7052422 100644
> --- a/arch/arm/boot/dts/omap4-panda.dts
> +++ b/arch/arm/boot/dts/omap4-panda.dts
> @@ -89,3 +89,7 @@
>  	ti,non-removable;
>  	bus-width = <4>;
>  };
> +
> +&twlusb {
> +	usb-supply = <&vusb>;
> +};
> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> index d08c4d1..6326d7c 100644
> --- a/arch/arm/boot/dts/omap4-sdp.dts
> +++ b/arch/arm/boot/dts/omap4-sdp.dts
> @@ -158,3 +158,7 @@
>  	bus-width = <4>;
>  	ti,non-removable;
>  };
> +
> +&twlusb {
> +	usb-supply = <&vusb>;
> +};
> diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
> index 3b2f351..8e3aac9 100644
> --- a/arch/arm/boot/dts/twl6030.dtsi
> +++ b/arch/arm/boot/dts/twl6030.dtsi
> @@ -83,4 +83,9 @@
>  	clk32kg: regulator at 12 {
>  		compatible = "ti,twl6030-clk32kg";
>  	};
> +
> +	twlusb: twl6030-usb {
> +		compatible = "ti,twl6030-usb";
> +		interrupts = < 4 10 >;
> +	};
>  };
> -- 
> 1.7.9.5
> 

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:32:15 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:32:15 +0300
Subject: [PATCH v6 07/11] drivers: usb: twl4030: Add device tree support
 for twl4030 usb
In-Reply-To: <1343639400-28725-8-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-8-git-send-email-kishon@ti.com>
Message-ID: <20120803133214.GI8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:56PM +0530, Kishon Vijay Abraham I wrote:
> Add device tree support for twl4030 usb driver.
> Update the Documentation with device tree binding information.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

I think this also doesn't have dependency on the rest of the series and
I could take this upstream. Right ?

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:32:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:32:54 +0300
Subject: [PATCH v6 08/11] arm/dts: Add twl4030-usb data
In-Reply-To: <1343639400-28725-9-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-9-git-send-email-kishon@ti.com>
Message-ID: <20120803133253.GJ8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:57PM +0530, Kishon Vijay Abraham I wrote:
> Add twl4030-usb data node in twl4030 device tree file.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/twl4030.dtsi |   21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
> index 22f4d13..761a5a5 100644
> --- a/arch/arm/boot/dts/twl4030.dtsi
> +++ b/arch/arm/boot/dts/twl4030.dtsi
> @@ -37,6 +37,18 @@
>  		regulator-max-microvolt = <3150000>;
>  	};
>  
> +	vusb1v5: regulator-vusb1v5 {
> +		compatible = "ti,twl4030-vusb1v5";
> +	};
> +
> +	vusb1v8: regulator-vusb1v8 {
> +		compatible = "ti,twl4030-vusb1v8";
> +	};
> +
> +	vusb3v1: regulator-vusb3v1 {
> +		compatible = "ti,twl4030-vusb3v1";
> +	};
> +
>  	twl_gpio: gpio {
>  		compatible = "ti,twl4030-gpio";
>  		gpio-controller;
> @@ -44,4 +56,13 @@
>  		interrupt-controller;
>  		#interrupt-cells = <1>;
>  	};
> +
> +	twl4030-usb {
> +		compatible = "ti,twl4030-usb";
> +		interrupts = < 10 4 >;
> +		usb1v5-supply = <&vusb1v5>;
> +		usb1v8-supply = <&vusb1v8>;
> +		usb3v1-supply = <&vusb3v1>;
> +		usb_mode = <1>;
> +	};
>  };
> -- 
> 1.7.9.5
> 

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:34:32 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:34:32 +0300
Subject: [PATCH v6 09/11] drivers: usb: musb: Add device tree support for
 omap musb glue
In-Reply-To: <1343639400-28725-10-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-10-git-send-email-kishon@ti.com>
Message-ID: <20120803133431.GK8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:58PM +0530, Kishon Vijay Abraham I wrote:
> Added device tree support for omap musb driver and updated the
> Documentation with device tree binding information.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

This looks good and I think I can take this without any dependencies
again. Correct ?

-- 
balbi
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From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:38:15 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 3 Aug 2012 15:38:15 +0200
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <1343076052-27312-7-git-send-email-marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
Message-ID: <20120803153815.758dc064@skate>

Marek,

Le Mon, 23 Jul 2012 22:40:48 +0200,
Marek Vasut <marex at denx.de> a ?crit :

> +static uint32_t mxs_spi_cs_to_reg(unsigned cs)
> +{
> +	uint32_t select = 0;
> +
> +	if (cs & 1)
> +		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
> +	if (cs & 2)
> +		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
> +
> +	return select;
> +}

It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ
bits to adjust the chip select, and when reading the driver, it seemed
suspicious to me. After going through the datasheet, indeed those bits
are the appropriate one to select between the SS0, SS1 and SS2 chip
selects, but I find the code not really obvious. Would it be possible
to make it more obvious either by adding or comment or doing something
like:

/* Should be put in some header file */
#define BM_SSP_CTRL0_SPI_CS_BITS (20)

+static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
+{
+	struct mxs_ssp *ssp = &spi->ssp;
+
+	writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS,
+              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+	writel(cs,
+              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+}

Regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From balbi at ti.com  Fri Aug  3 09:35:16 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:35:16 +0300
Subject: [PATCH v6 10/11] arm/dts: omap: Add usb_otg and glue data
In-Reply-To: <1343639400-28725-11-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-11-git-send-email-kishon@ti.com>
Message-ID: <20120803133514.GL8269@arwen.pp.htv.fi>

On Mon, Jul 30, 2012 at 02:39:59PM +0530, Kishon Vijay Abraham I wrote:
> Add usb otg data node in omap4/omap3 device tree file. Also update
> the node with board specific setting in omapx-<board>.dts file.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/omap3-beagle.dts |    6 ++++++
>  arch/arm/boot/dts/omap3-evm.dts    |    6 ++++++
>  arch/arm/boot/dts/omap3.dtsi       |    8 ++++++++
>  arch/arm/boot/dts/omap4-panda.dts  |    6 ++++++
>  arch/arm/boot/dts/omap4-sdp.dts    |    6 ++++++
>  arch/arm/boot/dts/omap4.dtsi       |    8 ++++++++
>  6 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
> index 5b4506c..f3d7076 100644
> --- a/arch/arm/boot/dts/omap3-beagle.dts
> +++ b/arch/arm/boot/dts/omap3-beagle.dts
> @@ -67,3 +67,9 @@
>  &mmc3 {
>  	status = "disable";
>  };
> +
> +&usb_otg_hs {
> +	interface_type = <0>;
> +	mode = <3>;
> +	power = <50>;
> +};
> diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
> index 2eee16e..8963b3d 100644
> --- a/arch/arm/boot/dts/omap3-evm.dts
> +++ b/arch/arm/boot/dts/omap3-evm.dts
> @@ -18,3 +18,9 @@
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
>  };
> +
> +&usb_otg_hs {
> +	interface_type = <0>;
> +	mode = <3>;
> +	power = <50>;
> +};
> diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
> index 99474fa..4b8c142 100644
> --- a/arch/arm/boot/dts/omap3.dtsi
> +++ b/arch/arm/boot/dts/omap3.dtsi
> @@ -215,5 +215,13 @@
>  			compatible = "ti,omap3-hsmmc";
>  			ti,hwmods = "mmc3";
>  		};
> +
> +		usb_otg_hs: usb_otg_hs {
> +			compatible = "ti,omap3-musb";
> +			ti,hwmods = "usb_otg_hs";
> +			multipoint = <1>;
> +			num_eps = <16>;
> +			ram_bits = <12>;
> +		};
>  	};
>  };
> diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
> index 7052422..dd19370 100644
> --- a/arch/arm/boot/dts/omap4-panda.dts
> +++ b/arch/arm/boot/dts/omap4-panda.dts
> @@ -93,3 +93,9 @@
>  &twlusb {
>  	usb-supply = <&vusb>;
>  };
> +
> +&usb_otg_hs {
> +	interface_type = <1>;
> +	mode = <3>;
> +	power = <50>;
> +};
> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> index 6326d7c..0fc10d4 100644
> --- a/arch/arm/boot/dts/omap4-sdp.dts
> +++ b/arch/arm/boot/dts/omap4-sdp.dts
> @@ -162,3 +162,9 @@
>  &twlusb {
>  	usb-supply = <&vusb>;
>  };
> +
> +&usb_otg_hs {
> +	interface_type = <1>;
> +	mode = <3>;
> +	power = <50>;
> +};
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 15f1890..7886518 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -285,5 +285,13 @@
>  				      <0x4a002300 0x1>;
>  			};
>  		};
> +
> +		usb_otg_hs: usb_otg_hs {
> +			compatible = "ti,omap4-musb";
> +			ti,hwmods = "usb_otg_hs";
> +			multipoint = <1>;
> +			num_eps = <16>;
> +			ram_bits = <12>;
> +		};
>  	};
>  };
> -- 
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
balbi
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From balbi at ti.com  Fri Aug  3 09:36:03 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 3 Aug 2012 16:36:03 +0300
Subject: [PATCH v6 11/11] arm: omap: phy: remove unused functions from
 omap-phy-internal.c
In-Reply-To: <1343639400-28725-12-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-12-git-send-email-kishon@ti.com>
Message-ID: <20120803133602.GM8269@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:40:00PM +0530, Kishon Vijay Abraham I wrote:
> All the unnessary functions in omap-phy-internal is removed.
> These functionality are now handled by omap-usb2 phy driver.
> 
> Cc: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> Acked-by: Tony Lindgren <tony at atomide.com>

Great stuff. I'll take this when we agree on the omap-usb2 phy driver.

-- 
balbi
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From arnd at arndb.de  Fri Aug  3 09:41:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 Aug 2012 13:41:32 +0000
Subject: [PATCH 2/4] arm: plat-orion: make bridge_virt_base non-const to
 support DT use case
In-Reply-To: <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <201208031341.32744.arnd@arndb.de>

On Friday 03 August 2012, Thomas Petazzoni wrote:
> diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
> index fd556f7..aafdd79 100644
> --- a/arch/arm/plat-orion/include/plat/addr-map.h
> +++ b/arch/arm/plat-orion/include/plat/addr-map.h
> @@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
>  struct orion_addr_map_cfg {
>         const int num_wins;     /* Total number of windows */
>         const int remappable_wins;
> -       const u32 bridge_virt_base;
> +       u32 bridge_virt_base;
>  
>         /* If NULL, the default cpu_win_can_remap will be used, using
>            the value in remappable_wins */

It would be nice to also change the type of this to void __iomem*, since you are
already touching the bridge_virt_base.

	Arnd


From festevam at gmail.com  Fri Aug  3 09:46:06 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 10:46:06 -0300
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <20120803153815.758dc064@skate>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1343076052-27312-7-git-send-email-marex@denx.de>
 <20120803153815.758dc064@skate>
Message-ID: <CAOMZO5AQs1NzJBogcLPcKtY=QSaxpDmzUTvpfScY7P10FEoMJw@mail.gmail.com>

On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:

>
> It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ
> bits to adjust the chip select, and when reading the driver, it seemed
> suspicious to me. After going through the datasheet, indeed those bits
> are the appropriate one to select between the SS0, SS1 and SS2 chip
> selects, but I find the code not really obvious. Would it be possible
> to make it more obvious either by adding or comment or doing something
> like:
>
> /* Should be put in some header file */
> #define BM_SSP_CTRL0_SPI_CS_BITS (20)
>
> +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
> +{
> +       struct mxs_ssp *ssp = &spi->ssp;
> +
> +       writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS,
> +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> +       writel(cs,
> +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
> +}

I agree with Thomas.

In U-boot I did the following in order to be able to select the
different chip selects:
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d351af33e59b64

Thanks,

Fabio Estevam


From thomas.petazzoni at free-electrons.com  Fri Aug  3 09:48:56 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 3 Aug 2012 15:48:56 +0200
Subject: [PATCH 2/4] arm: plat-orion: make bridge_virt_base non-const to
 support DT use case
In-Reply-To: <201208031341.32744.arnd@arndb.de>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1343999430-31816-3-git-send-email-thomas.petazzoni@free-electrons.com>
 <201208031341.32744.arnd@arndb.de>
Message-ID: <20120803154856.74a5368f@skate>

Le Fri, 3 Aug 2012 13:41:32 +0000,
Arnd Bergmann <arnd at arndb.de> a ?crit :

> > +       u32 bridge_virt_base;
> >  
> >         /* If NULL, the default cpu_win_can_remap will be used, using
> >            the value in remappable_wins */
> 
> It would be nice to also change the type of this to void __iomem*, since you are
> already touching the bridge_virt_base.

Yeah, I was also thinking about this cleanup. Will rework my patch
series to include a patch fixing this before doing the other changes.

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From marex at denx.de  Fri Aug  3 09:49:16 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 3 Aug 2012 15:49:16 +0200
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <CAOMZO5AQs1NzJBogcLPcKtY=QSaxpDmzUTvpfScY7P10FEoMJw@mail.gmail.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <20120803153815.758dc064@skate>
 <CAOMZO5AQs1NzJBogcLPcKtY=QSaxpDmzUTvpfScY7P10FEoMJw@mail.gmail.com>
Message-ID: <201208031549.16475.marex@denx.de>

Dear Fabio Estevam,

> On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni
> 
> <thomas.petazzoni at free-electrons.com> wrote:
> > It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ
> > bits to adjust the chip select, and when reading the driver, it seemed
> > suspicious to me. After going through the datasheet, indeed those bits
> > are the appropriate one to select between the SS0, SS1 and SS2 chip
> > selects, but I find the code not really obvious. Would it be possible
> > to make it more obvious either by adding or comment or doing something
> > like:
> > 
> > /* Should be put in some header file */
> > #define BM_SSP_CTRL0_SPI_CS_BITS (20)
> > 
> > +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
> > +{
> > +       struct mxs_ssp *ssp = &spi->ssp;
> > +
> > +       writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> > +       writel(cs,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
> > +}
> 
> I agree with Thomas.
> 
> In U-boot I did the following in order to be able to select the
> different chip selects:
> http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d
> 351af33e59b64

Good thing I waited with submission :)

I'll fix it in a bit and resubmit in the evening.

> Thanks,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From s.hauer at pengutronix.de  Fri Aug  3 09:59:56 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 15:59:56 +0200
Subject: [PATCH 1/2] ARM: mx27pdk: Add audio support
In-Reply-To: <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
References: <1341341098-9510-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5BXQ2OQVC6nXeo_yJB=SBC=sv=ez9k6uo3gLNkWnC0Gyg@mail.gmail.com>
 <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
Message-ID: <20120803135956.GT1451@pengutronix.de>

On Tue, Jul 31, 2012 at 09:49:13AM -0300, Fabio Estevam wrote:
> Sascha,
> 
> On 7/25/12, Fabio Estevam <festevam at gmail.com> wrote:
> > Hi Sascha,
> >
> > On Tue, Jul 3, 2012 at 3:44 PM, Fabio Estevam
> > <fabio.estevam at freescale.com> wrote:
> >> mx27pdk has a mc13783 audio codec.
> >>
> >> Add support for it.
> >>
> >> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> >
> > Is this patch OK? Can it be applied?
> 
> Could this get into 3.6?

Applied now. Sorry, missed this one.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From marex at denx.de  Fri Aug  3 10:00:43 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 3 Aug 2012 16:00:43 +0200
Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28
In-Reply-To: <CAOMZO5AQs1NzJBogcLPcKtY=QSaxpDmzUTvpfScY7P10FEoMJw@mail.gmail.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <20120803153815.758dc064@skate>
 <CAOMZO5AQs1NzJBogcLPcKtY=QSaxpDmzUTvpfScY7P10FEoMJw@mail.gmail.com>
Message-ID: <201208031600.43816.marex@denx.de>

Dear Fabio Estevam,

> On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni
> 
> <thomas.petazzoni at free-electrons.com> wrote:
> > It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ
> > bits to adjust the chip select, and when reading the driver, it seemed
> > suspicious to me. After going through the datasheet, indeed those bits
> > are the appropriate one to select between the SS0, SS1 and SS2 chip
> > selects, but I find the code not really obvious. Would it be possible
> > to make it more obvious either by adding or comment or doing something
> > like:
> > 
> > /* Should be put in some header file */
> > #define BM_SSP_CTRL0_SPI_CS_BITS (20)
> > 
> > +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
> > +{
> > +       struct mxs_ssp *ssp = &spi->ssp;
> > +
> > +       writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> > +       writel(cs,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
> > +}
> 
> I agree with Thomas.
> 
> In U-boot I did the following in order to be able to select the
> different chip selects:
> http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d
> 351af33e59b64

I'll just add the following comment if it's ok with you:

/*
 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
 *
 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
 * the datasheet for further details. In SPI mode, they are used to
 * toggle the chip-select lines (nCS pins).
 */

I hope it'll suffice. Recycling bits in registers is really crazy practice and 
I'd like to avoid these getting out of scope of this flaw's location.

> Thanks,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From s.hauer at pengutronix.de  Fri Aug  3 10:06:27 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 16:06:27 +0200
Subject: [PATCH v2] Visstrim SM10: Use mo_version to decide board video
 mode.
In-Reply-To: <1343995703-13578-1-git-send-email-javier.martin@vista-silicon.com>
References: <1343995703-13578-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120803140627.GU1451@pengutronix.de>

On Fri, Aug 03, 2012 at 02:08:23PM +0200, Javier Martin wrote:
> If the mother board version number is odd, emmaprp() for
> format conversion + UVC camera will be used.
> 
> Otherwise mx2_camera and m2m-deinterlacer will be registered.
> 
> For both cases Coda video codec is registered.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>

This does not apply. Mainline does not have visstrim_deinterlace_init.

Sascha

> ---
> Changes since v1:
>  - Add error message to emmaprp init function.
> 
> ---
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   54 ++++++++++++++++++++++++---
>  1 file changed, 49 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index 176533e..dbb344a 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -49,6 +49,10 @@
>  #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
>  #define SDHC1_IRQ IRQ_GPIOB(25)
>  
> +#define VERSION_MASK		0x7
> +#define MOTHERBOARD_SHIFT	4
> +#define EXPBOARD_SHIFT		0
> +
>  #define MOTHERBOARD_BIT2	(GPIO_PORTD + 31)
>  #define MOTHERBOARD_BIT1	(GPIO_PORTD + 30)
>  #define MOTHERBOARD_BIT0	(GPIO_PORTD + 29)
> @@ -205,7 +209,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
>  static phys_addr_t mx2_camera_base __initdata;
>  #define MX2_CAMERA_BUF_SIZE SZ_8M
>  
> -static void __init visstrim_camera_init(void)
> +static void __init visstrim_analog_camera_init(void)
>  {
>  	struct platform_device *pdev;
>  	int dma;
> @@ -442,6 +446,29 @@ static void __init visstrim_deinterlace_init(void)
>  		return;
>  }
>  
> +/* Emma-PrP for format conversion */
> +static void __init visstrim_emmaprp_init(void)
> +{
> +	struct platform_device *pdev;
> +	int dma;
> +
> +	pdev = imx27_add_mx2_emmaprp();
> +	if (IS_ERR(pdev))
> +		return;
> +
> +	/*
> +	 * Use the same memory area as the analog camera since both
> +	 * devices are, by nature, exclusive.
> +	 */
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +				mx2_camera_base, mx2_camera_base,
> +				MX2_CAMERA_BUF_SIZE,
> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +	if (!(dma & DMA_MEMORY_MAP)) {
> +		pr_err("Failed to declare memory for emmaprp\n");
> +		return;
> +	}
> +}
>  
>  static void __init visstrim_m10_revision(void)
>  {
> @@ -467,13 +494,14 @@ static void __init visstrim_m10_revision(void)
>  	mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
>  
>  	system_rev = 0x27000;
> -	system_rev |= (mo_version << 4);
> -	system_rev |= exp_version;
> +	system_rev |= (mo_version << MOTHERBOARD_SHIFT);
> +	system_rev |= (exp_version << EXPBOARD_SHIFT);
>  }
>  
>  static void __init visstrim_m10_board_init(void)
>  {
>  	int ret;
> +	int mo_version;
>  
>  	imx27_soc_init();
>  	visstrim_m10_revision();
> @@ -505,8 +533,24 @@ static void __init visstrim_m10_board_init(void)
>  	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
>  				      &iclink_tvp5150, sizeof(iclink_tvp5150));
>  	gpio_led_register_device(0, &visstrim_m10_led_data);
> -	visstrim_deinterlace_init();
> -	visstrim_camera_init();
> +
> +	/* Use mother board version to decide what video devices we shall use */
> +	mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
> +	if (mo_version & 0x1) {
> +		visstrim_emmaprp_init();
> +
> +		/*
> +		 * Despite not being used, tvp5150 must be
> +		 * powered on to avoid I2C problems. To minimize
> +		 * power consupmtion keep reset enabled.
> +		 */
> +		gpio_set_value(TVP5150_PWDN, 1);
> +		ndelay(1);
> +		gpio_set_value(TVP5150_RSTN, 0);
> +	} else {
> +		visstrim_deinterlace_init();
> +		visstrim_analog_camera_init();
> +	}
>  	visstrim_coda_init();
>  }
>  
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Fri Aug  3 10:07:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 Aug 2012 14:07:08 +0000
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <201208031407.09092.arnd@arndb.de>

On Friday 03 August 2012, Uwe Kleine-K?nig wrote:
> Hello,
> 
> the only changes compared to v5 (sent starting with Message-id:
> 1341512035-8173-1-git-send-email-u.kleine-koenig at pengutronix.de)
> are that several debug pr_infos were dropped that I missed to remove
> before. Thanks to Will Deacon for pointing out that problem.
> Furthermore I rebased (trivially) to v3.5.

No objections to the code from my side, but I'd like to understand
the big picture here. You introduce a new CPU_V7M configuration
symbol in the code, but there is no Kconfig change that introduces
that symbol. Is that another change that is still coming?

None of the code seems to be specific to Cortex-M3 rather than the
ARMv7M architecture. Does that mean it is expected to run
unmodifed on both M3 and M4, and possibly future ARMv-7M cores?

Is it possible to build a NOMMU kernel that runs on both ARMv7-A
amd ARMv7-M, in other words is ARMv7-M compatible with ARMv7-A
(or ARMv7-R for that matter) if you don't use the MMU?

How does this relate to the ARMv6-M (Cortex-M0/M0+/M1) support
that has been floating around [1]? Can we support both in
the same kernel? 

	Arnd

[1] http://developer.petalogix.com/git/gitweb.cgi?p=linux-2.6.x-cortexm1.git;a=summary


From s.hauer at pengutronix.de  Fri Aug  3 10:11:08 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 16:11:08 +0200
Subject: [PATCH 1/2] ARM: imx: enable emi_slow_gate clock for imx5
In-Reply-To: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>
References: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120803141108.GV1451@pengutronix.de>

On Thu, Aug 02, 2012 at 11:01:51PM +0800, Shawn Guo wrote:
> The imx5 common clock migration causes a regression with smsc911x
> driver on imx53-ard board, where a smsc lan9220 controller gets
> connected on imx53 with EIM interface.  EIM needs clock emi_slow_gate
> to be functional.  In the new imx5 clock driver, there is no use count
> incremented for the clock by enabling it, so the framework closes the
> clock at late init time and makes EIM stop working then.
> 
> Enable emi_slow_gate in clock driver initialization to fix the
> regression.

Can we add a comment that emi_slow_gate is needed for the EIM interface?
It's not obvious from the datasheet and this information might help
people who want to clean up the now unconditionally enabled clocks.

Otherwise:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

> 
> Cc: stable at vger.kernel.org
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index f608669..6eee32a 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	clk_prepare_enable(clk[aips_tz2]); /* fec */
>  	clk_prepare_enable(clk[spba]);
>  	clk_prepare_enable(clk[emi_fast_gate]); /* fec */
> +	clk_prepare_enable(clk[emi_slow_gate]);
>  	clk_prepare_enable(clk[tmax1]);
>  	clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
>  	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
> -- 
> 1.7.5.4
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:52 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:52 +0200
Subject: [v2] arm: mvebu: Add basic address decoding support for Marvell 370/XP
Message-ID: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>

Andrew, Jason, Gr?gory,

Here is a small patch set that introduces basic support for address
decoding on Armada 370 and Armada XP. The aim of this basic support is
essentially to be able to configure a window to remap the BootROM,
which is needed to startup the secondary CPUs for the SMP support.

As we had discussed already, the address decoding configuration is not
described in the Device Tree, it is for now hardcoded on a per-SoC
basis. We might later discuss how to extend this to the Device Tree.

This patch set has five patches:

 (*) First patch reworks the addr-map code to use void __iomem * where
     appropriate instead of u32, as per the suggestion of Arnd
     Bergmann.

 (*) Second patch introducing PLAT_ORION_LEGACY, which allows the
     Marvell 370/XP platforms to be part of PLAT_ORION, and therefore
     re-use the existing address decoding code.

 (*) Third patch making a small change to an address decoding
     structure so that we can define at runtime the virtual address of
     the configuration registers. This is needed as on Armada 370/XP
     the address decoding "controller" is declared in the Device Tree.

 (*) Fourth patch adding the 370/XP address decoding code itself. For
     now, it only maps the BootROM on Armada XP.

 (*) Fifth path adding the necessary DT code to instantiate the
     address decoding "controller".

Changes since v1:
 * Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
 * Add Acked-by on patches 2->5 from Gr?gory Cl?ment

Thanks,

Thomas Petazzoni



From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:53 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:53 +0200
Subject: [PATCH 1/5] arm: plat-orion: use 'void __iomem *' in addr-map code
In-Reply-To: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344003237-13575-2-git-send-email-thomas.petazzoni@free-electrons.com>

Use 'void __iomem *' instead of u32 where appropriate in the addr-map
code. It requires adding a few casts in SoC-specific addr-map.c files,
but those casts will disappear once those SoC are migrated to the
device tree, in which case the address will come from the DT instead
of from #define values.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-dove/addr-map.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c           |    5 +++--
 arch/arm/mach-mv78xx0/addr-map.c            |    4 ++--
 arch/arm/mach-orion5x/addr-map.c            |    5 +++--
 arch/arm/plat-orion/addr-map.c              |   11 ++++-------
 arch/arm/plat-orion/include/plat/addr-map.h |    4 ++--
 6 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 2a06c01..adb428e 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i)
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180..2b27de6 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -41,7 +41,7 @@
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d7..bac31e4 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
 	 */
 	if (mv78xx0_core_index() == 0)
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU0_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU0_BASE);
 	else
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU1_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d..bfe4f10 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
 static struct orion_addr_map_cfg addr_map_cfg __initdata = {
 	.num_wins = 8,
 	.cpu_win_can_remap = cpu_win_can_remap,
-	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) ORION5X_BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89..a7b8060 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-	return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+	return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base)
+					const void __iomem *ddr_window_cpu_base)
 {
-	void __iomem *addr;
 	int i;
 	int cs;
 
 	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-	addr = (void __iomem *)ddr_window_cpu_base;
-
 	for (i = 0, cs = 0; i < 4; i++) {
-		u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-		u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+		u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+		u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
 		/*
 		 * Chip select enabled?
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f7..0a746fd 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	const u32 bridge_virt_base;
+	void __iomem * const bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
 				const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base);
+					const void __iomem *ddr_window_cpu_base);
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:55 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:55 +0200
Subject: [PATCH 3/5] arm: plat-orion: make bridge_virt_base non-const to
 support DT use case
In-Reply-To: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344003237-13575-4-git-send-email-thomas.petazzoni@free-electrons.com>

For the Armada 370 and XP SoCs where the DT is used, we need to fill
at runtime the bridge_virt_base field on the
orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this
field.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/plat-orion/include/plat/addr-map.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index 0a746fd..ec63e4a 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	void __iomem * const bridge_virt_base;
+	void __iomem *bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:57 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:57 +0200
Subject: [PATCH 5/5] arm: mvebu: add address decoding controller to the DT
In-Reply-To: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344003237-13575-6-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..16cc82c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+		addr-decoding at d0020000 {
+			compatible = "marvell,armada-addr-decoding-controller";
+			reg = <0xd0020000 0x258>;
+		};
 	};
 };
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:54 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:54 +0200
Subject: [PATCH 2/5] arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
 config option
In-Reply-To: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344003237-13575-3-git-send-email-thomas.petazzoni@free-electrons.com>

Until now, the PLAT_ORION configuration option was common to all the
Marvell EBU SoCs, and selecting this option had the effect of enabling
the MPP code, GPIO code, address decoding and PCIe code from
plat-orion, as well as providing access to driver-specific header
files from plat-orion/include.

However, the Armada 370 and XP SoCs will not use the MPP and GPIO code
(instead some proper pinctrl and gpio drivers are in preparation), and
generally, we want to move away from plat-orion and instead have
everything in mach-mvebu.

That said, in the mean time, we want to leverage the driver-specific
headers as well as the address decoding code, so we introduce
PLAT_ORION_LEGACY. The older Marvell SoCs need to select
PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select
PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it
automatically selects PLAT_ORION.

Then, with just PLAT_ORION, you have the address decoding code plus
the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you
gain the old MPP, GPIO and PCIe code.

Again, this is only a temporary solution until we make all Marvell EBU
platforms converge into the mach-mvebu directory. This solution avoids
duplicating the existing address decoding code into mach-mvebu.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig             |   13 +++++++++----
 arch/arm/plat-orion/Makefile |    9 ++++-----
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7980873..fc36a93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PLAT_ORION
 	help
 	  Support for the Marvell SoC Family with device tree support
 
@@ -583,7 +584,7 @@ config ARCH_DOVE
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
@@ -594,7 +595,7 @@ config ARCH_KIRKWOOD
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.
@@ -621,7 +622,7 @@ config ARCH_MV78XX0
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.
@@ -634,7 +635,7 @@ config ARCH_ORION5X
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Orion 5x series SoCs:
 	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1153,6 +1154,10 @@ config PLAT_ORION
 	select GENERIC_IRQ_CHIP
 	select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+	bool
+	select PLAT_ORION
+
 config PLAT_PXA
 	bool
 
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f..1251e5b 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,9 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m	:=
-obj-n	:=
-obj-	:=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Fri Aug  3 10:13:56 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri,  3 Aug 2012 16:13:56 +0200
Subject: [PATCH 4/5] arm: mvebu: add basic address decoding support to Armada
 370/XP
In-Reply-To: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344003237-13575-5-git-send-email-thomas.petazzoni@free-electrons.com>

This commit adds basic support for address decoding configuration for
the Armada 370 and Armada XP SoCs, re-using the infrastructure
provided in plat-orion.

For now, only a BootROM window is configured on Armada XP, which is
needed to get the non-boot CPUs started and is therefore a requirement
for SMP support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mvebu/Makefile   |    2 +-
 arch/arm/mach-mvebu/addr-map.c |  134 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mvebu/addr-map.c

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8..2143558 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,2 @@
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 0000000..4a371a3
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS	1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1		3
+#define ARMADA_XP_TARGET_PCIE_0_2	4
+#define ARMADA_XP_TARGET_ETH0		7
+#define ARMADA_XP_TARGET_PCIE_1_3	8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+	/*
+	 * Window for the BootROM, needed for SMP on Armada XP
+	 */
+	{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+	  ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+	{ .compatible = "marvell,armada-addr-decoding-controller" },
+	{ /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+	unsigned int offset;
+
+	/* The register layout is a bit annoying and the below code
+	 * tries to cope with it.
+	 * - At offset 0x0, there are the registers for the first 8
+	 *   windows, with 4 registers of 32 bits per window (ctrl,
+	 *   base, remap low, remap high)
+	 * - Then at offset 0x80, there is a hole of 0x10 bytes for
+	 *   the internal registers base address and internal units
+	 *   sync barrier register.
+	 * - Then at offset 0x90, there the registers for 12
+	 *   windows, with only 2 registers of 32 bits per window
+	 *   (ctrl, base).
+	 */
+	if (win < 8)
+		offset = (win << 4);
+	else
+		offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+	return (void __iomem *)(cfg->bridge_virt_base + offset);
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+	.num_wins = 20,
+	.remappable_wins = 8,
+	.win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+	struct device_node *np;
+	void __iomem *mbus_unit_addr_decoding_base;
+	void __iomem *sdram_addr_decoding_base;
+
+	np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+	if (!np)
+		return -ENODEV;
+
+	mbus_unit_addr_decoding_base = of_iomap(np, 0);
+	BUG_ON(!mbus_unit_addr_decoding_base);
+
+	sdram_addr_decoding_base =
+		mbus_unit_addr_decoding_base +
+		ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+	addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+	/*
+	 * Disable, clear and configure windows.
+	 */
+	if (of_machine_is_compatible("marvell,armadaxp"))
+		orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+	else if (of_machine_is_compatible("marvell,armada370"))
+		orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+	else {
+		pr_err("Unsupported SoC\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    sdram_addr_decoding_base);
+	return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
-- 
1.7.9.5



From shawn.guo at linaro.org  Fri Aug  3 10:15:15 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 22:15:15 +0800
Subject: [PATCH 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1343922986-32469-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1343922986-32469-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120803141512.GC23791@S2101-09.ap.freescale.net>

On Thu, Aug 02, 2012 at 05:56:26PM +0200, Uwe Kleine-K?nig wrote:
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/dts/phytec-pcm043.dtsi |   49 ++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 arch/arm/boot/dts/phytec-pcm043.dtsi
> 
> diff --git a/arch/arm/boot/dts/phytec-pcm043.dtsi b/arch/arm/boot/dts/phytec-pcm043.dtsi
> new file mode 100644
> index 0000000..420627c
> --- /dev/null
> +++ b/arch/arm/boot/dts/phytec-pcm043.dtsi
> @@ -0,0 +1,49 @@
> +/include/ "imx35.dtsi"
> +
> +/ {
> +	soc {
> +		aips at 40000000 { /* AIPS1 */
> +			i2c at 43f80000 {
> +				status = "okay";
> +
> +				tempsens at 4a {
> +					compatible = "maxim,ds75";
> +					reg = <0x4a>;
> +				};

Again, please put a new line between nodes.

> +				rtc8564 at 51 {
> +					compatible = "nxp,pcf8563";
> +					reg = <0x51>;
> +				};
> +				at24 at 52 {
> +					compatible = "at,24c32";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};
> +			};
> +			uart at 43f90000 {
> +				status = "okay";
> +			};
> +			uart at 43f94000 {
> +				status = "okay";
> +			};
> +		};
> +		spba at 50000000 {
> +			uart at 5000c000 {
> +				status = "okay";
> +			};
> +			fec at 50038000 {
> +				status = "okay";
> +			};
> +		};
> +
> +		nor at a0000000 {
> +			compatible = "cfi-flash";
> +			reg = <0xa0000000 0x2000000>;
> +			bank-width = <2>;
> +		};
> +
We should be able to see how this device is connected to SoC with this
node under proper interface and bus topology.

> +		nand at bb000000 {
> +			status = "okay";
> +		};

Ditto.

> +	};
> +};
> -- 
> 1.7.10.4
> 

-- 
Regards,
Shawn



From s.hauer at pengutronix.de  Fri Aug  3 10:17:33 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 16:17:33 +0200
Subject: [PATCH 2/2 v2] i.MX27: Visstrim_M10: Add support for
 deinterlacing driver.
In-Reply-To: <1342092929-31590-2-git-send-email-javier.martin@vista-silicon.com>
References: <1342092929-31590-1-git-send-email-javier.martin@vista-silicon.com>
 <1342092929-31590-2-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120803141733.GW1451@pengutronix.de>

On Thu, Jul 12, 2012 at 01:35:29PM +0200, Javier Martin wrote:
> Visstrim_M10 have a tvp5150 whose video output must be deinterlaced.
> The new mem2mem deinterlacing driver is very useful for that purpose.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
> Changes since v1:
>  - Removed commented out code.
> 
> ---
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index 214e4ff..dbef59d 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -232,7 +232,7 @@ static void __init visstrim_camera_init(void)
>  static void __init visstrim_reserve(void)
>  {
>  	/* reserve 4 MiB for mx2-camera */
> -	mx2_camera_base = arm_memblock_steal(2 * MX2_CAMERA_BUF_SIZE,
> +	mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
>  			MX2_CAMERA_BUF_SIZE);
>  }
>  
> @@ -419,6 +419,30 @@ static void __init visstrim_coda_init(void)
>  		return;
>  }
>  
> +/* DMA deinterlace */
> +static struct platform_device visstrim_deinterlace = {
> +	.name = "m2m-deinterlace",
> +	.id = 0,
> +};
> +
> +static void __init visstrim_deinterlace_init(void)
> +{
> +	int ret = -ENOMEM;
> +	struct platform_device *pdev = &visstrim_deinterlace;
> +	int dma;
> +
> +	ret = platform_device_register(pdev);

ret is unused.

Better use platform_device_register_simple().

> +
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +					  mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
> +					  mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
> +					  MX2_CAMERA_BUF_SIZE,
> +					  DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);

Shouldn't this be done before registering the device?

> +	if (!(dma & DMA_MEMORY_MAP))
> +		return;
> +}

if (!flag) return; else return ?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shawn.guo at linaro.org  Fri Aug  3 10:23:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 22:23:04 +0800
Subject: [PATCH 1/2] ARM: imx: enable emi_slow_gate clock for imx5
In-Reply-To: <20120803141108.GV1451@pengutronix.de>
References: <1343919712-6240-1-git-send-email-shawn.guo@linaro.org>
 <20120803141108.GV1451@pengutronix.de>
Message-ID: <20120803142302.GD23791@S2101-09.ap.freescale.net>

On Fri, Aug 03, 2012 at 04:11:08PM +0200, Sascha Hauer wrote:
> Can we add a comment that emi_slow_gate is needed for the EIM interface?
> It's not obvious from the datasheet and this information might help
> people who want to clean up the now unconditionally enabled clocks.
> 
Ok, will amend the following change.

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6eee32a..4bdcaa9 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -303,7 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_prepare_enable(clk[aips_tz2]); /* fec */
        clk_prepare_enable(clk[spba]);
        clk_prepare_enable(clk[emi_fast_gate]); /* fec */
-       clk_prepare_enable(clk[emi_slow_gate]);
+       clk_prepare_enable(clk[emi_slow_gate]); /* eim */
        clk_prepare_enable(clk[tmax1]);
        clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
        clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */

> Otherwise:
> 
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
Thanks.

-- 
Regards,
Shawn



From arnd at arndb.de  Fri Aug  3 10:23:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 Aug 2012 14:23:09 +0000
Subject: arm: mvebu: Add basic address decoding support for Marvell 370/XP
In-Reply-To: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <201208031423.10561.arnd@arndb.de>

On Friday 03 August 2012, Thomas Petazzoni wrote:
> Here is a small patch set that introduces basic support for address
> decoding on Armada 370 and Armada XP. The aim of this basic support is
> essentially to be able to configure a window to remap the BootROM,
> which is needed to startup the secondary CPUs for the SMP support.
> 
> As we had discussed already, the address decoding configuration is not
> described in the Device Tree, it is for now hardcoded on a per-SoC
> basis. We might later discuss how to extend this to the Device Tree.

Makes sense. I wonder if there is a proper way to describe the
setting in the device tree anyway, given that there is more than one
valid option to do it.


	Arnd


From kishon at ti.com  Fri Aug  3 10:23:41 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 19:53:41 +0530
Subject: [PATCH v2 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <20120803132046.GA8269@arwen.pp.htv.fi>
References: <1342593039-7728-1-git-send-email-kishon@ti.com>
 <1342593039-7728-2-git-send-email-kishon@ti.com>
 <20120803132046.GA8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6Kk=YxwzcueZzriECiLCciaY3UAW+xfhhc-zyz5YWwXEA@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 6:50 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Wed, Jul 18, 2012 at 12:00:38PM +0530, Kishon Vijay Abraham I wrote:
>> Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
>> creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
>> USB2PHY is connected to ocp2scp.
>>
>> This also includes device tree support for ocp2scp driver and
>> the documentation with device tree binding information is updated.
>>
>> Cc: Felipe Balbi <balbi at ti.com>
>
> If you fix (or change my mind) on the comment below, you can add:
>
> Acked-by: Felipe Balbi <balbi at ti.com>
>
>
> Also, I wonder who should be the one to take this. Who will be queueing
> patches on this directory to mainline ?
>
>> Acked-by: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>> ---
>>  .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 ++
>>  drivers/Kconfig                                    |    2 +
>>  drivers/Makefile                                   |    2 +
>>  drivers/bus/Kconfig                                |   15 +++
>>  drivers/bus/Makefile                               |    5 +
>>  drivers/bus/omap-ocp2scp.c                         |   98 ++++++++++++++++++++
>>  6 files changed, 132 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
>>  create mode 100644 drivers/bus/Kconfig
>>  create mode 100644 drivers/bus/Makefile
>>  create mode 100644 drivers/bus/omap-ocp2scp.c
>>
>> diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
>> new file mode 100644
>> index 0000000..d2fe064
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
>> @@ -0,0 +1,10 @@
>> +* OMAP OCP2SCP - ocp interface to scp interface
>> +
>> +properties:
>> +- compatible : Should be "ti,omap-ocp2scp"
>> +- #address-cells, #size-cells : Must be present if the device has sub-nodes
>> +- ranges : the child address space are mapped 1:1 onto the parent address space
>> +- ti,hwmods : must be "ocp2scp_usb_phy"
>> +
>> +Sub-nodes:
>> +All the devices connected to ocp2scp are described using sub-node to ocp2scp
>> diff --git a/drivers/Kconfig b/drivers/Kconfig
>> index bfc9186..4fe1e4c 100644
>> --- a/drivers/Kconfig
>> +++ b/drivers/Kconfig
>> @@ -2,6 +2,8 @@ menu "Device Drivers"
>>
>>  source "drivers/base/Kconfig"
>>
>> +source "drivers/bus/Kconfig"
>> +
>>  source "drivers/connector/Kconfig"
>>
>>  source "drivers/mtd/Kconfig"
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index 2ba29ff..cac3819 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -5,6 +5,8 @@
>>  # Rewritten to use lists instead of if-statements.
>>  #
>>
>> +obj-y                                += bus/
>> +
>>  # GPIO must come after pinctrl as gpios may need to mux pins etc
>>  obj-y                                += pinctrl/
>>  obj-y                                += gpio/
>> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
>> new file mode 100644
>> index 0000000..6270415
>> --- /dev/null
>> +++ b/drivers/bus/Kconfig
>> @@ -0,0 +1,15 @@
>> +#
>> +# Bus Devices
>> +#
>> +
>> +menu "Bus devices"
>> +
>> +config OMAP_OCP2SCP
>> +     tristate "OMAP OCP2SCP DRIVER"
>> +     help
>> +       Driver to enable ocp2scp module which transforms ocp interface
>> +       protocol to scp protocol. In OMAP4, USB PHY is connected via
>> +       OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
>> +       OCP2SCP.
>> +
>> +endmenu
>> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
>> new file mode 100644
>> index 0000000..0ec50bc
>> --- /dev/null
>> +++ b/drivers/bus/Makefile
>> @@ -0,0 +1,5 @@
>> +#
>> +# Makefile for the bus drivers.
>> +#
>> +
>> +obj-$(CONFIG_OMAP_OCP2SCP)   += omap-ocp2scp.o
>> diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
>> new file mode 100644
>> index 0000000..8c3db3a
>> --- /dev/null
>> +++ b/drivers/bus/omap-ocp2scp.c
>> @@ -0,0 +1,98 @@
>> +/*
>> + * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
>> + *
>> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Author: Kishon Vijay Abraham I <kishon at ti.com>
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/err.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +
>> +static int ocp2scp_remove_devices(struct device *dev, void *c)
>> +{
>> +     struct platform_device *pdev = to_platform_device(dev);
>> +
>> +     platform_device_unregister(pdev);
>> +
>> +     return 0;
>> +}
>> +
>> +static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
>> +{
>> +     int                     ret;
>> +     struct device_node      *np = pdev->dev.of_node;
>> +
>> +     if (np) {
>> +             ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
>> +             if (ret) {
>> +                     dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
>> +                     goto err0;
>> +             }
>> +     }
>> +     pm_runtime_enable(&pdev->dev);
>> +
>> +     return 0;
>> +
>> +err0:
>> +     device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
>> +
>> +     return ret;
>> +}
>> +
>> +static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
>> +{
>> +     pm_runtime_disable(&pdev->dev);
>> +     device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id omap_ocp2scp_id_table[] = {
>> +     { .compatible = "ti,omap-ocp2scp" },
>> +     {}
>> +};
>> +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
>> +#endif
>> +
>> +static struct platform_driver omap_ocp2scp_driver = {
>> +     .probe          = omap_ocp2scp_probe,
>> +     .remove         = __devexit_p(omap_ocp2scp_remove),
>> +     .driver         = {
>> +             .name   = "omap-ocp2scp",
>> +             .owner  = THIS_MODULE,
>> +             .of_match_table = of_match_ptr(omap_ocp2scp_id_table),
>> +     },
>> +};
>> +
>> +static int __init omap_ocp2scp_init(void)
>> +{
>> +     return platform_driver_register(&omap_ocp2scp_driver);
>> +}
>> +arch_initcall(omap_ocp2scp_init);
>
> I really think we should avoid this trickery and make dependent drivers
> return -EPROBE_DEFER case this isn't ready yet.

Ok. Will do it that way in my next series.

Thanks
Kishon


From s.hauer at pengutronix.de  Fri Aug  3 10:26:52 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 16:26:52 +0200
Subject: [PATCH] arm imx31: add a few pinmux settings the tt01 needs
In-Reply-To: <1342616305-24722-1-git-send-email-torbenh@linutronix.de>
References: <1342616305-24722-1-git-send-email-torbenh@linutronix.de>
Message-ID: <20120803142652.GY1451@pengutronix.de>

On Wed, Jul 18, 2012 at 02:58:25PM +0200, Torben Hohn wrote:
> These are the Pinmux Settings for the PP4 SSI Port multiplexible
> onto the first UART Pins.
> 
> Signed-off-by: Torben Hohn <torbenh at linutronix.de>

Applied, thanks

Sascha

> ---
>  arch/arm/plat-mxc/include/mach/iomux-mx3.h |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
> index 63f22a0..019b0a0 100644
> --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
> @@ -515,12 +515,16 @@ enum iomux_pins {
>  #define MX31_PIN_CSPI3_SPI_RDY__CTS3	IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
>  #define MX31_PIN_CTS1__CTS1		IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_RTS1__RTS1		IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
> +#define MX31_PIN_RTS1__SFS		IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
>  #define MX31_PIN_TXD1__TXD1		IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
> +#define MX31_PIN_TXD1__SCK		IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
>  #define MX31_PIN_RXD1__RXD1		IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
> +#define MX31_PIN_RXD1__STXDA		IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
>  #define MX31_PIN_DCD_DCE1__DCD_DCE1	IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_RI_DCE1__RI_DCE1	IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_DSR_DCE1__DSR_DCE1	IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_DTR_DCE1__DTR_DCE1	IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
> +#define MX31_PIN_DTR_DCE1__SRXDA	IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
>  #define MX31_PIN_CTS2__CTS2		IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_RTS2__RTS2		IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_TXD2__TXD2		IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
> @@ -724,6 +728,7 @@ enum iomux_pins {
>  #define MX31_PIN_KEY_ROW2_KEY_ROW2	IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_KEY_ROW3_KEY_ROW3	IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_KEY_ROW4_KEY_ROW4	IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
> +#define MX31_PIN_KEY_ROW4_GPIO		IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
>  #define MX31_PIN_KEY_ROW5_KEY_ROW5	IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_KEY_ROW6_KEY_ROW6	IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
>  #define MX31_PIN_KEY_ROW7_KEY_ROW7	IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
> -- 
> 1.7.10
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Aug  3 10:27:41 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 3 Aug 2012 16:27:41 +0200
Subject: [PATCH] ARM: dts: imx27-3ds.dts: Fix serial console node
In-Reply-To: <1343658196-24243-1-git-send-email-fabio.estevam@freescale.com>
References: <1343658196-24243-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120803142741.GZ1451@pengutronix.de>

On Mon, Jul 30, 2012 at 11:23:16AM -0300, Fabio Estevam wrote:
> Fix serial console node and allow the board to boot again.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx27-3ds.dts |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)

Applied as fix, thanks

Sascha

> 
> diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
> index d3f8296..0a8978a 100644
> --- a/arch/arm/boot/dts/imx27-3ds.dts
> +++ b/arch/arm/boot/dts/imx27-3ds.dts
> @@ -27,7 +27,7 @@
>  				status = "okay";
>  			};
>  
> -			uart at 1000a000 {
> +			uart1: serial at 1000a000 {
>  				fsl,uart-has-rtscts;
>  				status = "okay";
>  			};
> -- 
> 1.7.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From maxime.ripard at free-electrons.com  Fri Aug  3 10:30:39 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri,  3 Aug 2012 16:30:39 +0200
Subject: [PATCH] SPI: MXS: Allow to pass the SPI master bus number from the
 device tree
In-Reply-To: <1343076052-27312-1-git-send-email-marex@denx.de>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
Message-ID: <1344004239-22868-1-git-send-email-maxime.ripard@free-electrons.com>

If you don't do it, the bus number will be a bogus value, possibly used
for device file names in drivers like spidev.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 drivers/spi/spi-mxs.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index d6a80a1..d6a73ef 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -527,6 +527,15 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	if (!master)
 		return -ENOMEM;
 
+	if (pdev->id != -1)
+		master->bus_num = pdev->id;
+	if (np) {
+		unsigned long prop;
+
+		of_property_read_u32(np, "cell-index", &prop);
+		master->bus_num = prop;
+	}
+
 	master->transfer_one_message = mxs_spi_transfer_one;
 	master->setup = mxs_spi_setup;
 	master->cleanup = mxs_spi_cleanup;
-- 
1.7.9.5



From kishon at ti.com  Fri Aug  3 10:31:44 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:01:44 +0530
Subject: [PATCH v6 01/11] drivers: usb: otg: add a new driver for omap
 usb2 phy
In-Reply-To: <20120803132708.GC8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-2-git-send-email-kishon@ti.com>
 <20120803132708.GC8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6K15Nm5aNs2Vn71G7ELZWka1zB2E3VGZWTc0VjyViJ6Yw@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 6:57 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Mon, Jul 30, 2012 at 02:39:50PM +0530, Kishon Vijay Abraham I wrote:
>> All phy related programming like enabling/disabling the clocks, powering
>> on/off the phy is taken care of by this driver. It is also used for OTG
>> related functionality like srp.
>>
>> This also includes device tree support for usb2 phy driver and
>> the documentation with device tree binding information is updated.
>>
>> Currently writing to control module register is taken care in this
>> driver which will be removed once the control module driver is in place.
>>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>> ---
>>  .../devicetree/bindings/bus/omap-ocp2scp.txt       |    3 +
>>  Documentation/devicetree/bindings/usb/omap-usb.txt |   17 ++
>>  drivers/usb/otg/Kconfig                            |   10 +
>>  drivers/usb/otg/Makefile                           |    1 +
>>  drivers/usb/otg/omap-usb2.c                        |  280 ++++++++++++++++++++
>
> let's move this to drivers/usb/phy/. I'll prepare a patch moving all phy
> drivers to that directory after the OTG state machine is ready ;-)

Ok.
>
>> diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
>> new file mode 100644
>> index 0000000..52f503b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
>> @@ -0,0 +1,17 @@
>> +OMAP USB PHY
>> +
>> +OMAP USB2 PHY
>> +
>> +Required properties:
>> + - compatible: Should be "ti,omap-usb2"
>> + - reg : Address and length of the register set for the device. Also
>> +add the address of control module dev conf register until a driver for
>> +control module is added
>> +
>> +This is usually a subnode of ocp2scp to which it is connected.
>> +
>> +usb2phy at 4a0ad080 {
>> +     compatible = "ti,omap-usb2";
>> +     reg = <0x4a0ad080 0x58>,
>> +             <0x4a002300 0x1>;
>> +};
>> diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
>> index 5c87db0..c751db7 100644
>> --- a/drivers/usb/otg/Kconfig
>> +++ b/drivers/usb/otg/Kconfig
>> @@ -78,6 +78,16 @@ config TWL6030_USB
>>         are hooked to this driver through platform_data structure.
>>         The definition of internal PHY APIs are in the mach-omap2 layer.
>>
>> +config OMAP_USB2
>> +     tristate "OMAP USB2 PHY Driver"
>> +     depends on OMAP_OCP2SCP
>> +     select USB_OTG_UTILS
>> +     help
>> +       Enable this to support the transceiver that is part of SOC. This
>> +       driver takes care of all the PHY functionality apart from comparator.
>> +       The USB OTG controller communicates with the comparator using this
>> +       driver.
>> +
>>  config NOP_USB_XCEIV
>>       tristate "NOP USB Transceiver Driver"
>>       select USB_OTG_UTILS
>> diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
>> index 41aa509..2c2a3ca 100644
>> --- a/drivers/usb/otg/Makefile
>> +++ b/drivers/usb/otg/Makefile
>> @@ -13,6 +13,7 @@ obj-$(CONFIG_USB_GPIO_VBUS) += gpio_vbus.o
>>  obj-$(CONFIG_ISP1301_OMAP)   += isp1301_omap.o
>>  obj-$(CONFIG_TWL4030_USB)    += twl4030-usb.o
>>  obj-$(CONFIG_TWL6030_USB)    += twl6030-usb.o
>> +obj-$(CONFIG_OMAP_USB2)              += omap-usb2.o
>>  obj-$(CONFIG_NOP_USB_XCEIV)  += nop-usb-xceiv.o
>>  obj-$(CONFIG_USB_ULPI)               += ulpi.o
>>  obj-$(CONFIG_USB_ULPI_VIEWPORT)      += ulpi_viewport.o
>> diff --git a/drivers/usb/otg/omap-usb2.c b/drivers/usb/otg/omap-usb2.c
>> new file mode 100644
>> index 0000000..026cb3c
>> --- /dev/null
>> +++ b/drivers/usb/otg/omap-usb2.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
>> + *
>> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Author: Kishon Vijay Abraham I <kishon at ti.com>
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/of.h>
>> +#include <linux/io.h>
>> +#include <linux/usb/omap_usb.h>
>> +#include <linux/usb/phy_companion.h>
>> +#include <linux/clk.h>
>> +#include <linux/err.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/delay.h>
>> +
>> +/**
>> + * omap_usb2_set_comparator - links the comparator present in the sytem with
>> + *   this phy
>> + * @comparator - the companion phy(comparator) for this phy
>> + *
>> + * The phy companion driver should call this API passing the phy_companion
>> + * filled with set_vbus and start_srp to be used by usb phy.
>> + *
>> + * For use by phy companion driver
>> + */
>> +void omap_usb2_set_comparator(struct phy_companion *comparator)
>> +{
>> +     struct omap_usb *phy;
>> +     struct usb_phy  *x = usb_get_phy(USB_PHY_TYPE_USB2);
>> +
>> +     if (x) {
>> +             phy = phy_to_omapusb(x);
>> +             phy->comparator = comparator;
>> +     }
>> +}
>> +EXPORT_SYMBOL_GPL(omap_usb2_set_comparator);
>> +
>> +/**
>> + * omap_usb_phy_power - power on/off the phy using control module reg
>> + * @phy: struct omap_usb *
>> + * @on: 0 or 1, based on powering on or off the PHY
>> + *
>> + * XXX: Remove this function once control module driver gets merged
>> + */
>> +static void omap_usb_phy_power(struct omap_usb *phy, int on)
>> +{
>> +     u32 val;
>> +
>> +     if (on) {
>> +             val = readl(phy->control_dev);
>> +             if (val & PHY_PD) {
>> +                     writel(~PHY_PD, phy->control_dev);
>> +                     /* XXX: add proper documentation for this delay */
>> +                     mdelay(200);
>> +             }
>> +     } else {
>> +             writel(PHY_PD, phy->control_dev);
>> +     }
>> +}
>> +
>> +static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
>> +{
>> +     struct omap_usb *phy = phy_to_omapusb(otg->phy);
>> +
>> +     if (!phy->comparator)
>> +             return -ENODEV;
>> +
>> +     return phy->comparator->set_vbus(phy->comparator, enabled);
>> +}
>> +
>> +static int omap_usb_start_srp(struct usb_otg *otg)
>> +{
>> +     struct omap_usb *phy = phy_to_omapusb(otg->phy);
>> +
>> +     if (!phy->comparator)
>> +             return -ENODEV;
>> +
>> +     return phy->comparator->start_srp(phy->comparator);
>> +}
>> +
>> +static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
>> +{
>> +     struct usb_phy  *phy = otg->phy;
>> +
>> +     otg->host = host;
>> +     if (!host)
>> +             phy->state = OTG_STATE_UNDEFINED;
>> +
>> +     return 0;
>> +}
>> +
>> +static int omap_usb_set_peripheral(struct usb_otg *otg,
>> +             struct usb_gadget *gadget)
>> +{
>> +     struct usb_phy  *phy = otg->phy;
>> +
>> +     otg->gadget = gadget;
>> +     if (!gadget)
>> +             phy->state = OTG_STATE_UNDEFINED;
>> +
>> +     return 0;
>> +}
>> +
>> +static int omap_usb2_suspend(struct usb_phy *x, int suspend)
>> +{
>> +     u32 ret;
>> +     struct omap_usb *phy = phy_to_omapusb(x);
>> +
>> +     if (suspend && !phy->is_suspended) {
>> +             omap_usb_phy_power(phy, 0);
>> +             pm_runtime_put_sync(phy->dev);
>> +             phy->is_suspended = 1;
>> +     } else if (!suspend && phy->is_suspended) {
>> +             ret = pm_runtime_get_sync(phy->dev);
>> +             if (ret < 0) {
>> +                     dev_err(phy->dev, "get_sync failed with err %d\n",
>> +                                                                     ret);
>> +                     return ret;
>> +             }
>> +             omap_usb_phy_power(phy, 1);
>> +             phy->is_suspended = 0;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static int __devinit omap_usb2_probe(struct platform_device *pdev)
>> +{
>> +     struct omap_usb                 *phy;
>> +     struct usb_otg                  *otg;
>> +     struct resource                 *res;
>> +
>> +     phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
>> +     if (!phy) {
>> +             dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
>> +             return -ENOMEM;
>> +     }
>> +
>> +     otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
>> +     if (!otg) {
>> +             dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
>> +             return -ENOMEM;
>> +     }
>> +
>> +     phy->dev                = &pdev->dev;
>> +
>> +     phy->phy.dev            = phy->dev;
>> +     phy->phy.label          = "omap-usb2";
>> +     phy->phy.set_suspend    = omap_usb2_suspend;
>> +     phy->phy.otg            = otg;
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +
>> +     phy->control_dev = devm_request_and_ioremap(&pdev->dev, res);
>> +     if (phy->control_dev == NULL) {
>> +             dev_err(&pdev->dev, "Failed to obtain io memory\n");
>> +             return -ENXIO;
>> +     }
>> +
>> +     phy->is_suspended       = 1;
>> +     omap_usb_phy_power(phy, 0);
>> +
>> +     otg->set_host           = omap_usb_set_host;
>> +     otg->set_peripheral     = omap_usb_set_peripheral;
>> +     otg->set_vbus           = omap_usb_set_vbus;
>> +     otg->start_srp          = omap_usb_start_srp;
>> +     otg->phy                = &phy->phy;
>> +
>> +     phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
>> +     if (IS_ERR(phy->wkupclk)) {
>> +             dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
>> +             return PTR_ERR(phy->wkupclk);
>> +     }
>> +     clk_prepare(phy->wkupclk);
>> +
>> +     usb_add_phy(&phy->phy, USB_PHY_TYPE_USB2);
>> +
>> +     platform_set_drvdata(pdev, phy);
>> +
>> +     pm_runtime_enable(phy->dev);
>> +
>> +     return 0;
>> +}
>> +
>> +static int __devexit omap_usb2_remove(struct platform_device *pdev)
>> +{
>> +     struct omap_usb *phy = platform_get_drvdata(pdev);
>> +
>> +     clk_unprepare(phy->wkupclk);
>> +     usb_remove_phy(&phy->phy);
>> +     platform_set_drvdata(pdev, NULL);
>
> this platform_set_drvdata() is unnecessary as the pdev object will be
> destroyed.

Fine. Will remove it.
>
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM_RUNTIME
>> +
>> +static int omap_usb2_runtime_suspend(struct device *dev)
>> +{
>> +     struct platform_device  *pdev = to_platform_device(dev);
>> +     struct omap_usb *phy = platform_get_drvdata(pdev);
>> +
>> +     clk_disable(phy->wkupclk);
>
> weird. I would expect the wakeup clock to be enabled on suspend and
> disabled on resume. Isn't this causing any unbalanced disable warnings ?

Even I was expecting the wakeup clock to be enabled on suspend but if
we have this enabled coreaon domain is never
gated and core does not hit low power state. btw Why do think this is
unbalanced?
>
>> +
>> +     return 0;
>> +}
>> +
>> +static int omap_usb2_runtime_resume(struct device *dev)
>> +{
>> +     u32 ret = 0;
>> +     struct platform_device  *pdev = to_platform_device(dev);
>> +     struct omap_usb *phy = platform_get_drvdata(pdev);
>> +
>> +     ret = clk_enable(phy->wkupclk);
>> +     if (ret < 0)
>> +             dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
>> +
>> +     return ret;
>> +}
>> +
>> +static const struct dev_pm_ops omap_usb2_pm_ops = {
>> +     SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
>> +             NULL)
>
> only runtime ? What about static suspend ? We need this to work also
> after a traditional echo mem > /sys/power/state ;-)

The static suspend case is handled by users of this phy using set_suspend hooks.
>
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id omap_usb2_id_table[] = {
>> +     { .compatible = "ti,omap-usb2" },
>> +     {}
>> +};
>> +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
>> +#endif
>> +
>> +static struct platform_driver omap_usb2_driver = {
>> +     .probe          = omap_usb2_probe,
>> +     .remove         = __devexit_p(omap_usb2_remove),
>> +     .driver         = {
>> +             .name   = "omap-usb2",
>> +             .owner  = THIS_MODULE,
>> +             .pm     = DEV_PM_OPS,
>> +             .of_match_table = of_match_ptr(omap_usb2_id_table),
>> +     },
>> +};
>> +
>> +static int __init usb2_omap_init(void)
>> +{
>> +     return platform_driver_register(&omap_usb2_driver);
>> +}
>> +arch_initcall(usb2_omap_init);
>
> I'd really like to see this converted into a module_platform_driver().
> If you have dependencies, just make sure to return -EPROBE_DEFER so your
> probe gets retried.

Sure.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:33:13 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:03:13 +0530
Subject: [PATCH v6 03/11] drivers: usb: otg: make twl6030_usb as a
 comparator driver to omap_usb2
In-Reply-To: <20120803132852.GE8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-4-git-send-email-kishon@ti.com>
 <20120803132852.GE8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6+HZfotZyf=YGf16hvNgZN5Pdk2zz+ywcFR71D=JxQ=XA@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 6:58 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:39:52PM +0530, Kishon Vijay Abraham I wrote:
>> All the PHY configuration other than VBUS, ID GND and OTG SRP are removed
>> from twl6030. The phy configurations are taken care by the dedicated
>> usb2 phy driver. So twl6030 is made as comparator driver for VBUS and
>> ID detection.
>>
>> Writing to control module which is now handled in omap2430.c should be
>> removed once a driver for control module is in place.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> This looks good for the time being. Do you think it has any hard
> dependencies on your new phy drivers, or can I apply this without those
> other patches ??

It has a hard dependency on usb2phy driver.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:37:49 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:07:49 +0530
Subject: [PATCH v6 04/11] arm: omap: hwmod: add a new addr space in otg
 for writing to control module
In-Reply-To: <20120803132945.GF8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-5-git-send-email-kishon@ti.com>
 <20120803132945.GF8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6Lm3v-g64QmWzJJs_mZ-Qy4_YK5WKnt_B-P7sbRDNq=Jg@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 6:59 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Mon, Jul 30, 2012 at 02:39:53PM +0530, Kishon Vijay Abraham I wrote:
>> The mailbox register for usb otg in omap is present in control module.
>> On detection of any events VBUS or ID, this register should be written
>> to send the notification to musb core.
>>
>> Till we have a separate control module driver to write to control module,
>> omap2430 will handle the register writes to control module by itself. So
>> a new address space to represent this control module register is added
>> to usb_otg_hs.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> this should come before previous patch, right ? Otherwise we will try to
> ioremap a resource which isn't passed down to driver. No ?

right. Will change the order in my next series.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:39:43 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:09:43 +0530
Subject: [PATCH v6 05/11] drivers: usb: twl6030: Add dt support for
 twl6030 usb
In-Reply-To: <20120803133122.GG8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-6-git-send-email-kishon@ti.com>
 <20120803133122.GG8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6JVcyiugeLtsK_15jTf5c7edCjAUZ=N1hoJJffpFr2_MQ@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 7:01 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:39:54PM +0530, Kishon Vijay Abraham I wrote:
>> Add device tree support for twl6030 usb driver.
>> Update the Documentation with device tree binding information.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> This looks great too. I can take this without any dependencies on the
> rest of the series, I believe. Right ??

I think it might not apply cleanly without [PATCH v6 03/11] drivers:
usb: otg: make twl6030_usb as a comparator driver to omap_usb2.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:40:38 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:10:38 +0530
Subject: [PATCH v6 07/11] drivers: usb: twl4030: Add device tree support
 for twl4030 usb
In-Reply-To: <20120803133214.GI8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-8-git-send-email-kishon@ti.com>
 <20120803133214.GI8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6+Vf-mWaPrLV=p3-WvF3xKTi202efj8RqPLy6eTeC1_UA@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 7:02 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:39:56PM +0530, Kishon Vijay Abraham I wrote:
>> Add device tree support for twl4030 usb driver.
>> Update the Documentation with device tree binding information.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> I think this also doesn't have dependency on the rest of the series and
> I could take this upstream. Right ?

right.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:41:12 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:11:12 +0530
Subject: [PATCH v6 11/11] arm: omap: phy: remove unused functions from
 omap-phy-internal.c
In-Reply-To: <20120803133602.GM8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-12-git-send-email-kishon@ti.com>
 <20120803133602.GM8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6+KC8kWD8BHpE20oYEfTS5JegRgU8sqrj4JWVLdOFxLrg@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 7:06 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:40:00PM +0530, Kishon Vijay Abraham I wrote:
>> All the unnessary functions in omap-phy-internal is removed.
>> These functionality are now handled by omap-usb2 phy driver.
>>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>> Acked-by: Tony Lindgren <tony at atomide.com>
>
> Great stuff. I'll take this when we agree on the omap-usb2 phy driver.

Sure.

Thanks
Kishon


From kishon at ti.com  Fri Aug  3 10:42:07 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 3 Aug 2012 20:12:07 +0530
Subject: [PATCH v6 09/11] drivers: usb: musb: Add device tree support for
 omap musb glue
In-Reply-To: <20120803133431.GK8269@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-10-git-send-email-kishon@ti.com>
 <20120803133431.GK8269@arwen.pp.htv.fi>
Message-ID: <CAAe_U6+fMyck-EyicDuwKx-HggMJFEbAHTO9+8PELgHNBL1nFA@mail.gmail.com>

Hi,

On Fri, Aug 3, 2012 at 7:04 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:39:58PM +0530, Kishon Vijay Abraham I wrote:
>> Added device tree support for omap musb driver and updated the
>> Documentation with device tree binding information.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
>
> This looks good and I think I can take this without any dependencies
> again. Correct ?

correct.

Thanks
Kishon


From shawn.guo at linaro.org  Fri Aug  3 10:43:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 3 Aug 2012 22:43:28 +0800
Subject: [PATCH] SPI: MXS: Allow to pass the SPI master bus number from
 the device tree
In-Reply-To: <1344004239-22868-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1344004239-22868-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120803144326.GE23791@S2101-09.ap.freescale.net>

On Fri, Aug 03, 2012 at 04:30:39PM +0200, Maxime Ripard wrote:
> If you don't do it, the bus number will be a bogus value, possibly used
> for device file names in drivers like spidev.
> 
Do you see any problem with that?  Here is the take from Grant.

http://thread.gmane.org/gmane.linux.kernel.spi.devel/9839/focus=9863

Regards,
Shawn



From arnd at arndb.de  Fri Aug  3 10:45:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 3 Aug 2012 14:45:09 +0000
Subject: [PATCH 4/5] arm: mvebu: add basic address decoding support to
 Armada 370/XP
In-Reply-To: <1344003237-13575-5-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344003237-13575-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1344003237-13575-5-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <201208031445.10102.arnd@arndb.de>

On Friday 03 August 2012, Thomas Petazzoni wrote:
> +static void __iomem *
> +armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
> +{
> +       unsigned int offset;
> +
> +       /* The register layout is a bit annoying and the below code
> +        * tries to cope with it.
> +        * - At offset 0x0, there are the registers for the first 8
> +        *   windows, with 4 registers of 32 bits per window (ctrl,
> +        *   base, remap low, remap high)
> +        * - Then at offset 0x80, there is a hole of 0x10 bytes for
> +        *   the internal registers base address and internal units
> +        *   sync barrier register.
> +        * - Then at offset 0x90, there the registers for 12
> +        *   windows, with only 2 registers of 32 bits per window
> +        *   (ctrl, base).
> +        */
> +       if (win < 8)
> +               offset = (win << 4);
> +       else
> +               offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
> +
> +       return (void __iomem *)(cfg->bridge_virt_base + offset);
> +}
> +

This cast can go away now that the type is already correct. Other
than that, the patch looks fine.

	Arnd


From u.kleine-koenig at pengutronix.de  Fri Aug  3 10:50:35 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 3 Aug 2012 16:50:35 +0200
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <201208031407.09092.arnd@arndb.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <201208031407.09092.arnd@arndb.de>
Message-ID: <20120803145035.GJ2626@pengutronix.de>

Hello,

On Fri, Aug 03, 2012 at 02:07:08PM +0000, Arnd Bergmann wrote:
> On Friday 03 August 2012, Uwe Kleine-K?nig wrote:
> > Hello,
> > 
> > the only changes compared to v5 (sent starting with Message-id:
> > 1341512035-8173-1-git-send-email-u.kleine-koenig at pengutronix.de)
> > are that several debug pr_infos were dropped that I missed to remove
> > before. Thanks to Will Deacon for pointing out that problem.
> > Furthermore I rebased (trivially) to v3.5.
> 
> No objections to the code from my side, but I'd like to understand
> the big picture here. You introduce a new CPU_V7M configuration
> symbol in the code, but there is no Kconfig change that introduces
> that symbol. Is that another change that is still coming?
I need to rework irq support which is up to now a seperate driver (nvic)
but it should be possible to integrate it into the gic driver. With this
patch I intend to send the Kconfig and Makefile stuff to make the code
actually do something.

> None of the code seems to be specific to Cortex-M3 rather than the
> ARMv7M architecture. Does that mean it is expected to run
> unmodifed on both M3 and M4, and possibly future ARMv-7M cores?
I'd expect to have M4 working out of the box. But as I don't have an M4
I cannot tell for sure.
 
> Is it possible to build a NOMMU kernel that runs on both ARMv7-A
> amd ARMv7-M, in other words is ARMv7-M compatible with ARMv7-A
> (or ARMv7-R for that matter) if you don't use the MMU?
the instructions to enable and disable irqs are different, so we'd need
another indirection at least there. Also the whole exception model is
different. So I'd say it's too different to target for a common kernel
for the A, R and M profiles.
 
> How does this relate to the ARMv6-M (Cortex-M0/M0+/M1) support
> that has been floating around [1]? Can we support both in
> the same kernel? 
I don't know M0/M1 but from a quick look at the tree you pointed out I'd
say they look reasonably similar.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From b-cousson at ti.com  Fri Aug  3 10:56:49 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 3 Aug 2012 16:56:49 +0200
Subject: [PATCH] hwmon: tmp102: Add device tree support
In-Reply-To: <1343997350-676-1-git-send-email-sourav.poddar@ti.com>
References: <1343997350-676-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <501BE6B1.9000100@ti.com>

Hi Sourav,

On 08/03/2012 02:35 PM, Sourav Poddar wrote:
> update tmp102 temperature sensor to also use device tree.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  drivers/hwmon/tmp102.c |   14 +++++++++++++-
>  1 files changed, 13 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c
> index 0d466b9..a8a9060 100644
> --- a/drivers/hwmon/tmp102.c
> +++ b/drivers/hwmon/tmp102.c
> @@ -26,6 +26,7 @@
>  #include <linux/err.h>
>  #include <linux/mutex.h>
>  #include <linux/device.h>
> +#include <linux/of.h>
>  
>  #define	DRIVER_NAME "tmp102"
>  
> @@ -284,8 +285,19 @@ static const struct i2c_device_id tmp102_id[] = {
>  };
>  MODULE_DEVICE_TABLE(i2c, tmp102_id);
>  
> +#ifdef CONFIG_OF
> +static const struct of_device_id temperature_dt_match[] = {
> +	{ .compatible = "ti,tmp102" },

Are you sure this is needed for this device?

There is an automatic binding done for I2C devices in the of_i2c core
code. So in theory, DT will be able to bind to any I2C device using the
already existing table: MODULE_DEVICE_TABLE(i2c, tmp102_id).

So I think this patch should not be needed.

Regards,
Benoit



From wd at denx.de  Fri Aug  3 11:06:02 2012
From: wd at denx.de (Wolfgang Denk)
Date: Fri, 03 Aug 2012 17:06:02 +0200
Subject: MMAP_MIN_ADDR problem/question
In-Reply-To: <201208020939.50225.marek.vasut@gmail.com>
References: <201208020939.50225.marek.vasut@gmail.com>
Message-ID: <20120803150602.687DF203B3D@gemini.denx.de>

Dear Wolfram,

In message <201208020939.50225.marek.vasut at gmail.com> Marek Vasut wrote:
> 
> Me and a coleague of mine recently ran into the issue [1]. The problem is, that 
> I set mmap_min_addr to 65536, making it unable for "su - user" command to work, 
> it crashes with SIGKILL. I now at least see a solution (set it to 32768). Though 
> I don't understand why. Can someone please exaplain me why it has to be 32768 an 
> not more?
> 
> [1] http://ubuntu.5.n6.nabble.com/PATCH-DEFAULT-MMAP-MIN-ADDR-32768-for-arm-td1604723.html


It appears the problem was introduced with commit cde7c41 "ARM:
configs: add defconfig for mach-mxs" which sets the default for
CONFIG_DEFAULT_MMAP_MIN_ADDR for MXS systems to 64 k.

"security/Kconfig" has somewhat related documentation:

	config LSM_MMAP_MIN_ADDR
	...
		default 32768 if ARM
		default 65536
		...
		On arm and other archs it should not be higher than 32768.

The reason is that on ARM the text segment of applications gets mapped
to 32 k, which fails for non-root processes if MMAP_MIN_ADDR is higher.


Is there any specific reason why you set it to 64 k for MXS ?

Can you please check if non-root processes work for you with this
configuration?

Thanks.

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I used to be indecisive, now I'm not sure.


From g.liakhovetski at gmx.de  Fri Aug  3 11:09:15 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 3 Aug 2012 17:09:15 +0200 (CEST)
Subject: Vacations.
In-Reply-To: <CACKLOr1Q6_xVhaaoWiy-kf9hViTW98aSa6hd5M2z7ogL-uwNVQ@mail.gmail.com>
References: <CACKLOr1Q6_xVhaaoWiy-kf9hViTW98aSa6hd5M2z7ogL-uwNVQ@mail.gmail.com>
Message-ID: <Pine.LNX.4.64.1208031708200.5170@axis700.grange>

Hi Javier

On Fri, 3 Aug 2012, javier Martin wrote:

> Hi,
> I will be out of the office until August the 19th.
> 
> I just wanted to send a reminder of some patches that I have pending.
> 
> For Mauro 3.7:
> 
> [PULL] video_visstrim for 3.6
> [PATCH] media: i.MX27: Fix mx2_emmaprp mem2mem driver clocks.
> 
> For Guennadi:
> 
> [PATCH 1/4] i.MX27: Fix emma-prp and csi clocks.

As I mentioned several times, the above patch is not for me. Have a nice 
vacation.

Thanks
Guennadi

> [PATCH 2/4] media: mx2_camera: Mark i.MX25 support as BROKEN.
> [PATCH 3/4] Schedule removal of i.MX25 support in mx2_camera.c
> [PATCH v2] media: mx2_camera: Fix clock handling for i.MX27.
> 
> For Sascha:
> 
> [PATCH v2] Visstrim SM10: Use mo_version to decide board video mode.
> 
> Regards.
> -- 
> Javier Martin
> Vista Silicon S.L.
> CDTUC - FASE C - Oficina S-345
> Avda de los Castros s/n
> 39005- Santander. Cantabria. Spain
> +34 942 25 32 60
> www.vista-silicon.com
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From festevam at gmail.com  Fri Aug  3 11:10:28 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 12:10:28 -0300
Subject: [PATCH v2 1/2] hw_random: mxc-rnga: Adapt clocks to new i.mx
 clock framework
In-Reply-To: <20120731064053.GW30009@pengutronix.de>
References: <1343407672-27185-1-git-send-email-fabio.estevam@freescale.com>
 <20120731064053.GW30009@pengutronix.de>
Message-ID: <CAOMZO5BSi7sfK+4mjPUn9j89CssyGBJkLXY_0aDekA5SRrXD-w@mail.gmail.com>

Hi Herbert,

On Tue, Jul 31, 2012 at 3:40 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Fri, Jul 27, 2012 at 01:47:51PM -0300, Fabio Estevam wrote:
>> Adapt clocks to the new i.mx clock framework and fix the following warning:
>>
>> Cc: Theodore Ts'o <tytso at mit.edu>
>> Cc: Herbert Xu <herbert at gondor.apana.org.au>
>> Cc: <linux-kernel at vger.kernel.org>
>> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>
> Both:
>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Looks like git did not Cc'ed you in these patches.

Would it be OK to apply these two patches?

Thanks,

Fabio Estevam


From shiraz.hashim at st.com  Fri Aug  3 11:17:40 2012
From: shiraz.hashim at st.com (Shiraz Hashim)
Date: Fri, 3 Aug 2012 20:47:40 +0530
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <20120803145035.GJ2626@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <201208031407.09092.arnd@arndb.de>
 <20120803145035.GJ2626@pengutronix.de>
Message-ID: <20120803151740.GZ2005@localhost.localdomain>

Hi Uwe,

On Fri, Aug 03, 2012 at 10:50:35PM +0800, Uwe Kleine-K?nig wrote:
> On Fri, Aug 03, 2012 at 02:07:08PM +0000, Arnd Bergmann wrote:
> > Is it possible to build a NOMMU kernel that runs on both
> > ARMv7-A amd ARMv7-M, in other words is ARMv7-M compatible with
> > ARMv7-A (or ARMv7-R for that matter) if you don't use the MMU?
>
> the instructions to enable and disable irqs are different, so
> we'd need another indirection at least there. Also the whole
> exception model is different. So I'd say it's too different to
> target for a common kernel for the A, R and M profiles.

We are using standard Linux kernel (v3.3) with MMU disabled on
a Cortex R4 system.

--
regards
Shiraz


From marex at denx.de  Fri Aug  3 11:26:06 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:06 +0200
Subject: [PATCH 01/10] mmc: spi: Move SSP register definitions into separate
 file
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-2-git-send-email-marex@denx.de>

Move the definitions into separate file so separate SPI driver can be
implemented. The SSP controller in MXS can act both as a MMC host and
as a SPI host.

Based on previous attempt by:
Fabio Estevam <fabio.estevam at freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mmc/host/mxs-mmc.c  |   87 ++--------------------------------
 include/linux/spi/mxs-spi.h |  109 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+), 84 deletions(-)
 create mode 100644 include/linux/spi/mxs-spi.h

diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index a51f930..26c95dc 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -45,87 +45,10 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/stmp_device.h>
 #include <linux/mmc/mxs-mmc.h>
+#include <linux/spi/mxs-spi.h>
 
 #define DRIVER_NAME	"mxs-mmc"
 
-/* card detect polling timeout */
-#define MXS_MMC_DETECT_TIMEOUT			(HZ/2)
-
-#define ssp_is_old(host)	((host)->devid == IMX23_MMC)
-
-/* SSP registers */
-#define HW_SSP_CTRL0				0x000
-#define  BM_SSP_CTRL0_RUN			(1 << 29)
-#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
-#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
-#define  BM_SSP_CTRL0_READ			(1 << 25)
-#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
-#define  BP_SSP_CTRL0_BUS_WIDTH			(22)
-#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
-#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
-#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
-#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
-#define  BM_SSP_CTRL0_ENABLE			(1 << 16)
-#define  BP_SSP_CTRL0_XFER_COUNT		(0)
-#define  BM_SSP_CTRL0_XFER_COUNT		(0xffff)
-#define HW_SSP_CMD0				0x010
-#define  BM_SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
-#define  BM_SSP_CMD0_SLOW_CLKING_EN		(1 << 22)
-#define  BM_SSP_CMD0_CONT_CLKING_EN		(1 << 21)
-#define  BM_SSP_CMD0_APPEND_8CYC		(1 << 20)
-#define  BP_SSP_CMD0_BLOCK_SIZE			(16)
-#define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
-#define  BP_SSP_CMD0_BLOCK_COUNT		(8)
-#define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
-#define  BP_SSP_CMD0_CMD			(0)
-#define  BM_SSP_CMD0_CMD			(0xff)
-#define HW_SSP_CMD1				0x020
-#define HW_SSP_XFER_SIZE			0x030
-#define HW_SSP_BLOCK_SIZE			0x040
-#define  BP_SSP_BLOCK_SIZE_BLOCK_COUNT		(4)
-#define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
-#define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		(0)
-#define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		(0xf)
-#define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
-#define  BP_SSP_TIMING_TIMEOUT			(16)
-#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
-#define  BP_SSP_TIMING_CLOCK_DIVIDE		(8)
-#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
-#define  BP_SSP_TIMING_CLOCK_RATE		(0)
-#define  BM_SSP_TIMING_CLOCK_RATE		(0xff)
-#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
-#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
-#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
-#define  BM_SSP_CTRL1_RESP_ERR_IRQ		(1 << 29)
-#define  BM_SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
-#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
-#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	(1 << 26)
-#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
-#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	(1 << 24)
-#define  BM_SSP_CTRL1_DATA_CRC_IRQ		(1 << 23)
-#define  BM_SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
-#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
-#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN	(1 << 20)
-#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
-#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	(1 << 16)
-#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
-#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
-#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
-#define  BM_SSP_CTRL1_POLARITY			(1 << 9)
-#define  BP_SSP_CTRL1_WORD_LENGTH		(4)
-#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
-#define  BP_SSP_CTRL1_SSP_MODE			(0)
-#define  BM_SSP_CTRL1_SSP_MODE			(0xf)
-#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
-#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
-#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
-#define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
-#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
-#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
-#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
-
-#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)
-
 #define MXS_MMC_IRQ_BITS	(BM_SSP_CTRL1_SDIO_IRQ		| \
 				 BM_SSP_CTRL1_RESP_ERR_IRQ	| \
 				 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ	| \
@@ -135,12 +58,8 @@
 				 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ  | \
 				 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
 
-#define SSP_PIO_NUM	3
-
-enum mxs_mmc_id {
-	IMX23_MMC,
-	IMX28_MMC,
-};
+/* card detect polling timeout */
+#define MXS_MMC_DETECT_TIMEOUT			(HZ/2)
 
 struct mxs_mmc_host {
 	struct mmc_host			*mmc;
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
new file mode 100644
index 0000000..b7ccd57
--- /dev/null
+++ b/include/linux/spi/mxs-spi.h
@@ -0,0 +1,109 @@
+/*
+ * include/linux/spi/mxs-spi.h
+ *
+ * Freescale i.MX233/i.MX28 SPI controller register definition
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __LINUX_SPI_MXS_SPI_H__
+#define __LINUX_SPI_MXS_SPI_H__
+
+#define ssp_is_old(host)	((host)->devid == IMX23_MMC)
+
+/* SSP registers */
+#define HW_SSP_CTRL0				0x000
+#define  BM_SSP_CTRL0_RUN			(1 << 29)
+#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
+#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
+#define  BM_SSP_CTRL0_READ			(1 << 25)
+#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
+#define  BP_SSP_CTRL0_BUS_WIDTH			22
+#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
+#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
+#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
+#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
+#define  BM_SSP_CTRL0_ENABLE			(1 << 16)
+#define  BP_SSP_CTRL0_XFER_COUNT		0
+#define  BM_SSP_CTRL0_XFER_COUNT		0xffff
+#define HW_SSP_CMD0				0x010
+#define  BM_SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
+#define  BM_SSP_CMD0_SLOW_CLKING_EN		(1 << 22)
+#define  BM_SSP_CMD0_CONT_CLKING_EN		(1 << 21)
+#define  BM_SSP_CMD0_APPEND_8CYC		(1 << 20)
+#define  BP_SSP_CMD0_BLOCK_SIZE			16
+#define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
+#define  BP_SSP_CMD0_BLOCK_COUNT		8
+#define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
+#define  BP_SSP_CMD0_CMD			0
+#define  BM_SSP_CMD0_CMD			0xff
+#define HW_SSP_CMD1				0x020
+#define HW_SSP_XFER_SIZE			0x030
+#define HW_SSP_BLOCK_SIZE			0x040
+#define  BP_SSP_BLOCK_SIZE_BLOCK_COUNT		4
+#define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
+#define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		0
+#define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		0xf
+#define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
+#define  BP_SSP_TIMING_TIMEOUT			16
+#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
+#define  BP_SSP_TIMING_CLOCK_DIVIDE		8
+#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
+#define  BP_SSP_TIMING_CLOCK_RATE		0
+#define  BM_SSP_TIMING_CLOCK_RATE		0xff
+#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
+#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
+#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
+#define  BM_SSP_CTRL1_RESP_ERR_IRQ		(1 << 29)
+#define  BM_SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
+#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
+#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	(1 << 26)
+#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
+#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	(1 << 24)
+#define  BM_SSP_CTRL1_DATA_CRC_IRQ		(1 << 23)
+#define  BM_SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
+#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
+#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN	(1 << 20)
+#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
+#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	(1 << 16)
+#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
+#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
+#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
+#define  BM_SSP_CTRL1_POLARITY			(1 << 9)
+#define  BP_SSP_CTRL1_WORD_LENGTH		4
+#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
+#define  BP_SSP_CTRL1_SSP_MODE			0
+#define  BM_SSP_CTRL1_SSP_MODE			0xf
+#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
+#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
+#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
+#define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
+#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
+#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
+#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
+
+#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)
+
+#define SSP_PIO_NUM	3
+
+enum mxs_mmc_id {
+	IMX23_MMC,
+	IMX28_MMC,
+};
+
+#endif	/* __LINUX_SPI_MXS_SPI_H__ */
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:13 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:13 +0200
Subject: [PATCH 08/10 V2] spi: Add DMA support into SPI driver
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-9-git-send-email-marex@denx.de>

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/spi/spi-mxs.c |  231 +++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 216 insertions(+), 15 deletions(-)

V2: Fix freeing of DMA channel in .remove()

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 0f28afb..130a436 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -55,8 +55,12 @@
 
 #define SSP_TIMEOUT		1000	/* 1000 ms */
 
+#define SG_NUM			4
+#define SG_MAXLEN		0xff00
+
 struct mxs_spi {
 	struct mxs_ssp		ssp;
+	struct completion	c;
 };
 
 static int mxs_spi_setup_transfer(struct spi_device *dev,
@@ -194,6 +198,115 @@ static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
 	return 0;
 }
 
+static void mxs_ssp_dma_irq_callback(void *param)
+{
+	struct mxs_spi *spi = param;
+	complete(&spi->c);
+}
+
+static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
+{
+	struct mxs_ssp *ssp = dev_id;
+	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
+		__func__, __LINE__,
+		readl(ssp->base + HW_SSP_CTRL1(ssp)),
+		readl(ssp->base + HW_SSP_STATUS(ssp)));
+	return IRQ_HANDLED;
+}
+
+static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
+			    unsigned char *buf, int len,
+			    int *first, int *last, int write)
+{
+	struct mxs_ssp *ssp = &spi->ssp;
+	struct dma_async_tx_descriptor *desc;
+	struct scatterlist sg[SG_NUM];
+	int sg_count;
+	uint32_t pio = BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);
+	int ret;
+
+	if (len > SG_NUM * SG_MAXLEN) {
+		dev_err(ssp->dev, "Data chunk too big for DMA\n");
+		return -EINVAL;
+	}
+
+	init_completion(&spi->c);
+
+	if (*first)
+		pio |= BM_SSP_CTRL0_LOCK_CS;
+	if (*last)
+		pio |= BM_SSP_CTRL0_IGNORE_CRC;
+	if (!write)
+		pio |= BM_SSP_CTRL0_READ;
+
+	if (ssp->devid == IMX23_SSP)
+		pio |= len;
+	else
+		writel(len, ssp->base + HW_SSP_XFER_SIZE);
+
+	/* Queue the PIO register write transfer. */
+	desc = dmaengine_prep_slave_sg(ssp->dmach,
+			(struct scatterlist *)&pio,
+			1, DMA_TRANS_NONE, 0);
+	if (!desc) {
+		dev_err(ssp->dev,
+			"Failed to get PIO reg. write descriptor.\n");
+		return -EINVAL;
+	}
+
+	/* Queue the DMA data transfer. */
+	sg_init_table(sg, (len / SG_MAXLEN) + 1);
+	sg_count = 0;
+	while (len) {
+		sg_set_buf(&sg[sg_count++], buf, min(len, SG_MAXLEN));
+		len -= min(len, SG_MAXLEN);
+		buf += min(len, SG_MAXLEN);
+	}
+	dma_map_sg(ssp->dev, sg, sg_count,
+		write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+
+	desc = dmaengine_prep_slave_sg(ssp->dmach, sg, sg_count,
+			write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
+			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+	if (!desc) {
+		dev_err(ssp->dev,
+			"Failed to get DMA data write descriptor.\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/*
+	 * The last descriptor must have this callback,
+	 * to finish the DMA transaction.
+	 */
+	desc->callback = mxs_ssp_dma_irq_callback;
+	desc->callback_param = spi;
+
+	/* Start the transfer. */
+	dmaengine_submit(desc);
+	dma_async_issue_pending(ssp->dmach);
+
+	ret = wait_for_completion_timeout(&spi->c,
+				msecs_to_jiffies(SSP_TIMEOUT));
+
+	if (!ret) {
+		dev_err(ssp->dev, "DMA transfer timeout\n");
+		ret = -ETIMEDOUT;
+		goto err;
+	}
+
+	ret = 0;
+
+err:
+	for (--sg_count; sg_count >= 0; sg_count--) {
+		dma_unmap_sg(ssp->dev, &sg[sg_count], 1,
+			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+	}
+
+	return ret;
+}
+
 static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
 			    unsigned char *buf, int len,
 			    int *first, int *last, int write)
@@ -281,19 +394,49 @@ static int mxs_spi_transfer_one(struct spi_master *master,
 			first = 1;
 		if (&t->transfer_list == m->transfers.prev)
 			last = 1;
-		if (t->rx_buf && t->tx_buf) {
+		if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
 			dev_err(ssp->dev,
 				"Cannot send and receive simultaneously\n");
 			status = -EINVAL;
 			break;
 		}
 
-		if (t->tx_buf)
-			status = mxs_spi_txrx_pio(spi, cs, (void *)t->tx_buf,
-					     t->len, &first, &last, 1);
-		if (t->rx_buf)
-			status = mxs_spi_txrx_pio(spi, cs, t->rx_buf,
-					     t->len, &first, &last, 0);
+		/*
+		 * Small blocks can be transfered via PIO.
+		 * Measured by empiric means:
+		 *
+		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
+		 *
+		 * DMA only: 2.164808 seconds, 473.0KB/s
+		 * Combined: 1.676276 seconds, 610.9KB/s
+		 */
+		if (t->len <= 256) {
+			writel(BM_SSP_CTRL1_DMA_ENABLE,
+				ssp->base + HW_SSP_CTRL1(ssp) +
+				STMP_OFFSET_REG_CLR);
+
+			if (t->tx_buf)
+				status = mxs_spi_txrx_pio(spi, cs,
+						(void *)t->tx_buf,
+						t->len, &first, &last, 1);
+			if (t->rx_buf)
+				status = mxs_spi_txrx_pio(spi, cs,
+						t->rx_buf, t->len,
+						&first, &last, 0);
+		} else {
+			writel(BM_SSP_CTRL1_DMA_ENABLE,
+				ssp->base + HW_SSP_CTRL1(ssp) +
+				STMP_OFFSET_REG_SET);
+
+			if (t->tx_buf)
+				status = mxs_spi_txrx_dma(spi, cs,
+						(void *)t->tx_buf, t->len,
+						&first, &last, 1);
+			if (t->rx_buf)
+				status = mxs_spi_txrx_dma(spi, cs,
+						t->rx_buf, t->len,
+						&first, &last, 0);
+		}
 
 		m->actual_length += t->len;
 		if (status)
@@ -308,6 +451,21 @@ static int mxs_spi_transfer_one(struct spi_master *master,
 	return status;
 }
 
+static bool mxs_ssp_dma_filter(struct dma_chan *chan, void *param)
+{
+	struct mxs_ssp *ssp = param;
+
+	if (!mxs_dma_is_apbh(chan))
+		return false;
+
+	if (chan->chan_id != ssp->dma_channel)
+		return false;
+
+	chan->private = &ssp->dma_data;
+
+	return true;
+}
+
 static const struct of_device_id mxs_spi_dt_ids[] = {
 	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
 	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
@@ -323,15 +481,18 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	struct mxs_spi *spi;
 	struct mxs_ssp *ssp;
-	struct resource *iores;
+	struct resource *iores, *dmares;
 	struct pinctrl *pinctrl;
 	struct clk *clk;
 	void __iomem *base;
-	int devid;
-	int ret = 0;
+	int devid, dma_channel;
+	int ret = 0, irq_err, irq_dma;
+	dma_cap_mask_t mask;
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!iores)
+	irq_err = platform_get_irq(pdev, 0);
+	irq_dma = platform_get_irq(pdev, 1);
+	if (!iores || irq_err < 0 || irq_dma < 0)
 		return -EINVAL;
 
 	base = devm_request_and_ioremap(&pdev->dev, iores);
@@ -346,10 +507,26 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
-	if (np)
+	if (np) {
 		devid = (enum mxs_ssp_id) of_id->data;
-	else
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helpers get in.
+		 */
+		ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
+					   &dma_channel);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Failed to get DMA channel\n");
+			return -EINVAL;
+		}
+	} else {
+		dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+		if (!dmares)
+			return -EINVAL;
 		devid = pdev->id_entry->driver_data;
+		dma_channel = dmares->start;
+	}
 
 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 	if (!master)
@@ -368,8 +545,28 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ssp->clk = clk;
 	ssp->base = base;
 	ssp->devid = devid;
+	ssp->dma_channel = dma_channel;
+
+	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
+			       DRIVER_NAME, ssp);
+	if (ret)
+		goto out_master_free;
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+	ssp->dma_data.chan_irq = irq_dma;
+	ssp->dmach = dma_request_channel(mask, mxs_ssp_dma_filter, ssp);
+	if (!ssp->dmach) {
+		dev_err(ssp->dev, "Failed to request DMA\n");
+		goto out_master_free;
+	}
 
+	/*
+	 * Crank up the clock to 120MHz, this will be further divided onto a
+	 * proper speed.
+	 */
 	clk_prepare_enable(ssp->clk);
+	clk_set_rate(ssp->clk, 120 * 1000 * 1000);
 	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
 
 	stmp_reset_block(ssp->base);
@@ -379,14 +576,16 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ret = spi_register_master(master);
 	if (ret) {
 		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
-		goto out_master_free;
+		goto out_free_dma;
 	}
 
 	return 0;
 
-out_master_free:
+out_free_dma:
 	platform_set_drvdata(pdev, NULL);
+	dma_release_channel(ssp->dmach);
 	clk_disable_unprepare(ssp->clk);
+out_master_free:
 	spi_master_put(master);
 	return ret;
 }
@@ -405,6 +604,8 @@ static int __devexit mxs_spi_remove(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, NULL);
 
+	dma_release_channel(ssp->dmach);
+
 	clk_disable_unprepare(ssp->clk);
 
 	spi_master_put(master);
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:05 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:05 +0200
Subject: [PATCH 00/10 V3] MXS SPI driver
Message-ID: <1344007575-11448-1-git-send-email-marex@denx.de>

This patchset adds SPI master support for Freescale i.MX233/i.MX28.
This is rebased on top of next-20120713. Please consider applying,
bugs shall now be squashed during the previous two review rounds.

Marek Vasut (10):
  mmc: spi: Move SSP register definitions into separate file
  mmc: spi: Rename IMX2[38]_MMC to IMX2[38]_SSP
  mmc: spi: Add necessary bits into mxs-spi.h
  mmc: spi: Pull out parts shared between MMC and SPI
  mmc: spi: Pull out the SSP clock configuration function
  spi: Add SPI driver for mx233/mx28
  mmc: spi: Pull out common DMA parts from MXS MMC
  spi: Add DMA support into SPI driver
  spi: Add SSP/SPI device tree documentation
  ARM: mx28: Add SPI pinmux into imx28.dtsi

 Documentation/devicetree/bindings/spi/mxs-spi.txt |   18 +
 arch/arm/boot/dts/imx28.dtsi                      |   39 ++
 drivers/clk/mxs/Makefile                          |    2 +-
 drivers/clk/mxs/clk-ssp.c                         |   62 ++
 drivers/mmc/host/mxs-mmc.c                        |  325 ++++-------
 drivers/spi/Kconfig                               |    7 +
 drivers/spi/Makefile                              |    1 +
 drivers/spi/spi-mxs.c                             |  631 +++++++++++++++++++++
 include/linux/spi/mxs-spi.h                       |  150 +++++
 9 files changed, 1016 insertions(+), 219 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/mxs-spi.txt
 create mode 100644 drivers/clk/mxs/clk-ssp.c
 create mode 100644 drivers/spi/spi-mxs.c
 create mode 100644 include/linux/spi/mxs-spi.h

Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:07 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:07 +0200
Subject: [PATCH 02/10] mmc: spi: Rename IMX2[38]_MMC to IMX2[38]_SSP
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-3-git-send-email-marex@denx.de>

Since the SSP controller can act as both SPI and MMC host,
renaming the enum to properly reflect the naming seems
appropriate.

Based on previous attempt by:
Fabio Estevam <fabio.estevam at freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mmc/host/mxs-mmc.c  |   18 +++++++++---------
 include/linux/spi/mxs-spi.h |    8 ++++----
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index 26c95dc..e80c2b6 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -78,7 +78,7 @@ struct mxs_mmc_host {
 	enum dma_transfer_direction	slave_dirn;
 	u32				ssp_pio_words[SSP_PIO_NUM];
 
-	enum mxs_mmc_id			devid;
+	enum mxs_ssp_id			devid;
 	unsigned char			bus_width;
 	spinlock_t			lock;
 	int				sdio_irq_en;
@@ -601,22 +601,22 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
 	return true;
 }
 
-static struct platform_device_id mxs_mmc_ids[] = {
+static struct platform_device_id mxs_ssp_ids[] = {
 	{
 		.name = "imx23-mmc",
-		.driver_data = IMX23_MMC,
+		.driver_data = IMX23_SSP,
 	}, {
 		.name = "imx28-mmc",
-		.driver_data = IMX28_MMC,
+		.driver_data = IMX28_SSP,
 	}, {
 		/* sentinel */
 	}
 };
-MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
+MODULE_DEVICE_TABLE(platform, mxs_ssp_ids);
 
 static const struct of_device_id mxs_mmc_dt_ids[] = {
-	{ .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, },
-	{ .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, },
+	{ .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
+	{ .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
@@ -655,7 +655,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	}
 
 	if (np) {
-		host->devid = (enum mxs_mmc_id) of_id->data;
+		host->devid = (enum mxs_ssp_id) of_id->data;
 		/*
 		 * TODO: This is a temporary solution and should be changed
 		 * to use generic DMA binding later when the helpers get in.
@@ -829,7 +829,7 @@ static const struct dev_pm_ops mxs_mmc_pm_ops = {
 static struct platform_driver mxs_mmc_driver = {
 	.probe		= mxs_mmc_probe,
 	.remove		= mxs_mmc_remove,
-	.id_table	= mxs_mmc_ids,
+	.id_table	= mxs_ssp_ids,
 	.driver		= {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index b7ccd57..c08aef5 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -24,7 +24,7 @@
 #ifndef __LINUX_SPI_MXS_SPI_H__
 #define __LINUX_SPI_MXS_SPI_H__
 
-#define ssp_is_old(host)	((host)->devid == IMX23_MMC)
+#define ssp_is_old(host)	((host)->devid == IMX23_SSP)
 
 /* SSP registers */
 #define HW_SSP_CTRL0				0x000
@@ -101,9 +101,9 @@
 
 #define SSP_PIO_NUM	3
 
-enum mxs_mmc_id {
-	IMX23_MMC,
-	IMX28_MMC,
+enum mxs_ssp_id {
+	IMX23_SSP,
+	IMX28_SSP,
 };
 
 #endif	/* __LINUX_SPI_MXS_SPI_H__ */
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:08 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:08 +0200
Subject: [PATCH 03/10] mmc: spi: Add necessary bits into mxs-spi.h
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-4-git-send-email-marex@denx.de>

Add missing register bits and registers into mxs-spi.h .
These will be used by the SPI driver.

Based on previous attempt by:
Fabio Estevam <fabio.estevam at freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 include/linux/spi/mxs-spi.h |   22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index c08aef5..7dfa1d7 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -30,12 +30,14 @@
 #define HW_SSP_CTRL0				0x000
 #define  BM_SSP_CTRL0_RUN			(1 << 29)
 #define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
+#define  BM_SSP_CTRL0_LOCK_CS			(1 << 27)
 #define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
 #define  BM_SSP_CTRL0_READ			(1 << 25)
 #define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
 #define  BP_SSP_CTRL0_BUS_WIDTH			22
 #define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
 #define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
+#define  BM_SSP_CTRL0_WAIT_FOR_CMD		(1 << 20)
 #define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
 #define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
 #define  BM_SSP_CTRL0_ENABLE			(1 << 16)
@@ -64,8 +66,12 @@
 #define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
 #define  BP_SSP_TIMING_CLOCK_DIVIDE		8
 #define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
+#define  BF_SSP_TIMING_CLOCK_DIVIDE(v)		\
+			(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
 #define  BP_SSP_TIMING_CLOCK_RATE		0
 #define  BM_SSP_TIMING_CLOCK_RATE		0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)		\
+			(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
 #define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
 #define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
 #define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
@@ -84,11 +90,26 @@
 #define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
 #define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
 #define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
+#define  BM_SSP_CTRL1_PHASE			(1 << 10)
 #define  BM_SSP_CTRL1_POLARITY			(1 << 9)
 #define  BP_SSP_CTRL1_WORD_LENGTH		4
 #define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
+#define  BF_SSP_CTRL1_WORD_LENGTH(v)		\
+			(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
+#define  BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS	0x3
+#define  BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS	0x7
+#define  BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS	0xF
 #define  BP_SSP_CTRL1_SSP_MODE			0
 #define  BM_SSP_CTRL1_SSP_MODE			0xf
+#define  BF_SSP_CTRL1_SSP_MODE(v)		\
+			(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
+#define  BV_SSP_CTRL1_SSP_MODE__SPI		0x0
+#define  BV_SSP_CTRL1_SSP_MODE__SSI		0x1
+#define  BV_SSP_CTRL1_SSP_MODE__SD_MMC		0x3
+#define  BV_SSP_CTRL1_SSP_MODE__MS		0x4
+
+#define HW_SSP_DATA(h)				(ssp_is_old(h) ? 0x070 : 0x090)
+
 #define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
 #define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
 #define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
@@ -96,6 +117,7 @@
 #define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
 #define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
 #define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
+#define  BM_SSP_STATUS_FIFO_EMPTY		(1 << 5)
 
 #define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)
 
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:11 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:11 +0200
Subject: [PATCH 06/10 V3] spi: Add SPI driver for mx233/mx28
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-7-git-send-email-marex@denx.de>

This is slightly reworked version of the SPI driver.
Support for DT has been added and it's been converted
to queued API.

Based on previous attempt by:
Fabio Estevam <fabio.estevam at freescale.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/spi/Kconfig   |    7 +
 drivers/spi/Makefile  |    1 +
 drivers/spi/spi-mxs.c |  431 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 439 insertions(+)
 create mode 100644 drivers/spi/spi-mxs.c

V3: Drop mxs_spi_cleanup()
    Set "hz" unconditionally to dev->max_speed_hz and then trim it down.
    Add comment about how Freescale is recycling random bits in CTRL0 register.

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b55..6992b30 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -364,6 +364,13 @@ config SPI_STMP3XXX
 	help
 	  SPI driver for Freescale STMP37xx/378x SoC SSP interface
 
+config SPI_MXS
+	tristate "Freescale MXS SPI controller"
+	depends on ARCH_MXS
+	select STMP_DEVICE
+	help
+	  SPI driver for Freescale MXS devices.
+
 config SPI_TEGRA
 	tristate "Nvidia Tegra SPI controller"
 	depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3920dcf..3b72d87 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SPI_LM70_LLP)		+= spi-lm70llp.o
 obj-$(CONFIG_SPI_MPC512x_PSC)		+= spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)		+= spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52xx.o
+obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
 obj-$(CONFIG_SPI_OMAP_UWIRE)		+= spi-omap-uwire.o
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
new file mode 100644
index 0000000..7bf826f
--- /dev/null
+++ b/drivers/spi/spi-mxs.c
@@ -0,0 +1,431 @@
+/*
+ * Freescale MXS SPI master driver
+ *
+ * Copyright 2012 DENX Software Engineering, GmbH.
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * Rework and transition to new API by:
+ * Marek Vasut <marex at denx.de>
+ *
+ * Based on previous attempt by:
+ * Fabio Estevam <fabio.estevam at freescale.com>
+ *
+ * Based on code from U-Boot bootloader by:
+ * Marek Vasut <marex at denx.de>
+ *
+ * Based on spi-stmp.c, which is:
+ * Author: Dmitry Pervushin <dimka at embeddedalley.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/highmem.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/module.h>
+#include <linux/fsl/mxs-dma.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/stmp_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/mxs-spi.h>
+
+#define DRIVER_NAME		"mxs-spi"
+
+#define SSP_TIMEOUT		1000	/* 1000 ms */
+
+struct mxs_spi {
+	struct mxs_ssp		ssp;
+};
+
+static int mxs_spi_setup_transfer(struct spi_device *dev,
+				struct spi_transfer *t)
+{
+	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
+	struct mxs_ssp *ssp = &spi->ssp;
+	uint8_t bits_per_word;
+	uint32_t hz = 0;
+
+	bits_per_word = dev->bits_per_word;
+	if (t && t->bits_per_word)
+		bits_per_word = t->bits_per_word;
+
+	if (bits_per_word != 8) {
+		dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
+					__func__, bits_per_word);
+		return -EINVAL;
+	}
+
+	hz = dev->max_speed_hz;
+	if (t && t->speed_hz)
+		hz = min(hz, t->speed_hz);
+	if (hz == 0) {
+		dev_err(&dev->dev, "Cannot continue with zero clock\n");
+		return -EINVAL;
+	}
+
+	mxs_ssp_set_clk_rate(ssp, hz);
+
+	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
+		     BF_SSP_CTRL1_WORD_LENGTH
+		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
+		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
+		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
+		     ssp->base + HW_SSP_CTRL1(ssp));
+
+	writel(0x0, ssp->base + HW_SSP_CMD0);
+	writel(0x0, ssp->base + HW_SSP_CMD1);
+
+	return 0;
+}
+
+static int mxs_spi_setup(struct spi_device *dev)
+{
+	int err = 0;
+
+	if (!dev->bits_per_word)
+		dev->bits_per_word = 8;
+
+	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
+		return -EINVAL;
+
+	err = mxs_spi_setup_transfer(dev, NULL);
+	if (err) {
+		dev_err(&dev->dev,
+			"Failed to setup transfer, error = %d\n", err);
+	}
+
+	return err;
+}
+
+static uint32_t mxs_spi_cs_to_reg(unsigned cs)
+{
+	uint32_t select = 0;
+
+	/*
+	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
+	 *
+	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
+	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
+	 * the datasheet for further details. In SPI mode, they are used to
+	 * toggle the chip-select lines (nCS pins).
+	 */
+	if (cs & 1)
+		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
+	if (cs & 2)
+		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
+
+	return select;
+}
+
+static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
+{
+	const uint32_t mask =
+		BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
+	uint32_t select;
+	struct mxs_ssp *ssp = &spi->ssp;
+
+	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+	select = mxs_spi_cs_to_reg(cs);
+	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+}
+
+static inline void mxs_spi_enable(struct mxs_spi *spi)
+{
+	struct mxs_ssp *ssp = &spi->ssp;
+
+	writel(BM_SSP_CTRL0_LOCK_CS,
+		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+	writel(BM_SSP_CTRL0_IGNORE_CRC,
+		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+}
+
+static inline void mxs_spi_disable(struct mxs_spi *spi)
+{
+	struct mxs_ssp *ssp = &spi->ssp;
+
+	writel(BM_SSP_CTRL0_LOCK_CS,
+		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+	writel(BM_SSP_CTRL0_IGNORE_CRC,
+		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+}
+
+static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
+	struct mxs_ssp *ssp = &spi->ssp;
+	uint32_t reg;
+
+	while (1) {
+		reg = readl_relaxed(ssp->base + offset);
+
+		if (set && ((reg & mask) == mask))
+			break;
+
+		if (!set && ((~reg & mask) == mask))
+			break;
+
+		udelay(1);
+
+		if (time_after(jiffies, timeout))
+			return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
+			    unsigned char *buf, int len,
+			    int *first, int *last, int write)
+{
+	struct mxs_ssp *ssp = &spi->ssp;
+
+	if (*first)
+		mxs_spi_enable(spi);
+
+	mxs_spi_set_cs(spi, cs);
+
+	while (len--) {
+		if (*last && len == 0)
+			mxs_spi_disable(spi);
+
+		if (ssp->devid == IMX23_SSP) {
+			writel(BM_SSP_CTRL0_XFER_COUNT,
+				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+			writel(1,
+				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+		} else {
+			writel(1, ssp->base + HW_SSP_XFER_SIZE);
+		}
+
+		if (write)
+			writel(BM_SSP_CTRL0_READ,
+				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+		else
+			writel(BM_SSP_CTRL0_READ,
+				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+
+		writel(BM_SSP_CTRL0_RUN,
+				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+
+		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
+			return -ETIMEDOUT;
+
+		if (write)
+			writel(*buf, ssp->base + HW_SSP_DATA(ssp));
+
+		writel(BM_SSP_CTRL0_DATA_XFER,
+			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+
+		if (!write) {
+			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
+						BM_SSP_STATUS_FIFO_EMPTY, 0))
+				return -ETIMEDOUT;
+
+			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
+		}
+
+		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
+			return -ETIMEDOUT;
+
+		buf++;
+	}
+
+	if (len <= 0)
+		return 0;
+
+	return -ETIMEDOUT;
+}
+
+static int mxs_spi_transfer_one(struct spi_master *master,
+				struct spi_message *m)
+{
+	struct mxs_spi *spi = spi_master_get_devdata(master);
+	struct mxs_ssp *ssp = &spi->ssp;
+	int first, last;
+	struct spi_transfer *t, *tmp_t;
+	int status = 0;
+	int cs;
+
+	first = last = 0;
+
+	cs = m->spi->chip_select;
+
+	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
+
+		status = mxs_spi_setup_transfer(m->spi, t);
+		if (status)
+			break;
+
+		if (&t->transfer_list == m->transfers.next)
+			first = 1;
+		if (&t->transfer_list == m->transfers.prev)
+			last = 1;
+		if (t->rx_buf && t->tx_buf) {
+			dev_err(ssp->dev,
+				"Cannot send and receive simultaneously\n");
+			status = -EINVAL;
+			break;
+		}
+
+		if (t->tx_buf)
+			status = mxs_spi_txrx_pio(spi, cs, (void *)t->tx_buf,
+					     t->len, &first, &last, 1);
+		if (t->rx_buf)
+			status = mxs_spi_txrx_pio(spi, cs, t->rx_buf,
+					     t->len, &first, &last, 0);
+
+		m->actual_length += t->len;
+		if (status)
+			break;
+
+		first = last = 0;
+	}
+
+	m->status = 0;
+	spi_finalize_current_message(master);
+
+	return status;
+}
+
+static const struct of_device_id mxs_spi_dt_ids[] = {
+	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
+	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
+
+static int __devinit mxs_spi_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id =
+			of_match_device(mxs_spi_dt_ids, &pdev->dev);
+	struct device_node *np = pdev->dev.of_node;
+	struct spi_master *master;
+	struct mxs_spi *spi;
+	struct mxs_ssp *ssp;
+	struct resource *iores;
+	struct pinctrl *pinctrl;
+	struct clk *clk;
+	void __iomem *base;
+	int devid;
+	int ret = 0;
+
+	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!iores)
+		return -EINVAL;
+
+	base = devm_request_and_ioremap(&pdev->dev, iores);
+	if (!base)
+		return -EADDRNOTAVAIL;
+
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl))
+		return PTR_ERR(pinctrl);
+
+	clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	if (np)
+		devid = (enum mxs_ssp_id) of_id->data;
+	else
+		devid = pdev->id_entry->driver_data;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
+	if (!master)
+		return -ENOMEM;
+
+	master->transfer_one_message = mxs_spi_transfer_one;
+	master->setup = mxs_spi_setup;
+	master->mode_bits = SPI_CPOL | SPI_CPHA;
+	master->num_chipselect = 3;
+	master->dev.of_node = np;
+	master->flags = SPI_MASTER_HALF_DUPLEX;
+
+	spi = spi_master_get_devdata(master);
+	ssp = &spi->ssp;
+	ssp->dev = &pdev->dev;
+	ssp->clk = clk;
+	ssp->base = base;
+	ssp->devid = devid;
+
+	clk_prepare_enable(ssp->clk);
+	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
+
+	stmp_reset_block(ssp->base);
+
+	platform_set_drvdata(pdev, master);
+
+	ret = spi_register_master(master);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
+		goto out_master_free;
+	}
+
+	return 0;
+
+out_master_free:
+	platform_set_drvdata(pdev, NULL);
+	clk_disable_unprepare(ssp->clk);
+	spi_master_put(master);
+	return ret;
+}
+
+static int __devexit mxs_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master;
+	struct mxs_spi *spi;
+	struct mxs_ssp *ssp;
+
+	master = platform_get_drvdata(pdev);
+	spi = spi_master_get_devdata(master);
+	ssp = &spi->ssp;
+
+	spi_unregister_master(master);
+
+	platform_set_drvdata(pdev, NULL);
+
+	clk_disable_unprepare(ssp->clk);
+
+	spi_master_put(master);
+
+	return 0;
+}
+
+static struct platform_driver mxs_spi_driver = {
+	.probe	= mxs_spi_probe,
+	.remove	= __devexit_p(mxs_spi_remove),
+	.driver	= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = mxs_spi_dt_ids,
+	},
+};
+
+module_platform_driver(mxs_spi_driver);
+
+MODULE_AUTHOR("Marek Vasut <marex at denx.de>");
+MODULE_DESCRIPTION("MXS SPI master driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:mxs-spi");
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:10 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:10 +0200
Subject: [PATCH 05/10] mmc: spi: Pull out the SSP clock configuration function
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-6-git-send-email-marex@denx.de>

Pull out the MMC clock configuration function and make it
into SSP clock configuration function, so it can be used by
the SPI driver too.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/mxs/Makefile    |    2 +-
 drivers/clk/mxs/clk-ssp.c   |   62 +++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mxs-mmc.c  |   39 +--------------------------
 include/linux/spi/mxs-spi.h |    2 ++
 4 files changed, 66 insertions(+), 39 deletions(-)
 create mode 100644 drivers/clk/mxs/clk-ssp.c

diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
index 7bedeec..a6a2223 100644
--- a/drivers/clk/mxs/Makefile
+++ b/drivers/clk/mxs/Makefile
@@ -2,7 +2,7 @@
 # Makefile for mxs specific clk
 #
 
-obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o
+obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
 
 obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
 obj-$(CONFIG_SOC_IMX28) += clk-imx28.o
diff --git a/drivers/clk/mxs/clk-ssp.c b/drivers/clk/mxs/clk-ssp.c
new file mode 100644
index 0000000..af7bdbf
--- /dev/null
+++ b/drivers/clk/mxs/clk-ssp.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2012 DENX Software Engineering, GmbH
+ *
+ * Pulled from code:
+ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
+ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/spi/mxs-spi.h>
+
+void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
+{
+	unsigned int ssp_clk, ssp_sck;
+	u32 clock_divide, clock_rate;
+	u32 val;
+
+	ssp_clk = clk_get_rate(ssp->clk);
+
+	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
+		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
+		clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
+		if (clock_rate <= 255)
+			break;
+	}
+
+	if (clock_divide > 254) {
+		dev_err(ssp->dev,
+			"%s: cannot set clock to %d\n", __func__, rate);
+		return;
+	}
+
+	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
+
+	val = readl(ssp->base + HW_SSP_TIMING(ssp));
+	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
+	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
+	val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
+	writel(val, ssp->base + HW_SSP_TIMING(ssp));
+
+	ssp->clk_rate = ssp_sck;
+
+	dev_dbg(ssp->dev,
+		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
+		__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
+}
+EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index 7b85e03..0813340 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -501,43 +501,6 @@ static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 	mxs_mmc_start_cmd(host, mrq->cmd);
 }
 
-static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
-{
-	struct mxs_ssp *ssp = &host->ssp;
-	unsigned int ssp_clk, ssp_sck;
-	u32 clock_divide, clock_rate;
-	u32 val;
-
-	ssp_clk = clk_get_rate(ssp->clk);
-
-	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
-		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
-		clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
-		if (clock_rate <= 255)
-			break;
-	}
-
-	if (clock_divide > 254) {
-		dev_err(mmc_dev(host->mmc),
-			"%s: cannot set clock to %d\n", __func__, rate);
-		return;
-	}
-
-	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
-
-	val = readl(ssp->base + HW_SSP_TIMING(ssp));
-	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
-	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
-	val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
-	writel(val, ssp->base + HW_SSP_TIMING(ssp));
-
-	ssp->clk_rate = ssp_sck;
-
-	dev_dbg(mmc_dev(host->mmc),
-		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
-		__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
-}
-
 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
@@ -550,7 +513,7 @@ static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		host->bus_width = 0;
 
 	if (ios->clock)
-		mxs_mmc_set_clk_rate(host, ios->clock);
+		mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
 }
 
 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index 475f69f..d07f8dc 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -136,4 +136,6 @@ struct mxs_ssp {
 	enum mxs_ssp_id			devid;
 };
 
+void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
+
 #endif	/* __LINUX_SPI_MXS_SPI_H__ */
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:09 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:09 +0200
Subject: [PATCH 04/10] mmc: spi: Pull out parts shared between MMC and SPI
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-5-git-send-email-marex@denx.de>

Abstract out the common part of private data shared between MMC
and SPI. These shall later allow to use common clock configuration
function.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mmc/host/mxs-mmc.c  |  107 ++++++++++++++++++++++++-------------------
 include/linux/spi/mxs-spi.h |    8 ++++
 2 files changed, 67 insertions(+), 48 deletions(-)

diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index e80c2b6..7b85e03 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -62,23 +62,20 @@
 #define MXS_MMC_DETECT_TIMEOUT			(HZ/2)
 
 struct mxs_mmc_host {
+	struct mxs_ssp			ssp;
+
 	struct mmc_host			*mmc;
 	struct mmc_request		*mrq;
 	struct mmc_command		*cmd;
 	struct mmc_data			*data;
 
-	void __iomem			*base;
 	int				dma_channel;
-	struct clk			*clk;
-	unsigned int			clk_rate;
-
 	struct dma_chan         	*dmach;
 	struct mxs_dma_data		dma_data;
 	unsigned int			dma_dir;
 	enum dma_transfer_direction	slave_dirn;
 	u32				ssp_pio_words[SSP_PIO_NUM];
 
-	enum mxs_ssp_id			devid;
 	unsigned char			bus_width;
 	spinlock_t			lock;
 	int				sdio_irq_en;
@@ -105,16 +102,18 @@ static int mxs_mmc_get_ro(struct mmc_host *mmc)
 static int mxs_mmc_get_cd(struct mmc_host *mmc)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_ssp *ssp = &host->ssp;
 
-	return !(readl(host->base + HW_SSP_STATUS(host)) &
+	return !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
 		 BM_SSP_STATUS_CARD_DETECT);
 }
 
 static void mxs_mmc_reset(struct mxs_mmc_host *host)
 {
+	struct mxs_ssp *ssp = &host->ssp;
 	u32 ctrl0, ctrl1;
 
-	stmp_reset_block(host->base);
+	stmp_reset_block(ssp->base);
 
 	ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
 	ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
@@ -130,15 +129,15 @@ static void mxs_mmc_reset(struct mxs_mmc_host *host)
 	writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
 	       BF_SSP(2, TIMING_CLOCK_DIVIDE) |
 	       BF_SSP(0, TIMING_CLOCK_RATE),
-	       host->base + HW_SSP_TIMING(host));
+	       ssp->base + HW_SSP_TIMING(ssp));
 
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
 	}
 
-	writel(ctrl0, host->base + HW_SSP_CTRL0);
-	writel(ctrl1, host->base + HW_SSP_CTRL1(host));
+	writel(ctrl0, ssp->base + HW_SSP_CTRL0);
+	writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
 }
 
 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
@@ -149,15 +148,16 @@ static void mxs_mmc_request_done(struct mxs_mmc_host *host)
 	struct mmc_command *cmd = host->cmd;
 	struct mmc_data *data = host->data;
 	struct mmc_request *mrq = host->mrq;
+	struct mxs_ssp *ssp = &host->ssp;
 
 	if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
 		if (mmc_resp_type(cmd) & MMC_RSP_136) {
-			cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
-			cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
-			cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
-			cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
+			cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
+			cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
+			cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
+			cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
 		} else {
-			cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
+			cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
 		}
 	}
 
@@ -196,13 +196,14 @@ static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
 	struct mxs_mmc_host *host = dev_id;
 	struct mmc_command *cmd = host->cmd;
 	struct mmc_data *data = host->data;
+	struct mxs_ssp *ssp = &host->ssp;
 	u32 stat;
 
 	spin_lock(&host->lock);
 
-	stat = readl(host->base + HW_SSP_CTRL1(host));
+	stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
 	writel(stat & MXS_MMC_IRQ_BITS,
-	       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
+	       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
 
 	if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
 		mmc_signal_sdio_irq(host->mmc);
@@ -366,6 +367,8 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 	unsigned int data_size = 0, log2_blksz;
 	unsigned int blocks = data->blocks;
 
+	struct mxs_ssp *ssp = &host->ssp;
+
 	u32 ignore_crc, get_resp, long_resp, read;
 	u32 ctrl0, cmd0, cmd1, val;
 
@@ -408,15 +411,15 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 		blocks = 1;
 
 	/* xfer count, block size and count need to be set differently */
-	if (ssp_is_old(host)) {
+	if (ssp_is_old(ssp)) {
 		ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
 		cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
 			BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
 	} else {
-		writel(data_size, host->base + HW_SSP_XFER_SIZE);
+		writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
 		writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
 		       BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
-		       host->base + HW_SSP_BLOCK_SIZE);
+		       ssp->base + HW_SSP_BLOCK_SIZE);
 	}
 
 	if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
@@ -431,11 +434,11 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 	}
 
 	/* set the timeout count */
-	timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
-	val = readl(host->base + HW_SSP_TIMING(host));
+	timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
+	val = readl(ssp->base + HW_SSP_TIMING(ssp));
 	val &= ~(BM_SSP_TIMING_TIMEOUT);
 	val |= BF_SSP(timeout, TIMING_TIMEOUT);
-	writel(val, host->base + HW_SSP_TIMING(host));
+	writel(val, ssp->base + HW_SSP_TIMING(ssp));
 
 	/* pio */
 	host->ssp_pio_words[0] = ctrl0;
@@ -500,11 +503,12 @@ static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 
 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
 {
+	struct mxs_ssp *ssp = &host->ssp;
 	unsigned int ssp_clk, ssp_sck;
 	u32 clock_divide, clock_rate;
 	u32 val;
 
-	ssp_clk = clk_get_rate(host->clk);
+	ssp_clk = clk_get_rate(ssp->clk);
 
 	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
 		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
@@ -521,13 +525,13 @@ static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
 
 	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
 
-	val = readl(host->base + HW_SSP_TIMING(host));
+	val = readl(ssp->base + HW_SSP_TIMING(ssp));
 	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
 	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
 	val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
-	writel(val, host->base + HW_SSP_TIMING(host));
+	writel(val, ssp->base + HW_SSP_TIMING(ssp));
 
-	host->clk_rate = ssp_sck;
+	ssp->clk_rate = ssp_sck;
 
 	dev_dbg(mmc_dev(host->mmc),
 		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
@@ -552,6 +556,7 @@ static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_ssp *ssp = &host->ssp;
 	unsigned long flags;
 
 	spin_lock_irqsave(&host->lock, flags);
@@ -560,19 +565,19 @@ static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 
 	if (enable) {
 		writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
-		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
+		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 		writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
-		       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
+		       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
 
-		if (readl(host->base + HW_SSP_STATUS(host)) &
+		if (readl(ssp->base + HW_SSP_STATUS(ssp)) &
 				BM_SSP_STATUS_SDIO_IRQ)
 			mmc_signal_sdio_irq(host->mmc);
 
 	} else {
 		writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
-		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
+		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 		writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
-		       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
+		       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
 	}
 
 	spin_unlock_irqrestore(&host->lock, flags);
@@ -635,6 +640,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	dma_cap_mask_t mask;
 	struct regulator *reg_vmmc;
 	enum of_gpio_flags flags;
+	struct mxs_ssp *ssp;
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
@@ -648,14 +654,16 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	host = mmc_priv(mmc);
-	host->base = devm_request_and_ioremap(&pdev->dev, iores);
-	if (!host->base) {
+	ssp = &host->ssp;
+	ssp->dev = &pdev->dev;
+	ssp->base = devm_request_and_ioremap(&pdev->dev, iores);
+	if (!ssp->base) {
 		ret = -EADDRNOTAVAIL;
 		goto out_mmc_free;
 	}
 
 	if (np) {
-		host->devid = (enum mxs_ssp_id) of_id->data;
+		ssp->devid = (enum mxs_ssp_id) of_id->data;
 		/*
 		 * TODO: This is a temporary solution and should be changed
 		 * to use generic DMA binding later when the helpers get in.
@@ -668,7 +676,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 			goto out_mmc_free;
 		}
 	} else {
-		host->devid = pdev->id_entry->driver_data;
+		ssp->devid = pdev->id_entry->driver_data;
 		host->dma_channel = dmares->start;
 	}
 
@@ -691,12 +699,12 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 		goto out_mmc_free;
 	}
 
-	host->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(host->clk)) {
-		ret = PTR_ERR(host->clk);
+	ssp->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(ssp->clk)) {
+		ret = PTR_ERR(ssp->clk);
 		goto out_mmc_free;
 	}
-	clk_prepare_enable(host->clk);
+	clk_prepare_enable(ssp->clk);
 
 	mxs_mmc_reset(host);
 
@@ -741,8 +749,8 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 
 	mmc->max_segs = 52;
 	mmc->max_blk_size = 1 << 0xf;
-	mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
-	mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
+	mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
+	mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
 	mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
 
 	platform_set_drvdata(pdev, mmc);
@@ -766,8 +774,8 @@ out_free_dma:
 	if (host->dmach)
 		dma_release_channel(host->dmach);
 out_clk_put:
-	clk_disable_unprepare(host->clk);
-	clk_put(host->clk);
+	clk_disable_unprepare(ssp->clk);
+	clk_put(ssp->clk);
 out_mmc_free:
 	mmc_free_host(mmc);
 	return ret;
@@ -777,6 +785,7 @@ static int mxs_mmc_remove(struct platform_device *pdev)
 {
 	struct mmc_host *mmc = platform_get_drvdata(pdev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_ssp *ssp = &host->ssp;
 
 	mmc_remove_host(mmc);
 
@@ -785,8 +794,8 @@ static int mxs_mmc_remove(struct platform_device *pdev)
 	if (host->dmach)
 		dma_release_channel(host->dmach);
 
-	clk_disable_unprepare(host->clk);
-	clk_put(host->clk);
+	clk_disable_unprepare(ssp->clk);
+	clk_put(ssp->clk);
 
 	mmc_free_host(mmc);
 
@@ -798,11 +807,12 @@ static int mxs_mmc_suspend(struct device *dev)
 {
 	struct mmc_host *mmc = dev_get_drvdata(dev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_ssp *ssp = &host->ssp;
 	int ret = 0;
 
 	ret = mmc_suspend_host(mmc);
 
-	clk_disable_unprepare(host->clk);
+	clk_disable_unprepare(ssp->clk);
 
 	return ret;
 }
@@ -811,9 +821,10 @@ static int mxs_mmc_resume(struct device *dev)
 {
 	struct mmc_host *mmc = dev_get_drvdata(dev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
+	struct mxs_ssp *ssp = &host->ssp;
 	int ret = 0;
 
-	clk_prepare_enable(host->clk);
+	clk_prepare_enable(ssp->clk);
 
 	ret = mmc_resume_host(mmc);
 
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index 7dfa1d7..475f69f 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -128,4 +128,12 @@ enum mxs_ssp_id {
 	IMX28_SSP,
 };
 
+struct mxs_ssp {
+	struct device			*dev;
+	void __iomem			*base;
+	struct clk			*clk;
+	unsigned int			clk_rate;
+	enum mxs_ssp_id			devid;
+};
+
 #endif	/* __LINUX_SPI_MXS_SPI_H__ */
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:14 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:14 +0200
Subject: [PATCH 09/10 V2] spi: Add SSP/SPI device tree documentation
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-10-git-send-email-marex@denx.de>

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 Documentation/devicetree/bindings/spi/mxs-spi.txt |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/mxs-spi.txt

V2: Fix the address property length to 0x2000

diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt
new file mode 100644
index 0000000..c36296f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt
@@ -0,0 +1,18 @@
+* Freescale MX233/MX28 SSP/SPI
+
+Required properties:
+- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
+- reg: Offset and length of the register set for the device
+- interrupts: Should contain SSP interrupts (error irq first, dma irq second)
+- fsl,ssp-dma-channel: APBX DMA channel for the SSP
+
+Example:
+
+ssp0: ssp at 80010000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,imx28-spi";
+	reg = <0x80010000 0x2000>;
+	interrupts = <96 82>;
+	fsl,ssp-dma-channel = <0>;
+};
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:12 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:12 +0200
Subject: [PATCH 07/10] mmc: spi: Pull out common DMA parts from MXS MMC
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-8-git-send-email-marex@denx.de>

These parts will be used by the MXS SPI driver too.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mmc/host/mxs-mmc.c  |   88 +++++++++++++++++++++----------------------
 drivers/spi/spi-mxs.c       |    1 -
 include/linux/spi/mxs-spi.h |    9 +++++
 3 files changed, 51 insertions(+), 47 deletions(-)

diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index 0813340..4da9966 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -41,7 +41,6 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
-#include <linux/fsl/mxs-dma.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/stmp_device.h>
 #include <linux/mmc/mxs-mmc.h>
@@ -69,13 +68,6 @@ struct mxs_mmc_host {
 	struct mmc_command		*cmd;
 	struct mmc_data			*data;
 
-	int				dma_channel;
-	struct dma_chan         	*dmach;
-	struct mxs_dma_data		dma_data;
-	unsigned int			dma_dir;
-	enum dma_transfer_direction	slave_dirn;
-	u32				ssp_pio_words[SSP_PIO_NUM];
-
 	unsigned char			bus_width;
 	spinlock_t			lock;
 	int				sdio_irq_en;
@@ -163,7 +155,7 @@ static void mxs_mmc_request_done(struct mxs_mmc_host *host)
 
 	if (data) {
 		dma_unmap_sg(mmc_dev(host->mmc), data->sg,
-			     data->sg_len, host->dma_dir);
+			     data->sg_len, ssp->dma_dir);
 		/*
 		 * If there was an error on any block, we mark all
 		 * data blocks as being in error.
@@ -232,6 +224,7 @@ static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
 	struct mxs_mmc_host *host, unsigned long flags)
 {
+	struct mxs_ssp *ssp = &host->ssp;
 	struct dma_async_tx_descriptor *desc;
 	struct mmc_data *data = host->data;
 	struct scatterlist * sgl;
@@ -240,24 +233,24 @@ static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
 	if (data) {
 		/* data */
 		dma_map_sg(mmc_dev(host->mmc), data->sg,
-			   data->sg_len, host->dma_dir);
+			   data->sg_len, ssp->dma_dir);
 		sgl = data->sg;
 		sg_len = data->sg_len;
 	} else {
 		/* pio */
-		sgl = (struct scatterlist *) host->ssp_pio_words;
+		sgl = (struct scatterlist *) ssp->ssp_pio_words;
 		sg_len = SSP_PIO_NUM;
 	}
 
-	desc = dmaengine_prep_slave_sg(host->dmach,
-				sgl, sg_len, host->slave_dirn, flags);
+	desc = dmaengine_prep_slave_sg(ssp->dmach,
+				sgl, sg_len, ssp->slave_dirn, flags);
 	if (desc) {
 		desc->callback = mxs_mmc_dma_irq_callback;
 		desc->callback_param = host;
 	} else {
 		if (data)
 			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
-				     data->sg_len, host->dma_dir);
+				     data->sg_len, ssp->dma_dir);
 	}
 
 	return desc;
@@ -265,6 +258,7 @@ static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
 
 static void mxs_mmc_bc(struct mxs_mmc_host *host)
 {
+	struct mxs_ssp *ssp = &host->ssp;
 	struct mmc_command *cmd = host->cmd;
 	struct dma_async_tx_descriptor *desc;
 	u32 ctrl0, cmd0, cmd1;
@@ -278,17 +272,17 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 
-	host->ssp_pio_words[0] = ctrl0;
-	host->ssp_pio_words[1] = cmd0;
-	host->ssp_pio_words[2] = cmd1;
-	host->dma_dir = DMA_NONE;
-	host->slave_dirn = DMA_TRANS_NONE;
+	ssp->ssp_pio_words[0] = ctrl0;
+	ssp->ssp_pio_words[1] = cmd0;
+	ssp->ssp_pio_words[2] = cmd1;
+	ssp->dma_dir = DMA_NONE;
+	ssp->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 
 	dmaengine_submit(desc);
-	dma_async_issue_pending(host->dmach);
+	dma_async_issue_pending(ssp->dmach);
 	return;
 
 out:
@@ -298,6 +292,7 @@ out:
 
 static void mxs_mmc_ac(struct mxs_mmc_host *host)
 {
+	struct mxs_ssp *ssp = &host->ssp;
 	struct mmc_command *cmd = host->cmd;
 	struct dma_async_tx_descriptor *desc;
 	u32 ignore_crc, get_resp, long_resp;
@@ -319,17 +314,17 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 
-	host->ssp_pio_words[0] = ctrl0;
-	host->ssp_pio_words[1] = cmd0;
-	host->ssp_pio_words[2] = cmd1;
-	host->dma_dir = DMA_NONE;
-	host->slave_dirn = DMA_TRANS_NONE;
+	ssp->ssp_pio_words[0] = ctrl0;
+	ssp->ssp_pio_words[1] = cmd0;
+	ssp->ssp_pio_words[2] = cmd1;
+	ssp->dma_dir = DMA_NONE;
+	ssp->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 
 	dmaengine_submit(desc);
-	dma_async_issue_pending(host->dmach);
+	dma_async_issue_pending(ssp->dmach);
 	return;
 
 out:
@@ -441,11 +436,11 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 	writel(val, ssp->base + HW_SSP_TIMING(ssp));
 
 	/* pio */
-	host->ssp_pio_words[0] = ctrl0;
-	host->ssp_pio_words[1] = cmd0;
-	host->ssp_pio_words[2] = cmd1;
-	host->dma_dir = DMA_NONE;
-	host->slave_dirn = DMA_TRANS_NONE;
+	ssp->ssp_pio_words[0] = ctrl0;
+	ssp->ssp_pio_words[1] = cmd0;
+	ssp->ssp_pio_words[2] = cmd1;
+	ssp->dma_dir = DMA_NONE;
+	ssp->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, 0);
 	if (!desc)
 		goto out;
@@ -453,14 +448,14 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 	/* append data sg */
 	WARN_ON(host->data != NULL);
 	host->data = data;
-	host->dma_dir = dma_data_dir;
-	host->slave_dirn = slave_dirn;
+	ssp->dma_dir = dma_data_dir;
+	ssp->slave_dirn = slave_dirn;
 	desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 
 	dmaengine_submit(desc);
-	dma_async_issue_pending(host->dmach);
+	dma_async_issue_pending(ssp->dmach);
 	return;
 out:
 	dev_warn(mmc_dev(host->mmc),
@@ -557,14 +552,15 @@ static const struct mmc_host_ops mxs_mmc_ops = {
 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
 {
 	struct mxs_mmc_host *host = param;
+	struct mxs_ssp *ssp = &host->ssp;
 
 	if (!mxs_dma_is_apbh(chan))
 		return false;
 
-	if (chan->chan_id != host->dma_channel)
+	if (chan->chan_id != ssp->dma_channel)
 		return false;
 
-	chan->private = &host->dma_data;
+	chan->private = &ssp->dma_data;
 
 	return true;
 }
@@ -632,7 +628,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 		 * to use generic DMA binding later when the helpers get in.
 		 */
 		ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
-					   &host->dma_channel);
+					   &ssp->dma_channel);
 		if (ret) {
 			dev_err(mmc_dev(host->mmc),
 				"failed to get dma channel\n");
@@ -640,7 +636,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 		}
 	} else {
 		ssp->devid = pdev->id_entry->driver_data;
-		host->dma_channel = dmares->start;
+		ssp->dma_channel = dmares->start;
 	}
 
 	host->mmc = mmc;
@@ -673,9 +669,9 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
-	host->dma_data.chan_irq = irq_dma;
-	host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
-	if (!host->dmach) {
+	ssp->dma_data.chan_irq = irq_dma;
+	ssp->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
+	if (!ssp->dmach) {
 		dev_err(mmc_dev(host->mmc),
 			"%s: failed to request dma\n", __func__);
 		goto out_clk_put;
@@ -714,7 +710,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	mmc->max_blk_size = 1 << 0xf;
 	mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
 	mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
-	mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
+	mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
 
 	platform_set_drvdata(pdev, mmc);
 
@@ -734,8 +730,8 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	return 0;
 
 out_free_dma:
-	if (host->dmach)
-		dma_release_channel(host->dmach);
+	if (ssp->dmach)
+		dma_release_channel(ssp->dmach);
 out_clk_put:
 	clk_disable_unprepare(ssp->clk);
 	clk_put(ssp->clk);
@@ -754,8 +750,8 @@ static int mxs_mmc_remove(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, NULL);
 
-	if (host->dmach)
-		dma_release_channel(host->dmach);
+	if (ssp->dmach)
+		dma_release_channel(ssp->dmach);
 
 	clk_disable_unprepare(ssp->clk);
 	clk_put(ssp->clk);
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 7bf826f..0f28afb 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -46,7 +46,6 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
-#include <linux/fsl/mxs-dma.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/stmp_device.h>
 #include <linux/spi/spi.h>
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index d07f8dc..61ae130 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -24,6 +24,8 @@
 #ifndef __LINUX_SPI_MXS_SPI_H__
 #define __LINUX_SPI_MXS_SPI_H__
 
+#include <linux/fsl/mxs-dma.h>
+
 #define ssp_is_old(host)	((host)->devid == IMX23_SSP)
 
 /* SSP registers */
@@ -134,6 +136,13 @@ struct mxs_ssp {
 	struct clk			*clk;
 	unsigned int			clk_rate;
 	enum mxs_ssp_id			devid;
+
+	int				dma_channel;
+	struct dma_chan			*dmach;
+	struct mxs_dma_data		dma_data;
+	unsigned int			dma_dir;
+	enum dma_transfer_direction	slave_dirn;
+	u32				ssp_pio_words[SSP_PIO_NUM];
 };
 
 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:26:15 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:26:15 +0200
Subject: [PATCH 10/10] ARM: mx28: Add SPI pinmux into imx28.dtsi
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <1344007575-11448-11-git-send-email-marex@denx.de>

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Attila Kinali <attila at kinali.ch>
Cc: Chris Ball <cjb at laptop.org>
CC: Dong Aisheng <b29396 at freescale.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
CC: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28.dtsi |   39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index badc76a..4a0f12c 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -507,6 +507,45 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <0>;
 				};
+
+				spi0_pins_a: spi0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids =
+						<0x2000 0x2010 0x2020 0x2030
+						0x2040 0x2050 0x2060 0x2070
+						0x2080 0x2090 0x20a0>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi1_pins_a: spi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids =
+						<0x20c0 0x20d0 0x20e0 0x20f0>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi2_pins_a: spi2 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids =
+						<0x2100 0x2110 0x2120
+						0x2130 0x2140 0x2150>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi3_pins_a: spi3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids =
+						<0x2180 0x2190 0x21a0 0x21b0>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
 			};
 
 			digctl at 8001c000 {
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:28:38 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:28:38 +0200
Subject: [PATCH 0/3] i.MX28 LRADC driver
Message-ID: <1344007721-11595-1-git-send-email-marex@denx.de>

Introduce the i.MX28 LRADC driver and support tech that comes with it.

Marek Vasut (3):
  IIO: Add 4-byte unsigned reads into generic-buffer example
  IIO: Add basic MXS LRADC driver
  IIO: arm: Add LRADC to i.MX28 dts

 arch/arm/boot/dts/imx28.dtsi                       |    3 +
 drivers/staging/iio/Documentation/generic_buffer.c |   10 +
 drivers/staging/iio/adc/Kconfig                    |   12 +
 drivers/staging/iio/adc/Makefile                   |    1 +
 drivers/staging/iio/adc/mxs-lradc.c                |  591 ++++++++++++++++++++
 5 files changed, 617 insertions(+)
 create mode 100644 drivers/staging/iio/adc/mxs-lradc.c

Cc: Jonathan Cameron <jic23 at kernel.org>
Cc: Juergen Beisert <jbe at pengutronix.de>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Cc: Wolfgang Denk <wd at denx.de>
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:28:41 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:28:41 +0200
Subject: [PATCH 3/3] IIO: arm: Add LRADC to i.MX28 dts
In-Reply-To: <1344007721-11595-1-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
Message-ID: <1344007721-11595-4-git-send-email-marex@denx.de>

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Jonathan Cameron <jic23 at kernel.org>
Cc: Juergen Beisert <jbe at pengutronix.de>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Wolfgang Denk <wd at denx.de>
---
 arch/arm/boot/dts/imx28.dtsi |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4a0f12c..91752d2 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -677,7 +677,10 @@
 			};
 
 			lradc at 80050000 {
+				compatible = "fsl,imx28-lradc";
 				reg = <0x80050000 2000>;
+				interrupts = <10 14 15 16 17 18 19
+						20 21 22 23 24 25>;
 				status = "disabled";
 			};
 
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:28:39 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:28:39 +0200
Subject: [PATCH 1/3] IIO: Add 4-byte unsigned reads into generic-buffer example
In-Reply-To: <1344007721-11595-1-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
Message-ID: <1344007721-11595-2-git-send-email-marex@denx.de>

Add unsigned 32bit-wide reads into the generic-buffer.c

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Jonathan Cameron <jic23 at kernel.org>
Cc: Juergen Beisert <jbe at pengutronix.de>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Cc: Wolfgang Denk <wd at denx.de>
---
 drivers/staging/iio/Documentation/generic_buffer.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/staging/iio/Documentation/generic_buffer.c b/drivers/staging/iio/Documentation/generic_buffer.c
index 827e92d..40d0eca 100644
--- a/drivers/staging/iio/Documentation/generic_buffer.c
+++ b/drivers/staging/iio/Documentation/generic_buffer.c
@@ -104,6 +104,16 @@ void process_scan(char *data,
 			print2byte(*(uint16_t *)(data + channels[k].location),
 				   &channels[k]);
 			break;
+		case 4:
+			if (!channels[k].is_signed) {
+				uint32_t val = *(uint32_t *)
+					(data + channels[k].location);
+				printf("%05f ", ((float)val +
+						 channels[k].offset)*
+				       channels[k].scale);
+
+			}
+			break;
 		case 8:
 			if (channels[k].is_signed) {
 				int64_t val = *(int64_t *)
-- 
1.7.10.4



From marex at denx.de  Fri Aug  3 11:28:40 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:28:40 +0200
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <1344007721-11595-1-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
Message-ID: <1344007721-11595-3-git-send-email-marex@denx.de>

This driver is very basic. It supports userland trigger, buffer and
raw access to channels. The support for delay channels is missing
altogether.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Jonathan Cameron <jic23 at kernel.org>
Cc: Juergen Beisert <jbe at pengutronix.de>
Cc: Lars-Peter Clausen <lars at metafoo.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Wolfgang Denk <wd at denx.de>
---
 drivers/staging/iio/adc/Kconfig     |   12 +
 drivers/staging/iio/adc/Makefile    |    1 +
 drivers/staging/iio/adc/mxs-lradc.c |  591 +++++++++++++++++++++++++++++++++++
 3 files changed, 604 insertions(+)
 create mode 100644 drivers/staging/iio/adc/mxs-lradc.c

V2: Use delay channel 0 in case of buffered sampling so the samples are deployed
    continuously.
    Disallow RAW sampling while buffered mode is enabled to simplify code.

diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig
index 67711b7..97ca697 100644
--- a/drivers/staging/iio/adc/Kconfig
+++ b/drivers/staging/iio/adc/Kconfig
@@ -200,6 +200,18 @@ config LPC32XX_ADC
 	  activate only one via device tree selection.  Provides direct access
 	  via sysfs.
 
+config MXS_LRADC
+	tristate "Freescale i.MX23/i.MX28 LRADC"
+	depends on ARCH_MXS
+	select IIO_BUFFER
+	select IIO_TRIGGERED_BUFFER
+	help
+	  Say yes here to build support for i.MX23/i.MX28 LRADC convertor
+	  built into these chips.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called mxs-lradc.
+
 config SPEAR_ADC
 	tristate "ST SPEAr ADC"
 	depends on PLAT_SPEAR
diff --git a/drivers/staging/iio/adc/Makefile b/drivers/staging/iio/adc/Makefile
index 14e98b6..ecac9a0 100644
--- a/drivers/staging/iio/adc/Makefile
+++ b/drivers/staging/iio/adc/Makefile
@@ -38,4 +38,5 @@ obj-$(CONFIG_ADT7310) += adt7310.o
 obj-$(CONFIG_ADT7410) += adt7410.o
 obj-$(CONFIG_AD7280) += ad7280a.o
 obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o
+obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
 obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
new file mode 100644
index 0000000..58eb50e
--- /dev/null
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -0,0 +1,591 @@
+/*
+ * Freescale i.MX233/i.MX28 LRADC driver
+ *
+ * Copyright (c) 2012 DENX Software Engineering, GmbH.
+ * Marek Vasut <marex at denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/sysfs.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/stmp_device.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/buffer.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/trigger_consumer.h>
+#include <linux/iio/triggered_buffer.h>
+
+#define DRIVER_NAME		"mxs-lradc"
+
+#define LRADC_MAX_DELAY_CHANS	4
+#define LRADC_MAX_MAPPED_CHANS	8
+#define LRADC_MAX_TOTAL_CHANS	16
+
+#define LRADC_DELAY_TIMER_HZ	2000
+
+/*
+ * Make this runtime configurable if necessary. Currently, if the buffered mode
+ * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
+ * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
+ * seconds. The result is that the samples arrive every 500mS.
+ */
+#define LRADC_DELAY_TIMER_PER	200
+#define LRADC_DELAY_TIMER_LOOP	5
+
+static const char * const mxs_lradc_irq_name[] = {
+	"mxs-lradc-touchscreen",
+	"mxs-lradc-thresh0",
+	"mxs-lradc-thresh1",
+	"mxs-lradc-channel0",
+	"mxs-lradc-channel1",
+	"mxs-lradc-channel2",
+	"mxs-lradc-channel3",
+	"mxs-lradc-channel4",
+	"mxs-lradc-channel5",
+	"mxs-lradc-channel6",
+	"mxs-lradc-channel7",
+	"mxs-lradc-button0",
+	"mxs-lradc-button1",
+};
+
+struct mxs_lradc_chan {
+	uint8_t				slot;
+	uint8_t				flags;
+};
+
+struct mxs_lradc {
+	struct device		*dev;
+	void __iomem		*base;
+	int			irq[13];
+
+	uint32_t		*buffer;
+	struct iio_trigger	*trig;
+
+	struct mutex		lock;
+
+	uint8_t			enable;
+
+	struct completion	completion;
+};
+
+#define	LRADC_CTRL0				0x00
+#define LRADC_CTRL0_TOUCH_DETECT_ENABLE		(1 << 23)
+#define LRADC_CTRL0_TOUCH_SCREEN_TYPE		(1 << 22)
+
+#define	LRADC_CTRL1				0x10
+#define	LRADC_CTRL1_LRADC_IRQ(n)		(1 << (n))
+#define	LRADC_CTRL1_LRADC_IRQ_MASK		0x1fff
+#define	LRADC_CTRL1_LRADC_IRQ_EN(n)		(1 << ((n) + 16))
+#define	LRADC_CTRL1_LRADC_IRQ_EN_MASK		(0x1fff << 16)
+
+#define	LRADC_CTRL2				0x20
+#define	LRADC_CTRL2_TEMPSENSE_PWD		(1 << 15)
+
+#define	LRADC_CH(n)				(0x50 + (0x10 * (n)))
+#define	LRADC_CH_ACCUMULATE			(1 << 29)
+#define	LRADC_CH_NUM_SAMPLES_MASK		(0x1f << 24)
+#define	LRADC_CH_NUM_SAMPLES_OFFSET		24
+#define	LRADC_CH_VALUE_MASK			0x3ffff
+#define	LRADC_CH_VALUE_OFFSET			0
+
+#define	LRADC_DELAY(n)				(0xd0 + (0x10 * (n)))
+#define	LRADC_DELAY_TRIGGER_LRADCS_MASK		(0xff << 24)
+#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET	24
+#define	LRADC_DELAY_KICK			(1 << 20)
+#define	LRADC_DELAY_TRIGGER_DELAYS_MASK		(0xf << 16)
+#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET	16
+#define	LRADC_DELAY_LOOP_COUNT_MASK		(0x1f << 11)
+#define	LRADC_DELAY_LOOP_COUNT_OFFSET		11
+#define	LRADC_DELAY_DELAY_MASK			0x7ff
+#define	LRADC_DELAY_DELAY_OFFSET		0
+
+#define	LRADC_CTRL4				0x140
+#define	LRADC_CTRL4_LRADCSELECT_MASK(n)		(0xf << ((n) * 4))
+#define	LRADC_CTRL4_LRADCSELECT_OFFSET(n)	((n) * 4)
+
+/*
+ * Raw I/O operations
+ */
+static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
+			const struct iio_chan_spec *chan,
+			int *val, int *val2, long m)
+{
+	struct mxs_lradc *lradc = iio_priv(iio_dev);
+	int ret;
+
+	if (m != IIO_CHAN_INFO_RAW)
+		return -EINVAL;
+
+	/* Check for invalid channel */
+	if (chan->channel > LRADC_MAX_TOTAL_CHANS)
+		return -EINVAL;
+
+	/*
+	 * See if there is no buffered operation in progess. If there is, simply
+	 * bail out. This can be improved to support both buffered and raw IO at
+	 * the same time, yet the code becomes horribly complicated. Therefore I
+	 * applied KISS principle here.
+	 */
+	ret = mutex_trylock(&lradc->lock);
+	if (!ret)
+		return -EBUSY;
+
+	init_completion(&lradc->completion);
+
+	/*
+	 * No buffered operation in progress, map the channel and trigger it.
+	 * Virtual channel 0 is always used here as the others are always not
+	 * used if doing raw sampling.
+	 */
+	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
+
+	writel(chan->channel, lradc->base + LRADC_CTRL4);
+	writel(0, lradc->base + LRADC_CH(0));
+
+	/* Enable the IRQ and start sampling the channel. */
+	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
+	writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
+
+	/* Wait for completion on the channel, 1 second max. */
+	ret = wait_for_completion_killable_timeout(&lradc->completion,
+						msecs_to_jiffies(1000));
+	if (!ret)
+		ret = -ETIMEDOUT;
+	if (ret < 0)
+		goto err;
+
+	/* Read the data. */
+	*val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
+	ret = IIO_VAL_INT;
+
+err:
+	writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+
+	mutex_unlock(&lradc->lock);
+
+	return ret;
+}
+
+static const struct iio_info mxs_lradc_iio_info = {
+	.driver_module		= THIS_MODULE,
+	.read_raw		= mxs_lradc_read_raw,
+};
+
+/*
+ * IRQ Handling
+ */
+static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
+{
+	struct iio_dev *iio = data;
+	struct mxs_lradc *lradc = iio_priv(iio);
+	unsigned long reg = readl(lradc->base + LRADC_CTRL1);
+
+	if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
+		return IRQ_NONE;
+
+	/*
+	 * Touchscreen IRQ handling code shall probably have priority
+	 * and therefore shall be placed here.
+	 */
+
+	if (iio_buffer_enabled(iio))
+		iio_trigger_poll(iio->trig, iio_get_time_ns());
+	else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
+		complete(&lradc->completion);
+
+	writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Trigger handling
+ */
+static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
+{
+	struct iio_poll_func *pf = p;
+	struct iio_dev *iio = pf->indio_dev;
+	struct mxs_lradc *lradc = iio_priv(iio);
+	struct iio_buffer *buffer = iio->buffer;
+	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
+		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
+	int i, j = 0;
+
+	for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
+		lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
+		writel(chan_value, lradc->base + LRADC_CH(j));
+		lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
+		lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
+		j++;
+	}
+
+	if (iio->scan_timestamp) {
+		s64 *timestamp = (s64 *)((u8 *)lradc->buffer +
+					ALIGN(j, sizeof(s64)));
+		*timestamp = pf->timestamp;
+	}
+
+	iio_push_to_buffer(buffer, (u8 *)lradc->buffer, pf->timestamp);
+
+	iio_trigger_notify_done(iio->trig);
+
+	return IRQ_HANDLED;
+}
+
+static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
+{
+	struct iio_dev *iio = trig->private_data;
+	struct mxs_lradc *lradc = iio_priv(iio);
+	const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
+
+	writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
+
+	return 0;
+}
+
+static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
+	.owner = THIS_MODULE,
+	.set_trigger_state = &mxs_lradc_configure_trigger,
+};
+
+static int mxs_lradc_trigger_init(struct iio_dev *iio)
+{
+	int ret;
+	struct iio_trigger *trig;
+
+	trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
+	if (trig == NULL)
+		return -ENOMEM;
+
+	trig->dev.parent = iio->dev.parent;
+	trig->private_data = iio;
+	trig->ops = &mxs_lradc_trigger_ops;
+
+	ret = iio_trigger_register(trig);
+	if (ret) {
+		iio_trigger_free(trig);
+		return ret;
+	}
+
+	iio->trig = trig;
+
+	return 0;
+}
+
+static void mxs_lradc_trigger_remove(struct iio_dev *iio)
+{
+	iio_trigger_unregister(iio->trig);
+	iio_trigger_free(iio->trig);
+}
+
+static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
+{
+	struct mxs_lradc *lradc = iio_priv(iio);
+	struct iio_buffer *buffer = iio->buffer;
+	int ret = 0, chan, ofs = 0, enable = 0;
+	uint32_t ctrl4 = 0;
+	uint32_t ctrl1_irq = 0;
+	const uint32_t chan_value = LRADC_CH_ACCUMULATE |
+		((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
+	const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
+
+	if (!len)
+		return -EINVAL;
+
+	/*
+	 * Lock the driver so raw access can not be done during buffered
+	 * operation. This simplifies the code a lot.
+	 */
+	ret = mutex_trylock(&lradc->lock);
+	if (!ret)
+		return -EBUSY;
+
+	lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
+	if (!lradc->buffer) {
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	ret = iio_sw_buffer_preenable(iio);
+	if (ret < 0)
+		goto err_buf;
+
+	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
+
+	for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
+		ctrl4 |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
+		ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
+		writel(chan_value, lradc->base + LRADC_CH(ofs));
+		enable |= 1 << ofs;
+		ofs++;
+	};
+
+	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
+		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
+
+	writel(ctrl4, lradc->base + LRADC_CTRL4);
+	writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
+
+	writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
+		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
+
+	return 0;
+
+err_buf:
+	kfree(lradc->buffer);
+err_mem:
+	mutex_unlock(&lradc->lock);
+	return ret;
+}
+
+static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
+{
+	struct mxs_lradc *lradc = iio_priv(iio);
+
+	writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
+		lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
+
+	writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
+	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+
+	kfree(lradc->buffer);
+	mutex_unlock(&lradc->lock);
+
+	return 0;
+}
+
+static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
+					const unsigned long *mask)
+{
+	const int mw = bitmap_weight(mask, iio->masklength);
+
+	return mw <= LRADC_MAX_MAPPED_CHANS;
+}
+
+static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
+	.preenable = &mxs_lradc_buffer_preenable,
+	.postenable = &iio_triggered_buffer_postenable,
+	.predisable = &iio_triggered_buffer_predisable,
+	.postdisable = &mxs_lradc_buffer_postdisable,
+	.validate_scan_mask = &mxs_lradc_validate_scan_mask,
+};
+
+/*
+ * Driver initialization
+ */
+
+#define MXS_ADC_CHAN(idx, chan_type) {				\
+	.type = (chan_type),					\
+	.indexed = 1,						\
+	.scan_index = (idx),					\
+	.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT,		\
+	.channel = (idx),					\
+	.scan_type = {						\
+		.sign = 'u',					\
+		.realbits = 18,					\
+		.storagebits = 32,				\
+	},							\
+}
+
+static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
+	MXS_ADC_CHAN(0, IIO_VOLTAGE),
+	MXS_ADC_CHAN(1, IIO_VOLTAGE),
+	MXS_ADC_CHAN(2, IIO_VOLTAGE),
+	MXS_ADC_CHAN(3, IIO_VOLTAGE),
+	MXS_ADC_CHAN(4, IIO_VOLTAGE),
+	MXS_ADC_CHAN(5, IIO_VOLTAGE),
+	MXS_ADC_CHAN(6, IIO_VOLTAGE),
+	MXS_ADC_CHAN(7, IIO_VOLTAGE),	/* VBATT */
+	MXS_ADC_CHAN(8, IIO_TEMP),	/* Temp sense 0 */
+	MXS_ADC_CHAN(9, IIO_TEMP),	/* Temp sense 1 */
+	MXS_ADC_CHAN(10, IIO_VOLTAGE),	/* VDDIO */
+	MXS_ADC_CHAN(11, IIO_VOLTAGE),	/* VTH */
+	MXS_ADC_CHAN(12, IIO_VOLTAGE),	/* VDDA */
+	MXS_ADC_CHAN(13, IIO_VOLTAGE),	/* VDDD */
+	MXS_ADC_CHAN(14, IIO_VOLTAGE),	/* VBG */
+	MXS_ADC_CHAN(15, IIO_VOLTAGE),	/* VDD5V */
+};
+
+static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
+{
+	int i;
+	const uint32_t cfg =
+		(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
+
+	stmp_reset_block(lradc->base);
+
+	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
+		writel(cfg | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)),
+			lradc->base + LRADC_DELAY(i));
+
+	/* Start internal temperature sensing. */
+	writel(0, lradc->base + LRADC_CTRL2);
+}
+
+static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
+{
+	int i;
+
+	writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
+		lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
+
+	for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
+		writel(0, lradc->base + LRADC_DELAY(i));
+}
+
+static int __devinit mxs_lradc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mxs_lradc *lradc;
+	struct iio_dev *iio;
+	struct resource *iores;
+	int ret = 0;
+	int i;
+
+	/* Allocate the IIO device. */
+	iio = iio_device_alloc(sizeof(*lradc));
+	if (!iio) {
+		dev_err(dev, "Failed to allocate IIO device\n");
+		return -ENOMEM;
+	}
+
+	lradc = iio_priv(iio);
+
+	/* Grab the memory area */
+	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	lradc->dev = &pdev->dev;
+	lradc->base = devm_request_and_ioremap(dev, iores);
+	if (!lradc->base) {
+		ret = -EADDRNOTAVAIL;
+		goto err_addr;
+	}
+
+	/* Grab all IRQ sources */
+	for (i = 0; i < 13; i++) {
+		lradc->irq[i] = platform_get_irq(pdev, i);
+		if (lradc->irq[i] < 0) {
+			ret = -EINVAL;
+			goto err_addr;
+		}
+
+		ret = devm_request_irq(dev, lradc->irq[i],
+					mxs_lradc_handle_irq, 0,
+					mxs_lradc_irq_name[i], iio);
+		if (ret)
+			goto err_addr;
+	}
+
+	dev_set_drvdata(&pdev->dev, iio);
+
+	init_completion(&lradc->completion);
+	mutex_init(&lradc->lock);
+
+	iio->name = pdev->name;
+	iio->dev.parent = &pdev->dev;
+	iio->info = &mxs_lradc_iio_info;
+	iio->modes = INDIO_DIRECT_MODE;
+	iio->channels = mxs_lradc_chan_spec;
+	iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
+
+	ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
+				&mxs_lradc_trigger_handler,
+				&mxs_lradc_buffer_ops);
+	if (ret)
+		goto err_addr;
+
+	ret = mxs_lradc_trigger_init(iio);
+	if (ret)
+		goto err_trig;
+
+	/* Register IIO device. */
+	ret = iio_device_register(iio);
+	if (ret) {
+		dev_err(dev, "Failed to register IIO device\n");
+		goto err_dev;
+	}
+
+	/* Configure the hardware. */
+	mxs_lradc_hw_init(lradc);
+
+	return 0;
+
+err_dev:
+	mxs_lradc_trigger_remove(iio);
+err_trig:
+	iio_triggered_buffer_cleanup(iio);
+err_addr:
+	iio_device_free(iio);
+	return ret;
+}
+
+static int __devexit mxs_lradc_remove(struct platform_device *pdev)
+{
+	struct iio_dev *iio = dev_get_drvdata(&pdev->dev);
+	struct mxs_lradc *lradc = iio_priv(iio);
+
+	mxs_lradc_hw_stop(lradc);
+
+	iio_device_unregister(iio);
+	iio_triggered_buffer_cleanup(iio);
+	mxs_lradc_trigger_remove(iio);
+	iio_device_free(iio);
+
+	return 0;
+}
+
+static const struct of_device_id mxs_lradc_dt_ids[] = {
+	{ .compatible = "fsl,imx28-lradc", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
+
+static struct platform_driver mxs_lradc_driver = {
+	.driver	= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+		.of_match_table = mxs_lradc_dt_ids,
+	},
+	.probe	= mxs_lradc_probe,
+	.remove	= __devexit_p(mxs_lradc_remove),
+};
+
+module_platform_driver(mxs_lradc_driver);
+
+MODULE_AUTHOR("Marek Vasut <marex at denx.de>");
+MODULE_DESCRIPTION("Freescale i.MX23/i.MX28 LRADC driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From baruch at tkos.co.il  Fri Aug  3 11:37:08 2012
From: baruch at tkos.co.il (Baruch Siach)
Date: Fri, 3 Aug 2012 18:37:08 +0300
Subject: [PATCH v2] Visstrim SM10: Use mo_version to decide board video
 mode.
In-Reply-To: <1343995703-13578-1-git-send-email-javier.martin@vista-silicon.com>
References: <1343995703-13578-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120803153708.GA3733@tarshish>

Hi Javier,

On Fri, Aug 03, 2012 at 02:08:23PM +0200, Javier Martin wrote:
> If the mother board version number is odd, emmaprp() for
> format conversion + UVC camera will be used.
> 
> Otherwise mx2_camera and m2m-deinterlacer will be registered.
> 
> For both cases Coda video codec is registered.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
> Changes since v1:
>  - Add error message to emmaprp init function.
> ---

...

> +/* Emma-PrP for format conversion */
> +static void __init visstrim_emmaprp_init(void)
> +{
> +	struct platform_device *pdev;
> +	int dma;
> +
> +	pdev = imx27_add_mx2_emmaprp();
> +	if (IS_ERR(pdev))
> +		return;
> +
> +	/*
> +	 * Use the same memory area as the analog camera since both
> +	 * devices are, by nature, exclusive.
> +	 */
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +				mx2_camera_base, mx2_camera_base,
> +				MX2_CAMERA_BUF_SIZE,
> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +	if (!(dma & DMA_MEMORY_MAP)) {
> +		pr_err("Failed to declare memory for emmaprp\n");
> +		return;

Nitpick: the 'return' is redundant here.

> +	}
> +}

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From jonathan.austin at arm.com  Fri Aug  3 11:37:58 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 03 Aug 2012 16:37:58 +0100
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <20120803145035.GJ2626@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <201208031407.09092.arnd@arndb.de> <20120803145035.GJ2626@pengutronix.de>
Message-ID: <501BF056.5000801@arm.com>

On 03/08/12 15:50, Uwe Kleine-K?nig wrote:

...
>  
>> How does this relate to the ARMv6-M (Cortex-M0/M0+/M1) support
>> that has been floating around [1]? Can we support both in
>> the same kernel? 
> I don't know M0/M1 but from a quick look at the tree you pointed out I'd
> say they look reasonably similar.
> 

I'm not so sure - M0/M0+/M1 don't use Thumb-2, they're a slightly
extended version of Thumb-1, which we don't support in the kernel...

For the curious, here are the relevant bits from the ARM ARMs

>From the ARM (v6-M) ARM A4.1 - about the instruction set:

"ARMv6-M supports the Thumb instruction set including a small number of
32-bit instructions introduced with Thumb-2 technology, see 32-bit Thumb
instruction encoding on page A5-91. The 16-bit instruction
support is equivalent to the Thumb instruction set support in ARMv6
prior to the introduction of Thumb-2 technology."

Whereas for V7-M, it says:
"supports a large number of 32-bit instructions that Thumb-2 technology
introduced into the Thumb instruction set. Much of the functionality
available is identical to the ARM instruction set supported alongside
the Thumb instruction set in ARMv6T2 and other ARMv7 profiles"

Jonny



From linux at arm.linux.org.uk  Fri Aug  3 11:43:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 Aug 2012 16:43:55 +0100
Subject: MMAP_MIN_ADDR problem/question
In-Reply-To: <201208020939.50225.marek.vasut@gmail.com>
References: <201208020939.50225.marek.vasut@gmail.com>
Message-ID: <20120803154355.GA6802@n2100.arm.linux.org.uk>

On Thu, Aug 02, 2012 at 09:39:50AM +0200, Marek Vasut wrote:
> Hi guys,
> 
> Me and a coleague of mine recently ran into the issue [1]. The problem is, that 
> I set mmap_min_addr to 65536, making it unable for "su - user" command to work, 
> it crashes with SIGKILL. I now at least see a solution (set it to 32768). Though 
> I don't understand why. Can someone please exaplain me why it has to be 32768 an 
> not more?
> 
> [1] http://ubuntu.5.n6.nabble.com/PATCH-DEFAULT-MMAP-MIN-ADDR-32768-for-arm-
> td1604723.html

Looks to me like there's a reading exercise for someone in the MXS
community who set the default to 64K.  The default in the Kconfig is
already appropriately chosen, so for the defconfig to have the 64K
value, someone must have _intentionally_ changed it without thinking
about what they were doing.

Just produce a patch to fix the defconfig.


From omar.luna at linaro.org  Fri Aug  3 11:52:09 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Fri, 3 Aug 2012 10:52:09 -0500
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <501B609F.9030403@ti.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
 <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>
 <501B609F.9030403@ti.com>
Message-ID: <CALLhW=7yJTq_cfB=KGY5VT8fNO1u_hrY118ysihFuQA+gVFRuQ@mail.gmail.com>

On 3 August 2012 00:24, Vaibhav Hiremath <hvaibhav at ti.com> wrote:
> On 8/3/2012 3:50 AM, Omar Ramirez Luna wrote:
>> So in _enable:
>>
>>         _enable_clocks(oh);
>>         if (soc_ops.enable_module)
>>                 soc_ops.enable_module(oh);
>>
>> The enable_module part seems redundant to me, since the module should
>> be already enabled by the first call to _enable_clocks.
>
> Yes they do same thing, I believe the plan is to get rid of all clock
> leaf-nodes in the near future, and let hwmod handle module
> enable/disable part.

If this is the case then an enable_module call is needed in my patch
for when these changes are made. The original works fine but only
because currently clock framework does what enable_module is doing.

Paul,

Please let me know if you want me to resend with this change.

Regards,

Omar


From marex at denx.de  Fri Aug  3 11:55:54 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 17:55:54 +0200
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
Message-ID: <1344009354-13249-1-git-send-email-marex@denx.de>

Initially reported by Detlev Zundel <dzu at denx.de>, this caused breakage
when "su - testuser" was called. "testuser" being a regular user account,
the command ended with SIGKILL.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Wolfgang Denk <wd at denx.de>
---
 arch/arm/configs/mxs_defconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..f212802 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -34,7 +34,7 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
-- 
1.7.10.4



From maxime.ripard at free-electrons.com  Fri Aug  3 12:27:41 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 03 Aug 2012 18:27:41 +0200
Subject: [PATCH] SPI: MXS: Allow to pass the SPI master bus number from
 the device tree
In-Reply-To: <20120803144326.GE23791@S2101-09.ap.freescale.net>
References: <1343076052-27312-1-git-send-email-marex@denx.de>
 <1344004239-22868-1-git-send-email-maxime.ripard@free-electrons.com>
 <20120803144326.GE23791@S2101-09.ap.freescale.net>
Message-ID: <501BFBFD.7060002@free-electrons.com>

Le 03/08/2012 16:43, Shawn Guo a ?crit :
> On Fri, Aug 03, 2012 at 04:30:39PM +0200, Maxime Ripard wrote:
>> If you don't do it, the bus number will be a bogus value, possibly used
>> for device file names in drivers like spidev.
>>
> Do you see any problem with that?  Here is the take from Grant.
> 
> http://thread.gmane.org/gmane.linux.kernel.spi.devel/9839/focus=9863

Ok, I didn't see this thread, obviously.

Thanks,
Maxime


-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From festevam at gmail.com  Fri Aug  3 12:46:00 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 13:46:00 -0300
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <1344009354-13249-1-git-send-email-marex@denx.de>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
Message-ID: <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>

Marek,

On Fri, Aug 3, 2012 at 12:55 PM, Marek Vasut <marex at denx.de> wrote:
> Initially reported by Detlev Zundel <dzu at denx.de>, this caused breakage
> when "su - testuser" was called. "testuser" being a regular user account,
> the command ended with SIGKILL.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Wolfgang Denk <wd at denx.de>
> ---
>  arch/arm/configs/mxs_defconfig |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
> index ccdb635..f212802 100644
> --- a/arch/arm/configs/mxs_defconfig
> +++ b/arch/arm/configs/mxs_defconfig
> @@ -34,7 +34,7 @@ CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
>  CONFIG_PREEMPT_VOLUNTARY=y
>  CONFIG_AEABI=y
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
> +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768

No need to set it to 32768.

If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then this
symbol will be 32768.

So your patch would become:

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..4edcfb4 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -34,7 +34,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y

Regards,

Fabio Estevam


From vikram.pandita at ti.com  Fri Aug  3 12:46:15 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 09:46:15 -0700
Subject: [PATCH v2] printk: add option to print cpu id
In-Reply-To: <20120803104212.GA6936@x1.osrc.amd.com>
References: <1343985378-22330-1-git-send-email-vikram.pandita@ti.com>
 <D958900912E20642BCBC71664EFECE3E6DDCAC49AB@BGMAIL02.nvidia.com>
 <D958900912E20642BCBC71664EFECE3E6DDCAC49AE@BGMAIL02.nvidia.com>
 <CAFm5wm2Z+FyVqG5oMWiEmZ8Je88hJ-cyDXmJw0wp4mqA-X9eYg@mail.gmail.com>
 <CAPXgP13UBwQLs+m_aSk3Ljbktz8WrL+ZO_Tfhrt_+tRBCARyQQ@mail.gmail.com>
 <CAFm5wm0nf47bcTu7iiXA3geR_5dDTF1tnf81Lz7JzbWkKdhUtA@mail.gmail.com>
 <CAPXgP11A=QfOt4SL2GvhsepP8JiDFfdaAhi6-AhW++-AvOz+aw@mail.gmail.com>
 <20120803104212.GA6936@x1.osrc.amd.com>
Message-ID: <CAFm5wm0rsvuBafMH+9PpKwfaBimbRrVzxYV0nD_pg1yisAYwxQ@mail.gmail.com>

Borislav/Kay

On Fri, Aug 3, 2012 at 3:42 AM, Borislav Petkov <bp at alien8.de> wrote:
>
> On Fri, Aug 03, 2012 at 12:09:15PM +0200, Kay Sievers wrote:
> > That would be needed, I guess. We easily have server systems with more
> > than 255 CPUs. It will only be a matter of time, that the number of
> > CPUs will increase for everybody, I guess.
>
> Actually, AFAICR, we already have SGI machines booting Linux on 4K cpus.
> Now.
>
> > > b) to put cpuid in struct cont and struct log - under the #ifdef
> > > macro?
> >
> > As said, I really can't tell how generally useful it is, and if people
> > think that it should be there unconditionally, should not be there at
> > all, or as a compile time option. Others might have an opinion on
> > that.
> >
> > I personally never missed the CPU-ID in the logs. I personally would
> > find the PID/task ID more interesting, and even that I never really
> > missed. :)

I mostly work with ARM Soc - specifically on OMAP.
SMP multi core systems in ARM-v7 world started to show up only few
years back - unlike x86 world.

ARM systems are a bit unique when it comes to security( read trust
zone ), and handling of FIQ's.
Most of the ARM cortex-A series SoC's out there have some kind of
affinity to CPU0 being the master.
One use case has been, it has helped to know with this printk logging,
if such constraints are honored.

Sometimes, tracking of some lockup cases between cpu's because of bad
code has also been helpful with this logging support.
For now i will post v3 of the patch and add arm-list and linux-omap
list, and there might be users there can benefit.

>
> And even then you can add debugging code to dump the stuff you need.
>
> And I have to agree with Kai here, having the cpu number in dmesg is
> not something I'd wish for - printk timestampts OTOH has at least some
> usecases.
>
> Thanks.
>
> --
> Regards/Gruss,
> Boris.


From festevam at gmail.com  Fri Aug  3 12:48:12 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 13:48:12 -0300
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
Message-ID: <CAOMZO5Cg_YvJSCdnxWkW3K5Wk=o0DLa9kefgeeuQYpRWVMCPkg@mail.gmail.com>

On Fri, Aug 3, 2012 at 1:46 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Marek,
>
> On Fri, Aug 3, 2012 at 12:55 PM, Marek Vasut <marex at denx.de> wrote:
>> Initially reported by Detlev Zundel <dzu at denx.de>, this caused breakage
>> when "su - testuser" was called. "testuser" being a regular user account,
>> the command ended with SIGKILL.

Also, please point to the commit that introduced such breakage.

Thanks,

Fabio Estevam


From festevam at gmail.com  Fri Aug  3 12:54:07 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 13:54:07 -0300
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
Message-ID: <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>

On Fri, Aug 3, 2012 at 1:46 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Marek,
>
> On Fri, Aug 3, 2012 at 12:55 PM, Marek Vasut <marex at denx.de> wrote:
>> Initially reported by Detlev Zundel <dzu at denx.de>, this caused breakage
>> when "su - testuser" was called. "testuser" being a regular user account,
>> the command ended with SIGKILL.
>>
>> Signed-off-by: Marek Vasut <marex at denx.de>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Shawn Guo <shawn.guo at linaro.org>
>> Cc: Wolfgang Denk <wd at denx.de>
>> ---
>>  arch/arm/configs/mxs_defconfig |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
>> index ccdb635..f212802 100644
>> --- a/arch/arm/configs/mxs_defconfig
>> +++ b/arch/arm/configs/mxs_defconfig
>> @@ -34,7 +34,7 @@ CONFIG_NO_HZ=y
>>  CONFIG_HIGH_RES_TIMERS=y
>>  CONFIG_PREEMPT_VOLUNTARY=y
>>  CONFIG_AEABI=y
>> -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
>> +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
>
> No need to set it to 32768.
>
> If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then this
> symbol will be 32768.

Sorry, ignore what I said. I just realized that the default is 4096.


From vikram.pandita at ti.com  Fri Aug  3 12:56:44 2012
From: vikram.pandita at ti.com (Vikram Pandita)
Date: Fri, 3 Aug 2012 09:56:44 -0700
Subject: [PATCH v3] printk: add option to print cpu id
Message-ID: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>

From: Vikram Pandita <vikram.pandita at ti.com>

Introduce config option to enable CPU id reporting for printk() calls.

Example logs with this option enabled look like:
[   0] [    0.063232] Mount-cache hash table entries: 512
[   0] [    0.068054] CPU: Testing write buffer coherency: ok
[   0] [    0.068939] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[   0] [    0.069305] Setting up static identity map for 0x8046dc90 - 0x8046dd00
[   0] [    0.069366] L310 cache controller enabled
[   0] [    0.069396] l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x7e470000
[   1] [    0.073211] CPU1: Booted secondary processor
[   1] [    0.100463] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[   1] [    0.100555] CPU1: Unknown IPI message 0x0
[   0] [    0.101348] Brought up 2 CPUs

Its sometimes very useful to have printk also print the CPU Identifier
that executed the call. This has helped to debug various SMP issues on shipping
products.

Known limitation is if the system gets preempted between function call and
actual printk, the reported cpu-id might not be accurate. But most of the
times its seen to give a good feel of how the N cpu's in the system are
getting loaded.

Signed-off-by: Vikram Pandita <vikram.pandita at ti.com>
Cc: Kay Sievers <kay at vrfy.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Vimarsh Zutshi <vimarsh.zutshi at gmail.com>
Signed-off-by: Vikram Pandita <vikram.pandita at ti.com>
---
v1: initial version - had wrong cpuid logging mechanism
v2: fixed as per review comments from Kay Sievers
v3: allow cpuid to be u16 to support multi-core systems with 1000+ cores

 kernel/printk.c   |   51 +++++++++++++++++++++++++++++++++++++++++----------
 lib/Kconfig.debug |   13 +++++++++++++
 2 files changed, 54 insertions(+), 10 deletions(-)

diff --git a/kernel/printk.c b/kernel/printk.c
index 6a76ab9..90d49b2 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -208,6 +208,7 @@ struct log {
 	u8 facility;		/* syslog facility */
 	u8 flags:5;		/* internal record flags */
 	u8 level:3;		/* syslog level */
+	u16 cpuid;		/* cpu invoking the log */
 };
 
 /*
@@ -305,7 +306,8 @@ static u32 log_next(u32 idx)
 static void log_store(int facility, int level,
 		      enum log_flags flags, u64 ts_nsec,
 		      const char *dict, u16 dict_len,
-		      const char *text, u16 text_len)
+		      const char *text, u16 text_len,
+		      const u16 cpuid)
 {
 	struct log *msg;
 	u32 size, pad_len;
@@ -356,6 +358,7 @@ static void log_store(int facility, int level,
 		msg->ts_nsec = local_clock();
 	memset(log_dict(msg) + dict_len, 0, pad_len);
 	msg->len = sizeof(struct log) + text_len + dict_len + pad_len;
+	msg->cpuid = cpuid;
 
 	/* insert message */
 	log_next_idx += msg->len;
@@ -855,6 +858,25 @@ static size_t print_time(u64 ts, char *buf)
 		       (unsigned long)ts, rem_nsec / 1000);
 }
 
+#if defined(CONFIG_PRINTK_CPUID)
+static bool printk_cpuid = 1;
+#else
+static bool printk_cpuid;
+#endif
+module_param_named(cpuid, printk_cpuid, bool, S_IRUGO | S_IWUSR);
+
+static size_t print_cpuid(u16 cpuid, char *buf)
+{
+
+	if (!printk_cpuid)
+		return 0;
+
+	if (!buf)
+		return 7;
+
+	return sprintf(buf, "[%4d] ", cpuid);
+}
+
 static size_t print_prefix(const struct log *msg, bool syslog, char *buf)
 {
 	size_t len = 0;
@@ -874,6 +896,7 @@ static size_t print_prefix(const struct log *msg, bool syslog, char *buf)
 		}
 	}
 
+	len += print_cpuid(msg->cpuid, buf ? buf + len : NULL);
 	len += print_time(msg->ts_nsec, buf ? buf + len : NULL);
 	return len;
 }
@@ -1387,6 +1410,7 @@ static struct cont {
 	u64 ts_nsec;			/* time of first print */
 	u8 level;			/* log level of first message */
 	u8 facility;			/* log level of first message */
+	u16 cpuid;			/* cpu invoking the logging request */
 	enum log_flags flags;		/* prefix, newline flags */
 	bool flushed:1;			/* buffer sealed and committed */
 } cont;
@@ -1405,7 +1429,8 @@ static void cont_flush(enum log_flags flags)
 		 * line. LOG_NOCONS suppresses a duplicated output.
 		 */
 		log_store(cont.facility, cont.level, flags | LOG_NOCONS,
-			  cont.ts_nsec, NULL, 0, cont.buf, cont.len);
+			  cont.ts_nsec, NULL, 0, cont.buf, cont.len,
+			  cont.cpuid);
 		cont.flags = flags;
 		cont.flushed = true;
 	} else {
@@ -1414,12 +1439,14 @@ static void cont_flush(enum log_flags flags)
 		 * just submit it to the store and free the buffer.
 		 */
 		log_store(cont.facility, cont.level, flags, 0,
-			  NULL, 0, cont.buf, cont.len);
+			  NULL, 0, cont.buf, cont.len,
+			  cont.cpuid);
 		cont.len = 0;
 	}
 }
 
-static bool cont_add(int facility, int level, const char *text, size_t len)
+static bool cont_add(int facility, int level, const char *text, size_t len,
+			const u16 cpuid)
 {
 	if (cont.len && cont.flushed)
 		return false;
@@ -1442,6 +1469,7 @@ static bool cont_add(int facility, int level, const char *text, size_t len)
 
 	memcpy(cont.buf + cont.len, text, len);
 	cont.len += len;
+	cont.cpuid = cpuid;
 
 	if (cont.len > (sizeof(cont.buf) * 80) / 100)
 		cont_flush(LOG_CONT);
@@ -1455,7 +1483,8 @@ static size_t cont_print_text(char *text, size_t size)
 	size_t len;
 
 	if (cont.cons == 0 && (console_prev & LOG_NEWLINE)) {
-		textlen += print_time(cont.ts_nsec, text);
+		textlen += print_cpuid(cont.cpuid, text);
+		textlen += print_time(cont.ts_nsec, text + textlen);
 		size -= textlen;
 	}
 
@@ -1527,7 +1556,7 @@ asmlinkage int vprintk_emit(int facility, int level,
 		printed_len += strlen(recursion_msg);
 		/* emit KERN_CRIT message */
 		log_store(0, 2, LOG_PREFIX|LOG_NEWLINE, 0,
-			  NULL, 0, recursion_msg, printed_len);
+			  NULL, 0, recursion_msg, printed_len, this_cpu);
 	}
 
 	/*
@@ -1577,9 +1606,9 @@ asmlinkage int vprintk_emit(int facility, int level,
 			cont_flush(LOG_NEWLINE);
 
 		/* buffer line if possible, otherwise store it right away */
-		if (!cont_add(facility, level, text, text_len))
+		if (!cont_add(facility, level, text, text_len, this_cpu))
 			log_store(facility, level, lflags | LOG_CONT, 0,
-				  dict, dictlen, text, text_len);
+				  dict, dictlen, text, text_len, this_cpu);
 	} else {
 		bool stored = false;
 
@@ -1591,13 +1620,15 @@ asmlinkage int vprintk_emit(int facility, int level,
 		 */
 		if (cont.len && cont.owner == current) {
 			if (!(lflags & LOG_PREFIX))
-				stored = cont_add(facility, level, text, text_len);
+				stored = cont_add(facility, level, text, text_len,
+						this_cpu);
 			cont_flush(LOG_NEWLINE);
 		}
 
 		if (!stored)
 			log_store(facility, level, lflags, 0,
-				  dict, dictlen, text, text_len);
+				  dict, dictlen, text, text_len,
+				  this_cpu);
 	}
 	printed_len += text_len;
 
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 2403a63..139b2b1 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -14,6 +14,19 @@ config PRINTK_TIME
 	  The behavior is also controlled by the kernel command line
 	  parameter printk.time=1. See Documentation/kernel-parameters.txt
 
+config PRINTK_CPUID
+	bool "Show cpu id information on printks"
+	depends on PRINTK
+	help
+	  Selecting this option causes cpu identifier to be added to the
+	  output of the syslog() system call and at the console.
+
+	  This flag just specifies if the cpu-id should
+	  be included.
+
+	  The behavior is also controlled by the kernel command line
+	  parameter printk.cpuid=1.
+
 config DEFAULT_MESSAGE_LOGLEVEL
 	int "Default message log level (1-7)"
 	range 1 7
-- 
1.7.9.5



From sshtylyov at mvista.com  Fri Aug  3 13:22:19 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 03 Aug 2012 21:22:19 +0400
Subject: [PATCH 1/4] arm/dts: omap5-evm: Add I2C support
In-Reply-To: <1343997486-710-2-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-2-git-send-email-sourav.poddar@ti.com>
Message-ID: <501C08CB.3060701@mvista.com>

Hello.

On 08/03/2012 04:38 PM, Sourav Poddar wrote:

> Add I2C data node in omap5 device tree file.

> Tested on omap5430 sdp.

> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  arch/arm/boot/dts/omap5.dtsi |   35 +++++++++++++++++++++++++++++++++++
>  1 files changed, 35 insertions(+), 0 deletions(-)

> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 57e5270..6b68dfe 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -145,6 +145,41 @@
>  			#interrupt-cells = <1>;
>  		};
>  
> +		i2c1: i2c at 48070000 {
> +			compatible = "ti,omap4-i2c";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			ti,hwmods = "i2c1";

   Address postfix in the node name and no "reg" property?

WBR, Sergei



From linux at arm.linux.org.uk  Fri Aug  3 13:40:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 Aug 2012 18:40:16 +0100
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
 <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>
Message-ID: <20120803174016.GE10335@n2100.arm.linux.org.uk>

On Fri, Aug 03, 2012 at 01:54:07PM -0300, Fabio Estevam wrote:
> On Fri, Aug 3, 2012 at 1:46 PM, Fabio Estevam <festevam at gmail.com> wrote:
> > Marek,
> >
> > On Fri, Aug 3, 2012 at 12:55 PM, Marek Vasut <marex at denx.de> wrote:
> >> Initially reported by Detlev Zundel <dzu at denx.de>, this caused breakage
> >> when "su - testuser" was called. "testuser" being a regular user account,
> >> the command ended with SIGKILL.
> >>
> >> Signed-off-by: Marek Vasut <marex at denx.de>
> >> Cc: Russell King <linux at arm.linux.org.uk>
> >> Cc: Shawn Guo <shawn.guo at linaro.org>
> >> Cc: Wolfgang Denk <wd at denx.de>
> >> ---
> >>  arch/arm/configs/mxs_defconfig |    2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
> >> index ccdb635..f212802 100644
> >> --- a/arch/arm/configs/mxs_defconfig
> >> +++ b/arch/arm/configs/mxs_defconfig
> >> @@ -34,7 +34,7 @@ CONFIG_NO_HZ=y
> >>  CONFIG_HIGH_RES_TIMERS=y
> >>  CONFIG_PREEMPT_VOLUNTARY=y
> >>  CONFIG_AEABI=y
> >> -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
> >> +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
> >
> > No need to set it to 32768.
> >
> > If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then this
> > symbol will be 32768.
> 
> Sorry, ignore what I said. I just realized that the default is 4096.

4096 is also fine for ARM too.  There's not much point in having
defconfigs change it - that would just be pure noise in the config
files.


From andi at firstfloor.org  Fri Aug  3 13:54:27 2012
From: andi at firstfloor.org (Andi Kleen)
Date: Fri, 03 Aug 2012 10:54:27 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com> (Vikram
 Pandita's message of "Fri, 3 Aug 2012 09:56:44 -0700")
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
Message-ID: <m2628z6euk.fsf@firstfloor.org>

Vikram Pandita <vikram.pandita at ti.com> writes:

> From: Vikram Pandita <vikram.pandita at ti.com>
>
> Introduce config option to enable CPU id reporting for printk() calls.

What's wrong with using trace_printk for this? That's much faster
anyways. Generally printk is so slow that it's typically useless for
instrumenting races.

And really: Wasting 1/3 of the 80 character line is too much.

-Andi

-- 
ak at linux.intel.com -- Speaking for myself only


From swarren at wwwdotorg.org  Fri Aug  3 14:01:40 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 03 Aug 2012 12:01:40 -0600
Subject: [PATCH] ARM: tegra: turn on UART A clock at boot
In-Reply-To: <1343170200-28228-1-git-send-email-swarren@wwwdotorg.org>
References: <1343170200-28228-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <501C1204.3010004@wwwdotorg.org>

On 07/24/2012 04:50 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Some boards use UART D for the main serial console, and some use UART A.
> UART D's clock is listed in board-dt-tegra20.c's clock table, whereas
> UART A's clock is not. This causes the clock code to think UART A's
> clock is unsed. The common clock framework turns off unused clocks at
> boot time. This makes the kernel appear to hang. Add UART A's clock into
> the clock table to prevent this. Eventually, this requirement should be
> handled by the UART driver, and/or properties in a board-specific device
> tree file.

Applied to for-3.7/common-clk.



From swarren at wwwdotorg.org  Fri Aug  3 14:01:51 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 03 Aug 2012 12:01:51 -0600
Subject: [PATCH] ARM: tegra: fix U16 divider range check
In-Reply-To: <1343170214-28262-1-git-send-email-swarren@wwwdotorg.org>
References: <1343170214-28262-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <501C120F.60404@wwwdotorg.org>

On 07/24/2012 04:50 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> A U16 divider can divide a clock by 1..64K. However, the range-check
> in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
> downstream kernels already have the fixed range-check.
> 
> In practice this is a problem on Whistler's I2C bus, which uses a bus
> clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
> which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
> leading to a desired divider of 270. Prior to conversion to the common
> clock framework, this range error was somehow ignored/irrelevant and
> caused no problems. However, the common clock framework evidently has
> more rigorous error-checking, so this failure causes the I2C bus to fail
> to operate correctly.

Applied to for-3.7/common-clk.



From swarren at wwwdotorg.org  Fri Aug  3 14:05:22 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 03 Aug 2012 12:05:22 -0600
Subject: [PATCH v3 12/32] PCI/ARM: use PCIe capabilities access functions
 to simplify implementation
In-Reply-To: <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>
References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
 <1343836477-7287-13-git-send-email-jiang.liu@huawei.com>
Message-ID: <501C12E2.3060807@wwwdotorg.org>

On 08/01/2012 09:54 AM, Jiang Liu wrote:
> From: Jiang Liu <jiang.liu at huawei.com>
> 
> Use PCIe capabilities access functions to simplify PCIe ARM implementation.
> 
> Signed-off-by: Jiang Liu <liuj97 at gmail.com>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From swarren at wwwdotorg.org  Fri Aug  3 14:08:50 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri,  3 Aug 2012 12:08:50 -0600
Subject: [PATCH V3] ARM: dt: tegra: seaboard: add regulators
Message-ID: <1344017330-29306-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Seaboard uses a TPS6586x regulator. Instantiate this, and hook up a
couple of fixed GPIO-controlled regulators too.

Two data sources were used for the data encoded here:
* The HW defaults, as extracted from real HW.
* The schematic, which specifies a voltage for each LDO rail.

In most cases these sources matched. The only differences is:

ldo6: The HW default on Springbank is 2.85v. The HW default on Seaboard
is 1.8v. The schematics for both Springbank and Seaboard match at 2.85v.
However, internal research indicates that the schematics are incorrectly
labelled, and 1.8v is correct. The ChromeOS kernel also uses 1.8v.

Note that these settings don't entirely match those in the ChromeOS
kernel found at the URL below. However, the selected values generally
cause no behavior change in the kernel, and so were picked to avoid
regressions.

repo http://git.chromium.org/chromiumos/third_party/kernel.git
branch chromeos-3.2
file arch/arm/mach-tegra/board-seaboard-power.c

Portions based on work by Laxman Dewangan <ldewangan at nvidia.com>

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v3:
* Switch back to simple-bus compatible value for the /regulators node.
* Added supply properties for all TPS6586x regulators.
* Made SM* children of the new SYS regulator.
* Removed ldo0 configuration, since it isn't used.
v2:
* Made all constraints match the HW defaults to avoid behavior changes,
  with exceptions noted above.
* Removed vin-supply properties from LDO nodes; the driver and binding
  need to be updated to support specifying the parent regulators before
  we can put these into DT.
* Use the enumerated-bus compatible value for the /regulators node.
* Enhanced all regulator-name properties to list all signal names directly
  derived from the regulator pins.
* Added ldo_rtc regulator.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra20-seaboard.dts |  184 ++++++++++++++++++++++++++++++++
 1 files changed, 184 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621a..92deb36 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,152 @@
 		status = "okay";
 		clock-frequency = <400000>;
 
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1125000>;
+					regulator-max-microvolt = <1125000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator at 7 {
+					reg = <7>;
+					regulator-compatible = "ldo3";
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
 		temperature-sensor at 4c {
 			compatible = "nct1008";
 			reg = <0x4c>;
@@ -387,6 +533,10 @@
 		};
 	};
 
+	pmc {
+		nvidia,invert-interrupt;
+	};
+
 	memory-controller at 0x7000f400 {
 		emc-table at 190000 {
 			reg = <190000>;
@@ -473,6 +623,40 @@
 		};
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 0>;
+		};
+
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 0>;
+			enable-active-high;
+		};
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-wm8903-seaboard",
 			     "nvidia,tegra-audio-wm8903";
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Aug  3 14:09:16 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri,  3 Aug 2012 12:09:16 -0600
Subject: [PATCH V3] ARM: dt: tegra: ventana: add regulators
Message-ID: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
couple of fixed GPIO-controlled regulators too.

The data was chosen to match the PMIC HW defaults, with the following
exception:

ldo6: The HW default is 2.85v. The schematics are unlabelled. Internal
research indicates that 1.8v is correct. Our downstream kernel also uses
1.8v.

Portions based on work by Laxman Dewangan <ldewangan at nvidia.com>

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v3:
* Switch back to simple-bus compatible value for the /regulators node.
* Added supply properties for all TPS6586x regulators.
* Made SM* children of the new SYS regulator.
* Removed ldo0 configuration, since it isn't used.
v2:
* Made all constraints match the HW defaults to avoid behavior changes,
  with exceptions noted above.
* Removed vin-supply properties from LDO nodes; the driver and binding
  need to be updated to support specifying the parent regulators before
  we can put these into DT.
* Rename vdd_pnl regulator-name to match schematic.
* Added vdd_bl regulator.
* Fix typo in regulator at 3 reg property.
* Use the enumerated-bus compatible value for the /regulators node.
* Enhanced all regulator-name properties to list all signal names directly
  derived from the regulator pins.
* Added ldo_rtc regulator.
---
 arch/arm/boot/dts/tegra20-ventana.dts |  204 +++++++++++++++++++++++++++++++++
 1 files changed, 204 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544..4ec6b4c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,156 @@
 	i2c at 7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;
+
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator at 7 {
+					reg = <7>;
+					regulator-compatible = "ldo3";
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
 	};
 
 	usb at c5000000 {
@@ -317,6 +467,60 @@
 		bus-width = <8>;
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 0>;
+		};
+
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 0>;
+			enable-active-high;
+		};
+
+		regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio 22 0>; /* gpio PC6 */
+			enable-active-high;
+		};
+
+		regulator at 4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio 176 0>; /* gpio PW0 */
+			enable-active-high;
+		};
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-wm8903-ventana",
 			     "nvidia,tegra-audio-wm8903";
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Aug  3 14:11:24 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri,  3 Aug 2012 12:11:24 -0600
Subject: [PATCH] ARM: dt: tegra: whistler: add regulators
Message-ID: <1344017484-29395-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Whistler uses a Maxim 8907 regulator. Instantiate this.

The voltage settings were derived from the schematic. The only exception
is the BBAT voltage; the schematic says 1.2v, but the HW can't go that
low, so use the HW default of 2.4v instead.

Almost all regulators list all driven supply signal names in their
regulator-names property. The exception is nvvdd_sv3, which is in turn
named 12 more different names on the schematic, so these were omitted
for brevity.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra20-whistler.dts |  294 ++++++++++++++++++++++++++++++++
 1 files changed, 294 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310..7338baa 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,285 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		max8907 at 3c {
+			compatible = "maxim,max8907";
+			reg = <0x3c>;
+			interrupts = <0 86 0x4>;
+
+			mbatt-supply = <&usb0_vbus_reg>;
+			in-v1-supply = <&mbatt_reg>;
+			in-v2-supply = <&mbatt_reg>;
+			in-v3-supply = <&mbatt_reg>;
+			in1-supply = <&mbatt_reg>;
+			in2-supply = <&nvvdd_sv3_reg>;
+			in3-supply = <&mbatt_reg>;
+			in4-supply = <&mbatt_reg>;
+			in5-supply = <&mbatt_reg>;
+			in6-supply = <&mbatt_reg>;
+			in7-supply = <&mbatt_reg>;
+			in8-supply = <&mbatt_reg>;
+			in9-supply = <&mbatt_reg>;
+			in10-supply = <&mbatt_reg>;
+			in11-supply = <&mbatt_reg>;
+			in12-supply = <&mbatt_reg>;
+			in13-supply = <&mbatt_reg>;
+			in14-supply = <&mbatt_reg>;
+			in15-supply = <&mbatt_reg>;
+			in16-supply = <&mbatt_reg>;
+			in17-supply = <&nvvdd_sv3_reg>;
+			in18-supply = <&nvvdd_sv3_reg>;
+			in19-supply = <&mbatt_reg>;
+			in20-supply = <&mbatt_reg>;
+			lxw-supply = <&mbatt_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mbatt_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "mbatt";
+					regulator-name = "vbat_pmu";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sd1";
+					regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sd2";
+					regulator-name = "nvvdd_sv2,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				nvvdd_sv3_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sd3";
+					regulator-name = "nvvdd_sv3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 4 {
+					reg = <4>;
+					regulator-compatible = "ldo1";
+					regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo2";
+					regulator-name = "nvvdd_ldo2,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo3";
+					regulator-name = "nvvdd_ldo3,vcom_1v8b";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 7 {
+					reg = <7>;
+					regulator-compatible = "ldo4";
+					regulator-name = "nvvdd_ldo4,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo5";
+					regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo6";
+					regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo7";
+					regulator-name = "nvvdd_ldo7,avddio_audio";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo8";
+					regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+				};
+
+				regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo9";
+					regulator-name = "nvvdd_ldo9,avdd_cam*";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo10";
+					regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo11";
+					regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 15 {
+					reg = <15>;
+					regulator-compatible = "ldo12";
+					regulator-name = "nvvdd_ldo12,vddio_sdio";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				regulator at 16 {
+					reg = <16>;
+					regulator-compatible = "ldo13";
+					regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				regulator at 17 {
+					reg = <17>;
+					regulator-compatible = "ldo14";
+					regulator-name = "nvvdd_ldo14,avdd_vdac";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				regulator at 18 {
+					reg = <18>;
+					regulator-compatible = "ldo15";
+					regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 19 {
+					reg = <19>;
+					regulator-compatible = "ldo16";
+					regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+				};
+
+				regulator at 20 {
+					reg = <20>;
+					regulator-compatible = "ldo17";
+					regulator-name = "nvvdd_ldo17,vddio_mipi";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator at 21 {
+					reg = <21>;
+					regulator-compatible = "ldo18";
+					regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 22 {
+					reg = <22>;
+					regulator-compatible = "ldo19";
+					regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				regulator at 23 {
+					reg = <23>;
+					regulator-compatible = "ldo20";
+					regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				regulator at 24 {
+					reg = <24>;
+					regulator-compatible = "out5v";
+					regulator-name = "usb0_vbus_reg";
+				};
+
+				regulator at 25 {
+					reg = <25>;
+					regulator-compatible = "out33v";
+					regulator-name = "pmu_out3v3";
+				};
+
+				regulator at 26 {
+					reg = <26>;
+					regulator-compatible = "bbat";
+					regulator-name = "pmu_bbat";
+					regulator-min-microvolt = <2400000>;
+					regulator-max-microvolt = <2400000>;
+					regulator-always-on;
+				};
+
+				regulator at 27 {
+					reg = <27>;
+					regulator-compatible = "sdby";
+					regulator-name = "vdd_aon";
+					regulator-always-on;
+				};
+
+				regulator at 28 {
+					reg = <28>;
+					regulator-compatible = "vrtc";
+					regulator-name = "vrtc,pmu_vccadc";
+					regulator-always-on;
+				};
+			};
+		};
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
 	};
 
 	usb at c5000000 {
@@ -284,6 +563,21 @@
 		bus-width = <8>;
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb0_vbus_reg: regulator {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-wm8753-whistler",
 			     "nvidia,tegra-audio-wm8753";
-- 
1.7.0.4



From fabio.estevam at freescale.com  Fri Aug  3 14:12:34 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 15:12:34 -0300
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Remove CONFIG_DEFAULT_MMAP_MIN_ADDR
Message-ID: <1344017554-4120-1-git-send-email-fabio.estevam@freescale.com>

By default CONFIG_DEFAULT_MMAP_MIN_ADDR is 4096 and can also be changed via
/proc/sys/vm/mmap_min_addr if needed.

Quoting Russell King (http://marc.info/?l=linux-arm-kernel&m=134401593807820&w=2):

"4096 is also fine for ARM too.  There's not much point in having
defconfigs change it - that would just be pure noise in the config
files."

,so remove CONFIG_DEFAULT_MMAP_MIN_ADDR from the defconfig file.
 
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/imx_v6_v7_defconfig |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f725b96..13bcfb1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -42,7 +42,6 @@ CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
-- 
1.7.1




From festevam at gmail.com  Fri Aug  3 14:23:49 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 3 Aug 2012 15:23:49 -0300
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <20120803174016.GE10335@n2100.arm.linux.org.uk>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5DZui3x554WcHsseSfXDgYeaq1va-QzVy1CQajE3M3=kQ@mail.gmail.com>
 <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>
 <20120803174016.GE10335@n2100.arm.linux.org.uk>
Message-ID: <CAOMZO5D=L=H6bnsoFcvedzdrdTGUFL2Ztyr4tLy9wbxpZ7a9ww@mail.gmail.com>

On Fri, Aug 3, 2012 at 2:40 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:

> 4096 is also fine for ARM too.  There's not much point in having
> defconfigs change it - that would just be pure noise in the config
> files.

Thanks for the clarification, Russell.

Marek, so maybe you can send a v2 of this patch with my previous
suggestion (and also mentioning the offending commit).

I have also removed CONFIG_DEFAULT_MMAP_MIN_ADDR from imx_v6_v7_defconfig.

Regards,

Fabio Estevam


From vikram.pandita at ti.com  Fri Aug  3 14:25:37 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 11:25:37 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <m2628z6euk.fsf@firstfloor.org>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
Message-ID: <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>

On Fri, Aug 3, 2012 at 10:54 AM, Andi Kleen <andi at firstfloor.org> wrote:
> Vikram Pandita <vikram.pandita at ti.com> writes:
>
>> From: Vikram Pandita <vikram.pandita at ti.com>
>>
>> Introduce config option to enable CPU id reporting for printk() calls.
>
> What's wrong with using trace_printk for this?

trace_printk works only when you know the _exact_ path in code that
you want to profile.
When you have no idea of a random lockup, then it would be kind of
touch and time consuming
to put trace prints all around the code.

> That's much faster
> anyways. Generally printk is so slow that it's typically useless for
> instrumenting races.
>

As stated in another thread, its found useful to debug some specific cases:
Check thread: http://marc.info/?l=linux-omap&m=134401269106619&w=2

> And really: Wasting 1/3 of the 80 character line is too much.

You _WASTE_ 4 chars only if you are interested in this info by
enabling: CONFIG_PRINTK_CPUID
Just like you _WASTE_ 15 chars when you enable existing: CONFIG_PRINTK_TIME

For general usecase, recommendation would be to keep these options disabled.
Working on shipping products, i find almost all shipping with
CONFIG_PRINTK_TIME enabled, so there must be some value.
Same would hold for the use case being debugged for CPUID enabling.

>
> -Andi
>
> --
> ak at linux.intel.com -- Speaking for myself only


From ldewangan at nvidia.com  Fri Aug  3 14:32:36 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Sat, 4 Aug 2012 00:02:36 +0530
Subject: [PATCH] ARM: dt: tegra: paz00: add regulators
In-Reply-To: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>
References: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <501C1944.4030505@nvidia.com>

On Friday 03 August 2012 12:06 AM, Stephen Warren wrote:
> From: Stephen Warren<swarren at nvidia.com>
>
> The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this.
>
> Three data sources were used for the data encoded here:
> * The HW defaults, as extracted from real HW.
> * The schematic, which specifies a voltage for each rail in the signal
>    names.
> * The AC100 kernel used by the Ubuntu port:
>
>    repo git://gitorious.org/~marvin24/ac100/marvin24s-kernel.git
>    branch chromeos-ac100-3.0
>    file arch/arm/mach-tegra/board-paz00-power.c
>
>    For many rails, the constraints in that tree specified differing min
>    and max voltages. In all cases, the min value was ignored, since
>    there's no need currently to vary any of the voltages at run-time.
>    DVFS might change this in the future.
>
> In most cases these sources all matched. Differences are:
>
> sm0: HW defaults and schematic match at 1.2v. marvin24's kernel had a max
> of 1.3v, but this higher voltage was only applied to HW by DVFS code,
> which isn't currently supported in mainline.
>
> sm1: HW defaults and schematic match at 1.0v. marvin24's kernel had a max
> of 1.125v, but this higher voltage was only applied to HW by DVFS code,
> which isn't currently supported in mainline.
>
> ldo3: The HW default is on. marvin24's kernel didn't specify always-on,
> but since the board wasn't marked as having fully constrained regulators,
> the rail was not turned off, so the difference had no effect. The rail
> is needed for USB.
>
> ldo6: The HW default is 2.85v. The schematics indicate 2.85v. However,
> since this regulator is used for the same purpose as on other boards that
> require 1.8v, this is set to 1.8v. Note that this regulator feeds the CRT
> VDAC on Tegra, and so in practice is unlikely to be used, even though it
> is actaully hooked up in HW.
>
> Portions based on work by Laxman Dewangan<ldewangan at nvidia.com>
>
> Signed-off-by: Stephen Warren<swarren at nvidia.com>
> Tested-by: Marc Dietrich<marvin24 at gmx.de>  # v2
> ---

Acked-by: Laxman Dewangan <ldewangan at nvidia.com>



>
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells =<1>;
> +		#size-cells =<0>;
> +

Is "simple-bus" accepted?
Accordingly I need to update for the Cardhu  also to have regulator 
support which I am going to send.



From marex at denx.de  Fri Aug  3 14:46:27 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 3 Aug 2012 20:46:27 +0200
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <20120803174016.GE10335@n2100.arm.linux.org.uk>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>
 <20120803174016.GE10335@n2100.arm.linux.org.uk>
Message-ID: <201208032046.28211.marex@denx.de>

Dear Russell King - ARM Linux,

[...]

> > > No need to set it to 32768.
> > > 
> > > If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then this
> > > symbol will be 32768.
> > 
> > Sorry, ignore what I said. I just realized that the default is 4096.
> 
> 4096 is also fine for ARM too.  There's not much point in having
> defconfigs change it - that would just be pure noise in the config
> files.

Wasn't there a security concern being the reason for setting this higher? Also, 
I still don't completely understand why ARM has to set it lower than others, is 
that an ABI thing?

Russell, do you happen to have some further reading for me I could study on this 
topic please?

Thanks!

Best regards,
Marek Vasut


From swarren at wwwdotorg.org  Fri Aug  3 14:49:12 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 03 Aug 2012 12:49:12 -0600
Subject: [PATCH] ARM: dt: tegra: paz00: add regulators
In-Reply-To: <501C1944.4030505@nvidia.com>
References: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>
 <501C1944.4030505@nvidia.com>
Message-ID: <501C1D28.60804@wwwdotorg.org>

On 08/03/2012 12:32 PM, Laxman Dewangan wrote:
> On Friday 03 August 2012 12:06 AM, Stephen Warren wrote:
>> From: Stephen Warren<swarren at nvidia.com>
>>
>> The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this.
...
> Acked-by: Laxman Dewangan <ldewangan at nvidia.com>

Thanks.

>> +    regulators {
>> +        compatible = "simple-bus";
>> +        #address-cells =<1>;
>> +        #size-cells =<0>;
>> +
> 
> Is "simple-bus" accepted?
> Accordingly I need to update for the Cardhu  also to have regulator
> support which I am going to send.

I believe so yes; the ability to use that bus type was the specific
purpose of:

https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-August/017963.html

... which Rob seems to find acceptable.


From marex at denx.de  Fri Aug  3 14:54:48 2012
From: marex at denx.de (Marek Vasut)
Date: Fri,  3 Aug 2012 20:54:48 +0200
Subject: [PATCH V2] MXS: Remove MMAP_MIN_ADDR setting from mxs_defconfig
Message-ID: <1344020088-8156-1-git-send-email-marex@denx.de>

The CONFIG_DEFAULT_MMAP_MIN_ADDR was set to 65536 in mxs_defconfig,
this caused severe breakage of userland applications since the upper
limit for ARM is 32768. By default CONFIG_DEFAULT_MMAP_MIN_ADDR is
set to 4096 and can also be changed via /proc/sys/vm/mmap_min_addr
if needed.

Quoting Russell King [1]:

"4096 is also fine for ARM too. There's not much point in having
defconfigs change it - that would just be pure noise in the config
files."

the CONFIG_DEFAULT_MMAP_MIN_ADDR can be removed from the defconfig
altogether.

This problem was introduced by:

commit cde7c41feaa06cb6bfc748b2fc3c7d809091c2b0
Author: Wolfram Sang <w.sang at pengutronix.de>
Date:   Fri Apr 29 15:06:40 2011 +0200

    ARM: configs: add defconfig for mach-mxs

[1] http://marc.info/?l=linux-arm-kernel&m=134401593807820&w=2

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Wolfgang Denk <wd at denx.de>
---
 arch/arm/configs/mxs_defconfig |    1 -
 1 file changed, 1 deletion(-)

V2: Remove the setting altogether
    Update description

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..4edcfb4 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -34,7 +34,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
-- 
1.7.10.4



From linux at arm.linux.org.uk  Fri Aug  3 15:06:40 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 3 Aug 2012 20:06:40 +0100
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <201208032046.28211.marex@denx.de>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <CAOMZO5AzaDcxJJV+Z-bHH58=xRq5RY6BanEjMd4uUhN+K9ZNZQ@mail.gmail.com>
 <20120803174016.GE10335@n2100.arm.linux.org.uk>
 <201208032046.28211.marex@denx.de>
Message-ID: <20120803190640.GF10335@n2100.arm.linux.org.uk>

On Fri, Aug 03, 2012 at 08:46:27PM +0200, Marek Vasut wrote:
> Dear Russell King - ARM Linux,
> 
> [...]
> 
> > > > No need to set it to 32768.
> > > > 
> > > > If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then this
> > > > symbol will be 32768.
> > > 
> > > Sorry, ignore what I said. I just realized that the default is 4096.
> > 
> > 4096 is also fine for ARM too.  There's not much point in having
> > defconfigs change it - that would just be pure noise in the config
> > files.
> 
> Wasn't there a security concern being the reason for setting this higher?

I don't believe there is.  The only requirement is that the first page
on older CPUs isn't stomped on (and we preserve that for later CPUs so
that NULL pointer derefs get caught.)

The higher it is the better though, because it means NULL pointer + offset
deref with larger offsets also gets caught.

> Also, 
> I still don't completely understand why ARM has to set it lower than
> others, is that an ABI thing?

Yes, we have always loaded user programs at 0x8000 by default, which are
generally not relocatable.  So if you set it to 64K, you prevent non-root
user programs being mapped in, which is why stuff gets killed as soon as
UID != 0.


From marex at denx.de  Fri Aug  3 15:08:06 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 3 Aug 2012 21:08:06 +0200
Subject: [PATCH] MXS: Fix mxs_defconfig MMAP_MIN_ADDR
In-Reply-To: <20120803190640.GF10335@n2100.arm.linux.org.uk>
References: <1344009354-13249-1-git-send-email-marex@denx.de>
 <201208032046.28211.marex@denx.de>
 <20120803190640.GF10335@n2100.arm.linux.org.uk>
Message-ID: <201208032108.06819.marex@denx.de>

Dear Russell King - ARM Linux,

> On Fri, Aug 03, 2012 at 08:46:27PM +0200, Marek Vasut wrote:
> > Dear Russell King - ARM Linux,
> > 
> > [...]
> > 
> > > > > No need to set it to 32768.
> > > > > 
> > > > > If you just remove the 'CONFIG_DEFAULT_MMAP_MIN_ADDR=65536' then
> > > > > this symbol will be 32768.
> > > > 
> > > > Sorry, ignore what I said. I just realized that the default is 4096.
> > > 
> > > 4096 is also fine for ARM too.  There's not much point in having
> > > defconfigs change it - that would just be pure noise in the config
> > > files.
> > 
> > Wasn't there a security concern being the reason for setting this higher?
> 
> I don't believe there is.  The only requirement is that the first page
> on older CPUs isn't stomped on (and we preserve that for later CPUs so
> that NULL pointer derefs get caught.)
> 
> The higher it is the better though, because it means NULL pointer + offset
> deref with larger offsets also gets caught.

Understood!

> > Also,
> > I still don't completely understand why ARM has to set it lower than
> > others, is that an ABI thing?
> 
> Yes, we have always loaded user programs at 0x8000 by default, which are
> generally not relocatable.  So if you set it to 64K, you prevent non-root
> user programs being mapped in, which is why stuff gets killed as soon as
> UID != 0.

I see! Thanks for explaining!

Best regards,
Marek Vasut


From paul at pwsan.com  Fri Aug  3 16:05:55 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 3 Aug 2012 14:05:55 -0600 (MDT)
Subject: DSS and USBHOST powerdomains not entering low-power states on 37xx EVM
Message-ID: <alpine.DEB.2.00.1208031355450.28888@utopia.booyaka.com>


Hi

On v3.6-rc1 on 37xx EVM, DSS and USBHOST powerdomains aren't entering 
low-power states.  Test log is below.


- Paul





Texas Instruments X-Loader 1.47 (Jan 14 2011 - 15:43:28)
Starting X-loader on MMC
Reading boot sector

212836 Bytes Read from MMC
Starting OS Bootloader from MMC...
Starting OS Bootloader...


U-Boot 2010.06 (Jan 14 2011 - 15:43:45)

OMAP34xx/35xx-GP ES2.1, CPU-OPP2 L3-165MHz
OMAP3 EVM board + LPDDR/NAND
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
In:    serial
Out:   serial
Err:   serial
Read back SMSC id 0x92200000
Die ID #368000229ff80000016071640902c013
Net:   smc911x-0
Hit any key to stop autoboot:  0 
smc911x: detected LAN9220 controller
smc911x: phy initialized
smc911x: MAC 00:50:c2:7e:99:42
BOOTP broadcast 1
DHCP client bound to address 192.168.57.131
Using smc911x-0 device
TFTP from server 192.168.57.1; our IP address is 192.168.57.131
Filename 'uImage.37xevm'.
Load address: 0x82000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ###################################################
done
Bytes transferred = 3254088 (31a748 hex)
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   Linux-3.6.0-rc1-00005-gacbfd56
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3254024 Bytes = 3.1 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0
[    0.000000] Linux version 3.6.0-rc1-00005-gacbfd56 (paul at nozomi) (gcc 
version 4.5.1 (Sourcery G++ Lite 2010.09-50) )
 #1 SMP Fri Aug 3 10:28:26 MDT 2012
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), 
cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing 
instruction cache
[    0.000000] Machine: OMAP3 EVM
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk )
[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
[    0.000000] PERCPU: Embedded 9 pages/cpu @c0e0d000 s12736 r8192 d15936 
u36864
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  
Total pages: 64768
[    0.000000] Kernel command line: console=ttyO0,115200n8 earlyprintk 
root=/dev/nfs nfsroot=192.168.57.1:/srv/nfs4/roo
tfs2 nfsrootdebug ip=dhcp init=/bin/sh
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 
bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 
bytes)
[    0.000000] Memory: 255MB = 255MB total
[    0.000000] Memory: 246492k/246492k available, 15652k reserved, 0K 
highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc05c6bbc   (5883 kB)
[    0.000000]       .init : 0xc05c7000 - 0xc06141c0   ( 309 kB)
[    0.000000]       .data : 0xc0616000 - 0xc06ae3e8   ( 609 kB)
[    0.000000]        .bss : 0xc06ae40c - 0xc0c06acc   (5474 kB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
[    0.000000] NR_IRQS:474
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 
interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps 
every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, 
Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.000946] Calibrating delay loop... 397.57 BogoMIPS (lpj=1554432)
[    0.109344] pid_max: default: 32768 minimum: 301
[    0.109924] Security Framework initialized
[    0.110137] Mount-cache hash table entries: 512
[    0.115661] CPU: Testing write buffer coherency: ok
[    0.116577] CPU0: thread -1, cpu 0, socket -1, mpidr 0
[    0.116668] Setting up static identity map for 0x8040c0d8 - 0x8040c148
[    0.119110] Brought up 1 CPUs
[    0.119140] SMP: Total of 1 processors activated (397.57 BogoMIPS).
[    0.142242] dummy: 
[    0.144622] NET: Registered protocol family 16
[    0.145507] DMA: preallocated 256 KiB pool for atomic coherent 
allocations
[    0.146545] GPMC revision 5.0
[    0.146789] gpmc: irq-20 could not claim: err -22
[    0.158538] OMAP GPIO hardware version 2.5
[    0.176635] omap_mux_init: Add partition: #1: core, flags: 0
[    0.193023] _omap_mux_get_by_name: Could not find signal 
uart4_rx.uart4_rx
[    0.202178] Reprogramming SDRC clock to 400000000 Hz
[    0.202209] dpll3_m2_clk rate change failed: -22
[    0.203704] Found NAND on CS0
[    0.203735] Registering NAND on CS0
[    0.205841] hw-breakpoint: debug architecture 0x4 unsupported.
[    0.223083]  omap-mcbsp.2: alias fck already exists
[    0.224029]  omap-mcbsp.3: alias fck already exists
[    0.229431] OMAP DMA hardware revision 5.0
[    0.300598] bio: create slab <bio-0> at 0
[    0.304412] fixed-dummy: 
[    0.311401] SCSI subsystem initialized
[    0.314483] usbcore: registered new interface driver usbfs
[    0.315124] usbcore: registered new interface driver hub
[    0.316009] usbcore: registered new device driver usb
[    0.318542] omap_i2c omap_i2c.1: bus 1 rev1.4.0 at 2600 kHz
[    0.330291] twl 1-0048: PIH (irq 7) chaining IRQs 320..328
[    0.330993] twl 1-0048: power (irq 325) chaining IRQs 328..335
[    0.333770] twl4030_gpio twl4030_gpio: gpio (irq 320) chaining IRQs 
336..353
[    0.346771] VIO: 1800 mV normal standby
[    0.349334] vdd_mpu_iva: 600 <--> 1450 mV normal 
[    0.352264] vdd_core: 600 <--> 1450 mV normal 
[    0.354705] VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
[    0.357757] VDAC: 1800 mV normal standby
[    0.360992] VAUX2_4030: 2800 mV normal standby
[    0.364135] VPLL2: 1800 mV normal standby
[    0.366851] VSIM: 1800 <--> 3000 mV at 1800 mV normal standby
[    0.383148] omap_i2c omap_i2c.2: bus 2 rev1.4.0 at 400 kHz
[    0.398590] omap_i2c omap_i2c.3: bus 3 rev1.4.0 at 400 kHz
[    0.408111] Switching to clocksource 32k_counter
[    0.534790] NET: Registered protocol family 2
[    0.537048] TCP established hash table entries: 8192 (order: 4, 65536 
bytes)
[    0.537567] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
[    0.542694] TCP: Hash tables configured (established 8192 bind 8192)
[    0.542907] TCP: reno registered
[    0.542938] UDP hash table entries: 256 (order: 2, 20480 bytes)
[    0.543273] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[    0.544342] NET: Registered protocol family 1
[    0.545806] RPC: Registered named UNIX socket transport module.
[    0.545837] RPC: Registered udp transport module.
[    0.545837] RPC: Registered tcp transport module.
[    0.545867] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.547119] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.741790] VFS: Disk quotas dquot_6.5.2
[    0.742156] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.744781] NFS: Registering the id_resolver key type
[    0.745330] Key type id_resolver registered
[    0.745361] Key type id_legacy registered
[    0.745544] jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, 
Inc.
[    0.746215] msgmni has been set to 481
[    0.750946] io scheduler noop registered
[    0.750976] io scheduler deadline registered
[    0.751068] io scheduler cfq registered (default)
[    0.754852] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.762573] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 72) is a OMAP 
UART0
[    1.425170] console [ttyO0] enabled
[    1.430816] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 73) is a OMAP 
UART1
[    1.440368] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 74) is a OMAP 
UART2
[    1.449676] omap_uart.3: ttyO3 at MMIO 0x49042000 (irq = 80) is a OMAP 
UART3
[    1.495605] brd: module loaded
[    1.521331] loop: module loaded
[    1.532928] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.540679] NAND device: Manufacturer ID: 0xad, Chip ID: 0xbc (Hynix 
NAND 512MiB 1,8V 16-bit), page size: 2048, OOB 
size: 64
[    1.552673] Creating 5 MTD partitions on "omap2-nand.0":
[    1.558349] 0x000000000000-0x000000080000 : "X-Loader"
[    1.571746] 0x000000080000-0x000000240000 : "U-Boot"
[    1.584289] 0x000000240000-0x000000280000 : "U-Boot Env"
[    1.595031] 0x000000280000-0x000000780000 : "Kernel"
[    1.609527] 0x000000780000-0x000020000000 : "File system"
[    2.060089] OneNAND driver initializing
[    2.068786] spi spi1.0: no RX DMA engine channel for McSPI
[    2.074890] omap2_mcspi omap2_mcspi.1: can't setup spi1.0, status -11
[    2.081787] omap2_mcspi omap2_mcspi.1: can't create new device for 
ads7846
[    2.098480] smsc911x: Driver version 2008-10-21
[    2.113037] libphy: smsc911x-mdio: probed
[    2.117523] smsc911x smsc911x.0: eth0: attached PHY driver [SMSC 
LAN8700] (mii_bus:phy_addr=smsc911x-0:01, irq=-1)
[    2.129089] smsc911x smsc911x.0: eth0: MAC Address: 00:50:c2:7e:99:42
[    2.137329] usbcore: registered new interface driver asix
[    2.143798] usbcore: registered new interface driver cdc_ether
[    2.150512] usbcore: registered new interface driver net1080
[    2.157257] usbcore: registered new interface driver cdc_subset
[    2.164245] usbcore: registered new interface driver zaurus
[    2.170898] usbcore: registered new interface driver cdc_ncm
[    2.179290] usbcore: registered new interface driver cdc_wdm
[    2.185394] Initializing USB Mass Storage driver...
[    2.191284] usbcore: registered new interface driver usb-storage
[    2.197631] USB Mass Storage support registered.
[    2.203887] usbcore: registered new interface driver libusual
[    2.210754] usbcore: registered new interface driver usbtest
[    2.218627] mousedev: PS/2 mouse device common for all mice
[    2.227325] input: TWL4030 Keypad as 
/devices/platform/omap_i2c.1/i2c-1/1-004a/twl4030_keypad/input/input0
[    2.245971] input: twl4030_pwrbutton as 
/devices/platform/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input1
[    2.259033] twl_rtc twl_rtc: Enabling TWL-RTC
[    2.268218] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
[    2.276367] i2c /dev entries driver
[    2.284240] Driver for 1-wire Dallas network protocol.
[    2.293426] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 
sec
[    2.302093] twl4030_wdt twl4030_wdt: Failed to register misc device
[    2.308898] twl4030_wdt: probe of twl4030_wdt failed with error -16
[    2.319854] omap_hsmmc omap_hsmmc.0: Failed to get debounce clk
[    2.326293] omap_hsmmc omap_hsmmc.0: unable to obtain RX DMA engine 
channel 62
[    2.336822] usbcore: registered new interface driver usbhid
[    2.352355] oprofile: using timer interrupt.
[    2.357788] TCP: cubic registered
[    2.361267] Initializing XFRM netlink socket
[    2.365997] NET: Registered protocol family 17
[    2.370880] NET: Registered protocol family 15
[    2.375976] Key type dns_resolver registered
[    2.380737] VFP support v0.3: implementor 41 architecture 3 part 30 
variant c rev 3
[    2.400665] ThumbEE CPU extension supported.
[    2.441802] clock: disabling unused clocks to save power
[    2.452972] VMMC1: incomplete constraints, leaving on
[    2.461303] twl_rtc twl_rtc: setting system clock to 2000-01-01 
00:43:40 UTC (946687420)
[    2.472717] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 
0xd085a000, IRQ: 272
[    2.979248] Sending DHCP requests .., OK
[    5.979644] IP-Config: Got DHCP answer from 0.0.0.0, my address is 
192.168.57.131
[    5.988281] IP-Config: Complete:
[    5.991699]      device=eth0, addr=192.168.57.131, mask=255.255.255.0, 
gw=255.255.255.255
[    6.000366]      host=192.168.57.131, domain=, nis-domain=(none)
[    6.006744]      bootserver=0.0.0.0, rootserver=192.168.57.1, rootpath=
[    6.042083] VFS: Mounted root (nfs filesystem) on device 0:11.
[    6.049072] Freeing init memory: 308K
/bin/sh: can't access tty; job control turned off
# mount -t sysfs none /sys
# mount -t debugfs none /debug
# 
# echo mem > /sys/power/state
[   35.068359] PM: Syncing filesystems ... done.
[   35.083038] Freezing user space processes ... (elapsed 0.00 seconds) 
done.
[   35.090698] Freezing remaining freezable tasks ... (elapsed 0.02 
seconds) done.
[   35.122833] Suspending console(s) (use no_console_suspend to debug)
[   35.144409] PM: suspend of devices complete after 11.260 msecs
[   35.147369] PM: late suspend of devices complete after 2.929 msecs
[   35.152465] PM: noirq suspend of devices complete after 5.096 msecs
[   35.152526] Disabling non-boot CPUs ...
[   36.958343] Successfully put all powerdomains to target state
[   36.960662] PM: noirq resume of devices complete after 2.166 msecs
[   36.964050] PM: early resume of devices complete after 1.892 msecs
[   36.973388] PM: resume of devices complete after 9.185 msecs
[   37.025207] Restarting tasks ... done.
# cat  /debug/pm_debug/count
usbhost_pwrdm 
(ON),OFF:0,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
sgx_pwrdm (OFF),OFF:1,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
core_pwrdm 
(ON),OFF:0,RET:1,INA:0,ON:2,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0
per_pwrdm (ON),OFF:0,RET:1,INA:0,ON:2,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
dss_pwrdm (ON),OFF:0,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
cam_pwrdm (RET),OFF:0,RET:1,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
neon_pwrdm (ON),OFF:0,RET:673,INA:0,ON:674,RET-LOGIC-OFF:0
mpu_pwrdm (ON),OFF:0,RET:673,INA:0,ON:674,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
iva2_pwrdm (RET),OFF:0,RET:1,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0,RET-MEMBANK3-OFF:0,RET-ME
MBANK4-OFF:0
usbhost_clkdm->usbhost_pwrdm (1)
sgx_clkdm->sgx_pwrdm (0)
per_clkdm->per_pwrdm (22)
cam_clkdm->cam_pwrdm (0)
dss_clkdm->dss_pwrdm (1)
d2d_clkdm->core_pwrdm (0)
iva2_clkdm->iva2_pwrdm (0)
mpu_clkdm->mpu_pwrdm (0)
core_l4_clkdm->core_pwrdm (24)
core_l3_clkdm->core_pwrdm (4)
neon_clkdm->neon_pwrdm (0)
# 

From aaro.koskinen at iki.fi  Fri Aug  3 16:08:22 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Fri, 3 Aug 2012 23:08:22 +0300
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
Message-ID: <20120803200822.GC731@harshnoise.musicnaut.iki.fi>

Hi,

On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
> > And really: Wasting 1/3 of the 80 character line is too much.
> 
> You _WASTE_ 4 chars only if you are interested in this info by
> enabling: CONFIG_PRINTK_CPUID

I guess you waste 4 + 3 chars? You could optimize the length by checking
CONFIG_NR_CPUS?

A.


From paul at pwsan.com  Fri Aug  3 16:20:07 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 3 Aug 2012 14:20:07 -0600 (MDT)
Subject: nfsroot problems with v3.6-rc1 on 37xx EVM and dynamic off-mode
Message-ID: <alpine.DEB.2.00.1208031340310.28888@utopia.booyaka.com>


NFS is broken on 37xx EVM with v3.6-rc1 after return from off-mode with 
dynamic idle.  System suspend ("echo mem > /sys/power/state") with 
off-mode enabled seems to work fine.

No obvious ideas here as to what could have broken this.  It worked in 
v3.5-rc2 + my omap_fixes_a_3.5rc at least:

http://www.pwsan.com/omap/bootlogs/20120617/omap_fixes_a_3.5rc__52a5ae406dadef781bfcf3a641dae2064e9697ff/37xxevm_bootlog.txt

After that, it's hard to tell when this problem started occurring, since 
CORE stopped entering low-power states on OMAP3 on >= v3.5-rc3.

Test log is below.


- Paul



Texas Instruments X-Loader 1.47 (Jan 14 2011 - 15:43:28)
Starting X-loader on MMC
Reading boot sector

212836 Bytes Read from MMC
Starting OS Bootloader from MMC...
Starting OS Bootloader...


U-Boot 2010.06 (Jan 14 2011 - 15:43:45)

OMAP34xx/35xx-GP ES2.1, CPU-OPP2 L3-165MHz
OMAP3 EVM board + LPDDR/NAND
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
In:    serial
Out:   serial
Err:   serial
Read back SMSC id 0x92200000
Die ID #368000229ff80000016071640902c013
Net:   smc911x-0
Hit any key to stop autoboot:  0 
smc911x: detected LAN9220 controller
smc911x: phy initialized
smc911x: MAC 00:50:c2:7e:99:42
BOOTP broadcast 1
DHCP client bound to address 192.168.57.131
Using smc911x-0 device
TFTP from server 192.168.57.1; our IP address is 192.168.57.131
Filename 'uImage.37xevm'.
Load address: 0x82000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ###################################################
done
Bytes transferred = 3254088 (31a748 hex)
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   Linux-3.6.0-rc1-00005-gacbfd56
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3254024 Bytes = 3.1 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
[    0.000000] Booting Linux on physical CPU 0
[    0.000000] Linux version 3.6.0-rc1-00005-gacbfd56 (paul at nozomi) (gcc 
version 4.5.1 (Sourcery G++ Lite 2010.09-50) )
 #1 SMP Fri Aug 3 10:28:26 MDT 2012
[    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), 
cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing 
instruction cache
[    0.000000] Machine: OMAP3 EVM
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] OMAP3630 ES1.2 (l2cache iva sgx neon isp 192mhz_clk )
[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
[    0.000000] PERCPU: Embedded 9 pages/cpu @c0e0d000 s12736 r8192 d15936 
u36864
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  
Total pages: 64768
[    0.000000] Kernel command line: console=ttyO0,115200n8 earlyprintk 
root=/dev/nfs nfsroot=192.168.57.1:/srv/nfs4/roo
tfs2 nfsrootdebug ip=dhcp init=/bin/sh
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 
bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 
bytes)
[    0.000000] Memory: 255MB = 255MB total
[    0.000000] Memory: 246492k/246492k available, 15652k reserved, 0K 
highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc05c6bbc   (5883 kB)
[    0.000000]       .init : 0xc05c7000 - 0xc06141c0   ( 309 kB)
[    0.000000]       .data : 0xc0616000 - 0xc06ae3e8   ( 609 kB)
[    0.000000]        .bss : 0xc06ae40c - 0xc0c06acc   (5474 kB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=1.
[    0.000000] NR_IRQS:474
[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 
interrupts
[    0.000000] Total of 96 interrupts on 1 active controller
[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps 
every 131071999ms
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, 
Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.000915] Calibrating delay loop... 397.57 BogoMIPS (lpj=1554432)
[    0.109344] pid_max: default: 32768 minimum: 301
[    0.109924] Security Framework initialized
[    0.110137] Mount-cache hash table entries: 512
[    0.115661] CPU: Testing write buffer coherency: ok
[    0.116577] CPU0: thread -1, cpu 0, socket -1, mpidr 0
[    0.116638] Setting up static identity map for 0x8040c0d8 - 0x8040c148
[    0.119110] Brought up 1 CPUs
[    0.119140] SMP: Total of 1 processors activated (397.57 BogoMIPS).
[    0.142211] dummy: 
[    0.144622] NET: Registered protocol family 16
[    0.145507] DMA: preallocated 256 KiB pool for atomic coherent 
allocations
[    0.146545] GPMC revision 5.0
[    0.146789] gpmc: irq-20 could not claim: err -22
[    0.158538] OMAP GPIO hardware version 2.5
[    0.176635] omap_mux_init: Add partition: #1: core, flags: 0
[    0.192993] _omap_mux_get_by_name: Could not find signal 
uart4_rx.uart4_rx
[    0.202178] Reprogramming SDRC clock to 400000000 Hz
[    0.202209] dpll3_m2_clk rate change failed: -22
[    0.203704] Found NAND on CS0
[    0.203704] Registering NAND on CS0
[    0.205810] hw-breakpoint: debug architecture 0x4 unsupported.
[    0.222991]  omap-mcbsp.2: alias fck already exists
[    0.223937]  omap-mcbsp.3: alias fck already exists
[    0.229370] OMAP DMA hardware revision 5.0
[    0.300506] bio: create slab <bio-0> at 0
[    0.304321] fixed-dummy: 
[    0.311279] SCSI subsystem initialized
[    0.314392] usbcore: registered new interface driver usbfs
[    0.315002] usbcore: registered new interface driver hub
[    0.315734] usbcore: registered new device driver usb
[    0.328735] omap_i2c omap_i2c.1: bus 1 rev1.4.0 at 2600 kHz
[    0.339294] twl 1-0048: PIH (irq 7) chaining IRQs 320..328
[    0.339996] twl 1-0048: power (irq 325) chaining IRQs 328..335
[    0.342773] twl4030_gpio twl4030_gpio: gpio (irq 320) chaining IRQs 
336..353
[    0.355865] VIO: 1800 mV normal standby
[    0.358428] vdd_mpu_iva: 600 <--> 1450 mV normal 
[    0.361389] vdd_core: 600 <--> 1450 mV normal 
[    0.363830] VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
[    0.366851] VDAC: 1800 mV normal standby
[    0.370178] VAUX2_4030: 2800 mV normal standby
[    0.373321] VPLL2: 1800 mV normal standby
[    0.376525] VSIM: 1800 <--> 3000 mV at 1800 mV normal standby
[    0.390838] omap_i2c omap_i2c.2: bus 2 rev1.4.0 at 400 kHz
[    0.406402] omap_i2c omap_i2c.3: bus 3 rev1.4.0 at 400 kHz
[    0.415954] Switching to clocksource 32k_counter
[    0.542602] NET: Registered protocol family 2
[    0.544891] TCP established hash table entries: 8192 (order: 4, 65536 
bytes)
[    0.545379] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
[    0.550506] TCP: Hash tables configured (established 8192 bind 8192)
[    0.550720] TCP: reno registered
[    0.550750] UDP hash table entries: 256 (order: 2, 20480 bytes)
[    0.551086] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[    0.552154] NET: Registered protocol family 1
[    0.553619] RPC: Registered named UNIX socket transport module.
[    0.553649] RPC: Registered udp transport module.
[    0.553649] RPC: Registered tcp transport module.
[    0.553680] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.554931] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.749359] VFS: Disk quotas dquot_6.5.2
[    0.749725] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.752044] NFS: Registering the id_resolver key type
[    0.752746] Key type id_resolver registered
[    0.752777] Key type id_legacy registered
[    0.752960] jffs2: version 2.2. (NAND) (SUMMARY)   2001-2006 Red Hat, 
Inc.
[    0.753662] msgmni has been set to 481
[    0.758728] io scheduler noop registered
[    0.758758] io scheduler deadline registered
[    0.758819] io scheduler cfq registered (default)
[    0.762573] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.770294] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 72) is a OMAP 
UART0
[    1.432830] console [ttyO0] enabled
[    1.438476] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 73) is a OMAP 
UART1
[    1.448181] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 74) is a OMAP 
UART2
[    1.457275] omap_uart.3: ttyO3 at MMIO 0x49042000 (irq = 80) is a OMAP 
UART3
[    1.503082] brd: module loaded
[    1.528717] loop: module loaded
[    1.540435] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.548156] NAND device: Manufacturer ID: 0xad, Chip ID: 0xbc (Hynix 
NAND 512MiB 1,8V 16-bit), page size: 2048, OOB 
size: 64
[    1.560150] Creating 5 MTD partitions on "omap2-nand.0":
[    1.565826] 0x000000000000-0x000000080000 : "X-Loader"
[    1.579254] 0x000000080000-0x000000240000 : "U-Boot"
[    1.591735] 0x000000240000-0x000000280000 : "U-Boot Env"
[    1.602478] 0x000000280000-0x000000780000 : "Kernel"
[    1.616943] 0x000000780000-0x000020000000 : "File system"
[    2.067474] OneNAND driver initializing
[    2.076110] spi spi1.0: no RX DMA engine channel for McSPI
[    2.082214] omap2_mcspi omap2_mcspi.1: can't setup spi1.0, status -11
[    2.089111] omap2_mcspi omap2_mcspi.1: can't create new device for 
ads7846
[    2.105773] smsc911x: Driver version 2008-10-21
[    2.120208] libphy: smsc911x-mdio: probed
[    2.124725] smsc911x smsc911x.0: eth0: attached PHY driver [SMSC 
LAN8700] (mii_bus:phy_addr=smsc911x-0:01, irq=-1)
[    2.150573] usbcore: registered new interface driver cdc_ether
[    2.157684] usbcore: registered new interface driver net1080
[    2.164428] usbcore: registered new interface driver cdc_subset
[    2.171447] usbcore: registered new interface driver zaurus
[    2.178070] usbcore: registered new interface driver cdc_ncm
[    2.186462] usbcore: registered new interface driver cdc_wdm
[    2.192596] Initializing USB Mass Storage driver...
[    2.198455] usbcore: registered new interface driver usb-storage
[    2.204803] USB Mass Storage support registered.
[    2.211059] usbcore: registered new interface driver libusual
[    2.217926] usbcore: registered new interface driver usbtest
[    2.225769] mousedev: PS/2 mouse device common for all mice
[    2.234466] input: TWL4030 Keypad as 
/devices/platform/omap_i2c.1/i2c-1/1-004a/twl4030_keypad/input/input0
[    2.253112] input: twl4030_pwrbutton as 
/devices/platform/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input1
[    2.266174] twl_rtc twl_rtc: Enabling TWL-RTC
[    2.275146] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
[    2.283325] i2c /dev entries driver
[    2.291229] Driver for 1-wire Dallas network protocol.
[    2.300628] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 
sec
[    2.309265] twl4030_wdt twl4030_wdt: Failed to register misc device
[    2.316101] twl4030_wdt: probe of twl4030_wdt failed with error -16
[    2.327056] omap_hsmmc omap_hsmmc.0: Failed to get debounce clk
[    2.333496] omap_hsmmc omap_hsmmc.0: unable to obtain RX DMA engine 
channel 62
[    2.343994] usbcore: registered new interface driver usbhid
[    2.350128] usbhid: USB HID core driver
[    2.354217] oprofile: hardware counters not available
[    2.359558] oprofile: using timer interrupt.
[    2.364959] TCP: cubic registered
[    2.368469] Initializing XFRM netlink socket
[    2.373199] NET: Registered protocol family 17
[    2.378082] NET: Registered protocol family 15
[    2.383178] Key type dns_resolver registered
[    2.387939] VFP support v0.3: implementor 41 architecture 3 part 30 
variant c rev 3
[    2.407867] ThumbEE CPU extension supported.
[    2.449066] clock: disabling unused clocks to save power
[    2.460235] VMMC1: incomplete constraints, leaving on
[    2.468933] twl_rtc twl_rtc: setting system clock to 2000-01-01 
00:18:45 UTC (946685925)
[    2.480316] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 
0xd085a000, IRQ: 272
[    2.987060] Sending DHCP requests ..., OK
[    8.823425] IP-Config: Got DHCP answer from 0.0.0.0, my address is 
192.168.57.131
[    8.832122] IP-Config: Complete:
[    8.835540]      device=eth0, addr=192.168.57.131, mask=255.255.255.0, 
gw=255.255.255.255
[    8.844238]      host=192.168.57.131, domain=, nis-domain=(none)
[    8.850616]      bootserver=0.0.0.0, rootserver=192.168.57.1, rootpath=
[    8.884765] VFS: Mounted root (nfs filesystem) on device 0:11.
[    8.891906] Freeing init memory: 308K
/bin/sh: can't access tty; job control turned off
# 
mount -t sysfs none # /sys
mount -t debugfs none /debug
#
echo 1 > /debug/pm_debug/enable_off_mode
#
     echo 1000 > 
/sys/devices/platform/omap_uart.0/power/autosuspend_delay_ms
echo 1000 > /sys/devices/platform/omap_uart.1/power/autosuspend_delay_ms
echo 1000 > /sys/devices/platform/omap_uart.2/power/autosuspend_delay_ms
echo 1000 > /sys/devices/platform/omap_uart.3/power/autosuspend_delay_ms
# # # # # # # # # 
#   cat /debug/pm_debug/count
[   64.363189] nfs: server 192.168.57.1 not responding, still trying




From swarren at wwwdotorg.org  Fri Aug  3 16:37:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 03 Aug 2012 14:37:18 -0600
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <501C367E.10808@wwwdotorg.org>

On 08/02/2012 09:39 AM, Uwe Kleine-K?nig wrote:
> This is mostly cut'n'paste from the imx51 pinctrl driver.

> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt

> +See below for available PIN_FUNC_ID for imx35:
> +# grep '   IMX_PIN_REG' drivers/pinctrl/pinctrl-imx35.c | awk '{ print NR-1 " " $8 }'

I'd remove that line from the document; the binding doc is supposed to
be OS-agnostic, and the file drivers/pinctrl/pinctrl-imx35.c probably
only exists in Linux.

> diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c

> +/*
> + * imx35 pinctrl driver.
> + *
> + * This driver was mostly copied from the imx51 pinctrl driver which has:
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro, Inc.
> + *
> + * Author: Dong Aisheng <dong.aisheng at linaro.org>

You're not going to add your (c)? Maybe since it's mostly just data it
doesn't matter.

> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */

Other than that this is basically just SoC data, so I'm not really
qualified to comment:-) So,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From vikram.pandita at ti.com  Fri Aug  3 17:24:20 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 14:24:20 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
Message-ID: <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>

Aaro

On Fri, Aug 3, 2012 at 1:08 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> Hi,
>
> On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
>> > And really: Wasting 1/3 of the 80 character line is too much.
>>
>> You _WASTE_ 4 chars only if you are interested in this info by
>> enabling: CONFIG_PRINTK_CPUID
>
> I guess you waste 4 + 3 chars? You could optimize the length by checking
> CONFIG_NR_CPUS?

Good point.
Looks there is a variable 'nr_cpu_ids' that could be used as well.

If there is general consensus that the patch can help the arm
community, and others in general,
this optimization should be easy to implement - saving few chars space
in each line of console output.

For now i will stick to this v3 version of path, unless you think otherwise.

>
> A.


From gregkh at linuxfoundation.org  Fri Aug  3 17:59:54 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Fri, 3 Aug 2012 14:59:54 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
Message-ID: <20120803215954.GA4489@kroah.com>

On Fri, Aug 03, 2012 at 02:24:20PM -0700, Pandita, Vikram wrote:
> Aaro
> 
> On Fri, Aug 3, 2012 at 1:08 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> > Hi,
> >
> > On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
> >> > And really: Wasting 1/3 of the 80 character line is too much.
> >>
> >> You _WASTE_ 4 chars only if you are interested in this info by
> >> enabling: CONFIG_PRINTK_CPUID
> >
> > I guess you waste 4 + 3 chars? You could optimize the length by checking
> > CONFIG_NR_CPUS?
> 
> Good point.
> Looks there is a variable 'nr_cpu_ids' that could be used as well.
> 
> If there is general consensus that the patch can help the arm
> community, and others in general,
> this optimization should be easy to implement - saving few chars space
> in each line of console output.
> 
> For now i will stick to this v3 version of path, unless you think otherwise.

I don't think is is something that anyone needs, and if you do, as
pointed out, you can use the trace function to make it happen.

Adding features are not "free", someone has to maintain them and all of
the other work involved with it.  So don't just think that because it is
hidden behind a config option, that it doesn't affect people.

greg k-h


From vikram.pandita at ti.com  Fri Aug  3 18:07:39 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 15:07:39 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <20120803215954.GA4489@kroah.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
Message-ID: <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>

On Fri, Aug 3, 2012 at 2:59 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Fri, Aug 03, 2012 at 02:24:20PM -0700, Pandita, Vikram wrote:
>> Aaro
>>
>> On Fri, Aug 3, 2012 at 1:08 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
>> > Hi,
>> >
>> > On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
>> >> > And really: Wasting 1/3 of the 80 character line is too much.
>> >>
>> >> You _WASTE_ 4 chars only if you are interested in this info by
>> >> enabling: CONFIG_PRINTK_CPUID
>> >
>> > I guess you waste 4 + 3 chars? You could optimize the length by checking
>> > CONFIG_NR_CPUS?
>>
>> Good point.
>> Looks there is a variable 'nr_cpu_ids' that could be used as well.
>>
>> If there is general consensus that the patch can help the arm
>> community, and others in general,
>> this optimization should be easy to implement - saving few chars space
>> in each line of console output.
>>
>> For now i will stick to this v3 version of path, unless you think otherwise.
>
> I don't think is is something that anyone needs, and if you do, as
> pointed out, you can use the trace function to make it happen.
>

This was something that got used internally and helped at times.
This attempt to give back to community, but i understand the rationale to go
with larger consensus.

At least the patch is out there in public for anyone to make use of.

> Adding features are not "free", someone has to maintain them and all of
> the other work involved with it.  So don't just think that because it is
> hidden behind a config option, that it doesn't affect people.

At least the v3 patch is a complete working implementation wrt
kernel/printk.c file
as it exists on linus tree master today.

Understand long term this does have maintenance overhead just like
printk_time does.

>
> greg k-h


From gregkh at linuxfoundation.org  Fri Aug  3 18:13:27 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Fri, 3 Aug 2012 15:13:27 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
Message-ID: <20120803221327.GA5102@kroah.com>

On Fri, Aug 03, 2012 at 03:07:39PM -0700, Pandita, Vikram wrote:
> On Fri, Aug 3, 2012 at 2:59 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> > On Fri, Aug 03, 2012 at 02:24:20PM -0700, Pandita, Vikram wrote:
> >> Aaro
> >>
> >> On Fri, Aug 3, 2012 at 1:08 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> >> > Hi,
> >> >
> >> > On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
> >> >> > And really: Wasting 1/3 of the 80 character line is too much.
> >> >>
> >> >> You _WASTE_ 4 chars only if you are interested in this info by
> >> >> enabling: CONFIG_PRINTK_CPUID
> >> >
> >> > I guess you waste 4 + 3 chars? You could optimize the length by checking
> >> > CONFIG_NR_CPUS?
> >>
> >> Good point.
> >> Looks there is a variable 'nr_cpu_ids' that could be used as well.
> >>
> >> If there is general consensus that the patch can help the arm
> >> community, and others in general,
> >> this optimization should be easy to implement - saving few chars space
> >> in each line of console output.
> >>
> >> For now i will stick to this v3 version of path, unless you think otherwise.
> >
> > I don't think is is something that anyone needs, and if you do, as
> > pointed out, you can use the trace function to make it happen.
> >
> 
> This was something that got used internally and helped at times.

Could you have used the trace point instead?

greg k-h


From vikram.pandita at ti.com  Fri Aug  3 18:25:17 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 15:25:17 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <20120803221327.GA5102@kroah.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
 <20120803221327.GA5102@kroah.com>
Message-ID: <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>

On Fri, Aug 3, 2012 at 3:13 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Fri, Aug 03, 2012 at 03:07:39PM -0700, Pandita, Vikram wrote:
>> On Fri, Aug 3, 2012 at 2:59 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
>> > On Fri, Aug 03, 2012 at 02:24:20PM -0700, Pandita, Vikram wrote:
>> >> Aaro
>> >>
>> >> On Fri, Aug 3, 2012 at 1:08 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
>> >> > Hi,
>> >> >
>> >> > On Fri, Aug 03, 2012 at 11:25:37AM -0700, Pandita, Vikram wrote:
>> >> >> > And really: Wasting 1/3 of the 80 character line is too much.
>> >> >>
>> >> >> You _WASTE_ 4 chars only if you are interested in this info by
>> >> >> enabling: CONFIG_PRINTK_CPUID
>> >> >
>> >> > I guess you waste 4 + 3 chars? You could optimize the length by checking
>> >> > CONFIG_NR_CPUS?
>> >>
>> >> Good point.
>> >> Looks there is a variable 'nr_cpu_ids' that could be used as well.
>> >>
>> >> If there is general consensus that the patch can help the arm
>> >> community, and others in general,
>> >> this optimization should be easy to implement - saving few chars space
>> >> in each line of console output.
>> >>
>> >> For now i will stick to this v3 version of path, unless you think otherwise.
>> >
>> > I don't think is is something that anyone needs, and if you do, as
>> > pointed out, you can use the trace function to make it happen.
>> >
>>
>> This was something that got used internally and helped at times.
>
> Could you have used the trace point instead?

As i understood the trace_prink(), one would need to modify existing
printk -> trace_printk. Is my understanding correct?

Most of the times the problem exhibits as a random hang, without having a clue
which code to modify. That time one generic defconfig global switch is
your first tool.

Other issue i found, using this patch, that on multi-core ARM systems,
almost 99% of times, IRQ's are handled by CPU0,
even if CPU0 was really busy and other CPU's were free. I am yet to
understand a good reason why.

this patch also helped in other areas as mentioned in the thread
http://marc.info/?l=linux-omap&m=134401269106619&w=2

Not sure how easy its to use trace_printk for such issues, i found
having one defconfig option was much easier
to get going. Correct me if i have not understood trace_printk well enough.


>
> greg k-h


From gregkh at linuxfoundation.org  Fri Aug  3 18:36:23 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Fri, 3 Aug 2012 15:36:23 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
 <20120803221327.GA5102@kroah.com>
 <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
Message-ID: <20120803223623.GB6156@kroah.com>

On Fri, Aug 03, 2012 at 03:25:17PM -0700, Pandita, Vikram wrote:
> >> This was something that got used internally and helped at times.
> >
> > Could you have used the trace point instead?
> 
> As i understood the trace_prink(), one would need to modify existing
> printk -> trace_printk. Is my understanding correct?

No, you should just be able to watch the tracepoint, right?

> Most of the times the problem exhibits as a random hang, without having a clue
> which code to modify. That time one generic defconfig global switch is
> your first tool.
> 
> Other issue i found, using this patch, that on multi-core ARM systems,
> almost 99% of times, IRQ's are handled by CPU0,
> even if CPU0 was really busy and other CPU's were free. I am yet to
> understand a good reason why.

Can't you see that from /proc/interrupts today?

> this patch also helped in other areas as mentioned in the thread
> http://marc.info/?l=linux-omap&m=134401269106619&w=2

I still don't understand how adding the cpu number to printk enabled you
to find any problem like this.  Can't you just add the cpu number to the
printk messages you care about for your specific hardware?

greg k-h


From sboyd at codeaurora.org  Fri Aug  3 18:42:42 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri,  3 Aug 2012 15:42:42 -0700
Subject: [PATCH] ARM: Don't enable GENERIC_LOCKBREAK with ticket spinlocks
Message-ID: <1344033762-3296-1-git-send-email-sboyd@codeaurora.org>

Now that ARM has implemented its spinlocks with tickets we don't
need to use the generic lockbreak algorithm. Remove the Kconfig
from ARM so that we use the arch_spin_is_contended() definition
from the asm header. This also saves a word in each lock because
we don't need the break_lock member anymore.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

It seems we define the arch_spin_is_contended() macro but we don't
use it on SMP && PREEMPT kernels?

 arch/arm/Kconfig | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..e4191cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -126,11 +126,6 @@ config TRACE_IRQFLAGS_SUPPORT
 	bool
 	default y
 
-config GENERIC_LOCKBREAK
-	bool
-	default y
-	depends on SMP && PREEMPT
-
 config RWSEM_GENERIC_SPINLOCK
 	bool
 	default y
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From vikram.pandita at ti.com  Fri Aug  3 18:48:26 2012
From: vikram.pandita at ti.com (Pandita, Vikram)
Date: Fri, 3 Aug 2012 15:48:26 -0700
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <20120803223623.GB6156@kroah.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
 <20120803221327.GA5102@kroah.com>
 <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
 <20120803223623.GB6156@kroah.com>
Message-ID: <CAFm5wm1SSmbdi09hc1Qo1eHw5Tc0vbMf1hWuNw-cjZEEx3jX5w@mail.gmail.com>

On Fri, Aug 3, 2012 at 3:36 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Fri, Aug 03, 2012 at 03:25:17PM -0700, Pandita, Vikram wrote:
>> >> This was something that got used internally and helped at times.
>> >
>> > Could you have used the trace point instead?
>>
>> As i understood the trace_prink(), one would need to modify existing
>> printk -> trace_printk. Is my understanding correct?
>
> No, you should just be able to watch the tracepoint, right?

yes.
Assumption being you know _EXACTLY_ what code piece to watch for.
Which may not be the case all times.

>
>> Most of the times the problem exhibits as a random hang, without having a clue
>> which code to modify. That time one generic defconfig global switch is
>> your first tool.
>>
>> Other issue i found, using this patch, that on multi-core ARM systems,
>> almost 99% of times, IRQ's are handled by CPU0,
>> even if CPU0 was really busy and other CPU's were free. I am yet to
>> understand a good reason why.
>
> Can't you see that from /proc/interrupts today?

You are right that was the next step i did and that shows the problem as well.
The point i was trying to make, with printk showing cpu-id, there are
problems in system that could get highlighted,
given printk almost always runs with linux kernel.

>
>> this patch also helped in other areas as mentioned in the thread
>> http://marc.info/?l=linux-omap&m=134401269106619&w=2
>
> I still don't understand how adding the cpu number to printk enabled you
> to find any problem like this.  Can't you just add the cpu number to the
> printk messages you care about for your specific hardware?
>

The assumption here is that a developer knows well enough, which code
to modify for logging.
I my experience, that is not true most of the times. A global
defconfig switch is much easier to enable.

Eg: when i have some timing related issue, first thing i go for is to
enable PRINTK_TIME, without even
having to think about the erring code. Then time-stamps lead to bad code.

That is the same though process behind the cpu-id in printk.


> greg k-h


From sboyd at codeaurora.org  Fri Aug  3 19:02:57 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri,  3 Aug 2012 16:02:57 -0700
Subject: [PATCH/TRIVIAL] ARM: Drop duplicate select for GENERIC_IRQ_PROBE
Message-ID: <1344034977-6105-1-git-send-email-sboyd@codeaurora.org>

Seems that Thomas' and my patches collided during the last merge
window.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..b528d04 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -38,7 +38,6 @@ config ARM
 	select HARDIRQS_SW_RESEND
 	select GENERIC_IRQ_PROBE
 	select GENERIC_IRQ_SHOW
-	select GENERIC_IRQ_PROBE
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select HARDIRQS_SW_RESEND
 	select CPU_PM if (SUSPEND || CPU_IDLE)
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From swarren at wwwdotorg.org  Fri Aug  3 19:45:21 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri,  3 Aug 2012 17:45:21 -0600
Subject: [PATCH] ARM: tegra: more regulator fixes for Harmony
Message-ID: <1344037521-6157-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Commit 3d55c29 "ARM: tegra: harmony: add regulator supply name and its
input supply" was supposed to fix all the problems with regulators on
Harmony. However, it appears that I only tested it when booting using
board files, not when booting using device tree. This change fixes two
problems with regulators when booting using device tree:

1) That patch only created the vdd_sys regulator when booting using a
   board file. Since this is the root of the whole regulator tree, this
   caused no regulators to successfully initialize when booting using
   device tree. The registration of vdd_sys is moved to fix this.

2) When booting use DT, the regulator core sets has_full_constraints,
   which in turn causes the core to turn off any regulators not marked
   as always on. Some of the affected regulators are required for basic
   system operation. To solve this, add always on constraints to all
   relevant regulators. This doesn't affect booting using a board file
   since nothing sets has_full_constraints in that case.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
This is a fix for v3.6.

I wrote and tested this patch on top of v3.6-rc1, and also tested it with
both next-20120803 and next-20120803 plus a bunch of local patches.

 arch/arm/mach-tegra/board-harmony-power.c |   32 +++++++++++++++-------------
 1 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 8fd387b..b7344be 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -51,7 +51,7 @@ static struct regulator_init_data ldo0_data = {
 	.consumer_supplies = tps658621_ldo0_supply,
 };
 
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv)	\
+#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
 	static struct regulator_init_data _id##_data = {		\
 		.supply_regulator = _supply,				\
 		.constraints = {					\
@@ -63,21 +63,22 @@ static struct regulator_init_data ldo0_data = {
 			.valid_ops_mask = (REGULATOR_CHANGE_MODE |	\
 					   REGULATOR_CHANGE_STATUS |	\
 					   REGULATOR_CHANGE_VOLTAGE),	\
+			.always_on = _on,				\
 		},							\
 	}
 
-HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500);
-HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500);
-HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,	    1250, 3300);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300);
+HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
+HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
+HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
+HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
+HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,	    1250, 3300, 1);
+HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
 
 #define TPS_REG(_id, _data)			\
 	{					\
@@ -119,9 +120,10 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 
 int __init harmony_regulator_init(void)
 {
+	regulator_register_always_on(0, "vdd_sys",
+		NULL, 0, 5000000);
+
 	if (machine_is_harmony()) {
-		regulator_register_always_on(0, "vdd_sys",
-			NULL, 0, 5000000);
 		i2c_register_board_info(3, harmony_regulators, 1);
 	} else { /* Harmony, booted using device tree */
 		struct device_node *np;
-- 
1.7.0.4



From cjb at laptop.org  Fri Aug  3 19:52:51 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 03 Aug 2012 19:52:51 -0400
Subject: [PATCH v3 2/9] MMC: pxa-mci: add DT bindings
In-Reply-To: <1343470061-16879-3-git-send-email-zonque@gmail.com> (Daniel
 Mack's message of "Sat, 28 Jul 2012 12:07:34 +0200")
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-3-git-send-email-zonque@gmail.com>
Message-ID: <87k3xf354c.fsf@octavius.laptop.org>

Hi,

On Sat, Jul 28 2012, Daniel Mack wrote:
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Chris Ball <cjb at laptop.org>
> ---
>  Documentation/devicetree/bindings/mmc/pxa-mmc.txt | 25 +++++++++++
>  drivers/mmc/host/pxamci.c                         | 52 +++++++++++++++++++++++
>  2 files changed, 77 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/pxa-mmc.txt

Mind if I merge this via the MMC tree?  I prefer to take MMC patches
there, and it doesn't look like there are any dependencies involved.
I've pushed it to mmc-next now.

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From broonie at opensource.wolfsonmicro.com  Fri Aug  3 20:48:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 4 Aug 2012 01:48:28 +0100
Subject: [alsa-devel] [PATCH 1/6] ASoC: dapm: If one widget fails, do not
 force all subsequent widgets to fail too
In-Reply-To: <20120803083009.GC7416@gmail.com>
References: <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <50193428.5000708@linaro.org>
 <20120801160824.GB11892@opensource.wolfsonmicro.com>
 <20120801194134.GA4103@sirena.org.uk>
 <20120802074517.GA19231@gmail.com>
 <20120802175604.GF4537@opensource.wolfsonmicro.com>
 <20120803083009.GC7416@gmail.com>
Message-ID: <20120804004821.GG4515@opensource.wolfsonmicro.com>

On Fri, Aug 03, 2012 at 09:30:10AM +0100, Lee Jones wrote:

> I do agree that it should be correct, but the difference between getting
> it 90% correct and absolutely perfect increases the effort at least x2.
> With so much left to do, I think it would be better to get everything in
> and functioning, then fix the minor issues as we come across them later.

If you're going to do this the usual way is to do it by leaving bits
out, and see below.

> If only it were that easy. We're not bursting at the seems with resources
> here. I'm working in a very customer focused ecosystem. If they don't 
> request it, or file a bug about it, there's no resource allocation to fix

Right, I work in the same industry - but this shouldn't be a problem,
if it's not urgent for people to help it's probably not urgent to do
whatever's blocked by it either.

> > You're not telling us about the problems you see so it's very difficult
> > for anyone to help you.

> > For example with this patch the only information you've sent is the
> > patch and the fact that you're seeing the error you're ignoring going
> > off on the system you're working with (which I had to ask to find out

> I only went off what I knew. Some objects (which wouldn't have
> prevented playing audio) were failing. It seemed wrong to shut down the
> entire audio system because for instance, 'headset mute' or the 'vibrator'
> links were broken. As I said to you before, time is a big factor and I
> have a massive TODO list. Fixing audio links a) isn't my subject of

This isn't the point, and it's a *very* important point which is the
main reason I'm replying here.

The immediate point here is that you're not communicating about what
you're trying to which is the source of a lot of problems.  Things would
run a lot more smoothly if when you try to cut corners you were explicit
about the corners you cut, and if when you run into problems you report
those problems as well as sending whatever code you're using to work
around things.  Set people's expecations about what they're seeing and
provide them with context.

Consider the patch that's in the subject line here - it took me a couple
of goes before you even said you'd seen an issue on your system which
you were working around (I still don't know what the actual errors are).
As far as I could tell looking at the patch description it was something
done for taste reasons which was being sent as a bug fix.

The usual approach for things like this is a changelog or cover mail
which says something like "I'm seeing this error, here's the code I'm
using to get things working on my system and I think this is a good idea
because..." (or "...but that can't be right", or whatever).  This works
a whole lot better, it makes it clear what the underlying motivation for
the change is and understand the submitter's expecation for the quality
of the patch.

Similarly with the missing device tree binding documentation, had you
said something about the patches not being complete and writing the
binding documentation later that'd have helped a lot.  Having it there
is a basic checklist thing for new DT bindings which is easy to spot
from a diffstat, it's really not something a reviewer should ever need
to ask about especially from someone doing a lot of DT work and it's a
big red flag for the quality of the code.

Things like this are really important, especially for people doing lots
of work, as they have such a big impact on communication and so much of
what makes this thing tick is about communication.

> expertise, so it would take me much longer to fix than someone with
> a good knowledge of the system and b) isn't really my responsibility.

That's fine, just tell people about the problem and move on to
something else from what's probably a large task list if it's blocking
you (and start nagging people if it doesn't get fixed and it seems
important).  This happens fairly often, it works well most of the time.
Sending a fix is of course ideal but it's not essential.

> Well I know my submissions are not always 100% perfect, but I hope 
> you're not implying that they're poor quality. Writing code and fixing
> things you view as bugs in code you have no prior knowledge of isn't the 

This is process stuff more than code stuff, it's all about communication.

> easiest task in the world. All I can do is attempt to fix the issues that
> I see, which get things off the ground or make drivers work again and
> submit the changes. If they're wrong they're wrong, but I don't think this
> should be viewed as poor quality code!

What you can do here is to commmunicate about what you're doing more.
Don't just think about the code, think about the communication
surrounding the code - this is the core of the issue.

> the experience. Some Maintainers say things like, "That's wrong. This
> is wrong. Why are you doing this?" etc without explaining what the
> issues are. That's not a good review, and will put people off trying
> again.

Like I said in my previous mail this is one of the tools people have
available to them to drive up quality - if you watch a bit more closely
you'll often see that the quality of the review is scaled to factors in
the submission (and often the pattern of submissions from a contributor).
It's often not something that's done conciously, a lot of this is just
people conveying that they're annoyed.

>        Equally being too overzealous and nit-picky about stuff that a)
> really doesn't matter or b) can be changed really easily _if_ in the
> rare case there's an issue. I've also submitted to some Maintainers

This is a similar thing - it's part of the toolbox.

> who are a pleasure to work with. They explain what's wrong and why
> and encourage resubmission. I know Maintainers aren't school teachers,
> or life coaches, but they should be encouraging more people to share
> their good ( after some fixup ;) ) code and not playing the role of 
> an incredibly hard to please boss, or impenetrable brick wall.

Maintainer bandwidth is limited, and people will focus these efforts
where they think it'd be useful.  What I'm spending time doing here is
trying to convey that there's some fairly easily solvable process issues
here which are making everyone's life harder here.


From haojian.zhuang at gmail.com  Fri Aug  3 21:30:42 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sat, 4 Aug 2012 09:30:42 +0800
Subject: [PATCH v3 2/9] MMC: pxa-mci: add DT bindings
In-Reply-To: <87k3xf354c.fsf@octavius.laptop.org>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-3-git-send-email-zonque@gmail.com>
 <87k3xf354c.fsf@octavius.laptop.org>
Message-ID: <CAN1soZxwBh4wR5C-x0bsj5U_wY6gF50uo=xo5HADS+PuXptCXA@mail.gmail.com>

On Sat, Aug 4, 2012 at 7:52 AM, Chris Ball <cjb at laptop.org> wrote:
> Hi,
>
> On Sat, Jul 28 2012, Daniel Mack wrote:
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>> Cc: Nicolas Pitre <nico at fluxnic.net>
>> Cc: Chris Ball <cjb at laptop.org>
>> ---
>>  Documentation/devicetree/bindings/mmc/pxa-mmc.txt | 25 +++++++++++
>>  drivers/mmc/host/pxamci.c                         | 52 +++++++++++++++++++++++
>>  2 files changed, 77 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/mmc/pxa-mmc.txt
>
> Mind if I merge this via the MMC tree?  I prefer to take MMC patches
> there, and it doesn't look like there are any dependencies involved.
> I've pushed it to mmc-next now.
>

There's no problem of your merging. I'll revert it in pxa git tree.

Regards
Haojian


From haojian.zhuang at gmail.com  Sat Aug  4 00:13:13 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sat, 4 Aug 2012 12:13:13 +0800
Subject: [PATCH 6/7] arm: mmp&dove: modify tauros2_init call
In-Reply-To: <501786AB.5010608@free-electrons.com>
References: <20120731070153.GA13777@lunn.ch>
 <CADApbehptEE++NoxBmTuPmbWY7q9Je_vXPxMv3Sq86_f_SpBCg@mail.gmail.com>
 <501786AB.5010608@free-electrons.com>
Message-ID: <CAN1soZxrxgarm2yF1WMuapvNN-1Vh8PXW7_RVpGVByKhX96QEg@mail.gmail.com>

On Tue, Jul 31, 2012 at 3:18 PM, Gregory CLEMENT
<gregory.clement at free-electrons.com> wrote:
> On 07/31/2012 09:09 AM, Chao Xie wrote:
>> On Tue, Jul 31, 2012 at 3:01 PM, Andrew Lunn <andrew at lunn.ch> wrote:
>>> Hi Chao
>>>
>>> When making changes to Dove, or any other Orion system, please could
>>> you CC: the orion maintainers:
>>>
>>> ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
>>> M:      Jason Cooper <jason at lakedaemon.net>
>>> M:      Andrew Lunn <andrew at lunn.ch>
>>> L:      linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>>> S:      Maintained
>>> F:      arch/arm/mach-dove/
>>> F:      arch/arm/mach-kirkwood/
>>> F:      arch/arm/mach-mv78xx0/
>>> F:      arch/arm/mach-orion5x/
>>> F:      arch/arm/plat-orion/
>>>
>>> Does this also affect Armada 370 and Armada XP SOC? I've no idea what
>>> cache it uses.
>>>
>>> Thanks
>>>         Andrew
>> It will impact Armada 370. The patch will make the user has choice to
>> enable extra features of tauros2
>
> As far as I know it wouldn't impact the Armada370 as it use an other L2
> called Aurora. We are currently working on it to submit it really soon.
> The ArmadaXP also use the Aurora L2 cache controller.
>
OK. I'll merge these patches.

Regards
Haojian


From bp at alien8.de  Sat Aug  4 01:16:08 2012
From: bp at alien8.de (Borislav Petkov)
Date: Sat, 4 Aug 2012 07:16:08 +0200
Subject: [PATCH v2] printk: add option to print cpu id
In-Reply-To: <CAFm5wm0rsvuBafMH+9PpKwfaBimbRrVzxYV0nD_pg1yisAYwxQ@mail.gmail.com>
References: <1343985378-22330-1-git-send-email-vikram.pandita@ti.com>
 <D958900912E20642BCBC71664EFECE3E6DDCAC49AB@BGMAIL02.nvidia.com>
 <D958900912E20642BCBC71664EFECE3E6DDCAC49AE@BGMAIL02.nvidia.com>
 <CAFm5wm2Z+FyVqG5oMWiEmZ8Je88hJ-cyDXmJw0wp4mqA-X9eYg@mail.gmail.com>
 <CAPXgP13UBwQLs+m_aSk3Ljbktz8WrL+ZO_Tfhrt_+tRBCARyQQ@mail.gmail.com>
 <CAFm5wm0nf47bcTu7iiXA3geR_5dDTF1tnf81Lz7JzbWkKdhUtA@mail.gmail.com>
 <CAPXgP11A=QfOt4SL2GvhsepP8JiDFfdaAhi6-AhW++-AvOz+aw@mail.gmail.com>
 <20120803104212.GA6936@x1.osrc.amd.com>
 <CAFm5wm0rsvuBafMH+9PpKwfaBimbRrVzxYV0nD_pg1yisAYwxQ@mail.gmail.com>
Message-ID: <20120804051608.GB6728@liondog.tnic>

On Fri, Aug 03, 2012 at 09:46:15AM -0700, Pandita, Vikram wrote:
> I mostly work with ARM Soc - specifically on OMAP. SMP multi core
> systems in ARM-v7 world started to show up only few years back -
> unlike x86 world.

This is exactly the thing: other SMP vendors have made it so far without
emitting which core is doing what in dmesg.

> ARM systems are a bit unique when it comes to security( read trust
> zone ), and handling of FIQ's. Most of the ARM cortex-A series SoC's
> out there have some kind of affinity to CPU0 being the master. One use
> case has been, it has helped to know with this printk logging, if such
> constraints are honored.
>
> Sometimes, tracking of some lockup cases between cpu's because of bad
> code has also been helpful with this logging support. For now i will
> post v3 of the patch and add arm-list and linux-omap list, and there
> might be users there can benefit.

Right, so if arm people need this thing, why not make it arm-only? I
still fail to see the need for this (... at all, actually).

Thanks.

-- 
Regards/Gruss,
    Boris.


From nicolas.pitre at linaro.org  Sat Aug  4 01:38:29 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 01:38:29 -0400 (EDT)
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <1343775898-28345-2-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040045360.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> The original phys_to_virt/virt_to_phys patching implementation relied on early
> patching prior to MMU initialization.  On PAE systems running out of >4G
> address space, this would have entailed an additional round of patching after
> switching over to the high address space.
> 
> The approach implemented here conceptually extends the original PHYS_OFFSET
> patching implementation with the introduction of "early" patch stubs.  Early
> patch code is required to be functional out of the box, even before the patch
> is applied.  This is implemented by inserting functional (but inefficient)
> load code into the .patch.code init section.  Having functional code out of
> the box then allows us to defer the init time patch application until later
> in the init sequence.
> 
> In addition to fitting better with our need for physical address-space
> switch-over, this implementation should be somewhat more extensible by virtue
> of its more readable (and hackable) C implementation.  This should prove
> useful for other similar init time specialization needs, especially in light
> of our multi-platform kernel initiative.
> 
> This code has been boot tested in both ARM and Thumb-2 modes on an ARMv7
> (Cortex-A8) device.
> 
> Note: the obtuse use of stringified symbols in patch_stub() and
> early_patch_stub() is intentional.  Theoretically this should have been
> accomplished with formal operands passed into the asm block, but this requires
> the use of the 'c' modifier for instantiating the long (e.g. .long %c0).
> However, the 'c' modifier has been found to ICE certain versions of GCC, and
> therefore we resort to stringified symbols here.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

This looks very nice.  Comments below.

> ---
>  arch/arm/include/asm/patch.h  |  123 +++++++++++++++++++++++++++++

Please find a better name for this file. "patch" is way too generic and 
commonly referring to something different. "runtime-patching" or similar 
would be more descriptive.

>  arch/arm/kernel/module.c      |    4 +
>  arch/arm/kernel/setup.c       |  175 +++++++++++++++++++++++++++++++++++++++++

This is complex enough to waarrant aa separate source file.  Please move 
those additions out from setup.c.  Given a good name for the header file 
above, the c file could share the same name.

> new file mode 100644
> index 0000000..a89749f
> --- /dev/null
> +++ b/arch/arm/include/asm/patch.h
> @@ -0,0 +1,123 @@
> +/*
> + *  arch/arm/include/asm/patch.h
> + *
> + *  Copyright (C) 2012, Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + *  Note: this file should not be included by non-asm/.h files
> + */
> +#ifndef __ASM_ARM_PATCH_H
> +#define __ASM_ARM_PATCH_H
> +
> +#include <linux/stringify.h>
> +
> +#ifndef __ASSEMBLY__
> +
> extern unsigned __patch_table_begin, __patch_table_end;

You could use "exttern void __patch_table_begin" so those symbols don't 
get any type that could be misused by mistake, while you still can take 
their addresses.

> +
> +struct patch_info {
> +	u32	 type;
> +	u32	 size;

Given the possibly large number of table entries, some effort at making 
those entries as compact as possible should be considered. For instance, 
the type and size fields could be u8's and insn_end pointer replaced 
with another size expressed as an u8.  By placing all the u8's together 
they would occupy a single word by themselves.  The assembly stub would 
only need a .align statement to reflect the c structure's padding.

[...]

Did you verify with some test program that your patching routines do 
produce the same opcodes as the assembled equivalent for all possible 
shift values?  Especially for Thumb2 code which isn't as trivial to get 
right as the ARM one.


Nicolas


From nicolas.pitre at linaro.org  Sat Aug  4 02:15:56 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:15:56 -0400 (EDT)
Subject: [PATCH 02/22] ARM: use late patch framework for phys-virt patching
In-Reply-To: <1343775898-28345-3-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-3-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040138560.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> This patch replaces the original physical offset patching implementation
> with one that uses the newly added patching framework.  In the process, we now
> unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
> head.S code.

Why unconditionally initializing those?  There is no reason for that.

> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Comments below.

> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 835898e..d165896 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
[...]
>  	.data
>  	.globl	__pv_phys_offset
>  	.type	__pv_phys_offset, %object
>  __pv_phys_offset:
>  	.long	0
>  	.size	__pv_phys_offset, . - __pv_phys_offset
> +
> +	.globl	__pv_offset
> +	.type	__pv_offset, %object
>  __pv_offset:
>  	.long	0
> -#endif
> +	.size	__pv_offset, . - __pv_offset

Please move those to C code.  They aren't of much use in this file 
anymore.  This will allow you to use pphys_addr_t for them as well in 
your subsequent patch. And more importantly get rid of that ugly 
pv_offset_high that you introduced iin another patch.

> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index df5e897..39f8fce 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -317,11 +317,6 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
>  					         maps[i].txt_sec->sh_addr,
>  					         maps[i].txt_sec->sh_size);
>  #endif
> -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> -	s = find_mod_section(hdr, sechdrs, ".pv_table");
> -	if (s)
> -		fixup_pv_table((void *)s->sh_addr, s->sh_size);
> -#endif
>  	s = find_mod_section(hdr, sechdrs, ".patch.table");
>  	if (s)
>  		patch_kernel((void *)s->sh_addr, s->sh_size);

The patch_kernel code and its invokation should still be conditional on 
CONFIG_ARM_PATCH_PHYS_VIRT.  This ability may still be configured out 
irrespective of the implementation used.

> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
> index bacb275..13731e3 100644
> --- a/arch/arm/kernel/vmlinux.lds.S
> +++ b/arch/arm/kernel/vmlinux.lds.S
> @@ -162,11 +162,6 @@ SECTIONS
>  		__smpalt_end = .;
>  	}
>  #endif
> -	.init.pv_table : {
> -		__pv_table_begin = .;
> -		*(.pv_table)
> -		__pv_table_end = .;
> -	}
>  	.init.patch_table : {
>  		__patch_table_begin = .;
>  		*(.patch.table)

Since you're changing the module ABI,it is important to also modify the 
module vermagic string in asm/module.h to prevent the loading of 
incompatible kernel modules.


Nicolas


From nicolas.pitre at linaro.org  Sat Aug  4 02:24:02 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:24:02 -0400 (EDT)
Subject: [PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <1343775898-28345-4-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-4-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040222110.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> This patch fixes up the types used when converting back and forth between
> physical and virtual addresses.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Did you verify that this didn't introduce any compilation warning when 
compiling for non LPAE?  If so and there were no warnings then...

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/include/asm/memory.h |   17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 01c710d..4a0108f 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -157,22 +157,27 @@ extern unsigned long __pv_phys_offset;
>  
>  extern unsigned long __pv_offset;
>  
> -static inline unsigned long __virt_to_phys(unsigned long x)
> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>  {
>  	unsigned long t;
>  	early_patch_imm8(x, t, "add", __pv_offset);
>  	return t;
>  }
>  
> -static inline unsigned long __phys_to_virt(unsigned long x)
> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>  {
>  	unsigned long t;
>  	early_patch_imm8(x, t, "sub", __pv_offset);
>  	return t;
>  }
>  #else
> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
> +
> +#define __virt_to_phys(x)		\
> +	((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)
> +
> +#define __phys_to_virt(x)		\
> +	((unsigned long)((phys_addr_t)(x) - PHYS_OFFSET + PAGE_OFFSET))
> +
>  #endif
>  #endif
>  
> @@ -207,14 +212,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>  
>  static inline void *phys_to_virt(phys_addr_t x)
>  {
> -	return (void *)(__phys_to_virt((unsigned long)(x)));
> +	return (void *)__phys_to_virt(x);
>  }
>  
>  /*
>   * Drivers should NOT use these either.
>   */
>  #define __pa(x)			__virt_to_phys((unsigned long)(x))
> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>  #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
>  
>  /*
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug  4 02:49:10 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:49:10 -0400 (EDT)
Subject: [PATCH 04/22] ARM: LPAE: support 64-bit virt/phys patching
In-Reply-To: <1343775898-28345-5-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-5-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040226060.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> This patch adds support for 64-bit physical addresses in virt_to_phys
> patching.  This does not do real 64-bit add/sub, but instead patches in the
> upper 32-bits of the phys_offset directly into the output of virt_to_phys.

You should explain _why_ you do not a real aadd/sub.  I did deduce it 
but that might not be obvious to everyone.  Also this subtlety should be 
commented in the code as well.

> In addition to adding 64-bit support, this patch also adds a set_phys_offset()
> helper that is needed on architectures that need to modify PHYS_OFFSET during
> initialization.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  arch/arm/include/asm/memory.h |   22 +++++++++++++++-------
>  arch/arm/kernel/head.S        |    6 ++++++
>  arch/arm/kernel/setup.c       |   14 ++++++++++++++
>  3 files changed, 35 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 4a0108f..110495c 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -153,23 +153,31 @@
>  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>  
>  extern unsigned long __pv_phys_offset;
> -#define PHYS_OFFSET __pv_phys_offset
> -
> +extern unsigned long __pv_phys_offset_high;

As mentioned previously, this is just too ugly.  Please make 
__pv_phys_offset into a phys_addr_t instead and mask the low/high parts 
as needed in __virt_to_phys().

>  extern unsigned long __pv_offset;
>  
> +extern void set_phys_offset(phys_addr_t po);
> +
> +#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
> +
>  static inline phys_addr_t __virt_to_phys(unsigned long x)
>  {
> -	unsigned long t;
> -	early_patch_imm8(x, t, "add", __pv_offset);
> -	return t;
> +	unsigned long tlo, thi = 0;
> +
> +	early_patch_imm8(x, tlo, "add", __pv_offset);
> +	if (sizeof(phys_addr_t) > 4)
> +		early_patch_imm8(0, thi, "add", __pv_phys_offset_high);

Given the high part is always the same, isn't there a better way than an 
add with 0 that could be done here?  The add will force a load of 0 in a 
register needlessly just to add a constant value to it.  Your new 
patching framework ought to be able to patch a mov (or a mvn) 
instruction directly.


Nicolas


From nicolas.pitre at linaro.org  Sat Aug  4 02:51:47 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:51:47 -0400 (EDT)
Subject: [PATCH 06/22] ARM: LPAE: use phys_addr_t in alloc_init_pud()
In-Reply-To: <1343775898-28345-7-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-7-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040251020.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> From: Vitaly Andrianov <vitalya at ti.com>
> 
> This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
> unsigned long when passing in the phys argument.
> 
> This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a, which
> applied similar changes elsewhere in the ARM memory management code.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mm/mmu.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index cf4528d..226985c 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -628,7 +628,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
>  }
>  
>  static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
> -	unsigned long end, unsigned long phys, const struct mem_type *type)
> +				  unsigned long end, phys_addr_t phys,
> +				  const struct mem_type *type)
>  {
>  	pud_t *pud = pud_offset(pgd, addr);
>  	unsigned long next;
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug  4 02:54:14 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:54:14 -0400 (EDT)
Subject: [PATCH 07/22] ARM: LPAE: use phys_addr_t in free_memmap()
In-Reply-To: <1343775898-28345-8-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-8-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040253140.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> From: Vitaly Andrianov <vitalya at ti.com>
> 
> The free_memmap() was mistakenly using unsigned long type to represent
> physical addresses.  This breaks on PAE systems where memory could be placed
> above the 32-bit addressible limit.
> 
> This patch fixes this function to properly use phys_addr_t instead.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mm/init.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index f54d592..8252c31 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -457,7 +457,7 @@ static inline void
>  free_memmap(unsigned long start_pfn, unsigned long end_pfn)
>  {
>  	struct page *start_pg, *end_pg;
> -	unsigned long pg, pgend;
> +	phys_addr_t pg, pgend;
>  
>  	/*
>  	 * Convert start_pfn/end_pfn to a struct page pointer.
> @@ -469,8 +469,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
>  	 * Convert to physical addresses, and
>  	 * round start upwards and end downwards.
>  	 */
> -	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
> -	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
> +	pg = PAGE_ALIGN(__pa(start_pg));
> +	pgend = __pa(end_pg) & PAGE_MASK;
>  
>  	/*
>  	 * If there are free pages between these,
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug  4 02:57:25 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 02:57:25 -0400 (EDT)
Subject: [PATCH 08/22] ARM: LPAE: use phys_addr_t for initrd location
 and size
In-Reply-To: <1343775898-28345-9-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-9-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040255100.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> From: Vitaly Andrianov <vitalya at ti.com>
> 
> This patch fixes the initrd setup code to use phys_addr_t instead of assuming
> 32-bit addressing.  Without this we cannot boot on systems where initrd is
> located above the 4G physical address limit.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  arch/arm/mm/init.c |   14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 8252c31..51f3e92 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -36,12 +36,12 @@
>  
>  #include "mm.h"
>  
> -static unsigned long phys_initrd_start __initdata = 0;
> -static unsigned long phys_initrd_size __initdata = 0;
> +static phys_addr_t phys_initrd_start __initdata = 0;
> +static phys_addr_t phys_initrd_size __initdata = 0;

phys_addr_t for the initrd size is rather overkill, isn't it?


Nicolas


From r.sricharan at ti.com  Sat Aug  4 03:00:22 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Sat, 4 Aug 2012 12:30:22 +0530
Subject: [PATCH 1/1] ARM: Fix mapping in alloc_init_section for unaligned
 addresses.
Message-ID: <1344063622-11021-1-git-send-email-r.sricharan@ti.com>

When either the start address or end address or physical address
to be mapped is unaligned, alloc_init_section creates
page granularity mappings. alloc_init_section calls
alloc_init_pte which populates one pmd entry and sets up
the ptes. But if the size is greater than what can be mapped
by one pmd entry, then the rest remains unmapped.

The issue becomes visible when LPAE is enabled, where we have
the 3 levels with seperate pgd and pmd's.
When a static mapping for 3MB is requested, only 2MB is mapped
and the remaining 1MB is unmapped. Fixing this here, by looping
in to map the entire unaligned address range.

Signed-off-by: R Sricharan <r.sricharan at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/mmu.c |   54 ++++++++++++++++++++++++++++++-----------------------
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d..c8c405f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -597,34 +597,42 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 				      const struct mem_type *type)
 {
 	pmd_t *pmd = pmd_offset(pud, addr);
-
-	/*
-	 * Try a section mapping - end, addr and phys must all be aligned
-	 * to a section boundary.  Note that PMDs refer to the individual
-	 * L1 entries, whereas PGDs refer to a group of L1 entries making
-	 * up one logical pointer to an L2 table.
-	 */
-	if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
-		pmd_t *p = pmd;
+	unsigned long next;
 
 #ifndef CONFIG_ARM_LPAE
-		if (addr & SECTION_SIZE)
-			pmd++;
+	if ((addr & SECTION_SIZE) &&
+	      (type->prot_sect && ((addr | next | phys) & ~SECTION_MASK) == 0))
+		pmd++;
 #endif
-
-		do {
-			*pmd = __pmd(phys | type->prot_sect);
-			phys += SECTION_SIZE;
-		} while (pmd++, addr += SECTION_SIZE, addr != end);
-
-		flush_pmd_entry(p);
-	} else {
+	do {
+		if ((end - addr) & SECTION_MASK)
+			next = (addr + SECTION_SIZE) & SECTION_MASK;
+		else
+			next = end;
 		/*
-		 * No need to loop; pte's aren't interested in the
-		 * individual L1 entries.
+		 * Try a section mapping - end, addr and phys must all be
+		 * aligned to a section boundary.  Note that PMDs refer to
+		 * the individual L1 entries, whereas PGDs refer to a group
+		 * of L1 entries making up one logical pointer to an L2 table.
 		 */
-		alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
-	}
+		if (type->prot_sect &&
+				((addr | next | phys) & ~SECTION_MASK) == 0) {
+			*pmd = __pmd(phys | type->prot_sect);
+			flush_pmd_entry(pmd);
+		} else {
+			/*
+			 * when addresses are not aligned,
+			 * we may be required to map address range greater
+			 * than a section size. So loop in here to map the
+			 * complete range.
+			 */
+			alloc_init_pte(pmd, addr, next,
+						__phys_to_pfn(phys), type);
+		}
+
+		phys += next - addr;
+
+	} while (pmd++, addr = next, addr != end);
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-- 
1.7.9.5



From nicolas.pitre at linaro.org  Sat Aug  4 03:04:56 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 4 Aug 2012 03:04:56 -0400 (EDT)
Subject: [PATCH 09/22] ARM: LPAE: use 64-bit pgd physical address in
 switch_mm()
In-Reply-To: <1343775898-28345-10-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-10-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208040259200.5231@xanadu.home>

On Tue, 31 Jul 2012, Cyril Chemparathy wrote:

> This patch modifies the switch_mm() processor functions to use 64-bit
> addresses.  We use u64 instead of phys_addr_t, in order to avoid having config
> dependent register usage when calling into switch_mm assembly code.
> 
> The changes in this patch are primarily adjustments for registers used for
> arguments to switch_mm.  The few processor definitions that did use the second
> argument have been modified accordingly.
> 
> Arguments and calling conventions aside, this patch should be a no-op on v6
> and non-LPAE v7 processors. 

NAK.

You just broke all big endian targets, LPAE or not.


Nicolas


From linux at arm.linux.org.uk  Sat Aug  4 04:39:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 4 Aug 2012 09:39:46 +0100
Subject: [PATCH 00/22] Introducing the TI Keystone platform
In-Reply-To: <1343775898-28345-1-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
Message-ID: <20120804083945.GB6802@n2100.arm.linux.org.uk>

On Tue, Jul 31, 2012 at 07:04:36PM -0400, Cyril Chemparathy wrote:
> This series is a follow on to the RFC series posted earlier (archived at [1]).
> The major change introduced here is the modification to the kernel patching
> mechanism for phys_to_virt/virt_to_phys, in order to support LPAE platforms
> that require late patching.  In addition to these changes, we've updated the
> series based on feedback from the earlier posting.
> 
> Most of the patches in this series are fixes and extensions to LPAE support on
> ARM. The last three patches in this series are specific to the TI Keystone
> platform, and are being provided here for the sake of completeness.  These
> three patches are dependent on the smpops patch set (see [2]), and are not
> ready to be merged in as yet.

Can you explain why you want the kernel loaded above the 4GB watermark?
This seems silly to me, as the kernel needs to run at points with a 1:1
physical to virtual mapping, and you can't do that if the kernel is
stored in physical memory above the 4GB watermark.



From linux at arm.linux.org.uk  Sat Aug  4 04:44:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 4 Aug 2012 09:44:39 +0100
Subject: [PATCH 1/1] ARM: Fix mapping in alloc_init_section for
 unaligned addresses.
In-Reply-To: <1344063622-11021-1-git-send-email-r.sricharan@ti.com>
References: <1344063622-11021-1-git-send-email-r.sricharan@ti.com>
Message-ID: <20120804084439.GC6802@n2100.arm.linux.org.uk>

On Sat, Aug 04, 2012 at 12:30:22PM +0530, R Sricharan wrote:
> When either the start address or end address or physical address
> to be mapped is unaligned, alloc_init_section creates
> page granularity mappings. alloc_init_section calls
> alloc_init_pte which populates one pmd entry and sets up
> the ptes. But if the size is greater than what can be mapped
> by one pmd entry, then the rest remains unmapped.
> 
> The issue becomes visible when LPAE is enabled, where we have
> the 3 levels with seperate pgd and pmd's.
> When a static mapping for 3MB is requested, only 2MB is mapped
> and the remaining 1MB is unmapped. Fixing this here, by looping
> in to map the entire unaligned address range.

This doesn't look like a nice fix.  The implication above is that it's
only alloc_init_pte() which is affected - so why not add a loop there?

Remember that pte's cover two sections, not one, so you need to use a
different increment to sections.


From Julia.Lawall at lip6.fr  Sat Aug  4 04:35:30 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sat,  4 Aug 2012 10:35:30 +0200
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
Message-ID: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Fix some problems with the use of devm_ functions.

devm_kzalloc: devm_kfree is not needed

devm_ioremap: iounmap should not be used, no free is needed

devm_request_irq: the devm_free_irq is followed by irq_dispose_mapping.  I
don't know if it is safe to move the freeing of the irq in this case, so I
have just un-devm'd this function, since the implicit freeing is never
taken advantage of.

In the original code failure of of_address_to_resource jumped to free_mem,
but should have jumped to irq_dispose, since irq_of_parse_and_map has
completed at this point.

In the original code unmap_mem was after irq_dispose, but it should have
been before, again since irq_of_parse_and_map has completed at this point.

One of these problems was found using the following semantic match:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression x;
@@

*x = devm_ioremap(...)
...
iounmap(x);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
Not compiled.  Does free_irq actually have to be called before
irq_dispose_mapping?

 drivers/dma/sirf-dma.c |   23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 434ad31..1af9e48 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -570,21 +570,19 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 
 	if (of_property_read_u32(dn, "cell-index", &id)) {
 		dev_err(dev, "Fail to get DMAC index\n");
-		ret = -ENODEV;
-		goto free_mem;
+		return -ENODEV;
 	}
 
 	sdma->irq = irq_of_parse_and_map(dn, 0);
 	if (sdma->irq == NO_IRQ) {
 		dev_err(dev, "Error mapping IRQ!\n");
-		ret = -EINVAL;
-		goto free_mem;
+		return -EINVAL;
 	}
 
 	ret = of_address_to_resource(dn, 0, &res);
 	if (ret) {
 		dev_err(dev, "Error parsing memory region!\n");
-		goto free_mem;
+		goto irq_dispose;
 	}
 
 	regs_start = res.start;
@@ -597,12 +595,11 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 		goto irq_dispose;
 	}
 
-	ret = devm_request_irq(dev, sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME,
-		sdma);
+	ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
 	if (ret) {
 		dev_err(dev, "Error requesting IRQ!\n");
 		ret = -EINVAL;
-		goto unmap_mem;
+		goto irq_dispose;
 	}
 
 	dma = &sdma->dma;
@@ -652,13 +649,9 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 	return 0;
 
 free_irq:
-	devm_free_irq(dev, sdma->irq, sdma);
+	free_irq(sdma->irq, sdma);
 irq_dispose:
 	irq_dispose_mapping(sdma->irq);
-unmap_mem:
-	iounmap(sdma->base);
-free_mem:
-	devm_kfree(dev, sdma);
 	return ret;
 }
 
@@ -668,10 +661,8 @@ static int __devexit sirfsoc_dma_remove(struct platform_device *op)
 	struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
 
 	dma_async_device_unregister(&sdma->dma);
-	devm_free_irq(dev, sdma->irq, sdma);
+	free_irq(sdma->irq, sdma);
 	irq_dispose_mapping(sdma->irq);
-	iounmap(sdma->base);
-	devm_kfree(dev, sdma);
 	return 0;
 }
 



From linux at arm.linux.org.uk  Sat Aug  4 04:51:42 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 4 Aug 2012 09:51:42 +0100
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
References: <1344013004-32211-1-git-send-email-vikram.pandita@ti.com>
 <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
 <20120803221327.GA5102@kroah.com>
 <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
Message-ID: <20120804085142.GP7405@n2100.arm.linux.org.uk>

On Fri, Aug 03, 2012 at 03:25:17PM -0700, Pandita, Vikram wrote:
> Other issue i found, using this patch, that on multi-core ARM systems,
> almost 99% of times, IRQ's are handled by CPU0,
> even if CPU0 was really busy and other CPU's were free. I am yet to
> understand a good reason why.

That is because you're probably not running irqbalanced on your platforms.

Firstly, the hardware does no IRQ balancing itself - you have to manually
route IRQs to CPUs in the hardware, and if you ask for an IRQ to be
delivered to several CPUs, all CPUs will get it each time it fires (unlike
x86 IOAPIC which picks a CPU to route the IRQ to.)

The ARM kernel does no IRQ balancing itself across CPUs, because when I
tried to implement it, every algorithm I tried gave completely sub-optimal
results, and irqbalanced existed to do the job in userspace.  So as there
is a userspace solution which works, there was no point to doing this in
the kernel.

Please use the irqbalance daemon to spread IRQs across your CPUs.


From r.sricharan at ti.com  Sat Aug  4 06:04:00 2012
From: r.sricharan at ti.com (R, Sricharan)
Date: Sat, 4 Aug 2012 15:34:00 +0530
Subject: [PATCH 1/1] ARM: Fix mapping in alloc_init_section for unaligned
 addresses.
In-Reply-To: <20120804084439.GC6802@n2100.arm.linux.org.uk>
References: <1344063622-11021-1-git-send-email-r.sricharan@ti.com>
 <20120804084439.GC6802@n2100.arm.linux.org.uk>
Message-ID: <CAJ7qFSdhjH+66kT_FF0LkiJmXL3Hp9wVKL7v-y3OoJk-LxzmzQ@mail.gmail.com>

Hi Russell,

On Sat, Aug 4, 2012 at 2:14 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Sat, Aug 04, 2012 at 12:30:22PM +0530, R Sricharan wrote:
>> When either the start address or end address or physical address
>> to be mapped is unaligned, alloc_init_section creates
>> page granularity mappings. alloc_init_section calls
>> alloc_init_pte which populates one pmd entry and sets up
>> the ptes. But if the size is greater than what can be mapped
>> by one pmd entry, then the rest remains unmapped.
>>
>> The issue becomes visible when LPAE is enabled, where we have
>> the 3 levels with seperate pgd and pmd's.
>> When a static mapping for 3MB is requested, only 2MB is mapped
>> and the remaining 1MB is unmapped. Fixing this here, by looping
>> in to map the entire unaligned address range.
>
> This doesn't look like a nice fix.  The implication above is that it's
> only alloc_init_pte() which is affected - so why not add a loop there?
>
    Ok, will move the loop to alloc_init_pte instead.

> Remember that pte's cover two sections, not one, so you need to use a
> different increment to sections.

     Yes, and that varies when LPAE is enabled. Will take care of this
     as well in V2 post.

Thanks,
 Sricharan


From broonie at opensource.wolfsonmicro.com  Sat Aug  4 07:11:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 4 Aug 2012 12:11:00 +0100
Subject: [PATCH 2/2] SPI: Refactor spi-orion to use SPI framework queue.
In-Reply-To: <1343042216-4113-2-git-send-email-andrew@lunn.ch>
References: <1343042216-4113-1-git-send-email-andrew@lunn.ch>
 <1343042216-4113-2-git-send-email-andrew@lunn.ch>
Message-ID: <20120804111100.GF10523@opensource.wolfsonmicro.com>

On Mon, Jul 23, 2012 at 01:16:55PM +0200, Andrew Lunn wrote:
> Replace the deprecated master->transfer with transfer_one_message()
> and allow the SPI subsystem handle all the queuing of messages.

Applied, thanks.


From u.kleine-koenig at pengutronix.de  Sat Aug  4 09:57:19 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sat, 4 Aug 2012 15:57:19 +0200
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <20120803151740.GZ2005@localhost.localdomain>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <201208031407.09092.arnd@arndb.de>
 <20120803145035.GJ2626@pengutronix.de>
 <20120803151740.GZ2005@localhost.localdomain>
Message-ID: <20120804135719.GK2626@pengutronix.de>

Hello,

On Fri, Aug 03, 2012 at 08:47:40PM +0530, Shiraz Hashim wrote:
> On Fri, Aug 03, 2012 at 10:50:35PM +0800, Uwe Kleine-K?nig wrote:
> > On Fri, Aug 03, 2012 at 02:07:08PM +0000, Arnd Bergmann wrote:
> > > Is it possible to build a NOMMU kernel that runs on both
> > > ARMv7-A amd ARMv7-M, in other words is ARMv7-M compatible with
> > > ARMv7-A (or ARMv7-R for that matter) if you don't use the MMU?
> >
> > the instructions to enable and disable irqs are different, so
> > we'd need another indirection at least there. Also the whole
> > exception model is different. So I'd say it's too different to
> > target for a common kernel for the A, R and M profiles.
> 
> We are using standard Linux kernel (v3.3) with MMU disabled on
> a Cortex R4 system.
Yeah, I expected A and R to be similar enough. It's the difference
between (A+R) and M that makes a common kernel for all three profiles
hard.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From shawn.guo at linaro.org  Sat Aug  4 10:09:02 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 Aug 2012 22:09:02 +0800
Subject: [PATCH V2] MXS: Remove MMAP_MIN_ADDR setting from mxs_defconfig
In-Reply-To: <1344020088-8156-1-git-send-email-marex@denx.de>
References: <1344020088-8156-1-git-send-email-marex@denx.de>
Message-ID: <20120804140859.GA3405@S2101-09.ap.freescale.net>

Again, patch subject should be like "ARM: mxs: ...".

On Fri, Aug 03, 2012 at 08:54:48PM +0200, Marek Vasut wrote:
> The CONFIG_DEFAULT_MMAP_MIN_ADDR was set to 65536 in mxs_defconfig,
> this caused severe breakage of userland applications since the upper
> limit for ARM is 32768. By default CONFIG_DEFAULT_MMAP_MIN_ADDR is
> set to 4096 and can also be changed via /proc/sys/vm/mmap_min_addr
> if needed.
> 
> Quoting Russell King [1]:
> 
> "4096 is also fine for ARM too. There's not much point in having
> defconfigs change it - that would just be pure noise in the config
> files."
> 
> the CONFIG_DEFAULT_MMAP_MIN_ADDR can be removed from the defconfig
> altogether.
> 
> This problem was introduced by:
> 
> commit cde7c41feaa06cb6bfc748b2fc3c7d809091c2b0
> Author: Wolfram Sang <w.sang at pengutronix.de>
> Date:   Fri Apr 29 15:06:40 2011 +0200
> 
>     ARM: configs: add defconfig for mach-mxs
> 

We generally quote another commit in commit message like

cde7c41 (ARM: configs: add defconfig for mach-mxs)

> [1] http://marc.info/?l=linux-arm-kernel&m=134401593807820&w=2
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Wolfgang Denk <wd at denx.de>

We should Cc stable.

I just fixed them and queued the patch for 3.6-rc.

Regards,
Shawn



From shawn.guo at linaro.org  Sat Aug  4 10:41:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 Aug 2012 22:41:00 +0800
Subject: [GIT PULL] mxs fixes for 3.6
Message-ID: <20120804144058.GB3405@S2101-09.ap.freescale.net>

Hi Arnd, Olof,

Please pull the following mxs fixes for 3.6.

Regards,
Shawn

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.linaro.org/people/shawnguo/linux-2.6.git mxs/fixes-for-3.6

Fabio Estevam (2):
      ARM: mx23: Fix registers range
      ARM: mx28: Fix registers range

Marek Vasut (1):
      ARM: mxs: Remove MMAP_MIN_ADDR setting from mxs_defconfig

 arch/arm/boot/dts/imx23.dtsi   |   52 ++++++++++++++--------------
 arch/arm/boot/dts/imx28.dtsi   |   74 ++++++++++++++++++++--------------------
 arch/arm/configs/mxs_defconfig |    1 -
 3 files changed, 63 insertions(+), 64 deletions(-)



From shawn.guo at linaro.org  Sat Aug  4 10:46:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 Aug 2012 22:46:38 +0800
Subject: [GIT PULL] imx fixes for 3.6
Message-ID: <20120804144636.GC3405@S2101-09.ap.freescale.net>

Hi Arnd, Olof,

Please pull the following imx fixes for 3.6.

Regards,
Shawn

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.linaro.org/people/shawnguo/linux-2.6.git imx/fixes-for-3.6

Fabio Estevam (1):
      ARM: imx6q-sabrelite: Setup CLKO IOMUX

Shawn Guo (3):
      ARM: imx: enable emi_slow_gate clock for imx5
      ARM: dts: imx53-ard: add regulators for lan9220
      ARM: dts: imx: fix gpio interrupts property

 arch/arm/boot/dts/imx51-babbage.dts   |    2 +-
 arch/arm/boot/dts/imx53-ard.dts       |   22 +++++++++++++++++++++-
 arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
 arch/arm/mach-imx/clk-imx51-imx53.c   |    1 +
 4 files changed, 24 insertions(+), 2 deletions(-)



From shawn.guo at linaro.org  Sat Aug  4 10:54:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 4 Aug 2012 22:54:47 +0800
Subject: [GIT PULL] mxs fixes for 3.6
In-Reply-To: <20120804144058.GB3405@S2101-09.ap.freescale.net>
References: <20120804144058.GB3405@S2101-09.ap.freescale.net>
Message-ID: <20120804145445.GD3405@S2101-09.ap.freescale.net>

On Sat, Aug 04, 2012 at 10:41:00PM +0800, Shawn Guo wrote:
> Hi Arnd, Olof,
> 
> Please pull the following mxs fixes for 3.6.
> 
One fix was missed there.  Updated request is below.

Regards,
Shawn

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.linaro.org/people/shawnguo/linux-2.6.git mxs/fixes-for-3.6

Fabio Estevam (2):
      ARM: mx23: Fix registers range
      ARM: mx28: Fix registers range

Marc Kleine-Budde (1):
      ARM: mxs: always build ocotp

Marek Vasut (1):
      ARM: mxs: Remove MMAP_MIN_ADDR setting from mxs_defconfig

 arch/arm/boot/dts/imx23.dtsi   |   52 ++++++++++++++--------------
 arch/arm/boot/dts/imx28.dtsi   |   74 ++++++++++++++++++++--------------------
 arch/arm/configs/mxs_defconfig |    1 -
 arch/arm/mach-mxs/Kconfig      |    6 ---
 arch/arm/mach-mxs/Makefile     |    3 +-
 5 files changed, 64 insertions(+), 72 deletions(-)



From dirk.behme at gmail.com  Sat Aug  4 11:47:17 2012
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sat, 04 Aug 2012 17:47:17 +0200
Subject: [PATCH] mtd: mxc_nand: Fix compiler warnings
In-Reply-To: <20120730073454.GI1528@pengutronix.de>
References: <1343466310-14584-1-git-send-email-dirk.behme@gmail.com>
 <20120730073454.GI1528@pengutronix.de>
Message-ID: <501D4405.6030900@googlemail.com>

On 30.07.2012 09:34, Uwe Kleine-K?nig wrote:
> Hello,
>
> On Sat, Jul 28, 2012 at 11:05:10AM +0200, Dirk Behme wrote:
>> From: Dirk Behme<dirk.behme at googlemail.com>
>>
>> Fix the compiler warnings
>>
>> drivers/mtd/nand/mxc_nand.c:1267: warning: initialization discards qualifiers from pointer target type
>> drivers/mtd/nand/mxc_nand.c:1270: warning: initialization discards qualifiers from pointer target type
>> drivers/mtd/nand/mxc_nand.c:1273: warning: initialization discards qualifiers from pointer target type
>> drivers/mtd/nand/mxc_nand.c:1276: warning: initialization discards qualifiers from pointer target type
> These should be gone in next already.

Hmm, which next?

I tried linux-next [1] from today (next-20120803, 55fa9961f) and still get

 > make drivers/mtd/nand/
...
  CC      drivers/mtd/nand/mxc_nand.o 

drivers/mtd/nand/mxc_nand.c:1298: warning: initialization discards 
qualifiers from pointer target type
drivers/mtd/nand/mxc_nand.c:1301: warning: initialization discards 
qualifiers from pointer target type
drivers/mtd/nand/mxc_nand.c:1304: warning: initialization discards 
qualifiers from pointer target type
drivers/mtd/nand/mxc_nand.c:1307: warning: initialization discards 
qualifiers from pointer target type
drivers/mtd/nand/mxc_nand.c:1310: warning: initialization discards 
qualifiers from pointer target type
   CC      drivers/mtd/nand/gpmi-nand/gpmi-nand.o
...

Sorry if I missed something ;)

Best regards

Dirk

[1] 
http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=shortlog;h=refs/heads/master



From haojian.zhuang at gmail.com  Sat Aug  4 12:06:03 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 00:06:03 +0800
Subject: [PATCH 1/7] ARM: pxa: support CKENC in clk_enable
In-Reply-To: <1343715194-25900-1-git-send-email-xiechao.mail@gmail.com>
References: <1343715194-25900-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <CAN1soZxoEhz+cANTpSAR1E80ZENnHVOJKn9tKY06dgT2cbk-0A@mail.gmail.com>

On Tue, Jul 31, 2012 at 2:13 PM, Chao Xie <xiechao.mail at gmail.com> wrote:
> From: Chao Xie <chao.xie at marvell.com>
>
> Since more device clock is supported in PXA95x, add CKENC support.
>
> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
> ---
>  arch/arm/mach-pxa/clock-pxa3xx.c |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
>

Applied all.

Thanks
Haojian


From thomas.petazzoni at free-electrons.com  Sat Aug  4 12:27:30 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 4 Aug 2012 18:27:30 +0200
Subject: arm: mvebu: Add basic address decoding support for Marvell 370/XP
In-Reply-To: <201208031423.10561.arnd@arndb.de>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201208031423.10561.arnd@arndb.de>
Message-ID: <20120804182730.1ef77f23@skate>

Le Fri, 3 Aug 2012 14:23:09 +0000,
Arnd Bergmann <arnd at arndb.de> a ?crit :

> On Friday 03 August 2012, Thomas Petazzoni wrote:
> > Here is a small patch set that introduces basic support for address
> > decoding on Armada 370 and Armada XP. The aim of this basic support
> > is essentially to be able to configure a window to remap the
> > BootROM, which is needed to startup the secondary CPUs for the SMP
> > support.
> > 
> > As we had discussed already, the address decoding configuration is
> > not described in the Device Tree, it is for now hardcoded on a
> > per-SoC basis. We might later discuss how to extend this to the
> > Device Tree.
> 
> Makes sense. I wonder if there is a proper way to describe the
> setting in the device tree anyway, given that there is more than one
> valid option to do it.

Well, we could do something like:

addr-decoding at d0020000 {
        compatible = "marvell,armada-addr-decoding-controller";
        reg = <0xd0020000 0x258>;

        window at 0 {
		/* Window number */
		cell-index = <0>;                             

		/* Physical address and size at which the device will be mapped. */
		reg = <0xfff00000 0x100000>;

		/* Which device is being mapped. Can either have 1
		   integer (for "big" devices) or 2 integers (for devices
		   in the "Device Bus") */
                marvell,target = <0x1 0x1d>;

		/* Optional. Remapping address */
		marvell,remap = <...>;
	};

	window at 12 {
		cell-index = <12>;
		reg = <0x... 0x....>;
		marvell,target = <0x4>;
	};
};

This is just a rough draft, just written in the mail, I haven't even
tried writing code that would work with it, but it should be relatively
easy to do.

Would that make sense? Of course, suggestions welcome, I'm not an
expert on how to decide what is the best DT encoding for such data.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Sat Aug  4 12:50:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 4 Aug 2012 16:50:50 +0000
Subject: arm: mvebu: Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120804182730.1ef77f23@skate>
References: <1343999430-31816-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201208031423.10561.arnd@arndb.de> <20120804182730.1ef77f23@skate>
Message-ID: <201208041650.51427.arnd@arndb.de>

On Saturday 04 August 2012, Thomas Petazzoni wrote:
> Well, we could do something like:
> 
> addr-decoding at d0020000 {
>         compatible = "marvell,armada-addr-decoding-controller";
>         reg = <0xd0020000 0x258>;
> 
>         window at 0 {
>                 /* Window number */
>                 cell-index = <0>;                             
> 
>                 /* Physical address and size at which the device will be mapped. */
>                 reg = <0xfff00000 0x100000>;
> 
>                 /* Which device is being mapped. Can either have 1
>                    integer (for "big" devices) or 2 integers (for devices
>                    in the "Device Bus") */
>                 marvell,target = <0x1 0x1d>;
> 
>                 /* Optional. Remapping address */
>                 marvell,remap = <...>;
>         };
> 
>         window at 12 {
>                 cell-index = <12>;
>                 reg = <0x... 0x....>;
>                 marvell,target = <0x4>;
>         };
> };
> 
> This is just a rough draft, just written in the mail, I haven't even
> tried writing code that would work with it, but it should be relatively
> easy to do.
> 
> Would that make sense? Of course, suggestions welcome, I'm not an
> expert on how to decide what is the best DT encoding for such data.

The point that I'm wondering about is where the physical address
comes from. This one is not describing the hardware at all, and the OS
is free to pick any other address, so why would be put that particular
one into the device tree?

Maybe you can find a way to better represent the actual address hierarchy
in a way that shows the remapping. I don't understand how the remapping
works, but I think what we would need for this is an intermediate
large address space and a ranges property that translate the large
addresses into bus addresses, but with the option of the driver for that
intermediate bus overriding the mapping.

remapped-bus at d0020000 {
	compatible = "marvell,armada-addr-decoding-controller";
	reg = <0xd0020000 0x258>;
	#address-cells = <3>;
	#size-cells = <1>;
	ranges = <0x1 0x1d 0x0     /* device 1 address */
		  0xfff00000	   /* host address */
		  0x100000>	   /* length */
		 <02 0x1e 0x0	   /* device 2 address */
		  0xffe00000	   /* host address */
		  0x100000>	   /* length */

	device at 1.1d.0 {
		compatible = "some-device";
		reg = <0x1 0x1d 0x0 0x5000>
	};
};


	Arnd


From olof at lixom.net  Sat Aug  4 14:27:20 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 4 Aug 2012 11:27:20 -0700
Subject: [GIT PULL][for 3.7] pull request from dt-mmp branch in pxa git
 tree
In-Reply-To: <CAN1soZy-FBmywNLn9a0yanx9ojfB-jnqzYyXwAYr6F1_Khvacg@mail.gmail.com>
References: <CAN1soZy-FBmywNLn9a0yanx9ojfB-jnqzYyXwAYr6F1_Khvacg@mail.gmail.com>
Message-ID: <CAOesGMgwX+Use1wGOhgMe=63F1u8vPrft=FvysYNY+EbsUO5Zw@mail.gmail.com>

Hi,

Looking at your branch more in detail now, and there's a few things I
would like to see changed. See below:


> Daniel Mack (9):
>       RTC: add DT bindings to pxa-rtc
>       MMC: pxa-mci: add DT bindings
>       MTD: pxa3xx-nand: add devicetree bindings
>       GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
>       GPIO: gpio-pxa: fix devicetree functions
>       ARM: pxa: add devicetree code for irq handling
>       ARM: pxa3xx: skip default device initialization when booting via DT
>       ARM: pxa3xx: add generic DT machine code
>       ARM: pxa: add .dtsi files
>
> Haojian Zhuang (6):
>       pinctrl: append new pins and groups in pxa910
>       pinctrl: add pinconf support in pxa3xx
>       pinctrl: support dt in pxa series
>       pinctrl: append new groups of mmp2

None of these have acks from Linus Walleij. They should possibly even
be merged through his tree. If you need them in both trees, or if you
have dependencies on other changes done in this branch, then there's
two options:

* Create one branch that gets pulled into both pinctrl and arm-soc
trees, and we need to agree that neither of us will rebase it
* Collect acks from Linus W and ask him if it's OK that you merge
through arm-soc.

I also don't see any devicetree bindings documented for the PXA
pinctrl bindings?

There are also a bunch of other changes to the tauros2 code that is in
this branch but was not in the pull request. Some of code should
probably go in through Russell's tree since it touches core ARM code.


-Olof


From thomas.petazzoni at free-electrons.com  Sat Aug  4 16:59:38 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 4 Aug 2012 22:59:38 +0200
Subject: [PATCH] [RFC] arm: add documentation describing Marvell
 families of SoC
In-Reply-To: <CAMPhdO8jiTwfdk0DkhjdwMbH3Mt6=XXZKhwNH412UfNbodu7Ww@mail.gmail.com>
References: <1342535201-12907-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <CAMPhdO8jiTwfdk0DkhjdwMbH3Mt6=XXZKhwNH412UfNbodu7Ww@mail.gmail.com>
Message-ID: <20120804225938.6d44a9af@skate>

Hello Eric,

Thanks for all those details! Some comments below.

Le Wed, 18 Jul 2012 02:01:51 +0800,
Eric Miao <eric.y.miao at gmail.com> a ?crit :

> This is so useful to Marvell processor new comers, thanks everyone to
> compile this.
> 
> The PXA side might need a bit modification though, so for historical
> reason there is PXA series as originated back from Intel. So there
> are really those legacy ones:
> 
>   PXA21x/PXA25x/PXA27x/PXA3xx/PXA93x
> 
> The new ones developed after Marvell acquired Intel's XScale biz are:
> 
>   PXA95x/PXA168/PXA910/MMP2
> 
> And among these, they are actually categorized into two flavors:
> 
>   AP with CP: PXA93x/PXA95X/PXA910
>   AP only without CP: the rest of them
> 
> And the ARM cores used are also a bit different:
> 
>   XScale (Intel's ARMv5te compatible):
> PXA21x/PXA25x/PXA27x/PXA3xx/PXA93x Marvell's PJ1 (Marvell's ARMv5te
> compatible): PXA168/PXA910 Marvell's PJ4 (Marvell's ARMv7
> compatible): PXA95x/MMP2

Great, I included all those informations in some form. Will be part of
v3.

> So these are really a bit complicated, by the end of the day, we
> would still go the way as Arnd suggested, that to collapse PXA and
> MMP series into one, so that will be simpler and easier to understand.
> 
> Considering the complications here, I would suggest to simply have a
> single processor line as: PXA/MMP processor line, and list all the
> processor flavors under, whether it's an AP or a AP+CP could be
> individually indicated.

For now, I prefer to keep those as two separate families, so that it
reflects the *current* state of the Linux mach-* directories. The
current state may not be perfect, but it's the current state, so let's
reflect it for now.

Thanks again for your comments!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From thomas.petazzoni at free-electrons.com  Sat Aug  4 17:01:59 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 4 Aug 2012 23:01:59 +0200
Subject: [PATCH] [RFC] arm: add documentation describing Marvell
 families of SoC
In-Reply-To: <alpine.LFD.2.02.1207171452250.9293@xanadu.home>
References: <1342535201-12907-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201207171509.30509.arnd@arndb.de>
 <alpine.LFD.2.02.1207171115161.9293@xanadu.home>
 <alpine.LFD.2.02.1207171452250.9293@xanadu.home>
Message-ID: <20120804230159.12f7108a@skate>

Hello Nicolas,

Le Tue, 17 Jul 2012 14:58:12 -0400 (EDT),
Nicolas Pitre <nico at fluxnic.net> a ?crit :

> > I think I have an old list that was compiled by Lennert.  I'll try to 
> > dig it out in case this document could benefit from it.
> 
> Here's what I've dug out. This is dated October 2007.
> 
> ----- >8
> 
> family			out of order			in order
> ==============================================================================
> no mmu		|				|			     |
> no cache	|	Falcon			|	Falcon D	     |
> "966"		|				|	a.k.a. Dragonite     |
> ==============================================================================
> no mmu		|				|			     |
> cache		|	Osprey			|	Osprey D	     |
> "946"		|				|			     |
> ==============================================================================
> 		|	single issue: Mohawk	|			     |
> mmu		|	a.k.a. Feroceon 1850	|			     |
> cache		|	a.k.a. Feroceon FR-331	|	single issue:	     |
> "926"		|				|	Mohawk D	     |
> 		|	dual issue: Jolteon	|			     |
> 		|	a.k.a. Feroceon 2850	|			     |
> ==============================================================================
> 
> Variants:
> - Falcon DMC - Multi-Core version of the Falcon D
> - Falcon DMT - Multi-Thread version of the Falcon D
> - Osprey DMT - Multi-Thread version of Osprey D
> 
> There is also the Flareon, which is what will be used in Dove:
> - Based on the Jolteon
> - v6/v7 support
> - packaged with L2, VFP, AXI
> 
> All of these cores can be mixed-and-matched with L2, VFP, AXI, wMMXt,
> etc.

Thanks for those details. However, I'm not really able to match those
details against the Marvell SoCs themselves. Could you detail which ARM
core corresponds to which Marvell SoC family, or specific model?

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From thomas.petazzoni at free-electrons.com  Sat Aug  4 17:16:44 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat,  4 Aug 2012 23:16:44 +0200
Subject: [PATCH] arm: add documentation describing Marvell families of SoC
Message-ID: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>

As stated in the introduction of the document, the families of ARM
SoCs at Marvell are very complicated, and it is difficult for
newcomers to understand the organization of this SoC family and how it
relates to the Linux kernel support for those hardware platforms.

This document is only at RFC stage for now, it requires reviews and
comments from the Marvell maintainers, the PXA maintainers and the MMP
maintainers. For correctness of course, but also to add any other
information that would be useful. For example, one of the thing that
wasn't clear how to detail in the documentation is how the SoCs relate
to each other in terms of hardware IP blocks. For example, most of the
Kirkwood/Dove/Armada 370-XP/etc. hardware IPs (I2C, SPI, USB, SATA,
etc.) are identical, while the PXA and MMP families are completely
separate.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Tawfik Bayouk <tawfik at marvell.com>
Cc: Shadi Ammouri <shadi at marvell.com>
Cc: Eran Ben-Avi <benavi at marvell.com>

---
Changes from v2:
 * Mention the plat-<foo> directory that each SoC family is using.
 * Take into account Eric Miao's comments on the PXA/MMP families: add
   PXA21x/PXA25x/PXA26x to the list, mention which processors are
   AP+CP or AP only. Clarify the comments on which SoCs were designed
   by Intel, which ones were designed by Marvell after the acquisition
   of the XScale family.
 * Mention long-term plans regarding the support of those SoC
   families.

Changes from v1:
 * Added publicly available datasheet for the 88F5182 pointed by
   Andrew Lunn.
 * Added publicly available datasheet for the 88F5281 found with
   Google searches
 * Mentionned the Feroceon core name where appropriate, and Sheeva
   where appropriate
 * Fixed the core names for PXA930, PXA935 and PXA955 after comments
   from Arnd Bergmann. Wikipedia is mistakenly suggesting that PXA93x
   are Sheeva-based, and there isn't much information available on the
   web about the 955.
---
 Documentation/arm/Marvell/README |  232 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 232 insertions(+)
 create mode 100644 Documentation/arm/Marvell/README

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
new file mode 100644
index 0000000..8f08a86
--- /dev/null
+++ b/Documentation/arm/Marvell/README
@@ -0,0 +1,232 @@
+ARM Marvell SoCs
+================
+
+This document lists all the ARM Marvell SoCs that are currently
+supported in mainline by the Linux kernel. As the Marvell families of
+SoCs are large and complex, it is hard to understand where the support
+for a particular SoC is available in the Linux kernel. This document
+tries to help in understanding where those SoCs are supported, and to
+match them with their corresponding public datasheet, when available.
+
+Orion family
+------------
+
+  Flavors:
+        88F5082
+        88F5181
+        88F5181L
+        88F5182
+               Datasheet               : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
+               Programmer's User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.pdf
+               User Manual             : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
+        88F5281
+               Datasheet               : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf
+        88F6183
+  Core: Feroceon ARMv5 compatible
+  Linux kernel mach directory: arch/arm/mach-orion5x
+  Linux kernel plat directory: arch/arm/plat-orion
+
+Kirkwood family
+---------------
+
+  Flavors:
+        88F6282 a.k.a Armada 300
+                Product Brief  : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+        88F6283 a.k.a Armada 310
+                Product Brief  : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
+        88F6190
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6190-003_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6192
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6192-003_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6182
+        88F6180
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+        88F6281
+                Product Brief  : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
+  Homepage: http://www.marvell.com/embedded-processors/kirkwood/
+  Core: Feroceon ARMv5 compatible
+  Linux kernel mach directory: arch/arm/mach-kirkwood
+  Linux kernel plat directory: arch/arm/plat-orion
+
+Discovery family
+----------------
+
+  Flavors:
+        MV78100
+                Product Brief  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78100-003_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78100_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+        MV78200
+                Product Brief  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78200-002_WEB.pdf
+                Hardware Spec  : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78200_OpenSource.pdf
+                Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
+        MV76100
+                Not supported by the Linux kernel.
+
+  Core: Feroceon ARMv5 compatible
+
+  Linux kernel mach directory: arch/arm/mach-mv78xx0
+  Linux kernel plat directory: arch/arm/plat-orion
+
+EBU Armada family
+-----------------
+
+  Armada 370 Flavors:
+        88F6710
+        88F6707
+        88F6W11
+
+  Armada XP Flavors:
+        MV78230
+        MV78260
+        MV78460
+
+  Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
+  No public datasheet available.
+
+  Core: Sheeva ARMv7 compatible
+
+  Linux kernel mach directory: arch/arm/mach-mvebu
+  Linux kernel plat directory: none
+
+Avanta family
+-------------
+
+  Flavors:
+       88F6510
+       88F6530P
+       88F6550
+       88F6560
+  Homepage     : http://www.marvell.com/broadband/
+  Product Brief: http://www.marvell.com/broadband/assets/Marvell_Avanta_88F6510_305_060-001_product_brief.pdf
+  No public datasheet available.
+
+  Core: ARMv5 compatible
+
+  Linux kernel mach directory: no code in mainline yet, planned for the future
+  Linux kernel plat directory: no code in mainline yet, planned for the future
+
+Dove family (application processor)
+-----------------------------------
+
+  Flavors:
+        88AP510 a.k.a Armada 510
+                Product Brief   : http://www.marvell.com/application-processors/armada-500/assets/Marvell_Armada510_SoC.pdf
+                Hardware Spec   : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Hardware-Spec.pdf
+                Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
+  Homepage: http://www.marvell.com/application-processors/armada-500/
+  Core: ARMv7 compatible
+  Directory: arch/arm/mach-dove
+
+PXA 2xx/3xx/93x/95x family
+--------------------------
+
+  Flavors:
+        PXA21x, PXA25x, PXA26x
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA270, PXA271, PXA272
+             Product Brief         : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf
+             Design guide          : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf
+             Developers manual     : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_dev_man.pdf
+             Specification         : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf
+             Specification update  : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA300, PXA310, PXA320
+             PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf
+             PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf
+             PXA 320 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA320_PB_R4.pdf
+             Design guide          : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Design_Guide.pdf
+             Developers manual     : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Developers_Manual.zip
+             Specifications        : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_EMTS.pdf
+             Specification Update  : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip
+             Reference Manual      : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf
+             Application processor only
+             Core: ARMv5 XScale core
+        PXA930, PXA935
+             Application processor with Communication processor
+             Core: ARMv5 XScale core
+        PXA955
+             Application processor with Communication processor
+             Core: ARMv7 compatible Sheeva PJ4 core
+
+   Comments:
+
+    * This line of SoCs originates from the XScale family developed by
+      Intel and acquired by Marvell in ~2006. The PXA21x, PXA25x,
+      PXA26x, PXA27x, PXA3xx and PXA93x were developed by Intel, while
+      the later PXA95x were developed by Marvell.
+
+    * Due to their XScale origin, these SoCs have virtually nothing in
+      common with the other (Kirkwood, Dove, etc.) families of Marvell
+      SoCs, except with the MMP/MMP2 family of SoCs.
+
+   Linux kernel mach directory: arch/arm/mach-pxa
+   Linux kernel plat directory: arch/arm/plat-pxa
+
+MMP/MMP2 family (communication processor)
+-----------------------------------------
+
+   Flavors:
+        PXA168, a.k.a Armada 168
+             Homepage             : http://www.marvell.com/application-processors/armada-100/armada-168.jsp
+             Product brief        : http://www.marvell.com/application-processors/armada-100/assets/pxa_168_pb.pdf
+             Hardware manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_datasheet.pdf
+             Software manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_software_manual.pdf
+             Specification update : http://www.marvell.com/application-processors/armada-100/assets/ARMADA16x_Spec_update.pdf
+             Boot ROM manual      : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf
+             App node package     : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf
+             Application processor only
+             Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+        PXA910
+             Homepage             : http://www.marvell.com/communication-processors/pxa910/
+             Product Brief        : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf
+             Application processor with Communication processor
+             Core: ARMv5 compatible Marvell PJ1 (Mohawk)
+        MMP2, a.k.a Armada 610
+             Product Brief        : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf
+             Application processor only
+             Core: ARMv7 compatible Sheeva PJ4 core
+
+   Comments:
+
+    * This line of SoCs originates from the XScale family developed by
+      Intel and acquired by Marvell in ~2006. All the processors of
+      this MMP/MMP2 family were developed by Marvell.
+
+    * Due to their XScale origin, these SoCs have virtually nothing in
+      common with the other (Kirkwood, Dove, etc.) families of Marvell
+      SoCs, except with the PXA family of SoCs listed above.
+
+   Linux kernel mach directory: arch/arm/mach-mmp
+   Linux kernel plat directory: arch/arm/plat-pxa
+
+Long-term plans
+---------------
+
+ * Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
+   mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
+   Marvell EBU (Engineering Business Unit) in a single mach-<foo>
+   directory. The plat-orion/ would therefore disappear.
+
+ * Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
+   directory. The plat-pxa/ would therefore disappear.
+
+Credits
+-------
+
+ Maen Suleiman <maen at marvell.com>
+ Lior Amsalem <alior at marvell.com>
+ Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ Andrew Lunn <andrew at lunn.ch>
+ Nicolas Pitre <nico at fluxnic.net>
+ Eric Miao <eric.y.miao at gmail.com>
-- 
1.7.9.5



From linus.walleij at linaro.org  Sat Aug  4 19:16:20 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 01:16:20 +0200
Subject: [PATCH 2/2] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <1343230539-7196-2-git-send-email-zonque@gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <1343230539-7196-2-git-send-email-zonque@gmail.com>
Message-ID: <CACRpkdY6zn+aigZituo37iq=Mttf9Bhn06nyH-A4zQ6mhsByow@mail.gmail.com>

On Wed, Jul 25, 2012 at 5:35 PM, Daniel Mack <zonque at gmail.com> wrote:

> Provide an of_xlate function for the PXA GPIO chips and make it work for
> devicetree environments.
>
> Successfully tested on a PXA3xx board.
>
> Signed-off-by: Daniel Mack <zonque at gmail.com>

Could the PXA maintainers pls have a look at this patch, if you're working
on DT support especially...

BTW: I guess this is not a fix for issues in the current kernel HEAD?
Is it OK to have this for the next (v3.7) cycle?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 19:20:04 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 01:20:04 +0200
Subject: [PATCH 1/2] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <201207251910.19088.arnd@arndb.de>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <201207251617.21735.arnd@arndb.de> <501036E1.5010309@gmail.com>
 <201207251910.19088.arnd@arndb.de>
Message-ID: <CACRpkdZBzFVmXZZQboe0Thd-7qEZi5iKds4iV7kcVyhD=CX+Jw@mail.gmail.com>

On Wed, Jul 25, 2012 at 9:10 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 25 July 2012, Daniel Mack wrote:
>>
>> Thanks. I somehow lost track about the upstream pathes recently. Who
>> would queue them up now?
>
> Haojian Zhuang is usually the person who picks up PXA patches these days.
> If he prefers, you can also prepare a series and send them directly to
> arm at kernel.org (that's Olof and me, for all practical purposes) for
> integration into the arm-soc tree.

Since these two are in drivers/gpio I can take them through the GPIO
tree if desired, but still need some PXA maintainer to ACK them,
however they haven't really listed themselves as maintainers for the
GPIO driver in MAINTAINERS which would be preferable.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 19:40:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 01:40:50 +0200
Subject: [PATCH v3 5/9] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <1343470061-16879-6-git-send-email-zonque@gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-6-git-send-email-zonque@gmail.com>
Message-ID: <CACRpkdb+N+sP1yA+JRe9Gqh9bHt-Nmx_+fxZKwmddrCcd-1a4g@mail.gmail.com>

On Sat, Jul 28, 2012 at 12:07 PM, Daniel Mack <zonque at gmail.com> wrote:

> Provide an of_xlate function for the PXA GPIO chips and make it work for
> devicetree environments.
>
> Successfully tested on a PXA3xx board.
>
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Are you planning to funnel these through say arm-soc?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 19:46:25 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 01:46:25 +0200
Subject: Sharing resources between several drivers.
In-Reply-To: <201207291419.52526.arnd@arndb.de>
References: <CACKLOr2enmsVqQnJ8JZJJd3z3gGKDKwj74PnWKEk6SwSN=ZoJw@mail.gmail.com>
 <201207291419.52526.arnd@arndb.de>
Message-ID: <CACRpkda8Y1oDP0oQSYH2e5qT=VPGXMop-_FWUS9-XjL3b=WE_g@mail.gmail.com>

On Sun, Jul 29, 2012 at 4:19 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 27 July 2012, javier Martin wrote:
>>
>> What is the right way to request the same memory region from two
>> different drivers? Moreover, how can we guarantee that there won't be
>> any conflicts when accessing these shared resources?
>
> I think the method that Linus Walleij usually recomments for dealing with
> this is to create a combined gpio+pinctrl driver that lives in
> drivers/pinctrl but registers to gpiolib as well.

Yepps.

> Have a look at drivers/pinctrl/pinctrl-nomadik.c for an example of this.

What this and many other drivers run into is the problem of mappings
between GPIOs and pin controller ranges (GPIO ranges).

Currently these are registered by the pin controller and may need
access to the struct gpio_chip which creates an "interesting"
probe order problem. But it can be solved (in not-so-elegant ways).

Long term we want to turn this upside down and have the GPIO
driver portion register it's ranges to the pin controller instead,
using local range GPIO numbers.

Yours,
Linus Walleij


From 21cnbao at gmail.com  Sat Aug  4 19:53:26 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Sun, 5 Aug 2012 07:53:26 +0800
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <CAGsJ_4zYt6fJg9iE65VO4kqc-bD+o8ZuHY=ESjuPwfh-1uAPUw@mail.gmail.com>

2012/8/4 Julia Lawall <Julia.Lawall at lip6.fr>
>
> From: Julia Lawall <Julia.Lawall at lip6.fr>
>
> Fix some problems with the use of devm_ functions.
>
> devm_kzalloc: devm_kfree is not needed
>
> devm_ioremap: iounmap should not be used, no free is needed
>
> devm_request_irq: the devm_free_irq is followed by irq_dispose_mapping.  I
> don't know if it is safe to move the freeing of the irq in this case, so I
> have just un-devm'd this function, since the implicit freeing is never
> taken advantage of.
>
> In the original code failure of of_address_to_resource jumped to free_mem,
> but should have jumped to irq_dispose, since irq_of_parse_and_map has
> completed at this point.
>
> In the original code unmap_mem was after irq_dispose, but it should have
> been before, again since irq_of_parse_and_map has completed at this point.
>
> One of these problems was found using the following semantic match:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @@
> expression x;
> @@
>
> *x = devm_ioremap(...)
> ...
> iounmap(x);
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

Acked-by: Barry Song <Baohua.Song at csr.com>

thanks!

>
> ---
> Not compiled.  Does free_irq actually have to be called before
> irq_dispose_mapping?
>
>  drivers/dma/sirf-dma.c |   23 +++++++----------------
>  1 file changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> index 434ad31..1af9e48 100644
> --- a/drivers/dma/sirf-dma.c
> +++ b/drivers/dma/sirf-dma.c
> @@ -570,21 +570,19 @@ static int __devinit sirfsoc_dma_probe(struct
> platform_device *op)
>
>         if (of_property_read_u32(dn, "cell-index", &id)) {
>                 dev_err(dev, "Fail to get DMAC index\n");
> -               ret = -ENODEV;
> -               goto free_mem;
> +               return -ENODEV;
>         }
>
>         sdma->irq = irq_of_parse_and_map(dn, 0);
>         if (sdma->irq == NO_IRQ) {
>                 dev_err(dev, "Error mapping IRQ!\n");
> -               ret = -EINVAL;
> -               goto free_mem;
> +               return -EINVAL;
>         }
>
>         ret = of_address_to_resource(dn, 0, &res);
>         if (ret) {
>                 dev_err(dev, "Error parsing memory region!\n");
> -               goto free_mem;
> +               goto irq_dispose;
>         }
>
>         regs_start = res.start;
> @@ -597,12 +595,11 @@ static int __devinit sirfsoc_dma_probe(struct
> platform_device *op)
>                 goto irq_dispose;
>         }
>
> -       ret = devm_request_irq(dev, sdma->irq, &sirfsoc_dma_irq, 0,
> DRV_NAME,
> -               sdma);
> +       ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
>         if (ret) {
>                 dev_err(dev, "Error requesting IRQ!\n");
>                 ret = -EINVAL;
> -               goto unmap_mem;
> +               goto irq_dispose;
>         }
>
>         dma = &sdma->dma;
> @@ -652,13 +649,9 @@ static int __devinit sirfsoc_dma_probe(struct
> platform_device *op)
>         return 0;
>
>  free_irq:
> -       devm_free_irq(dev, sdma->irq, sdma);
> +       free_irq(sdma->irq, sdma);
>  irq_dispose:
>         irq_dispose_mapping(sdma->irq);
> -unmap_mem:
> -       iounmap(sdma->base);
> -free_mem:
> -       devm_kfree(dev, sdma);
>         return ret;
>  }
>
> @@ -668,10 +661,8 @@ static int __devexit sirfsoc_dma_remove(struct
> platform_device *op)
>         struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
>
>         dma_async_device_unregister(&sdma->dma);
> -       devm_free_irq(dev, sdma->irq, sdma);
> +       free_irq(sdma->irq, sdma);
>         irq_dispose_mapping(sdma->irq);
> -       iounmap(sdma->base);
> -       devm_kfree(dev, sdma);
>         return 0;
>  }

-barry


From linus.walleij at linaro.org  Sat Aug  4 20:02:53 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:02:53 +0200
Subject: [GIT PULL][for 3.7] pull request from dt-mmp branch in pxa git
 tree
In-Reply-To: <CAOesGMgwX+Use1wGOhgMe=63F1u8vPrft=FvysYNY+EbsUO5Zw@mail.gmail.com>
References: <CAN1soZy-FBmywNLn9a0yanx9ojfB-jnqzYyXwAYr6F1_Khvacg@mail.gmail.com>
 <CAOesGMgwX+Use1wGOhgMe=63F1u8vPrft=FvysYNY+EbsUO5Zw@mail.gmail.com>
Message-ID: <CACRpkdavwK=PZjBsQ+FhJ75rx9nsuV6iae7Hp-sF0qmtnNGdSw@mail.gmail.com>

On Sat, Aug 4, 2012 at 8:27 PM, Olof Johansson <olof at lixom.net> wrote:

> None of these have acks from Linus Walleij. They should possibly even
> be merged through his tree.

I haven't managed to look closer at them until now. It's a bit confusing
since there are several iterations of the patches and two authors
involved, point me to missed patches if I don't see them.

I will assume that you want to send this through the ARM SoC tree
and ACK the stuff that looks good to me.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:04:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:04:23 +0200
Subject: [PATCH 1/6] pinctrl: append new pins and groups in pxa910
In-Reply-To: <1343458722-17127-2-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-2-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkda5B-vCGqER6-gTS70C8f6r3z2UOSbeW_GiVXbGbZZUYA@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
>  drivers/pinctrl/pinctrl-pxa910.c |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:05:30 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:05:30 +0200
Subject: [PATCH 2/6] pinctrl: add pinconf support in pxa3xx
In-Reply-To: <1343458722-17127-3-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-3-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkdatDb3=oD4zC45RumoPy0dteNLtpYS2D4MH_EHfqXFQmg@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

[Please put in a more verbose commit message, this is a pretty big patch!]

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:07:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:07:13 +0200
Subject: [PATCH 3/6] pinctrl: support dt in pxa series
In-Reply-To: <1343458722-17127-4-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-4-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkdbaVvBOmwOcO69Jt6DPV-Wi3jmpWHhfGLgqoiDbE+-7Jw@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Add DT support in PXA168/PXA910/MMP2 pinctrl driver.

[Expand on what that means a bit please]

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:07:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:07:43 +0200
Subject: [PATCH 4/6] pinctrl: append new groups of mmp2
In-Reply-To: <1343458722-17127-5-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-5-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkdYLpYYaX+DLZfF6X54CJ4-mipVLGDxadk9_Bb3DH2XJ7A@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
>  drivers/pinctrl/pinctrl-mmp2.c |    8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:08:06 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:08:06 +0200
Subject: [PATCH 5/6] ARM: mmp: select pinctrl for boards with DT
In-Reply-To: <1343458722-17127-6-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-6-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkdY_hU5u7SKWsbXBwYxUG6XHxr57BB6tU3Ovq8rnNBHrXg@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:09:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:09:13 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CACRpkdYgA1LFODJ01-QRkGbXRQNRS4dUWvCpoGLaHDAWmb98vA@mail.gmail.com>

On Sat, Jul 28, 2012 at 8:58 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>

I have no clue as to whether these are good DT bindings or not, so
leaving this up to the PXA maintainers :-)

You don't need my ACK for this part anyway.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:12:26 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:12:26 +0200
Subject: [PATCH v3 4/9] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <1343470061-16879-5-git-send-email-zonque@gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-5-git-send-email-zonque@gmail.com>
Message-ID: <CACRpkdaJhzzckg12uZrgweoOgC44VNb=0AEdp96AV2O0UM+AnA@mail.gmail.com>

On Sat, Jul 28, 2012 at 12:07 PM, Daniel Mack <zonque at gmail.com> wrote:

> Simplify the code in gpio-pxa.c and make them based on irq_base.
> When not probed from devicetree, initialize irq_base from
> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
> still works.
>
> Only tested on PXA3xx.
>
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>

OK:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

But:

> +#ifdef CONFIG_ARCH_PXA
> +               if (gpio_is_pxa_type(gpio_type))
> +                       irq_base = PXA_GPIO_TO_IRQ(0);
> +#endif
> +#ifdef CONFIG_ARCH_MMP
> +               if (gpio_is_mmp_type(gpio_type))
> +                       irq_base = MMP_GPIO_TO_IRQ(0);
> +#endif

Grrr. Can we think of a way to get rid of these #ifdef:s?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug  4 20:18:33 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 02:18:33 +0200
Subject: [RFC v2] ARM: sched_clock: update epoch_cyc on resume
In-Reply-To: <CAMbhsRSboLABOD8eX4czk8FsG3QmT60RTr+znVCqwWR6ZGhgaw@mail.gmail.com>
References: <1343184588-20239-1-git-send-email-ccross@android.com>
 <CACRpkdZv4p+QT3Y+=-xh5iJ=sr1_aahroxQ535QpzVD9e_ESJA@mail.gmail.com>
 <20120727233829.GB14835@n2100.arm.linux.org.uk>
 <CAMbhsRSGYmu=eyqik23cECsJPfpo6rUqZUa853nkY35XRo4Q_w@mail.gmail.com>
 <CAMbhsRQg4pETrM7cx+aSBzGn3S1LV_x7vo8X3A300vCWTjkFng@mail.gmail.com>
 <CAMbhsRSboLABOD8eX4czk8FsG3QmT60RTr+znVCqwWR6ZGhgaw@mail.gmail.com>
Message-ID: <CACRpkdbY9E6R+fohGsrEHcmeQJUf3m4duVMC=N5=+Q15a6_gjw@mail.gmail.com>

On Fri, Aug 3, 2012 at 3:28 AM, Colin Cross <ccross at android.com> wrote:
> On Fri, Jul 27, 2012 at 8:30 PM, Colin Cross <ccross at android.com> wrote:
>> On Fri, Jul 27, 2012 at 6:15 PM, Colin Cross <ccross at android.com> wrote:
>>> That patch was merged in 3.4, and my patch is on top of it.  Your
>>> patch updates epoch_cyc and epoch_ns in suspend, but if the first call
>>> to cyc_to_sched_clock after resume gets cyc = 0, cyc - epoch_cyc can
>>> be negative, although it will be cast back to a large positive number.
>>>
>>> With my patch, epoch_cyc is updated in resume to whatever
>>> read_sched_clock() returns, and epoch_ns is still set to the suspend
>>> value, so it appears that sched_clock has not changed between
>>> sched_clock_suspend and sched_clock_resume.  It will work with any
>>> timer behavior (reset to 0, reset to random value, or continuing
>>> counting).  The old setup_sched_clock function maintains the old
>>> behavior to appease those who like their 32kHz sched clock to continue
>>> ticking in suspend, although I think it is more correct for all sched
>>> clocks to be faster than 32 kHz (when possible) and stop in suspend.
>>
>> I think the existing code can cause sched_clock to go backwards if the
>> register read by the read function resets to 0 in suspend:
>>
>> In sched_clock_suspend epoch_cyc is updated to 0x00002000.
>>
>> The first sched_clock call after resume gets cyc = 0, returning
>> epoch_ns + cyc_to_ns(0xffffe000)
>>
>> Later, sched_clock gets cyc = 0x5000, returning epoch_ns +
>> cyc_to_ns(0x3000), which will be much smaller than the previous
>> sched_clock value.
>
> Russell, any update on this?  Should sched_clock.c handle read
> functions that go backwards in suspend, or should I modify the read
> function to track an offset in suspend and always return a
> monotonically increasing value across suspend?

Colin, I suggest you put this into Russell's patch tracker so
he can keep track of it from there.

Yours,
Linus Walleij


From robherring2 at gmail.com  Sat Aug  4 21:23:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:23:57 -0500
Subject: [PATCH v2 2/5] ARM: add strstr declaration for decompressors
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344129840-16447-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

With the generic unaligned.h, more kernel headers get pulled in including
dynamic_debug.h which needs strstr. As it is not really used, we only need
a declaration here.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/boot/compressed/decompress.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index f41b38c..9deb56a 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -32,6 +32,9 @@ extern void error(char *);
 #  define Tracecv(c,x)
 #endif
 
+/* Not needed, but used in some headers pulled in by decompressors */
+extern char * strstr(const char * s1, const char *s2);
+
 #ifdef CONFIG_KERNEL_GZIP
 #include "../../../../lib/decompress_inflate.c"
 #endif
-- 
1.7.9.5



From robherring2 at gmail.com  Sat Aug  4 21:23:56 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:23:56 -0500
Subject: [PATCH v2 1/5] ARM: use generic version of identical asm headers
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344129840-16447-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Inspired by the AArgh64 claim that it should be separate from ARM and one
reason was being able to use more asm-generic headers. Doing a diff of
arch/arm/include/asm and include/asm-generic there are numerous asm
headers which are functionally identical to their asm-generic counterparts.
Delete the ARM version and use the generic ones.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/Kbuild     |   15 +++
 arch/arm/include/asm/current.h  |   15 ---
 arch/arm/include/asm/exec.h     |    6 --
 arch/arm/include/asm/ipcbuf.h   |    1 -
 arch/arm/include/asm/msgbuf.h   |   31 ------
 arch/arm/include/asm/param.h    |   31 ------
 arch/arm/include/asm/parport.h  |   18 ----
 arch/arm/include/asm/segment.h  |   11 ---
 arch/arm/include/asm/sembuf.h   |   25 -----
 arch/arm/include/asm/serial.h   |   19 ----
 arch/arm/include/asm/shmbuf.h   |   42 ---------
 arch/arm/include/asm/socket.h   |   72 --------------
 arch/arm/include/asm/sockios.h  |   13 ---
 arch/arm/include/asm/termbits.h |  198 ---------------------------------------
 arch/arm/include/asm/timex.h    |    6 +-
 arch/arm/include/asm/types.h    |   16 ----
 16 files changed, 17 insertions(+), 502 deletions(-)
 delete mode 100644 arch/arm/include/asm/current.h
 delete mode 100644 arch/arm/include/asm/exec.h
 delete mode 100644 arch/arm/include/asm/ipcbuf.h
 delete mode 100644 arch/arm/include/asm/msgbuf.h
 delete mode 100644 arch/arm/include/asm/param.h
 delete mode 100644 arch/arm/include/asm/parport.h
 delete mode 100644 arch/arm/include/asm/segment.h
 delete mode 100644 arch/arm/include/asm/sembuf.h
 delete mode 100644 arch/arm/include/asm/serial.h
 delete mode 100644 arch/arm/include/asm/shmbuf.h
 delete mode 100644 arch/arm/include/asm/socket.h
 delete mode 100644 arch/arm/include/asm/sockios.h
 delete mode 100644 arch/arm/include/asm/termbits.h
 delete mode 100644 arch/arm/include/asm/types.h

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 960abce..6cc8a13 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -5,16 +5,31 @@ header-y += hwcap.h
 generic-y += auxvec.h
 generic-y += bitsperlong.h
 generic-y += cputime.h
+generic-y += current.h
 generic-y += emergency-restart.h
 generic-y += errno.h
+generic-y += exec.h
 generic-y += ioctl.h
+generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += local.h
 generic-y += local64.h
+generic-y += msgbuf.h
+generic-y += param.h
+generic-y += parport.h
 generic-y += percpu.h
 generic-y += poll.h
 generic-y += resource.h
 generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
 generic-y += siginfo.h
 generic-y += sizes.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += termbits.h
+generic-y += timex.h
+generic-y += types.h
diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h
deleted file mode 100644
index 75d21e2..0000000
--- a/arch/arm/include/asm/current.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASMARM_CURRENT_H
-#define _ASMARM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-static inline struct task_struct *get_current(void) __attribute_const__;
-
-static inline struct task_struct *get_current(void)
-{
-	return current_thread_info()->task;
-}
-
-#define current (get_current())
-
-#endif /* _ASMARM_CURRENT_H */
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
deleted file mode 100644
index 7c4fbef..0000000
--- a/arch/arm/include/asm/exec.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARM_EXEC_H
-#define __ASM_ARM_EXEC_H
-
-#define arch_align_stack(x) (x)
-
-#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51..0000000
--- a/arch/arm/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/arm/include/asm/msgbuf.h b/arch/arm/include/asm/msgbuf.h
deleted file mode 100644
index 33b35b9..0000000
--- a/arch/arm/include/asm/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _ASMARM_MSGBUF_H
-#define _ASMARM_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-	struct ipc64_perm msg_perm;
-	__kernel_time_t msg_stime;	/* last msgsnd time */
-	unsigned long	__unused1;
-	__kernel_time_t msg_rtime;	/* last msgrcv time */
-	unsigned long	__unused2;
-	__kernel_time_t msg_ctime;	/* last change time */
-	unsigned long	__unused3;
-	unsigned long  msg_cbytes;	/* current number of bytes on queue */
-	unsigned long  msg_qnum;	/* number of messages in queue */
-	unsigned long  msg_qbytes;	/* max number of bytes on queue */
-	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
-	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-#endif /* _ASMARM_MSGBUF_H */
diff --git a/arch/arm/include/asm/param.h b/arch/arm/include/asm/param.h
deleted file mode 100644
index 8b24bf94..0000000
--- a/arch/arm/include/asm/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  arch/arm/include/asm/param.h
- *
- *  Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_PARAM_H
-#define __ASM_PARAM_H
-
-#ifdef __KERNEL__
-# define HZ		CONFIG_HZ	/* Internal kernel timer frequency */
-# define USER_HZ	100		/* User interfaces are in "ticks" */
-# define CLOCKS_PER_SEC	(USER_HZ)	/* like times() */
-#else
-# define HZ		100
-#endif
-
-#define EXEC_PAGESIZE	4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-/* max length of hostname */
-#define MAXHOSTNAMELEN  64
-
-#endif
-
diff --git a/arch/arm/include/asm/parport.h b/arch/arm/include/asm/parport.h
deleted file mode 100644
index 26e94b0..0000000
--- a/arch/arm/include/asm/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  arch/arm/include/asm/parport.h: ARM-specific parport initialisation
- *
- *  Copyright (C) 1999, 2000  Tim Waugh <tim at cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef __ASMARM_PARPORT_H
-#define __ASMARM_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-	return parport_pc_find_isa_ports (autoirq, autodma);
-}
-
-#endif /* !(_ASMARM_PARPORT_H) */
diff --git a/arch/arm/include/asm/segment.h b/arch/arm/include/asm/segment.h
deleted file mode 100644
index 9e24c21..0000000
--- a/arch/arm/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_ARM_SEGMENT_H
-#define __ASM_ARM_SEGMENT_H
-
-#define __KERNEL_CS   0x0
-#define __KERNEL_DS   0x0
-
-#define __USER_CS     0x1
-#define __USER_DS     0x1
-
-#endif /* __ASM_ARM_SEGMENT_H */
-
diff --git a/arch/arm/include/asm/sembuf.h b/arch/arm/include/asm/sembuf.h
deleted file mode 100644
index 1c02839..0000000
--- a/arch/arm/include/asm/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASMARM_SEMBUF_H
-#define _ASMARM_SEMBUF_H
-
-/* 
- * The semid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-	struct ipc64_perm sem_perm;		/* permissions .. see ipc.h */
-	__kernel_time_t	sem_otime;		/* last semop time */
-	unsigned long	__unused1;
-	__kernel_time_t	sem_ctime;		/* last change time */
-	unsigned long	__unused2;
-	unsigned long	sem_nsems;		/* no. of semaphores in array */
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* _ASMARM_SEMBUF_H */
diff --git a/arch/arm/include/asm/serial.h b/arch/arm/include/asm/serial.h
deleted file mode 100644
index ebb0490..0000000
--- a/arch/arm/include/asm/serial.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/include/asm/serial.h
- *
- *  Copyright (C) 1996 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Changelog:
- *   15-10-1996	RMK	Created
- */
-
-#ifndef __ASM_SERIAL_H
-#define __ASM_SERIAL_H
-
-#define BASE_BAUD	(1843200 / 16)
-
-#endif
diff --git a/arch/arm/include/asm/shmbuf.h b/arch/arm/include/asm/shmbuf.h
deleted file mode 100644
index 2e5c67b..0000000
--- a/arch/arm/include/asm/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _ASMARM_SHMBUF_H
-#define _ASMARM_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-	struct ipc64_perm	shm_perm;	/* operation perms */
-	size_t			shm_segsz;	/* size of segment (bytes) */
-	__kernel_time_t		shm_atime;	/* last attach time */
-	unsigned long		__unused1;
-	__kernel_time_t		shm_dtime;	/* last detach time */
-	unsigned long		__unused2;
-	__kernel_time_t		shm_ctime;	/* last change time */
-	unsigned long		__unused3;
-	__kernel_pid_t		shm_cpid;	/* pid of creator */
-	__kernel_pid_t		shm_lpid;	/* pid of last operator */
-	unsigned long		shm_nattch;	/* no. of current attaches */
-	unsigned long		__unused4;
-	unsigned long		__unused5;
-};
-
-struct shminfo64 {
-	unsigned long	shmmax;
-	unsigned long	shmmin;
-	unsigned long	shmmni;
-	unsigned long	shmseg;
-	unsigned long	shmall;
-	unsigned long	__unused1;
-	unsigned long	__unused2;
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif /* _ASMARM_SHMBUF_H */
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
deleted file mode 100644
index 6433cad..0000000
--- a/arch/arm/include/asm/socket.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef _ASMARM_SOCKET_H
-#define _ASMARM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET	1
-
-#define SO_DEBUG	1
-#define SO_REUSEADDR	2
-#define SO_TYPE		3
-#define SO_ERROR	4
-#define SO_DONTROUTE	5
-#define SO_BROADCAST	6
-#define SO_SNDBUF	7
-#define SO_RCVBUF	8
-#define SO_SNDBUFFORCE	32
-#define SO_RCVBUFFORCE	33
-#define SO_KEEPALIVE	9
-#define SO_OOBINLINE	10
-#define SO_NO_CHECK	11
-#define SO_PRIORITY	12
-#define SO_LINGER	13
-#define SO_BSDCOMPAT	14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED	16
-#define SO_PEERCRED	17
-#define SO_RCVLOWAT	18
-#define SO_SNDLOWAT	19
-#define SO_RCVTIMEO	20
-#define SO_SNDTIMEO	21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION		22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT	23
-#define SO_SECURITY_ENCRYPTION_NETWORK		24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP		29
-#define SCM_TIMESTAMP		SO_TIMESTAMP
-
-#define SO_ACCEPTCONN		30
-
-#define SO_PEERSEC		31
-#define SO_PASSSEC		34
-#define SO_TIMESTAMPNS		35
-#define SCM_TIMESTAMPNS		SO_TIMESTAMPNS
-
-#define SO_MARK			36
-
-#define SO_TIMESTAMPING		37
-#define SCM_TIMESTAMPING	SO_TIMESTAMPING
-
-#define SO_PROTOCOL		38
-#define SO_DOMAIN		39
-
-#define SO_RXQ_OVFL             40
-
-#define SO_WIFI_STATUS		41
-#define SCM_WIFI_STATUS		SO_WIFI_STATUS
-#define SO_PEEK_OFF		42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS		43
-
-#endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/sockios.h b/arch/arm/include/asm/sockios.h
deleted file mode 100644
index a2588a2..0000000
--- a/arch/arm/include/asm/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_ARM_SOCKIOS_H
-#define __ARCH_ARM_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 	0x8901
-#define SIOCSPGRP	0x8902
-#define FIOGETOWN	0x8903
-#define SIOCGPGRP	0x8904
-#define SIOCATMARK	0x8905
-#define SIOCGSTAMP	0x8906		/* Get stamp (timeval) */
-#define SIOCGSTAMPNS	0x8907		/* Get stamp (timespec) */
-
-#endif
diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h
deleted file mode 100644
index 704135d..0000000
--- a/arch/arm/include/asm/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ASM_ARM_TERMBITS_H
-#define __ASM_ARM_TERMBITS_H
-
-typedef unsigned char	cc_t;
-typedef unsigned int	speed_t;
-typedef unsigned int	tcflag_t;
-
-#define NCCS 19
-struct termios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-};
-
-struct termios2 {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-struct ktermios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_line;			/* line discipline */
-	cc_t c_cc[NCCS];		/* control characters */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK	0000001
-#define BRKINT	0000002
-#define IGNPAR	0000004
-#define PARMRK	0000010
-#define INPCK	0000020
-#define ISTRIP	0000040
-#define INLCR	0000100
-#define IGNCR	0000200
-#define ICRNL	0000400
-#define IUCLC	0001000
-#define IXON	0002000
-#define IXANY	0004000
-#define IXOFF	0010000
-#define IMAXBEL	0020000
-#define IUTF8	0040000
-
-/* c_oflag bits */
-#define OPOST	0000001
-#define OLCUC	0000002
-#define ONLCR	0000004
-#define OCRNL	0000010
-#define ONOCR	0000020
-#define ONLRET	0000040
-#define OFILL	0000100
-#define OFDEL	0000200
-#define NLDLY	0000400
-#define   NL0	0000000
-#define   NL1	0000400
-#define CRDLY	0003000
-#define   CR0	0000000
-#define   CR1	0001000
-#define   CR2	0002000
-#define   CR3	0003000
-#define TABDLY	0014000
-#define   TAB0	0000000
-#define   TAB1	0004000
-#define   TAB2	0010000
-#define   TAB3	0014000
-#define   XTABS	0014000
-#define BSDLY	0020000
-#define   BS0	0000000
-#define   BS1	0020000
-#define VTDLY	0040000
-#define   VT0	0000000
-#define   VT1	0040000
-#define FFDLY	0100000
-#define   FF0	0000000
-#define   FF1	0100000
-
-/* c_cflag bit meaning */
-#define CBAUD	0010017
-#define  B0	0000000		/* hang up */
-#define  B50	0000001
-#define  B75	0000002
-#define  B110	0000003
-#define  B134	0000004
-#define  B150	0000005
-#define  B200	0000006
-#define  B300	0000007
-#define  B600	0000010
-#define  B1200	0000011
-#define  B1800	0000012
-#define  B2400	0000013
-#define  B4800	0000014
-#define  B9600	0000015
-#define  B19200	0000016
-#define  B38400	0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE	0000060
-#define   CS5	0000000
-#define   CS6	0000020
-#define   CS7	0000040
-#define   CS8	0000060
-#define CSTOPB	0000100
-#define CREAD	0000200
-#define PARENB	0000400
-#define PARODD	0001000
-#define HUPCL	0002000
-#define CLOCAL	0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD	  002003600000		/* input baud rate */
-#define CMSPAR    010000000000		/* mark or space (stick) parity */
-#define CRTSCTS	  020000000000		/* flow control */
-
-#define IBSHIFT	   16
-
-/* c_lflag bits */
-#define ISIG	0000001
-#define ICANON	0000002
-#define XCASE	0000004
-#define ECHO	0000010
-#define ECHOE	0000020
-#define ECHOK	0000040
-#define ECHONL	0000100
-#define NOFLSH	0000200
-#define TOSTOP	0000400
-#define ECHOCTL	0001000
-#define ECHOPRT	0002000
-#define ECHOKE	0004000
-#define FLUSHO	0010000
-#define PENDIN	0040000
-#define IEXTEN	0100000
-#define EXTPROC	0200000
-
-/* tcflow() and TCXONC use these */
-#define	TCOOFF		0
-#define	TCOON		1
-#define	TCIOFF		2
-#define	TCION		3
-
-/* tcflush() and TCFLSH use these */
-#define	TCIFLUSH	0
-#define	TCOFLUSH	1
-#define	TCIOFLUSH	2
-
-/* tcsetattr uses these */
-#define	TCSANOW		0
-#define	TCSADRAIN	1
-#define	TCSAFLUSH	2
-
-#endif	/* __ASM_ARM_TERMBITS_H */
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce11944..5e71172 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -15,12 +15,10 @@
 #include <asm/arch_timer.h>
 #include <mach/timex.h>
 
-typedef unsigned long cycles_t;
-
 #ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()	({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()	(0)
 #endif
 
+#include <asm-generic/timex.h>
+
 #endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
deleted file mode 100644
index 28beab9..0000000
--- a/arch/arm/include/asm/types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_ARM_TYPES_H
-#define __ASM_ARM_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#endif /* __KERNEL__ */
-
-#endif
-
-- 
1.7.9.5



From robherring2 at gmail.com  Sat Aug  4 21:23:58 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:23:58 -0500
Subject: [PATCH v2 3/5] ARM: use generic unaligned.h
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344129840-16447-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This moves ARM over to the asm-generic/unaligned.h header. This has the
benefit of better code generated especially for ARMv7 on gcc 4.7+
compilers.

As Arnd Bergmann, points out: The asm-generic version uses the "struct"
version for native-endian unaligned access and the "byteshift" version
for the opposite endianess. The current ARM version however uses the
"byteshift" implementation for both.

Thanks to Nicolas Pitre for the excellent analysis:

Test case:

int foo (int *x) { return get_unaligned(x); }
long long bar (long long *x) { return get_unaligned(x); }

With the current ARM version:

foo:
	ldrb	r3, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	r3, r3, asl #16	@ tmp154, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	r3, r3, r1, asl #8	@, tmp155, tmp154, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r3, r2	@ tmp157, tmp155, MEM[(const u8 *)x_1(D)]
	orr	r0, r3, r0, asl #24	@,, tmp157, MEM[(const u8 *)x_1(D) + 3B],
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	mov	r2, #0	@ tmp184,
	ldrb	r5, [r0, #6]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 6B], MEM[(const u8 *)x_1(D) + 6B]
	ldrb	r4, [r0, #5]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 5B], MEM[(const u8 *)x_1(D) + 5B]
	ldrb	ip, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #4]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 4B], MEM[(const u8 *)x_1(D) + 4B]
	mov	r5, r5, asl #16	@ tmp175, MEM[(const u8 *)x_1(D) + 6B],
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	orr	r5, r5, r4, asl #8	@, tmp176, tmp175, MEM[(const u8 *)x_1(D) + 5B],
	ldrb	r6, [r0, #7]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 7B], MEM[(const u8 *)x_1(D) + 7B]
	orr	r5, r5, r1	@ tmp178, tmp176, MEM[(const u8 *)x_1(D) + 4B]
	ldrb	r4, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	ip, ip, asl #16	@ tmp188, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r1, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	ip, ip, r7, asl #8	@, tmp189, tmp188, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r5, r6, asl #24	@,, tmp178, MEM[(const u8 *)x_1(D) + 7B],
	orr	ip, ip, r4	@ tmp191, tmp189, MEM[(const u8 *)x_1(D)]
	orr	ip, ip, r1, asl #24	@, tmp194, tmp191, MEM[(const u8 *)x_1(D) + 3B],
	mov	r1, r3	@,
	orr	r0, r2, ip	@ tmp171, tmp184, tmp194
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

In both cases the code is slightly suboptimal.  One may wonder why
wasting r2 with the constant 0 in the second case for example.  And all
the mov's could be folded in subsequent orr's, etc.

Now with the asm-generic version:

foo:
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	bx	lr	@

bar:
	mov	r3, r0	@ x, x
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	ldr	r1, [r3, #4]	@ unaligned	@,
	bx	lr	@

This is way better of course, but only because this was compiled for
ARMv7. In this case the compiler knows that the hardware can do
unaligned word access.  This isn't that obvious for foo(), but if we
remove the get_unaligned() from bar as follows:

long long bar (long long *x) {return *x; }

then the resulting code is:

bar:
	ldmia	r0, {r0, r1}	@ x,,
	bx	lr	@

So this proves that the presumed aligned vs unaligned cases does have
influence on the instructions the compiler may use and that the above
unaligned code results are not just an accident.

Still... this isn't fully conclusive without at least looking at the
resulting assembly fron a pre ARMv6 compilation.  Let's see with an
ARMv5 target:

foo:
	ldrb	r3, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r2, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r3, r3, r1, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r2, asl #16	@, tmp145, tmp142, tmp143,
	orr	r0, r3, r0, asl #24	@,, tmp145, tmp146,
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r3, [r0, #4]	@ zero_extendqisi2	@ tmp149,
	ldrb	r6, [r0, #5]	@ zero_extendqisi2	@ tmp150,
	ldrb	r5, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r4, [r0, #6]	@ zero_extendqisi2	@ tmp153,
	ldrb	r1, [r0, #7]	@ zero_extendqisi2	@ tmp156,
	ldrb	ip, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r2, r2, r7, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r6, asl #8	@, tmp152, tmp149, tmp150,
	orr	r2, r2, r5, asl #16	@, tmp145, tmp142, tmp143,
	orr	r3, r3, r4, asl #16	@, tmp155, tmp152, tmp153,
	orr	r0, r2, ip, asl #24	@,, tmp145, tmp146,
	orr	r1, r3, r1, asl #24	@,, tmp155, tmp156,
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

Compared to the initial results, this is really nicely optimized and I
couldn't do much better if I were to hand code it myself.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/Kbuild      |    1 +
 arch/arm/include/asm/unaligned.h |   19 -------------------
 2 files changed, 1 insertion(+), 19 deletions(-)
 delete mode 100644 arch/arm/include/asm/unaligned.h

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 6cc8a13..a86cabf 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -33,3 +33,4 @@ generic-y += sockios.h
 generic-y += termbits.h
 generic-y += timex.h
 generic-y += types.h
+generic-y += unaligned.h
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
deleted file mode 100644
index 44593a8..0000000
--- a/arch/arm/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_ARM_UNALIGNED_H
-#define _ASM_ARM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-/*
- * Select endianness
- */
-#ifndef __ARMEB__
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#else
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#endif
-
-#endif /* _ASM_ARM_UNALIGNED_H */
-- 
1.7.9.5



From robherring2 at gmail.com  Sat Aug  4 21:23:55 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:23:55 -0500
Subject: [PATCH v2 0/5] Use more asm-generic headers
Message-ID: <1344129840-16447-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Inspired by the AArgh64 claim that it should be separate from ARM and one
reason was being able to use more asm-generic headers. Doing a diff of
arch/arm/include/asm and include/asm-generic there are numerous asm
headers which are functionally identical to their asm-generic counterparts
and others which can use more of the generic versions.

V2 separates unaligned.h and termios.h changes to separate patches. Also,
it adds a fix for build failures on non-gzip decompressor compile.

Rob

Rob Herring (5):
  ARM: use generic version of identical asm headers
  ARM: add strstr declaration for decompressors
  ARM: use generic unaligned.h
  ARM: use generic termios.h
  ARM: convert asm/irqflags.h to use asm-generic/irqflags.h

 arch/arm/boot/compressed/decompress.c |    3 +
 arch/arm/include/asm/Kbuild           |   17 +++
 arch/arm/include/asm/current.h        |   15 ---
 arch/arm/include/asm/exec.h           |    6 -
 arch/arm/include/asm/ipcbuf.h         |    1 -
 arch/arm/include/asm/irqflags.h       |  131 ++++++++--------------
 arch/arm/include/asm/msgbuf.h         |   31 ------
 arch/arm/include/asm/param.h          |   31 ------
 arch/arm/include/asm/parport.h        |   18 ---
 arch/arm/include/asm/segment.h        |   11 --
 arch/arm/include/asm/sembuf.h         |   25 -----
 arch/arm/include/asm/serial.h         |   19 ----
 arch/arm/include/asm/shmbuf.h         |   42 -------
 arch/arm/include/asm/socket.h         |   72 ------------
 arch/arm/include/asm/sockios.h        |   13 ---
 arch/arm/include/asm/termbits.h       |  198 ---------------------------------
 arch/arm/include/asm/termios.h        |   92 ---------------
 arch/arm/include/asm/timex.h          |    6 +-
 arch/arm/include/asm/types.h          |   16 ---
 arch/arm/include/asm/unaligned.h      |   19 ----
 20 files changed, 67 insertions(+), 699 deletions(-)
 delete mode 100644 arch/arm/include/asm/current.h
 delete mode 100644 arch/arm/include/asm/exec.h
 delete mode 100644 arch/arm/include/asm/ipcbuf.h
 delete mode 100644 arch/arm/include/asm/msgbuf.h
 delete mode 100644 arch/arm/include/asm/param.h
 delete mode 100644 arch/arm/include/asm/parport.h
 delete mode 100644 arch/arm/include/asm/segment.h
 delete mode 100644 arch/arm/include/asm/sembuf.h
 delete mode 100644 arch/arm/include/asm/serial.h
 delete mode 100644 arch/arm/include/asm/shmbuf.h
 delete mode 100644 arch/arm/include/asm/socket.h
 delete mode 100644 arch/arm/include/asm/sockios.h
 delete mode 100644 arch/arm/include/asm/termbits.h
 delete mode 100644 arch/arm/include/asm/termios.h
 delete mode 100644 arch/arm/include/asm/types.h
 delete mode 100644 arch/arm/include/asm/unaligned.h

-- 
1.7.9.5



From robherring2 at gmail.com  Sat Aug  4 21:23:59 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:23:59 -0500
Subject: [PATCH v2 4/5] ARM: use generic termios.h
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344129840-16447-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

As pointed out by Arnd Bergmann, this fixes a couple of issues but will
increase code size:

The original macro user_termio_to_kernel_termios was not endian safe. It
used an unsigned short ptr to access the low bits in a 32-bit word.

Both user_termio_to_kernel_termios and kernel_termios_to_user_termio are
missing error checking on put_user/get_user and copy_to/from_user.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/Kbuild    |    1 +
 arch/arm/include/asm/termios.h |   92 ----------------------------------------
 2 files changed, 1 insertion(+), 92 deletions(-)
 delete mode 100644 arch/arm/include/asm/termios.h

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index a86cabf..8a7196c 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -31,6 +31,7 @@ generic-y += sizes.h
 generic-y += socket.h
 generic-y += sockios.h
 generic-y += termbits.h
+generic-y += termios.h
 generic-y += timex.h
 generic-y += types.h
 generic-y += unaligned.h
diff --git a/arch/arm/include/asm/termios.h b/arch/arm/include/asm/termios.h
deleted file mode 100644
index 293e3f1..0000000
--- a/arch/arm/include/asm/termios.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ASM_ARM_TERMIOS_H
-#define __ASM_ARM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-	unsigned short c_iflag;		/* input mode flags */
-	unsigned short c_oflag;		/* output mode flags */
-	unsigned short c_cflag;		/* control mode flags */
-	unsigned short c_lflag;		/* local mode flags */
-	unsigned char c_line;		/* line discipline */
-	unsigned char c_cc[NCC];	/* control characters */
-};
-
-#ifdef __KERNEL__
-/*	intr=^C		quit=^|		erase=del	kill=^U
-	eof=^D		vtime=\0	vmin=\1		sxtc=\0
-	start=^Q	stop=^S		susp=^Z		eol=\0
-	reprint=^R	discard=^U	werase=^W	lnext=^V
-	eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif
-
-/* modem lines */
-#define TIOCM_LE	0x001
-#define TIOCM_DTR	0x002
-#define TIOCM_RTS	0x004
-#define TIOCM_ST	0x008
-#define TIOCM_SR	0x010
-#define TIOCM_CTS	0x020
-#define TIOCM_CAR	0x040
-#define TIOCM_RNG	0x080
-#define TIOCM_DSR	0x100
-#define TIOCM_CD	TIOCM_CAR
-#define TIOCM_RI	TIOCM_RNG
-#define TIOCM_OUT1	0x2000
-#define TIOCM_OUT2	0x4000
-#define TIOCM_LOOP	0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) {		\
-	unsigned short __tmp;					\
-	get_user(__tmp,&(termio)->x);				\
-	*(unsigned short *) &(termios)->x = __tmp;		\
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-	SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-	copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-	put_user((termios)->c_iflag, &(termio)->c_iflag); \
-	put_user((termios)->c_oflag, &(termio)->c_oflag); \
-	put_user((termios)->c_cflag, &(termio)->c_cflag); \
-	put_user((termios)->c_lflag, &(termio)->c_lflag); \
-	put_user((termios)->c_line,  &(termio)->c_line); \
-	copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif	/* __KERNEL__ */
-
-#endif	/* __ASM_ARM_TERMIOS_H */
-- 
1.7.9.5



From robherring2 at gmail.com  Sat Aug  4 21:24:00 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat,  4 Aug 2012 20:24:00 -0500
Subject: [PATCH v2 5/5] ARM: convert asm/irqflags.h to use
 asm-generic/irqflags.h
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344129840-16447-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

By implmenting arch_local_irq_restore with constant flags, we can use
asm-generic/irqflags.h and remove some of the ARM version of irqflags.h.

Verified the code is equivalent by checking the disassembled code.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/include/asm/irqflags.h |  131 ++++++++++++++-------------------------
 1 file changed, 45 insertions(+), 86 deletions(-)

diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca5..67bfb53 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,88 +8,68 @@
 /*
  * CPU interrupt mask handling.
  */
-#if __LINUX_ARM_ARCH__ >= 6
+#define ARCH_IRQ_DISABLED	PSR_I_BIT
+#define ARCH_IRQ_ENABLED	0
 
-static inline unsigned long arch_local_irq_save(void)
+static inline unsigned long arch_local_save_flags(void)
 {
 	unsigned long flags;
 
 	asm volatile(
-		"	mrs	%0, cpsr	@ arch_local_irq_save\n"
-		"	cpsid	i"
+		"	mrs	%0, cpsr	@ arch_local_save_flags\n"
 		: "=r" (flags) : : "memory", "cc");
 	return flags;
 }
 
-static inline void arch_local_irq_enable(void)
+static inline void constant_arch_local_irq_restore(unsigned long flags)
 {
-	asm volatile(
-		"	cpsie i			@ arch_local_irq_enable"
-		:
-		:
-		: "memory", "cc");
+#if __LINUX_ARM_ARCH__ >= 6
+	if (flags == ARCH_IRQ_ENABLED)
+		asm volatile(
+			"	cpsie i			@ constant_arch_local_irq_restore"
+			: : : "memory", "cc");
+	else if (flags == ARCH_IRQ_DISABLED)
+		asm volatile(
+			"	cpsid i			@ constant_arch_local_irq_restore"
+			: : : "memory", "cc");
+#else
+	unsigned long temp;
+	if (flags == ARCH_IRQ_ENABLED)
+		asm volatile(
+			"	mrs	%0, cpsr	@ constant_arch_local_irq_restore\n"
+			"	bic	%0, %0, #128\n"
+			"	msr	cpsr_c, %0"
+			: "=r" (temp)
+			:
+			: "memory", "cc");
+	else if (flags == ARCH_IRQ_DISABLED)
+		asm volatile(
+			"	mrs	%0, cpsr	@ constant_arch_local_irq_restore\n"
+			"	orr	%0, %0, #128\n"
+			"	msr	cpsr_c, %0"
+			: "=r" (temp)
+			:
+			: "memory", "cc");
+#endif
 }
 
-static inline void arch_local_irq_disable(void)
+static inline void _arch_local_irq_restore(unsigned long flags)
 {
-	asm volatile(
-		"	cpsid i			@ arch_local_irq_disable"
-		:
+		asm volatile(
+		"	msr	cpsr_c, %0	@ _arch_local_irq_restore"
 		:
+		: "r" (flags)
 		: "memory", "cc");
 }
 
+#define arch_local_irq_restore(flags) \
+	(__builtin_constant_p(flags) ? constant_arch_local_irq_restore(flags) : \
+	_arch_local_irq_restore(flags))
+
+#if __LINUX_ARM_ARCH__ >= 6
 #define local_fiq_enable()  __asm__("cpsie f	@ __stf" : : : "memory", "cc")
 #define local_fiq_disable() __asm__("cpsid f	@ __clf" : : : "memory", "cc")
 #else
-
-/*
- * Save the current interrupt enable state & disable IRQs
- */
-static inline unsigned long arch_local_irq_save(void)
-{
-	unsigned long flags, temp;
-
-	asm volatile(
-		"	mrs	%0, cpsr	@ arch_local_irq_save\n"
-		"	orr	%1, %0, #128\n"
-		"	msr	cpsr_c, %1"
-		: "=r" (flags), "=r" (temp)
-		:
-		: "memory", "cc");
-	return flags;
-}
-
-/*
- * Enable IRQs
- */
-static inline void arch_local_irq_enable(void)
-{
-	unsigned long temp;
-	asm volatile(
-		"	mrs	%0, cpsr	@ arch_local_irq_enable\n"
-		"	bic	%0, %0, #128\n"
-		"	msr	cpsr_c, %0"
-		: "=r" (temp)
-		:
-		: "memory", "cc");
-}
-
-/*
- * Disable IRQs
- */
-static inline void arch_local_irq_disable(void)
-{
-	unsigned long temp;
-	asm volatile(
-		"	mrs	%0, cpsr	@ arch_local_irq_disable\n"
-		"	orr	%0, %0, #128\n"
-		"	msr	cpsr_c, %0"
-		: "=r" (temp)
-		:
-		: "memory", "cc");
-}
-
 /*
  * Enable FIQs
  */
@@ -122,34 +102,13 @@ static inline void arch_local_irq_disable(void)
 
 #endif
 
-/*
- * Save the current interrupt enable state.
- */
-static inline unsigned long arch_local_save_flags(void)
-{
-	unsigned long flags;
-	asm volatile(
-		"	mrs	%0, cpsr	@ local_save_flags"
-		: "=r" (flags) : : "memory", "cc");
-	return flags;
-}
-
-/*
- * restore saved IRQ & FIQ state
- */
-static inline void arch_local_irq_restore(unsigned long flags)
-{
-	asm volatile(
-		"	msr	cpsr_c, %0	@ local_irq_restore"
-		:
-		: "r" (flags)
-		: "memory", "cc");
-}
-
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
 	return flags & PSR_I_BIT;
 }
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include <asm-generic/irqflags.h>
 
 #endif
 #endif
-- 
1.7.9.5



From haojian.zhuang at gmail.com  Sat Aug  4 22:56:22 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 10:56:22 +0800
Subject: [PATCH v3 4/9] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <CACRpkdaJhzzckg12uZrgweoOgC44VNb=0AEdp96AV2O0UM+AnA@mail.gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-5-git-send-email-zonque@gmail.com>
 <CACRpkdaJhzzckg12uZrgweoOgC44VNb=0AEdp96AV2O0UM+AnA@mail.gmail.com>
Message-ID: <CAN1soZzOTMChr7WQzguH_CPQ8s=tyrsjwmAYNSBAVeMtwRE2uA@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:12 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sat, Jul 28, 2012 at 12:07 PM, Daniel Mack <zonque at gmail.com> wrote:
>
>> Simplify the code in gpio-pxa.c and make them based on irq_base.
>> When not probed from devicetree, initialize irq_base from
>> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
>> still works.
>>
>> +#ifdef CONFIG_ARCH_PXA
>> +               if (gpio_is_pxa_type(gpio_type))
>> +                       irq_base = PXA_GPIO_TO_IRQ(0);
>> +#endif
>> +#ifdef CONFIG_ARCH_MMP
>> +               if (gpio_is_mmp_type(gpio_type))
>> +                       irq_base = MMP_GPIO_TO_IRQ(0);
>> +#endif
>
> Grrr. Can we think of a way to get rid of these #ifdef:s?
>

It's used for non-DT mode. This driver is used in both arch-pxa
and arch-mmp. Since we use static irq allocation in non-DT mode,
we have to use this kind of code to get irq_base.

What Daniel did is only simplifying the code.

Regards
Haojian


From haojian.zhuang at gmail.com  Sat Aug  4 22:57:53 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 10:57:53 +0800
Subject: [GIT PULL][for 3.7] pull request from dt-mmp branch in pxa git
 tree
In-Reply-To: <CACRpkdavwK=PZjBsQ+FhJ75rx9nsuV6iae7Hp-sF0qmtnNGdSw@mail.gmail.com>
References: <CAN1soZy-FBmywNLn9a0yanx9ojfB-jnqzYyXwAYr6F1_Khvacg@mail.gmail.com>
 <CAOesGMgwX+Use1wGOhgMe=63F1u8vPrft=FvysYNY+EbsUO5Zw@mail.gmail.com>
 <CACRpkdavwK=PZjBsQ+FhJ75rx9nsuV6iae7Hp-sF0qmtnNGdSw@mail.gmail.com>
Message-ID: <CAN1soZwOuccKr-N4gRjKRkZ6yWG-767wGdPvDSvKnoecgUA1Dg@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:02 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sat, Aug 4, 2012 at 8:27 PM, Olof Johansson <olof at lixom.net> wrote:
>
>> None of these have acks from Linus Walleij. They should possibly even
>> be merged through his tree.
>
> I haven't managed to look closer at them until now. It's a bit confusing
> since there are several iterations of the patches and two authors
> involved, point me to missed patches if I don't see them.
>
> I will assume that you want to send this through the ARM SoC tree
> and ACK the stuff that looks good to me.
>
> Yours,
> Linus Walleij

Thanks. I'll append your Ack and send the pull quest again.

Regards
Haojian


From haojian.zhuang at gmail.com  Sat Aug  4 22:58:57 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 10:58:57 +0800
Subject: [PATCH v3 5/9] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <CACRpkdb+N+sP1yA+JRe9Gqh9bHt-Nmx_+fxZKwmddrCcd-1a4g@mail.gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-6-git-send-email-zonque@gmail.com>
 <CACRpkdb+N+sP1yA+JRe9Gqh9bHt-Nmx_+fxZKwmddrCcd-1a4g@mail.gmail.com>
Message-ID: <CAN1soZywD8QcOn3W4z4n-E87_ZJhtufYDR6390T-zuqzv9T92Q@mail.gmail.com>

On Sun, Aug 5, 2012 at 7:40 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sat, Jul 28, 2012 at 12:07 PM, Daniel Mack <zonque at gmail.com> wrote:
>
>> Provide an of_xlate function for the PXA GPIO chips and make it work for
>> devicetree environments.
>>
>> Successfully tested on a PXA3xx board.
>>
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>> Acked-by: Arnd Bergmann <arnd at arndb.de>
>
> Are you planning to funnel these through say arm-soc?
>
> Yours,
> Linus Walleij

Yes, Daniel plans to go through arm-soc. And I merged it into pxa git tree.

Regards
Haojian


From haojian.zhuang at gmail.com  Sat Aug  4 23:52:11 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 11:52:11 +0800
Subject: [PATCH 2/2] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <CACRpkdY6zn+aigZituo37iq=Mttf9Bhn06nyH-A4zQ6mhsByow@mail.gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <1343230539-7196-2-git-send-email-zonque@gmail.com>
 <CACRpkdY6zn+aigZituo37iq=Mttf9Bhn06nyH-A4zQ6mhsByow@mail.gmail.com>
Message-ID: <CAN1soZxzGeJWbG9g_j1L=gG42SE6LUt_W1vJwu61OSMHdcgAbQ@mail.gmail.com>

On Sun, Aug 5, 2012 at 7:16 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Jul 25, 2012 at 5:35 PM, Daniel Mack <zonque at gmail.com> wrote:
>
>> Provide an of_xlate function for the PXA GPIO chips and make it work for
>> devicetree environments.
>>
>> Successfully tested on a PXA3xx board.
>>
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>
> Could the PXA maintainers pls have a look at this patch, if you're working
> on DT support especially...
>
> BTW: I guess this is not a fix for issues in the current kernel HEAD?
> Is it OK to have this for the next (v3.7) cycle?
>
It's a real fix. Since of_get_named_gpio_flags() needs to get flags of gpio.
This function is widely used in mmc/usb/... drivers. So it requires
vendor's gpio
driver to support parse flags from DT script.

gpio-pxa driver doesn't support flags before. Now Daniel's patch can
fix this issue.
So I'm OK on this patch.

Regards
Haojian


From haojian.zhuang at gmail.com  Sun Aug  5 00:07:17 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 12:07:17 +0800
Subject: [GIT PULL][for 3.7 v2] pull request from dt_mmp branch in pxa git tree
Message-ID: <CAN1soZxXHL4X081RuhPkVvCB7v3jxY5A-O-L6dfYQ7EWB0=opA@mail.gmail.com>

Hi Olof & Arnd,

Please help to merge these patches from dt_mmp branch in pxa git tree.

It's the V2 version. The changes are in below.
1. Add Linus's Ack in pinctrl driver.
2. Add chao's & haojian's patches for Tauros2 cache.

Regards
Haojian

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git dt_mmp

for you to fetch changes up to a0b7a07b323a66b613a040d9fefd148f1cc7a2ed:

  ARM: mmp: enable tauros2 cache in mmp2 dt (2012-08-05 12:03:19 +0800)

----------------------------------------------------------------
Chao Xie (7):
      ARM: pxa: support CKENC in clk_enable
      gpio: pxa: add chain_eneter and chain_exit for irq handler
      ARM: cache: fix uninitialized ptr in tauros2_init
      ARM: cache: add cputype.h for tauros2
      ARM: cache: add extra feature enable for tauros2
      ARM: mmp&dove: modify tauros2_init call
      ARM: cache: add dt support for tauros2 cache

Daniel Mack (8):
      RTC: add DT bindings to pxa-rtc
      MTD: pxa3xx-nand: add devicetree bindings
      GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
      GPIO: gpio-pxa: fix devicetree functions
      ARM: pxa: add devicetree code for irq handling
      ARM: pxa3xx: skip default device initialization when booting via DT
      ARM: pxa3xx: add generic DT machine code
      ARM: pxa: add .dtsi files

Haojian Zhuang (8):
      pinctrl: append new pins and groups in pxa910
      pinctrl: add pinconf support in pxa3xx
      pinctrl: support dt in pxa series
      pinctrl: append new groups of mmp2
      ARM: mmp: select pinctrl for boards with DT
      ARM: dts: add pinctrl in PXA DT files
      ARM: mmp: enable tauros2 cache in pxa910
      ARM: mmp: enable tauros2 cache in mmp2 dt

 .../devicetree/bindings/arm/mrvl/tauros2.txt       |   17 +
 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |   31 ++
 .../bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt       |   35 +++
 Documentation/devicetree/bindings/rtc/pxa-rtc.txt  |   14 +
 arch/arm/boot/dts/mmp2-brownstone.dts              |   51 +++
 arch/arm/boot/dts/mmp2.dtsi                        |   10 +
 arch/arm/boot/dts/pxa168.dtsi                      |    5 +
 arch/arm/boot/dts/pxa27x.dtsi                      |   14 +
 arch/arm/boot/dts/pxa2xx.dtsi                      |  132 ++++++++
 arch/arm/boot/dts/pxa3xx.dtsi                      |   32 ++
 arch/arm/boot/dts/pxa910-dkb.dts                   |   47 +++
 arch/arm/boot/dts/pxa910.dtsi                      |   10 +
 arch/arm/include/asm/hardware/cache-tauros2.h      |    5 +-
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-mmp/Kconfig                          |    2 +
 arch/arm/mach-mmp/mmp2.c                           |    2 +-
 arch/arm/mach-mmp/pxa910.c                         |    4 +
 arch/arm/mach-pxa/Kconfig                          |   12 +
 arch/arm/mach-pxa/Makefile                         |    3 +
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    8 +-
 arch/arm/mach-pxa/irq.c                            |  131 ++++++--
 arch/arm/mach-pxa/pxa-dt.c                         |   63 ++++
 arch/arm/mach-pxa/pxa3xx.c                         |   21 +-
 arch/arm/mm/cache-tauros2.c                        |   83 +++--
 drivers/gpio/gpio-pxa.c                            |  103 +++----
 drivers/mtd/nand/pxa3xx_nand.c                     |   85 ++++-
 drivers/pinctrl/pinctrl-mmp2.c                     |   18 +-
 drivers/pinctrl/pinctrl-pxa168.c                   |   10 +-
 drivers/pinctrl/pinctrl-pxa3xx.c                   |  325 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-pxa3xx.h                   |   17 +
 drivers/pinctrl/pinctrl-pxa910.c                   |   16 +-
 drivers/rtc/rtc-pxa.c                              |   11 +
 32 files changed, 1195 insertions(+), 124 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
 create mode 100644
Documentation/devicetree/bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
 create mode 100644 arch/arm/boot/dts/pxa27x.dtsi
 create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
 create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
 create mode 100644 arch/arm/mach-pxa/pxa-dt.c


From shawn.guo at linaro.org  Sun Aug  5 02:01:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 14:01:25 +0800
Subject: [PATCH 1/4] gpio/mxc: remove redundant shadow variables initialization
Message-ID: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>

With commit 3e11f7b (gpio/generic: initialize basic_mmio_gpio shadow
variables properly) in place, the shadow variables initialization is
being done in generic driver bgpio_init call.

Remove the redundant shadow variables initialization from gpio-mxc
driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/gpio/gpio-mxc.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 4db460b..76e8cda 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -466,8 +466,6 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 
 	port->bgc.gc.to_irq = mxc_gpio_to_irq;
 	port->bgc.gc.base = pdev->id * 32;
-	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
-	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
 
 	err = gpiochip_add(&port->bgc.gc);
 	if (err)
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 02:01:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 14:01:26 +0800
Subject: [PATCH 2/4] gpio/mxc: specify gpio base for device tree probe
In-Reply-To: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344146488-9496-2-git-send-email-shawn.guo@linaro.org>

Currently, unlike the non-DT probe where the gpio base is specified
with pdev->id, the DT probe uses the base dynamically allocated by
gpio core, which uses a completely different numbering scheme.  This
causes two issues to user space applications which access sysfs entry
/sys/class/gpio/gpioN.

* It breaks the compatibility with user space applications between
  non-DT and DT kernels.

* It's not intuitive and sometimes hard for users to map the Linux
  gpio number to the actual hardware pin.

Use alias to identify the gpio port/bank, and then the gpio base
can be specified with port id to solve above issues.  If alias is not
defined in device tree, the base number dynamically allocated by gpio
core will be used.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/gpio/gpio-mxc.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 76e8cda..80f44bb 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -465,7 +465,8 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 		goto out_iounmap;
 
 	port->bgc.gc.to_irq = mxc_gpio_to_irq;
-	port->bgc.gc.base = pdev->id * 32;
+	port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
+					     pdev->id * 32;
 
 	err = gpiochip_add(&port->bgc.gc);
 	if (err)
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 02:01:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 14:01:27 +0800
Subject: [PATCH 3/4] gpio/mxs: specify gpio base for device tree probe
In-Reply-To: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344146488-9496-3-git-send-email-shawn.guo@linaro.org>

Currently, unlike the non-DT probe where the gpio base is specified
with pdev->id, the DT probe uses the base dynamically allocated by
gpio core, which uses a completely different numbering scheme.  This
causes two issues to user space applications which access sysfs entry
/sys/class/gpio/gpioN.

* It breaks the compatibility with user space applications between
  non-DT and DT kernels.

* It's not intuitive and sometimes hard for users to map the Linux
  gpio number to the actual hardware pin.

Use alias to identify the gpio port/bank, and then the gpio base
can be specified with port id to solve above issues.  If alias is not
defined in device tree, the base number dynamically allocated by gpio
core will be used.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/gpio/gpio-mxs.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 39e4956..09687ce 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -290,7 +290,8 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 		return err;
 
 	port->bgc.gc.to_irq = mxs_gpio_to_irq;
-	port->bgc.gc.base = port->id * 32;
+	port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
+					     pdev->id * 32;
 
 	err = gpiochip_add(&port->bgc.gc);
 	if (err) {
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 02:01:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 14:01:28 +0800
Subject: [PATCH 4/4] ARM: dts: imx: add alias for gpio
In-Reply-To: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344146488-9496-4-git-send-email-shawn.guo@linaro.org>

Add alias for gpio nodes, so that gpio driver can identify the port
number and then specify a sensible gpio base rather than using the
one dynamically allocated by gpio core.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx27.dtsi |    6 ++++++
 arch/arm/boot/dts/imx51.dtsi |    4 ++++
 arch/arm/boot/dts/imx53.dtsi |    7 +++++++
 arch/arm/boot/dts/imx6q.dtsi |    7 +++++++
 4 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 00bae3a..5303ab6 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -19,6 +19,12 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
 	};
 
 	avic: avic-interrupt-controller at e0000000 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 53cbaa3..aba28dc 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -17,6 +17,10 @@
 		serial0 = &uart1;
 		serial1 = &uart2;
 		serial2 = &uart3;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
 	};
 
 	tzic: tz-interrupt-controller at e0000000 {
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index fc79cdc..cd37165 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -19,6 +19,13 @@
 		serial2 = &uart3;
 		serial3 = &uart4;
 		serial4 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
 	};
 
 	tzic: tz-interrupt-controller at 0fffc000 {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d3c64b..fd57079 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -19,6 +19,13 @@
 		serial2 = &uart3;
 		serial3 = &uart4;
 		serial4 = &uart5;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
 	};
 
 	cpus {
-- 
1.7.5.4




From dirk.behme at gmail.com  Sun Aug  5 02:36:45 2012
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sun, 05 Aug 2012 08:36:45 +0200
Subject: [PATCH v2 2/3] mtd: nand: Let MTD_NAND_GPMI_NAND depend on MXS_DMA
In-Reply-To: <20120803100711.GC24458@pengutronix.de>
References: <1343215100-24005-1-git-send-email-festevam@gmail.com>
 <1343215100-24005-2-git-send-email-festevam@gmail.com>
 <20120803100711.GC24458@pengutronix.de>
Message-ID: <501E147D.5050707@gmail.com>

On 03.08.2012 12:07, Sascha Hauer wrote:
> On Wed, Jul 25, 2012 at 08:18:19AM -0300, Fabio Estevam wrote:
>> From: Fabio Estevam<fabio.estevam at freescale.com>
>>
>> MTD_NAND_GPMI_NAND driver depends on MXS_DMA to be selected, otherwise the following error happens
>> for imx_v6_v7_defconfig:
>>
>> drivers/built-in.o: In function `gpmi_dma_filter':
>> clk-fixed-factor.c:(.text+0xb124c): undefined reference to `mxs_dma_is_apbh'
>> make: *** [vmlinux] Error 1
>>
>> Signed-off-by: Fabio Estevam<fabio.estevam at freescale.com>
>
> Acked-by: Sascha Hauer<s.hauer at pengutronix.de>
>
> As mentioned elsewhere in this thread: We should not select user visible
> options, so this patch is the only thing we can do atm (apart from
> 'fixing the tools' as David mentioned, but this is out of scope for an
> -rc kernel)

I asked Shawn about this and it seems that this patch is the way to go 
for the moment. So:

Acked-by: Dirk Behme <dirk.behme at gmail.com>

David: Artem: Building recent 3.6-rc1mainline with imx_v6_v7_defconfig 
is broken. We need this patch to get it working, again.

It would be nice if this patch could go as a fix into 3.6-rcX mainline 
asap. Could you help with this?

Many thanks and best regards

Dirk

> Additionally the imx_v6_v7_defconfig should be adjusted so that the gpmi
> nand driver actually gets built.
>
> Sascha
>
>> ---
>> Changes since v1:
>> - Use 'depends' rather than 'select'
>>   drivers/mtd/nand/Kconfig |    1 +
>>   1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index a5d8a1b..da52c7d 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -463,6 +463,7 @@ config MTD_NAND_NANDSIM
>>   config MTD_NAND_GPMI_NAND
>>           bool "GPMI NAND Flash Controller driver"
>>           depends on MTD_NAND&&  (SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q)
>> +	depends on MXS_DMA
>>           help
>>   	 Enables NAND Flash support for IMX23, IMX28 or IMX6.
>>   	 The GPMI controller is very powerful, with the help of BCH
>> --
>> 1.7.1
>>
>>
>



From grinberg at compulab.co.il  Sun Aug  5 04:31:40 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 05 Aug 2012 11:31:40 +0300
Subject: [PATCH 1/2] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <1343230539-7196-1-git-send-email-zonque@gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
Message-ID: <501E2F6C.4050507@compulab.co.il>

Hi Daniel,

On 07/25/12 18:35, Daniel Mack wrote:
> Simplify the code in gpio-pxa.c and make them based on irq_base.
> When not probed from devicetree, initialize irq_base from
> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
> still works.
> 
> Only tested on PXA3xx.
> 
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> ---
>  drivers/gpio/gpio-pxa.c |   70 +++++++++++------------------------------------
>  1 file changed, 16 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
> index 58a6a63..6d0cb9d 100644
> --- a/drivers/gpio/gpio-pxa.c
> +++ b/drivers/gpio/gpio-pxa.c

[...]

> @@ -564,10 +516,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
>  	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
>  
>  	ret = pxa_gpio_probe_dt(pdev);
> -	if (ret < 0)
> +	if (ret < 0) {
>  		pxa_last_gpio = pxa_gpio_nums();
> -	else
> +#ifdef CONFIG_ARCH_PXA
> +		if (gpio_is_pxa_type(gpio_type))
> +			irq_base = PXA_GPIO_TO_IRQ(0);
> +#endif
> +#ifdef CONFIG_ARCH_MMP
> +		if (gpio_is_mmp_type(gpio_type))
> +			irq_base = MMP_GPIO_TO_IRQ(0);
> +#endif

The ifdes above do not look essential.
Can't we drop them and just have else if ... else if?

> +	} else {
>  		use_of = 1;
> +	}
> +
>  	if (!pxa_last_gpio)
>  		return -EINVAL;
>  

-- 
Regards,
Igor.


From u.kleine-koenig at pengutronix.de  Sun Aug  5 04:39:26 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sun, 5 Aug 2012 10:39:26 +0200
Subject: [PATCH] mtd: mxc_nand: Fix compiler warnings
In-Reply-To: <501D4405.6030900@googlemail.com>
References: <1343466310-14584-1-git-send-email-dirk.behme@gmail.com>
 <20120730073454.GI1528@pengutronix.de>
 <501D4405.6030900@googlemail.com>
Message-ID: <20120805083926.GL2626@pengutronix.de>

On Sat, Aug 04, 2012 at 05:47:17PM +0200, Dirk Behme wrote:
> On 30.07.2012 09:34, Uwe Kleine-K?nig wrote:
> >Hello,
> >
> >On Sat, Jul 28, 2012 at 11:05:10AM +0200, Dirk Behme wrote:
> >>From: Dirk Behme<dirk.behme at googlemail.com>
> >>
> >>Fix the compiler warnings
> >>
> >>drivers/mtd/nand/mxc_nand.c:1267: warning: initialization discards qualifiers from pointer target type
> >>drivers/mtd/nand/mxc_nand.c:1270: warning: initialization discards qualifiers from pointer target type
> >>drivers/mtd/nand/mxc_nand.c:1273: warning: initialization discards qualifiers from pointer target type
> >>drivers/mtd/nand/mxc_nand.c:1276: warning: initialization discards qualifiers from pointer target type
> >These should be gone in next already.
> 
> Hmm, which next?
> 
> I tried linux-next [1] from today (next-20120803, 55fa9961f) and still get
next-20120725 contained 98d7bbb9929bcc14e11ac8a55245a4f2dc174e17, don't
konw why it isn't included in the newer next snapshorts.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From xinyuansug at sina.cn  Sun Aug  5 04:49:46 2012
From: xinyuansug at sina.cn (=?GB2312?B?zdi7xMWj?=)
Date: Sun, 5 Aug 2012 16:49:46 +0800
Subject: =?GB2312?B?uPfOu8DPz+fT0NKq17DQ3re/19O1xNXSztI=?=
Message-ID: <c6bfaf$1dt3eh2@irja2-172.sinamail.sina.com.cn>

????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????30%??40%??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
 ??????????????????????????????????????20%?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? 

????
????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????
????????????
	1.??????------ ???????? ????
	?????????????????????????????????????????????????????????????????????????????????????????????????????????????? ??
	2.??????-------?????? ?????????????? ??
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	3.??????-------???????? ??
	????????30%??30%??30%??10%???????????????????????????????????????????????????????????????????????????????????????????????????? ??
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	5.??????---???????? ????
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	6.??????---???????? ????
???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? ????
	7.??????--???????? ????
????????????????????????????????????????????????????????????????????????????
 ??8.??????--.????????
    ??????????????????????????????????????????????????????????????????????????????????????????????????????????

??????www.sztopnew.com

??????????0755??36537697

????????????

????????????????????888??????????707


From u.kleine-koenig at pengutronix.de  Sun Aug  5 04:54:34 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sun, 5 Aug 2012 10:54:34 +0200
Subject: [PATCH v2 00/25] make *struct of_device_id.data const
In-Reply-To: <1343034810-3386-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343034810-3386-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120805085434.GM2626@pengutronix.de>

Hello,

> this is the 2nd version of this series whose goal is to make struct
> of_device_id.data const. Conceptually a driver must not modify the data
> contained there so making it const is the right thing.

I rebased my branch at:

	git://git.pengutronix.de/git/ukl/linux.git ofdeviceiddata

on top of v3.6-rc1 and retested the arm and powerpc defconfigs and a
powerpc allyesconfig. The result is still the same, i.e. a new warning
in drivers/regulator/twl-regulator.c because the probe routine modifies
the of_match table.

The series was contained in next up to next-20120725 (as commit

	100e8f5 (Merge branch 'ofdeviceiddata' of git://git.pengutronix.de/git/ukl/linux into late/warnings)

with an encoding error in the commit log btw). Don't know why it was
dropped from next. (late/warnings didn't show up in next-20120725's
arch/arm/arm-soc-for-next-contents.txt, maybe that's the reason?)

Compared to v2 of the series this drops two patches that made it in
during the v3.6 merge window.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.pengutronix.de/git/ukl/linux.git ofdeviceiddata

for you to fetch changes up to e22bd8177efeec9463dc2fc40bd172c717d0bd07:

  can: mpc5xxx_can: make data used as *of_device_id.data const (2012-08-03 13:58:41 +0200)

----------------------------------------------------------------
Arnd Bergmann (6):
      watchdog/mpc8xxx: add a const qualifier
      powerpc/fsl_msi: drop unneeded cast to non-const pointer
      mfd/da9052: make i2c_device_id array const
      i2c/mpc: make data used as *of_device_id.data const
      macintosh/mediabay: make data used as *of_device_id.data const
      can: mpc5xxx_can: make data used as *of_device_id.data const

Uwe Kleine-K?nig (17):
      spi/imx: make spi_imx_data.devtype_data member point to const data
      spi/spi-omap2-mcspi: add a const qualifier
      serial/imx: make imx_port.devdata member point to const data
      serial/mpc52xx_uart: add a const qualifier
      ARM: cache-l2x0: add a const qualifier
      misc/atmel_tc: make atmel_tc.tcb_config member point to const data
      gpio/gpio-omap.c: add a const qualifier
      gpio/mpc8xxx: add a const qualifier
      i2c/i2c-omap: add a const qualifier
      i2c/mpc: add a const qualifier
      mmc/omap_hsmmc: add a const qualifier
      macintosh/mediabay: add a const qualifier
      powerpc/83xx: add a const qualifier
      powerpc/fsl_msi: add a const qualifier
      powerpc/celleb_pci: add a const qualifier
      of: add const to struct *of_device_id.data
      gpio/gpio-omap: make platformdata used as *of_device_id.data const

 arch/arm/mm/cache-l2x0.c                 |    2 +-
 arch/powerpc/platforms/83xx/suspend.c    |    2 +-
 arch/powerpc/platforms/cell/celleb_pci.c |    2 +-
 arch/powerpc/sysdev/fsl_msi.c            |    8 ++++----
 drivers/gpio/gpio-mpc8xxx.c              |    2 +-
 drivers/gpio/gpio-omap.c                 |    8 ++++----
 drivers/i2c/busses/i2c-mpc.c             |   12 ++++++------
 drivers/i2c/busses/i2c-omap.c            |    3 ++-
 drivers/macintosh/mediabay.c             |    8 ++++----
 drivers/mfd/da9052-i2c.c                 |    4 ++--
 drivers/mmc/host/omap_hsmmc.c            |    2 +-
 drivers/net/can/mscan/mpc5xxx_can.c      |    4 ++--
 drivers/spi/spi-imx.c                    |    2 +-
 drivers/spi/spi-omap2-mcspi.c            |    2 +-
 drivers/tty/serial/imx.c                 |    2 +-
 drivers/tty/serial/mpc52xx_uart.c        |    2 +-
 drivers/watchdog/mpc8xxx_wdt.c           |    2 +-
 include/linux/atmel_tc.h                 |    2 +-
 include/linux/mod_devicetable.h          |    2 +-
 19 files changed, 36 insertions(+), 35 deletions(-)


-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From thomas.petazzoni at free-electrons.com  Sun Aug  5 05:34:21 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sun, 5 Aug 2012 11:34:21 +0200
Subject: [PATCH v2 0/5] Use more asm-generic headers
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <20120805113421.57401d21@skate>

Le Sat,  4 Aug 2012 20:23:55 -0500,
Rob Herring <robherring2 at gmail.com> a ?crit :

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Inspired by the AArgh64 claim that it should be separate from ARM and
> one reason was being able to use more asm-generic headers. Doing a
> diff of arch/arm/include/asm and include/asm-generic there are
> numerous asm headers which are functionally identical to their
> asm-generic counterparts and others which can use more of the generic
> versions.
> 
> V2 separates unaligned.h and termios.h changes to separate patches.
> Also, it adds a fix for build failures on non-gzip decompressor
> compile.
> 
> Rob
> 
> Rob Herring (5):
>   ARM: use generic version of identical asm headers
>   ARM: add strstr declaration for decompressors
>   ARM: use generic unaligned.h
>   ARM: use generic termios.h
>   ARM: convert asm/irqflags.h to use asm-generic/irqflags.h

Built and boot tested on Armada XP evaluation platform.

Tested-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linus.walleij at linaro.org  Sun Aug  5 05:37:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:37:35 +0200
Subject: [PATCH v3 4/9] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <CAN1soZzOTMChr7WQzguH_CPQ8s=tyrsjwmAYNSBAVeMtwRE2uA@mail.gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <1343470061-16879-5-git-send-email-zonque@gmail.com>
 <CACRpkdaJhzzckg12uZrgweoOgC44VNb=0AEdp96AV2O0UM+AnA@mail.gmail.com>
 <CAN1soZzOTMChr7WQzguH_CPQ8s=tyrsjwmAYNSBAVeMtwRE2uA@mail.gmail.com>
Message-ID: <CACRpkdYaL65VGFKD-3OM173jQV6zeAj3bCcpHneC2L0yK504rw@mail.gmail.com>

On Sun, Aug 5, 2012 at 4:56 AM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> On Sun, Aug 5, 2012 at 8:12 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
>> On Sat, Jul 28, 2012 at 12:07 PM, Daniel Mack <zonque at gmail.com> wrote:
>>
>>> Simplify the code in gpio-pxa.c and make them based on irq_base.
>>> When not probed from devicetree, initialize irq_base from
>>> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
>>> still works.
>>>
>>> +#ifdef CONFIG_ARCH_PXA
>>> +               if (gpio_is_pxa_type(gpio_type))
>>> +                       irq_base = PXA_GPIO_TO_IRQ(0);
>>> +#endif
>>> +#ifdef CONFIG_ARCH_MMP
>>> +               if (gpio_is_mmp_type(gpio_type))
>>> +                       irq_base = MMP_GPIO_TO_IRQ(0);
>>> +#endif
>>
>> Grrr. Can we think of a way to get rid of these #ifdef:s?
>>
>
> It's used for non-DT mode. This driver is used in both arch-pxa
> and arch-mmp. Since we use static irq allocation in non-DT mode,
> we have to use this kind of code to get irq_base.
>
> What Daniel did is only simplifying the code.

Yep I know, and the result is better than without the patch, so
I Acked it. But if I have my dreams come true we could do away
with this compile-time stuff as well...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:40:31 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:40:31 +0200
Subject: [PATCH 2/2] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <CAN1soZxzGeJWbG9g_j1L=gG42SE6LUt_W1vJwu61OSMHdcgAbQ@mail.gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <1343230539-7196-2-git-send-email-zonque@gmail.com>
 <CACRpkdY6zn+aigZituo37iq=Mttf9Bhn06nyH-A4zQ6mhsByow@mail.gmail.com>
 <CAN1soZxzGeJWbG9g_j1L=gG42SE6LUt_W1vJwu61OSMHdcgAbQ@mail.gmail.com>
Message-ID: <CACRpkdYGPgy8s505_rom2tnKdL8rVwrd3N=rbRUJnRYnDj726A@mail.gmail.com>

On Sun, Aug 5, 2012 at 5:52 AM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> On Sun, Aug 5, 2012 at 7:16 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
>> On Wed, Jul 25, 2012 at 5:35 PM, Daniel Mack <zonque at gmail.com> wrote:
>>
>>> Provide an of_xlate function for the PXA GPIO chips and make it work for
>>> devicetree environments.
>>>
>>> Successfully tested on a PXA3xx board.
>>>
>>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>>
>> Could the PXA maintainers pls have a look at this patch, if you're working
>> on DT support especially...
>>
>> BTW: I guess this is not a fix for issues in the current kernel HEAD?
>> Is it OK to have this for the next (v3.7) cycle?
>>
> It's a real fix. Since of_get_named_gpio_flags() needs to get flags of gpio.
> This function is widely used in mmc/usb/... drivers. So it requires
> vendor's gpio
> driver to support parse flags from DT script.

OK I take that as an ACK so I've put it on my fixes branch with
your Acked-by.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:45:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:45:56 +0200
Subject: [PATCH 1/4] gpio/mxc: remove redundant shadow variables
 initialization
In-Reply-To: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZhTFYLEmof9bRoYX0Erjpz+0k7y0wUhsmXtWroX=B3ug@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> With commit 3e11f7b (gpio/generic: initialize basic_mmio_gpio shadow
> variables properly) in place, the shadow variables initialization is
> being done in generic driver bgpio_init call.
>
> Remove the redundant shadow variables initialization from gpio-mxc
> driver.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:47:21 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:47:21 +0200
Subject: [PATCH 2/4] gpio/mxc: specify gpio base for device tree probe
In-Reply-To: <1344146488-9496-2-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZFmfb-Fg_K1UPyx5Qw1XkODNo4aiNiOkoSXyOYRGMZ7g@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Currently, unlike the non-DT probe where the gpio base is specified
> with pdev->id, the DT probe uses the base dynamically allocated by
> gpio core, which uses a completely different numbering scheme.  This
> causes two issues to user space applications which access sysfs entry
> /sys/class/gpio/gpioN.

Applied.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:48:24 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:48:24 +0200
Subject: [PATCH 3/4] gpio/mxs: specify gpio base for device tree probe
In-Reply-To: <1344146488-9496-3-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZz+F8gUGJG+d2mGrt8Rp0NzYypGdLEUbxmh=X1Q1cFhw@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Currently, unlike the non-DT probe where the gpio base is specified
> with pdev->id, the DT probe uses the base dynamically allocated by
> gpio core, which uses a completely different numbering scheme.  This
> causes two issues to user space applications which access sysfs entry
> /sys/class/gpio/gpioN.

Applied.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:49:40 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:49:40 +0200
Subject: [PATCH 4/4] ARM: dts: imx: add alias for gpio
In-Reply-To: <1344146488-9496-4-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdYVu2RyiOF7tr0jECeFpU1=mhRvQ5aMY-khuH_g2cDT8Q@mail.gmail.com>

On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Add alias for gpio nodes, so that gpio driver can identify the port
> number and then specify a sensible gpio base rather than using the
> one dynamically allocated by gpio core.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 05:53:46 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 11:53:46 +0200
Subject: [RFC PATCH] gpio: Add a generic GPIO handling driver
In-Reply-To: <1340961676-25432-1-git-send-email-LW@KARO-electronics.de>
References: <1340961676-25432-1-git-send-email-LW@KARO-electronics.de>
Message-ID: <CACRpkdbKxM5=2brx8S7WP6GQwGKuTSBcALOG-VTB_rgwnXNTUQ@mail.gmail.com>

On Fri, Jun 29, 2012 at 11:21 AM, Lothar Wa?mann <LW at karo-electronics.de> wrote:

> This driver provides an interface for device drivers that need to
> control some external hardware (e.g. reset or enable signals) for the
> devices they serve.

I sort of like the idea, but I want a solid use case, i.e. an indication
of platform using this, and patches in the works. So I want atleast
one more patch making real use of the mechanism, or we just
gain weight in the kernel for no use.

Also, the introduction message should be merged into
Documentation/gpio.txt so people can easily find it.

I'd ideally like Grant's feedback on this too, since it's a major thing.

Yours,
Linus Walleij


From u.kleine-koenig at pengutronix.de  Sun Aug  5 05:55:28 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sun, 5 Aug 2012 11:55:28 +0200
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120803114532.GB26925@mudshark.cambridge.arm.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
Message-ID: <20120805095528.GO2626@pengutronix.de>

On Fri, Aug 03, 2012 at 12:45:32PM +0100, Will Deacon wrote:
> On Fri, Aug 03, 2012 at 10:04:52AM +0100, Uwe Kleine-K?nig wrote:
> > Hello,
> 
> Hi Uwe,
> 
> > in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have
> > 
> > 	.arm
> >  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> >  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
> >  THUMB( .thumb                  )       @ switch to Thumb now.
> >  THUMB(1:                       )
> > 
> > as first instructions at the entry point. This is a problem for
> > thumb2-only cpus (e.g. Cortex-M3).
> 
> Yup, Documentation/arm/Booting mentions this too.
> 
> > Up to now I commented out the first three lines for the Cortex-M3 port.
> > What should we do about that. There are two possibilities I see:
> > 
> >  a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
> >     first three lines out if it is given.
> >  b) expect the bootloader to directly jump to the label 1.
> > 
> > The downside of a) is that a boot loader on a cpu that is capable to
> > execute the tradtional instructions would need to detect if the switch
> > to thumb is there or not and react accordingly. (In fact it needs to
> > distringuish three cases:
> > 
> >  - traditional kernel
> >  - thumb2 kernel with ARM entry
> >  - thumb2 kernel without ARM entry
> > 
> > .) So I think b) is the more sensible option in the long run.
> > 
> > What do you think?
> 
> How about something like:
> 
> 
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 835898e..9f07be2 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -86,6 +86,7 @@
>         __HEAD
>  ENTRY(stext)
>  
> + THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
>   THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
>   THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
>   THUMB(        .thumb                  )       @ switch to Thumb now.
Great idea, but it doesn't work as suggested. My compiler already barfs
on the .arm above:

	arch/arm/kernel/head-nommu.S:36: Error: selected processor does not support ARM opcodes
	arch/arm/kernel/head-nommu.S:42: Error: attempt to use an ARM instruction on a Thumb-only processor -- `adr r9,1f+1'
	arch/arm/kernel/head-nommu.S:43: Error: attempt to use an ARM instruction on a Thumb-only processor -- `bx r9'

but something like that should be doable.

Best regards
Uwe


-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From dirk.behme at gmail.com  Sun Aug  5 06:56:47 2012
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sun, 05 Aug 2012 12:56:47 +0200
Subject: [PATCH] mtd: mxc_nand: Fix compiler warnings
In-Reply-To: <20120805083926.GL2626@pengutronix.de>
References: <1343466310-14584-1-git-send-email-dirk.behme@gmail.com>
 <20120730073454.GI1528@pengutronix.de> <501D4405.6030900@googlemail.com>
 <20120805083926.GL2626@pengutronix.de>
Message-ID: <501E516F.2020507@gmail.com>

On 05.08.2012 10:39, Uwe Kleine-K?nig wrote:
> On Sat, Aug 04, 2012 at 05:47:17PM +0200, Dirk Behme wrote:
>> On 30.07.2012 09:34, Uwe Kleine-K?nig wrote:
>>> Hello,
>>>
>>> On Sat, Jul 28, 2012 at 11:05:10AM +0200, Dirk Behme wrote:
>>>> From: Dirk Behme<dirk.behme at googlemail.com>
>>>>
>>>> Fix the compiler warnings
>>>>
>>>> drivers/mtd/nand/mxc_nand.c:1267: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1270: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1273: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1276: warning: initialization discards qualifiers from pointer target type
>>> These should be gone in next already.
>>
>> Hmm, which next?
>>
>> I tried linux-next [1] from today (next-20120803, 55fa9961f) and still get
> next-20120725 contained 98d7bbb9929bcc14e11ac8a55245a4f2dc174e17, don't
> konw why it isn't included in the newer next snapshorts.

First, yes, it was part of next-20120725. Second, I can confirm that 
the patch [1] fixes the compiler warnings I reported above. So my 
patch is obsolete now.

And third, strange is the absence in next-20120803 and 3.6-rc1. Do we 
a chance to find out what's ongoing here? It would be a shame if your 
patch get lost.

Many thanks

Dirk


[1] https://patchwork.kernel.org/patch/1226851/



From will.deacon at arm.com  Sun Aug  5 07:42:00 2012
From: will.deacon at arm.com (Will Deacon)
Date: Sun, 5 Aug 2012 12:42:00 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120805095528.GO2626@pengutronix.de>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
Message-ID: <20120805114200.GC21771@mudshark.cambridge.arm.com>

On Sun, Aug 05, 2012 at 10:55:28AM +0100, Uwe Kleine-K?nig wrote:
> On Fri, Aug 03, 2012 at 12:45:32PM +0100, Will Deacon wrote:
> > How about something like:
> > 
> > 
> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > index 835898e..9f07be2 100644
> > --- a/arch/arm/kernel/head.S
> > +++ b/arch/arm/kernel/head.S
> > @@ -86,6 +86,7 @@
> >         __HEAD
> >  ENTRY(stext)
> >  
> > + THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
> >   THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> >   THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
> >   THUMB(        .thumb                  )       @ switch to Thumb now.
> Great idea, but it doesn't work as suggested. My compiler already barfs
> on the .arm above:
> 
> 	arch/arm/kernel/head-nommu.S:36: Error: selected processor does not support ARM opcodes
> 	arch/arm/kernel/head-nommu.S:42: Error: attempt to use an ARM instruction on a Thumb-only processor -- `adr r9,1f+1'
> 	arch/arm/kernel/head-nommu.S:43: Error: attempt to use an ARM instruction on a Thumb-only processor -- `bx r9'

Aaand our good friend gas bites us again. Out of interest, what happens 
if you pass -march=all instead of whatever you currently pass (armv7m or
something I guess?). We hit a bug the other day assembling the decompressor
and I'd be interested to know what the tools do with your code.

> but something like that should be doable.

Maybe we should just .inst the two arm instructions as well and lose the
.arm directive. Given that the size of those instructions is now encoded
in the first instruction (for the Thumb-2 branch), it would also make it
clear that you can't just add extra arm instructions there without
changing the branch.

Will


From zonque at gmail.com  Sun Aug  5 07:56:13 2012
From: zonque at gmail.com (Daniel Mack)
Date: Sun, 05 Aug 2012 13:56:13 +0200
Subject: [PATCH 1/2] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <501E2F6C.4050507@compulab.co.il>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <501E2F6C.4050507@compulab.co.il>
Message-ID: <501E5F5D.5070901@gmail.com>

On 05.08.2012 10:31, Igor Grinberg wrote:
> Hi Daniel,
> 
> On 07/25/12 18:35, Daniel Mack wrote:
>> Simplify the code in gpio-pxa.c and make them based on irq_base.
>> When not probed from devicetree, initialize irq_base from
>> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
>> still works.
>>
>> Only tested on PXA3xx.
>>
>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>> ---
>>  drivers/gpio/gpio-pxa.c |   70 +++++++++++------------------------------------
>>  1 file changed, 16 insertions(+), 54 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
>> index 58a6a63..6d0cb9d 100644
>> --- a/drivers/gpio/gpio-pxa.c
>> +++ b/drivers/gpio/gpio-pxa.c
> 
> [...]
> 
>> @@ -564,10 +516,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
>>  	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
>>  
>>  	ret = pxa_gpio_probe_dt(pdev);
>> -	if (ret < 0)
>> +	if (ret < 0) {
>>  		pxa_last_gpio = pxa_gpio_nums();
>> -	else
>> +#ifdef CONFIG_ARCH_PXA
>> +		if (gpio_is_pxa_type(gpio_type))
>> +			irq_base = PXA_GPIO_TO_IRQ(0);
>> +#endif
>> +#ifdef CONFIG_ARCH_MMP
>> +		if (gpio_is_mmp_type(gpio_type))
>> +			irq_base = MMP_GPIO_TO_IRQ(0);
>> +#endif
> 
> The ifdes above do not look essential.

But they are. In case of !CONFIG_ARCH_MMP, MMP_GPIO_TO_IRQ is undefined.
Same problem for !CONFIG_ARC_PXA.

> Can't we drop them and just have else if ... else if?

We can't do that either, as we might have a hybrid kernel that works on
both PXA and MMP platforms, and then the condition is a runtime thing.


Daniel



From aaro.koskinen at iki.fi  Sun Aug  5 08:50:29 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Sun,  5 Aug 2012 15:50:29 +0300
Subject: [PATCH] ARM: dma-mapping: fix incorrect freeing of atomic allocations
Message-ID: <1344171029-24804-1-git-send-email-aaro.koskinen@iki.fi>

Commit e9da6e9905e639b0f842a244bc770b48ad0523e9 (ARM: dma-mapping:
remove custom consistent dma region) changed the way atomic allocations
are handled. However, arm_dma_free() was not modified accordingly, and
as a result freeing of atomic allocations does not work correctly when
CMA is disabled. Memory is leaked and following WARNINGs are seen:

[   57.698911] ------------[ cut here ]------------
[   57.753518] WARNING: at arch/arm/mm/dma-mapping.c:263 arm_dma_free+0x88/0xe4()
[   57.811473] trying to free invalid coherent area: e0848000
[   57.867398] Modules linked in: sata_mv(-)
[   57.921373] [<c000d270>] (unwind_backtrace+0x0/0xf0) from [<c0015430>] (warn_slowpath_common+0x50/0x68)
[   58.033924] [<c0015430>] (warn_slowpath_common+0x50/0x68) from [<c00154dc>] (warn_slowpath_fmt+0x30/0x40)
[   58.152024] [<c00154dc>] (warn_slowpath_fmt+0x30/0x40) from [<c000dc18>] (arm_dma_free+0x88/0xe4)
[   58.219592] [<c000dc18>] (arm_dma_free+0x88/0xe4) from [<c008fa30>] (dma_pool_destroy+0x100/0x148)
[   58.345526] [<c008fa30>] (dma_pool_destroy+0x100/0x148) from [<c019a64c>] (release_nodes+0x144/0x218)
[   58.475782] [<c019a64c>] (release_nodes+0x144/0x218) from [<c0197e10>] (__device_release_driver+0x60/0xb8)
[   58.614260] [<c0197e10>] (__device_release_driver+0x60/0xb8) from [<c0198608>] (driver_detach+0xd8/0xec)
[   58.756527] [<c0198608>] (driver_detach+0xd8/0xec) from [<c0197c54>] (bus_remove_driver+0x7c/0xc4)
[   58.901648] [<c0197c54>] (bus_remove_driver+0x7c/0xc4) from [<c004bfac>] (sys_delete_module+0x19c/0x220)
[   59.051447] [<c004bfac>] (sys_delete_module+0x19c/0x220) from [<c0009140>] (ret_fast_syscall+0x0/0x2c)
[   59.207996] ---[ end trace 0745420412c0325a ]---
[   59.287110] ------------[ cut here ]------------
[   59.366324] WARNING: at arch/arm/mm/dma-mapping.c:263 arm_dma_free+0x88/0xe4()
[   59.450511] trying to free invalid coherent area: e0847000
[   59.534357] Modules linked in: sata_mv(-)
[   59.616785] [<c000d270>] (unwind_backtrace+0x0/0xf0) from [<c0015430>] (warn_slowpath_common+0x50/0x68)
[   59.790030] [<c0015430>] (warn_slowpath_common+0x50/0x68) from [<c00154dc>] (warn_slowpath_fmt+0x30/0x40)
[   59.972322] [<c00154dc>] (warn_slowpath_fmt+0x30/0x40) from [<c000dc18>] (arm_dma_free+0x88/0xe4)
[   60.070701] [<c000dc18>] (arm_dma_free+0x88/0xe4) from [<c008fa30>] (dma_pool_destroy+0x100/0x148)
[   60.256817] [<c008fa30>] (dma_pool_destroy+0x100/0x148) from [<c019a64c>] (release_nodes+0x144/0x218)
[   60.445201] [<c019a64c>] (release_nodes+0x144/0x218) from [<c0197e10>] (__device_release_driver+0x60/0xb8)
[   60.634148] [<c0197e10>] (__device_release_driver+0x60/0xb8) from [<c0198608>] (driver_detach+0xd8/0xec)
[   60.823623] [<c0198608>] (driver_detach+0xd8/0xec) from [<c0197c54>] (bus_remove_driver+0x7c/0xc4)
[   61.013268] [<c0197c54>] (bus_remove_driver+0x7c/0xc4) from [<c004bfac>] (sys_delete_module+0x19c/0x220)
[   61.203472] [<c004bfac>] (sys_delete_module+0x19c/0x220) from [<c0009140>] (ret_fast_syscall+0x0/0x2c)
[   61.393390] ---[ end trace 0745420412c0325b ]---

The patch fixes this.

Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>
---
 arch/arm/mm/dma-mapping.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c2cdf65..2cc77b7 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -648,12 +648,12 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 
 	if (arch_is_coherent() || nommu()) {
 		__dma_free_buffer(page, size);
+	} else if (__free_from_pool(cpu_addr, size)) {
+		return;
 	} else if (!IS_ENABLED(CONFIG_CMA)) {
 		__dma_free_remap(cpu_addr, size);
 		__dma_free_buffer(page, size);
 	} else {
-		if (__free_from_pool(cpu_addr, size))
-			return;
 		/*
 		 * Non-atomic allocations cannot be freed with IRQs disabled
 		 */
-- 
1.7.2.5



From haojian.zhuang at gmail.com  Sun Aug  5 08:58:41 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 5 Aug 2012 20:58:41 +0800
Subject: [PATCH 2/2] GPIO: gpio-pxa: fix devicetree functions
In-Reply-To: <CACRpkdYGPgy8s505_rom2tnKdL8rVwrd3N=rbRUJnRYnDj726A@mail.gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <1343230539-7196-2-git-send-email-zonque@gmail.com>
 <CACRpkdY6zn+aigZituo37iq=Mttf9Bhn06nyH-A4zQ6mhsByow@mail.gmail.com>
 <CAN1soZxzGeJWbG9g_j1L=gG42SE6LUt_W1vJwu61OSMHdcgAbQ@mail.gmail.com>
 <CACRpkdYGPgy8s505_rom2tnKdL8rVwrd3N=rbRUJnRYnDj726A@mail.gmail.com>
Message-ID: <CAN1soZzh+79eczrSyjY9RO0Eec7KvDDJ-s9rckiBGw56b7R-3Q@mail.gmail.com>

On Sun, Aug 5, 2012 at 5:40 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sun, Aug 5, 2012 at 5:52 AM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
>> On Sun, Aug 5, 2012 at 7:16 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
>>> On Wed, Jul 25, 2012 at 5:35 PM, Daniel Mack <zonque at gmail.com> wrote:
>>>
>>>> Provide an of_xlate function for the PXA GPIO chips and make it work for
>>>> devicetree environments.
>>>>
>>>> Successfully tested on a PXA3xx board.
>>>>
>>>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>>>
>>> Could the PXA maintainers pls have a look at this patch, if you're working
>>> on DT support especially...
>>>
>>> BTW: I guess this is not a fix for issues in the current kernel HEAD?
>>> Is it OK to have this for the next (v3.7) cycle?
>>>
>> It's a real fix. Since of_get_named_gpio_flags() needs to get flags of gpio.
>> This function is widely used in mmc/usb/... drivers. So it requires
>> vendor's gpio
>> driver to support parse flags from DT script.
>
> OK I take that as an ACK so I've put it on my fixes branch with
> your Acked-by.
>
Thanks. Let me revert it from pxa git tree.

Regards
Haojian


From will.deacon at arm.com  Sun Aug  5 09:20:02 2012
From: will.deacon at arm.com (Will Deacon)
Date: Sun, 5 Aug 2012 14:20:02 +0100
Subject: [PATCH] ARM: Don't enable GENERIC_LOCKBREAK with ticket spinlocks
In-Reply-To: <1344033762-3296-1-git-send-email-sboyd@codeaurora.org>
References: <1344033762-3296-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <20120805132001.GA1591@mudshark.cambridge.arm.com>

On Fri, Aug 03, 2012 at 11:42:42PM +0100, Stephen Boyd wrote:
> Now that ARM has implemented its spinlocks with tickets we don't
> need to use the generic lockbreak algorithm. Remove the Kconfig
> from ARM so that we use the arch_spin_is_contended() definition
> from the asm header. This also saves a word in each lock because
> we don't need the break_lock member anymore.
> 
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---
> 
> It seems we define the arch_spin_is_contended() macro but we don't
> use it on SMP && PREEMPT kernels?

Thanks, I missed that.

Acked-by: Will Deacon <will.deacon at arm.com>

Will


From cyril at ti.com  Sun Aug  5 09:56:20 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 09:56:20 -0400
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208040045360.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home>
Message-ID: <501E7B84.1050201@ti.com>

Hi Nicolas,

On 8/4/2012 1:38 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> The original phys_to_virt/virt_to_phys patching implementation relied on early
>> patching prior to MMU initialization.  On PAE systems running out of >4G
>> address space, this would have entailed an additional round of patching after
>> switching over to the high address space.
>>
>> The approach implemented here conceptually extends the original PHYS_OFFSET
>> patching implementation with the introduction of "early" patch stubs.  Early
>> patch code is required to be functional out of the box, even before the patch
>> is applied.  This is implemented by inserting functional (but inefficient)
>> load code into the .patch.code init section.  Having functional code out of
>> the box then allows us to defer the init time patch application until later
>> in the init sequence.
>>
>> In addition to fitting better with our need for physical address-space
>> switch-over, this implementation should be somewhat more extensible by virtue
>> of its more readable (and hackable) C implementation.  This should prove
>> useful for other similar init time specialization needs, especially in light
>> of our multi-platform kernel initiative.
>>
>> This code has been boot tested in both ARM and Thumb-2 modes on an ARMv7
>> (Cortex-A8) device.
>>
>> Note: the obtuse use of stringified symbols in patch_stub() and
>> early_patch_stub() is intentional.  Theoretically this should have been
>> accomplished with formal operands passed into the asm block, but this requires
>> the use of the 'c' modifier for instantiating the long (e.g. .long %c0).
>> However, the 'c' modifier has been found to ICE certain versions of GCC, and
>> therefore we resort to stringified symbols here.
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> This looks very nice.  Comments below.
>
>> ---
>>   arch/arm/include/asm/patch.h  |  123 +++++++++++++++++++++++++++++
>
> Please find a better name for this file. "patch" is way too generic and
> commonly referring to something different. "runtime-patching" or similar
> would be more descriptive.
>

Sure.  Does init-patch sound about right?  We need to reflect the fact 
that this is intended for init-time patching only.

>>   arch/arm/kernel/module.c      |    4 +
>>   arch/arm/kernel/setup.c       |  175 +++++++++++++++++++++++++++++++++++++++++
>
> This is complex enough to waarrant aa separate source file.  Please move
> those additions out from setup.c.  Given a good name for the header file
> above, the c file could share the same name.
>

Sure.

>> new file mode 100644
>> index 0000000..a89749f
>> --- /dev/null
>> +++ b/arch/arm/include/asm/patch.h
>> @@ -0,0 +1,123 @@
>> +/*
>> + *  arch/arm/include/asm/patch.h
>> + *
>> + *  Copyright (C) 2012, Texas Instruments
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + *  Note: this file should not be included by non-asm/.h files
>> + */
>> +#ifndef __ASM_ARM_PATCH_H
>> +#define __ASM_ARM_PATCH_H
>> +
>> +#include <linux/stringify.h>
>> +
>> +#ifndef __ASSEMBLY__
>> +
>> extern unsigned __patch_table_begin, __patch_table_end;
>
> You could use "exttern void __patch_table_begin" so those symbols don't
> get any type that could be misused by mistake, while you still can take
> their addresses.
>

Sure.

>> +
>> +struct patch_info {
>> +	u32	 type;
>> +	u32	 size;
>
> Given the possibly large number of table entries, some effort at making
> those entries as compact as possible should be considered. For instance,
> the type and size fields could be u8's and insn_end pointer replaced
> with another size expressed as an u8.  By placing all the u8's together
> they would occupy a single word by themselves.  The assembly stub would
> only need a .align statement to reflect the c structure's padding.
>

Thanks, will try and pack this struct up.

> [...]
>
> Did you verify with some test program that your patching routines do
> produce the same opcodes as the assembled equivalent for all possible
> shift values?  Especially for Thumb2 code which isn't as trivial to get
> right as the ARM one.
>

Not quite all, but I'm sure I can conjure up an off-line test harness to 
do so.


Much appreciated feedback.  Thanks for taking a look.

-- 
Thanks
- Cyril


From cyril at ti.com  Sun Aug  5 10:03:45 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 10:03:45 -0400
Subject: [PATCH 02/22] ARM: use late patch framework for phys-virt patching
In-Reply-To: <alpine.LFD.2.02.1208040138560.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-3-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040138560.5231@xanadu.home>
Message-ID: <501E7D41.8070303@ti.com>

Hi Nicolas,

On 8/4/2012 2:15 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> This patch replaces the original physical offset patching implementation
>> with one that uses the newly added patching framework.  In the process, we now
>> unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
>> head.S code.
>
> Why unconditionally initializing those?  There is no reason for that.
>

We could keep this conditional on LPAE, but do you see any specific need 
for keeping it conditional?

>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> Comments below.
>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index 835898e..d165896 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
> [...]
>>   	.data
>>   	.globl	__pv_phys_offset
>>   	.type	__pv_phys_offset, %object
>>   __pv_phys_offset:
>>   	.long	0
>>   	.size	__pv_phys_offset, . - __pv_phys_offset
>> +
>> +	.globl	__pv_offset
>> +	.type	__pv_offset, %object
>>   __pv_offset:
>>   	.long	0
>> -#endif
>> +	.size	__pv_offset, . - __pv_offset
>
> Please move those to C code.  They aren't of much use in this file
> anymore.  This will allow you to use pphys_addr_t for them as well in
> your subsequent patch. And more importantly get rid of that ugly
> pv_offset_high that you introduced iin another patch.
>

Moving it to C-code caused problems because these get filled in prior to 
BSS being cleared.

We could potentially have this initialized in C with a mystery dummy 
value to prevent it from landing in BSS.  Would that be acceptable?

>> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
>> index df5e897..39f8fce 100644
>> --- a/arch/arm/kernel/module.c
>> +++ b/arch/arm/kernel/module.c
>> @@ -317,11 +317,6 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
>>   					         maps[i].txt_sec->sh_addr,
>>   					         maps[i].txt_sec->sh_size);
>>   #endif
>> -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>> -	s = find_mod_section(hdr, sechdrs, ".pv_table");
>> -	if (s)
>> -		fixup_pv_table((void *)s->sh_addr, s->sh_size);
>> -#endif
>>   	s = find_mod_section(hdr, sechdrs, ".patch.table");
>>   	if (s)
>>   		patch_kernel((void *)s->sh_addr, s->sh_size);
>
> The patch_kernel code and its invokation should still be conditional on
> CONFIG_ARM_PATCH_PHYS_VIRT.  This ability may still be configured out
> irrespective of the implementation used.
>

Maybe CONFIG_ARM_PATCH_PHYS_VIRT is not quite appropriate if this is 
used to patch up other things in addition to phys-virt stuff?

I could have this dependent on CONFIG_ARM_INIT_PATCH (or whatever 
nomenclature we chose for this) and have CONFIG_ARM_PATCH_PHYS_VIRT 
depend on it.

>> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
>> index bacb275..13731e3 100644
>> --- a/arch/arm/kernel/vmlinux.lds.S
>> +++ b/arch/arm/kernel/vmlinux.lds.S
>> @@ -162,11 +162,6 @@ SECTIONS
>>   		__smpalt_end = .;
>>   	}
>>   #endif
>> -	.init.pv_table : {
>> -		__pv_table_begin = .;
>> -		*(.pv_table)
>> -		__pv_table_end = .;
>> -	}
>>   	.init.patch_table : {
>>   		__patch_table_begin = .;
>>   		*(.patch.table)
>
> Since you're changing the module ABI,it is important to also modify the
> module vermagic string in asm/module.h to prevent the loading of
> incompatible kernel modules.
>

Absolutely.  Thanks.

>
> Nicolas
>

-- 
Thanks
- Cyril


From cyril at ti.com  Sun Aug  5 10:05:11 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 10:05:11 -0400
Subject: [PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <alpine.LFD.2.02.1208040222110.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-4-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040222110.5231@xanadu.home>
Message-ID: <501E7D97.7070007@ti.com>

On 8/4/2012 2:24 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> This patch fixes up the types used when converting back and forth between
>> physical and virtual addresses.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> Did you verify that this didn't introduce any compilation warning when
> compiling for non LPAE?  If so and there were no warnings then...
>

Yes.  This series has been tested on vanilla ARMv7 Cortex-A8 non-LPAE 
hardware as well.

> Acked-by: Nicolas Pitre <nico at linaro.org>
>
>
>> ---
>>   arch/arm/include/asm/memory.h |   17 +++++++++++------
>>   1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
>> index 01c710d..4a0108f 100644
>> --- a/arch/arm/include/asm/memory.h
>> +++ b/arch/arm/include/asm/memory.h
>> @@ -157,22 +157,27 @@ extern unsigned long __pv_phys_offset;
>>
>>   extern unsigned long __pv_offset;
>>
>> -static inline unsigned long __virt_to_phys(unsigned long x)
>> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "add", __pv_offset);
>>   	return t;
>>   }
>>
>> -static inline unsigned long __phys_to_virt(unsigned long x)
>> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "sub", __pv_offset);
>>   	return t;
>>   }
>>   #else
>> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
>> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
>> +
>> +#define __virt_to_phys(x)		\
>> +	((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)
>> +
>> +#define __phys_to_virt(x)		\
>> +	((unsigned long)((phys_addr_t)(x) - PHYS_OFFSET + PAGE_OFFSET))
>> +
>>   #endif
>>   #endif
>>
>> @@ -207,14 +212,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>>
>>   static inline void *phys_to_virt(phys_addr_t x)
>>   {
>> -	return (void *)(__phys_to_virt((unsigned long)(x)));
>> +	return (void *)__phys_to_virt(x);
>>   }
>>
>>   /*
>>    * Drivers should NOT use these either.
>>    */
>>   #define __pa(x)			__virt_to_phys((unsigned long)(x))
>> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
>> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>>   #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
>>
>>   /*
>> --
>> 1.7.9.5
>>

-- 
Thanks
- Cyril


From cyril at ti.com  Sun Aug  5 10:21:17 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 10:21:17 -0400
Subject: [PATCH 04/22] ARM: LPAE: support 64-bit virt/phys patching
In-Reply-To: <alpine.LFD.2.02.1208040226060.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-5-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040226060.5231@xanadu.home>
Message-ID: <501E815D.1050707@ti.com>

Hi Nicolas,

On 8/4/2012 2:49 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> This patch adds support for 64-bit physical addresses in virt_to_phys
>> patching.  This does not do real 64-bit add/sub, but instead patches in the
>> upper 32-bits of the phys_offset directly into the output of virt_to_phys.
>
> You should explain _why_ you do not a real aadd/sub.  I did deduce it
> but that might not be obvious to everyone.  Also this subtlety should be
> commented in the code as well.
>

We could not do an ADDS + ADC here because the carry is not guaranteed 
to be retained and passed into the ADC.  This is because the compiler is 
free to insert all kinds of stuff between the two non-volatile asm blocks.

Is there another subtlety here that I have missed out on entirely?

>> In addition to adding 64-bit support, this patch also adds a set_phys_offset()
>> helper that is needed on architectures that need to modify PHYS_OFFSET during
>> initialization.
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
>>   arch/arm/include/asm/memory.h |   22 +++++++++++++++-------
>>   arch/arm/kernel/head.S        |    6 ++++++
>>   arch/arm/kernel/setup.c       |   14 ++++++++++++++
>>   3 files changed, 35 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
>> index 4a0108f..110495c 100644
>> --- a/arch/arm/include/asm/memory.h
>> +++ b/arch/arm/include/asm/memory.h
>> @@ -153,23 +153,31 @@
>>   #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>>
>>   extern unsigned long __pv_phys_offset;
>> -#define PHYS_OFFSET __pv_phys_offset
>> -
>> +extern unsigned long __pv_phys_offset_high;
>
> As mentioned previously, this is just too ugly.  Please make
> __pv_phys_offset into a phys_addr_t instead and mask the low/high parts
> as needed in __virt_to_phys().
>

Maybe u64 instead of phys_addr_t to keep the sizing non-variable?

>>   extern unsigned long __pv_offset;
>>
>> +extern void set_phys_offset(phys_addr_t po);
>> +
>> +#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
>> +
>>   static inline phys_addr_t __virt_to_phys(unsigned long x)
>>   {
>> -	unsigned long t;
>> -	early_patch_imm8(x, t, "add", __pv_offset);
>> -	return t;
>> +	unsigned long tlo, thi = 0;
>> +
>> +	early_patch_imm8(x, tlo, "add", __pv_offset);
>> +	if (sizeof(phys_addr_t) > 4)
>> +		early_patch_imm8(0, thi, "add", __pv_phys_offset_high);
>
> Given the high part is always the same, isn't there a better way than an
> add with 0 that could be done here?  The add will force a load of 0 in a
> register needlessly just to add a constant value to it.  Your new
> patching framework ought to be able to patch a mov (or a mvn)
> instruction directly.
>

True.  I'll try and figure out a better way of doing this.

>
> Nicolas
>

Once again, thanks for the excellent feedback.

-- 
Thanks
- Cyril


From cyril at ti.com  Sun Aug  5 10:23:20 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 10:23:20 -0400
Subject: [PATCH 08/22] ARM: LPAE: use phys_addr_t for initrd location
 and size
In-Reply-To: <alpine.LFD.2.02.1208040255100.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-9-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040255100.5231@xanadu.home>
Message-ID: <501E81D8.1010600@ti.com>

On 8/4/2012 2:57 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> From: Vitaly Andrianov <vitalya at ti.com>
>>
>> This patch fixes the initrd setup code to use phys_addr_t instead of assuming
>> 32-bit addressing.  Without this we cannot boot on systems where initrd is
>> located above the 4G physical address limit.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
>>   arch/arm/mm/init.c |   14 +++++++-------
>>   1 file changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
>> index 8252c31..51f3e92 100644
>> --- a/arch/arm/mm/init.c
>> +++ b/arch/arm/mm/init.c
>> @@ -36,12 +36,12 @@
>>
>>   #include "mm.h"
>>
>> -static unsigned long phys_initrd_start __initdata = 0;
>> -static unsigned long phys_initrd_size __initdata = 0;
>> +static phys_addr_t phys_initrd_start __initdata = 0;
>> +static phys_addr_t phys_initrd_size __initdata = 0;
>
> phys_addr_t for the initrd size is rather overkill, isn't it?
>

Fair enough. :-)

>
> Nicolas
>

-- 
Thanks
- Cyril


From cyril at ti.com  Sun Aug  5 10:29:59 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 10:29:59 -0400
Subject: [PATCH 09/22] ARM: LPAE: use 64-bit pgd physical address in
 switch_mm()
In-Reply-To: <alpine.LFD.2.02.1208040259200.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-10-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040259200.5231@xanadu.home>
Message-ID: <501E8367.8070907@ti.com>

On 8/4/2012 3:04 AM, Nicolas Pitre wrote:
> On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
>
>> This patch modifies the switch_mm() processor functions to use 64-bit
>> addresses.  We use u64 instead of phys_addr_t, in order to avoid having config
>> dependent register usage when calling into switch_mm assembly code.
>>
>> The changes in this patch are primarily adjustments for registers used for
>> arguments to switch_mm.  The few processor definitions that did use the second
>> argument have been modified accordingly.
>>
>> Arguments and calling conventions aside, this patch should be a no-op on v6
>> and non-LPAE v7 processors.
>
> NAK.
>
> You just broke all big endian targets, LPAE or not.
>

Indeed.  Thanks.

Would C-land word swappery on BE do?  Any other ideas on the best 
approach to this?

>
> Nicolas
>

-- 
Thanks
- Cyril


From sebastian.hesselbarth at gmail.com  Sun Aug  5 10:45:32 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sun,  5 Aug 2012 16:45:32 +0200
Subject: [PATCH 1/1] ARM: kirkwood: fix typo in Makefile.boot
Message-ID: <1344177932-6466-1-git-send-email-sebastian.hesselbarth@googlemail.com>

Just a small typo fix to make lsxl dtbs compile

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at googlemail.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/Makefile.boot |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 2a576ab..a571755 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -9,5 +9,5 @@ dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
 dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
 dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
-dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
-dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
+dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sun Aug  5 10:46:12 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sun,  5 Aug 2012 16:46:12 +0200
Subject: [PATCH 1/2] ARM: kirkwood: DT board setup for Seagate FreeAgent
 Dockstar
Message-ID: <1344177973-6505-1-git-send-email-sebastian.hesselbarth@googlemail.com>

This add a DT compatible board specific setup for the Seagate
FreeAgent Dockstar.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at googlemail.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/mach-kirkwood/Kconfig          |    7 ++++
 arch/arm/mach-kirkwood/Makefile         |    1 +
 arch/arm/mach-kirkwood/board-dockstar.c |   61 +++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c       |    4 ++
 arch/arm/mach-kirkwood/common.h         |    6 +++
 5 files changed, 79 insertions(+)
 create mode 100644 arch/arm/mach-kirkwood/board-dockstar.c

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..4eaeb93 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
 	  or MV6282. If you have the wrong one, the buttons will not
 	  work.
 
+config MACH_DOCKSTAR_DT
+	bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Seagate FreeAgent Dockstar (Flattened Device Tree).
+
 config MACH_GOFLEXNET_DT
 	bool "Seagate GoFlex Net (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..42e48cf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)		+= board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 0000000..6b9560b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+	MPP29_GPIO,	/* USB Power Enable */
+	MPP46_GPIO,	/* LED green */
+	MPP47_GPIO,	/* LED orange */
+	0
+};
+
+void __init dockstar_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(dockstar_mpp_config);
+
+	if (gpio_request(29, "USB Power Enable") != 0 ||
+	    gpio_direction_output(29, 1) != 0)
+		pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+	kirkwood_ehci_init();
+
+	kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..4693fad 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -81,6 +81,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("qnap,ts219"))
 		qnap_dt_ts219_init();
 
+	if (of_machine_is_compatible("seagate,dockstar"))
+		dockstar_init();
+
 	if (of_machine_is_compatible("seagate,goflexnet"))
 		goflexnet_init();
 
@@ -98,6 +101,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"iom,iconnect",
 	"raidsonic,ib-nas62x0",
 	"qnap,ts219",
+	"seagate,dockstar",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
 	NULL
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..dc73ff3 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_init(void);
+#else
+static inline void dockstar_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sun Aug  5 10:46:13 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sun,  5 Aug 2012 16:46:13 +0200
Subject: [PATCH 2/2] ARM: kirkwood: DT descriptor for Seagate FreeAgent
 Dockstar
In-Reply-To: <1344177973-6505-1-git-send-email-sebastian.hesselbarth@googlemail.com>
References: <1344177973-6505-1-git-send-email-sebastian.hesselbarth@googlemail.com>
Message-ID: <1344177973-6505-2-git-send-email-sebastian.hesselbarth@googlemail.com>

This adds the corresponding device tree descriptor for the
Seagate FreeAgent Dockstar based on Kirkwood DT.

Please note that this patch requires the mach-kirkwood Makefile.boot typo
fix to fully apply.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at googlemail.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 arch/arm/boot/dts/kirkwood-dockstar.dts |   57 +++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Makefile.boot    |    1 +
 2 files changed, 58 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-dockstar.dts

diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 0000000..08a5824
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Seagate FreeAgent Dockstar";
+	compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x400000>;
+			};
+
+			partition at 500000 {
+				label = "data";
+				reg = <0x0500000 0xfb00000>;
+			};
+		};
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		health {
+			label = "status:green:health";
+			gpios = <&gpio1 14 1>;
+			linux,default-trigger = "default-on";
+		};
+		fault {
+			label = "status:orange:fault";
+			gpios = <&gpio1 15 1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a571755..2c2edfb 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_DOCKSTAR_DT) += kirkwood-dockstar.dtb
-- 
1.7.10.4



From shawn.guo at linaro.org  Sun Aug  5 11:05:17 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 23:05:17 +0800
Subject: [PATCH v2 0/4] Add a generic cpufreq-cpu0 driver
Message-ID: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>

Changes since v1:
* Rebase on v3.6-rc1
* Add a patch introducing regulator_set_voltage_tol()
* Address review comments on v1

Richard Zhao (1):
  ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp

Shawn Guo (3):
  PM / OPP: Initialize OPP table from device tree
  regulator: add a new API regulator_set_voltage_tol()
  cpufreq: Add a generic cpufreq-cpu0 driver

 .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |   55 ++++
 Documentation/devicetree/bindings/power/opp.txt    |   25 ++
 arch/arm/kernel/smp.c                              |   54 ++++
 drivers/base/power/opp.c                           |   65 +++++
 drivers/cpufreq/Kconfig                            |   11 +
 drivers/cpufreq/Makefile                           |    2 +
 drivers/cpufreq/cpufreq-cpu0.c                     |  271 ++++++++++++++++++++
 include/linux/opp.h                                |    8 +
 include/linux/regulator/consumer.h                 |    7 +
 9 files changed, 498 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 create mode 100644 Documentation/devicetree/bindings/power/opp.txt
 create mode 100644 drivers/cpufreq/cpufreq-cpu0.c

-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 11:05:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 23:05:20 +0800
Subject: [PATCH v2 3/4] regulator: add a new API regulator_set_voltage_tol()
In-Reply-To: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344179121-17738-4-git-send-email-shawn.guo@linaro.org>

There are some use cases where a voltage range could be reasonably
specified by a target voltage and tolerance.  Add a new API
regulator_set_voltage_tol() wrapping regulator_set_voltage() call
to ease the users.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 include/linux/regulator/consumer.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/linux/regulator/consumer.h b/include/linux/regulator/consumer.h
index da339fd..2160352 100644
--- a/include/linux/regulator/consumer.h
+++ b/include/linux/regulator/consumer.h
@@ -352,4 +352,11 @@ static inline void regulator_set_drvdata(struct regulator *regulator,
 
 #endif
 
+static inline int regulator_set_voltage_tol(struct regulator *regulator,
+					    int new_uV, int tol_uV)
+{
+	return regulator_set_voltage(regulator,
+				     new_uV - tol_uV, new_uV + tol_uV);
+}
+
 #endif
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 11:05:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 23:05:18 +0800
Subject: [PATCH v2 1/4] ARM: add cpufreq transiton notifier to adjust
 loops_per_jiffy for smp
In-Reply-To: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344179121-17738-2-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

If CONFIG_SMP, cpufreq skips loops_per_jiffy update, because different
arch has different per-cpu loops_per_jiffy definition.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/kernel/smp.c |   54 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..8e03567 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -25,6 +25,7 @@
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/completion.h>
+#include <linux/cpufreq.h>
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
@@ -584,3 +585,56 @@ int setup_profiling_timer(unsigned int multiplier)
 {
 	return -EINVAL;
 }
+
+#ifdef CONFIG_CPU_FREQ
+
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
+static unsigned long global_l_p_j_ref;
+static unsigned long global_l_p_j_ref_freq;
+
+static int cpufreq_callback(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freq = data;
+	int cpu = freq->cpu;
+
+	if (freq->flags & CPUFREQ_CONST_LOOPS)
+		return NOTIFY_OK;
+
+	if (!per_cpu(l_p_j_ref, cpu)) {
+		per_cpu(l_p_j_ref, cpu) =
+			per_cpu(cpu_data, cpu).loops_per_jiffy;
+		per_cpu(l_p_j_ref_freq, cpu) = freq->old;
+		if (!global_l_p_j_ref) {
+			global_l_p_j_ref = loops_per_jiffy;
+			global_l_p_j_ref_freq = freq->old;
+		}
+	}
+
+	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
+	    (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+		loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
+						global_l_p_j_ref_freq,
+						freq->new);
+		per_cpu(cpu_data, cpu).loops_per_jiffy =
+			cpufreq_scale(per_cpu(l_p_j_ref, cpu),
+					per_cpu(l_p_j_ref_freq, cpu),
+					freq->new);
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block cpufreq_notifier = {
+	.notifier_call  = cpufreq_callback,
+};
+
+static int __init register_cpufreq_notifier(void)
+{
+	return cpufreq_register_notifier(&cpufreq_notifier,
+						CPUFREQ_TRANSITION_NOTIFIER);
+}
+core_initcall(register_cpufreq_notifier);
+
+#endif
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 11:05:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 23:05:19 +0800
Subject: [PATCH v2 2/4] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>

With a lot of devices booting from device tree nowadays, it requires
that OPP table can be initialized from device tree.  The patch adds
a helper function of_init_opp_table together with a binding doc for
that purpose.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 Documentation/devicetree/bindings/power/opp.txt |   25 +++++++++
 drivers/base/power/opp.c                        |   65 +++++++++++++++++++++++
 include/linux/opp.h                             |    8 +++
 3 files changed, 98 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/power/opp.txt

diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt
new file mode 100644
index 0000000..2238520
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/opp.txt
@@ -0,0 +1,25 @@
+* Generic OPP Interface
+
+SoCs have a standard set of tuples consisting of frequency and
+voltage pairs that the device will support per voltage domain. These
+are called Operating Performance Points or OPPs.
+
+Properties:
+- operating-points: An array of 3-tuples items, and each item consists
+  of frequency and voltage like <freq-kHz vol-uV>.
+	freq: clock frequency in kHz
+	vol: voltage in microvolt
+
+Examples:
+
+cpu at 0 {
+	compatible = "arm,cortex-a9";
+	reg = <0>;
+	next-level-cache = <&L2>;
+	operating-points = <
+		/* kHz    uV */
+		792000  1100000
+		396000  950000
+		198000  850000
+	>;
+};
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ac993ea..1bf1be8 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -22,6 +22,7 @@
 #include <linux/rculist.h>
 #include <linux/rcupdate.h>
 #include <linux/opp.h>
+#include <linux/of.h>
 
 /*
  * Internal data structure organization with the OPP layer library is as
@@ -674,3 +675,67 @@ struct srcu_notifier_head *opp_get_notifier(struct device *dev)
 
 	return &dev_opp->head;
 }
+
+#ifdef CONFIG_OF
+/**
+ * of_init_opp_table() - Initialize opp table from device tree
+ * @dev:	device pointer used to lookup device OPPs.
+ *
+ * Register the initial OPP table with the OPP library for given device.
+ */
+int of_init_opp_table(struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	const char *propname = "operating-points";
+	const struct property *pp;
+	u32 *opp;
+	int ret, i, nr;
+
+	pp = of_find_property(np, propname, NULL);
+	if (!pp) {
+		dev_err(dev, "%s: Unable to find property", __func__);
+		return -ENODEV;
+	}
+
+	opp = kzalloc(pp->length, GFP_KERNEL);
+	if (!opp) {
+		dev_err(dev, "%s: Unable to allocate array\n", __func__);
+		return -ENOMEM;
+	}
+
+	nr = pp->length / sizeof(u32);
+	ret = of_property_read_u32_array(np, propname, opp, nr);
+	if (ret) {
+		dev_err(dev, "%s: Unable to read OPPs\n", __func__);
+		goto out;
+	}
+
+	if (nr % 2) {
+		dev_err(dev, "%s: Invalid OPP list\n", __func__);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	nr /= 2;
+	for (i = 0; i < nr; i++) {
+		/*
+		 * Each OPP is a set of tuples consisting of frequency and
+		 * voltage like <freq-kHz vol-uV>.
+		 */
+		u32 *val = opp + i * 2;
+
+		val[0] *= 1000;
+		ret = opp_add(dev, val[0], val[1]);
+		if (ret) {
+			dev_warn(dev, "%s: Failed to add OPP %d: %d\n",
+				 __func__, val[0], ret);
+			continue;
+		}
+	}
+
+	ret = 0;
+out:
+	kfree(opp);
+	return ret;
+}
+#endif
diff --git a/include/linux/opp.h b/include/linux/opp.h
index 2a4e5fa..214e0eb 100644
--- a/include/linux/opp.h
+++ b/include/linux/opp.h
@@ -48,6 +48,14 @@ int opp_disable(struct device *dev, unsigned long freq);
 
 struct srcu_notifier_head *opp_get_notifier(struct device *dev);
 
+#ifdef CONFIG_OF
+int of_init_opp_table(struct device *dev);
+#else
+static inline int of_init_opp_table(struct device *dev)
+{
+	return -EINVAL;
+}
+#endif /* CONFIG_OF */
 #else
 static inline unsigned long opp_get_voltage(struct opp *opp)
 {
-- 
1.7.5.4




From shawn.guo at linaro.org  Sun Aug  5 11:05:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 5 Aug 2012 23:05:21 +0800
Subject: [PATCH v2 4/4] cpufreq: Add a generic cpufreq-cpu0 driver
In-Reply-To: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344179121-17738-5-git-send-email-shawn.guo@linaro.org>

It adds a generic cpufreq driver for CPU0 frequency management based on
clk, regulator, OPP and device tree support.  It can support both
uniprocessor (UP) and those symmetric multiprocessor (SMP) systems which
share clock and voltage across all CPUs.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |   55 ++++
 drivers/cpufreq/Kconfig                            |   11 +
 drivers/cpufreq/Makefile                           |    2 +
 drivers/cpufreq/cpufreq-cpu0.c                     |  271 ++++++++++++++++++++
 4 files changed, 339 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 create mode 100644 drivers/cpufreq/cpufreq-cpu0.c

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
new file mode 100644
index 0000000..4416ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
@@ -0,0 +1,55 @@
+Generic CPU0 cpufreq driver
+
+It is a generic cpufreq driver for CPU0 frequency management.  It
+supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+systems which share clock and voltage across all CPUs.
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu at 0.
+
+Required properties:
+- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
+  for details
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+  in unit of nanoseconds.
+- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
+
+Examples:
+
+cpus {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpu at 0 {
+		compatible = "arm,cortex-a9";
+		reg = <0>;
+		next-level-cache = <&L2>;
+		operating-points = <
+			/* kHz    uV */
+			792000  1100000
+			396000  950000
+			198000  850000
+		>;
+		transition-latency = <61036>; /* two CLK32 periods */
+	};
+
+	cpu at 1 {
+		compatible = "arm,cortex-a9";
+		reg = <1>;
+		next-level-cache = <&L2>;
+	};
+
+	cpu at 2 {
+		compatible = "arm,cortex-a9";
+		reg = <2>;
+		next-level-cache = <&L2>;
+	};
+
+	cpu at 3 {
+		compatible = "arm,cortex-a9";
+		reg = <3>;
+		next-level-cache = <&L2>;
+	};
+};
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index e24a2a1..ea512f4 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -179,6 +179,17 @@ config CPU_FREQ_GOV_CONSERVATIVE
 
 	  If in doubt, say N.
 
+config GENERIC_CPUFREQ_CPU0
+	bool "Generic CPU0 cpufreq driver"
+	depends on HAVE_CLK && REGULATOR && PM_OPP && OF
+	select CPU_FREQ_TABLE
+	help
+	  This adds a generic cpufreq driver for CPU0 frequency management.
+	  It supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+	  systems which share clock and voltage across all CPUs.
+
+	  If in doubt, say N.
+
 menu "x86 CPU frequency scaling drivers"
 depends on X86
 source "drivers/cpufreq/Kconfig.x86"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 9531fc2..a378ed2 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE)	+= cpufreq_conservative.o
 # CPUfreq cross-arch helpers
 obj-$(CONFIG_CPU_FREQ_TABLE)		+= freq_table.o
 
+obj-$(CONFIG_GENERIC_CPUFREQ_CPU0)	+= cpufreq-cpu0.o
+
 ##################################################################################
 # x86 drivers.
 # Link order matters. K8 is preferred to ACPI because of firmware bugs in early
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
new file mode 100644
index 0000000..fd3bac6
--- /dev/null
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Reuse some codes from drivers/cpufreq/omap-cpufreq.c
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+static unsigned int transition_latency;
+static unsigned int voltage_tolerance; /* in percentage */
+
+static struct device *cpu_dev;
+static struct clk *cpu_clk;
+static struct regulator *cpu_reg;
+static struct cpufreq_frequency_table *freq_table;
+
+static int cpu0_verify_speed(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static unsigned int cpu0_get_speed(unsigned int cpu)
+{
+	return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int cpu0_set_target(struct cpufreq_policy *policy,
+			   unsigned int target_freq, unsigned int relation)
+{
+	struct cpufreq_freqs freqs;
+	struct opp *opp;
+	unsigned long freq_Hz, volt = 0, volt_old = 0, tol = 0;
+	unsigned int index, cpu;
+	int ret;
+
+	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+					     relation, &index);
+	if (ret) {
+		pr_err("failed to match target freqency %d: %d\n",
+		       target_freq, ret);
+		return ret;
+	}
+
+	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
+	if (freq_Hz < 0)
+		freq_Hz = freq_table[index].frequency * 1000;
+	freqs.new = freq_Hz / 1000;
+	freqs.old = clk_get_rate(cpu_clk) / 1000;
+
+	if (freqs.old == freqs.new)
+		return 0;
+
+	for_each_online_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+	}
+
+	if (cpu_reg) {
+		opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
+		if (IS_ERR(opp)) {
+			pr_err("failed to find OPP for %ld\n", freq_Hz);
+			return PTR_ERR(opp);
+		}
+		volt = opp_get_voltage(opp);
+		tol = volt * voltage_tolerance / 100;
+		volt_old = regulator_get_voltage(cpu_reg);
+	}
+
+	pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
+		 freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
+		 freqs.new / 1000, volt ? volt / 1000 : -1);
+
+	/* scaling up?  scale voltage before frequency */
+	if (cpu_reg && freqs.new > freqs.old) {
+		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
+		if (ret) {
+			pr_err("failed to scale voltage up: %d\n", ret);
+			freqs.new = freqs.old;
+			return ret;
+		}
+	}
+
+	ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+	if (ret) {
+		pr_err("failed to set clock rate: %d\n", ret);
+		if (cpu_reg)
+			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
+		return ret;
+	}
+
+	/* scaling down?  scale voltage after frequency */
+	if (cpu_reg && freqs.new < freqs.old) {
+		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
+		if (ret) {
+			pr_err("failed to scale voltage down: %d\n", ret);
+			clk_set_rate(cpu_clk, freqs.old * 1000);
+			freqs.new = freqs.old;
+			return ret;
+		}
+	}
+
+	for_each_online_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+
+	return 0;
+}
+
+static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
+{
+	int ret;
+
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+	if (ret) {
+		pr_err("invalid frequency table: %d\n", ret);
+		return ret;
+	}
+
+	policy->cpuinfo.transition_latency = transition_latency;
+	policy->cur = clk_get_rate(cpu_clk) / 1000;
+
+	/*
+	 * The driver only supports the SMP configuartion where all processors
+	 * share the clock and voltage and clock.  Use cpufreq affected_cpus
+	 * interface to have all CPUs scaled together.
+	 */
+	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
+	cpumask_setall(policy->cpus);
+
+	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+
+	return 0;
+}
+
+static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
+{
+	cpufreq_frequency_table_put_attr(policy->cpu);
+
+	return 0;
+}
+
+static struct freq_attr *cpu0_cpufreq_attr[] = {
+	&cpufreq_freq_attr_scaling_available_freqs,
+	NULL,
+};
+
+static struct cpufreq_driver cpu0_cpufreq_driver = {
+	.flags = CPUFREQ_STICKY,
+	.verify = cpu0_verify_speed,
+	.target = cpu0_set_target,
+	.get = cpu0_get_speed,
+	.init = cpu0_cpufreq_init,
+	.exit = cpu0_cpufreq_exit,
+	.name = "generic_cpu0",
+	.attr = cpu0_cpufreq_attr,
+};
+
+static int __devinit cpu0_cpufreq_driver_init(void)
+{
+	struct device_node *np;
+	int ret;
+
+	np = of_find_node_by_path("/cpus/cpu at 0");
+	if (!np) {
+		pr_err("failed to find cpu0 node\n");
+		return -ENOENT;
+	}
+
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		pr_err("failed to get cpu0 device\n");
+		ret = -ENODEV;
+		goto out_put_node;
+	}
+
+	cpu_dev->of_node = np;
+
+	cpu_clk = clk_get(cpu_dev, NULL);
+	if (IS_ERR(cpu_clk)) {
+		ret = PTR_ERR(cpu_clk);
+		pr_err("failed to get cpu0 clock: %d\n", ret);
+		goto out_put_node;
+	}
+
+	cpu_reg = regulator_get(cpu_dev, "cpu0");
+	if (IS_ERR(cpu_reg)) {
+		pr_warn("failed to get cpu0 regulator\n");
+		cpu_reg = NULL;
+	}
+
+	ret = of_init_opp_table(cpu_dev);
+	if (ret) {
+		pr_err("failed to init OPP table: %d\n", ret);
+		goto out_put_node;
+	}
+
+	ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
+	if (ret) {
+		pr_err("failed to init cpufreq table: %d\n", ret);
+		goto out_put_node;
+	}
+
+	of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
+
+	if (of_property_read_u32(np, "clock-latency", &transition_latency))
+		transition_latency = CPUFREQ_ETERNAL;
+
+	if (cpu_reg) {
+		struct opp *opp;
+		unsigned long min_uV, max_uV;
+		int i;
+
+		/*
+		 * OPP is maintained in order of increasing frequency, and
+		 * freq_table initialised from OPP is therefore sorted in the
+		 * same order.
+		 */
+		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
+			;
+		opp = opp_find_freq_exact(cpu_dev,
+				freq_table[0].frequency * 1000, true);
+		min_uV = opp_get_voltage(opp);
+		opp = opp_find_freq_exact(cpu_dev,
+				freq_table[i-1].frequency * 1000, true);
+		max_uV = opp_get_voltage(opp);
+		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
+		if (ret > 0)
+			transition_latency += ret * 1000;
+	}
+
+	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
+	if (ret) {
+		pr_err("failed register driver: %d\n", ret);
+		goto out_free_table;
+	}
+
+	of_node_put(np);
+	return 0;
+
+out_free_table:
+	opp_free_cpufreq_table(cpu_dev, &freq_table);
+out_put_node:
+	of_node_put(np);
+	return ret;
+}
+late_initcall(cpu0_cpufreq_driver_init);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
1.7.5.4




From cyril at ti.com  Sun Aug  5 11:10:34 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 5 Aug 2012 11:10:34 -0400
Subject: [PATCH 00/22] Introducing the TI Keystone platform
In-Reply-To: <20120804083945.GB6802@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <20120804083945.GB6802@n2100.arm.linux.org.uk>
Message-ID: <501E8CEA.9050601@ti.com>

Hi Russell,

On 8/4/2012 4:39 AM, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2012 at 07:04:36PM -0400, Cyril Chemparathy wrote:
>> This series is a follow on to the RFC series posted earlier (archived at [1]).
>> The major change introduced here is the modification to the kernel patching
>> mechanism for phys_to_virt/virt_to_phys, in order to support LPAE platforms
>> that require late patching.  In addition to these changes, we've updated the
>> series based on feedback from the earlier posting.
>>
>> Most of the patches in this series are fixes and extensions to LPAE support on
>> ARM. The last three patches in this series are specific to the TI Keystone
>> platform, and are being provided here for the sake of completeness.  These
>> three patches are dependent on the smpops patch set (see [2]), and are not
>> ready to be merged in as yet.
>
> Can you explain why you want the kernel loaded above the 4GB watermark?
> This seems silly to me, as the kernel needs to run at points with a 1:1
> physical to virtual mapping, and you can't do that if the kernel is
> stored in physical memory above the 4GB watermark.
>

The Keystone family of devices is built to run with large (>8G) physical 
memory for certain use-cases.  From the CPUs perspective, this entire 
range of physical memory is mapped in linearly at 08:0000:0000, i.e., 
above the 4GB watermark.

The interconnect provides an aliased view of the first 2GB of this 
memory at the 8000:0000 offset.  This alias is intended primarily for 
boot-time usage, and does not support DMA coherence.  We considered the 
option of running with the first 2G of memory located under the 4GB 
watermark, and the rest located at the native >4GB location, but this 
would necessitate sparsemem, and would also break DMA coherence out of 
lowmem.  Hence the need for the more complicated approach implemented in 
this patch series.


The posted patch series manages to get an SMP system running out of 
memory beyond the 4GB watermark.  We identified a couple of places that 
needed the 1:1 physical to virtual mapping, and for these we take 
advantage of the alias view provided by the interconnect.  The two 
places that we found the need for 1:1 mapping were:

1. initial boot code in head.S:  here we've taken the approach of 
initially running out of the alias space, and then switching over to the 
high address space once we are safely in machine-specific territory.

2. idmap for secondary CPU boot:  here we've added a virt_to_idmap() 
facility that our sub-architecture then overrides to express the 
interconnect supported alias view.


We are well aware of the fact that we are barely scratching the surface 
of the problem space here, and we'd be very thankful for a heads up on 
issues that we may have missed so far.  We would similarly appreciate 
other better ideas to solve this problem in light of the unique 
constraints imposed here.

-- 
Thanks
- Cyril


From heiko at sntech.de  Sun Aug  5 11:38:27 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sun, 5 Aug 2012 17:38:27 +0200
Subject: [PATCH 0/2] ARM: S3C24XX: Fix compilation errors with 3.6-rc1
Message-ID: <201208051738.27728.heiko@sntech.de>

Small fallout from from the s3c64xx spi changes and from a dma change from
last year, that only surfaced after a gcc update.

Heiko Stuebner (2):
  ARM: S3C24XX: Add missing DMACH_DT_PROP
  ARM: S3C24XX: Fix s3c2410_dma_enqueue parameters

 arch/arm/mach-s3c24xx/include/mach/dma.h |    3 ++-
 arch/arm/plat-s3c24xx/dma.c              |    2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

-- 
1.7.2.3



From heiko at sntech.de  Sun Aug  5 11:39:17 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sun, 5 Aug 2012 17:39:17 +0200
Subject: [PATCH 1/2] ARM: S3C24XX: Add missing DMACH_DT_PROP
In-Reply-To: <201208051738.27728.heiko@sntech.de>
References: <201208051738.27728.heiko@sntech.de>
Message-ID: <201208051739.18355.heiko@sntech.de>

Commit 2b90807549 (spi: s3c64xx: add device tree support) requires
the DMACH_DT_PROP element in the dma_ch enum. It's not used on non-DT
platforms but has to be present nevertheless.

So mimic the dummy-add of DMACH_DT_PROP on s3c64xx for s3c24xx
machines, to correct the build breakage for the s3c24xx variants
using the s3c64xx-spi-driver.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/include/mach/dma.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 454831b..ee99fd5 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,8 @@
 */
 
 enum dma_ch {
-	DMACH_XD0,
+	DMACH_DT_PROP = -1,	/* not yet supported, do not use */
+	DMACH_XD0 = 0,
 	DMACH_XD1,
 	DMACH_SDI,
 	DMACH_SPI0,
-- 
1.7.2.3


From heiko at sntech.de  Sun Aug  5 11:39:48 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sun, 5 Aug 2012 17:39:48 +0200
Subject: [PATCH 2/2] ARM: S3C24XX: Fix s3c2410_dma_enqueue parameters
In-Reply-To: <201208051738.27728.heiko@sntech.de>
References: <201208051738.27728.heiko@sntech.de>
Message-ID: <201208051739.49023.heiko@sntech.de>

Commit d670ac019f60 (ARM: SAMSUNG: DMA Cleanup as per sparse) changed the
prototype of the s3c2410_dma_* functions to use the enum dma_ch instead
of an generic unsigned int.

In the s3c24xx dma.c s3c2410_dma_enqueue seems to have been forgotten,
the other functions there were changed correctly.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/plat-s3c24xx/dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 28f898f..db98e70 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
  * when necessary.
 */
 
-int s3c2410_dma_enqueue(unsigned int channel, void *id,
+int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
 			dma_addr_t data, int size)
 {
 	struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
-- 
1.7.2.3



From haojian.zhuang at gmail.com  Sun Aug  5 12:45:09 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 6 Aug 2012 00:45:09 +0800
Subject: [GIT PULL][for 3.7 v3] pull request from dt_mmp branch in pxa git tree
Message-ID: <CAN1soZwtVE2ud1t27Cw-_s0DxhMJTG9usu_u5xnEY8rnYfKy3g@mail.gmail.com>

Hi Olof & Arnd,

Please help to merge these patches from dt_mmp branch in pxa git tree.

It's the V3 version. The changes are in below.
v3:
1. Revert d03c1990c9681047bf94caa497c41172b3f28351 GPIO: gpio-pxa: fix
devicetree functions
since it's merged into Linus' gpio tree.

v2:
1. Add Linus's Ack in pinctrl driver.
2. Add chao's & haojian's patches for Tauros2 cache.


The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git dt_mmp

for you to fetch changes up to cd62ea8749e6383c0f76b57300be22503014b1c8:

  ARM: mmp: enable tauros2 cache in mmp2 dt (2012-08-06 00:39:24 +0800)

----------------------------------------------------------------
Chao Xie (7):
      ARM: pxa: support CKENC in clk_enable
      gpio: pxa: add chain_eneter and chain_exit for irq handler
      ARM: cache: fix uninitialized ptr in tauros2_init
      ARM: cache: add cputype.h for tauros2
      ARM: cache: add extra feature enable for tauros2
      ARM: mmp&dove: modify tauros2_init call
      ARM: cache: add dt support for tauros2 cache

Daniel Mack (7):
      RTC: add DT bindings to pxa-rtc
      MTD: pxa3xx-nand: add devicetree bindings
      GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
      ARM: pxa: add devicetree code for irq handling
      ARM: pxa3xx: skip default device initialization when booting via DT
      ARM: pxa3xx: add generic DT machine code
      ARM: pxa: add .dtsi files

Haojian Zhuang (8):
      pinctrl: append new pins and groups in pxa910
      pinctrl: add pinconf support in pxa3xx
      pinctrl: support dt in pxa series
      pinctrl: append new groups of mmp2
      ARM: mmp: select pinctrl for boards with DT
      ARM: dts: add pinctrl in PXA DT files
      ARM: mmp: enable tauros2 cache in pxa910
      ARM: mmp: enable tauros2 cache in mmp2 dt

 .../devicetree/bindings/arm/mrvl/tauros2.txt       |   17 +
 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |   31 ++
 .../bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt       |   35 +++
 Documentation/devicetree/bindings/rtc/pxa-rtc.txt  |   14 +
 arch/arm/boot/dts/mmp2-brownstone.dts              |   51 +++
 arch/arm/boot/dts/mmp2.dtsi                        |   10 +
 arch/arm/boot/dts/pxa168.dtsi                      |    5 +
 arch/arm/boot/dts/pxa27x.dtsi                      |   14 +
 arch/arm/boot/dts/pxa2xx.dtsi                      |  132 ++++++++
 arch/arm/boot/dts/pxa3xx.dtsi                      |   32 ++
 arch/arm/boot/dts/pxa910-dkb.dts                   |   47 +++
 arch/arm/boot/dts/pxa910.dtsi                      |   10 +
 arch/arm/include/asm/hardware/cache-tauros2.h      |    5 +-
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-mmp/Kconfig                          |    2 +
 arch/arm/mach-mmp/mmp2.c                           |    2 +-
 arch/arm/mach-mmp/pxa910.c                         |    4 +
 arch/arm/mach-pxa/Kconfig                          |   12 +
 arch/arm/mach-pxa/Makefile                         |    3 +
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    8 +-
 arch/arm/mach-pxa/irq.c                            |  131 ++++++--
 arch/arm/mach-pxa/pxa-dt.c                         |   63 ++++
 arch/arm/mach-pxa/pxa3xx.c                         |   21 +-
 arch/arm/mm/cache-tauros2.c                        |   83 +++--
 drivers/gpio/gpio-pxa.c                            |   77 ++---
 drivers/mtd/nand/pxa3xx_nand.c                     |   85 ++++-
 drivers/pinctrl/pinctrl-mmp2.c                     |   18 +-
 drivers/pinctrl/pinctrl-pxa168.c                   |   10 +-
 drivers/pinctrl/pinctrl-pxa3xx.c                   |  325 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-pxa3xx.h                   |   17 +
 drivers/pinctrl/pinctrl-pxa910.c                   |   16 +-
 drivers/rtc/rtc-pxa.c                              |   11 +
 32 files changed, 1169 insertions(+), 124 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
 create mode 100644
Documentation/devicetree/bindings/pinctrl/mrvl,pxa3xx-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
 create mode 100644 arch/arm/boot/dts/pxa27x.dtsi
 create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
 create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
 create mode 100644 arch/arm/mach-pxa/pxa-dt.c


From festevam at gmail.com  Sun Aug  5 13:04:18 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun,  5 Aug 2012 14:04:18 -0300
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
Message-ID: <1344186258-30841-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Enable USB host.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/mxs_defconfig |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..73842f9 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -95,7 +95,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -110,6 +110,18 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
-- 
1.7.1



From festevam at gmail.com  Sun Aug  5 13:08:07 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 5 Aug 2012 14:08:07 -0300
Subject: [PATCH] clk: mxs: Register USB clocks for mx23
In-Reply-To: <20120620143830.GF2253@S2101-09.ap.freescale.net>
References: <1340148392-9847-1-git-send-email-festevam@gmail.com>
 <20120620143830.GF2253@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>

On Wed, Jun 20, 2012 at 11:38 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
...
>> +     clk_register_clkdev(clks[usb_pwr], NULL, "8007c000.usbphy");
>> +     clk_register_clkdev(clks[usb], NULL, "80080000.usb");
>
> It depends on the node name in device tree.  I would defer this
> a little bit to have the node name in dts settled down first.

Now that the mxs usb driver is in mainline, could this patch be applied?

Regards,

Fabio Estevam


From aaro.koskinen at iki.fi  Sun Aug  5 13:32:06 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Sun,  5 Aug 2012 20:32:06 +0300
Subject: [PATCH] ARM: dma-mapping: fix atomic allocation alignment
Message-ID: <1344187926-22404-1-git-send-email-aaro.koskinen@iki.fi>

The alignment mask is calculated incorrectly. Fixing the calculation
makes strange hangs/lockups disappear during the boot with Amstrad E3
and 3.6-rc1 kernel.

Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>
---
 arch/arm/mm/dma-mapping.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 2cc77b7..0e0466d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -423,7 +423,7 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	unsigned int pageno;
 	unsigned long flags;
 	void *ptr = NULL;
-	size_t align;
+	unsigned long align_mask;
 
 	if (!pool->vaddr) {
 		WARN(1, "coherent pool not initialised!\n");
@@ -435,11 +435,11 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	 * small, so align them to their order in pages, minimum is a page
 	 * size. This helps reduce fragmentation of the DMA space.
 	 */
-	align = PAGE_SIZE << get_order(size);
+	align_mask = (1 << get_order(size)) - 1;
 
 	spin_lock_irqsave(&pool->lock, flags);
 	pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
-					    0, count, (1 << align) - 1);
+					    0, count, align_mask);
 	if (pageno < pool->nr_pages) {
 		bitmap_set(pool->bitmap, pageno, count);
 		ptr = pool->vaddr + PAGE_SIZE * pageno;
-- 
1.7.2.5



From linus.walleij at linaro.org  Sun Aug  5 16:28:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 22:28:36 +0200
Subject: [PATCH V2 5/6] x86: add CONFIG_ARM_AMBA, selected by STA2X11
In-Reply-To: <20120703193403.GA26355@n2100.arm.linux.org.uk>
References: <2b797c83-6a3c-4051-841a-a4cfa9d1cae1@email.android.com>
 <20120701104401.GA4352@mail.gnudd.com>
 <20120703130042.GA10007@mail.gnudd.com>
 <201207031319.40884.arnd@arndb.de>
 <20120703193403.GA26355@n2100.arm.linux.org.uk>
Message-ID: <CACRpkdZLGhgpUJy_3QGYvGRqyxMkkPPSdyP==h5YurWqKnctBw@mail.gmail.com>

On Tue, Jul 3, 2012 at 9:34 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Jul 03, 2012 at 01:19:40PM +0000, Arnd Bergmann wrote:
>> On Tuesday 03 July 2012, Alessandro Rubini wrote:
>> >    drivers/dma/amba-pl08x.c: needs <asm/hardware/pl080.h>
>> >      proposed fix: move pl080.h to include/linux
>>
>> Note that there is already an include/linux/amba/pl08x.h.
>> I would just move the few parts of pl080.h that are actually
>> needed with global visibility there, and move the rest
>> to drivers/dma/.
>
> NAK.  It's the entire register definitions for the PL08x, which we really
> should not be exporting to common code.

The major reason why that file is there is that there is *another*
PL080 driver in arch/arm/mach-s3c64xx/dma.c which I repeatedly
asked the Samsung people to replace with the
drivers/dma/amba-pl08x.c driver. :-(

When I worked on the PL08x driver in drivers/dma I reused
this header to avoid code duplication.

Now that thing is stranding in the way. Alim, Kukjin, what's happening?

I feel tempted to update Alim's patch myself and push it on you
soon...

> Please wait until _after_ my DMA engine stuff (which is now in linux-next)
> makes its way upstream before touching any of this stuff, otherwise there's
> going to be conflicts.

That stuff is in now, looking real good. Good work on this!

> As part of my patch series, this gets rid of a number of uses of it in
> arch/arm, but there's still the .cctl_memcpy initializer which does. I've
> not yet checked whether all implementations use the same value (they
> probably do), and if so then it should be eliminated from platform code
> and moved into the driver.

Sounds like a plan. If we just get rid of the duplicate implementation
we're going somewhere.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sun Aug  5 16:37:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun,  5 Aug 2012 22:37:55 +0200
Subject: [PATCH] ARM: integrator: use clk_prepare_enable() for timer
Message-ID: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>

The Integrator timer is using the clock framework to get the
timer frequency, but missed to prepare the clock before enabling.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-integrator/integrator_ap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 7b1055c..3b22675 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -456,7 +456,7 @@ static void __init ap_init_timer(void)
 
 	clk = clk_get_sys("ap_timer", NULL);
 	BUG_ON(IS_ERR(clk));
-	clk_enable(clk);
+	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
 
 	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-- 
1.7.11.2



From arnaud.patard at rtp-net.org  Sun Aug  5 16:35:56 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Sun, 05 Aug 2012 22:35:56 +0200
Subject: [patch] ARM: Kirkwood: Fix iconnect leds
Message-ID: <20120805203610.540496769@rtp-net.org>

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Name: iconnect-fix-leds.patch
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From arnaud.patard at rtp-net.org  Sun Aug  5 16:35:57 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Sun, 05 Aug 2012 22:35:57 +0200
Subject: [patch] ARM: Kirkwood: fix Makefile.boot
References: <20120805203555.457907381@rtp-net.org>
Message-ID: <20120805203610.644315269@rtp-net.org>

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From arnaud.patard at rtp-net.org  Sun Aug  5 16:39:13 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Sun, 05 Aug 2012 22:39:13 +0200
Subject: [patch 2/2] ARM: Kirkwood: Describe iconnect nand in DT.
References: <20120805203911.915580862@rtp-net.org>
Message-ID: <20120805203920.908663535@rtp-net.org>

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From arnaud.patard at rtp-net.org  Sun Aug  5 16:39:12 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Sun, 05 Aug 2012 22:39:12 +0200
Subject: [patch 1/2] ARM: Kirkwood: Describe iconnect keys in DT.
Message-ID: <20120805203920.804712126@rtp-net.org>

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From linus.walleij at linaro.org  Sun Aug  5 16:48:41 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 5 Aug 2012 22:48:41 +0200
Subject: [PATCH] ARM: integrator: use clk_prepare_enable() for timer
In-Reply-To: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>
References: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CACRpkdZqaJhCYuW+3WYacjuwJ3zshAexDqLSUJgCCDzVS+=X7g@mail.gmail.com>

On Sun, Aug 5, 2012 at 10:37 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> The Integrator timer is using the clock framework to get the
> timer frequency, but missed to prepare the clock before enabling.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Arnd, Olof,

If this patch looks OK to you I request that you apply it alone, no pull
requests, too much hazzle for a single patch...

Yours,
Linus Walleij


From heiko at sntech.de  Sun Aug  5 17:54:18 2012
From: heiko at sntech.de (Heiko =?iso-8859-15?q?St=FCbner?=)
Date: Sun, 5 Aug 2012 23:54:18 +0200
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <1343826351-8756-2-git-send-email-p.paneri@samsung.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <1343826351-8756-2-git-send-email-p.paneri@samsung.com>
Message-ID: <201208052354.18978.heiko@sntech.de>

Hi Praveen,

Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> smdk6410 and smdkv310. More SoCs can be brought under later.

Looks cool.

From what I've seen the phy controllers on newer Samsung SoCs are still 
somewhat similar to the one on my s3c2416/2450 machines. So hopefully at some 
point after the driver has settled, I'll find the time to add support for 
these to the phy driver.

Out of curiosity, what does the "sec" in sec_usbphy for?



> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>

Acked-by: Heiko Stuebner <heiko at sntech.de>


Heiko


> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/sec_usbphy.c                       |  354
> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h                       | 
>  48 +++
>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>  6 files changed, 425 insertions(+), 0 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
> 100644 drivers/usb/phy/sec_usbphy.c
>  create mode 100644 drivers/usb/phy/sec_usbphy.h
> 
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
> 100644
> index 0000000..fefd9c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -0,0 +1,9 @@
> +* Samsung's usb phy transceiver
> +
> +The Samsung's phy transceiver is used for controlling usb otg phy for
> +s3c-hsotg usb device controller.
> +
> +Required properties:
> +- compatible : should be "samsung,exynos4210-usbphy"
> +- reg : base physical address of the phy registers and length of memory
> mapped +	region.
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index e7cf84f..abbebe2 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -15,3 +15,11 @@ config USB_ISP1301
> 
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called isp1301.
> +
> +config SEC_USBPHY
> +       bool "Samsung USB PHY controller Driver"
> +       depends on USB_S3C_HSOTG
> +       select USB_OTG_UTILS
> +       help
> +         Enable this to support Samsung USB phy controller for samsung
> +         SoCs.
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index eca095b..6bb66f0 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -5,3 +5,4 @@
>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
> 
>  obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
> +obj-$(CONFIG_SEC_USBPHY)		+= sec_usbphy.o
> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
> new file mode 100644
> index 0000000..33119eb
> --- /dev/null
> +++ b/drivers/usb/phy/sec_usbphy.c
> @@ -0,0 +1,354 @@
> +/* linux/drivers/usb/phy/sec_usbphy.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * Author: Praveen Paneri <p.paneri at samsung.com>
> + *
> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
> controller + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +*/
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/usb/otg.h>
> +#include <linux/platform_data/s3c-hsotg.h>
> +
> +#include "sec_usbphy.h"
> +
> +enum sec_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_EXYNOS4210,
> +};
> +
> +/*
> + * struct sec_usbphy - transceiver driver state
> + * @phy: transceiver structure
> + * @plat: platform data
> + * @dev: The parent device supplied to the probe function
> + * @clk: usb phy clock
> + * @regs: usb phy register memory base
> + * @cpu_type: machine identifier
> + */
> +struct sec_usbphy {
> +	struct usb_phy	phy;
> +	struct s3c_usbphy_plat *plat;
> +	struct device	*dev;
> +	struct clk	*clk;
> +	void __iomem	*regs;
> +	int		cpu_type;
> +};
> +
> +#define phy_to_sec(x)		container_of((x), struct sec_usbphy, phy)
> +
> +/*
> + * Enables or disables the phy clock
> + * returns 0 on success else the error
> + */
> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
> +{
> +	if (on) {
> +		if (!sec->clk) {
> +			sec->clk = clk_get(sec->dev, "otg");
> +			if (IS_ERR(sec->clk)) {
> +				dev_err(sec->dev, "Failed to get otg clock\n");
> +				return PTR_ERR(sec->clk);
> +			}
> +		}
> +		clk_enable(sec->clk);
> +	} else {
> +		clk_disable(sec->clk);
> +		clk_put(sec->clk);
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Returns reference clock frequency
> + */
> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
> +{
> +	struct clk *ref_clk;
> +	int refclk_freq = 0;
> +
> +	ref_clk = clk_get(sec->dev, "xusbxti");
> +	if (IS_ERR(ref_clk)) {
> +		dev_err(sec->dev, "Failed to get reference clock\n");
> +		return PTR_ERR(ref_clk);
> +	}
> +
> +	switch (clk_get_rate(ref_clk)) {
> +	case 12 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> +		break;
> +	case 24 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> +		break;
> +	default:
> +	case 48 * MHZ:
> +		/* default reference clock */
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> +		break;
> +	}
> +	clk_put(ref_clk);
> +
> +	return refclk_freq;
> +}
> +
> +static void sec_usbphy_enable(struct sec_usbphy *sec)
> +{
> +	void __iomem *regs = sec->regs;
> +	u32 phypwr;
> +	u32 phyclk;
> +	u32 rstcon;
> +
> +	/* set clock frequency for PLL */
> +	phyclk = sec_usbphy_get_refclk_freq(sec);
> +	phypwr = readl(regs + S3C_PHYPWR);
> +	rstcon = readl(regs + S3C_RSTCON);
> +
> +	switch (sec->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
> +		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +	default:
> +		break;
> +	}
> +
> +	writel(phyclk, regs + S3C_PHYCLK);
> +	/* set to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +	/* reset all ports of PHY and Link */
> +	writel(rstcon, regs + S3C_RSTCON);
> +	udelay(10);
> +	rstcon &= ~S3C_RSTCON_PHY;
> +	writel(rstcon, regs + S3C_RSTCON);
> +}
> +
> +static void sec_usbphy_disable(struct sec_usbphy *sec)
> +{
> +	void __iomem *regs = sec->regs;
> +	u32 phypwr;
> +
> +	phypwr = readl(regs + S3C_PHYPWR);
> +
> +	switch (sec->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phypwr |= S3C_PHYPWR_NORMAL_MASK;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
> +	default:
> +		break;
> +	}
> +
> +	/* unset to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +}
> +
> +/*
> + * The function passed to the usb driver for phy initialization
> + */
> +static int sec_usbphy_init(struct usb_phy *phy)
> +{
> +	struct sec_usbphy *sec;
> +	int ret = 0;
> +
> +	sec = phy_to_sec(phy);
> +
> +	/* Enable the phy clock */
> +	ret = sec_usbphy_clk_control(sec, true);
> +	if (ret) {
> +		dev_err(sec->dev, "phy clock enable failed\n");
> +		return ret;
> +	}
> +
> +	/* Disable phy isolation */
> +	if (sec->plat && sec->plat->pmu_isolation)
> +		sec->plat->pmu_isolation(false);
> +
> +	/* Initialize usb phy registers */
> +	sec_usbphy_enable(sec);
> +	return ret;
> +}
> +
> +/*
> + * The function passed to the usb driver for phy shutdown
> + */
> +static void sec_usbphy_shutdown(struct usb_phy *phy)
> +{
> +	struct sec_usbphy *sec;
> +
> +	sec = phy_to_sec(phy);
> +
> +	/* De-initialize usb phy registers */
> +	sec_usbphy_disable(sec);
> +
> +	/* Enable phy isolation */
> +	if (sec->plat && sec->plat->pmu_isolation)
> +		sec->plat->pmu_isolation(true);
> +
> +	/* Disable the phy clock */
> +	sec_usbphy_clk_control(sec, false);
> +}
> +
> +static const struct of_device_id sec_usbphy_dt_match[];
> +
> +static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
> +{
> +#ifdef CONFIG_OF
> +	int data;
> +	if (pdev->dev.of_node) {
> +		const struct of_device_id *match;
> +		match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
> +		data = (int) match->data;
> +		return data;
> +	}
> +#endif
> +	return platform_get_device_id(pdev)->driver_data;
> +}
> +
> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
> +{
> +	struct sec_usbphy *sec;
> +	struct s3c_usbphy_plat *pdata;
> +	struct device *dev = &pdev->dev;
> +	struct resource *phy_mem;
> +	void __iomem	*phy_base;
> +	int	ret;
> +
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!phy_mem) {
> +		dev_err(dev, "%s: missing mem resource\n", __func__);
> +		return -ENODEV;
> +	}
> +
> +	phy_base = devm_request_and_ioremap(dev, phy_mem);
> +	if (!phy_base) {
> +		dev_err(dev, "%s: register mapping failed\n", __func__);
> +		return -ENXIO;
> +	}
> +
> +	sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
> +	if (!sec)
> +		return -ENOMEM;
> +
> +	sec->dev		= &pdev->dev;
> +	sec->plat		= pdata;
> +	sec->regs		= phy_base;
> +	sec->phy.dev		= sec->dev;
> +	sec->phy.label		= "sec-usbphy";
> +	sec->phy.init		= sec_usbphy_init;
> +	sec->phy.shutdown	= sec_usbphy_shutdown;
> +	sec->cpu_type		= sec_usbphy_get_driver_data(pdev);
> +
> +	ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
> +	if (ret)
> +		goto err;
> +
> +	platform_set_drvdata(pdev, sec);
> +
> +	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
> +err:
> +	return ret;
> +}
> +
> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
> +{
> +	struct sec_usbphy *sec = platform_get_drvdata(pdev);
> +
> +	usb_remove_phy(&sec->phy);
> +
> +	if (sec->clk) {
> +		clk_put(sec->clk);
> +		sec->clk = NULL;
> +	}
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id sec_usbphy_dt_match[] = {
> +	{
> +		.compatible = "samsung,s3c64xx-usbphy",
> +		.data = (void *)TYPE_S3C64XX,
> +	}, {
> +		.compatible = "samsung,exynos4210-usbphy",
> +		.data = (void *)TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
> +#else
> +#define sec_usbphy_dt_match NULL
> +#endif
> +
> +static struct platform_device_id sec_usbphy_driver_ids[] = {
> +	{
> +		.name		= "s3c64xx-usbphy",
> +		.driver_data	= TYPE_S3C64XX,
> +	}, {
> +		.name		= "exynos4210-usbphy",
> +		.driver_data	= TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
> +
> +static struct platform_driver sec_usbphy_driver = {
> +	.probe		= sec_usbphy_probe,
> +	.remove		= __devexit_p(sec_usbphy_remove),
> +	.id_table	= sec_usbphy_driver_ids,
> +	.driver		= {
> +		.name	= "sec-usbphy",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = sec_usbphy_dt_match,
> +	},
> +};
> +
> +static int __init sec_usbphy_driver_init(void)
> +{
> +	return platform_driver_register(&sec_usbphy_driver);
> +}
> +subsys_initcall(sec_usbphy_driver_init);
> +
> +static void __exit sec_usbphy_driver_exit(void)
> +{
> +	return platform_driver_unregister(&sec_usbphy_driver);
> +}
> +module_exit(sec_usbphy_driver_exit);
> +
> +MODULE_DESCRIPTION("Samsung USB phy controller");
> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:sec-usbphy");
> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
> new file mode 100644
> index 0000000..06e81d4
> --- /dev/null
> +++ b/drivers/usb/phy/sec_usbphy.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + * Author: Praveen Paneri <p.paneri at samsung.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify
> it + * under  the terms of  the GNU General  Public License as published
> by the + * Free Software Foundation;  either version 2 of the  License, or
> (at your + * option) any later version.
> + */
> +
> +#ifndef __SEC_USBPHY_H
> +#define __SEC_USBPHY_H
> +
> +#define S3C_PHYPWR				(0x00)
> +
> +#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
> +#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
> +#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
> +#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
> +/* For Exynos4 */
> +#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
> +#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
> +
> +#define S3C_PHYCLK				(0x04)
> +
> +#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
> +#define S3C_PHYCLK_EXT_OSC			(1 << 5)
> +#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
> +#define S3C_PHYCLK_ID_PULL			(1 << 2)
> +#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
> +#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
> +#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
> +#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
> +#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
> +
> +#define S3C_RSTCON				(0x08)
> +
> +#define S3C_RSTCON_PHYCLK			(1 << 2)
> +#define S3C_RSTCON_HCLK				(1 << 1)
> +#define S3C_RSTCON_PHY				(1 << 0)
> +
> +#ifndef MHZ
> +#define MHZ (1000*1000)
> +#endif
> +
> +#endif /* __SEC_USBPHY_H */
> diff --git a/include/linux/platform_data/s3c-hsotg.h
> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
> --- a/include/linux/platform_data/s3c-hsotg.h
> +++ b/include/linux/platform_data/s3c-hsotg.h
> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>  	int (*phy_exit)(struct platform_device *pdev, int type);
>  };
> 
> +struct s3c_usbphy_plat {
> +	void (*pmu_isolation)(int on);
> +};
> +
>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
> 
>  #endif /* __LINUX_USB_S3C_HSOTG_H */



From anton.vorontsov at linaro.org  Sun Aug  5 19:02:38 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun, 5 Aug 2012 16:02:38 -0700
Subject: [PATCH 0/9] Get rid of FIQ_START/enable/disable_fiq() + some FIQ
 cleanups
Message-ID: <20120805230238.GA1663@lizard>

Hello Russell,

During KDB FIQ patches review you mentioned that I should not introduce
another FIQ_START. It seems that in v3.6-rc the FIQ_START issue was
somewhat band-aided, i.e. machines don't necessary need to define this
stuff any longer, but I also read the background of the issue, and you
once said that you don't want the FIQ subsystem to mess with genirq.

It is surely makes sense as FIQs are arch-specific, plus FIQs are special
in that way that platform makers are free to connects device directly
to the FIQ line, avoiding IC routing, and then enable_fiq(<IRQ>) would
look awkward, at the best.

So, given that, it seems that the only entity that knows for sure how
the particular FIQ is routed is whoever claims the FIQ and fills-in the
fiq_handler struct. It might make sense to introduce disable/enable
callbacks in the fiq_handler struct, and then prototypes for disable/
enable FIQ calls would look like this:

	enable_fiq(struct fiq_handler *fh);
	disable_fiq(struct fiq_handler *fh);

I.e. completely abstracted from the genirq.

Although, to not duplicate IC code, I think it's pretty legitimate to
call genirq functions iff the caller knows for sure that FIQ comes from
IRQ line and it is is routed through the well-known platform IC.

In that case (which is a majority), the typical user would do this:

	static int irq_line;

	void foo_enable_fiq(struct fiq_handler *fh)
	{
		enable_irq(irq_line);
	}

	static struct fiq_handler foo_fiq = {
		.name = "foo",
		.enable_fiq = foo_enable_fiq,
	};

	claim_fiq(&foo_fiq);
	enable_fiq(&foo_fiq);

Obviously, it's needless indirection, so I don't do this. If we ever
pass 'foo_fiq' to some device, which does not know all the routing
details, then it would make sense to introduce it, but not now.

So, the patch set is pretty straightforward:

- Get rid of FIQ_START. Nobody but platform-specific code (and drivers)
  should know the details about which interrupt can be routed to FIQ
  and which cannot;

- Remove disable/enable_fiq() calls from the FIQ subsys (the calls can
  be reintroduced w/ new prototypes when/if needed).

Does the approach make sense?

Thanks!

--
 arch/arm/include/asm/fiq.h                |    2 --
 arch/arm/include/asm/mach/irq.h           |    9 +++++++--
 arch/arm/kernel/fiq.c                     |   22 +++-------------------
 arch/arm/kernel/irq.c                     |    2 --
 arch/arm/mach-rpc/dma.c                   |    4 ++--
 arch/arm/mach-rpc/include/mach/irqs.h     |    8 ++++----
 arch/arm/mach-rpc/irq.c                   |   21 +++++----------------
 arch/arm/mach-s3c24xx/include/mach/irqs.h |    3 ---
 arch/arm/plat-mxc/avic.c                  |    4 +---
 arch/arm/plat-mxc/include/mach/irqs.h     |    2 --
 arch/arm/plat-mxc/tzic.c                  |    4 +---
 arch/arm/plat-omap/include/plat/irqs.h    |    4 ----
 arch/arm/plat-s3c24xx/irq.c               |    6 ++----
 drivers/media/video/mx1_camera.c          |    6 +++---
 sound/soc/fsl/imx-pcm-fiq.c               |    4 ++--
 15 files changed, 30 insertions(+), 71 deletions(-)

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From anton.vorontsov at linaro.org  Sun Aug  5 19:03:31 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:31 -0700
Subject: [PATCH 1/9] ARM: mach-rpc: Don't register FIQs with genirq
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-1-git-send-email-anton.vorontsov@linaro.org>

mach-rps registers FIQ controller with genirq, which makes no sense:
these FIQs cannot be routed to IRQs, so there is no need to register
it with genirq.

This effectively makes FIQ_START irrelevant.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/mach-rpc/dma.c               |    4 ++--
 arch/arm/mach-rpc/include/mach/irqs.h |    5 +++++
 arch/arm/mach-rpc/irq.c               |   19 ++++---------------
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 85883b2..4a525be 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -289,13 +289,13 @@ static void floppy_enable_dma(unsigned int chan, dma_t *dma)
 
 	set_fiq_handler(fiqhandler_start, fiqhandler_length);
 	set_fiq_regs(&regs);
-	enable_fiq(fdma->fiq);
+	iomd_unmask_fiq(fdma->fiq);
 }
 
 static void floppy_disable_dma(unsigned int chan, dma_t *dma)
 {
 	struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
-	disable_fiq(fdma->fiq);
+	iomd_mask_fiq(fdma->fiq);
 	release_fiq(&fh);
 }
 
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index 6868e17..f27ead1 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -37,6 +37,11 @@
 #define FIQ_EXPANSIONCARD	6
 #define FIQ_FORCE		7
 
+#ifndef __ASSEMBLY__
+extern void iomd_mask_fiq(int fiq);
+extern void iomd_unmask_fiq(int fiq);
+#endif
+
 /*
  * This is the offset of the FIQ "IRQ" numbers
  */
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 3e4fa84..a4221b3 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -89,30 +89,24 @@ static struct irq_chip iomd_dma_chip = {
 	.irq_unmask	= iomd_unmask_irq_dma,
 };
 
-static void iomd_mask_irq_fiq(struct irq_data *d)
+void iomd_mask_fiq(int fiq)
 {
 	unsigned int val, mask;
 
-	mask = 1 << (d->irq & 7);
+	mask = 1 << (fiq & 7);
 	val = iomd_readb(IOMD_FIQMASK);
 	iomd_writeb(val & ~mask, IOMD_FIQMASK);
 }
 
-static void iomd_unmask_irq_fiq(struct irq_data *d)
+void iomd_unmask_fiq(int fiq)
 {
 	unsigned int val, mask;
 
-	mask = 1 << (d->irq & 7);
+	mask = 1 << (fiq & 7);
 	val = iomd_readb(IOMD_FIQMASK);
 	iomd_writeb(val | mask, IOMD_FIQMASK);
 }
 
-static struct irq_chip iomd_fiq_chip = {
-	.irq_ack	= iomd_mask_irq_fiq,
-	.irq_mask	= iomd_mask_irq_fiq,
-	.irq_unmask	= iomd_unmask_irq_fiq,
-};
-
 extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
 
 void __init rpc_init_irq(void)
@@ -155,11 +149,6 @@ void __init rpc_init_irq(void)
 						 handle_level_irq);
 			set_irq_flags(irq, flags);
 			break;
-
-		case 64 ... 71:
-			irq_set_chip(irq, &iomd_fiq_chip);
-			set_irq_flags(irq, IRQF_VALID);
-			break;
 		}
 	}
 
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:32 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:32 -0700
Subject: [PATCH 2/9] ARM: plat-s3c24xx: Don't use FIQ_START
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-2-git-send-email-anton.vorontsov@linaro.org>

We're about to remove FIQ_START mess, so move the platform-specific
detail inside platform-specific s3c24xx_set_fiq().

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/plat-s3c24xx/irq.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index fe57bbb..e4e9567 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -503,7 +503,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
 	unsigned offs;
 
 	if (on) {
-		offs = irq - FIQ_START;
+		offs = irq - IRQ_EINT0;
 		if (offs > 31)
 			return -EINVAL;
 
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:33 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:33 -0700
Subject: [PATCH 3/9] [media] mx1_camera: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-3-git-send-email-anton.vorontsov@linaro.org>

The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
passed to it, so it's pretty clear that the driver is absolutely sure
that the FIQ is routed via platform-specific IC, and that the cookie can
be used to mask/unmask FIQs. So, let's switch to the genirq routines,
since we're about to remove FIQ-specific variants.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/media/video/mx1_camera.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index d2e6f82..1536d09 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -801,7 +801,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
 	set_fiq_regs(&regs);
 
 	mxc_set_irq_fiq(irq, 1);
-	enable_fiq(irq);
+	enable_irq(irq);
 
 	pcdev->soc_host.drv_name	= DRIVER_NAME;
 	pcdev->soc_host.ops		= &mx1_soc_camera_host_ops;
@@ -817,7 +817,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
 	return 0;
 
 exit_free_irq:
-	disable_fiq(irq);
+	disable_irq(irq);
 	mxc_set_irq_fiq(irq, 0);
 	release_fiq(&fh);
 exit_free_dma:
@@ -842,7 +842,7 @@ static int __exit mx1_camera_remove(struct platform_device *pdev)
 	struct resource *res;
 
 	imx_dma_free(pcdev->dma_chan);
-	disable_fiq(pcdev->irq);
+	disable_irq(pcdev->irq);
 	mxc_set_irq_fiq(pcdev->irq, 0);
 	release_fiq(&fh);
 
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:34 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:34 -0700
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>

The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
passed to it, so it's pretty clear that the driver is absolutely sure
that the FIQ is routed via platform-specific IC, and that the cookie can
be used to mask/unmask FIQs. So, let's switch to the genirq routines,
since we're about to remove FIQ-specific variants.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 sound/soc/fsl/imx-pcm-fiq.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index ee27ba3..993e37d 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -139,7 +139,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 		hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
 		      HRTIMER_MODE_REL);
 		if (++fiq_enable == 1)
-			enable_fiq(imx_pcm_fiq);
+			enable_irq(imx_pcm_fiq);
 
 		break;
 
@@ -149,7 +149,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 		atomic_set(&iprtd->running, 0);
 
 		if (--fiq_enable == 0)
-			disable_fiq(imx_pcm_fiq);
+			disable_irq(imx_pcm_fiq);
 
 		break;
 	default:
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:35 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:35 -0700
Subject: [PATCH 5/9] ARM: FIQ: Remove enable_fiq() and disable_fiq() calls
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-5-git-send-email-anton.vorontsov@linaro.org>

There are no users left, so these can be removed.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/include/asm/fiq.h |    2 --
 arch/arm/kernel/fiq.c      |   15 ---------------
 2 files changed, 17 deletions(-)

diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h
index d493d0b..a293be4 100644
--- a/arch/arm/include/asm/fiq.h
+++ b/arch/arm/include/asm/fiq.h
@@ -36,8 +36,6 @@ struct fiq_handler {
 extern int claim_fiq(struct fiq_handler *f);
 extern void release_fiq(struct fiq_handler *f);
 extern void set_fiq_handler(void *start, unsigned int length);
-extern void enable_fiq(int fiq);
-extern void disable_fiq(int fiq);
 
 /* helpers defined in fiqasm.S: */
 extern void __set_fiq_regs(unsigned long const *regs);
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 2adda11..29b93b8 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -122,28 +122,13 @@ void release_fiq(struct fiq_handler *f)
 	while (current_fiq->fiq_op(current_fiq->dev_id, 0));
 }
 
-static int fiq_start;
-
-void enable_fiq(int fiq)
-{
-	enable_irq(fiq + fiq_start);
-}
-
-void disable_fiq(int fiq)
-{
-	disable_irq(fiq + fiq_start);
-}
-
 EXPORT_SYMBOL(set_fiq_handler);
 EXPORT_SYMBOL(__set_fiq_regs);	/* defined in fiqasm.S */
 EXPORT_SYMBOL(__get_fiq_regs);	/* defined in fiqasm.S */
 EXPORT_SYMBOL(claim_fiq);
 EXPORT_SYMBOL(release_fiq);
-EXPORT_SYMBOL(enable_fiq);
-EXPORT_SYMBOL(disable_fiq);
 
 void __init init_FIQ(int start)
 {
 	no_fiq_insn = *(unsigned long *)0xffff001c;
-	fiq_start = start;
 }
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:36 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:36 -0700
Subject: [PATCH 6/9] ARM: FIQ: Remove FIQ_START
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-6-git-send-email-anton.vorontsov@linaro.org>

RPC:

 FIQ_START is irrelevant nowadays, the arch uses platform-specific
 iomd_{,un}mask_fiq() calls.

OMAP1:

 The only user of FIQs is MACH_AMS_DELTA, and in particular its
 drivers/input/serio/ams_delta_serio.c driver. The driver does not rely
 on the FIQ interrupts directly, instead it uses a "deffered fiq"
 interrupt (raised after a buffer filled by the FIQ routine).

 The FIQ handling routines are not using disable_fiq() or enable_fiq()
 stuff, so it currently does not use FIQ_START at all -- the asm code
 uses OMAP_IH1_BASE and twiddles the bits itself.

S3C:

 The only user of FIQs on s3c24xx is spi-s3c24xx driver. The driver
 works with interrupt controller directly (via S3C24XX_VA_IRQ base
 address), and does not use IRQ subsystem to mask/unmask IRQs.

MXC:

 Users now use enable/disable_irq() routines. The drivers rely on a
 correctly passed VIRQ cookie anyway, so FIQ_START becomes irrelevant.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/include/asm/mach/irq.h           |    2 +-
 arch/arm/kernel/fiq.c                     |    2 +-
 arch/arm/mach-rpc/include/mach/irqs.h     |    5 -----
 arch/arm/mach-rpc/irq.c                   |    2 +-
 arch/arm/mach-s3c24xx/include/mach/irqs.h |    3 ---
 arch/arm/plat-mxc/avic.c                  |    2 +-
 arch/arm/plat-mxc/include/mach/irqs.h     |    2 --
 arch/arm/plat-mxc/tzic.c                  |    2 +-
 arch/arm/plat-omap/include/plat/irqs.h    |    4 ----
 arch/arm/plat-s3c24xx/irq.c               |    2 +-
 10 files changed, 6 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 15cb035..febe495 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,7 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
-extern void init_FIQ(int);
+extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, int);
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 29b93b8..bd369c5 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -128,7 +128,7 @@ EXPORT_SYMBOL(__get_fiq_regs);	/* defined in fiqasm.S */
 EXPORT_SYMBOL(claim_fiq);
 EXPORT_SYMBOL(release_fiq);
 
-void __init init_FIQ(int start)
+void __init init_FIQ(void)
 {
 	no_fiq_insn = *(unsigned long *)0xffff001c;
 }
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index f27ead1..2536543 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -42,9 +42,4 @@ extern void iomd_mask_fiq(int fiq);
 extern void iomd_unmask_fiq(int fiq);
 #endif
 
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START		64
-
 #define NR_IRQS			128
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index a4221b3..07770c8 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -152,6 +152,6 @@ void __init rpc_init_irq(void)
 		}
 	}
 
-	init_FIQ(FIQ_START);
+	init_FIQ();
 }
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index b7a9f4d..7d66d41 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -209,7 +209,4 @@
 #define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
 #endif
 
-/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
-#define FIQ_START		IRQ_EINT0
-
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index cbd55c3..19701ec 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -218,7 +218,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
 
 #ifdef CONFIG_FIQ
 	/* Initialize FIQ */
-	init_FIQ(FIQ_START);
+	init_FIQ();
 #endif
 
 	printk(KERN_INFO "MXC IRQ initialized\n");
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index d73f5e8..2ec942f 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -13,8 +13,6 @@
 
 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
-/* all normal IRQs can be FIQs */
-#define FIQ_START	0
 /* switch between IRQ and FIQ */
 extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
 
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 3ed1adb..d09b573 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -193,7 +193,7 @@ void __init tzic_init_irq(void __iomem *irqbase)
 
 #ifdef CONFIG_FIQ
 	/* Initialize FIQ */
-	init_FIQ(FIQ_START);
+	init_FIQ();
 #endif
 
 	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 37bbbbb..d2b91e3c 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -446,8 +446,4 @@
 
 #include <mach/hardware.h>
 
-#ifdef CONFIG_FIQ
-#define FIQ_START		1024
-#endif
-
 #endif
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index e4e9567..e0de92a 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -533,7 +533,7 @@ void __init s3c24xx_init_irq(void)
 	int i;
 
 #ifdef CONFIG_FIQ
-	init_FIQ(FIQ_START);
+	init_FIQ();
 #endif
 
 	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:37 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:37 -0700
Subject: [PATCH 7/9] ARM: FIQ: Should include asm/mach/irq.h
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-7-git-send-email-anton.vorontsov@linaro.org>

The patch fixes the following sparse warnings:

  CHECK   arch/arm/kernel/fiq.c
arch/arm/kernel/fiq.c:71:6: warning: symbol 'show_fiq_list' was not declared. Should it be static?
arch/arm/kernel/fiq.c:129:13: warning: symbol 'init_FIQ' was not declared. Should it be static?

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/kernel/fiq.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index bd369c5..7be2e74 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -46,6 +46,7 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/traps.h>
+#include <asm/mach/irq.h>
 
 static unsigned long no_fiq_insn;
 
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:38 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:38 -0700
Subject: [PATCH 8/9] ARM: FIQ: Implement !CONFIG_FIQ stubs
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-8-git-send-email-anton.vorontsov@linaro.org>

Simply removes ugly #ifdefs from C code.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/include/asm/mach/irq.h |    5 +++++
 arch/arm/kernel/irq.c           |    2 --
 arch/arm/plat-mxc/avic.c        |    2 --
 arch/arm/plat-mxc/tzic.c        |    2 --
 arch/arm/plat-s3c24xx/irq.c     |    2 --
 5 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index febe495..420d211 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,8 +17,13 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
+#ifdef CONFIG_FIQ
 extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, int);
+#else
+static inline void init_FIQ(void) {}
+static inline int show_fiq_list(struct seq_file *p, int prec) { return 0; }
+#endif
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 extern void (*handle_arch_irq)(struct pt_regs *);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 16cedb4..8013ad9 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -44,9 +44,7 @@ unsigned long irq_err_count;
 
 int arch_show_interrupts(struct seq_file *p, int prec)
 {
-#ifdef CONFIG_FIQ
 	show_fiq_list(p, prec);
-#endif
 #ifdef CONFIG_SMP
 	show_ipi_list(p, prec);
 #endif
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 19701ec..426980c 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -216,10 +216,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
 	for (i = 0; i < 8; i++)
 		__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-#ifdef CONFIG_FIQ
 	/* Initialize FIQ */
 	init_FIQ();
-#endif
 
 	printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index d09b573..8a5a633 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -191,10 +191,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
 	for (i = 0; i < 4; i++, irq_base += 32)
 		tzic_init_gc(i, irq_base);
 
-#ifdef CONFIG_FIQ
 	/* Initialize FIQ */
 	init_FIQ();
-#endif
 
 	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index e0de92a..531d6a4 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -532,9 +532,7 @@ void __init s3c24xx_init_irq(void)
 	int irqno;
 	int i;
 
-#ifdef CONFIG_FIQ
 	init_FIQ();
-#endif
 
 	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
 
-- 
1.7.10.4



From anton.vorontsov at linaro.org  Sun Aug  5 19:03:39 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sun,  5 Aug 2012 16:03:39 -0700
Subject: [PATCH 9/9] ARM: FIQ: Make show_fiq_list() return void
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <1344207819-3415-9-git-send-email-anton.vorontsov@linaro.org>

The return value is never checked, so we can turn show_fiq_list() into
returning void.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/include/asm/mach/irq.h |    4 ++--
 arch/arm/kernel/fiq.c           |    4 +---
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 420d211..8be5ba9 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -19,10 +19,10 @@ struct seq_file;
  */
 #ifdef CONFIG_FIQ
 extern void init_FIQ(void);
-extern int show_fiq_list(struct seq_file *, int);
+extern void show_fiq_list(struct seq_file *, int);
 #else
 static inline void init_FIQ(void) {}
-static inline int show_fiq_list(struct seq_file *p, int prec) { return 0; }
+static inline void show_fiq_list(struct seq_file *p, int prec) {}
 #endif
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 7be2e74..9bf3a60 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -69,13 +69,11 @@ static struct fiq_handler default_owner = {
 
 static struct fiq_handler *current_fiq = &default_owner;
 
-int show_fiq_list(struct seq_file *p, int prec)
+void show_fiq_list(struct seq_file *p, int prec)
 {
 	if (current_fiq != &default_owner)
 		seq_printf(p, "%*s:              %s\n", prec, "FIQ",
 			current_fiq->name);
-
-	return 0;
 }
 
 void set_fiq_handler(void *start, unsigned int length)
-- 
1.7.10.4



From nicolas.pitre at linaro.org  Sun Aug  5 22:06:30 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 5 Aug 2012 22:06:30 -0400 (EDT)
Subject: [PATCH 02/22] ARM: use late patch framework for phys-virt patching
In-Reply-To: <501E7D41.8070303@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-3-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040138560.5231@xanadu.home> <501E7D41.8070303@ti.com>
Message-ID: <alpine.LFD.2.02.1208052153540.5231@xanadu.home>

On Sun, 5 Aug 2012, Cyril Chemparathy wrote:

> Hi Nicolas,
> 
> On 8/4/2012 2:15 AM, Nicolas Pitre wrote:
> > On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
> > 
> > > This patch replaces the original physical offset patching implementation
> > > with one that uses the newly added patching framework.  In the process, we
> > > now
> > > unconditionally initialize the __pv_phys_offset and __pv_offset globals in
> > > the
> > > head.S code.
> > 
> > Why unconditionally initializing those?  There is no reason for that.
> > 
> 
> We could keep this conditional on LPAE, but do you see any specific need for
> keeping it conditional?

This has nothing to do with LPAe.  This is about 
CONFIG_ARM_PATCH_PHYS_VIRT only.  If not selected, those global 
vaariables have no need to exist.

> > Comments below.
> > 
> > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > > index 835898e..d165896 100644
> > > --- a/arch/arm/kernel/head.S
> > > +++ b/arch/arm/kernel/head.S
> > [...]
> > >   	.data
> > >   	.globl	__pv_phys_offset
> > >   	.type	__pv_phys_offset, %object
> > >   __pv_phys_offset:
> > >   	.long	0
> > >   	.size	__pv_phys_offset, . - __pv_phys_offset
> > > +
> > > +	.globl	__pv_offset
> > > +	.type	__pv_offset, %object
> > >   __pv_offset:
> > >   	.long	0
> > > -#endif
> > > +	.size	__pv_offset, . - __pv_offset
> > 
> > Please move those to C code.  They aren't of much use in this file
> > anymore.  This will allow you to use pphys_addr_t for them as well in
> > your subsequent patch. And more importantly get rid of that ugly
> > pv_offset_high that you introduced iin another patch.
> > 
> 
> Moving it to C-code caused problems because these get filled in prior to BSS
> being cleared.
> 
> We could potentially have this initialized in C with a mystery dummy value to
> prevent it from landing in BSS.  Would that be acceptable?

Just initialize them explicitly to zero.  They will end up in .ddata 
section.
> 
> > > index df5e897..39f8fce 100644
> > > --- a/arch/arm/kernel/module.c
> > > +++ b/arch/arm/kernel/module.c
> > > @@ -317,11 +317,6 @@ int module_finalize(const Elf32_Ehdr *hdr, const
> > > Elf_Shdr *sechdrs,
> > >   					         maps[i].txt_sec->sh_addr,
> > >   					         maps[i].txt_sec->sh_size);
> > >   #endif
> > > -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> > > -	s = find_mod_section(hdr, sechdrs, ".pv_table");
> > > -	if (s)
> > > -		fixup_pv_table((void *)s->sh_addr, s->sh_size);
> > > -#endif
> > >   	s = find_mod_section(hdr, sechdrs, ".patch.table");
> > >   	if (s)
> > >   		patch_kernel((void *)s->sh_addr, s->sh_size);
> > 
> > The patch_kernel code and its invokation should still be conditional on
> > CONFIG_ARM_PATCH_PHYS_VIRT.  This ability may still be configured out
> > irrespective of the implementation used.
> > 
> 
> Maybe CONFIG_ARM_PATCH_PHYS_VIRT is not quite appropriate if this is used to
> patch up other things in addition to phys-virt stuff?

Maybe, but at the moment this is not the case.

> I could have this dependent on CONFIG_ARM_INIT_PATCH (or whatever nomenclature
> we chose for this) and have CONFIG_ARM_PATCH_PHYS_VIRT depend on it.

Let's cross that bridge in time.

FWIW, I don't like "init patch" much.  I feel like the "runtime" 
qualifier more pricisely describe this code than "init".


Nicolas


From shawn.guo at linaro.org  Sun Aug  5 22:06:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 10:06:58 +0800
Subject: [PATCH 0/4] Remove Genesi Efika MX support
In-Reply-To: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
References: <1343843371-14143-1-git-send-email-matt@genesi-usa.com>
Message-ID: <20120806020656.GA18471@S2101-09.ap.freescale.net>

On Wed, Aug 01, 2012 at 12:49:27PM -0500, Matt Sealey wrote:
> In an effort to start afresh we are removing the "legacy" Efika MX support
> from the tree in this patch series so as to break ties with any non-device-tree
> code and minimize the possibility that there are two ways to build for our
> boards.
> 
> Patches to support the board again with FDT (along with a matching U-Boot)
> are not ready for submission, but that doesn't block *this* submission. The
> number of users of 3.5 kernels on Genesi platforms is generally thought of
> as zero and no significant work or support has been committed to the platform
> in a long time. In our opinion, all efforts by external developers wishing to
> run modern kernels on Genesi Efika MX boards should be directed at device tree
> support for the MX51 platforms.
> 
> Matt Sealey (4):
>   efikamx: remove support for Genesi Efika MX from the build
>   efikamx: remove Genesi Efika MX from the i.MX v6/v7 defconfig
>   efikamx: remove Genesi Efika MX platform files from the tree
>   efikamx: remove Efika MX-specific CHRGVBUS hack from the USB driver
> 
>  arch/arm/configs/imx_v6_v7_defconfig  |    2 -
>  arch/arm/mach-imx/Kconfig             |   26 --
>  arch/arm/mach-imx/Makefile            |    3 -
>  arch/arm/mach-imx/efika.h             |   10 -
>  arch/arm/mach-imx/mach-mx51_efikamx.c |  300 ----------------
>  arch/arm/mach-imx/mach-mx51_efikasb.c |  296 ---------------
>  arch/arm/mach-imx/mx51_efika.c        |  632 ---------------------------------
>  drivers/usb/host/ehci-mxc.c           |   20 --
>  8 files changed, 1289 deletions(-)
>  delete mode 100644 arch/arm/mach-imx/efika.h
>  delete mode 100644 arch/arm/mach-imx/mach-mx51_efikamx.c
>  delete mode 100644 arch/arm/mach-imx/mach-mx51_efikasb.c
>  delete mode 100644 arch/arm/mach-imx/mx51_efika.c
> 
I set up a branch imx/rm-boards and queued the series there.  I expect
I will have some patches removing imx53 board files to be queued there
for 3.7 too.

-- 
Regards,
Shawn



From nicolas.pitre at linaro.org  Sun Aug  5 22:19:04 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 5 Aug 2012 22:19:04 -0400 (EDT)
Subject: [PATCH 04/22] ARM: LPAE: support 64-bit virt/phys patching
In-Reply-To: <501E815D.1050707@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-5-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040226060.5231@xanadu.home> <501E815D.1050707@ti.com>
Message-ID: <alpine.LFD.2.02.1208052207040.5231@xanadu.home>

On Sun, 5 Aug 2012, Cyril Chemparathy wrote:

> Hi Nicolas,
> 
> On 8/4/2012 2:49 AM, Nicolas Pitre wrote:
> > On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
> > 
> > > This patch adds support for 64-bit physical addresses in virt_to_phys
> > > patching.  This does not do real 64-bit add/sub, but instead patches in
> > > the
> > > upper 32-bits of the phys_offset directly into the output of virt_to_phys.
> > 
> > You should explain _why_ you do not a real aadd/sub.  I did deduce it
> > but that might not be obvious to everyone.  Also this subtlety should be
> > commented in the code as well.
> > 
> 
> We could not do an ADDS + ADC here because the carry is not guaranteed to be
> retained and passed into the ADC.  This is because the compiler is free to
> insert all kinds of stuff between the two non-volatile asm blocks.
> 
> Is there another subtlety here that I have missed out on entirely?

The high bits for the valid physical memory address range for which 
virt_to_phys and phys_to_virt can be used are always the same.  
Therefore no aadition at all is needed, fake or real.  Only providing 
those bits in the top word for the value returned by virt_to_phys is 
needed.

> > > In addition to adding 64-bit support, this patch also adds a
> > > set_phys_offset()
> > > helper that is needed on architectures that need to modify PHYS_OFFSET
> > > during
> > > initialization.
> > > 
> > > Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> > > ---
> > >   arch/arm/include/asm/memory.h |   22 +++++++++++++++-------
> > >   arch/arm/kernel/head.S        |    6 ++++++
> > >   arch/arm/kernel/setup.c       |   14 ++++++++++++++
> > >   3 files changed, 35 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> > > index 4a0108f..110495c 100644
> > > --- a/arch/arm/include/asm/memory.h
> > > +++ b/arch/arm/include/asm/memory.h
> > > @@ -153,23 +153,31 @@
> > >   #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> > > 
> > >   extern unsigned long __pv_phys_offset;
> > > -#define PHYS_OFFSET __pv_phys_offset
> > > -
> > > +extern unsigned long __pv_phys_offset_high;
> > 
> > As mentioned previously, this is just too ugly.  Please make
> > __pv_phys_offset into a phys_addr_t instead and mask the low/high parts
> > as needed in __virt_to_phys().
> > 
> 
> Maybe u64 instead of phys_addr_t to keep the sizing non-variable?

No.  When not using LPAE, we don't have to pay the price of a u64 value.  
That's why the phys_addr_t type is conditionally defined.  You already 
do  extra processing in virt_to_phys when sizeof(phys_addr_t) > 4 which 
is perfect for dealing with this issue.


Nicolas


From shawn.guo at linaro.org  Sun Aug  5 22:29:17 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 10:29:17 +0800
Subject: [PATCH 10/10] ARM: mx28: Add SPI pinmux into imx28.dtsi
In-Reply-To: <1344007575-11448-11-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
 <1344007575-11448-11-git-send-email-marex@denx.de>
Message-ID: <20120806022915.GB18471@S2101-09.ap.freescale.net>

On Fri, Aug 03, 2012 at 05:26:15PM +0200, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Attila Kinali <attila at kinali.ch>
> Cc: Chris Ball <cjb at laptop.org>
> CC: Dong Aisheng <b29396 at freescale.com>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linux ARM kernel <linux-arm-kernel at lists.infradead.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> CC: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx28.dtsi |   39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index badc76a..4a0f12c 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -507,6 +507,45 @@
>  					fsl,voltage = <1>;
>  					fsl,pull-up = <0>;
>  				};
> +
> +				spi0_pins_a: spi0 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids =
> +						<0x2000 0x2010 0x2020 0x2030
> +						0x2040 0x2050 0x2060 0x2070
> +						0x2080 0x2090 0x20a0>;

Please follow the new format, one id per line with a comment afterward.

> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi1_pins_a: spi1 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids =
> +						<0x20c0 0x20d0 0x20e0 0x20f0>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi2_pins_a: spi2 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids =
> +						<0x2100 0x2110 0x2120
> +						0x2130 0x2140 0x2150>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi3_pins_a: spi3 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids =
> +						<0x2180 0x2190 0x21a0 0x21b0>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};

I do not accept patch adding pinctrl settings alone.  Instead, I want
them to be added together with the users (board dts).  That said, we
do not want to enumerate all the possible pinctrl settings but just
the ones being used.

>  			};
>  
>  			digctl at 8001c000 {
> -- 
> 1.7.10.4
> 

-- 
Regards,
Shawn



From nicolas.pitre at linaro.org  Sun Aug  5 22:35:33 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 5 Aug 2012 22:35:33 -0400 (EDT)
Subject: [PATCH 09/22] ARM: LPAE: use 64-bit pgd physical address in
 switch_mm()
In-Reply-To: <501E8367.8070907@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-10-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040259200.5231@xanadu.home> <501E8367.8070907@ti.com>
Message-ID: <alpine.LFD.2.02.1208052220060.5231@xanadu.home>

On Sun, 5 Aug 2012, Cyril Chemparathy wrote:

> On 8/4/2012 3:04 AM, Nicolas Pitre wrote:
> > On Tue, 31 Jul 2012, Cyril Chemparathy wrote:
> > 
> > > This patch modifies the switch_mm() processor functions to use 64-bit
> > > addresses.  We use u64 instead of phys_addr_t, in order to avoid having
> > > config
> > > dependent register usage when calling into switch_mm assembly code.
> > > 
> > > The changes in this patch are primarily adjustments for registers used for
> > > arguments to switch_mm.  The few processor definitions that did use the
> > > second
> > > argument have been modified accordingly.
> > > 
> > > Arguments and calling conventions aside, this patch should be a no-op on
> > > v6
> > > and non-LPAE v7 processors.
> > 
> > NAK.
> > 
> > You just broke all big endian targets, LPAE or not.
> > 
> 
> Indeed.  Thanks.
> 
> Would C-land word swappery on BE do?  Any other ideas on the best approach to
> this?

First, don't use a u64 unconditionally. A phys_addr_t is best for the 
same arguments as before.  Since this is equivalent to a u64 only when 
LPAE is defined, you then only have to care about endian issues in 
proc-v7-3level.S.  And in there you can deal with the issue with 
register aliases just as it is done in lib/div64.S.


Nicolas


From shawn.guo at linaro.org  Sun Aug  5 22:37:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 10:37:45 +0800
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <1344007721-11595-3-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-3-git-send-email-marex@denx.de>
Message-ID: <20120806023743.GC18471@S2101-09.ap.freescale.net>

On Fri, Aug 03, 2012 at 05:28:40PM +0200, Marek Vasut wrote:
> --- /dev/null
> +++ b/drivers/staging/iio/adc/mxs-lradc.c

<snip>

> +#include <mach/mxs.h>
> +#include <mach/common.h>
> +
Why do you need these two mach headers?

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Sun Aug  5 22:39:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 10:39:09 +0800
Subject: [PATCH 3/3] IIO: arm: Add LRADC to i.MX28 dts
In-Reply-To: <1344007721-11595-4-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-4-git-send-email-marex@denx.de>
Message-ID: <20120806023907.GD18471@S2101-09.ap.freescale.net>

On Fri, Aug 03, 2012 at 05:28:41PM +0200, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Jonathan Cameron <jic23 at kernel.org>
> Cc: Juergen Beisert <jbe at pengutronix.de>
> Cc: Lars-Peter Clausen <lars at metafoo.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Wolfgang Denk <wd at denx.de>
> ---
>  arch/arm/boot/dts/imx28.dtsi |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 4a0f12c..91752d2 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -677,7 +677,10 @@
>  			};
>  
>  			lradc at 80050000 {
> +				compatible = "fsl,imx28-lradc";
>  				reg = <0x80050000 2000>;
> +				interrupts = <10 14 15 16 17 18 19
> +						20 21 22 23 24 25>;

Is there a binding doc for this?

Regards,
Shawn

>  				status = "disabled";
>  			};
>  
> -- 
> 1.7.10.4
> 



From robherring2 at gmail.com  Sun Aug  5 22:50:32 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 05 Aug 2012 21:50:32 -0500
Subject: [PATCH v2 2/4] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <501F30F8.1040105@gmail.com>

On 08/05/2012 10:05 AM, Shawn Guo wrote:
> With a lot of devices booting from device tree nowadays, it requires
> that OPP table can be initialized from device tree.  The patch adds
> a helper function of_init_opp_table together with a binding doc for
> that purpose.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  Documentation/devicetree/bindings/power/opp.txt |   25 +++++++++
>  drivers/base/power/opp.c                        |   65 +++++++++++++++++++++++
>  include/linux/opp.h                             |    8 +++
>  3 files changed, 98 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/power/opp.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt
> new file mode 100644
> index 0000000..2238520
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/opp.txt
> @@ -0,0 +1,25 @@
> +* Generic OPP Interface
> +
> +SoCs have a standard set of tuples consisting of frequency and
> +voltage pairs that the device will support per voltage domain. These
> +are called Operating Performance Points or OPPs.
> +
> +Properties:
> +- operating-points: An array of 3-tuples items, and each item consists

3 tuples?

> +  of frequency and voltage like <freq-kHz vol-uV>.
> +	freq: clock frequency in kHz
> +	vol: voltage in microvolt

Although maybe 3 fields would be good for a flags field? I'm concerned
it's a pretty generic name and not very future proof. What about
transition times? Not sure how you would represent that as it probably
depends on which points you are changing between rather than a property
of the opp.

I'm not saying we have to address that now, but just have some path in
the future.

> +
> +Examples:
> +
> +cpu at 0 {
> +	compatible = "arm,cortex-a9";
> +	reg = <0>;
> +	next-level-cache = <&L2>;
> +	operating-points = <
> +		/* kHz    uV */
> +		792000  1100000
> +		396000  950000
> +		198000  850000
> +	>;
> +};
> diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
> index ac993ea..1bf1be8 100644
> --- a/drivers/base/power/opp.c
> +++ b/drivers/base/power/opp.c
> @@ -22,6 +22,7 @@
>  #include <linux/rculist.h>
>  #include <linux/rcupdate.h>
>  #include <linux/opp.h>
> +#include <linux/of.h>
>  
>  /*
>   * Internal data structure organization with the OPP layer library is as
> @@ -674,3 +675,67 @@ struct srcu_notifier_head *opp_get_notifier(struct device *dev)
>  
>  	return &dev_opp->head;
>  }
> +
> +#ifdef CONFIG_OF
> +/**
> + * of_init_opp_table() - Initialize opp table from device tree
> + * @dev:	device pointer used to lookup device OPPs.
> + *
> + * Register the initial OPP table with the OPP library for given device.
> + */
> +int of_init_opp_table(struct device *dev)
> +{
> +	struct device_node *np = dev->of_node;
> +	const char *propname = "operating-points";
> +	const struct property *pp;
> +	u32 *opp;
> +	int ret, i, nr;
> +
> +	pp = of_find_property(np, propname, NULL);
> +	if (!pp) {
> +		dev_err(dev, "%s: Unable to find property", __func__);
> +		return -ENODEV;
> +	}
> +
> +	opp = kzalloc(pp->length, GFP_KERNEL);
> +	if (!opp) {
> +		dev_err(dev, "%s: Unable to allocate array\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +	nr = pp->length / sizeof(u32);
> +	ret = of_property_read_u32_array(np, propname, opp, nr);
> +	if (ret) {
> +		dev_err(dev, "%s: Unable to read OPPs\n", __func__);
> +		goto out;
> +	}
> +
> +	if (nr % 2) {
> +		dev_err(dev, "%s: Invalid OPP list\n", __func__);
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	nr /= 2;
> +	for (i = 0; i < nr; i++) {
> +		/*
> +		 * Each OPP is a set of tuples consisting of frequency and
> +		 * voltage like <freq-kHz vol-uV>.
> +		 */
> +		u32 *val = opp + i * 2;
> +
> +		val[0] *= 1000;
> +		ret = opp_add(dev, val[0], val[1]);
> +		if (ret) {
> +			dev_warn(dev, "%s: Failed to add OPP %d: %d\n",
> +				 __func__, val[0], ret);
> +			continue;
> +		}
> +	}

I think this whole function can be written more concisely. Just iterate
over the property and avoid the intermediate array allocation.

Rob



From shawn.guo at linaro.org  Sun Aug  5 22:58:08 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 10:58:08 +0800
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <1344186258-30841-1-git-send-email-festevam@gmail.com>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
Message-ID: <20120806025806.GA22302@S2101-09.ap.freescale.net>

On Sun, Aug 05, 2012 at 02:04:18PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Enable USB host.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/configs/mxs_defconfig |   14 +++++++++++++-
>  1 files changed, 13 insertions(+), 1 deletions(-)
> 
I guess you did not run savedefconfig.  We do not need all those
options explicitly added there.

Regards,
Shawn

> diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
> index ccdb635..73842f9 100644
> --- a/arch/arm/configs/mxs_defconfig
> +++ b/arch/arm/configs/mxs_defconfig
> @@ -95,7 +95,7 @@ CONFIG_GPIO_SYSFS=y
>  # CONFIG_MFD_SUPPORT is not set
>  CONFIG_DISPLAY_SUPPORT=m
>  # CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> +CONFIG_USB_SUPPORT=y
>  CONFIG_SOUND=y
>  CONFIG_SND=y
>  CONFIG_SND_TIMER=y
> @@ -110,6 +110,18 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
>  CONFIG_SND_SOC_SGTL5000=y
>  CONFIG_REGULATOR=y
>  CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_USB_COMMON=y
> +CONFIG_USB_ARCH_HAS_HCD=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_ROOT_HUB_TT=y
> +CONFIG_USB_EHCI_TT_NEWSCHED=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_OTG_UTILS=y
> +CONFIG_USB_MXS_PHY=y
> +CONFIG_USB_CHIPIDEA=y
> +CONFIG_USB_CHIPIDEA_HOST=y
> +CONFIG_SCSI=y
> +CONFIG_BLK_DEV_SD=y
>  CONFIG_MMC=y
>  CONFIG_MMC_MXS=y
>  CONFIG_RTC_CLASS=y
> -- 
> 1.7.1
> 



From shawn.guo at linaro.org  Sun Aug  5 23:00:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 11:00:16 +0800
Subject: [PATCH] clk: mxs: Register USB clocks for mx23
In-Reply-To: <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>
References: <1340148392-9847-1-git-send-email-festevam@gmail.com>
 <20120620143830.GF2253@S2101-09.ap.freescale.net>
 <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>
Message-ID: <20120806030014.GB22302@S2101-09.ap.freescale.net>

On Sun, Aug 05, 2012 at 02:08:07PM -0300, Fabio Estevam wrote:
> On Wed, Jun 20, 2012 at 11:38 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> ...
> >> +     clk_register_clkdev(clks[usb_pwr], NULL, "8007c000.usbphy");
> >> +     clk_register_clkdev(clks[usb], NULL, "80080000.usb");
> >
> > It depends on the node name in device tree.  I would defer this
> > a little bit to have the node name in dts settled down first.
> 
> Now that the mxs usb driver is in mainline, could this patch be applied?
> 
Probably, no, as I plan to freeze the addition to clkdev lookup table
and replace it with DT clock lookup.

-- 
Regards,
Shawn



From festevam at gmail.com  Sun Aug  5 23:14:52 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 00:14:52 -0300
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <20120806025806.GA22302@S2101-09.ap.freescale.net>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
 <20120806025806.GA22302@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>

On Sun, Aug 5, 2012 at 11:58 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> I guess you did not run savedefconfig.  We do not need all those
> options explicitly added there.

No, I have not run savedefconfig. What is the correct way to use it?

Regards,

Fabio Estevam


From shawn.guo at linaro.org  Sun Aug  5 23:19:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 11:19:19 +0800
Subject: [PATCH v2 2/4] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <501F30F8.1040105@gmail.com>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>
 <501F30F8.1040105@gmail.com>
Message-ID: <20120806031916.GC22302@S2101-09.ap.freescale.net>

On Sun, Aug 05, 2012 at 09:50:32PM -0500, Rob Herring wrote:
> > +Properties:
> > +- operating-points: An array of 3-tuples items, and each item consists
> 
> 3 tuples?
> 
It's the case of v1, and I forgot updating it.  Thanks for spotting it.

> > +  of frequency and voltage like <freq-kHz vol-uV>.
> > +	freq: clock frequency in kHz
> > +	vol: voltage in microvolt
> 
> Although maybe 3 fields would be good for a flags field? I'm concerned
> it's a pretty generic name and not very future proof. What about
> transition times? Not sure how you would represent that as it probably
> depends on which points you are changing between rather than a property
> of the opp.
> 
This is a binding for OPP, which does not define transition times.

As for cpufreq, we only need to represent a possible maximum transition
latency.  The driver will ask regulator subsystem for voltage latency,
while the clock latency is defined in DT. 

> I think this whole function can be written more concisely. Just iterate
> over the property and avoid the intermediate array allocation.
> 
I'm not sure about that, since directly iterating over the property
means we have to take care of all these sanity checks done in API
of_property_read_u32_array().

-- 
Regards,
Shawn



From marex at denx.de  Sun Aug  5 23:53:50 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 6 Aug 2012 05:53:50 +0200
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <20120806023743.GC18471@S2101-09.ap.freescale.net>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-3-git-send-email-marex@denx.de>
 <20120806023743.GC18471@S2101-09.ap.freescale.net>
Message-ID: <201208060553.50398.marex@denx.de>

Dear Shawn Guo,

> On Fri, Aug 03, 2012 at 05:28:40PM +0200, Marek Vasut wrote:
> > --- /dev/null
> > +++ b/drivers/staging/iio/adc/mxs-lradc.c
> 
> <snip>
> 
> > +#include <mach/mxs.h>
> > +#include <mach/common.h>
> > +
> 
> Why do you need these two mach headers?

Might be just some remnant ... any further comments please?

Best regards,
Marek Vasut


From marek.vasut at gmail.com  Sun Aug  5 23:55:08 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 6 Aug 2012 05:55:08 +0200
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
 <20120806025806.GA22302@S2101-09.ap.freescale.net>
 <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>
Message-ID: <201208060555.08447.marex@denx.de>

Dear Fabio Estevam,

> On Sun, Aug 5, 2012 at 11:58 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > I guess you did not run savedefconfig.  We do not need all those
> > options explicitly added there.
> 
> No, I have not run savedefconfig. What is the correct way to use it?

make mxs_config
<edit>
make savedefconfig

I'd guess ...

> Regards,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From festevam at gmail.com  Mon Aug  6 00:03:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 01:03:55 -0300
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <201208060555.08447.marex@denx.de>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
 <20120806025806.GA22302@S2101-09.ap.freescale.net>
 <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>
 <201208060555.08447.marex@denx.de>
Message-ID: <CAOMZO5BBXwOME2MadkLwf=xJnTQ_djjXbNMkjA9yau1q4x_zgA@mail.gmail.com>

On Mon, Aug 6, 2012 at 12:55 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dear Fabio Estevam,
>
>> On Sun, Aug 5, 2012 at 11:58 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> > I guess you did not run savedefconfig.  We do not need all those
>> > options explicitly added there.
>>
>> No, I have not run savedefconfig. What is the correct way to use it?
>
> make mxs_config
> <edit>
> make savedefconfig
>
> I'd guess ...

So the generating diff would be:
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..a9556ef 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -95,7 +95,7 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -110,6 +110,13 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
-- 
1.7.1

Is this OK?

Regards,

Fabio Estevam


From B04825 at freescale.com  Mon Aug  6 00:06:03 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Mon, 6 Aug 2012 04:06:03 +0000
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <201208060555.08447.marex@denx.de>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
 <20120806025806.GA22302@S2101-09.ap.freescale.net>
 <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>
 <201208060555.08447.marex@denx.de>
Message-ID: <CAOZdJXXmr4hxEkR2ZdR6JwQduC691hGWbNWwAFqUs8H2yinbZg@mail.gmail.com>

On Sun, Aug 5, 2012 at 10:55 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>
> make mxs_config
> <edit>
> make savedefconfig

I also hand-diff the two defconfig files so that I only pick up the
relevant changes.

-- 
Timur Tabi
Linux kernel developer at Freescale


From B04825 at freescale.com  Mon Aug  6 00:08:09 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Mon, 6 Aug 2012 04:08:09 +0000
Subject: [PATCH] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <CAOMZO5BBXwOME2MadkLwf=xJnTQ_djjXbNMkjA9yau1q4x_zgA@mail.gmail.com>
References: <1344186258-30841-1-git-send-email-festevam@gmail.com>
 <20120806025806.GA22302@S2101-09.ap.freescale.net>
 <CAOMZO5CevtbEdch5v9jt5Gyis8o6C1-Vrm1p=289Gpx4zd_wxQ@mail.gmail.com>
 <201208060555.08447.marex@denx.de>
 <CAOMZO5BBXwOME2MadkLwf=xJnTQ_djjXbNMkjA9yau1q4x_zgA@mail.gmail.com>
Message-ID: <CAOZdJXViJCzaD8fHD87xmg3QHfdSmGnn4Oq444uiktjrsuv=8w@mail.gmail.com>

On Sun, Aug 5, 2012 at 11:03 PM, Fabio Estevam <festevam at gmail.com> wrote:

> +CONFIG_SCSI=y
> +CONFIG_BLK_DEV_SD=y

I'm not sure about these two.

Try doing this:

make mxs_config
make savedefconfig

And then compare the two defconfigs.  It will tell you which changes to ignore.

-- 
Timur Tabi
Linux kernel developer at Freescale


From robherring2 at gmail.com  Mon Aug  6 00:43:04 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 05 Aug 2012 23:43:04 -0500
Subject: [PATCH v2 2/4] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <20120806031916.GC22302@S2101-09.ap.freescale.net>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>
 <501F30F8.1040105@gmail.com>
 <20120806031916.GC22302@S2101-09.ap.freescale.net>
Message-ID: <501F4B58.4020308@gmail.com>

On 08/05/2012 10:19 PM, Shawn Guo wrote:
> On Sun, Aug 05, 2012 at 09:50:32PM -0500, Rob Herring wrote:
>>> +Properties:
>>> +- operating-points: An array of 3-tuples items, and each item consists
>>
>> 3 tuples?
>>
> It's the case of v1, and I forgot updating it.  Thanks for spotting it.
> 
>>> +  of frequency and voltage like <freq-kHz vol-uV>.
>>> +	freq: clock frequency in kHz
>>> +	vol: voltage in microvolt
>>
>> Although maybe 3 fields would be good for a flags field? I'm concerned
>> it's a pretty generic name and not very future proof. What about
>> transition times? Not sure how you would represent that as it probably
>> depends on which points you are changing between rather than a property
>> of the opp.
>>
> This is a binding for OPP, which does not define transition times.
> 
> As for cpufreq, we only need to represent a possible maximum transition
> latency.  The driver will ask regulator subsystem for voltage latency,
> while the clock latency is defined in DT. 
> 
>> I think this whole function can be written more concisely. Just iterate
>> over the property and avoid the intermediate array allocation.
>>
> I'm not sure about that, since directly iterating over the property
> means we have to take care of all these sanity checks done in API
> of_property_read_u32_array().
> 

This won't work?:

of_property_for_each_u32(...) {
	if (i & 0x1) {
		volt = val;
		ret = opp_add(dev, freq, volt);
		if (ret)
			...
	} else
		freq = val * 1000;

	i++;
}

Rob


From festevam at gmail.com  Mon Aug  6 00:43:19 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon,  6 Aug 2012 01:43:19 -0300
Subject: [PATCH v2] ARM: mxs_defconfig: Enable USB host
Message-ID: <1344228199-16231-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Enable USB host.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Use savedefconfig to generate a minimal config
 arch/arm/configs/mxs_defconfig |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..e3487e4 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -95,7 +95,6 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_MFD_SUPPORT is not set
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
@@ -110,6 +109,13 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
-- 
1.7.1



From shawn.guo at linaro.org  Mon Aug  6 01:23:02 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 13:23:02 +0800
Subject: [PATCH v2 2/4] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <501F4B58.4020308@gmail.com>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-3-git-send-email-shawn.guo@linaro.org>
 <501F30F8.1040105@gmail.com>
 <20120806031916.GC22302@S2101-09.ap.freescale.net>
 <501F4B58.4020308@gmail.com>
Message-ID: <20120806052300.GD22302@S2101-09.ap.freescale.net>

On Sun, Aug 05, 2012 at 11:43:04PM -0500, Rob Herring wrote:
> On 08/05/2012 10:19 PM, Shawn Guo wrote:
> > On Sun, Aug 05, 2012 at 09:50:32PM -0500, Rob Herring wrote:
> >> I think this whole function can be written more concisely. Just iterate
> >> over the property and avoid the intermediate array allocation.
> >>
> > I'm not sure about that, since directly iterating over the property
> > means we have to take care of all these sanity checks done in API
> > of_property_read_u32_array().
> > 
> 
> This won't work?:
> 
It should work.  But I rewrote the function like below after I find
the sanity check is simple enough to take care of it on our own.

The code does look more concise and still easy to read.

Regards,
Shawn

int of_init_opp_table(struct device *dev)
{
        const struct property *prop;
        const __be32 *val;
        int nr;

        prop = of_find_property(dev->of_node, "operating-points", NULL);
        if (!prop)
                return -ENODEV;
        if (!prop->value)
                return -ENODATA;

        /*
         * Each OPP is a set of tuples consisting of frequency and
         * voltage like <freq-kHz vol-uV>.
         */
        nr = prop->length / sizeof(u32);
        if (nr % 2) {
                dev_err(dev, "%s: Invalid OPP list\n", __func__);
                return -EINVAL;
        }

        val = prop->value;
        while (nr) {
                unsigned long freq = be32_to_cpup(val++) * 1000;
                unsigned long volt = be32_to_cpup(val++);

                if (opp_add(dev, freq, volt)) {
                        dev_warn(dev, "%s: Failed to add OPP %ld\n",
                                 __func__, freq);
                        continue;
                }
                nr -= 2;
        }

        return 0;
}



From nico at fluxnic.net  Mon Aug  6 00:32:14 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 06 Aug 2012 00:32:14 -0400 (EDT)
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120805095528.GO2626@pengutronix.de>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
Message-ID: <alpine.LFD.2.02.1208060026460.5231@xanadu.home>

On Sun, 5 Aug 2012, Uwe Kleine-K?nig wrote:

> On Fri, Aug 03, 2012 at 12:45:32PM +0100, Will Deacon wrote:
> > On Fri, Aug 03, 2012 at 10:04:52AM +0100, Uwe Kleine-K?nig wrote:
> > > Hello,
> > 
> > Hi Uwe,
> > 
> > > in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have
> > > 
> > > 	.arm
> > >  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> > >  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
> > >  THUMB( .thumb                  )       @ switch to Thumb now.
> > >  THUMB(1:                       )
> > > 
> > > as first instructions at the entry point. This is a problem for
> > > thumb2-only cpus (e.g. Cortex-M3).
> > 
> > Yup, Documentation/arm/Booting mentions this too.
> > 
> > > Up to now I commented out the first three lines for the Cortex-M3 port.
> > > What should we do about that. There are two possibilities I see:
> > > 
> > >  a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
> > >     first three lines out if it is given.
> > >  b) expect the bootloader to directly jump to the label 1.
> > > 
> > > The downside of a) is that a boot loader on a cpu that is capable to
> > > execute the tradtional instructions would need to detect if the switch
> > > to thumb is there or not and react accordingly. (In fact it needs to
> > > distringuish three cases:
> > > 
> > >  - traditional kernel
> > >  - thumb2 kernel with ARM entry
> > >  - thumb2 kernel without ARM entry
> > > 
> > > .) So I think b) is the more sensible option in the long run.
> > > 
> > > What do you think?
> > 
> > How about something like:
> > 
> > 
> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > index 835898e..9f07be2 100644
> > --- a/arch/arm/kernel/head.S
> > +++ b/arch/arm/kernel/head.S
> > @@ -86,6 +86,7 @@
> >         __HEAD
> >  ENTRY(stext)
> >  
> > + THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
> >   THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> >   THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
> >   THUMB(        .thumb                  )       @ switch to Thumb now.
> Great idea, but it doesn't work as suggested. My compiler already barfs
> on the .arm above:

Let's stop splitting hairs.

A Cortex-M kernel simply won't run on anything else.  It certainly won't 
run on ARM mode capable processors.  So in this case just make the 
kernel entry point Thumb mode only by #ifdef'ing out the .arm part.

This is good _only_ for CPUs without any ARM mode capability though.


Nicolas

From shawn.guo at linaro.org  Mon Aug  6 01:39:15 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 13:39:15 +0800
Subject: [PATCH v2] ARM: mxs_defconfig: Enable USB host
In-Reply-To: <1344228199-16231-1-git-send-email-festevam@gmail.com>
References: <1344228199-16231-1-git-send-email-festevam@gmail.com>
Message-ID: <20120806053913.GE22302@S2101-09.ap.freescale.net>

On Mon, Aug 06, 2012 at 01:43:19AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Enable USB host.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

-- 
Regards,
Shawn



From pgaikwad at nvidia.com  Mon Aug  6 02:27:38 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:38 +0530
Subject: [PATCH v4 0/6] Port Tegra to generic clk framework
Message-ID: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>

This patch set ports Tegra clock code to generic clock framework.

Depends on:
b2f4774 ARM: tegra: fix U16 divider range check
e1a8a4d ARM: tegra: turn on UART A clock at boot

Tested on Ventana and Cardhu.

v4:
 - Rebased on Tegra's for-3.7/common-clk

v3:
 - Fix Tegra20 pll clk round rate.
 - Fix Tegra30 periph clk ref count check.

v2:
 - Rebased on Tegra's for-3.6/common-clk.

Prashant Gaikwad (6):
  ARM: tegra30: Separate out clk ops and clk data
  ARM: tegra20: Separate out clk ops and clk data
  ARM: tegra: Rename tegra20 clock file
  ARM: tegra: Add clk_tegra structure and helper functions
  ARM: tegra: Port tegra to generic clock framework
  ARM: tegra: Remove duplicate code

 arch/arm/Kconfig                          |    1 +
 arch/arm/mach-tegra/Makefile              |    4 +-
 arch/arm/mach-tegra/clock.c               |  570 +------
 arch/arm/mach-tegra/clock.h               |   40 +-
 arch/arm/mach-tegra/common.c              |    1 -
 arch/arm/mach-tegra/include/mach/clk.h    |    3 +
 arch/arm/mach-tegra/tegra20_clocks.c      | 1526 +++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks.h      |   41 +
 arch/arm/mach-tegra/tegra20_clocks_data.c | 1113 +++++++++++++
 arch/arm/mach-tegra/tegra2_clocks.c       | 2484 ----------------------------
 arch/arm/mach-tegra/tegra30_clocks.c      | 2559 ++++++++++-------------------
 arch/arm/mach-tegra/tegra30_clocks.h      |   53 +
 arch/arm/mach-tegra/tegra30_clocks_data.c | 1370 +++++++++++++++
 13 files changed, 4991 insertions(+), 4774 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra20_clocks.c
 create mode 100644 arch/arm/mach-tegra/tegra20_clocks.h
 create mode 100644 arch/arm/mach-tegra/tegra20_clocks_data.c
 delete mode 100644 arch/arm/mach-tegra/tegra2_clocks.c
 create mode 100644 arch/arm/mach-tegra/tegra30_clocks.h
 create mode 100644 arch/arm/mach-tegra/tegra30_clocks_data.c

-- 
1.7.4.1



From pgaikwad at nvidia.com  Mon Aug  6 02:27:39 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:39 +0530
Subject: [PATCH v4 1/6] ARM: tegra30: Separate out clk ops and clk data
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-2-git-send-email-pgaikwad@nvidia.com>

Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/mach-tegra/Makefile              |    1 +
 arch/arm/mach-tegra/tegra30_clocks.c      | 1155 +----------------------------
 arch/arm/mach-tegra/tegra30_clocks.h      |   43 ++
 arch/arm/mach-tegra/tegra30_clocks_data.c | 1144 ++++++++++++++++++++++++++++
 4 files changed, 1210 insertions(+), 1133 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra30_clocks.h
 create mode 100644 arch/arm/mach-tegra/tegra30_clocks_data.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303..0b62a9b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f10..645ef69 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra30_clocks.c
  *
- * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -533,13 +533,13 @@ static void tegra30_clk_m_disable(struct clk *c)
 	WARN(1, "Attempting to disable main SoC clock\n");
 }
 
-static struct clk_ops tegra_clk_m_ops = {
+struct clk_ops tegra30_clk_m_ops = {
 	.init		= tegra30_clk_m_init,
 	.enable		= tegra30_clk_m_enable,
 	.disable	= tegra30_clk_m_disable,
 };
 
-static struct clk_ops tegra_clk_m_div_ops = {
+struct clk_ops tegra_clk_m_div_ops = {
 	.enable		= tegra30_clk_m_enable,
 };
 
@@ -567,7 +567,7 @@ static void tegra30_pll_ref_init(struct clk *c)
 	c->state = ON;
 }
 
-static struct clk_ops tegra_pll_ref_ops = {
+struct clk_ops tegra_pll_ref_ops = {
 	.init		= tegra30_pll_ref_init,
 	.enable		= tegra30_clk_m_enable,
 	.disable	= tegra30_clk_m_disable,
@@ -707,7 +707,7 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
 	return clk_set_rate(c->parent, rate);
 }
 
-static struct clk_ops tegra_super_ops = {
+struct clk_ops tegra30_super_ops = {
 	.init			= tegra30_super_clk_init,
 	.enable			= tegra30_super_clk_enable,
 	.disable		= tegra30_super_clk_disable,
@@ -722,7 +722,7 @@ static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra30_twd_ops = {
+struct clk_ops tegra30_twd_ops = {
 	.set_rate	= tegra30_twd_clk_set_rate,
 };
 
@@ -801,7 +801,7 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra_blink_clk_ops = {
+struct clk_ops tegra30_blink_clk_ops = {
 	.init			= &tegra30_blink_clk_init,
 	.enable			= &tegra30_blink_clk_enable,
 	.disable		= &tegra30_blink_clk_disable,
@@ -829,7 +829,6 @@ static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
 	return 0;
 }
 
-
 static void tegra30_utmi_param_configure(struct clk *c)
 {
 	u32 reg;
@@ -1100,7 +1099,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra_pll_ops = {
+struct clk_ops tegra30_pll_ops = {
 	.init			= tegra30_pll_clk_init,
 	.enable			= tegra30_pll_clk_enable,
 	.disable		= tegra30_pll_clk_disable,
@@ -1141,7 +1140,7 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return 0;
 }
 
-static struct clk_ops tegra_plld_ops = {
+struct clk_ops tegra_plld_ops = {
 	.init			= tegra30_pll_clk_init,
 	.enable			= tegra30_pll_clk_enable,
 	.disable		= tegra30_pll_clk_disable,
@@ -1258,7 +1257,7 @@ static int tegra30_plle_clk_enable(struct clk *c)
 	return tegra30_plle_configure(c, !c->set);
 }
 
-static struct clk_ops tegra_plle_ops = {
+struct clk_ops tegra30_plle_ops = {
 	.init			= tegra30_plle_clk_init,
 	.enable			= tegra30_plle_clk_enable,
 	.disable		= tegra30_plle_clk_disable,
@@ -1386,7 +1385,7 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_pll_div_ops = {
+struct clk_ops tegra30_pll_div_ops = {
 	.init			= tegra30_pll_div_clk_init,
 	.enable			= tegra30_pll_div_clk_enable,
 	.disable		= tegra30_pll_div_clk_disable,
@@ -1634,7 +1633,7 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_periph_clk_ops = {
+struct clk_ops tegra30_periph_clk_ops = {
 	.init			= &tegra30_periph_clk_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1644,7 +1643,6 @@ static struct clk_ops tegra_periph_clk_ops = {
 	.reset			= &tegra30_periph_clk_reset,
 };
 
-
 /* Periph extended clock configuration ops */
 static int
 tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
@@ -1660,7 +1658,7 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_vi_clk_ops = {
+struct clk_ops tegra_vi_clk_ops = {
 	.init			= &tegra30_periph_clk_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1686,7 +1684,7 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_nand_clk_ops = {
+struct clk_ops tegra_nand_clk_ops = {
 	.init			= &tegra30_periph_clk_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1697,7 +1695,6 @@ static struct clk_ops tegra_nand_clk_ops = {
 	.reset			= &tegra30_periph_clk_reset,
 };
 
-
 static int
 tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
@@ -1713,7 +1710,7 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_dtv_clk_ops = {
+struct clk_ops tegra_dtv_clk_ops = {
 	.init			= &tegra30_periph_clk_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1753,7 +1750,7 @@ static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_dsib_clk_ops = {
+struct clk_ops tegra_dsib_clk_ops = {
 	.init			= &tegra30_periph_clk_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1764,7 +1761,7 @@ static struct clk_ops tegra_dsib_clk_ops = {
 };
 
 /* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
+struct clk_ops tegra_pciex_clk_ops = {
 	.reset    = tegra30_periph_clk_reset,
 };
 
@@ -1851,14 +1848,13 @@ static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_clk_out_ops = {
+struct clk_ops tegra_clk_out_ops = {
 	.init			= &tegra30_clk_out_init,
 	.enable			= &tegra30_clk_out_enable,
 	.disable		= &tegra30_clk_out_disable,
 	.set_parent		= &tegra30_clk_out_set_parent,
 };
 
-
 /* Clock doubler ops */
 static void tegra30_clk_double_init(struct clk *c)
 {
@@ -1890,7 +1886,7 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_clk_double_ops = {
+struct clk_ops tegra30_clk_double_ops = {
 	.init			= &tegra30_clk_double_init,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
@@ -1904,7 +1900,7 @@ static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra_sync_source_ops = {
+struct clk_ops tegra_sync_source_ops = {
 	.set_rate		= &tegra30_sync_source_set_rate,
 };
 
@@ -1961,7 +1957,7 @@ static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_audio_sync_clk_ops = {
+struct clk_ops tegra30_audio_sync_clk_ops = {
 	.init       = tegra30_audio_sync_clk_init,
 	.enable     = tegra30_audio_sync_clk_enable,
 	.disable    = tegra30_audio_sync_clk_disable,
@@ -1990,1115 +1986,8 @@ static void tegra30_cml_clk_disable(struct clk *c)
 	clk_writel(val, c->reg);
 }
 
-static struct clk_ops tegra_cml_clk_ops = {
+struct clk_ops tegra_cml_clk_ops = {
 	.init			= &tegra30_cml_clk_init,
 	.enable			= &tegra30_cml_clk_enable,
 	.disable		= &tegra30_cml_clk_disable,
 };
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-	.name = "clk_32k",
-	.rate = 32768,
-	.ops  = NULL,
-	.max_rate = 32768,
-};
-
-static struct clk tegra_clk_m = {
-	.name      = "clk_m",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra_clk_m_ops,
-	.reg       = 0x1fc,
-	.reg_shift = 28,
-	.max_rate  = 48000000,
-};
-
-static struct clk tegra_clk_m_div2 = {
-	.name      = "clk_m_div2",
-	.ops       = &tegra_clk_m_div_ops,
-	.parent    = &tegra_clk_m,
-	.mul       = 1,
-	.div       = 2,
-	.state     = ON,
-	.max_rate  = 24000000,
-};
-
-static struct clk tegra_clk_m_div4 = {
-	.name      = "clk_m_div4",
-	.ops       = &tegra_clk_m_div_ops,
-	.parent    = &tegra_clk_m,
-	.mul       = 1,
-	.div       = 4,
-	.state     = ON,
-	.max_rate  = 12000000,
-};
-
-static struct clk tegra_pll_ref = {
-	.name      = "pll_ref",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra_pll_ref_ops,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-	{ 12000000, 1040000000, 520,  6, 1, 8},
-	{ 13000000, 1040000000, 480,  6, 1, 8},
-	{ 16800000, 1040000000, 495,  8, 1, 8},		/* actual: 1039.5 MHz */
-	{ 19200000, 1040000000, 325,  6, 1, 6},
-	{ 26000000, 1040000000, 520, 13, 1, 8},
-
-	{ 12000000, 832000000, 416,  6, 1, 8},
-	{ 13000000, 832000000, 832, 13, 1, 8},
-	{ 16800000, 832000000, 396,  8, 1, 8},		/* actual: 831.6 MHz */
-	{ 19200000, 832000000, 260,  6, 1, 8},
-	{ 26000000, 832000000, 416, 13, 1, 8},
-
-	{ 12000000, 624000000, 624, 12, 1, 8},
-	{ 13000000, 624000000, 624, 13, 1, 8},
-	{ 16800000, 600000000, 520, 14, 1, 8},
-	{ 19200000, 624000000, 520, 16, 1, 8},
-	{ 26000000, 624000000, 624, 26, 1, 8},
-
-	{ 12000000, 600000000, 600, 12, 1, 8},
-	{ 13000000, 600000000, 600, 13, 1, 8},
-	{ 16800000, 600000000, 500, 14, 1, 8},
-	{ 19200000, 600000000, 375, 12, 1, 6},
-	{ 26000000, 600000000, 600, 26, 1, 8},
-
-	{ 12000000, 520000000, 520, 12, 1, 8},
-	{ 13000000, 520000000, 520, 13, 1, 8},
-	{ 16800000, 520000000, 495, 16, 1, 8},		/* actual: 519.75 MHz */
-	{ 19200000, 520000000, 325, 12, 1, 6},
-	{ 26000000, 520000000, 520, 26, 1, 8},
-
-	{ 12000000, 416000000, 416, 12, 1, 8},
-	{ 13000000, 416000000, 416, 13, 1, 8},
-	{ 16800000, 416000000, 396, 16, 1, 8},		/* actual: 415.8 MHz */
-	{ 19200000, 416000000, 260, 12, 1, 6},
-	{ 26000000, 416000000, 416, 26, 1, 8},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-	.name      = "pll_c",
-	.flags	   = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x80,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1400000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_c_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_c_out1 = {
-	.name      = "pll_c_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_c,
-	.reg       = 0x84,
-	.reg_shift = 0,
-	.max_rate  = 700000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-	{ 12000000, 666000000, 666, 12, 1, 8},
-	{ 13000000, 666000000, 666, 13, 1, 8},
-	{ 16800000, 666000000, 555, 14, 1, 8},
-	{ 19200000, 666000000, 555, 16, 1, 8},
-	{ 26000000, 666000000, 666, 26, 1, 8},
-	{ 12000000, 600000000, 600, 12, 1, 8},
-	{ 13000000, 600000000, 600, 13, 1, 8},
-	{ 16800000, 600000000, 500, 14, 1, 8},
-	{ 19200000, 600000000, 375, 12, 1, 6},
-	{ 26000000, 600000000, 600, 26, 1, 8},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-	.name      = "pll_m",
-	.flags     = PLL_HAS_CPCON | PLLM,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x90,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 800000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_m_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_m_out1 = {
-	.name      = "pll_m_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_m,
-	.reg       = 0x94,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-	{ 12000000, 216000000, 432, 12, 2, 8},
-	{ 13000000, 216000000, 432, 13, 2, 8},
-	{ 16800000, 216000000, 360, 14, 2, 8},
-	{ 19200000, 216000000, 360, 16, 2, 8},
-	{ 26000000, 216000000, 432, 26, 2, 8},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-	.name      = "pll_p",
-	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xa0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 432000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_p_freq_table,
-		.lock_delay = 300,
-		.fixed_rate = 408000000,
-	},
-};
-
-static struct clk tegra_pll_p_out1 = {
-	.name      = "pll_p_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-	.name      = "pll_p_out2",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-	.name      = "pll_p_out3",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-	.name      = "pll_p_out4",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-	{ 9600000, 564480000, 294, 5, 1, 4},
-	{ 9600000, 552960000, 288, 5, 1, 4},
-	{ 9600000, 24000000,  5,   2, 1, 1},
-
-	{ 28800000, 56448000, 49, 25, 1, 1},
-	{ 28800000, 73728000, 64, 25, 1, 1},
-	{ 28800000, 24000000,  5,  6, 1, 1},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-	.name      = "pll_a",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xb0,
-	.parent    = &tegra_pll_p_out1,
-	.max_rate  = 700000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_a_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_a_out0 = {
-	.name      = "pll_a_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_a,
-	.reg       = 0xb4,
-	.reg_shift = 0,
-	.max_rate  = 100000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-	{ 12000000, 216000000, 216, 12, 1, 4},
-	{ 13000000, 216000000, 216, 13, 1, 4},
-	{ 16800000, 216000000, 180, 14, 1, 4},
-	{ 19200000, 216000000, 180, 16, 1, 4},
-	{ 26000000, 216000000, 216, 26, 1, 4},
-
-	{ 12000000, 594000000, 594, 12, 1, 8},
-	{ 13000000, 594000000, 594, 13, 1, 8},
-	{ 16800000, 594000000, 495, 14, 1, 8},
-	{ 19200000, 594000000, 495, 16, 1, 8},
-	{ 26000000, 594000000, 594, 26, 1, 8},
-
-	{ 12000000, 1000000000, 1000, 12, 1, 12},
-	{ 13000000, 1000000000, 1000, 13, 1, 12},
-	{ 19200000, 1000000000, 625,  12, 1, 8},
-	{ 26000000, 1000000000, 1000, 26, 1, 12},
-
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-	.name      = "pll_d",
-	.flags     = PLL_HAS_CPCON | PLLD,
-	.ops       = &tegra_plld_ops,
-	.reg       = 0xd0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
-
-static struct clk tegra_pll_d_out0 = {
-	.name      = "pll_d_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d,
-	.max_rate  = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
-	.name      = "pll_d2",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
-	.ops       = &tegra_plld_ops,
-	.reg       = 0x4b8,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
-
-static struct clk tegra_pll_d2_out0 = {
-	.name      = "pll_d2_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d2,
-	.max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-	{ 12000000, 480000000, 960, 12, 2, 12},
-	{ 13000000, 480000000, 960, 13, 2, 12},
-	{ 16800000, 480000000, 400, 7,  2, 5},
-	{ 19200000, 480000000, 200, 4,  2, 3},
-	{ 26000000, 480000000, 960, 26, 2, 12},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-	.name      = "pll_u",
-	.flags     = PLL_HAS_CPCON | PLLU,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xc0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 480000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 480000000,
-		.vco_max   = 960000000,
-		.freq_table = tegra_pll_u_freq_table,
-		.lock_delay = 1000,
-	},
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-	/* 1.7 GHz */
-	{ 12000000, 1700000000, 850,  6,  1, 8},
-	{ 13000000, 1700000000, 915,  7,  1, 8},	/* actual: 1699.2 MHz */
-	{ 16800000, 1700000000, 708,  7,  1, 8},	/* actual: 1699.2 MHz */
-	{ 19200000, 1700000000, 885,  10, 1, 8},	/* actual: 1699.2 MHz */
-	{ 26000000, 1700000000, 850,  13, 1, 8},
-
-	/* 1.6 GHz */
-	{ 12000000, 1600000000, 800,  6,  1, 8},
-	{ 13000000, 1600000000, 738,  6,  1, 8},	/* actual: 1599.0 MHz */
-	{ 16800000, 1600000000, 857,  9,  1, 8},	/* actual: 1599.7 MHz */
-	{ 19200000, 1600000000, 500,  6,  1, 8},
-	{ 26000000, 1600000000, 800,  13, 1, 8},
-
-	/* 1.5 GHz */
-	{ 12000000, 1500000000, 750,  6,  1, 8},
-	{ 13000000, 1500000000, 923,  8,  1, 8},	/* actual: 1499.8 MHz */
-	{ 16800000, 1500000000, 625,  7,  1, 8},
-	{ 19200000, 1500000000, 625,  8,  1, 8},
-	{ 26000000, 1500000000, 750,  13, 1, 8},
-
-	/* 1.4 GHz */
-	{ 12000000, 1400000000, 700,  6,  1, 8},
-	{ 13000000, 1400000000, 969,  9,  1, 8},	/* actual: 1399.7 MHz */
-	{ 16800000, 1400000000, 1000, 12, 1, 8},
-	{ 19200000, 1400000000, 875,  12, 1, 8},
-	{ 26000000, 1400000000, 700,  13, 1, 8},
-
-	/* 1.3 GHz */
-	{ 12000000, 1300000000, 975,  9,  1, 8},
-	{ 13000000, 1300000000, 1000, 10, 1, 8},
-	{ 16800000, 1300000000, 928,  12, 1, 8},	/* actual: 1299.2 MHz */
-	{ 19200000, 1300000000, 812,  12, 1, 8},	/* actual: 1299.2 MHz */
-	{ 26000000, 1300000000, 650,  13, 1, 8},
-
-	/* 1.2 GHz */
-	{ 12000000, 1200000000, 1000, 10, 1, 8},
-	{ 13000000, 1200000000, 923,  10, 1, 8},	/* actual: 1199.9 MHz */
-	{ 16800000, 1200000000, 1000, 14, 1, 8},
-	{ 19200000, 1200000000, 1000, 16, 1, 8},
-	{ 26000000, 1200000000, 600,  13, 1, 8},
-
-	/* 1.1 GHz */
-	{ 12000000, 1100000000, 825,  9,  1, 8},
-	{ 13000000, 1100000000, 846,  10, 1, 8},	/* actual: 1099.8 MHz */
-	{ 16800000, 1100000000, 982,  15, 1, 8},	/* actual: 1099.8 MHz */
-	{ 19200000, 1100000000, 859,  15, 1, 8},	/* actual: 1099.5 MHz */
-	{ 26000000, 1100000000, 550,  13, 1, 8},
-
-	/* 1 GHz */
-	{ 12000000, 1000000000, 1000, 12, 1, 8},
-	{ 13000000, 1000000000, 1000, 13, 1, 8},
-	{ 16800000, 1000000000, 833,  14, 1, 8},	/* actual: 999.6 MHz */
-	{ 19200000, 1000000000, 625,  12, 1, 8},
-	{ 26000000, 1000000000, 1000, 26, 1, 8},
-
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-	.name      = "pll_x",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xe0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1700000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1700000000,
-		.freq_table = tegra_pll_x_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_x_out0 = {
-	.name      = "pll_x_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_2 | PLLX,
-	.parent    = &tegra_pll_x,
-	.max_rate  = 850000000,
-};
-
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-	/* PLLE special case: use cpcon field to store cml divider value */
-	{ 12000000,  100000000, 150, 1,  18, 11},
-	{ 216000000, 100000000, 200, 18, 24, 13},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-	.name      = "pll_e",
-	.flags     = PLL_ALT_MISC_REG,
-	.ops       = &tegra_plle_ops,
-	.reg       = 0xe8,
-	.max_rate  = 100000000,
-	.u.pll = {
-		.input_min = 12000000,
-		.input_max = 216000000,
-		.cf_min    = 12000000,
-		.cf_max    = 12000000,
-		.vco_min   = 1200000000,
-		.vco_max   = 2400000000U,
-		.freq_table = tegra_pll_e_freq_table,
-		.lock_delay = 300,
-		.fixed_rate = 100000000,
-	},
-};
-
-static struct clk tegra_cml0_clk = {
-	.name      = "cml0",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_cml_clk_ops,
-	.reg       = PLLE_AUX,
-	.max_rate  = 100000000,
-	.u.periph  = {
-		.clk_num = 0,
-	},
-};
-
-static struct clk tegra_cml1_clk = {
-	.name      = "cml1",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_cml_clk_ops,
-	.reg       = PLLE_AUX,
-	.max_rate  = 100000000,
-	.u.periph  = {
-		.clk_num   = 1,
-	},
-};
-
-static struct clk tegra_pciex_clk = {
-	.name      = "pciex",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_pciex_clk_ops,
-	.max_rate  = 100000000,
-	.u.periph  = {
-		.clk_num   = 74,
-	},
-};
-
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id)				\
-	{						\
-		.name      = #_id "_sync",		\
-		.rate      = 24000000,			\
-		.max_rate  = 24000000,			\
-		.ops       = &tegra_sync_source_ops	\
-	}
-static struct clk tegra_sync_source_list[] = {
-	SYNC_SOURCE(spdif_in),
-	SYNC_SOURCE(i2s0),
-	SYNC_SOURCE(i2s1),
-	SYNC_SOURCE(i2s2),
-	SYNC_SOURCE(i2s3),
-	SYNC_SOURCE(i2s4),
-	SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
-	{ .input = &tegra_sync_source_list[0],	.value = 0},
-	{ .input = &tegra_sync_source_list[1],	.value = 1},
-	{ .input = &tegra_sync_source_list[2],	.value = 2},
-	{ .input = &tegra_sync_source_list[3],	.value = 3},
-	{ .input = &tegra_sync_source_list[4],	.value = 4},
-	{ .input = &tegra_sync_source_list[5],	.value = 5},
-	{ .input = &tegra_pll_a_out0,		.value = 6},
-	{ .input = &tegra_sync_source_list[6],	.value = 7},
-	{ 0, 0 }
-};
-
-#define AUDIO_SYNC_CLK(_id, _index)			\
-	{						\
-		.name      = #_id,			\
-		.inputs    = mux_audio_sync_clk,	\
-		.reg       = 0x4A0 + (_index) * 4,	\
-		.max_rate  = 24000000,			\
-		.ops       = &tegra_audio_sync_clk_ops	\
-	}
-static struct clk tegra_clk_audio_list[] = {
-	AUDIO_SYNC_CLK(audio0, 0),
-	AUDIO_SYNC_CLK(audio1, 1),
-	AUDIO_SYNC_CLK(audio2, 2),
-	AUDIO_SYNC_CLK(audio3, 3),
-	AUDIO_SYNC_CLK(audio4, 4),
-	AUDIO_SYNC_CLK(audio, 5),	/* SPDIF */
-};
-
-#define AUDIO_SYNC_2X_CLK(_id, _index)				\
-	{							\
-		.name      = #_id "_2x",			\
-		.flags     = PERIPH_NO_RESET,			\
-		.max_rate  = 48000000,				\
-		.ops       = &tegra_clk_double_ops,		\
-		.reg       = 0x49C,				\
-		.reg_shift = 24 + (_index),			\
-		.parent    = &tegra_clk_audio_list[(_index)],	\
-		.u.periph = {					\
-			.clk_num = 113 + (_index),		\
-		},						\
-	}
-static struct clk tegra_clk_audio_2x_list[] = {
-	AUDIO_SYNC_2X_CLK(audio0, 0),
-	AUDIO_SYNC_2X_CLK(audio1, 1),
-	AUDIO_SYNC_2X_CLK(audio2, 2),
-	AUDIO_SYNC_2X_CLK(audio3, 3),
-	AUDIO_SYNC_2X_CLK(audio4, 4),
-	AUDIO_SYNC_2X_CLK(audio, 5),	/* SPDIF */
-};
-
-#define MUX_I2S_SPDIF(_id, _index)					\
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {	\
-	{.input = &tegra_pll_a_out0, .value = 0},			\
-	{.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},	\
-	{.input = &tegra_pll_p, .value = 2},				\
-	{.input = &tegra_clk_m, .value = 3},				\
-	{ 0, 0},							\
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5);		/* SPDIF */
-
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)						\
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {	\
-	{.input = &tegra_clk_m,		.value = 0},			\
-	{.input = &tegra_clk_m_div2,	.value = 1},			\
-	{.input = &tegra_clk_m_div4,	.value = 2},			\
-	{.input = NULL,			.value = 3}, /* placeholder */	\
-	{ 0, 0},							\
-}
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-
-static struct clk_mux_sel *mux_extern_out_list[] = {
-	mux_clkm_clkm2_clkm4_extern1,
-	mux_clkm_clkm2_clkm4_extern2,
-	mux_clkm_clkm2_clkm4_extern3,
-};
-
-#define CLK_OUT_CLK(_id)					\
-	{							\
-		.name      = "clk_out_" #_id,			\
-		.lookup    = {					\
-			.dev_id    = "clk_out_" #_id,		\
-			.con_id	   = "extern" #_id,		\
-		},						\
-		.ops       = &tegra_clk_out_ops,		\
-		.reg       = 0x1a8,				\
-		.inputs    = mux_clkm_clkm2_clkm4_extern##_id,	\
-		.flags     = MUX_CLK_OUT,			\
-		.max_rate  = 216000000,				\
-		.u.periph = {					\
-			.clk_num   = (_id - 1) * 8 + 2,		\
-		},						\
-	}
-static struct clk tegra_clk_out_list[] = {
-	CLK_OUT_CLK(1),
-	CLK_OUT_CLK(2),
-	CLK_OUT_CLK(3),
-};
-
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
-{
-	int i;
-	struct clk *c;
-
-	/* output clock con_id is the name of peripheral
-	   external clock connected to input 3 of the output mux */
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
-		c = tegra_get_clock_by_name(
-			tegra_clk_out_list[i].lookup.con_id);
-		if (!c)
-			pr_err("%s: could not find clk %s\n", __func__,
-			       tegra_clk_out_list[i].lookup.con_id);
-		mux_extern_out_list[i][3].input = c;
-	}
-}
-
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c_out1,	.value = 1},
-	{ .input = &tegra_pll_p_out4,	.value = 2},
-	{ .input = &tegra_pll_p_out3,	.value = 3},
-	{ .input = &tegra_pll_p_out2,	.value = 4},
-	/* { .input = &tegra_clk_d,	.value = 5}, - no use on tegra30 */
-	{ .input = &tegra_clk_32k,	.value = 6},
-	{ .input = &tegra_pll_m_out1,	.value = 7},
-	{ 0, 0},
-};
-
-static struct clk tegra_clk_sclk = {
-	.name	= "sclk",
-	.inputs	= mux_sclk,
-	.reg	= 0x28,
-	.ops	= &tegra_super_ops,
-	.max_rate = 334000000,
-	.min_rate = 40000000,
-};
-
-static struct clk tegra_clk_blink = {
-	.name		= "blink",
-	.parent		= &tegra_clk_32k,
-	.reg		= 0x40,
-	.ops		= &tegra_blink_clk_ops,
-	.max_rate	= 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_pll_a_out0, .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_m, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_d_out0, .value = 1},
-	{.input = &tegra_pll_c, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_m, .value = 1},
-	{.input = &tegra_pll_d_out0, .value = 2},
-	{.input = &tegra_pll_a_out0, .value = 3},
-	{.input = &tegra_pll_c, .value = 4},
-	{.input = &tegra_pll_d2_out0, .value = 5},
-	{.input = &tegra_clk_m, .value = 6},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
-	{ .input = &tegra_pll_a_out0, .value = 0},
-	/* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_32k,   .value = 2},
-	{.input = &tegra_clk_m,     .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_m,     .value = 2},
-	{.input = &tegra_clk_32k,   .value = 3},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_pll_m,     .value = 2},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-	{ .input = &tegra_clk_m, .value = 0},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-	{ .input = &tegra_pll_p_out3, .value = 0},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0[] = {
-	{ .input = &tegra_pll_d_out0, .value = 0},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
-	{ .input = &tegra_pll_d_out0,  .value = 0},
-	{ .input = &tegra_pll_d2_out0, .value = 1},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
-	{ .input = &tegra_pll_a_out0, .value = 0},
-	{ .input = &tegra_clk_32k,    .value = 1},
-	{ .input = &tegra_pll_p,      .value = 2},
-	{ .input = &tegra_clk_m,      .value = 3},
-	{ .input = &tegra_pll_e,      .value = 4},
-	{ 0, 0},
-};
-
-static struct clk_mux_sel mux_cclk_g[] = {
-	{ .input = &tegra_clk_m,        .value = 0},
-	{ .input = &tegra_pll_c,        .value = 1},
-	{ .input = &tegra_clk_32k,      .value = 2},
-	{ .input = &tegra_pll_m,        .value = 3},
-	{ .input = &tegra_pll_p,        .value = 4},
-	{ .input = &tegra_pll_p_out4,   .value = 5},
-	{ .input = &tegra_pll_p_out3,   .value = 6},
-	{ .input = &tegra_pll_x,        .value = 8},
-	{ 0, 0},
-};
-
-static struct clk tegra_clk_cclk_g = {
-	.name	= "cclk_g",
-	.flags	= DIV_U71 | DIV_U71_INT,
-	.inputs = mux_cclk_g,
-	.reg	= 0x368,
-	.ops	= &tegra_super_ops,
-	.max_rate = 1700000000,
-};
-
-static struct clk tegra30_clk_twd = {
-	.parent	  = &tegra_clk_cclk_g,
-	.name     = "twd",
-	.ops      = &tegra30_twd_ops,
-	.max_rate = 1400000000,	/* Same as tegra_clk_cpu_cmplx.max_rate */
-	.mul      = 1,
-	.div      = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
-		},					\
-		.ops       = &tegra_periph_clk_ops,	\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
-		},					\
-	}
-
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs,	\
-			_flags, _ops)					\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
-		},					\
-		.ops       = _ops,			\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
-		},					\
-	}
-
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id    = _con,		\
-		},					\
-		.ops       = &tegra_clk_shared_bus_ops,	\
-		.parent = _parent,			\
-		.u.shared_bus_user = {			\
-			.client_id = _id,		\
-			.client_div = _div,		\
-			.mode = _mode,			\
-		},					\
-	}
-struct clk tegra_list_clks[] = {
-	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
-	PERIPH_CLK("kbc",	"tegra-kbc",		NULL,	36,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
-	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("kfuse",	"kfuse-tegra",		NULL,	40,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("fuse",	"fuse-tegra",		"fuse",	39,	0,	26000000,  mux_clk_m,			PERIPH_ON_APB),
-	PERIPH_CLK("fuse_burn",	"fuse-tegra",		"fuse_burn",	39,	0,	26000000,  mux_clk_m,		PERIPH_ON_APB),
-	PERIPH_CLK("apbif",	"tegra30-ahub",		"apbif", 107,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("i2s0",	"tegra30-i2s.0",	NULL,	30,	0x1d8,	26000000,  mux_pllaout0_audio0_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s1",	"tegra30-i2s.1",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio1_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s2",	"tegra30-i2s.2",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s3",	"tegra30-i2s.3",	NULL,	101,	0x3bc,	26000000,  mux_pllaout0_audio3_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s4",	"tegra30-i2s.4",	NULL,	102,	0x3c0,	26000000,  mux_pllaout0_audio4_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("spdif_out",	"tegra30-spdif",	"spdif_out",	10,	0x108,	100000000, mux_pllaout0_audio_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("spdif_in",	"tegra30-spdif",	"spdif_in",	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("d_audio",	"tegra30-ahub",		"d_audio", 106,	0x3d0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam0",	"tegra30-dam.0",	NULL,   108,	0x3d8,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam1",	"tegra30-dam.1",	NULL,   109,	0x3dc,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam2",	"tegra30-dam.2",	NULL,   110,	0x3e0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda",	"tegra30-hda",		"hda",   125,	0x428,	108000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda2codec_2x",	"tegra30-hda",	"hda2codec",   111,	0x3e4,	48000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda2hdmi",	"tegra30-hda",		"hda2hdmi",	128,	0,	48000000,  mux_clk_m,			0),
-	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc5",	"spi_tegra.4",		NULL,	104,	0x3c8,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc6",	"spi_tegra.5",		NULL,	105,	0x3cc,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sata_oob",	"tegra_sata_oob",	NULL,	123,	0x420,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sata",	"tegra_sata",		NULL,	124,	0x424,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sata_cold",	"tegra_sata_cold",	NULL,	129,	0,	48000000,  mux_clk_m,			0),
-	PERIPH_CLK_EX("ndflash", "tegra_nand",		NULL,	13,	0x160,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71,	&tegra_nand_clk_ops),
-	PERIPH_CLK("ndspeed",	"tegra_nand_speed",	NULL,	80,	0x3f8,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("vde",	"vde",			NULL,	61,	0x1c8,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
-	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	127000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
-	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c4",	"tegra-i2c.3",		NULL,	103,	0x3c4,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c5",	"tegra-i2c.4",		NULL,	47,	0x128,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK_EX("vi",	"tegra_camera",		"vi",	20,	0x148,	425000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT,	&tegra_vi_clk_ops),
-	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-	PERIPH_CLK("3d2",       "3d2",			NULL,	98,	0x3b0,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET),
-	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	260000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK_EX("dtv",	"dtv",			NULL,	79,	0x1dc,	250000000, mux_clk_m,			0,		&tegra_dtv_clk_ops),
-	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	220000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
-	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
-	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("dsia",	"tegradc.0",		"dsia",	48,	0,	500000000, mux_plld_out0,		0),
-	PERIPH_CLK_EX("dsib",	"tegradc.1",		"dsib",	82,	0xd0,	500000000, mux_plld_out0_plld2_out0,	MUX | PLLD,	&tegra_dsib_clk_ops),
-	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	102000000, mux_pllp_out3,		0),
-	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
-	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
-
-	PERIPH_CLK("tsensor",	"tegra-tsensor",	NULL,	100,	0x3b8,	216000000, mux_pllp_pllc_clkm_clk32,	MUX | DIV_U71),
-	PERIPH_CLK("actmon",	"actmon",		NULL,	119,	0x3e8,	216000000, mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("extern1",	"extern1",		NULL,	120,	0x3ec,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("extern2",	"extern2",		NULL,	121,	0x3f0,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("extern3",	"extern3",		NULL,	122,	0x3f4,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("i2cslow",	"i2cslow",		NULL,	81,	0x3fc,	26000000,  mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("pcie",	"tegra-pcie",		"pcie",	70,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("afi",	"tegra-pcie",		"afi",	72,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("se",	"se",			NULL,	127,	0x42c,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)		\
-	{						\
-		.name	= _name,			\
-		.lookup	= {				\
-			.dev_id	= _dev,			\
-			.con_id		= _con,		\
-		},					\
-	}
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
-	CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-	CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-	CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-	CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-	CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-	CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-	CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
-	CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-	CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
-	CLK_DUPLICATE("bsev", "nvavp", "bsev"),
-	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-	CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
-	CLK_DUPLICATE("bsea", "nvavp", "bsea"),
-	CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
-	CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
-	CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
-	CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
-	CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
-	CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
-	CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
-	CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
-	CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
-	CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
-	CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
-	CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
-	CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
-	CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
-	CLK_DUPLICATE("twd", "smp_twd", NULL),
-	CLK_DUPLICATE("vcp", "nvavp", "vcp"),
-	CLK_DUPLICATE("i2s0", NULL, "i2s0"),
-	CLK_DUPLICATE("i2s1", NULL, "i2s1"),
-	CLK_DUPLICATE("i2s2", NULL, "i2s2"),
-	CLK_DUPLICATE("i2s3", NULL, "i2s3"),
-	CLK_DUPLICATE("i2s4", NULL, "i2s4"),
-	CLK_DUPLICATE("dam0", NULL, "dam0"),
-	CLK_DUPLICATE("dam1", NULL, "dam1"),
-	CLK_DUPLICATE("dam2", NULL, "dam2"),
-	CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-};
-
-struct clk *tegra_ptr_clks[] = {
-	&tegra_clk_32k,
-	&tegra_clk_m,
-	&tegra_clk_m_div2,
-	&tegra_clk_m_div4,
-	&tegra_pll_ref,
-	&tegra_pll_m,
-	&tegra_pll_m_out1,
-	&tegra_pll_c,
-	&tegra_pll_c_out1,
-	&tegra_pll_p,
-	&tegra_pll_p_out1,
-	&tegra_pll_p_out2,
-	&tegra_pll_p_out3,
-	&tegra_pll_p_out4,
-	&tegra_pll_a,
-	&tegra_pll_a_out0,
-	&tegra_pll_d,
-	&tegra_pll_d_out0,
-	&tegra_pll_d2,
-	&tegra_pll_d2_out0,
-	&tegra_pll_u,
-	&tegra_pll_x,
-	&tegra_pll_x_out0,
-	&tegra_pll_e,
-	&tegra_clk_cclk_g,
-	&tegra_cml0_clk,
-	&tegra_cml1_clk,
-	&tegra_pciex_clk,
-	&tegra_clk_sclk,
-	&tegra_clk_blink,
-	&tegra30_clk_twd,
-};
-
-
-static void tegra30_init_one_clock(struct clk *c)
-{
-	clk_init(c);
-	INIT_LIST_HEAD(&c->shared_bus_list);
-	if (!c->lookup.dev_id && !c->lookup.con_id)
-		c->lookup.con_id = c->name;
-	c->lookup.clk = c;
-	clkdev_add(&c->lookup);
-}
-
-void __init tegra30_init_clocks(void)
-{
-	int i;
-	struct clk *c;
-
-	for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-		tegra30_init_one_clock(tegra_ptr_clks[i]);
-
-	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-		tegra30_init_one_clock(&tegra_list_clks[i]);
-
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-		if (!c) {
-			pr_err("%s: Unknown duplicate clock %s\n", __func__,
-				tegra_clk_duplicates[i].name);
-			continue;
-		}
-
-		tegra_clk_duplicates[i].lookup.clk = c;
-		clkdev_add(&tegra_clk_duplicates[i].lookup);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
-		tegra30_init_one_clock(&tegra_sync_source_list[i]);
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
-		tegra30_init_one_clock(&tegra_clk_audio_list[i]);
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-		tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
-
-	init_clk_out_mux();
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
-		tegra30_init_one_clock(&tegra_clk_out_list[i]);
-
-}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 0000000..f8c4df5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 0000000..b1243c9
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1144 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks_data.c
+ *
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/iomap.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra30_clocks.h"
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+	.name = "clk_32k",
+	.rate = 32768,
+	.ops  = NULL,
+	.max_rate = 32768,
+};
+
+static struct clk tegra_clk_m = {
+	.name      = "clk_m",
+	.flags     = ENABLE_ON_INIT,
+	.ops       = &tegra30_clk_m_ops,
+	.reg       = 0x1fc,
+	.reg_shift = 28,
+	.max_rate  = 48000000,
+};
+
+static struct clk tegra_clk_m_div2 = {
+	.name      = "clk_m_div2",
+	.ops       = &tegra_clk_m_div_ops,
+	.parent    = &tegra_clk_m,
+	.mul       = 1,
+	.div       = 2,
+	.state     = ON,
+	.max_rate  = 24000000,
+};
+
+static struct clk tegra_clk_m_div4 = {
+	.name      = "clk_m_div4",
+	.ops       = &tegra_clk_m_div_ops,
+	.parent    = &tegra_clk_m,
+	.mul       = 1,
+	.div       = 4,
+	.state     = ON,
+	.max_rate  = 12000000,
+};
+
+static struct clk tegra_pll_ref = {
+	.name      = "pll_ref",
+	.flags     = ENABLE_ON_INIT,
+	.ops       = &tegra_pll_ref_ops,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 26000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+	{ 12000000, 1040000000, 520,  6, 1, 8},
+	{ 13000000, 1040000000, 480,  6, 1, 8},
+	{ 16800000, 1040000000, 495,  8, 1, 8},		/* actual: 1039.5 MHz */
+	{ 19200000, 1040000000, 325,  6, 1, 6},
+	{ 26000000, 1040000000, 520, 13, 1, 8},
+
+	{ 12000000, 832000000, 416,  6, 1, 8},
+	{ 13000000, 832000000, 832, 13, 1, 8},
+	{ 16800000, 832000000, 396,  8, 1, 8},		/* actual: 831.6 MHz */
+	{ 19200000, 832000000, 260,  6, 1, 8},
+	{ 26000000, 832000000, 416, 13, 1, 8},
+
+	{ 12000000, 624000000, 624, 12, 1, 8},
+	{ 13000000, 624000000, 624, 13, 1, 8},
+	{ 16800000, 600000000, 520, 14, 1, 8},
+	{ 19200000, 624000000, 520, 16, 1, 8},
+	{ 26000000, 624000000, 624, 26, 1, 8},
+
+	{ 12000000, 600000000, 600, 12, 1, 8},
+	{ 13000000, 600000000, 600, 13, 1, 8},
+	{ 16800000, 600000000, 500, 14, 1, 8},
+	{ 19200000, 600000000, 375, 12, 1, 6},
+	{ 26000000, 600000000, 600, 26, 1, 8},
+
+	{ 12000000, 520000000, 520, 12, 1, 8},
+	{ 13000000, 520000000, 520, 13, 1, 8},
+	{ 16800000, 520000000, 495, 16, 1, 8},		/* actual: 519.75 MHz */
+	{ 19200000, 520000000, 325, 12, 1, 6},
+	{ 26000000, 520000000, 520, 26, 1, 8},
+
+	{ 12000000, 416000000, 416, 12, 1, 8},
+	{ 13000000, 416000000, 416, 13, 1, 8},
+	{ 16800000, 416000000, 396, 16, 1, 8},		/* actual: 415.8 MHz */
+	{ 19200000, 416000000, 260, 12, 1, 6},
+	{ 26000000, 416000000, 416, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+	.name      = "pll_c",
+	.flags	   = PLL_HAS_CPCON,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0x80,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 1400000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_c_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_c_out1 = {
+	.name      = "pll_c_out1",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_c,
+	.reg       = 0x84,
+	.reg_shift = 0,
+	.max_rate  = 700000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+	{ 12000000, 666000000, 666, 12, 1, 8},
+	{ 13000000, 666000000, 666, 13, 1, 8},
+	{ 16800000, 666000000, 555, 14, 1, 8},
+	{ 19200000, 666000000, 555, 16, 1, 8},
+	{ 26000000, 666000000, 666, 26, 1, 8},
+	{ 12000000, 600000000, 600, 12, 1, 8},
+	{ 13000000, 600000000, 600, 13, 1, 8},
+	{ 16800000, 600000000, 500, 14, 1, 8},
+	{ 19200000, 600000000, 375, 12, 1, 6},
+	{ 26000000, 600000000, 600, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+	.name      = "pll_m",
+	.flags     = PLL_HAS_CPCON | PLLM,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0x90,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 800000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1200000000,
+		.freq_table = tegra_pll_m_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_m_out1 = {
+	.name      = "pll_m_out1",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_m,
+	.reg       = 0x94,
+	.reg_shift = 0,
+	.max_rate  = 600000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+	{ 12000000, 216000000, 432, 12, 2, 8},
+	{ 13000000, 216000000, 432, 13, 2, 8},
+	{ 16800000, 216000000, 360, 14, 2, 8},
+	{ 19200000, 216000000, 360, 16, 2, 8},
+	{ 26000000, 216000000, 432, 26, 2, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+	.name      = "pll_p",
+	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0xa0,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 432000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_p_freq_table,
+		.lock_delay = 300,
+		.fixed_rate = 408000000,
+	},
+};
+
+static struct clk tegra_pll_p_out1 = {
+	.name      = "pll_p_out1",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 0,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out2 = {
+	.name      = "pll_p_out2",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 16,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out3 = {
+	.name      = "pll_p_out3",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 0,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out4 = {
+	.name      = "pll_p_out4",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 16,
+	.max_rate  = 432000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+	{ 9600000, 564480000, 294, 5, 1, 4},
+	{ 9600000, 552960000, 288, 5, 1, 4},
+	{ 9600000, 24000000,  5,   2, 1, 1},
+
+	{ 28800000, 56448000, 49, 25, 1, 1},
+	{ 28800000, 73728000, 64, 25, 1, 1},
+	{ 28800000, 24000000,  5,  6, 1, 1},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+	.name      = "pll_a",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0xb0,
+	.parent    = &tegra_pll_p_out1,
+	.max_rate  = 700000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_a_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_a_out0 = {
+	.name      = "pll_a_out0",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_a,
+	.reg       = 0xb4,
+	.reg_shift = 0,
+	.max_rate  = 100000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+	{ 12000000, 216000000, 216, 12, 1, 4},
+	{ 13000000, 216000000, 216, 13, 1, 4},
+	{ 16800000, 216000000, 180, 14, 1, 4},
+	{ 19200000, 216000000, 180, 16, 1, 4},
+	{ 26000000, 216000000, 216, 26, 1, 4},
+
+	{ 12000000, 594000000, 594, 12, 1, 8},
+	{ 13000000, 594000000, 594, 13, 1, 8},
+	{ 16800000, 594000000, 495, 14, 1, 8},
+	{ 19200000, 594000000, 495, 16, 1, 8},
+	{ 26000000, 594000000, 594, 26, 1, 8},
+
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+	.name      = "pll_d",
+	.flags     = PLL_HAS_CPCON | PLLD,
+	.ops       = &tegra_plld_ops,
+	.reg       = 0xd0,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 1000000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 40000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 40000000,
+		.vco_max   = 1000000000,
+		.freq_table = tegra_pll_d_freq_table,
+		.lock_delay = 1000,
+	},
+};
+
+static struct clk tegra_pll_d_out0 = {
+	.name      = "pll_d_out0",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_2 | PLLD,
+	.parent    = &tegra_pll_d,
+	.max_rate  = 500000000,
+};
+
+static struct clk tegra_pll_d2 = {
+	.name      = "pll_d2",
+	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
+	.ops       = &tegra_plld_ops,
+	.reg       = 0x4b8,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 1000000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 40000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 40000000,
+		.vco_max   = 1000000000,
+		.freq_table = tegra_pll_d_freq_table,
+		.lock_delay = 1000,
+	},
+};
+
+static struct clk tegra_pll_d2_out0 = {
+	.name      = "pll_d2_out0",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_2 | PLLD,
+	.parent    = &tegra_pll_d2,
+	.max_rate  = 500000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+	{ 12000000, 480000000, 960, 12, 2, 12},
+	{ 13000000, 480000000, 960, 13, 2, 12},
+	{ 16800000, 480000000, 400, 7,  2, 5},
+	{ 19200000, 480000000, 200, 4,  2, 3},
+	{ 26000000, 480000000, 960, 26, 2, 12},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+	.name      = "pll_u",
+	.flags     = PLL_HAS_CPCON | PLLU,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0xc0,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 480000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 40000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 480000000,
+		.vco_max   = 960000000,
+		.freq_table = tegra_pll_u_freq_table,
+		.lock_delay = 1000,
+	},
+};
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+	/* 1.7 GHz */
+	{ 12000000, 1700000000, 850,  6,  1, 8},
+	{ 13000000, 1700000000, 915,  7,  1, 8},	/* actual: 1699.2 MHz */
+	{ 16800000, 1700000000, 708,  7,  1, 8},	/* actual: 1699.2 MHz */
+	{ 19200000, 1700000000, 885,  10, 1, 8},	/* actual: 1699.2 MHz */
+	{ 26000000, 1700000000, 850,  13, 1, 8},
+
+	/* 1.6 GHz */
+	{ 12000000, 1600000000, 800,  6,  1, 8},
+	{ 13000000, 1600000000, 738,  6,  1, 8},	/* actual: 1599.0 MHz */
+	{ 16800000, 1600000000, 857,  9,  1, 8},	/* actual: 1599.7 MHz */
+	{ 19200000, 1600000000, 500,  6,  1, 8},
+	{ 26000000, 1600000000, 800,  13, 1, 8},
+
+	/* 1.5 GHz */
+	{ 12000000, 1500000000, 750,  6,  1, 8},
+	{ 13000000, 1500000000, 923,  8,  1, 8},	/* actual: 1499.8 MHz */
+	{ 16800000, 1500000000, 625,  7,  1, 8},
+	{ 19200000, 1500000000, 625,  8,  1, 8},
+	{ 26000000, 1500000000, 750,  13, 1, 8},
+
+	/* 1.4 GHz */
+	{ 12000000, 1400000000, 700,  6,  1, 8},
+	{ 13000000, 1400000000, 969,  9,  1, 8},	/* actual: 1399.7 MHz */
+	{ 16800000, 1400000000, 1000, 12, 1, 8},
+	{ 19200000, 1400000000, 875,  12, 1, 8},
+	{ 26000000, 1400000000, 700,  13, 1, 8},
+
+	/* 1.3 GHz */
+	{ 12000000, 1300000000, 975,  9,  1, 8},
+	{ 13000000, 1300000000, 1000, 10, 1, 8},
+	{ 16800000, 1300000000, 928,  12, 1, 8},	/* actual: 1299.2 MHz */
+	{ 19200000, 1300000000, 812,  12, 1, 8},	/* actual: 1299.2 MHz */
+	{ 26000000, 1300000000, 650,  13, 1, 8},
+
+	/* 1.2 GHz */
+	{ 12000000, 1200000000, 1000, 10, 1, 8},
+	{ 13000000, 1200000000, 923,  10, 1, 8},	/* actual: 1199.9 MHz */
+	{ 16800000, 1200000000, 1000, 14, 1, 8},
+	{ 19200000, 1200000000, 1000, 16, 1, 8},
+	{ 26000000, 1200000000, 600,  13, 1, 8},
+
+	/* 1.1 GHz */
+	{ 12000000, 1100000000, 825,  9,  1, 8},
+	{ 13000000, 1100000000, 846,  10, 1, 8},	/* actual: 1099.8 MHz */
+	{ 16800000, 1100000000, 982,  15, 1, 8},	/* actual: 1099.8 MHz */
+	{ 19200000, 1100000000, 859,  15, 1, 8},	/* actual: 1099.5 MHz */
+	{ 26000000, 1100000000, 550,  13, 1, 8},
+
+	/* 1 GHz */
+	{ 12000000, 1000000000, 1000, 12, 1, 8},
+	{ 13000000, 1000000000, 1000, 13, 1, 8},
+	{ 16800000, 1000000000, 833,  14, 1, 8},	/* actual: 999.6 MHz */
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 8},
+
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+	.name      = "pll_x",
+	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
+	.ops       = &tegra30_pll_ops,
+	.reg       = 0xe0,
+	.parent    = &tegra_pll_ref,
+	.max_rate  = 1700000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1700000000,
+		.freq_table = tegra_pll_x_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_x_out0 = {
+	.name      = "pll_x_out0",
+	.ops       = &tegra30_pll_div_ops,
+	.flags     = DIV_2 | PLLX,
+	.parent    = &tegra_pll_x,
+	.max_rate  = 850000000,
+};
+
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+	/* PLLE special case: use cpcon field to store cml divider value */
+	{ 12000000,  100000000, 150, 1,  18, 11},
+	{ 216000000, 100000000, 200, 18, 24, 13},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_e = {
+	.name      = "pll_e",
+	.flags     = PLL_ALT_MISC_REG,
+	.ops       = &tegra30_plle_ops,
+	.reg       = 0xe8,
+	.max_rate  = 100000000,
+	.u.pll = {
+		.input_min = 12000000,
+		.input_max = 216000000,
+		.cf_min    = 12000000,
+		.cf_max    = 12000000,
+		.vco_min   = 1200000000,
+		.vco_max   = 2400000000U,
+		.freq_table = tegra_pll_e_freq_table,
+		.lock_delay = 300,
+		.fixed_rate = 100000000,
+	},
+};
+
+static struct clk tegra_cml0_clk = {
+	.name      = "cml0",
+	.parent    = &tegra_pll_e,
+	.ops       = &tegra_cml_clk_ops,
+	.reg       = 0x48c,
+	.max_rate  = 100000000,
+	.u.periph  = {
+		.clk_num = 0,
+	},
+};
+
+static struct clk tegra_cml1_clk = {
+	.name      = "cml1",
+	.parent    = &tegra_pll_e,
+	.ops       = &tegra_cml_clk_ops,
+	.reg       = 0x48c,
+	.max_rate  = 100000000,
+	.u.periph  = {
+		.clk_num   = 1,
+	},
+};
+
+static struct clk tegra_pciex_clk = {
+	.name      = "pciex",
+	.parent    = &tegra_pll_e,
+	.ops       = &tegra_pciex_clk_ops,
+	.max_rate  = 100000000,
+	.u.periph  = {
+		.clk_num   = 74,
+	},
+};
+
+/* Audio sync clocks */
+#define SYNC_SOURCE(_id)				\
+	{						\
+		.name      = #_id "_sync",		\
+		.rate      = 24000000,			\
+		.max_rate  = 24000000,			\
+		.ops       = &tegra_sync_source_ops	\
+	}
+static struct clk tegra_sync_source_list[] = {
+	SYNC_SOURCE(spdif_in),
+	SYNC_SOURCE(i2s0),
+	SYNC_SOURCE(i2s1),
+	SYNC_SOURCE(i2s2),
+	SYNC_SOURCE(i2s3),
+	SYNC_SOURCE(i2s4),
+	SYNC_SOURCE(vimclk),
+};
+
+static struct clk_mux_sel mux_audio_sync_clk[] = {
+	{ .input = &tegra_sync_source_list[0],	.value = 0},
+	{ .input = &tegra_sync_source_list[1],	.value = 1},
+	{ .input = &tegra_sync_source_list[2],	.value = 2},
+	{ .input = &tegra_sync_source_list[3],	.value = 3},
+	{ .input = &tegra_sync_source_list[4],	.value = 4},
+	{ .input = &tegra_sync_source_list[5],	.value = 5},
+	{ .input = &tegra_pll_a_out0,		.value = 6},
+	{ .input = &tegra_sync_source_list[6],	.value = 7},
+	{ 0, 0 }
+};
+
+#define AUDIO_SYNC_CLK(_id, _index)			\
+	{						\
+		.name      = #_id,			\
+		.inputs    = mux_audio_sync_clk,	\
+		.reg       = 0x4A0 + (_index) * 4,	\
+		.max_rate  = 24000000,			\
+		.ops       = &tegra30_audio_sync_clk_ops	\
+	}
+static struct clk tegra_clk_audio_list[] = {
+	AUDIO_SYNC_CLK(audio0, 0),
+	AUDIO_SYNC_CLK(audio1, 1),
+	AUDIO_SYNC_CLK(audio2, 2),
+	AUDIO_SYNC_CLK(audio3, 3),
+	AUDIO_SYNC_CLK(audio4, 4),
+	AUDIO_SYNC_CLK(audio, 5),	/* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_id, _index)				\
+	{							\
+		.name      = #_id "_2x",			\
+		.flags     = PERIPH_NO_RESET,			\
+		.max_rate  = 48000000,				\
+		.ops       = &tegra30_clk_double_ops,		\
+		.reg       = 0x49C,				\
+		.reg_shift = 24 + (_index),			\
+		.parent    = &tegra_clk_audio_list[(_index)],	\
+		.u.periph = {					\
+			.clk_num = 113 + (_index),		\
+		},						\
+	}
+static struct clk tegra_clk_audio_2x_list[] = {
+	AUDIO_SYNC_2X_CLK(audio0, 0),
+	AUDIO_SYNC_2X_CLK(audio1, 1),
+	AUDIO_SYNC_2X_CLK(audio2, 2),
+	AUDIO_SYNC_2X_CLK(audio3, 3),
+	AUDIO_SYNC_2X_CLK(audio4, 4),
+	AUDIO_SYNC_2X_CLK(audio, 5),	/* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id, _index)					\
+static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {	\
+	{.input = &tegra_pll_a_out0, .value = 0},			\
+	{.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},	\
+	{.input = &tegra_pll_p, .value = 2},				\
+	{.input = &tegra_clk_m, .value = 3},				\
+	{ 0, 0},							\
+}
+MUX_I2S_SPDIF(audio0, 0);
+MUX_I2S_SPDIF(audio1, 1);
+MUX_I2S_SPDIF(audio2, 2);
+MUX_I2S_SPDIF(audio3, 3);
+MUX_I2S_SPDIF(audio4, 4);
+MUX_I2S_SPDIF(audio, 5);		/* SPDIF */
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)						\
+static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {	\
+	{.input = &tegra_clk_m,		.value = 0},			\
+	{.input = &tegra_clk_m_div2,	.value = 1},			\
+	{.input = &tegra_clk_m_div4,	.value = 2},			\
+	{.input = NULL,			.value = 3}, /* placeholder */	\
+	{ 0, 0},							\
+}
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+static struct clk_mux_sel *mux_extern_out_list[] = {
+	mux_clkm_clkm2_clkm4_extern1,
+	mux_clkm_clkm2_clkm4_extern2,
+	mux_clkm_clkm2_clkm4_extern3,
+};
+
+#define CLK_OUT_CLK(_id)					\
+	{							\
+		.name      = "clk_out_" #_id,			\
+		.lookup    = {					\
+			.dev_id    = "clk_out_" #_id,		\
+			.con_id	   = "extern" #_id,		\
+		},						\
+		.ops       = &tegra_clk_out_ops,		\
+		.reg       = 0x1a8,				\
+		.inputs    = mux_clkm_clkm2_clkm4_extern##_id,	\
+		.flags     = MUX_CLK_OUT,			\
+		.max_rate  = 216000000,				\
+		.u.periph = {					\
+			.clk_num   = (_id - 1) * 8 + 2,		\
+		},						\
+	}
+static struct clk tegra_clk_out_list[] = {
+	CLK_OUT_CLK(1),
+	CLK_OUT_CLK(2),
+	CLK_OUT_CLK(3),
+};
+
+/* called after peripheral external clocks are initialized */
+static void init_clk_out_mux(void)
+{
+	int i;
+	struct clk *c;
+
+	/* output clock con_id is the name of peripheral
+	   external clock connected to input 3 of the output mux */
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
+		c = tegra_get_clock_by_name(
+			tegra_clk_out_list[i].lookup.con_id);
+		if (!c)
+			pr_err("%s: could not find clk %s\n", __func__,
+			       tegra_clk_out_list[i].lookup.con_id);
+		mux_extern_out_list[i][3].input = c;
+	}
+}
+
+/* Peripheral muxes */
+static struct clk_mux_sel mux_sclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c_out1,	.value = 1},
+	{ .input = &tegra_pll_p_out4,	.value = 2},
+	{ .input = &tegra_pll_p_out3,	.value = 3},
+	{ .input = &tegra_pll_p_out2,	.value = 4},
+	/* { .input = &tegra_clk_d,	.value = 5}, - no use on tegra30 */
+	{ .input = &tegra_clk_32k,	.value = 6},
+	{ .input = &tegra_pll_m_out1,	.value = 7},
+	{ 0, 0},
+};
+
+static struct clk tegra_clk_sclk = {
+	.name	= "sclk",
+	.inputs	= mux_sclk,
+	.reg	= 0x28,
+	.ops	= &tegra30_super_ops,
+	.max_rate = 334000000,
+	.min_rate = 40000000,
+};
+
+static struct clk tegra_clk_blink = {
+	.name		= "blink",
+	.parent		= &tegra_clk_32k,
+	.reg		= 0x40,
+	.ops		= &tegra30_blink_clk_ops,
+	.max_rate	= 32768,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_pll_a_out0, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+	{ .input = &tegra_pll_p, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_m, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_clkm[] = {
+	{ .input = &tegra_pll_p, .value = 0},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+	{.input = &tegra_pll_p, .value = 0},
+	{.input = &tegra_pll_d_out0, .value = 1},
+	{.input = &tegra_pll_c, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+	{.input = &tegra_pll_p, .value = 0},
+	{.input = &tegra_pll_m, .value = 1},
+	{.input = &tegra_pll_d_out0, .value = 2},
+	{.input = &tegra_pll_a_out0, .value = 3},
+	{.input = &tegra_pll_c, .value = 4},
+	{.input = &tegra_pll_d2_out0, .value = 5},
+	{.input = &tegra_clk_m, .value = 6},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
+	{ .input = &tegra_pll_a_out0, .value = 0},
+	/* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_clk_32k,   .value = 2},
+	{.input = &tegra_clk_m,     .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_clk_m,     .value = 2},
+	{.input = &tegra_clk_32k,   .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_pll_m,     .value = 2},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+	{ .input = &tegra_clk_m, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+	{ .input = &tegra_pll_p_out3, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0[] = {
+	{ .input = &tegra_pll_d_out0, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
+	{ .input = &tegra_pll_d_out0,  .value = 0},
+	{ .input = &tegra_pll_d2_out0, .value = 1},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
+	{ .input = &tegra_pll_a_out0, .value = 0},
+	{ .input = &tegra_clk_32k,    .value = 1},
+	{ .input = &tegra_pll_p,      .value = 2},
+	{ .input = &tegra_clk_m,      .value = 3},
+	{ .input = &tegra_pll_e,      .value = 4},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_cclk_g[] = {
+	{ .input = &tegra_clk_m,        .value = 0},
+	{ .input = &tegra_pll_c,        .value = 1},
+	{ .input = &tegra_clk_32k,      .value = 2},
+	{ .input = &tegra_pll_m,        .value = 3},
+	{ .input = &tegra_pll_p,        .value = 4},
+	{ .input = &tegra_pll_p_out4,   .value = 5},
+	{ .input = &tegra_pll_p_out3,   .value = 6},
+	{ .input = &tegra_pll_x,        .value = 8},
+	{ 0, 0},
+};
+
+static struct clk tegra_clk_cclk_g = {
+	.name	= "cclk_g",
+	.flags	= DIV_U71 | DIV_U71_INT,
+	.inputs = mux_cclk_g,
+	.reg	= 0x368,
+	.ops	= &tegra30_super_ops,
+	.max_rate = 1700000000,
+};
+
+static struct clk tegra30_clk_twd = {
+	.parent	  = &tegra_clk_cclk_g,
+	.name     = "twd",
+	.ops      = &tegra30_twd_ops,
+	.max_rate = 1400000000,	/* Same as tegra_clk_cpu_cmplx.max_rate */
+	.mul      = 1,
+	.div      = 2,
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+		.ops       = &tegra30_periph_clk_ops,	\
+		.reg       = _reg,			\
+		.inputs    = _inputs,			\
+		.flags     = _flags,			\
+		.max_rate  = _max,			\
+		.u.periph = {				\
+			.clk_num   = _clk_num,		\
+		},					\
+	}
+
+#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs,	\
+			_flags, _ops)					\
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+		.ops       = _ops,			\
+		.reg       = _reg,			\
+		.inputs    = _inputs,			\
+		.flags     = _flags,			\
+		.max_rate  = _max,			\
+		.u.periph = {				\
+			.clk_num   = _clk_num,		\
+		},					\
+	}
+
+#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id    = _con,		\
+		},					\
+		.ops       = &tegra_clk_shared_bus_ops,	\
+		.parent = _parent,			\
+		.u.shared_bus_user = {			\
+			.client_id = _id,		\
+			.client_div = _div,		\
+			.mode = _mode,			\
+		},					\
+	}
+struct clk tegra_list_clks[] = {
+	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
+	PERIPH_CLK("kbc",	"tegra-kbc",		NULL,	36,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
+	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("kfuse",	"kfuse-tegra",		NULL,	40,	0,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("fuse",	"fuse-tegra",		"fuse",	39,	0,	26000000,  mux_clk_m,			PERIPH_ON_APB),
+	PERIPH_CLK("fuse_burn",	"fuse-tegra",		"fuse_burn",	39,	0,	26000000,  mux_clk_m,		PERIPH_ON_APB),
+	PERIPH_CLK("apbif",	"tegra30-ahub",		"apbif", 107,	0,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("i2s0",	"tegra30-i2s.0",	NULL,	30,	0x1d8,	26000000,  mux_pllaout0_audio0_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("i2s1",	"tegra30-i2s.1",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio1_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("i2s2",	"tegra30-i2s.2",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("i2s3",	"tegra30-i2s.3",	NULL,	101,	0x3bc,	26000000,  mux_pllaout0_audio3_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("i2s4",	"tegra30-i2s.4",	NULL,	102,	0x3c0,	26000000,  mux_pllaout0_audio4_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("spdif_out",	"tegra30-spdif",	"spdif_out",	10,	0x108,	100000000, mux_pllaout0_audio_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("spdif_in",	"tegra30-spdif",	"spdif_in",	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("d_audio",	"tegra30-ahub",		"d_audio", 106,	0x3d0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("dam0",	"tegra30-dam.0",	NULL,   108,	0x3d8,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("dam1",	"tegra30-dam.1",	NULL,   109,	0x3dc,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("dam2",	"tegra30-dam.2",	NULL,   110,	0x3e0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("hda",	"tegra30-hda",		"hda",   125,	0x428,	108000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("hda2codec_2x",	"tegra30-hda",	"hda2codec",   111,	0x3e4,	48000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("hda2hdmi",	"tegra30-hda",		"hda2hdmi",	128,	0,	48000000,  mux_clk_m,			0),
+	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sbc5",	"spi_tegra.4",		NULL,	104,	0x3c8,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sbc6",	"spi_tegra.5",		NULL,	105,	0x3cc,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sata_oob",	"tegra_sata_oob",	NULL,	123,	0x420,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sata",	"tegra_sata",		NULL,	124,	0x424,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sata_cold",	"tegra_sata_cold",	NULL,	129,	0,	48000000,  mux_clk_m,			0),
+	PERIPH_CLK_EX("ndflash", "tegra_nand",		NULL,	13,	0x160,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71,	&tegra_nand_clk_ops),
+	PERIPH_CLK("ndspeed",	"tegra_nand_speed",	NULL,	80,	0x3f8,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("vde",	"vde",			NULL,	61,	0x1c8,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
+	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
+	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	127000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
+	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
+	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
+	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
+	PERIPH_CLK("i2c4",	"tegra-i2c.3",		NULL,	103,	0x3c4,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
+	PERIPH_CLK("i2c5",	"tegra-i2c.4",		NULL,	47,	0x128,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
+	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+	PERIPH_CLK_EX("vi",	"tegra_camera",		"vi",	20,	0x148,	425000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT,	&tegra_vi_clk_ops),
+	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+	PERIPH_CLK("3d2",       "3d2",			NULL,	98,	0x3b0,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET),
+	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
+	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
+	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	260000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
+	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK_EX("dtv",	"dtv",			NULL,	79,	0x1dc,	250000000, mux_clk_m,			0,		&tegra_dtv_clk_ops),
+	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8 | DIV_U71),
+	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	220000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
+	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
+	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("dsia",	"tegradc.0",		"dsia",	48,	0,	500000000, mux_plld_out0,		0),
+	PERIPH_CLK_EX("dsib",	"tegradc.1",		"dsib",	82,	0xd0,	500000000, mux_plld_out0_plld2_out0,	MUX | PLLD,	&tegra_dsib_clk_ops),
+	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	102000000, mux_pllp_out3,		0),
+	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
+	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
+
+	PERIPH_CLK("tsensor",	"tegra-tsensor",	NULL,	100,	0x3b8,	216000000, mux_pllp_pllc_clkm_clk32,	MUX | DIV_U71),
+	PERIPH_CLK("actmon",	"actmon",		NULL,	119,	0x3e8,	216000000, mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("extern1",	"extern1",		NULL,	120,	0x3ec,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
+	PERIPH_CLK("extern2",	"extern2",		NULL,	121,	0x3f0,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
+	PERIPH_CLK("extern3",	"extern3",		NULL,	122,	0x3f4,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
+	PERIPH_CLK("i2cslow",	"i2cslow",		NULL,	81,	0x3fc,	26000000,  mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("pcie",	"tegra-pcie",		"pcie",	70,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("afi",	"tegra-pcie",		"afi",	72,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("se",	"se",			NULL,	127,	0x42c,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)		\
+	{						\
+		.name	= _name,			\
+		.lookup	= {				\
+			.dev_id	= _dev,			\
+			.con_id		= _con,		\
+		},					\
+	}
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+	CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+	CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+	CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+	CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+	CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+	CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+	CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+	CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+	CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+	CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+	CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+	CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+	CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+	CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+	CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+	CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+	CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+	CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+	CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+	CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+	CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+	CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+	CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+	CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+	CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+	CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+	CLK_DUPLICATE("twd", "smp_twd", NULL),
+	CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+	CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+	CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+	CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+	CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+	CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+	CLK_DUPLICATE("dam0", NULL, "dam0"),
+	CLK_DUPLICATE("dam1", NULL, "dam1"),
+	CLK_DUPLICATE("dam2", NULL, "dam2"),
+	CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+	&tegra_clk_32k,
+	&tegra_clk_m,
+	&tegra_clk_m_div2,
+	&tegra_clk_m_div4,
+	&tegra_pll_ref,
+	&tegra_pll_m,
+	&tegra_pll_m_out1,
+	&tegra_pll_c,
+	&tegra_pll_c_out1,
+	&tegra_pll_p,
+	&tegra_pll_p_out1,
+	&tegra_pll_p_out2,
+	&tegra_pll_p_out3,
+	&tegra_pll_p_out4,
+	&tegra_pll_a,
+	&tegra_pll_a_out0,
+	&tegra_pll_d,
+	&tegra_pll_d_out0,
+	&tegra_pll_d2,
+	&tegra_pll_d2_out0,
+	&tegra_pll_u,
+	&tegra_pll_x,
+	&tegra_pll_x_out0,
+	&tegra_pll_e,
+	&tegra_clk_cclk_g,
+	&tegra_cml0_clk,
+	&tegra_cml1_clk,
+	&tegra_pciex_clk,
+	&tegra_clk_sclk,
+	&tegra_clk_blink,
+	&tegra30_clk_twd,
+};
+
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+	clk_init(c);
+	INIT_LIST_HEAD(&c->shared_bus_list);
+	if (!c->lookup.dev_id && !c->lookup.con_id)
+		c->lookup.con_id = c->name;
+	c->lookup.clk = c;
+	clkdev_add(&c->lookup);
+}
+
+void __init tegra30_init_clocks(void)
+{
+	int i;
+	struct clk *c;
+
+	for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+		tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+		tegra30_init_one_clock(&tegra_list_clks[i]);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+		if (!c) {
+			pr_err("%s: Unknown duplicate clock %s\n", __func__,
+				tegra_clk_duplicates[i].name);
+			continue;
+		}
+
+		tegra_clk_duplicates[i].lookup.clk = c;
+		clkdev_add(&tegra_clk_duplicates[i].lookup);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+		tegra30_init_one_clock(&tegra_sync_source_list[i]);
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+		tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+		tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+
+	init_clk_out_mux();
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+		tegra30_init_one_clock(&tegra_clk_out_list[i]);
+
+}
-- 
1.7.4.1



From pgaikwad at nvidia.com  Mon Aug  6 02:27:41 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:41 +0530
Subject: [PATCH v4 3/6] ARM: tegra: Rename tegra20 clock file
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-4-git-send-email-pgaikwad@nvidia.com>

Make the name consistent with other files.
s/tegra2/tegra20

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/mach-tegra/Makefile                       |    2 +-
 .../{tegra2_clocks.c => tegra20_clocks.c}          |    0
 2 files changed, 1 insertions(+), 1 deletions(-)
 rename arch/arm/mach-tegra/{tegra2_clocks.c => tegra20_clocks.c} (100%)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 655fcfc..f07f994 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,7 +12,7 @@ obj-y					+= powergate.o
 obj-y					+= apbio.o
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_CPU_IDLE)			+= sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
similarity index 100%
rename from arch/arm/mach-tegra/tegra2_clocks.c
rename to arch/arm/mach-tegra/tegra20_clocks.c
-- 
1.7.4.1



From pgaikwad at nvidia.com  Mon Aug  6 02:27:40 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:40 +0530
Subject: [PATCH v4 2/6] ARM: tegra20: Separate out clk ops and clk data
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-3-git-send-email-pgaikwad@nvidia.com>

Move clock initialization data to separate file. This is
required for migrating to generic clock framework if static
initialization is used.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/mach-tegra/Makefile              |    1 +
 arch/arm/mach-tegra/tegra20_clocks.h      |   37 +
 arch/arm/mach-tegra/tegra20_clocks_data.c |  941 +++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra2_clocks.c       | 1058 +----------------------------
 4 files changed, 995 insertions(+), 1042 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra20_clocks.h
 create mode 100644 arch/arm/mach-tegra/tegra20_clocks_data.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0b62a9b..655fcfc 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,6 +13,7 @@ obj-y					+= apbio.o
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 0000000..167058c
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA20_CLOCK_H
+#define __MACH_TEGRA20_CLOCK_H
+
+extern struct clk_ops tegra_pll_ops;
+extern struct clk_ops tegra_clk_m_ops;
+extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_pllx_ops;
+extern struct clk_ops tegra_plle_ops;
+extern struct clk_ops tegra_clk_double_ops;
+extern struct clk_ops tegra_cdev_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra_super_ops;
+extern struct clk_ops tegra_cpu_ops;
+extern struct clk_ops tegra_cop_ops;
+extern struct clk_ops tegra_bus_ops;
+extern struct clk_ops tegra_blink_clk_ops;
+extern struct clk_ops tegra_emc_clk_ops;
+extern struct clk_ops tegra_periph_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 0000000..24f45ff
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,941 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra20_clocks.h"
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+	.name = "clk_32k",
+	.rate = 32768,
+	.ops  = NULL,
+	.max_rate = 32768,
+};
+
+static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
+	{32768, 12000000, 366, 1, 1, 0},
+	{32768, 13000000, 397, 1, 1, 0},
+	{32768, 19200000, 586, 1, 1, 0},
+	{32768, 26000000, 793, 1, 1, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct clk tegra_pll_s = {
+	.name      = "pll_s",
+	.flags     = PLL_ALT_MISC_REG,
+	.ops       = &tegra_pll_ops,
+	.parent    = &tegra_clk_32k,
+	.max_rate  = 26000000,
+	.reg       = 0xf0,
+	.u.pll = {
+		.input_min = 32768,
+		.input_max = 32768,
+		.cf_min    = 0, /* FIXME */
+		.cf_max    = 0, /* FIXME */
+		.vco_min   = 12000000,
+		.vco_max   = 26000000,
+		.freq_table = tegra_pll_s_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk_mux_sel tegra_clk_m_sel[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ .input = &tegra_pll_s,  .value = 1},
+	{ NULL , 0},
+};
+
+static struct clk tegra_clk_m = {
+	.name      = "clk_m",
+	.flags     = ENABLE_ON_INIT,
+	.ops       = &tegra_clk_m_ops,
+	.inputs    = tegra_clk_m_sel,
+	.reg       = 0x1fc,
+	.reg_shift = 28,
+	.max_rate  = 26000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+	{ 12000000, 600000000, 600, 12, 1, 8 },
+	{ 13000000, 600000000, 600, 13, 1, 8 },
+	{ 19200000, 600000000, 500, 16, 1, 6 },
+	{ 26000000, 600000000, 600, 26, 1, 8 },
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+	.name      = "pll_c",
+	.flags	   = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x80,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 600000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_c_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_c_out1 = {
+	.name      = "pll_c_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_c,
+	.reg       = 0x84,
+	.reg_shift = 0,
+	.max_rate  = 600000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+	{ 12000000, 666000000, 666, 12, 1, 8},
+	{ 13000000, 666000000, 666, 13, 1, 8},
+	{ 19200000, 666000000, 555, 16, 1, 8},
+	{ 26000000, 666000000, 666, 26, 1, 8},
+	{ 12000000, 600000000, 600, 12, 1, 8},
+	{ 13000000, 600000000, 600, 13, 1, 8},
+	{ 19200000, 600000000, 375, 12, 1, 6},
+	{ 26000000, 600000000, 600, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+	.name      = "pll_m",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x90,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 800000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1200000000,
+		.freq_table = tegra_pll_m_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_m_out1 = {
+	.name      = "pll_m_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_m,
+	.reg       = 0x94,
+	.reg_shift = 0,
+	.max_rate  = 600000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+	{ 12000000, 216000000, 432, 12, 2, 8},
+	{ 13000000, 216000000, 432, 13, 2, 8},
+	{ 19200000, 216000000, 90,   4, 2, 1},
+	{ 26000000, 216000000, 432, 26, 2, 8},
+	{ 12000000, 432000000, 432, 12, 1, 8},
+	{ 13000000, 432000000, 432, 13, 1, 8},
+	{ 19200000, 432000000, 90,   4, 1, 1},
+	{ 26000000, 432000000, 432, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+	.name      = "pll_p",
+	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xa0,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 432000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_p_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_p_out1 = {
+	.name      = "pll_p_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 0,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out2 = {
+	.name      = "pll_p_out2",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 16,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out3 = {
+	.name      = "pll_p_out3",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 0,
+	.max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out4 = {
+	.name      = "pll_p_out4",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 16,
+	.max_rate  = 432000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+	{ 28800000, 56448000, 49, 25, 1, 1},
+	{ 28800000, 73728000, 64, 25, 1, 1},
+	{ 28800000, 24000000,  5,  6, 1, 1},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+	.name      = "pll_a",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xb0,
+	.parent    = &tegra_pll_p_out1,
+	.max_rate  = 73728000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1400000000,
+		.freq_table = tegra_pll_a_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk tegra_pll_a_out0 = {
+	.name      = "pll_a_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_a,
+	.reg       = 0xb4,
+	.reg_shift = 0,
+	.max_rate  = 73728000,
+};
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+	{ 12000000, 216000000, 216, 12, 1, 4},
+	{ 13000000, 216000000, 216, 13, 1, 4},
+	{ 19200000, 216000000, 135, 12, 1, 3},
+	{ 26000000, 216000000, 216, 26, 1, 4},
+
+	{ 12000000, 594000000, 594, 12, 1, 8},
+	{ 13000000, 594000000, 594, 13, 1, 8},
+	{ 19200000, 594000000, 495, 16, 1, 8},
+	{ 26000000, 594000000, 594, 26, 1, 8},
+
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+	.name      = "pll_d",
+	.flags     = PLL_HAS_CPCON | PLLD,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xd0,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 1000000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 40000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 40000000,
+		.vco_max   = 1000000000,
+		.freq_table = tegra_pll_d_freq_table,
+		.lock_delay = 1000,
+	},
+};
+
+static struct clk tegra_pll_d_out0 = {
+	.name      = "pll_d_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_2 | PLLD,
+	.parent    = &tegra_pll_d,
+	.max_rate  = 500000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+	{ 12000000, 480000000, 960, 12, 2, 0},
+	{ 13000000, 480000000, 960, 13, 2, 0},
+	{ 19200000, 480000000, 200, 4,  2, 0},
+	{ 26000000, 480000000, 960, 26, 2, 0},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+	.name      = "pll_u",
+	.flags     = PLLU,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xc0,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 480000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 40000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 480000000,
+		.vco_max   = 960000000,
+		.freq_table = tegra_pll_u_freq_table,
+		.lock_delay = 1000,
+	},
+};
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+	/* 1 GHz */
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+
+	/* 912 MHz */
+	{ 12000000, 912000000,  912,  12, 1, 12},
+	{ 13000000, 912000000,  912,  13, 1, 12},
+	{ 19200000, 912000000,  760,  16, 1, 8},
+	{ 26000000, 912000000,  912,  26, 1, 12},
+
+	/* 816 MHz */
+	{ 12000000, 816000000,  816,  12, 1, 12},
+	{ 13000000, 816000000,  816,  13, 1, 12},
+	{ 19200000, 816000000,  680,  16, 1, 8},
+	{ 26000000, 816000000,  816,  26, 1, 12},
+
+	/* 760 MHz */
+	{ 12000000, 760000000,  760,  12, 1, 12},
+	{ 13000000, 760000000,  760,  13, 1, 12},
+	{ 19200000, 760000000,  950,  24, 1, 8},
+	{ 26000000, 760000000,  760,  26, 1, 12},
+
+	/* 750 MHz */
+	{ 12000000, 750000000,  750,  12, 1, 12},
+	{ 13000000, 750000000,  750,  13, 1, 12},
+	{ 19200000, 750000000,  625,  16, 1, 8},
+	{ 26000000, 750000000,  750,  26, 1, 12},
+
+	/* 608 MHz */
+	{ 12000000, 608000000,  608,  12, 1, 12},
+	{ 13000000, 608000000,  608,  13, 1, 12},
+	{ 19200000, 608000000,  380,  12, 1, 8},
+	{ 26000000, 608000000,  608,  26, 1, 12},
+
+	/* 456 MHz */
+	{ 12000000, 456000000,  456,  12, 1, 12},
+	{ 13000000, 456000000,  456,  13, 1, 12},
+	{ 19200000, 456000000,  380,  16, 1, 8},
+	{ 26000000, 456000000,  456,  26, 1, 12},
+
+	/* 312 MHz */
+	{ 12000000, 312000000,  312,  12, 1, 12},
+	{ 13000000, 312000000,  312,  13, 1, 12},
+	{ 19200000, 312000000,  260,  16, 1, 8},
+	{ 26000000, 312000000,  312,  26, 1, 12},
+
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+	.name      = "pll_x",
+	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
+	.ops       = &tegra_pllx_ops,
+	.reg       = 0xe0,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 1000000000,
+	.u.pll = {
+		.input_min = 2000000,
+		.input_max = 31000000,
+		.cf_min    = 1000000,
+		.cf_max    = 6000000,
+		.vco_min   = 20000000,
+		.vco_max   = 1200000000,
+		.freq_table = tegra_pll_x_freq_table,
+		.lock_delay = 300,
+	},
+};
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+	{ 12000000, 100000000,  200,  24, 1, 0 },
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_e = {
+	.name      = "pll_e",
+	.flags	   = PLL_ALT_MISC_REG,
+	.ops       = &tegra_plle_ops,
+	.parent    = &tegra_clk_m,
+	.reg       = 0xe8,
+	.max_rate  = 100000000,
+	.u.pll = {
+		.input_min = 12000000,
+		.input_max = 12000000,
+		.freq_table = tegra_pll_e_freq_table,
+	},
+};
+
+static struct clk tegra_clk_d = {
+	.name      = "clk_d",
+	.flags     = PERIPH_NO_RESET,
+	.ops       = &tegra_clk_double_ops,
+	.reg       = 0x34,
+	.reg_shift = 12,
+	.parent    = &tegra_clk_m,
+	.max_rate  = 52000000,
+	.u.periph  = {
+		.clk_num = 90,
+	},
+};
+
+/* dap_mclk1, belongs to the cdev1 pingroup. */
+static struct clk tegra_clk_cdev1 = {
+	.name      = "cdev1",
+	.ops       = &tegra_cdev_clk_ops,
+	.rate      = 26000000,
+	.max_rate  = 26000000,
+	.u.periph  = {
+		.clk_num = 94,
+	},
+};
+
+/* dap_mclk2, belongs to the cdev2 pingroup. */
+static struct clk tegra_clk_cdev2 = {
+	.name      = "cdev2",
+	.ops       = &tegra_cdev_clk_ops,
+	.rate      = 26000000,
+	.max_rate  = 26000000,
+	.u.periph  = {
+		.clk_num   = 93,
+	},
+};
+
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+	const char *name;
+	int value;
+} mux_audio_sync_clk_sources[] = {
+	{ .name = "spdif_in", .value = 0 },
+	{ .name = "i2s1", .value = 1 },
+	{ .name = "i2s2", .value = 2 },
+	{ .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+	{ .name = "ac97", .value = 3 },
+	{ .name = "ext_audio_clk2", .value = 5 },
+	{ .name = "ext_audio_clk1", .value = 6 },
+	{ .name = "ext_vimclk", .value = 7 },
+#endif
+	{ NULL, 0 }
+};
+
+static struct clk tegra_clk_audio = {
+	.name      = "audio",
+	.inputs    = mux_audio_sync_clk,
+	.reg       = 0x38,
+	.max_rate  = 73728000,
+	.ops       = &tegra_audio_sync_clk_ops
+};
+
+static struct clk tegra_clk_audio_2x = {
+	.name      = "audio_2x",
+	.flags     = PERIPH_NO_RESET,
+	.max_rate  = 48000000,
+	.ops       = &tegra_clk_double_ops,
+	.reg       = 0x34,
+	.reg_shift = 8,
+	.parent    = &tegra_clk_audio,
+	.u.periph = {
+		.clk_num = 89,
+	},
+};
+
+static struct clk_lookup tegra_audio_clk_lookups[] = {
+	{ .con_id = "audio", .clk = &tegra_clk_audio },
+	{ .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
+};
+
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+
+static void init_audio_sync_clock_mux(void)
+{
+	int i;
+	struct clk_mux_sel *sel = mux_audio_sync_clk;
+	const struct audio_sources *src = mux_audio_sync_clk_sources;
+	struct clk_lookup *lookup;
+
+	for (i = 0; src->name; i++, sel++, src++) {
+		sel->input = tegra_get_clock_by_name(src->name);
+		if (!sel->input)
+			pr_err("%s: could not find clk %s\n", __func__,
+				src->name);
+		sel->value = src->value;
+	}
+
+	lookup = tegra_audio_clk_lookups;
+	for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+		clk_init(lookup->clk);
+		clkdev_add(lookup);
+	}
+}
+
+static struct clk_mux_sel mux_cclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c,	.value = 1},
+	{ .input = &tegra_clk_32k,	.value = 2},
+	{ .input = &tegra_pll_m,	.value = 3},
+	{ .input = &tegra_pll_p,	.value = 4},
+	{ .input = &tegra_pll_p_out4,	.value = 5},
+	{ .input = &tegra_pll_p_out3,	.value = 6},
+	{ .input = &tegra_clk_d,	.value = 7},
+	{ .input = &tegra_pll_x,	.value = 8},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_sclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c_out1,	.value = 1},
+	{ .input = &tegra_pll_p_out4,	.value = 2},
+	{ .input = &tegra_pll_p_out3,	.value = 3},
+	{ .input = &tegra_pll_p_out2,	.value = 4},
+	{ .input = &tegra_clk_d,	.value = 5},
+	{ .input = &tegra_clk_32k,	.value = 6},
+	{ .input = &tegra_pll_m_out1,	.value = 7},
+	{ NULL, 0},
+};
+
+static struct clk tegra_clk_cclk = {
+	.name	= "cclk",
+	.inputs	= mux_cclk,
+	.reg	= 0x20,
+	.ops	= &tegra_super_ops,
+	.max_rate = 1000000000,
+};
+
+static struct clk tegra_clk_sclk = {
+	.name	= "sclk",
+	.inputs	= mux_sclk,
+	.reg	= 0x28,
+	.ops	= &tegra_super_ops,
+	.max_rate = 240000000,
+	.min_rate = 120000000,
+};
+
+static struct clk tegra_clk_virtual_cpu = {
+	.name      = "cpu",
+	.parent    = &tegra_clk_cclk,
+	.ops       = &tegra_cpu_ops,
+	.max_rate  = 1000000000,
+	.u.cpu = {
+		.main      = &tegra_pll_x,
+		.backup    = &tegra_pll_p,
+	},
+};
+
+static struct clk tegra_clk_cop = {
+	.name      = "cop",
+	.parent    = &tegra_clk_sclk,
+	.ops       = &tegra_cop_ops,
+	.max_rate  = 240000000,
+};
+
+static struct clk tegra_clk_hclk = {
+	.name		= "hclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_sclk,
+	.reg		= 0x30,
+	.reg_shift	= 4,
+	.ops		= &tegra_bus_ops,
+	.max_rate       = 240000000,
+};
+
+static struct clk tegra_clk_pclk = {
+	.name		= "pclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_hclk,
+	.reg		= 0x30,
+	.reg_shift	= 0,
+	.ops		= &tegra_bus_ops,
+	.max_rate       = 120000000,
+};
+
+static struct clk tegra_clk_blink = {
+	.name		= "blink",
+	.parent		= &tegra_clk_32k,
+	.reg		= 0x40,
+	.ops		= &tegra_blink_clk_ops,
+	.max_rate	= 32768,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_pll_a_out0, .value = 3},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+	{ .input = &tegra_pll_p, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_m, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
+	{.input = &tegra_pll_a_out0, .value = 0},
+	{.input = &tegra_clk_audio_2x, .value = 1},
+	{.input = &tegra_pll_p, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+	{.input = &tegra_pll_p, .value = 0},
+	{.input = &tegra_pll_d_out0, .value = 1},
+	{.input = &tegra_pll_c, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_clk_audio,     .value = 2},
+	{.input = &tegra_clk_m,     .value = 3},
+	{.input = &tegra_clk_32k,   .value = 4},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_pll_m,     .value = 2},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+	{ .input = &tegra_clk_m, .value = 0},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+	{ .input = &tegra_pll_p_out3, .value = 0},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_plld[] = {
+	{ .input = &tegra_pll_d, .value = 0},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ NULL, 0},
+};
+
+static struct clk_mux_sel mux_pclk[] = {
+	{ .input = &tegra_clk_pclk, .value = 0},
+	{ NULL, 0},
+};
+
+static struct clk tegra_clk_emc = {
+	.name = "emc",
+	.ops = &tegra_emc_clk_ops,
+	.reg = 0x19c,
+	.max_rate = 800000000,
+	.inputs = mux_pllm_pllc_pllp_clkm,
+	.flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+	.u.periph = {
+		.clk_num = 57,
+	},
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+		.ops       = &tegra_periph_clk_ops,	\
+		.reg       = _reg,			\
+		.inputs    = _inputs,			\
+		.flags     = _flags,			\
+		.max_rate  = _max,			\
+		.u.periph = {				\
+			.clk_num   = _clk_num,		\
+		},					\
+	}
+
+#define SHARED_CLK(_name, _dev, _con, _parent)		\
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id    = _con,		\
+		},					\
+		.ops       = &tegra_clk_shared_bus_ops,	\
+		.parent = _parent,			\
+	}
+
+static struct clk tegra_list_clks[] = {
+	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0),
+	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET),
+	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("i2s1",	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2s2",	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
+	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
+	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
+	PERIPH_CLK("vde",	"tegra-avp",		"vde",	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
+	/* FIXME: what is la? */
+	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
+	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
+	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	250000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
+	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
+	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	500000000, mux_plld,			0), /* scales with voltage */
+	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	72000000,  mux_pllp_out3,		0),
+	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
+	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
+	PERIPH_CLK("pex",       NULL,			"pex",  70,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
+	PERIPH_CLK("afi",       NULL,			"afi",  72,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
+	PERIPH_CLK("pcie_xclk", NULL,		  "pcie_xclk",  74,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
+
+	SHARED_CLK("avp.sclk",	"tegra-avp",		"sclk",	&tegra_clk_sclk),
+	SHARED_CLK("avp.emc",	"tegra-avp",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("cpu.emc",	"cpu",			"emc",	&tegra_clk_emc),
+	SHARED_CLK("disp1.emc",	"tegradc.0",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("disp2.emc",	"tegradc.1",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("hdmi.emc",	"hdmi",			"emc",	&tegra_clk_emc),
+	SHARED_CLK("host.emc",	"tegra_grhost",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("usbd.emc",	"fsl-tegra-udc",	"emc",	&tegra_clk_emc),
+	SHARED_CLK("usb1.emc",	"tegra-ehci.0",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("usb2.emc",	"tegra-ehci.1",		"emc",	&tegra_clk_emc),
+	SHARED_CLK("usb3.emc",	"tegra-ehci.2",		"emc",	&tegra_clk_emc),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)		\
+	{						\
+		.name	= _name,			\
+		.lookup	= {				\
+			.dev_id	= _dev,			\
+			.con_id		= _con,		\
+		},					\
+	}
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+static struct clk_duplicate tegra_clk_duplicates[] = {
+	CLK_DUPLICATE("uarta",	"serial8250.0",	NULL),
+	CLK_DUPLICATE("uartb",	"serial8250.1",	NULL),
+	CLK_DUPLICATE("uartc",	"serial8250.2",	NULL),
+	CLK_DUPLICATE("uartd",	"serial8250.3",	NULL),
+	CLK_DUPLICATE("uarte",	"serial8250.4",	NULL),
+	CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
+	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
+	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
+	CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
+	CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
+	CLK_DUPLICATE("cop", "tegra-avp", "cop"),
+	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+};
+
+#define CLK(dev, con, ck)	\
+	{			\
+		.dev_id = dev,	\
+		.con_id = con,	\
+		.clk = ck,	\
+	}
+
+static struct clk *tegra_ptr_clks[] = {
+	&tegra_clk_32k,
+	&tegra_pll_s,
+	&tegra_clk_m,
+	&tegra_pll_m,
+	&tegra_pll_m_out1,
+	&tegra_pll_c,
+	&tegra_pll_c_out1,
+	&tegra_pll_p,
+	&tegra_pll_p_out1,
+	&tegra_pll_p_out2,
+	&tegra_pll_p_out3,
+	&tegra_pll_p_out4,
+	&tegra_pll_a,
+	&tegra_pll_a_out0,
+	&tegra_pll_d,
+	&tegra_pll_d_out0,
+	&tegra_pll_u,
+	&tegra_pll_x,
+	&tegra_pll_e,
+	&tegra_clk_cclk,
+	&tegra_clk_sclk,
+	&tegra_clk_hclk,
+	&tegra_clk_pclk,
+	&tegra_clk_d,
+	&tegra_clk_cdev1,
+	&tegra_clk_cdev2,
+	&tegra_clk_virtual_cpu,
+	&tegra_clk_blink,
+	&tegra_clk_cop,
+	&tegra_clk_emc,
+};
+
+static void tegra2_init_one_clock(struct clk *c)
+{
+	clk_init(c);
+	INIT_LIST_HEAD(&c->shared_bus_list);
+	if (!c->lookup.dev_id && !c->lookup.con_id)
+		c->lookup.con_id = c->name;
+	c->lookup.clk = c;
+	clkdev_add(&c->lookup);
+}
+
+void __init tegra2_init_clocks(void)
+{
+	int i;
+	struct clk *c;
+
+	for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+		tegra2_init_one_clock(tegra_ptr_clks[i]);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+		tegra2_init_one_clock(&tegra_list_clks[i]);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+		if (!c) {
+			pr_err("%s: Unknown duplicate clock %s\n", __func__,
+				tegra_clk_duplicates[i].name);
+			continue;
+		}
+
+		tegra_clk_duplicates[i].lookup.clk = c;
+		clkdev_add(&tegra_clk_duplicates[i].lookup);
+	}
+
+	init_audio_sync_clock_mux();
+}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 83ccb85..4a32030 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -274,7 +274,7 @@ static void tegra2_clk_m_disable(struct clk *c)
 	BUG();
 }
 
-static struct clk_ops tegra_clk_m_ops = {
+struct clk_ops tegra_clk_m_ops = {
 	.init		= tegra2_clk_m_init,
 	.enable		= tegra2_clk_m_enable,
 	.disable	= tegra2_clk_m_disable,
@@ -364,7 +364,7 @@ static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
 	return clk_set_rate(c->parent, rate);
 }
 
-static struct clk_ops tegra_super_ops = {
+struct clk_ops tegra_super_ops = {
 	.init			= tegra2_super_clk_init,
 	.enable			= tegra2_super_clk_enable,
 	.disable		= tegra2_super_clk_disable,
@@ -431,7 +431,7 @@ out:
 	return ret;
 }
 
-static struct clk_ops tegra_cpu_ops = {
+struct clk_ops tegra_cpu_ops = {
 	.init     = tegra2_cpu_clk_init,
 	.enable   = tegra2_cpu_clk_enable,
 	.disable  = tegra2_cpu_clk_disable,
@@ -448,7 +448,7 @@ static void tegra2_cop_clk_reset(struct clk *c, bool assert)
 	clk_writel(1 << 1, reg);
 }
 
-static struct clk_ops tegra_cop_ops = {
+struct clk_ops tegra_cop_ops = {
 	.reset    = tegra2_cop_clk_reset,
 };
 
@@ -519,7 +519,7 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
 	return ret;
 }
 
-static struct clk_ops tegra_bus_ops = {
+struct clk_ops tegra_bus_ops = {
 	.init			= tegra2_bus_clk_init,
 	.enable			= tegra2_bus_clk_enable,
 	.disable		= tegra2_bus_clk_disable,
@@ -601,7 +601,7 @@ static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra_blink_clk_ops = {
+struct clk_ops tegra_blink_clk_ops = {
 	.init			= &tegra2_blink_clk_init,
 	.enable			= &tegra2_blink_clk_enable,
 	.disable		= &tegra2_blink_clk_disable,
@@ -711,7 +711,7 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_pll_ops = {
+struct clk_ops tegra_pll_ops = {
 	.init			= tegra2_pll_clk_init,
 	.enable			= tegra2_pll_clk_enable,
 	.disable		= tegra2_pll_clk_disable,
@@ -726,7 +726,7 @@ static void tegra2_pllx_clk_init(struct clk *c)
 		c->max_rate = 750000000;
 }
 
-static struct clk_ops tegra_pllx_ops = {
+struct clk_ops tegra_pllx_ops = {
 	.init     = tegra2_pllx_clk_init,
 	.enable   = tegra2_pll_clk_enable,
 	.disable  = tegra2_pll_clk_disable,
@@ -752,7 +752,7 @@ static int tegra2_plle_clk_enable(struct clk *c)
 	return 0;
 }
 
-static struct clk_ops tegra_plle_ops = {
+struct clk_ops tegra_plle_ops = {
 	.init       = tegra2_pll_clk_init,
 	.enable     = tegra2_plle_clk_enable,
 	.set_rate   = tegra2_pll_clk_set_rate,
@@ -895,7 +895,7 @@ static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_pll_div_ops = {
+struct clk_ops tegra_pll_div_ops = {
 	.init			= tegra2_pll_div_clk_init,
 	.enable			= tegra2_pll_div_clk_enable,
 	.disable		= tegra2_pll_div_clk_disable,
@@ -1128,7 +1128,7 @@ static long tegra2_periph_clk_round_rate(struct clk *c,
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_periph_clk_ops = {
+struct clk_ops tegra_periph_clk_ops = {
 	.init			= &tegra2_periph_clk_init,
 	.enable			= &tegra2_periph_clk_enable,
 	.disable		= &tegra2_periph_clk_disable,
@@ -1217,7 +1217,7 @@ static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
 	return ret;
 }
 
-static struct clk_ops tegra_emc_clk_ops = {
+struct clk_ops tegra_emc_clk_ops = {
 	.init			= &tegra2_emc_clk_init,
 	.enable			= &tegra2_periph_clk_enable,
 	.disable		= &tegra2_periph_clk_disable,
@@ -1251,7 +1251,7 @@ static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-static struct clk_ops tegra_clk_double_ops = {
+struct clk_ops tegra_clk_double_ops = {
 	.init			= &tegra2_clk_double_init,
 	.enable			= &tegra2_periph_clk_enable,
 	.disable		= &tegra2_periph_clk_disable,
@@ -1310,7 +1310,7 @@ static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
 	return -EINVAL;
 }
 
-static struct clk_ops tegra_audio_sync_clk_ops = {
+struct clk_ops tegra_audio_sync_clk_ops = {
 	.init       = tegra2_audio_sync_clk_init,
 	.enable     = tegra2_audio_sync_clk_enable,
 	.disable    = tegra2_audio_sync_clk_disable,
@@ -1349,7 +1349,7 @@ static void tegra2_cdev_clk_disable(struct clk *c)
 		CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
 }
 
-static struct clk_ops tegra_cdev_clk_ops = {
+struct clk_ops tegra_cdev_clk_ops = {
 	.init			= &tegra2_cdev_clk_init,
 	.enable			= &tegra2_cdev_clk_enable,
 	.disable		= &tegra2_cdev_clk_disable,
@@ -1449,1036 +1449,10 @@ static void tegra_clk_shared_bus_disable(struct clk *c)
 	spin_unlock_irqrestore(&c->parent->spinlock, flags);
 }
 
-static struct clk_ops tegra_clk_shared_bus_ops = {
+struct clk_ops tegra_clk_shared_bus_ops = {
 	.init = tegra_clk_shared_bus_init,
 	.enable = tegra_clk_shared_bus_enable,
 	.disable = tegra_clk_shared_bus_disable,
 	.set_rate = tegra_clk_shared_bus_set_rate,
 	.round_rate = tegra_clk_shared_bus_round_rate,
 };
-
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-	.name = "clk_32k",
-	.rate = 32768,
-	.ops  = NULL,
-	.max_rate = 32768,
-};
-
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
-	{32768, 12000000, 366, 1, 1, 0},
-	{32768, 13000000, 397, 1, 1, 0},
-	{32768, 19200000, 586, 1, 1, 0},
-	{32768, 26000000, 793, 1, 1, 0},
-	{0, 0, 0, 0, 0, 0},
-};
-
-static struct clk tegra_pll_s = {
-	.name      = "pll_s",
-	.flags     = PLL_ALT_MISC_REG,
-	.ops       = &tegra_pll_ops,
-	.parent    = &tegra_clk_32k,
-	.max_rate  = 26000000,
-	.reg       = 0xf0,
-	.u.pll = {
-		.input_min = 32768,
-		.input_max = 32768,
-		.cf_min    = 0, /* FIXME */
-		.cf_max    = 0, /* FIXME */
-		.vco_min   = 12000000,
-		.vco_max   = 26000000,
-		.freq_table = tegra_pll_s_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk_mux_sel tegra_clk_m_sel[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ .input = &tegra_pll_s,  .value = 1},
-	{ NULL , 0},
-};
-
-static struct clk tegra_clk_m = {
-	.name      = "clk_m",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra_clk_m_ops,
-	.inputs    = tegra_clk_m_sel,
-	.reg       = 0x1fc,
-	.reg_shift = 28,
-	.max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-	{ 12000000, 600000000, 600, 12, 1, 8 },
-	{ 13000000, 600000000, 600, 13, 1, 8 },
-	{ 19200000, 600000000, 500, 16, 1, 6 },
-	{ 26000000, 600000000, 600, 26, 1, 8 },
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-	.name      = "pll_c",
-	.flags	   = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x80,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 600000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_c_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_c_out1 = {
-	.name      = "pll_c_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_c,
-	.reg       = 0x84,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-	{ 12000000, 666000000, 666, 12, 1, 8},
-	{ 13000000, 666000000, 666, 13, 1, 8},
-	{ 19200000, 666000000, 555, 16, 1, 8},
-	{ 26000000, 666000000, 666, 26, 1, 8},
-	{ 12000000, 600000000, 600, 12, 1, 8},
-	{ 13000000, 600000000, 600, 13, 1, 8},
-	{ 19200000, 600000000, 375, 12, 1, 6},
-	{ 26000000, 600000000, 600, 26, 1, 8},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-	.name      = "pll_m",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x90,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 800000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_m_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_m_out1 = {
-	.name      = "pll_m_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_m,
-	.reg       = 0x94,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-	{ 12000000, 216000000, 432, 12, 2, 8},
-	{ 13000000, 216000000, 432, 13, 2, 8},
-	{ 19200000, 216000000, 90,   4, 2, 1},
-	{ 26000000, 216000000, 432, 26, 2, 8},
-	{ 12000000, 432000000, 432, 12, 1, 8},
-	{ 13000000, 432000000, 432, 13, 1, 8},
-	{ 19200000, 432000000, 90,   4, 1, 1},
-	{ 26000000, 432000000, 432, 26, 1, 8},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-	.name      = "pll_p",
-	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xa0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 432000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_p_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_p_out1 = {
-	.name      = "pll_p_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-	.name      = "pll_p_out2",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-	.name      = "pll_p_out3",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-	.name      = "pll_p_out4",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-	{ 28800000, 56448000, 49, 25, 1, 1},
-	{ 28800000, 73728000, 64, 25, 1, 1},
-	{ 28800000, 24000000,  5,  6, 1, 1},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-	.name      = "pll_a",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xb0,
-	.parent    = &tegra_pll_p_out1,
-	.max_rate  = 73728000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_a_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_a_out0 = {
-	.name      = "pll_a_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_a,
-	.reg       = 0xb4,
-	.reg_shift = 0,
-	.max_rate  = 73728000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-	{ 12000000, 216000000, 216, 12, 1, 4},
-	{ 13000000, 216000000, 216, 13, 1, 4},
-	{ 19200000, 216000000, 135, 12, 1, 3},
-	{ 26000000, 216000000, 216, 26, 1, 4},
-
-	{ 12000000, 594000000, 594, 12, 1, 8},
-	{ 13000000, 594000000, 594, 13, 1, 8},
-	{ 19200000, 594000000, 495, 16, 1, 8},
-	{ 26000000, 594000000, 594, 26, 1, 8},
-
-	{ 12000000, 1000000000, 1000, 12, 1, 12},
-	{ 13000000, 1000000000, 1000, 13, 1, 12},
-	{ 19200000, 1000000000, 625,  12, 1, 8},
-	{ 26000000, 1000000000, 1000, 26, 1, 12},
-
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-	.name      = "pll_d",
-	.flags     = PLL_HAS_CPCON | PLLD,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xd0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
-
-static struct clk tegra_pll_d_out0 = {
-	.name      = "pll_d_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d,
-	.max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-	{ 12000000, 480000000, 960, 12, 2, 0},
-	{ 13000000, 480000000, 960, 13, 2, 0},
-	{ 19200000, 480000000, 200, 4,  2, 0},
-	{ 26000000, 480000000, 960, 26, 2, 0},
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-	.name      = "pll_u",
-	.flags     = PLLU,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xc0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 480000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 480000000,
-		.vco_max   = 960000000,
-		.freq_table = tegra_pll_u_freq_table,
-		.lock_delay = 1000,
-	},
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-	/* 1 GHz */
-	{ 12000000, 1000000000, 1000, 12, 1, 12},
-	{ 13000000, 1000000000, 1000, 13, 1, 12},
-	{ 19200000, 1000000000, 625,  12, 1, 8},
-	{ 26000000, 1000000000, 1000, 26, 1, 12},
-
-	/* 912 MHz */
-	{ 12000000, 912000000,  912,  12, 1, 12},
-	{ 13000000, 912000000,  912,  13, 1, 12},
-	{ 19200000, 912000000,  760,  16, 1, 8},
-	{ 26000000, 912000000,  912,  26, 1, 12},
-
-	/* 816 MHz */
-	{ 12000000, 816000000,  816,  12, 1, 12},
-	{ 13000000, 816000000,  816,  13, 1, 12},
-	{ 19200000, 816000000,  680,  16, 1, 8},
-	{ 26000000, 816000000,  816,  26, 1, 12},
-
-	/* 760 MHz */
-	{ 12000000, 760000000,  760,  12, 1, 12},
-	{ 13000000, 760000000,  760,  13, 1, 12},
-	{ 19200000, 760000000,  950,  24, 1, 8},
-	{ 26000000, 760000000,  760,  26, 1, 12},
-
-	/* 750 MHz */
-	{ 12000000, 750000000,  750,  12, 1, 12},
-	{ 13000000, 750000000,  750,  13, 1, 12},
-	{ 19200000, 750000000,  625,  16, 1, 8},
-	{ 26000000, 750000000,  750,  26, 1, 12},
-
-	/* 608 MHz */
-	{ 12000000, 608000000,  608,  12, 1, 12},
-	{ 13000000, 608000000,  608,  13, 1, 12},
-	{ 19200000, 608000000,  380,  12, 1, 8},
-	{ 26000000, 608000000,  608,  26, 1, 12},
-
-	/* 456 MHz */
-	{ 12000000, 456000000,  456,  12, 1, 12},
-	{ 13000000, 456000000,  456,  13, 1, 12},
-	{ 19200000, 456000000,  380,  16, 1, 8},
-	{ 26000000, 456000000,  456,  26, 1, 12},
-
-	/* 312 MHz */
-	{ 12000000, 312000000,  312,  12, 1, 12},
-	{ 13000000, 312000000,  312,  13, 1, 12},
-	{ 19200000, 312000000,  260,  16, 1, 8},
-	{ 26000000, 312000000,  312,  26, 1, 12},
-
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-	.name      = "pll_x",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-	.ops       = &tegra_pllx_ops,
-	.reg       = 0xe0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_x_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-	{ 12000000, 100000000,  200,  24, 1, 0 },
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-	.name      = "pll_e",
-	.flags	   = PLL_ALT_MISC_REG,
-	.ops       = &tegra_plle_ops,
-	.parent    = &tegra_clk_m,
-	.reg       = 0xe8,
-	.max_rate  = 100000000,
-	.u.pll = {
-		.input_min = 12000000,
-		.input_max = 12000000,
-		.freq_table = tegra_pll_e_freq_table,
-	},
-};
-
-static struct clk tegra_clk_d = {
-	.name      = "clk_d",
-	.flags     = PERIPH_NO_RESET,
-	.ops       = &tegra_clk_double_ops,
-	.reg       = 0x34,
-	.reg_shift = 12,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 52000000,
-	.u.periph  = {
-		.clk_num = 90,
-	},
-};
-
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
-	.name      = "cdev1",
-	.ops       = &tegra_cdev_clk_ops,
-	.rate      = 26000000,
-	.max_rate  = 26000000,
-	.u.periph  = {
-		.clk_num = 94,
-	},
-};
-
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
-	.name      = "cdev2",
-	.ops       = &tegra_cdev_clk_ops,
-	.rate      = 26000000,
-	.max_rate  = 26000000,
-	.u.periph  = {
-		.clk_num   = 93,
-	},
-};
-
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
-	const char *name;
-	int value;
-} mux_audio_sync_clk_sources[] = {
-	{ .name = "spdif_in", .value = 0 },
-	{ .name = "i2s1", .value = 1 },
-	{ .name = "i2s2", .value = 2 },
-	{ .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
-	{ .name = "ac97", .value = 3 },
-	{ .name = "ext_audio_clk2", .value = 5 },
-	{ .name = "ext_audio_clk1", .value = 6 },
-	{ .name = "ext_vimclk", .value = 7 },
-#endif
-	{ NULL, 0 }
-};
-
-static struct clk tegra_clk_audio = {
-	.name      = "audio",
-	.inputs    = mux_audio_sync_clk,
-	.reg       = 0x38,
-	.max_rate  = 73728000,
-	.ops       = &tegra_audio_sync_clk_ops
-};
-
-static struct clk tegra_clk_audio_2x = {
-	.name      = "audio_2x",
-	.flags     = PERIPH_NO_RESET,
-	.max_rate  = 48000000,
-	.ops       = &tegra_clk_double_ops,
-	.reg       = 0x34,
-	.reg_shift = 8,
-	.parent    = &tegra_clk_audio,
-	.u.periph = {
-		.clk_num = 89,
-	},
-};
-
-static struct clk_lookup tegra_audio_clk_lookups[] = {
-	{ .con_id = "audio", .clk = &tegra_clk_audio },
-	{ .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
-};
-
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-
-static void init_audio_sync_clock_mux(void)
-{
-	int i;
-	struct clk_mux_sel *sel = mux_audio_sync_clk;
-	const struct audio_sources *src = mux_audio_sync_clk_sources;
-	struct clk_lookup *lookup;
-
-	for (i = 0; src->name; i++, sel++, src++) {
-		sel->input = tegra_get_clock_by_name(src->name);
-		if (!sel->input)
-			pr_err("%s: could not find clk %s\n", __func__,
-				src->name);
-		sel->value = src->value;
-	}
-
-	lookup = tegra_audio_clk_lookups;
-	for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-		clk_init(lookup->clk);
-		clkdev_add(lookup);
-	}
-}
-
-static struct clk_mux_sel mux_cclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c,	.value = 1},
-	{ .input = &tegra_clk_32k,	.value = 2},
-	{ .input = &tegra_pll_m,	.value = 3},
-	{ .input = &tegra_pll_p,	.value = 4},
-	{ .input = &tegra_pll_p_out4,	.value = 5},
-	{ .input = &tegra_pll_p_out3,	.value = 6},
-	{ .input = &tegra_clk_d,	.value = 7},
-	{ .input = &tegra_pll_x,	.value = 8},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_sclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c_out1,	.value = 1},
-	{ .input = &tegra_pll_p_out4,	.value = 2},
-	{ .input = &tegra_pll_p_out3,	.value = 3},
-	{ .input = &tegra_pll_p_out2,	.value = 4},
-	{ .input = &tegra_clk_d,	.value = 5},
-	{ .input = &tegra_clk_32k,	.value = 6},
-	{ .input = &tegra_pll_m_out1,	.value = 7},
-	{ NULL, 0},
-};
-
-static struct clk tegra_clk_cclk = {
-	.name	= "cclk",
-	.inputs	= mux_cclk,
-	.reg	= 0x20,
-	.ops	= &tegra_super_ops,
-	.max_rate = 1000000000,
-};
-
-static struct clk tegra_clk_sclk = {
-	.name	= "sclk",
-	.inputs	= mux_sclk,
-	.reg	= 0x28,
-	.ops	= &tegra_super_ops,
-	.max_rate = 240000000,
-	.min_rate = 120000000,
-};
-
-static struct clk tegra_clk_virtual_cpu = {
-	.name      = "cpu",
-	.parent    = &tegra_clk_cclk,
-	.ops       = &tegra_cpu_ops,
-	.max_rate  = 1000000000,
-	.u.cpu = {
-		.main      = &tegra_pll_x,
-		.backup    = &tegra_pll_p,
-	},
-};
-
-static struct clk tegra_clk_cop = {
-	.name      = "cop",
-	.parent    = &tegra_clk_sclk,
-	.ops       = &tegra_cop_ops,
-	.max_rate  = 240000000,
-};
-
-static struct clk tegra_clk_hclk = {
-	.name		= "hclk",
-	.flags		= DIV_BUS,
-	.parent		= &tegra_clk_sclk,
-	.reg		= 0x30,
-	.reg_shift	= 4,
-	.ops		= &tegra_bus_ops,
-	.max_rate       = 240000000,
-};
-
-static struct clk tegra_clk_pclk = {
-	.name		= "pclk",
-	.flags		= DIV_BUS,
-	.parent		= &tegra_clk_hclk,
-	.reg		= 0x30,
-	.reg_shift	= 0,
-	.ops		= &tegra_bus_ops,
-	.max_rate       = 120000000,
-};
-
-static struct clk tegra_clk_blink = {
-	.name		= "blink",
-	.parent		= &tegra_clk_32k,
-	.reg		= 0x40,
-	.ops		= &tegra_blink_clk_ops,
-	.max_rate	= 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_pll_a_out0, .value = 3},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_m, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
-	{.input = &tegra_pll_a_out0, .value = 0},
-	{.input = &tegra_clk_audio_2x, .value = 1},
-	{.input = &tegra_pll_p, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_d_out0, .value = 1},
-	{.input = &tegra_pll_c, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_audio,     .value = 2},
-	{.input = &tegra_clk_m,     .value = 3},
-	{.input = &tegra_clk_32k,   .value = 4},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_pll_m,     .value = 2},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-	{ .input = &tegra_clk_m, .value = 0},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-	{ .input = &tegra_pll_p_out3, .value = 0},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_plld[] = {
-	{ .input = &tegra_pll_d, .value = 0},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_pclk[] = {
-	{ .input = &tegra_clk_pclk, .value = 0},
-	{ NULL, 0},
-};
-
-static struct clk tegra_clk_emc = {
-	.name = "emc",
-	.ops = &tegra_emc_clk_ops,
-	.reg = 0x19c,
-	.max_rate = 800000000,
-	.inputs = mux_pllm_pllc_pllp_clkm,
-	.flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
-	.u.periph = {
-		.clk_num = 57,
-	},
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
-		},					\
-		.ops       = &tegra_periph_clk_ops,	\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
-		},					\
-	}
-
-#define SHARED_CLK(_name, _dev, _con, _parent)		\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id    = _con,		\
-		},					\
-		.ops       = &tegra_clk_shared_bus_ops,	\
-		.parent = _parent,			\
-	}
-
-static struct clk tegra_list_clks[] = {
-	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0),
-	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET),
-	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("i2s1",	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("i2s2",	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
-	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("vde",	"tegra-avp",		"vde",	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
-	/* FIXME: what is la? */
-	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	250000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
-	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
-	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	500000000, mux_plld,			0), /* scales with voltage */
-	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	72000000,  mux_pllp_out3,		0),
-	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
-	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
-	PERIPH_CLK("pex",       NULL,			"pex",  70,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-	PERIPH_CLK("afi",       NULL,			"afi",  72,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-	PERIPH_CLK("pcie_xclk", NULL,		  "pcie_xclk",  74,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-
-	SHARED_CLK("avp.sclk",	"tegra-avp",		"sclk",	&tegra_clk_sclk),
-	SHARED_CLK("avp.emc",	"tegra-avp",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("cpu.emc",	"cpu",			"emc",	&tegra_clk_emc),
-	SHARED_CLK("disp1.emc",	"tegradc.0",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("disp2.emc",	"tegradc.1",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("hdmi.emc",	"hdmi",			"emc",	&tegra_clk_emc),
-	SHARED_CLK("host.emc",	"tegra_grhost",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usbd.emc",	"fsl-tegra-udc",	"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb1.emc",	"tegra-ehci.0",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb2.emc",	"tegra-ehci.1",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb3.emc",	"tegra-ehci.2",		"emc",	&tegra_clk_emc),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)		\
-	{						\
-		.name	= _name,			\
-		.lookup	= {				\
-			.dev_id	= _dev,			\
-			.con_id		= _con,		\
-		},					\
-	}
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
-	CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-	CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-	CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-	CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-	CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-	CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
-	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
-	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-	CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
-	CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
-	CLK_DUPLICATE("cop", "tegra-avp", "cop"),
-	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-};
-
-#define CLK(dev, con, ck)	\
-	{			\
-		.dev_id = dev,	\
-		.con_id = con,	\
-		.clk = ck,	\
-	}
-
-static struct clk *tegra_ptr_clks[] = {
-	&tegra_clk_32k,
-	&tegra_pll_s,
-	&tegra_clk_m,
-	&tegra_pll_m,
-	&tegra_pll_m_out1,
-	&tegra_pll_c,
-	&tegra_pll_c_out1,
-	&tegra_pll_p,
-	&tegra_pll_p_out1,
-	&tegra_pll_p_out2,
-	&tegra_pll_p_out3,
-	&tegra_pll_p_out4,
-	&tegra_pll_a,
-	&tegra_pll_a_out0,
-	&tegra_pll_d,
-	&tegra_pll_d_out0,
-	&tegra_pll_u,
-	&tegra_pll_x,
-	&tegra_pll_e,
-	&tegra_clk_cclk,
-	&tegra_clk_sclk,
-	&tegra_clk_hclk,
-	&tegra_clk_pclk,
-	&tegra_clk_d,
-	&tegra_clk_cdev1,
-	&tegra_clk_cdev2,
-	&tegra_clk_virtual_cpu,
-	&tegra_clk_blink,
-	&tegra_clk_cop,
-	&tegra_clk_emc,
-};
-
-static void tegra2_init_one_clock(struct clk *c)
-{
-	clk_init(c);
-	INIT_LIST_HEAD(&c->shared_bus_list);
-	if (!c->lookup.dev_id && !c->lookup.con_id)
-		c->lookup.con_id = c->name;
-	c->lookup.clk = c;
-	clkdev_add(&c->lookup);
-}
-
-void __init tegra2_init_clocks(void)
-{
-	int i;
-	struct clk *c;
-
-	for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-		tegra2_init_one_clock(tegra_ptr_clks[i]);
-
-	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-		tegra2_init_one_clock(&tegra_list_clks[i]);
-
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-		if (!c) {
-			pr_err("%s: Unknown duplicate clock %s\n", __func__,
-				tegra_clk_duplicates[i].name);
-			continue;
-		}
-
-		tegra_clk_duplicates[i].lookup.clk = c;
-		clkdev_add(&tegra_clk_duplicates[i].lookup);
-	}
-
-	init_audio_sync_clock_mux();
-}
-
-#ifdef CONFIG_PM
-static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
-			   PERIPH_CLK_SOURCE_NUM + 22];
-
-void tegra_clk_suspend(void)
-{
-	unsigned long off, i;
-	u32 *ctx = clk_rst_suspend;
-
-	*ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
-	*ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
-	*ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-	*ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
-	*ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-	*ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
-	*ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-	*ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
-	*ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-	*ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
-	*ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-
-	*ctx++ = clk_readl(tegra_pll_m_out1.reg);
-	*ctx++ = clk_readl(tegra_pll_a_out0.reg);
-	*ctx++ = clk_readl(tegra_pll_c_out1.reg);
-
-	*ctx++ = clk_readl(tegra_clk_cclk.reg);
-	*ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-	*ctx++ = clk_readl(tegra_clk_sclk.reg);
-	*ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-	*ctx++ = clk_readl(tegra_clk_pclk.reg);
-
-	*ctx++ = clk_readl(tegra_clk_audio.reg);
-
-	for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-			off += 4) {
-		if (off == PERIPH_CLK_SOURCE_EMC)
-			continue;
-		*ctx++ = clk_readl(off);
-	}
-
-	off = RST_DEVICES;
-	for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-		*ctx++ = clk_readl(off);
-
-	off = CLK_OUT_ENB;
-	for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-		*ctx++ = clk_readl(off);
-
-	*ctx++ = clk_readl(MISC_CLK_ENB);
-	*ctx++ = clk_readl(CLK_MASK_ARM);
-
-	BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
-}
-
-void tegra_clk_resume(void)
-{
-	unsigned long off, i;
-	const u32 *ctx = clk_rst_suspend;
-	u32 val;
-
-	val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
-	val |= *ctx++;
-	clk_writel(val, OSC_CTRL);
-
-	clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
-	clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-	clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
-	clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-	clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
-	clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-	clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
-	clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-	clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
-	clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-	udelay(1000);
-
-	clk_writel(*ctx++, tegra_pll_m_out1.reg);
-	clk_writel(*ctx++, tegra_pll_a_out0.reg);
-	clk_writel(*ctx++, tegra_pll_c_out1.reg);
-
-	clk_writel(*ctx++, tegra_clk_cclk.reg);
-	clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-	clk_writel(*ctx++, tegra_clk_sclk.reg);
-	clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-	clk_writel(*ctx++, tegra_clk_pclk.reg);
-
-	clk_writel(*ctx++, tegra_clk_audio.reg);
-
-	/* enable all clocks before configuring clock sources */
-	clk_writel(0xbffffff9ul, CLK_OUT_ENB);
-	clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
-	clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
-	wmb();
-
-	for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-			off += 4) {
-		if (off == PERIPH_CLK_SOURCE_EMC)
-			continue;
-		clk_writel(*ctx++, off);
-	}
-	wmb();
-
-	off = RST_DEVICES;
-	for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-		clk_writel(*ctx++, off);
-	wmb();
-
-	off = CLK_OUT_ENB;
-	for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-		clk_writel(*ctx++, off);
-	wmb();
-
-	clk_writel(*ctx++, MISC_CLK_ENB);
-	clk_writel(*ctx++, CLK_MASK_ARM);
-}
-#endif
-- 
1.7.4.1



From pgaikwad at nvidia.com  Mon Aug  6 02:27:42 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:42 +0530
Subject: [PATCH v4 4/6] ARM: tegra: Add clk_tegra structure and helper
 functions
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-5-git-send-email-pgaikwad@nvidia.com>

Add Tegra platform specific clock structure clk_tegra and
some helper functions for generic clock framework.

struct clk_tegra is the single strcture used for all types of
clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/mach-tegra/clock.c            |  126 +++++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/clock.h            |   90 ++++++++++++++++++++---
 arch/arm/mach-tegra/common.c           |    2 +
 arch/arm/mach-tegra/include/mach/clk.h |    3 +
 4 files changed, 210 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c..ef9b494 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
 /*
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Colin Cross <ccross at google.com>
@@ -62,6 +63,7 @@
 static DEFINE_MUTEX(clock_list_lock);
 static LIST_HEAD(clocks);
 
+#ifndef CONFIG_COMMON_CLK
 struct clk *tegra_get_clock_by_name(const char *name)
 {
 	struct clk *c;
@@ -668,5 +670,127 @@ err_out:
 	debugfs_remove_recursive(clk_debugfs_root);
 	return err;
 }
-
 #endif
+#else
+
+void tegra_clk_add(struct clk *clk)
+{
+	struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
+
+	mutex_lock(&clock_list_lock);
+	list_add(&c->node, &clocks);
+	mutex_unlock(&clock_list_lock);
+}
+
+struct clk *tegra_get_clock_by_name(const char *name)
+{
+	struct clk_tegra *c;
+	struct clk *ret = NULL;
+	mutex_lock(&clock_list_lock);
+	list_for_each_entry(c, &clocks, node) {
+		if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
+			ret = c->hw.clk;
+			break;
+		}
+	}
+	mutex_unlock(&clock_list_lock);
+	return ret;
+}
+
+static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
+{
+	struct clk *c;
+	struct clk *p;
+	struct clk *parent;
+
+	int ret = 0;
+
+	c = tegra_get_clock_by_name(table->name);
+
+	if (!c) {
+		pr_warn("Unable to initialize clock %s\n",
+			table->name);
+		return -ENODEV;
+	}
+
+	parent = clk_get_parent(c);
+
+	if (table->parent) {
+		p = tegra_get_clock_by_name(table->parent);
+		if (!p) {
+			pr_warn("Unable to find parent %s of clock %s\n",
+				table->parent, table->name);
+			return -ENODEV;
+		}
+
+		if (parent != p) {
+			ret = clk_set_parent(c, p);
+			if (ret) {
+				pr_warn("Unable to set parent %s of clock %s: %d\n",
+					table->parent, table->name, ret);
+				return -EINVAL;
+			}
+		}
+	}
+
+	if (table->rate && table->rate != clk_get_rate(c)) {
+		ret = clk_set_rate(c, table->rate);
+		if (ret) {
+			pr_warn("Unable to set clock %s to rate %lu: %d\n",
+				table->name, table->rate, ret);
+			return -EINVAL;
+		}
+	}
+
+	if (table->enabled) {
+		ret = clk_prepare_enable(c);
+		if (ret) {
+			pr_warn("Unable to enable clock %s: %d\n",
+				table->name, ret);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
+{
+	for (; table->name; table++)
+		tegra_clk_init_one_from_table(table);
+}
+
+void tegra_periph_reset_deassert(struct clk *c)
+{
+	struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+	BUG_ON(!clk->reset);
+	clk->reset(__clk_get_hw(c), false);
+}
+EXPORT_SYMBOL(tegra_periph_reset_deassert);
+
+void tegra_periph_reset_assert(struct clk *c)
+{
+	struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+	BUG_ON(!clk->reset);
+	clk->reset(__clk_get_hw(c), true);
+}
+EXPORT_SYMBOL(tegra_periph_reset_assert);
+
+/* Several extended clock configuration bits (e.g., clock routing, clock
+ * phase control) are included in PLL and peripheral clock source
+ * registers. */
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+	int ret = 0;
+	struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+
+	if (!clk->clk_cfg_ex) {
+		ret = -ENOSYS;
+		goto out;
+	}
+	ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
+
+out:
+	return ret;
+}
+#endif /* !CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc30065..f4d32ba 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/include/mach/clock.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Colin Cross <ccross at google.com>
@@ -20,6 +21,7 @@
 #ifndef __MACH_TEGRA_CLOCK_H
 #define __MACH_TEGRA_CLOCK_H
 
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
@@ -54,6 +56,11 @@
 
 struct clk;
 
+#ifdef CONFIG_COMMON_CLK
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
+#endif
+
 struct clk_mux_sel {
 	struct clk	*input;
 	u32		value;
@@ -68,6 +75,13 @@ struct clk_pll_freq_table {
 	u8		cpcon;
 };
 
+enum clk_state {
+	UNINITIALIZED = 0,
+	ON,
+	OFF,
+};
+
+#ifndef CONFIG_COMMON_CLK
 struct clk_ops {
 	void		(*init)(struct clk *);
 	int		(*enable)(struct clk *);
@@ -80,12 +94,6 @@ struct clk_ops {
 				enum tegra_clk_ex_param, u32);
 };
 
-enum clk_state {
-	UNINITIALIZED = 0,
-	ON,
-	OFF,
-};
-
 struct clk {
 	/* node for master clocks list */
 	struct list_head	node;		/* node for list of all clocks */
@@ -147,6 +155,65 @@ struct clk {
 	spinlock_t spinlock;
 };
 
+#else
+
+struct clk_tegra {
+	/* node for master clocks list */
+	struct list_head	node;	/* node for list of all clocks */
+	struct clk_lookup	lookup;
+	struct clk_hw		hw;
+
+	bool			set;
+	unsigned long		fixed_rate;
+	unsigned long		max_rate;
+	unsigned long		min_rate;
+	u32			flags;
+	const char		*name;
+
+	enum clk_state		state;
+	u32			div;
+	u32			mul;
+
+	u32				reg;
+	u32				reg_shift;
+
+	struct list_head		shared_bus_list;
+
+	union {
+		struct {
+			unsigned int			clk_num;
+		} periph;
+		struct {
+			unsigned long			input_min;
+			unsigned long			input_max;
+			unsigned long			cf_min;
+			unsigned long			cf_max;
+			unsigned long			vco_min;
+			unsigned long			vco_max;
+			const struct clk_pll_freq_table	*freq_table;
+			int				lock_delay;
+			unsigned long			fixed_rate;
+		} pll;
+		struct {
+			u32				sel;
+			u32				reg_mask;
+		} mux;
+		struct {
+			struct clk			*main;
+			struct clk			*backup;
+		} cpu;
+		struct {
+			struct list_head		node;
+			bool				enabled;
+			unsigned long			rate;
+		} shared_bus_user;
+	} u;
+
+	void (*reset)(struct clk_hw *, bool);
+	int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
+};
+#endif /* !CONFIG_COMMON_CLK */
+
 struct clk_duplicate {
 	const char *name;
 	struct clk_lookup lookup;
@@ -159,13 +226,16 @@ struct tegra_clk_init_table {
 	bool enabled;
 };
 
+#ifndef CONFIG_COMMON_CLK
+void clk_init(struct clk *clk);
+unsigned long clk_get_rate_locked(struct clk *c);
+int clk_set_rate_locked(struct clk *c, unsigned long rate);
+int clk_reparent(struct clk *c, struct clk *parent);
+#endif /* !CONFIG_COMMON_CLK */
+
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
-void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6b..ef7d6f3 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -152,6 +152,8 @@ void __init tegra30_init_early(void)
 
 void __init tegra_init_late(void)
 {
+#ifndef CONFIG_COMMON_CLK
 	tegra_clk_debugfs_init();
+#endif
 	tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403..95f3a54 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
+#ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
+#endif
+
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
-- 
1.7.4.1



From pgaikwad at nvidia.com  Mon Aug  6 02:27:44 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 6 Aug 2012 11:57:44 +0530
Subject: [PATCH v4 6/6] ARM: tegra: Remove duplicate code
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-7-git-send-email-pgaikwad@nvidia.com>

Remove Tegra legacy clock framework code.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/mach-tegra/clock.c  |  632 ------------------------------------------
 arch/arm/mach-tegra/clock.h  |   89 ------
 arch/arm/mach-tegra/common.c |    3 -
 3 files changed, 0 insertions(+), 724 deletions(-)

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index ef9b494..632133f 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -20,8 +20,6 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/module.h>
@@ -37,642 +35,13 @@
 /*
  * Locking:
  *
- * Each struct clk has a spinlock.
- *
- * To avoid AB-BA locking problems, locks must always be traversed from child
- * clock to parent clock.  For example, when enabling a clock, the clock's lock
- * is taken, and then clk_enable is called on the parent, which take's the
- * parent clock's lock.  There is one exceptions to this ordering: When dumping
- * the clock tree through debugfs.  In this case, clk_lock_all is called,
- * which attemps to iterate through the entire list of clocks and take every
- * clock lock.  If any call to spin_trylock fails, all locked clocks are
- * unlocked, and the process is retried.  When all the locks are held,
- * the only clock operation that can be called is clk_get_rate_all_locked.
- *
- * Within a single clock, no clock operation can call another clock operation
- * on itself, except for clk_get_rate_locked and clk_set_rate_locked.  Any
- * clock operation can call any other clock operation on any of it's possible
- * parents.
- *
  * An additional mutex, clock_list_lock, is used to protect the list of all
  * clocks.
  *
- * The clock operations must lock internally to protect against
- * read-modify-write on registers that are shared by multiple clocks
  */
 static DEFINE_MUTEX(clock_list_lock);
 static LIST_HEAD(clocks);
 
-#ifndef CONFIG_COMMON_CLK
-struct clk *tegra_get_clock_by_name(const char *name)
-{
-	struct clk *c;
-	struct clk *ret = NULL;
-	mutex_lock(&clock_list_lock);
-	list_for_each_entry(c, &clocks, node) {
-		if (strcmp(c->name, name) == 0) {
-			ret = c;
-			break;
-		}
-	}
-	mutex_unlock(&clock_list_lock);
-	return ret;
-}
-
-/* Must be called with c->spinlock held */
-static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
-{
-	u64 rate;
-
-	rate = clk_get_rate(p);
-
-	if (c->mul != 0 && c->div != 0) {
-		rate *= c->mul;
-		rate += c->div - 1; /* round up */
-		do_div(rate, c->div);
-	}
-
-	return rate;
-}
-
-/* Must be called with c->spinlock held */
-unsigned long clk_get_rate_locked(struct clk *c)
-{
-	unsigned long rate;
-
-	if (c->parent)
-		rate = clk_predict_rate_from_parent(c, c->parent);
-	else
-		rate = c->rate;
-
-	return rate;
-}
-
-unsigned long clk_get_rate(struct clk *c)
-{
-	unsigned long flags;
-	unsigned long rate;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	rate = clk_get_rate_locked(c);
-
-	spin_unlock_irqrestore(&c->spinlock, flags);
-
-	return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_reparent(struct clk *c, struct clk *parent)
-{
-	c->parent = parent;
-	return 0;
-}
-
-void clk_init(struct clk *c)
-{
-	spin_lock_init(&c->spinlock);
-
-	if (c->ops && c->ops->init)
-		c->ops->init(c);
-
-	if (!c->ops || !c->ops->enable) {
-		c->refcnt++;
-		c->set = true;
-		if (c->parent)
-			c->state = c->parent->state;
-		else
-			c->state = ON;
-	}
-
-	mutex_lock(&clock_list_lock);
-	list_add(&c->node, &clocks);
-	mutex_unlock(&clock_list_lock);
-}
-
-int clk_enable(struct clk *c)
-{
-	int ret = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	if (c->refcnt == 0) {
-		if (c->parent) {
-			ret = clk_enable(c->parent);
-			if (ret)
-				goto out;
-		}
-
-		if (c->ops && c->ops->enable) {
-			ret = c->ops->enable(c);
-			if (ret) {
-				if (c->parent)
-					clk_disable(c->parent);
-				goto out;
-			}
-			c->state = ON;
-			c->set = true;
-		}
-	}
-	c->refcnt++;
-out:
-	spin_unlock_irqrestore(&c->spinlock, flags);
-	return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *c)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	if (c->refcnt == 0) {
-		WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
-		spin_unlock_irqrestore(&c->spinlock, flags);
-		return;
-	}
-	if (c->refcnt == 1) {
-		if (c->ops && c->ops->disable)
-			c->ops->disable(c);
-
-		if (c->parent)
-			clk_disable(c->parent);
-
-		c->state = OFF;
-	}
-	c->refcnt--;
-
-	spin_unlock_irqrestore(&c->spinlock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-int clk_set_parent(struct clk *c, struct clk *parent)
-{
-	int ret;
-	unsigned long flags;
-	unsigned long new_rate;
-	unsigned long old_rate;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	if (!c->ops || !c->ops->set_parent) {
-		ret = -ENOSYS;
-		goto out;
-	}
-
-	new_rate = clk_predict_rate_from_parent(c, parent);
-	old_rate = clk_get_rate_locked(c);
-
-	ret = c->ops->set_parent(c, parent);
-	if (ret)
-		goto out;
-
-out:
-	spin_unlock_irqrestore(&c->spinlock, flags);
-	return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *c)
-{
-	return c->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_rate_locked(struct clk *c, unsigned long rate)
-{
-	long new_rate;
-
-	if (!c->ops || !c->ops->set_rate)
-		return -ENOSYS;
-
-	if (rate > c->max_rate)
-		rate = c->max_rate;
-
-	if (c->ops && c->ops->round_rate) {
-		new_rate = c->ops->round_rate(c, rate);
-
-		if (new_rate < 0)
-			return new_rate;
-
-		rate = new_rate;
-	}
-
-	return c->ops->set_rate(c, rate);
-}
-
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
-	int ret;
-	unsigned long flags;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	ret = clk_set_rate_locked(c, rate);
-
-	spin_unlock_irqrestore(&c->spinlock, flags);
-
-	return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-
-/* Must be called with clocks lock and all indvidual clock locks held */
-unsigned long clk_get_rate_all_locked(struct clk *c)
-{
-	u64 rate;
-	int mul = 1;
-	int div = 1;
-	struct clk *p = c;
-
-	while (p) {
-		c = p;
-		if (c->mul != 0 && c->div != 0) {
-			mul *= c->mul;
-			div *= c->div;
-		}
-		p = c->parent;
-	}
-
-	rate = c->rate;
-	rate *= mul;
-	do_div(rate, div);
-
-	return rate;
-}
-
-long clk_round_rate(struct clk *c, unsigned long rate)
-{
-	unsigned long flags;
-	long ret;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	if (!c->ops || !c->ops->round_rate) {
-		ret = -ENOSYS;
-		goto out;
-	}
-
-	if (rate > c->max_rate)
-		rate = c->max_rate;
-
-	ret = c->ops->round_rate(c, rate);
-
-out:
-	spin_unlock_irqrestore(&c->spinlock, flags);
-	return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
-{
-	struct clk *c;
-	struct clk *p;
-
-	int ret = 0;
-
-	c = tegra_get_clock_by_name(table->name);
-
-	if (!c) {
-		pr_warning("Unable to initialize clock %s\n",
-			table->name);
-		return -ENODEV;
-	}
-
-	if (table->parent) {
-		p = tegra_get_clock_by_name(table->parent);
-		if (!p) {
-			pr_warning("Unable to find parent %s of clock %s\n",
-				table->parent, table->name);
-			return -ENODEV;
-		}
-
-		if (c->parent != p) {
-			ret = clk_set_parent(c, p);
-			if (ret) {
-				pr_warning("Unable to set parent %s of clock %s: %d\n",
-					table->parent, table->name, ret);
-				return -EINVAL;
-			}
-		}
-	}
-
-	if (table->rate && table->rate != clk_get_rate(c)) {
-		ret = clk_set_rate(c, table->rate);
-		if (ret) {
-			pr_warning("Unable to set clock %s to rate %lu: %d\n",
-				table->name, table->rate, ret);
-			return -EINVAL;
-		}
-	}
-
-	if (table->enabled) {
-		ret = clk_enable(c);
-		if (ret) {
-			pr_warning("Unable to enable clock %s: %d\n",
-				table->name, ret);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
-{
-	for (; table->name; table++)
-		tegra_clk_init_one_from_table(table);
-}
-EXPORT_SYMBOL(tegra_clk_init_from_table);
-
-void tegra_periph_reset_deassert(struct clk *c)
-{
-	BUG_ON(!c->ops->reset);
-	c->ops->reset(c, false);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-	BUG_ON(!c->ops->reset);
-	c->ops->reset(c, true);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
-/* Several extended clock configuration bits (e.g., clock routing, clock
- * phase control) are included in PLL and peripheral clock source
- * registers. */
-int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
-{
-	int ret = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	if (!c->ops || !c->ops->clk_cfg_ex) {
-		ret = -ENOSYS;
-		goto out;
-	}
-	ret = c->ops->clk_cfg_ex(c, p, setting);
-
-out:
-	spin_unlock_irqrestore(&c->spinlock, flags);
-
-	return ret;
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-static int __clk_lock_all_spinlocks(void)
-{
-	struct clk *c;
-
-	list_for_each_entry(c, &clocks, node)
-		if (!spin_trylock(&c->spinlock))
-			goto unlock_spinlocks;
-
-	return 0;
-
-unlock_spinlocks:
-	list_for_each_entry_continue_reverse(c, &clocks, node)
-		spin_unlock(&c->spinlock);
-
-	return -EAGAIN;
-}
-
-static void __clk_unlock_all_spinlocks(void)
-{
-	struct clk *c;
-
-	list_for_each_entry_reverse(c, &clocks, node)
-		spin_unlock(&c->spinlock);
-}
-
-/*
- * This function retries until it can take all locks, and may take
- * an arbitrarily long time to complete.
- * Must be called with irqs enabled, returns with irqs disabled
- * Must be called with clock_list_lock held
- */
-static void clk_lock_all(void)
-{
-	int ret;
-retry:
-	local_irq_disable();
-
-	ret = __clk_lock_all_spinlocks();
-	if (ret)
-		goto failed_spinlocks;
-
-	/* All locks taken successfully, return */
-	return;
-
-failed_spinlocks:
-	local_irq_enable();
-	yield();
-	goto retry;
-}
-
-/*
- * Unlocks all clocks after a clk_lock_all
- * Must be called with irqs disabled, returns with irqs enabled
- * Must be called with clock_list_lock held
- */
-static void clk_unlock_all(void)
-{
-	__clk_unlock_all_spinlocks();
-
-	local_irq_enable();
-}
-
-static struct dentry *clk_debugfs_root;
-
-
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
-	struct clk *child;
-	const char *state = "uninit";
-	char div[8] = {0};
-
-	if (c->state == ON)
-		state = "on";
-	else if (c->state == OFF)
-		state = "off";
-
-	if (c->mul != 0 && c->div != 0) {
-		if (c->mul > c->div) {
-			int mul = c->mul / c->div;
-			int mul2 = (c->mul * 10 / c->div) % 10;
-			int mul3 = (c->mul * 10) % c->div;
-			if (mul2 == 0 && mul3 == 0)
-				snprintf(div, sizeof(div), "x%d", mul);
-			else if (mul3 == 0)
-				snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
-			else
-				snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
-		} else {
-			snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
-				(c->div % c->mul) ? ".5" : "");
-		}
-	}
-
-	seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
-		level * 3 + 1, "",
-		c->rate > c->max_rate ? '!' : ' ',
-		!c->set ? '*' : ' ',
-		30 - level * 3, c->name,
-		state, c->refcnt, div, clk_get_rate_all_locked(c));
-
-	list_for_each_entry(child, &clocks, node) {
-		if (child->parent != c)
-			continue;
-
-		clock_tree_show_one(s, child, level + 1);
-	}
-}
-
-static int clock_tree_show(struct seq_file *s, void *data)
-{
-	struct clk *c;
-	seq_printf(s, "   clock                          state  ref div      rate\n");
-	seq_printf(s, "--------------------------------------------------------------\n");
-
-	mutex_lock(&clock_list_lock);
-
-	clk_lock_all();
-
-	list_for_each_entry(c, &clocks, node)
-		if (c->parent == NULL)
-			clock_tree_show_one(s, c, 0);
-
-	clk_unlock_all();
-
-	mutex_unlock(&clock_list_lock);
-	return 0;
-}
-
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, clock_tree_show, inode->i_private);
-}
-
-static const struct file_operations clock_tree_fops = {
-	.open		= clock_tree_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
-};
-
-static int possible_parents_show(struct seq_file *s, void *data)
-{
-	struct clk *c = s->private;
-	int i;
-
-	for (i = 0; c->inputs[i].input; i++) {
-		char *first = (i == 0) ? "" : " ";
-		seq_printf(s, "%s%s", first, c->inputs[i].input->name);
-	}
-	seq_printf(s, "\n");
-	return 0;
-}
-
-static int possible_parents_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, possible_parents_show, inode->i_private);
-}
-
-static const struct file_operations possible_parents_fops = {
-	.open		= possible_parents_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
-};
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-	struct dentry *d;
-
-	d = debugfs_create_dir(c->name, clk_debugfs_root);
-	if (!d)
-		return -ENOMEM;
-	c->dent = d;
-
-	d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
-	if (!d)
-		goto err_out;
-
-	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-	if (!d)
-		goto err_out;
-
-	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-	if (!d)
-		goto err_out;
-
-	if (c->inputs) {
-		d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
-			c, &possible_parents_fops);
-		if (!d)
-			goto err_out;
-	}
-
-	return 0;
-
-err_out:
-	debugfs_remove_recursive(c->dent);
-	return -ENOMEM;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-	int err;
-	struct clk *pa = c->parent;
-
-	if (pa && !pa->dent) {
-		err = clk_debugfs_register(pa);
-		if (err)
-			return err;
-	}
-
-	if (!c->dent) {
-		err = clk_debugfs_register_one(c);
-		if (err)
-			return err;
-	}
-	return 0;
-}
-
-int __init tegra_clk_debugfs_init(void)
-{
-	struct clk *c;
-	struct dentry *d;
-	int err = -ENOMEM;
-
-	d = debugfs_create_dir("clock", NULL);
-	if (!d)
-		return -ENOMEM;
-	clk_debugfs_root = d;
-
-	d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
-		&clock_tree_fops);
-	if (!d)
-		goto err_out;
-
-	list_for_each_entry(c, &clocks, node) {
-		err = clk_debugfs_register(c);
-		if (err)
-			goto err_out;
-	}
-	return 0;
-err_out:
-	debugfs_remove_recursive(clk_debugfs_root);
-	return err;
-}
-#endif
-#else
-
 void tegra_clk_add(struct clk *clk)
 {
 	struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
@@ -793,4 +162,3 @@ int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 out:
 	return ret;
 }
-#endif /* !CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index be69ae1..2aa37f5 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -24,7 +24,6 @@
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/list.h>
-#include <linux/spinlock.h>
 
 #include <mach/clk.h>
 
@@ -54,12 +53,8 @@
 #define ENABLE_ON_INIT		(1 << 28)
 #define PERIPH_ON_APB           (1 << 29)
 
-struct clk;
-
-#ifdef CONFIG_COMMON_CLK
 struct clk_tegra;
 #define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
-#endif
 
 struct clk_mux_sel {
 	struct clk	*input;
@@ -81,82 +76,6 @@ enum clk_state {
 	OFF,
 };
 
-#ifndef CONFIG_COMMON_CLK
-struct clk_ops {
-	void		(*init)(struct clk *);
-	int		(*enable)(struct clk *);
-	void		(*disable)(struct clk *);
-	int		(*set_parent)(struct clk *, struct clk *);
-	int		(*set_rate)(struct clk *, unsigned long);
-	long		(*round_rate)(struct clk *, unsigned long);
-	void		(*reset)(struct clk *, bool);
-	int		(*clk_cfg_ex)(struct clk *,
-				enum tegra_clk_ex_param, u32);
-};
-
-struct clk {
-	/* node for master clocks list */
-	struct list_head	node;		/* node for list of all clocks */
-	struct clk_lookup	lookup;
-
-#ifdef CONFIG_DEBUG_FS
-	struct dentry		*dent;
-#endif
-	bool			set;
-	struct clk_ops		*ops;
-	unsigned long		rate;
-	unsigned long		max_rate;
-	unsigned long		min_rate;
-	u32			flags;
-	const char		*name;
-
-	u32			refcnt;
-	enum clk_state		state;
-	struct clk		*parent;
-	u32			div;
-	u32			mul;
-
-	const struct clk_mux_sel	*inputs;
-	u32				reg;
-	u32				reg_shift;
-
-	struct list_head		shared_bus_list;
-
-	union {
-		struct {
-			unsigned int			clk_num;
-		} periph;
-		struct {
-			unsigned long			input_min;
-			unsigned long			input_max;
-			unsigned long			cf_min;
-			unsigned long			cf_max;
-			unsigned long			vco_min;
-			unsigned long			vco_max;
-			const struct clk_pll_freq_table	*freq_table;
-			int				lock_delay;
-			unsigned long			fixed_rate;
-		} pll;
-		struct {
-			u32				sel;
-			u32				reg_mask;
-		} mux;
-		struct {
-			struct clk			*main;
-			struct clk			*backup;
-		} cpu;
-		struct {
-			struct list_head		node;
-			bool				enabled;
-			unsigned long			rate;
-		} shared_bus_user;
-	} u;
-
-	spinlock_t spinlock;
-};
-
-#else
-
 struct clk_tegra {
 	/* node for master clocks list */
 	struct list_head	node;	/* node for list of all clocks */
@@ -212,7 +131,6 @@ struct clk_tegra {
 	void (*reset)(struct clk_hw *, bool);
 	int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
 };
-#endif /* !CONFIG_COMMON_CLK */
 
 struct clk_duplicate {
 	const char *name;
@@ -226,13 +144,6 @@ struct tegra_clk_init_table {
 	bool enabled;
 };
 
-#ifndef CONFIG_COMMON_CLK
-void clk_init(struct clk *clk);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
-int clk_reparent(struct clk *c, struct clk *parent);
-#endif /* !CONFIG_COMMON_CLK */
-
 void tegra_clk_add(struct clk *c);
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index ef7d6f3..f3654f8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -152,8 +152,5 @@ void __init tegra30_init_early(void)
 
 void __init tegra_init_late(void)
 {
-#ifndef CONFIG_COMMON_CLK
-	tegra_clk_debugfs_init();
-#endif
 	tegra_powergate_debugfs_init();
 }
-- 
1.7.4.1



From sumit.semwal at ti.com  Mon Aug  6 02:37:50 2012
From: sumit.semwal at ti.com (Semwal, Sumit)
Date: Mon, 6 Aug 2012 12:07:50 +0530
Subject: [PATCH 2/2] dma-buf: add helpers for attacher dma-parms
In-Reply-To: <CAF6AEGs2evpga=h1+0L0sz+vG1czHff83z13WxdBv+xvcxQKxw@mail.gmail.com>
References: <1342715014-5316-1-git-send-email-rob.clark@linaro.org>
 <1342715014-5316-3-git-send-email-rob.clark@linaro.org>
 <CAF6AEGs2evpga=h1+0L0sz+vG1czHff83z13WxdBv+xvcxQKxw@mail.gmail.com>
Message-ID: <CAB2ybb-jWWgxNMwRBCOA5W4=y4Q9U-xQHeu+CtNp-eRteA4jxQ@mail.gmail.com>

On Fri, Jul 20, 2012 at 10:09 PM, Rob Clark <rob.clark at linaro.org> wrote:
> Fyi, Daniel Vetter had suggested on IRC that it would be cleaner to
> have a single helper fxn that most-restrictive union of all attached
> device's dma_parms.  Really this should include dma_mask and
> coherent_dma_mask, I think.  But that touches a lot of other places in
> the code.  If no one objects to the cleanup of moving
> dma_mask/coherent_dma_mask into dma_parms, I'll do this first.
>
> So anyways, don't consider this patch yet for inclusion, I'll make an
> updated one based on dma_parms..
Hi Rob,
Any news on this patch-set?
>
> BR,
> -R
BR,
~Sumit.
>
> On Thu, Jul 19, 2012 at 11:23 AM, Rob Clark <rob.clark at linaro.org> wrote:
>> From: Rob Clark <rob at ti.com>
>>
>> Add some helpers to iterate through all attachers and get the most
>> restrictive segment size/count/boundary.
>>
>> Signed-off-by: Rob Clark <rob at ti.com>
>> ---
>>  drivers/base/dma-buf.c  |   63 +++++++++++++++++++++++++++++++++++++++++++++++
>>  include/linux/dma-buf.h |   19 ++++++++++++++
>>  2 files changed, 82 insertions(+)
>>
>> diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c
>> index 24e88fe..757ee20 100644
>> --- a/drivers/base/dma-buf.c
>> +++ b/drivers/base/dma-buf.c
>> @@ -192,6 +192,69 @@ void dma_buf_put(struct dma_buf *dmabuf)
>>  EXPORT_SYMBOL_GPL(dma_buf_put);
>>
>>  /**
>> + * dma_buf_max_seg_size - helper for exporters to get the minimum of
>> + * all attached device's max segment size
>> + */
>> +unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf)
>> +{
>> +       struct dma_buf_attachment *attach;
>> +       unsigned int max = (unsigned int)-1;
>> +
>> +       if (WARN_ON(!dmabuf))
>> +               return 0;
>> +
>> +       mutex_lock(&dmabuf->lock);
>> +       list_for_each_entry(attach, &dmabuf->attachments, node)
>> +               max = min(max, dma_get_max_seg_size(attach->dev));
>> +       mutex_unlock(&dmabuf->lock);
>> +
>> +       return max;
>> +}
>> +EXPORT_SYMBOL_GPL(dma_buf_max_seg_size);
>> +
>> +/**
>> + * dma_buf_max_seg_count - helper for exporters to get the minimum of
>> + * all attached device's max segment count
>> + */
>> +unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf)
>> +{
>> +       struct dma_buf_attachment *attach;
>> +       unsigned int max = (unsigned int)-1;
>> +
>> +       if (WARN_ON(!dmabuf))
>> +               return 0;
>> +
>> +       mutex_lock(&dmabuf->lock);
>> +       list_for_each_entry(attach, &dmabuf->attachments, node)
>> +               max = min(max, dma_get_max_seg_count(attach->dev));
>> +       mutex_unlock(&dmabuf->lock);
>> +
>> +       return max;
>> +}
>> +EXPORT_SYMBOL_GPL(dma_buf_max_seg_count);
>> +
>> +/**
>> + * dma_buf_get_seg_boundary - helper for exporters to get the most
>> + * restrictive segment alignment of all the attached devices
>> + */
>> +unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf)
>> +{
>> +       struct dma_buf_attachment *attach;
>> +       unsigned int mask = (unsigned int)-1;
>> +
>> +       if (WARN_ON(!dmabuf))
>> +               return 0;
>> +
>> +       mutex_lock(&dmabuf->lock);
>> +       list_for_each_entry(attach, &dmabuf->attachments, node)
>> +               mask &= dma_get_seg_boundary(attach->dev);
>> +       mutex_unlock(&dmabuf->lock);
>> +
>> +       return mask;
>> +}
>> +EXPORT_SYMBOL_GPL(dma_buf_get_seg_boundary);
>> +
>> +/**
>>   * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
>>   * calls attach() of dma_buf_ops to allow device-specific attach functionality
>>   * @dmabuf:    [in]    buffer to attach device to.
>> diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
>> index eb48f38..9533b9b 100644
>> --- a/include/linux/dma-buf.h
>> +++ b/include/linux/dma-buf.h
>> @@ -167,6 +167,10 @@ int dma_buf_fd(struct dma_buf *dmabuf, int flags);
>>  struct dma_buf *dma_buf_get(int fd);
>>  void dma_buf_put(struct dma_buf *dmabuf);
>>
>> +unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf);
>> +unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf);
>> +unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf);
>> +
>>  struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *,
>>                                         enum dma_data_direction);
>>  void dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *,
>> @@ -220,6 +224,21 @@ static inline void dma_buf_put(struct dma_buf *dmabuf)
>>         return;
>>  }
>>
>> +static inline unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf)
>> +{
>> +       return 0;
>> +}
>> +
>> +static inline unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf)
>> +{
>> +       return 0;
>> +}
>> +
>> +static inline unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf)
>> +{
>> +       return 0;
>> +}
>> +
>>  static inline struct sg_table *dma_buf_map_attachment(
>>         struct dma_buf_attachment *attach, enum dma_data_direction write)
>>  {
>> --
>> 1.7.9.5
>>


From Ying.liu at freescale.com  Mon Aug  6 02:02:08 2012
From: Ying.liu at freescale.com (Liu Ying)
Date: Mon, 6 Aug 2012 14:02:08 +0800
Subject: [PATCH 1/1] media: mx3_camera: Improve data bus width check code for
 probe
Message-ID: <1344232928-17361-1-git-send-email-Ying.liu@freescale.com>

This patch contains code change only to use the present macro-
MX3_CAMERA_DATAWIDTH_MASK to check valid camera platform data
bus width instead of enumerating every possible data bus width.

Signed-off-by: Liu Ying <Ying.Liu at freescale.com>
---
 drivers/media/video/mx3_camera.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c
index f96f92f..346e2cd 100644
--- a/drivers/media/video/mx3_camera.c
+++ b/drivers/media/video/mx3_camera.c
@@ -1173,9 +1173,7 @@ static int __devinit mx3_camera_probe(struct platform_device *pdev)
 
 	mx3_cam->pdata = pdev->dev.platform_data;
 	mx3_cam->platform_flags = mx3_cam->pdata->flags;
-	if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 |
-			MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 |
-			MX3_CAMERA_DATAWIDTH_15))) {
+	if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) {
 		/*
 		 * Platform hasn't set available data widths. This is bad.
 		 * Warn and use a default.
-- 
1.7.1




From sourav.poddar at ti.com  Mon Aug  6 03:35:34 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Mon, 6 Aug 2012 13:05:34 +0530
Subject: [PATCH] hwmon: tmp102: Add device tree support
In-Reply-To: <501BE6B1.9000100@ti.com>
References: <1343997350-676-1-git-send-email-sourav.poddar@ti.com>
 <501BE6B1.9000100@ti.com>
Message-ID: <CAKdam54Zshr-d502E_AS+vw5+vLQnTBrAGRPTy-9-hZy1QEFbA@mail.gmail.com>

Hi Benoit,

On Fri, Aug 3, 2012 at 8:26 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Sourav,
>
> On 08/03/2012 02:35 PM, Sourav Poddar wrote:
>> update tmp102 temperature sensor to also use device tree.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Acked-by: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>>  drivers/hwmon/tmp102.c |   14 +++++++++++++-
>>  1 files changed, 13 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c
>> index 0d466b9..a8a9060 100644
>> --- a/drivers/hwmon/tmp102.c
>> +++ b/drivers/hwmon/tmp102.c
>> @@ -26,6 +26,7 @@
>>  #include <linux/err.h>
>>  #include <linux/mutex.h>
>>  #include <linux/device.h>
>> +#include <linux/of.h>
>>
>>  #define      DRIVER_NAME "tmp102"
>>
>> @@ -284,8 +285,19 @@ static const struct i2c_device_id tmp102_id[] = {
>>  };
>>  MODULE_DEVICE_TABLE(i2c, tmp102_id);
>>
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id temperature_dt_match[] = {
>> +     { .compatible = "ti,tmp102" },
>
> Are you sure this is needed for this device?
>
> There is an automatic binding done for I2C devices in the of_i2c core
> code. So in theory, DT will be able to bind to any I2C device using the
> already existing table: MODULE_DEVICE_TABLE(i2c, tmp102_id).
>
> So I think this patch should not be needed.
>
Indeed. Checked it just now, this patch is not required and the already
existing table is enough for the device to work fine.

Thanks for the information.

This patch is abandoned.
~Sourav
> Regards,
> Benoit
>


From r.sricharan at ti.com  Mon Aug  6 03:41:25 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Mon, 6 Aug 2012 13:11:25 +0530
Subject: [PATCH v2 1/1] ARM: LPAE: Fix mapping in alloc_init_pte for unaligned
 addresses.
Message-ID: <1344238885-13683-1-git-send-email-r.sricharan@ti.com>

With LPAE, When either the start address or end address
or physical address to be mapped is unaligned,
alloc_init_section creates page granularity mappings.
alloc_init_section calls alloc_init_pte which populates
one pmd entry and sets up the ptes. But if the size is
greater than what can be mapped by one pmd entry,
then the rest remains unmapped.

The issue becomes visible when LPAE is enabled, where we have
the 3 levels with seperate pgd and pmd's.
When a static mapping for 3MB is requested, only 2MB is mapped
and the remaining 1MB is unmapped. Fixing this here, by looping
in to map the entire unaligned address range.

Boot tested on OMAP5 evm with both LPAE enabled/disabled
and verified that static mappings with unaligned addresses
are properly mapped.

Signed-off-by: R Sricharan <r.sricharan at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
---
[V2] Moved the loop to alloc_init_pte as per Russell's
     feedback and changed the subject accordingly.
     Using PMD_XXX instead of SECTION_XXX to avoid
     different loop increments with/without LPAE.

 arch/arm/mm/mmu.c |   22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d..0ed8808 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -585,11 +585,25 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 				  unsigned long end, unsigned long pfn,
 				  const struct mem_type *type)
 {
-	pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
+	unsigned long next;
+	pte_t *pte;
+	phys_addr_t phys;
+
 	do {
-		set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
-		pfn++;
-	} while (pte++, addr += PAGE_SIZE, addr != end);
+		if ((end-addr) & PMD_MASK)
+			next = (addr + PMD_SIZE) & PMD_MASK;
+		else
+			next = end;
+
+		pte = early_pte_alloc(pmd, addr, type->prot_l1);
+		do {
+			set_pte_ext(pte, pfn_pte(pfn,
+					__pgprot(type->prot_pte)), 0);
+			pfn++;
+		} while (pte++, addr += PAGE_SIZE, addr != next);
+
+		phys += next - addr;
+	} while (pmd++, addr = next, addr != end);
 }
 
 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
-- 
1.7.9.5



From linus.walleij at stericsson.com  Mon Aug  6 03:52:52 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 6 Aug 2012 09:52:52 +0200
Subject: [PATCH] MAINTAINERS: update my entries
Message-ID: <1344239572-23250-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

I prefer to use the Linaro mail address for the MAINTAINERS
entry due to heavy mail traffic. Take this opportunity to
update the wildcards, including removing the stmpe* drivers
from the ux500 entry since these are not specific to that
machine.

Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
Arnd, Olof: This is another patch I'd appreciate if you just
put into the fixes as a single thing.
---
 MAINTAINERS | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 94b823f..b694a9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -925,14 +925,14 @@ S:	Maintained
 
 ARM/NOMADIK ARCHITECTURE
 M:	Alessandro Rubini <rubini at unipv.it>
-M:	Linus Walleij <linus.walleij at stericsson.com>
+M:	Linus Walleij <linus.walleij at linaro.org>
 M:	STEricsson <STEricsson_nomadik_linux at list.st.com>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-nomadik/
 F:	arch/arm/plat-nomadik/
 F:	drivers/i2c/busses/i2c-nomadik.c
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
 
 ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
 M:	Nelson Castillo <arhuaco at freaks-unidos.net>
@@ -1146,7 +1146,7 @@ F:	drivers/usb/host/ehci-w90x900.c
 F:	drivers/video/nuc900fb.c
 
 ARM/U300 MACHINE SUPPORT
-M:	Linus Walleij <linus.walleij at stericsson.com>
+M:	Linus Walleij <linus.walleij at linaro.org>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Supported
 F:	arch/arm/mach-u300/
@@ -1161,15 +1161,20 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
 
 ARM/Ux500 ARM ARCHITECTURE
 M:	Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
-M:	Linus Walleij <linus.walleij at stericsson.com>
+M:	Linus Walleij <linus.walleij at linaro.org>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-ux500/
+F:	drivers/clocksource/clksrc-dbx500-prcmu.c
 F:	drivers/dma/ste_dma40*
+F:	drivers/hwspinlock/u8500_hsem.c
 F:	drivers/mfd/abx500*
 F:	drivers/mfd/ab8500*
-F:	drivers/mfd/stmpe*
+F:	drivers/mfd/dbx500*
+F:	drivers/mfd/db8500*
+F:	drivers/pinctrl/pinctrl-nomadik*
 F:	drivers/rtc/rtc-ab8500.c
+F:	drivers/rtc/rtc-pl031.c
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
 
 ARM/VFP SUPPORT
@@ -3094,7 +3099,7 @@ F:	include/linux/gigaset_dev.h
 
 GPIO SUBSYSTEM
 M:	Grant Likely <grant.likely at secretlab.ca>
-M:	Linus Walleij <linus.walleij at stericsson.com>
+M:	Linus Walleij <linus.walleij at linaro.org>
 S:	Maintained
 T:	git git://git.secretlab.ca/git/linux-2.6.git
 F:	Documentation/gpio.txt
-- 
1.7.11.3



From arnd at arndb.de  Mon Aug  6 04:09:15 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 08:09:15 +0000
Subject: [PATCH v3 4/9] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <CACRpkdYaL65VGFKD-3OM173jQV6zeAj3bCcpHneC2L0yK504rw@mail.gmail.com>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <CAN1soZzOTMChr7WQzguH_CPQ8s=tyrsjwmAYNSBAVeMtwRE2uA@mail.gmail.com>
 <CACRpkdYaL65VGFKD-3OM173jQV6zeAj3bCcpHneC2L0yK504rw@mail.gmail.com>
Message-ID: <201208060809.15527.arnd@arndb.de>

On Sunday 05 August 2012, Linus Walleij wrote:
> >>>
> >>> +#ifdef CONFIG_ARCH_PXA
> >>> +               if (gpio_is_pxa_type(gpio_type))
> >>> +                       irq_base = PXA_GPIO_TO_IRQ(0);
> >>> +#endif
> >>> +#ifdef CONFIG_ARCH_MMP
> >>> +               if (gpio_is_mmp_type(gpio_type))
> >>> +                       irq_base = MMP_GPIO_TO_IRQ(0);
> >>> +#endif
> >>
> >> Grrr. Can we think of a way to get rid of these #ifdef:s?
> >>
> >
> > It's used for non-DT mode. This driver is used in both arch-pxa
> > and arch-mmp. Since we use static irq allocation in non-DT mode,
> > we have to use this kind of code to get irq_base.
> >
> > What Daniel did is only simplifying the code.
> 
> Yep I know, and the result is better than without the patch, so
> I Acked it. But if I have my dreams come true we could do away
> with this compile-time stuff as well...

I think the real solution for these is to merge ARCH_PXA and ARCH_MMP
and move all the code into one directory. I think it's ok to have
the above hack in there in the meantime as long as we can agree on where
we're heading eventually.

	Arnd


From zonque at gmail.com  Mon Aug  6 04:11:33 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 06 Aug 2012 10:11:33 +0200
Subject: [PATCH v3 4/9] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <201208060809.15527.arnd@arndb.de>
References: <1343470061-16879-1-git-send-email-zonque@gmail.com>
 <CAN1soZzOTMChr7WQzguH_CPQ8s=tyrsjwmAYNSBAVeMtwRE2uA@mail.gmail.com>
 <CACRpkdYaL65VGFKD-3OM173jQV6zeAj3bCcpHneC2L0yK504rw@mail.gmail.com>
 <201208060809.15527.arnd@arndb.de>
Message-ID: <501F7C35.7040409@gmail.com>

On 06.08.2012 10:09, Arnd Bergmann wrote:
> On Sunday 05 August 2012, Linus Walleij wrote:
>>>>>
>>>>> +#ifdef CONFIG_ARCH_PXA
>>>>> +               if (gpio_is_pxa_type(gpio_type))
>>>>> +                       irq_base = PXA_GPIO_TO_IRQ(0);
>>>>> +#endif
>>>>> +#ifdef CONFIG_ARCH_MMP
>>>>> +               if (gpio_is_mmp_type(gpio_type))
>>>>> +                       irq_base = MMP_GPIO_TO_IRQ(0);
>>>>> +#endif
>>>>
>>>> Grrr. Can we think of a way to get rid of these #ifdef:s?
>>>>
>>>
>>> It's used for non-DT mode. This driver is used in both arch-pxa
>>> and arch-mmp. Since we use static irq allocation in non-DT mode,
>>> we have to use this kind of code to get irq_base.
>>>
>>> What Daniel did is only simplifying the code.
>>
>> Yep I know, and the result is better than without the patch, so
>> I Acked it. But if I have my dreams come true we could do away
>> with this compile-time stuff as well...
> 
> I think the real solution for these is to merge ARCH_PXA and ARCH_MMP
> and move all the code into one directory. I think it's ok to have
> the above hack in there in the meantime as long as we can agree on where
> we're heading eventually.

I don't know how much work that would be but I agree that it would
definitiely be nicer, yes. Note, however, that there was a lot more
#ifdef hackery in that driver before the cleanup.


Daniel



From arnd at arndb.de  Mon Aug  6 04:13:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 08:13:01 +0000
Subject: [PATCH] arm: add documentation describing Marvell families of SoC
In-Reply-To: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <201208060813.01524.arnd@arndb.de>

On Saturday 04 August 2012, Thomas Petazzoni wrote:
> As stated in the introduction of the document, the families of ARM
> SoCs at Marvell are very complicated, and it is difficult for
> newcomers to understand the organization of this SoC family and how it
> relates to the Linux kernel support for those hardware platforms.
> 
> This document is only at RFC stage for now, it requires reviews and
> comments from the Marvell maintainers, the PXA maintainers and the MMP
> maintainers. For correctness of course, but also to add any other
> information that would be useful. For example, one of the thing that
> wasn't clear how to detail in the documentation is how the SoCs relate
> to each other in terms of hardware IP blocks. For example, most of the
> Kirkwood/Dove/Armada 370-XP/etc. hardware IPs (I2C, SPI, USB, SATA,
> etc.) are identical, while the PXA and MMP families are completely
> separate.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Lior Amsalem <alior at marvell.com>
> Cc: Maen Suleiman <maen at marvell.com>
> Cc: Tawfik Bayouk <tawfik at marvell.com>
> Cc: Shadi Ammouri <shadi at marvell.com>
> Cc: Eran Ben-Avi <benavi at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From p.paneri at samsung.com  Mon Aug  6 04:20:30 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Mon, 6 Aug 2012 13:50:30 +0530
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <201208052354.18978.heiko@sntech.de>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <1343826351-8756-2-git-send-email-p.paneri@samsung.com>
 <201208052354.18978.heiko@sntech.de>
Message-ID: <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>

Hi Heiko,

On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de> wrote:
> Hi Praveen,
>
> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> smdk6410 and smdkv310. More SoCs can be brought under later.
>
> Looks cool.
Thanks
>
> From what I've seen the phy controllers on newer Samsung SoCs are still
> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at some
> point after the driver has settled, I'll find the time to add support for
> these to the phy driver.
Yes! that's great.
>
> Out of curiosity, what does the "sec" in sec_usbphy for?
Its Samsung Electronics Co. :)

Praveen
>
>
>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>
> Acked-by: Heiko Stuebner <heiko at sntech.de>
>
>
> Heiko
>
>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/sec_usbphy.c                       |  354
>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h                       |
>>  48 +++
>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>  create mode 100644
>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>> 100644 drivers/usb/phy/sec_usbphy.c
>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
>> 100644
>> index 0000000..fefd9c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -0,0 +1,9 @@
>> +* Samsung's usb phy transceiver
>> +
>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> +s3c-hsotg usb device controller.
>> +
>> +Required properties:
>> +- compatible : should be "samsung,exynos4210-usbphy"
>> +- reg : base physical address of the phy registers and length of memory
>> mapped +      region.
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index e7cf84f..abbebe2 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>
>>         To compile this driver as a module, choose M here: the
>>         module will be called isp1301.
>> +
>> +config SEC_USBPHY
>> +       bool "Samsung USB PHY controller Driver"
>> +       depends on USB_S3C_HSOTG
>> +       select USB_OTG_UTILS
>> +       help
>> +         Enable this to support Samsung USB phy controller for samsung
>> +         SoCs.
>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> index eca095b..6bb66f0 100644
>> --- a/drivers/usb/phy/Makefile
>> +++ b/drivers/usb/phy/Makefile
>> @@ -5,3 +5,4 @@
>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>
>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
>> new file mode 100644
>> index 0000000..33119eb
>> --- /dev/null
>> +++ b/drivers/usb/phy/sec_usbphy.c
>> @@ -0,0 +1,354 @@
>> +/* linux/drivers/usb/phy/sec_usbphy.c
>> + *
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + *              http://www.samsung.com
>> + *
>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> + *
>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>> controller + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> +*/
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/usb/otg.h>
>> +#include <linux/platform_data/s3c-hsotg.h>
>> +
>> +#include "sec_usbphy.h"
>> +
>> +enum sec_cpu_type {
>> +     TYPE_S3C64XX,
>> +     TYPE_EXYNOS4210,
>> +};
>> +
>> +/*
>> + * struct sec_usbphy - transceiver driver state
>> + * @phy: transceiver structure
>> + * @plat: platform data
>> + * @dev: The parent device supplied to the probe function
>> + * @clk: usb phy clock
>> + * @regs: usb phy register memory base
>> + * @cpu_type: machine identifier
>> + */
>> +struct sec_usbphy {
>> +     struct usb_phy  phy;
>> +     struct s3c_usbphy_plat *plat;
>> +     struct device   *dev;
>> +     struct clk      *clk;
>> +     void __iomem    *regs;
>> +     int             cpu_type;
>> +};
>> +
>> +#define phy_to_sec(x)                container_of((x), struct sec_usbphy, phy)
>> +
>> +/*
>> + * Enables or disables the phy clock
>> + * returns 0 on success else the error
>> + */
>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>> +{
>> +     if (on) {
>> +             if (!sec->clk) {
>> +                     sec->clk = clk_get(sec->dev, "otg");
>> +                     if (IS_ERR(sec->clk)) {
>> +                             dev_err(sec->dev, "Failed to get otg clock\n");
>> +                             return PTR_ERR(sec->clk);
>> +                     }
>> +             }
>> +             clk_enable(sec->clk);
>> +     } else {
>> +             clk_disable(sec->clk);
>> +             clk_put(sec->clk);
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +/*
>> + * Returns reference clock frequency
>> + */
>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>> +{
>> +     struct clk *ref_clk;
>> +     int refclk_freq = 0;
>> +
>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>> +     if (IS_ERR(ref_clk)) {
>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>> +             return PTR_ERR(ref_clk);
>> +     }
>> +
>> +     switch (clk_get_rate(ref_clk)) {
>> +     case 12 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> +             break;
>> +     case 24 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> +             break;
>> +     default:
>> +     case 48 * MHZ:
>> +             /* default reference clock */
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> +             break;
>> +     }
>> +     clk_put(ref_clk);
>> +
>> +     return refclk_freq;
>> +}
>> +
>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>> +{
>> +     void __iomem *regs = sec->regs;
>> +     u32 phypwr;
>> +     u32 phyclk;
>> +     u32 rstcon;
>> +
>> +     /* set clock frequency for PLL */
>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +     rstcon = readl(regs + S3C_RSTCON);
>> +
>> +     switch (sec->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     writel(phyclk, regs + S3C_PHYCLK);
>> +     /* set to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +     /* reset all ports of PHY and Link */
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +     udelay(10);
>> +     rstcon &= ~S3C_RSTCON_PHY;
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +}
>> +
>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>> +{
>> +     void __iomem *regs = sec->regs;
>> +     u32 phypwr;
>> +
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +
>> +     switch (sec->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     /* unset to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy initialization
>> + */
>> +static int sec_usbphy_init(struct usb_phy *phy)
>> +{
>> +     struct sec_usbphy *sec;
>> +     int ret = 0;
>> +
>> +     sec = phy_to_sec(phy);
>> +
>> +     /* Enable the phy clock */
>> +     ret = sec_usbphy_clk_control(sec, true);
>> +     if (ret) {
>> +             dev_err(sec->dev, "phy clock enable failed\n");
>> +             return ret;
>> +     }
>> +
>> +     /* Disable phy isolation */
>> +     if (sec->plat && sec->plat->pmu_isolation)
>> +             sec->plat->pmu_isolation(false);
>> +
>> +     /* Initialize usb phy registers */
>> +     sec_usbphy_enable(sec);
>> +     return ret;
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy shutdown
>> + */
>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>> +{
>> +     struct sec_usbphy *sec;
>> +
>> +     sec = phy_to_sec(phy);
>> +
>> +     /* De-initialize usb phy registers */
>> +     sec_usbphy_disable(sec);
>> +
>> +     /* Enable phy isolation */
>> +     if (sec->plat && sec->plat->pmu_isolation)
>> +             sec->plat->pmu_isolation(true);
>> +
>> +     /* Disable the phy clock */
>> +     sec_usbphy_clk_control(sec, false);
>> +}
>> +
>> +static const struct of_device_id sec_usbphy_dt_match[];
>> +
>> +static inline int sec_usbphy_get_driver_data(struct platform_device *pdev)
>> +{
>> +#ifdef CONFIG_OF
>> +     int data;
>> +     if (pdev->dev.of_node) {
>> +             const struct of_device_id *match;
>> +             match = of_match_node(sec_usbphy_dt_match, pdev->dev.of_node);
>> +             data = (int) match->data;
>> +             return data;
>> +     }
>> +#endif
>> +     return platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>> +{
>> +     struct sec_usbphy *sec;
>> +     struct s3c_usbphy_plat *pdata;
>> +     struct device *dev = &pdev->dev;
>> +     struct resource *phy_mem;
>> +     void __iomem    *phy_base;
>> +     int     ret;
>> +
>> +     pdata = pdev->dev.platform_data;
>> +     if (!pdata) {
>> +             dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
>> +             return -EINVAL;
>> +     }
>> +
>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     if (!phy_mem) {
>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>> +             return -ENODEV;
>> +     }
>> +
>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>> +     if (!phy_base) {
>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>> +             return -ENXIO;
>> +     }
>> +
>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>> +     if (!sec)
>> +             return -ENOMEM;
>> +
>> +     sec->dev                = &pdev->dev;
>> +     sec->plat               = pdata;
>> +     sec->regs               = phy_base;
>> +     sec->phy.dev            = sec->dev;
>> +     sec->phy.label          = "sec-usbphy";
>> +     sec->phy.init           = sec_usbphy_init;
>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>> +
>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>> +     if (ret)
>> +             goto err;
>> +
>> +     platform_set_drvdata(pdev, sec);
>> +
>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>> +err:
>> +     return ret;
>> +}
>> +
>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>> +{
>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>> +
>> +     usb_remove_phy(&sec->phy);
>> +
>> +     if (sec->clk) {
>> +             clk_put(sec->clk);
>> +             sec->clk = NULL;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>> +     {
>> +             .compatible = "samsung,s3c64xx-usbphy",
>> +             .data = (void *)TYPE_S3C64XX,
>> +     }, {
>> +             .compatible = "samsung,exynos4210-usbphy",
>> +             .data = (void *)TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>> +#else
>> +#define sec_usbphy_dt_match NULL
>> +#endif
>> +
>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>> +     {
>> +             .name           = "s3c64xx-usbphy",
>> +             .driver_data    = TYPE_S3C64XX,
>> +     }, {
>> +             .name           = "exynos4210-usbphy",
>> +             .driver_data    = TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>> +
>> +static struct platform_driver sec_usbphy_driver = {
>> +     .probe          = sec_usbphy_probe,
>> +     .remove         = __devexit_p(sec_usbphy_remove),
>> +     .id_table       = sec_usbphy_driver_ids,
>> +     .driver         = {
>> +             .name   = "sec-usbphy",
>> +             .owner  = THIS_MODULE,
>> +             .of_match_table = sec_usbphy_dt_match,
>> +     },
>> +};
>> +
>> +static int __init sec_usbphy_driver_init(void)
>> +{
>> +     return platform_driver_register(&sec_usbphy_driver);
>> +}
>> +subsys_initcall(sec_usbphy_driver_init);
>> +
>> +static void __exit sec_usbphy_driver_exit(void)
>> +{
>> +     return platform_driver_unregister(&sec_usbphy_driver);
>> +}
>> +module_exit(sec_usbphy_driver_exit);
>> +
>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:sec-usbphy");
>> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
>> new file mode 100644
>> index 0000000..06e81d4
>> --- /dev/null
>> +++ b/drivers/usb/phy/sec_usbphy.h
>> @@ -0,0 +1,48 @@
>> +/*
>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify
>> it + * under  the terms of  the GNU General  Public License as published
>> by the + * Free Software Foundation;  either version 2 of the  License, or
>> (at your + * option) any later version.
>> + */
>> +
>> +#ifndef __SEC_USBPHY_H
>> +#define __SEC_USBPHY_H
>> +
>> +#define S3C_PHYPWR                           (0x00)
>> +
>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>> +/* For Exynos4 */
>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>> +
>> +#define S3C_PHYCLK                           (0x04)
>> +
>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>> +
>> +#define S3C_RSTCON                           (0x08)
>> +
>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>> +#define S3C_RSTCON_PHY                               (1 << 0)
>> +
>> +#ifndef MHZ
>> +#define MHZ (1000*1000)
>> +#endif
>> +
>> +#endif /* __SEC_USBPHY_H */
>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>> --- a/include/linux/platform_data/s3c-hsotg.h
>> +++ b/include/linux/platform_data/s3c-hsotg.h
>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>  };
>>
>> +struct s3c_usbphy_plat {
>> +     void (*pmu_isolation)(int on);
>> +};
>> +
>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>
>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From kyungmin.park at samsung.com  Mon Aug  6 04:23:52 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Mon, 6 Aug 2012 17:23:52 +0900
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <1343826351-8756-2-git-send-email-p.paneri@samsung.com>
 <201208052354.18978.heiko@sntech.de>
 <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
Message-ID: <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>

Hi Praveen,

On 8/6/12, Praveen Paneri <p.paneri at samsung.com> wrote:
> Hi Heiko,
>
> On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de> wrote:
>> Hi Praveen,
>>
>> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>
>> Looks cool.
> Thanks
>>
>> From what I've seen the phy controllers on newer Samsung SoCs are still
>> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>> some
>> point after the driver has settled, I'll find the time to add support for
>> these to the phy driver.
> Yes! that's great.
>>
>> Out of curiosity, what does the "sec" in sec_usbphy for?
> Its Samsung Electronics Co. :)
I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
'sec' prefix for samsung drivers.

Thank you,
Kyungmin Park
>
> Praveen
>>
>>
>>
>>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>>
>> Acked-by: Heiko Stuebner <heiko at sntech.de>
>>
>>
>> Heiko
>>
>>
>>> ---
>>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>>  drivers/usb/phy/Kconfig                            |    8 +
>>>  drivers/usb/phy/Makefile                           |    1 +
>>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>> |
>>>  48 +++
>>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>>> 100644 drivers/usb/phy/sec_usbphy.c
>>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file mode
>>> 100644
>>> index 0000000..fefd9c8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> @@ -0,0 +1,9 @@
>>> +* Samsung's usb phy transceiver
>>> +
>>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>>> +s3c-hsotg usb device controller.
>>> +
>>> +Required properties:
>>> +- compatible : should be "samsung,exynos4210-usbphy"
>>> +- reg : base physical address of the phy registers and length of memory
>>> mapped +      region.
>>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>> index e7cf84f..abbebe2 100644
>>> --- a/drivers/usb/phy/Kconfig
>>> +++ b/drivers/usb/phy/Kconfig
>>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>>
>>>         To compile this driver as a module, choose M here: the
>>>         module will be called isp1301.
>>> +
>>> +config SEC_USBPHY
>>> +       bool "Samsung USB PHY controller Driver"
>>> +       depends on USB_S3C_HSOTG
>>> +       select USB_OTG_UTILS
>>> +       help
>>> +         Enable this to support Samsung USB phy controller for samsung
>>> +         SoCs.
>>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>> index eca095b..6bb66f0 100644
>>> --- a/drivers/usb/phy/Makefile
>>> +++ b/drivers/usb/phy/Makefile
>>> @@ -5,3 +5,4 @@
>>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>>
>>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>> diff --git a/drivers/usb/phy/sec_usbphy.c b/drivers/usb/phy/sec_usbphy.c
>>> new file mode 100644
>>> index 0000000..33119eb
>>> --- /dev/null
>>> +++ b/drivers/usb/phy/sec_usbphy.c
>>> @@ -0,0 +1,354 @@
>>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>> + *
>>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>> + *              http://www.samsung.com
>>> + *
>>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>> + *
>>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>> controller + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>> +*/
>>> +
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/err.h>
>>> +#include <linux/io.h>
>>> +#include <linux/of.h>
>>> +#include <linux/usb/otg.h>
>>> +#include <linux/platform_data/s3c-hsotg.h>
>>> +
>>> +#include "sec_usbphy.h"
>>> +
>>> +enum sec_cpu_type {
>>> +     TYPE_S3C64XX,
>>> +     TYPE_EXYNOS4210,
>>> +};
>>> +
>>> +/*
>>> + * struct sec_usbphy - transceiver driver state
>>> + * @phy: transceiver structure
>>> + * @plat: platform data
>>> + * @dev: The parent device supplied to the probe function
>>> + * @clk: usb phy clock
>>> + * @regs: usb phy register memory base
>>> + * @cpu_type: machine identifier
>>> + */
>>> +struct sec_usbphy {
>>> +     struct usb_phy  phy;
>>> +     struct s3c_usbphy_plat *plat;
>>> +     struct device   *dev;
>>> +     struct clk      *clk;
>>> +     void __iomem    *regs;
>>> +     int             cpu_type;
>>> +};
>>> +
>>> +#define phy_to_sec(x)                container_of((x), struct
>>> sec_usbphy, phy)
>>> +
>>> +/*
>>> + * Enables or disables the phy clock
>>> + * returns 0 on success else the error
>>> + */
>>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>> +{
>>> +     if (on) {
>>> +             if (!sec->clk) {
>>> +                     sec->clk = clk_get(sec->dev, "otg");
>>> +                     if (IS_ERR(sec->clk)) {
>>> +                             dev_err(sec->dev, "Failed to get otg
>>> clock\n");
>>> +                             return PTR_ERR(sec->clk);
>>> +                     }
>>> +             }
>>> +             clk_enable(sec->clk);
>>> +     } else {
>>> +             clk_disable(sec->clk);
>>> +             clk_put(sec->clk);
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +/*
>>> + * Returns reference clock frequency
>>> + */
>>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>> +{
>>> +     struct clk *ref_clk;
>>> +     int refclk_freq = 0;
>>> +
>>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>> +     if (IS_ERR(ref_clk)) {
>>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>> +             return PTR_ERR(ref_clk);
>>> +     }
>>> +
>>> +     switch (clk_get_rate(ref_clk)) {
>>> +     case 12 * MHZ:
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>> +             break;
>>> +     case 24 * MHZ:
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>> +             break;
>>> +     default:
>>> +     case 48 * MHZ:
>>> +             /* default reference clock */
>>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>> +             break;
>>> +     }
>>> +     clk_put(ref_clk);
>>> +
>>> +     return refclk_freq;
>>> +}
>>> +
>>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>> +{
>>> +     void __iomem *regs = sec->regs;
>>> +     u32 phypwr;
>>> +     u32 phyclk;
>>> +     u32 rstcon;
>>> +
>>> +     /* set clock frequency for PLL */
>>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> +     rstcon = readl(regs + S3C_RSTCON);
>>> +
>>> +     switch (sec->cpu_type) {
>>> +     case TYPE_S3C64XX:
>>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>> +             rstcon |= S3C_RSTCON_PHY;
>>> +             break;
>>> +     case TYPE_EXYNOS4210:
>>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>> +             rstcon |= S3C_RSTCON_PHY;
>>> +     default:
>>> +             break;
>>> +     }
>>> +
>>> +     writel(phyclk, regs + S3C_PHYCLK);
>>> +     /* set to normal of PHY0 */
>>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> +     /* reset all ports of PHY and Link */
>>> +     writel(rstcon, regs + S3C_RSTCON);
>>> +     udelay(10);
>>> +     rstcon &= ~S3C_RSTCON_PHY;
>>> +     writel(rstcon, regs + S3C_RSTCON);
>>> +}
>>> +
>>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>> +{
>>> +     void __iomem *regs = sec->regs;
>>> +     u32 phypwr;
>>> +
>>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> +
>>> +     switch (sec->cpu_type) {
>>> +     case TYPE_S3C64XX:
>>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>> +             break;
>>> +     case TYPE_EXYNOS4210:
>>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>> +     default:
>>> +             break;
>>> +     }
>>> +
>>> +     /* unset to normal of PHY0 */
>>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> +}
>>> +
>>> +/*
>>> + * The function passed to the usb driver for phy initialization
>>> + */
>>> +static int sec_usbphy_init(struct usb_phy *phy)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +     int ret = 0;
>>> +
>>> +     sec = phy_to_sec(phy);
>>> +
>>> +     /* Enable the phy clock */
>>> +     ret = sec_usbphy_clk_control(sec, true);
>>> +     if (ret) {
>>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>> +             return ret;
>>> +     }
>>> +
>>> +     /* Disable phy isolation */
>>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> +             sec->plat->pmu_isolation(false);
>>> +
>>> +     /* Initialize usb phy registers */
>>> +     sec_usbphy_enable(sec);
>>> +     return ret;
>>> +}
>>> +
>>> +/*
>>> + * The function passed to the usb driver for phy shutdown
>>> + */
>>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +
>>> +     sec = phy_to_sec(phy);
>>> +
>>> +     /* De-initialize usb phy registers */
>>> +     sec_usbphy_disable(sec);
>>> +
>>> +     /* Enable phy isolation */
>>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> +             sec->plat->pmu_isolation(true);
>>> +
>>> +     /* Disable the phy clock */
>>> +     sec_usbphy_clk_control(sec, false);
>>> +}
>>> +
>>> +static const struct of_device_id sec_usbphy_dt_match[];
>>> +
>>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>>> *pdev)
>>> +{
>>> +#ifdef CONFIG_OF
>>> +     int data;
>>> +     if (pdev->dev.of_node) {
>>> +             const struct of_device_id *match;
>>> +             match = of_match_node(sec_usbphy_dt_match,
>>> pdev->dev.of_node);
>>> +             data = (int) match->data;
>>> +             return data;
>>> +     }
>>> +#endif
>>> +     return platform_get_device_id(pdev)->driver_data;
>>> +}
>>> +
>>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>>> +{
>>> +     struct sec_usbphy *sec;
>>> +     struct s3c_usbphy_plat *pdata;
>>> +     struct device *dev = &pdev->dev;
>>> +     struct resource *phy_mem;
>>> +     void __iomem    *phy_base;
>>> +     int     ret;
>>> +
>>> +     pdata = pdev->dev.platform_data;
>>> +     if (!pdata) {
>>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>> __func__);
>>> +             return -EINVAL;
>>> +     }
>>> +
>>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +     if (!phy_mem) {
>>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>> +             return -ENODEV;
>>> +     }
>>> +
>>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>> +     if (!phy_base) {
>>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>>> +             return -ENXIO;
>>> +     }
>>> +
>>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>> +     if (!sec)
>>> +             return -ENOMEM;
>>> +
>>> +     sec->dev                = &pdev->dev;
>>> +     sec->plat               = pdata;
>>> +     sec->regs               = phy_base;
>>> +     sec->phy.dev            = sec->dev;
>>> +     sec->phy.label          = "sec-usbphy";
>>> +     sec->phy.init           = sec_usbphy_init;
>>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>> +
>>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>> +     if (ret)
>>> +             goto err;
>>> +
>>> +     platform_set_drvdata(pdev, sec);
>>> +
>>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>>> +err:
>>> +     return ret;
>>> +}
>>> +
>>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>> +{
>>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>> +
>>> +     usb_remove_phy(&sec->phy);
>>> +
>>> +     if (sec->clk) {
>>> +             clk_put(sec->clk);
>>> +             sec->clk = NULL;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +#ifdef CONFIG_OF
>>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>> +     {
>>> +             .compatible = "samsung,s3c64xx-usbphy",
>>> +             .data = (void *)TYPE_S3C64XX,
>>> +     }, {
>>> +             .compatible = "samsung,exynos4210-usbphy",
>>> +             .data = (void *)TYPE_EXYNOS4210,
>>> +     },
>>> +     {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>> +#else
>>> +#define sec_usbphy_dt_match NULL
>>> +#endif
>>> +
>>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>> +     {
>>> +             .name           = "s3c64xx-usbphy",
>>> +             .driver_data    = TYPE_S3C64XX,
>>> +     }, {
>>> +             .name           = "exynos4210-usbphy",
>>> +             .driver_data    = TYPE_EXYNOS4210,
>>> +     },
>>> +     {},
>>> +};
>>> +
>>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>> +
>>> +static struct platform_driver sec_usbphy_driver = {
>>> +     .probe          = sec_usbphy_probe,
>>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>> +     .id_table       = sec_usbphy_driver_ids,
>>> +     .driver         = {
>>> +             .name   = "sec-usbphy",
>>> +             .owner  = THIS_MODULE,
>>> +             .of_match_table = sec_usbphy_dt_match,
>>> +     },
>>> +};
>>> +
>>> +static int __init sec_usbphy_driver_init(void)
>>> +{
>>> +     return platform_driver_register(&sec_usbphy_driver);
>>> +}
>>> +subsys_initcall(sec_usbphy_driver_init);
>>> +
>>> +static void __exit sec_usbphy_driver_exit(void)
>>> +{
>>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>> +}
>>> +module_exit(sec_usbphy_driver_exit);
>>> +
>>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_ALIAS("platform:sec-usbphy");
>>> diff --git a/drivers/usb/phy/sec_usbphy.h b/drivers/usb/phy/sec_usbphy.h
>>> new file mode 100644
>>> index 0000000..06e81d4
>>> --- /dev/null
>>> +++ b/drivers/usb/phy/sec_usbphy.h
>>> @@ -0,0 +1,48 @@
>>> +/*
>>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>> + *
>>> + * This program is free software; you can redistribute  it and/or
>>> modify
>>> it + * under  the terms of  the GNU General  Public License as published
>>> by the + * Free Software Foundation;  either version 2 of the  License,
>>> or
>>> (at your + * option) any later version.
>>> + */
>>> +
>>> +#ifndef __SEC_USBPHY_H
>>> +#define __SEC_USBPHY_H
>>> +
>>> +#define S3C_PHYPWR                           (0x00)
>>> +
>>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>> +/* For Exynos4 */
>>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>> +
>>> +#define S3C_PHYCLK                           (0x04)
>>> +
>>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>> +
>>> +#define S3C_RSTCON                           (0x08)
>>> +
>>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>> +
>>> +#ifndef MHZ
>>> +#define MHZ (1000*1000)
>>> +#endif
>>> +
>>> +#endif /* __SEC_USBPHY_H */
>>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>>> --- a/include/linux/platform_data/s3c-hsotg.h
>>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>>  };
>>>
>>> +struct s3c_usbphy_plat {
>>> +     void (*pmu_isolation)(int on);
>>> +};
>>> +
>>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>>
>>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>
>> --
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>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
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>


From balbi at ti.com  Mon Aug  6 04:38:45 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 11:38:45 +0300
Subject: [PATCH 1/4] arm/dts: omap5-evm: Add I2C support
In-Reply-To: <501C08CB.3060701@mvista.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-2-git-send-email-sourav.poddar@ti.com>
 <501C08CB.3060701@mvista.com>
Message-ID: <20120806083843.GA17612@arwen.pp.htv.fi>

Hi,

On Fri, Aug 03, 2012 at 09:22:19PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 08/03/2012 04:38 PM, Sourav Poddar wrote:
> 
> > Add I2C data node in omap5 device tree file.
> 
> > Tested on omap5430 sdp.
> 
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > Acked-by: Felipe Balbi <balbi at ti.com>
> > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> > ---
> >  arch/arm/boot/dts/omap5.dtsi |   35 +++++++++++++++++++++++++++++++++++
> >  1 files changed, 35 insertions(+), 0 deletions(-)
> 
> > diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> > index 57e5270..6b68dfe 100644
> > --- a/arch/arm/boot/dts/omap5.dtsi
> > +++ b/arch/arm/boot/dts/omap5.dtsi
> > @@ -145,6 +145,41 @@
> >  			#interrupt-cells = <1>;
> >  		};
> >  
> > +		i2c1: i2c at 48070000 {
> > +			compatible = "ti,omap4-i2c";
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			ti,hwmods = "i2c1";
> 
>    Address postfix in the node name and no "reg" property?

that's because of the ti,hwmods attribute. OMAP is still not entirely
converted to DT and there's this weird ti,hwmods attribute. OMAP's hwmod
framework will fill up register addresses, irqs, etc when the device is
created. Oh well...

-- 
balbi
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From lars at metafoo.de  Mon Aug  6 04:49:13 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Mon, 06 Aug 2012 10:49:13 +0200
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <1344007721-11595-3-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-3-git-send-email-marex@denx.de>
Message-ID: <501F8509.1030903@metafoo.de>

On 08/03/2012 05:28 PM, Marek Vasut wrote:
> This driver is very basic. It supports userland trigger, buffer and
> raw access to channels. The support for delay channels is missing
> altogether.

Looks mostly good to me. Some comments inline.

I think you need to provide a documentation for the devicetree binding, even
though it's a rather simple binding.

> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Jonathan Cameron <jic23 at kernel.org>
> Cc: Juergen Beisert <jbe at pengutronix.de>
> Cc: Lars-Peter Clausen <lars at metafoo.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Wolfgang Denk <wd at denx.de>
> ---
>  drivers/staging/iio/adc/Kconfig     |   12 +
>  drivers/staging/iio/adc/Makefile    |    1 +
>  drivers/staging/iio/adc/mxs-lradc.c |  591 +++++++++++++++++++++++++++++++++++
>  3 files changed, 604 insertions(+)
>  create mode 100644 drivers/staging/iio/adc/mxs-lradc.c
> 
> V2: Use delay channel 0 in case of buffered sampling so the samples are deployed
>     continuously.
>     Disallow RAW sampling while buffered mode is enabled to simplify code.
> 
> diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig
> index 67711b7..97ca697 100644
> --- a/drivers/staging/iio/adc/Kconfig
> +++ b/drivers/staging/iio/adc/Kconfig
[...]
> + */
> +static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
> +			const struct iio_chan_spec *chan,
> +			int *val, int *val2, long m)
> +{
> [...]
> +
> +	init_completion(&lradc->completion);

This should rather be INIT_COMPLETION. init_completion should only called
once in probe, since it will reinitialize the spinlock which opens up race
conditions.

> [...]
> +
> +	/* Wait for completion on the channel, 1 second max. */
> +	ret = wait_for_completion_killable_timeout(&lradc->completion,
> +						msecs_to_jiffies(1000));

msecs_to_jiffies(1000) = HZ, but I guess both is OK.

> [...]
> +}
[...]
> +
> +static int __devinit mxs_lradc_probe(struct platform_device *pdev)
> +{
> [...]
> +
> +	/* Grab all IRQ sources */
> +	for (i = 0; i < 13; i++) {
> +		lradc->irq[i] = platform_get_irq(pdev, i);
> +		if (lradc->irq[i] < 0) {
> +			ret = -EINVAL;
> +			goto err_addr;
> +		}
> +
> +		ret = devm_request_irq(dev, lradc->irq[i],
> +					mxs_lradc_handle_irq, 0,
> +					mxs_lradc_irq_name[i], iio);

devm_request_irq is a bit dangerous as long we do not have a
devm_iio_device_alloc. The IRQ will only be freed after the memory for the
IIO device has been freed, which means there is a slight window where the
IRQ could fire although the memory has already been freed.

> +		if (ret)
> +			goto err_addr;
> +	}
> +
> +	dev_set_drvdata(&pdev->dev, iio);

platform_set_drvdata

> +
> +	init_completion(&lradc->completion);
> +	mutex_init(&lradc->lock);
> +

[...]


From linus.walleij at stericsson.com  Mon Aug  6 04:52:26 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 6 Aug 2012 10:52:26 +0200
Subject: [PATCH] ARM: ux500: resurrect I2C platform data
Message-ID: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Commit:
98582d9562b4bea6b0eb6e2bfafcd3fab3b60ccb
"ARM: ux500: Remove unused i2c platform_data initialisation code"

Deleted platform data intialization code that was used,
not unused as indicated in the commit. The boot log (without
devicetree) now looks like this:

nmk-i2c nmk-i2c.0: no platform data
nmk-i2c nmk-i2c.1: no platform data
nmk-i2c nmk-i2c.2: no platform data
nmk-i2c nmk-i2c.3: no platform data

And no I2C drivers register anymore.

Take this opportunity to bump the i2c bus speed to 400kHz.
Some recent discussion revealed inconsistency in the board file
for the MOP500 family. The board can very well do 400kHz on
the I2C busses, so make it do that.

Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Cc: Lee Jones <lee.jones at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c | 39 ++++++++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8674a89..dbb9946 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -327,12 +327,43 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
 	},
 };
 
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm)	\
+static struct nmk_i2c_controller u8500_i2c##id##_data = { \
+	/*				\
+	 * slave data setup time, which is	\
+	 * 250 ns,100ns,10ns which is 14,6,2	\
+	 * respectively for a 48 Mhz	\
+	 * i2c clock			\
+	 */				\
+	.slsu		= _slsu,	\
+	/* Tx FIFO threshold */		\
+	.tft		= _tft,		\
+	/* Rx FIFO threshold */		\
+	.rft		= _rft,		\
+	/* std. mode operation */	\
+	.clk_freq	= clk,		\
+	/* Slave response timeout(ms) */\
+	.timeout	= t_out,	\
+	.sm		= _sm,		\
+}
+
+/*
+ * The board uses 4 i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 1 resp. 8 and fast
+ * mode of operation
+ */
+U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 400000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 400000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(2,	0xe, 1, 8, 400000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(3,	0xe, 1, 8, 400000, 200, I2C_FREQ_MODE_FAST);
+
 static void __init mop500_i2c_init(struct device *parent)
 {
-	db8500_add_i2c0(parent, NULL);
-	db8500_add_i2c1(parent, NULL);
-	db8500_add_i2c2(parent, NULL);
-	db8500_add_i2c3(parent, NULL);
+	db8500_add_i2c0(parent, &u8500_i2c0_data);
+	db8500_add_i2c1(parent, &u8500_i2c1_data);
+	db8500_add_i2c2(parent, &u8500_i2c2_data);
+	db8500_add_i2c3(parent, &u8500_i2c3_data);
 }
 
 static struct gpio_keys_button mop500_gpio_keys[] = {
-- 
1.7.11.3



From balbi at ti.com  Mon Aug  6 04:49:30 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 11:49:30 +0300
Subject: [PATCH v6 01/11] drivers: usb: otg: add a new driver for omap
 usb2 phy
In-Reply-To: <CAAe_U6K15Nm5aNs2Vn71G7ELZWka1zB2E3VGZWTc0VjyViJ6Yw@mail.gmail.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-2-git-send-email-kishon@ti.com>
 <20120803132708.GC8269@arwen.pp.htv.fi>
 <CAAe_U6K15Nm5aNs2Vn71G7ELZWka1zB2E3VGZWTc0VjyViJ6Yw@mail.gmail.com>
Message-ID: <20120806084928.GD17551@arwen.pp.htv.fi>

Hi,

On Fri, Aug 03, 2012 at 08:01:44PM +0530, ABRAHAM, KISHON VIJAY wrote:
> >> +     return 0;
> >> +}
> >> +
> >> +#ifdef CONFIG_PM_RUNTIME
> >> +
> >> +static int omap_usb2_runtime_suspend(struct device *dev)
> >> +{
> >> +     struct platform_device  *pdev = to_platform_device(dev);
> >> +     struct omap_usb *phy = platform_get_drvdata(pdev);
> >> +
> >> +     clk_disable(phy->wkupclk);
> >
> > weird. I would expect the wakeup clock to be enabled on suspend and
> > disabled on resume. Isn't this causing any unbalanced disable warnings ?
> 
> Even I was expecting the wakeup clock to be enabled on suspend but if
> we have this enabled coreaon domain is never
> gated and core does not hit low power state. btw Why do think this is
> unbalanced?

because you never do a clk_enable() on probe(), so on your first
suspend, you will disable the clock without having enabled it before,
no? Unless pm_runtime forces a runtime_resume() when you call
pm_runtime_enable()...

> >> +static int omap_usb2_runtime_resume(struct device *dev)
> >> +{
> >> +     u32 ret = 0;
> >> +     struct platform_device  *pdev = to_platform_device(dev);
> >> +     struct omap_usb *phy = platform_get_drvdata(pdev);
> >> +
> >> +     ret = clk_enable(phy->wkupclk);
> >> +     if (ret < 0)
> >> +             dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
> >> +
> >> +     return ret;
> >> +}
> >> +
> >> +static const struct dev_pm_ops omap_usb2_pm_ops = {
> >> +     SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
> >> +             NULL)
> >
> > only runtime ? What about static suspend ? We need this to work also
> > after a traditional echo mem > /sys/power/state ;-)
> 
> The static suspend case is handled by users of this phy using
> set_suspend hooks.

I'm not sure if that's too wise, what if your user enabled USB, but
for whatever reason loaded only the phy driver and not musb or dwc3. It
will fail, right ?

-- 
balbi
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From balbi at ti.com  Mon Aug  6 04:52:22 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 11:52:22 +0300
Subject: [PATCH v6 00/11] omap: musb: Add device tree support
In-Reply-To: <1343639400-28725-1-git-send-email-kishon@ti.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
Message-ID: <20120806085221.GE17551@arwen.pp.htv.fi>

Hi,

On Mon, Jul 30, 2012 at 02:39:49PM +0530, Kishon Vijay Abraham I wrote:
> This patch series adds device tree support for MUSB and device
> tree support for all the related modules to get MUSB working in
> OMAP platform.
> 
> A new omap-usb2 phy driver has been added (with only dt suppport)
> to perform phy configurations. Previously this configuration was
> performed by twl6030, using pdata function pointers.
> 
> With the addition of omap-usb2 to perform phy configurations,
> twl6030 is made as a comparator driver to detect VBUS and ID events
> and notify it to the glue layer.
> 
> musb core is _NOT_ yet converted to support device tree support as it
> would need lot of driver re-design because of its enormous use of
> function pointers. That will be in _TO DO_ list.
> 
> Changes from v5:
> minor cleanups like checking for return value in get_sync and few changes
> in the documentation has been done.
> 
> Changes from v4:
> duplicate getting of 'mode' property is removed in omap-musb glue.
> 
> Changes from v3:
> remove the address in the node name of usb_otg_hs since the usb_otg_hs
> node doesn't have a reg property. Thanks Ajay Gupta for finding this.
> 
> Changes from v2:
> Fixed Sergei's comment to remove *0x* prefix in usb2phy at 0x4a0ad080
> 
> Changes from v1:
> * Fixed Rajendra Nayak comments (regulator naming, compatible naming of
> musb and other minor cleanups.)
> * It's agreed to have ocp2scp in drivers/bus and usb2 phy is a child of
> ocp2scp, the documentation is updated accordingly.
> 
> Changes from RFC:
> Removed the dependency on [RFC PATCH 00/11] OMAP System Control Module.
> Writing to control module register is now handled in otg driver itself.
> Once the system control module driver get upstreamed, I'll send a patch
> to make use of API's in control module driver to write to control
> module register.
> 
> This series was developed on
> git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv
> 
> This patch series depends on
> [PATCH 0/2] omap: add ocp2scp as a bus driver
> 
> Performed MUSB device mode testing on OMAP4 panda, OMAP4 SDP
> and OMAP3 beagle.
> 
> Kishon Vijay Abraham I (11):
>   drivers: usb: otg: add a new driver for omap usb2 phy
>   arm/dts: omap: Add omap-usb2 dt data
>   drivers: usb: otg: make twl6030_usb as a comparator driver to
>     omap_usb2
>   arm: omap: hwmod: add a new addr space in otg for writing to control
>     module
>   drivers: usb: twl6030: Add dt support for twl6030 usb
>   arm/dts: Add twl6030-usb data
>   drivers: usb: twl4030: Add device tree support for twl4030 usb
>   arm/dts: Add twl4030-usb data
>   drivers: usb: musb: Add device tree support for omap musb glue
>   arm/dts: omap: Add usb_otg and glue data
>   arm: omap: phy: remove unused functions from omap-phy-internal.c

When you send your next series, can you please split the stuff based on
their dependencies or at least note here what depends on what ? I mean,
I cannot take the DT patches without an Acked-by Grant and Tony, but the
drivers themselves I could take queue them since they're already in good
shape ;-)

Maybe just start the series with patches without dependencies on one
another, and the rest of the series would be ones that need to go
together, or something. That'll help me ;-)

-- 
balbi
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From heiko at sntech.de  Mon Aug  6 05:23:17 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 6 Aug 2012 11:23:17 +0200
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
 <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>
Message-ID: <201208061123.18065.heiko@sntech.de>

Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
> Hi Praveen,
> 
> On 8/6/12, Praveen Paneri <p.paneri at samsung.com> wrote:
> > Hi Heiko,
> > 
> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de> wrote:
> >> Hi Praveen,
> >> 
> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
> >> 
> >> Looks cool.
> > 
> > Thanks
> > 
> >> From what I've seen the phy controllers on newer Samsung SoCs are still
> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
> >> some
> >> point after the driver has settled, I'll find the time to add support
> >> for these to the phy driver.
> > 
> > Yes! that's great.
> > 
> >> Out of curiosity, what does the "sec" in sec_usbphy for?
> > 
> > Its Samsung Electronics Co. :)
> 
> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
> 'sec' prefix for samsung drivers.

I'd second that. All new generic samsung drivers look like this (i.e. gpio-
samsung, pwm-samsung).

Just checked the datasheets again. This general phy type is used in some form 
down to the S3C2443, so I'd prefer something with samsung in the name :-)


Heiko

> 
> Thank you,
> Kyungmin Park
> 
> > Praveen
> > 
> >>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> >> 
> >> Acked-by: Heiko Stuebner <heiko at sntech.de>
> >> 
> >> 
> >> Heiko
> >> 
> >>> ---
> >>> 
> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
> >>>  drivers/usb/phy/Kconfig                            |    8 +
> >>>  drivers/usb/phy/Makefile                           |    1 +
> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
> >>> 
> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
> >>> 
> >>>  48 +++
> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
> >>>  create mode 100644
> >>> 
> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
> >>> 100644 drivers/usb/phy/sec_usbphy.c
> >>> 
> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
> >>> 
> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
> >>> mode 100644
> >>> index 0000000..fefd9c8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> >>> @@ -0,0 +1,9 @@
> >>> +* Samsung's usb phy transceiver
> >>> +
> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
> >>> +s3c-hsotg usb device controller.
> >>> +
> >>> +Required properties:
> >>> +- compatible : should be "samsung,exynos4210-usbphy"
> >>> +- reg : base physical address of the phy registers and length of
> >>> memory mapped +      region.
> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> >>> index e7cf84f..abbebe2 100644
> >>> --- a/drivers/usb/phy/Kconfig
> >>> +++ b/drivers/usb/phy/Kconfig
> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
> >>> 
> >>>         To compile this driver as a module, choose M here: the
> >>>         module will be called isp1301.
> >>> 
> >>> +
> >>> +config SEC_USBPHY
> >>> +       bool "Samsung USB PHY controller Driver"
> >>> +       depends on USB_S3C_HSOTG
> >>> +       select USB_OTG_UTILS
> >>> +       help
> >>> +         Enable this to support Samsung USB phy controller for samsung
> >>> +         SoCs.
> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> >>> index eca095b..6bb66f0 100644
> >>> --- a/drivers/usb/phy/Makefile
> >>> +++ b/drivers/usb/phy/Makefile
> >>> @@ -5,3 +5,4 @@
> >>> 
> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
> >>>  
> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
> >>> 
> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
> >>> index 0000000..33119eb
> >>> --- /dev/null
> >>> +++ b/drivers/usb/phy/sec_usbphy.c
> >>> @@ -0,0 +1,354 @@
> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
> >>> + *
> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> >>> + *              http://www.samsung.com
> >>> + *
> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
> >>> + *
> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
> >>> controller + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> modify + * it under the terms of the GNU General Public License
> >>> version 2 as + * published by the Free Software Foundation.
> >>> + *
> >>> + * This program is distributed in the hope that it will be useful,
> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> + * GNU General Public License for more details.
> >>> + *
> >>> + * You should have received a copy of the GNU General Public License
> >>> + * along with this program; if not, write to the Free Software
> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> >>> +*/
> >>> +
> >>> +#include <linux/module.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/clk.h>
> >>> +#include <linux/delay.h>
> >>> +#include <linux/err.h>
> >>> +#include <linux/io.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/usb/otg.h>
> >>> +#include <linux/platform_data/s3c-hsotg.h>
> >>> +
> >>> +#include "sec_usbphy.h"
> >>> +
> >>> +enum sec_cpu_type {
> >>> +     TYPE_S3C64XX,
> >>> +     TYPE_EXYNOS4210,
> >>> +};
> >>> +
> >>> +/*
> >>> + * struct sec_usbphy - transceiver driver state
> >>> + * @phy: transceiver structure
> >>> + * @plat: platform data
> >>> + * @dev: The parent device supplied to the probe function
> >>> + * @clk: usb phy clock
> >>> + * @regs: usb phy register memory base
> >>> + * @cpu_type: machine identifier
> >>> + */
> >>> +struct sec_usbphy {
> >>> +     struct usb_phy  phy;
> >>> +     struct s3c_usbphy_plat *plat;
> >>> +     struct device   *dev;
> >>> +     struct clk      *clk;
> >>> +     void __iomem    *regs;
> >>> +     int             cpu_type;
> >>> +};
> >>> +
> >>> +#define phy_to_sec(x)                container_of((x), struct
> >>> sec_usbphy, phy)
> >>> +
> >>> +/*
> >>> + * Enables or disables the phy clock
> >>> + * returns 0 on success else the error
> >>> + */
> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
> >>> +{
> >>> +     if (on) {
> >>> +             if (!sec->clk) {
> >>> +                     sec->clk = clk_get(sec->dev, "otg");
> >>> +                     if (IS_ERR(sec->clk)) {
> >>> +                             dev_err(sec->dev, "Failed to get otg
> >>> clock\n");
> >>> +                             return PTR_ERR(sec->clk);
> >>> +                     }
> >>> +             }
> >>> +             clk_enable(sec->clk);
> >>> +     } else {
> >>> +             clk_disable(sec->clk);
> >>> +             clk_put(sec->clk);
> >>> +     }
> >>> +
> >>> +     return 0;
> >>> +}
> >>> +
> >>> +/*
> >>> + * Returns reference clock frequency
> >>> + */
> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
> >>> +{
> >>> +     struct clk *ref_clk;
> >>> +     int refclk_freq = 0;
> >>> +
> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
> >>> +     if (IS_ERR(ref_clk)) {
> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
> >>> +             return PTR_ERR(ref_clk);
> >>> +     }
> >>> +
> >>> +     switch (clk_get_rate(ref_clk)) {
> >>> +     case 12 * MHZ:
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> >>> +             break;
> >>> +     case 24 * MHZ:
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> >>> +             break;
> >>> +     default:
> >>> +     case 48 * MHZ:
> >>> +             /* default reference clock */
> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> >>> +             break;
> >>> +     }
> >>> +     clk_put(ref_clk);
> >>> +
> >>> +     return refclk_freq;
> >>> +}
> >>> +
> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
> >>> +{
> >>> +     void __iomem *regs = sec->regs;
> >>> +     u32 phypwr;
> >>> +     u32 phyclk;
> >>> +     u32 rstcon;
> >>> +
> >>> +     /* set clock frequency for PLL */
> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
> >>> +     phypwr = readl(regs + S3C_PHYPWR);
> >>> +     rstcon = readl(regs + S3C_RSTCON);
> >>> +
> >>> +     switch (sec->cpu_type) {
> >>> +     case TYPE_S3C64XX:
> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
> >>> +             rstcon |= S3C_RSTCON_PHY;
> >>> +             break;
> >>> +     case TYPE_EXYNOS4210:
> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
> >>> +             rstcon |= S3C_RSTCON_PHY;
> >>> +     default:
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     writel(phyclk, regs + S3C_PHYCLK);
> >>> +     /* set to normal of PHY0 */
> >>> +     writel(phypwr, regs + S3C_PHYPWR);
> >>> +     /* reset all ports of PHY and Link */
> >>> +     writel(rstcon, regs + S3C_RSTCON);
> >>> +     udelay(10);
> >>> +     rstcon &= ~S3C_RSTCON_PHY;
> >>> +     writel(rstcon, regs + S3C_RSTCON);
> >>> +}
> >>> +
> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
> >>> +{
> >>> +     void __iomem *regs = sec->regs;
> >>> +     u32 phypwr;
> >>> +
> >>> +     phypwr = readl(regs + S3C_PHYPWR);
> >>> +
> >>> +     switch (sec->cpu_type) {
> >>> +     case TYPE_S3C64XX:
> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
> >>> +             break;
> >>> +     case TYPE_EXYNOS4210:
> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
> >>> +     default:
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     /* unset to normal of PHY0 */
> >>> +     writel(phypwr, regs + S3C_PHYPWR);
> >>> +}
> >>> +
> >>> +/*
> >>> + * The function passed to the usb driver for phy initialization
> >>> + */
> >>> +static int sec_usbphy_init(struct usb_phy *phy)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +     int ret = 0;
> >>> +
> >>> +     sec = phy_to_sec(phy);
> >>> +
> >>> +     /* Enable the phy clock */
> >>> +     ret = sec_usbphy_clk_control(sec, true);
> >>> +     if (ret) {
> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
> >>> +             return ret;
> >>> +     }
> >>> +
> >>> +     /* Disable phy isolation */
> >>> +     if (sec->plat && sec->plat->pmu_isolation)
> >>> +             sec->plat->pmu_isolation(false);
> >>> +
> >>> +     /* Initialize usb phy registers */
> >>> +     sec_usbphy_enable(sec);
> >>> +     return ret;
> >>> +}
> >>> +
> >>> +/*
> >>> + * The function passed to the usb driver for phy shutdown
> >>> + */
> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +
> >>> +     sec = phy_to_sec(phy);
> >>> +
> >>> +     /* De-initialize usb phy registers */
> >>> +     sec_usbphy_disable(sec);
> >>> +
> >>> +     /* Enable phy isolation */
> >>> +     if (sec->plat && sec->plat->pmu_isolation)
> >>> +             sec->plat->pmu_isolation(true);
> >>> +
> >>> +     /* Disable the phy clock */
> >>> +     sec_usbphy_clk_control(sec, false);
> >>> +}
> >>> +
> >>> +static const struct of_device_id sec_usbphy_dt_match[];
> >>> +
> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
> >>> *pdev)
> >>> +{
> >>> +#ifdef CONFIG_OF
> >>> +     int data;
> >>> +     if (pdev->dev.of_node) {
> >>> +             const struct of_device_id *match;
> >>> +             match = of_match_node(sec_usbphy_dt_match,
> >>> pdev->dev.of_node);
> >>> +             data = (int) match->data;
> >>> +             return data;
> >>> +     }
> >>> +#endif
> >>> +     return platform_get_device_id(pdev)->driver_data;
> >>> +}
> >>> +
> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
> >>> +{
> >>> +     struct sec_usbphy *sec;
> >>> +     struct s3c_usbphy_plat *pdata;
> >>> +     struct device *dev = &pdev->dev;
> >>> +     struct resource *phy_mem;
> >>> +     void __iomem    *phy_base;
> >>> +     int     ret;
> >>> +
> >>> +     pdata = pdev->dev.platform_data;
> >>> +     if (!pdata) {
> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
> >>> __func__);
> >>> +             return -EINVAL;
> >>> +     }
> >>> +
> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> +     if (!phy_mem) {
> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
> >>> +             return -ENODEV;
> >>> +     }
> >>> +
> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
> >>> +     if (!phy_base) {
> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
> >>> +             return -ENXIO;
> >>> +     }
> >>> +
> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
> >>> +     if (!sec)
> >>> +             return -ENOMEM;
> >>> +
> >>> +     sec->dev                = &pdev->dev;
> >>> +     sec->plat               = pdata;
> >>> +     sec->regs               = phy_base;
> >>> +     sec->phy.dev            = sec->dev;
> >>> +     sec->phy.label          = "sec-usbphy";
> >>> +     sec->phy.init           = sec_usbphy_init;
> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
> >>> +
> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
> >>> +     if (ret)
> >>> +             goto err;
> >>> +
> >>> +     platform_set_drvdata(pdev, sec);
> >>> +
> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
> >>> +err:
> >>> +     return ret;
> >>> +}
> >>> +
> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
> >>> +{
> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
> >>> +
> >>> +     usb_remove_phy(&sec->phy);
> >>> +
> >>> +     if (sec->clk) {
> >>> +             clk_put(sec->clk);
> >>> +             sec->clk = NULL;
> >>> +     }
> >>> +
> >>> +     return 0;
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_OF
> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
> >>> +     {
> >>> +             .compatible = "samsung,s3c64xx-usbphy",
> >>> +             .data = (void *)TYPE_S3C64XX,
> >>> +     }, {
> >>> +             .compatible = "samsung,exynos4210-usbphy",
> >>> +             .data = (void *)TYPE_EXYNOS4210,
> >>> +     },
> >>> +     {},
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
> >>> +#else
> >>> +#define sec_usbphy_dt_match NULL
> >>> +#endif
> >>> +
> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
> >>> +     {
> >>> +             .name           = "s3c64xx-usbphy",
> >>> +             .driver_data    = TYPE_S3C64XX,
> >>> +     }, {
> >>> +             .name           = "exynos4210-usbphy",
> >>> +             .driver_data    = TYPE_EXYNOS4210,
> >>> +     },
> >>> +     {},
> >>> +};
> >>> +
> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
> >>> +
> >>> +static struct platform_driver sec_usbphy_driver = {
> >>> +     .probe          = sec_usbphy_probe,
> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
> >>> +     .id_table       = sec_usbphy_driver_ids,
> >>> +     .driver         = {
> >>> +             .name   = "sec-usbphy",
> >>> +             .owner  = THIS_MODULE,
> >>> +             .of_match_table = sec_usbphy_dt_match,
> >>> +     },
> >>> +};
> >>> +
> >>> +static int __init sec_usbphy_driver_init(void)
> >>> +{
> >>> +     return platform_driver_register(&sec_usbphy_driver);
> >>> +}
> >>> +subsys_initcall(sec_usbphy_driver_init);
> >>> +
> >>> +static void __exit sec_usbphy_driver_exit(void)
> >>> +{
> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
> >>> +}
> >>> +module_exit(sec_usbphy_driver_exit);
> >>> +
> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
> >>> +MODULE_LICENSE("GPL");
> >>> +MODULE_ALIAS("platform:sec-usbphy");
> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
> >>> index 0000000..06e81d4
> >>> --- /dev/null
> >>> +++ b/drivers/usb/phy/sec_usbphy.h
> >>> @@ -0,0 +1,48 @@
> >>> +/*
> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> >>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
> >>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
> >>> + *
> >>> + * This program is free software; you can redistribute  it and/or
> >>> modify
> >>> it + * under  the terms of  the GNU General  Public License as
> >>> published by the + * Free Software Foundation;  either version 2 of
> >>> the  License, or
> >>> (at your + * option) any later version.
> >>> + */
> >>> +
> >>> +#ifndef __SEC_USBPHY_H
> >>> +#define __SEC_USBPHY_H
> >>> +
> >>> +#define S3C_PHYPWR                           (0x00)
> >>> +
> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
> >>> +/* For Exynos4 */
> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
> >>> +
> >>> +#define S3C_PHYCLK                           (0x04)
> >>> +
> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
> >>> +
> >>> +#define S3C_RSTCON                           (0x08)
> >>> +
> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
> >>> +
> >>> +#ifndef MHZ
> >>> +#define MHZ (1000*1000)
> >>> +#endif
> >>> +
> >>> +#endif /* __SEC_USBPHY_H */
> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
> >>> --- a/include/linux/platform_data/s3c-hsotg.h
> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
> >>> 
> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
> >>>  
> >>>  };
> >>> 
> >>> +struct s3c_usbphy_plat {
> >>> +     void (*pmu_isolation)(int on);
> >>> +};
> >>> +
> >>> 
> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
> >>> 
> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
> >>> 
> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
> >> 
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> >> the body of a message to majordomo at vger.kernel.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html



From klightspeed at killerwolves.net  Mon Aug  6 05:25:09 2012
From: klightspeed at killerwolves.net (Ben Peddell)
Date: Mon, 06 Aug 2012 19:25:09 +1000
Subject: problems with external initramfs passed to device tree kernel
In-Reply-To: <CAB9O=CMADa26benQCkEoLOKKTGNeExjvFeVkFe4HLVi-W=o=Jg@mail.gmail.com>
References: <CAB9O=CMADa26benQCkEoLOKKTGNeExjvFeVkFe4HLVi-W=o=Jg@mail.gmail.com>
Message-ID: <501F8D75.8070108@killerwolves.net>

On 13/06/2012 9:12 AM, John Linn wrote:
> I'm not sure this is specific to ARM, but that's what I'm on so I 
> thought I'd ask.  I'm also running a device tree kernel.  I've
> tried it on 3.0 and 3.3 kernels.
> 
> I'm seeing where I have to remove CONFIG_BLK_DEV_RAM from the
> kernel to get it to boot with an external initramfs image. It says
> the image is not?good (junk in it), but it boots.  The same image
> boots fine when built into the kernel using INITRAMFS_SOURCE, even
> with BLK_DEV_RAM in the kernel.
> 
> I've done quite a bit of digging at the init/initramfs.c and it's
> not obvious to me where the issue lies (user error probably).
> 
> Any thoughts would be appreciated.

If the size of the initramfs image is set in either devicetree or the
initrd= kernel parameter, and is larger than the actual initramfs
image is, then the kernel throws the image away if it's followed by
anything other than null bytes.  U-boot doesn't initialize the RAM to
zeroes, so the initramfs will be followed by whatever was in RAM -
usually 0xFF with zero bits here and there, or the decayed contents
before the previous shutdown if the machine was off for a very short time.

I will follow up with a patch that should remedy this issue.  Please
let me know if there's a better way to do this.

-- 
Ben Peddell
IT Support Bowen, Collinsville and Proserpine Catholic schools
http://klightspeed.killerwolves.net/


From kishon at ti.com  Mon Aug  6 05:25:53 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Mon, 6 Aug 2012 14:55:53 +0530
Subject: [PATCH v6 00/11] omap: musb: Add device tree support
In-Reply-To: <20120806085221.GE17551@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <20120806085221.GE17551@arwen.pp.htv.fi>
Message-ID: <CAAe_U6KsyRppEd4Z__t448SD=SzvWa2u7pec86rwn6KW8tuB+Q@mail.gmail.com>

On Mon, Aug 6, 2012 at 2:22 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Mon, Jul 30, 2012 at 02:39:49PM +0530, Kishon Vijay Abraham I wrote:
>> This patch series adds device tree support for MUSB and device
>> tree support for all the related modules to get MUSB working in
>> OMAP platform.
>>
>> A new omap-usb2 phy driver has been added (with only dt suppport)
>> to perform phy configurations. Previously this configuration was
>> performed by twl6030, using pdata function pointers.
>>
>> With the addition of omap-usb2 to perform phy configurations,
>> twl6030 is made as a comparator driver to detect VBUS and ID events
>> and notify it to the glue layer.
>>
>> musb core is _NOT_ yet converted to support device tree support as it
>> would need lot of driver re-design because of its enormous use of
>> function pointers. That will be in _TO DO_ list.
>>
>> Changes from v5:
>> minor cleanups like checking for return value in get_sync and few changes
>> in the documentation has been done.
>>
>> Changes from v4:
>> duplicate getting of 'mode' property is removed in omap-musb glue.
>>
>> Changes from v3:
>> remove the address in the node name of usb_otg_hs since the usb_otg_hs
>> node doesn't have a reg property. Thanks Ajay Gupta for finding this.
>>
>> Changes from v2:
>> Fixed Sergei's comment to remove *0x* prefix in usb2phy at 0x4a0ad080
>>
>> Changes from v1:
>> * Fixed Rajendra Nayak comments (regulator naming, compatible naming of
>> musb and other minor cleanups.)
>> * It's agreed to have ocp2scp in drivers/bus and usb2 phy is a child of
>> ocp2scp, the documentation is updated accordingly.
>>
>> Changes from RFC:
>> Removed the dependency on [RFC PATCH 00/11] OMAP System Control Module.
>> Writing to control module register is now handled in otg driver itself.
>> Once the system control module driver get upstreamed, I'll send a patch
>> to make use of API's in control module driver to write to control
>> module register.
>>
>> This series was developed on
>> git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv
>>
>> This patch series depends on
>> [PATCH 0/2] omap: add ocp2scp as a bus driver
>>
>> Performed MUSB device mode testing on OMAP4 panda, OMAP4 SDP
>> and OMAP3 beagle.
>>
>> Kishon Vijay Abraham I (11):
>>   drivers: usb: otg: add a new driver for omap usb2 phy
>>   arm/dts: omap: Add omap-usb2 dt data
>>   drivers: usb: otg: make twl6030_usb as a comparator driver to
>>     omap_usb2
>>   arm: omap: hwmod: add a new addr space in otg for writing to control
>>     module
>>   drivers: usb: twl6030: Add dt support for twl6030 usb
>>   arm/dts: Add twl6030-usb data
>>   drivers: usb: twl4030: Add device tree support for twl4030 usb
>>   arm/dts: Add twl4030-usb data
>>   drivers: usb: musb: Add device tree support for omap musb glue
>>   arm/dts: omap: Add usb_otg and glue data
>>   arm: omap: phy: remove unused functions from omap-phy-internal.c
>
> When you send your next series, can you please split the stuff based on
> their dependencies or at least note here what depends on what ? I mean,
> I cannot take the DT patches without an Acked-by Grant and Tony, but the
> drivers themselves I could take queue them since they're already in good
> shape ;-)
>
> Maybe just start the series with patches without dependencies on one
> another, and the rest of the series would be ones that need to go
> together, or something. That'll help me ;-)

Ok Felipe.

Thanks
Kishon


From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:27:36 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 6 Aug 2012 11:27:36 +0200
Subject: [PATCH] arm: add documentation describing Marvell families of SoC
In-Reply-To: <201208060813.01524.arnd@arndb.de>
References: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201208060813.01524.arnd@arndb.de>
Message-ID: <20120806112736.6d441561@skate>

Le Mon, 6 Aug 2012 08:13:01 +0000,
Arnd Bergmann <arnd at arndb.de> a ?crit :

> Acked-by: Arnd Bergmann <arnd at arndb.de>

Thanks. Am I supposed to resend this to Rob Landley <rob at landley.net>,
who is apparently the Documentation/ maintainer, or can you push it
through the arm-soc tree since it is Documentation/arm/ material?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sourav.poddar at ti.com  Mon Aug  6 05:28:44 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 6 Aug 2012 14:58:44 +0530
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
Message-ID: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>

There is an automatic binding done for I2C devices in the of_i2c core
code. So, DT will be able to bind to any I2C device using the
already existing table: MODULE_DEVICE_TABLE(i2c, bmp085_id).

Tested on omap5430 evm.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/misc/bmp085-i2c.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/bmp085-i2c.c b/drivers/misc/bmp085-i2c.c
index 9943971..a4f33c9 100644
--- a/drivers/misc/bmp085-i2c.c
+++ b/drivers/misc/bmp085-i2c.c
@@ -57,12 +57,6 @@ static int bmp085_i2c_remove(struct i2c_client *client)
 	return bmp085_remove(&client->dev);
 }
 
-static const struct of_device_id bmp085_of_match[] = {
-	{ .compatible = "bosch,bmp085", },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, bmp085_of_match);
-
 static const struct i2c_device_id bmp085_id[] = {
 	{ BMP085_NAME, 0 },
 	{ "bmp180", 0 },
@@ -74,7 +68,6 @@ static struct i2c_driver bmp085_i2c_driver = {
 	.driver = {
 		.owner	= THIS_MODULE,
 		.name	= BMP085_NAME,
-		.of_match_table = bmp085_of_match
 	},
 	.id_table	= bmp085_id,
 	.probe		= bmp085_i2c_probe,
-- 
1.7.1



From balbi at ti.com  Mon Aug  6 05:30:34 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 12:30:34 +0300
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
In-Reply-To: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
References: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120806093033.GH17551@arwen.pp.htv.fi>

On Mon, Aug 06, 2012 at 02:58:44PM +0530, Sourav Poddar wrote:
> There is an automatic binding done for I2C devices in the of_i2c core
> code. So, DT will be able to bind to any I2C device using the
> already existing table: MODULE_DEVICE_TABLE(i2c, bmp085_id).
> 
> Tested on omap5430 evm.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  drivers/misc/bmp085-i2c.c |    7 -------
>  1 files changed, 0 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/misc/bmp085-i2c.c b/drivers/misc/bmp085-i2c.c
> index 9943971..a4f33c9 100644
> --- a/drivers/misc/bmp085-i2c.c
> +++ b/drivers/misc/bmp085-i2c.c
> @@ -57,12 +57,6 @@ static int bmp085_i2c_remove(struct i2c_client *client)
>  	return bmp085_remove(&client->dev);
>  }
>  
> -static const struct of_device_id bmp085_of_match[] = {
> -	{ .compatible = "bosch,bmp085", },
> -	{ },
> -};
> -MODULE_DEVICE_TABLE(of, bmp085_of_match);
> -
>  static const struct i2c_device_id bmp085_id[] = {
>  	{ BMP085_NAME, 0 },
>  	{ "bmp180", 0 },
> @@ -74,7 +68,6 @@ static struct i2c_driver bmp085_i2c_driver = {
>  	.driver = {
>  		.owner	= THIS_MODULE,
>  		.name	= BMP085_NAME,
> -		.of_match_table = bmp085_of_match
>  	},
>  	.id_table	= bmp085_id,
>  	.probe		= bmp085_i2c_probe,
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

-- 
balbi
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From klightspeed at killerwolves.net  Mon Aug  6 05:32:51 2012
From: klightspeed at killerwolves.net (Ben Peddell)
Date: Mon,  6 Aug 2012 19:32:51 +1000 (EST)
Subject: [PATCH] initramfs: handle trailing junk after valid image
In-Reply-To: <501F8D75.8070108@killerwolves.net>
References: <CAB9O=CMADa26benQCkEoLOKKTGNeExjvFeVkFe4HLVi-W=o=Jg@mail.gmail.com>, 
 <501F8D75.8070108@killerwolves.net>
Message-ID: <20120806093251.0528E77A0D@aristotle.killerwolves.net>

The initramfs handling since commit df37bd15 has been rejecting
valid images that have garbage after them.  For example, on an
architecture where the initramfs address and size are specified
as a kernel parameter (specifically unicore32 and arm), specifying
e.g. initrd=0x01000000,4M will not work unless the image is padded
with nulls to 4MiB.  This is unlikely to occur if the user is using
this parameter to work around a bug in the bootloader.

---
 init/initramfs.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/init/initramfs.c b/init/initramfs.c
index 84c6bf1..26c2cb1 100644
--- a/init/initramfs.c
+++ b/init/initramfs.c
@@ -467,6 +467,9 @@ static char * __init unpack_to_rootfs(char *buf, unsigned len)
 					 compress_name);
 				message = msg_buf;
 			}
+		} else if (state == Reset) {
+			my_inptr = len;
+			pr_warn("%s: junk at end of compressed archive\n", __func__);
 		} else
 			error("junk in compressed archive");
 		if (state != Reset)
-- 
1.7.3.4



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:16 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:16 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
Message-ID: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>

Andrew, Jason, Gr?gory,

Here is a small patch set that introduces basic support for address
decoding on Armada 370 and Armada XP. The aim of this basic support is
essentially to be able to configure a window to remap the BootROM,
which is needed to startup the secondary CPUs for the SMP support.

As we had discussed already, the address decoding configuration is not
described in the Device Tree, it is for now hardcoded on a per-SoC
basis. We might later discuss how to extend this to the Device Tree.

This patch set has five patches:

 (*) First patch reworks the addr-map code to use void __iomem * where
     appropriate instead of u32, as per the suggestion of Arnd
     Bergmann.

 (*) Second patch introducing PLAT_ORION_LEGACY, which allows the
     Marvell 370/XP platforms to be part of PLAT_ORION, and therefore
     re-use the existing address decoding code.

 (*) Third patch making a small change to an address decoding
     structure so that we can define at runtime the virtual address of
     the configuration registers. This is needed as on Armada 370/XP
     the address decoding "controller" is declared in the Device Tree.

 (*) Fourth patch adding the 370/XP address decoding code itself. For
     now, it only maps the BootROM on Armada XP.

 (*) Fifth path adding the necessary DT code to instantiate the
     address decoding "controller".

Changes since v2:
 * Remove one more useless (void __iomem *) cast in the Armada 370/XP
   addr-map.c file, as noticed by Arnd Bergmann.

Changes since v1:
 * Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
 * Add Acked-by on patches 2->5 from Gr?gory Cl?ment

Thanks,

Thomas Petazzoni



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:17 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:17 +0200
Subject: [PATCH 1/5] arm: plat-orion: use 'void __iomem *' in addr-map code
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344246141-23931-2-git-send-email-thomas.petazzoni@free-electrons.com>

Use 'void __iomem *' instead of u32 where appropriate in the addr-map
code. It requires adding a few casts in SoC-specific addr-map.c files,
but those casts will disappear once those SoC are migrated to the
device tree, in which case the address will come from the DT instead
of from #define values.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-dove/addr-map.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c           |    5 +++--
 arch/arm/mach-mv78xx0/addr-map.c            |    4 ++--
 arch/arm/mach-orion5x/addr-map.c            |    5 +++--
 arch/arm/plat-orion/addr-map.c              |   11 ++++-------
 arch/arm/plat-orion/include/plat/addr-map.h |    4 ++--
 6 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 2a06c01..adb428e 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i)
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180..2b27de6 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -41,7 +41,7 @@
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d7..bac31e4 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
 	 */
 	if (mv78xx0_core_index() == 0)
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU0_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU0_BASE);
 	else
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU1_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d..bfe4f10 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
 static struct orion_addr_map_cfg addr_map_cfg __initdata = {
 	.num_wins = 8,
 	.cpu_win_can_remap = cpu_win_can_remap,
-	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (void __iomem *) ORION5X_BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89..a7b8060 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-	return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+	return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base)
+					const void __iomem *ddr_window_cpu_base)
 {
-	void __iomem *addr;
 	int i;
 	int cs;
 
 	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-	addr = (void __iomem *)ddr_window_cpu_base;
-
 	for (i = 0, cs = 0; i < 4; i++) {
-		u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-		u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+		u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+		u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
 		/*
 		 * Chip select enabled?
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f7..0a746fd 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	const u32 bridge_virt_base;
+	void __iomem * const bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
 				const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base);
+					const void __iomem *ddr_window_cpu_base);
 #endif
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:19 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:19 +0200
Subject: [PATCH 3/5] arm: plat-orion: make bridge_virt_base non-const to
 support DT use case
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344246141-23931-4-git-send-email-thomas.petazzoni@free-electrons.com>

For the Armada 370 and XP SoCs where the DT is used, we need to fill
at runtime the bridge_virt_base field on the
orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this
field.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/plat-orion/include/plat/addr-map.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index 0a746fd..ec63e4a 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	void __iomem * const bridge_virt_base;
+	void __iomem *bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:21 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:21 +0200
Subject: [PATCH 5/5] arm: mvebu: add address decoding controller to the DT
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344246141-23931-6-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..16cc82c 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+		addr-decoding at d0020000 {
+			compatible = "marvell,armada-addr-decoding-controller";
+			reg = <0xd0020000 0x258>;
+		};
 	};
 };
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:20 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:20 +0200
Subject: [PATCH 4/5] arm: mvebu: add basic address decoding support to Armada
 370/XP
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344246141-23931-5-git-send-email-thomas.petazzoni@free-electrons.com>

This commit adds basic support for address decoding configuration for
the Armada 370 and Armada XP SoCs, re-using the infrastructure
provided in plat-orion.

For now, only a BootROM window is configured on Armada XP, which is
needed to get the non-boot CPUs started and is therefore a requirement
for SMP support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/mach-mvebu/Makefile   |    2 +-
 arch/arm/mach-mvebu/addr-map.c |  134 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mvebu/addr-map.c

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8..2143558 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,2 @@
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 0000000..fe454a4
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS	1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1		3
+#define ARMADA_XP_TARGET_PCIE_0_2	4
+#define ARMADA_XP_TARGET_ETH0		7
+#define ARMADA_XP_TARGET_PCIE_1_3	8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+	/*
+	 * Window for the BootROM, needed for SMP on Armada XP
+	 */
+	{ 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+	  ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+	/* End marker */
+	{ -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+	{ .compatible = "marvell,armada-addr-decoding-controller" },
+	{ /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+	unsigned int offset;
+
+	/* The register layout is a bit annoying and the below code
+	 * tries to cope with it.
+	 * - At offset 0x0, there are the registers for the first 8
+	 *   windows, with 4 registers of 32 bits per window (ctrl,
+	 *   base, remap low, remap high)
+	 * - Then at offset 0x80, there is a hole of 0x10 bytes for
+	 *   the internal registers base address and internal units
+	 *   sync barrier register.
+	 * - Then at offset 0x90, there the registers for 12
+	 *   windows, with only 2 registers of 32 bits per window
+	 *   (ctrl, base).
+	 */
+	if (win < 8)
+		offset = (win << 4);
+	else
+		offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+	return cfg->bridge_virt_base + offset;
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+	.num_wins = 20,
+	.remappable_wins = 8,
+	.win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+	struct device_node *np;
+	void __iomem *mbus_unit_addr_decoding_base;
+	void __iomem *sdram_addr_decoding_base;
+
+	np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+	if (!np)
+		return -ENODEV;
+
+	mbus_unit_addr_decoding_base = of_iomap(np, 0);
+	BUG_ON(!mbus_unit_addr_decoding_base);
+
+	sdram_addr_decoding_base =
+		mbus_unit_addr_decoding_base +
+		ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+	addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+	/*
+	 * Disable, clear and configure windows.
+	 */
+	if (of_machine_is_compatible("marvell,armadaxp"))
+		orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+	else if (of_machine_is_compatible("marvell,armada370"))
+		orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+	else {
+		pr_err("Unsupported SoC\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    sdram_addr_decoding_base);
+	return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Mon Aug  6 05:42:18 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon,  6 Aug 2012 11:42:18 +0200
Subject: [PATCH 2/5] arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
 config option
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344246141-23931-3-git-send-email-thomas.petazzoni@free-electrons.com>

Until now, the PLAT_ORION configuration option was common to all the
Marvell EBU SoCs, and selecting this option had the effect of enabling
the MPP code, GPIO code, address decoding and PCIe code from
plat-orion, as well as providing access to driver-specific header
files from plat-orion/include.

However, the Armada 370 and XP SoCs will not use the MPP and GPIO code
(instead some proper pinctrl and gpio drivers are in preparation), and
generally, we want to move away from plat-orion and instead have
everything in mach-mvebu.

That said, in the mean time, we want to leverage the driver-specific
headers as well as the address decoding code, so we introduce
PLAT_ORION_LEGACY. The older Marvell SoCs need to select
PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select
PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it
automatically selects PLAT_ORION.

Then, with just PLAT_ORION, you have the address decoding code plus
the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you
gain the old MPP, GPIO and PCIe code.

Again, this is only a temporary solution until we make all Marvell EBU
platforms converge into the mach-mvebu directory. This solution avoids
duplicating the existing address decoding code into mach-mvebu.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig             |   13 +++++++++----
 arch/arm/plat-orion/Makefile |    9 ++++-----
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..a2b6f74 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PLAT_ORION
 	help
 	  Support for the Marvell SoC Family with device tree support
 
@@ -583,7 +584,7 @@ config ARCH_DOVE
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
@@ -594,7 +595,7 @@ config ARCH_KIRKWOOD
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.
@@ -621,7 +622,7 @@ config ARCH_MV78XX0
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.
@@ -634,7 +635,7 @@ config ARCH_ORION5X
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Orion 5x series SoCs:
 	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1154,6 +1155,10 @@ config PLAT_ORION
 	select IRQ_DOMAIN
 	select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+	bool
+	select PLAT_ORION
+
 config PLAT_PXA
 	bool
 
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f..1251e5b 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,9 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m	:=
-obj-n	:=
-obj-	:=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 05:44:42 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Mon, 6 Aug 2012 15:14:42 +0530
Subject: [PATCH v6 01/11] drivers: usb: otg: add a new driver for omap
 usb2 phy
In-Reply-To: <20120806084928.GD17551@arwen.pp.htv.fi>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-2-git-send-email-kishon@ti.com>
 <20120803132708.GC8269@arwen.pp.htv.fi>
 <CAAe_U6K15Nm5aNs2Vn71G7ELZWka1zB2E3VGZWTc0VjyViJ6Yw@mail.gmail.com>
 <20120806084928.GD17551@arwen.pp.htv.fi>
Message-ID: <CAAe_U6LhfrRk7PP-Td7BTXPngo7+chvTp4LwwKR_GbsjE4jNJQ@mail.gmail.com>

Hi Felipe,

On Mon, Aug 6, 2012 at 2:19 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Fri, Aug 03, 2012 at 08:01:44PM +0530, ABRAHAM, KISHON VIJAY wrote:
>> >> +     return 0;
>> >> +}
>> >> +
>> >> +#ifdef CONFIG_PM_RUNTIME
>> >> +
>> >> +static int omap_usb2_runtime_suspend(struct device *dev)
>> >> +{
>> >> +     struct platform_device  *pdev = to_platform_device(dev);
>> >> +     struct omap_usb *phy = platform_get_drvdata(pdev);
>> >> +
>> >> +     clk_disable(phy->wkupclk);
>> >
>> > weird. I would expect the wakeup clock to be enabled on suspend and
>> > disabled on resume. Isn't this causing any unbalanced disable warnings ?
>>
>> Even I was expecting the wakeup clock to be enabled on suspend but if
>> we have this enabled coreaon domain is never
>> gated and core does not hit low power state. btw Why do think this is
>> unbalanced?
>
> because you never do a clk_enable() on probe(), so on your first
> suspend, you will disable the clock without having enabled it before,
> no? Unless pm_runtime forces a runtime_resume() when you call
> pm_runtime_enable()...
>
>> >> +static int omap_usb2_runtime_resume(struct device *dev)
>> >> +{
>> >> +     u32 ret = 0;
>> >> +     struct platform_device  *pdev = to_platform_device(dev);
>> >> +     struct omap_usb *phy = platform_get_drvdata(pdev);
>> >> +
>> >> +     ret = clk_enable(phy->wkupclk);
>> >> +     if (ret < 0)
>> >> +             dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
>> >> +
>> >> +     return ret;
>> >> +}
>> >> +
>> >> +static const struct dev_pm_ops omap_usb2_pm_ops = {
>> >> +     SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
>> >> +             NULL)
>> >
>> > only runtime ? What about static suspend ? We need this to work also
>> > after a traditional echo mem > /sys/power/state ;-)
>>
>> The static suspend case is handled by users of this phy using
>> set_suspend hooks.
>
> I'm not sure if that's too wise, what if your user enabled USB, but
> for whatever reason loaded only the phy driver and not musb or dwc3. It
> will fail, right ?

The enabling and disabling of phy is solely governed by usb controller
driver (musb/dwc3). So if you dont have musb/dwc3 loaded, the phy will
be for sure disabled.

Thanks
Kishon


From balbi at ti.com  Mon Aug  6 05:44:02 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 12:44:02 +0300
Subject: [PATCH v6 01/11] drivers: usb: otg: add a new driver for omap
 usb2 phy
In-Reply-To: <CAAe_U6LhfrRk7PP-Td7BTXPngo7+chvTp4LwwKR_GbsjE4jNJQ@mail.gmail.com>
References: <1343639400-28725-1-git-send-email-kishon@ti.com>
 <1343639400-28725-2-git-send-email-kishon@ti.com>
 <20120803132708.GC8269@arwen.pp.htv.fi>
 <CAAe_U6K15Nm5aNs2Vn71G7ELZWka1zB2E3VGZWTc0VjyViJ6Yw@mail.gmail.com>
 <20120806084928.GD17551@arwen.pp.htv.fi>
 <CAAe_U6LhfrRk7PP-Td7BTXPngo7+chvTp4LwwKR_GbsjE4jNJQ@mail.gmail.com>
Message-ID: <20120806094401.GI17551@arwen.pp.htv.fi>

On Mon, Aug 06, 2012 at 03:14:42PM +0530, ABRAHAM, KISHON VIJAY wrote:
> >> >> +static int omap_usb2_runtime_resume(struct device *dev)
> >> >> +{
> >> >> +     u32 ret = 0;
> >> >> +     struct platform_device  *pdev = to_platform_device(dev);
> >> >> +     struct omap_usb *phy = platform_get_drvdata(pdev);
> >> >> +
> >> >> +     ret = clk_enable(phy->wkupclk);
> >> >> +     if (ret < 0)
> >> >> +             dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
> >> >> +
> >> >> +     return ret;
> >> >> +}
> >> >> +
> >> >> +static const struct dev_pm_ops omap_usb2_pm_ops = {
> >> >> +     SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
> >> >> +             NULL)
> >> >
> >> > only runtime ? What about static suspend ? We need this to work also
> >> > after a traditional echo mem > /sys/power/state ;-)
> >>
> >> The static suspend case is handled by users of this phy using
> >> set_suspend hooks.
> >
> > I'm not sure if that's too wise, what if your user enabled USB, but
> > for whatever reason loaded only the phy driver and not musb or dwc3. It
> > will fail, right ?
> 
> The enabling and disabling of phy is solely governed by usb controller
> driver (musb/dwc3). So if you dont have musb/dwc3 loaded, the phy will
> be for sure disabled.

fair enough... that's ok then ;-)

-- 
balbi
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From p.paneri at samsung.com  Mon Aug  6 05:51:18 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Mon, 6 Aug 2012 15:21:18 +0530
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <201208061123.18065.heiko@sntech.de>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
 <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>
 <201208061123.18065.heiko@sntech.de>
Message-ID: <CAD6zSYPyRGgxVXFhcLSqjOpERq-jLrsqnjYNXM3jKsjymiLaTA@mail.gmail.com>

Hi,

On Mon, Aug 6, 2012 at 2:53 PM, Heiko St?bner <heiko at sntech.de> wrote:
> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>> Hi Praveen,
>>
>> On 8/6/12, Praveen Paneri <p.paneri at samsung.com> wrote:
>> > Hi Heiko,
>> >
>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de> wrote:
>> >> Hi Praveen,
>> >>
>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>> >>
>> >> Looks cool.
>> >
>> > Thanks
>> >
>> >> From what I've seen the phy controllers on newer Samsung SoCs are still
>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>> >> some
>> >> point after the driver has settled, I'll find the time to add support
>> >> for these to the phy driver.
>> >
>> > Yes! that's great.
>> >
>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>> >
>> > Its Samsung Electronics Co. :)
>>
>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>> 'sec' prefix for samsung drivers.
>
> I'd second that. All new generic samsung drivers look like this (i.e. gpio-
> samsung, pwm-samsung).
>
> Just checked the datasheets again. This general phy type is used in some form
> down to the S3C2443, so I'd prefer something with samsung in the name :-)
Yes! That makes sense. I will change the name to samsung_usbphy

Praveen
>
>
> Heiko
>
>>
>> Thank you,
>> Kyungmin Park
>>
>> > Praveen
>> >
>> >>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> >>
>> >> Acked-by: Heiko Stuebner <heiko at sntech.de>
>> >>
>> >>
>> >> Heiko
>> >>
>> >>> ---
>> >>>
>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>> >>>  drivers/usb/phy/Makefile                           |    1 +
>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>> >>>
>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>> >>>
>> >>>  48 +++
>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>> >>>  create mode 100644
>> >>>
>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>> >>>
>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>> >>> mode 100644
>> >>> index 0000000..fefd9c8
>> >>> --- /dev/null
>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> >>> @@ -0,0 +1,9 @@
>> >>> +* Samsung's usb phy transceiver
>> >>> +
>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> >>> +s3c-hsotg usb device controller.
>> >>> +
>> >>> +Required properties:
>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>> >>> +- reg : base physical address of the phy registers and length of
>> >>> memory mapped +      region.
>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> >>> index e7cf84f..abbebe2 100644
>> >>> --- a/drivers/usb/phy/Kconfig
>> >>> +++ b/drivers/usb/phy/Kconfig
>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>> >>>
>> >>>         To compile this driver as a module, choose M here: the
>> >>>         module will be called isp1301.
>> >>>
>> >>> +
>> >>> +config SEC_USBPHY
>> >>> +       bool "Samsung USB PHY controller Driver"
>> >>> +       depends on USB_S3C_HSOTG
>> >>> +       select USB_OTG_UTILS
>> >>> +       help
>> >>> +         Enable this to support Samsung USB phy controller for samsung
>> >>> +         SoCs.
>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> >>> index eca095b..6bb66f0 100644
>> >>> --- a/drivers/usb/phy/Makefile
>> >>> +++ b/drivers/usb/phy/Makefile
>> >>> @@ -5,3 +5,4 @@
>> >>>
>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>> >>>
>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>> >>>
>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>> >>> index 0000000..33119eb
>> >>> --- /dev/null
>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>> >>> @@ -0,0 +1,354 @@
>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>> >>> + *
>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> >>> + *              http://www.samsung.com
>> >>> + *
>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> >>> + *
>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>> >>> controller + *
>> >>> + * This program is free software; you can redistribute it and/or
>> >>> modify + * it under the terms of the GNU General Public License
>> >>> version 2 as + * published by the Free Software Foundation.
>> >>> + *
>> >>> + * This program is distributed in the hope that it will be useful,
>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> >>> + * GNU General Public License for more details.
>> >>> + *
>> >>> + * You should have received a copy of the GNU General Public License
>> >>> + * along with this program; if not, write to the Free Software
>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> >>> +*/
>> >>> +
>> >>> +#include <linux/module.h>
>> >>> +#include <linux/platform_device.h>
>> >>> +#include <linux/clk.h>
>> >>> +#include <linux/delay.h>
>> >>> +#include <linux/err.h>
>> >>> +#include <linux/io.h>
>> >>> +#include <linux/of.h>
>> >>> +#include <linux/usb/otg.h>
>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>> >>> +
>> >>> +#include "sec_usbphy.h"
>> >>> +
>> >>> +enum sec_cpu_type {
>> >>> +     TYPE_S3C64XX,
>> >>> +     TYPE_EXYNOS4210,
>> >>> +};
>> >>> +
>> >>> +/*
>> >>> + * struct sec_usbphy - transceiver driver state
>> >>> + * @phy: transceiver structure
>> >>> + * @plat: platform data
>> >>> + * @dev: The parent device supplied to the probe function
>> >>> + * @clk: usb phy clock
>> >>> + * @regs: usb phy register memory base
>> >>> + * @cpu_type: machine identifier
>> >>> + */
>> >>> +struct sec_usbphy {
>> >>> +     struct usb_phy  phy;
>> >>> +     struct s3c_usbphy_plat *plat;
>> >>> +     struct device   *dev;
>> >>> +     struct clk      *clk;
>> >>> +     void __iomem    *regs;
>> >>> +     int             cpu_type;
>> >>> +};
>> >>> +
>> >>> +#define phy_to_sec(x)                container_of((x), struct
>> >>> sec_usbphy, phy)
>> >>> +
>> >>> +/*
>> >>> + * Enables or disables the phy clock
>> >>> + * returns 0 on success else the error
>> >>> + */
>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>> >>> +{
>> >>> +     if (on) {
>> >>> +             if (!sec->clk) {
>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>> >>> +                     if (IS_ERR(sec->clk)) {
>> >>> +                             dev_err(sec->dev, "Failed to get otg
>> >>> clock\n");
>> >>> +                             return PTR_ERR(sec->clk);
>> >>> +                     }
>> >>> +             }
>> >>> +             clk_enable(sec->clk);
>> >>> +     } else {
>> >>> +             clk_disable(sec->clk);
>> >>> +             clk_put(sec->clk);
>> >>> +     }
>> >>> +
>> >>> +     return 0;
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * Returns reference clock frequency
>> >>> + */
>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     struct clk *ref_clk;
>> >>> +     int refclk_freq = 0;
>> >>> +
>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>> >>> +     if (IS_ERR(ref_clk)) {
>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>> >>> +             return PTR_ERR(ref_clk);
>> >>> +     }
>> >>> +
>> >>> +     switch (clk_get_rate(ref_clk)) {
>> >>> +     case 12 * MHZ:
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> >>> +             break;
>> >>> +     case 24 * MHZ:
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> >>> +             break;
>> >>> +     default:
>> >>> +     case 48 * MHZ:
>> >>> +             /* default reference clock */
>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> >>> +             break;
>> >>> +     }
>> >>> +     clk_put(ref_clk);
>> >>> +
>> >>> +     return refclk_freq;
>> >>> +}
>> >>> +
>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     void __iomem *regs = sec->regs;
>> >>> +     u32 phypwr;
>> >>> +     u32 phyclk;
>> >>> +     u32 rstcon;
>> >>> +
>> >>> +     /* set clock frequency for PLL */
>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>> >>> +
>> >>> +     switch (sec->cpu_type) {
>> >>> +     case TYPE_S3C64XX:
>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>> >>> +             rstcon |= S3C_RSTCON_PHY;
>> >>> +             break;
>> >>> +     case TYPE_EXYNOS4210:
>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>> >>> +             rstcon |= S3C_RSTCON_PHY;
>> >>> +     default:
>> >>> +             break;
>> >>> +     }
>> >>> +
>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>> >>> +     /* set to normal of PHY0 */
>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>> >>> +     /* reset all ports of PHY and Link */
>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>> >>> +     udelay(10);
>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>> >>> +}
>> >>> +
>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>> >>> +{
>> >>> +     void __iomem *regs = sec->regs;
>> >>> +     u32 phypwr;
>> >>> +
>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>> >>> +
>> >>> +     switch (sec->cpu_type) {
>> >>> +     case TYPE_S3C64XX:
>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>> >>> +             break;
>> >>> +     case TYPE_EXYNOS4210:
>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>> >>> +     default:
>> >>> +             break;
>> >>> +     }
>> >>> +
>> >>> +     /* unset to normal of PHY0 */
>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * The function passed to the usb driver for phy initialization
>> >>> + */
>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +     int ret = 0;
>> >>> +
>> >>> +     sec = phy_to_sec(phy);
>> >>> +
>> >>> +     /* Enable the phy clock */
>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>> >>> +     if (ret) {
>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>> >>> +             return ret;
>> >>> +     }
>> >>> +
>> >>> +     /* Disable phy isolation */
>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>> >>> +             sec->plat->pmu_isolation(false);
>> >>> +
>> >>> +     /* Initialize usb phy registers */
>> >>> +     sec_usbphy_enable(sec);
>> >>> +     return ret;
>> >>> +}
>> >>> +
>> >>> +/*
>> >>> + * The function passed to the usb driver for phy shutdown
>> >>> + */
>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +
>> >>> +     sec = phy_to_sec(phy);
>> >>> +
>> >>> +     /* De-initialize usb phy registers */
>> >>> +     sec_usbphy_disable(sec);
>> >>> +
>> >>> +     /* Enable phy isolation */
>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>> >>> +             sec->plat->pmu_isolation(true);
>> >>> +
>> >>> +     /* Disable the phy clock */
>> >>> +     sec_usbphy_clk_control(sec, false);
>> >>> +}
>> >>> +
>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>> >>> +
>> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>> >>> *pdev)
>> >>> +{
>> >>> +#ifdef CONFIG_OF
>> >>> +     int data;
>> >>> +     if (pdev->dev.of_node) {
>> >>> +             const struct of_device_id *match;
>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>> >>> pdev->dev.of_node);
>> >>> +             data = (int) match->data;
>> >>> +             return data;
>> >>> +     }
>> >>> +#endif
>> >>> +     return platform_get_device_id(pdev)->driver_data;
>> >>> +}
>> >>> +
>> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>> >>> +{
>> >>> +     struct sec_usbphy *sec;
>> >>> +     struct s3c_usbphy_plat *pdata;
>> >>> +     struct device *dev = &pdev->dev;
>> >>> +     struct resource *phy_mem;
>> >>> +     void __iomem    *phy_base;
>> >>> +     int     ret;
>> >>> +
>> >>> +     pdata = pdev->dev.platform_data;
>> >>> +     if (!pdata) {
>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>> >>> __func__);
>> >>> +             return -EINVAL;
>> >>> +     }
>> >>> +
>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> >>> +     if (!phy_mem) {
>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>> >>> +             return -ENODEV;
>> >>> +     }
>> >>> +
>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>> >>> +     if (!phy_base) {
>> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>> >>> +             return -ENXIO;
>> >>> +     }
>> >>> +
>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>> >>> +     if (!sec)
>> >>> +             return -ENOMEM;
>> >>> +
>> >>> +     sec->dev                = &pdev->dev;
>> >>> +     sec->plat               = pdata;
>> >>> +     sec->regs               = phy_base;
>> >>> +     sec->phy.dev            = sec->dev;
>> >>> +     sec->phy.label          = "sec-usbphy";
>> >>> +     sec->phy.init           = sec_usbphy_init;
>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>> >>> +
>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>> >>> +     if (ret)
>> >>> +             goto err;
>> >>> +
>> >>> +     platform_set_drvdata(pdev, sec);
>> >>> +
>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>> >>> +err:
>> >>> +     return ret;
>> >>> +}
>> >>> +
>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>> >>> +{
>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>> >>> +
>> >>> +     usb_remove_phy(&sec->phy);
>> >>> +
>> >>> +     if (sec->clk) {
>> >>> +             clk_put(sec->clk);
>> >>> +             sec->clk = NULL;
>> >>> +     }
>> >>> +
>> >>> +     return 0;
>> >>> +}
>> >>> +
>> >>> +#ifdef CONFIG_OF
>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>> >>> +     {
>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>> >>> +             .data = (void *)TYPE_S3C64XX,
>> >>> +     }, {
>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>> >>> +     },
>> >>> +     {},
>> >>> +};
>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>> >>> +#else
>> >>> +#define sec_usbphy_dt_match NULL
>> >>> +#endif
>> >>> +
>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>> >>> +     {
>> >>> +             .name           = "s3c64xx-usbphy",
>> >>> +             .driver_data    = TYPE_S3C64XX,
>> >>> +     }, {
>> >>> +             .name           = "exynos4210-usbphy",
>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>> >>> +     },
>> >>> +     {},
>> >>> +};
>> >>> +
>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>> >>> +
>> >>> +static struct platform_driver sec_usbphy_driver = {
>> >>> +     .probe          = sec_usbphy_probe,
>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>> >>> +     .id_table       = sec_usbphy_driver_ids,
>> >>> +     .driver         = {
>> >>> +             .name   = "sec-usbphy",
>> >>> +             .owner  = THIS_MODULE,
>> >>> +             .of_match_table = sec_usbphy_dt_match,
>> >>> +     },
>> >>> +};
>> >>> +
>> >>> +static int __init sec_usbphy_driver_init(void)
>> >>> +{
>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>> >>> +}
>> >>> +subsys_initcall(sec_usbphy_driver_init);
>> >>> +
>> >>> +static void __exit sec_usbphy_driver_exit(void)
>> >>> +{
>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>> >>> +}
>> >>> +module_exit(sec_usbphy_driver_exit);
>> >>> +
>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>> >>> +MODULE_LICENSE("GPL");
>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>> >>> index 0000000..06e81d4
>> >>> --- /dev/null
>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>> >>> @@ -0,0 +1,48 @@
>> >>> +/*
>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> >>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>> >>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> >>> + *
>> >>> + * This program is free software; you can redistribute  it and/or
>> >>> modify
>> >>> it + * under  the terms of  the GNU General  Public License as
>> >>> published by the + * Free Software Foundation;  either version 2 of
>> >>> the  License, or
>> >>> (at your + * option) any later version.
>> >>> + */
>> >>> +
>> >>> +#ifndef __SEC_USBPHY_H
>> >>> +#define __SEC_USBPHY_H
>> >>> +
>> >>> +#define S3C_PHYPWR                           (0x00)
>> >>> +
>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>> >>> +/* For Exynos4 */
>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>> >>> +
>> >>> +#define S3C_PHYCLK                           (0x04)
>> >>> +
>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>> >>> +
>> >>> +#define S3C_RSTCON                           (0x08)
>> >>> +
>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>> >>> +
>> >>> +#ifndef MHZ
>> >>> +#define MHZ (1000*1000)
>> >>> +#endif
>> >>> +
>> >>> +#endif /* __SEC_USBPHY_H */
>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>> >>>
>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>> >>>
>> >>>  };
>> >>>
>> >>> +struct s3c_usbphy_plat {
>> >>> +     void (*pmu_isolation)(int on);
>> >>> +};
>> >>> +
>> >>>
>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>> >>>
>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>> >>>
>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>> >>
>> >> --
>> >> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
>> >> the body of a message to majordomo at vger.kernel.org
>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe
>> > linux-samsung-soc" in
>> > the body of a message to majordomo at vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From lee.jones at linaro.org  Mon Aug  6 05:51:45 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 10:51:45 +0100
Subject: [PATCH] ARM: ux500: resurrect I2C platform data
In-Reply-To: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
References: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20120806095144.GA16996@gmail.com>

On Mon, Aug 06, 2012 at 10:52:26AM +0200, Linus Walleij wrote:
> Commit:
> 98582d9562b4bea6b0eb6e2bfafcd3fab3b60ccb
> "ARM: ux500: Remove unused i2c platform_data initialisation code"
> 
> Deleted platform data intialization code that was used,
> not unused as indicated in the commit. The boot log (without
> devicetree) now looks like this:

The aforementioned commit was part of a patch-set. One of its affiliates
moved this code into the Nomadik I2C driver; however, it was contested
because Device Tree support was also added and the maintainer thought 
the properties introduced could be consolidated with other I2C driver's
DT properties. I don't think anyone has taken up the consolidation work
and for that reason it hasn't gone in.

I think moving this stuff into the driver is the right thing to do.
Instead, I'll split out the configuration and DT enablement from the
patch and resubmit.

Sound good to you? 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From hdk at igel.co.jp  Mon Aug  6 05:55:20 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Mon,  6 Aug 2012 18:55:20 +0900
Subject: [PATCH v3 0/4] Use dma_mmap_coherent to support IOMMU mapper
Message-ID: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>

There is a dma_mmap_coherent() API in some architectures.  This API
provides a mmap function for memory allocated by dma_alloc_coherent().
Some drivers mmap a dma_addr_t returned by dma_alloc_coherent() as a
physical address.  But such drivers do not work correctly when IOMMU
mapper is used.

v3:
- Remove an unnecessary line which sets page protection bits.
v2:
- Rebase on fbdev-next branch of
  git://github.com/schandinat/linux-2.6.git.
- Initialize .fb_mmap in both sh_mobile_lcdc_overlay_ops and
  sh_mobile_lcdc_ops.
- Add Laurent's clean up patch.

Hideki EIRAKU (3):
  ARM: dma-mapping: define ARCH_HAS_DMA_MMAP_COHERENT
  media: videobuf2-dma-contig: use dma_mmap_coherent if available
  fbdev: sh_mobile_lcdc: use dma_mmap_coherent if available

Laurent Pinchart (1):
  ALSA: pcm - Don't define ARCH_HAS_DMA_MMAP_COHERENT privately for ARM

 arch/arm/include/asm/dma-mapping.h         |    1 +
 drivers/media/video/videobuf2-dma-contig.c |   17 +++++++++++++++++
 drivers/video/sh_mobile_lcdcfb.c           |   28 ++++++++++++++++++++++++++++
 sound/core/pcm_native.c                    |    7 -------
 4 files changed, 46 insertions(+), 7 deletions(-)



From hdk at igel.co.jp  Mon Aug  6 05:55:21 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Mon,  6 Aug 2012 18:55:21 +0900
Subject: [PATCH v3 1/4] ARM: dma-mapping: define ARCH_HAS_DMA_MMAP_COHERENT
In-Reply-To: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1344246924-32620-2-git-send-email-hdk@igel.co.jp>

ARCH_HAS_DMA_MMAP_COHERENT indicates that there is dma_mmap_coherent() API
in this architecture.  The name is already defined in PowerPC.

Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
---
 arch/arm/include/asm/dma-mapping.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index bbef15d..f41cd30 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -187,6 +187,7 @@ extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 			struct dma_attrs *attrs);
 
 #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
+#define ARCH_HAS_DMA_MMAP_COHERENT
 
 static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
 				  void *cpu_addr, dma_addr_t dma_addr,
-- 
1.7.0.4



From hdk at igel.co.jp  Mon Aug  6 05:55:22 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Mon,  6 Aug 2012 18:55:22 +0900
Subject: [PATCH v3 2/4] ALSA: pcm - Don't define ARCH_HAS_DMA_MMAP_COHERENT
 privately for ARM
In-Reply-To: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1344246924-32620-3-git-send-email-hdk@igel.co.jp>

From: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

The ARM architecture now defines ARCH_HAS_DMA_MMAP_COHERENT, there's no
need to define it privately anymore.

Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
---
 sound/core/pcm_native.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 53b5ada..84ead60 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -3156,13 +3156,6 @@ static const struct vm_operations_struct snd_pcm_vm_ops_data_fault = {
 	.fault =	snd_pcm_mmap_data_fault,
 };
 
-#ifndef ARCH_HAS_DMA_MMAP_COHERENT
-/* This should be defined / handled globally! */
-#ifdef CONFIG_ARM
-#define ARCH_HAS_DMA_MMAP_COHERENT
-#endif
-#endif
-
 /*
  * mmap the DMA buffer on RAM
  */
-- 
1.7.0.4



From hdk at igel.co.jp  Mon Aug  6 05:55:23 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Mon,  6 Aug 2012 18:55:23 +0900
Subject: [PATCH v3 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent if
 available
In-Reply-To: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1344246924-32620-4-git-send-email-hdk@igel.co.jp>

Previously the vb2_dma_contig_mmap() function was using a dma_addr_t as a
physical address.  The two addressses are not necessarily the same.
For example, when using the IOMMU funtion on certain platforms, dma_addr_t
addresses are not directly mappable physical address.
dma_mmap_coherent() maps the address correctly.
It is available on ARM platforms.

Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
---
 drivers/media/video/videobuf2-dma-contig.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/media/video/videobuf2-dma-contig.c b/drivers/media/video/videobuf2-dma-contig.c
index 4b71326..7eee9c5 100644
--- a/drivers/media/video/videobuf2-dma-contig.c
+++ b/drivers/media/video/videobuf2-dma-contig.c
@@ -101,14 +101,31 @@ static unsigned int vb2_dma_contig_num_users(void *buf_priv)
 static int vb2_dma_contig_mmap(void *buf_priv, struct vm_area_struct *vma)
 {
 	struct vb2_dc_buf *buf = buf_priv;
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+	int ret;
+#endif
 
 	if (!buf) {
 		printk(KERN_ERR "No buffer to map\n");
 		return -EINVAL;
 	}
 
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+	ret = dma_mmap_coherent(buf->conf->dev, vma, buf->vaddr, buf->dma_addr,
+				buf->size);
+	if (ret) {
+		pr_err("Remapping memory failed, error: %d\n", ret);
+		return ret;
+	}
+	vma->vm_flags |= VM_DONTEXPAND | VM_RESERVED;
+	vma->vm_private_data = &buf->handler;
+	vma->vm_ops = &vb2_common_vm_ops;
+	vma->vm_ops->open(vma);
+	return 0;
+#else
 	return vb2_mmap_pfn_range(vma, buf->dma_addr, buf->size,
 				  &vb2_common_vm_ops, &buf->handler);
+#endif
 }
 
 static void *vb2_dma_contig_get_userptr(void *alloc_ctx, unsigned long vaddr,
-- 
1.7.0.4



From hdk at igel.co.jp  Mon Aug  6 05:55:24 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Mon,  6 Aug 2012 18:55:24 +0900
Subject: [PATCH v3 4/4] fbdev: sh_mobile_lcdc: use dma_mmap_coherent if
 available
In-Reply-To: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1344246924-32620-5-git-send-email-hdk@igel.co.jp>

fb_mmap() implemented in fbmem.c uses smem_start as the physical
address of the frame buffer.  In the sh_mobile_lcdc driver, the
smem_start is a dma_addr_t that is not a physical address when IOMMU is
enabled.  dma_mmap_coherent() maps the address correctly.  It is
available on ARM platforms.

Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
---
 drivers/video/sh_mobile_lcdcfb.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 8cb653b..c8cba7a 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -1614,6 +1614,17 @@ static int sh_mobile_lcdc_overlay_blank(int blank, struct fb_info *info)
 	return 1;
 }
 
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+static int
+sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct sh_mobile_lcdc_overlay *ovl = info->par;
+
+	return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
+				 ovl->dma_handle, ovl->fb_size);
+}
+#endif
+
 static struct fb_ops sh_mobile_lcdc_overlay_ops = {
 	.owner          = THIS_MODULE,
 	.fb_read        = fb_sys_read,
@@ -1626,6 +1637,9 @@ static struct fb_ops sh_mobile_lcdc_overlay_ops = {
 	.fb_ioctl       = sh_mobile_lcdc_overlay_ioctl,
 	.fb_check_var	= sh_mobile_lcdc_overlay_check_var,
 	.fb_set_par	= sh_mobile_lcdc_overlay_set_par,
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+	.fb_mmap	= sh_mobile_lcdc_overlay_mmap,
+#endif
 };
 
 static void
@@ -2093,6 +2107,17 @@ static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
 	return 0;
 }
 
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+static int
+sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
+{
+	struct sh_mobile_lcdc_chan *ch = info->par;
+
+	return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
+				 ch->dma_handle, ch->fb_size);
+}
+#endif
+
 static struct fb_ops sh_mobile_lcdc_ops = {
 	.owner          = THIS_MODULE,
 	.fb_setcolreg	= sh_mobile_lcdc_setcolreg,
@@ -2108,6 +2133,9 @@ static struct fb_ops sh_mobile_lcdc_ops = {
 	.fb_release	= sh_mobile_lcdc_release,
 	.fb_check_var	= sh_mobile_lcdc_check_var,
 	.fb_set_par	= sh_mobile_lcdc_set_par,
+#ifdef ARCH_HAS_DMA_MMAP_COHERENT
+	.fb_mmap	= sh_mobile_lcdc_mmap,
+#endif
 };
 
 static void
-- 
1.7.0.4



From grinberg at compulab.co.il  Mon Aug  6 06:08:25 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Mon, 06 Aug 2012 13:08:25 +0300
Subject: [PATCH 1/2] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <501E5F5D.5070901@gmail.com>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <501E2F6C.4050507@compulab.co.il> <501E5F5D.5070901@gmail.com>
Message-ID: <501F9799.5020400@compulab.co.il>

On 08/05/12 14:56, Daniel Mack wrote:
> On 05.08.2012 10:31, Igor Grinberg wrote:
>> Hi Daniel,
>>
>> On 07/25/12 18:35, Daniel Mack wrote:
>>> Simplify the code in gpio-pxa.c and make them based on irq_base.
>>> When not probed from devicetree, initialize irq_base from
>>> PXA_GPIO_TO_IRQ() or MMP_GPIO_TO_IRQ(), respectively, so the non-DT case
>>> still works.
>>>
>>> Only tested on PXA3xx.
>>>
>>> Signed-off-by: Daniel Mack <zonque at gmail.com>
>>> ---
>>>  drivers/gpio/gpio-pxa.c |   70 +++++++++++------------------------------------
>>>  1 file changed, 16 insertions(+), 54 deletions(-)
>>>
>>> diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
>>> index 58a6a63..6d0cb9d 100644
>>> --- a/drivers/gpio/gpio-pxa.c
>>> +++ b/drivers/gpio/gpio-pxa.c
>>
>> [...]
>>
>>> @@ -564,10 +516,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
>>>  	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
>>>  
>>>  	ret = pxa_gpio_probe_dt(pdev);
>>> -	if (ret < 0)
>>> +	if (ret < 0) {
>>>  		pxa_last_gpio = pxa_gpio_nums();
>>> -	else
>>> +#ifdef CONFIG_ARCH_PXA
>>> +		if (gpio_is_pxa_type(gpio_type))
>>> +			irq_base = PXA_GPIO_TO_IRQ(0);
>>> +#endif
>>> +#ifdef CONFIG_ARCH_MMP
>>> +		if (gpio_is_mmp_type(gpio_type))
>>> +			irq_base = MMP_GPIO_TO_IRQ(0);
>>> +#endif
>>
>> The ifdes above do not look essential.
> 
> But they are. In case of !CONFIG_ARCH_MMP, MMP_GPIO_TO_IRQ is undefined.
> Same problem for !CONFIG_ARC_PXA.

I see. Ok then. I'm not a huge fan of having the #ifdes inside
the code (functions) and thinking of moving those outside of the function,
I get pretty much the same solution it was before your patch.

I really think that PXA|MMP_GPIO_TO_IRQ should be moved to some common
location (say arch/arm/plat-pxa/) so both are available regardless
of CONFIG_ARCH_MMP|PXA. That will simplify the code even more.
But probably it is too much to ask for that simple patch...
So, I'm fine with the patch.

Thanks

> 
>> Can't we drop them and just have else if ... else if?
> 
> We can't do that either, as we might have a hybrid kernel that works on
> both PXA and MMP platforms, and then the condition is a runtime thing.

Well, that is exactly what I mean...
I mean, the if ... else ... if ... else without the #ifdefs...
But again, it requires some more changes.

-- 
Regards,
Igor.


From jean.pihet at newoldbits.com  Mon Aug  6 06:14:08 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Mon, 6 Aug 2012 12:14:08 +0200
Subject: [PATCHv4 4/8] ARM: OMAP3: add manual control for mpu / core pwrdm
 usecounting
In-Reply-To: <1343637607.9847.13.camel@sokoban>
References: <1342189185-5306-1-git-send-email-t-kristo@ti.com>
 <1342189185-5306-5-git-send-email-t-kristo@ti.com>
 <878ve5j8se.fsf@ti.com> <1343637607.9847.13.camel@sokoban>
Message-ID: <CAORVsuUDo7VB3FnbQWJo=zowrviNDNbPM4DtqQMNrYAmOOat4w@mail.gmail.com>

Hi Tero,

On Mon, Jul 30, 2012 at 10:40 AM, Tero Kristo <t-kristo at ti.com> wrote:
> On Fri, 2012-07-27 at 12:36 -0700, Kevin Hilman wrote:
>> Tero Kristo <t-kristo at ti.com> writes:
>>
>> > mpu / core powerdomain usecounts are now statically increased
>> > by 1 during MPU activity. This allows the domains to reflect
>> > actual usage, and will allow the usecount to reach 0 just before
>> > all CPUs are ready to idle. Proper powerdomain usecounts are
>> > propageted to voltagedomain level also, and will allow vc
>> > callbacks to be triggered at right point of time.
>> >
>> > Signed-off-by: Tero Kristo <t-kristo at ti.com>
>> > Cc: Paul Walmsley <paul at pwsan.com>
>> > Cc: Kevin Hilman <khilman at ti.com>
>>
>> IMO, the idea is fine, but I'm not crazy about the implementation in
>> powerdomain.c, which is meant for pwrdm generic code.   In particular,
>> I'm not crazy about the pwrdm lookups in powerdomain.c.
>>
>> Since pm<soc>.c already has references to mpu_pwrdm and core_pwrdm, why
>> not just add the pwrdm_clkdm_enable/disable calls directly in pm<soc>.c
>
> I think this was how the patch was in some earlier rev but I thought I'd
> try to be more clever with this. :) I can revert the implementation back
> to this.
Furthermore after the changes in pre/post transitions [1], some more
checks will be needed to identify the transitions on the mpu and core
power domains.

[1] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=e055548953355b6e69c56f9e54388845b29b4e97

Regards,
Jean

>
>> Also, the changelog should be a bit more specific about why CORE
>> powerdomain is also handled here when most of the code only talks about
>> the CPU.
>
> Yea, I'll add some beef to this also.
>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From lee.jones at linaro.org  Mon Aug  6 06:21:52 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 11:21:52 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C driver
In-Reply-To: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
References: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20120806102151.GB16996@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Mon, 6 Aug 2012 11:04:14 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index a92440d..86aa73d 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -333,10 +333,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -899,15 +895,31 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* std. mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct resource *res;
-	struct nmk_i2c_controller *pdata =
-			pdev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = pdev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&pdev->dev, "cannot allocate memory\n");
-- 
1.7.9.5


From arnd at arndb.de  Mon Aug  6 04:44:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 08:44:28 +0000
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <201208060844.29333.arnd@arndb.de>

On Saturday 28 July 2012, Haojian Zhuang wrote:
> +Required subnode-properties:
> +- marvell,pins : An array of strings. Each string contains the name of a pin
> +                 or group.
> +- marvell,function     : A string containing the name of the function to mux to the
> +                 pin or group.
> +- marvell,drive-strength : An integer value that means the drive strength of a
> +                        pin.
> +- marvell,pull-up      : The property means a pin is pull up for input.
> +- marvell,pull-down : The property means a pin is pull down for input.
> +- marvell,lowpower-pull-up : The property means a pin is pull up for input in
> +                         sleep state.
> +- marvell,lowpower-pull-down : The property means a pin is pull down for input
> +                           in sleep state.
> +- marvell,lowpower-drive-high : The property means a pin is driving high for
> +                            output in sleep state.
> +- marvell,lowpower-drive-low : The property means a pin is driving low for
> +                           output in sleep state.
> +- marvell,lowpower-float : The property means a pin is float in sleep state.
> +- marvell,lowpower-zero : The property means a pin is not configured in sleep
> +                       state.

These (or most of them) look like they are not very Marvell specific. Should
we try to standardize the way they are set across different bindings?

On a side-node, you probably don't want to make all of the above properties
"required" because some of them are mutually exclusive.

	Arnd



From arnd at arndb.de  Mon Aug  6 06:26:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 10:26:08 +0000
Subject: [PATCH 1/2] GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and
 pxa_irq_to_chip()
In-Reply-To: <501F9799.5020400@compulab.co.il>
References: <1343230539-7196-1-git-send-email-zonque@gmail.com>
 <501E5F5D.5070901@gmail.com> <501F9799.5020400@compulab.co.il>
Message-ID: <201208061026.08928.arnd@arndb.de>

On Monday 06 August 2012, Igor Grinberg wrote:
> I see. Ok then. I'm not a huge fan of having the #ifdes inside
> the code (functions) and thinking of moving those outside of the function,
> I get pretty much the same solution it was before your patch.
> 
> I really think that PXA|MMP_GPIO_TO_IRQ should be moved to some common
> location (say arch/arm/plat-pxa/) so both are available regardless
> of CONFIG_ARCH_MMP|PXA. That will simplify the code even more.
> But probably it is too much to ask for that simple patch...
> So, I'm fine with the patch.

Right. I would also not try to spend too much work on making pxa and
mmp coexist better when the plan is to merge them eventually. At that
point, a couple of these hacks can just be removed.

	Arnd


From t.stanislaws at samsung.com  Mon Aug  6 06:29:34 2012
From: t.stanislaws at samsung.com (Tomasz Stanislawski)
Date: Mon, 06 Aug 2012 12:29:34 +0200
Subject: [PATCH 2/2] dma-buf: add helpers for attacher dma-parms
In-Reply-To: <1342715014-5316-3-git-send-email-rob.clark@linaro.org>
References: <1342715014-5316-1-git-send-email-rob.clark@linaro.org>
 <1342715014-5316-3-git-send-email-rob.clark@linaro.org>
Message-ID: <501F9C8E.4080002@samsung.com>

Hi Rob,

On 07/19/2012 06:23 PM, Rob Clark wrote:
> From: Rob Clark <rob at ti.com>
> 
> Add some helpers to iterate through all attachers and get the most
> restrictive segment size/count/boundary.
> 
> Signed-off-by: Rob Clark <rob at ti.com>
> ---
>  drivers/base/dma-buf.c  |   63 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/dma-buf.h |   19 ++++++++++++++
>  2 files changed, 82 insertions(+)
> 
> diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c
> index 24e88fe..757ee20 100644
> --- a/drivers/base/dma-buf.c
> +++ b/drivers/base/dma-buf.c
> @@ -192,6 +192,69 @@ void dma_buf_put(struct dma_buf *dmabuf)
>  EXPORT_SYMBOL_GPL(dma_buf_put);
>  
>  /**
> + * dma_buf_max_seg_size - helper for exporters to get the minimum of
> + * all attached device's max segment size
> + */
> +unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf)
> +{
> +	struct dma_buf_attachment *attach;
> +	unsigned int max = (unsigned int)-1;
> +
> +	if (WARN_ON(!dmabuf))
> +		return 0;

Maybe you should change return type to 'int' and return -EINVAL here?

> +
> +	mutex_lock(&dmabuf->lock);
> +	list_for_each_entry(attach, &dmabuf->attachments, node)
> +		max = min(max, dma_get_max_seg_size(attach->dev));
> +	mutex_unlock(&dmabuf->lock);
> +
> +	return max;
> +}
> +EXPORT_SYMBOL_GPL(dma_buf_max_seg_size);
> +
> +/**
> + * dma_buf_max_seg_count - helper for exporters to get the minimum of
> + * all attached device's max segment count
> + */
> +unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf)
> +{
> +	struct dma_buf_attachment *attach;
> +	unsigned int max = (unsigned int)-1;
> +
> +	if (WARN_ON(!dmabuf))
> +		return 0;

maybe return -EINVAL here?

> +
> +	mutex_lock(&dmabuf->lock);
> +	list_for_each_entry(attach, &dmabuf->attachments, node)
> +		max = min(max, dma_get_max_seg_count(attach->dev));

I think that there is a bug here.
Assume that there are two deices on the list, one using unlimited number of
segments (value 0), the second one needs a contiguous buffer (value 1).
The result of the function is 0 = min(0, 2).

The return value 0 indicates that the unlimited number of sg segments is
accepted what is *wrong* because the correct value should be 1.

I recommend to change the semantics for unlimited number of segments
from 'value 0' to:

#define DMA_SEGMENTS_COUNT_UNLIMITED ((unsigned long)INT_MAX)

Using INT_MAX will allow using safe conversions between signed and
unsigned integers.

> +	mutex_unlock(&dmabuf->lock);
> +
> +	return max;
> +}
> +EXPORT_SYMBOL_GPL(dma_buf_max_seg_count);
> +
> +/**
> + * dma_buf_get_seg_boundary - helper for exporters to get the most
> + * restrictive segment alignment of all the attached devices
> + */
> +unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf)
> +{
> +	struct dma_buf_attachment *attach;
> +	unsigned int mask = (unsigned int)-1;
> +
> +	if (WARN_ON(!dmabuf))
> +		return 0;
> +
> +	mutex_lock(&dmabuf->lock);
> +	list_for_each_entry(attach, &dmabuf->attachments, node)
> +		mask &= dma_get_seg_boundary(attach->dev);
> +	mutex_unlock(&dmabuf->lock);
> +
> +	return mask;
> +}
> +EXPORT_SYMBOL_GPL(dma_buf_get_seg_boundary);
> +
> +/**
>   * dma_buf_attach - Add the device to dma_buf's attachments list; optionally,
>   * calls attach() of dma_buf_ops to allow device-specific attach functionality
>   * @dmabuf:	[in]	buffer to attach device to.
> diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
> index eb48f38..9533b9b 100644
> --- a/include/linux/dma-buf.h
> +++ b/include/linux/dma-buf.h
> @@ -167,6 +167,10 @@ int dma_buf_fd(struct dma_buf *dmabuf, int flags);
>  struct dma_buf *dma_buf_get(int fd);
>  void dma_buf_put(struct dma_buf *dmabuf);
>  
> +unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf);
> +unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf);
> +unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf);

Instead of adding an army of new handlers you could provide a single helper:

int dma_buf_get_parameters(struct dma_buf *dmabuf,
	struct device_dma_parameters *params);

This function will fill *params with lowest common DMA requirements for
all devices on attachment list. Return value can be used to diagnose
errors like incorrectly initialized dma_buf pointer
(like no attachments on an attachment list).

Moreover, there will be no need to add a new handler every time
device_dma_parameters is extended.

Regards,
Tomasz Stanislawski

> +
>  struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *,
>  					enum dma_data_direction);
>  void dma_buf_unmap_attachment(struct dma_buf_attachment *, struct sg_table *,
> @@ -220,6 +224,21 @@ static inline void dma_buf_put(struct dma_buf *dmabuf)
>  	return;
>  }
>  
> +static inline unsigned int dma_buf_max_seg_size(struct dma_buf *dmabuf)
> +{
> +	return 0;
> +}
> +
> +static inline unsigned int dma_buf_max_seg_count(struct dma_buf *dmabuf)
> +{
> +	return 0;
> +}
> +
> +static inline unsigned int dma_buf_get_seg_boundary(struct dma_buf *dmabuf)
> +{
> +	return 0;
> +}
> +
>  static inline struct sg_table *dma_buf_map_attachment(
>  	struct dma_buf_attachment *attach, enum dma_data_direction write)
>  {
> 



From stefano.stabellini at eu.citrix.com  Mon Aug  6 06:31:04 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 11:31:04 +0100
Subject: [PATCH 15/24] xen/arm: receive Xen events on ARM
In-Reply-To: <20120801144418.GM7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-15-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801144418.GM7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208061127440.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:57PM +0100, Stefano Stabellini wrote:
> > Compile events.c on ARM.
> > Parse, map and enable the IRQ to get event notifications from the device
> > tree (node "/xen").
> > 
> > On ARM Linux irqs are not enabled by default:
> > 
> > - call enable_percpu_irq for xen_events_irq (drivers are supposed
> > to call enable_irq after request_irq);
> > 
> > - reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
> > default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
> > irq_startup, that is responsible for calling irq_unmask at startup time.
> > As a result event channels remain masked.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/enlighten.c |   33 +++++++++++++++++++++++++++++++++
> >  arch/x86/xen/enlighten.c |    1 +
> >  arch/x86/xen/irq.c       |    1 +
> >  arch/x86/xen/xen-ops.h   |    1 -
> >  drivers/xen/events.c     |   18 +++++++++++++++---
> >  include/xen/events.h     |    2 ++
> >  6 files changed, 52 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index 854af1e..60d6d36 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -7,8 +7,11 @@
> >  #include <xen/grant_table.h>
> >  #include <xen/hvm.h>
> >  #include <xen/xenbus.h>
> > +#include <xen/events.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irqreturn.h>
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/of_irq.h>
> > @@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
> >  int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
> >  EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
> >  
> > +static __read_mostly int xen_events_irq = -1;
> > +
> >  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
> >  			       unsigned long addr,
> >  			       unsigned long mfn, int nr,
> > @@ -65,6 +70,9 @@ int __init xen_guest_init(void)
> >  	if (of_address_to_resource(node, 0, &res))
> >  		return -EINVAL;
> >  	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
> > +	xen_events_irq = irq_of_parse_and_map(node, 0);
> > +	pr_info("Xen support found, events_irq=%d gnttab_frame_pfn=%lx\n",
> > +			xen_events_irq, xen_hvm_resume_frames);
> >  	xen_domain_type = XEN_HVM_DOMAIN;
> >  
> >  	xen_setup_features();
> > @@ -114,3 +122,28 @@ int __init xen_guest_init(void)
> >  }
> >  EXPORT_SYMBOL_GPL(xen_guest_init);
> >  core_initcall(xen_guest_init);
> > +
> > +static irqreturn_t xen_arm_callback(int irq, void *arg)
> > +{
> > +	xen_hvm_evtchn_do_upcall();
> > +	return 0;
> 
> Um, IRQ_HANDLED?

Yep


> > +}
> > +
> > +static int __init xen_init_events(void)
> > +{
> > +	if (!xen_domain() || xen_events_irq < 0)
> > +		return -ENODEV;
> > +
> > +	xen_init_IRQ();
> > +
> > +	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
> > +			"events", xen_vcpu)) {
> > +		pr_err("Error requesting IRQ %d\n", xen_events_irq);
> > +		return -EINVAL;
> > +	}
> > +
> > +	enable_percpu_irq(xen_events_irq, 0);
> > +
> > +	return 0;
> > +}
> > +postcore_initcall(xen_init_events);
> > diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
> > index 6131d43..5a30502 100644
> > --- a/arch/x86/xen/enlighten.c
> > +++ b/arch/x86/xen/enlighten.c
> > @@ -33,6 +33,7 @@
> >  #include <linux/memblock.h>
> >  
> >  #include <xen/xen.h>
> > +#include <xen/events.h>
> >  #include <xen/interface/xen.h>
> >  #include <xen/interface/version.h>
> >  #include <xen/interface/physdev.h>
> > diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
> > index 1573376..01a4dc0 100644
> > --- a/arch/x86/xen/irq.c
> > +++ b/arch/x86/xen/irq.c
> > @@ -5,6 +5,7 @@
> >  #include <xen/interface/xen.h>
> >  #include <xen/interface/sched.h>
> >  #include <xen/interface/vcpu.h>
> > +#include <xen/events.h>
> >  
> >  #include <asm/xen/hypercall.h>
> >  #include <asm/xen/hypervisor.h>
> > diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
> > index 202d4c1..2368295 100644
> > --- a/arch/x86/xen/xen-ops.h
> > +++ b/arch/x86/xen/xen-ops.h
> > @@ -35,7 +35,6 @@ void xen_set_pat(u64);
> >  
> >  char * __init xen_memory_setup(void);
> >  void __init xen_arch_setup(void);
> > -void __init xen_init_IRQ(void);
> >  void xen_enable_sysenter(void);
> >  void xen_enable_syscall(void);
> >  void xen_vcpu_restore(void);
> > diff --git a/drivers/xen/events.c b/drivers/xen/events.c
> > index 7da65d3..9b506b2 100644
> > --- a/drivers/xen/events.c
> > +++ b/drivers/xen/events.c
> > @@ -31,14 +31,16 @@
> >  #include <linux/irqnr.h>
> >  #include <linux/pci.h>
> >  
> > +#ifdef CONFIG_X86
> >  #include <asm/desc.h>
> >  #include <asm/ptrace.h>
> >  #include <asm/irq.h>
> >  #include <asm/idle.h>
> >  #include <asm/io_apic.h>
> > -#include <asm/sync_bitops.h>
> >  #include <asm/xen/page.h>
> >  #include <asm/xen/pci.h>
> > +#endif
> > +#include <asm/sync_bitops.h>
> >  #include <asm/xen/hypercall.h>
> >  #include <asm/xen/hypervisor.h>
> >  
> > @@ -50,6 +52,9 @@
> >  #include <xen/interface/event_channel.h>
> >  #include <xen/interface/hvm/hvm_op.h>
> >  #include <xen/interface/hvm/params.h>
> > +#include <xen/interface/physdev.h>
> > +#include <xen/interface/sched.h>
> > +#include <asm/hw_irq.h>
> >  
> >  /*
> >   * This lock protects updates to the following mapping and reference-count
> > @@ -834,6 +839,7 @@ int bind_evtchn_to_irq(unsigned int evtchn)
> >  		struct irq_info *info = info_for_irq(irq);
> >  		WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
> >  	}
> > +	irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
> 
> I feel that this should be its own commit by itself. I am not certain
> of the implication of this on x86 and I think it deserves some explanation.

OK. It shouldn't have any effects on x86, considering that both
IRQ_NOREQUEST and IRQ_NOAUTOEN are not set there.


> >  
> >  out:
> >  	mutex_unlock(&irq_mapping_update_lock);
> > @@ -1377,7 +1383,9 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
> >  {
> >  	struct pt_regs *old_regs = set_irq_regs(regs);
> >  
> > +#ifdef CONFIG_X86
> >  	exit_idle();
> > +#endif
> 
> Doesn't exist? Or is that it does not need it?

It does not exist.



From zonque at gmail.com  Mon Aug  6 06:32:23 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 06 Aug 2012 12:32:23 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <201208060844.29333.arnd@arndb.de>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
Message-ID: <501F9D37.9030809@gmail.com>

On 06.08.2012 10:44, Arnd Bergmann wrote:
> On Saturday 28 July 2012, Haojian Zhuang wrote:
>> +Required subnode-properties:
>> +- marvell,pins : An array of strings. Each string contains the name of a pin
>> +                 or group.
>> +- marvell,function     : A string containing the name of the function to mux to the
>> +                 pin or group.
>> +- marvell,drive-strength : An integer value that means the drive strength of a
>> +                        pin.
>> +- marvell,pull-up      : The property means a pin is pull up for input.
>> +- marvell,pull-down : The property means a pin is pull down for input.
>> +- marvell,lowpower-pull-up : The property means a pin is pull up for input in
>> +                         sleep state.
>> +- marvell,lowpower-pull-down : The property means a pin is pull down for input
>> +                           in sleep state.
>> +- marvell,lowpower-drive-high : The property means a pin is driving high for
>> +                            output in sleep state.
>> +- marvell,lowpower-drive-low : The property means a pin is driving low for
>> +                           output in sleep state.
>> +- marvell,lowpower-float : The property means a pin is float in sleep state.
>> +- marvell,lowpower-zero : The property means a pin is not configured in sleep
>> +                       state.
> 
> These (or most of them) look like they are not very Marvell specific. Should
> we try to standardize the way they are set across different bindings?

Yes please. That way we also have a higher chance that implementations
on other platforms will be similar.


Daniel



From haojian.zhuang at gmail.com  Mon Aug  6 06:33:52 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 6 Aug 2012 18:33:52 +0800
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <201208060844.29333.arnd@arndb.de>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
Message-ID: <CAN1soZwy4DeHbvwKWZMyUqXjS6we0eT=Bbm7dpAuLDQ5JdeYEg@mail.gmail.com>

On Mon, Aug 6, 2012 at 4:44 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Saturday 28 July 2012, Haojian Zhuang wrote:
>> +Required subnode-properties:
>> +- marvell,pins : An array of strings. Each string contains the name of a pin
>> +                 or group.
>> +- marvell,function     : A string containing the name of the function to mux to the
>> +                 pin or group.
>> +- marvell,drive-strength : An integer value that means the drive strength of a
>> +                        pin.
>> +- marvell,pull-up      : The property means a pin is pull up for input.
>> +- marvell,pull-down : The property means a pin is pull down for input.
>> +- marvell,lowpower-pull-up : The property means a pin is pull up for input in
>> +                         sleep state.
>> +- marvell,lowpower-pull-down : The property means a pin is pull down for input
>> +                           in sleep state.
>> +- marvell,lowpower-drive-high : The property means a pin is driving high for
>> +                            output in sleep state.
>> +- marvell,lowpower-drive-low : The property means a pin is driving low for
>> +                           output in sleep state.
>> +- marvell,lowpower-float : The property means a pin is float in sleep state.
>> +- marvell,lowpower-zero : The property means a pin is not configured in sleep
>> +                       state.
>
> These (or most of them) look like they are not very Marvell specific. Should
> we try to standardize the way they are set across different bindings?
>
> On a side-node, you probably don't want to make all of the above properties
> "required" because some of them are mutually exclusive.
>
OK, I'll handle it.


From r.sricharan at ti.com  Mon Aug  6 06:33:50 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Mon, 6 Aug 2012 16:03:50 +0530
Subject: [RFC PATCH] ARM: LPAE: Fix alloc_init_section to flush all the pmd
 entries.
Message-ID: <1344249230-29835-1-git-send-email-r.sricharan@ti.com>

flush_pmd_entry flushes one cache line by MVA. This is
called by alloc_init_section to flush the mapped pmd
entries. But this is called outside the loop and when
LPAE is enabled the number of pmd entries to be
flushed can be across multiple cache lines. So call
this inside the loop so that all the mapped entries are
flushed.

This is going to result in additional cache line
flushes. There might be other better way to handle
this.

Signed-off-by: R Sricharan <r.sricharan at ti.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mm/mmu.c |    4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 0ed8808..02af3fe 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -619,7 +619,6 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 	 * up one logical pointer to an L2 table.
 	 */
 	if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
-		pmd_t *p = pmd;
 
 #ifndef CONFIG_ARM_LPAE
 		if (addr & SECTION_SIZE)
@@ -629,9 +628,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 		do {
 			*pmd = __pmd(phys | type->prot_sect);
 			phys += SECTION_SIZE;
+			flush_pmd_entry(pmd);
 		} while (pmd++, addr += SECTION_SIZE, addr != end);
-
-		flush_pmd_entry(p);
 	} else {
 		/*
 		 * No need to loop; pte's aren't interested in the
-- 
1.7.9.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 06:46:14 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 11:46:14 +0100
Subject: [Xen-devel] [PATCH 01/24] arm: initial Xen support
In-Reply-To: <20120802141341.GE16749@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <50197527.3070007@gmail.com> <1343892951.7571.50.camel@dagon.hellion.org.uk>
 <20120802141341.GE16749@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208061142070.4645@kaball.uk.xensource.com>

On Thu, 2 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Aug 02, 2012 at 08:35:51AM +0100, Ian Campbell wrote:
> > On Wed, 2012-08-01 at 19:27 +0100, Rob Herring wrote:
> > > On 07/26/2012 10:33 AM, Stefano Stabellini wrote:
> > > > - Basic hypervisor.h and interface.h definitions.
> > > > - Skelethon enlighten.c, set xen_start_info to an empty struct.
> > > > - Do not limit xen_initial_domain to PV guests.
> > > > 
> > > > The new code only compiles when CONFIG_XEN is set, that is going to be
> > > > added to arch/arm/Kconfig in a later patch.
> > > > 
> > > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > > ---
> > > >  arch/arm/Makefile                     |    1 +
> > > >  arch/arm/include/asm/hypervisor.h     |    6 +++
> > > >  arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
> > > >  arch/arm/include/asm/xen/interface.h  |   64 +++++++++++++++++++++++++++++++++
> > > 
> > > These headers don't seem particularly ARM specific. Could they be moved
> > > to asm-generic or include/linux?
> > 
> > Or perhaps include/xen.
> > 
> > A bunch of it also looks like x86 specific stuff which has crept in.
> > e.g. PARAVIRT_LAZY_FOO and paravirt_get_lazy_mode() are arch/x86
> > specific and shouldn't be called from common code (and aren't, AFAICT).
> 
> The could be moved out..
> 

they are called from grant-table.c; sigh, I was the one to add them there :-(

interface.h is ARM specific, except for the pvclock structs, that in
fact are marked "XXX".

hypervisor.h is almost empty but I guess I could move out the following two
lines:

extern struct shared_info *HYPERVISOR_shared_info;
extern struct start_info *xen_start_info;

Considering that each arch is free to map them (or not) the way it
wants, I don't think is a good idea.


From lee.jones at linaro.org  Mon Aug  6 06:46:36 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:36 +0100
Subject: [PATCH 0/6] Device Tree IRQ related enablement patches
Message-ID: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>

This patch-set pertains to the addition of a new IRQ domain for
the DB8500-PRCMU and providing it with Interrupt Controller status
in the eyes of Device Tree. We also ensure that the Power-On-Key
driver obtains the correct IRQ when being probed with Device Tree
and otherwise.

 arch/arm/boot/dts/dbx5x0.dtsi      |    5 +++-
 drivers/input/misc/ab8500-ponkey.c |    6 ++--
 drivers/mfd/db8500-prcmu.c         |   54 +++++++++++++++++++++++++++---------
 drivers/mfd/mfd-core.c             |   10 +++++--
 include/linux/mfd/db8500-prcmu.h   |    2 ++
 5 files changed, 59 insertions(+), 18 deletions(-)



From lee.jones at linaro.org  Mon Aug  6 06:46:37 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:37 +0100
Subject: [PATCH 1/6] ARM: ux500: Identify the PRCMU as an interrupt controller
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-2-git-send-email-lee.jones@linaro.org>

We're just about to provide the DB8500-PRCMU with its own IRQ domain,
so that its subordinate drivers can use it as an interrupt controller.
It's obligatory for all IRQ controllers to reference themselves as
such from its own node in Device Tree. This patch does just that.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 241213c..f236bb7 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
 			interrupts = <0 47 0x4>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 			ranges;
 
 			prcmu-timer-4 at 80157450 {
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 06:46:39 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:39 +0100
Subject: [PATCH 3/6] ARM: ux500: Force AB8500 to use the GIC as its interrupt
 controller
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-4-git-send-email-lee.jones@linaro.org>

It's understood that the AB8500 should be subordinate to the DB8500;
however, the AB8500 uses the GIC as it's interrupt controller. If
we do not specify which IRQ controller to use the default is to use
the next encountered IRQ controller as we climb the tree. This would
be the DB8500. This patch ensures the AB8500 makes use of the correct
interrupt controller.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index f236bb7..83229f7 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -313,6 +313,7 @@
 			ab8500 at 5 {
 				compatible = "stericsson,ab8500";
 				reg = <5>; /* mailbox 5 is i2c */
+				interrupt-parent = <&intc>;
 				interrupts = <0 40 0x4>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 06:46:38 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:38 +0100
Subject: [PATCH 2/6] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-3-git-send-email-lee.jones@linaro.org>

The PRCMU has its own USB, Thermal, GPIO, Modem, HSI and RTC drivers,
amongst other things. This patch allows those subordinate devices to
use it as an interrupt controller as and when they are DT enabled.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/db8500-prcmu.c       |   54 +++++++++++++++++++++++++++++---------
 include/linux/mfd/db8500-prcmu.h |    2 ++
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 7040a00..937ce3a 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -270,6 +270,8 @@ static struct {
 	struct prcmu_fw_version version;
 } fw_info;
 
+struct irq_domain *db8500_irq_domain;
+
 /*
  * This vector maps irq numbers to the bits in the bit field used in
  * communication with the PRCMU firmware.
@@ -2583,7 +2585,7 @@ static void prcmu_irq_mask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2597,7 +2599,7 @@ static void prcmu_irq_unmask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2637,9 +2639,43 @@ static char *fw_project_name(u8 project)
 	}
 }
 
+int db8500_irq_get_virq(int irq)
+{
+	return irq_create_mapping(db8500_irq_domain, irq);
+}
+EXPORT_SYMBOL_GPL(db8500_irq_get_virq);
+
+static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
+				irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(virq, &prcmu_irq_chip,
+				handle_simple_irq);
+	set_irq_flags(virq, IRQF_VALID);
+
+	return 0;
+}
+
+static struct irq_domain_ops db8500_irq_ops = {
+        .map    = db8500_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+static int db8500_irq_init(struct device_node *np)
+{
+	db8500_irq_domain = irq_domain_add_legacy(
+		np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE,
+		0, &db8500_irq_ops, NULL);
+
+	if (!db8500_irq_domain) {
+		pr_err("Failed to create irqdomain\n");
+		return -ENOSYS;
+	}
+
+	return 0;
+}
+
 void __init db8500_prcmu_early_init(void)
 {
-	unsigned int i;
 	if (cpu_is_u8500v2()) {
 		void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
 
@@ -2683,16 +2719,6 @@ void __init db8500_prcmu_early_init(void)
 	init_completion(&mb5_transfer.work);
 
 	INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
-
-	/* Initalize irqs. */
-	for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
-		unsigned int irq;
-
-		irq = IRQ_PRCMU_BASE + i;
-		irq_set_chip_and_handler(irq, &prcmu_irq_chip,
-					 handle_simple_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
 }
 
 static void __init init_prcm_registers(void)
@@ -2999,6 +3025,8 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
 		goto no_irq_return;
 	}
 
+	db8500_irq_init(np);
+
 	for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
 		if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
 			db8500_prcmu_devs[i].platform_data = ab8500_platdata;
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index b82f6ee..38494d9 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -571,6 +571,8 @@ u32 db8500_prcmu_read(unsigned int reg);
 void db8500_prcmu_write(unsigned int reg, u32 value);
 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
 
+int db8500_irq_get_virq(int irq);
+
 #else /* !CONFIG_MFD_DB8500_PRCMU */
 
 static inline void db8500_prcmu_early_init(void) {}
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 06:46:42 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:42 +0100
Subject: [PATCH 6/6] Input: ab8500-ponkey: Make the distinction between DT and
 non-DT boots
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-7-git-send-email-lee.jones@linaro.org>

If we're booting with Device Tree enabled, we want the IRQ numbers to
be taken and translated from the Device Tree binary. If not, they
should be taken from the resource allocation defined in the AB8500 MFD
core driver.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/input/misc/ab8500-ponkey.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
index 1a1d974..afcd87f 100644
--- a/drivers/input/misc/ab8500-ponkey.c
+++ b/drivers/input/misc/ab8500-ponkey.c
@@ -47,6 +47,7 @@ static irqreturn_t ab8500_ponkey_handler(int irq, void *data)
 static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 {
 	struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
+	struct device_node *np = pdev->dev.of_node;
 	struct ab8500_ponkey *ponkey;
 	struct input_dev *input;
 	int irq_dbf, irq_dbr;
@@ -73,8 +74,9 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 
 	ponkey->idev = input;
 	ponkey->ab8500 = ab8500;
-	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
-	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
+
+	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
+	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
 
 	input->name = "AB8500 POn(PowerOn) Key";
 	input->dev.parent = &pdev->dev;
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 06:46:40 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:40 +0100
Subject: [PATCH 4/6] mfd: Use interrupt-parent as IRQ controller if specified
 in DT
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-5-git-send-email-lee.jones@linaro.org>

Without this patch the default behaviour is to climb the Device
Tree and use the first encountered interrupt controller. This
does not take into account if a device node has specified to use
a particular IRQ controller using the interrupt-parent property.
This patch ensures that property is adhered to.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/mfd-core.c |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 0c3a01c..f10f27b 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -20,6 +20,7 @@
 #include <linux/module.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 
 int mfd_cell_enable(struct platform_device *pdev)
 {
@@ -78,7 +79,7 @@ static int mfd_add_device(struct device *parent, int id,
 {
 	struct resource *res;
 	struct platform_device *pdev;
-	struct device_node *np = NULL;
+	struct device_node *np, *parent_node = NULL;
 	struct irq_domain *domain = NULL;
 	int ret = -ENOMEM;
 	int r;
@@ -97,7 +98,12 @@ static int mfd_add_device(struct device *parent, int id,
 		for_each_child_of_node(parent->of_node, np) {
 			if (of_device_is_compatible(np, cell->of_compatible)) {
 				pdev->dev.of_node = np;
-				domain = irq_find_host(parent->of_node);
+#ifdef CONFIG_OF
+				parent_node = of_irq_find_parent(np);
+#endif
+				if (!parent_node)
+					parent_node = parent->of_node;
+				domain = irq_find_host(parent_node);
 				break;
 			}
 		}
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 06:46:41 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 11:46:41 +0100
Subject: [PATCH 5/6] ARM: ux500: Match-up compatible stings with associated
 MFD cell
In-Reply-To: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344250002-6011-6-git-send-email-lee.jones@linaro.org>

Until now, we've either taken the IRQs listed in the MFD cell defined
in the AB8500 driver, or the ones in Device Tree when we probed each
AB8500 MFD device independently. However, now we make a logical choice
based on whether we're running Device Tree or not. For this to happen
we need the compatible stings in the AB8500 MFD cell and the DT to
match-up. We do that here.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 83229f7..0282353 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -355,7 +355,7 @@
 				};
 
 				ab8500-ponkey {
-					compatible = "stericsson,ab8500-ponkey";
+					compatible = "stericsson,ab8500-poweron-key";
 					interrupts = <6 0x4
 						      7 0x4>;
 					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
-- 
1.7.9.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 06:55:38 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 11:55:38 +0100
Subject: [Xen-devel] [PATCH 01/24] arm: initial Xen support
In-Reply-To: <20120801104237.GB7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120726163020.GB9222@phenom.dumpdata.com>
 <alpine.DEB.2.02.1207271246080.26163@kaball.uk.xensource.com>
 <20120801104237.GB7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208061146480.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> > > > +struct pvclock_wall_clock {
> > > > +	u32   version;
> > > > +	u32   sec;
> > > > +	u32   nsec;
> > > > +} __attribute__((__packed__));
> > > 
> > > That is weird. It is 4+4+4 = 12 bytes? Don't you want it to be 16 bytes?
> > 
> > I agree that 16 bytes would be a better choice, but it needs to match
> > the struct in Xen that is defined as follow:
> > 
> >     uint32_t wc_version;      /* Version counter: see vcpu_time_info_t. */
> >     uint32_t wc_sec;          /* Secs  00:00:00 UTC, Jan 1, 1970.  */
> >     uint32_t wc_nsec;         /* Nsecs 00:00:00 UTC, Jan 1, 1970.  */
> 
> Would it make sense to add some paddigin then at least? In both
> cases? Or is it too late for this?

I can see why adding some padding would be useful if the structs were
not packed and we wanted to enforce 32/64 bit compatibility on x86.
However on ARM the field alignments on 32 and 64 bits are the same for
integer values so the padding wouldn't make a difference.
In any case both structs are packed, so the alignment is forced to be the
same by the compiler.


From linux at arm.linux.org.uk  Mon Aug  6 07:12:24 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 Aug 2012 12:12:24 +0100
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <1343775898-28345-2-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
Message-ID: <20120806111224.GA18957@n2100.arm.linux.org.uk>

On Tue, Jul 31, 2012 at 07:04:37PM -0400, Cyril Chemparathy wrote:
> +static void __init init_patch_kernel(void)
> +{
> +	const void *start = &__patch_table_begin;
> +	const void *end   = &__patch_table_end;
> +
> +	BUG_ON(patch_kernel(start, end - start));
> +	flush_icache_range(init_mm.start_code, init_mm.end_code);

Err.  You are asking the kernel to flush every single cache line
manually throughout the kernel code.  That's a flush every 32-bytes
over maybe a few megabytes of address space.

This is one of the reasons we do the patching in assembly code before
the caches are enabled - so we don't have to worry about the interaction
with the CPU caches, which for this kind of application would be very
expensive.


From linux at arm.linux.org.uk  Mon Aug  6 07:14:13 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 Aug 2012 12:14:13 +0100
Subject: [PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <1343775898-28345-4-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-4-git-send-email-cyril@ti.com>
Message-ID: <20120806111413.GB18957@n2100.arm.linux.org.uk>

On Tue, Jul 31, 2012 at 07:04:39PM -0400, Cyril Chemparathy wrote:
> This patch fixes up the types used when converting back and forth between
> physical and virtual addresses.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  arch/arm/include/asm/memory.h |   17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 01c710d..4a0108f 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -157,22 +157,27 @@ extern unsigned long __pv_phys_offset;
>  
>  extern unsigned long __pv_offset;
>  
> -static inline unsigned long __virt_to_phys(unsigned long x)
> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>  {
>  	unsigned long t;
>  	early_patch_imm8(x, t, "add", __pv_offset);
>  	return t;
>  }
>  
> -static inline unsigned long __phys_to_virt(unsigned long x)
> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>  {
>  	unsigned long t;
>  	early_patch_imm8(x, t, "sub", __pv_offset);
>  	return t;
>  }
>  #else
> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
> +
> +#define __virt_to_phys(x)		\
> +	((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)
> +
> +#define __phys_to_virt(x)		\
> +	((unsigned long)((phys_addr_t)(x) - PHYS_OFFSET + PAGE_OFFSET))
> +
>  #endif
>  #endif
>  
> @@ -207,14 +212,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>  
>  static inline void *phys_to_virt(phys_addr_t x)
>  {
> -	return (void *)(__phys_to_virt((unsigned long)(x)));
> +	return (void *)__phys_to_virt(x);
>  }
>  
>  /*
>   * Drivers should NOT use these either.
>   */
>  #define __pa(x)			__virt_to_phys((unsigned long)(x))
> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>  #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)

This as a whole does not fill me with a great amount of enthusiasm,
because it breaks some of the typechecking that we have here.

The whole point of __phys_to_virt() and __virt_to_phys() is that they work
on integer types, and warn if you dare to use them with pointers.  Adding
a cast into them breaks that.

The whole point is that the typecasting is explicitly inside phys_to_virt()
and virt_to_phys() and not their macro counterparts.

Secondly, are you sure that this patch is correct on its own?  You're
passing a u64 into assembly only expecting a 32-bit register.  Have you
checked it does the right thing with a 64-bit phys_addr_t on both LE
and BE?


From stefano.stabellini at eu.citrix.com  Mon Aug  6 07:17:10 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 12:17:10 +0100
Subject: [PATCH 09/24] xen/arm: compile and run xenbus
In-Reply-To: <20120801142840.GG7227@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1207251741470.26163@kaball.uk.xensource.com>
 <1343316846-25860-9-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120801142840.GG7227@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208061200130.4645@kaball.uk.xensource.com>

On Wed, 1 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Thu, Jul 26, 2012 at 04:33:51PM +0100, Stefano Stabellini wrote:
> > bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> > an error.
> > 
> > If Linux is running as an HVM domain and is running as Dom0, use
> > xenstored_local_init to initialize the xenstore page and event channel.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  drivers/xen/xenbus/xenbus_comms.c |    2 +-
> >  drivers/xen/xenbus/xenbus_probe.c |   27 +++++++++++++++++----------
> >  drivers/xen/xenbus/xenbus_xs.c    |    1 +
> >  3 files changed, 19 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> > index 52fe7ad..c5aa55c 100644
> > --- a/drivers/xen/xenbus/xenbus_comms.c
> > +++ b/drivers/xen/xenbus/xenbus_comms.c
> > @@ -224,7 +224,7 @@ int xb_init_comms(void)
> >  		int err;
> >  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
> >  						0, "xenbus", &xb_waitq);
> > -		if (err <= 0) {
> > +		if (err < 0) {
> >  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
> >  			return err;
> >  		}
> > diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> > index b793723..3ae47c2 100644
> > --- a/drivers/xen/xenbus/xenbus_probe.c
> > +++ b/drivers/xen/xenbus/xenbus_probe.c
> > @@ -729,16 +729,23 @@ static int __init xenbus_init(void)
> >  	xenbus_ring_ops_init();
> >  
> >  	if (xen_hvm_domain()) {
> > -		uint64_t v = 0;
> > -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> > -		if (err)
> > -			goto out_error;
> > -		xen_store_evtchn = (int)v;
> > -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> > -		if (err)
> > -			goto out_error;
> > -		xen_store_mfn = (unsigned long)v;
> > -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> > +		if (xen_initial_domain()) {
> > +			err = xenstored_local_init();
> > +			xen_store_interface =
> > +				phys_to_virt(xen_store_mfn << PAGE_SHIFT);
> > +		} else {
> > +			uint64_t v = 0;
> > +			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> > +			if (err)
> > +				goto out_error;
> > +			xen_store_evtchn = (int)v;
> > +			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> > +			if (err)
> > +				goto out_error;
> > +			xen_store_mfn = (unsigned long)v;
> > +			xen_store_interface =
> > +				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> > +		}
> 
> This, and along with the Hybrid PV dom0 (not yet posted, but it was doing
> similar manipulation here) is getting more and more like a rat-mess.
> 
> 
> Any chance we can just abstract the three different XenStore access
> ways and just have something like this:
> 
> 	enum {
> 		USE_UNKNOWN
> 		USE_HVM,
> 		USE_PV,
> 		USE_LOCAL
> 		USE_ALREADY_INIT
> 	};
> 	int usage = USE_UNKNOWN;
> 	if (xen_pv_domain())
> 		usage = USE_PV;
> 	if (xen_hvm_domain())
> 		usage = USE_HVM;
> 	if (xen_initial_domain())
> 		usage = USE_LOCAL;
> 
> 	if (xen_start_info->store_evtchn)
> 		usage = USE_ALREADY_INIT;
> 	
> 	.. other overwrites..
> 
> 	switch (usage) {
> 		.. blah blah.
> 	}

I'll give it a try.


From linus.walleij at linaro.org  Mon Aug  6 07:17:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 Aug 2012 13:17:56 +0200
Subject: [PATCH 6/6] Input: ab8500-ponkey: Make the distinction between DT
 and non-DT boots
In-Reply-To: <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZmZtQJ_tqp8=cC2NbRvNosN8rDwfwDxocw=a=WtH0sZg@mail.gmail.com>

On Mon, Aug 6, 2012 at 12:46 PM, Lee Jones <lee.jones at linaro.org> wrote:

> If we're booting with Device Tree enabled, we want the IRQ numbers to
> be taken and translated from the Device Tree binary. If not, they
> should be taken from the resource allocation defined in the AB8500 MFD
> core driver.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Aha that's the missing patch.
Tested-by: Linus Walleij <linus.walleij at linaro.org>

This one should be split off from the patch series and sent as a separate
fix to Dmitry as it badly needs to go into the -rc series through the input
tree.

Can't see what it is doing as part of this series, it has no relation to the
other patches.

Dmitry, you can replace my revert with this patch as soon as Lee send
it to linux-input.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug  6 07:23:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 Aug 2012 13:23:13 +0200
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver
In-Reply-To: <20120806102151.GB16996@gmail.com>
References: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
 <20120806102151.GB16996@gmail.com>
Message-ID: <CACRpkdZRCJXFGAVaD2eFWDhRX_=1G=MzDp=-PB6C3HKUpqkkWA@mail.gmail.com>

On Mon, Aug 6, 2012 at 12:21 PM, Lee Jones <lee.jones at linaro.org> wrote:

> From: Lee Jones <lee.jones at linaro.org>
> Date: Mon, 6 Aug 2012 11:04:14 +0100
> Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
>  driver.
>
> At this moment in time there is only one known configuration for the
> Nomadik I2C driver. By not holding that configuration in the driver
> adds some unnecessary overhead in platform code. The configuration
> as already been removed from platform code, this patch checks for any
> over-riding configurations. If there aren't any, the default is used.
>
> Cc: linux-i2c at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Ah, I created my own solution for this as well by reverting back
some platform data.

This works too, but the patch does not apply to v3.6-rc1.
Please rebase and repost, then you can add my
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Please not that you need to send I2C patches for embedded
to Wolfram Sang.

Wolfram, please pick this for the -rc series because it's a regression
in v3.6-rc1.

Yours,
Linus Walleij


From kishon at ti.com  Mon Aug  6 07:25:31 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 16:55:31 +0530
Subject: [PATCH v3 2/2] arm/dts: omap4: Add ocp2scp data
In-Reply-To: <1344252331-18456-1-git-send-email-kishon@ti.com>
References: <1344252331-18456-1-git-send-email-kishon@ti.com>
Message-ID: <1344252331-18456-3-git-send-email-kishon@ti.com>

Add ocp2scp data node in omap4 device tree file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..8a780b2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,13 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
 		};
+
+		ocp2scp {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			ti,hwmods = "ocp2scp_usb_phy";
+		};
 	};
 };
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 07:25:29 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 16:55:29 +0530
Subject: [PATCH v3 0/2] omap: add ocp2scp as a bus driver
Message-ID: <1344252331-18456-1-git-send-email-kishon@ti.com>

This patch series is done as a preparatory step for adding phy drivers
for dwc3 and musb.

This series adds a new driver for ocp2scp (only dt) to which phy
drivers are connected.

Since currently there is no generic way to create a child device along
with doing a pm_runtime_enable (the exact requirement for ocp2scp), I'm
creating a separate driver for ocp2scp.

Changes from v2:
Fixed Felipe's comments to avoid using arch_initcall and make dependent
drivers return -EPROBE_DEFER case this isn't ready yet.

Changes from v1:
Fixed Sergei's comments to remove the address in the node name of ocp2scp
since the ocp2scp node doesn't have a reg property.

Changes from [RFC PATCH v2 0/2] omap: add ocp2scp as a misc driver:
Created a new folder drivers/bus and moved ocp2scp driver from misc to
drivers/bus.

This patch was developed and tested on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git

Kishon Vijay Abraham I (2):
  drivers: bus: add a new driver for omap-ocp2scp
  arm/dts: omap4: Add ocp2scp data

 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 arch/arm/boot/dts/omap4.dtsi                       |    8 ++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 7 files changed, 130 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 07:25:30 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 16:55:30 +0530
Subject: [PATCH v3 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <1344252331-18456-1-git-send-email-kishon@ti.com>
References: <1344252331-18456-1-git-send-email-kishon@ti.com>
Message-ID: <1344252331-18456-2-git-send-email-kishon@ti.com>

Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
USB2PHY is connected to ocp2scp.

This also includes device tree support for ocp2scp driver and
the documentation with device tree binding information is updated.

Acked-by: Felipe Balbi <balbi at ti.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 6 files changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
new file mode 100644
index 0000000..d2fe064
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -0,0 +1,10 @@
+* OMAP OCP2SCP - ocp interface to scp interface
+
+properties:
+- compatible : Should be "ti,omap-ocp2scp"
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ranges : the child address space are mapped 1:1 onto the parent address space
+- ti,hwmods : must be "ocp2scp_usb_phy"
+
+Sub-nodes:
+All the devices connected to ocp2scp are described using sub-node to ocp2scp
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ece958d..324e958 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -2,6 +2,8 @@ menu "Device Drivers"
 
 source "drivers/base/Kconfig"
 
+source "drivers/bus/Kconfig"
+
 source "drivers/connector/Kconfig"
 
 source "drivers/mtd/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 5b42184..f8cdeeb 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y				+= bus/
+
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
new file mode 100644
index 0000000..6270415
--- /dev/null
+++ b/drivers/bus/Kconfig
@@ -0,0 +1,15 @@
+#
+# Bus Devices
+#
+
+menu "Bus devices"
+
+config OMAP_OCP2SCP
+	tristate "OMAP OCP2SCP DRIVER"
+	help
+	  Driver to enable ocp2scp module which transforms ocp interface
+	  protocol to scp protocol. In OMAP4, USB PHY is connected via
+	  OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
+	  OCP2SCP.
+
+endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
new file mode 100644
index 0000000..0ec50bc
--- /dev/null
+++ b/drivers/bus/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the bus drivers.
+#
+
+obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
new file mode 100644
index 0000000..881d5bb
--- /dev/null
+++ b/drivers/bus/omap-ocp2scp.c
@@ -0,0 +1,88 @@
+/*
+ * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+static int ocp2scp_remove_devices(struct device *dev, void *c)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	platform_device_unregister(pdev);
+
+	return 0;
+}
+
+static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
+{
+	int			ret;
+	struct device_node	*np = pdev->dev.of_node;
+
+	if (np) {
+		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
+			goto err0;
+		}
+	}
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+
+err0:
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return ret;
+}
+
+static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_ocp2scp_id_table[] = {
+	{ .compatible = "ti,omap-ocp2scp" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
+static struct platform_driver omap_ocp2scp_driver = {
+	.probe		= omap_ocp2scp_probe,
+	.remove		= __devexit_p(omap_ocp2scp_remove),
+	.driver		= {
+		.name	= "omap-ocp2scp",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),
+	},
+};
+
+module_platform_driver(omap_ocp2scp_driver);
+
+MODULE_ALIAS("platform: omap-ocp2scp");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_DESCRIPTION("OMAP OCP2SCP DRIVER");
+MODULE_LICENSE("GPLv2");
-- 
1.7.9.5



From hvaibhav at ti.com  Mon Aug  6 07:29:04 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 6 Aug 2012 16:59:04 +0530
Subject: [PATCH] arm/dts: AM33XX: Set the default status of module to
 "disabled" state
Message-ID: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>

Ideally in common SoC dtsi file we should set all modules
to "disabled" state and it should get enabled in respective
EVM/Board dts file as per usage.

This patch sets default status of all modules to "disabled"
state in am33xx.dtsi file, and as per board requirement, enabled
in board dts file (like, bone, evm, etc...).

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Arnd Bergmann <arnd at arndb.de>
CC: Tony Lindgren <tony at atomide.com>
---
This patch is tested on BeagleBone platform.

 arch/arm/boot/dts/am335x-bone.dts |    6 ++++++
 arch/arm/boot/dts/am335x-evm.dts  |    6 ++++++
 arch/arm/boot/dts/am33xx.dtsi     |    9 +++++++++
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db..df672b4 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,10 @@
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
+
+	ocp {
+		uart1: serial at 44E09000 {
+			       status = "okay";
+		       };
+	};
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9..00bbae8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,10 @@
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
+
+	ocp {
+		uart1: serial at 44E09000 {
+			       status = "okay";
+		       };
+	};
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c4..5f6c8e3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,36 +102,42 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart2: serial at 48022000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart3: serial at 48024000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart4: serial at 481A6000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart5: serial at 481A8000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart6: serial at 481AA000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		i2c1: i2c at 44E0B000 {
@@ -139,6 +145,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			status = "disabled";
 		};

 		i2c2: i2c at 4802A000 {
@@ -146,6 +153,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			status = "disabled";
 		};

 		i2c3: i2c at 4819C000 {
@@ -153,6 +161,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			status = "disabled";
 		};
 	};
 };
--
1.7.0.4



From linus.walleij at stericsson.com  Mon Aug  6 07:37:04 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 6 Aug 2012 13:37:04 +0200
Subject: [PATCH] ARM: ux500: resurrect I2C platform data
In-Reply-To: <20120806095144.GA16996@gmail.com>
References: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
 <20120806095144.GA16996@gmail.com>
Message-ID: <501FAC60.1080600@stericsson.com>

On 08/06/2012 11:51 AM, Lee Jones wrote:
> On Mon, Aug 06, 2012 at 10:52:26AM +0200, Linus Walleij wrote:
>> Commit:
>> 98582d9562b4bea6b0eb6e2bfafcd3fab3b60ccb
>> "ARM: ux500: Remove unused i2c platform_data initialisation code"
>>
>> Deleted platform data intialization code that was used,
>> not unused as indicated in the commit. The boot log (without
>> devicetree) now looks like this:
> The aforementioned commit was part of a patch-set. One of its affiliates
> moved this code into the Nomadik I2C driver; however, it was contested
> because Device Tree support was also added and the maintainer thought
> the properties introduced could be consolidated with other I2C driver's
> DT properties. I don't think anyone has taken up the consolidation work
> and for that reason it hasn't gone in.

Too bad it had to turn into a regression though :-P

> I think moving this stuff into the driver is the right thing to do.
> Instead, I'll split out the configuration and DT enablement from the
> patch and resubmit.
>
> Sound good to you?

Either way works with me, but the patch sent out need to be
rebased and sent to Wolfram. Either he applies that to the I2C
tree or I apply this to the ux500 tree. So it's for Wolfram to decide.

Yours,
Linus Walleij


From dirk.behme at de.bosch.com  Mon Aug  6 07:38:42 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Mon, 6 Aug 2012 13:38:42 +0200
Subject: [PATCH 1/4] gpio/mxc: remove redundant shadow variables
 initialization
In-Reply-To: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <501FACC2.4010008@de.bosch.com>

On 05.08.2012 08:01, Shawn Guo wrote:
> With commit 3e11f7b (gpio/generic: initialize basic_mmio_gpio shadow
> variables properly) in place, the shadow variables initialization is
> being done in generic driver bgpio_init call.
> 
> Remove the redundant shadow variables initialization from gpio-mxc
> driver.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Whole series:

Tested-by: Dirk Behme <dirk.behme at de.bosch.com>

Looks good :)

Many thanks

Dirk

> ---
>  drivers/gpio/gpio-mxc.c |    2 --
>  1 files changed, 0 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
> index 4db460b..76e8cda 100644
> --- a/drivers/gpio/gpio-mxc.c
> +++ b/drivers/gpio/gpio-mxc.c
> @@ -466,8 +466,6 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
>  
>  	port->bgc.gc.to_irq = mxc_gpio_to_irq;
>  	port->bgc.gc.base = pdev->id * 32;
> -	port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
> -	port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
>  
>  	err = gpiochip_add(&port->bgc.gc);
>  	if (err)


From srinidhi.kasagar at stericsson.com  Mon Aug  6 07:43:51 2012
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Mon, 6 Aug 2012 17:13:51 +0530
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik
 I2C driver
In-Reply-To: <20120806102151.GB16996@gmail.com>
References: <1344243146-6598-1-git-send-email-linus.walleij@stericsson.com>
 <20120806102151.GB16996@gmail.com>
Message-ID: <20120806114351.GA10412@bnru02>

On Mon, Aug 06, 2012 at 12:21:52 +0200, Lee Jones wrote:
> From: Lee Jones <lee.jones at linaro.org>
> Date: Mon, 6 Aug 2012 11:04:14 +0100
> Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
>  driver.
> 
> At this moment in time there is only one known configuration for the
> Nomadik I2C driver. By not holding that configuration in the driver
> adds some unnecessary overhead in platform code. The configuration
> as already been removed from platform code, this patch checks for any
> over-riding configurations. If there aren't any, the default is used.
> 
> Cc: linux-i2c at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/i2c/busses/i2c-nomadik.c |   24 ++++++++++++++++++------
>  1 file changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
> index a92440d..86aa73d 100644
> --- a/drivers/i2c/busses/i2c-nomadik.c
> +++ b/drivers/i2c/busses/i2c-nomadik.c
> @@ -333,10 +333,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
>  
>  	i2c_clk = clk_get_rate(dev->clk);
>  
> -	/* fallback to std. mode if machine has not provided it */
> -	if (dev->cfg.clk_freq == 0)
> -		dev->cfg.clk_freq = 100000;
> -
>  	/*
>  	 * The spec says, in case of std. mode the divider is
>  	 * 2 whereas it is 3 for fast and fastplus mode of
> @@ -899,15 +895,31 @@ static const struct i2c_algorithm nmk_i2c_algo = {
>  	.functionality	= nmk_i2c_functionality
>  };
>  
> +static struct nmk_i2c_controller u8500_i2c = {
> +	/*
> +	 * Slave data setup time; 250ns, 100ns, and 10ns, which
> +	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
> +	 */
> +	.slsu           = 0xe,
> +	.tft            = 1,      /* Tx FIFO threshold */
> +	.rft            = 8,      /* Rx FIFO threshold */
> +	.clk_freq       = 400000, /* std. mode operation */
"Fast mode operation" in comment, or use your favorite "upto" keyword.

Otherwise it is Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

/srinidhi


From arnd at arndb.de  Mon Aug  6 07:46:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 11:46:58 +0000
Subject: [PATCH] arm/dts: AM33XX: Set the default status of module to
 "disabled" state
In-Reply-To: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>
References: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>
Message-ID: <201208061146.58753.arnd@arndb.de>

On Monday 06 August 2012, Vaibhav Hiremath wrote:
> Ideally in common SoC dtsi file we should set all modules
> to "disabled" state and it should get enabled in respective
> EVM/Board dts file as per usage.
> 
> This patch sets default status of all modules to "disabled"
> state in am33xx.dtsi file, and as per board requirement, enabled
> in board dts file (like, bone, evm, etc...).
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Arnd Bergmann <arnd at arndb.de>
> CC: Tony Lindgren <tony at atomide.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Mon Aug  6 07:50:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 11:50:52 +0000
Subject: [PATCH 2/6] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <1344250002-6011-3-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-3-git-send-email-lee.jones@linaro.org>
Message-ID: <201208061150.53076.arnd@arndb.de>

On Monday 06 August 2012, Lee Jones wrote:

>  
> +struct irq_domain *db8500_irq_domain;
> +
 
Should this be static?

> @@ -2583,7 +2585,7 @@ static void prcmu_irq_mask(struct irq_data *d)
>  
>         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
>  
> -       mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
> +       mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
>  
>         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);

Ah, so the hwirq number *is* used directly here, unlike what I thought
when we first discussed it. I suppose that means we don't need the
xlate function after all (and you did not add one).

	Arnd


From balbi at ti.com  Mon Aug  6 07:50:20 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 6 Aug 2012 14:50:20 +0300
Subject: [PATCH v3 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <1344252331-18456-2-git-send-email-kishon@ti.com>
References: <1344252331-18456-1-git-send-email-kishon@ti.com>
 <1344252331-18456-2-git-send-email-kishon@ti.com>
Message-ID: <20120806115018.GB28645@arwen.pp.htv.fi>

On Mon, Aug 06, 2012 at 04:55:30PM +0530, Kishon Vijay Abraham I wrote:
> Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
> creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
> USB2PHY is connected to ocp2scp.
> 
> This also includes device tree support for ocp2scp driver and
> the documentation with device tree binding information is updated.
> 
> Acked-by: Felipe Balbi <balbi at ti.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> ---
>  .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
>  drivers/Kconfig                                    |    2 +
>  drivers/Makefile                                   |    2 +
>  drivers/bus/Kconfig                                |   15 ++++
>  drivers/bus/Makefile                               |    5 ++
>  drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
>  6 files changed, 122 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
>  create mode 100644 drivers/bus/Kconfig
>  create mode 100644 drivers/bus/Makefile
>  create mode 100644 drivers/bus/omap-ocp2scp.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
> new file mode 100644
> index 0000000..d2fe064
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
> @@ -0,0 +1,10 @@
> +* OMAP OCP2SCP - ocp interface to scp interface
> +
> +properties:
> +- compatible : Should be "ti,omap-ocp2scp"
> +- #address-cells, #size-cells : Must be present if the device has sub-nodes
> +- ranges : the child address space are mapped 1:1 onto the parent address space
> +- ti,hwmods : must be "ocp2scp_usb_phy"
> +
> +Sub-nodes:
> +All the devices connected to ocp2scp are described using sub-node to ocp2scp
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index ece958d..324e958 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -2,6 +2,8 @@ menu "Device Drivers"
>  
>  source "drivers/base/Kconfig"
>  
> +source "drivers/bus/Kconfig"
> +
>  source "drivers/connector/Kconfig"
>  
>  source "drivers/mtd/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 5b42184..f8cdeeb 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -5,6 +5,8 @@
>  # Rewritten to use lists instead of if-statements.
>  #
>  
> +obj-y				+= bus/
> +
>  # GPIO must come after pinctrl as gpios may need to mux pins etc
>  obj-y				+= pinctrl/
>  obj-y				+= gpio/
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> new file mode 100644
> index 0000000..6270415
> --- /dev/null
> +++ b/drivers/bus/Kconfig
> @@ -0,0 +1,15 @@
> +#
> +# Bus Devices
> +#
> +
> +menu "Bus devices"
> +
> +config OMAP_OCP2SCP
> +	tristate "OMAP OCP2SCP DRIVER"
> +	help
> +	  Driver to enable ocp2scp module which transforms ocp interface
> +	  protocol to scp protocol. In OMAP4, USB PHY is connected via
> +	  OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
> +	  OCP2SCP.
> +
> +endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> new file mode 100644
> index 0000000..0ec50bc
> --- /dev/null
> +++ b/drivers/bus/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for the bus drivers.
> +#
> +
> +obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
> diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
> new file mode 100644
> index 0000000..881d5bb
> --- /dev/null
> +++ b/drivers/bus/omap-ocp2scp.c
> @@ -0,0 +1,88 @@
> +/*
> + * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * Author: Kishon Vijay Abraham I <kishon at ti.com>
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +static int ocp2scp_remove_devices(struct device *dev, void *c)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +
> +	platform_device_unregister(pdev);
> +
> +	return 0;
> +}
> +
> +static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
> +{
> +	int			ret;
> +	struct device_node	*np = pdev->dev.of_node;
> +
> +	if (np) {
> +		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
> +		if (ret) {
> +			dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
> +			goto err0;
> +		}
> +	}
> +	pm_runtime_enable(&pdev->dev);
> +
> +	return 0;
> +
> +err0:
> +	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
> +
> +	return ret;
> +}
> +
> +static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
> +{
> +	pm_runtime_disable(&pdev->dev);
> +	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id omap_ocp2scp_id_table[] = {
> +	{ .compatible = "ti,omap-ocp2scp" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
> +#endif
> +
> +static struct platform_driver omap_ocp2scp_driver = {
> +	.probe		= omap_ocp2scp_probe,
> +	.remove		= __devexit_p(omap_ocp2scp_remove),
> +	.driver		= {
> +		.name	= "omap-ocp2scp",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),
> +	},
> +};
> +
> +module_platform_driver(omap_ocp2scp_driver);
> +
> +MODULE_ALIAS("platform: omap-ocp2scp");
> +MODULE_AUTHOR("Texas Instruments Inc.");
> +MODULE_DESCRIPTION("OMAP OCP2SCP DRIVER");

driver isn't an acronym, so it need not be all uppercase. (nit-picking,
I know :-)

> +MODULE_LICENSE("GPLv2");

it should be "GPL v2" with a space. See <linux/module.h>.

-- 
balbi
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From mina86 at mina86.com  Mon Aug  6 07:58:32 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Mon, 06 Aug 2012 13:58:32 +0200
Subject: [PATCH 2/2] dma-buf: add helpers for attacher dma-parms
In-Reply-To: <501F9C8E.4080002@samsung.com>
References: <1342715014-5316-1-git-send-email-rob.clark@linaro.org>
 <1342715014-5316-3-git-send-email-rob.clark@linaro.org>
 <501F9C8E.4080002@samsung.com>
Message-ID: <xa1tobmoxmdz.fsf@mina86.com>


Tomasz Stanislawski <t.stanislaws at samsung.com> writes:
> I recommend to change the semantics for unlimited number of segments
> from 'value 0' to:
>
> #define DMA_SEGMENTS_COUNT_UNLIMITED ((unsigned long)INT_MAX)
>
> Using INT_MAX will allow using safe conversions between signed and
> unsigned integers.

LONG_MAX seems cleaner regardless.

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--
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From mchehab at redhat.com  Mon Aug  6 08:13:00 2012
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Mon, 06 Aug 2012 09:13:00 -0300
Subject: Vacations.
In-Reply-To: <Pine.LNX.4.64.1208031708200.5170@axis700.grange>
References: <CACKLOr1Q6_xVhaaoWiy-kf9hViTW98aSa6hd5M2z7ogL-uwNVQ@mail.gmail.com>
 <Pine.LNX.4.64.1208031708200.5170@axis700.grange>
Message-ID: <501FB4CC.1060301@redhat.com>

Em 03-08-2012 12:09, Guennadi Liakhovetski escreveu:
> Hi Javier
> 
> On Fri, 3 Aug 2012, javier Martin wrote:
> 
>> Hi,
>> I will be out of the office until August the 19th.
>>
>> I just wanted to send a reminder of some patches that I have pending.
>>
>> For Mauro 3.7:
>>
>> [PULL] video_visstrim for 3.6
>> [PATCH] media: i.MX27: Fix mx2_emmaprp mem2mem driver clocks.

Both got merged.

>>
>> For Guennadi:
>>
>> [PATCH 1/4] i.MX27: Fix emma-prp and csi clocks.
> 
> As I mentioned several times, the above patch is not for me. Have a nice 
> vacation.

It is an -arm patch, so it is not for me.

Have nice vacations

Regards,
Mauro


From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:28 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:28 +0200
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
Message-ID: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds DT support for Marvell Dove SoC and three boards
equipped with this SoC. The work is based on device tree support for
Marvell Orion based SoCs introduced in 3.6-rc1.

The first three patches move mach-dove closer to Marvell Kirkwood's
setup code by unifying the clock setup routines, adding clock gating
control, and support for Marvell's crypto engine to mach-dove.

Patches 4 and 5 add a generic DT machine descriptor to mach-dove and
corresponding DT descriptors for the SoC and already supported boards.

Finally, the last patch adds a DT descriptor for the SolidRun CuBox,
a plug computer based on Marvell Dove.

This patch set relies on a DT support patch for sdhci-dove that has
been sent to the corresponding maintainers a few days ago.

Sebastian Hesselbarth (6):
  ARM: dove: unify clock setup
  ARM: dove: add clock gating control
  ARM: dove: add crypto engine
  ARM: dove: add device tree based machine descriptor
  ARM: dove: add device tree descriptors
  ARM: dove: SolidRun CuBox DT

 arch/arm/boot/dts/dove-cm-a510.dts   |   38 ++++++++
 arch/arm/boot/dts/dove-cubox.dts     |   42 +++++++++
 arch/arm/boot/dts/dove-dove-db.dts   |   38 ++++++++
 arch/arm/boot/dts/dove.dtsi          |  143 ++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Kconfig           |    7 ++
 arch/arm/mach-dove/Makefile.boot     |    4 +
 arch/arm/mach-dove/common.c          |  159 +++++++++++++++++++++++++++++++---
 arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++----
 8 files changed, 455 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:29 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:29 +0200
Subject: [PATCH 1/6] ARM: dove: unify clock setup
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch synchronizes the clock setup of dove with other orion-based
platforms.

In dove_find_tclk there was a note about DOVE_SAMPLE_HI/LO register to
detect tclk. While it might be possible to set a different tclk frequency 
with reset strapping the Dove datasheets don't tell anything about tclk 
frequency here. Therefore, I removed that comment.

Also, the patch ensures that tclk is always clocked by prepare/enable.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c |   22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 4db5de5..20b765c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -33,8 +33,6 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -70,14 +68,18 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static void __init dove_clk_init(void)
 {
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-				       get_tclk());
+				       dove_tclk);
 
 	orion_clkdev_init(tclk);
+
+	/* Ensure tclk is always clocked */
+	clk_prepare_enable(tclk);
 }
 
 /*****************************************************************************
@@ -187,16 +189,16 @@ void __init dove_init_early(void)
 	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
 	return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+	dove_tclk = dove_find_tclk();
 	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_DOVE_BRIDGE, get_tclk());
+			IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -284,8 +286,8 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-	printk(KERN_INFO "Dove 88AP510 SoC, ");
-	printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init();
@@ -293,7 +295,7 @@ void __init dove_init(void)
 	dove_setup_cpu_mbus();
 
 	/* Setup root of clk tree */
-	clk_init();
+	dove_clk_init();
 
 	/* internal devices that every board has */
 	dove_rtc_init();
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:30 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:30 +0200
Subject: [PATCH 2/6] ARM: dove: add clock gating control
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-3-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds clock gates from the clock gating control register
available on dove. All clock gates are hooked up to tclk, except for
gigabit ethernet controller (ge) which is a child of gephy to allow
both enabled/disabled at the same time.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c          |   59 +++++++++++++++++++++++++++++++++-
 arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++++++++++++++-----------
 2 files changed, 94 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 20b765c..e074f1c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/mv643xx_i2c.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,6 +25,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -31,6 +33,7 @@
 #include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
+#include <plat/mv_xor.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -69,14 +72,68 @@ void __init dove_map_io(void)
  * CLK tree
  ****************************************************************************/
 static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
+static struct clk __init *dove_register_gate(const char *name,
+					     const char *parent, u8 bit_idx)
+{
+	return clk_register_gate(NULL, name, parent, 0,
+				 (void __iomem *)CLOCK_GATING_CONTROL,
+				 bit_idx, 0, &gating_lock);
+}
+
 static void __init dove_clk_init(void)
 {
+	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+	struct clk *xor0, *xor1, *ge, *gephy;
+
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 				       dove_tclk);
 
-	orion_clkdev_init(tclk);
+	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+	pex0 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE0);
+	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+	orion_clkdev_add(NULL, "orion_spi.0", tclk);
+	orion_clkdev_add(NULL, "orion_spi.1", tclk);
+	orion_clkdev_add(NULL, "orion_wdt", tclk);
+	orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
+
+	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge);
+	orion_clkdev_add("0", "sata_mv.0", sata);
+	orion_clkdev_add("0", "pcie", pex0);
+	orion_clkdev_add("1", "pcie", pex1);
+	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+	orion_clkdev_add(NULL, "orion_nand", nand);
+	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+	orion_clkdev_add(NULL, "mv_crypto", crypto);
+	orion_clkdev_add(NULL, "dove-ac97", ac97);
+	orion_clkdev_add(NULL, "dove-pdma", pdma);
+	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
+	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
 
 	/* Ensure tclk is always clocked */
 	clk_prepare_enable(tclk);
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f94..7bcd0df 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL	(DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK		(1 << 0)
-#define  CLOCK_GATING_USB1_MASK		(1 << 1)
-#define  CLOCK_GATING_GBE_MASK		(1 << 2)
-#define  CLOCK_GATING_SATA_MASK		(1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK	(1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK	(1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK	(1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK	(1 << 9)
-#define  CLOCK_GATING_NAND_MASK		(1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK	(1 << 11)
-#define  CLOCK_GATING_I2S0_MASK		(1 << 12)
-#define  CLOCK_GATING_I2S1_MASK		(1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK	(1 << 15)
-#define  CLOCK_GATING_AC97_MASK		(1 << 21)
-#define  CLOCK_GATING_PDMA_MASK		(1 << 22)
-#define  CLOCK_GATING_XOR0_MASK		(1 << 23)
-#define  CLOCK_GATING_XOR1_MASK		(1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << 30)
+#define  CLOCK_GATING_BIT_USB0		0
+#define  CLOCK_GATING_BIT_USB1		1
+#define  CLOCK_GATING_BIT_GBE		2
+#define  CLOCK_GATING_BIT_SATA		3
+#define  CLOCK_GATING_BIT_PCIE0		4
+#define  CLOCK_GATING_BIT_PCIE1		5
+#define  CLOCK_GATING_BIT_SDIO0		8
+#define  CLOCK_GATING_BIT_SDIO1		9
+#define  CLOCK_GATING_BIT_NAND		10
+#define  CLOCK_GATING_BIT_CAMERA	11
+#define  CLOCK_GATING_BIT_I2S0		12
+#define  CLOCK_GATING_BIT_I2S1		13
+#define  CLOCK_GATING_BIT_CRYPTO	15
+#define  CLOCK_GATING_BIT_AC97		21
+#define  CLOCK_GATING_BIT_PDMA		22
+#define  CLOCK_GATING_BIT_XOR0		23
+#define  CLOCK_GATING_BIT_XOR1		24
+#define  CLOCK_GATING_BIT_GIGA_PHY	30
+#define  CLOCK_GATING_USB0_MASK		(1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK		(1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK		(1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK		(1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK	(1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK	(1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK	(1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK	(1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK		(1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK	(1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK		(1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK		(1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK	(1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK		(1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK		(1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK		(1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK		(1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE	(DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK	(DOVE_PMU_VIRT_BASE + 0x54)
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:31 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:31 +0200
Subject: [PATCH 3/6] ARM: dove: add crypto engine
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-4-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a dove specific setup function for the Marvell CESA
crypto engine available on orion based SoCs. Dove setup was just
missing a function to call orion_crypto_init with dove specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e074f1c..6f2fe65 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -263,6 +263,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+	orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+			  DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:32 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:32 +0200
Subject: [PATCH 4/6] ARM: dove: add device tree based machine descriptor
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-5-git-send-email-sebastian.hesselbarth@gmail.com>

This adds a generic DT_MACHINE for mach-dove. As with other orion based
SoCs there still is some glue code required to make all internal devices
work, i.e. auxdata is provided to pass clocks to corresponding device
drivers. 

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/Kconfig  |    7 +++++
 arch/arm/mach-dove/common.c |   67 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+)

diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c5..00154e7 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
 	  Say 'Y' here if you want your kernel to support the
 	  CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+	bool "Marvell Dove Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 6f2fe65..6f594bd3 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -17,6 +17,8 @@
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -30,6 +32,7 @@
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
+#include <plat/irq.h>
 #include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -384,3 +387,67 @@ void dove_restart(char mode, const char *cmd)
 	while (1)
 		;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+	OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+	OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+		       NULL),
+	OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+	{},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+	tauros2_init();
+#endif
+	dove_setup_cpu_mbus();
+
+	/* Setup root of clk tree */
+	dove_clk_init();
+
+	/* Internal devices not ported to DT yet */
+	dove_rtc_init();
+	dove_xor0_init();
+	dove_xor1_init();
+
+	dove_ge00_init(&dove_dt_ge00_data);
+	dove_ehci0_init();
+	dove_ehci1_init();
+	dove_pcie_init(1, 1);
+	dove_crypto_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+	"marvell,dove",
+	NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+	.map_io		= dove_map_io,
+	.init_early	= dove_init_early,
+	.init_irq	= orion_dt_init_irq,
+	.timer		= &dove_timer,
+	.init_machine	= dove_dt_init,
+	.restart	= dove_restart,
+	.dt_compat	= dove_dt_board_compat,
+MACHINE_END
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:33 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:33 +0200
Subject: [PATCH 5/6] ARM: dove: add device tree descriptors
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-6-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds device tree decriptors for dove SoC and currently
supported boards.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cm-a510.dts |   38 ++++++++++
 arch/arm/boot/dts/dove-dove-db.dts |   38 ++++++++++
 arch/arm/boot/dts/dove.dtsi        |  143 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot   |    3 +
 4 files changed, 222 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 0000000..61a8062
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Compulab CM-A510";
+	compatible = "compulab,cm-a510", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 0000000..e5a920b
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Marvell DB-MV88AP510-BP Development Board";
+	compatible = "marvell,dove-db", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash ST-M25P32-VMF6P */
+	spi-flash at 0 {
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 0000000..96fb824
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "marvell,dove";
+	model = "Marvell Armada 88AP510 SoC";
+
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller {
+		compatible = "marvell,orion-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xf1020204 0x04>,
+		      <0xf1020214 0x04>;
+	};
+
+	mbus at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0 0xf1000000 0x4000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <7>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart1: serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <8>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart2: serial at 12200 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <9>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart3: serial at 12300 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <10>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		wdt: wdt at 20300 {
+			compatible = "marvell,orion-wdt";
+			reg = <0x20300 0x28>;
+		};
+
+		gpio0: gpio at d0400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0400 0x20>;
+			ngpio = <32>;
+			interrupts = <12>, <13>, <14>, <60>;
+		};
+
+		gpio1: gpio at d0420 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0420 0x20>;
+			ngpio = <32>;
+			interrupts = <61>;
+		};
+
+		gpio2: gpio at e8400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xe8400 0x0c>;
+			ngpio = <8>;
+		};
+
+		spi0: spi at 10600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			interrupts = <6>;
+			reg = <0x10600 0x28>;
+			status = "disabled";
+		};
+
+		spi1: spi at 14600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			interrupts = <5>;
+			reg = <0x14600 0x28>;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11>;
+			clock-frequency = <400000>;
+			timeout-ms = <1000>;
+			status = "disabled";
+		};
+
+		sdio0: sdio at 92000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x92000 0x100>;
+			interrupts = <35>, <37>;
+			status = "disabled";
+		};
+
+		sdio1: sdio at 90000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x90000 0x100>;
+			interrupts = <36>, <38>;
+			status = "disabled";
+		};
+
+		sata0: sata at a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x2400>;
+			interrupts = <62>;
+			nr-ports = <1>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 760a0ef..94ab6b3 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -1,3 +1,6 @@
    zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Mon Aug  6 08:23:34 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon,  6 Aug 2012 14:23:34 +0200
Subject: [PATCH 6/6] ARM: dove: SolidRun CuBox DT
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344255815-4457-7-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds basic support for the SolidRun CuBox to DT based
mach-dove. There are still some issues related to ongoing orion/mvebu
development, e.g. gpio-led will not work as there is no DT pinctrl
for dove yet and we don't have board specific setup code. Nevertheless,
the DT description is already introduced here.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cubox.dts |   42 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot |    1 +
 2 files changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 0000000..0adbd5a
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "SolidRun CuBox";
+	compatible = "solidrun,cubox", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		power {
+			label = "Power";
+			gpios = <&gpio0 18 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 94ab6b3..cfac9c5 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cubox.dtb
-- 
1.7.10.4



From lee.jones at linaro.org  Mon Aug  6 08:25:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 13:25:47 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.
Message-ID: <1344255947-10062-1-git-send-email-lee.jones@linaro.org>

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index a92440d..34ab587 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -333,10 +333,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -899,15 +895,31 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* fast mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct resource *res;
-	struct nmk_i2c_controller *pdata =
-			pdev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = pdev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&pdev->dev, "cannot allocate memory\n");
-- 
1.7.9.5



From mkl at pengutronix.de  Mon Aug  6 08:27:20 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Mon, 06 Aug 2012 14:27:20 +0200
Subject: [RFC PATCH] gpio: Add a generic GPIO handling driver
In-Reply-To: <1340961676-25432-1-git-send-email-LW@KARO-electronics.de>
References: <1340961676-25432-1-git-send-email-LW@KARO-electronics.de>
Message-ID: <501FB828.7060604@pengutronix.de>

On 06/29/2012 11:21 AM, Lothar Wa?mann wrote:
> This driver provides an interface for device drivers that need to
> control some external hardware (e.g. reset or enable signals) for the
> devices they serve.
> 
> Features:
>  - supports sharing a single GPIO between multiple devices.
>  - optionally sets the controlled GPIOs to a predefined state upon
>    suspend/resume.
>  - handles output polarity
> 
> Client API:
> 	cookie = request_gpio_switch(dev, id);
> 	gpio_switch_set(cookie, on|off);
> 	free_gpio_switch(cookie);
> 
> 	gpio_switch_set_suspend_state(cookie, on|off)
> 	gpio_switch_set_resume_state(cookie, on|off)
> 
> request_gpio_switch() always returns a valid cookie (that may be NULL
> if the requested pin is not registered on the current platform), so
> that client drivers do not need to check whether the current platform
> provides a certain pin or not.
> 
> The client drivers only cope with the logical pin states
> (active/inactive, on/off) while the gpio-switch driver takes care of
> the output polarity handling.
> 
> The typical use of this driver in a client driver (e.g. flexcan
> transceiver switch) would be like (with DT):

Adding linux-can on Cc.

In CAN drivers we have the following use cases:
a) more than one CAN devices share the same transceiver
b) transceiver has more than one GPIO that has to be switched

For the b) use case I think we currently never toggle the switches
independently from each other. This will become a use case, when we
consider to implement proper transceiver drivers.

What about pin-mux? Should the switch driver request pin-mux for the
gpios it handles?

> in the .dts file:
> 	flexcan_transceiver: gpio-switch at 0 {
> 		compatible = "linux,gpio-switch";
> 		gpio = <&gpio4 21 1>; /* GPIO is active low */
> 		label = "Flexcan Transceiver Enable";
> 		gpio-shared;
> 		init-state = <0>; /* Transceiver will be initially inactive */
> 	};
> 
> in flexcan_probe()
> 	struct gpio_sw *xcvr_switch = NULL;
> 	struct device_node *np = pdev->dev.of_node;
> 
> 	if (np) {
> 		ph = of_get_property(np, "transceiver-switch", NULL);
> 		if (ph) {
> 			xcvr_switch = request_gpio_switch(&pdev->dev,
> 					be32_to_cpu(*ph));
> 		}
> 	}

I don't like open coding this. What providing a devm capable helper
function.

> ...
> static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
> {
> 	if (priv->pdata && priv->pdata->transceiver_switch)
> 		priv->pdata->transceiver_switch(on);
> 	else
> 		gpio_switch_set(priv->xcvr_switch, on);
> }
> ...
> flexcan_remove()
>     free_gpio_switch(xcvr_switch);
> 
> Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
> ---
>  .../devicetree/bindings/gpio/gpio-switch.txt       |   36 ++
>  drivers/gpio/Kconfig                               |    9 +
>  drivers/gpio/Makefile                              |    3 +
>  drivers/gpio/gpio-switch.c                         |  389 ++++++++++++++++++++
>  include/linux/gpio-switch.h                        |   47 +++
>  5 files changed, 484 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio-switch.txt
>  create mode 100644 drivers/gpio/gpio-switch.c
>  create mode 100644 include/linux/gpio-switch.h
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-switch.txt b/Documentation/devicetree/bindings/gpio/gpio-switch.txt
> new file mode 100644
> index 0000000..d91c628
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-switch.txt
> @@ -0,0 +1,36 @@
> +Device-Tree bindings for gpio/gpio-switch.c driver
> +
> +Required properties:
> +	- compatible = "linux,gpio-switch";
> +	- gpios: OF device-tree gpio specification
> +
> +Optional properties:
> +	- label: Human readable name for the gpio function
> +	- init-state: specifies whether the gpio should be switched
> +	  active or inactive on startup.
> +	  If not set, pin will be initialized to the inactive state.
> +	- suspend-state: specifies the state that the GPIO should be
> +	  set to when suspending.
> +	  If not set, pin state will not be changed upon suspend.
> +	- resume-state: specifies the state that the GPIO should be
> +	  set to when resuming.
> +	  If not set, pin state will not be changed upon resume.
> +	- gpio-shared: Boolean, Enable refcounted
> +	  assertion/deassertion of the GPIO for a pin that is shared
> +	  between multiple devices.
> +
> +Pin states are logical states. The actual pin output state is
> +determined by the active low flag of the referenced gpio.
> +
> +Example nodes:
> +
> +	gpio-switch {
> +		compatible = "linux,gpio-switch";
> +		flexcan_transceiver: gpio-switch at 0 {
> +			label = "Flexcan transceiver";
> +			gpios = <&gpio1 0 1>;
> +			init-state = <0>;
> +			gpio-shared;
> +		};
> +	};
> +	...
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index e03653d..17f2f4f 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -514,4 +514,13 @@ config GPIO_TPS65910
>  	help
>  	  Select this option to enable GPIO driver for the TPS65910
>  	  chip family.
> +
> +comment "Generic GPIO switch"
> +
> +config GENERIC_GPIO_SWITCH
> +       tristate "Generic GPIO switch"
> +       help
> +         Provide a generic GPIO interface for drivers that require some
> +	 external logic for the device they serve to operate.
> +
>  endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 007f54b..b31f41a 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -64,3 +64,6 @@ obj-$(CONFIG_GPIO_WM831X)	+= gpio-wm831x.o
>  obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
>  obj-$(CONFIG_GPIO_WM8994)	+= gpio-wm8994.o
>  obj-$(CONFIG_GPIO_XILINX)	+= gpio-xilinx.o
> +
> +# Not a GPIO HW driver
> +obj-$(CONFIG_GENERIC_GPIO_SWITCH)	+= gpio-switch.o
> diff --git a/drivers/gpio/gpio-switch.c b/drivers/gpio/gpio-switch.c
> new file mode 100644
> index 0000000..ea0c390
> --- /dev/null
> +++ b/drivers/gpio/gpio-switch.c
> @@ -0,0 +1,389 @@
> +/*
> + * drivers/gpio/gpio-switch.c
> + *
> + * Copyright (C) 2012  Lothar Wassmann <LW at KARO-electronics.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Provide a generic interface for drivers that require to switch some
> + * external hardware such as transceivers, power enable or reset pins
> + * for the device they manage to work.
> + *
> + * Allows multiple devices to share a common switch.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/list.h>
> +#include <linux/err.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/gpio-switch.h>
> +
> +static LIST_HEAD(gpio_switch_list);
> +static DEFINE_MUTEX(gpio_switch_list_lock);
> +static int gpio_switch_index;
> +
> +struct gpio_sw {
> +	struct list_head list;
> +	struct device *parent;
> +	int id;
> +	const char *label;
> +	int gpio;
> +	unsigned flags;
> +	int use_count;
> +	int enable_count;
> +	unsigned state:1;
> +};
> +
> +/* Helper functions; must be called with 'gpio_switch_list_lock' held */
> +static struct gpio_sw *gpio_switch_find_gpio(struct device *parent,
> +					int gpio)
> +{
> +	struct gpio_sw *sw;
> +
> +	list_for_each_entry(sw, &gpio_switch_list, list) {
> +		if (gpio_is_valid(gpio) && sw->gpio != gpio)
> +			continue;
> +		return sw;
> +	}
> +	return NULL;
> +}
> +
> +static struct gpio_sw *gpio_switch_find_by_phandle(struct device *parent,
> +					phandle ph)
> +{
> +	struct gpio_sw *sw;
> +	struct device_node *dp;
> +
> +	dp = of_find_node_by_phandle(ph);
> +	if (dp == NULL)
> +		return NULL;
> +
> +	list_for_each_entry(sw, &gpio_switch_list, list) {
> +		if (sw->parent && sw->parent->of_node == dp)
> +			return sw;
> +	}
> +	return NULL;
> +}
> +
> +static struct gpio_sw *gpio_switch_find_by_id(struct device *parent,
> +					int id)
> +{
> +	struct gpio_sw *sw;
> +
> +	list_for_each_entry(sw, &gpio_switch_list, list) {
> +		if (sw->parent && to_platform_device(sw->parent)->id == id)
> +			return sw;
> +	}
> +	return NULL;
> +}
> +
> +static void gpio_switch_delete(struct gpio_sw *sw)
> +{
> +	list_del_init(&sw->list);
> +	if (!(sw->flags & GPIO_SW_SHARED) ||
> +	    !gpio_switch_find_gpio(sw->parent, sw->gpio))
> +		gpio_free(sw->gpio);
> +}
> +
> +/* GPIO accessor */
> +static void gpio_switch_set_value(struct gpio_sw *sw, int on)
> +{
> +	gpio_set_value(sw->gpio, !on ^ !(sw->flags & GPIO_SW_ACTIVE_LOW));
> +}
> +
> +/* Provider API */
> +int gpio_switch_register(struct device *parent, const char *id, int gpio,
> +			 enum gpio_sw_flags flags)
> +{
> +	int ret;
> +	struct platform_device *pdev;
> +	struct gpio_sw_platform_data *pdata;
> +
> +	if (!gpio_is_valid(gpio)) {
> +		dev_err(parent, "Invalid GPIO %u\n", gpio);
> +		return -EINVAL;
> +	}
> +
> +	pdata = devm_kzalloc(parent, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	pdata->gpio = gpio;
> +	pdata->flags = flags;
> +
> +	mutex_lock(&gpio_switch_list_lock);
> +	pdev = platform_device_alloc("gpio-switch", gpio_switch_index++);
> +	mutex_unlock(&gpio_switch_list_lock);
> +	if (pdev == NULL)
> +		return -ENOMEM;
> +
> +	pdev->dev.parent = parent;
> +	pdev->dev.platform_data = pdata;
> +
> +	ret = platform_device_add(pdev);
> +	if (ret)
> +		goto pdev_free;
> +
> +	return 0;
> +
> + pdev_free:
> +	platform_device_put(pdev);
> +	return ret;
> +}
> +EXPORT_SYMBOL(gpio_switch_register);
> +
> +int gpio_switch_unregister(struct gpio_sw *sw)
> +{
> +	int ret = -EINVAL;
> +	struct gpio_sw *ptr;
> +
> +	mutex_lock(&gpio_switch_list_lock);
> +	list_for_each_entry(ptr, &gpio_switch_list, list) {
> +		if (sw == ptr) {
> +			gpio_switch_delete(sw);
> +			ret = 0;
> +			break;
> +		}
> +	}
> +	mutex_unlock(&gpio_switch_list_lock);
> +	return ret;
> +}
> +EXPORT_SYMBOL(gpio_switch_unregister);
> +
> +/* Consumer API */
> +struct gpio_sw *request_gpio_switch(struct device *dev, u32 id)
> +{
> +	struct gpio_sw *sw;
> +	struct device_node *np = dev->of_node;
> +
> +	mutex_lock(&gpio_switch_list_lock);
> +	if (np)
> +		sw = gpio_switch_find_by_phandle(dev, id);
> +	else
> +		sw = gpio_switch_find_by_id(dev, id);
> +
> +	if (sw)
> +		sw->use_count++;
> +	mutex_unlock(&gpio_switch_list_lock);
> +
> +	if (sw)
> +		dev_dbg(dev, "Found gpio-switch %p\n", sw);
> +	else
> +		dev_dbg(dev, "No gpio found for ID %08x\n", id);
> +
> +	return sw;
> +}
> +EXPORT_SYMBOL(request_gpio_switch);
> +
> +void free_gpio_switch(struct gpio_sw *sw)
> +{
> +	if (!sw)
> +		return;
> +
> +	mutex_lock(&gpio_switch_list_lock);
> +	sw->use_count--;
> +	mutex_unlock(&gpio_switch_list_lock);
> +}
> +EXPORT_SYMBOL(free_gpio_switch);
> +
> +void __gpio_switch_set(struct gpio_sw *sw, int on)
> +{
> +	if (!(sw->flags & GPIO_SW_SHARED))
> +		gpio_switch_set_value(sw, on);
> +	else
> +		if ((on && (sw->enable_count++ == 0)) ||
> +			(!on && (--sw->enable_count == 0))) {
> +			WARN_ON(sw->enable_count < 0);
> +			gpio_switch_set_value(sw, on);
> +		}
> +}
> +EXPORT_SYMBOL(__gpio_switch_set);
> +
> +void gpio_switch_set_suspend_state(struct gpio_sw *sw, int suspend_state)
> +{
> +	switch (suspend_state) {
> +	case 0:
> +		sw->flags |= GPIO_SW_SUSPEND_OFF;
> +		break;
> +
> +	case 1:
> +		sw->flags |= GPIO_SW_SUSPEND_ON;
> +		break;
> +
> +	default:
> +		sw->flags &= ~(GPIO_SW_SUSPEND_ON | GPIO_SW_SUSPEND_OFF);
> +	}
> +}
> +EXPORT_SYMBOL(gpio_switch_set_suspend_state);
> +
> +void gpio_switch_set_resume_state(struct gpio_sw *sw, int resume_state)
> +{
> +	switch (resume_state) {
> +	case 0:
> +		sw->flags |= GPIO_SW_RESUME_OFF;
> +		break;
> +
> +	case 1:
> +		sw->flags |= GPIO_SW_RESUME_ON;
> +		break;
> +
> +	default:
> +		sw->flags &= ~(GPIO_SW_RESUME_ON | GPIO_SW_RESUME_OFF);
> +	}
> +}
> +EXPORT_SYMBOL(gpio_switch_set_resume_state);
> +
> +/* Driver boilerplate */
> +static int __devinit gpio_switch_platform_probe(struct platform_device *pdev,
> +						struct gpio_sw *sw)
> +{
> +	struct gpio_sw_platform_data *pdata = pdev->dev.platform_data;
> +
> +	sw->gpio = pdata->gpio;
> +	if (!gpio_is_valid(sw->gpio))
> +		return -EINVAL;
> +
> +	sw->flags = pdata->flags;
> +	sw->label = pdata->label;
> +	if (pdata->init_state) {
> +		if (pdata->init_state == GPIO_SW_INIT_ACTIVE)
> +			sw->enable_count++;
> +	}
> +	return 0;
> +}
> +
> +static int __devinit gpio_switch_dt_probe(struct platform_device *pdev,
> +					  struct gpio_sw *sw)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	int gpio;
> +	enum of_gpio_flags gpio_flags;
> +	const u32 *prop;
> +
> +	of_property_read_string(np, "label", &sw->label);
> +
> +	gpio = of_get_named_gpio_flags(np, "gpios", 0, &gpio_flags);
> +	if (!gpio_is_valid(gpio)) {
> +		dev_err(&pdev->dev, "No valid GPIO specified for '%s'\n",
> +			sw->label ?: "unknown");
> +		return -EINVAL;
> +	}
> +
> +	sw->gpio = gpio;
> +	if (gpio_flags & OF_GPIO_ACTIVE_LOW)
> +		sw->flags |= GPIO_SW_ACTIVE_LOW;
> +
> +	if (of_get_property(np, "shared-gpio", NULL))
> +		sw->flags |= GPIO_SW_SHARED;
> +
> +	prop = of_get_property(np, "suspend-state", NULL);
> +	if (prop)
> +		gpio_switch_set_suspend_state(sw, *prop);
> +
> +	prop = of_get_property(np, "resume-state", NULL);
> +	if (prop)
> +		gpio_switch_set_resume_state(sw, *prop);
> +
> +	prop = of_get_property(np, "init-state", NULL);
> +	if (prop) {
> +		if (*prop)
> +			sw->enable_count++;
> +	}
> +	return 0;
> +}
> +
> +static int __devinit gpio_switch_probe(struct platform_device *pdev)
> +{
> +	int ret;
> +	struct gpio_sw_platform_data *pdata = pdev->dev.platform_data;
> +	struct gpio_sw *sw;
> +
> +	sw = devm_kzalloc(&pdev->dev, sizeof(*sw), GFP_KERNEL);
> +	if (!sw)
> +		return -ENOMEM;
> +
> +	if (pdata)
> +		ret = gpio_switch_platform_probe(pdev, sw);
> +	else
> +		ret = gpio_switch_dt_probe(pdev, sw);
> +	if (ret)
> +		return ret;
> +
> +	INIT_LIST_HEAD(&sw->list);
> +	sw->parent = &pdev->dev;
> +
> +	if (!(sw->flags & GPIO_SW_SHARED) ||
> +	    !gpio_switch_find_gpio(sw->parent, sw->gpio)) {
> +		ret = gpio_request(sw->gpio, sw->label);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Failed to request GPIO%d '%s'\n",
> +				sw->gpio, sw->label);
> +			return ret;
> +		}
> +		gpio_direction_output(sw->gpio, !!sw->enable_count ^
> +				!(sw->flags & GPIO_SW_ACTIVE_LOW));
> +	}
> +	platform_set_drvdata(pdev, sw);
> +
> +	mutex_lock(&gpio_switch_list_lock);
> +	list_add(&sw->list, &gpio_switch_list);
> +	mutex_unlock(&gpio_switch_list_lock);
> +
> +	dev_info(&pdev->dev, "GPIO%u registered for '%s'\n",
> +		sw->gpio, sw->label ?: "unknown");
> +	return 0;
> +}
> +
> +static int __devexit gpio_switch_remove(struct platform_device *pdev)
> +{
> +	struct gpio_sw *sw, *tmp;
> +
> +	list_for_each_entry_safe(sw, tmp, &gpio_switch_list, list) {
> +		gpio_switch_unregister(sw);
> +	}
> +	return 0;
> +}
> +
> +static struct of_device_id gpio_switch_dt_ids[] = {
> +	{ .compatible = "linux,gpio-switch", },
> +	{ /* sentinel */ }
> +};
> +
> +struct platform_driver gpio_switch_driver = {
> +	.driver = {
> +		.name = "gpio-switch",
> +		.owner = THIS_MODULE,
> +		.of_match_table = gpio_switch_dt_ids,
> +	},
> +	.probe = gpio_switch_probe,
> +	.remove = __devexit_p(gpio_switch_remove),
> +};
> +
> +static int __init gpio_switch_init(void)
> +{
> +	return platform_driver_register(&gpio_switch_driver);
> +}
> +arch_initcall(gpio_switch_init);
> +
> +static void __exit gpio_switch_exit(void)
> +{
> +	platform_driver_unregister(&gpio_switch_driver);
> +}
> +module_exit(gpio_switch_exit);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Lother Wa?mann <LW at KARO-electronics.de>");
> +MODULE_DESCRIPTION("Generic GPIO switch driver");
> +MODULE_ALIAS("platform:gpio_switch");
> diff --git a/include/linux/gpio-switch.h b/include/linux/gpio-switch.h
> new file mode 100644
> index 0000000..23893ab
> --- /dev/null
> +++ b/include/linux/gpio-switch.h
> @@ -0,0 +1,47 @@
> +#ifndef LINUX_GPIO_SWITCH_H
> +#define LINUX_GPIO_SWITCH_H
> +
> +enum gpio_sw_flags {
> +	GPIO_SW_ACTIVE_LOW	= (1 << 0),
> +	GPIO_SW_SHARED		= (1 << 1),
> +	GPIO_SW_SUSPEND_ON	= (1 << 2),
> +	GPIO_SW_SUSPEND_OFF	= (1 << 3),
> +	GPIO_SW_RESUME_ON	= (1 << 4),
> +	GPIO_SW_RESUME_OFF	= (1 << 5),
> +};
> +
> +enum gpio_sw_initstate {
> +	GPIO_SW_INIT_NONE,
> +	GPIO_SW_INIT_ACTIVE,
> +	GPIO_SW_INIT_INACTIVE,
> +};
> +
> +struct gpio_sw_platform_data {
> +	const char *label;
> +	int gpio;
> +	enum gpio_sw_flags flags;
> +	int init_state;
> +};
> +
> +struct gpio_sw;
> +
> +extern int gpio_switch_register(struct device *parent, const char *id, int gpio,
> +			 enum gpio_sw_flags flags);
> +
> +extern int gpio_switch_unregister(struct gpio_sw *sw);
> +extern struct gpio_sw *request_gpio_switch(struct device *dev, u32 id);
> +extern void free_gpio_switch(struct gpio_sw *sw);
> +extern void __gpio_switch_set(struct gpio_sw *sw, int on);
> +
> +static inline void gpio_switch_set(struct gpio_sw *sw, int on)
> +{
> +	if (!sw)
> +		return;
> +
> +	__gpio_switch_set(sw, on);
> +}
> +
> +extern void gpio_switch_set_suspend_state(struct gpio_sw *sw, int suspend_state);
> +extern void gpio_switch_set_resume_state(struct gpio_sw *sw, int resume_state);
> +
> +#endif
> 


-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From lee.jones at linaro.org  Mon Aug  6 08:32:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 13:32:03 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between DT and
 non-DT boots
Message-ID: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>

If we're booting with Device Tree enabled, we want the IRQ numbers to
be taken and translated from the Device Tree binary. If not, they
should be taken from the resource allocation defined in the AB8500 MFD
core driver.

Tested-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/input/misc/ab8500-ponkey.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
index 1a1d974..afcd87f 100644
--- a/drivers/input/misc/ab8500-ponkey.c
+++ b/drivers/input/misc/ab8500-ponkey.c
@@ -47,6 +47,7 @@ static irqreturn_t ab8500_ponkey_handler(int irq, void *data)
 static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 {
 	struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
+	struct device_node *np = pdev->dev.of_node;
 	struct ab8500_ponkey *ponkey;
 	struct input_dev *input;
 	int irq_dbf, irq_dbr;
@@ -73,8 +74,9 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 
 	ponkey->idev = input;
 	ponkey->ab8500 = ab8500;
-	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
-	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
+
+	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
+	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
 
 	input->name = "AB8500 POn(PowerOn) Key";
 	input->dev.parent = &pdev->dev;
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 08:36:23 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 13:36:23 +0100
Subject: [PATCH 6/6] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
Message-ID: <20120806123622.GA10524@gmail.com>

On Mon, Aug 06, 2012 at 11:46:42AM +0100, Lee Jones wrote:
> If we're booting with Device Tree enabled, we want the IRQ numbers to
> be taken and translated from the Device Tree binary. If not, they
> should be taken from the resource allocation defined in the AB8500 MFD
> core driver.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/input/misc/ab8500-ponkey.c |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Revoked, sent elsewhere.


From t.stanislaws at samsung.com  Mon Aug  6 08:42:28 2012
From: t.stanislaws at samsung.com (Tomasz Stanislawski)
Date: Mon, 06 Aug 2012 14:42:28 +0200
Subject: [PATCH 2/2] dma-buf: add helpers for attacher dma-parms
In-Reply-To: <xa1tobmoxmdz.fsf@mina86.com>
References: <1342715014-5316-1-git-send-email-rob.clark@linaro.org>
 <1342715014-5316-3-git-send-email-rob.clark@linaro.org>
 <501F9C8E.4080002@samsung.com> <xa1tobmoxmdz.fsf@mina86.com>
Message-ID: <501FBBB4.6000109@samsung.com>

On 08/06/2012 01:58 PM, Michal Nazarewicz wrote:
> 
> Tomasz Stanislawski <t.stanislaws at samsung.com> writes:
>> I recommend to change the semantics for unlimited number of segments
>> from 'value 0' to:
>>
>> #define DMA_SEGMENTS_COUNT_UNLIMITED ((unsigned long)INT_MAX)

Sorry. It should be:
#define DMA_SEGMENTS_COUNT_UNLIMITED ((unsigned int)INT_MAX)

>>
>> Using INT_MAX will allow using safe conversions between signed and
>> unsigned integers.
> 
> LONG_MAX seems cleaner regardless.
> 
> 
> 



From pieterg at gmx.com  Mon Aug  6 08:55:43 2012
From: pieterg at gmx.com (pieterg at gmx.com)
Date: Mon,  6 Aug 2012 14:55:43 +0200
Subject: [PATCH] pxafb: fix BLW / ELW smart panel timing parameters
Message-ID: <1344257743-25692-1-git-send-email-pieterg@gmx.com>

From: Pieter Grimmerink <p.grimmerink at inepro.com>

The parameters were swapped;
LCCR1[BLW] configures rd_pulse_width and wr_pulse_width
LCCR1[ELW] configures a0csrd_set_hld and a0cswr_set_hld
---
 drivers/video/pxafb.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 3f90255..04c395a 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -1230,18 +1230,18 @@ static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
 static void setup_smart_timing(struct pxafb_info *fbi,
 				struct fb_var_screeninfo *var)
 {
 	struct pxafb_mach_info *inf = fbi->dev->platform_data;
 	struct pxafb_mode_info *mode = &inf->modes[0];
 	unsigned long lclk = clk_get_rate(fbi->clk);
 	unsigned t1, t2, t3, t4;
 
-	t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
-	t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
+	t1 = max(mode->rd_pulse_width, mode->wr_pulse_width);
+	t2 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
 	t3 = mode->op_hold_time;
 	t4 = mode->cmd_inh_time;
 
 	fbi->reg_lccr1 =
 		LCCR1_DisWdth(var->xres) |
 		LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
 		LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
 		LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
-- 
1.7.9.5



From pieterg at gmx.com  Mon Aug  6 08:56:18 2012
From: pieterg at gmx.com (pieterg at gmx.com)
Date: Mon,  6 Aug 2012 14:56:18 +0200
Subject: [PATCH] pxafb: allow zero for smart panel timings
Message-ID: <1344257778-25737-1-git-send-email-pieterg@gmx.com>

From: Pieter Grimmerink <p.grimmerink at inepro.com>

The LCCR1[BLW] description states:
"For LCD panels with an internal frame buffer, BLW
specifies the pulse width of the Write or Read signal
(...) which is equal to (BLW+1)*LCD_CLK_PERIOD"

And the LCD Smart Panel Timing Specifications states:
"L_PCLK_WR pulse width duration:
Min: 1
Typical: LCCR1[BLW] + 1
Max: 256
Units: LCLK"

The BLW field has a value range of 0 to 255, resulting in
a write or read pulse width range of
1*LCD_CLK_PERIOD..256*LCD_CLK_PERIOD

So LCCR1[BLW] = 0 is a valid configuration.
The same is the case for LCCR1[ELW] and LCCR3[PCD],
the other two smart panel timing values.
---
 drivers/video/pxafb.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 04c395a..7ea5e23 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -1223,8 +1223,7 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
 
 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
 {
-	unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
-	return (t == 0) ? 1 : t;
+	return time_ns * (lcd_clk / 1000000) / 1000;
 }
 
 static void setup_smart_timing(struct pxafb_info *fbi,
-- 
1.7.9.5



From gcembed at gmail.com  Mon Aug  6 09:07:27 2012
From: gcembed at gmail.com (=?UTF-8?q?Ga=C3=ABtan=20Carlier?=)
Date: Mon,  6 Aug 2012 15:07:27 +0200
Subject: [PATCH 1/1] mx27_3ds: Add sound support
Message-ID: <1344258447-6162-1-git-send-email-gcembed@gmail.com>

Hi,
I have ported code "Enable sound on mx31_3ds" from Philippe R?tornaz to
MX27 3DS platform on master branch of linux-next (tag next-20120806).
I also applied patch "dma: imx-dma: Fix kernel crash due to missing clock
conversion" of Fabio Estevam which is not yet merged in linux-next.
Thanks to them, everything is working good on MX27 3DS platform except that
sound is played too fast.
Which parameter must be adjusted to have sound playing at normal speed ?
In mc13783 codec driver, imx_add_imx_ssi(), clock configuration in
mach-mx27_3ds file ?

Thanks for your help.

Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
---
 arch/arm/mach-imx/Kconfig         |    1 +
 arch/arm/mach-imx/mach-mx27_3ds.c |   19 ++++++++++++++++++-
 2 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..63f64f1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -302,6 +302,7 @@ config MACH_MX27_3DS
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMX_FB
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_SSI
 	select IMX_HAVE_PLATFORM_IMX_KEYPAD
 	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MX2_CAMERA
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 58c24c1..a5d4080 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -158,6 +158,11 @@ static const int mx27pdk_pins[] __initconst = {
 	PB21_PF_CSI_HSYNC,
 	CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
 	CSI_RESET | GPIO_GPIO | GPIO_OUT,
+	/* SSI */
+	PC16_PF_SSI4_FS,
+	PC17_PF_SSI4_RXD,
+	PC18_PF_SSI4_TXD,
+	PC19_PF_SSI4_CLK,
 };
 
 static struct gpio mx27_3ds_camera_gpios[] = {
@@ -329,13 +334,23 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
 };
 
 /* MC13783 */
+static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
+	.dac_ssi_port = MC13783_SSI1_PORT,
+	.adc_ssi_port = MC13783_SSI1_PORT,
+};
+
 static struct mc13xxx_platform_data mc13783_pdata = {
 	.regulators = {
 		.regulators = mx27_3ds_regulators,
 		.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
 
 	},
-	.flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
+	.codec = &mx27_3ds_codec,
+	.flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
+};
+
+static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
+		.flags = IMX_SSI_DMA | IMX_SSI_NET,
 };
 
 /* SPI */
@@ -512,6 +527,8 @@ static void __init mx27pdk_init(void)
 	}
 
 	imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
+	imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
+	imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
 }
 
 static void __init mx27pdk_timer_init(void)
-- 
1.7.7.4



From kishon at ti.com  Mon Aug  6 09:07:53 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:53 +0530
Subject: [PATCH v7 0/7] omap: musb: Add device tree support
Message-ID: <1344258480-4304-1-git-send-email-kishon@ti.com>

This patch series adds device tree support for MUSB and device
tree support for all the related modules to get MUSB working in
OMAP platform.

A new omap-usb2 phy driver has been added (with only dt suppport)
to perform phy configurations. Previously this configuration was
performed by twl6030, using pdata function pointers.

With the addition of omap-usb2 to perform phy configurations,
twl6030 is made as a comparator driver to detect VBUS and ID events
and notify it to the glue layer.

musb core is _NOT_ yet converted to support device tree support as it
would need lot of driver re-design because of its enormous use of
function pointers. That will be in _TO DO_ list.

Changes from v6:
* Removed the dt data part of the patch series. It'll be sent as a
separate series.
* Replaced arch initcall in omap-usb2 phy driver with a module
platform driver. Dependent drivers should use -EPROBE_DEFER. 

Changes from v5:
minor cleanups like checking for return value in get_sync and few changes
in the documentation has been done.

Changes from v4:
duplicate getting of 'mode' property is removed in omap-musb glue.

Changes from v3:
remove the address in the node name of usb_otg_hs since the usb_otg_hs
node doesn't have a reg property. Thanks Ajay Gupta for finding this.

Changes from v2:
Fixed Sergei's comment to remove *0x* prefix in usb2phy at 0x4a0ad080

Changes from v1:
* Fixed Rajendra Nayak comments (regulator naming, compatible naming of
musb and other minor cleanups.)
* It's agreed to have ocp2scp in drivers/bus and usb2 phy is a child of
ocp2scp, the documentation is updated accordingly.

Changes from RFC:
Removed the dependency on [RFC PATCH 00/11] OMAP System Control Module.
Writing to control module register is now handled in otg driver itself.
Once the system control module driver get upstreamed, I'll send a patch
to make use of API's in control module driver to write to control
module register.

This series was developed on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git xceiv

This patch series depends on
[PATCH v3 0/2] omap: add ocp2scp as a bus driver

Performed MUSB device mode testing on OMAP4 panda, OMAP4 SDP
and OMAP3 beagle.

Kishon Vijay Abraham I (7):
  drivers: usb: phy: add a new driver for omap usb2 phy
  arm: omap: hwmod: add a new addr space in otg for writing to control
    module
  drivers: usb: otg: make twl6030_usb as a comparator driver to
    omap_usb2
  drivers: usb: twl6030: Add dt support for twl6030 usb
  drivers: usb: twl4030: Add device tree support for twl4030 usb
  drivers: usb: musb: Add device tree support for omap musb glue
  arm: omap: phy: remove unused functions from omap-phy-internal.c

 .../devicetree/bindings/bus/omap-ocp2scp.txt       |    3 +
 Documentation/devicetree/bindings/usb/omap-usb.txt |   49 ++++
 .../devicetree/bindings/usb/twlxxxx-usb.txt        |   40 +++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    5 +
 arch/arm/mach-omap2/omap_phy_internal.c            |  138 ----------
 arch/arm/mach-omap2/twl-common.c                   |    5 -
 arch/arm/mach-omap2/usb-musb.c                     |    3 -
 drivers/usb/musb/omap2430.c                        |  106 +++++++-
 drivers/usb/musb/omap2430.h                        |    9 +
 drivers/usb/otg/twl4030-usb.c                      |   26 +-
 drivers/usb/otg/twl6030-usb.c                      |  157 ++++--------
 drivers/usb/phy/Kconfig                            |   10 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/omap-usb2.c                        |  271 ++++++++++++++++++++
 include/linux/usb/omap_usb.h                       |   46 ++++
 include/linux/usb/phy_companion.h                  |   34 +++
 16 files changed, 631 insertions(+), 272 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/omap-usb.txt
 create mode 100644 Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
 create mode 100644 drivers/usb/phy/omap-usb2.c
 create mode 100644 include/linux/usb/omap_usb.h
 create mode 100644 include/linux/usb/phy_companion.h

-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:55 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:55 +0530
Subject: [PATCH v7 2/7] arm: omap: hwmod: add a new addr space in otg for
 writing to control module
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-3-git-send-email-kishon@ti.com>

The mailbox register for usb otg in omap is present in control module.
On detection of any events VBUS or ID, this register should be written
to send the notification to musb core.

Till we have a separate control module driver to write to control module,
omap2430 will handle the register writes to control module by itself. So
a new address space to represent this control module register is added
to usb_otg_hs.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e8e5405..6334e22 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -5885,6 +5885,11 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
 		.pa_end		= 0x4a0ab003,
 		.flags		= ADDR_TYPE_RT
 	},
+	{
+		.pa_start	= 0x4a00233c,
+		.pa_end		= 0x4a00233f,
+		.flags		= ADDR_TYPE_RT
+	},
 	{ }
 };
 
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:56 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:56 +0530
Subject: [PATCH v7 3/7] drivers: usb: otg: make twl6030_usb as a comparator
 driver to omap_usb2
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-4-git-send-email-kishon@ti.com>

All the PHY configuration other than VBUS, ID GND and OTG SRP are removed
from twl6030. The phy configurations are taken care by the dedicated
usb2 phy driver. So twl6030 is made as comparator driver for VBUS and
ID detection.

Writing to control module which is now handled in omap2430.c should be
removed once a driver for control module is in place.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 drivers/usb/musb/omap2430.c   |   52 +++++++++++++++---
 drivers/usb/musb/omap2430.h   |    9 ++++
 drivers/usb/otg/twl6030-usb.c |  118 +++++++----------------------------------
 3 files changed, 72 insertions(+), 107 deletions(-)

diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 392fc7a..74dbd6f 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -44,6 +44,7 @@ struct omap2430_glue {
 	struct platform_device	*musb;
 	enum omap_musb_vbus_id_status status;
 	struct work_struct	omap_musb_mailbox_work;
+	u32 __iomem		*control_otghs;
 };
 #define glue_to_musb(g)		platform_get_drvdata(g->musb)
 
@@ -51,6 +52,26 @@ struct omap2430_glue		*_glue;
 
 static struct timer_list musb_idle_timer;
 
+/**
+ * omap4_usb_phy_mailbox - write to usb otg mailbox
+ * @glue: struct omap2430_glue *
+ * @val: the value to be written to the mailbox
+ *
+ * On detection of a device (ID pin is grounded), this API should be called
+ * to set AVALID, VBUSVALID and ID pin is grounded.
+ *
+ * When OMAP is connected to a host (OMAP in device mode), this API
+ * is called to set AVALID, VBUSVALID and ID pin in high impedance.
+ *
+ * XXX: This function will be removed once we have a seperate driver for
+ * control module
+ */
+static void omap4_usb_phy_mailbox(struct omap2430_glue *glue, u32 val)
+{
+	if (glue->control_otghs)
+		writel(val, glue->control_otghs);
+}
+
 static void musb_do_idle(unsigned long _musb)
 {
 	struct musb	*musb = (void *)_musb;
@@ -245,6 +266,7 @@ EXPORT_SYMBOL_GPL(omap_musb_mailbox);
 
 static void omap_musb_set_mailbox(struct omap2430_glue *glue)
 {
+	u32 val;
 	struct musb *musb = glue_to_musb(glue);
 	struct device *dev = musb->controller;
 	struct musb_hdrc_platform_data *pdata = dev->platform_data;
@@ -260,7 +282,8 @@ static void omap_musb_set_mailbox(struct omap2430_glue *glue)
 		musb->xceiv->last_event = USB_EVENT_ID;
 		if (!is_otg_enabled(musb) || musb->gadget_driver) {
 			pm_runtime_get_sync(dev);
-			usb_phy_init(musb->xceiv);
+			val = AVALID | VBUSVALID;
+			omap4_usb_phy_mailbox(glue, val);
 			omap2430_musb_set_vbus(musb, 1);
 		}
 		break;
@@ -273,7 +296,8 @@ static void omap_musb_set_mailbox(struct omap2430_glue *glue)
 		musb->xceiv->last_event = USB_EVENT_VBUS;
 		if (musb->gadget_driver)
 			pm_runtime_get_sync(dev);
-		usb_phy_init(musb->xceiv);
+		val = IDDIG | AVALID | VBUSVALID;
+		omap4_usb_phy_mailbox(glue, val);
 		break;
 
 	case OMAP_MUSB_ID_FLOAT:
@@ -291,7 +315,8 @@ static void omap_musb_set_mailbox(struct omap2430_glue *glue)
 			if (musb->xceiv->otg->set_vbus)
 				otg_set_vbus(musb->xceiv->otg, 0);
 		}
-		usb_phy_shutdown(musb->xceiv);
+		val = SESSEND | IDDIG;
+		omap4_usb_phy_mailbox(glue, val);
 		break;
 	default:
 		dev_dbg(dev, "ID float\n");
@@ -366,6 +391,7 @@ err1:
 static void omap2430_musb_enable(struct musb *musb)
 {
 	u8		devctl;
+	u32		val;
 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 	struct device *dev = musb->controller;
 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
@@ -375,7 +401,8 @@ static void omap2430_musb_enable(struct musb *musb)
 	switch (glue->status) {
 
 	case OMAP_MUSB_ID_GROUND:
-		usb_phy_init(musb->xceiv);
+		val = AVALID | VBUSVALID;
+		omap4_usb_phy_mailbox(glue, val);
 		if (data->interface_type != MUSB_INTERFACE_UTMI)
 			break;
 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
@@ -394,7 +421,8 @@ static void omap2430_musb_enable(struct musb *musb)
 		break;
 
 	case OMAP_MUSB_VBUS_VALID:
-		usb_phy_init(musb->xceiv);
+		val = IDDIG | AVALID | VBUSVALID;
+		omap4_usb_phy_mailbox(glue, val);
 		break;
 
 	default:
@@ -404,11 +432,14 @@ static void omap2430_musb_enable(struct musb *musb)
 
 static void omap2430_musb_disable(struct musb *musb)
 {
+	u32 val;
 	struct device *dev = musb->controller;
 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
 
-	if (glue->status != OMAP_MUSB_UNKNOWN)
-		usb_phy_shutdown(musb->xceiv);
+	if (glue->status != OMAP_MUSB_UNKNOWN) {
+		val = SESSEND | IDDIG;
+		omap4_usb_phy_mailbox(glue, val);
+	}
 }
 
 static int omap2430_musb_exit(struct musb *musb)
@@ -440,6 +471,7 @@ static int __devinit omap2430_probe(struct platform_device *pdev)
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
 	struct platform_device		*musb;
 	struct omap2430_glue		*glue;
+	struct resource			*res;
 	int				ret = -ENOMEM;
 
 	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
@@ -462,6 +494,12 @@ static int __devinit omap2430_probe(struct platform_device *pdev)
 	glue->musb			= musb;
 	glue->status			= OMAP_MUSB_UNKNOWN;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	glue->control_otghs = devm_request_and_ioremap(&pdev->dev, res);
+	if (glue->control_otghs == NULL)
+		dev_dbg(&pdev->dev, "Failed to obtain control memory\n");
+
 	pdata->platform_ops		= &omap2430_ops;
 
 	platform_set_drvdata(pdev, glue);
diff --git a/drivers/usb/musb/omap2430.h b/drivers/usb/musb/omap2430.h
index 40b3c02..b85f397 100644
--- a/drivers/usb/musb/omap2430.h
+++ b/drivers/usb/musb/omap2430.h
@@ -49,4 +49,13 @@
 #define OTG_FORCESTDBY		0x414
 #	define	ENABLEFORCE		(1 << 0)
 
+/*
+ * Control Module bit definitions
+ * XXX: Will be removed once we have a driver for control module.
+ */
+#define	AVALID				BIT(0)
+#define	BVALID				BIT(1)
+#define	VBUSVALID			BIT(2)
+#define	SESSEND				BIT(3)
+#define	IDDIG				BIT(4)
 #endif	/* __MUSB_OMAP243X_H__ */
diff --git a/drivers/usb/otg/twl6030-usb.c b/drivers/usb/otg/twl6030-usb.c
index 6907d8d..32525bb 100644
--- a/drivers/usb/otg/twl6030-usb.c
+++ b/drivers/usb/otg/twl6030-usb.c
@@ -25,8 +25,9 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/usb/otg.h>
 #include <linux/usb/musb-omap.h>
+#include <linux/usb/phy_companion.h>
+#include <linux/usb/omap_usb.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/consumer.h>
 #include <linux/err.h>
@@ -87,7 +88,7 @@
 #define	VBUS_DET			BIT(2)
 
 struct twl6030_usb {
-	struct usb_phy		phy;
+	struct phy_companion	comparator;
 	struct device		*dev;
 
 	/* for vbus reporting with irqs disabled */
@@ -107,7 +108,7 @@ struct twl6030_usb {
 	unsigned long		features;
 };
 
-#define phy_to_twl(x)		container_of((x), struct twl6030_usb, phy)
+#define	comparator_to_twl(x) container_of((x), struct twl6030_usb, comparator)
 
 /*-------------------------------------------------------------------------*/
 
@@ -137,50 +138,9 @@ static inline u8 twl6030_readb(struct twl6030_usb *twl, u8 module, u8 address)
 	return ret;
 }
 
-static int twl6030_phy_init(struct usb_phy *x)
+static int twl6030_start_srp(struct phy_companion *comparator)
 {
-	struct twl6030_usb *twl;
-	struct device *dev;
-	struct twl4030_usb_data *pdata;
-
-	twl = phy_to_twl(x);
-	dev  = twl->dev;
-	pdata = dev->platform_data;
-
-	if (twl->linkstat == OMAP_MUSB_ID_GROUND)
-		pdata->phy_power(twl->dev, 1, 1);
-	else
-		pdata->phy_power(twl->dev, 0, 1);
-
-	return 0;
-}
-
-static void twl6030_phy_shutdown(struct usb_phy *x)
-{
-	struct twl6030_usb *twl;
-	struct device *dev;
-	struct twl4030_usb_data *pdata;
-
-	twl = phy_to_twl(x);
-	dev  = twl->dev;
-	pdata = dev->platform_data;
-	pdata->phy_power(twl->dev, 0, 0);
-}
-
-static int twl6030_phy_suspend(struct usb_phy *x, int suspend)
-{
-	struct twl6030_usb *twl = phy_to_twl(x);
-	struct device *dev = twl->dev;
-	struct twl4030_usb_data *pdata = dev->platform_data;
-
-	pdata->phy_suspend(dev, suspend);
-
-	return 0;
-}
-
-static int twl6030_start_srp(struct usb_otg *otg)
-{
-	struct twl6030_usb *twl = phy_to_twl(otg->phy);
+	struct twl6030_usb *twl = comparator_to_twl(comparator);
 
 	twl6030_writeb(twl, TWL_MODULE_USB, 0x24, USB_VBUS_CTRL_SET);
 	twl6030_writeb(twl, TWL_MODULE_USB, 0x84, USB_VBUS_CTRL_SET);
@@ -313,23 +273,8 @@ static irqreturn_t twl6030_usbotg_irq(int irq, void *_twl)
 	return IRQ_HANDLED;
 }
 
-static int twl6030_set_peripheral(struct usb_otg *otg,
-		struct usb_gadget *gadget)
+static int twl6030_enable_irq(struct twl6030_usb *twl)
 {
-	if (!otg)
-		return -ENODEV;
-
-	otg->gadget = gadget;
-	if (!gadget)
-		otg->phy->state = OTG_STATE_UNDEFINED;
-
-	return 0;
-}
-
-static int twl6030_enable_irq(struct usb_phy *x)
-{
-	struct twl6030_usb *twl = phy_to_twl(x);
-
 	twl6030_writeb(twl, TWL_MODULE_USB, 0x1, USB_ID_INT_EN_HI_SET);
 	twl6030_interrupt_unmask(0x05, REG_INT_MSK_LINE_C);
 	twl6030_interrupt_unmask(0x05, REG_INT_MSK_STS_C);
@@ -362,9 +307,9 @@ static void otg_set_vbus_work(struct work_struct *data)
 							CHARGERUSB_CTRL1);
 }
 
-static int twl6030_set_vbus(struct usb_otg *otg, bool enabled)
+static int twl6030_set_vbus(struct phy_companion *comparator, bool enabled)
 {
-	struct twl6030_usb *twl = phy_to_twl(otg->phy);
+	struct twl6030_usb *twl = comparator_to_twl(comparator);
 
 	twl->vbus_enable = enabled;
 	schedule_work(&twl->set_vbus_work);
@@ -372,23 +317,12 @@ static int twl6030_set_vbus(struct usb_otg *otg, bool enabled)
 	return 0;
 }
 
-static int twl6030_set_host(struct usb_otg *otg, struct usb_bus *host)
-{
-	if (!otg)
-		return -ENODEV;
-
-	otg->host = host;
-	if (!host)
-		otg->phy->state = OTG_STATE_UNDEFINED;
-	return 0;
-}
-
 static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 {
+	u32 ret;
 	struct twl6030_usb	*twl;
 	int			status, err;
 	struct twl4030_usb_data *pdata;
-	struct usb_otg		*otg;
 	struct device *dev = &pdev->dev;
 	pdata = dev->platform_data;
 
@@ -396,28 +330,20 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 	if (!twl)
 		return -ENOMEM;
 
-	otg = devm_kzalloc(dev, sizeof *otg, GFP_KERNEL);
-	if (!otg)
-		return -ENOMEM;
-
 	twl->dev		= &pdev->dev;
 	twl->irq1		= platform_get_irq(pdev, 0);
 	twl->irq2		= platform_get_irq(pdev, 1);
 	twl->features		= pdata->features;
 	twl->linkstat		= OMAP_MUSB_UNKNOWN;
 
-	twl->phy.dev		= twl->dev;
-	twl->phy.label		= "twl6030";
-	twl->phy.otg		= otg;
-	twl->phy.init		= twl6030_phy_init;
-	twl->phy.shutdown	= twl6030_phy_shutdown;
-	twl->phy.set_suspend	= twl6030_phy_suspend;
+	twl->comparator.set_vbus	= twl6030_set_vbus;
+	twl->comparator.start_srp	= twl6030_start_srp;
 
-	otg->phy		= &twl->phy;
-	otg->set_host		= twl6030_set_host;
-	otg->set_peripheral	= twl6030_set_peripheral;
-	otg->set_vbus		= twl6030_set_vbus;
-	otg->start_srp		= twl6030_start_srp;
+	ret = omap_usb2_set_comparator(&twl->comparator);
+	if (ret == -ENODEV) {
+		dev_info(&pdev->dev, "phy not ready, deferring probe");
+		return -EPROBE_DEFER;
+	}
 
 	/* init spinlock for workqueue */
 	spin_lock_init(&twl->lock);
@@ -427,7 +353,6 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "ldo init failed\n");
 		return err;
 	}
-	usb_add_phy(&twl->phy, USB_PHY_TYPE_USB2);
 
 	platform_set_drvdata(pdev, twl);
 	if (device_create_file(&pdev->dev, &dev_attr_vbus))
@@ -458,9 +383,7 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 	}
 
 	twl->asleep = 0;
-	pdata->phy_init(dev);
-	twl6030_phy_suspend(&twl->phy, 0);
-	twl6030_enable_irq(&twl->phy);
+	twl6030_enable_irq(twl);
 	dev_info(&pdev->dev, "Initialized TWL6030 USB module\n");
 
 	return 0;
@@ -470,10 +393,6 @@ static int __exit twl6030_usb_remove(struct platform_device *pdev)
 {
 	struct twl6030_usb *twl = platform_get_drvdata(pdev);
 
-	struct twl4030_usb_data *pdata;
-	struct device *dev = &pdev->dev;
-	pdata = dev->platform_data;
-
 	twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
 		REG_INT_MSK_LINE_C);
 	twl6030_interrupt_mask(TWL6030_USBOTG_INT_MASK,
@@ -481,7 +400,6 @@ static int __exit twl6030_usb_remove(struct platform_device *pdev)
 	free_irq(twl->irq1, twl);
 	free_irq(twl->irq2, twl);
 	regulator_put(twl->usb3v3);
-	pdata->phy_exit(twl->dev);
 	device_remove_file(twl->dev, &dev_attr_vbus);
 	cancel_work_sync(&twl->set_vbus_work);
 
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:58 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:58 +0530
Subject: [PATCH v7 5/7] drivers: usb: twl4030: Add device tree support for
 twl4030 usb
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-6-git-send-email-kishon@ti.com>

Add device tree support for twl4030 usb driver.
Update the Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/usb/twlxxxx-usb.txt        |   19 ++++++++++++++
 drivers/usb/otg/twl4030-usb.c                      |   26 +++++++++++++++-----
 2 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
index 930f9ff..36b9aed 100644
--- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
+++ b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
@@ -19,3 +19,22 @@ Board specific device node entry
 &twl6030-usb {
 	usb-supply = <&vusb>;
 };
+
+TWL4030 USB PHY AND COMPARATOR
+ - compatible : Should be "ti,twl4030-usb"
+ - interrupts : The interrupt numbers to the cpu should be specified. First
+   interrupt number is the otg interrupt number that raises ID interrupts
+   and VBUS interrupts. The second interrupt number is optional.
+ - <supply-name>-supply : phandle to the regulator device tree node.
+   <supply-name> should be vusb1v5, vusb1v8 and vusb3v1
+ - usb_mode : The mode used by the phy to connect to the controller. "1"
+   specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
+
+twl4030-usb {
+	compatible = "ti,twl4030-usb";
+	interrupts = < 10 4 >;
+	usb1v5-supply = <&vusb1v5>;
+	usb1v8-supply = <&vusb1v8>;
+	usb3v1-supply = <&vusb3v1>;
+	usb_mode = <1>;
+};
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
index 523cad5..f0d2e75 100644
--- a/drivers/usb/otg/twl4030-usb.c
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -585,23 +585,28 @@ static int __devinit twl4030_usb_probe(struct platform_device *pdev)
 	struct twl4030_usb	*twl;
 	int			status, err;
 	struct usb_otg		*otg;
-
-	if (!pdata) {
-		dev_dbg(&pdev->dev, "platform_data not available\n");
-		return -EINVAL;
-	}
+	struct device_node	*np = pdev->dev.of_node;
 
 	twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
 	if (!twl)
 		return -ENOMEM;
 
+	if (np)
+		of_property_read_u32(np, "usb_mode",
+				(enum twl4030_usb_mode *)&twl->usb_mode);
+	else if (pdata)
+		twl->usb_mode = pdata->usb_mode;
+	else {
+		dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
+		return -EINVAL;
+	}
+
 	otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
 	if (!otg)
 		return -ENOMEM;
 
 	twl->dev		= &pdev->dev;
 	twl->irq		= platform_get_irq(pdev, 0);
-	twl->usb_mode		= pdata->usb_mode;
 	twl->vbus_supplied	= false;
 	twl->asleep		= 1;
 	twl->linkstat		= OMAP_MUSB_UNKNOWN;
@@ -690,12 +695,21 @@ static int __exit twl4030_usb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id twl4030_usb_id_table[] = {
+	{ .compatible = "ti,twl4030-usb" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
+#endif
+
 static struct platform_driver twl4030_usb_driver = {
 	.probe		= twl4030_usb_probe,
 	.remove		= __exit_p(twl4030_usb_remove),
 	.driver		= {
 		.name	= "twl4030_usb",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(twl4030_usb_id_table),
 	},
 };
 
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:54 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:54 +0530
Subject: [PATCH v7 1/7] drivers: usb: phy: add a new driver for omap usb2 phy
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-2-git-send-email-kishon@ti.com>

All phy related programming like enabling/disabling the clocks, powering
on/off the phy is taken care of by this driver. It is also used for OTG
related functionality like srp.

This also includes device tree support for usb2 phy driver and
the documentation with device tree binding information is updated.

Currently writing to control module register is taken care in this
driver which will be removed once the control module driver is in place.

Cc: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/bus/omap-ocp2scp.txt       |    3 +
 Documentation/devicetree/bindings/usb/omap-usb.txt |   17 ++
 drivers/usb/phy/Kconfig                            |   10 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/omap-usb2.c                        |  271 ++++++++++++++++++++
 include/linux/usb/omap_usb.h                       |   46 ++++
 include/linux/usb/phy_companion.h                  |   34 +++
 7 files changed, 382 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/omap-usb.txt
 create mode 100644 drivers/usb/phy/omap-usb2.c
 create mode 100644 include/linux/usb/omap_usb.h
 create mode 100644 include/linux/usb/phy_companion.h

diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
index d2fe064..bb0c7f4 100644
--- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -8,3 +8,6 @@ properties:
 
 Sub-nodes:
 All the devices connected to ocp2scp are described using sub-node to ocp2scp
+- usb2phy :
+   The binding details of usb2phy can be found in:
+   Documentation/devicetree/bindings/usb/omap-usb.txt
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
new file mode 100644
index 0000000..52f503b
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -0,0 +1,17 @@
+OMAP USB PHY
+
+OMAP USB2 PHY
+
+Required properties:
+ - compatible: Should be "ti,omap-usb2"
+ - reg : Address and length of the register set for the device. Also
+add the address of control module dev conf register until a driver for
+control module is added
+
+This is usually a subnode of ocp2scp to which it is connected.
+
+usb2phy at 4a0ad080 {
+	compatible = "ti,omap-usb2";
+	reg = <0x4a0ad080 0x58>,
+		<0x4a002300 0x1>;
+};
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..c2ab461 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -4,6 +4,16 @@
 comment "USB Physical Layer drivers"
 	depends on USB || USB_GADGET
 
+config OMAP_USB2
+	tristate "OMAP USB2 PHY Driver"
+	depends on OMAP_OCP2SCP
+	select USB_OTG_UTILS
+	help
+	  Enable this to support the transceiver that is part of SOC. This
+	  driver takes care of all the PHY functionality apart from comparator.
+	  The USB OTG controller communicates with the comparator using this
+	  driver.
+
 config USB_ISP1301
 	tristate "NXP ISP1301 USB transceiver support"
 	depends on USB || USB_GADGET
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..d3fcec9 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -4,4 +4,5 @@
 
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
+obj-$(CONFIG_OMAP_USB2)			+= omap-usb2.o
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
diff --git a/drivers/usb/phy/omap-usb2.c b/drivers/usb/phy/omap-usb2.c
new file mode 100644
index 0000000..984899b
--- /dev/null
+++ b/drivers/usb/phy/omap-usb2.c
@@ -0,0 +1,271 @@
+/*
+ * omap-usb2.c - USB PHY, talking to musb controller in OMAP.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/usb/omap_usb.h>
+#include <linux/usb/phy_companion.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+#include <linux/delay.h>
+
+/**
+ * omap_usb2_set_comparator - links the comparator present in the sytem with
+ *	this phy
+ * @comparator - the companion phy(comparator) for this phy
+ *
+ * The phy companion driver should call this API passing the phy_companion
+ * filled with set_vbus and start_srp to be used by usb phy.
+ *
+ * For use by phy companion driver
+ */
+int omap_usb2_set_comparator(struct phy_companion *comparator)
+{
+	struct omap_usb	*phy;
+	struct usb_phy	*x = usb_get_phy(USB_PHY_TYPE_USB2);
+
+	if (IS_ERR(x))
+		return -ENODEV;
+
+	phy = phy_to_omapusb(x);
+	phy->comparator = comparator;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(omap_usb2_set_comparator);
+
+/**
+ * omap_usb_phy_power - power on/off the phy using control module reg
+ * @phy: struct omap_usb *
+ * @on: 0 or 1, based on powering on or off the PHY
+ *
+ * XXX: Remove this function once control module driver gets merged
+ */
+static void omap_usb_phy_power(struct omap_usb *phy, int on)
+{
+	u32 val;
+
+	if (on) {
+		val = readl(phy->control_dev);
+		if (val & PHY_PD) {
+			writel(~PHY_PD, phy->control_dev);
+			/* XXX: add proper documentation for this delay */
+			mdelay(200);
+		}
+	} else {
+		writel(PHY_PD, phy->control_dev);
+	}
+}
+
+static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
+{
+	struct omap_usb *phy = phy_to_omapusb(otg->phy);
+
+	if (!phy->comparator)
+		return -ENODEV;
+
+	return phy->comparator->set_vbus(phy->comparator, enabled);
+}
+
+static int omap_usb_start_srp(struct usb_otg *otg)
+{
+	struct omap_usb *phy = phy_to_omapusb(otg->phy);
+
+	if (!phy->comparator)
+		return -ENODEV;
+
+	return phy->comparator->start_srp(phy->comparator);
+}
+
+static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+	struct usb_phy	*phy = otg->phy;
+
+	otg->host = host;
+	if (!host)
+		phy->state = OTG_STATE_UNDEFINED;
+
+	return 0;
+}
+
+static int omap_usb_set_peripheral(struct usb_otg *otg,
+		struct usb_gadget *gadget)
+{
+	struct usb_phy	*phy = otg->phy;
+
+	otg->gadget = gadget;
+	if (!gadget)
+		phy->state = OTG_STATE_UNDEFINED;
+
+	return 0;
+}
+
+static int omap_usb2_suspend(struct usb_phy *x, int suspend)
+{
+	u32 ret;
+	struct omap_usb *phy = phy_to_omapusb(x);
+
+	if (suspend && !phy->is_suspended) {
+		omap_usb_phy_power(phy, 0);
+		pm_runtime_put_sync(phy->dev);
+		phy->is_suspended = 1;
+	} else if (!suspend && phy->is_suspended) {
+		ret = pm_runtime_get_sync(phy->dev);
+		if (ret < 0) {
+			dev_err(phy->dev, "get_sync failed with err %d\n",
+									ret);
+			return ret;
+		}
+		omap_usb_phy_power(phy, 1);
+		phy->is_suspended = 0;
+	}
+
+	return 0;
+}
+
+static int __devinit omap_usb2_probe(struct platform_device *pdev)
+{
+	struct omap_usb			*phy;
+	struct usb_otg			*otg;
+	struct resource			*res;
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy) {
+		dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n");
+		return -ENOMEM;
+	}
+
+	otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
+	if (!otg) {
+		dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
+		return -ENOMEM;
+	}
+
+	phy->dev		= &pdev->dev;
+
+	phy->phy.dev		= phy->dev;
+	phy->phy.label		= "omap-usb2";
+	phy->phy.set_suspend	= omap_usb2_suspend;
+	phy->phy.otg		= otg;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	phy->control_dev = devm_request_and_ioremap(&pdev->dev, res);
+	if (phy->control_dev == NULL) {
+		dev_err(&pdev->dev, "Failed to obtain io memory\n");
+		return -ENXIO;
+	}
+
+	phy->is_suspended	= 1;
+	omap_usb_phy_power(phy, 0);
+
+	otg->set_host		= omap_usb_set_host;
+	otg->set_peripheral	= omap_usb_set_peripheral;
+	otg->set_vbus		= omap_usb_set_vbus;
+	otg->start_srp		= omap_usb_start_srp;
+	otg->phy		= &phy->phy;
+
+	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+	if (IS_ERR(phy->wkupclk)) {
+		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
+		return PTR_ERR(phy->wkupclk);
+	}
+	clk_prepare(phy->wkupclk);
+
+	usb_add_phy(&phy->phy, USB_PHY_TYPE_USB2);
+
+	platform_set_drvdata(pdev, phy);
+
+	pm_runtime_enable(phy->dev);
+
+	return 0;
+}
+
+static int __devexit omap_usb2_remove(struct platform_device *pdev)
+{
+	struct omap_usb	*phy = platform_get_drvdata(pdev);
+
+	clk_unprepare(phy->wkupclk);
+	usb_remove_phy(&phy->phy);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_RUNTIME
+
+static int omap_usb2_runtime_suspend(struct device *dev)
+{
+	struct platform_device	*pdev = to_platform_device(dev);
+	struct omap_usb	*phy = platform_get_drvdata(pdev);
+
+	clk_disable(phy->wkupclk);
+
+	return 0;
+}
+
+static int omap_usb2_runtime_resume(struct device *dev)
+{
+	u32 ret = 0;
+	struct platform_device	*pdev = to_platform_device(dev);
+	struct omap_usb	*phy = platform_get_drvdata(pdev);
+
+	ret = clk_enable(phy->wkupclk);
+	if (ret < 0)
+		dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
+
+	return ret;
+}
+
+static const struct dev_pm_ops omap_usb2_pm_ops = {
+	SET_RUNTIME_PM_OPS(omap_usb2_runtime_suspend, omap_usb2_runtime_resume,
+		NULL)
+};
+
+#define DEV_PM_OPS     (&omap_usb2_pm_ops)
+#else
+#define DEV_PM_OPS     NULL
+#endif
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_usb2_id_table[] = {
+	{ .compatible = "ti,omap-usb2" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
+static struct platform_driver omap_usb2_driver = {
+	.probe		= omap_usb2_probe,
+	.remove		= __devexit_p(omap_usb2_remove),
+	.driver		= {
+		.name	= "omap-usb2",
+		.owner	= THIS_MODULE,
+		.pm	= DEV_PM_OPS,
+		.of_match_table = of_match_ptr(omap_usb2_id_table),
+	},
+};
+
+module_platform_driver(omap_usb2_driver);
+
+MODULE_ALIAS("platform: omap_usb2");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_DESCRIPTION("OMAP USB2 phy driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/usb/omap_usb.h b/include/linux/usb/omap_usb.h
new file mode 100644
index 0000000..0ea17f8
--- /dev/null
+++ b/include/linux/usb/omap_usb.h
@@ -0,0 +1,46 @@
+/*
+ * omap_usb.h -- omap usb2 phy header file
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_OMAP_USB2_H
+#define __DRIVERS_OMAP_USB2_H
+
+#include <linux/usb/otg.h>
+
+struct omap_usb {
+	struct usb_phy		phy;
+	struct phy_companion	*comparator;
+	struct device		*dev;
+	u32 __iomem		*control_dev;
+	struct clk		*wkupclk;
+	u8			is_suspended:1;
+};
+
+#define	PHY_PD	0x1
+
+#define	phy_to_omapusb(x)	container_of((x), struct omap_usb, phy)
+
+#if defined(CONFIG_OMAP_USB2) || defined(CONFIG_OMAP_USB2_MODULE)
+extern int omap_usb2_set_comparator(struct phy_companion *comparator);
+#else
+static inline int omap_usb2_set_comparator(struct phy_companion *comparator)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif /* __DRIVERS_OMAP_USB_H */
diff --git a/include/linux/usb/phy_companion.h b/include/linux/usb/phy_companion.h
new file mode 100644
index 0000000..edd2ec2
--- /dev/null
+++ b/include/linux/usb/phy_companion.h
@@ -0,0 +1,34 @@
+/*
+ * phy-companion.h -- phy companion to indicate the comparator part of PHY
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_PHY_COMPANION_H
+#define __DRIVERS_PHY_COMPANION_H
+
+#include <linux/usb/otg.h>
+
+/* phy_companion to take care of VBUS, ID and srp capabilities */
+struct phy_companion {
+
+	/* effective for A-peripheral, ignored for B devices */
+	int	(*set_vbus)(struct phy_companion *x, bool enabled);
+
+	/* for B devices only:  start session with A-Host */
+	int	(*start_srp)(struct phy_companion *x);
+};
+
+#endif /* __DRIVERS_PHY_COMPANION_H */
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:57 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:57 +0530
Subject: [PATCH v7 4/7] drivers: usb: twl6030: Add dt support for twl6030 usb
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-5-git-send-email-kishon@ti.com>

Add device tree support for twl6030 usb driver.
Update the Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/usb/twlxxxx-usb.txt        |   21 +++++++++++
 drivers/usb/otg/twl6030-usb.c                      |   39 +++++++++++++-------
 2 files changed, 47 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/twlxxxx-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
new file mode 100644
index 0000000..930f9ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt
@@ -0,0 +1,21 @@
+USB COMPARATOR OF TWL CHIPS
+
+TWL6030 USB COMPARATOR
+ - compatible : Should be "ti,twl6030-usb"
+ - interrupts : Two interrupt numbers to the cpu should be specified. First
+   interrupt number is the otg interrupt number that raises ID interrupts when
+   the controller has to act as host and the second interrupt number is the
+   usb interrupt number that raises VBUS interrupts when the controller has to
+   act as device
+ - usb-supply : phandle to the regulator device tree node. It should be vusb
+   if it is twl6030 or ldousb if it is twl6025 subclass.
+
+twl6030-usb {
+	compatible = "ti,twl6030-usb";
+	interrupts = < 4 10 >;
+};
+
+Board specific device node entry
+&twl6030-usb {
+	usb-supply = <&vusb>;
+};
diff --git a/drivers/usb/otg/twl6030-usb.c b/drivers/usb/otg/twl6030-usb.c
index 32525bb..fcadef7 100644
--- a/drivers/usb/otg/twl6030-usb.c
+++ b/drivers/usb/otg/twl6030-usb.c
@@ -105,7 +105,7 @@ struct twl6030_usb {
 	u8			asleep;
 	bool			irq_enabled;
 	bool			vbus_enable;
-	unsigned long		features;
+	const char		*regulator;
 };
 
 #define	comparator_to_twl(x) container_of((x), struct twl6030_usb, comparator)
@@ -153,13 +153,6 @@ static int twl6030_start_srp(struct phy_companion *comparator)
 
 static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
 {
-	char *regulator_name;
-
-	if (twl->features & TWL6025_SUBCLASS)
-		regulator_name = "ldousb";
-	else
-		regulator_name = "vusb";
-
 	/* Set to OTG_REV 1.3 and turn on the ID_WAKEUP_COMP */
 	twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x1, TWL6030_BACKUP_REG);
 
@@ -169,7 +162,7 @@ static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
 	/* Program MISC2 register and set bit VUSB_IN_VBAT */
 	twl6030_writeb(twl, TWL6030_MODULE_ID0 , 0x10, TWL6030_MISC2);
 
-	twl->usb3v3 = regulator_get(twl->dev, regulator_name);
+	twl->usb3v3 = regulator_get(twl->dev, twl->regulator);
 	if (IS_ERR(twl->usb3v3))
 		return -ENODEV;
 
@@ -322,9 +315,9 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 	u32 ret;
 	struct twl6030_usb	*twl;
 	int			status, err;
-	struct twl4030_usb_data *pdata;
-	struct device *dev = &pdev->dev;
-	pdata = dev->platform_data;
+	struct device_node	*np = pdev->dev.of_node;
+	struct device		*dev = &pdev->dev;
+	struct twl4030_usb_data	*pdata = dev->platform_data;
 
 	twl = devm_kzalloc(dev, sizeof *twl, GFP_KERNEL);
 	if (!twl)
@@ -333,7 +326,6 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 	twl->dev		= &pdev->dev;
 	twl->irq1		= platform_get_irq(pdev, 0);
 	twl->irq2		= platform_get_irq(pdev, 1);
-	twl->features		= pdata->features;
 	twl->linkstat		= OMAP_MUSB_UNKNOWN;
 
 	twl->comparator.set_vbus	= twl6030_set_vbus;
@@ -345,6 +337,18 @@ static int __devinit twl6030_usb_probe(struct platform_device *pdev)
 		return -EPROBE_DEFER;
 	}
 
+	if (np) {
+		twl->regulator = "usb";
+	} else if (pdata) {
+		if (pdata->features & TWL6025_SUBCLASS)
+			twl->regulator = "ldousb";
+		else
+			twl->regulator = "vusb";
+	} else {
+		dev_err(&pdev->dev, "twl6030 initialized without pdata\n");
+		return -EINVAL;
+	}
+
 	/* init spinlock for workqueue */
 	spin_lock_init(&twl->lock);
 
@@ -406,12 +410,21 @@ static int __exit twl6030_usb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id twl6030_usb_id_table[] = {
+	{ .compatible = "ti,twl6030-usb" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, twl6030_usb_id_table);
+#endif
+
 static struct platform_driver twl6030_usb_driver = {
 	.probe		= twl6030_usb_probe,
 	.remove		= __exit_p(twl6030_usb_remove),
 	.driver		= {
 		.name	= "twl6030_usb",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(twl6030_usb_id_table),
 	},
 };
 
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:08:00 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:38:00 +0530
Subject: [PATCH v7 7/7] arm: omap: phy: remove unused functions from
 omap-phy-internal.c
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-8-git-send-email-kishon@ti.com>

All the unnessary functions in omap-phy-internal is removed.
These functionality are now handled by omap-usb2 phy driver.

Cc: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/omap_phy_internal.c |  138 -------------------------------
 arch/arm/mach-omap2/twl-common.c        |    5 --
 arch/arm/mach-omap2/usb-musb.c          |    3 -
 3 files changed, 146 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d52651a..874aecc 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -31,144 +31,6 @@
 #include <plat/usb.h>
 #include "control.h"
 
-/* OMAP control module register for UTMI PHY */
-#define CONTROL_DEV_CONF		0x300
-#define PHY_PD				0x1
-
-#define USBOTGHS_CONTROL		0x33c
-#define	AVALID				BIT(0)
-#define	BVALID				BIT(1)
-#define	VBUSVALID			BIT(2)
-#define	SESSEND				BIT(3)
-#define	IDDIG				BIT(4)
-
-static struct clk *phyclk, *clk48m, *clk32k;
-static void __iomem *ctrl_base;
-static int usbotghs_control;
-
-int omap4430_phy_init(struct device *dev)
-{
-	ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
-	if (!ctrl_base) {
-		pr_err("control module ioremap failed\n");
-		return -ENOMEM;
-	}
-	/* Power down the phy */
-	__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-	if (!dev) {
-		iounmap(ctrl_base);
-		return 0;
-	}
-
-	phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
-	if (IS_ERR(phyclk)) {
-		dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
-		iounmap(ctrl_base);
-		return PTR_ERR(phyclk);
-	}
-
-	clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
-	if (IS_ERR(clk48m)) {
-		dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
-		clk_put(phyclk);
-		iounmap(ctrl_base);
-		return PTR_ERR(clk48m);
-	}
-
-	clk32k = clk_get(dev, "usb_phy_cm_clk32k");
-	if (IS_ERR(clk32k)) {
-		dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
-		clk_put(phyclk);
-		clk_put(clk48m);
-		iounmap(ctrl_base);
-		return PTR_ERR(clk32k);
-	}
-	return 0;
-}
-
-int omap4430_phy_set_clk(struct device *dev, int on)
-{
-	static int state;
-
-	if (on && !state) {
-		/* Enable the phy clocks */
-		clk_enable(phyclk);
-		clk_enable(clk48m);
-		clk_enable(clk32k);
-		state = 1;
-	} else if (state) {
-		/* Disable the phy clocks */
-		clk_disable(phyclk);
-		clk_disable(clk48m);
-		clk_disable(clk32k);
-		state = 0;
-	}
-	return 0;
-}
-
-int omap4430_phy_power(struct device *dev, int ID, int on)
-{
-	if (on) {
-		if (ID)
-			/* enable VBUS valid, IDDIG groung */
-			__raw_writel(AVALID | VBUSVALID, ctrl_base +
-							USBOTGHS_CONTROL);
-		else
-			/*
-			 * Enable VBUS Valid, AValid and IDDIG
-			 * high impedance
-			 */
-			__raw_writel(IDDIG | AVALID | VBUSVALID,
-						ctrl_base + USBOTGHS_CONTROL);
-	} else {
-		/* Enable session END and IDIG to high impedance. */
-		__raw_writel(SESSEND | IDDIG, ctrl_base +
-					USBOTGHS_CONTROL);
-	}
-	return 0;
-}
-
-int omap4430_phy_suspend(struct device *dev, int suspend)
-{
-	if (suspend) {
-		/* Disable the clocks */
-		omap4430_phy_set_clk(dev, 0);
-		/* Power down the phy */
-		__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-
-		/* save the context */
-		usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
-	} else {
-		/* Enable the internel phy clcoks */
-		omap4430_phy_set_clk(dev, 1);
-		/* power on the phy */
-		if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
-			__raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-			mdelay(200);
-		}
-
-		/* restore the context */
-		__raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
-	}
-
-	return 0;
-}
-
-int omap4430_phy_exit(struct device *dev)
-{
-	if (ctrl_base)
-		iounmap(ctrl_base);
-	if (phyclk)
-		clk_put(phyclk);
-	if (clk48m)
-		clk_put(clk48m);
-	if (clk32k)
-		clk_put(clk32k);
-
-	return 0;
-}
-
 void am35x_musb_reset(void)
 {
 	u32	regval;
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index de47f17..e2cdf67 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -250,11 +250,6 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 
 #if defined(CONFIG_ARCH_OMAP4)
 static struct twl4030_usb_data omap4_usb_pdata = {
-	.phy_init	= omap4430_phy_init,
-	.phy_exit	= omap4430_phy_exit,
-	.phy_power	= omap4430_phy_power,
-	.phy_set_clock	= omap4430_phy_set_clk,
-	.phy_suspend	= omap4430_phy_suspend,
 };
 
 static struct regulator_init_data omap4_vdac_idata = {
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index c4a5768..e9b4b23 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -117,7 +117,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
 	dev->dma_mask = &musb_dmamask;
 	dev->coherent_dma_mask = musb_dmamask;
 	put_device(dev);
-
-	if (cpu_is_omap44xx())
-		omap4430_phy_init(dev);
 }
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:07:59 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:37:59 +0530
Subject: [PATCH v7 6/7] drivers: usb: musb: Add device tree support for omap
 musb glue
In-Reply-To: <1344258480-4304-1-git-send-email-kishon@ti.com>
References: <1344258480-4304-1-git-send-email-kishon@ti.com>
Message-ID: <1344258480-4304-7-git-send-email-kishon@ti.com>

Added device tree support for omap musb driver and updated the
Documentation with device tree binding information.

Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 Documentation/devicetree/bindings/usb/omap-usb.txt |   34 +++++++++++-
 drivers/usb/musb/omap2430.c                        |   54 ++++++++++++++++++++
 2 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 52f503b..49a90fb 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -1,4 +1,4 @@
-OMAP USB PHY
+OMAP USB PHY AND GLUE
 
 OMAP USB2 PHY
 
@@ -15,3 +15,35 @@ usb2phy at 4a0ad080 {
 	reg = <0x4a0ad080 0x58>,
 		<0x4a002300 0x1>;
 };
+
+OMAP MUSB GLUE
+ - compatible : Should be "ti,musb-omap2430"
+ - ti,hwmods : must be "usb_otg_hs"
+ - multipoint : Should be "1" indicating the musb controller supports
+   multipoint. This is a MUSB configuration-specific setting.
+ - num_eps : Specifies the number of endpoints. This is also a
+   MUSB configuration-specific setting. Should be set to "16"
+ - ram_bits : Specifies the ram address size. Should be set to "12"
+ - interface_type : This is a board specific setting to describe the type of
+   interface between the controller and the phy. It should be "0" or "1"
+   specifying ULPI and UTMI respectively.
+ - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
+   represents PERIPHERAL.
+ - power : Should be "50". This signifies the controller can supply upto
+   100mA when operating in host mode.
+
+SOC specific device node entry
+usb_otg_hs: usb_otg_hs at 4a0ab000 {
+	compatible = "ti,musb-omap2430";
+	ti,hwmods = "usb_otg_hs";
+	multipoint = <1>;
+	num_eps = <16>;
+	ram_bits = <12>;
+};
+
+Board specific device node entry
+&usb_otg_hs {
+	interface_type = <1>;
+	mode = <3>;
+	power = <50>;
+};
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 74dbd6f..8b1d7c0 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -30,6 +30,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
@@ -469,8 +470,11 @@ static u64 omap2430_dmamask = DMA_BIT_MASK(32);
 static int __devinit omap2430_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
+	struct omap_musb_board_data	*data;
 	struct platform_device		*musb;
 	struct omap2430_glue		*glue;
+	struct device_node		*np = pdev->dev.of_node;
+	struct musb_hdrc_config		*config;
 	struct resource			*res;
 	int				ret = -ENOMEM;
 
@@ -500,6 +504,42 @@ static int __devinit omap2430_probe(struct platform_device *pdev)
 	if (glue->control_otghs == NULL)
 		dev_dbg(&pdev->dev, "Failed to obtain control memory\n");
 
+	if (np) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata) {
+			dev_err(&pdev->dev,
+				"failed to allocate musb platfrom data\n");
+			ret = -ENOMEM;
+			goto err1;
+		}
+
+		data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+		if (!data) {
+			dev_err(&pdev->dev,
+					"failed to allocate musb board data\n");
+			ret = -ENOMEM;
+			goto err1;
+		}
+
+		config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
+		if (!data) {
+			dev_err(&pdev->dev,
+				"failed to allocate musb hdrc config\n");
+			goto err1;
+		}
+
+		of_property_read_u32(np, "mode", (u32 *)&pdata->mode);
+		of_property_read_u32(np, "interface_type",
+						(u32 *)&data->interface_type);
+		of_property_read_u32(np, "num_eps", (u32 *)&config->num_eps);
+		of_property_read_u32(np, "ram_bits", (u32 *)&config->ram_bits);
+		of_property_read_u32(np, "power", (u32 *)&pdata->power);
+		config->multipoint = of_property_read_bool(np, "multipoint");
+
+		pdata->board_data	= data;
+		pdata->config		= config;
+	}
+
 	pdata->platform_ops		= &omap2430_ops;
 
 	platform_set_drvdata(pdev, glue);
@@ -596,12 +636,26 @@ static struct dev_pm_ops omap2430_pm_ops = {
 #define DEV_PM_OPS	NULL
 #endif
 
+#ifdef CONFIG_OF
+static const struct of_device_id omap2430_id_table[] = {
+	{
+		.compatible = "ti,omap4-musb"
+	},
+	{
+		.compatible = "ti,omap3-musb"
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, omap2430_id_table);
+#endif
+
 static struct platform_driver omap2430_driver = {
 	.probe		= omap2430_probe,
 	.remove		= __devexit_p(omap2430_remove),
 	.driver		= {
 		.name	= "musb-omap2430",
 		.pm	= DEV_PM_OPS,
+		.of_match_table = of_match_ptr(omap2430_id_table),
 	},
 };
 
-- 
1.7.9.5



From cyril at ti.com  Mon Aug  6 09:19:10 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Mon, 6 Aug 2012 09:19:10 -0400
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <20120806111224.GA18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <20120806111224.GA18957@n2100.arm.linux.org.uk>
Message-ID: <501FC44E.1040806@ti.com>

On 8/6/2012 7:12 AM, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2012 at 07:04:37PM -0400, Cyril Chemparathy wrote:
>> +static void __init init_patch_kernel(void)
>> +{
>> +	const void *start = &__patch_table_begin;
>> +	const void *end   = &__patch_table_end;
>> +
>> +	BUG_ON(patch_kernel(start, end - start));
>> +	flush_icache_range(init_mm.start_code, init_mm.end_code);
>
> Err.  You are asking the kernel to flush every single cache line
> manually throughout the kernel code.  That's a flush every 32-bytes
> over maybe a few megabytes of address space.
>

With a flush_cache_all(), we could avoid having to operate a cacheline 
at a time, but that clobbers way more than necessary.

Maybe the better answer is to flush only the patched cachelines.

> This is one of the reasons we do the patching in assembly code before
> the caches are enabled - so we don't have to worry about the interaction
> with the CPU caches, which for this kind of application would be very
> expensive.
>

Sure, flushing caches is expensive.  But then, so is running the 
patching code with caches disabled.  I guess memory access latencies 
drive the performance trade off here.

-- 
Thanks
- Cyril


From kishon at ti.com  Mon Aug  6 09:23:15 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:53:15 +0530
Subject: [PATCH 4/4] arm/dts: omap: Add usb_otg and glue data
In-Reply-To: <1344259395-4559-1-git-send-email-kishon@ti.com>
References: <1344259395-4559-1-git-send-email-kishon@ti.com>
Message-ID: <1344259395-4559-5-git-send-email-kishon@ti.com>

Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-<board>.dts file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap3-beagle.dts |    6 ++++++
 arch/arm/boot/dts/omap3-evm.dts    |    6 ++++++
 arch/arm/boot/dts/omap3.dtsi       |    8 ++++++++
 arch/arm/boot/dts/omap4-panda.dts  |    6 ++++++
 arch/arm/boot/dts/omap4-sdp.dts    |    6 ++++++
 arch/arm/boot/dts/omap4.dtsi       |    8 ++++++++
 6 files changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index cdcb98c..6d6a7a4 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -67,3 +67,9 @@
 &mmc3 {
 	status = "disabled";
 };
+
+&usb_otg_hs {
+	interface_type = <0>;
+	mode = <3>;
+	power = <50>;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9..c4ac75e 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -46,3 +46,9 @@
 		reg = <0x5c>;
 	};
 };
+
+&usb_otg_hs {
+	interface_type = <0>;
+	mode = <3>;
+	power = <50>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 8109471..2501416 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -220,5 +220,13 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		usb_otg_hs: usb_otg_hs {
+			compatible = "ti,omap3-musb";
+			ti,hwmods = "usb_otg_hs";
+			multipoint = <1>;
+			num_eps = <16>;
+			ram_bits = <12>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 2999eba..8cded95 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -130,3 +130,9 @@
 &twlusb {
 	usb-supply = <&vusb>;
 };
+
+&usb_otg_hs {
+	interface_type = <1>;
+	mode = <3>;
+	power = <50>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index d8290c0..24f4bfd 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -230,3 +230,9 @@
 &twlusb {
 	usb-supply = <&vusb>;
 };
+
+&usb_otg_hs {
+	interface_type = <1>;
+	mode = <3>;
+	power = <50>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d774733..a855d13 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -308,5 +308,13 @@
 				      <0x4a002300 0x1>;
 			};
 		};
+
+		usb_otg_hs: usb_otg_hs {
+			compatible = "ti,omap4-musb";
+			ti,hwmods = "usb_otg_hs";
+			multipoint = <1>;
+			num_eps = <16>;
+			ram_bits = <12>;
+		};
 	};
 };
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:23:14 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:53:14 +0530
Subject: [PATCH 3/4] arm/dts: Add twl4030-usb data
In-Reply-To: <1344259395-4559-1-git-send-email-kishon@ti.com>
References: <1344259395-4559-1-git-send-email-kishon@ti.com>
Message-ID: <1344259395-4559-4-git-send-email-kishon@ti.com>

Add twl4030-usb data node in twl4030 device tree file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/twl4030.dtsi |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d13..761a5a5 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -37,6 +37,18 @@
 		regulator-max-microvolt = <3150000>;
 	};
 
+	vusb1v5: regulator-vusb1v5 {
+		compatible = "ti,twl4030-vusb1v5";
+	};
+
+	vusb1v8: regulator-vusb1v8 {
+		compatible = "ti,twl4030-vusb1v8";
+	};
+
+	vusb3v1: regulator-vusb3v1 {
+		compatible = "ti,twl4030-vusb3v1";
+	};
+
 	twl_gpio: gpio {
 		compatible = "ti,twl4030-gpio";
 		gpio-controller;
@@ -44,4 +56,13 @@
 		interrupt-controller;
 		#interrupt-cells = <1>;
 	};
+
+	twl4030-usb {
+		compatible = "ti,twl4030-usb";
+		interrupts = < 10 4 >;
+		usb1v5-supply = <&vusb1v5>;
+		usb1v8-supply = <&vusb1v8>;
+		usb3v1-supply = <&vusb3v1>;
+		usb_mode = <1>;
+	};
 };
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:23:11 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:53:11 +0530
Subject: [PATCH 0/4] arm/dts: omap: add dt data for MUSB
Message-ID: <1344259395-4559-1-git-send-email-kishon@ti.com>

This patch series adds dt data for MUSB and related modules to
get MUSB working

These patches were initially part of
[PATCH v6 00/11] omap: musb: Add device tree support

These patches can be tested by applying it over
[PATCH v7 0/7] omap: musb: Add device tree support

These patches were developed on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git

If it needs to be rebased on some other tree, pls let me
know.

Performed MUSB device mode testing on omap4 panda,
omap4 sdp and omap3 beagle

Kishon Vijay Abraham I (4):
  arm/dts: omap: Add omap-usb2 dt data
  arm/dts: Add twl6030-usb data
  arm/dts: Add twl4030-usb data
  arm/dts: omap: Add usb_otg and glue data

 arch/arm/boot/dts/omap3-beagle.dts |    6 ++++++
 arch/arm/boot/dts/omap3-evm.dts    |    6 ++++++
 arch/arm/boot/dts/omap3.dtsi       |    8 ++++++++
 arch/arm/boot/dts/omap4-panda.dts  |   10 ++++++++++
 arch/arm/boot/dts/omap4-sdp.dts    |   10 ++++++++++
 arch/arm/boot/dts/omap4.dtsi       |   13 +++++++++++++
 arch/arm/boot/dts/twl4030.dtsi     |   21 +++++++++++++++++++++
 arch/arm/boot/dts/twl6030.dtsi     |    5 +++++
 8 files changed, 79 insertions(+)

-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:23:12 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:53:12 +0530
Subject: [PATCH 1/4] arm/dts: omap: Add omap-usb2 dt data
In-Reply-To: <1344259395-4559-1-git-send-email-kishon@ti.com>
References: <1344259395-4559-1-git-send-email-kishon@ti.com>
Message-ID: <1344259395-4559-2-git-send-email-kishon@ti.com>

Add omap-usb2 data node in omap4 device tree file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 8a780b2..d774733 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -302,6 +302,11 @@
 			#size-cells = <1>;
 			ranges;
 			ti,hwmods = "ocp2scp_usb_phy";
+			usb2phy at 4a0ad080 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a0ad080 0x58>,
+				      <0x4a002300 0x1>;
+			};
 		};
 	};
 };
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:23:13 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 18:53:13 +0530
Subject: [PATCH 2/4] arm/dts: Add twl6030-usb data
In-Reply-To: <1344259395-4559-1-git-send-email-kishon@ti.com>
References: <1344259395-4559-1-git-send-email-kishon@ti.com>
Message-ID: <1344259395-4559-3-git-send-email-kishon@ti.com>

Add twl6030-usb data node in twl6030 device tree file

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap4-panda.dts |    4 ++++
 arch/arm/boot/dts/omap4-sdp.dts   |    4 ++++
 arch/arm/boot/dts/twl6030.dtsi    |    5 +++++
 3 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12..2999eba 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -126,3 +126,7 @@
 	ti,non-removable;
 	bus-width = <4>;
 };
+
+&twlusb {
+	usb-supply = <&vusb>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e9..d8290c0 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -226,3 +226,7 @@
 	bus-width = <4>;
 	ti,non-removable;
 };
+
+&twlusb {
+	usb-supply = <&vusb>;
+};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 3b2f351..8e3aac9 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -83,4 +83,9 @@
 	clk32kg: regulator at 12 {
 		compatible = "ti,twl6030-clk32kg";
 	};
+
+	twlusb: twl6030-usb {
+		compatible = "ti,twl6030-usb";
+		interrupts = < 4 10 >;
+	};
 };
-- 
1.7.9.5



From linux at arm.linux.org.uk  Mon Aug  6 09:26:42 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 Aug 2012 14:26:42 +0100
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <501FC44E.1040806@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <20120806111224.GA18957@n2100.arm.linux.org.uk> <501FC44E.1040806@ti.com>
Message-ID: <20120806132642.GC18957@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 09:19:10AM -0400, Cyril Chemparathy wrote:
> With a flush_cache_all(), we could avoid having to operate a cacheline  
> at a time, but that clobbers way more than necessary.

You can't do that, because flush_cache_all() on some CPUs requires the
proper MMU mappings to be in place, and you can't get those mappings
in place because you don't have the V:P offsets fixed up in the kernel.
Welcome to the chicken and egg problem.

> Sure, flushing caches is expensive.  But then, so is running the  
> patching code with caches disabled.  I guess memory access latencies  
> drive the performance trade off here.

There we disagree on a few orders of magnitude.  There are relatively
few places that need updating.  According to the kernel I have here:

   text    data     bss     dec     hex filename
7644346  454320  212984 8311650  7ed362 vmlinux

Idx Name          Size      VMA       LMA       File off  Algn
  1 .text         004cd170  c00081c0  c00081c0  000081c0  2**5
 16 .init.pv_table 00000300  c0753a24  c0753a24  00753a24  2**0

That's about 7MB of text, and only 192 points in that code which need
patching.  Even if we did this with caches on, that's still 192 places,
and only 192 places we'd need to flush a cache line.

Alternatively, with your approach and 7MB of text, you need to flush
238885 cache lines to cover the entire kernel.

It would be far _cheaper_ with your approach to flush the individual
cache lines as you go.


From jean.pihet at newoldbits.com  Mon Aug  6 09:29:38 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Mon, 6 Aug 2012 15:29:38 +0200
Subject: [PATCHv7 06/12] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <500816BB.3090809@mvista.com>
References: <1342704392-23657-1-git-send-email-t-kristo@ti.com>
 <1342704392-23657-7-git-send-email-t-kristo@ti.com>
 <500816BB.3090809@mvista.com>
Message-ID: <CAORVsuWvWDcK5fxGmXmbaHZQ48utRv6FoS2cOrYcP_8eFOLiBw@mail.gmail.com>

Hi!

On Thu, Jul 19, 2012 at 4:16 PM, Sergei Shtylyov <sshtylyov at mvista.com> wrote:
> Hello.
>
> On 07/19/2012 05:26 PM, Tero Kristo wrote:
>
>> From: Rajendra Nayak <rnayak at ti.com>
>
>> Remove the FIXME's in the suspend sequence since
>> we now intend to support system level RET support.
>
>> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
>> Signed-off-by: Tero Kristo <t-kristo at ti.com>
>> [Jean Pihet <j-pihet at ti.com>: ported on top of the functional power
>> states]
>
>   Shouldn't Jean also have signed off?
Sure! I am OK with this change, feel free to add:
Acked-by: Jean Pihet <j-pihet at ti.com>

Regards,
Jean

>
>> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> WBR, Sergei
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From cyril at ti.com  Mon Aug  6 09:30:00 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Mon, 6 Aug 2012 09:30:00 -0400
Subject: [PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <20120806111413.GB18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-4-git-send-email-cyril@ti.com>
 <20120806111413.GB18957@n2100.arm.linux.org.uk>
Message-ID: <501FC6D8.3010900@ti.com>

On 8/6/2012 7:14 AM, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2012 at 07:04:39PM -0400, Cyril Chemparathy wrote:
>> This patch fixes up the types used when converting back and forth between
>> physical and virtual addresses.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
>>   arch/arm/include/asm/memory.h |   17 +++++++++++------
>>   1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
>> index 01c710d..4a0108f 100644
>> --- a/arch/arm/include/asm/memory.h
>> +++ b/arch/arm/include/asm/memory.h
>> @@ -157,22 +157,27 @@ extern unsigned long __pv_phys_offset;
>>
>>   extern unsigned long __pv_offset;
>>
>> -static inline unsigned long __virt_to_phys(unsigned long x)
>> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "add", __pv_offset);
>>   	return t;
>>   }
>>
>> -static inline unsigned long __phys_to_virt(unsigned long x)
>> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "sub", __pv_offset);
>>   	return t;
>>   }
>>   #else
>> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
>> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
>> +
>> +#define __virt_to_phys(x)		\
>> +	((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)
>> +
>> +#define __phys_to_virt(x)		\
>> +	((unsigned long)((phys_addr_t)(x) - PHYS_OFFSET + PAGE_OFFSET))
>> +
>>   #endif
>>   #endif
>>
>> @@ -207,14 +212,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>>
>>   static inline void *phys_to_virt(phys_addr_t x)
>>   {
>> -	return (void *)(__phys_to_virt((unsigned long)(x)));
>> +	return (void *)__phys_to_virt(x);
>>   }
>>
>>   /*
>>    * Drivers should NOT use these either.
>>    */
>>   #define __pa(x)			__virt_to_phys((unsigned long)(x))
>> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
>> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>>   #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
>
> This as a whole does not fill me with a great amount of enthusiasm,
> because it breaks some of the typechecking that we have here.
>
> The whole point of __phys_to_virt() and __virt_to_phys() is that they work
> on integer types, and warn if you dare to use them with pointers.  Adding
> a cast into them breaks that.
>

Understood.  Thanks.  The casts were needed to upgrade to 64-bit before 
arithmetic.  We should convert the non-patch __phys_to_virt and 
__virt_to_phys to inlines to keep the typechecking intact.

> The whole point is that the typecasting is explicitly inside phys_to_virt()
> and virt_to_phys() and not their macro counterparts.
>
> Secondly, are you sure that this patch is correct on its own?  You're
> passing a u64 into assembly only expecting a 32-bit register.  Have you
> checked it does the right thing with a 64-bit phys_addr_t on both LE
> and BE?
>

We should explicitly pass in the lower order bits here, at least until 
the next patch in the series fixes things up for 64-bit.  Thanks.

We've tested with 64-bit and 32-bit phys_addr_t, but only on LE.  Thanks 
for pointing this out, we'll figure out a way to run BE as well.

-- 
Thanks
- Cyril


From festevam at gmail.com  Mon Aug  6 09:36:32 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 10:36:32 -0300
Subject: [PATCH 1/1] mx27_3ds: Add sound support
In-Reply-To: <1344258447-6162-1-git-send-email-gcembed@gmail.com>
References: <1344258447-6162-1-git-send-email-gcembed@gmail.com>
Message-ID: <CAOMZO5B9ZmTHrYjVc5a7j=uUgUEyfDva54cKxBP3UeCYZsUWRw@mail.gmail.com>

Hi Ga?tan,

On Mon, Aug 6, 2012 at 10:07 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
> Hi,
> I have ported code "Enable sound on mx31_3ds" from Philippe R?tornaz to
> MX27 3DS platform on master branch of linux-next (tag next-20120806).
> I also applied patch "dma: imx-dma: Fix kernel crash due to missing clock
> conversion" of Fabio Estevam which is not yet merged in linux-next.
> Thanks to them, everything is working good on MX27 3DS platform except that
> sound is played too fast.
> Which parameter must be adjusted to have sound playing at normal speed ?
> In mc13783 codec driver, imx_add_imx_ssi(), clock configuration in
> mach-mx27_3ds file ?
>
> Thanks for your help.
>
> Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>

I have added audio support for mx27pdk:
https://patchwork.kernel.org/patch/1152951/

,and in my tests the audio was played at the correct rate.

Can you please have a try?

What is the sampling rate of your file?

Regards,

Fabio Estevam


From cyril at ti.com  Mon Aug  6 09:38:18 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Mon, 6 Aug 2012 09:38:18 -0400
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <20120806132642.GC18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <20120806111224.GA18957@n2100.arm.linux.org.uk> <501FC44E.1040806@ti.com>
 <20120806132642.GC18957@n2100.arm.linux.org.uk>
Message-ID: <501FC8CA.20303@ti.com>

On 8/6/2012 9:26 AM, Russell King - ARM Linux wrote:
> On Mon, Aug 06, 2012 at 09:19:10AM -0400, Cyril Chemparathy wrote:
>> With a flush_cache_all(), we could avoid having to operate a cacheline
>> at a time, but that clobbers way more than necessary.
>
> You can't do that, because flush_cache_all() on some CPUs requires the
> proper MMU mappings to be in place, and you can't get those mappings
> in place because you don't have the V:P offsets fixed up in the kernel.
> Welcome to the chicken and egg problem.
>
>> Sure, flushing caches is expensive.  But then, so is running the
>> patching code with caches disabled.  I guess memory access latencies
>> drive the performance trade off here.
>
> There we disagree on a few orders of magnitude.  There are relatively
> few places that need updating.  According to the kernel I have here:
>
>     text    data     bss     dec     hex filename
> 7644346  454320  212984 8311650  7ed362 vmlinux
>
> Idx Name          Size      VMA       LMA       File off  Algn
>    1 .text         004cd170  c00081c0  c00081c0  000081c0  2**5
>   16 .init.pv_table 00000300  c0753a24  c0753a24  00753a24  2**0
>
> That's about 7MB of text, and only 192 points in that code which need
> patching.  Even if we did this with caches on, that's still 192 places,
> and only 192 places we'd need to flush a cache line.
>
> Alternatively, with your approach and 7MB of text, you need to flush
> 238885 cache lines to cover the entire kernel.
>
> It would be far _cheaper_ with your approach to flush the individual
> cache lines as you go.
>

Agreed.  Thanks.

-- 
Thanks
- Cyril


From afzal at ti.com  Mon Aug  6 09:38:43 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 6 Aug 2012 13:38:43 +0000
Subject: gpmc generic retime function (subject was RE: [PATCH v5 3/3] ARM:
 OMAP2+: onenand: prepare for gpmc driver migration)
In-Reply-To: <20120711064724.GA1122@atomide.com>
References: <C8443D0743D26F4388EA172BF4E2A7A93E9A35E1@DBDE01.ent.ti.com>
 <20120705105535.GB1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A39DF@DBDE01.ent.ti.com>
 <20120706120533.GU1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A622E@DBDE01.ent.ti.com>
 <20120710094538.GT1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A64D0@DBDE01.ent.ti.com>
 <20120710131734.GV1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A669D@DBDE01.ent.ti.com>
 <4FFC6330.1040409@ti.com> <20120711064724.GA1122@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9B150D@DBDE01.ent.ti.com>

Hi Tony, Jon,

On Wed, Jul 11, 2012 at 12:17:25, Tony Lindgren wrote:
> * Jon Hunter <jon-hunter at ti.com> [120710 10:20]:

> > The DT node should simply have the information required by the retime
> > function or gpmc timings themselves if available. In the case of OneNAND

> > These can be stored in the DT and then translated to gpmc timings at
> > runtime. DT should only store static timing or clock information known

> Yup. And the format of the timing data in DT should be standardized so
> the only differences for each connected peripheral is the retime function.

If we are able to achieve a generic retime function applicable to all
peripherals then we don't need wrapper layer for retime handling or two
linux devices and drivers (one the existing and the other to handle retime)
to represent a single physical gpmc peripheral device (for DT conversion).
Then handling core frequency scaling and DT conversion would be easier.
We were trying to create such a retime function that would be generic so
as to handle different types of gpmc peripherals.

And we have been able to create such a function. Below is an implementation
that has been made for handling asynchronous timings. It has been tested for
OneNAND & SMSC on OMAP3EVM (rev G & C) with [1-4]. OneNAND was tested using
[5] (OMAP3EVM OneNAND works in async mode) & SMSC using [6] (mainline does
not have a timing calculation for smsc911x)

It was difficult to squeeze tusb6010 timing calculation into generic timing
calculation, hence a boolean "tusb" has been used. This is what I could
achieve based on existing retime for tusb6010 and for lack of tusb6010
timing specifications.

----8<-----------------------------------------------------------------------

/* Device timings in picoseconds */
struct gpmc_device_timings {
        u32     cs_setup;       /* CS setup time */
        u32     adv_setup;      /* ADV setup time */
        u32     adv_rd_off;     /* ADV read off time */
        u32     adv_add_hold;   /* address hold time */
        u32     oe_setup;       /* OE setup time */
        u32     adv_access;     /* access time from ADV assertion */
        u32     rd_access;      /* read access time */
        u32     oe_access;      /* access time from OE assertion */
        u32     cs_access;      /* access time from CS asertion */
        u32     rd_cycle;       /* read cycle time */
        u32     cs_highz;       /* CS deassertion to high Z */
        u32     oe_highz;       /* OE deassertion to high Z */
        u32     adv_wr_off;     /* ADV write off time */
        u32     we_setup;       /* WE setup time */
        u32     wr_pulse;       /* write assertion time */
        u32     wr_data_setup;  /* data setup time from write assertion */
        u32     wr_high;        /* write deassertion time */
        u32     we_highz;       /* WE deassertion to high Z */
        u32     wr_cycle;       /* write cycle time */

        bool    mux;            /* address & data muxed */
        bool    tusb;           /* peripheral is tusb6010 */
};

struct gpmc_timings gpmc_calc_timings(struct gpmc_device_timings *dev_t)
{
        struct gpmc_timings gpmc_t;
        bool mux = dev_t->mux;
        bool tusb = dev_t->tusb;
        u32 temp;

        memset(&gpmc_t, 0, sizeof(gpmc_t));

        /* cs_on */
        gpmc_t.cs_on = gpmc_round_ns_to_ticks(dev_t->cs_setup / 1000);

        /* adv_on */
        temp = dev_t->adv_setup;
        if (tusb)
                temp = max_t(u32,
                        (gpmc_t.cs_on + gpmc_ticks_to_ns(1)) * 1000, temp);
        gpmc_t.adv_on = gpmc_round_ns_to_ticks(temp / 1000);

        /* adv_rd_off */
        temp = dev_t->adv_rd_off;
        if (tusb)
                temp = max_t(u32,
                        (gpmc_t.adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
        gpmc_t.adv_rd_off = gpmc_round_ns_to_ticks(temp / 1000);

        /* oe_on */
        if (mux)
                temp = gpmc_t.adv_rd_off * 1000 + dev_t->adv_add_hold;
        else
                temp = dev_t->oe_setup;
        if (tusb)
                temp = max_t(u32,
                        (gpmc_t.adv_rd_off + gpmc_ticks_to_ns(1)) * 1000, temp);
        gpmc_t.oe_on = gpmc_round_ns_to_ticks(temp / 1000);

        /* access */
        temp = max_t(u32, dev_t->rd_access,
                                gpmc_t.oe_on * 1000 + dev_t->oe_access);
        temp = max_t(u32, temp,
                                gpmc_t.cs_on * 1000 + dev_t->cs_access);
        temp = max_t(u32, temp,
                                gpmc_t.adv_on * 1000 + dev_t->adv_access);
        if (tusb) {
                temp = max_t(u32, temp,
                                (gpmc_t.oe_on + gpmc_ticks_to_ns(1)) * 1000);
                temp = max_t(u32, temp, gpmc_t.oe_on * 1000 + 300);
        }
        gpmc_t.access = gpmc_round_ns_to_ticks(temp / 1000);

        gpmc_t.oe_off = gpmc_t.access + gpmc_ticks_to_ns(1);
        gpmc_t.cs_rd_off = gpmc_t.oe_off;

        /* rd_cycle */
        temp = max_t(u32, dev_t->rd_cycle,
                        gpmc_t.cs_rd_off * 1000 + dev_t->cs_highz);
        temp = max_t(u32, temp,
                        gpmc_t.oe_off * 1000 + dev_t->oe_highz);
        if (tusb) {
                temp = max_t(u32, temp,
                        (gpmc_t.cs_rd_off + gpmc_ticks_to_ns(1)) * 1000);
                temp = max_t(u32, temp, gpmc_t.cs_rd_off * 1000 + 7000);
        }
        gpmc_t.rd_cycle = gpmc_round_ns_to_ticks(temp / 1000);

        /* adv_wr_off */
        temp = dev_t->adv_wr_off;
        if (tusb)
                temp = max_t(u32,
                        (gpmc_t.adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
        gpmc_t.adv_wr_off = gpmc_round_ns_to_ticks(temp / 1000);

        /* we_on */
        if (mux)
                temp = gpmc_t.adv_wr_off * 1000 + dev_t->adv_add_hold;
        else
                temp = dev_t->we_setup;
        if (tusb)
                temp = max_t(u32,
                        (gpmc_t.adv_wr_off + gpmc_ticks_to_ns(1)) * 1000, temp);
        gpmc_t.we_on = gpmc_round_ns_to_ticks(temp / 1000);

        gpmc_t.wr_data_mux_bus = gpmc_t.we_on;

        /* we_off */
        temp = max_t(u32, gpmc_t.we_on * 1000 + dev_t->wr_pulse,
                        gpmc_t.we_on * 1000 + dev_t->wr_data_setup);
        if (tusb) {
                temp = max_t(u32, temp,
                                (gpmc_t.we_on + gpmc_ticks_to_ns(1)) * 1000);
                temp = max_t(u32, temp, gpmc_t.we_on * 1000 + 300);
        }
        gpmc_t.we_off = gpmc_round_ns_to_ticks(temp / 1000);

        gpmc_t.cs_wr_off = gpmc_round_ns_to_ticks((gpmc_t.we_off * 1000 +
                                dev_t->wr_high) / 1000);

        /* wr_cycle */
        temp = max_t(u32, dev_t->wr_cycle,
                        gpmc_t.cs_wr_off * 1000 + dev_t->cs_highz);
        temp = max_t(u32, temp,
                        gpmc_t.we_off * 1000 + dev_t->we_highz);
        if (tusb) {
                temp = max_t(u32, temp,
                        (gpmc_t.cs_wr_off + gpmc_ticks_to_ns(1)) * 1000);
                temp = max_t(u32, temp, gpmc_t.cs_wr_off * 1000 + 7000);
        }
        gpmc_t.wr_cycle = gpmc_round_ns_to_ticks(temp / 1000);

        return gpmc_t;
}

> > From a high-level I think that the goal should be ...
> > 
> > gpmc_probe
> > 	--> request CS
> > 	--> calls retime function to calculate gpmc timing (optional)
> > 	--> configures CS
> > 	--> registers peripheral device
> 
> Yes with few additions.. Connected peripheral probe requests CS from
> gpmc with the optional retime function pointer passed as a parameter.
> After gpmc code has determined the CS is available, it calls the optional
> retime function before returning back to the connected peripheral probe.
> 
> So how about the following with a bit more details:
> 
> gpmc_probe
> 	--> just sets up gpmc resources then idles itself
> 
> connected peripheral probe
> 	--> calls gpmc_cs_request() with gpmc timings from DT and an
> 	    optional retime function as a parameter
> 	--> gpmc_cs_request() allocates the CS
> 	--> gpmc_cs_request() calls the optional retime function and
> 	    if not specified, just sets the DT timings and disables
> 	    L3 DFS
> 	--> gpmc_cs_request() returns to connected peripheral probe

Once we are able to use the generic retime function as mentioned above,
instead of requiring additional driver for each peripheral that has
retime and its effect on complicating DT conversion,  we can have the
gpmc driver organization similar to the one that was posted
earlier[4].

With DT, we can pass peripheral timings that has been generalized as in 
gpmc_device_timings structure. In addition to timings, we would need
to have fields for specifying whether multiplexed or not ("mux" in
struct gpmc_device_timings), asynchronous or synchronous.

With the generic retime function, driver could do as follows,

gpmc_probe
  -> setup_device
    -> setup_cs
      ->setup_cs_config_timing
		if (gpmc_timings)
			gpmc_cs_set_timings(gpmc_t);
		else if (gpmc_device_timings) {
			gpmc_t = gpmc_calc_timings();
			gpmc_cs_set_timings(cs, &gpmc_t);
		}


In the above, addition to already posted driver series [4] would
be the "else if" portions.

For core DFS, we could register a notifier that would invoke,
	gpmc_t = gpmc_calc_timings(); /* defined above */
	gpmc_cs_set-timings(cs, &gpmc_t);
enabling us to have the gpmc timings adjusted.


Please let me know your comments on the above. Currently I am working
on achieving generalized timing for synchronous operations too so
that gpmc timings can be calculated at runtime using a single generic
retime function for all kinds of operations like mux, sync/async etc.

Regards
Afzal

[1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70096.html
[2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg71027.html
[3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg69881.html
[4] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70753.html

[5]
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index bbae674..fab21a1 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -50,6 +50,7 @@ static struct platform_device gpmc_onenand_device = {
 static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 {
        struct gpmc_timings t;
+       struct gpmc_device_timings dev_t;
 
        const int t_cer = 15;
        const int t_avdp = 12;
@@ -63,6 +64,24 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
        const int t_wph = 30;
 
        memset(&t, 0, sizeof(t));
+
+       memset(&dev_t, 0, sizeof(dev_t));
+       dev_t.cs_setup = 0;
+       dev_t.adv_setup = 0;
+       dev_t.adv_rd_off = 15 * 1000;
+       dev_t.adv_add_hold = 7 * 1000;
+       dev_t.adv_access = 76 * 1000;
+       dev_t.oe_access = 20 * 1000;
+       dev_t.cs_access = 76 * 1000;
+       dev_t.cs_highz = 20 * 1000;
+       dev_t.adv_wr_off = 15 * 1000;
+       dev_t.wr_pulse = 40 * 1000;
+       dev_t.wr_high = 30 * 1000;
+
+       dev_t.mux = true;
+
+       return gpmc_calc_timings(&dev_t);
+
        t.sync_clk = 0;
        t.cs_on = 0;
        t.adv_on = 0;

[6]

diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index b6c77be..53c7958 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -39,6 +39,50 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
 };
 
+static void gpmc_smsc911x_timing(struct omap_smsc911x_platform_data *gpmc_cfg)
+{
+       struct gpmc_timings t;
+       /* SMSC 9220 timings */
+       unsigned tcycle_r = 165;
+       unsigned tcsl_r = 32;
+       unsigned tcsh_r = 133;
+       unsigned tcsdv_r = 30;
+       unsigned tdoff_r = 9;
+       unsigned tcycle_w = 165;
+       unsigned tcsl_w = 32;
+       unsigned tcsh_w = 133;
+       unsigned tdsu_w = 7;
+       struct gpmc_device_timings dev_t;
+
+       memset(&t, sizeof(t), 0);
+
+       memset(&dev_t, sizeof(dev_t), 0);
+       dev_t.rd_access = tcsdv_r * 1000;
+       dev_t.rd_cycle = tcycle_r * 1000;
+       dev_t.wr_data_setup = tdsu_w * 1000;
+       dev_t.wr_pulse = tcsl_w * 1000;
+       dev_t.wr_cycle = tcycle_w * 1000;
+
+       t = gpmc_calc_timings(&dev_t);
+       gpmc_cs_set_timings(gpmc_cfg->cs, &t);
+       return;
+
+       t.cs_on = 0;
+       t.oe_on = 0;
+       t.access = tcsdv_r;
+       t.oe_off = max_t(unsigned, t.access + gpmc_ticks_to_ns(1), tcsl_r);
+       t.cs_rd_off = t.oe_off;
+       t.rd_cycle = tcsl_r + max(tcsh_r, tdoff_r);
+       t.rd_cycle = max_t(unsigned, tcycle_r, t.rd_cycle);
+
+       t.we_on = 0;
+       t.we_off = max(tcsl_w, tdsu_w);
+       t.cs_wr_off = t.we_off;
+       t.wr_cycle = max_t(unsigned, t.we_off + gpmc_ticks_to_ns(1), tcycle_w);
+
+       gpmc_cs_set_timings(gpmc_cfg->cs, &t);
+}
+
/*
  * Initialize smsc911x device connected to the GPMC. Note that we
  * assume that pin multiplexing is done in the board-*.c file,
@@ -81,6 +125,8 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
 
        gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
 
+       gpmc_smsc911x_timing(gpmc_cfg);
+
        pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
                 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
                 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));



From kishon at ti.com  Mon Aug  6 09:46:30 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 19:16:30 +0530
Subject: [PATCH v4 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <1344260791-6402-1-git-send-email-kishon@ti.com>
References: <1344260791-6402-1-git-send-email-kishon@ti.com>
Message-ID: <1344260791-6402-2-git-send-email-kishon@ti.com>

Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
USB2PHY is connected to ocp2scp.

This also includes device tree support for ocp2scp driver and
the documentation with device tree binding information is updated.

Acked-by: Felipe Balbi <balbi at ti.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 6 files changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
new file mode 100644
index 0000000..d2fe064
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -0,0 +1,10 @@
+* OMAP OCP2SCP - ocp interface to scp interface
+
+properties:
+- compatible : Should be "ti,omap-ocp2scp"
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ranges : the child address space are mapped 1:1 onto the parent address space
+- ti,hwmods : must be "ocp2scp_usb_phy"
+
+Sub-nodes:
+All the devices connected to ocp2scp are described using sub-node to ocp2scp
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ece958d..324e958 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -2,6 +2,8 @@ menu "Device Drivers"
 
 source "drivers/base/Kconfig"
 
+source "drivers/bus/Kconfig"
+
 source "drivers/connector/Kconfig"
 
 source "drivers/mtd/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 5b42184..f8cdeeb 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y				+= bus/
+
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
new file mode 100644
index 0000000..6270415
--- /dev/null
+++ b/drivers/bus/Kconfig
@@ -0,0 +1,15 @@
+#
+# Bus Devices
+#
+
+menu "Bus devices"
+
+config OMAP_OCP2SCP
+	tristate "OMAP OCP2SCP DRIVER"
+	help
+	  Driver to enable ocp2scp module which transforms ocp interface
+	  protocol to scp protocol. In OMAP4, USB PHY is connected via
+	  OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
+	  OCP2SCP.
+
+endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
new file mode 100644
index 0000000..0ec50bc
--- /dev/null
+++ b/drivers/bus/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the bus drivers.
+#
+
+obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
new file mode 100644
index 0000000..881d5bb
--- /dev/null
+++ b/drivers/bus/omap-ocp2scp.c
@@ -0,0 +1,88 @@
+/*
+ * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+static int ocp2scp_remove_devices(struct device *dev, void *c)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	platform_device_unregister(pdev);
+
+	return 0;
+}
+
+static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
+{
+	int			ret;
+	struct device_node	*np = pdev->dev.of_node;
+
+	if (np) {
+		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
+			goto err0;
+		}
+	}
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+
+err0:
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return ret;
+}
+
+static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_ocp2scp_id_table[] = {
+	{ .compatible = "ti,omap-ocp2scp" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
+static struct platform_driver omap_ocp2scp_driver = {
+	.probe		= omap_ocp2scp_probe,
+	.remove		= __devexit_p(omap_ocp2scp_remove),
+	.driver		= {
+		.name	= "omap-ocp2scp",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),
+	},
+};
+
+module_platform_driver(omap_ocp2scp_driver);
+
+MODULE_ALIAS("platform: omap-ocp2scp");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_DESCRIPTION("OMAP OCP2SCP driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:46:29 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 19:16:29 +0530
Subject: [PATCH v4 0/2] omap: add ocp2scp as a bus driver
Message-ID: <1344260791-6402-1-git-send-email-kishon@ti.com>

This patch series is done as a preparatory step for adding phy drivers
for dwc3 and musb.

This series adds a new driver for ocp2scp (only dt) to which phy
drivers are connected.

Since currently there is no generic way to create a child device along
with doing a pm_runtime_enable (the exact requirement for ocp2scp), I'm
creating a separate driver for ocp2scp.

Changes from v3:
No functional changes. Fixed few comments on filling *module* details.

Changes from v2:
Fixed Felipe's comments to avoid using arch_initcall and make dependent
drivers return -EPROBE_DEFER case this isn't ready yet.

Changes from v1:
Fixed Sergei's comments to remove the address in the node name of ocp2scp
since the ocp2scp node doesn't have a reg property.

Changes from [RFC PATCH v2 0/2] omap: add ocp2scp as a misc driver:
Created a new folder drivers/bus and moved ocp2scp driver from misc to
drivers/bus.

This patch was developed and tested on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git

Kishon Vijay Abraham I (2):
  drivers: bus: add a new driver for omap-ocp2scp
  arm/dts: omap4: Add ocp2scp data

 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 arch/arm/boot/dts/omap4.dtsi                       |    8 ++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 7 files changed, 130 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

-- 
1.7.9.5



From kishon at ti.com  Mon Aug  6 09:46:31 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Mon, 6 Aug 2012 19:16:31 +0530
Subject: [PATCH v4 2/2] arm/dts: omap4: Add ocp2scp data
In-Reply-To: <1344260791-6402-1-git-send-email-kishon@ti.com>
References: <1344260791-6402-1-git-send-email-kishon@ti.com>
Message-ID: <1344260791-6402-3-git-send-email-kishon@ti.com>

Add ocp2scp data node in omap4 device tree file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..8a780b2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,13 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
 		};
+
+		ocp2scp {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			ti,hwmods = "ocp2scp_usb_phy";
+		};
 	};
 };
-- 
1.7.9.5



From shawn.guo at linaro.org  Mon Aug  6 09:51:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 21:51:11 +0800
Subject: [PATCH 3/4] gpio/mxs: specify gpio base for device tree probe
In-Reply-To: <CACRpkdZz+F8gUGJG+d2mGrt8Rp0NzYypGdLEUbxmh=X1Q1cFhw@mail.gmail.com>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-3-git-send-email-shawn.guo@linaro.org>
 <CACRpkdZz+F8gUGJG+d2mGrt8Rp0NzYypGdLEUbxmh=X1Q1cFhw@mail.gmail.com>
Message-ID: <20120806135110.GA24289@S2101-09.ap.freescale.net>

On Sun, Aug 05, 2012 at 11:48:24AM +0200, Linus Walleij wrote:
> On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > Currently, unlike the non-DT probe where the gpio base is specified
> > with pdev->id, the DT probe uses the base dynamically allocated by
> > gpio core, which uses a completely different numbering scheme.  This
> > causes two issues to user space applications which access sysfs entry
> > /sys/class/gpio/gpioN.
> 
> Applied.
> 
Sorry, Linus.  I just recall gpio-mxs driver already reads alias to
assign port->id for DT boot at the beginning of probe function, and
this patch is completely a noise therefore.  So can you please drop
the patch from you branch?  Sorry again.

-- 
Regards,
Shawn



From tobetter at gmail.com  Mon Aug  6 09:57:39 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Mon,  6 Aug 2012 22:57:39 +0900
Subject: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor
In-Reply-To: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <1344261462-14183-2-git-send-email-dongjin.kim@agreeyamobility.net>

This patch assign the I2C channel for HDMIPHY for Exynos4x12
in s5p_i2c_hdmiphy_set_platdata() and s5p_hdmi_set_platdata()

Change-Id: I7e66c8f9327e2f7dce7440efb8583b506d65831a
Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/plat-samsung/devs.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index a199e55..54614d0 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -752,6 +752,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
 
 		if (soc_is_exynos4210())
 			pd->bus_num = 8;
+		else if (soc_is_exynos4212() || soc_is_exynos4412())
+			pd->bus_num = 8;
 		else if (soc_is_s5pv210())
 			pd->bus_num = 3;
 		else
@@ -771,6 +773,8 @@ void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
 
 	if (soc_is_exynos4210())
 		pd->hdmiphy_bus = 8;
+	else if (soc_is_exynos4212() || soc_is_exynos4412())
+		pd->hdmiphy_bus = 8;
 	else if (soc_is_s5pv210())
 		pd->hdmiphy_bus = 3;
 	else
-- 
1.7.9.5



From tobetter at gmail.com  Mon Aug  6 09:57:40 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Mon,  6 Aug 2012 22:57:40 +0900
Subject: [PATCH] ARM: EXYNOS: Add USB HSIC device
In-Reply-To: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <1344261462-14183-3-git-send-email-dongjin.kim@agreeyamobility.net>

This patch support to control USB HSIC of EXYNOS4,
edited based on Samsung's GT-i9100 ICS Opensource Update7.

Change-Id: Ifba33c6a5166abf3644794eee6abe528bd71f521
Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/mach-exynos/common.c                    |    5 +
 arch/arm/mach-exynos/include/mach/regs-pmu.h     |   12 +
 arch/arm/mach-exynos/include/mach/regs-usb-phy.h |   97 +++++
 arch/arm/mach-exynos/setup-usb-phy.c             |  493 ++++++++++++++++------
 drivers/usb/host/Kconfig                         |   14 +
 5 files changed, 501 insertions(+), 120 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..94d58af 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -179,6 +179,11 @@ static struct map_desc exynos4_iodesc[] __initdata = {
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO2,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
 		.virtual	= (unsigned long)S5P_VA_DMC0,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
 		.length		= SZ_64K,
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 0bb21e2..d98c2fe 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -185,6 +185,15 @@
 #define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
 
 /* Only for EXYNOS4x12 */
+#define S5P_USB_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define S5P_USB_PHY_ENABLE			(0x1 << 0)
+
+#define S5P_HSIC_1_PHY_CONTROL			S5P_PMUREG(0x0708)
+#define S5P_HSIC_1_PHY_ENABLE			(0x1 << 0)
+
+#define S5P_HSIC_2_PHY_CONTROL			S5P_PMUREG(0x070C)
+#define S5P_HSIC_2_PHY_ENABLE			(0x1 << 0)
+
 #define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
@@ -242,6 +251,9 @@
 
 #define EXYNOS5_SYS_WDTRESET					(1 << 20)
 
+#define EXYNOS5_USBDEV_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define EXYNOS5_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)
+
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index 0727773..79021a0 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -43,6 +43,43 @@
 #define EXYNOS4210_CLKSEL_12M		(0x2 << 0)
 #define EXYNOS4210_CLKSEL_24M		(0x3 << 0)
 
+#define EXYNOS4210_HSIC1_NORMAL_MASK            (0x3 << 11)
+#define EXYNOS4210_HSIC1_SLEEP                  (1 << 12)
+#define EXYNOS4210_HSIC1_FORCE_SUSPEND          (1 << 11)
+#define EXYNOS4210_HSIC0_NORMAL_MASK            (0x3 << 9)
+#define EXYNOS4210_HSIC0_SLEEP                  (1 << 10)
+#define EXYNOS4210_HSIC0_FORCE_SUSPEND          (1 << 9)
+
+#define EXYNOS4210_HOST_LINK_PORT_SWRST_MASK    (0xf << 6)
+#define EXYNOS4210_HOST_LINK_PORT2_SWRST        (1 << 9)
+#define EXYNOS4210_HOST_LINK_PORT1_SWRST        (1 << 8)
+#define EXYNOS4210_HOST_LINK_PORT0_SWRST        (1 << 7)
+#define EXYNOS4210_HOST_LINK_ALL_SWRST          (1 << 6)
+#define EXYNOS4210_PHY1_SWRST_MASK              (0x7 << 3)
+#define EXYNOS4210_PHY1_HSIC_SWRST              (1 << 5)
+#define EXYNOS4210_PHY1_STD_SWRST               (1 << 4)
+#define EXYNOS4210_PHY1_ALL_SWRST               (1 << 3)
+
+#define EXYNOS4X12_HSIC1_NORMAL_MASK		(0x7 << 12)
+#define EXYNOS4X12_HSIC1_SLEEP			(1 << 14)
+#define EXYNOS4X12_HSIC1_ANALOG_POWERDOWN	(1 << 13)
+#define EXYNOS4X12_HSIC1_FORCE_SUSPEND		(1 << 12)
+#define EXYNOS4X12_HSIC0_NORMAL_MASK		(0x7 << 9)
+#define EXYNOS4X12_HSIC0_SLEEP			(1 << 11)
+#define EXYNOS4X12_HSIC0_ANALOG_POWERDOWN	(1 << 10)
+#define EXYNOS4X12_HSIC0_FORCE_SUSPEND		(1 << 9)
+
+#define EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK	(0xf << 7)
+#define EXYNOS4X12_HOST_LINK_PORT2_SWRST	(1 << 10)
+#define EXYNOS4X12_HOST_LINK_PORT1_SWRST	(1 << 9)
+#define EXYNOS4X12_HOST_LINK_PORT0_SWRST	(1 << 8)
+#define EXYNOS4X12_HOST_LINK_ALL_SWRST		(1 << 7)
+#define EXYNOS4X12_PHY1_SWRST_MASK		(0xf << 3)
+#define EXYNOS4X12_PHY1_HSIC1_SWRST		(1 << 6)
+#define EXYNOS4X12_PHY1_HSIC0_SWRST		(1 << 5)
+#define EXYNOS4X12_PHY1_SWRST			(1 << 4)
+#define EXYNOS4X12_HOST_PHY_SWRST		(1 << 3)
+
 #define EXYNOS4X12_CLKSEL_MASK		(0x7 << 0)
 #define EXYNOS4X12_CLKSEL_9600K		(0x0 << 0)
 #define EXYNOS4X12_CLKSEL_10M		(0x1 << 0)
@@ -71,4 +108,64 @@
 #define EXYNOS4_PHY1CON			EXYNOS4_HSOTG_PHYREG(0x34)
 #define FPENABLEN			(1 << 0)
 
+/* For Exynos5 */
+#define EXYNOS5_PHY_HOST_CTRL0                  EXYNOS4_HSOTG_PHYREG(0x00)
+#define HOST_CTRL0_PHYSWRSTALL                  (0x1 << 31)
+#define HOST_CTRL0_REFCLKSEL(val)               (val << 19)
+#define EXYNOS5_CLKSEL_50M                      (0x7)
+#define EXYNOS5_CLKSEL_24M                      (0x5)
+#define EXYNOS5_CLKSEL_20M                      (0x4)
+#define EXYNOS5_CLKSEL_19200K                   (0x3)
+#define EXYNOS5_CLKSEL_12M                      (0x2)
+#define EXYNOS5_CLKSEL_10M                      (0x1)
+#define EXYNOS5_CLKSEL_9600K                    (0x0)
+#define HOST_CTRL0_CLKSEL_SHIFT                 (16)
+#define HOST_CTRL0_FSEL_MASK                    (0x7 << 16)
+
+#define HOST_CTRL0_COMMONON_N                   (0x1 << 9)
+#define HOST_CTRL0_SIDDQ                        (0x1 << 6)
+#define HOST_CTRL0_FORCESLEEP                   (0x1 << 5)
+#define HOST_CTRL0_FORCESUSPEND                 (0x1 << 4)
+#define HOST_CTRL0_WORDINTERFACE                (0x1 << 3)
+#define HOST_CTRL0_UTMISWRST                    (0x1 << 2)
+#define HOST_CTRL0_LINKSWRST                    (0x1 << 1)
+#define HOST_CTRL0_PHYSWRST                     (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_TUNE0                  EXYNOS4_HSOTG_PHYREG(0x04)
+#define EXYNOS5_PHY_HOST_TEST0                  EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define EXYNOS5_PHY_HSIC_CTRL1                  EXYNOS4_HSOTG_PHYREG(0x10)
+#define EXYNOS5_PHY_HSIC_CTRL2                  EXYNOS4_HSOTG_PHYREG(0x20)
+#define HSIC_CTRL_REFCLKSEL(val)                ((val&0x3) << 23)
+#define HSIC_CTRL_REFCLKDIV(val)                ((val&0x7f) << 16)
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_WORDINTERFACE                 (0x1 << 3)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_EHCICTRL               EXYNOS4_HSOTG_PHYREG(0x30)
+#define EHCICTRL_ENAINCRXALIGN                  (0x1 << 29)
+#define EHCICTRL_ENAINCR4                       (0x1 << 28)
+#define EHCICTRL_ENAINCR8                       (0x1 << 27)
+#define EHCICTRL_ENAINCR16                      (0x1 << 26)
+
+#define EXYNOS5_PHY_HOST_OHCICTRL               EXYNOS4_HSOTG_PHYREG(0x34)
+
+#define EXYNOS5_PHY_OTG_SYS                     EXYNOS4_HSOTG_PHYREG(0x38)
+#define OTG_SYS_PHYLINK_SW_RESET                (0x1 << 14)
+#define OTG_SYS_LINK_SW_RST_UOTG                (0x1 << 13)
+#define OTG_SYS_PHY0_SW_RST                     (0x1 << 12)
+#define OTG_SYS_REF_CLK_SEL(val)                ((val&0x3) << 9)
+#define OTG_SYS_REF_CLK_SEL_MASK                (0x3 << 9)
+#define OTG_SYS_IP_PULLUP_UOTG                  (0x1 << 8)
+#define OTG_SYS_COMMON_ON                       (0x1 << 7)
+#define OTG_SYS_CLKSEL_SHIFT                    (4)
+#define OTG_SYS_CTRL0_FSEL_MASK                 (0x7 << 4)
+#define OTG_SYS_FORCE_SLEEP                     (0x1 << 3)
+#define OTG_SYS_OTGDISABLE                      (0x1 << 2)
+#define OTG_SYS_SIDDQ_UOTG                      (0x1 << 1)
+#define OTG_SYS_FORCE_SUSPEND                   (0x1 << 0)
+
 #endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..c725745 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim at samsung.com>
  * Author: Joonyoung Shim <jy0922.shim at samsung.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -19,205 +20,457 @@
 #include <plat/cpu.h>
 #include <plat/usb-phy.h>
 
+#define ETC6PUD		(S5P_VA_GPIO2 + 0x228)
+#define EXYNOS4_USB_CFG	(S3C_VA_SYS + 0x21C)
+
+#define PHY_ENABLE	(1 << 0)
+#define PHY_DISABLE	(0)
+
+enum usb_host_type {
+	HOST_PHY_EHCI	= (0x1 << 0),
+	HOST_PHY_OHCI	= (0x1 << 1),
+};
+
+enum usb_phy_type {
+	USB_PHY		= (0x1 << 0),
+	USB_PHY0	= (0x1 << 0),
+	USB_PHY1	= (0x1 << 1),
+	USB_PHY_HSIC0	= (0x1 << 1),
+	USB_PHY_HSIC1	= (0x1 << 2),
+};
+
 static atomic_t host_usage;
+static DEFINE_MUTEX(phy_lock);
+static struct clk *phy_clk;
 
 static int exynos4_usb_host_phy_is_on(void)
 {
 	return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
 }
 
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
+static int exynos4_usb_phy20_is_on(void)
 {
-	struct clk *xusbxti_clk;
-	u32 phyclk;
+	return exynos4_usb_host_phy_is_on();
+}
+
+static int exynos_usb_phy_clock_enable(struct platform_device *pdev)
+{
+	int err;
+
+	if (!phy_clk) {
+		if (soc_is_exynos4210() ||
+				soc_is_exynos4212() || soc_is_exynos4412())
+			phy_clk = clk_get(&pdev->dev, "otg");
+		else
+			phy_clk = clk_get(&pdev->dev, "usbhost");
+
+		if (IS_ERR(phy_clk)) {
+			dev_err(&pdev->dev, "Failed to get phy clock\n");
+			return PTR_ERR(phy_clk);
+		}
+	}
+
+	err = clk_enable(phy_clk);
+
+	return err;
+}
 
-	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-		if (soc_is_exynos4210()) {
-			/* set clock frequency for PLL */
-			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
-
-			switch (clk_get_rate(xusbxti_clk)) {
-			case 12 * MHZ:
-				phyclk |= EXYNOS4210_CLKSEL_12M;
-				break;
-			case 48 * MHZ:
-				phyclk |= EXYNOS4210_CLKSEL_48M;
-				break;
-			default:
-			case 24 * MHZ:
-				phyclk |= EXYNOS4210_CLKSEL_24M;
-				break;
-			}
-			writel(phyclk, EXYNOS4_PHYCLK);
-		} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-			/* set clock frequency for PLL */
-			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
-
-			switch (clk_get_rate(xusbxti_clk)) {
-			case 9600 * KHZ:
-				phyclk |= EXYNOS4X12_CLKSEL_9600K;
-				break;
-			case 10 * MHZ:
-				phyclk |= EXYNOS4X12_CLKSEL_10M;
-				break;
-			case 12 * MHZ:
-				phyclk |= EXYNOS4X12_CLKSEL_12M;
-				break;
-			case 19200 * KHZ:
-				phyclk |= EXYNOS4X12_CLKSEL_19200K;
-				break;
-			case 20 * MHZ:
-				phyclk |= EXYNOS4X12_CLKSEL_20M;
-				break;
-			default:
-			case 24 * MHZ:
-				/* default reference clock */
-				phyclk |= EXYNOS4X12_CLKSEL_24M;
-				break;
-			}
-			writel(phyclk, EXYNOS4_PHYCLK);
+static int exynos_usb_phy_clock_disable(struct platform_device *pdev)
+{
+	if (!phy_clk) {
+		if (soc_is_exynos4210() ||
+				soc_is_exynos4212() || soc_is_exynos4412())
+			phy_clk = clk_get(&pdev->dev, "otg");
+		else
+			phy_clk = clk_get(&pdev->dev, "usbhost");
+		if (IS_ERR(phy_clk)) {
+			dev_err(&pdev->dev, "Failed to get phy clock\n");
+			return PTR_ERR(phy_clk);
 		}
-		clk_put(xusbxti_clk);
 	}
+
+	clk_disable(phy_clk);
+
+	return 0;
 }
 
-static int exynos4210_usb_phy0_init(struct platform_device *pdev)
+static u32 exynos_usb_phy_set_clock(struct platform_device *pdev)
 {
+	struct clk *ref_clk;
+	u32 refclk_freq = 0;
+
+	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+		ref_clk = clk_get(&pdev->dev, "xusbxti");
+	else
+		ref_clk = clk_get(&pdev->dev, "ext_xtal");
+
+	if (IS_ERR(ref_clk)) {
+		dev_err(&pdev->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	if (soc_is_exynos4210()) {
+		switch (clk_get_rate(ref_clk)) {
+		case 12 * MHZ:
+			refclk_freq = EXYNOS4210_CLKSEL_12M;
+			break;
+		case 48 * MHZ:
+			refclk_freq = EXYNOS4210_CLKSEL_48M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS4210_CLKSEL_24M;
+			break;
+		}
+	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
+		switch (clk_get_rate(ref_clk)) {
+		case 96 * 100000:
+			refclk_freq = EXYNOS4X12_CLKSEL_9600K;
+			break;
+		case 10 * MHZ:
+			refclk_freq = EXYNOS4X12_CLKSEL_10M;
+			break;
+		case 12 * MHZ:
+			refclk_freq = EXYNOS4X12_CLKSEL_12M;
+			break;
+		case 192 * 100000:
+			refclk_freq = EXYNOS4X12_CLKSEL_19200K;
+			break;
+		case 20 * MHZ:
+			refclk_freq = EXYNOS4X12_CLKSEL_20M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS4X12_CLKSEL_24M;
+			break;
+		}
+	} else {
+		switch (clk_get_rate(ref_clk)) {
+		case 96 * 100000:
+			refclk_freq = EXYNOS5_CLKSEL_9600K;
+			break;
+		case 10 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_10M;
+			break;
+		case 12 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_12M;
+			break;
+		case 192 * 100000:
+			refclk_freq = EXYNOS5_CLKSEL_19200K;
+			break;
+		case 20 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_20M;
+			break;
+		case 50 * MHZ:
+			refclk_freq = EXYNOS5_CLKSEL_50M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq = EXYNOS5_CLKSEL_24M;
+			break;
+		}
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
+{
+	if (soc_is_exynos4210()) {
+		if (phy_type & USB_PHY0)
+			writel(on, S5P_USBDEVICE_PHY_CONTROL);
+		if (phy_type & USB_PHY1)
+			writel(on, S5P_USBHOST_PHY_CONTROL);
+	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
+		if (phy_type & USB_PHY)
+			writel(on, S5P_USB_PHY_CONTROL);
+#ifdef CONFIG_USB_S5P_HSIC0
+		if (phy_type & USB_PHY_HSIC0)
+			writel(on, S5P_HSIC_1_PHY_CONTROL);
+#endif
+#ifdef CONFIG_USB_S5P_HSIC1
+		if (phy_type & USB_PHY_HSIC1)
+			writel(on, S5P_HSIC_2_PHY_CONTROL);
+#endif
+	} else {
+		if (phy_type & USB_PHY0)
+			writel(on, EXYNOS5_USBDEV_PHY_CONTROL);
+		if (phy_type & USB_PHY1)
+			writel(on, EXYNOS5_USBHOST_PHY_CONTROL);
+	}
+}
+
+static int exynos4_usb_phy0_init(struct platform_device *pdev)
+{
+	u32 phypwr;
+	u32 phyclk;
 	u32 rstcon;
 
-	writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
-			S5P_USBDEVICE_PHY_CONTROL);
+	exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
 
-	exynos4210_usb_phy_clkset(pdev);
+	/* set clock frequency for PLL */
+	phyclk = exynos_usb_phy_set_clock(pdev);
+	phyclk &= ~(PHY0_COMMON_ON_N);
+	writel(phyclk, EXYNOS4_PHYCLK);
 
-	/* set to normal PHY0 */
-	writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
+	/* set to normal of PHY0 */
+	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
 
-	/* reset PHY0 and Link */
+	/* reset all ports of both PHY and Link */
 	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
 	writel(rstcon, EXYNOS4_RSTCON);
 	udelay(10);
-
 	rstcon &= ~PHY0_SWRST_MASK;
 	writel(rstcon, EXYNOS4_RSTCON);
 
 	return 0;
 }
 
-static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
+static int exynos4_usb_phy0_exit(struct platform_device *pdev)
 {
-	writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
-				PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
+	/* unset to normal of PHY0 */
+	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
+			EXYNOS4_PHYPWR);
 
-	writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
-			S5P_USBDEVICE_PHY_CONTROL);
+	exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
 
 	return 0;
 }
 
-static int exynos4210_usb_phy1_init(struct platform_device *pdev)
+static int exynos4_usb_phy1_init(struct platform_device *pdev)
 {
-	struct clk *otg_clk;
+	u32 phypwr;
+	u32 phyclk;
 	u32 rstcon;
-	int err;
 
 	atomic_inc(&host_usage);
 
-	otg_clk = clk_get(&pdev->dev, "otg");
-	if (IS_ERR(otg_clk)) {
-		dev_err(&pdev->dev, "Failed to get otg clock\n");
-		return PTR_ERR(otg_clk);
+	if (exynos4_usb_host_phy_is_on()) {
+		dev_err(&pdev->dev, "Already power on PHY\n");
+		return 0;
 	}
 
-	err = clk_enable(otg_clk);
-	if (err) {
-		clk_put(otg_clk);
-		return err;
-	}
+	/*
+	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
+	 *  0x0 : pull-up/down disabled
+	 *  0x1 : pull-down enabled
+	 *  0x2 : reserved
+	 *  0x3 : pull-up enabled
+	 */
+	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
+		ETC6PUD);
 
-	if (exynos4_usb_host_phy_is_on())
-		return 0;
+	exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
 
-	writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
-			S5P_USBHOST_PHY_CONTROL);
+	/* set clock frequency for PLL */
+	phyclk = exynos_usb_phy_set_clock(pdev);
+	phyclk &= ~(PHY1_COMMON_ON_N);
+	writel(phyclk, EXYNOS4_PHYCLK);
 
-	exynos4210_usb_phy_clkset(pdev);
+	/* set to normal HSIC 0 and 1 of PHY1 */
+	phypwr = readl(EXYNOS4_PHYPWR);
+	phypwr &= ~(PHY1_STD_NORMAL_MASK
+		| EXYNOS4210_HSIC0_NORMAL_MASK);
+	writel(phypwr, EXYNOS4_PHYPWR);
 
 	/* floating prevention logic: disable */
 	writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
 
-	/* set to normal HSIC 0 and 1 of PHY1 */
-	writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
-			EXYNOS4_PHYPWR);
-
-	/* set to normal standard USB of PHY1 */
-	writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
-
 	/* reset all ports of both PHY and Link */
-	rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
-		PHY1_SWRST_MASK;
+	rstcon = readl(EXYNOS4_RSTCON)
+		| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4210_PHY1_SWRST_MASK;
 	writel(rstcon, EXYNOS4_RSTCON);
 	udelay(10);
 
-	rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
+	rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4210_PHY1_SWRST_MASK);
 	writel(rstcon, EXYNOS4_RSTCON);
 	udelay(80);
 
-	clk_disable(otg_clk);
-	clk_put(otg_clk);
+	return 0;
+}
+
+static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+{
+	u32 phypwr;
+
+	if (atomic_dec_return(&host_usage) > 0) {
+		dev_info(&pdev->dev, "still being used\n");
+		return -EBUSY;
+	}
+
+	phypwr = readl(EXYNOS4_PHYPWR)
+		| PHY1_STD_NORMAL_MASK
+		| EXYNOS4210_HSIC0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
 
 	return 0;
 }
 
-static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
+static int exynos4_usb_phy20_init(struct platform_device *pdev)
 {
-	struct clk *otg_clk;
-	int err;
+	u32 phypwr, phyclk, rstcon;
 
-	if (atomic_dec_return(&host_usage) > 0)
-		return 0;
+	atomic_inc(&host_usage);
 
-	otg_clk = clk_get(&pdev->dev, "otg");
-	if (IS_ERR(otg_clk)) {
-		dev_err(&pdev->dev, "Failed to get otg clock\n");
-		return PTR_ERR(otg_clk);
+	if (exynos4_usb_phy20_is_on()) {
+		dev_err(&pdev->dev, "Already power on PHY\n");
+		return 0;
 	}
 
-	err = clk_enable(otg_clk);
-	if (err) {
-		clk_put(otg_clk);
-		return err;
+	/*
+	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
+	 *  0x0 : pull-up/down disabled
+	 *  0x1 : pull-down enabled
+	 *  0x2 : reserved
+	 *  0x3 : pull-up enabled
+	 */
+	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
+		ETC6PUD);
+
+	exynos_usb_phy_control(USB_PHY
+		| USB_PHY_HSIC0,
+		PHY_ENABLE);
+
+	/* set clock frequency for PLL */
+	phyclk = exynos_usb_phy_set_clock(pdev);
+	/* COMMON Block configuration during suspend */
+	phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N);
+	writel(phyclk, EXYNOS4_PHYCLK);
+
+	/* set to normal of Device */
+	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* set to normal of Host */
+	phypwr = readl(EXYNOS4_PHYPWR);
+	phypwr &= ~(PHY1_STD_NORMAL_MASK
+		| EXYNOS4X12_HSIC0_NORMAL_MASK);
+	writel(phypwr, EXYNOS4_PHYPWR);
+
+	/* reset both PHY and Link of Device */
+	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+	rstcon &= ~PHY0_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+
+	/* reset both PHY and Link of Host */
+	rstcon = readl(EXYNOS4_RSTCON)
+		| EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4X12_PHY1_SWRST_MASK;
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(10);
+
+	rstcon &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
+		| EXYNOS4X12_PHY1_SWRST_MASK);
+	writel(rstcon, EXYNOS4_RSTCON);
+	udelay(80);
+
+	return 0;
+}
+
+static int exynos4_usb_phy20_exit(struct platform_device *pdev)
+{
+	u32 phypwr;
+
+	if (atomic_dec_return(&host_usage) > 0) {
+		dev_info(&pdev->dev, "still being used\n");
+		return -EBUSY;
 	}
 
-	writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
+	/* unset to normal of Device */
+	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
 			EXYNOS4_PHYPWR);
 
-	writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
-			S5P_USBHOST_PHY_CONTROL);
+	/* unset to normal of Host */
+	phypwr = readl(EXYNOS4_PHYPWR)
+		| PHY1_STD_NORMAL_MASK
+		| EXYNOS4X12_HSIC0_NORMAL_MASK;
+	writel(phypwr, EXYNOS4_PHYPWR);
 
-	clk_disable(otg_clk);
-	clk_put(otg_clk);
+	exynos_usb_phy_control(USB_PHY
+		| USB_PHY_HSIC0,
+		PHY_DISABLE);
+
+	return 0;
+}
+
+static int exynos_usb_dev_phy20_init(struct platform_device *pdev)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412())
+		exynos4_usb_phy20_init(pdev);
+
+	writel(0, EXYNOS4_USB_CFG);
+
+	return 0;
+}
+
+static int exynos_usb_dev_phy20_exit(struct platform_device *pdev)
+{
+	if (soc_is_exynos4212() || soc_is_exynos4412())
+		exynos4_usb_phy20_exit(pdev);
 
 	return 0;
 }
 
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
-	if (type == S5P_USB_PHY_DEVICE)
-		return exynos4210_usb_phy0_init(pdev);
-	else if (type == S5P_USB_PHY_HOST)
-		return exynos4210_usb_phy1_init(pdev);
+	int ret = -EINVAL;
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return ret;
+
+	mutex_lock(&phy_lock);
+	if (type == S5P_USB_PHY_HOST) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy1_init(pdev);
+		else if (soc_is_exynos4212() || soc_is_exynos4412())
+			ret = exynos4_usb_phy20_init(pdev);
+	} else if (type == S5P_USB_PHY_DEVICE) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_init(pdev);
+		else
+			ret = exynos_usb_dev_phy20_init(pdev);
+	}
+
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
 
-	return -EINVAL;
+	return ret;
 }
 
 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 {
-	if (type == S5P_USB_PHY_DEVICE)
-		return exynos4210_usb_phy0_exit(pdev);
-	else if (type == S5P_USB_PHY_HOST)
-		return exynos4210_usb_phy1_exit(pdev);
+	int ret = -EINVAL;
+
+	if (exynos_usb_phy_clock_enable(pdev))
+		return ret;
+
+	mutex_lock(&phy_lock);
+
+	if (type == S5P_USB_PHY_HOST) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy1_exit(pdev);
+		else if (soc_is_exynos4212() || soc_is_exynos4412())
+			ret = exynos4_usb_phy20_exit(pdev);
+	} else if (type == S5P_USB_PHY_DEVICE) {
+		if (soc_is_exynos4210())
+			ret = exynos4_usb_phy0_exit(pdev);
+		else
+			ret = exynos_usb_dev_phy20_exit(pdev);
+	}
+
+	mutex_unlock(&phy_lock);
+	exynos_usb_phy_clock_disable(pdev);
 
-	return -EINVAL;
+	return ret;
 }
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 075d2ec..5f69041 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -199,6 +199,20 @@ config USB_EHCI_S5P
        help
 	 Enable support for the S5P SOC's on-chip EHCI controller.
 
+config USB_S5P_HSIC0
+    boolean "S5P HSIC0 support"
+    depends on USB_EHCI_HCD && PLAT_S5P && USB_EHCI_S5P
+    default n
+    help
+      Enable support for the S5P SOC's on-chip HSIC PHY.
+
+config USB_S5P_HSIC1
+    boolean "S5P HSIC1 support"
+    depends on USB_EHCI_HCD && PLAT_S5P && USB_EHCI_S5P
+    default n
+    help
+      Enable support for the S5P SOC's on-chip HSIC PHY.
+
 config USB_EHCI_MV
 	bool "EHCI support for Marvell on-chip controller"
 	depends on USB_EHCI_HCD && (ARCH_PXA || ARCH_MMP)
-- 
1.7.9.5



From tobetter at gmail.com  Mon Aug  6 09:57:41 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Mon,  6 Aug 2012 22:57:41 +0900
Subject: [PATCH] ARM: EXYNOS: Enable multiple cores on Exynos4
In-Reply-To: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <1344261462-14183-4-git-send-email-dongjin.kim@agreeyamobility.net>

This patch enables CPU cores on Exynos4, on Exynos4412 secondary CPU cores
are power-gated, therefore we must turn on the CPU cores on the system boot.

Shows below log message on boot.
[    0.045000] CPU: Testing write buffer coherency: ok
[    0.045000] CPU0: thread -1, cpu 0, socket 10, mpidr 80000a00
[    0.045000] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7
counters e
[    0.045000] Setting up static identity map for 0x40370790 - 0x403707e8
[    0.045000] L310 cache controller enabled
[    0.045000] l2x0: 16 ways, CACHE_ID 0x4100c4c8, AUX_CTRL 0x7e470001, Cache
sizeB
[    0.070000] CPU1: Booted secondary processor
[    0.090000] CPU1: thread -1, cpu 1, socket 10, mpidr 80000a01
[    0.090000] CPU1: Unknown IPI message 0x1
[    0.100000] CPU2: Booted secondary processor
[    0.120000] CPU2: thread -1, cpu 2, socket 10, mpidr 80000a02
[    0.120000] CPU2: Unknown IPI message 0x1
[    0.130000] CPU3: Booted secondary processor
[    0.150000] CPU3: thread -1, cpu 3, socket 10, mpidr 80000a03
[    0.150000] CPU3: Unknown IPI message 0x1
[    0.150000] Brought up 4 CPUs
[    0.150000] SMP: Total of 4 processors activated (7969.17 BogoMIPS).

Change-Id: I61615c5b719d3646698f114fc3777eb304694099
Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/mach-exynos/hotplug.c               |    4 +-
 arch/arm/mach-exynos/include/mach/regs-pmu.h |   11 ++-
 arch/arm/mach-exynos/platsmp.c               |  100 +++++++++++++++++---------
 3 files changed, 76 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 9c17a0a..cd53497 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -66,8 +66,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 	for (;;) {
 
 		/* make cpu1 to be turned off at next WFI command */
-		if (cpu == 1)
-			__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+		if ((cpu >= 1) && (cpu < num_possible_cpus()))
+			__raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpu));
 
 		/*
 		 * here's the WFI
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index d4e392b..0bb21e2 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -123,10 +123,15 @@
 #define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)
 
 #define S5P_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS			S5P_PMUREG(0x2004)
 #define S5P_ARM_CORE0_OPTION			S5P_PMUREG(0x2008)
-#define S5P_ARM_CORE1_CONFIGURATION		S5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS			S5P_PMUREG(0x2084)
-#define S5P_ARM_CORE1_OPTION			S5P_PMUREG(0x2088)
+
+#define S5P_ARM_CORE_OPTION(_nr)	(S5P_ARM_CORE0_OPTION + ((_nr) * 0x80))
+#define S5P_ARM_CORE_STATUS(_nr)	(S5P_ARM_CORE0_STATUS + ((_nr) * 0x80))
+#define S5P_ARM_CORE_CONFIGURATION(_nr)	\
+				(S5P_ARM_CORE0_CONFIGURATION + ((_nr) * 0x80))
+
+#define S5P_CORE_OPTION_DIS                     (1 << 8)
 
 #define S5P_ARM_COMMON_OPTION			S5P_PMUREG(0x2408)
 #define S5P_TOP_PWR_OPTION			S5P_PMUREG(0x2C48)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..68ca26f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,9 +34,6 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-				S5P_INFORM5 : S5P_VA_SYSRAM)
-
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
@@ -59,6 +56,9 @@ static void write_pen_release(int val)
 
 static void __iomem *scu_base_addr(void)
 {
+	if (soc_is_exynos5250())
+		return 0;
+
 	return (void __iomem *)(S5P_VA_SCU);
 }
 
@@ -86,9 +86,41 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	spin_unlock(&boot_lock);
 }
 
+static int exynos_power_up_cpu(unsigned int cpu)
+{
+	unsigned long timeout;
+	unsigned int val;
+	void __iomem *power_base = S5P_ARM_CORE_CONFIGURATION(cpu);
+
+	val = __raw_readl(power_base);
+	if (!(val & S5P_CORE_LOCAL_PWR_EN)) {
+		__raw_writel(S5P_CORE_LOCAL_PWR_EN, power_base);
+
+		timeout = 10;
+
+		/* wait max 10 ms until cpu is on */
+		while ((__raw_readl(power_base + 0x4)
+			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+			if (timeout-- == 0)
+				break;
+
+			mdelay(1);
+		}
+
+		if (timeout == 0) {
+			pr_err("cpu%d power enable failed", cpu);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
+	void __iomem *boot_base;
+	int ret;
 
 	/*
 	 * Set synchronisation state between this boot processor
@@ -96,6 +128,12 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	spin_lock(&boot_lock);
 
+	ret = exynos_power_up_cpu(cpu);
+	if (ret) {
+		spin_unlock(&boot_lock);
+		return ret;
+	}
+
 	/*
 	 * The secondary processor is waiting to be released from
 	 * the holding pen - release it, then wait for it to flag
@@ -106,39 +144,33 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	write_pen_release(cpu_logical_map(cpu));
 
-	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
-		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-			     S5P_ARM_CORE1_CONFIGURATION);
-
-		timeout = 10;
-
-		/* wait max 10 ms until cpu1 is on */
-		while ((__raw_readl(S5P_ARM_CORE1_STATUS)
-			& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
-			if (timeout-- == 0)
-				break;
-
-			mdelay(1);
-		}
-
-		if (timeout == 0) {
-			printk(KERN_ERR "cpu1 power enable failed");
-			spin_unlock(&boot_lock);
-			return -ETIMEDOUT;
-		}
-	}
 	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
 		smp_rmb();
 
+		if (soc_is_exynos4210() &&
+				(samsung_rev() == EXYNOS4210_REV_1_1))
+			boot_base = S5P_INFORM5;
+		else
+			boot_base = S5P_VA_SYSRAM;
+
+		if (soc_is_exynos4412())
+			boot_base += (0x4 * cpu);
+
+		/*
+		 * Write the address of secondary startup into the
+		 * system-wide flags register. The boot monitor waits
+		 * until it receives a soft interrupt, and then the
+		 * secondary CPU branches to this address.
+		 */
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+				boot_base);
+
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
@@ -186,15 +218,15 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-	if (!soc_is_exynos5250())
-		scu_enable(scu_base_addr());
+	int i;
 
 	/*
-	 * Write the address of secondary startup into the
-	 * system-wide flags register. The boot monitor waits
-	 * until it receives a soft interrupt, and then the
-	 * secondary CPU branches to this address.
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	if (!soc_is_exynos5250())
+		scu_enable(scu_base_addr());
 }
-- 
1.7.9.5



From linus.walleij at linaro.org  Mon Aug  6 10:00:04 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 Aug 2012 16:00:04 +0200
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.
In-Reply-To: <1344255947-10062-1-git-send-email-lee.jones@linaro.org>
References: <1344255947-10062-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZoJxyZX6SOcAvBP4NBmGyUEiyLH_n_RzSDTBsjS13zug@mail.gmail.com>

On Mon, Aug 6, 2012 at 2:25 PM, Lee Jones <lee.jones at linaro.org> wrote:

> At this moment in time there is only one known configuration for the
> Nomadik I2C driver. By not holding that configuration in the driver
> adds some unnecessary overhead in platform code. The configuration
> as already been removed from platform code, this patch checks for any
> over-riding configurations. If there aren't any, the default is used.
>
> Cc: linux-i2c at vger.kernel.org
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This still does not apply for me on v3.6-rc1 what did you base
this patch on?

Applying: i2c: Add default configuration into the Nomadik I2C driver.
error: patch failed: drivers/i2c/busses/i2c-nomadik.c:899
error: drivers/i2c/busses/i2c-nomadik.c: patch does not apply
Patch failed at 0001 i2c: Add default configuration into the Nomadik I2C driver.
When you have resolved this problem run "git am --resolved".
If you would prefer to skip this patch, instead run "git am --skip".
To restore the original branch and stop patching run "git am --abort".

Yours,
Linus Walleij


From arnd at arndb.de  Mon Aug  6 10:02:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 14:02:22 +0000
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <201208061402.22815.arnd@arndb.de>

On Monday 06 August 2012, Sebastian Hesselbarth wrote:
> This patch set adds DT support for Marvell Dove SoC and three boards
> equipped with this SoC. The work is based on device tree support for
> Marvell Orion based SoCs introduced in 3.6-rc1.
> 
> The first three patches move mach-dove closer to Marvell Kirkwood's
> setup code by unifying the clock setup routines, adding clock gating
> control, and support for Marvell's crypto engine to mach-dove.
> 
> Patches 4 and 5 add a generic DT machine descriptor to mach-dove and
> corresponding DT descriptors for the SoC and already supported boards.
> 
> Finally, the last patch adds a DT descriptor for the SolidRun CuBox,
> a plug computer based on Marvell Dove.
> 
> This patch set relies on a DT support patch for sdhci-dove that has
> been sent to the corresponding maintainers a few days ago.

This looks vert nice!

Acked-by: Arnd Bergmann <arnd at arndb.de>

Has anyone tested it on cm-a510 and dove-db? Once we can reasonably
assume that there are no regressions compared to using the board
files, I think we can plan for removing the non-DT support in
mach-dove. If it's been tested positively, that can well be at
the same time as adding the DT support, otherwise I think we should
wait a couple of releases while having both simultaneously.

	Arnd


From tobetter at gmail.com  Mon Aug  6 10:10:51 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Mon,  6 Aug 2012 23:10:51 +0900
Subject: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412
Message-ID: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>

The HKDK4412 is the CPU module developed by Hardkernel which is based on
Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine ID
(4289) is registered.

Change-Id: I3af02808c03b9acea916c310390a4904ad92d761
Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/mach-exynos/Kconfig         |   23 +
 arch/arm/mach-exynos/Makefile        |    1 +
 arch/arm/mach-exynos/mach-hkdk4412.c |  979 ++++++++++++++++++++++++++++++++++
 arch/arm/tools/mach-types            |    1 +
 4 files changed, 1004 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..ae90773 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -54,6 +54,9 @@ config SOC_EXYNOS4412
 	default y
 	depends on ARCH_EXYNOS4
 	select SAMSUNG_DMADEV
+	select S5P_PM if PM
+	select S5P_SLEEP if PM
+	select PM_GENERIC_DOMAINS
 	help
 	  Enable EXYNOS4412 SoC support
 
@@ -394,6 +397,26 @@ config MACH_SMDK4412
 	select MACH_SMDK4212
 	help
 	  Machine support for Samsung SMDK4412
+
+config MACH_HKDK4412
+	bool "HKDK4412"
+	select SOC_EXYNOS4412
+	select MACH_SMDK4212
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_USB_HSOTG
+	select S5P_DEV_CSIS0
+	select S5P_DEV_G2D
+	select S5P_DEV_JPEG
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_I2C_HDMIPHY
+	select S5P_DEV_TV
+	select S5P_GPIO_INT
+	select EXYNOS4_DEV_USB_OHCI
+	select SAMSUNG_DEV_ADC
+	help
+	  Machine support for Odroid-X based on Samsung EXYNOS4412
+
 endif
 
 comment "Flattened Device Tree based board for EXYNOS SoCs"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024..dccc381 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o
 
 obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
+obj-$(CONFIG_MACH_HKDK4412)		+= mach-hkdk4412.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
diff --git a/arch/arm/mach-exynos/mach-hkdk4412.c b/arch/arm/mach-exynos/mach-hkdk4412.c
new file mode 100644
index 0000000..3b090ae
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-hkdk4412.c
@@ -0,0 +1,979 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-hkdk4412.c
+ *
+ * Copyright (c) 2012 AgreeYa Mobility Co., Ltd.
+ *		http://www.agreeyamobility.net
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/mfc.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+#include <plat/ehci.h>
+
+#include <mach/ohci.h>
+#include <mach/map.h>
+
+#include "common.h"
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define HKDK4412_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define HKDK4412_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define HKDK4412_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg hkdk4412_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+};
+
+static struct s3c_sdhci_platdata hkdk4412_hsmmc2_pdata __initdata = {
+	.cd_type	= S3C_SDHCI_CD_INTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width	= 8,
+	.host_caps	= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata hkdk4412_hsmmc3_pdata __initdata = {
+	.cd_type	= S3C_SDHCI_CD_INTERNAL,
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck1_consumer[] = {
+	REGULATOR_SUPPLY("vdd_mif", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck2_consumer[] = {
+	REGULATOR_SUPPLY("vdd_arm", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck3_consumer[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck4_consumer[] = {
+	REGULATOR_SUPPLY("vdd_g3d", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo1_consumer[] = {
+	REGULATOR_SUPPLY("vdd_alive", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo3_consumer[] = {
+	REGULATOR_SUPPLY("vddq_aud", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo4_consumer[] = {
+	REGULATOR_SUPPLY("vddq_mmc2", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo5_consumer[] = {
+	REGULATOR_SUPPLY("vddq_mmc1", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo8_consumer[] = {
+	REGULATOR_SUPPLY("vdd10_mipi", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo10_consumer[] = {
+	REGULATOR_SUPPLY("vdd18_mipi", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo11_consumer[] = {
+	REGULATOR_SUPPLY("vdd_ldo11", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo13_consumer[] = {
+	REGULATOR_SUPPLY("vdd18_mipihsi", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo14_consumer[] = {
+	REGULATOR_SUPPLY("vdd_ldo14", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo17_consumer[] = {
+	REGULATOR_SUPPLY("vddq_cam", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo18_consumer[] = {
+	REGULATOR_SUPPLY("vddq_isp", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo19_consumer[] = {
+	REGULATOR_SUPPLY("vt_cam", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo23_consumer[] = {
+	REGULATOR_SUPPLY("vdd_touch", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo24_consumer[] = {
+	REGULATOR_SUPPLY("vdd_touchled", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo25_consumer[] = {
+	REGULATOR_SUPPLY("vddq_lcd", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo26_consumer[] = {
+	REGULATOR_SUPPLY("vdd_motor", NULL),
+};
+
+static struct regulator_init_data __initdata max77686_buck1_data = {
+	.constraints = {
+		.name		= "vdd_mif range",
+		.min_uV		= 800000,
+		.max_uV		= 1050000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1_consumer),
+	.consumer_supplies = max77686_buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck2_data = {
+	.constraints = {
+		.name		= "vdd_arm range",
+		.min_uV		= 800000,
+		.max_uV		= 1350000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck2_consumer),
+	.consumer_supplies = max77686_buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck3_data = {
+	.constraints = {
+		.name		= "vdd_int range",
+		.min_uV		= 800000,
+		.max_uV		= 1150000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3_consumer),
+	.consumer_supplies = max77686_buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck4_data = {
+	.constraints = {
+		.name		= "vdd_g3d range",
+		.min_uV		= 850000,
+		.max_uV		= 1200000,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4_consumer),
+	.consumer_supplies = max77686_buck4_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck5_data = {
+	.constraints = {
+		.name		= "BUCK5 VDDQ_CKEM1_2",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck6_data = {
+	.constraints = {
+		.name		= "BUCK6 1V35",
+		.min_uV		= 1350000,
+		.max_uV		= 1350000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1350000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck7_data = {
+	.constraints = {
+		.name		= "BUCK7 2V0",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2000000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck8_data = {
+	.constraints = {
+		.name		= "BUCK8 3V3",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck9_data = {
+	.constraints = {
+		.name		= "BUCK9 1V2",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo1_data = {
+	.constraints = {
+		.name		= "LDO1 VDD_ALIVE",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo1_consumer),
+	.consumer_supplies = max77686_ldo1_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo2_data = {
+	.constraints = {
+		.name		= "LDO2 VDDQ_M1_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo3_data = {
+	.constraints = {
+		.name		= "LDO3 VDDQ_AUD_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo3_consumer),
+	.consumer_supplies = max77686_ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo4_data = {
+	.constraints = {
+		.name		= "LDO4 VDDQ_MMC2_2V8",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo4_consumer),
+	.consumer_supplies = max77686_ldo4_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo5_data = {
+	.constraints = {
+		.name		= "LDO5 VDDQ_MMC1_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo5_consumer),
+	.consumer_supplies = max77686_ldo5_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo6_data = {
+	.constraints = {
+		.name		= "LDO6 VDD10_MPLL_1V0",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo7_data = {
+	.constraints = {
+		.name		= "LDO7 VDD10_EPLL_1V0",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo8_data = {
+	.constraints = {
+		.name		= "LDO8 VDD10_MIPI_1V0",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo8_consumer),
+	.consumer_supplies = max77686_ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo9_data = {
+	.constraints = {
+		.name		= "LDO9 VT_CORE_1V0",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo10_data = {
+	.constraints = {
+		.name		= "LDO10 VDD18_MIPI_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo10_consumer),
+	.consumer_supplies = max77686_ldo10_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo11_data = {
+	.constraints = {
+		.name		= "vdd_ldo11 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem = {
+			.uV	= 1900000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(max77686_ldo11_consumer),
+	.consumer_supplies	= max77686_ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo12_data = {
+	.constraints = {
+		.name		= "LDO12 VDD33_UOTG_3V3",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo13_data = {
+	.constraints = {
+		.name		= "LDO13 VDD18_MIPIHSI_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo13_consumer),
+	.consumer_supplies = max77686_ldo13_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo14_data = {
+	.constraints = {
+		.name		= "vdd_ldo14 range",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem = {
+			.uV	= 1900000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(max77686_ldo14_consumer),
+	.consumer_supplies	= max77686_ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo15_data = {
+	.constraints = {
+		.name		= "LDO15 VDD10_OTG",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo16_data = {
+	.constraints = {
+		.name		= "LDO16 VDD18_HSIC",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo17_data = {
+	.constraints = {
+		.name		= "LDO17 VDDQ_CAM_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo17_consumer),
+	.consumer_supplies = max77686_ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo18_data = {
+	.constraints = {
+		.name		= "LDO18 VDDQ_ISP_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo18_consumer),
+	.consumer_supplies = max77686_ldo18_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo19_data = {
+	.constraints = {
+		.name		= "LDO19 VT_CAM_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 0,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo19_consumer),
+	.consumer_supplies = max77686_ldo19_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo20_data = {
+	.constraints = {
+		.name		= "LDO20 EMMC_IO_1V8",
+		.min_uV		= 1900000,
+		.max_uV		= 1900000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1900000,
+			.enabled = 0,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo21_data = {
+	.constraints = {
+		.name		= "LDO21 TFLASH_2V8",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo22_data = {
+	.constraints = {
+		.name		= "LDO22",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 0,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 0,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo23_data = {
+	.constraints = {
+		.name		= "LDO23 VDD_TOUCH_2V8",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo23_consumer),
+	.consumer_supplies = max77686_ldo23_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo24_data = {
+	.constraints = {
+		.name		= "LDO24 VDD_TOUCHLED_3V3",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo24_consumer),
+	.consumer_supplies = max77686_ldo24_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo25_data = {
+	.constraints = {
+		.name		= "LDO25 VDDQ_LCD_1V8",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo25_consumer),
+	.consumer_supplies = max77686_ldo25_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo26_data = {
+	.constraints = {
+		.name		= "LDO26 VDD_MOTOR_3V0",
+		.min_uV		= 3000000,
+		.max_uV		= 3000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV	= 3000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo26_consumer),
+	.consumer_supplies = max77686_ldo26_consumer,
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{ MAX77686_LDO1,	&max77686_ldo1_data },
+	{ MAX77686_LDO2,	&max77686_ldo2_data },
+	{ MAX77686_LDO3,	&max77686_ldo3_data },
+	{ MAX77686_LDO4,	&max77686_ldo4_data },
+	{ MAX77686_LDO5,	&max77686_ldo5_data },
+	{ MAX77686_LDO6,	&max77686_ldo6_data },
+	{ MAX77686_LDO7,	&max77686_ldo7_data },
+	{ MAX77686_LDO8,	&max77686_ldo8_data },
+	{ MAX77686_LDO9,	&max77686_ldo9_data },
+	{ MAX77686_LDO10,	&max77686_ldo10_data },
+	{ MAX77686_LDO11,	&max77686_ldo11_data },
+	{ MAX77686_LDO12,	&max77686_ldo12_data },
+	{ MAX77686_LDO13,	&max77686_ldo13_data },
+	{ MAX77686_LDO14,	&max77686_ldo14_data },
+	{ MAX77686_LDO15,	&max77686_ldo15_data },
+	{ MAX77686_LDO16,	&max77686_ldo16_data },
+	{ MAX77686_LDO17,	&max77686_ldo17_data },
+	{ MAX77686_LDO18,	&max77686_ldo18_data },
+	{ MAX77686_LDO19,	&max77686_ldo19_data },
+	{ MAX77686_LDO20,	&max77686_ldo20_data },
+	{ MAX77686_LDO21,	&max77686_ldo21_data },
+	{ MAX77686_LDO22,	&max77686_ldo22_data },
+	{ MAX77686_LDO23,	&max77686_ldo23_data },
+	{ MAX77686_LDO24,	&max77686_ldo24_data },
+	{ MAX77686_LDO25,	&max77686_ldo25_data },
+	{ MAX77686_LDO26,	&max77686_ldo26_data },
+
+	{ MAX77686_BUCK1,	&max77686_buck1_data },
+	{ MAX77686_BUCK2,	&max77686_buck2_data },
+	{ MAX77686_BUCK3,	&max77686_buck3_data },
+	{ MAX77686_BUCK4,	&max77686_buck4_data },
+	{ MAX77686_BUCK5,	&max77686_buck5_data },
+	{ MAX77686_BUCK6,	&max77686_buck6_data },
+	{ MAX77686_BUCK7,	&max77686_buck7_data },
+	{ MAX77686_BUCK8,	&max77686_buck8_data },
+	{ MAX77686_BUCK9,	&max77686_buck9_data },
+};
+
+static struct max77686_platform_data hkdk4412_max77686_info = {
+	.num_regulators	= ARRAY_SIZE(max77686_regulators),
+	.regulators	= max77686_regulators,
+	.irq_gpio	= 0,
+	.wakeup		= 0,
+
+	.opmode_data	= max77686_opmode_data,
+
+	.buck234_gpio_dvs[0]	= EXYNOS4_GPX2(3),
+	.buck234_gpio_dvs[1]	= EXYNOS4_GPX2(4),
+	.buck234_gpio_dvs[2]	= EXYNOS4_GPX2(5),
+
+	.buck2_voltage[0] = 1300000,	/* 1.3V */
+	.buck2_voltage[1] = 1000000,	/* 1.0V */
+	.buck2_voltage[2] = 950000,	/* 0.95V */
+	.buck2_voltage[3] = 900000,	/* 0.9V */
+	.buck2_voltage[4] = 1000000,	/* 1.0V */
+	.buck2_voltage[5] = 1000000,	/* 1.0V */
+	.buck2_voltage[6] = 950000,	/* 0.95V */
+	.buck2_voltage[7] = 900000,	/* 0.9V */
+
+	.buck3_voltage[0] = 1037500,	/* 1.0375V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 950000,	/* 0.95V */
+	.buck3_voltage[3] = 900000,	/* 0.9V */
+	.buck3_voltage[4] = 1000000,	/* 1.0V */
+	.buck3_voltage[5] = 1000000,	/* 1.0V */
+	.buck3_voltage[6] = 950000,	/* 0.95V */
+	.buck3_voltage[7] = 900000,	/* 0.9V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 950000,	/* 0.95V */
+	.buck4_voltage[3] = 900000,	/* 0.9V */
+	.buck4_voltage[4] = 1000000,	/* 1.0V */
+	.buck4_voltage[5] = 1000000,	/* 1.0V */
+	.buck4_voltage[6] = 950000,	/* 0.95V */
+	.buck4_voltage[7] = 900000,	/* 0.9V */
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs0[] __initdata = {
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &hkdk4412_max77686_info,
+	}
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs1[] __initdata = {
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs3[] __initdata = {
+	/* nothing here yet */
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs7[] __initdata = {
+	/* nothing here yet */
+};
+
+static struct gpio_led hkdk4412_gpio_leds[] = {
+	{
+		.name		= "led1",	/* D5 on ODROID-X */
+		.default_trigger	= "oneshot",
+		.gpio		= EXYNOS4_GPC1(0),
+		.active_low	= 1,
+	},
+	{
+		.name		= "led2",	/* D6 on ODROID-X */
+		.default_trigger	= "heartbeat",
+		.gpio		= EXYNOS4_GPC1(2),
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_led_platform_data hkdk4412_gpio_led_info = {
+	.leds		= hkdk4412_gpio_leds,
+	.num_leds	= ARRAY_SIZE(hkdk4412_gpio_leds),
+};
+
+static struct platform_device hkdk4412_leds_gpio = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &hkdk4412_gpio_led_info,
+	},
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata hkdk4412_ehci_pdata;
+
+static void __init hkdk4412_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &hkdk4412_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+
+/* USB OHCI */
+static struct exynos4_ohci_platdata hkdk4412_ohci_pdata;
+
+static void __init hkdk4412_ohci_init(void)
+{
+	struct exynos4_ohci_platdata *pdata = &hkdk4412_ohci_pdata;
+
+	exynos4_ohci_set_platdata(pdata);
+}
+
+/* USB OTG */
+static struct s3c_hsotg_plat hkdk4412_hsotg_pdata;
+
+static struct platform_device *hkdk4412_devices[] __initdata = {
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_i2c3,
+	&s3c_device_i2c7,
+	&s3c_device_rtc,
+	&s3c_device_usb_hsotg,
+	&s3c_device_wdt,
+	&s5p_device_ehci,
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+	&s5p_device_fimc_md,
+	&s5p_device_mfc,
+	&s5p_device_mfc_l,
+	&s5p_device_mfc_r,
+	&exynos4_device_ohci,
+	&hkdk4412_leds_gpio,
+};
+
+static void __init hkdk4412_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(clk_xusbxti.rate);
+	s3c24xx_init_uarts(hkdk4412_uartcfgs, ARRAY_SIZE(hkdk4412_uartcfgs));
+}
+
+static void __init hkdk4412_reserve(void)
+{
+	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init hkdk4412_gpio_init(void)
+{
+	/* Peripheral power enable (P3V3) */
+	gpio_request_one(EXYNOS4_GPA1(1), GPIOF_OUT_INIT_HIGH, "p3v3_en");
+}
+
+static void __init hkdk4412_machine_init(void)
+{
+	hkdk4412_gpio_init();
+
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, hkdk4412_i2c_devs0,
+				ARRAY_SIZE(hkdk4412_i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, hkdk4412_i2c_devs1,
+				ARRAY_SIZE(hkdk4412_i2c_devs1));
+
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, hkdk4412_i2c_devs3,
+				ARRAY_SIZE(hkdk4412_i2c_devs3));
+
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, hkdk4412_i2c_devs7,
+				ARRAY_SIZE(hkdk4412_i2c_devs7));
+
+	s3c_sdhci2_set_platdata(&hkdk4412_hsmmc2_pdata);
+	s3c_sdhci3_set_platdata(&hkdk4412_hsmmc3_pdata);
+
+	hkdk4412_ehci_init();
+	hkdk4412_ohci_init();
+	s3c_hsotg_set_platdata(&hkdk4412_hsotg_pdata);
+
+	platform_add_devices(hkdk4412_devices, ARRAY_SIZE(hkdk4412_devices));
+}
+
+MACHINE_START(ODROIDX, "ODROID-X")
+	/* Maintainer: Dongjin Kim <dongjin.kim at agreeyamobiity.net> */
+	.atag_offset	= 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= hkdk4412_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= hkdk4412_machine_init,
+	.init_late	= exynos_init_late,
+	.timer		= &exynos4_timer,
+	.restart	= exynos4_restart,
+	.reserve	= &hkdk4412_reserve,
+MACHINE_END
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56..e80ed9f 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1206,3 +1206,4 @@ baileys			MACH_BAILEYS		BAILEYS			4169
 familybox		MACH_FAMILYBOX		FAMILYBOX		4170
 ensemble_mx35		MACH_ENSEMBLE_MX35	ENSEMBLE_MX35		4171
 sc_sps_1		MACH_SC_SPS_1		SC_SPS_1		4172
+odroidx		MACH_ODROIDX		ODROIDX			4289
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 10:11:21 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 15:11:21 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.
In-Reply-To: <CACRpkdZoJxyZX6SOcAvBP4NBmGyUEiyLH_n_RzSDTBsjS13zug@mail.gmail.com>
References: <1344255947-10062-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdZoJxyZX6SOcAvBP4NBmGyUEiyLH_n_RzSDTBsjS13zug@mail.gmail.com>
Message-ID: <20120806141120.GE10524@gmail.com>

On Mon, Aug 06, 2012 at 04:00:04PM +0200, Linus Walleij wrote:
> On Mon, Aug 6, 2012 at 2:25 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > At this moment in time there is only one known configuration for the
> > Nomadik I2C driver. By not holding that configuration in the driver
> > adds some unnecessary overhead in platform code. The configuration
> > as already been removed from platform code, this patch checks for any
> > over-riding configurations. If there aren't any, the default is used.
> >
> > Cc: linux-i2c at vger.kernel.org
> > Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This still does not apply for me on v3.6-rc1 what did you base
> this patch on?
> 
> Applying: i2c: Add default configuration into the Nomadik I2C driver.
> error: patch failed: drivers/i2c/busses/i2c-nomadik.c:899
> error: drivers/i2c/busses/i2c-nomadik.c: patch does not apply
> Patch failed at 0001 i2c: Add default configuration into the Nomadik I2C driver.
> When you have resolved this problem run "git am --resolved".
> If you would prefer to skip this patch, instead run "git am --skip".
> To restore the original branch and stop patching run "git am --abort".

Ah, my mistake.

I'll rebase to latest and re-submit.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From u.kleine-koenig at pengutronix.de  Mon Aug  6 10:12:31 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 Aug 2012 16:12:31 +0200
Subject: [PATCH 2/4] gpio/mxc: specify gpio base for device tree probe
In-Reply-To: <1344146488-9496-2-git-send-email-shawn.guo@linaro.org>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120806141231.GA9329@pengutronix.de>

On Sun, Aug 05, 2012 at 02:01:26PM +0800, Shawn Guo wrote:
> Currently, unlike the non-DT probe where the gpio base is specified
> with pdev->id, the DT probe uses the base dynamically allocated by
> gpio core, which uses a completely different numbering scheme.  This
> causes two issues to user space applications which access sysfs entry
> /sys/class/gpio/gpioN.
> 
> * It breaks the compatibility with user space applications between
>   non-DT and DT kernels.
> 
> * It's not intuitive and sometimes hard for users to map the Linux
>   gpio number to the actual hardware pin.
> 
> Use alias to identify the gpio port/bank, and then the gpio base
> can be specified with port id to solve above issues.  If alias is not
> defined in device tree, the base number dynamically allocated by gpio
> core will be used.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
I applied patches 1, 2 and 4 to my imx35 dt tree and they work like a
charm.

Tested-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

for these three.

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From ohad at wizery.com  Mon Aug  6 10:16:18 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Mon, 6 Aug 2012 17:16:18 +0300
Subject: [PATCH 1/1] remoteproc: extend customized fw loader to cover
 request and release
In-Reply-To: <1344237865-32491-1-git-send-email-roylee17@gmail.com>
References: <1344237865-32491-1-git-send-email-roylee17@gmail.com>
Message-ID: <CAK=WgbbBHspN_LTUXH1kUugH8-Nr-G=p-G3Wj60tAmrqqfakmg@mail.gmail.com>

Hi Tzu-Jung Lee,

On Mon, Aug 6, 2012 at 10:24 AM, Tzu-Jung Lee <roylee17 at gmail.com> wrote:
> Previously, the remoteproc mandates an actual ELF firmware in order to
> parse the resource table and boot the remoteproc.
>
> An fw loader abstraction was added in v3.61-rc1 to make the ELF as a
> "default" handler, and allows firmwares in other formats to be loaded.
>
> However, in our use cases, we don't actually have a firmware for linux
> to load. The remote processor always boots first, and then boots the
> rest of processors that running linux.

Can you describe your use case some more ?

What parts in remoteproc are actually helpful for you (not much I
guess if Linux doesn't control the life cycle of the remote processor
in your case) ?

Do you use rpmsg ?

> In this case, forging an binary firmware just for the resource table
> creates a burden for maintenence.
> Allowing the firmware request/release function to be customized gives
> developers to construct the reqource table in memory, instead of loading
> one from filesystem.

I'm not sure this is an ideal abstraction though.

The problem you describe is architectural and not necessarily related
with a specific binary format, which this patch ties it up with (by
abstracting it away in rproc_fw_ops). It seems that a
binary-format-agnostic solution is preferable, because it could then
be utilized by any platform, regardless of the binary format it uses.

In general we prefer not to adopt a solution that puts the resource
table in the kernel, because that means redundant churn and
compatibility issues, as the resource table is inherently coupled with
the software running on the remote processor, and not with the Linux
kernel.

An easy solution is to allow loading an external stand-alone resource
table from the filesystem. We've discussed this in the past and
several parties showed interest. Will it help you ?

Another possible solution is to allow the low level rproc driver to
provide the remoteproc framework a pointer to an in-memory resource
table. This may prove useful in case the remote processor is already
up when Linux boots, and the resource table is already loaded to
memory.

> Change-Id: I0aa071dc1bd775eed6ea0822cff0fe2fc1b12b45

PS - no need to provide these tags when sending patches upstream.

Thanks,
Ohad.


From sebastian.hesselbarth at gmail.com  Mon Aug  6 10:16:57 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 6 Aug 2012 16:16:57 +0200
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <201208061402.22815.arnd@arndb.de>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <201208061402.22815.arnd@arndb.de>
Message-ID: <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>

On 8/6/12, Arnd Bergmann <arnd at arndb.de> wrote:
> This looks vert nice!
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Hi Arnd,

thanks for the ack!

> Has anyone tested it on cm-a510 and dove-db? Once we can reasonably
> assume that there are no regressions compared to using the board
> files, I think we can plan for removing the non-DT support in
> mach-dove. If it's been tested positively, that can well be at
> the same time as adding the DT support, otherwise I think we should
> wait a couple of releases while having both simultaneously.

Unfortunately, I has not (yet) been tested on cm-a510 nor dove-db but
from the status of the exisiting non-DT setup files I strongly doubt that
anyone is using current mainline kernel for mach-dove.

I suggest to keep non-DT support until we have pinctrl and gpiolib drivers
done. Thomas Petazzoni and I have been working on pinctrl that will be
posted in a few days and gpiolib driver needs some more cleanup but is
basically working. Until then I guess most of the other orion drivers have
DT support (eth and xor IIRC).

After that I am definitely fine with removing non-DT support although
there is neither DT support in u-boot installed on my CuBox nor
mach-dove support in mainline u-boot.

Sebastian


From balbi at ti.com  Mon Aug  6 10:18:53 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon,  6 Aug 2012 17:18:53 +0300
Subject: [PATCH 0/4] i2c: omap: few more patches
Message-ID: <1344262737-6662-1-git-send-email-balbi@ti.com>

Just a few extra patches on top of the earlier series I sent.

With these patches, we have threaded irq support and autosuspend support for
i2c-omap driver.

All patches boot tested with pandaboard.

Felipe Balbi (4):
  i2c: omap: always return IRQ_HANDLED
  i2c: omap: switch to threaded IRQ support
  i2c: omap: remove unnecessary pm_runtime_suspended check
  i2c: omap: switch over to autosuspend API

 drivers/i2c/busses/i2c-omap.c | 53 ++++++++++++++++++++++++++++++++++---------
 1 file changed, 42 insertions(+), 11 deletions(-)

-- 
1.7.12.rc0



From balbi at ti.com  Mon Aug  6 10:18:55 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon,  6 Aug 2012 17:18:55 +0300
Subject: [PATCH 2/4] i2c: omap: switch to threaded IRQ support
In-Reply-To: <1344262737-6662-1-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
Message-ID: <1344262737-6662-3-git-send-email-balbi@ti.com>

for OMAP2, we can easily switch over to threaded
IRQs on the I2C driver. This will allow us to
spend less time in hardirq context.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 42 ++++++++++++++++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f5eafb7..a3db053 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -176,6 +176,7 @@ enum {
 #define I2C_OMAP_ERRATA_I462		(1 << 1)
 
 struct omap_i2c_dev {
+	spinlock_t		lock;		/* IRQ synchronization */
 	struct device		*dev;
 	void __iomem		*base;		/* virtual */
 	int			irq;
@@ -854,9 +855,30 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 }
 
 static irqreturn_t
-omap_i2c_isr(int this_irq, void *dev_id)
+omap_i2c_isr(int irq, void *dev_id)
 {
 	struct omap_i2c_dev *dev = dev_id;
+	irqreturn_t ret = IRQ_HANDLED;
+	u16 mask;
+	u16 stat;
+
+	spin_lock(&dev->lock);
+	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+
+	if (stat & mask)
+		ret = IRQ_WAKE_THREAD;
+
+	spin_unlock(&dev->lock);
+
+	return ret;
+}
+
+static irqreturn_t
+omap_i2c_isr_thread(int this_irq, void *dev_id)
+{
+	struct omap_i2c_dev *dev = dev_id;
+	unsigned long flags;
 	u16 bits;
 	u16 stat;
 	int err = 0, count = 0;
@@ -864,6 +886,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	if (pm_runtime_suspended(dev->dev))
 		return IRQ_HANDLED;
 
+	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
@@ -877,6 +900,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
+			spin_unlock_irqrestore(&dev->lock, flags);
 			return IRQ_HANDLED;
 		}
 
@@ -985,6 +1009,8 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 out:
 	omap_i2c_complete_cmd(dev, err);
+	spin_unlock_irqrestore(&dev->lock, flags);
+
 	return IRQ_HANDLED;
 }
 
@@ -1028,7 +1054,6 @@ omap_i2c_probe(struct platform_device *pdev)
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
-	irq_handler_t isr;
 	int irq;
 	int r;
 
@@ -1078,6 +1103,8 @@ omap_i2c_probe(struct platform_device *pdev)
 	dev->dev = &pdev->dev;
 	dev->irq = irq;
 
+	spin_lock_init(&dev->lock);
+
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
 
@@ -1130,10 +1157,13 @@ omap_i2c_probe(struct platform_device *pdev)
 	/* reset ASAP, clearing any IRQs */
 	omap_i2c_init(dev);
 
-	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
-								   omap_i2c_isr;
-	r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
-			     pdev->name, dev);
+	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
+		r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
+				IRQF_NO_SUSPEND, pdev->name, dev);
+	else
+		r = devm_request_threaded_irq(&pdev->dev, dev->irq, omap_i2c_isr,
+				omap_i2c_isr_thread, IRQF_NO_SUSPEND | IRQF_ONESHOT,
+				pdev->name, dev);
 
 	if (r) {
 		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
-- 
1.7.12.rc0



From balbi at ti.com  Mon Aug  6 10:18:56 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon,  6 Aug 2012 17:18:56 +0300
Subject: [PATCH 3/4] i2c: omap: remove unnecessary pm_runtime_suspended check
In-Reply-To: <1344262737-6662-1-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
Message-ID: <1344262737-6662-4-git-send-email-balbi@ti.com>

before starting any messages we call pm_runtime_get_sync()
which will make sure that by the time we program a transfer
and our IRQ handler gets called, we're not suspended
anymore.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index a3db053..60928f2 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -883,9 +883,6 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 	u16 stat;
 	int err = 0, count = 0;
 
-	if (pm_runtime_suspended(dev->dev))
-		return IRQ_HANDLED;
-
 	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.12.rc0



From balbi at ti.com  Mon Aug  6 10:18:57 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon,  6 Aug 2012 17:18:57 +0300
Subject: [PATCH 4/4] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344262737-6662-1-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
Message-ID: <1344262737-6662-5-git-send-email-balbi@ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message been started
soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 60928f2..22efaba 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -645,7 +645,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1114,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, 1000);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1189,7 +1193,7 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.12.rc0



From balbi at ti.com  Mon Aug  6 10:18:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon,  6 Aug 2012 17:18:54 +0300
Subject: [PATCH 1/4] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1344262737-6662-1-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
Message-ID: <1344262737-6662-2-git-send-email-balbi@ti.com>

even if our clocks are disabled, we still
handled the IRQ, so we should return IRQ_HANDLED.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2dd2301..f5eafb7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -862,7 +862,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	int err = 0, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
-		return IRQ_NONE;
+		return IRQ_HANDLED;
 
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.12.rc0



From u.kleine-koenig at pengutronix.de  Mon Aug  6 10:23:45 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 Aug 2012 16:23:45 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <20120803122516.GA23791@S2101-09.ap.freescale.net>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803122516.GA23791@S2101-09.ap.freescale.net>
Message-ID: <20120806142345.GB9329@pengutronix.de>

Hello,

On Fri, Aug 03, 2012 at 08:25:18PM +0800, Shawn Guo wrote:
> On Thu, Aug 02, 2012 at 05:39:02PM +0200, Uwe Kleine-K?nig wrote:
> > +enum imx35_pads {
> > +	/* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
> 
> I'm not sure we want to keep a reference to
> arch/arm/plat-mxc/include/mach/iomux-mx35.h that is to be removed.
ok for me to remove it. Will resend without that line and Stephen's Ack.

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Mon Aug  6 10:24:06 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 Aug 2012 16:24:06 +0200
Subject: [PATCH] ARM: imx35: don't disable the uart clock when DEBUG_LL
 is in use
In-Reply-To: <20120731183206.GC10670@pengutronix.de>
References: <1343742279-29570-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120731174358.GC30009@pengutronix.de>
 <20120731183206.GC10670@pengutronix.de>
Message-ID: <20120806142406.GC9329@pengutronix.de>

On Tue, Jul 31, 2012 at 08:32:06PM +0200, Uwe Kleine-K?nig wrote:
> Hello Sascha,
> 
> On Tue, Jul 31, 2012 at 07:43:58PM +0200, Sascha Hauer wrote:
> > On Tue, Jul 31, 2012 at 03:44:39PM +0200, Uwe Kleine-K?nig wrote:
> > > Otherwise printch et al. and printk with earlyprintk and keep_bootcon
> > > becomes unfunctional when the clk framework disables all unused clocks.
> > 
> > Why don't you use the regular console? Letting the clock framework
> > disable the clocks was pretty much intentional.
> I don't question that disabling unused clocks is sensible. But usually
> if you enable DEBUG_LL you want to use it even after the clock framework
> disabled all (apparently) unused clocks. And in my case the regular
> console didn't work yet and so I relied on earlyprintk.
> Even if the problem proved to be the result of my stupidity this patch
> asserts that earlyprintk just works as it should be for debug aids.
ping

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From arnd at arndb.de  Mon Aug  6 10:23:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 14:23:38 +0000
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <201208061402.22815.arnd@arndb.de>
 <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>
Message-ID: <201208061423.38988.arnd@arndb.de>

On Monday 06 August 2012, Sebastian Hesselbarth wrote:
> I suggest to keep non-DT support until we have pinctrl and gpiolib drivers
> done. Thomas Petazzoni and I have been working on pinctrl that will be
> posted in a few days and gpiolib driver needs some more cleanup but is
> basically working. Until then I guess most of the other orion drivers have
> DT support (eth and xor IIRC).

Ok, sounds resonable.

	Arnd


From gcembed at gmail.com  Mon Aug  6 10:24:09 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Mon, 06 Aug 2012 16:24:09 +0200
Subject: [PATCH 1/1] mx27_3ds: Add sound support
In-Reply-To: <CAOMZO5B9ZmTHrYjVc5a7j=uUgUEyfDva54cKxBP3UeCYZsUWRw@mail.gmail.com>
References: <1344258447-6162-1-git-send-email-gcembed@gmail.com>
 <CAOMZO5B9ZmTHrYjVc5a7j=uUgUEyfDva54cKxBP3UeCYZsUWRw@mail.gmail.com>
Message-ID: <501FD389.1050105@gmail.com>

Hi Fabio,
Sorry, I have missed your patch in my email archive. I didn't search the 
right keywords.
I applied your [patch 1/2] (2/2 is already merged) but I have same 
effect. I use aplay with file k3b_error1.wav (Unsigned 8 bit, Rate 8000 
Hz, Mono) and alsa/Front_Left.wav (Signed 16 bit Little Endian, Rate 
48000 Hz, Mono). Two sounds are played too fast.
It is maybe a bad configuration of Alsa (but this is working with kernel 
2.6.22 from Freescale).
Thanks.
Ga?tan.

On 08/06/2012 03:36 PM, Fabio Estevam wrote:
> Hi Ga?tan,
>
> On Mon, Aug 6, 2012 at 10:07 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
>> Hi,
>> I have ported code "Enable sound on mx31_3ds" from Philippe R?tornaz to
>> MX27 3DS platform on master branch of linux-next (tag next-20120806).
>> I also applied patch "dma: imx-dma: Fix kernel crash due to missing clock
>> conversion" of Fabio Estevam which is not yet merged in linux-next.
>> Thanks to them, everything is working good on MX27 3DS platform except that
>> sound is played too fast.
>> Which parameter must be adjusted to have sound playing at normal speed ?
>> In mc13783 codec driver, imx_add_imx_ssi(), clock configuration in
>> mach-mx27_3ds file ?
>>
>> Thanks for your help.
>>
>> Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
>
> I have added audio support for mx27pdk:
> https://patchwork.kernel.org/patch/1152951/
>
> ,and in my tests the audio was played at the correct rate.
>
> Can you please have a try?
>
> What is the sampling rate of your file?
>
> Regards,
>
> Fabio Estevam
>



From Stefano.Stabellini at eu.citrix.com  Mon Aug  6 10:25:08 2012
From: Stefano.Stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:25:08 +0100
Subject: [PATCH v2 00/23] Introduce Xen support on ARM
Message-ID: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>

Hi all,
this patch series implements Xen support for ARMv7 with virtualization
extensions.  It allows a Linux guest to boot as dom0 and
as domU on Xen on ARM. PV console, disk and network frontends and
backends are all working correctly.

It has been tested on a Versatile Express Cortex A15 emulator, using the
latest Xen ARM developement branch
(git://xenbits.xen.org/people/ianc/xen-unstable.git arm-for-4.3) plus
the "ARM hypercall ABI: 64 bit ready" patch series
(http://marc.info/?l=xen-devel&m=134426267205408), and a simple ad-hoc
tool to build guest domains (marc.info/?l=xen-devel&m=134089788016546).

The patch marked with [HACK] shouldn't be applied and is part of the
series only because it is needed to create domUs.

I am also attaching to this email the dts'es that I am currently using
for dom0 and domU: vexpress-v2p-ca15-tc1.dts (that includes
vexpress-v2m-rs1-rtsm.dtsi) is the dts used for dom0 and it is passed to
Linux by Xen, while vexpress-virt.dts is the dts used for other domUs
and it is appended in binary form to the guest kernel image. I am not
sure where they are supposed to live yet, so I am just attaching them
here so that people can actually try out this series if they want to.

Comments are very welcome!


Changes in v2:
- fix up many comments and commit messages;
- remove the early_printk patches: rely on the emulated serial for now;
- remove the xen_guest_init patch: without any PV early_printk, we don't
  need any early call to xen_guest_init, we can rely on core_initcall
  alone;
- define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
  at the moment is unused;
- use ldm instead of pop in the hypercall wrappers;
- return -ENOSYS rather than -1 from the unimplemented grant_table
  functions;
- remove the pvclock ifdef in the Xen headers;
- remove include linux/types.h from xen/interface/xen.h;
- replace pr_info with pr_debug in xen_guest_init;
- add a new patch to introduce xen_ulong_t and use it top replace all
  the occurences of unsigned long in the public Xen interface;
- explicitely size all the pointers to 64 bit on ARM, so that the
  hypercall ABI is "64 bit ready";
- clean up xenbus_init;
- make pci.o depend on CONFIG_PCI and acpi.o depend on CONFIG_ACPI;
- mark Xen guest support on ARM as EXPERIMENTAL;
- introduce GRANT_TABLE_PHYSADDR;
- remove unneeded initialization of boot_max_nr_grant_frames;
- add a new patch to clear IRQ_NOAUTOEN and IRQ_NOREQUEST in events.c;
- return -EINVAL from xen_remap_domain_mfn_range if
  auto_translated_physmap;
- retain binary compatibility in xen_add_to_physmap: use a union to
  introduce foreign_domid.



Ian Campbell (1):
      [HACK] xen/arm: implement xen_remap_domain_mfn_range

Stefano Stabellini (22):
      arm: initial Xen support
      xen/arm: hypercalls
      xen/arm: page.h definitions
      xen/arm: sync_bitops
      xen/arm: empty implementation of grant_table arch specific functions
      xen: missing includes
      xen/arm: Xen detection and shared_info page mapping
      xen/arm: Introduce xen_pfn_t for pfn and mfn types
      xen/arm: Introduce xen_ulong_t for unsigned long
      xen/arm: compile and run xenbus
      xen: do not compile manage, balloon, pci, acpi and cpu_hotplug on ARM
      xen/arm: introduce CONFIG_XEN on ARM
      xen/arm: get privilege status
      xen/arm: initialize grant_table on ARM
      xen/arm: receive Xen events on ARM
      xen: clear IRQ_NOAUTOEN and IRQ_NOREQUEST
      xen/arm: implement alloc/free_xenballooned_pages with alloc_pages/kfree
      xen: allow privcmd for HVM guests
      xen/arm: compile blkfront and blkback
      xen/arm: compile netback
      xen: update xen_add_to_physmap interface
      arm/v2m: initialize arch_timers even if v2m_timer is not present

 arch/arm/Kconfig                           |   10 ++
 arch/arm/Makefile                          |    1 +
 arch/arm/include/asm/hypervisor.h          |    6 +
 arch/arm/include/asm/sync_bitops.h         |   27 +++
 arch/arm/include/asm/xen/events.h          |   18 ++
 arch/arm/include/asm/xen/hypercall.h       |   69 ++++++++
 arch/arm/include/asm/xen/hypervisor.h      |   19 +++
 arch/arm/include/asm/xen/interface.h       |   72 +++++++++
 arch/arm/include/asm/xen/page.h            |   79 +++++++++
 arch/arm/mach-vexpress/v2m.c               |   11 +-
 arch/arm/xen/Makefile                      |    1 +
 arch/arm/xen/enlighten.c                   |  237 ++++++++++++++++++++++++++++
 arch/arm/xen/grant-table.c                 |   53 ++++++
 arch/arm/xen/hypercall.S                   |  106 +++++++++++++
 arch/ia64/include/asm/xen/interface.h      |    6 +-
 arch/x86/include/asm/xen/interface.h       |    8 +
 arch/x86/xen/enlighten.c                   |    1 +
 arch/x86/xen/irq.c                         |    1 +
 arch/x86/xen/mmu.c                         |    3 +
 arch/x86/xen/xen-ops.h                     |    1 -
 drivers/block/xen-blkback/blkback.c        |    1 +
 drivers/net/xen-netback/netback.c          |    1 +
 drivers/net/xen-netfront.c                 |    1 +
 drivers/tty/hvc/hvc_xen.c                  |    2 +
 drivers/xen/Makefile                       |   11 +-
 drivers/xen/events.c                       |   18 ++-
 drivers/xen/grant-table.c                  |    1 +
 drivers/xen/privcmd.c                      |   20 +--
 drivers/xen/xenbus/xenbus_comms.c          |    2 +-
 drivers/xen/xenbus/xenbus_probe.c          |   62 +++++---
 drivers/xen/xenbus/xenbus_probe_frontend.c |    1 +
 drivers/xen/xenbus/xenbus_xs.c             |    1 +
 drivers/xen/xenfs/super.c                  |    7 +
 include/xen/events.h                       |    2 +
 include/xen/interface/features.h           |    3 +
 include/xen/interface/grant_table.h        |    4 +-
 include/xen/interface/io/protocols.h       |    3 +
 include/xen/interface/memory.h             |   32 +++--
 include/xen/interface/physdev.h            |    4 +-
 include/xen/interface/platform.h           |    4 +-
 include/xen/interface/version.h            |    2 +-
 include/xen/interface/xen.h                |   13 +-
 include/xen/privcmd.h                      |    3 +-
 include/xen/xen.h                          |    2 +-
 44 files changed, 857 insertions(+), 72 deletions(-)



A branch based on 3.5-rc7 is available here:

git://xenbits.xen.org/people/sstabellini/linux-pvhvm.git 3.5-rc7-arm-2

Cheers,

Stefano
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * ARM Envelope Model v7A (single CPU).
 */

/dts-v1/;

/include/ "skeleton.dtsi"

/ {
	model = "V2P-AEMv7A";
	compatible = "arm,vexpress,v2p-aem,v7a", "arm,vexpress,v2p-aem", "arm,vexpress";
	interrupt-parent = <&gic>;

        chosen {
                bootargs = "earlyprintk debug loglevel=9 console=hvc0 root=/dev/xvda init=/sbin/init";
        };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu at 0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x08000000>;
	};

	gic: interrupt-controller at 2c001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c002000 0x100>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	xen {
		compatible = "arm,xen";
		reg = <0xb0000000 0x20000>;
		interrupts = <1 15 0xf08>;
	};

	motherboard {
		arm,v2m-memory-map = "rs1";
		ranges = <0 0 0x08000000 0x04000000>,
			 <1 0 0x14000000 0x04000000>,
			 <2 0 0x18000000 0x04000000>,
			 <3 0 0x1c000000 0x04000000>,
			 <4 0 0x0c000000 0x04000000>,
			 <5 0 0x10000000 0x04000000>;

		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};
};
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 (version with Test Chip 1)
 * Cortex-A15 MPCore (V2P-CA15)
 *
 * HBI-0237A
 */

/dts-v1/;

/ {
	model = "V2P-CA15";
	arm,hbi = <0x237>;
	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";

	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	chosen {
                 bootargs = "dom0_mem=128M";
                 xen,dom0-bootargs = "earlyprintk console=ttyAMA1 root=/dev/mmcblk0 debug rw";
	};


	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu at 0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	gic: interrupt-controller at 2c001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c002000 0x100>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
	};

	xen {
		compatible = "arm,xen";
		reg = <0xb0000000 0x20000>;
		interrupts = <1 15 0xf08>;
	};

	motherboard {
		ranges = <0 0 0x08000000 0x04000000>,
			 <1 0 0x14000000 0x04000000>,
			 <2 0 0x18000000 0x04000000>,
			 <3 0 0x1c000000 0x04000000>,
			 <4 0 0x0c000000 0x04000000>,
			 <5 0 0x10000000 0x04000000>;

		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};
};

/include/ "vexpress-v2m-rs1-rtsm.dtsi"
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * original variant (vexpress-v2m.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m.dtsi!
 */

/ {
	aliases {
		arm,v2m_timer = &v2m_timer01;
	};

	motherboard {
		compatible = "simple-bus";
		arm,v2m-memory-map = "rs1";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;

		flash at 0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <4 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		psram at 1,00000000 {
			compatible = "arm,vexpress-psram", "mtd-ram";
			reg = <1 0x00000000 0x02000000>;
			bank-width = <4>;
		};

		vram at 2,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <2 0x00000000 0x00800000>;
		};

		ethernet at 2,02000000 {
			compatible = "smsc,lan91c111";
			reg = <2 0x02000000 0x10000>;
			interrupts = <15>;
		};
	
		usb at 2,03000000 {
			compatible = "nxp,usb-isp1761";
			reg = <2 0x03000000 0x20000>;
			interrupts = <16>;
			port1-otg;
		};

		iofpga at 3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			sysreg at 010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
			};

			sysctl at 020000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
			};

			/* PCI-E I2C bus */
			v2m_i2c_pcie: i2c at 030000 {
				compatible = "arm,versatile-i2c";
				reg = <0x030000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				pcie-switch at 60 {
					compatible = "idt,89hpes32h8";
					reg = <0x60>;
				};
			};

			aaci at 040000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x040000 0x1000>;
				interrupts = <11>;
			};

			mmci at 050000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x050000 0x1000>;
				interrupts = <9 10>;
			};

			kmi at 060000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x060000 0x1000>;
				interrupts = <12>;
			};

			kmi at 070000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x070000 0x1000>;
				interrupts = <13>;
			};

			v2m_serial0: uart at 090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
			};

			v2m_serial1: uart at 0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
			};

			v2m_serial2: uart at 0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
			};

			v2m_serial3: uart at 0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
			};

			wdt at 0f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0>;
			};

			v2m_timer01: timer at 110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <2>;
			};

			v2m_timer23: timer at 120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
			};

			/* DVI I2C bus */
			v2m_i2c_dvi: i2c at 160000 {
				compatible = "arm,versatile-i2c";
				reg = <0x160000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				dvi-transmitter at 39 {
					compatible = "sil,sii9022-tpi", "sil,sii9022";
					reg = <0x39>;
				};

				dvi-transmitter at 60 {
					compatible = "sil,sii9022-cpi", "sil,sii9022";
					reg = <0x60>;
				};
			};

			rtc at 170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <4>;
			};

			compact-flash at 1a0000 {
				compatible = "arm,vexpress-cf", "ata-generic";
				reg = <0x1a0000 0x100
				       0x1a0100 0xf00>;
				reg-shift = <2>;
			};

			clcd at 1f0000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f0000 0x1000>;
				interrupts = <14>;
			};
		};
	};
};

From festevam at gmail.com  Mon Aug  6 10:26:52 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 11:26:52 -0300
Subject: [PATCH 1/1] mx27_3ds: Add sound support
In-Reply-To: <501FD389.1050105@gmail.com>
References: <1344258447-6162-1-git-send-email-gcembed@gmail.com>
 <CAOMZO5B9ZmTHrYjVc5a7j=uUgUEyfDva54cKxBP3UeCYZsUWRw@mail.gmail.com>
 <501FD389.1050105@gmail.com>
Message-ID: <CAOMZO5B3i9NeSD-uqbjN6LLCR1UUhSYKs8g+D6yj7hs31kNJ6A@mail.gmail.com>

On Mon, Aug 6, 2012 at 11:24 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
> Hi Fabio,
> Sorry, I have missed your patch in my email archive. I didn't search the
> right keywords.
> I applied your [patch 1/2] (2/2 is already merged) but I have same effect. I
> use aplay with file k3b_error1.wav (Unsigned 8 bit, Rate 8000 Hz, Mono) and
> alsa/Front_Left.wav (Signed 16 bit Little Endian, Rate 48000 Hz, Mono). Two
> sounds are played too fast.
> It is maybe a bad configuration of Alsa (but this is working with kernel
> 2.6.22 from Freescale).

Ok, we will need to debug this problem then.

Can you please send me offline these two files?

Regards,

Fabio Estevam


From arnd at arndb.de  Mon Aug  6 10:30:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 14:30:43 +0000
Subject: [PATCH] arm: add documentation describing Marvell families of SoC
In-Reply-To: <20120806112736.6d441561@skate>
References: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <201208060813.01524.arnd@arndb.de> <20120806112736.6d441561@skate>
Message-ID: <201208061430.43962.arnd@arndb.de>

On Monday 06 August 2012, Thomas Petazzoni wrote:
> Le Mon, 6 Aug 2012 08:13:01 +0000,
> Arnd Bergmann <arnd at arndb.de> a ?crit :
> 
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> Thanks. Am I supposed to resend this to Rob Landley <rob at landley.net>,
> who is apparently the Documentation/ maintainer, or can you push it
> through the arm-soc tree since it is Documentation/arm/ material?

Taking this through arm-soc is fine with me, and Russell's ARM
tree would probably work as well.

Should I apply the patch right away, or do you plan to send
it as part of a set of pull requests? In general I would assume
that I get a pull request unless you specifically ask for the
patch to be applied to the arm-soc tree separately (which is
ok for single patches).

Also remember to send any requests for inclusion into arm-soc
(pull or patch) to both Olof and me, since we are taking turns
in the maintainance and you might not know who is doing it
on any given day.

	Arnd


From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:13 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:13 +0100
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>

bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
an error.

If Linux is running as an HVM domain and is running as Dom0, use
xenstored_local_init to initialize the xenstore page and event channel.

Changes in v2:

- refactor xenbus_init.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 drivers/xen/xenbus/xenbus_comms.c |    2 +-
 drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
 drivers/xen/xenbus/xenbus_xs.c    |    1 +
 3 files changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
index 52fe7ad..c5aa55c 100644
--- a/drivers/xen/xenbus/xenbus_comms.c
+++ b/drivers/xen/xenbus/xenbus_comms.c
@@ -224,7 +224,7 @@ int xb_init_comms(void)
 		int err;
 		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
 						0, "xenbus", &xb_waitq);
-		if (err <= 0) {
+		if (err < 0) {
 			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
 			return err;
 		}
diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
index b793723..a67ccc0 100644
--- a/drivers/xen/xenbus/xenbus_probe.c
+++ b/drivers/xen/xenbus/xenbus_probe.c
@@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
 	return err;
 }
 
+enum xenstore_init {
+	UNKNOWN,
+	PV,
+	HVM,
+	LOCAL,
+};
 static int __init xenbus_init(void)
 {
 	int err = 0;
+	enum xenstore_init usage = UNKNOWN;
+	uint64_t v = 0;
 
 	if (!xen_domain())
 		return -ENODEV;
 
 	xenbus_ring_ops_init();
 
-	if (xen_hvm_domain()) {
-		uint64_t v = 0;
-		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
-		if (err)
-			goto out_error;
-		xen_store_evtchn = (int)v;
-		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
-		if (err)
-			goto out_error;
-		xen_store_mfn = (unsigned long)v;
-		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
-	} else {
-		xen_store_evtchn = xen_start_info->store_evtchn;
-		xen_store_mfn = xen_start_info->store_mfn;
-		if (xen_store_evtchn)
-			xenstored_ready = 1;
-		else {
+	if (xen_pv_domain())
+		usage = PV;
+	if (xen_hvm_domain())
+		usage = HVM;
+	if (xen_hvm_domain() && xen_initial_domain())
+		usage = LOCAL;
+	if (xen_pv_domain() && !xen_start_info->store_evtchn)
+		usage = LOCAL;
+	if (xen_pv_domain() && xen_start_info->store_evtchn)
+		xenstored_ready = 1;
+
+	switch (usage) {
+		case LOCAL:
 			err = xenstored_local_init();
 			if (err)
 				goto out_error;
-		}
-		xen_store_interface = mfn_to_virt(xen_store_mfn);
+			xen_store_interface = mfn_to_virt(xen_store_mfn);
+			break;
+		case PV:
+			xen_store_evtchn = xen_start_info->store_evtchn;
+			xen_store_mfn = xen_start_info->store_mfn;
+			xen_store_interface = mfn_to_virt(xen_store_mfn);
+			break;
+		case HVM:
+			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
+			if (err)
+				goto out_error;
+			xen_store_evtchn = (int)v;
+			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
+			if (err)
+				goto out_error;
+			xen_store_mfn = (unsigned long)v;
+			xen_store_interface =
+				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
+			break;
+		default:
+			pr_warn("Xenstore state unknown\n");
+			break;
 	}
 
 	/* Initialize the interface to xenstore. */
diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
index d1c217b..f7feb3d 100644
--- a/drivers/xen/xenbus/xenbus_xs.c
+++ b/drivers/xen/xenbus/xenbus_xs.c
@@ -44,6 +44,7 @@
 #include <linux/rwsem.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <asm/xen/hypervisor.h>
 #include <xen/xenbus.h>
 #include <xen/xen.h>
 #include "xenbus_comms.h"
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:11 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:11 +0100
Subject: [PATCH v2 08/23] xen/arm: Introduce xen_pfn_t for pfn and mfn types
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-8-git-send-email-stefano.stabellini@eu.citrix.com>

All the original Xen headers have xen_pfn_t as mfn and pfn type, however
when they have been imported in Linux, xen_pfn_t has been replaced with
unsigned long. That might work for x86 and ia64 but it does not for arm.
Bring back xen_pfn_t and let each architecture define xen_pfn_t as they
see fit.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/interface.h  |    4 ++++
 arch/ia64/include/asm/xen/interface.h |    5 ++++-
 arch/x86/include/asm/xen/interface.h  |    5 +++++
 include/xen/interface/grant_table.h   |    4 ++--
 include/xen/interface/memory.h        |    6 +++---
 include/xen/interface/platform.h      |    4 ++--
 include/xen/interface/xen.h           |    6 +++---
 include/xen/privcmd.h                 |    2 --
 8 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index ab99270..f904dcc 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -25,6 +25,9 @@
 	} while (0)
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the interface with
+ * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
+typedef uint64_t xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
@@ -35,6 +38,7 @@ DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
 
 /* Maximum number of virtual CPUs in multi-processor guests. */
 #define MAX_VIRT_CPUS 1
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 09d5f7f..686464e 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -67,6 +67,10 @@
 #define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the public interface
+ * with Xen so that we could have one ABI that works for 32 and 64 bit
+ * guests. */
+typedef unsigned long xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
@@ -79,7 +83,6 @@ DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
 
-typedef unsigned long xen_pfn_t;
 DEFINE_GUEST_HANDLE(xen_pfn_t);
 #define PRI_xen_pfn	"lx"
 #endif
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index a93db16..555f94d 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -47,6 +47,10 @@
 #endif
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the public interface
+ * with Xen so that on ARM we can have one ABI that works for 32 and 64
+ * bit guests. */
+typedef unsigned long xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
@@ -57,6 +61,7 @@ DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
 #endif
 
 #ifndef HYPERVISOR_VIRT_START
diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h
index a17d844..7da811b 100644
--- a/include/xen/interface/grant_table.h
+++ b/include/xen/interface/grant_table.h
@@ -338,7 +338,7 @@ DEFINE_GUEST_HANDLE_STRUCT(gnttab_dump_table);
 #define GNTTABOP_transfer                4
 struct gnttab_transfer {
     /* IN parameters. */
-    unsigned long mfn;
+    xen_pfn_t mfn;
     domid_t       domid;
     grant_ref_t   ref;
     /* OUT parameters. */
@@ -375,7 +375,7 @@ struct gnttab_copy {
 	struct {
 		union {
 			grant_ref_t ref;
-			unsigned long   gmfn;
+			xen_pfn_t   gmfn;
 		} u;
 		domid_t  domid;
 		uint16_t offset;
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index eac3ce1..abbbff0 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -31,7 +31,7 @@ struct xen_memory_reservation {
      *   OUT: GMFN bases of extents that were allocated
      *   (NB. This command also updates the mach_to_phys translation table)
      */
-    GUEST_HANDLE(ulong) extent_start;
+    GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /* Number of extents, and size/alignment of each (2^extent_order pages). */
     unsigned long  nr_extents;
@@ -130,7 +130,7 @@ struct xen_machphys_mfn_list {
      * any large discontiguities in the machine address space, 2MB gaps in
      * the machphys table will be represented by an MFN base of zero.
      */
-    GUEST_HANDLE(ulong) extent_start;
+    GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /*
      * Number of extents written to the above array. This will be smaller
@@ -172,7 +172,7 @@ struct xen_add_to_physmap {
     unsigned long idx;
 
     /* GPFN where the source mapping page should appear. */
-    unsigned long gpfn;
+    xen_pfn_t gpfn;
 };
 DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap);
 
diff --git a/include/xen/interface/platform.h b/include/xen/interface/platform.h
index 486653f..0bea470 100644
--- a/include/xen/interface/platform.h
+++ b/include/xen/interface/platform.h
@@ -54,7 +54,7 @@ DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime_t);
 #define XENPF_add_memtype         31
 struct xenpf_add_memtype {
 	/* IN variables. */
-	unsigned long mfn;
+	xen_pfn_t mfn;
 	uint64_t nr_mfns;
 	uint32_t type;
 	/* OUT variables. */
@@ -84,7 +84,7 @@ struct xenpf_read_memtype {
 	/* IN variables. */
 	uint32_t reg;
 	/* OUT variables. */
-	unsigned long mfn;
+	xen_pfn_t mfn;
 	uint64_t nr_mfns;
 	uint32_t type;
 };
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index 3871e47..42834a3 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -188,7 +188,7 @@ struct mmuext_op {
 	unsigned int cmd;
 	union {
 		/* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR */
-		unsigned long mfn;
+		xen_pfn_t mfn;
 		/* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
 		unsigned long linear_addr;
 	} arg1;
@@ -428,11 +428,11 @@ struct start_info {
 	unsigned long nr_pages;     /* Total pages allocated to this domain.  */
 	unsigned long shared_info;  /* MACHINE address of shared info struct. */
 	uint32_t flags;             /* SIF_xxx flags.                         */
-	unsigned long store_mfn;    /* MACHINE page number of shared page.    */
+	xen_pfn_t store_mfn;        /* MACHINE page number of shared page.    */
 	uint32_t store_evtchn;      /* Event channel for store communication. */
 	union {
 		struct {
-			unsigned long mfn;  /* MACHINE page number of console page.   */
+			xen_pfn_t mfn;      /* MACHINE page number of console page.   */
 			uint32_t  evtchn;   /* Event channel for console page.        */
 		} domU;
 		struct {
diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
index 4d58881..45c1aa1 100644
--- a/include/xen/privcmd.h
+++ b/include/xen/privcmd.h
@@ -37,8 +37,6 @@
 #include <linux/compiler.h>
 #include <xen/interface/xen.h>
 
-typedef unsigned long xen_pfn_t;
-
 struct privcmd_hypercall {
 	__u64 op;
 	__u64 arg[5];
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:05 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:05 +0100
Subject: [PATCH v2 02/23] xen/arm: hypercalls
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-2-git-send-email-stefano.stabellini@eu.citrix.com>

Use r12 to pass the hypercall number to the hypervisor.

We need a register to pass the hypercall number because we might not
know it at compile time and HVC only takes an immediate argument.

Among the available registers r12 seems to be the best choice because it
is defined as "intra-procedure call scratch register".

Use the ISS to pass an hypervisor specific tag.

Changes in v2:
- define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
at the moment is unused;
- use ldm instead of pop;
- fix up comments.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/hypercall.h |   50 ++++++++++++++++
 arch/arm/xen/Makefile                |    2 +-
 arch/arm/xen/hypercall.S             |  106 ++++++++++++++++++++++++++++++++++
 3 files changed, 157 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/hypercall.h
 create mode 100644 arch/arm/xen/hypercall.S

diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
new file mode 100644
index 0000000..4ac0624
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+ * hypercall.h
+ *
+ * Linux-specific hypervisor handling.
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _ASM_ARM_XEN_HYPERCALL_H
+#define _ASM_ARM_XEN_HYPERCALL_H
+
+#include <xen/interface/xen.h>
+
+long privcmd_call(unsigned call, unsigned long a1,
+		unsigned long a2, unsigned long a3,
+		unsigned long a4, unsigned long a5);
+int HYPERVISOR_xen_version(int cmd, void *arg);
+int HYPERVISOR_console_io(int cmd, int count, char *str);
+int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count);
+int HYPERVISOR_sched_op(int cmd, void *arg);
+int HYPERVISOR_event_channel_op(int cmd, void *arg);
+unsigned long HYPERVISOR_hvm_op(int op, void *arg);
+int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
+int HYPERVISOR_physdev_op(int cmd, void *arg);
+
+#endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
index 0bad594..b9d6acc 100644
--- a/arch/arm/xen/Makefile
+++ b/arch/arm/xen/Makefile
@@ -1 +1 @@
-obj-y		:= enlighten.o
+obj-y		:= enlighten.o hypercall.o
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
new file mode 100644
index 0000000..074f5ed
--- /dev/null
+++ b/arch/arm/xen/hypercall.S
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the ARM
+ * procedure calling convention: the first paramter is passed in r0, the
+ * second in r1, the third in r2 and the fourth in r3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in r4, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in r12.
+ *
+ * The return value is in r0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
+
+#define HYPERCALL_SIMPLE(hypercall)		\
+ENTRY(HYPERVISOR_##hypercall)			\
+	mov r12, #__HYPERVISOR_##hypercall;	\
+	xen_hvc;							\
+	mov pc, lr;							\
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+
+#define HYPERCALL5(hypercall)			\
+ENTRY(HYPERVISOR_##hypercall)			\
+	stmdb sp!, {r4}						\
+	ldr r4, [sp, #4]					\
+	mov r12, #__HYPERVISOR_##hypercall;	\
+	xen_hvc								\
+	ldm sp!, {r4}						\
+	mov pc, lr							\
+ENDPROC(HYPERVISOR_##hypercall)
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+
+ENTRY(privcmd_call)
+	stmdb sp!, {r4}
+	mov r12, r0
+	mov r0, r1
+	mov r1, r2
+	mov r2, r3
+	ldr r3, [sp, #8]
+	ldr r4, [sp, #4]
+	xen_hvc
+	ldm sp!, {r4}
+	mov pc, lr
+ENDPROC(privcmd_call);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:04 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:04 +0100
Subject: [PATCH v2 01/23] arm: initial Xen support
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-1-git-send-email-stefano.stabellini@eu.citrix.com>

- Basic hypervisor.h and interface.h definitions.
- Skeleton enlighten.c, set xen_start_info to an empty struct.
- Make xen_initial_domain dependent on the SIF_PRIVILIGED_BIT.

The new code only compiles when CONFIG_XEN is set, that is going to be
added to arch/arm/Kconfig in patch #11 "xen/arm: introduce CONFIG_XEN on
ARM".

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/Makefile                     |    1 +
 arch/arm/include/asm/hypervisor.h     |    6 +++
 arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
 arch/arm/include/asm/xen/interface.h  |   64 +++++++++++++++++++++++++++++++++
 arch/arm/xen/Makefile                 |    1 +
 arch/arm/xen/enlighten.c              |   35 ++++++++++++++++++
 include/xen/xen.h                     |    2 +-
 7 files changed, 127 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/hypervisor.h
 create mode 100644 arch/arm/include/asm/xen/hypervisor.h
 create mode 100644 arch/arm/include/asm/xen/interface.h
 create mode 100644 arch/arm/xen/Makefile
 create mode 100644 arch/arm/xen/enlighten.c

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00..70aaa82 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -246,6 +246,7 @@ endif
 core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)		+= arch/arm/vfp/
+core-$(CONFIG_XEN)		+= arch/arm/xen/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
new file mode 100644
index 0000000..b90d9e5
--- /dev/null
+++ b/arch/arm/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
new file mode 100644
index 0000000..d7ab99a
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypervisor.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_XEN_HYPERVISOR_H
+#define _ASM_ARM_XEN_HYPERVISOR_H
+
+extern struct shared_info *HYPERVISOR_shared_info;
+extern struct start_info *xen_start_info;
+
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+	PARAVIRT_LAZY_NONE,
+	PARAVIRT_LAZY_MMU,
+	PARAVIRT_LAZY_CPU,
+};
+
+static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
+{
+	return PARAVIRT_LAZY_NONE;
+}
+
+#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
new file mode 100644
index 0000000..ab99270
--- /dev/null
+++ b/arch/arm/include/asm/xen/interface.h
@@ -0,0 +1,64 @@
+/******************************************************************************
+ * Guest OS interface to ARM Xen.
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ */
+
+#ifndef _ASM_ARM_XEN_INTERFACE_H
+#define _ASM_ARM_XEN_INTERFACE_H
+
+#include <linux/types.h>
+
+#define __DEFINE_GUEST_HANDLE(name, type) \
+	typedef type * __guest_handle_ ## name
+
+#define DEFINE_GUEST_HANDLE_STRUCT(name) \
+	__DEFINE_GUEST_HANDLE(name, struct name)
+#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
+#define GUEST_HANDLE(name)        __guest_handle_ ## name
+
+#define set_xen_guest_handle(hnd, val)			\
+	do {						\
+		if (sizeof(hnd) == 8)			\
+			*(uint64_t *)&(hnd) = 0;	\
+		(hnd) = val;				\
+	} while (0)
+
+#ifndef __ASSEMBLY__
+/* Guest handles for primitive C types. */
+__DEFINE_GUEST_HANDLE(uchar, unsigned char);
+__DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
+DEFINE_GUEST_HANDLE(char);
+DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
+DEFINE_GUEST_HANDLE(void);
+DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
+
+/* Maximum number of virtual CPUs in multi-processor guests. */
+#define MAX_VIRT_CPUS 1
+
+struct arch_vcpu_info { };
+struct arch_shared_info { };
+
+/* XXX: Move pvclock definitions some place arch independent */
+struct pvclock_vcpu_time_info {
+	u32   version;
+	u32   pad0;
+	u64   tsc_timestamp;
+	u64   system_time;
+	u32   tsc_to_system_mul;
+	s8    tsc_shift;
+	u8    flags;
+	u8    pad[2];
+} __attribute__((__packed__)); /* 32 bytes */
+
+struct pvclock_wall_clock {
+	u32   version;
+	u32   sec;
+	u32   nsec;
+} __attribute__((__packed__));
+#endif
+
+#endif /* _ASM_ARM_XEN_INTERFACE_H */
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
new file mode 100644
index 0000000..0bad594
--- /dev/null
+++ b/arch/arm/xen/Makefile
@@ -0,0 +1 @@
+obj-y		:= enlighten.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
new file mode 100644
index 0000000..d27c2a6
--- /dev/null
+++ b/arch/arm/xen/enlighten.c
@@ -0,0 +1,35 @@
+#include <xen/xen.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/memory.h>
+#include <xen/platform_pci.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include <linux/module.h>
+
+struct start_info _xen_start_info;
+struct start_info *xen_start_info = &_xen_start_info;
+EXPORT_SYMBOL_GPL(xen_start_info);
+
+enum xen_domain_type xen_domain_type = XEN_NATIVE;
+EXPORT_SYMBOL_GPL(xen_domain_type);
+
+struct shared_info xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+
+DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+
+/* XXX: to be removed */
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
+int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+
+int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
+			       unsigned long addr,
+			       unsigned long mfn, int nr,
+			       pgprot_t prot, unsigned domid)
+{
+	return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
diff --git a/include/xen/xen.h b/include/xen/xen.h
index a164024..2c0d3a5 100644
--- a/include/xen/xen.h
+++ b/include/xen/xen.h
@@ -23,7 +23,7 @@ extern enum xen_domain_type xen_domain_type;
 #include <xen/interface/xen.h>
 #include <asm/xen/hypervisor.h>
 
-#define xen_initial_domain()	(xen_pv_domain() && \
+#define xen_initial_domain()	(xen_domain() && \
 				 xen_start_info->flags & SIF_INITDOMAIN)
 #else  /* !CONFIG_XEN_DOM0 */
 #define xen_initial_domain()	(0)
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:12 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:12 +0100
Subject: [PATCH v2 09/23] xen/arm: Introduce xen_ulong_t for unsigned long
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-9-git-send-email-stefano.stabellini@eu.citrix.com>

All the original Xen headers have xen_ulong_t as unsigned long type, however
when they have been imported in Linux, xen_ulong_t has been replaced with
unsigned long. That might work for x86 and ia64 but it does not for arm.
Bring back xen_ulong_t and let each architecture define xen_ulong_t as they
see fit.

Also explicitly size pointers (__DEFINE_GUEST_HANDLE) to 64 bit.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/interface.h  |    8 ++++++--
 arch/ia64/include/asm/xen/interface.h |    1 +
 arch/x86/include/asm/xen/interface.h  |    1 +
 include/xen/interface/memory.h        |   12 ++++++------
 include/xen/interface/physdev.h       |    4 ++--
 include/xen/interface/version.h       |    2 +-
 include/xen/interface/xen.h           |    6 +++---
 7 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index f904dcc..1d3030c 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -9,8 +9,11 @@
 
 #include <linux/types.h>
 
+#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
+
 #define __DEFINE_GUEST_HANDLE(name, type) \
-	typedef type * __guest_handle_ ## name
+	typedef struct { union { type *p; uint64_aligned_t q; }; }  \
+        __guest_handle_ ## name
 
 #define DEFINE_GUEST_HANDLE_STRUCT(name) \
 	__DEFINE_GUEST_HANDLE(name, struct name)
@@ -21,13 +24,14 @@
 	do {						\
 		if (sizeof(hnd) == 8)			\
 			*(uint64_t *)&(hnd) = 0;	\
-		(hnd) = val;				\
+		(hnd).p = val;				\
 	} while (0)
 
 #ifndef __ASSEMBLY__
 /* Explicitly size integers that represent pfns in the interface with
  * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
 typedef uint64_t xen_pfn_t;
+typedef uint64_t xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 686464e..7c83445 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -71,6 +71,7 @@
  * with Xen so that we could have one ABI that works for 32 and 64 bit
  * guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index 555f94d..28fc621 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -51,6 +51,7 @@
  * with Xen so that on ARM we can have one ABI that works for 32 and 64
  * bit guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index abbbff0..b5c3098 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -34,7 +34,7 @@ struct xen_memory_reservation {
     GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /* Number of extents, and size/alignment of each (2^extent_order pages). */
-    unsigned long  nr_extents;
+    xen_ulong_t  nr_extents;
     unsigned int   extent_order;
 
     /*
@@ -92,7 +92,7 @@ struct xen_memory_exchange {
      *     command will be non-zero.
      *  5. THIS FIELD MUST BE INITIALISED TO ZERO BY THE CALLER!
      */
-    unsigned long nr_exchanged;
+    xen_ulong_t nr_exchanged;
 };
 
 DEFINE_GUEST_HANDLE_STRUCT(xen_memory_exchange);
@@ -148,8 +148,8 @@ DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list);
  */
 #define XENMEM_machphys_mapping     12
 struct xen_machphys_mapping {
-    unsigned long v_start, v_end; /* Start and end virtual addresses.   */
-    unsigned long max_mfn;        /* Maximum MFN that can be looked up. */
+    xen_ulong_t v_start, v_end; /* Start and end virtual addresses.   */
+    xen_ulong_t max_mfn;        /* Maximum MFN that can be looked up. */
 };
 DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mapping_t);
 
@@ -169,7 +169,7 @@ struct xen_add_to_physmap {
     unsigned int space;
 
     /* Index into source mapping space. */
-    unsigned long idx;
+    xen_ulong_t idx;
 
     /* GPFN where the source mapping page should appear. */
     xen_pfn_t gpfn;
@@ -186,7 +186,7 @@ struct xen_translate_gpfn_list {
     domid_t domid;
 
     /* Length of list. */
-    unsigned long nr_gpfns;
+    xen_ulong_t nr_gpfns;
 
     /* List of GPFNs to translate. */
     GUEST_HANDLE(ulong) gpfn_list;
diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h
index 9ce788d..bc3ae14 100644
--- a/include/xen/interface/physdev.h
+++ b/include/xen/interface/physdev.h
@@ -56,7 +56,7 @@ struct physdev_eoi {
 #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
 struct physdev_pirq_eoi_gmfn {
     /* IN */
-    unsigned long gmfn;
+    xen_ulong_t gmfn;
 };
 
 /*
@@ -108,7 +108,7 @@ struct physdev_set_iobitmap {
 #define PHYSDEVOP_apic_write		 9
 struct physdev_apic {
 	/* IN */
-	unsigned long apic_physbase;
+	xen_ulong_t apic_physbase;
 	uint32_t reg;
 	/* IN or OUT */
 	uint32_t value;
diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h
index e8b6519..30280c9 100644
--- a/include/xen/interface/version.h
+++ b/include/xen/interface/version.h
@@ -45,7 +45,7 @@ struct xen_changeset_info {
 
 #define XENVER_platform_parameters 5
 struct xen_platform_parameters {
-    unsigned long virt_start;
+    xen_ulong_t virt_start;
 };
 
 #define XENVER_get_features 6
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index 42834a3..ec32115 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -274,9 +274,9 @@ DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
  * NB. The fields are natural register size for this architecture.
  */
 struct multicall_entry {
-    unsigned long op;
-    long result;
-    unsigned long args[6];
+    xen_ulong_t op;
+    xen_ulong_t result;
+    xen_ulong_t args[6];
 };
 DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
 
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:06 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:06 +0100
Subject: [PATCH v2 03/23] xen/arm: page.h definitions
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-3-git-send-email-stefano.stabellini@eu.citrix.com>

ARM Xen guests always use paging in hardware, like PV on HVM guests in
the X86 world.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/page.h |   79 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/page.h

diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
new file mode 100644
index 0000000..fe78331
--- /dev/null
+++ b/arch/arm/include/asm/xen/page.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_ARM_XEN_PAGE_H
+#define _ASM_ARM_XEN_PAGE_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <linux/pfn.h>
+#include <linux/types.h>
+
+#include <xen/interface/grant_table.h>
+
+#define pfn_to_mfn(pfn)			(pfn)
+#define phys_to_machine_mapping_valid	(1)
+#define mfn_to_pfn(mfn)			(mfn)
+#define mfn_to_virt(m)			(__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+#define pte_mfn	    pte_pfn
+#define mfn_pte	    pfn_pte
+
+/* Xen machine address */
+typedef struct xmaddr {
+	phys_addr_t maddr;
+} xmaddr_t;
+
+/* Xen pseudo-physical address */
+typedef struct xpaddr {
+	phys_addr_t paddr;
+} xpaddr_t;
+
+#define XMADDR(x)	((xmaddr_t) { .maddr = (x) })
+#define XPADDR(x)	((xpaddr_t) { .paddr = (x) })
+
+static inline xmaddr_t phys_to_machine(xpaddr_t phys)
+{
+	unsigned offset = phys.paddr & ~PAGE_MASK;
+	return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+}
+
+static inline xpaddr_t machine_to_phys(xmaddr_t machine)
+{
+	unsigned offset = machine.maddr & ~PAGE_MASK;
+	return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+}
+/* VIRT <-> MACHINE conversion */
+#define virt_to_machine(v)	(phys_to_machine(XPADDR(__pa(v))))
+#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
+#define virt_to_mfn(v)		(pfn_to_mfn(virt_to_pfn(v)))
+#define mfn_to_virt(m)		(__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr)
+{
+	/* XXX: assuming it is mapped in the kernel 1:1 */
+	return virt_to_machine(vaddr);
+}
+
+/* XXX: this shouldn't be here */
+static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
+{
+	BUG();
+	return NULL;
+}
+
+static inline int m2p_add_override(unsigned long mfn, struct page *page,
+		struct gnttab_map_grant_ref *kmap_op)
+{
+	return 0;
+}
+
+static inline int m2p_remove_override(struct page *page, bool clear_pte)
+{
+	return 0;
+}
+
+static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+	BUG();
+	return false;
+}
+#endif /* _ASM_ARM_XEN_PAGE_H */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:08 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:08 +0100
Subject: [PATCH v2 05/23] xen/arm: empty implementation of grant_table arch
 specific functions
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-5-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- return -ENOSYS rather than -1.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/Makefile      |    2 +-
 arch/arm/xen/grant-table.c |   53 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/xen/grant-table.c

diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
index b9d6acc..4384103 100644
--- a/arch/arm/xen/Makefile
+++ b/arch/arm/xen/Makefile
@@ -1 +1 @@
-obj-y		:= enlighten.o hypercall.o
+obj-y		:= enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
new file mode 100644
index 0000000..dbd1330
--- /dev/null
+++ b/arch/arm/xen/grant-table.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * grant_table.c
+ * ARM specific part
+ *
+ * Granting foreign access to our memory reservation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <xen/interface/xen.h>
+#include <xen/page.h>
+#include <xen/grant_table.h>
+
+int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
+			   unsigned long max_nr_gframes,
+			   void **__shared)
+{
+	return -ENOSYS;
+}
+
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
+{
+	return;
+}
+
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+			   unsigned long max_nr_gframes,
+			   grant_status_t **__shared)
+{
+	return -ENOSYS;
+}
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:07 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:07 +0100
Subject: [PATCH v2 04/23] xen/arm: sync_bitops
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-4-git-send-email-stefano.stabellini@eu.citrix.com>

sync_bitops functions are equivalent to the SMP implementation of the
original functions, independently from CONFIG_SMP being defined.

We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
under Xen you might be communicating with a completely external entity
who might be on another CPU (e.g. two uniprocessor guests communicating
via event channels and grant tables). So we need a variant of the bit
ops which are SMP safe even on a UP kernel.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/sync_bitops.h |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/sync_bitops.h

diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
new file mode 100644
index 0000000..63479ee
--- /dev/null
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/system.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)		_set_bit(nr, p)
+#define sync_clear_bit(nr, p)		_clear_bit(nr, p)
+#define sync_change_bit(nr, p)		_change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)	_test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p)	_test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p)	_test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)		test_bit(nr, addr)
+#define sync_cmpxchg			cmpxchg
+
+
+#endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:09 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:09 +0100
Subject: [PATCH v2 06/23] xen: missing includes
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-6-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:
- remove pvclock hack;
- remove include linux/types.h from xen/interface/xen.h.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/x86/include/asm/xen/interface.h       |    2 ++
 drivers/tty/hvc/hvc_xen.c                  |    2 ++
 drivers/xen/grant-table.c                  |    1 +
 drivers/xen/xenbus/xenbus_probe_frontend.c |    1 +
 include/xen/interface/xen.h                |    1 -
 include/xen/privcmd.h                      |    1 +
 6 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index cbf0c9d..a93db16 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -121,6 +121,8 @@ struct arch_shared_info {
 #include "interface_64.h"
 #endif
 
+#include <asm/pvclock-abi.h>
+
 #ifndef __ASSEMBLY__
 /*
  * The following is all CPU context. Note that the fpu_ctxt block is filled
diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
index 944eaeb..dc07f56 100644
--- a/drivers/tty/hvc/hvc_xen.c
+++ b/drivers/tty/hvc/hvc_xen.c
@@ -21,6 +21,7 @@
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/list.h>
@@ -35,6 +36,7 @@
 #include <xen/page.h>
 #include <xen/events.h>
 #include <xen/interface/io/console.h>
+#include <xen/interface/sched.h>
 #include <xen/hvc-console.h>
 #include <xen/xenbus.h>
 
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
index 0bfc1ef..1d0d95e 100644
--- a/drivers/xen/grant-table.c
+++ b/drivers/xen/grant-table.c
@@ -47,6 +47,7 @@
 #include <xen/interface/memory.h>
 #include <xen/hvc-console.h>
 #include <asm/xen/hypercall.h>
+#include <asm/xen/interface.h>
 
 #include <asm/pgtable.h>
 #include <asm/sync_bitops.h>
diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
index a31b54d..3159a37 100644
--- a/drivers/xen/xenbus/xenbus_probe_frontend.c
+++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
@@ -21,6 +21,7 @@
 #include <xen/xenbus.h>
 #include <xen/events.h>
 #include <xen/page.h>
+#include <xen/xen.h>
 
 #include <xen/platform_pci.h>
 
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index a890804..3871e47 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -10,7 +10,6 @@
 #define __XEN_PUBLIC_XEN_H__
 
 #include <asm/xen/interface.h>
-#include <asm/pvclock-abi.h>
 
 /*
  * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
index 17857fb..4d58881 100644
--- a/include/xen/privcmd.h
+++ b/include/xen/privcmd.h
@@ -35,6 +35,7 @@
 
 #include <linux/types.h>
 #include <linux/compiler.h>
+#include <xen/interface/xen.h>
 
 typedef unsigned long xen_pfn_t;
 
-- 
1.7.2.5



From s.hauer at pengutronix.de  Mon Aug  6 10:35:35 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 6 Aug 2012 16:35:35 +0200
Subject: [PATCH] ARM: imx35: don't disable the uart clock when DEBUG_LL
 is in use
In-Reply-To: <20120806142406.GC9329@pengutronix.de>
References: <1343742279-29570-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120731174358.GC30009@pengutronix.de>
 <20120731183206.GC10670@pengutronix.de>
 <20120806142406.GC9329@pengutronix.de>
Message-ID: <20120806143535.GC1451@pengutronix.de>

On Mon, Aug 06, 2012 at 04:24:06PM +0200, Uwe Kleine-K?nig wrote:
> On Tue, Jul 31, 2012 at 08:32:06PM +0200, Uwe Kleine-K?nig wrote:
> > Hello Sascha,
> > 
> > On Tue, Jul 31, 2012 at 07:43:58PM +0200, Sascha Hauer wrote:
> > > On Tue, Jul 31, 2012 at 03:44:39PM +0200, Uwe Kleine-K?nig wrote:
> > > > Otherwise printch et al. and printk with earlyprintk and keep_bootcon
> > > > becomes unfunctional when the clk framework disables all unused clocks.
> > > 
> > > Why don't you use the regular console? Letting the clock framework
> > > disable the clocks was pretty much intentional.
> > I don't question that disabling unused clocks is sensible. But usually
> > if you enable DEBUG_LL you want to use it even after the clock framework
> > disabled all (apparently) unused clocks. And in my case the regular
> > console didn't work yet and so I relied on earlyprintk.
> > Even if the problem proved to be the result of my stupidity this patch
> > asserts that earlyprintk just works as it should be for debug aids.
> ping

Honestly, I don't think this is a good idea. You fixed one UART on one
SoC, so ARRAY_SIZE(i.MX1, i.MX21, i.MX25, i.MX27, i.MX31, i.MX35,
i.MX51, i.MX53, i.MX6) * NUM_UARTS remain broken for this usecase. IMO
DEBUG_LL is to get some stuff out of an otherwise silent board, nothing
more.

Sascha



-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Mon Aug  6 10:35:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 14:35:44 +0000
Subject: [PATCH v2 0/5] Use more asm-generic headers
In-Reply-To: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
References: <1344129840-16447-1-git-send-email-robherring2@gmail.com>
Message-ID: <201208061435.44216.arnd@arndb.de>

On Sunday 05 August 2012, Rob Herring wrote:
> 
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Inspired by the AArgh64 claim that it should be separate from ARM and one
> reason was being able to use more asm-generic headers. Doing a diff of
> arch/arm/include/asm and include/asm-generic there are numerous asm
> headers which are functionally identical to their asm-generic counterparts
> and others which can use more of the generic versions.
> 
> V2 separates unaligned.h and termios.h changes to separate patches. Also,
> it adds a fix for build failures on non-gzip decompressor compile.
> 

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:10 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:10 +0100
Subject: [PATCH v2 07/23] xen/arm: Xen detection and shared_info page mapping
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>

Check for a "/xen" node in the device tree, if it is present set
xen_domain_type to XEN_HVM_DOMAIN and continue initialization.

Map the real shared info page using XENMEM_add_to_physmap with
XENMAPSPACE_shared_info.

Changes in v2:

- replace pr_info with pr_debug.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 52 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index d27c2a6..102d823 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -5,6 +5,9 @@
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 struct start_info _xen_start_info;
 struct start_info *xen_start_info = &_xen_start_info;
@@ -33,3 +36,52 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 	return -ENOSYS;
 }
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+
+/*
+ * == Xen Device Tree format ==
+ * - /xen node;
+ * - compatible "arm,xen";
+ * - one interrupt for Xen event notifications;
+ * - one memory region to map the grant_table.
+ */
+static int __init xen_guest_init(void)
+{
+	struct xen_add_to_physmap xatp;
+	static struct shared_info *shared_info_page = 0;
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,xen");
+	if (!node) {
+		pr_debug("No Xen support\n");
+		return 0;
+	}
+	xen_domain_type = XEN_HVM_DOMAIN;
+
+	if (!shared_info_page)
+		shared_info_page = (struct shared_info *)
+			get_zeroed_page(GFP_KERNEL);
+	if (!shared_info_page) {
+		pr_err("not enough memory\n");
+		return -ENOMEM;
+	}
+	xatp.domid = DOMID_SELF;
+	xatp.idx = 0;
+	xatp.space = XENMAPSPACE_shared_info;
+	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+		BUG();
+
+	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+	 * page, we use it in the event channel upcall and in some pvclock
+	 * related functions. We don't need the vcpu_info placement
+	 * optimizations because we don't use any pv_mmu or pv_irq op on
+	 * HVM.
+	 * The shared info contains exactly 1 CPU (the boot CPU). The guest
+	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
+	 * for secondary CPUs as they are brought up. */
+	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+	return 0;
+}
+core_initcall(xen_guest_init);
-- 
1.7.2.5



From arnd at arndb.de  Mon Aug  6 10:37:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 14:37:52 +0000
Subject: [PATCH] ARM: integrator: use clk_prepare_enable() for timer
In-Reply-To: <CACRpkdZqaJhCYuW+3WYacjuwJ3zshAexDqLSUJgCCDzVS+=X7g@mail.gmail.com>
References: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>
 <CACRpkdZqaJhCYuW+3WYacjuwJ3zshAexDqLSUJgCCDzVS+=X7g@mail.gmail.com>
Message-ID: <201208061437.52415.arnd@arndb.de>

On Sunday 05 August 2012, Linus Walleij wrote:
> On Sun, Aug 5, 2012 at 10:37 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> > The Integrator timer is using the clock framework to get the
> > timer frequency, but missed to prepare the clock before enabling.
> >
> > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Arnd, Olof,
> 
> If this patch looks OK to you I request that you apply it alone, no pull
> requests, too much hazzle for a single patch...
> 

Applying a patch is fine, but please explain which version(s) to apply
this to? Is it a regression in v3.6, or should it be backported to
earlier versions too?

	Arnd


From u.kleine-koenig at pengutronix.de  Mon Aug  6 10:41:00 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 6 Aug 2012 16:41:00 +0200
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120803131230.GB23791@S2101-09.ap.freescale.net>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803131230.GB23791@S2101-09.ap.freescale.net>
Message-ID: <20120806144100.GD9329@pengutronix.de>

Hello,

On Fri, Aug 03, 2012 at 09:12:32PM +0800, Shawn Guo wrote:
> On Thu, Aug 02, 2012 at 05:56:25PM +0200, Uwe Kleine-K?nig wrote:
> > From: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> > 
> > This patch adds basic support for imx35-based devices to the kernel.
> > 
> > Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > ---
> >  arch/arm/boot/dts/imx35.dtsi            |  246 +++++++++++++++++++++++++++++++
> >  arch/arm/configs/imx_v6_v7_defconfig    |    1 +
> >  arch/arm/mach-imx/Kconfig               |   13 ++
> >  arch/arm/mach-imx/Makefile              |    1 +
> >  arch/arm/mach-imx/imx35-dt.c            |  119 +++++++++++++++
> >  arch/arm/plat-mxc/include/mach/common.h |    2 +
> >  6 files changed, 382 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx35.dtsi
> >  create mode 100644 arch/arm/mach-imx/imx35-dt.c
> > 
> > diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
> > new file mode 100644
> > index 0000000..d0c6456
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx35.dtsi
> > @@ -0,0 +1,246 @@
> > +/*
> > + * Copyright 2012 Steffen Trumtrar, Pengutronix
> > + *
> > + * based on imx27.dtsi
> > + *
> > + * This program is free software; you can redistribute it and/or modify it under
> > + * the terms of the GNU General Public License version 2 as published by the
> > + * Free Software Foundation.
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
> > +/ {
> > +	aliases {
> > +		serial0 = &uart1;
> > +		serial1 = &uart2;
> > +		serial2 = &uart3;
I will add gpio aliases here in the next round.

> > +	};
> > +
> > +	avic: avic-interrupt-controller at 68000000 {
> > +		compatible = "fsl,imx35-avic", "fsl,avic";
> > +		interrupt-controller;
> > +		#interrupt-cells = <1>;
> > +		reg = <0x68000000 0x10000000>;
> > +	};
> > +
> > +	clocks {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		ckil {
> > +			compatible = "fsl,imx-ckil", "fixed-clock";
> > +			clock-frequency = <32768>;
> > +		};
> > +
> > +		osc {
> > +			compatible = "fsl,imx-osc", "fixed-clock";
> > +			clock-frequency = <24000000>;
> > +		};
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		cpu at 0 {
> > +			device_type = "cpu";
> 
> This is not really necessary, IIRC.
ok, can drop that.
> 
> > +			compatible = "fsl,imx35", "arm,arm1136jfs";
> > +			reg = <0>;
> > +			d-cache-size = <0x4000>;	// L1, 16K
> > +			i-cache-size = <0x4000>;	// L1, 16K
> 
> Are these two common bindings?  Documented in
> Documentation/devicetree/bindings for somewhere?
Don't know, that part wass written by Steffen. I will look into the
other imx.dtsi files and make it use the same idioms.
 
> > +			bus-frequency = <0>;		// from bootloader
> 
> Ditto.  I'm not even sure how this works.  Does your bootloader
> really populates this property?  Which bus?
No it doesn't. As above ...

> > +		};
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "simple-bus";
> > +		interrupt-parent = <&avic>;
> > +		ranges;
> > +
> > +		aips at 40000000 { /* AIPS1 */
> > +			compatible = "fsl,aips", "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x40000000 0x100000>;
> > +			ranges;
> > +
> > +			i2c1: i2c at 43f80000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> > +				reg = <0x43f80000 0x4000>;
> > +				interrupts = <10>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c3: i2c at 43f84000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> > +				reg = <0x43f84000 0x4000>;
> > +				interrupts = <3>;
> > +				status = "disabled";
> > +			};
> > +
> > +			uart1: uart at 43f90000 {
> 
> Name the node "serial".
ok

> 
> > +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> > +				reg = <0x43f90000 0x4000>;
> > +				interrupts = <45>;
> > +				status = "disabled";
> > +			};
> > +
> > +			uart2: uart at 43f94000 {
> > +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> > +				reg = <0x43f94000 0x4000>;
> > +				interrupts = <32>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c2: i2c at 43f98000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> > +				reg = <0x43f98000 0x4000>;
> > +				interrupts = <4>;
> > +				status = "disabled";
> > +			};
> 
> We generally have a new line between nodes.
fine for me.

> > +			iomuxc at 43fac000 {
> > +				compatible = "fsl,imx35-iomuxc";
> > +				reg = <0x43fac000 0x4000>;
> > +
> > +				i2c3 {
> > +					pinctrl_i2c3_1: i2c3grp-1 {
> > +						fsl,pins = <773 0x1c0 /* MX35_PAD_ATA_DATA12__I2C3_SCL */
> > +							777 0x1c0>; /* MX35_PAD_ATA_DATA13__I2C3_SDA */
> > +					};
> > +				};
> > +
> > +				can1 {
> > +					pinctrl_can1_1: can1grp-1 {
> > +						fsl,pins = <223 0x1c0 /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
> > +							228 0x1c0>; /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
> > +					};
> > +				};
> > +				can2 {
> > +					pinctrl_can2_1: can2grp-1 {
> > +						fsl,pins = <291 0x1c0 /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
> > +							298 0x1c0>; /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
> > +					};
> > +				};
> > +
> > +			};
> > +		};
> > +
> > +		spba at 50000000 {
> > +			compatible = "fsl,spba-bus", "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x50000000 0x100000>;
> > +			ranges;
> > +
> > +			uart3: uart at 5000c000 {
> > +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> > +				reg = <0x5000c000 0x4000>;
> > +				interrupts = <18>;
> > +				status = "disabled";
> > +			};
> > +
> > +			fec: fec at 50038000 {
> > +				compatible = "fsl,imx35-fec", "fsl,imx27-fec";
> > +				reg = <0x50038000 0x4000>;
> > +				interrupts = <57>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +
> > +		aips at 53f00000 { /* AIPS2 */
> > +			compatible = "fsl,aips", "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x53f00000 0xffc0000>;
> > +			ranges;
> > +
> > +			gpio3: gpio at 0x53fa4000 {
> > +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> 
> compatible = "fsl,imx35-gpio";
> 
> > +				reg = <0x53fa4000 0x4000>;
> > +				interrupts = <56>;
> > +				gpio-controller;
> > +				#gpio-cells = <2>;
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> 
> It should be 2 now.
> 
> > +			};
> > +
> > +			esdhc1: esdhc at 53fb4000 {
> > +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
> 
> compatible = "fsl,imx35-esdhc";
> 
> > +				reg = <0x53fb4000 0x4000>;
> > +				interrupts = <7>;
> > +				status = "disabled";
> > +			};
> > +
> > +			esdhc2: esdhc at 53fb8000 {
> > +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
> > +				reg = <0x53fb8000 0x4000>;
> > +				interrupts = <8>;
> > +				status = "disabled";
> > +			};
> > +
> > +			esdhc3: esdhc at 53fbc000 {
> > +				compatible = "fsl,mx35-sdhc", "fsl,esdhc";
> > +				reg = <0x53fbc000 0x4000>;
> > +				interrupts = <9>;
> > +				status = "disabled";
> > +			};
> > +
> > +			gpio1: gpio at 0x53fcc000 {
> > +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> > +				reg = <0x53fcc000 0x4000>;
> > +				interrupts = <52>;
> > +				gpio-controller;
> > +				#gpio-cells = <2>;
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +
> > +			gpio2: gpio at 0x53fd0000 {
> > +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> > +				reg = <0x53fd0000 0x4000>;
> > +				interrupts = <51>;
> > +				gpio-controller;
> > +				#gpio-cells = <2>;
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +
> > +			wdog at 53fdc000 {
> > +				compatible = "fsl,imx35-wdt", "fsl,imx2-wdt";
> > +				reg = <0x53fdc000 0x4000>;
> > +				interrupts = <55>;
> > +				status = "disabled";
> 
> Drop status to have wdog such completely SoC internal stuff enabled by
> default.
Ah I remember to have seen the corresponding patches. OK.
 
> > +			};
> > +
> > +			can at 53fe4000 {
> > +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> > +				reg = <0x53fe4000 0x1000>;
> > +				interrupts = <43>;
> > +				status = "disabled";
> > +			};
> > +			can at 53fe8000 {
> > +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> > +				reg = <0x53fe8000 0x1000>;
> > +				interrupts = <44>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +		nand at bb000000 {
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +
> > +			compatible = "fsl,imx35-nand", "fsl,imx25-nand";
> > +			reg = <0xbb000000 0x2000>;
> > +			interrupts = <33>;
> > +			status = "disabled";
> > +		};
> 
> Why nand device isn't under any bus but soc directly?
I copied that from imx27.dtsi (where I introduced it myself before).
It's not obvious to me which bus this is a part of from reading the
hardware manual. Neither for i.MX27 nor i.MX35.
> 
> > +	};
> > +};
> > diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> > index b1d3675..9389ab6 100644
> > --- a/arch/arm/configs/imx_v6_v7_defconfig
> > +++ b/arch/arm/configs/imx_v6_v7_defconfig
> > @@ -26,6 +26,7 @@ CONFIG_MACH_ARMADILLO5X0=y
> >  CONFIG_MACH_KZM_ARM11_01=y
> >  CONFIG_MACH_PCM043=y
> >  CONFIG_MACH_MX35_3DS=y
> > +CONFIG_MACH_IMX35_DT=y
> >  CONFIG_MACH_VPR200=y
> >  CONFIG_MACH_IMX51_DT=y
> >  CONFIG_MACH_MX51_3DS=y
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index eff4db5..95f9d6a 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -644,6 +644,19 @@ config MACH_VPR200
> >  	  Include support for VPR200 platform. This includes specific
> >  	  configurations for the board and its peripherals.
> >  
> > +config MACH_IMX35_DT
> > +	bool "Support i.MX35 platforms from device tree"
> > +	select SOC_IMX35
> > +	select USE_OF
> 
> USE_OF is selected by ARCH_MXC now.
ah right.

> 
> > +	select HAVE_CAN_FLEXCAN if CAN
> 
> Move it to "config SOC_IMX35".
hmm, do we want CAN_FLEXCAN to be selectable for machines that don't
have can although they are based on i.MX35?

> 
> > +	select IMX_HAVE_PLATFORM_MXC_NAND
> > +	select IMX_HAVE_PLATFORM_SPI_IMX
> > +	select IMX_HAVE_PLATFORM_IMX2_WDT
> 
> These are unreasonable.
These are needed to be able to select the corresponding drivers.

> 
> > +	select PINCTRL
> 
> Need to select PINCTRL_IMX35 also?
good idea.

> And they should be under "config SOC_IMX35".
Even though currently the pincontrol driver isn't used for them?
 
> > +	help
> > +	  Include support for Freescale i.MX35 based platforms
> > +	  using the device tree for discovery
> > +
> >  comment "i.MX5 platforms:"
> >  
> >  config MACH_MX50_RDP
> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> > index ff29421..97d01b5 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
> > @@ -64,6 +64,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
> >  obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
> >  obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
> >  obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
> > +obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
> >  
> >  obj-$(CONFIG_DEBUG_LL) += lluart.o
> >  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> > diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
> > new file mode 100644
> > index 0000000..8b9cc84
> > --- /dev/null
> > +++ b/arch/arm/mach-imx/imx35-dt.c
> > @@ -0,0 +1,119 @@
> > +/*
> > + * Copyright 2012 Steffen Trumtrar, Pengutronix
> > + *
> > + * based on imx27-dt.c
> > + *
> > + * This program is free software; you can redistribute it and/or modify it under
> > + * the terms of the GNU General Public License version 2 as published by the
> > + * Free Software Foundation.
> > + */
> > +#include <linux/irq.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pinctrl/machine.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach/time.h>
> > +#include <mach/common.h>
> > +#include <mach/mx35.h>
> > +
> > +static const struct of_dev_auxdata imx35_auxdata_lookup[] __initconst = {
> > +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART1_BASE_ADDR, "imx21-uart.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART2_BASE_ADDR, "imx21-uart.1", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-uart", MX35_UART3_BASE_ADDR, "imx21-uart.2", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-fec", MX35_FEC_BASE_ADDR, "imx27-fec.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-wdt", MX35_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-i2c", MX35_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx35.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx35.1", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-sdhc", MX35_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx35.2", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx35-nand", MX35_NFC_BASE_ADDR, "mxc_nand.0", NULL),
> > +	{ /* sentinel */ }
> > +};
> 
> If these auxdata are here only for clk lookup, we can save them by
> having DT specific clkdev lookup in clock driver.
ok.

> 
> > +
> > +static int __init imx35_avic_add_irq_domain(struct device_node *np,
> > +				struct device_node *interrupt_parent)
> > +{
> > +	irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
> > +	return 0;
> > +}
> > +
> > +static int __init imx35_gpio_add_irq_domain(struct device_node *np,
> > +				struct device_node *interrupt_parent)
> > +{
> > +	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
> > +
> > +	gpio_irq_base -= 32;
> > +	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
> > +				NULL);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id imx35_irq_match[] __initconst = {
> > +	{ .compatible = "fsl,imx35-avic", .data = imx35_avic_add_irq_domain, },
> > +	{ .compatible = "fsl,imx35-gpio", .data = imx35_gpio_add_irq_domain, },
> > +	{ /* sentinel */ }
> > +};
> 
> All these are not needed now.
ok.

> 
> > +
> > +static const struct of_device_id imx35_of_mixed_devices_match[] __initconst = {
> > +	{ /* END OF LIST */ }
> > +};
> > +
> > +static void __init of_mixed_device_hook(void)
> > +{
> > +	struct device_node *np;
> > +	const struct of_device_id *of_id;
> > +
> > +	np = of_find_matching_node(NULL, imx35_of_mixed_devices_match);
> > +	if (np) {
> > +		void (*func)(void);
> > +
> > +		of_id = of_match_node(imx35_of_mixed_devices_match, np);
> > +		func = of_id->data;
> > +		func();
> > +	}
> > +}
> 
> We have this on other imx DT machines for hooking the IOMUX setup done
> in non-DT board files.  Since you have imx35 pinctrl support in place.
> What is above hook for then?
I need it to configure and export some gpios.

> > +static void __init imx35_dt_init(void)
> > +{
> > +	of_irq_init(imx35_irq_match);
> > +
> > +	/* Some mx35 have problems when the cache is not initialized
> > +	 * FIXME: ultimatly this belongs in the oftree definition
> > +	 */
> > +	imx3_init_l2x0();
> > +	pinctrl_provide_dummies();
> > +
> > +	of_platform_populate(NULL, of_default_bus_match_table,
> > +			     imx35_auxdata_lookup, NULL);
> > +
> > +	of_mixed_device_hook();
> > +}
> > +
> > +static void __init imx35_timer_init(void)
> > +{
> > +	mx35_clocks_init();
> > +}
> > +
> > +static struct sys_timer imx35_timer = {
> > +	.init = imx35_timer_init,
> > +};
> > +
> > +static const char *imx35_dt_board_compat[] __initdata = {
> > +	"fsl,imx35",
> > +	NULL
> > +};
> > +
> > +DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
> > +	.map_io		= mx35_map_io,
> > +	.init_early	= imx35_init_early,
> > +	.init_irq	= mx35_init_irq,
> > +	.handle_irq	= imx35_handle_irq,
> > +	.timer		= &imx35_timer,
> > +	.init_machine	= imx35_dt_init,
> > +	.dt_compat	= imx35_dt_board_compat,
> > +	.restart	= mxc_restart,
> > +MACHINE_END
> > diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> > index e429ca1..643b0aa 100644
> > --- a/arch/arm/plat-mxc/include/mach/common.h
> > +++ b/arch/arm/plat-mxc/include/mach/common.h
> > @@ -50,6 +50,7 @@ extern void imx25_soc_init(void);
> >  extern void imx27_soc_init(void);
> >  extern void imx31_soc_init(void);
> >  extern void imx35_soc_init(void);
> > +extern void imx3_init_l2x0(void);
> >  extern void imx50_soc_init(void);
> >  extern void imx51_soc_init(void);
> >  extern void imx53_soc_init(void);
> > @@ -67,6 +68,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
> >  extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
> >  			unsigned long ckih1, unsigned long ckih2);
> >  extern int mx27_clocks_init_dt(void);
> > +extern int mx35_clocks_init_dt(void);
> 
> It does not necessarily belong this driver.
I cannot parse this sentence. Can you please try to explain again your
objections here?

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linus.walleij at linaro.org  Mon Aug  6 10:46:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 6 Aug 2012 16:46:43 +0200
Subject: [PATCH] ARM: integrator: use clk_prepare_enable() for timer
In-Reply-To: <201208061437.52415.arnd@arndb.de>
References: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>
 <CACRpkdZqaJhCYuW+3WYacjuwJ3zshAexDqLSUJgCCDzVS+=X7g@mail.gmail.com>
 <201208061437.52415.arnd@arndb.de>
Message-ID: <CACRpkdaqFqE5D5LkT0buof_5YZkpP_J_Y6qu0B5gKi4W3mFEkw@mail.gmail.com>

On Mon, Aug 6, 2012 at 4:37 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Sunday 05 August 2012, Linus Walleij wrote:
>> On Sun, Aug 5, 2012 at 10:37 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
>> > The Integrator timer is using the clock framework to get the
>> > timer frequency, but missed to prepare the clock before enabling.
>> >
>> > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>>
>> Arnd, Olof,
>>
>> If this patch looks OK to you I request that you apply it alone, no pull
>> requests, too much hazzle for a single patch...
>>
>
> Applying a patch is fine, but please explain which version(s) to apply
> this to? Is it a regression in v3.6, or should it be backported to
> earlier versions too?

Ah sorry. This is for the v3.6 rc:s.

The migration to common clock makes the kernel spit warnings
unless you prepare all clocks.

Yours,
Linus Walleij


From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:20 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:20 +0100
Subject: [PATCH v2 17/23] xen/arm: implement alloc/free_xenballooned_pages
 with alloc_pages/kfree
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-17-git-send-email-stefano.stabellini@eu.citrix.com>

Only until we get the balloon driver to work.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 87b17f0..c244583 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -140,3 +140,21 @@ static int __init xen_init_events(void)
 	return 0;
 }
 postcore_initcall(xen_init_events);
+
+/* XXX: only until balloon is properly working */
+int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
+{
+	*pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
+			get_order(nr_pages));
+	if (*pages == NULL)
+		return -ENOMEM;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
+
+void free_xenballooned_pages(int nr_pages, struct page **pages)
+{
+	kfree(*pages);
+	*pages = NULL;
+}
+EXPORT_SYMBOL_GPL(free_xenballooned_pages);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:22 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:22 +0100
Subject: [PATCH v2 19/23] xen/arm: compile blkfront and blkback
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-19-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 drivers/block/xen-blkback/blkback.c  |    1 +
 include/xen/interface/io/protocols.h |    3 +++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
index 73f196c..63dd5b9 100644
--- a/drivers/block/xen-blkback/blkback.c
+++ b/drivers/block/xen-blkback/blkback.c
@@ -42,6 +42,7 @@
 
 #include <xen/events.h>
 #include <xen/page.h>
+#include <xen/xen.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include "common.h"
diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
index 01fc8ae..0eafaf2 100644
--- a/include/xen/interface/io/protocols.h
+++ b/include/xen/interface/io/protocols.h
@@ -5,6 +5,7 @@
 #define XEN_IO_PROTO_ABI_X86_64     "x86_64-abi"
 #define XEN_IO_PROTO_ABI_IA64       "ia64-abi"
 #define XEN_IO_PROTO_ABI_POWERPC64  "powerpc64-abi"
+#define XEN_IO_PROTO_ABI_ARM        "arm-abi"
 
 #if defined(__i386__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
@@ -14,6 +15,8 @@
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
 #elif defined(__powerpc64__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
+#elif defined(__arm__)
+# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
 #else
 # error arch fixup needed here
 #endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:25 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:25 +0100
Subject: [PATCH v2 22/23] arm/v2m: initialize arch_timers even if v2m_timer is
 not present
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-22-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-vexpress/v2m.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26ad..dee1451 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -637,16 +637,17 @@ static void __init v2m_dt_timer_init(void)
 	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
 	v2m_sysctl_init(of_iomap(node, 0));
 
-	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
-	if (WARN_ON(err))
-		return;
-	node = of_find_node_by_path(path);
-	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
 	if (arch_timer_of_register() != 0)
 		twd_local_timer_of_register();
 
 	if (arch_timer_sched_clock_init() != 0)
 		versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
 }
 
 static struct sys_timer v2m_dt_timer = {
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:19 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:19 +0100
Subject: [PATCH v2 16/23] xen: clear IRQ_NOAUTOEN and IRQ_NOREQUEST
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-16-git-send-email-stefano.stabellini@eu.citrix.com>

Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
irq_startup, that is responsible for calling irq_unmask at startup time.
As a result event channels remain masked.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 drivers/xen/events.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 5ecb596..8ffb7b7 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -836,6 +836,7 @@ int bind_evtchn_to_irq(unsigned int evtchn)
 		struct irq_info *info = info_for_irq(irq);
 		WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
 	}
+	irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
 
 out:
 	mutex_unlock(&irq_mapping_update_lock);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:15 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:15 +0100
Subject: [PATCH v2 12/23] xen/arm: introduce CONFIG_XEN on ARM
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-12-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- mark Xen guest support on ARM as EXPERIMENTAL.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/Kconfig |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c..f14664b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1855,6 +1855,16 @@ config DEPRECATED_PARAM_STRUCT
 	  This was deprecated in 2001 and announced to live on for 5 years.
 	  Some old boot loaders still use this way.
 
+config XEN_DOM0
+	def_bool y
+
+config XEN
+	bool "Xen guest support on ARM (EXPERIMENTAL)"
+	depends on EXPERIMENTAL && ARM && OF
+	select XEN_DOM0
+	help
+	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
+
 endmenu
 
 menu "Boot options"
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:17 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:17 +0100
Subject: [PATCH v2 14/23] xen/arm: initialize grant_table on ARM
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-14-git-send-email-stefano.stabellini@eu.citrix.com>

Initialize the grant table mapping at the address specified at index 0
in the DT under the /xen node.
After the grant table is initialized, call xenbus_probe (if not dom0).

Changes in v2:

- introduce GRANT_TABLE_PHYSADDR;
- remove unneeded initialization of boot_max_nr_grant_frames.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index ac3a2d6..e5e92d5 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,8 +1,12 @@
 #include <xen/xen.h>
+#include <xen/grant_table.h>
+#include <xen/hvm.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/memory.h>
+#include <xen/interface/hvm/params.h>
 #include <xen/features.h>
 #include <xen/platform_pci.h>
+#include <xen/xenbus.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include <linux/module.h>
@@ -45,17 +49,23 @@ EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
  * - one interrupt for Xen event notifications;
  * - one memory region to map the grant_table.
  */
+
+#define GRANT_TABLE_PHYSADDR 0
 static int __init xen_guest_init(void)
 {
 	struct xen_add_to_physmap xatp;
 	static struct shared_info *shared_info_page = 0;
 	struct device_node *node;
+	struct resource res;
 
 	node = of_find_compatible_node(NULL, NULL, "arm,xen");
 	if (!node) {
 		pr_debug("No Xen support\n");
 		return 0;
 	}
+	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
+		return 0;
+	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
 	xen_domain_type = XEN_HVM_DOMAIN;
 
 	xen_setup_features();
@@ -89,6 +99,11 @@ static int __init xen_guest_init(void)
 	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
 	 * for secondary CPUs as they are brought up. */
 	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+
+	gnttab_init();
+	if (!xen_initial_domain())
+		xenbus_probe(NULL);
+
 	return 0;
 }
 core_initcall(xen_guest_init);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:18 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:18 +0100
Subject: [PATCH v2 15/23] xen/arm: receive Xen events on ARM
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-15-git-send-email-stefano.stabellini@eu.citrix.com>

Compile events.c on ARM.
Parse, map and enable the IRQ to get event notifications from the device
tree (node "/xen").

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/events.h |   18 ++++++++++++++++++
 arch/arm/xen/enlighten.c          |   33 +++++++++++++++++++++++++++++++++
 arch/x86/xen/enlighten.c          |    1 +
 arch/x86/xen/irq.c                |    1 +
 arch/x86/xen/xen-ops.h            |    1 -
 drivers/xen/events.c              |   17 ++++++++++++++---
 include/xen/events.h              |    2 ++
 7 files changed, 69 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/events.h

diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
new file mode 100644
index 0000000..94b4e90
--- /dev/null
+++ b/arch/arm/include/asm/xen/events.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_XEN_EVENTS_H
+#define _ASM_ARM_XEN_EVENTS_H
+
+#include <asm/ptrace.h>
+
+enum ipi_vector {
+	XEN_PLACEHOLDER_VECTOR,
+
+	/* Xen IPIs go here */
+	XEN_NR_IPIS,
+};
+
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+	return raw_irqs_disabled_flags(regs->ARM_cpsr);
+}
+
+#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index e5e92d5..87b17f0 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,4 +1,5 @@
 #include <xen/xen.h>
+#include <xen/events.h>
 #include <xen/grant_table.h>
 #include <xen/hvm.h>
 #include <xen/interface/xen.h>
@@ -9,6 +10,8 @@
 #include <xen/xenbus.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
@@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
 int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
 EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 
+static __read_mostly int xen_events_irq = -1;
+
 int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 			       unsigned long addr,
 			       unsigned long mfn, int nr,
@@ -66,6 +71,9 @@ static int __init xen_guest_init(void)
 	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
 		return 0;
 	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
+	xen_events_irq = irq_of_parse_and_map(node, 0);
+	pr_info("Xen support found, events_irq=%d gnttab_frame_pfn=%lx\n",
+			xen_events_irq, xen_hvm_resume_frames);
 	xen_domain_type = XEN_HVM_DOMAIN;
 
 	xen_setup_features();
@@ -107,3 +115,28 @@ static int __init xen_guest_init(void)
 	return 0;
 }
 core_initcall(xen_guest_init);
+
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+	xen_hvm_evtchn_do_upcall();
+	return IRQ_HANDLED;
+}
+
+static int __init xen_init_events(void)
+{
+	if (!xen_domain() || xen_events_irq < 0)
+		return -ENODEV;
+
+	xen_init_IRQ();
+
+	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+			"events", xen_vcpu)) {
+		pr_err("Error requesting IRQ %d\n", xen_events_irq);
+		return -EINVAL;
+	}
+
+	enable_percpu_irq(xen_events_irq, 0);
+
+	return 0;
+}
+postcore_initcall(xen_init_events);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index ff962d4..9f8b0ef 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -33,6 +33,7 @@
 #include <linux/memblock.h>
 
 #include <xen/xen.h>
+#include <xen/events.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 1573376..01a4dc0 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -5,6 +5,7 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/sched.h>
 #include <xen/interface/vcpu.h>
+#include <xen/events.h>
 
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 202d4c1..2368295 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -35,7 +35,6 @@ void xen_set_pat(u64);
 
 char * __init xen_memory_setup(void);
 void __init xen_arch_setup(void);
-void __init xen_init_IRQ(void);
 void xen_enable_sysenter(void);
 void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 7595581..5ecb596 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -31,14 +31,16 @@
 #include <linux/irqnr.h>
 #include <linux/pci.h>
 
+#ifdef CONFIG_X86
 #include <asm/desc.h>
 #include <asm/ptrace.h>
 #include <asm/irq.h>
 #include <asm/idle.h>
 #include <asm/io_apic.h>
-#include <asm/sync_bitops.h>
 #include <asm/xen/page.h>
 #include <asm/xen/pci.h>
+#endif
+#include <asm/sync_bitops.h>
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
 
@@ -50,6 +52,9 @@
 #include <xen/interface/event_channel.h>
 #include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/hvm/params.h>
+#include <xen/interface/physdev.h>
+#include <xen/interface/sched.h>
+#include <asm/hw_irq.h>
 
 /*
  * This lock protects updates to the following mapping and reference-count
@@ -1374,7 +1379,9 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
 {
 	struct pt_regs *old_regs = set_irq_regs(regs);
 
+#ifdef CONFIG_X86
 	exit_idle();
+#endif
 	irq_enter();
 
 	__xen_evtchn_do_upcall();
@@ -1783,9 +1790,9 @@ void xen_callback_vector(void)
 void xen_callback_vector(void) {}
 #endif
 
-void __init xen_init_IRQ(void)
+void xen_init_IRQ(void)
 {
-	int i, rc;
+	int i;
 
 	evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
 				    GFP_KERNEL);
@@ -1801,6 +1808,7 @@ void __init xen_init_IRQ(void)
 
 	pirq_needs_eoi = pirq_needs_eoi_flag;
 
+#ifdef CONFIG_X86
 	if (xen_hvm_domain()) {
 		xen_callback_vector();
 		native_init_IRQ();
@@ -1808,6 +1816,7 @@ void __init xen_init_IRQ(void)
 		 * __acpi_register_gsi can point at the right function */
 		pci_xen_hvm_init();
 	} else {
+		int rc;
 		struct physdev_pirq_eoi_gmfn eoi_gmfn;
 
 		irq_ctx_init(smp_processor_id());
@@ -1823,4 +1832,6 @@ void __init xen_init_IRQ(void)
 		} else
 			pirq_needs_eoi = pirq_check_eoi_map;
 	}
+#endif
 }
+EXPORT_SYMBOL_GPL(xen_init_IRQ);
diff --git a/include/xen/events.h b/include/xen/events.h
index 04399b2..c6bfe01 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -109,4 +109,6 @@ int xen_irq_from_gsi(unsigned gsi);
 /* Determine whether to ignore this IRQ if it is passed to a guest. */
 int xen_test_irq_shared(int irq);
 
+/* initialize Xen IRQ subsystem */
+void xen_init_IRQ(void);
 #endif	/* _XEN_EVENTS_H */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:16 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:16 +0100
Subject: [PATCH v2 13/23] xen/arm: get privilege status
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-13-git-send-email-stefano.stabellini@eu.citrix.com>

Use Xen features to figure out if we are privileged.

XENFEAT_dom0 was introduced by 23735 in xen-unstable.hg.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c         |    7 +++++++
 include/xen/interface/features.h |    3 +++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 102d823..ac3a2d6 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,6 +1,7 @@
 #include <xen/xen.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/memory.h>
+#include <xen/features.h>
 #include <xen/platform_pci.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
@@ -57,6 +58,12 @@ static int __init xen_guest_init(void)
 	}
 	xen_domain_type = XEN_HVM_DOMAIN;
 
+	xen_setup_features();
+	if (xen_feature(XENFEAT_dom0))
+		xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
+	else
+		xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
+
 	if (!shared_info_page)
 		shared_info_page = (struct shared_info *)
 			get_zeroed_page(GFP_KERNEL);
diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h
index b6ca39a..131a6cc 100644
--- a/include/xen/interface/features.h
+++ b/include/xen/interface/features.h
@@ -50,6 +50,9 @@
 /* x86: pirq can be used by HVM guests */
 #define XENFEAT_hvm_pirqs           10
 
+/* operation as Dom0 is supported */
+#define XENFEAT_dom0                      11
+
 #define XENFEAT_NR_SUBMAPS 1
 
 #endif /* __XEN_PUBLIC_FEATURES_H__ */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:23 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:23 +0100
Subject: [PATCH v2 20/23] xen/arm: compile netback
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-20-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/hypercall.h |   19 +++++++++++++++++++
 drivers/net/xen-netback/netback.c    |    1 +
 drivers/net/xen-netfront.c           |    1 +
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
index 4ac0624..8a82325 100644
--- a/arch/arm/include/asm/xen/hypercall.h
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -47,4 +47,23 @@ unsigned long HYPERVISOR_hvm_op(int op, void *arg);
 int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
 int HYPERVISOR_physdev_op(int cmd, void *arg);
 
+static inline void
+MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
+			unsigned int new_val, unsigned long flags)
+{
+	BUG();
+}
+
+static inline void
+MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
+		 int count, int *success_count, domid_t domid)
+{
+	BUG();
+}
+
+static inline int
+HYPERVISOR_multicall(void *call_list, int nr_calls)
+{
+	BUG();
+}
 #endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index f4a6fca..ab4f81c 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -40,6 +40,7 @@
 
 #include <net/tcp.h>
 
+#include <xen/xen.h>
 #include <xen/events.h>
 #include <xen/interface/memory.h>
 
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 3089990..bf4ba2b 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -43,6 +43,7 @@
 #include <linux/slab.h>
 #include <net/ip.h>
 
+#include <asm/xen/page.h>
 #include <xen/xen.h>
 #include <xen/xenbus.h>
 #include <xen/events.h>
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:21 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:21 +0100
Subject: [PATCH v2 18/23] xen: allow privcmd for HVM guests
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-18-git-send-email-stefano.stabellini@eu.citrix.com>

This patch removes the "return -ENOSYS" for auto_translated_physmap
guests from privcmd_mmap, thus it allows ARM guests to issue privcmd
mmap calls. However privcmd mmap calls are still going to fail for HVM
and hybrid guests on x86 because the xen_remap_domain_mfn_range
implementation is currently PV only.

Changes in v2:

- better commit message;
- return -EINVAL from xen_remap_domain_mfn_range if
  auto_translated_physmap.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/x86/xen/mmu.c    |    3 +++
 drivers/xen/privcmd.c |    4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 3a73785..885a223 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -2310,6 +2310,9 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 	unsigned long range;
 	int err = 0;
 
+	if (xen_feature(XENFEAT_auto_translated_physmap))
+		return -EINVAL;
+
 	prot = __pgprot(pgprot_val(prot) | _PAGE_IOMAP);
 
 	BUG_ON(!((vma->vm_flags & (VM_PFNMAP | VM_RESERVED | VM_IO)) ==
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index ccee0f1..85226cb 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -380,10 +380,6 @@ static struct vm_operations_struct privcmd_vm_ops = {
 
 static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	/* Unsupported for auto-translate guests. */
-	if (xen_feature(XENFEAT_auto_translated_physmap))
-		return -ENOSYS;
-
 	/* DONTCOPY is essential for Xen because copy_page_range doesn't know
 	 * how to recreate these mappings */
 	vma->vm_flags |= VM_RESERVED | VM_IO | VM_DONTCOPY | VM_PFNMAP;
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:24 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:24 +0100
Subject: [PATCH v2 21/23] xen: update xen_add_to_physmap interface
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-21-git-send-email-stefano.stabellini@eu.citrix.com>

Update struct xen_add_to_physmap to be in sync with Xen's version of the
structure.
The size field was introduced by:

changeset:   24164:707d27fe03e7
user:        Jean Guyader <jean.guyader at eu.citrix.com>
date:        Fri Nov 18 13:42:08 2011 +0000
summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range

According to the comment:

"This new field .size is located in the 16 bits padding between .domid
and .space in struct xen_add_to_physmap to stay compatible with older
versions."

Changes in v2:

- remove erroneous comment in the commit message.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 include/xen/interface/memory.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index b5c3098..b66d04c 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -163,6 +163,9 @@ struct xen_add_to_physmap {
     /* Which domain to change the mapping for. */
     domid_t domid;
 
+    /* Number of pages to go through for gmfn_range */
+    uint16_t    size;
+
     /* Source mapping space. */
 #define XENMAPSPACE_shared_info 0 /* shared info page */
 #define XENMAPSPACE_grant_table 1 /* grant table page */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:26 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:26 +0100
Subject: [PATCH v2 23/23] [HACK] xen/arm: implement xen_remap_domain_mfn_range
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-23-git-send-email-stefano.stabellini@eu.citrix.com>

From: Ian Campbell <Ian.Campbell at citrix.com>

Do not apply!

This is a simple, hacky implementation of xen_remap_domain_mfn_range,
using XENMAPSPACE_gmfn_foreign.

It should use same interface as hybrid x86.

Changes in v2:

- retain binary compatibility in xen_add_to_physmap: use a union.

Signed-off-by: Ian Campbell <Ian.Campbell at citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c       |   79 +++++++++++++++++++++++++++++++++++++++-
 drivers/xen/privcmd.c          |   16 +++++----
 drivers/xen/xenfs/super.c      |    7 ++++
 include/xen/interface/memory.h |   15 ++++++--
 4 files changed, 105 insertions(+), 12 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index c244583..20ca1e4 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -16,6 +16,10 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+
+#include <asm/pgtable.h>
 
 struct start_info _xen_start_info;
 struct start_info *xen_start_info = &_xen_start_info;
@@ -38,12 +42,85 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 
 static __read_mostly int xen_events_irq = -1;
 
+#define FOREIGN_MAP_BUFFER 0x90000000UL
+#define FOREIGN_MAP_BUFFER_SIZE 0x10000000UL
+struct resource foreign_map_resource = {
+	.start = FOREIGN_MAP_BUFFER,
+	.end = FOREIGN_MAP_BUFFER + FOREIGN_MAP_BUFFER_SIZE,
+	.name = "Xen foreign map buffer",
+	.flags = 0,
+};
+
+static unsigned long foreign_map_buffer_pfn = FOREIGN_MAP_BUFFER >> PAGE_SHIFT;
+
+struct remap_data {
+	struct mm_struct *mm;
+	unsigned long mfn;
+	pgprot_t prot;
+};
+
+static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
+				 unsigned long addr, void *data)
+{
+	struct remap_data *rmd = data;
+	pte_t pte = pfn_pte(rmd->mfn, rmd->prot);
+
+	if (rmd->mfn < 0x90010)
+		pr_crit("%s: ptep %p addr %#lx => %#x / %#lx\n",
+		       __func__, ptep, addr, pte_val(pte), rmd->mfn);
+
+	set_pte_at(rmd->mm, addr, ptep, pte);
+
+	rmd->mfn++;
+	return 0;
+}
+
 int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 			       unsigned long addr,
 			       unsigned long mfn, int nr,
 			       pgprot_t prot, unsigned domid)
 {
-	return -ENOSYS;
+	int i, rc = 0;
+	struct remap_data rmd = {
+		.mm = vma->vm_mm,
+		.prot = prot,
+	};
+	struct xen_add_to_physmap xatp = {
+		.domid = DOMID_SELF,
+		.space = XENMAPSPACE_gmfn_foreign,
+
+		.foreign_domid = domid,
+	};
+
+	if (foreign_map_buffer_pfn + nr > ((FOREIGN_MAP_BUFFER +
+					FOREIGN_MAP_BUFFER_SIZE)>>PAGE_SHIFT)) {
+		pr_crit("RAM out of foreign map buffers...\n");
+		return -EBUSY;
+	}
+
+	for (i = 0; i < nr; i++) {
+		xatp.idx = mfn + i;
+		xatp.gpfn = foreign_map_buffer_pfn + i;
+		rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
+		if (rc != 0) {
+			pr_crit("foreign map add_to_physmap failed, err=%d\n", rc);
+			goto out;
+		}
+	}
+
+	rmd.mfn = foreign_map_buffer_pfn;
+	rc = apply_to_page_range(vma->vm_mm,
+				 addr,
+				 (unsigned long)nr << PAGE_SHIFT,
+				 remap_area_mfn_pte_fn, &rmd);
+	if (rc != 0) {
+		pr_crit("apply_to_page_range failed rc=%d\n", rc);
+		goto out;
+	}
+
+	foreign_map_buffer_pfn += nr;
+out:
+	return rc;
 }
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
 
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 85226cb..3e15c22 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -20,6 +20,8 @@
 #include <linux/pagemap.h>
 #include <linux/seq_file.h>
 #include <linux/miscdevice.h>
+#include <linux/resource.h>
+#include <linux/ioport.h>
 
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
@@ -196,9 +198,6 @@ static long privcmd_ioctl_mmap(void __user *udata)
 	LIST_HEAD(pagelist);
 	struct mmap_mfn_state state;
 
-	if (!xen_initial_domain())
-		return -EPERM;
-
 	if (copy_from_user(&mmapcmd, udata, sizeof(mmapcmd)))
 		return -EFAULT;
 
@@ -286,9 +285,6 @@ static long privcmd_ioctl_mmap_batch(void __user *udata)
 	LIST_HEAD(pagelist);
 	struct mmap_batch_state state;
 
-	if (!xen_initial_domain())
-		return -EPERM;
-
 	if (copy_from_user(&m, udata, sizeof(m)))
 		return -EFAULT;
 
@@ -365,6 +361,11 @@ static long privcmd_ioctl(struct file *file,
 	return ret;
 }
 
+static void privcmd_close(struct vm_area_struct *vma)
+{
+	/* TODO: unmap VMA */
+}
+
 static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 {
 	printk(KERN_DEBUG "privcmd_fault: vma=%p %lx-%lx, pgoff=%lx, uv=%p\n",
@@ -375,7 +376,8 @@ static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 }
 
 static struct vm_operations_struct privcmd_vm_ops = {
-	.fault = privcmd_fault
+	.fault = privcmd_fault,
+	.close = privcmd_close,
 };
 
 static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
diff --git a/drivers/xen/xenfs/super.c b/drivers/xen/xenfs/super.c
index a84b53c..edbe22f 100644
--- a/drivers/xen/xenfs/super.c
+++ b/drivers/xen/xenfs/super.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/magic.h>
+#include <linux/ioport.h>
 
 #include <xen/xen.h>
 
@@ -80,6 +81,8 @@ static const struct file_operations capabilities_file_ops = {
 	.llseek = default_llseek,
 };
 
+extern struct resource foreign_map_resource;
+
 static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
 {
 	static struct tree_descr xenfs_files[] = {
@@ -100,6 +103,10 @@ static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
 				  &xsd_kva_file_ops, NULL, S_IRUSR|S_IWUSR);
 		xenfs_create_file(sb, sb->s_root, "xsd_port",
 				  &xsd_port_file_ops, NULL, S_IRUSR|S_IWUSR);
+		rc = request_resource(&iomem_resource, &foreign_map_resource);
+		if (rc < 0)
+			pr_crit("failed to register foreign map resource\n");
+		rc = 0; /* ignore */
 	}
 
 	return rc;
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index b66d04c..dd2ffe0 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -163,12 +163,19 @@ struct xen_add_to_physmap {
     /* Which domain to change the mapping for. */
     domid_t domid;
 
-    /* Number of pages to go through for gmfn_range */
-    uint16_t    size;
+    union {
+        /* Number of pages to go through for gmfn_range */
+        uint16_t    size;
+        /* IFF gmfn_foreign */
+        domid_t foreign_domid;
+    };
 
     /* Source mapping space. */
-#define XENMAPSPACE_shared_info 0 /* shared info page */
-#define XENMAPSPACE_grant_table 1 /* grant table page */
+#define XENMAPSPACE_shared_info  0 /* shared info page */
+#define XENMAPSPACE_grant_table  1 /* grant table page */
+#define XENMAPSPACE_gmfn         2 /* GMFN */
+#define XENMAPSPACE_gmfn_range   3 /* GMFN range */
+#define XENMAPSPACE_gmfn_foreign 4 /* GMFN from another guest */
     unsigned int space;
 
     /* Index into source mapping space. */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Mon Aug  6 10:27:14 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Mon, 6 Aug 2012 15:27:14 +0100
Subject: [PATCH v2 11/23] xen: do not compile manage, balloon, pci,
 acpi and cpu_hotplug on ARM
In-Reply-To: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
Message-ID: <1344263246-28036-11-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- make pci.o depend on CONFIG_PCI and acpi.o depend on CONFIG_ACPI.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 drivers/xen/Makefile |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index fc34886..bee02b2 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -1,11 +1,17 @@
-obj-y	+= grant-table.o features.o events.o manage.o balloon.o
+ifneq ($(CONFIG_ARM),y)
+obj-y	+= manage.o balloon.o
+obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
+endif
+obj-y	+= grant-table.o features.o events.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_features.o			:= $(nostackp)
 
+obj-$(CONFIG_XEN_DOM0)			+= $(dom0-y)
+dom0-$(CONFIG_PCI) := pci.o
+dom0-$(CONFIG_ACPI) := acpi.o
 obj-$(CONFIG_BLOCK)			+= biomerge.o
-obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 obj-$(CONFIG_XEN_XENCOMM)		+= xencomm.o
 obj-$(CONFIG_XEN_BALLOON)		+= xen-balloon.o
 obj-$(CONFIG_XEN_SELFBALLOONING)	+= xen-selfballoon.o
@@ -17,7 +23,6 @@ obj-$(CONFIG_XEN_SYS_HYPERVISOR)	+= sys-hypervisor.o
 obj-$(CONFIG_XEN_PVHVM)			+= platform-pci.o
 obj-$(CONFIG_XEN_TMEM)			+= tmem.o
 obj-$(CONFIG_SWIOTLB_XEN)		+= swiotlb-xen.o
-obj-$(CONFIG_XEN_DOM0)			+= pci.o acpi.o
 obj-$(CONFIG_XEN_PCIDEV_BACKEND)	+= xen-pciback/
 obj-$(CONFIG_XEN_PRIVCMD)		+= xen-privcmd.o
 obj-$(CONFIG_XEN_ACPI_PROCESSOR)	+= xen-acpi-processor.o
-- 
1.7.2.5



From broonie at opensource.wolfsonmicro.com  Mon Aug  6 10:57:03 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 15:57:03 +0100
Subject: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412
In-Reply-To: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <20120806145702.GB29272@sirena.org.uk>

On Mon, Aug 06, 2012 at 11:10:51PM +0900, Dongjin Kim wrote:

> +static struct regulator_consumer_supply __initdata max77686_buck4_consumer[] = {
> +	REGULATOR_SUPPLY("vdd_g3d", NULL),
> +};

Not that it matters much since new board drivers won't get merged but
all your regulator setup here is problematic.  These look like names
from the board schematic as opposed to mappings of the supplies onto the
consumer devices.

> +static struct regulator_init_data __initdata max77686_buck1_data = {
> +	.constraints = {
> +		.name		= "vdd_mif range",

This would normally just be the name of the supply for display purposes.


From rostedt at goodmis.org  Mon Aug  6 09:39:17 2012
From: rostedt at goodmis.org (Steven Rostedt)
Date: Mon, 6 Aug 2012 09:39:17 -0400
Subject: [PATCH v3] printk: add option to print cpu id
In-Reply-To: <CAFm5wm1SSmbdi09hc1Qo1eHw5Tc0vbMf1hWuNw-cjZEEx3jX5w@mail.gmail.com>
References: <m2628z6euk.fsf@firstfloor.org>
 <CAFm5wm3ScpUU5wa=ei3TY0zjU4kVbOgJMmE5_QDpwy7B-TJa+A@mail.gmail.com>
 <20120803200822.GC731@harshnoise.musicnaut.iki.fi>
 <CAFm5wm2sf9LnZNj9_BDYTF9G7XH32fOL3x5n=kZ-1ih0Cek2DQ@mail.gmail.com>
 <20120803215954.GA4489@kroah.com>
 <CAFm5wm1_-JP0xjDdBvAcqqpZPQvxJPsmNtUOFQyaNw=6H_JJcg@mail.gmail.com>
 <20120803221327.GA5102@kroah.com>
 <CAFm5wm3ayofPD7oF1=z_jwE_wuqBxBHicAs=KOhjcUr7Jo0wDQ@mail.gmail.com>
 <20120803223623.GB6156@kroah.com>
 <CAFm5wm1SSmbdi09hc1Qo1eHw5Tc0vbMf1hWuNw-cjZEEx3jX5w@mail.gmail.com>
Message-ID: <20120806133917.GF16873@home.goodmis.org>

On Fri, Aug 03, 2012 at 03:48:26PM -0700, Pandita, Vikram wrote:
> On Fri, Aug 3, 2012 at 3:36 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> > On Fri, Aug 03, 2012 at 03:25:17PM -0700, Pandita, Vikram wrote:
> >> >> This was something that got used internally and helped at times.
> >> >
> >> > Could you have used the trace point instead?
> >>
> >> As i understood the trace_prink(), one would need to modify existing
> >> printk -> trace_printk. Is my understanding correct?
> >
> > No, you should just be able to watch the tracepoint, right?
> 
> yes.
> Assumption being you know _EXACTLY_ what code piece to watch for.
> Which may not be the case all times.

But it traces all printks.

 # echo 1 > /sys/kernel/debug/tracing/events/printk/console/enable
 # mount /home/rostedt
 # cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 2/2   #P:4
#
#                              _-----=> irqs-off
#                             / _----=> need-resched
#                            | / _---=> hardirq/softirq
#                            || / _--=> preempt-depth
#                            ||| /     delay
#           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
#              | |       |   ||||       |         |
        modprobe-2707  [002] d..1    97.079458: console: [   95.816945] NFS: Registering the id_resolver key type

        modprobe-2707  [002] d..1    97.084534: console: [   95.822038] Key type id_resolver registered

If you wanted this from boot up, you can just add to the kernel command line:

  trace_event=console

-- Steve



From mugunthanvnm at ti.com  Mon Aug  6 11:05:56 2012
From: mugunthanvnm at ti.com (Mugunthan V N)
Date: Mon, 6 Aug 2012 20:35:56 +0530
Subject: [PATCH 0/2] Add device tree support for davinci_mdio driver and fix
 cpsw DT binding documentation
Message-ID: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>

This patch set adds support for device tree for Davinci MDIO driver and fixes
CPSW DT binding documentation to make it copy pastable to dts file.

This patch set is tested with the following git tree on AM335X Beagle Bone
https://github.com/hvaibhav/am335x-linux/tree/am335x-upstream-staging-cpsw

Mugunthan V N (2):
  drivers: net: ethernet: davince_mdio: device tree implementation
  documentation: dt: bindings: cpsw: fixing the examples for directly
    using it in dts file

 Documentation/devicetree/bindings/net/cpsw.txt     |  101 ++++++++++---------
 .../devicetree/bindings/net/davinci-mdio.txt       |   33 +++++++
 drivers/net/ethernet/ti/davinci_mdio.c             |   41 +++++++-
 3 files changed, 123 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/davinci-mdio.txt



From mugunthanvnm at ti.com  Mon Aug  6 11:05:58 2012
From: mugunthanvnm at ti.com (Mugunthan V N)
Date: Mon, 6 Aug 2012 20:35:58 +0530
Subject: [PATCH 2/2] documentation: dt: bindings: cpsw: fixing the examples
 for directly using it in dts file
In-Reply-To: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
References: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
Message-ID: <1344265558-5724-3-git-send-email-mugunthanvnm@ti.com>

Fixing the cpsw device tree example to make it simpler to copy pastable to dts
file and use it directly.

Signed-off-by: Mugunthan V N <mugunthanvnm at ti.com>
---
 Documentation/devicetree/bindings/net/cpsw.txt |  101 ++++++++++++-----------
 1 files changed, 53 insertions(+), 48 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index acca48c..dcaabe9 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -11,6 +11,7 @@ Required properties:
 - cpdma_channels 	: Specifies number of channels in CPDMA
 - host_port_no		: Specifies host port shift
 - cpdma_reg_ofs		: Specifies CPDMA submodule register offset
+- cpdma_sram_ofs	: Specifies CPDMA SRAM offset
 - ale_reg_ofs		: Specifies ALE submodule register offset
 - ale_entries		: Specifies No of entries ALE can hold
 - host_port_reg_ofs	: Specifies host port register offset
@@ -43,62 +44,66 @@ Examples:
 		reg = <0x4A100000 0x1000>;
 		interrupts = <55 0x4>;
 		interrupt-parent = <&intc>;
-		cpdma_channels = 8;
-		host_port_no = 0;
-		cpdma_reg_ofs = 0x800;
-		ale_reg_ofs = 0xd00;
-		ale_entries = 1024;
-		host_port_reg_ofs = 0x108;
-		hw_stats_reg_ofs = 0x900;
-		bd_ram_ofs = 0x2000;
-		bd_ram_size = 0x2000;
-		no_bd_ram = 0;
-		rx_descs = 64;
-		mac_control = 0x20;
-		slaves = 2;
-		slave at 0 {
-			slave_reg_ofs = 0x208;
-			sliver_reg_ofs = 0xd80;
-			phy_id = "davinci_mdio-0:00"
-			mac-address = [00 04 9F 01 1B B8];
+		cpdma_channels = <8>;
+		host_port_no = <0>;
+		cpdma_reg_ofs = <0x800>;
+		cpdma_sram_ofs = <0xa00>;
+		ale_reg_ofs = <0xd00>;
+		ale_entries = <1024>;
+		host_port_reg_ofs = <0x108>;
+		hw_stats_reg_ofs = <0x900>;
+		bd_ram_ofs = <0x2000>;
+		bd_ram_size = <0x2000>;
+		no_bd_ram = <0>;
+		rx_descs = <64>;
+		mac_control = <0x20>;
+		slaves = <2>;
+		cpsw_emac0: slave at 0 {
+			slave_reg_ofs = <0x208>;
+			sliver_reg_ofs = <0xd80>;
+			phy_id = "davinci_mdio.16:00";
+			/* Filled in by U-Boot */
+			mac-address = [ 00 00 00 00 00 00 ];
 		};
-		slave at 1 {
-			slave_reg_ofs = 0x208;
-			sliver_reg_ofs = 0xd80;
-			phy_id = "davinci_mdio-0:01"
-			mac-address = [00 04 9F 01 1B B9];
+		cpsw_emac1: slave at 1 {
+			slave_reg_ofs = <0x308>;
+			sliver_reg_ofs = <0xdc0>;
+			phy_id = "davinci_mdio.16:01";
+			/* Filled in by U-Boot */
+			mac-address = [ 00 00 00 00 00 00 ];
 		};
 	};
 
 (or)
-
 	mac: ethernet at 4A100000 {
 		compatible = "ti,cpsw";
 		ti,hwmods = "cpgmac0";
-		cpdma_channels = 8;
-		host_port_no = 0;
-		cpdma_reg_ofs = 0x800;
-		ale_reg_ofs = 0xd00;
-		ale_entries = 1024;
-		host_port_reg_ofs = 0x108;
-		hw_stats_reg_ofs = 0x900;
-		bd_ram_ofs = 0x2000;
-		bd_ram_size = 0x2000;
-		no_bd_ram = 0;
-		rx_descs = 64;
-		mac_control = 0x20;
-		slaves = 2;
-		slave at 0 {
-			slave_reg_ofs = 0x208;
-			sliver_reg_ofs = 0xd80;
-			phy_id = "davinci_mdio-0:00"
-			mac-address = [00 04 9F 01 1B B8];
+		cpdma_channels = <8>;
+		host_port_no = <0>;
+		cpdma_reg_ofs = <0x800>;
+		cpdma_sram_ofs = <0xa00>;
+		ale_reg_ofs = <0xd00>;
+		ale_entries = <1024>;
+		host_port_reg_ofs = <0x108>;
+		hw_stats_reg_ofs = <0x900>;
+		bd_ram_ofs = <0x2000>;
+		bd_ram_size = <0x2000>;
+		no_bd_ram = <0>;
+		rx_descs = <64>;
+		mac_control = <0x20>;
+		slaves = <2>;
+		cpsw_emac0: slave at 0 {
+			slave_reg_ofs = <0x208>;
+			sliver_reg_ofs = <0xd80>;
+			phy_id = "davinci_mdio.16:00";
+			/* Filled in by U-Boot */
+			mac-address = [ 00 00 00 00 00 00 ];
 		};
-		slave at 1 {
-			slave_reg_ofs = 0x208;
-			sliver_reg_ofs = 0xd80;
-			phy_id = "davinci_mdio-0:01"
-			mac-address = [00 04 9F 01 1B B9];
+		cpsw_emac1: slave at 1 {
+			slave_reg_ofs = <0x308>;
+			sliver_reg_ofs = <0xdc0>;
+			phy_id = "davinci_mdio.16:01";
+			/* Filled in by U-Boot */
+			mac-address = [ 00 00 00 00 00 00 ];
 		};
-
 	};
-- 
1.7.0.4



From mugunthanvnm at ti.com  Mon Aug  6 11:05:57 2012
From: mugunthanvnm at ti.com (Mugunthan V N)
Date: Mon, 6 Aug 2012 20:35:57 +0530
Subject: [PATCH 1/2] drivers: net: ethernet: davince_mdio: device tree
 implementation
In-Reply-To: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
References: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
Message-ID: <1344265558-5724-2-git-send-email-mugunthanvnm@ti.com>

device tree implementation for davinci mdio driver

Signed-off-by: Mugunthan V N <mugunthanvnm at ti.com>
---
 .../devicetree/bindings/net/davinci-mdio.txt       |   33 ++++++++++++++++
 drivers/net/ethernet/ti/davinci_mdio.c             |   41 ++++++++++++++++++--
 2 files changed, 70 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/davinci-mdio.txt

diff --git a/Documentation/devicetree/bindings/net/davinci-mdio.txt b/Documentation/devicetree/bindings/net/davinci-mdio.txt
new file mode 100644
index 0000000..72efaaf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/davinci-mdio.txt
@@ -0,0 +1,33 @@
+TI SoC Davinci MDIO Controller Device Tree Bindings
+---------------------------------------------------
+
+Required properties:
+- compatible		: Should be "ti,davinci_mdio"
+- reg			: physical base address and size of the davinci mdio
+			  registers map
+- bus_freq		: Mdio Bus frequency
+
+Optional properties:
+- ti,hwmods		: Must be "davinci_mdio"
+
+Note: "ti,hwmods" field is used to fetch the base address and irq
+resources from TI, omap hwmod data base during device registration.
+Future plan is to migrate hwmod data base contents into device tree
+blob so that, all the required data will be used from device tree dts
+file.
+
+Examples:
+
+	mdio: davinci_mdio at 4A101000 {
+		compatible = "ti,cpsw";
+		reg = <0x4A101000 0x1000>;
+		bus_freq = <1000000>;
+	};
+
+(or)
+
+	mdio: davinci_mdio at 4A101000 {
+		compatible = "ti,cpsw";
+		ti,hwmods = "davinci_mdio";
+		bus_freq = <1000000>;
+	};
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index cd7ee20..573f3be 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -36,6 +36,8 @@
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
 #include <linux/davinci_emac.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 /*
  * This timeout definition is a worst-case ultra defensive measure against
@@ -289,6 +291,25 @@ static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
 	return 0;
 }
 
+static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
+			 struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	u32 prop;
+
+	if (!node)
+		return -EINVAL;
+
+	if (of_property_read_u32(node, "bus_freq", &prop)) {
+		pr_err("Missing bus_freq property in the DT.\n");
+		return -EINVAL;
+	}
+	data->bus_freq = prop;
+
+	return 0;
+}
+
+
 static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 {
 	struct mdio_platform_data *pdata = pdev->dev.platform_data;
@@ -304,8 +325,6 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	data->pdata = pdata ? (*pdata) : default_pdata;
-
 	data->bus = mdiobus_alloc();
 	if (!data->bus) {
 		dev_err(dev, "failed to alloc mii bus\n");
@@ -313,14 +332,22 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 		goto bail_out;
 	}
 
+	if (dev->of_node) {
+		if (davinci_mdio_probe_dt(&data->pdata, pdev))
+			data->pdata = default_pdata;
+		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
+	} else {
+		data->pdata = pdata ? (*pdata) : default_pdata;
+		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
+			 pdev->name, pdev->id);
+	}
+
 	data->bus->name		= dev_name(dev);
 	data->bus->read		= davinci_mdio_read,
 	data->bus->write	= davinci_mdio_write,
 	data->bus->reset	= davinci_mdio_reset,
 	data->bus->parent	= dev;
 	data->bus->priv		= data;
-	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
 
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
@@ -454,11 +481,17 @@ static const struct dev_pm_ops davinci_mdio_pm_ops = {
 	.resume		= davinci_mdio_resume,
 };
 
+static const struct of_device_id davinci_mdio_of_mtable[] = {
+	{ .compatible = "ti,davinci_mdio", },
+	{ /* sentinel */ },
+};
+
 static struct platform_driver davinci_mdio_driver = {
 	.driver = {
 		.name	 = "davinci_mdio",
 		.owner	 = THIS_MODULE,
 		.pm	 = &davinci_mdio_pm_ops,
+		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
 	},
 	.probe = davinci_mdio_probe,
 	.remove = __devexit_p(davinci_mdio_remove),
-- 
1.7.0.4



From lee.jones at linaro.org  Mon Aug  6 11:17:33 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon,  6 Aug 2012 16:17:33 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.
Message-ID: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 5e6f1ee..e42e526 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -350,10 +350,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -911,20 +907,32 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* fast mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
-	struct nmk_i2c_controller *pdata =
-			adev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = pdev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
-	if (!pdata) {
-		dev_warn(&adev->dev, "no platform data\n");
-		return -ENODEV;
-	}
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&adev->dev, "cannot allocate memory\n");
-- 
1.7.9.5



From lee.jones at linaro.org  Mon Aug  6 11:18:21 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 16:18:21 +0100
Subject: [PATCH 1/1] i2c: Add default configuration into the Nomadik I2C
 driver.
In-Reply-To: <CACRpkdZoJxyZX6SOcAvBP4NBmGyUEiyLH_n_RzSDTBsjS13zug@mail.gmail.com>
References: <1344255947-10062-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdZoJxyZX6SOcAvBP4NBmGyUEiyLH_n_RzSDTBsjS13zug@mail.gmail.com>
Message-ID: <20120806151820.GG10524@gmail.com>

> This still does not apply for me on v3.6-rc1 what did you base
> this patch on?

Resent based on v3.6-rc1, sorry for the mixup.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From dmitry.torokhov at gmail.com  Mon Aug  6 04:19:15 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Mon, 6 Aug 2012 01:19:15 -0700
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20120806081915.GA4518@core.coreip.homeip.net>

Hi Lee,

On Mon, Aug 06, 2012 at 01:32:03PM +0100, Lee Jones wrote:
> If we're booting with Device Tree enabled, we want the IRQ numbers to
> be taken and translated from the Device Tree binary. If not, they
> should be taken from the resource allocation defined in the AB8500 MFD
> core driver.
> 
> Tested-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/input/misc/ab8500-ponkey.c |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
> index 1a1d974..afcd87f 100644
> --- a/drivers/input/misc/ab8500-ponkey.c
> +++ b/drivers/input/misc/ab8500-ponkey.c
> @@ -47,6 +47,7 @@ static irqreturn_t ab8500_ponkey_handler(int irq, void *data)
>  static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
>  {
>  	struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
> +	struct device_node *np = pdev->dev.of_node;
>  	struct ab8500_ponkey *ponkey;
>  	struct input_dev *input;
>  	int irq_dbf, irq_dbr;
> @@ -73,8 +74,9 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
>  
>  	ponkey->idev = input;
>  	ponkey->ab8500 = ab8500;
> -	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
> -	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
> +
> +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;

Why this isn't done inside ab8500_irq_get_virq()?

Thanks.

-- 
Dmitry


From matt at genesi-usa.com  Mon Aug  6 11:19:50 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 10:19:50 -0500
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
Message-ID: <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>

On Sun, Aug 5, 2012 at 6:03 PM, Anton Vorontsov
<anton.vorontsov at linaro.org> wrote:
> The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
> passed to it, so it's pretty clear that the driver is absolutely sure
> that the FIQ is routed via platform-specific IC, and that the cookie can
> be used to mask/unmask FIQs. So, let's switch to the genirq routines,
> since we're about to remove FIQ-specific variants.

I have a semi-related question about this;

Firstly, I was planning on (re-)submitting a patch for the
arch/arm/plat-mxc/ssi-fiq.S code which made it build in ARM mode
(since the code isn't Thumb compatible for various reasons) as it was
a blocker for a Thumb2-compiled kernel. Since the code was only needed
on ARM-capable processors it wouldn't cause a problem. Sascha signed
off on this a long while back and I've been testing it on all my
internal kernel versions, and I don't see any ill effects (that said I
don't have an i.MX28 or so to really verify it, I can't see why it
would not work). I realise this is redundant right now, anyway, since
it's only really enabled on imx_v4_v5 configs and they don't support
Thumb2 kernels anyway. What might be worth submitting is a switch to
add the ".arm" directive anyway simply for correctness since it could
never be compiled for Thumb anyway. We all know what gnu as is like.

Looking at it again on the back of these patches, I noticed the
ssi-fiq.S code is compiled in when SND_IMX_SOC is enabled - of course,
it's only needed in the kernel if SND_SOC_IMX_PCM_FIQ is enabled (the
code that uses the FIQ stuff is only compiled then) but here on the
Efika MX builds it's being built, and I noticed it when it broke my
build because of the above. I'm therefore going to submit a patch
which changes the ifdef SND_SOC_IMX to ifdef SND_SOC_IMX_PCM_FIQ so
it's not compiled in unless absolutely necessary. However, there was a
rumble that this code may disappear or be reworked in the future
making this also quite redundant. Since it's not in the
imx_v6_v7_defconfig anyway, I'm sure this only didn't get noticed
because nobody's building Thumb2 kernels and nobody is trying configs
with audio enabled anyway..

This begs the question, could there be something somewhere hidden deep
in the kernel that is enabled by default or in some config somewhere
that requires "select FIQ" in it's Kconfig entry, but isn't being
enabled? On i.MX the only thing turning it on is that code, but other
ARM arch enable it by default. Since things have been moved to more
generic routines I can't in my mind guarantee that such a patch would
be well tested here since I would be relying on symbols missing or
defines not there anymore.. I have no real way to ensure that it would
work on boards I don't have.

So, is the first patch (ssi-fiq.S .arm) worth it? I think the
SND_SOC_IMX_PCM_FIQ patch is worth it for v6_v7 systems anyway, but
maybe this should have been caught sooner, so should I update the
defconfig to enable some kind of audio bus support (Babbage has it in
the DT so is a needful thing for testing, I figure..)? And does anyone
forsee any problems with that option changing and the only "user" of
"FIQ" in the Kconfigs going away now all the FIQ-specific symbols went
away outside of the generic irq subsystem?

I will probably throw out all three today anyway, but I thought it
would make a good discussion anyway.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From lee.jones at linaro.org  Mon Aug  6 11:35:06 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 16:35:06 +0100
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik I2C
 driver.
In-Reply-To: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20120806153503.GH10524@gmail.com>

Looks like I introduced a merge error on the last patch. Trying again:

From: Lee Jones <lee.jones at linaro.org>
Date: Mon, 6 Aug 2012 11:04:14 +0100
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik I2C
 driver.

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../mali/mali400ko/driver/src/devicedrv/mali/arch  |    1 +
 drivers/i2c/busses/i2c-nomadik.c                   |   28 +++++++++++++-------
 2 files changed, 19 insertions(+), 10 deletions(-)
 create mode 120000 drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch

diff --git a/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
new file mode 120000
index 0000000..427334b
--- /dev/null
+++ b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
@@ -0,0 +1 @@
+/home/ljkenny/projects/linaro/snowball/snowball/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch-ux500
\ No newline at end of file
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 5e6f1ee..61b00ed 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -350,10 +350,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -911,20 +907,32 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* fast mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
-	struct nmk_i2c_controller *pdata =
-			adev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = adev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
-	if (!pdata) {
-		dev_warn(&adev->dev, "no platform data\n");
-		return -ENODEV;
-	}
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&adev->dev, "cannot allocate memory\n");
-- 
1.7.9.5


From lee.jones at linaro.org  Mon Aug  6 11:37:52 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 16:37:52 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120806081915.GA4518@core.coreip.homeip.net>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
Message-ID: <20120806153750.GI10524@gmail.com>

On Mon, Aug 06, 2012 at 01:19:15AM -0700, Dmitry Torokhov wrote:
> > -	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
> > -	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
> > +
> > +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> > +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
> 
> Why this isn't done inside ab8500_irq_get_virq()?

There's no reason why it can't be.

My first version of the patch did just that in fact.

Would that be your preference?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From broonie at opensource.wolfsonmicro.com  Mon Aug  6 11:42:14 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 16:42:14 +0100
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
In-Reply-To: <20120806093033.GH17551@arwen.pp.htv.fi>
References: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
 <20120806093033.GH17551@arwen.pp.htv.fi>
Message-ID: <20120806154214.GC29272@sirena.org.uk>

On Mon, Aug 06, 2012 at 12:30:34PM +0300, Felipe Balbi wrote:
> On Mon, Aug 06, 2012 at 02:58:44PM +0530, Sourav Poddar wrote:
> > There is an automatic binding done for I2C devices in the of_i2c core
> > code. So, DT will be able to bind to any I2C device using the
> > already existing table: MODULE_DEVICE_TABLE(i2c, bmp085_id).

> Acked-by: Felipe Balbi <balbi at ti.com>

It's good practice to have an explict compatible string even if the
default happens to work in order to avoid any name clashes.


From shawn.guo at linaro.org  Mon Aug  6 11:42:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:43 +0800
Subject: [PATCH 0/6] ARM: mxs: remove board files
Message-ID: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>

The first two patches hack out the board oddness in DT boot for TX28
and MX28EVK, so that they do not block the whole progress of coverting
mxs platform over to DT.

The rest of the series removes board files and the codes only used in
non-DT boot, and make mxs a DT-only platform.

Shawn Guo (6):
  ARM: mxs: tx28: reset fec phy for device tree boot
  ARM: mxs: use auxdata to pass flexcan_switch function hook
  ARM: mxs: remove board files
  ARM: mxs: remove non-DT core functions
  ARM: mxs: remove platform device codes
  ARM: mxs: remove iomux driver

 arch/arm/boot/dts/imx28-tx28.dts                  |   21 +-
 arch/arm/configs/mxs_defconfig                    |    6 -
 arch/arm/mach-mxs/Kconfig                         |   89 ----
 arch/arm/mach-mxs/Makefile                        |   11 +-
 arch/arm/mach-mxs/devices-mx23.h                  |   43 --
 arch/arm/mach-mxs/devices-mx28.h                  |   63 ---
 arch/arm/mach-mxs/devices.c                       |   87 ----
 arch/arm/mach-mxs/devices/Kconfig                 |   33 --
 arch/arm/mach-mxs/devices/Makefile                |   12 -
 arch/arm/mach-mxs/devices/platform-auart.c        |   65 ---
 arch/arm/mach-mxs/devices/platform-dma.c          |   31 --
 arch/arm/mach-mxs/devices/platform-fec.c          |   52 --
 arch/arm/mach-mxs/devices/platform-flexcan.c      |   51 --
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c     |   33 --
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c    |   81 ---
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c      |   52 --
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c      |   76 ---
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c      |   22 -
 arch/arm/mach-mxs/devices/platform-mxs-saif.c     |   61 ---
 arch/arm/mach-mxs/devices/platform-mxsfb.c        |   47 --
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c |   51 --
 arch/arm/mach-mxs/include/mach/common.h           |    9 -
 arch/arm/mach-mxs/include/mach/devices-common.h   |  114 -----
 arch/arm/mach-mxs/include/mach/iomux-mx23.h       |  355 --------------
 arch/arm/mach-mxs/include/mach/iomux-mx28.h       |  537 ---------------------
 arch/arm/mach-mxs/include/mach/iomux.h            |  168 -------
 arch/arm/mach-mxs/iomux.c                         |  101 ----
 arch/arm/mach-mxs/mach-apx4devkit.c               |  273 -----------
 arch/arm/mach-mxs/mach-m28evk.c                   |  366 --------------
 arch/arm/mach-mxs/mach-mx23evk.c                  |  190 --------
 arch/arm/mach-mxs/mach-mx28evk.c                  |  477 ------------------
 arch/arm/mach-mxs/mach-mxs.c                      |  126 +++++-
 arch/arm/mach-mxs/mach-stmp378x_devb.c            |  123 -----
 arch/arm/mach-mxs/mach-tx28.c                     |  184 -------
 arch/arm/mach-mxs/mm.c                            |   39 --
 arch/arm/mach-mxs/module-tx28.c                   |  160 ------
 arch/arm/mach-mxs/module-tx28.h                   |   10 -
 37 files changed, 146 insertions(+), 4073 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/devices-mx23.h
 delete mode 100644 arch/arm/mach-mxs/devices-mx28.h
 delete mode 100644 arch/arm/mach-mxs/devices.c
 delete mode 100644 arch/arm/mach-mxs/devices/Kconfig
 delete mode 100644 arch/arm/mach-mxs/devices/Makefile
 delete mode 100644 arch/arm/mach-mxs/devices/platform-auart.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-dma.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-fec.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-flexcan.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-gpio-mxs.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-gpmi-nand.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-i2c.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-mmc.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-pwm.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-saif.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
 delete mode 100644 arch/arm/mach-mxs/include/mach/devices-common.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx23.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx28.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux.h
 delete mode 100644 arch/arm/mach-mxs/iomux.c
 delete mode 100644 arch/arm/mach-mxs/mach-apx4devkit.c
 delete mode 100644 arch/arm/mach-mxs/mach-m28evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-mx23evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-mx28evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-stmp378x_devb.c
 delete mode 100644 arch/arm/mach-mxs/mach-tx28.c
 delete mode 100644 arch/arm/mach-mxs/module-tx28.c
 delete mode 100644 arch/arm/mach-mxs/module-tx28.h

-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:44 +0800
Subject: [PATCH 1/6] ARM: mxs: tx28: reset fec phy for device tree boot
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>

For non-DT boot, function tx28_add_fec0 configures all ENET0 pins
into gpio mode for resetting fec phy, and then reconfigures those pins
into ENET function after that.

For DT boot, all the pin configuration is done by pinctrl subsystem.
Ideally, when gpio_requst gets called, GPIO subsystem should call
pinctrl to configure pins into gpio mode automatically, and have pins
freed up from pinctrl subsystem when gpio_free is called.  But right
now, this cooperation between gpio and pinctrl hasn't been available.
As the result, we have to explicitly call pinctrl_get_select and
pinctrl_put for device tree boot.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Lothar Wa?mann <LW at KARO-electronics.de>
---
 arch/arm/boot/dts/imx28-tx28.dts |   21 +++++++++-
 arch/arm/mach-mxs/mach-mxs.c     |   82 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 101 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767..a56ae05 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -34,6 +34,24 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <0>;
 				};
+
+				mac0_pins_gpio: mac0-gpio-mode at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+						0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+						0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+						0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+						0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+						0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+						0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+						0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+						0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
 			};
 		};
 
@@ -72,8 +90,9 @@
 	ahb at 80080000 {
 		mac0: ethernet at 800f0000 {
 			phy-mode = "rmii";
-			pinctrl-names = "default";
+			pinctrl-names = "default", "gpio_mode";
 			pinctrl-0 = <&mac0_pins_a>;
+			pinctrl-1 = <&mac0_pins_gpio>;
 			status = "okay";
 		};
 	};
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 02d1ab2..6ba37df 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -12,8 +12,9 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
@@ -21,10 +22,12 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
 #include <mach/digctl.h>
+#include <mach/mxs.h>
 
 static struct fb_videomode mx23evk_video_modes[] = {
 	{
@@ -273,6 +276,80 @@ static void __init apx4devkit_init(void)
 	mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 }
 
+#define ENET0_MDC__GPIO_4_0	MXS_GPIO_NR(4, 0)
+#define ENET0_MDIO__GPIO_4_1	MXS_GPIO_NR(4, 1)
+#define ENET0_RX_EN__GPIO_4_2	MXS_GPIO_NR(4, 2)
+#define ENET0_RXD0__GPIO_4_3	MXS_GPIO_NR(4, 3)
+#define ENET0_RXD1__GPIO_4_4	MXS_GPIO_NR(4, 4)
+#define ENET0_TX_EN__GPIO_4_6	MXS_GPIO_NR(4, 6)
+#define ENET0_TXD0__GPIO_4_7	MXS_GPIO_NR(4, 7)
+#define ENET0_TXD1__GPIO_4_8	MXS_GPIO_NR(4, 8)
+#define ENET_CLK__GPIO_4_16	MXS_GPIO_NR(4, 16)
+
+#define TX28_FEC_PHY_POWER	MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET	MXS_GPIO_NR(4, 13)
+#define TX28_FEC_nINT		MXS_GPIO_NR(4, 5)
+
+static const struct gpio tx28_gpios[] __initconst = {
+	{ ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
+	{ ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
+	{ ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
+	{ ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
+	{ ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
+	{ ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
+	{ ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
+	{ ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
+	{ ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
+	{ TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+	{ TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
+	{ TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
+};
+
+static void __init tx28_post_init(void)
+{
+	struct device_node *np;
+	struct platform_device *pdev;
+	struct pinctrl *pctl;
+	int ret;
+
+	enable_clk_enet_out();
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
+	pdev = of_find_device_by_node(np);
+	if (!pdev) {
+		pr_err("%s: failed to find fec device\n", __func__);
+		return;
+	}
+
+	pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
+	if (IS_ERR(pctl)) {
+		pr_err("%s: failed to get pinctrl state\n", __func__);
+		return;
+	}
+
+	ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+	if (ret) {
+		pr_err("%s: failed to request gpios: %d\n", __func__, ret);
+		return;
+	}
+
+	/* Power up fec phy */
+	gpio_set_value(TX28_FEC_PHY_POWER, 1);
+	mdelay(26); /* 25ms according to data sheet */
+
+	/* Mode strap pins */
+	gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
+	gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
+	gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
+
+	udelay(100); /* minimum assertion time for nRST */
+
+	/* Deasserting FEC PHY RESET */
+	gpio_set_value(TX28_FEC_PHY_RESET, 1);
+
+	pinctrl_put(pctl);
+}
+
 static void __init mxs_machine_init(void)
 {
 	if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -286,6 +363,9 @@ static void __init mxs_machine_init(void)
 
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     mxs_auxdata_lookup, NULL);
+
+	if (of_machine_is_compatible("karo,tx28"))
+		tx28_post_init();
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:47 +0800
Subject: [PATCH 4/6] ARM: mxs: remove non-DT core functions
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-5-git-send-email-shawn.guo@linaro.org>

With all board files removed, those core functions used for non-DT
boot only can be removed now.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-mxs/include/mach/common.h |    9 -------
 arch/arm/mach-mxs/mm.c                  |   39 -------------------------------
 2 files changed, 0 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index de6c7ba..4dec795 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -17,21 +17,12 @@ extern void mxs_timer_init(int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
-extern void mx23_soc_init(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
-extern void mx23_init_irq(void);
 
-extern void mx28_soc_init(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
-extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
-extern struct platform_device *mxs_add_dma(const char *devid,
-						resource_size_t base);
-extern struct platform_device *mxs_add_gpio(char *name, int id,
-					    resource_size_t iobase, int irq);
-
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index dccb67a..a4294aa 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,14 +13,11 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/mx23.h>
 #include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
 
 /*
  * Define the MX23 memory map.
@@ -48,43 +45,7 @@ void __init mx23_map_io(void)
 	iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
 }
 
-void __init mx23_init_irq(void)
-{
-	icoll_init_irq();
-}
-
 void __init mx28_map_io(void)
 {
 	iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
 }
-
-void __init mx28_init_irq(void)
-{
-	icoll_init_irq();
-}
-
-void __init mx23_soc_init(void)
-{
-	pinctrl_provide_dummies();
-
-	mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-	mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-	mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
-	mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
-	mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
-}
-
-void __init mx28_soc_init(void)
-{
-	pinctrl_provide_dummies();
-
-	mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-	mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-	mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
-	mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
-	mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
-	mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
-	mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
-}
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:45 +0800
Subject: [PATCH 2/6] ARM: mxs: use auxdata to pass flexcan_switch function hook
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-3-git-send-email-shawn.guo@linaro.org>

There are some efforts going on to have flexcan_switch function
implemented in flexcan driver, so that this platform function hook
can be saved for device tree boot.  But due to the mx28evk board
design oddness that two flexcan transceivers share one switch gpio,
we have to come up a separate and generic gpio-switch driver to handle
all these gpio switch use cases.

Before that happens, we choose to use auxdata to pass flexcan_switch
function hook, so that the DT conversion is not blocked there.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-mxs/mach-mxs.c |   44 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 6ba37df..1bfff30 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/can/platform/flexcan.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
@@ -103,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = {
 
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 
+/*
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
+ */
+#define MX28EVK_FLEXCAN_SWITCH	MXS_GPIO_NR(2, 13)
+
+static int flexcan0_en, flexcan1_en;
+
+static void mx28evk_flexcan_switch(void)
+{
+	if (flexcan0_en || flexcan1_en)
+		gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+	else
+		gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
+}
+
+static void mx28evk_flexcan0_switch(int enable)
+{
+	flexcan0_en = enable;
+	mx28evk_flexcan_switch();
+}
+
+static void mx28evk_flexcan1_switch(int enable)
+{
+	flexcan1_en = enable;
+	mx28evk_flexcan_switch();
+}
+
+static struct flexcan_platform_data flexcan_pdata[2];
+
 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
 	OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+	OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
+	OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
 	{ /* sentinel */ }
 };
 
@@ -245,6 +277,15 @@ static void __init imx28_evk_init(void)
 	mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
 
+static void __init imx28_evk_post_init(void)
+{
+	if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
+			      "flexcan-switch")) {
+		flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
+		flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
+	}
+}
+
 static void __init m28evk_init(void)
 {
 	enable_clk_enet_out();
@@ -366,6 +407,9 @@ static void __init mxs_machine_init(void)
 
 	if (of_machine_is_compatible("karo,tx28"))
 		tx28_post_init();
+
+	if (of_machine_is_compatible("fsl,imx28-evk"))
+		imx28_evk_post_init();
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:48 +0800
Subject: [PATCH 5/6] ARM: mxs: remove platform device codes
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-6-git-send-email-shawn.guo@linaro.org>

With all the board files removed, there is no user for those platform
device code.  Remove them.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-mxs/Kconfig                         |    2 -
 arch/arm/mach-mxs/Makefile                        |    4 +-
 arch/arm/mach-mxs/devices-mx23.h                  |   43 --------
 arch/arm/mach-mxs/devices-mx28.h                  |   63 -----------
 arch/arm/mach-mxs/devices.c                       |   87 ----------------
 arch/arm/mach-mxs/devices/Kconfig                 |   33 ------
 arch/arm/mach-mxs/devices/Makefile                |   12 --
 arch/arm/mach-mxs/devices/platform-auart.c        |   65 ------------
 arch/arm/mach-mxs/devices/platform-dma.c          |   31 ------
 arch/arm/mach-mxs/devices/platform-fec.c          |   52 ----------
 arch/arm/mach-mxs/devices/platform-flexcan.c      |   51 ---------
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c     |   33 ------
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c    |   81 ---------------
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c      |   52 ----------
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c      |   76 --------------
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c      |   22 ----
 arch/arm/mach-mxs/devices/platform-mxs-saif.c     |   61 -----------
 arch/arm/mach-mxs/devices/platform-mxsfb.c        |   47 ---------
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c |   51 ---------
 arch/arm/mach-mxs/include/mach/devices-common.h   |  114 ---------------------
 20 files changed, 1 insertions(+), 979 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/devices-mx23.h
 delete mode 100644 arch/arm/mach-mxs/devices-mx28.h
 delete mode 100644 arch/arm/mach-mxs/devices.c
 delete mode 100644 arch/arm/mach-mxs/devices/Kconfig
 delete mode 100644 arch/arm/mach-mxs/devices/Makefile
 delete mode 100644 arch/arm/mach-mxs/devices/platform-auart.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-dma.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-fec.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-flexcan.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-gpio-mxs.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-gpmi-nand.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-i2c.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-mmc.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-pwm.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxs-saif.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-mxsfb.c
 delete mode 100644 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
 delete mode 100644 arch/arm/mach-mxs/include/mach/devices-common.h

diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 2e6cb6d..ecc4319 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,7 +1,5 @@
 if ARCH_MXS
 
-source "arch/arm/mach-mxs/devices/Kconfig"
-
 config SOC_IMX23
 	bool
 	select ARM_AMBA
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index a7ace24..2480ce9 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,8 +1,6 @@
 # Common support
-obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
+obj-y := icoll.o iomux.o ocotp.o system.o timer.o mm.o
 
 obj-$(CONFIG_PM) += pm.o
 
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
-
-obj-y += devices/
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
deleted file mode 100644
index 9ee5ced..0000000
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx23.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx23_add_duart(void)
-{
-	struct amba_device *d;
-
-	d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
-				MX23_INT_DUART, 0, 0, 0);
-	return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx23_auart_data[] __initconst;
-#define mx23_add_auart(id)	mxs_add_auart(&mx23_auart_data[id])
-#define mx23_add_auart0()		mx23_add_auart(0)
-#define mx23_add_auart1()		mx23_add_auart(1)
-
-extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
-#define mx23_add_gpmi_nand(pdata)	\
-	mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
-
-extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
-#define mx23_add_mxs_mmc(id, pdata) \
-	mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
-
-#define mx23_add_mxs_pwm(id)		mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx23_add_mxsfb(
-		const struct mxsfb_platform_data *pdata);
-
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
deleted file mode 100644
index fcab431..0000000
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx28_add_duart(void)
-{
-	struct amba_device *d;
-
-	d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
-				MX28_INT_DUART, 0, 0, 0);
-	return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx28_auart_data[] __initconst;
-#define mx28_add_auart(id)	mxs_add_auart(&mx28_auart_data[id])
-#define mx28_add_auart0()		mx28_add_auart(0)
-#define mx28_add_auart1()		mx28_add_auart(1)
-#define mx28_add_auart2()		mx28_add_auart(2)
-#define mx28_add_auart3()		mx28_add_auart(3)
-#define mx28_add_auart4()		mx28_add_auart(4)
-
-extern const struct mxs_fec_data mx28_fec_data[] __initconst;
-#define mx28_add_fec(id, pdata) \
-	mxs_add_fec(&mx28_fec_data[id], pdata)
-
-extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
-#define mx28_add_flexcan(id, pdata)	\
-	mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
-#define mx28_add_flexcan0(pdata)	mx28_add_flexcan(0, pdata)
-#define mx28_add_flexcan1(pdata)	mx28_add_flexcan(1, pdata)
-
-extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
-#define mx28_add_gpmi_nand(pdata)	\
-	mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
-
-extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
-#define mx28_add_mxs_i2c(id)		mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
-
-extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
-#define mx28_add_mxs_mmc(id, pdata) \
-	mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata)
-
-#define mx28_add_mxs_pwm(id)		mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx28_add_mxsfb(
-		const struct mxsfb_platform_data *pdata);
-
-extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id, pdata) \
-	mxs_add_saif(&mx28_saif_data[id], pdata)
-
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
deleted file mode 100644
index cf50b5a..0000000
--- a/arch/arm/mach-mxs/devices.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, kernel at pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-
-struct platform_device *__init mxs_add_platform_device_dmamask(
-		const char *name, int id,
-		const struct resource *res, unsigned int num_resources,
-		const void *data, size_t size_data, u64 dmamask)
-{
-	int ret = -ENOMEM;
-	struct platform_device *pdev;
-
-	pdev = platform_device_alloc(name, id);
-	if (!pdev)
-		goto err;
-
-	if (dmamask) {
-		/*
-		 * This memory isn't freed when the device is put,
-		 * I don't have a nice idea for that though.  Conceptually
-		 * dma_mask in struct device should not be a pointer.
-		 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
-		 */
-		pdev->dev.dma_mask =
-			kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-		if (!pdev->dev.dma_mask)
-			/* ret is still -ENOMEM; */
-			goto err;
-
-		*pdev->dev.dma_mask = dmamask;
-		pdev->dev.coherent_dma_mask = dmamask;
-	}
-
-	if (res) {
-		ret = platform_device_add_resources(pdev, res, num_resources);
-		if (ret)
-			goto err;
-	}
-
-	if (data) {
-		ret = platform_device_add_data(pdev, data, size_data);
-		if (ret)
-			goto err;
-	}
-
-	ret = platform_device_add(pdev);
-	if (ret) {
-err:
-		if (dmamask)
-			kfree(pdev->dev.dma_mask);
-		platform_device_put(pdev);
-		return ERR_PTR(ret);
-	}
-
-	return pdev;
-}
-
-struct device mxs_apbh_bus = {
-	.init_name	= "mxs_apbh",
-	.parent         = &platform_bus,
-};
-
-static int __init mxs_device_init(void)
-{
-	return device_register(&mxs_apbh_bus);
-}
-core_initcall(mxs_device_init);
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
deleted file mode 100644
index 19659de..0000000
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-config MXS_HAVE_AMBA_DUART
-	bool
-
-config MXS_HAVE_PLATFORM_AUART
-	bool
-
-config MXS_HAVE_PLATFORM_FEC
-	bool
-
-config MXS_HAVE_PLATFORM_FLEXCAN
-	select HAVE_CAN_FLEXCAN if CAN
-	bool
-
-config MXS_HAVE_PLATFORM_GPMI_NAND
-	bool
-
-config MXS_HAVE_PLATFORM_MXS_I2C
-	bool
-
-config MXS_HAVE_PLATFORM_MXS_MMC
-	bool
-
-config MXS_HAVE_PLATFORM_MXS_PWM
-	bool
-
-config MXS_HAVE_PLATFORM_MXSFB
-	bool
-
-config MXS_HAVE_PLATFORM_MXS_SAIF
-	bool
-
-config MXS_HAVE_PLATFORM_RTC_STMP3XXX
-	bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
deleted file mode 100644
index 5f72d97..0000000
--- a/arch/arm/mach-mxs/devices/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
-obj-y += platform-dma.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
-obj-y += platform-gpio-mxs.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
deleted file mode 100644
index 27608f5..0000000
--- a/arch/arm/mach-mxs/devices/platform-auart.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_auart_data_entry_single(soc, _id, hwid)			\
-	{								\
-		.id = _id,						\
-		.iobase = soc ## _AUART ## hwid ## _BASE_ADDR,		\
-		.irq = soc ## _INT_AUART ## hwid,			\
-	}
-
-#define mxs_auart_data_entry(soc, _id, hwid)				\
-	[_id] = mxs_auart_data_entry_single(soc, _id, hwid)
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_auart_data mx23_auart_data[] __initconst = {
-#define mx23_auart_data_entry(_id, hwid)				\
-	mxs_auart_data_entry(MX23, _id, hwid)
-	mx23_auart_data_entry(0, 1),
-	mx23_auart_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_auart_data mx28_auart_data[] __initconst = {
-#define mx28_auart_data_entry(_id)					\
-	mxs_auart_data_entry(MX28, _id, _id)
-	mx28_auart_data_entry(0),
-	mx28_auart_data_entry(1),
-	mx28_auart_data_entry(2),
-	mx28_auart_data_entry(3),
-	mx28_auart_data_entry(4),
-};
-#endif
-
-struct platform_device *__init mxs_add_auart(
-		const struct mxs_auart_data *data)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->irq,
-			.end = data->irq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device_dmamask("mxs-auart", data->id,
-					res, ARRAY_SIZE(res), NULL, 0,
-					DMA_BIT_MASK(32));
-}
-
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
deleted file mode 100644
index 4682450..0000000
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_dma(const char *devid,
-						resource_size_t base)
-{
-	struct resource res[] = {
-		{
-			.start = base,
-			.end = base + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}
-	};
-
-	return mxs_add_platform_device_dmamask(devid, -1,
-				res, ARRAY_SIZE(res), NULL, 0,
-				DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
deleted file mode 100644
index ae96a4f..0000000
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_fec_data_entry_single(soc, _id)				\
-	{								\
-		.id = _id,						\
-		.iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,	\
-		.irq = soc ## _INT_ENET_MAC ## _id,			\
-	}
-
-#define mxs_fec_data_entry(soc, _id)					\
-	[_id] = mxs_fec_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_fec_data mx28_fec_data[] __initconst = {
-#define mx28_fec_data_entry(_id)					\
-	mxs_fec_data_entry(MX28, _id)
-	mx28_fec_data_entry(0),
-	mx28_fec_data_entry(1),
-};
-#endif
-
-struct platform_device *__init mxs_add_fec(
-		const struct mxs_fec_data *data,
-		const struct fec_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + SZ_16K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->irq,
-			.end = data->irq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device_dmamask("imx28-fec", data->id,
-			res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
-			DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
deleted file mode 100644
index 43a6b4b..0000000
--- a/arch/arm/mach-mxs/devices/platform-flexcan.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010, 2011 Pengutronix,
- *                          Marc Kleine-Budde <kernel at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)		\
-	{								\
-		.id = _id,						\
-		.iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,		\
-		.iosize = _size,					\
-		.irq = soc ## _INT_CAN ## _hwid,			\
-	}
-
-#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)			\
-	[_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
-#define mx28_flexcan_data_entry(_id, _hwid)				\
-	mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
-	mx28_flexcan_data_entry(0, 0),
-	mx28_flexcan_data_entry(1, 1),
-};
-#endif /* ifdef CONFIG_SOC_IMX28 */
-
-struct platform_device *__init mxs_add_flexcan(
-		const struct mxs_flexcan_data *data,
-		const struct flexcan_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + data->iosize - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->irq,
-			.end = data->irq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device("flexcan", data->id,
-			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
deleted file mode 100644
index cd99f19..0000000
--- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_gpio(
-	char *name, int id, resource_size_t iobase, int irq)
-{
-	struct resource res[] = {
-		{
-			.start = iobase,
-			.end = iobase + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = irq,
-			.end = irq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return platform_device_register_resndata(&mxs_apbh_bus,
-			name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
deleted file mode 100644
index 3e22df5..0000000
--- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/dma-mapping.h>
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
-	.devid = "imx23-gpmi-nand",
-	.res = {
-		/* GPMI */
-		DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
-					GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-		DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
-					GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-		/* BCH */
-		DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
-					GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-		DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
-					GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-		/* DMA */
-		DEFINE_RES_NAMED(MX23_DMA_GPMI0,
-					MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
-					GPMI_NAND_DMA_CHANNELS_RES_NAME,
-					IORESOURCE_DMA),
-		DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
-					GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-	},
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
-	.devid = "imx28-gpmi-nand",
-	.res = {
-		/* GPMI */
-		DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
-					GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-		DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
-					GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-		/* BCH */
-		DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
-					GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-		DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
-					GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-		/* DMA */
-		DEFINE_RES_NAMED(MX28_DMA_GPMI0,
-					MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
-					GPMI_NAND_DMA_CHANNELS_RES_NAME,
-					IORESOURCE_DMA),
-		DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
-					GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-	},
-};
-#endif
-
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-		const struct mxs_gpmi_nand_data *data)
-{
-	return mxs_add_platform_device_dmamask(data->devid, -1,
-				data->res, GPMI_NAND_RES_SIZE,
-				pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
deleted file mode 100644
index 79222ec..0000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix
- * Wolfram Sang <w.sang at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_i2c_data_entry_single(soc, _id)				\
-	{								\
-		.id = _id,						\
-		.iobase = soc ## _I2C ## _id ## _BASE_ADDR,		\
-		.errirq = soc ## _INT_I2C ## _id ## _ERROR,		\
-		.dmairq = soc ## _INT_I2C ## _id ## _DMA,		\
-	}
-
-#define mxs_i2c_data_entry(soc, _id)					\
-	[_id] = mxs_i2c_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
-	mxs_i2c_data_entry(MX28, 0),
-	mxs_i2c_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_i2c(
-		const struct mxs_mxs_i2c_data *data)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->errirq,
-			.end = data->errirq,
-			.flags = IORESOURCE_IRQ,
-		}, {
-			.start = data->dmairq,
-			.end = data->dmairq,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device("mxs-i2c", data->id, res,
-					ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
deleted file mode 100644
index b33c9d0..0000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)		\
-	{								\
-		.devid = _devid,					\
-		.id = _id,						\
-		.iobase = soc ## _SSP ## hwid ## _BASE_ADDR,		\
-		.dma = soc ## _DMA_SSP ## hwid,				\
-		.irq_err = soc ## _INT_SSP ## hwid ## _ERROR,		\
-		.irq_dma = soc ## _INT_SSP ## hwid ## _DMA,		\
-	}
-
-#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid)			\
-	[_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)
-
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
-	mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1),
-	mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
-	mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0),
-	mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1),
-	mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2),
-	mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_mmc(
-		const struct mxs_mxs_mmc_data *data,
-		const struct mxs_mmc_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start	= data->iobase,
-			.end	= data->iobase + SZ_8K - 1,
-			.flags	= IORESOURCE_MEM,
-		}, {
-			.start	= data->dma,
-			.end	= data->dma,
-			.flags	= IORESOURCE_DMA,
-		}, {
-			.start	= data->irq_err,
-			.end	= data->irq_err,
-			.flags	= IORESOURCE_IRQ,
-		}, {
-			.start	= data->irq_dma,
-			.end	= data->irq_dma,
-			.flags	= IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device(data->devid, data->id,
-			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
deleted file mode 100644
index 680f5a9..0000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
-{
-	struct resource res = {
-		.flags = IORESOURCE_MEM,
-	};
-
-	res.start = iobase + 0x10 + 0x20 * id;
-	res.end = res.start + 0x1f;
-
-	return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
deleted file mode 100644
index f6e3a60..0000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_saif_data_entry_single(soc, _id)				\
-	{								\
-		.id = _id,						\
-		.iobase = soc ## _SAIF ## _id ## _BASE_ADDR,		\
-		.irq = soc ## _INT_SAIF ## _id,				\
-		.dma = soc ## _DMA_SAIF ## _id,				\
-		.dmairq = soc ## _INT_SAIF ## _id ##_DMA,		\
-	}
-
-#define mxs_saif_data_entry(soc, _id)					\
-	[_id] = mxs_saif_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_saif_data mx28_saif_data[] __initconst = {
-	mxs_saif_data_entry(MX28, 0),
-	mxs_saif_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
-				const struct mxs_saif_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = data->iobase,
-			.end = data->iobase + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = data->irq,
-			.end = data->irq,
-			.flags = IORESOURCE_IRQ,
-		}, {
-			.start = data->dma,
-			.end = data->dma,
-			.flags = IORESOURCE_DMA,
-		}, {
-			.start = data->dmairq,
-			.end = data->dmairq,
-			.flags = IORESOURCE_IRQ,
-		},
-
-	};
-
-	return mxs_add_platform_device("mxs-saif", data->id, res,
-				ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
deleted file mode 100644
index 76b53f73..0000000
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_mxsfb(
-		const struct mxsfb_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = MX23_LCDIF_BASE_ADDR,
-			.end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-	};
-
-	return mxs_add_platform_device_dmamask("imx23-fb", -1,
-			res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_mxsfb(
-		const struct mxsfb_platform_data *pdata)
-{
-	struct resource res[] = {
-		{
-			.start = MX28_LCDIF_BASE_ADDR,
-			.end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-	};
-
-	return mxs_add_platform_device_dmamask("imx28-fb", -1,
-			res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
deleted file mode 100644
index 639eaee..0000000
--- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void)
-{
-	struct resource res[] = {
-		{
-			.start = MX23_RTC_BASE_ADDR,
-			.end = MX23_RTC_BASE_ADDR + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = MX23_INT_RTC_ALARM,
-			.end = MX23_INT_RTC_ALARM,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-					NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void)
-{
-	struct resource res[] = {
-		{
-			.start = MX28_RTC_BASE_ADDR,
-			.end = MX28_RTC_BASE_ADDR + SZ_8K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
-			.start = MX28_INT_RTC_ALARM,
-			.end = MX28_INT_RTC_ALARM,
-			.flags = IORESOURCE_IRQ,
-		},
-	};
-
-	return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-					NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
deleted file mode 100644
index e8b1d95..0000000
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/amba/bus.h>
-
-extern struct device mxs_apbh_bus;
-
-struct platform_device *mxs_add_platform_device_dmamask(
-		const char *name, int id,
-		const struct resource *res, unsigned int num_resources,
-		const void *data, size_t size_data, u64 dmamask);
-
-static inline struct platform_device *mxs_add_platform_device(
-		const char *name, int id,
-		const struct resource *res, unsigned int num_resources,
-		const void *data, size_t size_data)
-{
-	return mxs_add_platform_device_dmamask(
-			name, id, res, num_resources, data, size_data, 0);
-}
-
-/* auart */
-struct mxs_auart_data {
-	int id;
-	resource_size_t iobase;
-	resource_size_t iosize;
-	resource_size_t irq;
-};
-struct platform_device *__init mxs_add_auart(
-		const struct mxs_auart_data *data);
-
-/* fec */
-#include <linux/fec.h>
-struct mxs_fec_data {
-	int id;
-	resource_size_t iobase;
-	resource_size_t iosize;
-	resource_size_t irq;
-};
-struct platform_device *__init mxs_add_fec(
-		const struct mxs_fec_data *data,
-		const struct fec_platform_data *pdata);
-
-/* flexcan */
-#include <linux/can/platform/flexcan.h>
-struct mxs_flexcan_data {
-	int id;
-	resource_size_t iobase;
-	resource_size_t iosize;
-	resource_size_t irq;
-};
-struct platform_device *__init mxs_add_flexcan(
-		const struct mxs_flexcan_data *data,
-		const struct flexcan_platform_data *pdata);
-
-/* gpmi-nand */
-#include <linux/mtd/gpmi-nand.h>
-struct mxs_gpmi_nand_data {
-	const char *devid;
-	const struct resource res[GPMI_NAND_RES_SIZE];
-};
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-		const struct mxs_gpmi_nand_data *data);
-
-/* i2c */
-struct mxs_mxs_i2c_data {
-	int id;
-	resource_size_t iobase;
-	resource_size_t errirq;
-	resource_size_t dmairq;
-};
-struct platform_device * __init mxs_add_mxs_i2c(
-		const struct mxs_mxs_i2c_data *data);
-
-/* mmc */
-#include <linux/mmc/mxs-mmc.h>
-struct mxs_mxs_mmc_data {
-	const char *devid;
-	int id;
-	resource_size_t iobase;
-	resource_size_t dma;
-	resource_size_t irq_err;
-	resource_size_t irq_dma;
-};
-struct platform_device *__init mxs_add_mxs_mmc(
-		const struct mxs_mxs_mmc_data *data,
-		const struct mxs_mmc_platform_data *pdata);
-
-/* pwm */
-struct platform_device *__init mxs_add_mxs_pwm(
-		resource_size_t iobase, int id);
-
-/* saif */
-#include <sound/saif.h>
-struct mxs_saif_data {
-	int id;
-	resource_size_t iobase;
-	resource_size_t irq;
-	resource_size_t dma;
-	resource_size_t dmairq;
-};
-
-struct platform_device *__init mxs_add_saif(
-		const struct mxs_saif_data *data,
-		const struct mxs_saif_platform_data *pdata);
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:46 +0800
Subject: [PATCH 3/6] ARM: mxs: remove board files
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-4-git-send-email-shawn.guo@linaro.org>

Since DT kernel provides the equivalent support with those board
files, we can remove them now.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Lothar Wa?mann <LW at KARO-electronics.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Lauri Hintsala <lauri.hintsala at bluegiga.com>
---
 arch/arm/configs/mxs_defconfig         |    6 -
 arch/arm/mach-mxs/Kconfig              |   87 ------
 arch/arm/mach-mxs/Makefile             |    7 -
 arch/arm/mach-mxs/mach-apx4devkit.c    |  273 ------------------
 arch/arm/mach-mxs/mach-m28evk.c        |  366 ------------------------
 arch/arm/mach-mxs/mach-mx23evk.c       |  190 -------------
 arch/arm/mach-mxs/mach-mx28evk.c       |  477 --------------------------------
 arch/arm/mach-mxs/mach-stmp378x_devb.c |  123 --------
 arch/arm/mach-mxs/mach-tx28.c          |  184 ------------
 arch/arm/mach-mxs/module-tx28.c        |  160 -----------
 arch/arm/mach-mxs/module-tx28.h        |   10 -
 11 files changed, 0 insertions(+), 1883 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/mach-apx4devkit.c
 delete mode 100644 arch/arm/mach-mxs/mach-m28evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-mx23evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-mx28evk.c
 delete mode 100644 arch/arm/mach-mxs/mach-stmp378x_devb.c
 delete mode 100644 arch/arm/mach-mxs/mach-tx28.c
 delete mode 100644 arch/arm/mach-mxs/module-tx28.c
 delete mode 100644 arch/arm/mach-mxs/module-tx28.h

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index ccdb635..e5fc6c2 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXS=y
 CONFIG_MACH_MXS_DT=y
-CONFIG_MACH_MX23EVK=y
-CONFIG_MACH_MX28EVK=y
-CONFIG_MACH_STMP378X_DEVB=y
-CONFIG_MACH_TX28=y
-CONFIG_MACH_M28EVK=y
-CONFIG_MACH_APX4DEVKIT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 9a8bbda..2e6cb6d 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -27,91 +27,4 @@ config MACH_MXS_DT
 	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
 	  using the device tree for discovery
 
-config MACH_STMP378X_DEVB
-	bool "Support STMP378x_devb Platform"
-	select SOC_IMX23
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-	help
-	  Include support for STMP378x-devb platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MACH_MX23EVK
-	bool "Support MX23EVK Platform"
-	select SOC_IMX23
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_MXSFB
-	select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-	help
-	  Include support for MX23EVK platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MACH_MX28EVK
-	bool "Support MX28EVK Platform"
-	select SOC_IMX28
-	select LEDS_GPIO_REGISTER
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_FEC
-	select MXS_HAVE_PLATFORM_FLEXCAN
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_MXSFB
-	select MXS_HAVE_PLATFORM_MXS_SAIF
-	select MXS_HAVE_PLATFORM_MXS_I2C
-	select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-	help
-	  Include support for MX28EVK platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MODULE_TX28
-	bool
-	select SOC_IMX28
-	select LEDS_GPIO_REGISTER
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_FEC
-	select MXS_HAVE_PLATFORM_MXS_I2C
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_MXS_PWM
-	select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-
-config MODULE_M28
-	bool
-	select SOC_IMX28
-	select LEDS_GPIO_REGISTER
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_FEC
-	select MXS_HAVE_PLATFORM_FLEXCAN
-	select MXS_HAVE_PLATFORM_MXS_I2C
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_MXSFB
-
-config MODULE_APX4
-	bool
-	select SOC_IMX28
-	select LEDS_GPIO_REGISTER
-	select MXS_HAVE_AMBA_DUART
-	select MXS_HAVE_PLATFORM_AUART
-	select MXS_HAVE_PLATFORM_FEC
-	select MXS_HAVE_PLATFORM_MXS_I2C
-	select MXS_HAVE_PLATFORM_MXS_MMC
-	select MXS_HAVE_PLATFORM_MXS_SAIF
-
-config MACH_TX28
-	bool "Ka-Ro TX28 module"
-	select MODULE_TX28
-
-config MACH_M28EVK
-	bool "Support DENX M28EVK Platform"
-	select MODULE_M28
-
-config MACH_APX4DEVKIT
-	bool "Support Bluegiga APX4 Development Kit"
-	select MODULE_APX4
-
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index fed3695..a7ace24 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -4,12 +4,5 @@ obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
 obj-$(CONFIG_PM) += pm.o
 
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
-obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
-obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
-obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
-obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
-obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
-obj-$(CONFIG_MODULE_TX28) += module-tx28.o
-obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 
 obj-y += devices/
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
deleted file mode 100644
index f5f0617..0000000
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (C) 2011-2012
- * Lauri Hintsala, Bluegiga, <lauri.hintsala at bluegiga.com>
- * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola at bluegiga.com>
- *
- * based on: mach-mx28evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/micrel_phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define APX4DEVKIT_GPIO_USERLED	MXS_GPIO_NR(3, 28)
-
-static const iomux_cfg_t apx4devkit_pads[] __initconst = {
-	/* duart */
-	MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-	MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-	/* auart0 */
-	MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-
-	/* auart1 */
-	MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-
-	/* auart2 */
-	MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
-	MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
-
-	/* auart3 */
-	MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
-	MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC	(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-	/* fec0 */
-	MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-
-	/* i2c */
-	MX28_PAD_I2C0_SCL__I2C0_SCL,
-	MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-	/* mmc0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA1__SSP0_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA2__SSP0_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA3__SSP0_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA4__SSP0_D4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA5__SSP0_D5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA6__SSP0_D6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA7__SSP0_D7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_CMD__SSP0_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-	/* led */
-	MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-
-	/* saif0 & saif1 */
-	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led apx4devkit_leds[] __initconst = {
-	{
-		.name = "user-led",
-		.default_trigger = "heartbeat",
-		.gpio = APX4DEVKIT_GPIO_USERLED,
-	},
-};
-
-static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
-	.leds = apx4devkit_leds,
-	.num_leds = ARRAY_SIZE(apx4devkit_leds),
-};
-
-static const struct fec_platform_data mx28_fec_pdata __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
-	.wp_gpio = -EINVAL,
-	.flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
-	{ I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
-	{ I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
-		defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
-	REGULATOR_SUPPLY("VDDA", "0-000a"),
-	REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
-	.constraints	= {
-		.name	= "3V3",
-		.always_on = 1,
-	},
-	.consumer_supplies = apx4devkit_audio_consumer_supplies,
-	.num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config apx4devkit_vdd_pdata = {
-	.supply_name	= "board-3V3",
-	.microvolts	= 3300000,
-	.gpio		= -EINVAL,
-	.enabled_at_boot = 1,
-	.init_data	= &apx4devkit_vdd_reg_init_data,
-};
-
-static struct platform_device apx4devkit_voltage_regulator = {
-	.name		= "reg-fixed-voltage",
-	.id		= -1,
-	.num_resources	= 0,
-	.dev		= {
-		.platform_data	= &apx4devkit_vdd_pdata,
-	},
-};
-
-static void __init apx4devkit_add_regulators(void)
-{
-	platform_device_register(&apx4devkit_voltage_regulator);
-}
-#else
-static void __init apx4devkit_add_regulators(void) {}
-#endif
-
-static const struct mxs_saif_platform_data
-			apx4devkit_mxs_saif_pdata[] __initconst = {
-	/* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-	{
-		.master_mode = 1,
-		.master_id = 0,
-	}, {
-		.master_mode = 0,
-		.master_id = 0,
-	},
-};
-
-static int apx4devkit_phy_fixup(struct phy_device *phy)
-{
-	phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
-	return 0;
-}
-
-static void __init apx4devkit_fec_phy_clk_enable(void)
-{
-	struct clk *clk;
-
-	/* Enable fec phy clock */
-	clk = clk_get_sys("enet_out", NULL);
-	if (!IS_ERR(clk))
-		clk_prepare_enable(clk);
-}
-
-static void __init apx4devkit_init(void)
-{
-	mx28_soc_init();
-
-	mxs_iomux_setup_multiple_pads(apx4devkit_pads,
-			ARRAY_SIZE(apx4devkit_pads));
-
-	mx28_add_duart();
-	mx28_add_auart0();
-	mx28_add_auart1();
-	mx28_add_auart2();
-	mx28_add_auart3();
-
-	/*
-	 * Register fixup for the Micrel KS8031 PHY clock
-	 * (shares same ID with KS8051)
-	 */
-	phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
-			apx4devkit_phy_fixup);
-
-	apx4devkit_fec_phy_clk_enable();
-	mx28_add_fec(0, &mx28_fec_pdata);
-
-	mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
-
-	gpio_led_register_device(0, &apx4devkit_led_data);
-
-	mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-	mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
-	mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
-
-	apx4devkit_add_regulators();
-
-	mx28_add_mxs_i2c(0);
-	i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
-			ARRAY_SIZE(apx4devkit_i2c_boardinfo));
-
-	mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
-}
-
-static void __init apx4devkit_timer_init(void)
-{
-	mx28_clocks_init();
-}
-
-static struct sys_timer apx4devkit_timer = {
-	.init	= apx4devkit_timer_init,
-};
-
-MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
-	.map_io		= mx28_map_io,
-	.init_irq	= mx28_init_irq,
-	.timer		= &apx4devkit_timer,
-	.init_machine	= apx4devkit_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
deleted file mode 100644
index 4c00c87..0000000
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic at denx.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define M28EVK_GPIO_USERLED1	MXS_GPIO_NR(3, 16)
-#define M28EVK_GPIO_USERLED2	MXS_GPIO_NR(3, 17)
-
-#define MX28EVK_BL_ENABLE	MXS_GPIO_NR(3, 18)
-#define M28EVK_LCD_ENABLE	MXS_GPIO_NR(3, 28)
-
-#define MX28EVK_MMC0_WRITE_PROTECT	MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT	MXS_GPIO_NR(0, 28)
-
-static const iomux_cfg_t m28evk_pads[] __initconst = {
-	/* duart */
-	MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
-
-	/* auart0 */
-	MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-
-	/* auart3 */
-	MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC	(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-	/* fec0 */
-	MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-	/* fec1 */
-	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-
-	/* flexcan0 */
-	MX28_PAD_GPMI_RDY2__CAN0_TX,
-	MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-	/* flexcan1 */
-	MX28_PAD_GPMI_CE2N__CAN1_TX,
-	MX28_PAD_GPMI_CE3N__CAN1_RX,
-
-	/* I2C */
-	MX28_PAD_I2C0_SCL__I2C0_SCL,
-	MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-	/* mxsfb (lcdif) */
-	MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-
-	MX28_PAD_LCD_ENABLE__LCD_ENABLE	| MXS_PAD_CTRL,
-	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
-
-	/* mmc0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA1__SSP0_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA2__SSP0_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA3__SSP0_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA4__SSP0_D4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA5__SSP0_D5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA6__SSP0_D6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA7__SSP0_D7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_CMD__SSP0_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-	/* mmc1 */
-	MX28_PAD_GPMI_D00__SSP1_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D01__SSP1_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D02__SSP1_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D03__SSP1_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D04__SSP1_D4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D05__SSP1_D5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D06__SSP1_D6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D07__SSP1_D7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_RDY1__SSP1_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_WRN__SSP1_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* write protect */
-	MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* slot power enable */
-	MX28_PAD_PWM4__GPIO_3_29 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-	/* led */
-	MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
-	MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
-
-	/* nand */
-	MX28_PAD_GPMI_D00__GPMI_D0 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D01__GPMI_D1 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D02__GPMI_D2 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D03__GPMI_D3 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D04__GPMI_D4 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D05__GPMI_D5 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D06__GPMI_D6 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_D07__GPMI_D7 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_CE0N__GPMI_CE0N |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_RDY0__GPMI_READY0 |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_RDN__GPMI_RDN |
-		(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_WRN__GPMI_WRN |
-		(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_ALE__GPMI_ALE |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_CLE__GPMI_CLE |
-		(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_RESETN__GPMI_RESETN |
-		(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-
-	/* Backlight */
-	MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-};
-
-/* led */
-static const struct gpio_led m28evk_leds[] __initconst = {
-	{
-		.name = "user-led1",
-		.default_trigger = "heartbeat",
-		.gpio = M28EVK_GPIO_USERLED1,
-	},
-	{
-		.name = "user-led2",
-		.default_trigger = "heartbeat",
-		.gpio = M28EVK_GPIO_USERLED2,
-	},
-};
-
-static const struct gpio_led_platform_data m28evk_led_data __initconst = {
-	.leds = m28evk_leds,
-	.num_leds = ARRAY_SIZE(m28evk_leds),
-};
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-	{
-		/* fec0 */
-		.phy = PHY_INTERFACE_MODE_RMII,
-	}, {
-		/* fec1 */
-		.phy = PHY_INTERFACE_MODE_RMII,
-	},
-};
-
-static int __init m28evk_fec_get_mac(void)
-{
-	int i;
-	u32 val;
-	const u32 *ocotp = mxs_get_ocotp();
-
-	if (!ocotp)
-		return -ETIMEDOUT;
-
-	/*
-	 * OCOTP only stores the last 4 octets for each mac address,
-	 * so hard-code DENX OUI (C0:E5:4E) here.
-	 */
-	for (i = 0; i < 2; i++) {
-		val = ocotp[i];
-		mx28_fec_pdata[i].mac[0] = 0xC0;
-		mx28_fec_pdata[i].mac[1] = 0xE5;
-		mx28_fec_pdata[i].mac[2] = 0x4E;
-		mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-		mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-		mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-	}
-
-	return 0;
-}
-
-/* mxsfb (lcdif) */
-static struct fb_videomode m28evk_video_modes[] = {
-	{
-		.name		= "Ampire AM-800480R2TMQW-T01H",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= 30066, /* picosecond (33.26 MHz) */
-		.left_margin	= 0,
-		.right_margin	= 256,
-		.upper_margin	= 0,
-		.lower_margin	= 45,
-		.hsync_len	= 1,
-		.vsync_len	= 1,
-		.sync		= FB_SYNC_DATA_ENABLE_HIGH_ACT,
-	},
-};
-
-static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
-	.mode_list	= m28evk_video_modes,
-	.mode_count	= ARRAY_SIZE(m28evk_video_modes),
-	.default_bpp	= 16,
-	.ld_intf_width	= STMLCDIF_18BIT,
-};
-
-static struct at24_platform_data m28evk_eeprom = {
-	.byte_len = 16384,
-	.page_size = 32,
-	.flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
-	{
-		I2C_BOARD_INFO("at24", 0x51),	/* E0=1, E1=0, E2=0 */
-		.platform_data = &m28evk_eeprom,
-	},
-};
-
-static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
-	{
-		/* mmc0 */
-		.wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-		.flags = SLOTF_8_BIT_CAPABLE,
-	}, {
-		/* mmc1 */
-		.wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-		.flags = SLOTF_8_BIT_CAPABLE,
-	},
-};
-
-static void __init m28evk_init(void)
-{
-	mx28_soc_init();
-
-	mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
-
-	mx28_add_duart();
-	mx28_add_auart0();
-	mx28_add_auart3();
-
-	if (!m28evk_fec_get_mac()) {
-		mx28_add_fec(0, &mx28_fec_pdata[0]);
-		mx28_add_fec(1, &mx28_fec_pdata[1]);
-	}
-
-	mx28_add_flexcan(0, NULL);
-	mx28_add_flexcan(1, NULL);
-
-	mx28_add_mxsfb(&m28evk_mxsfb_pdata);
-
-	mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
-	mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
-
-	gpio_led_register_device(0, &m28evk_led_data);
-
-	/* I2C */
-	mx28_add_mxs_i2c(0);
-	i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
-			ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
-}
-
-static void __init m28evk_timer_init(void)
-{
-	mx28_clocks_init();
-}
-
-static struct sys_timer m28evk_timer = {
-	.init	= m28evk_timer_init,
-};
-
-MACHINE_START(M28EVK, "DENX M28 EVK")
-	.map_io		= mx28_map_io,
-	.init_irq	= mx28_init_irq,
-	.timer		= &m28evk_timer,
-	.init_machine	= m28evk_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
deleted file mode 100644
index e7272a4..0000000
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define MX23EVK_LCD_ENABLE	MXS_GPIO_NR(1, 18)
-#define MX23EVK_BL_ENABLE	MXS_GPIO_NR(1, 28)
-#define MX23EVK_MMC0_WRITE_PROTECT	MXS_GPIO_NR(1, 30)
-#define MX23EVK_MMC0_SLOT_POWER		MXS_GPIO_NR(1, 29)
-
-static const iomux_cfg_t mx23evk_pads[] __initconst = {
-	/* duart */
-	MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-	MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-	/* auart */
-	MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-	MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-	MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
-	MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
-
-	/* mxsfb (lcdif) */
-	MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
-	MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
-	MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
-	MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
-	MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
-	MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-	/* LCD panel enable */
-	MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
-	/* backlight control */
-	MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
-
-	/* mmc */
-	MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_GPMI_D08__SSP1_DATA4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_GPMI_D09__SSP1_DATA5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_GPMI_D10__SSP1_DATA6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_GPMI_D11__SSP1_DATA7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_CMD__SSP1_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX23_PAD_SSP1_SCK__SSP1_SCK |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* write protect */
-	MX23_PAD_PWM4__GPIO_1_30 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* slot power enable */
-	MX23_PAD_PWM3__GPIO_1_29 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx23evk_video_modes[] = {
-	{
-		.name		= "Samsung-LMS430HF02",
-		.refresh	= 60,
-		.xres		= 480,
-		.yres		= 272,
-		.pixclock	= 108096, /* picosecond (9.2 MHz) */
-		.left_margin	= 15,
-		.right_margin	= 8,
-		.upper_margin	= 12,
-		.lower_margin	= 4,
-		.hsync_len	= 1,
-		.vsync_len	= 1,
-		.sync		= FB_SYNC_DATA_ENABLE_HIGH_ACT |
-				  FB_SYNC_DOTCLK_FAILING_ACT,
-	},
-};
-
-static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
-	.mode_list	= mx23evk_video_modes,
-	.mode_count	= ARRAY_SIZE(mx23evk_video_modes),
-	.default_bpp	= 32,
-	.ld_intf_width	= STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = {
-	.wp_gpio = MX23EVK_MMC0_WRITE_PROTECT,
-	.flags = SLOTF_8_BIT_CAPABLE,
-};
-
-static void __init mx23evk_init(void)
-{
-	int ret;
-
-	mx23_soc_init();
-
-	mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
-
-	mx23_add_duart();
-	mx23_add_auart0();
-
-	/* power on mmc slot by writing 0 to the gpio */
-	ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-			       "mmc0-slot-power");
-	if (ret)
-		pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-	mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata);
-
-	ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
-	if (ret)
-		pr_warn("failed to request gpio lcd-enable: %d\n", ret);
-	else
-		gpio_set_value(MX23EVK_LCD_ENABLE, 1);
-
-	ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
-	if (ret)
-		pr_warn("failed to request gpio bl-enable: %d\n", ret);
-	else
-		gpio_set_value(MX23EVK_BL_ENABLE, 1);
-
-	mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
-	mx23_add_rtc_stmp3xxx();
-}
-
-static void __init mx23evk_timer_init(void)
-{
-	mx23_clocks_init();
-}
-
-static struct sys_timer mx23evk_timer = {
-	.init	= mx23evk_timer_init,
-};
-
-MACHINE_START(MX23EVK, "Freescale MX23 EVK")
-	/* Maintainer: Freescale Semiconductor, Inc. */
-	.map_io		= mx23_map_io,
-	.init_irq	= mx23_init_irq,
-	.timer		= &mx23evk_timer,
-	.init_machine	= mx23evk_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
deleted file mode 100644
index dafd48e..0000000
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include <mach/digctl.h>
-
-#include "devices-mx28.h"
-
-#define MX28EVK_FLEXCAN_SWITCH	MXS_GPIO_NR(2, 13)
-#define MX28EVK_FEC_PHY_POWER	MXS_GPIO_NR(2, 15)
-#define MX28EVK_GPIO_LED	MXS_GPIO_NR(3, 5)
-#define MX28EVK_BL_ENABLE	MXS_GPIO_NR(3, 18)
-#define MX28EVK_LCD_ENABLE	MXS_GPIO_NR(3, 30)
-#define MX28EVK_FEC_PHY_RESET	MXS_GPIO_NR(4, 13)
-
-#define MX28EVK_MMC0_WRITE_PROTECT	MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT	MXS_GPIO_NR(0, 28)
-#define MX28EVK_MMC0_SLOT_POWER		MXS_GPIO_NR(3, 28)
-#define MX28EVK_MMC1_SLOT_POWER		MXS_GPIO_NR(3, 29)
-
-static const iomux_cfg_t mx28evk_pads[] __initconst = {
-	/* duart */
-	MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-	MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-	/* auart0 */
-	MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-	MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-	/* auart3 */
-	MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-	MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC	(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-	/* fec0 */
-	MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-	/* fec1 */
-	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-	/* phy power line */
-	MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
-	/* phy reset line */
-	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
-
-	/* flexcan0 */
-	MX28_PAD_GPMI_RDY2__CAN0_TX,
-	MX28_PAD_GPMI_RDY3__CAN0_RX,
-	/* flexcan1 */
-	MX28_PAD_GPMI_CE2N__CAN1_TX,
-	MX28_PAD_GPMI_CE3N__CAN1_RX,
-	/* transceiver power control */
-	MX28_PAD_SSP1_CMD__GPIO_2_13,
-
-	/* mxsfb (lcdif) */
-	MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-	MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
-	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
-	MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
-	MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
-	/* LCD panel enable */
-	MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
-	/* backlight control */
-	MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
-	/* mmc0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA1__SSP0_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA2__SSP0_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA3__SSP0_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA4__SSP0_D4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA5__SSP0_D5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA6__SSP0_D6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA7__SSP0_D7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_CMD__SSP0_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* write protect */
-	MX28_PAD_SSP1_SCK__GPIO_2_12 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* slot power enable */
-	MX28_PAD_PWM3__GPIO_3_28 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-	/* mmc1 */
-	MX28_PAD_GPMI_D00__SSP1_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D01__SSP1_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D02__SSP1_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D03__SSP1_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D04__SSP1_D4 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D05__SSP1_D5 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D06__SSP1_D6 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_D07__SSP1_D7 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_RDY1__SSP1_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_GPMI_WRN__SSP1_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* write protect */
-	MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	/* slot power enable */
-	MX28_PAD_PWM4__GPIO_3_29 |
-		(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-	/* led */
-	MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
-
-	/* I2C */
-	MX28_PAD_I2C0_SCL__I2C0_SCL |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_I2C0_SDA__I2C0_SDA |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-
-	/* saif0 & saif1 */
-	MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led mx28evk_leds[] __initconst = {
-	{
-		.name = "GPIO-LED",
-		.default_trigger = "heartbeat",
-		.gpio = MX28EVK_GPIO_LED,
-	},
-};
-
-static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
-	.leds = mx28evk_leds,
-	.num_leds = ARRAY_SIZE(mx28evk_leds),
-};
-
-/* fec */
-static void __init mx28evk_fec_reset(void)
-{
-	struct clk *clk;
-
-	/* Enable fec phy clock */
-	clk = clk_get_sys("enet_out", NULL);
-	if (!IS_ERR(clk))
-		clk_prepare_enable(clk);
-
-	gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
-	mdelay(1);
-	gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
-}
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-	{
-		/* fec0 */
-		.phy = PHY_INTERFACE_MODE_RMII,
-	}, {
-		/* fec1 */
-		.phy = PHY_INTERFACE_MODE_RMII,
-	},
-};
-
-static int __init mx28evk_fec_get_mac(void)
-{
-	int i;
-	u32 val;
-	const u32 *ocotp = mxs_get_ocotp();
-
-	if (!ocotp)
-		return -ETIMEDOUT;
-
-	/*
-	 * OCOTP only stores the last 4 octets for each mac address,
-	 * so hard-code Freescale OUI (00:04:9f) here.
-	 */
-	for (i = 0; i < 2; i++) {
-		val = ocotp[i];
-		mx28_fec_pdata[i].mac[0] = 0x00;
-		mx28_fec_pdata[i].mac[1] = 0x04;
-		mx28_fec_pdata[i].mac[2] = 0x9f;
-		mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-		mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-		mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-	}
-
-	return 0;
-}
-
-/*
- * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
- */
-static int flexcan0_en, flexcan1_en;
-
-static void mx28evk_flexcan_switch(void)
-{
-	if (flexcan0_en || flexcan1_en)
-		gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
-	else
-		gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
-}
-
-static void mx28evk_flexcan0_switch(int enable)
-{
-	flexcan0_en = enable;
-	mx28evk_flexcan_switch();
-}
-
-static void mx28evk_flexcan1_switch(int enable)
-{
-	flexcan1_en = enable;
-	mx28evk_flexcan_switch();
-}
-
-static const struct flexcan_platform_data
-		mx28evk_flexcan_pdata[] __initconst = {
-	{
-		.transceiver_switch = mx28evk_flexcan0_switch,
-	}, {
-		.transceiver_switch = mx28evk_flexcan1_switch,
-	}
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx28evk_video_modes[] = {
-	{
-		.name		= "Seiko-43WVF1G",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= 29851, /* picosecond (33.5 MHz) */
-		.left_margin	= 89,
-		.right_margin	= 164,
-		.upper_margin	= 23,
-		.lower_margin	= 10,
-		.hsync_len	= 10,
-		.vsync_len	= 10,
-		.sync		= FB_SYNC_DATA_ENABLE_HIGH_ACT |
-				  FB_SYNC_DOTCLK_FAILING_ACT,
-	},
-};
-
-static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
-	.mode_list	= mx28evk_video_modes,
-	.mode_count	= ARRAY_SIZE(mx28evk_video_modes),
-	.default_bpp	= 32,
-	.ld_intf_width	= STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
-	{
-		/* mmc0 */
-		.wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-		.flags = SLOTF_8_BIT_CAPABLE,
-	}, {
-		/* mmc1 */
-		.wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-		.flags = SLOTF_8_BIT_CAPABLE,
-	},
-};
-
-static struct i2c_board_info mxs_i2c0_board_info[] __initdata = {
-	{
-		I2C_BOARD_INFO("sgtl5000", 0x0a),
-	},
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = {
-	REGULATOR_SUPPLY("VDDA", "0-000a"),
-	REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data mx28evk_vdd_reg_init_data = {
-	.constraints	= {
-		.name	= "3V3",
-		.always_on = 1,
-	},
-	.consumer_supplies = mx28evk_audio_consumer_supplies,
-	.num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config mx28evk_vdd_pdata = {
-	.supply_name	= "board-3V3",
-	.microvolts	= 3300000,
-	.gpio		= -EINVAL,
-	.enabled_at_boot = 1,
-	.init_data	= &mx28evk_vdd_reg_init_data,
-};
-static struct platform_device mx28evk_voltage_regulator = {
-	.name		= "reg-fixed-voltage",
-	.id		= -1,
-	.num_resources	= 0,
-	.dev		= {
-		.platform_data	= &mx28evk_vdd_pdata,
-	},
-};
-static void __init mx28evk_add_regulators(void)
-{
-	platform_device_register(&mx28evk_voltage_regulator);
-}
-#else
-static void __init mx28evk_add_regulators(void) {}
-#endif
-
-static const struct gpio mx28evk_gpios[] __initconst = {
-	{ MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
-	{ MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
-	{ MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
-	{ MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
-	{ MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
-	{ MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
-	{ MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
-};
-
-static const struct mxs_saif_platform_data
-			mx28evk_mxs_saif_pdata[] __initconst = {
-	/* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-	{
-		.master_mode = 1,
-		.master_id = 0,
-	}, {
-		.master_mode = 0,
-		.master_id = 0,
-	},
-};
-
-static void __init mx28evk_init(void)
-{
-	int ret;
-
-	mx28_soc_init();
-
-	mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
-
-	mx28_add_duart();
-	mx28_add_auart0();
-	mx28_add_auart3();
-
-	if (mx28evk_fec_get_mac())
-		pr_warn("%s: failed on fec mac setup\n", __func__);
-
-	ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
-	if (ret)
-		pr_err("One or more GPIOs failed to be requested: %d\n", ret);
-
-	mx28evk_fec_reset();
-	mx28_add_fec(0, &mx28_fec_pdata[0]);
-	mx28_add_fec(1, &mx28_fec_pdata[1]);
-
-	mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-	mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-
-	mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-
-	mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-	mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
-	mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
-
-	mx28_add_mxs_i2c(0);
-	i2c_register_board_info(0, mxs_i2c0_board_info,
-				ARRAY_SIZE(mxs_i2c0_board_info));
-
-	mx28evk_add_regulators();
-
-	mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
-			NULL, 0);
-
-	mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-	mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
-
-	mx28_add_rtc_stmp3xxx();
-
-	gpio_led_register_device(0, &mx28evk_led_data);
-}
-
-static void __init mx28evk_timer_init(void)
-{
-	mx28_clocks_init();
-}
-
-static struct sys_timer mx28evk_timer = {
-	.init	= mx28evk_timer_init,
-};
-
-MACHINE_START(MX28EVK, "Freescale MX28 EVK")
-	/* Maintainer: Freescale Semiconductor, Inc. */
-	.map_io		= mx28_map_io,
-	.init_irq	= mx28_init_irq,
-	.timer		= &mx28evk_timer,
-	.init_machine	= mx28evk_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
deleted file mode 100644
index 6548965..0000000
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * board setup for STMP378x-Development-Board
- *
- * based on mx23evk board setup and information gained form the original
- * plat-stmp based board setup, now converted to mach-mxs.
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define STMP378X_DEVB_MMC0_WRITE_PROTECT	MXS_GPIO_NR(1, 30)
-#define STMP378X_DEVB_MMC0_SLOT_POWER		MXS_GPIO_NR(1, 29)
-
-#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
-
-static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
-	/* duart (extended setup missing in old boardcode, too */
-	MX23_PAD_PWM0__DUART_RX,
-	MX23_PAD_PWM1__DUART_TX,
-
-	/* auart */
-	MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
-	MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
-	MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
-	MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
-
-	/* mmc */
-	MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_CMD__SSP1_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX23_PAD_SSP1_SCK__SSP1_SCK |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
-	MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
-};
-
-static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
-	.wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
-	{
-		.modalias       = "enc28j60",
-		.max_speed_hz   = 6 * 1000 * 1000,
-		.bus_num	= 1,
-		.chip_select    = 0,
-		.platform_data  = NULL,
-	},
-#endif
-};
-
-static void __init stmp378x_dvb_init(void)
-{
-	int ret;
-
-	mx23_soc_init();
-
-	mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
-			ARRAY_SIZE(stmp378x_dvb_pads));
-
-	mx23_add_duart();
-	mx23_add_auart0();
-	mx23_add_rtc_stmp3xxx();
-
-	/* power on mmc slot */
-	ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
-		GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
-	if (ret)
-		pr_warn("could not power mmc (%d)\n", ret);
-
-	mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
-
-	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-
-static void __init stmp378x_dvb_timer_init(void)
-{
-	mx23_clocks_init();
-}
-
-static struct sys_timer stmp378x_dvb_timer = {
-	.init	= stmp378x_dvb_timer_init,
-};
-
-MACHINE_START(STMP378X, "STMP378X")
-	.map_io		= mx23_map_io,
-	.init_irq	= mx23_init_irq,
-	.timer		= &stmp378x_dvb_timer,
-	.init_machine	= stmp378x_dvb_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
deleted file mode 100644
index 8837029..0000000
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (C) 2010 <LW at KARO-electronics.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/i2c.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-#include "module-tx28.h"
-
-#define TX28_STK5_GPIO_LED		MXS_GPIO_NR(4, 10)
-
-static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
-	/* LED */
-	MX28_PAD_ENET0_RXD3__GPIO_4_10 |
-		MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
-
-	/* framebuffer */
-#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
-	MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
-	MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
-	MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
-	MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
-	MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
-	MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
-	MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
-	MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
-	MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
-	MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
-	MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
-	MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
-	MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
-	MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
-	MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
-	MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
-	MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
-	MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
-	MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
-	MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
-	MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
-	MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
-	MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
-	MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
-	MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
-	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
-	MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
-	MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
-	MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
-	MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
-	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
-	MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
-	MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
-	MX28_PAD_PWM0__PWM_0 | LCD_MODE,
-
-	/* UART1 */
-	MX28_PAD_AUART0_CTS__DUART_RX,
-	MX28_PAD_AUART0_RTS__DUART_TX,
-	MX28_PAD_AUART0_TX__DUART_RTS,
-	MX28_PAD_AUART0_RX__DUART_CTS,
-
-	/* UART2 */
-	MX28_PAD_AUART1_RX__AUART1_RX,
-	MX28_PAD_AUART1_TX__AUART1_TX,
-	MX28_PAD_AUART1_RTS__AUART1_RTS,
-	MX28_PAD_AUART1_CTS__AUART1_CTS,
-
-	/* CAN */
-	MX28_PAD_GPMI_RDY2__CAN0_TX,
-	MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-	/* I2C */
-	MX28_PAD_I2C0_SCL__I2C0_SCL,
-	MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-	/* TSC2007 */
-	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
-
-	/* MMC0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA1__SSP0_D1 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA2__SSP0_D2 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DATA3__SSP0_D3 |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_CMD__SSP0_CMD |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-static const struct gpio_led tx28_stk5v3_leds[] __initconst = {
-	{
-		.name = "GPIO-LED",
-		.default_trigger = "heartbeat",
-		.gpio = TX28_STK5_GPIO_LED,
-	},
-};
-
-static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
-	.leds = tx28_stk5v3_leds,
-	.num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
-};
-
-static struct spi_board_info tx28_spi_board_info[] = {
-	{
-		.modalias = "spidev",
-		.max_speed_hz = 20000000,
-		.bus_num = 0,
-		.chip_select = 1,
-		.controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
-		.mode = SPI_MODE_0,
-	},
-};
-
-static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
-	{
-		I2C_BOARD_INFO("ds1339", 0x68),
-	},
-};
-
-static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
-       .wp_gpio = -EINVAL,
-       .flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static void __init tx28_stk5v3_init(void)
-{
-	mx28_soc_init();
-
-	mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
-			ARRAY_SIZE(tx28_stk5v3_pads));
-
-	mx28_add_duart(); /* UART1 */
-	mx28_add_auart(1); /* UART2 */
-
-	tx28_add_fec0();
-	/* spi via ssp will be added when available */
-	spi_register_board_info(tx28_spi_board_info,
-			ARRAY_SIZE(tx28_spi_board_info));
-	gpio_led_register_device(0, &tx28_stk5v3_led_data);
-	mx28_add_mxs_i2c(0);
-	i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
-			ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
-	mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
-	mx28_add_rtc_stmp3xxx();
-}
-
-static void __init tx28_timer_init(void)
-{
-	mx28_clocks_init();
-}
-
-static struct sys_timer tx28_timer = {
-	.init = tx28_timer_init,
-};
-
-MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
-	.map_io = mx28_map_io,
-	.init_irq = mx28_init_irq,
-	.timer = &tx28_timer,
-	.init_machine = tx28_stk5v3_init,
-	.restart	= mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
deleted file mode 100644
index 0f71f82..0000000
--- a/arch/arm/mach-mxs/module-tx28.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (C) 2010 <LW at KARO-electronics.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/fec.h>
-#include <linux/gpio.h>
-
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-
-#include "module-tx28.h"
-
-#define TX28_FEC_PHY_POWER	MXS_GPIO_NR(3, 29)
-#define TX28_FEC_PHY_RESET	MXS_GPIO_NR(4, 13)
-
-static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
-	/* PHY POWER */
-	MX28_PAD_PWM4__GPIO_3_29 |
-		MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-	/* PHY RESET */
-	MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
-		MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-	/* Mode strap pins 0-2 */
-	MX28_PAD_ENET0_RXD0__GPIO_4_3 |
-		MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-	MX28_PAD_ENET0_RXD1__GPIO_4_4 |
-		MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-	MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
-		MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-	/* nINT */
-	MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
-		MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-
-	MX28_PAD_ENET0_MDC__GPIO_4_0,
-	MX28_PAD_ENET0_MDIO__GPIO_4_1,
-	MX28_PAD_ENET0_TX_EN__GPIO_4_6,
-	MX28_PAD_ENET0_TXD0__GPIO_4_7,
-	MX28_PAD_ENET0_TXD1__GPIO_4_8,
-	MX28_PAD_ENET_CLK__GPIO_4_16,
-};
-
-#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
-static const iomux_cfg_t tx28_fec0_pads[] __initconst = {
-	MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
-};
-
-static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
-	MX28_PAD_ENET0_RXD2__ENET1_RXD0,
-	MX28_PAD_ENET0_RXD3__ENET1_RXD1,
-	MX28_PAD_ENET0_TXD2__ENET1_TXD0,
-	MX28_PAD_ENET0_TXD3__ENET1_TXD1,
-	MX28_PAD_ENET0_COL__ENET1_TX_EN,
-	MX28_PAD_ENET0_CRS__ENET1_RX_EN,
-};
-
-static const struct fec_platform_data tx28_fec0_data __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct fec_platform_data tx28_fec1_data __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-int __init tx28_add_fec0(void)
-{
-	int i, ret;
-
-	pr_debug("%s: Switching FEC PHY power off\n", __func__);
-	ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
-			ARRAY_SIZE(tx28_fec_gpio_pads));
-	for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
-		unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-			PAD_PIN(tx28_fec_gpio_pads[i]));
-
-		ret = gpio_request(gpio, "FEC");
-		if (ret) {
-			pr_err("Failed to request GPIO_%d_%d: %d\n",
-				PAD_BANK(tx28_fec_gpio_pads[i]),
-				PAD_PIN(tx28_fec_gpio_pads[i]), ret);
-			goto free_gpios;
-		}
-		ret = gpio_direction_output(gpio, 0);
-		if (ret) {
-			pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
-					gpio / 32 + 1, gpio % 32, ret);
-			goto free_gpios;
-		}
-	}
-
-	/* Power up fec phy */
-	pr_debug("%s: Switching FEC PHY power on\n", __func__);
-	ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
-	if (ret) {
-		pr_err("Failed to power on PHY: %d\n", ret);
-		goto free_gpios;
-	}
-	mdelay(26); /* 25ms according to data sheet */
-
-	/* nINT */
-	gpio_direction_input(MXS_GPIO_NR(4, 5));
-	/* Mode strap pins */
-	gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
-	gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
-	gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
-
-	udelay(100); /* minimum assertion time for nRST */
-
-	pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
-	gpio_set_value(TX28_FEC_PHY_RESET, 1);
-
-	ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads,
-			ARRAY_SIZE(tx28_fec0_pads));
-	if (ret) {
-		pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-				__func__, ret);
-		goto free_gpios;
-	}
-	pr_debug("%s: Registering FEC0 device\n", __func__);
-	mx28_add_fec(0, &tx28_fec0_data);
-	return 0;
-
-free_gpios:
-	while (--i >= 0) {
-		unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-			PAD_PIN(tx28_fec_gpio_pads[i]));
-
-		gpio_free(gpio);
-	}
-
-	return ret;
-}
-
-int __init tx28_add_fec1(void)
-{
-	int ret;
-
-	ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads,
-			ARRAY_SIZE(tx28_fec1_pads));
-	if (ret) {
-		pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-				__func__, ret);
-		return ret;
-	}
-	pr_debug("%s: Registering FEC1 device\n", __func__);
-	mx28_add_fec(1, &tx28_fec1_data);
-	return 0;
-}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
deleted file mode 100644
index 8ed4254..0000000
--- a/arch/arm/mach-mxs/module-tx28.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- *   Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-int __init tx28_add_fec0(void);
-int __init tx28_add_fec1(void);
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug  6 11:42:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 6 Aug 2012 23:42:49 +0800
Subject: [PATCH 6/6] ARM: mxs: remove iomux driver
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344267769-31166-7-git-send-email-shawn.guo@linaro.org>

With all board files removed, there is no user of iomux driver.
Remove it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-mxs/Makefile                  |    2 +-
 arch/arm/mach-mxs/include/mach/iomux-mx23.h |  355 ------------------
 arch/arm/mach-mxs/include/mach/iomux-mx28.h |  537 ---------------------------
 arch/arm/mach-mxs/include/mach/iomux.h      |  168 ---------
 arch/arm/mach-mxs/iomux.c                   |  101 -----
 5 files changed, 1 insertions(+), 1162 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx23.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx28.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux.h
 delete mode 100644 arch/arm/mach-mxs/iomux.c

diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 2480ce9..3d3c8a9 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,5 +1,5 @@
 # Common support
-obj-y := icoll.o iomux.o ocotp.o system.o timer.o mm.o
+obj-y := icoll.o ocotp.o system.o timer.o mm.o
 
 obj-$(CONFIG_PM) += pm.o
 
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
deleted file mode 100644
index b0190a4..0000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria at canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX23_H__
-#define __MACH_IOMUX_MX23_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *									BANK	PIN	MUX
- */
-/* MUXSEL_0 */
-#define MX23_PAD_GPMI_D00__GPMI_D00		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D01__GPMI_D01		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D02__GPMI_D02		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D03__GPMI_D03		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D04__GPMI_D04		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D05__GPMI_D05		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D06__GPMI_D06		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D07__GPMI_D07		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D08__GPMI_D08		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D09__GPMI_D09		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D10__GPMI_D10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D11__GPMI_D11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D12__GPMI_D12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D13__GPMI_D13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D14__GPMI_D14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D15__GPMI_D15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CLE__GPMI_CLE		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_ALE__GPMI_ALE		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE2N__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY0__GPMI_RDY0		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY1__GPMI_RDY1		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY2__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY3__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WPN__GPMI_WPN		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WRN__GPMI_WRN		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDN__GPMI_RDN		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_CTS__AUART1_CTS		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RTS__AUART1_RTS		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RX__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_TX__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SCL__I2C_SCL		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SDA__I2C_SDA		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_LCD_D00__LCD_D00		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D01__LCD_D01		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D02__LCD_D02		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D03__LCD_D03		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D04__LCD_D04		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D05__LCD_D05		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D06__LCD_D06		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D07__LCD_D07		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D08__LCD_D08		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D09__LCD_D09		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D10__LCD_D10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D11__LCD_D11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D12__LCD_D12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D13__LCD_D13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D14__LCD_D14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D15__LCD_D15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D16__LCD_D16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D17__LCD_D17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RESET__LCD_RESET		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RS__LCD_RS			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_WR__LCD_WR			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_CS__LCD_CS			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_DOTCK__LCD_DOTCK		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_ENABLE__LCD_ENABLE		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_HSYNC__LCD_HSYNC		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_VSYNC__LCD_VSYNC		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX23_PAD_PWM0__PWM0			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX23_PAD_PWM1__PWM1			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX23_PAD_PWM2__PWM2			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX23_PAD_PWM3__PWM3			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX23_PAD_PWM4__PWM4			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-
-#define MX23_PAD_SSP1_CMD__SSP1_CMD		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DETECT__SSP1_DETECT	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA0__SSP1_DATA0		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA1__SSP1_DATA1		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA2__SSP1_DATA2		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA3__SSP1_DATA3		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_SCK__SSP1_SCK		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYA__ROTARYA		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYB__ROTARYB		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A00__EMI_A00		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A01__EMI_A01		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A02__EMI_A02		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A03__EMI_A03		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A04__EMI_A04		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A05__EMI_A05		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A06__EMI_A06		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A07__EMI_A07		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A08__EMI_A08		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A09__EMI_A09		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A10__EMI_A10		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A11__EMI_A11		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A12__EMI_A12		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA0__EMI_BA0		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA1__EMI_BA1		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CASN__EMI_CASN		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE0N__EMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE1N__EMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE1N__GPMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE0N__GPMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CKE__EMI_CKE		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_RASN__EMI_RASN		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_WEN__EMI_WEN		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_EMI_D00__EMI_D00		MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D01__EMI_D01		MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D02__EMI_D02		MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D03__EMI_D03		MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D04__EMI_D04		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D05__EMI_D05		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D06__EMI_D06		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D07__EMI_D07		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D08__EMI_D08		MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D09__EMI_D09		MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D10__EMI_D10		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D11__EMI_D11		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D12__EMI_D12		MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D13__EMI_D13		MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D14__EMI_D14		MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D15__EMI_D15		MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM0__EMI_DQM0		MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM1__EMI_DQM1		MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS0__EMI_DQS0		MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS1__EMI_DQS1		MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLK__EMI_CLK		MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLKN__EMI_CLKN		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX23_PAD_GPMI_D00__LCD_D8		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D01__LCD_D9		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D02__LCD_D10		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D03__LCD_D11		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D04__LCD_D12		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D05__LCD_D13		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D06__LCD_D14		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D07__LCD_D15		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D08__LCD_D18		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D09__LCD_D19		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D10__LCD_D20		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D11__LCD_D21		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D12__LCD_D22		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D13__LCD_D23		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D14__AUART2_RX		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D15__AUART2_TX		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CLE__LCD_D16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_ALE__LCD_D17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CE2N__ATA_A2		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RTS__IR_CLK		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RX__IR_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_TX__IR_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SCL__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SDA__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
-
-#define MX23_PAD_LCD_D00__ETM_DA8		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D01__ETM_DA9		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D02__ETM_DA10		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D03__ETM_DA11		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D04__ETM_DA12		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D05__ETM_DA13		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D06__ETM_DA14		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D07__ETM_DA15		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D08__ETM_DA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D09__ETM_DA1		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D10__ETM_DA2		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D11__ETM_DA3		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D12__ETM_DA4		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D13__ETM_DA5		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D14__ETM_DA6		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D15__ETM_DA7		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RESET__ETM_TCTL		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RS__ETM_TCLK		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_DOTCK__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_ENABLE__I2C_SCL		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_HSYNC__I2C_SDA		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_VSYNC__LCD_BUSY		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX23_PAD_PWM0__ROTARYA			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX23_PAD_PWM1__ROTARYB			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX23_PAD_PWM2__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX23_PAD_PWM3__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX23_PAD_PWM4__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA1__I2C_SCL		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA2__I2C_SDA		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYA__AUART2_RTS		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYB__AUART2_CTS		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX23_PAD_GPMI_D00__SSP2_DATA0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D01__SSP2_DATA1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D02__SSP2_DATA2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D03__SSP2_DATA3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D04__SSP2_DATA4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D05__SSP2_DATA5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D06__SSP2_DATA6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D07__SSP2_DATA7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D08__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D09__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D10__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D11__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D15__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY0__SSP2_DETECT		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY1__SSP2_CMD		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_WRN__SSP2_SCK		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_CTS__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RTS__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RX__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_TX__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SCL__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SDA__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
-
-#define MX23_PAD_LCD_D08__SAIF2_SDATA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D09__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK	MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D11__SAIF_LRCLK		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D12__SAIF2_SDATA1		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D13__SAIF2_SDATA2		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D14__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D15__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK	MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_RESET__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX23_PAD_PWM0__DUART_RX			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
-#define MX23_PAD_PWM1__DUART_TX			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
-#define MX23_PAD_PWM3__AUART1_CTS		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX23_PAD_PWM4__AUART1_RTS		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX23_PAD_SSP1_CMD__JTAG_TDO		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DETECT__USB_OTG_ID	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA0__JTAG_TDI		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA1__JTAG_TCLK		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA2__JTAG_RTCK		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA3__JTAG_TMS		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_SCK__JTAG_TRST		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYA__SPDIF			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYB__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPIO_0_0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPIO_0_1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPIO_0_2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPIO_0_3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPIO_0_4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPIO_0_5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPIO_0_6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPIO_0_7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPIO_0_8		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPIO_0_9		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPIO_0_10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPIO_0_11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPIO_0_12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPIO_0_13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPIO_0_14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPIO_0_15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPIO_0_16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPIO_0_17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPIO_0_18		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPIO_0_19		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPIO_0_20		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPIO_0_21		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPIO_0_22		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPIO_0_23		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPIO_0_24		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPIO_0_25		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPIO_0_26		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPIO_0_27		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPIO_0_28		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPIO_0_29		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPIO_0_30		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPIO_0_31		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_LCD_D00__GPIO_1_0		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPIO_1_1		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPIO_1_2		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPIO_1_3		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPIO_1_4		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPIO_1_5		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPIO_1_6		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPIO_1_7		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPIO_1_8		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPIO_1_9		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPIO_1_10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPIO_1_11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPIO_1_12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPIO_1_13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPIO_1_14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPIO_1_15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPIO_1_16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPIO_1_17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPIO_1_18		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPIO_1_19		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPIO_1_20		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPIO_1_21		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPIO_1_22		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPIO_1_23		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPIO_1_24		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPIO_1_25		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPIO_1_26		MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPIO_1_27		MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPIO_1_28		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPIO_1_29		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPIO_1_30		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_SSP1_CMD__GPIO_2_0		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPIO_2_1		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPIO_2_2		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPIO_2_3		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPIO_2_4		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPIO_2_5		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPIO_2_6		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPIO_2_7		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPIO_2_8		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPIO_2_9		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPIO_2_10		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPIO_2_11		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPIO_2_12		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPIO_2_13		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPIO_2_14		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPIO_2_15		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPIO_2_16		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPIO_2_17		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPIO_2_18		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPIO_2_19		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPIO_2_20		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPIO_2_21		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPIO_2_22		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPIO_2_23		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPIO_2_24		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPIO_2_25		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPIO_2_26		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPIO_2_27		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPIO_2_28		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPIO_2_29		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPIO_2_30		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPIO_2_31		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
deleted file mode 100644
index f50fefd..0000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria at canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX28_H__
-#define __MACH_IOMUX_MX28_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *									BANK	PIN	MUX
- */
-/* MUXSEL_0 */
-#define MX28_PAD_GPMI_D00__GPMI_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D01__GPMI_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D02__GPMI_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D03__GPMI_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D04__GPMI_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D05__GPMI_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D06__GPMI_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D07__GPMI_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE0N__GPMI_CE0N			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE1N__GPMI_CE1N			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE2N__GPMI_CE2N			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE3N__GPMI_CE3N			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY0__GPMI_READY0			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY1__GPMI_READY1			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY2__GPMI_READY2			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY3__GPMI_READY3			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDN__GPMI_RDN			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_WRN__GPMI_WRN			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_ALE__GPMI_ALE			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CLE__GPMI_CLE			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RESETN__GPMI_RESETN		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-
-#define MX28_PAD_LCD_D00__LCD_D0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D01__LCD_D1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D02__LCD_D2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D03__LCD_D3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D04__LCD_D4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D05__LCD_D5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D06__LCD_D6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D07__LCD_D7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D08__LCD_D8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D09__LCD_D9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D10__LCD_D10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D11__LCD_D11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D12__LCD_D12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D13__LCD_D13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D14__LCD_D14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D15__LCD_D15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D16__LCD_D16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D17__LCD_D17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D18__LCD_D18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D19__LCD_D19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D20__LCD_D20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D21__LCD_D21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D22__LCD_D22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D23__LCD_D23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RD_E__LCD_RD_E			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RS__LCD_RS				MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_CS__LCD_CS				MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_VSYNC__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_HSYNC__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_ENABLE__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
-
-#define MX28_PAD_SSP0_DATA0__SSP0_D0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA1__SSP0_D1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA2__SSP0_D2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA3__SSP0_D3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA4__SSP0_D4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA5__SSP0_D5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA6__SSP0_D6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA7__SSP0_D7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_CMD__SSP0_CMD			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_SCK__SSP0_SCK			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_SCK__SSP1_SCK			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_CMD__SSP1_CMD			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA0__SSP1_D0			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA3__SSP1_D3			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SCK__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MOSI__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MISO__SSP2_D0			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS0__SSP2_D3			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS1__SSP2_D4			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS2__SSP2_D5			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SCK__SSP3_SCK			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MOSI__SSP3_CMD			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MISO__SSP3_D0			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SS0__SSP3_D3			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-
-#define MX28_PAD_AUART0_RX__AUART0_RX			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_TX__AUART0_TX			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_CTS__AUART0_CTS			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_RTS__AUART0_RTS			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RX__AUART1_RX			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_TX__AUART1_TX			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_CTS__AUART1_CTS			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RTS__AUART1_RTS			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RX__AUART2_RX			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_TX__AUART2_TX			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_CTS__AUART2_CTS			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RTS__AUART2_RTS			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RX__AUART3_RX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_TX__AUART3_TX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_CTS__AUART3_CTS			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RTS__AUART3_RTS			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX28_PAD_PWM0__PWM_0				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX28_PAD_PWM1__PWM_1				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX28_PAD_PWM2__PWM_2				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SCL__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SDA__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SPDIF__SPDIF_TX			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
-#define MX28_PAD_PWM3__PWM_3				MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
-#define MX28_PAD_PWM4__PWM_4				MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RESET__LCD_RESET			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
-
-#define MX28_PAD_ENET0_MDC__ENET0_MDC			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_MDIO__ENET0_MDIO			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD0__ENET0_RXD0			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD1__ENET0_RXD1			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD0__ENET0_TXD0			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD1__ENET0_TXD1			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD2__ENET0_RXD2			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD3__ENET0_RXD3			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD2__ENET0_TXD2			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD3__ENET0_TXD3			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_COL__ENET0_COL			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_CRS__ENET0_CRS			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
-#define MX28_PAD_ENET_CLK__CLKCTRL_ENET			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
-#define MX28_PAD_JTAG_RTCK__JTAG_RTCK			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_D00__EMI_DATA0			MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D01__EMI_DATA1			MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D02__EMI_DATA2			MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D03__EMI_DATA3			MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D04__EMI_DATA4			MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D05__EMI_DATA5			MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D06__EMI_DATA6			MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D07__EMI_DATA7			MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D08__EMI_DATA8			MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D09__EMI_DATA9			MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D10__EMI_DATA10			MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D11__EMI_DATA11			MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D12__EMI_DATA12			MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D13__EMI_DATA13			MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D14__EMI_DATA14			MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D15__EMI_DATA15			MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT0__EMI_ODT0			MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM0__EMI_DQM0			MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT1__EMI_ODT1			MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM1__EMI_DQM1			MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK	MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CLK__EMI_CLK			MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS0__EMI_DQS0			MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS1__EMI_DQS1			MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN		MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_A00__EMI_ADDR0			MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A01__EMI_ADDR1			MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A02__EMI_ADDR2			MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A03__EMI_ADDR3			MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A04__EMI_ADDR4			MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A05__EMI_ADDR5			MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A06__EMI_ADDR6			MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A07__EMI_ADDR7			MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A08__EMI_ADDR8			MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A09__EMI_ADDR9			MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A10__EMI_ADDR10			MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A11__EMI_ADDR11			MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A12__EMI_ADDR12			MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A13__EMI_ADDR13			MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A14__EMI_ADDR14			MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA0__EMI_BA0			MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA1__EMI_BA1			MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA2__EMI_BA2			MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CASN__EMI_CASN			MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_RASN__EMI_RASN			MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_WEN__EMI_WEN			MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE0N__EMI_CE0N			MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE1N__EMI_CE1N			MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CKE__EMI_CKE			MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX28_PAD_GPMI_D00__SSP1_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D01__SSP1_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D02__SSP1_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D03__SSP1_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D04__SSP1_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D05__SSP1_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D06__SSP1_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D07__SSP1_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE0N__SSP3_D0			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE1N__SSP3_D3			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE2N__CAN1_TX			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE3N__CAN1_RX			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY1__SSP1_CMD			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY2__CAN0_TX			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY3__CAN0_RX			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDN__SSP3_SCK			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_WRN__SSP1_SCK			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_ALE__SSP3_D1			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CLE__SSP3_D2			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RESETN__SSP3_CMD			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-
-#define MX28_PAD_LCD_D03__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D04__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D08__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D09__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RD_E__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RS__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_CS__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_SSP0_DATA4__SSP2_D0			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA5__SSP2_D3			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA6__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA7__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_SCK__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_CMD__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA0__SSP2_D6			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA3__SSP2_D7			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SCK__AUART2_RX			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MOSI__AUART2_TX			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MISO__AUART3_RX			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS0__AUART3_TX			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS1__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS2__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SCK__AUART4_TX			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MOSI__AUART4_RX			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MISO__AUART4_RTS			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SS0__AUART4_CTS			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
-
-#define MX28_PAD_AUART0_RX__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_TX__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_CTS__AUART4_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_RTS__AUART4_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RTS__USB0_ID			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RX__SSP3_D1			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_TX__SSP3_D2			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_CTS__I2C1_SCL			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RTS__I2C1_SDA			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RX__CAN0_TX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_TX__CAN0_RX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_CTS__CAN1_TX			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RTS__CAN1_RX			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
-#define MX28_PAD_PWM0__I2C1_SCL				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
-#define MX28_PAD_PWM1__I2C1_SDA				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
-#define MX28_PAD_PWM2__USB0_ID				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_MCLK__PWM_3			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_LRCLK__PWM_4			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_BITCLK__PWM_5			MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_SDATA0__PWM_6			MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF1_SDATA0__PWM_7			MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RESET__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_ENET0_MDC__GPMI_CE4N			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_MDIO__GPMI_CE5N			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD0__GPMI_CE7N			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD1__GPMI_READY4		MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_EN__GPMI_READY5		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD0__GPMI_READY6		MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD1__GPMI_READY7		MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD2__ENET1_RXD0			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD3__ENET1_RXD1			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD2__ENET1_TXD0			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD3__ENET1_TXD1			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_COL__ENET1_TX_EN			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_CRS__ENET1_RX_EN			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY0__USB0_ID			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_ALE__SSP3_D4			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CLE__SSP3_D5			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_LCD_D00__ETM_DA0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D01__ETM_DA1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D02__ETM_DA2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D03__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D04__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D05__ETM_DA5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D06__ETM_DA6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D07__ETM_DA7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D08__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D09__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D10__ETM_DA10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D11__ETM_DA11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D12__ETM_DA12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D13__ETM_DA13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D14__ETM_DA14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D15__ETM_DA15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D16__ETM_DA7			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D17__ETM_DA6			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D18__ETM_DA5			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D19__ETM_DA4			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D20__ETM_DA3			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D21__ETM_DA2			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D22__ETM_DA1			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D23__ETM_DA0			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_RD_E__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_WR_RWN__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_HSYNC__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_DOTCLK__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_AUART0_RX__DUART_CTS			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_TX__DUART_RTS			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_CTS__DUART_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_RTS__DUART_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RX__PWM_0			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_TX__PWM_1			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RX__SSP3_D4			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_TX__SSP3_D5			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
-#define MX28_PAD_PWM0__DUART_RX				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
-#define MX28_PAD_PWM1__DUART_TX				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
-#define MX28_PAD_PWM2__USB1_OVERCURRENT			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_MCLK__AUART4_CTS			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_BITCLK__AUART4_RX		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_SDATA0__AUART4_TX		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SCL__DUART_RX			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SDA__DUART_TX			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SPDIF__ENET1_RX_ER			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN	MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX28_PAD_GPMI_D00__GPIO_0_0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D01__GPIO_0_1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D02__GPIO_0_2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D03__GPIO_0_3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D04__GPIO_0_4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D05__GPIO_0_5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D06__GPIO_0_6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D07__GPIO_0_7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE0N__GPIO_0_16			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE1N__GPIO_0_17			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE2N__GPIO_0_18			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE3N__GPIO_0_19			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY0__GPIO_0_20			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY1__GPIO_0_21			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY2__GPIO_0_22			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY3__GPIO_0_23			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDN__GPIO_0_24			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_WRN__GPIO_0_25			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_ALE__GPIO_0_26			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CLE__GPIO_0_27			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RESETN__GPIO_0_28			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_LCD_D00__GPIO_1_0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D01__GPIO_1_1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D02__GPIO_1_2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D03__GPIO_1_3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D04__GPIO_1_4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D05__GPIO_1_5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D06__GPIO_1_6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D07__GPIO_1_7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D08__GPIO_1_8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D09__GPIO_1_9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D10__GPIO_1_10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D11__GPIO_1_11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D12__GPIO_1_12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D13__GPIO_1_13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D14__GPIO_1_14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D15__GPIO_1_15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D16__GPIO_1_16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D17__GPIO_1_17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D18__GPIO_1_18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D19__GPIO_1_19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D20__GPIO_1_20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D21__GPIO_1_21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D22__GPIO_1_22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D23__GPIO_1_23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RD_E__GPIO_1_24			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_WR_RWN__GPIO_1_25			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RS__GPIO_1_26			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_CS__GPIO_1_27			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_VSYNC__GPIO_1_28			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_HSYNC__GPIO_1_29			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_DOTCLK__GPIO_1_30			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_ENABLE__GPIO_1_31			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_SSP0_DATA0__GPIO_2_0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA1__GPIO_2_1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA2__GPIO_2_2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA3__GPIO_2_3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA4__GPIO_2_4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA5__GPIO_2_5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA6__GPIO_2_6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA7__GPIO_2_7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_CMD__GPIO_2_8			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DETECT__GPIO_2_9			MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_SCK__GPIO_2_10			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_SCK__GPIO_2_12			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_CMD__GPIO_2_13			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA0__GPIO_2_14			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA3__GPIO_2_15			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SCK__GPIO_2_16			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MOSI__GPIO_2_17			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MISO__GPIO_2_18			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS0__GPIO_2_19			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS1__GPIO_2_20			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS2__GPIO_2_21			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SCK__GPIO_2_24			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MOSI__GPIO_2_25			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MISO__GPIO_2_26			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SS0__GPIO_2_27			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_AUART0_RX__GPIO_3_0			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_TX__GPIO_3_1			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_CTS__GPIO_3_2			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_RTS__GPIO_3_3			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RX__GPIO_3_4			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_TX__GPIO_3_5			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_CTS__GPIO_3_6			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RTS__GPIO_3_7			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RX__GPIO_3_8			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_TX__GPIO_3_9			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_CTS__GPIO_3_10			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RTS__GPIO_3_11			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RX__GPIO_3_12			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_TX__GPIO_3_13			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_CTS__GPIO_3_14			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RTS__GPIO_3_15			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM0__GPIO_3_16			MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM1__GPIO_3_17			MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM2__GPIO_3_18			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_MCLK__GPIO_3_20			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SCL__GPIO_3_24			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SDA__GPIO_3_25			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SPDIF__GPIO_3_27			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM3__GPIO_3_28			MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM4__GPIO_3_29			MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RESET__GPIO_3_30			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_ENET0_MDC__GPIO_4_0			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_MDIO__GPIO_4_1			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_EN__GPIO_4_2			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD0__GPIO_4_3			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD1__GPIO_4_4			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5			MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_EN__GPIO_4_6			MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD0__GPIO_4_7			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD1__GPIO_4_8			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD2__GPIO_4_9			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD3__GPIO_4_10			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD2__GPIO_4_11			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD3__GPIO_4_12			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_COL__GPIO_4_14			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_CRS__GPIO_4_15			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET_CLK__GPIO_4_16			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_JTAG_RTCK__GPIO_4_20			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
deleted file mode 100644
index 7abdf58..0000000
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *			<armlinux at phytec.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_IOMUX_H__
-#define __MACH_MXS_IOMUX_H__
-
-/*
- * IOMUX/PAD Bit field definitions
- *
- * PAD_BANK:		 0..2	(3)
- * PAD_PIN:		 3..7	(5)
- * PAD_MUXSEL:		 8..9	(2)
- * PAD_MA:		10..11	(2)
- * PAD_MA_VALID:	12	(1)
- * PAD_VOL:		13	(1)
- * PAD_VOL_VALID:	14	(1)
- * PAD_PULL:		15	(1)
- * PAD_PULL_VALID:	16	(1)
- * RESERVED:		17..31	(15)
- */
-typedef u32 iomux_cfg_t;
-
-#define MXS_PAD_BANK_SHIFT	0
-#define MXS_PAD_BANK_MASK	((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT	3
-#define MXS_PAD_PIN_MASK	((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT	8
-#define MXS_PAD_MUXSEL_MASK	((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT	10
-#define MXS_PAD_MA_MASK		((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT	12
-#define MXS_PAD_MA_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT	13
-#define MXS_PAD_VOL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT	14
-#define MXS_PAD_VOL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT	15
-#define MXS_PAD_PULL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
-#define MXS_PAD_PULL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
-
-#define PAD_MUXSEL_0		0
-#define PAD_MUXSEL_1		1
-#define PAD_MUXSEL_2		2
-#define PAD_MUXSEL_GPIO		3
-
-#define PAD_4MA			0
-#define PAD_8MA			1
-#define PAD_12MA		2
-#define PAD_16MA		3
-
-#define PAD_1V8			0
-#define PAD_3V3			1
-
-#define PAD_NOPULL		0
-#define PAD_PULLUP		1
-
-#define MXS_PAD_4MA	((PAD_4MA << MXS_PAD_MA_SHIFT) | \
-					MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_8MA	((PAD_8MA << MXS_PAD_MA_SHIFT) | \
-					MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_12MA	((PAD_12MA << MXS_PAD_MA_SHIFT) | \
-					MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_16MA	((PAD_16MA << MXS_PAD_MA_SHIFT) | \
-					MXS_PAD_MA_VALID_MASK)
-
-#define MXS_PAD_1V8	((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
-					MXS_PAD_VOL_VALID_MASK)
-#define MXS_PAD_3V3	((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
-					MXS_PAD_VOL_VALID_MASK)
-
-#define MXS_PAD_NOPULL	((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
-					MXS_PAD_PULL_VALID_MASK)
-#define MXS_PAD_PULLUP	((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
-					MXS_PAD_PULL_VALID_MASK)
-
-/* generic pad control used in most cases */
-#define MXS_PAD_CTRL	(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
-
-#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)		\
-		(((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |		\
-		((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |		\
-		((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |	\
-		((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |		\
-		((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |		\
-		((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
-
-/*
- * A pad becomes naked, when none of mA, vol or pull
- * validity bits is set.
- */
-#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
-		MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
-
-static inline unsigned int PAD_BANK(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
-}
-
-static inline unsigned int PAD_PIN(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
-}
-
-static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
-}
-
-static inline unsigned int PAD_MA(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
-}
-
-static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_VOL(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
-}
-
-static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_PULL(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
-}
-
-static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
-{
-	return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
-}
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad);
-
-/*
- * configures multiple pads
- * convenient way to call the above function with tables
- */
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
-
-#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
deleted file mode 100644
index 0e804e2..0000000
--- a/arch/arm/mach-mxs/iomux.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel at pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux at phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mxs.h>
-#include <mach/iomux.h>
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad)
-{
-	u32 reg, ofs, bp, bm;
-	void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
-
-	/* muxsel */
-	ofs = 0x100;
-	ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
-	bp = PAD_PIN(pad) % 16 * 2;
-	bm = 0x3 << bp;
-	reg = __raw_readl(iomux_base + ofs);
-	reg &= ~bm;
-	reg |= PAD_MUXSEL(pad) << bp;
-	__raw_writel(reg, iomux_base + ofs);
-
-	/* drive */
-	ofs = cpu_is_mx23() ? 0x200 : 0x300;
-	ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
-	/* mA */
-	if (PAD_MA_VALID(pad)) {
-		bp = PAD_PIN(pad) % 8 * 4;
-		bm = 0x3 << bp;
-		reg = __raw_readl(iomux_base + ofs);
-		reg &= ~bm;
-		reg |= PAD_MA(pad) << bp;
-		__raw_writel(reg, iomux_base + ofs);
-	}
-	/* vol */
-	if (PAD_VOL_VALID(pad)) {
-		bp = PAD_PIN(pad) % 8 * 4 + 2;
-		if (PAD_VOL(pad))
-			__mxs_setl(1 << bp, iomux_base + ofs);
-		else
-			__mxs_clrl(1 << bp, iomux_base + ofs);
-	}
-
-	/* pull */
-	if (PAD_PULL_VALID(pad)) {
-		ofs = cpu_is_mx23() ? 0x400 : 0x600;
-		ofs += PAD_BANK(pad) * 0x10;
-		bp = PAD_PIN(pad);
-		if (PAD_PULL(pad))
-			__mxs_setl(1 << bp, iomux_base + ofs);
-		else
-			__mxs_clrl(1 << bp, iomux_base + ofs);
-	}
-
-	return 0;
-}
-
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
-{
-	const iomux_cfg_t *p = pad_list;
-	int i;
-	int ret;
-
-	for (i = 0; i < count; i++) {
-		ret = mxs_iomux_setup_pad(*p);
-		if (ret)
-			return ret;
-		p++;
-	}
-
-	return 0;
-}
-- 
1.7.5.4




From broonie at opensource.wolfsonmicro.com  Mon Aug  6 11:49:51 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 16:49:51 +0100
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
Message-ID: <20120806154951.GQ16861@opensource.wolfsonmicro.com>

On Mon, Aug 06, 2012 at 10:19:50AM -0500, Matt Sealey wrote:

> it's not compiled in unless absolutely necessary. However, there was a
> rumble that this code may disappear or be reworked in the future
> making this also quite redundant. Since it's not in the

There's no point in the FIQ driver if the DMA drivers are supported.


From broonie at opensource.wolfsonmicro.com  Mon Aug  6 11:54:46 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 16:54:46 +0100
Subject: [PATCH 4/6] mfd: Use interrupt-parent as IRQ controller if
 specified in DT
In-Reply-To: <1344250002-6011-5-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-5-git-send-email-lee.jones@linaro.org>
Message-ID: <20120806155446.GD29272@sirena.org.uk>

On Mon, Aug 06, 2012 at 11:46:40AM +0100, Lee Jones wrote:

> -				domain = irq_find_host(parent->of_node);
> +#ifdef CONFIG_OF
> +				parent_node = of_irq_find_parent(np);
> +#endif

Shouldn't of_irq_find_parent() be stubbed out by the header?  Every
single user of this is going to need it.  Indeed, shouldn't we be making
irq_find_host() just do this?


From broonie at opensource.wolfsonmicro.com  Mon Aug  6 12:00:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 17:00:39 +0100
Subject: [PATCH 6/6] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
Message-ID: <20120806160039.GE29272@sirena.org.uk>

On Mon, Aug 06, 2012 at 11:46:42AM +0100, Lee Jones wrote:
> If we're booting with Device Tree enabled, we want the IRQ numbers to
> be taken and translated from the Device Tree binary. If not, they
> should be taken from the resource allocation defined in the AB8500 MFD
> core driver.

>  	ponkey->ab8500 = ab8500;
> -	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
> -	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
> +
> +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;

Shouldn't the irq domain be coping with this?  It seems like a massive
failure to have to do this in every single user, the irq domain should
be able to encapsulate all this stuff.


From broonie at opensource.wolfsonmicro.com  Mon Aug  6 12:02:26 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 17:02:26 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120806153750.GI10524@gmail.com>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
 <20120806153750.GI10524@gmail.com>
Message-ID: <20120806160226.GF29272@sirena.org.uk>

On Mon, Aug 06, 2012 at 04:37:52PM +0100, Lee Jones wrote:
> On Mon, Aug 06, 2012 at 01:19:15AM -0700, Dmitry Torokhov wrote:

> > > +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> > > +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;

> > Why this isn't done inside ab8500_irq_get_virq()?

> There's no reason why it can't be.

> My first version of the patch did just that in fact.

> Would that be your preference?

Restating my comment elsewhere...  why do we even need to do this in
_get_virq() - I'd *really* expect this to be handled by the irq domain
code.


From david.vrabel at citrix.com  Mon Aug  6 12:23:01 2012
From: david.vrabel at citrix.com (David Vrabel)
Date: Mon, 6 Aug 2012 17:23:01 +0100
Subject: [Xen-devel] [PATCH v2 07/23] xen/arm: Xen detection and
 shared_info page mapping
In-Reply-To: <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <501FEF65.1000304@citrix.com>

On 06/08/12 15:27, Stefano Stabellini wrote:
> Check for a "/xen" node in the device tree, if it is present set
> xen_domain_type to XEN_HVM_DOMAIN and continue initialization.
> 
> Map the real shared info page using XENMEM_add_to_physmap with
> XENMAPSPACE_shared_info.
> 
> Changes in v2:
> 
> - replace pr_info with pr_debug.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 52 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index d27c2a6..102d823 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -5,6 +5,9 @@
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
>  
>  struct start_info _xen_start_info;
>  struct start_info *xen_start_info = &_xen_start_info;
> @@ -33,3 +36,52 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  	return -ENOSYS;
>  }
>  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> +
> +/*
> + * == Xen Device Tree format ==
> + * - /xen node;
> + * - compatible "arm,xen";
> + * - one interrupt for Xen event notifications;
> + * - one memory region to map the grant_table.
> + */

These needs to be documented in Documentation/devicetree/bindings/ and
should be sent to the devicetree-discuss mailing list for review.

The node should be called 'hypervisor' I think.

The first word of the compatible string is the vendor/organization that
defined the binding so should be "xen" here.  This does give a odd
looking "xen,xen" but we'll have to live with that.

I'd suggest that the DT provided by the hypervisor or tools give the
hypercall ABI version in the compatible string as well.  e.g.,

hypervisor {
    compatible = "xen,xen-4.3", "xen,xen"
};

I missed the Xen patch that adds this node for dom0.  Can you point me
to it?

David

> +static int __init xen_guest_init(void)
> +{
> +	struct xen_add_to_physmap xatp;
> +	static struct shared_info *shared_info_page = 0;
> +	struct device_node *node;
> +
> +	node = of_find_compatible_node(NULL, NULL, "arm,xen");
> +	if (!node) {
> +		pr_debug("No Xen support\n");
> +		return 0;
> +	}
> +	xen_domain_type = XEN_HVM_DOMAIN;
> +
> +	if (!shared_info_page)
> +		shared_info_page = (struct shared_info *)
> +			get_zeroed_page(GFP_KERNEL);
> +	if (!shared_info_page) {
> +		pr_err("not enough memory\n");
> +		return -ENOMEM;
> +	}
> +	xatp.domid = DOMID_SELF;
> +	xatp.idx = 0;
> +	xatp.space = XENMAPSPACE_shared_info;
> +	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
> +	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
> +		BUG();
> +
> +	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
> +
> +	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
> +	 * page, we use it in the event channel upcall and in some pvclock
> +	 * related functions. We don't need the vcpu_info placement
> +	 * optimizations because we don't use any pv_mmu or pv_irq op on
> +	 * HVM.
> +	 * The shared info contains exactly 1 CPU (the boot CPU). The guest
> +	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
> +	 * for secondary CPUs as they are brought up. */
> +	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
> +	return 0;
> +}
> +core_initcall(xen_guest_init);



From linus.walleij at stericsson.com  Mon Aug  6 12:32:08 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 6 Aug 2012 18:32:08 +0200
Subject: [PATCH] clk: convert ARM RealView to common clk
Message-ID: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the ARM RealView machine over to using the common
clock. The approach is similar to the one used for the Integrator,
and we're reusing the ICST wrapper code.

We have to put the clock intialization in the timer init function
for the clocks to be available when initializing the timer,
keeping them in early_init() is too early for the common clk.

Since we now have to go down and compile drivers/clk/versatile
a CONFIG_COMMON_CLK_VERSATILE symbol has been added so the proper
code gets compiled into the kernel for either machine. A leftover
CLK_VERSATILE in the Integrator Kconfig was fixed up to use
the new symbol as well.

Tested on ARM RealView PB1176.

Cc: Pawel Moll <pawel.moll at arm.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                             |   7 +-
 arch/arm/mach-realview/core.c                | 106 -------------------------
 arch/arm/mach-realview/include/mach/clkdev.h |  16 ----
 arch/arm/mach-realview/realview_eb.c         |   2 +
 arch/arm/mach-realview/realview_pb1176.c     |   2 +
 arch/arm/mach-realview/realview_pb11mp.c     |   2 +
 arch/arm/mach-realview/realview_pba8.c       |   2 +
 arch/arm/mach-realview/realview_pbx.c        |   2 +
 drivers/clk/Kconfig                          |   7 ++
 drivers/clk/Makefile                         |   2 +-
 drivers/clk/versatile/Makefile               |   1 +
 drivers/clk/versatile/clk-realview.c         | 114 +++++++++++++++++++++++++++
 include/linux/platform_data/clk-realview.h   |   1 +
 13 files changed, 137 insertions(+), 127 deletions(-)
 delete mode 100644 arch/arm/mach-realview/include/mach/clkdev.h
 create mode 100644 drivers/clk/versatile/clk-realview.c
 create mode 100644 include/linux/platform_data/clk-realview.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..530630c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -279,7 +279,7 @@ config ARCH_INTEGRATOR
 	select ARM_AMBA
 	select ARCH_HAS_CPUFREQ
 	select COMMON_CLK
-	select CLK_VERSATILE
+	select COMMON_CLK_VERSATILE
 	select HAVE_TCM
 	select ICST
 	select GENERIC_CLOCKEVENTS
@@ -295,13 +295,12 @@ config ARCH_INTEGRATOR
 config ARCH_REALVIEW
 	bool "ARM Ltd. RealView family"
 	select ARM_AMBA
-	select CLKDEV_LOOKUP
-	select HAVE_MACH_CLKDEV
+	select COMMON_CLK
+	select COMMON_CLK_VERSATILE
 	select ICST
 	select GENERIC_CLOCKEVENTS
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLOCK
 	select PLAT_VERSATILE_CLCD
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb..ff007d1 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,7 +30,6 @@
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
-#include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
@@ -226,115 +225,10 @@ struct mmci_platform_data realview_mmc1_plat_data = {
 	.cd_invert	= true,
 };
 
-/*
- * Clock handling
- */
-static const struct icst_params realview_oscvco_params = {
-	.ref		= 24000000,
-	.vco_max	= ICST307_VCO_MAX,
-	.vco_min	= ICST307_VCO_MIN,
-	.vd_min		= 4 + 8,
-	.vd_max		= 511 + 8,
-	.rd_min		= 1 + 2,
-	.rd_max		= 127 + 2,
-	.s2div		= icst307_s2div,
-	.idx2s		= icst307_idx2s,
-};
-
-static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
-{
-	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
-	u32 val;
-
-	val = readl(clk->vcoreg) & ~0x7ffff;
-	val |= vco.v | (vco.r << 9) | (vco.s << 16);
-
-	writel(0xa05f, sys_lock);
-	writel(val, clk->vcoreg);
-	writel(0, sys_lock);
-}
-
-static const struct clk_ops oscvco_clk_ops = {
-	.round	= icst_clk_round,
-	.set	= icst_clk_set,
-	.setvco	= realview_oscvco_set,
-};
-
-static struct clk oscvco_clk = {
-	.ops	= &oscvco_clk_ops,
-	.params	= &realview_oscvco_params,
-};
-
-/*
- * These are fixed clocks.
- */
-static struct clk ref24_clk = {
-	.rate	= 24000000,
-};
-
-static struct clk sp804_clk = {
-	.rate	= 1000000,
-};
-
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup lookups[] = {
-	{	/* Bus clock */
-		.con_id		= "apb_pclk",
-		.clk		= &dummy_apb_pclk,
-	}, {	/* UART0 */
-		.dev_id		= "dev:uart0",
-		.clk		= &ref24_clk,
-	}, {	/* UART1 */
-		.dev_id		= "dev:uart1",
-		.clk		= &ref24_clk,
-	}, {	/* UART2 */
-		.dev_id		= "dev:uart2",
-		.clk		= &ref24_clk,
-	}, {	/* UART3 */
-		.dev_id		= "fpga:uart3",
-		.clk		= &ref24_clk,
-	}, {	/* UART3 is on the dev chip in PB1176 */
-		.dev_id		= "dev:uart3",
-		.clk		= &ref24_clk,
-	}, {	/* UART4 only exists in PB1176 */
-		.dev_id		= "fpga:uart4",
-		.clk		= &ref24_clk,
-	}, {	/* KMI0 */
-		.dev_id		= "fpga:kmi0",
-		.clk		= &ref24_clk,
-	}, {	/* KMI1 */
-		.dev_id		= "fpga:kmi1",
-		.clk		= &ref24_clk,
-	}, {	/* MMC0 */
-		.dev_id		= "fpga:mmc0",
-		.clk		= &ref24_clk,
-	}, {	/* CLCD is in the PB1176 and EB DevChip */
-		.dev_id		= "dev:clcd",
-		.clk		= &oscvco_clk,
-	}, {	/* PB:CLCD */
-		.dev_id		= "issp:clcd",
-		.clk		= &oscvco_clk,
-	}, {	/* SSP */
-		.dev_id		= "dev:ssp0",
-		.clk		= &ref24_clk,
-	}, {	/* SP804 timers */
-		.dev_id		= "sp804",
-		.clk		= &sp804_clk,
-	},
-};
-
 void __init realview_init_early(void)
 {
 	void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
 
-	if (machine_is_realview_pb1176())
-		oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
-	else
-		oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
-
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
 	versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
 }
 
diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h
deleted file mode 100644
index e58d077..0000000
--- a/arch/arm/mach-realview/include/mach/clkdev.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <plat/clock.h>
-
-struct clk {
-	unsigned long		rate;
-	const struct clk_ops	*ops;
-	const struct icst_params *params;
-	void __iomem		*vcoreg;
-};
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..a33e33b 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -27,6 +27,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -414,6 +415,7 @@ static void __init realview_eb_timer_init(void)
 	else
 		timer_irq = IRQ_EB_TIMER0_1;
 
+	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
 	realview_timer_init(timer_irq);
 	realview_eb_twd_init();
 }
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..f0298cb 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -326,6 +327,7 @@ static void __init realview_pb1176_timer_init(void)
 	timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
 	timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
 
+	realview_clk_init(__io_address(REALVIEW_SYS_BASE), true);
 	realview_timer_init(IRQ_DC1176_TIMER0);
 }
 
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..1f019f7 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -27,6 +27,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -312,6 +313,7 @@ static void __init realview_pb11mp_timer_init(void)
 	timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
 	timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
 
+	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
 	realview_timer_init(IRQ_TC11MP_TIMER0_1);
 	realview_pb11mp_twd_init();
 }
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..5032775 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -27,6 +27,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -261,6 +262,7 @@ static void __init realview_pba8_timer_init(void)
 	timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE);
 	timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20;
 
+	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
 	realview_timer_init(IRQ_PBA8_TIMER0_1);
 }
 
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..de64ba0 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -26,6 +26,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
+#include <linux/platform_data/clk-realview.h>
 
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -320,6 +321,7 @@ static void __init realview_pbx_timer_init(void)
 	timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
 	timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
 
+	realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
 	realview_timer_init(IRQ_PBX_TIMER0_1);
 	realview_pbx_twd_init();
 }
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7f0b5ca..89b726d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -40,4 +40,11 @@ config COMMON_CLK_WM831X
           Supports the clocking subsystem of the WM831x/2x series of
 	  PMICs from Wolfson Microlectronics.
 
+config COMMON_CLK_VERSATILE
+	tristate "Clock driver for ARM Reference designs"
+	depends on ARCH_INTEGRATOR || ARCH_REALVIEW
+	---help---
+          Supports clocking on ARM Reference designs Integrator/AP,
+	  Integrator/CP, RealView PB1176, EB, PB11MP and PBX.
+
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..cfa7eeb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
-obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile
index 50cf6a2..c0a0f64 100644
--- a/drivers/clk/versatile/Makefile
+++ b/drivers/clk/versatile/Makefile
@@ -1,3 +1,4 @@
 # Makefile for Versatile-specific clocks
 obj-$(CONFIG_ICST)		+= clk-icst.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= clk-integrator.o
+obj-$(CONFIG_ARCH_REALVIEW)	+= clk-realview.o
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c
new file mode 100644
index 0000000..e21a99c
--- /dev/null
+++ b/drivers/clk/versatile/clk-realview.c
@@ -0,0 +1,114 @@
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#include "clk-icst.h"
+
+/*
+ * Implementation of the ARM RealView clock trees.
+ */
+
+static void __iomem *sys_lock;
+static void __iomem *sys_vcoreg;
+
+/**
+ * realview_oscvco_get() - get ICST OSC settings for the RealView
+ */
+static struct icst_vco realview_oscvco_get(void)
+{
+	u32 val;
+	struct icst_vco vco;
+
+	val = readl(sys_vcoreg);
+	vco.v = val & 0x1ff;
+	vco.r = (val >> 9) & 0x7f;
+	vco.s = (val >> 16) & 03;
+	return vco;
+}
+
+static void realview_oscvco_set(struct icst_vco vco)
+{
+	u32 val;
+
+	val = readl(sys_vcoreg) & ~0x7ffff;
+	val |= vco.v | (vco.r << 9) | (vco.s << 16);
+
+	/* This magic unlocks the CM VCO so it can be controlled */
+	writel(0xa05f, sys_lock);
+	writel(val, sys_vcoreg);
+	/* This locks the CM again */
+	writel(0, sys_lock);
+}
+
+static const struct icst_params realview_oscvco_params = {
+	.ref		= 24000000,
+	.vco_max	= ICST307_VCO_MAX,
+	.vco_min	= ICST307_VCO_MIN,
+	.vd_min		= 4 + 8,
+	.vd_max		= 511 + 8,
+	.rd_min		= 1 + 2,
+	.rd_max		= 127 + 2,
+	.s2div		= icst307_s2div,
+	.idx2s		= icst307_idx2s,
+};
+
+static const struct clk_icst_desc __initdata realview_icst_desc = {
+	.params = &realview_oscvco_params,
+	.getvco = realview_oscvco_get,
+	.setvco = realview_oscvco_set,
+};
+
+/*
+ * realview_clk_init() - set up the RealView clock tree
+ */
+void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
+{
+	struct clk *clk;
+
+	sys_lock = sysbase + REALVIEW_SYS_LOCK_OFFSET;
+	if (is_pb1176)
+		sys_vcoreg = sysbase + REALVIEW_SYS_OSC0_OFFSET;
+	else
+		sys_vcoreg = sysbase + REALVIEW_SYS_OSC4_OFFSET;
+
+
+	/* APB clock dummy */
+	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+	clk_register_clkdev(clk, "apb_pclk", NULL);
+
+	/* 24 MHz clock */
+	clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
+				24000000);
+	clk_register_clkdev(clk, NULL, "dev:uart0");
+	clk_register_clkdev(clk, NULL, "dev:uart1");
+	clk_register_clkdev(clk, NULL, "dev:uart2");
+	clk_register_clkdev(clk, NULL, "fpga:kmi0");
+	clk_register_clkdev(clk, NULL, "fpga:kmi1");
+	clk_register_clkdev(clk, NULL, "fpga:mmc0");
+	clk_register_clkdev(clk, NULL, "dev:ssp0");
+	if (is_pb1176) {
+		/*
+		 * UART3 is on the dev chip in PB1176
+		 * UART4 only exists in PB1176
+		 */
+		clk_register_clkdev(clk, NULL, "dev:uart3");
+		clk_register_clkdev(clk, NULL, "dev:uart4");
+	} else
+		clk_register_clkdev(clk, NULL, "fpga:uart3");
+
+
+	/* 1 MHz clock */
+	clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
+				      1000000);
+	clk_register_clkdev(clk, NULL, "sp804");
+
+	/* ICST VCO clock */
+	clk = icst_clk_register(NULL, &realview_icst_desc);
+	clk_register_clkdev(clk, NULL, "dev:clcd");
+	clk_register_clkdev(clk, NULL, "issp:clcd");
+}
diff --git a/include/linux/platform_data/clk-realview.h b/include/linux/platform_data/clk-realview.h
new file mode 100644
index 0000000..2e426a7
--- /dev/null
+++ b/include/linux/platform_data/clk-realview.h
@@ -0,0 +1 @@
+void realview_clk_init(void __iomem *sysbase, bool is_pb1176);
-- 
1.7.11.3



From roylee17 at gmail.com  Mon Aug  6 12:43:12 2012
From: roylee17 at gmail.com (Tzu-Jung Lee)
Date: Tue, 7 Aug 2012 00:43:12 +0800
Subject: [PATCH 1/1] remoteproc: extend customized fw loader to cover
 request and release
In-Reply-To: <CAK=WgbbBHspN_LTUXH1kUugH8-Nr-G=p-G3Wj60tAmrqqfakmg@mail.gmail.com>
References: <1344237865-32491-1-git-send-email-roylee17@gmail.com>
 <CAK=WgbbBHspN_LTUXH1kUugH8-Nr-G=p-G3Wj60tAmrqqfakmg@mail.gmail.com>
Message-ID: <CAEvN+1h5dVxX74YtBNwjiqzZNrpK56jBw9TaJjszf_-E3DY2gw@mail.gmail.com>

Hi Ohad,

On Mon, Aug 6, 2012 at 10:16 PM, Ohad Ben-Cohen <ohad at wizery.com> wrote:
> Hi Tzu-Jung Lee,
>
> On Mon, Aug 6, 2012 at 10:24 AM, Tzu-Jung Lee <roylee17 at gmail.com> wrote:
>> Previously, the remoteproc mandates an actual ELF firmware in order to
>> parse the resource table and boot the remoteproc.
>>
>> An fw loader abstraction was added in v3.61-rc1 to make the ELF as a
>> "default" handler, and allows firmwares in other formats to be loaded.
>>
>> However, in our use cases, we don't actually have a firmware for linux
>> to load. The remote processor always boots first, and then boots the
>> rest of processors that running linux.
>
> Can you describe your use case some more ?

It's three processors AMP SoC, the first powered on processors runs
 an RTOS and boots up the other two which run linux.

> What parts in remoteproc are actually helpful for you (not much I
> guess if Linux doesn't control the life cycle of the remote processor
> in your case) ?
>
> Do you use rpmsg ?

Yes, I'm using rpmsg.
And actually the remoteproc provides a good abstraction and the generic
facilities sysfs/debugfs handling, resource format, vring allocation, etc...
And the start/stop/kick API also serves as good place for handshaking
with the remote processors. Overall, most of the framework works well with
our platform, and the difference can be hidden in the platform priv
data structure.

>> In this case, forging an binary firmware just for the resource table
>> creates a burden for maintenence.
>> Allowing the firmware request/release function to be customized gives
>> developers to construct the reqource table in memory, instead of loading
>> one from filesystem.
>
> I'm not sure this is an ideal abstraction though.

Agree.
The patch may not solve this, but it should address some issues I'm having.

> The problem you describe is architectural and not necessarily related
> with a specific binary format, which this patch ties it up with (by
> abstracting it away in rproc_fw_ops). It seems that a
> binary-format-agnostic solution is preferable, because it could then
> be utilized by any platform, regardless of the binary format it uses.

> In general we prefer not to adopt a solution that puts the resource
> table in the kernel, because that means redundant churn and
> compatibility issues, as the resource table is inherently coupled with
> the software running on the remote processor, and not with the Linux
> kernel.

Yes, that's the point.

The format issue has been addressed by the fw format handler.
But we still need to address where the data come from.
Even it is in ELF format, it may not necessarily come from root file system.
It can be loaded from MTD partition or constructed/derived from the cmdline.

> An easy solution is to allow loading an external stand-alone resource
> table from the filesystem. We've discussed this in the past and
> several parties showed interest. Will it help you ?

Actually, I've been using the this approach for the past few weeks.
I forged an ELF file containing the resource table, and dummy loadable
sections, otherwise it  failed the sanity checks. Until yesterday I merged
and found the fw format handler support in v3.6-rc1, and wondered if we
can just extend it a little bit to not load (bypass) the firmware at all.

> Another possible solution is to allow the low level rproc driver to
> provide the remoteproc framework a pointer to an in-memory resource
> table. This may prove useful in case the remote processor is already
> up when Linux boots, and the resource table is already loaded to
> memory.

That's what I'm trying to do, and it has two things needs to be address.

  1)  Make the firmware loading step "optional" in the booting process.

  2)  Allow the remoteproc use an customized handler to get the resource table.

Thanks,
Roy


From otavio at ossystems.com.br  Mon Aug  6 12:51:07 2012
From: otavio at ossystems.com.br (Otavio Salvador)
Date: Mon, 6 Aug 2012 13:51:07 -0300
Subject: [PATCH 1/6] ARM: mxs: tx28: reset fec phy for device tree boot
In-Reply-To: <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
 <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAP9ODKqLzfSRFMjg6yrmzTviNv4R3EyD0Sa2TMnWvKL0Djyj=Q@mail.gmail.com>

On Mon, Aug 6, 2012 at 12:42 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> For non-DT boot, function tx28_add_fec0 configures all ENET0 pins
> into gpio mode for resetting fec phy, and then reconfigures those pins
> into ENET function after that.
>
> For DT boot, all the pin configuration is done by pinctrl subsystem.
> Ideally, when gpio_requst gets called, GPIO subsystem should call

                        ^ typo

> pinctrl to configure pins into gpio mode automatically, and have pins
> freed up from pinctrl subsystem when gpio_free is called.  But right
> now, this cooperation between gpio and pinctrl hasn't been available.
> As the result, we have to explicitly call pinctrl_get_select and
> pinctrl_put for device tree boot.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Acked-by: Lothar Wa?mann <LW at KARO-electronics.de>
> ---
>  arch/arm/boot/dts/imx28-tx28.dts |   21 +++++++++-
>  arch/arm/mach-mxs/mach-mxs.c     |   82 +++++++++++++++++++++++++++++++++++++-
>  2 files changed, 101 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
> index 62bf767..a56ae05 100644
> --- a/arch/arm/boot/dts/imx28-tx28.dts
> +++ b/arch/arm/boot/dts/imx28-tx28.dts
> @@ -34,6 +34,24 @@
>                                         fsl,voltage = <1>;
>                                         fsl,pull-up = <0>;
>                                 };
> +
> +                               mac0_pins_gpio: mac0-gpio-mode at 0 {
> +                                       reg = <0>;
> +                                       fsl,pinmux-ids = <
> +                                               0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
> +                                               0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
> +                                               0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
> +                                               0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
> +                                               0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
> +                                               0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
> +                                               0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
> +                                               0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
> +                                               0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
> +                                       >;
> +                                       fsl,drive-strength = <0>;
> +                                       fsl,voltage = <1>;
> +                                       fsl,pull-up = <0>;
> +                               };
>                         };
>                 };
>
> @@ -72,8 +90,9 @@
>         ahb at 80080000 {
>                 mac0: ethernet at 800f0000 {
>                         phy-mode = "rmii";
> -                       pinctrl-names = "default";
> +                       pinctrl-names = "default", "gpio_mode";
>                         pinctrl-0 = <&mac0_pins_a>;
> +                       pinctrl-1 = <&mac0_pins_gpio>;
>                         status = "okay";
>                 };
>         };
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 02d1ab2..6ba37df 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -12,8 +12,9 @@
>
>  #include <linux/clk.h>
>  #include <linux/clkdev.h>
> +#include <linux/delay.h>
>  #include <linux/err.h>
> -#include <linux/init.h>
> +#include <linux/gpio.h>
>  #include <linux/init.h>
>  #include <linux/irqdomain.h>
>  #include <linux/micrel_phy.h>
> @@ -21,10 +22,12 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  #include <linux/phy.h>
> +#include <linux/pinctrl/consumer.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/time.h>
>  #include <mach/common.h>
>  #include <mach/digctl.h>
> +#include <mach/mxs.h>
>
>  static struct fb_videomode mx23evk_video_modes[] = {
>         {
> @@ -273,6 +276,80 @@ static void __init apx4devkit_init(void)
>         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
>  }
>
> +#define ENET0_MDC__GPIO_4_0    MXS_GPIO_NR(4, 0)
> +#define ENET0_MDIO__GPIO_4_1   MXS_GPIO_NR(4, 1)
> +#define ENET0_RX_EN__GPIO_4_2  MXS_GPIO_NR(4, 2)
> +#define ENET0_RXD0__GPIO_4_3   MXS_GPIO_NR(4, 3)
> +#define ENET0_RXD1__GPIO_4_4   MXS_GPIO_NR(4, 4)
> +#define ENET0_TX_EN__GPIO_4_6  MXS_GPIO_NR(4, 6)
> +#define ENET0_TXD0__GPIO_4_7   MXS_GPIO_NR(4, 7)
> +#define ENET0_TXD1__GPIO_4_8   MXS_GPIO_NR(4, 8)
> +#define ENET_CLK__GPIO_4_16    MXS_GPIO_NR(4, 16)
> +
> +#define TX28_FEC_PHY_POWER     MXS_GPIO_NR(3, 29)
> +#define TX28_FEC_PHY_RESET     MXS_GPIO_NR(4, 13)
> +#define TX28_FEC_nINT          MXS_GPIO_NR(4, 5)
> +
> +static const struct gpio tx28_gpios[] __initconst = {
> +       { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
> +       { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
> +       { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
> +       { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
> +       { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
> +       { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
> +       { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
> +       { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
> +       { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
> +       { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
> +       { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
> +       { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
> +};
> +
> +static void __init tx28_post_init(void)
> +{
> +       struct device_node *np;
> +       struct platform_device *pdev;
> +       struct pinctrl *pctl;
> +       int ret;
> +
> +       enable_clk_enet_out();
> +
> +       np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
> +       pdev = of_find_device_by_node(np);
> +       if (!pdev) {
> +               pr_err("%s: failed to find fec device\n", __func__);
> +               return;
> +       }
> +
> +       pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
> +       if (IS_ERR(pctl)) {
> +               pr_err("%s: failed to get pinctrl state\n", __func__);
> +               return;
> +       }
> +
> +       ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
> +       if (ret) {
> +               pr_err("%s: failed to request gpios: %d\n", __func__, ret);
> +               return;
> +       }
> +
> +       /* Power up fec phy */
> +       gpio_set_value(TX28_FEC_PHY_POWER, 1);
> +       mdelay(26); /* 25ms according to data sheet */
> +
> +       /* Mode strap pins */
> +       gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
> +       gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
> +       gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
> +
> +       udelay(100); /* minimum assertion time for nRST */
> +
> +       /* Deasserting FEC PHY RESET */
> +       gpio_set_value(TX28_FEC_PHY_RESET, 1);
> +
> +       pinctrl_put(pctl);
> +}
> +
>  static void __init mxs_machine_init(void)
>  {
>         if (of_machine_is_compatible("fsl,imx28-evk"))
> @@ -286,6 +363,9 @@ static void __init mxs_machine_init(void)
>
>         of_platform_populate(NULL, of_default_bus_match_table,
>                              mxs_auxdata_lookup, NULL);
> +
> +       if (of_machine_is_compatible("karo,tx28"))
> +               tx28_post_init();
>  }
>
>  static const char *imx23_dt_compat[] __initdata = {
> --
> 1.7.5.4
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br


From fabio.estevam at freescale.com  Mon Aug  6 12:59:06 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 13:59:06 -0300
Subject: [PATCH] ARM: mxs_defconfig: Add LED, PWM and MTD_CHAR support
Message-ID: <1344272346-22797-1-git-send-email-fabio.estevam@freescale.com>

Add LED, PWM and MTD_CHAR support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/mxs_defconfig |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index e3487e4..4cb6170 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -60,6 +60,7 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
@@ -118,12 +119,23 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
 CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_PWM=y
+CONFIG_PWM_MXS=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
-- 
1.7.1




From lee.jones at linaro.org  Mon Aug  6 13:21:10 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 18:21:10 +0100
Subject: [PATCH 4/6] mfd: Use interrupt-parent as IRQ controller if
 specified in DT
In-Reply-To: <20120806155446.GD29272@sirena.org.uk>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-5-git-send-email-lee.jones@linaro.org>
 <20120806155446.GD29272@sirena.org.uk>
Message-ID: <20120806172109.GA31409@gmail.com>

On Mon, Aug 06, 2012 at 04:54:46PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 11:46:40AM +0100, Lee Jones wrote:
> 
> > -				domain = irq_find_host(parent->of_node);
> > +#ifdef CONFIG_OF
> > +				parent_node = of_irq_find_parent(np);
> > +#endif
> 
> Shouldn't of_irq_find_parent() be stubbed out by the header?  Every
> single user of this is going to need it.  Indeed, shouldn't we be making
> irq_find_host() just do this?

Sounds reasonable. I'll look into it tomorrow.
-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Mon Aug  6 13:22:05 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 18:22:05 +0100
Subject: [PATCH 6/6] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120806160039.GE29272@sirena.org.uk>
References: <1344250002-6011-1-git-send-email-lee.jones@linaro.org>
 <1344250002-6011-7-git-send-email-lee.jones@linaro.org>
 <20120806160039.GE29272@sirena.org.uk>
Message-ID: <20120806172204.GB31409@gmail.com>

On Mon, Aug 06, 2012 at 05:00:39PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 11:46:42AM +0100, Lee Jones wrote:
> > If we're booting with Device Tree enabled, we want the IRQ numbers to
> > be taken and translated from the Device Tree binary. If not, they
> > should be taken from the resource allocation defined in the AB8500 MFD
> > core driver.
> 
> >  	ponkey->ab8500 = ab8500;
> > -	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
> > -	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
> > +
> > +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> > +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
> 
> Shouldn't the irq domain be coping with this?  It seems like a massive
> failure to have to do this in every single user, the irq domain should
> be able to encapsulate all this stuff.

Already in hand.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Mon Aug  6 13:24:07 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 6 Aug 2012 18:24:07 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120806160226.GF29272@sirena.org.uk>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
 <20120806153750.GI10524@gmail.com>
 <20120806160226.GF29272@sirena.org.uk>
Message-ID: <20120806172406.GC31409@gmail.com>

On Mon, Aug 06, 2012 at 05:02:26PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 04:37:52PM +0100, Lee Jones wrote:
> > On Mon, Aug 06, 2012 at 01:19:15AM -0700, Dmitry Torokhov wrote:
> 
> > > > +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> > > > +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
> 
> > > Why this isn't done inside ab8500_irq_get_virq()?
> 
> > There's no reason why it can't be.
> 
> > My first version of the patch did just that in fact.
> 
> > Would that be your preference?
> 
> Restating my comment elsewhere...  why do we even need to do this in
> _get_virq() - I'd *really* expect this to be handled by the irq domain
> code.

I really should stop reading my emails backwards. :)

I'll look into this tomorrow.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From thomas.abraham at linaro.org  Mon Aug  6 13:37:33 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 6 Aug 2012 23:07:33 +0530
Subject: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412
In-Reply-To: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>

On 6 August 2012 19:40, Dongjin Kim <tobetter at gmail.com> wrote:
> The HKDK4412 is the CPU module developed by Hardkernel which is based on
> Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine ID
> (4289) is registered.
>
> Change-Id: I3af02808c03b9acea916c310390a4904ad92d761
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/mach-exynos/Kconfig         |   23 +
>  arch/arm/mach-exynos/Makefile        |    1 +
>  arch/arm/mach-exynos/mach-hkdk4412.c |  979 ++++++++++++++++++++++++++++++++++
>  arch/arm/tools/mach-types            |    1 +
>  4 files changed, 1004 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c

How about looking at using device tree option for this board. That
might require additional effort but would be helpful in the long run.

Thanks,
Thomas.


From arnd at arndb.de  Mon Aug  6 11:29:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 15:29:11 +0000
Subject: [PATCH 1/3] dmaengine: mmp-pdma support
In-Reply-To: <CAMj5BkigKhGE525at_pdN7cmav0K3-yfVmFOmWunmf4M_pBU2Q@mail.gmail.com>
References: <1342763164-19208-1-git-send-email-zhangfei.gao@marvell.com>
 <201207250858.39420.arnd@arndb.de>
 <CAMj5BkigKhGE525at_pdN7cmav0K3-yfVmFOmWunmf4M_pBU2Q@mail.gmail.com>
Message-ID: <201208061529.12150.arnd@arndb.de>

On Thursday 26 July 2012, zhangfei gao wrote:
> On Wed, Jul 25, 2012 at 4:58 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Wednesday 25 July 2012, zhangfei gao wrote:

> >
> > The current plan is to allow an arbitrary number of channels in the client,
> > which can all go to the same or different dmaengine drivers. You can also
> > specify multiple channels that can be used as alternatives, by adding a
> > dma-names property and naming them the same. Further, the number of fields
> > required for specifying the request line is determined by the dmac driver.
> > The first two cells of each specifier are parsed by the dmaengine common
> > code and all following ones are parsed handed to the dmac specific driver.
> >
> > A complex example would be
> >
> >                  dmas = <&pdma 1 0x1110   /* Y on pdma */
> >                         &tdma 1 0x100 32  /* Y on tdma */
> >                         &pdma 1 0x1114    /* U */
> >                         &tdma 1 0x200 32  /* U */
> >                         &pmaa 1 0x1118    /* V */
> >                         &tdma 1 0x300 32>; /* V */
> >                 dma-names = "Y", "Y", "U", "U", "V", "V";
> >
> > In this case the pdma node would set #dma-cells=<3> and the tdma node would
> > set #dma-cells=<4> in order to pass two separate arguments. Through the
> > dma-names property, the common code can identify which channels belong
> > together and the driver just needs to ask for a channel like
> >
> >         chan_y = of_dma_request_named_channel(pdev, "Y");
> >
> 
> Thanks Arnd for patient explain.
> 
> Still want to double confirm the understand:
> DMA client (nand, camera) get dmas, since each client has different dmas.
> DMA client (nand) pass dmas via dmaengine API and request and config
> channel with dmas.

Yes, although the client driver would not actually pass the property,
it would just pass the device pointer and then the dmaengine code
can look up the property.

> As you said:
> "The first two cells of dmas are parsed by the dmaengine common code.
> All following dmas cells are parsed handed to the dmac specific driver."
> Then dmac get config info like request line, etc.
> 
> "Further, the number of fields
> required for specifying the request line is determined by the dmac driver."
> dmac driver can not get client dmas from dt file but have to get from
> dmaengine API, right?

The dmac driver registers a callback to the dmaengine subsystem.
The client calls into dmaengine, which calls this dmac function.

> Besides, still not find of_dma_request_named_channel in latest linux-next.git.
> So dmac driver have to wait?

Yes, I hope we can get this done in v3.7.

> >> >> >> +static struct of_device_id mmp_pdma_dt_ids[] = {
> >> >> >> +     { .compatible = "mrvl,mmp-pdma", .data = (void *)MMP_PDMA},
> >> >> >> +     {}
> >> >> >> +};
> >> >> >> +MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
> >> >> >
> >> >> > You don't actually use the data field afaict, so that can be removed.
> >> >>
> >> >> We keep .data as type, for easy extension, in case future soc register
> >> >> may be different.
> >> >> It is fine to remove the data field, as well as mmp_pdma_id_table.
> >> >
> >> > Ok. Note that in many cases it's actually easier to point the .data
> >> > field to a data structure rather than an integer, it's valid either
> >> > way. Unfortunately the type is different between of_device_id and
> >> > platform_device_id, but a pointer also works for both.
> >>
> >> Yes, also find .data is different between of_device_id and platform_device_id.
> >> So using strong conversion for simplification.
> >> Will change to data structure if you think it is more professional.
> >
> > Just do whatever your fits your needs, I'm just noting that in a lot of
> > drivers, using a structure ends up being easier.
> 
> If so, prefer using strong conversion since it is simple :)
> If using data structure, one structure with single member "type" has
> to be defined.

You misunderstood the purpose of the data structure: The idea is to
remove the need for a "type" member but instead convert every decision
that is based on a type currently into a lookup of one of the
members of the structure.

Right now your driver does not seem to look at the type at all, so
you can simply remove that member altogether.

> >> > If you think that you will see different kinds of pdma that you need
> >> > to distinguish here, I would recommend that you use a more specific
> >> > "compatible" identifier, like
> >> >
> >> >         { .compatible = "marvell,pxa168-pdma", };
> >> >
> >> mmp-tdma.c have to take this, since register difference in pxa910 and pxa688.
> >> mmp-pdma.c register keeps same since pxa3xx, we will remove the type.
> >
> > In the pdma case, I would suggest that you also specify the name of the soc
> > there, but in the device tree list the device as compatible with the older
> > one, e.g. for pxa930:
> >
> >         compatible = "marvell,pxa930-pdma", "marvell,pxa300-pdma";
> >
> > This way the driver needs to know about only one, but is ready for future
> > extensions, e.g. if a future pxa985 is slightly different.
> 
> How about using the "marvell,mmp-pdma" on all platforms with same
> register, including pxa3xx.
> If future pxa985 is slightly different, we add "marvell,pxa985-pdma" then.
> 
> If using different name on different platform, they may too many names.

That would also be confusing because then it's not clear why pxa985
does not use a marvell,mmp-pdma. Using the name of the first model
that you are compatible with is the more common way, people will understand
that.

	Arnd



From arnd at arndb.de  Mon Aug  6 13:48:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 17:48:26 +0000
Subject: [GIT PULL][for 3.7] pull request from board branch in pxa git tree
In-Reply-To: <CAN1soZzRkozi3njrx5VJoXhP-o6H10knbDoWC=9xeQcjYNEbGw@mail.gmail.com>
References: <CAN1soZzRkozi3njrx5VJoXhP-o6H10knbDoWC=9xeQcjYNEbGw@mail.gmail.com>
Message-ID: <201208061748.26403.arnd@arndb.de>

On Friday 03 August 2012, Haojian Zhuang wrote:
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/hzhuang1/linux.git board
> 
> for you to fetch changes up to 0f74da3f4bd91da4f8d3f79c9dc39a781cc7ae82:
> 
>   ARM: ttc_dkb: add nand support (2012-08-03 15:15:58 +0800)
> 

Pulled, thanks!

	Arnd


From arnd at arndb.de  Mon Aug  6 13:52:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 17:52:35 +0000
Subject: [GIT PULL] imx fixes for 3.6
In-Reply-To: <20120804144636.GC3405@S2101-09.ap.freescale.net>
References: <20120804144636.GC3405@S2101-09.ap.freescale.net>
Message-ID: <201208061752.35513.arnd@arndb.de>

On Saturday 04 August 2012, Shawn Guo wrote:
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/fixes-for-3.6
> 

Pulled, thanks!

	Arnd


From arnd at arndb.de  Mon Aug  6 13:54:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 17:54:34 +0000
Subject: [GIT PULL] mxs fixes for 3.6
In-Reply-To: <20120804144058.GB3405@S2101-09.ap.freescale.net>
References: <20120804144058.GB3405@S2101-09.ap.freescale.net>
Message-ID: <201208061754.34914.arnd@arndb.de>

On Saturday 04 August 2012, Shawn Guo wrote:
> Hi Arnd, Olof,
> 
> Please pull the following mxs fixes for 3.6.
> 
> Regards,
> Shawn
> 
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
>   git://git.linaro.org/people/shawnguo/linux-2.6.git mxs/fixes-for-3.6
> 
> Fabio Estevam (2):
>       ARM: mx23: Fix registers range
>       ARM: mx28: Fix registers range
> 
> Marek Vasut (1):
>       ARM: mxs: Remove MMAP_MIN_ADDR setting from mxs_defconfig
> 

Pulled, thanks!

	Arnd


From arnd at arndb.de  Mon Aug  6 13:56:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 6 Aug 2012 17:56:17 +0000
Subject: [PATCH] ARM: integrator: use clk_prepare_enable() for timer
In-Reply-To: <CACRpkdaqFqE5D5LkT0buof_5YZkpP_J_Y6qu0B5gKi4W3mFEkw@mail.gmail.com>
References: <1344199075-4111-1-git-send-email-linus.walleij@linaro.org>
 <201208061437.52415.arnd@arndb.de>
 <CACRpkdaqFqE5D5LkT0buof_5YZkpP_J_Y6qu0B5gKi4W3mFEkw@mail.gmail.com>
Message-ID: <201208061756.18147.arnd@arndb.de>

On Monday 06 August 2012, Linus Walleij wrote:
> On Mon, Aug 6, 2012 at 4:37 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Sunday 05 August 2012, Linus Walleij wrote:
> >> On Sun, Aug 5, 2012 at 10:37 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> >> > The Integrator timer is using the clock framework to get the
> >> > timer frequency, but missed to prepare the clock before enabling.
> >> >
> >> > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> >>
> >> Arnd, Olof,
> >>
> >> If this patch looks OK to you I request that you apply it alone, no pull
> >> requests, too much hazzle for a single patch...
> >>
> >
> > Applying a patch is fine, but please explain which version(s) to apply
> > this to? Is it a regression in v3.6, or should it be backported to
> > earlier versions too?
> 
> Ah sorry. This is for the v3.6 rc:s.
> 
> The migration to common clock makes the kernel spit warnings
> unless you prepare all clocks.
> 

Ok, I've applied it to the fixes branch now.

	Arnd


From nicolas.pitre at linaro.org  Mon Aug  6 14:02:19 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 6 Aug 2012 14:02:19 -0400 (EDT)
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <20120806132642.GC18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <20120806111224.GA18957@n2100.arm.linux.org.uk> <501FC44E.1040806@ti.com>
 <20120806132642.GC18957@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1208061356480.5231@xanadu.home>

On Mon, 6 Aug 2012, Russell King - ARM Linux wrote:

> On Mon, Aug 06, 2012 at 09:19:10AM -0400, Cyril Chemparathy wrote:
> > With a flush_cache_all(), we could avoid having to operate a cacheline  
> > at a time, but that clobbers way more than necessary.
> 
> You can't do that, because flush_cache_all() on some CPUs requires the
> proper MMU mappings to be in place, and you can't get those mappings
> in place because you don't have the V:P offsets fixed up in the kernel.
> Welcome to the chicken and egg problem.

This problem is fixed in this case by having the p2v and v2p code sites 
using an out-of-line non optimized computation until those sites are 
runtime patched with the inlined optimized computation we have today.


Nicolas


From matt at genesi-usa.com  Mon Aug  6 14:09:26 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 13:09:26 -0500
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120806154951.GQ16861@opensource.wolfsonmicro.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
Message-ID: <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>

On Mon, Aug 6, 2012 at 10:49 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Aug 06, 2012 at 10:19:50AM -0500, Matt Sealey wrote:
>
>> it's not compiled in unless absolutely necessary. However, there was a
>> rumble that this code may disappear or be reworked in the future
>> making this also quite redundant. Since it's not in the
>
> There's no point in the FIQ driver if the DMA drivers are supported.

http://patchwork.ozlabs.org/patch/128853/

Russell's sage advise; "It's worth pointing out that people end up
using FIQs for certain things
because the hardware requires you to do it.  So if a platform is using
them, they're probably not
doing it out of choice, but are doing it because it's a baseline
requirement to get something working."

I don't recall Sascha's response to this, I thought it was on the ML
but it may have been in private,
but something is broken on the MX27/28 SSI FIFO which means FIQ is the
only way to get reliable
audio since the DMA unit cannot get accurate alarms (this seems a
common bug in Freescale
processors :) - I'll let him elaborate since I've never even seen an
MX28 let alone booted one, and
our MX27 board never got tested without the FIQ code if I recall correctly.

So that needs to stay, the issue here is why did nobody catch
ssi-fiq.S breaking in testing MX51
Babbage and building a Thumb2 kernel, for example? Why did nobody
notice it was building when
configuring for MX3/5/6 boards (which do actually have working SSI and
DMA, as you assume, and
do not need this code, nor build the imx-pcm-dma-fiq part of the
driver anyway)? I'm willing to fix all
of the above, but if there's an obvious deficiency in testing at some
point we need to fix that too..

Of course if Sascha says the fiq dma hack can disappear forever that's
absolutely fine, I'm also
willing to be the one to delete it... :)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From Dongjin.Kim at agreeyamobility.net  Mon Aug  6 14:16:18 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Mon, 6 Aug 2012 18:16:18 +0000
Subject: =?utf-8?B?7ZqM7IugOiBbUEFUQ0hdIE9EUk9JRC1YOiBoa2RrNDQxMjogQWRkIG5ldyBo?=
 =?utf-8?Q?ardware_based_on_Exynos4412?=
In-Reply-To: <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>,
 <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F4362EE@SN2PRD0510MB370.namprd05.prod.outlook.com>

Hello Tomas,

I am agree with you to look at using device tree and I have some plan for it.
But as of now I am focusing to bring up the hardware itself with mainline kernel and merge into it.
I also need some time to look at the requirement of device tree, because I am not familiar with it yet.

Any advice will be welcomed.

Thanks,
Dongjin.
________________________________________
?? ??: Thomas Abraham [thomas.abraham at linaro.org]
?? ??: 2012? 8? 7? ??? ?? 2:37
?? ??: Dongjin Kim
??: Dongjin Kim; Kukjin Kim; Russell King; Tony Lindgren; Jon Medhurst; Shawn Guo; Uwe Kleine-K?nig; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
??: Re: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412

On 6 August 2012 19:40, Dongjin Kim <tobetter at gmail.com> wrote:
> The HKDK4412 is the CPU module developed by Hardkernel which is based on
> Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine ID
> (4289) is registered.
>
> Change-Id: I3af02808c03b9acea916c310390a4904ad92d761
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/mach-exynos/Kconfig         |   23 +
>  arch/arm/mach-exynos/Makefile        |    1 +
>  arch/arm/mach-exynos/mach-hkdk4412.c |  979 ++++++++++++++++++++++++++++++++++
>  arch/arm/tools/mach-types            |    1 +
>  4 files changed, 1004 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c

How about looking at using device tree option for this board. That
might require additional effort but would be helpful in the long run.

Thanks,
Thomas.


From olof at lixom.net  Mon Aug  6 14:33:21 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 6 Aug 2012 11:33:21 -0700
Subject: =?UTF-8?Q?Re=3A_=ED=9A=8C=EC=8B=A0=3A_=5BPATCH=5D_ODROID=2DX=3A_hkdk4412=3A_Add_new_hard?=
 =?UTF-8?Q?ware_based_on_Exynos4412?=
In-Reply-To: <A6A3B7488C419F488E5B13FFD03C08AD2F4362EE@SN2PRD0510MB370.namprd05.prod.outlook.com>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4362EE@SN2PRD0510MB370.namprd05.prod.outlook.com>
Message-ID: <CAOesGMh=6QrCmL4EqnSqTxi1nH+8Wn+x=z9BYq8QJCznH3a=zQ@mail.gmail.com>

Hi,

On Mon, Aug 6, 2012 at 11:16 AM, Dongjin Kim
<Dongjin.Kim at agreeyamobility.net> wrote:
> Hello Tomas,
>
> I am agree with you to look at using device tree and I have some plan for it.
> But as of now I am focusing to bring up the hardware itself with mainline kernel and merge into it.
> I also need some time to look at the requirement of device tree, because I am not familiar with it yet.
>
> Any advice will be welcomed.

Basic rule (that has some flexibility for legacy platforms) is that
the net movement of board support should move from board files to
device-tree based. Introduction of a brand new board like this is a
prime example of something that should be using device tree from day
1.


-Olof


From matt at genesi-usa.com  Mon Aug  6 14:40:26 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 13:40:26 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
Message-ID: <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>

On Sun, Aug 5, 2012 at 11:32 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Sun, 5 Aug 2012, Uwe Kleine-K?nig wrote:
>
>> On Fri, Aug 03, 2012 at 12:45:32PM +0100, Will Deacon wrote:
>> > On Fri, Aug 03, 2012 at 10:04:52AM +0100, Uwe Kleine-K?nig wrote:
>> > > Hello,
>> >
>> > Hi Uwe,
>> >
>> > > in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have
>> > >
>> > >   .arm
>> > >  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
>> > >  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
>> > >  THUMB( .thumb                  )       @ switch to Thumb now.
>> > >  THUMB(1:                       )
>> > >
>> > > as first instructions at the entry point. This is a problem for
>> > > thumb2-only cpus (e.g. Cortex-M3).
>> >
>> > Yup, Documentation/arm/Booting mentions this too.
>> >
>> > > Up to now I commented out the first three lines for the Cortex-M3 port.
>> > > What should we do about that. There are two possibilities I see:
>> > >
>> > >  a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
>> > >     first three lines out if it is given.
>> > >  b) expect the bootloader to directly jump to the label 1.
>> > >
>> > > The downside of a) is that a boot loader on a cpu that is capable to
>> > > execute the tradtional instructions would need to detect if the switch
>> > > to thumb is there or not and react accordingly. (In fact it needs to
>> > > distringuish three cases:
>> > >
>> > >  - traditional kernel
>> > >  - thumb2 kernel with ARM entry
>> > >  - thumb2 kernel without ARM entry
>> > >
>> > > .) So I think b) is the more sensible option in the long run.
>> > >
>> > > What do you think?
>> >
>> > How about something like:
>> >
>> >
>> > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> > index 835898e..9f07be2 100644
>> > --- a/arch/arm/kernel/head.S
>> > +++ b/arch/arm/kernel/head.S
>> > @@ -86,6 +86,7 @@
>> >         __HEAD
>> >  ENTRY(stext)
>> >
>> > + THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
>> >   THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
>> >   THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
>> >   THUMB(        .thumb                  )       @ switch to Thumb now.
>> Great idea, but it doesn't work as suggested. My compiler already barfs
>> on the .arm above:
>
> Let's stop splitting hairs.
>
> A Cortex-M kernel simply won't run on anything else.  It certainly won't
> run on ARM mode capable processors.  So in this case just make the
> kernel entry point Thumb mode only by #ifdef'ing out the .arm part.
>
> This is good _only_ for CPUs without any ARM mode capability though.

Wouldn't it be nice to have a solution where you can build a Thumb2
bootloader (like U-Boot which can do this) for an ARM-with-Thumb2
processor and not needlessly enter/exit Thumb2 mode while entering the
kernel? It's not something that could be automated but it might make
for something a little more deterministic in terms of running "the
same code" on two only slightly different architectures (after all why
else would you want to run Linux on a Cortex-M? Most microcontroller
development shuns Linux :)

Could we have an option that basically is subordinate to
CONFIG_THUMB2_KERNEL such as CONFIG_THUMB2_ENTRYPOINT (depends on
CONFIG_THUMB2) with a huge warning in the enable that this won't boot
from U-Boot that's not compiled to support it (and there is a patch
for this somewhere that someone has to write to support it) and/or
your bootloader absolutely MUST be in Thumb2 mode before it jumps to
the entrypoint to avoid an exception?

Maybe we could implement a shiny new zImage magic value, I'm not sure
if 0x016f2818 might have some sentimental value, but there's nothing
to say that 0x016f2819 wouldn't also be valid and indicate that it's
an ARM zImage with a Thumb2 entrypoint?

What kind of images are we expecting to load on a Cortex-M anyway? I
would assume more common than a zImage would be some kind of special
compressed image somehow since flash would be at a premium... you
don't want to bulk your kernel up with 64kb of U-Boot SPL or so, or
even anything smaller than that. In this case, since surely Cortex-M
boots up in a more amenable state to loading kernels from flash (or
flexram or flexnvm or whatever the other manufacturers call it, and
all the docs say you can run pretty much C code from first instruction
instead of the assembler headers usually setting up exception vectors)
by just decompressing themselves automatically anyway. There, you
would not need the ARM code at all.

In the case where you'd rather run a bootloader and run a kernel from
removable storage or over USB or ethernet, you're stuck with an
external bootloader like U-Boot, and the compilation of both is going
to be controlled, one would hope; in this case, you'd configure your
loader for Thumb and your kernel for Thumb.

There's possibly some use in this, not a lot of use, but at least you
could guarantee your backtrace at early boot would be the same on M4
and A9 if it never swapped in and out of ARM mode just to execute
Thumb code exclusively from U-Boot through to Linux. Maybe that counts
for some people.. I personally like developing code on faster
processors before putting them on the slower ones, and the fact the
ISA is tantamount to identical is one of the great reasons to use the
M4..

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From sshtylyov at mvista.com  Mon Aug  6 15:05:07 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Mon, 06 Aug 2012 23:05:07 +0400
Subject: [PATCH] initramfs: handle trailing junk after valid image
In-Reply-To: <20120806093251.0528E77A0D@aristotle.killerwolves.net>
References: <CAB9O=CMADa26benQCkEoLOKKTGNeExjvFeVkFe4HLVi-W=o=Jg@mail.gmail.com>,
 <501F8D75.8070108@killerwolves.net>
 <20120806093251.0528E77A0D@aristotle.killerwolves.net>
Message-ID: <50201563.2020509@mvista.com>

Hello.

On 08/06/2012 01:32 PM, Ben Peddell wrote:

> The initramfs handling since commit df37bd15 has been rejecting

   Please also specify the summary of that commit in parens.

> valid images that have garbage after them.  For example, on an
> architecture where the initramfs address and size are specified
> as a kernel parameter (specifically unicore32 and arm), specifying
> e.g. initrd=0x01000000,4M will not work unless the image is padded
> with nulls to 4MiB.  This is unlikely to occur if the user is using
> this parameter to work around a bug in the bootloader.

   You didn't sign off the patchs, so it can't br applied.

WBR, Sergei




From linux at arm.linux.org.uk  Mon Aug  6 15:08:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 Aug 2012 20:08:56 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
Message-ID: <20120806190856.GA1120@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 01:40:26PM -0500, Matt Sealey wrote:
> Maybe we could implement a shiny new zImage magic value, I'm not sure
> if 0x016f2818 might have some sentimental value, but there's nothing
> to say that 0x016f2819 wouldn't also be valid and indicate that it's
> an ARM zImage with a Thumb2 entrypoint?

No.  That magic value is a bloody pain in the backside from my point
of view.  I've had soo many problems with it with boot loaders its
untrue.

For example, the Skiff (SA110 platform produced by Compaq) using
bootldr.  It detects the value in the kernel image after loading
the kernel at 0x8000 into RAM, and then proceeds to move the entire
kernel image to RAM location 0, and then calls it at 0x8000 !

Naturally, that action corrupts the ATAG list etc.

To work around that, I've ended up doing some weird and wonderful
tricks like pre-pending 32K of zeros, and copying the first 128
bytes of the kernel image to the start of the image file to fool
the boot loader.  Still results in a corrupted ATAG list but it is
bootable.

There's other boot loaders around too which change their behaviour
in weird and wonderful ways depending on magic values in the loaded
image file.

What this all means is that stuff like this is at the mercy of the
boot loader folk, and when problems happen, it's hard to work around
them, because you have no way to tell the boot loader to do something
different.

Instead, lets not continue this broken idea.  Instead, let's be able
to _tell_ the boot loader what we want it to do, rather than have it
magically decipher what _it_ thinks might be a good idea to do.


From matt at genesi-usa.com  Mon Aug  6 15:30:48 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 14:30:48 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120806190856.GA1120@n2100.arm.linux.org.uk>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
Message-ID: <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>

On Mon, Aug 6, 2012 at 2:08 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 06, 2012 at 01:40:26PM -0500, Matt Sealey wrote:
>> Maybe we could implement a shiny new zImage magic value, I'm not sure
>> if 0x016f2818 might have some sentimental value, but there's nothing
>> to say that 0x016f2819 wouldn't also be valid and indicate that it's
>> an ARM zImage with a Thumb2 entrypoint?
>
> No.  That magic value is a bloody pain in the backside from my point
> of view.  I've had soo many problems with it with boot loaders its
> untrue.

[snip]

> Instead, lets not continue this broken idea.  Instead, let's be able
> to _tell_ the boot loader what we want it to do, rather than have it
> magically decipher what _it_ thinks might be a good idea to do.

Okay, so how about we just append an ELF header to the front of the
image so the entry point, and the architecture, instruction
set, ABI etc. is well defined in an industry standard manner?

e_entry would then have the LSB set which indicates the entry is
Thumb.. or not :)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From ohad at wizery.com  Mon Aug  6 15:32:25 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Mon, 6 Aug 2012 22:32:25 +0300
Subject: [PATCH 1/1] remoteproc: extend customized fw loader to cover
 request and release
In-Reply-To: <CAEvN+1h5dVxX74YtBNwjiqzZNrpK56jBw9TaJjszf_-E3DY2gw@mail.gmail.com>
References: <1344237865-32491-1-git-send-email-roylee17@gmail.com>
 <CAK=WgbbBHspN_LTUXH1kUugH8-Nr-G=p-G3Wj60tAmrqqfakmg@mail.gmail.com>
 <CAEvN+1h5dVxX74YtBNwjiqzZNrpK56jBw9TaJjszf_-E3DY2gw@mail.gmail.com>
Message-ID: <CAK=WgbbaRMf+-1cS8E+8eK-X=571-nO1ot1ywEP3=-homfMWhg@mail.gmail.com>

Hi Roy,

On Mon, Aug 6, 2012 at 7:43 PM, Tzu-Jung Lee <roylee17 at gmail.com> wrote:
> That's what I'm trying to do, and it has two things needs to be address.
>
>   1)  Make the firmware loading step "optional" in the booting process.
>
>   2)  Allow the remoteproc use an customized handler to get the resource table.

Before we start digging into this, can you please tell which platform
are you working with ? is it upstream yet ?

Last we talked you couldn't yet disclose the platform identity. If
it's not upstream yet, we might prefer to postpone these discussions
until it is, to avoid unnecessary churn.

Thanks,
Ohad.


From broonie at opensource.wolfsonmicro.com  Mon Aug  6 15:37:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 20:37:34 +0100
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
Message-ID: <20120806193734.GA16199@opensource.wolfsonmicro.com>

On Mon, Aug 06, 2012 at 01:09:26PM -0500, Matt Sealey wrote:

> So that needs to stay, the issue here is why did nobody catch
> ssi-fiq.S breaking in testing MX51
> Babbage and building a Thumb2 kernel, for example? Why did nobody
> notice it was building when
> configuring for MX3/5/6 boards (which do actually have working SSI and
> DMA, as you assume, and
> do not need this code, nor build the imx-pcm-dma-fiq part of the
> driver anyway)? I'm willing to fix all
> of the above, but if there's an obvious deficiency in testing at some
> point we need to fix that too..

As far as I can tell nobody's really running much up to date mainline on
older i.MX processors, all the work is going on the new stuff and most
of the board are on either vendor BSPs or older kernels.


From festevam at gmail.com  Mon Aug  6 15:38:25 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 6 Aug 2012 16:38:25 -0300
Subject: [PATCH 1/1] mx27_3ds: Add sound support
In-Reply-To: <501FD389.1050105@gmail.com>
References: <1344258447-6162-1-git-send-email-gcembed@gmail.com>
 <CAOMZO5B9ZmTHrYjVc5a7j=uUgUEyfDva54cKxBP3UeCYZsUWRw@mail.gmail.com>
 <501FD389.1050105@gmail.com>
Message-ID: <CAOMZO5C-h214dtpRx6n13=6i2M+epebOeyrctr6zsApUtTgeBg@mail.gmail.com>

Ga?tan,

On Mon, Aug 6, 2012 at 11:24 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
> Hi Fabio,
> Sorry, I have missed your patch in my email archive. I didn't search the
> right keywords.
> I applied your [patch 1/2] (2/2 is already merged) but I have same effect. I
> use aplay with file k3b_error1.wav (Unsigned 8 bit, Rate 8000 Hz, Mono) and
> alsa/Front_Left.wav (Signed 16 bit Little Endian, Rate 48000 Hz, Mono). Two
> sounds are played too fast.
> It is maybe a bad configuration of Alsa (but this is working with kernel
> 2.6.22 from Freescale).

I have just sent the following patch to the alsa-list which fixes this
mono playback issue.

Regards,

Fabio Estevam

>From bc46087110bd48a41f1f7dcb826853349662c766 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam at freescale.com>
Date: Mon, 6 Aug 2012 16:30:51 -0300
Subject: [PATCH] ASoC: imx-ssi: Fix mono playback

Currently mono playback is played on a faster rate.

Adjust channels_min to 2 channels in order to play it back correctly.

Reported-by: Ga?tan Carlier <gcembed at gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 sound/soc/fsl/imx-ssi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index 28dd76c..c42df31 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -380,7 +380,7 @@ static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
 static struct snd_soc_dai_driver imx_ssi_dai = {
 	.probe = imx_ssi_dai_probe,
 	.playback = {
-		.channels_min = 1,
+		.channels_min = 2,
 		.channels_max = 2,
 		.rates = SNDRV_PCM_RATE_8000_96000,
 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
-- 
1.7.1


From linux at arm.linux.org.uk  Mon Aug  6 15:40:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 6 Aug 2012 20:40:16 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
Message-ID: <20120806194016.GB1120@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 02:30:48PM -0500, Matt Sealey wrote:
> On Mon, Aug 6, 2012 at 2:08 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Mon, Aug 06, 2012 at 01:40:26PM -0500, Matt Sealey wrote:
> >> Maybe we could implement a shiny new zImage magic value, I'm not sure
> >> if 0x016f2818 might have some sentimental value, but there's nothing
> >> to say that 0x016f2819 wouldn't also be valid and indicate that it's
> >> an ARM zImage with a Thumb2 entrypoint?
> >
> > No.  That magic value is a bloody pain in the backside from my point
> > of view.  I've had soo many problems with it with boot loaders its
> > untrue.
> 
> [snip]
> 
> > Instead, lets not continue this broken idea.  Instead, let's be able
> > to _tell_ the boot loader what we want it to do, rather than have it
> > magically decipher what _it_ thinks might be a good idea to do.
> 
> Okay, so how about we just append an ELF header to the front of the
> image so the entry point, and the architecture, instruction
> set, ABI etc. is well defined in an industry standard manner?
> 
> e_entry would then have the LSB set which indicates the entry is
> Thumb.. or not :)

No.  Take a moment to think about what you're saying.  Are you really
saying no to the single kernel image project?

Because anything that involves wrapping the kernel up in an "industry
standard manner" like an ELF header places fixed addresses (like the
entry point) into the kernel, and then we're back to the same problem
that every SoC vendor places their RAM at different places in the
system memory map.

No.  Can't do that.  Sorry.


From swarren at wwwdotorg.org  Mon Aug  6 15:42:21 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 06 Aug 2012 13:42:21 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <50201E1D.5060200@wwwdotorg.org>

On 07/26/2012 01:55 PM, Thierry Reding wrote:
> This patch series adds support for device tree based probing of the PCIe
> controller found on Tegra SoCs.

Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed that
PCIe doesn't work on TrimSlice when booting use device tree. I think I
found the cause, and I can't see why the same problem doesn't affect
this series. Perhaps you can enlighten me?

When booting TrimSlice (or Harmony) using board files, Tegra's PCIe is
initialized using a subsys_initcall to tegra_pcie_init() directly (or
for Harmony to harmony_pcie_init() which then calls tegra_pcie_init()).

The final thing tegra_pcie_init() does is call pci_common_init(). This
calls pcibios_init_hw() which calls hw->scan() which calls
pci_scan_root_bus() which adds a device object for each device on the
PCIe bus. However, since this happens very early in the boot sequence, I
believe the enumerated PCIe devices don't immediately get probed.
Instead, control gets returned to pci_common_init() which I believe then
calls pci_bus_assign_resources() which actually sets up the resources
for those devices. Later, the PCIe devices actually get probed, and
everything works.

However, when booting using device tree, with the code currently in
v3.6-rc1, tegra_pcie_init() is called late in the boot sequence, and so
in the sequence described above, as soon as pci_scan_root_bus() adds a
device, it gets probed, before the device object's resources have been
set up, which results in the following failure:

PCI: Device 0000:01:00.0 not available because of resource collisions

... because of the following code in pcibios_enable_device():

> 	for (idx = 0; idx < 6; idx++) {
> 		/* Only set up the requested stuff */
> 		if (!(mask & (1 << idx)))
> 			continue;
> 
> 		r = dev->resource + idx;
> 		if (!r->start && r->end) {
> 			printk(KERN_ERR "PCI: Device %s not available because"
> 			       " of resource collisions\n", pci_name(dev));

Doesn't this same problem exist when instantiating the PCIe device
itself from device tree as in your patch series? If not, can you explain
why?

Now, the obvious solution in v3.6 would be to simply have
tegra_pcie_init() be called at the same early stage in the boot process
when booting using device tree as it is when booting using board files.
This works for TrimSlice.

However, on Harmony, it doesn't work, because PCIe on Harmony depends on
regulators, and the regulators are accessed using an I2C bus that is
instantiated from DT, and the instantiation of the I2C bus happens
fairly late in the boot process so can't be found early during the boot
sequence. See harmony_regulator_init() for the failing code.

Does anyone have any good ideas (small, self-contained patches) for
solving this in v3.6 in such a way that PCIe works on both TrimSlice and
Harmony?

Thanks.


From matt at genesi-usa.com  Mon Aug  6 16:00:15 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 15:00:15 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <20120806194016.GB1120@n2100.arm.linux.org.uk>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
Message-ID: <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>

On Mon, Aug 6, 2012 at 2:40 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 06, 2012 at 02:30:48PM -0500, Matt Sealey wrote:
>> On Mon, Aug 6, 2012 at 2:08 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>> > On Mon, Aug 06, 2012 at 01:40:26PM -0500, Matt Sealey wrote:
>> >> Maybe we could implement a shiny new zImage magic value, I'm not sure
>> >> if 0x016f2818 might have some sentimental value, but there's nothing
>> >> to say that 0x016f2819 wouldn't also be valid and indicate that it's
>> >> an ARM zImage with a Thumb2 entrypoint?
>> >
>> > No.  That magic value is a bloody pain in the backside from my point
>> > of view.  I've had soo many problems with it with boot loaders its
>> > untrue.
>>
>> [snip]
>>
>> > Instead, lets not continue this broken idea.  Instead, let's be able
>> > to _tell_ the boot loader what we want it to do, rather than have it
>> > magically decipher what _it_ thinks might be a good idea to do.
>>
>> Okay, so how about we just append an ELF header to the front of the
>> image so the entry point, and the architecture, instruction
>> set, ABI etc. is well defined in an industry standard manner?
>>
>> e_entry would then have the LSB set which indicates the entry is
>> Thumb.. or not :)
>
> No.  Take a moment to think about what you're saying.  Are you really
> saying no to the single kernel image project?
>
> Because anything that involves wrapping the kernel up in an "industry
> standard manner" like an ELF header places fixed addresses (like the
> entry point) into the kernel, and then we're back to the same problem
> that every SoC vendor places their RAM at different places in the
> system memory map.
>
> No.  Can't do that.  Sorry.

Right now there's already a fixed entry point - ARM kernels are fixed
entry point of relative 0 to the start of the loaded image. Okay, so
we can't format a totally valid ELF header, but in the event that we
want to encode all this information yet again, why reinvent the wheel?

Just reserve your bytes or so at the front of the image for head.S,
and at the correct point (right where the zImage magic would be) sits
an ELF magic and the rest of the ELF header. I realize you'd need to
write another rudimentary ELF parser for U-Boot and one for very early
init in the kernel to get the jump right, therefore reinventing the
wheel in some respects, but I'm curious how anyone could do any better
with another custom image header format. It's somewhat this way anyway
(to my last recollection vmlinux is ELF so you can get gdb to load it)
and the only better thing I can think of is to use PECOFF, because
then it'd automatically be UEFI compatible (and we can all stop using
grub-efi and directly boot a kernel).

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From r.schwebel at pengutronix.de  Mon Aug  6 16:16:09 2012
From: r.schwebel at pengutronix.de (Robert Schwebel)
Date: Mon, 6 Aug 2012 22:16:09 +0200
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120806193734.GA16199@opensource.wolfsonmicro.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
Message-ID: <20120806201609.GX25644@pengutronix.de>

On Mon, Aug 06, 2012 at 08:37:34PM +0100, Mark Brown wrote:
> As far as I can tell nobody's really running much up to date mainline
> on older i.MX processors, all the work is going on the new stuff and
> most of the board are on either vendor BSPs or older kernels.

That's not true; we still run MX25, MX27, MX35, MX28 on mainline in
active projects.

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From swarren at wwwdotorg.org  Mon Aug  6 16:19:33 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 06 Aug 2012 14:19:33 -0600
Subject: [PATCH v4 0/6] Port Tegra to generic clk framework
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <502026D5.9060008@wwwdotorg.org>

On 08/06/2012 12:27 AM, Prashant Gaikwad wrote:
> This patch set ports Tegra clock code to generic clock framework.

Thanks. I've applied the series.


From grinberg at compulab.co.il  Mon Aug  6 16:22:15 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Mon,  6 Aug 2012 23:22:15 +0300
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce time
 for ads7846"
In-Reply-To: <876298iv9s.fsf@ti.com>
References: <876298iv9s.fsf@ti.com>
Message-ID: <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>

1) The above commit introduced a common ->get_pendown_state() function
into the generic code, but that function was board-specific for the
OMAP3EVM and thus broke most other boards using this code.

2) The above commit was mis-merged introducing another bug which
prevents the ads7846 driver probe function to succeed.
The omap_ads7846_init() function frees the pendown GPIO in case there is
no ->get_pendown_state() function set by the caller (board specific
code), so it can be requested later by the ads7846 driver.
The above commit add a common ->get_pendown_state() function without
removing the gpio_free() call and thus once the ads7846 driver tries
to use the pendown GPIO, it crashes as the pendown GPIO has not been
requested.

3) The above commit introduces NO new functionality as
get_pendown_state() function is already implemented in a suitable way by
the ads7846 driver and the debounce time handling has already been
fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).

This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.

Conflicts:
	arch/arm/mach-omap2/common-board-devices.c

Solved by taking the working version prior to the above commit.

Cc: Zumeng Chen <zumeng.chen at windriver.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
Kevin, sorry for the late reply.
How about the above commit message and the below patch?

The patch applies cleanly to Tony's master branch (6 Aug 2012)
or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
after resetting two top most commits.

This patch has been tested on both above branches on cm-t3730.
Any other board tested will be greately appreciated.

Also, if after all said in the commit message, you still don't
want to revert the original patch, feel free to post your thoughts.

 arch/arm/mach-omap2/board-omap3evm.c       |    1 +
 arch/arm/mach-omap2/common-board-devices.c |   11 -----------
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 3 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0..0d362e9 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -58,6 +58,7 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
 
+#define OMAP3_EVM_TS_GPIO	175
 #define OMAP3_EVM_EHCI_VBUS	22
 #define OMAP3_EVM_EHCI_SELECT	61
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 1473474..c187586 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
 	.turbo_mode	= 0,
 };
 
-/*
- * ADS7846 driver maybe request a gpio according to the value
- * of pdata->get_pendown_state, but we have done this. So set
- * get_pendown_state to avoid twice gpio requesting.
- */
-static int omap3_get_pendown_state(void)
-{
-	return !gpio_get_value(OMAP3_EVM_TS_GPIO);
-}
-
 static struct ads7846_platform_data ads7846_config = {
 	.x_max			= 0x0fff,
 	.y_max			= 0x0fff,
@@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
 	.debounce_rep		= 1,
 	.gpio_pendown		= -EINVAL,
 	.keep_vref_on		= 1,
-	.get_pendown_state	= &omap3_get_pendown_state,
 };
 
 static struct spi_board_info ads7846_spi_board_info __initdata = {
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 4c4ef6a..a0b4a428 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -4,7 +4,6 @@
 #include "twl-common.h"
 
 #define NAND_BLOCK_SIZE	SZ_128K
-#define OMAP3_EVM_TS_GPIO	175
 
 struct mtd_partition;
 struct ads7846_platform_data;
-- 
1.7.3.4



From matt at genesi-usa.com  Mon Aug  6 16:39:50 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 15:39:50 -0500
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120806201609.GX25644@pengutronix.de>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
Message-ID: <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>

On Mon, Aug 6, 2012 at 3:16 PM, Robert Schwebel
<r.schwebel at pengutronix.de> wrote:
> On Mon, Aug 06, 2012 at 08:37:34PM +0100, Mark Brown wrote:
>> As far as I can tell nobody's really running much up to date mainline
>> on older i.MX processors, all the work is going on the new stuff and
>> most of the board are on either vendor BSPs or older kernels.
>
> That's not true; we still run MX25, MX27, MX35, MX28 on mainline in
> active projects.

I think Shawn Guo (FSL/Linaro) would also disagree, since he's just
posted a large amount of MXS patches to fix up the board for device
trees, and Arnd is pulling them.

Work is ongoing, it would be awful to delete something people really
relied on or were in progress fixing (ahem). If they get up to audio
in the near future the audio FIQ stuff would just end up being
resubmitted almost verbatim... that seems like unnecessary churn.

As far as I know, the FIQ usage is quite valid for the processor it
needs to run on (MX21/27/28, right?) in the modes it runs in (AC97 on
these processors, and maybe MX35 too), and I'm just trying to figure
out what the steps are for

* making sure it doesn't get built for architectures/variants it's
certainly NOT required on (imx_v6_v7_defconfig, if it actually enabled
audio, that is - in fact, audio should be enabled as more one of the
boards supported defines it in the device tree) which would amount to
two seperate patches, one for the defconfig, one for the CONFIG item.

I did note that SND_SOC_EUKREA_TLV320 enables FIQ but it also depends
on MX51 which makes me think this need to be split, too, so that MX51
boards don't have it but MX2/MX3 do.

* if it is built then it's built as ARM code (redundant, as previously
stated, but would have stopped me from swearing at my build box when I
hit the issue yet again) which could be a patch or could be ignored.
I'd rather discuss this here than clutter the ML with several respins
of a patch, let's get an opinion first - to .arm or no to .arm?

* make sure there's no weird FIQ stuff floating around that has so far
relied on SND_SOC_IMX_PCM_FIQ doing select FIQ before I make it not
compile in for other boards (since otherwise no i.MX processor selects
FIQ if they're not using that driver, it could be simply coincidence
nobody noticed). I don't want to be the one submitting a patch I can't
test which mysteriously breaks every MX28 on the planet (since Rob,
Shawn, Sascha might be the ones swearing at me instead)

* making sure someone's actually testing audio as above... and
where/if/when the MX28 audio stuff is going in the future und so
weiter..

I guess I need Sascha to pipe up and tell me what the code is needed
for exactly again.. and someone to test the result of the changes..

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From ccross at google.com  Mon Aug  6 16:41:06 2012
From: ccross at google.com (Colin Cross)
Date: Mon, 6 Aug 2012 13:41:06 -0700
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>
Message-ID: <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>

On Wed, Aug 1, 2012 at 2:42 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Stephen Boyd wrote:
>>
>> On 07/10/12 23:34, Kukjin Kim wrote:
>> > Stephen Boyd wrote:
>> >> Great. Kukjin Kim, can exynos use SGI0? It looks like exynos is the
>> only
>> >> one left to move to SGI0.
>> >>
>> > Yeah, EXYNOS can use SGI0 instead of SGI1 :)
>> >
>> >
>>
>> Russell, can we apply something like this?
>>
> Please feel free to add my ack on following change.
>
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>
>

When testing coupled cpuidle on Exynos5, I found that sending an IPI
does not successfully wake up CPU1.  CPU1 is in a wfe with interrupts
masked, not a wfi, so an interrupt is not able to wake it up.  It
tends to wake up anyways because the next time a spin lock is
unlocked, often during a timer interrupt on CPU0, CPU0 executes an sev
which wakes up CPU1.  You can see that the IPI is unnecessary by
removing the gic_raise_softirq and replacing it with dsb_sev().


From khilman at ti.com  Mon Aug  6 16:52:18 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 06 Aug 2012 13:52:18 -0700
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce
 time for ads7846"
In-Reply-To: <1344284535-16717-1-git-send-email-grinberg@compulab.co.il> (Igor
 Grinberg's message of "Mon, 6 Aug 2012 23:22:15 +0300")
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <871ujj7ngd.fsf@ti.com>

Igor Grinberg <grinberg at compulab.co.il> writes:

> 1) The above commit introduced a common ->get_pendown_state() function
> into the generic code, but that function was board-specific for the
> OMAP3EVM and thus broke most other boards using this code.
>
> 2) The above commit was mis-merged introducing another bug which
> prevents the ads7846 driver probe function to succeed.
> The omap_ads7846_init() function frees the pendown GPIO in case there is
> no ->get_pendown_state() function set by the caller (board specific
> code), so it can be requested later by the ads7846 driver.
> The above commit add a common ->get_pendown_state() function without
> removing the gpio_free() call and thus once the ads7846 driver tries
> to use the pendown GPIO, it crashes as the pendown GPIO has not been
> requested.
>
> 3) The above commit introduces NO new functionality as
> get_pendown_state() function is already implemented in a suitable way by
> the ads7846 driver and the debounce time handling has already been
> fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).
>
> This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.
>
> Conflicts:
> 	arch/arm/mach-omap2/common-board-devices.c
>
> Solved by taking the working version prior to the above commit.
>
> Cc: Zumeng Chen <zumeng.chen at windriver.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
> Kevin, sorry for the late reply.
> How about the above commit message and the below patch?
>
> The patch applies cleanly to Tony's master branch (6 Aug 2012)
> or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
> after resetting two top most commits.

Now that v3.6-rc1 is out, it should probalby be applied on top of -rc1.
I've taken care of that and tested as well.

> This patch has been tested on both above branches on cm-t3730.
> Any other board tested will be greately appreciated.
>
> Also, if after all said in the commit message, you still don't
> want to revert the original patch, feel free to post your thoughts.

After all the digging I did, I agree that the revert is the best
solution.  

While it's a slightly different problem/bug, I think the gpio_free() in
common-board-devices.c should still be unconditonal since the
gpio_request() is now unconditional.  That can be a separate patch though.

Acked-by: Kevin Hilman <khilman at ti.com>
Tested-by: Kevin Hilman <khilman at ti.com>

Tested on 3430/n900, 3530/Overo, 3730/Overo STORM, 3730/BB-xM.

The Overo boards were the ones that were crashing due to this bug since
the pendown GPIO was the only one used in the bank.

Tony, can you queue this up for v3.6-rc?  I have a version in my
for_3.6/fixes/ads7846-2 branch with the tags above applied, based on v3.6-rc1.

Thanks

Kevin

>  arch/arm/mach-omap2/board-omap3evm.c       |    1 +
>  arch/arm/mach-omap2/common-board-devices.c |   11 -----------
>  arch/arm/mach-omap2/common-board-devices.h |    1 -
>  3 files changed, 1 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
> index ef230a0..0d362e9 100644
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -58,6 +58,7 @@
>  #include "hsmmc.h"
>  #include "common-board-devices.h"
>  
> +#define OMAP3_EVM_TS_GPIO	175
>  #define OMAP3_EVM_EHCI_VBUS	22
>  #define OMAP3_EVM_EHCI_SELECT	61
>  
> diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
> index 1473474..c187586 100644
> --- a/arch/arm/mach-omap2/common-board-devices.c
> +++ b/arch/arm/mach-omap2/common-board-devices.c
> @@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
>  	.turbo_mode	= 0,
>  };
>  
> -/*
> - * ADS7846 driver maybe request a gpio according to the value
> - * of pdata->get_pendown_state, but we have done this. So set
> - * get_pendown_state to avoid twice gpio requesting.
> - */
> -static int omap3_get_pendown_state(void)
> -{
> -	return !gpio_get_value(OMAP3_EVM_TS_GPIO);
> -}
> -
>  static struct ads7846_platform_data ads7846_config = {
>  	.x_max			= 0x0fff,
>  	.y_max			= 0x0fff,
> @@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
>  	.debounce_rep		= 1,
>  	.gpio_pendown		= -EINVAL,
>  	.keep_vref_on		= 1,
> -	.get_pendown_state	= &omap3_get_pendown_state,
>  };
>  
>  static struct spi_board_info ads7846_spi_board_info __initdata = {
> diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
> index 4c4ef6a..a0b4a428 100644
> --- a/arch/arm/mach-omap2/common-board-devices.h
> +++ b/arch/arm/mach-omap2/common-board-devices.h
> @@ -4,7 +4,6 @@
>  #include "twl-common.h"
>  
>  #define NAND_BLOCK_SIZE	SZ_128K
> -#define OMAP3_EVM_TS_GPIO	175
>  
>  struct mtd_partition;
>  struct ads7846_platform_data;


From khilman at ti.com  Mon Aug  6 17:31:48 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 06 Aug 2012 14:31:48 -0700
Subject: DSS and USBHOST powerdomains not entering low-power states on
 37xx EVM
In-Reply-To: <alpine.DEB.2.00.1208031355450.28888@utopia.booyaka.com> (Paul
 Walmsley's message of "Fri, 3 Aug 2012 14:05:55 -0600 (MDT)")
References: <alpine.DEB.2.00.1208031355450.28888@utopia.booyaka.com>
Message-ID: <877gtb6723.fsf@ti.com>

Hi Paul,

Paul Walmsley <paul at pwsan.com> writes:

> On v3.6-rc1 on 37xx EVM, DSS and USBHOST powerdomains aren't entering 
> low-power states.  Test log is below.

Is this only happening on this 37xx platform?    Just curious, because
it seems to be a problem on any OMAP3xxx SoC.

[...]

> # echo mem > /sys/power/state
> [   35.068359] PM: Syncing filesystems ... done.
> [   35.083038] Freezing user space processes ... (elapsed 0.00 seconds) 
> done.
> [   35.090698] Freezing remaining freezable tasks ... (elapsed 0.02 
> seconds) done.
> [   35.122833] Suspending console(s) (use no_console_suspend to debug)
> [   35.144409] PM: suspend of devices complete after 11.260 msecs
> [   35.147369] PM: late suspend of devices complete after 2.929 msecs
> [   35.152465] PM: noirq suspend of devices complete after 5.096 msecs
> [   35.152526] Disabling non-boot CPUs ...
> [   36.958343] Successfully put all powerdomains to target state

According to the readback of prev pwrst, it seems they are hitting the
target pwrst (retention by default), so...

> [   36.960662] PM: noirq resume of devices complete after 2.166 msecs
> [   36.964050] PM: early resume of devices complete after 1.892 msecs
> [   36.973388] PM: resume of devices complete after 9.185 msecs
> [   37.025207] Restarting tasks ... done.
> # cat  /debug/pm_debug/count
> usbhost_pwrdm 
> (ON),OFF:0,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> sgx_pwrdm (OFF),OFF:1,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> core_pwrdm 
> (ON),OFF:0,RET:1,INA:0,ON:2,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0
> per_pwrdm (ON),OFF:0,RET:1,INA:0,ON:2,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> dss_pwrdm (ON),OFF:0,RET:0,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> cam_pwrdm (RET),OFF:0,RET:1,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> neon_pwrdm (ON),OFF:0,RET:673,INA:0,ON:674,RET-LOGIC-OFF:0
> mpu_pwrdm (ON),OFF:0,RET:673,INA:0,ON:674,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0
> iva2_pwrdm (RET),OFF:0,RET:1,INA:0,ON:1,RET-LOGIC-OFF:0,RET-MEMBANK1-OFF:0,RET-MEMBANK2-OFF:0,RET-MEMBANK3-OFF:0,RET-ME
> MBANK4-OFF:0
> usbhost_clkdm->usbhost_pwrdm (1)
> sgx_clkdm->sgx_pwrdm (0)
> per_clkdm->per_pwrdm (22)
> cam_clkdm->cam_pwrdm (0)
> dss_clkdm->dss_pwrdm (1)
> d2d_clkdm->core_pwrdm (0)
> iva2_clkdm->iva2_pwrdm (0)
> mpu_clkdm->mpu_pwrdm (0)
> core_l4_clkdm->core_pwrdm (24)
> core_l3_clkdm->core_pwrdm (4)
> neon_clkdm->neon_pwrdm (0)

...it must be the usecounts that are not being updated.  This seems to
be a side effect of the pre/post transition optimization I did.  A quick
hack seems to indicate that that's indeed the case[1].  By default,
omap_sram_idle() is now only calling the pre/post callbacks for MPU,
NEON, PER, and CORE, and only if those domains are transitioning, so any
other domains not explicitly managed by the idle path have lots their
usecounting.  Oops.

I guess Tero's usecounting series should fix this up.

Kevin

[1] 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..d87416f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -70,6 +70,7 @@ void (*omap3_do_wfi_sram)(void);
 
 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
+static struct powerdomain *dss_pwrdm, *usbhost_pwrdm;
 
 static void omap3_core_save_context(void)
 {
@@ -393,7 +394,11 @@ static int omap3_pm_suspend(void)
 
 	omap3_intc_suspend();
 
+	pwrdm_pre_transition(dss_pwrdm);
+	pwrdm_pre_transition(usbhost_pwrdm);
 	omap_sram_idle();
+	pwrdm_post_transition(usbhost_pwrdm);
+	pwrdm_post_transition(dss_pwrdm);
 
 restore:
 	/* Restore next_pwrsts */
@@ -718,6 +723,8 @@ int __init omap3_pm_init(void)
 	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 	per_pwrdm = pwrdm_lookup("per_pwrdm");
 	core_pwrdm = pwrdm_lookup("core_pwrdm");
+	dss_pwrdm = pwrdm_lookup("dss_pwrdm");
+	usbhost_pwrdm = pwrdm_lookup("usbhost_pwrdm");
 
 	neon_clkdm = clkdm_lookup("neon_clkdm");
 	mpu_clkdm = clkdm_lookup("mpu_clkdm");


From matt at genesi-usa.com  Mon Aug  6 17:31:50 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 16:31:50 -0500
Subject: [PATCH 2/2] ARM i.MX5: Hard reset the IPU during startup
In-Reply-To: <20120605110834.GQ30400@pengutronix.de>
References: <1338888630-25930-1-git-send-email-s.hauer@pengutronix.de>
 <1338888630-25930-3-git-send-email-s.hauer@pengutronix.de>
 <20429.57208.228315.164637@ipc1.ka-ro> <20120605110834.GQ30400@pengutronix.de>
Message-ID: <CAKGA1bkA3eEHn4sM277mzcRT5OUyipW18-k-X0nK+T9rrotJNw@mail.gmail.com>

On Tue, Jun 5, 2012 at 6:08 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Tue, Jun 05, 2012 at 12:29:12PM +0200, Lothar Wa?mann wrote:
>> Hi,
>>
>> Sascha Hauer writes:
>> >
>> How would you implement a seamless transition from a boot logo to the
>> application display when resetting the IPU during startup?
>
> I usually say to Robert: Make the bootloader fast enough so that nobody
> misses a splash from the bootloader. Robert is never happy with that
> answer...
>
> Is there any mainline compatible way to take over an initialized
> graphics core?

No.

There used to be an ATAG for finding the linear framebuffer and it's
details but it got removed. This
was from a long forgotten time when you could initialize a VGA
graphics card and never care that
it had an interrupt or not, since it never got used for your average,
simple linear framebuffer operations.
A device tree would be able to define (based on seeding that
information from the bootloader) this too,
and we have sample code of this working on a PPC system (Pegasos II)
which would initialize a
VGA graphics card using x86 emulation, set up the framebuffer using
faked BIOS calls and put that
information in the device tree for Linux to pick up using ofwfb.

Lothar;

The problem is on the IPU at least, having a running IDMAC channel
kind of means breaking all kinds of
good behavior in the transition between bootloader and kernel -
usually you can assume that
interrupts and caches are disabled, all DMA operations are halted/torn
down, and strange effects
happen obviously if this is not exactly true (on Pegasos II we had an
old firmware which accidentally
left USB running, and when Linux started.. all hell broke loose. At
random.). It would also assume that
the framebuffer memory was preserved, that the OS booting knew how to
use that exact framebuffer
format,

So, unless your LCDC is extremely dumb, and your OS extremely smart,
it can't be done. Robert and
Lothar, you will have to live with it. What some people do is get
clever inside the kernel, i.e. boot your
kernel as fast as possible as you said and then use fancy features
like precompiling the splash image
into the kernel, then using DMA to fill the screen buffer with data so
you have a working splash extremely
early in boot - and while the kernel is probing devices after the bare
minimum you architected, the DMA
unit is putting your penguin on the screen. There's no reason to
expect that display has to be configured
after USB, for example, and you can make your "real" display driver
hand-off much easier between initial
kernel setup and real driver inside the kernel, than trying to handle
it across the loader/kernel transitition.
I saw an article on this (may have been published and peer reviewed,
but also had a youtube video.. :)
that did this exact thing, it was a response to all those "5 second
boot" articles, on how to do it properly
on embedded systems. I'll see if I can find it.

There are plenty of things that you could do in the bootloader like
using DMA for instance (why not
use SDMA for relocation of the kernel if required?) in ways other than
accelerating the disk accesses,
and the same stuff can be done in the kernel to get to the "put a nice
screen up" stage even faster.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From swarren at wwwdotorg.org  Mon Aug  6 17:32:12 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 Aug 2012 15:32:12 -0600
Subject: [PATCH 1/3] ARM: tegra: remove board (but not DT) support for
 TrimSlice
Message-ID: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

TrimSlice can be booted using device tree with equal functionality as
when booted using a board file. Remove the board file since it's no
longer needed.

One special-case is still left in board-dt-tegra20.c, since the Tegra
PCIe driver doesn't support device tree yet. This logic is now enabled
by CONFIG_TEGRA_PCI rather than via CONFIG_MACH_TRIMSLICE. The extra
cases where it's enabled (.configs which did not enable TrimSlice
support) shouldn't impact much since the amount of code is tiny.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
These patches might need some slight context updates depending on if/how
board-dt-tegra20.c gets updated in v3.6-rc2 to fix the Trimslice PCIe
issue. Perhaps a simple merge will work for that anyway. Either way, the
basic concept of these patches is going to stand...

 arch/arm/mach-tegra/Kconfig                  |    7 -
 arch/arm/mach-tegra/Makefile                 |    3 -
 arch/arm/mach-tegra/board-dt-tegra20.c       |    6 +-
 arch/arm/mach-tegra/board-trimslice-pinmux.c |  155 ----------------------
 arch/arm/mach-tegra/board-trimslice.c        |  183 --------------------------
 arch/arm/mach-tegra/board-trimslice.h        |   30 ----
 6 files changed, 2 insertions(+), 382 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/board-trimslice-pinmux.c
 delete mode 100644 arch/arm/mach-tegra/board-trimslice.c
 delete mode 100644 arch/arm/mach-tegra/board-trimslice.h

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9077aaa..41bc73c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -72,13 +72,6 @@ config MACH_PAZ00
        help
          Support for the Toshiba AC100/Dynabook AZ netbook
 
-config MACH_TRIMSLICE
-       bool "TrimSlice board"
-       depends on ARCH_TEGRA_2x_SOC
-       select TEGRA_PCI
-       help
-         Support for CompuLab TrimSlice platform
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303..88ddb75 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -33,6 +33,3 @@ obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
 
 obj-$(CONFIG_MACH_PAZ00)		+= board-paz00.o
 obj-$(CONFIG_MACH_PAZ00)		+= board-paz00-pinmux.o
-
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index b4e7cc1..422e89e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -96,16 +96,16 @@ static void __init tegra_dt_init(void)
 				tegra20_auxdata_lookup, NULL);
 }
 
-#ifdef CONFIG_MACH_TRIMSLICE
 static void __init trimslice_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
 	int ret;
 
 	ret = tegra_pcie_init(true, true);
 	if (ret)
 		pr_err("tegra_pci_init() failed: %d\n", ret);
-}
 #endif
+}
 
 #ifdef CONFIG_MACH_HARMONY
 static void __init harmony_init(void)
@@ -135,9 +135,7 @@ static struct {
 	char *machine;
 	void (*init)(void);
 } board_init_funcs[] = {
-#ifdef CONFIG_MACH_TRIMSLICE
 	{ "compulab,trimslice", trimslice_init },
-#endif
 #ifdef CONFIG_MACH_HARMONY
 	{ "nvidia,harmony", harmony_init },
 #endif
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
deleted file mode 100644
index 7b39511..0000000
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice-pinmux.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-
-#include "board-trimslice.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map trimslice_map[] = {
-	TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
-	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
-	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
-	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-	TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-	TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-	TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
-	TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
-	TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
-	TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
-	TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
-	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
-	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
-	TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
-	TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-	TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
-	TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
-	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
-	TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
-	TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
-	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
-	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
-	TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
-	TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
-	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
-	TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
-	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
-	TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
-	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
-	TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
-	TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
-	TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
-	TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
-	TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-	TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-	TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-	TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-	TEGRA_MAP_CONF("ck32",    none, na),
-	TEGRA_MAP_CONF("ddrc",    none, na),
-	TEGRA_MAP_CONF("pmca",    none, na),
-	TEGRA_MAP_CONF("pmcb",    none, na),
-	TEGRA_MAP_CONF("pmcc",    none, na),
-	TEGRA_MAP_CONF("pmcd",    none, na),
-	TEGRA_MAP_CONF("pmce",    none, na),
-	TEGRA_MAP_CONF("xm2c",    none, na),
-	TEGRA_MAP_CONF("xm2d",    none, na),
-	TEGRA_MAP_CONF("ls",      up,   na),
-	TEGRA_MAP_CONF("lc",      up,   na),
-	TEGRA_MAP_CONF("ld17_0",  down, na),
-	TEGRA_MAP_CONF("ld19_18", down, na),
-	TEGRA_MAP_CONF("ld21_20", down, na),
-	TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-	.maps = trimslice_map,
-	.map_count = ARRAY_SIZE(trimslice_map),
-};
-
-void trimslice_pinmux_init(void)
-{
-	tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
deleted file mode 100644
index 776aa95..0000000
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Author: Mike Rapoport <mike at compulab.co.il>
- *
- * Based on board-harmony.c
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-#include "board-trimslice.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-	{
-		.membase	= IO_ADDRESS(TEGRA_UARTA_BASE),
-		.mapbase	= TEGRA_UARTA_BASE,
-		.irq		= INT_UARTA,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-		.type		= PORT_TEGRA,
-		.handle_break	= tegra_serial_handle_break,
-		.iotype		= UPIO_MEM,
-		.regshift	= 2,
-		.uartclk	= 216000000,
-	}, {
-		.flags		= 0
-	}
-};
-
-static struct platform_device debug_uart = {
-	.name	= "serial8250",
-	.id	= PLAT8250_DEV_PLATFORM,
-	.dev	= {
-		.platform_data	= debug_uart_platform_data,
-	},
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-	.cd_gpio	= -1,
-	.wp_gpio	= -1,
-	.power_gpio	= -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-	.cd_gpio	= TRIMSLICE_GPIO_SD4_CD,
-	.wp_gpio	= TRIMSLICE_GPIO_SD4_WP,
-	.power_gpio	= -1,
-};
-
-static struct platform_device trimslice_audio_device = {
-	.name	= "tegra-snd-trimslice",
-	.id	= 0,
-};
-
-static struct platform_device *trimslice_devices[] __initdata = {
-	&debug_uart,
-	&tegra_sdhci_device1,
-	&tegra_sdhci_device4,
-	&tegra_i2s_device1,
-	&tegra_das_device,
-	&trimslice_audio_device,
-};
-
-static struct i2c_board_info trimslice_i2c3_board_info[] = {
-	{
-		I2C_BOARD_INFO("tlv320aic23", 0x1a),
-	},
-	{
-		I2C_BOARD_INFO("em3027", 0x56),
-	},
-};
-
-static void trimslice_i2c_init(void)
-{
-	platform_device_register(&tegra_i2c_device1);
-	platform_device_register(&tegra_i2c_device2);
-	platform_device_register(&tegra_i2c_device3);
-
-	i2c_register_board_info(2, trimslice_i2c3_board_info,
-				ARRAY_SIZE(trimslice_i2c3_board_info));
-}
-
-static void trimslice_usb_init(void)
-{
-	struct tegra_ehci_platform_data *pdata;
-
-	pdata = tegra_ehci1_device.dev.platform_data;
-	pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
-
-	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
-
-	platform_device_register(&tegra_ehci3_device);
-	platform_device_register(&tegra_ehci2_device);
-	platform_device_register(&tegra_ehci1_device);
-}
-
-static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
-	struct meminfo *mi)
-{
-	mi->nr_banks = 2;
-	mi->bank[0].start = PHYS_OFFSET;
-	mi->bank[0].size = 448 * SZ_1M;
-	mi->bank[1].start = SZ_512M;
-	mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
-	/* name		parent		rate		enabled */
-	{ "uarta",	"pll_p",	216000000,	true },
-	{ "pll_a",	"pll_p_out1",	56448000,	true },
-	{ "pll_a_out0",	"pll_a",	11289600,	true },
-	{ "cdev1",	NULL,		0,		true },
-	{ "i2s1",	"pll_a_out0",	11289600,	false},
-	{ NULL,		NULL,		0,		0},
-};
-
-static int __init tegra_trimslice_pci_init(void)
-{
-	if (!machine_is_trimslice())
-		return 0;
-
-	return tegra_pcie_init(true, true);
-}
-subsys_initcall(tegra_trimslice_pci_init);
-
-static void __init tegra_trimslice_init(void)
-{
-	tegra_clk_init_from_table(trimslice_clk_init_table);
-
-	trimslice_pinmux_init();
-
-	tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-	tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-	platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
-
-	trimslice_i2c_init();
-	trimslice_usb_init();
-}
-
-MACHINE_START(TRIMSLICE, "trimslice")
-	.atag_offset	= 0x100,
-	.fixup		= tegra_trimslice_fixup,
-	.map_io         = tegra_map_common_io,
-	.init_early	= tegra20_init_early,
-	.init_irq       = tegra_init_irq,
-	.handle_irq	= gic_handle_irq,
-	.timer          = &tegra_timer,
-	.init_machine   = tegra_trimslice_init,
-	.init_late	= tegra_init_late,
-	.restart	= tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
deleted file mode 100644
index 50f128d..0000000
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.h
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
-#define _MACH_TEGRA_BOARD_TRIMSLICE_H
-
-#include <mach/gpio-tegra.h>
-
-#define TRIMSLICE_GPIO_SD4_CD	TEGRA_GPIO_PP1	/* mmc4 cd */
-#define TRIMSLICE_GPIO_SD4_WP	TEGRA_GPIO_PP2	/* mmc4 wp */
-
-#define TRIMSLICE_GPIO_USB1_MODE	TEGRA_GPIO_PV2 /* USB1 mode */
-#define TRIMSLICE_GPIO_USB2_RST		TEGRA_GPIO_PV0 /* USB2 PHY reset */
-
-void trimslice_pinmux_init(void);
-
-#endif
-- 
1.7.0.4



From swarren at wwwdotorg.org  Mon Aug  6 17:32:13 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 Aug 2012 15:32:13 -0600
Subject: [PATCH 2/3] ARM: tegra: remove board (but not DT) support for Paz00
In-Reply-To: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
References: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1344288734-24131-2-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Paz00 (Toshiba AC100) can be booted using device tree with equal
functionality as when booted using a board file. Remove as much of the
board file as is possible, since it's no longer needed.

One special-case is still left in board-dt-tegra20.c, since there is no
way to create a WiFi rfkill device from device tree yet. This logic is
now enabled unconditionally rather than via CONFIG_MACH_PAZ00. The extra
cases where it's enabled (.configs which did not enable Paz00 support)
shouldn't impact much since the amount of code is tiny.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/Kconfig              |    6 -
 arch/arm/mach-tegra/Makefile             |    3 +-
 arch/arm/mach-tegra/board-dt-tegra20.c   |    4 -
 arch/arm/mach-tegra/board-paz00-pinmux.c |  156 ------------------------
 arch/arm/mach-tegra/board-paz00.c        |  192 ------------------------------
 arch/arm/mach-tegra/board-paz00.h        |   17 +---
 6 files changed, 2 insertions(+), 376 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/board-paz00-pinmux.c

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 41bc73c..f6e79ed 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -66,12 +66,6 @@ config MACH_HARMONY
        help
          Support for nVidia Harmony development platform
 
-config MACH_PAZ00
-       bool "Paz00 board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for the Toshiba AC100/Dynabook AZ netbook
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 88ddb75..1c2b473 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -31,5 +31,4 @@ obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
 obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
 obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
 
-obj-$(CONFIG_MACH_PAZ00)		+= board-paz00.o
-obj-$(CONFIG_MACH_PAZ00)		+= board-paz00-pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 422e89e..1d6c9df 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -124,12 +124,10 @@ static void __init harmony_init(void)
 }
 #endif
 
-#ifdef CONFIG_MACH_PAZ00
 static void __init paz00_init(void)
 {
 	tegra_paz00_wifikill_init();
 }
-#endif
 
 static struct {
 	char *machine;
@@ -139,9 +137,7 @@ static struct {
 #ifdef CONFIG_MACH_HARMONY
 	{ "nvidia,harmony", harmony_init },
 #endif
-#ifdef CONFIG_MACH_PAZ00
 	{ "compal,paz00", paz00_init },
-#endif
 };
 
 static void __init tegra_dt_init_late(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
deleted file mode 100644
index 6f1111b..0000000
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-paz00-pinmux.c
- *
- * Copyright (C) 2010 Marc Dietrich <marvin24 at gmx.de>
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-paz00.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map paz00_map[] = {
-	TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
-	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-	TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
-	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-	TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-	TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
-	TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
-	TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-	TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
-	TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
-	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-	TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
-	TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
-	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
-	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
-	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
-	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-	TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
-	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
-	TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
-	TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
-	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-	TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
-	TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
-	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-	TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
-	TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
-	TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
-	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
-	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-	TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
-	TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
-	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-	TEGRA_MAP_CONF("ck32",    none, na),
-	TEGRA_MAP_CONF("ddrc",    none, na),
-	TEGRA_MAP_CONF("pmca",    none, na),
-	TEGRA_MAP_CONF("pmcb",    none, na),
-	TEGRA_MAP_CONF("pmcc",    none, na),
-	TEGRA_MAP_CONF("pmcd",    none, na),
-	TEGRA_MAP_CONF("pmce",    none, na),
-	TEGRA_MAP_CONF("xm2c",    none, na),
-	TEGRA_MAP_CONF("xm2d",    none, na),
-	TEGRA_MAP_CONF("ls",      up,   na),
-	TEGRA_MAP_CONF("lc",      up,   na),
-	TEGRA_MAP_CONF("ld17_0",  down, na),
-	TEGRA_MAP_CONF("ld19_18", down, na),
-	TEGRA_MAP_CONF("ld21_20", down, na),
-	TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-	.maps = paz00_map,
-	.map_count = ARRAY_SIZE(paz00_map),
-};
-
-void paz00_pinmux_init(void)
-{
-	tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 4b64af5..5930551 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -17,72 +17,10 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio_keys.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
 
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
 #include "board-paz00.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-	{
-		/* serial port on JP1 */
-		.membase	= IO_ADDRESS(TEGRA_UARTA_BASE),
-		.mapbase	= TEGRA_UARTA_BASE,
-		.irq		= INT_UARTA,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-		.type		= PORT_TEGRA,
-		.handle_break	= tegra_serial_handle_break,
-		.iotype		= UPIO_MEM,
-		.regshift	= 2,
-		.uartclk	= 216000000,
-	}, {
-		/* serial port on mini-pcie */
-		.membase	= IO_ADDRESS(TEGRA_UARTC_BASE),
-		.mapbase	= TEGRA_UARTC_BASE,
-		.irq		= INT_UARTC,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-		.type		= PORT_TEGRA,
-		.handle_break	= tegra_serial_handle_break,
-		.iotype		= UPIO_MEM,
-		.regshift	= 2,
-		.uartclk	= 216000000,
-	}, {
-		.flags		= 0
-	}
-};
-
-static struct platform_device debug_uart = {
-	.name = "serial8250",
-	.id = PLAT8250_DEV_PLATFORM,
-	.dev = {
-		.platform_data = debug_uart_platform_data,
-	},
-};
 
 static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
 	.name		= "wifi_rfkill",
@@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
 	},
 };
 
-static struct gpio_led gpio_leds[] = {
-	{
-		.name			= "wifi-led",
-		.default_trigger	= "rfkill0",
-		.gpio			= TEGRA_WIFI_LED,
-	},
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
-	.leds		= gpio_leds,
-	.num_leds	= ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
-	.name	= "leds-gpio",
-	.id	= -1,
-	.dev	= {
-		.platform_data = &gpio_led_info,
-        },
-};
-
-static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
-	{
-		.code		= KEY_POWER,
-		.gpio		= TEGRA_GPIO_POWERKEY,
-		.active_low	= 1,
-		.desc		= "Power",
-		.type		= EV_KEY,
-		.wakeup		= 1,
-	},
-};
-
-static struct gpio_keys_platform_data paz00_gpio_keys = {
-	.buttons	= paz00_gpio_keys_buttons,
-	.nbuttons	= ARRAY_SIZE(paz00_gpio_keys_buttons),
-};
-
-static struct platform_device gpio_keys_device = {
-	.name	= "gpio-keys",
-	.id	= -1,
-	.dev	= {
-		.platform_data = &paz00_gpio_keys,
-	},
-};
-
-static struct platform_device *paz00_devices[] __initdata = {
-	&debug_uart,
-	&tegra_sdhci_device4,
-	&tegra_sdhci_device1,
-	&leds_gpio,
-	&gpio_keys_device,
-};
-
-static void paz00_i2c_init(void)
-{
-	platform_device_register(&tegra_i2c_device1);
-	platform_device_register(&tegra_i2c_device2);
-	platform_device_register(&tegra_i2c_device4);
-}
-
-static void paz00_usb_init(void)
-{
-	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
-
-	platform_device_register(&tegra_ehci2_device);
-	platform_device_register(&tegra_ehci3_device);
-}
-
-static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
-	struct meminfo *mi)
-{
-	mi->nr_banks = 1;
-	mi->bank[0].start = PHYS_OFFSET;
-	mi->bank[0].size = 448 * SZ_1M;
-}
-
-static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
-	/* name		parent		rate		enabled */
-	{ "uarta",	"pll_p",	216000000,	true },
-	{ "uartc",	"pll_p",	216000000,	true },
-
-	{ "usbd",	"clk_m",	12000000,	false },
-	{ "usb2",	"clk_m",	12000000,	false },
-	{ "usb3",	"clk_m",	12000000,	false },
-
-	{ NULL,		NULL,		0,		0},
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-	.cd_gpio	= TEGRA_GPIO_SD1_CD,
-	.wp_gpio	= TEGRA_GPIO_SD1_WP,
-	.power_gpio	= TEGRA_GPIO_SD1_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-	.cd_gpio	= -1,
-	.wp_gpio	= -1,
-	.power_gpio	= -1,
-	.is_8bit	= 1,
-};
-
 void __init tegra_paz00_wifikill_init(void)
 {
 	platform_device_register(&wifi_rfkill_device);
 }
-
-static void __init tegra_paz00_init(void)
-{
-	tegra_clk_init_from_table(paz00_clk_init_table);
-
-	paz00_pinmux_init();
-
-	tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-	tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-	platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
-	tegra_paz00_wifikill_init();
-
-	paz00_i2c_init();
-	paz00_usb_init();
-}
-
-MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
-	.atag_offset	= 0x100,
-	.fixup		= tegra_paz00_fixup,
-	.map_io         = tegra_map_common_io,
-	.init_early	= tegra20_init_early,
-	.init_irq       = tegra_init_irq,
-	.handle_irq	= gic_handle_irq,
-	.timer          = &tegra_timer,
-	.init_machine   = tegra_paz00_init,
-	.init_late	= tegra_init_late,
-	.restart	= tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 3c9f8da..25c08ec 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,24 +17,9 @@
 #ifndef _MACH_TEGRA_BOARD_PAZ00_H
 #define _MACH_TEGRA_BOARD_PAZ00_H
 
-#include <mach/gpio-tegra.h>
+#include "gpio-names.h"
 
-/* SDCARD */
-#define TEGRA_GPIO_SD1_CD		TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP		TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER		TEGRA_GPIO_PV1
-
-/* ULPI */
-#define TEGRA_ULPI_RST			TEGRA_GPIO_PV0
-
-/* WIFI */
 #define TEGRA_WIFI_PWRN			TEGRA_GPIO_PK5
 #define TEGRA_WIFI_RST			TEGRA_GPIO_PD1
-#define TEGRA_WIFI_LED			TEGRA_GPIO_PD0
-
-/* WakeUp */
-#define TEGRA_GPIO_POWERKEY	TEGRA_GPIO_PJ7
-
-void paz00_pinmux_init(void);
 
 #endif
-- 
1.7.0.4



From swarren at wwwdotorg.org  Mon Aug  6 17:32:14 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon,  6 Aug 2012 15:32:14 -0600
Subject: [PATCH 3/3] ARM: tegra: remove board (but not DT) support for Harmony
In-Reply-To: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
References: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1344288734-24131-3-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Harmony can be booted using device tree with equal functionality as when
booted using a board file. Remove as much of the board file as is
possible, since it's no longer needed.

Two special-cases are still left in board-dt-tegra20.c, since the Tegra
PCIe driver doesn't support device tree yet, and the Harmony .dts file
doesn't yet describe regulators which are needed for PCIe. This logic is
now enabled unconditionally rather than via CONFIG_MACH_HARMONY. While
this is more code than other boards, it's still unlikely to be much of a
problem, and both regulators and PCIe should be supported via device tree
in the near future, allowing the remaining code to be removed.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/Kconfig                |    6 -
 arch/arm/mach-tegra/Makefile               |    6 +-
 arch/arm/mach-tegra/board-dt-tegra20.c     |    6 +-
 arch/arm/mach-tegra/board-harmony-pinmux.c |  156 ----------------------
 arch/arm/mach-tegra/board-harmony-power.c  |   34 ++---
 arch/arm/mach-tegra/board-harmony.c        |  197 ----------------------------
 arch/arm/mach-tegra/board-harmony.h        |   13 --
 7 files changed, 19 insertions(+), 399 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/board-harmony-pinmux.c
 delete mode 100644 arch/arm/mach-tegra/board-harmony.c

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index f6e79ed..d3e73ec 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -60,12 +60,6 @@ config TEGRA_AHB
 
 comment "Tegra board type"
 
-config MACH_HARMONY
-       bool "Harmony board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for nVidia Harmony development platform
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1c2b473..6273853 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -26,9 +26,7 @@ obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
 
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-pcie.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-power.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 1d6c9df..d9eeae6 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -107,7 +107,6 @@ static void __init trimslice_init(void)
 #endif
 }
 
-#ifdef CONFIG_MACH_HARMONY
 static void __init harmony_init(void)
 {
 	int ret;
@@ -118,11 +117,12 @@ static void __init harmony_init(void)
 		return;
 	}
 
+#ifdef CONFIG_TEGRA_PCI
 	ret = harmony_pcie_init();
 	if (ret)
 		pr_err("harmony_pcie_init() failed: %d\n", ret);
-}
 #endif
+}
 
 static void __init paz00_init(void)
 {
@@ -134,9 +134,7 @@ static struct {
 	void (*init)(void);
 } board_init_funcs[] = {
 	{ "compulab,trimslice", trimslice_init },
-#ifdef CONFIG_MACH_HARMONY
 	{ "nvidia,harmony", harmony_init },
-#endif
 	{ "compal,paz00", paz00_init },
 };
 
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
deleted file mode 100644
index 83d420f..0000000
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-harmony.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map harmony_map[] = {
-	TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-	TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-	TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-	TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
-	TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
-	TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-	TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
-	TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
-	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-	TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-	TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
-	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-	TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
-	TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
-	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-	TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
-	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-	TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
-	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-	TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
-	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
-	TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
-	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
-	TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-	TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-	TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
-	TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-	TEGRA_MAP_CONF("ck32",    none, na),
-	TEGRA_MAP_CONF("ddrc",    none, na),
-	TEGRA_MAP_CONF("pmca",    none, na),
-	TEGRA_MAP_CONF("pmcb",    none, na),
-	TEGRA_MAP_CONF("pmcc",    none, na),
-	TEGRA_MAP_CONF("pmcd",    none, na),
-	TEGRA_MAP_CONF("pmce",    none, na),
-	TEGRA_MAP_CONF("xm2c",    none, na),
-	TEGRA_MAP_CONF("xm2d",    none, na),
-	TEGRA_MAP_CONF("ls",      up,   na),
-	TEGRA_MAP_CONF("lc",      up,   na),
-	TEGRA_MAP_CONF("ld17_0",  down, na),
-	TEGRA_MAP_CONF("ld19_18", down, na),
-	TEGRA_MAP_CONF("ld21_20", down, na),
-	TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-	.maps = harmony_map,
-	.map_count = ARRAY_SIZE(harmony_map),
-};
-
-void harmony_pinmux_init(void)
-{
-	tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index b7344be..8f9cf77 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -120,29 +120,25 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 
 int __init harmony_regulator_init(void)
 {
+	struct device_node *np;
+	struct i2c_adapter *adapter;
+
 	regulator_register_always_on(0, "vdd_sys",
 		NULL, 0, 5000000);
 
-	if (machine_is_harmony()) {
-		i2c_register_board_info(3, harmony_regulators, 1);
-	} else { /* Harmony, booted using device tree */
-		struct device_node *np;
-		struct i2c_adapter *adapter;
-
-		np = of_find_node_by_path("/i2c at 7000d000");
-		if (np == NULL) {
-			pr_err("Could not find device_node for DVC I2C\n");
-			return -ENODEV;
-		}
-
-		adapter = of_find_i2c_adapter_by_node(np);
-		if (!adapter) {
-			pr_err("Could not find i2c_adapter for DVC I2C\n");
-			return -ENODEV;
-		}
-
-		i2c_new_device(adapter, harmony_regulators);
+	np = of_find_node_by_path("/i2c at 7000d000");
+	if (np == NULL) {
+		pr_err("Could not find device_node for DVC I2C\n");
+		return -ENODEV;
+	}
+
+	adapter = of_find_i2c_adapter_by_node(np);
+	if (!adapter) {
+		pr_err("Could not find i2c_adapter for DVC I2C\n");
+		return -ENODEV;
 	}
 
+	i2c_new_device(adapter, harmony_regulators);
+
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
deleted file mode 100644
index e65e837..0000000
--- a/arch/arm/mach-tegra/board-harmony.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <sound/wm8903.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/tegra_wm8903_pdata.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "board-harmony.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-	{
-		.membase	= IO_ADDRESS(TEGRA_UARTD_BASE),
-		.mapbase	= TEGRA_UARTD_BASE,
-		.irq		= INT_UARTD,
-		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-		.type		= PORT_TEGRA,
-		.handle_break	= tegra_serial_handle_break,
-		.iotype		= UPIO_MEM,
-		.regshift	= 2,
-		.uartclk	= 216000000,
-	}, {
-		.flags		= 0
-	}
-};
-
-static struct platform_device debug_uart = {
-	.name = "serial8250",
-	.id = PLAT8250_DEV_PLATFORM,
-	.dev = {
-		.platform_data = debug_uart_platform_data,
-	},
-};
-
-static struct tegra_wm8903_platform_data harmony_audio_pdata = {
-	.gpio_spkr_en		= TEGRA_GPIO_SPKR_EN,
-	.gpio_hp_det		= TEGRA_GPIO_HP_DET,
-	.gpio_hp_mute		= -1,
-	.gpio_int_mic_en	= TEGRA_GPIO_INT_MIC_EN,
-	.gpio_ext_mic_en	= TEGRA_GPIO_EXT_MIC_EN,
-};
-
-static struct platform_device harmony_audio_device = {
-	.name	= "tegra-snd-wm8903",
-	.id	= 0,
-	.dev	= {
-		.platform_data  = &harmony_audio_pdata,
-	},
-};
-
-static struct wm8903_platform_data harmony_wm8903_pdata = {
-	.irq_active_low = 0,
-	.micdet_cfg = 0,
-	.micdet_delay = 100,
-	.gpio_base = HARMONY_GPIO_WM8903(0),
-	.gpio_cfg = {
-		0,
-		0,
-		WM8903_GPIO_CONFIG_ZERO,
-		0,
-		0,
-	},
-};
-
-static struct i2c_board_info __initdata wm8903_board_info = {
-	I2C_BOARD_INFO("wm8903", 0x1a),
-	.platform_data = &harmony_wm8903_pdata,
-};
-
-static void __init harmony_i2c_init(void)
-{
-	platform_device_register(&tegra_i2c_device1);
-	platform_device_register(&tegra_i2c_device2);
-	platform_device_register(&tegra_i2c_device3);
-	platform_device_register(&tegra_i2c_device4);
-
-	wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
-	i2c_register_board_info(0, &wm8903_board_info, 1);
-}
-
-static struct platform_device *harmony_devices[] __initdata = {
-	&debug_uart,
-	&tegra_sdhci_device1,
-	&tegra_sdhci_device2,
-	&tegra_sdhci_device4,
-	&tegra_ehci3_device,
-	&tegra_i2s_device1,
-	&tegra_das_device,
-	&harmony_audio_device,
-};
-
-static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
-	struct meminfo *mi)
-{
-	mi->nr_banks = 2;
-	mi->bank[0].start = PHYS_OFFSET;
-	mi->bank[0].size = 448 * SZ_1M;
-	mi->bank[1].start = SZ_512M;
-	mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
-	/* name		parent		rate		enabled */
-	{ "uartd",	"pll_p",	216000000,	true },
-	{ "pll_a",	"pll_p_out1",	56448000,	true },
-	{ "pll_a_out0",	"pll_a",	11289600,	true },
-	{ "cdev1",	NULL,		0,		true },
-	{ "i2s1",	"pll_a_out0",	11289600,	false},
-	{ "usb3",	"clk_m",	12000000,	true },
-	{ NULL,		NULL,		0,		0},
-};
-
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-	.cd_gpio	= -1,
-	.wp_gpio	= -1,
-	.power_gpio	= -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
-	.cd_gpio	= TEGRA_GPIO_SD2_CD,
-	.wp_gpio	= TEGRA_GPIO_SD2_WP,
-	.power_gpio	= TEGRA_GPIO_SD2_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-	.cd_gpio	= TEGRA_GPIO_SD4_CD,
-	.wp_gpio	= TEGRA_GPIO_SD4_WP,
-	.power_gpio	= TEGRA_GPIO_SD4_POWER,
-	.is_8bit	= 1,
-};
-
-static void __init tegra_harmony_init(void)
-{
-	tegra_clk_init_from_table(harmony_clk_init_table);
-
-	harmony_pinmux_init();
-
-	tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-	tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
-	tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
-	harmony_i2c_init();
-	harmony_regulator_init();
-}
-
-MACHINE_START(HARMONY, "harmony")
-	.atag_offset	= 0x100,
-	.fixup		= tegra_harmony_fixup,
-	.map_io         = tegra_map_common_io,
-	.init_early	= tegra20_init_early,
-	.init_irq       = tegra_init_irq,
-	.handle_irq	= gic_handle_irq,
-	.timer          = &tegra_timer,
-	.init_machine   = tegra_harmony_init,
-	.init_late	= tegra_init_late,
-	.restart	= tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
index 139d96c..7ae8708 100644
--- a/arch/arm/mach-tegra/board-harmony.h
+++ b/arch/arm/mach-tegra/board-harmony.h
@@ -20,22 +20,9 @@
 #include <mach/gpio-tegra.h>
 
 #define HARMONY_GPIO_TPS6586X(_x_)	(TEGRA_NR_GPIOS + (_x_))
-#define HARMONY_GPIO_WM8903(_x_)	(HARMONY_GPIO_TPS6586X(4) + (_x_))
 
-#define TEGRA_GPIO_SD2_CD		TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP		TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER		TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD		TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP		TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER		TEGRA_GPIO_PI6
-#define TEGRA_GPIO_CDC_IRQ		TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN		HARMONY_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET		TEGRA_GPIO_PW2
-#define TEGRA_GPIO_INT_MIC_EN		TEGRA_GPIO_PX0
-#define TEGRA_GPIO_EXT_MIC_EN		TEGRA_GPIO_PX1
 #define TEGRA_GPIO_EN_VDD_1V05_GPIO	HARMONY_GPIO_TPS6586X(2)
 
-void harmony_pinmux_init(void);
 int harmony_regulator_init(void);
 
 #endif
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Mon Aug  6 17:41:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 6 Aug 2012 22:41:22 +0100
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
 <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
Message-ID: <20120806214121.GA26698@opensource.wolfsonmicro.com>

On Mon, Aug 06, 2012 at 03:39:50PM -0500, Matt Sealey wrote:
> On Mon, Aug 6, 2012 at 3:16 PM, Robert Schwebel

> > That's not true; we still run MX25, MX27, MX35, MX28 on mainline in
> > active projects.

> I think Shawn Guo (FSL/Linaro) would also disagree, since he's just
> posted a large amount of MXS patches to fix up the board for device
> trees, and Arnd is pulling them.

MXS != i.MX.

> As far as I know, the FIQ usage is quite valid for the processor it
> needs to run on (MX21/27/28, right?) in the modes it runs in (AC97 on
> these processors, and maybe MX35 too), and I'm just trying to figure
> out what the steps are for

Oh, ick.  What is the problem that means people want to use the FIQ on
these processors?  There's been i.MX2x audio DMA since forever, it had
DMA in mainline before any of the later i.MXs due to them having SDMA.
The original mainline i.MX audio support was done on i.MX27 and didn't
have any issue here, this is the fist I've heard of a problem.

> I did note that SND_SOC_EUKREA_TLV320 enables FIQ but it also depends
> on MX51 which makes me think this need to be split, too, so that MX51
> boards don't have it but MX2/MX3 do.

Is that not bitrot due to it being there before SDMA support was?


From nico at fluxnic.net  Mon Aug  6 18:36:10 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 06 Aug 2012 18:36:10 -0400 (EDT)
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208061829510.5231@xanadu.home>

On Mon, 6 Aug 2012, Matt Sealey wrote:

> Right now there's already a fixed entry point - ARM kernels are fixed
> entry point of relative 0 to the start of the loaded image. Okay, so
> we can't format a totally valid ELF header, but in the event that we
> want to encode all this information yet again, why reinvent the wheel?

That's the point.  We do _not_ want to encode anything.

By convention, if your CPU is ARM mode capable, then it must call the 
kernel in ARM mode, period.  Can't be simpler than that, right?  The 
bootloader shouldn't care if the kernel is itself ARM or Thumb, and the 
kernel shouldn't care if the bootloader is ARM or Thumb.

If you have a real problem with this then let's hear it so it can be 
addressed.


Nicolas


From matt at genesi-usa.com  Mon Aug  6 19:14:33 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 18:14:33 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
Message-ID: <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>

On Mon, Aug 6, 2012 at 5:36 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 6 Aug 2012, Matt Sealey wrote:
>
>> Right now there's already a fixed entry point - ARM kernels are fixed
>> entry point of relative 0 to the start of the loaded image. Okay, so
>> we can't format a totally valid ELF header, but in the event that we
>> want to encode all this information yet again, why reinvent the wheel?
>
> That's the point.  We do _not_ want to encode anything.
>
> By convention, if your CPU is ARM mode capable, then it must call the
> kernel in ARM mode, period.  Can't be simpler than that, right?  The
> bootloader shouldn't care if the kernel is itself ARM or Thumb, and the
> kernel shouldn't care if the bootloader is ARM or Thumb.
>
> If you have a real problem with this then let's hear it so it can be
> addressed.

I don't have a real *problem* with it, I just think since the kernel
can be compiled in both modes, but you may have some kind of remit to
not run ARM code (even if it's just a couple instructions at the
start) or some toolchain requirement or.. something.. it would be
entirely the bootloader's job to determine what mode it is in when it
jumps into the kernel. If you boot a Thumb bootloader and load an ARM
kernel, you'll get a crash. If you boot an ARM bootloader and a Thumb
kernel (with the current ARM instructions in head.S), you'll get a
crash. This is well defined, perfectly obvious, and I realise that..

But if you would need to micromanage the system such that they both
matched, or were perverse enough to build a Thumb bootloader and a
Thumb kernel, you might be counfounded that you actually created a
99.99% Thumb bootloader which switched to ARM mode before going into
the kernel, and a 99.99% Thumb kernel but needed to jump into Thumb
mode after the first part of the kernel code? It should be possible
(with that kernel config switch it would be) if you're into that kind
of configurability to build your Thumb bootloader, build your Thumb
kernel and have it never exit Thumb mode for any reason, even if it is
just for some few bytes of very minor bootstrapping.

The same perfectly obvious caveats apply, but it's possible. The
question is, if you could do it, how would you make sure bootloaders
booted the right way? I would hazard a guess that given your opinion
on it, it would be just as good if they all just crashed.

So let's just patch out the ARM parts if you're building a Thumb
kernel on a Thumb-only device, and assume it was in Thumb mode all
along if another subordinate option was selected.. that way the kernel
can automatically fulfill one side of the contract in that you
configured "build thumb2 kernel" and it would contain 0% normal arm
code for ARMv7-M (or -R) and be able to be prompted to do so if you
were building for ARMv6k/ARMv7-A. Ordinary people would not turn it
on.. whacky weirdos like you and me might do it for proof of concept
;)

All it needs is a bootloader able to fulfill it's side of the contract
(build a thumb2 bootloader..) and jump while in Thumb mode, which I am
100% certain exists. It'd be a 20 line patch maximum to make U-Boot do
this (it already can build as Thumb2 I think.. if not, there are
patches around) through an environment variable and distros that knew
they built in Thumb mode could simply modify the variable in boot.scr
or so, and the jump would end up being done in Thumb. That way you
have to kick it, but no changes are required in the kernel format
(just in the packaging of the kernel and configuration of the
bootloader). Guessing would be a bad idea...

I still say considering you thought of a workable solution and your
problem is only the linker in use (seems like a bug report to the gas
guys is in order..) and there are probably ways to get around that
anyway, why not do it? I find it odd that Linux needs a "hard customer
requirement" for it to need it to be capable of doing it, if it's just
*possible*.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From matt at genesi-usa.com  Mon Aug  6 19:26:34 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 6 Aug 2012 18:26:34 -0500
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120806214121.GA26698@opensource.wolfsonmicro.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
 <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
 <20120806214121.GA26698@opensource.wolfsonmicro.com>
Message-ID: <CAKGA1bma1T5NXZgY4XDko0r4o_m1b-JioVjjC8+c4-1PE+r1aw@mail.gmail.com>

On Mon, Aug 6, 2012 at 4:41 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Aug 06, 2012 at 03:39:50PM -0500, Matt Sealey wrote:
>> On Mon, Aug 6, 2012 at 3:16 PM, Robert Schwebel
>
>> > That's not true; we still run MX25, MX27, MX35, MX28 on mainline in
>> > active projects.
>
>> I think Shawn Guo (FSL/Linaro) would also disagree, since he's just
>> posted a large amount of MXS patches to fix up the board for device
>> trees, and Arnd is pulling them.
>
> MXS != i.MX.
>
>> As far as I know, the FIQ usage is quite valid for the processor it
>> needs to run on (MX21/27/28, right?) in the modes it runs in (AC97 on
>> these processors, and maybe MX35 too), and I'm just trying to figure
>> out what the steps are for
>
> Oh, ick.  What is the problem that means people want to use the FIQ on
> these processors?  There's been i.MX2x audio DMA since forever, it had
> DMA in mainline before any of the later i.MXs due to them having SDMA.
> The original mainline i.MX audio support was done on i.MX27 and didn't
> have any issue here, this is the fist I've heard of a problem.

For SSI in I2S mode, I think it works great, AC97 not so much. It's
the AC97 mode
the FIQ stuff is there to fix. It seems a bunch of boards use AC97
codecs (for no
good reason)

>> I did note that SND_SOC_EUKREA_TLV320 enables FIQ but it also depends
>> on MX51 which makes me think this need to be split, too, so that MX51
>> boards don't have it but MX2/MX3 do.
>
> Is that not bitrot due to it being there before SDMA support was?

Possibly. I'm going to wait for Sascha to explain it again.. if AC97
was the predicate
for FIQ being required, it doesn't make any sense for a codec that says in it's
description that it's I2S. It may not be bitrot but pure,
unadulterated zeal on the part
of whoever wrote that Kconfig snippet - enable everything, in case it
fails (actually
that kind of thing is why I fear for nuking the building of this
driver since if FIQ stuff
is silently required by something else and all that kept it in there
was some badly
thought out or bitrotted Kconfig entries... I don't want to cause a
world of hurt).

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From khilman at ti.com  Mon Aug  6 19:31:10 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 06 Aug 2012 16:31:10 -0700
Subject: [PATCHv4 2/8] ARM: OMAP3+: voltage/pwrdm/clkdm/clock add
 recursive usecount tracking
In-Reply-To: <1342189185-5306-3-git-send-email-t-kristo@ti.com> (Tero Kristo's
 message of "Fri, 13 Jul 2012 17:19:39 +0300")
References: <1342189185-5306-1-git-send-email-t-kristo@ti.com>
 <1342189185-5306-3-git-send-email-t-kristo@ti.com>
Message-ID: <87ipcv4myp.fsf@ti.com>

Tero Kristo <t-kristo at ti.com> writes:

> This patch fixes the usecount tracking for omap3+, previously the
> usecount numbers were rather bogus and were not really useful for
> any purpose. Now usecount numbers track the number of really active
> clients on each domain. This patch also adds support for usecount
> tracking on powerdomain level and autoidle flag for clocks that
> are hardware controlled and should be skipped in usecount
> calculations.
>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Kevin Hilman <khilman at ti.com>

[...]

>  /* Clock control for DPLL outputs */
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
> index 9611490..68bdf36 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -981,6 +981,41 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
>  	return ret;
>  }
>  
> +/**
> + * pwrdm_clkdm_enable - increment powerdomain usecount
> + * @pwrdm: struct powerdomain *
> + *
> + * Increases the usecount for a powerdomain. Called from clockdomain
> + * code once a clockdomain's usecount reaches zero, i.e. it is ready
> + * to idle.
> + */

I think the comment here is wrong.

> +void pwrdm_clkdm_enable(struct powerdomain *pwrdm)
> +{
> +	if (!pwrdm)
> +		return;
> +
> +	atomic_inc(&pwrdm->usecount);
> +}
> +
> +/**
> + * pwrdm_clkdm_disable - decrease powerdomain usecount
> + * @pwrdm: struct powerdomain *
> + *
> + * Decreases the usecount for a powerdomain. Called from clockdomain
> + * code once a clockdomain becomes active.
> + */

Looks like these two comments need to be swapped?

> +void pwrdm_clkdm_disable(struct powerdomain *pwrdm)
> +{
> +	int val;
> +
> +	if (!pwrdm)
> +		return;
> +
> +	val = atomic_dec_return(&pwrdm->usecount);
> +
> +	BUG_ON(val < 0);
> +}
> +

Kevin


From khilman at ti.com  Mon Aug  6 19:32:16 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 06 Aug 2012 16:32:16 -0700
Subject: [PATCHv4 4/8] ARM: OMAP3: add manual control for mpu / core pwrdm
 usecounting
In-Reply-To: <878ve5j8se.fsf@ti.com> (Kevin Hilman's message of "Fri, 27 Jul
 2012 12:36:33 -0700")
References: <1342189185-5306-1-git-send-email-t-kristo@ti.com>
 <1342189185-5306-5-git-send-email-t-kristo@ti.com>
 <878ve5j8se.fsf@ti.com>
Message-ID: <87ehnj4mwv.fsf@ti.com>

Kevin Hilman <khilman at ti.com> writes:

> Tero Kristo <t-kristo at ti.com> writes:
>
>> mpu / core powerdomain usecounts are now statically increased
>> by 1 during MPU activity. This allows the domains to reflect
>> actual usage, and will allow the usecount to reach 0 just before
>> all CPUs are ready to idle. Proper powerdomain usecounts are
>> propageted to voltagedomain level also, and will allow vc
>> callbacks to be triggered at right point of time.
>>
>> Signed-off-by: Tero Kristo <t-kristo at ti.com>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Kevin Hilman <khilman at ti.com>
>
> IMO, the idea is fine, but I'm not crazy about the implementation in
> powerdomain.c, which is meant for pwrdm generic code.   In particular,
> I'm not crazy about the pwrdm lookups in powerdomain.c.
>
> Since pm<soc>.c already has references to mpu_pwrdm and core_pwrdm, why
> not just add the pwrdm_clkdm_enable/disable calls directly in pm<soc>.c
>
> Also, the changelog should be a bit more specific about why CORE
> powerdomain is also handled here when most of the code only talks about
> the CPU.

After playing with this some more, and doing a test hack of my idea
above, along with the per-pwrdm pre/post changes now in mainline, I
thinks this series should go one step further.

Basically, we should be able to get rid of the calls to
prdm_pre|post_transition that are outside the powerdomain code.  With
the addition of pwrdm_clkdm_enable|disable, it seems that the pre|post
transition calls should be called directly from
pwrdm_clkdm_enable|disable when the usecount transitions to/from zero.

Kevin





From nico at fluxnic.net  Mon Aug  6 20:08:57 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 06 Aug 2012 20:08:57 -0400 (EDT)
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208061935380.5231@xanadu.home>

On Mon, 6 Aug 2012, Matt Sealey wrote:

> On Mon, Aug 6, 2012 at 5:36 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > On Mon, 6 Aug 2012, Matt Sealey wrote:
> >
> >> Right now there's already a fixed entry point - ARM kernels are fixed
> >> entry point of relative 0 to the start of the loaded image. Okay, so
> >> we can't format a totally valid ELF header, but in the event that we
> >> want to encode all this information yet again, why reinvent the wheel?
> >
> > That's the point.  We do _not_ want to encode anything.
> >
> > By convention, if your CPU is ARM mode capable, then it must call the
> > kernel in ARM mode, period.  Can't be simpler than that, right?  The
> > bootloader shouldn't care if the kernel is itself ARM or Thumb, and the
> > kernel shouldn't care if the bootloader is ARM or Thumb.
> >
> > If you have a real problem with this then let's hear it so it can be
> > addressed.
> 
> I don't have a real *problem* with it, I just think since the kernel
> can be compiled in both modes, but you may have some kind of remit to
> not run ARM code (even if it's just a couple instructions at the
> start) or some toolchain requirement or.. something.. it would be
> entirely the bootloader's job to determine what mode it is in when it
> jumps into the kernel. If you boot a Thumb bootloader and load an ARM
> kernel, you'll get a crash. If you boot an ARM bootloader and a Thumb
> kernel (with the current ARM instructions in head.S), you'll get a
> crash. This is well defined, perfectly obvious, and I realise that..

And isn't it also rather silly?

History has told that the more "entirely the bootloader's job" we rely 
on, the less reliable and interoperable we become.  Because you now have 
to compile two kernels to fully validate your bootloader instead of only 
one, and some people won't bother if the second kernel doesn't match 
their own use case.

> But if you would need to micromanage the system such that they both
> matched, or were perverse enough to build a Thumb bootloader and a
> Thumb kernel, you might be counfounded that you actually created a
> 99.99% Thumb bootloader which switched to ARM mode before going into
> the kernel, and a 99.99% Thumb kernel but needed to jump into Thumb
> mode after the first part of the kernel code?

I'm pragmatic enough to fully accept this impurity.

The x86 kernel does boot in 16-bit mode even if nobody compiles 16-bit 
applications anymore.

> It should be possible (with that kernel config switch it would be) if 
> you're into that kind of configurability to build your Thumb 
> bootloader, build your Thumb kernel and have it never exit Thumb mode 
> for any reason, even if it is just for some few bytes of very minor 
> bootstrapping.

And what does this buy you?

> The same perfectly obvious caveats apply, but it's possible. The
> question is, if you could do it, how would you make sure bootloaders
> booted the right way? I would hazard a guess that given your opinion
> on it, it would be just as good if they all just crashed.

Whereas right now it just works because the kernel is always entered in 
ARM mode.

> So let's just patch out the ARM parts if you're building a Thumb
> kernel on a Thumb-only device, and assume it was in Thumb mode all
> along if another subordinate option was selected.. that way the kernel
> can automatically fulfill one side of the contract in that you
> configured "build thumb2 kernel" and it would contain 0% normal arm
> code for ARMv7-M (or -R) and be able to be prompted to do so if you
> were building for ARMv6k/ARMv7-A. Ordinary people would not turn it
> on.. whacky weirdos like you and me might do it for proof of concept
> ;)

No.  People will play with it as well and complain because their kernel 
doesn't boot anymore.  We have enough real bug reports not to add to 
them with futile ones.  And there are already way too many kernel config 
options.

Some other people will hardcode Thumb mode entry in their bootloaders.  
And if you wanted to compile your kernel in ARM mode for such a device 
then you'd have the perverse need for a shim in Thumb mode at the 
beginning of the kernel image to switch to ARM mode.

Whacky Weirdos can hack their kernel all they want.  That doesn't have 
to be sanctioned in mainline.

> All it needs is a bootloader able to fulfill it's side of the contract
> (build a thumb2 bootloader..) and jump while in Thumb mode, which I am
> 100% certain exists. It'd be a 20 line patch maximum to make U-Boot do
> this (it already can build as Thumb2 I think.. if not, there are
> patches around) through an environment variable and distros that knew
> they built in Thumb mode could simply modify the variable in boot.scr
> or so, and the jump would end up being done in Thumb. That way you
> have to kick it, but no changes are required in the kernel format
> (just in the packaging of the kernel and configuration of the
> bootloader). Guessing would be a bad idea...

The fewer contracts we have with bootloaders the better we are.  
Unfortunately those contracts are increasing in scope.  Let's avoid the 
really trivial cases if we can help it.

By mandating ARM mode, there is absolutely no guessing and no place for 
misinterpretation, buggy implementation, or other silliness of which 
bootloaders are full of.

The only good case for using Thumb mode in kernel entry is with those 
CPUs with no support for ARM mode.


Nicolas


From khilman at ti.com  Mon Aug  6 20:28:44 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 06 Aug 2012 17:28:44 -0700
Subject: [PATCH] I2C: OMAP: xfer: fix runtime PM get/put balance on error
In-Reply-To: <1340761532-27231-1-git-send-email-khilman@ti.com> (Kevin
 Hilman's message of "Tue, 26 Jun 2012 18:45:32 -0700")
References: <1340761532-27231-1-git-send-email-khilman@ti.com>
Message-ID: <87wr1b35qb.fsf@ti.com>

Hi Wolfram,

Kevin Hilman <khilman at ti.com> writes:

> In omap_i2c_xfer(), ensure pm_runtime_put() is called, even on
> failure.
>
> Without this, after a failed xfer, the runtime PM usecount will have
> been incremented, but not decremented causing the usecount to never
> reach zero after a failure.  This keeps the device always runtime PM
> enabled which keeps the enclosing power domain active, and prevents
> full-chip retention/off from happening during idle.
>
> Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
> This patch applies to current i2c-embedded/for-next branch

This one is needed for v3.6.  Can you queue this up as a fix for
v3.6-rc?

Thanks,

Kevin

>  drivers/i2c/busses/i2c-omap.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 9895fa7..b105733 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -582,7 +582,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  
>  	r = pm_runtime_get_sync(dev->dev);
>  	if (IS_ERR_VALUE(r))
> -		return r;
> +		goto out;
>  
>  	r = omap_i2c_wait_for_bb(dev);
>  	if (r < 0)


From zumeng.chen at windriver.com  Mon Aug  6 21:42:05 2012
From: zumeng.chen at windriver.com (Zumeng Chen)
Date: Tue, 7 Aug 2012 09:42:05 +0800
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce
 time for ads7846"
In-Reply-To: <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <5020726D.1030300@windriver.com>

? 2012?08?07? 04:22, Igor Grinberg ??:
> 1) The above commit introduced a common ->get_pendown_state() function
> into the generic code, but that function was board-specific for the
> OMAP3EVM and thus broke most other boards using this code.
>
> 2) The above commit was mis-merged introducing another bug which
> prevents the ads7846 driver probe function to succeed.
> The omap_ads7846_init() function frees the pendown GPIO in case there is
> no ->get_pendown_state() function set by the caller (board specific
> code), so it can be requested later by the ads7846 driver.
> The above commit add a common ->get_pendown_state() function without
> removing the gpio_free() call and thus once the ads7846 driver tries
> to use the pendown GPIO, it crashes as the pendown GPIO has not been
> requested.
>
> 3) The above commit introduces NO new functionality as
> get_pendown_state() function is already implemented in a suitable way by
> the ads7846 driver and the debounce time handling has already been
> fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).
Igor,

I suspect these two patches(this and 97ee9f01) works well, and there
is something new introduced in ads7846.c, I'll try to look at that new
stuff in this weekend.

Please refer to in-line comments:

Regards,
Zumeng
>
> This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.
>
> Conflicts:
> 	arch/arm/mach-omap2/common-board-devices.c
>
> Solved by taking the working version prior to the above commit.
>
> Cc: Zumeng Chen <zumeng.chen at windriver.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
> Kevin, sorry for the late reply.
> How about the above commit message and the below patch?
>
> The patch applies cleanly to Tony's master branch (6 Aug 2012)
> or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
> after resetting two top most commits.
>
> This patch has been tested on both above branches on cm-t3730.
> Any other board tested will be greately appreciated.
>
> Also, if after all said in the commit message, you still don't
> want to revert the original patch, feel free to post your thoughts.
>
>  arch/arm/mach-omap2/board-omap3evm.c       |    1 +
>  arch/arm/mach-omap2/common-board-devices.c |   11 -----------
>  arch/arm/mach-omap2/common-board-devices.h |    1 -
>  3 files changed, 1 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
> index ef230a0..0d362e9 100644
> --- a/arch/arm/mach-omap2/board-omap3evm.c
> +++ b/arch/arm/mach-omap2/board-omap3evm.c
> @@ -58,6 +58,7 @@
>  #include "hsmmc.h"
>  #include "common-board-devices.h"
>  
> +#define OMAP3_EVM_TS_GPIO	175
>  #define OMAP3_EVM_EHCI_VBUS	22
>  #define OMAP3_EVM_EHCI_SELECT	61
>  
> diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
> index 1473474..c187586 100644
> --- a/arch/arm/mach-omap2/common-board-devices.c
> +++ b/arch/arm/mach-omap2/common-board-devices.c
> @@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
>  	.turbo_mode	= 0,
>  };
>  
> -/*
> - * ADS7846 driver maybe request a gpio according to the value
> - * of pdata->get_pendown_state, but we have done this. So set
> - * get_pendown_state to avoid twice gpio requesting.
> - */
> -static int omap3_get_pendown_state(void)
> -{
> -	return !gpio_get_value(OMAP3_EVM_TS_GPIO);
> -}
> -
>  static struct ads7846_platform_data ads7846_config = {
>  	.x_max			= 0x0fff,
>  	.y_max			= 0x0fff,
> @@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
>  	.debounce_rep		= 1,
>  	.gpio_pendown		= -EINVAL,
>  	.keep_vref_on		= 1,
> -	.get_pendown_state	= &omap3_get_pendown_state,
You remove this, then please look at the following codes:

drivers/input/touchscreen/ads7846.c

969 if (pdata->get_pendown_state) {
970 ts->get_pendown_state = pdata->get_pendown_state;
971 } else if (gpio_is_valid(pdata->gpio_pendown)) {
972
973 err = gpio_request_one(pdata->gpio_pendown, GPIOF_IN,
^^^, the driver will want to request again, then it should
be error if i'm right.

974 "ads7846_pendown");
975 if (err) {
976 dev_err(&spi->dev,
977 "failed to request/setup pendown GPIO%d: %d\n",
978 pdata->gpio_pendown, err);
979 return err;
980 }
981
982 ts->gpio_pendown = pdata->gpio_pendown;
983
984 } else {

Regards,
Zumeng
>  };
>  
>  static struct spi_board_info ads7846_spi_board_info __initdata = {
> diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
> index 4c4ef6a..a0b4a428 100644
> --- a/arch/arm/mach-omap2/common-board-devices.h
> +++ b/arch/arm/mach-omap2/common-board-devices.h
> @@ -4,7 +4,6 @@
>  #include "twl-common.h"
>  
>  #define NAND_BLOCK_SIZE	SZ_128K
> -#define OMAP3_EVM_TS_GPIO	175
>  
>  struct mtd_partition;
>  struct ads7846_platform_data;



From zumeng.chen at windriver.com  Mon Aug  6 21:44:58 2012
From: zumeng.chen at windriver.com (Zumeng Chen)
Date: Tue, 7 Aug 2012 09:44:58 +0800
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce
 time for ads7846"
In-Reply-To: <871ujj7ngd.fsf@ti.com>
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
 <871ujj7ngd.fsf@ti.com>
Message-ID: <5020731A.1040206@windriver.com>

? 2012?08?07? 04:52, Kevin Hilman ??:
> Igor Grinberg<grinberg at compulab.co.il>  writes:
>
>> 1) The above commit introduced a common ->get_pendown_state() function
>> into the generic code, but that function was board-specific for the
>> OMAP3EVM and thus broke most other boards using this code.
>>
>> 2) The above commit was mis-merged introducing another bug which
>> prevents the ads7846 driver probe function to succeed.
>> The omap_ads7846_init() function frees the pendown GPIO in case there is
>> no ->get_pendown_state() function set by the caller (board specific
>> code), so it can be requested later by the ads7846 driver.
>> The above commit add a common ->get_pendown_state() function without
>> removing the gpio_free() call and thus once the ads7846 driver tries
>> to use the pendown GPIO, it crashes as the pendown GPIO has not been
>> requested.
>>
>> 3) The above commit introduces NO new functionality as
>> get_pendown_state() function is already implemented in a suitable way by
>> the ads7846 driver and the debounce time handling has already been
>> fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).
>>
>> This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.
>>
>> Conflicts:
>> 	arch/arm/mach-omap2/common-board-devices.c
>>
>> Solved by taking the working version prior to the above commit.
>>
>> Cc: Zumeng Chen<zumeng.chen at windriver.com>
>> Cc: Arnd Bergmann<arnd at arndb.de>
>> Signed-off-by: Igor Grinberg<grinberg at compulab.co.il>
>> ---
>> Kevin, sorry for the late reply.
>> How about the above commit message and the below patch?
>>
>> The patch applies cleanly to Tony's master branch (6 Aug 2012)
>> or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
>> after resetting two top most commits.
> Now that v3.6-rc1 is out, it should probalby be applied on top of -rc1.
> I've taken care of that and tested as well.
>
>> This patch has been tested on both above branches on cm-t3730.
>> Any other board tested will be greately appreciated.
>>
>> Also, if after all said in the commit message, you still don't
>> want to revert the original patch, feel free to post your thoughts.
> After all the digging I did, I agree that the revert is the best
> solution.
>
> While it's a slightly different problem/bug, I think the gpio_free() in
> common-board-devices.c should still be unconditonal since the
> gpio_request() is now unconditional.  That can be a separate patch though.
Absolutely right, acked this.

Regards,
Zumeng
>
> Acked-by: Kevin Hilman<khilman at ti.com>
> Tested-by: Kevin Hilman<khilman at ti.com>
>
> Tested on 3430/n900, 3530/Overo, 3730/Overo STORM, 3730/BB-xM.
>
> The Overo boards were the ones that were crashing due to this bug since
> the pendown GPIO was the only one used in the bank.
>
> Tony, can you queue this up for v3.6-rc?  I have a version in my
> for_3.6/fixes/ads7846-2 branch with the tags above applied, based on v3.6-rc1.
>
> Thanks
>
> Kevin
>
>>   arch/arm/mach-omap2/board-omap3evm.c       |    1 +
>>   arch/arm/mach-omap2/common-board-devices.c |   11 -----------
>>   arch/arm/mach-omap2/common-board-devices.h |    1 -
>>   3 files changed, 1 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
>> index ef230a0..0d362e9 100644
>> --- a/arch/arm/mach-omap2/board-omap3evm.c
>> +++ b/arch/arm/mach-omap2/board-omap3evm.c
>> @@ -58,6 +58,7 @@
>>   #include "hsmmc.h"
>>   #include "common-board-devices.h"
>>
>> +#define OMAP3_EVM_TS_GPIO	175
>>   #define OMAP3_EVM_EHCI_VBUS	22
>>   #define OMAP3_EVM_EHCI_SELECT	61
>>
>> diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
>> index 1473474..c187586 100644
>> --- a/arch/arm/mach-omap2/common-board-devices.c
>> +++ b/arch/arm/mach-omap2/common-board-devices.c
>> @@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
>>   	.turbo_mode	= 0,
>>   };
>>
>> -/*
>> - * ADS7846 driver maybe request a gpio according to the value
>> - * of pdata->get_pendown_state, but we have done this. So set
>> - * get_pendown_state to avoid twice gpio requesting.
>> - */
>> -static int omap3_get_pendown_state(void)
>> -{
>> -	return !gpio_get_value(OMAP3_EVM_TS_GPIO);
>> -}
>> -
>>   static struct ads7846_platform_data ads7846_config = {
>>   	.x_max			= 0x0fff,
>>   	.y_max			= 0x0fff,
>> @@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
>>   	.debounce_rep		= 1,
>>   	.gpio_pendown		= -EINVAL,
>>   	.keep_vref_on		= 1,
>> -	.get_pendown_state	=&omap3_get_pendown_state,
>>   };
>>
>>   static struct spi_board_info ads7846_spi_board_info __initdata = {
>> diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
>> index 4c4ef6a..a0b4a428 100644
>> --- a/arch/arm/mach-omap2/common-board-devices.h
>> +++ b/arch/arm/mach-omap2/common-board-devices.h
>> @@ -4,7 +4,6 @@
>>   #include "twl-common.h"
>>
>>   #define NAND_BLOCK_SIZE	SZ_128K
>> -#define OMAP3_EVM_TS_GPIO	175
>>
>>   struct mtd_partition;
>>   struct ads7846_platform_data;



From klightspeed at killerwolves.net  Mon Aug  6 22:02:54 2012
From: klightspeed at killerwolves.net (Ben Peddell)
Date: Tue,  7 Aug 2012 12:02:54 +1000 (EST)
Subject: [PATCH 1/1] initramfs: handle trailing junk after valid image (try 2)
In-Reply-To: <50201563.2020509@mvista.com>
References: <CAB9O=CMADa26benQCkEoLOKKTGNeExjvFeVkFe4HLVi-W=o=Jg@mail.gmail.com>, 
 <501F8D75.8070108@killerwolves.net>, <50201563.2020509@mvista.com>
Message-ID: <20120807020254.BE00F77A0F@aristotle.killerwolves.net>

The initramfs handling since commit df37bd15 (initramfs: handle 
unrecognised decompressor when unpacking) has been rejecting
valid images that have garbage after them.  For example, on an
architecture where the initramfs address and size are specified
as a kernel parameter (specifically unicore32 and arm), specifying
e.g. initrd=0x01000000,4M will not work unless the image is padded
with nulls to 4MiB.  This is unlikely to occur if the user is using
this parameter to work around a bug in the bootloader.

Signed-off-by: Ben Peddell <klightspeed at killerwolves.net>

---
 init/initramfs.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/init/initramfs.c b/init/initramfs.c
index 84c6bf1..26c2cb1 100644
--- a/init/initramfs.c
+++ b/init/initramfs.c
@@ -467,6 +467,9 @@ static char * __init unpack_to_rootfs(char *buf, unsigned len)
 					 compress_name);
 				message = msg_buf;
 			}
+		} else if (state == Reset) {
+			my_inptr = len;
+			pr_warn("%s: junk at end of compressed archive\n", __func__);
 		} else
 			error("junk in compressed archive");
 		if (state != Reset)
-- 
1.7.3.4



From Dongjin.Kim at agreeyamobility.net  Mon Aug  6 22:05:56 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Tue, 7 Aug 2012 02:05:56 +0000
Subject: =?utf-8?B?7ZqM7IugOiDtmozsi6A6IFtQQVRDSF0gT0RST0lELVg6IGhrZGs0NDEyOiBB?=
 =?utf-8?Q?dd_new_hardware_based_on_Exynos4412?=
In-Reply-To: <CAOesGMh=6QrCmL4EqnSqTxi1nH+8Wn+x=z9BYq8QJCznH3a=zQ@mail.gmail.com>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4362EE@SN2PRD0510MB370.namprd05.prod.outlook.com>,
 <CAOesGMh=6QrCmL4EqnSqTxi1nH+8Wn+x=z9BYq8QJCznH3a=zQ@mail.gmail.com>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F43688D@SN2PRD0510MB370.namprd05.prod.outlook.com>

Hello,

I am trying to understand what I have to do for device tree.

In order to create dts file for ODROID-X hardware, it seems I may need dts file of EXYNOS4412 SoC.
But maybe exynos4412.dtsi is not merged yet or not exist, like exynos4210.dtsi or exynos5250.dtsi.
Obviously it seems not easy to create such a file without SoC datasheet, and I do not have it.

So do I wait for the file to be merged by Samsung or better to create initial dts file cloned from exynos4210.dtsi and modify to have verified nodes with the source/header files?

What's your suggestion?

Regards,
Dongjin.
________________________________________
?? ??: Olof Johansson [olof at lixom.net]
?? ??: 2012? 8? 7? ??? ?? 3:33
?? ??: Dongjin Kim
??: Thomas Abraham; Dongjin Kim; Kukjin Kim; Russell King; Tony Lindgren; Jon Medhurst; Shawn Guo; Uwe Kleine-K?nig; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
??: Re: ??: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412

Hi,

On Mon, Aug 6, 2012 at 11:16 AM, Dongjin Kim
<Dongjin.Kim at agreeyamobility.net> wrote:
> Hello Tomas,
>
> I am agree with you to look at using device tree and I have some plan for it.
> But as of now I am focusing to bring up the hardware itself with mainline kernel and merge into it.
> I also need some time to look at the requirement of device tree, because I am not familiar with it yet.
>
> Any advice will be welcomed.

Basic rule (that has some flexibility for legacy platforms) is that
the net movement of board support should move from board files to
device-tree based. Introduction of a brand new board like this is a
prime example of something that should be using device tree from day
1.


-Olof

From shawn.guo at linaro.org  Mon Aug  6 22:09:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 Aug 2012 10:09:09 +0800
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
 <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
Message-ID: <20120807020907.GB24289@S2101-09.ap.freescale.net>

On Mon, Aug 06, 2012 at 03:39:50PM -0500, Matt Sealey wrote:
> * make sure there's no weird FIQ stuff floating around that has so far
> relied on SND_SOC_IMX_PCM_FIQ doing select FIQ before I make it not

Acked on changing SND_IMX_SOC to SND_SOC_IMX_PCM_FIQ in
arch/arm/plat-mxc/Makefile.

> compile in for other boards (since otherwise no i.MX processor selects
> FIQ if they're not using that driver, it could be simply coincidence
> nobody noticed). I don't want to be the one submitting a patch I can't
> test which mysteriously breaks every MX28 on the planet (since Rob,
> Shawn, Sascha might be the ones swearing at me instead)
> 
Though i.MX23 and i.MX28 are named in i.MX family, they are actually
a different architecture from IMX/MXC.  It's MXS, nothing to do with
SSI.  Folder sound/soc/mxs/ is the one for i.MX28.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Mon Aug  6 22:44:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 Aug 2012 10:44:04 +0800
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120806144100.GD9329@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803131230.GB23791@S2101-09.ap.freescale.net>
 <20120806144100.GD9329@pengutronix.de>
Message-ID: <20120807024401.GC24289@S2101-09.ap.freescale.net>

On Mon, Aug 06, 2012 at 04:41:00PM +0200, Uwe Kleine-K?nig wrote:
> > > +		nand at bb000000 {
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +
> > > +			compatible = "fsl,imx35-nand", "fsl,imx25-nand";
> > > +			reg = <0xbb000000 0x2000>;
> > > +			interrupts = <33>;
> > > +			status = "disabled";
> > > +		};
> > 
> > Why nand device isn't under any bus but soc directly?
> I copied that from imx27.dtsi (where I introduced it myself before).
> It's not obvious to me which bus this is a part of from reading the
> hardware manual. Neither for i.MX27 nor i.MX35.

See i.MX35 RM "Chapter 17 External Memory Interface (EMI)",
"Memory Map/Register Definition" section.

> > > +	select HAVE_CAN_FLEXCAN if CAN
> > 
> > Move it to "config SOC_IMX35".
> hmm, do we want CAN_FLEXCAN to be selectable for machines that don't
> have can although they are based on i.MX35?
> 
I just recall it has been done by commit 610578a (ARM: imx: enable
flexcan on imx25, imx35, imx53, imx6q).

> > 
> > > +	select IMX_HAVE_PLATFORM_MXC_NAND
> > > +	select IMX_HAVE_PLATFORM_SPI_IMX
> > > +	select IMX_HAVE_PLATFORM_IMX2_WDT
> > 
> > These are unreasonable.
> These are needed to be able to select the corresponding drivers.
> 
The driver Kconfig needs fixing then.

> > 
> > > +	select PINCTRL
> > 
> > Need to select PINCTRL_IMX35 also?
> good idea.
> 
> > And they should be under "config SOC_IMX35".
> Even though currently the pincontrol driver isn't used for them?
>  
No pressure for now.  But in the end, it will be like that.

> > > +static const struct of_device_id imx35_of_mixed_devices_match[] __initconst = {
> > > +	{ /* END OF LIST */ }
> > > +};
> > > +
> > > +static void __init of_mixed_device_hook(void)
> > > +{
> > > +	struct device_node *np;
> > > +	const struct of_device_id *of_id;
> > > +
> > > +	np = of_find_matching_node(NULL, imx35_of_mixed_devices_match);
> > > +	if (np) {
> > > +		void (*func)(void);
> > > +
> > > +		of_id = of_match_node(imx35_of_mixed_devices_match, np);
> > > +		func = of_id->data;
> > > +		func();
> > > +	}
> > > +}
> > 
> > We have this on other imx DT machines for hooking the IOMUX setup done
> > in non-DT board files.  Since you have imx35 pinctrl support in place.
> > What is above hook for then?
> I need it to configure and export some gpios.
> 
Add it when you add users?  So that we can know it's really the only
way to go.

> > > +extern int mx35_clocks_init_dt(void);
> > 
> > It does not necessarily belong this driver.
> I cannot parse this sentence. Can you please try to explain again your
> objections here?
> 
I see neither the implementation nor the users for mx35_clocks_init_dt().

-- 
Regards,
Shawn



From Dongjin.Kim at agreeyamobility.net  Mon Aug  6 22:56:06 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Tue, 7 Aug 2012 02:56:06 +0000
Subject: =?utf-8?B?7ZqM7IugOiDtmozsi6A6IO2ajOyLoDogW1BBVENIXSBPRFJPSUQtWDogaGtk?=
 =?utf-8?Q?k4412:_Add_new_hardware_based_on_Exynos4412?=
In-Reply-To: <CAOesGMj6BafLCpZjmtyn_ASbpeic_8E0CdYjQGOf3A4_NHfy=Q@mail.gmail.com>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <CAJuYYwSjnQ6z0iUaLCV9guC7yyKH3_pbd1QZe3ELKF-fYNfaqQ@mail.gmail.com>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4362EE@SN2PRD0510MB370.namprd05.prod.outlook.com>
 <CAOesGMh=6QrCmL4EqnSqTxi1nH+8Wn+x=z9BYq8QJCznH3a=zQ@mail.gmail.com>
 <A6A3B7488C419F488E5B13FFD03C08AD2F43688D@SN2PRD0510MB370.namprd05.prod.outlook.com>,
 <CAOesGMj6BafLCpZjmtyn_ASbpeic_8E0CdYjQGOf3A4_NHfy=Q@mail.gmail.com>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F4369FF@SN2PRD0510MB370.namprd05.prod.outlook.com>

Hi,

Thank you for your advice.
Fortunately I got ODROID-X hardware earlier and am able to boot with mainline kernel.

I will try to do alternative way first with source code kernel 3.0.15, and hope you review the patch if ready.

Regards,
Dongjin.
________________________________________
?? ??: Olof Johansson [olof at lixom.net]
?? ??: 2012? 8? 7? ??? ?? 11:28
?? ??: Dongjin Kim
??: Thomas Abraham; Dongjin Kim; Kukjin Kim; Russell King; Tony Lindgren; Jon Medhurst; Shawn Guo; Uwe Kleine-K?nig; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
??: Re: ??: ??: [PATCH] ODROID-X: hkdk4412: Add new hardware based on Exynos4412

Hi,

On Mon, Aug 6, 2012 at 7:05 PM, Dongjin Kim
<Dongjin.Kim at agreeyamobility.net> wrote:
> Hello,
>
> I am trying to understand what I have to do for device tree.
>
> In order to create dts file for ODROID-X hardware, it seems I may need dts file of EXYNOS4412 SoC.
> But maybe exynos4412.dtsi is not merged yet or not exist, like exynos4210.dtsi or exynos5250.dtsi.
> Obviously it seems not easy to create such a file without SoC datasheet, and I do not have it.
>
> So do I wait for the file to be merged by Samsung or better to create initial dts file cloned from exynos4210.dtsi and modify to have verified nodes with the source/header files?

Ideally they already have one waiting to be submitted, but that might
not be the case. Given that the origenboard design with 4412 is not
yet shipping, I'm guessing the Linaro Samsung engineers might not have
done much work on 4412 yet. Kukjin? Thomas?

> What's your suggestion?

The alternative is to use the data you have available -- i.e. sources
and patches, and craft the device tree from there. The design of 4412
is a derivative from 4210, so that's a good start. Next step would be
to describe the board on top of the SoC, peripherals, etc. Take a look
at how the origen board support was added, and so on.

I ordered an odroid-x several weeks ago but I haven't have a confirmed
shipping date yet. :( I'm not sure how long it'll be before I can help
out, unfortunately.


-Olof


From p.paneri at samsung.com  Mon Aug  6 23:57:45 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 7 Aug 2012 09:27:45 +0530
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <CAD6zSYPyRGgxVXFhcLSqjOpERq-jLrsqnjYNXM3jKsjymiLaTA@mail.gmail.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
 <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>
 <201208061123.18065.heiko@sntech.de>
 <CAD6zSYPyRGgxVXFhcLSqjOpERq-jLrsqnjYNXM3jKsjymiLaTA@mail.gmail.com>
Message-ID: <CAD6zSYMsHUeR9=ERx=XO5OXvx2SK8C2xX1WX5qXbmXBpfCuO_w@mail.gmail.com>

Hi,

On Mon, Aug 6, 2012 at 3:21 PM, Praveen Paneri <p.paneri at samsung.com> wrote:
> Hi,
>
> On Mon, Aug 6, 2012 at 2:53 PM, Heiko St?bner <heiko at sntech.de> wrote:
>> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>>> Hi Praveen,
>>>
>>> On 8/6/12, Praveen Paneri <p.paneri at samsung.com> wrote:
>>> > Hi Heiko,
>>> >
>>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de> wrote:
>>> >> Hi Praveen,
>>> >>
>>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>> >>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>> >>
>>> >> Looks cool.
>>> >
>>> > Thanks
>>> >
>>> >> From what I've seen the phy controllers on newer Samsung SoCs are still
>>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully at
>>> >> some
>>> >> point after the driver has settled, I'll find the time to add support
>>> >> for these to the phy driver.
>>> >
>>> > Yes! that's great.
>>> >
>>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>>> >
>>> > Its Samsung Electronics Co. :)
>>>
>>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>>> 'sec' prefix for samsung drivers.
>>
>> I'd second that. All new generic samsung drivers look like this (i.e. gpio-
>> samsung, pwm-samsung).
On the second thought I am thinking 'sec' is shorter and cooler. I
know that it has not
been used anywhere else but there is always a first time :-P The
shorter string helps in
writing the code; especially when we have 80 character restriction. If
you go through
this driver itself you will realize this. Also there was a suggestion
some time back to
use 'sec' instead of 'samsung'.
This is just my view about it. Please comment.

Praveen

>>
>> Just checked the datasheets again. This general phy type is used in some form
>> down to the S3C2443, so I'd prefer something with samsung in the name :-)
> Yes! That makes sense. I will change the name to samsung_usbphy
>
> Praveen
>>
>>
>> Heiko
>>
>>>
>>> Thank you,
>>> Kyungmin Park
>>>
>>> > Praveen
>>> >
>>> >>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>>> >>
>>> >> Acked-by: Heiko Stuebner <heiko at sntech.de>
>>> >>
>>> >>
>>> >> Heiko
>>> >>
>>> >>> ---
>>> >>>
>>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>>> >>>  drivers/usb/phy/Makefile                           |    1 +
>>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>> >>>
>>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>> >>>
>>> >>>  48 +++
>>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>> >>>  create mode 100644
>>> >>>
>>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>>> >>>
>>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>> >>>
>>> >>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>>> >>> mode 100644
>>> >>> index 0000000..fefd9c8
>>> >>> --- /dev/null
>>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>> >>> @@ -0,0 +1,9 @@
>>> >>> +* Samsung's usb phy transceiver
>>> >>> +
>>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>>> >>> +s3c-hsotg usb device controller.
>>> >>> +
>>> >>> +Required properties:
>>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>>> >>> +- reg : base physical address of the phy registers and length of
>>> >>> memory mapped +      region.
>>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>> >>> index e7cf84f..abbebe2 100644
>>> >>> --- a/drivers/usb/phy/Kconfig
>>> >>> +++ b/drivers/usb/phy/Kconfig
>>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>> >>>
>>> >>>         To compile this driver as a module, choose M here: the
>>> >>>         module will be called isp1301.
>>> >>>
>>> >>> +
>>> >>> +config SEC_USBPHY
>>> >>> +       bool "Samsung USB PHY controller Driver"
>>> >>> +       depends on USB_S3C_HSOTG
>>> >>> +       select USB_OTG_UTILS
>>> >>> +       help
>>> >>> +         Enable this to support Samsung USB phy controller for samsung
>>> >>> +         SoCs.
>>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>> >>> index eca095b..6bb66f0 100644
>>> >>> --- a/drivers/usb/phy/Makefile
>>> >>> +++ b/drivers/usb/phy/Makefile
>>> >>> @@ -5,3 +5,4 @@
>>> >>>
>>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>> >>>
>>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>> >>>
>>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>>> >>> index 0000000..33119eb
>>> >>> --- /dev/null
>>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>>> >>> @@ -0,0 +1,354 @@
>>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>> >>> + *
>>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>> >>> + *              http://www.samsung.com
>>> >>> + *
>>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>> >>> + *
>>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>> >>> controller + *
>>> >>> + * This program is free software; you can redistribute it and/or
>>> >>> modify + * it under the terms of the GNU General Public License
>>> >>> version 2 as + * published by the Free Software Foundation.
>>> >>> + *
>>> >>> + * This program is distributed in the hope that it will be useful,
>>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> >>> + * GNU General Public License for more details.
>>> >>> + *
>>> >>> + * You should have received a copy of the GNU General Public License
>>> >>> + * along with this program; if not, write to the Free Software
>>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>> >>> +*/
>>> >>> +
>>> >>> +#include <linux/module.h>
>>> >>> +#include <linux/platform_device.h>
>>> >>> +#include <linux/clk.h>
>>> >>> +#include <linux/delay.h>
>>> >>> +#include <linux/err.h>
>>> >>> +#include <linux/io.h>
>>> >>> +#include <linux/of.h>
>>> >>> +#include <linux/usb/otg.h>
>>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>>> >>> +
>>> >>> +#include "sec_usbphy.h"
>>> >>> +
>>> >>> +enum sec_cpu_type {
>>> >>> +     TYPE_S3C64XX,
>>> >>> +     TYPE_EXYNOS4210,
>>> >>> +};
>>> >>> +
>>> >>> +/*
>>> >>> + * struct sec_usbphy - transceiver driver state
>>> >>> + * @phy: transceiver structure
>>> >>> + * @plat: platform data
>>> >>> + * @dev: The parent device supplied to the probe function
>>> >>> + * @clk: usb phy clock
>>> >>> + * @regs: usb phy register memory base
>>> >>> + * @cpu_type: machine identifier
>>> >>> + */
>>> >>> +struct sec_usbphy {
>>> >>> +     struct usb_phy  phy;
>>> >>> +     struct s3c_usbphy_plat *plat;
>>> >>> +     struct device   *dev;
>>> >>> +     struct clk      *clk;
>>> >>> +     void __iomem    *regs;
>>> >>> +     int             cpu_type;
>>> >>> +};
>>> >>> +
>>> >>> +#define phy_to_sec(x)                container_of((x), struct
>>> >>> sec_usbphy, phy)
>>> >>> +
>>> >>> +/*
>>> >>> + * Enables or disables the phy clock
>>> >>> + * returns 0 on success else the error
>>> >>> + */
>>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>> >>> +{
>>> >>> +     if (on) {
>>> >>> +             if (!sec->clk) {
>>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>>> >>> +                     if (IS_ERR(sec->clk)) {
>>> >>> +                             dev_err(sec->dev, "Failed to get otg
>>> >>> clock\n");
>>> >>> +                             return PTR_ERR(sec->clk);
>>> >>> +                     }
>>> >>> +             }
>>> >>> +             clk_enable(sec->clk);
>>> >>> +     } else {
>>> >>> +             clk_disable(sec->clk);
>>> >>> +             clk_put(sec->clk);
>>> >>> +     }
>>> >>> +
>>> >>> +     return 0;
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * Returns reference clock frequency
>>> >>> + */
>>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     struct clk *ref_clk;
>>> >>> +     int refclk_freq = 0;
>>> >>> +
>>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>> >>> +     if (IS_ERR(ref_clk)) {
>>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>> >>> +             return PTR_ERR(ref_clk);
>>> >>> +     }
>>> >>> +
>>> >>> +     switch (clk_get_rate(ref_clk)) {
>>> >>> +     case 12 * MHZ:
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>> >>> +             break;
>>> >>> +     case 24 * MHZ:
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>> >>> +             break;
>>> >>> +     default:
>>> >>> +     case 48 * MHZ:
>>> >>> +             /* default reference clock */
>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>> >>> +             break;
>>> >>> +     }
>>> >>> +     clk_put(ref_clk);
>>> >>> +
>>> >>> +     return refclk_freq;
>>> >>> +}
>>> >>> +
>>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     void __iomem *regs = sec->regs;
>>> >>> +     u32 phypwr;
>>> >>> +     u32 phyclk;
>>> >>> +     u32 rstcon;
>>> >>> +
>>> >>> +     /* set clock frequency for PLL */
>>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>>> >>> +
>>> >>> +     switch (sec->cpu_type) {
>>> >>> +     case TYPE_S3C64XX:
>>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>> >>> +             break;
>>> >>> +     case TYPE_EXYNOS4210:
>>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>> >>> +     default:
>>> >>> +             break;
>>> >>> +     }
>>> >>> +
>>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>>> >>> +     /* set to normal of PHY0 */
>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> >>> +     /* reset all ports of PHY and Link */
>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>> >>> +     udelay(10);
>>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>> >>> +}
>>> >>> +
>>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>> >>> +{
>>> >>> +     void __iomem *regs = sec->regs;
>>> >>> +     u32 phypwr;
>>> >>> +
>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>> >>> +
>>> >>> +     switch (sec->cpu_type) {
>>> >>> +     case TYPE_S3C64XX:
>>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>> >>> +             break;
>>> >>> +     case TYPE_EXYNOS4210:
>>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>> >>> +     default:
>>> >>> +             break;
>>> >>> +     }
>>> >>> +
>>> >>> +     /* unset to normal of PHY0 */
>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * The function passed to the usb driver for phy initialization
>>> >>> + */
>>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +     int ret = 0;
>>> >>> +
>>> >>> +     sec = phy_to_sec(phy);
>>> >>> +
>>> >>> +     /* Enable the phy clock */
>>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>>> >>> +     if (ret) {
>>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>> >>> +             return ret;
>>> >>> +     }
>>> >>> +
>>> >>> +     /* Disable phy isolation */
>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> >>> +             sec->plat->pmu_isolation(false);
>>> >>> +
>>> >>> +     /* Initialize usb phy registers */
>>> >>> +     sec_usbphy_enable(sec);
>>> >>> +     return ret;
>>> >>> +}
>>> >>> +
>>> >>> +/*
>>> >>> + * The function passed to the usb driver for phy shutdown
>>> >>> + */
>>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +
>>> >>> +     sec = phy_to_sec(phy);
>>> >>> +
>>> >>> +     /* De-initialize usb phy registers */
>>> >>> +     sec_usbphy_disable(sec);
>>> >>> +
>>> >>> +     /* Enable phy isolation */
>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>> >>> +             sec->plat->pmu_isolation(true);
>>> >>> +
>>> >>> +     /* Disable the phy clock */
>>> >>> +     sec_usbphy_clk_control(sec, false);
>>> >>> +}
>>> >>> +
>>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>>> >>> +
>>> >>> +static inline int sec_usbphy_get_driver_data(struct platform_device
>>> >>> *pdev)
>>> >>> +{
>>> >>> +#ifdef CONFIG_OF
>>> >>> +     int data;
>>> >>> +     if (pdev->dev.of_node) {
>>> >>> +             const struct of_device_id *match;
>>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>>> >>> pdev->dev.of_node);
>>> >>> +             data = (int) match->data;
>>> >>> +             return data;
>>> >>> +     }
>>> >>> +#endif
>>> >>> +     return platform_get_device_id(pdev)->driver_data;
>>> >>> +}
>>> >>> +
>>> >>> +static int __devinit sec_usbphy_probe(struct platform_device *pdev)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec;
>>> >>> +     struct s3c_usbphy_plat *pdata;
>>> >>> +     struct device *dev = &pdev->dev;
>>> >>> +     struct resource *phy_mem;
>>> >>> +     void __iomem    *phy_base;
>>> >>> +     int     ret;
>>> >>> +
>>> >>> +     pdata = pdev->dev.platform_data;
>>> >>> +     if (!pdata) {
>>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>> >>> __func__);
>>> >>> +             return -EINVAL;
>>> >>> +     }
>>> >>> +
>>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> >>> +     if (!phy_mem) {
>>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>> >>> +             return -ENODEV;
>>> >>> +     }
>>> >>> +
>>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>> >>> +     if (!phy_base) {
>>> >>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>>> >>> +             return -ENXIO;
>>> >>> +     }
>>> >>> +
>>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>> >>> +     if (!sec)
>>> >>> +             return -ENOMEM;
>>> >>> +
>>> >>> +     sec->dev                = &pdev->dev;
>>> >>> +     sec->plat               = pdata;
>>> >>> +     sec->regs               = phy_base;
>>> >>> +     sec->phy.dev            = sec->dev;
>>> >>> +     sec->phy.label          = "sec-usbphy";
>>> >>> +     sec->phy.init           = sec_usbphy_init;
>>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>> >>> +
>>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>> >>> +     if (ret)
>>> >>> +             goto err;
>>> >>> +
>>> >>> +     platform_set_drvdata(pdev, sec);
>>> >>> +
>>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>>> >>> +err:
>>> >>> +     return ret;
>>> >>> +}
>>> >>> +
>>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>> >>> +{
>>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>> >>> +
>>> >>> +     usb_remove_phy(&sec->phy);
>>> >>> +
>>> >>> +     if (sec->clk) {
>>> >>> +             clk_put(sec->clk);
>>> >>> +             sec->clk = NULL;
>>> >>> +     }
>>> >>> +
>>> >>> +     return 0;
>>> >>> +}
>>> >>> +
>>> >>> +#ifdef CONFIG_OF
>>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>> >>> +     {
>>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>>> >>> +             .data = (void *)TYPE_S3C64XX,
>>> >>> +     }, {
>>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>>> >>> +     },
>>> >>> +     {},
>>> >>> +};
>>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>> >>> +#else
>>> >>> +#define sec_usbphy_dt_match NULL
>>> >>> +#endif
>>> >>> +
>>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>> >>> +     {
>>> >>> +             .name           = "s3c64xx-usbphy",
>>> >>> +             .driver_data    = TYPE_S3C64XX,
>>> >>> +     }, {
>>> >>> +             .name           = "exynos4210-usbphy",
>>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>>> >>> +     },
>>> >>> +     {},
>>> >>> +};
>>> >>> +
>>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>> >>> +
>>> >>> +static struct platform_driver sec_usbphy_driver = {
>>> >>> +     .probe          = sec_usbphy_probe,
>>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>> >>> +     .id_table       = sec_usbphy_driver_ids,
>>> >>> +     .driver         = {
>>> >>> +             .name   = "sec-usbphy",
>>> >>> +             .owner  = THIS_MODULE,
>>> >>> +             .of_match_table = sec_usbphy_dt_match,
>>> >>> +     },
>>> >>> +};
>>> >>> +
>>> >>> +static int __init sec_usbphy_driver_init(void)
>>> >>> +{
>>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>>> >>> +}
>>> >>> +subsys_initcall(sec_usbphy_driver_init);
>>> >>> +
>>> >>> +static void __exit sec_usbphy_driver_exit(void)
>>> >>> +{
>>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>> >>> +}
>>> >>> +module_exit(sec_usbphy_driver_exit);
>>> >>> +
>>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>>> >>> +MODULE_LICENSE("GPL");
>>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>>> >>> index 0000000..06e81d4
>>> >>> --- /dev/null
>>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>>> >>> @@ -0,0 +1,48 @@
>>> >>> +/*
>>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>> >>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>>> >>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>> >>> + *
>>> >>> + * This program is free software; you can redistribute  it and/or
>>> >>> modify
>>> >>> it + * under  the terms of  the GNU General  Public License as
>>> >>> published by the + * Free Software Foundation;  either version 2 of
>>> >>> the  License, or
>>> >>> (at your + * option) any later version.
>>> >>> + */
>>> >>> +
>>> >>> +#ifndef __SEC_USBPHY_H
>>> >>> +#define __SEC_USBPHY_H
>>> >>> +
>>> >>> +#define S3C_PHYPWR                           (0x00)
>>> >>> +
>>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>> >>> +/* For Exynos4 */
>>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>> >>> +
>>> >>> +#define S3C_PHYCLK                           (0x04)
>>> >>> +
>>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>> >>> +
>>> >>> +#define S3C_RSTCON                           (0x08)
>>> >>> +
>>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>> >>> +
>>> >>> +#ifndef MHZ
>>> >>> +#define MHZ (1000*1000)
>>> >>> +#endif
>>> >>> +
>>> >>> +#endif /* __SEC_USBPHY_H */
>>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>> >>>
>>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>> >>>
>>> >>>  };
>>> >>>
>>> >>> +struct s3c_usbphy_plat {
>>> >>> +     void (*pmu_isolation)(int on);
>>> >>> +};
>>> >>> +
>>> >>>
>>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>> >>>
>>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>> >>>
>>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>> >>
>>> >> --
>>> >> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
>>> >> the body of a message to majordomo at vger.kernel.org
>>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>> >
>>> > --
>>> > To unsubscribe from this list: send the line "unsubscribe
>>> > linux-samsung-soc" in
>>> > the body of a message to majordomo at vger.kernel.org
>>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From kyungmin.park at samsung.com  Tue Aug  7 00:33:27 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Tue, 7 Aug 2012 13:33:27 +0900
Subject: [PATCH 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <CAD6zSYMsHUeR9=ERx=XO5OXvx2SK8C2xX1WX5qXbmXBpfCuO_w@mail.gmail.com>
References: <1343826351-8756-1-git-send-email-p.paneri@samsung.com>
 <CAD6zSYMkrPLuV+8ev4pz8M7qW8pFo2Q12jmW-pHqvdVREuW=Tw@mail.gmail.com>
 <CAH9JG2Wo83_rO6fEazWij9wo=w7atdCqeuqJUmCPJYeYQ4t5dw@mail.gmail.com>
 <201208061123.18065.heiko@sntech.de>
 <CAD6zSYPyRGgxVXFhcLSqjOpERq-jLrsqnjYNXM3jKsjymiLaTA@mail.gmail.com>
 <CAD6zSYMsHUeR9=ERx=XO5OXvx2SK8C2xX1WX5qXbmXBpfCuO_w@mail.gmail.com>
Message-ID: <CAH9JG2Ws=HfJNaNWhN8UvHnONdt9pLRhy4ALYrQOYO8hQytstg@mail.gmail.com>

On 8/7/12, Praveen Paneri <p.paneri at samsung.com> wrote:
> Hi,
>
> On Mon, Aug 6, 2012 at 3:21 PM, Praveen Paneri <p.paneri at samsung.com>
> wrote:
>> Hi,
>>
>> On Mon, Aug 6, 2012 at 2:53 PM, Heiko St?bner <heiko at sntech.de> wrote:
>>> Am Montag, 6. August 2012, 10:23:52 schrieb Kyungmin Park:
>>>> Hi Praveen,
>>>>
>>>> On 8/6/12, Praveen Paneri <p.paneri at samsung.com> wrote:
>>>> > Hi Heiko,
>>>> >
>>>> > On Mon, Aug 6, 2012 at 3:24 AM, Heiko St?bner <heiko at sntech.de>
>>>> > wrote:
>>>> >> Hi Praveen,
>>>> >>
>>>> >> Am Mittwoch, 1. August 2012, 15:05:47 schrieb Praveen Paneri:
>>>> >>> This driver uses usb_phy interface to interact with s3c-hsotg.
>>>> >>> Supports
>>>> >>> phy_init and phy_shutdown functions to enable/disable phy. Tested
>>>> >>> with
>>>> >>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>>> >>
>>>> >> Looks cool.
>>>> >
>>>> > Thanks
>>>> >
>>>> >> From what I've seen the phy controllers on newer Samsung SoCs are
>>>> >> still
>>>> >> somewhat similar to the one on my s3c2416/2450 machines. So hopefully
>>>> >> at
>>>> >> some
>>>> >> point after the driver has settled, I'll find the time to add
>>>> >> support
>>>> >> for these to the phy driver.
>>>> >
>>>> > Yes! that's great.
>>>> >
>>>> >> Out of curiosity, what does the "sec" in sec_usbphy for?
>>>> >
>>>> > Its Samsung Electronics Co. :)
>>>>
>>>> I'm also prefer to use 'samsung' or 'exynos'. Since I didn't see the
>>>> 'sec' prefix for samsung drivers.
>>>
>>> I'd second that. All new generic samsung drivers look like this (i.e.
>>> gpio-
>>> samsung, pwm-samsung).
> On the second thought I am thinking 'sec' is shorter and cooler. I
> know that it has not
I also think about it. but most of people think 'sec' is "Securities
and Exchange Commission" or security instead of "Samsung Electronics".
Ans TLA is avoid if possible.

Thank you,
Kyungmin Park
> been used anywhere else but there is always a first time :-P The
> shorter string helps in
> writing the code; especially when we have 80 character restriction. If
> you go through
> this driver itself you will realize this. Also there was a suggestion
> some time back to
> use 'sec' instead of 'samsung'.
> This is just my view about it. Please comment.
>
> Praveen
>
>>>
>>> Just checked the datasheets again. This general phy type is used in some
>>> form
>>> down to the S3C2443, so I'd prefer something with samsung in the name
>>> :-)
>> Yes! That makes sense. I will change the name to samsung_usbphy
>>
>> Praveen
>>>
>>>
>>> Heiko
>>>
>>>>
>>>> Thank you,
>>>> Kyungmin Park
>>>>
>>>> > Praveen
>>>> >
>>>> >>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>>>> >>
>>>> >> Acked-by: Heiko Stuebner <heiko at sntech.de>
>>>> >>
>>>> >>
>>>> >> Heiko
>>>> >>
>>>> >>> ---
>>>> >>>
>>>> >>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>>> >>>  drivers/usb/phy/Kconfig                            |    8 +
>>>> >>>  drivers/usb/phy/Makefile                           |    1 +
>>>> >>>  drivers/usb/phy/sec_usbphy.c                       |  354
>>>> >>>
>>>> >>> ++++++++++++++++++++ drivers/usb/phy/sec_usbphy.h
>>>> >>>
>>>> >>>  48 +++
>>>> >>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>>> >>>  6 files changed, 425 insertions(+), 0 deletions(-)
>>>> >>>  create mode 100644
>>>> >>>
>>>> >>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create
>>>> >>> mode
>>>> >>> 100644 drivers/usb/phy/sec_usbphy.c
>>>> >>>
>>>> >>>  create mode 100644 drivers/usb/phy/sec_usbphy.h
>>>> >>>
>>>> >>> diff --git
>>>> >>> a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>>> >>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt new file
>>>> >>> mode 100644
>>>> >>> index 0000000..fefd9c8
>>>> >>> --- /dev/null
>>>> >>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>>> >>> @@ -0,0 +1,9 @@
>>>> >>> +* Samsung's usb phy transceiver
>>>> >>> +
>>>> >>> +The Samsung's phy transceiver is used for controlling usb otg phy
>>>> >>> for
>>>> >>> +s3c-hsotg usb device controller.
>>>> >>> +
>>>> >>> +Required properties:
>>>> >>> +- compatible : should be "samsung,exynos4210-usbphy"
>>>> >>> +- reg : base physical address of the phy registers and length of
>>>> >>> memory mapped +      region.
>>>> >>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>>>> >>> index e7cf84f..abbebe2 100644
>>>> >>> --- a/drivers/usb/phy/Kconfig
>>>> >>> +++ b/drivers/usb/phy/Kconfig
>>>> >>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>>> >>>
>>>> >>>         To compile this driver as a module, choose M here: the
>>>> >>>         module will be called isp1301.
>>>> >>>
>>>> >>> +
>>>> >>> +config SEC_USBPHY
>>>> >>> +       bool "Samsung USB PHY controller Driver"
>>>> >>> +       depends on USB_S3C_HSOTG
>>>> >>> +       select USB_OTG_UTILS
>>>> >>> +       help
>>>> >>> +         Enable this to support Samsung USB phy controller for
>>>> >>> samsung
>>>> >>> +         SoCs.
>>>> >>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>>>> >>> index eca095b..6bb66f0 100644
>>>> >>> --- a/drivers/usb/phy/Makefile
>>>> >>> +++ b/drivers/usb/phy/Makefile
>>>> >>> @@ -5,3 +5,4 @@
>>>> >>>
>>>> >>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>>> >>>
>>>> >>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>>>> >>>
>>>> >>> +obj-$(CONFIG_SEC_USBPHY)             += sec_usbphy.o
>>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.c
>>>> >>> b/drivers/usb/phy/sec_usbphy.c new file mode 100644
>>>> >>> index 0000000..33119eb
>>>> >>> --- /dev/null
>>>> >>> +++ b/drivers/usb/phy/sec_usbphy.c
>>>> >>> @@ -0,0 +1,354 @@
>>>> >>> +/* linux/drivers/usb/phy/sec_usbphy.c
>>>> >>> + *
>>>> >>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>>>> >>> + *              http://www.samsung.com
>>>> >>> + *
>>>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>>> >>> + *
>>>> >>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG
>>>> >>> controller + *
>>>> >>> + * This program is free software; you can redistribute it and/or
>>>> >>> modify + * it under the terms of the GNU General Public License
>>>> >>> version 2 as + * published by the Free Software Foundation.
>>>> >>> + *
>>>> >>> + * This program is distributed in the hope that it will be useful,
>>>> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>> >>> + * GNU General Public License for more details.
>>>> >>> + *
>>>> >>> + * You should have received a copy of the GNU General Public
>>>> >>> License
>>>> >>> + * along with this program; if not, write to the Free Software
>>>> >>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>>>> >>> +*/
>>>> >>> +
>>>> >>> +#include <linux/module.h>
>>>> >>> +#include <linux/platform_device.h>
>>>> >>> +#include <linux/clk.h>
>>>> >>> +#include <linux/delay.h>
>>>> >>> +#include <linux/err.h>
>>>> >>> +#include <linux/io.h>
>>>> >>> +#include <linux/of.h>
>>>> >>> +#include <linux/usb/otg.h>
>>>> >>> +#include <linux/platform_data/s3c-hsotg.h>
>>>> >>> +
>>>> >>> +#include "sec_usbphy.h"
>>>> >>> +
>>>> >>> +enum sec_cpu_type {
>>>> >>> +     TYPE_S3C64XX,
>>>> >>> +     TYPE_EXYNOS4210,
>>>> >>> +};
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * struct sec_usbphy - transceiver driver state
>>>> >>> + * @phy: transceiver structure
>>>> >>> + * @plat: platform data
>>>> >>> + * @dev: The parent device supplied to the probe function
>>>> >>> + * @clk: usb phy clock
>>>> >>> + * @regs: usb phy register memory base
>>>> >>> + * @cpu_type: machine identifier
>>>> >>> + */
>>>> >>> +struct sec_usbphy {
>>>> >>> +     struct usb_phy  phy;
>>>> >>> +     struct s3c_usbphy_plat *plat;
>>>> >>> +     struct device   *dev;
>>>> >>> +     struct clk      *clk;
>>>> >>> +     void __iomem    *regs;
>>>> >>> +     int             cpu_type;
>>>> >>> +};
>>>> >>> +
>>>> >>> +#define phy_to_sec(x)                container_of((x), struct
>>>> >>> sec_usbphy, phy)
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * Enables or disables the phy clock
>>>> >>> + * returns 0 on success else the error
>>>> >>> + */
>>>> >>> +static int sec_usbphy_clk_control(struct sec_usbphy *sec, bool on)
>>>> >>> +{
>>>> >>> +     if (on) {
>>>> >>> +             if (!sec->clk) {
>>>> >>> +                     sec->clk = clk_get(sec->dev, "otg");
>>>> >>> +                     if (IS_ERR(sec->clk)) {
>>>> >>> +                             dev_err(sec->dev, "Failed to get otg
>>>> >>> clock\n");
>>>> >>> +                             return PTR_ERR(sec->clk);
>>>> >>> +                     }
>>>> >>> +             }
>>>> >>> +             clk_enable(sec->clk);
>>>> >>> +     } else {
>>>> >>> +             clk_disable(sec->clk);
>>>> >>> +             clk_put(sec->clk);
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     return 0;
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * Returns reference clock frequency
>>>> >>> + */
>>>> >>> +static int sec_usbphy_get_refclk_freq(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     struct clk *ref_clk;
>>>> >>> +     int refclk_freq = 0;
>>>> >>> +
>>>> >>> +     ref_clk = clk_get(sec->dev, "xusbxti");
>>>> >>> +     if (IS_ERR(ref_clk)) {
>>>> >>> +             dev_err(sec->dev, "Failed to get reference clock\n");
>>>> >>> +             return PTR_ERR(ref_clk);
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     switch (clk_get_rate(ref_clk)) {
>>>> >>> +     case 12 * MHZ:
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>>>> >>> +             break;
>>>> >>> +     case 24 * MHZ:
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>>>> >>> +             break;
>>>> >>> +     default:
>>>> >>> +     case 48 * MHZ:
>>>> >>> +             /* default reference clock */
>>>> >>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +     clk_put(ref_clk);
>>>> >>> +
>>>> >>> +     return refclk_freq;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static void sec_usbphy_enable(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     void __iomem *regs = sec->regs;
>>>> >>> +     u32 phypwr;
>>>> >>> +     u32 phyclk;
>>>> >>> +     u32 rstcon;
>>>> >>> +
>>>> >>> +     /* set clock frequency for PLL */
>>>> >>> +     phyclk = sec_usbphy_get_refclk_freq(sec);
>>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>>> >>> +     rstcon = readl(regs + S3C_RSTCON);
>>>> >>> +
>>>> >>> +     switch (sec->cpu_type) {
>>>> >>> +     case TYPE_S3C64XX:
>>>> >>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>>>> >>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>>> >>> +             break;
>>>> >>> +     case TYPE_EXYNOS4210:
>>>> >>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>>>> >>> +             rstcon |= S3C_RSTCON_PHY;
>>>> >>> +     default:
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     writel(phyclk, regs + S3C_PHYCLK);
>>>> >>> +     /* set to normal of PHY0 */
>>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>>> >>> +     /* reset all ports of PHY and Link */
>>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>>> >>> +     udelay(10);
>>>> >>> +     rstcon &= ~S3C_RSTCON_PHY;
>>>> >>> +     writel(rstcon, regs + S3C_RSTCON);
>>>> >>> +}
>>>> >>> +
>>>> >>> +static void sec_usbphy_disable(struct sec_usbphy *sec)
>>>> >>> +{
>>>> >>> +     void __iomem *regs = sec->regs;
>>>> >>> +     u32 phypwr;
>>>> >>> +
>>>> >>> +     phypwr = readl(regs + S3C_PHYPWR);
>>>> >>> +
>>>> >>> +     switch (sec->cpu_type) {
>>>> >>> +     case TYPE_S3C64XX:
>>>> >>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>>>> >>> +             break;
>>>> >>> +     case TYPE_EXYNOS4210:
>>>> >>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>>>> >>> +     default:
>>>> >>> +             break;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     /* unset to normal of PHY0 */
>>>> >>> +     writel(phypwr, regs + S3C_PHYPWR);
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * The function passed to the usb driver for phy initialization
>>>> >>> + */
>>>> >>> +static int sec_usbphy_init(struct usb_phy *phy)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +     int ret = 0;
>>>> >>> +
>>>> >>> +     sec = phy_to_sec(phy);
>>>> >>> +
>>>> >>> +     /* Enable the phy clock */
>>>> >>> +     ret = sec_usbphy_clk_control(sec, true);
>>>> >>> +     if (ret) {
>>>> >>> +             dev_err(sec->dev, "phy clock enable failed\n");
>>>> >>> +             return ret;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     /* Disable phy isolation */
>>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>>> >>> +             sec->plat->pmu_isolation(false);
>>>> >>> +
>>>> >>> +     /* Initialize usb phy registers */
>>>> >>> +     sec_usbphy_enable(sec);
>>>> >>> +     return ret;
>>>> >>> +}
>>>> >>> +
>>>> >>> +/*
>>>> >>> + * The function passed to the usb driver for phy shutdown
>>>> >>> + */
>>>> >>> +static void sec_usbphy_shutdown(struct usb_phy *phy)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +
>>>> >>> +     sec = phy_to_sec(phy);
>>>> >>> +
>>>> >>> +     /* De-initialize usb phy registers */
>>>> >>> +     sec_usbphy_disable(sec);
>>>> >>> +
>>>> >>> +     /* Enable phy isolation */
>>>> >>> +     if (sec->plat && sec->plat->pmu_isolation)
>>>> >>> +             sec->plat->pmu_isolation(true);
>>>> >>> +
>>>> >>> +     /* Disable the phy clock */
>>>> >>> +     sec_usbphy_clk_control(sec, false);
>>>> >>> +}
>>>> >>> +
>>>> >>> +static const struct of_device_id sec_usbphy_dt_match[];
>>>> >>> +
>>>> >>> +static inline int sec_usbphy_get_driver_data(struct
>>>> >>> platform_device
>>>> >>> *pdev)
>>>> >>> +{
>>>> >>> +#ifdef CONFIG_OF
>>>> >>> +     int data;
>>>> >>> +     if (pdev->dev.of_node) {
>>>> >>> +             const struct of_device_id *match;
>>>> >>> +             match = of_match_node(sec_usbphy_dt_match,
>>>> >>> pdev->dev.of_node);
>>>> >>> +             data = (int) match->data;
>>>> >>> +             return data;
>>>> >>> +     }
>>>> >>> +#endif
>>>> >>> +     return platform_get_device_id(pdev)->driver_data;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static int __devinit sec_usbphy_probe(struct platform_device
>>>> >>> *pdev)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec;
>>>> >>> +     struct s3c_usbphy_plat *pdata;
>>>> >>> +     struct device *dev = &pdev->dev;
>>>> >>> +     struct resource *phy_mem;
>>>> >>> +     void __iomem    *phy_base;
>>>> >>> +     int     ret;
>>>> >>> +
>>>> >>> +     pdata = pdev->dev.platform_data;
>>>> >>> +     if (!pdata) {
>>>> >>> +             dev_err(&pdev->dev, "%s: no platform data defined\n",
>>>> >>> __func__);
>>>> >>> +             return -EINVAL;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>> >>> +     if (!phy_mem) {
>>>> >>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>>>> >>> +             return -ENODEV;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>>>> >>> +     if (!phy_base) {
>>>> >>> +             dev_err(dev, "%s: register mapping failed\n",
>>>> >>> __func__);
>>>> >>> +             return -ENXIO;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     sec = devm_kzalloc(dev, sizeof(*sec), GFP_KERNEL);
>>>> >>> +     if (!sec)
>>>> >>> +             return -ENOMEM;
>>>> >>> +
>>>> >>> +     sec->dev                = &pdev->dev;
>>>> >>> +     sec->plat               = pdata;
>>>> >>> +     sec->regs               = phy_base;
>>>> >>> +     sec->phy.dev            = sec->dev;
>>>> >>> +     sec->phy.label          = "sec-usbphy";
>>>> >>> +     sec->phy.init           = sec_usbphy_init;
>>>> >>> +     sec->phy.shutdown       = sec_usbphy_shutdown;
>>>> >>> +     sec->cpu_type           = sec_usbphy_get_driver_data(pdev);
>>>> >>> +
>>>> >>> +     ret = usb_add_phy(&sec->phy, USB_PHY_TYPE_USB2);
>>>> >>> +     if (ret)
>>>> >>> +             goto err;
>>>> >>> +
>>>> >>> +     platform_set_drvdata(pdev, sec);
>>>> >>> +
>>>> >>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY
>>>> >>> module\n");
>>>> >>> +err:
>>>> >>> +     return ret;
>>>> >>> +}
>>>> >>> +
>>>> >>> +static int __exit sec_usbphy_remove(struct platform_device *pdev)
>>>> >>> +{
>>>> >>> +     struct sec_usbphy *sec = platform_get_drvdata(pdev);
>>>> >>> +
>>>> >>> +     usb_remove_phy(&sec->phy);
>>>> >>> +
>>>> >>> +     if (sec->clk) {
>>>> >>> +             clk_put(sec->clk);
>>>> >>> +             sec->clk = NULL;
>>>> >>> +     }
>>>> >>> +
>>>> >>> +     return 0;
>>>> >>> +}
>>>> >>> +
>>>> >>> +#ifdef CONFIG_OF
>>>> >>> +static const struct of_device_id sec_usbphy_dt_match[] = {
>>>> >>> +     {
>>>> >>> +             .compatible = "samsung,s3c64xx-usbphy",
>>>> >>> +             .data = (void *)TYPE_S3C64XX,
>>>> >>> +     }, {
>>>> >>> +             .compatible = "samsung,exynos4210-usbphy",
>>>> >>> +             .data = (void *)TYPE_EXYNOS4210,
>>>> >>> +     },
>>>> >>> +     {},
>>>> >>> +};
>>>> >>> +MODULE_DEVICE_TABLE(of, sec_usbphy_dt_match);
>>>> >>> +#else
>>>> >>> +#define sec_usbphy_dt_match NULL
>>>> >>> +#endif
>>>> >>> +
>>>> >>> +static struct platform_device_id sec_usbphy_driver_ids[] = {
>>>> >>> +     {
>>>> >>> +             .name           = "s3c64xx-usbphy",
>>>> >>> +             .driver_data    = TYPE_S3C64XX,
>>>> >>> +     }, {
>>>> >>> +             .name           = "exynos4210-usbphy",
>>>> >>> +             .driver_data    = TYPE_EXYNOS4210,
>>>> >>> +     },
>>>> >>> +     {},
>>>> >>> +};
>>>> >>> +
>>>> >>> +MODULE_DEVICE_TABLE(platform, sec_usbphy_driver_ids);
>>>> >>> +
>>>> >>> +static struct platform_driver sec_usbphy_driver = {
>>>> >>> +     .probe          = sec_usbphy_probe,
>>>> >>> +     .remove         = __devexit_p(sec_usbphy_remove),
>>>> >>> +     .id_table       = sec_usbphy_driver_ids,
>>>> >>> +     .driver         = {
>>>> >>> +             .name   = "sec-usbphy",
>>>> >>> +             .owner  = THIS_MODULE,
>>>> >>> +             .of_match_table = sec_usbphy_dt_match,
>>>> >>> +     },
>>>> >>> +};
>>>> >>> +
>>>> >>> +static int __init sec_usbphy_driver_init(void)
>>>> >>> +{
>>>> >>> +     return platform_driver_register(&sec_usbphy_driver);
>>>> >>> +}
>>>> >>> +subsys_initcall(sec_usbphy_driver_init);
>>>> >>> +
>>>> >>> +static void __exit sec_usbphy_driver_exit(void)
>>>> >>> +{
>>>> >>> +     return platform_driver_unregister(&sec_usbphy_driver);
>>>> >>> +}
>>>> >>> +module_exit(sec_usbphy_driver_exit);
>>>> >>> +
>>>> >>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>>>> >>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>>>> >>> +MODULE_LICENSE("GPL");
>>>> >>> +MODULE_ALIAS("platform:sec-usbphy");
>>>> >>> diff --git a/drivers/usb/phy/sec_usbphy.h
>>>> >>> b/drivers/usb/phy/sec_usbphy.h new file mode 100644
>>>> >>> index 0000000..06e81d4
>>>> >>> --- /dev/null
>>>> >>> +++ b/drivers/usb/phy/sec_usbphy.h
>>>> >>> @@ -0,0 +1,48 @@
>>>> >>> +/*
>>>> >>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>>>> >>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>>>> >>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>>>> >>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>>>> >>> + *
>>>> >>> + * This program is free software; you can redistribute  it and/or
>>>> >>> modify
>>>> >>> it + * under  the terms of  the GNU General  Public License as
>>>> >>> published by the + * Free Software Foundation;  either version 2 of
>>>> >>> the  License, or
>>>> >>> (at your + * option) any later version.
>>>> >>> + */
>>>> >>> +
>>>> >>> +#ifndef __SEC_USBPHY_H
>>>> >>> +#define __SEC_USBPHY_H
>>>> >>> +
>>>> >>> +#define S3C_PHYPWR                           (0x00)
>>>> >>> +
>>>> >>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>>>> >>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>>>> >>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>>>> >>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>>>> >>> +/* For Exynos4 */
>>>> >>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>>>> >>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>>>> >>> +
>>>> >>> +#define S3C_PHYCLK                           (0x04)
>>>> >>> +
>>>> >>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>>>> >>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>>>> >>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>>>> >>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>>>> >>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>>>> >>> +
>>>> >>> +#define S3C_RSTCON                           (0x08)
>>>> >>> +
>>>> >>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>>>> >>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>>>> >>> +#define S3C_RSTCON_PHY                               (1 << 0)
>>>> >>> +
>>>> >>> +#ifndef MHZ
>>>> >>> +#define MHZ (1000*1000)
>>>> >>> +#endif
>>>> >>> +
>>>> >>> +#endif /* __SEC_USBPHY_H */
>>>> >>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>>>> >>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e
>>>> >>> 100644
>>>> >>> --- a/include/linux/platform_data/s3c-hsotg.h
>>>> >>> +++ b/include/linux/platform_data/s3c-hsotg.h
>>>> >>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>>> >>>
>>>> >>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>>> >>>
>>>> >>>  };
>>>> >>>
>>>> >>> +struct s3c_usbphy_plat {
>>>> >>> +     void (*pmu_isolation)(int on);
>>>> >>> +};
>>>> >>> +
>>>> >>>
>>>> >>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>>>> >>>
>>>> >>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>>> >>>
>>>> >>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>>>> >>
>>>> >> --
>>>> >> To unsubscribe from this list: send the line "unsubscribe linux-usb"
>>>> >> in
>>>> >> the body of a message to majordomo at vger.kernel.org
>>>> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>> >
>>>> > --
>>>> > To unsubscribe from this list: send the line "unsubscribe
>>>> > linux-samsung-soc" in
>>>> > the body of a message to majordomo at vger.kernel.org
>>>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe
>>> linux-samsung-soc" in
>>> the body of a message to majordomo at vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From kyungmin.park at samsung.com  Tue Aug  7 00:36:07 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Tue, 7 Aug 2012 13:36:07 +0900
Subject: [PATCH] ARM: EXYNOS: Add USB HSIC device
In-Reply-To: <1344261462-14183-3-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344261462-14183-3-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAH9JG2Xjjp4JtHGWu681ycDCbz=zYJ2mEvW1H2pFMWJxncuM9Q@mail.gmail.com>

Hi,

Now another person try to use drivers/usb/phy for it.
"usb: phy: samsung: Introducing usb phy driver for hsotg"
Can you use it instead of previous one?

Thank you,
Kyungmin Park

On 8/6/12, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch support to control USB HSIC of EXYNOS4,
> edited based on Samsung's GT-i9100 ICS Opensource Update7.
>
> Change-Id: Ifba33c6a5166abf3644794eee6abe528bd71f521
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/mach-exynos/common.c                    |    5 +
>  arch/arm/mach-exynos/include/mach/regs-pmu.h     |   12 +
>  arch/arm/mach-exynos/include/mach/regs-usb-phy.h |   97 +++++
>  arch/arm/mach-exynos/setup-usb-phy.c             |  493
> ++++++++++++++++------
>  drivers/usb/host/Kconfig                         |   14 +
>  5 files changed, 501 insertions(+), 120 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 4eb39cd..94d58af 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -179,6 +179,11 @@ static struct map_desc exynos4_iodesc[] __initdata = {
>  		.length		= SZ_4K,
>  		.type		= MT_DEVICE,
>  	}, {
> +		.virtual	= (unsigned long)S5P_VA_GPIO2,
> +		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE,
> +	}, {
>  		.virtual	= (unsigned long)S5P_VA_DMC0,
>  		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
>  		.length		= SZ_64K,
> diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> index 0bb21e2..d98c2fe 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
> @@ -185,6 +185,15 @@
>  #define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
>
>  /* Only for EXYNOS4x12 */
> +#define S5P_USB_PHY_CONTROL			S5P_PMUREG(0x0704)
> +#define S5P_USB_PHY_ENABLE			(0x1 << 0)
> +
> +#define S5P_HSIC_1_PHY_CONTROL			S5P_PMUREG(0x0708)
> +#define S5P_HSIC_1_PHY_ENABLE			(0x1 << 0)
> +
> +#define S5P_HSIC_2_PHY_CONTROL			S5P_PMUREG(0x070C)
> +#define S5P_HSIC_2_PHY_ENABLE			(0x1 << 0)
> +
>  #define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
>  #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
>  #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
> @@ -242,6 +251,9 @@
>
>  #define EXYNOS5_SYS_WDTRESET					(1 << 20)
>
> +#define EXYNOS5_USBDEV_PHY_CONTROL			S5P_PMUREG(0x0704)
> +#define EXYNOS5_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)
> +
>  #define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)
>  #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)
>  #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)
> diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> index 0727773..79021a0 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> @@ -43,6 +43,43 @@
>  #define EXYNOS4210_CLKSEL_12M		(0x2 << 0)
>  #define EXYNOS4210_CLKSEL_24M		(0x3 << 0)
>
> +#define EXYNOS4210_HSIC1_NORMAL_MASK            (0x3 << 11)
> +#define EXYNOS4210_HSIC1_SLEEP                  (1 << 12)
> +#define EXYNOS4210_HSIC1_FORCE_SUSPEND          (1 << 11)
> +#define EXYNOS4210_HSIC0_NORMAL_MASK            (0x3 << 9)
> +#define EXYNOS4210_HSIC0_SLEEP                  (1 << 10)
> +#define EXYNOS4210_HSIC0_FORCE_SUSPEND          (1 << 9)
> +
> +#define EXYNOS4210_HOST_LINK_PORT_SWRST_MASK    (0xf << 6)
> +#define EXYNOS4210_HOST_LINK_PORT2_SWRST        (1 << 9)
> +#define EXYNOS4210_HOST_LINK_PORT1_SWRST        (1 << 8)
> +#define EXYNOS4210_HOST_LINK_PORT0_SWRST        (1 << 7)
> +#define EXYNOS4210_HOST_LINK_ALL_SWRST          (1 << 6)
> +#define EXYNOS4210_PHY1_SWRST_MASK              (0x7 << 3)
> +#define EXYNOS4210_PHY1_HSIC_SWRST              (1 << 5)
> +#define EXYNOS4210_PHY1_STD_SWRST               (1 << 4)
> +#define EXYNOS4210_PHY1_ALL_SWRST               (1 << 3)
> +
> +#define EXYNOS4X12_HSIC1_NORMAL_MASK		(0x7 << 12)
> +#define EXYNOS4X12_HSIC1_SLEEP			(1 << 14)
> +#define EXYNOS4X12_HSIC1_ANALOG_POWERDOWN	(1 << 13)
> +#define EXYNOS4X12_HSIC1_FORCE_SUSPEND		(1 << 12)
> +#define EXYNOS4X12_HSIC0_NORMAL_MASK		(0x7 << 9)
> +#define EXYNOS4X12_HSIC0_SLEEP			(1 << 11)
> +#define EXYNOS4X12_HSIC0_ANALOG_POWERDOWN	(1 << 10)
> +#define EXYNOS4X12_HSIC0_FORCE_SUSPEND		(1 << 9)
> +
> +#define EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK	(0xf << 7)
> +#define EXYNOS4X12_HOST_LINK_PORT2_SWRST	(1 << 10)
> +#define EXYNOS4X12_HOST_LINK_PORT1_SWRST	(1 << 9)
> +#define EXYNOS4X12_HOST_LINK_PORT0_SWRST	(1 << 8)
> +#define EXYNOS4X12_HOST_LINK_ALL_SWRST		(1 << 7)
> +#define EXYNOS4X12_PHY1_SWRST_MASK		(0xf << 3)
> +#define EXYNOS4X12_PHY1_HSIC1_SWRST		(1 << 6)
> +#define EXYNOS4X12_PHY1_HSIC0_SWRST		(1 << 5)
> +#define EXYNOS4X12_PHY1_SWRST			(1 << 4)
> +#define EXYNOS4X12_HOST_PHY_SWRST		(1 << 3)
> +
>  #define EXYNOS4X12_CLKSEL_MASK		(0x7 << 0)
>  #define EXYNOS4X12_CLKSEL_9600K		(0x0 << 0)
>  #define EXYNOS4X12_CLKSEL_10M		(0x1 << 0)
> @@ -71,4 +108,64 @@
>  #define EXYNOS4_PHY1CON			EXYNOS4_HSOTG_PHYREG(0x34)
>  #define FPENABLEN			(1 << 0)
>
> +/* For Exynos5 */
> +#define EXYNOS5_PHY_HOST_CTRL0                  EXYNOS4_HSOTG_PHYREG(0x00)
> +#define HOST_CTRL0_PHYSWRSTALL                  (0x1 << 31)
> +#define HOST_CTRL0_REFCLKSEL(val)               (val << 19)
> +#define EXYNOS5_CLKSEL_50M                      (0x7)
> +#define EXYNOS5_CLKSEL_24M                      (0x5)
> +#define EXYNOS5_CLKSEL_20M                      (0x4)
> +#define EXYNOS5_CLKSEL_19200K                   (0x3)
> +#define EXYNOS5_CLKSEL_12M                      (0x2)
> +#define EXYNOS5_CLKSEL_10M                      (0x1)
> +#define EXYNOS5_CLKSEL_9600K                    (0x0)
> +#define HOST_CTRL0_CLKSEL_SHIFT                 (16)
> +#define HOST_CTRL0_FSEL_MASK                    (0x7 << 16)
> +
> +#define HOST_CTRL0_COMMONON_N                   (0x1 << 9)
> +#define HOST_CTRL0_SIDDQ                        (0x1 << 6)
> +#define HOST_CTRL0_FORCESLEEP                   (0x1 << 5)
> +#define HOST_CTRL0_FORCESUSPEND                 (0x1 << 4)
> +#define HOST_CTRL0_WORDINTERFACE                (0x1 << 3)
> +#define HOST_CTRL0_UTMISWRST                    (0x1 << 2)
> +#define HOST_CTRL0_LINKSWRST                    (0x1 << 1)
> +#define HOST_CTRL0_PHYSWRST                     (0x1 << 0)
> +
> +#define EXYNOS5_PHY_HOST_TUNE0                  EXYNOS4_HSOTG_PHYREG(0x04)
> +#define EXYNOS5_PHY_HOST_TEST0                  EXYNOS4_HSOTG_PHYREG(0x08)
> +
> +#define EXYNOS5_PHY_HSIC_CTRL1                  EXYNOS4_HSOTG_PHYREG(0x10)
> +#define EXYNOS5_PHY_HSIC_CTRL2                  EXYNOS4_HSOTG_PHYREG(0x20)
> +#define HSIC_CTRL_REFCLKSEL(val)                ((val&0x3) << 23)
> +#define HSIC_CTRL_REFCLKDIV(val)                ((val&0x7f) << 16)
> +#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
> +#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
> +#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
> +#define HSIC_CTRL_WORDINTERFACE                 (0x1 << 3)
> +#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
> +#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
> +
> +#define EXYNOS5_PHY_HOST_EHCICTRL               EXYNOS4_HSOTG_PHYREG(0x30)
> +#define EHCICTRL_ENAINCRXALIGN                  (0x1 << 29)
> +#define EHCICTRL_ENAINCR4                       (0x1 << 28)
> +#define EHCICTRL_ENAINCR8                       (0x1 << 27)
> +#define EHCICTRL_ENAINCR16                      (0x1 << 26)
> +
> +#define EXYNOS5_PHY_HOST_OHCICTRL               EXYNOS4_HSOTG_PHYREG(0x34)
> +
> +#define EXYNOS5_PHY_OTG_SYS                     EXYNOS4_HSOTG_PHYREG(0x38)
> +#define OTG_SYS_PHYLINK_SW_RESET                (0x1 << 14)
> +#define OTG_SYS_LINK_SW_RST_UOTG                (0x1 << 13)
> +#define OTG_SYS_PHY0_SW_RST                     (0x1 << 12)
> +#define OTG_SYS_REF_CLK_SEL(val)                ((val&0x3) << 9)
> +#define OTG_SYS_REF_CLK_SEL_MASK                (0x3 << 9)
> +#define OTG_SYS_IP_PULLUP_UOTG                  (0x1 << 8)
> +#define OTG_SYS_COMMON_ON                       (0x1 << 7)
> +#define OTG_SYS_CLKSEL_SHIFT                    (4)
> +#define OTG_SYS_CTRL0_FSEL_MASK                 (0x7 << 4)
> +#define OTG_SYS_FORCE_SLEEP                     (0x1 << 3)
> +#define OTG_SYS_OTGDISABLE                      (0x1 << 2)
> +#define OTG_SYS_SIDDQ_UOTG                      (0x1 << 1)
> +#define OTG_SYS_FORCE_SUSPEND                   (0x1 << 0)
> +
>  #endif /* __PLAT_S5P_REGS_USB_PHY_H */
> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c
> b/arch/arm/mach-exynos/setup-usb-phy.c
> index b81cc56..c725745 100644
> --- a/arch/arm/mach-exynos/setup-usb-phy.c
> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright (C) 2011 Samsung Electronics Co.Ltd
> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>   * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>   *
>   *  This program is free software; you can redistribute  it and/or modify
> it
> @@ -19,205 +20,457 @@
>  #include <plat/cpu.h>
>  #include <plat/usb-phy.h>
>
> +#define ETC6PUD		(S5P_VA_GPIO2 + 0x228)
> +#define EXYNOS4_USB_CFG	(S3C_VA_SYS + 0x21C)
> +
> +#define PHY_ENABLE	(1 << 0)
> +#define PHY_DISABLE	(0)
> +
> +enum usb_host_type {
> +	HOST_PHY_EHCI	= (0x1 << 0),
> +	HOST_PHY_OHCI	= (0x1 << 1),
> +};
> +
> +enum usb_phy_type {
> +	USB_PHY		= (0x1 << 0),
> +	USB_PHY0	= (0x1 << 0),
> +	USB_PHY1	= (0x1 << 1),
> +	USB_PHY_HSIC0	= (0x1 << 1),
> +	USB_PHY_HSIC1	= (0x1 << 2),
> +};
> +
>  static atomic_t host_usage;
> +static DEFINE_MUTEX(phy_lock);
> +static struct clk *phy_clk;
>
>  static int exynos4_usb_host_phy_is_on(void)
>  {
>  	return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
>  }
>
> -static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
> +static int exynos4_usb_phy20_is_on(void)
>  {
> -	struct clk *xusbxti_clk;
> -	u32 phyclk;
> +	return exynos4_usb_host_phy_is_on();
> +}
> +
> +static int exynos_usb_phy_clock_enable(struct platform_device *pdev)
> +{
> +	int err;
> +
> +	if (!phy_clk) {
> +		if (soc_is_exynos4210() ||
> +				soc_is_exynos4212() || soc_is_exynos4412())
> +			phy_clk = clk_get(&pdev->dev, "otg");
> +		else
> +			phy_clk = clk_get(&pdev->dev, "usbhost");
> +
> +		if (IS_ERR(phy_clk)) {
> +			dev_err(&pdev->dev, "Failed to get phy clock\n");
> +			return PTR_ERR(phy_clk);
> +		}
> +	}
> +
> +	err = clk_enable(phy_clk);
> +
> +	return err;
> +}
>
> -	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
> -	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
> -		if (soc_is_exynos4210()) {
> -			/* set clock frequency for PLL */
> -			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
> -
> -			switch (clk_get_rate(xusbxti_clk)) {
> -			case 12 * MHZ:
> -				phyclk |= EXYNOS4210_CLKSEL_12M;
> -				break;
> -			case 48 * MHZ:
> -				phyclk |= EXYNOS4210_CLKSEL_48M;
> -				break;
> -			default:
> -			case 24 * MHZ:
> -				phyclk |= EXYNOS4210_CLKSEL_24M;
> -				break;
> -			}
> -			writel(phyclk, EXYNOS4_PHYCLK);
> -		} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
> -			/* set clock frequency for PLL */
> -			phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
> -
> -			switch (clk_get_rate(xusbxti_clk)) {
> -			case 9600 * KHZ:
> -				phyclk |= EXYNOS4X12_CLKSEL_9600K;
> -				break;
> -			case 10 * MHZ:
> -				phyclk |= EXYNOS4X12_CLKSEL_10M;
> -				break;
> -			case 12 * MHZ:
> -				phyclk |= EXYNOS4X12_CLKSEL_12M;
> -				break;
> -			case 19200 * KHZ:
> -				phyclk |= EXYNOS4X12_CLKSEL_19200K;
> -				break;
> -			case 20 * MHZ:
> -				phyclk |= EXYNOS4X12_CLKSEL_20M;
> -				break;
> -			default:
> -			case 24 * MHZ:
> -				/* default reference clock */
> -				phyclk |= EXYNOS4X12_CLKSEL_24M;
> -				break;
> -			}
> -			writel(phyclk, EXYNOS4_PHYCLK);
> +static int exynos_usb_phy_clock_disable(struct platform_device *pdev)
> +{
> +	if (!phy_clk) {
> +		if (soc_is_exynos4210() ||
> +				soc_is_exynos4212() || soc_is_exynos4412())
> +			phy_clk = clk_get(&pdev->dev, "otg");
> +		else
> +			phy_clk = clk_get(&pdev->dev, "usbhost");
> +		if (IS_ERR(phy_clk)) {
> +			dev_err(&pdev->dev, "Failed to get phy clock\n");
> +			return PTR_ERR(phy_clk);
>  		}
> -		clk_put(xusbxti_clk);
>  	}
> +
> +	clk_disable(phy_clk);
> +
> +	return 0;
>  }
>
> -static int exynos4210_usb_phy0_init(struct platform_device *pdev)
> +static u32 exynos_usb_phy_set_clock(struct platform_device *pdev)
>  {
> +	struct clk *ref_clk;
> +	u32 refclk_freq = 0;
> +
> +	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
> +		ref_clk = clk_get(&pdev->dev, "xusbxti");
> +	else
> +		ref_clk = clk_get(&pdev->dev, "ext_xtal");
> +
> +	if (IS_ERR(ref_clk)) {
> +		dev_err(&pdev->dev, "Failed to get reference clock\n");
> +		return PTR_ERR(ref_clk);
> +	}
> +
> +	if (soc_is_exynos4210()) {
> +		switch (clk_get_rate(ref_clk)) {
> +		case 12 * MHZ:
> +			refclk_freq = EXYNOS4210_CLKSEL_12M;
> +			break;
> +		case 48 * MHZ:
> +			refclk_freq = EXYNOS4210_CLKSEL_48M;
> +			break;
> +		case 24 * MHZ:
> +		default:
> +			/* default reference clock */
> +			refclk_freq = EXYNOS4210_CLKSEL_24M;
> +			break;
> +		}
> +	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
> +		switch (clk_get_rate(ref_clk)) {
> +		case 96 * 100000:
> +			refclk_freq = EXYNOS4X12_CLKSEL_9600K;
> +			break;
> +		case 10 * MHZ:
> +			refclk_freq = EXYNOS4X12_CLKSEL_10M;
> +			break;
> +		case 12 * MHZ:
> +			refclk_freq = EXYNOS4X12_CLKSEL_12M;
> +			break;
> +		case 192 * 100000:
> +			refclk_freq = EXYNOS4X12_CLKSEL_19200K;
> +			break;
> +		case 20 * MHZ:
> +			refclk_freq = EXYNOS4X12_CLKSEL_20M;
> +			break;
> +		case 24 * MHZ:
> +		default:
> +			/* default reference clock */
> +			refclk_freq = EXYNOS4X12_CLKSEL_24M;
> +			break;
> +		}
> +	} else {
> +		switch (clk_get_rate(ref_clk)) {
> +		case 96 * 100000:
> +			refclk_freq = EXYNOS5_CLKSEL_9600K;
> +			break;
> +		case 10 * MHZ:
> +			refclk_freq = EXYNOS5_CLKSEL_10M;
> +			break;
> +		case 12 * MHZ:
> +			refclk_freq = EXYNOS5_CLKSEL_12M;
> +			break;
> +		case 192 * 100000:
> +			refclk_freq = EXYNOS5_CLKSEL_19200K;
> +			break;
> +		case 20 * MHZ:
> +			refclk_freq = EXYNOS5_CLKSEL_20M;
> +			break;
> +		case 50 * MHZ:
> +			refclk_freq = EXYNOS5_CLKSEL_50M;
> +			break;
> +		case 24 * MHZ:
> +		default:
> +			/* default reference clock */
> +			refclk_freq = EXYNOS5_CLKSEL_24M;
> +			break;
> +		}
> +	}
> +	clk_put(ref_clk);
> +
> +	return refclk_freq;
> +}
> +
> +static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on)
> +{
> +	if (soc_is_exynos4210()) {
> +		if (phy_type & USB_PHY0)
> +			writel(on, S5P_USBDEVICE_PHY_CONTROL);
> +		if (phy_type & USB_PHY1)
> +			writel(on, S5P_USBHOST_PHY_CONTROL);
> +	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {
> +		if (phy_type & USB_PHY)
> +			writel(on, S5P_USB_PHY_CONTROL);
> +#ifdef CONFIG_USB_S5P_HSIC0
> +		if (phy_type & USB_PHY_HSIC0)
> +			writel(on, S5P_HSIC_1_PHY_CONTROL);
> +#endif
> +#ifdef CONFIG_USB_S5P_HSIC1
> +		if (phy_type & USB_PHY_HSIC1)
> +			writel(on, S5P_HSIC_2_PHY_CONTROL);
> +#endif
> +	} else {
> +		if (phy_type & USB_PHY0)
> +			writel(on, EXYNOS5_USBDEV_PHY_CONTROL);
> +		if (phy_type & USB_PHY1)
> +			writel(on, EXYNOS5_USBHOST_PHY_CONTROL);
> +	}
> +}
> +
> +static int exynos4_usb_phy0_init(struct platform_device *pdev)
> +{
> +	u32 phypwr;
> +	u32 phyclk;
>  	u32 rstcon;
>
> -	writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
> -			S5P_USBDEVICE_PHY_CONTROL);
> +	exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
>
> -	exynos4210_usb_phy_clkset(pdev);
> +	/* set clock frequency for PLL */
> +	phyclk = exynos_usb_phy_set_clock(pdev);
> +	phyclk &= ~(PHY0_COMMON_ON_N);
> +	writel(phyclk, EXYNOS4_PHYCLK);
>
> -	/* set to normal PHY0 */
> -	writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
> +	/* set to normal of PHY0 */
> +	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
> +	writel(phypwr, EXYNOS4_PHYPWR);
>
> -	/* reset PHY0 and Link */
> +	/* reset all ports of both PHY and Link */
>  	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
>  	writel(rstcon, EXYNOS4_RSTCON);
>  	udelay(10);
> -
>  	rstcon &= ~PHY0_SWRST_MASK;
>  	writel(rstcon, EXYNOS4_RSTCON);
>
>  	return 0;
>  }
>
> -static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
> +static int exynos4_usb_phy0_exit(struct platform_device *pdev)
>  {
> -	writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
> -				PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
> +	/* unset to normal of PHY0 */
> +	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
> +			EXYNOS4_PHYPWR);
>
> -	writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
> -			S5P_USBDEVICE_PHY_CONTROL);
> +	exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
>
>  	return 0;
>  }
>
> -static int exynos4210_usb_phy1_init(struct platform_device *pdev)
> +static int exynos4_usb_phy1_init(struct platform_device *pdev)
>  {
> -	struct clk *otg_clk;
> +	u32 phypwr;
> +	u32 phyclk;
>  	u32 rstcon;
> -	int err;
>
>  	atomic_inc(&host_usage);
>
> -	otg_clk = clk_get(&pdev->dev, "otg");
> -	if (IS_ERR(otg_clk)) {
> -		dev_err(&pdev->dev, "Failed to get otg clock\n");
> -		return PTR_ERR(otg_clk);
> +	if (exynos4_usb_host_phy_is_on()) {
> +		dev_err(&pdev->dev, "Already power on PHY\n");
> +		return 0;
>  	}
>
> -	err = clk_enable(otg_clk);
> -	if (err) {
> -		clk_put(otg_clk);
> -		return err;
> -	}
> +	/*
> +	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
> +	 *  0x0 : pull-up/down disabled
> +	 *  0x1 : pull-down enabled
> +	 *  0x2 : reserved
> +	 *  0x3 : pull-up enabled
> +	 */
> +	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
> +		ETC6PUD);
>
> -	if (exynos4_usb_host_phy_is_on())
> -		return 0;
> +	exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
>
> -	writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
> -			S5P_USBHOST_PHY_CONTROL);
> +	/* set clock frequency for PLL */
> +	phyclk = exynos_usb_phy_set_clock(pdev);
> +	phyclk &= ~(PHY1_COMMON_ON_N);
> +	writel(phyclk, EXYNOS4_PHYCLK);
>
> -	exynos4210_usb_phy_clkset(pdev);
> +	/* set to normal HSIC 0 and 1 of PHY1 */
> +	phypwr = readl(EXYNOS4_PHYPWR);
> +	phypwr &= ~(PHY1_STD_NORMAL_MASK
> +		| EXYNOS4210_HSIC0_NORMAL_MASK);
> +	writel(phypwr, EXYNOS4_PHYPWR);
>
>  	/* floating prevention logic: disable */
>  	writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
>
> -	/* set to normal HSIC 0 and 1 of PHY1 */
> -	writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
> -			EXYNOS4_PHYPWR);
> -
> -	/* set to normal standard USB of PHY1 */
> -	writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
> -
>  	/* reset all ports of both PHY and Link */
> -	rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
> -		PHY1_SWRST_MASK;
> +	rstcon = readl(EXYNOS4_RSTCON)
> +		| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
> +		| EXYNOS4210_PHY1_SWRST_MASK;
>  	writel(rstcon, EXYNOS4_RSTCON);
>  	udelay(10);
>
> -	rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
> +	rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
> +		| EXYNOS4210_PHY1_SWRST_MASK);
>  	writel(rstcon, EXYNOS4_RSTCON);
>  	udelay(80);
>
> -	clk_disable(otg_clk);
> -	clk_put(otg_clk);
> +	return 0;
> +}
> +
> +static int exynos4_usb_phy1_exit(struct platform_device *pdev)
> +{
> +	u32 phypwr;
> +
> +	if (atomic_dec_return(&host_usage) > 0) {
> +		dev_info(&pdev->dev, "still being used\n");
> +		return -EBUSY;
> +	}
> +
> +	phypwr = readl(EXYNOS4_PHYPWR)
> +		| PHY1_STD_NORMAL_MASK
> +		| EXYNOS4210_HSIC0_NORMAL_MASK;
> +	writel(phypwr, EXYNOS4_PHYPWR);
> +
> +	exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
>
>  	return 0;
>  }
>
> -static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
> +static int exynos4_usb_phy20_init(struct platform_device *pdev)
>  {
> -	struct clk *otg_clk;
> -	int err;
> +	u32 phypwr, phyclk, rstcon;
>
> -	if (atomic_dec_return(&host_usage) > 0)
> -		return 0;
> +	atomic_inc(&host_usage);
>
> -	otg_clk = clk_get(&pdev->dev, "otg");
> -	if (IS_ERR(otg_clk)) {
> -		dev_err(&pdev->dev, "Failed to get otg clock\n");
> -		return PTR_ERR(otg_clk);
> +	if (exynos4_usb_phy20_is_on()) {
> +		dev_err(&pdev->dev, "Already power on PHY\n");
> +		return 0;
>  	}
>
> -	err = clk_enable(otg_clk);
> -	if (err) {
> -		clk_put(otg_clk);
> -		return err;
> +	/*
> +	 *  set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
> +	 *  0x0 : pull-up/down disabled
> +	 *  0x1 : pull-down enabled
> +	 *  0x2 : reserved
> +	 *  0x3 : pull-up enabled
> +	 */
> +	writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
> +		ETC6PUD);
> +
> +	exynos_usb_phy_control(USB_PHY
> +		| USB_PHY_HSIC0,
> +		PHY_ENABLE);
> +
> +	/* set clock frequency for PLL */
> +	phyclk = exynos_usb_phy_set_clock(pdev);
> +	/* COMMON Block configuration during suspend */
> +	phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N);
> +	writel(phyclk, EXYNOS4_PHYCLK);
> +
> +	/* set to normal of Device */
> +	phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
> +	writel(phypwr, EXYNOS4_PHYPWR);
> +
> +	/* set to normal of Host */
> +	phypwr = readl(EXYNOS4_PHYPWR);
> +	phypwr &= ~(PHY1_STD_NORMAL_MASK
> +		| EXYNOS4X12_HSIC0_NORMAL_MASK);
> +	writel(phypwr, EXYNOS4_PHYPWR);
> +
> +	/* reset both PHY and Link of Device */
> +	rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
> +	writel(rstcon, EXYNOS4_RSTCON);
> +	udelay(10);
> +	rstcon &= ~PHY0_SWRST_MASK;
> +	writel(rstcon, EXYNOS4_RSTCON);
> +
> +	/* reset both PHY and Link of Host */
> +	rstcon = readl(EXYNOS4_RSTCON)
> +		| EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
> +		| EXYNOS4X12_PHY1_SWRST_MASK;
> +	writel(rstcon, EXYNOS4_RSTCON);
> +	udelay(10);
> +
> +	rstcon &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
> +		| EXYNOS4X12_PHY1_SWRST_MASK);
> +	writel(rstcon, EXYNOS4_RSTCON);
> +	udelay(80);
> +
> +	return 0;
> +}
> +
> +static int exynos4_usb_phy20_exit(struct platform_device *pdev)
> +{
> +	u32 phypwr;
> +
> +	if (atomic_dec_return(&host_usage) > 0) {
> +		dev_info(&pdev->dev, "still being used\n");
> +		return -EBUSY;
>  	}
>
> -	writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
> +	/* unset to normal of Device */
> +	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
>  			EXYNOS4_PHYPWR);
>
> -	writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
> -			S5P_USBHOST_PHY_CONTROL);
> +	/* unset to normal of Host */
> +	phypwr = readl(EXYNOS4_PHYPWR)
> +		| PHY1_STD_NORMAL_MASK
> +		| EXYNOS4X12_HSIC0_NORMAL_MASK;
> +	writel(phypwr, EXYNOS4_PHYPWR);
>
> -	clk_disable(otg_clk);
> -	clk_put(otg_clk);
> +	exynos_usb_phy_control(USB_PHY
> +		| USB_PHY_HSIC0,
> +		PHY_DISABLE);
> +
> +	return 0;
> +}
> +
> +static int exynos_usb_dev_phy20_init(struct platform_device *pdev)
> +{
> +	if (soc_is_exynos4212() || soc_is_exynos4412())
> +		exynos4_usb_phy20_init(pdev);
> +
> +	writel(0, EXYNOS4_USB_CFG);
> +
> +	return 0;
> +}
> +
> +static int exynos_usb_dev_phy20_exit(struct platform_device *pdev)
> +{
> +	if (soc_is_exynos4212() || soc_is_exynos4412())
> +		exynos4_usb_phy20_exit(pdev);
>
>  	return 0;
>  }
>
>  int s5p_usb_phy_init(struct platform_device *pdev, int type)
>  {
> -	if (type == S5P_USB_PHY_DEVICE)
> -		return exynos4210_usb_phy0_init(pdev);
> -	else if (type == S5P_USB_PHY_HOST)
> -		return exynos4210_usb_phy1_init(pdev);
> +	int ret = -EINVAL;
> +
> +	if (exynos_usb_phy_clock_enable(pdev))
> +		return ret;
> +
> +	mutex_lock(&phy_lock);
> +	if (type == S5P_USB_PHY_HOST) {
> +		if (soc_is_exynos4210())
> +			ret = exynos4_usb_phy1_init(pdev);
> +		else if (soc_is_exynos4212() || soc_is_exynos4412())
> +			ret = exynos4_usb_phy20_init(pdev);
> +	} else if (type == S5P_USB_PHY_DEVICE) {
> +		if (soc_is_exynos4210())
> +			ret = exynos4_usb_phy0_init(pdev);
> +		else
> +			ret = exynos_usb_dev_phy20_init(pdev);
> +	}
> +
> +	mutex_unlock(&phy_lock);
> +	exynos_usb_phy_clock_disable(pdev);
>
> -	return -EINVAL;
> +	return ret;
>  }
>
>  int s5p_usb_phy_exit(struct platform_device *pdev, int type)
>  {
> -	if (type == S5P_USB_PHY_DEVICE)
> -		return exynos4210_usb_phy0_exit(pdev);
> -	else if (type == S5P_USB_PHY_HOST)
> -		return exynos4210_usb_phy1_exit(pdev);
> +	int ret = -EINVAL;
> +
> +	if (exynos_usb_phy_clock_enable(pdev))
> +		return ret;
> +
> +	mutex_lock(&phy_lock);
> +
> +	if (type == S5P_USB_PHY_HOST) {
> +		if (soc_is_exynos4210())
> +			ret = exynos4_usb_phy1_exit(pdev);
> +		else if (soc_is_exynos4212() || soc_is_exynos4412())
> +			ret = exynos4_usb_phy20_exit(pdev);
> +	} else if (type == S5P_USB_PHY_DEVICE) {
> +		if (soc_is_exynos4210())
> +			ret = exynos4_usb_phy0_exit(pdev);
> +		else
> +			ret = exynos_usb_dev_phy20_exit(pdev);
> +	}
> +
> +	mutex_unlock(&phy_lock);
> +	exynos_usb_phy_clock_disable(pdev);
>
> -	return -EINVAL;
> +	return ret;
>  }
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 075d2ec..5f69041 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -199,6 +199,20 @@ config USB_EHCI_S5P
>         help
>  	 Enable support for the S5P SOC's on-chip EHCI controller.
>
> +config USB_S5P_HSIC0
> +    boolean "S5P HSIC0 support"
> +    depends on USB_EHCI_HCD && PLAT_S5P && USB_EHCI_S5P
> +    default n
> +    help
> +      Enable support for the S5P SOC's on-chip HSIC PHY.
> +
> +config USB_S5P_HSIC1
> +    boolean "S5P HSIC1 support"
> +    depends on USB_EHCI_HCD && PLAT_S5P && USB_EHCI_S5P
> +    default n
> +    help
> +      Enable support for the S5P SOC's on-chip HSIC PHY.
> +
>  config USB_EHCI_MV
>  	bool "EHCI support for Marvell on-chip controller"
>  	depends on USB_EHCI_HCD && (ARCH_PXA || ARCH_MMP)
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From balbi at ti.com  Tue Aug  7 01:43:44 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 7 Aug 2012 08:43:44 +0300
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
In-Reply-To: <20120806154214.GC29272@sirena.org.uk>
References: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
 <20120806093033.GH17551@arwen.pp.htv.fi>
 <20120806154214.GC29272@sirena.org.uk>
Message-ID: <20120807054342.GF8468@arwen.pp.htv.fi>

Hi,

On Mon, Aug 06, 2012 at 04:42:14PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 12:30:34PM +0300, Felipe Balbi wrote:
> > On Mon, Aug 06, 2012 at 02:58:44PM +0530, Sourav Poddar wrote:
> > > There is an automatic binding done for I2C devices in the of_i2c core
> > > code. So, DT will be able to bind to any I2C device using the
> > > already existing table: MODULE_DEVICE_TABLE(i2c, bmp085_id).
> 
> > Acked-by: Felipe Balbi <balbi at ti.com>
> 
> It's good practice to have an explict compatible string even if the
> default happens to work in order to avoid any name clashes.

of_i2c.c makes no use whatsoever of the compatible string. See that it
will build an i2c_boardinfo and register a new device. That compatible
string is just churn and has no use at all.

-- 
balbi
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From balbi at ti.com  Tue Aug  7 01:51:29 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue,  7 Aug 2012 08:51:29 +0300
Subject: [PATCH] i2c: omap: sanitize exit path
Message-ID: <1344318689-24522-1-git-send-email-balbi@ti.com>

move the goto out label one line down, so that
it can be used when stat is read as zero. All
other exits, can be done with a break statement.

While at that, also break out as soon as we
complete draining IRQ, since at that time
we know we transferred everything there was
to be transferred.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 22efaba..57c2824 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -898,27 +898,26 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
-			spin_unlock_irqrestore(&dev->lock, flags);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
-			goto out;
+			break;
 		}
 
 		/*
@@ -931,7 +930,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 						OMAP_I2C_STAT_ARDY));
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RDR) {
@@ -946,7 +945,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 				i2c_omap_errata_i207(dev, stat);
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RRDY) {
@@ -969,10 +968,10 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XRDY) {
@@ -984,7 +983,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
@@ -994,19 +993,20 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 			dev_err(dev->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
-			goto out;
+			break;
 		}
 	} while (stat);
 
-out:
 	omap_i2c_complete_cmd(dev, err);
+
+out:
 	spin_unlock_irqrestore(&dev->lock, flags);
 
 	return IRQ_HANDLED;
-- 
1.7.12.rc0



From grinberg at compulab.co.il  Tue Aug  7 01:58:09 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 07 Aug 2012 08:58:09 +0300
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce
 time for ads7846"
In-Reply-To: <871ujj7ngd.fsf@ti.com>
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
 <871ujj7ngd.fsf@ti.com>
Message-ID: <5020AE71.1060405@compulab.co.il>

On 08/06/12 23:52, Kevin Hilman wrote:
> Igor Grinberg <grinberg at compulab.co.il> writes:
> 
>> 1) The above commit introduced a common ->get_pendown_state() function
>> into the generic code, but that function was board-specific for the
>> OMAP3EVM and thus broke most other boards using this code.
>>
>> 2) The above commit was mis-merged introducing another bug which
>> prevents the ads7846 driver probe function to succeed.
>> The omap_ads7846_init() function frees the pendown GPIO in case there is
>> no ->get_pendown_state() function set by the caller (board specific
>> code), so it can be requested later by the ads7846 driver.
>> The above commit add a common ->get_pendown_state() function without
>> removing the gpio_free() call and thus once the ads7846 driver tries
>> to use the pendown GPIO, it crashes as the pendown GPIO has not been
>> requested.
>>
>> 3) The above commit introduces NO new functionality as
>> get_pendown_state() function is already implemented in a suitable way by
>> the ads7846 driver and the debounce time handling has already been
>> fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).
>>
>> This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.
>>
>> Conflicts:
>> 	arch/arm/mach-omap2/common-board-devices.c
>>
>> Solved by taking the working version prior to the above commit.
>>
>> Cc: Zumeng Chen <zumeng.chen at windriver.com>
>> Cc: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>> ---
>> Kevin, sorry for the late reply.
>> How about the above commit message and the below patch?
>>
>> The patch applies cleanly to Tony's master branch (6 Aug 2012)
>> or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
>> after resetting two top most commits.
> 
> Now that v3.6-rc1 is out, it should probalby be applied on top of -rc1.
> I've taken care of that and tested as well.
> 
>> This patch has been tested on both above branches on cm-t3730.
>> Any other board tested will be greately appreciated.
>>
>> Also, if after all said in the commit message, you still don't
>> want to revert the original patch, feel free to post your thoughts.
> 
> After all the digging I did, I agree that the revert is the best
> solution.  
> 
> While it's a slightly different problem/bug, I think the gpio_free() in
> common-board-devices.c should still be unconditonal since the
> gpio_request() is now unconditional.  That can be a separate patch though.

Well, the logic behind the conditional gpio_free() is:
if a board specific code provides a board specific get_pendown_state()
function (which is different from the one in the ads7846 driver),
that board will not need to re-request the pendown GPIO (duplicate code).
If we free the pendown GPIO unconditionally, then the board specific code
will have to re-request it.
So, I think, no - it should be conditional.

> 
> Acked-by: Kevin Hilman <khilman at ti.com>
> Tested-by: Kevin Hilman <khilman at ti.com>
> 
> Tested on 3430/n900, 3530/Overo, 3730/Overo STORM, 3730/BB-xM.

Thanks!

[...]


-- 
Regards,
Igor.


From grinberg at compulab.co.il  Tue Aug  7 02:05:08 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 07 Aug 2012 09:05:08 +0300
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and debounce
 time for ads7846"
In-Reply-To: <5020726D.1030300@windriver.com>
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
 <5020726D.1030300@windriver.com>
Message-ID: <5020B014.60103@compulab.co.il>

On 08/07/12 04:42, Zumeng Chen wrote:
> ? 2012?08?07? 04:22, Igor Grinberg ??:
>> 1) The above commit introduced a common ->get_pendown_state() function
>> into the generic code, but that function was board-specific for the
>> OMAP3EVM and thus broke most other boards using this code.
>>
>> 2) The above commit was mis-merged introducing another bug which
>> prevents the ads7846 driver probe function to succeed.
>> The omap_ads7846_init() function frees the pendown GPIO in case there is
>> no ->get_pendown_state() function set by the caller (board specific
>> code), so it can be requested later by the ads7846 driver.
>> The above commit add a common ->get_pendown_state() function without
>> removing the gpio_free() call and thus once the ads7846 driver tries
>> to use the pendown GPIO, it crashes as the pendown GPIO has not been
>> requested.
>>
>> 3) The above commit introduces NO new functionality as
>> get_pendown_state() function is already implemented in a suitable way by
>> the ads7846 driver and the debounce time handling has already been
>> fixed by commit 97ee9f01 (ARM: OMAP: fix the ads7846 init code).
> Igor,
> 
> I suspect these two patches(this and 97ee9f01) works well, and there
> is something new introduced in ads7846.c, I'll try to look at that new
> stuff in this weekend.
> 
> Please refer to in-line comments:
> 
> Regards,
> Zumeng
>>
>> This reverts commit 16aced80f6739beb2a6ff7b6f96c83ba80d331e8.
>>
>> Conflicts:
>> 	arch/arm/mach-omap2/common-board-devices.c
>>
>> Solved by taking the working version prior to the above commit.
>>
>> Cc: Zumeng Chen <zumeng.chen at windriver.com>
>> Cc: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>> ---
>> Kevin, sorry for the late reply.
>> How about the above commit message and the below patch?
>>
>> The patch applies cleanly to Tony's master branch (6 Aug 2012)
>> or Kevin's kevin-omap-pm/for_3.6/fixes/ads7846
>> after resetting two top most commits.
>>
>> This patch has been tested on both above branches on cm-t3730.
>> Any other board tested will be greately appreciated.
>>
>> Also, if after all said in the commit message, you still don't
>> want to revert the original patch, feel free to post your thoughts.
>>
>>  arch/arm/mach-omap2/board-omap3evm.c       |    1 +
>>  arch/arm/mach-omap2/common-board-devices.c |   11 -----------
>>  arch/arm/mach-omap2/common-board-devices.h |    1 -
>>  3 files changed, 1 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
>> index ef230a0..0d362e9 100644
>> --- a/arch/arm/mach-omap2/board-omap3evm.c
>> +++ b/arch/arm/mach-omap2/board-omap3evm.c
>> @@ -58,6 +58,7 @@
>>  #include "hsmmc.h"
>>  #include "common-board-devices.h"
>>  
>> +#define OMAP3_EVM_TS_GPIO	175
>>  #define OMAP3_EVM_EHCI_VBUS	22
>>  #define OMAP3_EVM_EHCI_SELECT	61
>>  
>> diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
>> index 1473474..c187586 100644
>> --- a/arch/arm/mach-omap2/common-board-devices.c
>> +++ b/arch/arm/mach-omap2/common-board-devices.c
>> @@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
>>  	.turbo_mode	= 0,
>>  };
>>  
>> -/*
>> - * ADS7846 driver maybe request a gpio according to the value
>> - * of pdata->get_pendown_state, but we have done this. So set
>> - * get_pendown_state to avoid twice gpio requesting.
>> - */
>> -static int omap3_get_pendown_state(void)
>> -{
>> -	return !gpio_get_value(OMAP3_EVM_TS_GPIO);
>> -}
>> -
>>  static struct ads7846_platform_data ads7846_config = {
>>  	.x_max			= 0x0fff,
>>  	.y_max			= 0x0fff,
>> @@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
>>  	.debounce_rep		= 1,
>>  	.gpio_pendown		= -EINVAL,
>>  	.keep_vref_on		= 1,
>> -	.get_pendown_state	= &omap3_get_pendown_state,
> You remove this, then please look at the following codes:
> 
> drivers/input/touchscreen/ads7846.c
> 
> 969 if (pdata->get_pendown_state) {
> 970 ts->get_pendown_state = pdata->get_pendown_state;
> 971 } else if (gpio_is_valid(pdata->gpio_pendown)) {
> 972
> 973 err = gpio_request_one(pdata->gpio_pendown, GPIOF_IN,
> ^^^, the driver will want to request again, then it should
> be error if i'm right.

This patch removes the get_pendown_state function pointer from
the ads7846_platform_data and gpio_free() fires as there is no
get_pendown_state and therefore there will be no problem to request
it again by the ads7846 driver.
So, no there will be no error and if you still doubt, please test.

> 
> 974 "ads7846_pendown");
> 975 if (err) {
> 976 dev_err(&spi->dev,
> 977 "failed to request/setup pendown GPIO%d: %d\n",
> 978 pdata->gpio_pendown, err);
> 979 return err;
> 980 }
> 981
> 982 ts->gpio_pendown = pdata->gpio_pendown;
> 983
> 984 } else {

[...]


-- 
Regards,
Igor.


From s.hauer at pengutronix.de  Tue Aug  7 02:35:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 7 Aug 2012 08:35:58 +0200
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120806214121.GA26698@opensource.wolfsonmicro.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
 <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
 <20120806214121.GA26698@opensource.wolfsonmicro.com>
Message-ID: <20120807063558.GE1451@pengutronix.de>

On Mon, Aug 06, 2012 at 10:41:22PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 03:39:50PM -0500, Matt Sealey wrote:
> > On Mon, Aug 6, 2012 at 3:16 PM, Robert Schwebel
> 
> > > That's not true; we still run MX25, MX27, MX35, MX28 on mainline in
> > > active projects.
> 
> > I think Shawn Guo (FSL/Linaro) would also disagree, since he's just
> > posted a large amount of MXS patches to fix up the board for device
> > trees, and Arnd is pulling them.
> 
> MXS != i.MX.
> 
> > As far as I know, the FIQ usage is quite valid for the processor it
> > needs to run on (MX21/27/28, right?) in the modes it runs in (AC97 on
> > these processors, and maybe MX35 too), and I'm just trying to figure
> > out what the steps are for
> 
> Oh, ick.  What is the problem that means people want to use the FIQ on
> these processors?  There's been i.MX2x audio DMA since forever, it had
> DMA in mainline before any of the later i.MXs due to them having SDMA.
> The original mainline i.MX audio support was done on i.MX27 and didn't
> have any issue here, this is the fist I've heard of a problem.

Originally the FIQ support was only used because there hasn't been SDMA
support available at that time.
Nowadays the FIQ support is necessary only for AC97. The AC97 support in
the SSI unit is buggy: It does not allow you to select the slots you
want to receive. At least the wm9712 codec always sends (apart from the
stereo data) data in slot (I think it is) 12. You find this data mixed
in your audio stream. The FIQ driver skips this data to get a valid
audio stream.

One other way to solve this would be to use dma here and to filter out
the data afterwards.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linus.walleij at linaro.org  Tue Aug  7 02:49:17 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 08:49:17 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <201208060844.29333.arnd@arndb.de>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
Message-ID: <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>

On Mon, Aug 6, 2012 at 10:44 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Saturday 28 July 2012, Haojian Zhuang wrote:
>> +Required subnode-properties:
>> +- marvell,pins : An array of strings. Each string contains the name of a pin
>> +                 or group.
>> +- marvell,function     : A string containing the name of the function to mux to the
>> +                 pin or group.
>> +- marvell,drive-strength : An integer value that means the drive strength of a
>> +                        pin.
>> +- marvell,pull-up      : The property means a pin is pull up for input.
>> +- marvell,pull-down : The property means a pin is pull down for input.
>> +- marvell,lowpower-pull-up : The property means a pin is pull up for input in
>> +                         sleep state.
>> +- marvell,lowpower-pull-down : The property means a pin is pull down for input
>> +                           in sleep state.
>> +- marvell,lowpower-drive-high : The property means a pin is driving high for
>> +                            output in sleep state.
>> +- marvell,lowpower-drive-low : The property means a pin is driving low for
>> +                           output in sleep state.
>> +- marvell,lowpower-float : The property means a pin is float in sleep state.
>> +- marvell,lowpower-zero : The property means a pin is not configured in sleep
>> +                       state.
>
> These (or most of them) look like they are not very Marvell specific. Should
> we try to standardize the way they are set across different bindings?

If the device tree properties are to be standardized, the driver should be
moved over to using generic pin config (drivers/pinctrl/pinconf-generic.c,
include/linux/pinctrl/pinconf-generic.h) too, or it makes no sense.

So please augment the PXA driver to use these, then move the generic
bindings to pinconf-generic.txt or something.

If pinconf-generic needs extending/augmenting in the process, just do it,
it's supposed to be generic...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug  7 02:56:10 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 08:56:10 +0200
Subject: [PATCH 3/4] gpio/mxs: specify gpio base for device tree probe
In-Reply-To: <20120806135110.GA24289@S2101-09.ap.freescale.net>
References: <1344146488-9496-1-git-send-email-shawn.guo@linaro.org>
 <1344146488-9496-3-git-send-email-shawn.guo@linaro.org>
 <CACRpkdZz+F8gUGJG+d2mGrt8Rp0NzYypGdLEUbxmh=X1Q1cFhw@mail.gmail.com>
 <20120806135110.GA24289@S2101-09.ap.freescale.net>
Message-ID: <CACRpkdZ3HkkcjYLd_pcsmjDwjt26HfU0X9QV87Bmkx5tAQtXZQ@mail.gmail.com>

On Mon, Aug 6, 2012 at 3:51 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Sun, Aug 05, 2012 at 11:48:24AM +0200, Linus Walleij wrote:
>> On Sun, Aug 5, 2012 at 8:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>>
>> > Currently, unlike the non-DT probe where the gpio base is specified
>> > with pdev->id, the DT probe uses the base dynamically allocated by
>> > gpio core, which uses a completely different numbering scheme.  This
>> > causes two issues to user space applications which access sysfs entry
>> > /sys/class/gpio/gpioN.
>>
>> Applied.
>>
> Sorry, Linus.  I just recall gpio-mxs driver already reads alias to
> assign port->id for DT boot at the beginning of probe function, and
> this patch is completely a noise therefore.  So can you please drop
> the patch from you branch?  Sorry again.

OK dropped this patch...

Yours,
Linus Walleij


From sachin.kamat at linaro.org  Tue Aug  7 02:56:57 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Tue, 7 Aug 2012 12:26:57 +0530
Subject: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor
In-Reply-To: <1344261462-14183-2-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344261462-14183-2-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAK9yfHz_q22JgkULR9V8bR5W_TXVRn5qs5u2MiJJpa-Br_YQUQ@mail.gmail.com>

Hi Dongjin,

A patch series to add HDMI platform data support is already under consideration.

http://comments.gmane.org/gmane.linux.kernel.samsung-soc/11352



On 6 August 2012 19:27, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch assign the I2C channel for HDMIPHY for Exynos4x12
> in s5p_i2c_hdmiphy_set_platdata() and s5p_hdmi_set_platdata()
>
> Change-Id: I7e66c8f9327e2f7dce7440efb8583b506d65831a
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/plat-samsung/devs.c |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index a199e55..54614d0 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -752,6 +752,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
>
>                 if (soc_is_exynos4210())
>                         pd->bus_num = 8;
> +               else if (soc_is_exynos4212() || soc_is_exynos4412())
> +                       pd->bus_num = 8;
>                 else if (soc_is_s5pv210())
>                         pd->bus_num = 3;
>                 else
> @@ -771,6 +773,8 @@ void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
>
>         if (soc_is_exynos4210())
>                 pd->hdmiphy_bus = 8;
> +       else if (soc_is_exynos4212() || soc_is_exynos4412())
> +               pd->hdmiphy_bus = 8;
>         else if (soc_is_s5pv210())
>                 pd->hdmiphy_bus = 3;
>         else
> --
> 1.7.9.5
>
> --
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> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



-- 
With warm regards,
Sachin


From tony at atomide.com  Tue Aug  7 03:04:19 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:04:19 -0700
Subject: [PATCH 1/1] ARM: OMAP3: igep0020: set GPIO mode for mux
 mcspi1_cs2 pin
In-Reply-To: <CABxcv=kueP=UA6sQwS8Hs-s3vyAX+RhJgkHmyWWAVb668y-EOQ@mail.gmail.com>
References: <1341885452-5372-1-git-send-email-javier@dowhile0.org>
 <CAFqH_511c6CyAYnbtU0ECZwzRNwJEdTqtcZ63nODCYZU4GC0aA@mail.gmail.com>
 <CABxcv=miEavW5Qf-Y+S4Nph+ah5gQ6QDpt-T44tdHLBxcP8pqQ@mail.gmail.com>
 <20120718072052.GK6522@atomide.com>
 <CABxcv=kueP=UA6sQwS8Hs-s3vyAX+RhJgkHmyWWAVb668y-EOQ@mail.gmail.com>
Message-ID: <20120807070418.GJ11011@atomide.com>

* Javier Martinez Canillas <javier at dowhile0.org> [120803 01:06]:
> 
> I saw that Linus 3.6-rc1 has already been released and I didn't see
> this patch on it.

Yes I wanted to wait for -rc1 to avoid complicating things during
the merge window.
 
> So, this is a kindly reminder so you don't miss this patch :-)

Applying into fixes, thanks for the patience.

Tony


From tony at atomide.com  Tue Aug  7 03:13:51 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:13:51 -0700
Subject: [GIT PULL 1/5] omap device tree changes for v3.6 merge window
In-Reply-To: <20120713075658.GQ1122@atomide.com>
References: <pull-1341925556-888624>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A8BE1@DBDE01.ent.ti.com>
 <20120713064147.GG1122@atomide.com>
 <20120713075658.GQ1122@atomide.com>
Message-ID: <20120807071351.GK11011@atomide.com>

* Tony Lindgren <tony at atomide.com> [120713 01:01]:
> * Tony Lindgren <tony at atomide.com> [120712 23:46]:
> > * Mohammed, Afzal <afzal at ti.com> [120712 23:19]:
> > > > Afzal Mohammed (1):
> > > >       arm/dts: am33xx wdt node
> > > 
> > > The above patch seems to be an empty one, actual changes in it as in
> > > original patch [1] is missing, same changes are shown below for your
> > > reference [2].
> > > 
> > > Can you please do the needful so that the intended change of this
> > > patch makes to mainline this merge window.
> > 
> > Argh. Thanks for letting me know. I must have something wrong with
> > my scripts when applying patches. We'll have to apply this as a fix.
> 
> Arnd and Olof, let me know if you want me to resubmit a new branch instead
> of the already pulled devel-dt branch. That branch should not have other
> dependencies as it's based on -rc5. Of course is it's buried into other
> DT patches it's too late.

Now with -rc1 out, I'll queue the following fix.

Regards,

Tony

From: Afzal Mohammed <afzal at ti.com>
Date: Wed, 4 Jul 2012 18:00:37 +0530
Subject: [PATCH] arm/dts: Fix am33xx wdt node

Add am33xx wdt node.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
[tony at atomide.com: I messed up and produced an empty commit db27ac80 with stg apply]
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c4..bd0cff3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -154,5 +154,10 @@
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
 		};
+
+		wdt2: wdt at 44e35000 {
+			compatible = "ti,omap3-wdt";
+			ti,hwmods = "wd_timer2";
+		};
 	};
 };


From s.hauer at pengutronix.de  Tue Aug  7 03:17:52 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 7 Aug 2012 09:17:52 +0200
Subject: [GIT PULL] i.MX fixes for 3.6-rc
Message-ID: <20120807071752.GG1451@pengutronix.de>

Hi Arnd, Olof,

Please pull the following i.MX fixes for 3.6-rc

Sascha

The following changes since commit 1a9b4993b70fb1884716902774dc9025b457760d:

  Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus (2012-08-01 16:47:15 -0700)

are available in the git repository at:


  git://git.pengutronix.de/git/imx/linux-2.6.git tags/imx-fixes

for you to fetch changes up to 9de76b6df70003b657d907571b17ac3c17cd9082:

  i.MX27: Fix emma-prp and csi clocks. (2012-08-07 09:14:30 +0200)

----------------------------------------------------------------
ARM i.MX fixes for 3.6-rc

----------------------------------------------------------------
Fabio Estevam (2):
      ARM: dts: imx27-3ds.dts: Fix serial console node
      ARM: clk-imx31: Fix the keypad clock name

Javier Martin (1):
      i.MX27: Fix emma-prp and csi clocks.

 arch/arm/boot/dts/imx27-3ds.dts |    2 +-
 arch/arm/mach-imx/clk-imx27.c   |    8 +++++---
 arch/arm/mach-imx/clk-imx31.c   |    2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From balajitk at ti.com  Tue Aug  7 03:18:21 2012
From: balajitk at ti.com (Balaji T K)
Date: Tue, 7 Aug 2012 12:48:21 +0530
Subject: [PATCH] arm/dts: omap5: Add mmc controller nodes and board data
Message-ID: <1344323901-20342-1-git-send-email-balajitk@ti.com>

Add OMAP MMC related device tree data for OMAP5.

Signed-off-by: Balaji T K <balajitk at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   31 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |   31 +++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39a..7bb0c9d 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,35 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	vmmcsd_fixed: fixedregulator-mmcsd {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcsd_fixed";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+	};
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <4>;
+};
+
+&mmc2 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <8>;
+	ti,non-removable;
+};
+
+&mmc3 {
+	bus-width = <4>;
+	ti,non-removable;
+};
+
+&mmc4 {
+	status = "disabled";
+};
+
+&mmc5 {
+	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..881d60c 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -180,5 +180,36 @@
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
+
+		mmc1: mmc at 4809c000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc1";
+			ti,dual-volt;
+			ti,needs-special-reset;
+		};
+
+		mmc2: mmc at 480b4000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc2";
+			ti,needs-special-reset;
+		};
+
+		mmc3: mmc at 480ad000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc3";
+			ti,needs-special-reset;
+		};
+
+		mmc4: mmc at 480d1000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc4";
+			ti,needs-special-reset;
+		};
+
+		mmc5: mmc at 480d5000 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc5";
+			ti,needs-special-reset;
+		};
 	};
 };
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Aug  7 03:18:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 Aug 2012 15:18:56 +0800
Subject: [PATCH 1/6] ARM: mxs: tx28: reset fec phy for device tree boot
In-Reply-To: <CAP9ODKqLzfSRFMjg6yrmzTviNv4R3EyD0Sa2TMnWvKL0Djyj=Q@mail.gmail.com>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
 <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
 <CAP9ODKqLzfSRFMjg6yrmzTviNv4R3EyD0Sa2TMnWvKL0Djyj=Q@mail.gmail.com>
Message-ID: <20120807071853.GA13964@S2101-09.ap.freescale.net>

On Mon, Aug 06, 2012 at 01:51:07PM -0300, Otavio Salvador wrote:
> On Mon, Aug 6, 2012 at 12:42 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > For non-DT boot, function tx28_add_fec0 configures all ENET0 pins
> > into gpio mode for resetting fec phy, and then reconfigures those pins
> > into ENET function after that.
> >
> > For DT boot, all the pin configuration is done by pinctrl subsystem.
> > Ideally, when gpio_requst gets called, GPIO subsystem should call
> 
>                         ^ typo
> 
Fixed.  Thanks, Otavio.

-- 
Regards,
Shawn



From p.paneri at samsung.com  Tue Aug  7 03:28:44 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:44 +0530
Subject: [PATCH v2 5/5] ARM: Exynos4210: Enabling samsung_usbphy driver
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344324524-2286-6-git-send-email-p.paneri@samsung.com>

Adding usbphy node for Exynos4210 along with the platform data.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi       |    5 +++++
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c  |    8 ++++++++
 arch/arm/mach-exynos/setup-usb-phy.c    |   13 +++++++++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..e28cf10 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -62,6 +62,11 @@
 		interrupts = <0 44 0>, <0 45 0>;
 	};
 
+	usbphy at 125B0000 {
+		compatible = "samsung,exynos4210-usbphy";
+		reg = <0x125B0000 0x100>;
+	};
+
 	keypad at 100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..0625c0a 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -234,6 +234,7 @@
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG		EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY			EXYNOS4_PA_HSPHY
 
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..0f74438 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -20,9 +21,14 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct s3c_usbphy_plat exynos4_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -63,6 +69,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 				"exynos4210-spi.2", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+			"s3c-usbphy", &exynos4_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..1c62d20 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -221,3 +221,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 	return -EINVAL;
 }
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			& ~S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	} else {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			| S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	}
+}
-- 
1.7.1



From p.paneri at samsung.com  Tue Aug  7 03:28:39 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:39 +0530
Subject: [PATCH v2 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
Message-ID: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>

Changes from v1:
Rebased patches to latest usb-next branch
Changed the name 'sec_usbphy' to 'samsung_usbphy'

This patch set introduces a phy driver for samsung SoCs. It uses the existing
transceiver infrastructure to provide phy control functions. Use of this driver
can be extended for usb host phy as well. Over the period of time all the phy
related code for most of the samsung SoCs can be integrated here.
Removing the existing phy code from mach-s3c64xx but not from other machine 
code.This driver is tested with smdk6410 and Exynos4210(with DT).

Praveen Paneri (5):
  usb: phy: samsung: Introducing usb phy driver for hsotg
  usb: s3c-hsotg: Adding phy driver support
  ARM: S3C64XX: Removing old phy setup code
  ARM: S3C64XX: Enabling samsung_usbphy driver
  ARM: Exynos4210: Enabling samsung_usbphy driver

 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
 arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    5 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |    6 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    5 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
 arch/arm/plat-samsung/devs.c                       |   32 ++
 arch/arm/plat-samsung/include/plat/devs.h          |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 drivers/usb/gadget/s3c-hsotg.c                     |   38 ++-
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung_usbphy.c                   |  355 ++++++++++++++++++++
 drivers/usb/phy/samsung_usbphy.h                   |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 19 files changed, 534 insertions(+), 88 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung_usbphy.c
 create mode 100644 drivers/usb/phy/samsung_usbphy.h



From p.paneri at samsung.com  Tue Aug  7 03:28:40 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:40 +0530
Subject: [PATCH v2 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344324524-2286-2-git-send-email-p.paneri@samsung.com>

This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable phy. Tested with
smdk6410 and smdkv310. More SoCs can be brought under later.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung_usbphy.c                   |  355 ++++++++++++++++++++
 drivers/usb/phy/samsung_usbphy.h                   |   48 +++
 include/linux/platform_data/s3c-hsotg.h            |    5 +
 6 files changed, 426 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung_usbphy.c
 create mode 100644 drivers/usb/phy/samsung_usbphy.h

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 0000000..fefd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,9 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..d916477 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -15,3 +15,11 @@ config USB_ISP1301
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1301.
+
+config SAMSUNG_USBPHY
+       bool "Samsung USB PHY controller Driver"
+       depends on USB_S3C_HSOTG
+       select USB_OTG_UTILS
+       help
+         Enable this to support Samsung USB phy controller for samsung
+         SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..c5a483d 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_SAMSUNG_USBPHY)		+= samsung_usbphy.o
diff --git a/drivers/usb/phy/samsung_usbphy.c b/drivers/usb/phy/samsung_usbphy.c
new file mode 100644
index 0000000..8e9e772
--- /dev/null
+++ b/drivers/usb/phy/samsung_usbphy.c
@@ -0,0 +1,355 @@
+/* linux/drivers/usb/phy/samsung_usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/s3c-hsotg.h>
+
+#include "samsung_usbphy.h"
+
+enum samsung_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_EXYNOS4210,
+};
+
+/*
+ * struct samsung_usbphy - transceiver driver state
+ * @phy: transceiver structure
+ * @plat: platform data
+ * @dev: The parent device supplied to the probe function
+ * @clk: usb phy clock
+ * @regs: usb phy register memory base
+ * @cpu_type: machine identifier
+ */
+struct samsung_usbphy {
+	struct usb_phy	phy;
+	struct s3c_usbphy_plat *plat;
+	struct device	*dev;
+	struct clk	*clk;
+	void __iomem	*regs;
+	int		cpu_type;
+};
+
+#define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
+
+/*
+ * Enables or disables the phy clock
+ * returns 0 on success else the error
+ */
+static int samsung_usbphy_clk_control(struct samsung_usbphy *sphy, bool on)
+{
+	if (on) {
+		if (!sphy->clk) {
+			sphy->clk = clk_get(sphy->dev, "otg");
+			if (IS_ERR(sphy->clk)) {
+				dev_err(sphy->dev, "Failed to get otg clock\n");
+				return PTR_ERR(sphy->clk);
+			}
+		}
+		clk_enable(sphy->clk);
+	} else {
+		clk_disable(sphy->clk);
+		clk_put(sphy->clk);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns reference clock frequency
+ */
+static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
+{
+	struct clk *ref_clk;
+	int refclk_freq = 0;
+
+	ref_clk = clk_get(sphy->dev, "xusbxti");
+	if (IS_ERR(ref_clk)) {
+		dev_err(sphy->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	switch (clk_get_rate(ref_clk)) {
+	case 12 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+		break;
+	default:
+	case 48 * MHZ:
+		/* default reference clock */
+		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+		break;
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	/* set clock frequency for PLL */
+	phyclk = samsung_usbphy_get_refclk_freq(sphy);
+	phypwr = readl(regs + S3C_PHYPWR);
+	rstcon = readl(regs + S3C_RSTCON);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
+		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+	default:
+		break;
+	}
+
+	writel(phyclk, regs + S3C_PHYCLK);
+	/* set to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+	/* reset all ports of PHY and Link */
+	writel(rstcon, regs + S3C_RSTCON);
+	udelay(10);
+	rstcon &= ~S3C_RSTCON_PHY;
+	writel(rstcon, regs + S3C_RSTCON);
+}
+
+static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+
+	phypwr = readl(regs + S3C_PHYPWR);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phypwr |= S3C_PHYPWR_NORMAL_MASK;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
+	default:
+		break;
+	}
+
+	/* unset to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int samsung_usbphy_init(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+	int ret = 0;
+
+	sphy = phy_to_sphy(phy);
+
+	/* Enable the phy clock */
+	ret = samsung_usbphy_clk_control(sphy, true);
+	if (ret) {
+		dev_err(sphy->dev, "phy clock enable failed\n");
+		return ret;
+	}
+
+	/* Disable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(false);
+
+	/* Initialize usb phy registers */
+	samsung_usbphy_enable(sphy);
+	return ret;
+}
+
+/*
+ * The function passed to the usb driver for phy shutdown
+ */
+static void samsung_usbphy_shutdown(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+
+	sphy = phy_to_sphy(phy);
+
+	/* De-initialize usb phy registers */
+	samsung_usbphy_disable(sphy);
+
+	/* Enable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(true);
+
+	/* Disable the phy clock */
+	samsung_usbphy_clk_control(sphy, false);
+}
+
+static const struct of_device_id samsung_usbphy_dt_match[];
+
+static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	int data;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(samsung_usbphy_dt_match,
+							pdev->dev.of_node);
+		data = (int) match->data;
+		return data;
+	}
+#endif
+	return platform_get_device_id(pdev)->driver_data;
+}
+
+static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy;
+	struct s3c_usbphy_plat *pdata;
+	struct device *dev = &pdev->dev;
+	struct resource *phy_mem;
+	void __iomem	*phy_base;
+	int	ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
+		return -EINVAL;
+	}
+
+	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!phy_mem) {
+		dev_err(dev, "%s: missing mem resource\n", __func__);
+		return -ENODEV;
+	}
+
+	phy_base = devm_request_and_ioremap(dev, phy_mem);
+	if (!phy_base) {
+		dev_err(dev, "%s: register mapping failed\n", __func__);
+		return -ENXIO;
+	}
+
+	sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
+	if (!sphy)
+		return -ENOMEM;
+
+	sphy->dev		= &pdev->dev;
+	sphy->plat		= pdata;
+	sphy->regs		= phy_base;
+	sphy->phy.dev		= sphy->dev;
+	sphy->phy.label		= "samsung-usbphy";
+	sphy->phy.init		= samsung_usbphy_init;
+	sphy->phy.shutdown	= samsung_usbphy_shutdown;
+	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
+
+	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, sphy);
+
+	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
+err:
+	return ret;
+}
+
+static int __exit samsung_usbphy_remove(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&sphy->phy);
+
+	if (sphy->clk) {
+		clk_put(sphy->clk);
+		sphy->clk = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id samsung_usbphy_dt_match[] = {
+	{
+		.compatible = "samsung,s3c64xx-usbphy",
+		.data = (void *)TYPE_S3C64XX,
+	}, {
+		.compatible = "samsung,exynos4210-usbphy",
+		.data = (void *)TYPE_EXYNOS4210,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
+#else
+#define samsung_usbphy_dt_match NULL
+#endif
+
+static struct platform_device_id samsung_usbphy_driver_ids[] = {
+	{
+		.name		= "s3c64xx-usbphy",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "exynos4210-usbphy",
+		.driver_data	= TYPE_EXYNOS4210,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
+
+static struct platform_driver samsung_usbphy_driver = {
+	.probe		= samsung_usbphy_probe,
+	.remove		= __devexit_p(samsung_usbphy_remove),
+	.id_table	= samsung_usbphy_driver_ids,
+	.driver		= {
+		.name	= "samsung-usbphy",
+		.owner	= THIS_MODULE,
+		.of_match_table = samsung_usbphy_dt_match,
+	},
+};
+
+static int __init samsung_usbphy_driver_init(void)
+{
+	return platform_driver_register(&samsung_usbphy_driver);
+}
+subsys_initcall(samsung_usbphy_driver_init);
+
+static void __exit samsung_usbphy_driver_exit(void)
+{
+	return platform_driver_unregister(&samsung_usbphy_driver);
+}
+module_exit(samsung_usbphy_driver_exit);
+
+MODULE_DESCRIPTION("Samsung USB phy controller");
+MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-usbphy");
diff --git a/drivers/usb/phy/samsung_usbphy.h b/drivers/usb/phy/samsung_usbphy.h
new file mode 100644
index 0000000..093b1dc
--- /dev/null
+++ b/drivers/usb/phy/samsung_usbphy.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SAMSUNG_USBPHY_H
+#define __SAMSUNG_USBPHY_H
+
+#define S3C_PHYPWR				(0x00)
+
+#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
+#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
+#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
+
+#define S3C_PHYCLK				(0x04)
+
+#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
+#define S3C_PHYCLK_EXT_OSC			(1 << 5)
+#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
+#define S3C_PHYCLK_ID_PULL			(1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
+#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
+
+#define S3C_RSTCON				(0x08)
+
+#define S3C_RSTCON_PHYCLK			(1 << 2)
+#define S3C_RSTCON_HCLK				(1 << 1)
+#define S3C_RSTCON_PHY				(1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#endif /* __SAMSUNG_USBPHY_H */
diff --git a/include/linux/platform_data/s3c-hsotg.h b/include/linux/platform_data/s3c-hsotg.h
index 8b79e09..25ed31e 100644
--- a/include/linux/platform_data/s3c-hsotg.h
+++ b/include/linux/platform_data/s3c-hsotg.h
@@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
 	int (*phy_exit)(struct platform_device *pdev, int type);
 };
 
+struct s3c_usbphy_plat {
+	void (*pmu_isolation)(int on);
+};
+
 extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
+extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
 
 #endif /* __LINUX_USB_S3C_HSOTG_H */
-- 
1.7.1



From p.paneri at samsung.com  Tue Aug  7 03:28:41 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:41 +0530
Subject: [PATCH v2 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344324524-2286-3-git-send-email-p.paneri@samsung.com>

Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 drivers/usb/gadget/s3c-hsotg.c |   38 ++++++++++++++++++++++++++++----------
 1 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b13e0bb..f4ba9a3 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <mach/map.h>
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
  * struct s3c_hsotg - driver state.
  * @dev: The parent device supplied to the probe function
  * @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transeiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
  * @regs: The memory area mapped for accessing registers.
  * @irq: The IRQ number we are using
  * @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
+	struct usb_phy		*phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
-	if (hsotg->plat->phy_init)
+
+	if (hsotg->phy)
+		usb_phy_init(hsotg->phy);
+	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
 
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 {
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
-	if (hsotg->plat->phy_exit)
+	if (hsotg->phy)
+		usb_phy_shutdown(hsotg->phy);
+	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
 
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+	struct usb_phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,25 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 	int ret;
 	int i;
 
-	plat = pdev->dev.platform_data;
-	if (!plat) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
-
 	hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
 	if (!hsotg) {
 		dev_err(dev, "cannot get memory\n");
 		return -ENOMEM;
 	}
 
+	phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+	if (!phy) {
+		/* Fallback for platform data */
+		plat = pdev->dev.platform_data;
+		if (!plat) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -ENODEV;
+		} else
+			hsotg->plat = plat;
+	} else
+		hsotg->phy = phy;
+
 	hsotg->dev = dev;
-	hsotg->plat = plat;
 
 	hsotg->clk = clk_get(&pdev->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
@@ -3689,6 +3704,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
 	s3c_hsotg_phy_disable(hsotg);
 	regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
 
+	if (hsotg->phy)
+		devm_usb_put_phy(&pdev->dev, hsotg->phy);
+
 	clk_disable_unprepare(hsotg->clk);
 	clk_put(hsotg->clk);
 
-- 
1.7.1



From p.paneri at samsung.com  Tue Aug  7 03:28:42 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:42 +0530
Subject: [PATCH v2 3/5] ARM: S3C64XX: Removing old phy setup code
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344324524-2286-4-git-send-email-p.paneri@samsung.com>

This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |    2 -
 arch/arm/mach-s3c64xx/mach-smartq.c   |    2 -
 arch/arm/mach-s3c64xx/mach-smdk6410.c |    2 -
 arch/arm/mach-s3c64xx/setup-usb-phy.c |   79 ---------------------------------
 4 files changed, 0 insertions(+), 85 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..3bb0327 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -766,7 +766,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -792,7 +791,6 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de..3647202 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,7 +187,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
 	},
 };
 
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
 
 static int __init smartq_lcd_setup_gpio(void)
 {
@@ -385,7 +384,6 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
-	s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..1a2db14 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -627,7 +627,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -657,7 +656,6 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
  *
  */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <mach/regs-sys.h>
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
-	struct clk *xusbxti;
-	u32 phyclk;
-
-	writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	/* set clock frequency for PLL */
-	phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-	xusbxti = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti && !IS_ERR(xusbxti)) {
-		switch (clk_get_rate(xusbxti)) {
-		case 12 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
-		}
-		clk_put(xusbxti);
-	}
-
-	/* TODO: select external clock/oscillator */
-	writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-	/* set to normal OTG PHY */
-	writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-	mdelay(1);
-
-	/* reset OTG PHY and Link */
-	writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-			S3C_RSTCON);
-	udelay(20);	/* at-least 10uS */
-	writel(0, S3C_RSTCON);
-
-	return 0;
-}
-
-static int s3c_usb_otgphy_exit(struct platform_device *pdev)
-{
-	writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-				S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-	writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_init(pdev);
-
-	return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_exit(pdev);
-
-	return -EINVAL;
-}
-- 
1.7.1



From p.paneri at samsung.com  Tue Aug  7 03:28:43 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 07 Aug 2012 12:58:43 +0530
Subject: [PATCH v2 4/5] ARM: S3C64XX: Enabling samsung_usbphy driver
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344324524-2286-5-git-send-email-p.paneri@samsung.com>

Adding platform device for samsung_usbphy driver. Enabling it for
s3c64xx based machines using s3c-hsotg.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c        |    3 ++
 arch/arm/mach-s3c64xx/mach-smartq.c          |    4 +++
 arch/arm/mach-s3c64xx/mach-smdk6410.c        |    3 ++
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
 arch/arm/plat-samsung/devs.c                 |   32 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h    |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
 8 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
 
 #define S3C64XX_PA_NAND		(0x70200000)
 #define S3C64XX_PA_FB		(0x77100000)
+#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
@@ -113,6 +114,7 @@
 #define S3C_PA_FB		S3C64XX_PA_FB
 #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
 #define S3C_PA_RTC		S3C64XX_PA_RTC
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 #define S3C_PA_SPI0		S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 3bb0327..05e6e14 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -337,6 +337,7 @@ static struct platform_device wallvdd_device = {
 };
 
 static struct platform_device *crag6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc2,
 	&s3c_device_i2c0,
@@ -766,6 +767,7 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
+static struct s3c_usbphy_plat crag6410_usbphy_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -791,6 +793,7 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&crag6410_usbphy_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 3647202..97751d5 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -235,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata = {
 };
 
 static struct platform_device *smartq_devices[] __initdata = {
+	&s3c_device_usbphy,
 	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
 	&s3c_device_hsmmc0,	/* ... then the external SD card */
 	&s3c_device_hsmmc2,
@@ -381,9 +382,12 @@ void __init smartq_map_io(void)
 	smartq_lcd_mode_set();
 }
 
+static struct s3c_usbphy_plat smartq_usbphy_pdata;
+
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
+	s3c_usbphy_set_platdata(&smartq_usbphy_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 1a2db14..e5c55ba 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -264,6 +264,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
+	&s3c_device_usbphy,
 #ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
 #endif
@@ -627,6 +628,7 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
+static struct s3c_usbphy_plat smdk6410_usbphy_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -656,6 +658,7 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	s3c_usbphy_set_platdata(&smdk6410_usbphy_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 7a09553..3aee778 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,3 +9,17 @@
  *
  */
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	} else {
+		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	}
+}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..10bc2bf 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1343,6 +1343,35 @@ struct platform_device s5p_device_mixer = {
 
 /* USB */
 
+#ifdef CONFIG_S3C_DEV_USB_HSOTG
+/* USB PHY*/
+static struct resource s3c_usbphy_resource[] = {
+	[0] = {
+		.start = S3C_PA_USB_PHY,
+		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device s3c_device_usbphy = {
+	.name		= "s3c64xx-usbphy",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(s3c_usbphy_resource),
+	.resource	= s3c_usbphy_resource,
+};
+
+void __init s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd)
+{
+	struct s3c_usbphy_plat *npd;
+
+	npd = s3c_set_platdata(pd, sizeof(struct s3c_usbphy_plat),
+			&s3c_device_usbphy);
+
+	if (!npd->pmu_isolation)
+		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
+}
+#endif
+
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
 	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
@@ -1449,6 +1478,8 @@ struct platform_device s3c_device_usb_hsotg = {
 	},
 };
 
+#ifndef CONFIG_ARCH_S3C64XX
+/* TODO: To be removed later. Currently only S3C64XX is platform data free */
 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 {
 	struct s3c_hsotg_plat *npd;
@@ -1461,6 +1492,7 @@ void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 	if (!npd->phy_exit)
 		npd->phy_exit = s5p_usb_phy_exit;
 }
+#endif
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5da4b4f..abc6942 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -71,6 +71,7 @@ extern struct platform_device s3c_device_spi1;
 extern struct platform_device s3c_device_ts;
 extern struct platform_device s3c_device_timer[];
 extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usbphy;
 extern struct platform_device s3c_device_usb_hsotg;
 extern struct platform_device s3c_device_usb_hsudc;
 extern struct platform_device s3c_device_wdt;
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..165ffe7 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern void s5p_usb_phy_pmu_isolation(int on);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
-- 
1.7.1



From tony at atomide.com  Tue Aug  7 03:20:42 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:20:42 -0700
Subject: [PATCH v2] ARM: OMAP4: twl-common: Support for additional
 devices on i2c1 bus
In-Reply-To: <500D0FA5.3020208@ti.com>
References: <1342168682-15888-1-git-send-email-peter.ujfalusi@ti.com>
 <500D0FA5.3020208@ti.com>
Message-ID: <20120807072041.GL11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120723 01:52]:
> Hi Tony,
> 
> On 07/13/2012 10:38 AM, Peter Ujfalusi wrote:
> > On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices.
> > Manufacturers can opt to use different codec than twl6040 and also can add
> > audio related IC to the bus (external amplifier for example on SDP4430).
> > 
> > Make it possible to add differnet set of additional devices to i2c1 bus on
> > OMAP4 boards.
> 
> Would it be possible to queue this patch for 3.6?

Sorry things were getting already too complex for v3.6 merge window..
So v3.7 it will be. Looks like this need to be updated against v3.6-rc1
to apply.

Regards,

Tony


From s.hauer at pengutronix.de  Tue Aug  7 03:21:51 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 7 Aug 2012 09:21:51 +0200
Subject: Vacations.
In-Reply-To: <Pine.LNX.4.64.1208031708200.5170@axis700.grange>
References: <CACKLOr1Q6_xVhaaoWiy-kf9hViTW98aSa6hd5M2z7ogL-uwNVQ@mail.gmail.com>
 <Pine.LNX.4.64.1208031708200.5170@axis700.grange>
Message-ID: <20120807072151.GF24458@pengutronix.de>

On Fri, Aug 03, 2012 at 05:09:15PM +0200, Guennadi Liakhovetski wrote:
> Hi Javier
> 
> On Fri, 3 Aug 2012, javier Martin wrote:
> 
> > Hi,
> > I will be out of the office until August the 19th.
> > 
> > I just wanted to send a reminder of some patches that I have pending.
> > 
> > For Mauro 3.7:
> > 
> > [PULL] video_visstrim for 3.6
> > [PATCH] media: i.MX27: Fix mx2_emmaprp mem2mem driver clocks.
> > 
> > For Guennadi:
> > 
> > [PATCH 1/4] i.MX27: Fix emma-prp and csi clocks.
> 
> As I mentioned several times, the above patch is not for me. Have a nice 
> vacation.

Indeed it's for me. Queued this up.

Thanks
 Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Tue Aug  7 03:23:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:23:01 -0700
Subject: [PATCH] OMAP2+: Fix random config build break with
 !ARM_CPU_SUSPEND
In-Reply-To: <1342176307-6435-1-git-send-email-santosh.shilimkar@ti.com>
References: <1342176307-6435-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <20120807072300.GM11011@atomide.com>

* Santosh Shilimkar <santosh.shilimkar at ti.com> [120713 03:50]:
> The random config builds with PM and !ARM_CPU_SUSPEND breaks with below
> error on omap2plus_defconfig.
> 
> arch/arm/mach-omap2/sleep44xx.S:323: undefined reference to `cpu_resume'
> arch/arm/mach-omap2/omap-mpuss-lowpower.c:278: undefined reference to `cpu_suspend'
> 
> This is because recently merged OMAP5 platform shares the common files
> with OMAP4 but doesn't select ARM_CPU_SUSPEND. Without the ARM_CPU_SUSPEND
> the sleep code is meaningless.
> 
> Fix the same by adding ARM_CPU_SUSPEND for OMAP5. The suggestion came from
> Russell King in an off-list discussion.

Thanks applying into fixes.

Tony


From Dongjin.Kim at agreeyamobility.net  Tue Aug  7 03:28:02 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Tue, 7 Aug 2012 07:28:02 +0000
Subject: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor
In-Reply-To: <CAK9yfHz_q22JgkULR9V8bR5W_TXVRn5qs5u2MiJJpa-Br_YQUQ@mail.gmail.com>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344261462-14183-2-git-send-email-dongjin.kim@agreeyamobility.net>,
 <CAK9yfHz_q22JgkULR9V8bR5W_TXVRn5qs5u2MiJJpa-Br_YQUQ@mail.gmail.com>
Message-ID: <b937n0skj9tqmbg6tctdu48x.1344324481459@email.android.com>

Hi Sachin,

Thanks for your feedback, I couldnt find the patch series eariler. ;)

Regards,
Dongjin.

Sent from Moxier Mail
(http://www.moxier.com)


----- ?? ??? -----
?? ??:Sachin Kamat <sachin.kamat at linaro.org>
?? ??:Dongjin Kim <tobetter at gmail.com>
??:Dongjin Kim <Dongjin.Kim at agreeyamobility.net>, Ben Dooks <ben-linux at fluff.org>, Kukjin Kim <kgene.kim at samsung.com>, Russell King <linux at arm.linux.org.uk>, "linux-arm-kernel at lists.infradead.org" <linux-arm-kernel at lists.infradead.org>, "linux-samsung-soc at vger.kernel.org" <linux-samsung-soc at vger.kernel.org>, "linux-kernel at vger.kernel.org" <linux-kernel at vger.kernel.org>
?? ??:2012. 8. 7. 3:57 ??
??:Re: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor



Hi Dongjin,

A patch series to add HDMI platform data support is already under consideration.

http://comments.gmane.org/gmane.linux.kernel.samsung-soc/11352



On 6 August 2012 19:27, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch assign the I2C channel for HDMIPHY for Exynos4x12
> in s5p_i2c_hdmiphy_set_platdata() and s5p_hdmi_set_platdata()
>
> Change-Id: I7e66c8f9327e2f7dce7440efb8583b506d65831a
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/plat-samsung/devs.c |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index a199e55..54614d0 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -752,6 +752,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
>
>                 if (soc_is_exynos4210())
>                         pd->bus_num = 8;
> +               else if (soc_is_exynos4212() || soc_is_exynos4412())
> +                       pd->bus_num = 8;
>                 else if (soc_is_s5pv210())
>                         pd->bus_num = 3;
>                 else
> @@ -771,6 +773,8 @@ void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
>
>         if (soc_is_exynos4210())
>                 pd->hdmiphy_bus = 8;
> +       else if (soc_is_exynos4212() || soc_is_exynos4412())
> +               pd->hdmiphy_bus = 8;
>         else if (soc_is_s5pv210())
>                 pd->hdmiphy_bus = 3;
>         else
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



--
With warm regards,
Sachin


From tony at atomide.com  Tue Aug  7 03:28:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:28:52 -0700
Subject: [RFC 1/6] ARM: OMAP3: PRM: move prcm interrupt handlers to PRM
 driver code
In-Reply-To: <87ipd4g4a5.fsf@ti.com>
References: <1342197459-7920-1-git-send-email-t-kristo@ti.com>
 <1342197459-7920-2-git-send-email-t-kristo@ti.com>
 <87ipd4g4a5.fsf@ti.com>
Message-ID: <20120807072852.GN11011@atomide.com>

* Kevin Hilman <khilman at ti.com> [120730 17:36]:
> 
> At first, I wasn't sure why this was happening on Overo boards and not
> on the other boards, but then I notcied there was a *lot* more pm_wkup
> interrupts during boot on Overo compared to the other boards.  This is
> because of the GPIO IRQ for the network interface as well as the network
> stack itself setting timers, resulting in a lot more pm_wkup events
> during boot and making the race more likely.

Also happens if you may have somehow both edges selected for GPIO
interrupts. Might be worth checking at least just in case of bugs
somewhere..

Tony


From afzal at ti.com  Tue Aug  7 03:29:06 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 7 Aug 2012 07:29:06 +0000
Subject: [GIT PULL 1/5] omap device tree changes for v3.6 merge window
In-Reply-To: <20120807071351.GK11011@atomide.com>
References: <pull-1341925556-888624>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A8BE1@DBDE01.ent.ti.com>
 <20120713064147.GG1122@atomide.com> <20120713075658.GQ1122@atomide.com>
 <20120807071351.GK11011@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9B1B0C@DBDE01.ent.ti.com>

On Tue, Aug 07, 2012 at 12:43:51, Tony Lindgren wrote:
> * Tony Lindgren <tony at atomide.com> [120713 01:01]:
> > * Tony Lindgren <tony at atomide.com> [120712 23:46]:

> > > my scripts when applying patches. We'll have to apply this as a fix.
> > Arnd and Olof, let me know if you want me to resubmit a new branch instead
> > of the already pulled devel-dt branch. That branch should not have other
> > dependencies as it's based on -rc5. Of course is it's buried into other
> > DT patches it's too late.
> 
> Now with -rc1 out, I'll queue the following fix.

Thanks Tony

Regards
Afzal


From tony at atomide.com  Tue Aug  7 03:34:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:34:27 -0700
Subject: [PATCH] ARM: OMAP2+: Fix dmtimer set source clock failure
In-Reply-To: <1342210323-2129-1-git-send-email-jon-hunter@ti.com>
References: <1342210323-2129-1-git-send-email-jon-hunter@ti.com>
Message-ID: <20120807073427.GO11011@atomide.com>

Hi,

* Jon Hunter <jon-hunter at ti.com> [120713 13:17]:
> Calling the dmtimer function omap_dm_timer_set_source() fails if following a
> call to pm_runtime_put() to disable the timer. For example the following
> sequence would fail to set the parent clock ...
> 
> 	omap_dm_timer_stop(gptimer);
> 	omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
> 
> The following error message would be seen ...
> 
> omap_dm_timer_set_source: failed to set timer_32k_ck as parent
> 
> The problem is that, by design, pm_runtime_put() simply decrements the usage
> count and returns before the timer has actually been disabled. Therefore,
> setting the parent clock failed because the timer was still active when the
> trying to set the parent clock. Setting a parent clock will fail if the clock
> you are setting the parent of has a non-zero usage count. To ensure that this
> does not fail use pm_runtime_put_sync() when disabling the timer.
> 
> Note that this will not be seen on OMAP1 devices, because these devices do
> not use the clock framework for dmtimers.

Kevin care to ack this one? This should also be Cc: stable it seems?

Regards,

Tony
 
> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> ---
>  arch/arm/plat-omap/dmtimer.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 626ad8c..7b6689a 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
>  
>  void omap_dm_timer_disable(struct omap_dm_timer *timer)
>  {
> -	pm_runtime_put(&timer->pdev->dev);
> +	pm_runtime_put_sync(&timer->pdev->dev);
>  }
>  EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
>  
> -- 
> 1.7.9.5
> 


From tony at atomide.com  Tue Aug  7 03:38:03 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:38:03 -0700
Subject: [PATCH] OMAP: remove unused parameter arch_id from uncompress.h
In-Reply-To: <20120714204952.GA4798@raptus.dandreoli.com>
References: <20120714204952.GA4798@raptus.dandreoli.com>
Message-ID: <20120807073803.GP11011@atomide.com>

* Domenico Andreoli <cavokz at gmail.com> [120714 13:54]:
> From: Domenico Andreoli <domenico.andreoli at linux.com>
> 
> There is not point in having arch_id as parameter of __arch_decomp_setup(),
> nothing in it uses arch_id. The machine id is already exported (and used)
> with symbol __machine_arch_type as per mach-types.h.
> 
> Removing the pointless macro as well.

Thanks applying into fixes.

Tony


From tony at atomide.com  Tue Aug  7 03:43:48 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 00:43:48 -0700
Subject: [PATCH RESEND v2 1/2] arm/dts: Add AM33XX basic pinctrl support
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
References: <1343144719-26352-1-git-send-email-anilkumar@ti.com>
 <1343144719-26352-2-git-send-email-anilkumar@ti.com>
 <50125B1C.8000209@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
Message-ID: <20120807074348.GQ11011@atomide.com>

* AnilKumar, Chimata <anilkumar at ti.com> [120731 06:37]:
> Hi Peter,
> 
> On Fri, Jul 27, 2012 at 14:40:52, Ujfalusi, Peter wrote:
> > Hi,
> > 
> > On 07/24/2012 06:45 PM, AnilKumar Ch wrote:
> > > Adds basic pinctrl support for AM33XX family of devices. This patch
> > > is based on the pinctrl-simple driver submitted by Tony Lindgren's
> > > here: http://lwn.net/Articles/496075/
> > > 
> > > Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> > > ---
> > >  arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> > > index 59509c4..9b974dc 100644
> > > --- a/arch/arm/boot/dts/am33xx.dtsi
> > > +++ b/arch/arm/boot/dts/am33xx.dtsi
> > > @@ -40,6 +40,15 @@
> > >  		};
> > >  	};
> > >  
> > > +	am3358_pinmux: pinmux at 44E10800 {
> > > +		compatible = "pinctrl-single";
> > > +		reg = <0x44E10800 0x0338>;
> > 
> > I'm just curious about the size here: how it ended up as 0x0338?
> > While looking at the TRM of AM335x I can come up with 0x0238 (0x44e10800 -
> > 0x44e10a38), but I don't see any sings of the remaining 0x0100 to be
> > documented at least.
> 
> No, pinmux registers are available till 0x44E10B38, look at AM335x latest TRM
> or pinmux utility (we cannot find the exact offsets but pins we can find after
> 0x0A38, conf_ddr_resetn) at http://www.ti.com/tool/pinmuxtool

If you have a hole inbetween the registers it sounds like you also have core and
wkup domains? In that case those should be set up as separate controllers as other
SCM registers may be inbetween those domains.

Tony


From peter.ujfalusi at ti.com  Tue Aug  7 03:47:21 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 07 Aug 2012 10:47:21 +0300
Subject: [PATCH v2] ARM: OMAP4: twl-common: Support for additional devices
 on i2c1 bus
In-Reply-To: <20120807072041.GL11011@atomide.com>
References: <1342168682-15888-1-git-send-email-peter.ujfalusi@ti.com>
 <500D0FA5.3020208@ti.com> <20120807072041.GL11011@atomide.com>
Message-ID: <5020C809.9020009@ti.com>

Hi Tony,

On 08/07/2012 10:20 AM, Tony Lindgren wrote:
> Sorry things were getting already too complex for v3.6 merge window..

OK.

> So v3.7 it will be. Looks like this need to be updated against v3.6-rc1
> to apply.

I'll resend the updated patch on top of 3.6-rc1

Regards,
P?ter


From sachin.kamat at linaro.org  Tue Aug  7 04:03:22 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Tue, 7 Aug 2012 13:33:22 +0530
Subject: [PATCH v2 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1344324524-2286-3-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
 <1344324524-2286-3-git-send-email-p.paneri@samsung.com>
Message-ID: <CAK9yfHyJtM8p1wdS1B4LZPNL8SstP-tsgjKPyLtG4fQtBZyOUg@mail.gmail.com>

Hi Praveen,

Some minor comments:

On 7 August 2012 12:58, Praveen Paneri <p.paneri at samsung.com> wrote:
> Adding the transceiver to hsotg driver. Keeping the platform data
> for continuing the smooth operation for boards which still uses it
>
> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> ---
>  drivers/usb/gadget/s3c-hsotg.c |   38 ++++++++++++++++++++++++++++----------
>  1 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> index b13e0bb..f4ba9a3 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -32,6 +32,7 @@
>
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
> +#include <linux/usb/otg.h>
>  #include <linux/platform_data/s3c-hsotg.h>
>
>  #include <mach/map.h>
> @@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
>   * struct s3c_hsotg - driver state.
>   * @dev: The parent device supplied to the probe function
>   * @driver: USB gadget driver
> - * @plat: The platform specific configuration data.
> + * @phy: The otg phy transeiver structure for phy control.

s/transeiver/transceiver

> + * @plat: The platform specific configuration data. This can be removed once
> + * all SoCs support usb transceiver.
>   * @regs: The memory area mapped for accessing registers.
>   * @irq: The IRQ number we are using
>   * @supplies: Definition of USB power supplies
> @@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
>  struct s3c_hsotg {
>         struct device            *dev;
>         struct usb_gadget_driver *driver;
> +       struct usb_phy          *phy;
>         struct s3c_hsotg_plat    *plat;
>
>         spinlock_t              lock;
> @@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
>         struct platform_device *pdev = to_platform_device(hsotg->dev);
>
>         dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
> -       if (hsotg->plat->phy_init)
> +
> +       if (hsotg->phy)
> +               usb_phy_init(hsotg->phy);
> +       else if (hsotg->plat->phy_init)
>                 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
>  }
>
> @@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
>  {
>         struct platform_device *pdev = to_platform_device(hsotg->dev);
>
> -       if (hsotg->plat->phy_exit)
> +       if (hsotg->phy)
> +               usb_phy_shutdown(hsotg->phy);
> +       else if (hsotg->plat->phy_exit)
>                 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
>  }
>
> @@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
>  static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
>  {
>         struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
> +       struct usb_phy *phy;
>         struct device *dev = &pdev->dev;
>         struct s3c_hsotg_ep *eps;
>         struct s3c_hsotg *hsotg;
> @@ -3501,20 +3511,25 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
>         int ret;
>         int i;
>
> -       plat = pdev->dev.platform_data;
> -       if (!plat) {
> -               dev_err(&pdev->dev, "no platform data defined\n");
> -               return -EINVAL;
> -       }
> -
>         hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
>         if (!hsotg) {
>                 dev_err(dev, "cannot get memory\n");
>                 return -ENOMEM;
>         }
>
> +       phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
> +       if (!phy) {
> +               /* Fallback for platform data */
> +               plat = pdev->dev.platform_data;
> +               if (!plat) {
> +                       dev_err(&pdev->dev, "no platform data or transceiver defined\n");
> +                       return -ENODEV;
> +               } else
> +                       hsotg->plat = plat;
> +       } else
> +               hsotg->phy = phy;

Braces needed around the above 2 else statements.
Please refer to: Documentation/CodingStyle


> +
>         hsotg->dev = dev;
> -       hsotg->plat = plat;
>
>         hsotg->clk = clk_get(&pdev->dev, "otg");
>         if (IS_ERR(hsotg->clk)) {
> @@ -3689,6 +3704,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
>         s3c_hsotg_phy_disable(hsotg);
>         regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
>
> +       if (hsotg->phy)
> +               devm_usb_put_phy(&pdev->dev, hsotg->phy);
> +
>         clk_disable_unprepare(hsotg->clk);
>         clk_put(hsotg->clk);
>
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
With best regards,
Sachin


From dong.aisheng at linaro.org  Tue Aug  7 04:04:01 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Tue, 7 Aug 2012 16:04:01 +0800
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CAP1dx+wRZea8o8KTGRDCMtQkt7EjDRN5EoFek80OKqJgTxbvZA@mail.gmail.com>

Hi Uwe,

Thanks for the work. :)

Some minor format comment.
On 2 August 2012 23:39, Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> wrote:
........
> +Required properties:
> +- compatible: "fsl,imx35-iomuxc"
> +- fsl,pins: two integers array, represents a group of pins mux and config
> +  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
> +  pin working on a specific function, CONFIG is the pad setting value like
> +  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
s/imx53/imx35

> +See below for available PIN_FUNC_ID for imx35:
> +# grep '   IMX_PIN_REG' drivers/pinctrl/pinctrl-imx35.c | awk '{ print NR-1 " " $8 }'
> +0 MX35_PAD_CAPTURE__GPT_CAPIN1
> +1 MX35_PAD_CAPTURE__GPT_CMPOUT2
I'm not sure if you can use the format as exist IMX PIN_FUNC_ID tables as:
MX35_PAD_CAPTURE__GPT_CAPIN1        0
MX35_PAD_CAPTURE__GPT_CMPOUT2    1
Maybe the difficulty is the command (i did not know how to do it before),
If you know, we can do like that.
Anyway, it's not a big issue and does not block an ack.

> +enum imx35_pads {
> +       /* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
> +       MX35_PAD_CAPTURE,
> +       MX35_PAD_COMPARE,
> +       MX35_PAD_WDOG_RST,
> +       MX35_PAD_GPIO1_0,
> +       MX35_PAD_GPIO1_1,
> +       MX35_PAD_GPIO2_0,
> +       MX35_PAD_GPIO3_0,
Can we use the format as exist one?
enum imx53_pads {
        MX53_PAD_GPIO_19 = 1,
        MX53_PAD_KEY_COL0 = 2,
        MX53_PAD_KEY_ROW0 = 3,
        MX53_PAD_KEY_COL1 = 4,
.......
}
Then people can easy know its pin id.
I'm wondering there may be still some debug info are using pin id
then the above format helps.

.......
> +module_exit(imx35_pinctrl_exit);
> +MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
Not your name?

Otherwise,
you can add my ACK.

Regards
Dong Aisheng


From kgene.kim at samsung.com  Tue Aug  7 04:09:28 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 07 Aug 2012 17:09:28 +0900
Subject: [PATCH 1/2] ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
References: <1337307497-15777-1-git-send-email-jy0922.shim@samsung.com>
 <4FB5B9A1.2030606@samsung.com>
Message-ID: <097501cd7473$f73e51d0$e5baf570$%kim@samsung.com>

Kukjin Kim wrote:
> 
> Joonyoung Shim wrote:
> >
> > Add to cc Grant Likely and Linus Walleij
> >
> > On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
> > > Also use EXYNOS4210_GPIO_Ex instead of EXYNOS4_GPIO_Ex. The GPEx gpios
> > > exist only on Exynos4210 and there are no on Exynos4x12. Redefine them
> > > to exact SoC name.
> > >
> > > Signed-off-by: Joonyoung Shim<jy0922.shim at samsung.com>
> > > Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> > > ---
> > >   arch/arm/mach-exynos/include/mach/gpio.h   |   32
++++++++++++++------
> --
> > ------
> > >   arch/arm/mach-exynos/mach-nuri.c           |   16 +++++++-------
> > >   arch/arm/mach-exynos/mach-origen.c         |    6 ++--
> > >   arch/arm/mach-exynos/mach-universal_c210.c |   32
++++++++++++++-----
> --
> > -------
> > >   arch/arm/mach-exynos/setup-fimc.c          |    4 +-
> > >   drivers/gpio/gpio-samsung.c                |   20 ++++++++--------
> > >   6 files changed, 55 insertions(+), 55 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-
> > exynos/include/mach/gpio.h
> > > index eb24f1e..21c9bf1 100644
> > > --- a/arch/arm/mach-exynos/include/mach/gpio.h
> > > +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> > > @@ -26,11 +26,11 @@
> > >   #define EXYNOS4_GPIO_C1_NR	(5)
> > >   #define EXYNOS4_GPIO_D0_NR	(4)
> > >   #define EXYNOS4_GPIO_D1_NR	(4)
> > > -#define EXYNOS4_GPIO_E0_NR	(5)
> > > -#define EXYNOS4_GPIO_E1_NR	(8)
> > > -#define EXYNOS4_GPIO_E2_NR	(6)
> > > -#define EXYNOS4_GPIO_E3_NR	(8)
> > > -#define EXYNOS4_GPIO_E4_NR	(8)
> > > +#define EXYNOS4210_GPIO_E0_NR	(5)
> > > +#define EXYNOS4210_GPIO_E1_NR	(8)
> > > +#define EXYNOS4210_GPIO_E2_NR	(6)
> > > +#define EXYNOS4210_GPIO_E3_NR	(8)
> > > +#define EXYNOS4210_GPIO_E4_NR	(8)
> 
> I think, splitting the gpios like following(common exynos4 and exynos4210
> or exynos4x12). So please just put the definitions for EXYNOS4210 GPIO
> after EXYNOS4_GPIO_XXX.
> 
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-
> exynos/include/mach/gpio.h
> index eb24f1e..910b611 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -26,17 +26,10 @@
>  #define EXYNOS4_GPIO_C1_NR	(5)
>  #define EXYNOS4_GPIO_D0_NR	(4)
>  #define EXYNOS4_GPIO_D1_NR	(4)
> -#define EXYNOS4_GPIO_E0_NR	(5)
> -#define EXYNOS4_GPIO_E1_NR	(8)
> -#define EXYNOS4_GPIO_E2_NR	(6)
> -#define EXYNOS4_GPIO_E3_NR	(8)
> -#define EXYNOS4_GPIO_E4_NR	(8)
>  #define EXYNOS4_GPIO_F0_NR	(8)
>  #define EXYNOS4_GPIO_F1_NR	(8)
>  #define EXYNOS4_GPIO_F2_NR	(8)
>  #define EXYNOS4_GPIO_F3_NR	(6)
> -#define EXYNOS4_GPIO_J0_NR	(8)
> -#define EXYNOS4_GPIO_J1_NR	(5)
>  #define EXYNOS4_GPIO_K0_NR	(7)
>  #define EXYNOS4_GPIO_K1_NR	(7)
>  #define EXYNOS4_GPIO_K2_NR	(7)
> @@ -57,6 +50,31 @@
>  #define EXYNOS4_GPIO_Y6_NR	(8)
>  #define EXYNOS4_GPIO_Z_NR	(7)
> 
> +/* For EXYNOS4210 GPIO bank sizes */
> +
> +#define EXYNOS4210_GPIO_E0_NR	(5)
> +#define EXYNOS4210_GPIO_E1_NR	(8)
> +#define EXYNOS4210_GPIO_E2_NR	(6)
> +#define EXYNOS4210_GPIO_E3_NR	(8)
> +#define EXYNOS4210_GPIO_E4_NR	(8)
> +#define EXYNOS4210_GPIO_J0_NR	(8)
> +#define EXYNOS4210_GPIO_J1_NR	(5)
> 
> [...]
> 
> And we can add EXYNOS4X12 GPIO like following in other patch.
> 
> +/* For EXYNOS4X12 GPIO bank sizes */
> +
> +#define EXYNOS4X12_GPIO_J0_NR	(8)
> +#define EXYNOS4X12_GPIO_J1_NR	(5)
> +#define EXYNOS4X12_GPIO_M0_NR	(8)
> +#define EXYNOS4X12_GPIO_M1_NR	(7)
> +#define EXYNOS4X12_GPIO_M2_NR	(5)
> +#define EXYNOS4X12_GPIO_M3_NR	(8)
> +#define EXYNOS4X12_GPIO_M4_NR	(8)
> +#define EXYNOS4X12_GPIO_V0_NR	(8)
> +#define EXYNOS4X12_GPIO_V1_NR	(8)
> +#define EXYNOS4X12_GPIO_V2_NR	(8)
> +#define EXYNOS4X12_GPIO_V3_NR	(8)
> +#define EXYNOS4X12_GPIO_V4_NR	(2)
> 
> > >   #define EXYNOS4_GPIO_F0_NR	(8)
> > >   #define EXYNOS4_GPIO_F1_NR	(8)
> > >   #define EXYNOS4_GPIO_F2_NR	(8)
> > > @@ -67,12 +67,12 @@ enum exynos4_gpio_number {
> > >   	EXYNOS4_GPIO_C1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
> > >   	EXYNOS4_GPIO_D0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
> > >   	EXYNOS4_GPIO_D1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
> > > -	EXYNOS4_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
> > > -	EXYNOS4_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
> > > -	EXYNOS4_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
> > > -	EXYNOS4_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
> > > -	EXYNOS4_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
> > > -	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
> > > +	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
> > > +	EXYNOS4210_GPIO_E1_START	=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
> > > +	EXYNOS4210_GPIO_E2_START	=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
> > > +	EXYNOS4210_GPIO_E3_START	=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
> > > +	EXYNOS4210_GPIO_E4_START	=
EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
> > > +	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
> > >   	EXYNOS4_GPIO_F1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
> > >   	EXYNOS4_GPIO_F2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
> > >   	EXYNOS4_GPIO_F3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
> 
> Same as above.
> 
> @@ -99,6 +117,31 @@ enum exynos4_gpio_number {
>  	EXYNOS4_GPIO_Z_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
>  };
> 
> +enum exynos4210_gpio_number {
> +	EXYNOS4210_GPIO_E0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
> +	EXYNOS4210_GPIO_E1_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),
> +	EXYNOS4210_GPIO_E2_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),
> +	EXYNOS4210_GPIO_E3_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),
> +	EXYNOS4210_GPIO_E4_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),
> +	EXYNOS4210_GPIO_J0_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),
> +	EXYNOS4210_GPIO_J1_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),
> +};
> 
> [...]
> 
> And following is possible for EXYNOS4X12...
> 
> +enum exynos4x12_gpio_number {
> +	EXYNOS4X12_GPIO_J0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
> +	EXYNOS4X12_GPIO_J1_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J0),
> +	EXYNOS4X12_GPIO_M0_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J1),
> +	EXYNOS4X12_GPIO_M1_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
> +	EXYNOS4X12_GPIO_M2_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
> +	EXYNOS4X12_GPIO_M3_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
> +	EXYNOS4X12_GPIO_M4_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
> +	EXYNOS4X12_GPIO_V0_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
> +	EXYNOS4X12_GPIO_V1_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V0),
> +	EXYNOS4X12_GPIO_V2_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V1),
> +	EXYNOS4X12_GPIO_V3_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V2),
> +	EXYNOS4X12_GPIO_V4_START	=
EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V3),
> +};
> +
>  /* EXYNOS4 GPIO number definitions */
> 
>  #define EXYNOS4_GPA0(_nr)	(EXYNOS4_GPIO_A0_START + (_nr))
> 
> [...]
> 
> Of course, need to update other regarding gpio part accordingly.
> 
Joonyoung, any updates on this?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From heiko at sntech.de  Tue Aug  7 04:11:22 2012
From: heiko at sntech.de (Heiko =?iso-8859-15?q?St=FCbner?=)
Date: Tue, 7 Aug 2012 10:11:22 +0200
Subject: [PATCH v2 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <1344324524-2286-2-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
 <1344324524-2286-2-git-send-email-p.paneri@samsung.com>
Message-ID: <201208071011.23558.heiko@sntech.de>

Am Dienstag, 7. August 2012, 09:28:40 schrieb Praveen Paneri:
> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> smdk6410 and smdkv310. More SoCs can be brought under later.
>
> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/samsung_usbphy.c                   |  355
> ++++++++++++++++++++ drivers/usb/phy/samsung_usbphy.h                   | 
>  48 +++
>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>  6 files changed, 426 insertions(+), 0 deletions(-)
>  create mode 100644
> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
> 100644 drivers/usb/phy/samsung_usbphy.c
>  create mode 100644 drivers/usb/phy/samsung_usbphy.h
> 

[...]

> diff --git a/include/linux/platform_data/s3c-hsotg.h
> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
> --- a/include/linux/platform_data/s3c-hsotg.h
> +++ b/include/linux/platform_data/s3c-hsotg.h
> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>  	int (*phy_exit)(struct platform_device *pdev, int type);
>  };
> 
> +struct s3c_usbphy_plat {
> +	void (*pmu_isolation)(int on);
> +};
> +
>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
> 
>  #endif /* __LINUX_USB_S3C_HSOTG_H */

hmm, I'm not completely sure about this being in the s3c-hsotg header, as on 
s3c2443/2416/2450 it's the s3c-hsudc that will be (hopefully) using the phy in 
the future.


Heiko


From tony at atomide.com  Tue Aug  7 02:50:55 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 6 Aug 2012 23:50:55 -0700
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be
 used on both cpus
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA7F6C3@DBDE01.ent.ti.com>
References: <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>
 <501B7AE6.8080405@gmail.com>
 <76308EBE-F802-411A-973A-7BBC7575FE5A@dominion.thruhere.net>
 <BDB76D4F-31B0-47D0-B1A1-64A743D091D3@dominion.thruhere.net>
 <CAMQu2gxLAVk-LN8R1xBeeL1=iZ-mLSRmtZe4wpQYQPTBsY5RMA@mail.gmail.com>
 <FF29FBF3-67EC-478E-9A74-65F8A2870BDC@dominion.thruhere.net>
 <79CD15C6BA57404B839C016229A409A83EA7F59B@DBDE01.ent.ti.com>
 <A6396D46-C6B9-44A4-A960-657668AF08E4@dominion.thruhere.net>
 <CAMQu2gz-93W9zWD_v3m1nQkqmnvFwcWKDTxNsf0v39y9_rhQPA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA7F6C3@DBDE01.ent.ti.com>
Message-ID: <20120807065054.GH11011@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120803 03:34]:
> 
> Actually its not that.
> AM335x needs to be added as part of cpu_class_is_omap2(), without this it 
> gets into issues. 
> The patch has been already submitted to the list, but still not merged by 
> Tony.

Let's just add it to the list of cpu_class_is_omap2() with a proper patch
description for the fix. Then we still need to sort it out properly from
common zImage point of view without having to maintain that list.

Vaibhav, can you please post your original patch with the description
updated for v3.6-rc1?

Regards,

Tony


From cmahapatra at ti.com  Tue Aug  7 04:28:59 2012
From: cmahapatra at ti.com (Chandrabhanu Mahapatra)
Date: Tue, 7 Aug 2012 13:58:59 +0530
Subject: [PATCH 5/6] ARM: OMAP: Disable venc for OMAP4
In-Reply-To: <cover.1343912532.git.cmahapatra@ti.com>
References: <cover.1343912532.git.cmahapatra@ti.com>
Message-ID: <e99477f7030c655ef6f560adafcb30a7328f12cb.1343912533.git.cmahapatra@ti.com>

This is a alternative to "HACK: OMAP: DSS2: VENC: disable VENC on OMAP4 to
prevent crash" (ba02fa37de) by Tomi Valkeinen <tomi.valkeinen at ti.com> to prevent
VENC from crashing OMAP4 kernel. This prevents OMAPDSS from initial registration
of a device for VENC on OMAP4.

Signed-off-by: Chandrabhanu Mahapatra <cmahapatra at ti.com>
---
 arch/arm/mach-omap2/display.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d..ee40739 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -95,7 +95,6 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
-	{ "dss_venc", "omapdss_venc", -1 },
 	{ "dss_dsi1", "omapdss_dsi", 0 },
 	{ "dss_dsi2", "omapdss_dsi", 1 },
 	{ "dss_hdmi", "omapdss_hdmi", -1 },
-- 
1.7.10



From u.kleine-koenig at pengutronix.de  Tue Aug  7 04:49:04 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 7 Aug 2012 10:49:04 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <CAP1dx+wRZea8o8KTGRDCMtQkt7EjDRN5EoFek80OKqJgTxbvZA@mail.gmail.com>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <CAP1dx+wRZea8o8KTGRDCMtQkt7EjDRN5EoFek80OKqJgTxbvZA@mail.gmail.com>
Message-ID: <20120807084904.GA9888@pengutronix.de>

Hi,

On Tue, Aug 07, 2012 at 04:04:01PM +0800, Dong Aisheng wrote:
> Some minor format comment.
> On 2 August 2012 23:39, Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> wrote:
> ........
> > +Required properties:
> > +- compatible: "fsl,imx35-iomuxc"
> > +- fsl,pins: two integers array, represents a group of pins mux and config
> > +  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
> > +  pin working on a specific function, CONFIG is the pad setting value like
> > +  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
> s/imx53/imx35
obviously.

> > +See below for available PIN_FUNC_ID for imx35:
> > +# grep '   IMX_PIN_REG' drivers/pinctrl/pinctrl-imx35.c | awk '{ print NR-1 " " $8 }'
> > +0 MX35_PAD_CAPTURE__GPT_CAPIN1
> > +1 MX35_PAD_CAPTURE__GPT_CMPOUT2
> I'm not sure if you can use the format as exist IMX PIN_FUNC_ID tables as:
> MX35_PAD_CAPTURE__GPT_CAPIN1        0
> MX35_PAD_CAPTURE__GPT_CMPOUT2    1
I choosed to switch the order here to have a more column like format.
the length of the numbers is more uniform. I can switch if you want.

> Maybe the difficulty is the command (i did not know how to do it before),
> If you know, we can do like that.
> Anyway, it's not a big issue and does not block an ack.
> 
> > +enum imx35_pads {
> > +       /* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
> > +       MX35_PAD_CAPTURE,
> > +       MX35_PAD_COMPARE,
> > +       MX35_PAD_WDOG_RST,
> > +       MX35_PAD_GPIO1_0,
> > +       MX35_PAD_GPIO1_1,
> > +       MX35_PAD_GPIO2_0,
> > +       MX35_PAD_GPIO3_0,
> Can we use the format as exist one?
> enum imx53_pads {
>         MX53_PAD_GPIO_19 = 1,
>         MX53_PAD_KEY_COL0 = 2,
>         MX53_PAD_KEY_ROW0 = 3,
>         MX53_PAD_KEY_COL1 = 4,
> .......
> }
> Then people can easy know its pin id.
> I'm wondering there may be still some debug info are using pin id
> then the above format helps.
I didn't see output referring to pin ids (which doesn't mean it doesn't
exist of course). I don't care much and wondered why you started at 1
and not 0. All it all it was just lazyness on my side not to add the
numers.
 
> > +module_exit(imx35_pinctrl_exit);
> > +MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
> Not your name?
No, I only did

	cp drivers/pinctrl/pinctrl-imx{51,35}.c

and fixed the tables and names for i.MX35. It's OK for me when you get
the blame. :-)

> Otherwise,
> you can add my ACK.
Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From anilkumar at ti.com  Tue Aug  7 04:50:44 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 7 Aug 2012 08:50:44 +0000
Subject: [PATCH RESEND v2 1/2] arm/dts: Add AM33XX basic pinctrl support
In-Reply-To: <20120807074348.GQ11011@atomide.com>
References: <1343144719-26352-1-git-send-email-anilkumar@ti.com>
 <1343144719-26352-2-git-send-email-anilkumar@ti.com>
 <50125B1C.8000209@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
 <20120807074348.GQ11011@atomide.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA0D156@DBDE01.ent.ti.com>

Hi Tony,

On Tue, Aug 07, 2012 at 13:13:48, Tony Lindgren wrote:
> * AnilKumar, Chimata <anilkumar at ti.com> [120731 06:37]:
> > Hi Peter,
> > 
> > On Fri, Jul 27, 2012 at 14:40:52, Ujfalusi, Peter wrote:
> > > Hi,
> > > 
> > > On 07/24/2012 06:45 PM, AnilKumar Ch wrote:
> > > > Adds basic pinctrl support for AM33XX family of devices. This patch
> > > > is based on the pinctrl-simple driver submitted by Tony Lindgren's
> > > > here: http://lwn.net/Articles/496075/
> > > > 
> > > > Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> > > > ---
> > > >  arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> > > > index 59509c4..9b974dc 100644
> > > > --- a/arch/arm/boot/dts/am33xx.dtsi
> > > > +++ b/arch/arm/boot/dts/am33xx.dtsi
> > > > @@ -40,6 +40,15 @@
> > > >  		};
> > > >  	};
> > > >  
> > > > +	am3358_pinmux: pinmux at 44E10800 {
> > > > +		compatible = "pinctrl-single";
> > > > +		reg = <0x44E10800 0x0338>;
> > > 
> > > I'm just curious about the size here: how it ended up as 0x0338?
> > > While looking at the TRM of AM335x I can come up with 0x0238 (0x44e10800 -
> > > 0x44e10a38), but I don't see any sings of the remaining 0x0100 to be
> > > documented at least.
> > 
> > No, pinmux registers are available till 0x44E10B38, look at AM335x latest TRM
> > or pinmux utility (we cannot find the exact offsets but pins we can find after
> > 0x0A38, conf_ddr_resetn) at http://www.ti.com/tool/pinmuxtool
> 
> If you have a hole inbetween the registers it sounds like you also have core and
> wkup domains? In that case those should be set up as separate controllers as other
> SCM registers may be inbetween those domains.
> 

In case of AM33XX we have only one padconf domain and it do not have any holes
in between.

Regards
AnilKumar


From arnd at arndb.de  Tue Aug  7 04:30:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 08:30:01 +0000
Subject: [PATCH] arm/dts: omap5: Add mmc controller nodes and board data
In-Reply-To: <1344323901-20342-1-git-send-email-balajitk@ti.com>
References: <1344323901-20342-1-git-send-email-balajitk@ti.com>
Message-ID: <201208070830.01776.arnd@arndb.de>

On Tuesday 07 August 2012, Balaji T K wrote:
> 
> Add OMAP MMC related device tree data for OMAP5.
> 
> Signed-off-by: Balaji T K <balajitk at ti.com>
> ---

Acked-by: Arnd Bergmann <arnd at arndb.de>



From arnd at arndb.de  Tue Aug  7 05:21:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 09:21:35 +0000
Subject: [PATCH 1/1] ARM: kirkwood: fix typo in Makefile.boot
In-Reply-To: <1344177932-6466-1-git-send-email-sebastian.hesselbarth@googlemail.com>
References: <1344177932-6466-1-git-send-email-sebastian.hesselbarth@googlemail.com>
Message-ID: <201208070921.35459.arnd@arndb.de>

On Sunday 05 August 2012, Sebastian Hesselbarth wrote:
> Just a small typo fix to make lsxl dtbs compile
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at googlemail.com>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  arch/arm/mach-kirkwood/Makefile.boot |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index 2a576ab..a571755 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -9,5 +9,5 @@ dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
>  dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
>  dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
> -dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
> -dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> +dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
> +dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb

As Jason and Andrew are both currently unavailable, I'm applying this directly
to the fixes branch in arm-soc.

	Arnd


From l.krishna at samsung.com  Tue Aug  7 05:37:54 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:54 +0530
Subject: [PATCH V3 0/5] arm: samsung: Move FIMD headers to include/video/
Message-ID: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>

This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch side
to include/video/samsung_fimd.h

This patchset is created and rebased against master branch of torvalds tree.
Tested on smdk5250 board, build tested for other boards.

Changes from version 2:
	- Changed the EXYNOS5_xxx macro name to FIMD_V8_xxx
	- Moved the header inclusion under same kind

Changes from version 1:
	- Split the patches as per Sylwester comments
	- Changed FIMD_V8_xxx macro to EXYNOS5_xxx	

Leela Krishna Amudala (5):
  include/video: Add samsung FIMD register header
  include/video: Add Exynos5 specific FIMD register offsets
  arm: samsung: Include the modified FIMD header file
  driver: Include the modified FIMD header file
  arm: samsung: delete frame buffer header files from platform

 arch/arm/mach-exynos/mach-nuri.c                |    2 +-
 arch/arm/mach-exynos/mach-origen.c              |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c            |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c            |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c      |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c            |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c            |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c            |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c           |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c           |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c           |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c           |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c             |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c               |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c           |    2 +-
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h |  159 -------
 arch/arm/plat-samsung/include/plat/regs-fb.h    |  403 -----------------
 drivers/gpu/drm/exynos/exynos_drm_fimd.c        |    2 +-
 drivers/video/s3c-fb.c                          |    2 +-
 include/video/samsung_fimd.h                    |  533 +++++++++++++++++++++++
 27 files changed, 557 insertions(+), 586 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
 create mode 100644 include/video/samsung_fimd.h



From l.krishna at samsung.com  Tue Aug  7 05:37:55 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:55 +0530
Subject: [PATCH V3 1/5] include/video: Add samsung FIMD register header
In-Reply-To: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
References: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344332279-16736-2-git-send-email-l.krishna@samsung.com>

This patch copies the contents from regs-fb-v4.h and regs-fb.h to
include/video/samsung_fimd.h

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 include/video/samsung_fimd.h |  526 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 526 insertions(+), 0 deletions(-)
 create mode 100644 include/video/samsung_fimd.h

diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
new file mode 100644
index 0000000..e979f42
--- /dev/null
+++ b/include/video/samsung_fimd.h
@@ -0,0 +1,526 @@
+/* include/video/samsung_fimd.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben at simtec.co.uk>
+ *
+ * S3C Platform - new-style fimd and framebuffer register definitions
+ *
+ * This is the register set for the fimd and new style framebuffer interface
+ * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
+ * S3C64XX series such as the S3C6400 and S3C6410.
+ *
+ * The file does not contain the cpu specific items which are based on
+ * whichever architecture is selected, it only contains the core of the
+ * register set. See <mach/regs-fb.h> to get the specifics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* VIDCON0 */
+
+#define VIDCON0					(0x00)
+#define VIDCON0_INTERLACE			(1 << 29)
+#define VIDCON0_VIDOUT_MASK			(0x3 << 26)
+#define VIDCON0_VIDOUT_SHIFT			(26)
+#define VIDCON0_VIDOUT_RGB			(0x0 << 26)
+#define VIDCON0_VIDOUT_TV			(0x1 << 26)
+#define VIDCON0_VIDOUT_I80_LDI0			(0x2 << 26)
+#define VIDCON0_VIDOUT_I80_LDI1			(0x3 << 26)
+
+#define VIDCON0_L1_DATA_MASK			(0x7 << 23)
+#define VIDCON0_L1_DATA_SHIFT			(23)
+#define VIDCON0_L1_DATA_16BPP			(0x0 << 23)
+#define VIDCON0_L1_DATA_18BPP16			(0x1 << 23)
+#define VIDCON0_L1_DATA_18BPP9			(0x2 << 23)
+#define VIDCON0_L1_DATA_24BPP			(0x3 << 23)
+#define VIDCON0_L1_DATA_18BPP			(0x4 << 23)
+#define VIDCON0_L1_DATA_16BPP8			(0x5 << 23)
+
+#define VIDCON0_L0_DATA_MASK			(0x7 << 20)
+#define VIDCON0_L0_DATA_SHIFT			(20)
+#define VIDCON0_L0_DATA_16BPP			(0x0 << 20)
+#define VIDCON0_L0_DATA_18BPP16			(0x1 << 20)
+#define VIDCON0_L0_DATA_18BPP9			(0x2 << 20)
+#define VIDCON0_L0_DATA_24BPP			(0x3 << 20)
+#define VIDCON0_L0_DATA_18BPP			(0x4 << 20)
+#define VIDCON0_L0_DATA_16BPP8			(0x5 << 20)
+
+#define VIDCON0_PNRMODE_MASK			(0x3 << 17)
+#define VIDCON0_PNRMODE_SHIFT			(17)
+#define VIDCON0_PNRMODE_RGB			(0x0 << 17)
+#define VIDCON0_PNRMODE_BGR			(0x1 << 17)
+#define VIDCON0_PNRMODE_SERIAL_RGB		(0x2 << 17)
+#define VIDCON0_PNRMODE_SERIAL_BGR		(0x3 << 17)
+
+#define VIDCON0_CLKVALUP			(1 << 16)
+#define VIDCON0_CLKVAL_F_MASK			(0xff << 6)
+#define VIDCON0_CLKVAL_F_SHIFT			(6)
+#define VIDCON0_CLKVAL_F_LIMIT			(0xff)
+#define VIDCON0_CLKVAL_F(_x)			((_x) << 6)
+#define VIDCON0_VLCKFREE			(1 << 5)
+#define VIDCON0_CLKDIR				(1 << 4)
+
+#define VIDCON0_CLKSEL_MASK			(0x3 << 2)
+#define VIDCON0_CLKSEL_SHIFT			(2)
+#define VIDCON0_CLKSEL_HCLK			(0x0 << 2)
+#define VIDCON0_CLKSEL_LCD			(0x1 << 2)
+#define VIDCON0_CLKSEL_27M			(0x3 << 2)
+
+#define VIDCON0_ENVID				(1 << 1)
+#define VIDCON0_ENVID_F				(1 << 0)
+
+#define VIDCON1					(0x04)
+#define VIDCON1_LINECNT_MASK			(0x7ff << 16)
+#define VIDCON1_LINECNT_SHIFT			(16)
+#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 16) & 0x7ff)
+#define VIDCON1_VSTATUS_MASK			(0x3 << 13)
+#define VIDCON1_VSTATUS_SHIFT			(13)
+#define VIDCON1_VSTATUS_VSYNC			(0x0 << 13)
+#define VIDCON1_VSTATUS_BACKPORCH		(0x1 << 13)
+#define VIDCON1_VSTATUS_ACTIVE			(0x2 << 13)
+#define VIDCON1_VSTATUS_FRONTPORCH		(0x0 << 13)
+#define VIDCON1_VCLK_MASK			(0x3 << 9)
+#define VIDCON1_VCLK_HOLD			(0x0 << 9)
+#define VIDCON1_VCLK_RUN			(0x1 << 9)
+
+#define VIDCON1_INV_VCLK			(1 << 7)
+#define VIDCON1_INV_HSYNC			(1 << 6)
+#define VIDCON1_INV_VSYNC			(1 << 5)
+#define VIDCON1_INV_VDEN			(1 << 4)
+
+/* VIDCON2 */
+
+#define VIDCON2					(0x08)
+#define VIDCON2_EN601				(1 << 23)
+#define VIDCON2_TVFMTSEL_SW			(1 << 14)
+
+#define VIDCON2_TVFMTSEL1_MASK			(0x3 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT			(12)
+#define VIDCON2_TVFMTSEL1_RGB			(0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422		(0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444		(0x2 << 12)
+
+#define VIDCON2_ORGYCbCr			(1 << 8)
+#define VIDCON2_YUVORDCrCb			(1 << 7)
+
+/* PRTCON (S3C6410, S5PC100)
+ * Might not be present in the S3C6410 documentation,
+ * but tests prove it's there almost for sure; shouldn't hurt in any case.
+ */
+#define PRTCON					(0x0c)
+#define PRTCON_PROTECT				(1 << 11)
+
+/* VIDTCON0 */
+
+#define VIDTCON0_VBPDE_MASK			(0xff << 24)
+#define VIDTCON0_VBPDE_SHIFT			(24)
+#define VIDTCON0_VBPDE_LIMIT			(0xff)
+#define VIDTCON0_VBPDE(_x)			((_x) << 24)
+
+#define VIDTCON0_VBPD_MASK			(0xff << 16)
+#define VIDTCON0_VBPD_SHIFT			(16)
+#define VIDTCON0_VBPD_LIMIT			(0xff)
+#define VIDTCON0_VBPD(_x)			((_x) << 16)
+
+#define VIDTCON0_VFPD_MASK			(0xff << 8)
+#define VIDTCON0_VFPD_SHIFT			(8)
+#define VIDTCON0_VFPD_LIMIT			(0xff)
+#define VIDTCON0_VFPD(_x)			((_x) << 8)
+
+#define VIDTCON0_VSPW_MASK			(0xff << 0)
+#define VIDTCON0_VSPW_SHIFT			(0)
+#define VIDTCON0_VSPW_LIMIT			(0xff)
+#define VIDTCON0_VSPW(_x)			((_x) << 0)
+
+/* VIDTCON1 */
+
+#define VIDTCON1_VFPDE_MASK			(0xff << 24)
+#define VIDTCON1_VFPDE_SHIFT			(24)
+#define VIDTCON1_VFPDE_LIMIT			(0xff)
+#define VIDTCON1_VFPDE(_x)			((_x) << 24)
+
+#define VIDTCON1_HBPD_MASK			(0xff << 16)
+#define VIDTCON1_HBPD_SHIFT			(16)
+#define VIDTCON1_HBPD_LIMIT			(0xff)
+#define VIDTCON1_HBPD(_x)			((_x) << 16)
+
+#define VIDTCON1_HFPD_MASK			(0xff << 8)
+#define VIDTCON1_HFPD_SHIFT			(8)
+#define VIDTCON1_HFPD_LIMIT			(0xff)
+#define VIDTCON1_HFPD(_x)			((_x) << 8)
+
+#define VIDTCON1_HSPW_MASK			(0xff << 0)
+#define VIDTCON1_HSPW_SHIFT			(0)
+#define VIDTCON1_HSPW_LIMIT			(0xff)
+#define VIDTCON1_HSPW(_x)			((_x) << 0)
+
+#define VIDTCON2				(0x18)
+#define VIDTCON2_LINEVAL_E(_x)			((((_x) & 0x800) >> 11) << 23)
+#define VIDTCON2_LINEVAL_MASK			(0x7ff << 11)
+#define VIDTCON2_LINEVAL_SHIFT			(11)
+#define VIDTCON2_LINEVAL_LIMIT			(0x7ff)
+#define VIDTCON2_LINEVAL(_x)			(((_x) & 0x7ff) << 11)
+
+#define VIDTCON2_HOZVAL_E(_x)			((((_x) & 0x800) >> 11) << 22)
+#define VIDTCON2_HOZVAL_MASK			(0x7ff << 0)
+#define VIDTCON2_HOZVAL_SHIFT			(0)
+#define VIDTCON2_HOZVAL_LIMIT			(0x7ff)
+#define VIDTCON2_HOZVAL(_x)			(((_x) & 0x7ff) << 0)
+
+/* WINCONx */
+
+
+#define WINCONx_BITSWP				(1 << 18)
+#define WINCONx_BYTSWP				(1 << 17)
+#define WINCONx_HAWSWP				(1 << 16)
+#define WINCONx_WSWP				(1 << 15)
+#define WINCONx_BURSTLEN_MASK			(0x3 << 9)
+#define WINCONx_BURSTLEN_SHIFT			(9)
+#define WINCONx_BURSTLEN_16WORD			(0x0 << 9)
+#define WINCONx_BURSTLEN_8WORD			(0x1 << 9)
+#define WINCONx_BURSTLEN_4WORD			(0x2 << 9)
+
+#define WINCONx_ENWIN				(1 << 0)
+#define WINCON0_BPPMODE_MASK			(0xf << 2)
+#define WINCON0_BPPMODE_SHIFT			(2)
+#define WINCON0_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON0_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON0_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON0_BPPMODE_8BPP_PALETTE		(0x3 << 2)
+#define WINCON0_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON0_BPPMODE_16BPP_1555		(0x7 << 2)
+#define WINCON0_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON0_BPPMODE_24BPP_888		(0xb << 2)
+
+#define WINCON1_BLD_PIX				(1 << 6)
+
+#define WINCON1_ALPHA_SEL			(1 << 1)
+#define WINCON1_BPPMODE_MASK			(0xf << 2)
+#define WINCON1_BPPMODE_SHIFT			(2)
+#define WINCON1_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON1_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON1_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON1_BPPMODE_8BPP_PALETTE		(0x3 << 2)
+#define WINCON1_BPPMODE_8BPP_1232		(0x4 << 2)
+#define WINCON1_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON1_BPPMODE_16BPP_A1555		(0x6 << 2)
+#define WINCON1_BPPMODE_16BPP_I1555		(0x7 << 2)
+#define WINCON1_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON1_BPPMODE_18BPP_A1665		(0x9 << 2)
+#define WINCON1_BPPMODE_19BPP_A1666		(0xa << 2)
+#define WINCON1_BPPMODE_24BPP_888		(0xb << 2)
+#define WINCON1_BPPMODE_24BPP_A1887		(0xc << 2)
+#define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
+#define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
+
+/* S5PV210 */
+#define SHADOWCON				(0x34)
+#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
+/* DMA channels (all windows) */
+#define SHADOWCON_CHx_ENABLE(_win)		(1 << (_win))
+/* Local input channels (windows 0-2) */
+#define SHADOWCON_CHx_LOCAL_ENABLE(_win)	(1 << (5 + (_win)))
+
+#define VIDOSDxA_TOPLEFT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
+#define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
+#define VIDOSDxA_TOPLEFT_X_SHIFT		(11)
+#define VIDOSDxA_TOPLEFT_X_LIMIT		(0x7ff)
+#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x7ff) << 11)
+
+#define VIDOSDxA_TOPLEFT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
+#define VIDOSDxA_TOPLEFT_Y_MASK			(0x7ff << 0)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT		(0)
+#define VIDOSDxA_TOPLEFT_Y_LIMIT		(0x7ff)
+#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x7ff) << 0)
+
+#define VIDOSDxB_BOTRIGHT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
+#define VIDOSDxB_BOTRIGHT_X_MASK		(0x7ff << 11)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT		(11)
+#define VIDOSDxB_BOTRIGHT_X_LIMIT		(0x7ff)
+#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x7ff) << 11)
+
+#define VIDOSDxB_BOTRIGHT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
+#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x7ff << 0)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT		(0)
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT		(0x7ff)
+#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x7ff) << 0)
+
+/* For VIDOSD[1..4]C */
+#define VIDISD14C_ALPHA0_R(_x)			((_x) << 20)
+#define VIDISD14C_ALPHA0_G_MASK			(0xf << 16)
+#define VIDISD14C_ALPHA0_G_SHIFT		(16)
+#define VIDISD14C_ALPHA0_G_LIMIT		(0xf)
+#define VIDISD14C_ALPHA0_G(_x)			((_x) << 16)
+#define VIDISD14C_ALPHA0_B_MASK			(0xf << 12)
+#define VIDISD14C_ALPHA0_B_SHIFT		(12)
+#define VIDISD14C_ALPHA0_B_LIMIT		(0xf)
+#define VIDISD14C_ALPHA0_B(_x)			((_x) << 12)
+#define VIDISD14C_ALPHA1_R_MASK			(0xf << 8)
+#define VIDISD14C_ALPHA1_R_SHIFT		(8)
+#define VIDISD14C_ALPHA1_R_LIMIT		(0xf)
+#define VIDISD14C_ALPHA1_R(_x)			((_x) << 8)
+#define VIDISD14C_ALPHA1_G_MASK			(0xf << 4)
+#define VIDISD14C_ALPHA1_G_SHIFT		(4)
+#define VIDISD14C_ALPHA1_G_LIMIT		(0xf)
+#define VIDISD14C_ALPHA1_G(_x)			((_x) << 4)
+#define VIDISD14C_ALPHA1_B_MASK			(0xf << 0)
+#define VIDISD14C_ALPHA1_B_SHIFT		(0)
+#define VIDISD14C_ALPHA1_B_LIMIT		(0xf)
+#define VIDISD14C_ALPHA1_B(_x)			((_x) << 0)
+
+/* Video buffer addresses */
+#define VIDW_BUF_START(_buff)			(0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START1(_buff)			(0xA4 + ((_buff) * 8))
+#define VIDW_BUF_END(_buff)			(0xD0 + ((_buff) * 8))
+#define VIDW_BUF_END1(_buff)			(0xD4 + ((_buff) * 8))
+#define VIDW_BUF_SIZE(_buff)			(0x100 + ((_buff) * 4))
+
+#define VIDW_BUF_SIZE_OFFSET_E(_x)		((((_x) & 0x2000) >> 13) << 27)
+#define VIDW_BUF_SIZE_OFFSET_MASK		(0x1fff << 13)
+#define VIDW_BUF_SIZE_OFFSET_SHIFT		(13)
+#define VIDW_BUF_SIZE_OFFSET_LIMIT		(0x1fff)
+#define VIDW_BUF_SIZE_OFFSET(_x)		(((_x) & 0x1fff) << 13)
+
+#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)		((((_x) & 0x2000) >> 13) << 26)
+#define VIDW_BUF_SIZE_PAGEWIDTH_MASK		(0x1fff << 0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT		(0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT		(0x1fff)
+#define VIDW_BUF_SIZE_PAGEWIDTH(_x)		(((_x) & 0x1fff) << 0)
+
+/* Interrupt controls and status */
+
+#define VIDINTCON0_FIFOINTERVAL_MASK		(0x3f << 20)
+#define VIDINTCON0_FIFOINTERVAL_SHIFT		(20)
+#define VIDINTCON0_FIFOINTERVAL_LIMIT		(0x3f)
+#define VIDINTCON0_FIFOINTERVAL(_x)		((_x) << 20)
+
+#define VIDINTCON0_INT_SYSMAINCON		(1 << 19)
+#define VIDINTCON0_INT_SYSSUBCON		(1 << 18)
+#define VIDINTCON0_INT_I80IFDONE		(1 << 17)
+
+#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
+#define VIDINTCON0_FRAMESEL0_SHIFT		(15)
+#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
+#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
+#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
+#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
+
+#define VIDINTCON0_FRAMESEL1			(1 << 13)
+#define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
+#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
+#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
+
+#define VIDINTCON0_INT_FRAME			(1 << 12)
+#define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
+#define VIDINTCON0_FIFIOSEL_SHIFT		(5)
+#define VIDINTCON0_FIFIOSEL_WINDOW0		(0x1 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW1		(0x2 << 5)
+
+#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 2)
+#define VIDINTCON0_FIFOLEVEL_SHIFT		(2)
+#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x0 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x1 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO75PC		(0x2 << 2)
+#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x3 << 2)
+#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 2)
+
+#define VIDINTCON0_INT_FIFO_MASK		(0x3 << 0)
+#define VIDINTCON0_INT_FIFO_SHIFT		(0)
+#define VIDINTCON0_INT_ENABLE			(1 << 0)
+
+#define VIDINTCON1				(0x134)
+#define VIDINTCON1_INT_I180			(1 << 2)
+#define VIDINTCON1_INT_FRAME			(1 << 1)
+#define VIDINTCON1_INT_FIFO			(1 << 0)
+
+/* Window colour-key control registers */
+#define WKEYCON					(0x140)	/* 6410,V210 */
+
+#define WKEYCON0				(0x00)
+#define WKEYCON1				(0x04)
+
+#define WxKEYCON0_KEYBL_EN			(1 << 26)
+#define WxKEYCON0_KEYEN_F			(1 << 25)
+#define WxKEYCON0_DIRCON			(1 << 24)
+#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
+#define WxKEYCON0_COMPKEY_SHIFT			(0)
+#define WxKEYCON0_COMPKEY_LIMIT			(0xffffff)
+#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
+#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
+#define WxKEYCON1_COLVAL_SHIFT			(0)
+#define WxKEYCON1_COLVAL_LIMIT			(0xffffff)
+#define WxKEYCON1_COLVAL(_x)			((_x) << 0)
+
+
+/* Window blanking (MAP) */
+
+#define WINxMAP_MAP				(1 << 24)
+#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
+#define WINxMAP_MAP_COLOUR_SHIFT		(0)
+#define WINxMAP_MAP_COLOUR_LIMIT		(0xffffff)
+#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
+
+#define WPALCON_PAL_UPDATE			(1 << 9)
+#define WPALCON_W1PAL_MASK			(0x7 << 3)
+#define WPALCON_W1PAL_SHIFT			(3)
+#define WPALCON_W1PAL_25BPP_A888		(0x0 << 3)
+#define WPALCON_W1PAL_24BPP			(0x1 << 3)
+#define WPALCON_W1PAL_19BPP_A666		(0x2 << 3)
+#define WPALCON_W1PAL_18BPP_A665		(0x3 << 3)
+#define WPALCON_W1PAL_18BPP			(0x4 << 3)
+#define WPALCON_W1PAL_16BPP_A555		(0x5 << 3)
+#define WPALCON_W1PAL_16BPP_565			(0x6 << 3)
+
+#define WPALCON_W0PAL_MASK			(0x7 << 0)
+#define WPALCON_W0PAL_SHIFT			(0)
+#define WPALCON_W0PAL_25BPP_A888		(0x0 << 0)
+#define WPALCON_W0PAL_24BPP			(0x1 << 0)
+#define WPALCON_W0PAL_19BPP_A666		(0x2 << 0)
+#define WPALCON_W0PAL_18BPP_A665		(0x3 << 0)
+#define WPALCON_W0PAL_18BPP			(0x4 << 0)
+#define WPALCON_W0PAL_16BPP_A555		(0x5 << 0)
+#define WPALCON_W0PAL_16BPP_565			(0x6 << 0)
+
+/* Blending equation control */
+#define BLENDCON				(0x260)
+#define BLENDCON_NEW_MASK			(1 << 0)
+#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
+#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
+
+#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN	(1 << 15)
+
+/* Video timing controls */
+#define VIDTCON0				(0x10)
+#define VIDTCON1				(0x14)
+#define VIDTCON2				(0x18)
+
+/* Window position controls */
+
+#define WINCON(_win)				(0x20 + ((_win) * 4))
+
+/* OSD1 and OSD4 do not have register D */
+
+#define VIDOSD_BASE				(0x40)
+
+#define VIDINTCON0				(0x130)
+
+/* WINCONx */
+
+#define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT			(26)
+#define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
+
+#define WINCONx_ENLOCAL				(1 << 22)
+#define WINCONx_BUFSTATUS			(1 << 21)
+#define WINCONx_BUFSEL				(1 << 20)
+#define WINCONx_BUFAUTOEN			(1 << 19)
+#define WINCONx_YCbCr				(1 << 13)
+
+#define WINCON1_LOCALSEL_CAMIF			(1 << 23)
+
+#define WINCON2_LOCALSEL_CAMIF			(1 << 23)
+#define WINCON2_BLD_PIX				(1 << 6)
+
+#define WINCON2_ALPHA_SEL			(1 << 1)
+#define WINCON2_BPPMODE_MASK			(0xf << 2)
+#define WINCON2_BPPMODE_SHIFT			(2)
+#define WINCON2_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON2_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON2_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232		(0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555		(0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555		(0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665		(0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666		(0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888		(0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887		(0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888		(0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888		(0xd << 2)
+
+#define WINCON3_BLD_PIX				(1 << 6)
+
+#define WINCON3_ALPHA_SEL			(1 << 1)
+#define WINCON3_BPPMODE_MASK			(0xf << 2)
+#define WINCON3_BPPMODE_SHIFT			(2)
+#define WINCON3_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON3_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON3_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555		(0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555		(0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665		(0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666		(0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888		(0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887		(0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888		(0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888		(0xd << 2)
+
+#define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)
+
+#define DITHMODE				(0x170)
+#define WINxMAP(_win)				(0x180 + ((_win) * 4))
+
+
+#define DITHMODE_R_POS_MASK			(0x3 << 5)
+#define DITHMODE_R_POS_SHIFT			(5)
+#define DITHMODE_R_POS_8BIT			(0x0 << 5)
+#define DITHMODE_R_POS_6BIT			(0x1 << 5)
+#define DITHMODE_R_POS_5BIT			(0x2 << 5)
+
+#define DITHMODE_G_POS_MASK			(0x3 << 3)
+#define DITHMODE_G_POS_SHIFT			(3)
+#define DITHMODE_G_POS_8BIT			(0x0 << 3)
+#define DITHMODE_G_POS_6BIT			(0x1 << 3)
+#define DITHMODE_G_POS_5BIT			(0x2 << 3)
+
+#define DITHMODE_B_POS_MASK			(0x3 << 1)
+#define DITHMODE_B_POS_SHIFT			(1)
+#define DITHMODE_B_POS_8BIT			(0x0 << 1)
+#define DITHMODE_B_POS_6BIT			(0x1 << 1)
+#define DITHMODE_B_POS_5BIT			(0x2 << 1)
+
+#define DITHMODE_DITH_EN			(1 << 0)
+
+#define WPALCON					(0x1A0)
+
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555		(1 << 8)
+#define WPALCON_W3PAL_16BPP_A555		(1 << 7)
+#define WPALCON_W2PAL_16BPP_A555		(1 << 6)
+
+
+/* Notes on per-window bpp settings
+ *
+ * Value	Win0	 Win1	  Win2	   Win3	    Win 4
+ * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
+ * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
+ * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
+ * 0011		8(P)	 8(P)     -none-   -none-   -none-
+ * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
+ * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
+ * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
+ * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
+ * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
+ * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
+ * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
+ * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
+ * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
+ * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
+ * 1110		-none-	 -none-	  -none-   -none-    -none-
+ * 1111		-none-	 -none-   -none-   -none-    -none-
+*/
-- 
1.7.0.4



From l.krishna at samsung.com  Tue Aug  7 05:37:56 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:56 +0530
Subject: [PATCH V3 2/5] include/video: Add Exynos5 specific FIMD register
 offsets
In-Reply-To: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
References: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344332279-16736-3-git-send-email-l.krishna@samsung.com>

Exynos5 has VIDTCON and VIDCON registers at different offsets
from the previous SOCs. Hence, adding the macros.

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 include/video/samsung_fimd.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index e979f42..7ae6c07 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -524,3 +524,10 @@
  * 1110		-none-	 -none-	  -none-   -none-    -none-
  * 1111		-none-	 -none-   -none-   -none-    -none-
 */
+
+/* FIMD Version 8 register offset definitions */
+#define FIMD_V8_VIDTCON0	(0x20010)
+#define FIMD_V8_VIDTCON1	(0x20014)
+#define FIMD_V8_VIDTCON2	(0x20018)
+#define FIMD_V8_VIDTCON3	(0x2001C)
+#define FIMD_V8_VIDCON1		(0x20004)
-- 
1.7.0.4



From l.krishna at samsung.com  Tue Aug  7 05:37:57 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:57 +0530
Subject: [PATCH V3 3/5] arm: samsung: Include the modified FIMD header file
In-Reply-To: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
References: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344332279-16736-4-git-send-email-l.krishna@samsung.com>

The fimd register headers have been moved to include/video/
hence, modifying the machine files accordingly.

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 arch/arm/mach-exynos/mach-nuri.c           |    2 +-
 arch/arm/mach-exynos/mach-origen.c         |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c       |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c       |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c         |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c      |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c       |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c      |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c      |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c           |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c      |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c       |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c       |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c      |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c      |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c      |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c      |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c        |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c          |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c      |    2 +-
 22 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fc..90d8daa 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -29,6 +29,7 @@
 #include <drm/exynos_drm.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <media/m5mols.h>
 #include <media/s5k6aa.h>
 #include <media/s5p_fimc.h>
@@ -39,7 +40,6 @@
 #include <asm/mach-types.h>
 
 #include <plat/adc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5ca8030..4e245f1 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -29,9 +29,9 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index b26beb1..ee069b4 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -26,6 +26,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/backlight.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -35,7 +36,6 @@
 #include <plat/iic.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb.h>
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
 
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 3cfa688..b1c50da 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -26,9 +26,9 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 4d1f40d..8139cd2 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -30,6 +30,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -39,7 +40,6 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
 #include <plat/camport.h>
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
index 07a6dbe..5665bb4 100644
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -13,8 +13,8 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include <mach/map.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index c3100a0..96478f0 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -29,6 +29,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -52,7 +53,6 @@
 #include <plat/udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
 
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 
 #include <plat/common-smdk.h>
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ffa29dd..f7a108b 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -29,6 +29,7 @@
 #include <linux/dm9000.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -44,7 +45,6 @@
 #include <plat/regs-serial.h>
 #include <plat/iic.h>
 #include <plat/fb.h>
-#include <plat/regs-fb-v4.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..0f882f9 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -46,6 +46,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 
@@ -57,7 +58,6 @@
 #include <mach/regs-gpio-memport.h>
 
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 6890881..8ad0bfc 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -26,6 +26,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 
@@ -41,7 +42,6 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 5539a25..96ebcc5 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,9 +41,9 @@
 #include <plat/nand.h>
 #include <plat/regs-serial.h>
 #include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cad2e05..48599bc 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -43,7 +44,6 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 326b216..76d3ffb 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,9 +42,9 @@
 #include <plat/nand.h>
 #include <plat/regs-serial.h>
 #include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index d6266d8..96d6da2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 0957d2a..7d1167b 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..d1378d7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -43,6 +43,7 @@
 #endif
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -72,7 +73,6 @@
 #include <plat/ts.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 92fefad..5d0b36e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -52,7 +53,6 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e2335ec..7522fb9 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -52,7 +53,6 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0c3ae38..c3dcafa 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -33,6 +33,7 @@
 #include <mach/regs-gpio.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -51,7 +52,6 @@
 #include <plat/ts.h>
 #include <plat/audio.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 78028df..ee9fa5c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -28,6 +28,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 
@@ -39,7 +40,6 @@
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
 #include <plat/s5p-time.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 822a559..c552581 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -35,6 +35,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 
@@ -49,7 +50,6 @@
 #include <plat/clock.h>
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/camport.h>
 
 #include <media/v4l2-mediabus.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 918b23d..9bfbedf 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -28,6 +28,7 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -46,7 +47,6 @@
 #include <plat/fb.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
 
-- 
1.7.0.4



From l.krishna at samsung.com  Tue Aug  7 05:37:58 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:58 +0530
Subject: [PATCH V3 4/5] driver: Include the modified FIMD header file
In-Reply-To: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
References: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344332279-16736-5-git-send-email-l.krishna@samsung.com>

The fimd register headers have been moved to include/video/
hence, modifying the driver files accordingly.

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c |    2 +-
 drivers/video/s3c-fb.c                   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index a68d2b3..24c0bd4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -19,8 +19,8 @@
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
 
+#include <video/samsung_fimd.h>
 #include <drm/exynos_drm.h>
-#include <plat/regs-fb-v4.h>
 
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fbdev.h"
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 69bf9d0..901729e 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -25,8 +25,8 @@
 #include <linux/interrupt.h>
 #include <linux/pm_runtime.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 
 /* This driver will export a number of framebuffer interfaces depending
-- 
1.7.0.4



From l.krishna at samsung.com  Tue Aug  7 05:37:59 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 15:07:59 +0530
Subject: [PATCH V3 5/5] arm: samsung: delete frame buffer header files from
 platform
In-Reply-To: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
References: <1344332279-16736-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344332279-16736-6-git-send-email-l.krishna@samsung.com>

The FIMD register headers are moved to include/video/
hence, deleting these files from platform side

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h |  159 ---------
 arch/arm/plat-samsung/include/plat/regs-fb.h    |  403 -----------------------
 2 files changed, 0 insertions(+), 562 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben at simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards and specifically the S3C64XX series
- * S3C6400 and S3C6410.
- *
- * The file contains the cpu specific items which change between whichever
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* include the core definitions here, in case we really do need to
- * override them at a later date.
-*/
-
-#include <plat/regs-fb.h>
-
-#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN	(1 << 15)
-
-/* Video timing controls */
-#define VIDTCON0				(0x10)
-#define VIDTCON1				(0x14)
-#define VIDTCON2				(0x18)
-
-/* Window position controls */
-
-#define WINCON(_win)				(0x20 + ((_win) * 4))
-
-/* OSD1 and OSD4 do not have register D */
-
-#define VIDOSD_BASE				(0x40)
-
-#define VIDINTCON0				(0x130)
-
-/* WINCONx */
-
-#define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT			(26)
-#define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
-
-#define WINCONx_ENLOCAL				(1 << 22)
-#define WINCONx_BUFSTATUS			(1 << 21)
-#define WINCONx_BUFSEL				(1 << 20)
-#define WINCONx_BUFAUTOEN			(1 << 19)
-#define WINCONx_YCbCr				(1 << 13)
-
-#define WINCON1_LOCALSEL_CAMIF			(1 << 23)
-
-#define WINCON2_LOCALSEL_CAMIF			(1 << 23)
-#define WINCON2_BLD_PIX				(1 << 6)
-
-#define WINCON2_ALPHA_SEL			(1 << 1)
-#define WINCON2_BPPMODE_MASK			(0xf << 2)
-#define WINCON2_BPPMODE_SHIFT			(2)
-#define WINCON2_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON2_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON2_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232		(0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555		(0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555		(0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665		(0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666		(0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888		(0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887		(0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888		(0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888		(0xd << 2)
-
-#define WINCON3_BLD_PIX				(1 << 6)
-
-#define WINCON3_ALPHA_SEL			(1 << 1)
-#define WINCON3_BPPMODE_MASK			(0xf << 2)
-#define WINCON3_BPPMODE_SHIFT			(2)
-#define WINCON3_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON3_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON3_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555		(0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555		(0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665		(0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666		(0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888		(0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887		(0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888		(0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888		(0xd << 2)
-
-#define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)
-
-#define DITHMODE				(0x170)
-#define WINxMAP(_win)				(0x180 + ((_win) * 4))
-
-
-#define DITHMODE_R_POS_MASK			(0x3 << 5)
-#define DITHMODE_R_POS_SHIFT			(5)
-#define DITHMODE_R_POS_8BIT			(0x0 << 5)
-#define DITHMODE_R_POS_6BIT			(0x1 << 5)
-#define DITHMODE_R_POS_5BIT			(0x2 << 5)
-
-#define DITHMODE_G_POS_MASK			(0x3 << 3)
-#define DITHMODE_G_POS_SHIFT			(3)
-#define DITHMODE_G_POS_8BIT			(0x0 << 3)
-#define DITHMODE_G_POS_6BIT			(0x1 << 3)
-#define DITHMODE_G_POS_5BIT			(0x2 << 3)
-
-#define DITHMODE_B_POS_MASK			(0x3 << 1)
-#define DITHMODE_B_POS_SHIFT			(1)
-#define DITHMODE_B_POS_8BIT			(0x0 << 1)
-#define DITHMODE_B_POS_6BIT			(0x1 << 1)
-#define DITHMODE_B_POS_5BIT			(0x2 << 1)
-
-#define DITHMODE_DITH_EN			(1 << 0)
-
-#define WPALCON					(0x1A0)
-
-/* Palette control */
-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
-#define WPALCON_W4PAL_16BPP_A555		(1 << 8)
-#define WPALCON_W3PAL_16BPP_A555		(1 << 7)
-#define WPALCON_W2PAL_16BPP_A555		(1 << 6)
-
-
-/* Notes on per-window bpp settings
- *
- * Value	Win0	 Win1	  Win2	   Win3	    Win 4
- * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
- * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
- * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
- * 0011		8(P)	 8(P)     -none-   -none-   -none-
- * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
- * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
- * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
- * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
- * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
- * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
- * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
- * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
- * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
- * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
- * 1110		-none-	 -none-	  -none-   -none-    -none-
- * 1111		-none-	 -none-   -none-   -none-    -none-
-*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
deleted file mode 100644
index 9a78012..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben at simtec.co.uk>
- *
- * S3C Platform - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
- * S3C64XX series such as the S3C6400 and S3C6410.
- *
- * The file does not contain the cpu specific items which are based on
- * whichever architecture is selected, it only contains the core of the
- * register set. See <mach/regs-fb.h> to get the specifics.
- *
- * Note, we changed to using regs-fb.h as it avoids any clashes with
- * the original regs-lcd.h so out of the way of regs-lcd.h as well as
- * indicating the newer block is much more than just an LCD interface.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Please do not include this file directly, use <mach/regs-fb.h> to
- * ensure all the localised SoC support is included as necessary.
-*/
-
-/* VIDCON0 */
-
-#define VIDCON0					(0x00)
-#define VIDCON0_INTERLACE			(1 << 29)
-#define VIDCON0_VIDOUT_MASK			(0x3 << 26)
-#define VIDCON0_VIDOUT_SHIFT			(26)
-#define VIDCON0_VIDOUT_RGB			(0x0 << 26)
-#define VIDCON0_VIDOUT_TV			(0x1 << 26)
-#define VIDCON0_VIDOUT_I80_LDI0			(0x2 << 26)
-#define VIDCON0_VIDOUT_I80_LDI1			(0x3 << 26)
-
-#define VIDCON0_L1_DATA_MASK			(0x7 << 23)
-#define VIDCON0_L1_DATA_SHIFT			(23)
-#define VIDCON0_L1_DATA_16BPP			(0x0 << 23)
-#define VIDCON0_L1_DATA_18BPP16			(0x1 << 23)
-#define VIDCON0_L1_DATA_18BPP9			(0x2 << 23)
-#define VIDCON0_L1_DATA_24BPP			(0x3 << 23)
-#define VIDCON0_L1_DATA_18BPP			(0x4 << 23)
-#define VIDCON0_L1_DATA_16BPP8			(0x5 << 23)
-
-#define VIDCON0_L0_DATA_MASK			(0x7 << 20)
-#define VIDCON0_L0_DATA_SHIFT			(20)
-#define VIDCON0_L0_DATA_16BPP			(0x0 << 20)
-#define VIDCON0_L0_DATA_18BPP16			(0x1 << 20)
-#define VIDCON0_L0_DATA_18BPP9			(0x2 << 20)
-#define VIDCON0_L0_DATA_24BPP			(0x3 << 20)
-#define VIDCON0_L0_DATA_18BPP			(0x4 << 20)
-#define VIDCON0_L0_DATA_16BPP8			(0x5 << 20)
-
-#define VIDCON0_PNRMODE_MASK			(0x3 << 17)
-#define VIDCON0_PNRMODE_SHIFT			(17)
-#define VIDCON0_PNRMODE_RGB			(0x0 << 17)
-#define VIDCON0_PNRMODE_BGR			(0x1 << 17)
-#define VIDCON0_PNRMODE_SERIAL_RGB		(0x2 << 17)
-#define VIDCON0_PNRMODE_SERIAL_BGR		(0x3 << 17)
-
-#define VIDCON0_CLKVALUP			(1 << 16)
-#define VIDCON0_CLKVAL_F_MASK			(0xff << 6)
-#define VIDCON0_CLKVAL_F_SHIFT			(6)
-#define VIDCON0_CLKVAL_F_LIMIT			(0xff)
-#define VIDCON0_CLKVAL_F(_x)			((_x) << 6)
-#define VIDCON0_VLCKFREE			(1 << 5)
-#define VIDCON0_CLKDIR				(1 << 4)
-
-#define VIDCON0_CLKSEL_MASK			(0x3 << 2)
-#define VIDCON0_CLKSEL_SHIFT			(2)
-#define VIDCON0_CLKSEL_HCLK			(0x0 << 2)
-#define VIDCON0_CLKSEL_LCD			(0x1 << 2)
-#define VIDCON0_CLKSEL_27M			(0x3 << 2)
-
-#define VIDCON0_ENVID				(1 << 1)
-#define VIDCON0_ENVID_F				(1 << 0)
-
-#define VIDCON1					(0x04)
-#define VIDCON1_LINECNT_MASK			(0x7ff << 16)
-#define VIDCON1_LINECNT_SHIFT			(16)
-#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 16) & 0x7ff)
-#define VIDCON1_VSTATUS_MASK			(0x3 << 13)
-#define VIDCON1_VSTATUS_SHIFT			(13)
-#define VIDCON1_VSTATUS_VSYNC			(0x0 << 13)
-#define VIDCON1_VSTATUS_BACKPORCH		(0x1 << 13)
-#define VIDCON1_VSTATUS_ACTIVE			(0x2 << 13)
-#define VIDCON1_VSTATUS_FRONTPORCH		(0x0 << 13)
-#define VIDCON1_VCLK_MASK			(0x3 << 9)
-#define VIDCON1_VCLK_HOLD			(0x0 << 9)
-#define VIDCON1_VCLK_RUN			(0x1 << 9)
-
-#define VIDCON1_INV_VCLK			(1 << 7)
-#define VIDCON1_INV_HSYNC			(1 << 6)
-#define VIDCON1_INV_VSYNC			(1 << 5)
-#define VIDCON1_INV_VDEN			(1 << 4)
-
-/* VIDCON2 */
-
-#define VIDCON2					(0x08)
-#define VIDCON2_EN601				(1 << 23)
-#define VIDCON2_TVFMTSEL_SW			(1 << 14)
-
-#define VIDCON2_TVFMTSEL1_MASK			(0x3 << 12)
-#define VIDCON2_TVFMTSEL1_SHIFT			(12)
-#define VIDCON2_TVFMTSEL1_RGB			(0x0 << 12)
-#define VIDCON2_TVFMTSEL1_YUV422		(0x1 << 12)
-#define VIDCON2_TVFMTSEL1_YUV444		(0x2 << 12)
-
-#define VIDCON2_ORGYCbCr			(1 << 8)
-#define VIDCON2_YUVORDCrCb			(1 << 7)
-
-/* PRTCON (S3C6410, S5PC100)
- * Might not be present in the S3C6410 documentation,
- * but tests prove it's there almost for sure; shouldn't hurt in any case.
- */
-#define PRTCON					(0x0c)
-#define PRTCON_PROTECT				(1 << 11)
-
-/* VIDTCON0 */
-
-#define VIDTCON0_VBPDE_MASK			(0xff << 24)
-#define VIDTCON0_VBPDE_SHIFT			(24)
-#define VIDTCON0_VBPDE_LIMIT			(0xff)
-#define VIDTCON0_VBPDE(_x)			((_x) << 24)
-
-#define VIDTCON0_VBPD_MASK			(0xff << 16)
-#define VIDTCON0_VBPD_SHIFT			(16)
-#define VIDTCON0_VBPD_LIMIT			(0xff)
-#define VIDTCON0_VBPD(_x)			((_x) << 16)
-
-#define VIDTCON0_VFPD_MASK			(0xff << 8)
-#define VIDTCON0_VFPD_SHIFT			(8)
-#define VIDTCON0_VFPD_LIMIT			(0xff)
-#define VIDTCON0_VFPD(_x)			((_x) << 8)
-
-#define VIDTCON0_VSPW_MASK			(0xff << 0)
-#define VIDTCON0_VSPW_SHIFT			(0)
-#define VIDTCON0_VSPW_LIMIT			(0xff)
-#define VIDTCON0_VSPW(_x)			((_x) << 0)
-
-/* VIDTCON1 */
-
-#define VIDTCON1_VFPDE_MASK			(0xff << 24)
-#define VIDTCON1_VFPDE_SHIFT			(24)
-#define VIDTCON1_VFPDE_LIMIT			(0xff)
-#define VIDTCON1_VFPDE(_x)			((_x) << 24)
-
-#define VIDTCON1_HBPD_MASK			(0xff << 16)
-#define VIDTCON1_HBPD_SHIFT			(16)
-#define VIDTCON1_HBPD_LIMIT			(0xff)
-#define VIDTCON1_HBPD(_x)			((_x) << 16)
-
-#define VIDTCON1_HFPD_MASK			(0xff << 8)
-#define VIDTCON1_HFPD_SHIFT			(8)
-#define VIDTCON1_HFPD_LIMIT			(0xff)
-#define VIDTCON1_HFPD(_x)			((_x) << 8)
-
-#define VIDTCON1_HSPW_MASK			(0xff << 0)
-#define VIDTCON1_HSPW_SHIFT			(0)
-#define VIDTCON1_HSPW_LIMIT			(0xff)
-#define VIDTCON1_HSPW(_x)			((_x) << 0)
-
-#define VIDTCON2				(0x18)
-#define VIDTCON2_LINEVAL_E(_x)			((((_x) & 0x800) >> 11) << 23)
-#define VIDTCON2_LINEVAL_MASK			(0x7ff << 11)
-#define VIDTCON2_LINEVAL_SHIFT			(11)
-#define VIDTCON2_LINEVAL_LIMIT			(0x7ff)
-#define VIDTCON2_LINEVAL(_x)			(((_x) & 0x7ff) << 11)
-
-#define VIDTCON2_HOZVAL_E(_x)			((((_x) & 0x800) >> 11) << 22)
-#define VIDTCON2_HOZVAL_MASK			(0x7ff << 0)
-#define VIDTCON2_HOZVAL_SHIFT			(0)
-#define VIDTCON2_HOZVAL_LIMIT			(0x7ff)
-#define VIDTCON2_HOZVAL(_x)			(((_x) & 0x7ff) << 0)
-
-/* WINCONx */
-
-
-#define WINCONx_BITSWP				(1 << 18)
-#define WINCONx_BYTSWP				(1 << 17)
-#define WINCONx_HAWSWP				(1 << 16)
-#define WINCONx_WSWP				(1 << 15)
-#define WINCONx_BURSTLEN_MASK			(0x3 << 9)
-#define WINCONx_BURSTLEN_SHIFT			(9)
-#define WINCONx_BURSTLEN_16WORD			(0x0 << 9)
-#define WINCONx_BURSTLEN_8WORD			(0x1 << 9)
-#define WINCONx_BURSTLEN_4WORD			(0x2 << 9)
-
-#define WINCONx_ENWIN				(1 << 0)
-#define WINCON0_BPPMODE_MASK			(0xf << 2)
-#define WINCON0_BPPMODE_SHIFT			(2)
-#define WINCON0_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON0_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON0_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON0_BPPMODE_8BPP_PALETTE		(0x3 << 2)
-#define WINCON0_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON0_BPPMODE_16BPP_1555		(0x7 << 2)
-#define WINCON0_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON0_BPPMODE_24BPP_888		(0xb << 2)
-
-#define WINCON1_BLD_PIX				(1 << 6)
-
-#define WINCON1_ALPHA_SEL			(1 << 1)
-#define WINCON1_BPPMODE_MASK			(0xf << 2)
-#define WINCON1_BPPMODE_SHIFT			(2)
-#define WINCON1_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON1_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON1_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON1_BPPMODE_8BPP_PALETTE		(0x3 << 2)
-#define WINCON1_BPPMODE_8BPP_1232		(0x4 << 2)
-#define WINCON1_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON1_BPPMODE_16BPP_A1555		(0x6 << 2)
-#define WINCON1_BPPMODE_16BPP_I1555		(0x7 << 2)
-#define WINCON1_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON1_BPPMODE_18BPP_A1665		(0x9 << 2)
-#define WINCON1_BPPMODE_19BPP_A1666		(0xa << 2)
-#define WINCON1_BPPMODE_24BPP_888		(0xb << 2)
-#define WINCON1_BPPMODE_24BPP_A1887		(0xc << 2)
-#define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
-#define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
-
-/* S5PV210 */
-#define SHADOWCON				(0x34)
-#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
-/* DMA channels (all windows) */
-#define SHADOWCON_CHx_ENABLE(_win)		(1 << (_win))
-/* Local input channels (windows 0-2) */
-#define SHADOWCON_CHx_LOCAL_ENABLE(_win)	(1 << (5 + (_win)))
-
-#define VIDOSDxA_TOPLEFT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
-#define VIDOSDxA_TOPLEFT_X_SHIFT		(11)
-#define VIDOSDxA_TOPLEFT_X_LIMIT		(0x7ff)
-#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x7ff) << 11)
-
-#define VIDOSDxA_TOPLEFT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxA_TOPLEFT_Y_MASK			(0x7ff << 0)
-#define VIDOSDxA_TOPLEFT_Y_SHIFT		(0)
-#define VIDOSDxA_TOPLEFT_Y_LIMIT		(0x7ff)
-#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x7ff) << 0)
-
-#define VIDOSDxB_BOTRIGHT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxB_BOTRIGHT_X_MASK		(0x7ff << 11)
-#define VIDOSDxB_BOTRIGHT_X_SHIFT		(11)
-#define VIDOSDxB_BOTRIGHT_X_LIMIT		(0x7ff)
-#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x7ff) << 11)
-
-#define VIDOSDxB_BOTRIGHT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x7ff << 0)
-#define VIDOSDxB_BOTRIGHT_Y_SHIFT		(0)
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT		(0x7ff)
-#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x7ff) << 0)
-
-/* For VIDOSD[1..4]C */
-#define VIDISD14C_ALPHA0_R(_x)			((_x) << 20)
-#define VIDISD14C_ALPHA0_G_MASK			(0xf << 16)
-#define VIDISD14C_ALPHA0_G_SHIFT		(16)
-#define VIDISD14C_ALPHA0_G_LIMIT		(0xf)
-#define VIDISD14C_ALPHA0_G(_x)			((_x) << 16)
-#define VIDISD14C_ALPHA0_B_MASK			(0xf << 12)
-#define VIDISD14C_ALPHA0_B_SHIFT		(12)
-#define VIDISD14C_ALPHA0_B_LIMIT		(0xf)
-#define VIDISD14C_ALPHA0_B(_x)			((_x) << 12)
-#define VIDISD14C_ALPHA1_R_MASK			(0xf << 8)
-#define VIDISD14C_ALPHA1_R_SHIFT		(8)
-#define VIDISD14C_ALPHA1_R_LIMIT		(0xf)
-#define VIDISD14C_ALPHA1_R(_x)			((_x) << 8)
-#define VIDISD14C_ALPHA1_G_MASK			(0xf << 4)
-#define VIDISD14C_ALPHA1_G_SHIFT		(4)
-#define VIDISD14C_ALPHA1_G_LIMIT		(0xf)
-#define VIDISD14C_ALPHA1_G(_x)			((_x) << 4)
-#define VIDISD14C_ALPHA1_B_MASK			(0xf << 0)
-#define VIDISD14C_ALPHA1_B_SHIFT		(0)
-#define VIDISD14C_ALPHA1_B_LIMIT		(0xf)
-#define VIDISD14C_ALPHA1_B(_x)			((_x) << 0)
-
-/* Video buffer addresses */
-#define VIDW_BUF_START(_buff)			(0xA0 + ((_buff) * 8))
-#define VIDW_BUF_START1(_buff)			(0xA4 + ((_buff) * 8))
-#define VIDW_BUF_END(_buff)			(0xD0 + ((_buff) * 8))
-#define VIDW_BUF_END1(_buff)			(0xD4 + ((_buff) * 8))
-#define VIDW_BUF_SIZE(_buff)			(0x100 + ((_buff) * 4))
-
-#define VIDW_BUF_SIZE_OFFSET_E(_x)		((((_x) & 0x2000) >> 13) << 27)
-#define VIDW_BUF_SIZE_OFFSET_MASK		(0x1fff << 13)
-#define VIDW_BUF_SIZE_OFFSET_SHIFT		(13)
-#define VIDW_BUF_SIZE_OFFSET_LIMIT		(0x1fff)
-#define VIDW_BUF_SIZE_OFFSET(_x)		(((_x) & 0x1fff) << 13)
-
-#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)		((((_x) & 0x2000) >> 13) << 26)
-#define VIDW_BUF_SIZE_PAGEWIDTH_MASK		(0x1fff << 0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT		(0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT		(0x1fff)
-#define VIDW_BUF_SIZE_PAGEWIDTH(_x)		(((_x) & 0x1fff) << 0)
-
-/* Interrupt controls and status */
-
-#define VIDINTCON0_FIFOINTERVAL_MASK		(0x3f << 20)
-#define VIDINTCON0_FIFOINTERVAL_SHIFT		(20)
-#define VIDINTCON0_FIFOINTERVAL_LIMIT		(0x3f)
-#define VIDINTCON0_FIFOINTERVAL(_x)		((_x) << 20)
-
-#define VIDINTCON0_INT_SYSMAINCON		(1 << 19)
-#define VIDINTCON0_INT_SYSSUBCON		(1 << 18)
-#define VIDINTCON0_INT_I80IFDONE		(1 << 17)
-
-#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
-#define VIDINTCON0_FRAMESEL0_SHIFT		(15)
-#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
-#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
-#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
-#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
-
-#define VIDINTCON0_FRAMESEL1			(1 << 13)
-#define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
-#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
-#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
-#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
-#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
-
-#define VIDINTCON0_INT_FRAME			(1 << 12)
-#define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
-#define VIDINTCON0_FIFIOSEL_SHIFT		(5)
-#define VIDINTCON0_FIFIOSEL_WINDOW0		(0x1 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW1		(0x2 << 5)
-
-#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 2)
-#define VIDINTCON0_FIFOLEVEL_SHIFT		(2)
-#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x0 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x1 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO75PC		(0x2 << 2)
-#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x3 << 2)
-#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 2)
-
-#define VIDINTCON0_INT_FIFO_MASK		(0x3 << 0)
-#define VIDINTCON0_INT_FIFO_SHIFT		(0)
-#define VIDINTCON0_INT_ENABLE			(1 << 0)
-
-#define VIDINTCON1				(0x134)
-#define VIDINTCON1_INT_I180			(1 << 2)
-#define VIDINTCON1_INT_FRAME			(1 << 1)
-#define VIDINTCON1_INT_FIFO			(1 << 0)
-
-/* Window colour-key control registers */
-#define WKEYCON					(0x140)	/* 6410,V210 */
-
-#define WKEYCON0				(0x00)
-#define WKEYCON1				(0x04)
-
-#define WxKEYCON0_KEYBL_EN			(1 << 26)
-#define WxKEYCON0_KEYEN_F			(1 << 25)
-#define WxKEYCON0_DIRCON			(1 << 24)
-#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
-#define WxKEYCON0_COMPKEY_SHIFT			(0)
-#define WxKEYCON0_COMPKEY_LIMIT			(0xffffff)
-#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
-#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
-#define WxKEYCON1_COLVAL_SHIFT			(0)
-#define WxKEYCON1_COLVAL_LIMIT			(0xffffff)
-#define WxKEYCON1_COLVAL(_x)			((_x) << 0)
-
-
-/* Window blanking (MAP) */
-
-#define WINxMAP_MAP				(1 << 24)
-#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
-#define WINxMAP_MAP_COLOUR_SHIFT		(0)
-#define WINxMAP_MAP_COLOUR_LIMIT		(0xffffff)
-#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
-
-#define WPALCON_PAL_UPDATE			(1 << 9)
-#define WPALCON_W1PAL_MASK			(0x7 << 3)
-#define WPALCON_W1PAL_SHIFT			(3)
-#define WPALCON_W1PAL_25BPP_A888		(0x0 << 3)
-#define WPALCON_W1PAL_24BPP			(0x1 << 3)
-#define WPALCON_W1PAL_19BPP_A666		(0x2 << 3)
-#define WPALCON_W1PAL_18BPP_A665		(0x3 << 3)
-#define WPALCON_W1PAL_18BPP			(0x4 << 3)
-#define WPALCON_W1PAL_16BPP_A555		(0x5 << 3)
-#define WPALCON_W1PAL_16BPP_565			(0x6 << 3)
-
-#define WPALCON_W0PAL_MASK			(0x7 << 0)
-#define WPALCON_W0PAL_SHIFT			(0)
-#define WPALCON_W0PAL_25BPP_A888		(0x0 << 0)
-#define WPALCON_W0PAL_24BPP			(0x1 << 0)
-#define WPALCON_W0PAL_19BPP_A666		(0x2 << 0)
-#define WPALCON_W0PAL_18BPP_A665		(0x3 << 0)
-#define WPALCON_W0PAL_18BPP			(0x4 << 0)
-#define WPALCON_W0PAL_16BPP_A555		(0x5 << 0)
-#define WPALCON_W0PAL_16BPP_565			(0x6 << 0)
-
-/* Blending equation control */
-#define BLENDCON				(0x260)
-#define BLENDCON_NEW_MASK			(1 << 0)
-#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
-#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
-
-- 
1.7.0.4



From arnd at arndb.de  Tue Aug  7 05:23:15 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 09:23:15 +0000
Subject: [GIT PULL] i.MX fixes for 3.6-rc
In-Reply-To: <20120807071752.GG1451@pengutronix.de>
References: <20120807071752.GG1451@pengutronix.de>
Message-ID: <201208070923.15869.arnd@arndb.de>

On Tuesday 07 August 2012, Sascha Hauer wrote:
> 
> Hi Arnd, Olof,
> 
> Please pull the following i.MX fixes for 3.6-rc
> 
> Sascha
> 
> The following changes since commit 1a9b4993b70fb1884716902774dc9025b457760d:
> 
>   Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus (2012-08-01 16:47:15 -0700)
> 

Pulled, thanks!

	Arnd


From linus.walleij at linaro.org  Tue Aug  7 05:47:38 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 11:47:38 +0200
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <20120806153503.GH10524@gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120806153503.GH10524@gmail.com>
Message-ID: <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>

On Mon, Aug 6, 2012 at 5:35 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Looks like I introduced a merge error on the last patch. Trying again:

>  .../mali/mali400ko/driver/src/devicedrv/mali/arch  |    1 +
(...)
> diff --git a/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
> new file mode 120000
> index 0000000..427334b
> --- /dev/null
> +++ b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
> @@ -0,0 +1 @@
> +/home/ljkenny/projects/linaro/snowball/snowball/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch-ux500
> \ No newline at end of file

NACK, what is this stuff? It's even out-of-tree code.

Please be careful with git add -A, I prefer to use git add <pathspec>
I suspect that may be why this happened...

Please fix it up and send a v3.

Yours,
Linus Walleij


From kgene.kim at samsung.com  Tue Aug  7 06:00:04 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 07 Aug 2012 19:00:04 +0900
Subject: [PATCH v2 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
Message-ID: <098c01cd7483$6a93eeb0$3fbbcc10$%kim@samsung.com>

Praveen Paneri wrote:
> 
> Changes from v1:
> Rebased patches to latest usb-next branch
> Changed the name 'sec_usbphy' to 'samsung_usbphy'
> 
Yes, looks better. But I'm not sure Felipe or Greg would prefer to use '_'
not '-'...you used samsung-usbphy as a name in your patch.

> This patch set introduces a phy driver for samsung SoCs. It uses the
> existing
> transceiver infrastructure to provide phy control functions. Use of this
> driver
> can be extended for usb host phy as well. Over the period of time all the
> phy
> related code for most of the samsung SoCs can be integrated here.
> Removing the existing phy code from mach-s3c64xx but not from other
> machine

Why? Is there any reason? After quick looking at your patches, seems this
can remove all of setup-usb-phy in arch/arm/ for Samsung stuff. In addition,
the isolation hook function also can be put in this by using platform_data
or dt parsing.

> code.This driver is tested with smdk6410 and Exynos4210(with DT).
> 
I and my colleague, Yulgon will comment on this series soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> Praveen Paneri (5):
>   usb: phy: samsung: Introducing usb phy driver for hsotg
>   usb: s3c-hsotg: Adding phy driver support
>   ARM: S3C64XX: Removing old phy setup code
>   ARM: S3C64XX: Enabling samsung_usbphy driver
>   ARM: Exynos4210: Enabling samsung_usbphy driver
> 
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
>  arch/arm/mach-exynos/include/mach/map.h            |    1 +
>  arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
>  arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
>  arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
>  arch/arm/mach-s3c64xx/mach-crag6410.c              |    5 +-
>  arch/arm/mach-s3c64xx/mach-smartq.c                |    6 +-
>  arch/arm/mach-s3c64xx/mach-smdk6410.c              |    5 +-
>  arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
>  arch/arm/plat-samsung/devs.c                       |   32 ++
>  arch/arm/plat-samsung/include/plat/devs.h          |    1 +
>  arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>  drivers/usb/gadget/s3c-hsotg.c                     |   38 ++-
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/samsung_usbphy.c                   |  355
++++++++++++++++++++
>  drivers/usb/phy/samsung_usbphy.h                   |   48 +++
>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>  19 files changed, 534 insertions(+), 88 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-
> usbphy.txt
>  create mode 100644 drivers/usb/phy/samsung_usbphy.c
>  create mode 100644 drivers/usb/phy/samsung_usbphy.h



From paul at pwsan.com  Tue Aug  7 06:05:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 7 Aug 2012 04:05:33 -0600 (MDT)
Subject: DSS and USBHOST powerdomains not entering low-power states on
 37xx EVM
In-Reply-To: <877gtb6723.fsf@ti.com>
References: <alpine.DEB.2.00.1208031355450.28888@utopia.booyaka.com>
 <877gtb6723.fsf@ti.com>
Message-ID: <alpine.DEB.2.00.1208070401530.21945@utopia.booyaka.com>

Hi Kevin,

On Mon, 6 Aug 2012, Kevin Hilman wrote:

> Is this only happening on this 37xx platform?    Just curious, because
> it seems to be a problem on any OMAP3xxx SoC.

So far I've only run the baseline tests on 37xx, so wanted to state only 
what was observed here.

> ...it must be the usecounts that are not being updated.  This seems to
> be a side effect of the pre/post transition optimization I did.  A quick
> hack seems to indicate that that's indeed the case[1].  By default,
> omap_sram_idle() is now only calling the pre/post callbacks for MPU,
> NEON, PER, and CORE, and only if those domains are transitioning, so any
> other domains not explicitly managed by the idle path have lots their
> usecounting.  Oops.
> 
> I guess Tero's usecounting series should fix this up.

Thanks for the diagnosis.  Care to put together a patch to fix this for 
v3.6-rc?  The earliest point that the usecounting improvements could get 
in would be v3.7.  This problem is breaking the PM regression tests here 
that parse the powerdomain state count fields.


- Paul


From p.paneri at samsung.com  Tue Aug  7 06:05:43 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 7 Aug 2012 15:35:43 +0530
Subject: [PATCH v2 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <201208071011.23558.heiko@sntech.de>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
 <1344324524-2286-2-git-send-email-p.paneri@samsung.com>
 <201208071011.23558.heiko@sntech.de>
Message-ID: <CAD6zSYMnBAQuoH3N2HtSKfnbhRg6c3Ac27kf=fRQY++_+12d5A@mail.gmail.com>

On Tue, Aug 7, 2012 at 1:41 PM, Heiko St?bner <heiko at sntech.de> wrote:
> Am Dienstag, 7. August 2012, 09:28:40 schrieb Praveen Paneri:
>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/samsung_usbphy.c                   |  355
>> ++++++++++++++++++++ drivers/usb/phy/samsung_usbphy.h                   |
>>  48 +++
>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>  6 files changed, 426 insertions(+), 0 deletions(-)
>>  create mode 100644
>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt create mode
>> 100644 drivers/usb/phy/samsung_usbphy.c
>>  create mode 100644 drivers/usb/phy/samsung_usbphy.h
>>
>
> [...]
>
>> diff --git a/include/linux/platform_data/s3c-hsotg.h
>> b/include/linux/platform_data/s3c-hsotg.h index 8b79e09..25ed31e 100644
>> --- a/include/linux/platform_data/s3c-hsotg.h
>> +++ b/include/linux/platform_data/s3c-hsotg.h
>> @@ -35,6 +35,11 @@ struct s3c_hsotg_plat {
>>       int (*phy_exit)(struct platform_device *pdev, int type);
>>  };
>>
>> +struct s3c_usbphy_plat {
>> +     void (*pmu_isolation)(int on);
>> +};
>> +
>>  extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
>> +extern void s3c_usbphy_set_platdata(struct s3c_usbphy_plat *pd);
>>
>>  #endif /* __LINUX_USB_S3C_HSOTG_H */
>
> hmm, I'm not completely sure about this being in the s3c-hsotg header, as on
> s3c2443/2416/2450 it's the s3c-hsudc that will be (hopefully) using the phy in
> the future.
Okay then I will make a new header file for this. Not only hsudc, we
intent to use it for usb host phy as well so it's a valid point.

Praveen
>
>
> Heiko
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From kgene.kim at samsung.com  Tue Aug  7 06:06:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 07 Aug 2012 19:06:37 +0900
Subject: [PATCH V2 5/6] x86: add CONFIG_ARM_AMBA, selected by STA2X11
In-Reply-To: <CACRpkdZLGhgpUJy_3QGYvGRqyxMkkPPSdyP==h5YurWqKnctBw@mail.gmail.com>
References: <2b797c83-6a3c-4051-841a-a4cfa9d1cae1@email.android.com>
 <20120701104401.GA4352@mail.gnudd.com> <20120703130042.GA10007@mail.gnudd.com>
 <201207031319.40884.arnd@arndb.de>
 <20120703193403.GA26355@n2100.arm.linux.org.uk>
 <CACRpkdZLGhgpUJy_3QGYvGRqyxMkkPPSdyP==h5YurWqKnctBw@mail.gmail.com>
Message-ID: <098e01cd7484$553871c0$ffa95540$%kim@samsung.com>

Linus Walleij wrote:
> 

[...]

> The major reason why that file is there is that there is *another*
> PL080 driver in arch/arm/mach-s3c64xx/dma.c which I repeatedly
> asked the Samsung people to replace with the
> drivers/dma/amba-pl08x.c driver. :-(
> 
> When I worked on the PL08x driver in drivers/dma I reused
> this header to avoid code duplication.
> 
> Now that thing is stranding in the way. Alim, Kukjin, what's happening?
> 
Afaik, Alim was working on that but I'm not sure how long he needs more?

Alim, please share the progress of the pl080 work?

> I feel tempted to update Alim's patch myself and push it on you
> soon...

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From p.paneri at samsung.com  Tue Aug  7 06:09:45 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 7 Aug 2012 15:39:45 +0530
Subject: [PATCH v2 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <CAK9yfHyJtM8p1wdS1B4LZPNL8SstP-tsgjKPyLtG4fQtBZyOUg@mail.gmail.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
 <1344324524-2286-3-git-send-email-p.paneri@samsung.com>
 <CAK9yfHyJtM8p1wdS1B4LZPNL8SstP-tsgjKPyLtG4fQtBZyOUg@mail.gmail.com>
Message-ID: <CAD6zSYPoSxVSrkgr9RMV03DwVvg70oxdTV_5SeUifMFtQA09cQ@mail.gmail.com>

Thanks Sachin! Will incorporate.

On Tue, Aug 7, 2012 at 1:33 PM, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> Hi Praveen,
>
> Some minor comments:
>
> On 7 August 2012 12:58, Praveen Paneri <p.paneri at samsung.com> wrote:
>> Adding the transceiver to hsotg driver. Keeping the platform data
>> for continuing the smooth operation for boards which still uses it
>>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> ---
>>  drivers/usb/gadget/s3c-hsotg.c |   38 ++++++++++++++++++++++++++++----------
>>  1 files changed, 28 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
>> index b13e0bb..f4ba9a3 100644
>> --- a/drivers/usb/gadget/s3c-hsotg.c
>> +++ b/drivers/usb/gadget/s3c-hsotg.c
>> @@ -32,6 +32,7 @@
>>
>>  #include <linux/usb/ch9.h>
>>  #include <linux/usb/gadget.h>
>> +#include <linux/usb/otg.h>
>>  #include <linux/platform_data/s3c-hsotg.h>
>>
>>  #include <mach/map.h>
>> @@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
>>   * struct s3c_hsotg - driver state.
>>   * @dev: The parent device supplied to the probe function
>>   * @driver: USB gadget driver
>> - * @plat: The platform specific configuration data.
>> + * @phy: The otg phy transeiver structure for phy control.
>
> s/transeiver/transceiver
>
>> + * @plat: The platform specific configuration data. This can be removed once
>> + * all SoCs support usb transceiver.
>>   * @regs: The memory area mapped for accessing registers.
>>   * @irq: The IRQ number we are using
>>   * @supplies: Definition of USB power supplies
>> @@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
>>  struct s3c_hsotg {
>>         struct device            *dev;
>>         struct usb_gadget_driver *driver;
>> +       struct usb_phy          *phy;
>>         struct s3c_hsotg_plat    *plat;
>>
>>         spinlock_t              lock;
>> @@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
>>         struct platform_device *pdev = to_platform_device(hsotg->dev);
>>
>>         dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
>> -       if (hsotg->plat->phy_init)
>> +
>> +       if (hsotg->phy)
>> +               usb_phy_init(hsotg->phy);
>> +       else if (hsotg->plat->phy_init)
>>                 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
>>  }
>>
>> @@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
>>  {
>>         struct platform_device *pdev = to_platform_device(hsotg->dev);
>>
>> -       if (hsotg->plat->phy_exit)
>> +       if (hsotg->phy)
>> +               usb_phy_shutdown(hsotg->phy);
>> +       else if (hsotg->plat->phy_exit)
>>                 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
>>  }
>>
>> @@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
>>  static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
>>  {
>>         struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
>> +       struct usb_phy *phy;
>>         struct device *dev = &pdev->dev;
>>         struct s3c_hsotg_ep *eps;
>>         struct s3c_hsotg *hsotg;
>> @@ -3501,20 +3511,25 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
>>         int ret;
>>         int i;
>>
>> -       plat = pdev->dev.platform_data;
>> -       if (!plat) {
>> -               dev_err(&pdev->dev, "no platform data defined\n");
>> -               return -EINVAL;
>> -       }
>> -
>>         hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
>>         if (!hsotg) {
>>                 dev_err(dev, "cannot get memory\n");
>>                 return -ENOMEM;
>>         }
>>
>> +       phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
>> +       if (!phy) {
>> +               /* Fallback for platform data */
>> +               plat = pdev->dev.platform_data;
>> +               if (!plat) {
>> +                       dev_err(&pdev->dev, "no platform data or transceiver defined\n");
>> +                       return -ENODEV;
>> +               } else
>> +                       hsotg->plat = plat;
>> +       } else
>> +               hsotg->phy = phy;
>
> Braces needed around the above 2 else statements.
> Please refer to: Documentation/CodingStyle
>
>
>> +
>>         hsotg->dev = dev;
>> -       hsotg->plat = plat;
>>
>>         hsotg->clk = clk_get(&pdev->dev, "otg");
>>         if (IS_ERR(hsotg->clk)) {
>> @@ -3689,6 +3704,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
>>         s3c_hsotg_phy_disable(hsotg);
>>         regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
>>
>> +       if (hsotg->phy)
>> +               devm_usb_put_phy(&pdev->dev, hsotg->phy);
>> +
>>         clk_disable_unprepare(hsotg->clk);
>>         clk_put(hsotg->clk);
>>
>> --
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> With best regards,
> Sachin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From paul at pwsan.com  Tue Aug  7 06:34:39 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 07 Aug 2012 04:34:39 -0600
Subject: [PATCH 0/2] ARM: OMAP: smatch warning cleanup and string unwrapping
Message-ID: <20120807103009.8053.69389.stgit@dusk.lan>

This series fixes several bugs uncovered by smatch.  It also unwraps
all of the wrapped strings across the arch/arm/*omap* codebase.  Some
warning messages have been reformatted for concision and consistency.
And some printk(KERN_* ... have been converted to pr_*( ...

This series is intended for v3.7 cleanup.  It has been only lightly
tested; a pull request will be sent after testing is completed.


- Paul

---

warnings_cleanup_3.7
   text	   data	    bss	    dec	    hex	filename
7318144	 764324	5613004	13695472	 d0f9f0	vmlinux.omap2plus_defconfig.orig
7318188	 764348	5613004	13695540	 d0fa34	vmlinux.omap2plus_defconfig


Paul Walmsley (2):
      ARM: OMAP: clean up some smatch warnings, fix some printk(KERN_ERR ...
      ARM: OMAP: unwrap strings


 arch/arm/mach-omap1/board-htcherald.c       |    3 -
 arch/arm/mach-omap1/clock.c                 |    4 +
 arch/arm/mach-omap1/clock_data.c            |   13 ++---
 arch/arm/mach-omap1/dma.c                   |    5 +-
 arch/arm/mach-omap1/lcd_dma.c               |   15 +----
 arch/arm/mach-omap1/leds-h2p2-debug.c       |   12 +++-
 arch/arm/mach-omap2/board-n8x0.c            |    7 +--
 arch/arm/mach-omap2/board-overo.c           |    6 +-
 arch/arm/mach-omap2/board-zoom-debugboard.c |    7 +--
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c      |   10 +---
 arch/arm/mach-omap2/clkt_clksel.c           |   28 +++++-----
 arch/arm/mach-omap2/clkt_dpll.c             |    8 +--
 arch/arm/mach-omap2/clock.c                 |   20 +++----
 arch/arm/mach-omap2/clock3xxx.c             |    3 -
 arch/arm/mach-omap2/clockdomain.c           |   74 ++++++++++++---------------
 arch/arm/mach-omap2/common-board-devices.c  |    3 -
 arch/arm/mach-omap2/dpll3xxx.c              |    7 ++-
 arch/arm/mach-omap2/gpio.c                  |    1 
 arch/arm/mach-omap2/gpmc.c                  |    5 +-
 arch/arm/mach-omap2/id.c                    |    5 +-
 arch/arm/mach-omap2/irq.c                   |    5 +-
 arch/arm/mach-omap2/omap_hwmod.c            |   16 +++---
 arch/arm/mach-omap2/opp.c                   |   15 ++---
 arch/arm/mach-omap2/pm.c                    |    4 +
 arch/arm/mach-omap2/pm34xx.c                |    8 +--
 arch/arm/mach-omap2/pm44xx.c                |    8 +--
 arch/arm/mach-omap2/powerdomain.c           |   36 ++++++-------
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c  |    4 +
 arch/arm/mach-omap2/powerdomain44xx.c       |    4 +
 arch/arm/mach-omap2/prcm.c                  |    8 +--
 arch/arm/mach-omap2/serial.c                |   12 +++-
 arch/arm/mach-omap2/sr_device.c             |   13 ++---
 arch/arm/mach-omap2/timer.c                 |    2 -
 arch/arm/mach-omap2/vc.c                    |    5 +-
 arch/arm/mach-omap2/voltage.c               |   12 ++--
 arch/arm/mach-omap2/vp.c                    |   16 +++---
 arch/arm/plat-omap/dma.c                    |   61 +++++++++-------------
 arch/arm/plat-omap/mux.c                    |    2 -
 arch/arm/plat-omap/omap-pm-noop.c           |   39 +++++++-------
 arch/arm/plat-omap/omap_device.c            |   25 ++++-----
 40 files changed, 239 insertions(+), 292 deletions(-)



From paul at pwsan.com  Tue Aug  7 06:34:43 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 07 Aug 2012 04:34:43 -0600
Subject: [PATCH 1/2] ARM: OMAP: clean up some smatch warnings,
 fix some printk(KERN_ERR ...
In-Reply-To: <20120807103009.8053.69389.stgit@dusk.lan>
References: <20120807103009.8053.69389.stgit@dusk.lan>
Message-ID: <20120807103439.8053.65054.stgit@dusk.lan>

Resolve the following warnings from smatch:

arch/arm/mach-omap2/gpmc.c:282 gpmc_cs_set_timings() info: why not propagate 'div' from gpmc_cs_calc_divider() instead of -1?
arch/arm/mach-omap2/gpmc.c:456 gpmc_cs_free() info: ignoring unreachable code.
arch/arm/mach-omap2/gpmc.c:456 gpmc_cs_free() info: ignoring unreachable code.
arch/arm/mach-omap2/serial.c:328 omap_serial_init_port() error: 'pdev' dereferencing possible ERR_PTR()
arch/arm/mach-omap2/timer.c:213 omap2_gp_clockevent_init() Error invalid range 4096 to -1
arch/arm/mach-omap2/gpio.c:63 omap2_gpio_dev_init() warn: possible memory leak of 'pdata'
arch/arm/mach-omap2/omap_hwmod.c:1478 _assert_hardreset() warn: assigning -22 to unsigned variable 'ret'
arch/arm/mach-omap2/omap_hwmod.c:1487 _assert_hardreset() warn: 4294963201 is more than 255 (max '(ret)' can be) so this is always the same.
arch/arm/mach-omap2/omap_hwmod.c:1545 _read_hardreset() warn: assigning -22 to unsigned variable 'ret'
arch/arm/mach-omap2/omap_hwmod.c:1554 _read_hardreset() warn: 4294963201 is more than 255 (max '(ret)' can be) so this is always the same.
arch/arm/mach-omap2/dpll3xxx.c:629 omap3_clkoutx2_recalc() error: we previously assumed 'pclk' could be null (see line 627)
arch/arm/mach-omap2/board-n8x0.c:422 n8x0_mmc_late_init() Error invalid range 14 to 13
arch/arm/mach-omap1/leds-h2p2-debug.c:71 h2p2_dbg_leds_event() error: potentially derefencing uninitialized 'fpga'.
arch/arm/mach-omap1/lcd_dma.c:97 omap_set_lcd_dma_b1_rotation() info: ignoring unreachable code.
arch/arm/mach-omap1/lcd_dma.c:157 set_b1_regs() info: ignoring unreachable code.
arch/arm/mach-omap1/lcd_dma.c:237 set_b1_regs() info: ignoring unreachable code.
arch/arm/mach-omap1/lcd_dma.c:313 omap_request_lcd_dma() info: ignoring unreachable code.
arch/arm/mach-omap1/lcd_dma.c:340 omap_free_lcd_dma() info: ignoring unreachable code.
arch/arm/plat-omap/dma.c:200 omap_set_dma_priority() info: ignoring unreachable code.
arch/arm/plat-omap/dma.c:567 omap_set_dma_dest_burst_mode() info: ignoring unreachable code.
arch/arm/plat-omap/dma.c:1152 omap_dma_link_lch() info: ignoring unreachable code.
arch/arm/plat-omap/dma.c:1179 omap_dma_unlink_lch() info: ignoring unreachable code.
arch/arm/plat-omap/mux.c:79 omap_cfg_reg() Error invalid range 4096 to -1
arch/arm/plat-omap/dma.c:200 omap_set_dma_priority() info: ignoring unreachable code.
arch/arm/plat-omap/dma.c:567 omap_set_dma_dest_burst_mode() info: ignoring unreachable code.

Also, convert some nearby "printk(KERN_ERR ..." into "pr_err( ...",
and unwrap some strings.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap1/lcd_dma.c         |    9 ++-------
 arch/arm/mach-omap1/leds-h2p2-debug.c |   12 +++++++-----
 arch/arm/mach-omap2/dpll3xxx.c        |    7 +++++--
 arch/arm/mach-omap2/gpio.c            |    1 +
 arch/arm/mach-omap2/gpmc.c            |    5 ++---
 arch/arm/mach-omap2/omap_hwmod.c      |   12 ++++++------
 arch/arm/mach-omap2/serial.c          |    7 +++++--
 arch/arm/mach-omap2/timer.c           |    2 +-
 arch/arm/plat-omap/dma.c              |   19 ++++++-------------
 arch/arm/plat-omap/mux.c              |    2 +-
 10 files changed, 36 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 5769c71..6ec931c 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -94,7 +94,6 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
 	if (cpu_is_omap15xx()) {
 		printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 		BUG();
-		return;
 	}
 	lcd_dma.rotate = rotate;
 }
@@ -154,7 +153,6 @@ static void set_b1_regs(void)
 		break;
 	default:
 		BUG();
-		return;
 	}
 
 	vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
@@ -234,7 +232,6 @@ static void set_b1_regs(void)
 		break;
 	default:
 		BUG();
-		return;	/* Suppress warning about uninitialized vars */
 	}
 
 	if (cpu_is_omap15xx()) {
@@ -308,9 +305,8 @@ int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
 	spin_lock_irq(&lcd_dma.lock);
 	if (lcd_dma.reserved) {
 		spin_unlock_irq(&lcd_dma.lock);
-		printk(KERN_ERR "LCD DMA channel already reserved\n");
+		pr_err("LCD DMA channel already reserved\n");
 		BUG();
-		return -EBUSY;
 	}
 	lcd_dma.reserved = 1;
 	spin_unlock_irq(&lcd_dma.lock);
@@ -335,9 +331,8 @@ void omap_free_lcd_dma(void)
 	spin_lock(&lcd_dma.lock);
 	if (!lcd_dma.reserved) {
 		spin_unlock(&lcd_dma.lock);
-		printk(KERN_ERR "LCD DMA is not reserved\n");
+		pr_err("LCD DMA is not reserved\n");
 		BUG();
-		return;
 	}
 	if (!cpu_is_omap15xx())
 		omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index f6b14a1..78acaa9 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -68,11 +68,13 @@ void h2p2_dbg_leds_event(led_event_t evt)
 			gpio_set_value(GPIO_IDLE, 0);
 		}
 
-		__raw_writew(~0, &fpga->leds);
 		led_state &= ~LED_STATE_ENABLED;
-		if (evt == led_halted) {
-			iounmap(fpga);
-			fpga = NULL;
+		if (fpga) {
+			__raw_writew(~0, &fpga->leds);
+			if (evt == led_halted) {
+				iounmap(fpga);
+				fpga = NULL;
+			}
 		}
 
 		goto done;
@@ -158,7 +160,7 @@ void h2p2_dbg_leds_event(led_event_t evt)
 	/*
 	 *  Actually burn the LEDs
 	 */
-	if (led_state & LED_STATE_ENABLED)
+	if (led_state & LED_STATE_ENABLED && fpga)
 		__raw_writew(~hw_led_state, &fpga->leds);
 
 done:
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..4d0e645 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -623,8 +623,11 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 	while (pclk && !pclk->dpll_data)
 		pclk = pclk->parent;
 
-	/* clk does not have a DPLL as a parent? */
-	WARN_ON(!pclk);
+	/* clk does not have a DPLL as a parent?  error in the clock data */
+	if (!pclk) {
+		WARN_ON(1);
+		return 0;
+	}
 
 	dd = pclk->dpll_data;
 
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d48..30a3a94 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -60,6 +60,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
 	if (!pdata->regs) {
 		pr_err("gpio%d: Memory allocation failed\n", id);
+		kfree(pdata);
 		return -ENOMEM;
 	}
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index b2b5759..ba1bebc 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -279,7 +279,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
 	div = gpmc_cs_calc_divider(cs, t->sync_clk);
 	if (div < 0)
-		return -1;
+		return div;
 
 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
@@ -451,9 +451,8 @@ void gpmc_cs_free(int cs)
 {
 	spin_lock(&gpmc_mem_lock);
 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
-		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
-		BUG();
 		spin_unlock(&gpmc_mem_lock);
+		pr_err("Trying to free non-reserved GPMC CS%d\n", cs);
 		return;
 	}
 	gpmc_cs_disable_mem(cs);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..bd69eae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1438,8 +1438,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
  * Return the bit position of the reset line that match the
  * input name. Return -ENOENT if not found.
  */
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
-			    struct omap_hwmod_rst_info *ohri)
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+			     struct omap_hwmod_rst_info *ohri)
 {
 	int i;
 
@@ -1475,7 +1475,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
 	struct omap_hwmod_rst_info ohri;
-	u8 ret = -EINVAL;
+	int ret = -EINVAL;
 
 	if (!oh)
 		return -EINVAL;
@@ -1484,7 +1484,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 		return -ENOSYS;
 
 	ret = _lookup_hardreset(oh, name, &ohri);
-	if (IS_ERR_VALUE(ret))
+	if (ret < 0)
 		return ret;
 
 	ret = soc_ops.assert_hardreset(oh, &ohri);
@@ -1542,7 +1542,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
 	struct omap_hwmod_rst_info ohri;
-	u8 ret = -EINVAL;
+	int ret = -EINVAL;
 
 	if (!oh)
 		return -EINVAL;
@@ -1551,7 +1551,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 		return -ENOSYS;
 
 	ret = _lookup_hardreset(oh, name, &ohri);
-	if (IS_ERR_VALUE(ret))
+	if (ret < 0)
 		return ret;
 
 	return soc_ops.is_hardreset_asserted(oh, &ohri);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c7..0cc79d3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -313,8 +313,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
 	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 				 NULL, 0, false);
-	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
-	     name, oh->name);
+	if (IS_ERR(pdev)) {
+		WARN(1, "Could not build omap_device for %s: %s.\n", name,
+		     oh->name);
+		return;
+	}
 
 	if ((console_uart_id == bdata->id) && no_console_suspend)
 		omap_device_disable_idle_on_suspend(pdev);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..7e688c7 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -211,7 +211,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 	BUG_ON(res);
 
-	omap2_gp_timer_irq.dev_id = (void *)&clkev;
+	omap2_gp_timer_irq.dev_id = &clkev;
 	setup_irq(clkev.irq, &omap2_gp_timer_irq);
 
 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe6267..7f70235 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -197,7 +197,6 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
 			break;
 		default:
 			BUG();
-			return;
 		}
 		l = omap_readl(reg);
 		l &= ~(0xf << 8);
@@ -562,9 +561,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 		 * fall through
 		 */
 	default:
-		printk(KERN_ERR "Invalid DMA burst mode\n");
+		pr_err("Invalid DMA burst mode\n");
 		BUG();
-		return;
 	}
 	l |= (burst << 14);
 	p->dma_write(l, CSDP, lch);
@@ -1147,15 +1145,13 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 								CCR, lch_head);
 			return;
 		}
-		printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
+		pr_err("DMA linking is not supported in 1510 mode\n");
 		BUG();
-		return;
 	}
 
 	if ((dma_chan[lch_head].dev_id == -1) ||
 	    (dma_chan[lch_queue].dev_id == -1)) {
-		printk(KERN_ERR "omap_dma: trying to link "
-		       "non requested channels\n");
+		pr_err("omap_dma: trying to link non requested channels\n");
 		dump_stack();
 	}
 
@@ -1174,22 +1170,19 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 								CCR, lch_head);
 			return;
 		}
-		printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
+		pr_err("DMA linking is not supported in 1510 mode\n");
 		BUG();
-		return;
 	}
 
 	if (dma_chan[lch_head].next_lch != lch_queue ||
 	    dma_chan[lch_head].next_lch == -1) {
-		printk(KERN_ERR "omap_dma: trying to unlink "
-		       "non linked channels\n");
+		pr_err("omap_dma: trying to unlink non linked channels\n");
 		dump_stack();
 	}
 
 	if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 	    (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
-		printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
-		       "before unlinking\n");
+		pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
 		dump_stack();
 	}
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index cff8712..fd0d3aa 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -76,7 +76,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 		return -ENODEV;
 	}
 
-	reg = (struct pin_config *)&mux_cfg->pins[index];
+	reg = &mux_cfg->pins[index];
 
 	if (!mux_cfg->cfg_reg)
 		return -ENODEV;




From paul at pwsan.com  Tue Aug  7 06:34:46 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 07 Aug 2012 04:34:46 -0600
Subject: [PATCH 2/2] ARM: OMAP: unwrap strings
In-Reply-To: <20120807103009.8053.69389.stgit@dusk.lan>
References: <20120807103009.8053.69389.stgit@dusk.lan>
Message-ID: <20120807103443.8053.68917.stgit@dusk.lan>

Find and unwrap wrapped strings in the style:

	pr_debug("clockdomain: hardware cannot set/clear wake up of "
		 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);

Keeping these strings contiguous seems to be the current Linux kernel
policy.

The offending lines were found with the following command:

    pcregrep -rnM '"\s*$\s*"' arch/arm/*omap*

While here, some messages have been clarified, some pr_warning(
... calls have been converted to pr_warn( ..., and some printk(KERN_*
... have been converted to pr_*.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap1/board-htcherald.c       |    3 -
 arch/arm/mach-omap1/clock.c                 |    4 +
 arch/arm/mach-omap1/clock_data.c            |   13 ++---
 arch/arm/mach-omap1/dma.c                   |    5 +-
 arch/arm/mach-omap1/lcd_dma.c               |    6 +-
 arch/arm/mach-omap2/board-n8x0.c            |    7 +--
 arch/arm/mach-omap2/board-overo.c           |    6 +-
 arch/arm/mach-omap2/board-zoom-debugboard.c |    7 +--
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c      |   10 +---
 arch/arm/mach-omap2/clkt_clksel.c           |   28 +++++-----
 arch/arm/mach-omap2/clkt_dpll.c             |    8 +--
 arch/arm/mach-omap2/clock.c                 |   20 +++----
 arch/arm/mach-omap2/clock3xxx.c             |    3 -
 arch/arm/mach-omap2/clockdomain.c           |   74 ++++++++++++---------------
 arch/arm/mach-omap2/common-board-devices.c  |    3 -
 arch/arm/mach-omap2/id.c                    |    5 +-
 arch/arm/mach-omap2/irq.c                   |    5 +-
 arch/arm/mach-omap2/omap_hwmod.c            |    4 +
 arch/arm/mach-omap2/opp.c                   |   15 ++---
 arch/arm/mach-omap2/pm.c                    |    4 +
 arch/arm/mach-omap2/pm34xx.c                |    8 +--
 arch/arm/mach-omap2/pm44xx.c                |    8 +--
 arch/arm/mach-omap2/powerdomain.c           |   36 ++++++-------
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c  |    4 +
 arch/arm/mach-omap2/powerdomain44xx.c       |    4 +
 arch/arm/mach-omap2/prcm.c                  |    8 +--
 arch/arm/mach-omap2/serial.c                |    5 +-
 arch/arm/mach-omap2/sr_device.c             |   13 ++---
 arch/arm/mach-omap2/vc.c                    |    5 +-
 arch/arm/mach-omap2/voltage.c               |   12 ++--
 arch/arm/mach-omap2/vp.c                    |   16 +++---
 arch/arm/plat-omap/dma.c                    |   42 +++++++--------
 arch/arm/plat-omap/omap-pm-noop.c           |   39 +++++++-------
 arch/arm/plat-omap/omap_device.c            |   25 ++++-----
 34 files changed, 203 insertions(+), 252 deletions(-)

diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index b3f6e94..f0ef008 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -476,8 +476,7 @@ static void __init htcherald_lcd_init(void)
 				break;
 		}
 		if (!tries)
-			printk(KERN_WARNING "Timeout waiting for end of frame "
-			       "-- LCD may not be available\n");
+			pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
 
 		/* turn off DMA */
 		reg = omap_readw(OMAP_DMA_LCD_CCR);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index a9ee06b..638f407 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk)
 	/* Clocks in the DSP domain need api_ck. Just assume bootloader
 	 * has not enabled any DSP clocks */
 	if (clk->enable_reg == DSP_IDLECT2) {
-		printk(KERN_INFO "Skipping reset check for DSP domain "
-		       "clock \"%s\"\n", clk->name);
+		pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
+			clk->name);
 		return;
 	}
 
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c007d80..243e8b2 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -776,11 +776,10 @@ static struct clk_functions omap1_clk_functions = {
 
 static void __init omap1_show_rates(void)
 {
-	pr_notice("Clocking rate (xtal/DPLL1/MPU): "
-			"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-		ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-		ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-		arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+	pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+		  ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+		  ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+		  arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 
 u32 cpu_mask;
@@ -848,8 +847,8 @@ int __init omap1_clk_init(void)
 	if (cpu_is_omap16xx() && crystal_type == 2)
 		ck_ref.rate = 19200000;
 
-	pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
-		"0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+	pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+		omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 		omap_readw(ARM_CKCTL));
 
 	/* We want to be in syncronous scalable mode */
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3ef7d52..f51014d 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -330,8 +330,9 @@ static int __init omap1_system_dma_init(void)
 	d->chan = kzalloc(sizeof(struct omap_dma_lch) *
 					(d->lch_count), GFP_KERNEL);
 	if (!d->chan) {
-		dev_err(&pdev->dev, "%s: Memory allocation failed"
-					"for d->chan!!!\n", __func__);
+		dev_err(&pdev->dev,
+			"%s: Memory allocation failed for d->chan!\n",
+			__func__);
 		goto exit_release_d;
 	}
 
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 6ec931c..a4dc522 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -112,8 +112,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 {
 	if (cpu_is_omap15xx()) {
-		printk(KERN_ERR "DMA virtual resolution is not supported "
-				"in 1510 mode\n");
+		pr_err("DMA virtual resolution is not supported in 1510 mode\n");
 		BUG();
 	}
 	lcd_dma.vxres = vxres;
@@ -432,8 +431,7 @@ static int __init omap_init_lcd_dma(void)
 	r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
 			"LCD DMA", NULL);
 	if (r != 0)
-		printk(KERN_ERR "unable to request IRQ for LCD DMA "
-			       "(error %d)\n", r);
+		pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
 
 	return r;
 }
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 677357f..807299a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -553,8 +553,8 @@ static int n8x0_auto_sleep_regulators(void)
 
 	ret = menelaus_set_regulator_sleep(1, val);
 	if (ret < 0) {
-		printk(KERN_ERR "Could not set regulators to sleep on "
-			"menelaus: %u\n", ret);
+		pr_err("Could not set regulators to sleep on menelaus: %u\n",
+		       ret);
 		return ret;
 	}
 	return 0;
@@ -566,8 +566,7 @@ static int n8x0_auto_voltage_scale(void)
 
 	ret = menelaus_set_vcore_hw(1400, 1050);
 	if (ret < 0) {
-		printk(KERN_ERR "Could not set VCORE voltage on "
-			"menelaus: %u\n", ret);
+		pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
 		return ret;
 	}
 	return 0;
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d..175135a 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -522,8 +522,7 @@ static void __init overo_init(void)
 		udelay(10);
 		gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
 	} else {
-		printk(KERN_ERR "could not obtain gpio for "
-					"OVERO_GPIO_W2W_NRESET\n");
+		pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
 	}
 
 	ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
@@ -542,8 +541,7 @@ static void __init overo_init(void)
 	if (ret == 0)
 		gpio_export(OVERO_GPIO_USBH_CPEN, 0);
 	else
-		printk(KERN_ERR "could not obtain gpio for "
-					"OVERO_GPIO_USBH_CPEN\n");
+		pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index f64f441..1873059 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -81,8 +81,7 @@ static inline void __init zoom_init_quaduart(void)
 	quart_cs = ZOOM_QUADUART_CS;
 
 	if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
-		printk(KERN_ERR "Failed to request GPMC mem"
-				"for Quad UART(TL16CP754C)\n");
+		pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
 		return;
 	}
 
@@ -104,8 +103,8 @@ static inline int omap_zoom_debugboard_detect(void)
 
 	if (gpio_request_one(debug_board_detect, GPIOF_IN,
 			     "Zoom debug board detect") < 0) {
-		printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
-		"board detect\n", debug_board_detect);
+		pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+		       debug_board_detect);
 		return 0;
 	}
 
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..298887b 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -92,15 +92,13 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 		 validrate);
-	pr_debug("clock: SDRC CS0 timing params used:"
-		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
 	if (sdrc_cs1)
-		pr_debug("clock: SDRC CS1 timing params used: "
-		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+		pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+			 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+			 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 
 	if (sdrc_cs1)
 		omap3_configure_core_dpll(
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..19a9809 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 
 	if (!clks->parent) {
 		/* This indicates a data problem */
-		WARN(1, "clock: Could not find parent clock %s in clksel array "
-		     "of clock %s\n", src_clk->name, clk->name);
+		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+		     clk->name, src_clk->name);
 		return NULL;
 	}
 
@@ -126,8 +126,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
 
 	if (max_div == 0) {
 		/* This indicates an error in the clksel data */
-		WARN(1, "clock: Could not find divisor for clock %s parent %s"
-		     "\n", clk->name, src_clk->parent->name);
+		WARN(1, "clock: %s: could not find divisor for parent %s\n",
+		     clk->name, src_clk->parent->name);
 		return 0;
 	}
 
@@ -191,8 +191,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
 	if (!clkr->div) {
 		/* This indicates a data error */
-		WARN(1, "clock: Could not find fieldval %d for clock %s parent "
-		     "%s\n", field_val, clk->name, clk->parent->name);
+		WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
+		     clk->name, field_val, clk->parent->name);
 		return 0;
 	}
 
@@ -230,8 +230,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 	}
 
 	if (!clkr->div) {
-		pr_err("clock: Could not find divisor %d for clock %s parent "
-		       "%s\n", div, clk->name, clk->parent->name);
+		pr_err("clock: %s: could not find divisor %d parent %s\n",
+		       clk->name, div, clk->parent->name);
 		return ~0;
 	}
 
@@ -300,8 +300,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
 		/* Sanity check */
 		if (clkr->div <= last_div)
-			pr_err("clock: clksel_rate table not sorted "
-			       "for clock %s", clk->name);
+			pr_err("clock: %s: clksel_rate table not sorted",
+			       clk->name);
 
 		last_div = clkr->div;
 
@@ -312,9 +312,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 	}
 
 	if (!clkr->div) {
-		pr_err("clock: Could not find divisor for target "
-		       "rate %ld for clock %s parent %s\n", target_rate,
-		       clk->name, clk->parent->name);
+		pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
+		       clk->name, target_rate, clk->parent->name);
 		return ~0;
 	}
 
@@ -359,8 +358,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
 			if (clkr->val == r) {
 				if (clk->parent != clks->parent) {
-					pr_debug("clock: inited %s parent "
-						 "to %s (was %s)\n",
+					pr_debug("clock: %s: inited parent to %s (was %s)\n",
 						 clk->name, clks->parent->name,
 						 ((clk->parent) ?
 						  clk->parent->name : "NULL"));
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..f0b6b4b 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
 	}
 
 	if (fint < fint_min) {
-		pr_debug("rejecting n=%d due to Fint failure, "
-			 "lowering max_divider\n", n);
+		pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+			 n);
 		dd->max_divider = n;
 		ret = DPLL_FINT_UNDERFLOW;
 	} else if (fint > fint_max) {
-		pr_debug("rejecting n=%d due to Fint failure, "
-			 "boosting min_divider\n", n);
+		pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+			 n);
 		dd->min_divider = n;
 		ret = DPLL_FINT_INVALID;
 	} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..eeaf353 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -102,8 +102,8 @@ void omap2_init_clk_clkdm(struct clk *clk)
 			 clk->name, clk->clkdm_name);
 		clk->clkdm = clkdm;
 	} else {
-		pr_debug("clock: could not associate clk %s to "
-			 "clkdm %s\n", clk->name, clk->clkdm_name);
+		pr_debug("clock: could not associate clk %s to clkdm %s\n",
+			 clk->name, clk->clkdm_name);
 	}
 }
 
@@ -226,8 +226,7 @@ void omap2_dflt_clk_disable(struct clk *clk)
 		 * 'Independent' here refers to a clock which is not
 		 * controlled by its parent.
 		 */
-		printk(KERN_ERR "clock: clk_disable called on independent "
-		       "clock %s which has no enable_reg\n", clk->name);
+		pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
 		return;
 	}
 
@@ -270,8 +269,7 @@ const struct clkops clkops_omap2_dflt = {
 void omap2_clk_disable(struct clk *clk)
 {
 	if (clk->usecount == 0) {
-		WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
-		     "already 0?", clk->name);
+		WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
 		return;
 	}
 
@@ -332,8 +330,8 @@ int omap2_clk_enable(struct clk *clk)
 	if (clkdm_control && clk->clkdm) {
 		ret = clkdm_clk_enable(clk->clkdm, clk);
 		if (ret) {
-			WARN(1, "clock: %s: could not enable clockdomain %s: "
-			     "%d\n", clk->name, clk->clkdm->name, ret);
+			WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+			     clk->name, clk->clkdm->name, ret);
 			goto oce_err2;
 		}
 	}
@@ -501,10 +499,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 
 	hfclkin_rate = clk_get_rate(hfclkin_ck);
 
-	pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
-		"%ld.%01ld/%ld/%ld MHz\n",
-		(hfclkin_rate / 1000000),
-		((hfclkin_rate / 100000) % 10),
+	pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+		(hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
 		(clk_get_rate(core_ck) / 1000000),
 		(clk_get_rate(mpu_ck) / 1000000));
 }
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d827..912108e 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 	 * on DPLL4.
 	 */
 	if (omap_rev() == OMAP3430_REV_ES1_0) {
-		pr_err("clock: DPLL4 cannot change rate due to "
-		       "silicon 'Limitation 2.5' on 3430ES1.\n");
+		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
 		return -EINVAL;
 	}
 
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8664f5a..a155562 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
 		if (IS_ERR(autodep->clkdm.ptr))
 			continue;
 
-		pr_debug("clockdomain: adding %s sleepdep/wkdep for "
-			 "clkdm %s\n", autodep->clkdm.ptr->name,
-			 clkdm->name);
+		pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+			 clkdm->name, autodep->clkdm.ptr->name);
 
 		clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
 		clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
@@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
 		if (IS_ERR(autodep->clkdm.ptr))
 			continue;
 
-		pr_debug("clockdomain: removing %s sleepdep/wkdep for "
-			 "clkdm %s\n", autodep->clkdm.ptr->name,
-			 clkdm->name);
+		pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+			 clkdm->name, autodep->clkdm.ptr->name);
 
 		clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
 		clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
@@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear wake up of "
-			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
 	if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
-		pr_debug("clockdomain: hardware will wake up %s when %s wakes "
-			 "up\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+			 clkdm1->name, clkdm2->name);
 
 		ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
 	}
@@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear wake up of "
-			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
 	if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
-		pr_debug("clockdomain: hardware will no longer wake up %s "
-			 "after %s wakes up\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+			 clkdm1->name, clkdm2->name);
 
 		ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
 	}
@@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear wake up of "
-			 "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
@@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear sleep "
-			 "dependency affecting %s from %s\n", clkdm1->name,
-			 clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
 	if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
-		pr_debug("clockdomain: will prevent %s from sleeping if %s "
-			 "is active\n", clkdm1->name, clkdm2->name);
+		pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+			 clkdm1->name, clkdm2->name);
 
 		ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
 	}
@@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear sleep "
-			 "dependency affecting %s from %s\n", clkdm1->name,
-			 clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
 	if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
-		pr_debug("clockdomain: will no longer prevent %s from "
-			 "sleeping if %s is active\n", clkdm1->name,
-			 clkdm2->name);
+		pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+			 clkdm1->name, clkdm2->name);
 
 		ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
 	}
@@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
 		ret = -EINVAL;
 
 	if (ret) {
-		pr_debug("clockdomain: hardware cannot set/clear sleep "
-			 "dependency affecting %s from %s\n", clkdm1->name,
-			 clkdm2->name);
+		pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+			 clkdm1->name, clkdm2->name);
 		return ret;
 	}
 
@@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
 		return -EINVAL;
 
 	if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-		pr_debug("clockdomain: %s does not support forcing "
-			 "sleep via software\n", clkdm->name);
+		pr_debug("clockdomain: %s does not support forcing sleep via software\n",
+			 clkdm->name);
 		return -EINVAL;
 	}
 
@@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
 		return -EINVAL;
 
 	if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-		pr_debug("clockdomain: %s does not support forcing "
-			 "wakeup via software\n", clkdm->name);
+		pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
+			 clkdm->name);
 		return -EINVAL;
 	}
 
@@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
 		return;
 
 	if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
-		pr_debug("clock: automatic idle transitions cannot be enabled "
-			 "on clockdomain %s\n", clkdm->name);
+		pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
+			 clkdm->name);
 		return;
 	}
 
@@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
 		return;
 
 	if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
-		pr_debug("clockdomain: automatic idle transitions cannot be "
-			 "disabled on %s\n", clkdm->name);
+		pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
+			 clkdm->name);
 		return;
 	}
 
@@ -927,7 +921,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 	pwrdm_state_switch(clkdm->pwrdm.ptr);
 	spin_unlock_irqrestore(&clkdm->lock, flags);
 
-	pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+	pr_debug("clockdomain: %s: enabled\n", clkdm->name);
 
 	return 0;
 }
@@ -952,7 +946,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
 	pwrdm_state_switch(clkdm->pwrdm.ptr);
 	spin_unlock_irqrestore(&clkdm->lock, flags);
 
-	pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+	pr_debug("clockdomain: %s: disabled\n", clkdm->name);
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 1473474..e0385f0 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -130,8 +130,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
 	}
 
 	if (nandcs > GPMC_CS_NUM) {
-		printk(KERN_INFO "NAND: Unable to find configuration "
-				 "in GPMC\n ");
+		pr_info("NAND: Unable to find configuration in GPMC\n");
 		return;
 	}
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 40373db..d0631468 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void)
 	}
 
 	if (j == ARRAY_SIZE(omap_ids)) {
-		printk(KERN_ERR "Unknown OMAP device type. "
-				"Handling it as OMAP%04x\n",
-				omap_ids[i].type >> 16);
+		pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+		       omap_ids[i].type >> 16);
 		j = i;
 	}
 
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bcd83db..a4dd4cf 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -107,9 +107,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 	unsigned long tmp;
 
 	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
-	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
-			 "(revision %ld.%ld) with %d interrupts\n",
-			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+		bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 
 	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 	tmp |= 1 << 1;	/* soft reset */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index bd69eae..ae0dd96 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1641,8 +1641,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 
 	/* clocks must be on for this operation */
 	if (oh->_state != _HWMOD_STATE_ENABLED) {
-		pr_warning("omap_hwmod: %s: reset can only be entered from "
-			   "enabled state\n", oh->name);
+		pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+			oh->name);
 		return -EINVAL;
 	}
 
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index d8f6dbf..45ad7f7 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -64,25 +64,22 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
 		}
 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
 		if (!oh || !oh->od) {
-			pr_debug("%s: no hwmod or odev for %s, [%d] "
-				"cannot add OPPs.\n", __func__,
-				opp_def->hwmod_name, i);
+			pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+				 __func__, opp_def->hwmod_name, i);
 			continue;
 		}
 		dev = &oh->od->pdev->dev;
 
 		r = opp_add(dev, opp_def->freq, opp_def->u_volt);
 		if (r) {
-			dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
-				"result=%d\n",
-			       __func__, opp_def->freq,
-			       opp_def->hwmod_name, i, r);
+			dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
+				__func__, opp_def->freq,
+				opp_def->hwmod_name, i, r);
 		} else {
 			if (!opp_def->default_available)
 				r = opp_disable(dev, opp_def->freq);
 			if (r)
-				dev_err(dev, "%s: disable %ld failed for %s "
-					"[%d] result=%d\n",
+				dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
 					__func__, opp_def->freq,
 					opp_def->hwmod_name, i, r);
 		}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..939bd6f 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -203,8 +203,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
 	bootup_volt = opp_get_voltage(opp);
 	rcu_read_unlock();
 	if (!bootup_volt) {
-		pr_err("%s: unable to find voltage corresponding "
-			"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+		pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
+		       __func__, vdd_name);
 		goto exit;
 	}
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..57f3e2e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -400,9 +400,8 @@ restore:
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
-			pr_info("Powerdomain (%s) didn't enter "
-				"target state %d\n",
-			       pwrst->pwrdm->name, pwrst->next_state);
+			pr_info("Powerdomain (%s) didn't enter target state %d\n",
+				pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -742,8 +741,7 @@ int __init omap3_pm_init(void)
 		omap3_secure_ram_storage =
 			kmalloc(0x803F, GFP_KERNEL);
 		if (!omap3_secure_ram_storage)
-			pr_err("Memory allocation failed when "
-			       "allocating for secure sram context\n");
+			pr_err("Memory allocation failed when allocating for secure sram context\n");
 
 		local_irq_disable();
 		local_fiq_disable();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174..04922d1 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -69,9 +69,8 @@ static int omap4_pm_suspend(void)
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
-			pr_info("Powerdomain (%s) didn't enter "
-			       "target state %d\n",
-			       pwrst->pwrdm->name, pwrst->next_state);
+			pr_info("Powerdomain (%s) didn't enter target state %d\n",
+				pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -189,8 +188,7 @@ int __init omap4_pm_init(void)
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
 	if (ret) {
-		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
-				"wakeup dependency\n");
+		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
 		goto err2;
 	}
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..153cfe0 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -339,8 +339,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
 	if (!pwrdm || !clkdm)
 		return -EINVAL;
 
-	pr_debug("powerdomain: associating clockdomain %s with powerdomain "
-		 "%s\n", clkdm->name, pwrdm->name);
+	pr_debug("powerdomain: %s: associating clockdomain %s\n",
+		 pwrdm->name, clkdm->name);
 
 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
 		if (!pwrdm->pwrdm_clkdms[i])
@@ -354,8 +354,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
 	}
 
 	if (i == PWRDM_MAX_CLKDMS) {
-		pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
-			 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+		pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+			 pwrdm->name, clkdm->name);
 		WARN_ON(1);
 		ret = -ENOMEM;
 		goto pac_exit;
@@ -387,16 +387,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
 	if (!pwrdm || !clkdm)
 		return -EINVAL;
 
-	pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
-		 "%s\n", clkdm->name, pwrdm->name);
+	pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+		 pwrdm->name, clkdm->name);
 
 	for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
 		if (pwrdm->pwrdm_clkdms[i] == clkdm)
 			break;
 
 	if (i == PWRDM_MAX_CLKDMS) {
-		pr_debug("powerdomain: clkdm %s not associated with pwrdm "
-			 "%s ?!\n", clkdm->name, pwrdm->name);
+		pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+			 pwrdm->name, clkdm->name);
 		ret = -ENOENT;
 		goto pdc_exit;
 	}
@@ -485,7 +485,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 	if (!(pwrdm->pwrsts & (1 << pwrst)))
 		return -EINVAL;
 
-	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+	pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
 		 pwrdm->name, pwrst);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
@@ -587,7 +587,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 	if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
 		return -EINVAL;
 
-	pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+	pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
 		 pwrdm->name, pwrst);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
@@ -624,8 +624,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 	if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
 		return -EINVAL;
 
-	pr_debug("powerdomain: setting next memory powerstate for domain %s "
-		 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+	pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+		 pwrdm->name, bank, pwrst);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
 		ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
@@ -662,8 +662,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 	if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
 		return -EINVAL;
 
-	pr_debug("powerdomain: setting next memory powerstate for domain %s "
-		 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+	pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+		 pwrdm->name, bank, pwrst);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
 		ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
@@ -841,7 +841,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 	 * warn & fail if it is not ON.
 	 */
 
-	pr_debug("powerdomain: clearing previous power state reg for %s\n",
+	pr_debug("powerdomain: %s: clearing previous power state reg\n",
 		 pwrdm->name);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
@@ -871,8 +871,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
 		return ret;
 
-	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
-		 pwrdm->name);
+	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
 		ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
@@ -901,8 +900,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
 		return ret;
 
-	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
-		 pwrdm->name);
+	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
 		ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 0f0a9f1..3950ccf 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
 			udelay(1);
 
 	if (c > PWRDM_TRANSITION_BAILOUT) {
-		printk(KERN_ERR "powerdomain: waited too long for "
-			"powerdomain %s to complete transition\n", pwrdm->name);
+		pr_err("powerdomain: %s: waited too long to complete transition\n",
+		       pwrdm->name);
 		return -EAGAIN;
 	}
 
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 601325b..aeac6f3 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -198,8 +198,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 		udelay(1);
 
 	if (c > PWRDM_TRANSITION_BAILOUT) {
-		printk(KERN_ERR "powerdomain: waited too long for "
-		       "powerdomain %s to complete transition\n", pwrdm->name);
+		pr_err("powerdomain: %s: waited too long to complete transition\n",
+		       pwrdm->name);
 		return -EAGAIN;
 	}
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 053e24e..d1dd175 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -140,11 +140,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 			  MAX_MODULE_ENABLE_WAIT, i);
 
 	if (i < MAX_MODULE_ENABLE_WAIT)
-		pr_debug("cm: Module associated with clock %s ready after %d "
-			 "loops\n", name, i);
+		pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+			 name, i);
 	else
-		pr_err("cm: Module associated with clock %s didn't enable in "
-		       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+		pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+		       name, MAX_MODULE_ENABLE_WAIT);
 
 	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 };
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 0cc79d3..62763ef 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -229,9 +229,8 @@ static int __init omap_serial_early_init(void)
 
 			if (console_loglevel >= 10) {
 				uart_debug = true;
-				pr_info("%s used as console in debug mode"
-						" uart%d clocks will not be"
-						" gated", uart_name, uart->num);
+				pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+					uart_name, uart->num);
 			}
 
 			if (cmdline_find_option("no_console_suspend"))
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..cbeae56 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
 	sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
 	if (!sr_data) {
-		pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
-			__func__, oh->name);
+		pr_err("%s: Unable to allocate memory for %s sr_data\n",
+		       __func__, oh->name);
 		return -ENOMEM;
 	}
 
 	sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
 	if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
-		pr_err("%s: No voltage domain specified for %s."
-				"Cannot initialize\n", __func__,
-					oh->name);
+		pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+		       __func__, oh->name);
 		goto exit;
 	}
 
@@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
 	omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
 	if (!volt_data) {
-		pr_warning("%s: No Voltage table registered fo VDD%d."
-			"Something really wrong\n\n", __func__, i + 1);
+		pr_err("%s: No Voltage table registered for VDD%d\n",
+		       __func__, i + 1);
 		goto exit;
 	}
 
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 84da34f..4577764 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -116,9 +116,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
 	}
 
 	if (!voltdm->pmic->uv_to_vsel) {
-		pr_err("%s: PMIC function to convert voltage in uV to"
-			"vsel not registered. Hence unable to scale voltage"
-			"for vdd_%s\n", __func__, voltdm->name);
+		pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+		       __func__, voltdm->name);
 		return -ENODATA;
 	}
 
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4dc60e8..3ac8fe1 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
 			return &voltdm->volt_data[i];
 	}
 
-	pr_notice("%s: Unable to match the current voltage with the voltage"
-		"table for vdd_%s\n", __func__, voltdm->name);
+	pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
+		  __func__, voltdm->name);
 
 	return ERR_PTR(-ENODATA);
 }
@@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
 		voltdm->scale = omap_vc_bypass_scale;
 		return;
 	default:
-		pr_warning("%s: Trying to change the method of voltage scaling"
-			"to an unsupported one!\n", __func__);
+		pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
+			__func__);
 	}
 }
 
@@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
 	if (!voltdm || !pwrdm)
 		return -EINVAL;
 
-	pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
-		 "%s\n", pwrdm->name, voltdm->name);
+	pr_debug("voltagedomain: %s: associating powerdomain %s\n",
+		 voltdm->name, pwrdm->name);
 
 	list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
 
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index f95c1ba..85241b8 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
 		udelay(1);
 	}
 	if (timeout >= VP_TRANXDONE_TIMEOUT) {
-		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
-			"Voltage change aborted", __func__, voltdm->name);
+		pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+			__func__, voltdm->name);
 		return -ETIMEDOUT;
 	}
 
@@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
 	omap_test_timeout(vp->common->ops->check_txdone(vp->id),
 			  VP_TRANXDONE_TIMEOUT, timeout);
 	if (timeout >= VP_TRANXDONE_TIMEOUT)
-		pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
-			"TRANXDONE never got set after the voltage update\n",
-			__func__, voltdm->name);
+		pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
+		       __func__, voltdm->name);
 
 	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 
@@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
 	}
 
 	if (timeout >= VP_TRANXDONE_TIMEOUT)
-		pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
-			"to clear the TRANXDONE status\n",
+		pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
 			__func__, voltdm->name);
 
 	/* Clear force bit */
@@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm)
 
 	/* If VP is already disabled, do nothing. Return */
 	if (!vp->enabled) {
-		pr_warning("%s: Trying to disable VP for vdd_%s when"
-			"it is already disabled\n", __func__, voltdm->name);
+		pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
+			__func__, voltdm->name);
 		return;
 	}
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7f70235..8ddada5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -967,8 +967,7 @@ void omap_stop_dma(int lch)
 			l = p->dma_read(CCR, lch);
 		}
 		if (i >= 100)
-			printk(KERN_ERR "DMA drain did not complete on "
-					"lch %d\n", lch);
+			pr_err("DMA drain did not complete on lch %d\n", lch);
 		/* Restore OCP_SYSCONFIG */
 		p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 	} else {
@@ -1824,16 +1823,15 @@ static int omap1_dma_handle_ch(int ch)
 	if ((csr & 0x3f) == 0)
 		return 0;
 	if (unlikely(dma_chan[ch].dev_id == -1)) {
-		printk(KERN_WARNING "Spurious interrupt from DMA channel "
-		       "%d (CSR %04x)\n", ch, csr);
+		pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+			ch, csr);
 		return 0;
 	}
 	if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
-		printk(KERN_WARNING "DMA timeout with device %d\n",
-		       dma_chan[ch].dev_id);
+		pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
 	if (unlikely(csr & OMAP_DMA_DROP_IRQ))
-		printk(KERN_WARNING "DMA synchronization event drop occurred "
-		       "with device %d\n", dma_chan[ch].dev_id);
+		pr_warn("DMA synchronization event drop occurred with device %d\n",
+			dma_chan[ch].dev_id);
 	if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 		dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 	if (likely(dma_chan[ch].callback != NULL))
@@ -1873,21 +1871,19 @@ static int omap2_dma_handle_ch(int ch)
 
 	if (!status) {
 		if (printk_ratelimit())
-			printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
-				ch);
+			pr_warn("Spurious DMA IRQ for lch %d\n", ch);
 		p->dma_write(1 << ch, IRQSTATUS_L0, ch);
 		return 0;
 	}
 	if (unlikely(dma_chan[ch].dev_id == -1)) {
 		if (printk_ratelimit())
-			printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
-					"channel %d\n", status, ch);
+			pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+				status, ch);
 		return 0;
 	}
 	if (unlikely(status & OMAP_DMA_DROP_IRQ))
-		printk(KERN_INFO
-		       "DMA synchronization event drop occurred with device "
-		       "%d\n", dma_chan[ch].dev_id);
+		pr_info("DMA synchronization event drop occurred with device %d\n",
+			dma_chan[ch].dev_id);
 	if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
 		printk(KERN_INFO "DMA transaction error with device %d\n",
 		       dma_chan[ch].dev_id);
@@ -2007,8 +2003,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 
 	p = pdev->dev.platform_data;
 	if (!p) {
-		dev_err(&pdev->dev, "%s: System DMA initialized without"
-			"platform data\n", __func__);
+		dev_err(&pdev->dev,
+			"%s: System DMA initialized without platform data\n",
+			__func__);
 		return -EINVAL;
 	}
 
@@ -2083,8 +2080,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 		}
 		ret = setup_irq(dma_irq, &omap24xx_dma_irq);
 		if (ret) {
-			dev_err(&pdev->dev, "set_up failed for IRQ %d"
-				"for DMA (error %d)\n", dma_irq, ret);
+			dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+				dma_irq, ret);
 			goto exit_dma_lch_fail;
 		}
 	}
@@ -2092,8 +2089,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 	/* reserve dma channels 0 and 1 in high security devices */
 	if (cpu_is_omap34xx() &&
 		(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-		printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
-				"HS ROM code\n");
+		pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
 		dma_chan[0].dev_id = 0;
 		dma_chan[1].dev_id = 1;
 	}
@@ -2101,8 +2097,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 	return 0;
 
 exit_dma_irq_fail:
-	dev_err(&pdev->dev, "unable to request IRQ %d"
-			"for DMA (error %d)\n", dma_irq, ret);
+	dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+		dma_irq, ret);
 	for (irq_rel = 0; irq_rel < ch;	irq_rel++) {
 		dma_irq = platform_get_irq(pdev, irq_rel);
 		free_irq(dma_irq, (void *)(irq_rel + 1));
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 5a97b4d..9f64133 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -41,11 +41,11 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
 	};
 
 	if (t == -1)
-		pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
-			 "dev %s\n", dev_name(dev));
+		pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
+			 dev_name(dev));
 	else
-		pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
-			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+		pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
+			 dev_name(dev), t);
 
 	/*
 	 * For current Linux, this needs to map the MPU to a
@@ -70,11 +70,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
 	};
 
 	if (r == 0)
-		pr_debug("OMAP PM: remove min bus tput constraint: "
-			 "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+		pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
+			 dev_name(dev), agent_id);
 	else
-		pr_debug("OMAP PM: add min bus tput constraint: "
-			 "dev %s for agent_id %d: rate %ld KiB\n",
+		pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
 			 dev_name(dev), agent_id, r);
 
 	/*
@@ -97,11 +96,11 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
 	};
 
 	if (t == -1)
-		pr_debug("OMAP PM: remove max device latency constraint: "
-			 "dev %s\n", dev_name(dev));
+		pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
+			 dev_name(dev));
 	else
-		pr_debug("OMAP PM: add max device latency constraint: "
-			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+		pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
+			 dev_name(dev), t);
 
 	/*
 	 * For current Linux, this needs to map the device to a
@@ -127,11 +126,11 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
 	};
 
 	if (t == -1)
-		pr_debug("OMAP PM: remove max DMA latency constraint: "
-			 "dev %s\n", dev_name(dev));
+		pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
+			 dev_name(dev));
 	else
-		pr_debug("OMAP PM: add max DMA latency constraint: "
-			 "dev %s, t = %ld usec\n", dev_name(dev), t);
+		pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
+			 dev_name(dev), t);
 
 	/*
 	 * For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
 	}
 
 	if (r == 0)
-		pr_debug("OMAP PM: remove min clk rate constraint: "
-			 "dev %s\n", dev_name(dev));
+		pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
+			 dev_name(dev));
 	else
-		pr_debug("OMAP PM: add min clk rate constraint: "
-			 "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+		pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
+			 dev_name(dev), r);
 
 	/*
 	 * Code in a real implementation should keep track of these
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..b59edb0 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
-
 /*
  * omap_device implementation
  *
@@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
 		act_lat = timespec_to_ns(&c);
 
 		dev_dbg(&od->pdev->dev,
-			"omap_device: pm_lat %d: activate: elapsed time "
-			"%llu nsec\n", od->pm_lat_level, act_lat);
+			"omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
+			od->pm_lat_level, act_lat);
 
 		if (act_lat > odpl->activate_lat) {
 			odpl->activate_lat_worst = act_lat;
 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
 				odpl->activate_lat = act_lat;
 				dev_dbg(&od->pdev->dev,
-					"new worst case activate latency "
-					"%d: %llu\n",
+					"new worst case activate latency %d: %llu\n",
 					od->pm_lat_level, act_lat);
 			} else
 				dev_warn(&od->pdev->dev,
-					 "activate latency %d "
-					 "higher than exptected. (%llu > %d)\n",
+					 "activate latency %d higher than expected. (%llu > %d)\n",
 					 od->pm_lat_level, act_lat,
 					 odpl->activate_lat);
 		}
@@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
 		deact_lat = timespec_to_ns(&c);
 
 		dev_dbg(&od->pdev->dev,
-			"omap_device: pm_lat %d: deactivate: elapsed time "
-			"%llu nsec\n", od->pm_lat_level, deact_lat);
+			"omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
+			od->pm_lat_level, deact_lat);
 
 		if (deact_lat > odpl->deactivate_lat) {
 			odpl->deactivate_lat_worst = deact_lat;
 			if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
 				odpl->deactivate_lat = deact_lat;
 				dev_dbg(&od->pdev->dev,
-					"new worst case deactivate latency "
-					"%d: %llu\n",
+					"new worst case deactivate latency %d: %llu\n",
 					od->pm_lat_level, deact_lat);
 			} else
 				dev_warn(&od->pdev->dev,
-					 "deactivate latency %d "
-					 "higher than exptected. (%llu > %d)\n",
+					 "deactivate latency %d higher than expected. (%llu > %d)\n",
 					 od->pm_lat_level, deact_lat,
 					 odpl->deactivate_lat);
 		}
@@ -449,8 +444,8 @@ static int omap_device_count_resources(struct omap_device *od)
 	for (i = 0; i < od->hwmods_cnt; i++)
 		c += omap_hwmod_count_resources(od->hwmods[i]);
 
-	pr_debug("omap_device: %s: counted %d total resources across %d "
-		 "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+	pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
+		 od->pdev->name, c, od->hwmods_cnt);
 
 	return c;
 }




From kgene.kim at samsung.com  Tue Aug  7 06:37:40 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 07 Aug 2012 19:37:40 +0900
Subject: [PATCH 0/2] ARM: S3C24XX: Fix compilation errors with 3.6-rc1
In-Reply-To: <201208051738.27728.heiko@sntech.de>
References: <201208051738.27728.heiko@sntech.de>
Message-ID: <099001cd7488$ab7c3270$02749750$%kim@samsung.com>

Heiko St?bner wrote:
> 
> Small fallout from from the s3c64xx spi changes and from a dma change from
> last year, that only surfaced after a gcc update.
> 
> Heiko Stuebner (2):
>   ARM: S3C24XX: Add missing DMACH_DT_PROP
>   ARM: S3C24XX: Fix s3c2410_dma_enqueue parameters
> 
>  arch/arm/mach-s3c24xx/include/mach/dma.h |    3 ++-
>  arch/arm/plat-s3c24xx/dma.c              |    2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> --
> 1.7.2.3

Applied this series, thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From tony at atomide.com  Tue Aug  7 06:40:23 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 03:40:23 -0700
Subject: [PATCH 1/2] ARM: OMAP: clean up some smatch warnings, fix some
 printk(KERN_ERR ...
In-Reply-To: <20120807103439.8053.65054.stgit@dusk.lan>
References: <20120807103009.8053.69389.stgit@dusk.lan>
 <20120807103439.8053.65054.stgit@dusk.lan>
Message-ID: <20120807104023.GV11011@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120807 03:35]:
> --- a/arch/arm/mach-omap1/lcd_dma.c
> +++ b/arch/arm/mach-omap1/lcd_dma.c
> @@ -94,7 +94,6 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
>  	if (cpu_is_omap15xx()) {
>  		printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
>  		BUG();
> -		return;
>  	}
>  	lcd_dma.rotate = rotate;
>  }
> @@ -154,7 +153,6 @@ static void set_b1_regs(void)
>  		break;
>  	default:
>  		BUG();
> -		return;
>  	}
>  
>  	vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
> @@ -234,7 +232,6 @@ static void set_b1_regs(void)
>  		break;
>  	default:
>  		BUG();
> -		return;	/* Suppress warning about uninitialized vars */
>  	}
>  
>  	if (cpu_is_omap15xx()) {

I think these will cause new randconfig warnings without CONFIG_BUG set.

Tony


From tony at atomide.com  Tue Aug  7 06:44:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 03:44:41 -0700
Subject: [PATCH 1/2] arm/dts: Mark vcxio, v2v1 and v1v8 regulators as
 always on
In-Reply-To: <1343653940-16614-2-git-send-email-rnayak@ti.com>
References: <1343653940-16614-1-git-send-email-rnayak@ti.com>
 <1343653940-16614-2-git-send-email-rnayak@ti.com>
Message-ID: <20120807104441.GW11011@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120730 06:17]:
> vcxio, v2v1 and v1v8 are expected to be always on, update the dtsi
> for twl6030 to reflect this.
> 
> commit '86f5fc' regulator: core: Mark all DT based boards as having
> full constraints) caused these to be disabled at late boot causing
> OMAP4 boards (using twl6030) to lockup.

Thanks I'll apply this one into fixes.

Tony


From p.paneri at samsung.com  Tue Aug  7 06:49:21 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Tue, 7 Aug 2012 16:19:21 +0530
Subject: [PATCH v2 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <098c01cd7483$6a93eeb0$3fbbcc10$%kim@samsung.com>
References: <1344324524-2286-1-git-send-email-p.paneri@samsung.com>
 <098c01cd7483$6a93eeb0$3fbbcc10$%kim@samsung.com>
Message-ID: <CAD6zSYNq+7daWqER1PNaDCiTVrn72B1vGW0e3etZJJUxSnkdOg@mail.gmail.com>

On Tue, Aug 7, 2012 at 3:30 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Praveen Paneri wrote:
>>
>> Changes from v1:
>> Rebased patches to latest usb-next branch
>> Changed the name 'sec_usbphy' to 'samsung_usbphy'
>>
> Yes, looks better. But I'm not sure Felipe or Greg would prefer to use '_'
> not '-'...you used samsung-usbphy as a name in your patch.
Are you suggesting to change the name to 'samsung-usbphy' instead?
>
>> This patch set introduces a phy driver for samsung SoCs. It uses the
>> existing
>> transceiver infrastructure to provide phy control functions. Use of this
>> driver
>> can be extended for usb host phy as well. Over the period of time all the
>> phy
>> related code for most of the samsung SoCs can be integrated here.
>> Removing the existing phy code from mach-s3c64xx but not from other
>> machine
>
> Why? Is there any reason? After quick looking at your patches, seems this
> can remove all of setup-usb-phy in arch/arm/ for Samsung stuff. In addition,
> the isolation hook function also can be put in this by using platform_data
> or dt parsing.
No particular reason for it. Yes it can remove all of the setup-usbphy
code. I will send separate patches adding the support for other SoCs
and removing the phy related code from arch/arm.
>
>> code.This driver is tested with smdk6410 and Exynos4210(with DT).
>>
> I and my colleague, Yulgon will comment on this series soon.
That would be great. Will wait for that. You may use below patch to
add dt support for s3c-hsotg to test it on V310 board.

diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index e28cf10..de3cc78 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -67,6 +67,12 @@
 		reg = <0x125B0000 0x100>;
 	};

+	usbotg at 12480000 {
+		compatible = "samsung,exynos4210-hsotg";
+		reg = <0x12480000 0x20000>;
+		interrupts = <0 71 0>;
+	};
+
 	keypad at 100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index f4ba9a3..79b77ff 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -26,6 +26,7 @@
 #include <linux/seq_file.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/regulator/consumer.h>
@@ -3719,10 +3720,23 @@ static int __devexit s3c_hsotg_remove(struct
platform_device *pdev)
 #define s3c_hsotg_resume NULL
 #endif

+#ifdef CONFIG_OF
+static const struct of_device_id s3c_hsotg_dt_match[] = {
+	{
+		.compatible = "samsung,exynos4210-hsotg",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, s3c_usbphy_dt_match);
+#else
+#define s3c_hsotg_dt_match NULL
+#endif
+
 static struct platform_driver s3c_hsotg_driver = {
 	.driver		= {
 		.name	= "s3c-hsotg",
 		.owner	= THIS_MODULE,
+		.of_match_table = s3c_hsotg_dt_match,
 	},
 	.probe		= s3c_hsotg_probe,
 	.remove		= __devexit_p(s3c_hsotg_remove),

Thanks
Praveen
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
>> Praveen Paneri (5):
>>   usb: phy: samsung: Introducing usb phy driver for hsotg
>>   usb: s3c-hsotg: Adding phy driver support
>>   ARM: S3C64XX: Removing old phy setup code
>>   ARM: S3C64XX: Enabling samsung_usbphy driver
>>   ARM: Exynos4210: Enabling samsung_usbphy driver
>>
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
>>  arch/arm/mach-exynos/include/mach/map.h            |    1 +
>>  arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
>>  arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
>>  arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
>>  arch/arm/mach-s3c64xx/mach-crag6410.c              |    5 +-
>>  arch/arm/mach-s3c64xx/mach-smartq.c                |    6 +-
>>  arch/arm/mach-s3c64xx/mach-smdk6410.c              |    5 +-
>>  arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
>>  arch/arm/plat-samsung/devs.c                       |   32 ++
>>  arch/arm/plat-samsung/include/plat/devs.h          |    1 +
>>  arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>>  drivers/usb/gadget/s3c-hsotg.c                     |   38 ++-
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/samsung_usbphy.c                   |  355
> ++++++++++++++++++++
>>  drivers/usb/phy/samsung_usbphy.h                   |   48 +++
>>  include/linux/platform_data/s3c-hsotg.h            |    5 +
>>  19 files changed, 534 insertions(+), 88 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-
>> usbphy.txt
>>  create mode 100644 drivers/usb/phy/samsung_usbphy.c
>>  create mode 100644 drivers/usb/phy/samsung_usbphy.h
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From broonie at opensource.wolfsonmicro.com  Tue Aug  7 06:52:26 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 7 Aug 2012 11:52:26 +0100
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
In-Reply-To: <20120807054342.GF8468@arwen.pp.htv.fi>
References: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
 <20120806093033.GH17551@arwen.pp.htv.fi>
 <20120806154214.GC29272@sirena.org.uk>
 <20120807054342.GF8468@arwen.pp.htv.fi>
Message-ID: <20120807105225.GT16861@opensource.wolfsonmicro.com>

On Tue, Aug 07, 2012 at 08:43:44AM +0300, Felipe Balbi wrote:
> On Mon, Aug 06, 2012 at 04:42:14PM +0100, Mark Brown wrote:

> > It's good practice to have an explict compatible string even if the
> > default happens to work in order to avoid any name clashes.

> of_i2c.c makes no use whatsoever of the compatible string. See that it
> will build an i2c_boardinfo and register a new device. That compatible

If that's all that's done it seems like a bug frankly, certainly based
on previous discussions it ought to be.  There are collisions out there,
they've just happened to not bite us yet

> string is just churn and has no use at all.

This is device tree we're talking about, there's a lot churn anyway.


From tony at atomide.com  Tue Aug  7 06:58:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 03:58:47 -0700
Subject: [PATCH] Revert "ARM: OMAP3530evm: set pendown_state and
 debounce time for ads7846"
In-Reply-To: <871ujj7ngd.fsf@ti.com>
References: <876298iv9s.fsf@ti.com>
 <1344284535-16717-1-git-send-email-grinberg@compulab.co.il>
 <871ujj7ngd.fsf@ti.com>
Message-ID: <20120807105847.GX11011@atomide.com>

* Kevin Hilman <khilman at ti.com> [120806 13:52]:
> 
> The Overo boards were the ones that were crashing due to this bug since
> the pendown GPIO was the only one used in the bank.
> 
> Tony, can you queue this up for v3.6-rc?  I have a version in my
> for_3.6/fixes/ads7846-2 branch with the tags above applied, based on v3.6-rc1.

Yes thanks pulling into fixes.

Tony


From shubhrajyoti at ti.com  Tue Aug  7 07:27:51 2012
From: shubhrajyoti at ti.com (Shubhrajyoti)
Date: Tue, 07 Aug 2012 16:57:51 +0530
Subject: [PATCH 0/4] i2c: omap: few more patches
In-Reply-To: <1344262737-6662-1-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
Message-ID: <5020FBB7.3030308@ti.com>

On Monday 06 August 2012 07:48 PM, Felipe Balbi wrote:
> Just a few extra patches on top of the earlier series I sent.
>
> With these patches, we have threaded irq support and autosuspend support for
> i2c-omap driver.
Thanks for the patches.
>
> All patches boot tested with pandaboard.
Tested-by: Shubhrajyoti <shubhrajyoti at ti.com>

On omap4sdp and omap3sdp
also on omap3 did some basic power testing.
> Felipe Balbi (4):
>   i2c: omap: always return IRQ_HANDLED
>   i2c: omap: switch to threaded IRQ support
>   i2c: omap: remove unnecessary pm_runtime_suspended check
>   i2c: omap: switch over to autosuspend API
>
>  drivers/i2c/busses/i2c-omap.c | 53 ++++++++++++++++++++++++++++++++++---------
>  1 file changed, 42 insertions(+), 11 deletions(-)
>



From linus.walleij at stericsson.com  Tue Aug  7 07:34:12 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 7 Aug 2012 13:34:12 +0200
Subject: [PATCH] pinctrl/nomadik: fix hsi function group list
Message-ID: <1344339252-30978-1-git-send-email-linus.walleij@stericsson.com>

From: Patrice Chotard <patrice.chotard at stericsson.com>

Tidy up a small typo in the HSI function group list.

Signed-off-by: Patrice Chotard <patrice.chotard at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinctrl-nomadik-db8500.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index 6f99769..5f3e9d0 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -766,7 +766,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
 DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
 DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
 DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
-DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1", "hsit_a_2");
+DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
 DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
 DB8500_FUNC_GROUPS(usb, "usb_a_1");
 DB8500_FUNC_GROUPS(trig, "trig_b_1");
-- 
1.7.11.3



From shubhrajyoti at ti.com  Tue Aug  7 07:38:04 2012
From: shubhrajyoti at ti.com (Shubhrajyoti)
Date: Tue, 07 Aug 2012 17:08:04 +0530
Subject: [PATCH 4/4] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344262737-6662-5-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
 <1344262737-6662-5-git-send-email-balbi@ti.com>
Message-ID: <5020FE1C.2010005@ti.com>

Hi Felipe,
On Monday 06 August 2012 07:48 PM, Felipe Balbi wrote:
> this helps us reduce unnecessary pm transitions
> in case we have another i2c message been started
> soon.
>
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
>  drivers/i2c/busses/i2c-omap.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 60928f2..22efaba 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -645,7 +645,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  
>  	omap_i2c_wait_for_bb(dev);
>  out:
> -	pm_runtime_put(dev->dev);
> +	pm_runtime_mark_last_busy(dev->dev);
> +	pm_runtime_put_autosuspend(dev->dev);
>  	return r;
>  }
>  
> @@ -1113,6 +1114,9 @@ omap_i2c_probe(struct platform_device *pdev)
>  		dev->regs = (u8 *)reg_map_ip_v1;
>  
>  	pm_runtime_enable(dev->dev);
> +	pm_runtime_set_autosuspend_delay(dev->dev, 1000);
> +	pm_runtime_use_autosuspend(dev->dev);
> +
>  	r = pm_runtime_get_sync(dev->dev);
>  	if (IS_ERR_VALUE(r))
>  		goto err_free_mem;
> @@ -1189,7 +1193,7 @@ omap_i2c_probe(struct platform_device *pdev)
>  
>  	of_i2c_register_devices(adap);
>  
> -	pm_runtime_put(dev->dev);
Should we mark it last busy stamp here here?
Or it may not take effect till the first transaction.


> +	pm_runtime_put_autosuspend(dev->dev);
>  
>  	return 0;
>  



From anilkumar at ti.com  Tue Aug  7 07:40:40 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 7 Aug 2012 11:40:40 +0000
Subject: [PATCH v2 1/2] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <501B6F99.4020506@ti.com>
References: <1343219012-19472-1-git-send-email-anilkumar@ti.com>
 <1343219012-19472-2-git-send-email-anilkumar@ti.com>
 <501B6F99.4020506@ti.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA0D423@DBDE01.ent.ti.com>

Vaibhav,

Thanks for the review.

On Fri, Aug 03, 2012 at 11:58:41, Hiremath, Vaibhav wrote:
> 
> 
> On 7/25/2012 5:53 PM, AnilKumar Ch wrote:
> > Add Bosch D_CAN controller device tree data to AM33XX dtsi file
> > by adding d_can device node with all the necessary parameters.
> > 
> > Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> > ---
> >  arch/arm/boot/dts/am33xx.dtsi |    5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> > index 9b974dc..2db2ffb 100644
> > --- a/arch/arm/boot/dts/am33xx.dtsi
> > +++ b/arch/arm/boot/dts/am33xx.dtsi
> > @@ -163,5 +163,10 @@
> >  			#size-cells = <0>;
> >  			ti,hwmods = "i2c3";
> >  		};
> > +
> > +		dcan1: d_can at 481D0000 {
> > +			compatible = "bosch,d_can";
> > +			ti,hwmods = "d_can1";
> > +		};
> 
> Anil,
> 
> Any reason why we are only specifying dcan1 instance? Shouldn't we
> specify dcan0 as well here?
> 

Yes, I agree dcan0 needs to add because SoC support two instances. I
have added d_can1 only because on AM335x-EVM d_can1 is available and
in other case AM335x-bone have two instances available. I will send next
version of these patches.

Regards
AnilKumar


From lee.jones at linaro.org  Tue Aug  7 07:41:15 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 7 Aug 2012 12:41:15 +0100
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120806153503.GH10524@gmail.com>
 <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
Message-ID: <20120807114113.GA5684@gmail.com>

> > diff --git a/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
> > new file mode 120000
> > index 0000000..427334b
> > --- /dev/null
> > +++ b/drivers/gpu/mali/mali400ko/driver/src/devicedrv/mali/arch
> > @@ -0,0 +1 @@
> 
> NACK, what is this stuff? It's even out-of-tree code.

Whoa, no idea! Good spot though, I missed this completely.

> Please be careful with git add -A, I prefer to use git add <pathspec>
> I suspect that may be why this happened...

I don't use `git add -A`, ever. If I'm adding files, I usually use 
`git commit -s -- <pathspec>`, or `git commit -a` if I'm sure I require
all the necessary changes. I guess I could have accidentally collected 
it using `git add -i` whist fixing it up, or a similar misdemeanor.

> Please fix it up and send a v3.

Of course.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From b29396 at freescale.com  Tue Aug  7 07:34:19 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 7 Aug 2012 19:34:19 +0800
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <20120807084904.GA9888@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <CAP1dx+wRZea8o8KTGRDCMtQkt7EjDRN5EoFek80OKqJgTxbvZA@mail.gmail.com>
 <20120807084904.GA9888@pengutronix.de>
Message-ID: <20120807113418.GA13786@shlinux2.ap.freescale.net>

On Tue, Aug 07, 2012 at 10:49:04AM +0200, Uwe Kleine-K?nig wrote:
...
> > > +See below for available PIN_FUNC_ID for imx35:
> > > +# grep '   IMX_PIN_REG' drivers/pinctrl/pinctrl-imx35.c | awk '{ print NR-1 " " $8 }'
> > > +0 MX35_PAD_CAPTURE__GPT_CAPIN1
> > > +1 MX35_PAD_CAPTURE__GPT_CMPOUT2
> > I'm not sure if you can use the format as exist IMX PIN_FUNC_ID tables as:
> > MX35_PAD_CAPTURE__GPT_CAPIN1        0
> > MX35_PAD_CAPTURE__GPT_CMPOUT2    1
> I choosed to switch the order here to have a more column like format.
> the length of the numbers is more uniform. I can switch if you want.
> 
I think either is ok.
You can do as you wish. :)

> > Maybe the difficulty is the command (i did not know how to do it before),
> > If you know, we can do like that.
> > Anyway, it's not a big issue and does not block an ack.
> > 
> > > +enum imx35_pads {
> > > +       /* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
> > > +       MX35_PAD_CAPTURE,
> > > +       MX35_PAD_COMPARE,
> > > +       MX35_PAD_WDOG_RST,
> > > +       MX35_PAD_GPIO1_0,
> > > +       MX35_PAD_GPIO1_1,
> > > +       MX35_PAD_GPIO2_0,
> > > +       MX35_PAD_GPIO3_0,
> > Can we use the format as exist one?
> > enum imx53_pads {
> >         MX53_PAD_GPIO_19 = 1,
> >         MX53_PAD_KEY_COL0 = 2,
> >         MX53_PAD_KEY_ROW0 = 3,
> >         MX53_PAD_KEY_COL1 = 4,
> > .......
> > }
> > Then people can easy know its pin id.
> > I'm wondering there may be still some debug info are using pin id
> > then the above format helps.
> I didn't see output referring to pin ids (which doesn't mean it doesn't
> exist of course). I don't care much
Right, it seems currently most places of debug information
has a pin name going with pin id.
So without id here seems not affect debug information a lot.

But i'm not sure whether it won't be used in the future since it's a basic
property of pin and should be nature to have.
e.g. i formerly proposed pinctrl gpio binding uses the pin id like:
<&gpio0 $gpio_offset $pin_id $count>
So i think it may be better to also explicitly define it in driver.
It does not harm and make things clear, especially it's not a big work. :)

> and wondered why you started at 1 and not 0.
It looks my mistake during the data transition before.:)
It should be better 0. Thanks for the finding.

Regards
Dong Aisheng



From will.deacon at arm.com  Tue Aug  7 07:56:47 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 Aug 2012 12:56:47 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with asm-generic/mutex-xchg.h
Message-ID: <20120807115647.GA12828@mudshark.cambridge.arm.com>

Hello,

ARM recently moved to asm-generic/mutex-xchg.h for its mutex implementation
after our previous implementation was found to be missing some crucial
memory barriers. However, I'm seeing some problems running hackbench on
SMP platforms due to the way in which the MUTEX_SPIN_ON_OWNER code operates.

The symptoms are that a bunch of hackbench tasks are left waiting on an
unlocked mutex and therefore never get woken up to claim it. I think this
boils down to the following sequence:


        Task A        Task B        Task C        Lock value
0                                                     1
1       lock()                                        0
2                     lock()                          0
3                     spin(A)                         0
4       unlock()                                      1
5                                   lock()            0
6                     cmpxchg(1,0)                    0
7                     contended()                    -1
8       lock()                                        0
9       spin(C)                                       0
10                                  unlock()          1
11      cmpxchg(1,0)                                  0
12      unlock()                                      1


At this point, the lock is unlocked, but Task B is in an uninterruptible
sleep with nobody to wake it up.

The following patch fixes the problem by ensuring we put the lock into
the contended state if we acquire it from the spin loop on the slowpath
but I'd like to be sure that this won't cause problems with other mutex
implementations:


diff --git a/kernel/mutex.c b/kernel/mutex.c
index a307cc9..27b7887 100644
--- a/kernel/mutex.c
+++ b/kernel/mutex.c
@@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
                if (owner && !mutex_spin_on_owner(lock, owner))
                        break;
 
-               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
+               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
                        lock_acquired(&lock->dep_map, ip);
                        mutex_set_owner(lock);
                        preempt_enable();


All comments welcome.

Cheers,

Will


From laurent.pinchart at ideasonboard.com  Tue Aug  7 08:01:43 2012
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 07 Aug 2012 14:01:43 +0200
Subject: [PATCH v3 4/4] fbdev: sh_mobile_lcdc: use dma_mmap_coherent if
 available
In-Reply-To: <1344246924-32620-5-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-5-git-send-email-hdk@igel.co.jp>
Message-ID: <1854100.yBXTHaXkcr@avalon>

Hi Eiraku-san,

On Monday 06 August 2012 18:55:24 Hideki EIRAKU wrote:
> fb_mmap() implemented in fbmem.c uses smem_start as the physical
> address of the frame buffer.  In the sh_mobile_lcdc driver, the
> smem_start is a dma_addr_t that is not a physical address when IOMMU is
> enabled.  dma_mmap_coherent() maps the address correctly.  It is
> available on ARM platforms.
> 
> Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>

Acked-by: Hideki EIRAKU <hdk at igel.co.jp>

As this patch doesn't depend on any other patch in your series 
(ARCH_HAS_DMA_MMAP_COHERENT will not be defined without 1/4, so this patch 
will be a no-op until then), I've applied it to my tree and will push it to 
avoid merge conflicts, unless you would prefer to push it yourself.

> ---
>  drivers/video/sh_mobile_lcdcfb.c |   28 ++++++++++++++++++++++++++++
>  1 files changed, 28 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/video/sh_mobile_lcdcfb.c
> b/drivers/video/sh_mobile_lcdcfb.c index 8cb653b..c8cba7a 100644
> --- a/drivers/video/sh_mobile_lcdcfb.c
> +++ b/drivers/video/sh_mobile_lcdcfb.c
> @@ -1614,6 +1614,17 @@ static int sh_mobile_lcdc_overlay_blank(int blank,
> struct fb_info *info) return 1;
>  }
> 
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> +static int
> +sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct
> *vma) +{
> +	struct sh_mobile_lcdc_overlay *ovl = info->par;
> +
> +	return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
> +				 ovl->dma_handle, ovl->fb_size);
> +}
> +#endif
> +
>  static struct fb_ops sh_mobile_lcdc_overlay_ops = {
>  	.owner          = THIS_MODULE,
>  	.fb_read        = fb_sys_read,
> @@ -1626,6 +1637,9 @@ static struct fb_ops sh_mobile_lcdc_overlay_ops = {
>  	.fb_ioctl       = sh_mobile_lcdc_overlay_ioctl,
>  	.fb_check_var	= sh_mobile_lcdc_overlay_check_var,
>  	.fb_set_par	= sh_mobile_lcdc_overlay_set_par,
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> +	.fb_mmap	= sh_mobile_lcdc_overlay_mmap,
> +#endif
>  };
> 
>  static void
> @@ -2093,6 +2107,17 @@ static int sh_mobile_lcdc_blank(int blank, struct
> fb_info *info) return 0;
>  }
> 
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> +static int
> +sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
> +{
> +	struct sh_mobile_lcdc_chan *ch = info->par;
> +
> +	return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
> +				 ch->dma_handle, ch->fb_size);
> +}
> +#endif
> +
>  static struct fb_ops sh_mobile_lcdc_ops = {
>  	.owner          = THIS_MODULE,
>  	.fb_setcolreg	= sh_mobile_lcdc_setcolreg,
> @@ -2108,6 +2133,9 @@ static struct fb_ops sh_mobile_lcdc_ops = {
>  	.fb_release	= sh_mobile_lcdc_release,
>  	.fb_check_var	= sh_mobile_lcdc_check_var,
>  	.fb_set_par	= sh_mobile_lcdc_set_par,
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> +	.fb_mmap	= sh_mobile_lcdc_mmap,
> +#endif
>  };
> 
>  static void

-- 
Regards,

Laurent Pinchart



From balbi at ti.com  Tue Aug  7 08:07:29 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 7 Aug 2012 15:07:29 +0300
Subject: [PATCH 4/4] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344262737-6662-5-git-send-email-balbi@ti.com>
References: <1344262737-6662-1-git-send-email-balbi@ti.com>
 <1344262737-6662-5-git-send-email-balbi@ti.com>
Message-ID: <20120807120728.GW8468@arwen.pp.htv.fi>

Hi,

On Mon, Aug 06, 2012 at 05:18:57PM +0300, Felipe Balbi wrote:
> this helps us reduce unnecessary pm transitions
> in case we have another i2c message been started
> soon.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
>  drivers/i2c/busses/i2c-omap.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 60928f2..22efaba 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -645,7 +645,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  
>  	omap_i2c_wait_for_bb(dev);
>  out:
> -	pm_runtime_put(dev->dev);
> +	pm_runtime_mark_last_busy(dev->dev);
> +	pm_runtime_put_autosuspend(dev->dev);
>  	return r;
>  }
>  
> @@ -1113,6 +1114,9 @@ omap_i2c_probe(struct platform_device *pdev)
>  		dev->regs = (u8 *)reg_map_ip_v1;
>  
>  	pm_runtime_enable(dev->dev);
> +	pm_runtime_set_autosuspend_delay(dev->dev, 1000);
> +	pm_runtime_use_autosuspend(dev->dev);
> +
>  	r = pm_runtime_get_sync(dev->dev);
>  	if (IS_ERR_VALUE(r))
>  		goto err_free_mem;
> @@ -1189,7 +1193,7 @@ omap_i2c_probe(struct platform_device *pdev)
>  
>  	of_i2c_register_devices(adap);
>  
> -	pm_runtime_put(dev->dev);
> +	pm_runtime_put_autosuspend(dev->dev);

Probably... nice catch. Will send v2

-- 
balbi
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From l.krishna at samsung.com  Tue Aug  7 08:26:45 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 17:56:45 +0530
Subject: [PATCH V4 0/2] arm: samsung: Move FIMD headers to include/video/
Message-ID: <1344342407-9970-1-git-send-email-l.krishna@samsung.com>

This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch side
to include/video/samsung_fimd.h

This patchset is created and rebased against master branch of torvalds tree.
Tested on smdk5250 board, build tested for other boards.

Changes from version 3:
	- Squashed 1st, 3rd, 4th and 5th patches from version 3

Changes from version 2:
	- Changed the EXYNOS5_xxx macro name to FIMD_V8_xxx
	- Moved the header inclusion under same kind

Changes from version 1:
	- Split the patches as per Sylwester comments
	- Changed FIMD_V8_xxx macro to EXYNOS5_xxx	

Leela Krishna Amudala (2):
  include/video: move fimd register headers from platform to
    include/video
  include/video: Add register offsets for FIMD version 8

 arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
 arch/arm/mach-exynos/mach-origen.c                 |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --------------------
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/video/s3c-fb.c                             |    2 +-
 .../plat/regs-fb.h => include/video/samsung_fimd.h |  152 +++++++++++++++++--
 26 files changed, 165 insertions(+), 194 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 rename arch/arm/plat-samsung/include/plat/regs-fb.h => include/video/samsung_fimd.h (73%)



From linus.walleij at stericsson.com  Tue Aug  7 08:12:18 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 7 Aug 2012 14:12:18 +0200
Subject: [PATCH] pinctrl/nomadik: add ASIC DB8450 pinctrl driver
Message-ID: <1344341538-32223-1-git-send-email-linus.walleij@stericsson.com>

From: Patrice Chotard <patrice.chotard at stericsson.com>

This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.

Signed-off-by: Patrice Chotard <patrice.chotard at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/Kconfig                  |   4 +
 drivers/pinctrl/Makefile                 |   1 +
 drivers/pinctrl/pinctrl-nomadik-db8540.c | 999 +++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-nomadik.c        |   3 +
 drivers/pinctrl/pinctrl-nomadik.h        |  14 +
 5 files changed, 1021 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-nomadik-db8540.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..062f1a3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -90,6 +90,10 @@ config PINCTRL_DB8500
 	bool "DB8500 pin controller driver"
 	depends on PINCTRL_NOMADIK && ARCH_U8500
 
+config PINCTRL_DB8540
+	bool "DB8540 pin controller driver"
+	depends on PINCTRL_NOMADIK && ARCH_U8500
+
 config PINCTRL_PXA168
 	bool "PXA168 pin controller driver"
 	depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..b44538e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
 obj-$(CONFIG_PINCTRL_IMX28)	+= pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_NOMADIK)	+= pinctrl-nomadik.o
 obj-$(CONFIG_PINCTRL_DB8500)	+= pinctrl-nomadik-db8500.o
+obj-$(CONFIG_PINCTRL_DB8540)	+= pinctrl-nomadik-db8540.o
 obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)	+= pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
new file mode 100644
index 0000000..3daf665
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -0,0 +1,999 @@
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-nomadik.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define _GPIO(offset)		(offset)
+
+#define DB8540_PIN_AH6		_GPIO(0)
+#define DB8540_PIN_AG7		_GPIO(1)
+#define DB8540_PIN_AF2		_GPIO(2)
+#define DB8540_PIN_AD3		_GPIO(3)
+#define DB8540_PIN_AF6		_GPIO(4)
+#define DB8540_PIN_AG6		_GPIO(5)
+#define DB8540_PIN_AD5		_GPIO(6)
+#define DB8540_PIN_AF7		_GPIO(7)
+#define DB8540_PIN_AG5		_GPIO(8)
+#define DB8540_PIN_AH5		_GPIO(9)
+#define DB8540_PIN_AE4		_GPIO(10)
+#define DB8540_PIN_AD1		_GPIO(11)
+#define DB8540_PIN_AD2		_GPIO(12)
+#define DB8540_PIN_AC2		_GPIO(13)
+#define DB8540_PIN_AC4		_GPIO(14)
+#define DB8540_PIN_AC3		_GPIO(15)
+#define DB8540_PIN_AH7		_GPIO(16)
+#define DB8540_PIN_AE7		_GPIO(17)
+/* Hole */
+#define DB8540_PIN_AF8		_GPIO(22)
+#define DB8540_PIN_AH11		_GPIO(23)
+#define DB8540_PIN_AG11		_GPIO(24)
+#define DB8540_PIN_AF11		_GPIO(25)
+#define DB8540_PIN_AH10		_GPIO(26)
+#define DB8540_PIN_AG10		_GPIO(27)
+#define DB8540_PIN_AF10		_GPIO(28)
+/* Hole */
+#define DB8540_PIN_AD4		_GPIO(33)
+#define DB8540_PIN_AF3		_GPIO(34)
+#define DB8540_PIN_AF5		_GPIO(35)
+#define DB8540_PIN_AG4		_GPIO(36)
+#define DB8540_PIN_AF9		_GPIO(37)
+#define DB8540_PIN_AE8		_GPIO(38)
+/* Hole */
+#define DB8540_PIN_M26		_GPIO(64)
+#define DB8540_PIN_M25		_GPIO(65)
+#define DB8540_PIN_M27		_GPIO(66)
+#define DB8540_PIN_N25		_GPIO(67)
+/* Hole */
+#define DB8540_PIN_M28		_GPIO(70)
+#define DB8540_PIN_N26		_GPIO(71)
+#define DB8540_PIN_M22		_GPIO(72)
+#define DB8540_PIN_N22		_GPIO(73)
+#define DB8540_PIN_N27		_GPIO(74)
+#define DB8540_PIN_N28		_GPIO(75)
+#define DB8540_PIN_P22		_GPIO(76)
+#define DB8540_PIN_P28		_GPIO(77)
+#define DB8540_PIN_P26		_GPIO(78)
+#define DB8540_PIN_T22		_GPIO(79)
+#define DB8540_PIN_R27		_GPIO(80)
+#define DB8540_PIN_P27		_GPIO(81)
+#define DB8540_PIN_R26		_GPIO(82)
+#define DB8540_PIN_R25		_GPIO(83)
+#define DB8540_PIN_U22		_GPIO(84)
+#define DB8540_PIN_T27		_GPIO(85)
+#define DB8540_PIN_T25		_GPIO(86)
+#define DB8540_PIN_T26		_GPIO(87)
+/* Hole */
+#define DB8540_PIN_AF20		_GPIO(116)
+#define DB8540_PIN_AG21		_GPIO(117)
+#define DB8540_PIN_AH19		_GPIO(118)
+#define DB8540_PIN_AE19		_GPIO(119)
+#define DB8540_PIN_AG18		_GPIO(120)
+#define DB8540_PIN_AH17		_GPIO(121)
+#define DB8540_PIN_AF19		_GPIO(122)
+#define DB8540_PIN_AF18		_GPIO(123)
+#define DB8540_PIN_AE18		_GPIO(124)
+#define DB8540_PIN_AG17		_GPIO(125)
+#define DB8540_PIN_AF17		_GPIO(126)
+#define DB8540_PIN_AE17		_GPIO(127)
+#define DB8540_PIN_AC27		_GPIO(128)
+#define DB8540_PIN_AD27		_GPIO(129)
+#define DB8540_PIN_AE28		_GPIO(130)
+#define DB8540_PIN_AG26		_GPIO(131)
+#define DB8540_PIN_AF25		_GPIO(132)
+#define DB8540_PIN_AE27		_GPIO(133)
+#define DB8540_PIN_AF27		_GPIO(134)
+#define DB8540_PIN_AG28		_GPIO(135)
+#define DB8540_PIN_AF28		_GPIO(136)
+#define DB8540_PIN_AG25		_GPIO(137)
+#define DB8540_PIN_AG24		_GPIO(138)
+#define DB8540_PIN_AD25		_GPIO(139)
+#define DB8540_PIN_AH25		_GPIO(140)
+#define DB8540_PIN_AF26		_GPIO(141)
+#define DB8540_PIN_AF23		_GPIO(142)
+#define DB8540_PIN_AG23		_GPIO(143)
+#define DB8540_PIN_AE25		_GPIO(144)
+#define DB8540_PIN_AH24		_GPIO(145)
+#define DB8540_PIN_AJ25		_GPIO(146)
+#define DB8540_PIN_AG27		_GPIO(147)
+#define DB8540_PIN_AH23		_GPIO(148)
+#define DB8540_PIN_AE26		_GPIO(149)
+#define DB8540_PIN_AE24		_GPIO(150)
+#define DB8540_PIN_AJ24		_GPIO(151)
+#define DB8540_PIN_AE21		_GPIO(152)
+#define DB8540_PIN_AG22		_GPIO(153)
+#define DB8540_PIN_AF21		_GPIO(154)
+#define DB8540_PIN_AF24		_GPIO(155)
+#define DB8540_PIN_AH22		_GPIO(156)
+#define DB8540_PIN_AJ23		_GPIO(157)
+#define DB8540_PIN_AH21		_GPIO(158)
+#define DB8540_PIN_AG20		_GPIO(159)
+#define DB8540_PIN_AE23		_GPIO(160)
+#define DB8540_PIN_AH20		_GPIO(161)
+#define DB8540_PIN_AG19		_GPIO(162)
+#define DB8540_PIN_AF22		_GPIO(163)
+#define DB8540_PIN_AJ21		_GPIO(164)
+#define DB8540_PIN_AD26		_GPIO(165)
+#define DB8540_PIN_AD28		_GPIO(166)
+#define DB8540_PIN_AC28		_GPIO(167)
+#define DB8540_PIN_AC26		_GPIO(168)
+/* Hole */
+#define DB8540_PIN_J3		_GPIO(192)
+#define DB8540_PIN_H1		_GPIO(193)
+#define DB8540_PIN_J2		_GPIO(194)
+#define DB8540_PIN_H2		_GPIO(195)
+#define DB8540_PIN_H3		_GPIO(196)
+#define DB8540_PIN_H4		_GPIO(197)
+#define DB8540_PIN_G2		_GPIO(198)
+#define DB8540_PIN_G3		_GPIO(199)
+#define DB8540_PIN_G4		_GPIO(200)
+#define DB8540_PIN_F2		_GPIO(201)
+#define DB8540_PIN_C6		_GPIO(202)
+#define DB8540_PIN_B6		_GPIO(203)
+#define DB8540_PIN_B7		_GPIO(204)
+#define DB8540_PIN_A7		_GPIO(205)
+#define DB8540_PIN_D7		_GPIO(206)
+#define DB8540_PIN_D8		_GPIO(207)
+#define DB8540_PIN_F3		_GPIO(208)
+#define DB8540_PIN_E2		_GPIO(209)
+#define DB8540_PIN_C7		_GPIO(210)
+#define DB8540_PIN_B8		_GPIO(211)
+#define DB8540_PIN_C10		_GPIO(212)
+#define DB8540_PIN_C8		_GPIO(213)
+#define DB8540_PIN_C9		_GPIO(214)
+/* Hole */
+#define DB8540_PIN_B9		_GPIO(219)
+#define DB8540_PIN_A10		_GPIO(220)
+#define DB8540_PIN_D9		_GPIO(221)
+#define DB8540_PIN_B11		_GPIO(222)
+#define DB8540_PIN_B10		_GPIO(223)
+#define DB8540_PIN_E10		_GPIO(224)
+#define DB8540_PIN_B12		_GPIO(225)
+#define DB8540_PIN_D10		_GPIO(226)
+#define DB8540_PIN_D11		_GPIO(227)
+#define DB8540_PIN_AJ6		_GPIO(228)
+#define DB8540_PIN_B13		_GPIO(229)
+#define DB8540_PIN_C12		_GPIO(230)
+#define DB8540_PIN_B14		_GPIO(231)
+#define DB8540_PIN_E11		_GPIO(232)
+/* Hole */
+#define DB8540_PIN_D12		_GPIO(256)
+#define DB8540_PIN_D15		_GPIO(257)
+#define DB8540_PIN_C13		_GPIO(258)
+#define DB8540_PIN_C14		_GPIO(259)
+#define DB8540_PIN_C18		_GPIO(260)
+#define DB8540_PIN_C16		_GPIO(261)
+#define DB8540_PIN_B16		_GPIO(262)
+#define DB8540_PIN_D18		_GPIO(263)
+#define DB8540_PIN_C15		_GPIO(264)
+#define DB8540_PIN_C17		_GPIO(265)
+#define DB8540_PIN_B17		_GPIO(266)
+#define DB8540_PIN_D17		_GPIO(267)
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
+	PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
+	PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
+	PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
+	PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
+	PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
+	PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
+	PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
+	PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
+	PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
+	PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
+	PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
+	PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
+	PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
+	PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
+	PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
+	PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
+	PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
+	PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
+	PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
+	PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
+	PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
+	PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
+	PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
+	PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
+	PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
+	PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
+	PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
+	PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
+	PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
+	PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
+	PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
+	PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
+	PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
+	PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
+	PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
+	PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
+	PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
+	PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
+	PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
+	PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
+	PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
+	PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
+	PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
+	PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
+	PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
+	PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
+	PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
+	PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
+	PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
+	PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
+	PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
+	PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
+	PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
+	PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
+	PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
+	PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
+	PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
+	PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
+	PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
+	PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
+	PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
+	PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
+	PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
+	PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
+	PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
+	PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
+	PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
+	PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
+	PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
+	PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
+	PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
+	PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
+	PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
+	PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
+	PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
+	PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
+	PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
+	PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
+	PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
+	PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
+	PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
+	PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
+	PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
+	PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
+	PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
+	PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
+	PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
+	PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
+	PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
+	PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
+	PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
+	PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
+	PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
+	PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
+	PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
+	PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
+	PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
+	PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
+	PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
+	PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
+	PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
+	PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
+	PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
+	PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
+	PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
+	PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
+	PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
+	PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
+	PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
+	PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
+	PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
+	PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
+	PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
+	PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
+	PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
+	PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
+	PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
+	PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
+	PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
+	PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
+	PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
+	PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
+	PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
+	PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
+	PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
+	PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
+	PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
+	PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
+	PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
+	PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
+	PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
+	PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
+	PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
+	PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
+	PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
+	PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
+	PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
+	PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
+	PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
+	PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
+	PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
+	PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
+	PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
+	PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
+	PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
+	PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
+	PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
+};
+
+#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
+			.pin_base = b, .npins = c }
+
+/*
+ * This matches the 32-pin gpio chips registered by the GPIO portion. This
+ * cannot be const since we assign the struct gpio_chip * pointer at runtime.
+ */
+static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
+	DB8540_GPIO_RANGE(0, 0, 18),
+	DB8540_GPIO_RANGE(0, 22, 7),
+	DB8540_GPIO_RANGE(1, 33, 6),
+	DB8540_GPIO_RANGE(2, 64, 4),
+	DB8540_GPIO_RANGE(2, 70, 18),
+	DB8540_GPIO_RANGE(3, 116, 12),
+	DB8540_GPIO_RANGE(4, 128, 32),
+	DB8540_GPIO_RANGE(5, 160, 9),
+	DB8540_GPIO_RANGE(6, 192, 23),
+	DB8540_GPIO_RANGE(6, 219, 5),
+	DB8540_GPIO_RANGE(7, 224, 9),
+	DB8540_GPIO_RANGE(8, 256, 12),
+};
+
+/*
+ * Read the pin group names like this:
+ * u0_a_1    = first groups of pins for uart0 on alt function a
+ * i2c2_b_2  = second group of pins for i2c2 on alt function b
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* Altfunction A column */
+static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
+					DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+/* Image processor I2C line, this is driven by image processor firmware */
+static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
+	DB8540_PIN_AC4 };
+static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
+	DB8540_PIN_AE7 };
+/* Basic pins of the MMC/SD card 0 interface */
+static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+	DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
+/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
+
+static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
+static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
+/* LCD interface */
+static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25 };
+static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28 };
+/* D8 thru D11 often used as TVOUT lines */
+static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27 };
+static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
+static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
+	DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
+	DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
+	DB8540_PIN_AG24 };
+static const unsigned ssp1_a_1_pins[] = {  DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+	DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
+/*
+ * Image processor GPIO pins are named "ipgpio" and have their own
+ * numberspace
+ */
+static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
+/* modem i2s interface */
+static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
+	DB8540_PIN_AC28, DB8540_PIN_AC26 };
+static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
+	DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
+	DB8540_PIN_AF18 };
+static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
+static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
+	DB8540_PIN_H2 };
+static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
+	DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
+	DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
+	DB8540_PIN_D8 };
+static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
+	DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+	DB8540_PIN_C9 };
+/* mc1_a_2_pins exclude MC1_FBCLK */
+static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3,	DB8540_PIN_C7,
+	DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+	DB8540_PIN_C9 };
+static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+	DB8540_PIN_D9 };
+static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
+static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned clkout_a_1_pins[] = { DB8540_PIN_D11, DB8540_PIN_AJ6 };
+static const unsigned clkout_a_2_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
+static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
+	DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
+	DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
+	DB8540_PIN_B17, DB8540_PIN_D17 };
+/* Altfunction B colum */
+static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
+static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
+static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+	DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
+	DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
+	DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
+	DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
+	DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
+static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+	DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
+	DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
+	DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
+	DB8540_PIN_AD25 };
+static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
+static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
+static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
+static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
+static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
+	DB8540_PIN_AE19 };
+static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
+static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
+	DB8540_PIN_AE17 };
+static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
+	DB8540_PIN_C8, DB8540_PIN_C9 };
+static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+	DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
+	DB8540_PIN_B12 };
+static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
+static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
+static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
+static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
+
+/* Altfunction C column */
+static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
+static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
+static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
+static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
+static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
+static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
+	DB8540_PIN_AF5, DB8540_PIN_AG4 };
+static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
+	DB8540_PIN_AE21 };
+static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
+static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
+static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
+static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
+static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
+static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
+static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
+static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22 };
+static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
+static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+	DB8540_PIN_AJ21};
+static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
+static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
+static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
+static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
+static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
+static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+	DB8540_PIN_AH24 };
+static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
+	DB8540_PIN_AH17 };
+static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+
+/* Other alt C1 column */
+static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
+	DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+	DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
+static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
+	DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
+	DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
+	DB8540_PIN_T25};
+static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_T26 };
+static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
+static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
+static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
+
+/* Other alt C2 column */
+static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+	DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
+	DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
+	DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
+static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
+static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
+	DB8540_PIN_AE23 };
+static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
+static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
+	DB8540_PIN_AE24 };
+
+/* Other alt C3 column */
+static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+
+/* Other alt C4 column */
+static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
+	DB8540_PIN_T27 };
+static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
+	DB8540_PIN_AF21 };
+static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
+	DB8540_PIN_AH22 };
+static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
+	DB8540_PIN_AH21 };
+static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
+
+#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,		\
+			.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct nmk_pingroup nmk_db8540_groups[] = {
+	/* Altfunction A column */
+	DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
+	/* Altfunction B column */
+	DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
+	/* Altfunction C column */
+	DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C1 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C2 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C3 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C4 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
+
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define DB8540_FUNC_GROUPS(a, b...)	   \
+static const char * const a##_groups[] = { b };
+
+DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
+DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout_a_1", "clkout_a_2");
+DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
+DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
+DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
+DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
+DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
+DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
+DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
+DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
+DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
+DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
+DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
+/* The image processor has 8 GPIO pins that can be muxed out */
+DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
+		"ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
+		"ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
+		"ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
+		"ipgpio4_c_1", "ipgpio4_c_2",
+		"ipgpio5_c_1", "ipgpio5_c_2",
+		"ipgpio6_c_1", "ipgpio6_c_2",
+		"ipgpio7_b_1", "ipgpio7_c_1");
+DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
+DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
+DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
+		"lcdvsi0_a_1", "lcdvsi1_a_1");
+DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
+DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
+DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
+DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
+DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
+DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
+DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
+DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
+		"modaccgpo_oc3_1");
+DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
+		"modaccuartrtccts_oc4_1");
+DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
+DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
+		"modobspwrctrl_oc1_1", "modobspwrrst_c_1",
+		"modobsrefclk_oc1_1", "modobsresout_c_1",
+		"modobsresout_oc1_1", "modobsservice_oc2_1");
+DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
+DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
+DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
+DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
+DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
+		"moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
+DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
+		"moduartstmmux_oc4_1");
+DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
+/*
+ * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
+ * switched around by selecting the altfunction A or B.
+ */
+DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
+		"msp0txrx_b_1");
+DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
+DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
+DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
+DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
+DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
+DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
+/* Select between CS0 on alt B or PS1 on alt C */
+DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
+		"smps0_c_1", "smps1_c_1");
+DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
+DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
+DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
+DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
+DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
+DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
+DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
+DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
+DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
+DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
+DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
+DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
+		"u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
+		"u2txrx_oc1_1");
+DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
+DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
+DB8540_FUNC_GROUPS(usb, "usb_a_1");
+
+
+#define FUNCTION(fname)					\
+	{						\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+static const struct nmk_function nmk_db8540_functions[] = {
+	FUNCTION(apetrig),
+	FUNCTION(clkout),
+	FUNCTION(ddrtrig),
+	FUNCTION(hsi),
+	FUNCTION(hwobs),
+	FUNCTION(hx),
+	FUNCTION(i2c0),
+	FUNCTION(i2c1),
+	FUNCTION(i2c2),
+	FUNCTION(i2c3),
+	FUNCTION(i2c4),
+	FUNCTION(i2c5),
+	FUNCTION(i2c6),
+	FUNCTION(ipgpio),
+	FUNCTION(ipi2c),
+	FUNCTION(kp),
+	FUNCTION(lcd),
+	FUNCTION(lcdb),
+	FUNCTION(mc0),
+	FUNCTION(mc1),
+	FUNCTION(mc2),
+	FUNCTION(mc3),
+	FUNCTION(mc4),
+	FUNCTION(mc5),
+	FUNCTION(modaccgpo),
+	FUNCTION(modaccuart),
+	FUNCTION(modi2s),
+	FUNCTION(modobs),
+	FUNCTION(modprcmudbg),
+	FUNCTION(modrf),
+	FUNCTION(modsmb),
+	FUNCTION(modtrig),
+	FUNCTION(moduart),
+	FUNCTION(modxmip),
+	FUNCTION(msp0),
+	FUNCTION(msp1),
+	FUNCTION(msp2),
+	FUNCTION(msp4),
+	FUNCTION(pwl),
+	FUNCTION(remap),
+	FUNCTION(sbag),
+	FUNCTION(sm),
+	FUNCTION(spi0),
+	FUNCTION(spi1),
+	FUNCTION(spi2),
+	FUNCTION(spi3),
+	FUNCTION(ssp0),
+	FUNCTION(ssp1),
+	FUNCTION(stmape),
+	FUNCTION(stmmod),
+	FUNCTION(tpui),
+	FUNCTION(u0),
+	FUNCTION(u1),
+	FUNCTION(u2),
+	FUNCTION(u3),
+	FUNCTION(u4),
+	FUNCTION(usb)
+};
+
+static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
+	.gpio_ranges = nmk_db8540_ranges,
+	.gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
+	.pins = nmk_db8540_pins,
+	.npins = ARRAY_SIZE(nmk_db8540_pins),
+	.functions = nmk_db8540_functions,
+	.nfunctions = ARRAY_SIZE(nmk_db8540_functions),
+	.groups = nmk_db8540_groups,
+	.ngroups = ARRAY_SIZE(nmk_db8540_groups),
+};
+
+void __devinit
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+	*soc = &nmk_db8540_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 53b0d49..736a160 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1722,6 +1722,8 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
 	/* Poke in other ASIC variants here */
 	if (version == PINCTRL_NMK_DB8500)
 		nmk_pinctrl_db8500_init(&npct->soc);
+	if (platid->driver_data == PINCTRL_NMK_DB8540)
+		nmk_pinctrl_db8540_init(&npct->soc);
 
 	/*
 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
@@ -1773,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
 static const struct platform_device_id nmk_pinctrl_id[] = {
 	{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
 	{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
+	{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
 };
 
 static struct platform_driver nmk_pinctrl_driver = {
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bc91aed..e88320f 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -6,6 +6,7 @@
 /* Package definitions */
 #define PINCTRL_NMK_STN8815	0
 #define PINCTRL_NMK_DB8500	1
+#define PINCTRL_NMK_DB8540	2
 
 /**
  * struct nmk_function - Nomadik pinctrl mux function
@@ -74,4 +75,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
 
 #endif
 
+#ifdef CONFIG_PINCTRL_DB8540
+
+void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
 #endif /* PINCTRL_PINCTRL_NOMADIK_H */
-- 
1.7.11.3



From balbi at ti.com  Tue Aug  7 08:11:08 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue,  7 Aug 2012 15:11:08 +0300
Subject: [PATCH] i2c: omap: switch over to autosuspend API
In-Reply-To: <20120807120728.GW8468@arwen.pp.htv.fi>
References: <20120807120728.GW8468@arwen.pp.htv.fi>
Message-ID: <1344341468-8144-1-git-send-email-balbi@ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message been started
soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 60928f2..c210b45 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -645,7 +645,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1114,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, 1000);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1189,7 +1193,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.12.rc0



From laurent.pinchart at ideasonboard.com  Tue Aug  7 08:15:06 2012
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Tue, 07 Aug 2012 14:15:06 +0200
Subject: [PATCH v3 4/4] fbdev: sh_mobile_lcdc: use dma_mmap_coherent if
 available
In-Reply-To: <1854100.yBXTHaXkcr@avalon>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-5-git-send-email-hdk@igel.co.jp>
 <1854100.yBXTHaXkcr@avalon>
Message-ID: <3107106.PmlicBoqLd@avalon>

On Tuesday 07 August 2012 14:01:43 Laurent Pinchart wrote:
> Hi Eiraku-san,
> 
> On Monday 06 August 2012 18:55:24 Hideki EIRAKU wrote:
> > fb_mmap() implemented in fbmem.c uses smem_start as the physical
> > address of the frame buffer.  In the sh_mobile_lcdc driver, the
> > smem_start is a dma_addr_t that is not a physical address when IOMMU is
> > enabled.  dma_mmap_coherent() maps the address correctly.  It is
> > available on ARM platforms.
> > 
> > Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
> 
> Acked-by: Hideki EIRAKU <hdk at igel.co.jp>

I obviously meant

Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

> As this patch doesn't depend on any other patch in your series
> (ARCH_HAS_DMA_MMAP_COHERENT will not be defined without 1/4, so this patch
> will be a no-op until then), I've applied it to my tree and will push it to
> avoid merge conflicts, unless you would prefer to push it yourself.
> 
> > ---
> > 
> >  drivers/video/sh_mobile_lcdcfb.c |   28 ++++++++++++++++++++++++++++
> >  1 files changed, 28 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/video/sh_mobile_lcdcfb.c
> > b/drivers/video/sh_mobile_lcdcfb.c index 8cb653b..c8cba7a 100644
> > --- a/drivers/video/sh_mobile_lcdcfb.c
> > +++ b/drivers/video/sh_mobile_lcdcfb.c
> > @@ -1614,6 +1614,17 @@ static int sh_mobile_lcdc_overlay_blank(int blank,
> > struct fb_info *info) return 1;
> > 
> >  }
> > 
> > +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> > +static int
> > +sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct
> > *vma) +{
> > +	struct sh_mobile_lcdc_overlay *ovl = info->par;
> > +
> > +	return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
> > +				 ovl->dma_handle, ovl->fb_size);
> > +}
> > +#endif
> > +
> > 
> >  static struct fb_ops sh_mobile_lcdc_overlay_ops = {
> >  
> >  	.owner          = THIS_MODULE,
> >  	.fb_read        = fb_sys_read,
> > 
> > @@ -1626,6 +1637,9 @@ static struct fb_ops sh_mobile_lcdc_overlay_ops = {
> > 
> >  	.fb_ioctl       = sh_mobile_lcdc_overlay_ioctl,
> >  	.fb_check_var	= sh_mobile_lcdc_overlay_check_var,
> >  	.fb_set_par	= sh_mobile_lcdc_overlay_set_par,
> > 
> > +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> > +	.fb_mmap	= sh_mobile_lcdc_overlay_mmap,
> > +#endif
> > 
> >  };
> >  
> >  static void
> > 
> > @@ -2093,6 +2107,17 @@ static int sh_mobile_lcdc_blank(int blank, struct
> > fb_info *info) return 0;
> > 
> >  }
> > 
> > +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> > +static int
> > +sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
> > +{
> > +	struct sh_mobile_lcdc_chan *ch = info->par;
> > +
> > +	return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
> > +				 ch->dma_handle, ch->fb_size);
> > +}
> > +#endif
> > +
> > 
> >  static struct fb_ops sh_mobile_lcdc_ops = {
> >  
> >  	.owner          = THIS_MODULE,
> >  	.fb_setcolreg	= sh_mobile_lcdc_setcolreg,
> > 
> > @@ -2108,6 +2133,9 @@ static struct fb_ops sh_mobile_lcdc_ops = {
> > 
> >  	.fb_release	= sh_mobile_lcdc_release,
> >  	.fb_check_var	= sh_mobile_lcdc_check_var,
> >  	.fb_set_par	= sh_mobile_lcdc_set_par,
> > 
> > +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> > +	.fb_mmap	= sh_mobile_lcdc_mmap,
> > +#endif
> > 
> >  };
> >  
> >  static void
-- 
Regards,

Laurent Pinchart



From l.krishna at samsung.com  Tue Aug  7 08:34:30 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 18:04:30 +0530
Subject: [PATCH V4 0/2] arm: samsung: Move FIMD headers to include/video/
Message-ID: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>

This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch side
to include/video/samsung_fimd.h

This patchset is created and rebased against master branch of torvalds tree.
Tested on smdk5250 board, build tested for other boards.

Changes from version 3:
	- Squashed 1st, 3rd, 4th and 5th patches from version 3

Changes from version 2:
	- Changed the EXYNOS5_xxx macro name to FIMD_V8_xxx
	- Moved the header inclusion under same kind

Changes from version 1:
	- Split the patches as per Sylwester comments
	- Changed FIMD_V8_xxx macro to EXYNOS5_xxx	

Leela Krishna Amudala (2):
  include/video: move fimd register headers from platform to
    include/video
  include/video: Add register offsets for FIMD version 8

 arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
 arch/arm/mach-exynos/mach-origen.c                 |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --------------------
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/video/s3c-fb.c                             |    2 +-
 .../plat/regs-fb.h => include/video/samsung_fimd.h |  152 +++++++++++++++++--
 26 files changed, 165 insertions(+), 194 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 rename arch/arm/plat-samsung/include/plat/regs-fb.h => include/video/samsung_fimd.h (73%)



From l.krishna at samsung.com  Tue Aug  7 08:34:31 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 18:04:31 +0530
Subject: [PATCH V4 1/2] include/video: move fimd register headers from platform
 to include/video
In-Reply-To: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344342872-7904-2-git-send-email-l.krishna@samsung.com>

This patch moves the contents from regs-fb-v4.h and regs-fb.h to
include/video/samsung_fimd.h. Also updates the header inclusion in
machine files and driver files accordingly.

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
 arch/arm/mach-exynos/mach-origen.c                 |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --------------------
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/video/s3c-fb.c                             |    2 +-
 .../plat/regs-fb.h => include/video/samsung_fimd.h |  145 ++++++++++++++++--
 26 files changed, 158 insertions(+), 194 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 rename arch/arm/plat-samsung/include/plat/regs-fb.h => include/video/samsung_fimd.h (74%)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fc..90d8daa 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -29,6 +29,7 @@
 #include <drm/exynos_drm.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <media/m5mols.h>
 #include <media/s5k6aa.h>
 #include <media/s5p_fimc.h>
@@ -39,7 +40,6 @@
 #include <asm/mach-types.h>
 
 #include <plat/adc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5ca8030..4e245f1 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -29,9 +29,9 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index b26beb1..ee069b4 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -26,6 +26,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/backlight.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -35,7 +36,6 @@
 #include <plat/iic.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb.h>
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
 
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 3cfa688..b1c50da 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -26,9 +26,9 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 4d1f40d..8139cd2 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -30,6 +30,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
@@ -39,7 +40,6 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
 #include <plat/camport.h>
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
index 07a6dbe..5665bb4 100644
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -13,8 +13,8 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
 
+#include <video/samsung_fimd.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include <mach/map.h>
 
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index c3100a0..96478f0 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -29,6 +29,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -52,7 +53,6 @@
 #include <plat/udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
 
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 
 #include <plat/common-smdk.h>
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ffa29dd..f7a108b 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -29,6 +29,7 @@
 #include <linux/dm9000.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -44,7 +45,6 @@
 #include <plat/regs-serial.h>
 #include <plat/iic.h>
 #include <plat/fb.h>
-#include <plat/regs-fb-v4.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..0f882f9 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -46,6 +46,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 
@@ -57,7 +58,6 @@
 #include <mach/regs-gpio-memport.h>
 
 #include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 6890881..8ad0bfc 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -26,6 +26,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 
@@ -41,7 +42,6 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 5539a25..96ebcc5 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,9 +41,9 @@
 #include <plat/nand.h>
 #include <plat/regs-serial.h>
 #include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cad2e05..48599bc 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -43,7 +44,6 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 326b216..76d3ffb 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,9 +42,9 @@
 #include <plat/nand.h>
 #include <plat/regs-serial.h>
 #include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index d6266d8..96d6da2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 0957d2a..7d1167b 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -21,6 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 
@@ -28,7 +29,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 #include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..d1378d7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -43,6 +43,7 @@
 #endif
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -72,7 +73,6 @@
 #include <plat/ts.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 92fefad..5d0b36e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -52,7 +53,6 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e2335ec..7522fb9 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -27,6 +27,7 @@
 #include <linux/mmc/host.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -52,7 +53,6 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
-#include <plat/regs-fb.h>
 #include <plat/sdhci.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0c3ae38..c3dcafa 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -33,6 +33,7 @@
 #include <mach/regs-gpio.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -51,7 +52,6 @@
 #include <plat/ts.h>
 #include <plat/audio.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 78028df..ee9fa5c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -28,6 +28,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 
@@ -39,7 +40,6 @@
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
 #include <plat/s5p-time.h>
-#include <plat/regs-fb-v4.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 822a559..c552581 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -35,6 +35,7 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 
@@ -49,7 +50,6 @@
 #include <plat/clock.h>
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/camport.h>
 
 #include <media/v4l2-mediabus.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 918b23d..9bfbedf 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -28,6 +28,7 @@
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>
+#include <video/samsung_fimd.h>
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -46,7 +47,6 @@
 #include <plat/fb.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
 
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben at simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards and specifically the S3C64XX series
- * S3C6400 and S3C6410.
- *
- * The file contains the cpu specific items which change between whichever
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* include the core definitions here, in case we really do need to
- * override them at a later date.
-*/
-
-#include <plat/regs-fb.h>
-
-#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN	(1 << 15)
-
-/* Video timing controls */
-#define VIDTCON0				(0x10)
-#define VIDTCON1				(0x14)
-#define VIDTCON2				(0x18)
-
-/* Window position controls */
-
-#define WINCON(_win)				(0x20 + ((_win) * 4))
-
-/* OSD1 and OSD4 do not have register D */
-
-#define VIDOSD_BASE				(0x40)
-
-#define VIDINTCON0				(0x130)
-
-/* WINCONx */
-
-#define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT			(26)
-#define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
-
-#define WINCONx_ENLOCAL				(1 << 22)
-#define WINCONx_BUFSTATUS			(1 << 21)
-#define WINCONx_BUFSEL				(1 << 20)
-#define WINCONx_BUFAUTOEN			(1 << 19)
-#define WINCONx_YCbCr				(1 << 13)
-
-#define WINCON1_LOCALSEL_CAMIF			(1 << 23)
-
-#define WINCON2_LOCALSEL_CAMIF			(1 << 23)
-#define WINCON2_BLD_PIX				(1 << 6)
-
-#define WINCON2_ALPHA_SEL			(1 << 1)
-#define WINCON2_BPPMODE_MASK			(0xf << 2)
-#define WINCON2_BPPMODE_SHIFT			(2)
-#define WINCON2_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON2_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON2_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232		(0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555		(0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555		(0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665		(0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666		(0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888		(0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887		(0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888		(0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888		(0xd << 2)
-
-#define WINCON3_BLD_PIX				(1 << 6)
-
-#define WINCON3_ALPHA_SEL			(1 << 1)
-#define WINCON3_BPPMODE_MASK			(0xf << 2)
-#define WINCON3_BPPMODE_SHIFT			(2)
-#define WINCON3_BPPMODE_1BPP			(0x0 << 2)
-#define WINCON3_BPPMODE_2BPP			(0x1 << 2)
-#define WINCON3_BPPMODE_4BPP			(0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565		(0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555		(0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555		(0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666		(0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665		(0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666		(0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888		(0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887		(0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888		(0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888		(0xd << 2)
-
-#define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)
-
-#define DITHMODE				(0x170)
-#define WINxMAP(_win)				(0x180 + ((_win) * 4))
-
-
-#define DITHMODE_R_POS_MASK			(0x3 << 5)
-#define DITHMODE_R_POS_SHIFT			(5)
-#define DITHMODE_R_POS_8BIT			(0x0 << 5)
-#define DITHMODE_R_POS_6BIT			(0x1 << 5)
-#define DITHMODE_R_POS_5BIT			(0x2 << 5)
-
-#define DITHMODE_G_POS_MASK			(0x3 << 3)
-#define DITHMODE_G_POS_SHIFT			(3)
-#define DITHMODE_G_POS_8BIT			(0x0 << 3)
-#define DITHMODE_G_POS_6BIT			(0x1 << 3)
-#define DITHMODE_G_POS_5BIT			(0x2 << 3)
-
-#define DITHMODE_B_POS_MASK			(0x3 << 1)
-#define DITHMODE_B_POS_SHIFT			(1)
-#define DITHMODE_B_POS_8BIT			(0x0 << 1)
-#define DITHMODE_B_POS_6BIT			(0x1 << 1)
-#define DITHMODE_B_POS_5BIT			(0x2 << 1)
-
-#define DITHMODE_DITH_EN			(1 << 0)
-
-#define WPALCON					(0x1A0)
-
-/* Palette control */
-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
-#define WPALCON_W4PAL_16BPP_A555		(1 << 8)
-#define WPALCON_W3PAL_16BPP_A555		(1 << 7)
-#define WPALCON_W2PAL_16BPP_A555		(1 << 6)
-
-
-/* Notes on per-window bpp settings
- *
- * Value	Win0	 Win1	  Win2	   Win3	    Win 4
- * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
- * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
- * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
- * 0011		8(P)	 8(P)     -none-   -none-   -none-
- * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
- * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
- * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
- * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
- * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
- * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
- * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
- * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
- * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
- * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
- * 1110		-none-	 -none-	  -none-   -none-    -none-
- * 1111		-none-	 -none-   -none-   -none-    -none-
-*/
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index a68d2b3..24c0bd4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -19,8 +19,8 @@
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
 
+#include <video/samsung_fimd.h>
 #include <drm/exynos_drm.h>
-#include <plat/regs-fb-v4.h>
 
 #include "exynos_drm_drv.h"
 #include "exynos_drm_fbdev.h"
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 69bf9d0..901729e 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -25,8 +25,8 @@
 #include <linux/interrupt.h>
 #include <linux/pm_runtime.h>
 
+#include <video/samsung_fimd.h>
 #include <mach/map.h>
-#include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
 
 /* This driver will export a number of framebuffer interfaces depending
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/include/video/samsung_fimd.h
similarity index 74%
rename from arch/arm/plat-samsung/include/plat/regs-fb.h
rename to include/video/samsung_fimd.h
index 9a78012..e979f42 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/include/video/samsung_fimd.h
@@ -1,13 +1,13 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb.h
+/* include/video/samsung_fimd.h
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben at simtec.co.uk>
  *
- * S3C Platform - new-style framebuffer register definitions
+ * S3C Platform - new-style fimd and framebuffer register definitions
  *
- * This is the register set for the new style framebuffer interface
+ * This is the register set for the fimd and new style framebuffer interface
  * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
  * S3C64XX series such as the S3C6400 and S3C6410.
  *
@@ -15,19 +15,11 @@
  * whichever architecture is selected, it only contains the core of the
  * register set. See <mach/regs-fb.h> to get the specifics.
  *
- * Note, we changed to using regs-fb.h as it avoids any clashes with
- * the original regs-lcd.h so out of the way of regs-lcd.h as well as
- * indicating the newer block is much more than just an LCD interface.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-/* Please do not include this file directly, use <mach/regs-fb.h> to
- * ensure all the localised SoC support is included as necessary.
-*/
-
 /* VIDCON0 */
 
 #define VIDCON0					(0x00)
@@ -401,3 +393,134 @@
 #define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
 #define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
 
+#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN	(1 << 15)
+
+/* Video timing controls */
+#define VIDTCON0				(0x10)
+#define VIDTCON1				(0x14)
+#define VIDTCON2				(0x18)
+
+/* Window position controls */
+
+#define WINCON(_win)				(0x20 + ((_win) * 4))
+
+/* OSD1 and OSD4 do not have register D */
+
+#define VIDOSD_BASE				(0x40)
+
+#define VIDINTCON0				(0x130)
+
+/* WINCONx */
+
+#define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT			(26)
+#define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
+
+#define WINCONx_ENLOCAL				(1 << 22)
+#define WINCONx_BUFSTATUS			(1 << 21)
+#define WINCONx_BUFSEL				(1 << 20)
+#define WINCONx_BUFAUTOEN			(1 << 19)
+#define WINCONx_YCbCr				(1 << 13)
+
+#define WINCON1_LOCALSEL_CAMIF			(1 << 23)
+
+#define WINCON2_LOCALSEL_CAMIF			(1 << 23)
+#define WINCON2_BLD_PIX				(1 << 6)
+
+#define WINCON2_ALPHA_SEL			(1 << 1)
+#define WINCON2_BPPMODE_MASK			(0xf << 2)
+#define WINCON2_BPPMODE_SHIFT			(2)
+#define WINCON2_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON2_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON2_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232		(0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555		(0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555		(0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665		(0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666		(0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888		(0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887		(0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888		(0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888		(0xd << 2)
+
+#define WINCON3_BLD_PIX				(1 << 6)
+
+#define WINCON3_ALPHA_SEL			(1 << 1)
+#define WINCON3_BPPMODE_MASK			(0xf << 2)
+#define WINCON3_BPPMODE_SHIFT			(2)
+#define WINCON3_BPPMODE_1BPP			(0x0 << 2)
+#define WINCON3_BPPMODE_2BPP			(0x1 << 2)
+#define WINCON3_BPPMODE_4BPP			(0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565		(0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555		(0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555		(0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666		(0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665		(0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666		(0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888		(0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887		(0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888		(0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888		(0xd << 2)
+
+#define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)
+
+#define DITHMODE				(0x170)
+#define WINxMAP(_win)				(0x180 + ((_win) * 4))
+
+
+#define DITHMODE_R_POS_MASK			(0x3 << 5)
+#define DITHMODE_R_POS_SHIFT			(5)
+#define DITHMODE_R_POS_8BIT			(0x0 << 5)
+#define DITHMODE_R_POS_6BIT			(0x1 << 5)
+#define DITHMODE_R_POS_5BIT			(0x2 << 5)
+
+#define DITHMODE_G_POS_MASK			(0x3 << 3)
+#define DITHMODE_G_POS_SHIFT			(3)
+#define DITHMODE_G_POS_8BIT			(0x0 << 3)
+#define DITHMODE_G_POS_6BIT			(0x1 << 3)
+#define DITHMODE_G_POS_5BIT			(0x2 << 3)
+
+#define DITHMODE_B_POS_MASK			(0x3 << 1)
+#define DITHMODE_B_POS_SHIFT			(1)
+#define DITHMODE_B_POS_8BIT			(0x0 << 1)
+#define DITHMODE_B_POS_6BIT			(0x1 << 1)
+#define DITHMODE_B_POS_5BIT			(0x2 << 1)
+
+#define DITHMODE_DITH_EN			(1 << 0)
+
+#define WPALCON					(0x1A0)
+
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555		(1 << 8)
+#define WPALCON_W3PAL_16BPP_A555		(1 << 7)
+#define WPALCON_W2PAL_16BPP_A555		(1 << 6)
+
+
+/* Notes on per-window bpp settings
+ *
+ * Value	Win0	 Win1	  Win2	   Win3	    Win 4
+ * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
+ * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
+ * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
+ * 0011		8(P)	 8(P)     -none-   -none-   -none-
+ * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
+ * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
+ * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
+ * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
+ * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
+ * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
+ * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
+ * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
+ * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
+ * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
+ * 1110		-none-	 -none-	  -none-   -none-    -none-
+ * 1111		-none-	 -none-   -none-   -none-    -none-
+*/
-- 
1.7.0.4



From l.krishna at samsung.com  Tue Aug  7 08:34:32 2012
From: l.krishna at samsung.com (Leela Krishna Amudala)
Date: Tue, 07 Aug 2012 18:04:32 +0530
Subject: [PATCH V4 2/2] include/video: Add register offsets for FIMD version 8
In-Reply-To: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
Message-ID: <1344342872-7904-3-git-send-email-l.krishna@samsung.com>

FIMD version 8 has VIDTCON and VIDCON registers at different offsets
from the previous versions. Hence, adding the macros.

Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
---
 include/video/samsung_fimd.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index e979f42..7ae6c07 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -524,3 +524,10 @@
  * 1110		-none-	 -none-	  -none-   -none-    -none-
  * 1111		-none-	 -none-   -none-   -none-    -none-
 */
+
+/* FIMD Version 8 register offset definitions */
+#define FIMD_V8_VIDTCON0	(0x20010)
+#define FIMD_V8_VIDTCON1	(0x20014)
+#define FIMD_V8_VIDTCON2	(0x20018)
+#define FIMD_V8_VIDTCON3	(0x2001C)
+#define FIMD_V8_VIDCON1		(0x20004)
-- 
1.7.0.4



From linus.walleij at linaro.org  Tue Aug  7 08:21:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 14:21:08 +0200
Subject: [PATCH] pinctrl-sirf: remove devm_kfree at error path
In-Reply-To: <1343549498-2217-1-git-send-email-develkernel412222@gmail.com>
References: <1343549498-2217-1-git-send-email-develkernel412222@gmail.com>
Message-ID: <CACRpkdY8zD_14CTGjhXhNMhpb=e5ZJU53xd00=4gQgfZn0WJ=A@mail.gmail.com>

On Sun, Jul 29, 2012 at 10:11 AM, Devendra Naga
<develkernel412222 at gmail.com> wrote:

> the pointers that are allocated with devm_kzalloc will be automatically freed,
> at unload time.
>
> Signed-off-by: Devendra Naga <develkernel412222 at gmail.com>

Applied, Barry if you don't like this, shout now :-)

Yours,
Linus Walleij


From burman.yan at gmail.com  Tue Aug  7 07:21:14 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Tue, 07 Aug 2012 14:21:14 +0300
Subject: [PATCH] ARM: ep93xx: clockevent support
Message-ID: <1344338474.18237.6.camel@localhost>

ARM: ep93xx: clockevent support
I have ported to 3.6-rc1 and slightly modified a previous patch for clockevent support for the ep93xx.
The porting mainly consists of sched_clock support.
Tested on 9302 based board.
From: Ahmed Ammar <aammar <at> edge-techno.com>
Signed-off-by: Yan Burman <burman.yan at gmail.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..6dbb828 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -451,7 +451,7 @@ config ARCH_EP93XX
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_USES_GETTIMEOFFSET
+	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_MEMORY_H
 	help
 	  This enables support for the Cirrus EP93xx series of CPUs.
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4afe52a..1497cba 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -30,6 +30,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/mtd/physmap.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -43,6 +45,7 @@
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 
 #include <asm/hardware/vic.h>
 
@@ -114,63 +117,129 @@ void __init ep93xx_map_io(void)
 #define EP93XX_TIMER4_CLOCK		983040
 
 #define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
-#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
-
-static unsigned int last_jiffy_time;
 
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
-	/* Writing any value clears the timer interrupt */
-	__raw_writel(1, EP93XX_TIMER1_CLEAR);
+	struct clock_event_device *evt = dev_id;
 
-	/* Recover lost jiffies */
-	while ((signed long)
-		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
-						>= TIMER4_TICKS_PER_JIFFY) {
-		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
-		timer_tick();
-	}
+	__raw_writel(1, EP93XX_TIMER1_CLEAR);
+	evt->event_handler(evt);
 
 	return IRQ_HANDLED;
 }
 
+static int ep93xx_set_next_event(unsigned long evt,
+				struct clock_event_device *unused)
+{
+	u32 tmode = __raw_readl(EP93XX_TIMER1_CONTROL);
+
+	/* stop timer */
+	__raw_writel(tmode & ~EP93XX_TIMER123_CONTROL_ENABLE,
+			EP93XX_TIMER1_CONTROL);
+	/* program timer */
+	__raw_writel(evt, EP93XX_TIMER1_LOAD);
+	/* start timer */
+	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+			EP93XX_TIMER1_CONTROL);
+
+	return 0;
+}
+
+static void ep93xx_set_mode(enum clock_event_mode mode,
+			    struct clock_event_device *evt)
+{
+	u32 tmode = EP93XX_TIMER123_CONTROL_CLKSEL;
+	/* Disable timer */
+	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		/* Set timer period  */
+		__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
+		tmode |= EP93XX_TIMER123_CONTROL_MODE;
+
+	case CLOCK_EVT_MODE_ONESHOT:
+		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
+		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+		break;
+
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+		return;
+	}
+}
+
+static struct clock_event_device clockevent_ep93xx = {
+	.name		= "ep93xx-timer1",
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.shift		= 32,
+	.set_mode	= ep93xx_set_mode,
+	.set_next_event	= ep93xx_set_next_event,
+};
+
 static struct irqaction ep93xx_timer_irq = {
 	.name		= "ep93xx timer",
 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= ep93xx_timer_interrupt,
+	.dev_id		= &clockevent_ep93xx,
 };
 
-static void __init ep93xx_timer_init(void)
+static void __init ep93xx_clockevent_init(void)
 {
-	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
-		    EP93XX_TIMER123_CONTROL_CLKSEL;
+	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
+	clockevent_ep93xx.mult = div_sc(508469, NSEC_PER_SEC,
+					clockevent_ep93xx.shift);
+	clockevent_ep93xx.max_delta_ns =
+		clockevent_delta2ns(0xfffffffe, &clockevent_ep93xx);
+	clockevent_ep93xx.min_delta_ns =
+		clockevent_delta2ns(0xf, &clockevent_ep93xx);
+	clockevent_ep93xx.cpumask = cpumask_of(0);
+	clockevents_register_device(&clockevent_ep93xx);
+}
 
-	/* Enable periodic HZ timer.  */
-	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
-	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
-	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
-			EP93XX_TIMER1_CONTROL);
+/*
+ * timer4 is a 40 Bit timer, separated in a 32bit and a 8 bit
+ * register, EP93XX_TIMER4_VALUE_LOW stores 32 bit word. The
+ * controlregister is in EP93XX_TIMER4_VALUE_HIGH
+ */
+static cycle_t ep93xx_get_cycles(struct clocksource *unused)
+{
+	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
+}
 
-	/* Enable lost jiffy timer.  */
-	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
-			EP93XX_TIMER4_VALUE_HIGH);
+static struct clocksource clocksource_ep93xx = {
+	.name		= "ep93xx_timer4",
+	.rating		= 200,
+	.read		= ep93xx_get_cycles,
+	.mask		= 0xFFFFFFFF,
+	.shift		= 20,
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
 
-	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
+static void __init ep93xx_clocksource_init(void)
+{
+	/* Reset time-stamp counter */
+	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
+	clocksource_ep93xx.mult =
+		clocksource_hz2mult(983040, clocksource_ep93xx.shift);
+	clocksource_register(&clocksource_ep93xx);
 }
 
-static unsigned long ep93xx_gettimeoffset(void)
+static u32 notrace ep93xx_sched_clock(void)
 {
-	int offset;
-
-	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
+	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
+}
 
-	/* Calculate (1000000 / 983040) * offset.  */
-	return offset + (53 * offset / 3072);
+static void __init ep93xx_timer_init(void)
+{
+	ep93xx_clocksource_init();
+	ep93xx_clockevent_init();
+	setup_sched_clock(ep93xx_sched_clock, 32, CLOCK_TICK_RATE);
 }
 
 struct sys_timer ep93xx_timer = {
 	.init		= ep93xx_timer_init,
-	.offset		= ep93xx_gettimeoffset,
 };
 
 




From burman.yan at gmail.com  Tue Aug  7 07:26:58 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Tue, 07 Aug 2012 14:26:58 +0300
Subject: [PATCH] ARM: ep93xx: Use HW MAC filter in ethernet driver
Message-ID: <1344338818.18237.9.camel@localhost>

ARM: ep93xx: Use HW MAC filter in ethernet driver
Use HW MAC filtering for broadcasts and multicasts.
Do not always work in promiscuous mode.
Partially based on kernel 2.6.20.4 driver from cirrus logic.
Tested on 9302 and 9315 based boards.

Signed-off-by: Yan Burman <burman.yan at gmail.com>

diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..28bdf96 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
 
 #define DRV_MODULE_NAME		"ep93xx-eth"
-#define DRV_MODULE_VERSION	"0.1"
+#define DRV_MODULE_VERSION	"0.2"
 
 #define RX_QUEUE_ENTRIES	64
 #define TX_QUEUE_ENTRIES	8
@@ -38,7 +38,29 @@
 #define PKT_BUF_SIZE		2048
 
 #define REG_RXCTL		0x0000
-#define  REG_RXCTL_DEFAULT	0x00073800
+#define  REG_RXCTL_PauseA  (1<<20)
+#define  REG_RXCTL_RxFCE1  (1<<19)
+#define  REG_RXCTL_RxFCE0  (1<<18)
+#define  REG_RXCTL_BCRC    (1<<17)
+#define  REG_RXCTL_SRxON   (1<<16)
+#define  REG_RXCTL_RCRCA   (1<<13)
+#define  REG_RXCTL_RA      (1<<12)
+#define  REG_RXCTL_PA      (1<<11)
+#define  REG_RXCTL_BA      (1<<10)
+#define  REG_RXCTL_MA      (1<<9)
+#define  REG_RXCTL_IAHA    (1<<8)
+#define  REG_RXCTL_IA3     (1<<3)
+#define  REG_RXCTL_IA2     (1<<2)
+#define  REG_RXCTL_IA1     (1<<1)
+#define  REG_RXCTL_IA0     (1<<0)
+#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
+				REG_RXCTL_RA | \
+				REG_RXCTL_RCRCA | \
+				REG_RXCTL_SRxON | \
+				REG_RXCTL_BCRC | \
+				REG_RXCTL_RxFCE0 | \
+				REG_RXCTL_IA0)
+
 #define REG_TXCTL		0x0004
 #define  REG_TXCTL_ENABLE	0x00000001
 #define REG_MIICMD		0x0010
@@ -57,6 +79,12 @@
 #define  REG_INTSTS_RX		0x00000004
 #define REG_INTSTSC		0x002c
 #define REG_AFP			0x004c
+#define  REG_AFP_AFP_IA0	0
+#define  REG_AFP_AFP_IA1	1
+#define  REG_AFP_AFP_IA2	2
+#define  REG_AFP_AFP_IA3	3
+#define  REG_AFP_AFP_DTxP	6
+#define  REG_AFP_AFP_HASH	7
 #define REG_INDAD0		0x0050
 #define REG_INDAD1		0x0051
 #define REG_INDAD2		0x0052
@@ -386,6 +414,83 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 }
 
+#define CRC_PRIME 0xFFFFFFFF
+#define CRC_POLYNOMIAL 0x04C11DB6
+static unsigned char ep93xx_calculate_hash_index(char *mcast_addr)
+{
+	unsigned long crc;
+	unsigned char hash_idx;
+	unsigned char addr_byte;
+	unsigned char *addr;
+	unsigned long high_bit;
+	int byte;
+	int bit;
+
+	crc = CRC_PRIME;
+	addr = mcast_addr;
+
+	for (byte = 0; byte < 6; byte++) {
+		addr_byte = *addr;
+		addr++;
+
+		for (bit = 8; bit > 0; bit--) {
+			high_bit = crc >> 31;
+			crc <<= 1;
+
+			if (high_bit ^ (addr_byte & 1)) {
+				crc ^= CRC_POLYNOMIAL;
+				crc |= 1;
+			}
+
+			addr_byte >>= 1;
+		}
+	}
+
+	for (bit = 0, hash_idx = 0; bit < 6; bit++) {
+		hash_idx <<= 1;
+		hash_idx |= (unsigned char)(crc & 1);
+		crc >>= 1;
+	}
+
+	return hash_idx;
+}
+
+static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *pBuf)
+{
+	unsigned char position;
+	struct netdev_hw_addr *ha;
+
+	netdev_hw_addr_list_for_each(ha, &dev->mc) {
+		if (ha->addr[0] & 1)
+			continue;
+		position = ep93xx_calculate_hash_index(ha->addr);
+		pBuf[position >> 3] |= 1 << (position & 0x07);
+	}
+}
+
+static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *pBuf)
+{
+	u32 rxctl;
+	int i, len;
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	afp &= 0x07;
+	if (afp == 4 || afp == 5) {
+		pr_crit("invalid afp value\n");
+		return -1;
+	}
+	len = (afp == REG_AFP_AFP_HASH) ? 8 : 6;
+
+	rxctl = rdl(ep, REG_RXCTL);
+	wrl(ep, REG_RXCTL, ~REG_RXCTL_SRxON & rxctl);
+	wrl(ep, REG_AFP, afp);
+	for (i = 0; i < len; i++)
+		wrb(ep, REG_INDAD0 + i, pBuf[i]);
+	wrl(ep, REG_RXCTL, rxctl);
+
+	return 0;
+}
+
 static void ep93xx_tx_complete(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -615,13 +720,7 @@ static int ep93xx_start_hw(struct net_device *dev)
 	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
 	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
 
-	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
-	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
-	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
-	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
-	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
-	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
-	wrl(ep, REG_AFP, 0);
+	ep93xx_ind_addr_write(dev, REG_AFP_AFP_IA0, dev->dev_addr);
 
 	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
 
@@ -647,6 +746,31 @@ static void ep93xx_stop_hw(struct net_device *dev)
 		pr_crit("hw failed to reset\n");
 }
 
+static void ep93xx_set_multicast_list(struct net_device *dev)
+{
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	if (dev->flags & IFF_PROMISC) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
+	} else if (dev->flags & IFF_ALLMULTI) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
+		ep93xx_ind_addr_write(dev, REG_AFP_AFP_HASH,
+			      "\xff\xff\xff\xff\xff\xff\xff\xff");
+	} else if (netdev_hw_addr_list_count(&dev->mc)) {
+		u8 tblMulti[8 + 1];
+		memset(tblMulti, 0, sizeof(tblMulti));
+
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
+		ep93xx_set_mcast_tbl(dev, tblMulti);
+		ep93xx_ind_addr_write(dev, REG_AFP_AFP_HASH, tblMulti);
+	} else {
+		wrl(ep, REG_RXCTL,
+			~(REG_RXCTL_PA | REG_RXCTL_MA) & rdl(ep, REG_RXCTL));
+	}
+}
+
 static int ep93xx_open(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -754,6 +878,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_change_mtu		= eth_change_mtu,
 	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
 };
 
 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)




From linus.walleij at linaro.org  Tue Aug  7 08:27:48 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 14:27:48 +0200
Subject: [PATCH 1/2] pinctrl: use ERR_CAST instead of ERR_PTR(PTR_ERR(...))
In-Reply-To: <1343666314-18070-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343666314-18070-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CACRpkda5SO7fVtihxCnSTA39uCcJaFC-o9fZ8x9ExhmSoN6eQg@mail.gmail.com>

On Mon, Jul 30, 2012 at 6:38 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

> This doesn't change semantics, just looks nicer.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Applied for v3.7.

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug  7 08:28:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 7 Aug 2012 14:28:50 +0200
Subject: [PATCH 2/2] MAINTAINERS: fix a few pinctrl related entries
In-Reply-To: <1343666314-18070-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343666314-18070-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1343666314-18070-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CACRpkdZ9zg9XU_ZHB4gy1b1ba+bUrWxPa2nk_5=s8SyNvuyiEg@mail.gmail.com>

On Mon, Jul 30, 2012 at 6:38 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Applied.

Thanks,
Linus Walleij


From vaibhav.bedia at ti.com  Tue Aug  7 08:34:28 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Tue, 7 Aug 2012 12:34:28 +0000
Subject: [PATCH] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344341468-8144-1-git-send-email-balbi@ti.com>
References: <20120807120728.GW8468@arwen.pp.htv.fi>
 <1344341468-8144-1-git-send-email-balbi@ti.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D121433EB3087D@DBDE01.ent.ti.com>

On Tue, Aug 07, 2012 at 17:41:08, Balbi, Felipe wrote:
> this helps us reduce unnecessary pm transitions
> in case we have another i2c message been started
> soon.
>

s/been started/starting ?
 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
>  drivers/i2c/busses/i2c-omap.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 60928f2..c210b45 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -645,7 +645,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>  
>  	omap_i2c_wait_for_bb(dev);
>  out:
> -	pm_runtime_put(dev->dev);
> +	pm_runtime_mark_last_busy(dev->dev);
> +	pm_runtime_put_autosuspend(dev->dev);
>  	return r;
>  }
>  
> @@ -1113,6 +1114,9 @@ omap_i2c_probe(struct platform_device *pdev)
>  		dev->regs = (u8 *)reg_map_ip_v1;
>  
>  	pm_runtime_enable(dev->dev);
> +	pm_runtime_set_autosuspend_delay(dev->dev, 1000);

I guess there will always be a debate around what's the right
delay for autosuspend ;)

You can at least replace the magic number with a macro.

> +	pm_runtime_use_autosuspend(dev->dev);
> +
>  	r = pm_runtime_get_sync(dev->dev);
>  	if (IS_ERR_VALUE(r))
>  		goto err_free_mem;
> @@ -1189,7 +1193,8 @@ omap_i2c_probe(struct platform_device *pdev)
>  
>  	of_i2c_register_devices(adap);
>  
> -	pm_runtime_put(dev->dev);
> +	pm_runtime_mark_last_busy(dev->dev);
> +	pm_runtime_put_autosuspend(dev->dev);
>  
>  	return 0;
>  
> -- 
> 1.7.12.rc0
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From nicolas.ferre at atmel.com  Tue Aug  7 08:34:54 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 14:34:54 +0200
Subject: [PATCH 1/4] ARM: at91: gpio: implement request
In-Reply-To: <1342359637-15325-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120715131618.GF4450@game.jcrosoft.org>
 <1342359637-15325-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <50210B6E.70402@atmel.com>

On 07/15/2012 03:40 PM, Jean-Christophe PLAGNIOL-VILLARD :
> confire the pin as pio when requested
> 
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/mach-at91/gpio.c |   14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index 325837a..994ed02 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -44,6 +44,7 @@ struct at91_gpio_chip {
>  
>  #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
>  
> +static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
>  static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
>  static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
>  static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
> @@ -57,6 +58,7 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
>  	{								\
>  		.chip = {						\
>  			.label		  = name,			\
> +			.request	  = at91_gpiolib_request,	\
>  			.direction_input  = at91_gpiolib_direction_input, \
>  			.direction_output = at91_gpiolib_direction_output, \
>  			.get		  = at91_gpiolib_get,		\
> @@ -861,6 +863,18 @@ void __init at91_gpio_irq_setup(void)
>  }
>  
>  /* gpiolib support */
> +
> +
> +static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
> +{
> +	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +	void __iomem *pio = at91_gpio->regbase;
> +	unsigned mask = 1 << offset;
> +
> +	__raw_writel(mask, pio + PIO_PER);
> +	return 0;
> +}
> +
>  static int at91_gpiolib_direction_input(struct gpio_chip *chip,
>  					unsigned offset)
>  {
> 


-- 
Nicolas Ferre




From balbi at ti.com  Tue Aug  7 08:37:16 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue,  7 Aug 2012 15:37:16 +0300
Subject: [PATCH v3] i2c: omap: switch over to autosuspend API
Message-ID: <1344343036-8832-1-git-send-email-balbi@ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message starting soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 60928f2..35e8207 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -55,6 +55,9 @@
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
 
+/* timeout for pm runtime autosuspend */
+#define OMAP_I2C_PM_TIMEOUT		1000	/* ms */
+
 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
 enum {
 	OMAP_I2C_REV_REG = 0,
@@ -645,7 +648,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1117,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1189,7 +1196,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.12.rc0



From balbi at ti.com  Tue Aug  7 08:38:05 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 7 Aug 2012 15:38:05 +0300
Subject: [PATCH v3] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344343036-8832-1-git-send-email-balbi@ti.com>
References: <1344343036-8832-1-git-send-email-balbi@ti.com>
Message-ID: <20120807123803.GB8468@arwen.pp.htv.fi>

On Tue, Aug 07, 2012 at 03:37:16PM +0300, Felipe Balbi wrote:
> this helps us reduce unnecessary pm transitions
> in case we have another i2c message starting soon.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>

ignore this one. sorry

-- 
balbi
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From balbi at ti.com  Tue Aug  7 08:38:07 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue,  7 Aug 2012 15:38:07 +0300
Subject: [PATCH v3] i2c: omap: switch over to autosuspend API
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433EB3087D@DBDE01.ent.ti.com>
References: <B5906170F1614E41A8A28DE3B8D121433EB3087D@DBDE01.ent.ti.com>
Message-ID: <1344343087-8947-1-git-send-email-balbi@ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message starting soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/i2c/busses/i2c-omap.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 60928f2..35e8207 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -55,6 +55,9 @@
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
 
+/* timeout for pm runtime autosuspend */
+#define OMAP_I2C_PM_TIMEOUT		1000	/* ms */
+
 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
 enum {
 	OMAP_I2C_REV_REG = 0,
@@ -645,7 +648,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1117,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1189,7 +1196,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.12.rc0



From nicolas.ferre at atmel.com  Tue Aug  7 08:47:01 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 14:47:01 +0200
Subject: [PATCH 2/4] ARM: at91: gpio: implement gpio_free
In-Reply-To: <1342359637-15325-2-git-send-email-plagnioj@jcrosoft.com>
References: <20120715131618.GF4450@game.jcrosoft.org>
 <1342359637-15325-1-git-send-email-plagnioj@jcrosoft.com>
 <1342359637-15325-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <50210E45.9060605@atmel.com>

On 07/15/2012 03:40 PM, Jean-Christophe PLAGNIOL-VILLARD :
> configure a gpio as input when freeing it to reduce power consumption
> 
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/mach-at91/gpio.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index 994ed02..3833f82 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -45,6 +45,7 @@ struct at91_gpio_chip {
>  #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
>  
>  static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
> +static void at91_gpiolib_free(struct gpio_chip *chip, unsigned offset);
>  static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
>  static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
>  static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
> @@ -59,6 +60,7 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
>  		.chip = {						\
>  			.label		  = name,			\
>  			.request	  = at91_gpiolib_request,	\
> +			.free		  = at91_gpiolib_free,		\
>  			.direction_input  = at91_gpiolib_direction_input, \
>  			.direction_output = at91_gpiolib_direction_output, \
>  			.get		  = at91_gpiolib_get,		\
> @@ -863,7 +865,10 @@ void __init at91_gpio_irq_setup(void)
>  }
>  
>  /* gpiolib support */
> -
> +static void at91_gpiolib_free(struct gpio_chip *chip, unsigned offset)
> +{
> +	at91_gpiolib_direction_input(chip, offset);

I know we talked about it, but now I am not sure.
Maybe a safer solution would be to not touching the gpio configuration
when freeing it...

> +}
>  
>  static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
>  {
> 


-- 
Nicolas Ferre




From nicolas.ferre at atmel.com  Tue Aug  7 08:50:20 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 14:50:20 +0200
Subject: [PATCH 3/4] at91: regroup gpio and pinctrl under a simple-bus
In-Reply-To: <1342359637-15325-3-git-send-email-plagnioj@jcrosoft.com>
References: <20120715131618.GF4450@game.jcrosoft.org>
 <1342359637-15325-1-git-send-email-plagnioj@jcrosoft.com>
 <1342359637-15325-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <50210F0C.8050507@atmel.com>

On 07/15/2012 03:40 PM, Jean-Christophe PLAGNIOL-VILLARD :
> Fix also the reg size as we have 512 bytes bank not 256 bytes per gpio/mux
> controller

Definitively, there is not enough information about the purpose of this
patch: please elaborate a bit more the comment.

Moreover, it seems strange to change the device tree files without
introducing the pinctrl/pinmux driver (and the associated documentation)
at the same time...

So, no, not these changes now.

> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/boot/dts/at91sam9260.dtsi |   56 ++++++++++++---------
>  arch/arm/boot/dts/at91sam9263.dtsi |   98 ++++++++++++++++++++----------------
>  arch/arm/boot/dts/at91sam9g45.dtsi |   87 ++++++++++++++++++--------------
>  arch/arm/boot/dts/at91sam9n12.dtsi |   79 ++++++++++++++++-------------
>  arch/arm/boot/dts/at91sam9x5.dtsi  |   73 +++++++++++++++------------
>  5 files changed, 223 insertions(+), 170 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> index f449efc..1f6c3cd 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -96,31 +96,41 @@
>  				interrupts = <26 4 27 4 28 4>;
>  			};
>  
> -			pioA: gpio at fffff400 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff400 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +			pinctrl at fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges;
> +				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +				reg = <0xfffff400 0x200
> +				       0xfffff600 0x200
> +				       0xfffff800 0x200>;
> +
> +				pioA: gpio at 80018000 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioB: gpio at fffff600 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff600 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioB: gpio at fffff600 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioC: gpio at fffff800 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff800 0x100>;
> -				interrupts = <4 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> +				pioC: gpio at fffff800 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  			};
>  
>  			dbgu: serial at fffff200 {
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> index 0209913..84ac493 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -87,49 +87,61 @@
>  				reg = <0xfffffd10 0x10>;
>  			};
>  
> -			pioA: gpio at fffff200 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff200 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioB: gpio at fffff400 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff400 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioC: gpio at fffff600 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff600 0x100>;
> -				interrupts = <4 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioD: gpio at fffff800 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff800 0x100>;
> -				interrupts = <4 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioE: gpio at fffffa00 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffffa00 0x100>;
> -				interrupts = <4 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> +			pinctrl at fffff200 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges;
> +				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +				reg = <0xfffff200 0x200
> +				       0xfffff400 0x200
> +				       0xfffff600 0x200
> +				       0xfffff800 0x200
> +				       0xfffffa00 0x200>;
> +
> +				pioA: gpio at fffff200 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff200 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioB: gpio at fffff400 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioC: gpio at fffff600 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <4 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioD: gpio at fffff800 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <4 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioE: gpio at fffffa00 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <4 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  			};
>  
>  			dbgu: serial at ffffee00 {
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index 7dbccaf..9e03049 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -105,49 +105,58 @@
>  				interrupts = <21 4>;
>  			};
>  
> -			pioA: gpio at fffff200 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff200 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +			pinctrl at fffff200 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges;
> +				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +
> +				reg = <0xfffff200 0xa00>;
> +
> +				pioA: gpio at fffff200 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff200 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioB: gpio at fffff400 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff400 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioB: gpio at fffff400 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioC: gpio at fffff600 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff600 0x100>;
> -				interrupts = <4 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioC: gpio at fffff600 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <4 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioD: gpio at fffff800 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffff800 0x100>;
> -				interrupts = <5 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioD: gpio at fffff800 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <5 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioE: gpio at fffffa00 {
> -				compatible = "atmel,at91rm9200-gpio";
> -				reg = <0xfffffa00 0x100>;
> -				interrupts = <5 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> +				pioE: gpio at fffffa00 {
> +					compatible = "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <5 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  			};
>  
>  			dbgu: serial at ffffee00 {
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index cb84de7..7bd81c4 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -100,40 +100,51 @@
>  				interrupts = <20 4>;
>  			};
>  
> -			pioA: gpio at fffff400 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff400 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioB: gpio at fffff600 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff600 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioC: gpio at fffff800 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff800 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> -
> -			pioD: gpio at fffffa00 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffffa00 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> +			pinctrl at fffff400 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges;
> +				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +				reg = <0xfffff400 0x200
> +				       0xfffff600 0x200
> +				       0xfffff800 0x200
> +				       0xfffffa00 0x200>;
> +
> +				pioA: gpio at fffff400 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioB: gpio at fffff600 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioC: gpio at fffff800 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
> +
> +				pioD: gpio at fffffa00 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  			};
>  
>  			dbgu: serial at fffff200 {
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 6b3ef43..e25c8d0 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -107,40 +107,51 @@
>  				interrupts = <21 4>;
>  			};
>  
> -			pioA: gpio at fffff400 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff400 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +			pinctrl at fffff200 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges;
> +				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +				reg = <0xfffff400 0x200
> +				       0xfffff600 0x200
> +				       0xfffff800 0x200
> +				       0xfffffa00 0x200>;
> +
> +				pioA: gpio at fffff400 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff400 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioB: gpio at fffff600 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff600 0x100>;
> -				interrupts = <2 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioB: gpio at fffff600 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff600 0x200>;
> +					interrupts = <2 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioC: gpio at fffff800 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffff800 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> -			};
> +				pioC: gpio at fffff800 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffff800 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  
> -			pioD: gpio at fffffa00 {
> -				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> -				reg = <0xfffffa00 0x100>;
> -				interrupts = <3 4>;
> -				#gpio-cells = <2>;
> -				gpio-controller;
> -				interrupt-controller;
> +				pioD: gpio at fffffa00 {
> +					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +					reg = <0xfffffa00 0x200>;
> +					interrupts = <3 4>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					interrupt-controller;
> +				};
>  			};
>  
>  			dbgu: serial at fffff200 {
> 


-- 
Nicolas Ferre




From nicolas.ferre at atmel.com  Tue Aug  7 08:52:35 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 14:52:35 +0200
Subject: [PATCH 4/4] arm: at91: at91sam9x5: fix gpio number per bank
In-Reply-To: <1342359637-15325-4-git-send-email-plagnioj@jcrosoft.com>
References: <20120715131618.GF4450@game.jcrosoft.org>
 <1342359637-15325-1-git-send-email-plagnioj@jcrosoft.com>
 <1342359637-15325-4-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <50210F93.8010003@atmel.com>

On 07/15/2012 03:40 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On the serie 5 bank b and d have 19 and 22 pins only.

No, it is not understandable.

> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  .../devicetree/bindings/gpio/gpio_atmel.txt        |    5 +++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |    2 ++
>  arch/arm/mach-at91/gpio.c                          |   33 +++++++++++++-------
>  3 files changed, 29 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> index 66efc80..d8dd425 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> @@ -9,6 +9,10 @@ Required properties:
>    unused).
>  - gpio-controller: Marks the device node as a GPIO controller.
>  
> +optional properties:
> +- gpio-nb: Number of gpio if absent 32.

Cf. Olof's comments.

> +
> +
>  Example:
>  	pioA: gpio at fffff200 {
>  		compatible = "atmel,at91rm9200-gpio";
> @@ -16,5 +20,6 @@ Example:
>  		interrupts = <2 4>;
>  		#gpio-cells = <2>;
>  		gpio-controller;
> +                gpio-nb = <32>;

No need: 32 is the default.

>  	};
>  
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index e25c8d0..e4d785b 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -132,6 +132,7 @@
>  					interrupts = <2 4>;
>  					#gpio-cells = <2>;
>  					gpio-controller;
> +					gpio-nb = <19>;
>  					interrupt-controller;
>  				};
>  
> @@ -150,6 +151,7 @@
>  					interrupts = <3 4>;
>  					#gpio-cells = <2>;
>  					gpio-controller;
> +					gpio-nb = <22>;
>  					interrupt-controller;
>  				};
>  			};
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index 3833f82..1ab06e8 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -31,6 +31,8 @@
>  
>  #include "generic.h"
>  
> +#define MAX_NB_GPIO_PER_BANK	32
> +
>  struct at91_gpio_chip {
>  	struct gpio_chip	chip;
>  	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
> @@ -55,7 +57,7 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
>  					unsigned offset);
>  static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
>  
> -#define AT91_GPIO_CHIP(name, nr_gpio)					\
> +#define AT91_GPIO_CHIP(name)						\
>  	{								\
>  		.chip = {						\
>  			.label		  = name,			\
> @@ -67,16 +69,16 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
>  			.set		  = at91_gpiolib_set,		\
>  			.dbg_show	  = at91_gpiolib_dbg_show,	\
>  			.to_irq		  = at91_gpiolib_to_irq,	\
> -			.ngpio		  = nr_gpio,			\
> +			.ngpio		  = MAX_NB_GPIO_PER_BANK,	\
>  		},							\
>  	}
>  
>  static struct at91_gpio_chip gpio_chip[] = {
> -	AT91_GPIO_CHIP("pioA", 32),
> -	AT91_GPIO_CHIP("pioB", 32),
> -	AT91_GPIO_CHIP("pioC", 32),
> -	AT91_GPIO_CHIP("pioD", 32),
> -	AT91_GPIO_CHIP("pioE", 32),
> +	AT91_GPIO_CHIP("pioA"),
> +	AT91_GPIO_CHIP("pioB"),
> +	AT91_GPIO_CHIP("pioC"),
> +	AT91_GPIO_CHIP("pioD"),
> +	AT91_GPIO_CHIP("pioE"),
>  };
>  
>  static int gpio_banks;
> @@ -91,7 +93,7 @@ static unsigned long at91_gpio_caps;
>  
>  static inline void __iomem *pin_to_controller(unsigned pin)
>  {
> -	pin /= 32;
> +	pin /= MAX_NB_GPIO_PER_BANK;
>  	if (likely(pin < gpio_banks))
>  		return gpio_chip[pin].regbase;
>  
> @@ -100,7 +102,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
>  
>  static inline unsigned pin_to_mask(unsigned pin)
>  {
> -	return 1 << (pin % 32);
> +	return 1 << (pin % MAX_NB_GPIO_PER_BANK);
>  }
>  
>  
> @@ -998,6 +1000,7 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
>  {
>  	int alias_idx;
>  	struct at91_gpio_chip *at91_gpio;
> +	uint32_t ngpio;
>  
>  	if (!np)
>  		return;
> @@ -1010,7 +1013,7 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
>  	}
>  
>  	at91_gpio = &gpio_chip[alias_idx];
> -	at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
> +	at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
>  
>  	at91_gpio->regbase = of_iomap(np, 0);
>  	if (!at91_gpio->regbase) {
> @@ -1030,6 +1033,14 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
>  	if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
>  		at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
>  
> +	if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
> +		if (ngpio >= MAX_NB_GPIO_PER_BANK)
> +			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
> +			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
> +		else
> +			at91_gpio->chip.ngpio = ngpio;
> +	}
> +
>  	/* Setup clock */
>  	if (at91_gpio_setup_clk(alias_idx))
>  		goto ioremap_err;
> @@ -1067,7 +1078,7 @@ static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
>  {
>  	struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
>  
> -	at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
> +	at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
>  	at91_gpio->pioc_hwirq = pioc_hwirq;
>  	at91_gpio->pioc_idx = idx;

Otherwise, I like it: so please resend it with corrections.

Bye,
-- 
Nicolas Ferre




From koen at dominion.thruhere.net  Tue Aug  7 08:54:22 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Tue, 7 Aug 2012 14:54:22 +0200
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
Message-ID: <2AE404CF-E456-408A-B7A2-D9B3D331C58E@dominion.thruhere.net>


Op 3 aug. 2012, om 14:38 heeft Sourav Poddar <sourav.poddar at ti.com> het volgende geschreven:

> Add keypad data node in omap5 device tree file.
> Also fill the device tree binding parameters
> with the required value in "omap5-evm" dts file.
> 
> Tested on omap5430 evm with 3.5 custom kernel.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
> arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
> arch/arm/boot/dts/omap5.dtsi    |    5 +++++
> 2 files changed, 17 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
> index 45a8aeb..09fe941 100644
> --- a/arch/arm/boot/dts/omap5-evm.dts
> +++ b/arch/arm/boot/dts/omap5-evm.dts
> @@ -17,6 +17,18 @@
> 		device_type = "memory";
> 		reg = <0x80000000 0x40000000>; /* 1 GB */
> 	};
> +
> +	keypad {
> +		keypad,num-rows = <8>;
> +		keypad,num-columns = <8>;
> +		linux,keymap = < 0x02020073
> +			0x02030072
> +			0x020400e7
> +			0x02050066
> +			0x0206006b
> +			0x020700d9 >;
> +		linux,input-no-autorepeat;
> +	};

Again not a coment on your patch, but on DT:

If DT bindings must be OS independent, what then, is that linux keycode doing there?

regards,

Koen



From rmallon at gmail.com  Tue Aug  7 08:57:38 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 07 Aug 2012 22:57:38 +1000
Subject: [PATCH] ARM: ep93xx: Use HW MAC filter in ethernet driver
In-Reply-To: <1344338818.18237.9.camel@localhost>
References: <1344338818.18237.9.camel@localhost>
Message-ID: <502110C2.400@gmail.com>

On 07/08/12 21:26, Yan Burman wrote:

> ARM: ep93xx: Use HW MAC filter in ethernet driver
> Use HW MAC filtering for broadcasts and multicasts.
> Do not always work in promiscuous mode.
> Partially based on kernel 2.6.20.4 driver from cirrus logic.
> Tested on 9302 and 9315 based boards.
> 
> Signed-off-by: Yan Burman <burman.yan at gmail.com>


Hi Yan,

Just a quick scan through, mostly style comments. Will try
to review properly tomorrow.

~Ryan

> 
> diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> index 78c5521..28bdf96 100644
> --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
> +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> @@ -29,7 +29,7 @@
>  #include <mach/hardware.h>
>  
>  #define DRV_MODULE_NAME		"ep93xx-eth"
> -#define DRV_MODULE_VERSION	"0.1"
> +#define DRV_MODULE_VERSION	"0.2"

Don't bother with this, the driver version isn't really used anyway.

>  #define RX_QUEUE_ENTRIES	64
>  #define TX_QUEUE_ENTRIES	8
> @@ -38,7 +38,29 @@
>  #define PKT_BUF_SIZE		2048
>  
>  #define REG_RXCTL		0x0000
> -#define  REG_RXCTL_DEFAULT	0x00073800
> +#define  REG_RXCTL_PauseA  (1<<20)
> +#define  REG_RXCTL_RxFCE1  (1<<19)
> +#define  REG_RXCTL_RxFCE0  (1<<18)
> +#define  REG_RXCTL_BCRC    (1<<17)
> +#define  REG_RXCTL_SRxON   (1<<16)
> +#define  REG_RXCTL_RCRCA   (1<<13)
> +#define  REG_RXCTL_RA      (1<<12)
> +#define  REG_RXCTL_PA      (1<<11)
> +#define  REG_RXCTL_BA      (1<<10)
> +#define  REG_RXCTL_MA      (1<<9)
> +#define  REG_RXCTL_IAHA    (1<<8)
> +#define  REG_RXCTL_IA3     (1<<3)
> +#define  REG_RXCTL_IA2     (1<<2)
> +#define  REG_RXCTL_IA1     (1<<1)
> +#define  REG_RXCTL_IA0     (1<<0)


Nitpick - spaces either side of the << operator.

> +#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
> +				REG_RXCTL_RA | \
> +				REG_RXCTL_RCRCA | \
> +				REG_RXCTL_SRxON | \
> +				REG_RXCTL_BCRC | \
> +				REG_RXCTL_RxFCE0 | \
> +				REG_RXCTL_IA0)
> +
>  #define REG_TXCTL		0x0004
>  #define  REG_TXCTL_ENABLE	0x00000001
>  #define REG_MIICMD		0x0010
> @@ -57,6 +79,12 @@
>  #define  REG_INTSTS_RX		0x00000004
>  #define REG_INTSTSC		0x002c
>  #define REG_AFP			0x004c
> +#define  REG_AFP_AFP_IA0	0
> +#define  REG_AFP_AFP_IA1	1
> +#define  REG_AFP_AFP_IA2	2
> +#define  REG_AFP_AFP_IA3	3
> +#define  REG_AFP_AFP_DTxP	6
> +#define  REG_AFP_AFP_HASH	7


Why AFP_AFP?

>  #define REG_INDAD0		0x0050
>  #define REG_INDAD1		0x0051
>  #define REG_INDAD2		0x0052
> @@ -386,6 +414,83 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
>  	return NETDEV_TX_OK;
>  }
>  
> +#define CRC_PRIME 0xFFFFFFFF
> +#define CRC_POLYNOMIAL 0x04C11DB6


Lower case for hex constants.

> +static unsigned char ep93xx_calculate_hash_index(char *mcast_addr)
> +{


This looks like the sort of function which might already have a 
generic implementation somewhere?

> +	unsigned long crc;
> +	unsigned char hash_idx;
> +	unsigned char addr_byte;
> +	unsigned char *addr;
> +	unsigned long high_bit;
> +	int byte;
> +	int bit;
> +
> +	crc = CRC_PRIME;
> +	addr = mcast_addr;
> +
> +	for (byte = 0; byte < 6; byte++) {
> +		addr_byte = *addr;
> +		addr++;
> +
> +		for (bit = 8; bit > 0; bit--) {
> +			high_bit = crc >> 31;
> +			crc <<= 1;
> +
> +			if (high_bit ^ (addr_byte & 1)) {
> +				crc ^= CRC_POLYNOMIAL;
> +				crc |= 1;
> +			}
> +
> +			addr_byte >>= 1;
> +		}
> +	}
> +
> +	for (bit = 0, hash_idx = 0; bit < 6; bit++) {
> +		hash_idx <<= 1;
> +		hash_idx |= (unsigned char)(crc & 1);
> +		crc >>= 1;
> +	}
> +
> +	return hash_idx;
> +}
> +
> +static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *pBuf)
> +{


pbuf. No camel-case please.

> +	unsigned char position;
> +	struct netdev_hw_addr *ha;
> +
> +	netdev_hw_addr_list_for_each(ha, &dev->mc) {
> +		if (ha->addr[0] & 1)
> +			continue;
> +		position = ep93xx_calculate_hash_index(ha->addr);
> +		pBuf[position >> 3] |= 1 << (position & 0x07);
> +	}
> +}
> +
> +static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *pBuf)
> +{
> +	u32 rxctl;
> +	int i, len;
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	afp &= 0x07;
> +	if (afp == 4 || afp == 5) {
> +		pr_crit("invalid afp value\n");
> +		return -1;
> +	}
> +	len = (afp == REG_AFP_AFP_HASH) ? 8 : 6;

Lots of magic numbers here.

> +	rxctl = rdl(ep, REG_RXCTL);
> +	wrl(ep, REG_RXCTL, ~REG_RXCTL_SRxON & rxctl);
> +	wrl(ep, REG_AFP, afp);
> +	for (i = 0; i < len; i++)
> +		wrb(ep, REG_INDAD0 + i, pBuf[i]);
> +	wrl(ep, REG_RXCTL, rxctl);
> +
> +	return 0;
> +}
> +
>  static void ep93xx_tx_complete(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -615,13 +720,7 @@ static int ep93xx_start_hw(struct net_device *dev)
>  	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
>  	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
>  
> -	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
> -	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
> -	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
> -	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
> -	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
> -	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
> -	wrl(ep, REG_AFP, 0);
> +	ep93xx_ind_addr_write(dev, REG_AFP_AFP_IA0, dev->dev_addr);
>  
>  	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
>  
> @@ -647,6 +746,31 @@ static void ep93xx_stop_hw(struct net_device *dev)
>  		pr_crit("hw failed to reset\n");
>  }
>  
> +static void ep93xx_set_multicast_list(struct net_device *dev)
> +{
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	if (dev->flags & IFF_PROMISC) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
> +	} else if (dev->flags & IFF_ALLMULTI) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
> +		ep93xx_ind_addr_write(dev, REG_AFP_AFP_HASH,
> +			      "\xff\xff\xff\xff\xff\xff\xff\xff");
> +	} else if (netdev_hw_addr_list_count(&dev->mc)) {
> +		u8 tblMulti[8 + 1];
> +		memset(tblMulti, 0, sizeof(tblMulti));


Nitpick - leave a blank line between variable declarations and code.

> +
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
> +		ep93xx_set_mcast_tbl(dev, tblMulti);
> +		ep93xx_ind_addr_write(dev, REG_AFP_AFP_HASH, tblMulti);
> +	} else {
> +		wrl(ep, REG_RXCTL,
> +			~(REG_RXCTL_PA | REG_RXCTL_MA) & rdl(ep, REG_RXCTL));
> +	}
> +}
> +
>  static int ep93xx_open(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -754,6 +878,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
>  	.ndo_validate_addr	= eth_validate_addr,
>  	.ndo_change_mtu		= eth_change_mtu,
>  	.ndo_set_mac_address	= eth_mac_addr,
> +	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
>  };
>  
>  static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
> 
> 




From rmallon at gmail.com  Tue Aug  7 09:03:40 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 07 Aug 2012 23:03:40 +1000
Subject: [PATCH] ARM: ep93xx: clockevent support
In-Reply-To: <1344338474.18237.6.camel@localhost>
References: <1344338474.18237.6.camel@localhost>
Message-ID: <5021122C.3000503@gmail.com>

On 07/08/12 21:21, Yan Burman wrote:

> ARM: ep93xx: clockevent support
> I have ported to 3.6-rc1 and slightly modified a previous patch for clockevent support for the ep93xx.
> The porting mainly consists of sched_clock support.
> Tested on 9302 based board.
> From: Ahmed Ammar <aammar <at> edge-techno.com>
> Signed-off-by: Yan Burman <burman.yan at gmail.com>


Hi Yan, some comments below.

~Ryan

> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..6dbb828 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -451,7 +451,7 @@ config ARCH_EP93XX
>  	select CLKDEV_LOOKUP
>  	select ARCH_REQUIRE_GPIOLIB
>  	select ARCH_HAS_HOLES_MEMORYMODEL
> -	select ARCH_USES_GETTIMEOFFSET
> +	select GENERIC_CLOCKEVENTS
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  This enables support for the Cirrus EP93xx series of CPUs.
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 4afe52a..1497cba 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -30,6 +30,8 @@
>  #include <linux/amba/bus.h>
>  #include <linux/amba/serial.h>
>  #include <linux/mtd/physmap.h>
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
>  #include <linux/i2c.h>
>  #include <linux/i2c-gpio.h>
>  #include <linux/spi/spi.h>
> @@ -43,6 +45,7 @@
>  
>  #include <asm/mach/map.h>
>  #include <asm/mach/time.h>
> +#include <asm/sched_clock.h>
>  
>  #include <asm/hardware/vic.h>
>  
> @@ -114,63 +117,129 @@ void __init ep93xx_map_io(void)
>  #define EP93XX_TIMER4_CLOCK		983040
>  
>  #define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
> -#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
> -
> -static unsigned int last_jiffy_time;
>  
>  static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
>  {
> -	/* Writing any value clears the timer interrupt */
> -	__raw_writel(1, EP93XX_TIMER1_CLEAR);
> +	struct clock_event_device *evt = dev_id;
>  
> -	/* Recover lost jiffies */
> -	while ((signed long)
> -		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
> -						>= TIMER4_TICKS_PER_JIFFY) {
> -		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
> -		timer_tick();
> -	}
> +	__raw_writel(1, EP93XX_TIMER1_CLEAR);
> +	evt->event_handler(evt);
>  
>  	return IRQ_HANDLED;
>  }
>  
> +static int ep93xx_set_next_event(unsigned long evt,
> +				struct clock_event_device *unused)
> +{
> +	u32 tmode = __raw_readl(EP93XX_TIMER1_CONTROL);
> +
> +	/* stop timer */
> +	__raw_writel(tmode & ~EP93XX_TIMER123_CONTROL_ENABLE,
> +			EP93XX_TIMER1_CONTROL);
> +	/* program timer */
> +	__raw_writel(evt, EP93XX_TIMER1_LOAD);
> +	/* start timer */
> +	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
> +			EP93XX_TIMER1_CONTROL);
> +
> +	return 0;
> +}
> +
> +static void ep93xx_set_mode(enum clock_event_mode mode,
> +			    struct clock_event_device *evt)
> +{
> +	u32 tmode = EP93XX_TIMER123_CONTROL_CLKSEL;
> +	/* Disable timer */


Nitpick - blank line between variable declarations and code.

> +	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		/* Set timer period  */
> +		__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
> +		tmode |= EP93XX_TIMER123_CONTROL_MODE;
> +


Is the fall-through here intentional? If so, please put a comment
to indicate that it is.

> +	case CLOCK_EVT_MODE_ONESHOT:
> +		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
> +		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
> +		break;
> +
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_RESUME:
> +		return;


These cases can be removed.

> +	}
> +}
> +
> +static struct clock_event_device clockevent_ep93xx = {
> +	.name		= "ep93xx-timer1",
> +	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
> +	.shift		= 32,
> +	.set_mode	= ep93xx_set_mode,
> +	.set_next_event	= ep93xx_set_next_event,
> +};
> +
>  static struct irqaction ep93xx_timer_irq = {
>  	.name		= "ep93xx timer",
>  	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
>  	.handler	= ep93xx_timer_interrupt,
> +	.dev_id		= &clockevent_ep93xx,
>  };
>  
> -static void __init ep93xx_timer_init(void)
> +static void __init ep93xx_clockevent_init(void)
>  {
> -	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
> -		    EP93XX_TIMER123_CONTROL_CLKSEL;
> +	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
> +	clockevent_ep93xx.mult = div_sc(508469, NSEC_PER_SEC,
> +					clockevent_ep93xx.shift);


core.c has:

  #define EP93XX_TIMER123_CLOCK               508469

Maybe we should move that to soc.h so you can use it here.

> +	clockevent_ep93xx.max_delta_ns =
> +		clockevent_delta2ns(0xfffffffe, &clockevent_ep93xx);
> +	clockevent_ep93xx.min_delta_ns =
> +		clockevent_delta2ns(0xf, &clockevent_ep93xx);
> +	clockevent_ep93xx.cpumask = cpumask_of(0);
> +	clockevents_register_device(&clockevent_ep93xx);
> +}
>  
> -	/* Enable periodic HZ timer.  */
> -	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
> -	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
> -	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
> -			EP93XX_TIMER1_CONTROL);
> +/*
> + * timer4 is a 40 Bit timer, separated in a 32bit and a 8 bit
> + * register, EP93XX_TIMER4_VALUE_LOW stores 32 bit word. The
> + * controlregister is in EP93XX_TIMER4_VALUE_HIGH


Missing space between control and register.

> + */
> +static cycle_t ep93xx_get_cycles(struct clocksource *unused)
> +{
> +	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
> +}
>  
> -	/* Enable lost jiffy timer.  */
> -	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
> -			EP93XX_TIMER4_VALUE_HIGH);
> +static struct clocksource clocksource_ep93xx = {
> +	.name		= "ep93xx_timer4",
> +	.rating		= 200,
> +	.read		= ep93xx_get_cycles,
> +	.mask		= 0xFFFFFFFF,


Lower case for hex constant.

> +	.shift		= 20,
> +	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
> +};
>  
> -	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
> +static void __init ep93xx_clocksource_init(void)
> +{
> +	/* Reset time-stamp counter */
> +	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
> +	clocksource_ep93xx.mult =
> +		clocksource_hz2mult(983040, clocksource_ep93xx.shift);


core.c has define EP93XX_TIMER4_CLOCK 983040, probably should move
that to soc.h also.

> +	clocksource_register(&clocksource_ep93xx);
>  }
>  
> -static unsigned long ep93xx_gettimeoffset(void)
> +static u32 notrace ep93xx_sched_clock(void)
>  {
> -	int offset;
> -
> -	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
> +	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
> +}
>  
> -	/* Calculate (1000000 / 983040) * offset.  */
> -	return offset + (53 * offset / 3072);
> +static void __init ep93xx_timer_init(void)
> +{
> +	ep93xx_clocksource_init();
> +	ep93xx_clockevent_init();
> +	setup_sched_clock(ep93xx_sched_clock, 32, CLOCK_TICK_RATE);
>  }
>  
>  struct sys_timer ep93xx_timer = {
>  	.init		= ep93xx_timer_init,
> -	.offset		= ep93xx_gettimeoffset,
>  };
>  
>  
> 
> 




From nicolas.ferre at atmel.com  Tue Aug  7 09:05:45 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 15:05:45 +0200
Subject: [GIT PULL] at91: platform data for atmel-mci (for 3.5)
In-Reply-To: <50110163.70002@atmel.com>
References: <4FBE4FE7.3010005@atmel.com> <4FC722B7.10409@atmel.com>
 <201207252006.44523.arnd@arndb.de> <50110163.70002@atmel.com>
Message-ID: <502112A9.4060703@atmel.com>

On 07/26/2012 10:35 AM, ludovic.desroches :
> Hi Arnd,
> 
> Le 07/25/2012 10:06 PM, Arnd Bergmann a ?crit :
>> On Thursday 31 May 2012, Nicolas Ferre wrote:
>>>
>>> On 05/24/2012 05:12 PM, Nicolas Ferre :
>>>> Hi Arnd, hi Olof,
>>>
>>> Ping?
>>>
>>> (or maybe you will have a look at this after the merge window...)
>>>
>>
>> I've just gone through all old pull requests that I had somewhere in
>> my inbox and this turned out to be one that we never pulled.
>>
>> It looks like it still applies and we should send it to Linus as as
>> late branch this time, given that we screwed up and it was there
>> all the time.
>>
>> Nicolas, can you please confirm?
>>
> 
> Nicolas is on vacation, he'll be back on week 32.
> 
> Nicolas and Olof discussed about this addition of ifdefs to manage the
> two drivers. They agreed to remove platform data for the old driver.
> 
> It will be great to go ahead with this patch. I see three solutions:
> - take the patch and we will do a new patch to remove old platform data
> for 3.7 when at91-mci will be totally removed but it seems that Olof
> doesn't like this solution.
> - I can write a new patch to remove old platform data as planned by
> Nicolas. If Jean-Christophe gives his acked-by, you could take it.
> - wait Nicolas' return but it may be too late then we won't have the
> smooth transition we wanted.

I am back in the game ;-)

I am about to rebuild a pull-request with what we discussed with Olof:
complete removal of old driver's platform data.

You still have the possibility to queue it as a late branch for 3.6...
(I keep it based on 3.5-rc, but I can rebase it on 3.6-rc1 to ease one
conflict resolution when merging with current Linus' tree).

Bye,
-- 
Nicolas Ferre




From peter.ujfalusi at ti.com  Tue Aug  7 09:12:25 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  7 Aug 2012 16:12:25 +0300
Subject: [PATCH v2 resend] ARM: OMAP4: twl-common: Support for additional
 devices on i2c1 bus
Message-ID: <1344345145-32125-1-git-send-email-peter.ujfalusi@ti.com>

On OMAP4 the i2c1 bus is dedicated for the PMIC and audio related devices.
Manufacturers can opt to use different codec than twl6040 and also can add
audio related IC to the bus (external amplifier for example on SDP4430).

Make it possible to add different set of additional devices to i2c1 bus on
OMAP4 boards.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---

Hi Tony,

The v2 patch applied cleanly on top of today's mainline (with 2 offset).
It would be really great if this could make it to 3.6, but it is not a big issue
if this can only scheduled for 3.7.

Regards,
Peter 

 arch/arm/mach-omap2/board-4430sdp.c    |   12 ++++++++-
 arch/arm/mach-omap2/board-omap4panda.c |   12 ++++++++-
 arch/arm/mach-omap2/twl-common.c       |   37 +++++++++----------------------
 arch/arm/mach-omap2/twl-common.h       |    3 +-
 4 files changed, 33 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index d4831b6..bcbcad1 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -550,6 +550,14 @@ static struct twl6040_platform_data twl6040_data = {
 	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
+static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("twl6040", 0x4b),
+		.irq = OMAP44XX_IRQ_SYS_2N,
+		.platform_data = &twl6040_data,
+	},
+};
+
 static struct twl4030_platform_data sdp4430_twldata = {
 	/* Regulators */
 	.vusim		= &sdp4430_vusim,
@@ -583,8 +591,8 @@ static int __init omap4_i2c_init(void)
 			TWL_COMMON_REGULATOR_CLK32KG |
 			TWL_COMMON_REGULATOR_V1V8 |
 			TWL_COMMON_REGULATOR_V2V1);
-	omap4_pmic_init("twl6030", &sdp4430_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+	omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
+			ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
 				ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 70f6d1d..5e18927 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -266,6 +266,14 @@ static struct twl6040_platform_data twl6040_data = {
 	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("twl6040", 0x4b),
+		.irq = OMAP44XX_IRQ_SYS_2N,
+		.platform_data = &twl6040_data,
+	},
+};
+
 /* Panda board uses the common PMIC configuration */
 static struct twl4030_platform_data omap4_panda_twldata;
 
@@ -293,8 +301,8 @@ static int __init omap4_panda_i2c_init(void)
 			TWL_COMMON_REGULATOR_CLK32KG |
 			TWL_COMMON_REGULATOR_V1V8 |
 			TWL_COMMON_REGULATOR_V2V1);
-	omap4_pmic_init("twl6030", &omap4_panda_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+	omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
+			ARRAY_SIZE(panda_i2c_1_boardinfo));
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	/*
 	 * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index de47f17..d52be85 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -39,16 +39,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
 	.flags		= I2C_CLIENT_WAKE,
 };
 
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-	{
-		.addr		= 0x48,
-		.flags		= I2C_CLIENT_WAKE,
-	},
-	{
-		I2C_BOARD_INFO("twl6040", 0x4b),
-	},
-};
-
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
@@ -77,30 +67,25 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 
 void __init omap4_pmic_init(const char *pmic_type,
 		    struct twl4030_platform_data *pmic_data,
-		    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+		    struct i2c_board_info *devices, int nr_devices)
 {
 	/* PMIC part*/
 	omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-	strncpy(omap4_i2c1_board_info[0].type, pmic_type,
-		sizeof(omap4_i2c1_board_info[0].type));
-	omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
-	omap4_i2c1_board_info[0].platform_data = pmic_data;
-
-	/* TWL6040 audio IC part */
-	omap4_i2c1_board_info[1].irq = twl6040_irq;
-	omap4_i2c1_board_info[1].platform_data = twl6040_data;
-
-	omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+	omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
 
+	/* Register additional devices on i2c1 bus if needed */
+	if (devices)
+		i2c_register_board_info(1, devices, nr_devices);
 }
 
 void __init omap_pmic_late_init(void)
 {
-	/* Init the OMAP TWL parameters (if PMIC has been registered) */
-	if (pmic_i2c_board_info.irq)
-		omap3_twl_init();
-	if (omap4_i2c1_board_info[0].irq)
-		omap4_twl_init();
+	/* Init the OMAP TWL parameters (if PMIC has been registerd) */
+	if (!pmic_i2c_board_info.irq)
+		return;
+
+	omap3_twl_init();
+	omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 8fe71cf..de062c7 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -32,6 +32,7 @@
 
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct i2c_board_info;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
 		    struct twl4030_platform_data *pmic_data);
@@ -51,7 +52,7 @@ static inline void omap3_pmic_init(const char *pmic_type,
 
 void omap4_pmic_init(const char *pmic_type,
 		    struct twl4030_platform_data *pmic_data,
-		    struct twl6040_platform_data *audio_data, int twl6040_irq);
+		    struct i2c_board_info *devices, int nr_devices);
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 			   u32 pdata_flags, u32 regulators_flags);
-- 
1.7.8.6



From shawn.guo at linaro.org  Tue Aug  7 09:16:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 7 Aug 2012 21:16:10 +0800
Subject: [PATCH] ARM: mxs_defconfig: Add LED, PWM and MTD_CHAR support
In-Reply-To: <1344272346-22797-1-git-send-email-fabio.estevam@freescale.com>
References: <1344272346-22797-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120807131606.GB13964@S2101-09.ap.freescale.net>

On Mon, Aug 06, 2012 at 01:59:06PM -0300, Fabio Estevam wrote:
> Add LED, PWM and MTD_CHAR support.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

-- 
Regards,
Shawn



From m.szyprowski at samsung.com  Tue Aug  7 09:20:11 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 07 Aug 2012 15:20:11 +0200
Subject: [PATCH] ARM: dma-mapping: fix incorrect freeing of atomic
 allocations
In-Reply-To: <1344171029-24804-1-git-send-email-aaro.koskinen@iki.fi>
References: <1344171029-24804-1-git-send-email-aaro.koskinen@iki.fi>
Message-ID: <011c01cd749f$620a80d0$261f8270$%szyprowski@samsung.com>

Hi Aaro,

On Sunday, August 05, 2012 2:50 PM Aaro Koskinen wrote:

> Commit e9da6e9905e639b0f842a244bc770b48ad0523e9 (ARM: dma-mapping:
> remove custom consistent dma region) changed the way atomic allocations
> are handled. However, arm_dma_free() was not modified accordingly, and
> as a result freeing of atomic allocations does not work correctly when
> CMA is disabled. Memory is leaked and following WARNINGs are seen:
> 
> [   57.698911] ------------[ cut here ]------------
> [   57.753518] WARNING: at arch/arm/mm/dma-mapping.c:263 arm_dma_free+0x88/0xe4()
> [   57.811473] trying to free invalid coherent area: e0848000
> [   57.867398] Modules linked in: sata_mv(-)
> [   57.921373] [<c000d270>] (unwind_backtrace+0x0/0xf0) from [<c0015430>]
> (warn_slowpath_common+0x50/0x68)
> [   58.033924] [<c0015430>] (warn_slowpath_common+0x50/0x68) from [<c00154dc>]
> (warn_slowpath_fmt+0x30/0x40)
> [   58.152024] [<c00154dc>] (warn_slowpath_fmt+0x30/0x40) from [<c000dc18>]
> (arm_dma_free+0x88/0xe4)
> [   58.219592] [<c000dc18>] (arm_dma_free+0x88/0xe4) from [<c008fa30>]
> (dma_pool_destroy+0x100/0x148)
> [   58.345526] [<c008fa30>] (dma_pool_destroy+0x100/0x148) from [<c019a64c>]
> (release_nodes+0x144/0x218)
> [   58.475782] [<c019a64c>] (release_nodes+0x144/0x218) from [<c0197e10>]
> (__device_release_driver+0x60/0xb8)
> [   58.614260] [<c0197e10>] (__device_release_driver+0x60/0xb8) from [<c0198608>]
> (driver_detach+0xd8/0xec)
> [   58.756527] [<c0198608>] (driver_detach+0xd8/0xec) from [<c0197c54>]
> (bus_remove_driver+0x7c/0xc4)
> [   58.901648] [<c0197c54>] (bus_remove_driver+0x7c/0xc4) from [<c004bfac>]
> (sys_delete_module+0x19c/0x220)
> [   59.051447] [<c004bfac>] (sys_delete_module+0x19c/0x220) from [<c0009140>]
> (ret_fast_syscall+0x0/0x2c)
> [   59.207996] ---[ end trace 0745420412c0325a ]---
> [   59.287110] ------------[ cut here ]------------
> [   59.366324] WARNING: at arch/arm/mm/dma-mapping.c:263 arm_dma_free+0x88/0xe4()
> [   59.450511] trying to free invalid coherent area: e0847000
> [   59.534357] Modules linked in: sata_mv(-)
> [   59.616785] [<c000d270>] (unwind_backtrace+0x0/0xf0) from [<c0015430>]
> (warn_slowpath_common+0x50/0x68)
> [   59.790030] [<c0015430>] (warn_slowpath_common+0x50/0x68) from [<c00154dc>]
> (warn_slowpath_fmt+0x30/0x40)
> [   59.972322] [<c00154dc>] (warn_slowpath_fmt+0x30/0x40) from [<c000dc18>]
> (arm_dma_free+0x88/0xe4)
> [   60.070701] [<c000dc18>] (arm_dma_free+0x88/0xe4) from [<c008fa30>]
> (dma_pool_destroy+0x100/0x148)
> [   60.256817] [<c008fa30>] (dma_pool_destroy+0x100/0x148) from [<c019a64c>]
> (release_nodes+0x144/0x218)
> [   60.445201] [<c019a64c>] (release_nodes+0x144/0x218) from [<c0197e10>]
> (__device_release_driver+0x60/0xb8)
> [   60.634148] [<c0197e10>] (__device_release_driver+0x60/0xb8) from [<c0198608>]
> (driver_detach+0xd8/0xec)
> [   60.823623] [<c0198608>] (driver_detach+0xd8/0xec) from [<c0197c54>]
> (bus_remove_driver+0x7c/0xc4)
> [   61.013268] [<c0197c54>] (bus_remove_driver+0x7c/0xc4) from [<c004bfac>]
> (sys_delete_module+0x19c/0x220)
> [   61.203472] [<c004bfac>] (sys_delete_module+0x19c/0x220) from [<c0009140>]
> (ret_fast_syscall+0x0/0x2c)
> [   61.393390] ---[ end trace 0745420412c0325b ]---
> 
> The patch fixes this.
> 
> Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>

Thanks for spotting this issue. I've applied it to my fixes branch.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From m.szyprowski at samsung.com  Tue Aug  7 09:22:47 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 07 Aug 2012 15:22:47 +0200
Subject: [PATCH] ARM: dma-mapping: fix atomic allocation alignment
In-Reply-To: <1344187926-22404-1-git-send-email-aaro.koskinen@iki.fi>
References: <1344187926-22404-1-git-send-email-aaro.koskinen@iki.fi>
Message-ID: <011d01cd749f$be649fa0$3b2ddee0$%szyprowski@samsung.com>

Hi Aaro,

On Sunday, August 05, 2012 7:32 PM Aaro Koskinen wrote:

> The alignment mask is calculated incorrectly. Fixing the calculation
> makes strange hangs/lockups disappear during the boot with Amstrad E3
> and 3.6-rc1 kernel.
> 
> Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>

Again, thanks for spotting and fixing the issue. I've applied it to my fixes branch. 
I'm really sorry for introducing such stupid bugs together with my changes.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From nicolas.ferre at atmel.com  Tue Aug  7 09:31:08 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 7 Aug 2012 15:31:08 +0200
Subject: [GIT PULL] at91: soc update (for 3.6)
Message-ID: <5021189C.2010107@atmel.com>

Hi Arnd, hi Olof,

Here is an additional AT91 pull request that is 
still related with the replacement of sd/mmc 
platform data.

(it doesn't merge seamlessly with current 
Linus' tree: I can provide a resolution hint or
rebase this work if necessary).

The following changes since commit 6887a4131da3adaab011613776d865f4bcfb5678:

  Linux 3.5-rc5 (2012-06-30 16:08:57 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-for-next-soc

for you to fetch changes up to 4cf3326ab5f34a333a46c59d0d3783db9cef13bf:

  ARM: at91: add atmel-mci support for chips and boards which can use it (2012-07-02 18:03:01 +0200)

----------------------------------------------------------------
AT91 SoC related code modifications: a cleanup in defconfigs and
a one liner in a board file.
The most important is the move to atmel-mci driver in AT91 SoC & boards.
The old at91_mci (marked as deprecated) will be removed in 3.7. So all
platform data for this old driver are erased and replace by information
needed by atmel-mci driver.

----------------------------------------------------------------
Ludovic Desroches (1):
      ARM: at91: add atmel-mci support for chips and boards which can use it

Nicolas Ferre (1):
      ARM: at91/defconfig: change the MCI driver to use in defconfigs

Paul Bolle (1):
      ARM: at91: set i2c_board_info.type to "ds1339" directly

Richard Genoud (1):
      ARM: at91/defconfig: Remove unaffected config option

 arch/arm/configs/afeb9260_defconfig      |    1 -
 arch/arm/configs/at91rm9200_defconfig    |    2 +-
 arch/arm/configs/at91sam9261_defconfig   |    2 +-
 arch/arm/configs/at91sam9263_defconfig   |    3 +-
 arch/arm/configs/at91sam9g20_defconfig   |    2 +-
 arch/arm/configs/at91sam9rl_defconfig    |    2 +-
 arch/arm/configs/cpu9260_defconfig       |    2 +-
 arch/arm/configs/cpu9g20_defconfig       |    2 +-
 arch/arm/configs/qil-a9260_defconfig     |    3 +-
 arch/arm/configs/stamp9g20_defconfig     |    1 -
 arch/arm/configs/usb-a9260_defconfig     |    1 -
 arch/arm/mach-at91/at91rm9200_devices.c  |   92 ++++++++++++++++++++++++-----------------
 arch/arm/mach-at91/at91sam9260_devices.c |   84 +-------------------------------------
 arch/arm/mach-at91/at91sam9261_devices.c |   60 +++++++++++++--------------
 arch/arm/mach-at91/at91sam9263.c         |    4 +-
 arch/arm/mach-at91/at91sam9263_devices.c |  161 ++++++++++++++++++++++++++++++++++++++++++------------------------------
 arch/arm/mach-at91/at91sam9rl_devices.c  |   60 +++++++++++++--------------
 arch/arm/mach-at91/board-afeb-9260v1.c   |   14 +++----
 arch/arm/mach-at91/board-carmeva.c       |   14 +++----
 arch/arm/mach-at91/board-cpu9krea.c      |   17 ++++----
 arch/arm/mach-at91/board-cpuat91.c       |   13 +++---
 arch/arm/mach-at91/board-csb337.c        |   14 +++----
 arch/arm/mach-at91/board-eb9200.c        |   14 +++----
 arch/arm/mach-at91/board-ecbat91.c       |   14 +++----
 arch/arm/mach-at91/board-eco920.c        |   14 +++----
 arch/arm/mach-at91/board-flexibity.c     |   14 +++----
 arch/arm/mach-at91/board-foxg20.c        |   16 ++++----
 arch/arm/mach-at91/board-kb9202.c        |   14 +++----
 arch/arm/mach-at91/board-neocore926.c    |   13 +++---
 arch/arm/mach-at91/board-picotux200.c    |   14 +++----
 arch/arm/mach-at91/board-qil-a9260.c     |   14 +++----
 arch/arm/mach-at91/board-rm9200dk.c      |   14 +++----
 arch/arm/mach-at91/board-rm9200ek.c      |   14 +++----
 arch/arm/mach-at91/board-rsi-ews.c       |   13 +++---
 arch/arm/mach-at91/board-sam9-l9260.c    |   16 ++++----
 arch/arm/mach-at91/board-sam9260ek.c     |   16 ++++----
 arch/arm/mach-at91/board-sam9261ek.c     |   13 +++---
 arch/arm/mach-at91/board-sam9263ek.c     |   13 +++---
 arch/arm/mach-at91/board-sam9g20ek.c     |   16 +-------
 arch/arm/mach-at91/board-sam9rlek.c      |   13 +++---
 arch/arm/mach-at91/board-stamp9g20.c     |   14 -------
 arch/arm/mach-at91/board-usb-a926x.c     |    2 -
 arch/arm/mach-at91/board-yl-9200.c       |   13 +++---
 drivers/mtd/nand/Kconfig                 |   40 ------------------
 44 files changed, 384 insertions(+), 494 deletions(-)

Thanks, best regards,
-- 
Nicolas Ferre



From hvaibhav at ti.com  Tue Aug  7 09:30:50 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 Aug 2012 19:00:50 +0530
Subject: [PATCH] arm: OMAP3+: am33xx: Add new clk node entry for d_can modules
Message-ID: <1344346250-27606-1-git-send-email-hvaibhav@ti.com>

The d_can0/1 module integrated with AM335x device, requires
only one clock (fck) and driver expects clock to be available
without specifying any connection id (con_id) -

  clk_get(&pdev->dev, NULL);

This is acceptable as module has only one clock and platform
code should respect this request, so create new clock nodes
inside am33xx clock-tree table based on dev_id and "con_id = NULL"
for both d_can0 and d_can1 instances.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
This patch is boot tested on BeagleBone platform, and checked for
clk_get() api return value.

 arch/arm/mach-omap2/clock33xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index ae27de8..23251fa 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),
 	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),
 	CLK(NULL,	"dcan0_fck",		&dcan0_fck,	CK_AM33XX),
+	CLK("d_can.0",	NULL,			&dcan0_fck,	CK_AM33XX),
 	CLK(NULL,	"dcan1_fck",		&dcan1_fck,	CK_AM33XX),
+	CLK("d_can.1",	NULL,			&dcan1_fck,	CK_AM33XX),
 	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
 	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
 	CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
--
1.7.0.4



From a.p.zijlstra at chello.nl  Tue Aug  7 09:48:42 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Tue, 07 Aug 2012 15:48:42 +0200
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120807115647.GA12828@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
Message-ID: <1344347322.27828.120.camel@twins>

On Tue, 2012-08-07 at 12:56 +0100, Will Deacon wrote:
> Hello,
> 
> ARM recently moved to asm-generic/mutex-xchg.h for its mutex implementation
> after our previous implementation was found to be missing some crucial
> memory barriers. 


This is a76d7bd96d ("ARM: 7467/1: mutex: use generic xchg-based
implementation for ARMv6+"), right? Why do you use xchg and not dec
based? The changelog mumbles something about shorter critical sections,
but me not knowing anything about ARM wonders about the why of that.

> However, I'm seeing some problems running hackbench on
> SMP platforms due to the way in which the MUTEX_SPIN_ON_OWNER code operates.
> 
> The symptoms are that a bunch of hackbench tasks are left waiting on an
> unlocked mutex and therefore never get woken up to claim it. I think this
> boils down to the following sequence:
> 
> 
>         Task A        Task B        Task C        Lock value
> 0                                                     1
> 1       lock()                                        0
> 2                     lock()                          0
> 3                     spin(A)                         0
> 4       unlock()                                      1
> 5                                   lock()            0
> 6                     cmpxchg(1,0)                    0
> 7                     contended()                    -1
> 8       lock()                                        0
> 9       spin(C)                                       0
> 10                                  unlock()          1
> 11      cmpxchg(1,0)                                  0
> 12      unlock()                                      1
> 
> 
> At this point, the lock is unlocked, but Task B is in an uninterruptible
> sleep with nobody to wake it up.
> 
> The following patch fixes the problem by ensuring we put the lock into
> the contended state if we acquire it from the spin loop on the slowpath
> but I'd like to be sure that this won't cause problems with other mutex
> implementations:
> 
> 
> diff --git a/kernel/mutex.c b/kernel/mutex.c
> index a307cc9..27b7887 100644
> --- a/kernel/mutex.c
> +++ b/kernel/mutex.c
> @@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
>                 if (owner && !mutex_spin_on_owner(lock, owner))
>                         break;
>  
> -               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> +               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
>                         lock_acquired(&lock->dep_map, ip);
>                         mutex_set_owner(lock);
>                         preempt_enable();
> 

But in this case, either B is still spinning in our spin-loop, or it has
already passed the atomic_xchg(&lock->count, -1) when we fell out.

Since you say B is in UNINTERRUPTIBLE state, we'll assume it fell
through and so the lock count should be -1 (or less) to mark it
contended.




From will.deacon at arm.com  Tue Aug  7 10:04:55 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 Aug 2012 15:04:55 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <1344347322.27828.120.camel@twins>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <1344347322.27828.120.camel@twins>
Message-ID: <20120807140455.GB12828@mudshark.cambridge.arm.com>

On Tue, Aug 07, 2012 at 02:48:42PM +0100, Peter Zijlstra wrote:
> On Tue, 2012-08-07 at 12:56 +0100, Will Deacon wrote:
> > ARM recently moved to asm-generic/mutex-xchg.h for its mutex implementation
> > after our previous implementation was found to be missing some crucial
> > memory barriers. 
> 
> 
> This is a76d7bd96d ("ARM: 7467/1: mutex: use generic xchg-based
> implementation for ARMv6+"), right? Why do you use xchg and not dec
> based? The changelog mumbles something about shorter critical sections,
> but me not knowing anything about ARM wonders about the why of that.

Correct, that's the patch. We don't have atomic add/sub instructions on ARM,
so instead we have to do:

1:	ldrex	...	@ Exclusive load
	add/sub ...     @ Do the arithmetic
	strex	...	@ Exclusive store
	cmp	...	@ Check the store succeeded
	bne	1b	@ Retry if we weren't atomic

So using dec adds a sub where we wouldn't need an instruction there for xchg.
I suspect there's no measurable difference between the two, but we use the
xchg-based implementation for CPUs prior to ARMv6 so it saves an ifdef as
well. Some discussion on the original patch here:

  http://lists.infradead.org/pipermail/linux-arm-kernel/2012-July/109333.html

> >         Task A        Task B        Task C        Lock value
> > 0                                                     1
> > 1       lock()                                        0
> > 2                     lock()                          0
> > 3                     spin(A)                         0
> > 4       unlock()                                      1
> > 5                                   lock()            0
> > 6                     cmpxchg(1,0)                    0
> > 7                     contended()                    -1
> > 8       lock()                                        0
> > 9       spin(C)                                       0
> > 10                                  unlock()          1
> > 11      cmpxchg(1,0)                                  0
> > 12      unlock()                                      1
> > 
> > 
> > At this point, the lock is unlocked, but Task B is in an uninterruptible
> > sleep with nobody to wake it up.

[...]

> But in this case, either B is still spinning in our spin-loop, or it has
> already passed the atomic_xchg(&lock->count, -1) when we fell out.

Yes, it does that xchg on line 7 (see the lock value of -1)...

> Since you say B is in UNINTERRUPTIBLE state, we'll assume it fell
> through and so the lock count should be -1 (or less) to mark it
> contended.

... but then A sets it straight back to 0 in __mutex_fastpath_lock and falls
down the slowpath due to it being contended. The problem is that it doesn't
restore the -1 when it acquires the lock on line 11, so B is never woken up.

Will


From hvaibhav at ti.com  Tue Aug  7 10:14:01 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 Aug 2012 19:44:01 +0530
Subject: [PATCH-V3] ARM: OMAP2+: cpu: Add am33xx device under
 cpu_class_is_omap2
Message-ID: <1344348841-19868-1-git-send-email-hvaibhav@ti.com>

AM33XX device falls under omap2 class, so make cpu_class_is_omap2()
macro true by adding soc_is_am33xx() to existing list of cpu/soc
check.
This is required to unblock the basic boot support on AM335x platform.

Having done that, we still need to sort out properly from
common zImage point of view without having to maintain this
cpu/soc_is_xxx list.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
This patch is boot tested on BeagleBone
(using already accepted hwmod patches)

Changes from V2:
	- This change is dropped now, since it breaks common zImage support.

Changes from V1:
	- No code change, added detailed description for common zImage
	  support.

 arch/arm/plat-omap/include/plat/cpu.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 68b180e..bb5d08a 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -372,7 +372,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_class_is_omap1()	(cpu_is_omap7xx() || cpu_is_omap15xx() || \
 				cpu_is_omap16xx())
 #define cpu_class_is_omap2()	(cpu_is_omap24xx() || cpu_is_omap34xx() || \
-				cpu_is_omap44xx() || soc_is_omap54xx())
+				cpu_is_omap44xx() || soc_is_omap54xx() || \
+				soc_is_am33xx())

 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS		0x24200024
--
1.7.0.4



From hvaibhav at ti.com  Tue Aug  7 09:37:16 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 7 Aug 2012 19:07:16 +0530
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix dev_id
 for CAN module
Message-ID: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>

If the module requires only one clocksource to function, then
driver can very well call clk_get() api with "con_id = NULL",

       clk = clk_get(dev, NULL);

And platform code should respect this and return valid clk handle.
That means, now the clk_get() api would rely on dev_id, and platform
code should either have clk node with matching dev_id (with con_id=NULL)
or return dummy clk node.

With DT support, we can fix the dev_id for particular module
using "struct of_dev_auxdata" to satisfy above clk framework requirement.

In case of AM33XX, we required this for the DCAN module, so this
patch adds "of_dev_auxdata" for both DCAN_0/1 instances.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
This patch is boot tested on BeagleBone platform, and checked for
clk_get() return value in d_can module driver.

 arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20..c9b7903 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 	{ }
 };

+/*
+ * Lookup table for attaching a specific name and platform_data pointer to
+ * devices as they get created by of_platform_populate(). Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name OR to satisfy NULL con_id requirement from driver.
+ */
+static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
+	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
+	{ },
+};
+
 static void __init omap_generic_init(void)
 {
 	omap_sdrc_init(NULL, NULL);

-	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
+	if (of_machine_is_compatible("ti,am33xx"))
+		of_platform_populate(NULL, omap_dt_match_table,
+				am33xx_auxdata_lookup, NULL);
+	else
+		of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
 }

 #ifdef CONFIG_SOC_OMAP2420
--
1.7.0.4



From arnd at arndb.de  Tue Aug  7 10:28:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 14:28:56 +0000
Subject: [PATCH V4 1/2] include/video: move fimd register headers from
 platform to include/video
In-Reply-To: <1344342872-7904-2-git-send-email-l.krishna@samsung.com>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
 <1344342872-7904-2-git-send-email-l.krishna@samsung.com>
Message-ID: <201208071428.56290.arnd@arndb.de>

On Tuesday 07 August 2012, Leela Krishna Amudala wrote:
> 
> This patch moves the contents from regs-fb-v4.h and regs-fb.h to
> include/video/samsung_fimd.h. Also updates the header inclusion in
> machine files and driver files accordingly.
> 
> Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>

You are missing an explanation here about why the file is moved.
It does seem like a good idea but please say why you do this.

More importantly, I don't understany why you move regs-fb-v4.h
but not regs-fb.h, which is included by the former. Also, the
only identifiers used in arch/arm from either of the two headers
are

	VIDCON0_VIDOUT_RGB
	VIDCON0_PNRMODE_RGBV
	VIDCON0_CLKSEL_LCD

	VIDCON1_INV_HSYNC
	VIDCON1_INV_VSYNC
	VIDCON1_INV_VCLK
	VIDCON1_INV_VDEN

and they are all in plat/regs-fb.h, so there is no need to
include the entire header file.

	Arnd


From linux at arm.linux.org.uk  Tue Aug  7 10:33:42 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 15:33:42 +0100
Subject: [PATCH V4 0/2] arm: samsung: Move FIMD headers to include/video/
In-Reply-To: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
Message-ID: <20120807143342.GD18957@n2100.arm.linux.org.uk>

On Tue, Aug 07, 2012 at 06:04:30PM +0530, Leela Krishna Amudala wrote:
>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --------------------
>  drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
>  drivers/video/s3c-fb.c                             |    2 +-
>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  152 +++++++++++++++++--

Isn't include/video for framebuffer drivers?  Isn't this more a DRM thing?
Wouldn't include/drm therefore be more appropriate?


From hs at denx.de  Tue Aug  7 10:34:40 2012
From: hs at denx.de (Heiko Schocher)
Date: Tue, 07 Aug 2012 16:34:40 +0200
Subject: [PATCH v6] ARM: mtd: nand: davinci: add OF support for davinci
 nand controller
In-Reply-To: <1343632944-25971-1-git-send-email-hs@denx.de>
References: <1343632944-25971-1-git-send-email-hs@denx.de>
Message-ID: <50212780.5000809@denx.de>

Hello,

On 30.07.2012 09:22, Heiko Schocher wrote:
> add OF support for the davinci nand controller.
>
> Signed-off-by: Heiko Schocher<hs at denx.de>
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-mtd at lists.infradead.org
> Cc: David Woodhouse<dwmw2 at infradead.org>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> Cc: Sekhar Nori<nsekhar at ti.com>
> Cc: Wolfgang Denk<wd at denx.de>
> Cc: Scott Wood<scottwood at freescale.com>
>
> ---
> - changes for v2:
>    - add comments from Scott Wood:
>      - add "ti,davinci-" prefix
>      - Dashes are preferred to underscores
>      - rename "nandflash" to "nand"
>      - introduce new "ti,davinci" specific properties for setting
>        up ecc_mode, ecc_bits, options and bbt options, instead
>        using linux defines
>      - readme fixes
> - no changes for v3
> - changes for v4
>    remove "pinmux-handle" property as discussed here:
>    http://www.spinics.net/lists/arm-kernel/msg175701.html
>    with Nori Sekhar
> - no changes for v5
>
> - changes for v6:
>    add comments from Sekhar Nori:
>    - remove unnecessary includes
>    - use devm_kzalloc instead of kzalloc
>    - remove AEMIF timing specific bindings, as
>      this has to be done later.
>
>   .../devicetree/bindings/arm/davinci/nand.txt       |   51 ++++++++++++++
>   drivers/mtd/nand/davinci_nand.c                    |   72 +++++++++++++++++++-
>   2 files changed, 122 insertions(+), 1 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt

ping ... any comments?

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


From ian.molton at codethink.co.uk  Tue Aug  7 10:34:47 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:47 +0100
Subject: [PATCH v3 2/7] mv643xx.c: Remove magic numbers.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-3-git-send-email-ian.molton@codethink.co.uk>

replace magic number with RX_CSUM_WITH_HEADER.

Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 4fbba57..92497eb 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -86,6 +86,7 @@ static char mv643xx_eth_driver_version[] = "1.4";
  * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
  */
 #define PORT_CONFIG			0x0000
+#define  RX_CSUM_WITH_HEADER		0x02000000
 #define  UNICAST_PROMISCUOUS_MODE	0x00000001
 #define PORT_CONFIG_EXT			0x0004
 #define MAC_ADDR_LOW			0x0014
@@ -1607,7 +1608,7 @@ mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
 	struct mv643xx_eth_private *mp = netdev_priv(dev);
 	bool rx_csum = features & NETIF_F_RXCSUM;
 
-	wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
+	wrlp(mp, PORT_CONFIG, rx_csum ? RX_CSUM_WITH_HEADER : 0x00000000);
 
 	return 0;
 }
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:45 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:45 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
Message-ID: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>

Fixed all comments.

* Dropped csb1724 defconfig.
* Added patch to remove MV643XX_ETH_SHARED_NAME and MV643XX_ETH_NAME
* Dropped un-necessary D-T irq fixup code


Ian Molton (7):
  Initial csb1724 board support (FDT)
  mv643xx.c: Remove magic numbers.
  mv643xx.c: Add basic device tree support.
  kirkwood: Add fixups for DT based mv643xx ethernet.
  csb1724: Enable device tree based mv643xx ethernet support.
  DT: Convert all kirkwood boards with mv643xx that use DT
  NET: mv643xx: remove device name macro.

 Documentation/devicetree/bindings/net/mv643xx.txt |   75 +++++++++++++++
 arch/arm/boot/dts/kirkwood-csb1724.dts            |   49 ++++++++++
 arch/arm/boot/dts/kirkwood-dnskw.dtsi             |    9 ++
 arch/arm/boot/dts/kirkwood-dreamplug.dts          |   18 ++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts          |    8 ++
 arch/arm/boot/dts/kirkwood-ib62x0.dts             |   10 ++
 arch/arm/boot/dts/kirkwood-iconnect.dts           |   10 ++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi              |   17 ++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts         |    8 +-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts         |    8 +-
 arch/arm/boot/dts/kirkwood-ts219.dtsi             |    3 +
 arch/arm/boot/dts/kirkwood.dtsi                   |   33 +++++++
 arch/arm/mach-kirkwood/Kconfig                    |    7 ++
 arch/arm/mach-kirkwood/Makefile                   |    1 +
 arch/arm/mach-kirkwood/Makefile.boot              |    1 +
 arch/arm/mach-kirkwood/board-csb1724.c            |   60 ++++++++++++
 arch/arm/mach-kirkwood/board-dnskw.c              |    7 +-
 arch/arm/mach-kirkwood/board-dreamplug.c          |   13 +--
 arch/arm/mach-kirkwood/board-dt.c                 |   11 +++
 arch/arm/mach-kirkwood/board-goflexnet.c          |    7 +-
 arch/arm/mach-kirkwood/board-ib62x0.c             |    7 +-
 arch/arm/mach-kirkwood/board-iconnect.c           |    7 +-
 arch/arm/mach-kirkwood/board-lsxl.c               |   13 +--
 arch/arm/mach-kirkwood/board-ts219.c              |   10 +-
 arch/arm/mach-kirkwood/common.c                   |   26 +++++-
 arch/arm/mach-kirkwood/common.h                   |    9 ++
 arch/arm/plat-orion/common.c                      |   24 ++---
 arch/powerpc/platforms/chrp/pegasos_eth.c         |    4 +-
 arch/powerpc/sysdev/mv64x60_dev.c                 |    5 +-
 drivers/net/ethernet/marvell/mv643xx_eth.c        |  104 ++++++++++++++++++---
 include/linux/mv643xx_eth.h                       |    2 -
 31 files changed, 476 insertions(+), 90 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/mv643xx.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-csb1724.dts
 create mode 100644 arch/arm/mach-kirkwood/board-csb1724.c

-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:46 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:46 +0100
Subject: [PATCH v3 1/7] Initial csb1724 board support (FDT)
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-2-git-send-email-ian.molton@codethink.co.uk>

This patch adds support for the csb1724 SoM.

It includes serial and SATA support.

Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 arch/arm/boot/dts/kirkwood-csb1724.dts |   30 ++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig         |    7 ++++
 arch/arm/mach-kirkwood/Makefile        |    1 +
 arch/arm/mach-kirkwood/Makefile.boot   |    1 +
 arch/arm/mach-kirkwood/board-csb1724.c |   59 ++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c      |    4 +++
 arch/arm/mach-kirkwood/common.h        |    6 ++++
 7 files changed, 108 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-csb1724.dts
 create mode 100644 arch/arm/mach-kirkwood/board-csb1724.c

diff --git a/arch/arm/boot/dts/kirkwood-csb1724.dts b/arch/arm/boot/dts/kirkwood-csb1724.dts
new file mode 100644
index 0000000..44dfe9a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-csb1724.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Cogent CSB1724-88F-628X SoM";
+	compatible = "cogent,csb1724", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		sata at 80000 {
+			nr-ports = <2>;
+			status = "ok";
+		};
+	};
+
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..6d51c50 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -109,6 +109,13 @@ config MACH_LSXL_DT
 	  Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
 	  Flattened Device Tree.
 
+config MACH_CSB1724_DT
+	bool "Cogent CSB1724 SoM (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Cogent CSB1724 SoM, using Flattened Device Tree.
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..665ed63 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_CSB1724_DT)		+= board-csb1724.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 2a576ab..899bc80 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -2,6 +2,7 @@
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
 
+dtb-$(CONFIG_MACH_CSB1724_DT) += kirkwood-csb1724.dtb
 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
 dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
 dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
diff --git a/arch/arm/mach-kirkwood/board-csb1724.c b/arch/arm/mach-kirkwood/board-csb1724.c
new file mode 100644
index 0000000..979112d
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-csb1724.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2012 (C), Ian Molton <ian.molton at codethink.co.uk>
+ *
+ * arch/arm/mach-kirkwood/board-csb1724.c
+ *
+ * Cogent csb1724 Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include "mpp.h"
+
+static unsigned int csb1724_mpp_config[] __initdata = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
+	MPP12_SD_CLK,
+	MPP13_SD_CMD,
+	MPP14_SD_D0,
+	MPP15_SD_D1,
+	MPP16_SD_D2,
+	MPP17_SD_D3,
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GE1_TXD0,
+	MPP21_GE1_TXD1,
+	MPP22_GE1_TXD2,
+	MPP23_GE1_TXD3,
+	MPP24_GE1_RXD0,
+	MPP25_GE1_RXD1,
+	MPP26_GE1_RXD2,
+	MPP27_GE1_RXD3,
+	MPP30_GE1_RXCTL,
+	MPP31_GE1_RXCLK,
+	MPP32_GE1_TCLKOUT,
+	MPP33_GE1_TXCTL,
+	MPP34_SATA1_ACTn,
+	MPP35_SATA0_ACTn,
+	MPP36_TW1_SDA,
+	MPP37_TW1_SCK,
+};
+
+void __init csb1724_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(csb1724_mpp_config);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..7679f7f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
+	if (of_machine_is_compatible("cogent,csb1724"))
+		csb1724_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"cogent,csb1724",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..8aab1ae 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_CSB1724_DT
+void csb1724_init(void);
+#else
+static inline void csb1724_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:49 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:49 +0100
Subject: [PATCH v3 4/7] kirkwood: Add fixups for DT based mv643xx ethernet.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-5-git-send-email-ian.molton@codethink.co.uk>

This patch adds auxdata for kirkwood ethernet and an ethernet clock setup
helper function allowing the mv643xx clock to be kept enabled after boot so
that the MAC address(es) are not lost.

Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 arch/arm/mach-kirkwood/board-dt.c |    7 +++++++
 arch/arm/mach-kirkwood/common.c   |   22 ++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h   |    3 +++
 3 files changed, 32 insertions(+)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 7679f7f..aa213b6 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/mv643xx_eth.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -33,6 +34,10 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
 	OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
 	OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1072000, "mv643xx_eth_port.0",
+			NULL),
+	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1076000, "mv643xx_eth_port.1",
+			NULL),
 	{},
 };
 
@@ -92,6 +97,8 @@ static void __init kirkwood_dt_init(void)
 
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
+
+	kirkwood_eth_clock_fixup();
 }
 
 static const char *kirkwood_dt_board_compat[] = {
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c4b64ad..57b91cf 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -18,6 +18,7 @@
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -293,6 +294,27 @@ void __init kirkwood_ehci_init(void)
 	orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
 }
 
+/* Fixup ethernet clocks for DT based kirkwood platforms.
+ * This is required because if the clock is not kept running, the
+ * Interface will forget its MAC address.
+ */
+#ifdef CONFIG_OF
+void __init kirkwood_eth_clock_fixup(void)
+{
+	struct device_node *np;
+
+	np = of_find_node_by_name(NULL, "egiga0");
+	if (np && of_device_is_available(np))
+		clk_prepare_enable(ge0);
+	of_node_put(np);
+
+	np = of_find_node_by_name(NULL, "egiga1");
+	if (np && of_device_is_available(np))
+		clk_prepare_enable(ge1);
+	of_node_put(np);
+
+}
+#endif
 
 /*****************************************************************************
  * GE00
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 8aab1ae..7183718 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -36,6 +36,9 @@ void kirkwood_enable_pcie(void);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
 
 void kirkwood_ehci_init(void);
+#ifdef CONFIG_OF
+void kirkwood_eth_clock_fixup(void);
+#endif
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:50 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:50 +0100
Subject: [PATCH v3 5/7] csb1724: Enable device tree based mv643xx ethernet
 support.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-6-git-send-email-ian.molton@codethink.co.uk>

        This patch enables mv643xx based ethernet built into the SoM on the
        csb1724, via flattened device tree.

        Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 arch/arm/boot/dts/kirkwood-csb1724.dts |   19 ++++++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi        |   33 ++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-csb1724.c |    1 +
 3 files changed, 53 insertions(+)

diff --git a/arch/arm/boot/dts/kirkwood-csb1724.dts b/arch/arm/boot/dts/kirkwood-csb1724.dts
index 44dfe9a..f43f8dd 100644
--- a/arch/arm/boot/dts/kirkwood-csb1724.dts
+++ b/arch/arm/boot/dts/kirkwood-csb1724.dts
@@ -25,6 +25,25 @@
 			nr-ports = <2>;
 			status = "ok";
 		};
+
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		smi1: mdio at 76000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <0>;
+			status = "ok";
+		};
+
+		egiga1 {
+			phy_addr = <1>;
+			status = "ok";
+		};
+
 	};
 
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616..f5f1f92 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -76,6 +76,39 @@
 			status = "okay";
 		};
 
+		smi0: mdio at 72000 {
+			compatible = "marvell,mdio-mv643xx";
+			reg = <0x72000 0x4000>;
+			interrupts = <46>;
+			tx_csum_limit = <1600>;
+			status = "disabled";
+		};
+
+		egiga0 {
+			compatible = "marvell,mv643xx-eth";
+			reg = <0x72000 0x4000>;
+			mdio = <&smi0>;
+			interrupts = <11>;
+			status = "disabled";
+		};
+
+		smi1: mdio at 76000 {
+			compatible = "marvell,mdio-mv643xx";
+			reg = <0x76000 0x4000>;
+			interrupts = <47>;
+			shared_smi = <&smi0>;
+			tx_csum_limit = <1600>;
+			status = "disabled";
+		};
+
+		egiga1 {
+			compatible = "marvell,mv643xx-eth";
+			reg = <0x76000 0x4000>;
+			mdio = <&smi1>;
+			interrupts = <15>;
+			status = "disabled";
+		};
+
 		sata at 80000 {
 			compatible = "marvell,orion-sata";
 			reg = <0x80000 0x5000>;
diff --git a/arch/arm/mach-kirkwood/board-csb1724.c b/arch/arm/mach-kirkwood/board-csb1724.c
index 979112d..9c58b92 100644
--- a/arch/arm/mach-kirkwood/board-csb1724.c
+++ b/arch/arm/mach-kirkwood/board-csb1724.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include "common.h"
 #include "mpp.h"
 
 static unsigned int csb1724_mpp_config[] __initdata = {
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:48 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:48 +0100
Subject: [PATCH v3 3/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-4-git-send-email-ian.molton@codethink.co.uk>

    This patch adds basic device tree support to the mv643xx ethernet driver.

    It should be enough for most current users of the device, and should allow
    a painless migration.

    Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 Documentation/devicetree/bindings/net/mv643xx.txt |   75 +++++++++++++++++
 drivers/net/ethernet/marvell/mv643xx_eth.c        |   93 +++++++++++++++++++--
 2 files changed, 161 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/mv643xx.txt

diff --git a/Documentation/devicetree/bindings/net/mv643xx.txt b/Documentation/devicetree/bindings/net/mv643xx.txt
new file mode 100644
index 0000000..2727f79
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mv643xx.txt
@@ -0,0 +1,75 @@
+mv643xx related nodes.
+
+marvell,mdio-mv643xx:
+
+Required properties:
+
+ - interrupts : <a> where a is the SMI interrupt number.
+ - reg : the base address and size of the controllers register space.
+
+Optional properties:
+ - shared_smi : on some chips, the second PHY is "shared", meaning it is
+	really accessed via the first SMI controller. It is passed in this
+	way due to the present structure of the driver, which requires the
+	base address for the MAC to be passed in via the SMI controllers
+	platform data.
+ - tx_csum_limit : on some devices, this option is required for proper
+	operation wrt. jumbo frames.
+
+
+Example:
+
+smi0: mdio at 72000 {
+	compatible = "marvell,mdio-mv643xx";
+	reg = <0x72000 0x4000>;
+	interrupts = <46>;
+	tx_csum_limit = <1600>;
+	status = "disabled";
+};
+
+smi1: mdio at 76000 {
+	compatible = "marvell,mdio-mv643xx";
+	reg = <0x76000 0x4000>;
+	interrupts = <47>;
+	shared_smi = <&smi0>;
+	tx_csum_limit = <1600>;
+	status = "disabled";
+};
+
+
+
+marvell,mv643xx-eth:
+
+Required properties:
+ - interrupts : the port interrupt number.
+ - mdio : phandle of the smi device as drescribed above
+
+Optional properties:
+ - port_number : the port number on this bus.
+ - phy_addr : the PHY address.
+ - reg : should match the mdio reg this device is attached to.
+	this is a required hack for now due to the way the
+	driver is constructed. This allows the device clock to be
+	kept running so that the MAC is not lost after boot.
+
+
+Example:
+
+egiga0 {
+	compatible = "marvell,mv643xx-eth";
+	reg = <0x72000 0x4000>;
+	mdio = <&smi0>;
+	port_number = <0>;
+	phy_addr = <0x80>;
+	interrupts = <11>;
+};
+
+egiga1 {
+	compatible = "marvell,mv643xx-eth";
+	reg = <0x76000 0x4000>;
+	mdio = <&smi1>;
+	port_number = <0>;
+	phy_addr = <0x81>;
+	interrupts = <15>;
+};
+
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 92497eb..bb80050 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -48,6 +48,9 @@
 #include <linux/ethtool.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
@@ -2601,7 +2604,7 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_eth_version_printed;
-	struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
+	struct mv643xx_eth_shared_platform_data *pd;
 	struct mv643xx_eth_shared_private *msp;
 	const struct mbus_dram_target_info *dram;
 	struct resource *res;
@@ -2625,6 +2628,26 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	if (msp->base == NULL)
 		goto out_free;
 
+	if (pdev->dev.of_node) {
+		struct device_node *np = NULL;
+
+		/* when all users of this driver use FDT, we can remove this */
+		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+		if (!pd) {
+			dev_dbg(&pdev->dev, "Could not allocate platform data\n");
+			goto out_free;
+		}
+
+		of_property_read_u32(pdev->dev.of_node,
+			"tx_csum_limit", &pd->tx_csum_limit);
+
+		np = of_parse_phandle(pdev->dev.of_node, "shared_smi", 0);
+		if (np)
+			pd->shared_smi = of_find_device_by_node(np);
+
+	} else {
+		pd = pdev->dev.platform_data;
+	}
 	/*
 	 * Set up and register SMI bus.
 	 */
@@ -2657,7 +2680,6 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (res != NULL) {
 		int err;
-
 		err = request_irq(res->start, mv643xx_eth_err_irq,
 				  IRQF_SHARED, "mv643xx_eth", msp);
 		if (!err) {
@@ -2675,6 +2697,10 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 
 	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
 					pd->tx_csum_limit : 9 * 1024;
+
+	if (pdev->dev.of_node)
+		kfree(pd);  /* If we created a fake pd, free it now */
+
 	infer_hw_params(msp);
 
 	platform_set_drvdata(pdev, msp);
@@ -2708,12 +2734,21 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id mv_mdio_dt_ids[] __devinitdata = {
+	{ .compatible = "marvell,mdio-mv643xx", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mv_mdio_dt_ids);
+#endif
+
 static struct platform_driver mv643xx_eth_shared_driver = {
 	.probe		= mv643xx_eth_shared_probe,
 	.remove		= mv643xx_eth_shared_remove,
 	.driver = {
 		.name	= MV643XX_ETH_SHARED_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv_mdio_dt_ids),
 	},
 };
 
@@ -2873,7 +2908,36 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	struct resource *res;
 	int err;
 
-	pd = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		struct device_node *np = NULL;
+
+		/* when all users of this driver use FDT, we can remove this */
+		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+		if (!pd) {
+			dev_dbg(&pdev->dev, "Could not allocate platform data\n");
+			return -ENOMEM;
+		}
+
+		of_property_read_u32(pdev->dev.of_node,
+			"port_number", &pd->port_number);
+
+		if (!of_property_read_u32(pdev->dev.of_node,
+				"phy_addr", &pd->phy_addr))
+			pd->phy_addr = MV643XX_ETH_PHY_ADDR(pd->phy_addr);
+		else
+			pd->phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT;
+
+		np = of_parse_phandle(pdev->dev.of_node, "mdio", 0);
+		if (np) {
+			pd->shared = of_find_device_by_node(np);
+		} else {
+			kfree(pd);
+			return -ENODEV;
+		}
+	} else {
+		pd = pdev->dev.platform_data;
+	}
+
 	if (pd == NULL) {
 		dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
 		return -ENODEV;
@@ -2881,12 +2945,15 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	if (pd->shared == NULL) {
 		dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
-		return -ENODEV;
+		err = -ENODEV;
+		goto out_free_pd;
 	}
 
 	dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
-	if (!dev)
-		return -ENOMEM;
+	if (!dev) {
+		err = -ENOMEM;
+		goto out_free_pd;
+	}
 
 	mp = netdev_priv(dev);
 	platform_set_drvdata(pdev, mp);
@@ -2923,6 +2990,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 
 	init_pscr(mp, pd->speed, pd->duplex);
 
+	if (pdev->dev.of_node)
+		kfree(pd); /* If we created a fake pd, free it now */
 
 	mib_counters_clear(mp);
 
@@ -2942,7 +3011,6 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
 	mp->rx_oom.data = (unsigned long)mp;
 	mp->rx_oom.function = oom_timer_wrapper;
 
-
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	BUG_ON(!res);
 	dev->irq = res->start;
@@ -2991,6 +3059,8 @@ out:
 	}
 #endif
 	free_netdev(dev);
+out_free_pd:
+	kfree(pd);
 
 	return err;
 }
@@ -3030,6 +3100,14 @@ static void mv643xx_eth_shutdown(struct platform_device *pdev)
 		port_reset(mp);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id mv_eth_dt_ids[] __devinitdata = {
+	{ .compatible = "marvell,mv643xx-eth", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mv_eth_dt_ids);
+#endif
+
 static struct platform_driver mv643xx_eth_driver = {
 	.probe		= mv643xx_eth_probe,
 	.remove		= mv643xx_eth_remove,
@@ -3037,6 +3115,7 @@ static struct platform_driver mv643xx_eth_driver = {
 	.driver = {
 		.name	= MV643XX_ETH_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mv_eth_dt_ids),
 	},
 };
 
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:52 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:52 +0100
Subject: [PATCH v3 7/7] NET: mv643xx: remove device name macro.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-8-git-send-email-ian.molton@codethink.co.uk>

Coding style: remove the macros:

MV643XX_ETH_NAME and
MV643XX_ETH_SHARED_NAME

Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 arch/arm/mach-kirkwood/board-dt.c          |    4 ++--
 arch/arm/mach-kirkwood/common.c            |    4 ++--
 arch/arm/plat-orion/common.c               |   24 ++++++++++++------------
 arch/powerpc/platforms/chrp/pegasos_eth.c  |    4 ++--
 arch/powerpc/sysdev/mv64x60_dev.c          |    5 ++---
 drivers/net/ethernet/marvell/mv643xx_eth.c |    8 ++++----
 include/linux/mv643xx_eth.h                |    2 --
 7 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index aa213b6..91784d9 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -34,9 +34,9 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
 	OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
 	OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
-	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1072000, "mv643xx_eth_port.0",
+	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1072000, "mv643xx_eth.0",
 			NULL),
-	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1076000, "mv643xx_eth_port.1",
+	OF_DEV_AUXDATA("marvell,mv643xx", 0xf1076000, "mv643xx_eth.1",
 			NULL),
 	{},
 };
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 57b91cf..eb0a253 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -264,8 +264,8 @@ void __init kirkwood_clk_init(void)
 	/* clkdev entries, mapping clks to devices */
 	orion_clkdev_add(NULL, "orion_spi.0", runit);
 	orion_clkdev_add(NULL, "orion_spi.1", runit);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
+	orion_clkdev_add(NULL, "mv643xx_eth.0", ge0);
+	orion_clkdev_add(NULL, "mv643xx_eth.1", ge1);
 	orion_clkdev_add(NULL, "orion_wdt", tclk);
 	orion_clkdev_add("0", "sata_mv.0", sata0);
 	orion_clkdev_add("1", "sata_mv.0", sata1);
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index d245a87..d4a6467 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -42,10 +42,10 @@ void __init orion_clkdev_init(struct clk *tclk)
 {
 	orion_clkdev_add(NULL, "orion_spi.0", tclk);
 	orion_clkdev_add(NULL, "orion_spi.1", tclk);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
-	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
+	orion_clkdev_add(NULL, "mv643xx_eth.0", tclk);
+	orion_clkdev_add(NULL, "mv643xx_eth.1", tclk);
+	orion_clkdev_add(NULL, "mv643xx_eth.2", tclk);
+	orion_clkdev_add(NULL, "mv643xx_eth.3", tclk);
 	orion_clkdev_add(NULL, "orion_wdt", tclk);
 	orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
 }
@@ -264,7 +264,7 @@ static struct resource orion_ge00_shared_resources[] = {
 };
 
 static struct platform_device orion_ge00_shared = {
-	.name		= MV643XX_ETH_SHARED_NAME,
+	.name		= "mdio-mv643xx",
 	.id		= 0,
 	.dev		= {
 		.platform_data	= &orion_ge00_shared_data,
@@ -279,7 +279,7 @@ static struct resource orion_ge00_resources[] = {
 };
 
 static struct platform_device orion_ge00 = {
-	.name		= MV643XX_ETH_NAME,
+	.name		= "mv643xx_eth",
 	.id		= 0,
 	.num_resources	= 1,
 	.resource	= orion_ge00_resources,
@@ -316,7 +316,7 @@ static struct resource orion_ge01_shared_resources[] = {
 };
 
 static struct platform_device orion_ge01_shared = {
-	.name		= MV643XX_ETH_SHARED_NAME,
+	.name		= "mdio-mv643xx",
 	.id		= 1,
 	.dev		= {
 		.platform_data	= &orion_ge01_shared_data,
@@ -331,7 +331,7 @@ static struct resource orion_ge01_resources[] = {
 };
 
 static struct platform_device orion_ge01 = {
-	.name		= MV643XX_ETH_NAME,
+	.name		= "mv643xx_eth",
 	.id		= 1,
 	.num_resources	= 1,
 	.resource	= orion_ge01_resources,
@@ -368,7 +368,7 @@ static struct resource orion_ge10_shared_resources[] = {
 };
 
 static struct platform_device orion_ge10_shared = {
-	.name		= MV643XX_ETH_SHARED_NAME,
+	.name		= "mdio-mv643xx",
 	.id		= 1,
 	.dev		= {
 		.platform_data	= &orion_ge10_shared_data,
@@ -383,7 +383,7 @@ static struct resource orion_ge10_resources[] = {
 };
 
 static struct platform_device orion_ge10 = {
-	.name		= MV643XX_ETH_NAME,
+	.name		= "mv643xx_eth",
 	.id		= 1,
 	.num_resources	= 2,
 	.resource	= orion_ge10_resources,
@@ -420,7 +420,7 @@ static struct resource orion_ge11_shared_resources[] = {
 };
 
 static struct platform_device orion_ge11_shared = {
-	.name		= MV643XX_ETH_SHARED_NAME,
+	.name		= "mdio-mv643xx",
 	.id		= 1,
 	.dev		= {
 		.platform_data	= &orion_ge11_shared_data,
@@ -435,7 +435,7 @@ static struct resource orion_ge11_resources[] = {
 };
 
 static struct platform_device orion_ge11 = {
-	.name		= MV643XX_ETH_NAME,
+	.name		= "mv643xx_eth",
 	.id		= 1,
 	.num_resources	= 2,
 	.resource	= orion_ge11_resources,
diff --git a/arch/powerpc/platforms/chrp/pegasos_eth.c b/arch/powerpc/platforms/chrp/pegasos_eth.c
index 039fc8e..1832127 100644
--- a/arch/powerpc/platforms/chrp/pegasos_eth.c
+++ b/arch/powerpc/platforms/chrp/pegasos_eth.c
@@ -41,7 +41,7 @@ static struct resource mv643xx_eth_shared_resources[] = {
 };
 
 static struct platform_device mv643xx_eth_shared_device = {
-	.name		= MV643XX_ETH_SHARED_NAME,
+	.name		= "mdio-mv643xx",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(mv643xx_eth_shared_resources),
 	.resource	= mv643xx_eth_shared_resources,
@@ -71,7 +71,7 @@ static struct mv643xx_eth_platform_data eth_port1_pd = {
 };
 
 static struct platform_device eth_port1_device = {
-	.name		= MV643XX_ETH_NAME,
+	.name		= "mv643xx_eth",
 	.id		= 1,
 	.num_resources	= ARRAY_SIZE(mv643xx_eth_port1_resources),
 	.resource	= mv643xx_eth_port1_resources,
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 0f6af41..ca404ec 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -221,8 +221,7 @@ static struct platform_device * __init mv64x60_eth_register_shared_pdev(
 	if (err)
 		return ERR_PTR(err);
 
-	pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id,
-					       r, 1);
+	pdev = platform_device_register_simple("mdio-mv643xx", id, i r, 1);
 	return pdev;
 }
 
@@ -296,7 +295,7 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
 
 	of_node_put(phy);
 
-	pdev = platform_device_alloc(MV643XX_ETH_NAME, id);
+	pdev = platform_device_alloc("mv643xx_eth", id);
 	if (!pdev)
 		return -ENOMEM;
 
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index bb80050..9371601 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2746,7 +2746,7 @@ static struct platform_driver mv643xx_eth_shared_driver = {
 	.probe		= mv643xx_eth_shared_probe,
 	.remove		= mv643xx_eth_shared_remove,
 	.driver = {
-		.name	= MV643XX_ETH_SHARED_NAME,
+		.name	= "mdio-mv643xx",
 		.owner	= THIS_MODULE,
 		.of_match_table = of_match_ptr(mv_mdio_dt_ids),
 	},
@@ -3113,7 +3113,7 @@ static struct platform_driver mv643xx_eth_driver = {
 	.remove		= mv643xx_eth_remove,
 	.shutdown	= mv643xx_eth_shutdown,
 	.driver = {
-		.name	= MV643XX_ETH_NAME,
+		.name	= "mv643xx_eth",
 		.owner	= THIS_MODULE,
 		.of_match_table = of_match_ptr(mv_eth_dt_ids),
 	},
@@ -3145,5 +3145,5 @@ MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
 	      "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
-MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
+MODULE_ALIAS("platform:" "mdio-mv643xx");
+MODULE_ALIAS("platform:" "mv643xx_eth");
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 51bf8ad..33dc6f4 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -7,8 +7,6 @@
 
 #include <linux/mbus.h>
 
-#define MV643XX_ETH_SHARED_NAME		"mv643xx_eth"
-#define MV643XX_ETH_NAME		"mv643xx_eth_port"
 #define MV643XX_ETH_SHARED_REGS		0x2000
 #define MV643XX_ETH_SHARED_REGS_SIZE	0x2000
 #define MV643XX_ETH_BAR_4		0x2220
-- 
1.7.9.5



From ian.molton at codethink.co.uk  Tue Aug  7 10:34:51 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue,  7 Aug 2012 15:34:51 +0100
Subject: [PATCH v3 6/7] DT: Convert all kirkwood boards with mv643xx that use
 DT
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <1344350092-24050-7-git-send-email-ian.molton@codethink.co.uk>

This patch converts all present DT capable kirkwood board configurations
to use DT to configure the mv643xx ethernet controller.

Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
---
 arch/arm/boot/dts/kirkwood-dnskw.dtsi     |    9 +++++++++
 arch/arm/boot/dts/kirkwood-dreamplug.dts  |   18 ++++++++++++++++++
 arch/arm/boot/dts/kirkwood-goflexnet.dts  |    8 ++++++++
 arch/arm/boot/dts/kirkwood-ib62x0.dts     |   10 ++++++++++
 arch/arm/boot/dts/kirkwood-iconnect.dts   |   10 ++++++++++
 arch/arm/boot/dts/kirkwood-lsxl.dtsi      |   17 +++++++++++++++++
 arch/arm/boot/dts/kirkwood-ts219-6281.dts |    8 +++++++-
 arch/arm/boot/dts/kirkwood-ts219-6282.dts |    8 +++++++-
 arch/arm/boot/dts/kirkwood-ts219.dtsi     |    3 +++
 arch/arm/mach-kirkwood/board-dnskw.c      |    7 +------
 arch/arm/mach-kirkwood/board-dreamplug.c  |   13 ++-----------
 arch/arm/mach-kirkwood/board-goflexnet.c  |    7 +------
 arch/arm/mach-kirkwood/board-ib62x0.c     |    7 +------
 arch/arm/mach-kirkwood/board-iconnect.c   |    7 +------
 arch/arm/mach-kirkwood/board-lsxl.c       |   13 ++-----------
 arch/arm/mach-kirkwood/board-ts219.c      |   10 +---------
 16 files changed, 98 insertions(+), 57 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655..214fe0b 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -65,5 +65,14 @@
 				reg = <0x7b00000 0x500000>;
 			};
 		};
+
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <8>;
+			status = "ok";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 26e281f..c27ed1c 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -53,6 +53,24 @@
 			status = "okay";
 			nr-ports = <1>;
 		};
+
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		smi1: mdio at 76000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <0>;
+			status = "ok";
+		};
+
+		egiga1 {
+			phy_addr = <1>;
+			status = "ok";
+		};
 	};
 
 	gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 7c8238f..f03dbd0 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -50,6 +50,14 @@
 			nr-ports = <2>;
 		};
 
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <0>;
+			status = "ok";
+		};
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 66794ed..8c462a1 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -45,6 +45,16 @@
 			};
 
 		};
+
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <8>;
+			status = "ok";
+		};
+
 	};
 
 	gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 52d9470..9fc82be 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -30,6 +30,16 @@
 			clock-frequency = <200000000>;
 			status = "ok";
 		};
+
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <b>;
+			status = "ok";
+		};
+
 	};
 	gpio-leds {
 		compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 8ac51c0..2f47661 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -40,6 +40,23 @@
 				};
 			};
 		};
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
+
+		smi1: mdio at 76000 {
+			status = "ok";
+		};
+
+		egiga0 {
+			phy_addr = <0>;
+			status = "ok";
+		};
+
+		egiga1 {
+			phy_addr = <8>;
+			status = "ok";
+		};
 	};
 
 	gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index ccbf327..4ca49b5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -3,6 +3,12 @@
 /include/ "kirkwood-ts219.dtsi"
 
 / {
+	ocp at f1000000 {
+		egiga0 {
+			phy_addr = <8>;
+			status = "ok";
+		};
+	};
 	gpio_keys {
 		compatible = "gpio-keys";
 		#address-cells = <1>;
@@ -18,4 +24,4 @@
 			gpios = <&gpio0 16 1>;
 		};
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index fbe9932..40f3c61 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -3,6 +3,12 @@
 /include/ "kirkwood-ts219.dtsi"
 
 / {
+	ocp at f1000000 {
+		egiga0 {
+			phy_addr = <0>;
+			status = "ok";
+		};
+	};
 	gpio_keys {
 		compatible = "gpio-keys";
 		#address-cells = <1>;
@@ -18,4 +24,4 @@
 			gpios = <&gpio1 5 1>;
 		};
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27c..06caf41 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -74,5 +74,8 @@
 			status = "okay";
 			nr-ports = <2>;
 		};
+		smi0: mdio at 72000 {
+			status = "ok";
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab3506..4d8216b 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
@@ -29,10 +28,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 static unsigned int dnskw_mpp_config[] __initdata = {
 	MPP13_UART1_TXD,	/* Custom ... */
 	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
@@ -112,7 +107,7 @@ void __init dnskw_init(void)
 	kirkwood_mpp_conf(dnskw_mpp_config);
 
 	kirkwood_ehci_init();
-	kirkwood_ge00_init(&dnskw_ge00_data);
+	kirkwood_ge00_init(NULL);
 
 	platform_device_register(&dnskw_fan_device);
 
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index aeb234d..b97a112 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
@@ -34,14 +33,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
 static struct mvsdio_platform_data dreamplug_mvsdio_data = {
 	/* unfortunately the CD signal has not been connected */
 };
@@ -65,7 +56,7 @@ void __init dreamplug_init(void)
 	kirkwood_mpp_conf(dreamplug_mpp_config);
 
 	kirkwood_ehci_init();
-	kirkwood_ge00_init(&dreamplug_ge00_data);
-	kirkwood_ge01_init(&dreamplug_ge01_data);
+	kirkwood_ge00_init(NULL);
+	kirkwood_ge01_init(NULL);
 	kirkwood_sdio_init(&dreamplug_mvsdio_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 413e2c8..be7437d 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
@@ -36,10 +35,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
 static unsigned int goflexnet_mpp_config[] __initdata = {
 	MPP29_GPIO,	/* USB Power Enable */
 	MPP47_GPIO,	/* LED Orange */
@@ -67,5 +62,5 @@ void __init goflexnet_init(void)
 		pr_err("can't setup GPIO 29 (USB Power Enable)\n");
 	kirkwood_ehci_init();
 
-	kirkwood_ge00_init(&goflexnet_ge00_data);
+	kirkwood_ge00_init(NULL);
 }
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index cfc47f8..0a29183 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -16,7 +16,6 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <asm/mach-types.h>
@@ -27,10 +26,6 @@
 
 #define IB62X0_GPIO_POWER_OFF	24
 
-static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 static unsigned int ib62x0_mpp_config[] __initdata = {
 	MPP0_NF_IO2,
 	MPP1_NF_IO3,
@@ -62,7 +57,7 @@ void __init ib62x0_init(void)
 	kirkwood_mpp_conf(ib62x0_mpp_config);
 
 	kirkwood_ehci_init();
-	kirkwood_ge00_init(&ib62x0_ge00_data);
+	kirkwood_ge00_init(NULL);
 	if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
 	    gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
 		pm_power_off = ib62x0_power_off;
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198..220f0d4 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -17,7 +17,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/mtd/partitions.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -26,10 +25,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mv643xx_eth_platform_data iconnect_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
-};
-
 static unsigned int iconnect_mpp_config[] __initdata = {
 	MPP12_GPIO,
 	MPP35_GPIO,
@@ -92,7 +87,7 @@ void __init iconnect_init(void)
 	kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
 
 	kirkwood_ehci_init();
-	kirkwood_ge00_init(&iconnect_ge00_data);
+	kirkwood_ge00_init(NULL);
 
 	platform_device_register(&iconnect_button_device);
 }
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 83d8975..60331d1 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -18,7 +18,6 @@
 #include <linux/ata_platform.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/gpio-fan.h>
 #include <linux/input.h>
@@ -28,14 +27,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 static unsigned int lsxl_mpp_config[] __initdata = {
 	MPP10_GPO,	/* HDD Power Enable */
 	MPP11_GPIO,	/* USB Vbus Enable */
@@ -126,8 +117,8 @@ void __init lsxl_init(void)
 	gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
 
 	kirkwood_ehci_init();
-	kirkwood_ge00_init(&lsxl_ge00_data);
-	kirkwood_ge01_init(&lsxl_ge01_data);
+	kirkwood_ge00_init(NULL);
+	kirkwood_ge01_init(NULL);
 	platform_device_register(&lsxl_fan_device);
 
 	/* register power-off method */
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 1750e68..7e7fe6c 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -29,10 +28,6 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
-static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
-};
-
 static unsigned int qnap_ts219_mpp_config[] __initdata = {
 	MPP0_SPI_SCn,
 	MPP1_SPI_MOSI,
@@ -62,10 +57,7 @@ void __init qnap_dt_ts219_init(void)
 	kirkwood_mpp_conf(qnap_ts219_mpp_config);
 
 	kirkwood_pcie_id(&dev, &rev);
-	if (dev == MV88F6282_DEV_ID)
-		qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
-
-	kirkwood_ge00_init(&qnap_ts219_ge00_data);
+	kirkwood_ge00_init(NULL);
 	kirkwood_ehci_init();
 
 	pm_power_off = qnap_tsx1x_power_off;
-- 
1.7.9.5



From hs at denx.de  Tue Aug  7 10:35:16 2012
From: hs at denx.de (Heiko Schocher)
Date: Tue, 07 Aug 2012 16:35:16 +0200
Subject: [PATCH v7] ARM: davinci: i2c: add OF support
In-Reply-To: <1343632872-25896-1-git-send-email-hs@denx.de>
References: <1343632872-25896-1-git-send-email-hs@denx.de>
Message-ID: <502127A4.2040505@denx.de>

Hello,

On 30.07.2012 09:21, Heiko Schocher wrote:
> add of support for the davinci i2c driver.
>
> Signed-off-by: Heiko Schocher<hs at denx.de>
> Signed-off-by: Sekhar Nori<nsekhar at ti.com>
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: linux-i2c at vger.kernel.org
> Cc: Ben Dooks<ben-linux at fluff.org>
> Cc: Wolfram Sang<w.sang at pengutronix.de>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> Cc: Sekhar Nori<nsekhar at ti.com>
> Cc: Wolfgang Denk<wd at denx.de>
> Cc: Sylwester Nawrocki<s.nawrocki at samsung.com>
>
> ---
> - changes for v2:
> - add comments from Sylwester Nawrocki<s.nawrocki at samsung.com>:
>    - use "cell-index" instead "id"
>    - OF_DEV_AUXDATA in the machine code, instead pre-define platform
>      device name
> - add comment from Grant Likely:
>    - removed "id" resp. "cell-index" completely
>    - fixed documentation
>    - use of_match_ptr()
>    - use devm_kzalloc() for allocating plattform data mem
>    - fixed a whitespace issue
> - no changes for v3
> - changes for v4
>    remove "pinmux-handle" property as discussed here:
>    http://www.spinics.net/lists/arm-kernel/msg175701.html
>    with Nori Sekhar
>
> - changes for v5
>    add comments from Grant Likely:
>    - do not change value of dev->dev->platform_data, instead
>      hold a copy in davinci_i2c_dev.
>
> - changes for v6:
>    add comments from Sekhar Nori:
>    - removed unneccessary include
>    - merge patch from Sekhar Nori:
>      setup the newly introduced dev->pdata member correctly once in
>      probe ->  i2c_get_plattformdata(() not needed, remove a lot of
>      checks for pdata in code
>    - add Signed-off-by: Sekhar Nori<nsekhar at ti.com>
>    - patch no longer in patchserie, as it has no dependencies.
>
> - changes for v7:
>    add comments from Wolfram Sang:
>    - move Documentation/devicetree/bindings/arm/davinci/i2c.txt
>      to Documentation/devicetree/bindings/i2c/davinci.txt
>    - remove bus-delay property
>
>   Documentation/devicetree/bindings/i2c/davinci.txt |   28 ++++++++++++
>   drivers/i2c/busses/i2c-davinci.c                  |   48 ++++++++++++++++-----
>   2 files changed, 65 insertions(+), 11 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/i2c/davinci.txt

ping ... any comments?

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


From linux at arm.linux.org.uk  Tue Aug  7 10:37:48 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 15:37:48 +0100
Subject: [PATCH] ARM: ep93xx: clockevent support
In-Reply-To: <1344338474.18237.6.camel@localhost>
References: <1344338474.18237.6.camel@localhost>
Message-ID: <20120807143748.GE18957@n2100.arm.linux.org.uk>

On Tue, Aug 07, 2012 at 02:21:14PM +0300, Yan Burman wrote:
> +/*
> + * timer4 is a 40 Bit timer, separated in a 32bit and a 8 bit
> + * register, EP93XX_TIMER4_VALUE_LOW stores 32 bit word. The
> + * controlregister is in EP93XX_TIMER4_VALUE_HIGH
> + */
> +static cycle_t ep93xx_get_cycles(struct clocksource *unused)
> +{
> +	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
> +}
>  
> -	/* Enable lost jiffy timer.  */
> -	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
> -			EP93XX_TIMER4_VALUE_HIGH);
> +static struct clocksource clocksource_ep93xx = {
> +	.name		= "ep93xx_timer4",
> +	.rating		= 200,
> +	.read		= ep93xx_get_cycles,
> +	.mask		= 0xFFFFFFFF,
> +	.shift		= 20,
> +	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
> +};

Well done for porting this over to the clockevent/clocksource stuff.

Please have a look at the mmio clocksource helpers in
drivers/clocksource/mmio.c which I think you'll find will do everything
that you need without requiring all this code.


From vaibhav.bedia at ti.com  Tue Aug  7 10:40:46 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Tue, 7 Aug 2012 14:40:46 +0000
Subject: [PATCH v3] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344343087-8947-1-git-send-email-balbi@ti.com>
References: <B5906170F1614E41A8A28DE3B8D121433EB3087D@DBDE01.ent.ti.com>
 <1344343087-8947-1-git-send-email-balbi@ti.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D121433EB30BDA@DBDE01.ent.ti.com>

On Tue, Aug 07, 2012 at 18:08:07, Balbi, Felipe wrote:
> this helps us reduce unnecessary pm transitions
> in case we have another i2c message starting soon.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>

FWIW, Acked-by: Vaibhav Bedia <vaibhav.bedia at ti.com> 


From m.szyprowski at samsung.com  Tue Aug  7 10:53:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 07 Aug 2012 16:53:25 +0200
Subject: [PATCH v3 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent
 if available
In-Reply-To: <1344246924-32620-4-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-4-git-send-email-hdk@igel.co.jp>
Message-ID: <012701cd74ac$6a617060$3f245120$%szyprowski@samsung.com>

Hello,

On Monday, August 06, 2012 11:55 AM Hideki EIRAKU wrote:

> Previously the vb2_dma_contig_mmap() function was using a dma_addr_t as a
> physical address.  The two addressses are not necessarily the same.
> For example, when using the IOMMU funtion on certain platforms, dma_addr_t
> addresses are not directly mappable physical address.
> dma_mmap_coherent() maps the address correctly.
> It is available on ARM platforms.
> 
> Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>

I'm sorry for bringing this issue now, once you have already created v3 of your
patches, but similar patch has been already proposed some time ago. It is already
processed together with general videobuf2-dma-contig redesign and dma-buf extensions
by Tomasz Stanislawski.

See post http://thread.gmane.org/gmane.comp.video.dri.devel/70402/focus=49461 and
http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/49438 

It doesn't use conditional code inside videobuf2 allocator and rely entirely on 
dma-mapping subsystem to provide a working dma_mmap_coherent/writecombine/attrs() 
function. When it was posted, it relied on the dma-mapping extensions, which now
have been finally merged to v3.6-rc1. Now I wonder if there are any architectures, 
which don't use dma_map_ops based dma-mapping framework, which might use 
videobuf2-dma-conting module. 

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From arnd at arndb.de  Tue Aug  7 10:56:41 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 14:56:41 +0000
Subject: [PATCH v3 3/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <1344350092-24050-4-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <1344350092-24050-4-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <201208071456.41412.arnd@arndb.de>

On Tuesday 07 August 2012, Ian Molton wrote:
>     This patch adds basic device tree support to the mv643xx ethernet driver.
> 
>     It should be enough for most current users of the device, and should allow
>     a painless migration.
> 
>     Signed-off-by: Ian Molton <ian.molton at codethink.co.uk>
> ---
>  Documentation/devicetree/bindings/net/mv643xx.txt |   75 +++++++++++++++++
>  drivers/net/ethernet/marvell/mv643xx_eth.c        |   93 +++++++++++++++++++--
>  2 files changed, 161 insertions(+), 7 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/mv643xx.txt

Hi Ian,

Have you had a look at Documentation/devicetree/bindings/marvell.txt ?

I think it documents some of the same thing, so it would be good
to keep all of that in one place. We might also want to move
some of the code from arch/powerpc/sysdev/mv64x60_dev.c
to live in the same place as the device driver.

	Arnd


From paul at pwsan.com  Tue Aug  7 11:00:02 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 7 Aug 2012 09:00:02 -0600 (MDT)
Subject: [PATCH 1/2] ARM: OMAP: clean up some smatch warnings, fix some
 printk(KERN_ERR ...
In-Reply-To: <20120807104023.GV11011@atomide.com>
References: <20120807103009.8053.69389.stgit@dusk.lan>
 <20120807103439.8053.65054.stgit@dusk.lan>
 <20120807104023.GV11011@atomide.com>
Message-ID: <alpine.DEB.2.00.1208070859190.23956@utopia.booyaka.com>

On Tue, 7 Aug 2012, Tony Lindgren wrote:

> I think these will cause new randconfig warnings without CONFIG_BUG set.

Thanks for the comment.  Did not know BUG() could be disabled.  Will drop 
those changes.


- Paul


From s.nawrocki at samsung.com  Tue Aug  7 11:05:30 2012
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Tue, 07 Aug 2012 17:05:30 +0200
Subject: [PATCH V4 0/2] arm: samsung: Move FIMD headers to	include/video/
In-Reply-To: <20120807143342.GD18957@n2100.arm.linux.org.uk>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
 <20120807143342.GD18957@n2100.arm.linux.org.uk>
Message-ID: <50212EBA.5000600@samsung.com>

On 08/07/2012 04:33 PM, Russell King - ARM Linux wrote:
> On Tue, Aug 07, 2012 at 06:04:30PM +0530, Leela Krishna Amudala wrote:
>>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --------------------
>>  drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
>>  drivers/video/s3c-fb.c                             |    2 +-
>>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  152 +++++++++++++++++--
> 
> Isn't include/video for framebuffer drivers?  Isn't this more a DRM thing?
> Wouldn't include/drm therefore be more appropriate?

Those headers are now used by both: framebuffer and Exynos DRM
driver. And probably the framebuffer driver has more users, as it
also covers older FIMD devices than those found on exynos4/5 SoCs.

So include/video seems equally right (or wrong) as include/drm.

There have been some efforts, or at least requirements raised, to
create some common low level API for framebuffer and DRM drivers,
but nothing has clarified yet AFAICS.


From robherring2 at gmail.com  Tue Aug  7 11:19:48 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 07 Aug 2012 10:19:48 -0500
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
Message-ID: <50213214.7050505@gmail.com>

On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
> If the module requires only one clocksource to function, then
> driver can very well call clk_get() api with "con_id = NULL",
> 
>        clk = clk_get(dev, NULL);
> 
> And platform code should respect this and return valid clk handle.
> That means, now the clk_get() api would rely on dev_id, and platform
> code should either have clk node with matching dev_id (with con_id=NULL)
> or return dummy clk node.
> 
> With DT support, we can fix the dev_id for particular module
> using "struct of_dev_auxdata" to satisfy above clk framework requirement.
> 
> In case of AM33XX, we required this for the DCAN module, so this
> patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> ---
> This patch is boot tested on BeagleBone platform, and checked for
> clk_get() return value in d_can module driver.
> 
>  arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
>  1 files changed, 17 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index 6f93a20..c9b7903 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>  	{ }
>  };
> 
> +/*
> + * Lookup table for attaching a specific name and platform_data pointer to
> + * devices as they get created by of_platform_populate(). Ideally this table
> + * would not exist, but the current clock implementation depends on some devices
> + * having a specific name OR to satisfy NULL con_id requirement from driver.
> + */
> +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
> +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
> +	{ },
> +};

Adding an additional clkdev lookup accomplishes the same thing and is a
cleaner solution.

Rob

> +
>  static void __init omap_generic_init(void)
>  {
>  	omap_sdrc_init(NULL, NULL);
> 
> -	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
> +	if (of_machine_is_compatible("ti,am33xx"))
> +		of_platform_populate(NULL, omap_dt_match_table,
> +				am33xx_auxdata_lookup, NULL);
> +	else
> +		of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
>  }
> 
>  #ifdef CONFIG_SOC_OMAP2420
> --
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From m.szyprowski at samsung.com  Tue Aug  7 11:22:02 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 07 Aug 2012 17:22:02 +0200
Subject: [PATCH v3 1/4] ARM: dma-mapping: define ARCH_HAS_DMA_MMAP_COHERENT
In-Reply-To: <1344246924-32620-2-git-send-email-hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-2-git-send-email-hdk@igel.co.jp>
Message-ID: <013301cd74b0$691eba60$3b5c2f20$%szyprowski@samsung.com>

Hi Hideki,

On Monday, August 06, 2012 11:55 AM Hideki EIRAKU wrote:

> ARCH_HAS_DMA_MMAP_COHERENT indicates that there is dma_mmap_coherent() API
> in this architecture.  The name is already defined in PowerPC.
> 
> Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
> ---
>  arch/arm/include/asm/dma-mapping.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> index bbef15d..f41cd30 100644
> --- a/arch/arm/include/asm/dma-mapping.h
> +++ b/arch/arm/include/asm/dma-mapping.h
> @@ -187,6 +187,7 @@ extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
>  			struct dma_attrs *attrs);
> 
>  #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
> +#define ARCH_HAS_DMA_MMAP_COHERENT
> 
>  static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
>  				  void *cpu_addr, dma_addr_t dma_addr,
> --
> 1.7.0.4

I will take this patch to my dma-mapping kernel tree, to the fixes branch.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From lee.jones at linaro.org  Tue Aug  7 11:31:13 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 7 Aug 2012 16:31:13 +0100
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120806153503.GH10524@gmail.com>
 <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
Message-ID: <20120807153112.GF10719@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Tue, 7 Aug 2012 12:27:24 +0100
Subject: [PATCH 1/1 v3] i2c: Add default configuration into the Nomadik I2C
 driver.

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 5e6f1ee..61b00ed 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -350,10 +350,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -911,20 +907,32 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* fast mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
-	struct nmk_i2c_controller *pdata =
-			adev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = adev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
-	if (!pdata) {
-		dev_warn(&adev->dev, "no platform data\n");
-		return -ENODEV;
-	}
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&adev->dev, "cannot allocate memory\n");
-- 
1.7.9.5


From sourav.poddar at ti.com  Tue Aug  7 11:49:15 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 7 Aug 2012 21:19:15 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <2AE404CF-E456-408A-B7A2-D9B3D331C58E@dominion.thruhere.net>
References: <1343997486-710-1-git-send-email-sourav.poddar@ti.com>
 <1343997486-710-4-git-send-email-sourav.poddar@ti.com>
 <2AE404CF-E456-408A-B7A2-D9B3D331C58E@dominion.thruhere.net>
Message-ID: <CAKdam56BCGkfwM8XKnULJ0bXDu6UF+mZqcyMgdqDZJ=oLZp3Gg@mail.gmail.com>

Hi Koen,

On Tue, Aug 7, 2012 at 6:24 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>
> Op 3 aug. 2012, om 14:38 heeft Sourav Poddar <sourav.poddar at ti.com> het volgende geschreven:
>
>> Add keypad data node in omap5 device tree file.
>> Also fill the device tree binding parameters
>> with the required value in "omap5-evm" dts file.
>>
>> Tested on omap5430 evm with 3.5 custom kernel.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Acked-by: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>> arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
>> arch/arm/boot/dts/omap5.dtsi    |    5 +++++
>> 2 files changed, 17 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
>> index 45a8aeb..09fe941 100644
>> --- a/arch/arm/boot/dts/omap5-evm.dts
>> +++ b/arch/arm/boot/dts/omap5-evm.dts
>> @@ -17,6 +17,18 @@
>>               device_type = "memory";
>>               reg = <0x80000000 0x40000000>; /* 1 GB */
>>       };
>> +
>> +     keypad {
>> +             keypad,num-rows = <8>;
>> +             keypad,num-columns = <8>;
>> +             linux,keymap = < 0x02020073
>> +                     0x02030072
>> +                     0x020400e7
>> +                     0x02050066
>> +                     0x0206006b
>> +                     0x020700d9 >;
>> +             linux,input-no-autorepeat;
>> +     };
>
> Again not a coment on your patch, but on DT:
>
> If DT bindings must be OS independent, what then, is that linux keycode doing there?
>
Currently, for all matrix connected keyboards the keymap are defined
in the scope of the
linux key code since that is a stable and standardized interface at this time.

For the above reason , computation of the  keymap uses linux keycode

  row << 24 | column << 16 | linux-key-code
I think this is the primary reason for keeping "linux" prefix with this
property.
> regards,
>
> Koen
>


From will.deacon at arm.com  Tue Aug  7 11:49:48 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  7 Aug 2012 16:49:48 +0100
Subject: [PATCH 2/2] ARM: hw_breakpoints: allow single-byte watchpoints on all
 addresses
In-Reply-To: <1344354588-28153-1-git-send-email-will.deacon@arm.com>
References: <1344354588-28153-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344354588-28153-2-git-send-email-will.deacon@arm.com>

Breakpoint validation currently fails for single-byte watchpoints on
addresses ending in 11b. There is no reason to forbid such a watchpoint,
so extend the validation code to allow it.

Cc: Ulrich Weigand <Ulrich.Weigand at de.ibm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/hw_breakpoint.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 418d980..4eedfde 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -610,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 		/* Aligned */
 		break;
 	case 1:
-		/* Allow single byte watchpoint. */
-		if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
-			break;
 	case 2:
 		/* Allow halfword watchpoints and breakpoints. */
 		if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
 			break;
+	case 3:
+		/* Allow single byte watchpoint. */
+		if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
+			break;
 	default:
 		ret = -EINVAL;
 		goto out;
-- 
1.7.4.1



From will.deacon at arm.com  Tue Aug  7 11:49:47 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  7 Aug 2012 16:49:47 +0100
Subject: [PATCH 1/2] ARM: hw_breakpoint: don't rely on dfsr to show watchpoint
 access type
Message-ID: <1344354588-28153-1-git-send-email-will.deacon@arm.com>

>From ARM debug architecture v7.1 onwards, a watchpoint exception causes
the DFAR to be updated with the faulting data address. However, DFSR.WnR
takes an UNKNOWN value and therefore cannot be used in general to
determine the access type that triggered the watchpoint.

This patch forbids watchpoints without an overflow handler from
specifying a specific access type (load/store). Those with overflow
handlers must be able to handle false positives potentially triggered by
a watchpoint of a different access type on the same address. For
SIGTRAP-based handlers (i.e. ptrace), this should have no impact.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/hw_breakpoint.c |   54 ++++++++++++++++++++++++++++-----------
 1 files changed, 39 insertions(+), 15 deletions(-)

diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index ba386bd..418d980 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -159,6 +159,12 @@ static int debug_arch_supported(void)
 		arch >= ARM_DEBUG_ARCH_V7_1;
 }
 
+/* Can we determine the watchpoint access type from the fsr? */
+static int debug_exception_updates_fsr(void)
+{
+	return 0;
+}
+
 /* Determine number of WRP registers available. */
 static int get_num_wrp_resources(void)
 {
@@ -619,18 +625,34 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 	info->address &= ~alignment_mask;
 	info->ctrl.len <<= offset;
 
-	/*
-	 * Currently we rely on an overflow handler to take
-	 * care of single-stepping the breakpoint when it fires.
-	 * In the case of userspace breakpoints on a core with V7 debug,
-	 * we can use the mismatch feature as a poor-man's hardware
-	 * single-step, but this only works for per-task breakpoints.
-	 */
-	if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
-	    !core_has_mismatch_brps() || !bp->hw.bp_target)) {
-		pr_warning("overflow handler required but none found\n");
-		ret = -EINVAL;
+	if (!bp->overflow_handler) {
+		/*
+		 * Mismatch breakpoints are required for single-stepping
+		 * breakpoints.
+		 */
+		if (!core_has_mismatch_brps())
+			return -EINVAL;
+
+		/* We don't allow mismatch breakpoints in kernel space. */
+		if (arch_check_bp_in_kernelspace(bp))
+			return -EPERM;
+
+		/*
+		 * Per-cpu breakpoints are not supported by our stepping
+		 * mechanism. */
+		if (!bp->hw.bp_target)
+			return -EINVAL;
+
+		/*
+		 * We only support specific access types if the fsr
+		 * reports them.
+		 */
+		if (!debug_exception_updates_fsr() &&
+		    (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
+		     info->ctrl.type == ARM_BREAKPOINT_STORE))
+			return -EINVAL;
 	}
+
 out:
 	return ret;
 }
@@ -706,10 +728,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
 				goto unlock;
 
 			/* Check that the access type matches. */
-			access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
-				 HW_BREAKPOINT_R;
-			if (!(access & hw_breakpoint_type(wp)))
-				goto unlock;
+			if (debug_exception_updates_fsr()) {
+				access = (fsr & ARM_FSR_ACCESS_MASK) ?
+					  HW_BREAKPOINT_W : HW_BREAKPOINT_R;
+				if (!(access & hw_breakpoint_type(wp)))
+					goto unlock;
+			}
 
 			/* We have a winner. */
 			info->trigger = addr;
-- 
1.7.4.1



From hvaibhav at ti.com  Tue Aug  7 11:53:08 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Tue, 7 Aug 2012 15:53:08 +0000
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <50213214.7050505@gmail.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
 <50213214.7050505@gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>

On Tue, Aug 07, 2012 at 20:49:48, Rob Herring wrote:
> On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
> > If the module requires only one clocksource to function, then
> > driver can very well call clk_get() api with "con_id = NULL",
> > 
> >        clk = clk_get(dev, NULL);
> > 
> > And platform code should respect this and return valid clk handle.
> > That means, now the clk_get() api would rely on dev_id, and platform
> > code should either have clk node with matching dev_id (with con_id=NULL)
> > or return dummy clk node.
> > 
> > With DT support, we can fix the dev_id for particular module
> > using "struct of_dev_auxdata" to satisfy above clk framework requirement.
> > 
> > In case of AM33XX, we required this for the DCAN module, so this
> > patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
> > 
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Paul Walmsley <paul at pwsan.com>
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > ---
> > This patch is boot tested on BeagleBone platform, and checked for
> > clk_get() return value in d_can module driver.
> > 
> >  arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
> >  1 files changed, 17 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> > index 6f93a20..c9b7903 100644
> > --- a/arch/arm/mach-omap2/board-generic.c
> > +++ b/arch/arm/mach-omap2/board-generic.c
> > @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
> >  	{ }
> >  };
> > 
> > +/*
> > + * Lookup table for attaching a specific name and platform_data pointer to
> > + * devices as they get created by of_platform_populate(). Ideally this table
> > + * would not exist, but the current clock implementation depends on some devices
> > + * having a specific name OR to satisfy NULL con_id requirement from driver.
> > + */
> > +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
> > +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
> > +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
> > +	{ },
> > +};
> 
> Adding an additional clkdev lookup accomplishes the same thing and is a
> cleaner solution.
> 

That is also required and I have submitted patch for the same -

http://www.spinics.net/lists/arm-kernel/msg187998.html


With DT support, I am getting dev_id as -

 - Without "reg" property: d_can.16 and d_can.17,
   (I believe it changes dynamically here)

 - With "reg" property: 481cc000.d_can and 481d0000.d_can

Which is not so intuitive, I would like to see them as per Spec/TRM, so 
doesn't this patch make sense?

Similar thing has already been done for other platforms too.

Thanks,
Vaibhav


From ian.molton at codethink.co.uk  Tue Aug  7 11:56:59 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Tue, 07 Aug 2012 16:56:59 +0100
Subject: [PATCH v3 3/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208071456.41412.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <1344350092-24050-4-git-send-email-ian.molton@codethink.co.uk>
 <201208071456.41412.arnd@arndb.de>
Message-ID: <50213ACB.6040301@codethink.co.uk>

On 07/08/12 15:56, Arnd Bergmann wrote:

> Hi Ian,
>
> Have you had a look at Documentation/devicetree/bindings/marvell.txt
> ?

Nope. I had no idea it was hiding there.

> I think it documents some of the same thing,

Not really. It documents some godawful hack that recycled the platform
device -based driver and provided a DT binding for it, just for PPC.

I cant even *find* anything that implements code for whatever
"marvell,mv64360-mdio" might be. I'm sure it might exist somewhere.

> We might also want to move some of the
> code from arch/powerpc/sysdev/mv64x60_dev.c to live in the same place
> as the device driver.

I hope not. I don't really want to touch that stuff at all. If it works
the way it
is, then it can stay that way. If the PPC folk want to send patches to
add the
properties they use to the driver, then they can do. I'll send an email
their
way and see if they want to join in.

>From my perspective, the next thing that needs to happen to the driver is
for it to be broken up into ethernet and mdio drivers, so that we can
get rid
of all this shared_smi craziness... But that's for another patch series.

-Ian




From gcembed at gmail.com  Tue Aug  7 11:56:46 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Tue, 07 Aug 2012 17:56:46 +0200
Subject: Custom platform for commercial device
Message-ID: <50213ABE.6070305@gmail.com>

Hello,
I have license related questions :

1) if I create and sell a device which is a fork of an existing 
platform, should I have to publish code of this new platform and/or give 
the code to customer if he asks it ?

2) Should I have to mention that my device is powered by Linux kernel ?
For a PC software, the GPL must be displayed at installation time but 
for embedded devices (ie. if a closed source software is used to send 
new kernel to the device) ?

3) Can I send patches to this list to add this new platform to be able 
maintain it more easily when kernel change implementation of some drivers ?

Thank you for these informations.
Best regards,
Ga?tan Carlier.


From linux at arm.linux.org.uk  Tue Aug  7 12:13:33 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 17:13:33 +0100
Subject: Custom platform for commercial device
In-Reply-To: <50213ABE.6070305@gmail.com>
References: <50213ABE.6070305@gmail.com>
Message-ID: <20120807161333.GF18957@n2100.arm.linux.org.uk>

On Tue, Aug 07, 2012 at 05:56:46PM +0200, Ga?tan Carlier wrote:
> Hello,
> I have license related questions :

You should ask your solicitor these questions.

**** DISCLAIMER ****
What is below is my understanding of the GPL license, which is the
only license which allows you to make use of the Linux kernel - which
includes a substantial amount of code authored by myself.

> 1) if I create and sell a device which is a fork of an existing  
> platform, should I have to publish code of this new platform and/or give  
> the code to customer if he asks it ?

The GPL gives you essentially two options - one of them is that you
supply your products with a copy of the _full_ machine-readable source
code which was used to generate the GPL licensed executables.  See 3(a).

The second option is that you provide a written offer of the source
code to anyone who buys your product.  You must supply a copy of the
source to anyone who has bought your product within three years of
that purchase taking place.  See 3(b).

3(c) also comes into play if you decide to go down this route, because
it's not only your direct customers who can request a copy of the source,
it's anyone who _they_ have passed your product or the binaries in your
product to.  So the effect of 3(b) + 3(c) is that you have to supply
anyone who requests a copy of the source with it.

> 2) Should I have to mention that my device is powered by Linux kernel ?
> For a PC software, the GPL must be displayed at installation time but  
> for embedded devices (ie. if a closed source software is used to send  
> new kernel to the device) ?

2(c) comes into play for this.  I believe the Linux kernel not to be an
interactive program (it isn't gdb.)  Therefore, it doesn't display a
GPL notice at startup, and therefore there's no need for it to display
such a notice at boot time.

It would be nice if manufacturers would credit where they got a
substantial amount of code from in their products, whether it be in a
manual or something, but the GPL does not explicitly require it.

Note that what you aren't able to do is to remove or prevent any GPL'd
program which already displays its license from doing so when
incorporating it in a product.

> 3) Can I send patches to this list to add this new platform to be able  
> maintain it more easily when kernel change implementation of some drivers 
> ?

We always encourage that, provided the code isn't just "chucked over the
wall" at us.  In other words, we'd like any code that makes its way into
the kernel to be maintained and used.  Otherwise, it becomes a maintenance
burden, and will eventually be removed.

And here's a reminder of the disclaimer:
**** DISCLAIMER ****
What is above is my understanding of the GPL license, which is the
only license which allows you to make use of the Linux kernel - which
includes a substantial amount of code authored by myself.



From gcembed at gmail.com  Tue Aug  7 12:20:59 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Tue, 07 Aug 2012 18:20:59 +0200
Subject: Custom platform for commercial device
In-Reply-To: <20120807161333.GF18957@n2100.arm.linux.org.uk>
References: <50213ABE.6070305@gmail.com>
 <20120807161333.GF18957@n2100.arm.linux.org.uk>
Message-ID: <5021406B.4040302@gmail.com>

Hello,
On 08/07/2012 06:13 PM, Russell King - ARM Linux wrote:
> On Tue, Aug 07, 2012 at 05:56:46PM +0200, Ga?tan Carlier wrote:
>> Hello,
>> I have license related questions :
>
> You should ask your solicitor these questions.
>
> **** DISCLAIMER ****
> What is below is my understanding of the GPL license, which is the
> only license which allows you to make use of the Linux kernel - which
> includes a substantial amount of code authored by myself.
>
>> 1) if I create and sell a device which is a fork of an existing
>> platform, should I have to publish code of this new platform and/or give
>> the code to customer if he asks it ?
>
> The GPL gives you essentially two options - one of them is that you
> supply your products with a copy of the _full_ machine-readable source
> code which was used to generate the GPL licensed executables.  See 3(a).
>
> The second option is that you provide a written offer of the source
> code to anyone who buys your product.  You must supply a copy of the
> source to anyone who has bought your product within three years of
> that purchase taking place.  See 3(b).
>
> 3(c) also comes into play if you decide to go down this route, because
> it's not only your direct customers who can request a copy of the source,
> it's anyone who _they_ have passed your product or the binaries in your
> product to.  So the effect of 3(b) + 3(c) is that you have to supply
> anyone who requests a copy of the source with it.
>
Sorry, after reading COPYING, I found answers for this question but I 
forgot to remove this question from my draft.

>> 2) Should I have to mention that my device is powered by Linux kernel ?
>> For a PC software, the GPL must be displayed at installation time but
>> for embedded devices (ie. if a closed source software is used to send
>> new kernel to the device) ?
>
> 2(c) comes into play for this.  I believe the Linux kernel not to be an
> interactive program (it isn't gdb.)  Therefore, it doesn't display a
> GPL notice at startup, and therefore there's no need for it to display
> such a notice at boot time.
>
> It would be nice if manufacturers would credit where they got a
> substantial amount of code from in their products, whether it be in a
> manual or something, but the GPL does not explicitly require it.
>
> Note that what you aren't able to do is to remove or prevent any GPL'd
> program which already displays its license from doing so when
> incorporating it in a product.
>
>> 3) Can I send patches to this list to add this new platform to be able
>> maintain it more easily when kernel change implementation of some drivers
>> ?
>
> We always encourage that, provided the code isn't just "chucked over the
> wall" at us.  In other words, we'd like any code that makes its way into
> the kernel to be maintained and used.  Otherwise, it becomes a maintenance
> burden, and will eventually be removed.
>
> And here's a reminder of the disclaimer:
> **** DISCLAIMER ****
> What is above is my understanding of the GPL license, which is the
> only license which allows you to make use of the Linux kernel - which
> includes a substantial amount of code authored by myself.
>
Thanks.
Regards,
Ga?tan Carlier.


From jlu at pengutronix.de  Tue Aug  7 12:29:45 2012
From: jlu at pengutronix.de (Jan Luebbe)
Date: Tue,  7 Aug 2012 18:29:45 +0200
Subject: [PATCH] omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX are
 selected
Message-ID: <1344356985-21801-1-git-send-email-jlu@pengutronix.de>

When only ARCH_OMAP3 (or -2,-4,...) and SOC_AM33XX are selected, multi.h
doesn't set MULTI_OMAP2. In this case, cpu.h will simply define
cpu_is_omap24xx() as 1.

This causes problems for example for omap_hwmod.c:omap_hwmod_init which
checks for cpu_is_omap24xx() first, using the wrong soc_ops for AM33xx.

Fix this by defining MULTI_OMAP2 when using SOC_AM33XX together with
something else.

Signed-off-by: Jan Luebbe <jlu at pengutronix.de>
---
 arch/arm/plat-omap/include/plat/multi.h |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 045e320..324d31b 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -108,4 +108,13 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am33xx
+# endif
+#endif
+
 #endif	/* __PLAT_OMAP_MULTI_H */
-- 
1.7.10.4



From dave.martin at linaro.org  Tue Aug  7 12:48:22 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 7 Aug 2012 17:48:22 +0100
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
Message-ID: <20120807164822.GA2135@linaro.org>

On Mon, Aug 06, 2012 at 10:19:50AM -0500, Matt Sealey wrote:
> On Sun, Aug 5, 2012 at 6:03 PM, Anton Vorontsov
> <anton.vorontsov at linaro.org> wrote:
> > The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
> > passed to it, so it's pretty clear that the driver is absolutely sure
> > that the FIQ is routed via platform-specific IC, and that the cookie can
> > be used to mask/unmask FIQs. So, let's switch to the genirq routines,
> > since we're about to remove FIQ-specific variants.
> 
> I have a semi-related question about this;
> 
> Firstly, I was planning on (re-)submitting a patch for the
> arch/arm/plat-mxc/ssi-fiq.S code which made it build in ARM mode
> (since the code isn't Thumb compatible for various reasons) as it was
> a blocker for a Thumb2-compiled kernel. Since the code was only needed
> on ARM-capable processors it wouldn't cause a problem. Sascha signed
> off on this a long while back and I've been testing it on all my
> internal kernel versions, and I don't see any ill effects (that said I
> don't have an i.MX28 or so to really verify it, I can't see why it
> would not work). I realise this is redundant right now, anyway, since
> it's only really enabled on imx_v4_v5 configs and they don't support
> Thumb2 kernels anyway. What might be worth submitting is a switch to
> add the ".arm" directive anyway simply for correctness since it could
> never be compiled for Thumb anyway. We all know what gnu as is like.
> 
> Looking at it again on the back of these patches, I noticed the
> ssi-fiq.S code is compiled in when SND_IMX_SOC is enabled - of course,
> it's only needed in the kernel if SND_SOC_IMX_PCM_FIQ is enabled (the
> code that uses the FIQ stuff is only compiled then) but here on the
> Efika MX builds it's being built, and I noticed it when it broke my
> build because of the above. I'm therefore going to submit a patch
> which changes the ifdef SND_SOC_IMX to ifdef SND_SOC_IMX_PCM_FIQ so
> it's not compiled in unless absolutely necessary. However, there was a
> rumble that this code may disappear or be reworked in the future
> making this also quite redundant. Since it's not in the
> imx_v6_v7_defconfig anyway, I'm sure this only didn't get noticed
> because nobody's building Thumb2 kernels and nobody is trying configs
> with audio enabled anyway..
> 
> This begs the question, could there be something somewhere hidden deep
> in the kernel that is enabled by default or in some config somewhere
> that requires "select FIQ" in it's Kconfig entry, but isn't being
> enabled? On i.MX the only thing turning it on is that code, but other
> ARM arch enable it by default. Since things have been moved to more
> generic routines I can't in my mind guarantee that such a patch would
> be well tested here since I would be relying on symbols missing or
> defines not there anymore.. I have no real way to ensure that it would
> work on boards I don't have.
> 
> So, is the first patch (ssi-fiq.S .arm) worth it? I think the
> SND_SOC_IMX_PCM_FIQ patch is worth it for v6_v7 systems anyway, but
> maybe this should have been caught sooner, so should I update the
> defconfig to enable some kind of audio bus support (Babbage has it in
> the DT so is a needful thing for testing, I figure..)? And does anyone
> forsee any problems with that option changing and the only "user" of
> "FIQ" in the Kconfigs going away now all the FIQ-specific symbols went
> away outside of the generic irq subsystem?

I hit this issue some time ago when I was trying to do a Thumb2 build
of this kernel.

I don't remember having to fix the generic FIQ code just for this,
but I had a patch somewhere to swap r13 with another register in
ssi-fiq.S.  I think that use of r13 in ways not permitted for Thumb
was the only problem I found.  I can try to dig it out if you want.

In any case, it didn't seem worth pushing at the time, because it
seemed that the SSI FIQ code was not relevant to any v7 or later
platform -- so building that code for Thumb presumably doesn't make
sense.

Cheers
---Dave


From broonie at opensource.wolfsonmicro.com  Tue Aug  7 12:50:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 7 Aug 2012 17:50:20 +0100
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <20120807063558.GE1451@pengutronix.de>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
 <CAKGA1bkiHj=zMJXSzoGp3fpLS3POnFXSV5y7sYYFAikqoUT9tQ@mail.gmail.com>
 <20120806154951.GQ16861@opensource.wolfsonmicro.com>
 <CAKGA1b=_AOub_pEJJGBTb6Y7wLZaSYKQjFTyMVFSr_=9VX4wpg@mail.gmail.com>
 <20120806193734.GA16199@opensource.wolfsonmicro.com>
 <20120806201609.GX25644@pengutronix.de>
 <CAKGA1bmMqyL4gyLYcanEH=R=HuBjRCNRLjUEWCj8wmpi3HuL0g@mail.gmail.com>
 <20120806214121.GA26698@opensource.wolfsonmicro.com>
 <20120807063558.GE1451@pengutronix.de>
Message-ID: <20120807165019.GT16861@opensource.wolfsonmicro.com>

On Tue, Aug 07, 2012 at 08:35:58AM +0200, Sascha Hauer wrote:

> Nowadays the FIQ support is necessary only for AC97. The AC97 support in
> the SSI unit is buggy: It does not allow you to select the slots you
> want to receive. At least the wm9712 codec always sends (apart from the
> stereo data) data in slot (I think it is) 12. You find this data mixed
> in your audio stream. The FIQ driver skips this data to get a valid
> audio stream.

Right, any device with GPIO support will do this - it's how GPIO works
in AC'97.

> One other way to solve this would be to use dma here and to filter out
> the data afterwards.

Yup.  That's probably more sane but also more work to implement.


From linux at arm.linux.org.uk  Tue Aug  7 12:53:50 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 17:53:50 +0100
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <201208061402.22815.arnd@arndb.de>
 <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>
Message-ID: <20120807165350.GG18957@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 04:16:57PM +0200, Sebastian Hesselbarth wrote:
> After that I am definitely fine with removing non-DT support although
> there is neither DT support in u-boot installed on my CuBox nor
> mach-dove support in mainline u-boot.

As I have a Cubox, this is of interest to me.  However, not related to
your patches, here's some news I have on the Cubox.

Firstly, a big thanks to Nicolas Pitre for sending me this cute little
box.  Finally, I see my idea of having an ARM based Linux box as a
media player becoming a reality (I thought maybe the OMAP3430LDP would
do it, or maybe the OMAP4430SDP, but progress on OMAP platforms is
dreadfully slow - and complicated...)

I've recently pushed a fix into mainline (and stable) for VFP support
with Thumb instructions.  I noticed that the Cubox kernel had a different
fix, this "different" fix will need to be removed when Cubox folk update
to the next kernel from mainline.

Video support, not great.  The supplied Ubuntu Lucid stuff install
(including the latest dev kernel from the solid-run folk) doesn't work
with any of the tree HDMI devices I've tried it with:

. A Plasma TV refused to recognise the cubox existing.  Works with a PC
  running Linux.
. A LCD PC monitor with HDMI input.  If the monitor is disconnected, the
  Cubox booted, and the monitor connected, you get a picture, but you
  lose the top, left, bottom and right of the display off the side of the
  monitor.  No amount of adjusting on the monitor fixes this.
. A cheap LCD TV with HDMI input, 1080i (but not properly 1080p capable)
  only works when the Cubox is booted with the TV turned on and HDMI
  input selected.  If the Cubox is booted with the TV off or HDMI input
  deselected, it fails.  Even so, like the LCD PC monitor, the image is
  far too big.  I suspect there's something wrong with the HDMI chip
  setup.

What is obvious is that there is no HDMI hotplug support and reconfiguring
of the display.  So, I've been investigating the Linux DRM/DRI support -
both the kernel and X11 side, and I have something that is getting close
to being ready.  Last night I finally disabled the kernel dovefb driver,
and have X11 using solely my new DRM driver.

This gives us several advantages, not only does the DRM layer generate
hotplug events, but it also doesn't need such a large amount of "video
memory" reserved.  It can dynamically allocate objects for graphics
operations, and such like.  This, along side CMA should allow us to get
rid of quite a bit of the statically claimed RAM areas.  Another
advantage is that we can automatically reconfigure the X11 display on
hotplug to the capabilities of the attached monitor.  This works nicely
here. :)

	This brings up another off-topic point (not just about the
	cubox) - I think more people should be looking at the DRM
	stuff when they're creating video drivers.

The next thing to talk about is video overlay via the X11 Xvideo extension.
Yuck, this is not nice.  It relies upon using the X11 Xvideo SHM support,
using the shared memory as a two way buffer.  This buffer which is supposed
to contain graphic data passed from the app to X is instead used to pass
control and address pointers between the decoding application and the
kernel dovefb driver (!) and back again to the decoding application.  Note
that it doesn't even declare a different format for this kind of thing,
it merely relies on magic numbers and a checksum.

The side effect of that is applications using the Xvideo extension
properly do not work very well, partly because the formats they want to
use aren't presented by the dovefb X11 driver.

Now, when trying vlc on the cubox, it failed totally (the Qt libraries
from Ubuntu Lucid are built with neon support, and the Armada510 has
no Neon support - it is VFPv3 with only 16 double registers.)
Rebuilding libQtGui without Neon support fixes this (the cubox is currently
rebuilding the Qt package at the moment, which is going to take a while).
Next problem is there's something up with mpeg audio decoding, but ogg
decoding in vlc is fine.

With Qt fixed, DRM, and a better X11 driver, I now have vlc able to
reasonably display full screen video on the Cubox - and like on my PC,
it appears to play back at a destination resolution of 624x576 (so SD)
and then scales to the size you want the video to be.  Same for totem
with the same source material.

However, this won't be using the on-chip mpeg decoding (yet).  CPU
usage sits at around 30% while vlc playback is running.


From linux at arm.linux.org.uk  Tue Aug  7 13:00:26 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 18:00:26 +0100
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>
References: <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>
 <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>
Message-ID: <20120807170026.GH18957@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 01:41:06PM -0700, Colin Cross wrote:
> When testing coupled cpuidle on Exynos5, I found that sending an IPI
> does not successfully wake up CPU1.  CPU1 is in a wfe with interrupts
> masked, not a wfi, so an interrupt is not able to wake it up.  It
> tends to wake up anyways because the next time a spin lock is
> unlocked, often during a timer interrupt on CPU0, CPU0 executes an sev
> which wakes up CPU1.  You can see that the IPI is unnecessary by
> removing the gic_raise_softirq and replacing it with dsb_sev().

That's good news; that supports my assertion that the SMP bringup code
we see on various platforms as copies from the Realview code was done
without much thought about what is actually required.

It's good that you're looking into this, and fixing the code on the CPUs
you have access to.  I rather wish we'd made it a requirement for people
to _document_ the actual bringup conditions in the kernel for their
hardware before we accepted their SMP support code.


From lee.jones at linaro.org  Tue Aug  7 13:01:30 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 7 Aug 2012 18:01:30 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120806160226.GF29272@sirena.org.uk>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
 <20120806153750.GI10524@gmail.com>
 <20120806160226.GF29272@sirena.org.uk>
Message-ID: <20120807170129.GA3759@gmail.com>

On Mon, Aug 06, 2012 at 05:02:26PM +0100, Mark Brown wrote:
> On Mon, Aug 06, 2012 at 04:37:52PM +0100, Lee Jones wrote:
> > On Mon, Aug 06, 2012 at 01:19:15AM -0700, Dmitry Torokhov wrote:
> 
> > > > +	ponkey->irq_dbf = (np) ? ab8500_irq_get_virq(ab8500, irq_dbf) : irq_dbf;
> > > > +	ponkey->irq_dbr = (np) ? ab8500_irq_get_virq(ab8500, irq_dbr) : irq_dbr;
> 
> > > Why this isn't done inside ab8500_irq_get_virq()?
> 
> > There's no reason why it can't be.
> 
> > My first version of the patch did just that in fact.
> 
> > Would that be your preference?
> 
> Restating my comment elsewhere...  why do we even need to do this in
> _get_virq() - I'd *really* expect this to be handled by the irq domain
> code.

Okay, so I've just spent a small amount of time looking at this. I think
the best place for this would be in *_get_virq(), using the same logic that
selected a *_legacy or *_linear domain in the first place. The only thing 
the domain can test for is the 'type' of domain and the requested IRQ. This
is where the issue lies. If a hwirq to virq conversion is requested, but a
virq is passed (which happens in the non-DT case) a WARN() is triggered
because the irq passed is bigger than first_irq + size. I think *_get_virq()
should ensure that only a hwirq is passed to irq_create_mapping().

Let me know if you had other ideas.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From broonie at opensource.wolfsonmicro.com  Tue Aug  7 13:03:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 7 Aug 2012 18:03:34 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120807170129.GA3759@gmail.com>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
 <20120806153750.GI10524@gmail.com>
 <20120806160226.GF29272@sirena.org.uk>
 <20120807170129.GA3759@gmail.com>
Message-ID: <20120807170333.GV16861@opensource.wolfsonmicro.com>

On Tue, Aug 07, 2012 at 06:01:30PM +0100, Lee Jones wrote:

> Okay, so I've just spent a small amount of time looking at this. I think
> the best place for this would be in *_get_virq(), using the same logic that
> selected a *_legacy or *_linear domain in the first place. The only thing 
> the domain can test for is the 'type' of domain and the requested IRQ. This
> is where the issue lies. If a hwirq to virq conversion is requested, but a
> virq is passed (which happens in the non-DT case) a WARN() is triggered
> because the irq passed is bigger than first_irq + size. I think *_get_virq()
> should ensure that only a hwirq is passed to irq_create_mapping().

> Let me know if you had other ideas.

I'd expect your driver to always pass a hwirq into _get_virq() here.


From linux at arm.linux.org.uk  Tue Aug  7 13:04:28 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 18:04:28 +0100
Subject: [PATCH 2/2] ARM i.MX5: Hard reset the IPU during startup
In-Reply-To: <CAKGA1bkA3eEHn4sM277mzcRT5OUyipW18-k-X0nK+T9rrotJNw@mail.gmail.com>
References: <1338888630-25930-1-git-send-email-s.hauer@pengutronix.de>
 <1338888630-25930-3-git-send-email-s.hauer@pengutronix.de>
 <20429.57208.228315.164637@ipc1.ka-ro>
 <20120605110834.GQ30400@pengutronix.de>
 <CAKGA1bkA3eEHn4sM277mzcRT5OUyipW18-k-X0nK+T9rrotJNw@mail.gmail.com>
Message-ID: <20120807170428.GI18957@n2100.arm.linux.org.uk>

On Mon, Aug 06, 2012 at 04:31:50PM -0500, Matt Sealey wrote:
> There used to be an ATAG for finding the linear framebuffer and it's
> details but it got removed. This
> was from a long forgotten time when you could initialize a VGA
> graphics card and never care that
> it had an interrupt or not, since it never got used for your average,
> simple linear framebuffer operations.

No ATAG definitions have been removed from the kernel.  The one you
are referring to is:

#define ATAG_VIDEOLFB   0x54410008

and the associated struct tag_videolfb, which is still in the kernel
today.  What isn't there is the implementation which reads this data,
because only a few boards supported it, and they passed over some data
from this to their FB drivers.

So, when the boards were updated such that this became unnecessary,
unsurprisingly the users disappeared (because they were all in platform
code.)

We have never had a generic "framebuffer" driver which has used this
ATAG.  Or if one was created, it never came anywhere near mainline.

Either way, the situation is not as you describe above.


From linux at arm.linux.org.uk  Tue Aug  7 13:06:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 18:06:51 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
References: <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
Message-ID: <20120807170651.GJ18957@n2100.arm.linux.org.uk>

+1 on everything Nicolas has said below.  Full violent agreement there.

On Mon, Aug 06, 2012 at 08:08:57PM -0400, Nicolas Pitre wrote:
> On Mon, 6 Aug 2012, Matt Sealey wrote:
> 
> > On Mon, Aug 6, 2012 at 5:36 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > > On Mon, 6 Aug 2012, Matt Sealey wrote:
> > >
> > >> Right now there's already a fixed entry point - ARM kernels are fixed
> > >> entry point of relative 0 to the start of the loaded image. Okay, so
> > >> we can't format a totally valid ELF header, but in the event that we
> > >> want to encode all this information yet again, why reinvent the wheel?
> > >
> > > That's the point.  We do _not_ want to encode anything.
> > >
> > > By convention, if your CPU is ARM mode capable, then it must call the
> > > kernel in ARM mode, period.  Can't be simpler than that, right?  The
> > > bootloader shouldn't care if the kernel is itself ARM or Thumb, and the
> > > kernel shouldn't care if the bootloader is ARM or Thumb.
> > >
> > > If you have a real problem with this then let's hear it so it can be
> > > addressed.
> > 
> > I don't have a real *problem* with it, I just think since the kernel
> > can be compiled in both modes, but you may have some kind of remit to
> > not run ARM code (even if it's just a couple instructions at the
> > start) or some toolchain requirement or.. something.. it would be
> > entirely the bootloader's job to determine what mode it is in when it
> > jumps into the kernel. If you boot a Thumb bootloader and load an ARM
> > kernel, you'll get a crash. If you boot an ARM bootloader and a Thumb
> > kernel (with the current ARM instructions in head.S), you'll get a
> > crash. This is well defined, perfectly obvious, and I realise that..
> 
> And isn't it also rather silly?
> 
> History has told that the more "entirely the bootloader's job" we rely 
> on, the less reliable and interoperable we become.  Because you now have 
> to compile two kernels to fully validate your bootloader instead of only 
> one, and some people won't bother if the second kernel doesn't match 
> their own use case.
> 
> > But if you would need to micromanage the system such that they both
> > matched, or were perverse enough to build a Thumb bootloader and a
> > Thumb kernel, you might be counfounded that you actually created a
> > 99.99% Thumb bootloader which switched to ARM mode before going into
> > the kernel, and a 99.99% Thumb kernel but needed to jump into Thumb
> > mode after the first part of the kernel code?
> 
> I'm pragmatic enough to fully accept this impurity.
> 
> The x86 kernel does boot in 16-bit mode even if nobody compiles 16-bit 
> applications anymore.
> 
> > It should be possible (with that kernel config switch it would be) if 
> > you're into that kind of configurability to build your Thumb 
> > bootloader, build your Thumb kernel and have it never exit Thumb mode 
> > for any reason, even if it is just for some few bytes of very minor 
> > bootstrapping.
> 
> And what does this buy you?
> 
> > The same perfectly obvious caveats apply, but it's possible. The
> > question is, if you could do it, how would you make sure bootloaders
> > booted the right way? I would hazard a guess that given your opinion
> > on it, it would be just as good if they all just crashed.
> 
> Whereas right now it just works because the kernel is always entered in 
> ARM mode.
> 
> > So let's just patch out the ARM parts if you're building a Thumb
> > kernel on a Thumb-only device, and assume it was in Thumb mode all
> > along if another subordinate option was selected.. that way the kernel
> > can automatically fulfill one side of the contract in that you
> > configured "build thumb2 kernel" and it would contain 0% normal arm
> > code for ARMv7-M (or -R) and be able to be prompted to do so if you
> > were building for ARMv6k/ARMv7-A. Ordinary people would not turn it
> > on.. whacky weirdos like you and me might do it for proof of concept
> > ;)
> 
> No.  People will play with it as well and complain because their kernel 
> doesn't boot anymore.  We have enough real bug reports not to add to 
> them with futile ones.  And there are already way too many kernel config 
> options.
> 
> Some other people will hardcode Thumb mode entry in their bootloaders.  
> And if you wanted to compile your kernel in ARM mode for such a device 
> then you'd have the perverse need for a shim in Thumb mode at the 
> beginning of the kernel image to switch to ARM mode.
> 
> Whacky Weirdos can hack their kernel all they want.  That doesn't have 
> to be sanctioned in mainline.
> 
> > All it needs is a bootloader able to fulfill it's side of the contract
> > (build a thumb2 bootloader..) and jump while in Thumb mode, which I am
> > 100% certain exists. It'd be a 20 line patch maximum to make U-Boot do
> > this (it already can build as Thumb2 I think.. if not, there are
> > patches around) through an environment variable and distros that knew
> > they built in Thumb mode could simply modify the variable in boot.scr
> > or so, and the jump would end up being done in Thumb. That way you
> > have to kick it, but no changes are required in the kernel format
> > (just in the packaging of the kernel and configuration of the
> > bootloader). Guessing would be a bad idea...
> 
> The fewer contracts we have with bootloaders the better we are.  
> Unfortunately those contracts are increasing in scope.  Let's avoid the 
> really trivial cases if we can help it.
> 
> By mandating ARM mode, there is absolutely no guessing and no place for 
> misinterpretation, buggy implementation, or other silliness of which 
> bootloaders are full of.
> 
> The only good case for using Thumb mode in kernel entry is with those 
> CPUs with no support for ARM mode.
> 
> 
> Nicolas


From nico at fluxnic.net  Tue Aug  7 13:14:36 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 07 Aug 2012 13:14:36 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120807115647.GA12828@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208071259270.5231@xanadu.home>

On Tue, 7 Aug 2012, Will Deacon wrote:

> Hello,
> 
> ARM recently moved to asm-generic/mutex-xchg.h for its mutex implementation
> after our previous implementation was found to be missing some crucial
> memory barriers. However, I'm seeing some problems running hackbench on
> SMP platforms due to the way in which the MUTEX_SPIN_ON_OWNER code operates.
> 
> The symptoms are that a bunch of hackbench tasks are left waiting on an
> unlocked mutex and therefore never get woken up to claim it. I think this
> boils down to the following sequence:
> 
> 
>         Task A        Task B        Task C        Lock value
> 0                                                     1
> 1       lock()                                        0
> 2                     lock()                          0
> 3                     spin(A)                         0
> 4       unlock()                                      1
> 5                                   lock()            0
> 6                     cmpxchg(1,0)                    0
> 7                     contended()                    -1
> 8       lock()                                        0
> 9       spin(C)                                       0
> 10                                  unlock()          1
> 11      cmpxchg(1,0)                                  0
> 12      unlock()                                      1
> 
> 
> At this point, the lock is unlocked, but Task B is in an uninterruptible
> sleep with nobody to wake it up.

I fail to see how the lock value would go from -1 to 0 on line 8.  How 
does that happen?
> The following patch fixes the problem by ensuring we put the lock into
> the contended state if we acquire it from the spin loop on the slowpath
> but I'd like to be sure that this won't cause problems with other mutex
> implementations:
> 
> 
> diff --git a/kernel/mutex.c b/kernel/mutex.c
> index a307cc9..27b7887 100644
> --- a/kernel/mutex.c
> +++ b/kernel/mutex.c
> @@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
>                 if (owner && !mutex_spin_on_owner(lock, owner))
>                         break;
>  
> -               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> +               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
>                         lock_acquired(&lock->dep_map, ip);
>                         mutex_set_owner(lock);
>                         preempt_enable();

This would force invokation of the slow path on unlock even if in most 
cases the lock is unlikely to be contended.  The really slow path does 
check if the waiting list is empty and sets the count to 0 before 
exiting to avoid that.  I don't see how this could be done safely in the 
spin_on_owner loop code as the lock->wait_lock isn't held (which appears 
to be the point of this code in the first place).

Yet, if the lock is heavily contended with a waiting task, the count 
should never get back to 1 and the cmpxchg on line 11 would not set the 
count to 0.  Hence my interrogation about line 8 above.


Nicolas


From imp at bsdimp.com  Tue Aug  7 13:23:40 2012
From: imp at bsdimp.com (Warner Losh)
Date: Tue, 7 Aug 2012 11:23:40 -0600
Subject: [PATCH] driver: misc: bmp085: remove "of_match_table" property.
In-Reply-To: <20120807105225.GT16861@opensource.wolfsonmicro.com>
References: <1344245324-16704-1-git-send-email-sourav.poddar@ti.com>
 <20120806093033.GH17551@arwen.pp.htv.fi>
 <20120806154214.GC29272@sirena.org.uk>
 <20120807054342.GF8468@arwen.pp.htv.fi>
 <20120807105225.GT16861@opensource.wolfsonmicro.com>
Message-ID: <4CEA7FE1-B4B7-4702-BD94-C04154014763@bsdimp.com>


On Aug 7, 2012, at 4:52 AM, Mark Brown wrote:

> On Tue, Aug 07, 2012 at 08:43:44AM +0300, Felipe Balbi wrote:
>> On Mon, Aug 06, 2012 at 04:42:14PM +0100, Mark Brown wrote:
> 
>>> It's good practice to have an explict compatible string even if the
>>> default happens to work in order to avoid any name clashes.
> 
>> of_i2c.c makes no use whatsoever of the compatible string. See that it
>> will build an i2c_boardinfo and register a new device. That compatible
> 
> If that's all that's done it seems like a bug frankly, certainly based
> on previous discussions it ought to be.  There are collisions out there,
> they've just happened to not bite us yet

Also keep in mind that the device tree is supposed to be a description of the hardware, and different implementations of the device tree may use the compatible string.

Warner



From wade_farnsworth at mentor.com  Tue Aug  7 13:25:17 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Tue, 7 Aug 2012 10:25:17 -0700
Subject: Status of patch 7375/1
Message-ID: <50214F7D.6040001@mentor.com>

Hello Russell,

I'm inquiring regarding the status of patch 7375/1 in the patch tracker:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7375/1

The other two patches in the series were approved and are now in Linus's 
tree.  However this one never received approval, nor any comments 
indicating that it was rejected.  What is the status of this patch?  Is 
there anything I can do to help move it forward?

Thanks,

Wade Farnsworth


From will.deacon at arm.com  Tue Aug  7 13:33:44 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 Aug 2012 18:33:44 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208071259270.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208071259270.5231@xanadu.home>
Message-ID: <20120807173344.GD16877@mudshark.cambridge.arm.com>

On Tue, Aug 07, 2012 at 06:14:36PM +0100, Nicolas Pitre wrote:
> On Tue, 7 Aug 2012, Will Deacon wrote:
> > The symptoms are that a bunch of hackbench tasks are left waiting on an
> > unlocked mutex and therefore never get woken up to claim it. I think this
> > boils down to the following sequence:
> > 
> > 
> >         Task A        Task B        Task C        Lock value
> > 0                                                     1
> > 1       lock()                                        0
> > 2                     lock()                          0
> > 3                     spin(A)                         0
> > 4       unlock()                                      1
> > 5                                   lock()            0
> > 6                     cmpxchg(1,0)                    0
> > 7                     contended()                    -1
> > 8       lock()                                        0
> > 9       spin(C)                                       0
> > 10                                  unlock()          1
> > 11      cmpxchg(1,0)                                  0
> > 12      unlock()                                      1
> > 
> > 
> > At this point, the lock is unlocked, but Task B is in an uninterruptible
> > sleep with nobody to wake it up.
> 
> I fail to see how the lock value would go from -1 to 0 on line 8.  How 
> does that happen?

What I think is happening is that B writes the -1 in __mutex_lock_common
and, after seeing a NULL owner (C may not have set that yet), drops through
to the:

	if (atomic_xchg(&lock->count, -1) == 1)
		goto done;

bit. At the same time, A does a mutex_lock, which goes down the fastpath:

	if (unlikely(atomic_xchg(count, 0) != 1))
		fail_fn(count);

setting the count to 0. It then trundles off down the slowpath and spins on
the new owner (C).

Maybe my diagram is confusing... the lock value is supposed to be the value
*after* the relevant operations on that same line have completed.

> > diff --git a/kernel/mutex.c b/kernel/mutex.c
> > index a307cc9..27b7887 100644
> > --- a/kernel/mutex.c
> > +++ b/kernel/mutex.c
> > @@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
> >                 if (owner && !mutex_spin_on_owner(lock, owner))
> >                         break;
> >  
> > -               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> > +               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
> >                         lock_acquired(&lock->dep_map, ip);
> >                         mutex_set_owner(lock);
> >                         preempt_enable();
> 
> This would force invokation of the slow path on unlock even if in most 
> cases the lock is unlikely to be contended.  The really slow path does 
> check if the waiting list is empty and sets the count to 0 before 
> exiting to avoid that.  I don't see how this could be done safely in the 
> spin_on_owner loop code as the lock->wait_lock isn't held (which appears 
> to be the point of this code in the first place).

Indeed, it will trigger the slowpath on the next unlock but only in the case
that the lock was contended. You're right that there might not be any
waiters though, and we'd need to take the spinlock to check that.

> Yet, if the lock is heavily contended with a waiting task, the count 
> should never get back to 1 and the cmpxchg on line 11 would not set the 
> count to 0.  Hence my interrogation about line 8 above.

Hmm. __mutex_fastpath_unlock always sets the count to 1:

	if (unlikely(atomic_xchg(count, 1) != 0))
		failt_fn(count);

so there's always a window for a spinning waiter (as opposed to one blocked
in the queue) to succeed in the cmpxchg.

Unless I'm barking up the wrong tree!

Will


From nsekhar at ti.com  Tue Aug  7 13:36:05 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue, 7 Aug 2012 23:06:05 +0530
Subject: [PATCH v6] ARM: mtd: nand: davinci: add OF support for davinci
 nand controller
In-Reply-To: <1343632944-25971-1-git-send-email-hs@denx.de>
References: <1343632944-25971-1-git-send-email-hs@denx.de>
Message-ID: <50215205.5010909@ti.com>

On 7/30/2012 12:52 PM, Heiko Schocher wrote:
> add OF support for the davinci nand controller.
> 
> Signed-off-by: Heiko Schocher <hs at denx.de>

Acked-by: Sekhar Nori <nsekhar at ti.com>

Thanks,
Sekhar


From will.deacon at arm.com  Tue Aug  7 13:38:10 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 Aug 2012 18:38:10 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120807173344.GD16877@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208071259270.5231@xanadu.home>
 <20120807173344.GD16877@mudshark.cambridge.arm.com>
Message-ID: <20120807173810.GE16877@mudshark.cambridge.arm.com>

On Tue, Aug 07, 2012 at 06:33:44PM +0100, Will Deacon wrote:
> What I think is happening is that B writes the -1 in __mutex_lock_common
> and, after seeing a NULL owner (C may not have set that yet), drops through
> to the:
> 
> 	if (atomic_xchg(&lock->count, -1) == 1)
> 		goto done;

Sorry, should have proofread that. I meant to say:

 What I think is happening is that B writes the -1 in __mutex_lock_common
 after seeing a NULL owner (C may not have set that yet) and dropping through
 to the:
 
 	if (atomic_xchg(&lock->count, -1) == 1)
 		goto done;
 

Will


From koen at dominion.thruhere.net  Tue Aug  7 13:42:23 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Tue, 7 Aug 2012 19:42:23 +0200
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
 <50213214.7050505@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
Message-ID: <87D16BF2-6A3B-4B7D-AB61-EB606FA88A68@dominion.thruhere.net>


Op 7 aug. 2012, om 17:53 heeft "Hiremath, Vaibhav" <hvaibhav at ti.com> het volgende geschreven:

> On Tue, Aug 07, 2012 at 20:49:48, Rob Herring wrote:
>> On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
>>> If the module requires only one clocksource to function, then
>>> driver can very well call clk_get() api with "con_id = NULL",
>>> 
>>>       clk = clk_get(dev, NULL);
>>> 
>>> And platform code should respect this and return valid clk handle.
>>> That means, now the clk_get() api would rely on dev_id, and platform
>>> code should either have clk node with matching dev_id (with con_id=NULL)
>>> or return dummy clk node.
>>> 
>>> With DT support, we can fix the dev_id for particular module
>>> using "struct of_dev_auxdata" to satisfy above clk framework requirement.
>>> 
>>> In case of AM33XX, we required this for the DCAN module, so this
>>> patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
>>> 
>>> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
>>> Cc: Tony Lindgren <tony at atomide.com>
>>> Cc: Paul Walmsley <paul at pwsan.com>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> ---
>>> This patch is boot tested on BeagleBone platform, and checked for
>>> clk_get() return value in d_can module driver.
>>> 
>>> arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
>>> 1 files changed, 17 insertions(+), 1 deletions(-)
>>> 
>>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
>>> index 6f93a20..c9b7903 100644
>>> --- a/arch/arm/mach-omap2/board-generic.c
>>> +++ b/arch/arm/mach-omap2/board-generic.c
>>> @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>>> 	{ }
>>> };
>>> 
>>> +/*
>>> + * Lookup table for attaching a specific name and platform_data pointer to
>>> + * devices as they get created by of_platform_populate(). Ideally this table
>>> + * would not exist, but the current clock implementation depends on some devices
>>> + * having a specific name OR to satisfy NULL con_id requirement from driver.
>>> + */
>>> +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
>>> +	{ },
>>> +};
>> 
>> Adding an additional clkdev lookup accomplishes the same thing and is a
>> cleaner solution.
>> 
> 
> That is also required and I have submitted patch for the same -
> 
> http://www.spinics.net/lists/arm-kernel/msg187998.html
> 
> 
> With DT support, I am getting dev_id as -
> 
> - Without "reg" property: d_can.16 and d_can.17,
>   (I believe it changes dynamically here)
> 
> - With "reg" property: 481cc000.d_can and 481d0000.d_can
> 
> Which is not so intuitive, I would like to see them as per Spec/TRM, so 
> doesn't this patch make sense?
> 
> Similar thing has already been done for other platforms too.

Davinci-mdio has a similar problem

regards,

Koen

From hartleys at visionengravers.com  Tue Aug  7 13:47:04 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 7 Aug 2012 12:47:04 -0500
Subject: [PATCH] ARM: ep93xx: clockevent support
In-Reply-To: <5021122C.3000503@gmail.com>
References: <1344338474.18237.6.camel@localhost> <5021122C.3000503@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F00206AAE96C18@AUSP01VMBX24.collaborationhost.net>

On Tuesday, August 07, 2012 6:04 AM, Ryan Mallon wrote:
> On 07/08/12 21:21, Yan Burman wrote:
>
>> ARM: ep93xx: clockevent support
>> I have ported to 3.6-rc1 and slightly modified a previous patch for clockevent support for the ep93xx.
>> The porting mainly consists of sched_clock support.
>> Tested on 9302 based board.
>> From: Ahmed Ammar <aammar <at> edge-techno.com>
>> Signed-off-by: Yan Burman <burman.yan at gmail.com>

Hello Yan,

> Hi Yan, some comments below.
>
> ~Ryan

I have a couple minor comments as well...

<snip>

>> @@ -114,63 +117,129 @@ void __init ep93xx_map_io(void)
>>  #define EP93XX_TIMER4_CLOCK		983040
>>  
>>  #define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
>> -#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
>> -
>> -static unsigned int last_jiffy_time;
>>  
>>  static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
>>  {
>> -	/* Writing any value clears the timer interrupt */

Please leave this comment for the write to EP93XX_TIMER1_CLEAR
below.

>> -	__raw_writel(1, EP93XX_TIMER1_CLEAR);
>> +	struct clock_event_device *evt = dev_id;
>>  
>> -	/* Recover lost jiffies */
>> -	while ((signed long)
>> -		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
>> -						>= TIMER4_TICKS_PER_JIFFY) {
>> -		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
>> -		timer_tick();
>> -	}
>> +	__raw_writel(1, EP93XX_TIMER1_CLEAR);
>> +	evt->event_handler(evt);
>>  
>>  	return IRQ_HANDLED;
>>  }
>>  
>> +static int ep93xx_set_next_event(unsigned long evt,
>> +				struct clock_event_device *unused)
>> +{
>> +	u32 tmode = __raw_readl(EP93XX_TIMER1_CONTROL);
>> +
>> +	/* stop timer */
>> +	__raw_writel(tmode & ~EP93XX_TIMER123_CONTROL_ENABLE,
>> +			EP93XX_TIMER1_CONTROL);
>> +	/* program timer */
>> +	__raw_writel(evt, EP93XX_TIMER1_LOAD);
>> +	/* start timer */
>> +	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
>> +			EP93XX_TIMER1_CONTROL);
>> +
>> +	return 0;
>> +}
>> +
>> +static void ep93xx_set_mode(enum clock_event_mode mode,
>> +			    struct clock_event_device *evt)
>> +{
>> +	u32 tmode = EP93XX_TIMER123_CONTROL_CLKSEL;
>> +	/* Disable timer */
>
>
> Nitpick - blank line between variable declarations and code.
>
>> +	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
>> +
>> +	switch (mode) {
>> +	case CLOCK_EVT_MODE_PERIODIC:
>> +		/* Set timer period  */
>> +		__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);

As Ryan mentions below.  There are defines already in this file
for some of the magic values.

The ((508469 / HZ) - 1) is TIMER1_RELOAD.

>> +		tmode |= EP93XX_TIMER123_CONTROL_MODE;
>> +


Is the fall-through here intentional? If so, please put a comment
to indicate that it is.

>> +	case CLOCK_EVT_MODE_ONESHOT:
>> +		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
>> +		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
>> +		break;
>> +
>> +	case CLOCK_EVT_MODE_SHUTDOWN:
>> +	case CLOCK_EVT_MODE_UNUSED:
>> +	case CLOCK_EVT_MODE_RESUME:
>> +		return;
>
>
> These cases can be removed.
>
>> +	}
>> +}
>> +
>> +static struct clock_event_device clockevent_ep93xx = {

Nitpick, rename this to ep93xx_clockevent please.

>> +	.name		= "ep93xx-timer1",
>> +	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>> +	.shift		= 32,
>> +	.set_mode	= ep93xx_set_mode,
>> +	.set_next_event	= ep93xx_set_next_event,
>> +};
>> +
>>  static struct irqaction ep93xx_timer_irq = {
>>  	.name		= "ep93xx timer",
>>  	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
>>  	.handler	= ep93xx_timer_interrupt,
>> +	.dev_id		= &clockevent_ep93xx,
>>  };
>>  
>> -static void __init ep93xx_timer_init(void)
>> +static void __init ep93xx_clockevent_init(void)
>>  {

Assuming the rename above, add:

	struct clock_event_device *evt = &ep93xx_clockevent;

Then you can use 'evt->' instead of the longer 'ep93xx_clockevent.'
in the rest of this function. It makes the code a bit cleaner.

>> -	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
>> -		    EP93XX_TIMER123_CONTROL_CLKSEL;
>> +	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
>> +	clockevent_ep93xx.mult = div_sc(508469, NSEC_PER_SEC,
>> +					clockevent_ep93xx.shift);
>
>
> core.c has:
>
>  #define EP93XX_TIMER123_CLOCK               508469
>
> Maybe we should move that to soc.h so you can use it here.

No need to move the defines to soc.h. They are only used in this file.

>> +	clockevent_ep93xx.max_delta_ns =
>> +		clockevent_delta2ns(0xfffffffe, &clockevent_ep93xx);
>> +	clockevent_ep93xx.min_delta_ns =
>> +		clockevent_delta2ns(0xf, &clockevent_ep93xx);
>> +	clockevent_ep93xx.cpumask = cpumask_of(0);
>> +	clockevents_register_device(&clockevent_ep93xx);
>> +}
>>  
>> -	/* Enable periodic HZ timer.  */
>> -	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
>> -	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
>> -	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
>> -			EP93XX_TIMER1_CONTROL);
>> +/*
>> + * timer4 is a 40 Bit timer, separated in a 32bit and a 8 bit
>> + * register, EP93XX_TIMER4_VALUE_LOW stores 32 bit word. The
>> + * controlregister is in EP93XX_TIMER4_VALUE_HIGH

I don't think this comment is needed.

> Missing space between control and register.
>
>> + */
>> +static cycle_t ep93xx_get_cycles(struct clocksource *unused)
>> +{
>> +	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
>> +}
>>  
>> -	/* Enable lost jiffy timer.  */
>> -	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
>> -			EP93XX_TIMER4_VALUE_HIGH);
>> +static struct clocksource clocksource_ep93xx = {

Nitpick, rename this to ep93xx_clocksource.

>> +	.name		= "ep93xx_timer4",

Nitpick, use "ep93xx-timer4" for the name, the "-" is used
consistently in this file for all the names.

>> +	.rating		= 200,
>> +	.read		= ep93xx_get_cycles,
>> +	.mask		= 0xFFFFFFFF,
>>
>
> Lower case for hex constant.
>
>> +	.shift		= 20,
>> +	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
>> +};
>>  
>> -	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
>> +static void __init ep93xx_clocksource_init(void)

Again, assuming the rename above, add:

	struct clocksource *src = &ep93xx_clocksource;

Then use the pointer instead of the actual variable.

>> +{
>> +	/* Reset time-stamp counter */
>> +	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);

Again, the 0x100 magic value is defined as EP93XX_TIMER4_VALUE_HIGH_ENABLE.

>> +	clocksource_ep93xx.mult =
>> +		clocksource_hz2mult(983040, clocksource_ep93xx.shift);
>
>
> core.c has define EP93XX_TIMER4_CLOCK 983040, probably should move
> that to soc.h also.
>
>> +	clocksource_register(&clocksource_ep93xx);
>>  }
>>  
>> -static unsigned long ep93xx_gettimeoffset(void)
>> +static u32 notrace ep93xx_sched_clock(void)
>>  {
>> -	int offset;
>> -
>> -	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
>> +	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
>> +}
>>  
>> -	/* Calculate (1000000 / 983040) * offset.  */
>> -	return offset + (53 * offset / 3072);
>> +static void __init ep93xx_timer_init(void)
>> +{
>> +	ep93xx_clocksource_init();
>> +	ep93xx_clockevent_init();
>> +	setup_sched_clock(ep93xx_sched_clock, 32, CLOCK_TICK_RATE);
>>  }
>>  
>>  struct sys_timer ep93xx_timer = {
>>  	.init		= ep93xx_timer_init,
>> -	.offset		= ep93xx_gettimeoffset,
>>  };
>>  
>>  
>> 
>> 

Other than those comments, looks good. I'll try to test this later.

Thanks,
Hartley



From will.deacon at arm.com  Tue Aug  7 13:59:23 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 7 Aug 2012 18:59:23 +0100
Subject: Status of patch 7375/1
In-Reply-To: <50214F7D.6040001@mentor.com>
References: <50214F7D.6040001@mentor.com>
Message-ID: <20120807175923.GF16877@mudshark.cambridge.arm.com>

Wade,

On Tue, Aug 07, 2012 at 06:25:17PM +0100, Wade Farnsworth wrote:
> I'm inquiring regarding the status of patch 7375/1 in the patch tracker:
> 
> http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7375/1
> 
> The other two patches in the series were approved and are now in Linus's 
> tree.  However this one never received approval, nor any comments 
> indicating that it was rejected.  What is the status of this patch?  Is 
> there anything I can do to help move it forward?

There have been a bunch of fixes to the audit, syscall tracing and signal
handling code so you'll probably need to rebase your patch on top of
3.6-rc1. I think I CC'd you at the time (at least, that was my intention!).

Would you be able to do that and send it to the list again please?

Thanks,

Will


From linux at arm.linux.org.uk  Tue Aug  7 14:13:59 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 7 Aug 2012 19:13:59 +0100
Subject: Status of patch 7375/1
In-Reply-To: <20120807175923.GF16877@mudshark.cambridge.arm.com>
References: <50214F7D.6040001@mentor.com>
 <20120807175923.GF16877@mudshark.cambridge.arm.com>
Message-ID: <20120807181359.GK18957@n2100.arm.linux.org.uk>

On Tue, Aug 07, 2012 at 06:59:23PM +0100, Will Deacon wrote:
> Wade,
> 
> On Tue, Aug 07, 2012 at 06:25:17PM +0100, Wade Farnsworth wrote:
> > I'm inquiring regarding the status of patch 7375/1 in the patch tracker:
> > 
> > http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7375/1
> > 
> > The other two patches in the series were approved and are now in Linus's 
> > tree.  However this one never received approval, nor any comments 
> > indicating that it was rejected.  What is the status of this patch?  Is 
> > there anything I can do to help move it forward?
> 
> There have been a bunch of fixes to the audit, syscall tracing and signal
> handling code so you'll probably need to rebase your patch on top of
> 3.6-rc1. I think I CC'd you at the time (at least, that was my intention!).

Yes, it became impossible to apply when all the syscall/audit fixes went
in, which was more important than adding a new feature.

I think the audit/syscall fixes have settled now, so as Will says...

> Would you be able to do that and send it to the list again please?

Thanks.


From konrad.wilk at oracle.com  Tue Aug  7 14:10:17 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:10:17 -0400
Subject: [PATCH v2 01/23] arm: initial Xen support
In-Reply-To: <1344263246-28036-1-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-1-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181017.GF15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:04PM +0100, Stefano Stabellini wrote:
> - Basic hypervisor.h and interface.h definitions.
> - Skeleton enlighten.c, set xen_start_info to an empty struct.
> - Make xen_initial_domain dependent on the SIF_PRIVILIGED_BIT.
> 
> The new code only compiles when CONFIG_XEN is set, that is going to be
> added to arch/arm/Kconfig in patch #11 "xen/arm: introduce CONFIG_XEN on
> ARM".

You can add my Ack, but do one change pls:

> +/* XXX: Move pvclock definitions some place arch independent */

Just use 'TODO'

> +struct pvclock_vcpu_time_info {
> +	u32   version;
> +	u32   pad0;
> +	u64   tsc_timestamp;
> +	u64   system_time;
> +	u32   tsc_to_system_mul;
> +	s8    tsc_shift;
> +	u8    flags;
> +	u8    pad[2];
> +} __attribute__((__packed__)); /* 32 bytes */
> +
> +struct pvclock_wall_clock {
> +	u32   version;
> +	u32   sec;
> +	u32   nsec;
> +} __attribute__((__packed__));

Mention the size and why it is OK to have it be a weird
size while the one above is nicely padded.

> +#endif
> +
> +#endif /* _ASM_ARM_XEN_INTERFACE_H */
> diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> new file mode 100644
> index 0000000..0bad594
> --- /dev/null
> +++ b/arch/arm/xen/Makefile
> @@ -0,0 +1 @@
> +obj-y		:= enlighten.o
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> new file mode 100644
> index 0000000..d27c2a6
> --- /dev/null
> +++ b/arch/arm/xen/enlighten.c
> @@ -0,0 +1,35 @@
> +#include <xen/xen.h>
> +#include <xen/interface/xen.h>
> +#include <xen/interface/memory.h>
> +#include <xen/platform_pci.h>
> +#include <asm/xen/hypervisor.h>
> +#include <asm/xen/hypercall.h>
> +#include <linux/module.h>
> +
> +struct start_info _xen_start_info;
> +struct start_info *xen_start_info = &_xen_start_info;
> +EXPORT_SYMBOL_GPL(xen_start_info);
> +
> +enum xen_domain_type xen_domain_type = XEN_NATIVE;
> +EXPORT_SYMBOL_GPL(xen_domain_type);
> +
> +struct shared_info xen_dummy_shared_info;
> +struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
> +
> +DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
> +
> +/* XXX: to be removed */

s/XXX/TODO/ here, and mention pls why it needs to be removed.

> +__read_mostly int xen_have_vector_callback;
> +EXPORT_SYMBOL_GPL(xen_have_vector_callback);
> +
> +int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
> +EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);


From thierry.reding at avionic-design.de  Tue Aug  7 14:20:24 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 7 Aug 2012 20:20:24 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <50201E1D.5060200@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
Message-ID: <20120807182024.GA11328@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> > This patch series adds support for device tree based probing of the PCIe
> > controller found on Tegra SoCs.
> 
> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed that
> PCIe doesn't work on TrimSlice when booting use device tree. I think I
> found the cause, and I can't see why the same problem doesn't affect
> this series. Perhaps you can enlighten me?
> 
> When booting TrimSlice (or Harmony) using board files, Tegra's PCIe is
> initialized using a subsys_initcall to tegra_pcie_init() directly (or
> for Harmony to harmony_pcie_init() which then calls tegra_pcie_init()).
> 
> The final thing tegra_pcie_init() does is call pci_common_init(). This
> calls pcibios_init_hw() which calls hw->scan() which calls
> pci_scan_root_bus() which adds a device object for each device on the
> PCIe bus. However, since this happens very early in the boot sequence, I
> believe the enumerated PCIe devices don't immediately get probed.
> Instead, control gets returned to pci_common_init() which I believe then
> calls pci_bus_assign_resources() which actually sets up the resources
> for those devices. Later, the PCIe devices actually get probed, and
> everything works.
> 
> However, when booting using device tree, with the code currently in
> v3.6-rc1, tegra_pcie_init() is called late in the boot sequence, and so
> in the sequence described above, as soon as pci_scan_root_bus() adds a
> device, it gets probed, before the device object's resources have been
> set up, which results in the following failure:
> 
> PCI: Device 0000:01:00.0 not available because of resource collisions
> 
> ... because of the following code in pcibios_enable_device():
> 
> > 	for (idx = 0; idx < 6; idx++) {
> > 		/* Only set up the requested stuff */
> > 		if (!(mask & (1 << idx)))
> > 			continue;
> > 
> > 		r = dev->resource + idx;
> > 		if (!r->start && r->end) {
> > 			printk(KERN_ERR "PCI: Device %s not available because"
> > 			       " of resource collisions\n", pci_name(dev));
> 
> Doesn't this same problem exist when instantiating the PCIe device
> itself from device tree as in your patch series? If not, can you explain
> why?

I think I've seen this before as well but hadn't had the time to
investigate further. The devices that failed to initialize were serial
ports I think. Perhaps the ordering here is the key. All the drivers
that I use for the PCI devices are loaded as modules, so they'll probe
the devices much later anyway. The serial driver is an exception here as
it is builtin.

> Now, the obvious solution in v3.6 would be to simply have
> tegra_pcie_init() be called at the same early stage in the boot process
> when booting using device tree as it is when booting using board files.
> This works for TrimSlice.
> 
> However, on Harmony, it doesn't work, because PCIe on Harmony depends on
> regulators, and the regulators are accessed using an I2C bus that is
> instantiated from DT, and the instantiation of the I2C bus happens
> fairly late in the boot process so can't be found early during the boot
> sequence. See harmony_regulator_init() for the failing code.
> 
> Does anyone have any good ideas (small, self-contained patches) for
> solving this in v3.6 in such a way that PCIe works on both TrimSlice and
> Harmony?

To me this looks like a problem in the probing code. Drivers' .probe()
shouldn't be called on devices that haven't had their resources assigned
yet. Perhaps nobody has ever seen this before because the ordering
always ensured that the PCI controller driver was loaded first.

Thierry
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From khilman at ti.com  Tue Aug  7 14:21:40 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 11:21:40 -0700
Subject: [PATCH] ARM: OMAP2+: Fix dmtimer set source clock failure
In-Reply-To: <1342210323-2129-1-git-send-email-jon-hunter@ti.com> (Jon
 Hunter's message of "Fri, 13 Jul 2012 15:12:03 -0500")
References: <1342210323-2129-1-git-send-email-jon-hunter@ti.com>
Message-ID: <87boim36mj.fsf@ti.com>

Jon Hunter <jon-hunter at ti.com> writes:

> Calling the dmtimer function omap_dm_timer_set_source() fails if following a
> call to pm_runtime_put() to disable the timer. For example the following
> sequence would fail to set the parent clock ...
>
> 	omap_dm_timer_stop(gptimer);
> 	omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
>
> The following error message would be seen ...
>
> omap_dm_timer_set_source: failed to set timer_32k_ck as parent
>
> The problem is that, by design, pm_runtime_put() simply decrements the usage
> count and returns before the timer has actually been disabled. Therefore,
> setting the parent clock failed because the timer was still active when the
> trying to set the parent clock. Setting a parent clock will fail if the clock
> you are setting the parent of has a non-zero usage count. To ensure that this
> does not fail use pm_runtime_put_sync() when disabling the timer.
>
> Note that this will not be seen on OMAP1 devices, because these devices do
> not use the clock framework for dmtimers.
>
> Signed-off-by: Jon Hunter <jon-hunter at ti.com>

Acked-by: Kevin Hilman <khilman at ti.com>

> ---
>  arch/arm/plat-omap/dmtimer.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
> index 626ad8c..7b6689a 100644
> --- a/arch/arm/plat-omap/dmtimer.c
> +++ b/arch/arm/plat-omap/dmtimer.c
> @@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
>  
>  void omap_dm_timer_disable(struct omap_dm_timer *timer)
>  {
> -	pm_runtime_put(&timer->pdev->dev);
> +	pm_runtime_put_sync(&timer->pdev->dev);
>  }
>  EXPORT_SYMBOL_GPL(omap_dm_timer_disable);


From konrad.wilk at oracle.com  Tue Aug  7 14:13:22 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:13:22 -0400
Subject: [PATCH v2 03/23] xen/arm: page.h definitions
In-Reply-To: <1344263246-28036-3-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-3-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181322.GG15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:06PM +0100, Stefano Stabellini wrote:
> ARM Xen guests always use paging in hardware, like PV on HVM guests in
> the X86 world.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Ack.. with one nitpick

> +/* XXX: this shouldn't be here */

.. but its here b/c the frontend drivers are using it (its rolled in
headers)- even though we won't hit the code path. So for right now
just punt with this.

> +static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
> +{
> +	BUG();
> +	return NULL;
> +}
> +
> +static inline int m2p_add_override(unsigned long mfn, struct page *page,
> +		struct gnttab_map_grant_ref *kmap_op)
> +{
> +	return 0;
> +}
> +
> +static inline int m2p_remove_override(struct page *page, bool clear_pte)
> +{
> +	return 0;
> +}
> +
> +static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> +{
> +	BUG();
> +	return false;
> +}
> +#endif /* _ASM_ARM_XEN_PAGE_H */
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:13:29 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:13:29 -0400
Subject: [PATCH v2 04/23] xen/arm: sync_bitops
In-Reply-To: <1344263246-28036-4-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-4-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181329.GH15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:07PM +0100, Stefano Stabellini wrote:
> sync_bitops functions are equivalent to the SMP implementation of the
> original functions, independently from CONFIG_SMP being defined.
> 
> We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
> under Xen you might be communicating with a completely external entity
> who might be on another CPU (e.g. two uniprocessor guests communicating
> via event channels and grant tables). So we need a variant of the bit
> ops which are SMP safe even on a UP kernel.

Ack from me.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/sync_bitops.h |   27 +++++++++++++++++++++++++++
>  1 files changed, 27 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/sync_bitops.h
> 
> diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
> new file mode 100644
> index 0000000..63479ee
> --- /dev/null
> +++ b/arch/arm/include/asm/sync_bitops.h
> @@ -0,0 +1,27 @@
> +#ifndef __ASM_SYNC_BITOPS_H__
> +#define __ASM_SYNC_BITOPS_H__
> +
> +#include <asm/bitops.h>
> +#include <asm/system.h>
> +
> +/* sync_bitops functions are equivalent to the SMP implementation of the
> + * original functions, independently from CONFIG_SMP being defined.
> + *
> + * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
> + * under Xen you might be communicating with a completely external entity
> + * who might be on another CPU (e.g. two uniprocessor guests communicating
> + * via event channels and grant tables). So we need a variant of the bit
> + * ops which are SMP safe even on a UP kernel.
> + */
> +
> +#define sync_set_bit(nr, p)		_set_bit(nr, p)
> +#define sync_clear_bit(nr, p)		_clear_bit(nr, p)
> +#define sync_change_bit(nr, p)		_change_bit(nr, p)
> +#define sync_test_and_set_bit(nr, p)	_test_and_set_bit(nr, p)
> +#define sync_test_and_clear_bit(nr, p)	_test_and_clear_bit(nr, p)
> +#define sync_test_and_change_bit(nr, p)	_test_and_change_bit(nr, p)
> +#define sync_test_bit(nr, addr)		test_bit(nr, addr)
> +#define sync_cmpxchg			cmpxchg
> +
> +
> +#endif
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:13:37 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:13:37 -0400
Subject: [PATCH v2 05/23] xen/arm: empty implementation of grant_table
 arch specific functions
In-Reply-To: <1344263246-28036-5-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-5-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181337.GI15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:08PM +0100, Stefano Stabellini wrote:
> Changes in v2:
> 
> - return -ENOSYS rather than -1.

Ack.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/Makefile      |    2 +-
>  arch/arm/xen/grant-table.c |   53 ++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 54 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/xen/grant-table.c
> 
> diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> index b9d6acc..4384103 100644
> --- a/arch/arm/xen/Makefile
> +++ b/arch/arm/xen/Makefile
> @@ -1 +1 @@
> -obj-y		:= enlighten.o hypercall.o
> +obj-y		:= enlighten.o hypercall.o grant-table.o
> diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
> new file mode 100644
> index 0000000..dbd1330
> --- /dev/null
> +++ b/arch/arm/xen/grant-table.c
> @@ -0,0 +1,53 @@
> +/******************************************************************************
> + * grant_table.c
> + * ARM specific part
> + *
> + * Granting foreign access to our memory reservation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation; or, when distributed
> + * separately from the Linux kernel or incorporated into other
> + * software packages, subject to the following license:
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this source file (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use, copy, modify,
> + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> + * and to permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include <xen/interface/xen.h>
> +#include <xen/page.h>
> +#include <xen/grant_table.h>
> +
> +int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
> +			   unsigned long max_nr_gframes,
> +			   void **__shared)
> +{
> +	return -ENOSYS;
> +}
> +
> +void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
> +{
> +	return;
> +}
> +
> +int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
> +			   unsigned long max_nr_gframes,
> +			   grant_status_t **__shared)
> +{
> +	return -ENOSYS;
> +}
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:14:57 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:14:57 -0400
Subject: [PATCH v2 06/23] xen: missing includes
In-Reply-To: <1344263246-28036-6-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-6-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181457.GJ15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:09PM +0100, Stefano Stabellini wrote:
> Changes in v2:
> - remove pvclock hack;
> - remove include linux/types.h from xen/interface/xen.h.

I think I can take in my tree now right by itself right? Or do
you want to keep this in your patchqueue? If so, Ack from me.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/x86/include/asm/xen/interface.h       |    2 ++
>  drivers/tty/hvc/hvc_xen.c                  |    2 ++
>  drivers/xen/grant-table.c                  |    1 +
>  drivers/xen/xenbus/xenbus_probe_frontend.c |    1 +
>  include/xen/interface/xen.h                |    1 -
>  include/xen/privcmd.h                      |    1 +
>  6 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> index cbf0c9d..a93db16 100644
> --- a/arch/x86/include/asm/xen/interface.h
> +++ b/arch/x86/include/asm/xen/interface.h
> @@ -121,6 +121,8 @@ struct arch_shared_info {
>  #include "interface_64.h"
>  #endif
>  
> +#include <asm/pvclock-abi.h>
> +
>  #ifndef __ASSEMBLY__
>  /*
>   * The following is all CPU context. Note that the fpu_ctxt block is filled
> diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
> index 944eaeb..dc07f56 100644
> --- a/drivers/tty/hvc/hvc_xen.c
> +++ b/drivers/tty/hvc/hvc_xen.c
> @@ -21,6 +21,7 @@
>  #include <linux/console.h>
>  #include <linux/delay.h>
>  #include <linux/err.h>
> +#include <linux/irq.h>
>  #include <linux/init.h>
>  #include <linux/types.h>
>  #include <linux/list.h>
> @@ -35,6 +36,7 @@
>  #include <xen/page.h>
>  #include <xen/events.h>
>  #include <xen/interface/io/console.h>
> +#include <xen/interface/sched.h>
>  #include <xen/hvc-console.h>
>  #include <xen/xenbus.h>
>  
> diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
> index 0bfc1ef..1d0d95e 100644
> --- a/drivers/xen/grant-table.c
> +++ b/drivers/xen/grant-table.c
> @@ -47,6 +47,7 @@
>  #include <xen/interface/memory.h>
>  #include <xen/hvc-console.h>
>  #include <asm/xen/hypercall.h>
> +#include <asm/xen/interface.h>
>  
>  #include <asm/pgtable.h>
>  #include <asm/sync_bitops.h>
> diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
> index a31b54d..3159a37 100644
> --- a/drivers/xen/xenbus/xenbus_probe_frontend.c
> +++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
> @@ -21,6 +21,7 @@
>  #include <xen/xenbus.h>
>  #include <xen/events.h>
>  #include <xen/page.h>
> +#include <xen/xen.h>
>  
>  #include <xen/platform_pci.h>
>  
> diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> index a890804..3871e47 100644
> --- a/include/xen/interface/xen.h
> +++ b/include/xen/interface/xen.h
> @@ -10,7 +10,6 @@
>  #define __XEN_PUBLIC_XEN_H__
>  
>  #include <asm/xen/interface.h>
> -#include <asm/pvclock-abi.h>
>  
>  /*
>   * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
> diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
> index 17857fb..4d58881 100644
> --- a/include/xen/privcmd.h
> +++ b/include/xen/privcmd.h
> @@ -35,6 +35,7 @@
>  
>  #include <linux/types.h>
>  #include <linux/compiler.h>
> +#include <xen/interface/xen.h>
>  
>  typedef unsigned long xen_pfn_t;
>  
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:17:52 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:17:52 -0400
Subject: [PATCH v2 07/23] xen/arm: Xen detection and shared_info page
 mapping
In-Reply-To: <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181752.GK15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:10PM +0100, Stefano Stabellini wrote:
> Check for a "/xen" node in the device tree, if it is present set
> xen_domain_type to XEN_HVM_DOMAIN and continue initialization.
> 
> Map the real shared info page using XENMEM_add_to_physmap with
> XENMAPSPACE_shared_info.
> 
> Changes in v2:
> 
> - replace pr_info with pr_debug.

I second what David mentioned. The other thing is that you are going to
need to rebase this on top of v3.5-rc1, as Olaf's patches have changed
the shared_info_page a bit.

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 52 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index d27c2a6..102d823 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -5,6 +5,9 @@
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
>  
>  struct start_info _xen_start_info;
>  struct start_info *xen_start_info = &_xen_start_info;
> @@ -33,3 +36,52 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  	return -ENOSYS;
>  }
>  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> +
> +/*
> + * == Xen Device Tree format ==
> + * - /xen node;
> + * - compatible "arm,xen";
> + * - one interrupt for Xen event notifications;
> + * - one memory region to map the grant_table.
> + */
> +static int __init xen_guest_init(void)
> +{
> +	struct xen_add_to_physmap xatp;
> +	static struct shared_info *shared_info_page = 0;
> +	struct device_node *node;
> +
> +	node = of_find_compatible_node(NULL, NULL, "arm,xen");
> +	if (!node) {
> +		pr_debug("No Xen support\n");
> +		return 0;
> +	}
> +	xen_domain_type = XEN_HVM_DOMAIN;
> +
> +	if (!shared_info_page)
> +		shared_info_page = (struct shared_info *)
> +			get_zeroed_page(GFP_KERNEL);
> +	if (!shared_info_page) {
> +		pr_err("not enough memory\n");
> +		return -ENOMEM;
> +	}
> +	xatp.domid = DOMID_SELF;
> +	xatp.idx = 0;
> +	xatp.space = XENMAPSPACE_shared_info;
> +	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
> +	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
> +		BUG();
> +
> +	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
> +
> +	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
> +	 * page, we use it in the event channel upcall and in some pvclock
> +	 * related functions. We don't need the vcpu_info placement
> +	 * optimizations because we don't use any pv_mmu or pv_irq op on
> +	 * HVM.
> +	 * The shared info contains exactly 1 CPU (the boot CPU). The guest
> +	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
> +	 * for secondary CPUs as they are brought up. */
> +	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
> +	return 0;
> +}
> +core_initcall(xen_guest_init);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:18:21 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:18:21 -0400
Subject: [PATCH v2 08/23] xen/arm: Introduce xen_pfn_t for pfn and mfn
 types
In-Reply-To: <1344263246-28036-8-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-8-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181821.GL15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:11PM +0100, Stefano Stabellini wrote:
> All the original Xen headers have xen_pfn_t as mfn and pfn type, however
> when they have been imported in Linux, xen_pfn_t has been replaced with
> unsigned long. That might work for x86 and ia64 but it does not for arm.
> Bring back xen_pfn_t and let each architecture define xen_pfn_t as they
> see fit.

Ack.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/interface.h  |    4 ++++
>  arch/ia64/include/asm/xen/interface.h |    5 ++++-
>  arch/x86/include/asm/xen/interface.h  |    5 +++++
>  include/xen/interface/grant_table.h   |    4 ++--
>  include/xen/interface/memory.h        |    6 +++---
>  include/xen/interface/platform.h      |    4 ++--
>  include/xen/interface/xen.h           |    6 +++---
>  include/xen/privcmd.h                 |    2 --
>  8 files changed, 23 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
> index ab99270..f904dcc 100644
> --- a/arch/arm/include/asm/xen/interface.h
> +++ b/arch/arm/include/asm/xen/interface.h
> @@ -25,6 +25,9 @@
>  	} while (0)
>  
>  #ifndef __ASSEMBLY__
> +/* Explicitly size integers that represent pfns in the interface with
> + * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
> +typedef uint64_t xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> @@ -35,6 +38,7 @@ DEFINE_GUEST_HANDLE(long);
>  DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
> +DEFINE_GUEST_HANDLE(xen_pfn_t);
>  
>  /* Maximum number of virtual CPUs in multi-processor guests. */
>  #define MAX_VIRT_CPUS 1
> diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
> index 09d5f7f..686464e 100644
> --- a/arch/ia64/include/asm/xen/interface.h
> +++ b/arch/ia64/include/asm/xen/interface.h
> @@ -67,6 +67,10 @@
>  #define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
>  
>  #ifndef __ASSEMBLY__
> +/* Explicitly size integers that represent pfns in the public interface
> + * with Xen so that we could have one ABI that works for 32 and 64 bit
> + * guests. */
> +typedef unsigned long xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint, unsigned int);
> @@ -79,7 +83,6 @@ DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
>  
> -typedef unsigned long xen_pfn_t;
>  DEFINE_GUEST_HANDLE(xen_pfn_t);
>  #define PRI_xen_pfn	"lx"
>  #endif
> diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> index a93db16..555f94d 100644
> --- a/arch/x86/include/asm/xen/interface.h
> +++ b/arch/x86/include/asm/xen/interface.h
> @@ -47,6 +47,10 @@
>  #endif
>  
>  #ifndef __ASSEMBLY__
> +/* Explicitly size integers that represent pfns in the public interface
> + * with Xen so that on ARM we can have one ABI that works for 32 and 64
> + * bit guests. */
> +typedef unsigned long xen_pfn_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> @@ -57,6 +61,7 @@ DEFINE_GUEST_HANDLE(long);
>  DEFINE_GUEST_HANDLE(void);
>  DEFINE_GUEST_HANDLE(uint64_t);
>  DEFINE_GUEST_HANDLE(uint32_t);
> +DEFINE_GUEST_HANDLE(xen_pfn_t);
>  #endif
>  
>  #ifndef HYPERVISOR_VIRT_START
> diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h
> index a17d844..7da811b 100644
> --- a/include/xen/interface/grant_table.h
> +++ b/include/xen/interface/grant_table.h
> @@ -338,7 +338,7 @@ DEFINE_GUEST_HANDLE_STRUCT(gnttab_dump_table);
>  #define GNTTABOP_transfer                4
>  struct gnttab_transfer {
>      /* IN parameters. */
> -    unsigned long mfn;
> +    xen_pfn_t mfn;
>      domid_t       domid;
>      grant_ref_t   ref;
>      /* OUT parameters. */
> @@ -375,7 +375,7 @@ struct gnttab_copy {
>  	struct {
>  		union {
>  			grant_ref_t ref;
> -			unsigned long   gmfn;
> +			xen_pfn_t   gmfn;
>  		} u;
>  		domid_t  domid;
>  		uint16_t offset;
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index eac3ce1..abbbff0 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -31,7 +31,7 @@ struct xen_memory_reservation {
>       *   OUT: GMFN bases of extents that were allocated
>       *   (NB. This command also updates the mach_to_phys translation table)
>       */
> -    GUEST_HANDLE(ulong) extent_start;
> +    GUEST_HANDLE(xen_pfn_t) extent_start;
>  
>      /* Number of extents, and size/alignment of each (2^extent_order pages). */
>      unsigned long  nr_extents;
> @@ -130,7 +130,7 @@ struct xen_machphys_mfn_list {
>       * any large discontiguities in the machine address space, 2MB gaps in
>       * the machphys table will be represented by an MFN base of zero.
>       */
> -    GUEST_HANDLE(ulong) extent_start;
> +    GUEST_HANDLE(xen_pfn_t) extent_start;
>  
>      /*
>       * Number of extents written to the above array. This will be smaller
> @@ -172,7 +172,7 @@ struct xen_add_to_physmap {
>      unsigned long idx;
>  
>      /* GPFN where the source mapping page should appear. */
> -    unsigned long gpfn;
> +    xen_pfn_t gpfn;
>  };
>  DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap);
>  
> diff --git a/include/xen/interface/platform.h b/include/xen/interface/platform.h
> index 486653f..0bea470 100644
> --- a/include/xen/interface/platform.h
> +++ b/include/xen/interface/platform.h
> @@ -54,7 +54,7 @@ DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime_t);
>  #define XENPF_add_memtype         31
>  struct xenpf_add_memtype {
>  	/* IN variables. */
> -	unsigned long mfn;
> +	xen_pfn_t mfn;
>  	uint64_t nr_mfns;
>  	uint32_t type;
>  	/* OUT variables. */
> @@ -84,7 +84,7 @@ struct xenpf_read_memtype {
>  	/* IN variables. */
>  	uint32_t reg;
>  	/* OUT variables. */
> -	unsigned long mfn;
> +	xen_pfn_t mfn;
>  	uint64_t nr_mfns;
>  	uint32_t type;
>  };
> diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> index 3871e47..42834a3 100644
> --- a/include/xen/interface/xen.h
> +++ b/include/xen/interface/xen.h
> @@ -188,7 +188,7 @@ struct mmuext_op {
>  	unsigned int cmd;
>  	union {
>  		/* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR */
> -		unsigned long mfn;
> +		xen_pfn_t mfn;
>  		/* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
>  		unsigned long linear_addr;
>  	} arg1;
> @@ -428,11 +428,11 @@ struct start_info {
>  	unsigned long nr_pages;     /* Total pages allocated to this domain.  */
>  	unsigned long shared_info;  /* MACHINE address of shared info struct. */
>  	uint32_t flags;             /* SIF_xxx flags.                         */
> -	unsigned long store_mfn;    /* MACHINE page number of shared page.    */
> +	xen_pfn_t store_mfn;        /* MACHINE page number of shared page.    */
>  	uint32_t store_evtchn;      /* Event channel for store communication. */
>  	union {
>  		struct {
> -			unsigned long mfn;  /* MACHINE page number of console page.   */
> +			xen_pfn_t mfn;      /* MACHINE page number of console page.   */
>  			uint32_t  evtchn;   /* Event channel for console page.        */
>  		} domU;
>  		struct {
> diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
> index 4d58881..45c1aa1 100644
> --- a/include/xen/privcmd.h
> +++ b/include/xen/privcmd.h
> @@ -37,8 +37,6 @@
>  #include <linux/compiler.h>
>  #include <xen/interface/xen.h>
>  
> -typedef unsigned long xen_pfn_t;
> -
>  struct privcmd_hypercall {
>  	__u64 op;
>  	__u64 arg[5];
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:18:39 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:18:39 -0400
Subject: [PATCH v2 09/23] xen/arm: Introduce xen_ulong_t for unsigned long
In-Reply-To: <1344263246-28036-9-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-9-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807181839.GM15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:12PM +0100, Stefano Stabellini wrote:
> All the original Xen headers have xen_ulong_t as unsigned long type, however
> when they have been imported in Linux, xen_ulong_t has been replaced with
> unsigned long. That might work for x86 and ia64 but it does not for arm.
> Bring back xen_ulong_t and let each architecture define xen_ulong_t as they
> see fit.
> 
> Also explicitly size pointers (__DEFINE_GUEST_HANDLE) to 64 bit.

Looks ok to me.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/interface.h  |    8 ++++++--
>  arch/ia64/include/asm/xen/interface.h |    1 +
>  arch/x86/include/asm/xen/interface.h  |    1 +
>  include/xen/interface/memory.h        |   12 ++++++------
>  include/xen/interface/physdev.h       |    4 ++--
>  include/xen/interface/version.h       |    2 +-
>  include/xen/interface/xen.h           |    6 +++---
>  7 files changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
> index f904dcc..1d3030c 100644
> --- a/arch/arm/include/asm/xen/interface.h
> +++ b/arch/arm/include/asm/xen/interface.h
> @@ -9,8 +9,11 @@
>  
>  #include <linux/types.h>
>  
> +#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
> +
>  #define __DEFINE_GUEST_HANDLE(name, type) \
> -	typedef type * __guest_handle_ ## name
> +	typedef struct { union { type *p; uint64_aligned_t q; }; }  \
> +        __guest_handle_ ## name
>  
>  #define DEFINE_GUEST_HANDLE_STRUCT(name) \
>  	__DEFINE_GUEST_HANDLE(name, struct name)
> @@ -21,13 +24,14 @@
>  	do {						\
>  		if (sizeof(hnd) == 8)			\
>  			*(uint64_t *)&(hnd) = 0;	\
> -		(hnd) = val;				\
> +		(hnd).p = val;				\
>  	} while (0)
>  
>  #ifndef __ASSEMBLY__
>  /* Explicitly size integers that represent pfns in the interface with
>   * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
>  typedef uint64_t xen_pfn_t;
> +typedef uint64_t xen_ulong_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
> index 686464e..7c83445 100644
> --- a/arch/ia64/include/asm/xen/interface.h
> +++ b/arch/ia64/include/asm/xen/interface.h
> @@ -71,6 +71,7 @@
>   * with Xen so that we could have one ABI that works for 32 and 64 bit
>   * guests. */
>  typedef unsigned long xen_pfn_t;
> +typedef unsigned long xen_ulong_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint, unsigned int);
> diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> index 555f94d..28fc621 100644
> --- a/arch/x86/include/asm/xen/interface.h
> +++ b/arch/x86/include/asm/xen/interface.h
> @@ -51,6 +51,7 @@
>   * with Xen so that on ARM we can have one ABI that works for 32 and 64
>   * bit guests. */
>  typedef unsigned long xen_pfn_t;
> +typedef unsigned long xen_ulong_t;
>  /* Guest handles for primitive C types. */
>  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
>  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index abbbff0..b5c3098 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -34,7 +34,7 @@ struct xen_memory_reservation {
>      GUEST_HANDLE(xen_pfn_t) extent_start;
>  
>      /* Number of extents, and size/alignment of each (2^extent_order pages). */
> -    unsigned long  nr_extents;
> +    xen_ulong_t  nr_extents;
>      unsigned int   extent_order;
>  
>      /*
> @@ -92,7 +92,7 @@ struct xen_memory_exchange {
>       *     command will be non-zero.
>       *  5. THIS FIELD MUST BE INITIALISED TO ZERO BY THE CALLER!
>       */
> -    unsigned long nr_exchanged;
> +    xen_ulong_t nr_exchanged;
>  };
>  
>  DEFINE_GUEST_HANDLE_STRUCT(xen_memory_exchange);
> @@ -148,8 +148,8 @@ DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list);
>   */
>  #define XENMEM_machphys_mapping     12
>  struct xen_machphys_mapping {
> -    unsigned long v_start, v_end; /* Start and end virtual addresses.   */
> -    unsigned long max_mfn;        /* Maximum MFN that can be looked up. */
> +    xen_ulong_t v_start, v_end; /* Start and end virtual addresses.   */
> +    xen_ulong_t max_mfn;        /* Maximum MFN that can be looked up. */
>  };
>  DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mapping_t);
>  
> @@ -169,7 +169,7 @@ struct xen_add_to_physmap {
>      unsigned int space;
>  
>      /* Index into source mapping space. */
> -    unsigned long idx;
> +    xen_ulong_t idx;
>  
>      /* GPFN where the source mapping page should appear. */
>      xen_pfn_t gpfn;
> @@ -186,7 +186,7 @@ struct xen_translate_gpfn_list {
>      domid_t domid;
>  
>      /* Length of list. */
> -    unsigned long nr_gpfns;
> +    xen_ulong_t nr_gpfns;
>  
>      /* List of GPFNs to translate. */
>      GUEST_HANDLE(ulong) gpfn_list;
> diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h
> index 9ce788d..bc3ae14 100644
> --- a/include/xen/interface/physdev.h
> +++ b/include/xen/interface/physdev.h
> @@ -56,7 +56,7 @@ struct physdev_eoi {
>  #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
>  struct physdev_pirq_eoi_gmfn {
>      /* IN */
> -    unsigned long gmfn;
> +    xen_ulong_t gmfn;
>  };
>  
>  /*
> @@ -108,7 +108,7 @@ struct physdev_set_iobitmap {
>  #define PHYSDEVOP_apic_write		 9
>  struct physdev_apic {
>  	/* IN */
> -	unsigned long apic_physbase;
> +	xen_ulong_t apic_physbase;
>  	uint32_t reg;
>  	/* IN or OUT */
>  	uint32_t value;
> diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h
> index e8b6519..30280c9 100644
> --- a/include/xen/interface/version.h
> +++ b/include/xen/interface/version.h
> @@ -45,7 +45,7 @@ struct xen_changeset_info {
>  
>  #define XENVER_platform_parameters 5
>  struct xen_platform_parameters {
> -    unsigned long virt_start;
> +    xen_ulong_t virt_start;
>  };
>  
>  #define XENVER_get_features 6
> diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> index 42834a3..ec32115 100644
> --- a/include/xen/interface/xen.h
> +++ b/include/xen/interface/xen.h
> @@ -274,9 +274,9 @@ DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
>   * NB. The fields are natural register size for this architecture.
>   */
>  struct multicall_entry {
> -    unsigned long op;
> -    long result;
> -    unsigned long args[6];
> +    xen_ulong_t op;
> +    xen_ulong_t result;
> +    xen_ulong_t args[6];
>  };
>  DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
>  
> -- 
> 1.7.2.5


From nico at fluxnic.net  Tue Aug  7 14:28:31 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 07 Aug 2012 14:28:31 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120807173344.GD16877@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208071259270.5231@xanadu.home>
 <20120807173344.GD16877@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208071405590.5231@xanadu.home>

On Tue, 7 Aug 2012, Will Deacon wrote:

> On Tue, Aug 07, 2012 at 06:14:36PM +0100, Nicolas Pitre wrote:
> > On Tue, 7 Aug 2012, Will Deacon wrote:
> > > The symptoms are that a bunch of hackbench tasks are left waiting on an
> > > unlocked mutex and therefore never get woken up to claim it. I think this
> > > boils down to the following sequence:
> > > 
> > > 
> > >         Task A        Task B        Task C        Lock value
> > > 0                                                     1
> > > 1       lock()                                        0
> > > 2                     lock()                          0
> > > 3                     spin(A)                         0
> > > 4       unlock()                                      1
> > > 5                                   lock()            0
> > > 6                     cmpxchg(1,0)                    0
> > > 7                     contended()                    -1
> > > 8       lock()                                        0
> > > 9       spin(C)                                       0
> > > 10                                  unlock()          1
> > > 11      cmpxchg(1,0)                                  0
> > > 12      unlock()                                      1
> > > 
> > > 
> > > At this point, the lock is unlocked, but Task B is in an uninterruptible
> > > sleep with nobody to wake it up.
> > 
> > I fail to see how the lock value would go from -1 to 0 on line 8.  How 
> > does that happen?
> 
> [...]

Forget that.  I assumed cmpxchg when it is just xchg.

(And, for that matter, I'm even the original author for some of that 
 code.: http://lkml.org/lkml/2005/12/26/83).

Back to thinking.


Nicolas


From konrad.wilk at oracle.com  Tue Aug  7 14:21:57 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:21:57 -0400
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807182157.GN15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> an error.
> 
> If Linux is running as an HVM domain and is running as Dom0, use
> xenstored_local_init to initialize the xenstore page and event channel.
> 
> Changes in v2:
> 
> - refactor xenbus_init.

Thank you. Lets also CC our friend at NSA who has been doing some work
in that area. Daniel are you OK with this change - will it still make
PV initial domain with with the MiniOS XenBus driver?

Thanks.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
>  3 files changed, 45 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> index 52fe7ad..c5aa55c 100644
> --- a/drivers/xen/xenbus/xenbus_comms.c
> +++ b/drivers/xen/xenbus/xenbus_comms.c
> @@ -224,7 +224,7 @@ int xb_init_comms(void)
>  		int err;
>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
>  						0, "xenbus", &xb_waitq);
> -		if (err <= 0) {
> +		if (err < 0) {
>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
>  			return err;
>  		}

> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> index b793723..a67ccc0 100644
> --- a/drivers/xen/xenbus/xenbus_probe.c
> +++ b/drivers/xen/xenbus/xenbus_probe.c
> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
>  	return err;
>  }
>  
> +enum xenstore_init {
> +	UNKNOWN,
> +	PV,
> +	HVM,
> +	LOCAL,
> +};
>  static int __init xenbus_init(void)
>  {
>  	int err = 0;
> +	enum xenstore_init usage = UNKNOWN;
> +	uint64_t v = 0;
>  
>  	if (!xen_domain())
>  		return -ENODEV;
>  
>  	xenbus_ring_ops_init();
>  
> -	if (xen_hvm_domain()) {
> -		uint64_t v = 0;
> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> -		if (err)
> -			goto out_error;
> -		xen_store_evtchn = (int)v;
> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> -		if (err)
> -			goto out_error;
> -		xen_store_mfn = (unsigned long)v;
> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> -	} else {
> -		xen_store_evtchn = xen_start_info->store_evtchn;
> -		xen_store_mfn = xen_start_info->store_mfn;
> -		if (xen_store_evtchn)
> -			xenstored_ready = 1;
> -		else {
> +	if (xen_pv_domain())
> +		usage = PV;
> +	if (xen_hvm_domain())
> +		usage = HVM;
> +	if (xen_hvm_domain() && xen_initial_domain())
> +		usage = LOCAL;
> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
> +		usage = LOCAL;
> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
> +		xenstored_ready = 1;
> +
> +	switch (usage) {
> +		case LOCAL:
>  			err = xenstored_local_init();
>  			if (err)
>  				goto out_error;
> -		}
> -		xen_store_interface = mfn_to_virt(xen_store_mfn);
> +			xen_store_interface = mfn_to_virt(xen_store_mfn);
> +			break;
> +		case PV:
> +			xen_store_evtchn = xen_start_info->store_evtchn;
> +			xen_store_mfn = xen_start_info->store_mfn;
> +			xen_store_interface = mfn_to_virt(xen_store_mfn);
> +			break;
> +		case HVM:
> +			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> +			if (err)
> +				goto out_error;
> +			xen_store_evtchn = (int)v;
> +			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> +			if (err)
> +				goto out_error;
> +			xen_store_mfn = (unsigned long)v;
> +			xen_store_interface =
> +				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> +			break;
> +		default:
> +			pr_warn("Xenstore state unknown\n");
> +			break;
>  	}
>  
>  	/* Initialize the interface to xenstore. */
> diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
> index d1c217b..f7feb3d 100644
> --- a/drivers/xen/xenbus/xenbus_xs.c
> +++ b/drivers/xen/xenbus/xenbus_xs.c
> @@ -44,6 +44,7 @@
>  #include <linux/rwsem.h>
>  #include <linux/module.h>
>  #include <linux/mutex.h>
> +#include <asm/xen/hypervisor.h>
>  #include <xen/xenbus.h>
>  #include <xen/xen.h>
>  #include "xenbus_comms.h"
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:23:25 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:23:25 -0400
Subject: [PATCH v2 11/23] xen: do not compile manage, balloon, pci, acpi
 and cpu_hotplug on ARM
In-Reply-To: <1344263246-28036-11-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-11-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807182325.GO15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:14PM +0100, Stefano Stabellini wrote:
> Changes in v2:
> 
> - make pci.o depend on CONFIG_PCI and acpi.o depend on CONFIG_ACPI.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

Looks good.
> ---
>  drivers/xen/Makefile |   11 ++++++++---
>  1 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
> index fc34886..bee02b2 100644
> --- a/drivers/xen/Makefile
> +++ b/drivers/xen/Makefile
> @@ -1,11 +1,17 @@
> -obj-y	+= grant-table.o features.o events.o manage.o balloon.o
> +ifneq ($(CONFIG_ARM),y)
> +obj-y	+= manage.o balloon.o
> +obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
> +endif
> +obj-y	+= grant-table.o features.o events.o
>  obj-y	+= xenbus/
>  
>  nostackp := $(call cc-option, -fno-stack-protector)
>  CFLAGS_features.o			:= $(nostackp)
>  
> +obj-$(CONFIG_XEN_DOM0)			+= $(dom0-y)
> +dom0-$(CONFIG_PCI) := pci.o
> +dom0-$(CONFIG_ACPI) := acpi.o
>  obj-$(CONFIG_BLOCK)			+= biomerge.o
> -obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
>  obj-$(CONFIG_XEN_XENCOMM)		+= xencomm.o
>  obj-$(CONFIG_XEN_BALLOON)		+= xen-balloon.o
>  obj-$(CONFIG_XEN_SELFBALLOONING)	+= xen-selfballoon.o
> @@ -17,7 +23,6 @@ obj-$(CONFIG_XEN_SYS_HYPERVISOR)	+= sys-hypervisor.o
>  obj-$(CONFIG_XEN_PVHVM)			+= platform-pci.o
>  obj-$(CONFIG_XEN_TMEM)			+= tmem.o
>  obj-$(CONFIG_SWIOTLB_XEN)		+= swiotlb-xen.o
> -obj-$(CONFIG_XEN_DOM0)			+= pci.o acpi.o
>  obj-$(CONFIG_XEN_PCIDEV_BACKEND)	+= xen-pciback/
>  obj-$(CONFIG_XEN_PRIVCMD)		+= xen-privcmd.o
>  obj-$(CONFIG_XEN_ACPI_PROCESSOR)	+= xen-acpi-processor.o
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:23:37 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:23:37 -0400
Subject: [PATCH v2 12/23] xen/arm: introduce CONFIG_XEN on ARM
In-Reply-To: <1344263246-28036-12-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-12-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807182337.GP15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:15PM +0100, Stefano Stabellini wrote:
> Changes in v2:
> 
> - mark Xen guest support on ARM as EXPERIMENTAL.

OK. Looks good.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/Kconfig |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a91009c..f14664b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1855,6 +1855,16 @@ config DEPRECATED_PARAM_STRUCT
>  	  This was deprecated in 2001 and announced to live on for 5 years.
>  	  Some old boot loaders still use this way.
>  
> +config XEN_DOM0
> +	def_bool y
> +
> +config XEN
> +	bool "Xen guest support on ARM (EXPERIMENTAL)"
> +	depends on EXPERIMENTAL && ARM && OF
> +	select XEN_DOM0
> +	help
> +	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
> +
>  endmenu
>  
>  menu "Boot options"
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:24:14 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:24:14 -0400
Subject: [PATCH v2 13/23] xen/arm: get privilege status
In-Reply-To: <1344263246-28036-13-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-13-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807182414.GQ15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:16PM +0100, Stefano Stabellini wrote:
> Use Xen features to figure out if we are privileged.
> 
> XENFEAT_dom0 was introduced by 23735 in xen-unstable.hg.

Looks good.

> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c         |    7 +++++++
>  include/xen/interface/features.h |    3 +++
>  2 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 102d823..ac3a2d6 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -1,6 +1,7 @@
>  #include <xen/xen.h>
>  #include <xen/interface/xen.h>
>  #include <xen/interface/memory.h>
> +#include <xen/features.h>
>  #include <xen/platform_pci.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> @@ -57,6 +58,12 @@ static int __init xen_guest_init(void)
>  	}
>  	xen_domain_type = XEN_HVM_DOMAIN;
>  
> +	xen_setup_features();
> +	if (xen_feature(XENFEAT_dom0))
> +		xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
> +	else
> +		xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
> +
>  	if (!shared_info_page)
>  		shared_info_page = (struct shared_info *)
>  			get_zeroed_page(GFP_KERNEL);
> diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h
> index b6ca39a..131a6cc 100644
> --- a/include/xen/interface/features.h
> +++ b/include/xen/interface/features.h
> @@ -50,6 +50,9 @@
>  /* x86: pirq can be used by HVM guests */
>  #define XENFEAT_hvm_pirqs           10
>  
> +/* operation as Dom0 is supported */
> +#define XENFEAT_dom0                      11
> +
>  #define XENFEAT_NR_SUBMAPS 1
>  
>  #endif /* __XEN_PUBLIC_FEATURES_H__ */
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:30:36 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:30:36 -0400
Subject: [PATCH v2 15/23] xen/arm: receive Xen events on ARM
In-Reply-To: <1344263246-28036-15-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-15-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183036.GR15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:18PM +0100, Stefano Stabellini wrote:
> Compile events.c on ARM.
> Parse, map and enable the IRQ to get event notifications from the device
> tree (node "/xen").
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/events.h |   18 ++++++++++++++++++
>  arch/arm/xen/enlighten.c          |   33 +++++++++++++++++++++++++++++++++
>  arch/x86/xen/enlighten.c          |    1 +
>  arch/x86/xen/irq.c                |    1 +
>  arch/x86/xen/xen-ops.h            |    1 -
>  drivers/xen/events.c              |   17 ++++++++++++++---
>  include/xen/events.h              |    2 ++
>  7 files changed, 69 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/include/asm/xen/events.h
> 
> diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
> new file mode 100644
> index 0000000..94b4e90
> --- /dev/null
> +++ b/arch/arm/include/asm/xen/events.h
> @@ -0,0 +1,18 @@
> +#ifndef _ASM_ARM_XEN_EVENTS_H
> +#define _ASM_ARM_XEN_EVENTS_H
> +
> +#include <asm/ptrace.h>
> +
> +enum ipi_vector {
> +	XEN_PLACEHOLDER_VECTOR,
> +
> +	/* Xen IPIs go here */
> +	XEN_NR_IPIS,
> +};
> +
> +static inline int xen_irqs_disabled(struct pt_regs *regs)
> +{
> +	return raw_irqs_disabled_flags(regs->ARM_cpsr);
> +}
> +
> +#endif /* _ASM_ARM_XEN_EVENTS_H */
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index e5e92d5..87b17f0 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -1,4 +1,5 @@
>  #include <xen/xen.h>
> +#include <xen/events.h>
>  #include <xen/grant_table.h>
>  #include <xen/hvm.h>
>  #include <xen/interface/xen.h>
> @@ -9,6 +10,8 @@
>  #include <xen/xenbus.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqreturn.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_irq.h>
> @@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
>  int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
>  EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
>  
> +static __read_mostly int xen_events_irq = -1;
> +

So this is global..
>  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  			       unsigned long addr,
>  			       unsigned long mfn, int nr,
> @@ -66,6 +71,9 @@ static int __init xen_guest_init(void)
>  	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
>  		return 0;
>  	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
> +	xen_events_irq = irq_of_parse_and_map(node, 0);
> +	pr_info("Xen support found, events_irq=%d gnttab_frame_pfn=%lx\n",
> +			xen_events_irq, xen_hvm_resume_frames);
>  	xen_domain_type = XEN_HVM_DOMAIN;
>  
>  	xen_setup_features();
> @@ -107,3 +115,28 @@ static int __init xen_guest_init(void)
>  	return 0;
>  }
>  core_initcall(xen_guest_init);
> +
> +static irqreturn_t xen_arm_callback(int irq, void *arg)
> +{
> +	xen_hvm_evtchn_do_upcall();
> +	return IRQ_HANDLED;
> +}
> +
> +static int __init xen_init_events(void)
> +{
> +	if (!xen_domain() || xen_events_irq < 0)
> +		return -ENODEV;
> +
> +	xen_init_IRQ();
> +
> +	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
> +			"events", xen_vcpu)) {

But here you are asking for it to be percpu? What if there are other
interrupts on the _other_ CPUs that conflict with it?
> +		pr_err("Error requesting IRQ %d\n", xen_events_irq);
> +		return -EINVAL;
> +	}
> +
> +	enable_percpu_irq(xen_events_irq, 0);

Uh, that is bold. One global to rule them all, eh? Should you make
it at least:
static DEFINE_PER_CPU(int, xen_events_irq);
?

> +
> +	return 0;
> +}
> +postcore_initcall(xen_init_events);
> diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
> index ff962d4..9f8b0ef 100644
> --- a/arch/x86/xen/enlighten.c
> +++ b/arch/x86/xen/enlighten.c
> @@ -33,6 +33,7 @@
>  #include <linux/memblock.h>
>  
>  #include <xen/xen.h>
> +#include <xen/events.h>
>  #include <xen/interface/xen.h>
>  #include <xen/interface/version.h>
>  #include <xen/interface/physdev.h>
> diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
> index 1573376..01a4dc0 100644
> --- a/arch/x86/xen/irq.c
> +++ b/arch/x86/xen/irq.c
> @@ -5,6 +5,7 @@
>  #include <xen/interface/xen.h>
>  #include <xen/interface/sched.h>
>  #include <xen/interface/vcpu.h>
> +#include <xen/events.h>
>  
>  #include <asm/xen/hypercall.h>
>  #include <asm/xen/hypervisor.h>
> diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
> index 202d4c1..2368295 100644
> --- a/arch/x86/xen/xen-ops.h
> +++ b/arch/x86/xen/xen-ops.h
> @@ -35,7 +35,6 @@ void xen_set_pat(u64);
>  
>  char * __init xen_memory_setup(void);
>  void __init xen_arch_setup(void);
> -void __init xen_init_IRQ(void);
>  void xen_enable_sysenter(void);
>  void xen_enable_syscall(void);
>  void xen_vcpu_restore(void);
> diff --git a/drivers/xen/events.c b/drivers/xen/events.c
> index 7595581..5ecb596 100644
> --- a/drivers/xen/events.c
> +++ b/drivers/xen/events.c
> @@ -31,14 +31,16 @@
>  #include <linux/irqnr.h>
>  #include <linux/pci.h>
>  
> +#ifdef CONFIG_X86
>  #include <asm/desc.h>
>  #include <asm/ptrace.h>
>  #include <asm/irq.h>
>  #include <asm/idle.h>
>  #include <asm/io_apic.h>
> -#include <asm/sync_bitops.h>
>  #include <asm/xen/page.h>
>  #include <asm/xen/pci.h>
> +#endif
> +#include <asm/sync_bitops.h>
>  #include <asm/xen/hypercall.h>
>  #include <asm/xen/hypervisor.h>
>  
> @@ -50,6 +52,9 @@
>  #include <xen/interface/event_channel.h>
>  #include <xen/interface/hvm/hvm_op.h>
>  #include <xen/interface/hvm/params.h>
> +#include <xen/interface/physdev.h>
> +#include <xen/interface/sched.h>
> +#include <asm/hw_irq.h>
>  
>  /*
>   * This lock protects updates to the following mapping and reference-count
> @@ -1374,7 +1379,9 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
>  {
>  	struct pt_regs *old_regs = set_irq_regs(regs);
>  
> +#ifdef CONFIG_X86

Please explain this with a comment.

>  	exit_idle();
> +#endif
>  	irq_enter();
>  
>  	__xen_evtchn_do_upcall();
> @@ -1783,9 +1790,9 @@ void xen_callback_vector(void)
>  void xen_callback_vector(void) {}
>  #endif
>  
> -void __init xen_init_IRQ(void)
> +void xen_init_IRQ(void)
>  {
> -	int i, rc;
> +	int i;
>  
>  	evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
>  				    GFP_KERNEL);
> @@ -1801,6 +1808,7 @@ void __init xen_init_IRQ(void)
>  
>  	pirq_needs_eoi = pirq_needs_eoi_flag;
>  
> +#ifdef CONFIG_X86
>  	if (xen_hvm_domain()) {
>  		xen_callback_vector();
>  		native_init_IRQ();
> @@ -1808,6 +1816,7 @@ void __init xen_init_IRQ(void)
>  		 * __acpi_register_gsi can point at the right function */
>  		pci_xen_hvm_init();
>  	} else {
> +		int rc;
>  		struct physdev_pirq_eoi_gmfn eoi_gmfn;
>  
>  		irq_ctx_init(smp_processor_id());
> @@ -1823,4 +1832,6 @@ void __init xen_init_IRQ(void)
>  		} else
>  			pirq_needs_eoi = pirq_check_eoi_map;
>  	}
> +#endif
>  }
> +EXPORT_SYMBOL_GPL(xen_init_IRQ);
> diff --git a/include/xen/events.h b/include/xen/events.h
> index 04399b2..c6bfe01 100644
> --- a/include/xen/events.h
> +++ b/include/xen/events.h
> @@ -109,4 +109,6 @@ int xen_irq_from_gsi(unsigned gsi);
>  /* Determine whether to ignore this IRQ if it is passed to a guest. */
>  int xen_test_irq_shared(int irq);
>  
> +/* initialize Xen IRQ subsystem */
> +void xen_init_IRQ(void);
>  #endif	/* _XEN_EVENTS_H */
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:31:23 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:31:23 -0400
Subject: [PATCH v2 16/23] xen: clear IRQ_NOAUTOEN and IRQ_NOREQUEST
In-Reply-To: <1344263246-28036-16-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-16-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183123.GS15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:19PM +0100, Stefano Stabellini wrote:
> Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
> default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
> irq_startup, that is responsible for calling irq_unmask at startup time.
> As a result event channels remain masked.

Acked by me.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/xen/events.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/xen/events.c b/drivers/xen/events.c
> index 5ecb596..8ffb7b7 100644
> --- a/drivers/xen/events.c
> +++ b/drivers/xen/events.c
> @@ -836,6 +836,7 @@ int bind_evtchn_to_irq(unsigned int evtchn)
>  		struct irq_info *info = info_for_irq(irq);
>  		WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
>  	}
> +	irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
>  
>  out:
>  	mutex_unlock(&irq_mapping_update_lock);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:31:35 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:31:35 -0400
Subject: [PATCH v2 17/23] xen/arm: implement
 alloc/free_xenballooned_pages with alloc_pages/kfree
In-Reply-To: <1344263246-28036-17-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-17-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183135.GT15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:20PM +0100, Stefano Stabellini wrote:
> Only until we get the balloon driver to work.

OK. Acked-by be.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c |   18 ++++++++++++++++++
>  1 files changed, 18 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index 87b17f0..c244583 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -140,3 +140,21 @@ static int __init xen_init_events(void)
>  	return 0;
>  }
>  postcore_initcall(xen_init_events);
> +
> +/* XXX: only until balloon is properly working */
> +int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
> +{
> +	*pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
> +			get_order(nr_pages));
> +	if (*pages == NULL)
> +		return -ENOMEM;
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
> +
> +void free_xenballooned_pages(int nr_pages, struct page **pages)
> +{
> +	kfree(*pages);
> +	*pages = NULL;
> +}
> +EXPORT_SYMBOL_GPL(free_xenballooned_pages);
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:31:55 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:31:55 -0400
Subject: [PATCH v2 18/23] xen: allow privcmd for HVM guests
In-Reply-To: <1344263246-28036-18-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-18-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183155.GU15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:21PM +0100, Stefano Stabellini wrote:
> This patch removes the "return -ENOSYS" for auto_translated_physmap
> guests from privcmd_mmap, thus it allows ARM guests to issue privcmd
> mmap calls. However privcmd mmap calls are still going to fail for HVM
> and hybrid guests on x86 because the xen_remap_domain_mfn_range
> implementation is currently PV only.

Looks good. Ack from me.
> 
> Changes in v2:
> 
> - better commit message;
> - return -EINVAL from xen_remap_domain_mfn_range if
>   auto_translated_physmap.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/x86/xen/mmu.c    |    3 +++
>  drivers/xen/privcmd.c |    4 ----
>  2 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
> index 3a73785..885a223 100644
> --- a/arch/x86/xen/mmu.c
> +++ b/arch/x86/xen/mmu.c
> @@ -2310,6 +2310,9 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  	unsigned long range;
>  	int err = 0;
>  
> +	if (xen_feature(XENFEAT_auto_translated_physmap))
> +		return -EINVAL;
> +
>  	prot = __pgprot(pgprot_val(prot) | _PAGE_IOMAP);
>  
>  	BUG_ON(!((vma->vm_flags & (VM_PFNMAP | VM_RESERVED | VM_IO)) ==
> diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
> index ccee0f1..85226cb 100644
> --- a/drivers/xen/privcmd.c
> +++ b/drivers/xen/privcmd.c
> @@ -380,10 +380,6 @@ static struct vm_operations_struct privcmd_vm_ops = {
>  
>  static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
>  {
> -	/* Unsupported for auto-translate guests. */
> -	if (xen_feature(XENFEAT_auto_translated_physmap))
> -		return -ENOSYS;
> -
>  	/* DONTCOPY is essential for Xen because copy_page_range doesn't know
>  	 * how to recreate these mappings */
>  	vma->vm_flags |= VM_RESERVED | VM_IO | VM_DONTCOPY | VM_PFNMAP;
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:32:09 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:32:09 -0400
Subject: [PATCH v2 19/23] xen/arm: compile blkfront and blkback
In-Reply-To: <1344263246-28036-19-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-19-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183209.GV15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:22PM +0100, Stefano Stabellini wrote:

OK. Looks good.
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  drivers/block/xen-blkback/blkback.c  |    1 +
>  include/xen/interface/io/protocols.h |    3 +++
>  2 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
> index 73f196c..63dd5b9 100644
> --- a/drivers/block/xen-blkback/blkback.c
> +++ b/drivers/block/xen-blkback/blkback.c
> @@ -42,6 +42,7 @@
>  
>  #include <xen/events.h>
>  #include <xen/page.h>
> +#include <xen/xen.h>
>  #include <asm/xen/hypervisor.h>
>  #include <asm/xen/hypercall.h>
>  #include "common.h"
> diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
> index 01fc8ae..0eafaf2 100644
> --- a/include/xen/interface/io/protocols.h
> +++ b/include/xen/interface/io/protocols.h
> @@ -5,6 +5,7 @@
>  #define XEN_IO_PROTO_ABI_X86_64     "x86_64-abi"
>  #define XEN_IO_PROTO_ABI_IA64       "ia64-abi"
>  #define XEN_IO_PROTO_ABI_POWERPC64  "powerpc64-abi"
> +#define XEN_IO_PROTO_ABI_ARM        "arm-abi"
>  
>  #if defined(__i386__)
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
> @@ -14,6 +15,8 @@
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
>  #elif defined(__powerpc64__)
>  # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
> +#elif defined(__arm__)
> +# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
>  #else
>  # error arch fixup needed here
>  #endif
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:32:35 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:32:35 -0400
Subject: [PATCH v2 20/23] xen/arm: compile netback
In-Reply-To: <1344263246-28036-20-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-20-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183235.GW15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:23PM +0100, Stefano Stabellini wrote:
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>

OK. Looks good.
> ---
>  arch/arm/include/asm/xen/hypercall.h |   19 +++++++++++++++++++
>  drivers/net/xen-netback/netback.c    |    1 +
>  drivers/net/xen-netfront.c           |    1 +
>  3 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
> index 4ac0624..8a82325 100644
> --- a/arch/arm/include/asm/xen/hypercall.h
> +++ b/arch/arm/include/asm/xen/hypercall.h
> @@ -47,4 +47,23 @@ unsigned long HYPERVISOR_hvm_op(int op, void *arg);
>  int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
>  int HYPERVISOR_physdev_op(int cmd, void *arg);
>  
> +static inline void
> +MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
> +			unsigned int new_val, unsigned long flags)
> +{
> +	BUG();
> +}
> +
> +static inline void
> +MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
> +		 int count, int *success_count, domid_t domid)
> +{
> +	BUG();
> +}
> +
> +static inline int
> +HYPERVISOR_multicall(void *call_list, int nr_calls)
> +{
> +	BUG();
> +}
>  #endif /* _ASM_ARM_XEN_HYPERCALL_H */
> diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
> index f4a6fca..ab4f81c 100644
> --- a/drivers/net/xen-netback/netback.c
> +++ b/drivers/net/xen-netback/netback.c
> @@ -40,6 +40,7 @@
>  
>  #include <net/tcp.h>
>  
> +#include <xen/xen.h>
>  #include <xen/events.h>
>  #include <xen/interface/memory.h>
>  
> diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
> index 3089990..bf4ba2b 100644
> --- a/drivers/net/xen-netfront.c
> +++ b/drivers/net/xen-netfront.c
> @@ -43,6 +43,7 @@
>  #include <linux/slab.h>
>  #include <net/ip.h>
>  
> +#include <asm/xen/page.h>
>  #include <xen/xen.h>
>  #include <xen/xenbus.h>
>  #include <xen/events.h>
> -- 
> 1.7.2.5


From konrad.wilk at oracle.com  Tue Aug  7 14:33:06 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:33:06 -0400
Subject: [PATCH v2 21/23] xen: update xen_add_to_physmap interface
In-Reply-To: <1344263246-28036-21-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-21-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183306.GX15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:24PM +0100, Stefano Stabellini wrote:
> Update struct xen_add_to_physmap to be in sync with Xen's version of the
> structure.
> The size field was introduced by:
> 
> changeset:   24164:707d27fe03e7
> user:        Jean Guyader <jean.guyader at eu.citrix.com>
> date:        Fri Nov 18 13:42:08 2011 +0000
> summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range
> 
> According to the comment:
> 
> "This new field .size is located in the 16 bits padding between .domid
> and .space in struct xen_add_to_physmap to stay compatible with older
> versions."
> 
> Changes in v2:

Looks good. Let me take this as in my tree to prep it for Mukesh's patches.

> 
> - remove erroneous comment in the commit message.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  include/xen/interface/memory.h |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index b5c3098..b66d04c 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -163,6 +163,9 @@ struct xen_add_to_physmap {
>      /* Which domain to change the mapping for. */
>      domid_t domid;
>  
> +    /* Number of pages to go through for gmfn_range */
> +    uint16_t    size;
> +
>      /* Source mapping space. */
>  #define XENMAPSPACE_shared_info 0 /* shared info page */
>  #define XENMAPSPACE_grant_table 1 /* grant table page */
> -- 
> 1.7.2.5


From dgdegra at tycho.nsa.gov  Tue Aug  7 14:44:56 2012
From: dgdegra at tycho.nsa.gov (Daniel De Graaf)
Date: Tue, 07 Aug 2012 14:44:56 -0400
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <20120807182157.GN15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com>
Message-ID: <50216228.7010407@tycho.nsa.gov>

On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
>> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
>> an error.
>>
>> If Linux is running as an HVM domain and is running as Dom0, use
>> xenstored_local_init to initialize the xenstore page and event channel.
>>
>> Changes in v2:
>>
>> - refactor xenbus_init.
> 
> Thank you. Lets also CC our friend at NSA who has been doing some work
> in that area. Daniel are you OK with this change - will it still make
> PV initial domain with with the MiniOS XenBus driver?
> 
> Thanks.

That case will work, but what this will break is launching the initial domain
with a Xenstore stub domain already running (see below).

>>
>> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
>> ---
>>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
>>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
>>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
>>  3 files changed, 45 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
>> index 52fe7ad..c5aa55c 100644
>> --- a/drivers/xen/xenbus/xenbus_comms.c
>> +++ b/drivers/xen/xenbus/xenbus_comms.c
>> @@ -224,7 +224,7 @@ int xb_init_comms(void)
>>  		int err;
>>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
>>  						0, "xenbus", &xb_waitq);
>> -		if (err <= 0) {
>> +		if (err < 0) {
>>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
>>  			return err;
>>  		}
> 
>> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
>> index b793723..a67ccc0 100644
>> --- a/drivers/xen/xenbus/xenbus_probe.c
>> +++ b/drivers/xen/xenbus/xenbus_probe.c
>> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
>>  	return err;
>>  }
>>  
>> +enum xenstore_init {
>> +	UNKNOWN,
>> +	PV,
>> +	HVM,
>> +	LOCAL,
>> +};
>>  static int __init xenbus_init(void)
>>  {
>>  	int err = 0;
>> +	enum xenstore_init usage = UNKNOWN;
>> +	uint64_t v = 0;
>>  
>>  	if (!xen_domain())
>>  		return -ENODEV;
>>  
>>  	xenbus_ring_ops_init();
>>  
>> -	if (xen_hvm_domain()) {
>> -		uint64_t v = 0;
>> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
>> -		if (err)
>> -			goto out_error;
>> -		xen_store_evtchn = (int)v;
>> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
>> -		if (err)
>> -			goto out_error;
>> -		xen_store_mfn = (unsigned long)v;
>> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
>> -	} else {
>> -		xen_store_evtchn = xen_start_info->store_evtchn;
>> -		xen_store_mfn = xen_start_info->store_mfn;
>> -		if (xen_store_evtchn)
>> -			xenstored_ready = 1;
>> -		else {
>> +	if (xen_pv_domain())
>> +		usage = PV;
>> +	if (xen_hvm_domain())
>> +		usage = HVM;

The above is correct for domUs, and is overridden for dom0s:

>> +	if (xen_hvm_domain() && xen_initial_domain())
>> +		usage = LOCAL;
>> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
>> +		usage = LOCAL;

Instead of these checks, I think it should just be:

if (!xen_start_info->store_evtchn)
	usage = LOCAL;

Any domain started after xenstore will have store_evtchn set, so if you don't
have this set, you are either going to be running xenstore locally, or will
use the ioctl to change it later (and so should still set up everything as if
it will be running locally).

>> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
>> +		xenstored_ready = 1;

This part can now just be moved unconditionally into case PV.

>> +
>> +	switch (usage) {
>> +		case LOCAL:
>>  			err = xenstored_local_init();
>>  			if (err)
>>  				goto out_error;
>> -		}
>> -		xen_store_interface = mfn_to_virt(xen_store_mfn);
>> +			xen_store_interface = mfn_to_virt(xen_store_mfn);
>> +			break;
>> +		case PV:
>> +			xen_store_evtchn = xen_start_info->store_evtchn;
>> +			xen_store_mfn = xen_start_info->store_mfn;
>> +			xen_store_interface = mfn_to_virt(xen_store_mfn);
>> +			break;
>> +		case HVM:
>> +			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
>> +			if (err)
>> +				goto out_error;
>> +			xen_store_evtchn = (int)v;
>> +			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
>> +			if (err)
>> +				goto out_error;
>> +			xen_store_mfn = (unsigned long)v;
>> +			xen_store_interface =
>> +				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
>> +			break;
>> +		default:
>> +			pr_warn("Xenstore state unknown\n");
>> +			break;
>>  	}
>>  
>>  	/* Initialize the interface to xenstore. */
>> diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
>> index d1c217b..f7feb3d 100644
>> --- a/drivers/xen/xenbus/xenbus_xs.c
>> +++ b/drivers/xen/xenbus/xenbus_xs.c
>> @@ -44,6 +44,7 @@
>>  #include <linux/rwsem.h>
>>  #include <linux/module.h>
>>  #include <linux/mutex.h>
>> +#include <asm/xen/hypervisor.h>
>>  #include <xen/xenbus.h>
>>  #include <xen/xen.h>
>>  #include "xenbus_comms.h"
>> -- 
>> 1.7.2.5


-- 
Daniel De Graaf
National Security Agency


From wade_farnsworth at mentor.com  Tue Aug  7 14:46:59 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Tue, 7 Aug 2012 11:46:59 -0700
Subject: Status of patch 7375/1
In-Reply-To: <20120807181359.GK18957@n2100.arm.linux.org.uk>
References: <50214F7D.6040001@mentor.com>
 <20120807175923.GF16877@mudshark.cambridge.arm.com>
 <20120807181359.GK18957@n2100.arm.linux.org.uk>
Message-ID: <502162A3.1020502@mentor.com>

Russell King - ARM Linux wrote:
> On Tue, Aug 07, 2012 at 06:59:23PM +0100, Will Deacon wrote:
>> Wade,
>>
>> On Tue, Aug 07, 2012 at 06:25:17PM +0100, Wade Farnsworth wrote:
>>> I'm inquiring regarding the status of patch 7375/1 in the patch tracker:
>>>
>>> http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7375/1
>>>
>>> The other two patches in the series were approved and are now in Linus's
>>> tree.  However this one never received approval, nor any comments
>>> indicating that it was rejected.  What is the status of this patch?  Is
>>> there anything I can do to help move it forward?
>>
>> There have been a bunch of fixes to the audit, syscall tracing and signal
>> handling code so you'll probably need to rebase your patch on top of
>> 3.6-rc1. I think I CC'd you at the time (at least, that was my intention!).
>
> Yes, it became impossible to apply when all the syscall/audit fixes went
> in, which was more important than adding a new feature.
>
> I think the audit/syscall fixes have settled now, so as Will says...
>
>> Would you be able to do that and send it to the list again please?
>
> Thanks.

Fair enough.  I'll see about on rebasing the patch against 3.6-rc1.

Thanks for the quick response.

Wade


From konrad.wilk at oracle.com  Tue Aug  7 14:39:26 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Tue, 7 Aug 2012 14:39:26 -0400
Subject: [PATCH v2 23/23] [HACK] xen/arm: implement
 xen_remap_domain_mfn_range
In-Reply-To: <1344263246-28036-23-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-23-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120807183926.GY15053@phenom.dumpdata.com>

On Mon, Aug 06, 2012 at 03:27:26PM +0100, Stefano Stabellini wrote:
> From: Ian Campbell <Ian.Campbell at citrix.com>
> 
> Do not apply!

OK.
> 
> This is a simple, hacky implementation of xen_remap_domain_mfn_range,
> using XENMAPSPACE_gmfn_foreign.
> 
> It should use same interface as hybrid x86.

Yeah, Mukesh - can you share your patch here please?
> 
> Changes in v2:
> 
> - retain binary compatibility in xen_add_to_physmap: use a union.
> 
> Signed-off-by: Ian Campbell <Ian.Campbell at citrix.com>
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/xen/enlighten.c       |   79 +++++++++++++++++++++++++++++++++++++++-
>  drivers/xen/privcmd.c          |   16 +++++----
>  drivers/xen/xenfs/super.c      |    7 ++++
>  include/xen/interface/memory.h |   15 ++++++--
>  4 files changed, 105 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> index c244583..20ca1e4 100644
> --- a/arch/arm/xen/enlighten.c
> +++ b/arch/arm/xen/enlighten.c
> @@ -16,6 +16,10 @@
>  #include <linux/of.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_address.h>
> +#include <linux/mm.h>
> +#include <linux/ioport.h>
> +
> +#include <asm/pgtable.h>
>  
>  struct start_info _xen_start_info;
>  struct start_info *xen_start_info = &_xen_start_info;
> @@ -38,12 +42,85 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
>  
>  static __read_mostly int xen_events_irq = -1;
>  
> +#define FOREIGN_MAP_BUFFER 0x90000000UL
> +#define FOREIGN_MAP_BUFFER_SIZE 0x10000000UL
> +struct resource foreign_map_resource = {
> +	.start = FOREIGN_MAP_BUFFER,
> +	.end = FOREIGN_MAP_BUFFER + FOREIGN_MAP_BUFFER_SIZE,
> +	.name = "Xen foreign map buffer",
> +	.flags = 0,
> +};
> +
> +static unsigned long foreign_map_buffer_pfn = FOREIGN_MAP_BUFFER >> PAGE_SHIFT;
> +
> +struct remap_data {
> +	struct mm_struct *mm;
> +	unsigned long mfn;
> +	pgprot_t prot;
> +};
> +
> +static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
> +				 unsigned long addr, void *data)
> +{
> +	struct remap_data *rmd = data;
> +	pte_t pte = pfn_pte(rmd->mfn, rmd->prot);
> +
> +	if (rmd->mfn < 0x90010)
> +		pr_crit("%s: ptep %p addr %#lx => %#x / %#lx\n",
> +		       __func__, ptep, addr, pte_val(pte), rmd->mfn);
> +
> +	set_pte_at(rmd->mm, addr, ptep, pte);
> +
> +	rmd->mfn++;
> +	return 0;
> +}
> +
>  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
>  			       unsigned long addr,
>  			       unsigned long mfn, int nr,
>  			       pgprot_t prot, unsigned domid)
>  {
> -	return -ENOSYS;
> +	int i, rc = 0;
> +	struct remap_data rmd = {
> +		.mm = vma->vm_mm,
> +		.prot = prot,
> +	};
> +	struct xen_add_to_physmap xatp = {
> +		.domid = DOMID_SELF,
> +		.space = XENMAPSPACE_gmfn_foreign,
> +
> +		.foreign_domid = domid,
> +	};
> +
> +	if (foreign_map_buffer_pfn + nr > ((FOREIGN_MAP_BUFFER +
> +					FOREIGN_MAP_BUFFER_SIZE)>>PAGE_SHIFT)) {
> +		pr_crit("RAM out of foreign map buffers...\n");
> +		return -EBUSY;
> +	}
> +
> +	for (i = 0; i < nr; i++) {
> +		xatp.idx = mfn + i;
> +		xatp.gpfn = foreign_map_buffer_pfn + i;
> +		rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
> +		if (rc != 0) {
> +			pr_crit("foreign map add_to_physmap failed, err=%d\n", rc);
> +			goto out;
> +		}
> +	}
> +
> +	rmd.mfn = foreign_map_buffer_pfn;
> +	rc = apply_to_page_range(vma->vm_mm,
> +				 addr,
> +				 (unsigned long)nr << PAGE_SHIFT,
> +				 remap_area_mfn_pte_fn, &rmd);
> +	if (rc != 0) {
> +		pr_crit("apply_to_page_range failed rc=%d\n", rc);
> +		goto out;
> +	}
> +
> +	foreign_map_buffer_pfn += nr;
> +out:
> +	return rc;
>  }
>  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
>  
> diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
> index 85226cb..3e15c22 100644
> --- a/drivers/xen/privcmd.c
> +++ b/drivers/xen/privcmd.c
> @@ -20,6 +20,8 @@
>  #include <linux/pagemap.h>
>  #include <linux/seq_file.h>
>  #include <linux/miscdevice.h>
> +#include <linux/resource.h>
> +#include <linux/ioport.h>
>  
>  #include <asm/pgalloc.h>
>  #include <asm/pgtable.h>
> @@ -196,9 +198,6 @@ static long privcmd_ioctl_mmap(void __user *udata)
>  	LIST_HEAD(pagelist);
>  	struct mmap_mfn_state state;
>  
> -	if (!xen_initial_domain())
> -		return -EPERM;
> -
>  	if (copy_from_user(&mmapcmd, udata, sizeof(mmapcmd)))
>  		return -EFAULT;
>  
> @@ -286,9 +285,6 @@ static long privcmd_ioctl_mmap_batch(void __user *udata)
>  	LIST_HEAD(pagelist);
>  	struct mmap_batch_state state;
>  
> -	if (!xen_initial_domain())
> -		return -EPERM;
> -
>  	if (copy_from_user(&m, udata, sizeof(m)))
>  		return -EFAULT;
>  
> @@ -365,6 +361,11 @@ static long privcmd_ioctl(struct file *file,
>  	return ret;
>  }
>  
> +static void privcmd_close(struct vm_area_struct *vma)
> +{
> +	/* TODO: unmap VMA */
> +}
> +
>  static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
>  {
>  	printk(KERN_DEBUG "privcmd_fault: vma=%p %lx-%lx, pgoff=%lx, uv=%p\n",
> @@ -375,7 +376,8 @@ static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
>  }
>  
>  static struct vm_operations_struct privcmd_vm_ops = {
> -	.fault = privcmd_fault
> +	.fault = privcmd_fault,
> +	.close = privcmd_close,
>  };
>  
>  static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
> diff --git a/drivers/xen/xenfs/super.c b/drivers/xen/xenfs/super.c
> index a84b53c..edbe22f 100644
> --- a/drivers/xen/xenfs/super.c
> +++ b/drivers/xen/xenfs/super.c
> @@ -12,6 +12,7 @@
>  #include <linux/module.h>
>  #include <linux/fs.h>
>  #include <linux/magic.h>
> +#include <linux/ioport.h>
>  
>  #include <xen/xen.h>
>  
> @@ -80,6 +81,8 @@ static const struct file_operations capabilities_file_ops = {
>  	.llseek = default_llseek,
>  };
>  
> +extern struct resource foreign_map_resource;
> +
>  static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
>  {
>  	static struct tree_descr xenfs_files[] = {
> @@ -100,6 +103,10 @@ static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
>  				  &xsd_kva_file_ops, NULL, S_IRUSR|S_IWUSR);
>  		xenfs_create_file(sb, sb->s_root, "xsd_port",
>  				  &xsd_port_file_ops, NULL, S_IRUSR|S_IWUSR);
> +		rc = request_resource(&iomem_resource, &foreign_map_resource);
> +		if (rc < 0)
> +			pr_crit("failed to register foreign map resource\n");
> +		rc = 0; /* ignore */
>  	}
>  
>  	return rc;
> diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> index b66d04c..dd2ffe0 100644
> --- a/include/xen/interface/memory.h
> +++ b/include/xen/interface/memory.h
> @@ -163,12 +163,19 @@ struct xen_add_to_physmap {
>      /* Which domain to change the mapping for. */
>      domid_t domid;
>  
> -    /* Number of pages to go through for gmfn_range */
> -    uint16_t    size;
> +    union {
> +        /* Number of pages to go through for gmfn_range */
> +        uint16_t    size;
> +        /* IFF gmfn_foreign */
> +        domid_t foreign_domid;
> +    };
>  
>      /* Source mapping space. */
> -#define XENMAPSPACE_shared_info 0 /* shared info page */
> -#define XENMAPSPACE_grant_table 1 /* grant table page */
> +#define XENMAPSPACE_shared_info  0 /* shared info page */
> +#define XENMAPSPACE_grant_table  1 /* grant table page */
> +#define XENMAPSPACE_gmfn         2 /* GMFN */
> +#define XENMAPSPACE_gmfn_range   3 /* GMFN range */
> +#define XENMAPSPACE_gmfn_foreign 4 /* GMFN from another guest */
>      unsigned int space;
>  
>      /* Index into source mapping space. */
> -- 
> 1.7.2.5


From tobetter at gmail.com  Tue Aug  7 14:49:56 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Wed,  8 Aug 2012 03:49:56 +0900
Subject: [PATCH v2] ODROID-X: hkdk4412: Add new hardware based on Exynos4412
In-Reply-To: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <1344365401-18591-1-git-send-email-dongjin.kim@agreeyamobility.net>

The HKDK4412 is the CPU module developed by Hardkernel which is based on
Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine ID
(4289) is registered.

Changes in v2:
  -. Change regulator's display names

Change-Id: Iea6825a17b2e13f96bc6d892dd5135cad899b5df
Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/mach-exynos/Kconfig         |   23 +
 arch/arm/mach-exynos/Makefile        |    1 +
 arch/arm/mach-exynos/mach-hkdk4412.c |  964 ++++++++++++++++++++++++++++++++++
 arch/arm/tools/mach-types            |    1 +
 4 files changed, 989 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..ae90773 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -54,6 +54,9 @@ config SOC_EXYNOS4412
 	default y
 	depends on ARCH_EXYNOS4
 	select SAMSUNG_DMADEV
+	select S5P_PM if PM
+	select S5P_SLEEP if PM
+	select PM_GENERIC_DOMAINS
 	help
 	  Enable EXYNOS4412 SoC support
 
@@ -394,6 +397,26 @@ config MACH_SMDK4412
 	select MACH_SMDK4212
 	help
 	  Machine support for Samsung SMDK4412
+
+config MACH_HKDK4412
+	bool "HKDK4412"
+	select SOC_EXYNOS4412
+	select MACH_SMDK4212
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_USB_HSOTG
+	select S5P_DEV_CSIS0
+	select S5P_DEV_G2D
+	select S5P_DEV_JPEG
+	select S5P_DEV_USB_EHCI
+	select S5P_DEV_I2C_HDMIPHY
+	select S5P_DEV_TV
+	select S5P_GPIO_INT
+	select EXYNOS4_DEV_USB_OHCI
+	select SAMSUNG_DEV_ADC
+	help
+	  Machine support for Odroid-X based on Samsung EXYNOS4412
+
 endif
 
 comment "Flattened Device Tree based board for EXYNOS SoCs"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024..dccc381 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o
 
 obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
+obj-$(CONFIG_MACH_HKDK4412)		+= mach-hkdk4412.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
diff --git a/arch/arm/mach-exynos/mach-hkdk4412.c b/arch/arm/mach-exynos/mach-hkdk4412.c
new file mode 100644
index 0000000..0bd1e6d
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-hkdk4412.c
@@ -0,0 +1,964 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-hkdk4412.c
+ *
+ * Copyright (c) 2012 AgreeYa Mobility Co., Ltd.
+ *		http://www.agreeyamobility.net
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max77686.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/mfc.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+#include <plat/ehci.h>
+
+#include <mach/ohci.h>
+#include <mach/map.h>
+
+#include "common.h"
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define HKDK4412_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define HKDK4412_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define HKDK4412_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg hkdk4412_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= HKDK4412_UCON_DEFAULT,
+		.ulcon		= HKDK4412_ULCON_DEFAULT,
+		.ufcon		= HKDK4412_UFCON_DEFAULT,
+	},
+};
+
+static struct s3c_sdhci_platdata hkdk4412_hsmmc2_pdata __initdata = {
+	.cd_type	= S3C_SDHCI_CD_INTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+	.max_width	= 8,
+	.host_caps	= MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata hkdk4412_hsmmc3_pdata __initdata = {
+	.cd_type	= S3C_SDHCI_CD_INTERNAL,
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck1_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck2_consumer[] = {
+	REGULATOR_SUPPLY("vdd_arm", NULL),	/* CPUFREQ */
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck3_consumer[] = {
+	REGULATOR_SUPPLY("vdd_int", NULL),	/* CPUFREQ */
+};
+
+static struct regulator_consumer_supply __initdata max77686_buck4_consumer[] = {
+	REGULATOR_SUPPLY("vdd_g3d", "mali_drm"),	/* G3D */
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo1_consumer[] = {
+	REGULATOR_SUPPLY("vdd_alive", NULL),	/* ALIVE */
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo3_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo4_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo5_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo8_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo10_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo11_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo13_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo14_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo17_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo18_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo19_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo23_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo24_consumer[] = {
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo25_consumer[] = {
+	REGULATOR_SUPPLY("vddq_lcd", NULL),
+};
+
+static struct regulator_consumer_supply __initdata max77686_ldo26_consumer[] = {
+};
+
+static struct regulator_init_data __initdata max77686_buck1_data = {
+	.constraints = {
+		.name		= "VDD_MIF_1.0V",
+		.min_uV		= 800000,
+		.max_uV		= 1050000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck1_consumer),
+	.consumer_supplies = max77686_buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck2_data = {
+	.constraints = {
+		.name		= "VDD_ARM_1.3V",
+		.min_uV		= 800000,
+		.max_uV		= 1350000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck2_consumer),
+	.consumer_supplies = max77686_buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck3_data = {
+	.constraints = {
+		.name		= "VDD_INT_1.0V",
+		.min_uV		= 800000,
+		.max_uV		= 1150000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck3_consumer),
+	.consumer_supplies = max77686_buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck4_data = {
+	.constraints = {
+		.name		= "VDD_G3D_1.0V",
+		.min_uV		= 850000,
+		.max_uV		= 1200000,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+				  REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_buck4_consumer),
+	.consumer_supplies = max77686_buck4_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_buck5_data = {
+	.constraints = {
+		.name		= "VDDQ_CKEM1M2_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck6_data = {
+	.constraints = {
+		.name		= "VDD_INL_1.35V",
+		.min_uV		= 1350000,
+		.max_uV		= 1350000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1350000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck7_data = {
+	.constraints = {
+		.name		= "VDD_INL_2.0V",
+		.min_uV		= 2000000,
+		.max_uV		= 2000000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2000000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck8_data = {
+	.constraints = {
+		.name		= "VDD_BUCK8_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_buck9_data = {
+	.constraints = {
+		.name		= "VDD_BUCK9_1.2V",
+		.min_uV		= 1200000,
+		.max_uV		= 1200000,
+		.always_on	= 1,
+		.apply_uV	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1200000,
+			.mode	= REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo1_data = {
+	.constraints = {
+		.name		= "VDD_ALIVE_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo1_consumer),
+	.consumer_supplies = max77686_ldo1_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo2_data = {
+	.constraints = {
+		.name		= "VDDQ_M1M2_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo3_data = {
+	.constraints = {
+		.name		= "VDDQ_M0_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo3_consumer),
+	.consumer_supplies = max77686_ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo4_data = {
+	.constraints = {
+		.name		= "VDDQ_MMC2_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo4_consumer),
+	.consumer_supplies = max77686_ldo4_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo5_data = {
+	.constraints = {
+		.name		= "VDDQ_MMC13_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo5_consumer),
+	.consumer_supplies = max77686_ldo5_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo6_data = {
+	.constraints = {
+		.name		= "VDD_MPLL_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo7_data = {
+	.constraints = {
+		.name		= "VDD_VPLL_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo8_data = {
+	.constraints = {
+		.name		= "VDD10_HDMI_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo8_consumer),
+	.consumer_supplies = max77686_ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo9_data = {
+	.constraints = {
+		.name		= "VDD_VTCORE_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo10_data = {
+	.constraints = {
+		.name		= "VDDQ_MIPIHSI_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo10_consumer),
+	.consumer_supplies = max77686_ldo10_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo11_data = {
+	.constraints = {
+		.name		= "VDD18_ABB1_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(max77686_ldo11_consumer),
+	.consumer_supplies	= max77686_ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo12_data = {
+	.constraints = {
+		.name		= "VDD33_UOTG_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo13_data = {
+	.constraints = {
+		.name		= "VDDQ_C2C_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo13_consumer),
+	.consumer_supplies = max77686_ldo13_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo14_data = {
+	.constraints = {
+		.name		= "VDD18_ABB2_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(max77686_ldo14_consumer),
+	.consumer_supplies	= max77686_ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo15_data = {
+	.constraints = {
+		.name		= "VDD10_HSIC_1.0V",
+		.min_uV		= 1000000,
+		.max_uV		= 1000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1000000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo16_data = {
+	.constraints = {
+		.name		= "VDD18_HSIC_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo17_data = {
+	.constraints = {
+		.name		= "VDDQ_CAM_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo17_consumer),
+	.consumer_supplies = max77686_ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo18_data = {
+	.constraints = {
+		.name		= "VDD_LDO18_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo18_consumer),
+	.consumer_supplies = max77686_ldo18_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo19_data = {
+	.constraints = {
+		.name		= "VDD_VTCAM_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 0,
+		.always_on	= 0,
+		.boot_on	= 0,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 0,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo19_consumer),
+	.consumer_supplies = max77686_ldo19_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo20_data = {
+	.constraints = {
+		.name		= "VDD_LDO20_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.always_on	= 1,
+		.boot_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 1800000,
+			.enabled = 0,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo21_data = {
+	.constraints = {
+		.name		= "VDD_SDCARD_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 1,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo22_data = {
+	.constraints = {
+		.name		= "VDD_LDO22_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 0,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 0,
+		},
+	},
+};
+
+static struct regulator_init_data __initdata max77686_ldo23_data = {
+	.constraints = {
+		.name		= "VDD_TOUCH_2.8V",
+		.min_uV		= 2800000,
+		.max_uV		= 2800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 2800000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo23_consumer),
+	.consumer_supplies = max77686_ldo23_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo24_data = {
+	.constraints = {
+		.name		= "VDD_TOUCHLED_3.3V",
+		.min_uV		= 3300000,
+		.max_uV		= 3300000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.uV	= 3300000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo24_consumer),
+	.consumer_supplies = max77686_ldo24_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo25_data = {
+	.constraints = {
+		.name		= "VDDQ_LCD_1.8V",
+		.min_uV		= 1800000,
+		.max_uV		= 1800000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem = {
+			.disabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo25_consumer),
+	.consumer_supplies = max77686_ldo25_consumer,
+};
+
+static struct regulator_init_data __initdata max77686_ldo26_data = {
+	.constraints = {
+		.name		= "VDD_MOTOR_3.0V",
+		.min_uV		= 3000000,
+		.max_uV		= 3000000,
+		.apply_uV	= 1,
+		.always_on	= 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+		.state_mem	= {
+			.uV	= 3000000,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(max77686_ldo26_consumer),
+	.consumer_supplies = max77686_ldo26_consumer,
+};
+
+struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = {
+	[MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY},
+	[MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY},
+	[MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY},
+};
+
+static struct max77686_regulator_data max77686_regulators[] = {
+	{ MAX77686_LDO1,	&max77686_ldo1_data },
+	{ MAX77686_LDO2,	&max77686_ldo2_data },
+	{ MAX77686_LDO3,	&max77686_ldo3_data },
+	{ MAX77686_LDO4,	&max77686_ldo4_data },
+	{ MAX77686_LDO5,	&max77686_ldo5_data },
+	{ MAX77686_LDO6,	&max77686_ldo6_data },
+	{ MAX77686_LDO7,	&max77686_ldo7_data },
+	{ MAX77686_LDO8,	&max77686_ldo8_data },
+	{ MAX77686_LDO9,	&max77686_ldo9_data },
+	{ MAX77686_LDO10,	&max77686_ldo10_data },
+	{ MAX77686_LDO11,	&max77686_ldo11_data },
+	{ MAX77686_LDO12,	&max77686_ldo12_data },
+	{ MAX77686_LDO13,	&max77686_ldo13_data },
+	{ MAX77686_LDO14,	&max77686_ldo14_data },
+	{ MAX77686_LDO15,	&max77686_ldo15_data },
+	{ MAX77686_LDO16,	&max77686_ldo16_data },
+	{ MAX77686_LDO17,	&max77686_ldo17_data },
+	{ MAX77686_LDO18,	&max77686_ldo18_data },
+	{ MAX77686_LDO19,	&max77686_ldo19_data },
+	{ MAX77686_LDO20,	&max77686_ldo20_data },
+	{ MAX77686_LDO21,	&max77686_ldo21_data },
+	{ MAX77686_LDO22,	&max77686_ldo22_data },
+	{ MAX77686_LDO23,	&max77686_ldo23_data },
+	{ MAX77686_LDO24,	&max77686_ldo24_data },
+	{ MAX77686_LDO25,	&max77686_ldo25_data },
+	{ MAX77686_LDO26,	&max77686_ldo26_data },
+
+	{ MAX77686_BUCK1,	&max77686_buck1_data },
+	{ MAX77686_BUCK2,	&max77686_buck2_data },
+	{ MAX77686_BUCK3,	&max77686_buck3_data },
+	{ MAX77686_BUCK4,	&max77686_buck4_data },
+	{ MAX77686_BUCK5,	&max77686_buck5_data },
+	{ MAX77686_BUCK6,	&max77686_buck6_data },
+	{ MAX77686_BUCK7,	&max77686_buck7_data },
+	{ MAX77686_BUCK8,	&max77686_buck8_data },
+	{ MAX77686_BUCK9,	&max77686_buck9_data },
+};
+
+static struct max77686_platform_data hkdk4412_max77686_info = {
+	.num_regulators	= ARRAY_SIZE(max77686_regulators),
+	.regulators	= max77686_regulators,
+	.irq_gpio	= 0,
+	.wakeup		= 0,
+
+	.opmode_data	= max77686_opmode_data,
+
+	.buck234_gpio_dvs[0]	= EXYNOS4_GPX2(3),
+	.buck234_gpio_dvs[1]	= EXYNOS4_GPX2(4),
+	.buck234_gpio_dvs[2]	= EXYNOS4_GPX2(5),
+
+	.buck2_voltage[0] = 1300000,	/* 1.3V */
+	.buck2_voltage[1] = 1000000,	/* 1.0V */
+	.buck2_voltage[2] = 950000,	/* 0.95V */
+	.buck2_voltage[3] = 900000,	/* 0.9V */
+	.buck2_voltage[4] = 1000000,	/* 1.0V */
+	.buck2_voltage[5] = 1000000,	/* 1.0V */
+	.buck2_voltage[6] = 950000,	/* 0.95V */
+	.buck2_voltage[7] = 900000,	/* 0.9V */
+
+	.buck3_voltage[0] = 1037500,	/* 1.0375V */
+	.buck3_voltage[1] = 1000000,	/* 1.0V */
+	.buck3_voltage[2] = 950000,	/* 0.95V */
+	.buck3_voltage[3] = 900000,	/* 0.9V */
+	.buck3_voltage[4] = 1000000,	/* 1.0V */
+	.buck3_voltage[5] = 1000000,	/* 1.0V */
+	.buck3_voltage[6] = 950000,	/* 0.95V */
+	.buck3_voltage[7] = 900000,	/* 0.9V */
+
+	.buck4_voltage[0] = 1100000,	/* 1.1V */
+	.buck4_voltage[1] = 1000000,	/* 1.0V */
+	.buck4_voltage[2] = 950000,	/* 0.95V */
+	.buck4_voltage[3] = 900000,	/* 0.9V */
+	.buck4_voltage[4] = 1000000,	/* 1.0V */
+	.buck4_voltage[5] = 1000000,	/* 1.0V */
+	.buck4_voltage[6] = 950000,	/* 0.95V */
+	.buck4_voltage[7] = 900000,	/* 0.9V */
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs0[] __initdata = {
+	{
+		I2C_BOARD_INFO("max77686", (0x12 >> 1)),
+		.platform_data	= &hkdk4412_max77686_info,
+	}
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs1[] __initdata = {
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs3[] __initdata = {
+	/* nothing here yet */
+};
+
+static struct i2c_board_info hkdk4412_i2c_devs7[] __initdata = {
+	/* nothing here yet */
+};
+
+static struct gpio_led hkdk4412_gpio_leds[] = {
+	{
+		.name		= "led1",	/* D5 on ODROID-X */
+		.default_trigger	= "oneshot",
+		.gpio		= EXYNOS4_GPC1(0),
+		.active_low	= 1,
+	},
+	{
+		.name		= "led2",	/* D6 on ODROID-X */
+		.default_trigger	= "heartbeat",
+		.gpio		= EXYNOS4_GPC1(2),
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_led_platform_data hkdk4412_gpio_led_info = {
+	.leds		= hkdk4412_gpio_leds,
+	.num_leds	= ARRAY_SIZE(hkdk4412_gpio_leds),
+};
+
+static struct platform_device hkdk4412_leds_gpio = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &hkdk4412_gpio_led_info,
+	},
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata hkdk4412_ehci_pdata;
+
+static void __init hkdk4412_ehci_init(void)
+{
+	struct s5p_ehci_platdata *pdata = &hkdk4412_ehci_pdata;
+
+	s5p_ehci_set_platdata(pdata);
+}
+
+/* USB OHCI */
+static struct exynos4_ohci_platdata hkdk4412_ohci_pdata;
+
+static void __init hkdk4412_ohci_init(void)
+{
+	struct exynos4_ohci_platdata *pdata = &hkdk4412_ohci_pdata;
+
+	exynos4_ohci_set_platdata(pdata);
+}
+
+/* USB OTG */
+static struct s3c_hsotg_plat hkdk4412_hsotg_pdata;
+
+static struct platform_device *hkdk4412_devices[] __initdata = {
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
+	&s3c_device_i2c0,
+	&s3c_device_i2c1,
+	&s3c_device_i2c3,
+	&s3c_device_i2c7,
+	&s3c_device_rtc,
+	&s3c_device_usb_hsotg,
+	&s3c_device_wdt,
+	&s5p_device_ehci,
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
+	&s5p_device_fimc3,
+	&s5p_device_fimc_md,
+	&s5p_device_mfc,
+	&s5p_device_mfc_l,
+	&s5p_device_mfc_r,
+	&exynos4_device_ohci,
+	&hkdk4412_leds_gpio,
+};
+
+static void __init hkdk4412_map_io(void)
+{
+	clk_xusbxti.rate = 24000000;
+
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(clk_xusbxti.rate);
+	s3c24xx_init_uarts(hkdk4412_uartcfgs, ARRAY_SIZE(hkdk4412_uartcfgs));
+}
+
+static void __init hkdk4412_reserve(void)
+{
+	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init hkdk4412_gpio_init(void)
+{
+	/* Peripheral power enable (P3V3) */
+	gpio_request_one(EXYNOS4_GPA1(1), GPIOF_OUT_INIT_HIGH, "p3v3_en");
+}
+
+static void __init hkdk4412_machine_init(void)
+{
+	hkdk4412_gpio_init();
+
+	s3c_i2c0_set_platdata(NULL);
+	i2c_register_board_info(0, hkdk4412_i2c_devs0,
+				ARRAY_SIZE(hkdk4412_i2c_devs0));
+
+	s3c_i2c1_set_platdata(NULL);
+	i2c_register_board_info(1, hkdk4412_i2c_devs1,
+				ARRAY_SIZE(hkdk4412_i2c_devs1));
+
+	s3c_i2c3_set_platdata(NULL);
+	i2c_register_board_info(3, hkdk4412_i2c_devs3,
+				ARRAY_SIZE(hkdk4412_i2c_devs3));
+
+	s3c_i2c7_set_platdata(NULL);
+	i2c_register_board_info(7, hkdk4412_i2c_devs7,
+				ARRAY_SIZE(hkdk4412_i2c_devs7));
+
+	s3c_sdhci2_set_platdata(&hkdk4412_hsmmc2_pdata);
+	s3c_sdhci3_set_platdata(&hkdk4412_hsmmc3_pdata);
+
+	hkdk4412_ehci_init();
+	hkdk4412_ohci_init();
+	s3c_hsotg_set_platdata(&hkdk4412_hsotg_pdata);
+
+	platform_add_devices(hkdk4412_devices, ARRAY_SIZE(hkdk4412_devices));
+}
+
+MACHINE_START(ODROIDX, "ODROID-X")
+	/* Maintainer: Dongjin Kim <dongjin.kim at agreeyamobiity.net> */
+	.atag_offset	= 0x100,
+	.init_irq	= exynos4_init_irq,
+	.map_io		= hkdk4412_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= hkdk4412_machine_init,
+	.init_late	= exynos_init_late,
+	.timer		= &exynos4_timer,
+	.restart	= exynos4_restart,
+	.reserve	= &hkdk4412_reserve,
+MACHINE_END
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56..e80ed9f 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1206,3 +1206,4 @@ baileys			MACH_BAILEYS		BAILEYS			4169
 familybox		MACH_FAMILYBOX		FAMILYBOX		4170
 ensemble_mx35		MACH_ENSEMBLE_MX35	ENSEMBLE_MX35		4171
 sc_sps_1		MACH_SC_SPS_1		SC_SPS_1		4172
+odroidx			MACH_ODROIDX		ODROIDX			4289
-- 
1.7.9.5



From tobetter at gmail.com  Tue Aug  7 15:04:11 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Wed,  8 Aug 2012 04:04:11 +0900
Subject: [PATCH 1/4] arm/dts: max77686: Add DTS file for max77686 PMIC
Message-ID: <1344366267-18971-1-git-send-email-dongjin.kim@agreeyamobility.net>

Add a dedicated DTS file for max77686 PMIC.
This file is supposed to be included in a board DTS in order to control the
power for certain consumer devices or AP with 9 BUCKs and 26 LDOs

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/max77686.dtsi |  303 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 303 insertions(+)
 create mode 100644 arch/arm/boot/dts/max77686.dtsi

diff --git a/arch/arm/boot/dts/max77686.dtsi b/arch/arm/boot/dts/max77686.dtsi
new file mode 100644
index 0000000..4a46167
--- /dev/null
+++ b/arch/arm/boot/dts/max77686.dtsi
@@ -0,0 +1,303 @@
+/*
+ * arch/arm/boot/dts/max77686.dtsi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	max77686 at 09 {
+		compatible = "maxim,max77686";
+
+		voltage-regulators {
+			buck1 {
+				regulator-compatible = "BUCK1";
+				regulator-name = "VDD_MIF_1.0V";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck2 {
+				regulator-compatible = "BUCK2";
+				regulator-name = "VDD_ARM_1.3V";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck3 {
+				regulator-compatible = "BUCK3";
+				regulator-name = "VDD_INT_1.0V";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck4 {
+				regulator-compatible = "BUCK4";
+				regulator-name = "VDD_G3D_1.0V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+			};
+
+			buck5 {
+				regulator-compatible = "BUCK5";
+				regulator-name = "VDDQ_CKEM1M2_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck6 {
+				regulator-compatible = "BUCK6";
+				regulator-name = "VDD_INL_1.35V";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck7 {
+				regulator-compatible = "BUCK7";
+				regulator-name = "VDD_INL_2.0V";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck8 {
+				regulator-compatible = "BUCK8";
+				regulator-name = "VDD_BUCK8_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck9 {
+				regulator-compatible = "BUCK9";
+				regulator-name = "VDD_BUCK9_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo1 {
+				regulator-compatible = "LDO1";
+				regulator-name = "VDD_ALIVE_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo2 {
+				regulator-compatible = "LDO2";
+				regulator-name = "VDDQ_M1M2_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo3 {
+				regulator-compatible = "LDO3";
+				regulator-name = "VDDQ_M0_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo4 {
+				regulator-compatible = "LDO4";
+				regulator-name = "VDDQ_MMC2_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+			};
+
+			ldo5 {
+				regulator-compatible = "LDO5";
+				regulator-name = "VDDQ_MMC13_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo6 {
+				regulator-compatible = "LDO6";
+				regulator-name = "VDD_MPLL_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo7 {
+				regulator-compatible = "LDO7";
+				regulator-name = "VDD_VPLL_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo8 {
+				regulator-compatible = "LDO8";
+				regulator-name = "VDD10_HDMI_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo9 {
+				regulator-compatible = "LDO9";
+				regulator-name = "VDD_VTCORE_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo10 {
+				regulator-compatible = "LDO10";
+				regulator-name = "VDDQ_MIPIHSI_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo11 {
+				regulator-compatible = "LDO11";
+				regulator-name = "VDD18_ABB1_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo12 {
+				regulator-compatible = "LDO12";
+				regulator-name = "VDD33_UOTG_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			ldo13 {
+				regulator-compatible = "LDO13";
+				regulator-name = "VDDQ_C2C_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo14 {
+				regulator-compatible = "LDO14";
+				regulator-name = "VDD18_ABB2_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo15 {
+				regulator-compatible = "LDO15";
+				regulator-name = "VDD10_HSIC_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo16 {
+				regulator-compatible = "LDO16";
+				regulator-name = "VDD18_HSIC_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo17 {
+				regulator-compatible = "LDO17";
+				regulator-name = "VDDQ_CAM_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo18 {
+				regulator-compatible = "LDO18";
+				regulator-name = "VDD_LDO18_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo19 {
+				regulator-compatible = "LDO19";
+				regulator-name = "VDD_VTCAM_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo20 {
+				regulator-compatible = "LDO20";
+				regulator-name = "VDD_LDO20_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo21 {
+				regulator-compatible = "LDO21";
+				regulator-name = "VDD_SDCARD_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			ldo22 {
+				regulator-compatible = "LDO22";
+				regulator-name = "VDD_LDO22_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+			};
+
+			ldo23 {
+				regulator-compatible = "LDO23";
+				regulator-name = "VDD_TOUCH_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+			};
+
+			ldo24 {
+				regulator-compatible = "LDO24";
+				regulator-name = "VDD_TOUCHLED_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			ldo25 {
+				regulator-compatible = "LDO25";
+				regulator-name = "VDDQ_LCD_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo26 {
+				regulator-compatible = "LDO26";
+				regulator-name = "VDD_MOTOR_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
-- 
1.7.9.5



From tobetter at gmail.com  Tue Aug  7 15:06:24 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Wed,  8 Aug 2012 04:06:24 +0900
Subject: [PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common
 Exynos4
Message-ID: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>

This patch creates a DTS file, exynos4.dtsi, for Exynos4210/4x12 and it
describes common device nodes. SoC specific device nodes are described in
another DTS file derived from this, exynos4210.dtsi and exynos4412.dtsi.

exynos4412.dtsi is added new for Exynos4412 as well as exynos4210 is modified
for Exynos4210 specific device nodes.

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/exynos4.dtsi    |  404 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi |  374 +---------------------------------
 arch/arm/boot/dts/exynos4412.dtsi |  104 ++++++++++
 3 files changed, 510 insertions(+), 372 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4.dtsi
 create mode 100644 arch/arm/boot/dts/exynos4412.dtsi

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 0000000..ffda13e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,404 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos4";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		spi0 = &spi_0;
+		spi1 = &spi_1;
+		spi2 = &spi_2;
+	};
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		cpu-offset = <0x8000>;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x1000>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+	};
+
+	watchdog at 10060000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x10060000 0x100>;
+		interrupts = <0 43 0>;
+	};
+
+	rtc at 10070000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x10070000 0x100>;
+		interrupts = <0 44 0>, <0 45 0>;
+	};
+
+	keypad at 100A0000 {
+		compatible = "samsung,s5pv210-keypad";
+		reg = <0x100A0000 0x100>;
+		interrupts = <0 109 0>;
+	};
+
+	sdhci at 12510000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12510000 0x100>;
+		interrupts = <0 73 0>;
+	};
+
+	sdhci at 12520000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12520000 0x100>;
+		interrupts = <0 74 0>;
+	};
+
+	sdhci at 12530000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12530000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12540000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12540000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	serial at 13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 13820000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13820000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	serial at 13830000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13830000 0x100>;
+		interrupts = <0 55 0>;
+	};
+
+	i2c at 13860000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13860000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 13870000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13870000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 13880000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13880000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 13890000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13890000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 138A0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138A0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 138B0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138B0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c at 138C0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138C0000 0x100>;
+		interrupts = <0 64 0>;
+	};
+
+	i2c at 138D0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138D0000 0x100>;
+		interrupts = <0 65 0>;
+	};
+
+	spi_0: spi at 13920000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13920000 0x100>;
+		interrupts = <0 66 0>;
+		tx-dma-channel = <&pdma0 7>; /* preliminary */
+		rx-dma-channel = <&pdma0 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_1: spi at 13930000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13930000 0x100>;
+		interrupts = <0 67 0>;
+		tx-dma-channel = <&pdma1 7>; /* preliminary */
+		rx-dma-channel = <&pdma1 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_2: spi at 13940000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13940000 0x100>;
+		interrupts = <0 68 0>;
+		tx-dma-channel = <&pdma0 9>; /* preliminary */
+		rx-dma-channel = <&pdma0 8>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 12680000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12680000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		pdma1: pdma at 12690000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12690000 0x1000>;
+			interrupts = <0 36 0>;
+		};
+	};
+
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf2: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf3: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk0: gpio-controller at 11000040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk1: gpio-controller at 11000060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk2: gpio-controller at 11000080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk3: gpio-controller at 110000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl0: gpio-controller at 110000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl1: gpio-controller at 110000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl2: gpio-controller at 11000100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 11000120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 11000140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 11000160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11000180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 110001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 110001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 110001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11000C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11000C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11000C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11000C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..d41d9de 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,249 +19,16 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
-	interrupt-parent = <&gic>;
-
-	aliases {
-		spi0 = &spi_0;
-		spi1 = &spi_1;
-		spi2 = &spi_2;
-	};
 
 	gic:interrupt-controller at 10490000 {
-		compatible = "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		interrupt-controller;
 		cpu-offset = <0x8000>;
-		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
-	};
-
-	combiner:interrupt-controller at 10440000 {
-		compatible = "samsung,exynos4210-combiner";
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0x10440000 0x1000>;
-		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
-	};
-
-	watchdog at 10060000 {
-		compatible = "samsung,s3c2410-wdt";
-		reg = <0x10060000 0x100>;
-		interrupts = <0 43 0>;
-	};
-
-	rtc at 10070000 {
-		compatible = "samsung,s3c6410-rtc";
-		reg = <0x10070000 0x100>;
-		interrupts = <0 44 0>, <0 45 0>;
-	};
-
-	keypad at 100A0000 {
-		compatible = "samsung,s5pv210-keypad";
-		reg = <0x100A0000 0x100>;
-		interrupts = <0 109 0>;
-	};
-
-	sdhci at 12510000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12510000 0x100>;
-		interrupts = <0 73 0>;
-	};
-
-	sdhci at 12520000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12520000 0x100>;
-		interrupts = <0 74 0>;
-	};
-
-	sdhci at 12530000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12530000 0x100>;
-		interrupts = <0 75 0>;
-	};
-
-	sdhci at 12540000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12540000 0x100>;
-		interrupts = <0 76 0>;
-	};
-
-	serial at 13800000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13800000 0x100>;
-		interrupts = <0 52 0>;
-	};
-
-	serial at 13810000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13810000 0x100>;
-		interrupts = <0 53 0>;
-	};
-
-	serial at 13820000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13820000 0x100>;
-		interrupts = <0 54 0>;
-	};
-
-	serial at 13830000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13830000 0x100>;
-		interrupts = <0 55 0>;
-	};
-
-	i2c at 13860000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13860000 0x100>;
-		interrupts = <0 58 0>;
-	};
-
-	i2c at 13870000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13870000 0x100>;
-		interrupts = <0 59 0>;
-	};
-
-	i2c at 13880000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13880000 0x100>;
-		interrupts = <0 60 0>;
-	};
-
-	i2c at 13890000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13890000 0x100>;
-		interrupts = <0 61 0>;
-	};
-
-	i2c at 138A0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138A0000 0x100>;
-		interrupts = <0 62 0>;
-	};
-
-	i2c at 138B0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138B0000 0x100>;
-		interrupts = <0 63 0>;
-	};
-
-	i2c at 138C0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138C0000 0x100>;
-		interrupts = <0 64 0>;
-	};
-
-	i2c at 138D0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138D0000 0x100>;
-		interrupts = <0 65 0>;
-	};
-
-	spi_0: spi at 13920000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13920000 0x100>;
-		interrupts = <0 66 0>;
-		tx-dma-channel = <&pdma0 7>; /* preliminary */
-		rx-dma-channel = <&pdma0 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_1: spi at 13930000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13930000 0x100>;
-		interrupts = <0 67 0>;
-		tx-dma-channel = <&pdma1 7>; /* preliminary */
-		rx-dma-channel = <&pdma1 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_2: spi at 13940000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13940000 0x100>;
-		interrupts = <0 68 0>;
-		tx-dma-channel = <&pdma0 9>; /* preliminary */
-		rx-dma-channel = <&pdma0 8>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	amba {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "arm,amba-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		pdma0: pdma at 12680000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12680000 0x1000>;
-			interrupts = <0 35 0>;
-		};
-
-		pdma1: pdma at 12690000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12690000 0x1000>;
-			interrupts = <0 36 0>;
-		};
 	};
 
 	gpio-controllers {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		gpio-controller;
-		ranges;
-
-		gpa0: gpio-controller at 11400000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400000 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpa1: gpio-controller at 11400020 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400020 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpb: gpio-controller at 11400040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc0: gpio-controller at 11400060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc1: gpio-controller at 11400080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd0: gpio-controller at 114000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd1: gpio-controller at 114000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpe0: gpio-controller at 114000E0 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x114000E0 0x20>;
@@ -292,30 +59,6 @@
 			#gpio-cells = <4>;
 		};
 
-		gpf0: gpio-controller at 11400180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf1: gpio-controller at 114001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf2: gpio-controller at 114001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf3: gpio-controller at 114001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpj0: gpio-controller at 11000000 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x11000000 0x20>;
@@ -327,119 +70,6 @@
 			reg = <0x11000020 0x20>;
 			#gpio-cells = <4>;
 		};
-
-		gpk0: gpio-controller at 11000040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk1: gpio-controller at 11000060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk2: gpio-controller at 11000080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk3: gpio-controller at 110000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl0: gpio-controller at 110000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl1: gpio-controller at 110000E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl2: gpio-controller at 11000100 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000100 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy0: gpio-controller at 11000120 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000120 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy1: gpio-controller at 11000140 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000140 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy2: gpio-controller at 11000160 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000160 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy3: gpio-controller at 11000180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy4: gpio-controller at 110001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy5: gpio-controller at 110001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy6: gpio-controller at 110001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx0: gpio-controller at 11000C00 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C00 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx1: gpio-controller at 11000C20 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C20 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx2: gpio-controller at 11000C40 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C40 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx3: gpio-controller at 11000C60 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C60 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpz: gpio-controller at 03860000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x03860000 0x20>;
-			#gpio-cells = <4>;
-		};
 	};
 };
+
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
new file mode 100644
index 0000000..85ee3f8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -0,0 +1,104 @@
+/*
+ * Samsung's Exynos4412 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "exynos4.dtsi"
+
+/ {
+	compatible = "samsung,exynos4412";
+
+	gic:interrupt-controller at 10490000 {
+		cpu-offset = <0x4000>;
+	};
+
+	gpio-controllers {
+		gpj0: gpio-controller at 11400240 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400240 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpj1: gpio-controller at 11400260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm0: gpio-controller at 11000260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm1: gpio-controller at 11000280 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000280 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm2: gpio-controller at 110002A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm3: gpio-controller at 110002C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm4: gpio-controller at 110002E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv0: gpio-controller at 106E0000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv1: gpio-controller at 106E0020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv2: gpio-controller at 106E0060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv3: gpio-controller at 106E0080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv4: gpio-controller at 106E00C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E00C0 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
-- 
1.7.9.5



From tobetter at gmail.com  Tue Aug  7 15:12:01 2012
From: tobetter at gmail.com (Dongjin Kim)
Date: Wed,  8 Aug 2012 04:12:01 +0900
Subject: [PATCH 3/4] arm/dts: exynos4: Add DTS file for ODROID-X
Message-ID: <1344366725-19153-1-git-send-email-dongjin.kim@agreeyamobility.net>

This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
gpios base.

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 0000000..b0a892b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,148 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+/include/ "max77686.dtsi"
+
+/ {
+	model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
+	compatible = "hardkernel,odroidx", "samsung,exynos4412";
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
+	};
+
+	/* sdhci0 */
+	sdhci at 12510000 {
+		status = "disabled";
+	};
+
+	/* sdhci1 */
+	sdhci at 12520000 {
+		status = "disabled";
+	};
+
+	/* sdhci2 */
+	sdhci at 12530000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd = <&gpk2 2 2 3 3>;
+		gpios = <&gpk2 0 2 0 3>,
+			<&gpk2 1 2 0 3>,
+			<&gpk2 3 2 3 3>,
+			<&gpk2 4 2 3 3>,
+			<&gpk2 5 2 3 3>,
+			<&gpk2 6 2 3 3>;
+	};
+
+	/* sdhci3 */
+	sdhci at 12540000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd	= <&gpk3 2 2 3 3>;
+		gpios = <&gpk3 0 2 0 3>,
+			<&gpk3 1 2 0 3>,
+			<&gpk3 3 2 3 3>,
+			<&gpk3 4 2 3 3>,
+			<&gpk3 5 2 3 3>,
+			<&gpk3 6 2 3 3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1 {
+			label	= "led1";
+			gpios	= <&gpc1 0 1 0x10000 0>;
+			linux,default-trigger	= "oneshot";
+			default-state	= "off";
+		};
+
+		led2 {
+			label	= "led2";
+			gpios	= <&gpc1 2 1 0x10000 0>;
+			linux,default-trigger	= "heartbeat";
+		};
+	};
+
+	i2c at 13860000 {	/* i2c0 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpd1 0 2 0 0>,
+			<&gpd1 1 2 0 0>;
+		pmic at 9 {
+			compatible = "maxim,max77686";
+			reg = <9>;
+		};
+	};
+
+	i2c at 13870000 {	/* i2c1 */
+		status = "disabled";
+		gpios = <&gpd1 2 2 0 0>,
+			<&gpd1 3 2 0 0>;
+	};
+
+	i2c at 13880000 {	/* i2c2 */
+		status = "disabled";
+		gpios = <&gpa0 6 2 0 0>,
+			<&gpa0 7 2 0 0>;
+	};
+
+	i2c at 13890000 {	/* i2c3 */
+		status = "disabled";
+		gpios = <&gpa1 2 2 0 0>,
+			<&gpa1 3 2 0 0>;
+	};
+
+	i2c at 138A0000 {	/* i2c4 */
+		status = "disabled";
+	};
+
+	i2c at 138B0000 {	/* i2c5 */
+		status = "disabled";
+	};
+
+	i2c at 138C0000 {	/* i2c6 */
+		status = "disabled";
+	};
+
+	i2c at 138D0000 {	/* i2c7 */
+		status = "disabled";
+	};
+
+	keypad at 100A0000 {
+		status = "disabled";
+	};
+
+	spi_0: spi at 13920000 {
+		status = "disabled";
+	};
+
+	spi_1: spi at 13930000 {
+		status = "disabled";
+	};
+
+	spi_2: spi at 13940000 {
+		status = "disabled";
+	};
+};
-- 
1.7.9.5



From arnd at arndb.de  Tue Aug  7 11:25:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 15:25:14 +0000
Subject: [PATCH V4 1/2] include/video: move fimd register headers from
 platform to include/video
In-Reply-To: <201208071428.56290.arnd@arndb.de>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
 <1344342872-7904-2-git-send-email-l.krishna@samsung.com>
 <201208071428.56290.arnd@arndb.de>
Message-ID: <201208071525.15032.arnd@arndb.de>

On Tuesday 07 August 2012, Arnd Bergmann wrote:
> On Tuesday 07 August 2012, Leela Krishna Amudala wrote:
> > 
> > This patch moves the contents from regs-fb-v4.h and regs-fb.h to
> > include/video/samsung_fimd.h. Also updates the header inclusion in
> > machine files and driver files accordingly.
> > 
> > Signed-off-by: Leela Krishna Amudala <l.krishna at samsung.com>
> 
> You are missing an explanation here about why the file is moved.
> It does seem like a good idea but please say why you do this.
> 
> More importantly, I don't understany why you move regs-fb-v4.h
> but not regs-fb.h, which is included by the former.

Nevermind, I should have read your text better.

	Arnd



From arnd at arndb.de  Tue Aug  7 15:15:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 19:15:25 +0000
Subject: [PATCH 1/6] ARM: mxs: tx28: reset fec phy for device tree boot
In-Reply-To: <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
 <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <201208071915.26932.arnd@arndb.de>

On Monday 06 August 2012, Shawn Guo wrote:
> +static void __init tx28_post_init(void)
> +{
> +       struct device_node *np;
> +       struct platform_device *pdev;
> +       struct pinctrl *pctl;
> +       int ret;
> +
> +       enable_clk_enet_out();
> +
> +       np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
> +       pdev = of_find_device_by_node(np);
> +       if (!pdev) {
> +               pr_err("%s: failed to find fec device\n", __func__);
> +               return;
> +       }
> +
> +       pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
> +       if (IS_ERR(pctl)) {
> +               pr_err("%s: failed to get pinctrl state\n", __func__);
> +               return;
> +       }
> +
> +       ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
> +       if (ret) {
> +               pr_err("%s: failed to request gpios: %d\n", __func__, ret);
> +               return;
> +       }
> +
> +       /* Power up fec phy */
> +       gpio_set_value(TX28_FEC_PHY_POWER, 1);
> +       mdelay(26); /* 25ms according to data sheet */

26 ms is a long time for a delay. I think you should use msleep here.

	Arnd


From arnd at arndb.de  Tue Aug  7 15:27:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 19:27:00 +0000
Subject: [PATCH 0/6] ARM: mxs: remove board files
In-Reply-To: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <201208071927.01071.arnd@arndb.de>

On Monday 06 August 2012, Shawn Guo wrote:
> 
> The first two patches hack out the board oddness in DT boot for TX28
> and MX28EVK, so that they do not block the whole progress of coverting
> mxs platform over to DT.
> 
> The rest of the series removes board files and the codes only used in
> non-DT boot, and make mxs a DT-only platform.

So it has come to this ;-)

Great job Shawn and everyone else who was involved in this!

Acked-by: Arnd Bergmann <arnd at arndb.de>

	Arnd


From sebastian.hesselbarth at gmail.com  Tue Aug  7 15:32:34 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 07 Aug 2012 21:32:34 +0200
Subject: [PATCH 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <20120807165350.GG18957@n2100.arm.linux.org.uk>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <201208061402.22815.arnd@arndb.de>
 <CABJ1b_S6jRW9P7ygs7LPztbx1zW-u=gD1kk0UYbgBrHdvsaOeA@mail.gmail.com>
 <20120807165350.GG18957@n2100.arm.linux.org.uk>
Message-ID: <50216D52.3030402@gmail.com>

On 08/07/2012 06:53 PM, Russell King - ARM Linux wrote:
> I've recently pushed a fix into mainline (and stable) for VFP support
> with Thumb instructions.  I noticed that the Cubox kernel had a different
> fix, this "different" fix will need to be removed when Cubox folk update
> to the next kernel from mainline.

Russell,

I read about that fix but honestly, that is way to deep into ARM
architecture for me. All I realized while having my Cubox is that the
supplied kernel tree is very messy and on Debian wheezy/armhf almost
all applications started over ssh -X fail with segfault. I was hoping
that bringing the cubox into mainline kernel tree will help here -
and luckily the (hacking) community is growing!

> Video support, not great.  The supplied Ubuntu Lucid stuff install
> (including the latest dev kernel from the solid-run folk) doesn't work
> with any of the tree HDMI devices I've tried it with:

HDMI is another topic that I want to work on as soon as the main SoC
stuff is ported over to mainline. HDMI output actually is done by some
nxp HDMI transmitter that translates the rgb 888 video from lcd controller
on dove. AFAIR the HDMI transmitter code is "open", i.e. free to clean up
and port. I haven't looked closely into lcd yet but on Cubox the lcd pixclk
comes from an external clk chip (si5351a) that I have a quite ready driver
for. The existing driver does a table based setup of the plls and does not
hit 148.5 MHz precisely. The driver I wrote is based on an AN from SiLabs
and is also already based on common clk framework.

> . A LCD PC monitor with HDMI input.  If the monitor is disconnected, the
>    Cubox booted, and the monitor connected, you get a picture, but you
>    lose the top, left, bottom and right of the display off the side of the
>    monitor.  No amount of adjusting on the monitor fixes this.

There have been many reports of people no being able to get proper resolutions
with the original kernel setup. I know there are people working on gfx support
and xbmc. Maybe you hit the solid-run.com forums and have a look there.

> What is obvious is that there is no HDMI hotplug support and reconfiguring
> of the display.  So, I've been investigating the Linux DRM/DRI support -
> both the kernel and X11 side, and I have something that is getting close
> to being ready.  Last night I finally disabled the kernel dovefb driver,
> and have X11 using solely my new DRM driver.

Great, keep me posted and I ll be happy to test it.

> However, this won't be using the on-chip mpeg decoding (yet).  CPU
> usage sits at around 30% while vlc playback is running.

The bad thing with GLES and video decoding is that it all relies on
some dirty closed source user space libraries. But again, as I am not
that familiar with gfx and decoding drivers, I didn't look into that.

Sebastian


From broonie at opensource.wolfsonmicro.com  Tue Aug  7 15:34:14 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 7 Aug 2012 20:34:14 +0100
Subject: [PATCH 1/4] arm/dts: max77686: Add DTS file for max77686 PMIC
In-Reply-To: <1344366267-18971-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344366267-18971-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <20120807193413.GE14711@sirena.org.uk>

On Wed, Aug 08, 2012 at 04:04:11AM +0900, Dongjin Kim wrote:

> +			buck1 {
> +				regulator-compatible = "BUCK1";
> +				regulator-name = "VDD_MIF_1.0V";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1050000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};

These settings for the regulators are clearly specific to the board
rather than the device so should be in the board file.


From arnd at arndb.de  Tue Aug  7 15:38:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 19:38:26 +0000
Subject: [PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common
 Exynos4
In-Reply-To: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <201208071938.26507.arnd@arndb.de>

On Tuesday 07 August 2012, Dongjin Kim wrote:
> 
> This patch creates a DTS file, exynos4.dtsi, for Exynos4210/4x12 and it
> describes common device nodes. SoC specific device nodes are described in
> another DTS file derived from this, exynos4210.dtsi and exynos4412.dtsi.
> 
> exynos4412.dtsi is added new for Exynos4412 as well as exynos4210 is modified
> for Exynos4210 specific device nodes.
> 
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4.dtsi    |  404 +++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi |  374 +---------------------------------
>  arch/arm/boot/dts/exynos4412.dtsi |  104 ++++++++++
>  3 files changed, 510 insertions(+), 372 deletions(-)

Looks good in principle. I would hope that "git format-patch -M" can detect this
mostly-moved filed. Did you use that?

	Arnd


From Dongjin.Kim at agreeyamobility.net  Tue Aug  7 15:50:11 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Tue, 7 Aug 2012 19:50:11 +0000
Subject: =?ks_c_5601-1987?B?yLi9xTogW1BBVENIIDEvNF0gYXJtL2R0czogbWF4Nzc2ODY6IEFk?=
 =?ks_c_5601-1987?Q?d_DTS_file_for_max77686_PMIC?=
In-Reply-To: <20120807193413.GE14711@sirena.org.uk>
References: <1344366267-18971-1-git-send-email-dongjin.kim@agreeyamobility.net>,
 <20120807193413.GE14711@sirena.org.uk>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F4372BC@SN2PRD0510MB370.namprd05.prod.outlook.com>

Hello,

Are you meaning VDD_MIF_1.0V, for example, would be replaced with another common name for other boards and my board file, exynos4412-odroidx.dts, describe the name again if necessary? Like below?

max77686.dtsi:
    buck1 {
         regulator-compatible = "BUCK1";
         regulator-name = "VDD_BUCK1_1.0V";
         regulator-min-microvolt = <800000>;
         regulator-max-microvolt = <1050000>;
         regulator-always-on;
         regulator-boot-on;
    };

my board's DTS file:
    buck1 {
        regulator-name = "VDD_MIF_1.0V";
    }

Thank you in advance.
Dongjin.
________________________________________
?? ??: Mark Brown [broonie at opensource.wolfsonmicro.com]
?? ??: 2012? 8? 8? ??? ?? 4:34
?? ??: Dongjin Kim
??: Russell King; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Dongjin Kim
??: Re: [PATCH 1/4] arm/dts: max77686: Add DTS file for max77686 PMIC

On Wed, Aug 08, 2012 at 04:04:11AM +0900, Dongjin Kim wrote:

> +                     buck1 {
> +                             regulator-compatible = "BUCK1";
> +                             regulator-name = "VDD_MIF_1.0V";
> +                             regulator-min-microvolt = <800000>;
> +                             regulator-max-microvolt = <1050000>;
> +                             regulator-always-on;
> +                             regulator-boot-on;
> +                     };

These settings for the regulators are clearly specific to the board
rather than the device so should be in the board file.

From Dongjin.Kim at agreeyamobility.net  Tue Aug  7 15:57:33 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Tue, 7 Aug 2012 19:57:33 +0000
Subject: =?ks_c_5601-1987?B?yLi9xTogW1BBVENIIDIvNF0gYXJtL2R0czogZXh5bm9zNDogQWRk?=
 =?ks_c_5601-1987?Q?_DTS_files_derived_from_common_Exynos4?=
In-Reply-To: <201208071938.26507.arnd@arndb.de>
References: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>,
 <201208071938.26507.arnd@arndb.de>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F4372EB@SN2PRD0510MB370.namprd05.prod.outlook.com>

Hi,

I didn't use -M and I couldn't see any difference with the it.
Did I make something wrong on that patch?

Thank you in advance.
Dongjin.
________________________________________
?? ??: Arnd Bergmann [arnd at arndb.de]
?? ??: 2012? 8? 8? ??? ?? 4:38
?? ??: Dongjin Kim
??: Dongjin Kim; Russell King; Thomas Abraham; Kukjin Kim; Grant Likely; linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
??: Re: [PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common Exynos4

On Tuesday 07 August 2012, Dongjin Kim wrote:
>
> This patch creates a DTS file, exynos4.dtsi, for Exynos4210/4x12 and it
> describes common device nodes. SoC specific device nodes are described in
> another DTS file derived from this, exynos4210.dtsi and exynos4412.dtsi.
>
> exynos4412.dtsi is added new for Exynos4412 as well as exynos4210 is modified
> for Exynos4210 specific device nodes.
>
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4.dtsi    |  404 +++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi |  374 +---------------------------------
>  arch/arm/boot/dts/exynos4412.dtsi |  104 ++++++++++
>  3 files changed, 510 insertions(+), 372 deletions(-)

Looks good in principle. I would hope that "git format-patch -M" can detect this
mostly-moved filed. Did you use that?

        Arnd


From arnd at arndb.de  Tue Aug  7 16:25:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 20:25:22 +0000
Subject: [PATCH v3 3/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <50213ACB.6040301@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <201208071456.41412.arnd@arndb.de> <50213ACB.6040301@codethink.co.uk>
Message-ID: <201208072025.22871.arnd@arndb.de>

On Tuesday 07 August 2012, Ian Molton wrote:
> > I think it documents some of the same thing,
> 
> Not really. It documents some godawful hack that recycled the platform
> device -based driver and provided a DT binding for it, just for PPC.
> 
> I cant even find anything that implements code for whatever
> "marvell,mv64360-mdio" might be. I'm sure it might exist somewhere.

The code dates back to when we had separate buses for platform devices
and of devices, and then it was decided not to add support for both
bus types to each of the marvell drivers. In hindsight it would have
been better to do that, but that was impossible to tell back then.

> > We might also want to move some of the
> > code from arch/powerpc/sysdev/mv64x60_dev.c to live in the same place
> > as the device driver.
> 
> I hope not. I don't really want to touch that stuff at all. If it works
> the way it
> is, then it can stay that way. If the PPC folk want to send patches to
> add the
> properties they use to the driver, then they can do. I'll send an email
> their
> way and see if they want to join in.
> 
> From my perspective, the next thing that needs to happen to the driver is
> for it to be broken up into ethernet and mdio drivers, so that we can
> get rid
> of all this shared_smi craziness... But that's for another patch series.

Adding devicetree-discuss and linuxppc-dev, as well as Dale Farnsworth,
who initially added the bindings for mv643xx.

I would hope that at least some of the properties that are used on
powerpc can be reused in the same way for other architectures.
The method to find the phy address on powerpc does indeed make
more sense than the "port_number" property you suggested, and the
phandle for the phy node is usually called "phy" not "mdio".

I'm not sure if the ethernet-group is required on ARM as well, but
it does sound a lot like what you actually want instead of the
shared_smi property.

	Arnd


From swarren at wwwdotorg.org  Tue Aug  7 16:26:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 07 Aug 2012 14:26:18 -0600
Subject: [PATCH] pinctrl/nomadik: add ASIC DB8450 pinctrl driver
In-Reply-To: <1344341538-32223-1-git-send-email-linus.walleij@stericsson.com>
References: <1344341538-32223-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <502179EA.30301@wwwdotorg.org>

On 08/07/2012 06:12 AM, Linus Walleij wrote:
> From: Patrice Chotard <patrice.chotard at stericsson.com>
> 
> This implements a subdriver for the DB8540 ASIC for the
> Nomadik pin controller.

> diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c

> @@ -1722,6 +1722,8 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
>  	/* Poke in other ASIC variants here */
>  	if (version == PINCTRL_NMK_DB8500)
>  		nmk_pinctrl_db8500_init(&npct->soc);
> +	if (platid->driver_data == PINCTRL_NMK_DB8540)
> +		nmk_pinctrl_db8540_init(&npct->soc);

I'm surprised one of those checks "version" and the other
"platid->driver_data".

Aside from that, this looks fine.


From arnd at arndb.de  Tue Aug  7 16:29:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 7 Aug 2012 20:29:08 +0000
Subject: =?euc-kr?q?=C8=B8=BD=C5=3A_=5BPATCH_2/4=5D_arm/dts=3A_exynos4=3A_Add_DTS?=
 =?euc-kr?q?_files_derived_from_common?= Exynos4
In-Reply-To: <A6A3B7488C419F488E5B13FFD03C08AD2F4372EB@SN2PRD0510MB370.namprd05.prod.outlook.com>
References: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <201208071938.26507.arnd@arndb.de>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4372EB@SN2PRD0510MB370.namprd05.prod.outlook.com>
Message-ID: <201208072029.08693.arnd@arndb.de>

On Tuesday 07 August 2012, Dongjin Kim wrote:
> Hi,
> 
> I didn't use -M and I couldn't see any difference with the it.
> Did I make something wrong on that patch?

No, I think it's just git being less smart about file moves than I was hoping
for. It might do the right thing if you do the patch in two steps:

1. rename exynos4210.dtsi to exynos4.dtsi and add a one-line exynos4210.dtsi
file that just includes exynos4.dtsi.

2. do all the changes for moving contents back from exynos4.dtsi into
exynos4210.dtsi and exynos4412.dtsi.

Not sure if it's worth it though. Your version is probably good enough
if there are no tools to do a better job automatically.

	Arnd


From khilman at ti.com  Tue Aug  7 16:41:47 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue,  7 Aug 2012 13:41:47 -0700
Subject: [PATCH] Revert "ARM: OMAP3: PM: call pre/post transition per
 powerdomain"
Message-ID: <1344372107-17786-1-git-send-email-khilman@ti.com>

This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.

Converstion to per-pwrdm per/post transition calls was a bit
premature.  Only tracking MPU, PER & CORE in the idle path means we
lose the accounting for all the other powerdomains which may also
transition in idle.  On OMAP3, due to autodeps, several powerdomains
transition along with MPU (e.g. DSS, USBHOST), and the accounting for
these was lost with this patch.

This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
use-counting seires is merged since then we can properly do accounting
without relying on a call in the idle path.

Cc: Jean Pihet <jean.pihet at newoldbits.com>
Cc: Tero Kristo <t-kristo at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Reported-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..05bd8f0 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -272,21 +272,16 @@ void omap_sram_idle(void)
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 
-	if (mpu_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(mpu_pwrdm);
-		pwrdm_pre_transition(neon_pwrdm);
-	}
+	pwrdm_pre_transition(NULL);
 
 	/* PER */
 	if (per_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(per_pwrdm);
 		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 		omap2_gpio_prepare_for_idle(per_going_off);
 	}
 
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(core_pwrdm);
 		if (core_next_state == PWRDM_POWER_OFF) {
 			omap3_core_save_context();
 			omap3_cm_save_context();
@@ -339,20 +334,14 @@ void omap_sram_idle(void)
 			omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 					       OMAP3430_GR_MOD,
 					       OMAP3_PRM_VOLTCTRL_OFFSET);
-		pwrdm_post_transition(core_pwrdm);
 	}
 	omap3_intc_resume_idle();
 
+	pwrdm_post_transition(NULL);
+
 	/* PER */
-	if (per_next_state < PWRDM_POWER_ON) {
+	if (per_next_state < PWRDM_POWER_ON)
 		omap2_gpio_resume_after_idle();
-		pwrdm_post_transition(per_pwrdm);
-	}
-
-	if (mpu_next_state < PWRDM_POWER_ON) {
-		pwrdm_post_transition(mpu_pwrdm);
-		pwrdm_post_transition(neon_pwrdm);
-	}
 }
 
 static void omap3_pm_idle(void)
-- 
1.7.9.2



From khilman at ti.com  Tue Aug  7 16:48:02 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 13:48:02 -0700
Subject: DSS and USBHOST powerdomains not entering low-power states on
 37xx EVM
In-Reply-To: <alpine.DEB.2.00.1208070401530.21945@utopia.booyaka.com> (Paul
 Walmsley's message of "Tue, 7 Aug 2012 04:05:33 -0600 (MDT)")
References: <alpine.DEB.2.00.1208031355450.28888@utopia.booyaka.com>
 <877gtb6723.fsf@ti.com>
 <alpine.DEB.2.00.1208070401530.21945@utopia.booyaka.com>
Message-ID: <87628u2zul.fsf@ti.com>

Paul Walmsley <paul at pwsan.com> writes:

> Hi Kevin,
>
> On Mon, 6 Aug 2012, Kevin Hilman wrote:
>
>> Is this only happening on this 37xx platform?    Just curious, because
>> it seems to be a problem on any OMAP3xxx SoC.
>
> So far I've only run the baseline tests on 37xx, so wanted to state only 
> what was observed here.
>
>> ...it must be the usecounts that are not being updated.  This seems to
>> be a side effect of the pre/post transition optimization I did.  A quick
>> hack seems to indicate that that's indeed the case[1].  By default,
>> omap_sram_idle() is now only calling the pre/post callbacks for MPU,
>> NEON, PER, and CORE, and only if those domains are transitioning, so any
>> other domains not explicitly managed by the idle path have lots their
>> usecounting.  Oops.
>> 
>> I guess Tero's usecounting series should fix this up.
>
> Thanks for the diagnosis.  Care to put together a patch to fix this for 
> v3.6-rc?  

Done.

http://marc.info/?l=linux-omap&m=134437239010649&w=2

Kevin


From paul at pwsan.com  Tue Aug  7 17:26:00 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 7 Aug 2012 15:26:00 -0600 (MDT)
Subject: [PATCH 1/3] ARM: OMAP: omap_device: keep track of driver bound
 status
In-Reply-To: <1341961324-19657-1-git-send-email-khilman@ti.com>
References: <1341961324-19657-1-git-send-email-khilman@ti.com>
Message-ID: <alpine.DEB.2.00.1208071518370.28250@utopia.booyaka.com>

Hi Kevin

a couple of minor comments

On Tue, 10 Jul 2012, Kevin Hilman wrote:

> Use the bus notifier to keep track of driver bound status by adding a
> new internal field to struct omap_device: _driver_staus.

"_driver_status"

> This will be useful for follow-up patches which need to know whether
> or not a driver is bound in order to make intelligent omap_device
> enable/idle decisions.
> 
> Cc: Paul Walmsley <paul at pwsan.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
>  arch/arm/plat-omap/include/plat/omap_device.h |    2 ++
>  arch/arm/plat-omap/omap_device.c              |   14 +++++++++-----
>  2 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
> index 4327b2c..e0486cb 100644
> --- a/arch/arm/plat-omap/include/plat/omap_device.h
> +++ b/arch/arm/plat-omap/include/plat/omap_device.h
> @@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
>   * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
>   * @_state: one of OMAP_DEVICE_STATE_* (see above)
>   * @flags: device flags
> + * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
>   *
>   * Integrates omap_hwmod data into Linux platform_device.
>   *
> @@ -78,6 +79,7 @@ struct omap_device {
>  	u8				hwmods_cnt;
>  	u8				_state;
>  	u8                              flags;
> +	u8				_driver_status;
>  };
>  
>  /* Device driver interface (call via platform_data fn ptrs) */
> diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
> index c490240..1d1b5ff 100644
> --- a/arch/arm/plat-omap/omap_device.c
> +++ b/arch/arm/plat-omap/omap_device.c
> @@ -385,17 +385,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
>  				      unsigned long event, void *dev)
>  {
>  	struct platform_device *pdev = to_platform_device(dev);
> +	struct omap_device *od;
>  
>  	switch (event) {
> -	case BUS_NOTIFY_ADD_DEVICE:
> -		if (pdev->dev.of_node)
> -			omap_device_build_from_dt(pdev);
> -		break;
> -
>  	case BUS_NOTIFY_DEL_DEVICE:
>  		if (pdev->archdata.od)
>  			omap_device_delete(pdev->archdata.od);
>  		break;
> +	case BUS_NOTIFY_ADD_DEVICE:
> +		if (pdev->dev.of_node)
> +			omap_device_build_from_dt(pdev);
> +		/* fall through */
> +	default:
> +		od = to_omap_device(pdev);
> +		if (od)
> +			od->_driver_status = event;

_driver_status is a u8, but event is an unsigned long.  Might be worth 
adding a WARN() to complain if event is greater than (2^8)-1.

>  	}
>  
>  	return NOTIFY_DONE;
> -- 
> 1.7.9.2
> 


- Paul


From matt at genesi-usa.com  Tue Aug  7 17:44:23 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue,  7 Aug 2012 16:44:23 -0500
Subject: [PATCH] ARM: print an early warning if the ATAG_CORE/OF_DT_MAGIC vet
 did not pass
Message-ID: <1344375863-29947-1-git-send-email-matt@genesi-usa.com>

When booting and passing either corrupted or missing device trees or ATAGs,
the __vet_atags function in kernel/head-common.S will set r2 to 0, thus
causing what might be seen as strange behavior.

What happens is setup_machine_fdt is passed __atags_pointer which is NULL
in the above situation, and it will immediately exit with NULL return
value for the machine_desc. On NULL machine_desc, the implication is that
it was not a device tree, and it falls back to setup_machine_tags. This
function will also return NULL, and the list of supported boards will be
printed out. Only much, much later in the kernel is any message reporting
lack of ATAG_CORE or any other indicator present since they all rely on
there being a valid pointer to get to them.

The following situations where this may happen are suggested:

1) Modification of the device tree blob is performed in the bootloader,
and the tree is being corrupted for some reason.
2) Something is overwriting the device tree magic (kernel decompression,
perhaps) which is possibly more common.
3) Something is overwriting the ATAG_CORE magic (as above)
4) DTB address passed to bootloader is invalid
5) Bootloader actually does boot setting r2 to 0 which either means it
is ridiculously old or horrifically broken.

Several reads of Documentation/arm/Booting lead me to believe that passing
tags in r2 is OPTIONAL, HIGHLY RECOMMENDED for old bootloaders, and
MANDATORY for new bootloaders. The kernel can't tell which is in use, so 0
might actually be valid. However, later it says that a bootloader must
(lowercase) set r2 to "physical address of tagged list in system RAM, or
physical address of device tree block (dtb) in system RAM." So it is not
possible to define a behavior or print a definitive warning, and since we
cannot fix these problems in the kernel we can at least provide more
information about their occurrence at runtime rather than getting to the point
where it seems something even more strange has happened. The pointer is lost
at this point, though, so all we can do is report the event.

Therefore, print a warning at the earliest opportunity to catch the r2=0
case and reduce frustration with developers attempting to port to device
tree or port new bootloaders, hopefully without worrying people with old
bootloaders complying with the existing documentation.

Of course since this is very early in boot, DEBUG_LL needs to be enabled
and a valid UART for the booting board needs to be configured for it to
show any result, but this is true of all the above warnings anyway,
otherwise all you get is Starting Kernel.... and a blinking terminal prompt.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
Tested-by: Steev Klimaszewski <steev at genesi-usa.com>
---
 arch/arm/kernel/setup.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcec..f788d44 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -942,6 +942,18 @@ void __init setup_arch(char **cmdline_p)
 	struct machine_desc *mdesc;
 
 	setup_processor();
+
+	if (__atags_pointer == 0L) {
+		early_print(
+			"Warning: ATAG_CORE/OF_DT_MAGIC pass failed or __atags_pointer NULL\n"
+			" Either r2 was NULL or __vet_atags set r2 to NULL on boot. This can be because\n"
+			" the bootloader is broken, the ATAGs or Device Tree have been overwritten by\n"
+			" other data during the boot process, the wrong address was supplied for the\n"
+			" Device Tree blob, or NULL was explicitly passed for some reason. Please check\n"
+			" into the situation as it is not usual to be able to boot a board with no ATAGs\n"
+			" or Device Tree.\n");
+	}
+
 	mdesc = setup_machine_fdt(__atags_pointer);
 	if (!mdesc)
 		mdesc = setup_machine_tags(machine_arch_type);
-- 
1.7.9.5



From matt at genesi-usa.com  Tue Aug  7 17:46:18 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue,  7 Aug 2012 16:46:18 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device tree
Message-ID: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>

This device tree only supports the final retail board ("TO3").

It is currently feature equivalent to the MX51 Babbage device tree. The
following features have been tested and work as well as can be expected:

* Serial port
* SD card support
* I2C bus
* SGTL5000 audio support via the internal speaker
* SDMA support (via audio)
* SPI bus
* NOR flash (at 25MHz bus speed)
* MC13892 PMIC Regulator and Realtime clock functions

Since the board requires some extra work on the PMIC to power off, the system
will instead just halt, however reboot works. Other missing features are due
to a lack of drivers or device tree bindings currently.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
Signed-off-by: Steev Klimaszewski <steev at genesi-usa.com>
---
 arch/arm/boot/dts/imx51-efikamx.dts |  247 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/Makefile.boot     |    2 +-
 2 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/imx51-efikamx.dts

diff --git a/arch/arm/boot/dts/imx51-efikamx.dts b/arch/arm/boot/dts/imx51-efikamx.dts
new file mode 100644
index 0000000..dd14f77
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-efikamx.dts
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ * Copyright 2012 Genesi USA, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx51.dtsi"
+
+/ {
+	model = "Genesi Efika MX (Smarttop)";
+	compatible = "genesi,imx51-efikamx", "fsl,imx51";
+
+	memory {
+		reg = <0x90000000 0x20000000>;
+	};
+
+	soc {
+		aips at 70000000 {
+			spba at 70000000 {
+				esdhc at 70004000 {
+					cd-gpios = <&gpio1 0 0>;
+					wp-gpios = <&gpio1 1 0>;
+					status = "okay";
+				};
+
+				ssi2: ssi at 70014000 {
+				    fsl,mode = "i2s-slave";
+				    status = "okay";
+				};
+
+				ecspi at 70010000 {
+					fsl,spi-num-chipselects = <2>;
+					cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
+					status = "okay";
+
+					pmic: mc13892 at 0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						compatible = "fsl,mc13892";
+						spi-max-frequency = <6000000>;
+						reg = <0>;
+						interrupt-parent = <&gpio1>;
+						interrupts = <6 0x4>;
+						fsl,mc13xxx-uses-rtc;
+
+						regulators {
+							sw1_reg: sw1 {
+								regulator-min-microvolt = <600000>;
+								regulator-max-microvolt = <1375000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							sw2_reg: sw2 {
+								regulator-min-microvolt = <900000>;
+								regulator-max-microvolt = <1850000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							sw3_reg: sw3 {
+								regulator-min-microvolt = <1100000>;
+								regulator-max-microvolt = <1850000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							sw4_reg: sw4 {
+								regulator-min-microvolt = <1100000>;
+								regulator-max-microvolt = <1850000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							vpll_reg: vpll {
+								regulator-min-microvolt = <1050000>;
+								regulator-max-microvolt = <1800000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							vdig_reg: vdig {
+								regulator-min-microvolt = <1650000>;
+								regulator-max-microvolt = <1650000>;
+								regulator-boot-on;
+							};
+
+							vsd_reg: vsd {
+								regulator-min-microvolt = <3150000>;
+								regulator-max-microvolt = <3150000>;
+							};
+
+							vusb2_reg: vusb2 {
+								regulator-min-microvolt = <2400000>;
+								regulator-max-microvolt = <2775000>;
+								regulator-boot-on;
+								regulator-always-on;
+							};
+
+							vvideo_reg: vvideo {
+								regulator-min-microvolt = <2775000>;
+								regulator-max-microvolt = <2775000>;
+								regulator-boot-on;
+							};
+
+							vaudio_reg: vaudio {
+								regulator-min-microvolt = <2300000>;
+								regulator-max-microvolt = <3000000>;
+							};
+
+							vcam_reg: vcam {
+								regulator-min-microvolt = <2500000>;
+								regulator-max-microvolt = <3000000>;
+							};
+
+							vgen1_reg: vgen1 {
+								regulator-min-microvolt = <1200000>;
+								regulator-max-microvolt = <3150000>;
+							};
+
+							vgen2_reg: vgen2 {
+								regulator-min-microvolt = <3150000>;
+								regulator-max-microvolt = <3150000>;
+								regulator-always-on;
+							};
+
+							vgen3_reg: vgen3 {
+								regulator-min-microvolt = <1800000>;
+								regulator-max-microvolt = <2900000>;
+								regulator-always-on;
+							};
+						};
+					};
+
+					flash: sst25vf032b at 1 {
+						#address-cells = <1>;
+						#size-cells = <1>;
+						compatible = "sst,sst25vf032b";
+						spi-max-frequency = <25000000>;
+						reg = <1>;
+
+						partition at 0 {
+							label = "firmware";
+							reg = <0x0 0x200000>;
+						};
+
+						partition at 200000 {
+							label = "user";
+							reg = <0x200000 0x200000>;
+						};
+					};
+				};
+			};
+
+			wdog at 73f98000 {
+				status = "okay";
+			};
+
+			iomuxc at 73fa8000 {
+				compatible = "fsl,imx51-iomuxc";
+				reg = <0x73fa8000 0x4000>;
+			};
+
+			uart1: serial at 73fbc000 {
+				fsl,uart-has-rtscts;
+				status = "okay";
+			};
+
+		};
+
+		aips at 80000000 {
+			sdma at 83fb0000 {
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
+			};
+
+			i2c at 83fc4000 {
+				status = "okay";
+
+				codec: sgtl5000 at 0a {
+					compatible = "fsl,sgtl5000";
+					reg = <0x0a>;
+					clock-frequency = <12288000>;
+					VDDA-supply = <&vdig_reg>;
+					VDDIO-supply = <&vvideo_reg>;
+				};
+			};
+
+			audmux at 83fd0000 {
+				status = "okay";
+			};
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power Button";
+			gpios = <&gpio2 31 0>;
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		red {
+			label = "red";
+			gpios = <&gpio3 13>;
+			linux,default-trigger = "ide-disk";
+		};
+
+		green {
+			label = "green";
+			gpios = <&gpio3 14>;
+			linux,default-trigger = "default-on";
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&gpio3 15>;
+			linux,default-trigger = "mmc0";
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "efikamx-sgtl5000";
+		ssi-controller = <&ssi2>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Ext Spk", "LINE_OUT";
+		audio-codec = <&codec>;
+		mux-int-port = <2>;
+		mux-ext-port = <3>;
+	};
+};
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf..3ed7c9d 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -38,7 +38,7 @@ zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10800000
 
-dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
+dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb imx51-efikamx.dtb
 dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
 			       imx53-qsb.dtb imx53-smd.dtb
 dtb-$(CONFIG_SOC_IMX6Q)	+= imx6q-arm2.dtb \
-- 
1.7.9.5



From khilman at ti.com  Tue Aug  7 17:46:50 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 14:46:50 -0700
Subject: nfsroot problems with v3.6-rc1 on 37xx EVM and dynamic off-mode
In-Reply-To: <alpine.DEB.2.00.1208031340310.28888@utopia.booyaka.com> (Paul
 Walmsley's message of "Fri, 3 Aug 2012 14:20:07 -0600 (MDT)")
References: <alpine.DEB.2.00.1208031340310.28888@utopia.booyaka.com>
Message-ID: <87boim1ik5.fsf@ti.com>

Hi Paul,

Paul Walmsley <paul at pwsan.com> writes:

> NFS is broken on 37xx EVM with v3.6-rc1 after return from off-mode with 
> dynamic idle.  System suspend ("echo mem > /sys/power/state") with 
> off-mode enabled seems to work fine.
>
> No obvious ideas here as to what could have broken this.  It worked in 
> v3.5-rc2 + my omap_fixes_a_3.5rc at least:
>
> http://www.pwsan.com/omap/bootlogs/20120617/omap_fixes_a_3.5rc__52a5ae406dadef781bfcf3a641dae2064e9697ff/37xxevm_bootlog.txt
>
> After that, it's hard to tell when this problem started occurring, since 
> CORE stopped entering low-power states on OMAP3 on >= v3.5-rc3.

I see the same thing with vanilla v3.6-rc1, but it worked in my pm-cur
branch which has a few fixes that I'm queuing for v3.6-rc.  Tracking it
down, it seems the revert patch I just sent out[1] fixes this problem,
but I'm still a bit puzzled as to why.

Can you try v3.6-rc1 + that revert[1] to see if that fixes the problem
for you as well?

Thanks,

Kevin

[1] http://marc.info/?l=linux-omap&m=134437239010649&w=2


From khilman at ti.com  Tue Aug  7 17:49:57 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 14:49:57 -0700
Subject: [PATCH 1/3] ARM: OMAP: omap_device: keep track of driver bound
 status
In-Reply-To: <alpine.DEB.2.00.1208071518370.28250@utopia.booyaka.com> (Paul
 Walmsley's message of "Tue, 7 Aug 2012 15:26:00 -0600 (MDT)")
References: <1341961324-19657-1-git-send-email-khilman@ti.com>
 <alpine.DEB.2.00.1208071518370.28250@utopia.booyaka.com>
Message-ID: <871uji1iey.fsf@ti.com>

Paul Walmsley <paul at pwsan.com> writes:

> Hi Kevin
>
> a couple of minor comments
>
> On Tue, 10 Jul 2012, Kevin Hilman wrote:
>
>> Use the bus notifier to keep track of driver bound status by adding a
>> new internal field to struct omap_device: _driver_staus.
>
> "_driver_status"
>
>> This will be useful for follow-up patches which need to know whether
>> or not a driver is bound in order to make intelligent omap_device
>> enable/idle decisions.
>> 
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>> ---
>>  arch/arm/plat-omap/include/plat/omap_device.h |    2 ++
>>  arch/arm/plat-omap/omap_device.c              |   14 +++++++++-----
>>  2 files changed, 11 insertions(+), 5 deletions(-)
>> 
>> diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
>> index 4327b2c..e0486cb 100644
>> --- a/arch/arm/plat-omap/include/plat/omap_device.h
>> +++ b/arch/arm/plat-omap/include/plat/omap_device.h
>> @@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
>>   * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
>>   * @_state: one of OMAP_DEVICE_STATE_* (see above)
>>   * @flags: device flags
>> + * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
>>   *
>>   * Integrates omap_hwmod data into Linux platform_device.
>>   *
>> @@ -78,6 +79,7 @@ struct omap_device {
>>  	u8				hwmods_cnt;
>>  	u8				_state;
>>  	u8                              flags;
>> +	u8				_driver_status;
>>  };
>>  
>>  /* Device driver interface (call via platform_data fn ptrs) */
>> diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
>> index c490240..1d1b5ff 100644
>> --- a/arch/arm/plat-omap/omap_device.c
>> +++ b/arch/arm/plat-omap/omap_device.c
>> @@ -385,17 +385,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
>>  				      unsigned long event, void *dev)
>>  {
>>  	struct platform_device *pdev = to_platform_device(dev);
>> +	struct omap_device *od;
>>  
>>  	switch (event) {
>> -	case BUS_NOTIFY_ADD_DEVICE:
>> -		if (pdev->dev.of_node)
>> -			omap_device_build_from_dt(pdev);
>> -		break;
>> -
>>  	case BUS_NOTIFY_DEL_DEVICE:
>>  		if (pdev->archdata.od)
>>  			omap_device_delete(pdev->archdata.od);
>>  		break;
>> +	case BUS_NOTIFY_ADD_DEVICE:
>> +		if (pdev->dev.of_node)
>> +			omap_device_build_from_dt(pdev);
>> +		/* fall through */
>> +	default:
>> +		od = to_omap_device(pdev);
>> +		if (od)
>> +			od->_driver_status = event;
>
> _driver_status is a u8, but event is an unsigned long.  Might be worth 
> adding a WARN() to complain if event is greater than (2^8)-1.
>

It's probably more future proof if I just make _driver_status an
unsigned long, in case the values of those events ever change in the
driver core.

Thanks for the review,

Kevin



From matt at genesi-usa.com  Tue Aug  7 18:34:15 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue, 7 Aug 2012 17:34:15 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
Message-ID: <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>

On Mon, Aug 6, 2012 at 7:08 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 6 Aug 2012, Matt Sealey wrote:
>
>> I don't have a real *problem* with it, I just think since the kernel
>> can be compiled in both modes, but you may have some kind of remit to
>> not run ARM code (even if it's just a couple instructions at the
>> start) or some toolchain requirement or.. something.. it would be
>> entirely the bootloader's job to determine what mode it is in when it
>> jumps into the kernel. If you boot a Thumb bootloader and load an ARM
>> kernel, you'll get a crash. If you boot an ARM bootloader and a Thumb
>> kernel (with the current ARM instructions in head.S), you'll get a
>> crash. This is well defined, perfectly obvious, and I realise that..
>
> And isn't it also rather silly?

No?

> History has told that the more "entirely the bootloader's job" we rely
> on, the less reliable and interoperable we become.  Because you now have
> to compile two kernels to fully validate your bootloader instead of only
> one, and some people won't bother if the second kernel doesn't match
> their own use case.

That is true from a testing standpoint, and I guess I do agree with yourself and
Russell in this regard. But I do also think the chain of trust from
the bootloader
to kernel is important. I am in full violent disagreement with the
idea that doing
pin mux change operations based on a device tree description is both a necessity
or a requirement in Linux, especially as changing pin muxing this "late" in boot
is something a hardware designer would flip their lid over.

Sure, on some boards this is a requirement because the bootloaders do not do
the right thing, but in actual fact some of these boards (MX51 Babbage, MX6
SabreLite for example) cannot boot a device tree from their shipped bootloaders
anyway. To boot these boards from device tree you need to actually update U-Boot
or provide another compatible, capable bootloader, and in this case this support
should actually be provided in the bootloader (mux everything before
the kernel is
even in memory, and you reduce your device tree sizes by a factor of 3). The
idea that Linux should reinitialize everything anyway just to be sure is both
redundant, and means you're slowing down boot times and potentially causing
odd behavior (electrically) on boards with reset lines flailing around
during a mux
change, and GPIO directions changing on the fly for no good reason.

The device tree model has to imply some level of trust that the
configuration you
have in the device tree is exactly what you get on the board when the kernel has
booted. If that means adding pinctrl information to each device to
make sure it is
set up properly, then so be it. That said..

At Genesi we are proceeding with device tree support for all our platforms and
operating from an assumption that since we control our bootloader (it is U-Boot
after all, so not heavily..), we get to dictate what goes in our
device tree and we
will make a hard and fast stand against ANY pin mux changes going on inside the
kernel. And you guys will have to trust that we sat down and spent weeks and
weeks and weeks testing that this is actually the case before we committed
anything.

Just because there is a ton of absolutely awful, broken firmware code out there
doesn't mean it can and will always be the case, and Linux policy should not
be dictated on an architecture basis on a few bad eggs, especially if it means
developers in the big wide world have to jump through hoops. Surely it is just
as good for Linux to loudly advocate the correct solutions in firmware and
implement the workarounds anyway, like a device quirk, rather than just out and
out say "firmwares suck, ignore what they did, do it again. We don't trust them
and never will."

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From khilman at ti.com  Tue Aug  7 18:44:47 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 15:44:47 -0700
Subject: [PATCH] Revert "ARM: OMAP3: PM: call pre/post transition per
 powerdomain"
In-Reply-To: <1344372107-17786-1-git-send-email-khilman@ti.com> (Kevin
 Hilman's message of "Tue, 7 Aug 2012 13:41:47 -0700")
References: <1344372107-17786-1-git-send-email-khilman@ti.com>
Message-ID: <87lihqz5i8.fsf@ti.com>

Kevin Hilman <khilman at ti.com> writes:

> This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.
>
> Converstion to per-pwrdm per/post transition calls was a bit
> premature.  Only tracking MPU, PER & CORE in the idle path means we
> lose the accounting for all the other powerdomains which may also
> transition in idle.  On OMAP3, due to autodeps, several powerdomains
> transition along with MPU (e.g. DSS, USBHOST), and the accounting for
> these was lost with this patch.
>
> This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
> use-counting seires is merged since then we can properly do accounting
> without relying on a call in the idle path.
>
> Cc: Jean Pihet <jean.pihet at newoldbits.com>
> Cc: Tero Kristo <t-kristo at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Reported-by: Paul Walmsley <paul at pwsan.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>

After some debugging with Paul, I found that the patch being reverted
here was the cause of another regression: GPIO context not being
properly restored after off mode.  This caused the nfsroot problems in
off-mode on boards with ethernet devices with GPIO IRQ lines (Overo,
37xx EVM, ...)

Updating changelog, and will post v2 shortly.

Kevin


From matt at genesi-usa.com  Tue Aug  7 18:45:12 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue,  7 Aug 2012 17:45:12 -0500
Subject: [PATCH 0/2] ARM: imx: change building of SSI FIQ support for i.MX
 processors
Message-ID: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>

Patches to fix Thumb2 kernel building and change the dependency for SSI FIQ
support to a more specific option to prevent it from being needlessly built
in the first place on more frugal kernel configurations.

A better solution might be to rewrite the function in Thumb-compatible assembly
but the target processors do not support Thumb2 kernels anyway, and the last
time it was suggested the updated code was nacked by Russell. Since its built
as a side-effect on ARMv6/v7 i.MX processors, these could be considered somewhat
Needful Things(tm) by people wanting Thumb2 kernels based on imx_v6_v7_defconfig
or wanting to remove certain boards from their configs.

Matt Sealey (2):
  ARM: build ssi-fiq.S in ARM mode to prevent CONFIG_THUMB2_KERNEL
    build breakage
  ARM: only build ssi-fiq.S et al if CONFIG_SND_IMX_SOC_PCM_FIQ is
    selected

 arch/arm/plat-mxc/Makefile  |    2 +-
 arch/arm/plat-mxc/ssi-fiq.S |    1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

-- 
1.7.9.5



From matt at genesi-usa.com  Tue Aug  7 18:45:13 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue,  7 Aug 2012 17:45:13 -0500
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1344379514-30076-2-git-send-email-matt@genesi-usa.com>

If i.MX SSI FIQ support is enabled then it is impossible to build a Thumb2
kernel image due to the code not being written with Thumb2 in mind (over-use
of registers). In order not to break Thumb2 kernels, compile this as ARM. All
the processors which require this support will run ARM code so there is no
problem at runtime in doing this, even if it does produce a strange mix of
code that may not be desired.

In theory this should only be needed on configs based on imx_v4_v5_defconfig
where CONFIG_THUMB2_KERNEL cannot be selected anyway since these SoCs do not
have ARM cores capable of running Thumb2 code. This also makes rewriting the
code as Thumb-compatible kind of redundant. But since one Eukrea board audio
driver needs it, and there is an i.MX51 CPU module for this board, it gets
pulled in for imx_v6_v7_defconfig too, making this a necessity.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
---
 arch/arm/plat-mxc/ssi-fiq.S |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2d..ac09af8 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -28,6 +28,7 @@
 #define SSI_SIER_RFF0_EN	(1 << 2)
 
 		.text
+		.arm
 		.global	imx_ssi_fiq_start
 		.global	imx_ssi_fiq_end
 		.global imx_ssi_fiq_base
-- 
1.7.9.5



From matt at genesi-usa.com  Tue Aug  7 18:45:14 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue,  7 Aug 2012 17:45:14 -0500
Subject: [PATCH 2/2] ARM: only build ssi-fiq.S et al if
 CONFIG_SND_IMX_SOC_PCM_FIQ is selected
In-Reply-To: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
Message-ID: <1344379514-30076-3-git-send-email-matt@genesi-usa.com>

Further to the previous patch, a custom configuration may be used based on the
imx_v6_v7_defconfig which removes the board depending on the audio driver pulling
this support code. However, since it is built dependent on CONFIG_SND_IMX_SOC
it is enabled in the build for all i.MX processors which enable any audio drivers.

Correct this by only building the SSI FIQ support code when the more specific
CONFIG_SND_IMX_SOC_PCM_FIQ is enabled. Since it's enabled in the imx_v6_v7_defconfig
anyway by the Eukrea board, nothing changes using the defconfig, so this is just
a convenience for people reconfiguring their kernels more sparsely than the default.

Signed-off-by: Matt Sealey <matt at genesi-usa.com>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/plat-mxc/Makefile |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 6ac7200..89927f5 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-ifdef CONFIG_SND_IMX_SOC
+ifdef CONFIG_SND_IMX_SOC_PCM_FIQ
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
-- 
1.7.9.5



From khilman at ti.com  Tue Aug  7 18:47:39 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue,  7 Aug 2012 15:47:39 -0700
Subject: [PATCH v2] Revert "ARM: OMAP3: PM: call pre/post transition per
 powerdomain"
Message-ID: <1344379659-26152-1-git-send-email-khilman@ti.com>

This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.

Converstion to per-pwrdm per/post transition calls was a bit
premature.  Only tracking MPU, PER & CORE in the idle path means we
lose the accounting for all the other powerdomains which may also
transition in idle.  On OMAP3, due to autodeps, several powerdomains
transition along with MPU (e.g. DSS, USBHOST), and the accounting for
these was lost with this patch.  Since the accounting includes the
context loss counters, drivers for devices in those power domains
would never notice context lost, so would likely hang after any
off-mode transitions.

This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
use-counting seires is merged since then we can properly do accounting
without relying on a call in the idle path.

In addition, the original patch had another bug because the PER
powerdomain accounting was not updated until after the GPIO resume
hook is called.  Since gpio_resume_after_idle() checks the context
loss count (which is not yet updated) it would not properly restore
context, leaving the GPIO banks in an undefined state.

Cc: Jean Pihet <jean.pihet at newoldbits.com>
Cc: Tero Kristo <t-kristo at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Reported-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..05bd8f0 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -272,21 +272,16 @@ void omap_sram_idle(void)
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 
-	if (mpu_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(mpu_pwrdm);
-		pwrdm_pre_transition(neon_pwrdm);
-	}
+	pwrdm_pre_transition(NULL);
 
 	/* PER */
 	if (per_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(per_pwrdm);
 		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 		omap2_gpio_prepare_for_idle(per_going_off);
 	}
 
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
-		pwrdm_pre_transition(core_pwrdm);
 		if (core_next_state == PWRDM_POWER_OFF) {
 			omap3_core_save_context();
 			omap3_cm_save_context();
@@ -339,20 +334,14 @@ void omap_sram_idle(void)
 			omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 					       OMAP3430_GR_MOD,
 					       OMAP3_PRM_VOLTCTRL_OFFSET);
-		pwrdm_post_transition(core_pwrdm);
 	}
 	omap3_intc_resume_idle();
 
+	pwrdm_post_transition(NULL);
+
 	/* PER */
-	if (per_next_state < PWRDM_POWER_ON) {
+	if (per_next_state < PWRDM_POWER_ON)
 		omap2_gpio_resume_after_idle();
-		pwrdm_post_transition(per_pwrdm);
-	}
-
-	if (mpu_next_state < PWRDM_POWER_ON) {
-		pwrdm_post_transition(mpu_pwrdm);
-		pwrdm_post_transition(neon_pwrdm);
-	}
 }
 
 static void omap3_pm_idle(void)
-- 
1.7.9.2



From cyril at ti.com  Tue Aug  7 18:52:53 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Tue, 7 Aug 2012 18:52:53 -0400
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208040045360.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home>
Message-ID: <50219C45.7030601@ti.com>

Hi Nicolas,

On 8/4/2012 1:38 AM, Nicolas Pitre wrote:
[...]
>> extern unsigned __patch_table_begin, __patch_table_end;
>
> You could use "exttern void __patch_table_begin" so those symbols don't
> get any type that could be misused by mistake, while you still can take
> their addresses.
>

Looks like we'll have to stick with a non-void type here.  The compiler 
throws a warning when we try to take the address of a void.

[...]
> Did you verify with some test program that your patching routines do
> produce the same opcodes as the assembled equivalent for all possible
> shift values?  Especially for Thumb2 code which isn't as trivial to get
> right as the ARM one.
>

We've refactored the patching code into separate functions as:

static int do_patch_imm8_arm(u32 insn, u32 imm, u32 *ninsn);
static int do_patch_imm8_thumb(u32 insn, u32 imm, u32 *ninsn);


With this, the following test code has been used to verify the generated 
instruction encoding:

u32 arm_check[] = {
	0xe2810041, 0xe2810082, 0xe2810f41, 0xe2810f82, 0xe2810e41,
	0xe2810e82, 0xe2810d41, 0xe2810d82, 0xe2810c41, 0xe2810c82,
	0xe2810b41, 0xe2810b82, 0xe2810a41, 0xe2810a82, 0xe2810941,
	0xe2810982, 0xe2810841, 0xe2810882, 0xe2810741, 0xe2810782,
	0xe2810641, 0xe2810682, 0xe2810541, 0xe2810582, 0xe2810441,
};

u32 thumb_check[] = {
	0xf1010081, 0xf5017081, 0xf5017001, 0xf5016081, 0xf5016001,
	0xf5015081, 0xf5015001, 0xf5014081, 0xf5014001, 0xf5013081,
	0xf5013001, 0xf5012081, 0xf5012001, 0xf5011081, 0xf5011001,
	0xf5010081, 0xf5010001, 0xf1017081, 0xf1017001, 0xf1016081,
	0xf1016001, 0xf1015081, 0xf1015001, 0xf1014081, 0xf1014001,
};

int do_test(void)
{
	int i, ret;
	u32 ninsn, insn;
	
	insn = arm_check[0];
	for (i = 0; i < ARRAY_SIZE(arm_check); i++) {
		ret = do_patch_imm8_arm(insn, 0x41 << i, &ninsn);
		if (ret < 0)
			pr_err("patch failed at shift %d\n", i);
		if (ninsn != arm_check[i])
			pr_err("mismatch at %d, expect %x, got %x\n",
			       i, arm_check[i], ninsn);
	}

	insn = thumb_check[0];
	for (i = 0; i < ARRAY_SIZE(thumb_check); i++) {
		ret = do_patch_imm8_thumb(insn, 0x81 << i, &ninsn);
		if (ret < 0)
			pr_err("patch failed at shift %d\n", i);
		if (ninsn != thumb_check[i])
			pr_err("mismatch at %d, expect %x, got %x\n",
			       i, thumb_check[i], ninsn);
	}
}

Any ideas on improving these tests?

-- 
Thanks
- Cyril


From matt at genesi-usa.com  Tue Aug  7 19:06:27 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue, 7 Aug 2012 18:06:27 -0500
Subject: [PATCH 2/2] ARM i.MX5: Hard reset the IPU during startup
In-Reply-To: <20120807170428.GI18957@n2100.arm.linux.org.uk>
References: <1338888630-25930-1-git-send-email-s.hauer@pengutronix.de>
 <1338888630-25930-3-git-send-email-s.hauer@pengutronix.de>
 <20429.57208.228315.164637@ipc1.ka-ro> <20120605110834.GQ30400@pengutronix.de>
 <CAKGA1bkA3eEHn4sM277mzcRT5OUyipW18-k-X0nK+T9rrotJNw@mail.gmail.com>
 <20120807170428.GI18957@n2100.arm.linux.org.uk>
Message-ID: <CAKGA1bn8AEWhX_ZwuzB28mej7Y3da5_dFz+aOXcBaqMsJx9SBA@mail.gmail.com>

On Tue, Aug 7, 2012 at 12:04 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 06, 2012 at 04:31:50PM -0500, Matt Sealey wrote:
>> There used to be an ATAG for finding the linear framebuffer and it's
>> details but it got removed. This
>> was from a long forgotten time when you could initialize a VGA
>> graphics card and never care that
>> it had an interrupt or not, since it never got used for your average,
>> simple linear framebuffer operations.
>
> No ATAG definitions have been removed from the kernel.  The one you
> are referring to is:
>
> #define ATAG_VIDEOLFB   0x54410008
>
> and the associated struct tag_videolfb, which is still in the kernel
> today.  What isn't there is the implementation which reads this data,
> because only a few boards supported it, and they passed over some data
> from this to their FB drivers.
>
> So, when the boards were updated such that this became unnecessary,
> unsurprisingly the users disappeared (because they were all in platform
> code.)
>
> We have never had a generic "framebuffer" driver which has used this
> ATAG.  Or if one was created, it never came anywhere near mainline.
>
> Either way, the situation is not as you describe above.

That's funny, I was absolutely certain the complete removal was done
in the kernel, especially since it
was patched out of U-Boot (commit 47ea6ed) a long, long time ago based
on it being unsupported in
the ATAG parser.

I also saw a patch for OMAP which you nacked (violently :) long before
that, because it was parsing
ATAG_VIDEOLFB and passing it to it's display driver. Just found it again:

http://www.spinics.net/lists/linux-omap/msg08287.html

I must have just assumed that since the kernel doesn't pay attention
to it, which caused it to be
patched out of U-Boot since around June 2010, it would actually have
completely gone away by now.

Since no future boards use it (because you refuse to let them do it
anymore, and also because the
Device Tree is better anyway), no drivers use it anyway, wouldn't it
be time to remove it completely,
or is it there just for legacy's sake, a sepia-toned halcyon reminder
of what we used to do to boot
ARM boards? We are in 2012 though and the git history will always
reflect the day it got removed.
I think the only reason people haven't noticed it's still defined is
because U-Boot doesn't pass it
anymore and most of us are running U-Boots compiled much newer than June 2010.

Who's really going to miss it?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From davem at davemloft.net  Tue Aug  7 19:25:20 2012
From: davem at davemloft.net (David Miller)
Date: Tue, 07 Aug 2012 16:25:20 -0700 (PDT)
Subject: [PATCH 0/2] Add device tree support for davinci_mdio driver
 and fix cpsw DT binding documentation
In-Reply-To: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
References: <1344265558-5724-1-git-send-email-mugunthanvnm@ti.com>
Message-ID: <20120807.162520.1932972414873138617.davem@davemloft.net>

From: Mugunthan V N <mugunthanvnm at ti.com>
Date: Mon, 6 Aug 2012 20:35:56 +0530

> This patch set adds support for device tree for Davinci MDIO driver and fixes
> CPSW DT binding documentation to make it copy pastable to dts file.
> 
> This patch set is tested with the following git tree on AM335X Beagle Bone
> https://github.com/hvaibhav/am335x-linux/tree/am335x-upstream-staging-cpsw
> 
> Mugunthan V N (2):
>   drivers: net: ethernet: davince_mdio: device tree implementation
>   documentation: dt: bindings: cpsw: fixing the examples for directly
>     using it in dts file

Applied to net-next, thanks.


From khilman at ti.com  Tue Aug  7 19:26:21 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 07 Aug 2012 16:26:21 -0700
Subject: [linux-pm] [PATCH 4/4] PM: cleanup: stop mandating that platforms
 export (pm_idle)()
In-Reply-To: <0753050fb227e5a19f0df303d1e9bf74534aabcd.1343428708.git.len.brown@intel.com>
 (Len Brown's message of "Fri, 27 Jul 2012 18:42:55 -0400")
References: <1343428975-3897-1-git-send-email-lenb@kernel.org>
 <06ed885aac76cc68bd1ca1f32c8dcab7bcca1940.1343428708.git.len.brown@intel.com>
 <0753050fb227e5a19f0df303d1e9bf74534aabcd.1343428708.git.len.brown@intel.com>
Message-ID: <878vdqz3ky.fsf@ti.com>

+ linux-arm-kernel

Len Brown <lenb at kernel.org> writes:

> From: Len Brown <len.brown at intel.com>
>
> (pm_idle)() was originally used on x86 to vector bewteen
> ACPI and APM.  With the advent of CPU_IDLE, that reason
> for pm_idle to exist vanished.
>
> But x86 APM still scribbled on pm_idle from a module,
> so pm_idle didn't go away.  Worse, it was declared in pm.h,
> and so it spread to other architectures as dead code.
>
> But today, APM no longer scribbles on pm_idle, so
> x86 no longer requires pm_idle to be visible to modules,
> or global at all.
>
> Here we remove pm_idle from pm.h, to stop the mandate
> that all architectures define it.
>
> This deletes dead code from most architectures,
> while some continue using their own internal pm_idle.
>
> At the end of the day, pm_idle...
> becomes static in sh, was global
> becomes static in x86, was EXPORT_SYMBOL
> becomes as global in sparc, was EXPORT_SYMBOL
> continues as static in m32r (no pm.h use there)
> and is deleted from all other places in the kernel.
>
> Signed-off-by: Len Brown <len.brown at intel.com>
> Cc: x86 at kernel.org # x86
> Cc: Mike Frysinger <vapier at gentoo.org> # blackfin
> Cc: Jonas Bonn <jonas at southpole.se> # openrisc
> Cc: Tony Luck <tony.luck at intel.com> # ia64
> Cc: David Howells <dhowells at redhat.com> # mn10300
> Cc: Mikael Starvik <starvik at axis.com> # cris
> Cc: Michal Simek <monstr at monstr.eu> # microblaze
> Cc: Paul Mundt <lethal at linux-sh.org> # sh
> Cc: David S. Miller <davem at davemloft.net> # sparc
> Cc: Russell King <linux at arm.linux.org.uk> # ARM
> Cc: Rafael J. Wysocki <rjw at sisk.pl> # PM
> ---
>  arch/arm/kernel/process.c         | 12 +++---------

Just looking at the ARM changes, it looks good to me.  I tested it with
and without CPUidle on my ARM-based TI/OMAP platforms (3430/n900,
4430/Panda)

So for the arch/arm changes:

Reviewed-by: Kevin Hilman <khilman at ti.com>
Tested-by: Kevin Hilman <khilman at ti.com>

Kevin


From davem at davemloft.net  Tue Aug  7 19:29:23 2012
From: davem at davemloft.net (David Miller)
Date: Tue, 07 Aug 2012 16:29:23 -0700 (PDT)
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
Message-ID: <20120807.162923.34400427265666163.davem@davemloft.net>

From: Ian Molton <ian.molton at codethink.co.uk>
Date: Tue,  7 Aug 2012 15:34:45 +0100

> Fixed all comments.
> 
> * Dropped csb1724 defconfig.
> * Added patch to remove MV643XX_ETH_SHARED_NAME and MV643XX_ETH_NAME
> * Dropped un-necessary D-T irq fixup code

Who is going to take this series?


From matt at genesi-usa.com  Tue Aug  7 20:31:41 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue, 7 Aug 2012 19:31:41 -0500
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <20120807.162923.34400427265666163.davem@davemloft.net>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
Message-ID: <CAKGA1b=1Tct=Rp-itLGspXn4T3OyVGJUigwH0sPXRZo_2YX3ag@mail.gmail.com>

On Tue, Aug 7, 2012 at 6:29 PM, David Miller <davem at davemloft.net> wrote:
> From: Ian Molton <ian.molton at codethink.co.uk>
> Date: Tue,  7 Aug 2012 15:34:45 +0100
>
>> Fixed all comments.
>>
>> * Dropped csb1724 defconfig.
>> * Added patch to remove MV643XX_ETH_SHARED_NAME and MV643XX_ETH_NAME
>> * Dropped un-necessary D-T irq fixup code
>
> Who is going to take this series?

Would anyone mind too much if I *didn't* break out a Pegasos II and
test it? Our platform has a Marvell northbridge (Discovery II)
implementing this, with a Marvell PHY, and it's OpenFirmware (as in,
REAL OpenFirmware) so the device tree isn't about to change to fit new
bindings. But I'm not sure we even have one in the office that boots
anymore.. there may be users out there but they're well beyond
warranty support (early 2005 or so was the last time we sold one).

If anyone needs the original device tree entries to compare and
contrast I may be able to provide them such that any parsing and
initializing of the driver take into account this old
board/northbridge/implementation. I'm just curious if anyone cares
enough..

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From johnhlinn at gmail.com  Tue Aug  7 20:49:41 2012
From: johnhlinn at gmail.com (John Linn)
Date: Tue, 7 Aug 2012 17:49:41 -0700
Subject: changing clock source frequency input for ARM kernel
Message-ID: <CAB9O=CPoMdkbnCOTreUuNZ+yHa_+8L1A4VXk6A1ODtgxoGjz7Q@mail.gmail.com>

We are working on CPU frequency scaling and our clock source is
dependent on our CPU frequency. When we change the CPU frequency we'd
like to update the clock source so the time keeping is all correct.

It's not clear to use how to make this correcly. The ST mobile stuff
is the only example of calling clocksource_updatefreq() that we see,
but since it's in the enable function it's not clear that this will
help us.

We have another timer in the block that we can use to allow us to ping
pong when updating the frequency if needed, but it's still based on
the same clock which is dependent on the CPU frequency.  It seems not
wise to disable the clock source if there's only one then re-enable
it.

Thanks for any help,
John


From kgene.kim at samsung.com  Tue Aug  7 20:56:28 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 09:56:28 +0900
Subject: [PATCH] ARM: EXYNOS: cleanup unused code related to GPS
Message-ID: <0a2e01cd7500$a4765280$ed62f780$%kim@samsung.com>

From: Jonghwan Choi <jhbird.choi at samsung.com>

Signed-off-by: Jonghwan Choi <jhbird.choi at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c    |    9 ---------
 arch/arm/mach-exynos/include/mach/map.h |    1 -
 2 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..3b00e29 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
-		.name		= "gps",
-		.enable		= exynos5_clk_ip_gps_ctrl,
-		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 0)),
-	}, {
 		.name		= "nfcon",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 22),
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..9d1f3ac 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -131,7 +131,6 @@
 #define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
 #define EXYNOS5_PA_SYSMMU_IOP		0x12360000
 #define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
 #define EXYNOS5_PA_SYSMMU_ISP		0x13260000
 #define EXYNOS5_PA_SYSMMU_DRC		0x12370000
 #define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
-- 
1.7.4.1



From linux at prisktech.co.nz  Tue Aug  7 21:39:20 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:20 +1200
Subject: [PATCH 2/8] rtc: vt8500: Add devicetree support for vt8500-rtc
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-3-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/rtc/rtc-vt8500.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/rtc/rtc-vt8500.c b/drivers/rtc/rtc-vt8500.c
index 9e94fb1..7364564 100644
--- a/drivers/rtc/rtc-vt8500.c
+++ b/drivers/rtc/rtc-vt8500.c
@@ -23,6 +23,7 @@
 #include <linux/bcd.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 /*
  * Register definitions
@@ -302,12 +303,18 @@ static int __devexit vt8500_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-rtc", },
+	{}
+};
+
 static struct platform_driver vt8500_rtc_driver = {
 	.probe		= vt8500_rtc_probe,
 	.remove		= __devexit_p(vt8500_rtc_remove),
 	.driver		= {
 		.name	= "vt8500-rtc",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:18 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:18 +1200
Subject: [PATCH 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
Message-ID: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>

This patchset updates arch-vt8500 to devicetree and removes all the old-style
code. Support for WM8650 has also been added.

Example dts/dtsi files are given for the three currently supported models.

Major changes:

GPIO code has been converted to a platform_device and rewritten as WM8505
support was broken. Add support for WM8650 gpio controller.

UHCI support was missing. Added this as a generic non-pci uhci controller as
it doesn't require anything special. Should be usable by any system that doesn't
have special requirements to get the UHCI controller working.

Framebuffer code patched to support WM8650. The bindings for this are of concern
but there doesn't seem to be a formalized binding yet. This patch is based off
Sascha Hauer's current patch on the dri-devel mailing list and should be easily
patched out when its finalized.

Patchset based on Arnd's arm-soc/for-next branch.


Could I get this reviewed, hopefully for inclusion into v3.7.

Regards
Tony Prisk


Tony Prisk (8):
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  rtc: vt8500: Add devicetree support for vt8500-rtc
  serial: vt8500: Add devicetree support for vt8500-serial
  usb: vt8500: Add devicetree support for vt8500-ehci and -uhci.
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  ARM: vt8500: gpio: Devicetree support for arch-vt8500

 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 +
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 ++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 +
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   46 +++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 +
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   20 ++
 arch/arm/Kconfig                                   |    2 +
 arch/arm/boot/dts/vt8500.dtsi                      |   99 ++++++
 arch/arm/boot/dts/vt8500_ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8505.dtsi                      |  125 ++++++++
 arch/arm/boot/dts/wm8505_ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8650.dtsi                      |   95 ++++++
 arch/arm/boot/dts/wm8650_ref.dts                   |   31 ++
 arch/arm/mach-vt8500/Kconfig                       |   72 +----
 arch/arm/mach-vt8500/Makefile                      |    9 +-
 arch/arm/mach-vt8500/bv07.c                        |   80 -----
 arch/arm/mach-vt8500/common.h                      |   25 ++
 arch/arm/mach-vt8500/devices-vt8500.c              |   91 ------
 arch/arm/mach-vt8500/devices-wm8505.c              |   99 ------
 arch/arm/mach-vt8500/devices.c                     |  270 -----------------
 arch/arm/mach-vt8500/devices.h                     |   88 ------
 arch/arm/mach-vt8500/gpio.c                        |  240 ---------------
 arch/arm/mach-vt8500/include/mach/restart.h        |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h    |   88 ------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h    |   79 -----
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h    |  115 -------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h    |   78 -----
 arch/arm/mach-vt8500/irq.c                         |  160 +++++-----
 arch/arm/mach-vt8500/restart.c                     |   54 ----
 arch/arm/mach-vt8500/timer.c                       |   56 +++-
 arch/arm/mach-vt8500/vt8500.c                      |  192 ++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c                  |   79 -----
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-vt8500.c                         |  318 ++++++++++++++++++++
 drivers/rtc/rtc-vt8500.c                           |    7 +
 drivers/tty/serial/vt8500_serial.c                 |    7 +
 drivers/usb/host/Kconfig                           |    4 +-
 drivers/usb/host/ehci-vt8500.c                     |   24 +-
 drivers/usb/host/uhci-hcd.c                        |    5 +
 drivers/usb/host/uhci-platform.c                   |  166 ++++++++++
 drivers/video/Kconfig                              |    6 +-
 drivers/video/vt8500lcdfb.c                        |   77 ++++-
 drivers/video/wm8505fb.c                           |   95 +++++-
 drivers/video/wmt_ge_rops.c                        |    7 +
 52 files changed, 1674 insertions(+), 1566 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/vt8500_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650_ref.dts
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c
 create mode 100644 drivers/gpio/gpio-vt8500.c
 create mode 100644 drivers/usb/host/uhci-platform.c

-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:19 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:19 +1200
Subject: [PATCH 1/8] arm: vt8500: Add device tree files for VIA/Wondermedia
 SoC's
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-2-git-send-email-linux@prisktech.co.nz>

Add device tree files for VT8500, WM8505 and WM8650 SoC's and
reference boards.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/boot/dts/vt8500.dtsi    |   99 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/vt8500_ref.dts |   31 ++++++++++
 arch/arm/boot/dts/wm8505.dtsi    |  125 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8505_ref.dts |   31 ++++++++++
 arch/arm/boot/dts/wm8650.dtsi    |   95 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8650_ref.dts |   31 ++++++++++
 6 files changed, 412 insertions(+)
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/vt8500_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650_ref.dts

diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 0000000..7a2fe0e
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,99 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "via,vt8500";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc>;
+
+		intc: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "via,vt8500-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d800e400 {
+			compatible = "via,vt8500-fb";
+			reg = <0xd800e400 0x400>;
+			interrupts = <12>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/vt8500_ref.dts b/arch/arm/boot/dts/vt8500_ref.dts
new file mode 100644
index 0000000..ba5a6af
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500_ref.dts
@@ -0,0 +1,31 @@
+/*
+ * vt8500_ref.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+	model = "Benign BV07 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 0000000..76dbfdc
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,125 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8505";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8505-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007100 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007100 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007300 {
+			compatible = "platform-uhci";
+			reg = <0xd8007300 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		uart at d8370000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8370000 0x1040>;
+			interrupts = <31>;
+		};
+
+		uart at d8380000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8380000 0x1040>;
+			interrupts = <30>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505_ref.dts b/arch/arm/boot/dts/wm8505_ref.dts
new file mode 100644
index 0000000..3df6fbb
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505_ref.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8505_ref.dts - Device tree file for Wondermedia WM8505 reference board
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+	model = "Wondermedia WM8505";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <32>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 0000000..fab4ead
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,95 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8650";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8650-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650_ref.dts b/arch/arm/boot/dts/wm8650_ref.dts
new file mode 100644
index 0000000..3313006
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650_ref.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8650_ref.dts - Device tree file for Wondermedia WM8650 reference board
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+	model = "Wondermedia WM8650";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:21 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:21 +1200
Subject: [PATCH 3/8] serial: vt8500: Add devicetree support for vt8500-serial
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-4-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/tty/serial/vt8500_serial.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006f..a7f58c9 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -603,12 +604,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-uart", },
+	{}
+};
+
 static struct platform_driver vt8500_platform_driver = {
 	.probe  = vt8500_serial_probe,
 	.remove = __devexit_p(vt8500_serial_remove),
 	.driver = {
 		.name = "vt8500_serial",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:22 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:22 +1200
Subject: [PATCH 4/8] usb: vt8500: Add devicetree support for vt8500-ehci and
 -uhci.
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-5-git-send-email-linux@prisktech.co.nz>

Add devicetree support for vt8500-ehci.
Convert vt8500-uhci to a generic non-pci platform-uhci with
device tree support.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/usb/host/Kconfig         |    4 +-
 drivers/usb/host/ehci-vt8500.c   |   24 ++++--
 drivers/usb/host/uhci-hcd.c      |    5 ++
 drivers/usb/host/uhci-platform.c |  166 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 191 insertions(+), 8 deletions(-)
 create mode 100644 drivers/usb/host/uhci-platform.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index dcfaaa9..d7a6b10 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -450,7 +450,7 @@ config USB_OHCI_LITTLE_ENDIAN
 
 config USB_UHCI_HCD
 	tristate "UHCI HCD (most Intel and VIA) support"
-	depends on USB && (PCI || SPARC_LEON)
+	depends on USB && (PCI || SPARC_LEON || ARCH_VT8500)
 	---help---
 	  The Universal Host Controller Interface is a standard by Intel for
 	  accessing the USB hardware in the PC (which is also called the USB
@@ -468,7 +468,7 @@ config USB_UHCI_HCD
 config USB_UHCI_SUPPORT_NON_PCI_HC
 	bool
 	depends on USB_UHCI_HCD
-	default y if SPARC_LEON
+	default y if (SPARC_LEON  || ARCH_VT8500)
 
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c
index c1eda73..52e9f92 100644
--- a/drivers/usb/host/ehci-vt8500.c
+++ b/drivers/usb/host/ehci-vt8500.c
@@ -16,6 +16,7 @@
  *
  */
 
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
@@ -84,20 +85,23 @@ static const struct hc_driver vt8500_ehci_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static u64 wmt_ehci_dma_mask = DMA_BIT_MASK(32);
+
 static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
+	int irq;
 	int ret;
 
 	if (usb_disabled())
 		return -ENODEV;
 
-	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
-		pr_debug("resource[1] is not IORESOURCE_IRQ");
-		return -ENOMEM;
-	}
+	/* devicetree created devices don't specify a dma mask */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &wmt_ehci_dma_mask;
+
 	hcd = usb_create_hcd(&vt8500_ehci_hc_driver, &pdev->dev, "VT8500");
 	if (!hcd)
 		return -ENOMEM;
@@ -134,8 +138,9 @@ static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 
 	ehci_reset(ehci);
 
-	ret = usb_add_hcd(hcd, pdev->resource[1].start,
-			  IRQF_SHARED);
+	irq = platform_get_irq(pdev, 0);
+
+	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret == 0) {
 		platform_set_drvdata(pdev, hcd);
 		return ret;
@@ -162,6 +167,11 @@ static int vt8500_ehci_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id vt8500_ehci_ids[] = {
+	{ .compatible = "via,vt8500-ehci", },
+	{}
+};
+
 static struct platform_driver vt8500_ehci_driver = {
 	.probe		= vt8500_ehci_drv_probe,
 	.remove		= vt8500_ehci_drv_remove,
@@ -169,7 +179,9 @@ static struct platform_driver vt8500_ehci_driver = {
 	.driver = {
 		.name	= "vt8500-ehci",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(vt8500_ehci_ids),
 	}
 };
 
 MODULE_ALIAS("platform:vt8500-ehci");
+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index e4db350..5da5c99 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -846,6 +846,11 @@ static const char hcd_name[] = "uhci_hcd";
 #define PLATFORM_DRIVER		uhci_grlib_driver
 #endif
 
+#ifdef CONFIG_ARCH_VT8500
+#include "uhci-platform.c"
+#define PLATFORM_DRIVER		uhci_platform_driver
+#endif
+
 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
 #error "missing bus glue for uhci-hcd"
 #endif
diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
new file mode 100644
index 0000000..1d7e522
--- /dev/null
+++ b/drivers/usb/host/uhci-platform.c
@@ -0,0 +1,166 @@
+/*
+ * Generic UHCI HCD (Host Controller Driver) for Platform Devices
+ *
+ * Copyright (c) 2011 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This file is based on uhci-grlib.c
+ * (C) Copyright 2004-2007 Alan Stern, stern at rowland.harvard.edu
+ */
+
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static int uhci_platform_init(struct usb_hcd *hcd)
+{
+       struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+       uhci->rh_numports = uhci_count_ports(hcd);
+
+       /* Set up pointers to to generic functions */
+       uhci->reset_hc = uhci_generic_reset_hc;
+       uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc;
+
+       /* No special actions need to be taken for the functions below */
+       uhci->configure_hc = NULL;
+       uhci->resume_detect_interrupts_are_broken = NULL;
+       uhci->global_suspend_mode_is_broken = NULL;
+
+       /* Reset if the controller isn't already safely quiescent. */
+       check_and_reset_hc(uhci);
+       return 0;
+}
+
+static const struct hc_driver uhci_platform_hc_driver = {
+       .description =          hcd_name,
+       .product_desc =         "Generic UHCI Host Controller",
+       .hcd_priv_size =        sizeof(struct uhci_hcd),
+
+       /* Generic hardware linkage */
+       .irq =                  uhci_irq,
+       .flags =                HCD_MEMORY | HCD_USB11,
+
+       /* Basic lifecycle operations */
+       .reset =                uhci_platform_init,
+       .start =                uhci_start,
+#ifdef CONFIG_PM
+       .pci_suspend =          NULL,
+       .pci_resume =           NULL,
+       .bus_suspend =          uhci_rh_suspend,
+       .bus_resume =           uhci_rh_resume,
+#endif
+       .stop =                 uhci_stop,
+
+       .urb_enqueue =          uhci_urb_enqueue,
+       .urb_dequeue =          uhci_urb_dequeue,
+
+       .endpoint_disable =     uhci_hcd_endpoint_disable,
+       .get_frame_number =     uhci_hcd_get_frame_number,
+
+       .hub_status_data =      uhci_hub_status_data,
+       .hub_control =          uhci_hub_control,
+};
+
+static u64 platform_uhci_dma_mask = DMA_BIT_MASK(32);
+
+static int __devinit uhci_hcd_platform_probe(struct platform_device *pdev)
+{
+       struct usb_hcd *hcd;
+       struct uhci_hcd *uhci;
+       struct resource *res;
+       int ret;
+
+       if (usb_disabled())
+               return -ENODEV;
+
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &platform_uhci_dma_mask;
+
+       hcd = usb_create_hcd(&uhci_platform_hc_driver, &pdev->dev,
+                       pdev->name);
+       if (!hcd)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       hcd->rsrc_start = res->start;
+       hcd->rsrc_len = resource_size(res);
+
+       if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+               pr_err("%s: request_mem_region failed\n", __func__);
+               ret = -EBUSY;
+               goto err_rmr;
+       }
+
+       hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+       if (!hcd->regs) {
+               pr_err("%s: ioremap failed\n", __func__);
+               ret = -ENOMEM;
+               goto err_irq;
+       }
+       uhci = hcd_to_uhci(hcd);
+
+       uhci->regs = hcd->regs;
+
+       ret = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED |
+                                                               IRQF_SHARED);
+       if (ret)
+               goto err_uhci;
+
+       return 0;
+
+err_uhci:
+       iounmap(hcd->regs);
+err_irq:
+       release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+       usb_put_hcd(hcd);
+
+       return ret;
+}
+
+static int uhci_hcd_platform_remove(struct platform_device *pdev)
+{
+       struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+       usb_remove_hcd(hcd);
+       iounmap(hcd->regs);
+       release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+       usb_put_hcd(hcd);
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more.  This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel.  Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_hcd_platform_shutdown(struct platform_device *op)
+{
+       struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+       uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+static const struct of_device_id platform_uhci_ids[] = {
+       { .compatible = "platform-uhci", },
+       {}
+};
+
+static struct platform_driver uhci_platform_driver = {
+       .probe          = uhci_hcd_platform_probe,
+       .remove         = uhci_hcd_platform_remove,
+       .shutdown       = uhci_hcd_platform_shutdown,
+       .driver = {
+               .name = "platform-uhci",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(platform_uhci_ids),
+       },
+};
+
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:25 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:25 +1200
Subject: [PATCH 7/8] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-8-git-send-email-linux@prisktech.co.nz>

Bindings for gpio, interrupt controller, power management controller,
timer, realtime clock, serial uart, ehci and uhci controllers and
framebuffer controllers used on the arch-vt8500 platform.

Framebuffer binding also specifies a 'display' node which is required
for determining the lcd panel data.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +++++++
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +++++++
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 ++++++
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +++++++
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 ++++++++++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +++++++
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 +++++++
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +++++++
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +++++++
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   46 ++++++++++++++++++++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 ++++++
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   20 +++++++++
 13 files changed, 224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt

diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
new file mode 100644
index 0000000..1b3b187
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the VIA VT8500 SoC shall have the following properties:
+Required root node property:
+compatible = "via,vt8500";
+
+Boards with the Wondermedia WM8505 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8505";
+
+Boards with the Wondermedia WM8650 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8650";
+
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
new file mode 100644
index 0000000..0a4ce10
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
@@ -0,0 +1,16 @@
+VIA/Wondermedia VT8500 Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-intc"
+- reg : Should contain 1 register ranges(address and length)
+- #interrupt-cells : should be <1>
+
+Example:
+
+	intc: interrupt-controller at d8140000 {
+		compatible = "via,vt8500-intc";
+		interrupt-controller;
+		reg = <0xd8140000 0x10000>;
+		#interrupt-cells = <1>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
new file mode 100644
index 0000000..521b9c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia VT8500 Power Management Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-pmc"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	pmc at d8130000 {
+		compatible = "via,vt8500-pmc";
+		reg = <0xd8130000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
new file mode 100644
index 0000000..901c73f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+	timer at d8130100 {
+		compatible = "via,vt8500-timer";
+		reg = <0xd8130100 0x28>;
+		interrupts = <36>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
new file mode 100644
index 0000000..1a122bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+	or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+	1) bank
+	2) pin number
+	3) flags
+
+Example:
+
+	gpio: gpio-controller at d8110000 {
+		compatible = "via,vt8500-gpio";
+		gpio-controller;
+		reg = <0xd8110000 0x10000>;
+		#gpio-cells = <3>;
+	};
+
+	vibrate {
+		gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+	};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 0000000..3c0484c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+	rtc at d8100000 {
+		compatible = "via,vt8500-rtc";
+		reg = <0xd8100000 0x10000>;
+		interrupts = <48>;
+	};
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
new file mode 100644
index 0000000..3222502
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 UART Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-uart"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UART interrupt
+
+Example:
+
+	uart at d8210000 {
+		compatible = "via,vt8500-uart";
+		reg = <0xd8210000 0x1040>;
+		interrupts = <47>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
new file mode 100644
index 0000000..a4fb071
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/platform-uhci.txt
@@ -0,0 +1,15 @@
+Generic Platform UHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "platform-uhci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UHCI controller interrupt
+
+Example:
+
+	uhci at d8007b00 {
+		compatible = "platform-uhci";
+		reg = <0xd8007b00 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
new file mode 100644
index 0000000..17b3ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 EHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-ehci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : ehci controller interrupt
+
+Example:
+
+	ehci at d8007900 {
+		compatible = "via,vt8500-ehci";
+		reg = <0xd8007900 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af..5c63da2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -47,5 +47,7 @@ sirf	SiRF Technology, Inc.
 st	STMicroelectronics
 stericsson	ST-Ericsson
 ti	Texas Instruments
+via	VIA Technologies, Inc.
 wlf	Wolfson Microelectronics
+wm	Wondermedia Technologies, Inc.
 xlnx	Xilinx
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
new file mode 100644
index 0000000..ccd15b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
@@ -0,0 +1,46 @@
+VIA VT8500 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-fb"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : framebuffer controller interrupt
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts.
+
+Example:
+
+	fb at d800e400 {
+		compatible = "via,vt8500-fb";
+		reg = <0xd800e400 0x400>;
+		interrupts = <12>;
+	};
+
+VIA VT8500 Display
+-----------------------------------------------------
+Required properties:
+- xres : lcd panel horizontal resolution
+- yres : lcd panel vertical resolution
+- left-margin,
+- right-margin,
+- hsync-len: lcd panel horizontal timings in pixels
+- upper-margin,
+- lower-margin,
+- vsync-len: lcd panel verticals timings in pixels
+- bpp: lcd panel bit-depth.
+	<16> for RGB565, <32> for RGB888
+
+Example:
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
new file mode 100644
index 0000000..a850fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia Graphics Engine Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,prizm-ge-rops"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	ge_rops at d8050400 {
+		compatible = "wm,prizm-ge-rops";
+		reg = <0xd8050400 0x100>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
new file mode 100644
index 0000000..ab67382
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -0,0 +1,20 @@
+Wondermedia WM8505 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,wm8505-fb"
+- reg : Should contain 1 register ranges(address and length)
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts. See definition in
+	Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+
+
+Example:
+
+	fb at d8050800 {
+		compatible = "wm,wm8505-fb";
+		reg = <0xd8050800 0x200>;
+	};
+
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:23 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:23 +1200
Subject: [PATCH 5/8] video: vt8500: Add devicetree support for vt8500-fb and
 wm8505-fb
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-6-git-send-email-linux@prisktech.co.nz>

Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
tree bindings.
Small change in wm8505-fb.c to support WM8650 framebuffer color
format.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/Kconfig       |    6 +--
 drivers/video/vt8500lcdfb.c |   77 ++++++++++++++++++++++++++++++-----
 drivers/video/wm8505fb.c    |   95 ++++++++++++++++++++++++++++++++++++-------
 drivers/video/wmt_ge_rops.c |    7 ++++
 4 files changed, 158 insertions(+), 27 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..b66d951 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1788,7 +1788,7 @@ config FB_AU1200
 
 config FB_VT8500
 	bool "VT8500 LCD Driver"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
@@ -1797,11 +1797,11 @@ config FB_VT8500
 
 config FB_WM8505
 	bool "WM8505 frame buffer support"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
-	  This is the framebuffer driver for WonderMedia WM8505
+	  This is the framebuffer driver for WonderMedia WM8505/WM8650
 	  integrated LCD controller.
 
 source "drivers/video/geode/Kconfig"
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6e..5fb3a56 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -35,6 +35,13 @@
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
 
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
+#endif
+
+
 #define to_vt8500lcd_info(__info) container_of(__info, \
 						struct vt8500lcd_info, fb)
 
@@ -270,15 +277,21 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 {
 	struct vt8500lcd_info *fbi;
 	struct resource *res;
-	struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
 	void *addr;
 	int irq, ret;
 
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
+
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+			+ sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -333,9 +346,45 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
+	np = of_find_node_by_name(NULL, "display");
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n",__func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.fix.smem_start	= fb_mem_phys;
+	fbi->fb.fix.smem_len	= fb_mem_len;
+	fbi->fb.screen_base	= fb_mem_virt;
 
 	fbi->palette_size	= PAGE_ALIGN(512);
 	fbi->palette_cpu	= dma_alloc_coherent(&pdev->dev,
@@ -370,10 +419,11 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_irq;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
 
 	ret = vt8500lcd_set_par(&fbi->fb);
 	if (ret) {
@@ -448,12 +498,18 @@ static int __devexit vt8500lcd_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id via_dt_ids[] = {
+	{ .compatible = "via,vt8500-fb", },
+	{}
+};
+
 static struct platform_driver vt8500lcd_driver = {
 	.probe		= vt8500lcd_probe,
 	.remove		= __devexit_p(vt8500lcd_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "vt8500-lcd",
+		.of_match_table = of_match_ptr(via_dt_ids),
 	},
 };
 
@@ -462,3 +518,4 @@ module_platform_driver(vt8500lcd_driver);
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
 MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, via_dt_ids);
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd..aa1ada5 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/wait.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
 
 #include <mach/vt8500fb.h>
 
@@ -59,8 +62,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
 
-	/* Set in-memory picture format to RGB 32bpp */
-	writel(0x1c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
+	/*
+	 * Set in-memory picture format to RGB
+	 * 0x31C sets the correct color mode (RGB565) for WM8650
+	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
+	 */
+	writel(0x31c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
 	writel(1,		       fbi->regbase + WMT_GOVR_COLORSPACE1);
 
 	/* Virtual buffer size */
@@ -127,6 +134,18 @@ static int wm8505fb_set_par(struct fb_info *info)
 		info->var.blue.msb_right = 0;
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		info->fix.line_length = info->var.xres_virtual << 2;
+	} else if (info->var.bits_per_pixel == 16) {
+		info->var.red.offset = 11;
+		info->var.red.length = 5;
+		info->var.red.msb_right = 0;
+		info->var.green.offset = 5;
+		info->var.green.length = 6;
+		info->var.green.msb_right = 0;
+		info->var.blue.offset = 0;
+		info->var.blue.length = 5;
+		info->var.blue.msb_right = 0;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		info->fix.line_length = info->var.xres_virtual << 1;
 	}
 
 	wm8505fb_set_timing(info);
@@ -246,16 +265,20 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 	struct wm8505fb_info	*fbi;
 	struct resource		*res;
 	void			*addr;
-	struct vt8500fb_platform_data *pdata;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
 
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
+			sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -305,21 +328,58 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+	np = of_find_node_by_name(NULL, "display");
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
 
 	fbi->fb.var.nonstd		= 0;
 	fbi->fb.var.activate		= FB_ACTIVATE_NOW;
 
 	fbi->fb.var.height		= -1;
 	fbi->fb.var.width		= -1;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
-	fbi->fb.screen_size	= pdata->video_mem_len;
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n",__func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
+
+	fbi->fb.fix.smem_start		= fb_mem_phys;
+	fbi->fb.fix.smem_len		= fb_mem_len;
+	fbi->fb.screen_base		= fb_mem_virt;
+	fbi->fb.screen_size		= fb_mem_len;
 
 	if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
 		dev_err(&pdev->dev, "Failed to allocate color map\n");
@@ -395,12 +455,18 @@ static int __devexit wm8505fb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,wm8505-fb", },
+	{}
+};
+
 static struct platform_driver wm8505fb_driver = {
 	.probe		= wm8505fb_probe,
 	.remove		= __devexit_p(wm8505fb_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -409,3 +475,4 @@ module_platform_driver(wm8505fb_driver);
 MODULE_AUTHOR("Ed Spiridonov <edo.rus at gmail.com>");
 MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
 MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 55be386..a362480 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -158,12 +158,18 @@ static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,prizm-ge-rops", },
+	{ /* sentinel */ }
+};
+
 static struct platform_driver wmt_ge_rops_driver = {
 	.probe		= wmt_ge_rops_probe,
 	.remove		= __devexit_p(wmt_ge_rops_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "wmt_ge_rops",
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -173,3 +179,4 @@ MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com");
 MODULE_DESCRIPTION("Accelerators for raster operations using "
 		   "WonderMedia Graphics Engine");
 MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:26 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:26 +1200
Subject: [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>

Converted the existing arch-vt8500 gpio to a platform_device.
Added support for WM8505 and WM8650 GPIO controllers.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/gpio/Kconfig       |    6 +
 drivers/gpio/Makefile      |    1 +
 drivers/gpio/gpio-vt8500.c |  318 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 325 insertions(+)
 create mode 100644 drivers/gpio/gpio-vt8500.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 542f0c0..3c8897a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,12 @@ config GPIO_STA2X11
 	  Say yes here to support the STA2x11/ConneXt GPIO device.
 	  The GPIO module has 128 GPIO pins with alternate functions.
 
+config GPIO_VT8500
+	bool "VIA/Wondermedia SoC GPIO Support"
+	depends on ARCH_VT8500
+	help
+	  Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
 config GPIO_XILINX
 	bool "Xilinx GPIO support"
 	depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0f55662..2c014b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500)	+= gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)	+= gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
new file mode 100644
index 0000000..3306634
--- /dev/null
+++ b/drivers/gpio/gpio-vt8500.c
@@ -0,0 +1,318 @@
+/* linux/arch/arm/mach-vt8500/gpio.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ * Based on gpio.c:
+ * - Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+
+/*
+	We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
+	by one set of registers (although not all may be valid).
+
+	Because different SoC's have different register offsets, we pass the
+	register offsets as data in vt8500_gpio_dt_ids[].
+*/
+
+struct vt8500_gpio_bank_regs {
+	int	en;
+	int	dir;
+	int	data_out;
+	int	data_in;
+	int	ngpio;
+};
+
+struct vt8500_gpio_data {
+	unsigned int			num_banks;
+	struct vt8500_gpio_bank_regs	banks[];
+};
+
+#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)		\
+{								\
+	.en = __en,						\
+	.dir = __dir,						\
+	.data_out = __out,					\
+	.data_in = __in,					\
+	.ngpio = __ngpio,					\
+}
+
+static struct vt8500_gpio_data vt8500_data = {
+	.num_banks	= 7,
+	.banks	= {
+		VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
+		VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
+		VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
+		VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
+		VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
+		VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
+		VT8500_BANK(-1, 0x3C, 0x5C, 0x7C, 9),	 /* external gpio */
+	},
+};
+
+static struct vt8500_gpio_data wm8505_data = {
+	.num_banks	= 10,
+	.banks	= {
+		VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
+		VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
+		VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
+		VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
+		VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
+		VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
+		VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
+		VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
+		VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
+		VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+	},
+};
+
+/*
+ * No information about which bits are valid so we just make
+ * them all available until its figured out.
+ */
+static struct vt8500_gpio_data wm8650_data = {
+	.num_banks	= 9,
+	.banks	= {
+		VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
+		VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
+		VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
+		VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
+		VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
+		VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
+		VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
+		VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
+		VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+	},
+};
+
+struct vt8500_gpio_chip {
+	struct gpio_chip		chip;
+
+	const struct vt8500_gpio_bank_regs *regs;
+	void __iomem	*base;
+	unsigned int	regoff;
+};
+
+
+#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
+
+static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	unsigned val;
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	val = readl(vt8500_chip->base + vt8500_chip->regs->en +
+							vt8500_chip->regoff);
+	val |= (1 << offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en +
+							vt8500_chip->regoff);
+
+	return 0;
+}
+
+static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->en +
+							vt8500_chip->regoff);
+	val &= ~(1 << offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en +
+							vt8500_chip->regoff);
+}
+
+static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir +
+							vt8500_chip->regoff);
+	val &= ~(1 << offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir +
+							vt8500_chip->regoff);
+
+	return 0;
+}
+
+static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir +
+							vt8500_chip->regoff);
+	val |= (1 << offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir +
+							vt8500_chip->regoff);
+
+	if (value) {
+		val = readl(vt8500_chip->base + vt8500_chip->regs->data_out +
+							vt8500_chip->regoff);
+		val |= (1 << offset);
+		writel(val, vt8500_chip->base + vt8500_chip->regs->data_out +
+							vt8500_chip->regoff);
+	}
+	return 0;
+}
+
+static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	return (readl(vt8500_chip->base + vt8500_chip->regoff) >> offset) & 1;
+}
+
+static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->data_out +
+							vt8500_chip->regoff);
+	if (value)
+		val |= (1 << offset);
+	else
+		val &= ~(1 << offset);
+
+	writel(val, vt8500_chip->base + vt8500_chip->regs->data_out + 
+							vt8500_chip->regoff);
+}
+
+static int vt8500_of_xlate(struct gpio_chip *gc,
+			    const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	/* bank if specificed in gpiospec->args[0] */
+	if (flags)
+		*flags = gpiospec->args[2];
+
+	return gpiospec->args[1];
+}
+
+static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
+				const struct vt8500_gpio_data *data)
+{
+	struct vt8500_gpio_chip *vtchip;
+	struct gpio_chip *chip;
+	int i;
+	int pin_cnt = 0;
+
+	vtchip = devm_kzalloc(&pdev->dev,
+			sizeof(struct vt8500_gpio_chip) * data->num_banks,
+			GFP_KERNEL);
+	if (!vtchip) {
+		pr_err("%s: failed to allocate chip memory\n", __func__);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < data->num_banks; i++)
+	{
+		vtchip[i].base = base;
+		vtchip[i].regs = &data->banks[i];
+		vtchip[i].regoff = i << 2;
+
+		chip = &vtchip[i].chip;
+
+		chip->of_xlate = vt8500_of_xlate;
+		chip->of_gpio_n_cells = 3;
+		chip->of_node = pdev->dev.of_node;
+
+		chip->request = vt8500_gpio_request;
+		chip->free = vt8500_gpio_free;
+		chip->direction_input = vt8500_gpio_direction_input;
+		chip->direction_output = vt8500_gpio_direction_output;
+		chip->get = vt8500_gpio_get_value;
+		chip->set = vt8500_gpio_set_value;
+		chip->can_sleep = 0;
+		chip->base = pin_cnt;
+		chip->ngpio = data->banks[i].ngpio;
+
+		pin_cnt += data->banks[i].ngpio;
+
+		gpiochip_add(chip);
+	}
+	return 0;
+}
+
+static struct of_device_id vt8500_gpio_dt_ids[] = {
+	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
+	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
+	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
+	{ /* Sentinel */ },
+};
+
+static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
+{
+	void __iomem *gpio_base;
+	struct device_node *np;
+	const struct of_device_id *of_id =
+				of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -ENODEV;
+	}
+
+	np = of_find_matching_node(NULL, vt8500_gpio_dt_ids);
+	if (!np) {
+		dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
+		return -EFAULT;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(&pdev->dev, "Unable to map GPIO registers\n");
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	of_node_put(np);
+
+	vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+	return 0;
+}
+
+static struct platform_driver vt8500_gpio_driver = {
+	.probe		= vt8500_gpio_probe,
+	.driver		= {
+		.name	= "vt8500-gpio",
+		.owner	= THIS_MODULE,
+		.of_match_table = vt8500_gpio_dt_ids,
+	},
+};
+
+static int __init vt8500_gpio_init(void)
+{
+	return platform_driver_probe(&vt8500_gpio_driver, &vt8500_gpio_probe);
+}
+
+static void __exit vt8500_gpio_exit(void)
+{
+	return platform_driver_unregister(&vt8500_gpio_driver);
+}
+
+module_init(vt8500_gpio_init);
+module_exit(vt8500_gpio_exit);
+
+MODULE_DESCRIPTION("VT8500 GPIO Driver");
+MODULE_AUTHOR("Tony Prisk <linux at prisktech.co.nz>");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug  7 21:39:24 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed,  8 Aug 2012 13:39:24 +1200
Subject: [PATCH 6/8] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344389967-8465-7-git-send-email-linux@prisktech.co.nz>

Merged existing board files to a single dt-capable file.
Converted irq and timer code to devicetree.
Removed existing device files that are no longer required with
devicetree support.
All existing platform devices are converted to devicetree nodes
except GPIO and PWM.

GPIO support was limited to VT8500 (non-working on WM8505).

Removed restart.c and moved code into vt8500.c to remove
duplicate PMC code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/Kconfig                                |    2 +
 arch/arm/mach-vt8500/Kconfig                    |   72 +-----
 arch/arm/mach-vt8500/Makefile                   |    9 +-
 arch/arm/mach-vt8500/bv07.c                     |   80 -------
 arch/arm/mach-vt8500/common.h                   |   25 +++
 arch/arm/mach-vt8500/devices-vt8500.c           |   91 --------
 arch/arm/mach-vt8500/devices-wm8505.c           |   99 ---------
 arch/arm/mach-vt8500/devices.c                  |  270 -----------------------
 arch/arm/mach-vt8500/devices.h                  |   88 --------
 arch/arm/mach-vt8500/gpio.c                     |  240 --------------------
 arch/arm/mach-vt8500/include/mach/restart.h     |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h |   88 --------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h |   79 -------
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h |  115 ----------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h |   78 -------
 arch/arm/mach-vt8500/irq.c                      |  160 +++++++-------
 arch/arm/mach-vt8500/restart.c                  |   54 -----
 arch/arm/mach-vt8500/timer.c                    |   56 +++--
 arch/arm/mach-vt8500/vt8500.c                   |  192 ++++++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c               |   79 -------
 20 files changed, 350 insertions(+), 1531 deletions(-)
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6774c80..0555b70 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -996,6 +996,7 @@ config ARCH_VT8500
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_PWM
+	select USE_OF
 	help
 	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1613,6 +1614,7 @@ config ARCH_NR_GPIO
 	default 355 if ARCH_U8500
 	default 264 if MACH_H4700
 	default 512 if SOC_OMAP5
+	default 288 if ARCH_VT8500
 	default 0
 	help
 	  Maximum number of GPIOs in the system.
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2c20a34..44f9f9d 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,73 +1,15 @@
 if ARCH_VT8500
 
-config VTWM_VERSION_VT8500
+config VTWM_VERSION_WMT_DT
 	bool
 
-config VTWM_VERSION_WM8505
-	bool
-
-config MACH_BV07
-	bool "Benign BV07-8500 Mini Netbook"
-	depends on ARCH_VT8500
-	select VTWM_VERSION_VT8500
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-	bool "WM8505 7-inch generic netbook"
+config MACH_WMT_DT
+	bool "VIA/Wondermedia SoC based boards (Device Tree Support)"
 	depends on ARCH_VT8500
-	select VTWM_VERSION_WM8505
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-	bool "7-inch with 800x480 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	default y
-	help
-	  These are found in most of the netbooks in generic cases, as
-	  well as in Eken M001 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x480' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_800X600
-	bool "8-inch with 800x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M003 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X576
-	bool "10-inch with 1024x576 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
+	select VTWM_VERSION_WMT_DT
 	help
-	  These are found in CherryPal netbooks and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x576' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X600
-	bool "10-inch with 1024x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M006 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
+	  Add support for netbooks, tablets and other devices based on
+	  the reference board design as produced by VIA/WonderMedia, using
+	  VT8500/WM8505/WM8650 System-on-Chip.
 
 endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 54e6997..1966183 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,9 +1,4 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_VTWM_VERSION_WMT_DT) += irq.o timer.o
+obj-$(CONFIG_MACH_WMT_DT) += vt8500.o
 
 obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2..0000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_lcdc,
-	&vt8500_device_ehci,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-	wmt_setup_restart();
-	vt8500_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= vt8500_reserve_mem,
-	.map_io		= vt8500_map_io,
-	.init_irq	= vt8500_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
new file mode 100644
index 0000000..06e93bb
--- /dev/null
+++ b/arch/arm/mach-vt8500/common.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-vt8500/dt_common.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
+
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+				struct device_node *parent);
+
+#endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519ae..0000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-	tmp[1] = wmt_irq_res(IRQ_LCDC);
-	wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = VT8500_IC_BASE;
-	wmt_gpio_base = VT8500_GPIO_BASE;
-	wmt_pmc_base = VT8500_PMC_BASE;
-	wmt_i8042_base = VT8500_PS2_BASE;
-
-	wmt_nr_irqs = VT8500_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e..0000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-	wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART4);
-	wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART5);
-	wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = WM8505_IC_BASE;
-	wmt_sic_base = WM8505_SIC_BASE;
-	wmt_gpio_base = WM8505_GPIO_BASE;
-	wmt_pmc_base = WM8505_PMC_BASE;
-	wmt_i8042_base = WM8505_PS2_BASE;
-
-	wmt_nr_irqs = WM8505_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 1fcdc36..0000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-	.name           = "vt8500-lcd",
-	.id             = 0,
-	.dev		= {
-		.dma_mask	= &fb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-	.name           = "wm8505-fb",
-	.id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 480 * 2,
-	.mode		= {
-		.name		= "800x480",
-		.xres		= 800,
-		.yres		= 480,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "800x600",
-		.xres		= 800,
-		.yres		= 600,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 576 * 2,
-	.mode		= {
-		.name		= "1024x576",
-		.xres		= 1024,
-		.yres		= 576,
-		.left_margin	= 40,
-		.right_margin	= 24,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 96,
-		.vsync_len	= 2,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "1024x600",
-		.xres		= 1024,
-		.yres		= 600,
-		.left_margin	= 66,
-		.right_margin	= 2,
-		.upper_margin	= 19,
-		.lower_margin	= 1,
-		.hsync_len	= 23,
-		.vsync_len	= 8,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(panels); i++) {
-		if (strcmp(panels[i].mode.name, str) == 0) {
-			current_panel_idx = i;
-			break;
-		}
-	}
-	return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-				  unsigned long align) {
-	p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-			(p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-					(8 / p->bpp) + 1));
-	p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-							  align);
-	p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-	.name		= "vt8500_serial",
-	.id		= 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-	.name		= "vt8500_serial",
-	.id		= 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-	.name		= "vt8500_serial",
-	.id		= 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-	.name		= "vt8500_serial",
-	.id		= 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-	.name		= "vt8500_serial",
-	.id		= 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-	.name		= "vt8500_serial",
-	.id		= 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-	.name		= "vt8500-ehci",
-	.id		= 0,
-	.dev		= {
-		.dma_mask	= &ehci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_ge_rops = {
-	.name		= "wmt_ge_rops",
-	.id		= -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-	.name		= "vt8500-pwm",
-	.id		= 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-	.pwm_id		= 0,
-	.max_brightness	= 128,
-	.dft_brightness = 70,
-	.pwm_period_ns	= 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-	.name		= "pwm-backlight",
-	.id		= 0,
-	.dev		= {
-		.platform_data = &vt8500_pwmbl_data,
-	},
-};
-
-struct platform_device vt8500_device_rtc = {
-	.name		= "vt8500-rtc",
-	.id		= 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-	/* SoC MMIO registers */
-	[0] = {
-		.virtual	= 0xf8000000,
-		.pfn		= __phys_to_pfn(0xd8000000),
-		.length		= 0x00390000, /* max of all chip variants */
-		.type		= MT_DEVICE
-	},
-	/* PCI I/O space, numbers tied to those in <mach/io.h> */
-	[1] = {
-		.virtual	= 0xf0000000,
-		.pfn		= __phys_to_pfn(0xc0000000),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE
-	},
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-	panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-	preallocate_fb(&panels[current_panel_idx], SZ_4M);
-	vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-	panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-	preallocate_fb(&panels[current_panel_idx], 32);
-	vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e1..0000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_MEM,
-		.start = start,
-		.end = start + size - 1,
-	};
-
-	return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_IRQ,
-		.start = irq,
-		.end = irq,
-	};
-
-	return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-			       const struct resource *res, unsigned int num)
-{
-	if (unlikely(platform_device_add_resources(pdev, res, num)))
-		pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec..0000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS	0x0
-#define DIRECTION_REGS	0x20
-#define OUTVALUE_REGS	0x40
-#define INVALUE_REGS	0x60
-
-#define EXT_REGOFF	0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-	struct gpio_chip	chip;
-	unsigned int		shift;
-	unsigned int		regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-				     unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-				   unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-		val |= (1 << vt8500_chip->shift << offset);
-		writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-	}
-	return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-	return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-		>> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-	if (value)
-		val |= (1 << vt8500_chip->shift << offset);
-	else
-		val &= ~(1 << vt8500_chip->shift << offset);
-
-	writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)		\
-{									\
-	.chip = {							\
-		.label			= __name,			\
-		.request		= vt8500_muxed_gpio_request,	\
-		.free			= vt8500_muxed_gpio_free,	\
-		.direction_input  = vt8500_muxed_gpio_direction_input,	\
-		.direction_output = vt8500_muxed_gpio_direction_output,	\
-		.get			= vt8500_muxed_gpio_get_value,	\
-		.set			= vt8500_muxed_gpio_set_value,	\
-		.can_sleep		= 0,				\
-		.base			= __base,			\
-		.ngpio			= __num,			\
-	},								\
-	.shift		= __shift,					\
-	.regoff		= __off,					\
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-	VT8500_GPIO_BANK("uart0",	0,	0x0,	8,	4),
-	VT8500_GPIO_BANK("uart1",	4,	0x0,	12,	4),
-	VT8500_GPIO_BANK("spi0",	8,	0x0,	16,	4),
-	VT8500_GPIO_BANK("spi1",	12,	0x0,	20,	4),
-	VT8500_GPIO_BANK("spi2",	16,	0x0,	24,	4),
-	VT8500_GPIO_BANK("pwmout",	24,	0x0,	28,	2),
-
-	VT8500_GPIO_BANK("sdmmc",	0,	0x4,	30,	11),
-	VT8500_GPIO_BANK("ms",		16,	0x4,	41,	7),
-	VT8500_GPIO_BANK("i2c0",	24,	0x4,	48,	2),
-	VT8500_GPIO_BANK("i2c1",	26,	0x4,	50,	2),
-
-	VT8500_GPIO_BANK("mii",		0,	0x8,	52,	20),
-	VT8500_GPIO_BANK("see",		20,	0x8,	72,	4),
-	VT8500_GPIO_BANK("ide",		24,	0x8,	76,	7),
-
-	VT8500_GPIO_BANK("ccir",	0,	0xc,	83,	19),
-
-	VT8500_GPIO_BANK("ts",		8,	0x10,	102,	11),
-
-	VT8500_GPIO_BANK("lcd",		0,	0x14,	113,	23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val &= ~(1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-	return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val |= (1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-		val |= (1 << offset);
-		writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-	}
-	return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-	if (value)
-		val |= (1 << offset);
-	else
-		val &= ~(1 << offset);
-
-	writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	if (offset > 7)
-		return -EINVAL;
-
-	return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-	.label			= "extgpio",
-	.direction_input	= vt8500_gpio_direction_input,
-	.direction_output	= vt8500_gpio_direction_output,
-	.get			= vt8500_gpio_get_value,
-	.set			= vt8500_gpio_set_value,
-	.to_irq			= vt8500_gpio_to_irq,
-	.can_sleep		= 0,
-	.base			= 0,
-	.ngpio			= 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-	regbase = ioremap(wmt_gpio_base, SZ_64K);
-	if (!regbase) {
-		printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-		return;
-	}
-
-	gpiochip_add(&vt8500_external_gpios);
-
-	for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-		gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b78..7389795 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee91..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC	0	/* JPEG Encoder */
-#define IRQ_JPEGDEC	1	/* JPEG Decoder */
-				/* Reserved */
-#define IRQ_PATA	3	/* PATA Controller */
-				/* Reserved */
-#define IRQ_DMA		5	/* DMA Controller */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_GE		8	/* Graphic Engine */
-#define IRQ_GOV		9	/* Graphic Overlay Engine */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-#define IRQ_MPEGTS	11	/* Transport Stream Interface */
-#define IRQ_LCDC	12	/* LCD Controller */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_CIPHER	16	/* Cipher */
-#define IRQ_VPP		17	/* Video Post-Processor */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-				/* Reserved */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_LCDDF	27	/* LCD Data Formatter */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_MS		30	/* MemoryStick Controller */
-#define IRQ_MS_DMA	31	/* MemoryStick Controller DMA */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_I2S		34	/* I2S */
-#define IRQ_PCM		35	/* PCM */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_VPU		40	/* Video Processing Unit */
-#define IRQ_VID		41	/* Video Digital Input Interface */
-#define IRQ_AC97	42	/* AC97 Interface */
-#define IRQ_EHCI	43	/* USB */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_PS2MOUSE	45	/* PS/2 Mouse */
-#define IRQ_PS2KBD	46	/* PS/2 Keyboard */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_ADC		51	/* ADC */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_DMA0	56	/* DMA Channel 0 */
-#define IRQ_DMA1	57	/* DMA Channel 1 */
-#define IRQ_DMA2	58	/* DMA Channel 2 */
-#define IRQ_DMA3	59	/* DMA Channel 3 */
-#define IRQ_DMA4	60	/* DMA Channel 4 */
-#define IRQ_DMA5	61	/* DMA Channel 5 */
-#define IRQ_DMA6	62	/* DMA Channel 6 */
-#define IRQ_DMA7	63	/* DMA Channel 7 */
-
-#define VT8500_NR_IRQS		64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ec..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define VT8500_DDR_BASE		0xd8000000	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define VT8500_DMA_BASE		0xd8001000	/* 1k	DMA Controller */
-#define VT8500_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define VT8500_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define VT8500_USB_BASE		0xd8007800	/* 2k	USB OTG */
-# define VT8500_EHCI_BASE	0xd8007900	/*	EHCI */
-# define VT8500_UHCI_BASE	0xd8007b01	/*	UHCI */
-#define VT8500_PATA_BASE	0xd8008000	/* 512	PATA */
-#define VT8500_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define VT8500_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define VT8500_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define VT8500_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define VT8500_MS_BASE		0xd800b000	/* 1k	MS/MSPRO Controller */
-#define VT8500_LCDC_BASE	0xd800e400	/* 1k	LCD Controller */
-#define VT8500_VPU_BASE		0xd8050000	/* 256	VPU */
-#define VT8500_GOV_BASE		0xd8050300	/* 256	GOV */
-#define VT8500_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE	0xd8050900	/* 256	LCD Formatter */
-#define VT8500_VID_BASE		0xd8050a00	/* 256	VID */
-#define VT8500_VPP_BASE		0xd8050b00	/* 256	VPP */
-#define VT8500_TSBK_BASE	0xd80f4000	/* 4k	TSBK */
-#define VT8500_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define VT8500_JPEGENC_BASE	0xd80ff000	/* 4k	JPEG Encoder */
-#define VT8500_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define VT8500_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define VT8500_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define VT8500_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define VT8500_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define VT8500_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define VT8500_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define VT8500_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define VT8500_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define VT8500_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define VT8500_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define VT8500_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define VT8500_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define VT8500_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define VT8500_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define VT8500_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define VT8500_PCM_BASE		0xd82d0000	/* 64k	PCM */
-#define VT8500_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define VT8500_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define VT8500_ADC_BASE		0xd8340000	/* 64k	ADC */
-
-#define VT8500_REGS_END_PHYS	0xd834ffff	/* End of MMIO registers */
-#define VT8500_REGS_LENGTH	(VT8500_REGS_END_PHYS \
-				- VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI	0	/* UHC FS (UHCI?) */
-#define IRQ_EHCI	1	/* UHC HS */
-#define IRQ_UDCDMA	2	/* UDC DMA */
-				/* Reserved */
-#define IRQ_PS2MOUSE	4	/* PS/2 Mouse */
-#define IRQ_UDC		5	/* UDC */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_KEYPAD	8	/* Keypad */
-#define IRQ_DMA		9	/* DMA Controller */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-				/* Reserved */
-				/* Reserved */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_APB		16	/* APB Bridge */
-#define IRQ_DMA0	17	/* DMA Channel 0 */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-#define IRQ_PS2KBD	23	/* PS/2 Keyboard */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_DMA1	27	/* DMA Channel 1 */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_UART5	30	/* UART 5 */
-#define IRQ_UART4	31	/* UART 4 */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_DMA2	34	/* DMA Channel 2 */
-#define IRQ_I2S		35	/* I2S */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_DMA3	40	/* DMA Channel 3 */
-#define IRQ_DMA4	41	/* DMA Channel 4 */
-#define IRQ_AC97	42	/* AC97 Interface */
-				/* Reserved */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_DMA5	45	/* DMA Channel 5 */
-#define IRQ_DMA6	46	/* DMA Channel 6 */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_DMA7	51	/* DMA Channel 7 */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_SIC0	56	/* SIC IRQ0 */
-#define IRQ_SIC1	57	/* SIC IRQ1 */
-#define IRQ_SIC2	58	/* SIC IRQ2 */
-#define IRQ_SIC3	59	/* SIC IRQ3 */
-#define IRQ_SIC4	60	/* SIC IRQ4 */
-#define IRQ_SIC5	61	/* SIC IRQ5 */
-#define IRQ_SIC6	62	/* SIC IRQ6 */
-#define IRQ_SIC7	63	/* SIC IRQ7 */
-				/* Reserved */
-#define IRQ_JPEGDEC	65	/* JPEG Decoder */
-#define IRQ_SAE		66	/* SAE (?) */
-				/* Reserved */
-#define IRQ_VPU		79	/* Video Processing Unit */
-#define IRQ_VPP		80	/* Video Post-Processor */
-#define IRQ_VID		81	/* Video Digital Input Interface */
-#define IRQ_SPU		82	/* SPU (?) */
-#define IRQ_PIP		83	/* PIP Error */
-#define IRQ_GE		84	/* Graphic Engine */
-#define IRQ_GOV		85	/* Graphic Overlay Engine */
-#define IRQ_DVO		86	/* Digital Video Output */
-				/* Reserved */
-#define IRQ_DMA8	92	/* DMA Channel 8 */
-#define IRQ_DMA9	93	/* DMA Channel 9 */
-#define IRQ_DMA10	94	/* DMA Channel 10 */
-#define IRQ_DMA11	95	/* DMA Channel 11 */
-#define IRQ_DMA12	96	/* DMA Channel 12 */
-#define IRQ_DMA13	97	/* DMA Channel 13 */
-#define IRQ_DMA14	98	/* DMA Channel 14 */
-#define IRQ_DMA15	99	/* DMA Channel 15 */
-				/* Reserved */
-#define IRQ_GOVW	111	/* GOVW (?) */
-#define IRQ_GOVRSDSCD	112	/* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF	113	/* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD	114	/* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF	115	/* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS		116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df15509..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define WM8505_DDR_BASE		0xd8000400	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define WM8505_DMA_BASE		0xd8001800	/* 1k	DMA Controller */
-#define WM8505_VDMA_BASE	0xd8001c00	/* 1k	VDMA */
-#define WM8505_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define WM8505_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define WM8505_USB_BASE		0xd8007000	/* 2k	USB 2.0 Host */
-# define WM8505_EHCI_BASE	0xd8007100	/*	EHCI */
-# define WM8505_UHCI_BASE	0xd8007301	/*	UHCI */
-#define WM8505_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define WM8505_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define WM8505_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define WM8505_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define WM8505_VPU_BASE		0xd8050000	/* 256	VPU */
-#define WM8505_GOV_BASE		0xd8050300	/* 256	GOV */
-#define WM8505_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE	0xd8050800	/* 512	GOVR (frambuffer) */
-#define WM8505_VID_BASE		0xd8050a00	/* 256	VID */
-#define WM8505_SCL_BASE		0xd8050d00	/* 256	SCL */
-#define WM8505_VPP_BASE		0xd8050f00	/* 256	VPP */
-#define WM8505_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define WM8505_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define WM8505_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define WM8505_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define WM8505_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define WM8505_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define WM8505_SIC_BASE		0xd8150000	/* 64k	Secondary IC */
-#define WM8505_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define WM8505_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define WM8505_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define WM8505_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define WM8505_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define WM8505_KEYPAD_BASE	0xd8260000	/* 64k	Keypad control */
-#define WM8505_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define WM8505_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define WM8505_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define WM8505_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define WM8505_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define WM8505_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define WM8505_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define WM8505_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define WM8505_UART4_BASE	0xd8370000	/* 64k	UART 4 */
-#define WM8505_UART5_BASE	0xd8380000	/* 64k	UART 5 */
-
-#define WM8505_REGS_END_PHYS	0xd838ffff	/* End of MMIO registers */
-#define WM8505_REGS_LENGTH	(WM8505_REGS_END_PHYS \
-				- WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de04..b0d9ecb 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/irq.c
+ *  arch/arm/mach-vt8500/irq_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,16 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/* 
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
 
+#include <linux/of.h>
+#include <linux/of_address.h>
+
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR		0x40		/* Destination control
-						register, 64*u8 */
+#define VT8500_IC_DCTR		0x40
+
 #define VT8500_INT_ENABLE	(1 << 3)
 #define VT8500_TRIGGER_HIGH	(0 << 4)
 #define VT8500_TRIGGER_RISING	(1 << 4)
@@ -36,63 +46,52 @@
 				| VT8500_TRIGGER_FALLING)
 #define VT8500_IC_STATUS	0x80		/* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt = 0;
+
+struct vt8500_irq_priv {
+	void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv = (struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 edge;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+	edge = readb(base + VT8500_IC_DCTR + d->hwirq) & VT8500_EDGE;
 	if (edge) {
 		void __iomem *stat_reg = base + VT8500_IC_STATUS
-						+ (irq < 32 ? 0 : 4);
+						+ (d->hwirq < 32 ? 0 : 4);
 		unsigned status = readl(stat_reg);
 
-		status |= (1 << (irq & 0x1f));
+		status |= (1 << (d->hwirq & 0x1f));
 		writel(status, stat_reg);
 	} else {
-		u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+		u8 dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 
 		dctr &= ~VT8500_INT_ENABLE;
-		writeb(dctr, base + VT8500_IC_DCTR + irq);
+		writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 	}
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv = (struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 	dctr |= VT8500_INT_ENABLE;
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
-	unsigned orig_irq = irq;
+	struct vt8500_irq_priv *priv = (struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 	dctr &= ~VT8500_EDGE;
 
 	switch (flow_type) {
@@ -100,18 +99,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 		return -EINVAL;
 	case IRQF_TRIGGER_HIGH:
 		dctr |= VT8500_TRIGGER_HIGH;
-		__irq_set_handler_locked(orig_irq, handle_level_irq);
+		__irq_set_handler_locked(d->irq, handle_level_irq);
 		break;
 	case IRQF_TRIGGER_FALLING:
 		dctr |= VT8500_TRIGGER_FALLING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	case IRQF_TRIGGER_RISING:
 		dctr |= VT8500_TRIGGER_RISING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	}
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 
 	return 0;
 }
@@ -124,57 +123,56 @@ static struct irq_chip vt8500_irq_chip = {
 	.irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
 	unsigned int i;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+	/* Enable rotating priority for IRQ */
+	writel((1 << 6), base + 0x20);
+	writel(0, base + 0x24);
 
-	if (ic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
+	for (i = 0; i < 64; i++) {
+		/* Disable all interrupts and route them to IRQ */
+		writeb(0x00, base + VT8500_IC_DCTR + i);
+	}
+}
 
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
 
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+	.map = vt8500_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-	unsigned int i;
+	struct irq_domain *vt8500_irq_domain;
+	struct vt8500_irq_priv *priv;
+	struct device_node *np = node;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-	sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-	if (ic_regbase && sic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
-		writel((1 << 6), sic_regbase + 0x20);
-		writel(0, sic_regbase + 0x24);
-
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			if (i < 64)
-				writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-			else
-				writeb(0x00, sic_regbase + VT8500_IC_DCTR
-								+ i - 64);
-
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+	priv->base = of_iomap(np, 0);
+
+	vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+				&vt8500_irq_domain_ops, priv);
+	if (!vt8500_irq_domain)
+		printk("Unable to add wmt irq domain!\n");
+
+	irq_set_default_host(vt8500_irq_domain);
+
+	vt8500_init_irq_hw(priv->base);
+
+	printk("Added IRQ Controller @ %x [virq_base = %d]\n", (u32)(priv->base), irq_cnt);
+
+	irq_cnt += 64;
+
+	return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a..0000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE		0xD8130000
-#define WMT_PRIZM_PMSR_REG	0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-	struct device_node *np;
-
-	/*
-	 * Check if Power Mgmt Controller node is present in device tree. If no
-	 * device tree node, use the legacy PMSR value (valid for all current
-	 * SoCs).
-	 */
-	np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-	if (np) {
-		pmc_base = of_iomap(np, 0);
-
-		if (!pmc_base)
-			pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-		of_node_put(np);
-	} else {
-		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-		if (!pmc_base) {
-			pr_err("%s:ioremap(rstc) failed\n", __func__);
-			return;
-		}
-	}
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-	if (pmc_base)
-		writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c5..00778e9 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/* 
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET	0x0100
+#define VT8500_TIMER_HZ		3000000
 #define TIMER_MATCH_VAL		0x0000
 #define TIMER_COUNT_VAL		0x0010
 #define TIMER_STATUS_VAL	0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
 #define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
 #define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */
-#define VT8500_TIMER_HZ		3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
 	return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
 	.name           = "vt8500_timer",
 	.rating         = 200,
 	.read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
 	}
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
 	.name           = "vt8500_timer",
 	.features       = CLOCK_EVT_FEAT_ONESHOT,
 	.rating         = 200,
@@ -115,19 +122,41 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
 	.name    = "vt8500_timer",
 	.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = vt8500_timer_interrupt,
 	.dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+	{ .compatible = "via,vt8500-timer" },
+	{ }
+};
+
+void __init vt8500_timer_init(void)
 {
-	regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-	if (!regbase)
-		printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+	struct device_node *np;
+	int timer_irq;
 
+	np = of_find_matching_node(NULL, vt8500_timer_ids);
+	if (!np) {
+		printk(KERN_ERR "Timer: Timer description missing from Device Tree\n");
+		return;
+	}
+	regbase = of_iomap(np, 0);
+	if (!regbase) {
+		printk(KERN_ERR "Timer: Missing iobase description in Device Tree\n");
+		of_node_put(np);
+		return;
+	}
+	timer_irq = irq_of_parse_and_map(np, 0);
+	if (!timer_irq) {
+		printk(KERN_ERR "Timer: Missing irq description in Device Tree\n");
+		of_node_put(np);
+		return;
+	}
+	
 	writel(1, regbase + TIMER_CTRL_VAL);
 	writel(0xf, regbase + TIMER_STATUS_VAL);
 	writel(~0, regbase + TIMER_MATCH_VAL);
@@ -144,12 +173,9 @@ static void __init vt8500_timer_init(void)
 	clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
 	clockevent.cpumask = cpumask_of(0);
 
-	if (setup_irq(wmt_timer_irq, &irq))
+	if (setup_irq(timer_irq, &irq))
 		printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
 					clockevent.name);
 	clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-	.init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 0000000..9f98a6d
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,192 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE	0xD8110000
+#define LEGACY_PMC_BASE		0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG	0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG		0x12
+#define VT8500_PMSR_REG		0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+	if (pmc_base)
+		writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+	/* SoC MMIO registers */
+	[0] = {
+		.virtual	= 0xf8000000,
+		.pfn		= __phys_to_pfn(0xd8000000),
+		.length		= 0x00390000, /* max of all chip variants */
+		.type		= MT_DEVICE
+	},
+};
+
+void __init vt8500_map_io(void)
+{
+	iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+	local_irq_disable();
+	writew(5, pmc_base + VT8500_HCR_REG);
+	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+	struct device_node *np, *fb;
+	void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+	fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s:of_iomap(gpio_mux) failed\n", __func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s:ioremap(legacy_gpio_mux) failed\n", __func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+				gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+#ifdef CONFIG_FB_WM8505
+	fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np)
+			np = of_find_compatible_node(NULL, NULL,
+							"wm,wm8650-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s:of_iomap(gpio_mux) failed\n", __func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s:ioremap(legacy_gpio_mux) failed\n", __func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 0x80000000,
+				gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+	np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+	if (np) {
+		pmc_base = of_iomap(np, 0);
+
+		if (!pmc_base)
+			pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+		of_node_put(np);
+	} else {
+		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+		if (!pmc_base) {
+			pr_err("%s:ioremap(power_off) failed\n", __func__);
+		}
+	}
+	if (pmc_base)
+		pm_power_off = &vt8500_power_off;
+	else
+		pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+	{ .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+	{ /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+	of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+	.init = vt8500_timer_init,
+};
+
+static const char *vt8500_dt_compat[] = {
+	"via,vt8500",
+	"wm,wm8650",
+	"wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+	.dt_compat	= vt8500_dt_compat,
+	.map_io		= vt8500_map_io,
+	.init_irq	= vt8500_init_irq,
+	.timer		= &vt8500_timer,
+	.init_machine	= vt8500_init,
+	.restart	= vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886..0000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_ehci,
-	&vt8500_device_wm8505_fb,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-	wmt_setup_restart();
-	wm8505_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= wm8505_reserve_mem,
-	.map_io		= wm8505_map_io,
-	.init_irq	= wm8505_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= wm8505_7in_init,
-MACHINE_END
-- 
1.7.9.5



From robherring2 at gmail.com  Tue Aug  7 22:08:01 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 07 Aug 2012 21:08:01 -0500
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
 <50213214.7050505@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
Message-ID: <5021CA01.2020206@gmail.com>

On 08/07/2012 10:53 AM, Hiremath, Vaibhav wrote:
> On Tue, Aug 07, 2012 at 20:49:48, Rob Herring wrote:
>> On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
>>> If the module requires only one clocksource to function, then
>>> driver can very well call clk_get() api with "con_id = NULL",
>>>
>>>        clk = clk_get(dev, NULL);
>>>
>>> And platform code should respect this and return valid clk handle.
>>> That means, now the clk_get() api would rely on dev_id, and platform
>>> code should either have clk node with matching dev_id (with con_id=NULL)
>>> or return dummy clk node.
>>>
>>> With DT support, we can fix the dev_id for particular module
>>> using "struct of_dev_auxdata" to satisfy above clk framework requirement.
>>>
>>> In case of AM33XX, we required this for the DCAN module, so this
>>> patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
>>>
>>> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
>>> Cc: Tony Lindgren <tony at atomide.com>
>>> Cc: Paul Walmsley <paul at pwsan.com>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> ---
>>> This patch is boot tested on BeagleBone platform, and checked for
>>> clk_get() return value in d_can module driver.
>>>
>>>  arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
>>>  1 files changed, 17 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
>>> index 6f93a20..c9b7903 100644
>>> --- a/arch/arm/mach-omap2/board-generic.c
>>> +++ b/arch/arm/mach-omap2/board-generic.c
>>> @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>>>  	{ }
>>>  };
>>>
>>> +/*
>>> + * Lookup table for attaching a specific name and platform_data pointer to
>>> + * devices as they get created by of_platform_populate(). Ideally this table
>>> + * would not exist, but the current clock implementation depends on some devices
>>> + * having a specific name OR to satisfy NULL con_id requirement from driver.
>>> + */
>>> +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
>>> +	{ },
>>> +};
>>
>> Adding an additional clkdev lookup accomplishes the same thing and is a
>> cleaner solution.
>>
> 
> That is also required and I have submitted patch for the same -
> 
> http://www.spinics.net/lists/arm-kernel/msg187998.html

That only adds the non-DT name. What I'm saying is you can have 2 lookup
names for the same clock.

> 
> With DT support, I am getting dev_id as -
> 
>  - Without "reg" property: d_can.16 and d_can.17,
>    (I believe it changes dynamically here)
> 
>  - With "reg" property: 481cc000.d_can and 481d0000.d_can
> 
> Which is not so intuitive, I would like to see them as per Spec/TRM, so 
> doesn't this patch make sense?

The spec doesn't have a base address for the module? This name is going
to get used in sysfs anyway, and the old name should be going away.

> Similar thing has already been done for other platforms too.

Only ones I haven't reviewed.

Rob


From kgene.kim at samsung.com  Tue Aug  7 22:08:54 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 11:08:54 +0900
Subject: =?ks_c_5601-1987?B?UkU6IMi4vcU6IFtQQVRDSCAyLzRdIGFybS9kdHM6IGV4eQ==?=
 =?ks_c_5601-1987?B?bm9zNDogQWRkIERUUyBmaWxlcyBkZXJpdmVkIGZyb20gYw==?=
 =?ks_c_5601-1987?B?b21tb24gRXh5bm9zNA==?=
In-Reply-To: <201208072029.08693.arnd@arndb.de>
References: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <201208071938.26507.arnd@arndb.de>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4372EB@SN2PRD0510MB370.namprd05.prod.outlook.com>
 <201208072029.08693.arnd@arndb.de>
Message-ID: <0a3a01cd750a$c2e6a2b0$48b3e810$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> On Tuesday 07 August 2012, Dongjin Kim wrote:
> > Hi,
> >
> > I didn't use -M and I couldn't see any difference with the it.
> > Did I make something wrong on that patch?
> 
> No, I think it's just git being less smart about file moves than I was
> hoping
> for. It might do the right thing if you do the patch in two steps:
> 
Yeah, in this case, git does not work just as we expected :-(

> 1. rename exynos4210.dtsi to exynos4.dtsi and add a one-line
> exynos4210.dtsi
> file that just includes exynos4.dtsi.
> 
> 2. do all the changes for moving contents back from exynos4.dtsi into
> exynos4210.dtsi and exynos4412.dtsi.
> 
> Not sure if it's worth it though.

Hehehe, but I did with separated commit as per your comment and it was ok,
then squashed, same...uhm...I think, we don't need to keep two commits
here...

> Your version is probably good enough
> if there are no tools to do a better job automatically.
> 
I agree with Arnd's opinion and I will review in detail soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Aug  7 22:23:30 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 11:23:30 +0900
Subject: [PATCH v2] ODROID-X: hkdk4412: Add new hardware based on
 Exynos4412
In-Reply-To: <1344365401-18591-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344365401-18591-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <0a4301cd750c$cd29d2e0$677d78a0$%kim@samsung.com>

Dongjin Kim wrote:
> 
Hi,

Basically, we don't add more board file for non-DT for EXYNOS SoCs...

> The HKDK4412 is the CPU module developed by Hardkernel which is based on
> Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine
> ID
> (4289) is registered.
> 
This should be done at the link: http://www.arm.linux.org.uk/developer/machines/ by Russell King.

But I'm not sure whether it is worth to you without this patch for board file in mainline.

> Changes in v2:
>   -. Change regulator's display names
> 
> Change-Id: Iea6825a17b2e13f96bc6d892dd5135cad899b5df

No need gerrit Change-Id here.

> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>

If there is no reason, please use same e-mail address in the field of author and sign-off.

Note, if you want to use e-mail 'agreeyamobility.net', just add 'From: Dongjin Kim <dongjin.kim at agreeyamobility.net>', it's ok.

> ---
>  arch/arm/mach-exynos/Kconfig         |   23 +
>  arch/arm/mach-exynos/Makefile        |    1 +
>  arch/arm/mach-exynos/mach-hkdk4412.c |  964
> ++++++++++++++++++++++++++++++++++
>  arch/arm/tools/mach-types            |    1 +
>  4 files changed, 989 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c
> 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From Dongjin.Kim at agreeyamobility.net  Tue Aug  7 22:41:03 2012
From: Dongjin.Kim at agreeyamobility.net (Dongjin Kim)
Date: Wed, 8 Aug 2012 02:41:03 +0000
Subject: =?utf-8?B?7ZqM7IugOiBbUEFUQ0ggdjJdIE9EUk9JRC1YOiBoa2RrNDQxMjogQWRkIG5l?=
 =?utf-8?Q?w_hardware_based_on_Exynos4412?=
In-Reply-To: <0a4301cd750c$cd29d2e0$677d78a0$%kim@samsung.com>
References: <1344262254-14648-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344365401-18591-1-git-send-email-dongjin.kim@agreeyamobility.net>,
 <0a4301cd750c$cd29d2e0$677d78a0$%kim@samsung.com>
Message-ID: <A6A3B7488C419F488E5B13FFD03C08AD2F43CB39@BL2PRD0510MB363.namprd05.prod.outlook.com>

Hi,

Thank you for your advice.

And I didn't know non-DT board file will not be merged any more.
Rule is rule, I can manage the file in my git only.

I am very new to send git patches to open community, even I use git on my previous project.
I will pay attention to my next patches if I have more. :)

Thanks again.

Regards,
Dongjin.
________________________________________
?? ??: Kukjin Kim [kgene.kim at samsung.com]
?? ??: 2012? 8? 8? ??? ?? 11:23
?? ??: 'Dongjin Kim'
??: Dongjin Kim; 'Russell King'; 'Tony Lindgren'; 'Jon Medhurst'; 'Shawn Guo'; 'Uwe Kleine-K?nig'; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; linux-kernel at vger.kernel.org
??: RE: [PATCH v2] ODROID-X: hkdk4412: Add new hardware based on Exynos4412

Dongjin Kim wrote:
>
Hi,

Basically, we don't add more board file for non-DT for EXYNOS SoCs...

> The HKDK4412 is the CPU module developed by Hardkernel which is based on
> Exynos 4412.  mach_hkdk4412.c is to run on ODROID-X hardware and Machine
> ID
> (4289) is registered.
>
This should be done at the link: http://www.arm.linux.org.uk/developer/machines/ by Russell King.

But I'm not sure whether it is worth to you without this patch for board file in mainline.

> Changes in v2:
>   -. Change regulator's display names
>
> Change-Id: Iea6825a17b2e13f96bc6d892dd5135cad899b5df

No need gerrit Change-Id here.

> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>

If there is no reason, please use same e-mail address in the field of author and sign-off.

Note, if you want to use e-mail 'agreeyamobility.net', just add 'From: Dongjin Kim <dongjin.kim at agreeyamobility.net>', it's ok.

> ---
>  arch/arm/mach-exynos/Kconfig         |   23 +
>  arch/arm/mach-exynos/Makefile        |    1 +
>  arch/arm/mach-exynos/mach-hkdk4412.c |  964
> ++++++++++++++++++++++++++++++++++
>  arch/arm/tools/mach-types            |    1 +
>  4 files changed, 989 insertions(+)
>  create mode 100644 arch/arm/mach-exynos/mach-hkdk4412.c
>

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From linux at prisktech.co.nz  Tue Aug  7 22:40:30 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 8 Aug 2012 02:40:30 +0000
Subject: [PATCH 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <76F764B079F92A4E843589C893D0A022D1DC9141@SERVER.prisktech.co.nz>

Apologies for the formatting/style errors. Thought I had checkpatch'd these but missed a few (especially the uhci patch).
All formatting errors returned by scripts/checkpatch.pl are now fixed locally.

Apologies again,
Tony P

From b32955 at freescale.com  Tue Aug  7 22:37:59 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 8 Aug 2012 10:37:59 +0800
Subject: [PATCH V2] serial: mxs-auart: fix the wrong RTS hardware flow control
Message-ID: <1344393479-21109-1-git-send-email-b32955@freescale.com>

Without checking if the auart supports the hardware flow control or not,
the old mxs_auart_set_mctrl() asserted the RTS pin blindly.

This will causes the auart receives wrong data in the following case:
   The far-end has already started the write operation, and wait for
the auart asserts the RTS pin. Then the auart starts the read operation,
but mxs_auart_set_mctrl() may be called before we set the RTSCTS in the
mxs_auart_settermios(). So the RTS pin is asserted in a wrong situation,
and we get the wrong data in the end.

This bug has been catched when I connect the mx23(DTE) to the mx53(DCE).

This patch also replaces the AUART_CTRL2_RTS with AUART_CTRL2_RTSEN.
We should use the real the hardware flow control, not the software-controled
hardware flow control.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
v1 --> v2:
	The ASYNC_CTS_FLOW is set in the `flags` field of the tty_port{},
	not in the `flags` field of uart_port{}.
	
   
 drivers/tty/serial/mxs-auart.c |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 2e341b8..3a667ee 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -73,6 +73,7 @@
 #define AUART_CTRL0_CLKGATE			(1 << 30)
 
 #define AUART_CTRL2_CTSEN			(1 << 15)
+#define AUART_CTRL2_RTSEN			(1 << 14)
 #define AUART_CTRL2_RTS				(1 << 11)
 #define AUART_CTRL2_RXE				(1 << 9)
 #define AUART_CTRL2_TXE				(1 << 8)
@@ -259,9 +260,12 @@ static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
 
 	u32 ctrl = readl(u->membase + AUART_CTRL2);
 
-	ctrl &= ~AUART_CTRL2_RTS;
-	if (mctrl & TIOCM_RTS)
-		ctrl |= AUART_CTRL2_RTS;
+	ctrl &= ~AUART_CTRL2_RTSEN;
+	if (mctrl & TIOCM_RTS) {
+		if (u->state->port.flags & ASYNC_CTS_FLOW)
+			ctrl |= AUART_CTRL2_RTSEN;
+	}
+
 	s->ctrl = mctrl;
 	writel(ctrl, u->membase + AUART_CTRL2);
 }
@@ -359,9 +363,9 @@ static void mxs_auart_settermios(struct uart_port *u,
 
 	/* figure out the hardware flow control settings */
 	if (cflag & CRTSCTS)
-		ctrl2 |= AUART_CTRL2_CTSEN;
+		ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
 	else
-		ctrl2 &= ~AUART_CTRL2_CTSEN;
+		ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
 
 	/* set baud rate */
 	baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
-- 
1.7.0.4




From cjb at laptop.org  Tue Aug  7 23:05:33 2012
From: cjb at laptop.org (Chris Ball)
Date: Tue, 07 Aug 2012 23:05:33 -0400
Subject: [PATCH] mmc: atmel-mci: not busy flag has also to be used for
 read operations
In-Reply-To: <1343122924-7799-1-git-send-email-ludovic.desroches@atmel.com>
 (ludovic desroches's message of "Tue, 24 Jul 2012 11:42:04 +0200")
References: <1343122924-7799-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <87lihqxev6.fsf@octavius.laptop.org>

Hi,

On Tue, Jul 24 2012, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Even if the datasheet says that the not busy flag has to be used only for
> write operations, it's false excepted for version lesser than v2xx.
> Not waiting the not busy flag for read operations can cause the controller to
> hang-up during the initialization of some SD cards.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: stable at vger.kernel.org
>
>
> Hello,
>
> This is a fix for 3.5 and later.
>
> Due to the big changes into atmel-mci driver to support all atmel mci versions,
> a bug was introduced.
> With some SD cards (mainly micro) when using DMA, the controller hangs-up after
> the first CMD6 command because the next command is sent too early.
>
> Regards
>
> Ludovic
>
>
> ---
>  drivers/mmc/host/atmel-mci.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)

Thanks.  I've applied this for mmc-next now, but please put your patch
commentary *underneath* the "---" lines, so that it doesn't end up in
the git history itself.  I've rewritten the commit message to be:


From: Ludovic Desroches <ludovic.desroches at atmel.com>

Even if the datasheet says that the not busy flag has to be used only
for write operations, it's false except for version lesser than v2xx.

Not waiting on the not busy flag for read operations can cause the
controller to hang-up during the initialization of some SD cards
with DMA after the first CMD6 -- the next command is sent too early.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: stable <stable at vger.kernel.org> [3.5, 3.6]
Signed-off-by: Chris Ball <cjb at laptop.org>
---
<patch commentary can go here>

 drivers/mmc/host/atmel-mci.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From festevam at gmail.com  Tue Aug  7 23:07:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  8 Aug 2012 00:07:55 -0300
Subject: [PATCH] ARM: mxs_defconfig: Add framebuffer support
Message-ID: <1344395275-6275-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Add framebuffer support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Shawn,

I did not test it as I do not have an LCD for mx28evk handy.

 arch/arm/configs/mxs_defconfig |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4cb6170..6166838 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -110,6 +110,12 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_USB=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
-- 
1.7.1



From cjb at laptop.org  Tue Aug  7 23:14:23 2012
From: cjb at laptop.org (Chris Ball)
Date: Tue, 07 Aug 2012 23:14:23 -0400
Subject: [PATCH RESEND v5 0/4] atmel-mci device tree support
In-Reply-To: <1343136606-8874-1-git-send-email-ludovic.desroches@atmel.com>
 (ludovic desroches's message of "Tue, 24 Jul 2012 15:30:02 +0200")
References: <1343136606-8874-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <87hasexegg.fsf@octavius.laptop.org>

Hi,

On Tue, Jul 24 2012, ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Hello,
>
> I resend this set of patches because patches 2, 3 and 4 were acked by
> Jean-Christophe. Patch 1 was also acked by Jean-Christophe excepted for
> cd-inverted property since it was redundant with gpio bindings.

In future, it's helpful for me if you can add the Acked-by lines you
receive into the patches when you resend them.  Thanks!

> I thought we were agree to go ahead since it was a common binding already
> documented and it will concern all drivers.

Agreed.  It's a documented core MMC binding, it's fine to use it.

> Chris are you agree to take patch 1/4? Others patches may go to at91 tree,
> isn't it?

Yes, let's do that.  I've applied patch 1/4 to mmc-next for 3.7, and you
can send the others via the at91 tree with the ACK that Arnd gave.

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From zhangfei.gao at marvell.com  Tue Aug  7 23:14:57 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Wed,  8 Aug 2012 11:14:57 +0800
Subject: [PATCH v2 0/4]  dmaengine: add support mmp-pdma
Message-ID: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>

v1->v2
Sync with Arnd and Haojoan, change compatible name to "marvell,pdma-1.0"
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
Use IP name rather than platform name

v0->v1
Update dt member and desc according to Arnd's suggestion
Use dma_slave_config.slave_id to transfer drcmr followed Vinod's suggestion

Patch 4 is upload as example
mtd: pxa3xx-nand: replace pxa_request_dma with dmaengine
We would like hold this patch currently
since pdma will grab irq and disable pxa_init_dma. 


mmp-pdma is added under dmaengine framework.
The final purpose is replacing arch/arm/plat-pxa/dma.c

Test on pxa910 with pxa3xx-nand and dmatest.ko

Zhangfei Gao (4):
  dmaengine: mmp-pdma support
  dmaengine: mmp_tdma: add dt support
  dmatest: add dmaengine_slave_config for DMA_MEMCPY
  mtd: pxa3xx-nand: replace pxa_request_dma with dmaengine

 Documentation/devicetree/bindings/dma/mmp-dma.txt |   75 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/dmatest.c                             |    4 +
 drivers/dma/mmp_pdma.c                            |  872 +++++++++++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +-
 drivers/mtd/nand/pxa3xx_nand.c                    |  113 ++--
 include/linux/platform_data/mmp_dma.h             |   19 +
 8 files changed, 1072 insertions(+), 70 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h



From zhangfei.gao at marvell.com  Tue Aug  7 23:14:58 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Wed,  8 Aug 2012 11:14:58 +0800
Subject: [PATCH v2 1/4] dmaengine: mmp-pdma support
In-Reply-To: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344395701-30888-2-git-send-email-zhangfei.gao@marvell.com>

1. virtual channel vs. physical channel
Virtual channel is managed by dmaengine
Physical channel handling resource, such as irq
Physical channel is alloced dynamically as descending priority,
freed immediately when irq done.
The availble highest priority physically channel will alwayes be alloced

Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel

2. list: running list & pending list
submit: desc list -> pending list
issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
irq: free running list (IDLE)
     check pendlist -> pending list -> running list; free pending list (RUN)

3. irq:
Each list generate one irq, calling callback
One list may contain several desc chain, in such case, make sure only the last desc list generate irq.

4. async
Submit will add desc chain to pending list, which can be multi-called
If multi desc chain is submitted, only the last desc would generate irq -> call back
If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
If RUN, irq will start pending list

5. test
5.1 pxa3xx_nand on pxa910
5.2 insmod dmatest.ko (threads_per_chan=y)
By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   45 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/mmp_pdma.c                            |  873 +++++++++++++++++++++
 include/linux/platform_data/mmp_dma.h             |   19 +
 5 files changed, 945 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
new file mode 100644
index 0000000..3c85583
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -0,0 +1,45 @@
+* MARVELL MMP DMA controller
+
+Marvell Peripheral DMA Controller
+Used platfroms: pxa688, pxa910, pxa3xx, etc
+
+Required properties:
+- compatible: Should be "marvell,pdma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for pdma device
+- dma-channels: Number of DMA channels supported by the controller.
+
+"marvell,pdma-1.0"
+Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
+
+Examples:
+
+/*
+ * Each channel has specific irq
+ * ICU parse out irq channel from ICU register,
+ * while DMA controller may not able to distinguish the irq channel
+ * Using this method, interrupt-parent is required as demuxer
+ * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
+ * 18~21 is ADMA irq
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+	      interrupt-parent = <&intcmux32>;
+	      dma-channels = <16>;
+      };
+
+/*
+ * One irq for all channels
+ * Dmaengine driver (DMA controller) distinguish irq channel via
+ * parsing internal register
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <47>;
+	      dma-channels = <16>;
+      };
+
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8904bb6..663e26b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -292,6 +292,13 @@ config MMP_TDMA
 
 	  Say Y here if you enabled MMP ADMA, otherwise say N.
 
+config MMP_PDMA
+	bool "MMP PDMA support"
+	depends on (ARCH_MMP || ARCH_PXA)
+	select DMA_ENGINE
+	help
+	  Support the MMP PDMA engine for PXA and MMP platfrom.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index eabe13c..27bd86e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
+obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
new file mode 100644
index 0000000..6976480
--- /dev/null
+++ b/drivers/dma/mmp_pdma.c
@@ -0,0 +1,873 @@
+/*
+ * Copyright 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/platform_data/mmp_dma.h>
+#include <linux/dmapool.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+
+#include "dmaengine.h"
+
+#define DCSR		0x0000
+#define DALGN		0x00a0  /* DMA Alignment Register */
+#define DINT		0x00f0  /* DMA Interrupt Register */
+#define DDADR		0x0200
+#define DSADR		0x0204
+#define DTADR		0x0208
+#define DCMD		0x020c
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN	(1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR	(1 << 9)        /* The end of Receive */
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x1f		/* mask for Channel Number (read / write) */
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+#define PDMA_ALIGNMENT		3
+#define PDMA_MAX_DESC_BYTES	0x1000
+
+struct mmp_pdma_desc_hw {
+	u32 ddadr;	/* Points to the next descriptor + flags */
+	u32 dsadr;	/* DSADR value for the current transfer */
+	u32 dtadr;	/* DTADR value for the current transfer */
+	u32 dcmd;	/* DCMD value for the current transfer */
+} __aligned(32);
+
+struct mmp_pdma_desc_sw {
+	struct mmp_pdma_desc_hw desc;
+	struct list_head node;
+	struct list_head tx_list;
+	struct dma_async_tx_descriptor async_tx;
+};
+
+struct mmp_pdma_phy;
+
+struct mmp_pdma_chan {
+	struct device *dev;		/* Channel device */
+	struct dma_chan chan;		/* DMA common channel */
+	struct dma_async_tx_descriptor desc;
+	struct mmp_pdma_phy *phy;
+	enum dma_transfer_direction dir;
+
+	/* channel's basic info */
+	struct tasklet_struct tasklet;
+	u32 dcmd;
+	u32 drcmr;
+	u32 dev_addr;
+
+	/* list for desc */
+	spinlock_t desc_lock;		/* Descriptor list lock */
+	struct list_head chain_pending;	/* Link descriptors queue for pending */
+	struct list_head chain_running;	/* Link descriptors queue for running */
+	bool idle;			/* channel statue machine */
+
+	struct dma_pool *desc_pool;	/* Descriptors pool */
+};
+
+struct mmp_pdma_phy {
+	int idx;
+	void __iomem *base;
+	struct mmp_pdma_chan *vchan;
+};
+
+struct mmp_pdma_device {
+	int				dma_channels;
+	void __iomem			*base;
+	struct device			*dev;
+	struct dma_device		device;
+	struct mmp_pdma_phy		*phy;
+};
+
+#define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)
+#define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)
+#define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)
+#define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)
+
+static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
+{
+	u32 reg = (phy->idx << 4) + DDADR;
+
+	writel(addr, phy->base + reg);
+}
+
+static void enable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (!phy->vchan)
+		return;
+
+	reg = phy->vchan->drcmr;
+	reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
+	writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
+
+	reg = (phy->idx << 2) + DCSR;
+	writel(readl(phy->base + reg) | DCSR_RUN,
+					phy->base + reg);
+}
+
+static void disable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (phy) {
+		reg = (phy->idx << 2) + DCSR;
+		writel(readl(phy->base + reg) & ~DCSR_RUN,
+						phy->base + reg);
+	}
+}
+
+static int clear_chan_irq(struct mmp_pdma_phy *phy)
+{
+	u32 dcsr;
+	u32 dint = readl(phy->base + DINT);
+	u32 reg = (phy->idx << 2) + DCSR;
+
+	if (dint & BIT(phy->idx)) {
+		/* clear irq */
+		dcsr = readl(phy->base + reg);
+		writel(dcsr, phy->base + reg);
+		if ((dcsr & DCSR_BUSERR) && (phy->vchan))
+			dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
+		return 0;
+	}
+	return -EAGAIN;
+}
+
+static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_phy *phy = dev_id;
+
+	if (clear_chan_irq(phy) == 0) {
+		tasklet_schedule(&phy->vchan->tasklet);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_device *pdev = dev_id;
+	struct mmp_pdma_phy *phy;
+	u32 dint = readl(pdev->base + DINT);
+	int i, ret;
+	int irq_num = 0;
+
+	while (dint) {
+		i = __ffs(dint);
+		dint &= (dint - 1);
+		phy = &pdev->phy[i];
+		ret = mmp_pdma_chan_handler(irq, phy);
+		if (ret == IRQ_HANDLED)
+			irq_num++;
+	}
+
+	if (irq_num)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+/* lookup free phy channel as descending priority */
+static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
+{
+	int prio, i;
+	struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
+	struct mmp_pdma_phy *phy;
+
+	/*
+	 * dma channel priorities
+	 * ch 0 - 3,  16 - 19  <--> (0)
+	 * ch 4 - 7,  20 - 23  <--> (1)
+	 * ch 8 - 11, 24 - 27  <--> (2)
+	 * ch 12 - 15, 28 - 31  <--> (3)
+	 */
+	for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) {
+		for (i = 0; i < pdev->dma_channels; i++) {
+			if (prio != ((i & 0xf) >> 2))
+				continue;
+			phy = &pdev->phy[i];
+			if (!phy->vchan) {
+				phy->vchan = pchan;
+				return phy;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+/* desc->tx_list ==> pending list */
+static void append_pending_queue(struct mmp_pdma_chan *chan,
+					struct mmp_pdma_desc_sw *desc)
+{
+	struct mmp_pdma_desc_sw *tail =
+				to_mmp_pdma_desc(chan->chain_pending.prev);
+
+	if (list_empty(&chan->chain_pending))
+		goto out_splice;
+
+	/* one irq per queue, even appended */
+	tail->desc.ddadr = desc->async_tx.phys;
+	tail->desc.dcmd &= ~DCMD_ENDIRQEN;
+
+	/* softly link to pending list */
+out_splice:
+	list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
+}
+
+/**
+ * start_pending_queue - transfer any pending transactions
+ * pending list ==> running list
+ */
+static void start_pending_queue(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+
+	/* still in running, irq will start the pending list */
+	if (!chan->idle) {
+		dev_dbg(chan->dev, "DMA controller still busy\n");
+		return;
+	}
+
+	if (list_empty(&chan->chain_pending)) {
+		/* chance to re-fetch phy channel with higher prio */
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		dev_dbg(chan->dev, "no pending list\n");
+		return;
+	}
+
+	if (!chan->phy) {
+		chan->phy = lookup_phy(chan);
+		if (!chan->phy) {
+			dev_dbg(chan->dev, "no free dma channel\n");
+			return;
+		}
+	}
+
+	/*
+	 * pending -> running
+	 * reintilize pending list
+	 */
+	desc = list_first_entry(&chan->chain_pending,
+				struct mmp_pdma_desc_sw, node);
+	list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
+
+	/*
+	 * Program the descriptor's address into the DMA controller,
+	 * then start the DMA transaction
+	 */
+	set_desc(chan->phy, desc->async_tx.phys);
+	enable_chan(chan->phy);
+	chan->idle = false;
+}
+
+
+/* desc->tx_list ==> pending list */
+static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
+	struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
+	struct mmp_pdma_desc_sw *child;
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	list_for_each_entry(child, &desc->tx_list, node) {
+		cookie = dma_cookie_assign(&child->async_tx);
+	}
+
+	append_pending_queue(chan, desc);
+
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return cookie;
+}
+
+struct mmp_pdma_desc_sw *mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+	dma_addr_t pdesc;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
+	if (!desc) {
+		dev_err(chan->dev, "out of memory for link descriptor\n");
+		return NULL;
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	INIT_LIST_HEAD(&desc->tx_list);
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
+	/* each desc has submit */
+	desc->async_tx.tx_submit = mmp_pdma_tx_submit;
+	desc->async_tx.phys = pdesc;
+
+	return desc;
+}
+
+/**
+ * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
+ *
+ * This function will create a dma pool for descriptor allocation.
+ * Request irq only when channel is requested
+ * Return - The number of allocated descriptors.
+ */
+
+static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+
+	if (chan->desc_pool)
+		return 1;
+
+	chan->desc_pool =
+		dma_pool_create(dev_name(&dchan->dev->device), chan->dev,
+				  sizeof(struct mmp_pdma_desc_sw),
+				  __alignof__(struct mmp_pdma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate descriptor pool\n");
+		return -ENOMEM;
+	}
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	chan->idle = true;
+	chan->dev_addr = 0;
+	return 1;
+}
+
+static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
+				  struct list_head *list)
+{
+	struct mmp_pdma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+
+	}
+}
+
+static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+	mmp_pdma_free_desc_list(chan, &chan->chain_running);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+	chan->idle = true;
+	chan->dev_addr = 0;
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	return;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_memcpy(struct dma_chan *dchan,
+	dma_addr_t dma_dst, dma_addr_t dma_src,
+	size_t len, unsigned long flags)
+{
+	struct mmp_pdma_chan *chan;
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
+	size_t copy = 0;
+
+	if (!dchan)
+		return NULL;
+
+	if (!len)
+		return NULL;
+
+	chan = to_mmp_pdma_chan(dchan);
+
+	do {
+		/* Allocate the link descriptor from DMA pool */
+		new = mmp_pdma_alloc_descriptor(chan);
+		if (!new) {
+			dev_err(chan->dev, "no memory for desc\n");
+			goto fail;
+		}
+
+		copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
+
+		new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
+		new->desc.dsadr = dma_src;
+		new->desc.dtadr = dma_dst;
+
+		if (!first)
+			first = new;
+		else
+			prev->desc.ddadr = new->async_tx.phys;
+
+		new->async_tx.cookie = 0;
+		async_tx_ack(&new->async_tx);
+
+		prev = new;
+		len -= copy;
+
+		if (chan->dir == DMA_MEM_TO_DEV) {
+			dma_src += copy;
+		} else if (chan->dir == DMA_DEV_TO_MEM) {
+			dma_dst += copy;
+		} else if (chan->dir == DMA_MEM_TO_MEM) {
+			dma_src += copy;
+			dma_dst += copy;
+		}
+
+		/* Insert the link descriptor to the LD ring */
+		list_add_tail(&new->node, &first->tx_list);
+	} while (len);
+
+	first->async_tx.flags = flags; /* client is in control of this ack */
+	first->async_tx.cookie = -EBUSY;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
+			 unsigned int sg_len, enum dma_transfer_direction dir,
+			 unsigned long flags, void *context)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
+	size_t len, avail;
+	struct scatterlist *sg;
+	dma_addr_t addr;
+	int i;
+
+	if ((sgl == NULL) || (sg_len == 0))
+		return NULL;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		addr = sg_dma_address(sg);
+		avail = sg_dma_len(sgl);
+
+		do {
+			len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
+
+			/* allocate and populate the descriptor */
+			new = mmp_pdma_alloc_descriptor(chan);
+			if (!new) {
+				dev_err(chan->dev, "no memory for desc\n");
+				goto fail;
+			}
+
+			new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
+			if (dir == DMA_MEM_TO_DEV) {
+				new->desc.dsadr = addr;
+				new->desc.dtadr = chan->dev_addr;
+			} else {
+				new->desc.dsadr = chan->dev_addr;
+				new->desc.dtadr = addr;
+			}
+
+			if (!first)
+				first = new;
+			else
+				prev->desc.ddadr = new->async_tx.phys;
+
+			new->async_tx.cookie = 0;
+			async_tx_ack(&new->async_tx);
+			prev = new;
+
+			/* Insert the link descriptor to the LD ring */
+			list_add_tail(&new->node, &first->tx_list);
+
+			/* update metadata */
+			addr += len;
+			avail -= len;
+		} while (avail);
+	}
+
+	first->async_tx.cookie = -EBUSY;
+	first->async_tx.flags = flags;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
+		unsigned long arg)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct dma_slave_config *cfg = (void *)arg;
+	unsigned long flags;
+	int ret = 0;
+	u32 maxburst = 0, addr = 0;
+	enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+
+	if (!dchan)
+		return -EINVAL;
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		disable_chan(chan->phy);
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		spin_lock_irqsave(&chan->desc_lock, flags);
+		mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+		mmp_pdma_free_desc_list(chan, &chan->chain_running);
+		spin_unlock_irqrestore(&chan->desc_lock, flags);
+		chan->idle = true;
+		break;
+	case DMA_SLAVE_CONFIG:
+		if (cfg->direction == DMA_DEV_TO_MEM) {
+			chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
+			maxburst = cfg->src_maxburst;
+			width = cfg->src_addr_width;
+			addr = cfg->src_addr;
+		} else if (cfg->direction == DMA_MEM_TO_DEV) {
+			chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
+			maxburst = cfg->dst_maxburst;
+			width = cfg->dst_addr_width;
+			addr = cfg->dst_addr;
+		} else if (cfg->direction == DMA_MEM_TO_MEM) {
+			chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
+			width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+			maxburst = 32;
+		}
+
+		if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+			chan->dcmd |= DCMD_WIDTH1;
+		else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+			chan->dcmd |= DCMD_WIDTH2;
+		else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
+			chan->dcmd |= DCMD_WIDTH4;
+
+		if (maxburst == 8)
+			chan->dcmd |= DCMD_BURST8;
+		else if (maxburst == 16)
+			chan->dcmd |= DCMD_BURST16;
+		else if (maxburst == 32)
+			chan->dcmd |= DCMD_BURST32;
+
+		if (cfg) {
+			chan->dir = cfg->direction;
+			chan->drcmr = cfg->slave_id;
+		}
+		chan->dev_addr = addr;
+		break;
+	default:
+		return -ENOSYS;
+	}
+
+	return ret;
+}
+
+static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
+			dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	enum dma_status ret;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	ret = dma_cookie_status(dchan, cookie, txstate);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return ret;
+}
+
+/**
+ * mmp_pdma_issue_pending - Issue the DMA start command
+ * pending list ==> running list
+ */
+static void mmp_pdma_issue_pending(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+}
+
+/*
+ * dma_do_tasklet
+ * Do call back
+ * Start pending list
+ */
+static void dma_do_tasklet(unsigned long data)
+{
+	struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
+	struct mmp_pdma_desc_sw *desc, *_desc;
+	LIST_HEAD(chain_cleanup);
+	unsigned long flags;
+
+	/* submit pending list; callback for each desc; free desc */
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	/* update the cookie if we have some descriptors to cleanup */
+	if (!list_empty(&chan->chain_running)) {
+		dma_cookie_t cookie;
+
+		desc = to_mmp_pdma_desc(chan->chain_running.prev);
+		cookie = desc->async_tx.cookie;
+		dma_cookie_complete(&desc->async_tx);
+
+		dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
+	}
+
+	/*
+	 * move the descriptors to a temporary list so we can drop the lock
+	 * during the entire cleanup operation
+	 */
+	list_splice_tail_init(&chan->chain_running, &chain_cleanup);
+
+	/* the hardware is now idle and ready for more */
+	chan->idle = true;
+
+	/* Start any pending transactions automatically */
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	/* Run the callback for each descriptor, in order */
+	list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
+		struct dma_async_tx_descriptor *txd = &desc->async_tx;
+
+		/* Remove from the list of transactions */
+		list_del(&desc->node);
+		/* Run the link descriptor callback function */
+		if (txd->callback)
+			txd->callback(txd->callback_param);
+
+		dma_pool_free(chan->desc_pool, desc, txd->phys);
+	}
+}
+
+static int __devexit mmp_pdma_remove(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev = platform_get_drvdata(op);
+
+	dma_async_device_unregister(&pdev->device);
+	return 0;
+}
+
+static int __devinit mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
+							int idx, int irq)
+{
+	struct mmp_pdma_phy *phy  = &pdev->phy[idx];
+	struct mmp_pdma_chan *chan;
+	int ret;
+
+	chan = devm_kzalloc(pdev->dev,
+			sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (chan == NULL)
+		return -ENOMEM;
+
+	phy->idx = idx;
+	phy->base = pdev->base;
+
+	if (irq) {
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
+		if (ret) {
+			dev_err(pdev->dev, "channel request irq fail!\n");
+			return ret;
+		}
+	}
+
+	spin_lock_init(&chan->desc_lock);
+	chan->dev = pdev->dev;
+	chan->chan.device = &pdev->device;
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+	INIT_LIST_HEAD(&chan->chain_pending);
+	INIT_LIST_HEAD(&chan->chain_running);
+
+	/* register virt channel to dma engine */
+	list_add_tail(&chan->chan.device_node,
+			&pdev->device.channels);
+
+	return 0;
+}
+
+static struct of_device_id mmp_pdma_dt_ids[] = {
+	{ .compatible = "marvell,pdma-1.0", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
+
+static int __devinit mmp_pdma_probe(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev;
+	const struct of_device_id *of_id;
+	struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
+	struct resource *iores;
+	int i, ret, irq = 0;
+	int dma_channels = 0, irq_num = 0;
+
+	pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+	pdev->dev = &op->dev;
+
+	iores = platform_get_resource(op, IORESOURCE_MEM, 0);
+	if (!iores)
+		return -EINVAL;
+
+	pdev->base = devm_request_and_ioremap(pdev->dev, iores);
+	if (!pdev->base)
+		return -EADDRNOTAVAIL;
+
+	of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
+	if (of_id)
+		of_property_read_u32(pdev->dev->of_node,
+				"dma-channels",	&dma_channels);
+	else if (pdata && pdata->dma_channels)
+		dma_channels = pdata->dma_channels;
+	else
+		dma_channels = 32;	/* default 32 channel */
+	pdev->dma_channels = dma_channels;
+
+	for (i = 0; i < dma_channels; i++) {
+		if (platform_get_irq(op, i) > 0)
+			irq_num++;
+	}
+
+	pdev->phy = devm_kzalloc(pdev->dev,
+		dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (pdev->phy == NULL)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&pdev->device.channels);
+
+	if (irq_num != dma_channels) {
+		/* all chan share one irq, demux inside */
+		irq = platform_get_irq(op, 0);
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < dma_channels; i++) {
+		irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
+		ret = mmp_pdma_chan_init(pdev, i, irq);
+		if (ret)
+			return ret;
+	}
+
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	pdev->device.dev = &op->dev;
+	pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
+	pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
+	pdev->device.device_tx_status = mmp_pdma_tx_status;
+	pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
+	pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
+	pdev->device.device_issue_pending = mmp_pdma_issue_pending;
+	pdev->device.device_control = mmp_pdma_control;
+	pdev->device.copy_align = PDMA_ALIGNMENT;
+
+	if (pdev->dev->coherent_dma_mask)
+		dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
+	else
+		dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
+
+	ret = dma_async_device_register(&pdev->device);
+	if (ret) {
+		dev_err(pdev->device.dev, "unable to register\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct platform_device_id mmp_pdma_id_table[] = {
+	{ "mmp-pdma", },
+	{ },
+};
+
+static struct platform_driver mmp_pdma_driver = {
+	.driver		= {
+		.name	= "mmp-pdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = mmp_pdma_dt_ids,
+	},
+	.id_table	= mmp_pdma_id_table,
+	.probe		= mmp_pdma_probe,
+	.remove		= __devexit_p(mmp_pdma_remove),
+};
+
+module_platform_driver(mmp_pdma_driver);
+
+MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/mmp_dma.h b/include/linux/platform_data/mmp_dma.h
new file mode 100644
index 0000000..2a330ec
--- /dev/null
+++ b/include/linux/platform_data/mmp_dma.h
@@ -0,0 +1,19 @@
+/*
+ *  MMP Platform DMA Management
+ *
+ *  Copyright (c) 2011 Marvell Semiconductors Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#ifndef MMP_DMA_H
+#define MMP_DMA_H
+
+struct mmp_dma_platdata {
+	int dma_channels;
+};
+
+#endif /* MMP_DMA_H */
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug  7 23:14:59 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Wed,  8 Aug 2012 11:14:59 +0800
Subject: [PATCH v2 2/4] dmaengine: mmp_tdma: add dt support
In-Reply-To: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344395701-30888-3-git-send-email-zhangfei.gao@marvell.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   30 ++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +++++++++++++--------
 2 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
index 3c85583..91c60a5 100644
--- a/Documentation/devicetree/bindings/dma/mmp-dma.txt
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -43,3 +43,33 @@ pdma: dma-controller at d4000000 {
 	      dma-channels = <16>;
       };
 
+
+Marvell Two Channel DMA Controller used specifically for audio
+Used platfroms: pxa688, pxa910
+
+Required properties:
+- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for dma device
+
+"marvell,adma-1.0" used on pxa688
+"marvell,pxa910-squ" used on pxa910
+
+Examples:
+
+/* each channel has specific irq */
+adma0: dma-controller at d42a0800 {
+	      compatible = "marvell,adma-1.0";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <18 19>;
+	      interrupt-parent = <&intcmux32>;
+      };
+
+/* One irq for all channels */
+squ: dma-controller at d42a0800 {
+	      compatible = "marvell,pxa910-squ";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <46>;
+      };
+
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
index 8a15cf2..b93d73c 100644
--- a/drivers/dma/mmp_tdma.c
+++ b/drivers/dma/mmp_tdma.c
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <mach/regs-icu.h>
 #include <mach/sram.h>
+#include <linux/of_device.h>
 
 #include "dmaengine.h"
 
@@ -127,7 +128,6 @@ struct mmp_tdma_device {
 	void __iomem			*base;
 	struct dma_device		device;
 	struct mmp_tdma_chan		*tdmac[TDMA_CHANNEL_NUM];
-	int				irq;
 };
 
 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
@@ -492,7 +492,7 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 		return -ENOMEM;
 	}
 	if (irq)
-		tdmac->irq = irq + idx;
+		tdmac->irq = irq;
 	tdmac->dev	   = tdev->dev;
 	tdmac->chan.device = &tdev->device;
 	tdmac->idx	   = idx;
@@ -505,34 +505,43 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 	/* add the channel to tdma_chan list */
 	list_add_tail(&tdmac->chan.device_node,
 			&tdev->device.channels);
-
 	return 0;
 }
 
+static struct of_device_id mmp_tdma_dt_ids[] = {
+	{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
+	{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
+
 static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 {
-	const struct platform_device_id *id = platform_get_device_id(pdev);
-	enum mmp_tdma_type type = id->driver_data;
+	enum mmp_tdma_type type;
+	const struct of_device_id *of_id;
 	struct mmp_tdma_device *tdev;
 	struct resource *iores;
 	int i, ret;
-	int irq = 0;
+	int irq = 0, irq_num = 0;
 	int chan_num = TDMA_CHANNEL_NUM;
 
+	of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
+	if (of_id)
+		type = (enum mmp_tdma_type) of_id->data;
+	else
+		type = platform_get_device_id(pdev)->driver_data;
+
 	/* always have couple channels */
 	tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
 	if (!tdev)
 		return -ENOMEM;
 
 	tdev->dev = &pdev->dev;
-	iores = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!iores)
-		return -EINVAL;
 
-	if (resource_size(iores) != chan_num)
-		tdev->irq = iores->start;
-	else
-		irq = iores->start;
+	for (i = 0; i < chan_num; i++) {
+		if (platform_get_irq(pdev, i) > 0)
+			irq_num++;
+	}
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iores)
@@ -542,25 +551,26 @@ static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 	if (!tdev->base)
 		return -EADDRNOTAVAIL;
 
-	if (tdev->irq) {
-		ret = devm_request_irq(&pdev->dev, tdev->irq,
+	INIT_LIST_HEAD(&tdev->device.channels);
+
+	if (irq_num != chan_num) {
+		irq = platform_get_irq(pdev, 0);
+		ret = devm_request_irq(&pdev->dev, irq,
 			mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
 		if (ret)
 			return ret;
 	}
 
-	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
-	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
-
-	INIT_LIST_HEAD(&tdev->device.channels);
-
 	/* initialize channel parameters */
 	for (i = 0; i < chan_num; i++) {
+		irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
 		ret = mmp_tdma_chan_init(tdev, i, irq, type);
 		if (ret)
 			return ret;
 	}
 
+	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
+	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
 	tdev->device.dev = &pdev->dev;
 	tdev->device.device_alloc_chan_resources =
 					mmp_tdma_alloc_chan_resources;
@@ -595,6 +605,7 @@ static struct platform_driver mmp_tdma_driver = {
 	.driver		= {
 		.name	= "mmp-tdma",
 		.owner  = THIS_MODULE,
+		.of_match_table = mmp_tdma_dt_ids,
 	},
 	.id_table	= mmp_tdma_id_table,
 	.probe		= mmp_tdma_probe,
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug  7 23:15:00 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Wed,  8 Aug 2012 11:15:00 +0800
Subject: [PATCH v2 3/4] dmatest: add dmaengine_slave_config for DMA_MEMCPY
In-Reply-To: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344395701-30888-4-git-send-email-zhangfei.gao@marvell.com>

Set direction to DMA_MEM_TO_MEM
DMA driver may require such configure info

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 drivers/dma/dmatest.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 24225f0..73bab68 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -261,6 +261,9 @@ static int dmatest_func(void *data)
 	int			src_cnt;
 	int			dst_cnt;
 	int			i;
+	struct dma_slave_config conf = {
+		.direction = DMA_MEM_TO_MEM,
+	};
 
 	thread_name = current->comm;
 	set_freezable();
@@ -361,6 +364,7 @@ static int dmatest_func(void *data)
 						     DMA_BIDIRECTIONAL);
 		}
 
+		dmaengine_slave_config(chan, &conf);
 
 		if (thread->type == DMA_MEMCPY)
 			tx = dev->device_prep_dma_memcpy(chan,
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug  7 23:15:01 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Wed,  8 Aug 2012 11:15:01 +0800
Subject: [PATCH v2 4/4] mtd: pxa3xx-nand: replace pxa_request_dma with
 dmaengine
In-Reply-To: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344395701-30888-5-git-send-email-zhangfei.gao@marvell.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  113 ++++++++++++++++++++++------------------
 1 files changed, 63 insertions(+), 50 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c5ea313..2768826 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,8 +22,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
+#include <linux/dmaengine.h>
 
-#include <mach/dma.h>
 #include <plat/pxa3xx_nand.h>
 
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
@@ -162,8 +162,7 @@ struct pxa3xx_nand_info {
 	unsigned char		*data_buff;
 	unsigned char		*oob_buff;
 	dma_addr_t 		data_buff_phys;
-	int 			data_dma_ch;
-	struct pxa_dma_desc	*data_desc;
+	struct dma_chan		*data_dma_ch;
 	dma_addr_t 		data_desc_addr;
 
 	struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
@@ -332,14 +331,6 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 	nand_writel(info, NDSR, NDSR_MASK);
 }
 
-static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
-{
-	uint32_t ndcr;
-
-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~int_mask);
-}
-
 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 {
 	uint32_t ndcr;
@@ -372,24 +363,38 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
 	}
 }
 
+static void dma_complete_func(void *data)
+{
+	struct pxa3xx_nand_info *info = data;
+
+	info->state = STATE_DMA_DONE;
+}
+
 static void start_data_dma(struct pxa3xx_nand_info *info)
 {
-	struct pxa_dma_desc *desc = info->data_desc;
+	struct dma_device *dma_dev;
+	struct dma_async_tx_descriptor *tx = NULL;
+	dma_addr_t dma_src_addr, dma_dst_addr;
+	dma_cookie_t cookie;
 	int dma_len = ALIGN(info->data_size + info->oob_size, 32);
+	struct dma_slave_config conf;
 
-	desc->ddadr = DDADR_STOP;
-	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
+	dma_dev = info->data_dma_ch->device;
 
 	switch (info->state) {
 	case STATE_DMA_WRITING:
-		desc->dsadr = info->data_buff_phys;
-		desc->dtadr = info->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
+		dma_src_addr = info->data_buff_phys;
+		dma_dst_addr = info->mmio_phys + NDDB;
+		conf.direction = DMA_MEM_TO_DEV;
+		conf.dst_maxburst = 32;
+		conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	case STATE_DMA_READING:
-		desc->dtadr = info->data_buff_phys;
-		desc->dsadr = info->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
+		dma_src_addr = info->mmio_phys + NDDB;
+		dma_dst_addr = info->data_buff_phys;
+		conf.direction = DMA_DEV_TO_MEM;
+		conf.src_maxburst = 32;
+		conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	default:
 		dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
@@ -397,26 +402,27 @@ static void start_data_dma(struct pxa3xx_nand_info *info)
 		BUG();
 	}
 
-	DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
-	DDADR(info->data_dma_ch) = info->data_desc_addr;
-	DCSR(info->data_dma_ch) |= DCSR_RUN;
-}
-
-static void pxa3xx_nand_data_dma_irq(int channel, void *data)
-{
-	struct pxa3xx_nand_info *info = data;
-	uint32_t dcsr;
+	conf.slave_id = info->drcmr_dat;
+	dmaengine_slave_config(info->data_dma_ch, &conf);
+	tx = dma_dev->device_prep_dma_memcpy(info->data_dma_ch, dma_dst_addr,
+					     dma_src_addr, dma_len, 0);
+	if (!tx) {
+		dev_err(&info->pdev->dev, "Failed to prepare DMA memcpy\n");
+		return;
+	}
 
-	dcsr = DCSR(channel);
-	DCSR(channel) = dcsr;
+	tx->callback = dma_complete_func;
+	tx->callback_param = info;
 
-	if (dcsr & DCSR_BUSERR) {
-		info->retcode = ERR_DMABUSERR;
+	cookie = tx->tx_submit(tx);
+	if (dma_submit_error(cookie)) {
+		dev_err(&info->pdev->dev, "Failed to do DMA tx_submit\n");
+		return;
 	}
 
-	info->state = STATE_DMA_DONE;
-	enable_int(info, NDCR_INT_MASK);
-	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
+	dma_async_issue_pending(info->data_dma_ch);
+
+	return;
 }
 
 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
@@ -434,6 +440,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	}
 
 	status = nand_readl(info, NDSR);
+	nand_writel(info, NDSR, status);
 
 	if (status & NDSR_DBERR)
 		info->retcode = ERR_DBERR;
@@ -442,7 +449,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 		/* whether use dma to transfer data */
 		if (info->use_dma) {
-			disable_int(info, NDCR_INT_MASK);
 			info->state = (status & NDSR_RDDREQ) ?
 				      STATE_DMA_READING : STATE_DMA_WRITING;
 			start_data_dma(info);
@@ -757,6 +763,9 @@ static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
+	if (len > mtd->oobsize)
+		info->use_dma = use_dma;
+
 	memcpy(buf, info->data_buff + info->buf_start, real_len);
 	info->buf_start += real_len;
 }
@@ -768,6 +777,9 @@ static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
+	if (len > mtd->oobsize)
+		info->use_dma = use_dma;
+
 	memcpy(info->data_buff + info->buf_start, buf, real_len);
 	info->buf_start += real_len;
 }
@@ -886,7 +898,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 {
 	struct platform_device *pdev = info->pdev;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
+	dma_cap_mask_t mask;
 
 	if (use_dma == 0) {
 		info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
@@ -902,19 +914,20 @@ static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 		return -ENOMEM;
 	}
 
-	info->data_desc = (void *)info->data_buff + data_desc_offset;
-	info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 
-	info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
-				pxa3xx_nand_data_dma_irq, info);
-	if (info->data_dma_ch < 0) {
-		dev_err(&pdev->dev, "failed to request data dma\n");
-		dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-				info->data_buff, info->data_buff_phys);
-		return info->data_dma_ch;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_MEMCPY, mask);
+	info->data_dma_ch = dma_request_channel(mask, NULL, NULL);
+	if (!info->data_dma_ch) {
+		dev_info(&pdev->dev, "Failed to request DMA channel\n");
+		goto dma_request_fail;
 	}
-
 	return 0;
+
+dma_request_fail:
+	dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			info->data_buff, info->data_buff_phys);
+	return -EAGAIN;
 }
 
 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
@@ -1149,7 +1162,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
 fail_free_buf:
 	free_irq(irq, info);
 	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
+		dma_release_channel(info->data_dma_ch);
 		dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 			info->data_buff, info->data_buff_phys);
 	} else
@@ -1183,7 +1196,7 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
 	if (irq >= 0)
 		free_irq(irq, info);
 	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
+		dma_release_channel(info->data_dma_ch);
 		dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
 				info->data_buff, info->data_buff_phys);
 	} else
-- 
1.7.1



From thomas.abraham at linaro.org  Tue Aug  7 23:38:50 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 8 Aug 2012 09:08:50 +0530
Subject: [PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common
 Exynos4
In-Reply-To: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344366398-19022-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAJuYYwRT+Qjg6KSFP0DNHLjek59uoZyge-Fdr=7pqpS7Ej-TsQ@mail.gmail.com>

On 8 August 2012 00:36, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch creates a DTS file, exynos4.dtsi, for Exynos4210/4x12 and it
> describes common device nodes. SoC specific device nodes are described in
> another DTS file derived from this, exynos4210.dtsi and exynos4412.dtsi.
>
> exynos4412.dtsi is added new for Exynos4412 as well as exynos4210 is modified
> for Exynos4210 specific device nodes.
>
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4.dtsi    |  404 +++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi |  374 +---------------------------------
>  arch/arm/boot/dts/exynos4412.dtsi |  104 ++++++++++
>  3 files changed, 510 insertions(+), 372 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos4.dtsi
>  create mode 100644 arch/arm/boot/dts/exynos4412.dtsi
>
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> new file mode 100644
> index 0000000..ffda13e
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -0,0 +1,404 @@
> +/*
> + * Samsung's Exynos4210 SoC device tree source
> + *
> + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2010-2011 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
> + * based board files can include this file and provide values for board specfic
> + * bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
> + * nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +       compatible = "samsung,exynos4";
> +       interrupt-parent = <&gic>;
> +
> +       aliases {
> +               spi0 = &spi_0;
> +               spi1 = &spi_1;
> +               spi2 = &spi_2;
> +       };
> +
> +       gic:interrupt-controller at 10490000 {
> +               compatible = "arm,cortex-a9-gic";
> +               #interrupt-cells = <3>;
> +               interrupt-controller;
> +               cpu-offset = <0x8000>;

Since cpu-offset is SoC specific, this property can be moved into SoC
specific dtsi file. Or we could have it here and use 0x8000 as the
default value. I incline towards making this property SoC specific.

> +               reg = <0x10490000 0x1000>, <0x10480000 0x100>;
> +       };
> +
> +       combiner:interrupt-controller at 10440000 {
> +               compatible = "samsung,exynos4210-combiner";
> +               #interrupt-cells = <2>;
> +               interrupt-controller;
> +               reg = <0x10440000 0x1000>;
> +               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> +                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> +                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> +                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
> +       };


For combiner, the list of interrupts can be SoC speicifc. Exynos4412
has four more combiner groups and hence the list of interrupts can be
made SoC specific.

> +
> +       watchdog at 10060000 {
> +               compatible = "samsung,s3c2410-wdt";
> +               reg = <0x10060000 0x100>;
> +               interrupts = <0 43 0>;
> +       };
> +
> +       rtc at 10070000 {
> +               compatible = "samsung,s3c6410-rtc";
> +               reg = <0x10070000 0x100>;
> +               interrupts = <0 44 0>, <0 45 0>;
> +       };
> +
> +       keypad at 100A0000 {
> +               compatible = "samsung,s5pv210-keypad";
> +               reg = <0x100A0000 0x100>;
> +               interrupts = <0 109 0>;
> +       };
> +
> +       sdhci at 12510000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12510000 0x100>;
> +               interrupts = <0 73 0>;
> +       };
> +
> +       sdhci at 12520000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12520000 0x100>;
> +               interrupts = <0 74 0>;
> +       };
> +
> +       sdhci at 12530000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12530000 0x100>;
> +               interrupts = <0 75 0>;
> +       };
> +
> +       sdhci at 12540000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12540000 0x100>;
> +               interrupts = <0 76 0>;
> +       };
> +
> +       serial at 13800000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13800000 0x100>;
> +               interrupts = <0 52 0>;
> +       };
> +
> +       serial at 13810000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13810000 0x100>;
> +               interrupts = <0 53 0>;
> +       };
> +
> +       serial at 13820000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13820000 0x100>;
> +               interrupts = <0 54 0>;
> +       };
> +
> +       serial at 13830000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13830000 0x100>;
> +               interrupts = <0 55 0>;
> +       };
> +
> +       i2c at 13860000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13860000 0x100>;
> +               interrupts = <0 58 0>;
> +       };
> +
> +       i2c at 13870000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13870000 0x100>;
> +               interrupts = <0 59 0>;
> +       };
> +
> +       i2c at 13880000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13880000 0x100>;
> +               interrupts = <0 60 0>;
> +       };
> +
> +       i2c at 13890000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13890000 0x100>;
> +               interrupts = <0 61 0>;
> +       };
> +
> +       i2c at 138A0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138A0000 0x100>;
> +               interrupts = <0 62 0>;
> +       };
> +
> +       i2c at 138B0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138B0000 0x100>;
> +               interrupts = <0 63 0>;
> +       };
> +
> +       i2c at 138C0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138C0000 0x100>;
> +               interrupts = <0 64 0>;
> +       };
> +
> +       i2c at 138D0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138D0000 0x100>;
> +               interrupts = <0 65 0>;
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13920000 0x100>;
> +               interrupts = <0 66 0>;
> +               tx-dma-channel = <&pdma0 7>; /* preliminary */
> +               rx-dma-channel = <&pdma0 6>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13930000 0x100>;
> +               interrupts = <0 67 0>;
> +               tx-dma-channel = <&pdma1 7>; /* preliminary */
> +               rx-dma-channel = <&pdma1 6>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13940000 0x100>;
> +               interrupts = <0 68 0>;
> +               tx-dma-channel = <&pdma0 9>; /* preliminary */
> +               rx-dma-channel = <&pdma0 8>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       amba {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "arm,amba-bus";
> +               interrupt-parent = <&gic>;
> +               ranges;
> +
> +               pdma0: pdma at 12680000 {
> +                       compatible = "arm,pl330", "arm,primecell";
> +                       reg = <0x12680000 0x1000>;
> +                       interrupts = <0 35 0>;
> +               };
> +
> +               pdma1: pdma at 12690000 {
> +                       compatible = "arm,pl330", "arm,primecell";
> +                       reg = <0x12690000 0x1000>;
> +                       interrupts = <0 36 0>;
> +               };
> +       };
> +
> +
> +       gpio-controllers {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               gpio-controller;
> +               ranges;
> +
> +               gpa0: gpio-controller at 11400000 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400000 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpa1: gpio-controller at 11400020 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400020 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpb: gpio-controller at 11400040 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400040 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpc0: gpio-controller at 11400060 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400060 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpc1: gpio-controller at 11400080 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400080 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpd0: gpio-controller at 114000A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114000A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpd1: gpio-controller at 114000C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114000C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf0: gpio-controller at 11400180 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400180 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf1: gpio-controller at 114001A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf2: gpio-controller at 114001C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf3: gpio-controller at 114001E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk0: gpio-controller at 11000040 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000040 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk1: gpio-controller at 11000060 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000060 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk2: gpio-controller at 11000080 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000080 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk3: gpio-controller at 110000A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl0: gpio-controller at 110000C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl1: gpio-controller at 110000E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl2: gpio-controller at 11000100 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000100 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy0: gpio-controller at 11000120 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000120 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy1: gpio-controller at 11000140 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000140 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy2: gpio-controller at 11000160 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000160 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy3: gpio-controller at 11000180 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000180 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy4: gpio-controller at 110001A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy5: gpio-controller at 110001C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy6: gpio-controller at 110001E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx0: gpio-controller at 11000C00 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C00 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx1: gpio-controller at 11000C20 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C20 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx2: gpio-controller at 11000C40 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C40 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx3: gpio-controller at 11000C60 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C60 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpz: gpio-controller at 03860000 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x03860000 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +       };
> +};
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 02891fe..d41d9de 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -19,249 +19,16 @@
>   * published by the Free Software Foundation.
>  */
>
> -/include/ "skeleton.dtsi"
> +/include/ "exynos4.dtsi"
>
>  / {
>         compatible = "samsung,exynos4210";
> -       interrupt-parent = <&gic>;
> -
> -       aliases {
> -               spi0 = &spi_0;
> -               spi1 = &spi_1;
> -               spi2 = &spi_2;
> -       };
>
>         gic:interrupt-controller at 10490000 {
> -               compatible = "arm,cortex-a9-gic";
> -               #interrupt-cells = <3>;
> -               interrupt-controller;
>                 cpu-offset = <0x8000>;
> -               reg = <0x10490000 0x1000>, <0x10480000 0x100>;
> -       };
> -
> -       combiner:interrupt-controller at 10440000 {
> -               compatible = "samsung,exynos4210-combiner";
> -               #interrupt-cells = <2>;
> -               interrupt-controller;
> -               reg = <0x10440000 0x1000>;
> -               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> -                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> -                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> -                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
> -       };
> -
> -       watchdog at 10060000 {
> -               compatible = "samsung,s3c2410-wdt";
> -               reg = <0x10060000 0x100>;
> -               interrupts = <0 43 0>;
> -       };
> -
> -       rtc at 10070000 {
> -               compatible = "samsung,s3c6410-rtc";
> -               reg = <0x10070000 0x100>;
> -               interrupts = <0 44 0>, <0 45 0>;
> -       };
> -
> -       keypad at 100A0000 {
> -               compatible = "samsung,s5pv210-keypad";
> -               reg = <0x100A0000 0x100>;
> -               interrupts = <0 109 0>;
> -       };
> -
> -       sdhci at 12510000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12510000 0x100>;
> -               interrupts = <0 73 0>;
> -       };
> -
> -       sdhci at 12520000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12520000 0x100>;
> -               interrupts = <0 74 0>;
> -       };
> -
> -       sdhci at 12530000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12530000 0x100>;
> -               interrupts = <0 75 0>;
> -       };
> -
> -       sdhci at 12540000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12540000 0x100>;
> -               interrupts = <0 76 0>;
> -       };
> -
> -       serial at 13800000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13800000 0x100>;
> -               interrupts = <0 52 0>;
> -       };
> -
> -       serial at 13810000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13810000 0x100>;
> -               interrupts = <0 53 0>;
> -       };
> -
> -       serial at 13820000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13820000 0x100>;
> -               interrupts = <0 54 0>;
> -       };
> -
> -       serial at 13830000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13830000 0x100>;
> -               interrupts = <0 55 0>;
> -       };
> -
> -       i2c at 13860000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13860000 0x100>;
> -               interrupts = <0 58 0>;
> -       };
> -
> -       i2c at 13870000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13870000 0x100>;
> -               interrupts = <0 59 0>;
> -       };
> -
> -       i2c at 13880000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13880000 0x100>;
> -               interrupts = <0 60 0>;
> -       };
> -
> -       i2c at 13890000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13890000 0x100>;
> -               interrupts = <0 61 0>;
> -       };
> -
> -       i2c at 138A0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138A0000 0x100>;
> -               interrupts = <0 62 0>;
> -       };
> -
> -       i2c at 138B0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138B0000 0x100>;
> -               interrupts = <0 63 0>;
> -       };
> -
> -       i2c at 138C0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138C0000 0x100>;
> -               interrupts = <0 64 0>;
> -       };
> -
> -       i2c at 138D0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138D0000 0x100>;
> -               interrupts = <0 65 0>;
> -       };
> -
> -       spi_0: spi at 13920000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13920000 0x100>;
> -               interrupts = <0 66 0>;
> -               tx-dma-channel = <&pdma0 7>; /* preliminary */
> -               rx-dma-channel = <&pdma0 6>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       spi_1: spi at 13930000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13930000 0x100>;
> -               interrupts = <0 67 0>;
> -               tx-dma-channel = <&pdma1 7>; /* preliminary */
> -               rx-dma-channel = <&pdma1 6>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       spi_2: spi at 13940000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13940000 0x100>;
> -               interrupts = <0 68 0>;
> -               tx-dma-channel = <&pdma0 9>; /* preliminary */
> -               rx-dma-channel = <&pdma0 8>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       amba {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               compatible = "arm,amba-bus";
> -               interrupt-parent = <&gic>;
> -               ranges;
> -
> -               pdma0: pdma at 12680000 {
> -                       compatible = "arm,pl330", "arm,primecell";
> -                       reg = <0x12680000 0x1000>;
> -                       interrupts = <0 35 0>;
> -               };
> -
> -               pdma1: pdma at 12690000 {
> -                       compatible = "arm,pl330", "arm,primecell";
> -                       reg = <0x12690000 0x1000>;
> -                       interrupts = <0 36 0>;
> -               };
>         };
>
>         gpio-controllers {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               gpio-controller;
> -               ranges;
> -
> -               gpa0: gpio-controller at 11400000 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400000 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpa1: gpio-controller at 11400020 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400020 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpb: gpio-controller at 11400040 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400040 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpc0: gpio-controller at 11400060 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400060 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpc1: gpio-controller at 11400080 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400080 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpd0: gpio-controller at 114000A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114000A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpd1: gpio-controller at 114000C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114000C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
>                 gpe0: gpio-controller at 114000E0 {
>                         compatible = "samsung,exynos4-gpio";
>                         reg = <0x114000E0 0x20>;
> @@ -292,30 +59,6 @@
>                         #gpio-cells = <4>;
>                 };
>
> -               gpf0: gpio-controller at 11400180 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400180 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf1: gpio-controller at 114001A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf2: gpio-controller at 114001C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf3: gpio-controller at 114001E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
>                 gpj0: gpio-controller at 11000000 {
>                         compatible = "samsung,exynos4-gpio";
>                         reg = <0x11000000 0x20>;
> @@ -327,119 +70,6 @@
>                         reg = <0x11000020 0x20>;
>                         #gpio-cells = <4>;
>                 };
> -
> -               gpk0: gpio-controller at 11000040 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000040 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk1: gpio-controller at 11000060 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000060 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk2: gpio-controller at 11000080 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000080 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk3: gpio-controller at 110000A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl0: gpio-controller at 110000C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl1: gpio-controller at 110000E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl2: gpio-controller at 11000100 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000100 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy0: gpio-controller at 11000120 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000120 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy1: gpio-controller at 11000140 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000140 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy2: gpio-controller at 11000160 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000160 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy3: gpio-controller at 11000180 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000180 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy4: gpio-controller at 110001A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy5: gpio-controller at 110001C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy6: gpio-controller at 110001E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx0: gpio-controller at 11000C00 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C00 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx1: gpio-controller at 11000C20 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C20 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx2: gpio-controller at 11000C40 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C40 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx3: gpio-controller at 11000C60 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C60 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpz: gpio-controller at 03860000 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x03860000 0x20>;
> -                       #gpio-cells = <4>;
> -               };
>         };
>  };
> +
> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
> new file mode 100644
> index 0000000..85ee3f8
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412.dtsi
> @@ -0,0 +1,104 @@
> +/*
> + * Samsung's Exynos4412 SoC device tree source
> + *
> + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2010-2011 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
> + * based board files can include this file and provide values for board specfic
> + * bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
> + * nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/include/ "exynos4.dtsi"
> +
> +/ {
> +       compatible = "samsung,exynos4412";
> +
> +       gic:interrupt-controller at 10490000 {
> +               cpu-offset = <0x4000>;
> +       };
> +
> +       gpio-controllers {
> +               gpj0: gpio-controller at 11400240 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400240 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpj1: gpio-controller at 11400260 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400260 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpm0: gpio-controller at 11000260 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000260 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpm1: gpio-controller at 11000280 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000280 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpm2: gpio-controller at 110002A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110002A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpm3: gpio-controller at 110002C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110002C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpm4: gpio-controller at 110002E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110002E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpv0: gpio-controller at 106E0000 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x106E0000 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpv1: gpio-controller at 106E0020 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x106E0020 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpv2: gpio-controller at 106E0060 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x106E0060 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpv3: gpio-controller at 106E0080 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x106E0080 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpv4: gpio-controller at 106E00C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x106E00C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +       };
> +};

It is fine to list the gpio bank nodes here but for these nodes to be
usable, the corresponding support for Exynos4412 gpio has to be added
in the samsung gpio driver.

Thanks,
Thomas.

> --
> 1.7.9.5
>


From thomas.abraham at linaro.org  Tue Aug  7 23:47:23 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 8 Aug 2012 09:17:23 +0530
Subject: [PATCH 3/4] arm/dts: exynos4: Add DTS file for ODROID-X
In-Reply-To: <1344366725-19153-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344366725-19153-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAJuYYwTp00RohqKkF6+4yxq3bqW1O6NWkab29PuyEUPYTjeqgw@mail.gmail.com>

On 8 August 2012 00:42, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
> gpios base.
>
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
>  1 file changed, 148 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts
>
> diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
> new file mode 100644
> index 0000000..b0a892b
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
> @@ -0,0 +1,148 @@
> +/*
> + * Samsung's Exynos4210 based Origen board device tree source
> + *
> + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2010-2011 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Device tree source file for Insignal's Origen board which is based on
> + * Samsung's Exynos4210 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos4412.dtsi"
> +/include/ "max77686.dtsi"
> +
> +/ {
> +       model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
> +       compatible = "hardkernel,odroidx", "samsung,exynos4412";

The compatible value "samsung,exynos4412" can be added to the
compatible list in mach-exynos4-dt.c file. Otherwise, this looks fine.

Thanks,
Thomas.

> +
> +       memory {
> +               reg = <0x40000000 0x40000000>;
> +       };
> +
> +       chosen {
> +               bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
> +       };
> +
> +       /* sdhci0 */
> +       sdhci at 12510000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci1 */
> +       sdhci at 12520000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci2 */
> +       sdhci at 12530000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk2 2 2 3 3>;
> +               gpios = <&gpk2 0 2 0 3>,
> +                       <&gpk2 1 2 0 3>,
> +                       <&gpk2 3 2 3 3>,
> +                       <&gpk2 4 2 3 3>,
> +                       <&gpk2 5 2 3 3>,
> +                       <&gpk2 6 2 3 3>;
> +       };
> +
> +       /* sdhci3 */
> +       sdhci at 12540000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk3 2 2 3 3>;
> +               gpios = <&gpk3 0 2 0 3>,
> +                       <&gpk3 1 2 0 3>,
> +                       <&gpk3 3 2 3 3>,
> +                       <&gpk3 4 2 3 3>,
> +                       <&gpk3 5 2 3 3>,
> +                       <&gpk3 6 2 3 3>;
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led1 {
> +                       label   = "led1";
> +                       gpios   = <&gpc1 0 1 0x10000 0>;
> +                       linux,default-trigger   = "oneshot";
> +                       default-state   = "off";
> +               };
> +
> +               led2 {
> +                       label   = "led2";
> +                       gpios   = <&gpc1 2 1 0x10000 0>;
> +                       linux,default-trigger   = "heartbeat";
> +               };
> +       };
> +
> +       i2c at 13860000 {  /* i2c0 */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               gpios = <&gpd1 0 2 0 0>,
> +                       <&gpd1 1 2 0 0>;
> +               pmic at 9 {
> +                       compatible = "maxim,max77686";
> +                       reg = <9>;
> +               };
> +       };
> +
> +       i2c at 13870000 {  /* i2c1 */
> +               status = "disabled";
> +               gpios = <&gpd1 2 2 0 0>,
> +                       <&gpd1 3 2 0 0>;
> +       };
> +
> +       i2c at 13880000 {  /* i2c2 */
> +               status = "disabled";
> +               gpios = <&gpa0 6 2 0 0>,
> +                       <&gpa0 7 2 0 0>;
> +       };
> +
> +       i2c at 13890000 {  /* i2c3 */
> +               status = "disabled";
> +               gpios = <&gpa1 2 2 0 0>,
> +                       <&gpa1 3 2 0 0>;
> +       };
> +
> +       i2c at 138A0000 {  /* i2c4 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138B0000 {  /* i2c5 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138C0000 {  /* i2c6 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138D0000 {  /* i2c7 */
> +               status = "disabled";
> +       };
> +
> +       keypad at 100A0000 {
> +               status = "disabled";
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               status = "disabled";
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               status = "disabled";
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               status = "disabled";
> +       };
> +};
> --
> 1.7.9.5
>


From sachin.kamat at linaro.org  Wed Aug  8 00:04:42 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed, 8 Aug 2012 09:34:42 +0530
Subject: [PATCH 3/4] arm/dts: exynos4: Add DTS file for ODROID-X
In-Reply-To: <1344366725-19153-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344366725-19153-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAK9yfHyc4Cc1JDCeyo38vHWtxzO28vVr=TDWq5UbWPf4_LVFoA@mail.gmail.com>

On 8 August 2012 00:42, Dongjin Kim <tobetter at gmail.com> wrote:
> This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
> gpios base.
>
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
>  1 file changed, 148 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts
>
> diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
> new file mode 100644
> index 0000000..b0a892b
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
> @@ -0,0 +1,148 @@
> +/*
> + * Samsung's Exynos4210 based Origen board device tree source
> + *
> + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2010-2011 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Device tree source file for Insignal's Origen board which is based on
> + * Samsung's Exynos4210 SoC.

Don't you think you need to update this header?


> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos4412.dtsi"
> +/include/ "max77686.dtsi"
> +
> +/ {
> +       model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
> +       compatible = "hardkernel,odroidx", "samsung,exynos4412";
> +
> +       memory {
> +               reg = <0x40000000 0x40000000>;
> +       };
> +
> +       chosen {
> +               bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
> +       };
> +
> +       /* sdhci0 */
> +       sdhci at 12510000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci1 */
> +       sdhci at 12520000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci2 */
> +       sdhci at 12530000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk2 2 2 3 3>;
> +               gpios = <&gpk2 0 2 0 3>,
> +                       <&gpk2 1 2 0 3>,
> +                       <&gpk2 3 2 3 3>,
> +                       <&gpk2 4 2 3 3>,
> +                       <&gpk2 5 2 3 3>,
> +                       <&gpk2 6 2 3 3>;
> +       };
> +
> +       /* sdhci3 */
> +       sdhci at 12540000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk3 2 2 3 3>;
> +               gpios = <&gpk3 0 2 0 3>,
> +                       <&gpk3 1 2 0 3>,
> +                       <&gpk3 3 2 3 3>,
> +                       <&gpk3 4 2 3 3>,
> +                       <&gpk3 5 2 3 3>,
> +                       <&gpk3 6 2 3 3>;
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led1 {
> +                       label   = "led1";
> +                       gpios   = <&gpc1 0 1 0x10000 0>;
> +                       linux,default-trigger   = "oneshot";
> +                       default-state   = "off";
> +               };
> +
> +               led2 {
> +                       label   = "led2";
> +                       gpios   = <&gpc1 2 1 0x10000 0>;
> +                       linux,default-trigger   = "heartbeat";
> +               };
> +       };
> +
> +       i2c at 13860000 {  /* i2c0 */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               gpios = <&gpd1 0 2 0 0>,
> +                       <&gpd1 1 2 0 0>;
> +               pmic at 9 {
> +                       compatible = "maxim,max77686";
> +                       reg = <9>;
> +               };
> +       };
> +
> +       i2c at 13870000 {  /* i2c1 */
> +               status = "disabled";
> +               gpios = <&gpd1 2 2 0 0>,
> +                       <&gpd1 3 2 0 0>;
> +       };
> +
> +       i2c at 13880000 {  /* i2c2 */
> +               status = "disabled";
> +               gpios = <&gpa0 6 2 0 0>,
> +                       <&gpa0 7 2 0 0>;
> +       };
> +
> +       i2c at 13890000 {  /* i2c3 */
> +               status = "disabled";
> +               gpios = <&gpa1 2 2 0 0>,
> +                       <&gpa1 3 2 0 0>;
> +       };
> +
> +       i2c at 138A0000 {  /* i2c4 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138B0000 {  /* i2c5 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138C0000 {  /* i2c6 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138D0000 {  /* i2c7 */
> +               status = "disabled";
> +       };
> +
> +       keypad at 100A0000 {
> +               status = "disabled";
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               status = "disabled";
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               status = "disabled";
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               status = "disabled";
> +       };
> +};
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



-- 
With warm regards,
Sachin


From kgene.kim at samsung.com  Wed Aug  8 01:01:19 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 14:01:19 +0900
Subject: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor
In-Reply-To: <b937n0skj9tqmbg6tctdu48x.1344324481459@email.android.com>
References: <1344261462-14183-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <1344261462-14183-2-git-send-email-dongjin.kim@agreeyamobility.net>
 <CAK9yfHz_q22JgkULR9V8bR5W_TXVRn5qs5u2MiJJpa-Br_YQUQ@mail.gmail.com>
 <b937n0skj9tqmbg6tctdu48x.1344324481459@email.android.com>
Message-ID: <0a6a01cd7522$d8d75160$8a85f420$%kim@samsung.com>

I applied the patches Sachin pointed out, so we could drop this patch.

Note, Dongjin, please don't use Korean character in your e-mail and keep
the new line for over 80 columns, actually 76 or 78? anyways.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Dongjin Kim wrote:
> 
> Hi Sachin,
> 
> Thanks for your feedback, I couldnt find the patch series eariler. ;)
> 
> Regards,
> Dongjin.
> 
> Sent from Moxier Mail
> (http://www.moxier.com)
> 
> 
> ----- ?? ??? -----
> ?? ??:Sachin Kamat <sachin.kamat at linaro.org> ?? ??:Dongjin Kim
> <tobetter at gmail.com> ??:Dongjin Kim <Dongjin.Kim at agreeyamobility.net>,
> Ben Dooks <ben-linux at fluff.org>, Kukjin Kim <kgene.kim at samsung.com>,
> Russell King <linux at arm.linux.org.uk>, "linux-arm-
> kernel at lists.infradead.org" <linux-arm-kernel at lists.infradead.org>,
> "linux-samsung-soc at vger.kernel.org" <linux-samsung-soc at vger.kernel.org>,
> "linux-kernel at vger.kernel.org" <linux-kernel at vger.kernel.org> ??
??:2012.
> 8. 7. 3:57 ??
> ??:Re: [PATCH] ARM: EXYNOS: Add HDMIPHY I2C adaptor
> 
> 
> 
> Hi Dongjin,
> 
> A patch series to add HDMI platform data support is already under
> consideration.
> 
> http://comments.gmane.org/gmane.linux.kernel.samsung-soc/11352
> 
[...]



From nico at fluxnic.net  Wed Aug  8 01:04:41 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 08 Aug 2012 01:04:41 -0400 (EDT)
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
 <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208080033410.5231@xanadu.home>

On Tue, 7 Aug 2012, Matt Sealey wrote:

> On Mon, Aug 6, 2012 at 7:08 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > On Mon, 6 Aug 2012, Matt Sealey wrote:
> >
> >> I don't have a real *problem* with it, I just think since the kernel
> >> can be compiled in both modes, but you may have some kind of remit to
> >> not run ARM code (even if it's just a couple instructions at the
> >> start) or some toolchain requirement or.. something.. it would be
> >> entirely the bootloader's job to determine what mode it is in when it
> >> jumps into the kernel. If you boot a Thumb bootloader and load an ARM
> >> kernel, you'll get a crash. If you boot an ARM bootloader and a Thumb
> >> kernel (with the current ARM instructions in head.S), you'll get a
> >> crash. This is well defined, perfectly obvious, and I realise that..
> >
> > And isn't it also rather silly?
> 
> No?
> 
> > History has told that the more "entirely the bootloader's job" we rely
> > on, the less reliable and interoperable we become.  Because you now have
> > to compile two kernels to fully validate your bootloader instead of only
> > one, and some people won't bother if the second kernel doesn't match
> > their own use case.
> 
> That is true from a testing standpoint, and I guess I do agree with 
> yourself and Russell in this regard. But I do also think the chain of 
> trust from the bootloader to kernel is important. I am in full violent 
> disagreement with the idea that doing pin mux change operations based 
> on a device tree description is both a necessity or a requirement in 
> Linux, especially as changing pin muxing this "late" in boot is 
> something a hardware designer would flip their lid over.
[...]

I don't think it is reasonable to defer every pin mux setup to the 
kernel.  The bootloader obviously has to set those things up.  However 
the bootloader is way gone when it is time to perform CPU idle 
and suspend and operations.  This is when the DT representation is most 
useful.

> Sure, on some boards this is a requirement because the bootloaders do 
> not do the right thing, but in actual fact some of these boards (MX51 
> Babbage, MX6 SabreLite for example) cannot boot a device tree from 
> their shipped bootloaders anyway. To boot these boards from device 
> tree you need to actually update U-Boot or provide another compatible, 
> capable bootloader, and in this case this support should actually be 
> provided in the bootloader (mux everything before the kernel is even 
> in memory, and you reduce your device tree sizes by a factor of 3).

I do not disagree with you here.

> The idea that Linux should reinitialize everything anyway just to be 
> sure is both redundant, and means you're slowing down boot times and 
> potentially causing odd behavior (electrically) on boards with reset 
> lines flailing around during a mux change, and GPIO directions 
> changing on the fly for no good reason.

But if Linux is re-initializing everything identically to the bootloader 
then the hardware should see a no-op, no?  In any case, I'm not the 
right person to discuss pinmux design issues.  If you have concerns 
about redundant initialization or similar issues then I strongly 
suggest you start a new thread to initiate a discussion on that.

> The device tree model has to imply some level of trust that the 
> configuration you have in the device tree is exactly what you get on 
> the board when the kernel has booted. If that means adding pinctrl 
> information to each device to make sure it is set up properly, then so 
> be it. That said..

Yes, this is diverging from the original topic.

> At Genesi we are proceeding with device tree support for all our platforms and
> operating from an assumption that since we control our bootloader (it is U-Boot
> after all, so not heavily..), we get to dictate what goes in our
> device tree and we
> will make a hard and fast stand against ANY pin mux changes going on inside the
> kernel. And you guys will have to trust that we sat down and spent weeks and
> weeks and weeks testing that this is actually the case before we committed
> anything.

Note that I previously opposed the idea of any hard linkage between the 
bootloader and the device tree content.  If you are spending so much 
time validating your DT, you might feel so confident as to not allow it 
to be updatable unless the whole bootloader is also updated.  And that's 
wrong.  Please make your DTB into a separate flash area, separate from 
the boot loader so it can easily be updated without any risk of breaking 
the device.  Just in case...

> Just because there is a ton of absolutely awful, broken firmware code out there
> doesn't mean it can and will always be the case, and Linux policy should not
> be dictated on an architecture basis on a few bad eggs, especially if it means
> developers in the big wide world have to jump through hoops. Surely it is just
> as good for Linux to loudly advocate the correct solutions in firmware and
> implement the workarounds anyway, like a device quirk, rather than just out and
> out say "firmwares suck, ignore what they did, do it again. We don't trust them
> and never will."

I hear your frustration.  I'm glad you take your firmware work 
seriously.  But unless and until everyone else is like you, the kernel 
has to work defensively.  That means not giving too much freedom to the 
bootloader in order to preserve good interoperability.  That certainly 
includes _not_ allowing variations in the processor mode for booting the 
kernel.


Nicolas


From tushar.behera at linaro.org  Wed Aug  8 01:13:27 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed,  8 Aug 2012 10:43:27 +0530
Subject: [RFC] ARM: SAMSUNG: Remove redundant return code from
 xxx_register_clock
Message-ID: <1344402807-1007-1-git-send-email-tushar.behera@linaro.org>

s3c24xx_register_clock(struct clk *clk) always returns 0, so checking
its return value has no meaning.

Making this function to return void would help us save quite a line of
code.

Need comment on whether this is the right approach.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/plat-samsung/clock.c              |   32 +++++----------------------
 arch/arm/plat-samsung/include/plat/clock.h |    4 +-
 2 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 65c5eca..c0d75d0 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -276,7 +276,7 @@ struct clk s3c24xx_uclk = {
  *
  * Add the specified clock to the list of clocks known by the system.
  */
-int s3c24xx_register_clock(struct clk *clk)
+void s3c24xx_register_clock(struct clk *clk)
 {
 	if (clk->enable == NULL)
 		clk->enable = clk_null_enable;
@@ -286,8 +286,6 @@ int s3c24xx_register_clock(struct clk *clk)
 	clk->lookup.con_id = clk->name;
 	clk->lookup.clk = clk;
 	clkdev_add(&clk->lookup);
-
-	return 0;
 }
 
 /**
@@ -298,20 +296,10 @@ int s3c24xx_register_clock(struct clk *clk)
  * Call s3c24xx_register_clock() for all the clock pointers contained
  * in the @clks list. Returns the number of failures.
  */
-int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
+void s3c24xx_register_clocks(struct clk **clks, int nr_clks)
 {
-	int fails = 0;
-
-	for (; nr_clks > 0; nr_clks--, clks++) {
-		if (s3c24xx_register_clock(*clks) < 0) {
-			struct clk *clk = *clks;
-			printk(KERN_ERR "%s: failed to register %p: %s\n",
-			       __func__, clk, clk->name);
-			fails++;
-		}
-	}
-
-	return fails;
+	for (; nr_clks > 0; nr_clks--, clks++)
+		s3c24xx_register_clock(*clks);
 }
 
 /**
@@ -324,16 +312,8 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
  */
 void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
 {
-	int ret;
-
-	for (; nr_clks > 0; nr_clks--, clkp++) {
-		ret = s3c24xx_register_clock(clkp);
-
-		if (ret < 0) {
-			printk(KERN_ERR "Failed to register clock %s (%d)\n",
-			       clkp->name, ret);
-		}
-	}
+	for (; nr_clks > 0; nr_clks--, clkp++)
+		s3c24xx_register_clock(clkp);
 }
 
 /**
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index a62753d..d646093 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -101,8 +101,8 @@ extern spinlock_t clocks_lock;
 
 extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
 
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
+extern void s3c24xx_register_clock(struct clk *clk);
+extern void s3c24xx_register_clocks(struct clk **clk, int nr_clks);
 
 extern void s3c_register_clocks(struct clk *clk, int nr_clks);
 extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
-- 
1.7.4.1



From tobetter at gmail.com  Wed Aug  8 01:32:01 2012
From: tobetter at gmail.com (tobetter at gmail.com)
Date: Wed,  8 Aug 2012 14:32:01 +0900
Subject: [PATCH v2] arm/dts: exynos4: Add DTS files derived from common Exynos4
In-Reply-To: <[PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common
 Exynos4>
References: <[PATCH 2/4] arm/dts: exynos4: Add DTS files derived from common
 Exynos4>
Message-ID: <1344403934-8348-1-git-send-email-dongjin.kim@agreeyamobility.net>

From: Dongjin Kim <dongjin.kim at agreeyamobility.net>

This patch creates a DTS file, exynos4.dtsi, for Exynos4210/4x12 and it
describes common device nodes. SoC specific device nodes are described in
another DTS file derived from this, exynos4210.dtsi and exynos4412.dtsi.

exynos4412.dtsi is added new for Exynos4412 as well as exynos4210 is modified
for Exynos4210 specific device nodes.

Changes in V2:
  -. Below are moved to SoC speicific dtsi file
     o. property 'cpu-offset' of gic node
     o. the list of interrupts of combiner node
  -. 4 more combiner groups are added to exynos4412.dtsi
  -. The compatible value "samsung,exynos4412" is added to mach-exynos4-dt.c

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/exynos4.dtsi         |  399 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi      |  366 +----------------------------
 arch/arm/boot/dts/exynos4412.dtsi      |  112 +++++++++
 arch/arm/mach-exynos/mach-exynos4-dt.c |    1 +
 4 files changed, 513 insertions(+), 365 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4.dtsi
 create mode 100644 arch/arm/boot/dts/exynos4412.dtsi

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 0000000..d7d33e5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,399 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos4";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		spi0 = &spi_0;
+		spi1 = &spi_1;
+		spi2 = &spi_2;
+	};
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x1000>;
+	};
+
+	watchdog at 10060000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x10060000 0x100>;
+		interrupts = <0 43 0>;
+	};
+
+	rtc at 10070000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x10070000 0x100>;
+		interrupts = <0 44 0>, <0 45 0>;
+	};
+
+	keypad at 100A0000 {
+		compatible = "samsung,s5pv210-keypad";
+		reg = <0x100A0000 0x100>;
+		interrupts = <0 109 0>;
+	};
+
+	sdhci at 12510000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12510000 0x100>;
+		interrupts = <0 73 0>;
+	};
+
+	sdhci at 12520000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12520000 0x100>;
+		interrupts = <0 74 0>;
+	};
+
+	sdhci at 12530000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12530000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12540000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12540000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	serial at 13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 13820000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13820000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	serial at 13830000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13830000 0x100>;
+		interrupts = <0 55 0>;
+	};
+
+	i2c at 13860000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13860000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 13870000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13870000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 13880000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13880000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 13890000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13890000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 138A0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138A0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 138B0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138B0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c at 138C0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138C0000 0x100>;
+		interrupts = <0 64 0>;
+	};
+
+	i2c at 138D0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138D0000 0x100>;
+		interrupts = <0 65 0>;
+	};
+
+	spi_0: spi at 13920000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13920000 0x100>;
+		interrupts = <0 66 0>;
+		tx-dma-channel = <&pdma0 7>; /* preliminary */
+		rx-dma-channel = <&pdma0 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_1: spi at 13930000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13930000 0x100>;
+		interrupts = <0 67 0>;
+		tx-dma-channel = <&pdma1 7>; /* preliminary */
+		rx-dma-channel = <&pdma1 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_2: spi at 13940000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13940000 0x100>;
+		interrupts = <0 68 0>;
+		tx-dma-channel = <&pdma0 9>; /* preliminary */
+		rx-dma-channel = <&pdma0 8>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 12680000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12680000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		pdma1: pdma at 12690000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12690000 0x1000>;
+			interrupts = <0 36 0>;
+		};
+	};
+
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf2: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf3: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk0: gpio-controller at 11000040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk1: gpio-controller at 11000060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk2: gpio-controller at 11000080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk3: gpio-controller at 110000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl0: gpio-controller at 110000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl1: gpio-controller at 110000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl2: gpio-controller at 11000100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 11000120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 11000140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 11000160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11000180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 110001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 110001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 110001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11000C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11000C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11000C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11000C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..00835f4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,249 +19,23 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
-	interrupt-parent = <&gic>;
-
-	aliases {
-		spi0 = &spi_0;
-		spi1 = &spi_1;
-		spi2 = &spi_2;
-	};
 
 	gic:interrupt-controller at 10490000 {
-		compatible = "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		interrupt-controller;
 		cpu-offset = <0x8000>;
-		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
 	};
 
 	combiner:interrupt-controller at 10440000 {
-		compatible = "samsung,exynos4210-combiner";
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0x10440000 0x1000>;
 		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
 			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 	};
 
-	watchdog at 10060000 {
-		compatible = "samsung,s3c2410-wdt";
-		reg = <0x10060000 0x100>;
-		interrupts = <0 43 0>;
-	};
-
-	rtc at 10070000 {
-		compatible = "samsung,s3c6410-rtc";
-		reg = <0x10070000 0x100>;
-		interrupts = <0 44 0>, <0 45 0>;
-	};
-
-	keypad at 100A0000 {
-		compatible = "samsung,s5pv210-keypad";
-		reg = <0x100A0000 0x100>;
-		interrupts = <0 109 0>;
-	};
-
-	sdhci at 12510000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12510000 0x100>;
-		interrupts = <0 73 0>;
-	};
-
-	sdhci at 12520000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12520000 0x100>;
-		interrupts = <0 74 0>;
-	};
-
-	sdhci at 12530000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12530000 0x100>;
-		interrupts = <0 75 0>;
-	};
-
-	sdhci at 12540000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12540000 0x100>;
-		interrupts = <0 76 0>;
-	};
-
-	serial at 13800000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13800000 0x100>;
-		interrupts = <0 52 0>;
-	};
-
-	serial at 13810000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13810000 0x100>;
-		interrupts = <0 53 0>;
-	};
-
-	serial at 13820000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13820000 0x100>;
-		interrupts = <0 54 0>;
-	};
-
-	serial at 13830000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13830000 0x100>;
-		interrupts = <0 55 0>;
-	};
-
-	i2c at 13860000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13860000 0x100>;
-		interrupts = <0 58 0>;
-	};
-
-	i2c at 13870000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13870000 0x100>;
-		interrupts = <0 59 0>;
-	};
-
-	i2c at 13880000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13880000 0x100>;
-		interrupts = <0 60 0>;
-	};
-
-	i2c at 13890000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13890000 0x100>;
-		interrupts = <0 61 0>;
-	};
-
-	i2c at 138A0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138A0000 0x100>;
-		interrupts = <0 62 0>;
-	};
-
-	i2c at 138B0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138B0000 0x100>;
-		interrupts = <0 63 0>;
-	};
-
-	i2c at 138C0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138C0000 0x100>;
-		interrupts = <0 64 0>;
-	};
-
-	i2c at 138D0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138D0000 0x100>;
-		interrupts = <0 65 0>;
-	};
-
-	spi_0: spi at 13920000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13920000 0x100>;
-		interrupts = <0 66 0>;
-		tx-dma-channel = <&pdma0 7>; /* preliminary */
-		rx-dma-channel = <&pdma0 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_1: spi at 13930000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13930000 0x100>;
-		interrupts = <0 67 0>;
-		tx-dma-channel = <&pdma1 7>; /* preliminary */
-		rx-dma-channel = <&pdma1 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_2: spi at 13940000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13940000 0x100>;
-		interrupts = <0 68 0>;
-		tx-dma-channel = <&pdma0 9>; /* preliminary */
-		rx-dma-channel = <&pdma0 8>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	amba {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "arm,amba-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		pdma0: pdma at 12680000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12680000 0x1000>;
-			interrupts = <0 35 0>;
-		};
-
-		pdma1: pdma at 12690000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12690000 0x1000>;
-			interrupts = <0 36 0>;
-		};
-	};
-
 	gpio-controllers {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		gpio-controller;
-		ranges;
-
-		gpa0: gpio-controller at 11400000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400000 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpa1: gpio-controller at 11400020 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400020 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpb: gpio-controller at 11400040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc0: gpio-controller at 11400060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc1: gpio-controller at 11400080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd0: gpio-controller at 114000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd1: gpio-controller at 114000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpe0: gpio-controller at 114000E0 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x114000E0 0x20>;
@@ -292,30 +66,6 @@
 			#gpio-cells = <4>;
 		};
 
-		gpf0: gpio-controller at 11400180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf1: gpio-controller at 114001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf2: gpio-controller at 114001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf3: gpio-controller at 114001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpj0: gpio-controller at 11000000 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x11000000 0x20>;
@@ -327,119 +77,5 @@
 			reg = <0x11000020 0x20>;
 			#gpio-cells = <4>;
 		};
-
-		gpk0: gpio-controller at 11000040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk1: gpio-controller at 11000060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk2: gpio-controller at 11000080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk3: gpio-controller at 110000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl0: gpio-controller at 110000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl1: gpio-controller at 110000E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl2: gpio-controller at 11000100 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000100 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy0: gpio-controller at 11000120 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000120 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy1: gpio-controller at 11000140 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000140 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy2: gpio-controller at 11000160 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000160 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy3: gpio-controller at 11000180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy4: gpio-controller at 110001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy5: gpio-controller at 110001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy6: gpio-controller at 110001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx0: gpio-controller at 11000C00 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C00 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx1: gpio-controller at 11000C20 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C20 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx2: gpio-controller at 11000C40 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C40 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx3: gpio-controller at 11000C60 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C60 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpz: gpio-controller at 03860000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x03860000 0x20>;
-			#gpio-cells = <4>;
-		};
 	};
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
new file mode 100644
index 0000000..e19c77f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -0,0 +1,112 @@
+/*
+ * Samsung's Exynos4412 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "exynos4.dtsi"
+
+/ {
+	compatible = "samsung,exynos4412";
+
+	gic:interrupt-controller at 10490000 {
+		cpu-offset = <0x4000>;
+	};
+
+	combiner:interrupt-controller at 10440000 {
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+			     <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
+	};
+
+	gpio-controllers {
+		gpj0: gpio-controller at 11400240 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400240 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpj1: gpio-controller at 11400260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm0: gpio-controller at 11000260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm1: gpio-controller at 11000280 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000280 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm2: gpio-controller at 110002A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm3: gpio-controller at 110002C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpm4: gpio-controller at 110002E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110002E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv0: gpio-controller at 106E0000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv1: gpio-controller at 106E0020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv2: gpio-controller at 106E0060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv3: gpio-controller at 106E0080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E0080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv4: gpio-controller at 106E00C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x106E00C0 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..66ed883 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -80,6 +80,7 @@ static void __init exynos4210_dt_machine_init(void)
 
 static char const *exynos4210_dt_compat[] __initdata = {
 	"samsung,exynos4210",
+	"samsung,exynos4412",
 	NULL
 };
 
-- 
1.7.9.5



From tobetter at gmail.com  Wed Aug  8 01:36:38 2012
From: tobetter at gmail.com (tobetter at gmail.com)
Date: Wed,  8 Aug 2012 14:36:38 +0900
Subject: [PATCH v2] arm/dts: exynos4: Add DTS file for ODROID-X
In-Reply-To: <[PATCH 3/4] arm/dts: exynos4: Add DTS file for ODROID-X>
References: <[PATCH 3/4] arm/dts: exynos4: Add DTS file for ODROID-X>
Message-ID: <1344404201-8641-1-git-send-email-dongjin.kim@agreeyamobility.net>

From: Dongjin Kim <dongjin.kim at agreeyamobility.net>

This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
gpios base.

Changes in V2:
    -. Banner changed

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 0000000..1b8a7f8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,148 @@
+/*
+ * Samsung's Exynos4210 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 AgreeYa Mobility Co., Ltd.
+ *		http://www.agreeyamobility.net
+ * Copyright (c) 2012 Hardkernel Co., Ltd.
+ *		http://www.hardkernel.com
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+/include/ "max77686.dtsi"
+
+/ {
+	model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
+	compatible = "hardkernel,odroidx", "samsung,exynos4412";
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
+	};
+
+	/* sdhci0 */
+	sdhci at 12510000 {
+		status = "disabled";
+	};
+
+	/* sdhci1 */
+	sdhci at 12520000 {
+		status = "disabled";
+	};
+
+	/* sdhci2 */
+	sdhci at 12530000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd = <&gpk2 2 2 3 3>;
+		gpios = <&gpk2 0 2 0 3>,
+			<&gpk2 1 2 0 3>,
+			<&gpk2 3 2 3 3>,
+			<&gpk2 4 2 3 3>,
+			<&gpk2 5 2 3 3>,
+			<&gpk2 6 2 3 3>;
+	};
+
+	/* sdhci3 */
+	sdhci at 12540000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd	= <&gpk3 2 2 3 3>;
+		gpios = <&gpk3 0 2 0 3>,
+			<&gpk3 1 2 0 3>,
+			<&gpk3 3 2 3 3>,
+			<&gpk3 4 2 3 3>,
+			<&gpk3 5 2 3 3>,
+			<&gpk3 6 2 3 3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1 {
+			label	= "led1";
+			gpios	= <&gpc1 0 1 0x10000 0>;
+			linux,default-trigger	= "oneshot";
+			default-state	= "off";
+		};
+
+		led2 {
+			label	= "led2";
+			gpios	= <&gpc1 2 1 0x10000 0>;
+			linux,default-trigger	= "heartbeat";
+		};
+	};
+
+	i2c at 13860000 {	/* i2c0 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpd1 0 2 0 0>,
+			<&gpd1 1 2 0 0>;
+		pmic at 9 {
+			compatible = "maxim,max77686";
+			reg = <9>;
+		};
+	};
+
+	i2c at 13870000 {	/* i2c1 */
+		status = "disabled";
+		gpios = <&gpd1 2 2 0 0>,
+			<&gpd1 3 2 0 0>;
+	};
+
+	i2c at 13880000 {	/* i2c2 */
+		status = "disabled";
+		gpios = <&gpa0 6 2 0 0>,
+			<&gpa0 7 2 0 0>;
+	};
+
+	i2c at 13890000 {	/* i2c3 */
+		status = "disabled";
+		gpios = <&gpa1 2 2 0 0>,
+			<&gpa1 3 2 0 0>;
+	};
+
+	i2c at 138A0000 {	/* i2c4 */
+		status = "disabled";
+	};
+
+	i2c at 138B0000 {	/* i2c5 */
+		status = "disabled";
+	};
+
+	i2c at 138C0000 {	/* i2c6 */
+		status = "disabled";
+	};
+
+	i2c at 138D0000 {	/* i2c7 */
+		status = "disabled";
+	};
+
+	keypad at 100A0000 {
+		status = "disabled";
+	};
+
+	spi_0: spi at 13920000 {
+		status = "disabled";
+	};
+
+	spi_1: spi at 13930000 {
+		status = "disabled";
+	};
+
+	spi_2: spi at 13940000 {
+		status = "disabled";
+	};
+};
-- 
1.7.9.5



From sachin.kamat at linaro.org  Wed Aug  8 01:40:25 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed, 8 Aug 2012 11:10:25 +0530
Subject: [PATCH v2] arm/dts: exynos4: Add DTS file for ODROID-X
In-Reply-To: <1344404201-8641-1-git-send-email-dongjin.kim@agreeyamobility.net>
References: <1344404201-8641-1-git-send-email-dongjin.kim@agreeyamobility.net>
Message-ID: <CAK9yfHz=Lg=cY88=rq+buTf_=h1HA4rahVSF5W2EHUM_SrYNXA@mail.gmail.com>

On 8 August 2012 11:06,  <tobetter at gmail.com> wrote:
> From: Dongjin Kim <dongjin.kim at agreeyamobility.net>
>
> This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
> gpios base.
>
> Changes in V2:
>     -. Banner changed
>
> Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
> ---
>  arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
>  1 file changed, 148 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts
>
> diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
> new file mode 100644
> index 0000000..1b8a7f8
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
> @@ -0,0 +1,148 @@
> +/*
> + * Samsung's Exynos4210 based ODROID-X board device tree source

Exynos4210?



> + *
> + * Copyright (c) 2012 AgreeYa Mobility Co., Ltd.
> + *             http://www.agreeyamobility.net
> + * Copyright (c) 2012 Hardkernel Co., Ltd.
> + *             http://www.hardkernel.com
> + *
> + * Device tree source file for Hardkernel's ODROID-X board which is based on
> + * Samsung's Exynos4412 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos4412.dtsi"
> +/include/ "max77686.dtsi"
> +
> +/ {
> +       model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
> +       compatible = "hardkernel,odroidx", "samsung,exynos4412";
> +
> +       memory {
> +               reg = <0x40000000 0x40000000>;
> +       };
> +
> +       chosen {
> +               bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
> +       };
> +
> +       /* sdhci0 */
> +       sdhci at 12510000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci1 */
> +       sdhci at 12520000 {
> +               status = "disabled";
> +       };
> +
> +       /* sdhci2 */
> +       sdhci at 12530000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk2 2 2 3 3>;
> +               gpios = <&gpk2 0 2 0 3>,
> +                       <&gpk2 1 2 0 3>,
> +                       <&gpk2 3 2 3 3>,
> +                       <&gpk2 4 2 3 3>,
> +                       <&gpk2 5 2 3 3>,
> +                       <&gpk2 6 2 3 3>;
> +       };
> +
> +       /* sdhci3 */
> +       sdhci at 12540000 {
> +               samsung,sdhci-bus-width = <4>;
> +               linux,mmc_cap_4_bit_data;
> +               samsung,sdhci-cd-internal;
> +               gpio-cd = <&gpk3 2 2 3 3>;
> +               gpios = <&gpk3 0 2 0 3>,
> +                       <&gpk3 1 2 0 3>,
> +                       <&gpk3 3 2 3 3>,
> +                       <&gpk3 4 2 3 3>,
> +                       <&gpk3 5 2 3 3>,
> +                       <&gpk3 6 2 3 3>;
> +       };
> +
> +       leds {
> +               compatible = "gpio-leds";
> +
> +               led1 {
> +                       label   = "led1";
> +                       gpios   = <&gpc1 0 1 0x10000 0>;
> +                       linux,default-trigger   = "oneshot";
> +                       default-state   = "off";
> +               };
> +
> +               led2 {
> +                       label   = "led2";
> +                       gpios   = <&gpc1 2 1 0x10000 0>;
> +                       linux,default-trigger   = "heartbeat";
> +               };
> +       };
> +
> +       i2c at 13860000 {  /* i2c0 */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               gpios = <&gpd1 0 2 0 0>,
> +                       <&gpd1 1 2 0 0>;
> +               pmic at 9 {
> +                       compatible = "maxim,max77686";
> +                       reg = <9>;
> +               };
> +       };
> +
> +       i2c at 13870000 {  /* i2c1 */
> +               status = "disabled";
> +               gpios = <&gpd1 2 2 0 0>,
> +                       <&gpd1 3 2 0 0>;
> +       };
> +
> +       i2c at 13880000 {  /* i2c2 */
> +               status = "disabled";
> +               gpios = <&gpa0 6 2 0 0>,
> +                       <&gpa0 7 2 0 0>;
> +       };
> +
> +       i2c at 13890000 {  /* i2c3 */
> +               status = "disabled";
> +               gpios = <&gpa1 2 2 0 0>,
> +                       <&gpa1 3 2 0 0>;
> +       };
> +
> +       i2c at 138A0000 {  /* i2c4 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138B0000 {  /* i2c5 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138C0000 {  /* i2c6 */
> +               status = "disabled";
> +       };
> +
> +       i2c at 138D0000 {  /* i2c7 */
> +               status = "disabled";
> +       };
> +
> +       keypad at 100A0000 {
> +               status = "disabled";
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               status = "disabled";
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               status = "disabled";
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               status = "disabled";
> +       };
> +};
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/



-- 
With warm regards,
Sachin


From tobetter at gmail.com  Wed Aug  8 01:46:38 2012
From: tobetter at gmail.com (tobetter at gmail.com)
Date: Wed,  8 Aug 2012 14:46:38 +0900
Subject: [PATCH v3] arm/dts: exynos4: Add DTS file for ODROID-X
In-Reply-To: <[PATCH v2] arm/dts: exynos4: Add DTS file for ODROID-X>
References: <[PATCH v2] arm/dts: exynos4: Add DTS file for ODROID-X>
Message-ID: <1344404802-9442-1-git-send-email-dongjin.kim@agreeyamobility.net>

From: Dongjin Kim <dongjin.kim at agreeyamobility.net>

This patch create a DTS file for ODROID-X, it desribes PMIC max77686 and LED
gpios base.

Changes in V2 & V3:
    -. Banner changed

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/boot/dts/exynos4412-odroidx.dts |  148 ++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos4412-odroidx.dts

diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 0000000..7f63eaf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,148 @@
+/*
+ * Samsung's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 AgreeYa Mobility Co., Ltd.
+ *		http://www.agreeyamobility.net
+ * Copyright (c) 2012 Hardkernel Co., Ltd.
+ *		http://www.hardkernel.com
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+/include/ "max77686.dtsi"
+
+/ {
+	model = "Hardkernel ODROID-X evaluation board based on Exynos4412";
+	compatible = "hardkernel,odroidx", "samsung,exynos4412";
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/mmcblk0p1 init=/sbin/init console=ttySAC1,115200 console=tty1 rootdalay=2";
+	};
+
+	/* sdhci0 */
+	sdhci at 12510000 {
+		status = "disabled";
+	};
+
+	/* sdhci1 */
+	sdhci at 12520000 {
+		status = "disabled";
+	};
+
+	/* sdhci2 */
+	sdhci at 12530000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd = <&gpk2 2 2 3 3>;
+		gpios = <&gpk2 0 2 0 3>,
+			<&gpk2 1 2 0 3>,
+			<&gpk2 3 2 3 3>,
+			<&gpk2 4 2 3 3>,
+			<&gpk2 5 2 3 3>,
+			<&gpk2 6 2 3 3>;
+	};
+
+	/* sdhci3 */
+	sdhci at 12540000 {
+		samsung,sdhci-bus-width = <4>;
+		linux,mmc_cap_4_bit_data;
+		samsung,sdhci-cd-internal;
+		gpio-cd	= <&gpk3 2 2 3 3>;
+		gpios = <&gpk3 0 2 0 3>,
+			<&gpk3 1 2 0 3>,
+			<&gpk3 3 2 3 3>,
+			<&gpk3 4 2 3 3>,
+			<&gpk3 5 2 3 3>,
+			<&gpk3 6 2 3 3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1 {
+			label	= "led1";
+			gpios	= <&gpc1 0 1 0x10000 0>;
+			linux,default-trigger	= "oneshot";
+			default-state	= "off";
+		};
+
+		led2 {
+			label	= "led2";
+			gpios	= <&gpc1 2 1 0x10000 0>;
+			linux,default-trigger	= "heartbeat";
+		};
+	};
+
+	i2c at 13860000 {	/* i2c0 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpd1 0 2 0 0>,
+			<&gpd1 1 2 0 0>;
+		pmic at 9 {
+			compatible = "maxim,max77686";
+			reg = <9>;
+		};
+	};
+
+	i2c at 13870000 {	/* i2c1 */
+		status = "disabled";
+		gpios = <&gpd1 2 2 0 0>,
+			<&gpd1 3 2 0 0>;
+	};
+
+	i2c at 13880000 {	/* i2c2 */
+		status = "disabled";
+		gpios = <&gpa0 6 2 0 0>,
+			<&gpa0 7 2 0 0>;
+	};
+
+	i2c at 13890000 {	/* i2c3 */
+		status = "disabled";
+		gpios = <&gpa1 2 2 0 0>,
+			<&gpa1 3 2 0 0>;
+	};
+
+	i2c at 138A0000 {	/* i2c4 */
+		status = "disabled";
+	};
+
+	i2c at 138B0000 {	/* i2c5 */
+		status = "disabled";
+	};
+
+	i2c at 138C0000 {	/* i2c6 */
+		status = "disabled";
+	};
+
+	i2c at 138D0000 {	/* i2c7 */
+		status = "disabled";
+	};
+
+	keypad at 100A0000 {
+		status = "disabled";
+	};
+
+	spi_0: spi at 13920000 {
+		status = "disabled";
+	};
+
+	spi_1: spi at 13930000 {
+		status = "disabled";
+	};
+
+	spi_2: spi at 13940000 {
+		status = "disabled";
+	};
+};
-- 
1.7.9.5



From nicolas.pitre at linaro.org  Wed Aug  8 01:56:41 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 8 Aug 2012 01:56:41 -0400 (EDT)
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <50219C45.7030601@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
Message-ID: <alpine.LFD.2.02.1208080106500.5231@xanadu.home>

On Tue, 7 Aug 2012, Cyril Chemparathy wrote:

> Hi Nicolas,
> 
> On 8/4/2012 1:38 AM, Nicolas Pitre wrote:
> [...]
> > > extern unsigned __patch_table_begin, __patch_table_end;
> > 
> > You could use "exttern void __patch_table_begin" so those symbols don't
> > get any type that could be misused by mistake, while you still can take
> > their addresses.
> > 
> 
> Looks like we'll have to stick with a non-void type here.  The compiler throws
> a warning when we try to take the address of a void.

Ah, I see. Bummer.  This used not to be the case with older gcc 
versions.

> [...]
> > Did you verify with some test program that your patching routines do
> > produce the same opcodes as the assembled equivalent for all possible
> > shift values?  Especially for Thumb2 code which isn't as trivial to get
> > right as the ARM one.
> > 
> 
> We've refactored the patching code into separate functions as:
> 
> static int do_patch_imm8_arm(u32 insn, u32 imm, u32 *ninsn);
> static int do_patch_imm8_thumb(u32 insn, u32 imm, u32 *ninsn);
> 
> 
> With this, the following test code has been used to verify the generated
> instruction encoding:
> 
> u32 arm_check[] = {
> 	0xe2810041, 0xe2810082, 0xe2810f41, 0xe2810f82, 0xe2810e41,
> 	0xe2810e82, 0xe2810d41, 0xe2810d82, 0xe2810c41, 0xe2810c82,
> 	0xe2810b41, 0xe2810b82, 0xe2810a41, 0xe2810a82, 0xe2810941,
> 	0xe2810982, 0xe2810841, 0xe2810882, 0xe2810741, 0xe2810782,
> 	0xe2810641, 0xe2810682, 0xe2810541, 0xe2810582, 0xe2810441,
> };

Instead of using this array you could let the assembler do it for you 
like this:

asm (" \n\
	.arm \n\
arm_check: \n\
        .set shft, 0 \n\
        .rep 12 \n\
        add     r1, r2, #0x81 << \shft \n\
        .set shft, \shft + 2 \n\
        .endr \n\
");

> u32 thumb_check[] = {
> 	0xf1010081, 0xf5017081, 0xf5017001, 0xf5016081, 0xf5016001,
> 	0xf5015081, 0xf5015001, 0xf5014081, 0xf5014001, 0xf5013081,
> 	0xf5013001, 0xf5012081, 0xf5012001, 0xf5011081, 0xf5011001,
> 	0xf5010081, 0xf5010001, 0xf1017081, 0xf1017001, 0xf1016081,
> 	0xf1016001, 0xf1015081, 0xf1015001, 0xf1014081, 0xf1014001,

Same idea here.


Nicolas


From kgene.kim at samsung.com  Wed Aug  8 02:20:16 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 15:20:16 +0900
Subject: [PATCH V4 0/2] arm: samsung: Move FIMD headers to include/video/
In-Reply-To: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
References: <1344342872-7904-1-git-send-email-l.krishna@samsung.com>
Message-ID: <0ab701cd752d$e0d1db00$a2759100$%kim@samsung.com>

Leela Krishna Amudala wrote:
> 
> This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch
> side
> to include/video/samsung_fimd.h
> 
> This patchset is created and rebased against master branch of torvalds
> tree.
> Tested on smdk5250 board, build tested for other boards.
> 
> Changes from version 3:
> 	- Squashed 1st, 3rd, 4th and 5th patches from version 3
> 
> Changes from version 2:
> 	- Changed the EXYNOS5_xxx macro name to FIMD_V8_xxx
> 	- Moved the header inclusion under same kind
> 
> Changes from version 1:
> 	- Split the patches as per Sylwester comments
> 	- Changed FIMD_V8_xxx macro to EXYNOS5_xxx
> 
> Leela Krishna Amudala (2):
>   include/video: move fimd register headers from platform to
>     include/video
>   include/video: Add register offsets for FIMD version 8
> 
>  arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
>  arch/arm/mach-exynos/mach-origen.c                 |    2 +-
>  arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
>  arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
>  arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
>  arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
>  arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
>  arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
>  arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
>  arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
>  arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
>  arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
>  arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
>  arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
>  arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
>  arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
>  arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
>  arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
>  arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
>  arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
>  arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
>  arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
>  arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
----------------
> ----
>  drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
>  drivers/video/s3c-fb.c                             |    2 +-
>  .../plat/regs-fb.h => include/video/samsung_fimd.h |  152
> +++++++++++++++++--
>  26 files changed, 165 insertions(+), 194 deletions(-)
>  delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>  rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
> include/video/samsung_fimd.h (73%)

Looks OK to me. Will apply into topic branch, 'v3.7-for-florian' for
Florian's pulling.

If there is no objection for a couple of days, I will merge this into
for-next and send to Florian.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From jy0922.shim at samsung.com  Wed Aug  8 02:27:56 2012
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Wed, 08 Aug 2012 15:27:56 +0900
Subject: [PATCH 1/2] ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
In-Reply-To: <097501cd7473$f73e51d0$e5baf570$%kim@samsung.com>
References: <1337307497-15777-1-git-send-email-jy0922.shim@samsung.com>
 <4FB5B9A1.2030606@samsung.com>
 <097501cd7473$f73e51d0$e5baf570$%kim@samsung.com>
Message-ID: <502206EC.4030303@samsung.com>

On 08/07/2012 05:09 PM, Kukjin Kim wrote:
> Kukjin Kim wrote:
>> Joonyoung Shim wrote:
>>> Add to cc Grant Likely and Linus Walleij
>>>
>>> On 05/18/2012 11:18 AM, Joonyoung Shim wrote:
>>>> Also use EXYNOS4210_GPIO_Ex instead of EXYNOS4_GPIO_Ex. The GPEx gpios
>>>> exist only on Exynos4210 and there are no on Exynos4x12. Redefine them
>>>> to exact SoC name.
>>>>
>>>> Signed-off-by: Joonyoung Shim<jy0922.shim at samsung.com>
>>>> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
>>>> ---
>>>>    arch/arm/mach-exynos/include/mach/gpio.h   |   32
> ++++++++++++++------
>> --
>>> ------
>>>>    arch/arm/mach-exynos/mach-nuri.c           |   16 +++++++-------
>>>>    arch/arm/mach-exynos/mach-origen.c         |    6 ++--
>>>>    arch/arm/mach-exynos/mach-universal_c210.c |   32
> ++++++++++++++-----
>> --
>>> -------
>>>>    arch/arm/mach-exynos/setup-fimc.c          |    4 +-
>>>>    drivers/gpio/gpio-samsung.c                |   20 ++++++++--------
>>>>    6 files changed, 55 insertions(+), 55 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-
>>> exynos/include/mach/gpio.h
>>>> index eb24f1e..21c9bf1 100644
>>>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>>>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>>>> @@ -26,11 +26,11 @@
>>>>    #define EXYNOS4_GPIO_C1_NR	(5)
>>>>    #define EXYNOS4_GPIO_D0_NR	(4)
>>>>    #define EXYNOS4_GPIO_D1_NR	(4)
>>>> -#define EXYNOS4_GPIO_E0_NR	(5)
>>>> -#define EXYNOS4_GPIO_E1_NR	(8)
>>>> -#define EXYNOS4_GPIO_E2_NR	(6)
>>>> -#define EXYNOS4_GPIO_E3_NR	(8)
>>>> -#define EXYNOS4_GPIO_E4_NR	(8)
>>>> +#define EXYNOS4210_GPIO_E0_NR	(5)
>>>> +#define EXYNOS4210_GPIO_E1_NR	(8)
>>>> +#define EXYNOS4210_GPIO_E2_NR	(6)
>>>> +#define EXYNOS4210_GPIO_E3_NR	(8)
>>>> +#define EXYNOS4210_GPIO_E4_NR	(8)
>> I think, splitting the gpios like following(common exynos4 and exynos4210
>> or exynos4x12). So please just put the definitions for EXYNOS4210 GPIO
>> after EXYNOS4_GPIO_XXX.
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-
>> exynos/include/mach/gpio.h
>> index eb24f1e..910b611 100644
>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>> @@ -26,17 +26,10 @@
>>   #define EXYNOS4_GPIO_C1_NR	(5)
>>   #define EXYNOS4_GPIO_D0_NR	(4)
>>   #define EXYNOS4_GPIO_D1_NR	(4)
>> -#define EXYNOS4_GPIO_E0_NR	(5)
>> -#define EXYNOS4_GPIO_E1_NR	(8)
>> -#define EXYNOS4_GPIO_E2_NR	(6)
>> -#define EXYNOS4_GPIO_E3_NR	(8)
>> -#define EXYNOS4_GPIO_E4_NR	(8)
>>   #define EXYNOS4_GPIO_F0_NR	(8)
>>   #define EXYNOS4_GPIO_F1_NR	(8)
>>   #define EXYNOS4_GPIO_F2_NR	(8)
>>   #define EXYNOS4_GPIO_F3_NR	(6)
>> -#define EXYNOS4_GPIO_J0_NR	(8)
>> -#define EXYNOS4_GPIO_J1_NR	(5)
>>   #define EXYNOS4_GPIO_K0_NR	(7)
>>   #define EXYNOS4_GPIO_K1_NR	(7)
>>   #define EXYNOS4_GPIO_K2_NR	(7)
>> @@ -57,6 +50,31 @@
>>   #define EXYNOS4_GPIO_Y6_NR	(8)
>>   #define EXYNOS4_GPIO_Z_NR	(7)
>>
>> +/* For EXYNOS4210 GPIO bank sizes */
>> +
>> +#define EXYNOS4210_GPIO_E0_NR	(5)
>> +#define EXYNOS4210_GPIO_E1_NR	(8)
>> +#define EXYNOS4210_GPIO_E2_NR	(6)
>> +#define EXYNOS4210_GPIO_E3_NR	(8)
>> +#define EXYNOS4210_GPIO_E4_NR	(8)
>> +#define EXYNOS4210_GPIO_J0_NR	(8)
>> +#define EXYNOS4210_GPIO_J1_NR	(5)
>>
>> [...]
>>
>> And we can add EXYNOS4X12 GPIO like following in other patch.
>>
>> +/* For EXYNOS4X12 GPIO bank sizes */
>> +
>> +#define EXYNOS4X12_GPIO_J0_NR	(8)
>> +#define EXYNOS4X12_GPIO_J1_NR	(5)
>> +#define EXYNOS4X12_GPIO_M0_NR	(8)
>> +#define EXYNOS4X12_GPIO_M1_NR	(7)
>> +#define EXYNOS4X12_GPIO_M2_NR	(5)
>> +#define EXYNOS4X12_GPIO_M3_NR	(8)
>> +#define EXYNOS4X12_GPIO_M4_NR	(8)
>> +#define EXYNOS4X12_GPIO_V0_NR	(8)
>> +#define EXYNOS4X12_GPIO_V1_NR	(8)
>> +#define EXYNOS4X12_GPIO_V2_NR	(8)
>> +#define EXYNOS4X12_GPIO_V3_NR	(8)
>> +#define EXYNOS4X12_GPIO_V4_NR	(2)
>>
>>>>    #define EXYNOS4_GPIO_F0_NR	(8)
>>>>    #define EXYNOS4_GPIO_F1_NR	(8)
>>>>    #define EXYNOS4_GPIO_F2_NR	(8)
>>>> @@ -67,12 +67,12 @@ enum exynos4_gpio_number {
>>>>    	EXYNOS4_GPIO_C1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
>>>>    	EXYNOS4_GPIO_D0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
>>>>    	EXYNOS4_GPIO_D1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
>>>> -	EXYNOS4_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
>>>> -	EXYNOS4_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
>>>> -	EXYNOS4_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
>>>> -	EXYNOS4_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
>>>> -	EXYNOS4_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
>>>> -	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
>>>> +	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
>>>> +	EXYNOS4210_GPIO_E1_START	=
> EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
>>>> +	EXYNOS4210_GPIO_E2_START	=
> EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
>>>> +	EXYNOS4210_GPIO_E3_START	=
> EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
>>>> +	EXYNOS4210_GPIO_E4_START	=
> EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
>>>> +	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
>>>>    	EXYNOS4_GPIO_F1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
>>>>    	EXYNOS4_GPIO_F2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
>>>>    	EXYNOS4_GPIO_F3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
>> Same as above.
>>
>> @@ -99,6 +117,31 @@ enum exynos4_gpio_number {
>>   	EXYNOS4_GPIO_Z_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
>>   };
>>
>> +enum exynos4210_gpio_number {
>> +	EXYNOS4210_GPIO_E0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
>> +	EXYNOS4210_GPIO_E1_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E0),
>> +	EXYNOS4210_GPIO_E2_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E1),
>> +	EXYNOS4210_GPIO_E3_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E2),
>> +	EXYNOS4210_GPIO_E4_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E3),
>> +	EXYNOS4210_GPIO_J0_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_E4),
>> +	EXYNOS4210_GPIO_J1_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4210_GPIO_J0),
>> +};
>>
>> [...]
>>
>> And following is possible for EXYNOS4X12...
>>
>> +enum exynos4x12_gpio_number {
>> +	EXYNOS4X12_GPIO_J0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Z),
>> +	EXYNOS4X12_GPIO_J1_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J0),
>> +	EXYNOS4X12_GPIO_M0_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_J1),
>> +	EXYNOS4X12_GPIO_M1_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
>> +	EXYNOS4X12_GPIO_M2_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
>> +	EXYNOS4X12_GPIO_M3_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
>> +	EXYNOS4X12_GPIO_M4_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
>> +	EXYNOS4X12_GPIO_V0_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
>> +	EXYNOS4X12_GPIO_V1_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V0),
>> +	EXYNOS4X12_GPIO_V2_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V1),
>> +	EXYNOS4X12_GPIO_V3_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V2),
>> +	EXYNOS4X12_GPIO_V4_START	=
> EXYNOS4_GPIO_NEXT(EXYNOS4X12_GPIO_V3),
>> +};
>> +
>>   /* EXYNOS4 GPIO number definitions */
>>
>>   #define EXYNOS4_GPA0(_nr)	(EXYNOS4_GPIO_A0_START + (_nr))
>>
>> [...]
>>
>> Of course, need to update other regarding gpio part accordingly.
>>
> Joonyoung, any updates on this?

Sorry for late response, but i don't have any progress for this.

Thanks.


From tony at atomide.com  Wed Aug  8 02:47:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 7 Aug 2012 23:47:22 -0700
Subject: [PATCH] ARM: OMAP2+: Fix dmtimer set source clock failure
In-Reply-To: <87boim36mj.fsf@ti.com>
References: <1342210323-2129-1-git-send-email-jon-hunter@ti.com>
 <87boim36mj.fsf@ti.com>
Message-ID: <20120808064722.GB11011@atomide.com>

* Kevin Hilman <khilman at ti.com> [120807 11:21]:
> Jon Hunter <jon-hunter at ti.com> writes:
> 
> > Calling the dmtimer function omap_dm_timer_set_source() fails if following a
> > call to pm_runtime_put() to disable the timer. For example the following
> > sequence would fail to set the parent clock ...
> >
> > 	omap_dm_timer_stop(gptimer);
> > 	omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
> >
> > The following error message would be seen ...
> >
> > omap_dm_timer_set_source: failed to set timer_32k_ck as parent
> >
> > The problem is that, by design, pm_runtime_put() simply decrements the usage
> > count and returns before the timer has actually been disabled. Therefore,
> > setting the parent clock failed because the timer was still active when the
> > trying to set the parent clock. Setting a parent clock will fail if the clock
> > you are setting the parent of has a non-zero usage count. To ensure that this
> > does not fail use pm_runtime_put_sync() when disabling the timer.
> >
> > Note that this will not be seen on OMAP1 devices, because these devices do
> > not use the clock framework for dmtimers.
> >
> > Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> 
> Acked-by: Kevin Hilman <khilman at ti.com>

Thanks applying into fixes with Cc stable.

Tony


From magnus.damm at gmail.com  Wed Aug  8 02:52:12 2012
From: magnus.damm at gmail.com (Magnus Damm)
Date: Wed, 8 Aug 2012 15:52:12 +0900
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <5016D03D.8010607@codeaurora.org>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
Message-ID: <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>

On Tue, Jul 31, 2012 at 3:19 AM, Stephen Boyd <sboyd at codeaurora.org> wrote:
> On 07/10/12 23:34, Kukjin Kim wrote:
>> Stephen Boyd wrote:
>>> Great. Kukjin Kim, can exynos use SGI0? It looks like exynos is the only
>>> one left to move to SGI0.
>>>
>> Yeah, EXYNOS can use SGI0 instead of SGI1 :)
>>
>>
>
> Russell, can we apply something like this?
>
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 36c3984..090e32b 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -139,7 +139,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
>                 __raw_writel(virt_to_phys(exynos4_secondary_startup),
>                         CPU1_BOOT_REG);
> -               gic_raise_softirq(cpumask_of(cpu), 1);
> +               gic_raise_softirq(cpumask_of(cpu), 0);
>
>                 if (pen_release == -1)
>                         break;
>
>
> I see we have another user of SGI1. Magnus/Rafael, can we move
> smp-emev2.c to use SGI0 instead of SGI1?

So I finally managed to try this out on my KZM9D board. The SMP bring
up code continues to work as expected, so it seems that SGI0 can be
used instead of SGI1 on EMEV2. Let's just say that the boot protocol
implemented by the mask ROM is rather poorly documented. Anyway, to
test I used the following patch on top of linux git 42a579a.

--- 0001/arch/arm/mach-shmobile/smp-emev2.c
+++ work/arch/arm/mach-shmobile/smp-emev2.c	2012-08-08 15:42:54.000000000 +0900
@@ -82,7 +82,7 @@ int __cpuinit emev2_boot_secondary(unsig
 	/* Tell ROM loader about our vector (in headsmp.S) */
 	emev2_set_boot_vector(__pa(shmobile_secondary_vector));

-	gic_raise_softirq(cpumask_of(cpu), 1);
+	gic_raise_softirq(cpumask_of(cpu), 0);
 	return 0;
 }

So if/where needed, please add my:

Acked-by: Magnus Damm <damm at opensource.se>

Thanks,

/ magnus


From s.hauer at pengutronix.de  Wed Aug  8 02:52:41 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 8 Aug 2012 08:52:41 +0200
Subject: [PATCH 2/2] ARM: only build ssi-fiq.S et al if
 CONFIG_SND_IMX_SOC_PCM_FIQ is selected
In-Reply-To: <1344379514-30076-3-git-send-email-matt@genesi-usa.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-3-git-send-email-matt@genesi-usa.com>
Message-ID: <20120808065241.GG24458@pengutronix.de>

On Tue, Aug 07, 2012 at 05:45:14PM -0500, Matt Sealey wrote:
> Further to the previous patch, a custom configuration may be used based on the
> imx_v6_v7_defconfig which removes the board depending on the audio driver pulling
> this support code. However, since it is built dependent on CONFIG_SND_IMX_SOC
> it is enabled in the build for all i.MX processors which enable any audio drivers.
> 
> Correct this by only building the SSI FIQ support code when the more specific
> CONFIG_SND_IMX_SOC_PCM_FIQ is enabled. Since it's enabled in the imx_v6_v7_defconfig
> anyway by the Eukrea board, nothing changes using the defconfig, so this is just
> a convenience for people reconfiguring their kernels more sparsely than the default.
> 
> Signed-off-by: Matt Sealey <matt at genesi-usa.com>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/plat-mxc/Makefile |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> index 6ac7200..89927f5 100644
> --- a/arch/arm/plat-mxc/Makefile
> +++ b/arch/arm/plat-mxc/Makefile
> @@ -16,7 +16,7 @@ obj-$(CONFIG_MXC_USE_EPIT) += epit.o
>  obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
>  obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
>  obj-$(CONFIG_CPU_IDLE) += cpuidle.o
> -ifdef CONFIG_SND_IMX_SOC
> +ifdef CONFIG_SND_IMX_SOC_PCM_FIQ
>  obj-y += ssi-fiq.o
>  obj-y += ssi-fiq-ksym.o
>  endif

Since you are here already, better do:

obj-$(CONFIG_SND_IMX_SOC_PCM_FIQ) +) += ssi-fiq.o ssi-fiq-ksym.o

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Aug  8 02:55:02 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 8 Aug 2012 08:55:02 +0200
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
Message-ID: <20120808065502.GI1451@pengutronix.de>

On Tue, Aug 07, 2012 at 05:45:13PM -0500, Matt Sealey wrote:
> If i.MX SSI FIQ support is enabled then it is impossible to build a Thumb2
> kernel image due to the code not being written with Thumb2 in mind (over-use
> of registers). In order not to break Thumb2 kernels, compile this as ARM. All
> the processors which require this support will run ARM code so there is no
> problem at runtime in doing this, even if it does produce a strange mix of
> code that may not be desired.
> 
> In theory this should only be needed on configs based on imx_v4_v5_defconfig
> where CONFIG_THUMB2_KERNEL cannot be selected anyway since these SoCs do not
> have ARM cores capable of running Thumb2 code. This also makes rewriting the
> code as Thumb-compatible kind of redundant. But since one Eukrea board audio
> driver needs it, and there is an i.MX51 CPU module for this board, it gets
> pulled in for imx_v6_v7_defconfig too, making this a necessity.
> 
> Signed-off-by: Matt Sealey <matt at genesi-usa.com>
> ---
>  arch/arm/plat-mxc/ssi-fiq.S |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
> index 8397a2d..ac09af8 100644
> --- a/arch/arm/plat-mxc/ssi-fiq.S
> +++ b/arch/arm/plat-mxc/ssi-fiq.S
> @@ -28,6 +28,7 @@
>  #define SSI_SIER_RFF0_EN	(1 << 2)
>  
>  		.text
> +		.arm
>  		.global	imx_ssi_fiq_start
>  		.global	imx_ssi_fiq_end
>  		.global imx_ssi_fiq_base

I think it would be better to add a depends on !THUMB2_KERNEL to
SND_IMX_SOC_PCM_FIQ. The above may result in broken code in a thumb2
kernel, so I'd rather keep the compile error instead.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Aug  8 02:57:13 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 8 Aug 2012 08:57:13 +0200
Subject: [PATCH 3/9] [media] mx1_camera: Don't use {en,dis}able_fiq() calls
In-Reply-To: <1344207819-3415-3-git-send-email-anton.vorontsov@linaro.org>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-3-git-send-email-anton.vorontsov@linaro.org>
Message-ID: <20120808065713.GJ1451@pengutronix.de>

On Sun, Aug 05, 2012 at 04:03:33PM -0700, Anton Vorontsov wrote:
> The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
> passed to it, so it's pretty clear that the driver is absolutely sure
> that the FIQ is routed via platform-specific IC, and that the cookie can
> be used to mask/unmask FIQs. So, let's switch to the genirq routines,
> since we're about to remove FIQ-specific variants.
> 
> Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>


> ---
>  drivers/media/video/mx1_camera.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
> index d2e6f82..1536d09 100644
> --- a/drivers/media/video/mx1_camera.c
> +++ b/drivers/media/video/mx1_camera.c
> @@ -801,7 +801,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
>  	set_fiq_regs(&regs);
>  
>  	mxc_set_irq_fiq(irq, 1);
> -	enable_fiq(irq);
> +	enable_irq(irq);
>  
>  	pcdev->soc_host.drv_name	= DRIVER_NAME;
>  	pcdev->soc_host.ops		= &mx1_soc_camera_host_ops;
> @@ -817,7 +817,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
>  	return 0;
>  
>  exit_free_irq:
> -	disable_fiq(irq);
> +	disable_irq(irq);
>  	mxc_set_irq_fiq(irq, 0);
>  	release_fiq(&fh);
>  exit_free_dma:
> @@ -842,7 +842,7 @@ static int __exit mx1_camera_remove(struct platform_device *pdev)
>  	struct resource *res;
>  
>  	imx_dma_free(pcdev->dma_chan);
> -	disable_fiq(pcdev->irq);
> +	disable_irq(pcdev->irq);
>  	mxc_set_irq_fiq(pcdev->irq, 0);
>  	release_fiq(&fh);
>  
> -- 
> 1.7.10.4
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Aug  8 02:57:24 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 8 Aug 2012 08:57:24 +0200
Subject: [PATCH 4/9] ASoC: imx: Don't use {en,dis}able_fiq() calls
In-Reply-To: <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-4-git-send-email-anton.vorontsov@linaro.org>
Message-ID: <20120808065724.GK1451@pengutronix.de>

On Sun, Aug 05, 2012 at 04:03:34PM -0700, Anton Vorontsov wrote:
> The driver uses platform-specific mxc_set_irq_fiq() with the VIRQ cookie
> passed to it, so it's pretty clear that the driver is absolutely sure
> that the FIQ is routed via platform-specific IC, and that the cookie can
> be used to mask/unmask FIQs. So, let's switch to the genirq routines,
> since we're about to remove FIQ-specific variants.
> 
> Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

> ---
>  sound/soc/fsl/imx-pcm-fiq.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
> index ee27ba3..993e37d 100644
> --- a/sound/soc/fsl/imx-pcm-fiq.c
> +++ b/sound/soc/fsl/imx-pcm-fiq.c
> @@ -139,7 +139,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
>  		hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
>  		      HRTIMER_MODE_REL);
>  		if (++fiq_enable == 1)
> -			enable_fiq(imx_pcm_fiq);
> +			enable_irq(imx_pcm_fiq);
>  
>  		break;
>  
> @@ -149,7 +149,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
>  		atomic_set(&iprtd->running, 0);
>  
>  		if (--fiq_enable == 0)
> -			disable_fiq(imx_pcm_fiq);
> +			disable_irq(imx_pcm_fiq);
>  
>  		break;
>  	default:
> -- 
> 1.7.10.4
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From santosh.shilimkar at ti.com  Wed Aug  8 03:04:54 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 8 Aug 2012 12:34:54 +0530
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <20120807170026.GH18957@n2100.arm.linux.org.uk>
References: <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>
 <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>
 <20120807170026.GH18957@n2100.arm.linux.org.uk>
Message-ID: <CAMQu2gy7go1MUA4cJtqjtcGc4SADVVTcn5C7gR5UCO_WrCH+pQ@mail.gmail.com>

On Tue, Aug 7, 2012 at 10:30 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 06, 2012 at 01:41:06PM -0700, Colin Cross wrote:
>> When testing coupled cpuidle on Exynos5, I found that sending an IPI
>> does not successfully wake up CPU1.  CPU1 is in a wfe with interrupts
>> masked, not a wfi, so an interrupt is not able to wake it up.  It
>> tends to wake up anyways because the next time a spin lock is
>> unlocked, often during a timer interrupt on CPU0, CPU0 executes an sev
>> which wakes up CPU1.  You can see that the IPI is unnecessary by
>> removing the gic_raise_softirq and replacing it with dsb_sev().
>
> That's good news; that supports my assertion that the SMP bringup code
> we see on various platforms as copies from the Realview code was done
> without much thought about what is actually required.
>
> It's good that you're looking into this, and fixing the code on the CPUs
> you have access to.  I rather wish we'd made it a requirement for people
> to _document_ the actual bringup conditions in the kernel for their
> hardware before we accepted their SMP support code.
>
Movement to SGI0 for all ARM platform was also discussed when I
was trying to fix the "Unknown IPI message 0x1" warning with patch [1]

For OMAP too, the SGI0 works.

Regards
Santosh

[1 ] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-January/038430.html


From p.paneri at samsung.com  Wed Aug  8 03:40:57 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:10:57 +0530
Subject: [PATCH v3 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344411661-17821-2-git-send-email-p.paneri@samsung.com>

This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable phy. Tested with
smdk6410 and smdkv310. More SoCs can be brought under later.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
Acked-by: Heiko Stuebner <heiko at sntech.de>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung-usbphy.c                   |  355 ++++++++++++++++++++
 drivers/usb/phy/samsung-usbphy.h                   |   48 +++
 include/linux/platform_data/samsung-usbphy.h       |   27 ++
 6 files changed, 448 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung-usbphy.c
 create mode 100644 drivers/usb/phy/samsung-usbphy.h
 create mode 100644 include/linux/platform_data/samsung-usbphy.h

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 0000000..fefd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,9 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..d916477 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -15,3 +15,11 @@ config USB_ISP1301
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1301.
+
+config SAMSUNG_USBPHY
+       bool "Samsung USB PHY controller Driver"
+       depends on USB_S3C_HSOTG
+       select USB_OTG_UTILS
+       help
+         Enable this to support Samsung USB phy controller for samsung
+         SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..dfca70d 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_SAMSUNG_USBPHY)		+= samsung-usbphy.o
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
new file mode 100644
index 0000000..daefec6
--- /dev/null
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -0,0 +1,355 @@
+/* linux/drivers/usb/phy/samsung-usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/samsung-usbphy.h>
+
+#include "samsung-usbphy.h"
+
+enum samsung_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_EXYNOS4210,
+};
+
+/*
+ * struct samsung_usbphy - transceiver driver state
+ * @phy: transceiver structure
+ * @plat: platform data
+ * @dev: The parent device supplied to the probe function
+ * @clk: usb phy clock
+ * @regs: usb phy register memory base
+ * @cpu_type: machine identifier
+ */
+struct samsung_usbphy {
+	struct usb_phy	phy;
+	struct samsung_usbphy_data *plat;
+	struct device	*dev;
+	struct clk	*clk;
+	void __iomem	*regs;
+	int		cpu_type;
+};
+
+#define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
+
+/*
+ * Enables or disables the phy clock
+ * returns 0 on success else the error
+ */
+static int samsung_usbphy_clk_control(struct samsung_usbphy *sphy, bool on)
+{
+	if (on) {
+		if (!sphy->clk) {
+			sphy->clk = clk_get(sphy->dev, "otg");
+			if (IS_ERR(sphy->clk)) {
+				dev_err(sphy->dev, "Failed to get otg clock\n");
+				return PTR_ERR(sphy->clk);
+			}
+		}
+		clk_enable(sphy->clk);
+	} else {
+		clk_disable(sphy->clk);
+		clk_put(sphy->clk);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns reference clock frequency
+ */
+static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
+{
+	struct clk *ref_clk;
+	int refclk_freq = 0;
+
+	ref_clk = clk_get(sphy->dev, "xusbxti");
+	if (IS_ERR(ref_clk)) {
+		dev_err(sphy->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	switch (clk_get_rate(ref_clk)) {
+	case 12 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+		break;
+	default:
+	case 48 * MHZ:
+		/* default reference clock */
+		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+		break;
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	/* set clock frequency for PLL */
+	phyclk = samsung_usbphy_get_refclk_freq(sphy);
+	phypwr = readl(regs + S3C_PHYPWR);
+	rstcon = readl(regs + S3C_RSTCON);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
+		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+	default:
+		break;
+	}
+
+	writel(phyclk, regs + S3C_PHYCLK);
+	/* set to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+	/* reset all ports of PHY and Link */
+	writel(rstcon, regs + S3C_RSTCON);
+	udelay(10);
+	rstcon &= ~S3C_RSTCON_PHY;
+	writel(rstcon, regs + S3C_RSTCON);
+}
+
+static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+
+	phypwr = readl(regs + S3C_PHYPWR);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phypwr |= S3C_PHYPWR_NORMAL_MASK;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
+	default:
+		break;
+	}
+
+	/* unset to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int samsung_usbphy_init(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+	int ret = 0;
+
+	sphy = phy_to_sphy(phy);
+
+	/* Enable the phy clock */
+	ret = samsung_usbphy_clk_control(sphy, true);
+	if (ret) {
+		dev_err(sphy->dev, "phy clock enable failed\n");
+		return ret;
+	}
+
+	/* Disable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(false);
+
+	/* Initialize usb phy registers */
+	samsung_usbphy_enable(sphy);
+	return ret;
+}
+
+/*
+ * The function passed to the usb driver for phy shutdown
+ */
+static void samsung_usbphy_shutdown(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+
+	sphy = phy_to_sphy(phy);
+
+	/* De-initialize usb phy registers */
+	samsung_usbphy_disable(sphy);
+
+	/* Enable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(true);
+
+	/* Disable the phy clock */
+	samsung_usbphy_clk_control(sphy, false);
+}
+
+static const struct of_device_id samsung_usbphy_dt_match[];
+
+static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	int data;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(samsung_usbphy_dt_match,
+							pdev->dev.of_node);
+		data = (int) match->data;
+		return data;
+	}
+#endif
+	return platform_get_device_id(pdev)->driver_data;
+}
+
+static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy;
+	struct samsung_usbphy_data *pdata;
+	struct device *dev = &pdev->dev;
+	struct resource *phy_mem;
+	void __iomem	*phy_base;
+	int	ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
+		return -EINVAL;
+	}
+
+	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!phy_mem) {
+		dev_err(dev, "%s: missing mem resource\n", __func__);
+		return -ENODEV;
+	}
+
+	phy_base = devm_request_and_ioremap(dev, phy_mem);
+	if (!phy_base) {
+		dev_err(dev, "%s: register mapping failed\n", __func__);
+		return -ENXIO;
+	}
+
+	sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
+	if (!sphy)
+		return -ENOMEM;
+
+	sphy->dev		= &pdev->dev;
+	sphy->plat		= pdata;
+	sphy->regs		= phy_base;
+	sphy->phy.dev		= sphy->dev;
+	sphy->phy.label		= "samsung-usbphy";
+	sphy->phy.init		= samsung_usbphy_init;
+	sphy->phy.shutdown	= samsung_usbphy_shutdown;
+	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
+
+	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, sphy);
+
+	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
+err:
+	return ret;
+}
+
+static int __exit samsung_usbphy_remove(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&sphy->phy);
+
+	if (sphy->clk) {
+		clk_put(sphy->clk);
+		sphy->clk = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id samsung_usbphy_dt_match[] = {
+	{
+		.compatible = "samsung,s3c64xx-usbphy",
+		.data = (void *)TYPE_S3C64XX,
+	}, {
+		.compatible = "samsung,exynos4210-usbphy",
+		.data = (void *)TYPE_EXYNOS4210,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
+#else
+#define samsung_usbphy_dt_match NULL
+#endif
+
+static struct platform_device_id samsung_usbphy_driver_ids[] = {
+	{
+		.name		= "s3c64xx-usbphy",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "exynos4210-usbphy",
+		.driver_data	= TYPE_EXYNOS4210,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
+
+static struct platform_driver samsung_usbphy_driver = {
+	.probe		= samsung_usbphy_probe,
+	.remove		= __devexit_p(samsung_usbphy_remove),
+	.id_table	= samsung_usbphy_driver_ids,
+	.driver		= {
+		.name	= "samsung-usbphy",
+		.owner	= THIS_MODULE,
+		.of_match_table = samsung_usbphy_dt_match,
+	},
+};
+
+static int __init samsung_usbphy_driver_init(void)
+{
+	return platform_driver_register(&samsung_usbphy_driver);
+}
+subsys_initcall(samsung_usbphy_driver_init);
+
+static void __exit samsung_usbphy_driver_exit(void)
+{
+	return platform_driver_unregister(&samsung_usbphy_driver);
+}
+module_exit(samsung_usbphy_driver_exit);
+
+MODULE_DESCRIPTION("Samsung USB phy controller");
+MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-usbphy");
diff --git a/drivers/usb/phy/samsung-usbphy.h b/drivers/usb/phy/samsung-usbphy.h
new file mode 100644
index 0000000..093b1dc
--- /dev/null
+++ b/drivers/usb/phy/samsung-usbphy.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SAMSUNG_USBPHY_H
+#define __SAMSUNG_USBPHY_H
+
+#define S3C_PHYPWR				(0x00)
+
+#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
+#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
+#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
+
+#define S3C_PHYCLK				(0x04)
+
+#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
+#define S3C_PHYCLK_EXT_OSC			(1 << 5)
+#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
+#define S3C_PHYCLK_ID_PULL			(1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
+#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
+
+#define S3C_RSTCON				(0x08)
+
+#define S3C_RSTCON_PHYCLK			(1 << 2)
+#define S3C_RSTCON_HCLK				(1 << 1)
+#define S3C_RSTCON_PHY				(1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#endif /* __SAMSUNG_USBPHY_H */
diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
new file mode 100644
index 0000000..0749ce1
--- /dev/null
+++ b/include/linux/platform_data/samsung-usbphy.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *		http://www.samsung.com/
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Defines platform data for samsung usb phy driver.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SAMSUNG_USBPHY_PLATFORM_H
+#define __SAMSUNG_USBPHY_PLATFORM_H
+
+/**
+ * samsung_usbphy_data - Platform data for USB PHY driver.
+ * @pmu_isolation: Function to control usb phy isolation in PMU.
+ */
+struct samsung_usbphy_data {
+	void (*pmu_isolation)(int on);
+};
+
+extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
+
+#endif /* __SAMSUNG_USBPHY_PLATFORM_H */
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  8 03:40:56 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:10:56 +0530
Subject: [PATCH v3 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
Message-ID: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>

Changes from v2:
Changed the driver filenames to samsung-usbphy
Changed 's3c' to 'samsung' for platform device as well as platform data
Moved platform data structure to a separate file
Rectified coding style related errors

Changes from v1:
Rebased patches to latest usb-next branch
Changed the name 'sec_usbphy' to 'samsung_usbphy'

This patch set introduces a phy driver for samsung SoCs. It uses the existing
transceiver infrastructure to provide phy control functions. Use of this driver
can be extended for usb host phy as well. Over the period of time all the phy
related code for most of the samsung SoCs can be integrated here.
Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
when they start supporting this phy driver. 
This driver is tested with smdk6410 and Exynos4210(with DT).

Praveen Paneri (5):
  usb: phy: samsung: Introducing usb phy driver for hsotg
  usb: s3c-hsotg: Adding phy driver support
  ARM: S3C64XX: Removing old phy setup code
  ARM: S3C64XX: Enabling samsung-usbphy driver
  ARM: Exynos4210: Enabling samsung-usbphy driver

 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
 arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    7 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |    8 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    7 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
 arch/arm/plat-samsung/devs.c                       |   33 ++
 arch/arm/plat-samsung/include/plat/devs.h          |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 drivers/usb/gadget/s3c-hsotg.c                     |   40 ++-
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung-usbphy.c                   |  355 ++++++++++++++++++++
 drivers/usb/phy/samsung-usbphy.h                   |   48 +++
 include/linux/platform_data/samsung-usbphy.h       |   27 ++
 19 files changed, 562 insertions(+), 91 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung-usbphy.c
 create mode 100644 drivers/usb/phy/samsung-usbphy.h
 create mode 100644 include/linux/platform_data/samsung-usbphy.h



From p.paneri at samsung.com  Wed Aug  8 03:40:58 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:10:58 +0530
Subject: [PATCH v3 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344411661-17821-3-git-send-email-p.paneri@samsung.com>

Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 drivers/usb/gadget/s3c-hsotg.c |   40 ++++++++++++++++++++++++++++++----------
 1 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b13e0bb..feb202c 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <mach/map.h>
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
  * struct s3c_hsotg - driver state.
  * @dev: The parent device supplied to the probe function
  * @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transceiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
  * @regs: The memory area mapped for accessing registers.
  * @irq: The IRQ number we are using
  * @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
+	struct usb_phy		*phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
-	if (hsotg->plat->phy_init)
+
+	if (hsotg->phy)
+		usb_phy_init(hsotg->phy);
+	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
 
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 {
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
-	if (hsotg->plat->phy_exit)
+	if (hsotg->phy)
+		usb_phy_shutdown(hsotg->phy);
+	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
 
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+	struct usb_phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,27 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 	int ret;
 	int i;
 
-	plat = pdev->dev.platform_data;
-	if (!plat) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
-
 	hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
 	if (!hsotg) {
 		dev_err(dev, "cannot get memory\n");
 		return -ENOMEM;
 	}
 
+	phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+	if (!phy) {
+		/* Fallback for platform data */
+		plat = pdev->dev.platform_data;
+		if (!plat) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -ENODEV;
+		} else {
+			hsotg->plat = plat;
+		}
+	} else {
+		hsotg->phy = phy;
+	}
+
 	hsotg->dev = dev;
-	hsotg->plat = plat;
 
 	hsotg->clk = clk_get(&pdev->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
@@ -3689,6 +3706,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
 	s3c_hsotg_phy_disable(hsotg);
 	regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
 
+	if (hsotg->phy)
+		devm_usb_put_phy(&pdev->dev, hsotg->phy);
+
 	clk_disable_unprepare(hsotg->clk);
 	clk_put(hsotg->clk);
 
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  8 03:40:59 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:10:59 +0530
Subject: [PATCH v3 3/5] ARM: S3C64XX: Removing old phy setup code
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344411661-17821-4-git-send-email-p.paneri@samsung.com>

This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |    3 -
 arch/arm/mach-s3c64xx/mach-smartq.c   |    3 -
 arch/arm/mach-s3c64xx/mach-smdk6410.c |    3 -
 arch/arm/mach-s3c64xx/setup-usb-phy.c |   79 ---------------------------------
 4 files changed, 0 insertions(+), 88 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..b0f5baf 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,7 +31,6 @@
 #include <linux/spi/spi.h>
 
 #include <linux/i2c/pca953x.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #include <video/platform_lcd.h>
 
@@ -766,7 +765,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -792,7 +790,6 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de..7400da1 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,7 +18,6 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -187,7 +186,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
 	},
 };
 
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
 
 static int __init smartq_lcd_setup_gpio(void)
 {
@@ -385,7 +383,6 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
-	s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..cbdc91b 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,7 +30,6 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/pwm_backlight.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -627,7 +626,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -657,7 +655,6 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
  *
  */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <mach/regs-sys.h>
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
-	struct clk *xusbxti;
-	u32 phyclk;
-
-	writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	/* set clock frequency for PLL */
-	phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-	xusbxti = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti && !IS_ERR(xusbxti)) {
-		switch (clk_get_rate(xusbxti)) {
-		case 12 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
-		}
-		clk_put(xusbxti);
-	}
-
-	/* TODO: select external clock/oscillator */
-	writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-	/* set to normal OTG PHY */
-	writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-	mdelay(1);
-
-	/* reset OTG PHY and Link */
-	writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-			S3C_RSTCON);
-	udelay(20);	/* at-least 10uS */
-	writel(0, S3C_RSTCON);
-
-	return 0;
-}
-
-static int s3c_usb_otgphy_exit(struct platform_device *pdev)
-{
-	writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-				S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-	writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_init(pdev);
-
-	return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_exit(pdev);
-
-	return -EINVAL;
-}
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  8 03:41:00 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:11:00 +0530
Subject: [PATCH v3 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344411661-17821-5-git-send-email-p.paneri@samsung.com>

Adding platform device for samsung-usbphy driver. Enabling it for
s3c64xx based machines using s3c-hsotg.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c        |    4 +++
 arch/arm/mach-s3c64xx/mach-smartq.c          |    5 ++++
 arch/arm/mach-s3c64xx/mach-smdk6410.c        |    4 +++
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
 arch/arm/plat-samsung/devs.c                 |   33 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h    |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
 8 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
 
 #define S3C64XX_PA_NAND		(0x70200000)
 #define S3C64XX_PA_FB		(0x77100000)
+#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
@@ -113,6 +114,7 @@
 #define S3C_PA_FB		S3C64XX_PA_FB
 #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
 #define S3C_PA_RTC		S3C64XX_PA_RTC
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 #define S3C_PA_SPI0		S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index b0f5baf..fa02e2f 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,6 +31,7 @@
 #include <linux/spi/spi.h>
 
 #include <linux/i2c/pca953x.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <video/platform_lcd.h>
 
@@ -336,6 +337,7 @@ static struct platform_device wallvdd_device = {
 };
 
 static struct platform_device *crag6410_devices[] __initdata = {
+	&samsung_device_usbphy,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc2,
 	&s3c_device_i2c0,
@@ -765,6 +767,7 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
+static struct samsung_usbphy_data crag6410_usbphy_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -790,6 +793,7 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
+	samsung_usbphy_set_pdata(&crag6410_usbphy_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 7400da1..e0c4df8 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,6 +18,7 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -234,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata = {
 };
 
 static struct platform_device *smartq_devices[] __initdata = {
+	&samsung_device_usbphy,
 	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
 	&s3c_device_hsmmc0,	/* ... then the external SD card */
 	&s3c_device_hsmmc2,
@@ -380,9 +382,12 @@ void __init smartq_map_io(void)
 	smartq_lcd_mode_set();
 }
 
+static struct samsung_usbphy_data smartq_usbphy_pdata;
+
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
+	samsung_usbphy_set_pdata(&smartq_usbphy_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index cbdc91b..8d40511 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -263,6 +264,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
+	&samsung_device_usbphy,
 #ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
 #endif
@@ -626,6 +628,7 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
+static struct samsung_usbphy_data smdk6410_usbphy_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -655,6 +658,7 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	samsung_usbphy_set_pdata(&smdk6410_usbphy_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 7a09553..3aee778 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,3 +9,17 @@
  *
  */
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	} else {
+		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	}
+}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..a094143 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -31,6 +31,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_data/s3c-hsudc.h>
 #include <linux/platform_data/s3c-hsotg.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/irq.h>
 #include <asm/pmu.h>
@@ -1343,6 +1344,35 @@ struct platform_device s5p_device_mixer = {
 
 /* USB */
 
+#ifdef CONFIG_S3C_DEV_USB_HSOTG
+/* USB PHY*/
+static struct resource samsung_usbphy_resource[] = {
+	[0] = {
+		.start = S3C_PA_USB_PHY,
+		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device samsung_device_usbphy = {
+	.name		= "s3c64xx-usbphy",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(samsung_usbphy_resource),
+	.resource	= samsung_usbphy_resource,
+};
+
+void __init samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd)
+{
+	struct samsung_usbphy_data *npd;
+
+	npd = s3c_set_platdata(pd, sizeof(struct samsung_usbphy_data),
+			&samsung_device_usbphy);
+
+	if (!npd->pmu_isolation)
+		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
+}
+#endif
+
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
 	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
@@ -1449,6 +1479,8 @@ struct platform_device s3c_device_usb_hsotg = {
 	},
 };
 
+#ifndef CONFIG_ARCH_S3C64XX
+/* TODO: To be removed later. Currently only S3C64XX is platform data free */
 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 {
 	struct s3c_hsotg_plat *npd;
@@ -1461,6 +1493,7 @@ void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 	if (!npd->phy_exit)
 		npd->phy_exit = s5p_usb_phy_exit;
 }
+#endif
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5da4b4f..3849c88 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -138,6 +138,7 @@ extern struct platform_device exynos_device_drm;
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
+extern struct platform_device samsung_device_usbphy;
 
 /* s3c2440 specific devices */
 
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..165ffe7 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern void s5p_usb_phy_pmu_isolation(int on);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
-- 
1.7.1



From p.paneri at samsung.com  Wed Aug  8 03:41:01 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Wed, 08 Aug 2012 13:11:01 +0530
Subject: [PATCH v3 5/5] ARM: Exynos4210: Enabling samsung-usbphy driver
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344411661-17821-6-git-send-email-p.paneri@samsung.com>

Adding usbphy node for Exynos4210 along with the platform data.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi       |    5 +++++
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c  |    8 ++++++++
 arch/arm/mach-exynos/setup-usb-phy.c    |   13 +++++++++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..e28cf10 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -62,6 +62,11 @@
 		interrupts = <0 44 0>, <0 45 0>;
 	};
 
+	usbphy at 125B0000 {
+		compatible = "samsung,exynos4210-usbphy";
+		reg = <0x125B0000 0x100>;
+	};
+
 	keypad at 100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..0625c0a 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -234,6 +234,7 @@
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG		EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY			EXYNOS4_PA_HSPHY
 
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..a652db0 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -20,9 +21,14 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct samsung_usbphy_data exynos4_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -63,6 +69,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 				"exynos4210-spi.2", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+			"s3c-usbphy", &exynos4_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..1c62d20 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -221,3 +221,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 	return -EINVAL;
 }
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			& ~S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	} else {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			| S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	}
+}
-- 
1.7.1



From lee.jones at linaro.org  Wed Aug  8 03:35:19 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 08:35:19 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120807170333.GV16861@opensource.wolfsonmicro.com>
References: <1344256323-10484-1-git-send-email-lee.jones@linaro.org>
 <20120806081915.GA4518@core.coreip.homeip.net>
 <20120806153750.GI10524@gmail.com>
 <20120806160226.GF29272@sirena.org.uk>
 <20120807170129.GA3759@gmail.com>
 <20120807170333.GV16861@opensource.wolfsonmicro.com>
Message-ID: <20120808073518.GA4728@gmail.com>

> Restating my comment elsewhere...  why do we even need to do this in
> _get_virq() - I'd *really* expect this to be handled by the irq domain
> code.

> > Okay, so I've just spent a small amount of time looking at this. I think
> > the best place for this would be in *_get_virq(), using the same logic that
> > selected a *_legacy or *_linear domain in the first place. 

> I'd expect your driver to always pass a hwirq into _get_virq() here.

I actually had this thought last night.

(I really must learn to switch off in the evenings.) ;)

That's even easier then. I'll make the changes and submit.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Wed Aug  8 04:04:12 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 09:04:12 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120807170333.GV16861@opensource.wolfsonmicro.com>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
Message-ID: <20120808080411.GB4728@gmail.com>

On Tue, Aug 07, 2012 at 06:03:34PM +0100, Mark Brown wrote:
> On Tue, Aug 07, 2012 at 06:01:30PM +0100, Lee Jones wrote:
> 
> > Okay, so I've just spent a small amount of time looking at this. I think
> > the best place for this would be in *_get_virq(), using the same logic that
> > selected a *_legacy or *_linear domain in the first place. The only thing 
> > the domain can test for is the 'type' of domain and the requested IRQ. This
> > is where the issue lies. If a hwirq to virq conversion is requested, but a
> > virq is passed (which happens in the non-DT case) a WARN() is triggered
> > because the irq passed is bigger than first_irq + size. I think *_get_virq()
> > should ensure that only a hwirq is passed to irq_create_mapping().
> 
> > Let me know if you had other ideas.
> 
> I'd expect your driver to always pass a hwirq into _get_virq() here.

Okay, actually this isn't so easy. Currently we have:

During DT boot:
 - No platform data is passed, hence no IRQ base for AB8500 is either
 - No IRQ base means we register a Linear IRQ Domain
 - MFD sees there is no base and leaves the IRQ resource as a hwirq
 - AB8500 child devices use *_get_virq() to convert the hwirq to a virq

During non-DT boot:
 - Platform data is passed, which contains an IRQ base
 - If an IRQ base is requested we use it to register a Legacy IRQ Domain
 - MFD adds the IRQ base to the hwirq and registers it as a virq
 - AB8500 child devices use *_get_virq() to convert virq to virq - *ERROR*

I guess my suggestion falls-back to placing logic in *_get_virq() to only
call irq_create_mapping() when when !ab8500->irq_base.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Wed Aug  8 04:16:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 08:16:28 +0000
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <20120807.162923.34400427265666163.davem@davemloft.net>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
Message-ID: <201208080816.29218.arnd@arndb.de>

On Tuesday 07 August 2012, David Miller wrote:
> From: Ian Molton <ian.molton at codethink.co.uk>
> Date: Tue,  7 Aug 2012 15:34:45 +0100
> 
> > Fixed all comments.
> > 
> > * Dropped csb1724 defconfig.
> > * Added patch to remove MV643XX_ETH_SHARED_NAME and MV643XX_ETH_NAME
> > * Dropped un-necessary D-T irq fixup code
> 
> Who is going to take this series?

I'd prefer to take the entire series through the arm-soc tree from
the kirkwood maintainers. We first have to work out the bindings
though, since the current patch introduces a new one that is
incompatible with the one we were using on powerpc with
open firmware before.

	Arnd


From arnd at arndb.de  Wed Aug  8 04:28:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 08:28:35 +0000
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between DT
 and non-DT boots
In-Reply-To: <20120808080411.GB4728@gmail.com>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
 <20120808080411.GB4728@gmail.com>
Message-ID: <201208080828.35451.arnd@arndb.de>

On Wednesday 08 August 2012, Lee Jones wrote:
> Okay, actually this isn't so easy. Currently we have:
> 
> During DT boot:
>  - No platform data is passed, hence no IRQ base for AB8500 is either
>  - No IRQ base means we register a Linear IRQ Domain
>  - MFD sees there is no base and leaves the IRQ resource as a hwirq
>  - AB8500 child devices use *_get_virq() to convert the hwirq to a virq
> 
> During non-DT boot:
>  - Platform data is passed, which contains an IRQ base
>  - If an IRQ base is requested we use it to register a Legacy IRQ Domain
>  - MFD adds the IRQ base to the hwirq and registers it as a virq
>  - AB8500 child devices use *_get_virq() to convert virq to virq - ERROR
> 
> I guess my suggestion falls-back to placing logic in *_get_virq() to only
> call irq_create_mapping() when when !ab8500->irq_base.

In general, it seems easier to use the same domain type for both cases.
I don't think that MOP500_AB8500_VIR_GPIO_IRQ_BASE is used anywhere
else besides the .irq_base definition in board-mop500.c, so I would guess
that you can just remove that identifier and always use the linear
domain.

	Arnd


From linus.walleij at linaro.org  Wed Aug  8 04:43:06 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 10:43:06 +0200
Subject: [PATCH] pinctrl/nomadik: add ASIC DB8450 pinctrl driver
In-Reply-To: <502179EA.30301@wwwdotorg.org>
References: <1344341538-32223-1-git-send-email-linus.walleij@stericsson.com>
 <502179EA.30301@wwwdotorg.org>
Message-ID: <CACRpkdZ+SsMzAGotOVZ5HrOEQUDs-8ixBYwuLu1ff6Qe=84OdA@mail.gmail.com>

On Tue, Aug 7, 2012 at 10:26 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:

>> @@ -1722,6 +1722,8 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
>>       /* Poke in other ASIC variants here */
>>       if (version == PINCTRL_NMK_DB8500)
>>               nmk_pinctrl_db8500_init(&npct->soc);
>> +     if (platid->driver_data == PINCTRL_NMK_DB8540)
>> +             nmk_pinctrl_db8540_init(&npct->soc);
>
> I'm surprised one of those checks "version" and the other
> "platid->driver_data".
>
> Aside from that, this looks fine.

Bah, I'll fix this, then add your ACK.

Yours,
Linus Walleij


From u.kleine-koenig at pengutronix.de  Wed Aug  8 04:59:56 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 8 Aug 2012 10:59:56 +0200
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120803131230.GB23791@S2101-09.ap.freescale.net>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803131230.GB23791@S2101-09.ap.freescale.net>
Message-ID: <20120808085956.GB25520@pengutronix.de>

Hello Shawn,

On Fri, Aug 03, 2012 at 09:12:32PM +0800, Shawn Guo wrote:
> On Thu, Aug 02, 2012 at 05:56:25PM +0200, Uwe Kleine-K?nig wrote:
> > +			gpio3: gpio at 0x53fa4000 {
> > +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> 
> compatible = "fsl,imx35-gpio";
$ git grep fsl,imx3[15]-gpio drivers/gpio
drivers/gpio/gpio-mxc.c:        { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },

I guess that means I have to keep "fsl,imx31-gpio", right?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From davem at davemloft.net  Wed Aug  8 04:59:51 2012
From: davem at davemloft.net (David Miller)
Date: Wed, 08 Aug 2012 01:59:51 -0700 (PDT)
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208080816.29218.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
 <201208080816.29218.arnd@arndb.de>
Message-ID: <20120808.015951.1224491744100458448.davem@davemloft.net>

From: Arnd Bergmann <arnd at arndb.de>
Date: Wed, 8 Aug 2012 08:16:28 +0000

> On Tuesday 07 August 2012, David Miller wrote:
>> From: Ian Molton <ian.molton at codethink.co.uk>
>> Date: Tue,  7 Aug 2012 15:34:45 +0100
>> 
>> > Fixed all comments.
>> > 
>> > * Dropped csb1724 defconfig.
>> > * Added patch to remove MV643XX_ETH_SHARED_NAME and MV643XX_ETH_NAME
>> > * Dropped un-necessary D-T irq fixup code
>> 
>> Who is going to take this series?
> 
> I'd prefer to take the entire series through the arm-soc tree from
> the kirkwood maintainers. We first have to work out the bindings
> though, since the current patch introduces a new one that is
> incompatible with the one we were using on powerpc with
> open firmware before.

Ok.


From yliu.null at gmail.com  Wed Aug  8 05:02:08 2012
From: yliu.null at gmail.com (Yuanhan Liu)
Date: Wed,  8 Aug 2012 17:02:08 +0800
Subject: [PATCH] ARM: mmp: fix potential NULL dereference
Message-ID: <1344416528-3586-1-git-send-email-yliu.null@gmail.com>

Fix the wrong logic: we should use || instead of &&

Cc: Leo Yan <leoy at marvell.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Signed-off-by: Yuanhan Liu <yliu.null at gmail.com>
---
 arch/arm/mach-mmp/sram.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 4304f95..7e8a5a2 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev)
 	struct resource *res;
 	int ret = 0;
 
-	if (!pdata && !pdata->pool_name)
+	if (!pdata || !pdata->pool_name)
 		return -ENODEV;
 
 	info = kzalloc(sizeof(*info), GFP_KERNEL);
-- 
1.7.4.4



From linus.walleij at linaro.org  Wed Aug  8 05:11:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 11:11:45 +0200
Subject: [rtc-linux] [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for
 arch-vt8500
In-Reply-To: <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
Message-ID: <CACRpkdbYxpN9RCu8j8KMBgrb=-DsYZHq7hx-ifmHhJ0ZZcRYjw@mail.gmail.com>

On Wed, Aug 8, 2012 at 3:39 AM, Tony Prisk <linux at prisktech.co.nz> wrote:

> Converted the existing arch-vt8500 gpio to a platform_device.
> Added support for WM8505 and WM8650 GPIO controllers.
(...)
> +++ b/drivers/gpio/gpio-vt8500.c

This driver looks very one-bit-per-gpio typed. Are you sure you cannot
just reuse drivers/gpio/gpio-generic.c? Make a compelling case please...

> +struct vt8500_gpio_bank_regs {
> +       int     en;
> +       int     dir;
> +       int     data_out;
> +       int     data_in;

Why are all these members int? They should be u8 from reading your code.

> +       int     ngpio;
> +};


> +static struct vt8500_gpio_data vt8500_data = {
> +       .num_banks      = 7,
> +       .banks  = {
> +               VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
> +               VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
> +               VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
> +               VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
> +               VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
> +               VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
> +               VT8500_BANK(-1, 0x3C, 0x5C, 0x7C, 9),    /* external gpio */

What on earth are all those magic numbers?

I *guess* they're enabling some default GPIO settings etc.

But it really needs better structure, #defines for each one or
atleast include <linux/bitops.h> and say:

= BIT(4) | /* Enable GPIO pin 5 on this bank */
   BIT(5); /* Enable GPIO pin 6 on this bank */

However I suspect this is board specific and should
be taken from device tree. Please elaborate on this...

Ditto for the different instances.

(...)
> +       unsigned val;

Looks like all of these should be u8.

> +       val = readl(vt8500_chip->base + vt8500_chip->regs->en +
> +                                                       vt8500_chip->regoff);

val = (u8) readl(...);

usw

> +       val |= (1 << offset);

Use <linux/bitops.h>

val |= BIT(offset);

Apart from these remarks it's looking good...

Yours,
Linus Walleij


From peter.ujfalusi at ti.com  Wed Aug  8 05:11:30 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:30 +0300
Subject: [PATCH 00/11] ARM/ASoC: OMAP McBSP device tree support
Message-ID: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

in order to be able to add DT support for the McBSP driver which is used on all
OMAP platforms (OMAP1/2/3/4/5) I needed to make some cleanups to the stack:
- Removing callbacks used by the driver for
 - clock re-parenting (code moved to sound driver)
 - FSR/CLKR mux configuration (from now on it need to be done at board level)
   This mux is board specific and depends on the wiring.
- OMAP3 sidetone ICLK workaround has been reimplemented using the SYSCONFIG
  register's SIDLEMODE filed to prevent ICLK gating while ST is running.
- Replaced the cpu_is_omap* checks with future proof check.
- The FIFO was not enabled on OMAP2430 SoC

It has been tested on BeagleBoard (with legacy and DT boot).

The series changes McBSP related files mostly. It would be great if the whole
series could go via audio tree (if the patches are OK and it is fine by Tony).

Regards,
Peter
---
Peter Ujfalusi (11):
  ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code to ASoC driver
  ARM: OMAP2+: McBSP: Do not create legacy devices when booting with DT
    data
  ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
  ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR signal source
  ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR signal muxing
  ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux configuration code
  ASoC: omap-mcbsp: Sidetone: Use SIDLE bits in SYSCONFIG register to
    select noidle mode
  ARM: OMAP3: Remove callback for McBSP sidetone ICLK workaround
  ASoC: omap-mcbsp: Remove unused defines
  ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the code
  ASoC: omap-mcbsp: Add device tree bindings

 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 ++++++
 arch/arm/mach-omap2/board-am3517evm.c              |   13 ++
 arch/arm/mach-omap2/mcbsp.c                        |  152 +-------------------
 arch/arm/plat-omap/include/plat/mcbsp.h            |    3 -
 sound/soc/omap/am3517evm.c                         |   20 +---
 sound/soc/omap/mcbsp.c                             |   72 +++++-----
 sound/soc/omap/mcbsp.h                             |    4 +-
 sound/soc/omap/omap-mcbsp.c                        |  106 ++++++++++-----
 sound/soc/omap/omap-mcbsp.h                        |   20 ---
 9 files changed, 177 insertions(+), 258 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:31 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:31 +0300
Subject: [PATCH 01/11] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code
 to ASoC driver
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-2-git-send-email-peter.ujfalusi@ti.com>

Move the McBSP CLKS re-parenting code to ASoC driver from
arch/arm/mach-omap2.
The call fort the re-parenting has been already limited to OMAP2+ SoC in
the ASoC driver. There is no longer need to have callback function for it.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   40 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ++++++++++++++++++++----
 3 files changed, 26 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77..ebc801e 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -101,45 +101,6 @@ static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
 	return 0;
 }
 
-/* McBSP CLKS source switching function */
-static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-				   const char *src)
-{
-	struct clk *fck_src;
-	char *fck_src_name;
-	int r;
-
-	if (!strcmp(src, "clks_ext"))
-		fck_src_name = "pad_fck";
-	else if (!strcmp(src, "clks_fclk"))
-		fck_src_name = "prcm_fck";
-	else
-		return -EINVAL;
-
-	fck_src = clk_get(dev, fck_src_name);
-	if (IS_ERR_OR_NULL(fck_src)) {
-		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
-		       fck_src_name);
-		return -EINVAL;
-	}
-
-	pm_runtime_put_sync(dev);
-
-	r = clk_set_parent(clk, fck_src);
-	if (IS_ERR_VALUE(r)) {
-		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
-		       "clks", fck_src_name);
-		clk_put(fck_src);
-		return -EINVAL;
-	}
-
-	pm_runtime_get_sync(dev);
-
-	clk_put(fck_src);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -181,7 +142,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->reg_size = 4;
 		pdata->has_ccr = true;
 	}
-	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
 
 	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
 	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 1881412..0a7d5ca 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
 	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index d33c48b..d901fc0 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <plat/mcbsp.h>
 
@@ -726,19 +727,39 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 {
+	struct clk *fck_src;
 	const char *src;
+	int r;
 
 	if (fck_src_id == MCBSP_CLKS_PAD_SRC)
-		src = "clks_ext";
+		src = "pad_fck";
 	else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
-		src = "clks_fclk";
+		src = "prcm_fck";
 	else
 		return -EINVAL;
 
-	if (mcbsp->pdata->set_clk_src)
-		return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
-	else
+	fck_src = clk_get(mcbsp->dev, src);
+	if (IS_ERR_OR_NULL(fck_src)) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
 		return -EINVAL;
+	}
+
+	pm_runtime_put_sync(mcbsp->dev);
+
+	r = clk_set_parent(mcbsp->fclk, fck_src);
+	if (r) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
+			src);
+		clk_put(fck_src);
+		return r;
+	}
+
+	pm_runtime_get_sync(mcbsp->dev);
+
+	clk_put(fck_src);
+
+	return 0;
+
 }
 
 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:32 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:32 +0300
Subject: [PATCH 02/11] ARM: OMAP2+: McBSP: Do not create legacy devices when
 booting with DT data
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-3-git-send-email-peter.ujfalusi@ti.com>

Only create the devices in a legacy way if we do not have the DT data.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index ebc801e..57bd7ef 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -187,7 +188,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 
 static int __init omap2_mcbsp_init(void)
 {
-	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+	if (!of_have_populated_dt())
+		omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
 	return 0;
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:33 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:33 +0300
Subject: [PATCH 03/11] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-4-git-send-email-peter.ujfalusi@ti.com>

On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
the FIFO for the audio stack.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 57bd7ef..43899b6 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -152,7 +152,10 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
 		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
 
-	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
+		/* The FIFO has 128 locations */
+		pdata->buffer_size = 0x80;
+	} else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
 		if (id == 2)
 			/* The FIFO has 1024 + 256 locations */
 			pdata->buffer_size = 0x500;
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:35 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:35 +0300
Subject: [PATCH 05/11] ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR
 signal muxing
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-6-git-send-email-peter.ujfalusi@ti.com>

The muxing is done at board level, no need to do it in the ASoC machine
driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/am3517evm.c |   20 ++------------------
 1 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/sound/soc/omap/am3517evm.c b/sound/soc/omap/am3517evm.c
index 009533a..a997988 100644
--- a/sound/soc/omap/am3517evm.c
+++ b/sound/soc/omap/am3517evm.c
@@ -47,26 +47,10 @@ static int am3517evm_hw_params(struct snd_pcm_substream *substream,
 	/* Set the codec system clock for DAC and ADC */
 	ret = snd_soc_dai_set_sysclk(codec_dai, 0,
 			CODEC_CLOCK, SND_SOC_CLOCK_IN);
-	if (ret < 0) {
+	if (ret < 0)
 		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_CLKR_SRC_CLKX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_CLKR_SRC_CLKX\n");
-		return ret;
-	}
 
-	snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_FSR_SRC_FSX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_FSR_SRC_FSX\n");
-		return ret;
-	}
-
-	return 0;
+	return ret;
 }
 
 static struct snd_soc_ops am3517evm_ops = {
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:36 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:36 +0300
Subject: [PATCH 06/11] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux configuration
 code
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-7-git-send-email-peter.ujfalusi@ti.com>

Remove the feature to configure the CLKR/FSR mux on McBSP port with 6pin
configuration.
When moving to devicetree these callback can no longer be used in a clean
way anymore.
If a board require to change the 6pin port to work in 4pin setup it needs
to set up the mux in the board file.
For OMAP2/3:
u32 devconf0;

/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);

For OMAP4:
u32 mcbsp_pad;

/* McBSP4 CLKR/FSR signal to be connected to CLKX/FSX pin */
mcbsp_pad = omap4_ctrl_pad_readl(OMAP2_CONTROL_DEVCONF0);
mcbsp_pad |=  ((1 << 31) | (1 << 30));
omap4_ctrl_pad_writel(mcbsp_pad, OMAP2_CONTROL_DEVCONF0);

In case when the kernel is booted with DT blob the pinctrl-single will be
provided as soon as it is enabled on the platform.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   77 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ------------
 sound/soc/omap/mcbsp.h                  |    3 -
 sound/soc/omap/omap-mcbsp.c             |   32 +------------
 sound/soc/omap/omap-mcbsp.h             |    4 --
 6 files changed, 3 insertions(+), 145 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 43899b6..d57a357 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -26,8 +26,6 @@
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-#include "control.h"
-
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -35,73 +33,6 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP2_MCBSP1_CLKR_MASK;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP2_MCBSP1_CLKR_MASK;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP2_MCBSP1_FSR_MASK;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP2_MCBSP1_FSR_MASK;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-
-	return 0;
-}
-
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	/*
-	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
-	 * mux) is used */
-	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -144,14 +75,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->has_ccr = true;
 	}
 
-	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
-	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
-
-	/* On OMAP4 the McBSP4 port has 6 pin configuration */
-	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
-
 	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
 		/* The FIFO has 128 locations */
 		pdata->buffer_size = 0x80;
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 0a7d5ca..c78d90b 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
 /**
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index d901fc0..c870023 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -762,37 +762,6 @@ int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 
 }
 
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-{
-	const char *signal, *src;
-
-	if (!mcbsp->pdata->mux_signal)
-		return -EINVAL;
-
-	switch (mux) {
-	case CLKR_SRC_CLKR:
-		signal = "clkr";
-		src = "clkr";
-		break;
-	case CLKR_SRC_CLKX:
-		signal = "clkr";
-		src = "clkx";
-		break;
-	case FSR_SRC_FSR:
-		signal = "fsr";
-		src = "fsr";
-		break;
-	case FSR_SRC_FSX:
-		signal = "fsr";
-		src = "fsx";
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
-}
-
 #define max_thres(m)			(mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)		((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)					\
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index 262a615..49a6725 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -334,9 +334,6 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
 /* McBSP functional clock source changing function */
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
 
-/* McBSP signal muxing API */
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux);
-
 /* Sidetone specific API */
 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain);
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 1046083..5061594 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -516,21 +516,9 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 			return -EBUSY;
 	}
 
-	if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
-		mcbsp->in_freq = freq;
-		regs->srgr2	&= ~CLKSM;
-		regs->pcr0	&= ~SCLKME;
-	} else if (cpu_class_is_omap1()) {
-		/*
-		 * McBSP CLKR/FSR signal muxing functions are only available on
-		 * OMAP2 or newer versions
-		 */
-		return -EINVAL;
-	}
+	mcbsp->in_freq = freq;
+	regs->srgr2 &= ~CLKSM;
+	regs->pcr0 &= ~SCLKME;
 
 	switch (clk_id) {
 	case OMAP_MCBSP_SYSCLK_CLK:
@@ -558,20 +546,6 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 		regs->pcr0	|= SCLKME;
 		break;
-
-
-	case OMAP_MCBSP_CLKR_SRC_CLKR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
-		break;
-	case OMAP_MCBSP_CLKR_SRC_CLKX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
-		break;
 	default:
 		err = -ENODEV;
 	}
diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index f877b16..baebcee 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -32,10 +32,6 @@ enum omap_mcbsp_clksrg_clk {
 	OMAP_MCBSP_SYSCLK_CLK,		/* Internal ICLK */
 	OMAP_MCBSP_SYSCLK_CLKX_EXT,	/* External CLKX pin */
 	OMAP_MCBSP_SYSCLK_CLKR_EXT,	/* External CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKR,	/* CLKR from CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKX,	/* CLKR from CLKX pin */
-	OMAP_MCBSP_FSR_SRC_FSR,		/* FSR from FSR pin */
-	OMAP_MCBSP_FSR_SRC_FSX,		/* FSR from FSX pin */
 };
 
 /* McBSP dividers */
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:37 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:37 +0300
Subject: [PATCH 07/11] ASoC: omap-mcbsp: Sidetone: Use SIDLE bits in SYSCONFIG
 register to select noidle mode
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-8-git-send-email-peter.ujfalusi@ti.com>

Instead of the callback (which modifies control module register) use the
McBSP module's SYSCONFIG register to disable smart-idle mode when the
sidetone is enabled.
Store the original SIDLEMODE configuration and restore it when the sidetone
has been disabled.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/mcbsp.c |   18 ++++++++++++++----
 sound/soc/omap/mcbsp.h |    1 +
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index c870023..e008898 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -257,8 +257,15 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
 	unsigned int w;
 
-	if (mcbsp->pdata->enable_st_clock)
-		mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
+	/*
+	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
+	 * are enabled or sidetones start sounding ugly.
+	 */
+	w = MCBSP_READ(mcbsp, SYSCON);
+	mcbsp->st_data->mcbsp_sidle = (w >> 3) & 0x3;
+	w &= ~SIDLEMODE(0x3);
+	w |= SIDLEMODE(0x1);
+	MCBSP_WRITE(mcbsp, SYSCON, w);
 
 	/* Enable McBSP Sidetone */
 	w = MCBSP_READ(mcbsp, SSELCR);
@@ -279,8 +286,11 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
 	w = MCBSP_READ(mcbsp, SSELCR);
 	MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 
-	if (mcbsp->pdata->enable_st_clock)
-		mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
+	/* Restore the SIDLEMODE as it was before the ST has been started */
+	w = MCBSP_READ(mcbsp, SYSCON);
+	w &= ~SIDLEMODE(0x3);
+	w |= SIDLEMODE(mcbsp->st_data->mcbsp_sidle);
+	MCBSP_WRITE(mcbsp, SYSCON, w);
 }
 
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index 49a6725..ba82846 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -280,6 +280,7 @@ struct omap_mcbsp_st_data {
 	int nr_taps;	/* Number of filter coefficients in use */
 	s16 ch0gain;
 	s16 ch1gain;
+	unsigned int mcbsp_sidle;
 };
 
 struct omap_mcbsp {
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:38 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:38 +0300
Subject: [PATCH 08/11] ARM: OMAP3: Remove callback for McBSP sidetone ICLK
 workaround
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>

We can achieve the same result with SIDLEMODE field within McBSP SYSCONFIG
register.
The ASoC driver has been modified to use this method and we can now remove
the workaround using the control module register.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   26 --------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 2 files changed, 0 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index d57a357..996a15f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -26,31 +26,6 @@
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-/*
- * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
- * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
- */
-#include "cm2xxx_3xxx.h"
-#include "cm-regbits-34xx.h"
-
-static int omap3_enable_st_clock(unsigned int id, bool enable)
-{
-	unsigned int w;
-
-	/*
-	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
-	 * are enabled or sidetones start sounding ugly.
-	 */
-	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-	if (enable)
-		w &= ~(1 << (id - 2));
-	else
-		w |= 1 << (id - 2);
-	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
-
-	return 0;
-}
-
 static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 {
 	int id, count = 1;
@@ -98,7 +73,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	if (oh->dev_attr) {
 		oh_device[1] = omap_hwmod_lookup((
 		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
-		pdata->enable_st_clock = omap3_enable_st_clock;
 		count++;
 	}
 	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index c78d90b..698ccd8 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -46,7 +46,6 @@ struct omap_mcbsp_platform_data {
 	/* McBSP platform and instance specific features */
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
-	int (*enable_st_clock)(unsigned int, bool);
 };
 
 /**
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:39 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:39 +0300
Subject: [PATCH 09/11] ASoC: omap-mcbsp: Remove unused defines
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-10-git-send-email-peter.ujfalusi@ti.com>

NUM_LINKS is no longer in use by the code.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/omap-mcbsp.h |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index baebcee..ba8386a 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -39,22 +39,6 @@ enum omap_mcbsp_div {
 	OMAP_MCBSP_CLKGDV,		/* Sample rate generator divider */
 };
 
-#if defined(CONFIG_SOC_OMAP2420)
-#define NUM_LINKS	2
-#endif
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-#undef  NUM_LINKS
-#define NUM_LINKS	3
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#undef  NUM_LINKS
-#define NUM_LINKS	4
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430)
-#undef  NUM_LINKS
-#define NUM_LINKS	5
-#endif
-
 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd);
 
 #endif
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:40 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:40 +0300
Subject: [PATCH 10/11] ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the
 code
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-11-git-send-email-peter.ujfalusi@ti.com>

We can use the has_ccr flag to replace the cpu_is_omap* checks.
This provides future proof implementation and we do not need to update the
code if new OMAP revision starts to use the McBSP driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/omap-mcbsp.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 5061594..b9770ee 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -398,12 +398,14 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	/* Generic McBSP register settings */
 	regs->spcr2	|= XINTM(3) | FREE;
 	regs->spcr1	|= RINTM(3);
-	/* RFIG and XFIG are not defined in 34xx */
-	if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
+	/* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
+	if (!mcbsp->pdata->has_ccr) {
 		regs->rcr2	|= RFIG;
 		regs->xcr2	|= XFIG;
 	}
-	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+
+	/* Configure XCCR/RCCR only for revisions which have ccr registers */
+	if (mcbsp->pdata->has_ccr) {
 		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 	}
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:41 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:41 +0300
Subject: [PATCH 11/11] ASoC: omap-mcbsp: Add device tree bindings
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-12-git-send-email-peter.ujfalusi@ti.com>

Device tree support for McBSP modules on OMAP2+ SoC.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 +++++++++++++
 sound/soc/omap/omap-mcbsp.c                        |   66 +++++++++++++++++++-
 2 files changed, 110 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
new file mode 100644
index 0000000..447cb13
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -0,0 +1,45 @@
+* Texas Instruments OMAP2+ McBSP module
+
+Required properties:
+- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
+	      "ti,omap2430-mcbsp" for McBSP on OMAP2430
+	      "ti,omap3-mcbsp" for McBSP on OMAP3
+	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
+- reg: Register location and size, for OMAP4+ as an array:
+       <MPU access base address, size>,
+       <L3 interconnect address, size>;
+- interrupts: Interrupt numbers for the McBSP port, as an array in case the
+	      McBSP IP have more interrupt lines:
+	<OCP compliant irq>,
+	<TX irq>,
+	<RX irq>;
+- interrupt-parent: The parent interrupt controller
+- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
+- ti,hwmods: Name of the hwmod associated to the McBSP port
+
+Sidetone support for OMAP3 McBSP2 and 3 ports:
+- sidetone { }: Within this section the following parameters are required:
+- reg: Register location and size for the ST block
+- interrupts: The interrupt number for the ST block
+- interrupt-parent: The parent interrupt controller for the ST block
+
+Example:
+
+mcbsp2: mcbsp at 49022000 {
+	compatible = "ti,omap3-mcbsp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0x49022000 0xff>;
+	interrupts = <0 17 0x4>, /* OCP compliant interrup */
+		     <0 62 0x4>, /* TX interrup */
+		     <0 63 0x4>; /* RX interrup */
+	interrupt-parent = <&intc>;
+	ti,buffer-size = <1280>;
+	ti,hwmods = "mcbsp2";
+
+	sidetone {
+		reg = <0x49028000 0xff>;
+		interrupts = <0 4 0x4>;
+		interrupt-parent = <&intc>;
+	};
+};
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index b9770ee..2e1750e 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -26,6 +26,8 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -737,13 +739,74 @@ int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 }
 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 
+static struct omap_mcbsp_platform_data omap2420_pdata = {
+	.reg_step = 4,
+	.reg_size = 2,
+};
+
+static struct omap_mcbsp_platform_data omap2430_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+};
+
+static struct omap_mcbsp_platform_data omap3_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static struct omap_mcbsp_platform_data omap4_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static const struct of_device_id omap_mcbsp_of_match[] = {
+	{
+		.compatible = "ti,omap2420-mcbsp",
+		.data = &omap2420_pdata,
+	},
+	{
+		.compatible = "ti,omap2430-mcbsp",
+		.data = &omap2430_pdata,
+	},
+	{
+		.compatible = "ti,omap3-mcbsp",
+		.data = &omap3_pdata,
+	},
+	{
+		.compatible = "ti,omap4-mcbsp",
+		.data = &omap4_pdata,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
+
 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 {
 	struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 	struct omap_mcbsp *mcbsp;
+	const struct of_device_id *match;
 	int ret;
 
-	if (!pdata) {
+	match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
+	if (match) {
+		struct device_node *node = pdev->dev.of_node;
+		int buffer_size;
+
+		pdata = devm_kzalloc(&pdev->dev,
+				     sizeof(struct omap_mcbsp_platform_data),
+				     GFP_KERNEL);
+		if (!pdata)
+			return -ENOMEM;
+
+		memcpy(pdata, match->data, sizeof(*pdata));
+		if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
+			pdata->buffer_size = buffer_size;
+	} else if (!pdata) {
 		dev_err(&pdev->dev, "missing platform data.\n");
 		return -EINVAL;
 	}
@@ -785,6 +848,7 @@ static struct platform_driver asoc_mcbsp_driver = {
 	.driver = {
 			.name = "omap-mcbsp",
 			.owner = THIS_MODULE,
+			.of_match_table = omap_mcbsp_of_match,
 	},
 
 	.probe = asoc_mcbsp_probe,
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:11:34 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:11:34 +0300
Subject: [PATCH 04/11] ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR
 signal source
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344417101-5015-5-git-send-email-peter.ujfalusi@ti.com>

am3517evm board uses McBSP1 for audio with 4pin configuration.
The CLKR/FSR signals need to be connected to CLKX/FSX pin of the SoC in
this case.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/board-am3517evm.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f6010..592812a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -264,6 +264,16 @@ static __init void am3517_evm_musb_init(void)
 	usb_musb_init(&musb_board_data);
 }
 
+static __init void am3517_evm_mcbsp1_init(void)
+{
+	u32 devconf0;
+
+	/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
+	devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
+	omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
+}
+
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -373,6 +383,9 @@ static void __init am3517_evm_init(void)
 	/* MUSB */
 	am3517_evm_musb_init();
 
+	/* McBSP1 */
+	am3517_evm_mcbsp1_init();
+
 	/* MMC init function */
 	omap_hsmmc_init(mmc);
 }
-- 
1.7.8.6



From arnd at arndb.de  Wed Aug  8 05:19:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 09:19:52 +0000
Subject: [rtc-linux] [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for
 arch-vt8500
In-Reply-To: <CACRpkdbYxpN9RCu8j8KMBgrb=-DsYZHq7hx-ifmHhJ0ZZcRYjw@mail.gmail.com>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
 <CACRpkdbYxpN9RCu8j8KMBgrb=-DsYZHq7hx-ifmHhJ0ZZcRYjw@mail.gmail.com>
Message-ID: <201208080919.52592.arnd@arndb.de>

On Wednesday 08 August 2012, Linus Walleij wrote:
> On Wed, Aug 8, 2012 at 3:39 AM, Tony Prisk <linux at prisktech.co.nz> wrote:
> 
> > Converted the existing arch-vt8500 gpio to a platform_device.
> > Added support for WM8505 and WM8650 GPIO controllers.
> (...)
> > +++ b/drivers/gpio/gpio-vt8500.c
> 
> This driver looks very one-bit-per-gpio typed. Are you sure you cannot
> just reuse drivers/gpio/gpio-generic.c? Make a compelling case please...
> 
> > +struct vt8500_gpio_bank_regs {
> > +       int     en;
> > +       int     dir;
> > +       int     data_out;
> > +       int     data_in;
> 
> Why are all these members int? They should be u8 from reading your code.
> 
> > +       int     ngpio;
> > +};

Not necessarily 8 bit, but definitely unsigned.

> > +static struct vt8500_gpio_data vt8500_data = {
> > +       .num_banks      = 7,
> > +       .banks  = {
> > +               VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
> > +               VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
> > +               VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
> > +               VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
> > +               VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
> > +               VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
> > +               VT8500_BANK(-1, 0x3C, 0x5C, 0x7C, 9),    /* external gpio */
> 
> What on earth are all those magic numbers?
> 
> I *guess* they're enabling some default GPIO settings etc.

No, they are the register offsets you quoted above, per bank. There
is no easy way to abstract these, and I suggested putting the
values into the source code rather than describing each bank
separately in the .dtsi file.

My feeling however is that the "vt8500_chip->regoff" is wrong, which
would mean only the first bank works. The code adds the same offsets
per bank once more that it sets in this bank table.

	Arnd


From ian.molton at codethink.co.uk  Wed Aug  8 05:40:56 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Wed, 08 Aug 2012 10:40:56 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208080816.29218.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
 <201208080816.29218.arnd@arndb.de>
Message-ID: <50223428.6030506@codethink.co.uk>

On 08/08/12 09:16, Arnd Bergmann wrote:

> I'd prefer to take the entire series through the arm-soc tree from
> the kirkwood maintainers. We first have to work out the bindings
> though, since the current patch introduces a new one that is
> incompatible with the one we were using on powerpc with open firmware
> before.

Looking at the ethernet-group stuff, specifically from
arch/powerpc/boot/dts/prpmc2800.dts, which I've taken as a base for the
below:

I think we can (and should) do something similar.

Sadly, there is no code present to describe marvell,mv64360-mdio,
however the device tree looks basically sane.



        mdio at 2000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        device_type = "mdio";
                        compatible = "marvell,mv643xx-mdio";
                        PHY0: ethernet-phy at 1 {
                                device_type = "ethernet-phy";
                                compatible = "broadcom,bcm5421";
                                interrupts = <76>;      /* GPP 12 */
                                interrupt-parent = <&PIC>;
                                reg = <1>;
                        };
                        PHY1: ethernet-phy at 3 {
                                device_type = "ethernet-phy";
                                compatible = "broadcom,bcm5421";
                                interrupts = <76>;      /* GPP 12 */
                                interrupt-parent = <&PIC>;
                                reg = <3>;
                        };
                };

                ethernet-group at 2400 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "marvell,mv64360-eth-group";
                        reg = <0x2400 0x2000>;
                        ethernet at 0 {
                                device_type = "network";
                                compatible = "marvell,mv64360-eth";
                                reg = <0>;
                                interrupts = <32>;
                                interrupt-parent = <&mpic>;
                                phy = <&phy0>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                        };
                        ethernet at 1 {
                                device_type = "network";
                                compatible = "marvell,mv64360-eth";
                                reg = <1>;
                                interrupts = <33>;
                                interrupt-parent = <&mpic>;
                                phy = <&phy1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
                        };
                };



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:16 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:16 +0300
Subject: [PATCH 00/11] MFD/ASoC/Input: twl4030-audio submodule DT support
Message-ID: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

The following series adds DT support for the twl4030 audio submodule which
provides audio codec and vibra functionality.

The MFD core driver is probed via DT, it will create the needed child devices
based on the provided information in the DT blob.
Child drivers (vibra, ASoC codec) will parse the core's node if needed to get
the needed parameters for their configuration.

In the ASoC codec driver the hs_extmute callback (which was used to toggle a
GPIO line) has been removed. The codec driver will receive the GPIO number
(if it is needed on the platform) and also the level to disable the mute.

If the series is OK (and no objections from the maintainers), it would be good
if this can go via audio. Changed files are well contained within the
twl4030-audio stack so I do not expect merge issues later.

The series has been tested on BeagleBoard (with the McBSP DT series, and with
the upcoming DT audio support for BeagleBoard).

Regards,
Peter
---
Peter Ujfalusi (11):
  MFD: twl4030-audio: Clean up MODULE_* and platform_driver part
  MFD: twl4030-audio: Convert to use devm_kzalloc
  MFD: twl4030-audio: Rearange and clean-up the probe function
  MFD: twl4030-audio: Add DT support
  Input: twl4030-vibra: Support for DT booted kernel
  ASoC: twl4030: Move hs_extmute GPIO handling to driver
  ARM: OMAP/ASoC: Zoom2: Let the codec to handle the hs_extmute GPIO
  ASoC/MFD: twl4030: Remove set_hs_extmute callback from platform data
  ASoC: twl4030: Convert to use devm_kzalloc
  ASoC: twl4030: Add pointer to pdata within the private data
  ASoC: twl4030: Support for DT booted kernel

 .../devicetree/bindings/mfd/twl4030-audio.txt      |   51 +++++++++
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    9 +-
 arch/arm/mach-omap2/include/mach/board-zoom.h      |    2 -
 drivers/input/misc/twl4030-vibra.c                 |   20 +++-
 drivers/mfd/twl4030-audio.c                        |  114 +++++++++++++------
 include/linux/i2c/twl.h                            |    4 +-
 sound/soc/codecs/twl4030.c                         |  117 ++++++++++++++++----
 sound/soc/omap/zoom2.c                             |    4 -
 8 files changed, 250 insertions(+), 71 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:17 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:17 +0300
Subject: [PATCH 01/11] MFD: twl4030-audio: Clean up MODULE_* and
 platform_driver part
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-2-git-send-email-peter.ujfalusi@ti.com>

Place the MODULE_* lines in the same block and add MODULE_DESCRIPTION.
Rearange the platform_driver structure at the same time.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index 838ce4e..ac04b4f 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -250,18 +250,18 @@ static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 	return 0;
 }
 
-MODULE_ALIAS("platform:twl4030-audio");
-
 static struct platform_driver twl4030_audio_driver = {
-	.probe		= twl4030_audio_probe,
-	.remove		= __devexit_p(twl4030_audio_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "twl4030-audio",
 	},
+	.probe		= twl4030_audio_probe,
+	.remove		= __devexit_p(twl4030_audio_remove),
 };
 
 module_platform_driver(twl4030_audio_driver);
 
 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi at ti.com>");
+MODULE_DESCRIPTION("TWL4030 audio block MFD driver");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:twl4030-audio");
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:18 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:18 +0300
Subject: [PATCH 02/11] MFD: twl4030-audio: Convert to use devm_kzalloc
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-3-git-send-email-peter.ujfalusi@ti.com>

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |   15 ++++++---------
 1 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index ac04b4f..efa2d42 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -188,7 +188,8 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
 					val, TWL4030_REG_APLL_CTL);
 
-	audio = kzalloc(sizeof(struct twl4030_audio), GFP_KERNEL);
+	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
+			     GFP_KERNEL);
 	if (!audio)
 		return -ENOMEM;
 
@@ -229,22 +230,18 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		ret = -ENODEV;
 	}
 
-	if (!ret)
-		return 0;
+	if (ret) {
+		platform_set_drvdata(pdev, NULL);
+		twl4030_audio_dev = NULL;
+	}
 
-	platform_set_drvdata(pdev, NULL);
-	kfree(audio);
-	twl4030_audio_dev = NULL;
 	return ret;
 }
 
 static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 {
-	struct twl4030_audio *audio = platform_get_drvdata(pdev);
-
 	mfd_remove_devices(&pdev->dev);
 	platform_set_drvdata(pdev, NULL);
-	kfree(audio);
 	twl4030_audio_dev = NULL;
 
 	return 0;
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:19 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:19 +0300
Subject: [PATCH 03/11] MFD: twl4030-audio: Rearange and clean-up the probe
 function
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-4-git-send-email-peter.ujfalusi@ti.com>

To facilitate the device tree support the probe function need to be rearanged.
Small cleanup in the APLL frequency selection part as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |   34 ++++++++++++++++------------------
 1 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index efa2d42..ca2d669 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -169,35 +169,30 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
+			     GFP_KERNEL);
+	if (!audio)
+		return -ENOMEM;
+
+	mutex_init(&audio->mutex);
+	audio->audio_mclk = pdata->audio_mclk;
+
 	/* Configure APLL_INFREQ and disable APLL if enabled */
-	val = 0;
-	switch (pdata->audio_mclk) {
+	switch (audio->audio_mclk) {
 	case 19200000:
-		val |= TWL4030_APLL_INFREQ_19200KHZ;
+		val = TWL4030_APLL_INFREQ_19200KHZ;
 		break;
 	case 26000000:
-		val |= TWL4030_APLL_INFREQ_26000KHZ;
+		val = TWL4030_APLL_INFREQ_26000KHZ;
 		break;
 	case 38400000:
-		val |= TWL4030_APLL_INFREQ_38400KHZ;
+		val = TWL4030_APLL_INFREQ_38400KHZ;
 		break;
 	default:
 		dev_err(&pdev->dev, "Invalid audio_mclk\n");
 		return -EINVAL;
 	}
-	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
-					val, TWL4030_REG_APLL_CTL);
-
-	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
-			     GFP_KERNEL);
-	if (!audio)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, audio);
-
-	twl4030_audio_dev = pdev;
-	mutex_init(&audio->mutex);
-	audio->audio_mclk = pdata->audio_mclk;
+	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, val, TWL4030_REG_APLL_CTL);
 
 	/* Codec power */
 	audio->resource[TWL4030_AUDIO_RES_POWER].reg = TWL4030_REG_CODEC_MODE;
@@ -222,6 +217,9 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		childs++;
 	}
 
+	platform_set_drvdata(pdev, audio);
+	twl4030_audio_dev = pdev;
+
 	if (childs)
 		ret = mfd_add_devices(&pdev->dev, pdev->id, audio->cells,
 				      childs, NULL, 0);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:20 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:20 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>

Support for loading the twl4030 audio module via devicetree.
Sub devices for codec and vibra will be created as mfd devices once the
core MFD driver is loaded when the kernel is booted with a DT blob.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/mfd/twl4030-audio.txt      |   51 +++++++++++++++
 drivers/mfd/twl4030-audio.c                        |   65 +++++++++++++++++---
 2 files changed, 108 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt

diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
new file mode 100644
index 0000000..bc45025
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
@@ -0,0 +1,51 @@
+Texas Instruments TWL family (twl4030) audio module
+
+The audio module inside the TWL family consist of an audio codec and a vibra
+driver.
+
+Required properties:
+- compatible : must be "ti,twl4030-audio"
+- ti,audio_mclk: Master clock frequency used on the board. Supported
+	         frequencies: 19200000, 26000000 and 38400000
+
+Optional properties, nodes:
+
+Audio functionality:
+- codec { }: Need to be present if the audio functionality is used. Within this
+	     section the following options can be used:
+- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts
+		    from the start of the recorded sample (in ms)
+-ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise
+-ti,hs_extmute: Use external mute for HS pop reduction
+-ti,hs_extmute_gpio: Use external GPIO to control the external mute
+-ti,hs_extmute_disable_level: The desired level of the GPIO line when the
+			      external mute is disabled. valuse: 0 or 1
+-ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
+		      valid values.
+
+Vibra functionality
+- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if
+		   missing or it is 0, the vibra functionality is disabled.
+
+Example:
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl at 48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			ti,audio_mclk = <26000000>;
+
+			ti,enable-vibra = <1>;
+
+			codec {
+				ti,ramp_delay_value = <3>;
+			};
+
+		};
+	};
+};
diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index ca2d669..a4df8b3a 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -28,6 +28,8 @@
 #include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/i2c/twl.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/twl4030-audio.h>
@@ -156,15 +158,46 @@ unsigned int twl4030_audio_get_mclk(void)
 }
 EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk);
 
+static bool twl4030_audio_has_codec(struct twl4030_audio_data *pdata,
+			      struct device_node *node)
+{
+	if (pdata && pdata->codec)
+		return true;
+
+#ifdef CONFIG_OF
+	if (of_find_node_by_name(node, "codec"))
+		return true;
+#endif
+
+	return false;
+}
+
+static bool twl4030_audio_has_vibra(struct twl4030_audio_data *pdata,
+			      struct device_node *node)
+{
+	int vibra;
+
+	if (pdata && pdata->vibra)
+		return true;
+
+#ifdef CONFIG_OF
+	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
+		return true;
+#endif
+
+	return false;
+}
+
 static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 {
 	struct twl4030_audio *audio;
 	struct twl4030_audio_data *pdata = pdev->dev.platform_data;
+	struct device_node *node = pdev->dev.of_node;
 	struct mfd_cell *cell = NULL;
 	int ret, childs = 0;
 	u8 val;
 
-	if (!pdata) {
+	if (!pdata && !node) {
 		dev_err(&pdev->dev, "Platform data is missing\n");
 		return -EINVAL;
 	}
@@ -175,7 +208,12 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	mutex_init(&audio->mutex);
-	audio->audio_mclk = pdata->audio_mclk;
+	if (pdata)
+		audio->audio_mclk = pdata->audio_mclk;
+#ifdef CONFIG_OF
+	else
+		of_property_read_u32(node, "ti,audio_mclk", &audio->audio_mclk);
+#endif
 
 	/* Configure APLL_INFREQ and disable APLL if enabled */
 	switch (audio->audio_mclk) {
@@ -202,18 +240,22 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 	audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL;
 	audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN;
 
-	if (pdata->codec) {
+	if (twl4030_audio_has_codec(pdata, node)) {
 		cell = &audio->cells[childs];
 		cell->name = "twl4030-codec";
-		cell->platform_data = pdata->codec;
-		cell->pdata_size = sizeof(*pdata->codec);
+		if (pdata) {
+			cell->platform_data = pdata->codec;
+			cell->pdata_size = sizeof(*pdata->codec);
+		}
 		childs++;
 	}
-	if (pdata->vibra) {
+	if (twl4030_audio_has_vibra(pdata, node)) {
 		cell = &audio->cells[childs];
 		cell->name = "twl4030-vibra";
-		cell->platform_data = pdata->vibra;
-		cell->pdata_size = sizeof(*pdata->vibra);
+		if (pdata) {
+			cell->platform_data = pdata->vibra;
+			cell->pdata_size = sizeof(*pdata->vibra);
+		}
 		childs++;
 	}
 
@@ -245,10 +287,17 @@ static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id twl4030_audio_of_match[] = {
+	{.compatible = "ti,twl4030-audio", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, twl4030_audio_of_match);
+
 static struct platform_driver twl4030_audio_driver = {
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "twl4030-audio",
+		.of_match_table = twl4030_audio_of_match,
 	},
 	.probe		= twl4030_audio_probe,
 	.remove		= __devexit_p(twl4030_audio_remove),
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:21 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:21 +0300
Subject: [PATCH 05/11] Input: twl4030-vibra: Support for DT booted kernel
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-6-git-send-email-peter.ujfalusi@ti.com>

Add support when the kernel has been booted with DT blob. In this case the
pdata is NULL, we need to reach up to the core node and check if the codec
part has been enabled to determine if we need to coexist with the codec or
not.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/input/misc/twl4030-vibra.c |   20 ++++++++++++++++++--
 1 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/input/misc/twl4030-vibra.c b/drivers/input/misc/twl4030-vibra.c
index d1e1a7e..2cfc6c7 100644
--- a/drivers/input/misc/twl4030-vibra.c
+++ b/drivers/input/misc/twl4030-vibra.c
@@ -26,6 +26,7 @@
 #include <linux/module.h>
 #include <linux/jiffies.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/workqueue.h>
 #include <linux/i2c/twl.h>
 #include <linux/mfd/twl4030-audio.h>
@@ -194,13 +195,28 @@ static int twl4030_vibra_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(twl4030_vibra_pm_ops,
 			 twl4030_vibra_suspend, twl4030_vibra_resume);
 
+static bool twl4030_vibra_check_coexist(struct twl4030_vibra_data *pdata,
+			      struct device_node *node)
+{
+	if (pdata && pdata->coexist)
+		return true;
+
+#ifdef CONFIG_OF
+	if (of_find_node_by_name(node, "codec"))
+		return true;
+#endif
+
+	return false;
+}
+
 static int __devinit twl4030_vibra_probe(struct platform_device *pdev)
 {
 	struct twl4030_vibra_data *pdata = pdev->dev.platform_data;
+	struct device_node *twl4030_core_node = pdev->dev.parent->of_node;
 	struct vibra_info *info;
 	int ret;
 
-	if (!pdata) {
+	if (!pdata && !twl4030_core_node) {
 		dev_dbg(&pdev->dev, "platform_data not available\n");
 		return -EINVAL;
 	}
@@ -210,7 +226,7 @@ static int __devinit twl4030_vibra_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	info->dev = &pdev->dev;
-	info->coexist = pdata->coexist;
+	info->coexist = twl4030_vibra_check_coexist(pdata, twl4030_core_node);
 	INIT_WORK(&info->play_work, vibra_play_work);
 
 	info->input_dev = input_allocate_device();
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:22 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:22 +0300
Subject: [PATCH 06/11] ASoC: twl4030: Move hs_extmute GPIO handling to driver
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-7-git-send-email-peter.ujfalusi@ti.com>

The external mute (if it is in use) is handled by a GPIO line. Prepare to
remove the set_hs_extmute callback and replace it with two sets of platform
data:
hs_extmute_gpio: the GPIO number to use for external mute
hs_extmute_disable_level: the GPIO level to use when the external mute is
not enabled.

The codec driver can handle the external mute functionality based on these
parameters and when the users of set_hs_extmute has been converted the
callback can be removed.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/i2c/twl.h    |    6 +++++-
 sound/soc/codecs/twl4030.c |   36 ++++++++++++++++++++++++++++++++++--
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 7ea898c..75ce6d1 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -666,7 +666,11 @@ struct twl4030_codec_data {
 	unsigned int check_defaults:1;
 	unsigned int reset_registers:1;
 	unsigned int hs_extmute:1;
-	void (*set_hs_extmute)(int mute);
+	void (*set_hs_extmute)(int mute); /* Deprecated, use hs_extmute_gpio and
+					     hs_extmute_disable_level */
+	int hs_extmute_gpio;
+	unsigned int hs_extmute_disable_level:1; /* the GPIO state to disable
+						    the extmute */
 };
 
 struct twl4030_vibra_data {
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 391fcfc..0630040 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -28,6 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c/twl.h>
 #include <linux/slab.h>
+#include <linux/gpio.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -302,6 +303,24 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
 	u8 reg, byte;
 	int i = 0;
 
+	if (pdata && pdata->hs_extmute &&
+	    gpio_is_valid(pdata->hs_extmute_gpio)) {
+		int ret, level;
+
+		if (!pdata->hs_extmute_gpio)
+			dev_warn(codec->dev,
+				 "Extmute GPIO is 0 is this correct?\n");
+
+		level = pdata->hs_extmute_disable_level;
+		ret = gpio_request_one(pdata->hs_extmute_gpio, level ?
+				       GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
+				       "hs_extmute");
+		if (ret) {
+			dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
+			pdata->hs_extmute_gpio = -1;
+		}
+	}
+
 	/* Check defaults, if instructed before anything else */
 	if (pdata && pdata->check_defaults)
 		twl4030_check_defaults(codec);
@@ -748,7 +767,11 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 	/* Enable external mute control, this dramatically reduces
 	 * the pop-noise */
 	if (pdata && pdata->hs_extmute) {
-		if (pdata->set_hs_extmute) {
+		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
+			gpio_set_value(pdata->hs_extmute_gpio,
+				       !pdata->hs_extmute_disable_level);
+		} else if (pdata->set_hs_extmute) {
+			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
 			pdata->set_hs_extmute(1);
 		} else {
 			hs_pop |= TWL4030_EXTMUTE;
@@ -786,7 +809,11 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 
 	/* Disable external mute */
 	if (pdata && pdata->hs_extmute) {
-		if (pdata->set_hs_extmute) {
+		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
+			gpio_set_value(pdata->hs_extmute_gpio,
+				       pdata->hs_extmute_disable_level);
+		} else if (pdata->set_hs_extmute) {
+			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
 			pdata->set_hs_extmute(0);
 		} else {
 			hs_pop &= ~TWL4030_EXTMUTE;
@@ -2230,12 +2257,17 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 
 static int twl4030_soc_remove(struct snd_soc_codec *codec)
 {
+	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
 	twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
 	kfree(twl4030);
+
+	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
+		gpio_free(pdata->hs_extmute_gpio);
+
 	return 0;
 }
 
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:23 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:23 +0300
Subject: [PATCH 07/11] ARM: OMAP/ASoC: Zoom2: Let the codec to handle the
 hs_extmute GPIO
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-8-git-send-email-peter.ujfalusi@ti.com>

Remove the use of set_hs_extmute callback and let the codec driver to
handle the extmute GPIO.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/board-zoom-peripherals.c  |    9 ++-------
 arch/arm/mach-omap2/include/mach/board-zoom.h |    2 --
 sound/soc/omap/zoom2.c                        |    4 ----
 3 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index b797cb2..a7d3b04 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -34,6 +34,7 @@
 #include "common-board-devices.h"
 
 #define OMAP_ZOOM_WLAN_PMENA_GPIO	(101)
+#define ZOOM2_HEADSET_EXTMUTE_GPIO	(153)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO		(162)
 
 #define LCD_PANEL_ENABLE_GPIO		(7 + OMAP_MAX_GPIO_LINES)
@@ -244,12 +245,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
 	return ret;
 }
 
-/* EXTMUTE callback function */
-static void zoom2_set_hs_extmute(int mute)
-{
-	gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
-}
-
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
 	.gpio_base	= OMAP_MAX_GPIO_LINES,
 	.irq_base	= TWL4030_GPIO_IRQ_BASE,
@@ -279,7 +274,7 @@ static int __init omap_i2c_init(void)
 
 		codec_data->ramp_delay_value = 3;	/* 161 ms */
 		codec_data->hs_extmute = 1;
-		codec_data->set_hs_extmute = zoom2_set_hs_extmute;
+		codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO;
 	}
 	omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
 	omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 775fdc3..2e94869 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -8,5 +8,3 @@
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
 extern void __init zoom_display_init(void);
-
-#define ZOOM2_HEADSET_EXTMUTE_GPIO	153
diff --git a/sound/soc/omap/zoom2.c b/sound/soc/omap/zoom2.c
index 920e0d9..df97a41 100644
--- a/sound/soc/omap/zoom2.c
+++ b/sound/soc/omap/zoom2.c
@@ -191,9 +191,6 @@ static int __init zoom2_soc_init(void)
 	BUG_ON(gpio_request(ZOOM2_HEADSET_MUX_GPIO, "hs_mux") < 0);
 	gpio_direction_output(ZOOM2_HEADSET_MUX_GPIO, 0);
 
-	BUG_ON(gpio_request(ZOOM2_HEADSET_EXTMUTE_GPIO, "ext_mute") < 0);
-	gpio_direction_output(ZOOM2_HEADSET_EXTMUTE_GPIO, 0);
-
 	return 0;
 
 err1:
@@ -207,7 +204,6 @@ module_init(zoom2_soc_init);
 static void __exit zoom2_soc_exit(void)
 {
 	gpio_free(ZOOM2_HEADSET_MUX_GPIO);
-	gpio_free(ZOOM2_HEADSET_EXTMUTE_GPIO);
 
 	platform_device_unregister(zoom2_snd_device);
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:24 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:24 +0300
Subject: [PATCH 08/11] ASoC/MFD: twl4030: Remove set_hs_extmute callback from
 platform data
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-9-git-send-email-peter.ujfalusi@ti.com>

We no longer have users for the set_hs_extmute callback which has been
replaced by hs_extmute_gpio/hs_extmute_disable_level parameters so the
codec driver can handle the external mute if it is needed by the board.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/i2c/twl.h    |    2 --
 sound/soc/codecs/twl4030.c |    6 ------
 2 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 75ce6d1..c9c1fd2 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -666,8 +666,6 @@ struct twl4030_codec_data {
 	unsigned int check_defaults:1;
 	unsigned int reset_registers:1;
 	unsigned int hs_extmute:1;
-	void (*set_hs_extmute)(int mute); /* Deprecated, use hs_extmute_gpio and
-					     hs_extmute_disable_level */
 	int hs_extmute_gpio;
 	unsigned int hs_extmute_disable_level:1; /* the GPIO state to disable
 						    the extmute */
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 0630040..1247c4a 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -770,9 +770,6 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
 			gpio_set_value(pdata->hs_extmute_gpio,
 				       !pdata->hs_extmute_disable_level);
-		} else if (pdata->set_hs_extmute) {
-			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
-			pdata->set_hs_extmute(1);
 		} else {
 			hs_pop |= TWL4030_EXTMUTE;
 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
@@ -812,9 +809,6 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
 			gpio_set_value(pdata->hs_extmute_gpio,
 				       pdata->hs_extmute_disable_level);
-		} else if (pdata->set_hs_extmute) {
-			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
-			pdata->set_hs_extmute(0);
 		} else {
 			hs_pop &= ~TWL4030_EXTMUTE;
 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:25 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:25 +0300
Subject: [PATCH 09/11] ASoC: twl4030: Convert to use devm_kzalloc
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-10-git-send-email-peter.ujfalusi@ti.com>

Allocate the private data with devm_kzalloc.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 1247c4a..6a00c01 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -2235,7 +2235,8 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 {
 	struct twl4030_priv *twl4030;
 
-	twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
+	twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
+			       GFP_KERNEL);
 	if (twl4030 == NULL) {
 		dev_err(codec->dev, "Can not allocate memory\n");
 		return -ENOMEM;
@@ -2257,7 +2258,6 @@ static int twl4030_soc_remove(struct snd_soc_codec *codec)
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
 	twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
-	kfree(twl4030);
 
 	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
 		gpio_free(pdata->hs_extmute_gpio);
-- 
1.7.8.6



From ian.molton at codethink.co.uk  Wed Aug  8 05:42:05 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Wed, 08 Aug 2012 10:42:05 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <50223428.6030506@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
 <201208080816.29218.arnd@arndb.de> <50223428.6030506@codethink.co.uk>
Message-ID: <5022346D.1000900@codethink.co.uk>

Ignore, Hit send whilst editing, by mistake. Sorry for the noise guys.

-Ian



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:26 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:26 +0300
Subject: [PATCH 10/11] ASoC: twl4030: Add pointer to pdata within the private
 data
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-11-git-send-email-peter.ujfalusi@ti.com>

Access the pdata via a pointer within the twl4030_priv structure.
In preparation for DeviceTree support.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 6a00c01..bf0240d 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -153,8 +153,7 @@ struct twl4030_priv {
 	u8 predrivel_enabled, predriver_enabled;
 	u8 carkitl_enabled, carkitr_enabled;
 
-	/* Delay needed after enabling the digimic interface */
-	unsigned int digimic_delay;
+	struct twl4030_codec_data *pdata;
 };
 
 /*
@@ -350,7 +349,7 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
 	if (!pdata)
 		return;
 
-	twl4030->digimic_delay = pdata->digimic_delay;
+	twl4030->pdata = pdata;
 
 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
 	reg &= ~TWL4030_RAMP_DELAY;
@@ -751,9 +750,9 @@ static int aif_event(struct snd_soc_dapm_widget *w,
 
 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 {
-	struct twl4030_codec_data *pdata = codec->dev->platform_data;
 	unsigned char hs_gain, hs_pop;
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 	/* Base values for ramp delay calculation: 2^19 - 2^26 */
 	unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
 				    8388608, 16777216, 33554432, 67108864};
@@ -868,9 +867,10 @@ static int digimic_event(struct snd_soc_dapm_widget *w,
 		struct snd_kcontrol *kcontrol, int event)
 {
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 
-	if (twl4030->digimic_delay)
-		twl4030_wait_ms(twl4030->digimic_delay);
+	if (pdata && pdata->digimic_delay)
+		twl4030_wait_ms(pdata->digimic_delay);
 	return 0;
 }
 
@@ -2252,8 +2252,8 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 
 static int twl4030_soc_remove(struct snd_soc_codec *codec)
 {
-	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:41:27 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:41:27 +0300
Subject: [PATCH 11/11] ASoC: twl4030: Support for DT booted kernel
In-Reply-To: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344418887-5262-12-git-send-email-peter.ujfalusi@ti.com>

When the kernel has been booted with DT blob the platform data is NULL for
the driver.
We need to construct the pdata based on the DT information for runtime use.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |   67 ++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 59 insertions(+), 8 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index bf0240d..68495a2 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -26,6 +26,7 @@
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/i2c/twl.h>
 #include <linux/slab.h>
 #include <linux/gpio.h>
@@ -295,13 +296,70 @@ static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
 
 }
 
-static void twl4030_init_chip(struct snd_soc_codec *codec)
+static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
+				   struct device_node *node)
+{
+	int value;
+
+	of_property_read_u32(node, "ti,digimic_delay",
+			     &pdata->digimic_delay);
+	of_property_read_u32(node, "ti,ramp_delay_value",
+			     &pdata->ramp_delay_value);
+	of_property_read_u32(node, "ti,offset_cncl_path",
+			     &pdata->offset_cncl_path);
+	if (!of_property_read_u32(node, "ti,hs_extmute", &value))
+		pdata->hs_extmute = value;
+	else
+		pdata->hs_extmute = 0;
+
+	if (pdata->hs_extmute) {
+		int ret = of_property_read_u32(node, "ti,hs_extmute_gpio",
+					       &pdata->hs_extmute_gpio);
+		if (!ret) {
+			if (!of_property_read_u32(node,
+						  "ti,hs_extmute_disable_level",
+						  &value)) {
+				pdata->hs_extmute_disable_level = value;
+			}
+		} else {
+			pdata->hs_extmute_gpio = -1;
+		}
+	}
+}
+
+static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
 {
 	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
+	struct device_node *twl4030_codec_node = NULL;
+
+#ifdef CONFIG_OF
+	twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
+						  "codec");
+#endif
+
+	if (!pdata && twl4030_codec_node) {
+		pdata = devm_kzalloc(codec->dev,
+				     sizeof(struct twl4030_codec_data),
+				     GFP_KERNEL);
+		if (!pdata) {
+			dev_err(codec->dev, "Can not allocate memory\n");
+			return NULL;
+		}
+		twl4030_setup_pdata_of(pdata, twl4030_codec_node);
+	}
+
+	return pdata;
+}
+
+static void twl4030_init_chip(struct snd_soc_codec *codec)
+{
+	struct twl4030_codec_data *pdata;
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 	u8 reg, byte;
 	int i = 0;
 
+	pdata = twl4030_get_pdata(codec);
+
 	if (pdata && pdata->hs_extmute &&
 	    gpio_is_valid(pdata->hs_extmute_gpio)) {
 		int ret, level;
@@ -2288,13 +2346,6 @@ static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
 
 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
 {
-	struct twl4030_codec_data *pdata = pdev->dev.platform_data;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "platform_data is missing\n");
-		return -EINVAL;
-	}
-
 	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
 			twl4030_dai, ARRAY_SIZE(twl4030_dai));
 }
-- 
1.7.8.6



From broonie at opensource.wolfsonmicro.com  Wed Aug  8 05:49:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 10:49:52 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120808080411.GB4728@gmail.com>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
 <20120808080411.GB4728@gmail.com>
Message-ID: <20120808094952.GH16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 09:04:12AM +0100, Lee Jones wrote:

> During non-DT boot:
>  - Platform data is passed, which contains an IRQ base
>  - If an IRQ base is requested we use it to register a Legacy IRQ Domain
>  - MFD adds the IRQ base to the hwirq and registers it as a virq

Just don't do this step - the only reason to do it is for mapping back
into a linear domain but if you're going to do this...

>  - AB8500 child devices use *_get_virq() to convert virq to virq - *ERROR*

...then it's redundant.  The mapping functions in the domain code
replace this functionality.


From peter.ujfalusi at ti.com  Wed Aug  8 05:54:06 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:54:06 +0300
Subject: [PATCH 0/4] ASoC/OMAP: ASoC machine driver for simple SoC with twl4030
Message-ID: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Create new unified ASoC machine driver (with DT support) for boards using simple
configuration for audio and using the twl4030 codec.
This driver will replace the following machine drivers (since they are basically
the same):
igep0020, omap3beagle, omap3evm and overo.

This series will switch the boards I can identify to use the new unified ASoC
machine driver.

Changes under arch/arm/mach-omap2/ are trivial, I don't expect merge issues
later. If it is OK for the maintainers I would like this to go via audio tree
(with the McBSP and the twl4030-audio stack DT support).

The series has been tested on BeagleBoard (with the McBSP and twl4030-audio DT
support).

Regards,
Peter
---
Peter Ujfalusi (4):
  ASoC: omap-twl4030: Simple machine driver for TI SoC with twl4030
    codec
  ARM: OMAP: twl-common: Add helper function to register the
    omap-twl4030 audio driver
  ARM: OMAP3: Switch to use the unified audio driver (omap-twl4030) for
    selected boards
  ASoC: Remove obsolete OMAP3 machine drivers

 .../devicetree/bindings/sound/omap-twl4030.txt     |   19 ++
 arch/arm/mach-omap2/board-cm-t35.c                 |    1 +
 arch/arm/mach-omap2/board-devkit8000.c             |    1 +
 arch/arm/mach-omap2/board-igep0020.c               |    1 +
 arch/arm/mach-omap2/board-omap3beagle.c            |    1 +
 arch/arm/mach-omap2/board-omap3evm.c               |    1 +
 arch/arm/mach-omap2/board-overo.c                  |    1 +
 arch/arm/mach-omap2/twl-common.c                   |   28 +++
 arch/arm/mach-omap2/twl-common.h                   |    2 +
 include/linux/platform_data/omap-twl4030.h         |   33 +++
 sound/soc/omap/Kconfig                             |   48 ++---
 sound/soc/omap/Makefile                            |   10 +-
 sound/soc/omap/igep0020.c                          |  120 -----------
 sound/soc/omap/omap-twl4030.c                      |  219 ++++++++++++++++++++
 sound/soc/omap/omap3beagle.c                       |  150 -------------
 sound/soc/omap/omap3evm.c                          |  118 -----------
 sound/soc/omap/overo.c                             |  122 -----------
 17 files changed, 322 insertions(+), 553 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-twl4030.txt
 create mode 100644 include/linux/platform_data/omap-twl4030.h
 delete mode 100644 sound/soc/omap/igep0020.c
 create mode 100644 sound/soc/omap/omap-twl4030.c
 delete mode 100644 sound/soc/omap/omap3beagle.c
 delete mode 100644 sound/soc/omap/omap3evm.c
 delete mode 100644 sound/soc/omap/overo.c

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:54:07 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:54:07 +0300
Subject: [PATCH 1/4] ASoC: omap-twl4030: Simple machine driver for TI SoC with
 twl4030 codec
In-Reply-To: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344419650-5389-2-git-send-email-peter.ujfalusi@ti.com>

Machine driver to handle simple devices using twl4030 as audio codec.
The driver supports the following boards:
- Beagleboard or Devkit8000
- Gumstix Overo or CompuLab CM-T35/CM-T3730
- IGEP v2
- OMAP3EVM

All of these boards can be switched to use this driver since their setup is
identical.
Devicetree support for the omap-twl4030 machine driver also implemented.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/sound/omap-twl4030.txt     |   19 ++
 include/linux/platform_data/omap-twl4030.h         |   33 +++
 sound/soc/omap/Kconfig                             |   13 ++
 sound/soc/omap/Makefile                            |    2 +
 sound/soc/omap/omap-twl4030.c                      |  219 ++++++++++++++++++++
 5 files changed, 286 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-twl4030.txt
 create mode 100644 include/linux/platform_data/omap-twl4030.h
 create mode 100644 sound/soc/omap/omap-twl4030.c

diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
new file mode 100644
index 0000000..02e4e4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
@@ -0,0 +1,19 @@
+* Texas Instruments SoC with twl4030 based audio setups
+
+Required properties:
+- compatible: "ti,omap-twl4030"
+- ti,model: Name of the sound card (for example "omap3beagle")
+- ti,codec_sysclk: Sysclk frequency of twl4030 codec
+- ti,mcbsp: phandle for the McBSP node
+- ti,codec: phandle for the twl4030 audio node
+
+Example:
+
+sound {
+	compatible = "ti,omap-twl4030";
+	ti,model = "omap3beagle";
+
+	ti,mcbsp = <&mcbsp2>;
+	ti,codec = <&twl_audio>;
+	ti,codec_sysclk = <26000000>;
+};
diff --git a/include/linux/platform_data/omap-twl4030.h b/include/linux/platform_data/omap-twl4030.h
new file mode 100644
index 0000000..ee68473
--- /dev/null
+++ b/include/linux/platform_data/omap-twl4030.h
@@ -0,0 +1,33 @@
+/**
+ * omap-twl4030.h - ASoC machine driver for TI SoC based boards with twl4030
+ *		    codec, header.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Author: Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef _OMAP_TWL4030_H_
+#define _OMAP_TWL4030_H_
+
+struct omap_tw4030_pdata {
+	const char *card_name;
+	int codec_sysclk;
+};
+
+#endif /* _OMAP_TWL4030_H_ */
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 57a2fa7..fc83d74 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -95,6 +95,19 @@ config SND_OMAP_SOC_SDP3430
 	  Say Y if you want to add support for SoC audio on Texas Instruments
 	  SDP3430.
 
+config SND_OMAP_SOC_OMAP_TWL4030
+	tristate "SoC Audio support for TI SoC based boards with twl4030 codec"
+	depends on TWL4030_CORE && SND_OMAP_SOC
+	select SND_OMAP_SOC_MCBSP
+	select SND_SOC_TWL4030
+	help
+	  Say Y if you want to add support for SoC audio on TI SoC based boards
+	  using twl4030 as c codec. This driver currently supports:
+	  - Beagleboard or Devkit8000
+	  - Gumstix Overo or CompuLab CM-T35/CM-T3730
+	  - IGEP v2
+	  - OMAP3EVM
+
 config SND_OMAP_SOC_OMAP_ABE_TWL6040
 	tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec"
 	depends on TWL6040_CORE && SND_OMAP_SOC && ARCH_OMAP4
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 0e14dd3..861e640 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -21,6 +21,7 @@ snd-soc-omap3evm-objs := omap3evm.o
 snd-soc-am3517evm-objs := am3517evm.o
 snd-soc-sdp3430-objs := sdp3430.o
 snd-soc-omap-abe-twl6040-objs := omap-abe-twl6040.o
+snd-soc-omap-twl4030-objs := omap-twl4030.o
 snd-soc-omap3pandora-objs := omap3pandora.o
 snd-soc-omap3beagle-objs := omap3beagle.o
 snd-soc-zoom2-objs := zoom2.o
@@ -37,6 +38,7 @@ obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
 obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o
 obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040) += snd-soc-omap-abe-twl6040.o
+obj-$(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) += snd-soc-omap-twl4030.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
 obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o
diff --git a/sound/soc/omap/omap-twl4030.c b/sound/soc/omap/omap-twl4030.c
new file mode 100644
index 0000000..22ec08d
--- /dev/null
+++ b/sound/soc/omap/omap-twl4030.c
@@ -0,0 +1,219 @@
+/*
+ * omap-twl4030.c  --  SoC audio for TI SoC based boards with twl4030 codec
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Author: Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This driver replaces the following machine drivers:
+ * omap3beagle (Author: Steve Sakoman <steve at sakoman.com>)
+ * omap3evm (Author: Anuj Aggarwal <anuj.aggarwal at ti.com>)
+ * overo (Author: Steve Sakoman <steve at sakoman.com>)
+ * igep0020 (Author: Enric Balletbo i Serra <eballetbo at iseebcn.com>)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/platform_data/omap-twl4030.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+struct omap_twl4030_priv {
+	int	codec_sysclk;
+};
+
+static int omap_twl4030_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_card *card = codec->card;
+	struct omap_twl4030_priv *priv = snd_soc_card_get_drvdata(card);
+	unsigned int fmt;
+	int ret;
+
+	switch (params_channels(params)) {
+	case 2: /* Stereo I2S mode */
+		fmt =	SND_SOC_DAIFMT_I2S |
+			SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBM_CFM;
+		break;
+	case 4: /* Four channel TDM mode */
+		fmt =	SND_SOC_DAIFMT_DSP_A |
+			SND_SOC_DAIFMT_IB_NF |
+			SND_SOC_DAIFMT_CBM_CFM;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set codec DAI configuration */
+	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
+	if (ret < 0) {
+		dev_err(card->dev, "can't set codec DAI configuration\n");
+		return ret;
+	}
+
+	/* Set cpu DAI configuration */
+	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
+	if (ret < 0) {
+		dev_err(card->dev, "can't set cpu DAI configuration\n");
+		return ret;
+	}
+
+	/* Set the codec system clock for DAC and ADC */
+	ret = snd_soc_dai_set_sysclk(codec_dai, 0, priv->codec_sysclk,
+				     SND_SOC_CLOCK_IN);
+	if (ret < 0) {
+		dev_err(card->dev, "can't set codec system clock\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops omap_twl4030_ops = {
+	.hw_params = omap_twl4030_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link omap_twl4030_dai_links[] = {
+	{
+		.name = "TWL4030",
+		.stream_name = "TWL4030",
+		.cpu_dai_name = "omap-mcbsp.2",
+		.codec_dai_name = "twl4030-hifi",
+		.platform_name = "omap-pcm-audio",
+		.codec_name = "twl4030-codec",
+		.ops = &omap_twl4030_ops,
+	},
+};
+
+/* Audio machine driver */
+static struct snd_soc_card omap_twl4030_card = {
+	.owner = THIS_MODULE,
+	.dai_link = omap_twl4030_dai_links,
+	.num_links = ARRAY_SIZE(omap_twl4030_dai_links),
+};
+
+static __devinit int omap_twl4030_probe(struct platform_device *pdev)
+{
+	struct omap_tw4030_pdata *pdata = dev_get_platdata(&pdev->dev);
+	struct device_node *node = pdev->dev.of_node;
+	struct snd_soc_card *card = &omap_twl4030_card;
+	struct omap_twl4030_priv *priv;
+	int ret = 0;
+
+	card->dev = &pdev->dev;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct omap_twl4030_priv),
+			    GFP_KERNEL);
+	if (priv == NULL)
+		return -ENOMEM;
+
+	if (node) {
+		struct device_node *dai_node;
+
+		if (snd_soc_of_parse_card_name(card, "ti,model")) {
+			dev_err(&pdev->dev, "Card name is not provided\n");
+			return -ENODEV;
+		}
+
+		dai_node = of_parse_phandle(node, "ti,mcbsp", 0);
+		if (!dai_node) {
+			dev_err(&pdev->dev, "McBSP node is not provided\n");
+			return -EINVAL;
+		}
+		omap_twl4030_dai_links[0].cpu_dai_name  = NULL;
+		omap_twl4030_dai_links[0].cpu_of_node = dai_node;
+
+		of_property_read_u32(node, "ti,codec_sysclk",
+				     &priv->codec_sysclk);
+	} else if (pdata) {
+		if (pdata->card_name) {
+			card->name = pdata->card_name;
+		} else {
+			dev_err(&pdev->dev, "Card name is not provided\n");
+			return -ENODEV;
+		}
+
+		priv->codec_sysclk = pdata->codec_sysclk;
+	} else {
+		dev_err(&pdev->dev, "Missing pdata\n");
+		return -ENODEV;
+	}
+
+
+	if (!priv->codec_sysclk) {
+		dev_err(&pdev->dev, "Codec sysclk frequency missing\n");
+		return -ENODEV;
+	}
+
+	snd_soc_card_set_drvdata(card, priv);
+
+	ret = snd_soc_register_card(card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
+			ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit omap_twl4030_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(card);
+
+	return 0;
+}
+
+static const struct of_device_id omap_twl4030_of_match[] = {
+	{.compatible = "ti,omap-twl4030", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, omap_twl4030_of_match);
+
+static struct platform_driver omap_twl4030_driver = {
+	.driver = {
+		.name = "omap-twl4030",
+		.owner = THIS_MODULE,
+		.pm = &snd_soc_pm_ops,
+		.of_match_table = omap_twl4030_of_match,
+	},
+	.probe = omap_twl4030_probe,
+	.remove = __devexit_p(omap_twl4030_remove),
+};
+
+module_platform_driver(omap_twl4030_driver);
+
+MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi at ti.com>");
+MODULE_DESCRIPTION("ALSA SoC for TI SoC based boards with twl4030 codec");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:omap-twl4030");
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:54:08 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:54:08 +0300
Subject: [PATCH 2/4] ARM: OMAP: twl-common: Add helper function to register
 the omap-twl4030 audio driver
In-Reply-To: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344419650-5389-3-git-send-email-peter.ujfalusi@ti.com>

Since several OMAP3 based boards will be using the unified simple audio
driver it is better to not have duplicated code in the board files for this
purpose.
Board files can call omap_twl4030_audio_init(); to set up the needed device
for the audio support.

For example:
omap_twl4030_audio_init("omap3beagle", 26000000);

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/twl-common.c |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/twl-common.h |    2 ++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index d52be85..639ea02 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -522,3 +522,31 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 		pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
+
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \
+	defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
+#include <linux/platform_data/omap-twl4030.h>
+
+static struct omap_tw4030_pdata omap_twl4030_audio_data;
+
+static struct platform_device audio_device = {
+	.name		= "omap-twl4030",
+	.id		= -1,
+	.dev = {
+		.platform_data = &omap_twl4030_audio_data,
+	},
+};
+
+void __init omap_twl4030_audio_init(char *card_name, int codec_sysclk)
+{
+	omap_twl4030_audio_data.card_name = card_name;
+	omap_twl4030_audio_data.codec_sysclk = codec_sysclk;
+	platform_device_register(&audio_device);
+}
+
+#else /* SOC_OMAP_TWL4030 */
+void __init omap_twl4030_audio_init(char *card_name, int codec_sysclk)
+{
+	return;
+}
+#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index de062c7..b774c19 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -60,4 +60,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 			   u32 pdata_flags, u32 regulators_flags);
 
+void omap_twl4030_audio_init(char *card_name, int codec_sysclk);
+
 #endif /* __OMAP_PMIC_COMMON__ */
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:54:09 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:54:09 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>

These boards have similar audio setup and they can all use the same driver
for audio support if it is enabled in the kernel config.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/board-cm-t35.c      |    1 +
 arch/arm/mach-omap2/board-devkit8000.c  |    1 +
 arch/arm/mach-omap2/board-igep0020.c    |    1 +
 arch/arm/mach-omap2/board-omap3beagle.c |    1 +
 arch/arm/mach-omap2/board-omap3evm.c    |    1 +
 arch/arm/mach-omap2/board-overo.c       |    1 +
 6 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 97d7190..b73fa5c 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -731,6 +731,7 @@ static void __init cm_t3x_common_init(void)
 	cm_t35_init_ethernet();
 	cm_t35_init_led();
 	cm_t35_init_display();
+	omap_twl4030_audio_init("overo", 26000000);
 
 	usb_musb_init(NULL);
 	cm_t35_init_usbh();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1c..f834b3e 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -630,6 +630,7 @@ static void __init devkit8000_init(void)
 	usbhs_init(&usbhs_bdata);
 	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
 			     ARRAY_SIZE(devkit8000_nand_partitions));
+	omap_twl4030_audio_init("omap3beagle", 26000000);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 7491529..bc7c1ea 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -626,6 +626,7 @@ static void __init igep_init(void)
 
 	igep_flash_init();
 	igep_leds_init();
+	omap_twl4030_audio_init("igep2", 26000000);
 
 	/*
 	 * WLAN-BT combo module from MuRata which has a Marvell WLAN
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc7..dd6e4f0 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -519,6 +519,7 @@ static void __init omap3_beagle_init(void)
 	usbhs_init(&usbhs_bdata);
 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
 			     ARRAY_SIZE(omap3beagle_nand_partitions));
+	omap_twl4030_audio_init("omap3beagle", 26000000);
 
 	/* Ensure msecure is mux'd to be able to set the RTC. */
 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0..1be8f6e 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -736,6 +736,7 @@ static void __init omap3_evm_init(void)
 	omap3evm_init_smsc911x();
 	omap3_evm_display_init();
 	omap3_evm_wl12xx_init();
+	omap_twl4030_audio_init("omap3evm", 26000000);
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d..7b7db3d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -509,6 +509,7 @@ static void __init overo_init(void)
 	overo_display_init();
 	overo_init_led();
 	overo_init_keys();
+	omap_twl4030_audio_init("overo", 26000000);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug  8 05:54:10 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed,  8 Aug 2012 12:54:10 +0300
Subject: [PATCH 4/4] ASoC: Remove obsolete OMAP3 machine drivers
In-Reply-To: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344419650-5389-5-git-send-email-peter.ujfalusi@ti.com>

The new omap-twl4030 handles the boards used the following drivers:
igep0020, omap3beagle, omap3evm and overo.
Remove these drivers since they are mostly identical and we already have
drop in replacement for all of them.

Note: Earlier patch added the needed code for the board files to retain the
audio support for boards I can identify that used one of the removed
drivers.
If I missed something please take a look at for example:
arch/arm/mach-omap2/board-omap3beagle.c on how add support for omap-twl4030
audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/Kconfig       |   35 ----------
 sound/soc/omap/Makefile      |    8 --
 sound/soc/omap/igep0020.c    |  120 ---------------------------------
 sound/soc/omap/omap3beagle.c |  150 ------------------------------------------
 sound/soc/omap/omap3evm.c    |  118 ---------------------------------
 sound/soc/omap/overo.c       |  122 ----------------------------------
 6 files changed, 0 insertions(+), 553 deletions(-)
 delete mode 100644 sound/soc/omap/igep0020.c
 delete mode 100644 sound/soc/omap/omap3beagle.c
 delete mode 100644 sound/soc/omap/omap3evm.c
 delete mode 100644 sound/soc/omap/overo.c

diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index fc83d74..2c484a5 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -60,23 +60,6 @@ config SND_OMAP_SOC_OSK5912
 	help
 	  Say Y if you want to add support for SoC audio on osk5912.
 
-config SND_OMAP_SOC_OVERO
-	tristate "SoC Audio support for Gumstix Overo and CompuLab CM-T35"
-	depends on TWL4030_CORE && SND_OMAP_SOC && (MACH_OVERO || MACH_CM_T35)
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the
-	  Gumstix Overo or CompuLab CM-T35
-
-config SND_OMAP_SOC_OMAP3EVM
-	tristate "SoC Audio support for OMAP3EVM board"
-	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP3EVM
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the omap3evm board.
-
 config SND_OMAP_SOC_AM3517EVM
 	tristate "SoC Audio support for OMAP3517 / AM3517 EVM"
 	depends on SND_OMAP_SOC && MACH_OMAP3517EVM && I2C
@@ -140,16 +123,6 @@ config SND_OMAP_SOC_OMAP3_PANDORA
 	help
 	  Say Y if you want to add support for SoC audio on the OMAP3 Pandora.
 
-config SND_OMAP_SOC_OMAP3_BEAGLE
-	tristate "SoC Audio support for OMAP3 Beagle and Devkit8000"
-	depends on TWL4030_CORE && SND_OMAP_SOC
-	depends on (MACH_OMAP3_BEAGLE || MACH_DEVKIT8000)
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the Beagleboard or
-	  the clone Devkit8000.
-
 config SND_OMAP_SOC_ZOOM2
 	tristate "SoC Audio support for Zoom2"
 	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_ZOOM2
@@ -157,11 +130,3 @@ config SND_OMAP_SOC_ZOOM2
 	select SND_SOC_TWL4030
 	help
 	  Say Y if you want to add support for Soc audio on Zoom2 board.
-
-config SND_OMAP_SOC_IGEP0020
-	tristate "SoC Audio support for IGEP v2"
-	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_IGEP0020
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for Soc audio on IGEP v2 board.
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 861e640..19637e5 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -16,31 +16,23 @@ snd-soc-n810-objs := n810.o
 snd-soc-rx51-objs := rx51.o
 snd-soc-ams-delta-objs := ams-delta.o
 snd-soc-osk5912-objs := osk5912.o
-snd-soc-overo-objs := overo.o
-snd-soc-omap3evm-objs := omap3evm.o
 snd-soc-am3517evm-objs := am3517evm.o
 snd-soc-sdp3430-objs := sdp3430.o
 snd-soc-omap-abe-twl6040-objs := omap-abe-twl6040.o
 snd-soc-omap-twl4030-objs := omap-twl4030.o
 snd-soc-omap3pandora-objs := omap3pandora.o
-snd-soc-omap3beagle-objs := omap3beagle.o
 snd-soc-zoom2-objs := zoom2.o
-snd-soc-igep0020-objs := igep0020.o
 snd-soc-omap-hdmi-card-objs := omap-hdmi-card.o
 
 obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
 obj-$(CONFIG_SND_OMAP_SOC_RX51) += snd-soc-rx51.o
 obj-$(CONFIG_SND_OMAP_SOC_AMS_DELTA) += snd-soc-ams-delta.o
 obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
-obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP2EVM) += snd-soc-omap2evm.o
-obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
 obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o
 obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040) += snd-soc-omap-abe-twl6040.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) += snd-soc-omap-twl4030.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
-obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
 obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o
-obj-$(CONFIG_SND_OMAP_SOC_IGEP0020) += snd-soc-igep0020.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_HDMI) += snd-soc-omap-hdmi-card.o
diff --git a/sound/soc/omap/igep0020.c b/sound/soc/omap/igep0020.c
deleted file mode 100644
index e835781..0000000
--- a/sound/soc/omap/igep0020.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * igep0020.c  --  SoC audio for IGEP v2
- *
- * Based on sound/soc/omap/overo.c by Steve Sakoman
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int igep2_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-					    SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops igep2_ops = {
-	.hw_params = igep2_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link igep2_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops = &igep2_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_card_igep2 = {
-	.name = "igep2",
-	.owner = THIS_MODULE,
-	.dai_link = &igep2_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *igep2_snd_device;
-
-static int __init igep2_soc_init(void)
-{
-	int ret;
-
-	if (!machine_is_igep0020())
-		return -ENODEV;
-	printk(KERN_INFO "IGEP v2 SoC init\n");
-
-	igep2_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!igep2_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(igep2_snd_device, &snd_soc_card_igep2);
-
-	ret = platform_device_add(igep2_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(igep2_snd_device);
-
-	return ret;
-}
-module_init(igep2_soc_init);
-
-static void __exit igep2_soc_exit(void)
-{
-	platform_device_unregister(igep2_snd_device);
-}
-module_exit(igep2_soc_exit);
-
-MODULE_AUTHOR("Enric Balletbo i Serra <eballetbo at iseebcn.com>");
-MODULE_DESCRIPTION("ALSA SoC IGEP v2");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
deleted file mode 100644
index 2830dfd..0000000
--- a/sound/soc/omap/omap3beagle.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * omap3beagle.c  --  SoC audio for OMAP3 Beagle
- *
- * Author: Steve Sakoman <steve at sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int omap3beagle_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-	unsigned int fmt;
-	int ret;
-
-	switch (params_channels(params)) {
-	case 2: /* Stereo I2S mode */
-		fmt =	SND_SOC_DAIFMT_I2S |
-			SND_SOC_DAIFMT_NB_NF |
-			SND_SOC_DAIFMT_CBM_CFM;
-		break;
-	case 4: /* Four channel TDM mode */
-		fmt =	SND_SOC_DAIFMT_DSP_A |
-			SND_SOC_DAIFMT_IB_NF |
-			SND_SOC_DAIFMT_CBM_CFM;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* Set codec DAI configuration */
-	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec DAI configuration\n");
-		return ret;
-	}
-
-	/* Set cpu DAI configuration */
-	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set cpu DAI configuration\n");
-		return ret;
-	}
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-				     SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops omap3beagle_ops = {
-	.hw_params = omap3beagle_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link omap3beagle_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.platform_name = "omap-pcm-audio",
-	.codec_dai_name = "twl4030-hifi",
-	.codec_name = "twl4030-codec",
-	.ops = &omap3beagle_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_omap3beagle = {
-	.name = "omap3beagle",
-	.owner = THIS_MODULE,
-	.dai_link = &omap3beagle_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *omap3beagle_snd_device;
-
-static int __init omap3beagle_soc_init(void)
-{
-	int ret;
-
-	if (!(machine_is_omap3_beagle() || machine_is_devkit8000()))
-		return -ENODEV;
-	pr_info("OMAP3 Beagle/Devkit8000 SoC init\n");
-
-	omap3beagle_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!omap3beagle_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(omap3beagle_snd_device, &snd_soc_omap3beagle);
-
-	ret = platform_device_add(omap3beagle_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(omap3beagle_snd_device);
-
-	return ret;
-}
-
-static void __exit omap3beagle_soc_exit(void)
-{
-	platform_device_unregister(omap3beagle_snd_device);
-}
-
-module_init(omap3beagle_soc_init);
-module_exit(omap3beagle_soc_exit);
-
-MODULE_AUTHOR("Steve Sakoman <steve at sakoman.com>");
-MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
deleted file mode 100644
index 3d468c9..0000000
--- a/sound/soc/omap/omap3evm.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * omap3evm.c  -- ALSA SoC support for OMAP3 EVM
- *
- * Author: Anuj Aggarwal <anuj.aggarwal at ti.com>
- *
- * Based on sound/soc/omap/beagle.c by Steve Sakoman
- *
- * Copyright (C) 2008 Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
- * whether express or implied; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int omap3evm_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-				     SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "Can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops omap3evm_ops = {
-	.hw_params = omap3evm_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link omap3evm_dai = {
-	.name 		= "TWL4030",
-	.stream_name 	= "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops 		= &omap3evm_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_omap3evm = {
-	.name = "omap3evm",
-	.owner = THIS_MODULE,
-	.dai_link = &omap3evm_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *omap3evm_snd_device;
-
-static int __init omap3evm_soc_init(void)
-{
-	int ret;
-
-	if (!machine_is_omap3evm())
-		return -ENODEV;
-	pr_info("OMAP3 EVM SoC init\n");
-
-	omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!omap3evm_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(omap3evm_snd_device, &snd_soc_omap3evm);
-	ret = platform_device_add(omap3evm_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(omap3evm_snd_device);
-
-	return ret;
-}
-
-static void __exit omap3evm_soc_exit(void)
-{
-	platform_device_unregister(omap3evm_snd_device);
-}
-
-module_init(omap3evm_soc_init);
-module_exit(omap3evm_soc_exit);
-
-MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal at ti.com>");
-MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
-MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/omap/overo.c b/sound/soc/omap/overo.c
deleted file mode 100644
index 6ac3e0c..0000000
--- a/sound/soc/omap/overo.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * overo.c  --  SoC audio for Gumstix Overo
- *
- * Author: Steve Sakoman <steve at sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int overo_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-					    SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops overo_ops = {
-	.hw_params = overo_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link overo_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops = &overo_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_card_overo = {
-	.name = "overo",
-	.owner = THIS_MODULE,
-	.dai_link = &overo_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *overo_snd_device;
-
-static int __init overo_soc_init(void)
-{
-	int ret;
-
-	if (!(machine_is_overo() || machine_is_cm_t35())) {
-		pr_debug("Incomatible machine!\n");
-		return -ENODEV;
-	}
-	printk(KERN_INFO "overo SoC init\n");
-
-	overo_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!overo_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(overo_snd_device, &snd_soc_card_overo);
-
-	ret = platform_device_add(overo_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(overo_snd_device);
-
-	return ret;
-}
-module_init(overo_soc_init);
-
-static void __exit overo_soc_exit(void)
-{
-	platform_device_unregister(overo_snd_device);
-}
-module_exit(overo_soc_exit);
-
-MODULE_AUTHOR("Steve Sakoman <steve at sakoman.com>");
-MODULE_DESCRIPTION("ALSA SoC overo");
-MODULE_LICENSE("GPL");
-- 
1.7.8.6



From broonie at opensource.wolfsonmicro.com  Wed Aug  8 05:59:29 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 10:59:29 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <201208080828.35451.arnd@arndb.de>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
 <20120808080411.GB4728@gmail.com>
 <201208080828.35451.arnd@arndb.de>
Message-ID: <20120808095928.GI16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 08:28:35AM +0000, Arnd Bergmann wrote:

> In general, it seems easier to use the same domain type for both cases.
> I don't think that MOP500_AB8500_VIR_GPIO_IRQ_BASE is used anywhere
> else besides the .irq_base definition in board-mop500.c, so I would guess
> that you can just remove that identifier and always use the linear
> domain.

Given how easy this is to get working it doesn't seem sensible to avoid
it - there's a clear pattern already for maintaining support for legacy
domains.


From shawn.guo at linaro.org  Wed Aug  8 06:18:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 Aug 2012 18:18:20 +0800
Subject: imx6q restart is broken
Message-ID: <20120808101817.GA14718@S2101-09.ap.freescale.net>

Thanks Dirk for reporting that imx6q restart (reboot command) is broken.

I tracked down the issue a little bit and found imx6q_restart hangs
on the of_iomap/ioremap call.  The following change, moving the call
somewhere else than imx6q_restart, will just fix the problem.

Does that mean ioremap call is not allowed in platform restart hook?
I'm not sure about that, because I found it works just fine if I build
imx_v6_v7_defconfig with V6 (imx3) platforms excluded (IOW, build a V7
only kernel - imx5 and imx6), which is the case how I tested imx6q
restart feature when I was adding it.

To summarize, the imx6q_restart hangs at ioremap call on a V6 + V7
kernel, while it works fine on a V7 only image.  I need some help to
understand that.

Regards,
Shawn

--8<---

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..01e7489 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -37,14 +37,10 @@
 #include <mach/cpuidle.h>
 #include <mach/hardware.h>

+static void __iomem *wdog_base;

 void imx6q_restart(char mode, const char *cmd)
 {
-       struct device_node *np;
-       void __iomem *wdog_base;
-
-       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
-       wdog_base = of_iomap(np, 0);
        if (!wdog_base)
                goto soft;

@@ -159,6 +155,11 @@ static void __init imx6q_usb_init(void)

 static void __init imx6q_init_machine(void)
 {
+       struct device_node *np;
+
+       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
+       wdog_base = of_iomap(np, 0);
+
        /*
         * This should be removed when all imx6q boards have pinctrl
         * states for devices defined in device tree.




From vaibhav.bedia at ti.com  Wed Aug  8 06:35:17 2012
From: vaibhav.bedia at ti.com (Vaibhav Bedia)
Date: Wed, 8 Aug 2012 16:05:17 +0530
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no match
 exists for a hwmod class
Message-ID: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>

If no match is found for a hwmod class, omap_hwmod_for_each_by_class()
currently does not spit out any error messages. To make debugging
issues related to non-existent hwmod classes simpler make this function
print an error message in case no match is found for the supplied hwmod
class.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..90e2306 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3480,7 +3480,8 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
  * If the callback function returns something other than
  * zero, the iterator is terminated, and the callback function's return
  * value is passed back to the caller.  Returns 0 upon success, -EINVAL
- * if @classname or @fn are NULL, or passes back the error code from @fn.
+ * if @classname or @fn are NULL or no match is found for @classname,
+ * or passes back the error code from @fn.
  */
 int omap_hwmod_for_each_by_class(const char *classname,
 				 int (*fn)(struct omap_hwmod *oh,
@@ -3489,6 +3490,7 @@ int omap_hwmod_for_each_by_class(const char *classname,
 {
 	struct omap_hwmod *temp_oh;
 	int ret = 0;
+	bool found = false;
 
 	if (!classname || !fn)
 		return -EINVAL;
@@ -3498,6 +3500,7 @@ int omap_hwmod_for_each_by_class(const char *classname,
 
 	list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
 		if (!strcmp(temp_oh->class->name, classname)) {
+			found = true;
 			pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
 				 __func__, temp_oh->name);
 			ret = (*fn)(temp_oh, user);
@@ -3506,6 +3509,12 @@ int omap_hwmod_for_each_by_class(const char *classname,
 		}
 	}
 
+	if (!found) {
+		pr_err("omap_hwmod: %s: no match for class %s\n",
+			__func__, classname);
+		return -EINVAL;
+	}
+
 	if (ret)
 		pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
 			 __func__, ret);
-- 
1.7.0.4



From kgene.kim at samsung.com  Wed Aug  8 06:39:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 19:39:22 +0900
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <037601cd6fc9$f6e5fe30$e4b1fa90$%kim@samsung.com>
 <CAMbhsRRp429Fkk2-vEixt8OPW699ftVCaG+C83NWLvM2_jkOVw@mail.gmail.com>
Message-ID: <0af101cd7552$128bc3d0$37a34b70$%kim@samsung.com>

Colin Cross wrote:
> 
> On Wed, Aug 1, 2012 at 2:42 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Stephen Boyd wrote:
> >>
> >> On 07/10/12 23:34, Kukjin Kim wrote:
> >> > Stephen Boyd wrote:
> >> >> Great. Kukjin Kim, can exynos use SGI0? It looks like exynos is the
> >> only
> >> >> one left to move to SGI0.
> >> >>
> >> > Yeah, EXYNOS can use SGI0 instead of SGI1 :)
> >> >
> >> >
> >>
> >> Russell, can we apply something like this?
> >>
> > Please feel free to add my ack on following change.
> >
> > Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> >
> 
> When testing coupled cpuidle on Exynos5, I found that sending an IPI
> does not successfully wake up CPU1.  CPU1 is in a wfe with interrupts
> masked, not a wfi, so an interrupt is not able to wake it up.  It
> tends to wake up anyways because the next time a spin lock is
> unlocked, often during a timer interrupt on CPU0, CPU0 executes an sev
> which wakes up CPU1.  You can see that the IPI is unnecessary by
> removing the gic_raise_softirq and replacing it with dsb_sev().

Hmm...could be. Let me check you commented in detail. And if any updates,
I'll let you know.

Thanks for your information.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Wed Aug  8 06:47:26 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 19:47:26 +0900
Subject: [PATCH 2/9] ARM: plat-s3c24xx: Don't use FIQ_START
In-Reply-To: <1344207819-3415-2-git-send-email-anton.vorontsov@linaro.org>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-2-git-send-email-anton.vorontsov@linaro.org>
Message-ID: <0af201cd7553$3346dd70$99d49850$%kim@samsung.com>

Anton Vorontsov wrote:
> 
> We're about to remove FIQ_START mess, so move the platform-specific
> detail inside platform-specific s3c24xx_set_fiq().
> 
> Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

BTW, how was going on the 'change FIQ_START to a variable' patch from Shawn
Guo?
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-June/106486.html

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> ---
>  arch/arm/plat-s3c24xx/irq.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
> index fe57bbb..e4e9567 100644
> --- a/arch/arm/plat-s3c24xx/irq.c
> +++ b/arch/arm/plat-s3c24xx/irq.c
> @@ -503,7 +503,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
>  	unsigned offs;
> 
>  	if (on) {
> -		offs = irq - FIQ_START;
> +		offs = irq - IRQ_EINT0;
>  		if (offs > 31)
>  			return -EINVAL;
> 
> --
> 1.7.10.4



From rnayak at ti.com  Wed Aug  8 06:54:12 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 8 Aug 2012 16:24:12 +0530
Subject: [PATCH 0/2] OMAP cpufreq fixes
Message-ID: <1344423254-3475-1-git-send-email-rnayak@ti.com>

Hi Kevin,

While testing cpufreq on 3.6-rc1, I noticed strange issues on OMAP4,
like a lockup when booting with 'performace' governer as default,
and crashes when using 'usespace' (which booted up) and switching
to higher OPPs.
It took me a while to realise I was using a 4460 device. The OPPs
registered though seemed to be for 4430 and hence were causing
issues on the 4460 device. 

This series basically avoids registering the 4430 OPPs on other
varients like 4460 and 4470 (and hence causing random issues)
and also fixes a subsequent bug uncovered by doing this in
OMAP cpufreq driver.

regards,
Rajendra 

Rajendra Nayak (2):
  cpufreq: OMAP: Handle missing frequency table on SMP systems
  ARM: OMAP4: Register the OPP table only for 4430 device

 arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
 drivers/cpufreq/omap-cpufreq.c     |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
1.7.9.5



From rnayak at ti.com  Wed Aug  8 06:54:13 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 8 Aug 2012 16:24:13 +0530
Subject: [PATCH 1/2] cpufreq: OMAP: Handle missing frequency table on SMP
 systems
In-Reply-To: <1344423254-3475-1-git-send-email-rnayak@ti.com>
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
Message-ID: <1344423254-3475-2-git-send-email-rnayak@ti.com>

On OMAP4, if the first CPU fails to get a valid frequency table (this
could happen if the platform does not register any OPP table), the
subsequent CPU instances end up dealing with a NULL freq_table and
crash. Add a check for a NULL freq_table to help error the rest
of the CPU instances out.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: <linux-pm at vger.kernel.org>
---
 drivers/cpufreq/omap-cpufreq.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 17fa04d..0ee824c 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -221,7 +221,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 	if (atomic_inc_return(&freq_table_users) == 1)
 		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
 
-	if (result) {
+	if (result || !freq_table) {
 		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
 				__func__, policy->cpu, result);
 		goto fail_ck;
-- 
1.7.9.5



From rnayak at ti.com  Wed Aug  8 06:54:14 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 8 Aug 2012 16:24:14 +0530
Subject: [PATCH 2/2] ARM: OMAP4: Register the OPP table only for 4430 device
In-Reply-To: <1344423254-3475-1-git-send-email-rnayak@ti.com>
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
Message-ID: <1344423254-3475-3-git-send-email-rnayak@ti.com>

The 4430 OPP table was being registered for all other OMAP4 variants
too, like 4460 and 4470 causing issues with cpufreq driver
enabled. 4460 and 4470 devices have different OPPs as compared to
4430, and they should be populated seperately. As long as that
happens, let the OPP table registeration happen only on 4430 device.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba2..c95415d 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
 {
 	int r = -ENODEV;
 
-	if (!cpu_is_omap44xx())
+	if (!cpu_is_omap443x())
 		return r;
 
 	r = omap_init_opp_table(omap44xx_opp_def_list,
-- 
1.7.9.5



From dave.martin at linaro.org  Wed Aug  8 06:54:36 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed, 8 Aug 2012 11:54:36 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
Message-ID: <20120808105436.GA2134@linaro.org>

On Mon, Aug 06, 2012 at 12:32:14AM -0400, Nicolas Pitre wrote:
> On Sun, 5 Aug 2012, Uwe Kleine-K?nig wrote:
> 
> > On Fri, Aug 03, 2012 at 12:45:32PM +0100, Will Deacon wrote:
> > > On Fri, Aug 03, 2012 at 10:04:52AM +0100, Uwe Kleine-K?nig wrote:
> > > > Hello,
> > > 
> > > Hi Uwe,
> > > 
> > > > in both arch/arm/kernel/head.S and arch/arm/kernel/head-nommu.S we have
> > > > 
> > > > 	.arm
> > > >  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> > > >  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
> > > >  THUMB( .thumb                  )       @ switch to Thumb now.
> > > >  THUMB(1:                       )
> > > > 
> > > > as first instructions at the entry point. This is a problem for
> > > > thumb2-only cpus (e.g. Cortex-M3).
> > > 
> > > Yup, Documentation/arm/Booting mentions this too.
> > > 
> > > > Up to now I commented out the first three lines for the Cortex-M3 port.
> > > > What should we do about that. There are two possibilities I see:
> > > > 
> > > >  a) introduce a kconfig symbol for thumb2-only builds and #ifdef the
> > > >     first three lines out if it is given.
> > > >  b) expect the bootloader to directly jump to the label 1.
> > > > 
> > > > The downside of a) is that a boot loader on a cpu that is capable to
> > > > execute the tradtional instructions would need to detect if the switch
> > > > to thumb is there or not and react accordingly. (In fact it needs to
> > > > distringuish three cases:
> > > > 
> > > >  - traditional kernel
> > > >  - thumb2 kernel with ARM entry
> > > >  - thumb2 kernel without ARM entry
> > > > 
> > > > .) So I think b) is the more sensible option in the long run.
> > > > 
> > > > What do you think?
> > > 
> > > How about something like:
> > > 
> > > 
> > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > > index 835898e..9f07be2 100644
> > > --- a/arch/arm/kernel/head.S
> > > +++ b/arch/arm/kernel/head.S
> > > @@ -86,6 +86,7 @@
> > >         __HEAD
> > >  ENTRY(stext)
> > >  
> > > + THUMB(        .inst   0xe200e004      )       @ ARM: and lr, r0, #4 T2: b 1f
> > >   THUMB(        adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
> > >   THUMB(        bx      r9              )       @ If this is a Thumb-2 kernel,
> > >   THUMB(        .thumb                  )       @ switch to Thumb now.
> > Great idea, but it doesn't work as suggested. My compiler already barfs
> > on the .arm above:
> 
> Let's stop splitting hairs.
> 
> A Cortex-M kernel simply won't run on anything else.  It certainly won't 
> run on ARM mode capable processors.  So in this case just make the 
> kernel entry point Thumb mode only by #ifdef'ing out the .arm part.

This was exactly my view when originally adding that code.

Previously, there was no well-defined way for a bootloader to know
whether the target kernel was ARM or Thumb and this had to be separately
configured.  This just caused a compatibility mess.

To fix this, we now have a fixed boot protocol: on a CPU supporting ARM
state, you must enter the kernel in ARM state, period.  This means there
is nothing for the bootloader to get wrong.  If a single bootloader
image is required across CPUs with and without ARM state, the bootloader
must detect the CPU and enter the kernel in the appropriate way.

The unconditionalness of the veneer sequence was an omission caused by
the fact that there was no real upstream support for ARM-less v7 CPUs
at the time.

For ARM-less CPUs, I would go for the #ifdef approach.


The only potential problem comes from the fact that the boot protocol
groups CPUs into two mutually exclusive sets: those with ARM state and
those without.  I single image cannot therefore run on both:

 a) building a single image that is bootable on ARM-less (M class)
    and AR class.  Those architecture families are just too different
    for this to seem realistic.

 b) building a single image that is bootable on current -AR CPUs
    (with ARM state) and hypothetical future -AR CPUs without ARM
    state.

Both of these seem pretty speculative.

Unless we have a need for these right now I would much rather that a
bootloader which does not follow arm/Booting fails instead of silently
working.

Cheers
---Dave


From notasas at gmail.com  Wed Aug  8 06:56:33 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Wed, 8 Aug 2012 13:56:33 +0300
Subject: [PATCH v2] Revert "ARM: OMAP3: PM: call pre/post transition per
 powerdomain"
In-Reply-To: <1344379659-26152-1-git-send-email-khilman@ti.com>
References: <1344379659-26152-1-git-send-email-khilman@ti.com>
Message-ID: <CANOLnONQhqYcqW8ZAfn+5ceZQ_h2W_yKZVZrnrP5cUJDooTrQg@mail.gmail.com>

On Wed, Aug 8, 2012 at 1:47 AM, Kevin Hilman <khilman at ti.com> wrote:
> This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.
>
> Converstion to per-pwrdm per/post transition calls was a bit
> premature.  Only tracking MPU, PER & CORE in the idle path means we
> lose the accounting for all the other powerdomains which may also
> transition in idle.  On OMAP3, due to autodeps, several powerdomains
> transition along with MPU (e.g. DSS, USBHOST), and the accounting for
> these was lost with this patch.  Since the accounting includes the
> context loss counters, drivers for devices in those power domains
> would never notice context lost, so would likely hang after any
> off-mode transitions.

That's a shame, pwrdm_pre_transition/pwrdm_post_transition are the
main contributors to idle latency and cause large performance loss on
small and frequent loads, like short DMAs. Could we perhaps only do it
when PM_DEBUG is on or when off transitions happen instead?

> This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
> use-counting seires is merged since then we can properly do accounting
> without relying on a call in the idle path.

So all hope of getting rid of those pre/post transition calls goes here then?
Small typo with 'seires'..

> In addition, the original patch had another bug because the PER
> powerdomain accounting was not updated until after the GPIO resume
> hook is called.  Since gpio_resume_after_idle() checks the context
> loss count (which is not yet updated) it would not properly restore
> context, leaving the GPIO banks in an undefined state.
>
> Cc: Jean Pihet <jean.pihet at newoldbits.com>
> Cc: Tero Kristo <t-kristo at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Reported-by: Paul Walmsley <paul at pwsan.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
>  arch/arm/mach-omap2/pm34xx.c |   19 ++++---------------
>  1 file changed, 4 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index e4fc88c..05bd8f0 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -272,21 +272,16 @@ void omap_sram_idle(void)
>         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
>         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
>
> -       if (mpu_next_state < PWRDM_POWER_ON) {
> -               pwrdm_pre_transition(mpu_pwrdm);
> -               pwrdm_pre_transition(neon_pwrdm);
> -       }
> +       pwrdm_pre_transition(NULL);
>
>         /* PER */
>         if (per_next_state < PWRDM_POWER_ON) {
> -               pwrdm_pre_transition(per_pwrdm);
>                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
>                 omap2_gpio_prepare_for_idle(per_going_off);
>         }
>
>         /* CORE */
>         if (core_next_state < PWRDM_POWER_ON) {
> -               pwrdm_pre_transition(core_pwrdm);
>                 if (core_next_state == PWRDM_POWER_OFF) {
>                         omap3_core_save_context();
>                         omap3_cm_save_context();
> @@ -339,20 +334,14 @@ void omap_sram_idle(void)
>                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
>                                                OMAP3430_GR_MOD,
>                                                OMAP3_PRM_VOLTCTRL_OFFSET);
> -               pwrdm_post_transition(core_pwrdm);
>         }
>         omap3_intc_resume_idle();
>
> +       pwrdm_post_transition(NULL);
> +
>         /* PER */
> -       if (per_next_state < PWRDM_POWER_ON) {
> +       if (per_next_state < PWRDM_POWER_ON)
>                 omap2_gpio_resume_after_idle();
> -               pwrdm_post_transition(per_pwrdm);
> -       }
> -
> -       if (mpu_next_state < PWRDM_POWER_ON) {
> -               pwrdm_post_transition(mpu_pwrdm);
> -               pwrdm_post_transition(neon_pwrdm);
> -       }
>  }
>
>  static void omap3_pm_idle(void)
> --
> 1.7.9.2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Gra?vydas


From dirk.behme at de.bosch.com  Wed Aug  8 06:53:59 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Wed, 8 Aug 2012 12:53:59 +0200
Subject: imx6q restart is broken
In-Reply-To: <20120808101817.GA14718@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
Message-ID: <50224547.9020000@de.bosch.com>

On 08.08.2012 12:18, Shawn Guo wrote:
> Thanks Dirk for reporting that imx6q restart (reboot command) is broken.
> 
> I tracked down the issue a little bit and found imx6q_restart hangs
> on the of_iomap/ioremap call.  The following change, moving the call
> somewhere else than imx6q_restart, will just fix the problem.
> 
> Does that mean ioremap call is not allowed in platform restart hook?
> I'm not sure about that, because I found it works just fine if I build
> imx_v6_v7_defconfig with V6 (imx3) platforms excluded (IOW, build a V7
> only kernel - imx5 and imx6), which is the case how I tested imx6q
> restart feature when I was adding it.
> 
> To summarize, the imx6q_restart hangs at ioremap call on a V6 + V7
> kernel, while it works fine on a V7 only image.  I need some help to
> understand that.

Some additional information from my debugging:

a) Having a JTAG debugger attached to the i.MX6 SabreLite board I use 
(kernel built with imx_v6_v7_defconfig) the reboot does work. No hang. 
This does mean I can't debug the reboot hang with a JTAG debugger. 
Therefore I added some printk debugging:

b) Adding some printk statements [1] in the of_iomap/ioremap call, it 
looks to me that the system hangs in

of_iomap() -> ... -> set_pte_at() -> set_pte_ext() / 
cpu_v7_set_pte_ext() <= hang

On our system, set_pte_ext() is translated to cpu_v7_set_pte_ext() in 
proc-v7-2level.S.

As cpu_v7_set_pte_ext() is assembly, I can't add additional printk's, 
and JTAG doesn't work, so I don't have more details at the moment.

 From this it looks like that cpu_v7_set_pte_ext() hangs if called from 
within machine_restart() after machine_shutdown() was called (?).

Best regards

Dirk

[1] To be able to add some printk's to set_pte_at() which is a inline 
function in pgtable.h, I copied this to ioremap.c:

--- a/lib/ioremap.c
+++ b/lib/ioremap.c
@@ -13,6 +13,19 @@
  #include <asm/cacheflush.h>
  #include <asm/pgtable.h>

+void set_pte_debug(struct mm_struct *mm, unsigned long addr,
+                             pte_t *ptep, pte_t pteval)
+{
+       if (addr >= TASK_SIZE) {
+               printk("=> set_pte_debug #1\n");
+               set_pte_ext(ptep, pteval, 0);
+               printk("=> set_pte_debug #2\n");
+       } else {
+               __sync_icache_dcache(pteval);
+               set_pte_ext(ptep, pteval, PTE_EXT_NG);
+       }
+}
+
  static int ioremap_pte_range(pmd_t *pmd, unsigned long addr,
                 unsigned long end, phys_addr_t phys_addr, pgprot_t prot)
  {
@@ -25,7 +38,7 @@ static int ioremap_pte_range(pmd_t *pmd, unsigned long 
addr,
                 return -ENOMEM;
         do {
                 BUG_ON(!pte_none(*pte));
-               set_pte_at(&init_mm, addr, pte, pfn_pte(pfn, prot));
+               set_pte_debug(&init_mm, addr, pte, pfn_pte(pfn, prot));
                 pfn++;
         } while (pte++, addr += PAGE_SIZE, addr != end);
         return 0;

With this I get:

# reboot -f
Restarting system.
=> set_pte_debug #1

-- no further output, hang, 'set_pte_debug #2' missing

> --8<---
> 
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 5ec0608..01e7489 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -37,14 +37,10 @@
>  #include <mach/cpuidle.h>
>  #include <mach/hardware.h>
> 
> +static void __iomem *wdog_base;
> 
>  void imx6q_restart(char mode, const char *cmd)
>  {
> -       struct device_node *np;
> -       void __iomem *wdog_base;
> -
> -       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
> -       wdog_base = of_iomap(np, 0);
>         if (!wdog_base)
>                 goto soft;
> 
> @@ -159,6 +155,11 @@ static void __init imx6q_usb_init(void)
> 
>  static void __init imx6q_init_machine(void)
>  {
> +       struct device_node *np;
> +
> +       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
> +       wdog_base = of_iomap(np, 0);
> +
>         /*
>          * This should be removed when all imx6q boards have pinctrl
>          * states for devices defined in device tree.


From anton.vorontsov at linaro.org  Wed Aug  8 07:00:59 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Wed, 8 Aug 2012 04:00:59 -0700
Subject: [PATCH 2/9] ARM: plat-s3c24xx: Don't use FIQ_START
In-Reply-To: <0af201cd7553$3346dd70$99d49850$%kim@samsung.com>
References: <20120805230238.GA1663@lizard>
 <1344207819-3415-2-git-send-email-anton.vorontsov@linaro.org>
 <0af201cd7553$3346dd70$99d49850$%kim@samsung.com>
Message-ID: <20120808110058.GA22197@lizard>

On Wed, Aug 08, 2012 at 07:47:26PM +0900, Kukjin Kim wrote:
> Anton Vorontsov wrote:
> > We're about to remove FIQ_START mess, so move the platform-specific
> > detail inside platform-specific s3c24xx_set_fiq().
> > 
> > Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
> 
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks!

> BTW, how was going on the 'change FIQ_START to a variable' patch from Shawn
> Guo?
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-June/106486.html

It's in Linus' tree already. My patch set is just a next step in
the same direction.

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From notasas at gmail.com  Wed Aug  8 07:07:55 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Wed, 8 Aug 2012 14:07:55 +0300
Subject: [PATCH 1/2] ARM: pgtable: add pgprot_writethrough() macro
In-Reply-To: <1337716444-30139-2-git-send-email-siarhei.siamashka@gmail.com>
References: <1337716444-30139-1-git-send-email-siarhei.siamashka@gmail.com>
 <1337716444-30139-2-git-send-email-siarhei.siamashka@gmail.com>
Message-ID: <CANOLnOMTFLMNidjyML5XFF3Wz4oXWCnRH1WCqvFD7FqOgO20Sg@mail.gmail.com>

On Tue, May 22, 2012 at 10:54 PM, Siarhei Siamashka
<siarhei.siamashka at gmail.com> wrote:
> Needed for remapping pages with write-through cacheable
> attribute. May be useful for framebuffers.

With this series applied, some of my framebuffer programs get over 70%
performance improvement, could we get this patch in? OMAP DSS
maintainer agreed to take the second patch if this can be merged.

> Signed-off-by: Siarhei Siamashka <siarhei.siamashka at gmail.com>
> ---
>  arch/arm/include/asm/pgtable.h |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
> index f66626d..04297fa 100644
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -103,6 +103,9 @@ extern pgprot_t             pgprot_kernel;
>  #define pgprot_stronglyordered(prot) \
>         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
>
> +#define pgprot_writethrough(prot) \
> +       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_WRITETHROUGH)
> +
>  #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
>  #define pgprot_dmacoherent(prot) \
>         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
> --
> 1.7.3.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Gra?vydas


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 07:21:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 12:21:32 +0100
Subject: [PATCH 00/11] ARM/ASoC: OMAP McBSP device tree support
In-Reply-To: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120808112132.GN16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 12:11:30PM +0300, Peter Ujfalusi wrote:

> The series changes McBSP related files mostly. It would be great if the whole
> series could go via audio tree (if the patches are OK and it is fine by Tony).

I'm OK with all the patches, if Tony's happy with me applying them then
I'll put them in a separate branch so they can easily be merged into the
OMAP trees (or similarly if it's applied in an OMAP tree having a branch
I can merge if needed would be good).


From santosh.shilimkar at ti.com  Wed Aug  8 07:30:10 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 8 Aug 2012 17:00:10 +0530
Subject: [PATCH 1/2] cpufreq: OMAP: Handle missing frequency table on SMP
 systems
In-Reply-To: <1344423254-3475-2-git-send-email-rnayak@ti.com>
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-2-git-send-email-rnayak@ti.com>
Message-ID: <CAMQu2gyooQ4x=ZGDZFg5BuBaEkgQx2kTAvtiGLEjXwOYvF_wMQ@mail.gmail.com>

On Wed, Aug 8, 2012 at 4:24 PM, Rajendra Nayak <rnayak at ti.com> wrote:
>
> On OMAP4, if the first CPU fails to get a valid frequency table (this
> could happen if the platform does not register any OPP table), the
> subsequent CPU instances end up dealing with a NULL freq_table and
> crash. Add a check for a NULL freq_table to help error the rest
> of the CPU instances out.
>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Cc: <linux-pm at vger.kernel.org>
> ---
>  drivers/cpufreq/omap-cpufreq.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/omap-cpufreq.c
> b/drivers/cpufreq/omap-cpufreq.c
> index 17fa04d..0ee824c 100644
> --- a/drivers/cpufreq/omap-cpufreq.c
> +++ b/drivers/cpufreq/omap-cpufreq.c
> @@ -221,7 +221,7 @@ static int __cpuinit omap_cpu_init(struct
> cpufreq_policy *policy)
>         if (atomic_inc_return(&freq_table_users) == 1)
>                 result = opp_init_cpufreq_table(mpu_dev, &freq_table);
>
> -       if (result) {
> +       if (result || !freq_table) {
>                 dev_err(mpu_dev, "%s: cpu%d: failed creating freq
> table[%d]\n",
>                                 __func__, policy->cpu, result);
>                 goto fail_ck;

The freq_table use count seems to be buggy in that case.
Something like below should fix the issue.
Feel free to update your patch with below if you agree.

diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 17fa04d..fd97c3d 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *po

        policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);

-       if (atomic_inc_return(&freq_table_users) == 1)
+       if (freq_table)
                result = opp_init_cpufreq_table(mpu_dev, &freq_table);

        if (result) {
@@ -227,6 +227,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *po
                goto fail_ck;
        }

+       atomic_inc_return(&freq_table_users);
        result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
        if (result)
                goto fail_table;


From lee.jones at linaro.org  Wed Aug  8 07:40:38 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 12:40:38 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120808094952.GH16861@opensource.wolfsonmicro.com>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
 <20120808080411.GB4728@gmail.com>
 <20120808094952.GH16861@opensource.wolfsonmicro.com>
Message-ID: <20120808114037.GB8227@gmail.com>

On Wed, Aug 08, 2012 at 10:49:52AM +0100, Mark Brown wrote:
> On Wed, Aug 08, 2012 at 09:04:12AM +0100, Lee Jones wrote:
> 
> > During non-DT boot:
> >  - Platform data is passed, which contains an IRQ base
> >  - If an IRQ base is requested we use it to register a Legacy IRQ Domain
> >  - MFD adds the IRQ base to the hwirq and registers it as a virq
> 
> Just don't do this step - the only reason to do it is for mapping back
> into a linear domain but if you're going to do this...
> 
> >  - AB8500 child devices use *_get_virq() to convert virq to virq - *ERROR*
> 
> ...then it's redundant.  The mapping functions in the domain code
> replace this functionality.

No, the other way round. This is now required all the time.

Now we force the use of hwirq, the driver needs to convert that into a
virq before requesting the resource. So we need to put *_get_virq()'s into
every child device that requests an IRQ.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From hvaibhav at ti.com  Wed Aug  8 07:43:25 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 8 Aug 2012 11:43:25 +0000
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <5021CA01.2020206@gmail.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
 <50213214.7050505@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
 <5021CA01.2020206@gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA897EA@DBDE01.ent.ti.com>

On Wed, Aug 08, 2012 at 07:38:01, Rob Herring wrote:
> On 08/07/2012 10:53 AM, Hiremath, Vaibhav wrote:
> > On Tue, Aug 07, 2012 at 20:49:48, Rob Herring wrote:
> >> On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
> >>> If the module requires only one clocksource to function, then
> >>> driver can very well call clk_get() api with "con_id = NULL",
> >>>
> >>>        clk = clk_get(dev, NULL);
> >>>
> >>> And platform code should respect this and return valid clk handle.
> >>> That means, now the clk_get() api would rely on dev_id, and platform
> >>> code should either have clk node with matching dev_id (with con_id=NULL)
> >>> or return dummy clk node.
> >>>
> >>> With DT support, we can fix the dev_id for particular module
> >>> using "struct of_dev_auxdata" to satisfy above clk framework requirement.
> >>>
> >>> In case of AM33XX, we required this for the DCAN module, so this
> >>> patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
> >>>
> >>> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> >>> Cc: Tony Lindgren <tony at atomide.com>
> >>> Cc: Paul Walmsley <paul at pwsan.com>
> >>> Cc: Benoit Cousson <b-cousson at ti.com>
> >>> Cc: Grant Likely <grant.likely at secretlab.ca>
> >>> ---
> >>> This patch is boot tested on BeagleBone platform, and checked for
> >>> clk_get() return value in d_can module driver.
> >>>
> >>>  arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
> >>>  1 files changed, 17 insertions(+), 1 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> >>> index 6f93a20..c9b7903 100644
> >>> --- a/arch/arm/mach-omap2/board-generic.c
> >>> +++ b/arch/arm/mach-omap2/board-generic.c
> >>> @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
> >>>  	{ }
> >>>  };
> >>>
> >>> +/*
> >>> + * Lookup table for attaching a specific name and platform_data pointer to
> >>> + * devices as they get created by of_platform_populate(). Ideally this table
> >>> + * would not exist, but the current clock implementation depends on some devices
> >>> + * having a specific name OR to satisfy NULL con_id requirement from driver.
> >>> + */
> >>> +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
> >>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
> >>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
> >>> +	{ },
> >>> +};
> >>
> >> Adding an additional clkdev lookup accomplishes the same thing and is a
> >> cleaner solution.
> >>
> > 
> > That is also required and I have submitted patch for the same -
> > 
> > http://www.spinics.net/lists/arm-kernel/msg187998.html
> 
> That only adds the non-DT name. What I'm saying is you can have 2 lookup
> names for the same clock.
> 
> > 
> > With DT support, I am getting dev_id as -
> > 
> >  - Without "reg" property: d_can.16 and d_can.17,
> >    (I believe it changes dynamically here)
> > 
> >  - With "reg" property: 481cc000.d_can and 481d0000.d_can
> > 
> > Which is not so intuitive, I would like to see them as per Spec/TRM, so 
> > doesn't this patch make sense?
> 
> The spec doesn't have a base address for the module? This name is going
> to get used in sysfs anyway, and the old name should be going away.
> 

This is certainly going to change user interface change, and I thought we 
should not change the user interface irrespective of whether it is DT or 
non-DT.
Few points, which I do care about, are,

1. request_irq():
   For the driver if I am using dev_name(dev) as for the 3rd argument, which 
   will now different with DT support - brings change in user interface.

   Non-DT:
    #cat /proc/interrupts
               CPU0
    52:          0      INTC  xxx0
    55:          0      INTC  xxx1

   DT:
    #cat /proc/interrupts
               CPU0
    52:          0      INTC  481cc000.xxx
    55:          0      INTC  481d0000.xxx


2. SYSFS:
   For example,
   Without auxdata:
     /sys/devices/481cc000.xxx/
     /sys/devices/481d0000.xxx/

   With auxdata:
     /sys/devices/xxx.0/
     /sys/devices/xxx.1/

   From user perspective, I still would not want to change the existing 
   naming convention.

3. Certainly I don't want user to go back to spec everytime to find out 
   which address is mapped to which instance of module.
   Also, in addition to that, in case of SoC's like AM33xx (for that matter, 
   any embedded SoC) we have different domains and modules are placed in 
   different domains as per use-cases.
   For example, in this case, can0 is places in wakeup domain and can1 is 
   placed in per-domain. Some boards might use only one instance or some 
   board might use both of them.

   I still would like to keep instance number wherever user interface comes 
   into picture and populate base address as an additional info to user.


I may be missing something, may be I am not able to see the bigger picture 
here.

Grant/Benoit, May be you can conform and put your opinion on this.

Thanks,
Vaibhav


From pawel.moll at arm.com  Wed Aug  8 07:48:20 2012
From: pawel.moll at arm.com (Pawel Moll)
Date: Wed, 08 Aug 2012 12:48:20 +0100
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1344426500.2435.39.camel@hornet>

On Mon, 2012-08-06 at 17:32 +0100, Linus Walleij wrote:
> This converts the ARM RealView machine over to using the common
> clock. The approach is similar to the one used for the Integrator,
> and we're reusing the ICST wrapper code.

I've just tried it with v3.6-rc1 and an EB Model and I get this:

------------[ cut here ]------------
WARNING: at /home/pawmol01/src/kernel.org/linux/kernel/timer.c:1076 del_timer_sync+0x34/0x5c()
Modules linked in:
[<c0014054>] (unwind_backtrace+0x0/0xe0) from [<c001ca3c>] (warn_slowpath_common+0x4c/0x64)
[<c001ca3c>] (warn_slowpath_common+0x4c/0x64) from [<c001ca6c>] (warn_slowpath_null+0x18/0x1c)
[<c001ca6c>] (warn_slowpath_null+0x18/0x1c) from [<c00285b8>] (del_timer_sync+0x34/0x5c)
[<c00285b8>] (del_timer_sync+0x34/0x5c) from [<c01d57e4>] (led_set_brightness+0x14/0x4c)
[<c01d57e4>] (led_set_brightness+0x14/0x4c) from [<c01d6270>] (led_trigger_event+0x30/0x70)
[<c01d6270>] (led_trigger_event+0x30/0x70) from [<c01c7ee8>] (mmc_request_done+0x68/0x90)
[<c01c7ee8>] (mmc_request_done+0x68/0x90) from [<c01d5770>] (mmci_irq+0x274/0x2d4)
[<c01d5770>] (mmci_irq+0x274/0x2d4) from [<c005a090>] (handle_irq_event_percpu+0x2c/0x170)
[<c005a090>] (handle_irq_event_percpu+0x2c/0x170) from [<c005a22c>] (handle_irq_event+0x58/0x78)
[<c005a22c>] (handle_irq_event+0x58/0x78) from [<c005ce68>] (handle_fasteoi_irq+0xcc/0x13c)
[<c005ce68>] (handle_fasteoi_irq+0xcc/0x13c) from [<c0059ae8>] (generic_handle_irq+0x20/0x30)
[<c0059ae8>] (generic_handle_irq+0x20/0x30) from [<c000eafc>] (handle_IRQ+0x78/0xb8)
[<c000eafc>] (handle_IRQ+0x78/0xb8) from [<c0008468>] (gic_handle_irq+0x3c/0x60)
[<c0008468>] (gic_handle_irq+0x3c/0x60) from [<c000d820>] (__irq_svc+0x40/0x54)
Exception stack(0xcf83be20 to 0xcf83be68)
be20: cfbfd26c 60000013 00130013 00000000 cf83be84 cfbfd000 00000000 cf83be94
be40: cf83beb8 c01c989c 00000000 00000000 00000000 cf83be68 c01c7f80 c02aaac0
be60: 40000013 ffffffff
[<c000d820>] (__irq_svc+0x40/0x54) from [<c02aaac0>] (_raw_spin_unlock_irqrestore+0x2c/0x30)
[<c02aaac0>] (_raw_spin_unlock_irqrestore+0x2c/0x30) from [<c01c7f80>] (mmc_wait_for_req_done+0x70/0x74)
[<c01c7f80>] (mmc_wait_for_req_done+0x70/0x74) from [<c01c83b8>] (mmc_wait_for_cmd+0x64/0x74)        
[<c01c83b8>] (mmc_wait_for_cmd+0x64/0x74) from [<c01cfcfc>] (mmc_send_io_op_cond+0x58/0xc4)
[<c01cfcfc>] (mmc_send_io_op_cond+0x58/0xc4) from [<c01cf8b0>] (mmc_attach_sdio+0x3c/0x304)
[<c01cf8b0>] (mmc_attach_sdio+0x3c/0x304) from [<c01c9ab0>] (mmc_rescan+0x214/0x290)
[<c01c9ab0>] (mmc_rescan+0x214/0x290) from [<c00328f4>] (process_one_work+0x240/0x3b8)
[<c00328f4>] (process_one_work+0x240/0x3b8) from [<c0032d70>] (worker_thread+0x2d8/0x434)
[<c0032d70>] (worker_thread+0x2d8/0x434) from [<c00373b0>] (kthread+0x84/0x94)
[<c00373b0>] (kthread+0x84/0x94) from [<c000ed44>] (kernel_thread_exit+0x0/0x8)
---[ end trace 93fc2bf490575317 ]---

I'm not sure who's fault it is (may be mine), will try to figure out
what is going on...

Cheers!

Pawe?




From b-cousson at ti.com  Wed Aug  8 07:50:53 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 8 Aug 2012 13:50:53 +0200
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <5022529D.3090406@ti.com>

Hi Peter,

On 08/08/2012 11:41 AM, Peter Ujfalusi wrote:
> Support for loading the twl4030 audio module via devicetree.
> Sub devices for codec and vibra will be created as mfd devices once the
> core MFD driver is loaded when the kernel is booted with a DT blob.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> ---
>  .../devicetree/bindings/mfd/twl4030-audio.txt      |   51 +++++++++++++++
>  drivers/mfd/twl4030-audio.c                        |   65 +++++++++++++++++---
>  2 files changed, 108 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt
> 
> diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
> new file mode 100644
> index 0000000..bc45025
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
> @@ -0,0 +1,51 @@
> +Texas Instruments TWL family (twl4030) audio module
> +
> +The audio module inside the TWL family consist of an audio codec and a vibra
> +driver.
> +
> +Required properties:
> +- compatible : must be "ti,twl4030-audio"
> +- ti,audio_mclk: Master clock frequency used on the board. Supported
> +	         frequencies: 19200000, 26000000 and 38400000

Since you care about the frequency only you can use the generic
attribute: clock-frequency (in your example, I2C is using it).


That being said, since we do have the clock binding now, maybe we should
create a clock provider at board level for the sys_clk and thus you will
just have to create a phandle to it in your audio description.

In theory OMAP and other components will thus have to use that sys_clock
reference as well.

Regards,
Benoit


> +
> +Optional properties, nodes:
> +
> +Audio functionality:
> +- codec { }: Need to be present if the audio functionality is used. Within this
> +	     section the following options can be used:
> +- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts
> +		    from the start of the recorded sample (in ms)
> +-ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise
> +-ti,hs_extmute: Use external mute for HS pop reduction
> +-ti,hs_extmute_gpio: Use external GPIO to control the external mute
> +-ti,hs_extmute_disable_level: The desired level of the GPIO line when the
> +			      external mute is disabled. valuse: 0 or 1
> +-ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
> +		      valid values.
> +
> +Vibra functionality
> +- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if
> +		   missing or it is 0, the vibra functionality is disabled.
> +
> +Example:
> +&i2c1 {
> +	clock-frequency = <2600000>;
> +
> +	twl: twl at 48 {
> +		reg = <0x48>;
> +		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
> +		interrupt-parent = <&intc>;
> +
> +		twl_audio: audio {
> +			compatible = "ti,twl4030-audio";
> +			ti,audio_mclk = <26000000>;
> +
> +			ti,enable-vibra = <1>;
> +
> +			codec {
> +				ti,ramp_delay_value = <3>;
> +			};
> +
> +		};
> +	};
> +};
> diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
> index ca2d669..a4df8b3a 100644
> --- a/drivers/mfd/twl4030-audio.c
> +++ b/drivers/mfd/twl4030-audio.c
> @@ -28,6 +28,8 @@
>  #include <linux/kernel.h>
>  #include <linux/fs.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
>  #include <linux/i2c/twl.h>
>  #include <linux/mfd/core.h>
>  #include <linux/mfd/twl4030-audio.h>
> @@ -156,15 +158,46 @@ unsigned int twl4030_audio_get_mclk(void)
>  }
>  EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk);
>  
> +static bool twl4030_audio_has_codec(struct twl4030_audio_data *pdata,
> +			      struct device_node *node)
> +{
> +	if (pdata && pdata->codec)
> +		return true;
> +
> +#ifdef CONFIG_OF
> +	if (of_find_node_by_name(node, "codec"))
> +		return true;
> +#endif
> +
> +	return false;
> +}
> +
> +static bool twl4030_audio_has_vibra(struct twl4030_audio_data *pdata,
> +			      struct device_node *node)
> +{
> +	int vibra;
> +
> +	if (pdata && pdata->vibra)
> +		return true;
> +
> +#ifdef CONFIG_OF
> +	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
> +		return true;
> +#endif
> +
> +	return false;
> +}
> +
>  static int __devinit twl4030_audio_probe(struct platform_device *pdev)
>  {
>  	struct twl4030_audio *audio;
>  	struct twl4030_audio_data *pdata = pdev->dev.platform_data;
> +	struct device_node *node = pdev->dev.of_node;
>  	struct mfd_cell *cell = NULL;
>  	int ret, childs = 0;
>  	u8 val;
>  
> -	if (!pdata) {
> +	if (!pdata && !node) {
>  		dev_err(&pdev->dev, "Platform data is missing\n");
>  		return -EINVAL;
>  	}
> @@ -175,7 +208,12 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	mutex_init(&audio->mutex);
> -	audio->audio_mclk = pdata->audio_mclk;
> +	if (pdata)
> +		audio->audio_mclk = pdata->audio_mclk;
> +#ifdef CONFIG_OF
> +	else
> +		of_property_read_u32(node, "ti,audio_mclk", &audio->audio_mclk);
> +#endif
>  
>  	/* Configure APLL_INFREQ and disable APLL if enabled */
>  	switch (audio->audio_mclk) {
> @@ -202,18 +240,22 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
>  	audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL;
>  	audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN;
>  
> -	if (pdata->codec) {
> +	if (twl4030_audio_has_codec(pdata, node)) {
>  		cell = &audio->cells[childs];
>  		cell->name = "twl4030-codec";
> -		cell->platform_data = pdata->codec;
> -		cell->pdata_size = sizeof(*pdata->codec);
> +		if (pdata) {
> +			cell->platform_data = pdata->codec;
> +			cell->pdata_size = sizeof(*pdata->codec);
> +		}
>  		childs++;
>  	}
> -	if (pdata->vibra) {
> +	if (twl4030_audio_has_vibra(pdata, node)) {
>  		cell = &audio->cells[childs];
>  		cell->name = "twl4030-vibra";
> -		cell->platform_data = pdata->vibra;
> -		cell->pdata_size = sizeof(*pdata->vibra);
> +		if (pdata) {
> +			cell->platform_data = pdata->vibra;
> +			cell->pdata_size = sizeof(*pdata->vibra);
> +		}
>  		childs++;
>  	}
>  
> @@ -245,10 +287,17 @@ static int __devexit twl4030_audio_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static const struct of_device_id twl4030_audio_of_match[] = {
> +	{.compatible = "ti,twl4030-audio", },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, twl4030_audio_of_match);
> +
>  static struct platform_driver twl4030_audio_driver = {
>  	.driver		= {
>  		.owner	= THIS_MODULE,
>  		.name	= "twl4030-audio",
> +		.of_match_table = twl4030_audio_of_match,
>  	},
>  	.probe		= twl4030_audio_probe,
>  	.remove		= __devexit_p(twl4030_audio_remove),
> 



From ian.molton at codethink.co.uk  Wed Aug  8 07:51:02 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Wed, 08 Aug 2012 12:51:02 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <50223428.6030506@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <20120807.162923.34400427265666163.davem@davemloft.net>
 <201208080816.29218.arnd@arndb.de> <50223428.6030506@codethink.co.uk>
Message-ID: <502252A6.4090409@codethink.co.uk>

On 08/08/12 10:40, Ian Molton wrote:
> On 08/08/12 09:16, Arnd Bergmann wrote:
>
>> I'd prefer to take the entire series through the arm-soc tree from
>> the kirkwood maintainers. We first have to work out the bindings
>> though, since the current patch introduces a new one that is
>> incompatible with the one we were using on powerpc with open
>> firmware before.

Looking at the ethernet-group stuff, specifically from
arch/powerpc/boot/dts/prpmc2800.dts, which I've taken as a base for
the below:


The SMI / PHY stuff should look very similar, so I'm happy with something
like:

mdio at 2000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "mdio";
                compatible = "marvell,mv643xx-mdio";
                phy0: ethernet-phy at 0 {
                        device_type = "ethernet-phy";
                        compatible = "marvell,whatever";
                        interrupts = <76>;
                        interrupt-parent = <&mpic>;
                        reg = <0 32>;          // Auto probed phy addr
                };

                phy1: ethernet-phy at 3 {
                        device_type = "ethernet-phy";
                        compatible = "marvell,whatever";
                        interrupts = <77>;
                        interrupt-parent = <&mpic>;
                        reg = <3 1>;            // specified phy addr
                };

                ... and so on.
}

Where we can use the reg parameter to allow auto-probing, by
specifying a size of 32 (32 phy addrs max).


The ethernet driver itself is more complicated:

We have the following considerations:

* we have one MDIO bus, typically, shared between all the MACs / PHYs.
* each ethernet device can multiple ports (up to three), each with its
  own MAC/PHY.
* MAC <-> PHY mapping can be specified, probed (ugh!) or a (gah!)
  mix of the two.
* existing D-T users, albeit not well documented / code complete.
* some port address ranges overlap (MIB counters, MCAST / UNICAST
  tables, etc.

The existing ethernet-group idea only works because the current
platform-device based driver doesnt really do proper resource
management, and thus the MAC registers are actually mapped by
the MDIO driver.

I don't think that preserving this bad behaviour is a good idea, which
leaves us with two choices:

1) My preferred solution - allow each device to specify up to three
interrupts, MACs, and PHYs. This is clean in that it doesnt require
multiply instantiating a driver three times over the same address
space.

ethernet at 2400 {
                compatible = "marvell,mv643xx-eth";
                reg = <0x2400 0x1c00>
                interrupt_parent = <&mpic>;
                ports = <3>;
                interrupts = <4>, <5>, <6>;
                phys = <&phy0>, <&phy1>, <&phy2>;
};

ethernet at 6400 {
                compatible = "marvell,mv643xx-eth";
                reg = <0x6400 0x1c00>
                interrupt_parent = <&mpic>;
                ports = <1>;
                interrupts = <4>;
                phys = <&phy3>;
};

Note that the address is 2400, not 2000 - since this driver no longer
would share its address range with the MDIO driver.

This method would require a small amount of rework in the driver to
set up <n> ports, rather than just one.

2) Create some kind of pseudo-ethernet group device that manages
all the work for some sort of lightweight ethernet device, one per
port. This can never be done cleanly since the port address ranges
overlap:

pseudo_eth at 2400 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "marvell,mv643xx-shared-eth"
        reg = <0x2400 0x1c00>;

        ethernet at 0 {
                compatible = "marvell,mv643xx-port";
                interrupts = <4>;
                interrupt_parent = <&mpic>;
                phy = <&phy0>;
        };

        ethernet at 1 {
                compatible = "marvell,mv643xx-port";
                interrupts = <5>;
                interrupt_parent = <&mpic>;
                phy = <&phy1>;
        };

        ethernet at 2 {
                compatible = "marvell,mv643xx-port";
                interrupts = <6>;
                interrupt_parent = <&mpic>;
                phy = <&phy2>;
        };
}
pseudo_eth at 6400 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "marvell,mv643xx-shared-eth"
        reg = <0x6400 0x1c00>;

        ethernet at 0 {
                compatible = "marvell,mv643xx-port";
                interrupts = <4>;
                interrupt_parent = <&mpic>;
                phy = <&phy3>;
        };
};

Thoughts?

-Ian


From pawel.moll at arm.com  Wed Aug  8 07:52:33 2012
From: pawel.moll at arm.com (Pawel Moll)
Date: Wed, 08 Aug 2012 12:52:33 +0100
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1344426500.2435.39.camel@hornet>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <1344426500.2435.39.camel@hornet>
Message-ID: <1344426753.2435.40.camel@hornet>

On Wed, 2012-08-08 at 12:48 +0100, Pawel Moll wrote:
> On Mon, 2012-08-06 at 17:32 +0100, Linus Walleij wrote:
> > This converts the ARM RealView machine over to using the common
> > clock. The approach is similar to the one used for the Integrator,
> > and we're reusing the ICST wrapper code.
> 
> I've just tried it with v3.6-rc1 and an EB Model and I get this:
> 
> ------------[ cut here ]------------
> WARNING: at /home/pawmol01/src/kernel.org/linux/kernel/timer.c:1076 del_timer_sync+0x34/0x5c()

Err. Ignore that. The same happens without your patch :-)

Will try with 3.5.

Pawe?




From linus.walleij at linaro.org  Wed Aug  8 07:55:30 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 13:55:30 +0200
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1344426753.2435.40.camel@hornet>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <1344426500.2435.39.camel@hornet> <1344426753.2435.40.camel@hornet>
Message-ID: <CACRpkdYkoeH09H6c4WEw40hpP9+oRD4pa0-yBk1L02yfao2sgg@mail.gmail.com>

On Wed, Aug 8, 2012 at 1:52 PM, Pawel Moll <pawel.moll at arm.com> wrote:

>> ------------[ cut here ]------------
>> WARNING: at /home/pawmol01/src/kernel.org/linux/kernel/timer.c:1076 del_timer_sync+0x34/0x5c()
>
> Err. Ignore that. The same happens without your patch :-)
>
> Will try with 3.5.

Hm it boots like a charm on PB1176, what's so very different about the EB?

Oh well. Are you maintaining RealView EB, BTW?

Yours,
Linus Walleij


From peter.ujfalusi at ti.com  Wed Aug  8 08:05:44 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 15:05:44 +0300
Subject: [PATCH RESEND v2 1/2] arm/dts: Add AM33XX basic pinctrl support
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
References: <1343144719-26352-1-git-send-email-anilkumar@ti.com>
 <1343144719-26352-2-git-send-email-anilkumar@ti.com>
 <50125B1C.8000209@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
Message-ID: <50225618.9070501@ti.com>

On 07/31/2012 04:37 PM, AnilKumar, Chimata wrote:
>> I'm just curious about the size here: how it ended up as 0x0338?
>> While looking at the TRM of AM335x I can come up with 0x0238 (0x44e10800 -
>> 0x44e10a38), but I don't see any sings of the remaining 0x0100 to be
>> documented at least.
> 
> No, pinmux registers are available till 0x44E10B38, look at AM335x latest TRM
> or pinmux utility (we cannot find the exact offsets but pins we can find after
> 0x0A38, conf_ddr_resetn) at http://www.ti.com/tool/pinmuxtool

I have looked at the latest TRM (Rev F, SPRUH73F -  public TRM) and there is
not mention of registers between 0x0a34 and 0x0e00.
I can not even find any reference of conf_ddr_resetn register either in the TRM.
I can not check with the pinmuxtool since it is crashing with wine under Linux.
There could be registers after 0x0a34, but they are not publicly documented...

-- 
P?ter


From linus.walleij at stericsson.com  Wed Aug  8 08:05:43 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 8 Aug 2012 14:05:43 +0200
Subject: [PATCH v2] pinctrl/nomadik: add ASIC DB8450 pinctrl driver
Message-ID: <1344427543-29524-1-git-send-email-linus.walleij@stericsson.com>

From: Patrice Chotard <patrice.chotard at stericsson.com>

This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.

Signed-off-by: Patrice Chotard <patrice.chotard at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Check the explicit "version" variable instead of indirectly
  inspecting platform data as pointed out by Stephen.
---
 drivers/pinctrl/Kconfig                  |   4 +
 drivers/pinctrl/Makefile                 |   1 +
 drivers/pinctrl/pinctrl-nomadik-db8540.c | 999 +++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-nomadik.c        |   3 +
 drivers/pinctrl/pinctrl-nomadik.h        |  14 +
 5 files changed, 1021 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-nomadik-db8540.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..062f1a3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -90,6 +90,10 @@ config PINCTRL_DB8500
 	bool "DB8500 pin controller driver"
 	depends on PINCTRL_NOMADIK && ARCH_U8500
 
+config PINCTRL_DB8540
+	bool "DB8540 pin controller driver"
+	depends on PINCTRL_NOMADIK && ARCH_U8500
+
 config PINCTRL_PXA168
 	bool "PXA168 pin controller driver"
 	depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..b44538e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
 obj-$(CONFIG_PINCTRL_IMX28)	+= pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_NOMADIK)	+= pinctrl-nomadik.o
 obj-$(CONFIG_PINCTRL_DB8500)	+= pinctrl-nomadik-db8500.o
+obj-$(CONFIG_PINCTRL_DB8540)	+= pinctrl-nomadik-db8540.o
 obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)	+= pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8540.c b/drivers/pinctrl/pinctrl-nomadik-db8540.c
new file mode 100644
index 0000000..3daf665
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8540.c
@@ -0,0 +1,999 @@
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-nomadik.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define _GPIO(offset)		(offset)
+
+#define DB8540_PIN_AH6		_GPIO(0)
+#define DB8540_PIN_AG7		_GPIO(1)
+#define DB8540_PIN_AF2		_GPIO(2)
+#define DB8540_PIN_AD3		_GPIO(3)
+#define DB8540_PIN_AF6		_GPIO(4)
+#define DB8540_PIN_AG6		_GPIO(5)
+#define DB8540_PIN_AD5		_GPIO(6)
+#define DB8540_PIN_AF7		_GPIO(7)
+#define DB8540_PIN_AG5		_GPIO(8)
+#define DB8540_PIN_AH5		_GPIO(9)
+#define DB8540_PIN_AE4		_GPIO(10)
+#define DB8540_PIN_AD1		_GPIO(11)
+#define DB8540_PIN_AD2		_GPIO(12)
+#define DB8540_PIN_AC2		_GPIO(13)
+#define DB8540_PIN_AC4		_GPIO(14)
+#define DB8540_PIN_AC3		_GPIO(15)
+#define DB8540_PIN_AH7		_GPIO(16)
+#define DB8540_PIN_AE7		_GPIO(17)
+/* Hole */
+#define DB8540_PIN_AF8		_GPIO(22)
+#define DB8540_PIN_AH11		_GPIO(23)
+#define DB8540_PIN_AG11		_GPIO(24)
+#define DB8540_PIN_AF11		_GPIO(25)
+#define DB8540_PIN_AH10		_GPIO(26)
+#define DB8540_PIN_AG10		_GPIO(27)
+#define DB8540_PIN_AF10		_GPIO(28)
+/* Hole */
+#define DB8540_PIN_AD4		_GPIO(33)
+#define DB8540_PIN_AF3		_GPIO(34)
+#define DB8540_PIN_AF5		_GPIO(35)
+#define DB8540_PIN_AG4		_GPIO(36)
+#define DB8540_PIN_AF9		_GPIO(37)
+#define DB8540_PIN_AE8		_GPIO(38)
+/* Hole */
+#define DB8540_PIN_M26		_GPIO(64)
+#define DB8540_PIN_M25		_GPIO(65)
+#define DB8540_PIN_M27		_GPIO(66)
+#define DB8540_PIN_N25		_GPIO(67)
+/* Hole */
+#define DB8540_PIN_M28		_GPIO(70)
+#define DB8540_PIN_N26		_GPIO(71)
+#define DB8540_PIN_M22		_GPIO(72)
+#define DB8540_PIN_N22		_GPIO(73)
+#define DB8540_PIN_N27		_GPIO(74)
+#define DB8540_PIN_N28		_GPIO(75)
+#define DB8540_PIN_P22		_GPIO(76)
+#define DB8540_PIN_P28		_GPIO(77)
+#define DB8540_PIN_P26		_GPIO(78)
+#define DB8540_PIN_T22		_GPIO(79)
+#define DB8540_PIN_R27		_GPIO(80)
+#define DB8540_PIN_P27		_GPIO(81)
+#define DB8540_PIN_R26		_GPIO(82)
+#define DB8540_PIN_R25		_GPIO(83)
+#define DB8540_PIN_U22		_GPIO(84)
+#define DB8540_PIN_T27		_GPIO(85)
+#define DB8540_PIN_T25		_GPIO(86)
+#define DB8540_PIN_T26		_GPIO(87)
+/* Hole */
+#define DB8540_PIN_AF20		_GPIO(116)
+#define DB8540_PIN_AG21		_GPIO(117)
+#define DB8540_PIN_AH19		_GPIO(118)
+#define DB8540_PIN_AE19		_GPIO(119)
+#define DB8540_PIN_AG18		_GPIO(120)
+#define DB8540_PIN_AH17		_GPIO(121)
+#define DB8540_PIN_AF19		_GPIO(122)
+#define DB8540_PIN_AF18		_GPIO(123)
+#define DB8540_PIN_AE18		_GPIO(124)
+#define DB8540_PIN_AG17		_GPIO(125)
+#define DB8540_PIN_AF17		_GPIO(126)
+#define DB8540_PIN_AE17		_GPIO(127)
+#define DB8540_PIN_AC27		_GPIO(128)
+#define DB8540_PIN_AD27		_GPIO(129)
+#define DB8540_PIN_AE28		_GPIO(130)
+#define DB8540_PIN_AG26		_GPIO(131)
+#define DB8540_PIN_AF25		_GPIO(132)
+#define DB8540_PIN_AE27		_GPIO(133)
+#define DB8540_PIN_AF27		_GPIO(134)
+#define DB8540_PIN_AG28		_GPIO(135)
+#define DB8540_PIN_AF28		_GPIO(136)
+#define DB8540_PIN_AG25		_GPIO(137)
+#define DB8540_PIN_AG24		_GPIO(138)
+#define DB8540_PIN_AD25		_GPIO(139)
+#define DB8540_PIN_AH25		_GPIO(140)
+#define DB8540_PIN_AF26		_GPIO(141)
+#define DB8540_PIN_AF23		_GPIO(142)
+#define DB8540_PIN_AG23		_GPIO(143)
+#define DB8540_PIN_AE25		_GPIO(144)
+#define DB8540_PIN_AH24		_GPIO(145)
+#define DB8540_PIN_AJ25		_GPIO(146)
+#define DB8540_PIN_AG27		_GPIO(147)
+#define DB8540_PIN_AH23		_GPIO(148)
+#define DB8540_PIN_AE26		_GPIO(149)
+#define DB8540_PIN_AE24		_GPIO(150)
+#define DB8540_PIN_AJ24		_GPIO(151)
+#define DB8540_PIN_AE21		_GPIO(152)
+#define DB8540_PIN_AG22		_GPIO(153)
+#define DB8540_PIN_AF21		_GPIO(154)
+#define DB8540_PIN_AF24		_GPIO(155)
+#define DB8540_PIN_AH22		_GPIO(156)
+#define DB8540_PIN_AJ23		_GPIO(157)
+#define DB8540_PIN_AH21		_GPIO(158)
+#define DB8540_PIN_AG20		_GPIO(159)
+#define DB8540_PIN_AE23		_GPIO(160)
+#define DB8540_PIN_AH20		_GPIO(161)
+#define DB8540_PIN_AG19		_GPIO(162)
+#define DB8540_PIN_AF22		_GPIO(163)
+#define DB8540_PIN_AJ21		_GPIO(164)
+#define DB8540_PIN_AD26		_GPIO(165)
+#define DB8540_PIN_AD28		_GPIO(166)
+#define DB8540_PIN_AC28		_GPIO(167)
+#define DB8540_PIN_AC26		_GPIO(168)
+/* Hole */
+#define DB8540_PIN_J3		_GPIO(192)
+#define DB8540_PIN_H1		_GPIO(193)
+#define DB8540_PIN_J2		_GPIO(194)
+#define DB8540_PIN_H2		_GPIO(195)
+#define DB8540_PIN_H3		_GPIO(196)
+#define DB8540_PIN_H4		_GPIO(197)
+#define DB8540_PIN_G2		_GPIO(198)
+#define DB8540_PIN_G3		_GPIO(199)
+#define DB8540_PIN_G4		_GPIO(200)
+#define DB8540_PIN_F2		_GPIO(201)
+#define DB8540_PIN_C6		_GPIO(202)
+#define DB8540_PIN_B6		_GPIO(203)
+#define DB8540_PIN_B7		_GPIO(204)
+#define DB8540_PIN_A7		_GPIO(205)
+#define DB8540_PIN_D7		_GPIO(206)
+#define DB8540_PIN_D8		_GPIO(207)
+#define DB8540_PIN_F3		_GPIO(208)
+#define DB8540_PIN_E2		_GPIO(209)
+#define DB8540_PIN_C7		_GPIO(210)
+#define DB8540_PIN_B8		_GPIO(211)
+#define DB8540_PIN_C10		_GPIO(212)
+#define DB8540_PIN_C8		_GPIO(213)
+#define DB8540_PIN_C9		_GPIO(214)
+/* Hole */
+#define DB8540_PIN_B9		_GPIO(219)
+#define DB8540_PIN_A10		_GPIO(220)
+#define DB8540_PIN_D9		_GPIO(221)
+#define DB8540_PIN_B11		_GPIO(222)
+#define DB8540_PIN_B10		_GPIO(223)
+#define DB8540_PIN_E10		_GPIO(224)
+#define DB8540_PIN_B12		_GPIO(225)
+#define DB8540_PIN_D10		_GPIO(226)
+#define DB8540_PIN_D11		_GPIO(227)
+#define DB8540_PIN_AJ6		_GPIO(228)
+#define DB8540_PIN_B13		_GPIO(229)
+#define DB8540_PIN_C12		_GPIO(230)
+#define DB8540_PIN_B14		_GPIO(231)
+#define DB8540_PIN_E11		_GPIO(232)
+/* Hole */
+#define DB8540_PIN_D12		_GPIO(256)
+#define DB8540_PIN_D15		_GPIO(257)
+#define DB8540_PIN_C13		_GPIO(258)
+#define DB8540_PIN_C14		_GPIO(259)
+#define DB8540_PIN_C18		_GPIO(260)
+#define DB8540_PIN_C16		_GPIO(261)
+#define DB8540_PIN_B16		_GPIO(262)
+#define DB8540_PIN_D18		_GPIO(263)
+#define DB8540_PIN_C15		_GPIO(264)
+#define DB8540_PIN_C17		_GPIO(265)
+#define DB8540_PIN_B17		_GPIO(266)
+#define DB8540_PIN_D17		_GPIO(267)
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
+	PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
+	PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
+	PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
+	PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
+	PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
+	PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
+	PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
+	PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
+	PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
+	PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
+	PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
+	PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
+	PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
+	PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
+	PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
+	PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
+	PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
+	PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
+	PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
+	PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
+	PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
+	PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
+	PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
+	PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
+	PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
+	PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
+	PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
+	PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
+	PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
+	PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
+	PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
+	PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
+	PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
+	PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
+	PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
+	PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
+	PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
+	PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
+	PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
+	PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
+	PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
+	PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
+	PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
+	PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
+	PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
+	PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
+	PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
+	PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
+	PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
+	PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
+	PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
+	PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
+	PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
+	PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
+	PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
+	PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
+	PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
+	PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
+	PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
+	PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
+	PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
+	PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
+	PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
+	PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
+	PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
+	PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
+	PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
+	PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
+	PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
+	PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
+	PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
+	PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
+	PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
+	PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
+	PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
+	PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
+	PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
+	PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
+	PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
+	PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
+	PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
+	PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
+	PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
+	PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
+	PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
+	PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
+	PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
+	PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
+	PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
+	PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
+	PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
+	PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
+	PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
+	PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
+	PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
+	PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
+	PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
+	PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
+	PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
+	PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
+	PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
+	PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
+	PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
+	PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
+	PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
+	PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
+	PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
+	PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
+	PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
+	PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
+	PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
+	PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
+	PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
+	PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
+	PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
+	PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
+	PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
+	PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
+	PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
+	PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
+	PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
+	PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
+	PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
+	PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
+	PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
+	PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
+	PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
+	PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
+	PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
+	PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
+	PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
+	PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
+	PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
+	PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
+	PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
+	PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
+	/* Hole */
+	PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
+	PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
+	PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
+	PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
+	PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
+	PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
+	PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
+	PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
+	PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
+	PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
+	PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
+	PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
+};
+
+#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
+			.pin_base = b, .npins = c }
+
+/*
+ * This matches the 32-pin gpio chips registered by the GPIO portion. This
+ * cannot be const since we assign the struct gpio_chip * pointer at runtime.
+ */
+static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
+	DB8540_GPIO_RANGE(0, 0, 18),
+	DB8540_GPIO_RANGE(0, 22, 7),
+	DB8540_GPIO_RANGE(1, 33, 6),
+	DB8540_GPIO_RANGE(2, 64, 4),
+	DB8540_GPIO_RANGE(2, 70, 18),
+	DB8540_GPIO_RANGE(3, 116, 12),
+	DB8540_GPIO_RANGE(4, 128, 32),
+	DB8540_GPIO_RANGE(5, 160, 9),
+	DB8540_GPIO_RANGE(6, 192, 23),
+	DB8540_GPIO_RANGE(6, 219, 5),
+	DB8540_GPIO_RANGE(7, 224, 9),
+	DB8540_GPIO_RANGE(8, 256, 12),
+};
+
+/*
+ * Read the pin group names like this:
+ * u0_a_1    = first groups of pins for uart0 on alt function a
+ * i2c2_b_2  = second group of pins for i2c2 on alt function b
+ *
+ * The groups are arranged as sets per altfunction column, so we can
+ * mux in one group at a time by selecting the same altfunction for them
+ * all. When functions require pins on different altfunctions, you need
+ * to combine several groups.
+ */
+
+/* Altfunction A column */
+static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
+					DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+/* Image processor I2C line, this is driven by image processor firmware */
+static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
+	DB8540_PIN_AC4 };
+static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
+	DB8540_PIN_AE7 };
+/* Basic pins of the MMC/SD card 0 interface */
+static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+	DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
+/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
+static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
+
+static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
+static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
+/* LCD interface */
+static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25 };
+static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28 };
+/* D8 thru D11 often used as TVOUT lines */
+static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27 };
+static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
+static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
+	DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
+	DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
+	DB8540_PIN_AG24 };
+static const unsigned ssp1_a_1_pins[] = {  DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+	DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
+/*
+ * Image processor GPIO pins are named "ipgpio" and have their own
+ * numberspace
+ */
+static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
+/* modem i2s interface */
+static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
+	DB8540_PIN_AC28, DB8540_PIN_AC26 };
+static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
+	DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
+	DB8540_PIN_AF18 };
+static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
+static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
+	DB8540_PIN_H2 };
+static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
+	DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
+	DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
+	DB8540_PIN_D8 };
+static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
+	DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+	DB8540_PIN_C9 };
+/* mc1_a_2_pins exclude MC1_FBCLK */
+static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3,	DB8540_PIN_C7,
+	DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
+	DB8540_PIN_C9 };
+static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+	DB8540_PIN_D9 };
+static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
+static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned clkout_a_1_pins[] = { DB8540_PIN_D11, DB8540_PIN_AJ6 };
+static const unsigned clkout_a_2_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
+static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
+	DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
+	DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
+	DB8540_PIN_B17, DB8540_PIN_D17 };
+/* Altfunction B colum */
+static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
+static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
+static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
+static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
+static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
+static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
+static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
+static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+	DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
+static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
+	DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
+	DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
+	DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
+	DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
+static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+	DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
+	DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
+	DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
+	DB8540_PIN_AD25 };
+static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
+static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
+static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
+static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
+static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
+static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
+	DB8540_PIN_AE19 };
+static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
+static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
+static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
+	DB8540_PIN_AE17 };
+static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
+static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
+	DB8540_PIN_C8, DB8540_PIN_C9 };
+static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
+	DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
+	DB8540_PIN_B12 };
+static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
+static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
+static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
+static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
+
+/* Altfunction C column */
+static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
+static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
+static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
+static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
+static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
+static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
+	DB8540_PIN_AF5, DB8540_PIN_AG4 };
+static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
+	DB8540_PIN_AE21 };
+static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
+static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
+static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
+static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
+static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
+static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
+static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
+static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22 };
+static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
+static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
+	DB8540_PIN_AJ21};
+static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
+static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
+static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
+static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
+static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
+static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
+static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AF26, DB8540_PIN_AF23 };
+static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
+	DB8540_PIN_AH24 };
+static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
+static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
+static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
+	DB8540_PIN_AH17 };
+static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
+static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
+static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
+static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
+	DB8540_PIN_E10, DB8540_PIN_B12 };
+static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
+
+/* Other alt C1 column */
+static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
+	DB8540_PIN_AE4, DB8540_PIN_AD1 };
+static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
+	DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
+static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
+static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
+static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
+static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
+	DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
+	DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
+	DB8540_PIN_T25};
+static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_T26 };
+static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23 };
+static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
+	DB8540_PIN_AG23, DB8540_PIN_AE25 };
+static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
+static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
+static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
+
+/* Other alt C2 column */
+static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
+	DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
+static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
+static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
+static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
+static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
+static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
+	DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
+	DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
+	DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
+static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
+static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
+	DB8540_PIN_AE23 };
+static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
+static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
+	DB8540_PIN_AE24 };
+
+/* Other alt C3 column */
+static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
+static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
+	DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
+	DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
+	DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
+
+/* Other alt C4 column */
+static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
+	DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
+	DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
+	DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
+	DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
+static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
+	DB8540_PIN_T27 };
+static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
+	DB8540_PIN_AF21 };
+static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
+	DB8540_PIN_AH22 };
+static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
+	DB8540_PIN_AH21 };
+static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
+	DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
+static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
+
+#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins,		\
+			.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct nmk_pingroup nmk_db8540_groups[] = {
+	/* Altfunction A column */
+	DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
+	DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
+	/* Altfunction B column */
+	DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
+	DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
+	/* Altfunction C column */
+	DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C1 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C2 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C3 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
+
+	/* Other alt C4 column, these are still configured as alt C */
+	DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
+	DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
+
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define DB8540_FUNC_GROUPS(a, b...)	   \
+static const char * const a##_groups[] = { b };
+
+DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
+DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout_a_1", "clkout_a_2");
+DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
+DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
+DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
+DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
+DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
+DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
+DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
+DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
+DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
+DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
+DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
+/* The image processor has 8 GPIO pins that can be muxed out */
+DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
+		"ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
+		"ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
+		"ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
+		"ipgpio4_c_1", "ipgpio4_c_2",
+		"ipgpio5_c_1", "ipgpio5_c_2",
+		"ipgpio6_c_1", "ipgpio6_c_2",
+		"ipgpio7_b_1", "ipgpio7_c_1");
+DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
+DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
+DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
+		"lcdvsi0_a_1", "lcdvsi1_a_1");
+DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
+DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
+DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
+DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
+DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
+DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
+DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
+DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
+		"modaccgpo_oc3_1");
+DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
+		"modaccuartrtccts_oc4_1");
+DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
+DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
+		"modobspwrctrl_oc1_1", "modobspwrrst_c_1",
+		"modobsrefclk_oc1_1", "modobsresout_c_1",
+		"modobsresout_oc1_1", "modobsservice_oc2_1");
+DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
+DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
+DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
+DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
+DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
+		"moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
+DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
+		"moduartstmmux_oc4_1");
+DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
+/*
+ * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
+ * switched around by selecting the altfunction A or B.
+ */
+DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
+		"msp0txrx_b_1");
+DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
+DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
+DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
+DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
+DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
+DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
+/* Select between CS0 on alt B or PS1 on alt C */
+DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
+		"smps0_c_1", "smps1_c_1");
+DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
+DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
+DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
+DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
+DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
+DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
+DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
+DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
+DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
+DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
+DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
+DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
+		"u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
+		"u2txrx_oc1_1");
+DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
+DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
+DB8540_FUNC_GROUPS(usb, "usb_a_1");
+
+
+#define FUNCTION(fname)					\
+	{						\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+static const struct nmk_function nmk_db8540_functions[] = {
+	FUNCTION(apetrig),
+	FUNCTION(clkout),
+	FUNCTION(ddrtrig),
+	FUNCTION(hsi),
+	FUNCTION(hwobs),
+	FUNCTION(hx),
+	FUNCTION(i2c0),
+	FUNCTION(i2c1),
+	FUNCTION(i2c2),
+	FUNCTION(i2c3),
+	FUNCTION(i2c4),
+	FUNCTION(i2c5),
+	FUNCTION(i2c6),
+	FUNCTION(ipgpio),
+	FUNCTION(ipi2c),
+	FUNCTION(kp),
+	FUNCTION(lcd),
+	FUNCTION(lcdb),
+	FUNCTION(mc0),
+	FUNCTION(mc1),
+	FUNCTION(mc2),
+	FUNCTION(mc3),
+	FUNCTION(mc4),
+	FUNCTION(mc5),
+	FUNCTION(modaccgpo),
+	FUNCTION(modaccuart),
+	FUNCTION(modi2s),
+	FUNCTION(modobs),
+	FUNCTION(modprcmudbg),
+	FUNCTION(modrf),
+	FUNCTION(modsmb),
+	FUNCTION(modtrig),
+	FUNCTION(moduart),
+	FUNCTION(modxmip),
+	FUNCTION(msp0),
+	FUNCTION(msp1),
+	FUNCTION(msp2),
+	FUNCTION(msp4),
+	FUNCTION(pwl),
+	FUNCTION(remap),
+	FUNCTION(sbag),
+	FUNCTION(sm),
+	FUNCTION(spi0),
+	FUNCTION(spi1),
+	FUNCTION(spi2),
+	FUNCTION(spi3),
+	FUNCTION(ssp0),
+	FUNCTION(ssp1),
+	FUNCTION(stmape),
+	FUNCTION(stmmod),
+	FUNCTION(tpui),
+	FUNCTION(u0),
+	FUNCTION(u1),
+	FUNCTION(u2),
+	FUNCTION(u3),
+	FUNCTION(u4),
+	FUNCTION(usb)
+};
+
+static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
+	.gpio_ranges = nmk_db8540_ranges,
+	.gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
+	.pins = nmk_db8540_pins,
+	.npins = ARRAY_SIZE(nmk_db8540_pins),
+	.functions = nmk_db8540_functions,
+	.nfunctions = ARRAY_SIZE(nmk_db8540_functions),
+	.groups = nmk_db8540_groups,
+	.ngroups = ARRAY_SIZE(nmk_db8540_groups),
+};
+
+void __devinit
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+	*soc = &nmk_db8540_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 53b0d49..c0c89be 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1722,6 +1722,8 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
 	/* Poke in other ASIC variants here */
 	if (version == PINCTRL_NMK_DB8500)
 		nmk_pinctrl_db8500_init(&npct->soc);
+	if (version == PINCTRL_NMK_DB8540)
+		nmk_pinctrl_db8540_init(&npct->soc);
 
 	/*
 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
@@ -1773,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
 static const struct platform_device_id nmk_pinctrl_id[] = {
 	{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
 	{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
+	{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
 };
 
 static struct platform_driver nmk_pinctrl_driver = {
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bc91aed..e88320f 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -6,6 +6,7 @@
 /* Package definitions */
 #define PINCTRL_NMK_STN8815	0
 #define PINCTRL_NMK_DB8500	1
+#define PINCTRL_NMK_DB8540	2
 
 /**
  * struct nmk_function - Nomadik pinctrl mux function
@@ -74,4 +75,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
 
 #endif
 
+#ifdef CONFIG_PINCTRL_DB8540
+
+void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
 #endif /* PINCTRL_PINCTRL_NOMADIK_H */
-- 
1.7.11.3



From dave.martin at linaro.org  Wed Aug  8 08:23:45 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed,  8 Aug 2012 13:23:45 +0100
Subject: [PATCH v2 REPOST 0/4] ARM: opcodes: Facilitate custom opcode
 injection 
Message-ID: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>

I stopped pushing this series because it was not clear whether it would
be immediately useful.

Since it looks again like this series might be useful to some people
(KVM and Xen guys in particular), it seems worth reposting.  I've
rebased it and done some simple build testing.  It looks like it is
still working OK for ARM and Thumb in LE and BE8 configurations. 


Changes since v2:

 * Rebased againt v3.6-rc1 for repost.  No other changes.

Changes since v1:

 * This update contains minor typo fixes and extra clarification
   in the commit messages.  There are no functional changes.

Thanks to Nico for his review.


Original cover letter:

Since my "uniform assembler" series had some problems and did not
meet with widespread agreement, this can't be used as a basis for a
mechanism to safely inject custom instruction opcodes (which was my
immediate reason for writing those patchse).

This series follows a more conventional approach to achieve the
goal for safe opcode injection across all kernel endianness and
instruction set configurations.

I have made best efforts to verify that these patches do the right
thing for big-endian configurations, but review/testing from people
who are actively working with big-endian targets would be
appreciated.  There's no code in the kernel using these macros yet,
but you can experiment with the __HVC() macro added by the final
patch.  If this disassembles correctly in vmlinux (see below), then
the macros should be safe for your configuration.


Note that for BE8 targets, you _will_ get weird-looking instruction
data in your .o files:  because the ".inst" family of assembler
directives is relatively new I use data directives instead.  This
means that the data for those directives has to be pre-swapped by
the opcode injection macros, whereas _instruction_ data should get
byteswapped by the linker in the final link (with ld --be8).  Using
with older assembler versions.

To check correctness, you should therefore review the final linker
output (vmlinux) if you want to be certain what the final
instruction stream looks like.  You may need to strip data mapping
symbols (strip -N'$d') from vmlinux in order for the injected
instructions to be disassembled properly -- note that this has no
effect on the run-time meaning of the image.

For BE32 the situation is simpler again, because like LE, BE32 uses
the same endianness for data and instructions.


Dave Martin (4):
  ARM: opcodes: Don't define the thumb32 byteswapping macros for BE32
  ARM: opcodes: Make opcode byteswapping macros assembly-compatible
  ARM: opcodes: Add helpers for emitting custom opcodes
  ARM: opcodes: Opcode definitions for the Virtualization Extensions

 arch/arm/include/asm/opcodes-virt.h |   29 ++++++
 arch/arm/include/asm/opcodes.h      |  181 ++++++++++++++++++++++++++++++++---
 2 files changed, 195 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

-- 
1.7.4.1



From dave.martin at linaro.org  Wed Aug  8 08:23:46 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed,  8 Aug 2012 13:23:46 +0100
Subject: [PATCH v2 REPOST 1/4] ARM: opcodes: Don't define the thumb32
 byteswapping macros for BE32
In-Reply-To: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
References: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1344428629-12787-2-git-send-email-dave.martin@linaro.org>

The existing __mem_to_opcode_thumb32() is incorrect for BE32
platforms.  However, these don't support Thumb-2 kernels, so this
option is not so relevant for those platforms anyway.

This operation is complicated by the lack of unaligned memory
access support prior to ARMv6.

Rather than provide a "working" macro which will probably won't get
used (or worse, will get misused), this patch removes the macro for
BE32 kernels.  People manipulating Thumb opcodes prior to ARMv6
should almost certainly be splitting these operations into
halfwords anyway, using __opcode_thumb32_{first,second,compose}()
and the 16-bit opcode transformations.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48de..6bf54f9 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -49,18 +49,31 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 #include <linux/swab.h>
 
 #ifdef CONFIG_CPU_ENDIAN_BE8
+
 #define __opcode_to_mem_arm(x) swab32(x)
 #define __opcode_to_mem_thumb16(x) swab16(x)
 #define __opcode_to_mem_thumb32(x) swahb32(x)
-#else
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __opcode_to_mem_arm(x) ((u32)(x))
 #define __opcode_to_mem_thumb16(x) ((u16)(x))
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
 #define __opcode_to_mem_thumb32(x) swahw32(x)
 #endif
 
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 
 /* Operations specific to Thumb opcodes */
 
-- 
1.7.4.1



From dave.martin at linaro.org  Wed Aug  8 08:23:47 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed,  8 Aug 2012 13:23:47 +0100
Subject: [PATCH v2 REPOST 2/4] ARM: opcodes: Make opcode byteswapping macros
 assembly-compatible
In-Reply-To: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
References: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1344428629-12787-3-git-send-email-dave.martin@linaro.org>

Most of the existing macros don't work with assembler, due to the
use of type casts and C functions from <linux/swab.h>.

This patch abstracts out those operations and provides simple
explicit versions for use in assembly code.

__opcode_is_thumb32() and __opcode_is_thumb16() are also converted
to do bitmask-based testing to avoid confusion if these are used in
assembly code (the assembler typically treats all arithmetic values
as signed).

These changes avoid the need for the compiler to pre-evaluate
constant expressions used to generate opcodes.  By ensuring that
the forms of these expressions can be evaluated directly by the
assembler, we can just stringify the expressions directly into the
asm during the preprocessing pass.  The alternative approach
(passing the evaluated expression via an inline asm "i" constraint)
gets painful because the contents of the asm and the constraints
must be kept in sync.  This makes the resulting macros awkward to
use.

Retaining the C forms of the macros allows more efficient code to
be generated when opcodes are generated programmatically at run-
time, but there is no way to embed run-time-generated opcodes in
asm() blocks.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   97 +++++++++++++++++++++++++++++++++------
 1 files changed, 82 insertions(+), 15 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 6bf54f9..f57e417 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 
 
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
  * Opcode byteswap helpers
  *
  * These macros help with converting instructions between a canonical integer
@@ -41,30 +68,58 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
  * represent any valid Thumb-2 instruction.  For this range,
  * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
  */
+#ifdef __ASSEMBLY__
 
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
 
 #include <linux/types.h>
 #include <linux/swab.h>
 
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
 #ifdef CONFIG_CPU_ENDIAN_BE8
 
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
 
 #else /* ! CONFIG_CPU_ENDIAN_BE8 */
 
-#define __opcode_to_mem_arm(x) ((u32)(x))
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
 #ifndef CONFIG_CPU_ENDIAN_BE32
 /*
  * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
  * work in all cases, due to alignment constraints.  For now, a correct
  * version is not provided for BE32.
  */
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
 
 #endif /* ! CONFIG_CPU_ENDIAN_BE8 */
@@ -78,15 +133,27 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 /* Operations specific to Thumb opcodes */
 
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
 
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
-#define __opcode_thumb32_compose(first, second) \
-	(((u32)(u16)(first) << 16) | (u32)(u16)(second))
-
-#endif /* __ASSEMBLY__ */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
 
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Wed Aug  8 08:23:48 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed,  8 Aug 2012 13:23:48 +0100
Subject: [PATCH v2 REPOST 3/4] ARM: opcodes: Add helpers for emitting custom
 opcodes
In-Reply-To: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
References: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1344428629-12787-4-git-send-email-dave.martin@linaro.org>

This patch adds some __inst_() macros for injecting custom opcodes
in assembler (both inline and in .S files).  They should make it
easier and cleaner to get things right in little-/big-
endian/ARM/Thumb-2 kernels without a lot of #ifdefs.

This pure-preprocessor approach is preferred over the alternative
method of wedging extra assembler directives into the assembler
input using top-level asm() blocks, since there is no way to
guarantee that the compiler won't reorder those with respect to
each other or with respect to non-toplevel asm() blocks, unless
-fno-toplevel-reorder is passed (which is in itself somewhat
undesirable because it defeats some potential optimisations).

Currently <asm/unified.h> _does_ silently rely on the compiler not
reordering at the top level, but it seems better to avoid adding
extra code which depends on this if the same result can be achieved
in another way.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   69 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index f57e417..f7937e1 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -156,4 +156,73 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
 )
 
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Wed Aug  8 08:23:49 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed,  8 Aug 2012 13:23:49 +0100
Subject: [PATCH v2 REPOST 4/4] ARM: opcodes: Opcode definitions for the
 Virtualization Extensions
In-Reply-To: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
References: <1344428629-12787-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1344428629-12787-5-git-send-email-dave.martin@linaro.org>

For now, this patch just adds a definition for the HVC instruction.
More can be added here later, as needed.

Now that we have a real example of how to use the opcode injection
macros properly, this patch also adds a cross-reference from the
explanation in opcodes.h (since without an example, figuring out
how to use the macros is not that easy).

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes-virt.h |   29 +++++++++++++++++++++++++++++
 arch/arm/include/asm/opcodes.h      |    2 ++
 2 files changed, 31 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 0000000..b85665a
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,29 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index f7937e1..74e211a 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -193,6 +193,8 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * specify the ARM and Thumb alternatives at the same time.  This ensures
  * that the correct opcode gets emitted depending on the instruction set
  * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
  */
 #include <linux/stringify.h>
 
-- 
1.7.4.1



From grinberg at compulab.co.il  Wed Aug  8 08:24:36 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 08 Aug 2012 15:24:36 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <50225A84.5010008@compulab.co.il>

Hi Peter,

Thank you very much for the patch series.
I probably will have some time to look into it more deeply on the next week.
Currently, only a small comment, please see below.

On 08/08/12 12:54, Peter Ujfalusi wrote:
> These boards have similar audio setup and they can all use the same driver
> for audio support if it is enabled in the kernel config.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> ---
>  arch/arm/mach-omap2/board-cm-t35.c      |    1 +
>  arch/arm/mach-omap2/board-devkit8000.c  |    1 +
>  arch/arm/mach-omap2/board-igep0020.c    |    1 +
>  arch/arm/mach-omap2/board-omap3beagle.c |    1 +
>  arch/arm/mach-omap2/board-omap3evm.c    |    1 +
>  arch/arm/mach-omap2/board-overo.c       |    1 +
>  6 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
> index 97d7190..b73fa5c 100644
> --- a/arch/arm/mach-omap2/board-cm-t35.c
> +++ b/arch/arm/mach-omap2/board-cm-t35.c
> @@ -731,6 +731,7 @@ static void __init cm_t3x_common_init(void)
>  	cm_t35_init_ethernet();
>  	cm_t35_init_led();
>  	cm_t35_init_display();
> +	omap_twl4030_audio_init("overo", 26000000);

Can the card_name here be "cm-t3x" ?

[...]


-- 
Regards,
Igor.


From peter.ujfalusi at ti.com  Wed Aug  8 08:29:41 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 15:29:41 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <50225A84.5010008@compulab.co.il>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
 <50225A84.5010008@compulab.co.il>
Message-ID: <50225BB5.3000407@ti.com>

Hi Igor,

On 08/08/2012 03:24 PM, Igor Grinberg wrote:
>> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
>> index 97d7190..b73fa5c 100644
>> --- a/arch/arm/mach-omap2/board-cm-t35.c
>> +++ b/arch/arm/mach-omap2/board-cm-t35.c
>> @@ -731,6 +731,7 @@ static void __init cm_t3x_common_init(void)
>>  	cm_t35_init_ethernet();
>>  	cm_t35_init_led();
>>  	cm_t35_init_display();
>> +	omap_twl4030_audio_init("overo", 26000000);
> 
> Can the card_name here be "cm-t3x" ?

I have used the "overo" as card name here since what I gathered is that cm-t35
used the sound/soc/omap/overo.c machine driver for audio support.
If the card name is changing your existing user space might get confused by
the card name change.
But sure, I can change the card name to "cm-t3x" if it is better for you.

-- 
P?ter


From prabhakar.lad at ti.com  Wed Aug  8 08:30:18 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:00:18 +0530
Subject: [PATCH 0/2] Replace the obsolete preset API by timings API
Message-ID: <1344429020-27616-1-git-send-email-prabhakar.lad@ti.com>

This first patch replaces the obsolete preset API by timings
API for davinci VPBE, appropriate chnages in machine file for
dm644x in which VPBE is enabled. And the second patch adds support for 
timings API for ths7303 driver. Sending them as s series 
since VPBE uses the ths7303 driver.

Hans Verkuil (1):
  dm644x: replace the obsolete preset API by the timings API.

Manjunath Hadli (1):
  ths7303: enable THS7303 for HD modes

 arch/arm/mach-davinci/board-dm644x-evm.c   |   15 ++--
 arch/arm/mach-davinci/dm644x.c             |   17 +---
 drivers/media/video/davinci/vpbe.c         |  110 ++++++++++++----------------
 drivers/media/video/davinci/vpbe_display.c |   60 +++++++--------
 drivers/media/video/davinci/vpbe_venc.c    |   25 +++---
 drivers/media/video/ths7303.c              |  107 +++++++++++++++++++++++----
 include/media/davinci/vpbe.h               |   14 ++--
 include/media/davinci/vpbe_types.h         |    8 +--
 include/media/davinci/vpbe_venc.h          |    2 +-
 9 files changed, 202 insertions(+), 156 deletions(-)



From prabhakar.lad at ti.com  Wed Aug  8 08:30:19 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:00:19 +0530
Subject: [PATCH 1/2] dm644x: replace the obsolete preset API by the timings
 API.
In-Reply-To: <1344429020-27616-1-git-send-email-prabhakar.lad@ti.com>
References: <1344429020-27616-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344429020-27616-2-git-send-email-prabhakar.lad@ti.com>

From: Hans Verkuil <hans.verkuil at cisco.com>

Signed-off-by: Hans Verkuil <hans.verkuil at cisco.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
---
 arch/arm/mach-davinci/board-dm644x-evm.c   |   15 ++--
 arch/arm/mach-davinci/dm644x.c             |   17 +---
 drivers/media/video/davinci/vpbe.c         |  110 ++++++++++++----------------
 drivers/media/video/davinci/vpbe_display.c |   60 +++++++--------
 drivers/media/video/davinci/vpbe_venc.c    |   25 +++---
 include/media/davinci/vpbe.h               |   14 ++--
 include/media/davinci/vpbe_types.h         |    8 +--
 include/media/davinci/vpbe_venc.h          |    2 +-
 8 files changed, 111 insertions(+), 140 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d34ed55..3baf56d 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -23,6 +23,7 @@
 #include <linux/phy.h>
 #include <linux/clk.h>
 #include <linux/videodev2.h>
+#include <linux/v4l2-dv-timings.h>
 #include <linux/export.h>
 
 #include <media/tvp514x.h>
@@ -620,7 +621,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
 	{
 		.name		= "ntsc",
 		.timings_type	= VPBE_ENC_STD,
-		.timings	= {V4L2_STD_525_60},
+		.std_id		= V4L2_STD_525_60,
 		.interlaced	= 1,
 		.xres		= 720,
 		.yres		= 480,
@@ -632,7 +633,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
 	{
 		.name		= "pal",
 		.timings_type	= VPBE_ENC_STD,
-		.timings	= {V4L2_STD_625_50},
+		.std_id		= V4L2_STD_625_50,
 		.interlaced	= 1,
 		.xres		= 720,
 		.yres		= 576,
@@ -647,8 +648,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
 static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
 	{
 		.name		= "480p59_94",
-		.timings_type	= VPBE_ENC_DV_PRESET,
-		.timings	= {V4L2_DV_480P59_94},
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_720X480P59_94,
 		.interlaced	= 0,
 		.xres		= 720,
 		.yres		= 480,
@@ -659,8 +660,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
 	},
 	{
 		.name		= "576p50",
-		.timings_type	= VPBE_ENC_DV_PRESET,
-		.timings	= {V4L2_DV_576P50},
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_720X576P50,
 		.interlaced	= 0,
 		.xres		= 720,
 		.yres		= 576,
@@ -698,7 +699,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = {
 			.index		= 1,
 			.name		= "Component",
 			.type		= V4L2_OUTPUT_TYPE_ANALOG,
-			.capabilities	= V4L2_OUT_CAP_PRESETS,
+			.capabilities	= V4L2_OUT_CAP_CUSTOM_TIMINGS,
 		},
 		.subdev_name	= VPBE_VENC_SUBDEV_NAME,
 		.default_mode	= "480p59_94",
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..79d2880 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -701,7 +701,7 @@ static struct resource dm644x_venc_resources[] = {
 #define DM644X_VPSS_DACCLKEN                  BIT(4)
 
 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
-				   unsigned int mode)
+				   unsigned int pclock)
 {
 	int ret = 0;
 	u32 v = DM644X_VPSS_VENCLKEN;
@@ -711,27 +711,18 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
 		v |= DM644X_VPSS_DACCLKEN;
 		writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
 		break;
-	case VPBE_ENC_DV_PRESET:
-		switch (mode) {
-		case V4L2_DV_480P59_94:
-		case V4L2_DV_576P50:
+	case VPBE_ENC_CUSTOM_TIMINGS:
+		if (pclock <= 27000000) {
 			v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
 			     DM644X_VPSS_DACCLKEN;
 			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
-			break;
-		case V4L2_DV_720P60:
-		case V4L2_DV_1080I60:
-		case V4L2_DV_1080P30:
+		} else {
 			/*
 			 * For HD, use external clock source since
 			 * HD requires higher clock rate
 			 */
 			v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
 			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
-			break;
-		default:
-			ret = -EINVAL;
-			break;
 		}
 		break;
 	default:
diff --git a/drivers/media/video/davinci/vpbe.c b/drivers/media/video/davinci/vpbe.c
index c4a82a1..bc27b2a 100644
--- a/drivers/media/video/davinci/vpbe.c
+++ b/drivers/media/video/davinci/vpbe.c
@@ -174,26 +174,6 @@ static int vpbe_get_current_mode_info(struct vpbe_device *vpbe_dev,
 	return 0;
 }
 
-static int vpbe_get_dv_preset_info(struct vpbe_device *vpbe_dev,
-				   unsigned int dv_preset)
-{
-	struct vpbe_config *cfg = vpbe_dev->cfg;
-	struct vpbe_enc_mode_info var;
-	int curr_output = vpbe_dev->current_out_index;
-	int i;
-
-	for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
-		var = cfg->outputs[curr_output].modes[i];
-		if ((var.timings_type & VPBE_ENC_DV_PRESET) &&
-		  (var.timings.dv_preset == dv_preset)) {
-			vpbe_dev->current_timings = var;
-			return 0;
-		}
-	}
-
-	return -EINVAL;
-}
-
 /* Get std by std id */
 static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
 			     v4l2_std_id std_id)
@@ -206,7 +186,7 @@ static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
 	for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
 		var = cfg->outputs[curr_output].modes[i];
 		if ((var.timings_type & VPBE_ENC_STD) &&
-		  (var.timings.std_id & std_id)) {
+		  (var.std_id & std_id)) {
 			vpbe_dev->current_timings = var;
 			return 0;
 		}
@@ -344,38 +324,42 @@ static unsigned int vpbe_get_output(struct vpbe_device *vpbe_dev)
 }
 
 /**
- * vpbe_s_dv_preset - Set the given preset timings in the encoder
+ * vpbe_s_dv_timings - Set the given preset timings in the encoder
  *
- * Sets the preset if supported by the current encoder. Return the status.
+ * Sets the timings if supported by the current encoder. Return the status.
  * 0 - success & -EINVAL on error
  */
-static int vpbe_s_dv_preset(struct vpbe_device *vpbe_dev,
-		     struct v4l2_dv_preset *dv_preset)
+static int vpbe_s_dv_timings(struct vpbe_device *vpbe_dev,
+		     struct v4l2_dv_timings *dv_timings)
 {
 	struct vpbe_config *cfg = vpbe_dev->cfg;
 	int out_index = vpbe_dev->current_out_index;
+	struct vpbe_output *output = &cfg->outputs[out_index];
 	int sd_index = vpbe_dev->current_sd_index;
-	int ret;
+	int ret, i;
 
 
 	if (!(cfg->outputs[out_index].output.capabilities &
-	    V4L2_OUT_CAP_PRESETS))
+	    V4L2_OUT_CAP_CUSTOM_TIMINGS))
 		return -EINVAL;
 
-	ret = vpbe_get_dv_preset_info(vpbe_dev, dv_preset->preset);
-
-	if (ret)
-		return ret;
-
+	for (i = 0; i < output->num_modes; i++) {
+		if (output->modes[i].timings_type == VPBE_ENC_CUSTOM_TIMINGS &&
+		    !memcmp(&output->modes[i].dv_timings,
+				dv_timings, sizeof(*dv_timings)))
+			break;
+	}
+	if (i >= output->num_modes)
+		return -EINVAL;
+	vpbe_dev->current_timings = output->modes[i];
 	mutex_lock(&vpbe_dev->lock);
 
-
 	ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
-					s_dv_preset, dv_preset);
+					s_dv_timings, dv_timings);
 	if (!ret && (vpbe_dev->amp != NULL)) {
 		/* Call amplifier subdevice */
 		ret = v4l2_subdev_call(vpbe_dev->amp, video,
-				s_dv_preset, dv_preset);
+				s_dv_timings, dv_timings);
 	}
 	/* set the lcd controller output for the given mode */
 	if (!ret) {
@@ -392,17 +376,17 @@ static int vpbe_s_dv_preset(struct vpbe_device *vpbe_dev,
 }
 
 /**
- * vpbe_g_dv_preset - Get the preset in the current encoder
+ * vpbe_g_dv_timings - Get the timings in the current encoder
  *
- * Get the preset in the current encoder. Return the status. 0 - success
+ * Get the timings in the current encoder. Return the status. 0 - success
  * -EINVAL on error
  */
-static int vpbe_g_dv_preset(struct vpbe_device *vpbe_dev,
-		     struct v4l2_dv_preset *dv_preset)
+static int vpbe_g_dv_timings(struct vpbe_device *vpbe_dev,
+		     struct v4l2_dv_timings *dv_timings)
 {
 	if (vpbe_dev->current_timings.timings_type &
-	  VPBE_ENC_DV_PRESET) {
-		dv_preset->preset = vpbe_dev->current_timings.timings.dv_preset;
+	  VPBE_ENC_CUSTOM_TIMINGS) {
+		*dv_timings = vpbe_dev->current_timings.dv_timings;
 		return 0;
 	}
 
@@ -410,13 +394,13 @@ static int vpbe_g_dv_preset(struct vpbe_device *vpbe_dev,
 }
 
 /**
- * vpbe_enum_dv_presets - Enumerate the dv presets in the current encoder
+ * vpbe_enum_dv_timings - Enumerate the dv timings in the current encoder
  *
- * Get the preset in the current encoder. Return the status. 0 - success
+ * Get the timings in the current encoder. Return the status. 0 - success
  * -EINVAL on error
  */
-static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
-			 struct v4l2_dv_enum_preset *preset_info)
+static int vpbe_enum_dv_timings(struct vpbe_device *vpbe_dev,
+			 struct v4l2_enum_dv_timings *timings)
 {
 	struct vpbe_config *cfg = vpbe_dev->cfg;
 	int out_index = vpbe_dev->current_out_index;
@@ -424,12 +408,12 @@ static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
 	int j = 0;
 	int i;
 
-	if (!(output->output.capabilities & V4L2_OUT_CAP_PRESETS))
+	if (!(output->output.capabilities & V4L2_OUT_CAP_CUSTOM_TIMINGS))
 		return -EINVAL;
 
 	for (i = 0; i < output->num_modes; i++) {
-		if (output->modes[i].timings_type == VPBE_ENC_DV_PRESET) {
-			if (j == preset_info->index)
+		if (output->modes[i].timings_type == VPBE_ENC_CUSTOM_TIMINGS) {
+			if (j == timings->index)
 				break;
 			j++;
 		}
@@ -437,9 +421,8 @@ static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
 
 	if (i == output->num_modes)
 		return -EINVAL;
-
-	return v4l_fill_dv_preset_info(output->modes[i].timings.dv_preset,
-					preset_info);
+	timings->timings = output->modes[i].dv_timings;
+	return 0;
 }
 
 /**
@@ -489,10 +472,10 @@ static int vpbe_s_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
  */
 static int vpbe_g_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
 {
-	struct vpbe_enc_mode_info cur_timings = vpbe_dev->current_timings;
+	struct vpbe_enc_mode_info *cur_timings = &vpbe_dev->current_timings;
 
-	if (cur_timings.timings_type & VPBE_ENC_STD) {
-		*std_id = cur_timings.timings.std_id;
+	if (cur_timings->timings_type & VPBE_ENC_STD) {
+		*std_id = cur_timings->std_id;
 		return 0;
 	}
 
@@ -511,7 +494,7 @@ static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
 {
 	struct vpbe_enc_mode_info *preset_mode = NULL;
 	struct vpbe_config *cfg = vpbe_dev->cfg;
-	struct v4l2_dv_preset dv_preset;
+	struct v4l2_dv_timings dv_timings;
 	struct osd_state *osd_device;
 	int out_index = vpbe_dev->current_out_index;
 	int ret = 0;
@@ -530,11 +513,12 @@ static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
 			 */
 			if (preset_mode->timings_type & VPBE_ENC_STD)
 				return vpbe_s_std(vpbe_dev,
-						 &preset_mode->timings.std_id);
-			if (preset_mode->timings_type & VPBE_ENC_DV_PRESET) {
-				dv_preset.preset =
-					preset_mode->timings.dv_preset;
-				return vpbe_s_dv_preset(vpbe_dev, &dv_preset);
+						 &preset_mode->std_id);
+			if (preset_mode->timings_type &
+						VPBE_ENC_CUSTOM_TIMINGS) {
+				dv_timings =
+					preset_mode->dv_timings;
+				return vpbe_s_dv_timings(vpbe_dev, &dv_timings);
 			}
 		}
 	}
@@ -810,9 +794,9 @@ static struct vpbe_device_ops vpbe_dev_ops = {
 	.enum_outputs = vpbe_enum_outputs,
 	.set_output = vpbe_set_output,
 	.get_output = vpbe_get_output,
-	.s_dv_preset = vpbe_s_dv_preset,
-	.g_dv_preset = vpbe_g_dv_preset,
-	.enum_dv_presets = vpbe_enum_dv_presets,
+	.s_dv_timings = vpbe_s_dv_timings,
+	.g_dv_timings = vpbe_g_dv_timings,
+	.enum_dv_timings = vpbe_enum_dv_timings,
 	.s_std = vpbe_s_std,
 	.g_std = vpbe_g_std,
 	.initialize = vpbe_initialize,
diff --git a/drivers/media/video/davinci/vpbe_display.c b/drivers/media/video/davinci/vpbe_display.c
index 6fe7034..2fbf3bc 100644
--- a/drivers/media/video/davinci/vpbe_display.c
+++ b/drivers/media/video/davinci/vpbe_display.c
@@ -393,7 +393,7 @@ vpbe_disp_calculate_scale_factor(struct vpbe_display *disp_dev,
 	int h_scale;
 	int v_scale;
 
-	v4l2_std_id standard_id = vpbe_dev->current_timings.timings.std_id;
+	v4l2_std_id standard_id = vpbe_dev->current_timings.std_id;
 
 	/*
 	 * Application initially set the image format. Current display
@@ -943,7 +943,7 @@ static int vpbe_display_g_std(struct file *file, void *priv,
 
 	/* Get the standard from the current encoder */
 	if (vpbe_dev->current_timings.timings_type & VPBE_ENC_STD) {
-		*std_id = vpbe_dev->current_timings.timings.std_id;
+		*std_id = vpbe_dev->current_timings.std_id;
 		return 0;
 	}
 
@@ -1029,29 +1029,29 @@ static int vpbe_display_g_output(struct file *file, void *priv,
 }
 
 /**
- * vpbe_display_enum_dv_presets - Enumerate the dv presets
+ * vpbe_display_enum_dv_timings - Enumerate the dv timings
  *
- * enum the preset in the current encoder. Return the status. 0 - success
+ * enum the timings in the current encoder. Return the status. 0 - success
  * -EINVAL on error
  */
 static int
-vpbe_display_enum_dv_presets(struct file *file, void *priv,
-			struct v4l2_dv_enum_preset *preset)
+vpbe_display_enum_dv_timings(struct file *file, void *priv,
+			struct v4l2_enum_dv_timings *timings)
 {
 	struct vpbe_fh *fh = priv;
 	struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
 	int ret;
 
-	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_PRESETS\n");
+	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_TIMINGS\n");
 
 	/* Enumerate outputs */
-	if (NULL == vpbe_dev->ops.enum_dv_presets)
+	if (NULL == vpbe_dev->ops.enum_dv_timings)
 		return -EINVAL;
 
-	ret = vpbe_dev->ops.enum_dv_presets(vpbe_dev, preset);
+	ret = vpbe_dev->ops.enum_dv_timings(vpbe_dev, timings);
 	if (ret) {
 		v4l2_err(&vpbe_dev->v4l2_dev,
-			"Failed to enumerate dv presets info\n");
+			"Failed to enumerate dv timings info\n");
 		return -EINVAL;
 	}
 
@@ -1059,21 +1059,21 @@ vpbe_display_enum_dv_presets(struct file *file, void *priv,
 }
 
 /**
- * vpbe_display_s_dv_preset - Set the dv presets
+ * vpbe_display_s_dv_timings - Set the dv timings
  *
- * Set the preset in the current encoder. Return the status. 0 - success
+ * Set the timings in the current encoder. Return the status. 0 - success
  * -EINVAL on error
  */
 static int
-vpbe_display_s_dv_preset(struct file *file, void *priv,
-				struct v4l2_dv_preset *preset)
+vpbe_display_s_dv_timings(struct file *file, void *priv,
+				struct v4l2_dv_timings *timings)
 {
 	struct vpbe_fh *fh = priv;
 	struct vpbe_layer *layer = fh->layer;
 	struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
 	int ret;
 
-	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_PRESETS\n");
+	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_TIMINGS\n");
 
 
 	/* If streaming is started, return error */
@@ -1083,13 +1083,13 @@ vpbe_display_s_dv_preset(struct file *file, void *priv,
 	}
 
 	/* Set the given standard in the encoder */
-	if (!vpbe_dev->ops.s_dv_preset)
+	if (!vpbe_dev->ops.s_dv_timings)
 		return -EINVAL;
 
-	ret = vpbe_dev->ops.s_dv_preset(vpbe_dev, preset);
+	ret = vpbe_dev->ops.s_dv_timings(vpbe_dev, timings);
 	if (ret) {
 		v4l2_err(&vpbe_dev->v4l2_dev,
-			"Failed to set the dv presets info\n");
+			"Failed to set the dv timings info\n");
 		return -EINVAL;
 	}
 	/* set the current norm to zero to be consistent. If STD is used
@@ -1101,26 +1101,25 @@ vpbe_display_s_dv_preset(struct file *file, void *priv,
 }
 
 /**
- * vpbe_display_g_dv_preset - Set the dv presets
+ * vpbe_display_g_dv_timings - Set the dv timings
  *
- * Get the preset in the current encoder. Return the status. 0 - success
+ * Get the timings in the current encoder. Return the status. 0 - success
  * -EINVAL on error
  */
 static int
-vpbe_display_g_dv_preset(struct file *file, void *priv,
-				struct v4l2_dv_preset *dv_preset)
+vpbe_display_g_dv_timings(struct file *file, void *priv,
+				struct v4l2_dv_timings *dv_timings)
 {
 	struct vpbe_fh *fh = priv;
 	struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
 
-	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_PRESETS\n");
+	v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_TIMINGS\n");
 
 	/* Get the given standard in the encoder */
 
 	if (vpbe_dev->current_timings.timings_type &
-				VPBE_ENC_DV_PRESET) {
-		dv_preset->preset =
-			vpbe_dev->current_timings.timings.dv_preset;
+				VPBE_ENC_CUSTOM_TIMINGS) {
+		*dv_timings = vpbe_dev->current_timings.dv_timings;
 	} else {
 		return -EINVAL;
 	}
@@ -1560,9 +1559,9 @@ static const struct v4l2_ioctl_ops vpbe_ioctl_ops = {
 	.vidioc_enum_output	 = vpbe_display_enum_output,
 	.vidioc_s_output	 = vpbe_display_s_output,
 	.vidioc_g_output	 = vpbe_display_g_output,
-	.vidioc_s_dv_preset	 = vpbe_display_s_dv_preset,
-	.vidioc_g_dv_preset	 = vpbe_display_g_dv_preset,
-	.vidioc_enum_dv_presets	 = vpbe_display_enum_dv_presets,
+	.vidioc_s_dv_timings	 = vpbe_display_s_dv_timings,
+	.vidioc_g_dv_timings	 = vpbe_display_g_dv_timings,
+	.vidioc_enum_dv_timings	 = vpbe_display_enum_dv_timings,
 #ifdef CONFIG_VIDEO_ADV_DEBUG
 	.vidioc_g_register	 = vpbe_display_g_register,
 	.vidioc_s_register	 = vpbe_display_s_register,
@@ -1630,8 +1629,7 @@ static __devinit int init_vpbe_layer(int i, struct vpbe_display *disp_dev,
 			VPBE_ENC_STD) {
 		vbd->tvnorms = (V4L2_STD_525_60 | V4L2_STD_625_50);
 		vbd->current_norm =
-			disp_dev->vpbe_dev->
-			current_timings.timings.std_id;
+			disp_dev->vpbe_dev->current_timings.std_id;
 	} else
 		vbd->current_norm = 0;
 
diff --git a/drivers/media/video/davinci/vpbe_venc.c b/drivers/media/video/davinci/vpbe_venc.c
index b21ecc8..86d47c3 100644
--- a/drivers/media/video/davinci/vpbe_venc.c
+++ b/drivers/media/video/davinci/vpbe_venc.c
@@ -298,7 +298,7 @@ static int venc_set_480p59_94(struct v4l2_subdev *sd)
 		return -EINVAL;
 
 	/* Setup clock at VPSS & VENC for SD */
-	if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_480P59_94) < 0)
+	if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 27000000) < 0)
 		return -EINVAL;
 
 	venc_enabledigitaloutput(sd, 0);
@@ -345,7 +345,7 @@ static int venc_set_576p50(struct v4l2_subdev *sd)
 	  (pdata->venc_type != VPBE_VERSION_2))
 		return -EINVAL;
 	/* Setup clock at VPSS & VENC for SD */
-	if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_576P50) < 0)
+	if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 27000000) < 0)
 		return -EINVAL;
 
 	venc_enabledigitaloutput(sd, 0);
@@ -385,7 +385,7 @@ static int venc_set_720p60_internal(struct v4l2_subdev *sd)
 	struct venc_state *venc = to_state(sd);
 	struct venc_platform_data *pdata = venc->pdata;
 
-	if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_720P60) < 0)
+	if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 74250000) < 0)
 		return -EINVAL;
 
 	venc_enabledigitaloutput(sd, 0);
@@ -413,7 +413,7 @@ static int venc_set_1080i30_internal(struct v4l2_subdev *sd)
 	struct venc_state *venc = to_state(sd);
 	struct venc_platform_data *pdata = venc->pdata;
 
-	if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_1080P30) < 0)
+	if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 74250000) < 0)
 		return -EINVAL;
 
 	venc_enabledigitaloutput(sd, 0);
@@ -446,26 +446,27 @@ static int venc_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
 	return -EINVAL;
 }
 
-static int venc_s_dv_preset(struct v4l2_subdev *sd,
-			    struct v4l2_dv_preset *dv_preset)
+static int venc_s_dv_timings(struct v4l2_subdev *sd,
+			    struct v4l2_dv_timings *dv_timings)
 {
 	struct venc_state *venc = to_state(sd);
+	u32 height = dv_timings->bt.height;
 	int ret;
 
-	v4l2_dbg(debug, 1, sd, "venc_s_dv_preset\n");
+	v4l2_dbg(debug, 1, sd, "venc_s_dv_timings\n");
 
-	if (dv_preset->preset == V4L2_DV_576P50)
+	if (height == 576)
 		return venc_set_576p50(sd);
-	else if (dv_preset->preset == V4L2_DV_480P59_94)
+	else if (height == 480)
 		return venc_set_480p59_94(sd);
-	else if ((dv_preset->preset == V4L2_DV_720P60) &&
+	else if ((height == 720) &&
 			(venc->pdata->venc_type == VPBE_VERSION_2)) {
 		/* TBD setup internal 720p mode here */
 		ret = venc_set_720p60_internal(sd);
 		/* for DM365 VPBE, there is DAC inside */
 		vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
 		return ret;
-	} else if ((dv_preset->preset == V4L2_DV_1080I30) &&
+	} else if ((height == 1080) &&
 		(venc->pdata->venc_type == VPBE_VERSION_2)) {
 		/* TBD setup internal 1080i mode here */
 		ret = venc_set_1080i30_internal(sd);
@@ -518,7 +519,7 @@ static const struct v4l2_subdev_core_ops venc_core_ops = {
 static const struct v4l2_subdev_video_ops venc_video_ops = {
 	.s_routing = venc_s_routing,
 	.s_std_output = venc_s_std_output,
-	.s_dv_preset = venc_s_dv_preset,
+	.s_dv_timings = venc_s_dv_timings,
 };
 
 static const struct v4l2_subdev_ops venc_ops = {
diff --git a/include/media/davinci/vpbe.h b/include/media/davinci/vpbe.h
index 8bc1b3c..a7ca488 100644
--- a/include/media/davinci/vpbe.h
+++ b/include/media/davinci/vpbe.h
@@ -35,7 +35,7 @@ struct osd_config_info {
 struct vpbe_output {
 	struct v4l2_output output;
 	/*
-	 * If output capabilities include dv_preset, list supported presets
+	 * If output capabilities include dv_timings, list supported timings
 	 * below
 	 */
 	char *subdev_name;
@@ -120,16 +120,16 @@ struct vpbe_device_ops {
 	unsigned int (*get_output)(struct vpbe_device *vpbe_dev);
 
 	/* Set DV preset at current output */
-	int (*s_dv_preset)(struct vpbe_device *vpbe_dev,
-			   struct v4l2_dv_preset *dv_preset);
+	int (*s_dv_timings)(struct vpbe_device *vpbe_dev,
+			   struct v4l2_dv_timings *dv_timings);
 
 	/* Get DV presets supported at the output */
-	int (*g_dv_preset)(struct vpbe_device *vpbe_dev,
-			   struct v4l2_dv_preset *dv_preset);
+	int (*g_dv_timings)(struct vpbe_device *vpbe_dev,
+			   struct v4l2_dv_timings *dv_timings);
 
 	/* Enumerate the DV Presets supported at the output */
-	int (*enum_dv_presets)(struct vpbe_device *vpbe_dev,
-			       struct v4l2_dv_enum_preset *preset_info);
+	int (*enum_dv_timings)(struct vpbe_device *vpbe_dev,
+			       struct v4l2_enum_dv_timings *timings_info);
 
 	/* Set std at the output */
 	int (*s_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id);
diff --git a/include/media/davinci/vpbe_types.h b/include/media/davinci/vpbe_types.h
index 727f551..9b85396 100644
--- a/include/media/davinci/vpbe_types.h
+++ b/include/media/davinci/vpbe_types.h
@@ -32,11 +32,6 @@ enum vpbe_enc_timings_type {
 	VPBE_ENC_TIMINGS_INVALID = 0x8,
 };
 
-union vpbe_timings {
-	v4l2_std_id std_id;
-	unsigned int dv_preset;
-};
-
 /*
  * struct vpbe_enc_mode_info
  * @name: ptr to name string of the standard, "NTSC", "PAL" etc
@@ -73,7 +68,8 @@ union vpbe_timings {
 struct vpbe_enc_mode_info {
 	unsigned char *name;
 	enum vpbe_enc_timings_type timings_type;
-	union vpbe_timings timings;
+	v4l2_std_id std_id;
+	struct v4l2_dv_timings dv_timings;
 	unsigned int interlaced;
 	unsigned int xres;
 	unsigned int yres;
diff --git a/include/media/davinci/vpbe_venc.h b/include/media/davinci/vpbe_venc.h
index 6b57334..cc78c2e 100644
--- a/include/media/davinci/vpbe_venc.h
+++ b/include/media/davinci/vpbe_venc.h
@@ -32,7 +32,7 @@ struct venc_platform_data {
 	int (*setup_pinmux)(enum v4l2_mbus_pixelcode if_type,
 			    int field);
 	int (*setup_clock)(enum vpbe_enc_timings_type type,
-			   unsigned int mode);
+			   unsigned int pixclock);
 	int (*setup_if_config)(enum v4l2_mbus_pixelcode pixcode);
 	/* Number of LCD outputs supported */
 	int num_lcd_outputs;
-- 
1.7.0.4



From prabhakar.lad at ti.com  Wed Aug  8 08:30:20 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:00:20 +0530
Subject: [PATCH 2/2] ths7303: enable THS7303 for HD modes
In-Reply-To: <1344429020-27616-1-git-send-email-prabhakar.lad@ti.com>
References: <1344429020-27616-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344429020-27616-3-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

add filter settings for high def modes like 1080i,
1080p,720p and others and implementing dv_timings.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
---
 drivers/media/video/ths7303.c |  107 ++++++++++++++++++++++++++++++++++------
 1 files changed, 91 insertions(+), 16 deletions(-)

diff --git a/drivers/media/video/ths7303.c b/drivers/media/video/ths7303.c
index e5c0eed..d997583 100644
--- a/drivers/media/video/ths7303.c
+++ b/drivers/media/video/ths7303.c
@@ -28,6 +28,18 @@
 #include <media/v4l2-subdev.h>
 #include <media/v4l2-chip-ident.h>
 
+#define THS7303_CHANNEL_1	1
+#define THS7303_CHANNEL_2	2
+#define THS7303_CHANNEL_3	3
+
+enum ths7303_filter_mode {
+	THS7303_FILTER_MODE_480I_576I,
+	THS7303_FILTER_MODE_480P_576P,
+	THS7303_FILTER_MODE_720P_1080I,
+	THS7303_FILTER_MODE_1080P,
+	THS7303_FILTER_MODE_DISABLE
+};
+
 MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
 MODULE_AUTHOR("Chaithrika U S");
 MODULE_LICENSE("GPL");
@@ -37,35 +49,97 @@ module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "Debug level 0-1");
 
 /* following function is used to set ths7303 */
-static int ths7303_setvalue(struct v4l2_subdev *sd, v4l2_std_id std)
+int ths7303_setval(struct v4l2_subdev *sd, enum ths7303_filter_mode mode)
 {
+	u8 input_bias_chroma = 3;
+	u8 input_bias_luma = 3;
+	int disable = 0;
 	int err = 0;
-	u8 val;
-	struct i2c_client *client;
+	u8 val = 0;
+	u8 temp;
 
-	client = v4l2_get_subdevdata(sd);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
 
-	if (std & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
-		val = 0x02;
-		v4l2_dbg(1, debug, sd, "setting value for SDTV format\n");
-	} else {
-		val = 0x00;
-		v4l2_dbg(1, debug, sd, "disabling all channels\n");
+	if (!client)
+		return -EINVAL;
+
+
+	switch (mode) {
+	case THS7303_FILTER_MODE_1080P:
+		val = (3 << 6);
+		val |= (3 << 3);
+		break;
+	case THS7303_FILTER_MODE_720P_1080I:
+		val = (2 << 6);
+		val |= (2 << 3);
+		break;
+	case THS7303_FILTER_MODE_480P_576P:
+		val = (1 << 6);
+		val |= (1 << 3);
+		break;
+	case THS7303_FILTER_MODE_480I_576I:
+		break;
+	case THS7303_FILTER_MODE_DISABLE:
+		pr_info("mode disabled\n");
+		/* disable all channels */
+		disable = 1;
+	default:
+		/* disable all channels */
+		disable = 1;
 	}
+	/* Setup channel 2 - Luma - Green */
+	temp = val;
+	if (!disable)
+		val |= input_bias_luma;
+	err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_2, val);
+	if (err)
+		goto out;
 
-	err |= i2c_smbus_write_byte_data(client, 0x01, val);
-	err |= i2c_smbus_write_byte_data(client, 0x02, val);
-	err |= i2c_smbus_write_byte_data(client, 0x03, val);
+	/* setup two chroma channels */
+	if (!disable)
+		temp |= input_bias_chroma;
 
+	err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_1, temp);
 	if (err)
-		v4l2_err(sd, "write failed\n");
+		goto out;
 
+	err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_3, temp);
+	if (err)
+		goto out;
+	return err;
+out:
+	pr_info("write byte data failed\n");
 	return err;
 }
 
 static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
 {
-	return ths7303_setvalue(sd, norm);
+	if (norm & (V4L2_STD_ALL & ~V4L2_STD_SECAM))
+		return ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
+	else
+		return ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
+}
+
+/* for setting filter for HD output */
+static int ths7303_s_dv_timings(struct v4l2_subdev *sd,
+			       struct v4l2_dv_timings *dv_timings)
+{
+	u32 height = dv_timings->bt.height;
+	int interlaced = dv_timings->bt.interlaced;
+	int res = 0;
+
+	if (height == 1080 && !interlaced)
+		res = ths7303_setval(sd, THS7303_FILTER_MODE_1080P);
+	else if ((height == 720 && !interlaced) ||
+			(height == 1080 && interlaced))
+		res = ths7303_setval(sd, THS7303_FILTER_MODE_720P_1080I);
+	else if ((height == 480 || height == 576) && !interlaced)
+		res = ths7303_setval(sd, THS7303_FILTER_MODE_480P_576P);
+	else
+		/* disable all channels */
+		res = ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
+
+	return res;
 }
 
 static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
@@ -78,6 +152,7 @@ static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
 
 static const struct v4l2_subdev_video_ops ths7303_video_ops = {
 	.s_std_output	= ths7303_s_std_output,
+	.s_dv_timings    = ths7303_s_dv_timings,
 };
 
 static const struct v4l2_subdev_core_ops ths7303_core_ops = {
@@ -107,7 +182,7 @@ static int ths7303_probe(struct i2c_client *client,
 
 	v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
 
-	return ths7303_setvalue(sd, std_id);
+	return ths7303_s_std_output(sd, std_id);
 }
 
 static int ths7303_remove(struct i2c_client *client)
-- 
1.7.0.4



From linus.walleij at linaro.org  Wed Aug  8 08:38:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 14:38:23 +0200
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <20120807153112.GF10719@gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120806153503.GH10524@gmail.com>
 <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
 <20120807153112.GF10719@gmail.com>
Message-ID: <CACRpkdZj2LqFF_i6f3M2uzUkhG6og5n2cTzUgqRZA1_NmhWBNA@mail.gmail.com>

On Tue, Aug 7, 2012 at 5:31 PM, Lee Jones <lee.jones at linaro.org> wrote:

> From: Lee Jones <lee.jones at linaro.org>
> Date: Tue, 7 Aug 2012 12:27:24 +0100
> Subject: [PATCH 1/1 v3] i2c: Add default configuration into the Nomadik I2C
>  driver.

This has some bad whitespace damage, and the subject should
be "i2c/nomadik:"

> Cc: linux-i2c at vger.kernel.org
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Double sign-off.

Unless Wolfram volunteers to fix this up I suggest you
fix it nocheinmal und senden einer neues version.

Ihre,
Linus Walleij


From arnd at arndb.de  Wed Aug  8 08:39:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 12:39:16 +0000
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <502252A6.4090409@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <50223428.6030506@codethink.co.uk> <502252A6.4090409@codethink.co.uk>
Message-ID: <201208081239.16778.arnd@arndb.de>

On Wednesday 08 August 2012, Ian Molton wrote:
> The SMI / PHY stuff should look very similar, so I'm happy with something
> like:
> 
> mdio at 2000 {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 device_type = "mdio";
>                 compatible = "marvell,mv643xx-mdio";
>                 phy0: ethernet-phy at 0 {
>                         device_type = "ethernet-phy";
>                         compatible = "marvell,whatever";
>                         interrupts = <76>;
>                         interrupt-parent = <&mpic>;
>                         reg = <0 32>;          // Auto probed phy addr
>                 };
> 
>                 phy1: ethernet-phy at 3 {
>                         device_type = "ethernet-phy";
>                         compatible = "marvell,whatever";
>                         interrupts = <77>;
>                         interrupt-parent = <&mpic>;
>                         reg = <3 1>;            // specified phy addr
>                 };
> 
>                 ... and so on.
> }
> 
> Where we can use the reg parameter to allow auto-probing, by
> specifying a size of 32 (32 phy addrs max).

I don't understand the auto-probed phy address. What is the purpose of that?

If possible, I think we should keep using #size-cells=<0>, which would
make the method you describe impossible. It might still work if you just
leave out the "reg" property for that node.

I also don't understand how the phy driver would locate ethernet-phy at 0
on the bus if it does not know the address.

> The ethernet driver itself is more complicated:
> 
> We have the following considerations:
> 
> * we have one MDIO bus, typically, shared between all the MACs / PHYs.
> * each ethernet device can multiple ports (up to three), each with its
>   own MAC/PHY.
> * MAC <-> PHY mapping can be specified, probed (ugh!) or a (gah!)
>   mix of the two.
> * existing D-T users, albeit not well documented / code complete.
> * some port address ranges overlap (MIB counters, MCAST / UNICAST
>   tables, etc.
> 
> The existing ethernet-group idea only works because the current
> platform-device based driver doesnt really do proper resource
> management, and thus the MAC registers are actually mapped by
> the MDIO driver.
> 
> I don't think that preserving this bad behaviour is a good idea, which
> leaves us with two choices:
> 
> 1) My preferred solution - allow each device to specify up to three
> interrupts, MACs, and PHYs. This is clean in that it doesnt require
> multiply instantiating a driver three times over the same address
> space.
> 
> ethernet at 2400 {
>                 compatible = "marvell,mv643xx-eth";
>                 reg = <0x2400 0x1c00>
>                 interrupt_parent = <&mpic>;
>                 ports = <3>;
>                 interrupts = <4>, <5>, <6>;
>                 phys = <&phy0>, <&phy1>, <&phy2>;
> };
> 
> ethernet at 6400 {
>                 compatible = "marvell,mv643xx-eth";
>                 reg = <0x6400 0x1c00>
>                 interrupt_parent = <&mpic>;
>                 ports = <1>;
>                 interrupts = <4>;
>                 phys = <&phy3>;
> };
> 
> Note that the address is 2400, not 2000 - since this driver no longer
> would share its address range with the MDIO driver.
> 
> This method would require a small amount of rework in the driver to
> set up <n> ports, rather than just one.

This looks quite nice, but it is still very much incompatible with the
existing binding. Obviously we can abandon an existing binding and
introduce a second one for the same hardware, but that should not
be taken lightly.

> 2) Create some kind of pseudo-ethernet group device that manages
> all the work for some sort of lightweight ethernet device, one per
> port. This can never be done cleanly since the port address ranges
> overlap:
> 
> pseudo_eth at 2400 {
>         #address-cells = <1>;
>         #size-cells = <0>;
>         compatible = "marvell,mv643xx-shared-eth"
>         reg = <0x2400 0x1c00>;
> 
>         ethernet at 0 {
>                 compatible = "marvell,mv643xx-port";
>                 interrupts = <4>;
>                 interrupt_parent = <&mpic>;
>                 phy = <&phy0>;
>         };
> 
>         ethernet at 1 {
>                 compatible = "marvell,mv643xx-port";
>                 interrupts = <5>;
>                 interrupt_parent = <&mpic>;
>                 phy = <&phy1>;
>         };
> 
>         ethernet at 2 {
>                 compatible = "marvell,mv643xx-port";
>                 interrupts = <6>;
>                 interrupt_parent = <&mpic>;
>                 phy = <&phy2>;
>         };
> }
> pseudo_eth at 6400 {
>         #address-cells = <1>;
>         #size-cells = <0>;
>         compatible = "marvell,mv643xx-shared-eth"
>         reg = <0x6400 0x1c00>;
> 
>         ethernet at 0 {
>                 compatible = "marvell,mv643xx-port";
>                 interrupts = <4>;
>                 interrupt_parent = <&mpic>;
>                 phy = <&phy3>;
>         };
> };

This looks almost compatible with the existing binding, which is
good. I would in fact recommend to use the actual "compatible"
strings from the binding. More generally speaking, you should not
use wildcards in those strings anyway, so always use
"marvell,mv64360-eth" instead of "marvell,mv64x60-eth" or
"marvell,mv643xx-eth". If you have multiple chips that are
completely compatible, put use the identifier for the older one.

I don't fully understand your concern with the overlapping
registers, mostly because I still don't know all the combinations
that are actually valid here. Let me try to say what I understood
so far, and you can correct me if that's wrong:

* A system can have multiple instances of an mv64360 ethernet
block, with a register area of 0x2000 bytes.
* Each such block can have three MACs and three PHYs.
* The first 0x400 bytes in the register space control the three
  PHYs and the remaining registers control the MACs.
* While this is meant to be used in a way that you assign
  the each of the three PHYs to one of the MACs, this is not
  always done, and sometimes you use a different PHY (?), or
  one from a different instance of the mv64360 ethernet block
  on the same SoC?.

	Arnd


From dave.martin at linaro.org  Wed Aug  8 08:41:11 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed, 8 Aug 2012 13:41:11 +0100
Subject: [PATCH v2 02/23] xen/arm: hypercalls
In-Reply-To: <1344263246-28036-2-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-2-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <20120808124111.GB2134@linaro.org>

On Mon, Aug 06, 2012 at 03:27:05PM +0100, Stefano Stabellini wrote:
> Use r12 to pass the hypercall number to the hypervisor.
> 
> We need a register to pass the hypercall number because we might not
> know it at compile time and HVC only takes an immediate argument.
> 
> Among the available registers r12 seems to be the best choice because it
> is defined as "intra-procedure call scratch register".
> 
> Use the ISS to pass an hypervisor specific tag.
> 
> Changes in v2:
> - define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
> at the moment is unused;
> - use ldm instead of pop;
> - fix up comments.
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> ---
>  arch/arm/include/asm/xen/hypercall.h |   50 ++++++++++++++++
>  arch/arm/xen/Makefile                |    2 +-
>  arch/arm/xen/hypercall.S             |  106 ++++++++++++++++++++++++++++++++++
>  3 files changed, 157 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/include/asm/xen/hypercall.h
>  create mode 100644 arch/arm/xen/hypercall.S

[...]

> diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
> new file mode 100644
> index 0000000..074f5ed
> --- /dev/null
> +++ b/arch/arm/xen/hypercall.S
> @@ -0,0 +1,106 @@
> +/******************************************************************************
> + * hypercall.S
> + *
> + * Xen hypercall wrappers
> + *
> + * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation; or, when distributed
> + * separately from the Linux kernel or incorporated into other
> + * software packages, subject to the following license:
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this source file (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use, copy, modify,
> + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> + * and to permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +/*
> + * The Xen hypercall calling convention is very similar to the ARM
> + * procedure calling convention: the first paramter is passed in r0, the
> + * second in r1, the third in r2 and the fourth in r3. Considering that
> + * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
> + * in r4, differently from the procedure calling convention of using the
> + * stack for that case.
> + *
> + * The hypercall number is passed in r12.
> + *
> + * The return value is in r0.
> + *
> + * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
> + * hypercall tag.
> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> +#include <xen/interface/xen.h>
> +
> +
> +/* HVC 0xEA1 */
> +#ifdef CONFIG_THUMB2_KERNEL
> +#define xen_hvc .word 0xf7e08ea1
> +#else
> +#define xen_hvc .word 0xe140ea71
> +#endif

Consider using my opcode injection helpers patch for this (see
separate repost: [PATCH v2 REPOST 0/4] ARM: opcodes: Facilitate custom
opcode injection), assuming that nobody objects to it.  This should mean
that the right opcodes get generated when building a kernel for a big-
endian target for example.

I believe the __HVC(imm) macro which I put in <asm/opcodes-virt.h> as an
example should do what you need in this case.

> +
> +#define HYPERCALL_SIMPLE(hypercall)		\
> +ENTRY(HYPERVISOR_##hypercall)			\
> +	mov r12, #__HYPERVISOR_##hypercall;	\
> +	xen_hvc;							\
> +	mov pc, lr;							\
> +ENDPROC(HYPERVISOR_##hypercall)
> +
> +#define HYPERCALL0 HYPERCALL_SIMPLE
> +#define HYPERCALL1 HYPERCALL_SIMPLE
> +#define HYPERCALL2 HYPERCALL_SIMPLE
> +#define HYPERCALL3 HYPERCALL_SIMPLE
> +#define HYPERCALL4 HYPERCALL_SIMPLE
> +
> +#define HYPERCALL5(hypercall)			\
> +ENTRY(HYPERVISOR_##hypercall)			\
> +	stmdb sp!, {r4}						\
> +	ldr r4, [sp, #4]					\
> +	mov r12, #__HYPERVISOR_##hypercall;	\
> +	xen_hvc								\
> +	ldm sp!, {r4}						\
> +	mov pc, lr							\
> +ENDPROC(HYPERVISOR_##hypercall)
> +
> +                .text
> +
> +HYPERCALL2(xen_version);
> +HYPERCALL3(console_io);
> +HYPERCALL3(grant_table_op);
> +HYPERCALL2(sched_op);
> +HYPERCALL2(event_channel_op);
> +HYPERCALL2(hvm_op);
> +HYPERCALL2(memory_op);
> +HYPERCALL2(physdev_op);
> +
> +ENTRY(privcmd_call)
> +	stmdb sp!, {r4}
> +	mov r12, r0
> +	mov r0, r1
> +	mov r1, r2
> +	mov r2, r3
> +	ldr r3, [sp, #8]
> +	ldr r4, [sp, #4]
> +	xen_hvc
> +	ldm sp!, {r4}
> +	mov pc, lr

Note that the preferred entry/exit sequences in such cases are:

	stmfd	sp!, {r4,lr}
	...
	ldmfd	sp!, {r4,pc}

...but it works either way.  I would bother to change it unless you
have other changes to make too.


Cheers
---Dave



From peter.ujfalusi at ti.com  Wed Aug  8 08:43:29 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 15:43:29 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <5022529D.3090406@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <5022529D.3090406@ti.com>
Message-ID: <50225EF1.4010203@ti.com>

Hi Benoit,

On 08/08/2012 02:50 PM, Benoit Cousson wrote:
>> +Required properties:
>> +- compatible : must be "ti,twl4030-audio"
>> +- ti,audio_mclk: Master clock frequency used on the board. Supported
>> +	         frequencies: 19200000, 26000000 and 38400000
> 
> Since you care about the frequency only you can use the generic
> attribute: clock-frequency (in your example, I2C is using it).

I see, I'll use replace the property with clock-frequency.

> That being said, since we do have the clock binding now, maybe we should
> create a clock provider at board level for the sys_clk and thus you will
> just have to create a phandle to it in your audio description.
> 
> In theory OMAP and other components will thus have to use that sys_clock
> reference as well.

And in the driver I would need to do for example:
clkp = clk_get(NULL, "audio_mclk");
clk_rate = clk_get_rate(clkp);
clk_put(clkp);

to get the frequency in this way?
Note that the twl4030-audio stack itself does not handle clocks at the moment
since the clock needed for the audio module is always running (HFCLKIN ->
HFCLKOUT -> AUDIO_MCLK (USB_MCLK)). All of this is within twl4030. Do we
really want to model this?

-- 
P?ter


From prabhakar.lad at ti.com  Wed Aug  8 08:50:57 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:20:57 +0530
Subject: [PATCH v4 0/2] ARM: davinci: add support for dm365 vpbe display
Message-ID: <1344430259-23968-1-git-send-email-prabhakar.lad@ti.com>

This patch series enables VPBE display driver on DM365. 

This patch series is dependent on this patches posted
http://www.spinics.net/lists/arm-kernel/msg188234.html

Changes for v4:
1: Replaced the obsolete preset API by timings API.

Changes for v3: 
1: Removed VPSS clock alias for master and slave which was 
   sent for VPSS driver. since this patch was dependent on 
   patch[1]. I will revist this patch once MC(captrure driver) 
   goes into mainline. 
[1] http://www.spinics.net/lists/linux-media/msg50562.html

Changes for v2: 
1: Added VPSS clock so that capture and display 
   can work independent.

Manjunath Hadli (2):
  ARM: davinci: dm365: add support for v4l2 video display
  ARM: davinci: dm365 EVM: add support for VPBE display

 arch/arm/mach-davinci/board-dm365-evm.c |  179 +++++++++++++++++++++++++++-
 arch/arm/mach-davinci/davinci.h         |    2 +-
 arch/arm/mach-davinci/dm365.c           |  203 +++++++++++++++++++++++++++++--
 3 files changed, 371 insertions(+), 13 deletions(-)



From prabhakar.lad at ti.com  Wed Aug  8 08:50:59 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:20:59 +0530
Subject: [PATCH v4 2/2] ARM: davinci: dm365 EVM: add support for VPBE display
In-Reply-To: <1344430259-23968-1-git-send-email-prabhakar.lad@ti.com>
References: <1344430259-23968-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344430259-23968-3-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

add support for V4L2 video display to DM365 EVM.
Support for SD and ED modes is provided, along with Composite
and Component outputs.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
---
 arch/arm/mach-davinci/board-dm365-evm.c |  177 ++++++++++++++++++++++++++++++-
 1 files changed, 176 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index ac1f20d..52422f9 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -27,6 +27,7 @@
 #include <linux/input.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
+#include <linux/v4l2-dv-timings.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -374,6 +375,180 @@ static struct vpfe_config vpfe_cfg = {
 	.ccdc = "ISIF",
 };
 
+#define VENC_STD_ALL	(V4L2_STD_NTSC | V4L2_STD_PAL)
+
+/* venc standards timings */
+static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
+	{
+		.name		= "ntsc",
+		.timings_type	= VPBE_ENC_STD,
+		.std_id		= V4L2_STD_525_60,
+		.interlaced	= 1,
+		.xres		= 720,
+		.yres		= 480,
+		.aspect		= {11, 10},
+		.fps		= {30000, 1001},
+		.left_margin	= 0x79,
+		.right_margin	= 0,
+		.upper_margin	= 0x10,
+		.lower_margin	= 0,
+		.hsync_len	= 0,
+		.vsync_len	= 0,
+		.flags		= 0,
+	},
+	{
+		.name		= "pal",
+		.timings_type	= VPBE_ENC_STD,
+		.std_id		= V4L2_STD_625_50,
+		.interlaced	= 1,
+		.xres		= 720,
+		.yres		= 576,
+		.aspect		= {54, 59},
+		.fps		= {25, 1},
+		.left_margin	= 0x7E,
+		.right_margin	= 0,
+		.upper_margin	= 0x16,
+		.lower_margin	= 0,
+		.hsync_len	= 0,
+		.vsync_len	= 0,
+		.flags		= 0,
+	},
+};
+
+/* venc dv timings */
+static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
+	{
+		.name		= "480p59_94",
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_720X480P59_94,
+		.interlaced	= 0,
+		.xres		= 720,
+		.yres		= 480,
+		.aspect		= {1, 1},
+		.fps		= {5994, 100},
+		.left_margin	= 0x8F,
+		.right_margin	= 0,
+		.upper_margin	= 0x2D,
+		.lower_margin	= 0,
+		.hsync_len	= 0,
+		.vsync_len	= 0,
+		.flags		= 0,
+	},
+	{
+		.name		= "576p50",
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_720X576P50,
+		.interlaced	= 0,
+		.xres		= 720,
+		.yres		= 576,
+		.aspect		= {1, 1},
+		.fps		= {50, 1},
+		.left_margin	= 0x8C,
+		.right_margin	= 0,
+		.upper_margin	= 0x36,
+		.lower_margin	= 0,
+		.hsync_len	= 0,
+		.vsync_len	= 0,
+		.flags		= 0,
+	},
+	{
+		.name		= "720p60",
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_1280X720P60,
+		.interlaced	= 0,
+		.xres		= 1280,
+		.yres		= 720,
+		.aspect		= {1, 1},
+		.fps		= {60, 1},
+		.left_margin	= 0x117,
+		.right_margin	= 70,
+		.upper_margin	= 38,
+		.lower_margin	= 3,
+		.hsync_len	= 80,
+		.vsync_len	= 5,
+		.flags		= 0,
+	},
+	{
+		.name		= "1080i60",
+		.timings_type	= VPBE_ENC_CUSTOM_TIMINGS,
+		.dv_timings	= V4L2_DV_BT_CEA_1920X1080I60,
+		.interlaced	= 1,
+		.xres		= 1920,
+		.yres		= 1080,
+		.aspect		= {1, 1},
+		.fps		= {30, 1},
+		.left_margin	= 0xc9,
+		.right_margin	= 80,
+		.upper_margin	= 30,
+		.lower_margin	= 3,
+		.hsync_len	= 88,
+		.vsync_len	= 5,
+		.flags		= 0,
+	},
+};
+
+/*
+ * The outputs available from VPBE + ecnoders. Keep the
+ * the order same as that of encoders. First those from venc followed by that
+ * from encoders. Index in the outpuvpbe-t refers to index on a particular
+ * encoder.Driver uses this index to pass it to encoder when it supports more
+ * than one output. Application uses index of the array to set an output.
+ */
+static struct vpbe_output dm365evm_vpbe_outputs[] = {
+	{
+		.output		= {
+			.index		= 0,
+			.name		= "Composite",
+			.type		= V4L2_OUTPUT_TYPE_ANALOG,
+			.std		= VENC_STD_ALL,
+			.capabilities	= V4L2_OUT_CAP_STD,
+		},
+		.subdev_name	= VPBE_VENC_SUBDEV_NAME,
+		.default_mode	= "ntsc",
+		.num_modes	= ARRAY_SIZE(dm365evm_enc_std_timing),
+		.modes		= dm365evm_enc_std_timing,
+		.if_params	= V4L2_MBUS_FMT_FIXED,
+	},
+	{
+		.output		= {
+			.index		= 1,
+			.name		= "Component",
+			.type		= V4L2_OUTPUT_TYPE_ANALOG,
+			.capabilities	= V4L2_OUT_CAP_CUSTOM_TIMINGS,
+		},
+		.subdev_name	= VPBE_VENC_SUBDEV_NAME,
+		.default_mode	= "480p59_94",
+		.num_modes	= ARRAY_SIZE(dm365evm_enc_preset_timing),
+		.modes		= dm365evm_enc_preset_timing,
+		.if_params	= V4L2_MBUS_FMT_FIXED,
+	},
+};
+
+/*
+ * Amplifiers on the board
+ */
+static struct amp_config_info vpbe_amp = {
+	.module_name	= "ths7303",
+	.is_i2c		= 1,
+	.board_info	= {
+		I2C_BOARD_INFO("ths7303", 0x2c)
+	}
+};
+
+static struct vpbe_config dm365evm_display_cfg = {
+	.module_name	= "dm365-vpbe-display",
+	.i2c_adapter_id	= 1,
+	.amp		= &vpbe_amp,
+	.osd		= {
+		.module_name	= VPBE_OSD_SUBDEV_NAME,
+	},
+	.venc		= {
+		.module_name	= VPBE_VENC_SUBDEV_NAME,
+	},
+	.num_outputs	= ARRAY_SIZE(dm365evm_vpbe_outputs),
+	.outputs	= dm365evm_vpbe_outputs,
+};
+
 static void __init evm_init_i2c(void)
 {
 	davinci_init_i2c(&i2c_pdata);
@@ -595,7 +770,7 @@ static __init void dm365_evm_init(void)
 
 	davinci_setup_mmc(0, &dm365evm_mmc_config);
 
-	dm365_init_video(&vpfe_cfg, NULL);
+	dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
 
 	/* maybe setup mmc1/etc ... _after_ mmc0 */
 	evm_init_cpld();
-- 
1.7.0.4



From prabhakar.lad at ti.com  Wed Aug  8 08:50:58 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:20:58 +0530
Subject: [PATCH v4 1/2] ARM: davinci: dm365: add support for v4l2 video display
In-Reply-To: <1344430259-23968-1-git-send-email-prabhakar.lad@ti.com>
References: <1344430259-23968-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344430259-23968-2-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

Create platform devices for various video modules like venc,osd,
vpbe and v4l2 driver for dm365.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
---
 arch/arm/mach-davinci/board-dm365-evm.c |    4 +-
 arch/arm/mach-davinci/davinci.h         |    2 +-
 arch/arm/mach-davinci/dm365.c           |  203 +++++++++++++++++++++++++++++--
 3 files changed, 196 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 688a9c5..ac1f20d 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -564,8 +564,6 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm365_evm_map_io(void)
 {
-	/* setup input configuration for VPFE input devices */
-	dm365_set_vpfe_config(&vpfe_cfg);
 	dm365_init();
 }
 
@@ -597,6 +595,8 @@ static __init void dm365_evm_init(void)
 
 	davinci_setup_mmc(0, &dm365evm_mmc_config);
 
+	dm365_init_video(&vpfe_cfg, NULL);
+
 	/* maybe setup mmc1/etc ... _after_ mmc0 */
 	evm_init_cpld();
 
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6..94d867f 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -84,7 +84,7 @@ void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void __init dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
 			const struct spi_board_info *info, unsigned len);
-void dm365_set_vpfe_config(struct vpfe_config *cfg);
+int __init dm365_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM644x function declarations */
 void __init dm644x_init(void);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49d..7c0cc66 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1232,6 +1232,199 @@ static struct platform_device dm365_isif_dev = {
 	},
 };
 
+#define DM365_OSD_REG_BASE		0x01C71C00
+
+static struct resource dm365_osd_resources[] = {
+	{
+	.start	= DM365_OSD_REG_BASE,
+	.end	= DM365_OSD_REG_BASE + 0x100,
+	.flags	= IORESOURCE_MEM,
+	},
+};
+
+static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
+
+static struct osd_platform_data dm365_osd_data = {
+	.vpbe_type	= VPBE_VERSION_2,
+};
+
+static struct platform_device dm365_osd_dev = {
+	.name		= VPBE_OSD_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm365_osd_resources),
+	.resource	= dm365_osd_resources,
+	.dev		= {
+		.dma_mask		= &dm365_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &dm365_osd_data,
+	},
+};
+
+#define DM365_VENC_REG_BASE		0x01C71E00
+#define DM3XX_VDAC_CONFIG		0x01C4002C
+
+static struct resource dm365_venc_resources[] = {
+	{
+		.start	= IRQ_VENCINT,
+		.end	= IRQ_VENCINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+	/* venc registers io space */
+	{
+		.start	= DM365_VENC_REG_BASE,
+		.end	= DM365_VENC_REG_BASE + 0x180,
+		.flags	= IORESOURCE_MEM,
+	},
+	/* vdaccfg registers io space */
+	{
+		.start	= DM3XX_VDAC_CONFIG,
+		.end	= DM3XX_VDAC_CONFIG + 4,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource dm365_v4l2_disp_resources[] = {
+	{
+		.start	= IRQ_VENCINT,
+		.end	= IRQ_VENCINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+	/* venc registers io space */
+	{
+		.start	= DM365_VENC_REG_BASE,
+		.end	= DM365_VENC_REG_BASE + 0x180,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+			    int field)
+{
+	int ret = 0;
+
+	switch (if_type) {
+	case V4L2_MBUS_FMT_SGRBG8_1X8:
+		davinci_cfg_reg(DM365_VOUT_FIELD_G81);
+		davinci_cfg_reg(DM365_VOUT_COUTL_EN);
+		davinci_cfg_reg(DM365_VOUT_COUTH_EN);
+		break;
+	case V4L2_MBUS_FMT_YUYV10_1X20:
+		if (field)
+			davinci_cfg_reg(DM365_VOUT_FIELD);
+		else
+			davinci_cfg_reg(DM365_VOUT_FIELD_G81);
+		davinci_cfg_reg(DM365_VOUT_COUTL_EN);
+		davinci_cfg_reg(DM365_VOUT_COUTH_EN);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+#define DM365_VPSS_VENCCLKEN_ENABLE		0x8
+#define DM365_VPSS_DACCLKEN_ENABLE		0x10
+#define DM365_VPSS_PLLC2SYSCLK5			0x20
+#define DM365_VPSS_CLK_CTRL_ADDR		0x44
+
+static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
+				  unsigned int pclock)
+{
+	void __iomem *vpss_clkctl_reg;
+	int ret = 0;
+
+	vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(DM365_VPSS_CLK_CTRL_ADDR);
+
+	switch (type) {
+	case VPBE_ENC_STD:
+		vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
+		vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
+		__raw_writel(DM365_VPSS_VENCCLKEN_ENABLE +
+			DM365_VPSS_DACCLKEN_ENABLE, vpss_clkctl_reg);
+		break;
+	case VPBE_ENC_CUSTOM_TIMINGS:
+		if (pclock <= 27000000) {
+			vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
+			vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
+			__raw_writel(DM365_VPSS_VENCCLKEN_ENABLE +
+				DM365_VPSS_DACCLKEN_ENABLE, vpss_clkctl_reg);
+		} else {
+			/* set sysclk4 to output 74.25 MHz from pll1 */
+			__raw_writel(DM365_VPSS_PLLC2SYSCLK5 +
+				DM365_VPSS_DACCLKEN_ENABLE +
+				DM365_VPSS_VENCCLKEN_ENABLE, vpss_clkctl_reg);
+		}
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static struct platform_device dm365_vpbe_display = {
+	.name		= "vpbe-v4l2",
+	.id		= -1,
+	.num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
+	.resource	= dm365_v4l2_disp_resources,
+	.dev		= {
+		.dma_mask		= &dm365_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+struct venc_platform_data dm365_venc_pdata = {
+	.venc_type	= VPBE_VERSION_2,
+	.setup_pinmux	= dm365_vpbe_setup_pinmux,
+	.setup_clock	= dm365_venc_setup_clock,
+};
+
+static struct platform_device dm365_venc_dev = {
+	.name		= VPBE_VENC_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm365_venc_resources),
+	.resource	= dm365_venc_resources,
+	.dev		= {
+		.dma_mask		= &dm365_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= (void *)&dm365_venc_pdata,
+	},
+};
+
+static struct platform_device dm365_vpbe_dev = {
+	.name		= "vpbe_controller",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &dm365_video_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
+				struct vpbe_config *vpbe_cfg)
+{
+	if (vpfe_cfg || vpbe_cfg)
+		platform_device_register(&dm365_vpss_device);
+
+	if (vpfe_cfg) {
+		vpfe_capture_dev.dev.platform_data = vpfe_cfg;
+		platform_device_register(&dm365_isif_dev);
+		platform_device_register(&vpfe_capture_dev);
+		/* Add isif clock alias */
+		clk_add_alias("master", dm365_isif_dev.name, "vpss_master",
+					NULL);
+	}
+	if (vpbe_cfg) {
+		dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
+		platform_device_register(&dm365_osd_dev);
+		platform_device_register(&dm365_venc_dev);
+		platform_device_register(&dm365_vpbe_dev);
+		platform_device_register(&dm365_vpbe_display);
+	}
+
+	return 0;
+}
+
 static int __init dm365_init_devices(void)
 {
 	if (!cpu_is_davinci_dm365())
@@ -1245,16 +1438,6 @@ static int __init dm365_init_devices(void)
 	clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
 		      NULL, &dm365_emac_device.dev);
 
-	/* Add isif clock alias */
-	clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
-	platform_device_register(&dm365_vpss_device);
-	platform_device_register(&dm365_isif_dev);
-	platform_device_register(&vpfe_capture_dev);
 	return 0;
 }
 postcore_initcall(dm365_init_devices);
-
-void dm365_set_vpfe_config(struct vpfe_config *cfg)
-{
-       vpfe_capture_dev.dev.platform_data = cfg;
-}
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Wed Aug  8 08:52:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 13:52:52 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <5022529D.3090406@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <5022529D.3090406@ti.com>
Message-ID: <20120808125252.GR16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 01:50:53PM +0200, Benoit Cousson wrote:

> That being said, since we do have the clock binding now, maybe we should
> create a clock provider at board level for the sys_clk and thus you will
> just have to create a phandle to it in your audio description.

Yes, we should be doing this.


From arnd at arndb.de  Wed Aug  8 08:54:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:50 +0200
Subject: [PATCH 3/6] ARM: sa1100: include asm/io.h in hackkit leds code
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-4-git-send-email-arnd@arndb.de>

The sa1100 definition of the io_p2v macro has changed in v3.6, and this one
file stopped working because of that.

Without this patch, building hackkit_defconfig results in:

arch/arm/mach-sa1100/leds-hackkit.c: In function 'hackkit_leds_event':
arch/arm/mach-sa1100/leds-hackkit.c:39:4: error: implicit declaration of function 'IOMEM' [-Werror=implicit-function-declaration]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-sa1100/leds-hackkit.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
index 6a23524..9c79674 100644
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ b/arch/arm/mach-sa1100/leds-hackkit.c
@@ -13,6 +13,7 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
+#include <asm/io.h>
 
 #include "leds.h"
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:53 +0200
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-7-git-send-email-arnd@arndb.de>

It is not currently possible to build the gpmi-nand driver without
also building the mxs-dma driver. Clarify this Kconfig and enable
both in the defconfig file so we can build it again with both enabled.

drivers/built-in.o: In function `gpmi_dma_filter':
clk-fixed-factor.c:(.text+0xafc18): undefined reference to `mxs_dma_is_apbh'
make[1]: *** [vmlinux] Error 1
make: *** [sub-make] Error 2

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Sascha Hauer <kernel at pengutronix.de>
---
 arch/arm/configs/imx_v6_v7_defconfig |    1 +
 drivers/mtd/nand/Kconfig             |    2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f725b96..3c9f32f 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -192,6 +192,7 @@ CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
 CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 31bb7e5..8ca4176 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -480,7 +480,7 @@ config MTD_NAND_NANDSIM
 
 config MTD_NAND_GPMI_NAND
         bool "GPMI NAND Flash Controller driver"
-        depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q)
+        depends on MTD_NAND && MXS_DMA
         help
 	 Enables NAND Flash support for IMX23 or IMX28.
 	 The GPMI controller is very powerful, with the help of BCH
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:51 +0200
Subject: [PATCH 4/6] ARM: s3c24xx: use new PWM driver
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-5-git-send-email-arnd@arndb.de>

The samsung PWM driver has moved to the new PWM subsystem, which
changed the Kconfig symbol for that driver, but the rx1950 and
gta02 boards still uses the old one.

Without this patch, building s3c2410_defconfig results in:

arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_lcd_power':
arch/arm/mach-s3c24xx/mach-rx1950.c:430: undefined reference to `pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:431: undefined reference to `pwm_disable'
arch/arm/mach-s3c24xx/mach-rx1950.c:437: undefined reference to `pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:438: undefined reference to `pwm_enable'
arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_exit':
arch/arm/mach-s3c24xx/mach-rx1950.c:504: undefined reference to `pwm_free'
arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_init':
arch/arm/mach-s3c24xx/mach-rx1950.c:487: undefined reference to `pwm_request'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-s3c24xx/Kconfig |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e249611..422133a 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -483,7 +483,8 @@ config MACH_NEO1973_GTA02
 	select I2C
 	select POWER_SUPPLY
 	select MACH_NEO1973
-	select S3C2410_PWM
+	select PWM
+	select PWM_SAMSUNG
 	select S3C_DEV_USB_HOST
 	help
 	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
@@ -493,7 +494,8 @@ config MACH_RX1950
 	select S3C24XX_DCLK
 	select PM_H1940 if PM
 	select I2C
-	select S3C2410_PWM
+	select PWM
+	select PWM_SAMSUNG
 	select S3C_DEV_NAND
 	select S3C2410_IOTIMING if S3C2440_CPUFREQ
 	select S3C2440_XTAL_16934400
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:48 +0200
Subject: [PATCH 1/6] ARM: pxa: remove irq_to_gpio from ezx-pcap driver
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-2-git-send-email-arnd@arndb.de>

The irq_to_gpio function was removed from the pxa platform
in linux-3.2, and this driver has been broken since.

There is actually no in-tree user of this driver that adds
this platform device, but the driver can and does get enabled
on some platforms.

Without this patch, building ezx_defconfig results in:

drivers/mfd/ezx-pcap.c: In function 'pcap_isr_work':
drivers/mfd/ezx-pcap.c:205:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: stable at vger.kernel.org (v3.2+)
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Daniel Ribeiro <drwyrm at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 drivers/mfd/ezx-pcap.c       |    2 +-
 include/linux/mfd/ezx-pcap.h |    1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
index 43a76c4..db662e2 100644
--- a/drivers/mfd/ezx-pcap.c
+++ b/drivers/mfd/ezx-pcap.c
@@ -202,7 +202,7 @@ static void pcap_isr_work(struct work_struct *work)
 		}
 		local_irq_enable();
 		ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
-	} while (gpio_get_value(irq_to_gpio(pcap->spi->irq)));
+	} while (gpio_get_value(pdata->gpio));
 }
 
 static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index 40c37216..32a1b5c 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -16,6 +16,7 @@ struct pcap_subdev {
 struct pcap_platform_data {
 	unsigned int irq_base;
 	unsigned int config;
+	int gpio;
 	void (*init) (void *);	/* board specific init */
 	int num_subdevs;
 	struct pcap_subdev *subdevs;
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:47 +0200
Subject: [PATCH 0/6] ARM: defconfig build errors
Message-ID: <1344430493-5304-1-git-send-email-arnd@arndb.de>

I'm dusting off my defconfig warning fixes. This is the most important
bunch as these are actual build failures that happen in one of the
defconfigs. I've put these into the "fixes" branch of the arm-soc
tree already and will send them out for -r2 unless I hear objections.

Please take a look.

	Arnd

Cc: Daniel Mack <zonque at gmail.com>
Cc: Daniel Ribeiro <drwyrm at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Shawn Guo <shawn.guo at linaro.org>

Arnd Bergmann (6):
  ARM: pxa: remove irq_to_gpio from ezx-pcap driver
  ARM: pxa remove irq_to_gpio from eeti_ts driver
  ARM: sa1100: include asm/io.h in hackkit leds code
  ARM: s3c24xx: use new PWM driver
  ARM: integrator: include <linux/export.h
  ARM: imx: gpmi-nand depends on mxs-dma

 arch/arm/configs/imx_v6_v7_defconfig |    1 +
 arch/arm/mach-integrator/core.c      |    1 +
 arch/arm/mach-pxa/raumfeld.c         |    1 +
 arch/arm/mach-s3c24xx/Kconfig        |    6 ++++--
 arch/arm/mach-sa1100/leds-hackkit.c  |    1 +
 drivers/input/touchscreen/eeti_ts.c  |    8 +++++---
 drivers/mfd/ezx-pcap.c               |    2 +-
 drivers/mtd/nand/Kconfig             |    2 +-
 include/linux/input/eeti_ts.h        |    1 +
 include/linux/mfd/ezx-pcap.h         |    1 +
 10 files changed, 17 insertions(+), 7 deletions(-)

-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:49 +0200
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-3-git-send-email-arnd@arndb.de>

The irq_to_gpio function was removed from the pxa platform
in linux-3.2, and this driver has been broken since.

Without this patch, building raumfeld_defconfig results in:

drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: stable at vger.kernel.org (v3.2+)
Cc: Daniel Mack <zonque at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-pxa/raumfeld.c        |    1 +
 drivers/input/touchscreen/eeti_ts.c |    8 +++++---
 include/linux/input/eeti_ts.h       |    1 +
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 5905ed1..9e1c4ea 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -953,6 +953,7 @@ static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
 
 static struct eeti_ts_platform_data eeti_ts_pdata = {
 	.irq_active_high = 1,
+	.gpio = GPIO_TOUCH_IRQ,
 };
 
 static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
diff --git a/drivers/input/touchscreen/eeti_ts.c b/drivers/input/touchscreen/eeti_ts.c
index 503c709..45dab18 100644
--- a/drivers/input/touchscreen/eeti_ts.c
+++ b/drivers/input/touchscreen/eeti_ts.c
@@ -48,7 +48,7 @@ struct eeti_ts_priv {
 	struct input_dev *input;
 	struct work_struct work;
 	struct mutex mutex;
-	int irq, irq_active_high;
+	int irq, gpio, irq_active_high;
 };
 
 #define EETI_TS_BITDEPTH	(11)
@@ -62,7 +62,7 @@ struct eeti_ts_priv {
 
 static inline int eeti_ts_irq_active(struct eeti_ts_priv *priv)
 {
-	return gpio_get_value(irq_to_gpio(priv->irq)) == priv->irq_active_high;
+	return gpio_get_value(priv->gpio) == priv->irq_active_high;
 }
 
 static void eeti_ts_read(struct work_struct *work)
@@ -203,8 +203,10 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
 
 	pdata = client->dev.platform_data;
 
-	if (pdata)
+	if (pdata) {
+		priv->gpio = pdata->gpio;
 		priv->irq_active_high = pdata->irq_active_high;
+	}
 
 	irq_flags = priv->irq_active_high ?
 		IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING;
diff --git a/include/linux/input/eeti_ts.h b/include/linux/input/eeti_ts.h
index f875b31..3404504 100644
--- a/include/linux/input/eeti_ts.h
+++ b/include/linux/input/eeti_ts.h
@@ -3,6 +3,7 @@
 
 struct eeti_ts_platform_data {
 	unsigned int irq_active_high;
+	unsigned int gpio;
 };
 
 #endif /* LINUX_INPUT_EETI_TS_H */
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 08:54:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 14:54:52 +0200
Subject: [PATCH 5/6] ARM: integrator: include <linux/export.h
In-Reply-To: <1344430493-5304-1-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
Message-ID: <1344430493-5304-6-git-send-email-arnd@arndb.de>

Without this patch, building integrator_defconfig results in:

arch/arm/mach-integrator/core.c:150:1: warning: data definition has no type or storage class [enabled by default]
arch/arm/mach-integrator/core.c:150:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Wimplicit-int]
arch/arm/mach-integrator/core.c:150:1: warning: parameter names (without types) in function declaration [enabled by default]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-integrator/core.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index ebf680b..3fa6c51 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-- 
1.7.10



From festevam at gmail.com  Wed Aug  8 09:01:26 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 8 Aug 2012 10:01:26 -0300
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <1344430493-5304-7-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-7-git-send-email-arnd@arndb.de>
Message-ID: <CAOMZO5CZ7mJd89cN_S0KBS74mc5qTzvrfRbmHVX3nmEakx19ow@mail.gmail.com>

Hi Arnd,

On Wed, Aug 8, 2012 at 9:54 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> It is not currently possible to build the gpmi-nand driver without
> also building the mxs-dma driver. Clarify this Kconfig and enable
> both in the defconfig file so we can build it again with both enabled.
>
> drivers/built-in.o: In function `gpmi_dma_filter':
> clk-fixed-factor.c:(.text+0xafc18): undefined reference to `mxs_dma_is_apbh'
> make[1]: *** [vmlinux] Error 1
> make: *** [sub-make] Error 2
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>

I have already sent a fix for this to the mtd list:
https://patchwork.kernel.org/patch/1236551/

Regards,

Fabio Estevam


From dirk.behme at de.bosch.com  Wed Aug  8 09:00:20 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Wed, 8 Aug 2012 15:00:20 +0200
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <1344430493-5304-7-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-7-git-send-email-arnd@arndb.de>
Message-ID: <502262E4.9020303@de.bosch.com>

On 08.08.2012 14:54, Arnd Bergmann wrote:
> It is not currently possible to build the gpmi-nand driver without
> also building the mxs-dma driver. Clarify this Kconfig and enable
> both in the defconfig file so we can build it again with both enabled.
> 
> drivers/built-in.o: In function `gpmi_dma_filter':
> clk-fixed-factor.c:(.text+0xafc18): undefined reference to `mxs_dma_is_apbh'
> make[1]: *** [vmlinux] Error 1
> make: *** [sub-make] Error 2
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>

Acked-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk

> ---
>  arch/arm/configs/imx_v6_v7_defconfig |    1 +
>  drivers/mtd/nand/Kconfig             |    2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..3c9f32f 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -192,6 +192,7 @@ CONFIG_RTC_DRV_MC13XXX=y
>  CONFIG_RTC_DRV_MXC=y
>  CONFIG_DMADEVICES=y
>  CONFIG_IMX_SDMA=y
> +CONFIG_MXS_DMA=y
>  CONFIG_COMMON_CLK_DEBUG=y
>  # CONFIG_IOMMU_SUPPORT is not set
>  CONFIG_EXT2_FS=y
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 31bb7e5..8ca4176 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -480,7 +480,7 @@ config MTD_NAND_NANDSIM
>  
>  config MTD_NAND_GPMI_NAND
>          bool "GPMI NAND Flash Controller driver"
> -        depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q)
> +        depends on MTD_NAND && MXS_DMA
>          help
>  	 Enables NAND Flash support for IMX23 or IMX28.
>  	 The GPMI controller is very powerful, with the help of BCH


From pawel.moll at arm.com  Wed Aug  8 09:06:10 2012
From: pawel.moll at arm.com (Pawel Moll)
Date: Wed, 08 Aug 2012 14:06:10 +0100
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <CACRpkdYkoeH09H6c4WEw40hpP9+oRD4pa0-yBk1L02yfao2sgg@mail.gmail.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <1344426500.2435.39.camel@hornet>	<1344426753.2435.40.camel@hornet>
 <CACRpkdYkoeH09H6c4WEw40hpP9+oRD4pa0-yBk1L02yfao2sgg@mail.gmail.com>
Message-ID: <1344431170.2435.47.camel@hornet>

On Wed, 2012-08-08 at 12:55 +0100, Linus Walleij wrote:
> On Wed, Aug 8, 2012 at 1:52 PM, Pawel Moll <pawel.moll at arm.com> wrote:
> 
> >> ------------[ cut here ]------------
> >> WARNING: at /home/pawmol01/src/kernel.org/linux/kernel/timer.c:1076 del_timer_sync+0x34/0x5c()
> >
> > Err. Ignore that. The same happens without your patch :-)
> >
> > Will try with 3.5.
> 
> Hm it boots like a charm on PB1176, what's so very different about the EB?

It's configuration difference, I guess. You may try enabling
CONFIG_LEDS_TRIGGERS (not that it makes much sense on Realview) if you
want to see the same effect :-)

It seems that a0193cbee0809d65362a0767b2d50306b145b2f5 "leds: use
led_set_brightness in led_trigger_event" causes a problem when
led_trigger_event() is called from an interrupt context. I'll let the
LEDS people know.

> Oh well. Are you maintaining RealView EB, BTW?

Not really. At least I didn't have any reason to do this so far. And the
only Realview platforms I'm really interested in are the EB models. DT
for Realview is on my todo list, but with really low priority (around
"most likely will never happen").

Anyway, after testing your change on EB model:

Acked-by: Pawel Moll <pawel.moll at arm.com>

Cheers!

Pawe?




From grinberg at compulab.co.il  Wed Aug  8 09:06:12 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 08 Aug 2012 16:06:12 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <50225BB5.3000407@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
 <50225A84.5010008@compulab.co.il> <50225BB5.3000407@ti.com>
Message-ID: <50226444.4060100@compulab.co.il>

On 08/08/12 15:29, Peter Ujfalusi wrote:
> Hi Igor,
> 
> On 08/08/2012 03:24 PM, Igor Grinberg wrote:
>>> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
>>> index 97d7190..b73fa5c 100644
>>> --- a/arch/arm/mach-omap2/board-cm-t35.c
>>> +++ b/arch/arm/mach-omap2/board-cm-t35.c
>>> @@ -731,6 +731,7 @@ static void __init cm_t3x_common_init(void)
>>>  	cm_t35_init_ethernet();
>>>  	cm_t35_init_led();
>>>  	cm_t35_init_display();
>>> +	omap_twl4030_audio_init("overo", 26000000);
>>
>> Can the card_name here be "cm-t3x" ?
> 
> I have used the "overo" as card name here since what I gathered is that cm-t35
> used the sound/soc/omap/overo.c machine driver for audio support.
> If the card name is changing your existing user space might get confused by
> the card name change.
> But sure, I can change the card name to "cm-t3x" if it is better for you.

Well, yes I know we will need to adjust the user space.
I wanted to change that for a long time and did not get to it...
Now, with your patches, it seems like the best time for doing this.

Thanks


-- 
Regards,
Igor.


From festevam at gmail.com  Wed Aug  8 09:06:16 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  8 Aug 2012 10:06:16 -0300
Subject: [PATCH] ARM: plat-mxc: Remove unused imx_ioremap
Message-ID: <1344431176-10486-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

imx_ioremap is no longer used on imx platforms, so remove it.

As the EXPORT_SYMBOL_GPL is removed, it is also safe to remove the module.h header.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/plat-mxc/system.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 1996c3e..3da78cf 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/module.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -29,9 +28,6 @@
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
 
-void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
-EXPORT_SYMBOL_GPL(imx_ioremap);
-
 static void __iomem *wdog_base;
 
 /*
-- 
1.7.1



From dirk.behme at de.bosch.com  Wed Aug  8 09:05:13 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Wed, 8 Aug 2012 15:05:13 +0200
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <CAOMZO5CZ7mJd89cN_S0KBS74mc5qTzvrfRbmHVX3nmEakx19ow@mail.gmail.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-7-git-send-email-arnd@arndb.de>
 <CAOMZO5CZ7mJd89cN_S0KBS74mc5qTzvrfRbmHVX3nmEakx19ow@mail.gmail.com>
Message-ID: <50226409.1060800@de.bosch.com>

On 08.08.2012 15:01, Fabio Estevam wrote:
> Hi Arnd,
> 
> On Wed, Aug 8, 2012 at 9:54 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> It is not currently possible to build the gpmi-nand driver without
>> also building the mxs-dma driver. Clarify this Kconfig and enable
>> both in the defconfig file so we can build it again with both enabled.
>>
>> drivers/built-in.o: In function `gpmi_dma_filter':
>> clk-fixed-factor.c:(.text+0xafc18): undefined reference to `mxs_dma_is_apbh'
>> make[1]: *** [vmlinux] Error 1
>> make: *** [sub-make] Error 2
>>
>> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>> Cc: Shawn Guo <shawn.guo at linaro.org>
>> Cc: Sascha Hauer <kernel at pengutronix.de>
> 
> I have already sent a fix for this to the mtd list:
> https://patchwork.kernel.org/patch/1236551/

Yes. But it seems it's not handled there? I'm trying since ~2 weeks to 
get something like your patch applied to get the broken mainline fixed, 
but unfortunately without success so far.

Best regards

Dirk


From lee.jones at linaro.org  Wed Aug  8 09:09:59 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 14:09:59 +0100
Subject: [PATCH 1/1 v2] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <CACRpkdZj2LqFF_i6f3M2uzUkhG6og5n2cTzUgqRZA1_NmhWBNA@mail.gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120806153503.GH10524@gmail.com>
 <CACRpkdZjbyQbht+UpXrrVGhAzGYPjb=HRZhJ+TvsEXhGeviJLA@mail.gmail.com>
 <20120807153112.GF10719@gmail.com>
 <CACRpkdZj2LqFF_i6f3M2uzUkhG6og5n2cTzUgqRZA1_NmhWBNA@mail.gmail.com>
Message-ID: <20120808130958.GC8227@gmail.com>

On Wed, Aug 08, 2012 at 02:38:23PM +0200, Linus Walleij wrote:
> On Tue, Aug 7, 2012 at 5:31 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > From: Lee Jones <lee.jones at linaro.org>
> > Date: Tue, 7 Aug 2012 12:27:24 +0100
> > Subject: [PATCH 1/1 v3] i2c: Add default configuration into the Nomadik I2C
> >  driver.
> 
> This has some bad whitespace damage, and the subject should
> be "i2c/nomadik:"

White space damage? You mean the subject line-wrap? 

`git format-patch` does that. I'll change the subject line to i2c/nomadik.

> > Cc: linux-i2c at vger.kernel.org
> > Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Double sign-off.

Hmm... this is fast becoming my nemosis patch!

> Unless Wolfram volunteers to fix this up I suggest you
> fix it nocheinmal und senden einer neues version.

That's okay, it's my error, I'll fix. 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From kgene.kim at samsung.com  Wed Aug  8 09:10:20 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 08 Aug 2012 22:10:20 +0900
Subject: [PATCH 4/6] ARM: s3c24xx: use new PWM driver
In-Reply-To: <1344430493-5304-5-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-5-git-send-email-arnd@arndb.de>
Message-ID: <0b6801cd7567$29be48b0$7d3ada10$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> The samsung PWM driver has moved to the new PWM subsystem, which
> changed the Kconfig symbol for that driver, but the rx1950 and
> gta02 boards still uses the old one.
> 
> Without this patch, building s3c2410_defconfig results in:
> 
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_lcd_power':
> arch/arm/mach-s3c24xx/mach-rx1950.c:430: undefined reference to
> `pwm_config'
> arch/arm/mach-s3c24xx/mach-rx1950.c:431: undefined reference to
> `pwm_disable'
> arch/arm/mach-s3c24xx/mach-rx1950.c:437: undefined reference to
> `pwm_config'
> arch/arm/mach-s3c24xx/mach-rx1950.c:438: undefined reference to
> `pwm_enable'
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_exit':
> arch/arm/mach-s3c24xx/mach-rx1950.c:504: undefined reference to `pwm_free'
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_init':
> arch/arm/mach-s3c24xx/mach-rx1950.c:487: undefined reference to
> `pwm_request'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/mach-s3c24xx/Kconfig |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
> index e249611..422133a 100644
> --- a/arch/arm/mach-s3c24xx/Kconfig
> +++ b/arch/arm/mach-s3c24xx/Kconfig
> @@ -483,7 +483,8 @@ config MACH_NEO1973_GTA02
>  	select I2C
>  	select POWER_SUPPLY
>  	select MACH_NEO1973
> -	select S3C2410_PWM
> +	select PWM
> +	select PWM_SAMSUNG
>  	select S3C_DEV_USB_HOST
>  	help
>  	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM
> Phone
> @@ -493,7 +494,8 @@ config MACH_RX1950
>  	select S3C24XX_DCLK
>  	select PM_H1940 if PM
>  	select I2C
> -	select S3C2410_PWM
> +	select PWM
> +	select PWM_SAMSUNG
>  	select S3C_DEV_NAND
>  	select S3C2410_IOTIMING if S3C2440_CPUFREQ
>  	select S3C2440_XTAL_16934400
> --
> 1.7.10
> 
Hi Arnd,

There is following patch for fixing it in my tree now, its reference:

https://lkml.org/lkml/2012/8/8/185

So...?

From: Tushar Behera <tushar.behera at linaro.org>
Subject: [PATCH] ARM: SAMSUNG: Fix compilation error with s3c2410_defconfig

Commit 215c29d3d0e9 ("ARM Samsung: Move s3c pwm driver to pwm framework")
moved Samsung PWM driver to drivers/pwm and the config option to select
this driver has changed.

This patch fixes following build-error with s3c2410_defconfig.

arch/arm/mach-s3c24xx/built-in.o: In function 'rx1950_lcd_power':
arch/arm/mach-s3c24xx/mach-rx1950.c:430: undefined reference to 'pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:431: undefined reference to
'pwm_disable'
arch/arm/mach-s3c24xx/mach-rx1950.c:437: undefined reference to 'pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:438: undefined reference to 'pwm_enable'
arch/arm/mach-s3c24xx/built-in.o: In function 'rx1950_backlight_exit':
arch/arm/mach-s3c24xx/mach-rx1950.c:504: undefined reference to 'pwm_free'
arch/arm/mach-s3c24xx/built-in.o: In function 'rx1950_backlight_init':
arch/arm/mach-s3c24xx/mach-rx1950.c:487: undefined reference to
'pwm_request'

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
[kgene.kim at samsung.com: re-worked as per review comments]
Acked-by: Thierry Reding <thierry.reding at avionic-design.de>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c24xx/Kconfig |    4 ++--
 arch/arm/plat-samsung/Kconfig |    2 +-
 drivers/pwm/Kconfig           |    6 ++----
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e249611..d56b0f7 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
 	select I2C
 	select POWER_SUPPLY
 	select MACH_NEO1973
-	select S3C2410_PWM
+	select S3C24XX_PWM
 	select S3C_DEV_USB_HOST
 	help
 	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM
Phone
@@ -493,7 +493,7 @@ config MACH_RX1950
 	select S3C24XX_DCLK
 	select PM_H1940 if PM
 	select I2C
-	select S3C2410_PWM
+	select S3C24XX_PWM
 	select S3C_DEV_NAND
 	select S3C2410_IOTIMING if S3C2440_CPUFREQ
 	select S3C2440_XTAL_16934400
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 7aca31c..dcdfb77 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -403,7 +403,7 @@ config S5P_DEV_USB_EHCI
 
 config S3C24XX_PWM
 	bool "PWM device support"
-	select HAVE_PWM
+	select PWM
 	help
 	  Support for exporting the PWM timer blocks via the pwm device
 	  system
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 8fc3808..c74d055 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -58,14 +58,12 @@ config PWM_PXA
 	  will be called pwm-pxa.
 
 config PWM_SAMSUNG
-	tristate "Samsung pwm support"
+	bool "Samsung PWM support"
 	depends on PLAT_SAMSUNG
+	default y
 	help
 	  Generic PWM framework driver for Samsung.
 
-	  To compile this driver as a module, choose M here: the module
-	  will be called pwm-samsung.
-
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
-- 
1.7.4.1

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From lee.jones at linaro.org  Wed Aug  8 09:11:59 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 14:11:59 +0100
Subject: [PATCH 1/1 v4] i2c: Add default configuration into the Nomadik I2C
 driver.
In-Reply-To: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20120808131158.GD8227@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Tue, 7 Aug 2012 12:27:24 +0100
Subject: [PATCH 1/1 v4] i2c/nomadik: Add default configuration into the Nomadik I2C driver

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
as already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 5e6f1ee..61b00ed 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -350,10 +350,6 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
 
 	i2c_clk = clk_get_rate(dev->clk);
 
-	/* fallback to std. mode if machine has not provided it */
-	if (dev->cfg.clk_freq == 0)
-		dev->cfg.clk_freq = 100000;
-
 	/*
 	 * The spec says, in case of std. mode the divider is
 	 * 2 whereas it is 3 for fast and fastplus mode of
@@ -911,20 +907,32 @@ static const struct i2c_algorithm nmk_i2c_algo = {
 	.functionality	= nmk_i2c_functionality
 };
 
+static struct nmk_i2c_controller u8500_i2c = {
+	/*
+	 * Slave data setup time; 250ns, 100ns, and 10ns, which
+	 * is 14, 6 and 2 respectively for a 48Mhz i2c clock.
+	 */
+	.slsu           = 0xe,
+	.tft            = 1,      /* Tx FIFO threshold */
+	.rft            = 8,      /* Rx FIFO threshold */
+	.clk_freq       = 400000, /* fast mode operation */
+	.timeout        = 200,    /* Slave response timeout(ms) */
+	.sm             = I2C_FREQ_MODE_FAST,
+};
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
-	struct nmk_i2c_controller *pdata =
-			adev->dev.platform_data;
+	struct nmk_i2c_controller *pdata = adev->dev.platform_data;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
-	if (!pdata) {
-		dev_warn(&adev->dev, "no platform data\n");
-		return -ENODEV;
-	}
+	if (!pdata)
+		/* No i2c configuration found, using the default. */
+		pdata = &u8500_i2c;
+
 	dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
 	if (!dev) {
 		dev_err(&adev->dev, "cannot allocate memory\n");
-- 
1.7.9.5


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:13:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:13:56 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120808131356.GS16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 12:41:20PM +0300, Peter Ujfalusi wrote:

> +Required properties:
> +- compatible : must be "ti,twl4030-audio"

So, as I mentioned before I find this sort of direct mapping of the
Linux device representation into the device tree really troubling.
I'm just way too aware of the fact that even the Linux split of these
things can change over time and often represents internal Linux
considerations.

> +-ti,hs_extmute: Use external mute for HS pop reduction
> +-ti,hs_extmute_gpio: Use external GPIO to control the external mute
> +-ti,hs_extmute_disable_level: The desired level of the GPIO line when the
> +			      external mute is disabled. valuse: 0 or 1

This doesn't seem like something that should be in the CODEC driver
really, there's a general need for something which can unmute controls
at the end of the power up sequence and mute before power down.  Also,
if this is going to be part of the binding shouldn't we just omit the
first property and simply check for the presence of the property which
specifies the GPIO?

> +#ifdef CONFIG_OF
> +	if (of_find_node_by_name(node, "codec"))
> +		return true;
> +#endif

This really seems like we should be stubbing out of_find_node_by_name()
to return false in non-OF cases.

> +#ifdef CONFIG_OF
> +	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
> +		return true;
> +#endif

Similarly here.


From prabhakar.lad at ti.com  Wed Aug  8 09:14:35 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:44:35 +0530
Subject: [PATCH v3 0/2] ARM: davinci: add support for dm355 vpbe display
Message-ID: <1344431677-32030-1-git-send-email-prabhakar.lad@ti.com>

This patch series enables VPBE display driver on DM355. 

This patch series is dependent on this patches posted 
http://www.spinics.net/lists/arm-kernel/msg188234.html

Changes for v3:
1: Replaced obsolete preset API by timings API.

Changes for v2: 
1: Removed VPSS clock alias for master and slave which was 
   sent for VPSS driver. since this patch was dependent on 
   patch[1]. I will revist this patch once MC(captrure driver) 
   goes into mainline. 
[1] http://www.spinics.net/lists/linux-media/msg50562.html

Manjunath Hadli (2):
  ARM: davinci: dm355: add support for v4l2 video display
  ARM: davinci: dm355 EVM: add support for VPBE display

 arch/arm/mach-davinci/board-dm355-evm.c |   73 +++++++++++-
 arch/arm/mach-davinci/davinci.h         |    2 +-
 arch/arm/mach-davinci/dm355.c           |  203 +++++++++++++++++++++++++++++--
 3 files changed, 267 insertions(+), 11 deletions(-)



From prabhakar.lad at ti.com  Wed Aug  8 09:14:36 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:44:36 +0530
Subject: [PATCH v3 1/2] ARM: davinci: dm355: add support for v4l2 video display
In-Reply-To: <1344431677-32030-1-git-send-email-prabhakar.lad@ti.com>
References: <1344431677-32030-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344431677-32030-2-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

Create platform devices for various video modules like venc,osd,
vpbe and v4l2 driver for dm355.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
---
 arch/arm/mach-davinci/board-dm355-evm.c |    4 +-
 arch/arm/mach-davinci/davinci.h         |    2 +-
 arch/arm/mach-davinci/dm355.c           |  203 +++++++++++++++++++++++++++++--
 3 files changed, 198 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 1c7b1f4..b9bb0fb 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -253,8 +253,6 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm355_evm_map_io(void)
 {
-	/* setup input configuration for VPFE input devices */
-	dm355_set_vpfe_config(&vpfe_cfg);
 	dm355_init();
 }
 
@@ -344,6 +342,8 @@ static __init void dm355_evm_init(void)
 	davinci_setup_mmc(0, &dm355evm_mmc_config);
 	davinci_setup_mmc(1, &dm355evm_mmc_config);
 
+	dm355_init_video(&vpfe_cfg, NULL);
+
 	dm355_init_spi0(BIT(0), dm355_evm_spi_info,
 			ARRAY_SIZE(dm355_evm_spi_info));
 
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 94d867f..d9eb1a9 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -74,7 +74,7 @@ void __init dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
 		const struct spi_board_info *info, unsigned len);
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
-void dm355_set_vpfe_config(struct vpfe_config *cfg);
+int __init dm355_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM365 function declarations */
 void __init dm365_init(void);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..5f86596 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -713,6 +713,7 @@ static struct resource vpfe_resources[] = {
 };
 
 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+
 static struct resource dm355_ccdc_resource[] = {
 	/* CCDC Base address */
 	{
@@ -744,11 +745,177 @@ static struct platform_device vpfe_capture_dev = {
 	},
 };
 
-void dm355_set_vpfe_config(struct vpfe_config *cfg)
+#define DM355_OSD_REG_BASE		0x01C70200
+
+static struct resource dm355_osd_resources[] = {
+	{
+		.start	= DM355_OSD_REG_BASE,
+		.end	= DM355_OSD_REG_BASE + 0x180,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct osd_platform_data dm355_osd_data = {
+	.vpbe_type	= VPBE_VERSION_3,
+};
+
+static struct platform_device dm355_osd_dev = {
+	.name		= VPBE_OSD_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm355_osd_resources),
+	.resource	= dm355_osd_resources,
+	.dev = {
+		.dma_mask		= &vpfe_capture_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &dm355_osd_data,
+	},
+};
+
+#define DM355_VENC_REG_BASE		0x01C70400
+#define DM3XX_VDAC_CONFIG		0x01C4002C
+
+static struct resource dm355_venc_resources[] = {
+	{
+		.start	= IRQ_VENCINT,
+		.end	= IRQ_VENCINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+	/* venc registers io space */
+	{
+		.start	= DM355_VENC_REG_BASE,
+		.end	= DM355_VENC_REG_BASE + 0x180,
+		.flags	= IORESOURCE_MEM,
+	},
+	/* VDAC config register io space */
+	{
+		.start	= DM3XX_VDAC_CONFIG,
+		.end	= DM3XX_VDAC_CONFIG + 4,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource dm355_v4l2_disp_resources[] = {
+	{
+		.start	= IRQ_VENCINT,
+		.end	= IRQ_VENCINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+	/* venc registers io space */
+	{
+		.start	= DM355_VENC_REG_BASE,
+		.end	= DM355_VENC_REG_BASE + 0x180,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+			    int field)
+{
+	int ret = 0;
+
+	switch (if_type) {
+	case V4L2_MBUS_FMT_SGRBG8_1X8:
+		davinci_cfg_reg(DM355_VOUT_COUTL_EN);
+		davinci_cfg_reg(DM355_VOUT_COUTH_EN);
+		davinci_cfg_reg(DM355_VOUT_FIELD_G70);
+		break;
+	case V4L2_MBUS_FMT_YUYV10_1X20:
+		/*
+		 * This was VPBE_DIGITAL_IF_YCC16. Replace the enum
+		 * accordingly when the right one gets into open source
+		 */
+		if (field)
+			davinci_cfg_reg(DM355_VOUT_FIELD);
+		else
+			davinci_cfg_reg(DM355_VOUT_FIELD_G70);
+		davinci_cfg_reg(DM355_VOUT_COUTL_EN);
+		davinci_cfg_reg(DM355_VOUT_COUTH_EN);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+static inline u32 dm355_reg_modify(void *reg, u32 val, u32 mask)
+{
+	u32 new_val = (__raw_readl(reg) & ~mask) | (val & mask);
+	__raw_writel(new_val, reg);
+	return new_val;
+}
+
+#define DM355_EXTERNAL_CLK_HD			0xa
+#define DM355_VPSS_VENCCLKEN_ENABLE		0x8
+#define DM355_VPSS_DACCLKEN_ENABLE		0x10
+#define DM355_VPSS_CLK_CTRL_ADDR		0x44
+
+static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
+				   unsigned int pclock)
 {
-	vpfe_capture_dev.dev.platform_data = cfg;
+	void __iomem *vpss_clk_ctrl_reg;
+	int ret = 0;
+
+	vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(DM355_VPSS_CLK_CTRL_ADDR);
+
+	switch (type) {
+	case VPBE_ENC_STD:
+		vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 0);
+		__raw_writel(DM355_VPSS_DACCLKEN_ENABLE +
+			DM355_VPSS_VENCCLKEN_ENABLE, vpss_clk_ctrl_reg);
+		break;
+	case VPBE_ENC_CUSTOM_TIMINGS:
+		if (pclock > 27000000) {
+			/*
+			 * For HD, use external clock source since we cannot
+			 * support HD mode with internal clocks.
+			 */
+			__raw_writel(DM355_EXTERNAL_CLK_HD, vpss_clk_ctrl_reg);
+		}
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
 }
 
+static struct platform_device dm355_vpbe_display = {
+	.name		= "vpbe-v4l2",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm355_v4l2_disp_resources),
+	.resource	= dm355_v4l2_disp_resources,
+	.dev		= {
+		.dma_mask		= &vpfe_capture_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+struct venc_platform_data dm355_venc_pdata = {
+	.venc_type		= VPBE_VERSION_3,
+	.setup_pinmux		= dm355_vpbe_setup_pinmux,
+	.setup_clock		= dm355_venc_setup_clock,
+};
+
+static struct platform_device dm355_venc_dev = {
+	.name		= VPBE_VENC_SUBDEV_NAME,
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(dm355_venc_resources),
+	.resource	= dm355_venc_resources,
+	.dev		= {
+		.dma_mask		= &vpfe_capture_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= (void *)&dm355_venc_pdata,
+	},
+};
+
+static struct platform_device dm355_vpbe_dev = {
+	.name		= "vpbe_controller",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &vpfe_capture_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm355_io_desc[] = {
@@ -874,19 +1041,39 @@ void __init dm355_init(void)
 	davinci_map_sysmod();
 }
 
+int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
+				struct vpbe_config *vpbe_cfg)
+{
+	if (vpfe_cfg || vpbe_cfg)
+		platform_device_register(&dm355_vpss_device);
+
+	if (vpfe_cfg) {
+		/* Add ccdc clock aliases */
+		clk_add_alias("master", dm355_ccdc_dev.name,
+			      "vpss_master", NULL);
+		clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_slave", NULL);
+		vpfe_capture_dev.dev.platform_data = vpfe_cfg;
+		platform_device_register(&dm355_ccdc_dev);
+		platform_device_register(&vpfe_capture_dev);
+	}
+
+	if (vpbe_cfg) {
+		dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
+		platform_device_register(&dm355_osd_dev);
+		platform_device_register(&dm355_venc_dev);
+		platform_device_register(&dm355_vpbe_dev);
+		platform_device_register(&dm355_vpbe_display);
+	}
+	return 0;
+}
+
 static int __init dm355_init_devices(void)
 {
 	if (!cpu_is_davinci_dm355())
 		return 0;
 
-	/* Add ccdc clock aliases */
-	clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
-	clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
 	davinci_cfg_reg(DM355_INT_EDMA_CC);
 	platform_device_register(&dm355_edma_device);
-	platform_device_register(&dm355_vpss_device);
-	platform_device_register(&dm355_ccdc_dev);
-	platform_device_register(&vpfe_capture_dev);
 
 	return 0;
 }
-- 
1.7.0.4



From prabhakar.lad at ti.com  Wed Aug  8 09:14:37 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Wed, 8 Aug 2012 18:44:37 +0530
Subject: [PATCH v3 2/2] ARM: davinci: dm355 EVM: add support for VPBE display
In-Reply-To: <1344431677-32030-1-git-send-email-prabhakar.lad@ti.com>
References: <1344431677-32030-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1344431677-32030-3-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

add support for V4L2 video display to DM355 EVM.
Support for SD modes is provided, along with Composite
output

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
---
 arch/arm/mach-davinci/board-dm355-evm.c |   71 ++++++++++++++++++++++++++++++-
 1 files changed, 70 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index b9bb0fb..138dc40 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -242,6 +242,75 @@ static struct vpfe_config vpfe_cfg = {
 	.ccdc = "DM355 CCDC",
 };
 
+#define VENC_STD_ALL	(V4L2_STD_NTSC | V4L2_STD_PAL)
+
+/* venc standards timings */
+static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
+	{
+		.name		= "ntsc",
+		.timings_type	= VPBE_ENC_STD,
+		.std_id		= V4L2_STD_525_60,
+		.interlaced	= 1,
+		.xres		= 720,
+		.yres		= 480,
+		.aspect		= {11, 10},
+		.fps		= {30000, 1001},
+		.left_margin	= 0x79,
+		.right_margin	= 0,
+		.upper_margin	= 0x10,
+	},
+	{
+		.name		= "pal",
+		.timings_type	= VPBE_ENC_STD,
+		.std_id		= V4L2_STD_625_50,
+		.interlaced	= 1,
+		.xres		= 720,
+		.yres		= 576,
+		.aspect		= {54, 59},
+		.fps		= {25, 1},
+		.left_margin	= 0x7E,
+		.right_margin	= 0,
+		.upper_margin	= 0x16
+	},
+};
+
+/*
+ * The outputs available from VPBE + ecnoders. Keep the
+ * the order same as that of encoders. First those from venc followed by that
+ * from encoders. Index in the output refers to index on a particular encoder.
+ * Driver uses this index to pass it to encoder when it supports more than
+ * one output. Application uses index of the array to set an output.
+ */
+static struct vpbe_output dm355evm_vpbe_outputs[] = {
+	{
+		.output		= {
+			.index		= 0,
+			.name		= "Composite",
+			.type		= V4L2_OUTPUT_TYPE_ANALOG,
+			.std		= VENC_STD_ALL,
+			.capabilities	= V4L2_OUT_CAP_STD,
+		},
+		.subdev_name	= VPBE_VENC_SUBDEV_NAME,
+		.default_mode	= "ntsc",
+		.num_modes	= ARRAY_SIZE(dm355evm_enc_preset_timing),
+		.modes		= dm355evm_enc_preset_timing,
+		.if_params	= V4L2_MBUS_FMT_FIXED,
+	},
+};
+
+static struct vpbe_config dm355evm_display_cfg = {
+	.module_name	= "dm355-vpbe-display",
+	.i2c_adapter_id	= 1,
+	.osd		= {
+		.module_name	= VPBE_OSD_SUBDEV_NAME,
+	},
+	.venc		= {
+		.module_name	= VPBE_VENC_SUBDEV_NAME,
+	},
+	.num_outputs	= ARRAY_SIZE(dm355evm_vpbe_outputs),
+	.outputs	= dm355evm_vpbe_outputs,
+};
+
 static struct platform_device *davinci_evm_devices[] __initdata = {
 	&dm355evm_dm9000,
 	&davinci_nand_device,
@@ -342,7 +411,7 @@ static __init void dm355_evm_init(void)
 	davinci_setup_mmc(0, &dm355evm_mmc_config);
 	davinci_setup_mmc(1, &dm355evm_mmc_config);
 
-	dm355_init_video(&vpfe_cfg, NULL);
+	dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
 
 	dm355_init_spi0(BIT(0), dm355_evm_spi_info,
 			ARRAY_SIZE(dm355_evm_spi_info));
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:17:14 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:17:14 +0100
Subject: [PATCH 1/1] Input: ab8500-ponkey: Make the distinction between
 DT and non-DT boots
In-Reply-To: <20120808114037.GB8227@gmail.com>
References: <20120807170333.GV16861@opensource.wolfsonmicro.com>
 <20120808080411.GB4728@gmail.com>
 <20120808094952.GH16861@opensource.wolfsonmicro.com>
 <20120808114037.GB8227@gmail.com>
Message-ID: <20120808131714.GT16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 12:40:38PM +0100, Lee Jones wrote:
> On Wed, Aug 08, 2012 at 10:49:52AM +0100, Mark Brown wrote:

> > >  - MFD adds the IRQ base to the hwirq and registers it as a virq

> > Just don't do this step - the only reason to do it is for mapping back
> > into a linear domain but if you're going to do this...

> > >  - AB8500 child devices use *_get_virq() to convert virq to virq - *ERROR*

> > ...then it's redundant.  The mapping functions in the domain code
> > replace this functionality.

> No, the other way round. This is now required all the time.

> Now we force the use of hwirq, the driver needs to convert that into a
> virq before requesting the resource. So we need to put *_get_virq()'s into
> every child device that requests an IRQ.

Yes, that's exactly what I said - and as a result of doing this the
remapping in the MFD core becomes redundant.


From festevam at gmail.com  Wed Aug  8 09:18:15 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 8 Aug 2012 10:18:15 -0300
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <50226409.1060800@de.bosch.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-7-git-send-email-arnd@arndb.de>
 <CAOMZO5CZ7mJd89cN_S0KBS74mc5qTzvrfRbmHVX3nmEakx19ow@mail.gmail.com>
 <50226409.1060800@de.bosch.com>
Message-ID: <CAOMZO5BtStkEWGRWi7LcVT_DK0C2WnjPiCOh2ZriVzrP+1NW3g@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:05 AM, Dirk Behme <dirk.behme at de.bosch.com> wrote:

> Yes. But it seems it's not handled there? I'm trying since ~2 weeks to get
> something like your patch applied to get the broken mainline fixed, but
> unfortunately without success so far.

Let's try once again.

Artem,

Could https://patchwork.kernel.org/patch/1236551/ be applied?

Thanks,

Fabio Estevam


From cyril at ti.com  Wed Aug  8 09:18:50 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Wed, 8 Aug 2012 09:18:50 -0400
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208080106500.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
 <alpine.LFD.2.02.1208080106500.5231@xanadu.home>
Message-ID: <5022673A.7060407@ti.com>

On 08/08/12 01:56, Nicolas Pitre wrote:
> On Tue, 7 Aug 2012, Cyril Chemparathy wrote:
[...]
>> u32 arm_check[] = {
>> 	0xe2810041, 0xe2810082, 0xe2810f41, 0xe2810f82, 0xe2810e41,
>> 	0xe2810e82, 0xe2810d41, 0xe2810d82, 0xe2810c41, 0xe2810c82,
>> 	0xe2810b41, 0xe2810b82, 0xe2810a41, 0xe2810a82, 0xe2810941,
>> 	0xe2810982, 0xe2810841, 0xe2810882, 0xe2810741, 0xe2810782,
>> 	0xe2810641, 0xe2810682, 0xe2810541, 0xe2810582, 0xe2810441,
>> };
>
> Instead of using this array you could let the assembler do it for you
> like this:
>
> asm (" \n\
> 	.arm \n\
> arm_check: \n\
>          .set shft, 0 \n\
>          .rep 12 \n\
>          add     r1, r2, #0x81 << \shft \n\
>          .set shft, \shft + 2 \n\
>          .endr \n\
> ");
>

Neat macro magic.  Are you thinking that we build this in as a self test 
in the code?

Thanks
-- Cyril.


From ian.molton at codethink.co.uk  Wed Aug  8 09:19:53 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Wed, 08 Aug 2012 14:19:53 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208081239.16778.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <50223428.6030506@codethink.co.uk> <502252A6.4090409@codethink.co.uk>
 <201208081239.16778.arnd@arndb.de>
Message-ID: <50226779.6060201@codethink.co.uk>

On 08/08/12 13:39, Arnd Bergmann wrote:
> On Wednesday 08 August 2012, Ian Molton wrote:
>> The SMI / PHY stuff should look very similar, so I'm happy with something
>> like:
>>
>> mdio at 2000 {
>>                 #address-cells = <1>;
>>                 #size-cells = <1>;
>>                 device_type = "mdio";
>>                 compatible = "marvell,mv643xx-mdio";
>>                 phy0: ethernet-phy at 0 {
>>                         device_type = "ethernet-phy";
>>                         compatible = "marvell,whatever";
>>                         interrupts = <76>;
>>                         interrupt-parent = <&mpic>;
>>                         reg = <0 32>;          // Auto probed phy addr
>>                 };
>>
>>                 phy1: ethernet-phy at 3 {
>>                         device_type = "ethernet-phy";
>>                         compatible = "marvell,whatever";
>>                         interrupts = <77>;
>>                         interrupt-parent = <&mpic>;
>>                         reg = <3 1>;            // specified phy addr
>>                 };
>>
>>                 ... and so on.
>> }
>>
>> Where we can use the reg parameter to allow auto-probing, by
>> specifying a size of 32 (32 phy addrs max).
> I don't understand the auto-probed phy address. What is the purpose of that?

Personally, I think it should die - but the existing driver and a number
of its users actually scan the bus for their PHY.

I doubt the PHY really moves about or is hotplugged by any of them,
and its actually quite a slow process.

> If possible, I think we should keep using #size-cells=<0>, which would
> make the method you describe impossible. It might still work if you just
> leave out the "reg" property for that node.

I can certainly investigate that. I couldn't see any good evidence that
it was a supported mechanism when I looked.

> I also don't understand how the phy driver would locate ethernet-phy at 0
> on the bus if it does not know the address.
>
>> The ethernet driver itself is more complicated:
>>
>> We have the following considerations:
>>
>> * we have one MDIO bus, typically, shared between all the MACs / PHYs.
>> * each ethernet device can multiple ports (up to three), each with its
>>   own MAC/PHY.
>> * MAC <-> PHY mapping can be specified, probed (ugh!) or a (gah!)
>>   mix of the two.
>> * existing D-T users, albeit not well documented / code complete.
>> * some port address ranges overlap (MIB counters, MCAST / UNICAST
>>   tables, etc.
>>
>> The existing ethernet-group idea only works because the current
>> platform-device based driver doesnt really do proper resource
>> management, and thus the MAC registers are actually mapped by
>> the MDIO driver.
>>
>> I don't think that preserving this bad behaviour is a good idea, which
>> leaves us with two choices:
>>
>> 1) My preferred solution - allow each device to specify up to three
>> interrupts, MACs, and PHYs. This is clean in that it doesnt require
>> multiply instantiating a driver three times over the same address
>> space.
>>
>> ethernet at 2400 {
>>                 compatible = "marvell,mv643xx-eth";
>>                 reg = <0x2400 0x1c00>
>>                 interrupt_parent = <&mpic>;
>>                 ports = <3>;
>>                 interrupts = <4>, <5>, <6>;
>>                 phys = <&phy0>, <&phy1>, <&phy2>;
>> };
>>
>> ethernet at 6400 {
>>                 compatible = "marvell,mv643xx-eth";
>>                 reg = <0x6400 0x1c00>
>>                 interrupt_parent = <&mpic>;
>>                 ports = <1>;
>>                 interrupts = <4>;
>>                 phys = <&phy3>;
>> };
>>
>> Note that the address is 2400, not 2000 - since this driver no longer
>> would share its address range with the MDIO driver.
>>
>> This method would require a small amount of rework in the driver to
>> set up <n> ports, rather than just one.
> This looks quite nice, but it is still very much incompatible with the
> existing binding. Obviously we can abandon an existing binding and
> introduce a second one for the same hardware, but that should not
> be taken lightly.

Fair, however the existing users aren't anywhere near as
numerous as the new ones.

>> 2) Create some kind of pseudo-ethernet group device that manages
>> all the work for some sort of lightweight ethernet device, one per
>> port. This can never be done cleanly since the port address ranges
>> overlap:
>>
>> pseudo_eth at 2400 {
>>         #address-cells = <1>;
>>         #size-cells = <0>;
>>         compatible = "marvell,mv643xx-shared-eth"
>>         reg = <0x2400 0x1c00>;
>>
>>         ethernet at 0 {
>>                 compatible = "marvell,mv643xx-port";
>>                 interrupts = <4>;
>>                 interrupt_parent = <&mpic>;
>>                 phy = <&phy0>;
>>         };
>>
>>         ethernet at 1 {
>>                 compatible = "marvell,mv643xx-port";
>>                 interrupts = <5>;
>>                 interrupt_parent = <&mpic>;
>>                 phy = <&phy1>;
>>         };
>>
>>         ethernet at 2 {
>>                 compatible = "marvell,mv643xx-port";
>>                 interrupts = <6>;
>>                 interrupt_parent = <&mpic>;
>>                 phy = <&phy2>;
>>         };
>> }
>> pseudo_eth at 6400 {
>>         #address-cells = <1>;
>>         #size-cells = <0>;
>>         compatible = "marvell,mv643xx-shared-eth"
>>         reg = <0x6400 0x1c00>;
>>
>>         ethernet at 0 {
>>                 compatible = "marvell,mv643xx-port";
>>                 interrupts = <4>;
>>                 interrupt_parent = <&mpic>;
>>                 phy = <&phy3>;
>>         };
>> };
> This looks almost compatible with the existing binding, which is
> good.

Well, I'm not sure about that - if the existing bindings are really
baked into firmware, then "almost" wont be any use at all.

>  I would in fact recommend to use the actual "compatible"
> strings from the binding. More generally speaking, you should not
> use wildcards in those strings anyway, so always use
> "marvell,mv64360-eth" instead of "marvell,mv64x60-eth" or
> "marvell,mv643xx-eth". If you have multiple chips that are
> completely compatible, put use the identifier for the older one.
Noted.

> I don't fully understand your concern with the overlapping
> registers, mostly because I still don't know all the combinations
> that are actually valid here. Let me try to say what I understood
> so far, and you can correct me if that's wrong:
>
> * A system can have multiple instances of an mv64360 ethernet
> block, with a register area of 0x2000 bytes.
> * Each such block can have three MACs and three PHYs.
> * The first 0x400 bytes in the register space control the three
>   PHYs and the remaining registers control the MACs.
> * While this is meant to be used in a way that you assign
>   the each of the three PHYs to one of the MACs, this is not
>   always done, and sometimes you use a different PHY (?), or
>   one from a different instance of the mv64360 ethernet block
>   on the same SoC?.

Nearly - the whole block is 0x2000 in size, yes. And each one
can have 3 MACs and PHYs, as you say.

There is SMI @ 0x2000 - just one for all ports, and in many
(all?) cases, for all all the other controllers on the SoC to
share. On the armadaXP SoC, for example, each ethernet
block has its own alias of the same bas SMI reg. (there are
4 blocks)

ethernet0@ 0x2400
## regs in order: Main regs, MIB counters, Special mcast table, Mcast
table, Unicast table.
   port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
   port1 has regs at +0x0400 *0x1080 +0x1800 +0x1900 +0x1a00
   port2 has regs at +0x0800 *0x1100 +0x1c00 +0x1d00 +0x1e00
ethernet1@ 0x6400
  port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
...

As you can see, instead of putting port1 at +0x1700 or so,
marvell have overlapped the register files - in fact, doubly
so, since port1 + 0x1080 is right in the middle of
(port0 + 0x1000) -> (port0 + 0x16ff), so one cant simply map two
sets of regs like 0x0000->0x03ff and 0x1000->0x16ff for port one
either.

-Ian


From zonque at gmail.com  Wed Aug  8 09:23:15 2012
From: zonque at gmail.com (Daniel Mack)
Date: Wed, 08 Aug 2012 15:23:15 +0200
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <1344430493-5304-3-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-3-git-send-email-arnd@arndb.de>
Message-ID: <50226843.4080508@gmail.com>

On 08.08.2012 14:54, Arnd Bergmann wrote:
> The irq_to_gpio function was removed from the pxa platform
> in linux-3.2, and this driver has been broken since.
> 
> Without this patch, building raumfeld_defconfig results in:
> 
> drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
> drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]

I've sent out a slightly different version of such a patch just
yesterday. It deferres mainly in the fact that it uses gpio_to_irq() and
ignores the i2c_client's irq line. That way, there can't be any
inconsitency.

I've appended the patch again - I haven't heard back from Dmitry yet.


Thanks,
Daniel



> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: stable at vger.kernel.org (v3.2+)
> Cc: Daniel Mack <zonque at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
>  arch/arm/mach-pxa/raumfeld.c        |    1 +
>  drivers/input/touchscreen/eeti_ts.c |    8 +++++---
>  include/linux/input/eeti_ts.h       |    1 +
>  3 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
> index 5905ed1..9e1c4ea 100644
> --- a/arch/arm/mach-pxa/raumfeld.c
> +++ b/arch/arm/mach-pxa/raumfeld.c
> @@ -953,6 +953,7 @@ static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
>  
>  static struct eeti_ts_platform_data eeti_ts_pdata = {
>  	.irq_active_high = 1,
> +	.gpio = GPIO_TOUCH_IRQ,
>  };
>  
>  static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
> diff --git a/drivers/input/touchscreen/eeti_ts.c b/drivers/input/touchscreen/eeti_ts.c
> index 503c709..45dab18 100644
> --- a/drivers/input/touchscreen/eeti_ts.c
> +++ b/drivers/input/touchscreen/eeti_ts.c
> @@ -48,7 +48,7 @@ struct eeti_ts_priv {
>  	struct input_dev *input;
>  	struct work_struct work;
>  	struct mutex mutex;
> -	int irq, irq_active_high;
> +	int irq, gpio, irq_active_high;
>  };
>  
>  #define EETI_TS_BITDEPTH	(11)
> @@ -62,7 +62,7 @@ struct eeti_ts_priv {
>  
>  static inline int eeti_ts_irq_active(struct eeti_ts_priv *priv)
>  {
> -	return gpio_get_value(irq_to_gpio(priv->irq)) == priv->irq_active_high;
> +	return gpio_get_value(priv->gpio) == priv->irq_active_high;
>  }
>  
>  static void eeti_ts_read(struct work_struct *work)
> @@ -203,8 +203,10 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
>  
>  	pdata = client->dev.platform_data;
>  
> -	if (pdata)
> +	if (pdata) {
> +		priv->gpio = pdata->gpio;
>  		priv->irq_active_high = pdata->irq_active_high;
> +	}
>  
>  	irq_flags = priv->irq_active_high ?
>  		IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING;
> diff --git a/include/linux/input/eeti_ts.h b/include/linux/input/eeti_ts.h
> index f875b31..3404504 100644
> --- a/include/linux/input/eeti_ts.h
> +++ b/include/linux/input/eeti_ts.h
> @@ -3,6 +3,7 @@
>  
>  struct eeti_ts_platform_data {
>  	unsigned int irq_active_high;
> +	unsigned int gpio;
>  };
>  
>  #endif /* LINUX_INPUT_EETI_TS_H */
> 

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From linus.walleij at linaro.org  Wed Aug  8 09:24:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 15:24:23 +0200
Subject: [PATCH 5/6] ARM: integrator: include <linux/export.h
In-Reply-To: <1344430493-5304-6-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-6-git-send-email-arnd@arndb.de>
Message-ID: <CACRpkdYbHTtOg6inbemD2SG+XT9ZYN3pcFQjEPv7mbyecagawg@mail.gmail.com>

On Wed, Aug 8, 2012 at 2:54 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> Without this patch, building integrator_defconfig results in:
>
> arch/arm/mach-integrator/core.c:150:1: warning: data definition has no type or storage class [enabled by default]
> arch/arm/mach-integrator/core.c:150:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Wimplicit-int]
> arch/arm/mach-integrator/core.c:150:1: warning: parameter names (without types) in function declaration [enabled by default]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Russell King <linux at arm.linux.org.uk>

Missing a ">" at the end of the subject line, but whatever.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From jarkko.nikula at bitmer.com  Wed Aug  8 09:25:05 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Wed, 08 Aug 2012 16:25:05 +0300
Subject: [PATCH 08/11] ARM: OMAP3: Remove callback for McBSP sidetone
 ICLK workaround
In-Reply-To: <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <502268B1.9040506@bitmer.com>

On 08/08/2012 12:11 PM, Peter Ujfalusi wrote:
> We can achieve the same result with SIDLEMODE field within McBSP SYSCONFIG
> register.
> The ASoC driver has been modified to use this method and we can now remove
> the workaround using the control module register.
> 
Are you sure it works without any changes to sidetone audio quality or
current consumption? What I remember idlemode was broken at least on
3430 and caused bad sidetone audio if autoidle was set and a little bit
higher current consumption (something like 2-3 mA higher where reference
consumption was around 10 mA) when McBSP was set to no-idle.

Here's the old thread:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg52024.html

I think I tested all of this by using arecord >/dev/null | aplay
/dev/zero with threshold based DMA transfers with all bells and whistles
set for dynamic retention idle in order to hear only McBSP sidetone
while measuring current consumption.

But I guess 2-3 mA higher consumption is ok if it simplifies SW a lot
and base consumption is anyway much higher than 10 mA when sidetone is
in real use (my test above was artificial where actual use is under a
phone call with heavy consumption from cellular modem etc).

-- 
Jarkko


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:27:41 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:27:41 +0100
Subject: [PATCH 0/4] ASoC/OMAP: ASoC machine driver for simple SoC with
 twl4030
In-Reply-To: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120808132741.GX16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 12:54:06PM +0300, Peter Ujfalusi wrote:

> Changes under arch/arm/mach-omap2/ are trivial, I don't expect merge issues
> later. If it is OK for the maintainers I would like this to go via audio tree
> (with the McBSP and the twl4030-audio stack DT support).

This all looks OK to me, again if it gets applied via ASoC I'll put it
on a separate branch so if we do need to get into OMAP as well it's easy
to do so.


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:30:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:30:13 +0100
Subject: =?utf-8?B?yLjvv73vv706IFtQQVRD?= =?utf-8?Q?H?= 1/4] arm/dts:
 max77686: Add DTS file for max77686 PMIC
In-Reply-To: <A6A3B7488C419F488E5B13FFD03C08AD2F4372BC@SN2PRD0510MB370.namprd05.prod.outlook.com>
References: <1344366267-18971-1-git-send-email-dongjin.kim@agreeyamobility.net>
 <20120807193413.GE14711@sirena.org.uk>
 <A6A3B7488C419F488E5B13FFD03C08AD2F4372BC@SN2PRD0510MB370.namprd05.prod.outlook.com>
Message-ID: <20120808133013.GY16861@opensource.wolfsonmicro.com>

On Tue, Aug 07, 2012 at 07:50:11PM +0000, Dongjin Kim wrote:

Please fix your mailer to word wrap within paragraphs.

> Are you meaning VDD_MIF_1.0V, for example, would be replaced with
> another common name for other boards and my board file,
> exynos4412-odroidx.dts, describe the name again if necessary? Like
> below?

No, the entire configuration.

> max77686.dtsi:
>     buck1 {
>          regulator-compatible = "BUCK1";
>          regulator-name = "VDD_BUCK1_1.0V";
>          regulator-min-microvolt = <800000>;
>          regulator-max-microvolt = <1050000>;
>          regulator-always-on;
>          regulator-boot-on;
>     };

Especially things like the voltage range might not be appropriate if the
regulator is used for a different purpose on a different board.


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:35:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:35:40 +0100
Subject: [PATCH v2 3/4] regulator: add a new API
 regulator_set_voltage_tol()
In-Reply-To: <1344179121-17738-4-git-send-email-shawn.guo@linaro.org>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120808133540.GB16861@opensource.wolfsonmicro.com>

On Sun, Aug 05, 2012 at 11:05:20PM +0800, Shawn Guo wrote:
> There are some use cases where a voltage range could be reasonably
> specified by a target voltage and tolerance.  Add a new API
> regulator_set_voltage_tol() wrapping regulator_set_voltage() call
> to ease the users.

Applied, thanks!  It's on a separate branch so can easily be either
applied somewhere else or merged into another tree if required for
dependencies, just let me know.


From zonque at gmail.com  Wed Aug  8 09:36:37 2012
From: zonque at gmail.com (Daniel Mack)
Date: Wed, 08 Aug 2012 15:36:37 +0200
Subject: [alsa-devel] DT support for Davinci ASoC platform
In-Reply-To: <501B954C.3070606@ti.com>
References: <1BAFE6F6C881BF42822005164F1491C33EA35352@DBDE01.ent.ti.com>
 <4FF5733E.6000604@gmail.com> <501AE3C6.8040708@gmail.com>
 <501B954C.3070606@ti.com>
Message-ID: <50226B65.4090804@gmail.com>

Hi Serkar,

On 03.08.2012 11:09, Sekhar Nori wrote:
> On 8/3/2012 2:02 AM, Daniel Mack wrote:
>> On 05.07.2012 12:58, Daniel Mack wrote:
>>> Hi Gururaja,
>>>
>>> On 04.07.2012 14:48, Hebbar, Gururaja wrote:
>>>> All,
>>>>
>>>> Are there any plans or work going on for providing Device Tree Support for Davinci
>>>> ASoC?
>>>>
>>>> I am planning to add DT support for TI AM335x (McASP) and I don't want to do duplicate
>>>> task.
>>>
>>> That's good to know. But isn't there a dependency on the EDMA engine? Is
>>> that part ported yet?
>>
>> May I ask whether you made any progress on that yet?
> 
> Matt Porter from TI is working on DMA engine migration. This would still
> be some time away since there is a bunch of work involved here.
> 
> To make progress on Audio DT conversion Gururaja is doing an up port of
> AM335x EDMA support from TI release to mainline kernel. If you are
> interested in it, he can probably share that with you once he posts his
> DT patches.

As the DMA engine is also a requirement for the MMC controller, I would
be interested in helping, in case help is required. Is there any
repository with code that I can have a look at?

Thanks,
Daniel



From peter.ujfalusi at ti.com  Wed Aug  8 09:43:16 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 16:43:16 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120808131356.GS16861@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
Message-ID: <50226CF4.1010202@ti.com>

On 08/08/2012 04:13 PM, Mark Brown wrote:
> On Wed, Aug 08, 2012 at 12:41:20PM +0300, Peter Ujfalusi wrote:
> 
>> +Required properties:
>> +- compatible : must be "ti,twl4030-audio"
> 
> So, as I mentioned before I find this sort of direct mapping of the
> Linux device representation into the device tree really troubling.
> I'm just way too aware of the fact that even the Linux split of these
> things can change over time and often represents internal Linux
> considerations.

Yes, I remember. This is however a bit different case compared to the twl6040.
The twl4030 series of PMIC includes the following parts:
twl4030, twl5030, twl5031, tps65950, tps65930 - contains audio block
tps65920, tps65921 - does not contain audio block

So the audio block within these PMICs are really a block, it is present on
some PMIC and it is missing on other's.

This is what we discussed regarding to twl6040. I only expose the audio block
and not the Linux implementation (that we have separate driver for vibra and
codec sub functionality).

>> +-ti,hs_extmute: Use external mute for HS pop reduction
>> +-ti,hs_extmute_gpio: Use external GPIO to control the external mute
>> +-ti,hs_extmute_disable_level: The desired level of the GPIO line when the
>> +			      external mute is disabled. valuse: 0 or 1
> 
> This doesn't seem like something that should be in the CODEC driver
> really, there's a general need for something which can unmute controls
> at the end of the power up sequence and mute before power down.  Also,
> if this is going to be part of the binding shouldn't we just omit the
> first property and simply check for the presence of the property which
> specifies the GPIO?

The hs_extmute is used for reducing pop noise on the headset. The sequence is
described in the TRM and it need to be done within the codec driver since it
is within the sequence.
Now there's two ways for boards to implement it:
using the dedicated pin from twl4030 PMIC (MUTE/GPIO6) - if only
"ti,hs_extmute" present we use this mode.
Some boards are using the GPIO6 from twl4030 for other purposes, in this case
an external GPIO is used for the same purpose - thus we have
ti,hs_extmute_gpio and ti,hs_extmute_disable_level to tell the driver this.
As for the ti,hs_extmute_disable_level: some boards chosen that the mute is
disabled when the signal is high on the GPIO (don't ask me why). This property
tells this.

All of this has to be in the driver due to the sequencing requirements.

> 
>> +#ifdef CONFIG_OF
>> +	if (of_find_node_by_name(node, "codec"))
>> +		return true;
>> +#endif
> 
> This really seems like we should be stubbing out of_find_node_by_name()
> to return false in non-OF cases.

Yes, most likely the of_find_node_by_name() deserves the same treatment as
some selected of_* function in case CONFIG_OF is not selected.
But at the moment this is not the case, we need to protect with ifdef since we
might break other randconfigs where CONFIG_OF is not set.

>> +#ifdef CONFIG_OF
>> +	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
>> +		return true;
>> +#endif
> 
> Similarly here.

Here the ifdef is no needed. of_property_read_u32() return -ENOSYS in case
CONFIG_OF is not selected.

-- 
P?ter


From tony at atomide.com  Wed Aug  8 09:48:50 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 06:48:50 -0700
Subject: [PATCH v3 2/7] mfd: omap: control: core system control driver
In-Reply-To: <4FEB4B46.9020904@dev.rtsoft.ru>
References: <4FEB4B46.9020904@dev.rtsoft.ru>
Message-ID: <20120808134849.GC11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120627 11:09]:
> +
> +/* TODO: Add helpers for 16bit and byte access */
> +#ifdef CONFIG_MFD_OMAP_CONTROL
> +u32 omap_control_status_read(u16 offset);
> +#else
> +static inline u32 omap_control_status_read(u16 offset)
> +{
> +	return 0;
> +}
> +#endif

This should be an exported function instead. And it should
not need the offset as a parameter as the SCM core should know
where to find it's control_status register.

Regards,

Tony


From tony at atomide.com  Wed Aug  8 09:50:00 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 06:50:00 -0700
Subject: [PATCH v3 3/7] OMAP2+: use control module mfd driver in omap_type
In-Reply-To: <4FEB4B4A.1040204@dev.rtsoft.ru>
References: <4FEB4B4A.1040204@dev.rtsoft.ru>
Message-ID: <20120808135000.GD11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120627 11:09]:
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -18,6 +18,7 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <linux/mfd/omap_control.h>
>  
>  #include <asm/cputype.h>
>  
> @@ -43,13 +44,13 @@ int omap_type(void)
>  	u32 val = 0;
>  
>  	if (cpu_is_omap24xx()) {
> -		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
> +		val = omap_control_status_read(OMAP24XX_CONTROL_STATUS);
>  	} else if (cpu_is_am33xx()) {
> -		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
> +		val = omap_control_status_read(AM33XX_CONTROL_STATUS);
>  	} else if (cpu_is_omap34xx()) {
> -		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
> +		val = omap_control_status_read(OMAP343X_CONTROL_STATUS);
>  	} else if (cpu_is_omap44xx()) {
> -		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
> +		val = omap_control_status_read(OMAP4_CTRL_MODULE_CORE_STATUS);
>  	} else {
>  		pr_err("Cannot detect omap type!\n");
>  		goto out;

I think I already commented on this.. This needs to become just:

val = omap_control_status_read();

with no need to pass the status register as a parameter.

Regards,

Tony


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 09:52:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 14:52:53 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <50226CF4.1010202@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
Message-ID: <20120808135253.GC16861@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 04:43:16PM +0300, Peter Ujfalusi wrote:
> On 08/08/2012 04:13 PM, Mark Brown wrote:

> > This doesn't seem like something that should be in the CODEC driver
> > really, there's a general need for something which can unmute controls
> > at the end of the power up sequence and mute before power down.  Also,
> > if this is going to be part of the binding shouldn't we just omit the
> > first property and simply check for the presence of the property which
> > specifies the GPIO?

> The hs_extmute is used for reducing pop noise on the headset. The sequence is
> described in the TRM and it need to be done within the codec driver since it
> is within the sequence.

Is the point it's at in the sequence the end?

> >> +#ifdef CONFIG_OF
> >> +	if (of_find_node_by_name(node, "codec"))
> >> +		return true;
> >> +#endif

> > This really seems like we should be stubbing out of_find_node_by_name()
> > to return false in non-OF cases.

> Yes, most likely the of_find_node_by_name() deserves the same treatment as
> some selected of_* function in case CONFIG_OF is not selected.
> But at the moment this is not the case, we need to protect with ifdef since we
> might break other randconfigs where CONFIG_OF is not set.

We can always add a patch stubbing it out as part of the series, or in a
branch in the OF tree that we can pull in.

> 
> >> +#ifdef CONFIG_OF
> >> +	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
> >> +		return true;
> >> +#endif
> > 
> > Similarly here.
> 
> Here the ifdef is no needed. of_property_read_u32() return -ENOSYS in case
> CONFIG_OF is not selected.
> 
> -- 
> P?ter


From nicolas.pitre at linaro.org  Wed Aug  8 09:55:12 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 8 Aug 2012 09:55:12 -0400 (EDT)
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <5022673A.7060407@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
 <alpine.LFD.2.02.1208080106500.5231@xanadu.home>
 <5022673A.7060407@ti.com>
Message-ID: <alpine.LFD.2.02.1208080948210.5231@xanadu.home>

On Wed, 8 Aug 2012, Cyril Chemparathy wrote:

> On 08/08/12 01:56, Nicolas Pitre wrote:
> > On Tue, 7 Aug 2012, Cyril Chemparathy wrote:
> [...]
> > > u32 arm_check[] = {
> > > 	0xe2810041, 0xe2810082, 0xe2810f41, 0xe2810f82, 0xe2810e41,
> > > 	0xe2810e82, 0xe2810d41, 0xe2810d82, 0xe2810c41, 0xe2810c82,
> > > 	0xe2810b41, 0xe2810b82, 0xe2810a41, 0xe2810a82, 0xe2810941,
> > > 	0xe2810982, 0xe2810841, 0xe2810882, 0xe2810741, 0xe2810782,
> > > 	0xe2810641, 0xe2810682, 0xe2810541, 0xe2810582, 0xe2810441,
> > > };
> > 
> > Instead of using this array you could let the assembler do it for you
> > like this:
> > 
> > asm (" \n\
> > 	.arm \n\
> > arm_check: \n\
> >          .set shft, 0 \n\
> >          .rep 12 \n\
> >          add     r1, r2, #0x81 << \shft \n\
> >          .set shft, \shft + 2 \n\
> >          .endr \n\
> > ");
> > 
> 
> Neat macro magic.  Are you thinking that we build this in as a self test in
> the code?

For such things, this is never a bad idea to have some test alongside 
with the main code, especially if this is extended to more cases in the 
future.  It is too easy to break it in subtle ways.

See arch/arm/kernel/kprobes-test*.c for a precedent.


Nicolas


From tony at atomide.com  Wed Aug  8 09:55:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 06:55:28 -0700
Subject: [PATCH v3 5/7] ARM: OMAP4+: thermal: introduce bandgap
 temperature sensor
In-Reply-To: <4FEB4B4F.9040709@dev.rtsoft.ru>
References: <4FEB4B4F.9040709@dev.rtsoft.ru>
Message-ID: <20120808135527.GE11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120627 11:09]:
> +
> +module_platform_driver(omap_bandgap_sensor_driver);
> +early_platform_init("early_omap_temperature", &omap_bandgap_sensor_driver);

Why does this need to be early_platform_init?

Tony


From will.deacon at arm.com  Wed Aug  8 09:57:24 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 Aug 2012 14:57:24 +0100
Subject: [PATCH 00/22] Introducing the TI Keystone platform
In-Reply-To: <1343775898-28345-1-git-send-email-cyril@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
Message-ID: <20120808135724.GC4579@mudshark.cambridge.arm.com>

Hi Cyril,

On Wed, Aug 01, 2012 at 12:04:36AM +0100, Cyril Chemparathy wrote:
> This series is a follow on to the RFC series posted earlier (archived at [1]).
> The major change introduced here is the modification to the kernel patching
> mechanism for phys_to_virt/virt_to_phys, in order to support LPAE platforms
> that require late patching.  In addition to these changes, we've updated the
> series based on feedback from the earlier posting.

One thing I've noticed going through this code and also looking at the rest
of the LPAE code in mainline is that it's not at all clear what is the maximum
physical address we can support for memory.

We currently have the following restrictions:

ARM architecture: 40 bits
ARCH_PGD_SHIFT	: 38 bits
swapfile	: 36 bits (I posted some patches for this. We could
                           extend to 37 bits if we complicate the code)
SPARSEMEM	: 36 bits (due to limited number of page-flags)

It would be nice if we could define a 36-bit memory limit across the kernel
for LPAE whilst allowing higher addresses to be used for peripherals. This
also matches x86 PAE, so the common code will also work correctly.

Otherwise I worry that we will see platforms with memory right at the top of
the physical map and these will be incredibly painful to support.

Will


From tarun.kanti at ti.com  Wed Aug  8 09:58:36 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 8 Aug 2012 19:28:36 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
Message-ID: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>

Add *remove* callback so that necessary cleanup operations are
performed when device is unregistered. The device is deleted
from the list and associated clock handle is released by
calling clk_put() and irq descriptor is released using the
irq_free_desc() api.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reported-by: Paul Walmsley <paul at pwsan.com>
Reviewed-by: Jon Hunter <jon-hunter at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Cousson, Benoit <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
---
v2:
Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)

(1) Use irq_free_descs() instead of irq_free_desc().
    Besides, irq_free_desc() was using wrong parameter,
    irq_base, instead of bank->irq.
(2) irq_free_descs() moved outside spin_lock/unlock_*()
    in order to avoid exception warnings.

(3) pm_runtime_disable() added so that bind can happen successfully

Test Detail:
Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
#echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind

Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
#echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind

Step 3: Execute read/write GPIO test case.

 drivers/gpio/gpio-omap.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..50de875 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1152,6 +1152,40 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 	return ret;
 }
 
+/**
+ * omap_gpio_remove - cleanup a registered gpio device
+ * @pdev:       pointer to current gpio platform device
+ *
+ * Called by driver framework whenever a gpio device is unregistered.
+ * GPIO is deleted from the list and associated clock handle freed.
+ */
+static int __devexit omap_gpio_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct gpio_bank *bank;
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	list_for_each_entry(bank, &omap_gpio_list, node) {
+		spin_lock_irqsave(&bank->lock, flags);
+		if (bank->dev == dev) {
+			clk_put(bank->dbck);
+			list_del(&bank->node);
+			ret = 0;
+			spin_unlock_irqrestore(&bank->lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&bank->lock, flags);
+	}
+
+	if (!ret) {
+		pm_runtime_disable(bank->dev);
+		irq_free_descs(bank->irq_base, bank->width);
+	}
+
+	return ret;
+}
+
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
 #if defined(CONFIG_PM_RUNTIME)
@@ -1478,6 +1512,7 @@ MODULE_DEVICE_TABLE(of, omap_gpio_match);
 
 static struct platform_driver omap_gpio_driver = {
 	.probe		= omap_gpio_probe,
+	.remove = __devexit_p(omap_gpio_remove),
 	.driver		= {
 		.name	= "omap_gpio",
 		.pm	= &gpio_pm_ops,
-- 
1.7.0.4



From peter.ujfalusi at ti.com  Wed Aug  8 10:00:36 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 17:00:36 +0300
Subject: [alsa-devel] [PATCH 08/11] ARM: OMAP3: Remove callback for McBSP
 sidetone ICLK workaround
In-Reply-To: <502268B1.9040506@bitmer.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>
 <502268B1.9040506@bitmer.com>
Message-ID: <50227104.3040506@ti.com>

Hi Jarkko,

On 08/08/2012 04:25 PM, Jarkko Nikula wrote:
> On 08/08/2012 12:11 PM, Peter Ujfalusi wrote:
>> We can achieve the same result with SIDLEMODE field within McBSP SYSCONFIG
>> register.
>> The ASoC driver has been modified to use this method and we can now remove
>> the workaround using the control module register.
>>
> Are you sure it works without any changes to sidetone audio quality or
> current consumption? What I remember idlemode was broken at least on
> 3430 and caused bad sidetone audio if autoidle was set and a little bit
> higher current consumption (something like 2-3 mA higher where reference
> consumption was around 10 mA) when McBSP was set to no-idle.

Yes, the idelmode settings are still broken in the sidetone block. However we
are toggling the SIDLEMODE of the corresponding McBSP instance where the ST
block is attached.
This should have the same effect as doing the same down in PRCM level since
the McBSP SIDLEMODE does work correctly preventing ICLK to be gated when it is
set to no-idle.

Unfortunately I can not get my BeagleBoard to start gating iclk even if I
remove the ICLK gating prevention (on top of 3.6-rc1). So I can not really say
for 100% this is equivalent to the the PRCM level workaround.
However I have also spend long time hacking around in McBSP, and I know that
the SIDLEMODE in McBSP is working correctly.
Do you know how can I get OMAP3 to start gating the clocks (to idle)?

> Here's the old thread:
> 
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg52024.html
> 
> I think I tested all of this by using arecord >/dev/null | aplay
> /dev/zero with threshold based DMA transfers with all bells and whistles
> set for dynamic retention idle in order to hear only McBSP sidetone
> while measuring current consumption.

I'm doing the same test on BeagleBoard, but this thing does not want to hit
retention despite all the effort :(

> But I guess 2-3 mA higher consumption is ok if it simplifies SW a lot
> and base consumption is anyway much higher than 10 mA when sidetone is
> in real use (my test above was artificial where actual use is under a
> phone call with heavy consumption from cellular modem etc).

Well 2-3 mA is quite big number in my book...
I'm still not sure if I ever measured the difference between the PRCM level
autoidle prevention compared to the McBSP SIDLEMODE(no_idle).

Having said that, it is suspicious how we ended up doing the ICLK fixup in
PRCM level...

-- 
P?ter


From arnd at arndb.de  Wed Aug  8 10:01:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 14:01:12 +0000
Subject: [PATCH 5/6] ARM: integrator: include <linux/export.h
In-Reply-To: <CACRpkdYbHTtOg6inbemD2SG+XT9ZYN3pcFQjEPv7mbyecagawg@mail.gmail.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-6-git-send-email-arnd@arndb.de>
 <CACRpkdYbHTtOg6inbemD2SG+XT9ZYN3pcFQjEPv7mbyecagawg@mail.gmail.com>
Message-ID: <201208081401.12909.arnd@arndb.de>

On Wednesday 08 August 2012, Linus Walleij wrote:
> Missing a ">" at the end of the subject line, but whatever.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Fixed the subject and added the Ack. Thanks!

	Arnd


From santosh.shilimkar at ti.com  Wed Aug  8 10:03:12 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 8 Aug 2012 19:33:12 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <CAMQu2gzi0_NS_W_DN=D=+3n6sNw_NTfkaNzaqV3QPG4mL+RoRg@mail.gmail.com>

On Wed, Aug 8, 2012 at 7:28 PM, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
> Add *remove* callback so that necessary cleanup operations are
> performed when device is unregistered. The device is deleted
> from the list and associated clock handle is released by
> calling clk_put() and irq descriptor is released using the
> irq_free_desc() api.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Reported-by: Paul Walmsley <paul at pwsan.com>
> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Cousson, Benoit <b-cousson at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> ---
> v2:
> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>
> (1) Use irq_free_descs() instead of irq_free_desc().
>     Besides, irq_free_desc() was using wrong parameter,
>     irq_base, instead of bank->irq.
> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>     in order to avoid exception warnings.
>
> (3) pm_runtime_disable() added so that bind can happen successfully
>
> Test Detail:
> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>
> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>
> Step 3: Execute read/write GPIO test case.
>
Thanks details about test. Whe  you to "Unbind->bind", do
you see that PM is not broken.

In other words, can you also test and ensure that the OMAP3 suspend and
CPUIDLE are not broken because of this patch.
PER and CORE domains should transition to low power states.

Regards
Santosh


From tony at atomide.com  Wed Aug  8 10:05:07 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 07:05:07 -0700
Subject: [PATCH v4 2/4] mfd: omap: control: core system control driver
In-Reply-To: <500FD2EC.7060208@dev.rtsoft.ru>
References: <500FD2EC.7060208@dev.rtsoft.ru>
Message-ID: <20120808140507.GF11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120725 04:10]:
> +
> +u32 omap_control_status_read(void)
> +{
> +	return __raw_readl(omap_control_base);
> +}

Ah OK it's changed here.. Sorry I was looking at the older
version.

> +void __init of_omap_control_init(const struct of_device_id *matches)
> +{
> +	struct device_node *np;
> +	struct property *pp = 0;
> +
> +	for_each_matching_node(np, matches) {
> +		pp = of_find_property(np, "reg", NULL);
> +		if(pp) {
> +			omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
> +			omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
> +			/*
> +			 * Map control module register CONTROL_STATUS register:
> +			 * omap24xx - OMAP24XX_CONTROL_STATUS
> +			 * am33xx   - AM33XX_CONTROL_STATUS
> +			 * omap34xx - OMAP343X_CONTROL_STATUS
> +			 * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
> +			 * omap54xx - OMAP5XXX_CONTROL_STATUS
> +			 */
> +			omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
> +		}
> +	}
> +}

You should probably add a function for setting omap_control_base
separately from *set_globals* in arch/arm/mach-omap2/common.c.
That way it's initialized early for id.c, and you can initialize
everything else later as regular device drivers.

FYI, we want to initialize as much as possible late so we have
proper debugging console set up in case things go wrong.

Regards,

Tony


From paul at pwsan.com  Wed Aug  8 10:05:50 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 8 Aug 2012 08:05:50 -0600 (MDT)
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
Message-ID: <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>

Hello Vaibhav,

On Wed, 8 Aug 2012, Vaibhav Bedia wrote:

> If no match is found for a hwmod class, omap_hwmod_for_each_by_class()
> currently does not spit out any error messages. To make debugging
> issues related to non-existent hwmod classes simpler make this function
> print an error message in case no match is found for the supplied hwmod
> class.
> 
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>

It doesn't seem to me that this would necessarily always be an error.  
Suppose some init code to create cpsw devices is running on an OMAP3430.  
Then a omap_hwmod_for_each_by_class() that doesn't locate anything 
wouldn't be an error, right?


- Paul


From tarun.kanti at ti.com  Wed Aug  8 10:08:07 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Wed, 8 Aug 2012 19:38:07 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <CAMQu2gzi0_NS_W_DN=D=+3n6sNw_NTfkaNzaqV3QPG4mL+RoRg@mail.gmail.com>
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
 <CAMQu2gzi0_NS_W_DN=D=+3n6sNw_NTfkaNzaqV3QPG4mL+RoRg@mail.gmail.com>
Message-ID: <CAC83ZvK9KVpH=7K9eAHQY3WDtEbw_W_Drxqhk=6v+wZzcOYHDw@mail.gmail.com>

On Wed, Aug 8, 2012 at 7:33 PM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> On Wed, Aug 8, 2012 at 7:28 PM, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
>> Add *remove* callback so that necessary cleanup operations are
>> performed when device is unregistered. The device is deleted
>> from the list and associated clock handle is released by
>> calling clk_put() and irq descriptor is released using the
>> irq_free_desc() api.
>>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> Reported-by: Paul Walmsley <paul at pwsan.com>
>> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
>> Cc: Kevin Hilman <khilman at ti.com>
>> Cc: Rajendra Nayak <rnayak at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Cc: Cousson, Benoit <b-cousson at ti.com>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> ---
>> v2:
>> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>>
>> (1) Use irq_free_descs() instead of irq_free_desc().
>>     Besides, irq_free_desc() was using wrong parameter,
>>     irq_base, instead of bank->irq.
>> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>>     in order to avoid exception warnings.
>>
>> (3) pm_runtime_disable() added so that bind can happen successfully
>>
>> Test Detail:
>> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>>
>> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>>
>> Step 3: Execute read/write GPIO test case.
>>
> Thanks details about test. Whe  you to "Unbind->bind", do
> you see that PM is not broken.
>
> In other words, can you also test and ensure that the OMAP3 suspend and
> CPUIDLE are not broken because of this patch.
> PER and CORE domains should transition to low power states.
Sure, I will do the PM test on OMAP3 and confirm this.
---
Tarun
>
> Regards
> Santosh


From tony at atomide.com  Wed Aug  8 10:10:51 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 07:10:51 -0700
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system
 control driver
In-Reply-To: <20120808140507.GF11011@atomide.com>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com>
Message-ID: <20120808141051.GG11011@atomide.com>

* Tony Lindgren <tony at atomide.com> [120808 07:05]:
> * Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120725 04:10]:
> > +
> > +u32 omap_control_status_read(void)
> > +{
> > +	return __raw_readl(omap_control_base);
> > +}
> 
> Ah OK it's changed here.. Sorry I was looking at the older
> version.
> 
> > +void __init of_omap_control_init(const struct of_device_id *matches)
> > +{
> > +	struct device_node *np;
> > +	struct property *pp = 0;
> > +
> > +	for_each_matching_node(np, matches) {
> > +		pp = of_find_property(np, "reg", NULL);
> > +		if(pp) {
> > +			omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
> > +			omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
> > +			/*
> > +			 * Map control module register CONTROL_STATUS register:
> > +			 * omap24xx - OMAP24XX_CONTROL_STATUS
> > +			 * am33xx   - AM33XX_CONTROL_STATUS
> > +			 * omap34xx - OMAP343X_CONTROL_STATUS
> > +			 * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
> > +			 * omap54xx - OMAP5XXX_CONTROL_STATUS
> > +			 */
> > +			omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
> > +		}
> > +	}
> > +}
> 
> You should probably add a function for setting omap_control_base
> separately from *set_globals* in arch/arm/mach-omap2/common.c.
> That way it's initialized early for id.c, and you can initialize
> everything else later as regular device drivers.
> 
> FYI, we want to initialize as much as possible late so we have
> proper debugging console set up in case things go wrong.

Hmm it seems that omap_control_base is now only initialized for DT boot
case? This will break booting on almost all systems..

Tony


From peter.ujfalusi at ti.com  Wed Aug  8 10:16:58 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 17:16:58 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120808135253.GC16861@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
Message-ID: <502274DA.9020204@ti.com>

On 08/08/2012 04:52 PM, Mark Brown wrote:
>> The hs_extmute is used for reducing pop noise on the headset. The sequence is
>> described in the TRM and it need to be done within the codec driver since it
>> is within the sequence.
> 
> Is the point it's at in the sequence the end?

On both ends :o
On HS enable: the extmute has to be enabled, run the power on sequence for the
HS, wait for ramp, disable the HS extmute.

On stop: enable the extmute, run the sequence, wait for ramp, release the extmute.

> We can always add a patch stubbing it out as part of the series, or in a
> branch in the OF tree that we can pull in.

If you are OK with the hassle I can add a patch to the series for
include/linux/of.h to handle this.

-- 
P?ter


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 10:18:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 15:18:50 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <502274DA.9020204@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
Message-ID: <20120808141849.GA24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 05:16:58PM +0300, Peter Ujfalusi wrote:
> On 08/08/2012 04:52 PM, Mark Brown wrote:

> > Is the point it's at in the sequence the end?

> On both ends :o
> On HS enable: the extmute has to be enabled, run the power on sequence for the
> HS, wait for ramp, disable the HS extmute.

> On stop: enable the extmute, run the sequence, wait for ramp, release the extmute.

I'm struggling to see any reason not to just hold the external mute on
for the entire time the headset is powered off?

> > We can always add a patch stubbing it out as part of the series, or in a
> > branch in the OF tree that we can pull in.

> If you are OK with the hassle I can add a patch to the series for
> include/linux/of.h to handle this.

Yes, please.


From arnd at arndb.de  Wed Aug  8 10:19:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 14:19:16 +0000
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <50226843.4080508@gmail.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-3-git-send-email-arnd@arndb.de> <50226843.4080508@gmail.com>
Message-ID: <201208081419.17181.arnd@arndb.de>

On Wednesday 08 August 2012, Daniel Mack wrote:
> On 08.08.2012 14:54, Arnd Bergmann wrote:
> > The irq_to_gpio function was removed from the pxa platform
> > in linux-3.2, and this driver has been broken since.
> > 
> > Without this patch, building raumfeld_defconfig results in:
> > 
> > drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
> > drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]
> 
> I've sent out a slightly different version of such a patch just
> yesterday. It deferres mainly in the fact that it uses gpio_to_irq() and
> ignores the i2c_client's irq line. That way, there can't be any
> inconsitency.
> 
> I've appended the patch again - I haven't heard back from Dmitry yet.
> 

I've taken your patch instead now, because contains the gpio_request_one
call that I was missing and you sent it before me, but I also noticed
that you forgot to change arch/arm/mach-pxa/raumfeld.c along with the
driver. I've put that in there as well now. If Dmitry wants to take this
patch, I'll drop it from my tree, otherwise I'll send it myself.

	Arnd

8<-----
From a919cfbeb9441f5058feec8f790ef90d9299a448 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Mon, 30 Apr 2012 16:21:37 +0000
Subject: [PATCH] Input: eeti_ts: pass gpio value instead of IRQ

The EETI touchscreen asserts its IRQ line as soon as it has data in its
internal buffers. The line is automatically deasserted once all data has
been read via I2C. Hence, the driver has to monitor the GPIO line and
cannot simply rely on the interrupt handler reception.

In the current implementation of the driver, irq_to_gpio() is used to
determine the GPIO number from the i2c_client's IRQ value.

As irq_to_gpio() is not available on all platforms, this patch changes
this and makes the driver ignore the passed in IRQ. Instead, a GPIO is
added to the platform_data struct and gpio_to_irq is used to derive the
IRQ from that GPIO. If this fails, bail out. The driver is only able to
work in environments where the touchscreen GPIO can be mapped to an
IRQ.

Without this patch, building raumfeld_defconfig results in:

drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]

Signed-off-by: Daniel Mack <zonque at gmail.com>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: stable at vger.kernel.org (v3.2+)
Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: Sven Neumann <s.neumann at raumfeld.com>
Cc: linux-input at vger.kernel.org
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>

diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 5905ed1..d89d87ae 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -953,12 +953,12 @@ static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
 
 static struct eeti_ts_platform_data eeti_ts_pdata = {
 	.irq_active_high = 1,
+	.irq_gpio = GPIO_TOUCH_IRQ,
 };
 
 static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
 	.type	= "eeti_ts",
 	.addr	= 0x0a,
-	.irq	= PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
 	.platform_data = &eeti_ts_pdata,
 };
 
diff --git a/drivers/input/touchscreen/eeti_ts.c b/drivers/input/touchscreen/eeti_ts.c
index 503c709..908407e 100644
--- a/drivers/input/touchscreen/eeti_ts.c
+++ b/drivers/input/touchscreen/eeti_ts.c
@@ -48,7 +48,7 @@ struct eeti_ts_priv {
 	struct input_dev *input;
 	struct work_struct work;
 	struct mutex mutex;
-	int irq, irq_active_high;
+	int irq_gpio, irq, irq_active_high;
 };
 
 #define EETI_TS_BITDEPTH	(11)
@@ -62,7 +62,7 @@ struct eeti_ts_priv {
 
 static inline int eeti_ts_irq_active(struct eeti_ts_priv *priv)
 {
-	return gpio_get_value(irq_to_gpio(priv->irq)) == priv->irq_active_high;
+	return gpio_get_value(priv->irq_gpio) == priv->irq_active_high;
 }
 
 static void eeti_ts_read(struct work_struct *work)
@@ -157,7 +157,7 @@ static void eeti_ts_close(struct input_dev *dev)
 static int __devinit eeti_ts_probe(struct i2c_client *client,
 				   const struct i2c_device_id *idp)
 {
-	struct eeti_ts_platform_data *pdata;
+	struct eeti_ts_platform_data *pdata = client->dev.platform_data;
 	struct eeti_ts_priv *priv;
 	struct input_dev *input;
 	unsigned int irq_flags;
@@ -199,9 +199,12 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
 
 	priv->client = client;
 	priv->input = input;
-	priv->irq = client->irq;
+	priv->irq_gpio = pdata->irq_gpio;
+	priv->irq = gpio_to_irq(pdata->irq_gpio);
 
-	pdata = client->dev.platform_data;
+	err = gpio_request_one(pdata->irq_gpio, GPIOF_IN, client->name);
+	if (err < 0)
+		goto err1;
 
 	if (pdata)
 		priv->irq_active_high = pdata->irq_active_high;
@@ -215,13 +218,13 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
 
 	err = input_register_device(input);
 	if (err)
-		goto err1;
+		goto err2;
 
 	err = request_irq(priv->irq, eeti_ts_isr, irq_flags,
 			  client->name, priv);
 	if (err) {
 		dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
-		goto err2;
+		goto err3;
 	}
 
 	/*
@@ -233,9 +236,11 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
 	device_init_wakeup(&client->dev, 0);
 	return 0;
 
-err2:
+err3:
 	input_unregister_device(input);
 	input = NULL; /* so we dont try to free it below */
+err2:
+	gpio_free(pdata->irq_gpio);
 err1:
 	input_free_device(input);
 	kfree(priv);
diff --git a/include/linux/input/eeti_ts.h b/include/linux/input/eeti_ts.h
index f875b31..16625d7 100644
--- a/include/linux/input/eeti_ts.h
+++ b/include/linux/input/eeti_ts.h
@@ -2,6 +2,7 @@
 #define LINUX_INPUT_EETI_TS_H
 
 struct eeti_ts_platform_data {
+	int irq_gpio;
 	unsigned int irq_active_high;
 };
 


From zonque at gmail.com  Wed Aug  8 10:22:13 2012
From: zonque at gmail.com (Daniel Mack)
Date: Wed, 08 Aug 2012 16:22:13 +0200
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <201208081419.17181.arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-3-git-send-email-arnd@arndb.de> <50226843.4080508@gmail.com>
 <201208081419.17181.arnd@arndb.de>
Message-ID: <50227615.1090907@gmail.com>

On 08.08.2012 16:19, Arnd Bergmann wrote:
> On Wednesday 08 August 2012, Daniel Mack wrote:
>> On 08.08.2012 14:54, Arnd Bergmann wrote:
>>> The irq_to_gpio function was removed from the pxa platform
>>> in linux-3.2, and this driver has been broken since.
>>>
>>> Without this patch, building raumfeld_defconfig results in:
>>>
>>> drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
>>> drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]
>>
>> I've sent out a slightly different version of such a patch just
>> yesterday. It deferres mainly in the fact that it uses gpio_to_irq() and
>> ignores the i2c_client's irq line. That way, there can't be any
>> inconsitency.
>>
>> I've appended the patch again - I haven't heard back from Dmitry yet.
>>
> 
> I've taken your patch instead now, 

Will that go to some other tree than linux-input now?

> because contains the gpio_request_one
> call that I was missing and you sent it before me, but I also noticed
> that you forgot to change arch/arm/mach-pxa/raumfeld.c along with the
> driver. I've put that in there as well now. If Dmitry wants to take this
> patch, I'll drop it from my tree, otherwise I'll send it myself.

Forget about that raumfeld.c part for now. I'm in the process of
replacing all that code with DT bindings and wanted to avoid updates to
that code :)

Btw - I have a patch ready that adds eeti_ts DT bindings. I would submit
that once Dmitry (or you) has taken the other one.



Daniel


> 8<-----
> From a919cfbeb9441f5058feec8f790ef90d9299a448 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Mon, 30 Apr 2012 16:21:37 +0000
> Subject: [PATCH] Input: eeti_ts: pass gpio value instead of IRQ
> 
> The EETI touchscreen asserts its IRQ line as soon as it has data in its
> internal buffers. The line is automatically deasserted once all data has
> been read via I2C. Hence, the driver has to monitor the GPIO line and
> cannot simply rely on the interrupt handler reception.
> 
> In the current implementation of the driver, irq_to_gpio() is used to
> determine the GPIO number from the i2c_client's IRQ value.
> 
> As irq_to_gpio() is not available on all platforms, this patch changes
> this and makes the driver ignore the passed in IRQ. Instead, a GPIO is
> added to the platform_data struct and gpio_to_irq is used to derive the
> IRQ from that GPIO. If this fails, bail out. The driver is only able to
> work in environments where the touchscreen GPIO can be mapped to an
> IRQ.
> 
> Without this patch, building raumfeld_defconfig results in:
> 
> drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
> drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]
> 
> Signed-off-by: Daniel Mack <zonque at gmail.com>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: stable at vger.kernel.org (v3.2+)
> Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
> Cc: Sven Neumann <s.neumann at raumfeld.com>
> Cc: linux-input at vger.kernel.org
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> 
> diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
> index 5905ed1..d89d87ae 100644
> --- a/arch/arm/mach-pxa/raumfeld.c
> +++ b/arch/arm/mach-pxa/raumfeld.c
> @@ -953,12 +953,12 @@ static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
>  
>  static struct eeti_ts_platform_data eeti_ts_pdata = {
>  	.irq_active_high = 1,
> +	.irq_gpio = GPIO_TOUCH_IRQ,
>  };
>  
>  static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
>  	.type	= "eeti_ts",
>  	.addr	= 0x0a,
> -	.irq	= PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
>  	.platform_data = &eeti_ts_pdata,
>  };
>  
> diff --git a/drivers/input/touchscreen/eeti_ts.c b/drivers/input/touchscreen/eeti_ts.c
> index 503c709..908407e 100644
> --- a/drivers/input/touchscreen/eeti_ts.c
> +++ b/drivers/input/touchscreen/eeti_ts.c
> @@ -48,7 +48,7 @@ struct eeti_ts_priv {
>  	struct input_dev *input;
>  	struct work_struct work;
>  	struct mutex mutex;
> -	int irq, irq_active_high;
> +	int irq_gpio, irq, irq_active_high;
>  };
>  
>  #define EETI_TS_BITDEPTH	(11)
> @@ -62,7 +62,7 @@ struct eeti_ts_priv {
>  
>  static inline int eeti_ts_irq_active(struct eeti_ts_priv *priv)
>  {
> -	return gpio_get_value(irq_to_gpio(priv->irq)) == priv->irq_active_high;
> +	return gpio_get_value(priv->irq_gpio) == priv->irq_active_high;
>  }
>  
>  static void eeti_ts_read(struct work_struct *work)
> @@ -157,7 +157,7 @@ static void eeti_ts_close(struct input_dev *dev)
>  static int __devinit eeti_ts_probe(struct i2c_client *client,
>  				   const struct i2c_device_id *idp)
>  {
> -	struct eeti_ts_platform_data *pdata;
> +	struct eeti_ts_platform_data *pdata = client->dev.platform_data;
>  	struct eeti_ts_priv *priv;
>  	struct input_dev *input;
>  	unsigned int irq_flags;
> @@ -199,9 +199,12 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
>  
>  	priv->client = client;
>  	priv->input = input;
> -	priv->irq = client->irq;
> +	priv->irq_gpio = pdata->irq_gpio;
> +	priv->irq = gpio_to_irq(pdata->irq_gpio);
>  
> -	pdata = client->dev.platform_data;
> +	err = gpio_request_one(pdata->irq_gpio, GPIOF_IN, client->name);
> +	if (err < 0)
> +		goto err1;
>  
>  	if (pdata)
>  		priv->irq_active_high = pdata->irq_active_high;
> @@ -215,13 +218,13 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
>  
>  	err = input_register_device(input);
>  	if (err)
> -		goto err1;
> +		goto err2;
>  
>  	err = request_irq(priv->irq, eeti_ts_isr, irq_flags,
>  			  client->name, priv);
>  	if (err) {
>  		dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
> -		goto err2;
> +		goto err3;
>  	}
>  
>  	/*
> @@ -233,9 +236,11 @@ static int __devinit eeti_ts_probe(struct i2c_client *client,
>  	device_init_wakeup(&client->dev, 0);
>  	return 0;
>  
> -err2:
> +err3:
>  	input_unregister_device(input);
>  	input = NULL; /* so we dont try to free it below */
> +err2:
> +	gpio_free(pdata->irq_gpio);
>  err1:
>  	input_free_device(input);
>  	kfree(priv);
> diff --git a/include/linux/input/eeti_ts.h b/include/linux/input/eeti_ts.h
> index f875b31..16625d7 100644
> --- a/include/linux/input/eeti_ts.h
> +++ b/include/linux/input/eeti_ts.h
> @@ -2,6 +2,7 @@
>  #define LINUX_INPUT_EETI_TS_H
>  
>  struct eeti_ts_platform_data {
> +	int irq_gpio;
>  	unsigned int irq_active_high;
>  };
>  
> 



From tony at atomide.com  Wed Aug  8 10:23:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 07:23:10 -0700
Subject: [PATCH] omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX
 are selected
In-Reply-To: <1344356985-21801-1-git-send-email-jlu@pengutronix.de>
References: <1344356985-21801-1-git-send-email-jlu@pengutronix.de>
Message-ID: <20120808142309.GH11011@atomide.com>

* Jan Luebbe <jlu at pengutronix.de> [120807 09:30]:
> When only ARCH_OMAP3 (or -2,-4,...) and SOC_AM33XX are selected, multi.h
> doesn't set MULTI_OMAP2. In this case, cpu.h will simply define
> cpu_is_omap24xx() as 1.
> 
> This causes problems for example for omap_hwmod.c:omap_hwmod_init which
> checks for cpu_is_omap24xx() first, using the wrong soc_ops for AM33xx.
> 
> Fix this by defining MULTI_OMAP2 when using SOC_AM33XX together with
> something else.

Thanks applying into fixes.

Tony


From tony at atomide.com  Wed Aug  8 10:24:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 07:24:54 -0700
Subject: [PATCH-V3] ARM: OMAP2+: cpu: Add am33xx device under
 cpu_class_is_omap2
In-Reply-To: <1344348841-19868-1-git-send-email-hvaibhav@ti.com>
References: <1344348841-19868-1-git-send-email-hvaibhav@ti.com>
Message-ID: <20120808142453.GI11011@atomide.com>

* Vaibhav Hiremath <hvaibhav at ti.com> [120807 07:15]:
> AM33XX device falls under omap2 class, so make cpu_class_is_omap2()
> macro true by adding soc_is_am33xx() to existing list of cpu/soc
> check.
> This is required to unblock the basic boot support on AM335x platform.
> 
> Having done that, we still need to sort out properly from
> common zImage point of view without having to maintain this
> cpu/soc_is_xxx list.

Thanks applying into fixes.

Tony


From linus.walleij at linaro.org  Wed Aug  8 10:28:24 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 8 Aug 2012 16:28:24 +0200
Subject: [rtc-linux] [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for
 arch-vt8500
In-Reply-To: <201208080919.52592.arnd@arndb.de>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
 <CACRpkdbYxpN9RCu8j8KMBgrb=-DsYZHq7hx-ifmHhJ0ZZcRYjw@mail.gmail.com>
 <201208080919.52592.arnd@arndb.de>
Message-ID: <CACRpkdabUWpDsBhz4ZEJNhEuqw-U+v-HrX7NcWoNLeuenv5t9A@mail.gmail.com>

On Wed, Aug 8, 2012 at 11:19 AM, Arnd Bergmann <arnd at arndb.de> wrote:

>> What on earth are all those magic numbers?
>>
>> I *guess* they're enabling some default GPIO settings etc.
>
> No, they are the register offsets you quoted above, per bank.

Aha I was fooled by this:

+struct vt8500_gpio_bank_regs {
+       int     en;
+       int     dir;
+       int     data_out;
+       int     data_in;
+       int     ngpio;
+};

This needs to be named something intuitive like "vt8500_gpio_bank_regoffsets"

Some kerneldoc intsead of the opaque comment above will also improve
readability a lot:

/**
  * struct vt8500_gpio_bank_regoffsets
  * @en: offset to enable register in the bank
  * ...

Yours,
Linus Walleij


From festevam at gmail.com  Wed Aug  8 10:28:07 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  8 Aug 2012 11:28:07 -0300
Subject: [PATCH] ARM: dts: imx: Move SDMA firmware to SoC dtsi file
Message-ID: <1344436087-5612-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Instead of adding sdma-ram-script-name into each board dts file, move 
it to the SoC dtsi file instead.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx51-babbage.dts |    4 ----
 arch/arm/boot/dts/imx51.dtsi        |    1 +
 arch/arm/boot/dts/imx53-ard.dts     |    6 ------
 arch/arm/boot/dts/imx53-evk.dts     |    4 ----
 arch/arm/boot/dts/imx53-qsb.dts     |    4 ----
 arch/arm/boot/dts/imx53-smd.dts     |    4 ----
 arch/arm/boot/dts/imx53.dtsi        |    1 +
 7 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index de065b5..46d4c93 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -189,10 +189,6 @@
 		};
 
 		aips at 80000000 {	/* aips-2 */
-			sdma at 83fb0000 {
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
-			};
-
 			i2c at 83fc4000 { /* I2C2 */
 				status = "okay";
 
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aaa0c0a..0bb5958 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -219,6 +219,7 @@
 				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 				reg = <0x83fb0000 0x4000>;
 				interrupts = <6>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 			};
 
 			cspi at 83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 5b8eafc..dbe0353 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -44,12 +44,6 @@
 				status = "okay";
 			};
 		};
-
-		aips at 60000000 {	/* AIPS2 */
-			sdma at 63fb0000 {
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-			};
-		};
 	};
 
 	eim-cs1 at f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c79803..8e72f68 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -77,10 +77,6 @@
 		};
 
 		aips at 60000000 {	/* AIPS2 */
-			sdma at 63fb0000 {
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-			};
-
 			i2c at 63fc4000 { /* I2C2 */
 				status = "okay";
 
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9..7153aa0 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -56,10 +56,6 @@
 		};
 
 		aips at 60000000 {	/* AIPS2 */
-			sdma at 63fb0000 {
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-			};
-
 			i2c at 63fc4000 { /* I2C2 */
 				status = "okay";
 
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 0809102..9baef00 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -96,10 +96,6 @@
 		};
 
 		aips at 60000000 {	/* AIPS2 */
-			sdma at 63fb0000 {
-				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-			};
-
 			i2c at 63fc4000 { /* I2C2 */
 				status = "okay";
 
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index dc00c62..81abfad 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -277,6 +277,7 @@
 				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 				reg = <0x63fb0000 0x4000>;
 				interrupts = <6>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 			};
 
 			cspi at 63fc0000 {
-- 
1.7.1



From shawn.guo at linaro.org  Wed Aug  8 10:30:07 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 Aug 2012 22:30:07 +0800
Subject: [PATCH v2 3/4] regulator: add a new API
 regulator_set_voltage_tol()
In-Reply-To: <20120808133540.GB16861@opensource.wolfsonmicro.com>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-4-git-send-email-shawn.guo@linaro.org>
 <20120808133540.GB16861@opensource.wolfsonmicro.com>
Message-ID: <20120808143004.GB14718@S2101-09.ap.freescale.net>

On Wed, Aug 08, 2012 at 02:35:40PM +0100, Mark Brown wrote:
> Applied, thanks!  It's on a separate branch so can easily be either
> applied somewhere else or merged into another tree if required for
> dependencies, just let me know.

I intended to have the whole series go via cpufreq tree with your ack
on this patch.  But I could also ask Rafael to merge your branch to
resolve the dependency.

-- 
Regards,
Shawn



From peter.ujfalusi at ti.com  Wed Aug  8 10:31:19 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 17:31:19 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120808141849.GA24328@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com>
Message-ID: <50227837.10400@ti.com>

On 08/08/2012 05:18 PM, Mark Brown wrote:
> I'm struggling to see any reason not to just hold the external mute on
> for the entire time the headset is powered off?

I think because it would mean in most cases that we keep a GPIO line enabled
during the time the HS is not in use, which burns power.
In most cases the mute is enabled when the GPIO line is up.

>> If you are OK with the hassle I can add a patch to the series for
>> include/linux/of.h to handle this.
> 
> Yes, please.

I'll wait for more comments and I'll include it to v2.

-- 
P?ter


From arnd at arndb.de  Wed Aug  8 10:34:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 14:34:55 +0000
Subject: [PATCH 4/6] ARM: s3c24xx: use new PWM driver
In-Reply-To: <0b6801cd7567$29be48b0$7d3ada10$%kim@samsung.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-5-git-send-email-arnd@arndb.de>
 <0b6801cd7567$29be48b0$7d3ada10$%kim@samsung.com>
Message-ID: <201208081434.56198.arnd@arndb.de>

On Wednesday 08 August 2012, Kukjin Kim wrote:

> diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
> index e249611..d56b0f7 100644
> --- a/arch/arm/mach-s3c24xx/Kconfig
> +++ b/arch/arm/mach-s3c24xx/Kconfig
> @@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
>  	select I2C
>  	select POWER_SUPPLY
>  	select MACH_NEO1973
> -	select S3C2410_PWM
> +	select S3C24XX_PWM
>  	select S3C_DEV_USB_HOST
>  	help
>  	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM
> Phone
> @@ -493,7 +493,7 @@ config MACH_RX1950
>  	select S3C24XX_DCLK
>  	select PM_H1940 if PM
>  	select I2C
> -	select S3C2410_PWM
> +	select S3C24XX_PWM
>  	select S3C_DEV_NAND
>  	select S3C2410_IOTIMING if S3C2440_CPUFREQ
>  	select S3C2440_XTAL_16934400
> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
> index 7aca31c..dcdfb77 100644
> --- a/arch/arm/plat-samsung/Kconfig
> +++ b/arch/arm/plat-samsung/Kconfig
> @@ -403,7 +403,7 @@ config S5P_DEV_USB_EHCI
>  
>  config S3C24XX_PWM
>  	bool "PWM device support"
> -	select HAVE_PWM
> +	select PWM
>  	help
>  	  Support for exporting the PWM timer blocks via the pwm device
>  	  system
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 8fc3808..c74d055 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -58,14 +58,12 @@ config PWM_PXA
>  	  will be called pwm-pxa.
>  
>  config PWM_SAMSUNG
> -	tristate "Samsung pwm support"
> +	bool "Samsung PWM support"
>  	depends on PLAT_SAMSUNG
> +	default y
>  	help
>  	  Generic PWM framework driver for Samsung.
>  
> -	  To compile this driver as a module, choose M here: the module
> -	  will be called pwm-samsung.
> -
>  config PWM_TEGRA
>  	tristate "NVIDIA Tegra PWM support"
>  	depends on ARCH_TEGRA

This approach has two disadvantages compared to mine:

* When building for the samsung platforms other than rx1950 or gta02,
  you can no longer have the PWM driver as a loadable module, for no
  good reason.

* It is still possible to manually disable PWM_SAMSUNG, even on
  rx1950 and gta02, because the Kconfig symbol is visible.

I've added a "Reported-by: Tushar Behera <tushar.behera at linaro.org>"
line to my version of the patch, but I would prefer to keep that
approach. I have also changed the patch to use the S3C24XX_PWM
symbol because that lets everyone migrate the defconfig files.

Do you want to give this patch some more testing, or should I keep
it in arm-soc?

	Arnd
---
From 438b0cf94adb2528bdeeb71314f7be16512ea5b1 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Sat, 4 Aug 2012 07:52:19 +0000
Subject: [PATCH] ARM: s3c24xx: use new PWM driver

The samsung PWM driver has moved to the new PWM subsystem, which
changed the Kconfig symbol for that driver, but the rx1950 and
gta02 boards still uses the old one.

Without this patch, building s3c2410_defconfig results in:

arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_lcd_power':
arch/arm/mach-s3c24xx/mach-rx1950.c:430: undefined reference to `pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:431: undefined reference to `pwm_disable'
arch/arm/mach-s3c24xx/mach-rx1950.c:437: undefined reference to `pwm_config'
arch/arm/mach-s3c24xx/mach-rx1950.c:438: undefined reference to `pwm_enable'
arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_exit':
arch/arm/mach-s3c24xx/mach-rx1950.c:504: undefined reference to `pwm_free'
arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_init':
arch/arm/mach-s3c24xx/mach-rx1950.c:487: undefined reference to `pwm_request'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Reported-by: Tushar Behera <tushar.behera at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e249611..d56b0f7 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
 	select I2C
 	select POWER_SUPPLY
 	select MACH_NEO1973
-	select S3C2410_PWM
+	select S3C24XX_PWM
 	select S3C_DEV_USB_HOST
 	help
 	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
@@ -493,7 +493,7 @@ config MACH_RX1950
 	select S3C24XX_DCLK
 	select PM_H1940 if PM
 	select I2C
-	select S3C2410_PWM
+	select S3C24XX_PWM
 	select S3C_DEV_NAND
 	select S3C2410_IOTIMING if S3C2440_CPUFREQ
 	select S3C2440_XTAL_16934400
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 7aca31c..9c3b90c 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -403,7 +403,8 @@ config S5P_DEV_USB_EHCI
 
 config S3C24XX_PWM
 	bool "PWM device support"
-	select HAVE_PWM
+	select PWM
+	select PWM_SAMSUNG
 	help
 	  Support for exporting the PWM timer blocks via the pwm device
 	  system



From peter.ujfalusi at ti.com  Wed Aug  8 10:35:34 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 08 Aug 2012 17:35:34 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120808125252.GR16861@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <5022529D.3090406@ti.com>
 <20120808125252.GR16861@opensource.wolfsonmicro.com>
Message-ID: <50227936.3040701@ti.com>

On 08/08/2012 03:52 PM, Mark Brown wrote:
> On Wed, Aug 08, 2012 at 01:50:53PM +0200, Benoit Cousson wrote:
> 
>> That being said, since we do have the clock binding now, maybe we should
>> create a clock provider at board level for the sys_clk and thus you will
>> just have to create a phandle to it in your audio description.
> 
> Yes, we should be doing this.

Does this needs the common clock framework on the platform? OMAP3 certainly
does not have it enabled since it has not been adopted.

-- 
P?ter


From arnd at arndb.de  Wed Aug  8 10:38:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 14:38:04 +0000
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <50227615.1090907@gmail.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <201208081419.17181.arnd@arndb.de> <50227615.1090907@gmail.com>
Message-ID: <201208081438.04931.arnd@arndb.de>

On Wednesday 08 August 2012, Daniel Mack wrote:
> > 
> > I've taken your patch instead now, 
> 
> Will that go to some other tree than linux-input now?

I have it in the arm-soc tree for now, but I don't really care
which tree it goes through, as long as it does. I've kept a
version of this patch in one branch with random fixes that
I try to clear out now.

Other than that, I'm fine with whatever Dmitry prefers.

	Arnd


From tony at atomide.com  Wed Aug  8 10:39:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 07:39:30 -0700
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system
 control driver
In-Reply-To: <20120808141051.GG11011@atomide.com>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com>
 <20120808141051.GG11011@atomide.com>
Message-ID: <20120808143929.GJ11011@atomide.com>

* Tony Lindgren <tony at atomide.com> [120808 07:11]:
> * Tony Lindgren <tony at atomide.com> [120808 07:05]:
> > * Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120725 04:10]:
> > > +
> > > +u32 omap_control_status_read(void)
> > > +{
> > > +	return __raw_readl(omap_control_base);
> > > +}
> > 
> > Ah OK it's changed here.. Sorry I was looking at the older
> > version.
> > 
> > > +void __init of_omap_control_init(const struct of_device_id *matches)
> > > +{
> > > +	struct device_node *np;
> > > +	struct property *pp = 0;
> > > +
> > > +	for_each_matching_node(np, matches) {
> > > +		pp = of_find_property(np, "reg", NULL);
> > > +		if(pp) {
> > > +			omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
> > > +			omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
> > > +			/*
> > > +			 * Map control module register CONTROL_STATUS register:
> > > +			 * omap24xx - OMAP24XX_CONTROL_STATUS
> > > +			 * am33xx   - AM33XX_CONTROL_STATUS
> > > +			 * omap34xx - OMAP343X_CONTROL_STATUS
> > > +			 * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
> > > +			 * omap54xx - OMAP5XXX_CONTROL_STATUS
> > > +			 */
> > > +			omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
> > > +		}
> > > +	}
> > > +}
> > 
> > You should probably add a function for setting omap_control_base
> > separately from *set_globals* in arch/arm/mach-omap2/common.c.
> > That way it's initialized early for id.c, and you can initialize
> > everything else later as regular device drivers.
> > 
> > FYI, we want to initialize as much as possible late so we have
> > proper debugging console set up in case things go wrong.
> 
> Hmm it seems that omap_control_base is now only initialized for DT boot
> case? This will break booting on almost all systems..

Looking at things more, looks like omap_type() is getting called
early from timer.c. So maybe just let set_globals initialize
omap_control_base and let omap_type() read that directly. That way
the SCM core driver can behave like a regular device driver and it
does not need to be initialized early.

Regards,

Tony


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 10:39:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 15:39:27 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <50227936.3040701@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <5022529D.3090406@ti.com>
 <20120808125252.GR16861@opensource.wolfsonmicro.com>
 <50227936.3040701@ti.com>
Message-ID: <20120808143927.GB24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 05:35:34PM +0300, Peter Ujfalusi wrote:

> Does this needs the common clock framework on the platform? OMAP3 certainly
> does not have it enabled since it has not been adopted.

I'd hope at least the binding code for finding clocks has been done at
the clkdev level so it can be used on other platforms but perhaps that's
not the case.


From shawn.guo at linaro.org  Wed Aug  8 10:41:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 Aug 2012 22:41:51 +0800
Subject: [PATCH 1/6] ARM: mxs: tx28: reset fec phy for device tree boot
In-Reply-To: <201208071915.26932.arnd@arndb.de>
References: <1344267769-31166-1-git-send-email-shawn.guo@linaro.org>
 <1344267769-31166-2-git-send-email-shawn.guo@linaro.org>
 <201208071915.26932.arnd@arndb.de>
Message-ID: <20120808144148.GC14718@S2101-09.ap.freescale.net>

On Tue, Aug 07, 2012 at 07:15:25PM +0000, Arnd Bergmann wrote:
> > +       /* Power up fec phy */
> > +       gpio_set_value(TX28_FEC_PHY_POWER, 1);
> > +       mdelay(26); /* 25ms according to data sheet */
> 
> 26 ms is a long time for a delay. I think you should use msleep here.
> 
I copied this from TX28 board file.  But I just changed it per your
comment.  Thanks.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Wed Aug  8 10:43:39 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 Aug 2012 22:43:39 +0800
Subject: [PATCH 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120808085956.GB25520@pengutronix.de>
References: <1343922986-32469-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120803131230.GB23791@S2101-09.ap.freescale.net>
 <20120808085956.GB25520@pengutronix.de>
Message-ID: <20120808144337.GD14718@S2101-09.ap.freescale.net>

On Wed, Aug 08, 2012 at 10:59:56AM +0200, Uwe Kleine-K?nig wrote:
> $ git grep fsl,imx3[15]-gpio drivers/gpio
> drivers/gpio/gpio-mxc.c:        { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
> 
Try it on v3.6-rc1.

-- 
Regards,
Shawn



From arnd at arndb.de  Wed Aug  8 10:47:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:26 +0200
Subject: [PATCH 09/11] regulator/twl: remove fixed resource handling
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-10-git-send-email-arnd@arndb.de>

The recent patch 0e8e5c34cf "regulator: twl: Remove references to
32kHz clock from DT bindings" removed the only use of the fake
"CLK32KG" regulator but not the TWL6030_FIXED_RESOURCE and
twl6030_fixed_resource definitions that are unused otherwise.

Without this patch, building omap2plus_defconfig results in:

drivers/regulator/twl-regulator.c:1051:27: warning: 'TWLRES_INFO_CLK32KG' defined but not used [-Wunused-variable]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/regulator/twl-regulator.c |   21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/drivers/regulator/twl-regulator.c b/drivers/regulator/twl-regulator.c
index 242fe90..514a84b 100644
--- a/drivers/regulator/twl-regulator.c
+++ b/drivers/regulator/twl-regulator.c
@@ -659,13 +659,6 @@ static struct regulator_ops twl6030fixed_ops = {
 	.get_status	= twl6030reg_get_status,
 };
 
-static struct regulator_ops twl6030_fixed_resource = {
-	.enable		= twl6030reg_enable,
-	.disable	= twl6030reg_disable,
-	.is_enabled	= twl6030reg_is_enabled,
-	.get_status	= twl6030reg_get_status,
-};
-
 /*
  * SMPS status and control
  */
@@ -967,19 +960,6 @@ static struct twlreg_info TWLFIXED_INFO_##label = { \
 		}, \
 	}
 
-#define TWL6030_FIXED_RESOURCE(label, offset, turnon_delay) \
-static struct twlreg_info TWLRES_INFO_##label = { \
-	.base = offset, \
-	.desc = { \
-		.name = #label, \
-		.id = TWL6030_REG_##label, \
-		.ops = &twl6030_fixed_resource, \
-		.type = REGULATOR_VOLTAGE, \
-		.owner = THIS_MODULE, \
-		.enable_time = turnon_delay, \
-		}, \
-	}
-
 #define TWL6025_ADJUSTABLE_SMPS(label, offset) \
 static struct twlreg_info TWLSMPS_INFO_##label = { \
 	.base = offset, \
@@ -1048,7 +1028,6 @@ TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 0);
 TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 0);
 TWL6030_FIXED_LDO(V1V8, 0x16, 1800, 0);
 TWL6030_FIXED_LDO(V2V1, 0x1c, 2100, 0);
-TWL6030_FIXED_RESOURCE(CLK32KG, 0x8C, 0);
 TWL6025_ADJUSTABLE_SMPS(SMPS3, 0x34);
 TWL6025_ADJUSTABLE_SMPS(SMPS4, 0x10);
 TWL6025_ADJUSTABLE_SMPS(VIO, 0x16);
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:27 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:27 +0200
Subject: [PATCH 10/11] spi/s3c64xx: improve error handling
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-11-git-send-email-arnd@arndb.de>

When a device tree definition os an s3c64xx SPI master is missing
a "controller-data" subnode, the newly added s3c64xx_get_slave_ctrldata
function might use uninitialized memory in place of that node,
which was correctly reported by gcc.

Without this patch, building s3c6400_defconfig results in:

drivers/spi/spi-s3c64xx.c: In function 's3c64xx_get_slave_ctrldata.isra.25':
drivers/spi/spi-s3c64xx.c:841:5: warning: 'data_np' may be used uninitialized in this function [-Wuninitialized]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Jaswinder Singh <jaswinder.singh at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/spi/spi-s3c64xx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 646a765..cfa2c35 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -826,7 +826,7 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 				struct spi_device *spi)
 {
 	struct s3c64xx_spi_csinfo *cs;
-	struct device_node *slave_np, *data_np;
+	struct device_node *slave_np, *data_np = NULL;
 	u32 fb_delay = 0;
 
 	slave_np = spi->dev.of_node;
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:23 +0200
Subject: [PATCH 06/11] gpio: em: do not discard em_gio_irq_domain_cleanup
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-7-git-send-email-arnd@arndb.de>

The newly added gpio-em driver marks its em_gio_irq_domain_cleanup
function as __devexit, which would lead to that function being
discarded in case CONFIG_HOTPLUG is disabled. However, the function
is also called by the error handling logic em_gio_probe, which
would cause a jump into a NULL pointer if it was removed from the
kernel or module.

Without this patch, building kzm9d_defconfig results in:

WARNING: drivers/gpio/built-in.o(.devinit.text+0x330): Section mismatch in reference from the function em_gio_probe() to the function .devexit.text:em_gio_irq_domain_cleanup()
The function __devinit em_gio_probe() references
a function __devexit em_gio_irq_domain_cleanup().
This is often seen when error handling in the init function
uses functionality in the exit path.
The fix is often to remove the __devexit annotation of
em_gio_irq_domain_cleanup() so it may be used outside an exit section.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Magnus Damm <damm at opensource.se>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
---
 drivers/gpio/gpio-em.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
index 150d976..ae37181 100644
--- a/drivers/gpio/gpio-em.c
+++ b/drivers/gpio/gpio-em.c
@@ -266,7 +266,7 @@ static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p)
 	return 0;
 }
 
-static void __devexit em_gio_irq_domain_cleanup(struct em_gio_priv *p)
+static void em_gio_irq_domain_cleanup(struct em_gio_priv *p)
 {
 	struct gpio_em_config *pdata = p->pdev->dev.platform_data;
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:19 +0200
Subject: [PATCH 02/11] mfd/asic3: fix asic3_mfd_probe return value
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-3-git-send-email-arnd@arndb.de>

In commit 4f304245b "mfd: Set asic3 DS1WM clock_rate", a possible
path through asic3_mfd_probe was introduced that would lead to
an unpredictable return value, if everything succeeds but there
are pdata->leds is NULL. This was reported correctly by gcc.

Without this patch, building magician_defconfig results in:

drivers/mfd/asic3.c: In function 'asic3_mfd_probe':
drivers/mfd/asic3.c:940:2: warning: 'ret' may be used uninitialized in this function [-Wuninitialized]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Paul Parsons <lost.distance at yahoo.com>
Cc: Philipp Zabel <philipp.zabel at gmail.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
---
 drivers/mfd/asic3.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 383421b..683e18a 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -925,6 +925,7 @@ static int __init asic3_mfd_probe(struct platform_device *pdev,
 			goto out;
 	}
 
+	ret = 0;
 	if (pdata->leds) {
 		int i;
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:21 +0200
Subject: [PATCH 04/11] ARM: ux500: really kill snowball_of_platform_devs
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-5-git-send-email-arnd@arndb.de>

Commit fc67a597a "ARM: ux500: Remove temporary snowball_of_platform_devs
enablement structure" removed the only user of this variable, but did
not actually remove the array itself.

Without this patch, building u8500_defconfig results in:

arch/arm/mach-ux500/board-mop500.c:729:32: warning: 'snowball_of_platform_devs' defined but not used [-Wunused-variable]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Lee Jones <lee.jones at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8674a89..2a732f7 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -726,11 +726,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-	&snowball_led_dev,
-	&snowball_key_dev,
-};
-
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires DMA and call-back bindings. */
 	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:24 +0200
Subject: [PATCH 07/11] net/stmmac: mark probe function as __devinit
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-8-git-send-email-arnd@arndb.de>

Driver probe functions are generally __devinit so they will be
discarded after initialization for non-hotplug kernels.
This was found by a new warning after patch 6a228452d "stmmac: Add
device-tree support" adds a new __devinit function that is called
from stmmac_pltfr_probe.

Without this patch, building socfpga_defconfig results in:

WARNING: drivers/net/ethernet/stmicro/stmmac/stmmac.o(.text+0x5d4c): Section mismatch in reference from the function stmmac_pltfr_probe() to the function .devinit.text:stmmac_probe_config_dt()
The function stmmac_pltfr_probe() references
the function __devinit stmmac_probe_config_dt().
This is often because stmmac_pltfr_probe lacks a __devinit
annotation or the annotation of stmmac_probe_config_dt is wrong.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Stefan Roese <sr at denx.de>
Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
Cc: David S. Miller <davem at davemloft.net>
Cc: netdev at vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index cd01ee7..b93245c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -74,7 +74,7 @@ static int __devinit stmmac_probe_config_dt(struct platform_device *pdev,
  * the necessary resources and invokes the main to init
  * the net device, register the mdio bus etc.
  */
-static int stmmac_pltfr_probe(struct platform_device *pdev)
+static int __devinit stmmac_pltfr_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct resource *res;
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:25 +0200
Subject: [PATCH 08/11] mtd/omap2: fix dmaengine_slave_config error handling
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-9-git-send-email-arnd@arndb.de>

The newly added dmaengine support in the omap2 nand driver
potentially causes an undefined return value from the
omap_nand_probe function when dmaengine_slave_config
reports an error. Let's handle this by returning the
same error back to the caller.

Without this patch, building omap2plus_defconfig results in:

drivers/mtd/nand/omap2.c: In function 'omap_nand_probe':
drivers/mtd/nand/omap2.c:1154:6: warning: 'err' may be used uninitialized in this function [-Wuninitialized]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Grazvydas Ignotas <notasas at gmail.com>
---
 drivers/mtd/nand/omap2.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index e9309b3..ac4fd75 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1245,7 +1245,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 			goto out_release_mem_region;
 		} else {
 			struct dma_slave_config cfg;
-			int rc;
 
 			memset(&cfg, 0, sizeof(cfg));
 			cfg.src_addr = info->phys_base;
@@ -1254,10 +1253,10 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 			cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 			cfg.src_maxburst = 16;
 			cfg.dst_maxburst = 16;
-			rc = dmaengine_slave_config(info->dma, &cfg);
-			if (rc) {
+			err = dmaengine_slave_config(info->dma, &cfg);
+			if (err) {
 				dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
-					rc);
+					err);
 				goto out_release_mem_region;
 			}
 			info->nand.read_buf   = omap_read_buf_dma_pref;
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:18 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:18 +0200
Subject: [PATCH 01/11] ARM: topology: mark init_cpu_topology as __init
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-2-git-send-email-arnd@arndb.de>

The init_cpu_topology function can be put into the __init section
and discarded after boot, because it is only called from
smp_prepare_cpus, which is also marked __init. This was reported
by gcc after Vincent Guittot added the parse_dt_topology function
in 339ca09d7ada "ARM: 7463/1: topology: Update cpu_power according to DT
information".

Without this patch, building kzm9g_defconfig results in:

WARNING: vmlinux.o(.text+0xb5a0): Section mismatch in reference from the function init_cpu_topology() to the function .init.text:parse_dt_topology()
The function init_cpu_topology() references
the function __init parse_dt_topology().
This is often because init_cpu_topology lacks a __init
annotation or the annotation of parse_dt_topology is wrong.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Vincent Guittot <vincent.guittot at linaro.org>
Cc: Namhyung Kim <namhyung at kernel.org>
Cc: Peter Zijlstra <a.p.zijlstra at chello.nl>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/kernel/topology.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 198b084..26c12c6 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -321,7 +321,7 @@ void store_cpu_topology(unsigned int cpuid)
  * init_cpu_topology is called at boot when only one cpu is running
  * which prevent simultaneous write access to cpu_topology array
  */
-void init_cpu_topology(void)
+void __init init_cpu_topology(void)
 {
 	unsigned int cpu;
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:22 +0200
Subject: [PATCH 05/11] ARM: exynos: exynos_pm_add_dev_to_genpd may be unused
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-6-git-send-email-arnd@arndb.de>

exynos_pm_add_dev_to_genpd is used if one or more out of a large
number of Kconfig symbols are enabled. However the new
exynos_defconfig selects none of those, so the function becomes
unused. Marking it so lets the compiler automatically discard
it.

Without this patch, building exynos_defconfig results in:

arch/arm/mach-exynos/pm_domains.c:118:123: warning: 'exynos_pm_add_dev_to_genpd' defined but not used [-Wunused-function]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/pm_domains.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 373c3c0..c0bc83a 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -115,7 +115,7 @@ static __init int exynos_pm_dt_parse_domains(void)
 }
 #endif /* CONFIG_OF */
 
-static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
+static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
 						struct exynos_pm_domain *pd)
 {
 	if (pdev->dev.bus) {
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:17 +0200
Subject: [PATCH 00/11] recently added ARM defconfig warnings
Message-ID: <1344437248-20560-1-git-send-email-arnd@arndb.de>

These patches address problems that showed up in new warnings
when building all ARM defconfig files in v3.6-rc1 compared
with v3.5.

I can merge them through the arm-soc tree or have subsystem
maintainers pick them up if they prefer.

Arnd Bergmann (11):
  ARM: topology: mark init_cpu_topology as __init
  mfd/asic3: fix asic3_mfd_probe return value
  usb/ohci-omap: remove unused variable
  ARM: ux500: really kill snowball_of_platform_devs
  ARM: exynos: exynos_pm_add_dev_to_genpd may be unused
  gpio: em: do not discard em_gio_irq_domain_cleanup
  net/stmmac: mark probe function as __devinit
  mtd/omap2: fix dmaengine_slave_config error handling
  regulator/twl: remove fixed resource handling
  spi/s3c64xx: improve error handling
  pm/drivers: fix use of SIMPLE_DEV_PM_OPS

Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: David S. Miller <davem at davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Grazvydas Ignotas <notasas at gmail.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Jaswinder Singh <jaswinder.singh at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Laxman Dewangan <ldewangan at nvidia.com>
Cc: Lee Jones <lee.jones at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Magnus Damm <damm at opensource.se>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Namhyung Kim <namhyung at kernel.org>
Cc: Paul Parsons <lost.distance at yahoo.com>
Cc: Peter Zijlstra <a.p.zijlstra at chello.nl>
Cc: Philipp Zabel <philipp.zabel at gmail.com>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Richard Zhao <richard.zhao at freescale.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Stefan Roese <sr at denx.de>
Cc: Takashi Iwai <tiwai at suse.de>
Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Vincent Guittot <vincent.guittot at linaro.org>
Cc: netdev at vger.kernel.org

 arch/arm/kernel/topology.c                         |    2 +-
 arch/arm/mach-exynos/pm_domains.c                  |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |    5 -----
 drivers/char/hw_random/omap-rng.c                  |    2 +-
 drivers/gpio/gpio-em.c                             |    2 +-
 drivers/i2c/busses/i2c-tegra.c                     |    2 +-
 drivers/mfd/asic3.c                                |    1 +
 drivers/mtd/nand/omap2.c                           |    7 +++----
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |    2 +-
 drivers/regulator/twl-regulator.c                  |   21 --------------------
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/usb/host/ohci-omap.c                       |    2 --
 sound/drivers/dummy.c                              |    2 +-
 13 files changed, 12 insertions(+), 40 deletions(-)

-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:28 +0200
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-12-git-send-email-arnd@arndb.de>

A few drivers use a construct like

 #ifdef CONFIG_PM
 static int foo_suspend(struct device *pdev)
 {
    ...
 }
 static int foo_resume struct device *pdev)
 {
    ...
 }
 #endif
 static SIMPLE_DEV_PM_OPS(foo_pm, foo_suspend, foo_resume);

which leaves the two functions unused if CONFIG_PM is enabled
but CONFIG_PM_SLEEP is disabled. I found this while building
all defconfig files on ARM. It's not clear to me if this is
the right solution, but at least it makes the code consistent
again.

Without this patch, building omap1_defconfig results in:

drivers/char/hw_random/omap-rng.c:165:12: warning: 'omap_rng_suspend' defined but not used [-Wunused-function]
drivers/char/hw_random/omap-rng.c:171:12: warning: 'omap_rng_resume' defined but not used [-Wunused-function]
sound/drivers/dummy.c:1068:12: warning: 'snd_dummy_suspend' defined but not used [-Wunused-function]
sound/drivers/dummy.c:1078:12: warning: 'snd_dummy_resume' defined but not used [-Wunused-function]

and building tegra_defconfig results in:

drivers/i2c/busses/i2c-tegra.c:716:12: warning: 'tegra_i2c_suspend' defined but not used [-Wunused-function]
drivers/i2c/busses/i2c-tegra.c:727:12: warning: 'tegra_i2c_resume' defined but not used [-Wunused-function]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Takashi Iwai <tiwai at suse.de>
Cc: Laxman Dewangan <ldewangan at nvidia.com>
---
 drivers/char/hw_random/omap-rng.c |    2 +-
 drivers/i2c/busses/i2c-tegra.c    |    2 +-
 sound/drivers/dummy.c             |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index d706bd0e..4fbdceb 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -160,7 +160,7 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 
 static int omap_rng_suspend(struct device *dev)
 {
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 66eb53f..9a08c57 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -712,7 +712,7 @@ static int __devexit tegra_i2c_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 static int tegra_i2c_suspend(struct device *dev)
 {
 	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
diff --git a/sound/drivers/dummy.c b/sound/drivers/dummy.c
index f7d3bfc..54bb664 100644
--- a/sound/drivers/dummy.c
+++ b/sound/drivers/dummy.c
@@ -1064,7 +1064,7 @@ static int __devexit snd_dummy_remove(struct platform_device *devptr)
 	return 0;
 }
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 static int snd_dummy_suspend(struct device *pdev)
 {
 	struct snd_card *card = dev_get_drvdata(pdev);
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 10:47:20 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 16:47:20 +0200
Subject: [PATCH 03/11] usb/ohci-omap: remove unused variable
In-Reply-To: <1344437248-20560-1-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344437248-20560-4-git-send-email-arnd@arndb.de>

Commit c2e935a7d "USB: move transceiver from ehci_hcd and ohci_hcd to
hcd and rename it as phy" removed the last use of the "ohci" variable
in the usb_hcd_omap_remove function, but left the variable in place
unused.

Without this patch, building omap1_defconfig results in:

In file included from drivers/usb/host/ohci-hcd.c:1013:0:
drivers/usb/host/ohci-omap.c: In function 'usb_hcd_omap_remove':
drivers/usb/host/ohci-omap.c:406:19: warning: unused variable 'ohci' [-Wunused-variable]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Richard Zhao <richard.zhao at freescale.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
---
 drivers/usb/host/ohci-omap.c |    2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index e7d75d2..f8b2d91 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -403,8 +403,6 @@ err0:
 static inline void
 usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev)
 {
-	struct ohci_hcd		*ohci = hcd_to_ohci (hcd);
-
 	usb_remove_hcd(hcd);
 	if (!IS_ERR_OR_NULL(hcd->phy)) {
 		(void) otg_set_host(hcd->phy->otg, 0);
-- 
1.7.10



From mporter at ti.com  Wed Aug  8 10:48:19 2012
From: mporter at ti.com (Porter, Matt)
Date: Wed, 8 Aug 2012 14:48:19 +0000
Subject: [alsa-devel] DT support for Davinci ASoC platform
In-Reply-To: <50226B65.4090804@gmail.com>
References: <1BAFE6F6C881BF42822005164F1491C33EA35352@DBDE01.ent.ti.com>
 <4FF5733E.6000604@gmail.com> <501AE3C6.8040708@gmail.com>
 <501B954C.3070606@ti.com> <50226B65.4090804@gmail.com>
Message-ID: <7AF83341-20F2-4714-A4BB-8A2D4D7238F5@ti.com>


On Aug 8, 2012, at 9:36 AM, Daniel Mack wrote:

> Hi Serkar,
> 
> On 03.08.2012 11:09, Sekhar Nori wrote:
>> On 8/3/2012 2:02 AM, Daniel Mack wrote:
>>> On 05.07.2012 12:58, Daniel Mack wrote:
>>>> Hi Gururaja,
>>>> 
>>>> On 04.07.2012 14:48, Hebbar, Gururaja wrote:
>>>>> All,
>>>>> 
>>>>> Are there any plans or work going on for providing Device Tree Support for Davinci
>>>>> ASoC?
>>>>> 
>>>>> I am planning to add DT support for TI AM335x (McASP) and I don't want to do duplicate
>>>>> task.
>>>> 
>>>> That's good to know. But isn't there a dependency on the EDMA engine? Is
>>>> that part ported yet?
>>> 
>>> May I ask whether you made any progress on that yet?
>> 
>> Matt Porter from TI is working on DMA engine migration. This would still
>> be some time away since there is a bunch of work involved here.
>> 
>> To make progress on Audio DT conversion Gururaja is doing an up port of
>> AM335x EDMA support from TI release to mainline kernel. If you are
>> interested in it, he can probably share that with you once he posts his
>> DT patches.
> 
> As the DMA engine is also a requirement for the MMC controller, I would
> be interested in helping, in case help is required. Is there any
> repository with code that I can have a look at?

I'm just getting to the point now where I *almost* have something to push
to my github repo and post. It'll be Davinci-specific to start since it's
a wrapper around mach-davinci/dma.c and includes only memcpy and SG transfer
type support initially...plus conversions of davinci spi/mmc drivers.

There'll be a bit of work to get the omap-dma.c-dependent channel filtering
removed from the omap hsmmc and mcspi drivers so they can provide a filter
that works with either dmaengine driver. Also, that means DT support for
the actual dmaengine driver too and some glue to configure the crossbar.

I'll copy you when I get this RFC series posted and we can go from there.

-Matt

From broonie at opensource.wolfsonmicro.com  Wed Aug  8 10:49:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 15:49:34 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <50227837.10400@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com>
 <50227837.10400@ti.com>
Message-ID: <20120808144933.GC24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 05:31:19PM +0300, Peter Ujfalusi wrote:
> On 08/08/2012 05:18 PM, Mark Brown wrote:

> > I'm struggling to see any reason not to just hold the external mute on
> > for the entire time the headset is powered off?

> I think because it would mean in most cases that we keep a GPIO line enabled
> during the time the HS is not in use, which burns power.
> In most cases the mute is enabled when the GPIO line is up.

That makes sense if the GPIO is actively driven, open drain should be
better here, but it's still a generic thing which it'd be nice to
extract.

Still, the main thing here was the fact that we should be able to drop
the flag for the feature in the first place.


From broonie at opensource.wolfsonmicro.com  Wed Aug  8 10:50:19 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 8 Aug 2012 15:50:19 +0100
Subject: [PATCH 09/11] regulator/twl: remove fixed resource handling
In-Reply-To: <1344437248-20560-10-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-10-git-send-email-arnd@arndb.de>
Message-ID: <20120808145018.GD24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 04:47:26PM +0200, Arnd Bergmann wrote:
> The recent patch 0e8e5c34cf "regulator: twl: Remove references to
> 32kHz clock from DT bindings" removed the only use of the fake
> "CLK32KG" regulator but not the TWL6030_FIXED_RESOURCE and
> twl6030_fixed_resource definitions that are unused otherwise.

I've already got a fix for this in my tree.

Please do also make an effort to use subject lines that match the style
of the subsystem.


From kbaidarov at dev.rtsoft.ru  Wed Aug  8 10:59:37 2012
From: kbaidarov at dev.rtsoft.ru (Konstantin Baydarov)
Date: Wed, 08 Aug 2012 18:59:37 +0400
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system control
 driver
In-Reply-To: <20120808143929.GJ11011@atomide.com>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com> <20120808141051.GG11011@atomide.com>
 <20120808143929.GJ11011@atomide.com>
Message-ID: <50227ED9.3010508@dev.rtsoft.ru>

  Hi, Tony.

On 08/08/2012 06:39 PM, Tony Lindgren wrote:
> * Tony Lindgren <tony at atomide.com> [120808 07:11]:
>> * Tony Lindgren <tony at atomide.com> [120808 07:05]:
>>> * Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120725 04:10]:
>>>> +
>>>> +u32 omap_control_status_read(void)
>>>> +{
>>>> +	return __raw_readl(omap_control_base);
>>>> +}
>>> Ah OK it's changed here.. Sorry I was looking at the older
>>> version.
>>>
>>>> +void __init of_omap_control_init(const struct of_device_id *matches)
>>>> +{
>>>> +	struct device_node *np;
>>>> +	struct property *pp = 0;
>>>> +
>>>> +	for_each_matching_node(np, matches) {
>>>> +		pp = of_find_property(np, "reg", NULL);
>>>> +		if(pp) {
>>>> +			omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
>>>> +			omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
>>>> +			/*
>>>> +			 * Map control module register CONTROL_STATUS register:
>>>> +			 * omap24xx - OMAP24XX_CONTROL_STATUS
>>>> +			 * am33xx   - AM33XX_CONTROL_STATUS
>>>> +			 * omap34xx - OMAP343X_CONTROL_STATUS
>>>> +			 * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
>>>> +			 * omap54xx - OMAP5XXX_CONTROL_STATUS
>>>> +			 */
>>>> +			omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
>>>> +		}
>>>> +	}
>>>> +}
>>> You should probably add a function for setting omap_control_base
>>> separately from *set_globals* in arch/arm/mach-omap2/common.c.
>>> That way it's initialized early for id.c, and you can initialize
>>> everything else later as regular device drivers.
>>>
>>> FYI, we want to initialize as much as possible late so we have
>>> proper debugging console set up in case things go wrong.
>> Hmm it seems that omap_control_base is now only initialized for DT boot
>> case? This will break booting on almost all systems..
> Looking at things more, looks like omap_type() is getting called
> early from timer.c. So maybe just let set_globals initialize
> omap_control_base and let omap_type() read that directly. That way
> the SCM core driver can behave like a regular device driver and it
> does not need to be initialized early.

  Yes, omap_type() is called very early , that is why I'm using early_initcall for omap_control_base initialization.

Do you mean following?:
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
    if (omap2_globals->ctrl)
        omap2_ctrl_base = omap2_globals->ctrl;

    if (omap2_globals->ctrl_pad)
        omap4_ctrl_pad_base = omap2_globals->ctrl_pad;

    omap_control_base = omap2_ctrl_base;  // this line is added
}

  Or you suggest to move
void __init of_omap_control_init(const struct of_device_id *matches)
{
    struct device_node *np;
    struct property *pp = 0;

    for_each_matching_node(np, matches) {
        pp = of_find_property(np, "reg", NULL);
        if(pp) {
            omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
            omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
            /*
             * Map control module register CONTROL_STATUS register:
             * omap24xx - OMAP24XX_CONTROL_STATUS
             * am33xx   - AM33XX_CONTROL_STATUS
             * omap34xx - OMAP343X_CONTROL_STATUS
             * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
             * omap54xx - OMAP5XXX_CONTROL_STATUS
             */
            omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
        }
    }
}

into omap2_set_globals_control() ?

Also if we move omap_control_base initialization to omap2_set_globals_control(), than the initialization routine of drivers/mfd/omap-control-core.c become empty, because omap_control_base is the only thing that is initialized in omap-control-core driver.

  BR,
    Konstantin Baydarov.

>
> Regards,
>
> Tony
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From gregory.clement at free-electrons.com  Wed Aug  8 11:05:00 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed,  8 Aug 2012 17:05:00 +0200
Subject: [RFC] Add support for Aurora L2 Cache Controller
Message-ID: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

The purpose of this patch set is to add support for Aurora L2 Cache
Controller used by Armada 370 and Armada XP SoCs. As it was initially
designed by Marvell engineer to be compatible with the ARM L2 Cache
Controller, we chose to reuse the existing code and to just extend it
to support the differences and improvements brought by the Aurora
controller.The diffstat looks like:

 Documentation/devicetree/bindings/arm/l2cc.txt  |    9 +
 arch/arm/boot/dts/armada-370.dtsi               |    6 +
 arch/arm/boot/dts/armada-xp.dtsi                |    7 +
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 ++++
 arch/arm/include/asm/hardware/cache-l2x0.h      |    1 +
 arch/arm/mach-mvebu/Kconfig                     |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c         |    4 +
 arch/arm/mm/cache-l2x0.c                        |  297 +++++++++++++++++++++--
 8 files changed, 362 insertions(+), 14 deletions(-)

The main differences and improvements are:

- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller 'outer cache' and 'system cache' (the
  last one meaning maintenance operations on L1 are broadcasted to the
  L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved
  and can be done on a range inside a page and are not limited to a
  cache line.
- during resume the controller need to restore the ctrl register.

The first patch adds some modifications in the driver
infrastructure. As most of the outer cache functions can use the
Aurora improvements, we had to introduce new functions. So we thought
it was better to use a outer_cache_fns field inside l2x0_of_data and
just memcopy it into outer_cache depending of the type of the l2x0
cache.

If the change we have made in the l2x0 driver are judged too invasive
we are perfectly fine to submit a dedicated driver for the Aurora
Cache Controller.

For interested people you can find the results of the cache benchmarks
which was ran for validate the driver:
htps://github.com/MISL-EBU-System-SW/mainline-public/wiki/Cache-bench-results-for-Aurora-L2-cache-controller-on-Armada-XP-and-Armada-370

All the data related to this benchmark are hosted at:
http://free-electrons.com/%7Egregory/pub/Armada-370-xp/cachebench-results/

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Regards,

Gregory



From arnd at arndb.de  Wed Aug  8 11:06:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 15:06:24 +0000
Subject: [PATCH 09/11] regulator/twl: remove fixed resource handling
In-Reply-To: <20120808145018.GD24328@opensource.wolfsonmicro.com>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-10-git-send-email-arnd@arndb.de>
 <20120808145018.GD24328@opensource.wolfsonmicro.com>
Message-ID: <201208081506.24773.arnd@arndb.de>

On Wednesday 08 August 2012, Mark Brown wrote:
> On Wed, Aug 08, 2012 at 04:47:26PM +0200, Arnd Bergmann wrote:
> > The recent patch 0e8e5c34cf "regulator: twl: Remove references to
> > 32kHz clock from DT bindings" removed the only use of the fake
> > "CLK32KG" regulator but not the TWL6030_FIXED_RESOURCE and
> > twl6030_fixed_resource definitions that are unused otherwise.
> 
> I've already got a fix for this in my tree.

Ok, dropping it here.

	Arnd


From sr at denx.de  Wed Aug  8 11:07:21 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 08 Aug 2012 17:07:21 +0200
Subject: [PATCH 07/11] net/stmmac: mark probe function as __devinit
In-Reply-To: <1344437248-20560-8-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-8-git-send-email-arnd@arndb.de>
Message-ID: <502280A9.5070009@denx.de>

On 08/08/2012 04:47 PM, Arnd Bergmann wrote:
> Driver probe functions are generally __devinit so they will be
> discarded after initialization for non-hotplug kernels.
> This was found by a new warning after patch 6a228452d "stmmac: Add
> device-tree support" adds a new __devinit function that is called
> from stmmac_pltfr_probe.
> 
> Without this patch, building socfpga_defconfig results in:
> 
> WARNING: drivers/net/ethernet/stmicro/stmmac/stmmac.o(.text+0x5d4c): Section mismatch in reference from the function stmmac_pltfr_probe() to the function .devinit.text:stmmac_probe_config_dt()
> The function stmmac_pltfr_probe() references
> the function __devinit stmmac_probe_config_dt().
> This is often because stmmac_pltfr_probe lacks a __devinit
> annotation or the annotation of stmmac_probe_config_dt is wrong.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Stefan Roese <sr at denx.de>
> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: netdev at vger.kernel.org

Acked-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan


From shawn.guo at linaro.org  Wed Aug  8 11:15:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 8 Aug 2012 23:15:58 +0800
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
Message-ID: <20120808151555.GE14718@S2101-09.ap.freescale.net>

On Tue, Aug 07, 2012 at 04:46:18PM -0500, Matt Sealey wrote:
> This device tree only supports the final retail board ("TO3").
> 
> It is currently feature equivalent to the MX51 Babbage device tree. The
> following features have been tested and work as well as can be expected:
> 
> * Serial port
> * SD card support
> * I2C bus
> * SGTL5000 audio support via the internal speaker
> * SDMA support (via audio)
> * SPI bus
> * NOR flash (at 25MHz bus speed)
> * MC13892 PMIC Regulator and Realtime clock functions
> 
> Since the board requires some extra work on the PMIC to power off, the system
> will instead just halt, however reboot works. Other missing features are due
> to a lack of drivers or device tree bindings currently.
> 
> Signed-off-by: Matt Sealey <matt at genesi-usa.com>
> Signed-off-by: Steev Klimaszewski <steev at genesi-usa.com>
> ---
>  arch/arm/boot/dts/imx51-efikamx.dts |  247 +++++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/Makefile.boot     |    2 +-
>  2 files changed, 248 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/imx51-efikamx.dts
> 
> diff --git a/arch/arm/boot/dts/imx51-efikamx.dts b/arch/arm/boot/dts/imx51-efikamx.dts
> new file mode 100644
> index 0000000..dd14f77
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx51-efikamx.dts
> @@ -0,0 +1,247 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + * Copyright 2012 Genesi USA, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx51.dtsi"
> +
> +/ {
> +	model = "Genesi Efika MX (Smarttop)";
> +	compatible = "genesi,imx51-efikamx", "fsl,imx51";
> +
> +	memory {
> +		reg = <0x90000000 0x20000000>;
> +	};
> +
> +	soc {
> +		aips at 70000000 {
> +			spba at 70000000 {
> +				esdhc at 70004000 {

The pinctrl_provide_dummies() in imx51_dt_init() is something to be
removed.  Then any driver calling pinctrl API will require pinctrl
set up for the device here.  So please have the pinctrl setup for
those devices. 

> +					cd-gpios = <&gpio1 0 0>;
> +					wp-gpios = <&gpio1 1 0>;
> +					status = "okay";
> +				};
> +
> +				ssi2: ssi at 70014000 {
> +				    fsl,mode = "i2s-slave";
> +				    status = "okay";
> +				};
> +
> +				ecspi at 70010000 {
> +					fsl,spi-num-chipselects = <2>;
> +					cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
> +					status = "okay";
> +
> +					pmic: mc13892 at 0 {
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +						compatible = "fsl,mc13892";
> +						spi-max-frequency = <6000000>;
> +						reg = <0>;
> +						interrupt-parent = <&gpio1>;
> +						interrupts = <6 0x4>;
> +						fsl,mc13xxx-uses-rtc;
> +
> +						regulators {
> +							sw1_reg: sw1 {
> +								regulator-min-microvolt = <600000>;
> +								regulator-max-microvolt = <1375000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							sw2_reg: sw2 {
> +								regulator-min-microvolt = <900000>;
> +								regulator-max-microvolt = <1850000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							sw3_reg: sw3 {
> +								regulator-min-microvolt = <1100000>;
> +								regulator-max-microvolt = <1850000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							sw4_reg: sw4 {
> +								regulator-min-microvolt = <1100000>;
> +								regulator-max-microvolt = <1850000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							vpll_reg: vpll {
> +								regulator-min-microvolt = <1050000>;
> +								regulator-max-microvolt = <1800000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							vdig_reg: vdig {
> +								regulator-min-microvolt = <1650000>;
> +								regulator-max-microvolt = <1650000>;
> +								regulator-boot-on;
> +							};
> +
> +							vsd_reg: vsd {
> +								regulator-min-microvolt = <3150000>;
> +								regulator-max-microvolt = <3150000>;
> +							};
> +
> +							vusb2_reg: vusb2 {
> +								regulator-min-microvolt = <2400000>;
> +								regulator-max-microvolt = <2775000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};
> +
> +							vvideo_reg: vvideo {
> +								regulator-min-microvolt = <2775000>;
> +								regulator-max-microvolt = <2775000>;
> +								regulator-boot-on;
> +							};
> +
> +							vaudio_reg: vaudio {
> +								regulator-min-microvolt = <2300000>;
> +								regulator-max-microvolt = <3000000>;
> +							};
> +
> +							vcam_reg: vcam {
> +								regulator-min-microvolt = <2500000>;
> +								regulator-max-microvolt = <3000000>;
> +							};
> +
> +							vgen1_reg: vgen1 {
> +								regulator-min-microvolt = <1200000>;
> +								regulator-max-microvolt = <3150000>;
> +							};
> +
> +							vgen2_reg: vgen2 {
> +								regulator-min-microvolt = <3150000>;
> +								regulator-max-microvolt = <3150000>;
> +								regulator-always-on;
> +							};
> +
> +							vgen3_reg: vgen3 {
> +								regulator-min-microvolt = <1800000>;
> +								regulator-max-microvolt = <2900000>;
> +								regulator-always-on;
> +							};
> +						};
> +					};
> +
> +					flash: sst25vf032b at 1 {
> +						#address-cells = <1>;
> +						#size-cells = <1>;
> +						compatible = "sst,sst25vf032b";
> +						spi-max-frequency = <25000000>;
> +						reg = <1>;
> +
> +						partition at 0 {
> +							label = "firmware";
> +							reg = <0x0 0x200000>;
> +						};
> +
> +						partition at 200000 {
> +							label = "user";
> +							reg = <0x200000 0x200000>;
> +						};
> +					};
> +				};
> +			};
> +
> +			wdog at 73f98000 {
> +				status = "okay";
> +			};

Remove it.  I have queued a patch to enable wdog in <soc>.dtsi
by default.

> +
> +			iomuxc at 73fa8000 {
> +				compatible = "fsl,imx51-iomuxc";
> +				reg = <0x73fa8000 0x4000>;
> +			};
> +
> +			uart1: serial at 73fbc000 {
> +				fsl,uart-has-rtscts;
> +				status = "okay";
> +			};
> +
> +		};
> +
> +		aips at 80000000 {
> +			sdma at 83fb0000 {
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
> +			};

Remove it.  I have seen a patch to move this name into <soc>.dtsi
as default.

> +
> +			i2c at 83fc4000 {
> +				status = "okay";
> +
> +				codec: sgtl5000 at 0a {
> +					compatible = "fsl,sgtl5000";
> +					reg = <0x0a>;
> +					clock-frequency = <12288000>;
> +					VDDA-supply = <&vdig_reg>;
> +					VDDIO-supply = <&vvideo_reg>;
> +				};
> +			};
> +
> +			audmux at 83fd0000 {
> +				status = "okay";
> +			};
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		power {
> +			label = "Power Button";
> +			gpios = <&gpio2 31 0>;
> +			linux,code = <116>; /* KEY_POWER */
> +			gpio-key,wakeup;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		red {
> +			label = "red";
> +			gpios = <&gpio3 13>;
> +			linux,default-trigger = "ide-disk";
> +		};
> +
> +		green {
> +			label = "green";
> +			gpios = <&gpio3 14>;
> +			linux,default-trigger = "default-on";
> +		};
> +
> +		blue {
> +			label = "blue";
> +			gpios = <&gpio3 15>;
> +			linux,default-trigger = "mmc0";
> +		};
> +	};
> +
> +	sound {
> +		compatible = "fsl,imx-audio-sgtl5000";
> +		model = "efikamx-sgtl5000";
> +		ssi-controller = <&ssi2>;
> +		audio-routing =
> +			"MIC_IN", "Mic Jack",
> +			"Mic Jack", "Mic Bias",
> +			"Ext Spk", "LINE_OUT";
> +		audio-codec = <&codec>;
> +		mux-int-port = <2>;
> +		mux-ext-port = <3>;
> +	};
> +};
> diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
> index 05541cf..3ed7c9d 100644
> --- a/arch/arm/mach-imx/Makefile.boot
> +++ b/arch/arm/mach-imx/Makefile.boot
> @@ -38,7 +38,7 @@ zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
>  params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
>  initrd_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10800000
>  
> -dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
> +dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb imx51-efikamx.dtb

Please have the new entry on the new line like dtb-$(CONFIG_SOC_IMX6Q).
Yes, we will change dtb-$(CONFIG_MACH_IMX53_DT).

>  dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
>  			       imx53-qsb.dtb imx53-smd.dtb
>  dtb-$(CONFIG_SOC_IMX6Q)	+= imx6q-arm2.dtb \
> -- 
> 1.7.9.5
> 

-- 
Regards,
Shawn



From catalin.marinas at arm.com  Wed Aug  8 11:16:11 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 Aug 2012 16:16:11 +0100
Subject: [RFC] Add support for Aurora L2 Cache Controller
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <CAHkRjk4qPPktXsqnRaZLG0Z=VMH_Qf6xRdQBPMvxC20m6noc+A@mail.gmail.com>

On 8 August 2012 16:05, Gregory CLEMENT
<gregory.clement at free-electrons.com> wrote:
> - two flavors of the controller 'outer cache' and 'system cache' (the
>   last one meaning maintenance operations on L1 are broadcasted to the
>   L2 and L2 performs the same operation).

BTW, is the DSB also transparently handled by the L2 in 'system cache' mode?

-- 
Catalin


From will.deacon at arm.com  Wed Aug  8 11:19:47 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 8 Aug 2012 16:19:47 +0100
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20120808151946.GE4579@mudshark.cambridge.arm.com>

On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
> +static void aurora_pa_range(unsigned long start, unsigned long end,
> +                       unsigned long offset)
> +{

This controller is used by Armada XP right? I think that SoC supports LPAE,
so please tell me that the above is a mistake and the controller can support
physical addresses > 32 bits!

If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
instead of unsigned longs.

Will


From haojian.zhuang at gmail.com  Wed Aug  8 11:24:40 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 8 Aug 2012 23:24:40 +0800
Subject: [PATCH 2/6] ARM: pxa remove irq_to_gpio from eeti_ts driver
In-Reply-To: <1344430493-5304-3-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-3-git-send-email-arnd@arndb.de>
Message-ID: <CAN1soZwzSVe2VrTOod0ZtwF9UUS7fPYSt6Vkqgg4-6csUB3mqw@mail.gmail.com>

On Wed, Aug 8, 2012 at 8:54 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The irq_to_gpio function was removed from the pxa platform
> in linux-3.2, and this driver has been broken since.
>
> Without this patch, building raumfeld_defconfig results in:
>
> drivers/input/touchscreen/eeti_ts.c: In function 'eeti_ts_irq_active':
> drivers/input/touchscreen/eeti_ts.c:65:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: stable at vger.kernel.org (v3.2+)
> Cc: Daniel Mack <zonque at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
>  arch/arm/mach-pxa/raumfeld.c        |    1 +
>  drivers/input/touchscreen/eeti_ts.c |    8 +++++---
>  include/linux/input/eeti_ts.h       |    1 +
>  3 files changed, 7 insertions(+), 3 deletions(-)
>

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>


From gururaja.hebbar at ti.com  Wed Aug  8 11:10:31 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 8 Aug 2012 20:40:31 +0530
Subject: [PATCH] ASoC: Davinci: McASP: Flush the FIFO before enabling
In-Reply-To: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344438632-2604-2-git-send-email-gururaja.hebbar@ti.com>

From: Vaibhav Bedia <vaibhav.bedia at ti.com>

FIFO should be flushed before it is enabled for the first time.
This fixes the I/O errors reported by the ASoC core on a fresh boot

Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
This patch was tested on AM18x Board and is based on repo at 
http://git.kernel.org/?p=linux/kernel/git/broonie/sound.git;
a=shortlog;h=refs/heads/for-3.6

:100644 100644 95441bf... ce5e5cd... M	sound/soc/davinci/davinci-mcasp.c
 sound/soc/davinci/davinci-mcasp.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 95441bf..ce5e5cd 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -380,14 +380,20 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
 {
 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		if (dev->txnumevt)	/* enable FIFO */
+		if (dev->txnumevt) {	/* enable FIFO */
+			mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+								FIFO_ENABLE);
 			mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
 								FIFO_ENABLE);
+		}
 		mcasp_start_tx(dev);
 	} else {
-		if (dev->rxnumevt)	/* enable FIFO */
+		if (dev->rxnumevt) {	/* enable FIFO */
+			mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+								FIFO_ENABLE);
 			mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
 								FIFO_ENABLE);
+		}
 		mcasp_start_rx(dev);
 	}
 }
-- 
1.7.1



From gururaja.hebbar at ti.com  Wed Aug  8 11:10:32 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 8 Aug 2012 20:40:32 +0530
Subject: [PATCH] ASoC: McASP: Convert driver to use Runtime PM API
In-Reply-To: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344438632-2604-3-git-send-email-gururaja.hebbar@ti.com>

  * Add Runtime PM support to McASP host controller.
  * Use Runtime PM API to enable/disable McASP clock.

This was tested on AM18x Board using suspend/resume

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
This patch was tested on AM18x Board and is based on repo at 
http://git.kernel.org/?p=linux/kernel/git/broonie/sound.git;
a=shortlog;h=refs/heads/for-3.6

:100644 100644 ce5e5cd... 6a2c54c... M	sound/soc/davinci/davinci-mcasp.c
:100644 100644 4681acc... 51479f9... M	sound/soc/davinci/davinci-mcasp.h
 sound/soc/davinci/davinci-mcasp.c |   40 +++++++++++++++++-------------------
 sound/soc/davinci/davinci-mcasp.h |    3 +-
 2 files changed, 20 insertions(+), 23 deletions(-)

diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index ce5e5cd..6a2c54c 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -21,7 +21,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/clk.h>
+#include <linux/pm_runtime.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -782,20 +782,17 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
 	case SNDRV_PCM_TRIGGER_RESUME:
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-		if (!dev->clk_active) {
-			clk_enable(dev->clk);
-			dev->clk_active = 1;
-		}
+		ret = pm_runtime_get_sync(dev->dev);
+		if (IS_ERR_VALUE(ret))
+			dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
 		davinci_mcasp_start(dev, substream->stream);
 		break;
 
 	case SNDRV_PCM_TRIGGER_SUSPEND:
 		davinci_mcasp_stop(dev, substream->stream);
-		if (dev->clk_active) {
-			clk_disable(dev->clk);
-			dev->clk_active = 0;
-		}
-
+		ret = pm_runtime_put_sync(dev->dev);
+		if (IS_ERR_VALUE(ret))
+			dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
@@ -892,12 +889,13 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	}
 
 	pdata = pdev->dev.platform_data;
-	dev->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(dev->clk))
-		return -ENODEV;
+	pm_runtime_enable(&pdev->dev);
 
-	clk_enable(dev->clk);
-	dev->clk_active = 1;
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (IS_ERR_VALUE(ret)) {
+		dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
+		return ret;
+	}
 
 	dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 	if (!dev->base) {
@@ -914,6 +912,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	dev->version = pdata->version;
 	dev->txnumevt = pdata->txnumevt;
 	dev->rxnumevt = pdata->rxnumevt;
+	dev->dev = &pdev->dev;
 
 	dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
 	dma_data->asp_chan_q = pdata->asp_chan_q;
@@ -955,19 +954,18 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	return 0;
 
 err_release_clk:
-	clk_disable(dev->clk);
-	clk_put(dev->clk);
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
 	return ret;
 }
 
 static int davinci_mcasp_remove(struct platform_device *pdev)
 {
-	struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
 
 	snd_soc_unregister_dai(&pdev->dev);
-	clk_disable(dev->clk);
-	clk_put(dev->clk);
-	dev->clk = NULL;
+
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
 
 	return 0;
 }
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
index 4681acc..51479f9 100644
--- a/sound/soc/davinci/davinci-mcasp.h
+++ b/sound/soc/davinci/davinci-mcasp.h
@@ -40,9 +40,8 @@ struct davinci_audio_dev {
 	struct davinci_pcm_dma_params dma_params[2];
 	void __iomem *base;
 	int sample_rate;
-	struct clk *clk;
+	struct device *dev;
 	unsigned int codec_fmt;
-	u8 clk_active;
 
 	/* McASP specific data */
 	int	tdm_slots;
-- 
1.7.1



From gururaja.hebbar at ti.com  Wed Aug  8 11:10:30 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 8 Aug 2012 20:40:30 +0530
Subject: [PATCH] ASoC: Davinci: McASP: remove unused header include
Message-ID: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>

Defines or parameters from <mach/mux.h> isn't used anywhere. Hence
remove the header include.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
This patch was tested on AM18x Board and is based on repo at 
http://git.kernel.org/?p=linux/kernel/git/broonie/sound.git;
a=shortlog;h=refs/heads/for-3.6

:100644 100644 10a2d8c... c80c20a... M	sound/soc/davinci/davinci-evm.c
 sound/soc/davinci/davinci-evm.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 10a2d8c..c80c20a 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -24,7 +24,6 @@
 
 #include <mach/asp.h>
 #include <mach/edma.h>
-#include <mach/mux.h>
 
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
-- 
1.7.1



From gregkh at linuxfoundation.org  Wed Aug  8 11:25:45 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Wed, 8 Aug 2012 08:25:45 -0700
Subject: [PATCH 03/11] usb/ohci-omap: remove unused variable
In-Reply-To: <1344437248-20560-4-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-4-git-send-email-arnd@arndb.de>
Message-ID: <20120808152545.GC15776@kroah.com>

On Wed, Aug 08, 2012 at 04:47:20PM +0200, Arnd Bergmann wrote:
> Commit c2e935a7d "USB: move transceiver from ehci_hcd and ohci_hcd to
> hcd and rename it as phy" removed the last use of the "ohci" variable
> in the usb_hcd_omap_remove function, but left the variable in place
> unused.
> 
> Without this patch, building omap1_defconfig results in:
> 
> In file included from drivers/usb/host/ohci-hcd.c:1013:0:
> drivers/usb/host/ohci-omap.c: In function 'usb_hcd_omap_remove':
> drivers/usb/host/ohci-omap.c:406:19: warning: unused variable 'ohci' [-Wunused-variable]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Richard Zhao <richard.zhao at freescale.com>
> Cc: Alan Stern <stern at rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>

Acked-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>


From haojian.zhuang at gmail.com  Wed Aug  8 11:27:34 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 8 Aug 2012 23:27:34 +0800
Subject: [PATCH 1/6] ARM: pxa: remove irq_to_gpio from ezx-pcap driver
In-Reply-To: <1344430493-5304-2-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-2-git-send-email-arnd@arndb.de>
Message-ID: <CAN1soZy8nWpneqgbA7tdN-868WW8QC7SVHoGDRqyKz_=mTJEAQ@mail.gmail.com>

On Wed, Aug 8, 2012 at 8:54 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The irq_to_gpio function was removed from the pxa platform
> in linux-3.2, and this driver has been broken since.
>
> There is actually no in-tree user of this driver that adds
> this platform device, but the driver can and does get enabled
> on some platforms.
>
> Without this patch, building ezx_defconfig results in:
>
> drivers/mfd/ezx-pcap.c: In function 'pcap_isr_work':
> drivers/mfd/ezx-pcap.c:205:2: error: implicit declaration of function 'irq_to_gpio' [-Werror=implicit-function-declaration]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: stable at vger.kernel.org (v3.2+)
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Daniel Ribeiro <drwyrm at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
>  drivers/mfd/ezx-pcap.c       |    2 +-
>  include/linux/mfd/ezx-pcap.h |    1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>


From linux at arm.linux.org.uk  Wed Aug  8 11:33:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 Aug 2012 16:33:31 +0100
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
References: <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
 <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
Message-ID: <20120808153330.GM18957@n2100.arm.linux.org.uk>

On Tue, Aug 07, 2012 at 05:34:15PM -0500, Matt Sealey wrote:
> Just because there is a ton of absolutely awful, broken firmware code out there
> doesn't mean it can and will always be the case, and Linux policy should not
> be dictated on an architecture basis on a few bad eggs, especially if it means
> developers in the big wide world have to jump through hoops. Surely it is just
> as good for Linux to loudly advocate the correct solutions in firmware and
> implement the workarounds anyway, like a device quirk, rather than just out and
> out say "firmwares suck, ignore what they did, do it again. We don't trust them
> and never will."

Sadly, firmware developers have taught us time and time and time and time
again that they can not be trusted.  You may be the single one who can be
trusted to validate their stuff properly, but you would be in a severe
minority if that is true.

Many firmware developers do the barest minimum that's required.  Once their
job is done, that's the end of the development cycle and nothing further
happens, not even for bugs.

We've seen this time and time again.  We see it with corrupted ATAG lists,
we see it with bad memory tags passed to the kernel that the kernel has to
then screw around with to fix up the broken firmware developers crap.
Let me show you the crappy workarounds that we have:

static void __init
fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
{
        mi->nr_banks=1;
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 0x01000000;
}
static void __init
fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
{
        /*
         * Bank start addresses are not present in the information
         * passed in from the boot loader.  We could potentially
         * detect them, but instead we hard-code them.
         *
         * Banks sizes _are_ present in the param block, but we're
         * not using that information yet.
         */
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 8*1024*1024;
        mi->bank[1].start = 0xc1000000;
        mi->bank[1].size = 8*1024*1024;
        mi->nr_banks = 2;
}
static void __init
fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
{
...
        memmap.bank[0].size = ip->ram_size;
        *mi = memmap;
}
static void __init mahimahi_fixup(struct tag *tags, char **cmdline,
                                  struct meminfo *mi)
{
        mi->nr_banks = 2;
        mi->bank[0].start = PHYS_OFFSET;
        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
        mi->bank[0].size = (219*1024*1024);
        mi->bank[1].start = MSM_HIGHMEM_BASE;
        mi->bank[1].node = PHYS_TO_NID(MSM_HIGHMEM_BASE);
        mi->bank[1].size = MSM_HIGHMEM_SIZE;
}
static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
                struct meminfo *mi)
{
        for (; tag->hdr.size; tag = tag_next(tag))
                if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
                        tag->u.mem.start = 0;
                        tag->u.mem.size += SZ_2M;
                }
}
static void __init msm8960_fixup(struct tag *tag, char **cmdline,
                struct meminfo *mi)
{
        for (; tag->hdr.size; tag = tag_next(tag))
                if (tag->hdr.tag == ATAG_MEM &&
                                tag->u.mem.start == 0x40200000) {
                        tag->u.mem.start = 0x40000000;
                        tag->u.mem.size += SZ_2M;
                }
}
static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
                struct meminfo *mi)
{
        for (; tag->hdr.size; tag = tag_next(tag))
                if (tag->hdr.tag == ATAG_MEM &&
                                tag->u.mem.start == 0x40200000) {
                        tag->u.mem.start = 0x40000000;
                        tag->u.mem.size += SZ_2M;
                }
}
static void __init sapphire_fixup(struct tag *tags, char **cmdline,
                                  struct meminfo *mi)
{
        int smi_sz = parse_tag_smi((const struct tag *)tags);

        mi->nr_banks = 1;
        mi->bank[0].start = PHYS_OFFSET;
        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
        if (smi_sz == 32) {
                mi->bank[0].size = (84*1024*1024);
        } else if (smi_sz == 64) {
                mi->bank[0].size = (101*1024*1024);
        } else {
                /* Give a default value when not get smi size */
                smi_sz = 64;
                mi->bank[0].size = (101*1024*1024);
        }
}
static void __init trout_fixup(struct tag *tags, char **cmdline,
                               struct meminfo *mi)
{
        mi->nr_banks = 1;
        mi->bank[0].start = PHYS_OFFSET;
        mi->bank[0].size = (101*1024*1024);
}
static void __init fixup_corgi(struct tag *tags, char **cmdline,
                               struct meminfo *mi)
{
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
        if (machine_is_corgi())
                mi->bank[0].size = (32*1024*1024);
        else
                mi->bank[0].size = (64*1024*1024);
}
void __init eseries_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
{
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
        if (machine_is_e800())
                mi->bank[0].size = (128*1024*1024);
        else
                mi->bank[0].size = (64*1024*1024);
}
static void __init fixup_poodle(struct tag *tags, char **cmdline,
                                struct meminfo *mi)
{
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
        mi->bank[0].size = (32*1024*1024);
}
static void __init spitz_fixup(struct tag *tags, char **cmdline,
                               struct meminfo *mi)
{
        sharpsl_save_param();
        mi->nr_banks = 1;
        mi->bank[0].start = 0xa0000000;
        mi->bank[0].size = (64*1024*1024);
}
static void __init fixup_tosa(struct tag *tags, char **cmdline,
                              struct meminfo *mi)
{
        sharpsl_save_param();
        mi->nr_banks=1;
        mi->bank[0].start = 0xa0000000;
        mi->bank[0].size = (64*1024*1024);
}
static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
                                  struct meminfo *mi)
{
        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
                mi->nr_banks=1;
                mi->bank[0].start = 0x30000000;
                mi->bank[0].size = SZ_64M;
        }
}
static void __init vstms_fixup(struct tag *tags, char **cmdline,
                               struct meminfo *mi)
{
        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
                mi->nr_banks=1;
                mi->bank[0].start = 0x30000000;
                mi->bank[0].size = SZ_64M;
        }
}

Spot a pattern there?  The one which stands out to me is that boot loaders
can not get the trivial task of passing the simple information about where
the RAM is in the system to the kernel right.

Many boot loaders for _years_ have not been able to get the very very
trivially simple issue of passing the right machine ID value in r1 to the
kernel either.

History has taught us time and time and time again that firmware can
not be trusted in *any* *way* and we have plenty of proof to back that
up.

Have we tried to push the onus back on firmware people?  I've tried damned
hard to the extent of preventing some of these work-arounds getting into
mainline, but the sole result of that was that mainline would not work on
those platforms; it didn't make a blind bit of difference to the firmware
on the platforms.  It didn't magically cause the firmware to get fixed in
any way.  We just ended up with a detrimental situation to everyone because
mainline just didn't work on those platforms.

So please, stop telling us what we should and shouldn't do with firmware.
We've learnt by the action of firmware developers how to treat them, and
that's how we're going to treat them.  They have earned our distrust.  In
order for that to change, they must change, and they must _earn_ our trust
that they _can_ be trusted to do a good job.  Until then...


From linux at arm.linux.org.uk  Wed Aug  8 11:36:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 Aug 2012 16:36:55 +0100
Subject: [PATCH 3/6] ARM: sa1100: include asm/io.h in hackkit leds code
In-Reply-To: <1344430493-5304-4-git-send-email-arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-4-git-send-email-arnd@arndb.de>
Message-ID: <20120808153655.GN18957@n2100.arm.linux.org.uk>

On Wed, Aug 08, 2012 at 02:54:50PM +0200, Arnd Bergmann wrote:
> The sa1100 definition of the io_p2v macro has changed in v3.6, and this one
> file stopped working because of that.
> 
> Without this patch, building hackkit_defconfig results in:
> 
> arch/arm/mach-sa1100/leds-hackkit.c: In function 'hackkit_leds_event':
> arch/arm/mach-sa1100/leds-hackkit.c:39:4: error: implicit declaration of function 'IOMEM' [-Werror=implicit-function-declaration]

NAK.  Should be linux/io.h


From swarren at wwwdotorg.org  Wed Aug  8 11:40:57 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 09:40:57 -0600
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <1344437248-20560-12-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-12-git-send-email-arnd@arndb.de>
Message-ID: <50228889.5060709@wwwdotorg.org>

On 08/08/2012 08:47 AM, Arnd Bergmann wrote:
> A few drivers use a construct like
> 
>  #ifdef CONFIG_PM
>  static int foo_suspend(struct device *pdev)
>  {
>     ...
>  }
>  static int foo_resume struct device *pdev)
>  {
>     ...
>  }
>  #endif
>  static SIMPLE_DEV_PM_OPS(foo_pm, foo_suspend, foo_resume);
...
> drivers/i2c/busses/i2c-tegra.c:716:12: warning: 'tegra_i2c_suspend' defined but not used [-Wunused-function]
> drivers/i2c/busses/i2c-tegra.c:727:12: warning: 'tegra_i2c_resume' defined but not used [-Wunused-function]

Laxman already posted a patch for this, which I'm hoping will make it
into 3.6, through the I2C tree.

http://www.spinics.net/lists/linux-i2c/msg09359.html


From stern at rowland.harvard.edu  Wed Aug  8 11:34:47 2012
From: stern at rowland.harvard.edu (Alan Stern)
Date: Wed, 8 Aug 2012 11:34:47 -0400 (EDT)
Subject: [PATCH 03/11] usb/ohci-omap: remove unused variable
In-Reply-To: <1344437248-20560-4-git-send-email-arnd@arndb.de>
Message-ID: <Pine.LNX.4.44L0.1208081134350.1701-100000@iolanthe.rowland.org>

On Wed, 8 Aug 2012, Arnd Bergmann wrote:

> Commit c2e935a7d "USB: move transceiver from ehci_hcd and ohci_hcd to
> hcd and rename it as phy" removed the last use of the "ohci" variable
> in the usb_hcd_omap_remove function, but left the variable in place
> unused.
> 
> Without this patch, building omap1_defconfig results in:
> 
> In file included from drivers/usb/host/ohci-hcd.c:1013:0:
> drivers/usb/host/ohci-omap.c: In function 'usb_hcd_omap_remove':
> drivers/usb/host/ohci-omap.c:406:19: warning: unused variable 'ohci' [-Wunused-variable]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Richard Zhao <richard.zhao at freescale.com>
> Cc: Alan Stern <stern at rowland.harvard.edu>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> ---
>  drivers/usb/host/ohci-omap.c |    2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
> index e7d75d2..f8b2d91 100644
> --- a/drivers/usb/host/ohci-omap.c
> +++ b/drivers/usb/host/ohci-omap.c
> @@ -403,8 +403,6 @@ err0:
>  static inline void
>  usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev)
>  {
> -	struct ohci_hcd		*ohci = hcd_to_ohci (hcd);
> -
>  	usb_remove_hcd(hcd);
>  	if (!IS_ERR_OR_NULL(hcd->phy)) {
>  		(void) otg_set_host(hcd->phy->otg, 0);
> 

Acked-by: Alan Stern <stern at rowland.harvard.edu>



From b-cousson at ti.com  Wed Aug  8 11:41:47 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Wed, 8 Aug 2012 17:41:47 +0200
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <50227936.3040701@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <5022529D.3090406@ti.com>
 <20120808125252.GR16861@opensource.wolfsonmicro.com>
 <50227936.3040701@ti.com>
Message-ID: <502288BB.6020709@ti.com>

On 08/08/2012 04:35 PM, Peter Ujfalusi wrote:
> On 08/08/2012 03:52 PM, Mark Brown wrote:
>> On Wed, Aug 08, 2012 at 01:50:53PM +0200, Benoit Cousson wrote:
>>
>>> That being said, since we do have the clock binding now, maybe we should
>>> create a clock provider at board level for the sys_clk and thus you will
>>> just have to create a phandle to it in your audio description.
>>
>> Yes, we should be doing this.
> 
> Does this needs the common clock framework on the platform? OMAP3 certainly
> does not have it enabled since it has not been adopted.
> 

Yeah, good point, we are still not there yet. Rajendra is still working
on it and I hope we can get something for 3.7, but let's avoid having a
strong dependency on that migration for the moment.

Regards,
Benoit


From catalin.marinas at arm.com  Wed Aug  8 11:43:18 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 8 Aug 2012 16:43:18 +0100
Subject: [PATCH 00/22] Introducing the TI Keystone platform
In-Reply-To: <501E8CEA.9050601@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <20120804083945.GB6802@n2100.arm.linux.org.uk>
 <501E8CEA.9050601@ti.com>
Message-ID: <20120808154318.GE8444@arm.com>

On Sun, Aug 05, 2012 at 04:10:34PM +0100, Cyril Chemparathy wrote:
> On 8/4/2012 4:39 AM, Russell King - ARM Linux wrote:
> > On Tue, Jul 31, 2012 at 07:04:36PM -0400, Cyril Chemparathy wrote:
> >> This series is a follow on to the RFC series posted earlier (archived at [1]).
> >> The major change introduced here is the modification to the kernel patching
> >> mechanism for phys_to_virt/virt_to_phys, in order to support LPAE platforms
> >> that require late patching.  In addition to these changes, we've updated the
> >> series based on feedback from the earlier posting.
> >>
> >> Most of the patches in this series are fixes and extensions to LPAE support on
> >> ARM. The last three patches in this series are specific to the TI Keystone
> >> platform, and are being provided here for the sake of completeness.  These
> >> three patches are dependent on the smpops patch set (see [2]), and are not
> >> ready to be merged in as yet.
> >
> > Can you explain why you want the kernel loaded above the 4GB watermark?
> > This seems silly to me, as the kernel needs to run at points with a 1:1
> > physical to virtual mapping, and you can't do that if the kernel is
> > stored in physical memory above the 4GB watermark.
[...]
> We are well aware of the fact that we are barely scratching the surface 
> of the problem space here, and we'd be very thankful for a heads up on 
> issues that we may have missed so far.

Another thing to be aware is that apart from a virtual alias between the
kernel mapping and the idmap, you now introduce a physical alias as well
and the caches (physically tagged) get confused.

-- 
Catalin


From festevam at gmail.com  Wed Aug  8 11:53:36 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 8 Aug 2012 12:53:36 -0300
Subject: [PATCH 1/2] ARM: mx27pdk: Add audio support
In-Reply-To: <20120803135956.GT1451@pengutronix.de>
References: <1341341098-9510-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5BXQ2OQVC6nXeo_yJB=SBC=sv=ez9k6uo3gLNkWnC0Gyg@mail.gmail.com>
 <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
 <20120803135956.GT1451@pengutronix.de>
Message-ID: <CAOMZO5CPak9EZQnxWwzzNSj2jFbSbDpYGB-gAStHihnnKEGRSg@mail.gmail.com>

On Fri, Aug 3, 2012 at 10:59 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:

> Applied now. Sorry, missed this one.

Which git tree, please? I was not able to find it at
http://git.pengutronix.de/?p=imx/linux-2.6.git;a=summary

Regards,

Fabio Estevam


From linux at arm.linux.org.uk  Wed Aug  8 12:05:17 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 8 Aug 2012 17:05:17 +0100
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208080948210.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
 <alpine.LFD.2.02.1208080106500.5231@xanadu.home> <5022673A.7060407@ti.com>
 <alpine.LFD.2.02.1208080948210.5231@xanadu.home>
Message-ID: <20120808160517.GO18957@n2100.arm.linux.org.uk>

On Wed, Aug 08, 2012 at 09:55:12AM -0400, Nicolas Pitre wrote:
> On Wed, 8 Aug 2012, Cyril Chemparathy wrote:
> > Neat macro magic.  Are you thinking that we build this in as a self test in
> > the code?
> 
> For such things, this is never a bad idea to have some test alongside 
> with the main code, especially if this is extended to more cases in the 
> future.  It is too easy to break it in subtle ways.
> 
> See arch/arm/kernel/kprobes-test*.c for a precedent.

Done correctly, it shouldn't be a problem, but I wouldn't say that
arch/arm/kernel/kprobes-test*.c is done correctly.  It's seen quite
a number of patching attempts since it was introduced for various
problems, and I've seen quite a number of builds fail for various
reasons in this file (none which I could be bothered to investigate.)

When the test code ends up causing more problems than the code it's
testing, something is definitely wrong.


From gcembed at gmail.com  Wed Aug  8 12:11:55 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Wed, 08 Aug 2012 18:11:55 +0200
Subject: [PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block
 Indicator, and use for imx27pdk nand support.
In-Reply-To: <20110706120551.GU6069@pengutronix.de>
References: <1309872828-13942-1-git-send-email-J.Lambrecht@televic.com>
 <20110706080942.GC26347@pengutronix.de> <4E142B18.60407@televic.com>
 <20110706120551.GU6069@pengutronix.de>
Message-ID: <50228FCB.7020003@gmail.com>

Hi,

On 07/06/2011 02:05 PM, Sascha Hauer wrote:
> On Wed, Jul 06, 2011 at 11:30:00AM +0200, Lambrecht J?rgen wrote:
>> On 07/06/2011 10:09 AM, Sascha Hauer wrote:
>>> On Tue, Jul 05, 2011 at 03:33:48PM +0200, J?rgen Lambrecht wrote:
>>>> - Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To
>>> fix a bug
>>>>    in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and
>>> imx31.
>>>>    Warning: The same solution needs to be applied to the boot loader
>>> and the
>>>>    flash programmer.
>>>> - Enable NAND support for the imx27pdk (3ds), and use BISWAP.
>>>>
>>>> Signed-off-by: J?rgen Lambrecht <J.Lambrecht at televic.com>
>>>> ---
>>>>   arch/arm/mach-imx/Kconfig         |   30 ++++++++++++++++++++++++++++--
>>>>   arch/arm/mach-imx/mach-mx27_3ds.c |   14 ++++++++++++++
>>>>   drivers/mtd/nand/mxc_nand.c       |   29 +++++++++++++++++++++++++++++
>>>>   3 files changed, 71 insertions(+), 2 deletions(-)
>>>>
>>> [snip]
>>>
>>>> +
>>>> +config IMX_NFC_V1_BISWAP
>>>> +     bool "Make the MXC 2kB-page NAND driver swap the Bad Block
>>> Indicator"
>>>> +     depends on MACH_MX27_3DS
>>>> +     depends on MTD_NAND_MXC
>>>> +     help
>>>> +       Enable this if you want that the MXC NAND driver swaps the
>>> Bad Block
>>>> +       Indicator (BBI) byte. The IMX NFC v1 (present in IMX27 and
>>> IMX31)
>>>> +       contains a bug for 2kB-page flashes: the 2kB page is read out in
>>>> +       4x512B chunks, so also the spare area is read out in 4
>>>> +       chunks. Therefore the data area and the spare area becomes
>>>> +       mixed. This causes a problem for the factory programmed BBI: it
>>>> +       appears in the data area instead of the spare area, and is
>>>> +       overwritten. This patch swaps that byte to the "real" spare
>>>> +       area. WARNING: then also the bootloader and the flash
>>> programmer must
>>>> +       be patched!!
>>>
>>> I don't like this approach. IMO some code should be run on a virgin
>>> flash which is aware of this issue and creates a correct bad block
>>> table. You run this once and forget about this afterwards and every
>>> kernel/bootloader can run without patching. Otherwise if you accidently
>>> or intentionally start an older (unpatched) kernel your Nand gets
>>> corrupted.
>>>
>> I see 3 solutions: rely on the quality of the NAND flash driver (1),
>> patch the SW (2) or patch the HW (3).
>>
>> 1. A normal NAND flash driver relies on the ECC to detect a
>> (potentially) bad block. But a factory bad block can have more bad bits
>> that the specified ECC bits.
>>      Solution is to check after each write if the data was written
>> reliable: a write/read-back policy. (linux kernel option: Device Drivers
>> -> MTD support -> NAND Device Support -> Verify NAND page writes)
>>      This will of course slow-down writing a lot.
>> 2. The Freescale solution: patch the SW:
>>         1. flash programmer
>>         2. boot-loader NAND driver
>>         3. OS NAND driver
>> 3. For the HW patch, a special SW must be written that must be executed
>> before the board is programmed. That special SW must run in RAM and copy
>> the BBI byte to the "swapped" place, so that after swapping, the BBI is
>> at the good place. Then the SW must not be patched.
>>      Risk: if this step is skipped, the factory BBI information is lost,
>> and if the SW has no write/read-back policy (solution 1), data will be
>> lost in some point in time.
>>
>> Your solution is (3), but for the linux rootfs partition only, using the
>> BBT. Of course bootloader partitions and the linux kernel binary are not
>> written often, but I read (several times, and also been told) that even
>> when only reading a nand flash it can become bad!
>> I still have to investigate this for how to solve this in the bootloader..
>>
>> Because of the risk, and to have a fast solution, we went for solution (2).
>> But if no one else is interested in this solution, I guess there is no
>> point trying to get it accepted.
>>
>>> Also, my comment above applies here too. You added a 'depends on the
>>> board I care of', but usually my kernels have all available boards
>>> compiled in. So I can select this option and it will change the
>>> behaviour of all boards I might run the kernel on, not only the
>>> ones you depend on above.
>> Ok, i should then find a better way to do it.
>> But, the mxc_nand.c code contains this to protect it: 'if
>> ((mtd->writesize > 512) && nfc_is_v1())'.
>
> This is the correct way to limit the fix to the correct versions of the
> nand controller, but that's not what I tried to say. You might want
> to use solution (2) for your board whereas I want to use solution (3)
> for my boards. With the Kconfig approach it would not be possible for
> us to use the same kernel binary.
A few years ago, I assist to a training done by Adeneo France (partner 
of Freescale). They gave us the sources (Bootloader + Kernel 2.6.22) 
that include patches to swap bytes. So all of my work is now based with 
the swap of bytes done by NFC driver in bootloader and Kernel.
I use OpenOCD to program NAND and the NFC driver that I send us also 
include this patch. Now in OpenOCD 6.0rc1, there is an option to enable 
or not the biswap at runtime (openocd command line).
So is there a way to add this option as module parameter and enable the 
biswap via command-line at kernel boot. Is this solution better than 
Kconfig ?
I really need this biswap patch otherwise my previous work will be 
broken. If you told me that module parameter is an acceptable way to 
implement this workaround, I will write the patch.

>
>> Am I correct that all nfc-v1's have that bug, so only imx27 and imx51?
>> The application note we finally got from freescale only mentions "FSL
>> IMX NFC".
>
> s/imx51/imx31/.
>
> Yes, only imx27 and imx31 a affected by this bug.
>
> Sascha
>

Thanks,
Ga?tan Carlier


From lee.jones at linaro.org  Wed Aug  8 12:22:01 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 8 Aug 2012 17:22:01 +0100
Subject: [PATCH 04/11] ARM: ux500: really kill snowball_of_platform_devs
In-Reply-To: <1344437248-20560-5-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-5-git-send-email-arnd@arndb.de>
Message-ID: <20120808162200.GB30473@gmail.com>

On Wed, Aug 08, 2012 at 04:47:21PM +0200, Arnd Bergmann wrote:
> Commit fc67a597a "ARM: ux500: Remove temporary snowball_of_platform_devs
> enablement structure" removed the only user of this variable, but did
> not actually remove the array itself.
> 
> Without this patch, building u8500_defconfig results in:
> 
> arch/arm/mach-ux500/board-mop500.c:729:32: warning: 'snowball_of_platform_devs' defined but not used [-Wunused-variable]

I've already sent a patch that does this:

https://lkml.org/lkml/2012/7/31/305

Just waiting on Linus to review the set.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Wed Aug  8 12:22:29 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 16:22:29 +0000
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <50228889.5060709@wwwdotorg.org>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-12-git-send-email-arnd@arndb.de>
 <50228889.5060709@wwwdotorg.org>
Message-ID: <201208081622.29777.arnd@arndb.de>

On Wednesday 08 August 2012, Stephen Warren wrote:
> On 08/08/2012 08:47 AM, Arnd Bergmann wrote:
> > A few drivers use a construct like
> > 
> >  #ifdef CONFIG_PM
> >  static int foo_suspend(struct device *pdev)
> >  {
> >     ...
> >  }
> >  static int foo_resume struct device *pdev)
> >  {
> >     ...
> >  }
> >  #endif
> >  static SIMPLE_DEV_PM_OPS(foo_pm, foo_suspend, foo_resume);
> ...
> > drivers/i2c/busses/i2c-tegra.c:716:12: warning: 'tegra_i2c_suspend' defined but not used [-Wunused-function]
> > drivers/i2c/busses/i2c-tegra.c:727:12: warning: 'tegra_i2c_resume' defined but not used [-Wunused-function]
> 
> Laxman already posted a patch for this, which I'm hoping will make it
> into 3.6, through the I2C tree.
> 
> http://www.spinics.net/lists/linux-i2c/msg09359.html

Ok, dropping this one then.

Thanks,

	Arnd


From gregory.clement at free-electrons.com  Wed Aug  8 12:22:58 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 18:22:58 +0200
Subject: [RFC] Add support for Aurora L2 Cache Controller
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <50229262.8020005@free-electrons.com>

On 08/08/2012 05:05 PM, Gregory CLEMENT wrote:
> Hello,
> 
> The purpose of this patch set is to add support for Aurora L2 Cache

I am surprised because all the patches are awaiting for moderator approval
with the reason "Message has a suspicious header".
As I used the same "git send-email" command as for my previous
submissions I am puzzled.

I hope to receive an explanation soon to be able to fix it.

Now waiting for the arrivals of the patches, the commits are still
available on branch aurora-L2-cache-ctrl located at
https://github.com/MISL-EBU-System-SW/mainline-public.git

regards,

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:24:43 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:24:43 +0100
Subject: [Xen-devel] [PATCH v2 07/23] xen/arm: Xen detection and
 shared_info page mapping
In-Reply-To: <501FEF65.1000304@citrix.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-7-git-send-email-stefano.stabellini@eu.citrix.com>
 <501FEF65.1000304@citrix.com>
Message-ID: <alpine.DEB.2.02.1208081715550.21096@kaball.uk.xensource.com>

On Mon, 6 Aug 2012, David Vrabel wrote:
> On 06/08/12 15:27, Stefano Stabellini wrote:
> > Check for a "/xen" node in the device tree, if it is present set
> > xen_domain_type to XEN_HVM_DOMAIN and continue initialization.
> > 
> > Map the real shared info page using XENMEM_add_to_physmap with
> > XENMAPSPACE_shared_info.
> > 
> > Changes in v2:
> > 
> > - replace pr_info with pr_debug.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/xen/enlighten.c |   52 ++++++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 52 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index d27c2a6..102d823 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -5,6 +5,9 @@
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> >  #include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> >  
> >  struct start_info _xen_start_info;
> >  struct start_info *xen_start_info = &_xen_start_info;
> > @@ -33,3 +36,52 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
> >  	return -ENOSYS;
> >  }
> >  EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
> > +
> > +/*
> > + * == Xen Device Tree format ==
> > + * - /xen node;
> > + * - compatible "arm,xen";
> > + * - one interrupt for Xen event notifications;
> > + * - one memory region to map the grant_table.
> > + */
> 
> These needs to be documented in Documentation/devicetree/bindings/ and
> should be sent to the devicetree-discuss mailing list for review.

That's a good idea.


> The node should be called 'hypervisor' I think.
> 
> The first word of the compatible string is the vendor/organization that
> defined the binding so should be "xen" here.  This does give a odd
> looking "xen,xen" but we'll have to live with that.
> 
> I'd suggest that the DT provided by the hypervisor or tools give the
> hypercall ABI version in the compatible string as well.  e.g.,
> 
> hypervisor {
>     compatible = "xen,xen-4.3", "xen,xen"
> };

It makes sense, I'll do that.


> I missed the Xen patch that adds this node for dom0.  Can you point me
> to it?

Nope, you didn't miss it: I don't have a patch for Xen yet.


From gregory.clement at free-electrons.com  Wed Aug  8 12:30:26 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 18:30:26 +0200
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <20120808151946.GE4579@mudshark.cambridge.arm.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
Message-ID: <50229422.40305@free-electrons.com>

On 08/08/2012 05:19 PM, Will Deacon wrote:
> On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
>> +static void aurora_pa_range(unsigned long start, unsigned long end,
>> +                       unsigned long offset)
>> +{
> 
> This controller is used by Armada XP right? I think that SoC supports LPAE,
> so please tell me that the above is a mistake and the controller can support
> physical addresses > 32 bits!

Yes indeed this SoC support LPAE.

> 
> If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
> instead of unsigned longs.

Ok I will look at this.

> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:31:13 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:31:13 +0100
Subject: [PATCH v2 01/23] arm: initial Xen support
In-Reply-To: <20120807181017.GF15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807181017.GF15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081730560.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:04PM +0100, Stefano Stabellini wrote:
> > - Basic hypervisor.h and interface.h definitions.
> > - Skeleton enlighten.c, set xen_start_info to an empty struct.
> > - Make xen_initial_domain dependent on the SIF_PRIVILIGED_BIT.
> > 
> > The new code only compiles when CONFIG_XEN is set, that is going to be
> > added to arch/arm/Kconfig in patch #11 "xen/arm: introduce CONFIG_XEN on
> > ARM".
> 
> You can add my Ack, but do one change pls:

Thanks! I'll make the changes.


> > +/* XXX: Move pvclock definitions some place arch independent */
> 
> Just use 'TODO'
> 
> > +struct pvclock_vcpu_time_info {
> > +	u32   version;
> > +	u32   pad0;
> > +	u64   tsc_timestamp;
> > +	u64   system_time;
> > +	u32   tsc_to_system_mul;
> > +	s8    tsc_shift;
> > +	u8    flags;
> > +	u8    pad[2];
> > +} __attribute__((__packed__)); /* 32 bytes */
> > +
> > +struct pvclock_wall_clock {
> > +	u32   version;
> > +	u32   sec;
> > +	u32   nsec;
> > +} __attribute__((__packed__));
> 
> Mention the size and why it is OK to have it be a weird
> size while the one above is nicely padded.
> 
> > +#endif
> > +
> > +#endif /* _ASM_ARM_XEN_INTERFACE_H */
> > diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
> > new file mode 100644
> > index 0000000..0bad594
> > --- /dev/null
> > +++ b/arch/arm/xen/Makefile
> > @@ -0,0 +1 @@
> > +obj-y		:= enlighten.o
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > new file mode 100644
> > index 0000000..d27c2a6
> > --- /dev/null
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -0,0 +1,35 @@
> > +#include <xen/xen.h>
> > +#include <xen/interface/xen.h>
> > +#include <xen/interface/memory.h>
> > +#include <xen/platform_pci.h>
> > +#include <asm/xen/hypervisor.h>
> > +#include <asm/xen/hypercall.h>
> > +#include <linux/module.h>
> > +
> > +struct start_info _xen_start_info;
> > +struct start_info *xen_start_info = &_xen_start_info;
> > +EXPORT_SYMBOL_GPL(xen_start_info);
> > +
> > +enum xen_domain_type xen_domain_type = XEN_NATIVE;
> > +EXPORT_SYMBOL_GPL(xen_domain_type);
> > +
> > +struct shared_info xen_dummy_shared_info;
> > +struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
> > +
> > +DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
> > +
> > +/* XXX: to be removed */
> 
> s/XXX/TODO/ here, and mention pls why it needs to be removed.
> 
> > +__read_mostly int xen_have_vector_callback;
> > +EXPORT_SYMBOL_GPL(xen_have_vector_callback);
> > +
> > +int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
> > +EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
> 


From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:33:09 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:33:09 +0100
Subject: [PATCH v2 03/23] xen/arm: page.h definitions
In-Reply-To: <20120807181322.GG15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-3-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807181322.GG15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081732590.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:06PM +0100, Stefano Stabellini wrote:
> > ARM Xen guests always use paging in hardware, like PV on HVM guests in
> > the X86 world.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> 
> Ack.. with one nitpick
> 
> > +/* XXX: this shouldn't be here */
> 
> .. but its here b/c the frontend drivers are using it (its rolled in
> headers)- even though we won't hit the code path. So for right now
> just punt with this.

Yep, I'll do that.


> > +static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
> > +{
> > +	BUG();
> > +	return NULL;
> > +}
> > +
> > +static inline int m2p_add_override(unsigned long mfn, struct page *page,
> > +		struct gnttab_map_grant_ref *kmap_op)
> > +{
> > +	return 0;
> > +}
> > +
> > +static inline int m2p_remove_override(struct page *page, bool clear_pte)
> > +{
> > +	return 0;
> > +}
> > +
> > +static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > +{
> > +	BUG();
> > +	return false;
> > +}
> > +#endif /* _ASM_ARM_XEN_PAGE_H */
> > -- 
> > 1.7.2.5
> 


From vaibhav.bedia at ti.com  Wed Aug  8 12:34:15 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Wed, 8 Aug 2012 16:34:15 +0000
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
 <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>

Hi Paul,

On Wed, Aug 08, 2012 at 19:35:50, Paul Walmsley wrote:
[...]
> It doesn't seem to me that this would necessarily always be an error.  
> Suppose some init code to create cpsw devices is running on an OMAP3430.  
> Then a omap_hwmod_for_each_by_class() that doesn't locate anything 
> wouldn't be an error, right?
> 

Well, I think a failed lookup operation will be a bit expensive since it
iterates over the whole list of registered hwmods and hence put in the
pr_err(). But I don't see how the SoC specific example that you pointed out
could be handled without putting in cpu_is_* checks in the registration
process itself :(

Would a pr_debug() be ok?

Regards,
Vaibhav B.



From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:38:17 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:38:17 +0100
Subject: [PATCH v2 06/23] xen: missing includes
In-Reply-To: <20120807181457.GJ15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-6-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807181457.GJ15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081737330.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:09PM +0100, Stefano Stabellini wrote:
> > Changes in v2:
> > - remove pvclock hack;
> > - remove include linux/types.h from xen/interface/xen.h.
> 
> I think I can take in my tree now right by itself right? Or do
> you want to keep this in your patchqueue? If so, Ack from me.

Yep, just go ahead and take the patch, thanks.


> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/x86/include/asm/xen/interface.h       |    2 ++
> >  drivers/tty/hvc/hvc_xen.c                  |    2 ++
> >  drivers/xen/grant-table.c                  |    1 +
> >  drivers/xen/xenbus/xenbus_probe_frontend.c |    1 +
> >  include/xen/interface/xen.h                |    1 -
> >  include/xen/privcmd.h                      |    1 +
> >  6 files changed, 7 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> > index cbf0c9d..a93db16 100644
> > --- a/arch/x86/include/asm/xen/interface.h
> > +++ b/arch/x86/include/asm/xen/interface.h
> > @@ -121,6 +121,8 @@ struct arch_shared_info {
> >  #include "interface_64.h"
> >  #endif
> >  
> > +#include <asm/pvclock-abi.h>
> > +
> >  #ifndef __ASSEMBLY__
> >  /*
> >   * The following is all CPU context. Note that the fpu_ctxt block is filled
> > diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
> > index 944eaeb..dc07f56 100644
> > --- a/drivers/tty/hvc/hvc_xen.c
> > +++ b/drivers/tty/hvc/hvc_xen.c
> > @@ -21,6 +21,7 @@
> >  #include <linux/console.h>
> >  #include <linux/delay.h>
> >  #include <linux/err.h>
> > +#include <linux/irq.h>
> >  #include <linux/init.h>
> >  #include <linux/types.h>
> >  #include <linux/list.h>
> > @@ -35,6 +36,7 @@
> >  #include <xen/page.h>
> >  #include <xen/events.h>
> >  #include <xen/interface/io/console.h>
> > +#include <xen/interface/sched.h>
> >  #include <xen/hvc-console.h>
> >  #include <xen/xenbus.h>
> >  
> > diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
> > index 0bfc1ef..1d0d95e 100644
> > --- a/drivers/xen/grant-table.c
> > +++ b/drivers/xen/grant-table.c
> > @@ -47,6 +47,7 @@
> >  #include <xen/interface/memory.h>
> >  #include <xen/hvc-console.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <asm/xen/interface.h>
> >  
> >  #include <asm/pgtable.h>
> >  #include <asm/sync_bitops.h>
> > diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
> > index a31b54d..3159a37 100644
> > --- a/drivers/xen/xenbus/xenbus_probe_frontend.c
> > +++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
> > @@ -21,6 +21,7 @@
> >  #include <xen/xenbus.h>
> >  #include <xen/events.h>
> >  #include <xen/page.h>
> > +#include <xen/xen.h>
> >  
> >  #include <xen/platform_pci.h>
> >  
> > diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> > index a890804..3871e47 100644
> > --- a/include/xen/interface/xen.h
> > +++ b/include/xen/interface/xen.h
> > @@ -10,7 +10,6 @@
> >  #define __XEN_PUBLIC_XEN_H__
> >  
> >  #include <asm/xen/interface.h>
> > -#include <asm/pvclock-abi.h>
> >  
> >  /*
> >   * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
> > diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
> > index 17857fb..4d58881 100644
> > --- a/include/xen/privcmd.h
> > +++ b/include/xen/privcmd.h
> > @@ -35,6 +35,7 @@
> >  
> >  #include <linux/types.h>
> >  #include <linux/compiler.h>
> > +#include <xen/interface/xen.h>
> >  
> >  typedef unsigned long xen_pfn_t;
> >  
> > -- 
> > 1.7.2.5
> 


From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:42:33 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:42:33 +0100
Subject: [PATCH v2 09/23] xen/arm: Introduce xen_ulong_t for unsigned long
In-Reply-To: <20120807181839.GM15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-9-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807181839.GM15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081741331.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:12PM +0100, Stefano Stabellini wrote:
> > All the original Xen headers have xen_ulong_t as unsigned long type, however
> > when they have been imported in Linux, xen_ulong_t has been replaced with
> > unsigned long. That might work for x86 and ia64 but it does not for arm.
> > Bring back xen_ulong_t and let each architecture define xen_ulong_t as they
> > see fit.
> > 
> > Also explicitly size pointers (__DEFINE_GUEST_HANDLE) to 64 bit.
> 
> Looks ok to me.

Considering that I'll have to change it a bit in the next version
(remove the apic_physbase and multicall_entry changes), I won't add your
acked-by here just yet.


> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/include/asm/xen/interface.h  |    8 ++++++--
> >  arch/ia64/include/asm/xen/interface.h |    1 +
> >  arch/x86/include/asm/xen/interface.h  |    1 +
> >  include/xen/interface/memory.h        |   12 ++++++------
> >  include/xen/interface/physdev.h       |    4 ++--
> >  include/xen/interface/version.h       |    2 +-
> >  include/xen/interface/xen.h           |    6 +++---
> >  7 files changed, 20 insertions(+), 14 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
> > index f904dcc..1d3030c 100644
> > --- a/arch/arm/include/asm/xen/interface.h
> > +++ b/arch/arm/include/asm/xen/interface.h
> > @@ -9,8 +9,11 @@
> >  
> >  #include <linux/types.h>
> >  
> > +#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
> > +
> >  #define __DEFINE_GUEST_HANDLE(name, type) \
> > -	typedef type * __guest_handle_ ## name
> > +	typedef struct { union { type *p; uint64_aligned_t q; }; }  \
> > +        __guest_handle_ ## name
> >  
> >  #define DEFINE_GUEST_HANDLE_STRUCT(name) \
> >  	__DEFINE_GUEST_HANDLE(name, struct name)
> > @@ -21,13 +24,14 @@
> >  	do {						\
> >  		if (sizeof(hnd) == 8)			\
> >  			*(uint64_t *)&(hnd) = 0;	\
> > -		(hnd) = val;				\
> > +		(hnd).p = val;				\
> >  	} while (0)
> >  
> >  #ifndef __ASSEMBLY__
> >  /* Explicitly size integers that represent pfns in the interface with
> >   * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
> >  typedef uint64_t xen_pfn_t;
> > +typedef uint64_t xen_ulong_t;
> >  /* Guest handles for primitive C types. */
> >  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
> >  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> > diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
> > index 686464e..7c83445 100644
> > --- a/arch/ia64/include/asm/xen/interface.h
> > +++ b/arch/ia64/include/asm/xen/interface.h
> > @@ -71,6 +71,7 @@
> >   * with Xen so that we could have one ABI that works for 32 and 64 bit
> >   * guests. */
> >  typedef unsigned long xen_pfn_t;
> > +typedef unsigned long xen_ulong_t;
> >  /* Guest handles for primitive C types. */
> >  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
> >  __DEFINE_GUEST_HANDLE(uint, unsigned int);
> > diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
> > index 555f94d..28fc621 100644
> > --- a/arch/x86/include/asm/xen/interface.h
> > +++ b/arch/x86/include/asm/xen/interface.h
> > @@ -51,6 +51,7 @@
> >   * with Xen so that on ARM we can have one ABI that works for 32 and 64
> >   * bit guests. */
> >  typedef unsigned long xen_pfn_t;
> > +typedef unsigned long xen_ulong_t;
> >  /* Guest handles for primitive C types. */
> >  __DEFINE_GUEST_HANDLE(uchar, unsigned char);
> >  __DEFINE_GUEST_HANDLE(uint,  unsigned int);
> > diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> > index abbbff0..b5c3098 100644
> > --- a/include/xen/interface/memory.h
> > +++ b/include/xen/interface/memory.h
> > @@ -34,7 +34,7 @@ struct xen_memory_reservation {
> >      GUEST_HANDLE(xen_pfn_t) extent_start;
> >  
> >      /* Number of extents, and size/alignment of each (2^extent_order pages). */
> > -    unsigned long  nr_extents;
> > +    xen_ulong_t  nr_extents;
> >      unsigned int   extent_order;
> >  
> >      /*
> > @@ -92,7 +92,7 @@ struct xen_memory_exchange {
> >       *     command will be non-zero.
> >       *  5. THIS FIELD MUST BE INITIALISED TO ZERO BY THE CALLER!
> >       */
> > -    unsigned long nr_exchanged;
> > +    xen_ulong_t nr_exchanged;
> >  };
> >  
> >  DEFINE_GUEST_HANDLE_STRUCT(xen_memory_exchange);
> > @@ -148,8 +148,8 @@ DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list);
> >   */
> >  #define XENMEM_machphys_mapping     12
> >  struct xen_machphys_mapping {
> > -    unsigned long v_start, v_end; /* Start and end virtual addresses.   */
> > -    unsigned long max_mfn;        /* Maximum MFN that can be looked up. */
> > +    xen_ulong_t v_start, v_end; /* Start and end virtual addresses.   */
> > +    xen_ulong_t max_mfn;        /* Maximum MFN that can be looked up. */
> >  };
> >  DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mapping_t);
> >  
> > @@ -169,7 +169,7 @@ struct xen_add_to_physmap {
> >      unsigned int space;
> >  
> >      /* Index into source mapping space. */
> > -    unsigned long idx;
> > +    xen_ulong_t idx;
> >  
> >      /* GPFN where the source mapping page should appear. */
> >      xen_pfn_t gpfn;
> > @@ -186,7 +186,7 @@ struct xen_translate_gpfn_list {
> >      domid_t domid;
> >  
> >      /* Length of list. */
> > -    unsigned long nr_gpfns;
> > +    xen_ulong_t nr_gpfns;
> >  
> >      /* List of GPFNs to translate. */
> >      GUEST_HANDLE(ulong) gpfn_list;
> > diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h
> > index 9ce788d..bc3ae14 100644
> > --- a/include/xen/interface/physdev.h
> > +++ b/include/xen/interface/physdev.h
> > @@ -56,7 +56,7 @@ struct physdev_eoi {
> >  #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
> >  struct physdev_pirq_eoi_gmfn {
> >      /* IN */
> > -    unsigned long gmfn;
> > +    xen_ulong_t gmfn;
> >  };
> >  
> >  /*
> > @@ -108,7 +108,7 @@ struct physdev_set_iobitmap {
> >  #define PHYSDEVOP_apic_write		 9
> >  struct physdev_apic {
> >  	/* IN */
> > -	unsigned long apic_physbase;
> > +	xen_ulong_t apic_physbase;
> >  	uint32_t reg;
> >  	/* IN or OUT */
> >  	uint32_t value;
> > diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h
> > index e8b6519..30280c9 100644
> > --- a/include/xen/interface/version.h
> > +++ b/include/xen/interface/version.h
> > @@ -45,7 +45,7 @@ struct xen_changeset_info {
> >  
> >  #define XENVER_platform_parameters 5
> >  struct xen_platform_parameters {
> > -    unsigned long virt_start;
> > +    xen_ulong_t virt_start;
> >  };
> >  
> >  #define XENVER_get_features 6
> > diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
> > index 42834a3..ec32115 100644
> > --- a/include/xen/interface/xen.h
> > +++ b/include/xen/interface/xen.h
> > @@ -274,9 +274,9 @@ DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
> >   * NB. The fields are natural register size for this architecture.
> >   */
> >  struct multicall_entry {
> > -    unsigned long op;
> > -    long result;
> > -    unsigned long args[6];
> > +    xen_ulong_t op;
> > +    xen_ulong_t result;
> > +    xen_ulong_t args[6];
> >  };
> >  DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
> >  
> > -- 
> > 1.7.2.5
> 


From tiwai at suse.de  Wed Aug  8 12:43:34 2012
From: tiwai at suse.de (Takashi Iwai)
Date: Wed, 08 Aug 2012 18:43:34 +0200
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <201208081622.29777.arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-12-git-send-email-arnd@arndb.de>
 <50228889.5060709@wwwdotorg.org> <201208081622.29777.arnd@arndb.de>
Message-ID: <s5hwr19fi6h.wl%tiwai@suse.de>

At Wed, 8 Aug 2012 16:22:29 +0000,
Arnd Bergmann wrote:
> 
> On Wednesday 08 August 2012, Stephen Warren wrote:
> > On 08/08/2012 08:47 AM, Arnd Bergmann wrote:
> > > A few drivers use a construct like
> > > 
> > >  #ifdef CONFIG_PM
> > >  static int foo_suspend(struct device *pdev)
> > >  {
> > >     ...
> > >  }
> > >  static int foo_resume struct device *pdev)
> > >  {
> > >     ...
> > >  }
> > >  #endif
> > >  static SIMPLE_DEV_PM_OPS(foo_pm, foo_suspend, foo_resume);
> > ...
> > > drivers/i2c/busses/i2c-tegra.c:716:12: warning: 'tegra_i2c_suspend' defined but not used [-Wunused-function]
> > > drivers/i2c/busses/i2c-tegra.c:727:12: warning: 'tegra_i2c_resume' defined but not used [-Wunused-function]
> > 
> > Laxman already posted a patch for this, which I'm hoping will make it
> > into 3.6, through the I2C tree.
> > 
> > http://www.spinics.net/lists/linux-i2c/msg09359.html
> 
> Ok, dropping this one then.

I'm going to fix the similar errors in sound tree tomorrow, too.


thanks,

Takashi


From stefano.stabellini at eu.citrix.com  Wed Aug  8 12:51:39 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 17:51:39 +0100
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <50216228.7010407@tycho.nsa.gov>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com> <50216228.7010407@tycho.nsa.gov>
Message-ID: <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Daniel De Graaf wrote:
> On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
> > On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
> >> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> >> an error.
> >>
> >> If Linux is running as an HVM domain and is running as Dom0, use
> >> xenstored_local_init to initialize the xenstore page and event channel.
> >>
> >> Changes in v2:
> >>
> >> - refactor xenbus_init.
> > 
> > Thank you. Lets also CC our friend at NSA who has been doing some work
> > in that area. Daniel are you OK with this change - will it still make
> > PV initial domain with with the MiniOS XenBus driver?
> > 
> > Thanks.
> 
> That case will work, but what this will break is launching the initial domain
> with a Xenstore stub domain already running (see below).
> 
> >>
> >> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> >> ---
> >>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
> >>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
> >>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
> >>  3 files changed, 45 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> >> index 52fe7ad..c5aa55c 100644
> >> --- a/drivers/xen/xenbus/xenbus_comms.c
> >> +++ b/drivers/xen/xenbus/xenbus_comms.c
> >> @@ -224,7 +224,7 @@ int xb_init_comms(void)
> >>  		int err;
> >>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
> >>  						0, "xenbus", &xb_waitq);
> >> -		if (err <= 0) {
> >> +		if (err < 0) {
> >>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
> >>  			return err;
> >>  		}
> > 
> >> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> >> index b793723..a67ccc0 100644
> >> --- a/drivers/xen/xenbus/xenbus_probe.c
> >> +++ b/drivers/xen/xenbus/xenbus_probe.c
> >> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
> >>  	return err;
> >>  }
> >>  
> >> +enum xenstore_init {
> >> +	UNKNOWN,
> >> +	PV,
> >> +	HVM,
> >> +	LOCAL,
> >> +};
> >>  static int __init xenbus_init(void)
> >>  {
> >>  	int err = 0;
> >> +	enum xenstore_init usage = UNKNOWN;
> >> +	uint64_t v = 0;
> >>  
> >>  	if (!xen_domain())
> >>  		return -ENODEV;
> >>  
> >>  	xenbus_ring_ops_init();
> >>  
> >> -	if (xen_hvm_domain()) {
> >> -		uint64_t v = 0;
> >> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> >> -		if (err)
> >> -			goto out_error;
> >> -		xen_store_evtchn = (int)v;
> >> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> >> -		if (err)
> >> -			goto out_error;
> >> -		xen_store_mfn = (unsigned long)v;
> >> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> >> -	} else {
> >> -		xen_store_evtchn = xen_start_info->store_evtchn;
> >> -		xen_store_mfn = xen_start_info->store_mfn;
> >> -		if (xen_store_evtchn)
> >> -			xenstored_ready = 1;
> >> -		else {
> >> +	if (xen_pv_domain())
> >> +		usage = PV;
> >> +	if (xen_hvm_domain())
> >> +		usage = HVM;
> 
> The above is correct for domUs, and is overridden for dom0s:
>
> >> +	if (xen_hvm_domain() && xen_initial_domain())
> >> +		usage = LOCAL;
> >> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
> >> +		usage = LOCAL;
> 
> Instead of these checks, I think it should just be:
> 
> if (!xen_start_info->store_evtchn)
> 	usage = LOCAL;
> 
> Any domain started after xenstore will have store_evtchn set, so if you don't
> have this set, you are either going to be running xenstore locally, or will
> use the ioctl to change it later (and so should still set up everything as if
> it will be running locally).

That would be wrong for an HVM dom0 domain (at least on ARM), because
we don't have a start_info page at all.


> >> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
> >> +		xenstored_ready = 1;
> 
> This part can now just be moved unconditionally into case PV.

What about:

if (xen_pv_domain())
    usage = PV;
if (xen_hvm_domain())
    usage = HVM;
if (!xen_store_evtchn)
    usage = LOCAL;

and moving xenstored_ready in case PV, like you suggested.


From gregory.clement at free-electrons.com  Wed Aug  8 12:52:20 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 18:52:20 +0200
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <50229422.40305@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <50229422.40305@free-electrons.com>
Message-ID: <50229944.60603@free-electrons.com>

On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
> On 08/08/2012 05:19 PM, Will Deacon wrote:
>> On Wed, Aug 08, 2012 at 04:05:03PM +0100, Gregory CLEMENT wrote:
>>> +static void aurora_pa_range(unsigned long start, unsigned long end,
>>> +                       unsigned long offset)
>>> +{
>>
>> This controller is used by Armada XP right? I think that SoC supports LPAE,
>> so please tell me that the above is a mistake and the controller can support
>> physical addresses > 32 bits!
> 
> Yes indeed this SoC support LPAE.

Well Armada XP supports LPAE but don't use any outer cache functions, he works
with the Aurora cache controller on 'system cache'.
Armada 370 uses this outer cache functions but doesn't support LPAE.

But it seem possible to use the Aurora controller as an 'outer cache' on an
Armada XP. In this case we need to handle this case, even if I am not sure when
someone wanted to select this use case.

> 
>>
>> If so, you'll need to hack the cache-l2x0 driver to use phys_addr_t types
>> instead of unsigned longs.
> 
> Ok I will look at this.
> 
>>
>> Will
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
> 
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From matt at genesi-usa.com  Wed Aug  8 12:55:30 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 8 Aug 2012 11:55:30 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120808151555.GE14718@S2101-09.ap.freescale.net>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:15 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Tue, Aug 07, 2012 at 04:46:18PM -0500, Matt Sealey wrote:
>> This device tree only supports the final retail board ("TO3").
>>
>> It is currently feature equivalent to the MX51 Babbage device tree. The
>> following features have been tested and work as well as can be expected:
[snip]
>> +     soc {
>> +             aips at 70000000 {
>> +                     spba at 70000000 {
>> +                             esdhc at 70004000 {
>
> The pinctrl_provide_dummies() in imx51_dt_init() is something to be
> removed.  Then any driver calling pinctrl API will require pinctrl
> set up for the device here.  So please have the pinctrl setup for
> those devices.

Absolutely not. Our pins are muxed in U-Boot as they should be. I
refuse to add pinmux entries
or any setup at all for this. What's stopping this right now is you
need a new U-Boot which we
didn't release or mainline because we are still testing it (old U-Boot
shipped on the boards
cannot boot device tree anyway). While the number of users of this is
limited to everyone in
the office here and a few trusted testers, actually the support here
is meaningless for everyone
else, but we feel it needs to go into the tree so we can track changes
when people changing
bindings and basically be future-thinking. We need the nitpicks, but
in this instance, I will
take a leaf from Russell's book and say I violently disagree with
requiring pinctrl to be set up.
There's no need on MX51 with the current state of the architecture and
we've successfully
tested all pad settings in mainline (and older kernels by stripping
muxing from the kernel)
just relying on gpio_direction and value sets.

We'll have a public U-Boot for this board by the end of next week
probably, and it will do it
right the first time.

>> +                     wdog at 73f98000 {
>> +                             status = "okay";
>> +                     };
>
> Remove it.  I have queued a patch to enable wdog in <soc>.dtsi
> by default.

Okay.

>> +             aips at 80000000 {
>> +                     sdma at 83fb0000 {
>> +                             fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
>> +                     };
>
> Remove it.  I have seen a patch to move this name into <soc>.dtsi
> as default.

BTW I propose we make this somehow a bootloader-stage thing - at least, the SDMA
firmware should be in a location which is dictated not by the kernel
itself, certainly not
the device tree, but packaging and operating system dependent
features. It describes
the board, not the rootfs. As in, depending on the OS booted it may not be
imx/sdma/sdma-imx51.bin or anything like it. Remember device trees are NOT just
for Linux (or Android, which may still put it in a relative path with
that name, but it
may NOT depending on future changes!)

In a boot.scr for modern U-Boot you might just have

setenv bootargs ${bootargs} imx-sdma.firmware="imx/sdma/sdma-imx51.bin"

Or something similar. OS filesystem paths in device tree are absolutely wrong.

>> -dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
>> +dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb imx51-efikamx.dtb
>
> Please have the new entry on the new line like dtb-$(CONFIG_SOC_IMX6Q).
> Yes, we will change dtb-$(CONFIG_MACH_IMX53_DT).

Okay.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From nicolas.pitre at linaro.org  Wed Aug  8 12:56:54 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 8 Aug 2012 12:56:54 -0400 (EDT)
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <20120808160517.GO18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
 <alpine.LFD.2.02.1208080106500.5231@xanadu.home> <5022673A.7060407@ti.com>
 <alpine.LFD.2.02.1208080948210.5231@xanadu.home>
 <20120808160517.GO18957@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1208081248340.5231@xanadu.home>

On Wed, 8 Aug 2012, Russell King - ARM Linux wrote:

> On Wed, Aug 08, 2012 at 09:55:12AM -0400, Nicolas Pitre wrote:
> > On Wed, 8 Aug 2012, Cyril Chemparathy wrote:
> > > Neat macro magic.  Are you thinking that we build this in as a self test in
> > > the code?
> > 
> > For such things, this is never a bad idea to have some test alongside 
> > with the main code, especially if this is extended to more cases in the 
> > future.  It is too easy to break it in subtle ways.
> > 
> > See arch/arm/kernel/kprobes-test*.c for a precedent.
> 
> Done correctly, it shouldn't be a problem, but I wouldn't say that
> arch/arm/kernel/kprobes-test*.c is done correctly.  It's seen quite
> a number of patching attempts since it was introduced for various
> problems, and I've seen quite a number of builds fail for various
> reasons in this file (none which I could be bothered to investigate.)
> 
> When the test code ends up causing more problems than the code it's
> testing, something is definitely wrong.

I think we shouldn't compare the complexity of test code for kprobes and 
test code for runtime patching code.  The former, while more difficult 
to keep compiling, has found loads of issues in the former kprobes code.  
So it certainly paid back many times its cost in maintenance.

My mention of it wasn't about the actual test code implementation, but 
rather about the fact that we do have test code in the tree which can be 
enabled with a config option.

As for build failures with that test code, I'd suggest you simply drop a 
note to Tixy who is normally very responsive.  I randomly enable it 
myself and didn't run into any issues yet.


Nicolas


From dgdegra at tycho.nsa.gov  Wed Aug  8 13:01:36 2012
From: dgdegra at tycho.nsa.gov (Daniel De Graaf)
Date: Wed, 08 Aug 2012 13:01:36 -0400
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com> <50216228.7010407@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
Message-ID: <50229B70.3090507@tycho.nsa.gov>

On 08/08/2012 12:51 PM, Stefano Stabellini wrote:
> On Tue, 7 Aug 2012, Daniel De Graaf wrote:
>> On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
>>> On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
>>>> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
>>>> an error.
>>>>
>>>> If Linux is running as an HVM domain and is running as Dom0, use
>>>> xenstored_local_init to initialize the xenstore page and event channel.
>>>>
>>>> Changes in v2:
>>>>
>>>> - refactor xenbus_init.
>>>
>>> Thank you. Lets also CC our friend at NSA who has been doing some work
>>> in that area. Daniel are you OK with this change - will it still make
>>> PV initial domain with with the MiniOS XenBus driver?
>>>
>>> Thanks.
>>
>> That case will work, but what this will break is launching the initial domain
>> with a Xenstore stub domain already running (see below).
>>
>>>>
>>>> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
>>>> ---
>>>>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
>>>>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
>>>>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
>>>>  3 files changed, 45 insertions(+), 20 deletions(-)
>>>>
>>>> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
>>>> index 52fe7ad..c5aa55c 100644
>>>> --- a/drivers/xen/xenbus/xenbus_comms.c
>>>> +++ b/drivers/xen/xenbus/xenbus_comms.c
>>>> @@ -224,7 +224,7 @@ int xb_init_comms(void)
>>>>  		int err;
>>>>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
>>>>  						0, "xenbus", &xb_waitq);
>>>> -		if (err <= 0) {
>>>> +		if (err < 0) {
>>>>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
>>>>  			return err;
>>>>  		}
>>>
>>>> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
>>>> index b793723..a67ccc0 100644
>>>> --- a/drivers/xen/xenbus/xenbus_probe.c
>>>> +++ b/drivers/xen/xenbus/xenbus_probe.c
>>>> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
>>>>  	return err;
>>>>  }
>>>>  
>>>> +enum xenstore_init {
>>>> +	UNKNOWN,
>>>> +	PV,
>>>> +	HVM,
>>>> +	LOCAL,
>>>> +};
>>>>  static int __init xenbus_init(void)
>>>>  {
>>>>  	int err = 0;
>>>> +	enum xenstore_init usage = UNKNOWN;
>>>> +	uint64_t v = 0;
>>>>  
>>>>  	if (!xen_domain())
>>>>  		return -ENODEV;
>>>>  
>>>>  	xenbus_ring_ops_init();
>>>>  
>>>> -	if (xen_hvm_domain()) {
>>>> -		uint64_t v = 0;
>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
>>>> -		if (err)
>>>> -			goto out_error;
>>>> -		xen_store_evtchn = (int)v;
>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
>>>> -		if (err)
>>>> -			goto out_error;
>>>> -		xen_store_mfn = (unsigned long)v;
>>>> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
>>>> -	} else {
>>>> -		xen_store_evtchn = xen_start_info->store_evtchn;
>>>> -		xen_store_mfn = xen_start_info->store_mfn;
>>>> -		if (xen_store_evtchn)
>>>> -			xenstored_ready = 1;
>>>> -		else {
>>>> +	if (xen_pv_domain())
>>>> +		usage = PV;
>>>> +	if (xen_hvm_domain())
>>>> +		usage = HVM;
>>
>> The above is correct for domUs, and is overridden for dom0s:
>>
>>>> +	if (xen_hvm_domain() && xen_initial_domain())
>>>> +		usage = LOCAL;
>>>> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
>>>> +		usage = LOCAL;
>>
>> Instead of these checks, I think it should just be:
>>
>> if (!xen_start_info->store_evtchn)
>> 	usage = LOCAL;
>>
>> Any domain started after xenstore will have store_evtchn set, so if you don't
>> have this set, you are either going to be running xenstore locally, or will
>> use the ioctl to change it later (and so should still set up everything as if
>> it will be running locally).
> 
> That would be wrong for an HVM dom0 domain (at least on ARM), because
> we don't have a start_info page at all.
> 
> 
>>>> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
>>>> +		xenstored_ready = 1;
>>
>> This part can now just be moved unconditionally into case PV.
> 
> What about:
> 
> if (xen_pv_domain())
>     usage = PV;
> if (xen_hvm_domain())
>     usage = HVM;
> if (!xen_store_evtchn)
>     usage = LOCAL;
> 
> and moving xenstored_ready in case PV, like you suggested.
> 

That looks correct, but you'd need to split up the switch statement in
order to populate xen_store_evtchn before that last condition, which
ends up pretty much eliminating the usage variable.



From khilman at ti.com  Wed Aug  8 13:06:54 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 10:06:54 -0700
Subject: [PATCH v2] Revert "ARM: OMAP3: PM: call pre/post transition per
 powerdomain"
In-Reply-To: <CANOLnONQhqYcqW8ZAfn+5ceZQ_h2W_yKZVZrnrP5cUJDooTrQg@mail.gmail.com>
 (Grazvydas Ignotas's message of "Wed, 8 Aug 2012 13:56:33 +0300")
References: <1344379659-26152-1-git-send-email-khilman@ti.com>
 <CANOLnONQhqYcqW8ZAfn+5ceZQ_h2W_yKZVZrnrP5cUJDooTrQg@mail.gmail.com>
Message-ID: <87sjbxwbwx.fsf@ti.com>

Grazvydas Ignotas <notasas at gmail.com> writes:

> On Wed, Aug 8, 2012 at 1:47 AM, Kevin Hilman <khilman at ti.com> wrote:
>> This reverts commit 58f0829b7186150318c79515f0e0850c5e7a9c89.
>>
>> Converstion to per-pwrdm per/post transition calls was a bit
>> premature.  Only tracking MPU, PER & CORE in the idle path means we
>> lose the accounting for all the other powerdomains which may also
>> transition in idle.  On OMAP3, due to autodeps, several powerdomains
>> transition along with MPU (e.g. DSS, USBHOST), and the accounting for
>> these was lost with this patch.  Since the accounting includes the
>> context loss counters, drivers for devices in those power domains
>> would never notice context lost, so would likely hang after any
>> off-mode transitions.
>
> That's a shame, pwrdm_pre_transition/pwrdm_post_transition are the
> main contributors to idle latency and cause large performance loss on
> small and frequent loads, like short DMAs. Could we perhaps only do it
> when PM_DEBUG is on or when off transitions happen instead?

Unfortunately, that's also where we're currently doing the accounting 
for when power domains lose context.  Drivers rely on this to determine
whether or not to restore context, so it's not a debug only feature.

>> This patch should be revisited when the upcoming clkdm/pwrmdm/voltdm
>> use-counting seires is merged since then we can properly do accounting
>> without relying on a call in the idle path.
>
> So all hope of getting rid of those pre/post transition calls goes here then?
> Small typo with 'seires'..

Yes.  The goal of the use-counting series is so that proper accounting
can be done when the usecount changes so that not all of them have to be
done in the idle path.

Kevin

>> In addition, the original patch had another bug because the PER
>> powerdomain accounting was not updated until after the GPIO resume
>> hook is called.  Since gpio_resume_after_idle() checks the context
>> loss count (which is not yet updated) it would not properly restore
>> context, leaving the GPIO banks in an undefined state.
>>
>> Cc: Jean Pihet <jean.pihet at newoldbits.com>
>> Cc: Tero Kristo <t-kristo at ti.com>
>> Cc: Rajendra Nayak <rnayak at ti.com>
>> Reported-by: Paul Walmsley <paul at pwsan.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>> ---
>>  arch/arm/mach-omap2/pm34xx.c |   19 ++++---------------
>>  1 file changed, 4 insertions(+), 15 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index e4fc88c..05bd8f0 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -272,21 +272,16 @@ void omap_sram_idle(void)
>>         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
>>         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
>>
>> -       if (mpu_next_state < PWRDM_POWER_ON) {
>> -               pwrdm_pre_transition(mpu_pwrdm);
>> -               pwrdm_pre_transition(neon_pwrdm);
>> -       }
>> +       pwrdm_pre_transition(NULL);
>>
>>         /* PER */
>>         if (per_next_state < PWRDM_POWER_ON) {
>> -               pwrdm_pre_transition(per_pwrdm);
>>                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
>>                 omap2_gpio_prepare_for_idle(per_going_off);
>>         }
>>
>>         /* CORE */
>>         if (core_next_state < PWRDM_POWER_ON) {
>> -               pwrdm_pre_transition(core_pwrdm);
>>                 if (core_next_state == PWRDM_POWER_OFF) {
>>                         omap3_core_save_context();
>>                         omap3_cm_save_context();
>> @@ -339,20 +334,14 @@ void omap_sram_idle(void)
>>                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
>>                                                OMAP3430_GR_MOD,
>>                                                OMAP3_PRM_VOLTCTRL_OFFSET);
>> -               pwrdm_post_transition(core_pwrdm);
>>         }
>>         omap3_intc_resume_idle();
>>
>> +       pwrdm_post_transition(NULL);
>> +
>>         /* PER */
>> -       if (per_next_state < PWRDM_POWER_ON) {
>> +       if (per_next_state < PWRDM_POWER_ON)
>>                 omap2_gpio_resume_after_idle();
>> -               pwrdm_post_transition(per_pwrdm);
>> -       }
>> -
>> -       if (mpu_next_state < PWRDM_POWER_ON) {
>> -               pwrdm_post_transition(mpu_pwrdm);
>> -               pwrdm_post_transition(neon_pwrdm);
>> -       }
>>  }
>>
>>  static void omap3_pm_idle(void)
>> --
>> 1.7.9.2
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From khilman at ti.com  Wed Aug  8 13:10:07 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 10:10:07 -0700
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Wed, 8 Aug 2012 19:28:36 +0530")
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <87k3x9wbrk.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> Add *remove* callback so that necessary cleanup operations are
> performed when device is unregistered. The device is deleted
> from the list and associated clock handle is released by
> calling clk_put() and irq descriptor is released using the
> irq_free_desc() api.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Reported-by: Paul Walmsley <paul at pwsan.com>
> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Cousson, Benoit <b-cousson at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> ---
> v2:
> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>
> (1) Use irq_free_descs() instead of irq_free_desc().
>     Besides, irq_free_desc() was using wrong parameter,
>     irq_base, instead of bank->irq.
> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>     in order to avoid exception warnings.
>
> (3) pm_runtime_disable() added so that bind can happen successfully
>
> Test Detail:
> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>
> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>
> Step 3: Execute read/write GPIO test case.

What happens when GPIOs are in use (requested)?   

Kevin

>  drivers/gpio/gpio-omap.c |   35 +++++++++++++++++++++++++++++++++++
>  1 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index e6efd77..50de875 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1152,6 +1152,40 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>  	return ret;
>  }
>  
> +/**
> + * omap_gpio_remove - cleanup a registered gpio device
> + * @pdev:       pointer to current gpio platform device
> + *
> + * Called by driver framework whenever a gpio device is unregistered.
> + * GPIO is deleted from the list and associated clock handle freed.
> + */
> +static int __devexit omap_gpio_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct gpio_bank *bank;
> +	unsigned long flags;
> +	int ret = -EINVAL;
> +
> +	list_for_each_entry(bank, &omap_gpio_list, node) {
> +		spin_lock_irqsave(&bank->lock, flags);
> +		if (bank->dev == dev) {
> +			clk_put(bank->dbck);
> +			list_del(&bank->node);
> +			ret = 0;
> +			spin_unlock_irqrestore(&bank->lock, flags);
> +			break;
> +		}
> +		spin_unlock_irqrestore(&bank->lock, flags);
> +	}
> +
> +	if (!ret) {
> +		pm_runtime_disable(bank->dev);
> +		irq_free_descs(bank->irq_base, bank->width);
> +	}
> +
> +	return ret;
> +}
> +
>  #ifdef CONFIG_ARCH_OMAP2PLUS
>  
>  #if defined(CONFIG_PM_RUNTIME)
> @@ -1478,6 +1512,7 @@ MODULE_DEVICE_TABLE(of, omap_gpio_match);
>  
>  static struct platform_driver omap_gpio_driver = {
>  	.probe		= omap_gpio_probe,
> +	.remove = __devexit_p(omap_gpio_remove),
>  	.driver		= {
>  		.name	= "omap_gpio",
>  		.pm	= &gpio_pm_ops,


From khilman at ti.com  Wed Aug  8 13:15:20 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 10:15:20 -0700
Subject: [PATCH] ARM: OMAP4: sleep: Save the complete used register stack
 frame
In-Reply-To: <1342183715-13734-1-git-send-email-santosh.shilimkar@ti.com>
 (Santosh Shilimkar's message of "Fri, 13 Jul 2012 18:18:34 +0530")
References: <1342183715-13734-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <87d331wbiv.fsf@ti.com>

Santosh Shilimkar <santosh.shilimkar at ti.com> writes:

> OMAP4 sleep entry code even though itself don't use many CPU registers
> makes call to the v7_flush_dcache_all() which uses them. Since
> v7_flush_dcache_all() doesn't make use of stack, the caller must take
> care of the stack frame. Otherwise it will lead to corrupted stack frame.
>
> Fix it by saving used registers.
>
> Reported-by: Grygorii Strashko <grygorii.strashko at ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>

Please add a brief comment in the code as well explaining why the
additional registers are saved/restored.

After that, I'll add to my PM fixes queue for v3.6-rc.

Thanks for the fix.

Kevin

> ---
>  arch/arm/mach-omap2/sleep44xx.S |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
> index 9f6b83d..b5823e9 100644
> --- a/arch/arm/mach-omap2/sleep44xx.S
> +++ b/arch/arm/mach-omap2/sleep44xx.S
> @@ -58,7 +58,7 @@ ppa_por_params:
>   * CPU failed to transition to targeted OFF/DORMANT state.
>   */
>  ENTRY(omap4_finish_suspend)
> -	stmfd	sp!, {lr}
> +	stmfd	sp!, {r4-r12, lr}
>  	cmp	r0, #0x0
>  	beq	do_WFI				@ No lowpower state, jump to WFI
>  
> @@ -226,7 +226,7 @@ scu_gp_clear:
>  skip_scu_gp_clear:
>  	isb
>  	dsb
> -	ldmfd	sp!, {pc}
> +	ldmfd	sp!, {r4-r12, pc}
>  ENDPROC(omap4_finish_suspend)
>  
>  /*


From khilman at ti.com  Wed Aug  8 13:18:48 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 10:18:48 -0700
Subject: [PATCH 2/2] ARM: OMAP4: Register the OPP table only for 4430
 device
In-Reply-To: <1344423254-3475-3-git-send-email-rnayak@ti.com> (Rajendra
 Nayak's message of "Wed, 8 Aug 2012 16:24:14 +0530")
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-3-git-send-email-rnayak@ti.com>
Message-ID: <87628twbd3.fsf@ti.com>

Rajendra Nayak <rnayak at ti.com> writes:

> The 4430 OPP table was being registered for all other OMAP4 variants
> too, like 4460 and 4470 causing issues with cpufreq driver
> enabled. 4460 and 4470 devices have different OPPs as compared to
> 4430, and they should be populated seperately. As long as that
> happens, let the OPP table registeration happen only on 4430 device.
>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>

Thanks, adding to PM fixes for v3.6-rc (branch: for_3.6/fixes/pm)

Kevin

> ---
>  arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
> index 2293ba2..c95415d 100644
> --- a/arch/arm/mach-omap2/opp4xxx_data.c
> +++ b/arch/arm/mach-omap2/opp4xxx_data.c
> @@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
>  {
>  	int r = -ENODEV;
>  
> -	if (!cpu_is_omap44xx())
> +	if (!cpu_is_omap443x())
>  		return r;
>  
>  	r = omap_init_opp_table(omap44xx_opp_def_list,


From marvin24 at gmx.de  Wed Aug  8 13:19:05 2012
From: marvin24 at gmx.de (Marc Dietrich)
Date: Wed, 08 Aug 2012 19:19:05 +0200
Subject: [PATCH 2/3] ARM: tegra: remove board (but not DT) support for
 Paz00
In-Reply-To: <1344288734-24131-2-git-send-email-swarren@wwwdotorg.org>
References: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
 <1344288734-24131-2-git-send-email-swarren@wwwdotorg.org>
Message-ID: <2039432.1G46MzXUkA@ax5200p>

On Monday 06 August 2012 15:32:13 Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> Paz00 (Toshiba AC100) can be booted using device tree with equal
> functionality as when booted using a board file. Remove as much of the
> board file as is possible, since it's no longer needed.
> 
> One special-case is still left in board-dt-tegra20.c, since there is no
> way to create a WiFi rfkill device from device tree yet. This logic is
> now enabled unconditionally rather than via CONFIG_MACH_PAZ00. The extra
> cases where it's enabled (.configs which did not enable Paz00 support)
> shouldn't impact much since the amount of code is tiny.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

works fine here. Thanks for all your work to make this happen!

Acked-By: Marc Dietrich <marvin24 at gmx.de>


> ---
>  arch/arm/mach-tegra/Kconfig              |    6 -
>  arch/arm/mach-tegra/Makefile             |    3 +-
>  arch/arm/mach-tegra/board-dt-tegra20.c   |    4 -
>  arch/arm/mach-tegra/board-paz00-pinmux.c |  156 ------------------------
>  arch/arm/mach-tegra/board-paz00.c        |  192
> ------------------------------ arch/arm/mach-tegra/board-paz00.h        |  
> 17 +---
>  6 files changed, 2 insertions(+), 376 deletions(-)
>  delete mode 100644 arch/arm/mach-tegra/board-paz00-pinmux.c
> 
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 41bc73c..f6e79ed 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -66,12 +66,6 @@ config MACH_HARMONY
>         help
>           Support for nVidia Harmony development platform
> 
> -config MACH_PAZ00
> -       bool "Paz00 board"
> -       depends on ARCH_TEGRA_2x_SOC
> -       help
> -         Support for the Toshiba AC100/Dynabook AZ netbook
> -
>  choice
>          prompt "Default low-level debug console UART"
>          default TEGRA_DEBUG_UART_NONE
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index 88ddb75..1c2b473 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -31,5 +31,4 @@ obj-$(CONFIG_MACH_HARMONY)              +=
> board-harmony-pinmux.o obj-$(CONFIG_MACH_HARMONY)              +=
> board-harmony-pcie.o
>  obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
> 
> -obj-$(CONFIG_MACH_PAZ00)		+= board-paz00.o
> -obj-$(CONFIG_MACH_PAZ00)		+= board-paz00-pinmux.o
> +obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o
> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c
> b/arch/arm/mach-tegra/board-dt-tegra20.c index 422e89e..1d6c9df 100644
> --- a/arch/arm/mach-tegra/board-dt-tegra20.c
> +++ b/arch/arm/mach-tegra/board-dt-tegra20.c
> @@ -124,12 +124,10 @@ static void __init harmony_init(void)
>  }
>  #endif
> 
> -#ifdef CONFIG_MACH_PAZ00
>  static void __init paz00_init(void)
>  {
>  	tegra_paz00_wifikill_init();
>  }
> -#endif
> 
>  static struct {
>  	char *machine;
> @@ -139,9 +137,7 @@ static struct {
>  #ifdef CONFIG_MACH_HARMONY
>  	{ "nvidia,harmony", harmony_init },
>  #endif
> -#ifdef CONFIG_MACH_PAZ00
>  	{ "compal,paz00", paz00_init },
> -#endif
>  };
> 
>  static void __init tegra_dt_init_late(void)
> diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c
> b/arch/arm/mach-tegra/board-paz00-pinmux.c deleted file mode 100644
> index 6f1111b..0000000
> --- a/arch/arm/mach-tegra/board-paz00-pinmux.c
> +++ /dev/null
> @@ -1,156 +0,0 @@
> -/*
> - * arch/arm/mach-tegra/board-paz00-pinmux.c
> - *
> - * Copyright (C) 2010 Marc Dietrich <marvin24 at gmx.de>
> - * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
> - *
> - * This software is licensed under the terms of the GNU General Public
> - * License version 2, as published by the Free Software Foundation, and
> - * may be copied, distributed, and modified under those terms.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -#include <linux/kernel.h>
> -
> -#include "board-paz00.h"
> -#include "board-pinmux.h"
> -
> -static struct pinctrl_map paz00_map[] = {
> -	TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
> -	TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
> -	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
> -	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
> -	TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
> -	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
> -	TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
> -	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
> -	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
> -	TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
> -	TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
> -	TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
> -	TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
> -	TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
> -	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
> -	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
> -	TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
> -	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
> -	TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
> -	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
> -	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
> -	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
> -	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
> -	TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
> -	TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
> -	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
> -	TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
> -	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
> -	TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
> -	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
> -	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
> -	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
> -	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
> -	TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
> -	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
> -	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
> -	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
> -	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
> -	TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
> -	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
> -	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
> -	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
> -	TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
> -	TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
> -	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
> -	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
> -	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
> -	TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
> -	TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
> -	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
> -	TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
> -	TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
> -	TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
> -	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
> -	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
> -	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
> -	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
> -	TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
> -	TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
> -	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
> -	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
> -	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
> -	TEGRA_MAP_CONF("ck32",    none, na),
> -	TEGRA_MAP_CONF("ddrc",    none, na),
> -	TEGRA_MAP_CONF("pmca",    none, na),
> -	TEGRA_MAP_CONF("pmcb",    none, na),
> -	TEGRA_MAP_CONF("pmcc",    none, na),
> -	TEGRA_MAP_CONF("pmcd",    none, na),
> -	TEGRA_MAP_CONF("pmce",    none, na),
> -	TEGRA_MAP_CONF("xm2c",    none, na),
> -	TEGRA_MAP_CONF("xm2d",    none, na),
> -	TEGRA_MAP_CONF("ls",      up,   na),
> -	TEGRA_MAP_CONF("lc",      up,   na),
> -	TEGRA_MAP_CONF("ld17_0",  down, na),
> -	TEGRA_MAP_CONF("ld19_18", down, na),
> -	TEGRA_MAP_CONF("ld21_20", down, na),
> -	TEGRA_MAP_CONF("ld23_22", down, na),
> -};
> -
> -static struct tegra_board_pinmux_conf conf = {
> -	.maps = paz00_map,
> -	.map_count = ARRAY_SIZE(paz00_map),
> -};
> -
> -void paz00_pinmux_init(void)
> -{
> -	tegra_board_pinmux_init(&conf, NULL);
> -}
> diff --git a/arch/arm/mach-tegra/board-paz00.c
> b/arch/arm/mach-tegra/board-paz00.c index 4b64af5..5930551 100644
> --- a/arch/arm/mach-tegra/board-paz00.c
> +++ b/arch/arm/mach-tegra/board-paz00.c
> @@ -17,72 +17,10 @@
>   *
>   */
> 
> -#include <linux/kernel.h>
> -#include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/serial_8250.h>
> -#include <linux/of_serial.h>
> -#include <linux/clk.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/gpio_keys.h>
> -#include <linux/pda_power.h>
> -#include <linux/io.h>
> -#include <linux/input.h>
> -#include <linux/i2c.h>
> -#include <linux/gpio.h>
>  #include <linux/rfkill-gpio.h>
> 
> -#include <asm/hardware/gic.h>
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> -#include <asm/mach/time.h>
> -#include <asm/setup.h>
> -
> -#include <mach/iomap.h>
> -#include <mach/irqs.h>
> -#include <mach/sdhci.h>
> -
> -#include "board.h"
>  #include "board-paz00.h"
> -#include "clock.h"
> -#include "devices.h"
> -#include "gpio-names.h"
> -
> -static struct plat_serial8250_port debug_uart_platform_data[] = {
> -	{
> -		/* serial port on JP1 */
> -		.membase	= IO_ADDRESS(TEGRA_UARTA_BASE),
> -		.mapbase	= TEGRA_UARTA_BASE,
> -		.irq		= INT_UARTA,
> -		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
> -		.type		= PORT_TEGRA,
> -		.handle_break	= tegra_serial_handle_break,
> -		.iotype		= UPIO_MEM,
> -		.regshift	= 2,
> -		.uartclk	= 216000000,
> -	}, {
> -		/* serial port on mini-pcie */
> -		.membase	= IO_ADDRESS(TEGRA_UARTC_BASE),
> -		.mapbase	= TEGRA_UARTC_BASE,
> -		.irq		= INT_UARTC,
> -		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
> -		.type		= PORT_TEGRA,
> -		.handle_break	= tegra_serial_handle_break,
> -		.iotype		= UPIO_MEM,
> -		.regshift	= 2,
> -		.uartclk	= 216000000,
> -	}, {
> -		.flags		= 0
> -	}
> -};
> -
> -static struct platform_device debug_uart = {
> -	.name = "serial8250",
> -	.id = PLAT8250_DEV_PLATFORM,
> -	.dev = {
> -		.platform_data = debug_uart_platform_data,
> -	},
> -};
> 
>  static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
>  	.name		= "wifi_rfkill",
> @@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
>  	},
>  };
> 
> -static struct gpio_led gpio_leds[] = {
> -	{
> -		.name			= "wifi-led",
> -		.default_trigger	= "rfkill0",
> -		.gpio			= TEGRA_WIFI_LED,
> -	},
> -};
> -
> -static struct gpio_led_platform_data gpio_led_info = {
> -	.leds		= gpio_leds,
> -	.num_leds	= ARRAY_SIZE(gpio_leds),
> -};
> -
> -static struct platform_device leds_gpio = {
> -	.name	= "leds-gpio",
> -	.id	= -1,
> -	.dev	= {
> -		.platform_data = &gpio_led_info,
> -        },
> -};
> -
> -static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
> -	{
> -		.code		= KEY_POWER,
> -		.gpio		= TEGRA_GPIO_POWERKEY,
> -		.active_low	= 1,
> -		.desc		= "Power",
> -		.type		= EV_KEY,
> -		.wakeup		= 1,
> -	},
> -};
> -
> -static struct gpio_keys_platform_data paz00_gpio_keys = {
> -	.buttons	= paz00_gpio_keys_buttons,
> -	.nbuttons	= ARRAY_SIZE(paz00_gpio_keys_buttons),
> -};
> -
> -static struct platform_device gpio_keys_device = {
> -	.name	= "gpio-keys",
> -	.id	= -1,
> -	.dev	= {
> -		.platform_data = &paz00_gpio_keys,
> -	},
> -};
> -
> -static struct platform_device *paz00_devices[] __initdata = {
> -	&debug_uart,
> -	&tegra_sdhci_device4,
> -	&tegra_sdhci_device1,
> -	&leds_gpio,
> -	&gpio_keys_device,
> -};
> -
> -static void paz00_i2c_init(void)
> -{
> -	platform_device_register(&tegra_i2c_device1);
> -	platform_device_register(&tegra_i2c_device2);
> -	platform_device_register(&tegra_i2c_device4);
> -}
> -
> -static void paz00_usb_init(void)
> -{
> -	tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
> -
> -	platform_device_register(&tegra_ehci2_device);
> -	platform_device_register(&tegra_ehci3_device);
> -}
> -
> -static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
> -	struct meminfo *mi)
> -{
> -	mi->nr_banks = 1;
> -	mi->bank[0].start = PHYS_OFFSET;
> -	mi->bank[0].size = 448 * SZ_1M;
> -}
> -
> -static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
> -	/* name		parent		rate		enabled */
> -	{ "uarta",	"pll_p",	216000000,	true },
> -	{ "uartc",	"pll_p",	216000000,	true },
> -
> -	{ "usbd",	"clk_m",	12000000,	false },
> -	{ "usb2",	"clk_m",	12000000,	false },
> -	{ "usb3",	"clk_m",	12000000,	false },
> -
> -	{ NULL,		NULL,		0,		0},
> -};
> -
> -static struct tegra_sdhci_platform_data sdhci_pdata1 = {
> -	.cd_gpio	= TEGRA_GPIO_SD1_CD,
> -	.wp_gpio	= TEGRA_GPIO_SD1_WP,
> -	.power_gpio	= TEGRA_GPIO_SD1_POWER,
> -};
> -
> -static struct tegra_sdhci_platform_data sdhci_pdata4 = {
> -	.cd_gpio	= -1,
> -	.wp_gpio	= -1,
> -	.power_gpio	= -1,
> -	.is_8bit	= 1,
> -};
> -
>  void __init tegra_paz00_wifikill_init(void)
>  {
>  	platform_device_register(&wifi_rfkill_device);
>  }
> -
> -static void __init tegra_paz00_init(void)
> -{
> -	tegra_clk_init_from_table(paz00_clk_init_table);
> -
> -	paz00_pinmux_init();
> -
> -	tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
> -	tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
> -
> -	platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
> -	tegra_paz00_wifikill_init();
> -
> -	paz00_i2c_init();
> -	paz00_usb_init();
> -}
> -
> -MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
> -	.atag_offset	= 0x100,
> -	.fixup		= tegra_paz00_fixup,
> -	.map_io         = tegra_map_common_io,
> -	.init_early	= tegra20_init_early,
> -	.init_irq       = tegra_init_irq,
> -	.handle_irq	= gic_handle_irq,
> -	.timer          = &tegra_timer,
> -	.init_machine   = tegra_paz00_init,
> -	.init_late	= tegra_init_late,
> -	.restart	= tegra_assert_system_reset,
> -MACHINE_END
> diff --git a/arch/arm/mach-tegra/board-paz00.h
> b/arch/arm/mach-tegra/board-paz00.h index 3c9f8da..25c08ec 100644
> --- a/arch/arm/mach-tegra/board-paz00.h
> +++ b/arch/arm/mach-tegra/board-paz00.h
> @@ -17,24 +17,9 @@
>  #ifndef _MACH_TEGRA_BOARD_PAZ00_H
>  #define _MACH_TEGRA_BOARD_PAZ00_H
> 
> -#include <mach/gpio-tegra.h>
> +#include "gpio-names.h"
> 
> -/* SDCARD */
> -#define TEGRA_GPIO_SD1_CD		TEGRA_GPIO_PV5
> -#define TEGRA_GPIO_SD1_WP		TEGRA_GPIO_PH1
> -#define TEGRA_GPIO_SD1_POWER		TEGRA_GPIO_PV1
> -
> -/* ULPI */
> -#define TEGRA_ULPI_RST			TEGRA_GPIO_PV0
> -
> -/* WIFI */
>  #define TEGRA_WIFI_PWRN			TEGRA_GPIO_PK5
>  #define TEGRA_WIFI_RST			TEGRA_GPIO_PD1
> -#define TEGRA_WIFI_LED			TEGRA_GPIO_PD0
> -
> -/* WakeUp */
> -#define TEGRA_GPIO_POWERKEY	TEGRA_GPIO_PJ7
> -
> -void paz00_pinmux_init(void);
> 
>  #endif


From stefano.stabellini at eu.citrix.com  Wed Aug  8 13:19:08 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 18:19:08 +0100
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <50229B70.3090507@tycho.nsa.gov>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com> <50216228.7010407@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
 <50229B70.3090507@tycho.nsa.gov>
Message-ID: <alpine.DEB.2.02.1208081805520.21096@kaball.uk.xensource.com>

On Wed, 8 Aug 2012, Daniel De Graaf wrote:
> On 08/08/2012 12:51 PM, Stefano Stabellini wrote:
> > On Tue, 7 Aug 2012, Daniel De Graaf wrote:
> >> On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
> >>> On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
> >>>> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> >>>> an error.
> >>>>
> >>>> If Linux is running as an HVM domain and is running as Dom0, use
> >>>> xenstored_local_init to initialize the xenstore page and event channel.
> >>>>
> >>>> Changes in v2:
> >>>>
> >>>> - refactor xenbus_init.
> >>>
> >>> Thank you. Lets also CC our friend at NSA who has been doing some work
> >>> in that area. Daniel are you OK with this change - will it still make
> >>> PV initial domain with with the MiniOS XenBus driver?
> >>>
> >>> Thanks.
> >>
> >> That case will work, but what this will break is launching the initial domain
> >> with a Xenstore stub domain already running (see below).
> >>
> >>>>
> >>>> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> >>>> ---
> >>>>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
> >>>>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
> >>>>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
> >>>>  3 files changed, 45 insertions(+), 20 deletions(-)
> >>>>
> >>>> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> >>>> index 52fe7ad..c5aa55c 100644
> >>>> --- a/drivers/xen/xenbus/xenbus_comms.c
> >>>> +++ b/drivers/xen/xenbus/xenbus_comms.c
> >>>> @@ -224,7 +224,7 @@ int xb_init_comms(void)
> >>>>  		int err;
> >>>>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
> >>>>  						0, "xenbus", &xb_waitq);
> >>>> -		if (err <= 0) {
> >>>> +		if (err < 0) {
> >>>>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
> >>>>  			return err;
> >>>>  		}
> >>>
> >>>> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> >>>> index b793723..a67ccc0 100644
> >>>> --- a/drivers/xen/xenbus/xenbus_probe.c
> >>>> +++ b/drivers/xen/xenbus/xenbus_probe.c
> >>>> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
> >>>>  	return err;
> >>>>  }
> >>>>  
> >>>> +enum xenstore_init {
> >>>> +	UNKNOWN,
> >>>> +	PV,
> >>>> +	HVM,
> >>>> +	LOCAL,
> >>>> +};
> >>>>  static int __init xenbus_init(void)
> >>>>  {
> >>>>  	int err = 0;
> >>>> +	enum xenstore_init usage = UNKNOWN;
> >>>> +	uint64_t v = 0;
> >>>>  
> >>>>  	if (!xen_domain())
> >>>>  		return -ENODEV;
> >>>>  
> >>>>  	xenbus_ring_ops_init();
> >>>>  
> >>>> -	if (xen_hvm_domain()) {
> >>>> -		uint64_t v = 0;
> >>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> >>>> -		if (err)
> >>>> -			goto out_error;
> >>>> -		xen_store_evtchn = (int)v;
> >>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> >>>> -		if (err)
> >>>> -			goto out_error;
> >>>> -		xen_store_mfn = (unsigned long)v;
> >>>> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> >>>> -	} else {
> >>>> -		xen_store_evtchn = xen_start_info->store_evtchn;
> >>>> -		xen_store_mfn = xen_start_info->store_mfn;
> >>>> -		if (xen_store_evtchn)
> >>>> -			xenstored_ready = 1;
> >>>> -		else {
> >>>> +	if (xen_pv_domain())
> >>>> +		usage = PV;
> >>>> +	if (xen_hvm_domain())
> >>>> +		usage = HVM;
> >>
> >> The above is correct for domUs, and is overridden for dom0s:
> >>
> >>>> +	if (xen_hvm_domain() && xen_initial_domain())
> >>>> +		usage = LOCAL;
> >>>> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
> >>>> +		usage = LOCAL;
> >>
> >> Instead of these checks, I think it should just be:
> >>
> >> if (!xen_start_info->store_evtchn)
> >> 	usage = LOCAL;
> >>
> >> Any domain started after xenstore will have store_evtchn set, so if you don't
> >> have this set, you are either going to be running xenstore locally, or will
> >> use the ioctl to change it later (and so should still set up everything as if
> >> it will be running locally).
> > 
> > That would be wrong for an HVM dom0 domain (at least on ARM), because
> > we don't have a start_info page at all.
> > 
> > 
> >>>> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
> >>>> +		xenstored_ready = 1;
> >>
> >> This part can now just be moved unconditionally into case PV.
> > 
> > What about:
> > 
> > if (xen_pv_domain())
> >     usage = PV;
> > if (xen_hvm_domain())
> >     usage = HVM;
> > if (!xen_store_evtchn)
> >     usage = LOCAL;
> > 
> > and moving xenstored_ready in case PV, like you suggested.
> > 
> 
> That looks correct, but you'd need to split up the switch statement in
> order to populate xen_store_evtchn before that last condition, which
> ends up pretty much eliminating the usage variable.

Going back to what you wrote in the previous email, in what way this
patch breaks the case when an initial domain is started after a Xenstore
stub domain?

Assuming that we are talking about a PV initial domain on x86, the
following check

if (xen_pv_domain() && !xen_start_info->store_evtchn)
    usage = LOCAL;

will return false (because store_evtchn is set), therefore usage will
remain set to PV.
And the check:

if (xen_pv_domain() && xen_start_info->store_evtchn)
	xenstored_ready = 1;

will return true so xenstored_ready is going to be set to 1.


From festevam at gmail.com  Wed Aug  8 13:19:40 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 8 Aug 2012 14:19:40 -0300
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
Message-ID: <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>

Matt,

On Wed, Aug 8, 2012 at 1:55 PM, Matt Sealey <matt at genesi-usa.com> wrote:

...
> or any setup at all for this. What's stopping this right now is you
> need a new U-Boot which we
> didn't release or mainline because we are still testing it (old U-Boot
> shipped on the boards
> cannot boot device tree anyway). While the number of users of this is

Actually you can boot a device tree kernel even on old bootloaders
that do not support dt.

You need to select:
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y

Then,

make -j4 zImage
make imx51-babbage.dtb
cat arch/arm/boot/zImage arch/arm/boot/ imx51-babbage.dtb  >
arch/arm/boot/zImage_dtb
mkimage -A arm -O linux -T kernel -C none -a 0x90008000 -e 0x90008000
-n Linux -d arch/arm/boot/zImage_dtb arch/arm/boot/uImage

and boot this generated uImage the same way as you used to do in the
non-dt case.

Regards,

Fabio Estevam


From stefano.stabellini at eu.citrix.com  Wed Aug  8 13:22:50 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 18:22:50 +0100
Subject: [PATCH v2 21/23] xen: update xen_add_to_physmap interface
In-Reply-To: <20120807183306.GX15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-21-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807183306.GX15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081821380.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:24PM +0100, Stefano Stabellini wrote:
> > Update struct xen_add_to_physmap to be in sync with Xen's version of the
> > structure.
> > The size field was introduced by:
> > 
> > changeset:   24164:707d27fe03e7
> > user:        Jean Guyader <jean.guyader at eu.citrix.com>
> > date:        Fri Nov 18 13:42:08 2011 +0000
> > summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range
> > 
> > According to the comment:
> > 
> > "This new field .size is located in the 16 bits padding between .domid
> > and .space in struct xen_add_to_physmap to stay compatible with older
> > versions."
> > 
> > Changes in v2:
> 
> Looks good. Let me take this as in my tree to prep it for Mukesh's patches.

OK.
Beware that patch #23 is going to modify xen_add_to_physmap again to
replace .size with a union.


> > - remove erroneous comment in the commit message.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  include/xen/interface/memory.h |    3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
> > index b5c3098..b66d04c 100644
> > --- a/include/xen/interface/memory.h
> > +++ b/include/xen/interface/memory.h
> > @@ -163,6 +163,9 @@ struct xen_add_to_physmap {
> >      /* Which domain to change the mapping for. */
> >      domid_t domid;
> >  
> > +    /* Number of pages to go through for gmfn_range */
> > +    uint16_t    size;
> > +
> >      /* Source mapping space. */
> >  #define XENMAPSPACE_shared_info 0 /* shared info page */
> >  #define XENMAPSPACE_grant_table 1 /* grant table page */
> > -- 
> > 1.7.2.5
> 


From khilman at ti.com  Wed Aug  8 13:28:50 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 10:28:50 -0700
Subject: [PATCH 1/2] cpufreq: OMAP: Handle missing frequency table on SMP
 systems
In-Reply-To: <CAMQu2gyooQ4x=ZGDZFg5BuBaEkgQx2kTAvtiGLEjXwOYvF_wMQ@mail.gmail.com>
 (Santosh Shilimkar's message of "Wed, 8 Aug 2012 17:00:10 +0530")
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-2-git-send-email-rnayak@ti.com>
 <CAMQu2gyooQ4x=ZGDZFg5BuBaEkgQx2kTAvtiGLEjXwOYvF_wMQ@mail.gmail.com>
Message-ID: <87wr19uwbx.fsf@ti.com>

"Shilimkar, Santosh" <santosh.shilimkar at ti.com> writes:

> On Wed, Aug 8, 2012 at 4:24 PM, Rajendra Nayak <rnayak at ti.com> wrote:
>>
>> On OMAP4, if the first CPU fails to get a valid frequency table (this
>> could happen if the platform does not register any OPP table), the
>> subsequent CPU instances end up dealing with a NULL freq_table and
>> crash. Add a check for a NULL freq_table to help error the rest
>> of the CPU instances out.
>>
>> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
>> Cc: <linux-pm at vger.kernel.org>
>> ---
>>  drivers/cpufreq/omap-cpufreq.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/cpufreq/omap-cpufreq.c
>> b/drivers/cpufreq/omap-cpufreq.c
>> index 17fa04d..0ee824c 100644
>> --- a/drivers/cpufreq/omap-cpufreq.c
>> +++ b/drivers/cpufreq/omap-cpufreq.c
>> @@ -221,7 +221,7 @@ static int __cpuinit omap_cpu_init(struct
>> cpufreq_policy *policy)
>>         if (atomic_inc_return(&freq_table_users) == 1)
>>                 result = opp_init_cpufreq_table(mpu_dev, &freq_table);
>>
>> -       if (result) {
>> +       if (result || !freq_table) {
>>                 dev_err(mpu_dev, "%s: cpu%d: failed creating freq
>> table[%d]\n",
>>                                 __func__, policy->cpu, result);
>>                 goto fail_ck;
>
> The freq_table use count seems to be buggy in that case.
> Something like below should fix the issue.
> Feel free to update your patch with below if you agree.
>
> diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
> index 17fa04d..fd97c3d 100644
> --- a/drivers/cpufreq/omap-cpufreq.c
> +++ b/drivers/cpufreq/omap-cpufreq.c
> @@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *po
>
>         policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
>
> -       if (atomic_inc_return(&freq_table_users) == 1)
> +       if (freq_table)

I think you meant 'if (!freq_table)' ?

Kevin

>                 result = opp_init_cpufreq_table(mpu_dev, &freq_table);
>
>         if (result) {
> @@ -227,6 +227,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *po
>                 goto fail_ck;
>         }
>
> +       atomic_inc_return(&freq_table_users);
>         result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
>         if (result)
>                 goto fail_table;
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From matt at genesi-usa.com  Wed Aug  8 13:32:39 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 8 Aug 2012 12:32:39 -0500
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <20120808065502.GI1451@pengutronix.de>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
Message-ID: <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>

On Wed, Aug 8, 2012 at 1:55 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>>               .text
>> +             .arm
>>               .global imx_ssi_fiq_start
>>               .global imx_ssi_fiq_end
>>               .global imx_ssi_fiq_base
>
> I think it would be better to add a depends on !THUMB2_KERNEL to
> SND_IMX_SOC_PCM_FIQ. The above may result in broken code in a thumb2
> kernel, so I'd rather keep the compile error instead.

I'm curious as to how/why would it result in broken code? It's not
possible that the processors relying on
the imx_ssi_fiq_* stuff cannot run ARM code (unless Freescale shipped
a weird version) so it should
magically enter and exit. I wonder if it needs some thumb-interworking
stuff wrapped around it though.
You'd know better than me..

I'm a little worried that making it !CONFIG_THUMB2_KERNEL would
basically make more than
one of the boards in imx_v6_v7_defconfig suddenly lose audio support
for no other reason.. I don't
like things just disappearing from the kernel by dependency magic.
That said, a crash would be worse.

I guess the eukrea tlv320 audio support should also be split, or
looked at. This is the snippet that
confuses me the most;

config SND_SOC_EUKREA_TLV320
        tristate "Eukrea TLV320"
        depends on MACH_EUKREA_MBIMX27_BASEBOARD \
                || MACH_EUKREA_MBIMXSD25_BASEBOARD \
                || MACH_EUKREA_MBIMXSD35_BASEBOARD \
                || MACH_EUKREA_MBIMXSD51_BASEBOARD
        depends on I2C
        select SND_SOC_TLV320AIC23
        select SND_SOC_IMX_PCM_FIQ
        select SND_SOC_IMX_AUDMUX
        select SND_SOC_IMX_SSI
        help
          Enable I2S based access to the TLV320AIC23B codec attached
          to the SSI interface

.. Since you said I2S support doesn't require it, only AC97, this alone seems
redundant, but since I wasn't the one to write it, test it, have no
access to this
board I have no idea. Mark's assertion that it's just not required now DMA works
properly, could be true and this can be ditched, but I don't want to
patch something
I can't actually test.. my primary concern was fixing the build breakage.

If that gets fixed, then the only dependencies are the WM1131_EV1 board
which isn't in imx_v6_v7_defconfig, and the phyCORE support which needs it
for AC97. That's one of your customers, right? I wouldn't want to disable a
board, but I can justify to myself disabling the audio for *one* board based if
it's just a caveat of a Thumb2 kernel.

I'm going to do a trapse through and find where Russell nacked Dave's
thumb-aware
rewrite.. would you mind if you have any of these boards seeing if it
really DOES
cause broken code? The moment we noticed this was broken we quit designing
with AC97 codecs, so there's no Genesi board of similar pedigree
around that ever
got to a PCB..

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From dgdegra at tycho.nsa.gov  Wed Aug  8 13:33:55 2012
From: dgdegra at tycho.nsa.gov (Daniel De Graaf)
Date: Wed, 08 Aug 2012 13:33:55 -0400
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <alpine.DEB.2.02.1208081805520.21096@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com> <50216228.7010407@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
 <50229B70.3090507@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081805520.21096@kaball.uk.xensource.com>
Message-ID: <5022A303.709@tycho.nsa.gov>

On 08/08/2012 01:19 PM, Stefano Stabellini wrote:
> On Wed, 8 Aug 2012, Daniel De Graaf wrote:
>> On 08/08/2012 12:51 PM, Stefano Stabellini wrote:
>>> On Tue, 7 Aug 2012, Daniel De Graaf wrote:
>>>> On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
>>>>> On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
>>>>>> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
>>>>>> an error.
>>>>>>
>>>>>> If Linux is running as an HVM domain and is running as Dom0, use
>>>>>> xenstored_local_init to initialize the xenstore page and event channel.
>>>>>>
>>>>>> Changes in v2:
>>>>>>
>>>>>> - refactor xenbus_init.
>>>>>
>>>>> Thank you. Lets also CC our friend at NSA who has been doing some work
>>>>> in that area. Daniel are you OK with this change - will it still make
>>>>> PV initial domain with with the MiniOS XenBus driver?
>>>>>
>>>>> Thanks.
>>>>
>>>> That case will work, but what this will break is launching the initial domain
>>>> with a Xenstore stub domain already running (see below).
>>>>
>>>>>>
>>>>>> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
>>>>>> ---
>>>>>>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
>>>>>>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
>>>>>>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
>>>>>>  3 files changed, 45 insertions(+), 20 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
>>>>>> index 52fe7ad..c5aa55c 100644
>>>>>> --- a/drivers/xen/xenbus/xenbus_comms.c
>>>>>> +++ b/drivers/xen/xenbus/xenbus_comms.c
>>>>>> @@ -224,7 +224,7 @@ int xb_init_comms(void)
>>>>>>  		int err;
>>>>>>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
>>>>>>  						0, "xenbus", &xb_waitq);
>>>>>> -		if (err <= 0) {
>>>>>> +		if (err < 0) {
>>>>>>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
>>>>>>  			return err;
>>>>>>  		}
>>>>>
>>>>>> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
>>>>>> index b793723..a67ccc0 100644
>>>>>> --- a/drivers/xen/xenbus/xenbus_probe.c
>>>>>> +++ b/drivers/xen/xenbus/xenbus_probe.c
>>>>>> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
>>>>>>  	return err;
>>>>>>  }
>>>>>>  
>>>>>> +enum xenstore_init {
>>>>>> +	UNKNOWN,
>>>>>> +	PV,
>>>>>> +	HVM,
>>>>>> +	LOCAL,
>>>>>> +};
>>>>>>  static int __init xenbus_init(void)
>>>>>>  {
>>>>>>  	int err = 0;
>>>>>> +	enum xenstore_init usage = UNKNOWN;
>>>>>> +	uint64_t v = 0;
>>>>>>  
>>>>>>  	if (!xen_domain())
>>>>>>  		return -ENODEV;
>>>>>>  
>>>>>>  	xenbus_ring_ops_init();
>>>>>>  
>>>>>> -	if (xen_hvm_domain()) {
>>>>>> -		uint64_t v = 0;
>>>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
>>>>>> -		if (err)
>>>>>> -			goto out_error;
>>>>>> -		xen_store_evtchn = (int)v;
>>>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
>>>>>> -		if (err)
>>>>>> -			goto out_error;
>>>>>> -		xen_store_mfn = (unsigned long)v;
>>>>>> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
>>>>>> -	} else {
>>>>>> -		xen_store_evtchn = xen_start_info->store_evtchn;
>>>>>> -		xen_store_mfn = xen_start_info->store_mfn;
>>>>>> -		if (xen_store_evtchn)
>>>>>> -			xenstored_ready = 1;
>>>>>> -		else {
>>>>>> +	if (xen_pv_domain())
>>>>>> +		usage = PV;
>>>>>> +	if (xen_hvm_domain())
>>>>>> +		usage = HVM;
>>>>
>>>> The above is correct for domUs, and is overridden for dom0s:
>>>>
>>>>>> +	if (xen_hvm_domain() && xen_initial_domain())
>>>>>> +		usage = LOCAL;
>>>>>> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
>>>>>> +		usage = LOCAL;
>>>>
>>>> Instead of these checks, I think it should just be:
>>>>
>>>> if (!xen_start_info->store_evtchn)
>>>> 	usage = LOCAL;
>>>>
>>>> Any domain started after xenstore will have store_evtchn set, so if you don't
>>>> have this set, you are either going to be running xenstore locally, or will
>>>> use the ioctl to change it later (and so should still set up everything as if
>>>> it will be running locally).
>>>
>>> That would be wrong for an HVM dom0 domain (at least on ARM), because
>>> we don't have a start_info page at all.
>>>
>>>
>>>>>> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
>>>>>> +		xenstored_ready = 1;
>>>>
>>>> This part can now just be moved unconditionally into case PV.
>>>
>>> What about:
>>>
>>> if (xen_pv_domain())
>>>     usage = PV;
>>> if (xen_hvm_domain())
>>>     usage = HVM;
>>> if (!xen_store_evtchn)
>>>     usage = LOCAL;
>>>
>>> and moving xenstored_ready in case PV, like you suggested.
>>>
>>
>> That looks correct, but you'd need to split up the switch statement in
>> order to populate xen_store_evtchn before that last condition, which
>> ends up pretty much eliminating the usage variable.
> 
> Going back to what you wrote in the previous email, in what way this
> patch breaks the case when an initial domain is started after a Xenstore
> stub domain?
> 
> Assuming that we are talking about a PV initial domain on x86, the
> following check
> 
> if (xen_pv_domain() && !xen_start_info->store_evtchn)
>     usage = LOCAL;
> 
> will return false (because store_evtchn is set), therefore usage will
> remain set to PV.
> And the check:
> 
> if (xen_pv_domain() && xen_start_info->store_evtchn)
> 	xenstored_ready = 1;
> 
> will return true so xenstored_ready is going to be set to 1.
> 

Right, the original patch didn't break anything with PV domains. The case
it doesn't handle is an HVM initial domain with an already-running
Xenstore domain; I think this applies both to ARM and hybrid/PVH on x86.
In that case, usage would be set to LOCAL instead of HVM.

As a side note: the value of xen_initial_domain() shouldn't be connected to
determining if xenstore is running locally or not.

-- 
Daniel De Graaf
National Security Agency


From nsekhar at ti.com  Wed Aug  8 13:35:35 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Wed, 8 Aug 2012 23:05:35 +0530
Subject: [PATCH v6 7/7] ARM: davinci: add support for the am1808 based
 enbw_cmc board
In-Reply-To: <1341492608-20597-1-git-send-email-hs@denx.de>
References: <1341492608-20597-1-git-send-email-hs@denx.de>
Message-ID: <5022A367.1070903@ti.com>

Hi Heiko,

On 7/5/2012 6:20 PM, Heiko Schocher wrote:
> - AM1808 based board
> - 64 MiB DDR ram
> - 2 MiB Nor flash
> - 128 MiB NAND flash
> - use internal RTC
> - I2C support
> - hwmon lm75 support
> - UBI/UBIFS support
> - MMC support
> - USB OTG support
> 
> Signed-off-by: Heiko Schocher <hs at denx.de>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Cc: linux-mtd at lists.infradead.org
> Cc: linux-i2c at vger.kernel.org
> Cc: netdev at vger.kernel.org
> Cc: David Woodhouse <dwmw2 at infradead.org>
> Cc: Ben Dooks <ben-linux at fluff.org>
> Cc: Wolfram Sang <w.sang at pengutronix.de>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Wolfgang Denk <wd at denx.de>
> Cc: Scott Wood <scottwood at freescale.com>
> Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>
> 
> ---
> - post this board support with USB support, even though
>   USB is only working with the 10 ms "workaround", posted here:
>   http://comments.gmane.org/gmane.linux.usb.general/54505
>   I see this issue also on the AM1808 TMDXEXP1808L evalboard.
> - MMC and USB are not using OF support yet, ideas how to port
>   this are welcome. I need for USB and MMC boards board
>   specific callbacks, how to solve this with OF support?
> 
> - changes for v2:
>   - changes in the nand node due to comments from Scott Wood:
>     - add "ti,davinci-" prefix
>     - Dashes are preferred to underscores
>     - rename "nandflash" to "nand"
>     - introduce new "ti,davinci" specific properties for setting
>       up ecc_mode, ecc_bits, options and bbt options, instead
>       using linux defines
>   - changes for i2c due to comments from Sylwester Nawrocki:
>     - use "cell-index" instead "id"
>     - OF_DEV_AUXDATA in the machine code, instead pre-define
>       platform device name
>   - add comment from Grant Likely for i2c:
>     - removed "id" resp. "cell-index" completely
>     - fixed documentation
>     - use of_match_ptr()
>     - use devm_kzalloc() for allocating plattform data mem
>     - fixed a whitespace issue
>   - add net comments from Grant Likely:
>     - add prefix "ti,davinci-" to davinci specific property names
>     - remove version property
>     - use compatible name "ti,davinci-dm6460-emac"
>   - add comment from Grant Likely:
>     - rename compatible node
>     - do not use cell-index
>     - CONFIG_OF required for this board
>     TODO:
>     - create a generic board support file, as I got no
>       answer to my ping to grant, maybe this could be done
>       in a second step?
> - changes for v3:
>   - add comments from Sergei Shtylyov:
>     - rename compatible" prop to "ti,cp_intc"
>     - cp_intc_init now used for Interrupt controller init
> - changes for v4:
>   add comment from Nori Sekhar:
>   - rename davinci emac compatible property to "ti,davinci-dm6467-emac"
>   - remove "pinmux-handle" property as discussed here:
>     http://www.spinics.net/lists/arm-kernel/msg175701.html
>     with Nori Sekhar
> 
> - changes for v5:
>   add comments from Grant Likely:
>   - rename compatible" prop to "ti,cp-intc"
> 
> - changes for v6:
>   rework this patch, as patch
>   ARM: davinci: cp_intc: Add OF support for TI interrupt controller
>   was changed from Nori Sekhar on Jul 03, 2012; 9:16pm
>   Changes therefore in this patch:
> 
>   Call of_irq_init() in the generic DT board file and not in the
>   interrupt controller code. See arch/arm/mach-at91/board-dt.c or
>   arch/arm/mach-omap2/board-generic.c for examples.
> 
>   At this point the question raises, if we should rename this
>   board port from arch/arm/mach-davinci/enbw_cmc.c to
>   arch/arm/mach-davinci/board-dt.c ? Also the defconfig to
>   davinci_of_defconfig ... ? The USB and MMC callbacks are
>   currently board specific, but if other boards come in,
>   that could be easily adapted for their needs ...
> 
>  arch/arm/boot/dts/enbw_cmc.dts                  |  183 +++++++++++
>  arch/arm/configs/enbw_cmc_defconfig             |  126 ++++++++
>  arch/arm/mach-davinci/Kconfig                   |    9 +
>  arch/arm/mach-davinci/Makefile                  |    1 +
>  arch/arm/mach-davinci/board-enbw-cmc.c          |  385 +++++++++++++++++++++++
>  arch/arm/mach-davinci/include/mach/uncompress.h |    1 +
>  6 files changed, 705 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/enbw_cmc.dts
>  create mode 100644 arch/arm/configs/enbw_cmc_defconfig
>  create mode 100644 arch/arm/mach-davinci/board-enbw-cmc.c

With the move to DT, we are not going to add more board specific files
and defconfigs. I am working on adding a generic dt board file for DA850
(similar to what has been done for imx). That file is not going to do
any platform device registrations. If you are OK with it, I will add the
dts file for enbw_cmc board in the patch series I am planning to post.

Things like USB and MMC/SD will need to be converted to DT before they
can be supported on new boards.

Thanks,
Sekhar


From matt at genesi-usa.com  Wed Aug  8 13:36:41 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 8 Aug 2012 12:36:41 -0500
Subject: Kernels on Bad Firmware (was Re: kernel entry for thumb2-only cpus)
Message-ID: <CAKGA1b=8gZdgpSJ28Hff+1199J0GarLxZU-NAv7JJDuk+La0ew@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:33 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Aug 07, 2012 at 05:34:15PM -0500, Matt Sealey wrote:
>> Just because there is a ton of absolutely awful, broken firmware code out there
>> doesn't mean it can and will always be the case, and Linux policy should not
>> be dictated on an architecture basis on a few bad eggs, especially if it means
>> developers in the big wide world have to jump through hoops. Surely it is just
>> as good for Linux to loudly advocate the correct solutions in firmware and
>> implement the workarounds anyway, like a device quirk, rather than just out and
>> out say "firmwares suck, ignore what they did, do it again. We don't trust them
>> and never will."
>
> Sadly, firmware developers have taught us time and time and time and time
> again that they can not be trusted.  You may be the single one who can be
> trusted to validate their stuff properly, but you would be in a severe
> minority if that is true.
>
> Many firmware developers do the barest minimum that's required.  Once their
> job is done, that's the end of the development cycle and nothing further
> happens, not even for bugs.
>
> We've seen this time and time again.  We see it with corrupted ATAG lists,
> we see it with bad memory tags passed to the kernel that the kernel has to
> then screw around with to fix up the broken firmware developers crap.
> Let me show you the crappy workarounds that we have:

No need, we're guilty of that too; line 2600 onwards of
arch/powerpc/kernel/prom_init.c

However we do provide a Forth script that can run the kernel that does
all this, but nobody
would accept removing the fixups from the kernel (an old patch is
inside the zip archive..).

http://www.powerdeveloper.org/platforms/efika/devicetree

We definitely learned from our mistakes - nasty firmware shipped
before Linux had
properly implemented device trees for that SoC, and many many user problems that
just caused support and update hassle.. it costs money to support bad code. Far
more than just spending getting it right in the first place.

The fact we could update it with a script was the awesome thing about
using OpenFirmware -
but U-Boot can do this too, since libfdt is there and it's one option
to enable it to allow script
based modification of the blob. If the DT is hardcoded into the firmware somehow
(CONFIG_OF_CONTROL I think) then platforms can load "boot.scr" from
the root filesystem
(cram or jffs or ubifs if necessary) or similar and fix their device
trees in-place, and if they're
from filesystem and "known bad", fix them after loading them. Highly
embedded platforms
might make this clumsy, but it can ALL be done there.. one problem is,
this is also way, way
too late to do pin muxing :]

On UEFI updates to device tree or ACPI DSDT could be done via a small
EBC loader that
chained to the next boot device.. did anyone make any inroads into
what the real spec
for booting from UEFI should be, by the way, I noticed the Beagle
Tiano Core "only" supports
zImage which is infuriating as this flaunts the existing EFI/UEFI
standard. Wrapping the
kernel in a PECOFF image would not be all that hard and then what you
get is the ability
to write the exact nature of the entry point into the architecture id
field of the header (the
latest spec from 2010 or so includes ARMv7 Thumb2).

> Spot a pattern there?  The one which stands out to me is that boot loaders
> can not get the trivial task of passing the simple information about where
> the RAM is in the system to the kernel right.
>
> Many boot loaders for _years_ have not been able to get the very very
> trivially simple issue of passing the right machine ID value in r1 to the
> kernel either.

Also guilty although we inherited that problem from a large Taiwanese
manufacturer
who hacked U-Boot to load their machine ID from the filesystem
(type_id.bin) before
being able to boot. Otherwise it'd throw in a 0 and everything would
break. We still
have to ship that to update firmware on old machines. It never made
any sense since
you couldn't boot their boards from a common bootloader binary anyway where the
machine_id would be that dynamic..

> Have we tried to push the onus back on firmware people?  I've tried damned
> hard to the extent of preventing some of these work-arounds getting into
> mainline, but the sole result of that was that mainline would not work on
> those platforms;

> on the platforms.  It didn't magically cause the firmware to get fixed in
> any way.  We just ended up with a detrimental situation to everyone because
> mainline just didn't work on those platforms.

I'm fairly sure you're not above saying "tough shit" to these guys, though?

If their firmware is broken they don't get to boot mainline Linux. If
they have to
stick to BSPs, then, that is their problem. If BSPs get hard to maintain, maybe
someone writing those BSPs will finally get up and implement some change.

Worst case, they'd end up with a mainline tree in git somewhere with a couple
patches that never got accepted to enable booting your board.

This is one reason I'm fairly excited about the proposition of UEFI - it's very
well defined on x86 right now and there's a chance to lock down everything
absolutely necessary to perform boot on ARM and have it be there from the
first consumer board, 100%.

> order for that to change, they must change, and they must _earn_ our trust
> that they _can_ be trusted to do a good job.  Until then...

Until then I think what's missing is someone important kernel-side
being involved
in bootloader specifications. ePAPR was a nice try, since Grant Likely got to be
the one to push it through, and we got a nice base for device tree, although we
were on the technical committee for PAPR and ePAPR and founder members
of Power.org at the time, they basically ignored us because what we wanted out
of it was to change the status quo for something better - what they wanted to do
was re-ratify the spec from 10 years ago and put a new trademark stamp on it.

No offense intended to anyone on the list, but Linaro is kind of doing
the same thing
right now on a lot of things. It needs to be specified first then
implemented, but the
"Linux development model" is patch first, patch again, patch again,
patch again and
retrofit the binding to match. Right now it's possible there won't be
a line of common
code between the device tree I just pushed and the one required to
boot the board
in 2 years.. no wonder you can't trust the bootloader guys, they're on
a train going
east at 200kmh, Linux is on a train going west at 200kmh, and you're both trying
to shoot each other. Moving targets are very hard to implement on a consumer
device since you can't force Grandma to update her U-Boot every week and match
a kernel to it. The only reason it's acceptable right now is because
there are no
consumer devices in the mainline Linux ARM tree (except, arguably, ours and the
AlwaysInnovating Touchbook, but I would be happy to know there is
someone running
a phone or another tablet capable of booting a mainline Linux and a
device tree),
only reference designs and platform experiments.

-- 
Matt Sealey <matt at genesi-usa.com>


From stefano.stabellini at eu.citrix.com  Wed Aug  8 13:42:05 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 18:42:05 +0100
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <5022A303.709@tycho.nsa.gov>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com> <50216228.7010407@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
 <50229B70.3090507@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081805520.21096@kaball.uk.xensource.com>
 <5022A303.709@tycho.nsa.gov>
Message-ID: <alpine.DEB.2.02.1208081836050.21096@kaball.uk.xensource.com>

On Wed, 8 Aug 2012, Daniel De Graaf wrote:
> On 08/08/2012 01:19 PM, Stefano Stabellini wrote:
> > On Wed, 8 Aug 2012, Daniel De Graaf wrote:
> >> On 08/08/2012 12:51 PM, Stefano Stabellini wrote:
> >>> On Tue, 7 Aug 2012, Daniel De Graaf wrote:
> >>>> On 08/07/2012 02:21 PM, Konrad Rzeszutek Wilk wrote:
> >>>>> On Mon, Aug 06, 2012 at 03:27:13PM +0100, Stefano Stabellini wrote:
> >>>>>> bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
> >>>>>> an error.
> >>>>>>
> >>>>>> If Linux is running as an HVM domain and is running as Dom0, use
> >>>>>> xenstored_local_init to initialize the xenstore page and event channel.
> >>>>>>
> >>>>>> Changes in v2:
> >>>>>>
> >>>>>> - refactor xenbus_init.
> >>>>>
> >>>>> Thank you. Lets also CC our friend at NSA who has been doing some work
> >>>>> in that area. Daniel are you OK with this change - will it still make
> >>>>> PV initial domain with with the MiniOS XenBus driver?
> >>>>>
> >>>>> Thanks.
> >>>>
> >>>> That case will work, but what this will break is launching the initial domain
> >>>> with a Xenstore stub domain already running (see below).
> >>>>
> >>>>>>
> >>>>>> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> >>>>>> ---
> >>>>>>  drivers/xen/xenbus/xenbus_comms.c |    2 +-
> >>>>>>  drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
> >>>>>>  drivers/xen/xenbus/xenbus_xs.c    |    1 +
> >>>>>>  3 files changed, 45 insertions(+), 20 deletions(-)
> >>>>>>
> >>>>>> diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
> >>>>>> index 52fe7ad..c5aa55c 100644
> >>>>>> --- a/drivers/xen/xenbus/xenbus_comms.c
> >>>>>> +++ b/drivers/xen/xenbus/xenbus_comms.c
> >>>>>> @@ -224,7 +224,7 @@ int xb_init_comms(void)
> >>>>>>  		int err;
> >>>>>>  		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
> >>>>>>  						0, "xenbus", &xb_waitq);
> >>>>>> -		if (err <= 0) {
> >>>>>> +		if (err < 0) {
> >>>>>>  			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
> >>>>>>  			return err;
> >>>>>>  		}
> >>>>>
> >>>>>> diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
> >>>>>> index b793723..a67ccc0 100644
> >>>>>> --- a/drivers/xen/xenbus/xenbus_probe.c
> >>>>>> +++ b/drivers/xen/xenbus/xenbus_probe.c
> >>>>>> @@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
> >>>>>>  	return err;
> >>>>>>  }
> >>>>>>  
> >>>>>> +enum xenstore_init {
> >>>>>> +	UNKNOWN,
> >>>>>> +	PV,
> >>>>>> +	HVM,
> >>>>>> +	LOCAL,
> >>>>>> +};
> >>>>>>  static int __init xenbus_init(void)
> >>>>>>  {
> >>>>>>  	int err = 0;
> >>>>>> +	enum xenstore_init usage = UNKNOWN;
> >>>>>> +	uint64_t v = 0;
> >>>>>>  
> >>>>>>  	if (!xen_domain())
> >>>>>>  		return -ENODEV;
> >>>>>>  
> >>>>>>  	xenbus_ring_ops_init();
> >>>>>>  
> >>>>>> -	if (xen_hvm_domain()) {
> >>>>>> -		uint64_t v = 0;
> >>>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
> >>>>>> -		if (err)
> >>>>>> -			goto out_error;
> >>>>>> -		xen_store_evtchn = (int)v;
> >>>>>> -		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
> >>>>>> -		if (err)
> >>>>>> -			goto out_error;
> >>>>>> -		xen_store_mfn = (unsigned long)v;
> >>>>>> -		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
> >>>>>> -	} else {
> >>>>>> -		xen_store_evtchn = xen_start_info->store_evtchn;
> >>>>>> -		xen_store_mfn = xen_start_info->store_mfn;
> >>>>>> -		if (xen_store_evtchn)
> >>>>>> -			xenstored_ready = 1;
> >>>>>> -		else {
> >>>>>> +	if (xen_pv_domain())
> >>>>>> +		usage = PV;
> >>>>>> +	if (xen_hvm_domain())
> >>>>>> +		usage = HVM;
> >>>>
> >>>> The above is correct for domUs, and is overridden for dom0s:
> >>>>
> >>>>>> +	if (xen_hvm_domain() && xen_initial_domain())
> >>>>>> +		usage = LOCAL;
> >>>>>> +	if (xen_pv_domain() && !xen_start_info->store_evtchn)
> >>>>>> +		usage = LOCAL;
> >>>>
> >>>> Instead of these checks, I think it should just be:
> >>>>
> >>>> if (!xen_start_info->store_evtchn)
> >>>> 	usage = LOCAL;
> >>>>
> >>>> Any domain started after xenstore will have store_evtchn set, so if you don't
> >>>> have this set, you are either going to be running xenstore locally, or will
> >>>> use the ioctl to change it later (and so should still set up everything as if
> >>>> it will be running locally).
> >>>
> >>> That would be wrong for an HVM dom0 domain (at least on ARM), because
> >>> we don't have a start_info page at all.
> >>>
> >>>
> >>>>>> +	if (xen_pv_domain() && xen_start_info->store_evtchn)
> >>>>>> +		xenstored_ready = 1;
> >>>>
> >>>> This part can now just be moved unconditionally into case PV.
> >>>
> >>> What about:
> >>>
> >>> if (xen_pv_domain())
> >>>     usage = PV;
> >>> if (xen_hvm_domain())
> >>>     usage = HVM;
> >>> if (!xen_store_evtchn)
> >>>     usage = LOCAL;
> >>>
> >>> and moving xenstored_ready in case PV, like you suggested.
> >>>
> >>
> >> That looks correct, but you'd need to split up the switch statement in
> >> order to populate xen_store_evtchn before that last condition, which
> >> ends up pretty much eliminating the usage variable.
> > 
> > Going back to what you wrote in the previous email, in what way this
> > patch breaks the case when an initial domain is started after a Xenstore
> > stub domain?
> > 
> > Assuming that we are talking about a PV initial domain on x86, the
> > following check
> > 
> > if (xen_pv_domain() && !xen_start_info->store_evtchn)
> >     usage = LOCAL;
> > 
> > will return false (because store_evtchn is set), therefore usage will
> > remain set to PV.
> > And the check:
> > 
> > if (xen_pv_domain() && xen_start_info->store_evtchn)
> > 	xenstored_ready = 1;
> > 
> > will return true so xenstored_ready is going to be set to 1.
> > 
> 
> Right, the original patch didn't break anything with PV domains. The case
> it doesn't handle is an HVM initial domain with an already-running
> Xenstore domain; I think this applies both to ARM and hybrid/PVH on x86.
> In that case, usage would be set to LOCAL instead of HVM.


Right, however if I am not mistaken there is no such thing as an HVM
dom0 right now on x86 and hybrid/PVH is probably going to return true on
xen_pv_domain() and false on xen_hvm_domain().

In the ARM case, given that we don't have a start_info page, we would
need another way to figure out whether a xenstore stub domain is already
running, so I think we can just postpone the solution of that problem
for now.


From swarren at wwwdotorg.org  Wed Aug  8 13:50:49 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 11:50:49 -0600
Subject: Kernels on Bad Firmware (was Re: kernel entry for thumb2-only
 cpus)
In-Reply-To: <CAKGA1b=8gZdgpSJ28Hff+1199J0GarLxZU-NAv7JJDuk+La0ew@mail.gmail.com>
References: <CAKGA1b=8gZdgpSJ28Hff+1199J0GarLxZU-NAv7JJDuk+La0ew@mail.gmail.com>
Message-ID: <5022A6F9.2000206@wwwdotorg.org>

On 08/08/2012 11:36 AM, Matt Sealey wrote:
...
> The fact we could update it with a script was the awesome thing about
> using OpenFirmware -
> but U-Boot can do this too, since libfdt is there and it's one option
> to enable it to allow script
> based modification of the blob. If the DT is hardcoded into the firmware somehow
> (CONFIG_OF_CONTROL I think) then platforms can load "boot.scr" from
> the root filesystem ...

Just a comment on CONFIG_OF_CONTROL...

In U-Boot, CONFIG_OF_CONTROL determines whether U-Boot uses a device
tree to configure itself. This is completely orthogonal to whether a
device tree is passed to the kernel, and where the kernel DT comes from,
which is still controlled by the bootm/bootz command parameters.

The DT used to configure U-Boot isn't the same one passed to the kernel
typically. The one for U-Boot is typically appended to the U-Boot image,
whereas the one passed to the kernel is likely loaded from a file in
/boot alongside the uImage/zImage of the kernel. I suppose the U-Boot
script /could/ be written to encode the location of the appended DTB
used by U-Boot and so pass the same one to the kernel, I don't believe
anyone has done that. Besides, U-Boot's copy of the .dts files has
diverged a little from the kernel's...:-(


From sboyd at codeaurora.org  Wed Aug  8 13:53:34 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 08 Aug 2012 10:53:34 -0700
Subject: [PATCH 01/11] ARM: topology: mark init_cpu_topology as __init
In-Reply-To: <1344437248-20560-2-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-2-git-send-email-arnd@arndb.de>
Message-ID: <5022A79E.6050504@codeaurora.org>

On 08/08/12 07:47, Arnd Bergmann wrote:
> The init_cpu_topology function can be put into the __init section
> and discarded after boot, because it is only called from
> smp_prepare_cpus, which is also marked __init. This was reported
> by gcc after Vincent Guittot added the parse_dt_topology function
> in 339ca09d7ada "ARM: 7463/1: topology: Update cpu_power according to DT
> information".
>
> Without this patch, building kzm9g_defconfig results in:
>
> WARNING: vmlinux.o(.text+0xb5a0): Section mismatch in reference from the function init_cpu_topology() to the function .init.text:parse_dt_topology()
> The function init_cpu_topology() references
> the function __init parse_dt_topology().
> This is often because init_cpu_topology lacks a __init
> annotation or the annotation of parse_dt_topology is wrong.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Vincent Guittot <vincent.guittot at linaro.org>
> Cc: Namhyung Kim <namhyung at kernel.org>
> Cc: Peter Zijlstra <a.p.zijlstra at chello.nl>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

This is already in the patch tracker

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7482/1

I also notice that store_cpu_topology() should be marked __cpuinit and
update_siblings_mask, middle_capacity, cpu_capacity, and
update_cpu_power should be static. We should probably also rename
update_cpu_power() so as to not conflict with the one in kernel/sched/fair.c

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From matt at genesi-usa.com  Wed Aug  8 13:53:39 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 8 Aug 2012 12:53:39 -0500
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <alpine.LFD.2.02.1208080033410.5231@xanadu.home>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
 <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
 <alpine.LFD.2.02.1208080033410.5231@xanadu.home>
Message-ID: <CAKGA1bn7YwT33F=J0AMWAy+mSDy=7iUt2U46dmABXPc+664rNw@mail.gmail.com>

On Wed, Aug 8, 2012 at 12:04 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Tue, 7 Aug 2012, Matt Sealey wrote:
>
>> On Mon, Aug 6, 2012 at 7:08 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> > On Mon, 6 Aug 2012, Matt Sealey wrote:
>
>> lines flailing around during a mux change, and GPIO directions
>> changing on the fly for no good reason.
>
> But if Linux is re-initializing everything identically to the bootloader
> then the hardware should see a no-op, no?

Not necessarily.. it is most likely implementation dependent, I'd think.
It also depends on what is outside the chip.

> right person to discuss pinmux design issues.  If you have concerns
> about redundant initialization or similar issues then I strongly
> suggest you start a new thread to initiate a discussion on that.

Been doing that since 2005, still going strong..

> Note that I previously opposed the idea of any hard linkage between the
> bootloader and the device tree content.  If you are spending so much
> time validating your DT, you might feel so confident as to not allow it
> to be updatable unless the whole bootloader is also updated.

The DTB is seperate from the firmware. But the firmware does all the pinmuxing
long before the DTB is loaded - that way the DTB does the correct thing and
in the worst case describes only the currently configured and ready-to-operate
hardware (or in the best case, describes hardware the bootloader is currently
using..).

On OF since every node tends to have a driver backed to it, you just write
small stub drivers that pinmux then add it to the tree. U-Boot and other FW
are more clunky but the same effect can be achieved - just make sure every
entry you commit to the Linux arch/arm/boot/dts tree definitely has it's pinmux
set up.

There are good reasons to pinmux stuff at runtime - configurable hardware such
as on my HP Touchpad, the headphone port is also a UART. It's creepy, but
you may want to listen to audio and then switch to debugging - the microphone
part is always input (uart rx on host side) and the left audio is
output (uart tx),
and ground is ground. The right audio pin is not used in UART. You don't want
to reboot in the middle of debugging an app that specifically uses the headphone
and with correct board design and prudent use by the developer it's safe.. but
not all boards are designed that way. One thing we can change is the software
to work around hardware. We can make sure DTBs describe the breakages well
and make sure that FW solves all the problems it can before Linux gets to
it (for instance ARM errata settings in SCU, PL310, aux cp registers which would
otherwise be done in cpu init once at boot, need to be done before running any
code so FW should do them).

But as we just saw when submitting our device tree, we got a nit from
the maintainer
that we don't set up pinctrl - and that pinctrl setup would be
required in case any
device drivers needed it. I'm saying no; pinctrl shouldn't be
*required* by a platform,
it should be optional for all those where it's impossible to entertain
it or where there's
some kind of late-hitting errata that nobody could have predicted
(like the MX51 SPI
chipselect bug) and the collaboration between updating U-Boot and Linux to match
using GPIO for chipselects instead of letting the chip handle it is
too much cost or
effort compared to adding 2 entries to a device tree and updating Linux.

But not 100 entries in device tree, please, and no hard requirements..

> wrong.  Please make your DTB into a separate flash area, separate from
> the boot loader so it can easily be updated without any risk of breaking
> the device.  Just in case...

Our DTB is on the filesystem, ext2 or ext3 or ext4 or vfat. SD card, PATA,
SATA or USB, or even NFS or TFTP. You could even take an SD card, put
it in a Windows box, and copy a new one in place, no Linux required. It's
totally userspace/user friendly. We made absolutely sure of it.

Thanks,

I'll leave the discussion for the other thread I spawned from this ;)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From stefano.stabellini at eu.citrix.com  Wed Aug  8 14:05:26 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Wed, 8 Aug 2012 19:05:26 +0100
Subject: [PATCH v2 15/23] xen/arm: receive Xen events on ARM
In-Reply-To: <20120807183036.GR15053@phenom.dumpdata.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-15-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807183036.GR15053@phenom.dumpdata.com>
Message-ID: <alpine.DEB.2.02.1208081826190.21096@kaball.uk.xensource.com>

On Tue, 7 Aug 2012, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 06, 2012 at 03:27:18PM +0100, Stefano Stabellini wrote:
> > Compile events.c on ARM.
> > Parse, map and enable the IRQ to get event notifications from the device
> > tree (node "/xen").
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/include/asm/xen/events.h |   18 ++++++++++++++++++
> >  arch/arm/xen/enlighten.c          |   33 +++++++++++++++++++++++++++++++++
> >  arch/x86/xen/enlighten.c          |    1 +
> >  arch/x86/xen/irq.c                |    1 +
> >  arch/x86/xen/xen-ops.h            |    1 -
> >  drivers/xen/events.c              |   17 ++++++++++++++---
> >  include/xen/events.h              |    2 ++
> >  7 files changed, 69 insertions(+), 4 deletions(-)
> >  create mode 100644 arch/arm/include/asm/xen/events.h
> > 
> > diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
> > new file mode 100644
> > index 0000000..94b4e90
> > --- /dev/null
> > +++ b/arch/arm/include/asm/xen/events.h
> > @@ -0,0 +1,18 @@
> > +#ifndef _ASM_ARM_XEN_EVENTS_H
> > +#define _ASM_ARM_XEN_EVENTS_H
> > +
> > +#include <asm/ptrace.h>
> > +
> > +enum ipi_vector {
> > +	XEN_PLACEHOLDER_VECTOR,
> > +
> > +	/* Xen IPIs go here */
> > +	XEN_NR_IPIS,
> > +};
> > +
> > +static inline int xen_irqs_disabled(struct pt_regs *regs)
> > +{
> > +	return raw_irqs_disabled_flags(regs->ARM_cpsr);
> > +}
> > +
> > +#endif /* _ASM_ARM_XEN_EVENTS_H */
> > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
> > index e5e92d5..87b17f0 100644
> > --- a/arch/arm/xen/enlighten.c
> > +++ b/arch/arm/xen/enlighten.c
> > @@ -1,4 +1,5 @@
> >  #include <xen/xen.h>
> > +#include <xen/events.h>
> >  #include <xen/grant_table.h>
> >  #include <xen/hvm.h>
> >  #include <xen/interface/xen.h>
> > @@ -9,6 +10,8 @@
> >  #include <xen/xenbus.h>
> >  #include <asm/xen/hypervisor.h>
> >  #include <asm/xen/hypercall.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irqreturn.h>
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/of_irq.h>
> > @@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
> >  int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
> >  EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
> >  
> > +static __read_mostly int xen_events_irq = -1;
> > +
> 
> So this is global..
> >  int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
> >  			       unsigned long addr,
> >  			       unsigned long mfn, int nr,
> > @@ -66,6 +71,9 @@ static int __init xen_guest_init(void)
> >  	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
> >  		return 0;
> >  	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
> > +	xen_events_irq = irq_of_parse_and_map(node, 0);
> > +	pr_info("Xen support found, events_irq=%d gnttab_frame_pfn=%lx\n",
> > +			xen_events_irq, xen_hvm_resume_frames);
> >  	xen_domain_type = XEN_HVM_DOMAIN;
> >  
> >  	xen_setup_features();
> > @@ -107,3 +115,28 @@ static int __init xen_guest_init(void)
> >  	return 0;
> >  }
> >  core_initcall(xen_guest_init);
> > +
> > +static irqreturn_t xen_arm_callback(int irq, void *arg)
> > +{
> > +	xen_hvm_evtchn_do_upcall();
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static int __init xen_init_events(void)
> > +{
> > +	if (!xen_domain() || xen_events_irq < 0)
> > +		return -ENODEV;
> > +
> > +	xen_init_IRQ();
> > +
> > +	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
> > +			"events", xen_vcpu)) {
> 
> But here you are asking for it to be percpu? What if there are other
> interrupts on the _other_ CPUs that conflict with it?
> > +		pr_err("Error requesting IRQ %d\n", xen_events_irq);
> > +		return -EINVAL;
> > +	}
> > +
> > +	enable_percpu_irq(xen_events_irq, 0);
> 
> Uh, that is bold. One global to rule them all, eh? Should you make
> it at least:
> static DEFINE_PER_CPU(int, xen_events_irq);
> ?

That is an interesting observation.

Currently Xen is using a per-cpu interrupt (a PPI, using the GIC
terminology), and it makes sense so that we can receive event
notifications on multiple vcpus independently.
The irq range 16-31 is reserved for PPIs and I am assuming that Xen will
be able to find one spare, the same one, for all vcpus.
In fact the third field corresponding to the interrupt in the DT (0xf08
in my dts) contains the cpu mask and it is set to 0xf (the maximum)
right now.

Maybe I should just BUG_ON(xen_events_irq > 31 || xen_events_irq < 16)?

The versioning of the hypervisor node on the DT is going to help us make
any changes to the interface in the future.


From swarren at wwwdotorg.org  Wed Aug  8 14:08:27 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 12:08:27 -0600
Subject: [PATCH v2] pinctrl/nomadik: add ASIC DB8450 pinctrl driver
In-Reply-To: <1344427543-29524-1-git-send-email-linus.walleij@stericsson.com>
References: <1344427543-29524-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <5022AB1B.5050401@wwwdotorg.org>

On 08/08/2012 06:05 AM, Linus Walleij wrote:
> From: Patrice Chotard <patrice.chotard at stericsson.com>
> 
> This implements a subdriver for the DB8540 ASIC for the
> Nomadik pin controller.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard at stericsson.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Reviewed-by: Stephen Warren <swarren at wwwdotorg.org>



From khilman at ti.com  Wed Aug  8 14:11:25 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 08 Aug 2012 11:11:25 -0700
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <1344437248-20560-12-git-send-email-arnd@arndb.de> (Arnd
 Bergmann's message of "Wed, 8 Aug 2012 16:47:28 +0200")
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-12-git-send-email-arnd@arndb.de>
Message-ID: <87obmluucy.fsf@ti.com>

Arnd Bergmann <arnd at arndb.de> writes:

> A few drivers use a construct like
>
>  #ifdef CONFIG_PM
>  static int foo_suspend(struct device *pdev)
>  {
>     ...
>  }
>  static int foo_resume struct device *pdev)
>  {
>     ...
>  }
>  #endif
>  static SIMPLE_DEV_PM_OPS(foo_pm, foo_suspend, foo_resume);
>
> which leaves the two functions unused if CONFIG_PM is enabled
> but CONFIG_PM_SLEEP is disabled. I found this while building
> all defconfig files on ARM. It's not clear to me if this is
> the right solution, but at least it makes the code consistent
> again.
>
> Without this patch, building omap1_defconfig results in:
>
> drivers/char/hw_random/omap-rng.c:165:12: warning: 'omap_rng_suspend' defined but not used [-Wunused-function]
> drivers/char/hw_random/omap-rng.c:171:12: warning: 'omap_rng_resume' defined but not used [-Wunused-function]
> sound/drivers/dummy.c:1068:12: warning: 'snd_dummy_suspend' defined but not used [-Wunused-function]
> sound/drivers/dummy.c:1078:12: warning: 'snd_dummy_resume' defined but not used [-Wunused-function]
>
> and building tegra_defconfig results in:
>
> drivers/i2c/busses/i2c-tegra.c:716:12: warning: 'tegra_i2c_suspend' defined but not used [-Wunused-function]
> drivers/i2c/busses/i2c-tegra.c:727:12: warning: 'tegra_i2c_resume' defined but not used [-Wunused-function]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Takashi Iwai <tiwai at suse.de>
> Cc: Laxman Dewangan <ldewangan at nvidia.com>
> ---
>  drivers/char/hw_random/omap-rng.c |    2 +-

For the OMAP change,

Acked-by: Kevin Hilman <khilman at ti.com>



From swarren at wwwdotorg.org  Wed Aug  8 14:38:58 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 12:38:58 -0600
Subject: [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
Message-ID: <5022B242.1050001@wwwdotorg.org>

On 08/07/2012 07:39 PM, Tony Prisk wrote:
> Converted the existing arch-vt8500 gpio to a platform_device.
> Added support for WM8505 and WM8650 GPIO controllers.

> diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c

> +static struct of_device_id vt8500_gpio_dt_ids[] = {
> +	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
> +	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
> +	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
> +	{ /* Sentinel */ },
> +};
> +
> +static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
> +{
> +	void __iomem *gpio_base;
> +	struct device_node *np;
> +	const struct of_device_id *of_id =
> +				of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
> +
> +	if (!of_id) {
> +		dev_err(&pdev->dev, "Failed to find gpio controller\n");
> +		return -ENODEV;
> +	}
> +
> +	np = of_find_matching_node(NULL, vt8500_gpio_dt_ids);

Can't you use pdev->dev.of_node instead of searching for it again?

...
> +	of_node_put(np);

If so, you could also remove that.

> +static int __init vt8500_gpio_init(void)
> +{
> +	return platform_driver_probe(&vt8500_gpio_driver, &vt8500_gpio_probe);
> +}
> +
> +static void __exit vt8500_gpio_exit(void)
> +{
> +	return platform_driver_unregister(&vt8500_gpio_driver);
> +}
> +
> +module_init(vt8500_gpio_init);
> +module_exit(vt8500_gpio_exit);

I think that's all just:

module_platform_driver(vt8500_gpio_driver);

(except that _init uses platform_driver_probe() rather than
platform_driver_register(), which seems unusual. I guess that explains
the of_find_matching_node() above too.)

> +MODULE_LICENSE("GPL");

That should be "GPL v2" given the license header.



From swarren at wwwdotorg.org  Wed Aug  8 14:43:14 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 12:43:14 -0600
Subject: [PATCH 1/8] arm: vt8500: Add device tree files for VIA/Wondermedia
 SoC's
In-Reply-To: <1344389967-8465-2-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-2-git-send-email-linux@prisktech.co.nz>
Message-ID: <5022B342.7080606@wwwdotorg.org>

On 08/07/2012 07:39 PM, Tony Prisk wrote:
> Add device tree files for VT8500, WM8505 and WM8650 SoC's and
> reference boards.

> diff --git a/arch/arm/boot/dts/vt8500_ref.dts b/arch/arm/boot/dts/vt8500_ref.dts

It appears more typical to use "-" rather than "_" in the filename to
join SoC and board names.

I guess "_ref" means "reference". Is that how the boards are commonly
known? Are you sure there will never be another reference board for
these SoCs? Given the "model" values in the file, something more like
vt8500-bv07.dts might be more appropriate?

> +	/*
> +	 * Display node is based on Sascha Hauer's patch on dri-devel.
> +	 * Added a bpp property to calculate the size of the framebuffer
> +	 * until the binding is formalized.
> +	 */
> +	display {

Maybe it's better to just hold off on adding this node, to wait until
the binding is complete so this file doesn't churn? Certainly it sounded
like Sascha was going to change the binding a little in response to
comments it received.


From swarren at wwwdotorg.org  Wed Aug  8 14:47:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 12:47:32 -0600
Subject: [PATCH 5/8] video: vt8500: Add devicetree support for vt8500-fb
 and wm8505-fb
In-Reply-To: <1344389967-8465-6-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-6-git-send-email-linux@prisktech.co.nz>
Message-ID: <5022B444.2020501@wwwdotorg.org>

On 08/07/2012 07:39 PM, Tony Prisk wrote:
> Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
> tree bindings.

> Small change in wm8505-fb.c to support WM8650 framebuffer color
> format.

That might warrant a separate patch?

> diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c

> +	np = of_find_node_by_name(NULL, "display");
> +	if (!np) {
> +		pr_err("%s: No display description in Device Tree\n", __func__);
> +		ret = -EINVAL;
> +		goto failed_free_res;
> +	}

I believe that using hard-coded node names is frowned upon. Better would
be to put a phandle into the display controller's node that points at
the node representing the display, e.g.:

    fb at d800e400 {
        compatible = "via,vt8500-fb";
        reg = <0xd800e400 0x400>;
        interrupts = <12>;
        via,display = <&display>;
    };
    display: display {
        ...
    };



From nico at fluxnic.net  Wed Aug  8 14:53:34 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 08 Aug 2012 14:53:34 -0400 (EDT)
Subject: kernel entry for thumb2-only cpus
In-Reply-To: <CAKGA1bn7YwT33F=J0AMWAy+mSDy=7iUt2U46dmABXPc+664rNw@mail.gmail.com>
References: <20120803090452.GE2626@pengutronix.de>
 <20120803114532.GB26925@mudshark.cambridge.arm.com>
 <20120805095528.GO2626@pengutronix.de>
 <alpine.LFD.2.02.1208060026460.5231@xanadu.home>
 <CAKGA1b=Pxif=4qSvK-Odmunbm_T6LjWP_CXid_v2VNmpuyHLDA@mail.gmail.com>
 <20120806190856.GA1120@n2100.arm.linux.org.uk>
 <CAKGA1b=Np8+RMwgQEzwxdJcL6AjC4qiv1Jyq0bTTa_dHCeLokA@mail.gmail.com>
 <20120806194016.GB1120@n2100.arm.linux.org.uk>
 <CAKGA1b=hMZD3nd2sjXzR89-wX4BotxZwHOkkiLFoEL_CSS4zug@mail.gmail.com>
 <alpine.LFD.2.02.1208061829510.5231@xanadu.home>
 <CAKGA1bnJCSaVcErs3R8U3ZjQkhMmZAZPM=2P2R7udVc80ZmoDQ@mail.gmail.com>
 <alpine.LFD.2.02.1208061935380.5231@xanadu.home>
 <CAKGA1b=UBEf783egzoKqyXipfgziOy7QremNbFoz_i+r1X_9hQ@mail.gmail.com>
 <alpine.LFD.2.02.1208080033410.5231@xanadu.home>
 <CAKGA1bn7YwT33F=J0AMWAy+mSDy=7iUt2U46dmABXPc+664rNw@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208081436000.5231@xanadu.home>

On Wed, 8 Aug 2012, Matt Sealey wrote:

> On Wed, Aug 8, 2012 at 12:04 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > Note that I previously opposed the idea of any hard linkage between the
> > bootloader and the device tree content.  If you are spending so much
> > time validating your DT, you might feel so confident as to not allow it
> > to be updatable unless the whole bootloader is also updated.
> 
> The DTB is seperate from the firmware. But the firmware does all the pinmuxing
> long before the DTB is loaded - that way the DTB does the correct thing and
> in the worst case describes only the currently configured and ready-to-operate
> hardware (or in the best case, describes hardware the bootloader is currently
> using..).

I do not disagree with that.  What's the problem?

> There are good reasons to pinmux stuff at runtime - configurable hardware such
> as on my HP Touchpad, the headphone port is also a UART. It's creepy, but
> you may want to listen to audio and then switch to debugging

Exact.  There are cases like that where changing pin muxing at run time 
is necessary.  We therefore have a subsystem in Linux to deal with that 
in a common way.

But if nothing has to change at run time then just let the boot loader 
set it up and be done with it... if your boot loader isn't buggy that 
is.

I'm always fighting against too much reliance on DT especially for stuff 
that the code can easily probe at run time.  I'm all for _reducing_ the 
dependencies between all the moving pieces i.e. the firmware, the 
bootloader, the DTB and the kernel.  Interactions must be kept to a 
minimum.  Hence my stance on the fixed CPU mode for booting Linux.

> But as we just saw when submitting our device tree, we got a nit from 
> the maintainer that we don't set up pinctrl - and that pinctrl setup 
> would be required in case any device drivers needed it.

And what's wrong with that statement?  The key point here is "in case 
device drivers need it".  If they don't, you don't, right?  I don't 
think you should provide information in your DTB if it is never going to 
be useful.

> I'm saying no; pinctrl shouldn't be *required* by a platform, it 
> should be optional for all those where it's impossible to entertain it 
> or where there's some kind of late-hitting errata that nobody could 
> have predicted (like the MX51 SPI chipselect bug) and the 
> collaboration between updating U-Boot and Linux to match using GPIO 
> for chipselects instead of letting the chip handle it is too much cost 
> or effort compared to adding 2 entries to a device tree and updating 
> Linux.
> 
> But not 100 entries in device tree, please, and no hard requirements..

Again, no disagreement from me on this.


Nicolas


From matt at genesi-usa.com  Wed Aug  8 14:54:50 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 8 Aug 2012 13:54:50 -0500
Subject: Kernels on Bad Firmware (was Re: kernel entry for thumb2-only
 cpus)
In-Reply-To: <5022A6F9.2000206@wwwdotorg.org>
References: <CAKGA1b=8gZdgpSJ28Hff+1199J0GarLxZU-NAv7JJDuk+La0ew@mail.gmail.com>
 <5022A6F9.2000206@wwwdotorg.org>
Message-ID: <CAKGA1bmST6HropaLmQzPrVpcXirRwUx1jbHkr3WB8PG8qXMLJA@mail.gmail.com>

On Wed, Aug 8, 2012 at 12:50 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/08/2012 11:36 AM, Matt Sealey wrote:
> ...
>> The fact we could update it with a script was the awesome thing about
>> using OpenFirmware -
>> but U-Boot can do this too, since libfdt is there and it's one option
>> to enable it to allow script
>> based modification of the blob. If the DT is hardcoded into the firmware somehow
>> (CONFIG_OF_CONTROL I think) then platforms can load "boot.scr" from
>> the root filesystem ...
>
> Just a comment on CONFIG_OF_CONTROL...
>
> In U-Boot, CONFIG_OF_CONTROL determines whether U-Boot uses a device
> tree to configure itself. This is completely orthogonal to whether a
> device tree is passed to the kernel, and where the kernel DT comes from,
> which is still controlled by the bootm/bootz command parameters.
>
> The DT used to configure U-Boot isn't the same one passed to the kernel
> typically. The one for U-Boot is typically appended to the U-Boot image,
> whereas the one passed to the kernel is likely loaded from a file in
> /boot alongside the uImage/zImage of the kernel. I suppose the U-Boot
> script /could/ be written to encode the location of the appended DTB
> used by U-Boot and so pass the same one to the kernel, I don't believe
> anyone has done that. Besides, U-Boot's copy of the .dts files has
> diverged a little from the kernel's...:-(

... excuse me while I find a quiet room to scream in.

The ideal solution is as follows, though (taken from experience writing
OpenFirmware and Forth..)

* Bootloader straps from the processor and initializes the CPU. It may
(SHOULD) contain a basic device tree at this point specialized for the
CPU which defines the basic elements (memory start/size where it is
fixed, cpus, basic stuff as in dtsi skeletons)

* Board init code then uses a set of macros or internal functions to add
entries to the device tree as it brings up devices. Every device on the
system needs to be initialized as used. Anything that is not running
by default needs a "driver" to do this which does the minimal amount
required to give an environment for the OS (for instance, setting a
reasonable default for a clock or doing a mux setting). Adding a device
to the tree instantly makes it available to the rest of the bootloader,
such that devicetree_add_node("/foo/bar/mmc", ...) adds an MMC
device to the block devices list internally and can do generic boot stuff
from it.

* If Linux advances way beyond the driver bindings, the bootloader needs a
"runtime" way of externally specifying the hardware configuration such
that it can be scripted or otherwise automated (even if it's copious use
of mw.l and fdt_add or so in U-Boot hush shell scripting).

As such, actual device trees would go away from the kernel and be
a function of the bootloader's built-in specification, bootloader device
drivers, and pre-kernel execution of automated fixup.

What would be perfect is someone gets a clue about SoC design and
implements the bare minimum boot code inside the SoC. i.MX does this
about halfway - it has a common set of possibilities for iomux settings,
where it probes for SD/MMC, SPI, I2C, PATA, SATA, USB boot sources
and then provides a mask rom function to be able to stream *more* data
(using DMA, interrupts and with L2 cache enabled which is something
you cannot say about 99.99% of running U-Boots today) from the first
valid found source (overridden by fuses and boot config pins). Since it
can read from all these devices anyway it should be capable of selecting
a new boot device and streaming data to memory from these so the
bootloader no longer needs particular drivers for these boot sources.

Less advanced designs would just need a specific driver for it, as today,
with the added extra caveat that they would require adding their DT
bindings at the driver init time, as above.

I've been looking into the tinykernel/moboot solutions to create something
very similar to this but my urge to actually do it is quenched by the fact
we really should be using UEFI. The complexity of, for example, TianoCore
and the horrible HOB/PEI/PEIM legacy from x86 makes me want to cry,
though.

Has nobody really thought of the benefits of actually fixing the UEFI spec
on ARM such that you can grab something, write some bare platform code
that initializes it without the complicated chaining of pre-EFI, sort-of-EFI,
EFI-but-pre-kernel, EFI-booting-but-not-quite blocks? After all what the
kernel needs is valid tables in memory and a working call interface. How
you initialize the platform when standardized is nice, but it's overcomplex
and I think is lowering adoption on ARM... what's going on with device
trees or ACPI DSDT (and how is that going to make you guys cry)?

We had an internal architecture planning document here that basically
reworked UEFI ignoring some of the platform restrictions we had from
OpenFirmware or RTAS call interface (disable mmu, interrupts, caches
and then jump) - we did have a proof of concept (which we still call
Aura, although the actual "Aura" product has advanced to something
almost completely different) which allowed Linux to jump into a
pre-emptive code environment installed by firmware and perform any
driver code you needed at the firmware level. We used it to knock
down some performance problems on the PCI side and provide an
interface to several things which otherwise get done a lot (RTC handling,
PCI configuration space and domain handling) but you don't want to
basically kick Linux in the kidneys while you do it. After all, since
when did you want to disable interrupts, ditch the virtual
memory map, turn off the cache just to set or read the time?)

UEFI provides a lot of the core functionality Linux needs to boot in
a totally SoC-independent way, and even functionality Linux needs
to run, but it fails in that it requires that same disable-everything,
jump, re-enable everything architecture to persist for every call. We
were going to define a new system table that allowed for a new kind of
device tree (with the same kind of functionality as the current one,
but more flexible in that it allowed cross-referencing phandles to
actual UEFI-AURA runtime services). Where PPC and SPARC
platforms pull all the DT code out via calls to OF, ARM UEFI-AURA
would do this the same way. It may parse everything into a flattened
tree and use common functions after that, but the idea would be the
UEFI-AURA runtime would be able to dynamically update the tree
depending on things happening like hotplug events that could be
hidden from the OS somehow, DMA scripting, IPMI or other remote
management) or even encapsulate things like OpenGLES API calls
or media decoding (which is the ultimate expression of the requirements
of all these binary blob people) along with the ability to do funky things
like use the FPU in the firmware (would require the OS to understand
that this happens though) or NEON or so.

What it ends up being though is a mostly functional OS (which UEFI
basically is anyway if you add a GUI, which does exist) with Linux as
the shiny real-world interface to the top, tells the firmware it's done
with this functionality and has a real driver, tells the firmware it wants
to do this and that, passes userspace calls and data by virtual
addresses and references, reducing memory copies etc..

What we're talking about there though is 100 engineers, a couple years
and millions of dollars of funding to make the world a better place. I guess
we could always sign up for Kickstarter and put a few ads for new positions
on Stackoverflow.. :) so, just so you know, I'm not proposing we change
the world. We tried it, it's too big a job and there are too many people saying
"U-Boot is free and libfdt works".

I think the bare minimum "define the board properly and allow scripting changes"
would not be too big a job though, and as long as it can be done on UEFI
too.. that's fine. The work for the current device tree model would not go to
waste as it would be broadly compatible or at least immediately portable?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From swarren at wwwdotorg.org  Wed Aug  8 14:58:54 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 12:58:54 -0600
Subject: [PATCH 6/8] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <1344389967-8465-7-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-7-git-send-email-linux@prisktech.co.nz>
Message-ID: <5022B6EE.7060006@wwwdotorg.org>

On 08/07/2012 07:39 PM, Tony Prisk wrote:
> Merged existing board files to a single dt-capable file.
> Converted irq and timer code to devicetree.
> Removed existing device files that are no longer required with
> devicetree support.
>
> All existing platform devices are converted to devicetree nodes
> except GPIO and PWM.

Perhaps that also explains what I was commenting on in the GPIO driver
patch. Why not convert GPIO too?

> diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c

>  /*
> - *  arch/arm/mach-vt8500/irq.c
> + *  arch/arm/mach-vt8500/irq_dt.c

This file didn't get renamed?

> diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c

> +void __init vt8500_init(void)
> +{
> +	struct device_node *np, *fb;
> +	void __iomem *gpio_base;
> +
> +#ifdef CONFIG_FB_VT8500
> +	fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
> +	if (fb) {
> +		np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
> +		if (np) {
> +			gpio_base = of_iomap(np, 0);
> +
> +			if (!gpio_base)
> +				pr_err("%s:of_iomap(gpio_mux) failed\n", __func__);
> +
> +			of_node_put(np);
> +		} else {
> +			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
> +			if (!gpio_base)
> +				pr_err("%s:ioremap(legacy_gpio_mux) failed\n", __func__);
> +		}
> +		if (gpio_base) {
> +			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
> +				gpio_base + VT8500_GPIO_MUX_REG);
> +			iounmap(gpio_base);
> +		} else
> +			pr_err("%s: Could not remap GPIO mux\n", __func__);
> +
> +		of_node_put(fb);
> +	}
> +#endif

That looks quite suspicious. What's it doing? Is this something that
should be part of a pinctrl driver, or the GPIO driver?


From arnd at arndb.de  Wed Aug  8 13:19:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 17:19:40 +0000
Subject: [PATCH 04/11] ARM: ux500: really kill snowball_of_platform_devs
In-Reply-To: <20120808162200.GB30473@gmail.com>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-5-git-send-email-arnd@arndb.de>
 <20120808162200.GB30473@gmail.com>
Message-ID: <201208081719.40749.arnd@arndb.de>

On Wednesday 08 August 2012, Lee Jones wrote:
> On Wed, Aug 08, 2012 at 04:47:21PM +0200, Arnd Bergmann wrote:
> > Commit fc67a597a "ARM: ux500: Remove temporary snowball_of_platform_devs
> > enablement structure" removed the only user of this variable, but did
> > not actually remove the array itself.
> > 
> > Without this patch, building u8500_defconfig results in:
> > 
> > arch/arm/mach-ux500/board-mop500.c:729:32: warning: 'snowball_of_platform_devs' defined but not used [-Wunused-variable]
> 
> I've already sent a patch that does this:
> 
> https://lkml.org/lkml/2012/7/31/305
> 
> Just waiting on Linus to review the set.

Ok, I've removed my version.

	Arnd



From arnd at arndb.de  Wed Aug  8 13:17:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 17:17:47 +0000
Subject: [PATCH 3/6] ARM: sa1100: include asm/io.h in hackkit leds code
In-Reply-To: <20120808153655.GN18957@n2100.arm.linux.org.uk>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-4-git-send-email-arnd@arndb.de>
 <20120808153655.GN18957@n2100.arm.linux.org.uk>
Message-ID: <201208081717.47747.arnd@arndb.de>

On Wednesday 08 August 2012, Russell King - ARM Linux wrote:
> On Wed, Aug 08, 2012 at 02:54:50PM +0200, Arnd Bergmann wrote:
> > The sa1100 definition of the io_p2v macro has changed in v3.6, and this one
> > file stopped working because of that.
> > 
> > Without this patch, building hackkit_defconfig results in:
> > 
> > arch/arm/mach-sa1100/leds-hackkit.c: In function 'hackkit_leds_event':
> > arch/arm/mach-sa1100/leds-hackkit.c:39:4: error: implicit declaration of function 'IOMEM' [-Werror=implicit-function-declaration]
> 
> NAK.  Should be linux/io.h


Right, fixed now.

Thanks for having a look over this!

	Arnd



From arnd at arndb.de  Wed Aug  8 13:26:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 17:26:21 +0000
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <s5hwr19fi6h.wl%tiwai@suse.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <201208081622.29777.arnd@arndb.de> <s5hwr19fi6h.wl%tiwai@suse.de>
Message-ID: <201208081726.21878.arnd@arndb.de>

On Wednesday 08 August 2012, Takashi Iwai wrote:
> At Wed, 8 Aug 2012 16:22:29 +0000,
> Arnd Bergmann wrote:
> > > Laxman already posted a patch for this, which I'm hoping will make it
> > > into 3.6, through the I2C tree.
> > > 
> > > http://www.spinics.net/lists/linux-i2c/msg09359.html
> > 
> > Ok, dropping this one then.
> 
> I'm going to fix the similar errors in sound tree tomorrow, too.
> 

Ok. this leaves the omap-rng driver, and my patch comes down to the below.
Thanks!

	Arnd

8<----

From d83e9e0e5c0e41a0ee2ba6293c8be21e54988f99 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Sat, 4 Aug 2012 07:11:34 +0000
Subject: [PATCH] omap-rng: fix use of SIMPLE_DEV_PM_OPS

omap_rng_suspend and omap_rng_resume are unused if CONFIG_PM is enabled
but CONFIG_PM_SLEEP is disabled. I found this while building all defconfig
files on ARM. It's not clear to me if this is the right solution, but
at least it makes the code consistent again.

Without this patch, building omap1_defconfig results in:

drivers/char/hw_random/omap-rng.c:165:12: warning: 'omap_rng_suspend' defined but not used [-Wunused-function]
drivers/char/hw_random/omap-rng.c:171:12: warning: 'omap_rng_resume' defined but not used [-Wunused-function]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Herbert Xu <herbert at gondor.apana.org.au>

diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index d706bd0e..4fbdceb 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -160,7 +160,7 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 
 static int omap_rng_suspend(struct device *dev)
 {



From arnd at arndb.de  Wed Aug  8 15:14:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 19:14:17 +0000
Subject: [PATCH 01/11] ARM: topology: mark init_cpu_topology as __init
In-Reply-To: <5022A79E.6050504@codeaurora.org>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-2-git-send-email-arnd@arndb.de>
 <5022A79E.6050504@codeaurora.org>
Message-ID: <201208081914.17651.arnd@arndb.de>

On Wednesday 08 August 2012, Stephen Boyd wrote:
> 
> On 08/08/12 07:47, Arnd Bergmann wrote:
> > The init_cpu_topology function can be put into the __init section
> > and discarded after boot, because it is only called from
> > smp_prepare_cpus, which is also marked __init. This was reported
> > by gcc after Vincent Guittot added the parse_dt_topology function
> > in 339ca09d7ada "ARM: 7463/1: topology: Update cpu_power according to DT
> > information".
> >
> > Without this patch, building kzm9g_defconfig results in:
> >
> > WARNING: vmlinux.o(.text+0xb5a0): Section mismatch in reference from the function init_cpu_topology() to the function .init.text:parse_dt_topology()
> > The function init_cpu_topology() references
> > the function __init parse_dt_topology().
> > This is often because init_cpu_topology lacks a __init
> > annotation or the annotation of parse_dt_topology is wrong.
> >
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Vincent Guittot <vincent.guittot at linaro.org>
> > Cc: Namhyung Kim <namhyung at kernel.org>
> > Cc: Peter Zijlstra <a.p.zijlstra at chello.nl>
> > Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> > ---
> 
> This is already in the patch tracker
> 
> http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7482/1

Ok, dropped here.

> I also notice that store_cpu_topology() should be marked __cpuinit and
> update_siblings_mask, middle_capacity, cpu_capacity, and
> update_cpu_power should be static. We should probably also rename
> update_cpu_power() so as to not conflict with the one in kernel/sched/fair.c

Yes, all good points. 

	Arnd


From arnd at arndb.de  Wed Aug  8 15:17:18 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 8 Aug 2012 19:17:18 +0000
Subject: [PATCH 8/8] ARM: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <5022B242.1050001@wwwdotorg.org>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
 <5022B242.1050001@wwwdotorg.org>
Message-ID: <201208081917.19111.arnd@arndb.de>

On Wednesday 08 August 2012, Stephen Warren wrote:
> I think that's all just:
> 
> module_platform_driver(vt8500_gpio_driver);
> 
> (except that _init uses platform_driver_probe() rather than
> platform_driver_register(), which seems unusual. I guess that explains
> the of_find_matching_node() above too.)

Ah, I totally missed both of these. Using platform_driver_register
is definitely preferred over platform_driver_probe in cases like
this, so using module_platform_driver is the right simplification.

	Arnd


From rjw at sisk.pl  Wed Aug  8 15:25:55 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 8 Aug 2012 21:25:55 +0200
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <201208081726.21878.arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <s5hwr19fi6h.wl%tiwai@suse.de> <201208081726.21878.arnd@arndb.de>
Message-ID: <201208082125.56184.rjw@sisk.pl>

On Wednesday, August 08, 2012, Arnd Bergmann wrote:
> On Wednesday 08 August 2012, Takashi Iwai wrote:
> > At Wed, 8 Aug 2012 16:22:29 +0000,
> > Arnd Bergmann wrote:
> > > > Laxman already posted a patch for this, which I'm hoping will make it
> > > > into 3.6, through the I2C tree.
> > > > 
> > > > http://www.spinics.net/lists/linux-i2c/msg09359.html
> > > 
> > > Ok, dropping this one then.
> > 
> > I'm going to fix the similar errors in sound tree tomorrow, too.
> > 
> 
> Ok. this leaves the omap-rng driver, and my patch comes down to the below.
> Thanks!

Looks good!

Sorry for introducing those warnings in the first place, I should have been
more careful about that.

Thanks,
Rafael


> 8<----
> 
> From d83e9e0e5c0e41a0ee2ba6293c8be21e54988f99 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Sat, 4 Aug 2012 07:11:34 +0000
> Subject: [PATCH] omap-rng: fix use of SIMPLE_DEV_PM_OPS
> 
> omap_rng_suspend and omap_rng_resume are unused if CONFIG_PM is enabled
> but CONFIG_PM_SLEEP is disabled. I found this while building all defconfig
> files on ARM. It's not clear to me if this is the right solution, but
> at least it makes the code consistent again.
> 
> Without this patch, building omap1_defconfig results in:
> 
> drivers/char/hw_random/omap-rng.c:165:12: warning: 'omap_rng_suspend' defined but not used [-Wunused-function]
> drivers/char/hw_random/omap-rng.c:171:12: warning: 'omap_rng_resume' defined but not used [-Wunused-function]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Herbert Xu <herbert at gondor.apana.org.au>
> 
> diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
> index d706bd0e..4fbdceb 100644
> --- a/drivers/char/hw_random/omap-rng.c
> +++ b/drivers/char/hw_random/omap-rng.c
> @@ -160,7 +160,7 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#ifdef CONFIG_PM
> +#ifdef CONFIG_PM_SLEEP
>  
>  static int omap_rng_suspend(struct device *dev)
>  {
> 
> 
> 



From s.hauer at pengutronix.de  Wed Aug  8 15:27:07 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 8 Aug 2012 21:27:07 +0200
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
Message-ID: <20120808192707.GL1451@pengutronix.de>

On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:
> On Wed, Aug 8, 2012 at 1:55 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >>               .text
> >> +             .arm
> >>               .global imx_ssi_fiq_start
> >>               .global imx_ssi_fiq_end
> >>               .global imx_ssi_fiq_base
> >
> > I think it would be better to add a depends on !THUMB2_KERNEL to
> > SND_IMX_SOC_PCM_FIQ. The above may result in broken code in a thumb2
> > kernel, so I'd rather keep the compile error instead.
> 
> I'm curious as to how/why would it result in broken code? It's not
> possible that the processors relying on
> the imx_ssi_fiq_* stuff cannot run ARM code (unless Freescale shipped
> a weird version) so it should
> magically enter and exit. I wonder if it needs some thumb-interworking
> stuff wrapped around it though.
> You'd know better than me..

Currently I don't know if the code compiled in arm mode on an otherwise
thumb2 kernel does work and I do not have a thumb2 capacle hardware with
sound support to test this.

> 
> I'm a little worried that making it !CONFIG_THUMB2_KERNEL would
> basically make more than
> one of the boards in imx_v6_v7_defconfig suddenly lose audio support
> for no other reason..

Obviously no v6_v7 board does use this code as it is, because it does
not compile. So there's no risk of breaking something if we just disable
FIQ support in thumb2 mode.

Better disable an unused feature than add some untested code.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at prisktech.co.nz  Wed Aug  8 15:37:04 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 8 Aug 2012 19:37:04 +0000
Subject: [PATCH 6/8] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <5022B6EE.7060006@wwwdotorg.org>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-7-git-send-email-linux@prisktech.co.nz>,
 <5022B6EE.7060006@wwwdotorg.org>
Message-ID: <76F764B079F92A4E843589C893D0A022D1DCA8C1@SERVER.prisktech.co.nz>

>On 08/07/2012 07:39 PM, Tony Prisk wrote:
>> Merged existing board files to a single dt-capable file.
>> Converted irq and timer code to devicetree.
>> Removed existing device files that are no longer required with
>> devicetree support.
>>
>> All existing platform devices are converted to devicetree nodes
>> except GPIO and PWM.

>Perhaps that also explains what I was commenting on in the GPIO driver
>patch. Why not convert GPIO too?

GPIO was converted - I hadn't planned on doing it, but apparently I did it anyway :/
Comment is now removed from the commit message.

>> diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c

>>  /*
>> - *  arch/arm/mach-vt8500/irq.c
>> + *  arch/arm/mach-vt8500/irq_dt.c

>This file didn't get renamed?

Not sure what is going on here. I will take a look - it should just be renamed.

>> diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c

>> +void __init vt8500_init(void)
>> +{
>> +     struct device_node *np, *fb;
>> +     void __iomem *gpio_base;
>> +
>> +#ifdef CONFIG_FB_VT8500
>> +     fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
>> +     if (fb) {
>> +             np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
>> +             if (np) {
>> +                     gpio_base = of_iomap(np, 0);
>> +
>> +                     if (!gpio_base)
>> +                             pr_err("%s:of_iomap(gpio_mux) failed\n", __func__);
>> +
>> +                     of_node_put(np);
>> +             } else {
>> +                     gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
>> +                     if (!gpio_base)
>> +                             pr_err("%s:ioremap(legacy_gpio_mux) failed\n", __func__);
>> +             }
>> +             if (gpio_base) {
>> +                     writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
>> +                             gpio_base + VT8500_GPIO_MUX_REG);
>> +                     iounmap(gpio_base);
>> +             } else
>> +                     pr_err("%s: Could not remap GPIO mux\n", __func__);
>> +
>> +             of_node_put(fb);
>> +     }
>> +#endif

>That looks quite suspicious. What's it doing? Is this something that
>should be part of a pinctrl driver, or the GPIO driver?

This code is carried over from the original implementation but converted for device
tree. It should be part of a pinctrl driver, but we don't have one. It is basically selecting
between CCIR or LCD. 

Annoyingly, the bit-fields changed between models, so we have it twice, once for each
framebuffer driver. It needs to check for compatible nodes so that it only applies the setting
for the framebuffer type being requested by the dts because of the conflicting bit-fields.

Tony Prisk

From linux at prisktech.co.nz  Wed Aug  8 15:37:24 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 8 Aug 2012 19:37:24 +0000
Subject: [PATCH 5/8] video: vt8500: Add devicetree support for vt8500-fb
 and wm8505-fb
In-Reply-To: <5022B444.2020501@wwwdotorg.org>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-6-git-send-email-linux@prisktech.co.nz>,
 <5022B444.2020501@wwwdotorg.org>
Message-ID: <76F764B079F92A4E843589C893D0A022D1DCA8D0@SERVER.prisktech.co.nz>

>On 08/07/2012 07:39 PM, Tony Prisk wrote:
>> Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
>> tree bindings.

>> Small change in wm8505-fb.c to support WM8650 framebuffer color
>> format.

>That might warrant a separate patch?

The patch consisted of changing one value in one line and is commented in
the source. I didn't think it justified a separate patch as it has been thoroughly
tested and is unlikely to cause any problems.

>> diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c

>> +     np = of_find_node_by_name(NULL, "display");
>> +     if (!np) {
>> +             pr_err("%s: No display description in Device Tree\n", __func__);
>> +             ret = -EINVAL;
>> +             goto failed_free_res;
>> +     }

>I believe that using hard-coded node names is frowned upon. Better would
>be to put a phandle into the display controller's node that points at
>the node representing the display, e.g.:

Will do.

Regards
Tony Prisk

From linux at prisktech.co.nz  Wed Aug  8 15:46:54 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 8 Aug 2012 19:46:54 +0000
Subject: [rtc-linux] [PATCH 8/8] ARM: vt8500: gpio: Devicetree support
 for arch-vt8500
In-Reply-To: <CACRpkdabUWpDsBhz4ZEJNhEuqw-U+v-HrX7NcWoNLeuenv5t9A@mail.gmail.com>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-9-git-send-email-linux@prisktech.co.nz>
 <CACRpkdbYxpN9RCu8j8KMBgrb=-DsYZHq7hx-ifmHhJ0ZZcRYjw@mail.gmail.com>
 <201208080919.52592.arnd@arndb.de>,
 <CACRpkdabUWpDsBhz4ZEJNhEuqw-U+v-HrX7NcWoNLeuenv5t9A@mail.gmail.com>
Message-ID: <76F764B079F92A4E843589C893D0A022D1DCA8E3@SERVER.prisktech.co.nz>

>This needs to be named something intuitive like "vt8500_gpio_bank_regoffsets"

>Some kerneldoc intsead of the opaque comment above will also improve
>readability a lot:

>/**
>  * struct vt8500_gpio_bank_regoffsets
>  * @en: offset to enable register in the bank
>  * ...

Changes made as requested.


>My feeling however is that the "vt8500_chip->regoff" is wrong, which
>would mean only the first bank works. The code adds the same offsets
>per bank once more that it sets in this bank table.

>        Arnd

Oh.. Thanks for picking that up Arnd. You are absolutely correct. I have removed
the references for ->regoff. Left over from old code.

Regards

Tony Prisk

From marek.vasut at gmail.com  Wed Aug  8 15:57:20 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 8 Aug 2012 21:57:20 +0200
Subject: [Openpxa-users] pxa3x0 smart panel interface
In-Reply-To: <20120806152551.4ec2cad0@laptoppieter>
References: <20120806152551.4ec2cad0@laptoppieter>
Message-ID: <201208082157.22064.marek.vasut@gmail.com>

Dear pieterg,

CCing linux-arm-kernel and Haojian

> Hi all,
> 
> Does any of you have experience with interfacing smart lcd panels, with
> a pxa3x0?
> 
> I'm interfacing an ILI9327DS smart panel controller, all commands
> are handled correctly, however the SMART_CMD_WRITE_FRAME command (which
> sends out all frame data) seems to produce an invalid number of output
> bytes every now and then.
> This results in a shifted display, every 10-100 updates (immediately
> corrected by the next update)
> 
> The strange thing is that this does not occur with a pxa300, but it
> occurs with the pxa310 and pxa320.
> However running the 310/320 with the same ACCR as I'm running the 300
> does not 'fix' it.
> And I'm not sure it is even timing related, I've tried to configure
> huge smart timing delay parameters, but the results remain the same.
> (in fact I can even lower the parameters to way under the
> controller specs, and the issue does not get worse).
> I've also played with the drive strength of the LCD lines, which also
> does not have an effect on the issue.
> 
> I do not think this is a controller bug, because before this ILI9327DS
> controller, we had a display with a different controller chip, with
> which I experienced the same thing, however at that time even with the
> pxa300.
> We switched to the ILI9327DS (for a different reason), and I was glad to
> find that it worked fine with the pxa300.
> Till I discovered it had the same issues, but then only with a
> pxa310/320.
> 
> Does this sound familiar to anyone?
> Is there anything else I might try to get rid of this issue?
> 
> Regards, Pieter


Best regards,
Marek Vasut


From linux at prisktech.co.nz  Wed Aug  8 16:08:24 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 8 Aug 2012 20:08:24 +0000
Subject: [PATCH 1/8] arm: vt8500: Add device tree files for
 VIA/Wondermedia SoC's
In-Reply-To: <5022B342.7080606@wwwdotorg.org>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-2-git-send-email-linux@prisktech.co.nz>,
 <5022B342.7080606@wwwdotorg.org>
Message-ID: <76F764B079F92A4E843589C893D0A022D1DCA8F3@SERVER.prisktech.co.nz>

>It appears more typical to use "-" rather than "_" in the filename to
>join SoC and board names.

Fixed.

>I guess "_ref" means "reference". Is that how the boards are commonly
>known? Are you sure there will never be another reference board for
>these SoCs? Given the "model" values in the file, something more like
>vt8500-bv07.dts might be more appropriate?

I'm fairly certain there will never be another reference board, as these
SoC's seem to disappear after a few months and a new one comes out.
Most of the models are chinese in origin with no real identifying names.
Having said that, I have renamed the dts files to a less 'generic' name.
vt8500-bv07.dts, wm8850-mid.dts.
wm8505-ref is the same as I can't find any other identification for it, and
everyone else I've had contact with who has one has the same board
design.

>> +     /*
>> +      * Display node is based on Sascha Hauer's patch on dri-devel.
>> +      * Added a bpp property to calculate the size of the framebuffer
>> +      * until the binding is formalized.
>> +      */
>> +     display {

>Maybe it's better to just hold off on adding this node, to wait until
>the binding is complete so this file doesn't churn? Certainly it sounded
>like Sascha was going to change the binding a little in response to
>comments it received.

My understanding with Sascha's patch is that it won't include a pixel
format property and therefore we won't be able to use his binding properly
until its revisited. Without this node, we have no display output available
other than uart - and that's only available if you modify the hardware.

This patchset will make arch-vt8500 nearly unusable without this node as
we would have to leave the framebuffer code out as well.

Always open to suggestions,

Regards
Tony Prisk

From olof at lixom.net  Wed Aug  8 16:17:27 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 8 Aug 2012 13:17:27 -0700
Subject: Kernels on Bad Firmware (was Re: kernel entry for thumb2-only
 cpus)
In-Reply-To: <5022A6F9.2000206@wwwdotorg.org>
References: <CAKGA1b=8gZdgpSJ28Hff+1199J0GarLxZU-NAv7JJDuk+La0ew@mail.gmail.com>
 <5022A6F9.2000206@wwwdotorg.org>
Message-ID: <CAOesGMiEt9hGE=WzDrNg4vkcfu+Z6Q9V42tzKE2ENq3ifcOEfg@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:50 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/08/2012 11:36 AM, Matt Sealey wrote:
> ...
>> The fact we could update it with a script was the awesome thing about
>> using OpenFirmware -
>> but U-Boot can do this too, since libfdt is there and it's one option
>> to enable it to allow script
>> based modification of the blob. If the DT is hardcoded into the firmware somehow
>> (CONFIG_OF_CONTROL I think) then platforms can load "boot.scr" from
>> the root filesystem ...
>
> Just a comment on CONFIG_OF_CONTROL...
>
> In U-Boot, CONFIG_OF_CONTROL determines whether U-Boot uses a device
> tree to configure itself. This is completely orthogonal to whether a
> device tree is passed to the kernel, and where the kernel DT comes from,
> which is still controlled by the bootm/bootz command parameters.
>
> The DT used to configure U-Boot isn't the same one passed to the kernel
> typically. The one for U-Boot is typically appended to the U-Boot image,
> whereas the one passed to the kernel is likely loaded from a file in
> /boot alongside the uImage/zImage of the kernel. I suppose the U-Boot
> script /could/ be written to encode the location of the appended DTB
> used by U-Boot and so pass the same one to the kernel, I don't believe
> anyone has done that. Besides, U-Boot's copy of the .dts files has
> diverged a little from the kernel's...:-(

Right, OF_CONTROL was instigated around here, and I explicitly have
kept them from attempting to do that. Why? Because the U-boot device
tree is non-standard, and has a bunch of u-boot cruft in it. We quite
frankly don't want to see it in the kernel.

But the bigger argument is that the device tree bindings are still
rapidly evolving together with the kernel, and until we reach a more
stable state, it's a bad idea to provide a tree that is separate from
the kernel (on ARM), since there will be no way to undo early
mistakes.

The plan is to, at some point in time, take the device tree bindings,
as well as the DTS sources, out of the kernel tree and to a separate
repo. But not until the bindings have settled down quite a bit more.


-Olof


From paul at pwsan.com  Wed Aug  8 16:19:34 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 8 Aug 2012 14:19:34 -0600 (MDT)
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
 <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1208081411010.6819@utopia.booyaka.com>

Hi Vaibhav

On Wed, 8 Aug 2012, Bedia, Vaibhav wrote:

> On Wed, Aug 08, 2012 at 19:35:50, Paul Walmsley wrote:
>
> > It doesn't seem to me that this would necessarily always be an error.  
> > Suppose some init code to create cpsw devices is running on an OMAP3430.  
> > Then a omap_hwmod_for_each_by_class() that doesn't locate anything 
> > wouldn't be an error, right?
> 
> Well, I think a failed lookup operation will be a bit expensive since it
> iterates over the whole list of registered hwmods and hence put in the
> pr_err().

If performance is a serious problem there, we can maintain a list of hwmod 
pointers inside each struct omap_hwmod_class, updated when the hwmods are 
registered.  But as far as I know, performance hasn't been an issue here 
yet.  If performance is the real motivation, I'd rather see an 
implementation of per-class lists as described above.

> But I don't see how the SoC specific example that you pointed out
> could be handled without putting in cpu_is_* checks in the registration
> process itself :(

Hmm, why not?

To continue the earlier example, the init code in the platform code simply 
calls omap_hwmod_for_each_by_class(), and creates the appropriate device 
if anything was found.  If no cpsw IP blocks are present on a given SoC, 
nothing would happen.  No cpu_is_*() would be needed.


- Paul


From chris_brand at broadcom.com  Wed Aug  8 17:04:30 2012
From: chris_brand at broadcom.com (chris_brand at broadcom.com)
Date: Wed, 8 Aug 2012 14:04:30 -0700
Subject: [PATCH] ARM: mm: MMU mapping of CMA regions
Message-ID: <1344459870-12790-1-git-send-email-chris_brand@broadcom.com>

From: Chris Brand <cbrand at broadcom.com>

Fix dma_contiguous_remap() so that it continues through all the
regions, even after encountering one that is outside lowmem.
Without this change, if you have two CMA regions, the first outside
lowmem and the second inside lowmem, neither will get
set up in the MMU. Data written to the second region then doesn't get
automatically flushed from the cache into memory.

Signed-off-by: Chris Brand <cbrand at broadcom.com>
---
 arch/arm/mm/dma-mapping.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 655878b..4a4f3f9 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -388,7 +388,7 @@ void __init dma_contiguous_remap(void)
 		if (end > arm_lowmem_limit)
 			end = arm_lowmem_limit;
 		if (start >= end)
-			return;
+			continue;
 
 		map.pfn = __phys_to_pfn(start);
 		map.virtual = __phys_to_virt(start);
-- 
1.7.5.4




From arnd at arndb.de  Wed Aug  8 17:27:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:50 +0200
Subject: [PATCH 02/10] ARM: ks8695: __arch_virt_to_dma type handling
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-3-git-send-email-arnd@arndb.de>

__arch_virt_to_dma expects a virtual address pointer, but
the ks8695 implementation of this macro treats it as an
integer. Adding a type cast avoids hundreds of identical
warning messages.

Without this patch, building acs5k_defconfig results in:

arch/arm/include/asm/dma-mapping.h: In function 'virt_to_dma':
arch/arm/include/asm/dma-mapping.h:60:2: warning: passing argument 1 of '__virt_to_phys' makes integer from pointer without a cast [enabled by default]
arch/arm/include/asm/memory.h:172:60: note: expected 'long unsigned int' but argument is of type 'void *'
In file included from include/linux/dma-mapping.h:73:0,
                 from include/linux/skbuff.h:33,
                 from security/commoncap.c:21:

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-ks8695/include/mach/memory.h |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index f7e1b9b..95e731a 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -34,7 +34,8 @@ extern struct bus_type platform_bus_type;
 #define __arch_dma_to_virt(dev, x)	({ (void *) (is_lbus_device(dev) ? \
 					__phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)	({ is_lbus_device(dev) ? \
-					(dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
+					(dma_addr_t)__virt_to_phys((unsigned long)x) \
+					: (dma_addr_t)__virt_to_bus(x); })
 #define __arch_pfn_to_dma(dev, pfn)	\
 	({ dma_addr_t __dma = __pfn_to_phys(pfn); \
 	   if (!is_lbus_device(dev)) \
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:56 +0200
Subject: [PATCH 08/10] ARM: s3c24xx: enable CONFIG_BUG for tct_hammer
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-9-git-send-email-arnd@arndb.de>

Disabling CONFIG_BUG creates an insane amount of build warnings, which
makes it useless to check for building defconfigs to see if new
warnings show up.

Without this patch, building tct_hammer_defconfig results in:

net/packet/af_packet.c: In function 'tpacket_rcv':
net/packet/af_packet.c:1889:30: warning: 'hdrlen' may be used uninitialized in this function [-Wuninitialized]
net/core/ethtool.c: In function 'ethtool_get_feature_mask':
net/core/ethtool.c:213:1: warning: control reaches end of non-void function [-Wreturn-type]
block/cfq-iosched.c: In function 'cfq_async_queue_prio':
block/cfq-iosched.c:2914:1: warning: control reaches end of non-void function [-Wreturn-type]
mm/bootmem.c: In function 'mark_bootmem':
mm/bootmem.c:352:1: warning: control reaches end of non-void function [-Wreturn-type]
net/core/dev.c: In function 'skb_warn_bad_offload':
net/core/dev.c:1904:33: warning: unused variable 'null_features' [-Wunused-variable]
drivers/mtd/chips/cfi_probe.c: In function 'cfi_chip_setup':
include/linux/mtd/cfi.h:489:3: warning: 'r.x[0]' may be used uninitialized in this function [-Wuninitialized]
include/linux/mtd/map.h:394:11: note: 'r.x[0]' was declared here
include/linux/mtd/cfi.h:489:3: warning: 'r.x[0]' may be used uninitialized in this function [-Wuninitialized]
(and many more)

The size of vmlinux increases by 1.78% because of this:

size obj-arm/vmlinux.nobug
   text    data     bss     dec     hex filename
   2108474  116916   55352 2280742  22cd26 obj-arm/vmlinux
size obj-arm/vmlinux.bug
   text    data     bss     dec     hex filename
   2150804  116916   53696 2321416  236c08 obj-arm/vmlinux

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Ben Dooks <ben-linux at fluff.org>
---
 arch/arm/configs/tct_hammer_defconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 1d24f84..71277a1 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_KALLSYMS is not set
-# CONFIG_BUG is not set
+# CONFIG_BUGVERBOSE is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_SHMEM is not set
 CONFIG_SLOB=y
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:55 +0200
Subject: [PATCH 07/10] ARM: rpc: check device_register return code in
 ecard_probe
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-8-git-send-email-arnd@arndb.de>

device_register is marked __must_check, so we better propagate the error
value by returning it from ecard_probe.

Without this patch, building rpc_defconfig results in:

arch/arm/mach-rpc/ecard.c: In function 'ecard_probe':
arch/arm/mach-rpc/ecard.c:963:17: warning: ignoring return value of 'device_register', declared with attribute warn_unused_result [-Wunused-result]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mach-rpc/ecard.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index b91bc87..fcb1d59 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -960,7 +960,9 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
 	*ecp = ec;
 	slot_to_expcard[slot] = ec;
 
-	device_register(&ec->dev);
+	rc = device_register(&ec->dev);
+	if (rc)
+		goto nodev;
 
 	return 0;
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:58 +0200
Subject: [PATCH 10/10] leds: renesas: fix error handling
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-11-git-send-email-arnd@arndb.de>

bfe4c041 "leds: convert Renesas TPU LED driver to devm_kzalloc() and
cleanup error exit path" introduced a possible case in which r_tpu_probe
calls iounmap on a wild pointer. This changes the one case that was
missed in the same way as the other error paths.

Without this patch, building kota2_defconfig results in:

drivers/leds/leds-renesas-tpu.c: In function 'r_tpu_probe':
drivers/leds/leds-renesas-tpu.c:246:6: warning: 'ret' may be used uninitialized in this function [-Wuninitialized]
drivers/leds/leds-renesas-tpu.c:308:17: warning: 'p' may be used uninitialized in this function [-Wuninitialized]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Bryan Wu <bryan.wu at canonical.com>
Cc: Magnus Damm <damm at opensource.se>

--- a/drivers/leds/leds-renesas-tpu.c
+++ b/drivers/leds/leds-renesas-tpu.c
@@ -247,7 +247,7 @@ static int __devinit r_tpu_probe(struct platform_device *pdev)

        if (!cfg) {
                dev_err(&pdev->dev, "missing platform data\n");
-               goto err0;
+               return -ENODEV;
        }

        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
---
 drivers/leds/leds-renesas-tpu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/leds/leds-renesas-tpu.c b/drivers/leds/leds-renesas-tpu.c
index 9ee12c2..771ea06 100644
--- a/drivers/leds/leds-renesas-tpu.c
+++ b/drivers/leds/leds-renesas-tpu.c
@@ -247,7 +247,7 @@ static int __devinit r_tpu_probe(struct platform_device *pdev)
 
 	if (!cfg) {
 		dev_err(&pdev->dev, "missing platform data\n");
-		goto err0;
+		return -ENODEV;
 	}
 
 	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:57 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:57 +0200
Subject: [PATCH 09/10] ARM: rpc: Fix building RiscPC
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-10-git-send-email-arnd@arndb.de>

ARMv3 support was removed in 357c9c1f07 "ARM: Remove support for ARMv3
ARM610 and ARM710 CPUs", which explicitly left parts of the CPU32v3
support in place for building RiscPC. However, this does not actually
build in my test setup.

This is probably not the right solution, but maybe someone has a better
idea for how to deal with this.

Without this patch, building rpc_defconfig results in:

arch/arm/lib/io-readsw-armv4.S: Assembler messages:
arch/arm/lib/io-readsw-armv4.S:23: Error: selected processor does not support ARM mode `ldrh ip,[r0]'
arch/arm/lib/io-readsw-armv4.S:25: Error: selected processor does not support ARM mode `strh ip,[r1],#2'
arch/arm/lib/io-readsw-armv4.S:38: Error: selected processor does not support ARM mode `ldrh r3,[r0]'
make[2]: *** [arch/arm/lib/io-readsw-armv4.o] Error 1
make[1]: *** [arch/arm/lib] Error 2

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/Kconfig    |    2 +-
 arch/arm/Makefile   |    1 -
 arch/arm/mm/Kconfig |   12 ++----------
 3 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..1e435185 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2259,7 +2259,7 @@ config FPE_NWFPE_XP
 
 config FPE_FASTFPE
 	bool "FastFPE math emulation (EXPERIMENTAL)"
-	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
+	depends on (!AEABI || OABI_COMPAT) && EXPERIMENTAL
 	---help---
 	  Say Y here to include the FAST floating point emulator in the kernel.
 	  This is an experimental much faster emulator which now also has full
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b4c2296..2c53344 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,7 +70,6 @@ endif
 arch-$(CONFIG_CPU_32v5)		:=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
 arch-$(CONFIG_CPU_32v4T)	:=-D__LINUX_ARM_ARCH__=4 -march=armv4t
 arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3
 
 # This selects how we optimise for the processor.
 tune-$(CONFIG_CPU_ARM7TDMI)	:=-mtune=arm7tdmi
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101b968..28773e6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -265,8 +265,7 @@ config CPU_ARM1026
 # SA110
 config CPU_SA110
 	bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
-	select CPU_32v3 if ARCH_RPC
-	select CPU_32v4 if !ARCH_RPC
+	select CPU_32v4
 	select CPU_ABRT_EV4
 	select CPU_PABRT_LEGACY
 	select CPU_CACHE_V4WB
@@ -395,12 +394,6 @@ config CPU_V7
 
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
-config CPU_32v3
-	bool
-	select TLS_REG_EMUL if SMP || !MMU
-	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
-	select CPU_USE_DOMAINS if MMU
-
 config CPU_32v4
 	bool
 	select TLS_REG_EMUL if SMP || !MMU
@@ -587,8 +580,7 @@ comment "Processor Features"
 
 config ARM_LPAE
 	bool "Support for the Large Physical Address Extension"
-	depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
-		!CPU_32v4 && !CPU_32v3
+	depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && !CPU_32v4
 	help
 	  Say Y if you have an ARMv7 processor supporting the LPAE page
 	  table format and you would like to access memory beyond the
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:54 +0200
Subject: [PATCH 06/10] ARM: davinci: don't use broken ntosd2_init_i2c
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-7-git-send-email-arnd@arndb.de>

ntosd2_init_i2c walks the ntosd2_i2c_info array, which it expects to
be populated with at least one member. gcc correctly warns about
the out-of-bounds access here.

Without this patch, building davinci_all_defconfig results in:

arch/arm/mach-davinci/board-neuros-osd2.c: In function 'davinci_ntosd2_init':
arch/arm/mach-davinci/board-neuros-osd2.c:187:20: warning: array subscript is above array bounds [-Warray-bounds]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Andrey Porodko <panda at chelcom.ru>
---
 arch/arm/mach-davinci/board-neuros-osd2.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5de69f2..9d40df9 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -162,6 +162,7 @@ static void __init davinci_ntosd2_map_io(void)
 	dm644x_init();
 }
 
+#if 0
 /*
  I2C initialization
 */
@@ -193,6 +194,12 @@ static	int ntosd2_init_i2c(void)
 	}
 	return status;
 }
+#else
+static  int ntosd2_init_i2c(void)
+{
+	return 0;
+}
+#endif
 
 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
 	.wires		= 4,
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:53 +0200
Subject: [PATCH 05/10] asm-generic: xor: mark static functions as
 __maybe_unused
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-6-git-send-email-arnd@arndb.de>

The asm-generic/xor.h header file is nasty and defines static functions
that are not inline. The header file is include by the ARM version of
asm/xor.h, which uses some but not all of the symbols defined there.

Marking the extraneous functions as __maybe_unused lets gcc drop them
without complaining.

Without this patch, building iop13xx_defconfig results in:

include/asm-generic/xor.h:696:34: warning: 'xor_block_8regs_p' defined but not used [-Wunused-variable]
include/asm-generic/xor.h:704:34: warning: 'xor_block_32regs_p' defined but not used [-Wunused-variable]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: Dan Williams <dan.j.williams at intel.com>
Cc: Neil Brown <neilb at suse.de>
---
 include/asm-generic/xor.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/asm-generic/xor.h b/include/asm-generic/xor.h
index 6028fb8..b4d8432 100644
--- a/include/asm-generic/xor.h
+++ b/include/asm-generic/xor.h
@@ -693,7 +693,7 @@ static struct xor_block_template xor_block_32regs = {
 	.do_5 = xor_32regs_5,
 };
 
-static struct xor_block_template xor_block_8regs_p = {
+static struct xor_block_template xor_block_8regs_p __maybe_unused = {
 	.name = "8regs_prefetch",
 	.do_2 = xor_8regs_p_2,
 	.do_3 = xor_8regs_p_3,
@@ -701,7 +701,7 @@ static struct xor_block_template xor_block_8regs_p = {
 	.do_5 = xor_8regs_p_5,
 };
 
-static struct xor_block_template xor_block_32regs_p = {
+static struct xor_block_template xor_block_32regs_p __maybe_unused = {
 	.name = "32regs_prefetch",
 	.do_2 = xor_32regs_p_2,
 	.do_3 = xor_32regs_p_3,
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:52 +0200
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-5-git-send-email-arnd@arndb.de>

The Linaro cross toolchain and probably others nowadays default to
building in THUMB2 mode. When building a kernel for a CPU that does
not support THUMB2, the compiler complains about incorrect flags.
We can work around this by setting -marm for all non-T2 builds.

Without this patch, building assabet_defconfig results in:

usr/initramfs_data.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
arch/arm/nwfpe/entry.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
firmware/cis/PCMLM28.cis.gen.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
(and many more)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/Makefile |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..b4c2296 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -111,6 +111,9 @@ AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
 ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)
 CFLAGS_MODULE	+=-fno-optimize-sibling-calls
 endif
+else
+CFLAGS_THUMB2  :=-marm
+AFLAGS_THUMB2	:=-marm
 endif
 
 # Need -Uarm for gcc < 3.x
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:49 +0200
Subject: [PATCH 01/10] ARM: footbridge: nw_gpio_lock is raw_spin_lock
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-2-git-send-email-arnd@arndb.de>

bd31b85960a "locking, ARM: Annotate low level hw locks as raw"
made nw_gpio_lock a raw spinlock, but did not change all the
users in device drivers. This fixes the remaining ones.

sound/oss/waveartist.c: In function 'vnc_mute_spkr':
sound/oss/waveartist.c:1485:2: warning: passing argument 1 of 'spinlock_check' from incompatible pointer type [enabled by default]
include/linux/spinlock.h:272:102: note: expected 'struct spinlock_t *' but argument is of type 'struct raw_spinlock_t *'
drivers/char/ds1620.c: In function 'netwinder_lock':
drivers/char/ds1620.c:77:2: warning: passing argument 1 of 'spinlock_check' from incompatible pointer type [enabled by default]
include/linux/spinlock.h:272:102: note: expected 'struct spinlock_t *' but argument is of type 'struct raw_spinlock_t *'
drivers/char/nwflash.c: In function 'kick_open':
drivers/char/nwflash.c:620:2: warning: passing argument 1 of 'spinlock_check' from incompatible pointer type [enabled by default]
include/linux/spinlock.h:272:102: note: expected 'struct spinlock_t *' but argument is of type 'struct raw_spinlock_t *'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/char/ds1620.c  |    8 ++++----
 drivers/char/nwflash.c |    4 ++--
 sound/oss/waveartist.c |    4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index aab9605..24ffd8c 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -74,21 +74,21 @@ static inline void netwinder_ds1620_reset(void)
 
 static inline void netwinder_lock(unsigned long *flags)
 {
-	spin_lock_irqsave(&nw_gpio_lock, *flags);
+	raw_spin_lock_irqsave(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_unlock(unsigned long *flags)
 {
-	spin_unlock_irqrestore(&nw_gpio_lock, *flags);
+	raw_spin_unlock_irqrestore(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_set_fan(int i)
 {
 	unsigned long flags;
 
-	spin_lock_irqsave(&nw_gpio_lock, flags);
+	raw_spin_lock_irqsave(&nw_gpio_lock, flags);
 	nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
-	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+	raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static inline int netwinder_get_fan(void)
diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c
index d45c334..04e2a94 100644
--- a/drivers/char/nwflash.c
+++ b/drivers/char/nwflash.c
@@ -617,9 +617,9 @@ static void kick_open(void)
 	 * we want to write a bit pattern XXX1 to Xilinx to enable
 	 * the write gate, which will be open for about the next 2ms.
 	 */
-	spin_lock_irqsave(&nw_gpio_lock, flags);
+	raw_spin_lock_irqsave(&nw_gpio_lock, flags);
 	nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
-	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+	raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 
 	/*
 	 * let the ISA bus to catch on...
diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c
index 24c430f..672af8b 100644
--- a/sound/oss/waveartist.c
+++ b/sound/oss/waveartist.c
@@ -1482,9 +1482,9 @@ vnc_mute_spkr(wavnc_info *devc)
 {
 	unsigned long flags;
 
-	spin_lock_irqsave(&nw_gpio_lock, flags);
+	raw_spin_lock_irqsave(&nw_gpio_lock, flags);
 	nw_cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE);
-	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+	raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static void
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:51 +0200
Subject: [PATCH 03/10] ARM: mv78xx0: fix win_cfg_base prototype
In-Reply-To: <1344461278-28245-1-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
Message-ID: <1344461278-28245-4-git-send-email-arnd@arndb.de>

Patch b6d1c33a31 "ARM: Orion: Consolidate the address map setup" tried
to merge the address map for the four orion platforms, but apparently
got it wrong for mv78xx0. Admittedly I don't understand what this
code actually does, but it's clear that the current version is
wrong.

Without this patch, building mv78xx0_defconfig results in:

arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: initialization from incompatible pointer type [enabled by default]
arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Michael Walle <michael at walle.cc>
Cc: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/mach-mv78xx0/addr-map.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d7..a9bc841 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -37,7 +37,7 @@
 #define WIN0_OFF(n)		(BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)		(BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
 
-static void __init __iomem *win_cfg_base(int win)
+static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
 	/*
 	 * Find the control register base address for this window.
-- 
1.7.10



From arnd at arndb.de  Wed Aug  8 17:27:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed,  8 Aug 2012 23:27:48 +0200
Subject: [PATCH 00/10] ARM: interesting warnings from defconfig builds
Message-ID: <1344461278-28245-1-git-send-email-arnd@arndb.de>

Most of these have been around for quite a while, but I think we
should fix them nonetheless. In some cases, I'm not very sure about
my solution, so I'd appreciate any ACK or NAK I can get.

	Arnd

Arnd Bergmann (10):
  ARM: footbridge: nw_gpio_lock is raw_spin_lock
  ARM: ks8695: __arch_virt_to_dma type handling
  ARM: mv78xx0: fix win_cfg_base prototype
  ARM: pass -marm to gcc by default
  asm-generic: xor: mark static functions as __maybe_unused
  ARM: davinci: don't use broken ntosd2_init_i2c
  ARM: rpc: check device_register return code in ecard_probe
  ARM: s3c24xx: enable CONFIG_BUG for tct_hammer
  ARM: rpc: Fix building RiscPC
  leds: renesas: fix error handling

 arch/arm/Kconfig                           |    2 +-
 arch/arm/Makefile                          |    4 +++-
 arch/arm/configs/tct_hammer_defconfig      |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c  |    7 +++++++
 arch/arm/mach-ks8695/include/mach/memory.h |    3 ++-
 arch/arm/mach-mv78xx0/addr-map.c           |    2 +-
 arch/arm/mach-rpc/ecard.c                  |    4 +++-
 arch/arm/mm/Kconfig                        |   12 ++----------
 drivers/char/ds1620.c                      |    8 ++++----
 drivers/char/nwflash.c                     |    4 ++--
 drivers/leds/leds-renesas-tpu.c            |    2 +-
 include/asm-generic/xor.h                  |    4 ++--
 sound/oss/waveartist.c                     |    4 ++--
 13 files changed, 31 insertions(+), 27 deletions(-)

-- 
1.7.10

Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Michael Walle <michael at walle.cc>
Cc: Nicolas Pitre <nico at linaro.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Dave Martin <dave.martin at linaro.org>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
Cc: Dan Williams <dan.j.williams at intel.com>
Cc: Neil Brown <neilb at suse.de>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Andrey Porodko <panda at chelcom.ru>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Bryan Wu <bryan.wu at canonical.com>
Cc: Magnus Damm <damm at opensource.se>


From festevam at gmail.com  Wed Aug  8 17:30:51 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 8 Aug 2012 18:30:51 -0300
Subject: USB host on mx23-olinuxino
Message-ID: <CAOMZO5BS_f1cJk=15gpYV3q-hza+ehST_DkTdUa27N-w5KCCOA@mail.gmail.com>

Hi,

I am trying to add USB support for mx23olinuxino board (running
3.6-rc1), but I am getting:

[    0.890000] usbcore: registered new interface driver asix
[    0.890000] usbcore: registered new interface driver cdc_ether
[    0.900000] usbcore: registered new interface driver smsc95xx
[    0.900000] usbcore: registered new interface driver net1080
[    0.910000] usbcore: registered new interface driver cdc_subset
[    0.920000] usbcore: registered new interface driver zaurus
[    0.920000] usbcore: registered new interface driver cdc_ncm
[    0.930000] Initializing USB Mass Storage driver...
[    0.930000] usbcore: registered new interface driver usb-storage
[    0.940000] USB Mass Storage support registered.
[    0.950000] ci_hdrc ci_hdrc.0: doesn't support gadget
[    0.960000] ci_hdrc ci_hdrc.0: ChipIdea HDRC EHCI
[    0.960000] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[    1.020000] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[    1.030000] hub 1-0:1.0: USB hub found
[    1.040000] hub 1-0:1.0: 1 port detected

....

[    1.300000] hub 1-0:1.0: unable to enumerate USB device on port 1
[    1.520000] hub 1-0:1.0: unable to enumerate USB device on port 1
[    1.740000] hub 1-0:1.0: unable to enumerate USB device on port 1
[    1.960000] hub 1-0:1.0: unable to enumerate USB device on port 1
[    2.180000] hub 1-0:1.0: unable to enumerate USB device on port 1
... and keeps forever

My changes are below. Hardware is fine as I can use USB host running
the FSL 2.6.35 kernel.

Schematics:
https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/iMX233-OLinuXino-Maxi/iMX233-OLINUXINO-MAXI_Rev_B1.sch.pdf

If anyone has any suggestions, I will be glad to hear.

Thanks,

Fabio Estevam

---
 arch/arm/boot/dts/imx23-olinuxino.dts |   41 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx23.dtsi          |    8 +++++-
 2 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts
b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1..3ab18c3 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,21 @@
 				bus-width = <4>;
 				status = "okay";
 			};
+
+			pinctrl at 80018000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&hog_pins_a>;
+
+				hog_pins_a: hog-gpios at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
+					>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+			};
 		};

 		apbx at 80040000 {
@@ -39,6 +54,32 @@
 				pinctrl-0 = <&duart_pins_a>;
 				status = "okay";
 			};
+
+			usbphy0: usbphy at 8007c000 {
+				status = "okay";
+			};
+		};
+
+	};
+
+	ahb at 80080000 {
+		usb0: usb at 80080000 {
+			vbus-supply = <&reg_usb0_vbus>;
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_usb0_vbus: usb0_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
+			gpio = <&gpio0 17 0>;
+			enable-active-high;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e613831..83a8152 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -414,7 +414,8 @@
 				status = "disabled";
 			};

-			usbphy at 8007c000 {
+			usbphy0: usbphy at 8007c000 {
+				compatible = "fsl,imx23-usbphy";
 				reg = <0x8007c000 0x2000>;
 				status = "disabled";
 			};
@@ -428,8 +429,11 @@
 		reg = <0x80080000 0x80000>;
 		ranges;

-		usbctrl at 80080000 {
+		usb0: usb at 80080000 {
+			compatible = "fsl,imx23-usb", "fsl,imx27-usb";
 			reg = <0x80080000 0x40000>;
+			interrupts = <11>;
+			fsl,usbphy = <&usbphy0>;
 			status = "disabled";
 		};
 	};
--


From festevam at gmail.com  Wed Aug  8 18:06:29 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  8 Aug 2012 19:06:29 -0300
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Add Chipidea USB driver support
Message-ID: <1344463589-8115-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Add Chipidea USB driver support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/imx_v6_v7_defconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f725b96..5f6138d 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -179,6 +179,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_MXS_PHY=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
-- 
1.7.1



From ricardo.neri at ti.com  Wed Aug  8 18:12:58 2012
From: ricardo.neri at ti.com (Ricardo Neri)
Date: Wed, 8 Aug 2012 17:12:58 -0500
Subject: [alsa-devel] [PATCH 07/11] ASoC: omap-mcbsp: Sidetone: Use SIDLE
 bits in SYSCONFIG register to select noidle mode
In-Reply-To: <1344417101-5015-8-git-send-email-peter.ujfalusi@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-8-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <5022E46A.4010909@ti.com>

On 08/08/2012 04:11 AM, Peter Ujfalusi wrote:
> Instead of the callback (which modifies control module register) use the
> McBSP module's SYSCONFIG register to disable smart-idle mode when the
> sidetone is enabled.
> Store the original SIDLEMODE configuration and restore it when the sidetone
> has been disabled.

Is this another case in which it is required to change the idle-mode on 
a per-use-case basis? In the past I was trying to do the same with HDMI 
[1]. In that case it was decided to add the HWMOD_SWSUP_SIDLE to hwmod 
data with the drawback of using no-idle/force-idle rather than 
smart-idle[2][3].

[1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg60226.html
[2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70463.html
[3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70653.html
>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> ---
>   sound/soc/omap/mcbsp.c |   18 ++++++++++++++----
>   sound/soc/omap/mcbsp.h |    1 +
>   2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
> index c870023..e008898 100644
> --- a/sound/soc/omap/mcbsp.c
> +++ b/sound/soc/omap/mcbsp.c
> @@ -257,8 +257,15 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
>   {
>   	unsigned int w;
>
> -	if (mcbsp->pdata->enable_st_clock)
> -		mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
> +	/*
> +	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
> +	 * are enabled or sidetones start sounding ugly.
> +	 */
> +	w = MCBSP_READ(mcbsp, SYSCON);
> +	mcbsp->st_data->mcbsp_sidle = (w >> 3) & 0x3;
> +	w &= ~SIDLEMODE(0x3);
> +	w |= SIDLEMODE(0x1);
> +	MCBSP_WRITE(mcbsp, SYSCON, w);

Wouldn't this create a mismatch between the SYSCONFIG register and McBSP 
omap_hwmod._sysc_cache? Perhaps this could be done with a future 
omap_hwmod API?

Ricardo
>
>   	/* Enable McBSP Sidetone */
>   	w = MCBSP_READ(mcbsp, SSELCR);
> @@ -279,8 +286,11 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
>   	w = MCBSP_READ(mcbsp, SSELCR);
>   	MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
>
> -	if (mcbsp->pdata->enable_st_clock)
> -		mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
> +	/* Restore the SIDLEMODE as it was before the ST has been started */
> +	w = MCBSP_READ(mcbsp, SYSCON);
> +	w &= ~SIDLEMODE(0x3);
> +	w |= SIDLEMODE(mcbsp->st_data->mcbsp_sidle);
> +	MCBSP_WRITE(mcbsp, SYSCON, w);
>   }
>
>   static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
> diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
> index 49a6725..ba82846 100644
> --- a/sound/soc/omap/mcbsp.h
> +++ b/sound/soc/omap/mcbsp.h
> @@ -280,6 +280,7 @@ struct omap_mcbsp_st_data {
>   	int nr_taps;	/* Number of filter coefficients in use */
>   	s16 ch0gain;
>   	s16 ch1gain;
> +	unsigned int mcbsp_sidle;
>   };
>
>   struct omap_mcbsp {
>



From swarren at wwwdotorg.org  Wed Aug  8 18:44:16 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 08 Aug 2012 16:44:16 -0600
Subject: [PATCH] ARM: tegra: more regulator fixes for Harmony
In-Reply-To: <1344037521-6157-1-git-send-email-swarren@wwwdotorg.org>
References: <1344037521-6157-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <5022EBC0.5060102@wwwdotorg.org>

On 08/03/2012 05:45 PM, Stephen Warren wrote:
> Commit 3d55c29 "ARM: tegra: harmony: add regulator supply name and its
> input supply" was supposed to fix all the problems with regulators on
> Harmony. However, it appears that I only tested it when booting using
> board files, not when booting using device tree. This change fixes two
> problems with regulators when booting using device tree:
> 
> 1) That patch only created the vdd_sys regulator when booting using a
>    board file. Since this is the root of the whole regulator tree, this
>    caused no regulators to successfully initialize when booting using
>    device tree. The registration of vdd_sys is moved to fix this.
> 
> 2) When booting use DT, the regulator core sets has_full_constraints,
>    which in turn causes the core to turn off any regulators not marked
>    as always on. Some of the affected regulators are required for basic
>    system operation. To solve this, add always on constraints to all
>    relevant regulators. This doesn't affect booting using a board file
>    since nothing sets has_full_constraints in that case.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> This is a fix for v3.6.

Arnd, Olof, I don't see this in the arm-soc fixes tree, although do see
you've applied a bunch of patches since I posted this. Did it drop
through the cracks?


From linux at prisktech.co.nz  Wed Aug  8 19:06:26 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 09 Aug 2012 11:06:26 +1200
Subject: Platform data from devicetree
Message-ID: <1344467186.6707.6.camel@gitbox>

Quick question regarding platform_devices created from devicetree.

At the moment, we do a of_match_device() against vt8500_gpio_dt_ids[] to
get an of_device_id that contains the .data field to pass into the
driver.

Given that pdev is created from a match against vt8500_gpio_dt_ids[] as
well, why does pdev->dev.of_node.data == NULL? Is this data not
populated into this field? What data can be passed into this field?

Regards

Tony Prisk


Example code below:

static struct of_device_id vt8500_gpio_dt_ids[] = {
	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
	{ /* Sentinel */ },
};

static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
{
	void __iomem *gpio_base;
	struct device_node *np;
	const struct of_device_id *of_id =
			of_match_device(vt8500_gpio_dt_ids, &pdev->dev);

	if (!of_id) {
		dev_err(&pdev->dev, "Failed to find gpio controller\n");
		return -ENODEV;
	}

	np = pdev->dev.of_node;
	...
}

static struct platform_driver vt8500_gpio_driver = {
	.probe		= vt8500_gpio_probe,
	.driver		= {
		.name	= "vt8500-gpio",
		.owner	= THIS_MODULE,
		.of_match_table = vt8500_gpio_dt_ids,
	},
};



From fernando.lugo at ti.com  Wed Aug  8 19:07:41 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Wed,  8 Aug 2012 18:07:41 -0500
Subject: [PATCH 0/3] remoteproc: introduce rproc recovery
Message-ID: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>

These set of patches make possible the remoteproc recover after a crash.
This is a hard recovery, that means the remoteproc is reset and it will
start from the beginning. When a crash happen all the virtio devices are
destroyed. Therefore, both rpmsg drivers and devices are gracefully
removed which also cause rproc users become 0 and the remoteproc is turned
off. After the virtio devices are destroyed the crash handler function
will read the virtio information from the firmware in order to recreate
the virtio devices that will boot the remoteproc and everything will be
functional again.

Fernando Guzman Lugo (3):
  remoteproc: add rproc_report_crash function to notify rproc crashes
  remoteproc: recover a remoteproc when it has crashed
  remoteproc: create debugfs entry to disable/enable recovery
    dynamically

 Documentation/remoteproc.txt             |    7 ++
 drivers/remoteproc/remoteproc_core.c     |  107 ++++++++++++++++++++++++++++--
 drivers/remoteproc/remoteproc_debugfs.c  |   83 +++++++++++++++++++++++
 drivers/remoteproc/remoteproc_internal.h |    1 +
 include/linux/remoteproc.h               |   20 ++++++
 5 files changed, 211 insertions(+), 7 deletions(-)



From fernando.lugo at ti.com  Wed Aug  8 19:07:42 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Wed,  8 Aug 2012 18:07:42 -0500
Subject: [PATCH 1/3] remoteproc: add rproc_report_crash function to notify
 rproc crashes
In-Reply-To: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
References: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1344467264-5128-2-git-send-email-fernando.lugo@ti.com>

This patch is exporting the rproc_report_crash function which can be used
to report a rproc crash to the remoteproc core. This function is specially
thought to be called by low-level remoteproc driver code in case of
detecting a crash (remoteproc is not functional anymore). Using this
function from another driver (non rproc driver) should be analyzed very
carefully most of the time that will be considered wrong.

rproc_report_crash function can be called from any context, that means,
it can be called from atomic context without any problem. The reporter
function is creating a new thread (workqueue work) in charge of handling
the crash (if possible).

Creating this new thread is done for two main reasons. First reason is
to be able to call it from atomic context, due to the fact that many
crashes trigger an interrupt, so this function can be called directly
from ISR context. Second reason is avoid any deadlock condition which
could happen if the rproc_report_crash function is called from a
function which is indirectly holding a rproc lock.

The reporter function is scheduling the crash handler task. This task
is thought to have some features like:

-remoteproc register dump
-remoteproc stack dump
-remoteproc core dump
-Saving of the remoteproc traces in order to be visible after the crash
-Reseting the remoteproc in order to make it functional again (hard recovery)

Right now, it is only printing the crash type which was detected. The
types of crashes are represented by an enum. I have only added mmufault
crash type. Remoteproc low-level drivers can add more types when needed.

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 Documentation/remoteproc.txt         |    7 +++
 drivers/remoteproc/remoteproc_core.c |   80 +++++++++++++++++++++++++++++++---
 include/linux/remoteproc.h           |   18 ++++++++
 3 files changed, 98 insertions(+), 7 deletions(-)

diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt
index 23a09b8..e6469fd 100644
--- a/Documentation/remoteproc.txt
+++ b/Documentation/remoteproc.txt
@@ -129,6 +129,13 @@ int dummy_rproc_example(struct rproc *my_rproc)
 
       Returns 0 on success and -EINVAL if @rproc isn't valid.
 
+  void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type)
+    - Report a crash in a remoteproc
+      This function must be called every time a crash is detected by the
+      platform specific rproc implementation. This should not be called from a
+      non-remoteproc driver. This function can be called from atomic/interrupt
+      context.
+
 5. Implementation callbacks
 
 These callbacks should be provided by platform-specific remoteproc
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index d5c2dbf..3a6f1a1 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -50,6 +50,18 @@ typedef int (*rproc_handle_resource_t)(struct rproc *rproc, void *, int avail);
 /* Unique indices for remoteproc devices */
 static DEFINE_IDA(rproc_dev_index);
 
+static const char * const rproc_crash_names[] = {
+	[RPROC_MMUFAULT]	= "mmufault",
+};
+
+/* translate rproc_crash_type to string */
+static const char *rproc_crash_to_string(enum rproc_crash_type type)
+{
+	if (type < ARRAY_SIZE(rproc_crash_names))
+		return rproc_crash_names[type];
+	return "unkown";
+}
+
 /*
  * This is the IOMMU fault handler we register with the IOMMU API
  * (when relevant; not all remote processors access memory through
@@ -57,19 +69,17 @@ static DEFINE_IDA(rproc_dev_index);
  *
  * IOMMU core will invoke this handler whenever the remote processor
  * will try to access an unmapped device address.
- *
- * Currently this is mostly a stub, but it will be later used to trigger
- * the recovery of the remote processor.
  */
 static int rproc_iommu_fault(struct iommu_domain *domain, struct device *dev,
 		unsigned long iova, int flags, void *token)
 {
+	struct rproc *rproc = token;
+
 	dev_err(dev, "iommu fault: da 0x%lx flags 0x%x\n", iova, flags);
 
-	/*
-	 * Let the iommu core know we're not really handling this fault;
-	 * we just plan to use this as a recovery trigger.
-	 */
+	rproc_report_crash(rproc, RPROC_MMUFAULT);
+
+	/* Let the iommu core know we're not really handling this fault; */
 	return -ENOSYS;
 }
 
@@ -872,6 +882,34 @@ out:
 }
 
 /**
+ * rproc_crash_handler_work() - handle a crash
+ *
+ * This function needs to handle everything related to a crash, like cpu
+ * registers and stack dump, information to help to debug the fatal error, etc.
+ */
+static void rproc_crash_handler_work(struct work_struct *work)
+{
+	struct rproc *rproc = container_of(work, struct rproc, crash_handler);
+	struct device *dev = &rproc->dev;
+
+	dev_dbg(dev, "enter %s\n", __func__);
+
+	mutex_lock(&rproc->lock);
+	if (rproc->state == RPROC_CRASHED || rproc->state == RPROC_OFFLINE) {
+		/* handle only the first crash detected */
+		mutex_unlock(&rproc->lock);
+		return;
+	}
+
+	rproc->state = RPROC_CRASHED;
+	dev_err(&rproc->dev, "handling crash #%u in %s\n",
+		++rproc->crash_cnt, rproc->name);
+	mutex_unlock(&rproc->lock);
+
+	/* TODO: handle crash */
+}
+
+/**
  * rproc_boot() - boot a remote processor
  * @rproc: handle of a remote processor
  *
@@ -1165,6 +1203,8 @@ struct rproc *rproc_alloc(struct device *dev, const char *name,
 	INIT_LIST_HEAD(&rproc->traces);
 	INIT_LIST_HEAD(&rproc->rvdevs);
 
+	INIT_WORK(&rproc->crash_handler, rproc_crash_handler_work);
+
 	rproc->state = RPROC_OFFLINE;
 
 	return rproc;
@@ -1221,6 +1261,32 @@ int rproc_del(struct rproc *rproc)
 }
 EXPORT_SYMBOL(rproc_del);
 
+/**
+ * rproc_report_crash() - rproc crash reporter function
+ * @rproc: remote processor
+ * @type: crash type
+ *
+ * This function must be called every time a crash is detected by the low-level
+ * drivers implementing a specific remoteproc. This should not be called from a
+ * non-remoteproc driver.
+ *
+ * This function can be called from atomic/interrupt context.
+ */
+void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type)
+{
+	if (!rproc) {
+		pr_err("NULL rproc pointer\n");
+		return;
+	}
+
+	dev_err(&rproc->dev, "crash detected in %s: type %s\n",
+		rproc->name, rproc_crash_to_string(type));
+
+	/* create a new task to handle the error */
+	schedule_work(&rproc->crash_handler);
+}
+EXPORT_SYMBOL(rproc_report_crash);
+
 static int __init remoteproc_init(void)
 {
 	rproc_init_debugfs();
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 131b539..a46ed27 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -361,6 +361,19 @@ enum rproc_state {
 };
 
 /**
+ * enum rproc_crash_type - remote processor crash types
+ * @RPROC_MMUFAULT:	iommu fault
+ *
+ * Each element of the enum is used as an array index. So that, the value of
+ * the elements should be always something sane.
+ *
+ * Feel free to add more types when needed.
+ */
+enum rproc_crash_type {
+	RPROC_MMUFAULT,
+};
+
+/**
  * struct rproc - represents a physical remote processor device
  * @node: klist node of this rproc object
  * @domain: iommu domain
@@ -383,6 +396,8 @@ enum rproc_state {
  * @rvdevs: list of remote virtio devices
  * @notifyids: idr for dynamically assigning rproc-wide unique notify ids
  * @index: index of this rproc device
+ * @crash_handler: workqueue for handling a crash
+ * @crash_cnt: crash counter
  */
 struct rproc {
 	struct klist_node node;
@@ -406,6 +421,8 @@ struct rproc {
 	struct list_head rvdevs;
 	struct idr notifyids;
 	int index;
+	struct work_struct crash_handler;
+	unsigned crash_cnt;
 };
 
 /* we currently support only two vrings per rvdev */
@@ -460,6 +477,7 @@ int rproc_del(struct rproc *rproc);
 
 int rproc_boot(struct rproc *rproc);
 void rproc_shutdown(struct rproc *rproc);
+void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type);
 
 static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
 {
-- 
1.7.1



From fernando.lugo at ti.com  Wed Aug  8 19:07:43 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Wed,  8 Aug 2012 18:07:43 -0500
Subject: [PATCH 2/3] remoteproc: recover a remoteproc when it has crashed
In-Reply-To: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
References: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1344467264-5128-3-git-send-email-fernando.lugo@ti.com>

This patch is introducing rproc_trigger_recover function which is in
charge of recovering the rproc. One way to recover the rproc after a crash
is resetting all its virtio devices. Doing that, all rpmsg drivers are
restored along with the rpmsg devices and that also causes the reset of
the remoteproc making the rpmsg communication with the remoteproc
functional again. So far, rproc_trigger_recover function is only resetting
all virtio devices, if in the future other rproc features are introduced
and need to be reset too, rproc_trigger_recover function should take care
of that.

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 drivers/remoteproc/remoteproc_core.c     |   28 +++++++++++++++++++++++++++-
 drivers/remoteproc/remoteproc_internal.h |    1 +
 2 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 3a6f1a1..c879069 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -882,6 +882,32 @@ out:
 }
 
 /**
+ * rproc_trigger_recover() - recover a remoteproc
+ * @rproc: the remote processor
+ *
+ * The recovery is done by reseting all the virtio devices, that way all the
+ * rpmsg drivers will be reseted along with the remote processor making the
+ * remoteproc functional again.
+ *
+ * This function can sleep, so that it cannot be called from atomic context.
+ */
+int rproc_trigger_recover(struct rproc *rproc)
+{
+	struct rproc_vdev *rvdev, *rvtmp;
+
+	dev_err(&rproc->dev, "recovering %s\n", rproc->name);
+
+	/* clean up remote vdev entries */
+	list_for_each_entry_safe(rvdev, rvtmp, &rproc->rvdevs, node)
+		rproc_remove_virtio_dev(rvdev);
+
+	/* run rproc_fw_config_virtio to create vdevs again */
+	return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+			rproc->firmware, &rproc->dev, GFP_KERNEL,
+			rproc, rproc_fw_config_virtio);
+}
+
+/**
  * rproc_crash_handler_work() - handle a crash
  *
  * This function needs to handle everything related to a crash, like cpu
@@ -906,7 +932,7 @@ static void rproc_crash_handler_work(struct work_struct *work)
 		++rproc->crash_cnt, rproc->name);
 	mutex_unlock(&rproc->lock);
 
-	/* TODO: handle crash */
+	rproc_trigger_recover(rproc);
 }
 
 /**
diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h
index a690ebe..d9c0730 100644
--- a/drivers/remoteproc/remoteproc_internal.h
+++ b/drivers/remoteproc/remoteproc_internal.h
@@ -63,6 +63,7 @@ void rproc_free_vring(struct rproc_vring *rvring);
 int rproc_alloc_vring(struct rproc_vdev *rvdev, int i);
 
 void *rproc_da_to_va(struct rproc *rproc, u64 da, int len);
+int rproc_trigger_recover(struct rproc *rproc);
 
 static inline
 int rproc_fw_sanity_check(struct rproc *rproc, const struct firmware *fw)
-- 
1.7.1



From fernando.lugo at ti.com  Wed Aug  8 19:07:44 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Wed,  8 Aug 2012 18:07:44 -0500
Subject: [PATCH 3/3] remoteproc: create debugfs entry to disable/enable
 recovery dynamically
In-Reply-To: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
References: <1344467264-5128-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1344467264-5128-4-git-send-email-fernando.lugo@ti.com>

Add a debugfs entry (named recovery) so that recovery can be disabled
dynamically at runtime. This entry is very useful when you are trying to
debug a rproc crash. Without this a recovery will take place making
impossible to debug the issue.

Original idea from Ohad Ben-Cohen and contributions from
Subramaniam Chanderashekarapuram

Example:
-disabling recovery:
$ echo disabled > <debugfs>/remoteproc/remoteproc0/recovery

-enabling recovery:
$ echo enabled > <debugfs>/remoteproc/remoteproc0/recovery

-in case you have disabled recovery and you want to continue
 debugging you can recover the remoteproc once using recover.
 This will not change the state of the recovery entry, it will
 only recovery the rproc if its state is RPROC_CRASHED
$ echo recover > <debugfs>/remoteproc/remoteproc0/recovery

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 drivers/remoteproc/remoteproc_core.c    |    3 +-
 drivers/remoteproc/remoteproc_debugfs.c |   83 +++++++++++++++++++++++++++++++
 include/linux/remoteproc.h              |    2 +
 3 files changed, 87 insertions(+), 1 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index c879069..0b52169 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -932,7 +932,8 @@ static void rproc_crash_handler_work(struct work_struct *work)
 		++rproc->crash_cnt, rproc->name);
 	mutex_unlock(&rproc->lock);
 
-	rproc_trigger_recover(rproc);
+	if (!rproc->recovery_disabled)
+		rproc_trigger_recover(rproc);
 }
 
 /**
diff --git a/drivers/remoteproc/remoteproc_debugfs.c b/drivers/remoteproc/remoteproc_debugfs.c
index 0383385..aa95cde 100644
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -28,6 +28,9 @@
 #include <linux/debugfs.h>
 #include <linux/remoteproc.h>
 #include <linux/device.h>
+#include <linux/uaccess.h>
+
+#include "remoteproc_internal.h"
 
 /* remoteproc debugfs parent dir */
 static struct dentry *rproc_dbg;
@@ -111,6 +114,84 @@ static const struct file_operations rproc_name_ops = {
 	.llseek	= generic_file_llseek,
 };
 
+/* expose recovery flag via debugfs */
+static ssize_t rproc_recovery_read(struct file *filp, char __user *userbuf,
+		size_t count, loff_t *ppos)
+{
+	struct rproc *rproc = filp->private_data;
+	char *buf = rproc->recovery_disabled ? "disabled\n" : "enabled\n";
+
+	return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
+}
+
+
+/*
+ * Writing to the recovey debugfs entry we can change the behavior of the
+ * recovery dynamically. The default value of this entry is "enabled".
+ *
+ * There are 3 possible options you can write to the recovery debug entry:
+ * "enabled", "disabled" and "recover"
+ *
+ * enabled:	In this case recovery will be enabled, every time there is a
+ *		rproc crashed the rproc will be recovered. If recovery has been
+ *		disabled and it crashed and you enable recovery it will be
+ *		recover as soon as you enable recovery.
+ * disabled:	In this case recovery will be disabled, that means if a rproc
+ *		crashes it will remain in crashed state. Therefore the rproc
+ *		won't be functional any more. But this option is used for
+ *		debugging purposes. Otherwise, debugging a crash would not be
+ *		possible.
+ * recover:	This function will trigger a recovery without taking care of
+ *		the recovery state (enabled/disabled) and without changing it.
+ *		This useful for the cases when you are debugging a crash and
+ *		after enabling recovery you get another crash immediately. As
+ *		the recovery state will be enabled it will recover the rproc
+ *		without let you debug the new crash. So, it is recommended to
+ *		disabled recovery, then starting debugging and use "recovery"
+ *		command while still debugging and when you are done then you
+ *		case use enabled command.
+ */
+static ssize_t rproc_recovery_write(struct file *filp,
+		const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct rproc *rproc = filp->private_data;
+	char buf[10];
+	int ret;
+
+	if (count > sizeof(buf))
+		return count;
+
+	ret = copy_from_user(buf, user_buf, count);
+	if (ret)
+		return ret;
+
+	/* remove end of line */
+	if (buf[count - 1] == '\n')
+		buf[count - 1] = '\0';
+
+	if (!strncmp(buf, "enabled", count)) {
+		rproc->recovery_disabled = false;
+		/* if rproc has crashed trigger recovery */
+		if (rproc->state == RPROC_CRASHED)
+			rproc_trigger_recover(rproc);
+	} else if (!strncmp(buf, "disabled", count)) {
+		rproc->recovery_disabled = true;
+	} else if (!strncmp(buf, "recover", count)) {
+		/* if rproc has crashed trigger recovery */
+		if (rproc->state == RPROC_CRASHED)
+			rproc_trigger_recover(rproc);
+	}
+
+	return count;
+}
+
+static const struct file_operations rproc_recovery_ops = {
+	.read = rproc_recovery_read,
+	.write = rproc_recovery_write,
+	.open = simple_open,
+	.llseek = generic_file_llseek,
+};
+
 void rproc_remove_trace_file(struct dentry *tfile)
 {
 	debugfs_remove(tfile);
@@ -154,6 +235,8 @@ void rproc_create_debug_dir(struct rproc *rproc)
 					rproc, &rproc_name_ops);
 	debugfs_create_file("state", 0400, rproc->dbg_dir,
 					rproc, &rproc_state_ops);
+	debugfs_create_file("recovery", 0400, rproc->dbg_dir,
+					rproc, &rproc_recovery_ops);
 }
 
 void __init rproc_init_debugfs(void)
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index a46ed27..1f73c75 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -398,6 +398,7 @@ enum rproc_crash_type {
  * @index: index of this rproc device
  * @crash_handler: workqueue for handling a crash
  * @crash_cnt: crash counter
+ * @recovery_disabled: flag that state if recovery was disabled
  */
 struct rproc {
 	struct klist_node node;
@@ -423,6 +424,7 @@ struct rproc {
 	int index;
 	struct work_struct crash_handler;
 	unsigned crash_cnt;
+	bool recovery_disabled;
 };
 
 /* we currently support only two vrings per rvdev */
-- 
1.7.1



From davem at davemloft.net  Wed Aug  8 19:08:50 2012
From: davem at davemloft.net (David Miller)
Date: Wed, 08 Aug 2012 16:08:50 -0700 (PDT)
Subject: [PATCH 07/11] net/stmmac: mark probe function as __devinit
In-Reply-To: <1344437248-20560-8-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-8-git-send-email-arnd@arndb.de>
Message-ID: <20120808.160850.2106318395245281875.davem@davemloft.net>

From: Arnd Bergmann <arnd at arndb.de>
Date: Wed,  8 Aug 2012 16:47:24 +0200

> Driver probe functions are generally __devinit so they will be
> discarded after initialization for non-hotplug kernels.
> This was found by a new warning after patch 6a228452d "stmmac: Add
> device-tree support" adds a new __devinit function that is called
> from stmmac_pltfr_probe.
> 
> Without this patch, building socfpga_defconfig results in:
> 
> WARNING: drivers/net/ethernet/stmicro/stmmac/stmmac.o(.text+0x5d4c): Section mismatch in reference from the function stmmac_pltfr_probe() to the function .devinit.text:stmmac_probe_config_dt()
> The function stmmac_pltfr_probe() references
> the function __devinit stmmac_probe_config_dt().
> This is often because stmmac_pltfr_probe lacks a __devinit
> annotation or the annotation of stmmac_probe_config_dt is wrong.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Stefan Roese <sr at denx.de>
> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> Cc: David S. Miller <davem at davemloft.net>
> Cc: netdev at vger.kernel.org

Applied, thanks.


From robherring2 at gmail.com  Wed Aug  8 19:23:54 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 08 Aug 2012 18:23:54 -0500
Subject: Platform data from devicetree
In-Reply-To: <1344467186.6707.6.camel@gitbox>
References: <1344467186.6707.6.camel@gitbox>
Message-ID: <5022F50A.3020105@gmail.com>

On 08/08/2012 06:06 PM, Tony Prisk wrote:
> Quick question regarding platform_devices created from devicetree.
> 
> At the moment, we do a of_match_device() against vt8500_gpio_dt_ids[] to
> get an of_device_id that contains the .data field to pass into the
> driver.
> 
> Given that pdev is created from a match against vt8500_gpio_dt_ids[] as
> well, why does pdev->dev.of_node.data == NULL? Is this data not
> populated into this field? What data can be passed into this field?
> 

This commit may be why:

commit b1608d69cb804e414d0887140ba08a9398e4e638
Author: Grant Likely <grant.likely at secretlab.ca>
Date:   Wed May 18 11:19:24 2011 -0600

    drivercore: revert addition of of_match to struct device

    Commit b826291c, "drivercore/dt: add a match table pointer to struct
    device" added an of_match pointer to struct device to cache the
    of_match_table entry discovered at driver match time.  This was unsafe
    because matching is not an atomic operation with probing a driver.  If
    two or more drivers are attempted to be matched to a driver at the
    same time, then the cached matching entry pointer could get
    overwritten.

    This patch reverts the of_match cache pointer and reworks all users to
    call of_match_device() directly instead.

    Signed-off-by: Grant Likely <grant.likely at secretlab.ca>



> Regards
> 
> Tony Prisk
> 
> 
> Example code below:
> 
> static struct of_device_id vt8500_gpio_dt_ids[] = {
> 	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
> 	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
> 	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
> 	{ /* Sentinel */ },
> };
> 
> static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
> {
> 	void __iomem *gpio_base;
> 	struct device_node *np;
> 	const struct of_device_id *of_id =
> 			of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
> 
> 	if (!of_id) {
> 		dev_err(&pdev->dev, "Failed to find gpio controller\n");
> 		return -ENODEV;
> 	}
> 
> 	np = pdev->dev.of_node;
> 	...
> }
> 
> static struct platform_driver vt8500_gpio_driver = {
> 	.probe		= vt8500_gpio_probe,
> 	.driver		= {
> 		.name	= "vt8500-gpio",
> 		.owner	= THIS_MODULE,
> 		.of_match_table = vt8500_gpio_dt_ids,
> 	},
> };
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From linux at prisktech.co.nz  Wed Aug  8 20:35:11 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 09 Aug 2012 12:35:11 +1200
Subject: Platform data from devicetree
In-Reply-To: <5022F50A.3020105@gmail.com>
References: <1344467186.6707.6.camel@gitbox> <5022F50A.3020105@gmail.com>
Message-ID: <1344472511.23813.1.camel@gitbox>

On Wed, 2012-08-08 at 18:23 -0500, Rob Herring wrote:
> On 08/08/2012 06:06 PM, Tony Prisk wrote:
> > Quick question regarding platform_devices created from devicetree.
> > 
> > At the moment, we do a of_match_device() against vt8500_gpio_dt_ids[] to
> > get an of_device_id that contains the .data field to pass into the
> > driver.
> > 
> > Given that pdev is created from a match against vt8500_gpio_dt_ids[] as
> > well, why does pdev->dev.of_node.data == NULL? Is this data not
> > populated into this field? What data can be passed into this field?
> > 
> 
> This commit may be why:
> 
> commit b1608d69cb804e414d0887140ba08a9398e4e638
> Author: Grant Likely <grant.likely at secretlab.ca>
> Date:   Wed May 18 11:19:24 2011 -0600
> 
>     drivercore: revert addition of of_match to struct device
> 
>     Commit b826291c, "drivercore/dt: add a match table pointer to struct
>     device" added an of_match pointer to struct device to cache the
>     of_match_table entry discovered at driver match time.  This was unsafe
>     because matching is not an atomic operation with probing a driver.  If
>     two or more drivers are attempted to be matched to a driver at the
>     same time, then the cached matching entry pointer could get
>     overwritten.
> 
>     This patch reverts the of_match cache pointer and reworks all users to
>     call of_match_device() directly instead.
> 
>     Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
> 
> 
> 
> > Regards
> > 
> > Tony Prisk
> > 
> > 
> > Example code below:
> > 
> > static struct of_device_id vt8500_gpio_dt_ids[] = {
> > 	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
> > 	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
> > 	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
> > 	{ /* Sentinel */ },
> > };
> > 
> > static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
> > {
> > 	void __iomem *gpio_base;
> > 	struct device_node *np;
> > 	const struct of_device_id *of_id =
> > 			of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
> > 
> > 	if (!of_id) {
> > 		dev_err(&pdev->dev, "Failed to find gpio controller\n");
> > 		return -ENODEV;
> > 	}
> > 
> > 	np = pdev->dev.of_node;
> > 	...
> > }
> > 
> > static struct platform_driver vt8500_gpio_driver = {
> > 	.probe		= vt8500_gpio_probe,
> > 	.driver		= {
> > 		.name	= "vt8500-gpio",
> > 		.owner	= THIS_MODULE,
> > 		.of_match_table = vt8500_gpio_dt_ids,
> > 	},
> > };
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 

Thanks Rob.

Thought I was doing something wrong because it seemed like it should
work.



From linux at prisktech.co.nz  Wed Aug  8 21:54:52 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:52 +1200
Subject: [PATCHv2 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
Message-ID: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>

This patchset updates arch-vt8500 to devicetree and removes all the old-style
code. Support for WM8650 has also been added.

Example dts/dtsi files are given for the three currently supported models.

Major changes:

GPIO code has been converted to a platform_device and rewritten as WM8505
support was broken. Add support for WM8650 gpio controller.

UHCI support was missing. Added this as a generic non-pci uhci controller as
it doesn't require anything special. Should be usable by any system that doesn't
have special requirements to get the UHCI controller working.

Framebuffer code patched to support WM8650. The bindings for this are of concern
but there doesn't seem to be a formalized binding yet. This patch is based off
Sascha Hauer's current patch on the dri-devel mailing list and should be easily
patched out when its finalized.

Patchset based on Arnd's arm-soc/for-next branch.


Could I get this reviewed, hopefully for inclusion into v3.7.

Regards
Tony Prisk

Changes
v2:
Cleanup style/formatting errors
Removed erroneous commit message about GPIO not being converted to devicetree
Corrected arch-vt8500/irq.c header to correct filename
Changed GPIO driver to use module_platform_driver()
Renamed vt8500_gpio_bank_regs -> vt8500_gpio_bank_regoffsets
Changed vt8500_gpio_bank_regoffset fields to unsigned int
Changed bit-setting code to use BIT() macro
Removed of_find_compatible() and use pdev->dev.of_node in _probe()
Removed regoff field and related code - leftover from old design
Added kerneldoc regarding struct vt8500_gpio_bank_regoffsets fields
Update MODULE_LICENSE on all platform devices to "GPL v2" to match their headers
Renamed dts board files to clarify product names

Tony Prisk (8):
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  rtc: vt8500: Add devicetree support for vt8500-rtc
  serial: vt8500: Add devicetree support for vt8500-serial
  usb: vt8500: Add devicetree support for vt8500-ehci and -uhci.
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  ARM: vt8500: gpio: Devicetree support for arch-vt8500

 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 +
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 ++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 +
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   46 +++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 +
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   20 ++
 arch/arm/Kconfig                                   |    2 +
 arch/arm/boot/dts/vt8500.dtsi                      |   99 ++++++
 arch/arm/boot/dts/vt8500_ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8505.dtsi                      |  125 ++++++++
 arch/arm/boot/dts/wm8505_ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8650.dtsi                      |   95 ++++++
 arch/arm/boot/dts/wm8650_ref.dts                   |   31 ++
 arch/arm/mach-vt8500/Kconfig                       |   72 +----
 arch/arm/mach-vt8500/Makefile                      |    9 +-
 arch/arm/mach-vt8500/bv07.c                        |   80 -----
 arch/arm/mach-vt8500/common.h                      |   25 ++
 arch/arm/mach-vt8500/devices-vt8500.c              |   91 ------
 arch/arm/mach-vt8500/devices-wm8505.c              |   99 ------
 arch/arm/mach-vt8500/devices.c                     |  270 -----------------
 arch/arm/mach-vt8500/devices.h                     |   88 ------
 arch/arm/mach-vt8500/gpio.c                        |  240 ---------------
 arch/arm/mach-vt8500/include/mach/restart.h        |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h    |   88 ------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h    |   79 -----
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h    |  115 -------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h    |   78 -----
 arch/arm/mach-vt8500/irq.c                         |  160 +++++-----
 arch/arm/mach-vt8500/restart.c                     |   54 ----
 arch/arm/mach-vt8500/timer.c                       |   56 +++-
 arch/arm/mach-vt8500/vt8500.c                      |  192 ++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c                  |   79 -----
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-vt8500.c                         |  318 ++++++++++++++++++++
 drivers/rtc/rtc-vt8500.c                           |    7 +
 drivers/tty/serial/vt8500_serial.c                 |    7 +
 drivers/usb/host/Kconfig                           |    4 +-
 drivers/usb/host/ehci-vt8500.c                     |   24 +-
 drivers/usb/host/uhci-hcd.c                        |    5 +
 drivers/usb/host/uhci-platform.c                   |  166 ++++++++++
 drivers/video/Kconfig                              |    6 +-
 drivers/video/vt8500lcdfb.c                        |   77 ++++-
 drivers/video/wm8505fb.c                           |   95 +++++-
 drivers/video/wmt_ge_rops.c                        |    7 +
 52 files changed, 1674 insertions(+), 1566 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/vt8500_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505_ref.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650_ref.dts
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c
 create mode 100644 drivers/gpio/gpio-vt8500.c
 create mode 100644 drivers/usb/host/uhci-platform.c

-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:55 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:55 +1200
Subject: [PATCHv2 3/8] serial: vt8500: Add devicetree support for vt8500-serial
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-4-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/tty/serial/vt8500_serial.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006f..dee6715 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -603,12 +604,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-uart", },
+	{}
+};
+
 static struct platform_driver vt8500_platform_driver = {
 	.probe  = vt8500_serial_probe,
 	.remove = __devexit_p(vt8500_serial_remove),
 	.driver = {
 		.name = "vt8500_serial",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -642,4 +649,4 @@ module_exit(vt8500_serial_exit);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("Driver for vt8500 serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:54 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:54 +1200
Subject: [PATCHv2 2/8] rtc: vt8500: Add devicetree support for vt8500-rtc
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-3-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/rtc/rtc-vt8500.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-vt8500.c b/drivers/rtc/rtc-vt8500.c
index 9e94fb1..07bf193 100644
--- a/drivers/rtc/rtc-vt8500.c
+++ b/drivers/rtc/rtc-vt8500.c
@@ -23,6 +23,7 @@
 #include <linux/bcd.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 /*
  * Register definitions
@@ -302,12 +303,18 @@ static int __devexit vt8500_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-rtc", },
+	{}
+};
+
 static struct platform_driver vt8500_rtc_driver = {
 	.probe		= vt8500_rtc_probe,
 	.remove		= __devexit_p(vt8500_rtc_remove),
 	.driver		= {
 		.name	= "vt8500-rtc",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -315,5 +322,5 @@ module_platform_driver(vt8500_rtc_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:vt8500-rtc");
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:53 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:53 +1200
Subject: [PATCHv2 1/8] arm: vt8500: Add device tree files for VIA/Wondermedia
 SoC's
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-2-git-send-email-linux@prisktech.co.nz>

Add device tree files for VT8500, WM8505 and WM8650 SoC's and
reference boards.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/boot/dts/vt8500-bv07.dts |   31 +++++++++
 arch/arm/boot/dts/vt8500.dtsi     |   99 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8505-ref.dts  |   31 +++++++++
 arch/arm/boot/dts/wm8505.dtsi     |  125 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8650-mid.dts  |   31 +++++++++
 arch/arm/boot/dts/wm8650.dtsi     |   95 ++++++++++++++++++++++++++++
 6 files changed, 412 insertions(+)
 create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505-ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650-mid.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi

diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 0000000..20dda12
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,31 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+	model = "Benign BV07 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 0000000..7a2fe0e
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,99 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "via,vt8500";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc>;
+
+		intc: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "via,vt8500-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d800e400 {
+			compatible = "via,vt8500-fb";
+			reg = <0xd800e400 0x400>;
+			interrupts = <12>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 0000000..2b10282
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+	model = "Wondermedia WM8505 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <32>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 0000000..76dbfdc
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,125 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8505";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8505-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007100 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007100 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007300 {
+			compatible = "platform-uhci";
+			reg = <0xd8007300 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		uart at d8370000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8370000 0x1040>;
+			interrupts = <31>;
+		};
+
+		uart at d8380000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8380000 0x1040>;
+			interrupts = <30>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 0000000..8e0119e
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+	model = "Wondermedia WM8650-MID Tablet";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 0000000..fab4ead
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,95 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8650";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8650-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:56 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:56 +1200
Subject: [PATCHv2 4/8] usb: vt8500: Add devicetree support for vt8500-ehci and
 -uhci.
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-5-git-send-email-linux@prisktech.co.nz>

Add devicetree support for vt8500-ehci.
Convert vt8500-uhci to a generic non-pci platform-uhci with
device tree support.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/usb/host/Kconfig         |    4 +-
 drivers/usb/host/ehci-vt8500.c   |   25 ++++--
 drivers/usb/host/uhci-hcd.c      |    5 ++
 drivers/usb/host/uhci-platform.c |  169 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 195 insertions(+), 8 deletions(-)
 create mode 100644 drivers/usb/host/uhci-platform.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index dcfaaa9..d7a6b10 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -450,7 +450,7 @@ config USB_OHCI_LITTLE_ENDIAN
 
 config USB_UHCI_HCD
 	tristate "UHCI HCD (most Intel and VIA) support"
-	depends on USB && (PCI || SPARC_LEON)
+	depends on USB && (PCI || SPARC_LEON || ARCH_VT8500)
 	---help---
 	  The Universal Host Controller Interface is a standard by Intel for
 	  accessing the USB hardware in the PC (which is also called the USB
@@ -468,7 +468,7 @@ config USB_UHCI_HCD
 config USB_UHCI_SUPPORT_NON_PCI_HC
 	bool
 	depends on USB_UHCI_HCD
-	default y if SPARC_LEON
+	default y if (SPARC_LEON  || ARCH_VT8500)
 
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c
index c1eda73..0e1637b 100644
--- a/drivers/usb/host/ehci-vt8500.c
+++ b/drivers/usb/host/ehci-vt8500.c
@@ -16,6 +16,7 @@
  *
  */
 
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
@@ -84,20 +85,23 @@ static const struct hc_driver vt8500_ehci_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static u64 wmt_ehci_dma_mask = DMA_BIT_MASK(32);
+
 static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
+	int irq;
 	int ret;
 
 	if (usb_disabled())
 		return -ENODEV;
 
-	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
-		pr_debug("resource[1] is not IORESOURCE_IRQ");
-		return -ENOMEM;
-	}
+	/* devicetree created devices don't specify a dma mask */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &wmt_ehci_dma_mask;
+
 	hcd = usb_create_hcd(&vt8500_ehci_hc_driver, &pdev->dev, "VT8500");
 	if (!hcd)
 		return -ENOMEM;
@@ -134,8 +138,9 @@ static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 
 	ehci_reset(ehci);
 
-	ret = usb_add_hcd(hcd, pdev->resource[1].start,
-			  IRQF_SHARED);
+	irq = platform_get_irq(pdev, 0);
+
+	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret == 0) {
 		platform_set_drvdata(pdev, hcd);
 		return ret;
@@ -162,6 +167,11 @@ static int vt8500_ehci_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id vt8500_ehci_ids[] = {
+	{ .compatible = "via,vt8500-ehci", },
+	{}
+};
+
 static struct platform_driver vt8500_ehci_driver = {
 	.probe		= vt8500_ehci_drv_probe,
 	.remove		= vt8500_ehci_drv_remove,
@@ -169,7 +179,10 @@ static struct platform_driver vt8500_ehci_driver = {
 	.driver = {
 		.name	= "vt8500-ehci",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(vt8500_ehci_ids),
 	}
 };
 
 MODULE_ALIAS("platform:vt8500-ehci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index e4db350..5da5c99 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -846,6 +846,11 @@ static const char hcd_name[] = "uhci_hcd";
 #define PLATFORM_DRIVER		uhci_grlib_driver
 #endif
 
+#ifdef CONFIG_ARCH_VT8500
+#include "uhci-platform.c"
+#define PLATFORM_DRIVER		uhci_platform_driver
+#endif
+
 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
 #error "missing bus glue for uhci-hcd"
 #endif
diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
new file mode 100644
index 0000000..35ca094
--- /dev/null
+++ b/drivers/usb/host/uhci-platform.c
@@ -0,0 +1,169 @@
+/*
+ * Generic UHCI HCD (Host Controller Driver) for Platform Devices
+ *
+ * Copyright (c) 2011 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This file is based on uhci-grlib.c
+ * (C) Copyright 2004-2007 Alan Stern, stern at rowland.harvard.edu
+ */
+
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static int uhci_platform_init(struct usb_hcd *hcd)
+{
+	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+	uhci->rh_numports = uhci_count_ports(hcd);
+
+	/* Set up pointers to to generic functions */
+	uhci->reset_hc = uhci_generic_reset_hc;
+	uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc;
+
+	/* No special actions need to be taken for the functions below */
+	uhci->configure_hc = NULL;
+	uhci->resume_detect_interrupts_are_broken = NULL;
+	uhci->global_suspend_mode_is_broken = NULL;
+
+	/* Reset if the controller isn't already safely quiescent. */
+	check_and_reset_hc(uhci);
+	return 0;
+}
+
+static const struct hc_driver uhci_platform_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "Generic UHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct uhci_hcd),
+
+	/* Generic hardware linkage */
+	.irq =                  uhci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/* Basic lifecycle operations */
+	.reset =                uhci_platform_init,
+	.start =                uhci_start,
+#ifdef CONFIG_PM
+	.pci_suspend =          NULL,
+	.pci_resume =           NULL,
+	.bus_suspend =          uhci_rh_suspend,
+	.bus_resume =           uhci_rh_resume,
+#endif
+	.stop =                 uhci_stop,
+
+	.urb_enqueue =          uhci_urb_enqueue,
+	.urb_dequeue =          uhci_urb_dequeue,
+
+	.endpoint_disable =     uhci_hcd_endpoint_disable,
+	.get_frame_number =     uhci_hcd_get_frame_number,
+
+	.hub_status_data =      uhci_hub_status_data,
+	.hub_control =          uhci_hub_control,
+};
+
+static u64 platform_uhci_dma_mask = DMA_BIT_MASK(32);
+
+static int __devinit uhci_hcd_platform_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd;
+	struct uhci_hcd *uhci;
+	struct resource *res;
+	int ret;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &platform_uhci_dma_mask;
+
+	hcd = usb_create_hcd(&uhci_platform_hc_driver, &pdev->dev,
+				pdev->name);
+	if (!hcd)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		pr_err("%s: request_mem_region failed\n", __func__);
+		ret = -EBUSY;
+		goto err_rmr;
+	}
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		pr_err("%s: ioremap failed\n", __func__);
+		ret = -ENOMEM;
+		goto err_irq;
+	}
+	uhci = hcd_to_uhci(hcd);
+
+	uhci->regs = hcd->regs;
+
+	ret = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED |
+								IRQF_SHARED);
+	if (ret)
+		goto err_uhci;
+
+	return 0;
+
+err_uhci:
+	iounmap(hcd->regs);
+err_irq:
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+	usb_put_hcd(hcd);
+
+	return ret;
+}
+
+static int uhci_hcd_platform_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more.  This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel.  Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_hcd_platform_shutdown(struct platform_device *op)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+	uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+static const struct of_device_id platform_uhci_ids[] = {
+	{ .compatible = "platform-uhci", },
+	{}
+};
+
+static struct platform_driver uhci_platform_driver = {
+	.probe          = uhci_hcd_platform_probe,
+	.remove         = uhci_hcd_platform_remove,
+	.shutdown       = uhci_hcd_platform_shutdown,
+	.driver = {
+		.name = "platform-uhci",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(platform_uhci_ids),
+	},
+};
+
+MODULE_ALIAS("platform:platform-uhci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, platform_uhci_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:57 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:57 +1200
Subject: [PATCHv2 5/8] video: vt8500: Add devicetree support for vt8500-fb and
 wm8505-fb
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-6-git-send-email-linux@prisktech.co.nz>

Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
tree bindings.
Small change in wm8505-fb.c to support WM8650 framebuffer color
format.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/Kconfig       |    6 +--
 drivers/video/vt8500lcdfb.c |   79 ++++++++++++++++++++++++++++++-----
 drivers/video/wm8505fb.c    |   97 ++++++++++++++++++++++++++++++++++++-------
 drivers/video/wmt_ge_rops.c |    9 +++-
 4 files changed, 161 insertions(+), 30 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..b66d951 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1788,7 +1788,7 @@ config FB_AU1200
 
 config FB_VT8500
 	bool "VT8500 LCD Driver"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
@@ -1797,11 +1797,11 @@ config FB_VT8500
 
 config FB_WM8505
 	bool "WM8505 frame buffer support"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
-	  This is the framebuffer driver for WonderMedia WM8505
+	  This is the framebuffer driver for WonderMedia WM8505/WM8650
 	  integrated LCD controller.
 
 source "drivers/video/geode/Kconfig"
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6e..d62234e 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -35,6 +35,13 @@
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
 
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
+#endif
+
+
 #define to_vt8500lcd_info(__info) container_of(__info, \
 						struct vt8500lcd_info, fb)
 
@@ -270,15 +277,21 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 {
 	struct vt8500lcd_info *fbi;
 	struct resource *res;
-	struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
 	void *addr;
 	int irq, ret;
 
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
+
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+			+ sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -333,9 +346,45 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
+	np = of_find_node_by_name(NULL, "display");
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.fix.smem_start	= fb_mem_phys;
+	fbi->fb.fix.smem_len	= fb_mem_len;
+	fbi->fb.screen_base	= fb_mem_virt;
 
 	fbi->palette_size	= PAGE_ALIGN(512);
 	fbi->palette_cpu	= dma_alloc_coherent(&pdev->dev,
@@ -370,10 +419,11 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_irq;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
 
 	ret = vt8500lcd_set_par(&fbi->fb);
 	if (ret) {
@@ -448,12 +498,18 @@ static int __devexit vt8500lcd_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id via_dt_ids[] = {
+	{ .compatible = "via,vt8500-fb", },
+	{}
+};
+
 static struct platform_driver vt8500lcd_driver = {
 	.probe		= vt8500lcd_probe,
 	.remove		= __devexit_p(vt8500lcd_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "vt8500-lcd",
+		.of_match_table = of_match_ptr(via_dt_ids),
 	},
 };
 
@@ -461,4 +517,5 @@ module_platform_driver(vt8500lcd_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, via_dt_ids);
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd..ed9b5eb 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/wait.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
 
 #include <mach/vt8500fb.h>
 
@@ -59,8 +62,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
 
-	/* Set in-memory picture format to RGB 32bpp */
-	writel(0x1c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
+	/*
+	 * Set in-memory picture format to RGB
+	 * 0x31C sets the correct color mode (RGB565) for WM8650
+	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
+	 */
+	writel(0x31c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
 	writel(1,		       fbi->regbase + WMT_GOVR_COLORSPACE1);
 
 	/* Virtual buffer size */
@@ -127,6 +134,18 @@ static int wm8505fb_set_par(struct fb_info *info)
 		info->var.blue.msb_right = 0;
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		info->fix.line_length = info->var.xres_virtual << 2;
+	} else if (info->var.bits_per_pixel == 16) {
+		info->var.red.offset = 11;
+		info->var.red.length = 5;
+		info->var.red.msb_right = 0;
+		info->var.green.offset = 5;
+		info->var.green.length = 6;
+		info->var.green.msb_right = 0;
+		info->var.blue.offset = 0;
+		info->var.blue.length = 5;
+		info->var.blue.msb_right = 0;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		info->fix.line_length = info->var.xres_virtual << 1;
 	}
 
 	wm8505fb_set_timing(info);
@@ -246,16 +265,20 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 	struct wm8505fb_info	*fbi;
 	struct resource		*res;
 	void			*addr;
-	struct vt8500fb_platform_data *pdata;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
 
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
+			sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -305,21 +328,58 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+	np = of_find_node_by_name(NULL, "display");
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
 
 	fbi->fb.var.nonstd		= 0;
 	fbi->fb.var.activate		= FB_ACTIVATE_NOW;
 
 	fbi->fb.var.height		= -1;
 	fbi->fb.var.width		= -1;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
-	fbi->fb.screen_size	= pdata->video_mem_len;
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
+
+	fbi->fb.fix.smem_start		= fb_mem_phys;
+	fbi->fb.fix.smem_len		= fb_mem_len;
+	fbi->fb.screen_base		= fb_mem_virt;
+	fbi->fb.screen_size		= fb_mem_len;
 
 	if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
 		dev_err(&pdev->dev, "Failed to allocate color map\n");
@@ -395,12 +455,18 @@ static int __devexit wm8505fb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,wm8505-fb", },
+	{}
+};
+
 static struct platform_driver wm8505fb_driver = {
 	.probe		= wm8505fb_probe,
 	.remove		= __devexit_p(wm8505fb_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -408,4 +474,5 @@ module_platform_driver(wm8505fb_driver);
 
 MODULE_AUTHOR("Ed Spiridonov <edo.rus at gmail.com>");
 MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 55be386..ba025b4 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -158,12 +158,18 @@ static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,prizm-ge-rops", },
+	{ /* sentinel */ }
+};
+
 static struct platform_driver wmt_ge_rops_driver = {
 	.probe		= wmt_ge_rops_probe,
 	.remove		= __devexit_p(wmt_ge_rops_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "wmt_ge_rops",
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -172,4 +178,5 @@ module_platform_driver(wmt_ge_rops_driver);
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com");
 MODULE_DESCRIPTION("Accelerators for raster operations using "
 		   "WonderMedia Graphics Engine");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:55:00 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:55:00 +1200
Subject: [PATCHv2 8/8] arm: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-9-git-send-email-linux@prisktech.co.nz>

Converted the existing arch-vt8500 gpio to a platform_device.
Added support for WM8505 and WM8650 GPIO controllers.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/gpio/Kconfig       |    6 +
 drivers/gpio/Makefile      |    1 +
 drivers/gpio/gpio-vt8500.c |  313 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 320 insertions(+)
 create mode 100644 drivers/gpio/gpio-vt8500.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 542f0c0..3c8897a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,12 @@ config GPIO_STA2X11
 	  Say yes here to support the STA2x11/ConneXt GPIO device.
 	  The GPIO module has 128 GPIO pins with alternate functions.
 
+config GPIO_VT8500
+	bool "VIA/Wondermedia SoC GPIO Support"
+	depends on ARCH_VT8500
+	help
+	  Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
 config GPIO_XILINX
 	bool "Xilinx GPIO support"
 	depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0f55662..2c014b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500)	+= gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)	+= gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
new file mode 100644
index 0000000..19b12d9
--- /dev/null
+++ b/drivers/gpio/gpio-vt8500.c
@@ -0,0 +1,313 @@
+/* linux/arch/arm/mach-vt8500/gpio.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ * Based on gpio.c:
+ * - Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+
+/*
+	We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
+	by one set of registers (although not all may be valid).
+
+	Because different SoC's have different register offsets, we pass the
+	register offsets as data in vt8500_gpio_dt_ids[].
+
+	A value of NO_REG is used to indicate that this register is not
+	supported. Only used for ->en at the moment.
+*/
+
+#define NO_REG	0xFFFF
+
+/*
+ * struct vt8500_gpio_bank_regoffsets
+ * @en: offset to enable register of the bank
+ * @dir: offset to direction register of the bank
+ * @data_out: offset to the data out register of the bank
+ * @data_in: offset to the data in register of the bank
+ * @ngpio: highest valid pin in this bank
+ */
+
+struct vt8500_gpio_bank_regoffsets {
+	unsigned int	en;
+	unsigned int	dir;
+	unsigned int	data_out;
+	unsigned int	data_in;
+	unsigned char	ngpio;
+};
+
+struct vt8500_gpio_data {
+	unsigned int				num_banks;
+	struct vt8500_gpio_bank_regoffsets	banks[];
+};
+
+#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)		\
+{								\
+	.en = __en,						\
+	.dir = __dir,						\
+	.data_out = __out,					\
+	.data_in = __in,					\
+	.ngpio = __ngpio,					\
+}
+
+static struct vt8500_gpio_data vt8500_data = {
+	.num_banks	= 7,
+	.banks	= {
+		VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
+		VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
+		VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
+		VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
+		VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
+		VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
+		VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
+	},
+};
+
+static struct vt8500_gpio_data wm8505_data = {
+	.num_banks	= 10,
+	.banks	= {
+		VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
+		VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
+		VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
+		VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
+		VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
+		VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
+		VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
+		VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
+		VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
+		VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+	},
+};
+
+/*
+ * No information about which bits are valid so we just make
+ * them all available until its figured out.
+ */
+static struct vt8500_gpio_data wm8650_data = {
+	.num_banks	= 9,
+	.banks	= {
+		VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
+		VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
+		VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
+		VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
+		VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
+		VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
+		VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
+		VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
+		VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+	},
+};
+
+struct vt8500_gpio_chip {
+	struct gpio_chip		chip;
+
+	const struct vt8500_gpio_bank_regoffsets *regs;
+	void __iomem	*base;
+};
+
+
+#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
+
+static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	unsigned val;
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return 0;
+
+	val = readl(vt8500_chip->base + vt8500_chip->regs->en);
+	val |= BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en);
+
+	return 0;
+}
+
+static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+	unsigned val;
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return;
+
+	val = readl(vt8500_chip->base + vt8500_chip->regs->en);
+	val &= ~BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en);
+}
+
+static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir);
+	val &= ~BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	return 0;
+}
+
+static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir);
+	val |= BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	if (value) {
+		val = readl(vt8500_chip->base + vt8500_chip->regs->data_out);
+		val |= BIT(offset);
+		writel(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+	}
+	return 0;
+}
+
+static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	return (readl(vt8500_chip->base + vt8500_chip->regs->data_in) >>
+								offset) & 1;
+}
+
+static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->data_out);
+	if (value)
+		val |= BIT(offset);
+	else
+		val &= ~BIT(offset);
+
+	writel(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+}
+
+static int vt8500_of_xlate(struct gpio_chip *gc,
+			    const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	/* bank if specificed in gpiospec->args[0] */
+	if (flags)
+		*flags = gpiospec->args[2];
+
+	return gpiospec->args[1];
+}
+
+static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
+				const struct vt8500_gpio_data *data)
+{
+	struct vt8500_gpio_chip *vtchip;
+	struct gpio_chip *chip;
+	int i;
+	int pin_cnt = 0;
+
+	vtchip = devm_kzalloc(&pdev->dev,
+			sizeof(struct vt8500_gpio_chip) * data->num_banks,
+			GFP_KERNEL);
+	if (!vtchip) {
+		pr_err("%s: failed to allocate chip memory\n", __func__);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < data->num_banks; i++) {
+		vtchip[i].base = base;
+		vtchip[i].regs = &data->banks[i];
+
+		chip = &vtchip[i].chip;
+
+		chip->of_xlate = vt8500_of_xlate;
+		chip->of_gpio_n_cells = 3;
+		chip->of_node = pdev->dev.of_node;
+
+		chip->request = vt8500_gpio_request;
+		chip->free = vt8500_gpio_free;
+		chip->direction_input = vt8500_gpio_direction_input;
+		chip->direction_output = vt8500_gpio_direction_output;
+		chip->get = vt8500_gpio_get_value;
+		chip->set = vt8500_gpio_set_value;
+		chip->can_sleep = 0;
+		chip->base = pin_cnt;
+		chip->ngpio = data->banks[i].ngpio;
+
+		pin_cnt += data->banks[i].ngpio;
+
+		gpiochip_add(chip);
+	}
+	return 0;
+}
+
+static struct of_device_id vt8500_gpio_dt_ids[] = {
+	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
+	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
+	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
+	{ /* Sentinel */ },
+};
+
+static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
+{
+	void __iomem *gpio_base;
+	struct device_node *np;
+	const struct of_device_id *of_id =
+				of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -ENODEV;
+	}
+
+	np = pdev->dev.of_node;
+	if (!np) {
+		dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
+		return -EFAULT;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(&pdev->dev, "Unable to map GPIO registers\n");
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+	return 0;
+}
+
+static struct platform_driver vt8500_gpio_driver = {
+	.probe		= vt8500_gpio_probe,
+	.driver		= {
+		.name	= "vt8500-gpio",
+		.owner	= THIS_MODULE,
+		.of_match_table = vt8500_gpio_dt_ids,
+	},
+};
+
+module_platform_driver(vt8500_gpio_driver);
+
+MODULE_DESCRIPTION("VT8500 GPIO Driver");
+MODULE_AUTHOR("Tony Prisk <linux at prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:59 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:59 +1200
Subject: [PATCHv2 7/8] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-8-git-send-email-linux@prisktech.co.nz>

Bindings for gpio, interrupt controller, power management controller,
timer, realtime clock, serial uart, ehci and uhci controllers and
framebuffer controllers used on the arch-vt8500 platform.

Framebuffer binding also specifies a 'display' node which is required
for determining the lcd panel data.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +++++++
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +++++++
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 ++++++
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +++++++
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 ++++++++++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +++++++
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 +++++++
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +++++++
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +++++++
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   46 ++++++++++++++++++++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 ++++++
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   20 +++++++++
 13 files changed, 224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt

diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
new file mode 100644
index 0000000..1b3b187
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the VIA VT8500 SoC shall have the following properties:
+Required root node property:
+compatible = "via,vt8500";
+
+Boards with the Wondermedia WM8505 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8505";
+
+Boards with the Wondermedia WM8650 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8650";
+
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
new file mode 100644
index 0000000..0a4ce10
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
@@ -0,0 +1,16 @@
+VIA/Wondermedia VT8500 Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-intc"
+- reg : Should contain 1 register ranges(address and length)
+- #interrupt-cells : should be <1>
+
+Example:
+
+	intc: interrupt-controller at d8140000 {
+		compatible = "via,vt8500-intc";
+		interrupt-controller;
+		reg = <0xd8140000 0x10000>;
+		#interrupt-cells = <1>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
new file mode 100644
index 0000000..521b9c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia VT8500 Power Management Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-pmc"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	pmc at d8130000 {
+		compatible = "via,vt8500-pmc";
+		reg = <0xd8130000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
new file mode 100644
index 0000000..901c73f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+	timer at d8130100 {
+		compatible = "via,vt8500-timer";
+		reg = <0xd8130100 0x28>;
+		interrupts = <36>;
+	};
diff --git a/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
new file mode 100644
index 0000000..1a122bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+	or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+	1) bank
+	2) pin number
+	3) flags
+
+Example:
+
+	gpio: gpio-controller at d8110000 {
+		compatible = "via,vt8500-gpio";
+		gpio-controller;
+		reg = <0xd8110000 0x10000>;
+		#gpio-cells = <3>;
+	};
+
+	vibrate {
+		gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+	};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 0000000..3c0484c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+	rtc at d8100000 {
+		compatible = "via,vt8500-rtc";
+		reg = <0xd8100000 0x10000>;
+		interrupts = <48>;
+	};
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
new file mode 100644
index 0000000..3222502
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 UART Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-uart"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UART interrupt
+
+Example:
+
+	uart at d8210000 {
+		compatible = "via,vt8500-uart";
+		reg = <0xd8210000 0x1040>;
+		interrupts = <47>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
new file mode 100644
index 0000000..a4fb071
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/platform-uhci.txt
@@ -0,0 +1,15 @@
+Generic Platform UHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "platform-uhci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UHCI controller interrupt
+
+Example:
+
+	uhci at d8007b00 {
+		compatible = "platform-uhci";
+		reg = <0xd8007b00 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
new file mode 100644
index 0000000..17b3ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 EHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-ehci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : ehci controller interrupt
+
+Example:
+
+	ehci at d8007900 {
+		compatible = "via,vt8500-ehci";
+		reg = <0xd8007900 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af..5c63da2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -47,5 +47,7 @@ sirf	SiRF Technology, Inc.
 st	STMicroelectronics
 stericsson	ST-Ericsson
 ti	Texas Instruments
+via	VIA Technologies, Inc.
 wlf	Wolfson Microelectronics
+wm	Wondermedia Technologies, Inc.
 xlnx	Xilinx
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
new file mode 100644
index 0000000..ccd15b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
@@ -0,0 +1,46 @@
+VIA VT8500 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-fb"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : framebuffer controller interrupt
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts.
+
+Example:
+
+	fb at d800e400 {
+		compatible = "via,vt8500-fb";
+		reg = <0xd800e400 0x400>;
+		interrupts = <12>;
+	};
+
+VIA VT8500 Display
+-----------------------------------------------------
+Required properties:
+- xres : lcd panel horizontal resolution
+- yres : lcd panel vertical resolution
+- left-margin,
+- right-margin,
+- hsync-len: lcd panel horizontal timings in pixels
+- upper-margin,
+- lower-margin,
+- vsync-len: lcd panel verticals timings in pixels
+- bpp: lcd panel bit-depth.
+	<16> for RGB565, <32> for RGB888
+
+Example:
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
new file mode 100644
index 0000000..a850fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia Graphics Engine Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,prizm-ge-rops"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	ge_rops at d8050400 {
+		compatible = "wm,prizm-ge-rops";
+		reg = <0xd8050400 0x100>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
new file mode 100644
index 0000000..ab67382
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -0,0 +1,20 @@
+Wondermedia WM8505 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,wm8505-fb"
+- reg : Should contain 1 register ranges(address and length)
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts. See definition in
+	Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+
+
+Example:
+
+	fb at d8050800 {
+		compatible = "wm,wm8505-fb";
+		reg = <0xd8050800 0x200>;
+	};
+
-- 
1.7.9.5



From linux at prisktech.co.nz  Wed Aug  8 21:54:58 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu,  9 Aug 2012 13:54:58 +1200
Subject: [PATCHv2 6/8] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1344477300-25251-7-git-send-email-linux@prisktech.co.nz>

Merged existing board files to a single dt-capable file.
Converted irq and timer code to devicetree.
Removed existing device files that are no longer required with
devicetree support.
All existing platform devices are converted to devicetree nodes
except PWM.

Removed restart.c and moved code into vt8500.c to remove
duplicate PMC code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/Kconfig                                |    2 +
 arch/arm/mach-vt8500/Kconfig                    |   72 +-----
 arch/arm/mach-vt8500/Makefile                   |    9 +-
 arch/arm/mach-vt8500/bv07.c                     |   80 -------
 arch/arm/mach-vt8500/common.h                   |   25 +++
 arch/arm/mach-vt8500/devices-vt8500.c           |   91 --------
 arch/arm/mach-vt8500/devices-wm8505.c           |   99 ---------
 arch/arm/mach-vt8500/devices.c                  |  270 -----------------------
 arch/arm/mach-vt8500/devices.h                  |   88 --------
 arch/arm/mach-vt8500/gpio.c                     |  240 --------------------
 arch/arm/mach-vt8500/include/mach/restart.h     |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h |   88 --------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h |   79 -------
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h |  115 ----------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h |   78 -------
 arch/arm/mach-vt8500/irq.c                      |  162 +++++++-------
 arch/arm/mach-vt8500/restart.c                  |   54 -----
 arch/arm/mach-vt8500/timer.c                    |   67 ++++--
 arch/arm/mach-vt8500/vt8500.c                   |  195 ++++++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c               |   79 -------
 20 files changed, 363 insertions(+), 1534 deletions(-)
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6774c80..0555b70 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -996,6 +996,7 @@ config ARCH_VT8500
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_PWM
+	select USE_OF
 	help
 	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1613,6 +1614,7 @@ config ARCH_NR_GPIO
 	default 355 if ARCH_U8500
 	default 264 if MACH_H4700
 	default 512 if SOC_OMAP5
+	default 288 if ARCH_VT8500
 	default 0
 	help
 	  Maximum number of GPIOs in the system.
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2c20a34..44f9f9d 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,73 +1,15 @@
 if ARCH_VT8500
 
-config VTWM_VERSION_VT8500
+config VTWM_VERSION_WMT_DT
 	bool
 
-config VTWM_VERSION_WM8505
-	bool
-
-config MACH_BV07
-	bool "Benign BV07-8500 Mini Netbook"
-	depends on ARCH_VT8500
-	select VTWM_VERSION_VT8500
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-	bool "WM8505 7-inch generic netbook"
+config MACH_WMT_DT
+	bool "VIA/Wondermedia SoC based boards (Device Tree Support)"
 	depends on ARCH_VT8500
-	select VTWM_VERSION_WM8505
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-	bool "7-inch with 800x480 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	default y
-	help
-	  These are found in most of the netbooks in generic cases, as
-	  well as in Eken M001 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x480' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_800X600
-	bool "8-inch with 800x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M003 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X576
-	bool "10-inch with 1024x576 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
+	select VTWM_VERSION_WMT_DT
 	help
-	  These are found in CherryPal netbooks and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x576' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X600
-	bool "10-inch with 1024x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M006 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
+	  Add support for netbooks, tablets and other devices based on
+	  the reference board design as produced by VIA/WonderMedia, using
+	  VT8500/WM8505/WM8650 System-on-Chip.
 
 endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 54e6997..1966183 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,9 +1,4 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_VTWM_VERSION_WMT_DT) += irq.o timer.o
+obj-$(CONFIG_MACH_WMT_DT) += vt8500.o
 
 obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2..0000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_lcdc,
-	&vt8500_device_ehci,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-	wmt_setup_restart();
-	vt8500_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= vt8500_reserve_mem,
-	.map_io		= vt8500_map_io,
-	.init_irq	= vt8500_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
new file mode 100644
index 0000000..06e93bb
--- /dev/null
+++ b/arch/arm/mach-vt8500/common.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-vt8500/dt_common.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
+
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+				struct device_node *parent);
+
+#endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519ae..0000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-	tmp[1] = wmt_irq_res(IRQ_LCDC);
-	wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = VT8500_IC_BASE;
-	wmt_gpio_base = VT8500_GPIO_BASE;
-	wmt_pmc_base = VT8500_PMC_BASE;
-	wmt_i8042_base = VT8500_PS2_BASE;
-
-	wmt_nr_irqs = VT8500_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e..0000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-	wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART4);
-	wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART5);
-	wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = WM8505_IC_BASE;
-	wmt_sic_base = WM8505_SIC_BASE;
-	wmt_gpio_base = WM8505_GPIO_BASE;
-	wmt_pmc_base = WM8505_PMC_BASE;
-	wmt_i8042_base = WM8505_PS2_BASE;
-
-	wmt_nr_irqs = WM8505_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 1fcdc36..0000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-	.name           = "vt8500-lcd",
-	.id             = 0,
-	.dev		= {
-		.dma_mask	= &fb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-	.name           = "wm8505-fb",
-	.id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 480 * 2,
-	.mode		= {
-		.name		= "800x480",
-		.xres		= 800,
-		.yres		= 480,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "800x600",
-		.xres		= 800,
-		.yres		= 600,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 576 * 2,
-	.mode		= {
-		.name		= "1024x576",
-		.xres		= 1024,
-		.yres		= 576,
-		.left_margin	= 40,
-		.right_margin	= 24,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 96,
-		.vsync_len	= 2,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "1024x600",
-		.xres		= 1024,
-		.yres		= 600,
-		.left_margin	= 66,
-		.right_margin	= 2,
-		.upper_margin	= 19,
-		.lower_margin	= 1,
-		.hsync_len	= 23,
-		.vsync_len	= 8,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(panels); i++) {
-		if (strcmp(panels[i].mode.name, str) == 0) {
-			current_panel_idx = i;
-			break;
-		}
-	}
-	return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-				  unsigned long align) {
-	p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-			(p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-					(8 / p->bpp) + 1));
-	p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-							  align);
-	p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-	.name		= "vt8500_serial",
-	.id		= 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-	.name		= "vt8500_serial",
-	.id		= 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-	.name		= "vt8500_serial",
-	.id		= 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-	.name		= "vt8500_serial",
-	.id		= 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-	.name		= "vt8500_serial",
-	.id		= 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-	.name		= "vt8500_serial",
-	.id		= 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-	.name		= "vt8500-ehci",
-	.id		= 0,
-	.dev		= {
-		.dma_mask	= &ehci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_ge_rops = {
-	.name		= "wmt_ge_rops",
-	.id		= -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-	.name		= "vt8500-pwm",
-	.id		= 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-	.pwm_id		= 0,
-	.max_brightness	= 128,
-	.dft_brightness = 70,
-	.pwm_period_ns	= 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-	.name		= "pwm-backlight",
-	.id		= 0,
-	.dev		= {
-		.platform_data = &vt8500_pwmbl_data,
-	},
-};
-
-struct platform_device vt8500_device_rtc = {
-	.name		= "vt8500-rtc",
-	.id		= 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-	/* SoC MMIO registers */
-	[0] = {
-		.virtual	= 0xf8000000,
-		.pfn		= __phys_to_pfn(0xd8000000),
-		.length		= 0x00390000, /* max of all chip variants */
-		.type		= MT_DEVICE
-	},
-	/* PCI I/O space, numbers tied to those in <mach/io.h> */
-	[1] = {
-		.virtual	= 0xf0000000,
-		.pfn		= __phys_to_pfn(0xc0000000),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE
-	},
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-	panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-	preallocate_fb(&panels[current_panel_idx], SZ_4M);
-	vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-	panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-	preallocate_fb(&panels[current_panel_idx], 32);
-	vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e1..0000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_MEM,
-		.start = start,
-		.end = start + size - 1,
-	};
-
-	return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_IRQ,
-		.start = irq,
-		.end = irq,
-	};
-
-	return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-			       const struct resource *res, unsigned int num)
-{
-	if (unlikely(platform_device_add_resources(pdev, res, num)))
-		pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec..0000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS	0x0
-#define DIRECTION_REGS	0x20
-#define OUTVALUE_REGS	0x40
-#define INVALUE_REGS	0x60
-
-#define EXT_REGOFF	0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-	struct gpio_chip	chip;
-	unsigned int		shift;
-	unsigned int		regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-				     unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-				   unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-		val |= (1 << vt8500_chip->shift << offset);
-		writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-	}
-	return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-	return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-		>> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-	if (value)
-		val |= (1 << vt8500_chip->shift << offset);
-	else
-		val &= ~(1 << vt8500_chip->shift << offset);
-
-	writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)		\
-{									\
-	.chip = {							\
-		.label			= __name,			\
-		.request		= vt8500_muxed_gpio_request,	\
-		.free			= vt8500_muxed_gpio_free,	\
-		.direction_input  = vt8500_muxed_gpio_direction_input,	\
-		.direction_output = vt8500_muxed_gpio_direction_output,	\
-		.get			= vt8500_muxed_gpio_get_value,	\
-		.set			= vt8500_muxed_gpio_set_value,	\
-		.can_sleep		= 0,				\
-		.base			= __base,			\
-		.ngpio			= __num,			\
-	},								\
-	.shift		= __shift,					\
-	.regoff		= __off,					\
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-	VT8500_GPIO_BANK("uart0",	0,	0x0,	8,	4),
-	VT8500_GPIO_BANK("uart1",	4,	0x0,	12,	4),
-	VT8500_GPIO_BANK("spi0",	8,	0x0,	16,	4),
-	VT8500_GPIO_BANK("spi1",	12,	0x0,	20,	4),
-	VT8500_GPIO_BANK("spi2",	16,	0x0,	24,	4),
-	VT8500_GPIO_BANK("pwmout",	24,	0x0,	28,	2),
-
-	VT8500_GPIO_BANK("sdmmc",	0,	0x4,	30,	11),
-	VT8500_GPIO_BANK("ms",		16,	0x4,	41,	7),
-	VT8500_GPIO_BANK("i2c0",	24,	0x4,	48,	2),
-	VT8500_GPIO_BANK("i2c1",	26,	0x4,	50,	2),
-
-	VT8500_GPIO_BANK("mii",		0,	0x8,	52,	20),
-	VT8500_GPIO_BANK("see",		20,	0x8,	72,	4),
-	VT8500_GPIO_BANK("ide",		24,	0x8,	76,	7),
-
-	VT8500_GPIO_BANK("ccir",	0,	0xc,	83,	19),
-
-	VT8500_GPIO_BANK("ts",		8,	0x10,	102,	11),
-
-	VT8500_GPIO_BANK("lcd",		0,	0x14,	113,	23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val &= ~(1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-	return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val |= (1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-		val |= (1 << offset);
-		writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-	}
-	return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-	if (value)
-		val |= (1 << offset);
-	else
-		val &= ~(1 << offset);
-
-	writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	if (offset > 7)
-		return -EINVAL;
-
-	return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-	.label			= "extgpio",
-	.direction_input	= vt8500_gpio_direction_input,
-	.direction_output	= vt8500_gpio_direction_output,
-	.get			= vt8500_gpio_get_value,
-	.set			= vt8500_gpio_set_value,
-	.to_irq			= vt8500_gpio_to_irq,
-	.can_sleep		= 0,
-	.base			= 0,
-	.ngpio			= 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-	regbase = ioremap(wmt_gpio_base, SZ_64K);
-	if (!regbase) {
-		printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-		return;
-	}
-
-	gpiochip_add(&vt8500_external_gpios);
-
-	for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-		gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b78..7389795 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee91..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC	0	/* JPEG Encoder */
-#define IRQ_JPEGDEC	1	/* JPEG Decoder */
-				/* Reserved */
-#define IRQ_PATA	3	/* PATA Controller */
-				/* Reserved */
-#define IRQ_DMA		5	/* DMA Controller */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_GE		8	/* Graphic Engine */
-#define IRQ_GOV		9	/* Graphic Overlay Engine */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-#define IRQ_MPEGTS	11	/* Transport Stream Interface */
-#define IRQ_LCDC	12	/* LCD Controller */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_CIPHER	16	/* Cipher */
-#define IRQ_VPP		17	/* Video Post-Processor */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-				/* Reserved */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_LCDDF	27	/* LCD Data Formatter */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_MS		30	/* MemoryStick Controller */
-#define IRQ_MS_DMA	31	/* MemoryStick Controller DMA */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_I2S		34	/* I2S */
-#define IRQ_PCM		35	/* PCM */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_VPU		40	/* Video Processing Unit */
-#define IRQ_VID		41	/* Video Digital Input Interface */
-#define IRQ_AC97	42	/* AC97 Interface */
-#define IRQ_EHCI	43	/* USB */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_PS2MOUSE	45	/* PS/2 Mouse */
-#define IRQ_PS2KBD	46	/* PS/2 Keyboard */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_ADC		51	/* ADC */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_DMA0	56	/* DMA Channel 0 */
-#define IRQ_DMA1	57	/* DMA Channel 1 */
-#define IRQ_DMA2	58	/* DMA Channel 2 */
-#define IRQ_DMA3	59	/* DMA Channel 3 */
-#define IRQ_DMA4	60	/* DMA Channel 4 */
-#define IRQ_DMA5	61	/* DMA Channel 5 */
-#define IRQ_DMA6	62	/* DMA Channel 6 */
-#define IRQ_DMA7	63	/* DMA Channel 7 */
-
-#define VT8500_NR_IRQS		64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ec..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define VT8500_DDR_BASE		0xd8000000	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define VT8500_DMA_BASE		0xd8001000	/* 1k	DMA Controller */
-#define VT8500_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define VT8500_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define VT8500_USB_BASE		0xd8007800	/* 2k	USB OTG */
-# define VT8500_EHCI_BASE	0xd8007900	/*	EHCI */
-# define VT8500_UHCI_BASE	0xd8007b01	/*	UHCI */
-#define VT8500_PATA_BASE	0xd8008000	/* 512	PATA */
-#define VT8500_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define VT8500_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define VT8500_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define VT8500_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define VT8500_MS_BASE		0xd800b000	/* 1k	MS/MSPRO Controller */
-#define VT8500_LCDC_BASE	0xd800e400	/* 1k	LCD Controller */
-#define VT8500_VPU_BASE		0xd8050000	/* 256	VPU */
-#define VT8500_GOV_BASE		0xd8050300	/* 256	GOV */
-#define VT8500_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE	0xd8050900	/* 256	LCD Formatter */
-#define VT8500_VID_BASE		0xd8050a00	/* 256	VID */
-#define VT8500_VPP_BASE		0xd8050b00	/* 256	VPP */
-#define VT8500_TSBK_BASE	0xd80f4000	/* 4k	TSBK */
-#define VT8500_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define VT8500_JPEGENC_BASE	0xd80ff000	/* 4k	JPEG Encoder */
-#define VT8500_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define VT8500_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define VT8500_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define VT8500_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define VT8500_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define VT8500_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define VT8500_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define VT8500_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define VT8500_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define VT8500_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define VT8500_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define VT8500_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define VT8500_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define VT8500_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define VT8500_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define VT8500_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define VT8500_PCM_BASE		0xd82d0000	/* 64k	PCM */
-#define VT8500_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define VT8500_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define VT8500_ADC_BASE		0xd8340000	/* 64k	ADC */
-
-#define VT8500_REGS_END_PHYS	0xd834ffff	/* End of MMIO registers */
-#define VT8500_REGS_LENGTH	(VT8500_REGS_END_PHYS \
-				- VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI	0	/* UHC FS (UHCI?) */
-#define IRQ_EHCI	1	/* UHC HS */
-#define IRQ_UDCDMA	2	/* UDC DMA */
-				/* Reserved */
-#define IRQ_PS2MOUSE	4	/* PS/2 Mouse */
-#define IRQ_UDC		5	/* UDC */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_KEYPAD	8	/* Keypad */
-#define IRQ_DMA		9	/* DMA Controller */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-				/* Reserved */
-				/* Reserved */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_APB		16	/* APB Bridge */
-#define IRQ_DMA0	17	/* DMA Channel 0 */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-#define IRQ_PS2KBD	23	/* PS/2 Keyboard */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_DMA1	27	/* DMA Channel 1 */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_UART5	30	/* UART 5 */
-#define IRQ_UART4	31	/* UART 4 */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_DMA2	34	/* DMA Channel 2 */
-#define IRQ_I2S		35	/* I2S */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_DMA3	40	/* DMA Channel 3 */
-#define IRQ_DMA4	41	/* DMA Channel 4 */
-#define IRQ_AC97	42	/* AC97 Interface */
-				/* Reserved */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_DMA5	45	/* DMA Channel 5 */
-#define IRQ_DMA6	46	/* DMA Channel 6 */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_DMA7	51	/* DMA Channel 7 */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_SIC0	56	/* SIC IRQ0 */
-#define IRQ_SIC1	57	/* SIC IRQ1 */
-#define IRQ_SIC2	58	/* SIC IRQ2 */
-#define IRQ_SIC3	59	/* SIC IRQ3 */
-#define IRQ_SIC4	60	/* SIC IRQ4 */
-#define IRQ_SIC5	61	/* SIC IRQ5 */
-#define IRQ_SIC6	62	/* SIC IRQ6 */
-#define IRQ_SIC7	63	/* SIC IRQ7 */
-				/* Reserved */
-#define IRQ_JPEGDEC	65	/* JPEG Decoder */
-#define IRQ_SAE		66	/* SAE (?) */
-				/* Reserved */
-#define IRQ_VPU		79	/* Video Processing Unit */
-#define IRQ_VPP		80	/* Video Post-Processor */
-#define IRQ_VID		81	/* Video Digital Input Interface */
-#define IRQ_SPU		82	/* SPU (?) */
-#define IRQ_PIP		83	/* PIP Error */
-#define IRQ_GE		84	/* Graphic Engine */
-#define IRQ_GOV		85	/* Graphic Overlay Engine */
-#define IRQ_DVO		86	/* Digital Video Output */
-				/* Reserved */
-#define IRQ_DMA8	92	/* DMA Channel 8 */
-#define IRQ_DMA9	93	/* DMA Channel 9 */
-#define IRQ_DMA10	94	/* DMA Channel 10 */
-#define IRQ_DMA11	95	/* DMA Channel 11 */
-#define IRQ_DMA12	96	/* DMA Channel 12 */
-#define IRQ_DMA13	97	/* DMA Channel 13 */
-#define IRQ_DMA14	98	/* DMA Channel 14 */
-#define IRQ_DMA15	99	/* DMA Channel 15 */
-				/* Reserved */
-#define IRQ_GOVW	111	/* GOVW (?) */
-#define IRQ_GOVRSDSCD	112	/* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF	113	/* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD	114	/* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF	115	/* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS		116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df15509..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define WM8505_DDR_BASE		0xd8000400	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define WM8505_DMA_BASE		0xd8001800	/* 1k	DMA Controller */
-#define WM8505_VDMA_BASE	0xd8001c00	/* 1k	VDMA */
-#define WM8505_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define WM8505_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define WM8505_USB_BASE		0xd8007000	/* 2k	USB 2.0 Host */
-# define WM8505_EHCI_BASE	0xd8007100	/*	EHCI */
-# define WM8505_UHCI_BASE	0xd8007301	/*	UHCI */
-#define WM8505_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define WM8505_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define WM8505_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define WM8505_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define WM8505_VPU_BASE		0xd8050000	/* 256	VPU */
-#define WM8505_GOV_BASE		0xd8050300	/* 256	GOV */
-#define WM8505_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE	0xd8050800	/* 512	GOVR (frambuffer) */
-#define WM8505_VID_BASE		0xd8050a00	/* 256	VID */
-#define WM8505_SCL_BASE		0xd8050d00	/* 256	SCL */
-#define WM8505_VPP_BASE		0xd8050f00	/* 256	VPP */
-#define WM8505_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define WM8505_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define WM8505_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define WM8505_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define WM8505_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define WM8505_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define WM8505_SIC_BASE		0xd8150000	/* 64k	Secondary IC */
-#define WM8505_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define WM8505_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define WM8505_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define WM8505_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define WM8505_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define WM8505_KEYPAD_BASE	0xd8260000	/* 64k	Keypad control */
-#define WM8505_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define WM8505_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define WM8505_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define WM8505_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define WM8505_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define WM8505_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define WM8505_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define WM8505_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define WM8505_UART4_BASE	0xd8370000	/* 64k	UART 4 */
-#define WM8505_UART5_BASE	0xd8380000	/* 64k	UART 5 */
-
-#define WM8505_REGS_END_PHYS	0xd838ffff	/* End of MMIO registers */
-#define WM8505_REGS_LENGTH	(WM8505_REGS_END_PHYS \
-				- WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de04..d9aac4b 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
  *  arch/arm/mach-vt8500/irq.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,16 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
 
+#include <linux/of.h>
+#include <linux/of_address.h>
+
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR		0x40		/* Destination control
-						register, 64*u8 */
+#define VT8500_IC_DCTR		0x40
+
 #define VT8500_INT_ENABLE	(1 << 3)
 #define VT8500_TRIGGER_HIGH	(0 << 4)
 #define VT8500_TRIGGER_RISING	(1 << 4)
@@ -36,63 +46,55 @@
 				| VT8500_TRIGGER_FALLING)
 #define VT8500_IC_STATUS	0x80		/* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt;
+
+struct vt8500_irq_priv {
+	void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 edge;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+	edge = readb(base + VT8500_IC_DCTR + d->hwirq) & VT8500_EDGE;
 	if (edge) {
 		void __iomem *stat_reg = base + VT8500_IC_STATUS
-						+ (irq < 32 ? 0 : 4);
+						+ (d->hwirq < 32 ? 0 : 4);
 		unsigned status = readl(stat_reg);
 
-		status |= (1 << (irq & 0x1f));
+		status |= (1 << (d->hwirq & 0x1f));
 		writel(status, stat_reg);
 	} else {
-		u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+		u8 dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 
 		dctr &= ~VT8500_INT_ENABLE;
-		writeb(dctr, base + VT8500_IC_DCTR + irq);
+		writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 	}
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 	dctr |= VT8500_INT_ENABLE;
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
-	unsigned orig_irq = irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_IC_DCTR + d->hwirq);
 	dctr &= ~VT8500_EDGE;
 
 	switch (flow_type) {
@@ -100,18 +102,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 		return -EINVAL;
 	case IRQF_TRIGGER_HIGH:
 		dctr |= VT8500_TRIGGER_HIGH;
-		__irq_set_handler_locked(orig_irq, handle_level_irq);
+		__irq_set_handler_locked(d->irq, handle_level_irq);
 		break;
 	case IRQF_TRIGGER_FALLING:
 		dctr |= VT8500_TRIGGER_FALLING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	case IRQF_TRIGGER_RISING:
 		dctr |= VT8500_TRIGGER_RISING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	}
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_IC_DCTR + d->hwirq);
 
 	return 0;
 }
@@ -124,57 +126,57 @@ static struct irq_chip vt8500_irq_chip = {
 	.irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
 	unsigned int i;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+	/* Enable rotating priority for IRQ */
+	writel((1 << 6), base + 0x20);
+	writel(0, base + 0x24);
 
-	if (ic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
+	for (i = 0; i < 64; i++) {
+		/* Disable all interrupts and route them to IRQ */
+		writeb(0x00, base + VT8500_IC_DCTR + i);
+	}
+}
 
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
 
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+	.map = vt8500_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-	unsigned int i;
+	struct irq_domain *vt8500_irq_domain;
+	struct vt8500_irq_priv *priv;
+	struct device_node *np = node;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-	sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-	if (ic_regbase && sic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
-		writel((1 << 6), sic_regbase + 0x20);
-		writel(0, sic_regbase + 0x24);
-
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			if (i < 64)
-				writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-			else
-				writeb(0x00, sic_regbase + VT8500_IC_DCTR
-								+ i - 64);
-
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+	priv->base = of_iomap(np, 0);
+
+	vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+				&vt8500_irq_domain_ops, priv);
+	if (!vt8500_irq_domain)
+		pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+
+	irq_set_default_host(vt8500_irq_domain);
+
+	vt8500_init_irq_hw(priv->base);
+
+	pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+						(u32)(priv->base), irq_cnt);
+
+	irq_cnt += 64;
+
+	return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a..0000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE		0xD8130000
-#define WMT_PRIZM_PMSR_REG	0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-	struct device_node *np;
-
-	/*
-	 * Check if Power Mgmt Controller node is present in device tree. If no
-	 * device tree node, use the legacy PMSR value (valid for all current
-	 * SoCs).
-	 */
-	np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-	if (np) {
-		pmc_base = of_iomap(np, 0);
-
-		if (!pmc_base)
-			pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-		of_node_put(np);
-	} else {
-		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-		if (!pmc_base) {
-			pr_err("%s:ioremap(rstc) failed\n", __func__);
-			return;
-		}
-	}
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-	if (pmc_base)
-		writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c5..050e183 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET	0x0100
+#define VT8500_TIMER_HZ		3000000
 #define TIMER_MATCH_VAL		0x0000
 #define TIMER_COUNT_VAL		0x0010
 #define TIMER_STATUS_VAL	0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
 #define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
 #define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */
-#define VT8500_TIMER_HZ		3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
 	return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
 	.name           = "vt8500_timer",
 	.rating         = 200,
 	.read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
 	}
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
 	.name           = "vt8500_timer",
 	.features       = CLOCK_EVT_FEAT_ONESHOT,
 	.rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
 	.name    = "vt8500_timer",
 	.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = vt8500_timer_interrupt,
 	.dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+	{ .compatible = "via,vt8500-timer" },
+	{ }
+};
+
+void __init vt8500_timer_init(void)
 {
-	regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-	if (!regbase)
-		printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+	struct device_node *np;
+	int timer_irq;
+
+	np = of_find_matching_node(NULL, vt8500_timer_ids);
+	if (!np) {
+		pr_err("%s: Timer description missing from Device Tree\n",
+								__func__);
+		return;
+	}
+	regbase = of_iomap(np, 0);
+	if (!regbase) {
+		pr_err("%s: Missing iobase description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
+	timer_irq = irq_of_parse_and_map(np, 0);
+	if (!timer_irq) {
+		pr_err("%s: Missing irq description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
 
 	writel(1, regbase + TIMER_CTRL_VAL);
 	writel(0xf, regbase + TIMER_STATUS_VAL);
 	writel(~0, regbase + TIMER_MATCH_VAL);
 
 	if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-		printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
-					clocksource.name);
+		pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
+					__func__, clocksource.name);
 
 	clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
 
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
 	clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
 	clockevent.cpumask = cpumask_of(0);
 
-	if (setup_irq(wmt_timer_irq, &irq))
-		printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
-					clockevent.name);
+	if (setup_irq(timer_irq, &irq))
+		pr_err("%s: setup_irq failed for %s\n", __func__,
+							clockevent.name);
 	clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-	.init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 0000000..2bfff9f
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,195 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE	0xD8110000
+#define LEGACY_PMC_BASE		0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG	0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG		0x12
+#define VT8500_PMSR_REG		0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+	if (pmc_base)
+		writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+	/* SoC MMIO registers */
+	[0] = {
+		.virtual	= 0xf8000000,
+		.pfn		= __phys_to_pfn(0xd8000000),
+		.length		= 0x00390000, /* max of all chip variants */
+		.type		= MT_DEVICE
+	},
+};
+
+void __init vt8500_map_io(void)
+{
+	iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+	local_irq_disable();
+	writew(5, pmc_base + VT8500_HCR_REG);
+	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+	struct device_node *np, *fb;
+	void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+	fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+				gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+#ifdef CONFIG_FB_WM8505
+	fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np)
+			np = of_find_compatible_node(NULL, NULL,
+							"wm,wm8650-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+				0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+	np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+	if (np) {
+		pmc_base = of_iomap(np, 0);
+
+		if (!pmc_base)
+			pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+		of_node_put(np);
+	} else {
+		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+		if (!pmc_base)
+			pr_err("%s:ioremap(power_off) failed\n", __func__);
+	}
+	if (pmc_base)
+		pm_power_off = &vt8500_power_off;
+	else
+		pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+	{ .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+	{ /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+	of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+	.init = vt8500_timer_init,
+};
+
+static const char * const vt8500_dt_compat[] = {
+	"via,vt8500",
+	"wm,wm8650",
+	"wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+	.dt_compat	= vt8500_dt_compat,
+	.map_io		= vt8500_map_io,
+	.init_irq	= vt8500_init_irq,
+	.timer		= &vt8500_timer,
+	.init_machine	= vt8500_init,
+	.restart	= vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886..0000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_ehci,
-	&vt8500_device_wm8505_fb,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-	wmt_setup_restart();
-	wm8505_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= wm8505_reserve_mem,
-	.map_io		= wm8505_map_io,
-	.init_irq	= wm8505_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= wm8505_7in_init,
-MACHINE_END
-- 
1.7.9.5



From jason77.wang at gmail.com  Wed Aug  8 23:18:47 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 9 Aug 2012 11:18:47 +0800
Subject: imx6q restart is broken
In-Reply-To: <50224547.9020000@de.bosch.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com>
Message-ID: <50232C17.9000700@gmail.com>

Dirk Behme wrote:
> On 08.08.2012 12:18, Shawn Guo wrote:
>> Thanks Dirk for reporting that imx6q restart (reboot command) is broken.
>>
>> I tracked down the issue a little bit and found imx6q_restart hangs
>> on the of_iomap/ioremap call. The following change, moving the call
>> somewhere else than imx6q_restart, will just fix the problem.
>>
>> Does that mean ioremap call is not allowed in platform restart hook?
>> I'm not sure about that, because I found it works just fine if I build
>> imx_v6_v7_defconfig with V6 (imx3) platforms excluded (IOW, build a V7
>> only kernel - imx5 and imx6), which is the case how I tested imx6q
>> restart feature when I was adding it.
>>
>> To summarize, the imx6q_restart hangs at ioremap call on a V6 + V7
>> kernel, while it works fine on a V7 only image. I need some help to
>> understand that.
>
> Some additional information from my debugging:
>
> a) Having a JTAG debugger attached to the i.MX6 SabreLite board I use 
> (kernel built with imx_v6_v7_defconfig) the reboot does work. No hang. 
> This does mean I can't debug the reboot hang with a JTAG debugger. 
> Therefore I added some printk debugging:
>
> b) Adding some printk statements [1] in the of_iomap/ioremap call, it 
> looks to me that the system hangs in
>
> of_iomap() -> ... -> set_pte_at() -> set_pte_ext() / 
> cpu_v7_set_pte_ext() <= hang
>
I noticed this problem several weeks ago, and did some debug, what i 
found is following:

- at the last stage of reset, all non-boot cpus will call 
ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb() for 
V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10, 5")

- the boot cpu will call cpu_v7_set_pte_ext() in the proc-v7-2level.S, 
at the end of this function, boot cpu will call flush_pte (mcr p15, 0, 
r0, c7, c10, 1), after executing this function, the system will hang. 
That is to say, all non-boot cpus repeatedly call ("mcr p15, 0, %0, c7, 
c10, 5"), if boot cpu call flush_pte (mcr p15, 0, r0, c7, c10, 1), the 
system will hang, this occurs on the cortexa9 r2p10 cpus (freescale 
i.MX6Q), i don't know the root cause for this problem, but if we split 
imx_v6_v7_defconfig into v7_only and use v7_only to build kernel image 
for imx6q, this problem will disappear, since the cpu_relax() will be 
defined to barrier().

- i think we should split imx_v6_v7_defconfig into v6_only and v7_only, 
since when we use imx_v6_v7_defconfig, we will introduce 
"-D__LINUX_ARM_ARCH__=6" unconditionally, this macro is OK for V6 
platforms (imx3), but it is not good for V7 platforms (imx5, imx6). lets 
grep "__LINUX_ARM_ARCH__" occurrence under the arch/arm, all (#if 
__LINUX_ARM_ARCH__ == 6) and (#if __LINUX_ARM_ARCH__ >= 7) occurrence 
will affect V7 platforms.

Regards,
Hui.






From yuxu at marvell.com  Wed Aug  8 23:33:23 2012
From: yuxu at marvell.com (Yu Xu)
Date: Thu,  9 Aug 2012 11:33:23 +0800
Subject: [PATCH] ARM: mmp: add USB3.0 PHY support
Message-ID: <1344483203-17446-1-git-send-email-yuxu@marvell.com>

Add USB 3.0 PHY support.

Signed-off-by: Yu Xu <yuxu at marvell.com>
---
 arch/arm/mach-mmp/devices.c               |  227 +++++++++++++++++++++++++++++
 arch/arm/mach-mmp/include/mach/regs-usb.h |   94 ++++++++++++
 2 files changed, 321 insertions(+)

diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index dd2d8b1..699522b 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -349,3 +349,230 @@ struct platform_device pxa168_device_u2ootg = {
 #endif /* CONFIG_USB_MV_OTG */
 
 #endif
+
+#ifdef CONFIG_USB_MV_U3D
+static u32 u3d_phy_read(u32 base, u32 reg)
+{
+	u32 addr, data;
+	addr = base;
+	data = base + 0x4;
+
+	writel_relaxed(reg, addr);
+	return readl_relaxed(data);
+}
+
+static void u3d_phy_set(u32 base, u32 reg, u32 value)
+{
+	u32 addr, data;
+	u32 tmp;
+	addr = base;
+	data = base + 0x4;
+
+	writel_relaxed(reg, addr);
+	tmp = readl_relaxed(data);
+	tmp |= value;
+	writel_relaxed(tmp, data);
+}
+
+static void u3d_phy_clear(u32 base, u32 reg, u32 value)
+{
+	u32 addr, data;
+	u32 tmp;
+	addr = base;
+	data = base + 0x4;
+
+	writel_relaxed(reg, addr);
+	tmp = readl_relaxed(data);
+	tmp &= ~value;
+	writel_relaxed(tmp, data);
+}
+
+static void u3d_phy_write(u32 base, u32 reg, u32 value)
+{
+	u32 addr, data;
+	addr = base;
+	data = base + 0x4;
+
+	writel_relaxed(reg, addr);
+	writel_relaxed(value, data);
+}
+
+static void u3d_phy_reg_print(u32 base, u32 reg)
+{
+	u32 data;
+	data = u3d_phy_read(base, reg);
+	pr_debug("phy reg 0x%x: phy data 0x%x\n", reg, data);
+}
+
+void pxa_u3d_phy_deinit(void __iomem *usb3phy)
+{
+	u32 base, val;
+
+	pr_debug("%s\n", __func__);
+
+	base = (unsigned int)usb3phy;
+
+	/* Power down Reference Analog current, bit 15
+	 * Power down PLL, bit 14
+	 * Power down Receiver, bit 13
+	 * Power down Transmitter, bit 12
+	 * of USB3_POWER_PLL_CONTROL register
+	 */
+	val = u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
+	val &= ~(USB3_POWER_PLL_CONTROL_PU);
+	u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
+}
+
+int pxa_u3d_phy_init(void __iomem *usb3phy)
+{
+	u32 count;
+	u32 base, val;
+
+	pr_debug("%s\n", __func__);
+
+	/* enable usb3 phy */
+	base = (unsigned int)usb3phy;
+
+	val = u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
+	val &= ~(USB3_POWER_PLL_CONTROL_PU_MASK);
+	val |= 0xF << USB3_POWER_PLL_CONTROL_PU_SHIFT;
+	u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
+	udelay(100);
+
+	u3d_phy_write(base, USB3_RESET_CONTROL, USB3_RESET_CONTROL_RESET_PIPE);
+	udelay(100);
+
+	u3d_phy_write(base, USB3_RESET_CONTROL,
+		USB3_RESET_CONTROL_RESET_PIPE | USB3_RESET_CONTROL_RESET_PHY);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_POWER_PLL_CONTROL);
+	val &= ~(USB3_POWER_PLL_CONTROL_REF_FREF_SEL_MASK
+		| USB3_POWER_PLL_CONTROL_PHY_MODE_MASK);
+	val |=  (USB3_PLL_25MHZ << USB3_POWER_PLL_CONTROL_REF_FREF_SEL_SHIFT)
+		| (0x5 << USB3_POWER_PLL_CONTROL_PHY_MODE_SHIFT);
+	u3d_phy_write(base, USB3_POWER_PLL_CONTROL, val);
+	udelay(100);
+
+	u3d_phy_clear(base, USB3_KVCO_CALI_CONTROL,
+		USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_MASK);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_SQUELCH_FFE);
+	val &= ~(USB3_SQUELCH_FFE_FFE_CAP_SEL_MASK
+		| USB3_SQUELCH_FFE_FFE_RES_SEL_MASK
+		| USB3_SQUELCH_FFE_SQ_THRESH_IN_MASK);
+	val |= ((0xD << USB3_SQUELCH_FFE_FFE_CAP_SEL_SHIFT)
+		| (0x7 << USB3_SQUELCH_FFE_FFE_RES_SEL_SHIFT)
+		| (0x8 << USB3_SQUELCH_FFE_SQ_THRESH_IN_SHIFT));
+	u3d_phy_write(base, USB3_SQUELCH_FFE, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_GEN1_SET0);
+	val &= ~USB3_GEN1_SET0_G1_TX_SLEW_CTRL_EN_MASK;
+	val |= 1 << USB3_GEN1_SET0_G1_TX_EMPH_EN_SHIFT;
+	u3d_phy_write(base, USB3_GEN1_SET0, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_GEN2_SET0);
+	val &= ~(USB3_GEN2_SET0_G2_TX_AMP_MASK
+		| USB3_GEN2_SET0_G2_TX_EMPH_AMP_MASK
+		| USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_MASK);
+	val |= ((0x14 << USB3_GEN2_SET0_G2_TX_AMP_SHIFT)
+		| (1 << USB3_GEN2_SET0_G2_TX_AMP_ADJ_SHIFT)
+		| (0xA << USB3_GEN2_SET0_G2_TX_EMPH_AMP_SHIFT)
+		| (1 << USB3_GEN2_SET0_G2_TX_EMPH_EN_SHIFT));
+	u3d_phy_write(base, USB3_GEN2_SET0, val);
+	udelay(100);
+
+	u3d_phy_read(base, USB3_TX_EMPPH);
+	val &= ~(USB3_TX_EMPPH_AMP_MASK
+		| USB3_TX_EMPPH_EN_MASK
+		| USB3_TX_EMPPH_AMP_FORCE_MASK
+		| USB3_TX_EMPPH_PAR1_MASK
+		| USB3_TX_EMPPH_PAR2_MASK);
+	val |= ((0xB << USB3_TX_EMPPH_AMP_SHIFT)
+		| (1 << USB3_TX_EMPPH_EN_SHIFT)
+		| (1 << USB3_TX_EMPPH_AMP_FORCE_SHIFT)
+		| (0x1C << USB3_TX_EMPPH_PAR1_SHIFT)
+		| (1 << USB3_TX_EMPPH_PAR2_SHIFT));
+
+	u3d_phy_write(base, USB3_TX_EMPPH, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_GEN2_SET1);
+	val &= ~(USB3_GEN2_SET1_G2_RX_SELMUPI_MASK
+		| USB3_GEN2_SET1_G2_RX_SELMUPF_MASK
+		| USB3_GEN2_SET1_G2_RX_SELMUFI_MASK
+		| USB3_GEN2_SET1_G2_RX_SELMUFF_MASK);
+	val |= ((1 << USB3_GEN2_SET1_G2_RX_SELMUPI_SHIFT)
+		| (1 << USB3_GEN2_SET1_G2_RX_SELMUPF_SHIFT)
+		| (1 << USB3_GEN2_SET1_G2_RX_SELMUFI_SHIFT)
+		| (1 << USB3_GEN2_SET1_G2_RX_SELMUFF_SHIFT));
+	u3d_phy_write(base, USB3_GEN2_SET1, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_DIGITAL_LOOPBACK_EN);
+	val &= ~USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_MASK;
+	val |= 1 << USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_SHIFT;
+	u3d_phy_write(base, USB3_DIGITAL_LOOPBACK_EN, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_IMPEDANCE_TX_SSC);
+	val &= ~USB3_IMPEDANCE_TX_SSC_SSC_AMP_MASK;
+	val |= 0xC << USB3_IMPEDANCE_TX_SSC_SSC_AMP_SHIFT;
+	u3d_phy_write(base, USB3_IMPEDANCE_TX_SSC, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_IMPEDANCE_CALI_CTRL);
+	val &= ~USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_MASK;
+	val |= 0x4 << USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_SHIFT;
+	u3d_phy_write(base, USB3_IMPEDANCE_CALI_CTRL, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_PHY_ISOLATION_MODE);
+	val &= ~(USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_MASK
+		| USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_MASK
+		| USB3_PHY_ISOLATION_MODE_TX_DRV_IDLE_MASK);
+	val |= ((1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_SHIFT)
+		| (1 << USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_SHIFT));
+	u3d_phy_write(base, USB3_PHY_ISOLATION_MODE, val);
+	udelay(100);
+
+	val = u3d_phy_read(base, USB3_TXDETRX);
+	val &= ~(USB3_TXDETRX_VTHSEL_MASK);
+	val |= 0x1 << USB3_TXDETRX_VTHSEL_SHIFT;
+	u3d_phy_write(base, USB3_TXDETRX, val);
+	udelay(100);
+
+	u3d_phy_reg_print(base, USB3_KVCO_CALI_CONTROL);
+
+	pr_debug("%s: start calibration", __func__);
+
+calstart:
+	/* Perform Manual Calibration */
+	u3d_phy_set(base, USB3_KVCO_CALI_CONTROL,
+		1 << USB3_KVCO_CALI_CONTROL_CAL_START_SHIFT);
+
+	mdelay(1);
+
+	count = 0;
+	while (1) {
+		val = u3d_phy_read(base, USB3_KVCO_CALI_CONTROL);
+		if (val & (1 << USB3_KVCO_CALI_CONTROL_CAL_DONE_SHIFT))
+			break;
+		else if (count > 50) {
+			pr_debug("calibration failure, retry...\n");
+			goto calstart;
+		}
+		count++;
+		mdelay(1);
+	}
+
+	/* active PIPE interface */
+	u3d_phy_write(base, USB3_PIPE_SM_CTRL,
+		1 << USB3_PIPE_SM_CTRL_PHY_INIT_DONE);
+
+	return 0;
+}
+#endif /* CONFIG_USB_MV_U3D */
diff --git a/arch/arm/mach-mmp/include/mach/regs-usb.h b/arch/arm/mach-mmp/include/mach/regs-usb.h
index b047bf4..5bac566 100644
--- a/arch/arm/mach-mmp/include/mach/regs-usb.h
+++ b/arch/arm/mach-mmp/include/mach/regs-usb.h
@@ -250,4 +250,98 @@
 #define	HSIC_USB_CLK_PHY		0x0
 #define HSIC_USB_CLK_PMU		0x1
 
+/* For USB3 PHY */
+#define USB3_POWER_PLL_CONTROL		0x1
+#define USB3_KVCO_CALI_CONTROL		0x2
+#define USB3_IMPEDANCE_CALI_CTRL	0x3
+#define USB3_IMPEDANCE_TX_SSC		0x4
+#define USB3_SQUELCH_FFE		0x6
+#define USB3_GEN1_SET0			0xD
+#define USB3_GEN2_SET0			0xF
+#define USB3_GEN2_SET1			0x10
+#define USB3_DIGITAL_LOOPBACK_EN	0x23
+#define USB3_PHY_ISOLATION_MODE		0x26
+#define USB3_TXDETRX			0x48
+#define USB3_TX_EMPPH			0x5E
+#define USB3_RESET_CONTROL		0x90
+#define USB3_PIPE_SM_CTRL		0x91
+
+#define USB3_RESET_CONTROL_RESET_PIPE			0x1
+#define USB3_RESET_CONTROL_RESET_PHY			0x2
+
+#define USB3_POWER_PLL_CONTROL_REF_FREF_SEL_MASK	(0x1F << 0)
+#define USB3_POWER_PLL_CONTROL_REF_FREF_SEL_SHIFT	0
+#define USB3_PLL_25MHZ					0x2
+#define USB3_PLL_26MHZ					0x5
+#define USB3_POWER_PLL_CONTROL_PHY_MODE_MASK		(0x7 << 5)
+#define USB3_POWER_PLL_CONTROL_PHY_MODE_SHIFT		5
+#define USB3_POWER_PLL_CONTROL_PU_MASK			(0xF << 12)
+#define USB3_POWER_PLL_CONTROL_PU_SHIFT			12
+#define USB3_POWER_PLL_CONTROL_PU			(0xF << 12)
+
+#define USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_MASK	(0x1 << 12)
+#define USB3_KVCO_CALI_CONTROL_USE_MAX_PLL_RATE_SHIFT	12
+#define USB3_KVCO_CALI_CONTROL_CAL_DONE_SHIFT		14
+#define USB3_KVCO_CALI_CONTROL_CAL_START_SHIFT		15
+
+#define USB3_SQUELCH_FFE_FFE_CAP_SEL_MASK		0xF
+#define USB3_SQUELCH_FFE_FFE_CAP_SEL_SHIFT		0
+#define USB3_SQUELCH_FFE_FFE_RES_SEL_MASK		(0x7 << 4)
+#define USB3_SQUELCH_FFE_FFE_RES_SEL_SHIFT		4
+#define USB3_SQUELCH_FFE_SQ_THRESH_IN_MASK		(0x1F << 8)
+#define USB3_SQUELCH_FFE_SQ_THRESH_IN_SHIFT		8
+
+#define USB3_GEN1_SET0_G1_TX_SLEW_CTRL_EN_MASK		(0x1 << 15)
+#define USB3_GEN1_SET0_G1_TX_EMPH_EN_SHIFT		11
+
+#define USB3_GEN2_SET0_G2_TX_AMP_MASK			(0x1F << 1)
+#define USB3_GEN2_SET0_G2_TX_AMP_SHIFT			1
+#define USB3_GEN2_SET0_G2_TX_AMP_ADJ_SHIFT		6
+#define USB3_GEN2_SET0_G2_TX_EMPH_AMP_MASK		(0xF << 7)
+#define USB3_GEN2_SET0_G2_TX_EMPH_AMP_SHIFT		7
+#define USB3_GEN2_SET0_G2_TX_EMPH_EN_MASK		(0x1 << 11)
+#define USB3_GEN2_SET0_G2_TX_EMPH_EN_SHIFT		11
+#define USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_MASK		(0x1 << 15)
+#define USB3_GEN2_SET0_G2_TX_SLEW_CTRL_EN_SHIFT		15
+
+#define USB3_GEN2_SET1_G2_RX_SELMUPI_MASK		(0x7 << 0)
+#define USB3_GEN2_SET1_G2_RX_SELMUPI_SHIFT		0
+#define USB3_GEN2_SET1_G2_RX_SELMUPF_MASK		(0x7 << 3)
+#define USB3_GEN2_SET1_G2_RX_SELMUPF_SHIFT		3
+#define USB3_GEN2_SET1_G2_RX_SELMUFI_MASK		(0x3 << 6)
+#define USB3_GEN2_SET1_G2_RX_SELMUFI_SHIFT		6
+#define USB3_GEN2_SET1_G2_RX_SELMUFF_MASK		(0x3 << 8)
+#define USB3_GEN2_SET1_G2_RX_SELMUFF_SHIFT		8
+
+#define USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_MASK		(0x3 << 10)
+#define USB3_DIGITAL_LOOPBACK_EN_SEL_BITS_SHIFT		10
+
+#define USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_MASK	(0x7 << 12)
+#define USB3_IMPEDANCE_CALI_CTRL_IMP_CAL_THR_SHIFT	12
+
+#define USB3_IMPEDANCE_TX_SSC_SSC_AMP_MASK		(0x3F << 0)
+#define USB3_IMPEDANCE_TX_SSC_SSC_AMP_SHIFT		0
+
+#define USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_MASK		0xF
+#define USB3_PHY_ISOLATION_MODE_PHY_GEN_RX_SHIFT	0
+#define USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_MASK		(0xF << 4)
+#define USB3_PHY_ISOLATION_MODE_PHY_GEN_TX_SHIFT	4
+#define USB3_PHY_ISOLATION_MODE_TX_DRV_IDLE_MASK	(0x1 << 8)
+
+#define USB3_TXDETRX_VTHSEL_MASK			(0x3 << 4)
+#define USB3_TXDETRX_VTHSEL_SHIFT			4
+
+#define USB3_TX_EMPPH_AMP_MASK				(0xF << 0)
+#define USB3_TX_EMPPH_AMP_SHIFT				0
+#define USB3_TX_EMPPH_EN_MASK				(0x1 << 6)
+#define USB3_TX_EMPPH_EN_SHIFT				6
+#define USB3_TX_EMPPH_AMP_FORCE_MASK			(0x1 << 7)
+#define USB3_TX_EMPPH_AMP_FORCE_SHIFT			7
+#define USB3_TX_EMPPH_PAR1_MASK				(0x1F << 8)
+#define USB3_TX_EMPPH_PAR1_SHIFT			8
+#define USB3_TX_EMPPH_PAR2_MASK				(0x1 << 13)
+#define USB3_TX_EMPPH_PAR2_SHIFT			13
+
+#define USB3_PIPE_SM_CTRL_PHY_INIT_DONE			15
+
 #endif /* __ASM_ARCH_PXA_U2O_H */
-- 
1.7.9.5



From tarun.kanti at ti.com  Thu Aug  9 00:06:05 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Thu, 9 Aug 2012 09:36:05 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <87k3x9wbrk.fsf@ti.com>
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
 <87k3x9wbrk.fsf@ti.com>
Message-ID: <CAC83ZvLKk71O=+9U16FoTUU_-ffg+iJsHPgnJx+bzbHhBDXzhQ@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:40 PM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> Add *remove* callback so that necessary cleanup operations are
>> performed when device is unregistered. The device is deleted
>> from the list and associated clock handle is released by
>> calling clk_put() and irq descriptor is released using the
>> irq_free_desc() api.
>>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> Reported-by: Paul Walmsley <paul at pwsan.com>
>> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
>> Cc: Kevin Hilman <khilman at ti.com>
>> Cc: Rajendra Nayak <rnayak at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Cc: Cousson, Benoit <b-cousson at ti.com>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> ---
>> v2:
>> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>>
>> (1) Use irq_free_descs() instead of irq_free_desc().
>>     Besides, irq_free_desc() was using wrong parameter,
>>     irq_base, instead of bank->irq.
>> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>>     in order to avoid exception warnings.
>>
>> (3) pm_runtime_disable() added so that bind can happen successfully
>>
>> Test Detail:
>> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>>
>> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>>
>> Step 3: Execute read/write GPIO test case.
>
> What happens when GPIOs are in use (requested)?
If I try to unbind a currently active GPIO bank then I see an exception
after the irq descriptor is freed by the remove. I believe this is expected
because interrupt raised by the system would not be handled.

[   18.859405] irq_free_descs: calling free_desc(192)...
[   18.866180] irq_free_descs: calling free_desc(192)...
[   18.872680] irq_free_descs: calling free_desc(192)...
[   18.877990] irq_free_descs: calling free_desc(192)...
[   18.883270] irq_free_descs: calling free_desc(192)...
[   18.888549] irq_free_descs: calling free_desc(192)...
[   18.893859] irq_free_descs: calling free_desc(192)...
[   18.899139] irq_free_descs: calling free_desc(192)...
[   18.904418] irq_free_descs: calling free_desc(192)...
[   18.909729] irq_free_descs: calling free_desc(192)...
[   18.915008] irq_free_descs: calling free_desc(192)...
[   18.920288] irq_free_descs: calling free_desc(192)...
[   18.925598] irq_free_descs: calling free_desc(192)...
[   18.930877] irq_free_descs: calling free_desc(192)...
[   18.936157] irq_free_descs: calling free_desc(192)...
[   18.941467] irq_free_descs: calling free_desc(192)...
[   18.946746] irq_free_descs: calling free_desc(192)...
[   18.952026] irq_free_descs: calling free_desc(192)...
[   18.957336] irq_free_descs: calling free_desc(192)...
[   18.962615] irq_free_descs: calling free_desc(192)...
[   18.967895] irq_free_descs: calling free_desc(192)...
[   18.973205] irq_free_descs: calling free_desc(192)...
[   18.978485] irq_free_descs: calling free_desc(192)...
[   18.983764] irq_free_descs: calling free_desc(192)...
[   18.989074] irq_free_descs: calling free_desc(192)...
[   18.994354] irq_free_descs: calling free_desc(192)...
[   18.999633] irq_free_descs: calling free_desc(192)...
[   19.004913] irq_free_descs: calling free_desc(192)...
[   19.010223] irq_free_descs: calling free_desc(192)...
[   19.015502] irq_free_descs: calling free_desc(192)...
[   19.020782] irq_free_descs: calling free_desc(192)...
[   19.026092] irq_free_descs: calling free_desc(192)...
[   19.032440] irq 194, desc: c072f340, depth: 1, count: 0, unhandled: 0
[   19.039154] ->handle_irq():  c00a3e08, handle_bad_irq+0x0/0x260
[   19.045379] ->irq_data.chip(): c078ff7c, no_irq_chip+0x0/0x5c
[   19.051391] ->action(): ef0d42c0
[   19.054748] ->action->handler(): c0399ee0, ks8851_irq+0x0/0x1c
[   19.060852]    IRQ_NOPROBE set
[   19.064056]  IRQ_NOREQUEST set
[   19.067230] Unable to handle kernel paging request at virtual address 203a6c9
[   19.074768] pgd = c0004000
[   19.077606] [203a6c99] *pgd=00000000
[   19.081329] Internal error: Oops: 5 [#1] SMP ARM
[   19.086151] Modules linked in:
[   19.089355] CPU: 0    Not tainted  (3.6.0-rc1-00003-g43a916d-dirty #885)
[   19.096374] PC is at gpio_irq_handler+0x7c/0x26c
[   19.101165] LR is at handle_bad_irq+0x1cc/0x260
[   19.105895] pc : [<c02e13b0>]    lr : [<c00a3fd4>]    psr: 60000093
[   19.105895] sp : c0725df8  ip : 00006fc6  fp : 00000001
[   19.117889] r10: 00000000  r9 : fa05502c  r8 : 00000020
[   19.123352] r7 : 00000000  r6 : 00000000  r5 : 00000000  r4 : ef0bbe10
[   19.130157] r3 : ef0c1980  r2 : 203a6c65  r1 : 00000034  r0 : 00000000
[   19.136993] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kel
[   19.144714] Control: 10c53c7d  Table: ae89804a  DAC: 00000017
[   19.150695] Process swapper/0 (pid: 0, stack limit = 0xc07242f8)
[   19.156982] Stack: (0xc0725df8 to 0xc0726000)
[   19.161529] 5de0:                                                       c0740
[   19.170074] 5e00: c0724000 c0724000 c07440d8 c07224a4 0000003e 00000000 c0740
[   19.178619] 5e20: c0725edc c00a3670 000001da c0015380 fa24010c c0742d30 c0720
[   19.187164] 5e40: 00000001 c000846c c0746980 c04f8c74 20000013 ffffffff c0724
[   19.195709] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
[   19.204223] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
[   19.212768] 5ea0: 20000013 ffffffff c0724000 c007425c 00000002 00000000 c0077
[   19.221313] 5ec0: ef320b00 c0746980 00000000 c1530ac0 ef320b00 c0722ac0 c0720
[   19.229858] 5ee0: c152ec20 c00696cc 00000000 00000000 c0724000 c0724000 c1524
[   19.238403] 5f00: c152ec20 c0015e14 c0722ac0 c0722ac0 c0722ac0 c0722ac0 c0720
[   19.246948] 5f20: c0722ac0 c0722ac0 6e6b0f0d 00000004 00000000 00000000 c0080
[   19.255493] 5f40: 00000001 00000000 00000000 501539bc 00000004 c0091654 c1528
[   19.264038] 5f60: c07d55b8 5006c071 00000000 c008cab8 00000000 00000002 50064
[   19.272552] 5f80: c0748078 c0724000 c07c0548 c0504510 c0747e60 00000000 411f8
[   19.281097] 5fa0: 00000000 c0015e14 00000000 c0743e1c c07c0480 c07057dc bfffa
[   19.289642] 5fc0: 00000000 c06d48d8 ffffffff ffffffff c06d4450 00000000 0000c
[   19.298187] 5fe0: 00000000 10c53c7d c0742d08 c07057ac c0747e54 80008044 00000
[   19.306732] [<c02e13b0>] (gpio_irq_handler+0x7c/0x26c) from [<c00a3670>] (ge)
[   19.316558] [<c00a3670>] (generic_handle_irq+0x34/0x44) from [<c0015380>] (h)
[   19.325744] [<c0015380>] (handle_IRQ+0x4c/0xac) from [<c000846c>] (gic_handl)
[   19.334564] [<c000846c>] (gic_handle_irq+0x2c/0x60) from [<c04f8ee4>] (__irq)
[   19.343292] Exception stack(0xc0725e60 to 0xc0725ea8)
[   19.348571] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
[   19.357116] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
[   19.365631] 5ea0: 20000013 ffffffff
[   19.369293] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c04f8c74>] (_raw_spin_)
[   19.378570] [<c04f8c74>] (_raw_spin_unlock_irq+0x28/0x2c) from [<c007425c>] )
[   19.388732] [<c007425c>] (finish_task_switch+0x84/0x198) from [<c04f7760>] ()
[   19.398193] [<c04f7760>] (__schedule+0x404/0x870) from [<c0015e14>] (cpu_idl)
[   19.406768] [<c0015e14>] (cpu_idle+0xe8/0x114) from [<c06d48d8>] (start_kern)
[   19.415466] Code: e59480e4 e1d311b4 e5d36034 e1a0a81b (e7920001)
[   19.421844] ---[ end trace 3eb9bf4b81babe15 ]---
[   19.426666] Kernel panic - not syncing: Fatal exception in interrupt
[   19.433288] CPU1: stopping
[   19.436157] [<c001beac>] (unwind_backtrace+0x0/0xf4) from [<c0019db4>] (hand)
[   19.445220] [<c0019db4>] (handle_IPI+0x130/0x15c) from [<c0008498>] (gic_han)
[   19.454223] [<c0008498>] (gic_handle_irq+0x58/0x60) from [<c04f8ee4>] (__irq)
[   19.462951] Exception stack(0xef06ff88 to 0xef06ffd0)
[   19.468231] ff80:                   c079f960 c079f960 00000000 00000000 ef068
[   19.476745] ffa0: c0504510 c0747e60 00000000 411fc092 c0748078 00000000 00000
[   19.485290] ffc0: c0015570 c0015574 60000113 ffffffff
[   19.490570] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c0015574>] (default_id)
[   19.499114] [<c0015574>] (default_idle+0x20/0x44) from [<c0015dc8>] (cpu_idl)
[   19.507659] [<c0015dc8>] (cpu_idle+0x9c/0x114) from [<804f1d94>] (0x804f1d94)
---
Tarun
>
> Kevin
>
>>  drivers/gpio/gpio-omap.c |   35 +++++++++++++++++++++++++++++++++++
>>  1 files changed, 35 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>> index e6efd77..50de875 100644
>> --- a/drivers/gpio/gpio-omap.c
>> +++ b/drivers/gpio/gpio-omap.c
>> @@ -1152,6 +1152,40 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>>       return ret;
>>  }
>>
>> +/**
>> + * omap_gpio_remove - cleanup a registered gpio device
>> + * @pdev:       pointer to current gpio platform device
>> + *
>> + * Called by driver framework whenever a gpio device is unregistered.
>> + * GPIO is deleted from the list and associated clock handle freed.
>> + */
>> +static int __devexit omap_gpio_remove(struct platform_device *pdev)
>> +{
>> +     struct device *dev = &pdev->dev;
>> +     struct gpio_bank *bank;
>> +     unsigned long flags;
>> +     int ret = -EINVAL;
>> +
>> +     list_for_each_entry(bank, &omap_gpio_list, node) {
>> +             spin_lock_irqsave(&bank->lock, flags);
>> +             if (bank->dev == dev) {
>> +                     clk_put(bank->dbck);
>> +                     list_del(&bank->node);
>> +                     ret = 0;
>> +                     spin_unlock_irqrestore(&bank->lock, flags);
>> +                     break;
>> +             }
>> +             spin_unlock_irqrestore(&bank->lock, flags);
>> +     }
>> +
>> +     if (!ret) {
>> +             pm_runtime_disable(bank->dev);
>> +             irq_free_descs(bank->irq_base, bank->width);
>> +     }
>> +
>> +     return ret;
>> +}
>> +
>>  #ifdef CONFIG_ARCH_OMAP2PLUS
>>
>>  #if defined(CONFIG_PM_RUNTIME)
>> @@ -1478,6 +1512,7 @@ MODULE_DEVICE_TABLE(of, omap_gpio_match);
>>
>>  static struct platform_driver omap_gpio_driver = {
>>       .probe          = omap_gpio_probe,
>> +     .remove = __devexit_p(omap_gpio_remove),
>>       .driver         = {
>>               .name   = "omap_gpio",
>>               .pm     = &gpio_pm_ops,


From shawn.guo at linaro.org  Thu Aug  9 00:41:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 12:41:38 +0800
Subject: imx6q restart is broken
In-Reply-To: <50232C17.9000700@gmail.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
Message-ID: <20120809044131.GF14718@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
> Dirk Behme wrote:
> >On 08.08.2012 12:18, Shawn Guo wrote:
> >>Thanks Dirk for reporting that imx6q restart (reboot command) is broken.
> >>
> >>I tracked down the issue a little bit and found imx6q_restart hangs
> >>on the of_iomap/ioremap call. The following change, moving the call
> >>somewhere else than imx6q_restart, will just fix the problem.
> >>
> >>Does that mean ioremap call is not allowed in platform restart hook?
> >>I'm not sure about that, because I found it works just fine if I build
> >>imx_v6_v7_defconfig with V6 (imx3) platforms excluded (IOW, build a V7
> >>only kernel - imx5 and imx6), which is the case how I tested imx6q
> >>restart feature when I was adding it.
> >>
> >>To summarize, the imx6q_restart hangs at ioremap call on a V6 + V7
> >>kernel, while it works fine on a V7 only image. I need some help to
> >>understand that.
> >
> >Some additional information from my debugging:
> >
> >a) Having a JTAG debugger attached to the i.MX6 SabreLite board I
> >use (kernel built with imx_v6_v7_defconfig) the reboot does work.
> >No hang. This does mean I can't debug the reboot hang with a JTAG
> >debugger. Therefore I added some printk debugging:
> >
> >b) Adding some printk statements [1] in the of_iomap/ioremap call,
> >it looks to me that the system hangs in
> >
> >of_iomap() -> ... -> set_pte_at() -> set_pte_ext() /
> >cpu_v7_set_pte_ext() <= hang
> >
> I noticed this problem several weeks ago, and did some debug, what i
> found is following:
> 
Thanks for these great findings.  I also just tracked it down to that
cpu_v7_set_pte_ext hangs on

	mcr   p15, 0, r0, c7, c10, 1          @ flush_pte

> - at the last stage of reset, all non-boot cpus will call
> ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb()
> for V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10,
> 5")
> 
> - the boot cpu will call cpu_v7_set_pte_ext() in the
> proc-v7-2level.S, at the end of this function, boot cpu will call
> flush_pte (mcr p15, 0, r0, c7, c10, 1), after executing this
> function, the system will hang. That is to say, all non-boot cpus
> repeatedly call ("mcr p15, 0, %0, c7, c10, 5"), if boot cpu call
> flush_pte (mcr p15, 0, r0, c7, c10, 1), the system will hang, this
> occurs on the cortexa9 r2p10 cpus (freescale i.MX6Q), i don't know
> the root cause for this problem, but if we split imx_v6_v7_defconfig
> into v7_only and use v7_only to build kernel image for imx6q, this
> problem will disappear, since the cpu_relax() will be defined to
> barrier().
> 
> - i think we should split imx_v6_v7_defconfig into v6_only and
> v7_only, since when we use imx_v6_v7_defconfig, we will introduce
> "-D__LINUX_ARM_ARCH__=6" unconditionally, this macro is OK for V6
> platforms (imx3), but it is not good for V7 platforms (imx5, imx6).
> lets grep "__LINUX_ARM_ARCH__" occurrence under the arch/arm, all
> (#if __LINUX_ARM_ARCH__ == 6) and (#if __LINUX_ARM_ARCH__ >= 7)
> occurrence will affect V7 platforms.

I just copied a few more people.  Let's hear their comments.

Regards,
Shawn



From nico at fluxnic.net  Thu Aug  9 01:12:15 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 09 Aug 2012 01:12:15 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120807115647.GA12828@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208090029460.5231@xanadu.home>

On Tue, 7 Aug 2012, Will Deacon wrote:

> Hello,
> 
> ARM recently moved to asm-generic/mutex-xchg.h for its mutex implementation
> after our previous implementation was found to be missing some crucial
> memory barriers. However, I'm seeing some problems running hackbench on
> SMP platforms due to the way in which the MUTEX_SPIN_ON_OWNER code operates.
> 
> The symptoms are that a bunch of hackbench tasks are left waiting on an
> unlocked mutex and therefore never get woken up to claim it. I think this
> boils down to the following sequence:
> 
> 
>         Task A        Task B        Task C        Lock value
> 0                                                     1
> 1       lock()                                        0
> 2                     lock()                          0
> 3                     spin(A)                         0
> 4       unlock()                                      1
> 5                                   lock()            0
> 6                     cmpxchg(1,0)                    0
> 7                     contended()                    -1
> 8       lock()                                        0
> 9       spin(C)                                       0
> 10                                  unlock()          1
> 11      cmpxchg(1,0)                                  0
> 12      unlock()                                      1
> 
> 
> At this point, the lock is unlocked, but Task B is in an uninterruptible
> sleep with nobody to wake it up.
> 
> The following patch fixes the problem by ensuring we put the lock into
> the contended state if we acquire it from the spin loop on the slowpath
> but I'd like to be sure that this won't cause problems with other mutex
> implementations:
> 
> 
> diff --git a/kernel/mutex.c b/kernel/mutex.c
> index a307cc9..27b7887 100644
> --- a/kernel/mutex.c
> +++ b/kernel/mutex.c
> @@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
>                 if (owner && !mutex_spin_on_owner(lock, owner))
>                         break;
>  
> -               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> +               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
>                         lock_acquired(&lock->dep_map, ip);
>                         mutex_set_owner(lock);
>                         preempt_enable();
> 
> 
> All comments welcome.

Well... after thinking about this for a while, I came to the conclusion 
that the mutex_spin_on_owner code is indeed breaking the contract 
between the xchg lock fast path and the slow path.  The xchg fast path 
will always set the count to 0 and rely on the slow path to restore a 
possible pre-existing negative count.  So the above change would be 
needed for correctness in the xchg case, even if it always forces the 
unlock into the slow path.

As I mentioned previously, we don't want to force the slow path in all 
cases though.  The atomic decrement based fast path doesn't need that, 
so I'd suggest this fix instead:

diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 580a6d35c7..60964844c8 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -108,4 +108,6 @@ __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
 	return prev;
 }
 
+#define __MUTEX_XCHG_FAST_PATH
+
 #endif
diff --git a/kernel/mutex.c b/kernel/mutex.c
index a307cc9c95..c6a26a4f1c 100644
--- a/kernel/mutex.c
+++ b/kernel/mutex.c
@@ -161,6 +161,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
 
 	for (;;) {
 		struct task_struct *owner;
+		int locked_val;
 
 		/*
 		 * If there's an owner, wait for it to either
@@ -170,7 +171,19 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
 		if (owner && !mutex_spin_on_owner(lock, owner))
 			break;
 
-		if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
+#ifdef __MUTEX_XCHG_FAST_PATH
+		/*
+		 * The fast path based on xchg sets a transient 0 count,
+		 * relying on the slow path to restore a possible
+		 * pre-existing contended count.  Without checking the
+		 * waiters' list we must presume possible contension here.
+		 */
+		locked_val = -1;
+#else
+		locked_val = 0;
+#endif
+
+		if (atomic_cmpxchg(&lock->count, 1, locked_val) == 1) {
 			lock_acquired(&lock->dep_map, ip);
 			mutex_set_owner(lock);
 			preempt_enable();

That would be needed for the stable tree as well.

A further cleanup could remove all definitions of 
__mutex_slowpath_needs_to_unlock() given that they're all set to 1 
except for the xchg fast path, in which case __MUTEX_XCHG_FAST_PATH 
could be reused instead.

Of course that might tilt the balance towards using mutex-dec.h on ARM 
v6 and above instead of mutex-xchg.h.  But that is an orthogonal issue, 
and that doesn't remove the need for fixing the xchg based case for 
correctness.


Nicolas


From santosh.shilimkar at ti.com  Thu Aug  9 01:27:37 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 9 Aug 2012 10:57:37 +0530
Subject: [PATCH 1/2] cpufreq: OMAP: Handle missing frequency table on SMP
 systems
In-Reply-To: <87wr19uwbx.fsf@ti.com>
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-2-git-send-email-rnayak@ti.com>
 <CAMQu2gyooQ4x=ZGDZFg5BuBaEkgQx2kTAvtiGLEjXwOYvF_wMQ@mail.gmail.com>
 <87wr19uwbx.fsf@ti.com>
Message-ID: <CAMQu2gxo8gdvk1jYx_asw+R7iyE1OAqxaVFbDgJSc0ED_-y9xQ@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:58 PM, Kevin Hilman <khilman at ti.com> wrote:
>
> "Shilimkar, Santosh" <santosh.shilimkar at ti.com> writes:
>
> > On Wed, Aug 8, 2012 at 4:24 PM, Rajendra Nayak <rnayak at ti.com> wrote:
> >>
> >> On OMAP4, if the first CPU fails to get a valid frequency table (this
> >> could happen if the platform does not register any OPP table), the
> >> subsequent CPU instances end up dealing with a NULL freq_table and
> >> crash. Add a check for a NULL freq_table to help error the rest
> >> of the CPU instances out.
> >>
> >> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> >> Cc: <linux-pm at vger.kernel.org>
> >> ---
> >>  drivers/cpufreq/omap-cpufreq.c |    2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/cpufreq/omap-cpufreq.c
> >> b/drivers/cpufreq/omap-cpufreq.c
> >> index 17fa04d..0ee824c 100644
> >> --- a/drivers/cpufreq/omap-cpufreq.c
> >> +++ b/drivers/cpufreq/omap-cpufreq.c
> >> @@ -221,7 +221,7 @@ static int __cpuinit omap_cpu_init(struct
> >> cpufreq_policy *policy)
> >>         if (atomic_inc_return(&freq_table_users) == 1)
> >>                 result = opp_init_cpufreq_table(mpu_dev, &freq_table);
> >>
> >> -       if (result) {
> >> +       if (result || !freq_table) {
> >>                 dev_err(mpu_dev, "%s: cpu%d: failed creating freq
> >> table[%d]\n",
> >>                                 __func__, policy->cpu, result);
> >>                 goto fail_ck;
> >
> > The freq_table use count seems to be buggy in that case.
> > Something like below should fix the issue.
> > Feel free to update your patch with below if you agree.
> >
> > diff --git a/drivers/cpufreq/omap-cpufreq.c
> > b/drivers/cpufreq/omap-cpufreq.c
> > index 17fa04d..fd97c3d 100644
> > --- a/drivers/cpufreq/omap-cpufreq.c
> > +++ b/drivers/cpufreq/omap-cpufreq.c
> > @@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct
> > cpufreq_policy *po
> >
> >         policy->cur = policy->min = policy->max =
> > omap_getspeed(policy->cpu);
> >
> > -       if (atomic_inc_return(&freq_table_users) == 1)
> > +       if (freq_table)
>
> I think you meant 'if (!freq_table)' ?
>
Right.

regards
Santosh


From kgene.kim at samsung.com  Thu Aug  9 01:31:59 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 09 Aug 2012 14:31:59 +0900
Subject: [PATCH 4/6] ARM: s3c24xx: use new PWM driver
In-Reply-To: <201208081434.56198.arnd@arndb.de>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-5-git-send-email-arnd@arndb.de>
 <0b6801cd7567$29be48b0$7d3ada10$%kim@samsung.com>
 <201208081434.56198.arnd@arndb.de>
Message-ID: <0c3901cd75f0$4c26bb60$e4743220$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> On Wednesday 08 August 2012, Kukjin Kim wrote:
> 
> > diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-
> s3c24xx/Kconfig
> > index e249611..d56b0f7 100644
> > --- a/arch/arm/mach-s3c24xx/Kconfig
> > +++ b/arch/arm/mach-s3c24xx/Kconfig
> > @@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
> >  	select I2C
> >  	select POWER_SUPPLY
> >  	select MACH_NEO1973
> > -	select S3C2410_PWM
> > +	select S3C24XX_PWM
> >  	select S3C_DEV_USB_HOST
> >  	help
> >  	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM
> > Phone
> > @@ -493,7 +493,7 @@ config MACH_RX1950
> >  	select S3C24XX_DCLK
> >  	select PM_H1940 if PM
> >  	select I2C
> > -	select S3C2410_PWM
> > +	select S3C24XX_PWM
> >  	select S3C_DEV_NAND
> >  	select S3C2410_IOTIMING if S3C2440_CPUFREQ
> >  	select S3C2440_XTAL_16934400
> > diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-
> samsung/Kconfig
> > index 7aca31c..dcdfb77 100644
> > --- a/arch/arm/plat-samsung/Kconfig
> > +++ b/arch/arm/plat-samsung/Kconfig
> > @@ -403,7 +403,7 @@ config S5P_DEV_USB_EHCI
> >
> >  config S3C24XX_PWM
> >  	bool "PWM device support"
> > -	select HAVE_PWM
> > +	select PWM
> >  	help
> >  	  Support for exporting the PWM timer blocks via the pwm device
> >  	  system
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index 8fc3808..c74d055 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -58,14 +58,12 @@ config PWM_PXA
> >  	  will be called pwm-pxa.
> >
> >  config PWM_SAMSUNG
> > -	tristate "Samsung pwm support"
> > +	bool "Samsung PWM support"
> >  	depends on PLAT_SAMSUNG
> > +	default y
> >  	help
> >  	  Generic PWM framework driver for Samsung.
> >
> > -	  To compile this driver as a module, choose M here: the module
> > -	  will be called pwm-samsung.
> > -
> >  config PWM_TEGRA
> >  	tristate "NVIDIA Tegra PWM support"
> >  	depends on ARCH_TEGRA
> 
> This approach has two disadvantages compared to mine:
> 
> * When building for the samsung platforms other than rx1950 or gta02,
>   you can no longer have the PWM driver as a loadable module, for no
>   good reason.
> 
OK I see, I'm still thinking the PWM driver can be selected in kernel
menuconfig though.

My concept is when PWM is selected on Samsung platforms by defconfig or
manually enabling, PWM_SAMSUNG is selected automatically. In addition,
current Samsung PWM driver cannot support module now because pwm_init() is
called by arch_initcall().

I think, we can remove S3C24XX_PWM and just select PWM (or using HAVE_PWM)
and PWM_SAMSUNG can be selected by enabling PWM in samsung platform next
time :-)

> * It is still possible to manually disable PWM_SAMSUNG, even on
>   rx1950 and gta02, because the Kconfig symbol is visible.
> 
Yeah you're right, makes sense.

> I've added a "Reported-by: Tushar Behera <tushar.behera at linaro.org>"
> line to my version of the patch, but I would prefer to keep that
> approach. I have also changed the patch to use the S3C24XX_PWM
> symbol because that lets everyone migrate the defconfig files.
> 
OK.

> Do you want to give this patch some more testing, or should I keep
> it in arm-soc?
> 
Looks good to me, please keep going on.

> ---
> From 438b0cf94adb2528bdeeb71314f7be16512ea5b1 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Sat, 4 Aug 2012 07:52:19 +0000
> Subject: [PATCH] ARM: s3c24xx: use new PWM driver
> 
> The samsung PWM driver has moved to the new PWM subsystem, which
> changed the Kconfig symbol for that driver, but the rx1950 and
> gta02 boards still uses the old one.
> 
> Without this patch, building s3c2410_defconfig results in:
> 
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_lcd_power':
> arch/arm/mach-s3c24xx/mach-rx1950.c:430: undefined reference to
> `pwm_config'
> arch/arm/mach-s3c24xx/mach-rx1950.c:431: undefined reference to
> `pwm_disable'
> arch/arm/mach-s3c24xx/mach-rx1950.c:437: undefined reference to
> `pwm_config'
> arch/arm/mach-s3c24xx/mach-rx1950.c:438: undefined reference to
> `pwm_enable'
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_exit':
> arch/arm/mach-s3c24xx/mach-rx1950.c:504: undefined reference to `pwm_free'
> arch/arm/mach-s3c24xx/built-in.o: In function `rx1950_backlight_init':
> arch/arm/mach-s3c24xx/mach-rx1950.c:487: undefined reference to
> `pwm_request'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Reported-by: Tushar Behera <tushar.behera at linaro.org>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> 
Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
> index e249611..d56b0f7 100644
> --- a/arch/arm/mach-s3c24xx/Kconfig
> +++ b/arch/arm/mach-s3c24xx/Kconfig
> @@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
>  	select I2C
>  	select POWER_SUPPLY
>  	select MACH_NEO1973
> -	select S3C2410_PWM
> +	select S3C24XX_PWM
>  	select S3C_DEV_USB_HOST
>  	help
>  	   Say Y here if you are using the Openmoko GTA02 / Freerunner GSM
> Phone
> @@ -493,7 +493,7 @@ config MACH_RX1950
>  	select S3C24XX_DCLK
>  	select PM_H1940 if PM
>  	select I2C
> -	select S3C2410_PWM
> +	select S3C24XX_PWM
>  	select S3C_DEV_NAND
>  	select S3C2410_IOTIMING if S3C2440_CPUFREQ
>  	select S3C2440_XTAL_16934400
> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
> index 7aca31c..9c3b90c 100644
> --- a/arch/arm/plat-samsung/Kconfig
> +++ b/arch/arm/plat-samsung/Kconfig
> @@ -403,7 +403,8 @@ config S5P_DEV_USB_EHCI
> 
>  config S3C24XX_PWM
>  	bool "PWM device support"
> -	select HAVE_PWM
> +	select PWM
> +	select PWM_SAMSUNG
>  	help
>  	  Support for exporting the PWM timer blocks via the pwm device
>  	  system



From robherring2 at gmail.com  Thu Aug  9 01:37:02 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  9 Aug 2012 00:37:02 -0500
Subject: [RFC PATCH] ARM: add coherent dma ops
Message-ID: <1344490622-20029-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

arch_is_coherent is problematic as it is a global symbol. This
doesn't work for multi-platform kernels or platforms which can support
per device coherent DMA.

This adds arm_coherent_dma_ops to be used for devices which connected
coherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops
are modified at boot when arch_is_coherent is true.

This does not address arch_is_coherent used in iommu dma ops.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
---
Compile tested only.

 arch/arm/mm/dma-mapping.c |   89 +++++++++++++++++++++++++++++++++++++++------
 1 file changed, 77 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c2cdf65..8875cd4 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -73,11 +73,18 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
 	     unsigned long offset, size_t size, enum dma_data_direction dir,
 	     struct dma_attrs *attrs)
 {
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_cpu_to_dev(page, offset, size, dir);
 	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
 }
 
+static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
+	     unsigned long offset, size_t size, enum dma_data_direction dir,
+	     struct dma_attrs *attrs)
+{
+	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
+}
+
 /**
  * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -96,7 +103,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
 		size_t size, enum dma_data_direction dir,
 		struct dma_attrs *attrs)
 {
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
 				      handle & ~PAGE_MASK, size, dir);
 }
@@ -106,8 +113,7 @@ static void arm_dma_sync_single_for_cpu(struct device *dev,
 {
 	unsigned int offset = handle & (PAGE_SIZE - 1);
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-	if (!arch_is_coherent())
-		__dma_page_dev_to_cpu(page, offset, size, dir);
+	__dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
 static void arm_dma_sync_single_for_device(struct device *dev,
@@ -115,8 +121,7 @@ static void arm_dma_sync_single_for_device(struct device *dev,
 {
 	unsigned int offset = handle & (PAGE_SIZE - 1);
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-	if (!arch_is_coherent())
-		__dma_page_cpu_to_dev(page, offset, size, dir);
+	__dma_page_cpu_to_dev(page, offset, size, dir);
 }
 
 static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
@@ -138,6 +143,40 @@ struct dma_map_ops arm_dma_ops = {
 };
 EXPORT_SYMBOL(arm_dma_ops);
 
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+				  dma_addr_t handle, struct dma_attrs *attrs);
+
+struct dma_map_ops arm_coherent_dma_ops = {
+	.alloc			= arm_coherent_dma_alloc,
+	.free			= arm_coherent_dma_free,
+	.mmap			= arm_dma_mmap,
+	.get_sgtable		= arm_dma_get_sgtable,
+	.map_page		= arm_coherent_dma_map_page,
+	.map_sg			= arm_dma_map_sg,
+	.set_dma_mask		= arm_dma_set_mask,
+};
+EXPORT_SYMBOL(arm_coherent_dma_ops);
+
+static int __init dma_map_init(void)
+{
+	if (!arch_is_coherent())
+		return 0;
+
+	arm_dma_ops.map_page = arm_coherent_dma_map_page;
+	arm_dma_ops.unmap_page = NULL;
+	arm_dma_ops.map_sg = NULL;
+	arm_dma_ops.unmap_sg = NULL;
+	arm_dma_ops.sync_single_for_cpu = NULL;
+	arm_dma_ops.sync_single_for_device = NULL;
+	arm_dma_ops.sync_sg_for_cpu = NULL;
+	arm_dma_ops.sync_sg_for_device = NULL;
+	arm_dma_ops.alloc = arm_coherent_dma_alloc;
+	arm_dma_ops.free = arm_coherent_dma_free;
+}
+core_initcall(dma_map_init);
+
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = (u64)arm_dma_limit;
@@ -538,7 +577,7 @@ static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
 
 
 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
-			 gfp_t gfp, pgprot_t prot, const void *caller)
+			 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
 {
 	u64 mask = get_coherent_dma_mask(dev);
 	struct page *page;
@@ -571,7 +610,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 	*handle = DMA_ERROR_CODE;
 	size = PAGE_ALIGN(size);
 
-	if (arch_is_coherent() || nommu())
+	if (is_coherent || nommu())
 		addr = __alloc_simple_buffer(dev, size, gfp, &page);
 	else if (gfp & GFP_ATOMIC)
 		addr = __alloc_from_pool(size, &page);
@@ -599,7 +638,20 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 	if (dma_alloc_from_coherent(dev, size, handle, &memory))
 		return memory;
 
-	return __dma_alloc(dev, size, handle, gfp, prot,
+	return __dma_alloc(dev, size, handle, gfp, prot, false,
+			   __builtin_return_address(0));
+}
+
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
+{
+	pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
+	void *memory;
+
+	if (dma_alloc_from_coherent(dev, size, handle, &memory))
+		return memory;
+
+	return __dma_alloc(dev, size, handle, gfp, prot, true,
 			   __builtin_return_address(0));
 }
 
@@ -636,8 +688,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 /*
  * Free a buffer as defined by the above mapping.
  */
-void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
-		  dma_addr_t handle, struct dma_attrs *attrs)
+static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+			   dma_addr_t handle, struct dma_attrs *attrs,
+			   bool is_coherent)
 {
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
 
@@ -646,7 +699,7 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 
 	size = PAGE_ALIGN(size);
 
-	if (arch_is_coherent() || nommu()) {
+	if (is_coherent || nommu()) {
 		__dma_free_buffer(page, size);
 	} else if (!IS_ENABLED(CONFIG_CMA)) {
 		__dma_free_remap(cpu_addr, size);
@@ -662,6 +715,18 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 	}
 }
 
+void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+		  dma_addr_t handle, struct dma_attrs *attrs)
+{
+	__arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
+}
+
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+				  dma_addr_t handle, struct dma_attrs *attrs)
+{
+	__arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
+}
+
 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
 		 void *cpu_addr, dma_addr_t handle, size_t size,
 		 struct dma_attrs *attrs)
-- 
1.7.9.5



From dirk.behme at de.bosch.com  Thu Aug  9 01:45:19 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 9 Aug 2012 07:45:19 +0200
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Add Chipidea USB driver support
In-Reply-To: <1344463589-8115-1-git-send-email-festevam@gmail.com>
References: <1344463589-8115-1-git-send-email-festevam@gmail.com>
Message-ID: <50234E6F.1050406@de.bosch.com>

On 09.08.2012 00:06, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Add Chipidea USB driver support.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/configs/imx_v6_v7_defconfig |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..5f6138d 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -179,6 +179,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_EHCI_MXC=y
> +CONFIG_USB_CHIPIDEA=y
> +CONFIG_USB_CHIPIDEA_HOST=y
> +CONFIG_USB_MXS_PHY=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_MMC=y
>  CONFIG_MMC_SDHCI=y

I'm not sure if we still need

CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y

or if this can be removed? Besides this:

Acked-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk


From santosh.shilimkar at ti.com  Thu Aug  9 01:51:01 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 9 Aug 2012 11:21:01 +0530
Subject: [PATCH] ARM: OMAP4: sleep: Save the complete used register stack
 frame
In-Reply-To: <87d331wbiv.fsf@ti.com>
References: <1342183715-13734-1-git-send-email-santosh.shilimkar@ti.com>
 <87d331wbiv.fsf@ti.com>
Message-ID: <CAMQu2gzzNjd7-5MOB27k-wCq+bKfzPmR1RebXYzzBTxsQvYqzg@mail.gmail.com>

On Wed, Aug 8, 2012 at 10:45 PM, Kevin Hilman <khilman at ti.com> wrote:
> Santosh Shilimkar <santosh.shilimkar at ti.com> writes:
>
>> OMAP4 sleep entry code even though itself don't use many CPU registers
>> makes call to the v7_flush_dcache_all() which uses them. Since
>> v7_flush_dcache_all() doesn't make use of stack, the caller must take
>> care of the stack frame. Otherwise it will lead to corrupted stack frame.
>>
>> Fix it by saving used registers.
>>
>> Reported-by: Grygorii Strashko <grygorii.strashko at ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Cc: Kevin Hilman <khilman at ti.com>
>
> Please add a brief comment in the code as well explaining why the
> additional registers are saved/restored.
>
Ok.
> After that, I'll add to my PM fixes queue for v3.6-rc.
>
Thanks.

Regards
Santosh


From m.szyprowski at samsung.com  Thu Aug  9 01:53:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 09 Aug 2012 07:53:25 +0200
Subject: [GIT PULL] DMA-mapping fixups for v3.6-rc2
Message-ID: <1344491605-19770-1-git-send-email-m.szyprowski@samsung.com>

Hi Linus,

I would like to ask for pulling a set of fixup patches for ARM
dma-mapping extensions merged in v3.6-rc1.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

with the top-most commit d9e0d149b5dcc2ef4688afc572b9906bcda941ef

  ARM: dma-mapping: fix incorrect freeing of atomic allocations

are available in the git repository at:

  git://git.linaro.org/people/mszyprowski/linux-dma-mapping.git fixes-for-linus-for-3.6-rc2

Thanks!

Best regards
Marek Szyprowski
Samsung Poland R&D Center


Patch summary:

Aaro Koskinen (2):
      ARM: dma-mapping: fix atomic allocation alignment
      ARM: dma-mapping: fix incorrect freeing of atomic allocations

Chris Brand (1):
      ARM: mm: fix MMU mapping of CMA regions

 arch/arm/mm/dma-mapping.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


From bryan.wu at canonical.com  Thu Aug  9 02:15:29 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu, 9 Aug 2012 14:15:29 +0800
Subject: [PATCH 10/10] leds: renesas: fix error handling
In-Reply-To: <1344461278-28245-11-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-11-git-send-email-arnd@arndb.de>
Message-ID: <CAK5ve-LXaA1xi5NDWTUxeVnr6DpDFv4LMzx0knHvO=1bzJO9jQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:27 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> bfe4c041 "leds: convert Renesas TPU LED driver to devm_kzalloc() and
> cleanup error exit path" introduced a possible case in which r_tpu_probe
> calls iounmap on a wild pointer. This changes the one case that was
> missed in the same way as the other error paths.
>
> Without this patch, building kota2_defconfig results in:
>
> drivers/leds/leds-renesas-tpu.c: In function 'r_tpu_probe':
> drivers/leds/leds-renesas-tpu.c:246:6: warning: 'ret' may be used uninitialized in this function [-Wuninitialized]
> drivers/leds/leds-renesas-tpu.c:308:17: warning: 'p' may be used uninitialized in this function [-Wuninitialized]
>

Thanks, Arnd. If you don't mind, I will apply this fixing through my led tree.

-Bryan

> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Bryan Wu <bryan.wu at canonical.com>
> Cc: Magnus Damm <damm at opensource.se>
>
> --- a/drivers/leds/leds-renesas-tpu.c
> +++ b/drivers/leds/leds-renesas-tpu.c
> @@ -247,7 +247,7 @@ static int __devinit r_tpu_probe(struct platform_device *pdev)
>
>         if (!cfg) {
>                 dev_err(&pdev->dev, "missing platform data\n");
> -               goto err0;
> +               return -ENODEV;
>         }
>
>         p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
> ---
>  drivers/leds/leds-renesas-tpu.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/leds/leds-renesas-tpu.c b/drivers/leds/leds-renesas-tpu.c
> index 9ee12c2..771ea06 100644
> --- a/drivers/leds/leds-renesas-tpu.c
> +++ b/drivers/leds/leds-renesas-tpu.c
> @@ -247,7 +247,7 @@ static int __devinit r_tpu_probe(struct platform_device *pdev)
>
>         if (!cfg) {
>                 dev_err(&pdev->dev, "missing platform data\n");
> -               goto err0;
> +               return -ENODEV;
>         }
>
>         p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
> --
> 1.7.10
>



-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer    +86.186-168-78255 Mobile
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From tony at atomide.com  Thu Aug  9 02:18:13 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 8 Aug 2012 23:18:13 -0700
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system
 control driver
In-Reply-To: <50227ED9.3010508@dev.rtsoft.ru>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com>
 <20120808141051.GG11011@atomide.com>
 <20120808143929.GJ11011@atomide.com>
 <50227ED9.3010508@dev.rtsoft.ru>
Message-ID: <20120809061813.GK11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120808 07:59]:
> On 08/08/2012 06:39 PM, Tony Lindgren wrote:
> 
> Yes, omap_type() is called very early , that is why I'm using early_initcall
> for omap_control_base initialization.
> 
> Do you mean following?:
> void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
> {
>     if (omap2_globals->ctrl)
>         omap2_ctrl_base = omap2_globals->ctrl;
> 
>     if (omap2_globals->ctrl_pad)
>         omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
> 
>     omap_control_base = omap2_ctrl_base;  // this line is added
> }

OK so we already have set_globals_control, but we're not using it..
No need for this line is added above.

Let's do the attached clean-up patch and just leave omap_control_base
out of the driver for now as it's not currently needed there.

If omap_control_base is needed in the driver, then we need to pass
it in the platform_data to the driver for the non-DT boot case, or
parse it from DT like you're doing.

Regards,

Tony


From: Tony Lindgren <tony at atomide.com>
Date: Wed, 8 Aug 2012 23:13:03 -0700
Subject: [PATCH] ARM: OMAP2+: Change omap_type() to use omap_ctrl_base_get()

We have the SoC specific ctrl_base already initialized in
set_globals.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -42,28 +42,20 @@ int omap_type(void)
 {
 	u32 val = 0;
 
-	if (cpu_is_omap24xx()) {
-		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-	} else if (soc_is_am33xx()) {
-		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
-	} else if (cpu_is_omap34xx()) {
-		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
-	} else if (cpu_is_omap44xx()) {
-		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
-	} else if (soc_is_omap54xx()) {
-		val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+	val = __raw_readl(omap_ctrl_base_get());
+	if (!val) {
+		pr_err("Cannot detect omap type!\n");
+		return 0;
+	}
+
+	if (soc_is_omap54xx()) {
 		val &= OMAP5_DEVICETYPE_MASK;
 		val >>= 6;
-		goto out;
 	} else {
-		pr_err("Cannot detect omap type!\n");
-		goto out;
+		val &= OMAP2_DEVICETYPE_MASK;
+		val >>= 8;
 	}
 
-	val &= OMAP2_DEVICETYPE_MASK;
-	val >>= 8;
-
-out:
 	return val;
 }
 EXPORT_SYMBOL(omap_type);


From ludovic.desroches at atmel.com  Thu Aug  9 02:29:15 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Thu, 9 Aug 2012 08:29:15 +0200
Subject: [PATCH] mmc: atmel-mci: not busy flag has also to be used for
 read operations
In-Reply-To: <87lihqxev6.fsf@octavius.laptop.org>
References: <1343122924-7799-1-git-send-email-ludovic.desroches@atmel.com>
 <87lihqxev6.fsf@octavius.laptop.org>
Message-ID: <502358BB.8010801@atmel.com>

Le 08/08/2012 05:05 AM, Chris Ball a ?crit :
> Hi,
>
> On Tue, Jul 24 2012, ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Even if the datasheet says that the not busy flag has to be used only for
>> write operations, it's false excepted for version lesser than v2xx.
>> Not waiting the not busy flag for read operations can cause the controller to
>> hang-up during the initialization of some SD cards.
>>
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> Cc: stable at vger.kernel.org
>>
>>
>> Hello,
>>
>> This is a fix for 3.5 and later.
>>
>> Due to the big changes into atmel-mci driver to support all atmel mci versions,
>> a bug was introduced.
>> With some SD cards (mainly micro) when using DMA, the controller hangs-up after
>> the first CMD6 command because the next command is sent too early.
>>
>> Regards
>>
>> Ludovic
>>
>>
>> ---
>>   drivers/mmc/host/atmel-mci.c |    6 +++++-
>>   1 files changed, 5 insertions(+), 1 deletions(-)
>
> Thanks.  I've applied this for mmc-next now, but please put your patch
> commentary *underneath* the "---" lines, so that it doesn't end up in
> the git history itself.  I've rewritten the commit message to be:

Sorry for this error.

Thanks

Ludovic

>
>
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Even if the datasheet says that the not busy flag has to be used only
> for write operations, it's false except for version lesser than v2xx.
>
> Not waiting on the not busy flag for read operations can cause the
> controller to hang-up during the initialization of some SD cards
> with DMA after the first CMD6 -- the next command is sent too early.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: stable <stable at vger.kernel.org> [3.5, 3.6]
> Signed-off-by: Chris Ball <cjb at laptop.org>
> ---
> <patch commentary can go here>
>
>   drivers/mmc/host/atmel-mci.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
>



From s.hauer at pengutronix.de  Thu Aug  9 02:32:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 9 Aug 2012 08:32:10 +0200
Subject: imx6q restart is broken
In-Reply-To: <20120809044131.GF14718@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809044131.GF14718@S2101-09.ap.freescale.net>
Message-ID: <20120809063209.GM1451@pengutronix.de>

On Thu, Aug 09, 2012 at 12:41:38PM +0800, Shawn Guo wrote:
> On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
> > 
> > - i think we should split imx_v6_v7_defconfig into v6_only and
> > v7_only, since when we use imx_v6_v7_defconfig, we will introduce
> > "-D__LINUX_ARM_ARCH__=6" unconditionally, this macro is OK for V6
> > platforms (imx3), but it is not good for V7 platforms (imx5, imx6).
> > lets grep "__LINUX_ARM_ARCH__" occurrence under the arch/arm, all
> > (#if __LINUX_ARM_ARCH__ == 6) and (#if __LINUX_ARM_ARCH__ >= 7)
> > occurrence will affect V7 platforms.
> 
> I just copied a few more people.  Let's hear their comments.

As a last resort we could split the defconfigs, but before we should
try to find a solution for this problem.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From ludovic.desroches at atmel.com  Thu Aug  9 02:32:04 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Thu, 9 Aug 2012 08:32:04 +0200
Subject: [PATCH RESEND v5 0/4] atmel-mci device tree support
In-Reply-To: <87hasexegg.fsf@octavius.laptop.org>
References: <1343136606-8874-1-git-send-email-ludovic.desroches@atmel.com>
 <87hasexegg.fsf@octavius.laptop.org>
Message-ID: <50235964.2080409@atmel.com>

Le 08/08/2012 05:14 AM, Chris Ball a ?crit :
> Hi,
>
> On Tue, Jul 24 2012, ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Hello,
>>
>> I resend this set of patches because patches 2, 3 and 4 were acked by
>> Jean-Christophe. Patch 1 was also acked by Jean-Christophe excepted for
>> cd-inverted property since it was redundant with gpio bindings.
>
> In future, it's helpful for me if you can add the Acked-by lines you
> receive into the patches when you resend them.  Thanks!
>

Ok.

>> I thought we were agree to go ahead since it was a common binding already
>> documented and it will concern all drivers.
>
> Agreed.  It's a documented core MMC binding, it's fine to use it.
>
>> Chris are you agree to take patch 1/4? Others patches may go to at91 tree,
>> isn't it?
>
> Yes, let's do that.  I've applied patch 1/4 to mmc-next for 3.7, and you
> can send the others via the at91 tree with the ACK that Arnd gave.

Thanks Chris.

Ludovic

>
> Thanks,
>
> - Chris.
>



From s.hauer at pengutronix.de  Thu Aug  9 02:32:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 9 Aug 2012 08:32:58 +0200
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Add Chipidea USB driver support
In-Reply-To: <50234E6F.1050406@de.bosch.com>
References: <1344463589-8115-1-git-send-email-festevam@gmail.com>
 <50234E6F.1050406@de.bosch.com>
Message-ID: <20120809063258.GN1451@pengutronix.de>

On Thu, Aug 09, 2012 at 07:45:19AM +0200, Dirk Behme wrote:
> On 09.08.2012 00:06, Fabio Estevam wrote:
> >From: Fabio Estevam <fabio.estevam at freescale.com>
> >
> >Add Chipidea USB driver support.
> >
> >Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> >---
> > arch/arm/configs/imx_v6_v7_defconfig |    3 +++
> > 1 files changed, 3 insertions(+), 0 deletions(-)
> >
> >diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> >index f725b96..5f6138d 100644
> >--- a/arch/arm/configs/imx_v6_v7_defconfig
> >+++ b/arch/arm/configs/imx_v6_v7_defconfig
> >@@ -179,6 +179,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
> > CONFIG_USB=y
> > CONFIG_USB_EHCI_HCD=y
> > CONFIG_USB_EHCI_MXC=y
> >+CONFIG_USB_CHIPIDEA=y
> >+CONFIG_USB_CHIPIDEA_HOST=y
> >+CONFIG_USB_MXS_PHY=y
> > CONFIG_USB_STORAGE=y
> > CONFIG_MMC=y
> > CONFIG_MMC_SDHCI=y
> 
> I'm not sure if we still need
> 
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_MXC=y
> 
> or if this can be removed? Besides this:

It is still needed for the non devicetree platforms.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From haojian.zhuang at gmail.com  Thu Aug  9 02:36:51 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 9 Aug 2012 14:36:51 +0800
Subject: [PATCH] ARM: mmp: add USB3.0 PHY support
In-Reply-To: <1344483203-17446-1-git-send-email-yuxu@marvell.com>
References: <1344483203-17446-1-git-send-email-yuxu@marvell.com>
Message-ID: <CAN1soZzWur7idY9jEwKTETo0NeZfSkycso44GtWKuftX1HT+9g@mail.gmail.com>

On Thu, Aug 9, 2012 at 11:33 AM, Yu Xu <yuxu at marvell.com> wrote:
> Add USB 3.0 PHY support.
>
> Signed-off-by: Yu Xu <yuxu at marvell.com>
> ---
>  arch/arm/mach-mmp/devices.c               |  227 +++++++++++++++++++++++++++++
>  arch/arm/mach-mmp/include/mach/regs-usb.h |   94 ++++++++++++
>  2 files changed, 321 insertions(+)
>

I hope that you can move USB PHY init into usb drivers. Since your
current implementation
would be add callback in platform data. It should be avoid since it's
a block of device tree
implementation.

Regards
Haojian


From tixy at yxit.co.uk  Thu Aug  9 02:59:37 2012
From: tixy at yxit.co.uk (Tixy)
Date: Thu, 09 Aug 2012 07:59:37 +0100
Subject: [PATCH 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208081248340.5231@xanadu.home>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208040045360.5231@xanadu.home> <50219C45.7030601@ti.com>
 <alpine.LFD.2.02.1208080106500.5231@xanadu.home> <5022673A.7060407@ti.com>
 <alpine.LFD.2.02.1208080948210.5231@xanadu.home>
 <20120808160517.GO18957@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1208081248340.5231@xanadu.home>
Message-ID: <1344495577.2852.4.camel@computer2.home>

On Wed, 2012-08-08 at 12:56 -0400, Nicolas Pitre wrote:
> On Wed, 8 Aug 2012, Russell King - ARM Linux wrote:
> > Done correctly, it shouldn't be a problem, but I wouldn't say that
> > arch/arm/kernel/kprobes-test*.c is done correctly.  It's seen quite
> > a number of patching attempts since it was introduced for various
> > problems, and I've seen quite a number of builds fail for various
> > reasons in this file (none which I could be bothered to investigate.)
<snip>
> >
> As for build failures with that test code, I'd suggest you simply drop a 
> note to Tixy who is normally very responsive.

Indeed. If there are build failures, I'm happy to investigate and fix.

-- 
Tixy



From s.hauer at pengutronix.de  Thu Aug  9 03:04:53 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 9 Aug 2012 09:04:53 +0200
Subject: [PATCH] ARM: dts: imx: Move SDMA firmware to SoC dtsi file
In-Reply-To: <1344436087-5612-1-git-send-email-festevam@gmail.com>
References: <1344436087-5612-1-git-send-email-festevam@gmail.com>
Message-ID: <20120809070453.GS1451@pengutronix.de>

On Wed, Aug 08, 2012 at 11:28:07AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Instead of adding sdma-ram-script-name into each board dts file, move 
> it to the SoC dtsi file instead.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

It's good to have a sane default for it. A board could still overwrite
the property should it have to.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

> ---
>  arch/arm/boot/dts/imx51-babbage.dts |    4 ----
>  arch/arm/boot/dts/imx51.dtsi        |    1 +
>  arch/arm/boot/dts/imx53-ard.dts     |    6 ------
>  arch/arm/boot/dts/imx53-evk.dts     |    4 ----
>  arch/arm/boot/dts/imx53-qsb.dts     |    4 ----
>  arch/arm/boot/dts/imx53-smd.dts     |    4 ----
>  arch/arm/boot/dts/imx53.dtsi        |    1 +
>  7 files changed, 2 insertions(+), 22 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
> index de065b5..46d4c93 100644
> --- a/arch/arm/boot/dts/imx51-babbage.dts
> +++ b/arch/arm/boot/dts/imx51-babbage.dts
> @@ -189,10 +189,6 @@
>  		};
>  
>  		aips at 80000000 {	/* aips-2 */
> -			sdma at 83fb0000 {
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
> -			};
> -
>  			i2c at 83fc4000 { /* I2C2 */
>  				status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
> index aaa0c0a..0bb5958 100644
> --- a/arch/arm/boot/dts/imx51.dtsi
> +++ b/arch/arm/boot/dts/imx51.dtsi
> @@ -219,6 +219,7 @@
>  				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
>  				reg = <0x83fb0000 0x4000>;
>  				interrupts = <6>;
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
>  			};
>  
>  			cspi at 83fc0000 {
> diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
> index 5b8eafc..dbe0353 100644
> --- a/arch/arm/boot/dts/imx53-ard.dts
> +++ b/arch/arm/boot/dts/imx53-ard.dts
> @@ -44,12 +44,6 @@
>  				status = "okay";
>  			};
>  		};
> -
> -		aips at 60000000 {	/* AIPS2 */
> -			sdma at 63fb0000 {
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
> -			};
> -		};
>  	};
>  
>  	eim-cs1 at f4000000 {
> diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
> index 9c79803..8e72f68 100644
> --- a/arch/arm/boot/dts/imx53-evk.dts
> +++ b/arch/arm/boot/dts/imx53-evk.dts
> @@ -77,10 +77,6 @@
>  		};
>  
>  		aips at 60000000 {	/* AIPS2 */
> -			sdma at 63fb0000 {
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
> -			};
> -
>  			i2c at 63fc4000 { /* I2C2 */
>  				status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
> index 2d803a9..7153aa0 100644
> --- a/arch/arm/boot/dts/imx53-qsb.dts
> +++ b/arch/arm/boot/dts/imx53-qsb.dts
> @@ -56,10 +56,6 @@
>  		};
>  
>  		aips at 60000000 {	/* AIPS2 */
> -			sdma at 63fb0000 {
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
> -			};
> -
>  			i2c at 63fc4000 { /* I2C2 */
>  				status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
> index 0809102..9baef00 100644
> --- a/arch/arm/boot/dts/imx53-smd.dts
> +++ b/arch/arm/boot/dts/imx53-smd.dts
> @@ -96,10 +96,6 @@
>  		};
>  
>  		aips at 60000000 {	/* AIPS2 */
> -			sdma at 63fb0000 {
> -				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
> -			};
> -
>  			i2c at 63fc4000 { /* I2C2 */
>  				status = "okay";
>  
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index dc00c62..81abfad 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -277,6 +277,7 @@
>  				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
>  				reg = <0x63fb0000 0x4000>;
>  				interrupts = <6>;
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
>  			};
>  
>  			cspi at 63fc0000 {
> -- 
> 1.7.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From peter.ujfalusi at ti.com  Thu Aug  9 03:05:50 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 09 Aug 2012 10:05:50 +0300
Subject: [alsa-devel] [PATCH 07/11] ASoC: omap-mcbsp: Sidetone: Use SIDLE
 bits in SYSCONFIG register to select noidle mode
In-Reply-To: <5022E46A.4010909@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-8-git-send-email-peter.ujfalusi@ti.com>
 <5022E46A.4010909@ti.com>
Message-ID: <5023614E.3030308@ti.com>

Hi Ricardo,

On 08/09/2012 01:12 AM, Ricardo Neri wrote:
> Is this another case in which it is required to change the idle-mode on a
> per-use-case basis? In the past I was trying to do the same with HDMI [1]. In
> that case it was decided to add the HWMOD_SWSUP_SIDLE to hwmod data with the
> drawback of using no-idle/force-idle rather than smart-idle[2][3].

This only concerns use case on OMAP3 when the sidetone is in use. In all other
use cases we want to use smart-idle (music playback, FM TX/RX, etc).
The main problem here is that the sidetone block have broken sidle line, it
can not prevent McBSP iclk to be gated.
The sidetone block is using the ICLK of the McBSP port (OMAP3 has ST block
attached to McBSP2 and 3 ports only).


> [1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg60226.html
> [2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70463.html
> [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70653.html
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
>> ---
>>   sound/soc/omap/mcbsp.c |   18 ++++++++++++++----
>>   sound/soc/omap/mcbsp.h |    1 +
>>   2 files changed, 15 insertions(+), 4 deletions(-)
>>
>> diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
>> index c870023..e008898 100644
>> --- a/sound/soc/omap/mcbsp.c
>> +++ b/sound/soc/omap/mcbsp.c
>> @@ -257,8 +257,15 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
>>   {
>>       unsigned int w;
>>
>> -    if (mcbsp->pdata->enable_st_clock)
>> -        mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
>> +    /*
>> +     * Sidetone uses McBSP ICLK - which must not idle when sidetones
>> +     * are enabled or sidetones start sounding ugly.
>> +     */
>> +    w = MCBSP_READ(mcbsp, SYSCON);
>> +    mcbsp->st_data->mcbsp_sidle = (w >> 3) & 0x3;
>> +    w &= ~SIDLEMODE(0x3);
>> +    w |= SIDLEMODE(0x1);
>> +    MCBSP_WRITE(mcbsp, SYSCON, w);
> 
> Wouldn't this create a mismatch between the SYSCONFIG register and McBSP
> omap_hwmod._sysc_cache?

We modify the bits runtime (if the ST is enabled), after the hwmod already
configured the McBSP port to s-idle. We change the McBSP port's s-idle mode
back to it's original before pm_runtime_put().

Previously we did the same thing in PRCM level which was as ugly as this
workaround with the penalty of a callback function to mach-omap2 since we can
only got access to PRCM register API there.

> Perhaps this could be done with a future omap_hwmod API?

But there's no such an API and I'm not aware any ongoing effort to have one.
Still the issue mostly remains since we need to modify other block's s-idle
mode. If sidetone block is enabled we need to change the McBSP port's s-idle
mode to no-idle.

In most of the use cases the McBSP need to be in smart-idle mode since it
provides significant power saving.

-- 
P?ter


From rnayak at ti.com  Thu Aug  9 03:08:20 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 9 Aug 2012 12:38:20 +0530
Subject: [PATCH v2 0/2] OMAP cpufreq fixes
Message-ID: <1344496102-24451-1-git-send-email-rnayak@ti.com>

Changes in v2:
Fixed the handling of freq_table_users in Patch 1/2 as
suggested by Santosh. Patch 2/2 is unchanged.

Hi Kevin,

While testing cpufreq on 3.6-rc1, I noticed strange issues on OMAP4,
like a lockup when booting with 'performace' governer as default,
and crashes when using 'usespace' (which booted up) and switching
to higher OPPs.
It took me a while to realise I was using a 4460 device. The OPPs
registered though seemed to be for 4430 and hence were causing
issues on the 4460 device. 

This series basically avoids registering the 4430 OPPs on other
varients like 4460 and 4470 (and hence causing random issues)
and also fixes a subsequent bug uncovered by doing this in
OMAP cpufreq driver.

regards,
Rajendra 

Rajendra Nayak (2):
  cpufreq: OMAP: Handle missing frequency table on SMP systems
  ARM: OMAP4: Register the OPP table only for 4430 device

 arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
 drivers/cpufreq/omap-cpufreq.c     |    4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

-- 
1.7.9.5



From rnayak at ti.com  Thu Aug  9 03:08:21 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 9 Aug 2012 12:38:21 +0530
Subject: [PATCH v2 1/2] cpufreq: OMAP: Handle missing frequency table on SMP
 systems
In-Reply-To: <1344496102-24451-1-git-send-email-rnayak@ti.com>
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
Message-ID: <1344496102-24451-2-git-send-email-rnayak@ti.com>

On OMAP4, if the first CPU fails to get a valid frequency table (this
could happen if the platform does not register any OPP table), the
subsequent CPU instances end up dealing with a NULL freq_table and
crash.

Check for an already existing freq_table, before trying to create one,
and increment the freq_table_users only if the table is sucessfully
created.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: <linux-pm at vger.kernel.org>
---
 drivers/cpufreq/omap-cpufreq.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 17fa04d..b47034e 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 
 	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
 
-	if (atomic_inc_return(&freq_table_users) == 1)
+	if (!freq_table)
 		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
 
 	if (result) {
@@ -227,6 +227,8 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 		goto fail_ck;
 	}
 
+	atomic_inc_return(&freq_table_users);
+
 	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
 	if (result)
 		goto fail_table;
-- 
1.7.9.5



From rnayak at ti.com  Thu Aug  9 03:08:22 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 9 Aug 2012 12:38:22 +0530
Subject: [PATCH v2 2/2] ARM: OMAP4: Register the OPP table only for 4430 device
In-Reply-To: <1344496102-24451-1-git-send-email-rnayak@ti.com>
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
Message-ID: <1344496102-24451-3-git-send-email-rnayak@ti.com>

The 4430 OPP table was being registered for all other OMAP4 variants
too, like 4460 and 4470 causing issues with cpufreq driver
enabled. 4460 and 4470 devices have different OPPs as compared to
4430, and they should be populated seperately. As long as that
happens, let the OPP table registeration happen only on 4430 device.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba2..c95415d 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
 {
 	int r = -ENODEV;
 
-	if (!cpu_is_omap44xx())
+	if (!cpu_is_omap443x())
 		return r;
 
 	r = omap_init_opp_table(omap44xx_opp_def_list,
-- 
1.7.9.5



From haojian.zhuang at gmail.com  Thu Aug  9 03:10:40 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 9 Aug 2012 15:10:40 +0800
Subject: [Openpxa-users] pxa3x0 smart panel interface
In-Reply-To: <201208082157.22064.marek.vasut@gmail.com>
References: <20120806152551.4ec2cad0@laptoppieter>
 <201208082157.22064.marek.vasut@gmail.com>
Message-ID: <CAN1soZyf5m+n7F+=jiKhqCjEuxdzESq9Cft8oDUhD3t4UN75sA@mail.gmail.com>

On Thu, Aug 9, 2012 at 3:57 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dear pieterg,
>
> CCing linux-arm-kernel and Haojian
>
>> Hi all,
>>
>> Does any of you have experience with interfacing smart lcd panels, with
>> a pxa3x0?
>>

We didn't try to connect smart lcd panel with pxa300 or pxa310.

>> I'm interfacing an ILI9327DS smart panel controller, all commands
>> are handled correctly, however the SMART_CMD_WRITE_FRAME command (which
>> sends out all frame data) seems to produce an invalid number of output
>> bytes every now and then.
>> This results in a shifted display, every 10-100 updates (immediately
>> corrected by the next update)

Do you mean that you observe this behavior on oscilloscope? Are you
using LCD interface
or SMEM interface?

>>
>> The strange thing is that this does not occur with a pxa300, but it
>> occurs with the pxa310 and pxa320.
>> However running the 310/320 with the same ACCR as I'm running the 300
>> does not 'fix' it.

Do you change frequency while you are testing this smart panel?

>> And I'm not sure it is even timing related, I've tried to configure
>> huge smart timing delay parameters, but the results remain the same.
>> (in fact I can even lower the parameters to way under the
>> controller specs, and the issue does not get worse).
>> I've also played with the drive strength of the LCD lines, which also
>> does not have an effect on the issue.
>>
>> I do not think this is a controller bug, because before this ILI9327DS
>> controller, we had a display with a different controller chip, with
>> which I experienced the same thing, however at that time even with the
>> pxa300.
>> We switched to the ILI9327DS (for a different reason), and I was glad to
>> find that it worked fine with the pxa300.
>> Till I discovered it had the same issues, but then only with a
>> pxa310/320.
LCD controller between pxa300 and pxa310 is nearly same.


From rnayak at ti.com  Thu Aug  9 03:23:28 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 09 Aug 2012 12:53:28 +0530
Subject: [PATCH 2/2] ARM: OMAP4: Register the OPP table only for 4430
 device
In-Reply-To: <87628twbd3.fsf@ti.com>
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-3-git-send-email-rnayak@ti.com> <87628twbd3.fsf@ti.com>
Message-ID: <50236570.6030301@ti.com>

Hi Kevin,

On Wednesday 08 August 2012 10:48 PM, Kevin Hilman wrote:
>> The 4430 OPP table was being registered for all other OMAP4 variants
>> >  too, like 4460 and 4470 causing issues with cpufreq driver
>> >  enabled. 4460 and 4470 devices have different OPPs as compared to
>> >  4430, and they should be populated seperately. As long as that
>> >  happens, let the OPP table registeration happen only on 4430 device.
>> >
>> >  Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> Thanks, adding to PM fixes for v3.6-rc (branch: for_3.6/fixes/pm)

I just posted a v2 of this series addressing the issues raised by
Santosh on Patch 1/2. The problem with taking just $subject fix (or
taking it before Patch 1/2) is that you would hit the issue fixed
by the Patch 1/2 and cause a crash on non-4430 based OMAP4 devices with
cpufreq enabled.

regards,
Rajendra



From santosh.shilimkar at ti.com  Thu Aug  9 03:23:33 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 9 Aug 2012 12:53:33 +0530
Subject: [PATCH v2 2/2] ARM: OMAP4: Register the OPP table only for 4430
 device
In-Reply-To: <1344496102-24451-3-git-send-email-rnayak@ti.com>
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
 <1344496102-24451-3-git-send-email-rnayak@ti.com>
Message-ID: <CAMQu2gxq2x=Qrr2-bpkDdAu-KVuMBZiZnhv-fzUnv2q02667Jg@mail.gmail.com>

On Thu, Aug 9, 2012 at 12:38 PM, Rajendra Nayak <rnayak at ti.com> wrote:
> The 4430 OPP table was being registered for all other OMAP4 variants
> too, like 4460 and 4470 causing issues with cpufreq driver
> enabled. 4460 and 4470 devices have different OPPs as compared to
> 4430, and they should be populated seperately. As long as that
> happens, let the OPP table registeration happen only on 4430 device.
>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From arnd at arndb.de  Thu Aug  9 03:34:03 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 Aug 2012 07:34:03 +0000
Subject: [PATCH 10/10] leds: renesas: fix error handling
In-Reply-To: <CAK5ve-LXaA1xi5NDWTUxeVnr6DpDFv4LMzx0knHvO=1bzJO9jQ@mail.gmail.com>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-11-git-send-email-arnd@arndb.de>
 <CAK5ve-LXaA1xi5NDWTUxeVnr6DpDFv4LMzx0knHvO=1bzJO9jQ@mail.gmail.com>
Message-ID: <201208090734.04087.arnd@arndb.de>

On Thursday 09 August 2012, Bryan Wu wrote:
> 
> On Thu, Aug 9, 2012 at 5:27 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > bfe4c041 "leds: convert Renesas TPU LED driver to devm_kzalloc() and
> > cleanup error exit path" introduced a possible case in which r_tpu_probe
> > calls iounmap on a wild pointer. This changes the one case that was
> > missed in the same way as the other error paths.
> >
> > Without this patch, building kota2_defconfig results in:
> >
> > drivers/leds/leds-renesas-tpu.c: In function 'r_tpu_probe':
> > drivers/leds/leds-renesas-tpu.c:246:6: warning: 'ret' may be used uninitialized in this function [-Wuninitialized]
> > drivers/leds/leds-renesas-tpu.c:308:17: warning: 'p' may be used uninitialized in this function [-Wuninitialized]
> >
> 
> Thanks, Arnd. If you don't mind, I will apply this fixing through my led tree.
> 

Ok, excellent. One less patch for me to worry about. Dropped from my tree now.

	Arnd


From ijc at hellion.org.uk  Thu Aug  9 03:47:57 2012
From: ijc at hellion.org.uk (Ian Campbell)
Date: Thu, 09 Aug 2012 08:47:57 +0100
Subject: dreamplug spi partitions
Message-ID: <1344498477.11783.38.camel@dagon.hellion.org.uk>

Hi all,

I've been using "fw_printenv" and "fw_setenv" from the u-boot-tools
package on my DreamPlug which work fine with this /etc/fw_env.config:
        # Configuration file for fw_(printenv/saveenv) utility.
        # Up to two entries are valid, in this case the redundant
        # environment sector is assumed present.
        # MTD device name       Device offset   Env. size       Flash sector size
        /dev/mtd1               0x00000000      0x00001000      0x00001000
        
This corresponds roughly, but not exactly, with:
        # cat /proc/mtd 
        dev:    size   erasesize  name
        mtd0: 00080000 00001000 "u-boot"
        mtd1: 00010000 00001000 "u-boot env"
        mtd2: 00010000 00001000 "dtb"

But notice how "Env. size" and mtd1's size don't match -- if I use
0x10000 in fw_env.cfg then the tools don't work (checksums don't match).

This map appears to be hardcoded in u-boot & the kernel, u-boot has:
        #define CONFIG_ENV_SECT_SIZE            0x10000 /* 64k */
        #define CONFIG_ENV_SIZE                 0x1000  /* 4k */
        #define CONFIG_ENV_ADDR                 0x100000
        #define CONFIG_ENV_OFFSET               0x100000 /* env starts here */
        
(this is upstream u-boot, I've not checked the one shipped by the
factory)

The kernel has:
        struct mtd_partition dreamplug_partitions[] = {
                {
                        .name   = "u-boot",
                        .size   = SZ_512K,
                        .offset = 0,
                },
                {
                        .name   = "u-boot env",
                        .size   = SZ_64K,
                        .offset = SZ_512K + SZ_512K,
                },
                {
                        .name   = "dtb",
                        .size   = SZ_64K,
                        .offset = SZ_512K + SZ_512K + SZ_512K,
                },
        };

However u-boot has a comment next to CONFIG_ENV_SIZE about rounding the
size to a sector which "sf probe" under u-boot reports as being 64K
(consistent with CONFIG_ENV_SECT_SIZE). However /proc/mtd reports it as
4K. So I'm totally confused about who is wrong, other than the fact that
using the u-boot numbers in /etc/fw_env.config works...

Even then I'm not sure what the rest of the layout should look like. The
kernel's partitioning scheme seems to leave an awful lot of holes and
the dtb partition seems to be entirely a kernel thing.

I'd be happy to make a patch, I just have no idea what I would write in
it ;-)

Cheers,
Ian.
-- 
Ian Campbell


When some people discover the truth, they just can't understand why
everybody isn't eager to hear it.
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From linux at arm.linux.org.uk  Thu Aug  9 03:47:54 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 08:47:54 +0100
Subject: [PATCH 09/10] ARM: rpc: Fix building RiscPC
In-Reply-To: <1344461278-28245-10-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-10-git-send-email-arnd@arndb.de>
Message-ID: <20120809074754.GP18957@n2100.arm.linux.org.uk>

On Wed, Aug 08, 2012 at 11:27:57PM +0200, Arnd Bergmann wrote:
> ARMv3 support was removed in 357c9c1f07 "ARM: Remove support for ARMv3
> ARM610 and ARM710 CPUs", which explicitly left parts of the CPU32v3
> support in place for building RiscPC. However, this does not actually
> build in my test setup.
> 
> This is probably not the right solution, but maybe someone has a better
> idea for how to deal with this.

This isn't the right solution.  The RiscPC bus does not support half-word
load/stores, so we must continue to build that target for the 32v3
architecture (which is why I carefully left that stuff behind.)

The mistake is in what I did with arch/arm/lib - the armv3 code in there
needs to be resurected instead.


From hs at denx.de  Thu Aug  9 03:52:40 2012
From: hs at denx.de (Heiko Schocher)
Date: Thu, 09 Aug 2012 09:52:40 +0200
Subject: [PATCH v6 7/7] ARM: davinci: add support for the am1808 based
 enbw_cmc board
In-Reply-To: <5022A367.1070903@ti.com>
References: <1341492608-20597-1-git-send-email-hs@denx.de>
 <5022A367.1070903@ti.com>
Message-ID: <50236C48.3090108@denx.de>

Hello Nori,

On 08.08.2012 19:35, Sekhar Nori wrote:
> Hi Heiko,
>
> On 7/5/2012 6:20 PM, Heiko Schocher wrote:
>> - AM1808 based board
>> - 64 MiB DDR ram
>> - 2 MiB Nor flash
>> - 128 MiB NAND flash
>> - use internal RTC
>> - I2C support
>> - hwmon lm75 support
>> - UBI/UBIFS support
>> - MMC support
>> - USB OTG support
>>
>> Signed-off-by: Heiko Schocher<hs at denx.de>
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: devicetree-discuss at lists.ozlabs.org
>> Cc: davinci-linux-open-source at linux.davincidsp.com
>> Cc: linux-mtd at lists.infradead.org
>> Cc: linux-i2c at vger.kernel.org
>> Cc: netdev at vger.kernel.org
>> Cc: David Woodhouse<dwmw2 at infradead.org>
>> Cc: Ben Dooks<ben-linux at fluff.org>
>> Cc: Wolfram Sang<w.sang at pengutronix.de>
>> Cc: Sekhar Nori<nsekhar at ti.com>
>> Cc: Kevin Hilman<khilman at ti.com>
>> Cc: Wolfgang Denk<wd at denx.de>
>> Cc: Scott Wood<scottwood at freescale.com>
>> Cc: Sylwester Nawrocki<s.nawrocki at samsung.com>
>>
>> ---
>> - post this board support with USB support, even though
>>    USB is only working with the 10 ms "workaround", posted here:
>>    http://comments.gmane.org/gmane.linux.usb.general/54505
>>    I see this issue also on the AM1808 TMDXEXP1808L evalboard.
>> - MMC and USB are not using OF support yet, ideas how to port
>>    this are welcome. I need for USB and MMC boards board
>>    specific callbacks, how to solve this with OF support?
>>
>> - changes for v2:
>>    - changes in the nand node due to comments from Scott Wood:
>>      - add "ti,davinci-" prefix
>>      - Dashes are preferred to underscores
>>      - rename "nandflash" to "nand"
>>      - introduce new "ti,davinci" specific properties for setting
>>        up ecc_mode, ecc_bits, options and bbt options, instead
>>        using linux defines
>>    - changes for i2c due to comments from Sylwester Nawrocki:
>>      - use "cell-index" instead "id"
>>      - OF_DEV_AUXDATA in the machine code, instead pre-define
>>        platform device name
>>    - add comment from Grant Likely for i2c:
>>      - removed "id" resp. "cell-index" completely
>>      - fixed documentation
>>      - use of_match_ptr()
>>      - use devm_kzalloc() for allocating plattform data mem
>>      - fixed a whitespace issue
>>    - add net comments from Grant Likely:
>>      - add prefix "ti,davinci-" to davinci specific property names
>>      - remove version property
>>      - use compatible name "ti,davinci-dm6460-emac"
>>    - add comment from Grant Likely:
>>      - rename compatible node
>>      - do not use cell-index
>>      - CONFIG_OF required for this board
>>      TODO:
>>      - create a generic board support file, as I got no
>>        answer to my ping to grant, maybe this could be done
>>        in a second step?
>> - changes for v3:
>>    - add comments from Sergei Shtylyov:
>>      - rename compatible" prop to "ti,cp_intc"
>>      - cp_intc_init now used for Interrupt controller init
>> - changes for v4:
>>    add comment from Nori Sekhar:
>>    - rename davinci emac compatible property to "ti,davinci-dm6467-emac"
>>    - remove "pinmux-handle" property as discussed here:
>>      http://www.spinics.net/lists/arm-kernel/msg175701.html
>>      with Nori Sekhar
>>
>> - changes for v5:
>>    add comments from Grant Likely:
>>    - rename compatible" prop to "ti,cp-intc"
>>
>> - changes for v6:
>>    rework this patch, as patch
>>    ARM: davinci: cp_intc: Add OF support for TI interrupt controller
>>    was changed from Nori Sekhar on Jul 03, 2012; 9:16pm
>>    Changes therefore in this patch:
>>
>>    Call of_irq_init() in the generic DT board file and not in the
>>    interrupt controller code. See arch/arm/mach-at91/board-dt.c or
>>    arch/arm/mach-omap2/board-generic.c for examples.
>>
>>    At this point the question raises, if we should rename this
>>    board port from arch/arm/mach-davinci/enbw_cmc.c to
>>    arch/arm/mach-davinci/board-dt.c ? Also the defconfig to
>>    davinci_of_defconfig ... ? The USB and MMC callbacks are
>>    currently board specific, but if other boards come in,
>>    that could be easily adapted for their needs ...
>>
>>   arch/arm/boot/dts/enbw_cmc.dts                  |  183 +++++++++++
>>   arch/arm/configs/enbw_cmc_defconfig             |  126 ++++++++
>>   arch/arm/mach-davinci/Kconfig                   |    9 +
>>   arch/arm/mach-davinci/Makefile                  |    1 +
>>   arch/arm/mach-davinci/board-enbw-cmc.c          |  385 +++++++++++++++++++++++
>>   arch/arm/mach-davinci/include/mach/uncompress.h |    1 +
>>   6 files changed, 705 insertions(+), 0 deletions(-)
>>   create mode 100644 arch/arm/boot/dts/enbw_cmc.dts
>>   create mode 100644 arch/arm/configs/enbw_cmc_defconfig
>>   create mode 100644 arch/arm/mach-davinci/board-enbw-cmc.c
>
> With the move to DT, we are not going to add more board specific files
> and defconfigs. I am working on adding a generic dt board file for DA850
> (similar to what has been done for imx). That file is not going to do
> any platform device registrations. If you are OK with it, I will add the
> dts file for enbw_cmc board in the patch series I am planning to post.

I am fine with that. If you have a working version, you can sent it
(if you want) to me, so I can test it on the enbw_cmc board.

> Things like USB and MMC/SD will need to be converted to DT before they
> can be supported on new boards.

Ok, understood.

bye,
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


From catalin.marinas at arm.com  Thu Aug  9 04:06:48 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 9 Aug 2012 09:06:48 +0100
Subject: imx6q restart is broken
In-Reply-To: <20120809044131.GF14718@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809044131.GF14718@S2101-09.ap.freescale.net>
Message-ID: <20120809080648.GB14102@arm.com>

On Thu, Aug 09, 2012 at 05:41:38AM +0100, Shawn Guo wrote:
> On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
> > Dirk Behme wrote:
> > >On 08.08.2012 12:18, Shawn Guo wrote:
> > >>Thanks Dirk for reporting that imx6q restart (reboot command) is broken.
> > >>
> > >>I tracked down the issue a little bit and found imx6q_restart hangs
> > >>on the of_iomap/ioremap call. The following change, moving the call
> > >>somewhere else than imx6q_restart, will just fix the problem.
> > >>
> > >>Does that mean ioremap call is not allowed in platform restart hook?
> > >>I'm not sure about that, because I found it works just fine if I build
> > >>imx_v6_v7_defconfig with V6 (imx3) platforms excluded (IOW, build a V7
> > >>only kernel - imx5 and imx6), which is the case how I tested imx6q
> > >>restart feature when I was adding it.
> > >>
> > >>To summarize, the imx6q_restart hangs at ioremap call on a V6 + V7
> > >>kernel, while it works fine on a V7 only image. I need some help to
> > >>understand that.
> > >
> > >Some additional information from my debugging:
> > >
> > >a) Having a JTAG debugger attached to the i.MX6 SabreLite board I
> > >use (kernel built with imx_v6_v7_defconfig) the reboot does work.
> > >No hang. This does mean I can't debug the reboot hang with a JTAG
> > >debugger. Therefore I added some printk debugging:
> > >
> > >b) Adding some printk statements [1] in the of_iomap/ioremap call,
> > >it looks to me that the system hangs in
> > >
> > >of_iomap() -> ... -> set_pte_at() -> set_pte_ext() /
> > >cpu_v7_set_pte_ext() <= hang
> > >
> > I noticed this problem several weeks ago, and did some debug, what i
> > found is following:
> > 
> Thanks for these great findings.  I also just tracked it down to that
> cpu_v7_set_pte_ext hangs on
> 
> 	mcr   p15, 0, r0, c7, c10, 1          @ flush_pte
> 
> > - at the last stage of reset, all non-boot cpus will call
> > ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb()
> > for V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10,
> > 5")
> > 
> > - the boot cpu will call cpu_v7_set_pte_ext() in the
> > proc-v7-2level.S, at the end of this function, boot cpu will call
> > flush_pte (mcr p15, 0, r0, c7, c10, 1), after executing this
> > function, the system will hang. That is to say, all non-boot cpus
> > repeatedly call ("mcr p15, 0, %0, c7, c10, 5"), if boot cpu call
> > flush_pte (mcr p15, 0, r0, c7, c10, 1), the system will hang, this
> > occurs on the cortexa9 r2p10 cpus (freescale i.MX6Q), i don't know
> > the root cause for this problem, but if we split imx_v6_v7_defconfig
> > into v7_only and use v7_only to build kernel image for imx6q, this
> > problem will disappear, since the cpu_relax() will be defined to
> > barrier().

Does this work if you always define cpu_relax() to smp_mb() (even on
ARMv7) and compile the kernel to v7-only? In this case, the smp_mb()
would use the DMB instruction rather than the CP15 equivalent. It's not
a solution, just trying to understand the problem better.

Thanks.

-- 
Catalin


From shawn.guo at linaro.org  Thu Aug  9 04:18:35 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 16:18:35 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120809080648.GB14102@arm.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809044131.GF14718@S2101-09.ap.freescale.net>
 <20120809080648.GB14102@arm.com>
Message-ID: <20120809081833.GA15492@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 09:06:48AM +0100, Catalin Marinas wrote:
> Does this work if you always define cpu_relax() to smp_mb() (even on
> ARMv7) and compile the kernel to v7-only? In this case, the smp_mb()
> would use the DMB instruction rather than the CP15 equivalent. It's not
> a solution, just trying to understand the problem better.
> 
This is a test I already did a couple of hours ago.  No, it does not
work.  The kernel hangs at the same place.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Thu Aug  9 04:39:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 16:39:13 +0800
Subject: [PATCH] ARM: dts: imx: Move SDMA firmware to SoC dtsi file
In-Reply-To: <1344436087-5612-1-git-send-email-festevam@gmail.com>
References: <1344436087-5612-1-git-send-email-festevam@gmail.com>
Message-ID: <20120809083912.GB15492@S2101-09.ap.freescale.net>

On Wed, Aug 08, 2012 at 11:28:07AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Instead of adding sdma-ram-script-name into each board dts file, move 
> it to the SoC dtsi file instead.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

-- 
Regards,
Shawn



From burman.yan at gmail.com  Thu Aug  9 04:54:40 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Thu, 9 Aug 2012 11:54:40 +0300
Subject: [PATCH] ARM: ep93xx: clockevent support
In-Reply-To: <5021122C.3000503@gmail.com>
References: <1344338474.18237.6.camel@localhost> <5021122C.3000503@gmail.com>
Message-ID: <CANapsLQ6kCUN5UoaA3xejm24SGxCKmZEFgmR_+r7N-=DPz0TVA@mail.gmail.com>

On 8/7/12, Ryan Mallon <rmallon at gmail.com> wrote:
> On 07/08/12 21:21, Yan Burman wrote:
>
>> ARM: ep93xx: clockevent support
>> I have ported to 3.6-rc1 and slightly modified a previous patch for
>> clockevent support for the ep93xx.
>> The porting mainly consists of sched_clock support.
>> Tested on 9302 based board.
>> From: Ahmed Ammar <aammar <at> edge-techno.com>
>> Signed-off-by: Yan Burman <burman.yan at gmail.com>
>
>
> Hi Yan, some comments below.
>
> ~Ryan
>
>> +	case CLOCK_EVT_MODE_ONESHOT:
>> +		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
>> +		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
>> +		break;
>> +
>> +	case CLOCK_EVT_MODE_SHUTDOWN:
>> +	case CLOCK_EVT_MODE_UNUSED:
>> +	case CLOCK_EVT_MODE_RESUME:
>> +		return;
>
>
> These cases can be removed.
>

This case is something that is present in most (if not all) other architectures.
I don't mind removing it, but it will have to be replaced with:
default:
     ;

Since GCC produces warnings otherwise.

Other than that I am going to wait a while more for more comments if
somebody has them,
and post a new version with style fixes as well as switch to
drivers/clocksource/mmio.c usage.

Regards,
Yan


From arnd at arndb.de  Thu Aug  9 04:00:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 Aug 2012 08:00:17 +0000
Subject: [PATCH v2 06/10] ARM: davinci: don't use broken ntosd2_init_i2c
In-Reply-To: <1344461278-28245-7-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-7-git-send-email-arnd@arndb.de>
Message-ID: <201208090800.18321.arnd@arndb.de>

On second thought, there is probably no use in keeping the broken function
around, and we can just kill it off. If someone wants to add an i2c
device to the bus, they can always add the init code back as well.

8<-----
Subject: ARM: davinci: don't use broken ntosd2_init_i2c

ntosd2_init_i2c walks the ntosd2_i2c_info array, which it expects to
be populated with at least one member. gcc correctly warns about
the out-of-bounds access here.

Since this can not possibly work, it's better to disable i2c
support entirely on this board.

Without this patch, building davinci_all_defconfig results in:

arch/arm/mach-davinci/board-neuros-osd2.c: In function 'davinci_ntosd2_init':
arch/arm/mach-davinci/board-neuros-osd2.c:187:20: warning: array subscript is above array bounds [-Warray-bounds]

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Andrey Porodko <panda at chelcom.ru>

diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5de69f2..f6b9fc7 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -162,38 +162,6 @@ static void __init davinci_ntosd2_map_io(void)
 	dm644x_init();
 }
 
-/*
- I2C initialization
-*/
-static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
-	.bus_freq	= 20 /* kHz */,
-	.bus_delay	= 100 /* usec */,
-};
-
-static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
-};
-
-static	int ntosd2_init_i2c(void)
-{
-	int	status;
-
-	davinci_init_i2c(&ntosd2_i2c_pdata);
-	status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
-	if (status == 0) {
-		status = gpio_direction_input(NTOSD2_MSP430_IRQ);
-		if (status == 0) {
-			status = gpio_to_irq(NTOSD2_MSP430_IRQ);
-			if (status > 0) {
-				ntosd2_i2c_info[0].irq = status;
-				i2c_register_board_info(1,
-					ntosd2_i2c_info,
-					ARRAY_SIZE(ntosd2_i2c_info));
-			}
-		}
-	}
-	return status;
-}
-
 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
 	.wires		= 4,
 	.version	= MMC_CTLR_VERSION_1
@@ -218,7 +186,6 @@ static __init void davinci_ntosd2_init(void)
 {
 	struct clk *aemif_clk;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	int	status;
 
 	aemif_clk = clk_get(NULL, "aemif");
 	clk_enable(aemif_clk);
@@ -242,12 +209,6 @@ static __init void davinci_ntosd2_init(void)
 	platform_add_devices(davinci_ntosd2_devices,
 				ARRAY_SIZE(davinci_ntosd2_devices));
 
-	/* Initialize I2C interface specific for this board */
-	status = ntosd2_init_i2c();
-	if (status < 0)
-		pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
-						"	 %d\n", status);
-
 	davinci_serial_init(&uart_config);
 	dm644x_init_asp(&dm644x_ntosd2_snd_data);
 


From linux at arm.linux.org.uk  Thu Aug  9 05:20:21 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 10:20:21 +0100
Subject: imx6q restart is broken
In-Reply-To: <50232C17.9000700@gmail.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
Message-ID: <20120809092021.GQ18957@n2100.arm.linux.org.uk>

On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
> - at the last stage of reset, all non-boot cpus will call  
> ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb() for  
> V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10, 5")

I suspect having this dmb inside cpu_relax() is flooding the
interconnects with traffic, which then prevents other CPUs getting
a look-in (maybe there's no fairness when it comes to dmb's.

If I'm right, you'll find is that even converting this to the ARMv7
DMB instruction won't fix the problem.  It does, however, point
towards a more serious problem - it means that any tight loop using
dmb is detremental.  I have heard some people mention that even on
various ARM SMP platforms, they have see quite an amount of
interaction between the individual CPU cores, and I'm beginning
to wonder whether this is why.

I think a useful test would be to only execute the DMB maybe once
in 50 or 100 loops - the DMB is there to work around a different
problem with the temporal locality of stores on the local CPU.  So,
the only requirement is that we issue a DMB at some point while
spinning waiting for another CPU to respond to our previous writes.


From rjw at sisk.pl  Thu Aug  9 05:32:14 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 9 Aug 2012 11:32:14 +0200
Subject: [PATCH v2 1/2] cpufreq: OMAP: Handle missing frequency table on
 SMP systems
In-Reply-To: <1344496102-24451-2-git-send-email-rnayak@ti.com>
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
 <1344496102-24451-2-git-send-email-rnayak@ti.com>
Message-ID: <201208091132.14992.rjw@sisk.pl>

On Thursday, August 09, 2012, Rajendra Nayak wrote:
> On OMAP4, if the first CPU fails to get a valid frequency table (this
> could happen if the platform does not register any OPP table), the
> subsequent CPU instances end up dealing with a NULL freq_table and
> crash.
> 
> Check for an already existing freq_table, before trying to create one,
> and increment the freq_table_users only if the table is sucessfully
> created.
> 
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: <linux-pm at vger.kernel.org>

Kevin, are you going to merge this?

Rafael


> ---
>  drivers/cpufreq/omap-cpufreq.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
> index 17fa04d..b47034e 100644
> --- a/drivers/cpufreq/omap-cpufreq.c
> +++ b/drivers/cpufreq/omap-cpufreq.c
> @@ -218,7 +218,7 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
>  
>  	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
>  
> -	if (atomic_inc_return(&freq_table_users) == 1)
> +	if (!freq_table)
>  		result = opp_init_cpufreq_table(mpu_dev, &freq_table);
>  
>  	if (result) {
> @@ -227,6 +227,8 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
>  		goto fail_ck;
>  	}
>  
> +	atomic_inc_return(&freq_table_users);
> +
>  	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
>  	if (result)
>  		goto fail_table;
> 



From pieter at gmx.com  Thu Aug  9 05:30:55 2012
From: pieter at gmx.com (pieterg)
Date: Thu, 9 Aug 2012 11:30:55 +0200
Subject: [Openpxa-users] pxa3x0 smart panel interface
In-Reply-To: <CAN1soZyf5m+n7F+=jiKhqCjEuxdzESq9Cft8oDUhD3t4UN75sA@mail.gmail.com>
References: <20120806152551.4ec2cad0@laptoppieter>
 <201208082157.22064.marek.vasut@gmail.com>
 <CAN1soZyf5m+n7F+=jiKhqCjEuxdzESq9Cft8oDUhD3t4UN75sA@mail.gmail.com>
Message-ID: <20120809113055.210f35e4@laptoppieter>

On Thu, 9 Aug 2012 15:10:40 +0800
Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> >> Does any of you have experience with interfacing smart lcd panels,
> >> with a pxa3x0?
> >>
> 
> We didn't try to connect smart lcd panel with pxa300 or pxa310.
> 
> >> I'm interfacing an ILI9327DS smart panel controller, all commands
> >> are handled correctly, however the SMART_CMD_WRITE_FRAME command
> >> (which sends out all frame data) seems to produce an invalid
> >> number of output bytes every now and then.
> >> This results in a shifted display, every 10-100 updates
> >> (immediately corrected by the next update)
> 
> Do you mean that you observe this behavior on oscilloscope? Are you
> using LCD interface
> or SMEM interface?

I'm using the LCD interface (pxafb.c with CONFIG_FB_PXA_SMARTPANEL).

It is hard to check the exact length of the data block on an
oscilloscope (400 * 240 * 3 bytes of data is a bit too much). There is
no noticable difference in transfer length, when the display shifts.
I do not have the equipment to check the exact number of bytes being
transferred.
But when I configure the controller to wrap the write pointer around at
the end of the visible area, and update using just the
SMART_CMD_WRITE_FRAME command (no start command for the controller to
reset the write pointer to the beginning of the frame), I can see the
display image almost constantly shifting. A few columns forward, a few
columns back. Therefore my conclusion that the number of data bytes
sent (or received by the controller) must be fluctuating.
And this effect is at the end (or the beginning) of the frame, never
in the middle. Because the display image, though being shifted, is never
distorted.

> >> The strange thing is that this does not occur with a pxa300, but it
> >> occurs with the pxa310 and pxa320.
> >> However running the 310/320 with the same ACCR as I'm running the
> >> 300 does not 'fix' it.
> 
> Do you change frequency while you are testing this smart panel?

No, I'm keeping the frequencies constant, during the test.
(and the smart panel timings are not yet recalculated after a frequency
switch, so that would need some work)

> >> And I'm not sure it is even timing related, I've tried to configure
> >> huge smart timing delay parameters, but the results remain the
> >> same. (in fact I can even lower the parameters to way under the
> >> controller specs, and the issue does not get worse).
> >> I've also played with the drive strength of the LCD lines, which
> >> also does not have an effect on the issue.
> >>
> >> I do not think this is a controller bug, because before this
> >> ILI9327DS controller, we had a display with a different controller
> >> chip, with which I experienced the same thing, however at that
> >> time even with the pxa300.
> >> We switched to the ILI9327DS (for a different reason), and I was
> >> glad to find that it worked fine with the pxa300.
> >> Till I discovered it had the same issues, but then only with a
> >> pxa310/320.
> LCD controller between pxa300 and pxa310 is nearly same.


From balbi at ti.com  Thu Aug  9 05:28:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 9 Aug 2012 12:28:54 +0300
Subject: [PATCH v3 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <1344411661-17821-2-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-2-git-send-email-p.paneri@samsung.com>
Message-ID: <20120809092853.GJ12174@arwen.pp.htv.fi>

On Wed, Aug 08, 2012 at 01:10:57PM +0530, Praveen Paneri wrote:
> +static int __init samsung_usbphy_driver_init(void)
> +{
> +	return platform_driver_register(&samsung_usbphy_driver);
> +}
> +subsys_initcall(samsung_usbphy_driver_init);

let's make use of the module_platform_driver() and have dependent
drivers return -EPROBE_DEFER until this has registered.

-- 
balbi
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From balbi at ti.com  Thu Aug  9 05:29:39 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 9 Aug 2012 12:29:39 +0300
Subject: [PATCH v3 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1344411661-17821-3-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-3-git-send-email-p.paneri@samsung.com>
Message-ID: <20120809092938.GK12174@arwen.pp.htv.fi>

On Wed, Aug 08, 2012 at 01:10:58PM +0530, Praveen Paneri wrote:
> @@ -3689,6 +3706,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
>  	s3c_hsotg_phy_disable(hsotg);
>  	regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
>  
> +	if (hsotg->phy)
> +		devm_usb_put_phy(&pdev->dev, hsotg->phy);

unnecessary. This will be called for you when the platform_device object
is detroyed.

-- 
balbi
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From p.paneri at samsung.com  Thu Aug  9 05:56:48 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Thu, 9 Aug 2012 15:26:48 +0530
Subject: [PATCH v3 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <20120809092853.GJ12174@arwen.pp.htv.fi>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-2-git-send-email-p.paneri@samsung.com>
 <20120809092853.GJ12174@arwen.pp.htv.fi>
Message-ID: <CAD6zSYO4b6FXAdAKBnz1xU1TW3=rtqLdnD+X7-K8jxFVTaPtuA@mail.gmail.com>

On Thu, Aug 9, 2012 at 2:58 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Wed, Aug 08, 2012 at 01:10:57PM +0530, Praveen Paneri wrote:
>> +static int __init samsung_usbphy_driver_init(void)
>> +{
>> +     return platform_driver_register(&samsung_usbphy_driver);
>> +}
>> +subsys_initcall(samsung_usbphy_driver_init);
>
> let's make use of the module_platform_driver() and have dependent
> drivers return -EPROBE_DEFER until this has registered.
Thanks! I will modify accordingly and resend.

Praveen
>
> --
> balbi


From p.paneri at samsung.com  Thu Aug  9 06:00:11 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Thu, 9 Aug 2012 15:30:11 +0530
Subject: [PATCH v3 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <20120809092938.GK12174@arwen.pp.htv.fi>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-3-git-send-email-p.paneri@samsung.com>
 <20120809092938.GK12174@arwen.pp.htv.fi>
Message-ID: <CAD6zSYOU2Adz1dPjEjTEqp3L09Hmxd6Qu1AGL-1D8bvcLv_f3Q@mail.gmail.com>

On Thu, Aug 9, 2012 at 2:59 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Wed, Aug 08, 2012 at 01:10:58PM +0530, Praveen Paneri wrote:
>> @@ -3689,6 +3706,9 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
>>       s3c_hsotg_phy_disable(hsotg);
>>       regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
>>
>> +     if (hsotg->phy)
>> +             devm_usb_put_phy(&pdev->dev, hsotg->phy);
>
> unnecessary. This will be called for you when the platform_device object
> is detroyed.
Off-course, I will remove this.

Thanks
Praveen
>
> --
> balbi


From peter.ujfalusi at ti.com  Thu Aug  9 06:18:50 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 09 Aug 2012 13:18:50 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120808144933.GC24328@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com> <50227837.10400@ti.com>
 <20120808144933.GC24328@opensource.wolfsonmicro.com>
Message-ID: <50238E8A.5030902@ti.com>

On 08/08/2012 05:49 PM, Mark Brown wrote:
> That makes sense if the GPIO is actively driven, open drain should be
> better here, but it's still a generic thing which it'd be nice to
> extract.

Yes, the idea in it's core is generic, but right now I can not think of a
generic implementation which would work.
In case of twl4030 this is how it looks like:

1. if extmute is requested
 1.1. if GPIO number is not valid
   Use the internal MUTE functionality (HS_POPN_SET register, EXTMUTE bit)
 1.2. if GPIO number is valid
   set the GPIO to 1
2. Execute the sequence for the power up/down
3. if extmute is requested
 3.1. if GPIO number is not valid
   Use the internal MUTE functionality (HS_POPN_SET register, EXTMUTE bit)
 3.2. if GPIO number is valid
   set the GPIO to 0

For other devices it could be simpler:
1. Set GPIO for mute
2. Toggle a bit in the codec
3. Clear the GPIO to unmute

another device would need a sequence in step 2 instead of a single bit change.

To cover all of this in a generic way is not that straight forward IMHO.

> Still, the main thing here was the fact that we should be able to drop
> the flag for the feature in the first place.

Which flag you are referring?
I can (and have dropped) the hs_extmute_disable_level flag, but separate
hs_extmute, hs_extmute_gpio is needed for this device.

hs_extmute tells that the board implemented some sort of HS extmute functionality.
hs_extmute_gpio tells if the board is _not_ using the built in functionality,
but it is using external GPIO line to enable/disable the mute.

Sure I could do this:
hs_extmute: if only this is set we shall use the chip built in functionality
hs_extmute_gpio: if this is set we use the extmute feature but with external
                 GPIO.

But both need to be documented and supported.

-- 
P?ter


From broonie at opensource.wolfsonmicro.com  Thu Aug  9 06:19:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 11:19:47 +0100
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via
 device tree
In-Reply-To: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
Message-ID: <20120809101947.GA8474@sirena.org.uk>

On Tue, Aug 07, 2012 at 04:46:18PM -0500, Matt Sealey wrote:

Yay for indentation!  It'd be good to rewrite your DT so you could cut
down on that, at the minute it's not good for legibility.

> +							sw1_reg: sw1 {
> +								regulator-min-microvolt = <600000>;
> +								regulator-max-microvolt = <1375000>;
> +								regulator-boot-on;
> +								regulator-always-on;
> +							};

This and many of your other regulators have voltage ranges specified but
no consumers which doesn't make sense.  It looks awfully like you've
just typed in the maximum range supported by the regulator which is most
likely broken.

You're also specifying both boot_on and always_on which again doesn't
seem to make a lot of sense - boot_on mainly exists to help autoprobe,
using it quite this routinely isn't too clever.


From peter.ujfalusi at ti.com  Thu Aug  9 06:21:43 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 09 Aug 2012 13:21:43 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <50226444.4060100@compulab.co.il>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
 <50225A84.5010008@compulab.co.il> <50225BB5.3000407@ti.com>
 <50226444.4060100@compulab.co.il>
Message-ID: <50238F37.2030302@ti.com>

On 08/08/2012 04:06 PM, Igor Grinberg wrote:
> Well, yes I know we will need to adjust the user space.
> I wanted to change that for a long time and did not get to it...
> Now, with your patches, it seems like the best time for doing this.

Done for the v2. You will have card named "cm-t3x".

-- 
P?ter


From dave.martin at linaro.org  Thu Aug  9 06:24:14 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 9 Aug 2012 11:24:14 +0100
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
Message-ID: <20120809102414.GA17588@linaro.org>

On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:

[...]
 
> I'm going to do a trapse through and find where Russell nacked Dave's
> thumb-aware
> rewrite.. would you mind if you have any of these boards seeing if it
> really DOES

There was no NAK because I didn't get as far as posting the patch,
mostly because of the doubt about whether this code is ever relevant
on Thumb2-capable hardware.

If somebody with some old imx hardware that definitely relies on this
wants to pick it up and test it, it might still be useful.

I don't know whether I still have the original patch, but I think the
only think I did was to swap the roles of r13 and r12.  In the original
code r12 is only used as a base register, which is permissible usage
for r13 in Thumb-2.  Those two registers appear private to the fiq
handler, so I don't think the change will break anything, but I'd be
more confident is somebody is able to test it.

Cheers
---Dave

diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2d..3589afb 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -35,19 +35,19 @@
 		.global imx_ssi_fiq_tx_buffer
 
 imx_ssi_fiq_start:
-		ldr r12, imx_ssi_fiq_base
+		ldr r13, imx_ssi_fiq_base
 
 		/* TX */
 		ldr r11, imx_ssi_fiq_tx_buffer
 
 		/* shall we send? */
-		ldr r13, [r12, #SSI_SIER]
-		tst r13, #SSI_SIER_TFE0_EN
+		ldr r12, [r13, #SSI_SIER]
+		tst r12, #SSI_SIER_TFE0_EN
 		beq 1f
 
 		/* TX FIFO empty? */
-		ldr r13, [r12, #SSI_SISR]
-		tst r13, #SSI_SISR_TFE0
+		ldr r12, [r13, #SSI_SISR]
+		tst r12, #SSI_SISR_TFE0
 		beq 1f
 
 		mov r10, #0x10000
@@ -56,34 +56,34 @@ imx_ssi_fiq_start:
 
 		add r11, r11, r10
 
-		ldrh r13, [r11]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r12, [r11]
+		strh r12, [r13, #SSI_STX0]
 
-		ldrh r13, [r11, #2]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r12, [r11, #2]
+		strh r12, [r13, #SSI_STX0]
 
-		ldrh r13, [r11, #4]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r12, [r11, #4]
+		strh r12, [r13, #SSI_STX0]
 
-		ldrh r13, [r11, #6]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r12, [r11, #6]
+		strh r12, [r13, #SSI_STX0]
 
 		add r10, #8
-		lsr r13, r8, #16	/* r13: buffer size */
-		cmp r10, r13
-		lslgt r8, r13, #16
+		lsr r12, r8, #16	/* r12: buffer size */
+		cmp r10, r12
+		lslgt r8, r12, #16
 		addle r8, #8
 1:
 		/* RX */
 
 		/* shall we receive? */
-		ldr r13, [r12, #SSI_SIER]
-		tst r13, #SSI_SIER_RFF0_EN
+		ldr r12, [r13, #SSI_SIER]
+		tst r12, #SSI_SIER_RFF0_EN
 		beq 1f
 
 		/* RX FIFO full? */
-		ldr r13, [r12, #SSI_SISR]
-		tst r13, #SSI_SISR_RFF0
+		ldr r12, [r13, #SSI_SISR]
+		tst r12, #SSI_SISR_RFF0
 		beq 1f
 
 		ldr r11, imx_ssi_fiq_rx_buffer
@@ -94,31 +94,31 @@ imx_ssi_fiq_start:
 
 		add r11, r11, r10
 
-		ldr r13, [r12, #SSI_SACNT]
-		tst r13, #SSI_SACNT_AC97EN
+		ldr r12, [r13, #SSI_SACNT]
+		tst r12, #SSI_SACNT_AC97EN
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11]
+		ldr r12, [r13, #SSI_SRX0]
+		strh r12, [r11]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #2]
+		ldr r12, [r13, #SSI_SRX0]
+		strh r12, [r11, #2]
 
 		/* dummy read to skip slot 12 */
-		ldrne r13, [r12, #SSI_SRX0]
+		ldrne r12, [r13, #SSI_SRX0]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #4]
+		ldr r12, [r13, #SSI_SRX0]
+		strh r12, [r11, #4]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #6]
+		ldr r12, [r13, #SSI_SRX0]
+		strh r12, [r11, #6]
 
 		/* dummy read to skip slot 12 */
-		ldrne r13, [r12, #SSI_SRX0]
+		ldrne r12, [r13, #SSI_SRX0]
 
 		add r10, #8
-		lsr r13, r9, #16	/* r13: buffer size */
-		cmp r10, r13
-		lslgt r9, r13, #16
+		lsr r12, r9, #16	/* r12: buffer size */
+		cmp r10, r12
+		lslgt r9, r12, #16
 		addle r9, #8
 
 1:



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 06:36:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 11:36:00 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <50238E8A.5030902@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com>
 <50227837.10400@ti.com>
 <20120808144933.GC24328@opensource.wolfsonmicro.com>
 <50238E8A.5030902@ti.com>
Message-ID: <20120809103600.GI24328@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 01:18:50PM +0300, Peter Ujfalusi wrote:
> On 08/08/2012 05:49 PM, Mark Brown wrote:

> > That makes sense if the GPIO is actively driven, open drain should be
> > better here, but it's still a generic thing which it'd be nice to
> > extract.

> To cover all of this in a generic way is not that straight forward IMHO.

The sequence is just:

  1. Enable mutes (at _PRE time)
  2. Do whatever the device needs
  3. Disable the mutes (at _POST time)

I'm not sure there's any reason for you not to use the internal mute
even if the external mute is present but if there is that's the only
thing that's weird here.  If there's no reason not to do it it just goes
into step 2 and then it's fine, even if there is you can make it
conditional in step 2.

> Sure I could do this:
> hs_extmute: if only this is set we shall use the chip built in functionality
> hs_extmute_gpio: if this is set we use the extmute feature but with external
>                  GPIO.

> But both need to be documented and supported.

Is there any actual case where an external mute is supplied via a
mechanism other than a GPIO, and if there is would it not either need
its own DT property or already need to interact with the driver from
code, making the DT property redundant?  My thinking here is that the
flag should be redundant because we already need to specify how we do
the mute, what I'd expect is that we activate the external mute
functionality as a result of being given another way of doing it so we
don't need to provide a flag.


From wni at nvidia.com  Thu Aug  9 06:43:26 2012
From: wni at nvidia.com (Wei Ni)
Date: Thu, 9 Aug 2012 18:43:26 +0800
Subject: How to get the irq flags from the dts file
Message-ID: <1344509006.2295.148.camel@tegra-chromium-2>

Hi, all
I'm working on tegra wlan upstream issue.
The tegra board use the Broadcom 4329 as wlan device, and the driver is
the brcmfmac. 

This wlan driver support out-band-interrupt (OOB), I want to add DT
support to use this OOB.
I can add following lines in the dts file to create platform device and
pass the interrupt resource to the driver.

wlan {
        compatible = "broadcome, brcmf_sdio_pd";
        interrupt-parten = <&gpio>;
        interrupts = <144, 0x04>; /* IRQF_TRIGGER_HIGH */
};

In the wlan driver, it will use platform_get_resource() to get the
res->irq, res->flags, the irq number is right, but the flags will be
IORESOURCE_IRQ, not the 0x04 (IRQF_TRIGGER_HIGH).
The wlan driver wish this flags include the IRQF_TRGGER_* information,
and it will use this flags to configure other hw settings. If it is
wrong, the wlan can't work.

I checked drivers/of/irq.c, in function of_irq_to_resource(), it will
set r->flags = IORESOURCE_IRQ directly, not read the flags from the dtb
file. And I didn't find any of_xx api to get this flags.

How can I get this flags, does anyone has suggestion?

Thanks.
Wei.



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 06:53:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 11:53:50 +0100
Subject: [PATCH v2 3/4] regulator: add a new API
 regulator_set_voltage_tol()
In-Reply-To: <20120808143004.GB14718@S2101-09.ap.freescale.net>
References: <1344179121-17738-1-git-send-email-shawn.guo@linaro.org>
 <1344179121-17738-4-git-send-email-shawn.guo@linaro.org>
 <20120808133540.GB16861@opensource.wolfsonmicro.com>
 <20120808143004.GB14718@S2101-09.ap.freescale.net>
Message-ID: <20120809105349.GL24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 10:30:07PM +0800, Shawn Guo wrote:
> On Wed, Aug 08, 2012 at 02:35:40PM +0100, Mark Brown wrote:

> > Applied, thanks!  It's on a separate branch so can easily be either
> > applied somewhere else or merged into another tree if required for
> > dependencies, just let me know.

> I intended to have the whole series go via cpufreq tree with your ack
> on this patch.  But I could also ask Rafael to merge your branch to
> resolve the dependency.

I anticipate wanting the new API in other trees too (I have one likely
use in mind) so having it only in the cpufreq tree would be inconvenient.
The whole reason to have this in the regulator API is that it's
something that's useful outside your cpufreq code!


From ian.molton at codethink.co.uk  Thu Aug  9 06:59:33 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Thu, 09 Aug 2012 11:59:33 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <50226779.6060201@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <50223428.6030506@codethink.co.uk> <502252A6.4090409@codethink.co.uk>
 <201208081239.16778.arnd@arndb.de> <50226779.6060201@codethink.co.uk>
Message-ID: <50239815.6020108@codethink.co.uk>

Adding devicetree-discuss and linuxppc-dev, as well as Dale Farnsworth,
who initially added the bindings for mv643xx.

On 08/08/12 14:19, Ian Molton wrote:
> On 08/08/12 13:39, Arnd Bergmann wrote:
>> On Wednesday 08 August 2012, Ian Molton wrote:
>>> The SMI / PHY stuff should look very similar, so I'm happy with something
>>> like:
>>>
>>> mdio at 2000 {
>>>                 #address-cells = <1>;
>>>                 #size-cells = <1>;
>>>                 device_type = "mdio";
>>>                 compatible = "marvell,mv643xx-mdio";
>>>                 phy0: ethernet-phy at 0 {
>>>                         device_type = "ethernet-phy";
>>>                         compatible = "marvell,whatever";
>>>                         interrupts = <76>;
>>>                         interrupt-parent = <&mpic>;
>>>                         reg = <0 32>;          // Auto probed phy addr
>>>                 };
>>>
>>>                 phy1: ethernet-phy at 3 {
>>>                         device_type = "ethernet-phy";
>>>                         compatible = "marvell,whatever";
>>>                         interrupts = <77>;
>>>                         interrupt-parent = <&mpic>;
>>>                         reg = <3 1>;            // specified phy addr
>>>                 };
>>>
>>>                 ... and so on.
>>> }
>>>
>>> Where we can use the reg parameter to allow auto-probing, by
>>> specifying a size of 32 (32 phy addrs max).
>> I don't understand the auto-probed phy address. What is the purpose of that?
> Personally, I think it should die - but the existing driver and a number
> of its users actually scan the bus for their PHY.
>
> I doubt the PHY really moves about or is hotplugged by any of them,
> and its actually quite a slow process.
>
>> If possible, I think we should keep using #size-cells=<0>, which would
>> make the method you describe impossible. It might still work if you just
>> leave out the "reg" property for that node.
> I can certainly investigate that. I couldn't see any good evidence that
> it was a supported mechanism when I looked.
>
>> I also don't understand how the phy driver would locate ethernet-phy at 0
>> on the bus if it does not know the address.
>>
>>> The ethernet driver itself is more complicated:
>>>
>>> We have the following considerations:
>>>
>>> * we have one MDIO bus, typically, shared between all the MACs / PHYs.
>>> * each ethernet device can multiple ports (up to three), each with its
>>>   own MAC/PHY.
>>> * MAC <-> PHY mapping can be specified, probed (ugh!) or a (gah!)
>>>   mix of the two.
>>> * existing D-T users, albeit not well documented / code complete.
>>> * some port address ranges overlap (MIB counters, MCAST / UNICAST
>>>   tables, etc.
>>>
>>> The existing ethernet-group idea only works because the current
>>> platform-device based driver doesnt really do proper resource
>>> management, and thus the MAC registers are actually mapped by
>>> the MDIO driver.
>>>
>>> I don't think that preserving this bad behaviour is a good idea, which
>>> leaves us with two choices:
>>>
>>> 1) My preferred solution - allow each device to specify up to three
>>> interrupts, MACs, and PHYs. This is clean in that it doesnt require
>>> multiply instantiating a driver three times over the same address
>>> space.
>>>
>>> ethernet at 2400 {
>>>                 compatible = "marvell,mv643xx-eth";
>>>                 reg = <0x2400 0x1c00>
>>>                 interrupt_parent = <&mpic>;
>>>                 ports = <3>;
>>>                 interrupts = <4>, <5>, <6>;
>>>                 phys = <&phy0>, <&phy1>, <&phy2>;
>>> };
>>>
>>> ethernet at 6400 {
>>>                 compatible = "marvell,mv643xx-eth";
>>>                 reg = <0x6400 0x1c00>
>>>                 interrupt_parent = <&mpic>;
>>>                 ports = <1>;
>>>                 interrupts = <4>;
>>>                 phys = <&phy3>;
>>> };
>>>
>>> Note that the address is 2400, not 2000 - since this driver no longer
>>> would share its address range with the MDIO driver.
>>>
>>> This method would require a small amount of rework in the driver to
>>> set up <n> ports, rather than just one.
>> This looks quite nice, but it is still very much incompatible with the
>> existing binding. Obviously we can abandon an existing binding and
>> introduce a second one for the same hardware, but that should not
>> be taken lightly.
> Fair, however the existing users aren't anywhere near as
> numerous as the new ones.
>
>>> 2) Create some kind of pseudo-ethernet group device that manages
>>> all the work for some sort of lightweight ethernet device, one per
>>> port. This can never be done cleanly since the port address ranges
>>> overlap:
>>>
>>> pseudo_eth at 2400 {
>>>         #address-cells = <1>;
>>>         #size-cells = <0>;
>>>         compatible = "marvell,mv643xx-shared-eth"
>>>         reg = <0x2400 0x1c00>;
>>>
>>>         ethernet at 0 {
>>>                 compatible = "marvell,mv643xx-port";
>>>                 interrupts = <4>;
>>>                 interrupt_parent = <&mpic>;
>>>                 phy = <&phy0>;
>>>         };
>>>
>>>         ethernet at 1 {
>>>                 compatible = "marvell,mv643xx-port";
>>>                 interrupts = <5>;
>>>                 interrupt_parent = <&mpic>;
>>>                 phy = <&phy1>;
>>>         };
>>>
>>>         ethernet at 2 {
>>>                 compatible = "marvell,mv643xx-port";
>>>                 interrupts = <6>;
>>>                 interrupt_parent = <&mpic>;
>>>                 phy = <&phy2>;
>>>         };
>>> }
>>> pseudo_eth at 6400 {
>>>         #address-cells = <1>;
>>>         #size-cells = <0>;
>>>         compatible = "marvell,mv643xx-shared-eth"
>>>         reg = <0x6400 0x1c00>;
>>>
>>>         ethernet at 0 {
>>>                 compatible = "marvell,mv643xx-port";
>>>                 interrupts = <4>;
>>>                 interrupt_parent = <&mpic>;
>>>                 phy = <&phy3>;
>>>         };
>>> };
>> This looks almost compatible with the existing binding, which is
>> good.
> Well, I'm not sure about that - if the existing bindings are really
> baked into firmware, then "almost" wont be any use at all.
>
>>  I would in fact recommend to use the actual "compatible"
>> strings from the binding. More generally speaking, you should not
>> use wildcards in those strings anyway, so always use
>> "marvell,mv64360-eth" instead of "marvell,mv64x60-eth" or
>> "marvell,mv643xx-eth". If you have multiple chips that are
>> completely compatible, put use the identifier for the older one.
> Noted.
>
>> I don't fully understand your concern with the overlapping
>> registers, mostly because I still don't know all the combinations
>> that are actually valid here. Let me try to say what I understood
>> so far, and you can correct me if that's wrong:
>>
>> * A system can have multiple instances of an mv64360 ethernet
>> block, with a register area of 0x2000 bytes.
>> * Each such block can have three MACs and three PHYs.
>> * The first 0x400 bytes in the register space control the three
>>   PHYs and the remaining registers control the MACs.
>> * While this is meant to be used in a way that you assign
>>   the each of the three PHYs to one of the MACs, this is not
>>   always done, and sometimes you use a different PHY (?), or
>>   one from a different instance of the mv64360 ethernet block
>>   on the same SoC?.
> Nearly - the whole block is 0x2000 in size, yes. And each one
> can have 3 MACs and PHYs, as you say.
>
> There is SMI @ 0x2000 - just one for all ports, and in many
> (all?) cases, for all all the other controllers on the SoC to
> share. On the armadaXP SoC, for example, each ethernet
> block has its own alias of the same bas SMI reg. (there are
> 4 blocks)
>
> ethernet0@ 0x2400
> ## regs in order: Main regs, MIB counters, Special mcast table, Mcast
> table, Unicast table.
>    port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
>    port1 has regs at +0x0400 *0x1080 +0x1800 +0x1900 +0x1a00
>    port2 has regs at +0x0800 *0x1100 +0x1c00 +0x1d00 +0x1e00
> ethernet1@ 0x6400
>   port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
> ...
>
> As you can see, instead of putting port1 at +0x1700 or so,
> marvell have overlapped the register files - in fact, doubly
> so, since port1 + 0x1080 is right in the middle of
> (port0 + 0x1000) -> (port0 + 0x16ff), so one cant simply map two
> sets of regs like 0x0000->0x03ff and 0x1000->0x16ff for port one
> either.
>
> -Ian
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From kbaidarov at dev.rtsoft.ru  Thu Aug  9 07:00:47 2012
From: kbaidarov at dev.rtsoft.ru (Konstantin Baydarov)
Date: Thu, 09 Aug 2012 15:00:47 +0400
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system control
 driver
In-Reply-To: <50227ED9.3010508@dev.rtsoft.ru>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com> <20120808141051.GG11011@atomide.com>
 <20120808143929.GJ11011@atomide.com> <50227ED9.3010508@dev.rtsoft.ru>
Message-ID: <5023985F.3090606@dev.rtsoft.ru>

  Hi, Tony.

On 08/08/2012 06:59 PM, Konstantin Baydarov wrote:
>   Yes, omap_type() is called very early , that is why I'm using early_initcall for omap_control_base initialization.
>
> Do you mean following?:
> void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
> {
>     if (omap2_globals->ctrl)
>         omap2_ctrl_base = omap2_globals->ctrl;
>
>     if (omap2_globals->ctrl_pad)
>         omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
>
>     omap_control_base = omap2_ctrl_base;  // this line is added
> }
  Sorry for the confusion - the code above isn't correct. First, as omap-control-core.c driver maps only control module status register the omap_control_base should be renamed to omap_control_status_reg:

--- a/drivers/mfd/omap-control-core.c
+++ b/drivers/mfd/omap-control-core.c
@@ -35,13 +35,15 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-void __iomem *omap_control_base;
+void __iomem *omap_control_status_reg;
 unsigned long omap_control_phys_base;
 size_t omap_control_mapsize;
 
 u32 omap_control_status_read(void)


Then, if you want to move omap_control_status_reg(omap_control_base) initialization to the
omap2_set_globals_control(), it can be done following way:

--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -149,6 +149,8 @@ static struct omap3_control_regs control_context;
 #define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))
 #define OMAP4_CTRL_PAD_REGADDR(reg)	(omap4_ctrl_pad_base + (reg))
 
+extern void __iomem *omap_control_status_reg;
+
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
 	if (omap2_globals->ctrl)
@@ -156,6 +158,20 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 
 	if (omap2_globals->ctrl_pad)
 		omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
+
+	omap_control_status_reg = omap2_ctrl_base;
+	if (cpu_is_omap24xx())
+		omap_control_status_reg += OMAP24XX_CONTROL_STATUS;
+	else if (soc_is_am33xx())
+		omap_control_status_reg += AM33XX_CONTROL_STATUS;
+	else if (cpu_is_omap34xx())
+		omap_control_status_reg += OMAP343X_CONTROL_STATUS;
+	else if (cpu_is_omap44xx())
+		omap_control_status_reg += OMAP4_CTRL_MODULE_CORE_STATUS;
+	else if (soc_is_omap54xx())
+		omap_control_status_reg += OMAP5XXX_CONTROL_STATUS;
+	else
+		omap_control_status_reg = 0;
 }
 
 void __iomem *omap_ctrl_base_get(void)


Then omap_type() can be changed:

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8018cad..916b3f6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -39,31 +39,27 @@ unsigned int omap_rev(void)
 }
 EXPORT_SYMBOL(omap_rev);
 
+extern void __iomem *omap_control_status_reg;
+
 int omap_type(void)
 {
 	u32 val = 0;
 
-	if (cpu_is_omap24xx()) {
-		val = omap_control_status_read();
-	} else if (soc_is_am33xx()) {
-		val = omap_control_status_read();
-	} else if (cpu_is_omap34xx()) {
-		val = omap_control_status_read();
-	} else if (cpu_is_omap44xx()) {
+	if(!omap_control_status_reg) {
+		pr_err("Cannot detect omap type!\n");
+		goto out;
+	}
+
+	if(!soc_is_omap54xx()) {
 		val = omap_control_status_read();
-	} else if (soc_is_omap54xx()) {
+		val &= OMAP2_DEVICETYPE_MASK;
+		val >>= 8;
+	} else {
 		val = omap_control_status_read();
 		val &= OMAP5_DEVICETYPE_MASK;
 		val >>= 6;
-		goto out;
-	} else {
-		pr_err("Cannot detect omap type!\n");
-		goto out;
 	}
 
-	val &= OMAP2_DEVICETYPE_MASK;
-	val >>= 8;
-
 out:
 	return val;
 }


  BR,
    Konstantin Baydarov.

>   Or you suggest to move
> void __init of_omap_control_init(const struct of_device_id *matches)
> {
>     struct device_node *np;
>     struct property *pp = 0;
>
>     for_each_matching_node(np, matches) {
>         pp = of_find_property(np, "reg", NULL);
>         if(pp) {
>             omap_control_phys_base = (unsigned long)be32_to_cpup(pp->value);
>             omap_control_mapsize = (size_t)be32_to_cpup( (void*)((char*)pp->value + 4) );
>             /*
>              * Map control module register CONTROL_STATUS register:
>              * omap24xx - OMAP24XX_CONTROL_STATUS
>              * am33xx   - AM33XX_CONTROL_STATUS
>              * omap34xx - OMAP343X_CONTROL_STATUS
>              * omap44xx - OMAP4_CTRL_MODULE_CORE_STATUS
>              * omap54xx - OMAP5XXX_CONTROL_STATUS
>              */
>             omap_control_base = ioremap(omap_control_phys_base, omap_control_mapsize);
>         }
>     }
> }
>
> into omap2_set_globals_control() ?
>
> Also if we move omap_control_base initialization to omap2_set_globals_control(), than the initialization routine of drivers/mfd/omap-control-core.c become empty, because omap_control_base is the only thing that is initialized in omap-control-core driver.
>
>   BR,
>     Konstantin Baydarov.
>
>> Regards,
>>
>> Tony
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From arnd at arndb.de  Thu Aug  9 07:43:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 Aug 2012 11:43:32 +0000
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <50239815.6020108@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <50226779.6060201@codethink.co.uk> <50239815.6020108@codethink.co.uk>
Message-ID: <201208091143.32972.arnd@arndb.de>

 On 08/08/12 14:19, Ian Molton wrote:
 > On 08/08/12 13:39, Arnd Bergmann wrote:
 >> On Wednesday 08 August 2012, Ian Molton wrote:
 >>> This method would require a small amount of rework in the driver to
 >>> set up <n> ports, rather than just one.
 >> This looks quite nice, but it is still very much incompatible with the
 >> existing binding. Obviously we can abandon an existing binding and
 >> introduce a second one for the same hardware, but that should not
 >> be taken lightly.
 > Fair, however the existing users aren't anywhere near as
 > numerous as the new ones.

Depends on how you count the numbers. I see at least three machines
supported in the kernel with the old binding and none with the new one
so far ;-)

 >> I don't fully understand your concern with the overlapping
 >> registers, mostly because I still don't know all the combinations
 >> that are actually valid here. Let me try to say what I understood
 >> so far, and you can correct me if that's wrong:
 >>
 >> * A system can have multiple instances of an mv64360 ethernet
 >> block, with a register area of 0x2000 bytes.
 >> * Each such block can have three MACs and three PHYs.
 >> * The first 0x400 bytes in the register space control the three
 >>   PHYs and the remaining registers control the MACs.
 >> * While this is meant to be used in a way that you assign
 >>   the each of the three PHYs to one of the MACs, this is not
 >>   always done, and sometimes you use a different PHY (?), or
 >>   one from a different instance of the mv64360 ethernet block
 >>   on the same SoC?.
 > Nearly - the whole block is 0x2000 in size, yes. And each one
 > can have 3 MACs and PHYs, as you say.
 >
 > There is SMI @ 0x2000 - just one for all ports, and in many
 > (all?) cases, for all all the other controllers on the SoC to
 > share. On the armadaXP SoC, for example, each ethernet
 > block has its own alias of the same bas SMI reg. (there are
 > 4 blocks)
 >
 > ethernet0@ 0x2400
 > ## regs in order: Main regs, MIB counters, Special mcast table, Mcast
 > table, Unicast table.
 >    port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
 >    port1 has regs at +0x0400 *0x1080 +0x1800 +0x1900 +0x1a00
 >    port2 has regs at +0x0800 *0x1100 +0x1c00 +0x1d00 +0x1e00
 > ethernet1@ 0x6400
 >   port0 has regs at +0x0000 *0x1000 +0x1400 +0x1500 +0x1600
 > ...
 >
 > As you can see, instead of putting port1 at +0x1700 or so,
 > marvell have overlapped the register files - in fact, doubly
 > so, since port1 + 0x1080 is right in the middle of
 > (port0 + 0x1000) -> (port0 + 0x16ff), so one cant simply map two
 > sets of regs like 0x0000->0x03ff and 0x1000->0x16ff for port one
 > either.

This could theoretically be dealt with by having 5 register ranges
per device, but that would cause extra overhead and also be
incompatible with the existing binding. I think showing one
parent device with children at address 0, 1 and 2 is ok. The driver
already knows all those offsets and they are always the same
for all variants of mv643xx, right?

	Arnd


From arnd at arndb.de  Thu Aug  9 07:48:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 Aug 2012 11:48:42 +0000
Subject: How to get the irq flags from the dts file
In-Reply-To: <1344509006.2295.148.camel@tegra-chromium-2>
References: <1344509006.2295.148.camel@tegra-chromium-2>
Message-ID: <201208091148.42748.arnd@arndb.de>

On Thursday 09 August 2012, Wei Ni wrote:
> In the wlan driver, it will use platform_get_resource() to get the
> res->irq, res->flags, the irq number is right, but the flags will be
> IORESOURCE_IRQ, not the 0x04 (IRQF_TRIGGER_HIGH).
> The wlan driver wish this flags include the IRQF_TRGGER_* information,
> and it will use this flags to configure other hw settings. If it is
> wrong, the wlan can't work.
> 
> I checked drivers/of/irq.c, in function of_irq_to_resource(), it will
> set r->flags = IORESOURCE_IRQ directly, not read the flags from the dtb
> file. And I didn't find any of_xx api to get this flags.
> 
> How can I get this flags, does anyone has suggestion?

The driver should not need to know about thie flag. It gets read
by irq_create_of_mapping when calling teh xlate function and
gets set using irq_set_irq_type from there too.

	Arnd


From shawn.guo at linaro.org  Thu Aug  9 08:01:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 20:01:47 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120809092021.GQ18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
Message-ID: <20120809120144.GA19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 10:20:21AM +0100, Russell King - ARM Linux wrote:
> I suspect having this dmb inside cpu_relax() is flooding the
> interconnects with traffic, which then prevents other CPUs getting
> a look-in (maybe there's no fairness when it comes to dmb's.
> 
> If I'm right, you'll find is that even converting this to the ARMv7
> DMB instruction won't fix the problem.  It does, however, point
> towards a more serious problem - it means that any tight loop using
> dmb is detremental.  I have heard some people mention that even on
> various ARM SMP platforms, they have see quite an amount of
> interaction between the individual CPU cores, and I'm beginning
> to wonder whether this is why.
> 
> I think a useful test would be to only execute the DMB maybe once
> in 50 or 100 loops - the DMB is there to work around a different
> problem with the temporal locality of stores on the local CPU.  So,
> the only requirement is that we issue a DMB at some point while
> spinning waiting for another CPU to respond to our previous writes.

You got it.

The following change fixed the problem for me.  But I think you only
meant it for testing.  So how should we actually fix the problem?

Regards,
Shawn

--8<---

diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 99afa74..1282b61 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -80,11 +80,18 @@ extern void release_thread(struct task_struct *);
 unsigned long get_wchan(struct task_struct *p);

 #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
-#define cpu_relax()                    smp_mb()
+#define __cpu_relax()                  smp_mb()
 #else
-#define cpu_relax()                    barrier()
+#define __cpu_relax()                  barrier()
 #endif

+#define cpu_relax()                                                    \
+({                                                                     \
+       static int i;                                                   \
+       if (i++ % 100)                                                  \
+               __cpu_relax();                                          \
+})
+



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 08:05:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 13:05:30 +0100
Subject: How to get the irq flags from the dts file
In-Reply-To: <201208091148.42748.arnd@arndb.de>
References: <1344509006.2295.148.camel@tegra-chromium-2>
 <201208091148.42748.arnd@arndb.de>
Message-ID: <20120809120530.GC8474@sirena.org.uk>

On Thu, Aug 09, 2012 at 11:48:42AM +0000, Arnd Bergmann wrote:
> On Thursday 09 August 2012, Wei Ni wrote:

> > The wlan driver wish this flags include the IRQF_TRGGER_* information,
> > and it will use this flags to configure other hw settings. If it is
> > wrong, the wlan can't work.

You can read the configuration with irqd_get_trigger_type() - see the OF
code in sound/soc/codecs/wm8903.c for an example.

> The driver should not need to know about thie flag. It gets read
> by irq_create_of_mapping when calling teh xlate function and
> gets set using irq_set_irq_type from there too.

That only helps the interrupt controller, it doesn't help the interrupt
source.  A good proportion of embedded devices have a great deal of
flexibility in how they signal interrupts so they need to know what mode
to pick.


From arend at broadcom.com  Thu Aug  9 08:09:51 2012
From: arend at broadcom.com (Arend van Spriel)
Date: Thu, 9 Aug 2012 14:09:51 +0200
Subject: How to get the irq flags from the dts file
In-Reply-To: <1344509006.2295.148.camel@tegra-chromium-2>
References: <1344509006.2295.148.camel@tegra-chromium-2>
Message-ID: <5023A88F.8040402@broadcom.com>

On 08/09/2012 12:43 PM, Wei Ni wrote:
> Hi, all
> I'm working on tegra wlan upstream issue.
> The tegra board use the Broadcom 4329 as wlan device, and the driver is
> the brcmfmac. 
> 
> This wlan driver support out-band-interrupt (OOB), I want to add DT
> support to use this OOB.
> I can add following lines in the dts file to create platform device and
> pass the interrupt resource to the driver.
> 
> wlan {
>         compatible = "broadcome, brcmf_sdio_pd";

I don't know the DT syntax, but I assume broadcome should be broadcom,
right? ;-)

>         interrupt-parten = <&gpio>;
>         interrupts = <144, 0x04>; /* IRQF_TRIGGER_HIGH */
> };
> 
> In the wlan driver, it will use platform_get_resource() to get the
> res->irq, res->flags, the irq number is right, but the flags will be
> IORESOURCE_IRQ, not the 0x04 (IRQF_TRIGGER_HIGH).
> The wlan driver wish this flags include the IRQF_TRGGER_* information,
> and it will use this flags to configure other hw settings. If it is
> wrong, the wlan can't work.
> 
> I checked drivers/of/irq.c, in function of_irq_to_resource(), it will
> set r->flags = IORESOURCE_IRQ directly, not read the flags from the dtb
> file. And I didn't find any of_xx api to get this flags.
> 
> How can I get this flags, does anyone has suggestion?

I did a quick search in the kernel and there are a number of platform
drivers that seem to expect the IRQF_TRIGGER_* info by using (res->flags
& IRQF_TRIGGER_MASK) and to determine IRQF_SHARED as well.

Gr. AvS



From ldewangan at nvidia.com  Thu Aug  9 08:03:34 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Thu, 9 Aug 2012 17:33:34 +0530
Subject: [PATCH V3] ARM: dt: tegra: ventana: add regulators
In-Reply-To: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
References: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <5023A716.50807@nvidia.com>

On Friday 03 August 2012 11:39 PM, Stephen Warren wrote:
> From: Stephen Warren<swarren at nvidia.com>
>
> Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
> couple of fixed GPIO-controlled regulators too.
>
> The data was chosen to match the PMIC HW defaults, with the following
> exception:
>
> ldo6: The HW default is 2.85v. The schematics are unlabelled. Internal
> research indicates that 1.8v is correct. Our downstream kernel also uses
> 1.8v.
>
> Portions based on work by Laxman Dewangan<ldewangan at nvidia.com>
>
> Signed-off-by: Stephen Warren<swarren at nvidia.com>
> ---
> v3:
> * Switch back to simple-bus compatible value for the /regulators node.
> * Added supply properties for all TPS6586x regulators.
> * Made SM* children of the new SYS regulator.
> * Removed ldo0 configuration, since it isn't used.
> v2:
> * Made all constraints match the HW defaults to avoid behavior changes,
>    with exceptions noted above.
> * Removed vin-supply properties from LDO nodes; the driver and binding
>    need to be updated to support specifying the parent regulators before
>    we can put these into DT.
> * Rename vdd_pnl regulator-name to match schematic.
> * Added vdd_bl regulator.
> * Fix typo in regulator at 3 reg property.
> * Use the enumerated-bus compatible value for the /regulators node.
> * Enhanced all regulator-name properties to list all signal names directly
>    derived from the regulator pins.
> * Added ldo_rtc regulator.
> ---

Acked-by: Laxman Dewangan <ldewangan at nvidia.com>
You can addd my ACK for harmony dts file.

>   arch/arm/boot/dts/tegra20-ventana.dts |  204 +++++++++++++++++++++++++++++++++
>   1 files changed, 204 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
> index be90544..4ec6b4c 100644
> --- a/arch/arm/boot/dts/tegra20-ventana.dts
> +++ b/arch/arm/boot/dts/tegra20-ventana.dts
> @@ -289,6 +289,156 @@
>   	i2c at 7000d000 {
>   		status = "okay";
>   		clock-frequency =<400000>;
> +
> +		pmic: tps6586x at 34 {
> +			compatible = "ti,tps6586x";
> +			reg =<0x34>;
> +			interrupts =<0 86 0x4>;

Should we say interrupt-controller also here?
> +
> +			sys-supply =<&vdd_5v0_reg>;
> +			vin-sm0-supply =<&sys_reg>;
> +			vin-sm1-supply =<&sys_reg>;
> +			vin-sm2-supply =<&sys_reg>;

This depends on two changes on tps6586x regulator which are not merged yet.


> +
> +	pmc {

Should say status OK?



From shawn.guo at linaro.org  Thu Aug  9 08:22:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 20:22:22 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120809120144.GA19617@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <20120809120144.GA19617@S2101-09.ap.freescale.net>
Message-ID: <20120809122220.GB19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 08:01:47PM +0800, Shawn Guo wrote:
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index 99afa74..1282b61 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -80,11 +80,18 @@ extern void release_thread(struct task_struct *);
>  unsigned long get_wchan(struct task_struct *p);
> 
>  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> -#define cpu_relax()                    smp_mb()
> +#define __cpu_relax()                  smp_mb()
>  #else
> -#define cpu_relax()                    barrier()
> +#define __cpu_relax()                  barrier()
>  #endif
> 
> +#define cpu_relax()                                                    \
> +({                                                                     \
> +       static int i;                                                   \
> +       if (i++ % 100)                                                  \

This should be 

	if (i++ % 100 == 0)

But either way it fixes the problem.

> +               __cpu_relax();                                          \
> +})
> +
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Regards,
Shawn



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 09:06:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 14:06:20 +0100
Subject: [PATCH] ASoC: Davinci: McASP: remove unused header include
In-Reply-To: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344438632-2604-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120809130620.GR24328@opensource.wolfsonmicro.com>

On Wed, Aug 08, 2012 at 08:40:30PM +0530, Hebbar, Gururaja wrote:
> Defines or parameters from <mach/mux.h> isn't used anywhere. Hence
> remove the header include.

Applied all, thanks.


From grinberg at compulab.co.il  Thu Aug  9 09:12:13 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 09 Aug 2012 16:12:13 +0300
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <50238F37.2030302@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
 <50225A84.5010008@compulab.co.il> <50225BB5.3000407@ti.com>
 <50226444.4060100@compulab.co.il> <50238F37.2030302@ti.com>
Message-ID: <5023B72D.9030005@compulab.co.il>

On 08/09/12 13:21, Peter Ujfalusi wrote:
> On 08/08/2012 04:06 PM, Igor Grinberg wrote:
>> Well, yes I know we will need to adjust the user space.
>> I wanted to change that for a long time and did not get to it...
>> Now, with your patches, it seems like the best time for doing this.
> 
> Done for the v2. You will have card named "cm-t3x".

Thanks!

-- 
Regards,
Igor.


From arnd at arndb.de  Thu Aug  9 09:17:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 9 Aug 2012 13:17:24 +0000
Subject: [PATCH] ARM: tegra: more regulator fixes for Harmony
In-Reply-To: <5022EBC0.5060102@wwwdotorg.org>
References: <1344037521-6157-1-git-send-email-swarren@wwwdotorg.org>
 <5022EBC0.5060102@wwwdotorg.org>
Message-ID: <201208091317.24816.arnd@arndb.de>

On Wednesday 08 August 2012, Stephen Warren wrote:
> > Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > ---
> > This is a fix for v3.6.
> 
> Arnd, Olof, I don't see this in the arm-soc fixes tree, although do see
> you've applied a bunch of patches since I posted this. Did it drop
> through the cracks?

Yes, you are right. I'm sorry I missed it at first. Applied to the
fixes branch now.

	Arnd


From u.kleine-koenig at pengutronix.de  Thu Aug  9 09:35:33 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu,  9 Aug 2012 15:35:33 +0200
Subject: [PATCH] ARM: imx/imx31-dt: drop selecting USE_OF
Message-ID: <1344519333-6446-1-git-send-email-u.kleine-koenig@pengutronix.de>

since commit
	3e62af8 (ARM: imx: select USE_OF)
ARM_MXC already selects USE_OF, so there is no need to repeat it for
MACH_IMX31_DT

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 419c292..6152a84 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -561,7 +561,6 @@ config MACH_BUG
 config MACH_IMX31_DT
 	bool "Support i.MX31 platforms from device tree"
 	select SOC_IMX31
-	select USE_OF
 	help
 	  Include support for Freescale i.MX31 based platforms
 	  using the device tree for discovery.
-- 
1.7.10.4



From matt at genesi-usa.com  Thu Aug  9 09:40:36 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 9 Aug 2012 08:40:36 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120809101947.GA8474@sirena.org.uk>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120809101947.GA8474@sirena.org.uk>
Message-ID: <CAKGA1bkT2GDXXXAgjG4ySfTxwO=4O7o30BLzLHCMZKDrR318xQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:19 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Aug 07, 2012 at 04:46:18PM -0500, Matt Sealey wrote:
>
> Yay for indentation!  It'd be good to rewrite your DT so you could cut
> down on that, at the minute it's not good for legibility.
>
>> +                                                     sw1_reg: sw1 {
>> +                                                             regulator-min-microvolt = <600000>;
>> +                                                             regulator-max-microvolt = <1375000>;
>> +                                                             regulator-boot-on;
>> +                                                             regulator-always-on;
>> +                                                     };
>
> This and many of your other regulators have voltage ranges specified but
> no consumers which doesn't make sense.  It looks awfully like you've
> just typed in the maximum range supported by the regulator which is most
> likely broken.
>
> You're also specifying both boot_on and always_on which again doesn't
> seem to make a lot of sense - boot_on mainly exists to help autoprobe,
> using it quite this routinely isn't too clever.

The reason they're set like that is legacy - that's how they're set up
in a kernel
(pre-DT) that we know works. Most of those ranges are directly from the Babbage
reference and stay like that in the Babbage DT too - so there's another broken
one nobody noticed. I know what those voltages should be, but we're
leaving that for another patch that restricts the range of voltages
(it works right
now, since there are no consumers, nothing CHANGES the voltages as
configured at U-Boot time, and anything not boot-on is just not listed
in the DT anyway, but some of them really need to stay on)

There are few consumers because the primary ones out there are the display
controllers and USB hubs and some other things. MMC should be a consumer
but since on one board we share two MMC slots with one regulator we don't
want anyone to change the voltage (it breaks spec anyway, since we can't
provide more than 3.15V with FSL's PMIC and it should be 3.3V by default)
and since you can't coordinate between MMC hosts on what the lowest voltage
both cards can support actually is.. having someone change it would be
bad.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From peter.ujfalusi at ti.com  Thu Aug  9 09:53:26 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 09 Aug 2012 16:53:26 +0300
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <20120809103600.GI24328@opensource.wolfsonmicro.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-5-git-send-email-peter.ujfalusi@ti.com>
 <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com> <50227837.10400@ti.com>
 <20120808144933.GC24328@opensource.wolfsonmicro.com>
 <50238E8A.5030902@ti.com>
 <20120809103600.GI24328@opensource.wolfsonmicro.com>
Message-ID: <5023C0D6.8040600@ti.com>

On 08/09/2012 01:36 PM, Mark Brown wrote:
> On Thu, Aug 09, 2012 at 01:18:50PM +0300, Peter Ujfalusi wrote:
>> On 08/08/2012 05:49 PM, Mark Brown wrote:
> 
>>> That makes sense if the GPIO is actively driven, open drain should be
>>> better here, but it's still a generic thing which it'd be nice to
>>> extract.
> 
>> To cover all of this in a generic way is not that straight forward IMHO.
> 
> The sequence is just:
> 
>   1. Enable mutes (at _PRE time)
>   2. Do whatever the device needs
>   3. Disable the mutes (at _POST time)
> 
> I'm not sure there's any reason for you not to use the internal mute
> even if the external mute is present but if there is that's the only
> thing that's weird here.  If there's no reason not to do it it just goes
> into step 2 and then it's fine, even if there is you can make it
> conditional in step 2.

Not sure, but it should not cause issues. The PIN is multiplexed between
GPIO6/PWM0/MUTE functionality.
For that matter probably I could just don't care about flags here and
configure the extmute (the internal one) all the time. Not sure, it has been a
long time I have dealt with the twl4030...

>> Sure I could do this:
>> hs_extmute: if only this is set we shall use the chip built in functionality
>> hs_extmute_gpio: if this is set we use the extmute feature but with external
>>                  GPIO.
> 
>> But both need to be documented and supported.
> 
> Is there any actual case where an external mute is supplied via a
> mechanism other than a GPIO, and if there is would it not either need
> its own DT property or already need to interact with the driver from
> code, making the DT property redundant?

Not with my knowledge. The only board using it is the zoom2 upstream. I know
other boards (not in upstream) which either uses the internal mute or GPIO.

> My thinking here is that the
> flag should be redundant because we already need to specify how we do
> the mute, what I'd expect is that we activate the external mute
> functionality as a result of being given another way of doing it so we
> don't need to provide a flag.

I perfectly understand your point. However how would you imagine this in the core?
We should have something similar to DAPM_SUPPLY which we can attach to the
widget which needs this sort of mute, but how big change we would need in the
core to do this I'm not sure.
I can take a look at this, but I would do it as a follow up series.

-- 
P?ter


From linux at arm.linux.org.uk  Thu Aug  9 09:57:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 14:57:55 +0100
Subject: imx6q restart is broken
In-Reply-To: <20120809122220.GB19617@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <20120809120144.GA19617@S2101-09.ap.freescale.net>
 <20120809122220.GB19617@S2101-09.ap.freescale.net>
Message-ID: <20120809135755.GR18957@n2100.arm.linux.org.uk>

On Thu, Aug 09, 2012 at 08:22:22PM +0800, Shawn Guo wrote:
> On Thu, Aug 09, 2012 at 08:01:47PM +0800, Shawn Guo wrote:
> > diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> > index 99afa74..1282b61 100644
> > --- a/arch/arm/include/asm/processor.h
> > +++ b/arch/arm/include/asm/processor.h
> > @@ -80,11 +80,18 @@ extern void release_thread(struct task_struct *);
> >  unsigned long get_wchan(struct task_struct *p);
> > 
> >  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> > -#define cpu_relax()                    smp_mb()
> > +#define __cpu_relax()                  smp_mb()
> >  #else
> > -#define cpu_relax()                    barrier()
> > +#define __cpu_relax()                  barrier()
> >  #endif
> > 
> > +#define cpu_relax()                                                    \
> > +({                                                                     \
> > +       static int i;                                                   \
> > +       if (i++ % 100)                                                  \
> 
> This should be 
> 
> 	if (i++ % 100 == 0)
> 
> But either way it fixes the problem.

Right, so it does sound like issuing dmb instructions in a tight loop
can bring a system to its knees.

While we can address it in the above way in the kernel, it points to
a much bigger problem - userspace can issue dmb instructions itself,
which means any user program can effectively take a system down.  Can
you confirm this by building and running the following program:

int main()
{
	while (1)
		asm("dmb");
}

Then try running some other programs.  If I'm correct, this should
result in the system becoming rather unresponsive.

Thanks.


From linux at arm.linux.org.uk  Thu Aug  9 10:01:37 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 15:01:37 +0100
Subject: imx6q restart is broken
In-Reply-To: <20120809135755.GR18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <20120809120144.GA19617@S2101-09.ap.freescale.net>
 <20120809122220.GB19617@S2101-09.ap.freescale.net>
 <20120809135755.GR18957@n2100.arm.linux.org.uk>
Message-ID: <20120809140137.GS18957@n2100.arm.linux.org.uk>

On Thu, Aug 09, 2012 at 02:57:55PM +0100, Russell King - ARM Linux wrote:
> Then try running some other programs.  If I'm correct, this should
> result in the system becoming rather unresponsive.

I should better describe what I mean by "unresponsive" - it won't lock
the system up (because the dmb loop will be interrupted from time to
time) but it should make it rather sluggish to deal with page faults on
other CPUs.


From cyril at ti.com  Thu Aug  9 10:10:18 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 9 Aug 2012 10:10:18 -0400
Subject: [PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <20120806111413.GB18957@n2100.arm.linux.org.uk>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <1343775898-28345-4-git-send-email-cyril@ti.com>
 <20120806111413.GB18957@n2100.arm.linux.org.uk>
Message-ID: <5023C4CA.4020402@ti.com>

Hi Russell,

On 8/6/2012 7:14 AM, Russell King - ARM Linux wrote:
> On Tue, Jul 31, 2012 at 07:04:39PM -0400, Cyril Chemparathy wrote:
>> This patch fixes up the types used when converting back and forth between
>> physical and virtual addresses.
>>
>> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
>>   arch/arm/include/asm/memory.h |   17 +++++++++++------
>>   1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
>> index 01c710d..4a0108f 100644
>> --- a/arch/arm/include/asm/memory.h
>> +++ b/arch/arm/include/asm/memory.h
>> @@ -157,22 +157,27 @@ extern unsigned long __pv_phys_offset;
>>
>>   extern unsigned long __pv_offset;
>>
>> -static inline unsigned long __virt_to_phys(unsigned long x)
>> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "add", __pv_offset);
>>   	return t;
>>   }
>>
>> -static inline unsigned long __phys_to_virt(unsigned long x)
>> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>>   {
>>   	unsigned long t;
>>   	early_patch_imm8(x, t, "sub", __pv_offset);
>>   	return t;
>>   }
>>   #else
>> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
>> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
>> +
>> +#define __virt_to_phys(x)		\
>> +	((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET)
>> +
>> +#define __phys_to_virt(x)		\
>> +	((unsigned long)((phys_addr_t)(x) - PHYS_OFFSET + PAGE_OFFSET))
>> +
>>   #endif
>>   #endif
>>
>> @@ -207,14 +212,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>>
>>   static inline void *phys_to_virt(phys_addr_t x)
>>   {
>> -	return (void *)(__phys_to_virt((unsigned long)(x)));
>> +	return (void *)__phys_to_virt(x);
>>   }
>>
>>   /*
>>    * Drivers should NOT use these either.
>>    */
>>   #define __pa(x)			__virt_to_phys((unsigned long)(x))
>> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
>> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>>   #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
>
> This as a whole does not fill me with a great amount of enthusiasm,
> because it breaks some of the typechecking that we have here.
>
> The whole point of __phys_to_virt() and __virt_to_phys() is that they work
> on integer types, and warn if you dare to use them with pointers.  Adding
> a cast into them breaks that.
>
> The whole point is that the typecasting is explicitly inside phys_to_virt()
> and virt_to_phys() and not their macro counterparts.
>

The casts in __phys_to_virt() and __virt_to_phys() were necessary to 
widen integer types in case of LPAE without phys/virt patching.

I assume that this specifically is the typecasting that you are 
concerned about.  Would it be better then to convert these to inlines 
then?  That way we could get the typechecking, with proper widening as 
needed.

-- 
Thanks
- Cyril


From broonie at opensource.wolfsonmicro.com  Thu Aug  9 10:17:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 15:17:28 +0100
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1bkT2GDXXXAgjG4ySfTxwO=4O7o30BLzLHCMZKDrR318xQ@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120809101947.GA8474@sirena.org.uk>
 <CAKGA1bkT2GDXXXAgjG4ySfTxwO=4O7o30BLzLHCMZKDrR318xQ@mail.gmail.com>
Message-ID: <20120809141727.GW24328@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 08:40:36AM -0500, Matt Sealey wrote:

> The reason they're set like that is legacy - that's how they're set up
> in a kernel
> (pre-DT) that we know works. Most of those ranges are directly from the Babbage
> reference and stay like that in the Babbage DT too - so there's another broken
> one nobody noticed. I know what those voltages should be, but we're
> leaving that for another patch that restricts the range of voltages
> (it works right
> now, since there are no consumers, nothing CHANGES the voltages as
> configured at U-Boot time, and anything not boot-on is just not listed
> in the DT anyway, but some of them really need to stay on)

Oh dear.  Well, no reason to propagate the breakage - if nothing else it
might well explode if we start doing more aggressive power saving with
the regulators (like having an option for dropping down to the lower end
of the voltage ranges in late init which I keep contemplating, it'd
explode with the boards doing this).

> There are few consumers because the primary ones out there are the display
> controllers and USB hubs and some other things. MMC should be a consumer
> but since on one board we share two MMC slots with one regulator we don't
> want anyone to change the voltage (it breaks spec anyway, since we can't
> provide more than 3.15V with FSL's PMIC and it should be 3.3V by default)
> and since you can't coordinate between MMC hosts on what the lowest voltage
> both cards can support actually is.. having someone change it would be
> bad.

It's not a problem to have fixed voltages, the problem is the
combination of specifying voltage ranges in conjunction with not having
anything there that wants to change the voltage.  Especially with things
like the audio supply, it's clear what that's for and it'd normally get
upset with the voltage changing.


From shawn.guo at linaro.org  Thu Aug  9 10:24:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 9 Aug 2012 22:24:47 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120809140137.GS18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <20120809120144.GA19617@S2101-09.ap.freescale.net>
 <20120809122220.GB19617@S2101-09.ap.freescale.net>
 <20120809135755.GR18957@n2100.arm.linux.org.uk>
 <20120809140137.GS18957@n2100.arm.linux.org.uk>
Message-ID: <20120809142444.GC19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 03:01:37PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 09, 2012 at 02:57:55PM +0100, Russell King - ARM Linux wrote:
> > Then try running some other programs.  If I'm correct, this should
> > result in the system becoming rather unresponsive.
> 
> I should better describe what I mean by "unresponsive" - it won't lock
> the system up (because the dmb loop will be interrupted from time to
> time) but it should make it rather sluggish to deal with page faults on
> other CPUs.

You are right.  I'm seeing exactly the "unresponsive" you describe here
after launching that little program.

-- 
Regards,
Shawn



From vaibhav.bedia at ti.com  Thu Aug  9 10:24:15 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 9 Aug 2012 14:24:15 +0000
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <alpine.DEB.2.00.1208081411010.6819@utopia.booyaka.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
 <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1208081411010.6819@utopia.booyaka.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D121433EB34624@DBDE01.ent.ti.com>

Hi Paul,

On Thu, Aug 09, 2012 at 01:49:34, Paul Walmsley wrote:
> Hi Vaibhav
> 
> On Wed, 8 Aug 2012, Bedia, Vaibhav wrote:
> 
> > On Wed, Aug 08, 2012 at 19:35:50, Paul Walmsley wrote:
> >
> > > It doesn't seem to me that this would necessarily always be an error.  
> > > Suppose some init code to create cpsw devices is running on an OMAP3430.  
> > > Then a omap_hwmod_for_each_by_class() that doesn't locate anything 
> > > wouldn't be an error, right?
> > 
> > Well, I think a failed lookup operation will be a bit expensive since it
> > iterates over the whole list of registered hwmods and hence put in the
> > pr_err().
> 
> If performance is a serious problem there, we can maintain a list of hwmod 
> pointers inside each struct omap_hwmod_class, updated when the hwmods are 
> registered.  But as far as I know, performance hasn't been an issue here 
> yet.  If performance is the real motivation, I'd rather see an 
> implementation of per-class lists as described above.
> 

Ok. I'll try to do some profiling using a timer to see how much time we
spend over here. On AM335x there are 2 such lookups, one for the dma
and one for the mcbsp. I could get this done today but will get to it
tomorrow. Based on how this goes I'll try out the omap_hwmod_class list
like you suggested.

> > But I don't see how the SoC specific example that you pointed out
> > could be handled without putting in cpu_is_* checks in the registration
> > process itself :(
> 
> Hmm, why not?
> 
> To continue the earlier example, the init code in the platform code simply 
> calls omap_hwmod_for_each_by_class(), and creates the appropriate device 
> if anything was found.  If no cpsw IP blocks are present on a given SoC, 
> nothing would happen.  No cpu_is_*() would be needed.
> 
> 

I was thinking of avoiding the lookup process itself and hence mentioned
the need for cpu checks surrounding the platform init code. The current
API does help avoid all this in an excellent manner.

Regards,
Vaibhav B. 



From zonque at gmail.com  Thu Aug  9 10:28:51 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 09 Aug 2012 16:28:51 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
 <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>
Message-ID: <5023C923.3080808@gmail.com>

On 07.08.2012 08:49, Linus Walleij wrote:
> On Mon, Aug 6, 2012 at 10:44 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> On Saturday 28 July 2012, Haojian Zhuang wrote:
>>> +Required subnode-properties:
>>> +- marvell,pins : An array of strings. Each string contains the name of a pin
>>> +                 or group.
>>> +- marvell,function     : A string containing the name of the function to mux to the
>>> +                 pin or group.
>>> +- marvell,drive-strength : An integer value that means the drive strength of a
>>> +                        pin.
>>> +- marvell,pull-up      : The property means a pin is pull up for input.
>>> +- marvell,pull-down : The property means a pin is pull down for input.
>>> +- marvell,lowpower-pull-up : The property means a pin is pull up for input in
>>> +                         sleep state.
>>> +- marvell,lowpower-pull-down : The property means a pin is pull down for input
>>> +                           in sleep state.
>>> +- marvell,lowpower-drive-high : The property means a pin is driving high for
>>> +                            output in sleep state.
>>> +- marvell,lowpower-drive-low : The property means a pin is driving low for
>>> +                           output in sleep state.
>>> +- marvell,lowpower-float : The property means a pin is float in sleep state.
>>> +- marvell,lowpower-zero : The property means a pin is not configured in sleep
>>> +                       state.
>>
>> These (or most of them) look like they are not very Marvell specific. Should
>> we try to standardize the way they are set across different bindings?
> 
> If the device tree properties are to be standardized, the driver should be
> moved over to using generic pin config (drivers/pinctrl/pinconf-generic.c,
> include/linux/pinctrl/pinconf-generic.h) too, or it makes no sense.
> 
> So please augment the PXA driver to use these, then move the generic
> bindings to pinconf-generic.txt or something.
> 
> If pinconf-generic needs extending/augmenting in the process, just do it,
> it's supposed to be generic...

I am looking at the generic pinctrl code right now and I wonder if the
following approach would be ok:

- each driver that calls pinctrl_register() has its own dt_match_table
entry, so the 'compatible' part of the bindings is specific to a pin
controller chip.
- introduce a pinctrl_parse_of(struct of_node *) and call that after the
driver has added all its pins. That function walks all the children of
the given node and uses the callbacks provided by the driver to do the
actual work.
- Unfortunately, we can't parse the node from pinctrl_register() as the
gpio ranges are only added after that by the drivers.

If that sounds good, I can come up with a patch.


Thanks,
Daniel



From matt at genesi-usa.com  Thu Aug  9 10:29:39 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 9 Aug 2012 09:29:39 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
Message-ID: <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>

On Wed, Aug 8, 2012 at 12:19 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Matt,
>
> On Wed, Aug 8, 2012 at 1:55 PM, Matt Sealey <matt at genesi-usa.com> wrote:
>
> ...
>> or any setup at all for this. What's stopping this right now is you
>> need a new U-Boot which we
>> didn't release or mainline because we are still testing it (old U-Boot
>> shipped on the boards
>> cannot boot device tree anyway). While the number of users of this is
>
> Actually you can boot a device tree kernel even on old bootloaders
> that do not support dt.
>
> You need to select:
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
>
> Then,
>
> make -j4 zImage
> make imx51-babbage.dtb
> cat arch/arm/boot/zImage arch/arm/boot/ imx51-babbage.dtb  >
> arch/arm/boot/zImage_dtb
> mkimage -A arm -O linux -T kernel -C none -a 0x90008000 -e 0x90008000
> -n Linux -d arch/arm/boot/zImage_dtb arch/arm/boot/uImage
>
> and boot this generated uImage the same way as you used to do in the
> non-dt case.

That's true, but we don't have our customers compile their own kernels
if they can help it, and appending a dtb to the end of a kernel isn't
part of distro packaging so it just doesn't get done yet... We'd need
to update a bunch of scripts, test them, and then deal with the
frightening scenario of appending a dtb to a kernel *and* passing the
address of the filesystem version (usually the one appended!) - hoping
either works. It's too much testing. We'd rather update everyone to a
new U-Boot that works, and deal with a single point on that end, that
can boot the legacy kernel (machine id matches, legacy boot works on
old kernel) and the new kernel alike.

All of this is coming from development branches we have here, and
we're pushing it to mainline as a convenience for everyone concerned.

What we've got on the test plan is;

1) Old U-Boot, Old Kernel. This works already for years.
2) New U-Boot, Old Kernel. This works, well tested.
3) New U-Boot, New Kernel+DTB. This works or we wouldn't be sending patches.

The Old U-Boot, New Kernel doesn't make sense for us if the New U-Boot
is all that's required to retain functionality.

The reason the new kernel depends on the new U-Boot is we're trying to
do all pinmux configuration in U-Boot (and we do in-house, and it
works). No pinctrl stuff in the kernel or device tree is required at
this point. The Old Kernel will remux a few things redundantly or
change drive strengths or whatever or add hysteresis to the UART port
which is not board-burning but is not really necessary, but it will
work. The new kernel will just be able to do what it does out of the
box, which is how it should be (hence why I object to adding pinctrl
setup...)

--
Matt Sealey <matt at genesi-usa.com>


From matt at genesi-usa.com  Thu Aug  9 10:32:59 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 9 Aug 2012 09:32:59 -0500
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <20120809102414.GA17588@linaro.org>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
 <20120809102414.GA17588@linaro.org>
Message-ID: <CAKGA1bniQK9DbZudrHk1mA7FyDZkQzBJbWNUFTFW3pc_2A2x4g@mail.gmail.com>

Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Thu, Aug 9, 2012 at 5:24 AM, Dave Martin <dave.martin at linaro.org> wrote:
> On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:
>
> [...]
>
>> I'm going to do a trapse through and find where Russell nacked Dave's
>> thumb-aware
>> rewrite.. would you mind if you have any of these boards seeing if it
>> really DOES
>
> There was no NAK because I didn't get as far as posting the patch,

http://lists.arm.linux.org.uk/lurker/message/20111202.133911.393b6e28.en.html

You did, twice :)

> mostly because of the doubt about whether this code is ever relevant
> on Thumb2-capable hardware.

It's not, but it does break the build, and without disabling phyCORE boards for
Thumb2 it will always break the build..

> If somebody with some old imx hardware that definitely relies on this
> wants to pick it up and test it, it might still be useful.
>
> I don't know whether I still have the original patch, but I think the
> only think I did was to swap the roles of r13 and r12.  In the original
> code r12 is only used as a base register, which is permissible usage
> for r13 in Thumb-2.  Those two registers appear private to the fiq
> handler, so I don't think the change will break anything, but I'd be
> more confident is somebody is able to test it.
>
> Cheers
> ---Dave
>
> diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
> index 8397a2d..3589afb 100644
> --- a/arch/arm/plat-mxc/ssi-fiq.S
> +++ b/arch/arm/plat-mxc/ssi-fiq.S
> @@ -35,19 +35,19 @@
>                 .global imx_ssi_fiq_tx_buffer
>
>  imx_ssi_fiq_start:
> -               ldr r12, imx_ssi_fiq_base
> +               ldr r13, imx_ssi_fiq_base
>
>                 /* TX */
>                 ldr r11, imx_ssi_fiq_tx_buffer
>
>                 /* shall we send? */
> -               ldr r13, [r12, #SSI_SIER]
> -               tst r13, #SSI_SIER_TFE0_EN
> +               ldr r12, [r13, #SSI_SIER]
> +               tst r12, #SSI_SIER_TFE0_EN
>                 beq 1f
>
>                 /* TX FIFO empty? */
> -               ldr r13, [r12, #SSI_SISR]
> -               tst r13, #SSI_SISR_TFE0
> +               ldr r12, [r13, #SSI_SISR]
> +               tst r12, #SSI_SISR_TFE0
>                 beq 1f
>
>                 mov r10, #0x10000
> @@ -56,34 +56,34 @@ imx_ssi_fiq_start:
>
>                 add r11, r11, r10
>
> -               ldrh r13, [r11]
> -               strh r13, [r12, #SSI_STX0]
> +               ldrh r12, [r11]
> +               strh r12, [r13, #SSI_STX0]
>
> -               ldrh r13, [r11, #2]
> -               strh r13, [r12, #SSI_STX0]
> +               ldrh r12, [r11, #2]
> +               strh r12, [r13, #SSI_STX0]
>
> -               ldrh r13, [r11, #4]
> -               strh r13, [r12, #SSI_STX0]
> +               ldrh r12, [r11, #4]
> +               strh r12, [r13, #SSI_STX0]
>
> -               ldrh r13, [r11, #6]
> -               strh r13, [r12, #SSI_STX0]
> +               ldrh r12, [r11, #6]
> +               strh r12, [r13, #SSI_STX0]
>
>                 add r10, #8
> -               lsr r13, r8, #16        /* r13: buffer size */
> -               cmp r10, r13
> -               lslgt r8, r13, #16
> +               lsr r12, r8, #16        /* r12: buffer size */
> +               cmp r10, r12
> +               lslgt r8, r12, #16
>                 addle r8, #8
>  1:
>                 /* RX */
>
>                 /* shall we receive? */
> -               ldr r13, [r12, #SSI_SIER]
> -               tst r13, #SSI_SIER_RFF0_EN
> +               ldr r12, [r13, #SSI_SIER]
> +               tst r12, #SSI_SIER_RFF0_EN
>                 beq 1f
>
>                 /* RX FIFO full? */
> -               ldr r13, [r12, #SSI_SISR]
> -               tst r13, #SSI_SISR_RFF0
> +               ldr r12, [r13, #SSI_SISR]
> +               tst r12, #SSI_SISR_RFF0
>                 beq 1f
>
>                 ldr r11, imx_ssi_fiq_rx_buffer
> @@ -94,31 +94,31 @@ imx_ssi_fiq_start:
>
>                 add r11, r11, r10
>
> -               ldr r13, [r12, #SSI_SACNT]
> -               tst r13, #SSI_SACNT_AC97EN
> +               ldr r12, [r13, #SSI_SACNT]
> +               tst r12, #SSI_SACNT_AC97EN
>
> -               ldr r13, [r12, #SSI_SRX0]
> -               strh r13, [r11]
> +               ldr r12, [r13, #SSI_SRX0]
> +               strh r12, [r11]
>
> -               ldr r13, [r12, #SSI_SRX0]
> -               strh r13, [r11, #2]
> +               ldr r12, [r13, #SSI_SRX0]
> +               strh r12, [r11, #2]
>
>                 /* dummy read to skip slot 12 */
> -               ldrne r13, [r12, #SSI_SRX0]
> +               ldrne r12, [r13, #SSI_SRX0]
>
> -               ldr r13, [r12, #SSI_SRX0]
> -               strh r13, [r11, #4]
> +               ldr r12, [r13, #SSI_SRX0]
> +               strh r12, [r11, #4]
>
> -               ldr r13, [r12, #SSI_SRX0]
> -               strh r13, [r11, #6]
> +               ldr r12, [r13, #SSI_SRX0]
> +               strh r12, [r11, #6]
>
>                 /* dummy read to skip slot 12 */
> -               ldrne r13, [r12, #SSI_SRX0]
> +               ldrne r12, [r13, #SSI_SRX0]
>
>                 add r10, #8
> -               lsr r13, r9, #16        /* r13: buffer size */
> -               cmp r10, r13
> -               lslgt r9, r13, #16
> +               lsr r12, r9, #16        /* r12: buffer size */
> +               cmp r10, r12
> +               lslgt r9, r12, #16
>                 addle r9, #8
>
>  1:
>


From dave.martin at linaro.org  Thu Aug  9 10:50:05 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 9 Aug 2012 15:50:05 +0100
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <CAKGA1bniQK9DbZudrHk1mA7FyDZkQzBJbWNUFTFW3pc_2A2x4g@mail.gmail.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
 <20120809102414.GA17588@linaro.org>
 <CAKGA1bniQK9DbZudrHk1mA7FyDZkQzBJbWNUFTFW3pc_2A2x4g@mail.gmail.com>
Message-ID: <20120809145005.GB17588@linaro.org>

On Thu, Aug 09, 2012 at 09:32:59AM -0500, Matt Sealey wrote:
> Matt Sealey <matt at genesi-usa.com>
> Product Development Analyst, Genesi USA, Inc.
> 
> 
> On Thu, Aug 9, 2012 at 5:24 AM, Dave Martin <dave.martin at linaro.org> wrote:
> > On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:
> >
> > [...]
> >
> >> I'm going to do a trapse through and find where Russell nacked Dave's
> >> thumb-aware
> >> rewrite.. would you mind if you have any of these boards seeing if it
> >> really DOES
> >
> > There was no NAK because I didn't get as far as posting the patch,
> 
> http://lists.arm.linux.org.uk/lurker/message/20111202.133911.393b6e28.en.html
> 
> You did, twice :)

Well, I meant that I had not posted it as a stand-alone patch for
inclusion; I only posted it when commenting on other threads.

> > mostly because of the doubt about whether this code is ever relevant
> > on Thumb2-capable hardware.
> 
> It's not, but it does break the build, and without disabling phyCORE boards for
> Thumb2 it will always break the build..

If you want me to push it, let me know.  I don't think this should get
merged without some Tested-bys for hardware where the FIQ stuff actually
gets used.

The older post would be the one to use, since that at least got a
reasonable level of build testing.

Cheers
---Dave


From will.deacon at arm.com  Thu Aug  9 10:49:53 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 9 Aug 2012 15:49:53 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
Message-ID: <20120809144953.GC18486@mudshark.cambridge.arm.com>

Hi Nicolas,

Thanks for the replies.

On Thu, Aug 09, 2012 at 06:12:15AM +0100, Nicolas Pitre wrote:
> On Tue, 7 Aug 2012, Will Deacon wrote:
> > diff --git a/kernel/mutex.c b/kernel/mutex.c
> > index a307cc9..27b7887 100644
> > --- a/kernel/mutex.c
> > +++ b/kernel/mutex.c
> > @@ -170,7 +170,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
> >                 if (owner && !mutex_spin_on_owner(lock, owner))
> >                         break;
> >  
> > -               if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> > +               if (atomic_cmpxchg(&lock->count, 1, -1) == 1) {
> >                         lock_acquired(&lock->dep_map, ip);
> >                         mutex_set_owner(lock);
> >                         preempt_enable();
> > 
> > 
> > All comments welcome.
> 
> Well... after thinking about this for a while, I came to the conclusion 
> that the mutex_spin_on_owner code is indeed breaking the contract 
> between the xchg lock fast path and the slow path.  The xchg fast path 
> will always set the count to 0 and rely on the slow path to restore a 
> possible pre-existing negative count.  So the above change would be 
> needed for correctness in the xchg case, even if it always forces the 
> unlock into the slow path.

Great, so we agree on that.

> As I mentioned previously, we don't want to force the slow path in all 
> cases though.  The atomic decrement based fast path doesn't need that, 
> so I'd suggest this fix instead:

One minor typo and a suggested alternative below...

> diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> index 580a6d35c7..60964844c8 100644
> --- a/include/asm-generic/mutex-xchg.h
> +++ b/include/asm-generic/mutex-xchg.h
> @@ -108,4 +108,6 @@ __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
>  	return prev;
>  }
>  
> +#define __MUTEX_XCHG_FAST_PATH
> +
>  #endif
> diff --git a/kernel/mutex.c b/kernel/mutex.c
> index a307cc9c95..c6a26a4f1c 100644
> --- a/kernel/mutex.c
> +++ b/kernel/mutex.c
> @@ -161,6 +161,7 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
>  
>  	for (;;) {
>  		struct task_struct *owner;
> +		int locked_val;
>  
>  		/*
>  		 * If there's an owner, wait for it to either
> @@ -170,7 +171,19 @@ __mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
>  		if (owner && !mutex_spin_on_owner(lock, owner))
>  			break;
>  
> -		if (atomic_cmpxchg(&lock->count, 1, 0) == 1) {
> +#ifdef __MUTEX_XCHG_FAST_PATH
> +		/*
> +		 * The fast path based on xchg sets a transient 0 count,
> +		 * relying on the slow path to restore a possible
> +		 * pre-existing contended count.  Without checking the
> +		 * waiters' list we must presume possible contension here.

s/contension/contention/

> +		 */
> +		locked_val = -1;
> +#else
> +		locked_val = 0;
> +#endif
> +
> +		if (atomic_cmpxchg(&lock->count, 1, locked_val) == 1) {
>  			lock_acquired(&lock->dep_map, ip);
>  			mutex_set_owner(lock);
>  			preempt_enable();
> 
> That would be needed for the stable tree as well.
> 
> A further cleanup could remove all definitions of 
> __mutex_slowpath_needs_to_unlock() given that they're all set to 1 
> except for the xchg fast path, in which case __MUTEX_XCHG_FAST_PATH 
> could be reused instead.

I think we could actually fix this entirely in mutex-xchg.h by doing
something in fastpath_lock similar to what we do for trylock:


diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 580a6d3..c082e99 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -25,8 +25,19 @@
 static inline void
 __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
-       if (unlikely(atomic_xchg(count, 0) != 1))
-               fail_fn(count);
+       int prev = atomic_xchg(count, 0);
+
+       if (unlikely(prev != 1)) {
+               if (prev < 0)
+                       /*
+                        * The lock was contended, so we need to restore
+                        * its original state to ensure that any waiting
+                        * tasks are woken up by the unlock slow path.
+                        */
+                       prev = atomic_xchg(count, prev);
+               if (prev != 1)
+                       fail_fn(count);
+       }
 }
 
 /**


What do you reckon?

> Of course that might tilt the balance towards using mutex-dec.h on ARM 
> v6 and above instead of mutex-xchg.h.  But that is an orthogonal issue, 
> and that doesn't remove the need for fixing the xchg based case for 
> correctness.

I'll do some hackbench runs against mutex-dec once we've decided on the final
xchg code. If it's faster, I'll submit a patch for ARM.

Cheers,

Will


From khilman at ti.com  Thu Aug  9 10:58:44 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 09 Aug 2012 07:58:44 -0700
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <CAC83ZvLKk71O=+9U16FoTUU_-ffg+iJsHPgnJx+bzbHhBDXzhQ@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Thu, 9 Aug 2012 09:36:05 +0530")
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
 <87k3x9wbrk.fsf@ti.com>
 <CAC83ZvLKk71O=+9U16FoTUU_-ffg+iJsHPgnJx+bzbHhBDXzhQ@mail.gmail.com>
Message-ID: <87hascgli3.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

> On Wed, Aug 8, 2012 at 10:40 PM, Kevin Hilman <khilman at ti.com> wrote:
>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>
>>> Add *remove* callback so that necessary cleanup operations are
>>> performed when device is unregistered. The device is deleted
>>> from the list and associated clock handle is released by
>>> calling clk_put() and irq descriptor is released using the
>>> irq_free_desc() api.
>>>
>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>> Reported-by: Paul Walmsley <paul at pwsan.com>
>>> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
>>> Cc: Kevin Hilman <khilman at ti.com>
>>> Cc: Rajendra Nayak <rnayak at ti.com>
>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>> Cc: Cousson, Benoit <b-cousson at ti.com>
>>> Cc: Paul Walmsley <paul at pwsan.com>
>>> ---
>>> v2:
>>> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>>> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>>>
>>> (1) Use irq_free_descs() instead of irq_free_desc().
>>>     Besides, irq_free_desc() was using wrong parameter,
>>>     irq_base, instead of bank->irq.
>>> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>>>     in order to avoid exception warnings.
>>>
>>> (3) pm_runtime_disable() added so that bind can happen successfully
>>>
>>> Test Detail:
>>> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>>>
>>> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>>>
>>> Step 3: Execute read/write GPIO test case.
>>
>> What happens when GPIOs are in use (requested)?
> If I try to unbind a currently active GPIO bank then I see an exception
> after the irq descriptor is freed by the remove. I believe this is expected
> because interrupt raised by the system would not be handled.

... and the GPIO is still configured to trigger interrupts.

The point is that there is lots to cleanup/unconfigure properly for this
to work properly.

Kevin

> [   18.859405] irq_free_descs: calling free_desc(192)...
> [   18.866180] irq_free_descs: calling free_desc(192)...
> [   18.872680] irq_free_descs: calling free_desc(192)...
> [   18.877990] irq_free_descs: calling free_desc(192)...
> [   18.883270] irq_free_descs: calling free_desc(192)...
> [   18.888549] irq_free_descs: calling free_desc(192)...
> [   18.893859] irq_free_descs: calling free_desc(192)...
> [   18.899139] irq_free_descs: calling free_desc(192)...
> [   18.904418] irq_free_descs: calling free_desc(192)...
> [   18.909729] irq_free_descs: calling free_desc(192)...
> [   18.915008] irq_free_descs: calling free_desc(192)...
> [   18.920288] irq_free_descs: calling free_desc(192)...
> [   18.925598] irq_free_descs: calling free_desc(192)...
> [   18.930877] irq_free_descs: calling free_desc(192)...
> [   18.936157] irq_free_descs: calling free_desc(192)...
> [   18.941467] irq_free_descs: calling free_desc(192)...
> [   18.946746] irq_free_descs: calling free_desc(192)...
> [   18.952026] irq_free_descs: calling free_desc(192)...
> [   18.957336] irq_free_descs: calling free_desc(192)...
> [   18.962615] irq_free_descs: calling free_desc(192)...
> [   18.967895] irq_free_descs: calling free_desc(192)...
> [   18.973205] irq_free_descs: calling free_desc(192)...
> [   18.978485] irq_free_descs: calling free_desc(192)...
> [   18.983764] irq_free_descs: calling free_desc(192)...
> [   18.989074] irq_free_descs: calling free_desc(192)...
> [   18.994354] irq_free_descs: calling free_desc(192)...
> [   18.999633] irq_free_descs: calling free_desc(192)...
> [   19.004913] irq_free_descs: calling free_desc(192)...
> [   19.010223] irq_free_descs: calling free_desc(192)...
> [   19.015502] irq_free_descs: calling free_desc(192)...
> [   19.020782] irq_free_descs: calling free_desc(192)...
> [   19.026092] irq_free_descs: calling free_desc(192)...
> [   19.032440] irq 194, desc: c072f340, depth: 1, count: 0, unhandled: 0
> [   19.039154] ->handle_irq():  c00a3e08, handle_bad_irq+0x0/0x260
> [   19.045379] ->irq_data.chip(): c078ff7c, no_irq_chip+0x0/0x5c
> [   19.051391] ->action(): ef0d42c0
> [   19.054748] ->action->handler(): c0399ee0, ks8851_irq+0x0/0x1c
> [   19.060852]    IRQ_NOPROBE set
> [   19.064056]  IRQ_NOREQUEST set
> [   19.067230] Unable to handle kernel paging request at virtual address 203a6c9
> [   19.074768] pgd = c0004000
> [   19.077606] [203a6c99] *pgd=00000000
> [   19.081329] Internal error: Oops: 5 [#1] SMP ARM
> [   19.086151] Modules linked in:
> [   19.089355] CPU: 0    Not tainted  (3.6.0-rc1-00003-g43a916d-dirty #885)
> [   19.096374] PC is at gpio_irq_handler+0x7c/0x26c
> [   19.101165] LR is at handle_bad_irq+0x1cc/0x260
> [   19.105895] pc : [<c02e13b0>]    lr : [<c00a3fd4>]    psr: 60000093
> [   19.105895] sp : c0725df8  ip : 00006fc6  fp : 00000001
> [   19.117889] r10: 00000000  r9 : fa05502c  r8 : 00000020
> [   19.123352] r7 : 00000000  r6 : 00000000  r5 : 00000000  r4 : ef0bbe10
> [   19.130157] r3 : ef0c1980  r2 : 203a6c65  r1 : 00000034  r0 : 00000000
> [   19.136993] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kel
> [   19.144714] Control: 10c53c7d  Table: ae89804a  DAC: 00000017
> [   19.150695] Process swapper/0 (pid: 0, stack limit = 0xc07242f8)
> [   19.156982] Stack: (0xc0725df8 to 0xc0726000)
> [   19.161529] 5de0:                                                       c0740
> [   19.170074] 5e00: c0724000 c0724000 c07440d8 c07224a4 0000003e 00000000 c0740
> [   19.178619] 5e20: c0725edc c00a3670 000001da c0015380 fa24010c c0742d30 c0720
> [   19.187164] 5e40: 00000001 c000846c c0746980 c04f8c74 20000013 ffffffff c0724
> [   19.195709] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
> [   19.204223] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
> [   19.212768] 5ea0: 20000013 ffffffff c0724000 c007425c 00000002 00000000 c0077
> [   19.221313] 5ec0: ef320b00 c0746980 00000000 c1530ac0 ef320b00 c0722ac0 c0720
> [   19.229858] 5ee0: c152ec20 c00696cc 00000000 00000000 c0724000 c0724000 c1524
> [   19.238403] 5f00: c152ec20 c0015e14 c0722ac0 c0722ac0 c0722ac0 c0722ac0 c0720
> [   19.246948] 5f20: c0722ac0 c0722ac0 6e6b0f0d 00000004 00000000 00000000 c0080
> [   19.255493] 5f40: 00000001 00000000 00000000 501539bc 00000004 c0091654 c1528
> [   19.264038] 5f60: c07d55b8 5006c071 00000000 c008cab8 00000000 00000002 50064
> [   19.272552] 5f80: c0748078 c0724000 c07c0548 c0504510 c0747e60 00000000 411f8
> [   19.281097] 5fa0: 00000000 c0015e14 00000000 c0743e1c c07c0480 c07057dc bfffa
> [   19.289642] 5fc0: 00000000 c06d48d8 ffffffff ffffffff c06d4450 00000000 0000c
> [   19.298187] 5fe0: 00000000 10c53c7d c0742d08 c07057ac c0747e54 80008044 00000
> [   19.306732] [<c02e13b0>] (gpio_irq_handler+0x7c/0x26c) from [<c00a3670>] (ge)
> [   19.316558] [<c00a3670>] (generic_handle_irq+0x34/0x44) from [<c0015380>] (h)
> [   19.325744] [<c0015380>] (handle_IRQ+0x4c/0xac) from [<c000846c>] (gic_handl)
> [   19.334564] [<c000846c>] (gic_handle_irq+0x2c/0x60) from [<c04f8ee4>] (__irq)
> [   19.343292] Exception stack(0xc0725e60 to 0xc0725ea8)
> [   19.348571] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
> [   19.357116] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
> [   19.365631] 5ea0: 20000013 ffffffff
> [   19.369293] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c04f8c74>] (_raw_spin_)
> [   19.378570] [<c04f8c74>] (_raw_spin_unlock_irq+0x28/0x2c) from [<c007425c>] )
> [   19.388732] [<c007425c>] (finish_task_switch+0x84/0x198) from [<c04f7760>] ()
> [   19.398193] [<c04f7760>] (__schedule+0x404/0x870) from [<c0015e14>] (cpu_idl)
> [   19.406768] [<c0015e14>] (cpu_idle+0xe8/0x114) from [<c06d48d8>] (start_kern)
> [   19.415466] Code: e59480e4 e1d311b4 e5d36034 e1a0a81b (e7920001)
> [   19.421844] ---[ end trace 3eb9bf4b81babe15 ]---
> [   19.426666] Kernel panic - not syncing: Fatal exception in interrupt
> [   19.433288] CPU1: stopping
> [   19.436157] [<c001beac>] (unwind_backtrace+0x0/0xf4) from [<c0019db4>] (hand)
> [   19.445220] [<c0019db4>] (handle_IPI+0x130/0x15c) from [<c0008498>] (gic_han)
> [   19.454223] [<c0008498>] (gic_handle_irq+0x58/0x60) from [<c04f8ee4>] (__irq)
> [   19.462951] Exception stack(0xef06ff88 to 0xef06ffd0)
> [   19.468231] ff80:                   c079f960 c079f960 00000000 00000000 ef068
> [   19.476745] ffa0: c0504510 c0747e60 00000000 411fc092 c0748078 00000000 00000
> [   19.485290] ffc0: c0015570 c0015574 60000113 ffffffff
> [   19.490570] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c0015574>] (default_id)
> [   19.499114] [<c0015574>] (default_idle+0x20/0x44) from [<c0015dc8>] (cpu_idl)
> [   19.507659] [<c0015dc8>] (cpu_idle+0x9c/0x114) from [<804f1d94>] (0x804f1d94)
> ---
> Tarun
>>
>> Kevin
>>
>>>  drivers/gpio/gpio-omap.c |   35 +++++++++++++++++++++++++++++++++++
>>>  1 files changed, 35 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>> index e6efd77..50de875 100644
>>> --- a/drivers/gpio/gpio-omap.c
>>> +++ b/drivers/gpio/gpio-omap.c
>>> @@ -1152,6 +1152,40 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>>>       return ret;
>>>  }
>>>
>>> +/**
>>> + * omap_gpio_remove - cleanup a registered gpio device
>>> + * @pdev:       pointer to current gpio platform device
>>> + *
>>> + * Called by driver framework whenever a gpio device is unregistered.
>>> + * GPIO is deleted from the list and associated clock handle freed.
>>> + */
>>> +static int __devexit omap_gpio_remove(struct platform_device *pdev)
>>> +{
>>> +     struct device *dev = &pdev->dev;
>>> +     struct gpio_bank *bank;
>>> +     unsigned long flags;
>>> +     int ret = -EINVAL;
>>> +
>>> +     list_for_each_entry(bank, &omap_gpio_list, node) {
>>> +             spin_lock_irqsave(&bank->lock, flags);
>>> +             if (bank->dev == dev) {
>>> +                     clk_put(bank->dbck);
>>> +                     list_del(&bank->node);
>>> +                     ret = 0;
>>> +                     spin_unlock_irqrestore(&bank->lock, flags);
>>> +                     break;
>>> +             }
>>> +             spin_unlock_irqrestore(&bank->lock, flags);
>>> +     }
>>> +
>>> +     if (!ret) {
>>> +             pm_runtime_disable(bank->dev);
>>> +             irq_free_descs(bank->irq_base, bank->width);
>>> +     }
>>> +
>>> +     return ret;
>>> +}
>>> +
>>>  #ifdef CONFIG_ARCH_OMAP2PLUS
>>>
>>>  #if defined(CONFIG_PM_RUNTIME)
>>> @@ -1478,6 +1512,7 @@ MODULE_DEVICE_TABLE(of, omap_gpio_match);
>>>
>>>  static struct platform_driver omap_gpio_driver = {
>>>       .probe          = omap_gpio_probe,
>>> +     .remove = __devexit_p(omap_gpio_remove),
>>>       .driver         = {
>>>               .name   = "omap_gpio",
>>>               .pm     = &gpio_pm_ops,
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From khilman at ti.com  Thu Aug  9 11:00:50 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 09 Aug 2012 08:00:50 -0700
Subject: [PATCH v2 1/2] cpufreq: OMAP: Handle missing frequency table on
 SMP systems
In-Reply-To: <201208091132.14992.rjw@sisk.pl> (Rafael J. Wysocki's message of
 "Thu, 9 Aug 2012 11:32:14 +0200")
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
 <1344496102-24451-2-git-send-email-rnayak@ti.com>
 <201208091132.14992.rjw@sisk.pl>
Message-ID: <87d330glel.fsf@ti.com>

"Rafael J. Wysocki" <rjw at sisk.pl> writes:

> On Thursday, August 09, 2012, Rajendra Nayak wrote:
>> On OMAP4, if the first CPU fails to get a valid frequency table (this
>> could happen if the platform does not register any OPP table), the
>> subsequent CPU instances end up dealing with a NULL freq_table and
>> crash.
>> 
>> Check for an already existing freq_table, before trying to create one,
>> and increment the freq_table_users only if the table is sucessfully
>> created.
>> 
>> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Cc: <linux-pm at vger.kernel.org>
>
> Kevin, are you going to merge this?
>

Yes, I plan to queue this with 2/2 for v3.6-rc.

Kevin





From khilman at ti.com  Thu Aug  9 11:01:13 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 09 Aug 2012 08:01:13 -0700
Subject: [PATCH 2/2] ARM: OMAP4: Register the OPP table only for 4430
 device
In-Reply-To: <50236570.6030301@ti.com> (Rajendra Nayak's message of "Thu, 09
 Aug 2012 12:53:28 +0530")
References: <1344423254-3475-1-git-send-email-rnayak@ti.com>
 <1344423254-3475-3-git-send-email-rnayak@ti.com>
 <87628twbd3.fsf@ti.com> <50236570.6030301@ti.com>
Message-ID: <878vdogldy.fsf@ti.com>

Rajendra Nayak <rnayak at ti.com> writes:

> Hi Kevin,
>
> On Wednesday 08 August 2012 10:48 PM, Kevin Hilman wrote:
>>> The 4430 OPP table was being registered for all other OMAP4 variants
>>> >  too, like 4460 and 4470 causing issues with cpufreq driver
>>> >  enabled. 4460 and 4470 devices have different OPPs as compared to
>>> >  4430, and they should be populated seperately. As long as that
>>> >  happens, let the OPP table registeration happen only on 4430 device.
>>> >
>>> >  Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>> Thanks, adding to PM fixes for v3.6-rc (branch: for_3.6/fixes/pm)
>
> I just posted a v2 of this series addressing the issues raised by
> Santosh on Patch 1/2. The problem with taking just $subject fix (or
> taking it before Patch 1/2) is that you would hit the issue fixed
> by the Patch 1/2 and cause a crash on non-4430 based OMAP4 devices with
> cpufreq enabled.

OK, thanks for the warning.  I'll be sure to keep them together.

Kevin


From swarren at wwwdotorg.org  Thu Aug  9 11:15:13 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 09 Aug 2012 09:15:13 -0600
Subject: [PATCH V3] ARM: dt: tegra: ventana: add regulators
In-Reply-To: <5023A716.50807@nvidia.com>
References: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
 <5023A716.50807@nvidia.com>
Message-ID: <5023D401.20303@wwwdotorg.org>

On 08/09/2012 06:03 AM, Laxman Dewangan wrote:
> On Friday 03 August 2012 11:39 PM, Stephen Warren wrote:
>> From: Stephen Warren<swarren at nvidia.com>
>>
>> Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
>> couple of fixed GPIO-controlled regulators too.
>>
>> The data was chosen to match the PMIC HW defaults, with the following
>> exception:
>>
>> ldo6: The HW default is 2.85v. The schematics are unlabelled. Internal
>> research indicates that 1.8v is correct. Our downstream kernel also uses
>> 1.8v.
>>
>> Portions based on work by Laxman Dewangan<ldewangan at nvidia.com>
...
> 
> Acked-by: Laxman Dewangan <ldewangan at nvidia.com>
> You can addd my ACK for harmony dts file.

There is no Harmony patch; just Paz00, Ventana, Seaboard. I assume you
meant to ack Seaboard as well, not Harmony?


From ricardo.neri at ti.com  Thu Aug  9 11:15:39 2012
From: ricardo.neri at ti.com (Ricardo Neri)
Date: Thu, 9 Aug 2012 10:15:39 -0500
Subject: [alsa-devel] [PATCH 07/11] ASoC: omap-mcbsp: Sidetone: Use SIDLE
 bits in SYSCONFIG register to select noidle mode
In-Reply-To: <5023614E.3030308@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-8-git-send-email-peter.ujfalusi@ti.com>
 <5022E46A.4010909@ti.com> <5023614E.3030308@ti.com>
Message-ID: <5023D41B.7090104@ti.com>

Hi Peter,

On 08/09/2012 02:05 AM, Peter Ujfalusi wrote:
> Hi Ricardo,
>
> On 08/09/2012 01:12 AM, Ricardo Neri wrote:
>> Is this another case in which it is required to change the idle-mode on a
>> per-use-case basis? In the past I was trying to do the same with HDMI [1]. In
>> that case it was decided to add the HWMOD_SWSUP_SIDLE to hwmod data with the
>> drawback of using no-idle/force-idle rather than smart-idle[2][3].
>
> This only concerns use case on OMAP3 when the sidetone is in use. In all other
> use cases we want to use smart-idle (music playback, FM TX/RX, etc).
> The main problem here is that the sidetone block have broken sidle line, it
> can not prevent McBSP iclk to be gated.
> The sidetone block is using the ICLK of the McBSP port (OMAP3 has ST block
> attached to McBSP2 and 3 ports only).

The situation was similar with HDMI. We need no-idle only when playing 
audio and smart-idle in all other use cases. With HWMOD_SWSUP_SIDLE we 
are in no-idle/force-idle all the time. :/
>
>
>> [1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg60226.html
>> [2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70463.html
>> [3] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg70653.html
>>>
>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
>>> ---
>>>    sound/soc/omap/mcbsp.c |   18 ++++++++++++++----
>>>    sound/soc/omap/mcbsp.h |    1 +
>>>    2 files changed, 15 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
>>> index c870023..e008898 100644
>>> --- a/sound/soc/omap/mcbsp.c
>>> +++ b/sound/soc/omap/mcbsp.c
>>> @@ -257,8 +257,15 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
>>>    {
>>>        unsigned int w;
>>>
>>> -    if (mcbsp->pdata->enable_st_clock)
>>> -        mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
>>> +    /*
>>> +     * Sidetone uses McBSP ICLK - which must not idle when sidetones
>>> +     * are enabled or sidetones start sounding ugly.
>>> +     */
>>> +    w = MCBSP_READ(mcbsp, SYSCON);
>>> +    mcbsp->st_data->mcbsp_sidle = (w >> 3) & 0x3;
>>> +    w &= ~SIDLEMODE(0x3);
>>> +    w |= SIDLEMODE(0x1);
>>> +    MCBSP_WRITE(mcbsp, SYSCON, w);
>>
>> Wouldn't this create a mismatch between the SYSCONFIG register and McBSP
>> omap_hwmod._sysc_cache?
>
> We modify the bits runtime (if the ST is enabled), after the hwmod already
> configured the McBSP port to s-idle. We change the McBSP port's s-idle mode
> back to it's original before pm_runtime_put().
>
> Previously we did the same thing in PRCM level which was as ugly as this
> workaround with the penalty of a callback function to mach-omap2 since we can
> only got access to PRCM register API there.
>
>> Perhaps this could be done with a future omap_hwmod API?
>
> But there's no such an API and I'm not aware any ongoing effort to have one.
> Still the issue mostly remains since we need to modify other block's s-idle
> mode. If sidetone block is enabled we need to change the McBSP port's s-idle
> mode to no-idle.

Would omap_hwmod_set_slave_idlemode make the workaround look less ugly? 
In this case you are changing other block's idle-mode, though.
>
> In most of the use cases the McBSP need to be in smart-idle mode since it
> provides significant power saving.

Yes, I was just trying to use this case to justify the need of a driver 
to be able to set the idle-mode for particular use cases. It would be 
nice to be able to use an API (present or future) to set to no-idle if 
required by a particular use-case and still be able to take advantage of 
smart-idle in other use cases.

Ricardo
>


From ian.molton at codethink.co.uk  Thu Aug  9 11:21:27 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Thu, 09 Aug 2012 16:21:27 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208091143.32972.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <50226779.6060201@codethink.co.uk> <50239815.6020108@codethink.co.uk>
 <201208091143.32972.arnd@arndb.de>
Message-ID: <5023D577.8090001@codethink.co.uk>

On 09/08/12 12:43, Arnd Bergmann wrote:
>  On 08/08/12 14:19, Ian Molton wrote:
>  > On 08/08/12 13:39, Arnd Bergmann wrote:
>  >> On Wednesday 08 August 2012, Ian Molton wrote:
>  >>> This method would require a small amount of rework in the driver to
>  >>> set up <n> ports, rather than just one.
>  >> This looks quite nice, but it is still very much incompatible with the
>  >> existing binding. Obviously we can abandon an existing binding and
>  >> introduce a second one for the same hardware, but that should not
>  >> be taken lightly.
>  > Fair, however the existing users aren't anywhere near as
>  > numerous as the new ones.
>
> Depends on how you count the numbers. I see at least three machines
> supported in the kernel with the old binding and none with the new one
> so far ;-)

I'm curious as to how any of those actually work, given the
apparent total lack of a mv64360-mdio device binding...
>  > As you can see, instead of putting port1 at +0x1700 or so,
>  > marvell have overlapped the register files - in fact, doubly
>  > so, since port1 + 0x1080 is right in the middle of
>  > (port0 + 0x1000) -> (port0 + 0x16ff), so one cant simply map two
>  > sets of regs like 0x0000->0x03ff and 0x1000->0x16ff for port one
>  > either.
>
> This could theoretically be dealt with by having 5 register ranges

I make that three...

> per device, but that would cause extra overhead and also be
> incompatible with the existing binding.

Indeed.

>  I think showing one
> parent device with children at address 0, 1 and 2 is ok.
Is it acceptable for the child devices to directly access the
parents register space? because there would be no other
way for that to work.

>  The driver
> already knows all those offsets and they are always the same
> for all variants of mv643xx, right?
Yes, but its not clean. And no amount of refactoring is
really going to make a nice driver that also fits the ancient
(and badly thought out) OF bindings.

If we have to break things, we can at least go for a nice
clean design, surely?

The ports arent really child devices of the MAC. The MAC
just has 3 ports.

Luckily, it looks like the existing users don't actually use
the device tree to set up the driver at all, preferring to
translate their D-T bindings to calls to
platform_device_register() so all we'd need to do to
support them is completely ignore them.

We're going to have to maintain a legacy
platform_device -> DT bindings hack somewhere anyway,
at least until the remaining other users of the driver
convert to D-T.

-Ian


From stefano.stabellini at eu.citrix.com  Thu Aug  9 11:37:24 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 9 Aug 2012 16:37:24 +0100
Subject: [PATCH v2 02/23] xen/arm: hypercalls
In-Reply-To: <20120808124111.GB2134@linaro.org>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120808124111.GB2134@linaro.org>
Message-ID: <alpine.DEB.2.02.1208091046330.21096@kaball.uk.xensource.com>

On Wed, 8 Aug 2012, Dave Martin wrote:
> On Mon, Aug 06, 2012 at 03:27:05PM +0100, Stefano Stabellini wrote:
> > Use r12 to pass the hypercall number to the hypervisor.
> > 
> > We need a register to pass the hypercall number because we might not
> > know it at compile time and HVC only takes an immediate argument.
> > 
> > Among the available registers r12 seems to be the best choice because it
> > is defined as "intra-procedure call scratch register".
> > 
> > Use the ISS to pass an hypervisor specific tag.
> > 
> > Changes in v2:
> > - define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
> > at the moment is unused;
> > - use ldm instead of pop;
> > - fix up comments.
> > 
> > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > ---
> >  arch/arm/include/asm/xen/hypercall.h |   50 ++++++++++++++++
> >  arch/arm/xen/Makefile                |    2 +-
> >  arch/arm/xen/hypercall.S             |  106 ++++++++++++++++++++++++++++++++++
> >  3 files changed, 157 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/include/asm/xen/hypercall.h
> >  create mode 100644 arch/arm/xen/hypercall.S
> 
> [...]
> 
> > diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
> > new file mode 100644
> > index 0000000..074f5ed
> > --- /dev/null
> > +++ b/arch/arm/xen/hypercall.S
> > @@ -0,0 +1,106 @@
> > +/******************************************************************************
> > + * hypercall.S
> > + *
> > + * Xen hypercall wrappers
> > + *
> > + * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation; or, when distributed
> > + * separately from the Linux kernel or incorporated into other
> > + * software packages, subject to the following license:
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > + * of this source file (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use, copy, modify,
> > + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> > + * and to permit persons to whom the Software is furnished to do so, subject to
> > + * the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> > + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +/*
> > + * The Xen hypercall calling convention is very similar to the ARM
> > + * procedure calling convention: the first paramter is passed in r0, the
> > + * second in r1, the third in r2 and the fourth in r3. Considering that
> > + * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
> > + * in r4, differently from the procedure calling convention of using the
> > + * stack for that case.
> > + *
> > + * The hypercall number is passed in r12.
> > + *
> > + * The return value is in r0.
> > + *
> > + * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
> > + * hypercall tag.
> > + */
> > +
> > +#include <linux/linkage.h>
> > +#include <asm/assembler.h>
> > +#include <xen/interface/xen.h>
> > +
> > +
> > +/* HVC 0xEA1 */
> > +#ifdef CONFIG_THUMB2_KERNEL
> > +#define xen_hvc .word 0xf7e08ea1
> > +#else
> > +#define xen_hvc .word 0xe140ea71
> > +#endif
> 
> Consider using my opcode injection helpers patch for this (see
> separate repost: [PATCH v2 REPOST 0/4] ARM: opcodes: Facilitate custom
> opcode injection), assuming that nobody objects to it.  This should mean
> that the right opcodes get generated when building a kernel for a big-
> endian target for example.
> 
> I believe the __HVC(imm) macro which I put in <asm/opcodes-virt.h> as an
> example should do what you need in this case.

Sure I can do that. Maybe I'll add another patch at the end of my series
to replace xen_hvc with __HVC(0xEA1), so that it remains independent
from your series.
I have learned through experience that avoiding cross patch series
dependencies help to reduce the amount of headaches during merge windows
:)


> > +
> > +#define HYPERCALL_SIMPLE(hypercall)		\
> > +ENTRY(HYPERVISOR_##hypercall)			\
> > +	mov r12, #__HYPERVISOR_##hypercall;	\
> > +	xen_hvc;							\
> > +	mov pc, lr;							\
> > +ENDPROC(HYPERVISOR_##hypercall)
> > +
> > +#define HYPERCALL0 HYPERCALL_SIMPLE
> > +#define HYPERCALL1 HYPERCALL_SIMPLE
> > +#define HYPERCALL2 HYPERCALL_SIMPLE
> > +#define HYPERCALL3 HYPERCALL_SIMPLE
> > +#define HYPERCALL4 HYPERCALL_SIMPLE
> > +
> > +#define HYPERCALL5(hypercall)			\
> > +ENTRY(HYPERVISOR_##hypercall)			\
> > +	stmdb sp!, {r4}						\
> > +	ldr r4, [sp, #4]					\
> > +	mov r12, #__HYPERVISOR_##hypercall;	\
> > +	xen_hvc								\
> > +	ldm sp!, {r4}						\
> > +	mov pc, lr							\
> > +ENDPROC(HYPERVISOR_##hypercall)
> > +
> > +                .text
> > +
> > +HYPERCALL2(xen_version);
> > +HYPERCALL3(console_io);
> > +HYPERCALL3(grant_table_op);
> > +HYPERCALL2(sched_op);
> > +HYPERCALL2(event_channel_op);
> > +HYPERCALL2(hvm_op);
> > +HYPERCALL2(memory_op);
> > +HYPERCALL2(physdev_op);
> > +
> > +ENTRY(privcmd_call)
> > +	stmdb sp!, {r4}
> > +	mov r12, r0
> > +	mov r0, r1
> > +	mov r1, r2
> > +	mov r2, r3
> > +	ldr r3, [sp, #8]
> > +	ldr r4, [sp, #4]
> > +	xen_hvc
> > +	ldm sp!, {r4}
> > +	mov pc, lr
> 
> Note that the preferred entry/exit sequences in such cases are:
> 
> 	stmfd	sp!, {r4,lr}
> 	...
> 	ldmfd	sp!, {r4,pc}
> 
> ...but it works either way.  I would bother to change it unless you
> have other changes to make too.

Wouldn't this needlessly save and restore one more register (lr) to the
stack?
I would try to keep the hypercall wrappers as small as possible...


From lee.jones at linaro.org  Thu Aug  9 11:47:26 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:26 +0100
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
Message-ID: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>

Another fine instalment of Audio fixes and Device Tree enablement
surrounding the mop500 sound driver. Hopefully containing all of 
the recommendations suggested by Mark Brown.

 Documentation/devicetree/bindings/mfd/ab8500.txt   |   15 +
 .../devicetree/bindings/sound/ux500-mop500.txt     |   39 ++
 .../devicetree/bindings/sound/ux500-msp.txt        |   43 ++
 arch/arm/boot/dts/db8500.dtsi                      |  627 ------------------
 arch/arm/boot/dts/dbx5x0.dtsi                      |  666 ++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts                     |   18 +-
 arch/arm/mach-ux500/Makefile                       |    2 +-
 arch/arm/mach-ux500/board-mop500-audio.c           |  189 ++++++
 arch/arm/mach-ux500/board-mop500-msp.c             |  267 --------
 arch/arm/mach-ux500/board-mop500-msp.h             |   14 -
 arch/arm/mach-ux500/board-mop500.c                 |   18 +-
 arch/arm/mach-ux500/board-mop500.h                 |    6 +
 arch/arm/mach-ux500/include/mach/msp.h             |    2 -
 include/linux/mfd/abx500/ab8500-codec.h            |    6 +-
 sound/soc/codecs/ab8500-codec.c                    |   85 +++
 sound/soc/ux500/mop500.c                           |   44 +-
 sound/soc/ux500/ux500_msp_dai.c                    |   20 +-
 sound/soc/ux500/ux500_msp_i2s.c                    |   97 ++-
 sound/soc/ux500/ux500_msp_i2s.h                    |    2 -
 sound/soc/ux500/ux500_pcm.c                        |   19 +-
 sound/soc/ux500/ux500_pcm.h                        |    3 +
 21 files changed, 1225 insertions(+), 957 deletions(-)



From lee.jones at linaro.org  Thu Aug  9 11:47:27 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:27 +0100
Subject: [PATCH 01/22] ARM: ux500: Fix merge error,
 no matching driver name for 'snd_soc_u8500'
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-2-git-send-email-lee.jones@linaro.org>

The platform attempts to register platform device 'snd_soc_u8500'
which doesn't actually exist. Here we change the reference to the
correct one 'snd_soc_mop500'.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 9960480..df15646 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 	return pdev;
 }
 
-/* Platform device for ASoC U8500 machine */
-static struct platform_device snd_soc_u8500 = {
-		.name = "snd-soc-u8500",
+/* Platform device for ASoC MOP500 machine */
+static struct platform_device snd_soc_mop500 = {
+		.name = "snd-soc-mop500",
 		.id = 0,
 		.dev = {
 			.platform_data = NULL,
@@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent)
 {
 	struct platform_device *msp1;
 
-	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
-	platform_device_register(&snd_soc_u8500);
+	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
 
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:28 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:28 +0100
Subject: [PATCH 02/22] ARM: ux500: Ensure probing of Audio devices when Device
 Tree is enabled
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-3-git-send-email-lee.jones@linaro.org>

Previous attempts to add platform probing of the Audio related devices
only call from non-DT initialisation functions. This patch extends that
functionality to the Device Tree related ones too.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f413587..5d9600b 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -799,6 +799,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		mop500_sdi_init(parent);
+		mop500_msp_init(parent);
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 		i2c_register_board_info(2, mop500_i2c2_devices,
@@ -806,6 +807,8 @@ static void __init u8500_init_machine(void)
 
 		mop500_uib_init();
 
+	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
+		mop500_msp_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
@@ -817,6 +820,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		hrefv60_sdi_init(parent);
+		mop500_msp_init(parent);
 
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:29 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:29 +0100
Subject: [PATCH 03/22] ASoC: ab8500: Inform SoC Core that we have our own I/O
 arrangements
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-4-git-send-email-lee.jones@linaro.org>

If codec->control_data is not populated SoC Core assumes we want to
use regmap, which fails catastrophically, as we don't have one:

Unable to handle kernel NULL pointer dereference at virtual address 00000080
pgd = c0004000
[00000080] *pgd=00000000
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 1    Not tainted  (3.5.0-rc6-00884-g0b2419e-dirty #130)
PC is at regmap_read+0x10/0x5c
LR is at hw_read+0x80/0x90
pc : [<c01a91b8>]    lr : [<c0216804>]    psr: 60000013

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/codecs/ab8500-codec.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 3c79592..23b4018 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -2406,6 +2406,10 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
 
 	/* Setup AB8500 according to board-settings */
 	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
+
+	/* Inform SoC Core that we have our own I/O arrangements. */
+	codec->control_data = (void *)true;
+
 	status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
 	if (status < 0) {
 		pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:30 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:30 +0100
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP driver
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-5-git-send-email-lee.jones@linaro.org>

In the initial submission of the MSP driver msp1 and msp3's associated
pinctrl mechanism was passed back to platform code using a plat_init()
call-back routine, but it has no place in platform code. The MSP driver
should set this up for the appropriate ports. Instead we use a use_pinctrl
identifier which is passed from platform_data/Device Tree which indicates
which ports should use pinctrl.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   75 +-------------------------------
 arch/arm/mach-ux500/include/mach/msp.h |    2 -
 sound/soc/ux500/ux500_msp_i2s.c        |   75 +++++++++++++++++++++++++-------
 sound/soc/ux500/ux500_msp_i2s.h        |    2 -
 4 files changed, 60 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index df15646..fc78d5d 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -23,53 +23,6 @@
 #include "devices-db8500.h"
 #include "pins-db8500.h"
 
-/* MSP1/3 Tx/Rx usage protection */
-static DEFINE_SPINLOCK(msp_rxtx_lock);
-
-/* Reference Count */
-static int msp_rxtx_ref;
-
-/* Pin modes */
-struct pinctrl *msp1_p;
-struct pinctrl_state *msp1_def;
-struct pinctrl_state *msp1_sleep;
-
-int msp13_i2s_init(void)
-{
-	int retval = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&msp_rxtx_lock, flags);
-	if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
-		retval = pinctrl_select_state(msp1_p, msp1_def);
-		if (retval)
-			pr_err("could not set MSP1 defstate\n");
-	}
-	if (!retval)
-		msp_rxtx_ref++;
-	spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-	return retval;
-}
-
-int msp13_i2s_exit(void)
-{
-	int retval = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&msp_rxtx_lock, flags);
-	WARN_ON(!msp_rxtx_ref);
-	msp_rxtx_ref--;
-	if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
-		retval = pinctrl_select_state(msp1_p, msp1_sleep);
-		if (retval)
-			pr_err("could not set MSP1 sleepstate\n");
-	}
-	spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-	return retval;
-}
-
 static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
@@ -132,8 +85,6 @@ static struct msp_i2s_platform_data msp1_platform_data = {
 	.id = MSP_I2S_1,
 	.msp_i2s_dma_rx = NULL,
 	.msp_i2s_dma_tx = &msp1_dma_tx,
-	.msp_i2s_init = msp13_i2s_init,
-	.msp_i2s_exit = msp13_i2s_exit,
 };
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -219,47 +170,23 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.id		= MSP_I2S_3,
 	.msp_i2s_dma_rx	= &msp1_dma_rx,
 	.msp_i2s_dma_tx	= NULL,
-	.msp_i2s_init = msp13_i2s_init,
-	.msp_i2s_exit = msp13_i2s_exit,
 };
 
 int mop500_msp_init(struct device *parent)
 {
-	struct platform_device *msp1;
-
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
 	platform_device_register(&snd_soc_mop500);
 
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
 			   &msp0_platform_data);
-	msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
 			   &msp1_platform_data);
 	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
 			   &msp2_platform_data);
 	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
 			   &msp3_platform_data);
 
-	/* Get the pinctrl handle for MSP1 */
-	if (msp1) {
-		msp1_p = pinctrl_get(&msp1->dev);
-		if (IS_ERR(msp1_p))
-			dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
-		else {
-			msp1_def = pinctrl_lookup_state(msp1_p,
-							PINCTRL_STATE_DEFAULT);
-			if (IS_ERR(msp1_def)) {
-				dev_err(&msp1->dev,
-					"could not get MSP1 defstate\n");
-			}
-			msp1_sleep = pinctrl_lookup_state(msp1_p,
-							  PINCTRL_STATE_SLEEP);
-			if (IS_ERR(msp1_sleep))
-				dev_err(&msp1->dev,
-					"could not get MSP1 idlestate\n");
-		}
-	}
-
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
 
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19..3cc7142 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
 	enum msp_i2s_id id;
 	struct stedma40_chan_cfg *msp_i2s_dma_rx;
 	struct stedma40_chan_cfg *msp_i2s_dma_tx;
-	int (*msp_i2s_init) (void);
-	int (*msp_i2s_exit) (void);
 };
 
 #endif
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index 36be11e..2cbfc54 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -15,6 +15,7 @@
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 
@@ -25,6 +26,17 @@
 
 #include "ux500_msp_i2s.h"
 
+/* MSP1/3 Tx/Rx usage protection */
+static DEFINE_SPINLOCK(msp_rxtx_lock);
+
+/* Pin modes */
+struct pinctrl *pinctrl_p;
+struct pinctrl_state *pinctrl_def;
+struct pinctrl_state *pinctrl_sleep;
+
+/* Reference Count */
+int pinctrl_rxtx_ref;
+
  /* Protocol desciptors */
 static const struct msp_protdesc prot_descs[] = {
 	{ /* I2S */
@@ -352,17 +364,23 @@ static int configure_multichannel(struct ux500_msp *msp,
 
 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
 {
-	int status = 0;
+	int status = 0, retval = 0;
 	u32 reg_val_DMACR, reg_val_GCR;
+	unsigned long flags;
 
 	/* Check msp state whether in RUN or CONFIGURED Mode */
-	if ((msp->msp_state == MSP_STATE_IDLE) && (msp->plat_init)) {
-		status = msp->plat_init();
-		if (status) {
-			dev_err(msp->dev, "%s: ERROR: Failed to init MSP (%d)!\n",
-				__func__, status);
-			return status;
+	if (msp->msp_state == MSP_STATE_IDLE) {
+		spin_lock_irqsave(&msp_rxtx_lock, flags);
+		if (pinctrl_rxtx_ref == 0 &&
+			!(IS_ERR(pinctrl_p) || IS_ERR(pinctrl_def))) {
+			retval = pinctrl_select_state(pinctrl_p,
+						pinctrl_def);
+			if (retval)
+				pr_err("could not set MSP defstate\n");
 		}
+		if (!retval)
+			pinctrl_rxtx_ref++;
+		spin_unlock_irqrestore(&msp_rxtx_lock, flags);
 	}
 
 	/* Configure msp with protocol dependent settings */
@@ -620,7 +638,8 @@ int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
 
 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
 {
-	int status = 0;
+	int status = 0, retval = 0;
+	unsigned long flags;
 
 	dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
 
@@ -631,12 +650,19 @@ int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
 		writel((readl(msp->registers + MSP_GCR) &
 			       (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
 			      msp->registers + MSP_GCR);
-		if (msp->plat_exit)
-			status = msp->plat_exit();
-			if (status)
-				dev_warn(msp->dev,
-					"%s: WARN: ux500_msp_i2s_exit failed (%d)!\n",
-					__func__, status);
+
+		spin_lock_irqsave(&msp_rxtx_lock, flags);
+		WARN_ON(!pinctrl_rxtx_ref);
+		pinctrl_rxtx_ref--;
+		if (pinctrl_rxtx_ref == 0 &&
+			!(IS_ERR(pinctrl_p) || IS_ERR(pinctrl_sleep))) {
+			retval = pinctrl_select_state(pinctrl_p,
+						pinctrl_sleep);
+			if (retval)
+				pr_err("could not set MSP sleepstate\n");
+		}
+		spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+
 		writel(0, msp->registers + MSP_GCR);
 		writel(0, msp->registers + MSP_TCF);
 		writel(0, msp->registers + MSP_RCF);
@@ -678,8 +704,6 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 
 	msp->id = platform_data->id;
 	msp->dev = &pdev->dev;
-	msp->plat_init = platform_data->msp_i2s_init;
-	msp->plat_exit = platform_data->msp_i2s_exit;
 	msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
 	msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
 
@@ -717,6 +741,25 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 	dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
 	msp->i2s_cont = i2s_cont;
 
+	pinctrl_p = pinctrl_get(msp->dev);
+	if (IS_ERR(pinctrl_p))
+		dev_err(&pdev->dev, "could not get MSP pinctrl\n");
+	else {
+		pinctrl_def = pinctrl_lookup_state(pinctrl_p,
+						PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(pinctrl_def)) {
+			dev_err(&pdev->dev,
+				"could not get MSP defstate (%li)\n",
+				PTR_ERR(pinctrl_def));
+		}
+		pinctrl_sleep = pinctrl_lookup_state(pinctrl_p,
+						PINCTRL_STATE_SLEEP);
+		if (IS_ERR(pinctrl_sleep))
+			dev_err(&pdev->dev,
+				"could not get MSP idlestate (%li)\n",
+				PTR_ERR(pinctrl_def));
+	}
+
 	return 0;
 
 err_i2s_cont:
diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h
index 2d9136d..1ce336f 100644
--- a/sound/soc/ux500/ux500_msp_i2s.h
+++ b/sound/soc/ux500/ux500_msp_i2s.h
@@ -524,8 +524,6 @@ struct ux500_msp {
 	struct dma_chan *rx_pipeid;
 	enum msp_state msp_state;
 	int (*transfer) (struct ux500_msp *msp, struct i2s_message *message);
-	int (*plat_init) (void);
-	int (*plat_exit) (void);
 	struct timer_list notify_timer;
 	int def_elem_len;
 	unsigned int dir_busy;
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:31 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:31 +0100
Subject: [PATCH 05/22] ASoC: Ux500: Enable MOP500 driver for Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-6-git-send-email-lee.jones@linaro.org>

Here we ensure that the MOP500 audio driver will be probed during a
Device Tree boot. We also parse the sound node to link together the
codec, dma and the CPU-side Digital Audio Interface.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/mop500.c |   40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/sound/soc/ux500/mop500.c b/sound/soc/ux500/mop500.c
index 31c4d26..6840df7 100644
--- a/sound/soc/ux500/mop500.c
+++ b/sound/soc/ux500/mop500.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/spi/spi.h>
+#include <linux/of.h>
 
 #include <sound/soc.h>
 #include <sound/initval.h>
@@ -56,8 +57,35 @@ static struct snd_soc_card mop500_card = {
 	.num_links = ARRAY_SIZE(mop500_dai_links),
 };
 
+static int __devinit mop500_of_probe(struct platform_device *pdev,
+				struct device_node *np)
+{
+	struct device_node *codec_np, *msp_np[2];
+	int i;
+
+	msp_np[0] = of_parse_phandle(np, "stericsson,cpu-dai", 0);
+	msp_np[1] = of_parse_phandle(np, "stericsson,cpu-dai", 1);
+	codec_np  = of_parse_phandle(np, "stericsson,audio-codec", 0);
+
+	if (!(msp_np[0] && msp_np[1] && codec_np)) {
+		dev_err(&pdev->dev, "Phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < 2; i++) {
+		mop500_dai_links[i].cpu_of_node = msp_np[i];
+		mop500_dai_links[i].cpu_dai_name = NULL;
+		mop500_dai_links[i].codec_of_node = codec_np;
+		mop500_dai_links[i].codec_name = NULL;
+	}
+
+	snd_soc_of_parse_card_name(&mop500_card, "stericsson,card-name");
+
+	return 0;
+}
 static int __devinit mop500_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	int ret;
 
 	pr_debug("%s: Enter.\n", __func__);
@@ -66,6 +94,12 @@ static int __devinit mop500_probe(struct platform_device *pdev)
 
 	mop500_card.dev = &pdev->dev;
 
+	if (np) {
+		ret = mop500_of_probe(pdev, np);
+		if (ret)
+			return ret;
+	}
+
 	dev_dbg(&pdev->dev, "%s: Card %s: Set platform drvdata.\n",
 		__func__, mop500_card.name);
 	platform_set_drvdata(pdev, &mop500_card);
@@ -101,10 +135,16 @@ static int __devexit mop500_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id snd_soc_mop500_match[] = {
+	{ .compatible = "stericsson,snd-soc-mop500", },
+	{},
+};
+
 static struct platform_driver snd_soc_mop500_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = "snd-soc-mop500",
+		.of_match_table = snd_soc_mop500_match,
 	},
 	.probe = mop500_probe,
 	.remove = __devexit_p(mop500_remove),
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:32 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:32 +0100
Subject: [PATCH 06/22] ASoC: Ux500: Enable ux500 MSP driver for Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-7-git-send-email-lee.jones@linaro.org>

Register both parts of the MSP driver from Device Tree so that they
are probed when Device Tree is enabled. Also, as there is platform
data involved, we ensure that there is allocated memory to place the
configuration into and that the correct information is extracted from
the DT binary.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/ux500_msp_dai.c |    6 ++++++
 sound/soc/ux500/ux500_msp_i2s.c |   22 +++++++++++++++++++---
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 772cb19..0f7dd49 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -833,10 +833,16 @@ static int __devexit ux500_msp_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id ux500_msp_i2c_match[] = {
+	{ .compatible = "stericsson,ux500-msp-i2s", },
+	{},
+};
+
 static struct platform_driver msp_i2s_driver = {
 	.driver = {
 		.name = "ux500-msp-i2s",
 		.owner = THIS_MODULE,
+		.of_match_table = ux500_msp_i2c_match,
 	},
 	.probe = ux500_msp_drv_probe,
 	.remove = ux500_msp_drv_remove,
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index 2cbfc54..5e0bf8c 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -18,6 +18,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <mach/hardware.h>
 #include <mach/msp.h>
@@ -692,16 +693,31 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 	int ret = 0;
 	struct resource *res = NULL;
 	struct i2s_controller *i2s_cont;
+	struct device_node *np = pdev->dev.of_node;
 	struct ux500_msp *msp;
 
-	dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
-		pdev->name, platform_data->id);
-
 	*msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
 	msp = *msp_p;
 	if (!msp)
 		return -ENOMEM;
 
+	if (np) {
+		if (!platform_data) {
+			platform_data = devm_kzalloc(&pdev->dev,
+				sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
+			if (!platform_data)
+				ret = -ENOMEM;
+		}
+	} else
+		if (!platform_data)
+			ret = -EINVAL;
+
+	if (ret)
+		goto err_res;
+
+	dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
+		pdev->name, platform_data->id);
+
 	msp->id = platform_data->id;
 	msp->dev = &pdev->dev;
 	msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:33 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:33 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather than
 as a device
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-8-git-send-email-lee.jones@linaro.org>

The PCM is a pseudo-device. It doesn't have any of it's own registers
or hardware. It rather acts as a layer of abstraction for DMA
transfers. Hence, instead of classifying it as a device in its own
right, we call the initialisation from the MSP driver.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/mop500.c        |    4 ++--
 sound/soc/ux500/ux500_msp_dai.c |   14 +++++++++++++-
 sound/soc/ux500/ux500_pcm.c     |   19 ++++---------------
 sound/soc/ux500/ux500_pcm.h     |    3 +++
 4 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/sound/soc/ux500/mop500.c b/sound/soc/ux500/mop500.c
index 6840df7..fe6223a 100644
--- a/sound/soc/ux500/mop500.c
+++ b/sound/soc/ux500/mop500.c
@@ -33,7 +33,7 @@ struct snd_soc_dai_link mop500_dai_links[] = {
 		.stream_name = "ab8500_0",
 		.cpu_dai_name = "ux500-msp-i2s.1",
 		.codec_dai_name = "ab8500-codec-dai.0",
-		.platform_name = "ux500-pcm.0",
+		.platform_name = "ux500-msp-i2s.1",
 		.codec_name = "ab8500-codec.0",
 		.init = mop500_ab8500_machine_init,
 		.ops = mop500_ab8500_ops,
@@ -43,7 +43,7 @@ struct snd_soc_dai_link mop500_dai_links[] = {
 		.stream_name = "ab8500_1",
 		.cpu_dai_name = "ux500-msp-i2s.3",
 		.codec_dai_name = "ab8500-codec-dai.1",
-		.platform_name = "ux500-pcm.0",
+		.platform_name = "ux500-msp-i2s.3",
 		.codec_name = "ab8500-codec.0",
 		.init = NULL,
 		.ops = mop500_ab8500_ops,
diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 0f7dd49..3476d6a 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -28,6 +28,7 @@
 
 #include "ux500_msp_i2s.h"
 #include "ux500_msp_dai.h"
+#include "ux500_pcm.h"
 
 static int setup_pcm_multichan(struct snd_soc_dai *dai,
 			struct ux500_msp_config *msp_config)
@@ -806,11 +807,20 @@ static int __devinit ux500_msp_drv_probe(struct platform_device *pdev)
 		goto err_init_msp;
 	}
 
+	ret = ux500_pcm_register_platform(pdev);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"Error: %s: Failed to register PCM platform device!\n",
+			__func__);
+		goto err_reg_plat;
+	}
+
 	return 0;
 
+err_reg_plat:
+	snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(ux500_msp_dai_drv));
 err_init_msp:
 	clk_put(drvdata->clk);
-
 err_clk:
 	devm_regulator_put(drvdata->reg_vape);
 
@@ -821,6 +831,8 @@ static int __devexit ux500_msp_drv_remove(struct platform_device *pdev)
 {
 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
 
+	ux500_pcm_unregister_platform(pdev);
+
 	snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(ux500_msp_dai_drv));
 
 	devm_regulator_put(drvdata->reg_vape);
diff --git a/sound/soc/ux500/ux500_pcm.c b/sound/soc/ux500/ux500_pcm.c
index 1a04e24..894c9f4 100644
--- a/sound/soc/ux500/ux500_pcm.c
+++ b/sound/soc/ux500/ux500_pcm.c
@@ -282,7 +282,7 @@ static struct snd_soc_platform_driver ux500_pcm_soc_drv = {
 	.pcm_new        = ux500_pcm_new,
 };
 
-static int __devexit ux500_pcm_drv_probe(struct platform_device *pdev)
+int __devinit ux500_pcm_register_platform(struct platform_device *pdev)
 {
 	int ret;
 
@@ -296,23 +296,12 @@ static int __devexit ux500_pcm_drv_probe(struct platform_device *pdev)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(ux500_pcm_register_platform);
 
-static int __devinit ux500_pcm_drv_remove(struct platform_device *pdev)
+int __devexit ux500_pcm_unregister_platform(struct platform_device *pdev)
 {
 	snd_soc_unregister_platform(&pdev->dev);
 
 	return 0;
 }
-
-static struct platform_driver ux500_pcm_driver = {
-	.driver = {
-		.name = "ux500-pcm",
-		.owner = THIS_MODULE,
-	},
-
-	.probe = ux500_pcm_drv_probe,
-	.remove = __devexit_p(ux500_pcm_drv_remove),
-};
-module_platform_driver(ux500_pcm_driver);
-
-MODULE_LICENSE("GPL v2");
+EXPORT_SYMBOL_GPL(ux500_pcm_unregister_platform);
diff --git a/sound/soc/ux500/ux500_pcm.h b/sound/soc/ux500/ux500_pcm.h
index 77ed44d..76d3444 100644
--- a/sound/soc/ux500/ux500_pcm.h
+++ b/sound/soc/ux500/ux500_pcm.h
@@ -32,4 +32,7 @@
 #define UX500_PLATFORM_PERIODS_MAX		48
 #define UX500_PLATFORM_BUFFER_BYTES_MAX		(2048 * PAGE_SIZE)
 
+int ux500_pcm_register_platform(struct platform_device *pdev);
+int ux500_pcm_unregister_platform(struct platform_device *pdev);
+
 #endif
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:34 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:34 +0100
Subject: [PATCH 08/22] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-9-git-send-email-lee.jones@linaro.org>

We continue to allow the AB8500 CODEC to be registered via the AB8500
Multi Functional Device API, only this time we extract its configuration
from the Device Tree binary.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/mfd/abx500/ab8500-codec.h |    6 ++-
 sound/soc/codecs/ab8500-codec.c         |   81 +++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/include/linux/mfd/abx500/ab8500-codec.h b/include/linux/mfd/abx500/ab8500-codec.h
index dc65292..d707941 100644
--- a/include/linux/mfd/abx500/ab8500-codec.h
+++ b/include/linux/mfd/abx500/ab8500-codec.h
@@ -23,7 +23,8 @@ enum amic_type {
 /* Mic-biases */
 enum amic_micbias {
 	AMIC_MICBIAS_VAMIC1,
-	AMIC_MICBIAS_VAMIC2
+	AMIC_MICBIAS_VAMIC2,
+	AMIC_MICBIAS_UNKNOWN
 };
 
 /* Bias-voltage */
@@ -31,7 +32,8 @@ enum ear_cm_voltage {
 	EAR_CMV_0_95V,
 	EAR_CMV_1_10V,
 	EAR_CMV_1_27V,
-	EAR_CMV_1_58V
+	EAR_CMV_1_58V,
+	EAR_CMV_UNKNOWN
 };
 
 /* Analog microphone settings */
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 23b4018..fa80961 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -34,6 +34,7 @@
 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 #include <linux/mfd/abx500/ab8500-codec.h>
 #include <linux/regulator/consumer.h>
+#include <linux/of.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -2394,9 +2395,65 @@ struct snd_soc_dai_driver ab8500_codec_dai[] = {
 	}
 };
 
+static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
+				struct ab8500_codec_platform_data *codec)
+{
+	u32 value;
+
+	if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
+		codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
+
+	if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
+		codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
+
+	/* Has a non-standard Vamic been requested? */
+	if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
+	else
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
+
+	if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
+		switch (value) {
+		case 950 :
+			codec->ear_cmv = EAR_CMV_0_95V;
+			break;
+		case 1100 :
+			codec->ear_cmv = EAR_CMV_1_10V;
+			break;
+		case 1270 :
+			codec->ear_cmv = EAR_CMV_1_27V;
+			break;
+		case 1580 :
+			codec->ear_cmv = EAR_CMV_1_58V;
+			break;
+		default :
+			codec->ear_cmv = EAR_CMV_UNKNOWN;
+			dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
+		}
+	} else {
+		dev_warn(dev, "No earpiece voltage found in DT - using default\n");
+		codec->ear_cmv = EAR_CMV_0_95V;
+	}
+}
+
 static int ab8500_codec_probe(struct snd_soc_codec *codec)
 {
 	struct device *dev = codec->dev;
+	struct device_node *np = dev->of_node;
 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
 	struct ab8500_platform_data *pdata;
 	struct filter_control *fc;
@@ -2407,6 +2464,30 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
 	/* Setup AB8500 according to board-settings */
 	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
 
+	if (np) {
+		if (!pdata)
+			pdata = devm_kzalloc(dev,
+					sizeof(struct ab8500_platform_data),
+					GFP_KERNEL);
+
+		if (!pdata->codec)
+			pdata->codec
+				= devm_kzalloc(dev,
+					sizeof(struct ab8500_codec_platform_data),
+					GFP_KERNEL);
+
+		if (!(pdata && pdata->codec))
+			return -ENOMEM;
+
+		ab8500_codec_of_probe(dev, np, pdata->codec);
+
+	} else {
+		if (!(pdata && pdata->codec)) {
+			dev_err(dev, "No codec platform data or DT found\n");
+			return -EINVAL;
+		}
+	}
+
 	/* Inform SoC Core that we have our own I/O arrangements. */
 	codec->control_data = (void *)true;
 
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:36 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:36 +0100
Subject: [PATCH 10/22] Documentation: Define the MSP Driver Device Tree
 bindings
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-11-git-send-email-lee.jones@linaro.org>

Here we add the required documentation for the new Device Tree
bindings pertaining to the MSP CPU-side DAI Driver.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/sound/ux500-msp.txt        |   43 ++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ux500-msp.txt

diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt
new file mode 100644
index 0000000..99acd9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-msp.txt
@@ -0,0 +1,43 @@
+* ux500 MSP (CPU-side Digital Audio Interface)
+
+Required properties:
+ - compatible       :"stericsson,ux500-msp-i2s"
+ - reg              : Physical base address and length of the device's registers.
+
+Optional properties:
+ - interrupts       : The interrupt output from the device.
+ - interrupt-parent : The parent interrupt controller.
+ - <name>-supply    : Phandle to the regulator <name> supply
+
+Example:
+
+	sound {
+		compatible = "stericsson,snd-soc-mop500";
+
+		stericsson,platform-pcm-dma = <&pcm>;
+		stericsson,cpu-dai = <&msp1 &msp3>;
+		stericsson,audio-codec = <&codec>;
+	};
+
+	pcm: ux500-pcm {
+		compatible = "stericsson,ux500-pcm";
+	};
+
+	msp1: msp at 80124000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80124000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	msp3: msp at 80125000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80125000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:35 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:35 +0100
Subject: [PATCH 09/22] Documentation: Define the MOP500 Audio Machine Driver
 Device Tree bindings
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-10-git-send-email-lee.jones@linaro.org>

Here we add the required documentation for the new Device Tree
bindings pertaining to the MOP500 Audio Machine driver.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/sound/ux500-mop500.txt     |   39 ++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ux500-mop500.txt

diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
new file mode 100644
index 0000000..48e071c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
@@ -0,0 +1,39 @@
+* MOP500 Audio Machine Driver
+
+This node is responsible for linking together all ux500 Audio Driver components.
+
+Required properties:
+ - compatible              : "stericsson,snd-soc-mop500"
+
+Non-standard properties:
+ - stericsson,cpu-dai      : Phandle to the CPU-side DAI
+ - stericsson,audio-codec  : Phandle to the Audio CODEC
+ - stericsson,card-name    : Over-ride default card name
+
+Example:
+
+	sound {
+		compatible = "stericsson,snd-soc-mop500";
+
+		stericsson,cpu-dai = <&msp1 &msp3>;
+		stericsson,audio-codec = <&codec>;
+	};
+
+	msp1: msp at 80124000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80124000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	msp3: msp at 80125000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80125000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:37 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:37 +0100
Subject: [PATCH 11/22] ARM: ux500: Clean-up MSP platform code
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-12-git-send-email-lee.jones@linaro.org>

This patch contains a couple of general MSP clean-ups pertaining to
layout changes and changing functions to be void instead of int instead
of regardlessly returning '0'.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   24 +++++++++++-------------
 arch/arm/mach-ux500/board-mop500-msp.h |   14 --------------
 arch/arm/mach-ux500/board-mop500.c     |    1 -
 arch/arm/mach-ux500/board-mop500.h     |    3 +++
 4 files changed, 14 insertions(+), 28 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/board-mop500-msp.h

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index fc78d5d..1a67577 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -144,20 +144,20 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 
 /* Platform device for ASoC MOP500 machine */
 static struct platform_device snd_soc_mop500 = {
-		.name = "snd-soc-mop500",
-		.id = 0,
-		.dev = {
-			.platform_data = NULL,
-		},
+	.name = "snd-soc-mop500",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
 };
 
 /* Platform device for Ux500-PCM */
 static struct platform_device ux500_pcm = {
-		.name = "ux500-pcm",
-		.id = 0,
-		.dev = {
-			.platform_data = NULL,
-		},
+	.name = "ux500-pcm",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
 };
 
 static struct msp_i2s_platform_data msp2_platform_data = {
@@ -172,7 +172,7 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
-int mop500_msp_init(struct device *parent)
+void mop500_msp_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
 	platform_device_register(&snd_soc_mop500);
@@ -189,6 +189,4 @@ int mop500_msp_init(struct device *parent)
 
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
-
-	return 0;
 }
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e..0000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja at stericsson.com>,
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5d9600b..11dd962 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -54,7 +54,6 @@
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-#include "board-mop500-msp.h"
 
 static struct gpio_led snowball_led_array[] = {
 	{
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d04a8e6..1d7316b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -92,6 +92,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
+void mop500_msp_init(struct device *parent);
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_msp_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:38 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:38 +0100
Subject: [PATCH 12/22] ARM: ux500: Add AB8500 CODEC node to DB8500 Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-13-git-send-email-lee.jones@linaro.org>

Ensure correct probing and pass though important configuration
options to the AB8500 CODEC driver when DT is enabled

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 33fafe3..83ed692 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -389,6 +389,12 @@
 					compatible = "stericsson,ab8500-debug";
 				};
 
+				codec: ab8500-codec {
+					compatible = "stericsson,ab8500-codec";
+
+					stericsson,earpeice-cmv = <950>; /* Units in mV. */
+				};
+
 				ab8500-regulators {
 					compatible = "stericsson,ab8500-regulator";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:39 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:39 +0100
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-14-git-send-email-lee.jones@linaro.org>

We've done this before and it worked well last time. Here we're
duplicating a complex registration function to ease the process
of enabling it for Device Tree. As there are quite a few steps
taken during the registration process, it makes sense to break
them up into more manageable chunks. This patch will aid us.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   20 ++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500.c     |    2 +-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 1a67577..24a3604 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -172,6 +172,26 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_msp_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
+
+	pr_info("Initialize MSP I2S-devices.\n");
+	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+			   &msp0_platform_data);
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+			   &msp1_platform_data);
+	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+			   &msp2_platform_data);
+	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+			   &msp3_platform_data);
+
+	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+	platform_device_register(&ux500_pcm);
+}
+
 void mop500_msp_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 11dd962..8f419b1 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
 		mop500_uib_init();
 
 	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-		mop500_msp_init(parent);
+		mop500_of_msp_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:40 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:40 +0100
Subject: [PATCH 14/22] ARM: ux500: Pass MSP DMA platform data though AUXDATA
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-15-git-send-email-lee.jones@linaro.org>

It isn't currently possible to pass all platform specific configuration
though Device Tree. Thinks like device names used in the clock
infrastructure, call-backs and DMA information have to be passed in via
AUXDATA structures and the MSP is no exception. Here we're passing DMA
settings.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |    8 ++++----
 arch/arm/mach-ux500/board-mop500.c     |    9 +++++++++
 arch/arm/mach-ux500/board-mop500.h     |    5 +++++
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 24a3604..ec802d0 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -49,7 +49,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
 	/* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp0_platform_data = {
+struct msp_i2s_platform_data msp0_platform_data = {
 	.id = MSP_I2S_0,
 	.msp_i2s_dma_rx = &msp0_dma_rx,
 	.msp_i2s_dma_tx = &msp0_dma_tx,
@@ -81,7 +81,7 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
 	/* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp1_platform_data = {
+struct msp_i2s_platform_data msp1_platform_data = {
 	.id = MSP_I2S_1,
 	.msp_i2s_dma_rx = NULL,
 	.msp_i2s_dma_tx = &msp1_dma_tx,
@@ -160,13 +160,13 @@ static struct platform_device ux500_pcm = {
 	},
 };
 
-static struct msp_i2s_platform_data msp2_platform_data = {
+struct msp_i2s_platform_data msp2_platform_data = {
 	.id = MSP_I2S_2,
 	.msp_i2s_dma_rx = &msp2_dma_rx,
 	.msp_i2s_dma_tx = &msp2_dma_tx,
 };
 
-static struct msp_i2s_platform_data msp3_platform_data = {
+struct msp_i2s_platform_data msp3_platform_data = {
 	.id		= MSP_I2S_3,
 	.msp_i2s_dma_rx	= &msp1_dma_rx,
 	.msp_i2s_dma_tx	= NULL,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8f419b1..0c141d5 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -758,6 +758,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+	/* Requires clock name and DMA bindings. */
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+		"ux500-msp-i2s.0", &msp0_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+		"ux500-msp-i2s.1", &msp1_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+		"ux500-msp-i2s.2", &msp2_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+		"ux500-msp-i2s.3", &msp3_platform_data),
 	{},
 };
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 1d7316b..3fbf48f 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <mach/msp.h>
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -81,6 +82,10 @@ struct device;
 struct i2c_board_info;
 extern struct mmci_platform_data mop500_sdi0_data;
 extern struct mmci_platform_data mop500_sdi4_data;
+extern struct msp_i2s_platform_data msp0_platform_data;
+extern struct msp_i2s_platform_data msp1_platform_data;
+extern struct msp_i2s_platform_data msp2_platform_data;
+extern struct msp_i2s_platform_data msp3_platform_data;
 extern struct arm_pmu_platdata db8500_pmu_platdata;
 
 extern void mop500_sdi_init(struct device *parent);
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:41 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:41 +0100
Subject: [PATCH 15/22] ARM: ux500: Stop registering the MOP500 Audio driver
 from platform code
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-16-git-send-email-lee.jones@linaro.org>

In this patch we prevent MOP500 driver registration from platform
code and rely solely on Device Tree to do the probing for us.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index ec802d0..41e4df2 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -175,9 +175,6 @@ struct msp_i2s_platform_data msp3_platform_data = {
 /* Due for removal once the MSP driver has been fully DT:ed. */
 void mop500_of_msp_init(struct device *parent)
 {
-	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
-	platform_device_register(&snd_soc_mop500);
-
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
 			   &msp0_platform_data);
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:42 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:42 +0100
Subject: [PATCH 16/22] ARM: ux500: Stop registering the PCM driver from
 platform code
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-17-git-send-email-lee.jones@linaro.org>

We now initialise the PCM driver through the MSP DAI, so there is
no need to register it though platform code anymore. This patch
strips out all PCM platform registration.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 41e4df2..58768c2 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -184,9 +184,6 @@ void mop500_of_msp_init(struct device *parent)
 			   &msp2_platform_data);
 	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
 			   &msp3_platform_data);
-
-	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-	platform_device_register(&ux500_pcm);
 }
 
 void mop500_msp_init(struct device *parent)
@@ -203,7 +200,4 @@ void mop500_msp_init(struct device *parent)
 			   &msp2_platform_data);
 	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
 			   &msp3_platform_data);
-
-	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-	platform_device_register(&ux500_pcm);
 }
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:43 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:43 +0100
Subject: [PATCH 17/22] ARM: ux500: Remove platform registration of MSP devices
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-18-git-send-email-lee.jones@linaro.org>

This patch removes platform device registration of all 4 MSP
devices. It also takes care of all redundant infrastructure now
that each of the ux500 audio components have been Device Tree
enabled.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   14 --------------
 arch/arm/mach-ux500/board-mop500.c     |    2 --
 arch/arm/mach-ux500/board-mop500.h     |    2 --
 3 files changed, 18 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 58768c2..326de5a 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -172,20 +172,6 @@ struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent)
-{
-	pr_info("Initialize MSP I2S-devices.\n");
-	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-			   &msp0_platform_data);
-	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
-			   &msp1_platform_data);
-	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
-			   &msp2_platform_data);
-	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
-			   &msp3_platform_data);
-}
-
 void mop500_msp_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0c141d5..f48d463 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -815,8 +815,6 @@ static void __init u8500_init_machine(void)
 
 		mop500_uib_init();
 
-	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-		mop500_of_msp_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3fbf48f..e56c983 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -98,8 +98,6 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_msp_init(struct device *parent);
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:44 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:44 +0100
Subject: [PATCH 18/22] ARM: ux500: Rename MSP board file to something more
 meaningful
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-19-git-send-email-lee.jones@linaro.org>

The 'msp' board file does more than just register MSP devices. It
also registers some other components necessary to get audio working
on ux500 based platforms; such as the PCM and Machine Drivers. For
that reason we're changing the filename to be more encompassing -
'audio'.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/Makefile             |    2 +-
 arch/arm/mach-ux500/board-mop500-audio.c |  189 ++++++++++++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500-msp.c   |  189 ------------------------------
 arch/arm/mach-ux500/board-mop500.c       |   10 +-
 arch/arm/mach-ux500/board-mop500.h       |    2 +-
 5 files changed, 196 insertions(+), 196 deletions(-)
 create mode 100644 arch/arm/mach-ux500/board-mop500-audio.c
 delete mode 100644 arch/arm/mach-ux500/board-mop500-msp.c

diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086f..1dc2cfa 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
 				board-mop500-uib.o board-mop500-stuib.o \
 				board-mop500-u8500uib.o \
 				board-mop500-pins.o \
-				board-mop500-msp.o
+				board-mop500-audio.o
 obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
new file mode 100644
index 0000000..e939d34
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/consumer.h>
+
+#include <plat/gpio-nomadik.h>
+#include <plat/pincfg.h>
+#include <plat/ste_dma40.h>
+
+#include <mach/devices.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/msp.h>
+
+#include "ste-dma40-db8500.h"
+#include "board-mop500.h"
+#include "devices-db8500.h"
+#include "pins-db8500.h"
+
+static struct stedma40_chan_cfg msp0_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp0_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+struct msp_i2s_platform_data msp0_platform_data = {
+	.id = MSP_I2S_0,
+	.msp_i2s_dma_rx = &msp0_dma_rx,
+	.msp_i2s_dma_tx = &msp0_dma_tx,
+};
+
+static struct stedma40_chan_cfg msp1_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp1_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+struct msp_i2s_platform_data msp1_platform_data = {
+	.id = MSP_I2S_1,
+	.msp_i2s_dma_rx = NULL,
+	.msp_i2s_dma_tx = &msp1_dma_tx,
+};
+
+static struct stedma40_chan_cfg msp2_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
+	.src_info.psize = STEDMA40_PSIZE_LOG_1,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp2_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	.use_fixed_channel = true,
+	.phy_channel = 1,
+
+	/* data_width is set during configuration */
+};
+
+static struct platform_device *db8500_add_msp_i2s(struct device *parent,
+			int id,
+			resource_size_t base, int irq,
+			struct msp_i2s_platform_data *pdata)
+{
+	struct platform_device *pdev;
+	struct resource res[] = {
+		DEFINE_RES_MEM(base, SZ_4K),
+		DEFINE_RES_IRQ(irq),
+	};
+
+	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
+		id, irq);
+	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
+						res, ARRAY_SIZE(res),
+						pdata, sizeof(*pdata));
+	if (!pdev) {
+		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
+			id);
+		return NULL;
+	}
+
+	return pdev;
+}
+
+/* Platform device for ASoC MOP500 machine */
+static struct platform_device snd_soc_mop500 = {
+	.name = "snd-soc-mop500",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
+};
+
+/* Platform device for Ux500-PCM */
+static struct platform_device ux500_pcm = {
+	.name = "ux500-pcm",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
+};
+
+struct msp_i2s_platform_data msp2_platform_data = {
+	.id = MSP_I2S_2,
+	.msp_i2s_dma_rx = &msp2_dma_rx,
+	.msp_i2s_dma_tx = &msp2_dma_tx,
+};
+
+struct msp_i2s_platform_data msp3_platform_data = {
+	.id		= MSP_I2S_3,
+	.msp_i2s_dma_rx	= &msp1_dma_rx,
+	.msp_i2s_dma_tx	= NULL,
+};
+
+void mop500_audio_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
+
+	pr_info("Initialize MSP I2S-devices.\n");
+	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+			   &msp0_platform_data);
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+			   &msp1_platform_data);
+	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+			   &msp2_platform_data);
+	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+			   &msp3_platform_data);
+}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
deleted file mode 100644
index 326de5a..0000000
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL), version 2
- */
-
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/pinctrl/consumer.h>
-
-#include <plat/gpio-nomadik.h>
-#include <plat/pincfg.h>
-#include <plat/ste_dma40.h>
-
-#include <mach/devices.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/msp.h>
-
-#include "ste-dma40-db8500.h"
-#include "board-mop500.h"
-#include "devices-db8500.h"
-#include "pins-db8500.h"
-
-static struct stedma40_chan_cfg msp0_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp0_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-struct msp_i2s_platform_data msp0_platform_data = {
-	.id = MSP_I2S_0,
-	.msp_i2s_dma_rx = &msp0_dma_rx,
-	.msp_i2s_dma_tx = &msp0_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp1_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp1_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-struct msp_i2s_platform_data msp1_platform_data = {
-	.id = MSP_I2S_1,
-	.msp_i2s_dma_rx = NULL,
-	.msp_i2s_dma_tx = &msp1_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp2_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-	.src_info.psize = STEDMA40_PSIZE_LOG_1,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp2_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	.use_fixed_channel = true,
-	.phy_channel = 1,
-
-	/* data_width is set during configuration */
-};
-
-static struct platform_device *db8500_add_msp_i2s(struct device *parent,
-			int id,
-			resource_size_t base, int irq,
-			struct msp_i2s_platform_data *pdata)
-{
-	struct platform_device *pdev;
-	struct resource res[] = {
-		DEFINE_RES_MEM(base, SZ_4K),
-		DEFINE_RES_IRQ(irq),
-	};
-
-	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
-		id, irq);
-	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
-						res, ARRAY_SIZE(res),
-						pdata, sizeof(*pdata));
-	if (!pdev) {
-		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
-			id);
-		return NULL;
-	}
-
-	return pdev;
-}
-
-/* Platform device for ASoC MOP500 machine */
-static struct platform_device snd_soc_mop500 = {
-	.name = "snd-soc-mop500",
-	.id = 0,
-	.dev = {
-		.platform_data = NULL,
-	},
-};
-
-/* Platform device for Ux500-PCM */
-static struct platform_device ux500_pcm = {
-	.name = "ux500-pcm",
-	.id = 0,
-	.dev = {
-		.platform_data = NULL,
-	},
-};
-
-struct msp_i2s_platform_data msp2_platform_data = {
-	.id = MSP_I2S_2,
-	.msp_i2s_dma_rx = &msp2_dma_rx,
-	.msp_i2s_dma_tx = &msp2_dma_tx,
-};
-
-struct msp_i2s_platform_data msp3_platform_data = {
-	.id		= MSP_I2S_3,
-	.msp_i2s_dma_rx	= &msp1_dma_rx,
-	.msp_i2s_dma_tx	= NULL,
-};
-
-void mop500_msp_init(struct device *parent)
-{
-	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
-	platform_device_register(&snd_soc_mop500);
-
-	pr_info("Initialize MSP I2S-devices.\n");
-	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-			   &msp0_platform_data);
-	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
-			   &msp1_platform_data);
-	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
-			   &msp2_platform_data);
-	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
-			   &msp3_platform_data);
-}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f48d463..a93b147 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -607,7 +607,7 @@ static void __init mop500_init_machine(void)
 	mop500_i2c_init(parent);
 	mop500_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	u8500_cryp1_hash1_init(parent);
@@ -641,7 +641,7 @@ static void __init snowball_init_machine(void)
 	mop500_i2c_init(parent);
 	snowball_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	/* This board has full regulator constraints */
@@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
 	mop500_i2c_init(parent);
 	hrefv60_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		mop500_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 		i2c_register_board_info(2, mop500_i2c2_devices,
@@ -826,7 +826,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		hrefv60_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index e56c983..a0f920d 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -97,7 +97,7 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
-void mop500_msp_init(struct device *parent);
+void mop500_audio_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:46 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:46 +0100
Subject: [PATCH 20/22] ARM: ux500: Add nodes for the MSP into Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-21-git-send-email-lee.jones@linaro.org>

This patch inserts all known MSP devices into the DBx5x0 Device Tree
disabled and enables the two important ones for the Snowball low-cost
development board.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  |   33 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts |    8 ++++++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 83ed692..32e063d 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -621,6 +621,39 @@
 			status = "disabled";
 		};
 
+		msp0: msp at 80123000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80123000 0x1000>;
+			interrupts = <0 31 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		msp1: msp at 80124000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80124000 0x1000>;
+			interrupts = <0 62 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		// HDMI sound
+		msp2: msp at 80117000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80117000 0x1000>;
+			interrupts = <0 98 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		msp3: msp at 80125000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80125000 0x1000>;
+			interrupts = <0 62 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
 		external-bus at 50000000 {
 			compatible = "simple-bus";
 			reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index df6fc57..fce4a00 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -83,6 +83,14 @@
 	};
 
 	soc-u9500 {
+		msp1: msp at 80124000 {
+			status = "okay";
+		};
+
+		msp3: msp at 80125000 {
+			status = "okay";
+		};
+
 		external-bus at 50000000 {
 			status = "okay";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:47 +0100
Subject: [PATCH 21/22] ARM: ux500: Add all encompassing sound node to the
 Snowball Device Tree
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-22-git-send-email-lee.jones@linaro.org>

This is where we link together all of the SoC sound components for
a given platform. This all encompassing sound node is only found
in the very lowest hierarchical DTS file, since the component mix may
well change from board variant to board variant.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/snowball.dts |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index fce4a00..2969997 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -83,6 +83,14 @@
 	};
 
 	soc-u9500 {
+
+		sound {
+			compatible = "stericsson,snd-soc-mop500";
+
+			stericsson,cpu-dai = <&msp1 &msp3>;
+			stericsson,audio-codec = <&codec>;
+		};
+
 		msp1: msp at 80124000 {
 			status = "okay";
 		};
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:48 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:48 +0100
Subject: [PATCH 22/22] Documentation: Add the AB8500 CODEC device to the MFD
 AB8500 doc
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-23-git-send-email-lee.jones@linaro.org>

Here we document the AB8500 Audio CODEC in the existing MFD AB8500 document.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/mfd/ab8500.txt |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index 69e757a..ce83c8d 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -23,6 +23,7 @@ Device                     IRQ Names              Supply Names   Description
 ab8500-bm                :                      :              : Battery Manager
 ab8500-btemp             :                      :              : Battery Temperature
 ab8500-charger           :                      :              : Battery Charger
+ab8500-codec             :                      :              : Audio Codec
 ab8500-fg                :                      :              : Fuel Gauge
 ab8500-gpadc             : HW_CONV_END          : vddadc       : Analogue to Digital Converter
                            SW_CONV_END          :              :
@@ -52,6 +53,14 @@ Optional child device properties:
                            supplied in the interrupts property
 - <supply_name>-supply   : contains a phandle to the regulator supply node in Device Tree
 
+Non-standard child device properties:
+ - Audio CODEC:
+   - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential)
+   - stericsson,amic1a-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic1b-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic2-bias-vamic1           : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,earpeice-cmv                : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
+
 ab8500 at 5 {
          compatible = "stericsson,ab8500";
          reg = <5>; /* mailbox 5 is i2c */
@@ -110,6 +119,12 @@ ab8500 at 5 {
                 compatible = "stericsson,ab8500-pwm";
         };
 
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
+
         ab8500-regulators {
                 compatible = "stericsson,ab8500-regulator";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:47:45 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:47:45 +0100
Subject: [PATCH 19/22] ARM: ux500: Rename db8500.dtsi to dbx5x0.dtsi to
 encompass the u9500, u8540 and u9540
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527268-5964-20-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi  |  633 ----------------------------------------
 arch/arm/boot/dts/dbx5x0.dtsi  |  633 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts |    2 +-
 3 files changed, 634 insertions(+), 634 deletions(-)
 delete mode 100644 arch/arm/boot/dts/db8500.dtsi
 create mode 100644 arch/arm/boot/dts/dbx5x0.dtsi

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
deleted file mode 100644
index 83ed692..0000000
--- a/arch/arm/boot/dts/db8500.dtsi
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * Copyright 2012 Linaro Ltd
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-	soc-u9500 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "stericsson,db8500";
-		interrupt-parent = <&intc>;
-		ranges;
-
-		intc: interrupt-controller at a0411000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			#address-cells = <1>;
-			interrupt-controller;
-			reg = <0xa0411000 0x1000>,
-			      <0xa0410100 0x100>;
-		};
-
-		L2: l2-cache {
-			compatible = "arm,pl310-cache";
-			reg = <0xa0412000 0x1000>;
-			interrupts = <0 13 4>;
-			cache-unified;
-			cache-level = <2>;
-		};
-
-		pmu {
-			compatible = "arm,cortex-a9-pmu";
-			interrupts = <0 7 0x4>;
-		};
-
-		timer at a0410600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0xa0410600 0x20>;
-			interrupts = <1 13 0x304>;
-		};
-
-		rtc at 80154000 {
-			compatible = "arm,rtc-pl031", "arm,primecell";
-			reg = <0x80154000 0x1000>;
-			interrupts = <0 18 0x4>;
-		};
-
-		gpio0: gpio at 8012e000 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8012e000 0x80>;
-			interrupts = <0 119 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <0>;
-		};
-
-		gpio1: gpio at 8012e080 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8012e080 0x80>;
-			interrupts = <0 120 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <1>;
-		};
-
-		gpio2: gpio at 8000e000 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8000e000 0x80>;
-			interrupts = <0 121 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <2>;
-		};
-
-		gpio3: gpio at 8000e080 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8000e080 0x80>;
-			interrupts = <0 122 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <3>;
-		};
-
-		gpio4: gpio at 8000e100 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8000e100 0x80>;
-			interrupts = <0 123 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <4>;
-		};
-
-		gpio5: gpio at 8000e180 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8000e180 0x80>;
-			interrupts = <0 124 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <5>;
-		};
-
-		gpio6: gpio at 8011e000 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8011e000 0x80>;
-			interrupts = <0 125 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <6>;
-		};
-
-		gpio7: gpio at 8011e080 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0x8011e080 0x80>;
-			interrupts = <0 126 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <7>;
-		};
-
-		gpio8: gpio at a03fe000 {
-			compatible = "stericsson,db8500-gpio",
-				"st,nomadik-gpio";
-			reg =  <0xa03fe000 0x80>;
-			interrupts = <0 127 0x4>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			st,supports-sleepmode;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-bank = <8>;
-		};
-
-		pinctrl {
-			compatible = "stericsson,nmk_pinctrl";
-		};
-
-		usb at a03e0000 {
-			compatible = "stericsson,db8500-musb",
-				"mentor,musb";
-			reg = <0xa03e0000 0x10000>;
-			interrupts = <0 23 0x4>;
-		};
-
-		dma-controller at 801C0000 {
-			compatible = "stericsson,db8500-dma40",
-					"stericsson,dma40";
-			reg = <0x801C0000 0x1000 0x40010000 0x800>;
-			interrupts = <0 25 0x4>;
-		};
-
-		prcmu at 80157000 {
-			compatible = "stericsson,db8500-prcmu";
-			reg = <0x80157000 0x1000>;
-			interrupts = <0 47 0x4>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			prcmu-timer-4 at 80157450 {
-				compatible = "stericsson,db8500-prcmu-timer-4";
-				reg = <0x80157450 0xC>;
-			};
-
-			db8500-prcmu-regulators {
-				compatible = "stericsson,db8500-prcmu-regulator";
-
-				// DB8500_REGULATOR_VAPE
-				db8500_vape_reg: db8500_vape {
-					regulator-compatible = "db8500_vape";
-					regulator-name = "db8500-vape";
-					regulator-always-on;
-				};
-
-				// DB8500_REGULATOR_VARM
-				db8500_varm_reg: db8500_varm {
-					regulator-compatible = "db8500_varm";
-					regulator-name = "db8500-varm";
-				};
-
-				// DB8500_REGULATOR_VMODEM
-				db8500_vmodem_reg: db8500_vmodem {
-					regulator-compatible = "db8500_vmodem";
-					regulator-name = "db8500-vmodem";
-				};
-
-				// DB8500_REGULATOR_VPLL
-				db8500_vpll_reg: db8500_vpll {
-					regulator-compatible = "db8500_vpll";
-					regulator-name = "db8500-vpll";
-				};
-
-				// DB8500_REGULATOR_VSMPS1
-				db8500_vsmps1_reg: db8500_vsmps1 {
-					regulator-compatible = "db8500_vsmps1";
-					regulator-name = "db8500-vsmps1";
-				};
-
-				// DB8500_REGULATOR_VSMPS2
-				db8500_vsmps2_reg: db8500_vsmps2 {
-					regulator-compatible = "db8500_vsmps2";
-					regulator-name = "db8500-vsmps2";
-				};
-
-				// DB8500_REGULATOR_VSMPS3
-				db8500_vsmps3_reg: db8500_vsmps3 {
-					regulator-compatible = "db8500_vsmps3";
-					regulator-name = "db8500-vsmps3";
-				};
-
-				// DB8500_REGULATOR_VRF1
-				db8500_vrf1_reg: db8500_vrf1 {
-					regulator-compatible = "db8500_vrf1";
-					regulator-name = "db8500-vrf1";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SVAMMDSP
-				db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
-					regulator-compatible = "db8500_sva_mmdsp";
-					regulator-name = "db8500-sva-mmdsp";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
-				db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
-					regulator-compatible = "db8500_sva_mmdsp_ret";
-					regulator-name = "db8500-sva-mmdsp-ret";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SVAPIPE
-				db8500_sva_pipe_reg: db8500_sva_pipe {
-					regulator-compatible = "db8500_sva_pipe";
-					regulator-name = "db8500_sva_pipe";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SIAMMDSP
-				db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
-					regulator-compatible = "db8500_sia_mmdsp";
-					regulator-name = "db8500_sia_mmdsp";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
-				db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
-					regulator-name = "db8500-sia-mmdsp-ret";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SIAPIPE
-				db8500_sia_pipe_reg: db8500_sia_pipe {
-					regulator-compatible = "db8500_sia_pipe";
-					regulator-name = "db8500-sia-pipe";
-				};
-
-				// DB8500_REGULATOR_SWITCH_SGA
-				db8500_sga_reg: db8500_sga {
-					regulator-compatible = "db8500_sga";
-					regulator-name = "db8500-sga";
-					vin-supply = <&db8500_vape_reg>;
-				};
-
-				// DB8500_REGULATOR_SWITCH_B2R2_MCDE
-				db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
-					regulator-compatible = "db8500_b2r2_mcde";
-					regulator-name = "db8500-b2r2-mcde";
-					vin-supply = <&db8500_vape_reg>;
-				};
-
-				// DB8500_REGULATOR_SWITCH_ESRAM12
-				db8500_esram12_reg: db8500_esram12 {
-					regulator-compatible = "db8500_esram12";
-					regulator-name = "db8500-esram12";
-				};
-
-				// DB8500_REGULATOR_SWITCH_ESRAM12RET
-				db8500_esram12_ret_reg: db8500_esram12_ret {
-					regulator-compatible = "db8500_esram12_ret";
-					regulator-name = "db8500-esram12-ret";
-				};
-
-				// DB8500_REGULATOR_SWITCH_ESRAM34
-				db8500_esram34_reg: db8500_esram34 {
-					regulator-compatible = "db8500_esram34";
-					regulator-name = "db8500-esram34";
-				};
-
-				// DB8500_REGULATOR_SWITCH_ESRAM34RET
-				db8500_esram34_ret_reg: db8500_esram34_ret {
-					regulator-compatible = "db8500_esram34_ret";
-					regulator-name = "db8500-esram34-ret";
-				};
-			};
-
-			ab8500 at 5 {
-				compatible = "stericsson,ab8500";
-				reg = <5>; /* mailbox 5 is i2c */
-				interrupts = <0 40 0x4>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-
-				ab8500-rtc {
-					compatible = "stericsson,ab8500-rtc";
-					interrupts = <17 0x4
-					              18 0x4>;
-					interrupt-names = "60S", "ALARM";
-				};
-
-				ab8500-gpadc {
-					compatible = "stericsson,ab8500-gpadc";
-					interrupts = <32 0x4
-						      39 0x4>;
-					interrupt-names = "HW_CONV_END", "SW_CONV_END";
-					vddadc-supply = <&ab8500_ldo_tvout_reg>;
-				};
-
-				ab8500-usb {
-					compatible = "stericsson,ab8500-usb";
-					interrupts = < 90 0x4
-						       96 0x4
-						       14 0x4
-						       15 0x4
-						       79 0x4
-						       74 0x4
-						       75 0x4>;
-					interrupt-names = "ID_WAKEUP_R",
-							  "ID_WAKEUP_F",
-							  "VBUS_DET_F",
-							  "VBUS_DET_R",
-							  "USB_LINK_STATUS",
-							  "USB_ADP_PROBE_PLUG",
-							  "USB_ADP_PROBE_UNPLUG";
-					vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
-					v-ape-supply = <&db8500_vape_reg>;
-					musb_1v8-supply = <&db8500_vsmps2_reg>;
-				};
-
-				ab8500-ponkey {
-					compatible = "stericsson,ab8500-ponkey";
-					interrupts = <6 0x4
-						      7 0x4>;
-					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
-				};
-
-				ab8500-sysctrl {
-					compatible = "stericsson,ab8500-sysctrl";
-				};
-
-				ab8500-pwm {
-					compatible = "stericsson,ab8500-pwm";
-				};
-
-				ab8500-debugfs {
-					compatible = "stericsson,ab8500-debug";
-				};
-
-				codec: ab8500-codec {
-					compatible = "stericsson,ab8500-codec";
-
-					stericsson,earpeice-cmv = <950>; /* Units in mV. */
-				};
-
-				ab8500-regulators {
-					compatible = "stericsson,ab8500-regulator";
-
-					// supplies to the display/camera
-					ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
-						regulator-compatible = "ab8500_ldo_aux1";
-						regulator-name = "V-DISPLAY";
-						regulator-min-microvolt = <2500000>;
-						regulator-max-microvolt = <2900000>;
-						regulator-boot-on;
-						/* BUG: If turned off MMC will be affected. */
-						regulator-always-on;
-					};
-
-					// supplies to the on-board eMMC
-					ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
-						regulator-compatible = "ab8500_ldo_aux2";
-						regulator-name = "V-eMMC1";
-						regulator-min-microvolt = <1100000>;
-						regulator-max-microvolt = <3300000>;
-					};
-
-					// supply for VAUX3; SDcard slots
-					ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
-						regulator-compatible = "ab8500_ldo_aux3";
-						regulator-name = "V-MMC-SD";
-						regulator-min-microvolt = <1100000>;
-						regulator-max-microvolt = <3300000>;
-					};
-
-					// supply for v-intcore12; VINTCORE12 LDO
-					ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
-						regulator-compatible = "ab8500_ldo_initcore";
-						regulator-name = "V-INTCORE";
-					};
-
-					// supply for tvout; gpadc; TVOUT LDO
-					ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
-						regulator-compatible = "ab8500_ldo_tvout";
-						regulator-name = "V-TVOUT";
-					};
-
-					// supply for ab8500-usb; USB LDO
-					ab8500_ldo_usb_reg: ab8500_ldo_usb {
-						regulator-compatible = "ab8500_ldo_usb";
-						regulator-name = "dummy";
-					};
-
-					// supply for ab8500-vaudio; VAUDIO LDO
-					ab8500_ldo_audio_reg: ab8500_ldo_audio {
-						regulator-compatible = "ab8500_ldo_audio";
-						regulator-name = "V-AUD";
-					};
-
-					// supply for v-anamic1 VAMic1-LDO
-					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
-						regulator-compatible = "ab8500_ldo_anamic1";
-						regulator-name = "V-AMIC1";
-					};
-
-					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
-					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
-						regulator-compatible = "ab8500_ldo_amamic2";
-						regulator-name = "V-AMIC2";
-					};
-
-					// supply for v-dmic; VDMIC LDO
-					ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
-						regulator-compatible = "ab8500_ldo_dmic";
-						regulator-name = "V-DMIC";
-					};
-
-					// supply for U8500 CSI/DSI; VANA LDO
-					ab8500_ldo_ana_reg: ab8500_ldo_ana {
-						regulator-compatible = "ab8500_ldo_ana";
-						regulator-name = "V-CSI/DSI";
-					};
-				};
-			};
-		};
-
-		i2c at 80004000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-			reg = <0x80004000 0x1000>;
-			interrupts = <0 21 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			clock-frequency = <400000>;
-			stericsson,slsu = <0xe>;
-			stericsson,tft = <1>;
-			stericsson,rft = <8>;
-			stericsson,timeout = <200>;
-			stericsson,i2c_freq_mode_fast;
-		};
-
-		i2c at 80122000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-			reg = <0x80122000 0x1000>;
-			interrupts = <0 22 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			clock-frequency = <400000>;
-			stericsson,slsu = <0xe>;
-			stericsson,tft = <1>;
-			stericsson,rft = <8>;
-			stericsson,timeout = <200>;
-			stericsson,i2c_freq_mode_fast;
-		};
-
-		i2c at 80128000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-			reg = <0x80128000 0x1000>;
-			interrupts = <0 55 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			clock-frequency = <400000>;
-			stericsson,slsu = <0xe>;
-			stericsson,tft = <1>;
-			stericsson,rft = <8>;
-			stericsson,timeout = <200>;
-			stericsson,i2c_freq_mode_fast;
-		};
-
-		i2c at 80110000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-			reg = <0x80110000 0x1000>;
-			interrupts = <0 12 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			clock-frequency = <400000>;
-			stericsson,slsu = <0xe>;
-			stericsson,tft = <1>;
-			stericsson,rft = <8>;
-			stericsson,timeout = <200>;
-			stericsson,i2c_freq_mode_fast;
-		};
-
-		i2c at 8012a000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
-			reg = <0x8012a000 0x1000>;
-			interrupts = <0 51 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			clock-frequency = <400000>;
-			stericsson,slsu = <0xe>;
-			stericsson,tft = <1>;
-			stericsson,rft = <8>;
-			stericsson,timeout = <200>;
-			stericsson,i2c_freq_mode_fast;
-		};
-
-		ssp at 80002000 {
-			compatible = "arm,pl022", "arm,primecell";
-			reg = <80002000 0x1000>;
-			interrupts = <0 14 0x4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			// Add one of these for each child device
-			cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
-				    &gpio6 22 0x4 &gpio7 0 0x4>;
-
-		};
-
-		uart at 80120000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x80120000 0x1000>;
-			interrupts = <0 11 0x4>;
-			status = "disabled";
-		};
-		uart at 80121000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x80121000 0x1000>;
-			interrupts = <0 19 0x4>;
-			status = "disabled";
-		};
-		uart at 80007000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x80007000 0x1000>;
-			interrupts = <0 26 0x4>;
-			status = "disabled";
-		};
-
-		sdi at 80126000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80126000 0x1000>;
-			interrupts = <0 60 0x4>;
-			status = "disabled";
-		};
-		sdi at 80118000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80118000 0x1000>;
-			interrupts = <0 50 0x4>;
-			status = "disabled";
-		};
-		sdi at 80005000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80005000 0x1000>;
-			interrupts = <0 41 0x4>;
-			status = "disabled";
-		};
-		sdi at 80119000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80119000 0x1000>;
-			interrupts = <0 59 0x4>;
-			status = "disabled";
-		};
-		sdi at 80114000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80114000 0x1000>;
-			interrupts = <0 99 0x4>;
-			status = "disabled";
-		};
-		sdi at 80008000 {
-			compatible = "arm,pl18x", "arm,primecell";
-			reg = <0x80114000 0x1000>;
-			interrupts = <0 100 0x4>;
-			status = "disabled";
-		};
-
-		external-bus at 50000000 {
-			compatible = "simple-bus";
-			reg = <0x50000000 0x4000000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x50000000 0x4000000>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
new file mode 100644
index 0000000..83ed692
--- /dev/null
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -0,0 +1,633 @@
+/*
+ * Copyright 2012 Linaro Ltd
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	soc-u9500 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "stericsson,db8500";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		intc: interrupt-controller at a0411000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0xa0411000 0x1000>,
+			      <0xa0410100 0x100>;
+		};
+
+		L2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0xa0412000 0x1000>;
+			interrupts = <0 13 4>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <0 7 0x4>;
+		};
+
+		timer at a0410600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xa0410600 0x20>;
+			interrupts = <1 13 0x304>;
+		};
+
+		rtc at 80154000 {
+			compatible = "arm,rtc-pl031", "arm,primecell";
+			reg = <0x80154000 0x1000>;
+			interrupts = <0 18 0x4>;
+		};
+
+		gpio0: gpio at 8012e000 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8012e000 0x80>;
+			interrupts = <0 119 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <0>;
+		};
+
+		gpio1: gpio at 8012e080 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8012e080 0x80>;
+			interrupts = <0 120 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <1>;
+		};
+
+		gpio2: gpio at 8000e000 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8000e000 0x80>;
+			interrupts = <0 121 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <2>;
+		};
+
+		gpio3: gpio at 8000e080 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8000e080 0x80>;
+			interrupts = <0 122 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <3>;
+		};
+
+		gpio4: gpio at 8000e100 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8000e100 0x80>;
+			interrupts = <0 123 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <4>;
+		};
+
+		gpio5: gpio at 8000e180 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8000e180 0x80>;
+			interrupts = <0 124 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <5>;
+		};
+
+		gpio6: gpio at 8011e000 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8011e000 0x80>;
+			interrupts = <0 125 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <6>;
+		};
+
+		gpio7: gpio at 8011e080 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0x8011e080 0x80>;
+			interrupts = <0 126 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <7>;
+		};
+
+		gpio8: gpio at a03fe000 {
+			compatible = "stericsson,db8500-gpio",
+				"st,nomadik-gpio";
+			reg =  <0xa03fe000 0x80>;
+			interrupts = <0 127 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			st,supports-sleepmode;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-bank = <8>;
+		};
+
+		pinctrl {
+			compatible = "stericsson,nmk_pinctrl";
+		};
+
+		usb at a03e0000 {
+			compatible = "stericsson,db8500-musb",
+				"mentor,musb";
+			reg = <0xa03e0000 0x10000>;
+			interrupts = <0 23 0x4>;
+		};
+
+		dma-controller at 801C0000 {
+			compatible = "stericsson,db8500-dma40",
+					"stericsson,dma40";
+			reg = <0x801C0000 0x1000 0x40010000 0x800>;
+			interrupts = <0 25 0x4>;
+		};
+
+		prcmu at 80157000 {
+			compatible = "stericsson,db8500-prcmu";
+			reg = <0x80157000 0x1000>;
+			interrupts = <0 47 0x4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			prcmu-timer-4 at 80157450 {
+				compatible = "stericsson,db8500-prcmu-timer-4";
+				reg = <0x80157450 0xC>;
+			};
+
+			db8500-prcmu-regulators {
+				compatible = "stericsson,db8500-prcmu-regulator";
+
+				// DB8500_REGULATOR_VAPE
+				db8500_vape_reg: db8500_vape {
+					regulator-compatible = "db8500_vape";
+					regulator-name = "db8500-vape";
+					regulator-always-on;
+				};
+
+				// DB8500_REGULATOR_VARM
+				db8500_varm_reg: db8500_varm {
+					regulator-compatible = "db8500_varm";
+					regulator-name = "db8500-varm";
+				};
+
+				// DB8500_REGULATOR_VMODEM
+				db8500_vmodem_reg: db8500_vmodem {
+					regulator-compatible = "db8500_vmodem";
+					regulator-name = "db8500-vmodem";
+				};
+
+				// DB8500_REGULATOR_VPLL
+				db8500_vpll_reg: db8500_vpll {
+					regulator-compatible = "db8500_vpll";
+					regulator-name = "db8500-vpll";
+				};
+
+				// DB8500_REGULATOR_VSMPS1
+				db8500_vsmps1_reg: db8500_vsmps1 {
+					regulator-compatible = "db8500_vsmps1";
+					regulator-name = "db8500-vsmps1";
+				};
+
+				// DB8500_REGULATOR_VSMPS2
+				db8500_vsmps2_reg: db8500_vsmps2 {
+					regulator-compatible = "db8500_vsmps2";
+					regulator-name = "db8500-vsmps2";
+				};
+
+				// DB8500_REGULATOR_VSMPS3
+				db8500_vsmps3_reg: db8500_vsmps3 {
+					regulator-compatible = "db8500_vsmps3";
+					regulator-name = "db8500-vsmps3";
+				};
+
+				// DB8500_REGULATOR_VRF1
+				db8500_vrf1_reg: db8500_vrf1 {
+					regulator-compatible = "db8500_vrf1";
+					regulator-name = "db8500-vrf1";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SVAMMDSP
+				db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+					regulator-compatible = "db8500_sva_mmdsp";
+					regulator-name = "db8500-sva-mmdsp";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
+				db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+					regulator-compatible = "db8500_sva_mmdsp_ret";
+					regulator-name = "db8500-sva-mmdsp-ret";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SVAPIPE
+				db8500_sva_pipe_reg: db8500_sva_pipe {
+					regulator-compatible = "db8500_sva_pipe";
+					regulator-name = "db8500_sva_pipe";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SIAMMDSP
+				db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+					regulator-compatible = "db8500_sia_mmdsp";
+					regulator-name = "db8500_sia_mmdsp";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
+				db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
+					regulator-name = "db8500-sia-mmdsp-ret";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SIAPIPE
+				db8500_sia_pipe_reg: db8500_sia_pipe {
+					regulator-compatible = "db8500_sia_pipe";
+					regulator-name = "db8500-sia-pipe";
+				};
+
+				// DB8500_REGULATOR_SWITCH_SGA
+				db8500_sga_reg: db8500_sga {
+					regulator-compatible = "db8500_sga";
+					regulator-name = "db8500-sga";
+					vin-supply = <&db8500_vape_reg>;
+				};
+
+				// DB8500_REGULATOR_SWITCH_B2R2_MCDE
+				db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+					regulator-compatible = "db8500_b2r2_mcde";
+					regulator-name = "db8500-b2r2-mcde";
+					vin-supply = <&db8500_vape_reg>;
+				};
+
+				// DB8500_REGULATOR_SWITCH_ESRAM12
+				db8500_esram12_reg: db8500_esram12 {
+					regulator-compatible = "db8500_esram12";
+					regulator-name = "db8500-esram12";
+				};
+
+				// DB8500_REGULATOR_SWITCH_ESRAM12RET
+				db8500_esram12_ret_reg: db8500_esram12_ret {
+					regulator-compatible = "db8500_esram12_ret";
+					regulator-name = "db8500-esram12-ret";
+				};
+
+				// DB8500_REGULATOR_SWITCH_ESRAM34
+				db8500_esram34_reg: db8500_esram34 {
+					regulator-compatible = "db8500_esram34";
+					regulator-name = "db8500-esram34";
+				};
+
+				// DB8500_REGULATOR_SWITCH_ESRAM34RET
+				db8500_esram34_ret_reg: db8500_esram34_ret {
+					regulator-compatible = "db8500_esram34_ret";
+					regulator-name = "db8500-esram34-ret";
+				};
+			};
+
+			ab8500 at 5 {
+				compatible = "stericsson,ab8500";
+				reg = <5>; /* mailbox 5 is i2c */
+				interrupts = <0 40 0x4>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				ab8500-rtc {
+					compatible = "stericsson,ab8500-rtc";
+					interrupts = <17 0x4
+					              18 0x4>;
+					interrupt-names = "60S", "ALARM";
+				};
+
+				ab8500-gpadc {
+					compatible = "stericsson,ab8500-gpadc";
+					interrupts = <32 0x4
+						      39 0x4>;
+					interrupt-names = "HW_CONV_END", "SW_CONV_END";
+					vddadc-supply = <&ab8500_ldo_tvout_reg>;
+				};
+
+				ab8500-usb {
+					compatible = "stericsson,ab8500-usb";
+					interrupts = < 90 0x4
+						       96 0x4
+						       14 0x4
+						       15 0x4
+						       79 0x4
+						       74 0x4
+						       75 0x4>;
+					interrupt-names = "ID_WAKEUP_R",
+							  "ID_WAKEUP_F",
+							  "VBUS_DET_F",
+							  "VBUS_DET_R",
+							  "USB_LINK_STATUS",
+							  "USB_ADP_PROBE_PLUG",
+							  "USB_ADP_PROBE_UNPLUG";
+					vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+					v-ape-supply = <&db8500_vape_reg>;
+					musb_1v8-supply = <&db8500_vsmps2_reg>;
+				};
+
+				ab8500-ponkey {
+					compatible = "stericsson,ab8500-ponkey";
+					interrupts = <6 0x4
+						      7 0x4>;
+					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
+				};
+
+				ab8500-sysctrl {
+					compatible = "stericsson,ab8500-sysctrl";
+				};
+
+				ab8500-pwm {
+					compatible = "stericsson,ab8500-pwm";
+				};
+
+				ab8500-debugfs {
+					compatible = "stericsson,ab8500-debug";
+				};
+
+				codec: ab8500-codec {
+					compatible = "stericsson,ab8500-codec";
+
+					stericsson,earpeice-cmv = <950>; /* Units in mV. */
+				};
+
+				ab8500-regulators {
+					compatible = "stericsson,ab8500-regulator";
+
+					// supplies to the display/camera
+					ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+						regulator-compatible = "ab8500_ldo_aux1";
+						regulator-name = "V-DISPLAY";
+						regulator-min-microvolt = <2500000>;
+						regulator-max-microvolt = <2900000>;
+						regulator-boot-on;
+						/* BUG: If turned off MMC will be affected. */
+						regulator-always-on;
+					};
+
+					// supplies to the on-board eMMC
+					ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+						regulator-compatible = "ab8500_ldo_aux2";
+						regulator-name = "V-eMMC1";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <3300000>;
+					};
+
+					// supply for VAUX3; SDcard slots
+					ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+						regulator-compatible = "ab8500_ldo_aux3";
+						regulator-name = "V-MMC-SD";
+						regulator-min-microvolt = <1100000>;
+						regulator-max-microvolt = <3300000>;
+					};
+
+					// supply for v-intcore12; VINTCORE12 LDO
+					ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+						regulator-compatible = "ab8500_ldo_initcore";
+						regulator-name = "V-INTCORE";
+					};
+
+					// supply for tvout; gpadc; TVOUT LDO
+					ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+						regulator-compatible = "ab8500_ldo_tvout";
+						regulator-name = "V-TVOUT";
+					};
+
+					// supply for ab8500-usb; USB LDO
+					ab8500_ldo_usb_reg: ab8500_ldo_usb {
+						regulator-compatible = "ab8500_ldo_usb";
+						regulator-name = "dummy";
+					};
+
+					// supply for ab8500-vaudio; VAUDIO LDO
+					ab8500_ldo_audio_reg: ab8500_ldo_audio {
+						regulator-compatible = "ab8500_ldo_audio";
+						regulator-name = "V-AUD";
+					};
+
+					// supply for v-anamic1 VAMic1-LDO
+					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+						regulator-compatible = "ab8500_ldo_anamic1";
+						regulator-name = "V-AMIC1";
+					};
+
+					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
+					ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+						regulator-compatible = "ab8500_ldo_amamic2";
+						regulator-name = "V-AMIC2";
+					};
+
+					// supply for v-dmic; VDMIC LDO
+					ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+						regulator-compatible = "ab8500_ldo_dmic";
+						regulator-name = "V-DMIC";
+					};
+
+					// supply for U8500 CSI/DSI; VANA LDO
+					ab8500_ldo_ana_reg: ab8500_ldo_ana {
+						regulator-compatible = "ab8500_ldo_ana";
+						regulator-name = "V-CSI/DSI";
+					};
+				};
+			};
+		};
+
+		i2c at 80004000 {
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			reg = <0x80004000 0x1000>;
+			interrupts = <0 21 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-frequency = <400000>;
+			stericsson,slsu = <0xe>;
+			stericsson,tft = <1>;
+			stericsson,rft = <8>;
+			stericsson,timeout = <200>;
+			stericsson,i2c_freq_mode_fast;
+		};
+
+		i2c at 80122000 {
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			reg = <0x80122000 0x1000>;
+			interrupts = <0 22 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-frequency = <400000>;
+			stericsson,slsu = <0xe>;
+			stericsson,tft = <1>;
+			stericsson,rft = <8>;
+			stericsson,timeout = <200>;
+			stericsson,i2c_freq_mode_fast;
+		};
+
+		i2c at 80128000 {
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			reg = <0x80128000 0x1000>;
+			interrupts = <0 55 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-frequency = <400000>;
+			stericsson,slsu = <0xe>;
+			stericsson,tft = <1>;
+			stericsson,rft = <8>;
+			stericsson,timeout = <200>;
+			stericsson,i2c_freq_mode_fast;
+		};
+
+		i2c at 80110000 {
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			reg = <0x80110000 0x1000>;
+			interrupts = <0 12 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-frequency = <400000>;
+			stericsson,slsu = <0xe>;
+			stericsson,tft = <1>;
+			stericsson,rft = <8>;
+			stericsson,timeout = <200>;
+			stericsson,i2c_freq_mode_fast;
+		};
+
+		i2c at 8012a000 {
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			reg = <0x8012a000 0x1000>;
+			interrupts = <0 51 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-frequency = <400000>;
+			stericsson,slsu = <0xe>;
+			stericsson,tft = <1>;
+			stericsson,rft = <8>;
+			stericsson,timeout = <200>;
+			stericsson,i2c_freq_mode_fast;
+		};
+
+		ssp at 80002000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <80002000 0x1000>;
+			interrupts = <0 14 0x4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			// Add one of these for each child device
+			cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
+				    &gpio6 22 0x4 &gpio7 0 0x4>;
+
+		};
+
+		uart at 80120000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80120000 0x1000>;
+			interrupts = <0 11 0x4>;
+			status = "disabled";
+		};
+		uart at 80121000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80121000 0x1000>;
+			interrupts = <0 19 0x4>;
+			status = "disabled";
+		};
+		uart at 80007000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80007000 0x1000>;
+			interrupts = <0 26 0x4>;
+			status = "disabled";
+		};
+
+		sdi at 80126000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80126000 0x1000>;
+			interrupts = <0 60 0x4>;
+			status = "disabled";
+		};
+		sdi at 80118000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80118000 0x1000>;
+			interrupts = <0 50 0x4>;
+			status = "disabled";
+		};
+		sdi at 80005000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80005000 0x1000>;
+			interrupts = <0 41 0x4>;
+			status = "disabled";
+		};
+		sdi at 80119000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80119000 0x1000>;
+			interrupts = <0 59 0x4>;
+			status = "disabled";
+		};
+		sdi at 80114000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80114000 0x1000>;
+			interrupts = <0 99 0x4>;
+			status = "disabled";
+		};
+		sdi at 80008000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80114000 0x1000>;
+			interrupts = <0 100 0x4>;
+			status = "disabled";
+		};
+
+		external-bus at 50000000 {
+			compatible = "simple-bus";
+			reg = <0x50000000 0x4000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x50000000 0x4000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4..df6fc57 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "db8500.dtsi"
+/include/ "dbx5x0.dtsi"
 
 / {
 	model = "Calao Systems Snowball platform with device tree";
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:47 +0100
Subject: [PATCH 0/8] Changes surrounding IRQs and IRQ domains 
Message-ID: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>

Here we apply some fixes to the way the AB8500 handles IRQs and
provide the DB8500 with an IRQ domain. We also handle hwirq to
virq conversion slightly differently when registering MFD devices.
The other changes pertain to the way IRQs are requested and dealt
with by AB8500 child devices.

 arch/arm/boot/dts/dbx5x0.dtsi      |    3 ++
 drivers/input/misc/ab8500-ponkey.c |    4 +--
 drivers/mfd/ab8500-core.c          |    3 +-
 drivers/mfd/db8500-prcmu.c         |   54 +++++++++++++++++++++++++++---------
 drivers/mfd/mfd-core.c             |    2 +-
 include/linux/mfd/db8500-prcmu.h   |    2 ++
 include/linux/of_irq.h             |    5 ++++
 kernel/irq/irqdomain.c             |    7 +++++
 8 files changed, 63 insertions(+), 17 deletions(-)



From lee.jones at linaro.org  Thu Aug  9 11:53:48 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:48 +0100
Subject: [PATCH 1/8] of/irq: Create stub for of_irq_find_parent when !CONFIG_OF
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-2-git-send-email-lee.jones@linaro.org>

of_irq_find_parent is a handy function to use outside the confines of
the Open Firmware subsystem. One such use-case is when the IRQ Domain
wishes to find an IRQ domain for a given device node. Currently it can
not take any notice of the 'interrupt-parent' property. Instead it
just uses the first IRQ controller as it climbs the Device Tree. If
we were to use this as a precursor the resultant controller is more
likely to be correct.

CC: Rob Herring <rob.herring at calxeda.com>
CC: devicetree-discuss at lists.ozlabs.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/of_irq.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index 1717cd9..b8e2411 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -83,6 +83,11 @@ static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
 {
 	return 0;
 }
+
+static inline void *of_irq_find_parent(struct device_node *child)
+{
+	return NULL;
+}
 #endif /* !CONFIG_OF */
 
 #endif /* __OF_IRQ_H */
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:50 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:50 +0100
Subject: [PATCH 3/8] ARM: ux500: Identify the PRCMU as an interrupt controller
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-4-git-send-email-lee.jones@linaro.org>

We're just about to provide the DB8500-PRCMU with its own IRQ domain,
so that its subordinate drivers can use it as an interrupt controller.
It's obligatory for all IRQ controllers to reference themselves as
such from its own node in Device Tree. This patch does just that.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 32e063d..6da7ccb 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
 			interrupts = <0 47 0x4>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
 			ranges;
 
 			prcmu-timer-4 at 80157450 {
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:51 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:51 +0100
Subject: [PATCH 4/8] ARM: ux500: Force AB8500 to use the GIC as its interrupt
 controller
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-5-git-send-email-lee.jones@linaro.org>

It's understood that the AB8500 should be subordinate to the DB8500;
however, the AB8500 uses the GIC as it's interrupt controller. If
we do not specify which IRQ controller to use the default is to use
the next encountered IRQ controller as we climb the tree. This would
be the DB8500. This patch ensures the AB8500 makes use of the correct
interrupt controller.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 6da7ccb..5106662 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -332,6 +332,7 @@
 			ab8500 at 5 {
 				compatible = "stericsson,ab8500";
 				reg = <5>; /* mailbox 5 is i2c */
+				interrupt-parent = <&intc>;
 				interrupts = <0 40 0x4>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:53 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:53 +0100
Subject: [PATCH 6/8] mfd: Use interrupt-parent as IRQ controller if specified
 in DT
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-7-git-send-email-lee.jones@linaro.org>

Without this patch the default behaviour is to climb the Device
Tree and use the first encountered interrupt controller. This
does not take into account if a device node has specified to use
a particular IRQ controller using the interrupt-parent property.
This patch ensures that property is adhered to.

CC: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/mfd-core.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 0c3a01c..bb5e753 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -97,7 +97,7 @@ static int mfd_add_device(struct device *parent, int id,
 		for_each_child_of_node(parent->of_node, np) {
 			if (of_device_is_compatible(np, cell->of_compatible)) {
 				pdev->dev.of_node = np;
-				domain = irq_find_host(parent->of_node);
+				domain = irq_find_host(np);
 				break;
 			}
 		}
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:52 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:52 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-6-git-send-email-lee.jones@linaro.org>

The PRCMU has its own USB, Thermal, GPIO, Modem, HSI and RTC drivers,
amongst other things. This patch allows those subordinate devices to
use it as an interrupt controller as and when they are DT enabled.

CC: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/db8500-prcmu.c       |   54 +++++++++++++++++++++++++++++---------
 include/linux/mfd/db8500-prcmu.h |    2 ++
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 7040a00..9899b3f 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -270,6 +270,8 @@ static struct {
 	struct prcmu_fw_version version;
 } fw_info;
 
+static struct irq_domain *db8500_irq_domain;
+
 /*
  * This vector maps irq numbers to the bits in the bit field used in
  * communication with the PRCMU firmware.
@@ -2583,7 +2585,7 @@ static void prcmu_irq_mask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2597,7 +2599,7 @@ static void prcmu_irq_unmask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2637,9 +2639,43 @@ static char *fw_project_name(u8 project)
 	}
 }
 
+int db8500_irq_get_virq(int irq)
+{
+	return irq_create_mapping(db8500_irq_domain, irq);
+}
+EXPORT_SYMBOL_GPL(db8500_irq_get_virq);
+
+static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
+				irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(virq, &prcmu_irq_chip,
+				handle_simple_irq);
+	set_irq_flags(virq, IRQF_VALID);
+
+	return 0;
+}
+
+static struct irq_domain_ops db8500_irq_ops = {
+        .map    = db8500_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+static int db8500_irq_init(struct device_node *np)
+{
+	db8500_irq_domain = irq_domain_add_legacy(
+		np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE,
+		0, &db8500_irq_ops, NULL);
+
+	if (!db8500_irq_domain) {
+		pr_err("Failed to create irqdomain\n");
+		return -ENOSYS;
+	}
+
+	return 0;
+}
+
 void __init db8500_prcmu_early_init(void)
 {
-	unsigned int i;
 	if (cpu_is_u8500v2()) {
 		void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
 
@@ -2683,16 +2719,6 @@ void __init db8500_prcmu_early_init(void)
 	init_completion(&mb5_transfer.work);
 
 	INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
-
-	/* Initalize irqs. */
-	for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
-		unsigned int irq;
-
-		irq = IRQ_PRCMU_BASE + i;
-		irq_set_chip_and_handler(irq, &prcmu_irq_chip,
-					 handle_simple_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
 }
 
 static void __init init_prcm_registers(void)
@@ -2999,6 +3025,8 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
 		goto no_irq_return;
 	}
 
+	db8500_irq_init(np);
+
 	for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
 		if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
 			db8500_prcmu_devs[i].platform_data = ab8500_platdata;
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index b82f6ee..38494d9 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -571,6 +571,8 @@ u32 db8500_prcmu_read(unsigned int reg);
 void db8500_prcmu_write(unsigned int reg, u32 value);
 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
 
+int db8500_irq_get_virq(int irq);
+
 #else /* !CONFIG_MFD_DB8500_PRCMU */
 
 static inline void db8500_prcmu_early_init(void) {}
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:49 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:49 +0100
Subject: [PATCH 2/8] irqdomain: Take interrupt-parent property into account if
 specified
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-3-git-send-email-lee.jones@linaro.org>

irq_find_host() currently ignores the 'interrupt-parent' property
even if it's specified in the Device Tree. Meaning that a node can
match to a domain in its hierarchy even if it doesn't belong to it.
By searching for the parent first using of_irq_find_parent() we
insist that the 'interrupt-parent' property is taken into account
ensuring a greater chance of returning the correct domain.

CC: Benjamin Herrenschmidt <benh at kernel.crashing.org>
CC: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 kernel/irq/irqdomain.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index 49a7772..db63b9b 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/topology.h>
 #include <linux/seq_file.h>
@@ -323,8 +324,14 @@ EXPORT_SYMBOL_GPL(irq_domain_add_tree);
 struct irq_domain *irq_find_host(struct device_node *node)
 {
 	struct irq_domain *h, *found = NULL;
+	struct device_node *parent_node;
 	int rc;
 
+	/* Take heed if an 'interrupt-parent' was specified. */
+	parent_node = of_irq_find_parent(node);
+	if (parent_node)
+		node = parent_node;
+
 	/* We might want to match the legacy controller last since
 	 * it might potentially be set to match all interrupts in
 	 * the absence of a device node. This isn't a problem so far
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:54 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:54 +0100
Subject: [PATCH 7/8] mfd: Use the AB8500's IRQ domain to convert hwirq to virq
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-8-git-send-email-lee.jones@linaro.org>

Before the AB8500 had its own IRQ domain, the IRQ handler would take
the fired local IRQ (hwirq) and add it to the irq_base to convert it
to an IRQ number which Linux would understand (virq). However, the
IRQ base is not always used anymore since we can make use of Linear
domains. It's better to use the AB8500 hwirq -> virq mapping helper
function to convert them instead. That's what we do here.

CC: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/ab8500-core.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 0c5b70f..71a7757 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -501,8 +501,9 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
 		do {
 			int bit = __ffs(value);
 			int line = i * 8 + bit;
+			int virq = ab8500_irq_get_virq(ab8500, line);
 
-			handle_nested_irq(ab8500->irq_base + line);
+			handle_nested_irq(virq);
 			value &= ~(1 << bit);
 
 		} while (value);
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:53:55 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:53:55 +0100
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert IRQs to
 virtual
In-Reply-To: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527635-6163-9-git-send-email-lee.jones@linaro.org>

There was a plan to place ab8500_irq_get_virq() calls in each AB8500
child device prior to requesting an IRQ, but as we're no longer using
Device Tree to collect our IRQ numbers, it's actually better to allow
the core to do this during device registration time. So the IRQ number
we pull from its resource has already been converted to a virtual IRQ.

CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
CC: linux-input at vger.kernel.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/input/misc/ab8500-ponkey.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
index f06231b..84ec691 100644
--- a/drivers/input/misc/ab8500-ponkey.c
+++ b/drivers/input/misc/ab8500-ponkey.c
@@ -74,8 +74,8 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 
 	ponkey->idev = input;
 	ponkey->ab8500 = ab8500;
-	ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
-	ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
+	ponkey->irq_dbf = irq_dbf;
+	ponkey->irq_dbr = irq_dbr;
 
 	input->name = "AB8500 POn(PowerOn) Key";
 	input->dev.parent = &pdev->dev;
-- 
1.7.9.5



From u.kleine-koenig at pengutronix.de  Thu Aug  9 11:57:15 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu,  9 Aug 2012 17:57:15 +0200
Subject: [PATCH] ARM: imx/iomux-v3: allow pad_list to be const
Message-ID: <1344527835-32567-1-git-send-email-u.kleine-koenig@pengutronix.de>

Also fix all machine files to make use of it and while at it also make
the pad lists __init_const.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Hello,

well, iomux-v3 is dying so I don't know how welcome this patch is.

Best regards
Uwe

 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c |    2 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c |    2 +-
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c |    2 +-
 arch/arm/mach-imx/mach-cpuimx35.c              |    2 +-
 arch/arm/mach-imx/mach-cpuimx51sd.c            |    2 +-
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c       |    2 +-
 arch/arm/mach-imx/mach-mx25_3ds.c              |    2 +-
 arch/arm/mach-imx/mach-mx35_3ds.c              |    2 +-
 arch/arm/mach-imx/mach-mx50_rdp.c              |    2 +-
 arch/arm/mach-imx/mach-mx51_3ds.c              |    2 +-
 arch/arm/mach-imx/mach-mx51_babbage.c          |    2 +-
 arch/arm/mach-imx/mach-mx51_efikamx.c          |    2 +-
 arch/arm/mach-imx/mach-mx51_efikasb.c          |    2 +-
 arch/arm/mach-imx/mach-mx53_ard.c              |    2 +-
 arch/arm/mach-imx/mach-mx53_evk.c              |    2 +-
 arch/arm/mach-imx/mach-mx53_loco.c             |    2 +-
 arch/arm/mach-imx/mach-mx53_smd.c              |    2 +-
 arch/arm/mach-imx/mach-pcm043.c                |    2 +-
 arch/arm/mach-imx/mach-vpr200.c                |    2 +-
 arch/arm/mach-imx/mx51_efika.c                 |    2 +-
 arch/arm/plat-mxc/include/mach/iomux-v3.h      |    3 ++-
 arch/arm/plat-mxc/iomux-v3.c                   |    5 +++--
 22 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index dfd2da8..9ca351d 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -35,7 +35,7 @@
 
 #include "devices-imx25.h"
 
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
 	/* LCD */
 	MX25_PAD_LD0__LD0,
 	MX25_PAD_LD1__LD1,
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 6e9dd12..0a37e17 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -101,7 +101,7 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = {
 	.num_modes	= ARRAY_SIZE(fb_modedb),
 };
 
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
 	/* LCD */
 	MX35_PAD_LD0__IPU_DISPB_DAT_0,
 	MX35_PAD_LD1__IPU_DISPB_DAT_1,
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index 96a24b7..7d77038 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -42,7 +42,7 @@
 
 #include "devices-imx51.h"
 
-static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
+static const iomux_v3_cfg_t eukrea_mbimxsd51_pads[] __initconst = {
 	/* LED */
 	MX51_PAD_NANDF_D10__GPIO3_30,
 	/* SWITCH */
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index d49b0ec..13e31a5 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -75,7 +75,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
 	},
 };
 
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
+static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
 	/* UART1 */
 	MX35_PAD_CTS1__UART1_CTS,
 	MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index b87cc49..3b893b4 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -63,7 +63,7 @@
 #define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
 #define	MX51_USB_PLL_DIV_24_MHZ		0x02
 
-static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
+static const iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] __initconst = {
 	/* UART1 */
 	MX51_PAD_UART1_RXD__UART1_RXD,
 	MX51_PAD_UART1_TXD__UART1_TXD,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 017bbb70..2e93ba1 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -44,7 +44,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
+static const iomux_v3_cfg_t eukrea_cpuimx25_pads[] __initconst = {
 	/* FEC - RMII */
 	MX25_PAD_FEC_MDC__FEC_MDC,
 	MX25_PAD_FEC_MDIO__FEC_MDIO,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index ce247fd..5fb4592 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -49,7 +49,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static iomux_v3_cfg_t mx25pdk_pads[] = {
+static const iomux_v3_cfg_t mx25pdk_pads[] __initconst = {
 	MX25_PAD_FEC_MDC__FEC_MDC,
 	MX25_PAD_FEC_MDIO__FEC_MDIO,
 	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 504983c..ef175fb 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -165,7 +165,7 @@ static struct platform_device *devices[] __initdata = {
 	&mx35pdk_flash,
 };
 
-static iomux_v3_cfg_t mx35pdk_pads[] = {
+static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
 	/* UART1 */
 	MX35_PAD_CTS1__UART1_CTS,
 	MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
index 42b66e8..7910761 100644
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ b/arch/arm/mach-imx/mach-mx50_rdp.c
@@ -39,7 +39,7 @@
 #define FEC_EN		IMX_GPIO_NR(6, 23)
 #define FEC_RESET_B	IMX_GPIO_NR(4, 12)
 
-static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
+static const iomux_v3_cfg_t mx50_rdp_pads[] __initconst = {
 	/* SD1 */
 	MX50_PAD_ECSPI2_SS0__GPIO_4_19,
 	MX50_PAD_EIM_CRE__GPIO_1_27,
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 9ee84a4..fd972a9 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -28,7 +28,7 @@
 
 #define MX51_3DS_ECSPI2_CS	(GPIO_PORTC + 28)
 
-static iomux_v3_cfg_t mx51_3ds_pads[] = {
+static const iomux_v3_cfg_t mx51_3ds_pads[] __initconst = {
 	/* UART1 */
 	MX51_PAD_UART1_RXD__UART1_RXD,
 	MX51_PAD_UART1_TXD__UART1_TXD,
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 7b31cbd..7bc9731 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -65,7 +65,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = {
 	.nbuttons	= ARRAY_SIZE(babbage_buttons),
 };
 
-static iomux_v3_cfg_t mx51babbage_pads[] = {
+static const iomux_v3_cfg_t mx51babbage_pads[] __initconst = {
 	/* UART1 */
 	MX51_PAD_UART1_RXD__UART1_RXD,
 	MX51_PAD_UART1_TXD__UART1_TXD,
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 8d09c01..b792086 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -65,7 +65,7 @@
 #define MX51_PAD_PCBID2	IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
 #define MX51_PAD_PWRKEY	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
 
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
+static const iomux_v3_cfg_t mx51efikamx_pads[] __initconst = {
 	/* board id */
 	MX51_PAD_PCBID0,
 	MX51_PAD_PCBID1,
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index fdbd181..1285920 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -57,7 +57,7 @@
 #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
 #define MX51_PAD_SD1_CD	IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
+static const iomux_v3_cfg_t mx51efikasb_pads[] __initconst = {
 	/* USB HOST2 */
 	MX51_PAD_EIM_D16__USBH2_DATA0,
 	MX51_PAD_EIM_D17__USBH2_DATA1,
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 6c28e65..acbc2f5 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -46,7 +46,7 @@
 #define ARD_PROG			IMX_GPIO_NR(5, 12)
 #define ARD_VOLUMEUP		IMX_GPIO_NR(5, 13)
 
-static iomux_v3_cfg_t mx53_ard_pads[] = {
+static const iomux_v3_cfg_t mx53_ard_pads[] __initconst = {
 	/* UART1 */
 	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
 	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
index 09fe219..e49d55f 100644
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ b/arch/arm/mach-imx/mach-mx53_evk.c
@@ -39,7 +39,7 @@
 
 #include "devices-imx53.h"
 
-static iomux_v3_cfg_t mx53_evk_pads[] = {
+static const iomux_v3_cfg_t mx53_evk_pads[] __initconst = {
 	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
 	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
 
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
index 8abe23c..367aeb5 100644
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ b/arch/arm/mach-imx/mach-mx53_loco.c
@@ -44,7 +44,7 @@
 #define LOCO_SD1_CD			IMX_GPIO_NR(3, 13)
 #define LOCO_ACCEL_EN			IMX_GPIO_NR(6, 14)
 
-static iomux_v3_cfg_t mx53_loco_pads[] = {
+static const iomux_v3_cfg_t mx53_loco_pads[] __initconst = {
 	/* FEC */
 	MX53_PAD_FEC_MDC__FEC_MDC,
 	MX53_PAD_FEC_MDIO__FEC_MDIO,
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
index b15d6a6..21ee713 100644
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ b/arch/arm/mach-imx/mach-mx53_smd.c
@@ -36,7 +36,7 @@
 #define SMD_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
 #define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
 
-static iomux_v3_cfg_t mx53_smd_pads[] = {
+static const iomux_v3_cfg_t mx53_smd_pads[] __initconst = {
 	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
 	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
 
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index e4bd438..618cea9 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -129,7 +129,7 @@ static struct platform_device *devices[] __initdata = {
 	&pcm043_flash,
 };
 
-static iomux_v3_cfg_t pcm043_pads[] = {
+static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
 	/* UART1 */
 	MX35_PAD_CTS1__UART1_CTS,
 	MX35_PAD_RTS1__UART1_RTS,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 39eb796..26e1674 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -161,7 +161,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
 	}
 };
 
-static iomux_v3_cfg_t vpr200_pads[] = {
+static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
 	/* UART1 */
 	MX35_PAD_TXD1__UART1_TXD_MUX,
 	MX35_PAD_RXD1__UART1_RXD_MUX,
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
index ee870c4..25e3417 100644
--- a/arch/arm/mach-imx/mx51_efika.c
+++ b/arch/arm/mach-imx/mx51_efika.c
@@ -55,7 +55,7 @@
 
 #define EFIKAMX_PMIC		IMX_GPIO_NR(1, 6)
 
-static iomux_v3_cfg_t mx51efika_pads[] = {
+static const iomux_v3_cfg_t mx51efika_pads[] __initconst = {
 	/* UART1 */
 	MX51_PAD_UART1_RXD__UART1_RXD,
 	MX51_PAD_UART1_TXD__UART1_TXD,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 2fa3b54..5f4bbf1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -131,7 +131,8 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
  * setups mutliple pads
  * convenient way to call the above function with tables
  */
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+		unsigned count);
 
 /*
  * Initialise the iomux controller
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 99a9cdb..1258ebf 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -56,9 +56,10 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
 
-int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
+		unsigned count)
 {
-	iomux_v3_cfg_t *p = pad_list;
+	const iomux_v3_cfg_t *p = pad_list;
 	int i;
 	int ret;
 
-- 
1.7.10.4



From lee.jones at linaro.org  Thu Aug  9 11:57:06 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:57:06 +0100
Subject: [PATCH 1/1] ARM: ux500: Match Power-On-Key MFD and DTS compatible
 strings
Message-ID: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>

The compatible string found in the Power-On-Key's MFD cell matches
the device name provided in the driver. Keeping this naming convention
seems like a good idea, so we're changing the one found in the DTS
file to match.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 5106662..7d84f46 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -374,7 +374,7 @@
 				};
 
 				ab8500-ponkey {
-					compatible = "stericsson,ab8500-ponkey";
+					compatible = "stericsson,ab8500-poweron-key";
 					interrupts = <6 0x4
 						      7 0x4>;
 					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:57:07 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:57:07 +0100
Subject: [PATCH 1/1] ARM: ux500: Remove unused snowball_of_platform_devs struct
In-Reply-To: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527828-6283-2-git-send-email-lee.jones@linaro.org>

This was left over during a recent clean-up which removed Device Tree
helper structs. There is no longer a requirement for it, so we can just
remove it.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index a93b147..de10f8f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -725,11 +725,6 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-	&snowball_led_dev,
-	&snowball_key_dev,
-};
-
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	/* Requires call-back bindings. */
 	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug  9 11:57:08 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu,  9 Aug 2012 16:57:08 +0100
Subject: [PATCH 1/1] drivers/rtc/rtc-ab8500.c: Revoke Device Tree enablement
In-Reply-To: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1344527828-6283-3-git-send-email-lee.jones@linaro.org>

All AB8500 devices are now registered via MFD core, so Device Tree
capability is no longer required for probing. Here we pull the DT
match table to ensure we're no longer probed during Device Tree
start-up.

CC: Alessandro Zummo <a.zummo at towertech.it>
CC: rtc-linux at googlegroups.com
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/rtc/rtc-ab8500.c |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/rtc/rtc-ab8500.c b/drivers/rtc/rtc-ab8500.c
index bf3c2f6..2e5970f 100644
--- a/drivers/rtc/rtc-ab8500.c
+++ b/drivers/rtc/rtc-ab8500.c
@@ -462,16 +462,10 @@ static int __devexit ab8500_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id ab8500_rtc_match[] = {
-	{ .compatible = "stericsson,ab8500-rtc", },
-	{}
-};
-
 static struct platform_driver ab8500_rtc_driver = {
 	.driver = {
 		.name = "ab8500-rtc",
 		.owner = THIS_MODULE,
-		.of_match_table = ab8500_rtc_match,
 	},
 	.probe	= ab8500_rtc_probe,
 	.remove = __devexit_p(ab8500_rtc_remove),
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Thu Aug  9 12:48:44 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu,  9 Aug 2012 18:48:44 +0200
Subject: LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0:
 add support for Aurora L2 cache ctrl)
In-Reply-To: <20120808151946.GE4579@mudshark.cambridge.arm.com>
References: <20120808151946.GE4579@mudshark.cambridge.arm.com>
Message-ID: <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>

Hi Will,

You will find an updated version of this patch with LPAE support. I've
tested with and without LPAE selected.

Now I get some warning during compilation: "initialization from
incompatible pointer type [enabled by default]"

It is because the outer_cache_fns struct still embed functions with
unsigned long for address instead of phys_addr_t. You are aware of
it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
use phys_addr_t instead of unsigned long in outercache functions".

So a first step would be to update the definitions in struct
outer_cache_fns and also in the files using this prototype, I found
only 4 files:

git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
arch/arm/mm/cache-feroceon-l2.c:
arch/arm/mm/cache-l2x0.c:
arch/arm/mm/cache-tauros2.c:
arch/arm/mm/cache-xsc3l2.c:

But it is not enough we also fixed the call to theses functions:
git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
arch/arm/include/asm/outercache.h
arch/arm/kernel/smp.c
arch/arm/kernel/suspend.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-highbank/highbank.c
arch/arm/mach-msm/platsmp.c
arch/arm/mach-omap2/omap-secure.c
arch/arm/mach-ux500/platsmp.c
arch/arm/mm/dma-mapping.c
arch/arm/mm/fault-armv.c
arch/arm/plat-versatile/platsmp.c

Most of them use __pa or directly __virt_to_phys, so once the patch
"[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
conversion" will be merged the correct type will be used.

Finally the last file which need some change will be
arch/arm/mm/dma-mapping.c.

Does it sound correct?

If it does, then I can prepare a patch for it.

Regards,

Gregory



From dave.martin at linaro.org  Thu Aug  9 12:50:26 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 9 Aug 2012 17:50:26 +0100
Subject: [PATCH v2 02/23] xen/arm: hypercalls
In-Reply-To: <alpine.DEB.2.02.1208091046330.21096@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-2-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120808124111.GB2134@linaro.org>
 <alpine.DEB.2.02.1208091046330.21096@kaball.uk.xensource.com>
Message-ID: <20120809165026.GC17588@linaro.org>

On Thu, Aug 09, 2012 at 04:37:24PM +0100, Stefano Stabellini wrote:
> On Wed, 8 Aug 2012, Dave Martin wrote:
> > On Mon, Aug 06, 2012 at 03:27:05PM +0100, Stefano Stabellini wrote:
> > > Use r12 to pass the hypercall number to the hypervisor.
> > > 
> > > We need a register to pass the hypercall number because we might not
> > > know it at compile time and HVC only takes an immediate argument.
> > > 
> > > Among the available registers r12 seems to be the best choice because it
> > > is defined as "intra-procedure call scratch register".
> > > 
> > > Use the ISS to pass an hypervisor specific tag.
> > > 
> > > Changes in v2:
> > > - define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
> > > at the moment is unused;
> > > - use ldm instead of pop;
> > > - fix up comments.
> > > 
> > > Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> > > ---
> > >  arch/arm/include/asm/xen/hypercall.h |   50 ++++++++++++++++
> > >  arch/arm/xen/Makefile                |    2 +-
> > >  arch/arm/xen/hypercall.S             |  106 ++++++++++++++++++++++++++++++++++
> > >  3 files changed, 157 insertions(+), 1 deletions(-)
> > >  create mode 100644 arch/arm/include/asm/xen/hypercall.h
> > >  create mode 100644 arch/arm/xen/hypercall.S
> > 
> > [...]
> > 
> > > diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
> > > new file mode 100644
> > > index 0000000..074f5ed
> > > --- /dev/null
> > > +++ b/arch/arm/xen/hypercall.S
> > > @@ -0,0 +1,106 @@
> > > +/******************************************************************************
> > > + * hypercall.S
> > > + *
> > > + * Xen hypercall wrappers
> > > + *
> > > + * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License version 2
> > > + * as published by the Free Software Foundation; or, when distributed
> > > + * separately from the Linux kernel or incorporated into other
> > > + * software packages, subject to the following license:
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > > + * of this source file (the "Software"), to deal in the Software without
> > > + * restriction, including without limitation the rights to use, copy, modify,
> > > + * merge, publish, distribute, sublicense, and/or sell copies of the Software,
> > > + * and to permit persons to whom the Software is furnished to do so, subject to
> > > + * the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice shall be included in
> > > + * all copies or substantial portions of the Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> > > + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + */
> > > +
> > > +/*
> > > + * The Xen hypercall calling convention is very similar to the ARM
> > > + * procedure calling convention: the first paramter is passed in r0, the
> > > + * second in r1, the third in r2 and the fourth in r3. Considering that
> > > + * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
> > > + * in r4, differently from the procedure calling convention of using the
> > > + * stack for that case.
> > > + *
> > > + * The hypercall number is passed in r12.
> > > + *
> > > + * The return value is in r0.
> > > + *
> > > + * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
> > > + * hypercall tag.
> > > + */
> > > +
> > > +#include <linux/linkage.h>
> > > +#include <asm/assembler.h>
> > > +#include <xen/interface/xen.h>
> > > +
> > > +
> > > +/* HVC 0xEA1 */
> > > +#ifdef CONFIG_THUMB2_KERNEL
> > > +#define xen_hvc .word 0xf7e08ea1
> > > +#else
> > > +#define xen_hvc .word 0xe140ea71
> > > +#endif
> > 
> > Consider using my opcode injection helpers patch for this (see
> > separate repost: [PATCH v2 REPOST 0/4] ARM: opcodes: Facilitate custom
> > opcode injection), assuming that nobody objects to it.  This should mean
> > that the right opcodes get generated when building a kernel for a big-
> > endian target for example.
> > 
> > I believe the __HVC(imm) macro which I put in <asm/opcodes-virt.h> as an
> > example should do what you need in this case.
> 
> Sure I can do that. Maybe I'll add another patch at the end of my series
> to replace xen_hvc with __HVC(0xEA1), so that it remains independent
> from your series.
> I have learned through experience that avoiding cross patch series
> dependencies help to reduce the amount of headaches during merge windows
> :)

I agree.  I'll let you know when my patch gets merged -- in the meantime,
it makes sense for you to keep your existing code.

> 
> 
> > > +
> > > +#define HYPERCALL_SIMPLE(hypercall)		\
> > > +ENTRY(HYPERVISOR_##hypercall)			\
> > > +	mov r12, #__HYPERVISOR_##hypercall;	\
> > > +	xen_hvc;							\
> > > +	mov pc, lr;							\
> > > +ENDPROC(HYPERVISOR_##hypercall)
> > > +
> > > +#define HYPERCALL0 HYPERCALL_SIMPLE
> > > +#define HYPERCALL1 HYPERCALL_SIMPLE
> > > +#define HYPERCALL2 HYPERCALL_SIMPLE
> > > +#define HYPERCALL3 HYPERCALL_SIMPLE
> > > +#define HYPERCALL4 HYPERCALL_SIMPLE
> > > +
> > > +#define HYPERCALL5(hypercall)			\
> > > +ENTRY(HYPERVISOR_##hypercall)			\
> > > +	stmdb sp!, {r4}						\
> > > +	ldr r4, [sp, #4]					\
> > > +	mov r12, #__HYPERVISOR_##hypercall;	\
> > > +	xen_hvc								\
> > > +	ldm sp!, {r4}						\
> > > +	mov pc, lr							\
> > > +ENDPROC(HYPERVISOR_##hypercall)
> > > +
> > > +                .text
> > > +
> > > +HYPERCALL2(xen_version);
> > > +HYPERCALL3(console_io);
> > > +HYPERCALL3(grant_table_op);
> > > +HYPERCALL2(sched_op);
> > > +HYPERCALL2(event_channel_op);
> > > +HYPERCALL2(hvm_op);
> > > +HYPERCALL2(memory_op);
> > > +HYPERCALL2(physdev_op);
> > > +
> > > +ENTRY(privcmd_call)
> > > +	stmdb sp!, {r4}
> > > +	mov r12, r0
> > > +	mov r0, r1
> > > +	mov r1, r2
> > > +	mov r2, r3
> > > +	ldr r3, [sp, #8]
> > > +	ldr r4, [sp, #4]
> > > +	xen_hvc
> > > +	ldm sp!, {r4}
> > > +	mov pc, lr
> > 
> > Note that the preferred entry/exit sequences in such cases are:
> > 
> > 	stmfd	sp!, {r4,lr}
> > 	...
> > 	ldmfd	sp!, {r4,pc}
> > 
> > ...but it works either way.  I would bother to change it unless you
> > have other changes to make too.
> 
> Wouldn't this needlessly save and restore one more register (lr) to the
> stack?
> I would try to keep the hypercall wrappers as small as possible...

Argh, ignore me -- I was hallucinating for some reason that we actually
needed to save lr, but we don't.

Using the stmfd/ldmfd mnemonics might still be nicer than stmdb/ldm, since
the fd suffix makes the stack semantics more obvious, and the code
looks more symmetrical.  This was the conventional way to write these
mnemonics before the "push" and "pop" mnemonics existed.

That's purely cosmetic, though.

Cheers
---Dave


From dave.martin at linaro.org  Thu Aug  9 12:51:45 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 9 Aug 2012 17:51:45 +0100
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <CAKGA1bkzOEiMm8Uo=AiXdquhKHFhjgHE0qXaztcxRvMDSjkfaQ@mail.gmail.com>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
 <20120809102414.GA17588@linaro.org>
 <CAKGA1bniQK9DbZudrHk1mA7FyDZkQzBJbWNUFTFW3pc_2A2x4g@mail.gmail.com>
 <20120809145005.GB17588@linaro.org>
 <CAKGA1bkzOEiMm8Uo=AiXdquhKHFhjgHE0qXaztcxRvMDSjkfaQ@mail.gmail.com>
Message-ID: <20120809165145.GD17588@linaro.org>

On Thu, Aug 09, 2012 at 11:05:47AM -0500, Matt Sealey wrote:
> On Thu, Aug 9, 2012 at 9:50 AM, Dave Martin <dave.martin at linaro.org> wrote:
> > On Thu, Aug 09, 2012 at 09:32:59AM -0500, Matt Sealey wrote:
> >> Matt Sealey <matt at genesi-usa.com>
> >> Product Development Analyst, Genesi USA, Inc.
> >>
> >>
> >> On Thu, Aug 9, 2012 at 5:24 AM, Dave Martin <dave.martin at linaro.org> wrote:
> >> > On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:
> >> >
> >> > [...]
> >> >
> >> >> I'm going to do a trapse through and find where Russell nacked Dave's
> >> >> thumb-aware
> >> >> rewrite.. would you mind if you have any of these boards seeing if it
> >> >> really DOES
> >> >
> >> > There was no NAK because I didn't get as far as posting the patch,
> >>
> >> http://lists.arm.linux.org.uk/lurker/message/20111202.133911.393b6e28.en.html
> >>
> >> You did, twice :)
> >
> > Well, I meant that I had not posted it as a stand-alone patch for
> > inclusion; I only posted it when commenting on other threads.
> >
> >> > mostly because of the doubt about whether this code is ever relevant
> >> > on Thumb2-capable hardware.
> >>
> >> It's not, but it does break the build, and without disabling phyCORE boards for
> >> Thumb2 it will always break the build..
> >
> > If you want me to push it, let me know.  I don't think this should get
> > merged without some Tested-bys for hardware where the FIQ stuff actually
> > gets used.
> 
> Please, then all the Tested-by's should flood in, right? :)

Do you have any suggestions for who I should CC to speed things up?

Cheers
---Dave


From nico at fluxnic.net  Thu Aug  9 12:57:33 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 09 Aug 2012 12:57:33 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
Message-ID: <alpine.LFD.2.02.1208091243080.5231@xanadu.home>

On Thu, 9 Aug 2012, Nicolas Pitre wrote:

> On Thu, 9 Aug 2012, Will Deacon wrote:
> 
> > I think we could actually fix this entirely in mutex-xchg.h by doing
> > something in fastpath_lock similar to what we do for trylock:
> > 
> > 
> > diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> > index 580a6d3..c082e99 100644
> > --- a/include/asm-generic/mutex-xchg.h
> > +++ b/include/asm-generic/mutex-xchg.h
> > @@ -25,8 +25,19 @@
> >  static inline void
> >  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
> >  {
> > -       if (unlikely(atomic_xchg(count, 0) != 1))
> > -               fail_fn(count);
> > +       int prev = atomic_xchg(count, 0);
> > +
> > +       if (unlikely(prev != 1)) {
> > +               if (prev < 0)
> > +                       /*
> > +                        * The lock was contended, so we need to restore
> > +                        * its original state to ensure that any waiting
> > +                        * tasks are woken up by the unlock slow path.
> > +                        */
> > +                       prev = atomic_xchg(count, prev);
> > +               if (prev != 1)
> > +                       fail_fn(count);
> > +       }
> >  }
> > 
> > What do you reckon?
> 
> Yes, that looks fine.  I'd remove that if (prev < 0) entirely though.  
> We'll just swap a 0 for a 0 if the count wasn't < 0, or a 0 for a 1 if 
> the mutex just got unlocked which is also fine.  This is especially 
> beneficial when a native xchg processor instruction is used.

In fact, this suggestion isn't entirely correct either. The inner xchg 
in this case should be -1 and not 'count'.  If 'count' is 0 and the 
mutex becomes contended in the small window between the two xchg's then 
the contention mark would be lost again.

In other words, I think this should look like this:

diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 580a6d35c7..44a66c99c8 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -25,8 +25,11 @@
 static inline void
 __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
-	if (unlikely(atomic_xchg(count, 0) != 1))
-		fail_fn(count);
+	if (unlikely(atomic_xchg(count, 0) != 1)) {
+		/* Mark lock contention explicitly */
+		if (likely(atomic_xchg(count, -1) != 1))
+			fail_fn(count);
+	}
 }
 
 /**


Nicolas


From konrad.wilk at oracle.com  Thu Aug  9 12:54:24 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Thu, 9 Aug 2012 12:54:24 -0400
Subject: [PATCH v2 10/23] xen/arm: compile and run xenbus
In-Reply-To: <alpine.DEB.2.02.1208081836050.21096@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208061428060.4645@kaball.uk.xensource.com>
 <1344263246-28036-10-git-send-email-stefano.stabellini@eu.citrix.com>
 <20120807182157.GN15053@phenom.dumpdata.com>
 <50216228.7010407@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081743430.21096@kaball.uk.xensource.com>
 <50229B70.3090507@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081805520.21096@kaball.uk.xensource.com>
 <5022A303.709@tycho.nsa.gov>
 <alpine.DEB.2.02.1208081836050.21096@kaball.uk.xensource.com>
Message-ID: <20120809165424.GA7220@phenom.dumpdata.com>

> > Right, the original patch didn't break anything with PV domains. The case
> > it doesn't handle is an HVM initial domain with an already-running
> > Xenstore domain; I think this applies both to ARM and hybrid/PVH on x86.
> > In that case, usage would be set to LOCAL instead of HVM.
> 
> 
> Right, however if I am not mistaken there is no such thing as an HVM
> dom0 right now on x86 and hybrid/PVH is probably going to return true on
> xen_pv_domain() and false on xen_hvm_domain().

The other way around.  HVM = true, PV = false.

Mukesh, correct me if I am wrong pls.
> 
> In the ARM case, given that we don't have a start_info page, we would
> need another way to figure out whether a xenstore stub domain is already
> running, so I think we can just postpone the solution of that problem
> for now.


From matt at genesi-usa.com  Thu Aug  9 12:05:47 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 9 Aug 2012 11:05:47 -0500
Subject: [PATCH 1/2] ARM: build ssi-fiq.S in ARM mode to prevent
 CONFIG_THUMB2_KERNEL build breakage
In-Reply-To: <20120809145005.GB17588@linaro.org>
References: <1344379514-30076-1-git-send-email-matt@genesi-usa.com>
 <1344379514-30076-2-git-send-email-matt@genesi-usa.com>
 <20120808065502.GI1451@pengutronix.de>
 <CAKGA1bmUuSZuWDM4QPTxmNR0+=uQ1RbFhw4u-sb9KaSPYwQiVw@mail.gmail.com>
 <20120809102414.GA17588@linaro.org>
 <CAKGA1bniQK9DbZudrHk1mA7FyDZkQzBJbWNUFTFW3pc_2A2x4g@mail.gmail.com>
 <20120809145005.GB17588@linaro.org>
Message-ID: <CAKGA1bkzOEiMm8Uo=AiXdquhKHFhjgHE0qXaztcxRvMDSjkfaQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 9:50 AM, Dave Martin <dave.martin at linaro.org> wrote:
> On Thu, Aug 09, 2012 at 09:32:59AM -0500, Matt Sealey wrote:
>> Matt Sealey <matt at genesi-usa.com>
>> Product Development Analyst, Genesi USA, Inc.
>>
>>
>> On Thu, Aug 9, 2012 at 5:24 AM, Dave Martin <dave.martin at linaro.org> wrote:
>> > On Wed, Aug 08, 2012 at 12:32:39PM -0500, Matt Sealey wrote:
>> >
>> > [...]
>> >
>> >> I'm going to do a trapse through and find where Russell nacked Dave's
>> >> thumb-aware
>> >> rewrite.. would you mind if you have any of these boards seeing if it
>> >> really DOES
>> >
>> > There was no NAK because I didn't get as far as posting the patch,
>>
>> http://lists.arm.linux.org.uk/lurker/message/20111202.133911.393b6e28.en.html
>>
>> You did, twice :)
>
> Well, I meant that I had not posted it as a stand-alone patch for
> inclusion; I only posted it when commenting on other threads.
>
>> > mostly because of the doubt about whether this code is ever relevant
>> > on Thumb2-capable hardware.
>>
>> It's not, but it does break the build, and without disabling phyCORE boards for
>> Thumb2 it will always break the build..
>
> If you want me to push it, let me know.  I don't think this should get
> merged without some Tested-bys for hardware where the FIQ stuff actually
> gets used.

Please, then all the Tested-by's should flood in, right? :)

> The older post would be the one to use, since that at least got a
> reasonable level of build testing.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From nico at fluxnic.net  Thu Aug  9 12:17:30 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 09 Aug 2012 12:17:30 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120809144953.GC18486@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208091201380.5231@xanadu.home>

On Thu, 9 Aug 2012, Will Deacon wrote:

> I think we could actually fix this entirely in mutex-xchg.h by doing
> something in fastpath_lock similar to what we do for trylock:
> 
> 
> diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> index 580a6d3..c082e99 100644
> --- a/include/asm-generic/mutex-xchg.h
> +++ b/include/asm-generic/mutex-xchg.h
> @@ -25,8 +25,19 @@
>  static inline void
>  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
>  {
> -       if (unlikely(atomic_xchg(count, 0) != 1))
> -               fail_fn(count);
> +       int prev = atomic_xchg(count, 0);
> +
> +       if (unlikely(prev != 1)) {
> +               if (prev < 0)
> +                       /*
> +                        * The lock was contended, so we need to restore
> +                        * its original state to ensure that any waiting
> +                        * tasks are woken up by the unlock slow path.
> +                        */
> +                       prev = atomic_xchg(count, prev);
> +               if (prev != 1)
> +                       fail_fn(count);
> +       }
>  }
> 
> What do you reckon?

Yes, that looks fine.  I'd remove that if (prev < 0) entirely though.  
We'll just swap a 0 for a 0 if the count wasn't < 0, or a 0 for a 1 if 
the mutex just got unlocked which is also fine.  This is especially 
beneficial when a native xchg processor instruction is used.

> > Of course that might tilt the balance towards using mutex-dec.h on ARM 
> > v6 and above instead of mutex-xchg.h.  But that is an orthogonal issue, 
> > and that doesn't remove the need for fixing the xchg based case for 
> > correctness.
> 
> I'll do some hackbench runs against mutex-dec once we've decided on the final
> xchg code. If it's faster, I'll submit a patch for ARM.

I don't think it would be faster.  It is just potentially more fair.


Nicolas


From robherring2 at gmail.com  Thu Aug  9 12:20:54 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 09 Aug 2012 11:20:54 -0500
Subject: [PATCH 1/8] of/irq: Create stub for of_irq_find_parent when
 !CONFIG_OF
In-Reply-To: <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
Message-ID: <5023E366.9010603@gmail.com>

On 08/09/2012 10:53 AM, Lee Jones wrote:
> of_irq_find_parent is a handy function to use outside the confines of
> the Open Firmware subsystem. One such use-case is when the IRQ Domain
> wishes to find an IRQ domain for a given device node. Currently it can
> not take any notice of the 'interrupt-parent' property. Instead it
> just uses the first IRQ controller as it climbs the Device Tree. If
> we were to use this as a precursor the resultant controller is more
> likely to be correct.

Where are you using this? I don't have all the patches in the series.

Rob

> 
> CC: Rob Herring <rob.herring at calxeda.com>
> CC: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  include/linux/of_irq.h |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
> index 1717cd9..b8e2411 100644
> --- a/include/linux/of_irq.h
> +++ b/include/linux/of_irq.h
> @@ -83,6 +83,11 @@ static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
>  {
>  	return 0;
>  }
> +
> +static inline void *of_irq_find_parent(struct device_node *child)
> +{
> +	return NULL;
> +}
>  #endif /* !CONFIG_OF */
>  
>  #endif /* __OF_IRQ_H */
> 



From linux at arm.linux.org.uk  Thu Aug  9 12:31:05 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 17:31:05 +0100
Subject: The curse of EPROBE_DEFER
Message-ID: <20120809163105.GU18957@n2100.arm.linux.org.uk>

Okay, so we have this wonderful new feature called EPROBE_DEFER.  I
had in the back of my mind while at the meetup in Prague where this
was discussed that it would cause problems... of the type I'm now
having, which is:

soc-audio soc-audio: ASoC machine CuBox-spdif should use snd_soc_register_card()
soc-audio soc-audio: Failed to register card
platform soc-audio: Driver soc-audio requests probe deferral

repeated many times in the kernel messages, but there's _zero_ clue
as to why, and unless I enable debugging in sound/soc through a kernel
rebuild, there's little chance of finding out.

This is idiotic, and fragile, and completely mad.  If we're going to
have EPROBE_DEFER at least have the curtesy to your users to say *why*
you're failing the probe, and *not* at the (by default) invisible debug
level.  I mean, saying that the probe failed but not saying *why* is
utterly stupid.


From u.kleine-koenig at pengutronix.de  Thu Aug  9 12:27:42 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 9 Aug 2012 18:27:42 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120809162742.GG25520@pengutronix.de>

Hello,

> +  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
argh, I forgot to fix that (ie. s/53/35/). I won't resend just for that.
Linus, assuming you intend to take the patch now, can you fix it up
while commiting please?

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From broonie at opensource.wolfsonmicro.com  Thu Aug  9 13:36:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 18:36:28 +0100
Subject: The curse of EPROBE_DEFER
In-Reply-To: <20120809163105.GU18957@n2100.arm.linux.org.uk>
References: <20120809163105.GU18957@n2100.arm.linux.org.uk>
Message-ID: <20120809173628.GY24328@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 05:31:05PM +0100, Russell King - ARM Linux wrote:

> Okay, so we have this wonderful new feature called EPROBE_DEFER.  I
> had in the back of my mind while at the meetup in Prague where this
> was discussed that it would cause problems... of the type I'm now
> having, which is:

Well, it's not really an issue in probe deferral per se - it's an issue
in ASoC and something we have to watch out for in other users.

> soc-audio soc-audio: Failed to register card

This is bitrot, should be killed.  It was a bit more useful with our
custom deferred probe but since we routinely fail it's completely
useless now, as you say we need more specific logging.

> repeated many times in the kernel messages, but there's _zero_ clue
> as to why, and unless I enable debugging in sound/soc through a kernel
> rebuild, there's little chance of finding out.

There's also the option of doing a contrast and compare between the card
definition and the lists of registered things in debugfs but that's
obviously not something we should expect the general audience to work
with.

> This is idiotic, and fragile, and completely mad.  If we're going to
> have EPROBE_DEFER at least have the curtesy to your users to say *why*
> you're failing the probe, and *not* at the (by default) invisible debug
> level.  I mean, saying that the probe failed but not saying *why* is
> utterly stupid.

The reason that the log messages are debug level is that back when
nobody though probe deferral would ever be useful people complained
about the log spam from probe deferral and didn't want to know that
anyone might need it.  Obviously this no longer applies - not only do we
now have probe deferral in the core but it's chatty anyway so we may as
well add some diagnostic information on top of it.

Anyway, thanks for noticing this.  I've just upgraded the severity of
all the logs from probe deferral to dev_err(), a patch should show up on
the list and in -next tomorrow or the day after.


From will.deacon at arm.com  Thu Aug  9 13:50:20 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 9 Aug 2012 18:50:20 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
Message-ID: <20120809175019.GE18486@mudshark.cambridge.arm.com>

On Thu, Aug 09, 2012 at 05:57:33PM +0100, Nicolas Pitre wrote:
> On Thu, 9 Aug 2012, Nicolas Pitre wrote:
> > Yes, that looks fine.  I'd remove that if (prev < 0) entirely though.  
> > We'll just swap a 0 for a 0 if the count wasn't < 0, or a 0 for a 1 if 
> > the mutex just got unlocked which is also fine.  This is especially 
> > beneficial when a native xchg processor instruction is used.
> 
> In fact, this suggestion isn't entirely correct either. The inner xchg 
> in this case should be -1 and not 'count'.  If 'count' is 0 and the 
> mutex becomes contended in the small window between the two xchg's then 
> the contention mark would be lost again.
> 
> In other words, I think this should look like this:
> 
> diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> index 580a6d35c7..44a66c99c8 100644
> --- a/include/asm-generic/mutex-xchg.h
> +++ b/include/asm-generic/mutex-xchg.h
> @@ -25,8 +25,11 @@
>  static inline void
>  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
>  {
> -	if (unlikely(atomic_xchg(count, 0) != 1))
> -		fail_fn(count);
> +	if (unlikely(atomic_xchg(count, 0) != 1)) {
> +		/* Mark lock contention explicitly */
> +		if (likely(atomic_xchg(count, -1) != 1))
> +			fail_fn(count);
> +	}
>  }
>  
>  /**

Doesn't this mean that we're no longer just swapping 0 for a 0 if the lock
was taken, therefore needlessly sending the current owner down the slowpath
on unlock? If we have the explicit test, that doesn't happen and the
disassembly isn't much different (an additional cmp/conditional branch).

Will


From swarren at wwwdotorg.org  Thu Aug  9 14:04:14 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 09 Aug 2012 12:04:14 -0600
Subject: [PATCH V3] ARM: dt: tegra: ventana: add regulators
In-Reply-To: <5023A716.50807@nvidia.com>
References: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
 <5023A716.50807@nvidia.com>
Message-ID: <5023FB9E.4010904@wwwdotorg.org>

On 08/09/2012 06:03 AM, Laxman Dewangan wrote:
> On Friday 03 August 2012 11:39 PM, Stephen Warren wrote:
>> Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
>> couple of fixed GPIO-controlled regulators too.
...

Sorry, I didn't look below at your other comments. Now responding...

>> +        pmic: tps6586x at 34 {
>> +            compatible = "ti,tps6586x";
>> +            reg =<0x34>;
>> +            interrupts =<0 86 0x4>;
> 
> Should we say interrupt-controller also here?

I don't think so; it looks like all the interrupts within this chip are
for things that should be handled completely internally to to driver
itself. Either way, there's certainly nothing attempting to use any
interrupts from this chip right now, so if we did need that property, we
could always add it if/when we added a client that needed it.

>> +
>> +            sys-supply =<&vdd_5v0_reg>;
>> +            vin-sm0-supply =<&sys_reg>;
>> +            vin-sm1-supply =<&sys_reg>;
>> +            vin-sm2-supply =<&sys_reg>;
> 
> This depends on two changes on tps6586x regulator which are not merged yet.

Yes, I'm waiting for those changes to be merged before actually applying
this. However, there's no particular dependency; this patch simply won't
end up enabling the regulators until it's merged with the other patches,
so the .dts and regulator driver patches can go in through separate
trees OK.

>> +    pmc {
> 
> Should say status OK?

The default status is OK. Since the PMC is useful on all boards, it
isn't disabled in tegra30.dtsi; only board-specific things are disabled
in tegra30.dtsi (e.g. which I2C, MMC, I2S, ... ports are used is board
specific. Core SoC functionality isn't.)



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 14:05:49 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu,  9 Aug 2012 19:05:49 +0100
Subject: [PATCH 2/2] ARM: S3C64XX: Register audio platform devices for Bells
 on Cragganmore
In-Reply-To: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <1344535549-4371-2-git-send-email-broonie@opensource.wolfsonmicro.com>

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index ab8dbbe4..4103ed3 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -287,6 +287,16 @@ static struct platform_device littlemill_device = {
 	.id		= -1,
 };
 
+static struct platform_device bells_wm5102_device = {
+	.name		= "bells",
+	.id		= 0,
+};
+
+static struct platform_device bells_wm5110_device = {
+	.name		= "bells",
+	.id		= 1,
+};
+
 static struct regulator_consumer_supply wallvdd_consumers[] = {
 	REGULATOR_SUPPLY("SPKVDD", "1-001a"),
 	REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
@@ -359,6 +369,8 @@ static struct platform_device *crag6410_devices[] __initdata = {
 	&tobermory_device,
 	&littlemill_device,
 	&lowland_device,
+	&bells_wm5102_device,
+	&bells_wm5110_device,
 	&wallvdd_device,
 };
 
-- 
1.7.10.4



From broonie at opensource.wolfsonmicro.com  Thu Aug  9 14:05:48 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu,  9 Aug 2012 19:05:48 +0100
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module on
 Cragganmore
Message-ID: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>

SPI is also connected on the board, use that instead of I2C as it's much
faster. Also define platform data now the core driver is in mainline.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410-module.c |   35 ++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index f81f089..22dd77b 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -192,9 +192,33 @@ static const struct i2c_board_info wm1277_devs[] = {
 	},
 };
 
-static const struct i2c_board_info wm5102_devs[] = {
-	{ I2C_BOARD_INFO("wm5102", 0x1a),
-	  .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, },
+static struct arizona_pdata wm5102_pdata = {
+	.ldoena = S3C64XX_GPN(7),
+	.gpio_base = CODEC_GPIO_BASE,
+	.irq_active_high = true,
+	.micd_pol_gpio = CODEC_GPIO_BASE + 4,
+	.gpio_defaults = {
+		[2] = 0x10000, /* AIF3TXLRCLK */
+		[3] = 0x4,     /* OPCLK */
+	},
+};
+
+static struct s3c64xx_spi_csinfo wm5102_spi_csinfo = {
+	.line = S3C64XX_GPN(5),
+};
+
+static struct spi_board_info wm5102_spi_devs[] = {
+	[0] = {
+		.modalias	= "wm5102",
+		.max_speed_hz	= 10 * 1000 * 1000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+		.mode		= SPI_MODE_0,
+		.irq            = GLENFARCLAS_PMIC_IRQ_BASE +
+				  WM831X_IRQ_GPIO_2,
+		.controller_data = &wm5102_spi_csinfo,
+		.platform_data = &wm5102_pdata,
+	},
 };
 
 static const struct i2c_board_info wm6230_i2c_devs[] = {
@@ -234,8 +258,9 @@ static __devinitdata const struct {
 	{ .id = 0x3c, .name = "1273-EV1 Longmorn" },
 	{ .id = 0x3d, .name = "1277-EV1 Littlemill",
 	  .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
-	{ .id = 0x3e, .name = "WM5102-6271-EV1-CS127",
-	  .i2c_devs = wm5102_devs, .num_i2c_devs = ARRAY_SIZE(wm5102_devs) },
+	{ .id = 0x3e, .name = "WM5102-6271-EV1-CS127 Amrut",
+	  .spi_devs = wm5102_spi_devs,
+	  .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
 };
 
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
-- 
1.7.10.4



From nico at fluxnic.net  Thu Aug  9 14:09:02 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 09 Aug 2012 14:09:02 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120809175019.GE18486@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <20120809175019.GE18486@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208091405340.5231@xanadu.home>

On Thu, 9 Aug 2012, Will Deacon wrote:

> On Thu, Aug 09, 2012 at 05:57:33PM +0100, Nicolas Pitre wrote:
> > On Thu, 9 Aug 2012, Nicolas Pitre wrote:
> > > Yes, that looks fine.  I'd remove that if (prev < 0) entirely though.  
> > > We'll just swap a 0 for a 0 if the count wasn't < 0, or a 0 for a 1 if 
> > > the mutex just got unlocked which is also fine.  This is especially 
> > > beneficial when a native xchg processor instruction is used.
> > 
> > In fact, this suggestion isn't entirely correct either. The inner xchg 
> > in this case should be -1 and not 'count'.  If 'count' is 0 and the 
> > mutex becomes contended in the small window between the two xchg's then 
> > the contention mark would be lost again.
> > 
> > In other words, I think this should look like this:
> > 
> > diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> > index 580a6d35c7..44a66c99c8 100644
> > --- a/include/asm-generic/mutex-xchg.h
> > +++ b/include/asm-generic/mutex-xchg.h
> > @@ -25,8 +25,11 @@
> >  static inline void
> >  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
> >  {
> > -	if (unlikely(atomic_xchg(count, 0) != 1))
> > -		fail_fn(count);
> > +	if (unlikely(atomic_xchg(count, 0) != 1)) {
> > +		/* Mark lock contention explicitly */
> > +		if (likely(atomic_xchg(count, -1) != 1))
> > +			fail_fn(count);
> > +	}
> >  }
> >  
> >  /**
> 
> Doesn't this mean that we're no longer just swapping 0 for a 0 if the lock
> was taken, therefore needlessly sending the current owner down the slowpath
> on unlock?

If the lock was taken, this means the count was either 0 or -1.  If it 
was 1 then we just put a 0 there and we own it.  But if the cound was 0 
then we should store -1 instead, which is what the inner xchg does.  If 
the count was already -1 then we store -1 back.  That more closely mimic 
what the atomic dec does which is what we want.


Nicolas


From davidb at codeaurora.org  Thu Aug  9 14:11:12 2012
From: davidb at codeaurora.org (David Brown)
Date: Thu, 9 Aug 2012 11:11:12 -0700
Subject: [PATCH 2/2] msm: io: Change the default static iomappings to be
 shared
In-Reply-To: <1343696061-11445-1-git-send-email-rvaswani@codeaurora.org>
References: <1343696061-11445-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <20120809181112.GA24633@codeaurora.org>

On Mon, Jul 30, 2012 at 05:54:21PM -0700, Rohit Vaswani wrote:
> With 3.4 kernel the static iomappings can be shared with the ioremap
> mappings. If ioremap is called with an address for which a static
> mapping already exists, then that mapping should be used instead
> of creating a new one.
> However, the MT_DEVICE_NONSHARED flag prevents this. Hence, get rid
> of this flag. Some targets (7X00) that require the static iomappings
> to be NONSHARED use the MSM_DEVICE_TYPE and MSM_CHIP_DEVICE_TYPE macros.
> 
> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>  arch/arm/mach-msm/io.c |   25 +++++++++++++++++--------
>  1 files changed, 17 insertions(+), 8 deletions(-)

I don't seem to be able to find a tree that this change applies to.
Can you apply this patch to a recent kernel tree (v3.5 is good), and
resend.

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From will.deacon at arm.com  Thu Aug  9 14:17:05 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 9 Aug 2012 19:17:05 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208091405340.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <20120809175019.GE18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091405340.5231@xanadu.home>
Message-ID: <20120809181705.GG18486@mudshark.cambridge.arm.com>

On Thu, Aug 09, 2012 at 07:09:02PM +0100, Nicolas Pitre wrote:
> On Thu, 9 Aug 2012, Will Deacon wrote:
> > On Thu, Aug 09, 2012 at 05:57:33PM +0100, Nicolas Pitre wrote:
> > > On Thu, 9 Aug 2012, Nicolas Pitre wrote:
> > > diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> > > index 580a6d35c7..44a66c99c8 100644
> > > --- a/include/asm-generic/mutex-xchg.h
> > > +++ b/include/asm-generic/mutex-xchg.h
> > > @@ -25,8 +25,11 @@
> > >  static inline void
> > >  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
> > >  {
> > > -	if (unlikely(atomic_xchg(count, 0) != 1))
> > > -		fail_fn(count);
> > > +	if (unlikely(atomic_xchg(count, 0) != 1)) {
> > > +		/* Mark lock contention explicitly */
> > > +		if (likely(atomic_xchg(count, -1) != 1))
> > > +			fail_fn(count);
> > > +	}
> > >  }
> > >  
> > >  /**
> > 
> > Doesn't this mean that we're no longer just swapping 0 for a 0 if the lock
> > was taken, therefore needlessly sending the current owner down the slowpath
> > on unlock?
> 
> If the lock was taken, this means the count was either 0 or -1.  If it 
> was 1 then we just put a 0 there and we own it.  But if the cound was 0 
> then we should store -1 instead, which is what the inner xchg does.  If 
> the count was already -1 then we store -1 back.  That more closely mimic 
> what the atomic dec does which is what we want.

Ok, I just wasn't sure that marking the lock contended was required when it
was previously locked, given that we'll drop into spinning on the owner
anyway.

I'll add a commit message to the above and re-post if that's ok?

Will


From nsekhar at ti.com  Thu Aug  9 14:23:26 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Thu, 9 Aug 2012 23:53:26 +0530
Subject: [PATCH v2 06/10] ARM: davinci: don't use broken ntosd2_init_i2c
In-Reply-To: <201208090800.18321.arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-7-git-send-email-arnd@arndb.de>
 <201208090800.18321.arnd@arndb.de>
Message-ID: <5024001E.3080803@ti.com>

Hi Arnd,

On 8/9/2012 1:30 PM, Arnd Bergmann wrote:
> On second thought, there is probably no use in keeping the broken function
> around, and we can just kill it off. If someone wants to add an i2c
> device to the bus, they can always add the init code back as well.
> 
> 8<-----
> Subject: ARM: davinci: don't use broken ntosd2_init_i2c
> 
> ntosd2_init_i2c walks the ntosd2_i2c_info array, which it expects to
> be populated with at least one member. gcc correctly warns about
> the out-of-bounds access here.
> 
> Since this can not possibly work, it's better to disable i2c
> support entirely on this board.
> 
> Without this patch, building davinci_all_defconfig results in:
> 
> arch/arm/mach-davinci/board-neuros-osd2.c: In function 'davinci_ntosd2_init':
> arch/arm/mach-davinci/board-neuros-osd2.c:187:20: warning: array subscript is above array bounds [-Warray-bounds]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Andrey Porodko <panda at chelcom.ru>

Acked-by: Sekhar Nori <nsekhar at ti.com>

Thanks,
Sekhar


From broonie at opensource.wolfsonmicro.com  Thu Aug  9 14:50:29 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 9 Aug 2012 19:50:29 +0100
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
In-Reply-To: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20120809185029.GC24328@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 04:47:26PM +0100, Lee Jones wrote:
> Another fine instalment of Audio fixes and Device Tree enablement
> surrounding the mop500 sound driver. Hopefully containing all of 
> the recommendations suggested by Mark Brown.

Can we have some review of this from the ARM side please?  It's pretty
big...


From matt at genesi-usa.com  Thu Aug  9 15:03:13 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 9 Aug 2012 14:03:13 -0500
Subject: imx6q restart is broken
In-Reply-To: <20120809092021.GQ18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
Message-ID: <CAKGA1b=--C_MEHgc4m2f4cQwkx-=njss7bpT+EzXgKZJ2v=+Hw@mail.gmail.com>

On Thu, Aug 9, 2012 at 4:20 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
>> - at the last stage of reset, all non-boot cpus will call
>> ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb() for
>> V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10, 5")
>
> I suspect having this dmb inside cpu_relax() is flooding the
> interconnects with traffic, which then prevents other CPUs getting
> a look-in (maybe there's no fairness when it comes to dmb's.
>
> If I'm right, you'll find is that even converting this to the ARMv7
> DMB instruction won't fix the problem.  It does, however, point
> towards a more serious problem - it means that any tight loop using
> dmb is detremental.  I have heard some people mention that even on
> various ARM SMP platforms, they have see quite an amount of
> interaction between the individual CPU cores, and I'm beginning
> to wonder whether this is why.

I have an irrelevant but possibly related question here; in
mm/proc-v7.S there's this snip of code;

#ifdef CONFIG_SMP
        ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
        ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
        tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
        orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
        orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
        mcreq   p15, 0, r0, c1, c0, 1
#endif

Which I am reading as, read the SMP bit from cp15 and see if it's
enabled, or on UP set the SMP bit and then write it back
regardless.

On a system where !CONFIG_SMP but it's SMP-capable like i.MX6Q, ALT_UP
method will get used and the SMP bit will get
set regardless. No other cores will be enabled (at least the i.MX6Q
you need to turn them on using the System Reset
Controller..) but it's still going to end up involving the processors
in SMP activity on the bus. Or.. actually it just sets the SMP
bit *regardless* on any platform. I don't have my assembly hat on
today. Is this correct? Is this actually architecturally correct?

Does SMP bit get set regardless on any system that has multiple CPU
cores but they're all brought down except the
primary (or only-left-executing) core?

Once you've got all the CPUs down, in my mind, SMP should be unset and
in theory any cache management broadcasts
between the CPUs should stop architecturally (with the caveat that on
CPU hotplug, you need to flush the bejesus out
of the primary CPU cache and invalidate the cache for one you just
brought up). So I assume this is some kind of
performance optimization to enable CPUs to be unplugged and replugged
without expensive cache management? Aren't
caches invalidated/flushed by the kernel anyway at this point, or is
the expectation that the SCU/PL310 or so would
manage this underneath as long as the primary CPU is involved in SMP?

Above that TLB ops broadcasting is turned on for A9 and A15 too. Even
in UP? Are these operations simply essential
to the SCU since it might not have any idea how many CPUs are running,
and just broadcasts changes on the AXI bus
anyway for the one CPU that's left to pick up?

The docs don't make it too clear what's going on here, and the code
doesn't enlighten me. I would think that on a non-SMP
system you'd want to turn all of this off, not "fake it for UP"..?

We think we've had some serious performance problems here which point
to a significant loss of performance on the AXI
bus going to DDR memory. The only thing we can attribute it to is some
misconfiguration of the SCU/PL310 or on MX51
maybe the "M4IF" unit with regards to AXI caching or priority for
different bus masters, and that SMP bus traffic is causing
a bottleneck of cache management operations. Otherwise we'd expect
several gigabytes per second to memory in a
streaming situation and we can architect it to only manage a couple of
hundred, and that doesn't seem at all right (since
beyond using misaligned accesses or plain kooky instruction sequences,
everything gets aligned by the time it gets to
DDR, and the DDR memory controller should be doing huge bursts which
get cached in the bus arbiter..). I can only look
at this from a naive point of view because there's no way to look at
it with the bare minimum code running, we need the
OS around to do what we're doing. Also in other tests (cortex-strings)
we get ridiculously good performance, but that's
mostly because it's single threaded.. no other CPU does anything and
the cache is basically useless with very large
transfers.

Now we know dmb makes things explode, you have to wonder are things
being needlessly involved here or turned on
when they needn't be, just to make the code easier to write?

We also saw a performance decrease by some hard to understand amount
in the lpj calculation on i.MX51 between
a CPU_V7-only kernel based on 2.6.31 and Freescale's BSP, versus a
V6/V7 defconfig kernel direct from mainline.
I wonder if the less efficient V6 stuff is causing that.. it would
really, really bite if that was it... we're still running tests
though. We like to enable errata fixes regardless of whether it's on
our processor since the vast majority of them are
only selected at runtime depending on whether the core or unit
revision affected is present, however...

#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
#define cpu_relax()                    smp_mb()
#else
#define cpu_relax()                    barrier()
#endif

This dirt-old (pre r2p0) Cortex-A9 erratum being selected will force a
V7-only kernel to use smp_mb rather than
barrier regardless of what the processor type is.. that means every
one-image-for-ARMv7 kernel which included
Tegra2, the appropriate above erratum and a few others would hit this
problem regardless. I assume if looping
and comparing a value of "i" and then calling smp_mb can't break the
procedure being expected then reading out
the CPU core revision from a cached value in memory somewhere and
comparing it and OPTIONALLY running
smp_mb (which is then defined as dmb) would not be bad either?

Maybe I am getting this backwards, but I really want someone to tell me that :)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From rjw at sisk.pl  Thu Aug  9 15:32:24 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 9 Aug 2012 21:32:24 +0200
Subject: [PATCH v2 1/2] cpufreq: OMAP: Handle missing frequency table on
 SMP systems
In-Reply-To: <87d330glel.fsf@ti.com>
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
 <201208091132.14992.rjw@sisk.pl> <87d330glel.fsf@ti.com>
Message-ID: <201208092132.25141.rjw@sisk.pl>

On Thursday, August 09, 2012, Kevin Hilman wrote:
> "Rafael J. Wysocki" <rjw at sisk.pl> writes:
> 
> > On Thursday, August 09, 2012, Rajendra Nayak wrote:
> >> On OMAP4, if the first CPU fails to get a valid frequency table (this
> >> could happen if the platform does not register any OPP table), the
> >> subsequent CPU instances end up dealing with a NULL freq_table and
> >> crash.
> >> 
> >> Check for an already existing freq_table, before trying to create one,
> >> and increment the freq_table_users only if the table is sucessfully
> >> created.
> >> 
> >> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> >> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >> Cc: <linux-pm at vger.kernel.org>
> >
> > Kevin, are you going to merge this?
> >
> 
> Yes, I plan to queue this with 2/2 for v3.6-rc.

If you have any cpufreq patches for v3.7, can you please tell me where to
pull them from (and when)?

Rafael


From lee.jones at linaro.org  Thu Aug  9 15:40:46 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 9 Aug 2012 20:40:46 +0100
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
In-Reply-To: <20120809185029.GC24328@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <20120809185029.GC24328@opensource.wolfsonmicro.com>
Message-ID: <20120809194044.GA9966@gmail.com>

On Thu, Aug 09, 2012 at 07:50:29PM +0100, Mark Brown wrote:
> On Thu, Aug 09, 2012 at 04:47:26PM +0100, Lee Jones wrote:
> > Another fine instalment of Audio fixes and Device Tree enablement
> > surrounding the mop500 sound driver. Hopefully containing all of 
> > the recommendations suggested by Mark Brown.
> 
> Can we have some review of this from the ARM side please?  It's pretty
> big...

I don't expect Linus will do anything until he returns back from vacation.

I'll speak to Arnd tomorrow and offer him some kind of liquid refreshment. :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu Aug  9 15:44:05 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 9 Aug 2012 20:44:05 +0100
Subject: [PATCH 1/8] of/irq: Create stub for of_irq_find_parent when
 !CONFIG_OF
In-Reply-To: <5023E366.9010603@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
 <5023E366.9010603@gmail.com>
Message-ID: <20120809194403.GB9966@gmail.com>

On Thu, Aug 09, 2012 at 11:20:54AM -0500, Rob Herring wrote:
> On 08/09/2012 10:53 AM, Lee Jones wrote:
> > of_irq_find_parent is a handy function to use outside the confines of
> > the Open Firmware subsystem. One such use-case is when the IRQ Domain
> > wishes to find an IRQ domain for a given device node. Currently it can
> > not take any notice of the 'interrupt-parent' property. Instead it
> > just uses the first IRQ controller as it climbs the Device Tree. If
> > we were to use this as a precursor the resultant controller is more
> > likely to be correct.
> 
> Where are you using this? I don't have all the patches in the series.

Sorry Rob. Here:

https://lkml.org/lkml/2012/8/9/373

> > CC: Rob Herring <rob.herring at calxeda.com>
> > CC: devicetree-discuss at lists.ozlabs.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >  include/linux/of_irq.h |    5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
> > index 1717cd9..b8e2411 100644
> > --- a/include/linux/of_irq.h
> > +++ b/include/linux/of_irq.h
> > @@ -83,6 +83,11 @@ static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
> >  {
> >  	return 0;
> >  }
> > +
> > +static inline void *of_irq_find_parent(struct device_node *child)
> > +{
> > +	return NULL;
> > +}
> >  #endif /* !CONFIG_OF */
> >  
> >  #endif /* __OF_IRQ_H */
> > 
> 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From robherring2 at gmail.com  Thu Aug  9 15:53:23 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 09 Aug 2012 14:53:23 -0500
Subject: [PATCH 1/8] of/irq: Create stub for of_irq_find_parent when
 !CONFIG_OF
In-Reply-To: <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
Message-ID: <50241533.3080709@gmail.com>

On 08/09/2012 10:53 AM, Lee Jones wrote:
> of_irq_find_parent is a handy function to use outside the confines of
> the Open Firmware subsystem. One such use-case is when the IRQ Domain
> wishes to find an IRQ domain for a given device node. Currently it can
> not take any notice of the 'interrupt-parent' property. Instead it
> just uses the first IRQ controller as it climbs the Device Tree. If
> we were to use this as a precursor the resultant controller is more
> likely to be correct.
> 
> CC: Rob Herring <rob.herring at calxeda.com>
> CC: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Rob Herring <rob.herring at calxeda.com>

Rob

> ---
>  include/linux/of_irq.h |    5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
> index 1717cd9..b8e2411 100644
> --- a/include/linux/of_irq.h
> +++ b/include/linux/of_irq.h
> @@ -83,6 +83,11 @@ static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
>  {
>  	return 0;
>  }
> +
> +static inline void *of_irq_find_parent(struct device_node *child)
> +{
> +	return NULL;
> +}
>  #endif /* !CONFIG_OF */
>  
>  #endif /* __OF_IRQ_H */
> 



From nico at fluxnic.net  Thu Aug  9 16:05:24 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 09 Aug 2012 16:05:24 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120809181705.GG18486@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <20120809175019.GE18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091405340.5231@xanadu.home>
 <20120809181705.GG18486@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208091601570.5231@xanadu.home>

On Thu, 9 Aug 2012, Will Deacon wrote:

> On Thu, Aug 09, 2012 at 07:09:02PM +0100, Nicolas Pitre wrote:
> > On Thu, 9 Aug 2012, Will Deacon wrote:
> > > On Thu, Aug 09, 2012 at 05:57:33PM +0100, Nicolas Pitre wrote:
> > > > On Thu, 9 Aug 2012, Nicolas Pitre wrote:
> > > > diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> > > > index 580a6d35c7..44a66c99c8 100644
> > > > --- a/include/asm-generic/mutex-xchg.h
> > > > +++ b/include/asm-generic/mutex-xchg.h
> > > > @@ -25,8 +25,11 @@
> > > >  static inline void
> > > >  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
> > > >  {
> > > > -	if (unlikely(atomic_xchg(count, 0) != 1))
> > > > -		fail_fn(count);
> > > > +	if (unlikely(atomic_xchg(count, 0) != 1)) {
> > > > +		/* Mark lock contention explicitly */
> > > > +		if (likely(atomic_xchg(count, -1) != 1))
> > > > +			fail_fn(count);
> > > > +	}
> > > >  }
> > > >  
> > > >  /**
> > > 
> > > Doesn't this mean that we're no longer just swapping 0 for a 0 if the lock
> > > was taken, therefore needlessly sending the current owner down the slowpath
> > > on unlock?
> > 
> > If the lock was taken, this means the count was either 0 or -1.  If it 
> > was 1 then we just put a 0 there and we own it.  But if the cound was 0 
> > then we should store -1 instead, which is what the inner xchg does.  If 
> > the count was already -1 then we store -1 back.  That more closely mimic 
> > what the atomic dec does which is what we want.
> 
> Ok, I just wasn't sure that marking the lock contended was required when it
> was previously locked, given that we'll drop into spinning on the owner
> anyway.

That's fine, and the owner will put 1 back when it unlocks it as well as 
processing the wait queue which is what we need.

> I'll add a commit message to the above and re-post if that's ok?

Sure.  Don't forget to update __mutex_fastpath_lock_retval() as well.


Nicolas


From rmallon at gmail.com  Thu Aug  9 17:02:41 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Fri, 10 Aug 2012 07:02:41 +1000
Subject: [PATCH] ARM: ep93xx: clockevent support
In-Reply-To: <CANapsLQ6kCUN5UoaA3xejm24SGxCKmZEFgmR_+r7N-=DPz0TVA@mail.gmail.com>
References: <1344338474.18237.6.camel@localhost>	<5021122C.3000503@gmail.com>
 <CANapsLQ6kCUN5UoaA3xejm24SGxCKmZEFgmR_+r7N-=DPz0TVA@mail.gmail.com>
Message-ID: <50242571.70402@gmail.com>

On 09/08/12 18:54, Yan Burman wrote:

> On 8/7/12, Ryan Mallon <rmallon at gmail.com> wrote:
>> On 07/08/12 21:21, Yan Burman wrote:
>>
>>> ARM: ep93xx: clockevent support
>>> I have ported to 3.6-rc1 and slightly modified a previous patch for
>>> clockevent support for the ep93xx.
>>> The porting mainly consists of sched_clock support.
>>> Tested on 9302 based board.
>>> From: Ahmed Ammar <aammar <at> edge-techno.com>
>>> Signed-off-by: Yan Burman <burman.yan at gmail.com>
>>
>>
>> Hi Yan, some comments below.
>>
>> ~Ryan
>>
>>> +	case CLOCK_EVT_MODE_ONESHOT:
>>> +		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
>>> +		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
>>> +		break;
>>> +
>>> +	case CLOCK_EVT_MODE_SHUTDOWN:
>>> +	case CLOCK_EVT_MODE_UNUSED:
>>> +	case CLOCK_EVT_MODE_RESUME:
>>> +		return;
>>
>>
>> These cases can be removed.
>>
> 
> This case is something that is present in most (if not all) other architectures.
> I don't mind removing it, but it will have to be replaced with:
> default:
>      ;
> 
> Since GCC produces warnings otherwise.

Oh, I missed the fact the switch was on an enum. You are correct, we
should keep the code consistent with other architectures, so this
can be left as is.

> Other than that I am going to wait a while more for more comments if
> somebody has them,
> and post a new version with style fixes as well as switch to
> drivers/clocksource/mmio.c usage.


Great, thanks,
~Ryan


From linux at arm.linux.org.uk  Thu Aug  9 17:07:09 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 22:07:09 +0100
Subject: imx6q restart is broken
In-Reply-To: <CAKGA1b=--C_MEHgc4m2f4cQwkx-=njss7bpT+EzXgKZJ2v=+Hw@mail.gmail.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <CAKGA1b=--C_MEHgc4m2f4cQwkx-=njss7bpT+EzXgKZJ2v=+Hw@mail.gmail.com>
Message-ID: <20120809210709.GV18957@n2100.arm.linux.org.uk>

On Thu, Aug 09, 2012 at 02:03:13PM -0500, Matt Sealey wrote:
> I have an irrelevant but possibly related question here; in
> mm/proc-v7.S there's this snip of code;
> 
> #ifdef CONFIG_SMP
>         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
>         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
>         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
>         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
>         mcreq   p15, 0, r0, c1, c0, 1
> #endif
> 
> Which I am reading as, read the SMP bit from cp15 and see if it's
> enabled, or on UP set the SMP bit and then write it back
> regardless.
> 
> On a system where !CONFIG_SMP but it's SMP-capable like i.MX6Q, ALT_UP
> method will get used and the SMP bit will get
> set regardless.

I got here and stopped reading any further.  No, it doesn't work like
that; you don't understand the assembly.

Yes, you're right that the ALT_UP version will be used.  This sets r0
to 1 << 6.  The very next instruction tests whether bit 6 is set in r0.
The following three instructions will only be executed _if_ that bit
was zero.

I'm assuming that the rest of your email is therefore irrelevant; I
have no desire to continue reading such a long message when the premise
it's (presumably) based upon is false.  If you have any further questions
please restate them succinctly after taking on board the above.  Thanks.


From nicolas.pitre at linaro.org  Thu Aug  9 17:12:58 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 9 Aug 2012 17:12:58 -0400 (EDT)
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <1344461278-28245-5-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-5-git-send-email-arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208091709010.5231@xanadu.home>

On Wed, 8 Aug 2012, Arnd Bergmann wrote:

> The Linaro cross toolchain and probably others nowadays default to
> building in THUMB2 mode. When building a kernel for a CPU that does
> not support THUMB2, the compiler complains about incorrect flags.
> We can work around this by setting -marm for all non-T2 builds.
> 
> Without this patch, building assabet_defconfig results in:
> 
> usr/initramfs_data.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
> arch/arm/nwfpe/entry.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
> firmware/cis/PCMLM28.cis.gen.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
> (and many more)
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Dave Martin <dave.martin at linaro.org>
> ---
>  arch/arm/Makefile |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 30eae87..b4c2296 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -111,6 +111,9 @@ AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
>  ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)
>  CFLAGS_MODULE	+=-fno-optimize-sibling-calls
>  endif
> +else
> +CFLAGS_THUMB2  :=-marm
> +AFLAGS_THUMB2	:=-marm

CFLAGS_THUMB2 should probably be renamed to something more appropriate 
in this case, e.g. CFLAGS_MODE.


Nicolas


From festevam at gmail.com  Thu Aug  9 17:16:46 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu,  9 Aug 2012 18:16:46 -0300
Subject: [PATCH v2] ARM: mxs_defconfig: Add framebuffer support
Message-ID: <1344547006-26738-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Add framebuffer support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Add missing features and tested on a mx28evk
 arch/arm/configs/mxs_defconfig |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 9e79125..67d5c05 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -109,6 +109,15 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_USB=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
-- 
1.7.1



From linux at arm.linux.org.uk  Thu Aug  9 17:17:17 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 9 Aug 2012 22:17:17 +0100
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <alpine.LFD.2.02.1208091709010.5231@xanadu.home>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-5-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208091709010.5231@xanadu.home>
Message-ID: <20120809211717.GW18957@n2100.arm.linux.org.uk>

On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote:
> CFLAGS_THUMB2 should probably be renamed to something more appropriate 
> in this case, e.g. CFLAGS_MODE.

CFLAGS_ISA would be more relevant to it, because it's selecting the
instruction set.


From nicolas.pitre at linaro.org  Thu Aug  9 17:22:30 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 9 Aug 2012 17:22:30 -0400 (EDT)
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <20120809211717.GW18957@n2100.arm.linux.org.uk>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-5-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208091709010.5231@xanadu.home>
 <20120809211717.GW18957@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1208091721460.5231@xanadu.home>

On Thu, 9 Aug 2012, Russell King - ARM Linux wrote:

> On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote:
> > CFLAGS_THUMB2 should probably be renamed to something more appropriate 
> > in this case, e.g. CFLAGS_MODE.
> 
> CFLAGS_ISA would be more relevant to it, because it's selecting the
> instruction set.

Agreed.  This particular TLA escaped my mind somehow.


Nicolas


From khilman at ti.com  Thu Aug  9 17:25:39 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 09 Aug 2012 14:25:39 -0700
Subject: [PATCH v2 1/2] cpufreq: OMAP: Handle missing frequency table on
 SMP systems
In-Reply-To: <201208092132.25141.rjw@sisk.pl> (Rafael J. Wysocki's message of
 "Thu, 9 Aug 2012 21:32:24 +0200")
References: <1344496102-24451-1-git-send-email-rnayak@ti.com>
 <201208091132.14992.rjw@sisk.pl> <87d330glel.fsf@ti.com>
 <201208092132.25141.rjw@sisk.pl>
Message-ID: <874nobhi5o.fsf@ti.com>

"Rafael J. Wysocki" <rjw at sisk.pl> writes:

> On Thursday, August 09, 2012, Kevin Hilman wrote:
>> "Rafael J. Wysocki" <rjw at sisk.pl> writes:
>> 
>> > On Thursday, August 09, 2012, Rajendra Nayak wrote:
>> >> On OMAP4, if the first CPU fails to get a valid frequency table (this
>> >> could happen if the platform does not register any OPP table), the
>> >> subsequent CPU instances end up dealing with a NULL freq_table and
>> >> crash.
>> >> 
>> >> Check for an already existing freq_table, before trying to create one,
>> >> and increment the freq_table_users only if the table is sucessfully
>> >> created.
>> >> 
>> >> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
>> >> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> >> Cc: <linux-pm at vger.kernel.org>
>> >
>> > Kevin, are you going to merge this?
>> >
>> 
>> Yes, I plan to queue this with 2/2 for v3.6-rc.
>
> If you have any cpufreq patches for v3.7, can you please tell me where to
> pull them from (and when)?

Yes, I will. 

Thanks,

Kevin


From linus.walleij at linaro.org  Thu Aug  9 18:43:40 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 00:43:40 +0200
Subject: [PATCH 2/2] ARM: nomadik: configure Nomadik for pin control
Message-ID: <1344552220-995-1-git-send-email-linus.walleij@linaro.org>

This converts the Nomadik to using pin control using the
driver for the STN8815 ASIC.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                      |  1 +
 arch/arm/mach-nomadik/board-nhk8815.c | 36 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-nomadik/cpu-8815.c      | 13 +++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..2bd9953 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -962,6 +962,7 @@ config ARCH_NOMADIK
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
 	select PINCTRL
+	select PINCTRL_STN8815
 	select MIGHT_HAVE_CACHE_L2X0
 	select ARCH_REQUIRE_GPIOLIB
 	help
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index f4535a7..66862fb 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
@@ -33,6 +34,7 @@
 
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
+#include <plat/pincfg.h>
 
 #include <mach/nand.h>
 #include <mach/fsmc.h>
@@ -291,8 +293,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
 	},
 };
 
+static unsigned long out_low[] = { PIN_OUTPUT_LOW };
+static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
+static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
+static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
+
+static struct pinctrl_map __initdata nhk8815_pinmap[] = {
+	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
+	/* Hog in MMC/SD card mux */
+	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
+	/* MCCLK */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
+	/* MCCMD */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
+	/* MCCMDDIR */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
+	/* MCDAT3-0 */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
+	/* MCDAT0DIR */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
+	/* MCDAT31DIR */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
+	/* MCMSFBCLK */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
+	/* CD input GPIO */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
+	/* CD bias drive */
+	PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
+};
+
 static void __init nhk8815_platform_init(void)
 {
+	pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
 	cpu8815_platform_init();
 	nhk8815_onenand_init();
 	platform_add_devices(nhk8815_platform_devices,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 6fd8e46..b617eae 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
 	}
 }
 
+static inline void
+cpu8815_add_pinctrl(struct device *parent, const char *name)
+{
+	struct platform_device_info pdevinfo = {
+		.parent = parent,
+		.name = name,
+		.id = -1,
+	};
+
+	platform_device_register_full(&pdevinfo);
+}
+
 static int __init cpu8815_init(void)
 {
 	struct nmk_gpio_platform_data pdata = {
@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
 
 	cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
 			  IRQ_GPIO0, &pdata);
+	cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
 	amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
 	amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
 	return 0;
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug  9 18:43:28 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 00:43:28 +0200
Subject: [PATCH 1/2] pinctrl/nomadik: add STn8815 ASIC support
Message-ID: <1344552208-957-1-git-send-email-linus.walleij@linaro.org>

This adds support for the STN8815 ASIC for the Nomadik pin
controller.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/Kconfig                   |   4 +
 drivers/pinctrl/Makefile                  |   1 +
 drivers/pinctrl/pinctrl-nomadik-stn8815.c | 357 ++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-nomadik.c         |   2 +
 drivers/pinctrl/pinctrl-nomadik.h         |  13 ++
 5 files changed, 377 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-nomadik-stn8815.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..17379f9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -86,6 +86,10 @@ config PINCTRL_NOMADIK
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_STN8815
+	bool "STN8815 pin controller driver"
+	depends on PINCTRL_NOMADIK && ARCH_NOMADIK
+
 config PINCTRL_DB8500
 	bool "DB8500 pin controller driver"
 	depends on PINCTRL_NOMADIK && ARCH_U8500
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..4aed49c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MXS)	+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_IMX23)	+= pinctrl-imx23.o
 obj-$(CONFIG_PINCTRL_IMX28)	+= pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_NOMADIK)	+= pinctrl-nomadik.o
+obj-$(CONFIG_PINCTRL_STN8815)	+= pinctrl-nomadik-stn8815.o
 obj-$(CONFIG_PINCTRL_DB8500)	+= pinctrl-nomadik-db8500.o
 obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)	+= pinctrl-pxa910.o
diff --git a/drivers/pinctrl/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
new file mode 100644
index 0000000..7d432c3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-stn8815.c
@@ -0,0 +1,357 @@
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-nomadik.h"
+
+/* All the pins that can be used for GPIO and some other functions */
+#define _GPIO(offset)		(offset)
+
+#define STN8815_PIN_B4		_GPIO(0)
+#define STN8815_PIN_D5		_GPIO(1)
+#define STN8815_PIN_C5		_GPIO(2)
+#define STN8815_PIN_A4		_GPIO(3)
+#define STN8815_PIN_B5		_GPIO(4)
+#define STN8815_PIN_D6		_GPIO(5)
+#define STN8815_PIN_C6		_GPIO(6)
+#define STN8815_PIN_B6		_GPIO(7)
+#define STN8815_PIN_B10		_GPIO(8)
+#define STN8815_PIN_A10		_GPIO(9)
+#define STN8815_PIN_C11		_GPIO(10)
+#define STN8815_PIN_B11		_GPIO(11)
+#define STN8815_PIN_A11		_GPIO(12)
+#define STN8815_PIN_C12		_GPIO(13)
+#define STN8815_PIN_B12		_GPIO(14)
+#define STN8815_PIN_A12		_GPIO(15)
+#define STN8815_PIN_C13		_GPIO(16)
+#define STN8815_PIN_B13		_GPIO(17)
+#define STN8815_PIN_A13		_GPIO(18)
+#define STN8815_PIN_D13		_GPIO(19)
+#define STN8815_PIN_C14		_GPIO(20)
+#define STN8815_PIN_B14		_GPIO(21)
+#define STN8815_PIN_A14		_GPIO(22)
+#define STN8815_PIN_D15		_GPIO(23)
+#define STN8815_PIN_C15		_GPIO(24)
+#define STN8815_PIN_B15		_GPIO(25)
+#define STN8815_PIN_A15		_GPIO(26)
+#define STN8815_PIN_C16		_GPIO(27)
+#define STN8815_PIN_B16		_GPIO(28)
+#define STN8815_PIN_A16		_GPIO(29)
+#define STN8815_PIN_D17		_GPIO(30)
+#define STN8815_PIN_C17		_GPIO(31)
+#define STN8815_PIN_AB6		_GPIO(32)
+#define STN8815_PIN_AA6		_GPIO(33)
+#define STN8815_PIN_Y6		_GPIO(34)
+#define STN8815_PIN_Y5		_GPIO(35)
+#define STN8815_PIN_AA5		_GPIO(36)
+#define STN8815_PIN_AB5		_GPIO(37)
+#define STN8815_PIN_AB4		_GPIO(38)
+#define STN8815_PIN_Y4		_GPIO(39)
+#define STN8815_PIN_R1		_GPIO(40)
+#define STN8815_PIN_R2		_GPIO(41)
+#define STN8815_PIN_R3		_GPIO(42)
+#define STN8815_PIN_P1		_GPIO(43)
+#define STN8815_PIN_P2		_GPIO(44)
+#define STN8815_PIN_P3		_GPIO(45)
+#define STN8815_PIN_N1		_GPIO(46)
+#define STN8815_PIN_N2		_GPIO(47)
+#define STN8815_PIN_N3		_GPIO(48)
+#define STN8815_PIN_M1		_GPIO(49)
+#define STN8815_PIN_M3		_GPIO(50)
+#define STN8815_PIN_M2		_GPIO(51)
+#define STN8815_PIN_L1		_GPIO(52)
+#define STN8815_PIN_L4		_GPIO(53)
+#define STN8815_PIN_L3		_GPIO(54)
+#define STN8815_PIN_L2		_GPIO(55)
+#define STN8815_PIN_F3		_GPIO(56)
+#define STN8815_PIN_F2		_GPIO(57)
+#define STN8815_PIN_E1		_GPIO(58)
+#define STN8815_PIN_E3		_GPIO(59)
+#define STN8815_PIN_E2		_GPIO(60)
+#define STN8815_PIN_E4		_GPIO(61)
+#define STN8815_PIN_D3		_GPIO(62)
+#define STN8815_PIN_D2		_GPIO(63)
+#define STN8815_PIN_F21		_GPIO(64)
+#define STN8815_PIN_F20		_GPIO(65)
+#define STN8815_PIN_E22		_GPIO(66)
+#define STN8815_PIN_D22		_GPIO(67)
+#define STN8815_PIN_E21		_GPIO(68)
+#define STN8815_PIN_E20		_GPIO(69)
+#define STN8815_PIN_C22		_GPIO(70)
+#define STN8815_PIN_D21		_GPIO(71)
+#define STN8815_PIN_D20		_GPIO(72)
+#define STN8815_PIN_C21		_GPIO(73)
+#define STN8815_PIN_C20		_GPIO(74)
+#define STN8815_PIN_C19		_GPIO(75)
+#define STN8815_PIN_B20		_GPIO(76)
+#define STN8815_PIN_B8		_GPIO(77)
+#define STN8815_PIN_A8		_GPIO(78)
+#define STN8815_PIN_C9		_GPIO(79)
+#define STN8815_PIN_B9		_GPIO(80)
+#define STN8815_PIN_A9		_GPIO(81)
+#define STN8815_PIN_C10		_GPIO(82)
+#define STN8815_PIN_K1		_GPIO(83)
+#define STN8815_PIN_K3		_GPIO(84)
+#define STN8815_PIN_K2		_GPIO(85)
+#define STN8815_PIN_J1		_GPIO(86)
+#define STN8815_PIN_J3		_GPIO(87)
+#define STN8815_PIN_J2		_GPIO(88)
+#define STN8815_PIN_H1		_GPIO(89)
+#define STN8815_PIN_H3		_GPIO(90)
+#define STN8815_PIN_H2		_GPIO(91)
+#define STN8815_PIN_G1		_GPIO(92)
+#define STN8815_PIN_G3		_GPIO(93)
+#define STN8815_PIN_G2		_GPIO(94)
+#define STN8815_PIN_F1		_GPIO(95)
+#define STN8815_PIN_T20		_GPIO(96)
+#define STN8815_PIN_R21		_GPIO(97)
+#define STN8815_PIN_R20		_GPIO(98)
+#define STN8815_PIN_U22		_GPIO(99)
+#define STN8815_PIN_N21		_GPIO(100)
+#define STN8815_PIN_N20		_GPIO(101)
+#define STN8815_PIN_P22		_GPIO(102)
+#define STN8815_PIN_N22		_GPIO(103)
+#define STN8815_PIN_V22		_GPIO(104)
+#define STN8815_PIN_V21		_GPIO(105)
+#define STN8815_PIN_K22		_GPIO(106)
+#define STN8815_PIN_K21		_GPIO(107)
+#define STN8815_PIN_H20		_GPIO(108)
+#define STN8815_PIN_G20		_GPIO(109)
+#define STN8815_PIN_L21		_GPIO(110)
+#define STN8815_PIN_H21		_GPIO(111)
+#define STN8815_PIN_J21		_GPIO(112)
+#define STN8815_PIN_H22		_GPIO(113)
+#define STN8815_PIN_K20		_GPIO(114)
+#define STN8815_PIN_L22		_GPIO(115)
+#define STN8815_PIN_G21		_GPIO(116)
+#define STN8815_PIN_J20		_GPIO(117)
+#define STN8815_PIN_G22		_GPIO(118)
+#define STN8815_PIN_U19		_GPIO(119)
+#define STN8815_PIN_G19		_GPIO(120)
+#define STN8815_PIN_M22		_GPIO(121)
+#define STN8815_PIN_M19		_GPIO(122)
+#define STN8815_PIN_J22		_GPIO(123)
+/* GPIOs 124-127 not routed to pins */
+
+/*
+ * The names of the pins are denoted by GPIO number and ball name, even
+ * though they can be used for other things than GPIO, this is the first
+ * column in the table of the data sheet and often used on schematics and
+ * such.
+ */
+static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
+	PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
+	PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
+	PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
+	PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
+	PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
+	PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
+	PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
+	PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
+	PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
+	PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
+	PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
+	PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
+	PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
+	PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
+	PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
+	PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
+	PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"),
+	PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"),
+	PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"),
+	PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"),
+	PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"),
+	PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"),
+	PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"),
+	PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"),
+	PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"),
+	PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"),
+	PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"),
+	PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"),
+	PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"),
+	PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"),
+	PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"),
+	PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"),
+	PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"),
+	PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"),
+	PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"),
+	PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"),
+	PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"),
+	PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"),
+	PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"),
+	PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"),
+	PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"),
+	PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"),
+	PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"),
+	PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"),
+	PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"),
+	PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"),
+	PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"),
+	PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"),
+	PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"),
+	PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"),
+	PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"),
+	PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"),
+	PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"),
+	PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"),
+	PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"),
+	PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"),
+	PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"),
+	PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"),
+	PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"),
+	PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"),
+	PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"),
+	PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"),
+	PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"),
+	PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"),
+	PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"),
+	PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"),
+	PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"),
+	PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"),
+	PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"),
+	PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"),
+	PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"),
+	PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"),
+	PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"),
+	PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"),
+	PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"),
+	PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"),
+	PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"),
+	PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"),
+	PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"),
+	PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"),
+	PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"),
+	PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"),
+	PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"),
+	PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"),
+	PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"),
+	PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"),
+	PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"),
+	PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"),
+	PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"),
+	PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"),
+	PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"),
+	PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"),
+	PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"),
+	PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"),
+	PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"),
+	PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"),
+	PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"),
+	PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"),
+	PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"),
+	PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"),
+	PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"),
+	PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"),
+	PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"),
+	PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"),
+	PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"),
+	PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"),
+	PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"),
+	PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"),
+	PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"),
+	PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"),
+	PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"),
+	PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"),
+	PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"),
+	PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"),
+	PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"),
+	PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"),
+	PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"),
+	PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"),
+	PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"),
+	PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"),
+	PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"),
+	PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"),
+	PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"),
+	PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
+};
+
+#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
+			.pin_base = b, .npins = c }
+
+/*
+ * This matches the 32-pin gpio chips registered by the GPIO portion. This
+ * cannot be const since we assign the struct gpio_chip * pointer at runtime.
+ */
+static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
+	STN8815_GPIO_RANGE(0, 0, 32),
+	STN8815_GPIO_RANGE(1, 32, 32),
+	STN8815_GPIO_RANGE(2, 64, 32),
+	STN8815_GPIO_RANGE(3, 96, 28),
+};
+
+/*
+ * Read the pin group names like this:
+ * u0_a_1    = first groups of pins for uart0 on alt function a
+ * i2c2_b_2  = second group of pins for i2c2 on alt function b
+ */
+
+/* Altfunction A */
+static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
+	STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6,
+	STN8815_PIN_C6, STN8815_PIN_B6 };
+static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
+	STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
+	STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
+static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
+					STN8815_PIN_F3, STN8815_PIN_F2 };
+static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
+static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
+/* Altfunction B */
+static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
+static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
+
+#define STN8815_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins,		\
+			.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
+
+static const struct nmk_pingroup nmk_stn8815_groups[] = {
+	STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
+	STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
+	STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
+	STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
+	STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
+	STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
+	STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
+};
+
+/* We use this macro to define the groups applicable to a function */
+#define STN8815_FUNC_GROUPS(a, b...)	   \
+static const char * const a##_groups[] = { b };
+
+STN8815_FUNC_GROUPS(u0, "u0_a_1");
+STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
+STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
+STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
+STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
+STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
+
+#define FUNCTION(fname)					\
+	{						\
+		.name = #fname,				\
+		.groups = fname##_groups,		\
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+static const struct nmk_function nmk_stn8815_functions[] = {
+	FUNCTION(u0),
+	FUNCTION(mmcsd),
+	FUNCTION(u1),
+	FUNCTION(i2c1),
+	FUNCTION(i2c0),
+	FUNCTION(i2cusb),
+};
+
+static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
+	.gpio_ranges = nmk_stn8815_ranges,
+	.gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
+	.pins = nmk_stn8815_pins,
+	.npins = ARRAY_SIZE(nmk_stn8815_pins),
+	.functions = nmk_stn8815_functions,
+	.nfunctions = ARRAY_SIZE(nmk_stn8815_functions),
+	.groups = nmk_stn8815_groups,
+	.ngroups = ARRAY_SIZE(nmk_stn8815_groups),
+};
+
+void __devinit
+nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+{
+	*soc = &nmk_stn8815_soc;
+}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 53b0d49..bee5e52 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1720,6 +1720,8 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
 			of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
 
 	/* Poke in other ASIC variants here */
+	if (version == PINCTRL_NMK_STN8815)
+		nmk_pinctrl_stn8815_init(&npct->soc);
 	if (version == PINCTRL_NMK_DB8500)
 		nmk_pinctrl_db8500_init(&npct->soc);
 
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bc91aed..e10735b 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -61,6 +61,19 @@ struct nmk_pinctrl_soc_data {
 	unsigned ngroups;
 };
 
+#ifdef CONFIG_PINCTRL_STN8815
+
+void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
+
+#else
+
+static inline void
+nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
+{
+}
+
+#endif
+
 #ifdef CONFIG_PINCTRL_DB8500
 
 void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
-- 
1.7.11.2



From jy0922.shim at samsung.com  Thu Aug  9 21:33:50 2012
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 10 Aug 2012 10:33:50 +0900
Subject: [PATCH v3 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
Message-ID: <502464FE.3000908@samsung.com>

Hi, Praveen.

On 08/08/2012 04:40 PM, Praveen Paneri wrote:
> Changes from v2:
> Changed the driver filenames to samsung-usbphy
> Changed 's3c' to 'samsung' for platform device as well as platform data
> Moved platform data structure to a separate file
> Rectified coding style related errors
>
> Changes from v1:
> Rebased patches to latest usb-next branch
> Changed the name 'sec_usbphy' to 'samsung_usbphy'
>
> This patch set introduces a phy driver for samsung SoCs. It uses the existing
> transceiver infrastructure to provide phy control functions. Use of this driver
> can be extended for usb host phy as well.

How can you support usb host phy? I cannot choose to use which phy when
call init or shutdown of phy at current phy framework.

Thanks.

> Over the period of time all the phy
> related code for most of the samsung SoCs can be integrated here.
> Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
> when they start supporting this phy driver.
> This driver is tested with smdk6410 and Exynos4210(with DT).
>
> Praveen Paneri (5):
>    usb: phy: samsung: Introducing usb phy driver for hsotg
>    usb: s3c-hsotg: Adding phy driver support
>    ARM: S3C64XX: Removing old phy setup code
>    ARM: S3C64XX: Enabling samsung-usbphy driver
>    ARM: Exynos4210: Enabling samsung-usbphy driver
>
>   .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>   arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
>   arch/arm/mach-exynos/include/mach/map.h            |    1 +
>   arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
>   arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
>   arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
>   arch/arm/mach-s3c64xx/mach-crag6410.c              |    7 +-
>   arch/arm/mach-s3c64xx/mach-smartq.c                |    8 +-
>   arch/arm/mach-s3c64xx/mach-smdk6410.c              |    7 +-
>   arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
>   arch/arm/plat-samsung/devs.c                       |   33 ++
>   arch/arm/plat-samsung/include/plat/devs.h          |    1 +
>   arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>   drivers/usb/gadget/s3c-hsotg.c                     |   40 ++-
>   drivers/usb/phy/Kconfig                            |    8 +
>   drivers/usb/phy/Makefile                           |    1 +
>   drivers/usb/phy/samsung-usbphy.c                   |  355 ++++++++++++++++++++
>   drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>   include/linux/platform_data/samsung-usbphy.h       |   27 ++
>   19 files changed, 562 insertions(+), 91 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>   create mode 100644 drivers/usb/phy/samsung-usbphy.c
>   create mode 100644 drivers/usb/phy/samsung-usbphy.h
>   create mode 100644 include/linux/platform_data/samsung-usbphy.h
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



From shawn.guo at linaro.org  Thu Aug  9 21:41:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 09:41:22 +0800
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
Message-ID: <20120810014119.GD19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 09:29:39AM -0500, Matt Sealey wrote:
> The reason the new kernel depends on the new U-Boot is we're trying to
> do all pinmux configuration in U-Boot (and we do in-house, and it
> works). No pinctrl stuff in the kernel or device tree is required at
> this point. The Old Kernel will remux a few things redundantly or
> change drive strengths or whatever or add hysteresis to the UART port
> which is not board-burning but is not really necessary, but it will
> work. The new kernel will just be able to do what it does out of the
> box, which is how it should be (hence why I object to adding pinctrl
> setup...)
> 
Then I will have to refuse to accept your patch, because I'm working on
a series to remove pinctrl_provide_dummies() from imx51_dt_init().

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Thu Aug  9 23:12:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 11:12:53 +0800
Subject: [PATCH] ARM: imx/imx31-dt: drop selecting USE_OF
In-Reply-To: <1344519333-6446-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344519333-6446-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120810031251.GE19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 03:35:33PM +0200, Uwe Kleine-K?nig wrote:
> since commit
> 	3e62af8 (ARM: imx: select USE_OF)
> ARM_MXC already selects USE_OF, so there is no need to repeat it for
> MACH_IMX31_DT
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Applied, thanks.

-- 
Regards,
Shawn



From dong.aisheng at linaro.org  Thu Aug  9 23:14:38 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Fri, 10 Aug 2012 11:14:38 +0800
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CAP1dx+y7hjPcCHzfL+Axjz-NK12Vq4YkU_UFcXnKhNP0_UT0vw@mail.gmail.com>

On 10 August 2012 00:23, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> This is mostly cut'n'paste from the imx51 pinctrl driver. The data was
> generated using sed and awk on
> arch/arm/plat-mxc/include/mach/iomux-mx35.h.
>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> Acked-by: Dong Aisheng <dong.aisheng at linaro.org>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> --
> Changes since (implicit) v1,
> id:1343921942-22079-1-git-send-email-u.kleine-koenig at pengutronix.de
>
>  - remove references to file names in binding documentation
>  - remove sed commands from comments in driver
>  - add explicit numbers for pins and functions
>
> @Stephen and Dong: I assumed your ack even though we didn't talk about
> adding numbers for the functions. If you don't like these please scream
> before the patch makes it in :-)
Is that for align with the pin func ids in binding doc?
It looks no harmful, so i'm ok with it.

Regards
Dong Aisheng


From shawn.guo at linaro.org  Thu Aug  9 23:22:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 11:22:20 +0800
Subject: [PATCH] ARM: imx/iomux-v3: allow pad_list to be const
In-Reply-To: <1344527835-32567-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344527835-32567-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120810032217.GF19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 05:57:15PM +0200, Uwe Kleine-K?nig wrote:
> Also fix all machine files to make use of it and while at it also make
> the pad lists __init_const.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> Hello,
> 
> well, iomux-v3 is dying so I don't know how welcome this patch is.
> 
For me, it's not so welcomed at this point, as I have seen it's
patching a bunch of imx5 board files that are scheduled for removal
for this cycle.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Thu Aug  9 23:31:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 11:31:27 +0800
Subject: [PATCH v2] ARM: mxs_defconfig: Add framebuffer support
In-Reply-To: <1344547006-26738-1-git-send-email-festevam@gmail.com>
References: <1344547006-26738-1-git-send-email-festevam@gmail.com>
Message-ID: <20120810033126.GG19617@S2101-09.ap.freescale.net>

On Thu, Aug 09, 2012 at 06:16:46PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Add framebuffer support.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

-- 
Regards,
Shawn



From b32955 at freescale.com  Thu Aug  9 23:18:57 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Fri, 10 Aug 2012 11:18:57 +0800
Subject: [PATCH] mtd: gpmi: add NAND write verify support
Message-ID: <1344568737-902-1-git-send-email-b32955@freescale.com>

Add NAND write verify support in gpmi-nand driver.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 8c0d2f0..6394483 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1488,6 +1488,22 @@ static int gpmi_set_geometry(struct gpmi_nand_data *this)
 	return gpmi_alloc_dma_buffer(this);
 }
 
+#define MAX_PAGESIZE 8192
+static uint8_t verify_buf[MAX_PAGESIZE];
+
+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip *nand = mtd->priv;
+	int ret;
+
+	ret = gpmi_ecc_read_page(mtd, nand, verify_buf, 0, 0);
+	if (ret)
+		return -EFAULT;
+	if (memcmp(buf, verify_buf, len))
+		return -EFAULT;
+	return 0;
+}
+
 static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
 {
 	int ret;
@@ -1556,6 +1572,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 	chip->read_byte		= gpmi_read_byte;
 	chip->read_buf		= gpmi_read_buf;
 	chip->write_buf		= gpmi_write_buf;
+	chip->verify_buf	= gpmi_verify_buf;
 	chip->ecc.read_page	= gpmi_ecc_read_page;
 	chip->ecc.write_page	= gpmi_ecc_write_page;
 	chip->ecc.read_oob	= gpmi_ecc_read_oob;
-- 
1.7.0.4




From festevam at gmail.com  Fri Aug 10 00:12:34 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 10 Aug 2012 01:12:34 -0300
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344568737-902-1-git-send-email-b32955@freescale.com>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
Message-ID: <CAOMZO5AuiquQ2OE6P33AiTmn-qS-EsWhCDY9W+mShzeb-3Rm0g@mail.gmail.com>

On Fri, Aug 10, 2012 at 12:18 AM, Huang Shijie <b32955 at freescale.com> wrote:
> Add NAND write verify support in gpmi-nand driver.
>
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Tested by: Fabio Estevam <fabio.estevam at freescale.com>


From u.kleine-koenig at pengutronix.de  Fri Aug 10 00:45:44 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 10 Aug 2012 06:45:44 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <CAP1dx+y7hjPcCHzfL+Axjz-NK12Vq4YkU_UFcXnKhNP0_UT0vw@mail.gmail.com>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <CAP1dx+y7hjPcCHzfL+Axjz-NK12Vq4YkU_UFcXnKhNP0_UT0vw@mail.gmail.com>
Message-ID: <20120810044544.GH25520@pengutronix.de>

Hello,

On Fri, Aug 10, 2012 at 11:14:38AM +0800, Dong Aisheng wrote:
> On 10 August 2012 00:23, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
> > This is mostly cut'n'paste from the imx51 pinctrl driver. The data was
> > generated using sed and awk on
> > arch/arm/plat-mxc/include/mach/iomux-mx35.h.
> >
> > Cc: Shawn Guo <shawn.guo at linaro.org>
> > Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> > Acked-by: Dong Aisheng <dong.aisheng at linaro.org>
> > Cc: Linus Walleij <linus.walleij at linaro.org>
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > --
> > Changes since (implicit) v1,
> > id:1343921942-22079-1-git-send-email-u.kleine-koenig at pengutronix.de
> >
> >  - remove references to file names in binding documentation
> >  - remove sed commands from comments in driver
> >  - add explicit numbers for pins and functions
> >
> > @Stephen and Dong: I assumed your ack even though we didn't talk about
> > adding numbers for the functions. If you don't like these please scream
> > before the patch makes it in :-)
> Is that for align with the pin func ids in binding doc?
> It looks no harmful, so i'm ok with it.
Yeah, the idea was to make the (more important) mapping also explicit in
the driver to allow for grepping there.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From kgene.kim at samsung.com  Fri Aug 10 00:56:23 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 Aug 2012 13:56:23 +0900
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>

Mark Brown wrote:
> 
> SPI is also connected on the board, use that instead of I2C as it's much
> faster. Also define platform data now the core driver is in mainline.
> 
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  arch/arm/mach-s3c64xx/mach-crag6410-module.c |   35
> ++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-
> s3c64xx/mach-crag6410-module.c
> index f81f089..22dd77b 100644
> --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
> +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
> @@ -192,9 +192,33 @@ static const struct i2c_board_info wm1277_devs[] = {
>  	},
>  };
> 
> -static const struct i2c_board_info wm5102_devs[] = {
> -	{ I2C_BOARD_INFO("wm5102", 0x1a),
> -	  .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, },
> +static struct arizona_pdata wm5102_pdata = {
> +	.ldoena = S3C64XX_GPN(7),
> +	.gpio_base = CODEC_GPIO_BASE,
> +	.irq_active_high = true,
> +	.micd_pol_gpio = CODEC_GPIO_BASE + 4,
> +	.gpio_defaults = {
> +		[2] = 0x10000, /* AIF3TXLRCLK */
> +		[3] = 0x4,     /* OPCLK */
> +	},
> +};

Mark, happens error.

arch/arm/mach-s3c64xx/mach-crag6410-module.c:184: error: variable
'wm5102_pdata' has initializer but incomplete type
arch/arm/mach-s3c64xx/mach-crag6410-module.c:185: error: unknown field
'ldoena' specified in initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:185: warning: excess elements
in struct initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:185: warning: (near
initialization for 'wm5102_pdata')
arch/arm/mach-s3c64xx/mach-crag6410-module.c:186: error: unknown field
'gpio_base' specified in initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:186: warning: excess elements
in struct initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:186: warning: (near
initialization for 'wm5102_pdata')
arch/arm/mach-s3c64xx/mach-crag6410-module.c:187: error: unknown field
'irq_active_high' specified in initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:187: warning: excess elements
in struct initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:187: warning: (near
initialization for 'wm5102_pdata')
arch/arm/mach-s3c64xx/mach-crag6410-module.c:188: error: unknown field
'micd_pol_gpio' specified in initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:188: warning: excess elements
in struct initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:188: warning: (near
initialization for 'wm5102_pdata')
arch/arm/mach-s3c64xx/mach-crag6410-module.c:189: error: unknown field
'gpio_defaults' specified in initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:189: error: extra brace group
at end of initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:189: error: (near
initialization for 'wm5102_pdata')
arch/arm/mach-s3c64xx/mach-crag6410-module.c:192: warning: excess elements
in struct initializer
arch/arm/mach-s3c64xx/mach-crag6410-module.c:192: warning: (near
initialization for 'wm5102_pdata')
make[1]: *** [arch/arm/mach-s3c64xx/mach-crag6410-module.o] Error 1
make: *** [arch/arm/mach-s3c64xx] Error 2
make: *** Waiting for unfinished jobs....

Probably, this patch needs following?

--
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index c148384..7f4f9eb 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -16,6 +16,7 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
 #include <linux/mfd/wm8994/pdata.h>
+#include <linux/mfd/arizona/pdata.h>

 #include <linux/regulator/machine.h>
--

If you're ok, I will fix build error by above when I apply.

[...]

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From u.kleine-koenig at pengutronix.de  Fri Aug 10 01:12:00 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 10 Aug 2012 07:12:00 +0200
Subject: [PATCH] ARM: imx/iomux-v3: allow pad_list to be const
In-Reply-To: <20120810032217.GF19617@S2101-09.ap.freescale.net>
References: <1344527835-32567-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120810032217.GF19617@S2101-09.ap.freescale.net>
Message-ID: <20120810051200.GI25520@pengutronix.de>

Hello Shawn,

On Fri, Aug 10, 2012 at 11:22:20AM +0800, Shawn Guo wrote:
> On Thu, Aug 09, 2012 at 05:57:15PM +0200, Uwe Kleine-K?nig wrote:
> > Also fix all machine files to make use of it and while at it also make
> > the pad lists __init_const.
> > 
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > ---
> > Hello,
> > 
> > well, iomux-v3 is dying so I don't know how welcome this patch is.
> > 
> For me, it's not so welcomed at this point, as I have seen it's
> patching a bunch of imx5 board files that are scheduled for removal
> for this cycle.
I can resend with the respective board files dropped when your changes
hit next.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From shawn.guo at linaro.org  Fri Aug 10 01:13:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 13:13:58 +0800
Subject: [PATCH] ARM: imx/iomux-v3: allow pad_list to be const
In-Reply-To: <20120810051200.GI25520@pengutronix.de>
References: <1344527835-32567-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120810032217.GF19617@S2101-09.ap.freescale.net>
 <20120810051200.GI25520@pengutronix.de>
Message-ID: <CAAQ0ZWQp3ZDriTGNkX9OxtE4bTOPox-c9_ZeLkDH58JLa6SNOQ@mail.gmail.com>

On 10 August 2012 13:12, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> I can resend with the respective board files dropped when your changes
> hit next.
>
Sounds good.  Thanks, Uwe.

Regards,
Shawn


From shawn.guo at linaro.org  Fri Aug 10 01:37:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 13:37:22 +0800
Subject: [PATCH v3 0/3] Add a generic cpufreq-cpu0 driver
Message-ID: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>

Patch "cpufreq: Add a generic cpufreq-cpu0 driver" has a dependency
on following branch.

 git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git topic/tol

Changes since v2:
* Drop patch "regulator: add a new API regulator_set_voltage_tol()",
  which has been applied on regulator tree as above.
* Rewrite function of_init_opp_table to make it concise.
  
Regards,
Shawn

Richard Zhao (1):
  ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp

Shawn Guo (2):
  PM / OPP: Initialize OPP table from device tree
  cpufreq: Add a generic cpufreq-cpu0 driver

 .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |   55 ++++
 Documentation/devicetree/bindings/power/opp.txt    |   25 ++
 arch/arm/kernel/smp.c                              |   54 ++++
 drivers/base/power/opp.c                           |   47 ++++
 drivers/cpufreq/Kconfig                            |   11 +
 drivers/cpufreq/Makefile                           |    2 +
 drivers/cpufreq/cpufreq-cpu0.c                     |  271 ++++++++++++++++++++
 include/linux/opp.h                                |    8 +
 8 files changed, 473 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 create mode 100644 Documentation/devicetree/bindings/power/opp.txt
 create mode 100644 drivers/cpufreq/cpufreq-cpu0.c

-- 
1.7.5.4




From shawn.guo at linaro.org  Fri Aug 10 01:37:23 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 13:37:23 +0800
Subject: [PATCH v3 1/3] ARM: add cpufreq transiton notifier to adjust
 loops_per_jiffy for smp
In-Reply-To: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344577046-14847-2-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

If CONFIG_SMP, cpufreq skips loops_per_jiffy update, because different
arch has different per-cpu loops_per_jiffy definition.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Acked-by: Russell King <rmk+kernel at arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/kernel/smp.c |   54 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..8e03567 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -25,6 +25,7 @@
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/completion.h>
+#include <linux/cpufreq.h>
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
@@ -584,3 +585,56 @@ int setup_profiling_timer(unsigned int multiplier)
 {
 	return -EINVAL;
 }
+
+#ifdef CONFIG_CPU_FREQ
+
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
+static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
+static unsigned long global_l_p_j_ref;
+static unsigned long global_l_p_j_ref_freq;
+
+static int cpufreq_callback(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freq = data;
+	int cpu = freq->cpu;
+
+	if (freq->flags & CPUFREQ_CONST_LOOPS)
+		return NOTIFY_OK;
+
+	if (!per_cpu(l_p_j_ref, cpu)) {
+		per_cpu(l_p_j_ref, cpu) =
+			per_cpu(cpu_data, cpu).loops_per_jiffy;
+		per_cpu(l_p_j_ref_freq, cpu) = freq->old;
+		if (!global_l_p_j_ref) {
+			global_l_p_j_ref = loops_per_jiffy;
+			global_l_p_j_ref_freq = freq->old;
+		}
+	}
+
+	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
+	    (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+	    (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
+		loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
+						global_l_p_j_ref_freq,
+						freq->new);
+		per_cpu(cpu_data, cpu).loops_per_jiffy =
+			cpufreq_scale(per_cpu(l_p_j_ref, cpu),
+					per_cpu(l_p_j_ref_freq, cpu),
+					freq->new);
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block cpufreq_notifier = {
+	.notifier_call  = cpufreq_callback,
+};
+
+static int __init register_cpufreq_notifier(void)
+{
+	return cpufreq_register_notifier(&cpufreq_notifier,
+						CPUFREQ_TRANSITION_NOTIFIER);
+}
+core_initcall(register_cpufreq_notifier);
+
+#endif
-- 
1.7.5.4




From shawn.guo at linaro.org  Fri Aug 10 01:37:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 13:37:24 +0800
Subject: [PATCH v3 2/3] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344577046-14847-3-git-send-email-shawn.guo@linaro.org>

With a lot of devices booting from device tree nowadays, it requires
that OPP table can be initialized from device tree.  The patch adds
a helper function of_init_opp_table together with a binding doc for
that purpose.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 Documentation/devicetree/bindings/power/opp.txt |   25 ++++++++++++
 drivers/base/power/opp.c                        |   47 +++++++++++++++++++++++
 include/linux/opp.h                             |    8 ++++
 3 files changed, 80 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/power/opp.txt

diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt
new file mode 100644
index 0000000..74499e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/opp.txt
@@ -0,0 +1,25 @@
+* Generic OPP Interface
+
+SoCs have a standard set of tuples consisting of frequency and
+voltage pairs that the device will support per voltage domain. These
+are called Operating Performance Points or OPPs.
+
+Properties:
+- operating-points: An array of 2-tuples items, and each item consists
+  of frequency and voltage like <freq-kHz vol-uV>.
+	freq: clock frequency in kHz
+	vol: voltage in microvolt
+
+Examples:
+
+cpu at 0 {
+	compatible = "arm,cortex-a9";
+	reg = <0>;
+	next-level-cache = <&L2>;
+	operating-points = <
+		/* kHz    uV */
+		792000  1100000
+		396000  950000
+		198000  850000
+	>;
+};
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index ac993ea..d946864 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -22,6 +22,7 @@
 #include <linux/rculist.h>
 #include <linux/rcupdate.h>
 #include <linux/opp.h>
+#include <linux/of.h>
 
 /*
  * Internal data structure organization with the OPP layer library is as
@@ -674,3 +675,49 @@ struct srcu_notifier_head *opp_get_notifier(struct device *dev)
 
 	return &dev_opp->head;
 }
+
+#ifdef CONFIG_OF
+/**
+ * of_init_opp_table() - Initialize opp table from device tree
+ * @dev:	device pointer used to lookup device OPPs.
+ *
+ * Register the initial OPP table with the OPP library for given device.
+ */
+int of_init_opp_table(struct device *dev)
+{
+	const struct property *prop;
+	const __be32 *val;
+	int nr;
+
+	prop = of_find_property(dev->of_node, "operating-points", NULL);
+	if (!prop)
+		return -ENODEV;
+	if (!prop->value)
+		return -ENODATA;
+
+	/*
+	 * Each OPP is a set of tuples consisting of frequency and
+	 * voltage like <freq-kHz vol-uV>.
+	 */
+	nr = prop->length / sizeof(u32);
+	if (nr % 2) {
+		dev_err(dev, "%s: Invalid OPP list\n", __func__);
+		return -EINVAL;
+	}
+
+	val = prop->value;
+	while (nr) {
+		unsigned long freq = be32_to_cpup(val++) * 1000;
+		unsigned long volt = be32_to_cpup(val++);
+
+		if (opp_add(dev, freq, volt)) {
+			dev_warn(dev, "%s: Failed to add OPP %ld\n",
+				 __func__, freq);
+			continue;
+		}
+		nr -= 2;
+	}
+
+	return 0;
+}
+#endif
diff --git a/include/linux/opp.h b/include/linux/opp.h
index 2a4e5fa..214e0eb 100644
--- a/include/linux/opp.h
+++ b/include/linux/opp.h
@@ -48,6 +48,14 @@ int opp_disable(struct device *dev, unsigned long freq);
 
 struct srcu_notifier_head *opp_get_notifier(struct device *dev);
 
+#ifdef CONFIG_OF
+int of_init_opp_table(struct device *dev);
+#else
+static inline int of_init_opp_table(struct device *dev)
+{
+	return -EINVAL;
+}
+#endif /* CONFIG_OF */
 #else
 static inline unsigned long opp_get_voltage(struct opp *opp)
 {
-- 
1.7.5.4




From shawn.guo at linaro.org  Fri Aug 10 01:37:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 13:37:25 +0800
Subject: [PATCH v3 3/3] cpufreq: Add a generic cpufreq-cpu0 driver
In-Reply-To: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344577046-14847-4-git-send-email-shawn.guo@linaro.org>

It adds a generic cpufreq driver for CPU0 frequency management based on
clk, regulator, OPP and device tree support.  It can support both
uniprocessor (UP) and those symmetric multiprocessor (SMP) systems which
share clock and voltage across all CPUs.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |   55 ++++
 drivers/cpufreq/Kconfig                            |   11 +
 drivers/cpufreq/Makefile                           |    2 +
 drivers/cpufreq/cpufreq-cpu0.c                     |  271 ++++++++++++++++++++
 4 files changed, 339 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
 create mode 100644 drivers/cpufreq/cpufreq-cpu0.c

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
new file mode 100644
index 0000000..4416ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
@@ -0,0 +1,55 @@
+Generic CPU0 cpufreq driver
+
+It is a generic cpufreq driver for CPU0 frequency management.  It
+supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+systems which share clock and voltage across all CPUs.
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu at 0.
+
+Required properties:
+- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
+  for details
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+  in unit of nanoseconds.
+- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
+
+Examples:
+
+cpus {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpu at 0 {
+		compatible = "arm,cortex-a9";
+		reg = <0>;
+		next-level-cache = <&L2>;
+		operating-points = <
+			/* kHz    uV */
+			792000  1100000
+			396000  950000
+			198000  850000
+		>;
+		transition-latency = <61036>; /* two CLK32 periods */
+	};
+
+	cpu at 1 {
+		compatible = "arm,cortex-a9";
+		reg = <1>;
+		next-level-cache = <&L2>;
+	};
+
+	cpu at 2 {
+		compatible = "arm,cortex-a9";
+		reg = <2>;
+		next-level-cache = <&L2>;
+	};
+
+	cpu at 3 {
+		compatible = "arm,cortex-a9";
+		reg = <3>;
+		next-level-cache = <&L2>;
+	};
+};
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index e24a2a1..ea512f4 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -179,6 +179,17 @@ config CPU_FREQ_GOV_CONSERVATIVE
 
 	  If in doubt, say N.
 
+config GENERIC_CPUFREQ_CPU0
+	bool "Generic CPU0 cpufreq driver"
+	depends on HAVE_CLK && REGULATOR && PM_OPP && OF
+	select CPU_FREQ_TABLE
+	help
+	  This adds a generic cpufreq driver for CPU0 frequency management.
+	  It supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+	  systems which share clock and voltage across all CPUs.
+
+	  If in doubt, say N.
+
 menu "x86 CPU frequency scaling drivers"
 depends on X86
 source "drivers/cpufreq/Kconfig.x86"
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 9531fc2..a378ed2 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE)	+= cpufreq_conservative.o
 # CPUfreq cross-arch helpers
 obj-$(CONFIG_CPU_FREQ_TABLE)		+= freq_table.o
 
+obj-$(CONFIG_GENERIC_CPUFREQ_CPU0)	+= cpufreq-cpu0.o
+
 ##################################################################################
 # x86 drivers.
 # Link order matters. K8 is preferred to ACPI because of firmware bugs in early
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
new file mode 100644
index 0000000..fd3bac6
--- /dev/null
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Reuse some codes from drivers/cpufreq/omap-cpufreq.c
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+static unsigned int transition_latency;
+static unsigned int voltage_tolerance; /* in percentage */
+
+static struct device *cpu_dev;
+static struct clk *cpu_clk;
+static struct regulator *cpu_reg;
+static struct cpufreq_frequency_table *freq_table;
+
+static int cpu0_verify_speed(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static unsigned int cpu0_get_speed(unsigned int cpu)
+{
+	return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int cpu0_set_target(struct cpufreq_policy *policy,
+			   unsigned int target_freq, unsigned int relation)
+{
+	struct cpufreq_freqs freqs;
+	struct opp *opp;
+	unsigned long freq_Hz, volt = 0, volt_old = 0, tol = 0;
+	unsigned int index, cpu;
+	int ret;
+
+	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+					     relation, &index);
+	if (ret) {
+		pr_err("failed to match target freqency %d: %d\n",
+		       target_freq, ret);
+		return ret;
+	}
+
+	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
+	if (freq_Hz < 0)
+		freq_Hz = freq_table[index].frequency * 1000;
+	freqs.new = freq_Hz / 1000;
+	freqs.old = clk_get_rate(cpu_clk) / 1000;
+
+	if (freqs.old == freqs.new)
+		return 0;
+
+	for_each_online_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+	}
+
+	if (cpu_reg) {
+		opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
+		if (IS_ERR(opp)) {
+			pr_err("failed to find OPP for %ld\n", freq_Hz);
+			return PTR_ERR(opp);
+		}
+		volt = opp_get_voltage(opp);
+		tol = volt * voltage_tolerance / 100;
+		volt_old = regulator_get_voltage(cpu_reg);
+	}
+
+	pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
+		 freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
+		 freqs.new / 1000, volt ? volt / 1000 : -1);
+
+	/* scaling up?  scale voltage before frequency */
+	if (cpu_reg && freqs.new > freqs.old) {
+		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
+		if (ret) {
+			pr_err("failed to scale voltage up: %d\n", ret);
+			freqs.new = freqs.old;
+			return ret;
+		}
+	}
+
+	ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+	if (ret) {
+		pr_err("failed to set clock rate: %d\n", ret);
+		if (cpu_reg)
+			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
+		return ret;
+	}
+
+	/* scaling down?  scale voltage after frequency */
+	if (cpu_reg && freqs.new < freqs.old) {
+		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
+		if (ret) {
+			pr_err("failed to scale voltage down: %d\n", ret);
+			clk_set_rate(cpu_clk, freqs.old * 1000);
+			freqs.new = freqs.old;
+			return ret;
+		}
+	}
+
+	for_each_online_cpu(cpu) {
+		freqs.cpu = cpu;
+		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	}
+
+	return 0;
+}
+
+static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
+{
+	int ret;
+
+	if (policy->cpu != 0)
+		return -EINVAL;
+
+	ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+	if (ret) {
+		pr_err("invalid frequency table: %d\n", ret);
+		return ret;
+	}
+
+	policy->cpuinfo.transition_latency = transition_latency;
+	policy->cur = clk_get_rate(cpu_clk) / 1000;
+
+	/*
+	 * The driver only supports the SMP configuartion where all processors
+	 * share the clock and voltage and clock.  Use cpufreq affected_cpus
+	 * interface to have all CPUs scaled together.
+	 */
+	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
+	cpumask_setall(policy->cpus);
+
+	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+
+	return 0;
+}
+
+static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
+{
+	cpufreq_frequency_table_put_attr(policy->cpu);
+
+	return 0;
+}
+
+static struct freq_attr *cpu0_cpufreq_attr[] = {
+	&cpufreq_freq_attr_scaling_available_freqs,
+	NULL,
+};
+
+static struct cpufreq_driver cpu0_cpufreq_driver = {
+	.flags = CPUFREQ_STICKY,
+	.verify = cpu0_verify_speed,
+	.target = cpu0_set_target,
+	.get = cpu0_get_speed,
+	.init = cpu0_cpufreq_init,
+	.exit = cpu0_cpufreq_exit,
+	.name = "generic_cpu0",
+	.attr = cpu0_cpufreq_attr,
+};
+
+static int __devinit cpu0_cpufreq_driver_init(void)
+{
+	struct device_node *np;
+	int ret;
+
+	np = of_find_node_by_path("/cpus/cpu at 0");
+	if (!np) {
+		pr_err("failed to find cpu0 node\n");
+		return -ENOENT;
+	}
+
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev) {
+		pr_err("failed to get cpu0 device\n");
+		ret = -ENODEV;
+		goto out_put_node;
+	}
+
+	cpu_dev->of_node = np;
+
+	cpu_clk = clk_get(cpu_dev, NULL);
+	if (IS_ERR(cpu_clk)) {
+		ret = PTR_ERR(cpu_clk);
+		pr_err("failed to get cpu0 clock: %d\n", ret);
+		goto out_put_node;
+	}
+
+	cpu_reg = regulator_get(cpu_dev, "cpu0");
+	if (IS_ERR(cpu_reg)) {
+		pr_warn("failed to get cpu0 regulator\n");
+		cpu_reg = NULL;
+	}
+
+	ret = of_init_opp_table(cpu_dev);
+	if (ret) {
+		pr_err("failed to init OPP table: %d\n", ret);
+		goto out_put_node;
+	}
+
+	ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
+	if (ret) {
+		pr_err("failed to init cpufreq table: %d\n", ret);
+		goto out_put_node;
+	}
+
+	of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
+
+	if (of_property_read_u32(np, "clock-latency", &transition_latency))
+		transition_latency = CPUFREQ_ETERNAL;
+
+	if (cpu_reg) {
+		struct opp *opp;
+		unsigned long min_uV, max_uV;
+		int i;
+
+		/*
+		 * OPP is maintained in order of increasing frequency, and
+		 * freq_table initialised from OPP is therefore sorted in the
+		 * same order.
+		 */
+		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
+			;
+		opp = opp_find_freq_exact(cpu_dev,
+				freq_table[0].frequency * 1000, true);
+		min_uV = opp_get_voltage(opp);
+		opp = opp_find_freq_exact(cpu_dev,
+				freq_table[i-1].frequency * 1000, true);
+		max_uV = opp_get_voltage(opp);
+		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
+		if (ret > 0)
+			transition_latency += ret * 1000;
+	}
+
+	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
+	if (ret) {
+		pr_err("failed register driver: %d\n", ret);
+		goto out_free_table;
+	}
+
+	of_node_put(np);
+	return 0;
+
+out_free_table:
+	opp_free_cpufreq_table(cpu_dev, &freq_table);
+out_put_node:
+	of_node_put(np);
+	return ret;
+}
+late_initcall(cpu0_cpufreq_driver_init);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
1.7.5.4




From p.paneri at samsung.com  Fri Aug 10 01:47:29 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 11:17:29 +0530
Subject: [PATCH v3 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <502464FE.3000908@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <502464FE.3000908@samsung.com>
Message-ID: <CAD6zSYP33PDrXwifQM=7q+Esk1X7m5+DNG_=A2a-qTENk4zq8w@mail.gmail.com>

On Fri, Aug 10, 2012 at 7:03 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> Hi, Praveen.
>
>
> On 08/08/2012 04:40 PM, Praveen Paneri wrote:
>>
>> Changes from v2:
>> Changed the driver filenames to samsung-usbphy
>> Changed 's3c' to 'samsung' for platform device as well as platform data
>> Moved platform data structure to a separate file
>> Rectified coding style related errors
>>
>> Changes from v1:
>> Rebased patches to latest usb-next branch
>> Changed the name 'sec_usbphy' to 'samsung_usbphy'
>>
>> This patch set introduces a phy driver for samsung SoCs. It uses the
>> existing
>> transceiver infrastructure to provide phy control functions. Use of this
>> driver
>> can be extended for usb host phy as well.
>
>
> How can you support usb host phy? I cannot choose to use which phy when
> call init or shutdown of phy at current phy framework.
If you are talking about choosing between PHY0 (for device) and PHY1
(for host), I think you can make use of the flags available in usb_phy
to pass that information to phy driver and that can be handled there.
This is just one way I have successfully implement two different phy
control. There might be a better way to do that.

Thanks
Praveen
>
> Thanks.
>
>> Over the period of time all the phy
>> related code for most of the samsung SoCs can be integrated here.
>> Removing the existing phy code from mach-s3c64xx. Same can be done for
>> other SoCs
>> when they start supporting this phy driver.
>> This driver is tested with smdk6410 and Exynos4210(with DT).
>>
>> Praveen Paneri (5):
>>    usb: phy: samsung: Introducing usb phy driver for hsotg
>>    usb: s3c-hsotg: Adding phy driver support
>>    ARM: S3C64XX: Removing old phy setup code
>>    ARM: S3C64XX: Enabling samsung-usbphy driver
>>    ARM: Exynos4210: Enabling samsung-usbphy driver
>>
>>   .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>   arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
>>   arch/arm/mach-exynos/include/mach/map.h            |    1 +
>>   arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
>>   arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
>>   arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
>>   arch/arm/mach-s3c64xx/mach-crag6410.c              |    7 +-
>>   arch/arm/mach-s3c64xx/mach-smartq.c                |    8 +-
>>   arch/arm/mach-s3c64xx/mach-smdk6410.c              |    7 +-
>>   arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
>>   arch/arm/plat-samsung/devs.c                       |   33 ++
>>   arch/arm/plat-samsung/include/plat/devs.h          |    1 +
>>   arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>>   drivers/usb/gadget/s3c-hsotg.c                     |   40 ++-
>>   drivers/usb/phy/Kconfig                            |    8 +
>>   drivers/usb/phy/Makefile                           |    1 +
>>   drivers/usb/phy/samsung-usbphy.c                   |  355
>> ++++++++++++++++++++
>>   drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>>   include/linux/platform_data/samsung-usbphy.h       |   27 ++
>>   19 files changed, 562 insertions(+), 91 deletions(-)
>>   create mode 100644
>> Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>   create mode 100644 drivers/usb/phy/samsung-usbphy.c
>>   create mode 100644 drivers/usb/phy/samsung-usbphy.h
>>   create mode 100644 include/linux/platform_data/samsung-usbphy.h
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From mrosenberg at mozilla.com  Fri Aug 10 01:52:29 2012
From: mrosenberg at mozilla.com (Martin Rosenberg)
Date: Thu, 9 Aug 2012 22:52:29 -0700 (PDT)
Subject: Discontiguous memory and cacheflush
In-Reply-To: <447177957.1189939.1344577602635.JavaMail.root@mozilla.com>
Message-ID: <1613427331.1190769.1344577949008.JavaMail.root@mozilla.com>

A couple of days ago, I started a project to coalesce calls to cachefush in mozilla's JIT.  After working out most of the bugs that I could find, there were still some lingering failures, which I believe finally tracked down to do_cache_op, where it looks like only the first contiguous region of virtual memory is consulted.  I don't actually know about any of the functions that are being called, nor exactly what the datastructures represent, but if my understanding of the code is correct, then it is at odds with the documentation that is available (namely, man cacheflush(2)).  Is there something I've overlooked, any suggested workarounds?  Thanks --Marty


From kgene.kim at samsung.com  Fri Aug 10 02:07:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 Aug 2012 15:07:37 +0900
Subject: [PATCH 08/10] ARM: s3c24xx: enable CONFIG_BUG for tct_hammer
In-Reply-To: <1344461278-28245-9-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-9-git-send-email-arnd@arndb.de>
Message-ID: <0dd301cd76be$7101a750$5304f5f0$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> Disabling CONFIG_BUG creates an insane amount of build warnings, which
> makes it useless to check for building defconfigs to see if new
> warnings show up.
> 
> Without this patch, building tct_hammer_defconfig results in:
> 
> net/packet/af_packet.c: In function 'tpacket_rcv':
> net/packet/af_packet.c:1889:30: warning: 'hdrlen' may be used
> uninitialized in this function [-Wuninitialized]
> net/core/ethtool.c: In function 'ethtool_get_feature_mask':
> net/core/ethtool.c:213:1: warning: control reaches end of non-void
> function [-Wreturn-type]
> block/cfq-iosched.c: In function 'cfq_async_queue_prio':
> block/cfq-iosched.c:2914:1: warning: control reaches end of non-void
> function [-Wreturn-type]
> mm/bootmem.c: In function 'mark_bootmem':
> mm/bootmem.c:352:1: warning: control reaches end of non-void function [-
> Wreturn-type]
> net/core/dev.c: In function 'skb_warn_bad_offload':
> net/core/dev.c:1904:33: warning: unused variable 'null_features' [-
> Wunused-variable]
> drivers/mtd/chips/cfi_probe.c: In function 'cfi_chip_setup':
> include/linux/mtd/cfi.h:489:3: warning: 'r.x[0]' may be used uninitialized
> in this function [-Wuninitialized]
> include/linux/mtd/map.h:394:11: note: 'r.x[0]' was declared here
> include/linux/mtd/cfi.h:489:3: warning: 'r.x[0]' may be used uninitialized
> in this function [-Wuninitialized]
> (and many more)
> 
> The size of vmlinux increases by 1.78% because of this:
> 
> size obj-arm/vmlinux.nobug
>    text    data     bss     dec     hex filename
>    2108474  116916   55352 2280742  22cd26 obj-arm/vmlinux
> size obj-arm/vmlinux.bug
>    text    data     bss     dec     hex filename
>    2150804  116916   53696 2321416  236c08 obj-arm/vmlinux
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Kukjin Kim <kgene.kim at samsung.com>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

BTW, I'm not sure we should still keep the tct_hammer_defconfig because
s3c2410_defconfig is including MACH_TCT_HAMMER, its selection are different
though.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> Cc: Ben Dooks <ben-linux at fluff.org>
> ---
>  arch/arm/configs/tct_hammer_defconfig |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/configs/tct_hammer_defconfig
> b/arch/arm/configs/tct_hammer_defconfig
> index 1d24f84..71277a1 100644
> --- a/arch/arm/configs/tct_hammer_defconfig
> +++ b/arch/arm/configs/tct_hammer_defconfig
> @@ -7,7 +7,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y
>  CONFIG_BLK_DEV_INITRD=y
>  CONFIG_EXPERT=y
>  # CONFIG_KALLSYMS is not set
> -# CONFIG_BUG is not set
> +# CONFIG_BUGVERBOSE is not set
>  # CONFIG_ELF_CORE is not set
>  # CONFIG_SHMEM is not set
>  CONFIG_SLOB=y
> --
> 1.7.10



From tarun.kanti at ti.com  Fri Aug 10 02:08:56 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Fri, 10 Aug 2012 11:38:56 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <87hascgli3.fsf@ti.com>
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
 <87k3x9wbrk.fsf@ti.com>
 <CAC83ZvLKk71O=+9U16FoTUU_-ffg+iJsHPgnJx+bzbHhBDXzhQ@mail.gmail.com>
 <87hascgli3.fsf@ti.com>
Message-ID: <CAC83Zv++4CO_0xsNbwMYX_5uEv56csprqrrCjshxfb+ay2gBQg@mail.gmail.com>

On Thu, Aug 9, 2012 at 8:28 PM, Kevin Hilman <khilman at ti.com> wrote:
> "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
>
>> On Wed, Aug 8, 2012 at 10:40 PM, Kevin Hilman <khilman at ti.com> wrote:
>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>
>>>> Add *remove* callback so that necessary cleanup operations are
>>>> performed when device is unregistered. The device is deleted
>>>> from the list and associated clock handle is released by
>>>> calling clk_put() and irq descriptor is released using the
>>>> irq_free_desc() api.
>>>>
>>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>>> Reported-by: Paul Walmsley <paul at pwsan.com>
>>>> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
>>>> Cc: Kevin Hilman <khilman at ti.com>
>>>> Cc: Rajendra Nayak <rnayak at ti.com>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>>> Cc: Cousson, Benoit <b-cousson at ti.com>
>>>> Cc: Paul Walmsley <paul at pwsan.com>
>>>> ---
>>>> v2:
>>>> Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>>>> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
>>>>
>>>> (1) Use irq_free_descs() instead of irq_free_desc().
>>>>     Besides, irq_free_desc() was using wrong parameter,
>>>>     irq_base, instead of bank->irq.
>>>> (2) irq_free_descs() moved outside spin_lock/unlock_*()
>>>>     in order to avoid exception warnings.
>>>>
>>>> (3) pm_runtime_disable() added so that bind can happen successfully
>>>>
>>>> Test Detail:
>>>> Step 1: Unbind gpio.5 device in order to invoke the *remove* callback.
>>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
>>>>
>>>> Step 2: Bind gpio.5 device and confirm probe() for the device succeeds.
>>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
>>>>
>>>> Step 3: Execute read/write GPIO test case.
>>>
>>> What happens when GPIOs are in use (requested)?
>> If I try to unbind a currently active GPIO bank then I see an exception
>> after the irq descriptor is freed by the remove. I believe this is expected
>> because interrupt raised by the system would not be handled.
>
> ... and the GPIO is still configured to trigger interrupts.
Right!

>
> The point is that there is lots to cleanup/unconfigure properly for this
> to work properly.
As far as I can think of, all active gpio requests done either in
board files or through DT
have to be freed. But if this is done then when we bind() the device
again initialization
done in omap_gpio_probe() would not restore the board/DT related configuration.
So the point is are we supposed to do all these cleanup in *remove* callback?
If yes, how do we manage board level gpio usage?
---
Tarun
>
> Kevin
>
>> [   18.859405] irq_free_descs: calling free_desc(192)...
>> [   18.866180] irq_free_descs: calling free_desc(192)...
>> [   18.872680] irq_free_descs: calling free_desc(192)...
>> [   18.877990] irq_free_descs: calling free_desc(192)...
>> [   18.883270] irq_free_descs: calling free_desc(192)...
>> [   18.888549] irq_free_descs: calling free_desc(192)...
>> [   18.893859] irq_free_descs: calling free_desc(192)...
>> [   18.899139] irq_free_descs: calling free_desc(192)...
>> [   18.904418] irq_free_descs: calling free_desc(192)...
>> [   18.909729] irq_free_descs: calling free_desc(192)...
>> [   18.915008] irq_free_descs: calling free_desc(192)...
>> [   18.920288] irq_free_descs: calling free_desc(192)...
>> [   18.925598] irq_free_descs: calling free_desc(192)...
>> [   18.930877] irq_free_descs: calling free_desc(192)...
>> [   18.936157] irq_free_descs: calling free_desc(192)...
>> [   18.941467] irq_free_descs: calling free_desc(192)...
>> [   18.946746] irq_free_descs: calling free_desc(192)...
>> [   18.952026] irq_free_descs: calling free_desc(192)...
>> [   18.957336] irq_free_descs: calling free_desc(192)...
>> [   18.962615] irq_free_descs: calling free_desc(192)...
>> [   18.967895] irq_free_descs: calling free_desc(192)...
>> [   18.973205] irq_free_descs: calling free_desc(192)...
>> [   18.978485] irq_free_descs: calling free_desc(192)...
>> [   18.983764] irq_free_descs: calling free_desc(192)...
>> [   18.989074] irq_free_descs: calling free_desc(192)...
>> [   18.994354] irq_free_descs: calling free_desc(192)...
>> [   18.999633] irq_free_descs: calling free_desc(192)...
>> [   19.004913] irq_free_descs: calling free_desc(192)...
>> [   19.010223] irq_free_descs: calling free_desc(192)...
>> [   19.015502] irq_free_descs: calling free_desc(192)...
>> [   19.020782] irq_free_descs: calling free_desc(192)...
>> [   19.026092] irq_free_descs: calling free_desc(192)...
>> [   19.032440] irq 194, desc: c072f340, depth: 1, count: 0, unhandled: 0
>> [   19.039154] ->handle_irq():  c00a3e08, handle_bad_irq+0x0/0x260
>> [   19.045379] ->irq_data.chip(): c078ff7c, no_irq_chip+0x0/0x5c
>> [   19.051391] ->action(): ef0d42c0
>> [   19.054748] ->action->handler(): c0399ee0, ks8851_irq+0x0/0x1c
>> [   19.060852]    IRQ_NOPROBE set
>> [   19.064056]  IRQ_NOREQUEST set
>> [   19.067230] Unable to handle kernel paging request at virtual address 203a6c9
>> [   19.074768] pgd = c0004000
>> [   19.077606] [203a6c99] *pgd=00000000
>> [   19.081329] Internal error: Oops: 5 [#1] SMP ARM
>> [   19.086151] Modules linked in:
>> [   19.089355] CPU: 0    Not tainted  (3.6.0-rc1-00003-g43a916d-dirty #885)
>> [   19.096374] PC is at gpio_irq_handler+0x7c/0x26c
>> [   19.101165] LR is at handle_bad_irq+0x1cc/0x260
>> [   19.105895] pc : [<c02e13b0>]    lr : [<c00a3fd4>]    psr: 60000093
>> [   19.105895] sp : c0725df8  ip : 00006fc6  fp : 00000001
>> [   19.117889] r10: 00000000  r9 : fa05502c  r8 : 00000020
>> [   19.123352] r7 : 00000000  r6 : 00000000  r5 : 00000000  r4 : ef0bbe10
>> [   19.130157] r3 : ef0c1980  r2 : 203a6c65  r1 : 00000034  r0 : 00000000
>> [   19.136993] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kel
>> [   19.144714] Control: 10c53c7d  Table: ae89804a  DAC: 00000017
>> [   19.150695] Process swapper/0 (pid: 0, stack limit = 0xc07242f8)
>> [   19.156982] Stack: (0xc0725df8 to 0xc0726000)
>> [   19.161529] 5de0:                                                       c0740
>> [   19.170074] 5e00: c0724000 c0724000 c07440d8 c07224a4 0000003e 00000000 c0740
>> [   19.178619] 5e20: c0725edc c00a3670 000001da c0015380 fa24010c c0742d30 c0720
>> [   19.187164] 5e40: 00000001 c000846c c0746980 c04f8c74 20000013 ffffffff c0724
>> [   19.195709] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
>> [   19.204223] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
>> [   19.212768] 5ea0: 20000013 ffffffff c0724000 c007425c 00000002 00000000 c0077
>> [   19.221313] 5ec0: ef320b00 c0746980 00000000 c1530ac0 ef320b00 c0722ac0 c0720
>> [   19.229858] 5ee0: c152ec20 c00696cc 00000000 00000000 c0724000 c0724000 c1524
>> [   19.238403] 5f00: c152ec20 c0015e14 c0722ac0 c0722ac0 c0722ac0 c0722ac0 c0720
>> [   19.246948] 5f20: c0722ac0 c0722ac0 6e6b0f0d 00000004 00000000 00000000 c0080
>> [   19.255493] 5f40: 00000001 00000000 00000000 501539bc 00000004 c0091654 c1528
>> [   19.264038] 5f60: c07d55b8 5006c071 00000000 c008cab8 00000000 00000002 50064
>> [   19.272552] 5f80: c0748078 c0724000 c07c0548 c0504510 c0747e60 00000000 411f8
>> [   19.281097] 5fa0: 00000000 c0015e14 00000000 c0743e1c c07c0480 c07057dc bfffa
>> [   19.289642] 5fc0: 00000000 c06d48d8 ffffffff ffffffff c06d4450 00000000 0000c
>> [   19.298187] 5fe0: 00000000 10c53c7d c0742d08 c07057ac c0747e54 80008044 00000
>> [   19.306732] [<c02e13b0>] (gpio_irq_handler+0x7c/0x26c) from [<c00a3670>] (ge)
>> [   19.316558] [<c00a3670>] (generic_handle_irq+0x34/0x44) from [<c0015380>] (h)
>> [   19.325744] [<c0015380>] (handle_IRQ+0x4c/0xac) from [<c000846c>] (gic_handl)
>> [   19.334564] [<c000846c>] (gic_handle_irq+0x2c/0x60) from [<c04f8ee4>] (__irq)
>> [   19.343292] Exception stack(0xc0725e60 to 0xc0725ea8)
>> [   19.348571] 5e60: 0005ebb2 00000001 00000000 c0746980 c1530ac0 ee8cfe00 c1530
>> [   19.357116] 5e80: 00000001 c07440d8 ee8cfe00 c0725edc 00000001 c0725ea8 00054
>> [   19.365631] 5ea0: 20000013 ffffffff
>> [   19.369293] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c04f8c74>] (_raw_spin_)
>> [   19.378570] [<c04f8c74>] (_raw_spin_unlock_irq+0x28/0x2c) from [<c007425c>] )
>> [   19.388732] [<c007425c>] (finish_task_switch+0x84/0x198) from [<c04f7760>] ()
>> [   19.398193] [<c04f7760>] (__schedule+0x404/0x870) from [<c0015e14>] (cpu_idl)
>> [   19.406768] [<c0015e14>] (cpu_idle+0xe8/0x114) from [<c06d48d8>] (start_kern)
>> [   19.415466] Code: e59480e4 e1d311b4 e5d36034 e1a0a81b (e7920001)
>> [   19.421844] ---[ end trace 3eb9bf4b81babe15 ]---
>> [   19.426666] Kernel panic - not syncing: Fatal exception in interrupt
>> [   19.433288] CPU1: stopping
>> [   19.436157] [<c001beac>] (unwind_backtrace+0x0/0xf4) from [<c0019db4>] (hand)
>> [   19.445220] [<c0019db4>] (handle_IPI+0x130/0x15c) from [<c0008498>] (gic_han)
>> [   19.454223] [<c0008498>] (gic_handle_irq+0x58/0x60) from [<c04f8ee4>] (__irq)
>> [   19.462951] Exception stack(0xef06ff88 to 0xef06ffd0)
>> [   19.468231] ff80:                   c079f960 c079f960 00000000 00000000 ef068
>> [   19.476745] ffa0: c0504510 c0747e60 00000000 411fc092 c0748078 00000000 00000
>> [   19.485290] ffc0: c0015570 c0015574 60000113 ffffffff
>> [   19.490570] [<c04f8ee4>] (__irq_svc+0x44/0x5c) from [<c0015574>] (default_id)
>> [   19.499114] [<c0015574>] (default_idle+0x20/0x44) from [<c0015dc8>] (cpu_idl)
>> [   19.507659] [<c0015dc8>] (cpu_idle+0x9c/0x114) from [<804f1d94>] (0x804f1d94)
>> ---
>> Tarun
>>>
>>> Kevin
>>>
>>>>  drivers/gpio/gpio-omap.c |   35 +++++++++++++++++++++++++++++++++++
>>>>  1 files changed, 35 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>>> index e6efd77..50de875 100644
>>>> --- a/drivers/gpio/gpio-omap.c
>>>> +++ b/drivers/gpio/gpio-omap.c
>>>> @@ -1152,6 +1152,40 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
>>>>       return ret;
>>>>  }
>>>>
>>>> +/**
>>>> + * omap_gpio_remove - cleanup a registered gpio device
>>>> + * @pdev:       pointer to current gpio platform device
>>>> + *
>>>> + * Called by driver framework whenever a gpio device is unregistered.
>>>> + * GPIO is deleted from the list and associated clock handle freed.
>>>> + */
>>>> +static int __devexit omap_gpio_remove(struct platform_device *pdev)
>>>> +{
>>>> +     struct device *dev = &pdev->dev;
>>>> +     struct gpio_bank *bank;
>>>> +     unsigned long flags;
>>>> +     int ret = -EINVAL;
>>>> +
>>>> +     list_for_each_entry(bank, &omap_gpio_list, node) {
>>>> +             spin_lock_irqsave(&bank->lock, flags);
>>>> +             if (bank->dev == dev) {
>>>> +                     clk_put(bank->dbck);
>>>> +                     list_del(&bank->node);
>>>> +                     ret = 0;
>>>> +                     spin_unlock_irqrestore(&bank->lock, flags);
>>>> +                     break;
>>>> +             }
>>>> +             spin_unlock_irqrestore(&bank->lock, flags);
>>>> +     }
>>>> +
>>>> +     if (!ret) {
>>>> +             pm_runtime_disable(bank->dev);
>>>> +             irq_free_descs(bank->irq_base, bank->width);
>>>> +     }
>>>> +
>>>> +     return ret;
>>>> +}
>>>> +
>>>>  #ifdef CONFIG_ARCH_OMAP2PLUS
>>>>
>>>>  #if defined(CONFIG_PM_RUNTIME)
>>>> @@ -1478,6 +1512,7 @@ MODULE_DEVICE_TABLE(of, omap_gpio_match);
>>>>
>>>>  static struct platform_driver omap_gpio_driver = {
>>>>       .probe          = omap_gpio_probe,
>>>> +     .remove = __devexit_p(omap_gpio_remove),
>>>>       .driver         = {
>>>>               .name   = "omap_gpio",
>>>>               .pm     = &gpio_pm_ops,
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From balbi at ti.com  Fri Aug 10 02:16:17 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 10 Aug 2012 09:16:17 +0300
Subject: [PATCH v3 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <CAD6zSYP33PDrXwifQM=7q+Esk1X7m5+DNG_=A2a-qTENk4zq8w@mail.gmail.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <502464FE.3000908@samsung.com>
 <CAD6zSYP33PDrXwifQM=7q+Esk1X7m5+DNG_=A2a-qTENk4zq8w@mail.gmail.com>
Message-ID: <20120810061616.GC1689@arwen.pp.htv.fi>

HI,

On Fri, Aug 10, 2012 at 11:17:29AM +0530, Praveen Paneri wrote:
> On Fri, Aug 10, 2012 at 7:03 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> > Hi, Praveen.
> >
> >
> > On 08/08/2012 04:40 PM, Praveen Paneri wrote:
> >>
> >> Changes from v2:
> >> Changed the driver filenames to samsung-usbphy
> >> Changed 's3c' to 'samsung' for platform device as well as platform data
> >> Moved platform data structure to a separate file
> >> Rectified coding style related errors
> >>
> >> Changes from v1:
> >> Rebased patches to latest usb-next branch
> >> Changed the name 'sec_usbphy' to 'samsung_usbphy'
> >>
> >> This patch set introduces a phy driver for samsung SoCs. It uses the
> >> existing
> >> transceiver infrastructure to provide phy control functions. Use of this
> >> driver
> >> can be extended for usb host phy as well.
> >
> >
> > How can you support usb host phy? I cannot choose to use which phy when
> > call init or shutdown of phy at current phy framework.

correct. Curretly that's not supported. We are trying to come up with
proper DeviceTree bindings to allow that. Kishon has been working on
providing devm_usb_get_phy_by_phandle() would should help achieving what
you need.

> If you are talking about choosing between PHY0 (for device) and PHY1
> (for host), I think you can make use of the flags available in usb_phy
> to pass that information to phy driver and that can be handled there.

I rather you didn't do it that way. Those flags are used to pass
features to the PHY. See drivers/usb/otg/ulpi.c, for instance.

> This is just one way I have successfully implement two different phy
> control. There might be a better way to do that.

I guess using DT phandles is the way to go here.

-- 
balbi
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From p.paneri at samsung.com  Fri Aug 10 02:24:32 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 11:54:32 +0530
Subject: [PATCH v3 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <20120810061616.GC1689@arwen.pp.htv.fi>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <502464FE.3000908@samsung.com>
 <CAD6zSYP33PDrXwifQM=7q+Esk1X7m5+DNG_=A2a-qTENk4zq8w@mail.gmail.com>
 <20120810061616.GC1689@arwen.pp.htv.fi>
Message-ID: <CAD6zSYMC072bMqMPTmsH4ZzTAd4OmFk5TVpcxAAu82b7J9jNHw@mail.gmail.com>

On Fri, Aug 10, 2012 at 11:46 AM, Felipe Balbi <balbi at ti.com> wrote:
> HI,
>
> On Fri, Aug 10, 2012 at 11:17:29AM +0530, Praveen Paneri wrote:
>> On Fri, Aug 10, 2012 at 7:03 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>> > Hi, Praveen.
>> >
>> >
>> > On 08/08/2012 04:40 PM, Praveen Paneri wrote:
>> >>
>> >> Changes from v2:
>> >> Changed the driver filenames to samsung-usbphy
>> >> Changed 's3c' to 'samsung' for platform device as well as platform data
>> >> Moved platform data structure to a separate file
>> >> Rectified coding style related errors
>> >>
>> >> Changes from v1:
>> >> Rebased patches to latest usb-next branch
>> >> Changed the name 'sec_usbphy' to 'samsung_usbphy'
>> >>
>> >> This patch set introduces a phy driver for samsung SoCs. It uses the
>> >> existing
>> >> transceiver infrastructure to provide phy control functions. Use of this
>> >> driver
>> >> can be extended for usb host phy as well.
>> >
>> >
>> > How can you support usb host phy? I cannot choose to use which phy when
>> > call init or shutdown of phy at current phy framework.
>
> correct. Curretly that's not supported. We are trying to come up with
> proper DeviceTree bindings to allow that. Kishon has been working on
> providing devm_usb_get_phy_by_phandle() would should help achieving what
> you need.
>
>> If you are talking about choosing between PHY0 (for device) and PHY1
>> (for host), I think you can make use of the flags available in usb_phy
>> to pass that information to phy driver and that can be handled there.
>
> I rather you didn't do it that way. Those flags are used to pass
> features to the PHY. See drivers/usb/otg/ulpi.c, for instance.
>
>> This is just one way I have successfully implement two different phy
>> control. There might be a better way to do that.
>
> I guess using DT phandles is the way to go here.
off-course! That is why I haven't included host support as of now.

Praveen
>
> --
> balbi


From tony at atomide.com  Fri Aug 10 02:28:00 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 Aug 2012 23:28:00 -0700
Subject: [PATCH 07/11] ARM: OMAP/ASoC: Zoom2: Let the codec to handle
 the hs_extmute GPIO
In-Reply-To: <1344418887-5262-8-git-send-email-peter.ujfalusi@ti.com>
References: <1344418887-5262-1-git-send-email-peter.ujfalusi@ti.com>
 <1344418887-5262-8-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120810062800.GO11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120808 02:42]:
> Remove the use of set_hs_extmute callback and let the codec driver to
> handle the extmute GPIO.

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 10 02:29:17 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 Aug 2012 23:29:17 -0700
Subject: [PATCH 2/4] ARM: OMAP: twl-common: Add helper function to
 register the omap-twl4030 audio driver
In-Reply-To: <1344419650-5389-3-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120810062916.GP11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120808 02:54]:
> Since several OMAP3 based boards will be using the unified simple audio
> driver it is better to not have duplicated code in the board files for this
> purpose.
> Board files can call omap_twl4030_audio_init(); to set up the needed device
> for the audio support.
> 
> For example:
> omap_twl4030_audio_init("omap3beagle", 26000000);

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 10 02:31:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 Aug 2012 23:31:06 -0700
Subject: [PATCH 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <1344419650-5389-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120810063105.GQ11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120808 02:54]:
> These boards have similar audio setup and they can all use the same driver
> for audio support if it is enabled in the kernel config.

After the naming changes suggested by Igor:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 10 02:32:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 9 Aug 2012 23:32:10 -0700
Subject: [PATCH 0/4] ASoC/OMAP: ASoC machine driver for simple SoC with
 twl4030
In-Reply-To: <20120808132741.GX16861@opensource.wolfsonmicro.com>
References: <1344419650-5389-1-git-send-email-peter.ujfalusi@ti.com>
 <20120808132741.GX16861@opensource.wolfsonmicro.com>
Message-ID: <20120810063209.GR11011@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120808 06:27]:
> On Wed, Aug 08, 2012 at 12:54:06PM +0300, Peter Ujfalusi wrote:
> 
> > Changes under arch/arm/mach-omap2/ are trivial, I don't expect merge issues
> > later. If it is OK for the maintainers I would like this to go via audio tree
> > (with the McBSP and the twl4030-audio stack DT support).
> 
> This all looks OK to me, again if it gets applied via ASoC I'll put it
> on a separate branch so if we do need to get into OMAP as well it's easy
> to do so.

I've acked the omap related patches so when the other changes
comments are dealt with, please feel free to merge via ASoC tree.

Regards,

Tony


From kgene.kim at samsung.com  Fri Aug 10 02:39:38 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 Aug 2012 15:39:38 +0900
Subject: [PATCH 10/11] spi/s3c64xx: improve error handling
In-Reply-To: <1344437248-20560-11-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-11-git-send-email-arnd@arndb.de>
Message-ID: <0de501cd76c2$ea07dfd0$be179f70$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> When a device tree definition os an s3c64xx SPI master is missing
> a "controller-data" subnode, the newly added s3c64xx_get_slave_ctrldata
> function might use uninitialized memory in place of that node,
> which was correctly reported by gcc.
> 
> Without this patch, building s3c6400_defconfig results in:
> 
> drivers/spi/spi-s3c64xx.c: In function
> 's3c64xx_get_slave_ctrldata.isra.25':
> drivers/spi/spi-s3c64xx.c:841:5: warning: 'data_np' may be used
> uninitialized in this function [-Wuninitialized]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Jaswinder Singh <jaswinder.singh at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  drivers/spi/spi-s3c64xx.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 646a765..cfa2c35 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -826,7 +826,7 @@ static struct s3c64xx_spi_csinfo
> *s3c64xx_get_slave_ctrldata(
>  				struct spi_device *spi)
>  {
>  	struct s3c64xx_spi_csinfo *cs;
> -	struct device_node *slave_np, *data_np;
> +	struct device_node *slave_np, *data_np = NULL;
>  	u32 fb_delay = 0;
> 
>  	slave_np = spi->dev.of_node;
> --
> 1.7.10

Looks ok to me,
Acked-by: Kukjin Kim <kgene.kim at samsung.com>

BTW for same reason, probably, we need following fix?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

----
From: Kukjin Kim <kgene.kim at samsung.com>

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-tegra/tegra2_emc.c             |    4 ++--
 arch/c6x/kernel/setup.c                      |    2 +-
 arch/powerpc/kernel/ibmebus.c                |    2 +-
 arch/powerpc/kernel/pci_of_scan.c            |    2 +-
 arch/powerpc/kernel/prom.c                   |    2 +-
 arch/powerpc/kernel/rtas_pci.c               |    2 +-
 arch/powerpc/kernel/vio.c                    |    2 +-
 arch/powerpc/platforms/44x/warp.c            |    2 +-
 arch/powerpc/platforms/cell/setup.c          |    2 +-
 arch/powerpc/platforms/powernv/opal.c        |    2 +-
 arch/powerpc/platforms/powernv/pci-ioda.c    |    2 +-
 arch/powerpc/platforms/powernv/pci-p5ioc2.c  |    2 +-
 arch/powerpc/platforms/pseries/eeh.c         |   12 ++++++------
 arch/powerpc/sysdev/mv64x60_dev.c            |    2 +-
 drivers/dma/fsldma.c                         |    2 +-
 drivers/gpu/drm/nouveau/nouveau_connector.c  |    2 +-
 drivers/hwmon/ads1015.c                      |    2 +-
 drivers/i2c/busses/i2c-powermac.c            |    2 +-
 drivers/i2c/busses/i2c-pxa-pci.c             |    2 +-
 drivers/i2c/i2c-mux.c                        |    2 +-
 drivers/iio/adc/at91_adc.c                   |    2 +-
 drivers/input/keyboard/samsung-keypad.c      |    2 +-
 drivers/leds/leds-gpio.c                     |    2 +-
 drivers/net/ethernet/freescale/fsl_pq_mdio.c |    2 +-
 drivers/net/phy/mdio-mux.c                   |    2 +-
 drivers/of/of_i2c.c                          |    2 +-
 drivers/of/of_mdio.c                         |    2 +-
 drivers/of/of_pci.c                          |    2 +-
 drivers/of/platform.c                        |    6 +++---
 drivers/pinctrl/pinctrl-imx.c                |    4 ++--
 drivers/pinctrl/pinctrl-tegra.c              |    2 +-
 drivers/pinctrl/spear/pinctrl-spear.c        |    2 +-
 drivers/regulator/da9052-regulator.c         |    2 +-
 drivers/regulator/mc13xxx-regulator-core.c   |    2 +-
 drivers/regulator/of_regulator.c             |    2 +-
 drivers/spi/spi.c                            |    2 +-
 drivers/tty/hvc/hvc_opal.c                   |    2 +-
 37 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_emc.c
b/arch/arm/mach-tegra/tegra2_emc.c
index 5070d83..d045a9e 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -181,7 +181,7 @@ int tegra_emc_set_rate(unsigned long rate)
 #ifdef CONFIG_OF
 static struct device_node *tegra_emc_ramcode_devnode(struct device_node
*np)
 {
-	struct device_node *iter;
+	struct device_node *iter = NULL;
 	u32 reg;
 
 	for_each_child_of_node(np, iter) {
@@ -198,7 +198,7 @@ static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
 		struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
-	struct device_node *tnp, *iter;
+	struct device_node *tnp, *iter = NULL;
 	struct tegra_emc_pdata *pdata;
 	int ret, i, num_tables;
 
diff --git a/arch/c6x/kernel/setup.c b/arch/c6x/kernel/setup.c
index f4e72bd..0f4cd29 100644
--- a/arch/c6x/kernel/setup.c
+++ b/arch/c6x/kernel/setup.c
@@ -99,7 +99,7 @@ static void __init get_cpuinfo(void)
 	unsigned long core_khz;
 	u64 tmp;
 	struct cpuinfo_c6x *p;
-	struct device_node *node, *np;
+	struct device_node *node, *np = NULL;
 
 	p = &per_cpu(cpu_data, smp_processor_id());
 
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index b01d14e..1147931 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -180,7 +180,7 @@ static int ibmebus_create_device(struct device_node *dn)
 
 static int ibmebus_create_devices(const struct of_device_id *matches)
 {
-	struct device_node *root, *child;
+	struct device_node *root, *child = NULL;
 	int ret = 0;
 
 	root = of_find_node_by_path("/");
diff --git a/arch/powerpc/kernel/pci_of_scan.c
b/arch/powerpc/kernel/pci_of_scan.c
index 30378a1..8344f9a 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -302,7 +302,7 @@ EXPORT_SYMBOL(of_scan_pci_bridge);
 static void __devinit __of_scan_bus(struct device_node *node,
 				    struct pci_bus *bus, int
rescan_existing)
 {
-	struct device_node *child;
+	struct device_node *child = NULL;
 	const u32 *reg;
 	int reglen, devfn;
 	struct pci_dev *dev;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index f191bf0..b4a021e 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -735,7 +735,7 @@ void __init early_init_devtree(void *params)
  */
 struct device_node *of_find_next_cache_node(struct device_node *np)
 {
-	struct device_node *child;
+	struct device_node *child = NULL;
 	const phandle *handle;
 
 	handle = of_get_property(np, "l2-cache", NULL);
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 179af90..b75d76b 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -255,7 +255,7 @@ int __devinit rtas_setup_phb(struct pci_controller *phb)
 
 void __init find_and_init_phbs(void)
 {
-	struct device_node *node;
+	struct device_node *node = NULL;
 	struct pci_controller *phb;
 	struct device_node *root = of_find_node_by_path("/");
 
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 02b3221..37b2a76 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -116,7 +116,7 @@ static int vio_cmo_num_OF_devs(void)
 	 */
 	node_vroot = of_find_node_by_name(NULL, "vdevice");
 	if (node_vroot) {
-		struct device_node *of_node;
+		struct device_node *of_node = NULL;
 		struct property *prop;
 
 		for_each_child_of_node(node_vroot, of_node) {
diff --git a/arch/powerpc/platforms/44x/warp.c
b/arch/powerpc/platforms/44x/warp.c
index 4cfa499..b505ca7 100644
--- a/arch/powerpc/platforms/44x/warp.c
+++ b/arch/powerpc/platforms/44x/warp.c
@@ -172,7 +172,7 @@ static irqreturn_t temp_isr(int irq, void *context)
 
 static int pika_setup_leds(void)
 {
-	struct device_node *np, *child;
+	struct device_node *np, *child = NULL;
 
 	np = of_find_compatible_node(NULL, NULL, "gpio-leds");
 	if (!np) {
diff --git a/arch/powerpc/platforms/cell/setup.c
b/arch/powerpc/platforms/cell/setup.c
index 4ab0876..356fb9c 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -155,7 +155,7 @@ static const struct of_device_id cell_bus_ids[]
__initconst = {
 static int __init cell_publish_devices(void)
 {
 	struct device_node *root = of_find_node_by_path("/");
-	struct device_node *np;
+	struct device_node *np = NULL;
 	int node;
 
 	/* Publish OF platform devices for southbridge IOs */
diff --git a/arch/powerpc/platforms/powernv/opal.c
b/arch/powerpc/platforms/powernv/opal.c
index aaa0dba..4df5f2d 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -279,7 +279,7 @@ static irqreturn_t opal_interrupt(int irq, void *data)
 
 static int __init opal_init(void)
 {
-	struct device_node *np, *consoles;
+	struct device_node *np = NULL, *consoles;
 	const u32 *irqs;
 	int rc, i, irqlen;
 
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index 9cda6a1..e08c238 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1317,7 +1317,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node
*np)
 
 void __init pnv_pci_init_ioda_hub(struct device_node *np)
 {
-	struct device_node *phbn;
+	struct device_node *phbn = NULL;
 	const u64 *prop64;
 	u64 hub_id;
 
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 2649677..d2565d0 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -175,7 +175,7 @@ static void __init pnv_pci_init_p5ioc2_phb(struct
device_node *np,
 
 void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
 {
-	struct device_node *phbn;
+	struct device_node *phbn = NULL;
 	const u64 *prop64;
 	u64 hub_id;
 	void *tce_mem;
diff --git a/arch/powerpc/platforms/pseries/eeh.c
b/arch/powerpc/platforms/pseries/eeh.c
index ecd394c..4b5913e 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -206,7 +206,7 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev,
char * buf, size_t len)
 
 	/* Gather status on devices under the bridge */
 	if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
-		struct device_node *child;
+		struct device_node *child = NULL;
 
 		for_each_child_of_node(dn, child) {
 			if (of_node_to_eeh_dev(child))
@@ -289,7 +289,7 @@ struct device_node *eeh_find_device_pe(struct
device_node *dn)
  */
 static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
 {
-	struct device_node *dn;
+	struct device_node *dn = NULL;
 
 	for_each_child_of_node(parent, dn) {
 		if (of_node_to_eeh_dev(dn)) {
@@ -342,7 +342,7 @@ void eeh_mark_slot(struct device_node *dn, int
mode_flag)
  */
 static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
 {
-	struct device_node *dn;
+	struct device_node *dn = NULL;
 
 	for_each_child_of_node(parent, dn) {
 		if (of_node_to_eeh_dev(dn)) {
@@ -601,7 +601,7 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev,
enum pcie_reset_state stat
  */
 void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset)
 {
-	struct device_node *dn;
+	struct device_node *dn = NULL;
 
 	for_each_child_of_node(parent, dn) {
 		if (of_node_to_eeh_dev(dn)) {
@@ -788,7 +788,7 @@ static inline void eeh_restore_one_device_bars(struct
eeh_dev *edev)
  */
 void eeh_restore_bars(struct eeh_dev *edev)
 {
-	struct device_node *dn;
+	struct device_node *dn = NULL;
 	if (!edev)
 		return;
 	
@@ -1050,7 +1050,7 @@ static void eeh_add_device_early(struct device_node
*dn)
  */
 void eeh_add_device_tree_early(struct device_node *dn)
 {
-	struct device_node *sib;
+	struct device_node *sib = NULL;
 
 	for_each_child_of_node(dn, sib)
 		eeh_add_device_tree_early(sib);
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c
b/arch/powerpc/sysdev/mv64x60_dev.c
index 0f6af41..7d4ffd2 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -430,7 +430,7 @@ error:
 
 static int __init mv64x60_device_setup(void)
 {
-	struct device_node *np, *np2;
+	struct device_node *np, *np2 = NULL;
 	struct platform_device *pdev;
 	int id, id2;
 	int err;
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 8f84761..3786bfc 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1327,7 +1327,7 @@ static void fsl_dma_chan_remove(struct fsldma_chan
*chan)
 static int __devinit fsldma_of_probe(struct platform_device *op)
 {
 	struct fsldma_device *fdev;
-	struct device_node *child;
+	struct device_node *child = NULL;
 	int err;
 
 	fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 7b11edb..33edf87 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -145,7 +145,7 @@ nouveau_connector_of_detect(struct drm_connector
*connector)
 	struct drm_device *dev = connector->dev;
 	struct nouveau_connector *nv_connector =
nouveau_connector(connector);
 	struct nouveau_encoder *nv_encoder;
-	struct device_node *cn, *dn = pci_device_to_OF_node(dev->pdev);
+	struct device_node *cn = NULL, *dn =
pci_device_to_OF_node(dev->pdev);
 
 	if (!dn ||
 	    !((nv_encoder = find_encoder(connector, OUTPUT_TMDS)) ||
diff --git a/drivers/hwmon/ads1015.c b/drivers/hwmon/ads1015.c
index 1958f03..d1ced0d 100644
--- a/drivers/hwmon/ads1015.c
+++ b/drivers/hwmon/ads1015.c
@@ -164,7 +164,7 @@ static int ads1015_remove(struct i2c_client *client)
 static int ads1015_get_channels_config_of(struct i2c_client *client)
 {
 	struct ads1015_data *data = i2c_get_clientdata(client);
-	struct device_node *node;
+	struct device_node *node = NULL;
 
 	if (!client->dev.of_node
 	    || !of_get_next_child(client->dev.of_node, NULL))
diff --git a/drivers/i2c/busses/i2c-powermac.c
b/drivers/i2c/busses/i2c-powermac.c
index 5285f85..60b041b 100644
--- a/drivers/i2c/busses/i2c-powermac.c
+++ b/drivers/i2c/busses/i2c-powermac.c
@@ -340,7 +340,7 @@ static void __devinit
i2c_powermac_register_devices(struct i2c_adapter *adap,
 						    struct pmac_i2c_bus
*bus)
 {
 	struct i2c_client *newdev;
-	struct device_node *node;
+	struct device_node *node = NULL;
 	bool found_onyx = 0;
 
 	/*
diff --git a/drivers/i2c/busses/i2c-pxa-pci.c
b/drivers/i2c/busses/i2c-pxa-pci.c
index 4dc9bef..ca407d5 100644
--- a/drivers/i2c/busses/i2c-pxa-pci.c
+++ b/drivers/i2c/busses/i2c-pxa-pci.c
@@ -22,7 +22,7 @@ static struct platform_device *add_i2c_device(struct
pci_dev *dev, int bar)
 	struct platform_device *pdev;
 	struct i2c_pxa_platform_data pdata;
 	struct resource res[2];
-	struct device_node *child;
+	struct device_node *child = NULL;
 	static int devnum;
 	int ret;
 
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index 1038c38..cb632a9 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -132,7 +132,7 @@ struct i2c_adapter *i2c_add_mux_adapter(struct
i2c_adapter *parent,
 	 * nothing if !CONFIG_OF.
 	 */
 	if (mux_dev->of_node) {
-		struct device_node *child;
+		struct device_node *child = NULL;
 		u32 reg;
 
 		for_each_child_of_node(mux_dev->of_node, child) {
diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c
index f61780a..52203d4 100644
--- a/drivers/iio/adc/at91_adc.c
+++ b/drivers/iio/adc/at91_adc.c
@@ -381,7 +381,7 @@ static int at91_adc_probe_dt(struct at91_adc_state *st,
 {
 	struct iio_dev *idev = iio_priv_to_dev(st);
 	struct device_node *node = pdev->dev.of_node;
-	struct device_node *trig_node;
+	struct device_node *trig_node = NULL;
 	int i = 0, ret;
 	u32 prop;
 
diff --git a/drivers/input/keyboard/samsung-keypad.c
b/drivers/input/keyboard/samsung-keypad.c
index a061ba6..6b3334f 100644
--- a/drivers/input/keyboard/samsung-keypad.c
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -255,7 +255,7 @@ static struct samsung_keypad_platdata
*samsung_keypad_parse_dt(
 	struct samsung_keypad_platdata *pdata;
 	struct matrix_keymap_data *keymap_data;
 	uint32_t *keymap, num_rows = 0, num_cols = 0;
-	struct device_node *np = dev->of_node, *key_np;
+	struct device_node *np = dev->of_node, *key_np = NULL;
 	unsigned int key_count = 0;
 
 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
index c032b21..7458663 100644
--- a/drivers/leds/leds-gpio.c
+++ b/drivers/leds/leds-gpio.c
@@ -168,7 +168,7 @@ static inline int sizeof_gpio_leds_priv(int num_leds)
 #ifdef CONFIG_OF_GPIO
 static struct gpio_leds_priv * __devinit gpio_leds_create_of(struct
platform_device *pdev)
 {
-	struct device_node *np = pdev->dev.of_node, *child;
+	struct device_node *np = pdev->dev.of_node, *child = NULL;
 	struct gpio_leds_priv *priv;
 	int count = 0, ret;
 
diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.c
b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
index 9527b28..ea34f84 100644
--- a/drivers/net/ethernet/freescale/fsl_pq_mdio.c
+++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
@@ -260,7 +260,7 @@ static int get_ucc_id_for_range(u64 start, u64 end, u32
*ucc_id)
 static int fsl_pq_mdio_probe(struct platform_device *ofdev)
 {
 	struct device_node *np = ofdev->dev.of_node;
-	struct device_node *tbi;
+	struct device_node *tbi = NULL;
 	struct fsl_pq_mdio_priv *priv;
 	struct fsl_pq_mdio __iomem *regs = NULL;
 	void __iomem *map;
diff --git a/drivers/net/phy/mdio-mux.c b/drivers/net/phy/mdio-mux.c
index 5c12018..cb4ceb6 100644
--- a/drivers/net/phy/mdio-mux.c
+++ b/drivers/net/phy/mdio-mux.c
@@ -99,7 +99,7 @@ int mdio_mux_init(struct device *dev,
 		  void *data)
 {
 	struct device_node *parent_bus_node;
-	struct device_node *child_bus_node;
+	struct device_node *child_bus_node = NULL;
 	int r, ret_val;
 	struct mii_bus *parent_bus;
 	struct mdio_mux_parent_bus *pb;
diff --git a/drivers/of/of_i2c.c b/drivers/of/of_i2c.c
index 1e173f3..6a080c7 100644
--- a/drivers/of/of_i2c.c
+++ b/drivers/of/of_i2c.c
@@ -21,7 +21,7 @@
 void of_i2c_register_devices(struct i2c_adapter *adap)
 {
 	void *result;
-	struct device_node *node;
+	struct device_node *node = NULL;
 
 	/* Only register child devices if the adapter has a node pointer set
*/
 	if (!adap->dev.of_node)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 8e6c25f..a52b354 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -33,7 +33,7 @@ MODULE_LICENSE("GPL");
 int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
 {
 	struct phy_device *phy;
-	struct device_node *child;
+	struct device_node *child = NULL;
 	int rc, i;
 
 	/* Mask out all PHYs from auto probing.  Instead the PHYs listed in
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 13e37e2..dfede93 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -18,7 +18,7 @@ static inline int __of_pci_pci_compare(struct device_node
*node,
 struct device_node *of_pci_find_child_device(struct device_node *parent,
 					     unsigned int devfn)
 {
-	struct device_node *node, *node2;
+	struct device_node *node = NULL, *node2 = NULL;
 
 	for_each_child_of_node(parent, node) {
 		if (__of_pci_pci_compare(node, devfn))
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index e44f8c2..58e8374 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -344,7 +344,7 @@ static int of_platform_bus_create(struct device_node
*bus,
 				  struct device *parent, bool strict)
 {
 	const struct of_dev_auxdata *auxdata;
-	struct device_node *child;
+	struct device_node *child = NULL;
 	struct platform_device *dev;
 	const char *bus_id = NULL;
 	void *platform_data = NULL;
@@ -396,7 +396,7 @@ int of_platform_bus_probe(struct device_node *root,
 			  const struct of_device_id *matches,
 			  struct device *parent)
 {
-	struct device_node *child;
+	struct device_node *child = NULL;
 	int rc = 0;
 
 	root = root ? of_node_get(root) : of_find_node_by_path("/");
@@ -445,7 +445,7 @@ int of_platform_populate(struct device_node *root,
 			const struct of_dev_auxdata *lookup,
 			struct device *parent)
 {
-	struct device_node *child;
+	struct device_node *child = NULL;
 	int rc = 0;
 
 	root = root ? of_node_get(root) : of_find_node_by_path("/");
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 44e9726..0f1d0ba 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -485,7 +485,7 @@ static int __devinit imx_pinctrl_parse_groups(struct
device_node *np,
 static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
 			struct imx_pinctrl_soc_info *info, u32 index)
 {
-	struct device_node *child;
+	struct device_node *child = NULL;
 	struct imx_pmx_func *func;
 	struct imx_pin_group *grp;
 	int ret;
@@ -521,7 +521,7 @@ static int __devinit imx_pinctrl_probe_dt(struct
platform_device *pdev,
 				struct imx_pinctrl_soc_info *info)
 {
 	struct device_node *np = pdev->dev.of_node;
-	struct device_node *child;
+	struct device_node *child = NULL;
 	int ret;
 	u32 nfuncs = 0;
 	u32 i = 0;
diff --git a/drivers/pinctrl/pinctrl-tegra.c
b/drivers/pinctrl/pinctrl-tegra.c
index ae52e4e..253d338 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -295,7 +295,7 @@ int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev
*pctldev,
 				 struct pinctrl_map **map, unsigned
*num_maps)
 {
 	unsigned reserved_maps;
-	struct device_node *np;
+	struct device_node *np = NULL;
 	int ret;
 
 	reserved_maps = 0;
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c
b/drivers/pinctrl/spear/pinctrl-spear.c
index 5d4f44f..ca7a6df 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -126,7 +126,7 @@ int spear_pinctrl_dt_node_to_map(struct pinctrl_dev
*pctldev,
 				 struct pinctrl_map **map, unsigned
*num_maps)
 {
 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct device_node *np;
+	struct device_node *np = NULL;
 	struct property *prop;
 	const char *function, *group;
 	int ret, index = 0, count = 0;
diff --git a/drivers/regulator/da9052-regulator.c
b/drivers/regulator/da9052-regulator.c
index 903299c..ce3aa94 100644
--- a/drivers/regulator/da9052-regulator.c
+++ b/drivers/regulator/da9052-regulator.c
@@ -396,7 +396,7 @@ static int __devinit da9052_regulator_probe(struct
platform_device *pdev)
 	} else {
 #ifdef CONFIG_OF
 		struct device_node *nproot = da9052->dev->of_node;
-		struct device_node *np;
+		struct device_node *np = NULL;
 
 		if (!nproot)
 			return -ENODEV;
diff --git a/drivers/regulator/mc13xxx-regulator-core.c
b/drivers/regulator/mc13xxx-regulator-core.c
index d6eda28..d179f54 100644
--- a/drivers/regulator/mc13xxx-regulator-core.c
+++ b/drivers/regulator/mc13xxx-regulator-core.c
@@ -173,7 +173,7 @@ EXPORT_SYMBOL_GPL(mc13xxx_fixed_regulator_ops);
 #ifdef CONFIG_OF
 int __devinit mc13xxx_get_num_regulators_dt(struct platform_device *pdev)
 {
-	struct device_node *parent, *child;
+	struct device_node *parent, *child = NULL;
 	int num = 0;
 
 	of_node_get(pdev->dev.parent->of_node);
diff --git a/drivers/regulator/of_regulator.c
b/drivers/regulator/of_regulator.c
index 3e4106f..62f59814 100644
--- a/drivers/regulator/of_regulator.c
+++ b/drivers/regulator/of_regulator.c
@@ -113,7 +113,7 @@ int of_regulator_match(struct device *dev, struct
device_node *node,
 	unsigned int count = 0;
 	unsigned int i;
 	const char *regulator_comp;
-	struct device_node *child;
+	struct device_node *child = NULL;
 
 	if (!dev || !node)
 		return -EINVAL;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 84c2861..81f20cf 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -811,7 +811,7 @@ err_init_queue:
 static void of_register_spi_devices(struct spi_master *master)
 {
 	struct spi_device *spi;
-	struct device_node *nc;
+	struct device_node *nc = NULL;
 	const __be32 *prop;
 	int rc;
 	int len;
diff --git a/drivers/tty/hvc/hvc_opal.c b/drivers/tty/hvc/hvc_opal.c
index 0d2ea0c..07f308e 100644
--- a/drivers/tty/hvc/hvc_opal.c
+++ b/drivers/tty/hvc/hvc_opal.c
@@ -344,7 +344,7 @@ void __init hvc_opal_init_early(void)
 			return;
 		}
 	} else {
-		struct device_node *opal, *np;
+		struct device_node *opal, *np = NULL;
 
 		/* Current OPAL takeover doesn't provide the stdout
 		 * path, so we hard wire it
-- 
1.7.4.1




From sboyd at codeaurora.org  Fri Aug 10 02:46:05 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 09 Aug 2012 23:46:05 -0700
Subject: [PATCH] ARM: Fix XIP build due to PHYS_OFFSET definition moving
In-Reply-To: <1343956994-27513-1-git-send-email-sboyd@codeaurora.org>
References: <1343956994-27513-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <5024AE2D.5050506@codeaurora.org>

On 8/2/2012 6:23 PM, Stephen Boyd wrote:
> During the p2v changes, the PHYS_OFFSET #define moved into a
> !__ASSEMBLY__ section. This causes a XIP build to fail with
>
>  arch/arm/kernel/head.o: In function 'stext':
>  arch/arm/kernel/head.S:146: undefined reference to 'PHYS_OFFSET'
>
> Momentarily leave the #ifndef __ASSEMBLY__ section so we can
> define PHYS_OFFSET for all compilation units.
>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---
>
> I don't know if it's worth stable, seems that nobody has compiled XIP for
> a year (back to 2.6.39 days?).

Is this approach acceptable? Shall I put this in the patch tracker?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kgene.kim at samsung.com  Fri Aug 10 02:48:40 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 10 Aug 2012 15:48:40 +0900
Subject: [PATCH 05/11] ARM: exynos: exynos_pm_add_dev_to_genpd may be
 unused
In-Reply-To: <1344437248-20560-6-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-6-git-send-email-arnd@arndb.de>
Message-ID: <0de601cd76c4$2d5846c0$8808d440$%kim@samsung.com>

Arnd Bergmann wrote:
> 
> exynos_pm_add_dev_to_genpd is used if one or more out of a large
> number of Kconfig symbols are enabled. However the new
> exynos_defconfig selects none of those, so the function becomes
> unused. Marking it so lets the compiler automatically discard
> it.
> 
> Without this patch, building exynos_defconfig results in:
> 
> arch/arm/mach-exynos/pm_domains.c:118:123: warning:
> 'exynos_pm_add_dev_to_genpd' defined but not used [-Wunused-function]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Kukjin Kim <kgene.kim at samsung.com>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From av.tikhomirov at samsung.com  Fri Aug 10 02:54:17 2012
From: av.tikhomirov at samsung.com (Anton Tikhomirov)
Date: Fri, 10 Aug 2012 15:54:17 +0900
Subject: [PATCH v3 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
In-Reply-To: <1344411661-17821-5-git-send-email-p.paneri@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-5-git-send-email-p.paneri@samsung.com>
Message-ID: <004301cd76c4$f63d4310$e2b7c930$%tikhomirov@samsung.com>

Hi Praveen,

> -----Original Message-----
> From: linux-usb-owner at vger.kernel.org [mailto:linux-usb-
> owner at vger.kernel.org] On Behalf Of Praveen Paneri
> Sent: Wednesday, August 08, 2012 4:41 PM
> To: linux-usb at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
> kgene.kim at samsung.com; balbi at ti.com; gregkh at linuxfoundation.org;
> thomas.abraham at linaro.org; ben-linux at fluff.org;
> broonie at opensource.wolfsonmicro.com; l.majewski at samsung.com;
> kyungmin.park at samsung.com; grant.likely at secretlab.ca; heiko at sntech.de
> Subject: [PATCH v3 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
> 
> Adding platform device for samsung-usbphy driver. Enabling it for
> s3c64xx based machines using s3c-hsotg.
> 
> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> ---
>  arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
>  arch/arm/mach-s3c64xx/mach-crag6410.c        |    4 +++
>  arch/arm/mach-s3c64xx/mach-smartq.c          |    5 ++++
>  arch/arm/mach-s3c64xx/mach-smdk6410.c        |    4 +++
>  arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
>  arch/arm/plat-samsung/devs.c                 |   33
++++++++++++++++++++++++++
>  arch/arm/plat-samsung/include/plat/devs.h    |    1 +
>  arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
>  8 files changed, 64 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-
> s3c64xx/include/mach/map.h
> index 8e2097b..dc482bb 100644
> --- a/arch/arm/mach-s3c64xx/include/mach/map.h
> +++ b/arch/arm/mach-s3c64xx/include/mach/map.h
> @@ -65,6 +65,7 @@
> 
>  #define S3C64XX_PA_NAND		(0x70200000)
>  #define S3C64XX_PA_FB		(0x77100000)
> +#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
>  #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
>  #define S3C64XX_PA_WATCHDOG	(0x7E004000)
>  #define S3C64XX_PA_RTC		(0x7E005000)
> @@ -113,6 +114,7 @@
>  #define S3C_PA_FB		S3C64XX_PA_FB
>  #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
>  #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
> +#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
>  #define S3C_PA_RTC		S3C64XX_PA_RTC
>  #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
>  #define S3C_PA_SPI0		S3C64XX_PA_SPI0
> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-
> s3c64xx/mach-crag6410.c
> index b0f5baf..fa02e2f 100644
> --- a/arch/arm/mach-s3c64xx/mach-crag6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
> @@ -31,6 +31,7 @@
>  #include <linux/spi/spi.h>
> 
>  #include <linux/i2c/pca953x.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> 
>  #include <video/platform_lcd.h>
> 
> @@ -336,6 +337,7 @@ static struct platform_device wallvdd_device = {
>  };
> 
>  static struct platform_device *crag6410_devices[] __initdata = {
> +	&samsung_device_usbphy,
>  	&s3c_device_hsmmc0,
>  	&s3c_device_hsmmc2,
>  	&s3c_device_i2c0,
> @@ -765,6 +767,7 @@ static const struct gpio_led_platform_data
> gpio_leds_pdata = {
>  	.num_leds = ARRAY_SIZE(gpio_leds),
>  };
> 
> +static struct samsung_usbphy_data crag6410_usbphy_pdata;

Why don't you use __initdata for this structure? It will be duplicated
in s3c_set_platdata() and we don't need it in memory after booting.
I think you can even initialize it here (with s5p_usb_phy_pmu_isolation).

> 
>  static void __init crag6410_machine_init(void)
>  {
> @@ -790,6 +793,7 @@ static void __init crag6410_machine_init(void)
>  	s3c_i2c0_set_platdata(&i2c0_pdata);
>  	s3c_i2c1_set_platdata(&i2c1_pdata);
>  	s3c_fb_set_platdata(&crag6410_lcd_pdata);
> +	samsung_usbphy_set_pdata(&crag6410_usbphy_pdata);
> 
>  	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
>  	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
> diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-
> s3c64xx/mach-smartq.c
> index 7400da1..e0c4df8 100644
> --- a/arch/arm/mach-s3c64xx/mach-smartq.c
> +++ b/arch/arm/mach-s3c64xx/mach-smartq.c
> @@ -18,6 +18,7 @@
>  #include <linux/serial_core.h>
>  #include <linux/spi/spi_gpio.h>
>  #include <linux/usb/gpio_vbus.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> 
>  #include <asm/mach-types.h>
>  #include <asm/mach/map.h>
> @@ -234,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[]
> __initdata = {
>  };
> 
>  static struct platform_device *smartq_devices[] __initdata = {
> +	&samsung_device_usbphy,
>  	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
>  	&s3c_device_hsmmc0,	/* ... then the external SD card */
>  	&s3c_device_hsmmc2,
> @@ -380,9 +382,12 @@ void __init smartq_map_io(void)
>  	smartq_lcd_mode_set();
>  }
> 
> +static struct samsung_usbphy_data smartq_usbphy_pdata;

Same here

> +
>  void __init smartq_machine_init(void)
>  {
>  	s3c_i2c0_set_platdata(NULL);
> +	samsung_usbphy_set_pdata(&smartq_usbphy_pdata);
>  	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
>  	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
>  	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-
> s3c64xx/mach-smdk6410.c
> index cbdc91b..8d40511 100644
> --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
> @@ -30,6 +30,7 @@
>  #include <linux/regulator/fixed.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/pwm_backlight.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> 
>  #ifdef CONFIG_SMDK6410_WM1190_EV1
>  #include <linux/mfd/wm8350/core.h>
> @@ -263,6 +264,7 @@ static struct samsung_keypad_platdata
> smdk6410_keypad_data __initdata = {
>  static struct map_desc smdk6410_iodesc[] = {};
> 
>  static struct platform_device *smdk6410_devices[] __initdata = {
> +	&samsung_device_usbphy,
>  #ifdef CONFIG_SMDK6410_SD_CH0
>  	&s3c_device_hsmmc0,
>  #endif
> @@ -626,6 +628,7 @@ static struct platform_pwm_backlight_data
> smdk6410_bl_data = {
>  	.pwm_id = 1,
>  };
> 
> +static struct samsung_usbphy_data smdk6410_usbphy_pdata;

Same here

> 
>  static void __init smdk6410_map_io(void)
>  {
> @@ -655,6 +658,7 @@ static void __init smdk6410_machine_init(void)
>  	s3c_i2c0_set_platdata(NULL);
>  	s3c_i2c1_set_platdata(NULL);
>  	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
> +	samsung_usbphy_set_pdata(&smdk6410_usbphy_pdata);
> 
>  	samsung_keypad_set_platdata(&smdk6410_keypad_data);
> 
> diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-
> s3c64xx/setup-usb-phy.c
> index 7a09553..3aee778 100644
> --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
> +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
> @@ -9,3 +9,17 @@
>   *
>   */
> 
> +#include <linux/io.h>
> +#include <mach/map.h>
> +#include <mach/regs-sys.h>
> +
> +void s5p_usb_phy_pmu_isolation(int on)
> +{
> +	if (on) {
> +		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
> +			S3C64XX_OTHERS);
> +	} else {
> +		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
> +			S3C64XX_OTHERS);
> +	}
> +}
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index 74e31ce..a094143 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -31,6 +31,7 @@
>  #include <linux/ioport.h>
>  #include <linux/platform_data/s3c-hsudc.h>
>  #include <linux/platform_data/s3c-hsotg.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> 
>  #include <asm/irq.h>
>  #include <asm/pmu.h>
> @@ -1343,6 +1344,35 @@ struct platform_device s5p_device_mixer = {
> 
>  /* USB */
> 
> +#ifdef CONFIG_S3C_DEV_USB_HSOTG
> +/* USB PHY*/
> +static struct resource samsung_usbphy_resource[] = {
> +	[0] = {
> +		.start = S3C_PA_USB_PHY,
> +		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +struct platform_device samsung_device_usbphy = {
> +	.name		= "s3c64xx-usbphy",
> +	.id		= -1,
> +	.num_resources	= ARRAY_SIZE(samsung_usbphy_resource),
> +	.resource	= samsung_usbphy_resource,
> +};
> +
> +void __init samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd)
> +{
> +	struct samsung_usbphy_data *npd;
> +
> +	npd = s3c_set_platdata(pd, sizeof(struct samsung_usbphy_data),
> +			&samsung_device_usbphy);
> +
> +	if (!npd->pmu_isolation)
> +		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
> +}
> +#endif
> +
>  #ifdef CONFIG_S3C_DEV_USB_HOST
>  static struct resource s3c_usb_resource[] = {
>  	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
> @@ -1449,6 +1479,8 @@ struct platform_device s3c_device_usb_hsotg = {
>  	},
>  };
> 
> +#ifndef CONFIG_ARCH_S3C64XX
> +/* TODO: To be removed later. Currently only S3C64XX is platform data
> free */
>  void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
>  {
>  	struct s3c_hsotg_plat *npd;
> @@ -1461,6 +1493,7 @@ void __init s3c_hsotg_set_platdata(struct
> s3c_hsotg_plat *pd)
>  	if (!npd->phy_exit)
>  		npd->phy_exit = s5p_usb_phy_exit;
>  }
> +#endif
>  #endif /* CONFIG_S3C_DEV_USB_HSOTG */
> 
>  /* USB High Spped 2.0 Device (Gadget) */
> diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-
> samsung/include/plat/devs.h
> index 5da4b4f..3849c88 100644
> --- a/arch/arm/plat-samsung/include/plat/devs.h
> +++ b/arch/arm/plat-samsung/include/plat/devs.h
> @@ -138,6 +138,7 @@ extern struct platform_device exynos_device_drm;
>  extern struct platform_device samsung_asoc_dma;
>  extern struct platform_device samsung_asoc_idma;
>  extern struct platform_device samsung_device_keypad;
> +extern struct platform_device samsung_device_usbphy;
> 
>  /* s3c2440 specific devices */
> 
> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-
> samsung/include/plat/usb-phy.h
> index 959bcdb..165ffe7 100644
> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
> @@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
> 
>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
> +extern void s5p_usb_phy_pmu_isolation(int on);
> 
>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
> --
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From thomas.abraham at linaro.org  Fri Aug 10 02:57:27 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 10 Aug 2012 12:27:27 +0530
Subject: [PATCH 05/11] ARM: exynos: exynos_pm_add_dev_to_genpd may be
 unused
In-Reply-To: <1344437248-20560-6-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-6-git-send-email-arnd@arndb.de>
Message-ID: <CAJuYYwRJqpPbrn-8FfQEhsdw1Vafr4MoH0hmfTObxdY8WRiHpQ@mail.gmail.com>

On 8 August 2012 20:17, Arnd Bergmann <arnd at arndb.de> wrote:
> exynos_pm_add_dev_to_genpd is used if one or more out of a large
> number of Kconfig symbols are enabled. However the new
> exynos_defconfig selects none of those, so the function becomes
> unused. Marking it so lets the compiler automatically discard
> it.
>
> Without this patch, building exynos_defconfig results in:
>
> arch/arm/mach-exynos/pm_domains.c:118:123: warning: 'exynos_pm_add_dev_to_genpd' defined but not used [-Wunused-function]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/mach-exynos/pm_domains.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
> index 373c3c0..c0bc83a 100644
> --- a/arch/arm/mach-exynos/pm_domains.c
> +++ b/arch/arm/mach-exynos/pm_domains.c
> @@ -115,7 +115,7 @@ static __init int exynos_pm_dt_parse_domains(void)
>  }
>  #endif /* CONFIG_OF */
>
> -static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
> +static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
>                                                 struct exynos_pm_domain *pd)
>  {
>         if (pdev->dev.bus) {
> --
> 1.7.10
>

Acked-by: Thomas Abraham <thomas.abraham at linaro.org>


From santosh.shilimkar at ti.com  Fri Aug 10 02:57:49 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 10 Aug 2012 12:27:49 +0530
Subject: [PATCH v2] gpio/omap: add *remove* callback in platform_driver
In-Reply-To: <CAC83Zv++4CO_0xsNbwMYX_5uEv56csprqrrCjshxfb+ay2gBQg@mail.gmail.com>
References: <1344434316-21141-1-git-send-email-tarun.kanti@ti.com>
 <87k3x9wbrk.fsf@ti.com>
 <CAC83ZvLKk71O=+9U16FoTUU_-ffg+iJsHPgnJx+bzbHhBDXzhQ@mail.gmail.com>
 <87hascgli3.fsf@ti.com>
 <CAC83Zv++4CO_0xsNbwMYX_5uEv56csprqrrCjshxfb+ay2gBQg@mail.gmail.com>
Message-ID: <CAMQu2gxzBSXrZ5s=ZJP-A+H=1RhzFJ-7FP=jAeBdPNHStYSCbQ@mail.gmail.com>

On Fri, Aug 10, 2012 at 11:38 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
>
> On Thu, Aug 9, 2012 at 8:28 PM, Kevin Hilman <khilman at ti.com> wrote:
> > "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
> >
> >> On Wed, Aug 8, 2012 at 10:40 PM, Kevin Hilman <khilman at ti.com> wrote:
> >>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
> >>>
> >>>> Add *remove* callback so that necessary cleanup operations are
> >>>> performed when device is unregistered. The device is deleted
> >>>> from the list and associated clock handle is released by
> >>>> calling clk_put() and irq descriptor is released using the
> >>>> irq_free_desc() api.
> >>>>
> >>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> >>>> Reported-by: Paul Walmsley <paul at pwsan.com>
> >>>> Reviewed-by: Jon Hunter <jon-hunter at ti.com>
> >>>> Cc: Kevin Hilman <khilman at ti.com>
> >>>> Cc: Rajendra Nayak <rnayak at ti.com>
> >>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >>>> Cc: Cousson, Benoit <b-cousson at ti.com>
> >>>> Cc: Paul Walmsley <paul at pwsan.com>
> >>>> ---
> >>>> v2:
> >>>> Baseline:
> >>>> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> >>>> Commit: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (Linux 3.6-rc1)
> >>>>
> >>>> (1) Use irq_free_descs() instead of irq_free_desc().
> >>>>     Besides, irq_free_desc() was using wrong parameter,
> >>>>     irq_base, instead of bank->irq.
> >>>> (2) irq_free_descs() moved outside spin_lock/unlock_*()
> >>>>     in order to avoid exception warnings.
> >>>>
> >>>> (3) pm_runtime_disable() added so that bind can happen successfully
> >>>>
> >>>> Test Detail:
> >>>> Step 1: Unbind gpio.5 device in order to invoke the *remove*
> >>>> callback.
> >>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/unbind
> >>>>
> >>>> Step 2: Bind gpio.5 device and confirm probe() for the device
> >>>> succeeds.
> >>>> #echo "omap_gpio.5" > sys/bus/platform/drivers/omap_gpio/bind
> >>>>
> >>>> Step 3: Execute read/write GPIO test case.
> >>>
> >>> What happens when GPIOs are in use (requested)?
> >> If I try to unbind a currently active GPIO bank then I see an exception
> >> after the irq descriptor is freed by the remove. I believe this is
> >> expected
> >> because interrupt raised by the system would not be handled.
> >
> > ... and the GPIO is still configured to trigger interrupts.
> Right!
>
> >
> > The point is that there is lots to cleanup/unconfigure properly for this
> > to work properly.
> As far as I can think of, all active gpio requests done either in
> board files or through DT
> have to be freed. But if this is done then when we bind() the device
> again initialization
> done in omap_gpio_probe() would not restore the board/DT related
> configuration.
> So the point is are we supposed to do all these cleanup in *remove*
> callback?
> If yes, how do we manage board level gpio usage?

More and more I think of the .remove() for GPIO, the interface not seems to
make sense. Being an infrastructure driver which can be used by many client
drivers like Ethernet, MMC card detect, sensors etc etc. And hence it can
not be made a loadable module.

So I am in favor of dropping the $subject patch completely unless and until
we need it genuinely.

Regards
Santosh


From thomas.abraham at linaro.org  Fri Aug 10 02:58:44 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 10 Aug 2012 12:28:44 +0530
Subject: [PATCH 10/11] spi/s3c64xx: improve error handling
In-Reply-To: <1344437248-20560-11-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-11-git-send-email-arnd@arndb.de>
Message-ID: <CAJuYYwR9SnEUdQ_VUjmNzZZeshHjsdVKhj1scqCMXrjtG9zo=A@mail.gmail.com>

On 8 August 2012 20:17, Arnd Bergmann <arnd at arndb.de> wrote:
> When a device tree definition os an s3c64xx SPI master is missing
> a "controller-data" subnode, the newly added s3c64xx_get_slave_ctrldata
> function might use uninitialized memory in place of that node,
> which was correctly reported by gcc.
>
> Without this patch, building s3c6400_defconfig results in:
>
> drivers/spi/spi-s3c64xx.c: In function 's3c64xx_get_slave_ctrldata.isra.25':
> drivers/spi/spi-s3c64xx.c:841:5: warning: 'data_np' may be used uninitialized in this function [-Wuninitialized]
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Jaswinder Singh <jaswinder.singh at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  drivers/spi/spi-s3c64xx.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 646a765..cfa2c35 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -826,7 +826,7 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
>                                 struct spi_device *spi)
>  {
>         struct s3c64xx_spi_csinfo *cs;
> -       struct device_node *slave_np, *data_np;
> +       struct device_node *slave_np, *data_np = NULL;
>         u32 fb_delay = 0;
>
>         slave_np = spi->dev.of_node;
> --
> 1.7.10
>

Acked-by: Thomas Abraham <thomas.abraham at linaro.org>


From p.paneri at samsung.com  Fri Aug 10 03:10:26 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:26 +0530
Subject: [PATCH v4 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
Message-ID: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>

Changes from v3:
Replaced susbsys_initcall()/module_exit() by module_platform_driver().
Accordingly in the hsotg driver returned -EPROBE_DEFER until phy driver
is registered
Removed unnecessary devm_usb_put_phy() call from the hsotg driver remove.

Changes from v2:
Changed the driver filenames to samsung-usbphy
Changed 's3c' to 'samsung' for platform device as well as platform data
Moved platform data structure to a separate file
Rectified coding style related errors

Changes from v1:
Rebased patches to latest usb-next branch
Changed the name 'sec_usbphy' to 'samsung_usbphy'

This patch set introduces a phy driver for samsung SoCs. It uses the existing
transceiver infrastructure to provide phy control functions. Use of this driver
can be extended for usb host phy as well. Over the period of time all the phy
related code for most of the samsung SoCs can be integrated here.
Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
when they start supporting this phy driver. 
This driver is tested with smdk6410 and Exynos4210(with DT).

Praveen Paneri (5):
  usb: phy: samsung: Introducing usb phy driver for hsotg
  usb: s3c-hsotg: Adding phy driver support
  ARM: S3C64XX: Removing old phy setup code
  ARM: S3C64XX: Enabling samsung-usbphy driver
  ARM: Exynos4210: Enabling samsung-usbphy driver

 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 arch/arm/boot/dts/exynos4210.dtsi                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    8 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   13 +
 arch/arm/mach-s3c64xx/include/mach/map.h           |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    7 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |    8 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    7 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   79 +----
 arch/arm/plat-samsung/devs.c                       |   33 ++
 arch/arm/plat-samsung/include/plat/devs.h          |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 drivers/usb/gadget/s3c-hsotg.c                     |   37 ++-
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
 drivers/usb/phy/samsung-usbphy.h                   |   48 +++
 include/linux/platform_data/samsung-usbphy.h       |   27 ++
 19 files changed, 549 insertions(+), 91 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung-usbphy.c
 create mode 100644 drivers/usb/phy/samsung-usbphy.h
 create mode 100644 include/linux/platform_data/samsung-usbphy.h



From p.paneri at samsung.com  Fri Aug 10 03:10:28 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:28 +0530
Subject: [PATCH v4 2/5] usb: s3c-hsotg: Adding phy driver support
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344582631-13658-3-git-send-email-p.paneri@samsung.com>

Adding the transceiver to hsotg driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 drivers/usb/gadget/s3c-hsotg.c |   37 +++++++++++++++++++++++++++----------
 1 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b13e0bb..60f6160 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -32,6 +32,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <mach/map.h>
@@ -133,7 +134,9 @@ struct s3c_hsotg_ep {
  * struct s3c_hsotg - driver state.
  * @dev: The parent device supplied to the probe function
  * @driver: USB gadget driver
- * @plat: The platform specific configuration data.
+ * @phy: The otg phy transceiver structure for phy control.
+ * @plat: The platform specific configuration data. This can be removed once
+ * all SoCs support usb transceiver.
  * @regs: The memory area mapped for accessing registers.
  * @irq: The IRQ number we are using
  * @supplies: Definition of USB power supplies
@@ -153,6 +156,7 @@ struct s3c_hsotg_ep {
 struct s3c_hsotg {
 	struct device		 *dev;
 	struct usb_gadget_driver *driver;
+	struct usb_phy		*phy;
 	struct s3c_hsotg_plat	 *plat;
 
 	spinlock_t              lock;
@@ -2854,7 +2858,10 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
 	dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
-	if (hsotg->plat->phy_init)
+
+	if (hsotg->phy)
+		usb_phy_init(hsotg->phy);
+	else if (hsotg->plat->phy_init)
 		hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 }
 
@@ -2869,7 +2876,9 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
 {
 	struct platform_device *pdev = to_platform_device(hsotg->dev);
 
-	if (hsotg->plat->phy_exit)
+	if (hsotg->phy)
+		usb_phy_shutdown(hsotg->phy);
+	else if (hsotg->plat->phy_exit)
 		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 }
 
@@ -3493,6 +3502,7 @@ static void s3c_hsotg_release(struct device *dev)
 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 {
 	struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+	struct usb_phy *phy;
 	struct device *dev = &pdev->dev;
 	struct s3c_hsotg_ep *eps;
 	struct s3c_hsotg *hsotg;
@@ -3501,20 +3511,27 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
 	int ret;
 	int i;
 
-	plat = pdev->dev.platform_data;
-	if (!plat) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
-
 	hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
 	if (!hsotg) {
 		dev_err(dev, "cannot get memory\n");
 		return -ENOMEM;
 	}
 
+	plat = pdev->dev.platform_data;
+	if (!plat) {
+		/* Fallback for transceiver */
+		phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+		if (IS_ERR_OR_NULL(phy)) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -EPROBE_DEFER;
+		} else {
+			hsotg->phy = phy;
+		}
+	} else {
+		hsotg->plat = plat;
+	}
+
 	hsotg->dev = dev;
-	hsotg->plat = plat;
 
 	hsotg->clk = clk_get(&pdev->dev, "otg");
 	if (IS_ERR(hsotg->clk)) {
-- 
1.7.1



From p.paneri at samsung.com  Fri Aug 10 03:10:27 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:27 +0530
Subject: [PATCH v4 1/5] usb: phy: samsung: Introducing usb phy driver for hsotg
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344582631-13658-2-git-send-email-p.paneri@samsung.com>

This driver uses usb_phy interface to interact with s3c-hsotg. Supports
phy_init and phy_shutdown functions to enable/disable phy. Tested with
smdk6410 and smdkv310. More SoCs can be brought under later.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
Acked-by: Heiko Stuebner <heiko at sntech.de>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
 drivers/usb/phy/Kconfig                            |    8 +
 drivers/usb/phy/Makefile                           |    1 +
 drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
 drivers/usb/phy/samsung-usbphy.h                   |   48 +++
 include/linux/platform_data/samsung-usbphy.h       |   27 ++
 6 files changed, 438 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
 create mode 100644 drivers/usb/phy/samsung-usbphy.c
 create mode 100644 drivers/usb/phy/samsung-usbphy.h
 create mode 100644 include/linux/platform_data/samsung-usbphy.h

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 0000000..fefd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,9 @@
+* Samsung's usb phy transceiver
+
+The Samsung's phy transceiver is used for controlling usb otg phy for
+s3c-hsotg usb device controller.
+
+Required properties:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index e7cf84f..d916477 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -15,3 +15,11 @@ config USB_ISP1301
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called isp1301.
+
+config SAMSUNG_USBPHY
+       bool "Samsung USB PHY controller Driver"
+       depends on USB_S3C_HSOTG
+       select USB_OTG_UTILS
+       help
+         Enable this to support Samsung USB phy controller for samsung
+         SoCs.
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..dfca70d 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_SAMSUNG_USBPHY)		+= samsung-usbphy.o
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
new file mode 100644
index 0000000..739b6c9
--- /dev/null
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -0,0 +1,345 @@
+/* linux/drivers/usb/phy/samsung-usbphy.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/usb/otg.h>
+#include <linux/platform_data/samsung-usbphy.h>
+
+#include "samsung-usbphy.h"
+
+enum samsung_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_EXYNOS4210,
+};
+
+/*
+ * struct samsung_usbphy - transceiver driver state
+ * @phy: transceiver structure
+ * @plat: platform data
+ * @dev: The parent device supplied to the probe function
+ * @clk: usb phy clock
+ * @regs: usb phy register memory base
+ * @cpu_type: machine identifier
+ */
+struct samsung_usbphy {
+	struct usb_phy	phy;
+	struct samsung_usbphy_data *plat;
+	struct device	*dev;
+	struct clk	*clk;
+	void __iomem	*regs;
+	int		cpu_type;
+};
+
+#define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
+
+/*
+ * Enables or disables the phy clock
+ * returns 0 on success else the error
+ */
+static int samsung_usbphy_clk_control(struct samsung_usbphy *sphy, bool on)
+{
+	if (on) {
+		if (!sphy->clk) {
+			sphy->clk = clk_get(sphy->dev, "otg");
+			if (IS_ERR(sphy->clk)) {
+				dev_err(sphy->dev, "Failed to get otg clock\n");
+				return PTR_ERR(sphy->clk);
+			}
+		}
+		clk_enable(sphy->clk);
+	} else {
+		clk_disable(sphy->clk);
+		clk_put(sphy->clk);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns reference clock frequency
+ */
+static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
+{
+	struct clk *ref_clk;
+	int refclk_freq = 0;
+
+	ref_clk = clk_get(sphy->dev, "xusbxti");
+	if (IS_ERR(ref_clk)) {
+		dev_err(sphy->dev, "Failed to get reference clock\n");
+		return PTR_ERR(ref_clk);
+	}
+
+	switch (clk_get_rate(ref_clk)) {
+	case 12 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+		break;
+	case 24 * MHZ:
+		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+		break;
+	default:
+	case 48 * MHZ:
+		/* default reference clock */
+		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+		break;
+	}
+	clk_put(ref_clk);
+
+	return refclk_freq;
+}
+
+static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+	u32 phyclk;
+	u32 rstcon;
+
+	/* set clock frequency for PLL */
+	phyclk = samsung_usbphy_get_refclk_freq(sphy);
+	phypwr = readl(regs + S3C_PHYPWR);
+	rstcon = readl(regs + S3C_RSTCON);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
+		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
+		rstcon |= S3C_RSTCON_PHY;
+	default:
+		break;
+	}
+
+	writel(phyclk, regs + S3C_PHYCLK);
+	/* set to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+	/* reset all ports of PHY and Link */
+	writel(rstcon, regs + S3C_RSTCON);
+	udelay(10);
+	rstcon &= ~S3C_RSTCON_PHY;
+	writel(rstcon, regs + S3C_RSTCON);
+}
+
+static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phypwr;
+
+	phypwr = readl(regs + S3C_PHYPWR);
+
+	switch (sphy->cpu_type) {
+	case TYPE_S3C64XX:
+		phypwr |= S3C_PHYPWR_NORMAL_MASK;
+		break;
+	case TYPE_EXYNOS4210:
+		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
+	default:
+		break;
+	}
+
+	/* unset to normal of PHY0 */
+	writel(phypwr, regs + S3C_PHYPWR);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int samsung_usbphy_init(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+	int ret = 0;
+
+	sphy = phy_to_sphy(phy);
+
+	/* Enable the phy clock */
+	ret = samsung_usbphy_clk_control(sphy, true);
+	if (ret) {
+		dev_err(sphy->dev, "phy clock enable failed\n");
+		return ret;
+	}
+
+	/* Disable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(false);
+
+	/* Initialize usb phy registers */
+	samsung_usbphy_enable(sphy);
+	return ret;
+}
+
+/*
+ * The function passed to the usb driver for phy shutdown
+ */
+static void samsung_usbphy_shutdown(struct usb_phy *phy)
+{
+	struct samsung_usbphy *sphy;
+
+	sphy = phy_to_sphy(phy);
+
+	/* De-initialize usb phy registers */
+	samsung_usbphy_disable(sphy);
+
+	/* Enable phy isolation */
+	if (sphy->plat && sphy->plat->pmu_isolation)
+		sphy->plat->pmu_isolation(true);
+
+	/* Disable the phy clock */
+	samsung_usbphy_clk_control(sphy, false);
+}
+
+static const struct of_device_id samsung_usbphy_dt_match[];
+
+static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	int data;
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(samsung_usbphy_dt_match,
+							pdev->dev.of_node);
+		data = (int) match->data;
+		return data;
+	}
+#endif
+	return platform_get_device_id(pdev)->driver_data;
+}
+
+static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy;
+	struct samsung_usbphy_data *pdata;
+	struct device *dev = &pdev->dev;
+	struct resource *phy_mem;
+	void __iomem	*phy_base;
+	int	ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
+		return -EINVAL;
+	}
+
+	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!phy_mem) {
+		dev_err(dev, "%s: missing mem resource\n", __func__);
+		return -ENODEV;
+	}
+
+	phy_base = devm_request_and_ioremap(dev, phy_mem);
+	if (!phy_base) {
+		dev_err(dev, "%s: register mapping failed\n", __func__);
+		return -ENXIO;
+	}
+
+	sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
+	if (!sphy)
+		return -ENOMEM;
+
+	sphy->dev		= &pdev->dev;
+	sphy->plat		= pdata;
+	sphy->regs		= phy_base;
+	sphy->phy.dev		= sphy->dev;
+	sphy->phy.label		= "samsung-usbphy";
+	sphy->phy.init		= samsung_usbphy_init;
+	sphy->phy.shutdown	= samsung_usbphy_shutdown;
+	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
+
+	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
+	if (ret)
+		goto err;
+
+	platform_set_drvdata(pdev, sphy);
+
+	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
+err:
+	return ret;
+}
+
+static int __exit samsung_usbphy_remove(struct platform_device *pdev)
+{
+	struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
+
+	usb_remove_phy(&sphy->phy);
+
+	if (sphy->clk) {
+		clk_put(sphy->clk);
+		sphy->clk = NULL;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id samsung_usbphy_dt_match[] = {
+	{
+		.compatible = "samsung,s3c64xx-usbphy",
+		.data = (void *)TYPE_S3C64XX,
+	}, {
+		.compatible = "samsung,exynos4210-usbphy",
+		.data = (void *)TYPE_EXYNOS4210,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
+#else
+#define samsung_usbphy_dt_match NULL
+#endif
+
+static struct platform_device_id samsung_usbphy_driver_ids[] = {
+	{
+		.name		= "s3c64xx-usbphy",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "exynos4210-usbphy",
+		.driver_data	= TYPE_EXYNOS4210,
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
+
+static struct platform_driver samsung_usbphy_driver = {
+	.probe		= samsung_usbphy_probe,
+	.remove		= __devexit_p(samsung_usbphy_remove),
+	.id_table	= samsung_usbphy_driver_ids,
+	.driver		= {
+		.name	= "samsung-usbphy",
+		.owner	= THIS_MODULE,
+		.of_match_table = samsung_usbphy_dt_match,
+	},
+};
+
+module_platform_driver(samsung_usbphy_driver);
+
+MODULE_DESCRIPTION("Samsung USB phy controller");
+MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-usbphy");
diff --git a/drivers/usb/phy/samsung-usbphy.h b/drivers/usb/phy/samsung-usbphy.h
new file mode 100644
index 0000000..093b1dc
--- /dev/null
+++ b/drivers/usb/phy/samsung-usbphy.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Yulgon Kim <yulgon.kim at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SAMSUNG_USBPHY_H
+#define __SAMSUNG_USBPHY_H
+
+#define S3C_PHYPWR				(0x00)
+
+#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
+#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
+/* For Exynos4 */
+#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
+#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
+
+#define S3C_PHYCLK				(0x04)
+
+#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
+#define S3C_PHYCLK_EXT_OSC			(1 << 5)
+#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
+#define S3C_PHYCLK_ID_PULL			(1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
+#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
+
+#define S3C_RSTCON				(0x08)
+
+#define S3C_RSTCON_PHYCLK			(1 << 2)
+#define S3C_RSTCON_HCLK				(1 << 1)
+#define S3C_RSTCON_PHY				(1 << 0)
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#endif /* __SAMSUNG_USBPHY_H */
diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
new file mode 100644
index 0000000..1bd24cb
--- /dev/null
+++ b/include/linux/platform_data/samsung-usbphy.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *		http://www.samsung.com/
+ * Author: Praveen Paneri <p.paneri at samsung.com>
+ *
+ * Defines platform data for samsung usb phy driver.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __SAMSUNG_USBPHY_PLATFORM_H
+#define __SAMSUNG_USBPHY_PLATFORM_H
+
+/**
+ * samsung_usbphy_data - Platform data for USB PHY driver.
+ * @pmu_isolation: Function to control usb phy isolation in PMU.
+ */
+struct samsung_usbphy_data {
+	void (*pmu_isolation)(int on);
+};
+
+extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
+
+#endif /* __SAMSUNG_USBPHY_PLATFORM_H */
-- 
1.7.1



From p.paneri at samsung.com  Fri Aug 10 03:10:29 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:29 +0530
Subject: [PATCH v4 3/5] ARM: S3C64XX: Removing old phy setup code
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344582631-13658-4-git-send-email-p.paneri@samsung.com>

This patch removes old phy code from platform side. 'setup-usb-phy.c'
will be used for providing transceiver platform data in next
patch. Not all of the platform data code is removed as there are others
making use of platform_data defined for hsotg. That can be removed once
all the SoCs start using the new transceiver for usb phy setup.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/mach-crag6410.c |    3 -
 arch/arm/mach-s3c64xx/mach-smartq.c   |    3 -
 arch/arm/mach-s3c64xx/mach-smdk6410.c |    3 -
 arch/arm/mach-s3c64xx/setup-usb-phy.c |   79 ---------------------------------
 4 files changed, 0 insertions(+), 88 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..b0f5baf 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,7 +31,6 @@
 #include <linux/spi/spi.h>
 
 #include <linux/i2c/pca953x.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #include <video/platform_lcd.h>
 
@@ -766,7 +765,6 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
-static struct s3c_hsotg_plat crag6410_hsotg_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -792,7 +790,6 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ceeb1de..7400da1 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,7 +18,6 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -187,7 +186,6 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
 	},
 };
 
-static struct s3c_hsotg_plat smartq_hsotg_pdata;
 
 static int __init smartq_lcd_setup_gpio(void)
 {
@@ -385,7 +383,6 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
-	s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..cbdc91b 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,7 +30,6 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/pwm_backlight.h>
-#include <linux/platform_data/s3c-hsotg.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -627,7 +626,6 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
-static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -657,7 +655,6 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
-	s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index f6757e0..7a09553 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,82 +9,3 @@
  *
  */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <mach/regs-sys.h>
-#include <plat/cpu.h>
-#include <plat/regs-usb-hsotg-phy.h>
-#include <plat/usb-phy.h>
-
-static int s3c_usb_otgphy_init(struct platform_device *pdev)
-{
-	struct clk *xusbxti;
-	u32 phyclk;
-
-	writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	/* set clock frequency for PLL */
-	phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
-
-	xusbxti = clk_get(&pdev->dev, "xusbxti");
-	if (xusbxti && !IS_ERR(xusbxti)) {
-		switch (clk_get_rate(xusbxti)) {
-		case 12 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= S3C_PHYCLK_CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
-		}
-		clk_put(xusbxti);
-	}
-
-	/* TODO: select external clock/oscillator */
-	writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
-
-	/* set to normal OTG PHY */
-	writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
-	mdelay(1);
-
-	/* reset OTG PHY and Link */
-	writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
-			S3C_RSTCON);
-	udelay(20);	/* at-least 10uS */
-	writel(0, S3C_RSTCON);
-
-	return 0;
-}
-
-static int s3c_usb_otgphy_exit(struct platform_device *pdev)
-{
-	writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
-				S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
-
-	writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
-
-	return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_init(pdev);
-
-	return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-	if (type == S5P_USB_PHY_DEVICE)
-		return s3c_usb_otgphy_exit(pdev);
-
-	return -EINVAL;
-}
-- 
1.7.1



From p.paneri at samsung.com  Fri Aug 10 03:10:30 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:30 +0530
Subject: [PATCH v4 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344582631-13658-5-git-send-email-p.paneri@samsung.com>

Adding platform device for samsung-usbphy driver. Enabling it for
s3c64xx based machines using s3c-hsotg.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
 arch/arm/mach-s3c64xx/mach-crag6410.c        |    4 +++
 arch/arm/mach-s3c64xx/mach-smartq.c          |    5 ++++
 arch/arm/mach-s3c64xx/mach-smdk6410.c        |    4 +++
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
 arch/arm/plat-samsung/devs.c                 |   33 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h    |    1 +
 arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
 8 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097b..dc482bb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -65,6 +65,7 @@
 
 #define S3C64XX_PA_NAND		(0x70200000)
 #define S3C64XX_PA_FB		(0x77100000)
+#define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
@@ -113,6 +114,7 @@
 #define S3C_PA_FB		S3C64XX_PA_FB
 #define S3C_PA_USBHOST		S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG	S3C64XX_PA_USB_HSOTG
+#define S3C_PA_USB_PHY		S3C64XX_PA_USB_HSPHY
 #define S3C_PA_RTC		S3C64XX_PA_RTC
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 #define S3C_PA_SPI0		S3C64XX_PA_SPI0
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index b0f5baf..a9c3b5e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,6 +31,7 @@
 #include <linux/spi/spi.h>
 
 #include <linux/i2c/pca953x.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <video/platform_lcd.h>
 
@@ -336,6 +337,7 @@ static struct platform_device wallvdd_device = {
 };
 
 static struct platform_device *crag6410_devices[] __initdata = {
+	&samsung_device_usbphy,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc2,
 	&s3c_device_i2c0,
@@ -765,6 +767,7 @@ static const struct gpio_led_platform_data gpio_leds_pdata = {
 	.num_leds = ARRAY_SIZE(gpio_leds),
 };
 
+static struct samsung_usbphy_data crag6410_usbphy_pdata;
 
 static void __init crag6410_machine_init(void)
 {
@@ -790,6 +793,7 @@ static void __init crag6410_machine_init(void)
 	s3c_i2c0_set_platdata(&i2c0_pdata);
 	s3c_i2c1_set_platdata(&i2c1_pdata);
 	s3c_fb_set_platdata(&crag6410_lcd_pdata);
+	samsung_usbphy_set_pdata(&crag6410_usbphy_pdata);
 
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 7400da1..0e75c36 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,6 +18,7 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -234,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[] __initdata = {
 };
 
 static struct platform_device *smartq_devices[] __initdata = {
+	&samsung_device_usbphy,
 	&s3c_device_hsmmc1,	/* Init iNAND first, ... */
 	&s3c_device_hsmmc0,	/* ... then the external SD card */
 	&s3c_device_hsmmc2,
@@ -380,9 +382,12 @@ void __init smartq_map_io(void)
 	smartq_lcd_mode_set();
 }
 
+static struct samsung_usbphy_data smartq_usbphy_pdata;
+
 void __init smartq_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
+	samsung_usbphy_set_pdata(&smartq_usbphy_pdata);
 	s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
 	s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
 	s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index cbdc91b..6c2ee6d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -263,6 +264,7 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
+	&samsung_device_usbphy,
 #ifdef CONFIG_SMDK6410_SD_CH0
 	&s3c_device_hsmmc0,
 #endif
@@ -626,6 +628,7 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
 	.pwm_id = 1,
 };
 
+static struct samsung_usbphy_data smdk6410_usbphy_pdata;
 
 static void __init smdk6410_map_io(void)
 {
@@ -655,6 +658,7 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+	samsung_usbphy_set_pdata(&smdk6410_usbphy_pdata);
 
 	samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 7a09553..3aee778 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -9,3 +9,17 @@
  *
  */
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	} else {
+		writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
+			S3C64XX_OTHERS);
+	}
+}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..9a796cb 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -31,6 +31,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_data/s3c-hsudc.h>
 #include <linux/platform_data/s3c-hsotg.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/irq.h>
 #include <asm/pmu.h>
@@ -1343,6 +1344,35 @@ struct platform_device s5p_device_mixer = {
 
 /* USB */
 
+#ifdef CONFIG_S3C_DEV_USB_HSOTG
+/* USB PHY*/
+static struct resource samsung_usbphy_resource[] = {
+	[0] = {
+		.start = S3C_PA_USB_PHY,
+		.end   = S3C_PA_USB_PHY + SZ_16 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device samsung_device_usbphy = {
+	.name		= "s3c64xx-usbphy",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(samsung_usbphy_resource),
+	.resource	= samsung_usbphy_resource,
+};
+
+void __init samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd)
+{
+	struct samsung_usbphy_data *npd;
+
+	npd = s3c_set_platdata(pd, sizeof(struct samsung_usbphy_data),
+			&samsung_device_usbphy);
+
+	if (!npd->pmu_isolation)
+		npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
+}
+#endif
+
 #ifdef CONFIG_S3C_DEV_USB_HOST
 static struct resource s3c_usb_resource[] = {
 	[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
@@ -1449,6 +1479,8 @@ struct platform_device s3c_device_usb_hsotg = {
 	},
 };
 
+#ifndef CONFIG_ARCH_S3C64XX
+/* TODO: To be removed later. Currently only S3C64XX is platform data free */
 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 {
 	struct s3c_hsotg_plat *npd;
@@ -1461,6 +1493,7 @@ void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
 	if (!npd->phy_exit)
 		npd->phy_exit = s5p_usb_phy_exit;
 }
+#endif
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5da4b4f..3849c88 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -138,6 +138,7 @@ extern struct platform_device exynos_device_drm;
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
+extern struct platform_device samsung_device_usbphy;
 
 /* s3c2440 specific devices */
 
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb..165ffe7 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern void s5p_usb_phy_pmu_isolation(int on);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
-- 
1.7.1



From p.paneri at samsung.com  Fri Aug 10 03:10:31 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:40:31 +0530
Subject: [PATCH v4 5/5] ARM: Exynos4210: Enabling samsung-usbphy driver
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <1344582631-13658-6-git-send-email-p.paneri@samsung.com>

Adding usbphy node for Exynos4210 along with the platform data.

Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi       |    5 +++++
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos4-dt.c  |    8 ++++++++
 arch/arm/mach-exynos/setup-usb-phy.c    |   13 +++++++++++++
 4 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..e28cf10 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -62,6 +62,11 @@
 		interrupts = <0 44 0>, <0 45 0>;
 	};
 
+	usbphy at 125B0000 {
+		compatible = "samsung,exynos4210-usbphy";
+		reg = <0x125B0000 0x100>;
+	};
+
 	keypad at 100A0000 {
 		compatible = "samsung,s5pv210-keypad";
 		reg = <0x100A0000 0x100>;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..0625c0a 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -234,6 +234,7 @@
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 #define S3C_PA_USB_HSOTG		EXYNOS4_PA_HSOTG
+#define S3C_PA_USB_PHY			EXYNOS4_PA_HSPHY
 
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0			EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..0739be8 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -13,6 +13,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -20,9 +21,14 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct samsung_usbphy_data exynos4_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -63,6 +69,8 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 				"exynos4210-spi.2", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-usbphy", EXYNOS4_PA_HSPHY,
+			"s3c-usbphy", &exynos4_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc56..1c62d20 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -221,3 +221,16 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 	return -EINVAL;
 }
+
+void s5p_usb_phy_pmu_isolation(int on)
+{
+	if (on) {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			& ~S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	} else {
+		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+			| S5P_USBDEVICE_PHY_ENABLE,
+				S5P_USBDEVICE_PHY_CONTROL);
+	}
+}
-- 
1.7.1



From balbi at ti.com  Fri Aug 10 03:04:08 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 10 Aug 2012 10:04:08 +0300
Subject: [PATCH v4 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
Message-ID: <20120810070407.GK1689@arwen.pp.htv.fi>

Hi,

On Fri, Aug 10, 2012 at 12:40:27PM +0530, Praveen Paneri wrote:
> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> smdk6410 and smdkv310. More SoCs can be brought under later.
> 
> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> Acked-by: Heiko Stuebner <heiko at sntech.de>

this looks good. Just 2 comments below.

> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
>  drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>  include/linux/platform_data/samsung-usbphy.h       |   27 ++
>  6 files changed, 438 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>  create mode 100644 drivers/usb/phy/samsung-usbphy.c
>  create mode 100644 drivers/usb/phy/samsung-usbphy.h
>  create mode 100644 include/linux/platform_data/samsung-usbphy.h
> 
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> new file mode 100644
> index 0000000..fefd9c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -0,0 +1,9 @@
> +* Samsung's usb phy transceiver
> +
> +The Samsung's phy transceiver is used for controlling usb otg phy for
> +s3c-hsotg usb device controller.
> +
> +Required properties:
> +- compatible : should be "samsung,exynos4210-usbphy"
> +- reg : base physical address of the phy registers and length of memory mapped
> +	region.
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index e7cf84f..d916477 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -15,3 +15,11 @@ config USB_ISP1301
>  
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called isp1301.
> +
> +config SAMSUNG_USBPHY
> +       bool "Samsung USB PHY controller Driver"
> +       depends on USB_S3C_HSOTG
> +       select USB_OTG_UTILS
> +       help
> +         Enable this to support Samsung USB phy controller for samsung
> +         SoCs.
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index eca095b..dfca70d 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -5,3 +5,4 @@
>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>  
>  obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
> +obj-$(CONFIG_SAMSUNG_USBPHY)		+= samsung-usbphy.o
> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
> new file mode 100644
> index 0000000..739b6c9
> --- /dev/null
> +++ b/drivers/usb/phy/samsung-usbphy.c
> @@ -0,0 +1,345 @@
> +/* linux/drivers/usb/phy/samsung-usbphy.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * Author: Praveen Paneri <p.paneri at samsung.com>
> + *
> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +*/
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/usb/otg.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> +
> +#include "samsung-usbphy.h"
> +
> +enum samsung_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_EXYNOS4210,
> +};
> +
> +/*
> + * struct samsung_usbphy - transceiver driver state
> + * @phy: transceiver structure
> + * @plat: platform data
> + * @dev: The parent device supplied to the probe function
> + * @clk: usb phy clock
> + * @regs: usb phy register memory base
> + * @cpu_type: machine identifier
> + */
> +struct samsung_usbphy {
> +	struct usb_phy	phy;
> +	struct samsung_usbphy_data *plat;
> +	struct device	*dev;
> +	struct clk	*clk;
> +	void __iomem	*regs;
> +	int		cpu_type;
> +};
> +
> +#define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
> +
> +/*
> + * Enables or disables the phy clock
> + * returns 0 on success else the error
> + */
> +static int samsung_usbphy_clk_control(struct samsung_usbphy *sphy, bool on)
> +{
> +	if (on) {
> +		if (!sphy->clk) {
> +			sphy->clk = clk_get(sphy->dev, "otg");
> +			if (IS_ERR(sphy->clk)) {
> +				dev_err(sphy->dev, "Failed to get otg clock\n");
> +				return PTR_ERR(sphy->clk);
> +			}
> +		}
> +		clk_enable(sphy->clk);
> +	} else {
> +		clk_disable(sphy->clk);
> +		clk_put(sphy->clk);
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Returns reference clock frequency
> + */
> +static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
> +{
> +	struct clk *ref_clk;
> +	int refclk_freq = 0;
> +
> +	ref_clk = clk_get(sphy->dev, "xusbxti");
> +	if (IS_ERR(ref_clk)) {
> +		dev_err(sphy->dev, "Failed to get reference clock\n");
> +		return PTR_ERR(ref_clk);
> +	}
> +
> +	switch (clk_get_rate(ref_clk)) {
> +	case 12 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> +		break;
> +	case 24 * MHZ:
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> +		break;
> +	default:
> +	case 48 * MHZ:
> +		/* default reference clock */
> +		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> +		break;
> +	}
> +	clk_put(ref_clk);
> +
> +	return refclk_freq;
> +}
> +
> +static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
> +{
> +	void __iomem *regs = sphy->regs;
> +	u32 phypwr;
> +	u32 phyclk;
> +	u32 rstcon;
> +
> +	/* set clock frequency for PLL */
> +	phyclk = samsung_usbphy_get_refclk_freq(sphy);
> +	phypwr = readl(regs + S3C_PHYPWR);
> +	rstcon = readl(regs + S3C_RSTCON);
> +
> +	switch (sphy->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
> +		phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
> +		rstcon |= S3C_RSTCON_PHY;
> +	default:
> +		break;
> +	}
> +
> +	writel(phyclk, regs + S3C_PHYCLK);
> +	/* set to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +	/* reset all ports of PHY and Link */
> +	writel(rstcon, regs + S3C_RSTCON);
> +	udelay(10);
> +	rstcon &= ~S3C_RSTCON_PHY;
> +	writel(rstcon, regs + S3C_RSTCON);
> +}
> +
> +static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
> +{
> +	void __iomem *regs = sphy->regs;
> +	u32 phypwr;
> +
> +	phypwr = readl(regs + S3C_PHYPWR);
> +
> +	switch (sphy->cpu_type) {
> +	case TYPE_S3C64XX:
> +		phypwr |= S3C_PHYPWR_NORMAL_MASK;
> +		break;
> +	case TYPE_EXYNOS4210:
> +		phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
> +	default:
> +		break;
> +	}
> +
> +	/* unset to normal of PHY0 */
> +	writel(phypwr, regs + S3C_PHYPWR);
> +}
> +
> +/*
> + * The function passed to the usb driver for phy initialization
> + */
> +static int samsung_usbphy_init(struct usb_phy *phy)
> +{
> +	struct samsung_usbphy *sphy;
> +	int ret = 0;
> +
> +	sphy = phy_to_sphy(phy);
> +
> +	/* Enable the phy clock */
> +	ret = samsung_usbphy_clk_control(sphy, true);
> +	if (ret) {
> +		dev_err(sphy->dev, "phy clock enable failed\n");
> +		return ret;
> +	}
> +
> +	/* Disable phy isolation */
> +	if (sphy->plat && sphy->plat->pmu_isolation)
> +		sphy->plat->pmu_isolation(false);
> +
> +	/* Initialize usb phy registers */
> +	samsung_usbphy_enable(sphy);
> +	return ret;
> +}
> +
> +/*
> + * The function passed to the usb driver for phy shutdown
> + */
> +static void samsung_usbphy_shutdown(struct usb_phy *phy)
> +{
> +	struct samsung_usbphy *sphy;
> +
> +	sphy = phy_to_sphy(phy);
> +
> +	/* De-initialize usb phy registers */
> +	samsung_usbphy_disable(sphy);
> +
> +	/* Enable phy isolation */
> +	if (sphy->plat && sphy->plat->pmu_isolation)
> +		sphy->plat->pmu_isolation(true);
> +
> +	/* Disable the phy clock */
> +	samsung_usbphy_clk_control(sphy, false);
> +}
> +
> +static const struct of_device_id samsung_usbphy_dt_match[];
> +
> +static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
> +{
> +#ifdef CONFIG_OF
> +	int data;
> +	if (pdev->dev.of_node) {
> +		const struct of_device_id *match;
> +		match = of_match_node(samsung_usbphy_dt_match,
> +							pdev->dev.of_node);
> +		data = (int) match->data;
> +		return data;
> +	}
> +#endif
> +	return platform_get_device_id(pdev)->driver_data;
> +}
> +
> +static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
> +{
> +	struct samsung_usbphy *sphy;
> +	struct samsung_usbphy_data *pdata;
> +	struct device *dev = &pdev->dev;
> +	struct resource *phy_mem;
> +	void __iomem	*phy_base;
> +	int	ret;
> +
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!phy_mem) {
> +		dev_err(dev, "%s: missing mem resource\n", __func__);
> +		return -ENODEV;
> +	}
> +
> +	phy_base = devm_request_and_ioremap(dev, phy_mem);
> +	if (!phy_base) {
> +		dev_err(dev, "%s: register mapping failed\n", __func__);
> +		return -ENXIO;
> +	}
> +
> +	sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
> +	if (!sphy)
> +		return -ENOMEM;
> +
> +	sphy->dev		= &pdev->dev;
> +	sphy->plat		= pdata;
> +	sphy->regs		= phy_base;
> +	sphy->phy.dev		= sphy->dev;
> +	sphy->phy.label		= "samsung-usbphy";
> +	sphy->phy.init		= samsung_usbphy_init;
> +	sphy->phy.shutdown	= samsung_usbphy_shutdown;
> +	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
> +
> +	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
> +	if (ret)
> +		goto err;
> +
> +	platform_set_drvdata(pdev, sphy);
> +
> +	dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");

please avoid dev_info() at the end of probe. It just makes booting
noisier.

> +err:
> +	return ret;
> +}
> +
> +static int __exit samsung_usbphy_remove(struct platform_device *pdev)
> +{
> +	struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
> +
> +	usb_remove_phy(&sphy->phy);
> +
> +	if (sphy->clk) {
> +		clk_put(sphy->clk);
> +		sphy->clk = NULL;
> +	}
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF
> +static const struct of_device_id samsung_usbphy_dt_match[] = {
> +	{
> +		.compatible = "samsung,s3c64xx-usbphy",
> +		.data = (void *)TYPE_S3C64XX,
> +	}, {
> +		.compatible = "samsung,exynos4210-usbphy",
> +		.data = (void *)TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
> +#else
> +#define samsung_usbphy_dt_match NULL
> +#endif
> +
> +static struct platform_device_id samsung_usbphy_driver_ids[] = {
> +	{
> +		.name		= "s3c64xx-usbphy",
> +		.driver_data	= TYPE_S3C64XX,
> +	}, {
> +		.name		= "exynos4210-usbphy",
> +		.driver_data	= TYPE_EXYNOS4210,
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
> +
> +static struct platform_driver samsung_usbphy_driver = {
> +	.probe		= samsung_usbphy_probe,
> +	.remove		= __devexit_p(samsung_usbphy_remove),
> +	.id_table	= samsung_usbphy_driver_ids,
> +	.driver		= {
> +		.name	= "samsung-usbphy",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = samsung_usbphy_dt_match,
> +	},
> +};
> +
> +module_platform_driver(samsung_usbphy_driver);
> +
> +MODULE_DESCRIPTION("Samsung USB phy controller");
> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:samsung-usbphy");
> diff --git a/drivers/usb/phy/samsung-usbphy.h b/drivers/usb/phy/samsung-usbphy.h
> new file mode 100644
> index 0000000..093b1dc
> --- /dev/null
> +++ b/drivers/usb/phy/samsung-usbphy.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + * Author: Praveen Paneri <p.paneri at samsung.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#ifndef __SAMSUNG_USBPHY_H
> +#define __SAMSUNG_USBPHY_H
> +
> +#define S3C_PHYPWR				(0x00)
> +
> +#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
> +#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
> +#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
> +#define S3C_PHYPWR_FORCE_SUSPEND		(1 << 1)
> +/* For Exynos4 */
> +#define EXYNOS4_PHYPWR_NORMAL_MASK		(0x39 << 0)
> +#define EXYNOS4_PHYPWR_SLEEP			(1 << 5)
> +
> +#define S3C_PHYCLK				(0x04)
> +
> +#define S3C_PHYCLK_MODE_SERIAL			(1 << 6)
> +#define S3C_PHYCLK_EXT_OSC			(1 << 5)
> +#define S3C_PHYCLK_COMMON_ON_N			(1 << 4)
> +#define S3C_PHYCLK_ID_PULL			(1 << 2)
> +#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
> +#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
> +#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
> +#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
> +#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)
> +
> +#define S3C_RSTCON				(0x08)
> +
> +#define S3C_RSTCON_PHYCLK			(1 << 2)
> +#define S3C_RSTCON_HCLK				(1 << 1)
> +#define S3C_RSTCON_PHY				(1 << 0)
> +
> +#ifndef MHZ
> +#define MHZ (1000*1000)
> +#endif

this header is so small that it doesn't make sense to have it. pleae
move these macros to C source file itself ;-)

-- 
balbi
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From balbi at ti.com  Fri Aug 10 03:06:24 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 10 Aug 2012 10:06:24 +0300
Subject: [PATCH v4 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
Message-ID: <20120810070623.GL1689@arwen.pp.htv.fi>

On Fri, Aug 10, 2012 at 12:40:26PM +0530, Praveen Paneri wrote:
> Changes from v3:
> Replaced susbsys_initcall()/module_exit() by module_platform_driver().
> Accordingly in the hsotg driver returned -EPROBE_DEFER until phy driver
> is registered
> Removed unnecessary devm_usb_put_phy() call from the hsotg driver remove.
> 
> Changes from v2:
> Changed the driver filenames to samsung-usbphy
> Changed 's3c' to 'samsung' for platform device as well as platform data
> Moved platform data structure to a separate file
> Rectified coding style related errors
> 
> Changes from v1:
> Rebased patches to latest usb-next branch
> Changed the name 'sec_usbphy' to 'samsung_usbphy'
> 
> This patch set introduces a phy driver for samsung SoCs. It uses the existing
> transceiver infrastructure to provide phy control functions. Use of this driver
> can be extended for usb host phy as well. Over the period of time all the phy
> related code for most of the samsung SoCs can be integrated here.
> Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
> when they start supporting this phy driver. 
> This driver is tested with smdk6410 and Exynos4210(with DT).
> 
> Praveen Paneri (5):
>   usb: phy: samsung: Introducing usb phy driver for hsotg
>   usb: s3c-hsotg: Adding phy driver support
>   ARM: S3C64XX: Removing old phy setup code
>   ARM: S3C64XX: Enabling samsung-usbphy driver
>   ARM: Exynos4210: Enabling samsung-usbphy driver

just one idea. It looks like after introducing the PHY, you converted
all users to create the phy device. I wonder if you should have a
patch 6/6 which will remove pdata->init support from s3c_hsotg.c and
stick to using phy driver.

-- 
balbi
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From p.paneri at samsung.com  Fri Aug 10 03:16:57 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 12:46:57 +0530
Subject: [PATCH v4 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <20120810070407.GK1689@arwen.pp.htv.fi>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
 <20120810070407.GK1689@arwen.pp.htv.fi>
Message-ID: <CAD6zSYMByoyEw4ugYDwU9+Lh1dKd4ua=2a8F2cmO4aQCNAosiw@mail.gmail.com>

On Fri, Aug 10, 2012 at 12:34 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Fri, Aug 10, 2012 at 12:40:27PM +0530, Praveen Paneri wrote:
>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> Acked-by: Heiko Stuebner <heiko at sntech.de>
>
> this looks good. Just 2 comments below.
>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
>>  drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>>  include/linux/platform_data/samsung-usbphy.h       |   27 ++
>>  6 files changed, 438 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>  create mode 100644 drivers/usb/phy/samsung-usbphy.c
>>  create mode 100644 drivers/usb/phy/samsung-usbphy.h
>>  create mode 100644 include/linux/platform_data/samsung-usbphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> new file mode 100644
>> index 0000000..fefd9c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -0,0 +1,9 @@
>> +* Samsung's usb phy transceiver
>> +
>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> +s3c-hsotg usb device controller.
>> +
>> +Required properties:
>> +- compatible : should be "samsung,exynos4210-usbphy"
>> +- reg : base physical address of the phy registers and length of memory mapped
>> +     region.
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index e7cf84f..d916477 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>
>>         To compile this driver as a module, choose M here: the
>>         module will be called isp1301.
>> +
>> +config SAMSUNG_USBPHY
>> +       bool "Samsung USB PHY controller Driver"
>> +       depends on USB_S3C_HSOTG
>> +       select USB_OTG_UTILS
>> +       help
>> +         Enable this to support Samsung USB phy controller for samsung
>> +         SoCs.
>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> index eca095b..dfca70d 100644
>> --- a/drivers/usb/phy/Makefile
>> +++ b/drivers/usb/phy/Makefile
>> @@ -5,3 +5,4 @@
>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>
>>  obj-$(CONFIG_USB_ISP1301)            += isp1301.o
>> +obj-$(CONFIG_SAMSUNG_USBPHY)         += samsung-usbphy.o
>> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
>> new file mode 100644
>> index 0000000..739b6c9
>> --- /dev/null
>> +++ b/drivers/usb/phy/samsung-usbphy.c
>> @@ -0,0 +1,345 @@
>> +/* linux/drivers/usb/phy/samsung-usbphy.c
>> + *
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + *              http://www.samsung.com
>> + *
>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> + *
>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> +*/
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/usb/otg.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>> +
>> +#include "samsung-usbphy.h"
>> +
>> +enum samsung_cpu_type {
>> +     TYPE_S3C64XX,
>> +     TYPE_EXYNOS4210,
>> +};
>> +
>> +/*
>> + * struct samsung_usbphy - transceiver driver state
>> + * @phy: transceiver structure
>> + * @plat: platform data
>> + * @dev: The parent device supplied to the probe function
>> + * @clk: usb phy clock
>> + * @regs: usb phy register memory base
>> + * @cpu_type: machine identifier
>> + */
>> +struct samsung_usbphy {
>> +     struct usb_phy  phy;
>> +     struct samsung_usbphy_data *plat;
>> +     struct device   *dev;
>> +     struct clk      *clk;
>> +     void __iomem    *regs;
>> +     int             cpu_type;
>> +};
>> +
>> +#define phy_to_sphy(x)               container_of((x), struct samsung_usbphy, phy)
>> +
>> +/*
>> + * Enables or disables the phy clock
>> + * returns 0 on success else the error
>> + */
>> +static int samsung_usbphy_clk_control(struct samsung_usbphy *sphy, bool on)
>> +{
>> +     if (on) {
>> +             if (!sphy->clk) {
>> +                     sphy->clk = clk_get(sphy->dev, "otg");
>> +                     if (IS_ERR(sphy->clk)) {
>> +                             dev_err(sphy->dev, "Failed to get otg clock\n");
>> +                             return PTR_ERR(sphy->clk);
>> +                     }
>> +             }
>> +             clk_enable(sphy->clk);
>> +     } else {
>> +             clk_disable(sphy->clk);
>> +             clk_put(sphy->clk);
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +/*
>> + * Returns reference clock frequency
>> + */
>> +static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
>> +{
>> +     struct clk *ref_clk;
>> +     int refclk_freq = 0;
>> +
>> +     ref_clk = clk_get(sphy->dev, "xusbxti");
>> +     if (IS_ERR(ref_clk)) {
>> +             dev_err(sphy->dev, "Failed to get reference clock\n");
>> +             return PTR_ERR(ref_clk);
>> +     }
>> +
>> +     switch (clk_get_rate(ref_clk)) {
>> +     case 12 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> +             break;
>> +     case 24 * MHZ:
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> +             break;
>> +     default:
>> +     case 48 * MHZ:
>> +             /* default reference clock */
>> +             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> +             break;
>> +     }
>> +     clk_put(ref_clk);
>> +
>> +     return refclk_freq;
>> +}
>> +
>> +static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
>> +{
>> +     void __iomem *regs = sphy->regs;
>> +     u32 phypwr;
>> +     u32 phyclk;
>> +     u32 rstcon;
>> +
>> +     /* set clock frequency for PLL */
>> +     phyclk = samsung_usbphy_get_refclk_freq(sphy);
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +     rstcon = readl(regs + S3C_RSTCON);
>> +
>> +     switch (sphy->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phyclk &= ~(S3C_PHYCLK_COMMON_ON_N);
>> +             phypwr &= ~S3C_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr &= ~EXYNOS4_PHYPWR_NORMAL_MASK;
>> +             rstcon |= S3C_RSTCON_PHY;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     writel(phyclk, regs + S3C_PHYCLK);
>> +     /* set to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +     /* reset all ports of PHY and Link */
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +     udelay(10);
>> +     rstcon &= ~S3C_RSTCON_PHY;
>> +     writel(rstcon, regs + S3C_RSTCON);
>> +}
>> +
>> +static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
>> +{
>> +     void __iomem *regs = sphy->regs;
>> +     u32 phypwr;
>> +
>> +     phypwr = readl(regs + S3C_PHYPWR);
>> +
>> +     switch (sphy->cpu_type) {
>> +     case TYPE_S3C64XX:
>> +             phypwr |= S3C_PHYPWR_NORMAL_MASK;
>> +             break;
>> +     case TYPE_EXYNOS4210:
>> +             phypwr |= EXYNOS4_PHYPWR_NORMAL_MASK;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     /* unset to normal of PHY0 */
>> +     writel(phypwr, regs + S3C_PHYPWR);
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy initialization
>> + */
>> +static int samsung_usbphy_init(struct usb_phy *phy)
>> +{
>> +     struct samsung_usbphy *sphy;
>> +     int ret = 0;
>> +
>> +     sphy = phy_to_sphy(phy);
>> +
>> +     /* Enable the phy clock */
>> +     ret = samsung_usbphy_clk_control(sphy, true);
>> +     if (ret) {
>> +             dev_err(sphy->dev, "phy clock enable failed\n");
>> +             return ret;
>> +     }
>> +
>> +     /* Disable phy isolation */
>> +     if (sphy->plat && sphy->plat->pmu_isolation)
>> +             sphy->plat->pmu_isolation(false);
>> +
>> +     /* Initialize usb phy registers */
>> +     samsung_usbphy_enable(sphy);
>> +     return ret;
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy shutdown
>> + */
>> +static void samsung_usbphy_shutdown(struct usb_phy *phy)
>> +{
>> +     struct samsung_usbphy *sphy;
>> +
>> +     sphy = phy_to_sphy(phy);
>> +
>> +     /* De-initialize usb phy registers */
>> +     samsung_usbphy_disable(sphy);
>> +
>> +     /* Enable phy isolation */
>> +     if (sphy->plat && sphy->plat->pmu_isolation)
>> +             sphy->plat->pmu_isolation(true);
>> +
>> +     /* Disable the phy clock */
>> +     samsung_usbphy_clk_control(sphy, false);
>> +}
>> +
>> +static const struct of_device_id samsung_usbphy_dt_match[];
>> +
>> +static inline int samsung_usbphy_get_driver_data(struct platform_device *pdev)
>> +{
>> +#ifdef CONFIG_OF
>> +     int data;
>> +     if (pdev->dev.of_node) {
>> +             const struct of_device_id *match;
>> +             match = of_match_node(samsung_usbphy_dt_match,
>> +                                                     pdev->dev.of_node);
>> +             data = (int) match->data;
>> +             return data;
>> +     }
>> +#endif
>> +     return platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> +static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
>> +{
>> +     struct samsung_usbphy *sphy;
>> +     struct samsung_usbphy_data *pdata;
>> +     struct device *dev = &pdev->dev;
>> +     struct resource *phy_mem;
>> +     void __iomem    *phy_base;
>> +     int     ret;
>> +
>> +     pdata = pdev->dev.platform_data;
>> +     if (!pdata) {
>> +             dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
>> +             return -EINVAL;
>> +     }
>> +
>> +     phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     if (!phy_mem) {
>> +             dev_err(dev, "%s: missing mem resource\n", __func__);
>> +             return -ENODEV;
>> +     }
>> +
>> +     phy_base = devm_request_and_ioremap(dev, phy_mem);
>> +     if (!phy_base) {
>> +             dev_err(dev, "%s: register mapping failed\n", __func__);
>> +             return -ENXIO;
>> +     }
>> +
>> +     sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
>> +     if (!sphy)
>> +             return -ENOMEM;
>> +
>> +     sphy->dev               = &pdev->dev;
>> +     sphy->plat              = pdata;
>> +     sphy->regs              = phy_base;
>> +     sphy->phy.dev           = sphy->dev;
>> +     sphy->phy.label         = "samsung-usbphy";
>> +     sphy->phy.init          = samsung_usbphy_init;
>> +     sphy->phy.shutdown      = samsung_usbphy_shutdown;
>> +     sphy->cpu_type          = samsung_usbphy_get_driver_data(pdev);
>> +
>> +     ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
>> +     if (ret)
>> +             goto err;
>> +
>> +     platform_set_drvdata(pdev, sphy);
>> +
>> +     dev_info(&pdev->dev, "Initialized samsung USB OTG PHY module\n");
>
> please avoid dev_info() at the end of probe. It just makes booting
> noisier.
>
>> +err:
>> +     return ret;
>> +}
>> +
>> +static int __exit samsung_usbphy_remove(struct platform_device *pdev)
>> +{
>> +     struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
>> +
>> +     usb_remove_phy(&sphy->phy);
>> +
>> +     if (sphy->clk) {
>> +             clk_put(sphy->clk);
>> +             sphy->clk = NULL;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id samsung_usbphy_dt_match[] = {
>> +     {
>> +             .compatible = "samsung,s3c64xx-usbphy",
>> +             .data = (void *)TYPE_S3C64XX,
>> +     }, {
>> +             .compatible = "samsung,exynos4210-usbphy",
>> +             .data = (void *)TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
>> +#else
>> +#define samsung_usbphy_dt_match NULL
>> +#endif
>> +
>> +static struct platform_device_id samsung_usbphy_driver_ids[] = {
>> +     {
>> +             .name           = "s3c64xx-usbphy",
>> +             .driver_data    = TYPE_S3C64XX,
>> +     }, {
>> +             .name           = "exynos4210-usbphy",
>> +             .driver_data    = TYPE_EXYNOS4210,
>> +     },
>> +     {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
>> +
>> +static struct platform_driver samsung_usbphy_driver = {
>> +     .probe          = samsung_usbphy_probe,
>> +     .remove         = __devexit_p(samsung_usbphy_remove),
>> +     .id_table       = samsung_usbphy_driver_ids,
>> +     .driver         = {
>> +             .name   = "samsung-usbphy",
>> +             .owner  = THIS_MODULE,
>> +             .of_match_table = samsung_usbphy_dt_match,
>> +     },
>> +};
>> +
>> +module_platform_driver(samsung_usbphy_driver);
>> +
>> +MODULE_DESCRIPTION("Samsung USB phy controller");
>> +MODULE_AUTHOR("Praveen Paneri <p.paneri at samsung.com>");
>> +MODULE_LICENSE("GPL");
>> +MODULE_ALIAS("platform:samsung-usbphy");
>> diff --git a/drivers/usb/phy/samsung-usbphy.h b/drivers/usb/phy/samsung-usbphy.h
>> new file mode 100644
>> index 0000000..093b1dc
>> --- /dev/null
>> +++ b/drivers/usb/phy/samsung-usbphy.h
>> @@ -0,0 +1,48 @@
>> +/*
>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> + * Author: Yulgon Kim <yulgon.kim at samsung.com>
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> + *
>> + * This program is free software; you can redistribute  it and/or modify it
>> + * under  the terms of  the GNU General  Public License as published by the
>> + * Free Software Foundation;  either version 2 of the  License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#ifndef __SAMSUNG_USBPHY_H
>> +#define __SAMSUNG_USBPHY_H
>> +
>> +#define S3C_PHYPWR                           (0x00)
>> +
>> +#define S3C_PHYPWR_NORMAL_MASK                       (0x19 << 0)
>> +#define S3C_PHYPWR_OTG_DISABLE                       (1 << 4)
>> +#define S3C_PHYPWR_ANALOG_POWERDOWN          (1 << 3)
>> +#define S3C_PHYPWR_FORCE_SUSPEND             (1 << 1)
>> +/* For Exynos4 */
>> +#define EXYNOS4_PHYPWR_NORMAL_MASK           (0x39 << 0)
>> +#define EXYNOS4_PHYPWR_SLEEP                 (1 << 5)
>> +
>> +#define S3C_PHYCLK                           (0x04)
>> +
>> +#define S3C_PHYCLK_MODE_SERIAL                       (1 << 6)
>> +#define S3C_PHYCLK_EXT_OSC                   (1 << 5)
>> +#define S3C_PHYCLK_COMMON_ON_N                       (1 << 4)
>> +#define S3C_PHYCLK_ID_PULL                   (1 << 2)
>> +#define S3C_PHYCLK_CLKSEL_MASK                       (0x3 << 0)
>> +#define S3C_PHYCLK_CLKSEL_SHIFT                      (0)
>> +#define S3C_PHYCLK_CLKSEL_48M                        (0x0 << 0)
>> +#define S3C_PHYCLK_CLKSEL_12M                        (0x2 << 0)
>> +#define S3C_PHYCLK_CLKSEL_24M                        (0x3 << 0)
>> +
>> +#define S3C_RSTCON                           (0x08)
>> +
>> +#define S3C_RSTCON_PHYCLK                    (1 << 2)
>> +#define S3C_RSTCON_HCLK                              (1 << 1)
>> +#define S3C_RSTCON_PHY                               (1 << 0)
>> +
>> +#ifndef MHZ
>> +#define MHZ (1000*1000)
>> +#endif
>
> this header is so small that it doesn't make sense to have it. pleae
> move these macros to C source file itself ;-)

Thanks! I will do that.

Praveen
>
> --
> balbi


From kishon at ti.com  Fri Aug 10 03:19:08 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Fri, 10 Aug 2012 12:49:08 +0530
Subject: [PATCH v4 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
Message-ID: <CAAe_U6K=h7gP+fTQTkzP_WQfccVMYhG+UtsLprDMrsozuBywoQ@mail.gmail.com>

Hi,

On Fri, Aug 10, 2012 at 12:40 PM, Praveen Paneri <p.paneri at samsung.com> wrote:
> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
> phy_init and phy_shutdown functions to enable/disable phy. Tested with
> smdk6410 and smdkv310. More SoCs can be brought under later.
>
> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
> Acked-by: Heiko Stuebner <heiko at sntech.de>
> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>  drivers/usb/phy/Kconfig                            |    8 +
>  drivers/usb/phy/Makefile                           |    1 +
>  drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
>  drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>  include/linux/platform_data/samsung-usbphy.h       |   27 ++
>  6 files changed, 438 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>  create mode 100644 drivers/usb/phy/samsung-usbphy.c
>  create mode 100644 drivers/usb/phy/samsung-usbphy.h
>  create mode 100644 include/linux/platform_data/samsung-usbphy.h
>
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> new file mode 100644
> index 0000000..fefd9c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -0,0 +1,9 @@
> +* Samsung's usb phy transceiver
> +
> +The Samsung's phy transceiver is used for controlling usb otg phy for
> +s3c-hsotg usb device controller.
> +
> +Required properties:
> +- compatible : should be "samsung,exynos4210-usbphy"
> +- reg : base physical address of the phy registers and length of memory mapped
> +       region.
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index e7cf84f..d916477 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -15,3 +15,11 @@ config USB_ISP1301
>
>           To compile this driver as a module, choose M here: the
>           module will be called isp1301.
> +
> +config SAMSUNG_USBPHY
> +       bool "Samsung USB PHY controller Driver"
> +       depends on USB_S3C_HSOTG
> +       select USB_OTG_UTILS
> +       help
> +         Enable this to support Samsung USB phy controller for samsung
> +         SoCs.
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index eca095b..dfca70d 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -5,3 +5,4 @@
>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>
>  obj-$(CONFIG_USB_ISP1301)              += isp1301.o
> +obj-$(CONFIG_SAMSUNG_USBPHY)           += samsung-usbphy.o
> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
> new file mode 100644
> index 0000000..739b6c9
> --- /dev/null
> +++ b/drivers/usb/phy/samsung-usbphy.c
> @@ -0,0 +1,345 @@
> +/* linux/drivers/usb/phy/samsung-usbphy.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *              http://www.samsung.com
> + *
> + * Author: Praveen Paneri <p.paneri at samsung.com>
> + *
> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

I suggest you drop that last paragraph unless you want to keep track
of Free Software Foundation office. Right now it is 51 Franklin
Street, Boston (http://www.fsf.org/about/contact/) :-)

-Kishon


From p.paneri at samsung.com  Fri Aug 10 03:34:48 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 13:04:48 +0530
Subject: [PATCH v4 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <20120810070623.GL1689@arwen.pp.htv.fi>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <20120810070623.GL1689@arwen.pp.htv.fi>
Message-ID: <CAD6zSYPT_K9bTP=8k-Q+5N-yAVjDx86Haay27OLuPsqz38pczA@mail.gmail.com>

On Fri, Aug 10, 2012 at 12:36 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Fri, Aug 10, 2012 at 12:40:26PM +0530, Praveen Paneri wrote:
>> Changes from v3:
>> Replaced susbsys_initcall()/module_exit() by module_platform_driver().
>> Accordingly in the hsotg driver returned -EPROBE_DEFER until phy driver
>> is registered
>> Removed unnecessary devm_usb_put_phy() call from the hsotg driver remove.
>>
>> Changes from v2:
>> Changed the driver filenames to samsung-usbphy
>> Changed 's3c' to 'samsung' for platform device as well as platform data
>> Moved platform data structure to a separate file
>> Rectified coding style related errors
>>
>> Changes from v1:
>> Rebased patches to latest usb-next branch
>> Changed the name 'sec_usbphy' to 'samsung_usbphy'
>>
>> This patch set introduces a phy driver for samsung SoCs. It uses the existing
>> transceiver infrastructure to provide phy control functions. Use of this driver
>> can be extended for usb host phy as well. Over the period of time all the phy
>> related code for most of the samsung SoCs can be integrated here.
>> Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
>> when they start supporting this phy driver.
>> This driver is tested with smdk6410 and Exynos4210(with DT).
>>
>> Praveen Paneri (5):
>>   usb: phy: samsung: Introducing usb phy driver for hsotg
>>   usb: s3c-hsotg: Adding phy driver support
>>   ARM: S3C64XX: Removing old phy setup code
>>   ARM: S3C64XX: Enabling samsung-usbphy driver
>>   ARM: Exynos4210: Enabling samsung-usbphy driver
>
> just one idea. It looks like after introducing the PHY, you converted
> all users to create the phy device. I wonder if you should have a
Not all
> patch 6/6 which will remove pdata->init support from s3c_hsotg.c and
> stick to using phy driver.
This will make the hsotg driver unusable for others (in mach-s5pv210
and mach-exynos) which are not supported in the phy driver as of now.
My idea was to drop the pdata->init when the last user gets the phy
support. Need some time for that :-)

Praveen
>
> --
> balbi


From arnd at arndb.de  Fri Aug 10 03:34:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 07:34:46 +0000
Subject: [PATCH 10/11] spi/s3c64xx: improve error handling
In-Reply-To: <0de501cd76c2$ea07dfd0$be179f70$%kim@samsung.com>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-11-git-send-email-arnd@arndb.de>
 <0de501cd76c2$ea07dfd0$be179f70$%kim@samsung.com>
Message-ID: <201208100734.47339.arnd@arndb.de>

On Friday 10 August 2012, Kukjin Kim wrote:

> BTW for same reason, probably, we need following fix?
> 
>  arch/arm/mach-tegra/tegra2_emc.c             |    4 ++--
>  arch/c6x/kernel/setup.c                      |    2 +-
>  arch/powerpc/kernel/ibmebus.c                |    2 +-
>  arch/powerpc/kernel/pci_of_scan.c            |    2 +-
>  arch/powerpc/kernel/prom.c                   |    2 +-
>  arch/powerpc/kernel/rtas_pci.c               |    2 +-
>  arch/powerpc/kernel/vio.c                    |    2 +-
>  arch/powerpc/platforms/44x/warp.c            |    2 +-
> ...

Actually not. The difference is that only s3c64xx_get_slave_ctrldata
accesses the node pointer outside of the look (after break).
This fails when there are no child nodes at all. In the other
cases, the only use of the node pointer is inside the loop,
where it is guaranteed to be valid.

	Arnd


From p.paneri at samsung.com  Fri Aug 10 03:36:42 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 13:06:42 +0530
Subject: [PATCH v4 1/5] usb: phy: samsung: Introducing usb phy driver for
 hsotg
In-Reply-To: <CAAe_U6K=h7gP+fTQTkzP_WQfccVMYhG+UtsLprDMrsozuBywoQ@mail.gmail.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <1344582631-13658-2-git-send-email-p.paneri@samsung.com>
 <CAAe_U6K=h7gP+fTQTkzP_WQfccVMYhG+UtsLprDMrsozuBywoQ@mail.gmail.com>
Message-ID: <CAD6zSYOSfkuEO7Bv+AFLrHKiFMj77v+EMYVjGrAytGTCurLPuw@mail.gmail.com>

On Fri, Aug 10, 2012 at 12:49 PM, ABRAHAM, KISHON VIJAY <kishon at ti.com> wrote:
> Hi,
>
> On Fri, Aug 10, 2012 at 12:40 PM, Praveen Paneri <p.paneri at samsung.com> wrote:
>> This driver uses usb_phy interface to interact with s3c-hsotg. Supports
>> phy_init and phy_shutdown functions to enable/disable phy. Tested with
>> smdk6410 and smdkv310. More SoCs can be brought under later.
>>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> Acked-by: Heiko Stuebner <heiko at sntech.de>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |    9 +
>>  drivers/usb/phy/Kconfig                            |    8 +
>>  drivers/usb/phy/Makefile                           |    1 +
>>  drivers/usb/phy/samsung-usbphy.c                   |  345 ++++++++++++++++++++
>>  drivers/usb/phy/samsung-usbphy.h                   |   48 +++
>>  include/linux/platform_data/samsung-usbphy.h       |   27 ++
>>  6 files changed, 438 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>>  create mode 100644 drivers/usb/phy/samsung-usbphy.c
>>  create mode 100644 drivers/usb/phy/samsung-usbphy.h
>>  create mode 100644 include/linux/platform_data/samsung-usbphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> new file mode 100644
>> index 0000000..fefd9c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -0,0 +1,9 @@
>> +* Samsung's usb phy transceiver
>> +
>> +The Samsung's phy transceiver is used for controlling usb otg phy for
>> +s3c-hsotg usb device controller.
>> +
>> +Required properties:
>> +- compatible : should be "samsung,exynos4210-usbphy"
>> +- reg : base physical address of the phy registers and length of memory mapped
>> +       region.
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index e7cf84f..d916477 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -15,3 +15,11 @@ config USB_ISP1301
>>
>>           To compile this driver as a module, choose M here: the
>>           module will be called isp1301.
>> +
>> +config SAMSUNG_USBPHY
>> +       bool "Samsung USB PHY controller Driver"
>> +       depends on USB_S3C_HSOTG
>> +       select USB_OTG_UTILS
>> +       help
>> +         Enable this to support Samsung USB phy controller for samsung
>> +         SoCs.
>> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
>> index eca095b..dfca70d 100644
>> --- a/drivers/usb/phy/Makefile
>> +++ b/drivers/usb/phy/Makefile
>> @@ -5,3 +5,4 @@
>>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>>
>>  obj-$(CONFIG_USB_ISP1301)              += isp1301.o
>> +obj-$(CONFIG_SAMSUNG_USBPHY)           += samsung-usbphy.o
>> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
>> new file mode 100644
>> index 0000000..739b6c9
>> --- /dev/null
>> +++ b/drivers/usb/phy/samsung-usbphy.c
>> @@ -0,0 +1,345 @@
>> +/* linux/drivers/usb/phy/samsung-usbphy.c
>> + *
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + *              http://www.samsung.com
>> + *
>> + * Author: Praveen Paneri <p.paneri at samsung.com>
>> + *
>> + * Samsung USB2.0 High-speed OTG transceiver, talks to S3C HS OTG controller
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>
> I suggest you drop that last paragraph unless you want to keep track
> of Free Software Foundation office. Right now it is 51 Franklin
> Street, Boston (http://www.fsf.org/about/contact/) :-)
Yeah! it can be dropped :-)

Praveen
>
> -Kishon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From p.paneri at samsung.com  Fri Aug 10 03:44:18 2012
From: p.paneri at samsung.com (Praveen Paneri)
Date: Fri, 10 Aug 2012 13:14:18 +0530
Subject: [PATCH v3 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
In-Reply-To: <004301cd76c4$f63d4310$e2b7c930$%tikhomirov@samsung.com>
References: <1344411661-17821-1-git-send-email-p.paneri@samsung.com>
 <1344411661-17821-5-git-send-email-p.paneri@samsung.com>
 <004301cd76c4$f63d4310$e2b7c930$%tikhomirov@samsung.com>
Message-ID: <CAD6zSYPcVTjG8x5Dz-eettT96XEd7BK1wm5J0MTbfVgA20afAg@mail.gmail.com>

On Fri, Aug 10, 2012 at 12:24 PM, Anton Tikhomirov
<av.tikhomirov at samsung.com> wrote:
> Hi Praveen,
>
>> -----Original Message-----
>> From: linux-usb-owner at vger.kernel.org [mailto:linux-usb-
>> owner at vger.kernel.org] On Behalf Of Praveen Paneri
>> Sent: Wednesday, August 08, 2012 4:41 PM
>> To: linux-usb at vger.kernel.org
>> Cc: devicetree-discuss at lists.ozlabs.org; linux-arm-
>> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
>> kgene.kim at samsung.com; balbi at ti.com; gregkh at linuxfoundation.org;
>> thomas.abraham at linaro.org; ben-linux at fluff.org;
>> broonie at opensource.wolfsonmicro.com; l.majewski at samsung.com;
>> kyungmin.park at samsung.com; grant.likely at secretlab.ca; heiko at sntech.de
>> Subject: [PATCH v3 4/5] ARM: S3C64XX: Enabling samsung-usbphy driver
>>
>> Adding platform device for samsung-usbphy driver. Enabling it for
>> s3c64xx based machines using s3c-hsotg.
>>
>> Signed-off-by: Praveen Paneri <p.paneri at samsung.com>
>> ---
>>  arch/arm/mach-s3c64xx/include/mach/map.h     |    2 +
>>  arch/arm/mach-s3c64xx/mach-crag6410.c        |    4 +++
>>  arch/arm/mach-s3c64xx/mach-smartq.c          |    5 ++++
>>  arch/arm/mach-s3c64xx/mach-smdk6410.c        |    4 +++
>>  arch/arm/mach-s3c64xx/setup-usb-phy.c        |   14 +++++++++++
>>  arch/arm/plat-samsung/devs.c                 |   33
> ++++++++++++++++++++++++++
>>  arch/arm/plat-samsung/include/plat/devs.h    |    1 +
>>  arch/arm/plat-samsung/include/plat/usb-phy.h |    1 +
>>  8 files changed, 64 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-
>> s3c64xx/include/mach/map.h
>> index 8e2097b..dc482bb 100644
>> --- a/arch/arm/mach-s3c64xx/include/mach/map.h
>> +++ b/arch/arm/mach-s3c64xx/include/mach/map.h
>> @@ -65,6 +65,7 @@
>>
>>  #define S3C64XX_PA_NAND              (0x70200000)
>>  #define S3C64XX_PA_FB                (0x77100000)
>> +#define S3C64XX_PA_USB_HSPHY (0x7C100000)
>>  #define S3C64XX_PA_USB_HSOTG (0x7C000000)
>>  #define S3C64XX_PA_WATCHDOG  (0x7E004000)
>>  #define S3C64XX_PA_RTC               (0x7E005000)
>> @@ -113,6 +114,7 @@
>>  #define S3C_PA_FB            S3C64XX_PA_FB
>>  #define S3C_PA_USBHOST               S3C64XX_PA_USBHOST
>>  #define S3C_PA_USB_HSOTG     S3C64XX_PA_USB_HSOTG
>> +#define S3C_PA_USB_PHY               S3C64XX_PA_USB_HSPHY
>>  #define S3C_PA_RTC           S3C64XX_PA_RTC
>>  #define S3C_PA_WDT           S3C64XX_PA_WATCHDOG
>>  #define S3C_PA_SPI0          S3C64XX_PA_SPI0
>> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-
>> s3c64xx/mach-crag6410.c
>> index b0f5baf..fa02e2f 100644
>> --- a/arch/arm/mach-s3c64xx/mach-crag6410.c
>> +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
>> @@ -31,6 +31,7 @@
>>  #include <linux/spi/spi.h>
>>
>>  #include <linux/i2c/pca953x.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>
>>  #include <video/platform_lcd.h>
>>
>> @@ -336,6 +337,7 @@ static struct platform_device wallvdd_device = {
>>  };
>>
>>  static struct platform_device *crag6410_devices[] __initdata = {
>> +     &samsung_device_usbphy,
>>       &s3c_device_hsmmc0,
>>       &s3c_device_hsmmc2,
>>       &s3c_device_i2c0,
>> @@ -765,6 +767,7 @@ static const struct gpio_led_platform_data
>> gpio_leds_pdata = {
>>       .num_leds = ARRAY_SIZE(gpio_leds),
>>  };
>>
>> +static struct samsung_usbphy_data crag6410_usbphy_pdata;
>
> Why don't you use __initdata for this structure? It will be duplicated
> in s3c_set_platdata() and we don't need it in memory after booting.
> I think you can even initialize it here (with s5p_usb_phy_pmu_isolation).
Thanks! will change it.

Praveen
>
>>
>>  static void __init crag6410_machine_init(void)
>>  {
>> @@ -790,6 +793,7 @@ static void __init crag6410_machine_init(void)
>>       s3c_i2c0_set_platdata(&i2c0_pdata);
>>       s3c_i2c1_set_platdata(&i2c1_pdata);
>>       s3c_fb_set_platdata(&crag6410_lcd_pdata);
>> +     samsung_usbphy_set_pdata(&crag6410_usbphy_pdata);
>>
>>       i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
>>       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
>> diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-
>> s3c64xx/mach-smartq.c
>> index 7400da1..e0c4df8 100644
>> --- a/arch/arm/mach-s3c64xx/mach-smartq.c
>> +++ b/arch/arm/mach-s3c64xx/mach-smartq.c
>> @@ -18,6 +18,7 @@
>>  #include <linux/serial_core.h>
>>  #include <linux/spi/spi_gpio.h>
>>  #include <linux/usb/gpio_vbus.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>
>>  #include <asm/mach-types.h>
>>  #include <asm/mach/map.h>
>> @@ -234,6 +235,7 @@ static struct i2c_board_info smartq_i2c_devs[]
>> __initdata = {
>>  };
>>
>>  static struct platform_device *smartq_devices[] __initdata = {
>> +     &samsung_device_usbphy,
>>       &s3c_device_hsmmc1,     /* Init iNAND first, ... */
>>       &s3c_device_hsmmc0,     /* ... then the external SD card */
>>       &s3c_device_hsmmc2,
>> @@ -380,9 +382,12 @@ void __init smartq_map_io(void)
>>       smartq_lcd_mode_set();
>>  }
>>
>> +static struct samsung_usbphy_data smartq_usbphy_pdata;
>
> Same here
>
>> +
>>  void __init smartq_machine_init(void)
>>  {
>>       s3c_i2c0_set_platdata(NULL);
>> +     samsung_usbphy_set_pdata(&smartq_usbphy_pdata);
>>       s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
>>       s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
>>       s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
>> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-
>> s3c64xx/mach-smdk6410.c
>> index cbdc91b..8d40511 100644
>> --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
>> +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
>> @@ -30,6 +30,7 @@
>>  #include <linux/regulator/fixed.h>
>>  #include <linux/regulator/machine.h>
>>  #include <linux/pwm_backlight.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>
>>  #ifdef CONFIG_SMDK6410_WM1190_EV1
>>  #include <linux/mfd/wm8350/core.h>
>> @@ -263,6 +264,7 @@ static struct samsung_keypad_platdata
>> smdk6410_keypad_data __initdata = {
>>  static struct map_desc smdk6410_iodesc[] = {};
>>
>>  static struct platform_device *smdk6410_devices[] __initdata = {
>> +     &samsung_device_usbphy,
>>  #ifdef CONFIG_SMDK6410_SD_CH0
>>       &s3c_device_hsmmc0,
>>  #endif
>> @@ -626,6 +628,7 @@ static struct platform_pwm_backlight_data
>> smdk6410_bl_data = {
>>       .pwm_id = 1,
>>  };
>>
>> +static struct samsung_usbphy_data smdk6410_usbphy_pdata;
>
> Same here
>
>>
>>  static void __init smdk6410_map_io(void)
>>  {
>> @@ -655,6 +658,7 @@ static void __init smdk6410_machine_init(void)
>>       s3c_i2c0_set_platdata(NULL);
>>       s3c_i2c1_set_platdata(NULL);
>>       s3c_fb_set_platdata(&smdk6410_lcd_pdata);
>> +     samsung_usbphy_set_pdata(&smdk6410_usbphy_pdata);
>>
>>       samsung_keypad_set_platdata(&smdk6410_keypad_data);
>>
>> diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-
>> s3c64xx/setup-usb-phy.c
>> index 7a09553..3aee778 100644
>> --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
>> +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
>> @@ -9,3 +9,17 @@
>>   *
>>   */
>>
>> +#include <linux/io.h>
>> +#include <mach/map.h>
>> +#include <mach/regs-sys.h>
>> +
>> +void s5p_usb_phy_pmu_isolation(int on)
>> +{
>> +     if (on) {
>> +             writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
>> +                     S3C64XX_OTHERS);
>> +     } else {
>> +             writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK,
>> +                     S3C64XX_OTHERS);
>> +     }
>> +}
>> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
>> index 74e31ce..a094143 100644
>> --- a/arch/arm/plat-samsung/devs.c
>> +++ b/arch/arm/plat-samsung/devs.c
>> @@ -31,6 +31,7 @@
>>  #include <linux/ioport.h>
>>  #include <linux/platform_data/s3c-hsudc.h>
>>  #include <linux/platform_data/s3c-hsotg.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>
>>  #include <asm/irq.h>
>>  #include <asm/pmu.h>
>> @@ -1343,6 +1344,35 @@ struct platform_device s5p_device_mixer = {
>>
>>  /* USB */
>>
>> +#ifdef CONFIG_S3C_DEV_USB_HSOTG
>> +/* USB PHY*/
>> +static struct resource samsung_usbphy_resource[] = {
>> +     [0] = {
>> +             .start = S3C_PA_USB_PHY,
>> +             .end   = S3C_PA_USB_PHY + SZ_16 - 1,
>> +             .flags = IORESOURCE_MEM,
>> +     },
>> +};
>> +
>> +struct platform_device samsung_device_usbphy = {
>> +     .name           = "s3c64xx-usbphy",
>> +     .id             = -1,
>> +     .num_resources  = ARRAY_SIZE(samsung_usbphy_resource),
>> +     .resource       = samsung_usbphy_resource,
>> +};
>> +
>> +void __init samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd)
>> +{
>> +     struct samsung_usbphy_data *npd;
>> +
>> +     npd = s3c_set_platdata(pd, sizeof(struct samsung_usbphy_data),
>> +                     &samsung_device_usbphy);
>> +
>> +     if (!npd->pmu_isolation)
>> +             npd->pmu_isolation = s5p_usb_phy_pmu_isolation;
>> +}
>> +#endif
>> +
>>  #ifdef CONFIG_S3C_DEV_USB_HOST
>>  static struct resource s3c_usb_resource[] = {
>>       [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
>> @@ -1449,6 +1479,8 @@ struct platform_device s3c_device_usb_hsotg = {
>>       },
>>  };
>>
>> +#ifndef CONFIG_ARCH_S3C64XX
>> +/* TODO: To be removed later. Currently only S3C64XX is platform data
>> free */
>>  void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
>>  {
>>       struct s3c_hsotg_plat *npd;
>> @@ -1461,6 +1493,7 @@ void __init s3c_hsotg_set_platdata(struct
>> s3c_hsotg_plat *pd)
>>       if (!npd->phy_exit)
>>               npd->phy_exit = s5p_usb_phy_exit;
>>  }
>> +#endif
>>  #endif /* CONFIG_S3C_DEV_USB_HSOTG */
>>
>>  /* USB High Spped 2.0 Device (Gadget) */
>> diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-
>> samsung/include/plat/devs.h
>> index 5da4b4f..3849c88 100644
>> --- a/arch/arm/plat-samsung/include/plat/devs.h
>> +++ b/arch/arm/plat-samsung/include/plat/devs.h
>> @@ -138,6 +138,7 @@ extern struct platform_device exynos_device_drm;
>>  extern struct platform_device samsung_asoc_dma;
>>  extern struct platform_device samsung_asoc_idma;
>>  extern struct platform_device samsung_device_keypad;
>> +extern struct platform_device samsung_device_usbphy;
>>
>>  /* s3c2440 specific devices */
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-
>> samsung/include/plat/usb-phy.h
>> index 959bcdb..165ffe7 100644
>> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
>> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
>> @@ -18,5 +18,6 @@ enum s5p_usb_phy_type {
>>
>>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
>> +extern void s5p_usb_phy_pmu_isolation(int on);
>>
>>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
>> --
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From balbi at ti.com  Fri Aug 10 03:40:55 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 10 Aug 2012 10:40:55 +0300
Subject: [PATCH v4 0/5] usb: phy: samsung: Introducing usb phy driver for
 samsung SoCs
In-Reply-To: <CAD6zSYPT_K9bTP=8k-Q+5N-yAVjDx86Haay27OLuPsqz38pczA@mail.gmail.com>
References: <1344582631-13658-1-git-send-email-p.paneri@samsung.com>
 <20120810070623.GL1689@arwen.pp.htv.fi>
 <CAD6zSYPT_K9bTP=8k-Q+5N-yAVjDx86Haay27OLuPsqz38pczA@mail.gmail.com>
Message-ID: <20120810074055.GD5755@arwen.pp.htv.fi>

On Fri, Aug 10, 2012 at 01:04:48PM +0530, Praveen Paneri wrote:
> On Fri, Aug 10, 2012 at 12:36 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Fri, Aug 10, 2012 at 12:40:26PM +0530, Praveen Paneri wrote:
> >> Changes from v3:
> >> Replaced susbsys_initcall()/module_exit() by module_platform_driver().
> >> Accordingly in the hsotg driver returned -EPROBE_DEFER until phy driver
> >> is registered
> >> Removed unnecessary devm_usb_put_phy() call from the hsotg driver remove.
> >>
> >> Changes from v2:
> >> Changed the driver filenames to samsung-usbphy
> >> Changed 's3c' to 'samsung' for platform device as well as platform data
> >> Moved platform data structure to a separate file
> >> Rectified coding style related errors
> >>
> >> Changes from v1:
> >> Rebased patches to latest usb-next branch
> >> Changed the name 'sec_usbphy' to 'samsung_usbphy'
> >>
> >> This patch set introduces a phy driver for samsung SoCs. It uses the existing
> >> transceiver infrastructure to provide phy control functions. Use of this driver
> >> can be extended for usb host phy as well. Over the period of time all the phy
> >> related code for most of the samsung SoCs can be integrated here.
> >> Removing the existing phy code from mach-s3c64xx. Same can be done for other SoCs
> >> when they start supporting this phy driver.
> >> This driver is tested with smdk6410 and Exynos4210(with DT).
> >>
> >> Praveen Paneri (5):
> >>   usb: phy: samsung: Introducing usb phy driver for hsotg
> >>   usb: s3c-hsotg: Adding phy driver support
> >>   ARM: S3C64XX: Removing old phy setup code
> >>   ARM: S3C64XX: Enabling samsung-usbphy driver
> >>   ARM: Exynos4210: Enabling samsung-usbphy driver
> >
> > just one idea. It looks like after introducing the PHY, you converted
> > all users to create the phy device. I wonder if you should have a
> Not all
> > patch 6/6 which will remove pdata->init support from s3c_hsotg.c and
> > stick to using phy driver.
> This will make the hsotg driver unusable for others (in mach-s5pv210
> and mach-exynos) which are not supported in the phy driver as of now.
> My idea was to drop the pdata->init when the last user gets the phy
> support. Need some time for that :-)

makes sense. wasn't aware there were more users. no problem then ;-)

-- 
balbi
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From nicolas.ferre at atmel.com  Fri Aug 10 03:46:22 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 10 Aug 2012 09:46:22 +0200
Subject: [GIT PULL] at91: platform data for atmel-mci (for 3.5)
In-Reply-To: <201207252006.44523.arnd@arndb.de>
References: <4FBE4FE7.3010005@atmel.com> <4FC722B7.10409@atmel.com>
 <201207252006.44523.arnd@arndb.de>
Message-ID: <5024BC4E.9010709@atmel.com>

On 07/25/2012 10:06 PM, Arnd Bergmann :
> On Thursday 31 May 2012, Nicolas Ferre wrote:
>>
>> On 05/24/2012 05:12 PM, Nicolas Ferre :
>>> Hi Arnd, hi Olof,
>>
>> Ping?
>>
>> (or maybe you will have a look at this after the merge window...)
>>
> 
> I've just gone through all old pull requests that I had somewhere in
> my inbox and this turned out to be one that we never pulled.
> 
> It looks like it still applies and we should send it to Linus as as
> late branch this time, given that we screwed up and it was there
> all the time.
> 
> Nicolas, can you please confirm?

Arnd,

I have sent to you a pull-request covering this work several days ago
([GIT PULL] at91: soc update (for 3.6)): what is your feeling about it:
do you think that it will still go upstream for 3.6?

Thanks, bye,
-- 
Nicolas Ferre


From linus.walleij at stericsson.com  Fri Aug 10 04:43:54 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 10 Aug 2012 10:43:54 +0200
Subject: [PATCH 1/4] ARM: ux500: delete remnant U5500 macros
Message-ID: <1344588234-8597-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The code using these ASIC detection functions is now gone so
we remove it.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/include/mach/id.h | 29 -----------------------------
 1 file changed, 29 deletions(-)

diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c6e2db9..87aa921 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -51,35 +51,6 @@ static inline bool cpu_is_u8500_family(void)
 	return cpu_is_u8500() || cpu_is_u9540();
 }
 
-static inline bool __attribute_const__ cpu_is_u5500(void)
-{
-	return dbx500_partnumber() == 0x5500;
-}
-
-/*
- * 5500 revisions
- */
-
-static inline bool __attribute_const__ cpu_is_u5500v1(void)
-{
-	return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v2(void)
-{
-	return (dbx500_id.revision & 0xf0) == 0xB0;
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v20(void)
-{
-	return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v21(void)
-{
-	return cpu_is_u5500() && (dbx500_revision() == 0xB1);
-}
-
 /*
  * 8500 revisions
  */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri Aug 10 04:44:08 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 10 Aug 2012 10:44:08 +0200
Subject: [PATCH 3/4] ARM: ux500: reform Ux500 family names
Message-ID: <1344588248-8670-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Counting the U9540 and the new U8540 as a U8500 family member
does not work. Instead, split the function in two:

cpu_is_u8500_family() covering U8500 and U8520
cpu_is_ux540_family() covering U9540 and U8540

This works much better in practice. Update users to keep the
same behaviour.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/cache-l2x0.c      |  2 +-
 arch/arm/mach-ux500/cpu-db8500.c      |  2 +-
 arch/arm/mach-ux500/cpu.c             |  2 +-
 arch/arm/mach-ux500/include/mach/id.h | 21 +++++++++++++--------
 arch/arm/mach-ux500/platsmp.c         |  2 +-
 5 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index dc12394..75d5b51 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,7 +38,7 @@ static int __init ux500_l2x0_init(void)
 {
 	u32 aux_val = 0x3e000000;
 
-	if (cpu_is_u8500_family())
+	if (cpu_is_u8500_family() || cpu_is_ux540_family())
 		l2x0_base = __io_address(U8500_L2CC_BASE);
 	else
 		ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d..2dd8593 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -80,7 +80,7 @@ void __init u8500_map_io(void)
 
 	iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
 
-	if (cpu_is_u9540())
+	if (cpu_is_ux540_family())
 		iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
 	else
 		iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7..4b0a9b3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -51,7 +51,7 @@ void __init ux500_init_irq(void)
 	void __iomem *dist_base;
 	void __iomem *cpu_base;
 
-	if (cpu_is_u8500_family()) {
+	if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
 		dist_base = __io_address(U8500_GIC_DIST_BASE);
 		cpu_base = __io_address(U8500_GIC_CPU_BASE);
 	} else
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index d1240e4..c7fcf69 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -46,14 +46,24 @@ static inline bool __attribute_const__ cpu_is_u8520(void)
 	return dbx500_partnumber() == 0x8520;
 }
 
+static inline bool cpu_is_u8500_family(void)
+{
+	return cpu_is_u8500() || cpu_is_u8520();
+}
+
 static inline bool __attribute_const__ cpu_is_u9540(void)
 {
 	return dbx500_partnumber() == 0x9540;
 }
 
-static inline bool cpu_is_u8500_family(void)
+static inline bool __attribute_const__ cpu_is_u8540(void)
+{
+	return dbx500_partnumber() == 0x8540;
+}
+
+static inline bool cpu_is_ux540_family(void)
 {
-	return cpu_is_u8500() || cpu_is_u9540();
+	return cpu_is_u9540() || cpu_is_u8540();
 }
 
 /*
@@ -97,12 +107,7 @@ static inline bool cpu_is_u8500v21(void)
 
 static inline bool cpu_is_u8500v20_or_later(void)
 {
-	/*
-	 * U9540 has so much in common with U8500 that is is considered a
-	 * U8500 variant.
-	 */
-	return cpu_is_u9540() ||
-		(cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
+	return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
 
 static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad..cb35897 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,7 +48,7 @@ static void write_pen_release(int val)
 
 static void __iomem *scu_base_addr(void)
 {
-	if (cpu_is_u8500_family())
+	if (cpu_is_u8500_family() || cpu_is_ux540_family())
 		return __io_address(U8500_SCU_BASE);
 	else
 		ux500_unknown_soc();
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri Aug 10 04:44:14 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 10 Aug 2012 10:44:14 +0200
Subject: [PATCH 4/4] ARM: ux500: add detection for DB8500 ASIC v2.2
Message-ID: <1344588254-8706-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Add a macro to properly detect the v2.2 version of the
DB8500 ASIC.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/include/mach/id.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c7fcf69..9c42642 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -105,6 +105,11 @@ static inline bool cpu_is_u8500v21(void)
 	return cpu_is_u8500() && (dbx500_revision() == 0xB1);
 }
 
+static inline bool cpu_is_u8500v22(void)
+{
+	return cpu_is_u8500() && (dbx500_revision() == 0xB2);
+}
+
 static inline bool cpu_is_u8500v20_or_later(void)
 {
 	return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
-- 
1.7.11.3



From linus.walleij at stericsson.com  Fri Aug 10 04:44:01 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 10 Aug 2012 10:44:01 +0200
Subject: [PATCH 2/4] ARM: ux500: add a U8520 detection macro
Message-ID: <1344588241-8633-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

In line with the other macros this detects the DB8520
ASIC variant.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/include/mach/id.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index 87aa921..d1240e4 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,6 +41,11 @@ static inline bool __attribute_const__ cpu_is_u8500(void)
 	return dbx500_partnumber() == 0x8500;
 }
 
+static inline bool __attribute_const__ cpu_is_u8520(void)
+{
+	return dbx500_partnumber() == 0x8520;
+}
+
 static inline bool __attribute_const__ cpu_is_u9540(void)
 {
 	return dbx500_partnumber() == 0x9540;
-- 
1.7.11.3



From linus.walleij at linaro.org  Fri Aug 10 04:48:39 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 10:48:39 +0200
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
In-Reply-To: <20120809194044.GA9966@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <20120809185029.GC24328@opensource.wolfsonmicro.com>
 <20120809194044.GA9966@gmail.com>
Message-ID: <CACRpkdZCKQCkWSPYby2rYd4Oas481nZE7eDmZRETovJOks2p0Q@mail.gmail.com>

On Thu, Aug 9, 2012 at 9:40 PM, Lee Jones <lee.jones at linaro.org> wrote:
> On Thu, Aug 09, 2012 at 07:50:29PM +0100, Mark Brown wrote:
>> On Thu, Aug 09, 2012 at 04:47:26PM +0100, Lee Jones wrote:
>> > Another fine instalment of Audio fixes and Device Tree enablement
>> > surrounding the mop500 sound driver. Hopefully containing all of
>> > the recommendations suggested by Mark Brown.
>>
>> Can we have some review of this from the ARM side please?  It's pretty
>> big...
>
> I don't expect Linus will do anything until he returns back from vacation.

I'm back from vacation, and catching up. Now there is a few different
DT patch bombs from you in my inbox, which patchset shall I review
first? This one? Or is there a more urgent one?

Yours,
Linus Walleij


From tony at atomide.com  Fri Aug 10 04:50:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 10 Aug 2012 01:50:22 -0700
Subject: [linux-pm] [PATCH v4 2/4] mfd: omap: control: core system
 control driver
In-Reply-To: <5023985F.3090606@dev.rtsoft.ru>
References: <500FD2EC.7060208@dev.rtsoft.ru>
 <20120808140507.GF11011@atomide.com>
 <20120808141051.GG11011@atomide.com>
 <20120808143929.GJ11011@atomide.com>
 <50227ED9.3010508@dev.rtsoft.ru> <5023985F.3090606@dev.rtsoft.ru>
Message-ID: <20120810085022.GS11011@atomide.com>

* Konstantin Baydarov <kbaidarov at dev.rtsoft.ru> [120809 04:00]:
>   Hi, Tony.
> 
> On 08/08/2012 06:59 PM, Konstantin Baydarov wrote:
> >   Yes, omap_type() is called very early , that is why I'm using early_initcall for omap_control_base initialization.
> >
> > Do you mean following?:
> > void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
> > {
> >     if (omap2_globals->ctrl)
> >         omap2_ctrl_base = omap2_globals->ctrl;
> >
> >     if (omap2_globals->ctrl_pad)
> >         omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
> >
> >     omap_control_base = omap2_ctrl_base;  // this line is added
> > }
>   Sorry for the confusion - the code above isn't correct. First, as omap-control-core.c driver maps only control module status register the omap_control_base should be renamed to omap_control_status_reg:

Heh right :) And that makes the patch I posted wrong too.
 
> @@ -156,6 +158,20 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
>  
>  	if (omap2_globals->ctrl_pad)
>  		omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
> +
> +	omap_control_status_reg = omap2_ctrl_base;
> +	if (cpu_is_omap24xx())
> +		omap_control_status_reg += OMAP24XX_CONTROL_STATUS;
> +	else if (soc_is_am33xx())
> +		omap_control_status_reg += AM33XX_CONTROL_STATUS;
> +	else if (cpu_is_omap34xx())
> +		omap_control_status_reg += OMAP343X_CONTROL_STATUS;
> +	else if (cpu_is_omap44xx())
> +		omap_control_status_reg += OMAP4_CTRL_MODULE_CORE_STATUS;
> +	else if (soc_is_omap54xx())
> +		omap_control_status_reg += OMAP5XXX_CONTROL_STATUS;
> +	else
> +		omap_control_status_reg = 0;
>  }

We can get rid of the if else SoC check here too. And we can limit the
control_status tinkering to id.c. Here's an updated clean-up patch.

Regards,

Tony
 

From: Tony Lindgren <tony at atomide.com>
Date: Wed, 8 Aug 2012 23:13:03 -0700
Subject: [PATCH] ARM: OMAP2+: Initialize things for omap_type() to simplify
 SoC detection

Let's rename omap2_set_globals_tap() to omap2_set_globals_id() and update
the comments to remove old comments about map_io() as we don't need SoC
detection for map_io() any longer.

Let's also initialize control_status_reg with omap2_set_globals_id()
so we can avoid SoC tests every time omap_type() gets called.

Note that this patch sets the ti81xx to always return GP mode as
the mode bits seem to be marked as reserved in ti81xx TRM.

Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 069f972..64afeee 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -31,7 +31,7 @@
 
 static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 {
-	omap2_set_globals_tap(omap2_globals);
+	omap2_set_globals_id(omap2_globals);
 	omap2_set_globals_sdrc(omap2_globals);
 	omap2_set_globals_control(omap2_globals);
 	omap2_set_globals_prcm(omap2_globals);
@@ -45,6 +45,8 @@ static struct omap_globals omap242x_globals = {
 	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 	.sms	= OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
 	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
+	.ctrl_status	= OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE) +
+				OMAP24XX_CONTROL_STATUS,
 	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
 	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
 };
@@ -68,6 +70,8 @@ static struct omap_globals omap243x_globals = {
 	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 	.sms	= OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
 	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
+	.ctrl_status	= OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE) +
+				OMAP24XX_CONTROL_STATUS,
 	.prm	= OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
 	.cm	= OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
 };
@@ -91,6 +95,8 @@ static struct omap_globals omap3_globals = {
 	.sdrc	= OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 	.sms	= OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
 	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
+	.ctrl_status	= OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE) +
+				OMAP343X_CONTROL_STATUS,
 	.prm	= OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
 	.cm	= OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 };
@@ -117,6 +123,8 @@ static struct omap_globals ti81xx_globals = {
 	.class  = OMAP343X_CLASS,
 	.tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
 	.ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+	.ctrl_status   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE) +
+				TI81XX_CONTROL_STATUS,
 	.prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 	.cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 };
@@ -140,6 +148,8 @@ static struct omap_globals am33xx_globals = {
 	.class  = AM335X_CLASS,
 	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
 	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+	.ctrl_status = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE) +
+			AM33XX_CONTROL_STATUS,
 	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
 	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
 };
@@ -160,6 +170,8 @@ static struct omap_globals omap4_globals = {
 	.class	= OMAP443X_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
 	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+	.ctrl_status	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE) +
+				OMAP4_CTRL_MODULE_CORE_STATUS,
 	.ctrl_pad	= OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
 	.prm	= OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
 	.cm	= OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
@@ -183,6 +195,8 @@ static struct omap_globals omap5_globals = {
 	.class	= OMAP54XX_CLASS,
 	.tap	= OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
 	.ctrl	= OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+	.ctrl_status	= OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE) +
+				OMAP5XXX_CONTROL_STATUS,
 	.ctrl_pad	= OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
 	.prm	= OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
 	.cm	= OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
@@ -192,7 +206,7 @@ static struct omap_globals omap5_globals = {
 
 void __init omap2_set_globals_5xxx(void)
 {
-	omap2_set_globals_tap(&omap5_globals);
+	omap2_set_globals_id(&omap5_globals);
 	omap2_set_globals_control(&omap5_globals);
 	omap2_set_globals_prcm(&omap5_globals);
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 1f65b18..a3cee8c 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -168,6 +168,7 @@ struct omap_globals {
 	void __iomem	*sdrc;           /* SDRAM Controller */
 	void __iomem	*sms;            /* SDRAM Memory Scheduler */
 	void __iomem	*ctrl;           /* System Control Module */
+	void __iomem	*ctrl_status;	/* Control status register */
 	void __iomem	*ctrl_pad;	/* PAD Control Module */
 	void __iomem	*prm;            /* Power and Reset Management */
 	void __iomem	*cm;             /* Clock Management */
@@ -184,7 +185,7 @@ void omap2_set_globals_ti81xx(void);
 void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
-void omap2_set_globals_tap(struct omap_globals *);
+void omap2_set_globals_id(struct omap_globals *);
 #if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
 void omap2_set_globals_sdrc(struct omap_globals *);
 #else
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8cdc85..cf92e06 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -59,6 +59,7 @@
 
 /* TI81XX spefic control submodules */
 #define TI81XX_CONTROL_DEVCONF		0x600
+#define TI81XX_CONTROL_STATUS		0x040
 
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 40373db..19cc66d 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -29,6 +29,7 @@
 #include "control.h"
 
 static unsigned int omap_revision;
+static unsigned int control_status;
 static const char *cpu_rev;
 u32 omap_features;
 
@@ -40,31 +41,13 @@ EXPORT_SYMBOL(omap_rev);
 
 int omap_type(void)
 {
-	u32 val = 0;
-
-	if (cpu_is_omap24xx()) {
-		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-	} else if (soc_is_am33xx()) {
-		val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
-	} else if (cpu_is_omap34xx()) {
-		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
-	} else if (cpu_is_omap44xx()) {
-		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
-	} else if (soc_is_omap54xx()) {
-		val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
-		val &= OMAP5_DEVICETYPE_MASK;
-		val >>= 6;
-		goto out;
-	} else {
-		pr_err("Cannot detect omap type!\n");
-		goto out;
+	if (!control_status) {
+		pr_err("Uninitialized control_status!\n");
+		WARN_ON(1);
+		return 0;
 	}
 
-	val &= OMAP2_DEVICETYPE_MASK;
-	val >>= 8;
-
-out:
-	return val;
+	return control_status;
 }
 EXPORT_SYMBOL(omap_type);
 
@@ -554,13 +537,9 @@ void __init omap5xxx_check_revision(void)
 }
 
 /*
- * Set up things for map_io and processor detection later on. Gets called
- * pretty much first thing from board init. For multi-omap, this gets
- * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
- * detect the exact revision later on in omap2_detect_revision() once map_io
- * is done.
+ * Initialize things for SoC detecttion. Gets called from init_early.
  */
-void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+void __init omap2_set_globals_id(struct omap_globals *omap2_globals)
 {
 	omap_revision = omap2_globals->class;
 	tap_base = omap2_globals->tap;
@@ -569,4 +548,16 @@ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 		tap_prod_id = 0x0210;
 	else
 		tap_prod_id = 0x0208;
+
+	control_status = __raw_readl(omap2_globals->ctrl_status);
+	if (cpu_is_ti81xx()) {
+		/* At least ti81xx TRM sprugx8.pdf lists type bits as reserved */
+		control_status = OMAP2_DEVICE_TYPE_GP;
+	} else if (soc_is_omap54xx()) {
+		control_status &= OMAP5_DEVICETYPE_MASK;
+		control_status >>= 6;
+	} else {
+		control_status &= OMAP2_DEVICETYPE_MASK;
+		control_status >>= 8;
+	}
 }


From s.hauer at pengutronix.de  Fri Aug 10 05:04:28 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 10 Aug 2012 11:04:28 +0200
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Add Chipidea USB driver support
In-Reply-To: <1344463589-8115-1-git-send-email-festevam@gmail.com>
References: <1344463589-8115-1-git-send-email-festevam@gmail.com>
Message-ID: <20120810090428.GW1451@pengutronix.de>

On Wed, Aug 08, 2012 at 07:06:29PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Add Chipidea USB driver support.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks (to the defconfig branch btw)

Sascha

> ---
>  arch/arm/configs/imx_v6_v7_defconfig |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..5f6138d 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -179,6 +179,9 @@ CONFIG_SND_SOC_IMX_MC13783=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_EHCI_MXC=y
> +CONFIG_USB_CHIPIDEA=y
> +CONFIG_USB_CHIPIDEA_HOST=y
> +CONFIG_USB_MXS_PHY=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_MMC=y
>  CONFIG_MMC_SDHCI=y
> -- 
> 1.7.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Aug 10 05:05:22 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 10 Aug 2012 11:05:22 +0200
Subject: [PATCH] ARM: imx_v6_v7_defconfig: Remove
 CONFIG_DEFAULT_MMAP_MIN_ADDR
In-Reply-To: <1344017554-4120-1-git-send-email-fabio.estevam@freescale.com>
References: <1344017554-4120-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120810090522.GX1451@pengutronix.de>

On Fri, Aug 03, 2012 at 03:12:34PM -0300, Fabio Estevam wrote:
> By default CONFIG_DEFAULT_MMAP_MIN_ADDR is 4096 and can also be changed via
> /proc/sys/vm/mmap_min_addr if needed.
> 
> Quoting Russell King (http://marc.info/?l=linux-arm-kernel&m=134401593807820&w=2):
> 
> "4096 is also fine for ARM too.  There's not much point in having
> defconfigs change it - that would just be pure noise in the config
> files."
> 
> ,so remove CONFIG_DEFAULT_MMAP_MIN_ADDR from the defconfig file.
>  
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks

Sascha

> ---
>  arch/arm/configs/imx_v6_v7_defconfig |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..13bcfb1 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -42,7 +42,6 @@ CONFIG_VMSPLIT_2G=y
>  CONFIG_PREEMPT_VOLUNTARY=y
>  CONFIG_AEABI=y
>  # CONFIG_OABI_COMPAT is not set
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
>  CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
>  CONFIG_VFP=y
>  CONFIG_NEON=y
> -- 
> 1.7.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From wni at nvidia.com  Fri Aug 10 05:11:56 2012
From: wni at nvidia.com (Wei Ni)
Date: Fri, 10 Aug 2012 17:11:56 +0800
Subject: How to get the irq flags from the dts file
In-Reply-To: <20120809120530.GC8474@sirena.org.uk>
References: <1344509006.2295.148.camel@tegra-chromium-2>
 <201208091148.42748.arnd@arndb.de>  <20120809120530.GC8474@sirena.org.uk>
Message-ID: <1344589916.21467.1.camel@tegra-chromium-2>

On Thu, 2012-08-09 at 20:05 +0800, Mark Brown wrote:
> On Thu, Aug 09, 2012 at 11:48:42AM +0000, Arnd Bergmann wrote:
> > On Thursday 09 August 2012, Wei Ni wrote:
> 
> > > The wlan driver wish this flags include the IRQF_TRGGER_* information,
> > > and it will use this flags to configure other hw settings. If it is
> > > wrong, the wlan can't work.
> 
> You can read the configuration with irqd_get_trigger_type() - see the OF
> code in sound/soc/codecs/wm8903.c for an example.

I tried it, it worked fine. thanks for your help.

> 
> > The driver should not need to know about thie flag. It gets read
> > by irq_create_of_mapping when calling teh xlate function and
> > gets set using irq_set_irq_type from there too.
> 
> That only helps the interrupt controller, it doesn't help the interrupt
> source.  A good proportion of embedded devices have a great deal of
> flexibility in how they signal interrupts so they need to know what mode
> to pick.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html




From wni at nvidia.com  Fri Aug 10 05:14:58 2012
From: wni at nvidia.com (Wei Ni)
Date: Fri, 10 Aug 2012 17:14:58 +0800
Subject: How to get the irq flags from the dts file
In-Reply-To: <5023A88F.8040402@broadcom.com>
References: <1344509006.2295.148.camel@tegra-chromium-2>
 <5023A88F.8040402@broadcom.com>
Message-ID: <1344590098.21467.4.camel@tegra-chromium-2>

On Thu, 2012-08-09 at 20:09 +0800, Arend van Spriel wrote:
> On 08/09/2012 12:43 PM, Wei Ni wrote:
> > Hi, all
> > I'm working on tegra wlan upstream issue.
> > The tegra board use the Broadcom 4329 as wlan device, and the driver is
> > the brcmfmac. 
> > 
> > This wlan driver support out-band-interrupt (OOB), I want to add DT
> > support to use this OOB.
> > I can add following lines in the dts file to create platform device and
> > pass the interrupt resource to the driver.
> > 
> > wlan {
> >         compatible = "broadcome, brcmf_sdio_pd";
> 
> I don't know the DT syntax, but I assume broadcome should be broadcom,
> right? ;-)

Sorry, it's my typo, it should be broadcom.

> 
> >         interrupt-parten = <&gpio>;
> >         interrupts = <144, 0x04>; /* IRQF_TRIGGER_HIGH */
> > };
> > 
> > In the wlan driver, it will use platform_get_resource() to get the
> > res->irq, res->flags, the irq number is right, but the flags will be
> > IORESOURCE_IRQ, not the 0x04 (IRQF_TRIGGER_HIGH).
> > The wlan driver wish this flags include the IRQF_TRGGER_* information,
> > and it will use this flags to configure other hw settings. If it is
> > wrong, the wlan can't work.
> > 
> > I checked drivers/of/irq.c, in function of_irq_to_resource(), it will
> > set r->flags = IORESOURCE_IRQ directly, not read the flags from the dtb
> > file. And I didn't find any of_xx api to get this flags.
> > 
> > How can I get this flags, does anyone has suggestion?
> 
> I did a quick search in the kernel and there are a number of platform
> drivers that seem to expect the IRQF_TRIGGER_* info by using (res->flags
> & IRQF_TRIGGER_MASK) and to determine IRQF_SHARED as well.
> 
> Gr. AvS
> 




From u.kleine-koenig at pengutronix.de  Fri Aug 10 05:32:49 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 10 Aug 2012 11:32:49 +0200
Subject: [PATCH v2 1/2] ARM: i.MX35: Add kernel oftree support
Message-ID: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>

From: Steffen Trumtrar <s.trumtrar at pengutronix.de>

This patch adds basic support for imx35-based devices to the kernel.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
--
Changes since implict v1
(id:1343922986-32469-1-git-send-email-u.kleine-koenig at pengutronix.de)

 - add aliases for gpio devices
 - drop calling irq_domain_add_legacy
 - drop soc/cpus from device tree
 - rename uart entries to serial
 - drop "status = "disabled"" from watchdog node
 - drop fallback compatibility entries for fsl,mx35-sdhc
 - put nand below a new emi node
 - fix register range for aips1
 - add ssi1
 - gpio controllers have two interrupt cells
 - register additional clklookups instead of using auxdata lookup

 arch/arm/boot/dts/imx35.dtsi            |  253 +++++++++++++++++++++++++++++++
 arch/arm/configs/imx_v6_v7_defconfig    |    1 +
 arch/arm/mach-imx/Kconfig               |   12 ++
 arch/arm/mach-imx/Makefile              |    1 +
 arch/arm/mach-imx/clk-imx35.c           |   14 ++
 arch/arm/mach-imx/imx35-dt.c            |   56 +++++++
 arch/arm/plat-mxc/include/mach/common.h |    1 +
 7 files changed, 338 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx35.dtsi
 create mode 100644 arch/arm/mach-imx/imx35-dt.c

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
new file mode 100644
index 0000000..05f906f
--- /dev/null
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27.dtsi
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+	};
+
+	avic: avic-interrupt-controller at 68000000 {
+		compatible = "fsl,imx35-avic", "fsl,avic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x68000000 0x10000000>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ckil {
+			compatible = "fsl,imx-ckil", "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		osc {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&avic>;
+		ranges;
+
+		aips at 40000000 { /* AIPS1 */
+			compatible = "fsl,aips", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x43f00000 0x100000>;
+			ranges;
+
+			i2c1: i2c at 43f80000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f80000 0x4000>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 43f84000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f84000 0x4000>;
+				interrupts = <3>;
+				status = "disabled";
+			};
+
+			uart1: serial at 43f90000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x43f90000 0x4000>;
+				interrupts = <45>;
+				status = "disabled";
+			};
+
+			uart2: serial at 43f94000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x43f94000 0x4000>;
+				interrupts = <32>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 43f98000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+				reg = <0x43f98000 0x4000>;
+				interrupts = <4>;
+				status = "disabled";
+			};
+
+			ssi1: ssi at 43fa0000 {
+				compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
+				reg = <0x43fa0000 0x4000>;
+				interrupts = <11>;
+				fsl,ssi-dma-events = <29 28 27 26>;
+				status = "disabled";
+			};
+			iomuxc at 43fac000 {
+				compatible = "fsl,imx35-iomuxc";
+				reg = <0x43fac000 0x4000>;
+
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <773 0x1c0 /* MX35_PAD_ATA_DATA12__I2C3_SCL */
+							777 0x1c0>; /* MX35_PAD_ATA_DATA13__I2C3_SDA */
+					};
+				};
+
+				can1 {
+					pinctrl_can1_1: can1grp-1 {
+						fsl,pins = <223 0x1c0 /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
+							228 0x1c0>; /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
+					};
+				};
+
+				can2 {
+					pinctrl_can2_1: can2grp-1 {
+						fsl,pins = <291 0x1c0 /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
+							298 0x1c0>; /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
+					};
+				};
+
+			};
+		};
+
+		spba at 50000000 {
+			compatible = "fsl,spba-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x50000000 0x100000>;
+			ranges;
+
+			uart3: serial at 5000c000 {
+				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+				reg = <0x5000c000 0x4000>;
+				interrupts = <18>;
+				status = "disabled";
+			};
+
+			fec: fec at 50038000 {
+				compatible = "fsl,imx35-fec", "fsl,imx27-fec";
+				reg = <0x50038000 0x4000>;
+				interrupts = <57>;
+				status = "disabled";
+			};
+		};
+
+		aips at 53f00000 { /* AIPS2 */
+			compatible = "fsl,aips", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x53f00000 0xffc0000>;
+			ranges;
+
+			gpio3: gpio at 0x53fa4000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fa4000 0x4000>;
+				interrupts = <56>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			esdhc1: esdhc at 53fb4000 {
+				compatible = "fsl,mx35-sdhc";
+				reg = <0x53fb4000 0x4000>;
+				interrupts = <7>;
+				status = "disabled";
+			};
+
+			esdhc2: esdhc at 53fb8000 {
+				compatible = "fsl,mx35-sdhc";
+				reg = <0x53fb8000 0x4000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			esdhc3: esdhc at 53fbc000 {
+				compatible = "fsl,mx35-sdhc";
+				reg = <0x53fbc000 0x4000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			gpio1: gpio at 0x53fcc000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fcc000 0x4000>;
+				interrupts = <52>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio at 0x53fd0000 {
+				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+				reg = <0x53fd0000 0x4000>;
+				interrupts = <51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			wdog at 53fdc000 {
+				compatible = "fsl,imx35-wdt", "fsl,imx2-wdt";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <55>;
+			};
+
+			can at 53fe4000 {
+				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				reg = <0x53fe4000 0x1000>;
+				interrupts = <43>;
+				status = "disabled";
+			};
+			can at 53fe8000 {
+				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+				reg = <0x53fe8000 0x1000>;
+				interrupts = <44>;
+				status = "disabled";
+			};
+		};
+
+		emi at 80000000 { /* External Memory Interface */
+			compatible = "fsl,emi", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x40000000>;
+			ranges;
+
+			nand at bb000000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				compatible = "fsl,imx35-nand", "fsl,imx25-nand";
+				reg = <0xbb000000 0x2000>;
+				interrupts = <33>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index f725b96..d27a3e2 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -28,6 +28,7 @@ CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
+CONFIG_MACH_IMX35_DT=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 156c986..0d9bf22 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -653,6 +653,18 @@ config MACH_VPR200
 	  Include support for VPR200 platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_IMX35_DT
+	bool "Support i.MX35 platforms from device tree"
+	select SOC_IMX35
+	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select PINCTRL
+	select PINCTRL_IMX35
+	help
+	  Include support for Freescale i.MX35 based platforms
+	  using the device tree for discovery
+
 comment "i.MX5 platforms:"
 
 config MACH_MX50_RDP
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 07f7c22..c68a925 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
 
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 83d614c..323907e 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -202,7 +202,9 @@ int __init mx35_clocks_init()
 				i, PTR_ERR(clk[i]));
 
 	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
+	clk_register_clkdev(clk[can1_gate], NULL, "53fe4000.can");
 	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
+	clk_register_clkdev(clk[can2_gate], NULL, "53fe8000.can");
 	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
 	clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
 	clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
@@ -219,12 +221,16 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
 	clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
 	clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
+	clk_register_clkdev(clk[fec_gate], NULL, "50038000.fec");
 	/* i.mx35 has the i.mx27 type fec */
 	clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
 	clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+	clk_register_clkdev(clk[i2c1_gate], NULL, "43f80000.i2c");
 	clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+	clk_register_clkdev(clk[i2c2_gate], NULL, "43f98000.i2c");
 	clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+	clk_register_clkdev(clk[i2c3_gate], NULL, "43f84000.i2c");
 	clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
 	clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
@@ -234,6 +240,12 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
 	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[uart1_gate], "per", "43f90000.serial");
+	clk_register_clkdev(clk[ipg], "ipg", "43f90000.serial");
+	clk_register_clkdev(clk[uart2_gate], "per", "43f94000.serial");
+	clk_register_clkdev(clk[ipg], "ipg", "43f94000.serial");
+	clk_register_clkdev(clk[uart3_gate], "per", "5000c000.serial");
+	clk_register_clkdev(clk[ipg], "ipg", "5000c000.serial");
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
@@ -253,7 +265,9 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
 	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
+	clk_register_clkdev(clk[wdog_gate], NULL, "53fdc000.wdog");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+	clk_register_clkdev(clk[nfc_div], NULL, "bb000000.nand");
 	clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
 
 	clk_prepare_enable(clk[spba_gate]);
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
new file mode 100644
index 0000000..52b619a
--- /dev/null
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27-dt.c
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx35.h>
+#include <mach/hardware.h>
+#include <linux/gpio.h>
+
+static void __init imx35_dt_init(void)
+{
+	/* Some mx35 have problems when the cache is not initialized
+	 * FIXME: ultimatly this belongs in the oftree definition
+	 */
+	imx3_init_l2x0();
+	pinctrl_provide_dummies();
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init imx35_timer_init(void)
+{
+	mx35_clocks_init();
+}
+
+static struct sys_timer imx35_timer = {
+	.init = imx35_timer_init,
+};
+
+static const char *imx35_dt_board_compat[] __initdata = {
+	"fsl,imx35",
+	NULL
+};
+
+DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
+	.map_io		= mx35_map_io,
+	.init_early	= imx35_init_early,
+	.init_irq	= mx35_init_irq,
+	.handle_irq	= imx35_handle_irq,
+	.timer		= &imx35_timer,
+	.init_machine	= imx35_dt_init,
+	.dt_compat	= imx35_dt_board_compat,
+	.restart	= mxc_restart,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e97..82b0a57 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -50,6 +50,7 @@ extern void imx25_soc_init(void);
 extern void imx27_soc_init(void);
 extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
+extern void imx3_init_l2x0(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx53_soc_init(void);
-- 
1.7.10.4



From u.kleine-koenig at pengutronix.de  Fri Aug 10 05:32:50 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 10 Aug 2012 11:32:50 +0200
Subject: [PATCH v2 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

--
changes since (implicit) v1
(id:1343922986-32469-2-git-send-email-u.kleine-koenig at pengutronix.de)

 - add newlines between nodes
 - adapt to changes in patch 1
---
 arch/arm/boot/dts/phytec-pcm043.dtsi |   57 ++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 arch/arm/boot/dts/phytec-pcm043.dtsi

diff --git a/arch/arm/boot/dts/phytec-pcm043.dtsi b/arch/arm/boot/dts/phytec-pcm043.dtsi
new file mode 100644
index 0000000..e3b8690
--- /dev/null
+++ b/arch/arm/boot/dts/phytec-pcm043.dtsi
@@ -0,0 +1,57 @@
+/include/ "imx35.dtsi"
+
+/ {
+	soc {
+		aips at 40000000 { /* AIPS1 */
+			i2c at 43f80000 {
+				status = "okay";
+
+				tempsens at 4a {
+					compatible = "maxim,ds75";
+					reg = <0x4a>;
+				};
+
+				rtc8564 at 51 {
+					compatible = "nxp,pcf8563";
+					reg = <0x51>;
+				};
+
+				at24 at 52 {
+					compatible = "at,24c32";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+			};
+
+			serial at 43f90000 {
+				status = "okay";
+			};
+
+			serial at 43f94000 {
+				status = "okay";
+			};
+		};
+
+		spba at 50000000 {
+			serial at 5000c000 {
+				status = "okay";
+			};
+
+			fec at 50038000 {
+				status = "okay";
+			};
+		};
+
+		emi at 80000000 {
+			nor at a0000000 {
+				compatible = "cfi-flash";
+				reg = <0xa0000000 0x2000000>;
+				bank-width = <2>;
+			};
+
+			nand at bb000000 {
+				status = "okay";
+			};
+		};
+	};
+};
-- 
1.7.10.4



From lee.jones at linaro.org  Fri Aug 10 05:37:29 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 10 Aug 2012 10:37:29 +0100
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
In-Reply-To: <CACRpkdZCKQCkWSPYby2rYd4Oas481nZE7eDmZRETovJOks2p0Q@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <20120809185029.GC24328@opensource.wolfsonmicro.com>
 <20120809194044.GA9966@gmail.com>
 <CACRpkdZCKQCkWSPYby2rYd4Oas481nZE7eDmZRETovJOks2p0Q@mail.gmail.com>
Message-ID: <20120810093728.GD18708@gmail.com>

On Fri, Aug 10, 2012 at 10:48:39AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 9:40 PM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Thu, Aug 09, 2012 at 07:50:29PM +0100, Mark Brown wrote:
> >> On Thu, Aug 09, 2012 at 04:47:26PM +0100, Lee Jones wrote:
> >> > Another fine instalment of Audio fixes and Device Tree enablement
> >> > surrounding the mop500 sound driver. Hopefully containing all of
> >> > the recommendations suggested by Mark Brown.
> >>
> >> Can we have some review of this from the ARM side please?  It's pretty
> >> big...
> >
> > I don't expect Linus will do anything until he returns back from vacation.
> 
> I'm back from vacation, and catching up. Now there is a few different
> DT patch bombs from you in my inbox, which patchset shall I review
> first? This one? Or is there a more urgent one?

You can ignore all the ones from before yesterday.

None are more important than the other, as I'm on vacation all next week.

Take your time and I'll see to the carnage when I return. :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From dave.martin at linaro.org  Fri Aug 10 05:59:11 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 10 Aug 2012 10:59:11 +0100
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <alpine.LFD.2.02.1208091721460.5231@xanadu.home>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-5-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208091709010.5231@xanadu.home>
 <20120809211717.GW18957@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1208091721460.5231@xanadu.home>
Message-ID: <20120810095911.GA2157@linaro.org>

On Thu, Aug 09, 2012 at 05:22:30PM -0400, Nicolas Pitre wrote:
> On Thu, 9 Aug 2012, Russell King - ARM Linux wrote:
> 
> > On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote:
> > > CFLAGS_THUMB2 should probably be renamed to something more appropriate 
> > > in this case, e.g. CFLAGS_MODE.
> > 
> > CFLAGS_ISA would be more relevant to it, because it's selecting the
> > instruction set.
> 
> Agreed.  This particular TLA escaped my mind somehow.

Seems fair enough.  It doesn't quite match the official architectural
terminology, but it clear enough what it means, and less cumbersome than
the alternatives.

Best not to use MODE though.  That word is way too overloaded.

---Dave



From broonie at opensource.wolfsonmicro.com  Fri Aug 10 06:07:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 10 Aug 2012 11:07:13 +0100
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
Message-ID: <20120810100713.GH24328@opensource.wolfsonmicro.com>

On Fri, Aug 10, 2012 at 01:56:23PM +0900, Kukjin Kim wrote:

> Probably, this patch needs following?

> If you're ok, I will fix build error by above when I apply.

Yes, thanks.


From arnd at arndb.de  Fri Aug 10 06:49:57 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 10:49:57 +0000
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <5023D577.8090001@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <201208091143.32972.arnd@arndb.de> <5023D577.8090001@codethink.co.uk>
Message-ID: <201208101049.57586.arnd@arndb.de>

On Thursday 09 August 2012, Ian Molton wrote:
> >  I think showing one
> > parent device with children at address 0, 1 and 2 is ok.
> Is it acceptable for the child devices to directly access the
> parents register space? because there would be no other
> way for that to work.

Yes, I see no problem with that. As long as all the drivers
agree on who can access what.

> >  The driver
> > already knows all those offsets and they are always the same
> > for all variants of mv643xx, right?
> Yes, but its not clean. And no amount of refactoring is
> really going to make a nice driver that also fits the ancient
> (and badly thought out) OF bindings.

In what way is it badly though out, or not clean? The use of
underscores in the properties, and the way that the sram
is configured is problematic, I agree. But The way that
the three ports are addressed and how the PHY is found
seems quite clever.

> If we have to break things, we can at least go for a nice
> clean design, surely?
> 
> The ports arent really child devices of the MAC. The MAC
> just has 3 ports.

I don't see the difference between those two things.

> Luckily, it looks like the existing users don't actually use
> the device tree to set up the driver at all, preferring to
> translate their D-T bindings to calls to
> platform_device_register() so all we'd need to do to
> support them is completely ignore them.
> 
> We're going to have to maintain a legacy
> platform_device -> DT bindings hack somewhere anyway,
> at least until the remaining other users of the driver
> convert to D-T.

I don't understand why you describe the method used in
powerpc as a hack. It was the normal way to introduce
DT support for platform devices back when it was implemented.
It also had the advantage of not requiring any modifications
to the generic driver, because it was shared between one
architecture using DT (powerpc) and one that didn't (ARM).

	Arnd


From linus.walleij at linaro.org  Fri Aug 10 06:56:51 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 12:56:51 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <5023C923.3080808@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
 <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>
 <5023C923.3080808@gmail.com>
Message-ID: <CACRpkda0443PF-SwNaiJCO9RmdCFqw1+OtLgTBoTfZzwnFjJ4w@mail.gmail.com>

On Thu, Aug 9, 2012 at 4:28 PM, Daniel Mack <zonque at gmail.com> wrote:

> I am looking at the generic pinctrl code right now

Sweet!

> and I wonder if the following approach would be ok:
>
> - each driver that calls pinctrl_register() has its own dt_match_table
> entry, so the 'compatible' part of the bindings is specific to a pin
> controller chip.

Yep.

> - introduce a pinctrl_parse_of(struct of_node *) and call that after the
> driver has added all its pins. That function walks all the children of
> the given node and uses the callbacks provided by the driver to do the
> actual work.

Isn't that already how it works? Maybe I misunderstand, do you mean
that you want to pass the DT node to pinctrl_register()?

Are you talking about using pinctrl hogs to set up the default
configuration and muxing? That can already be done today,
and has nothing to do with whether you use generic pin config
or not.

This uses the .dt_node_to_map() and .dt_free_map() callbacks
in the pinctrl_ops vtable to generate a map from the device tree,
in any way you want.

So the infrastructure I think already exists, but whereas all
current driver have their own config and mux (etc) parsing
code, pinconf-generic could provide something that would
be common for all driver using generic pin config.

> - Unfortunately, we can't parse the node from pinctrl_register() as the
> gpio ranges are only added after that by the drivers.

The ranges are a *big* problem and we haven't come up with
a proper DT binding for these. After discussion with Grant,
he has proposed that GPIO chips should register their ranges
using their local numberspace and always passing the
struct gpio_chip, instead of pin controllers registering ranges.
Documented here:
https://blueprints.launchpad.net/linux-linaro/+spec/pinctrl-gpiorange-makeover

> If that sounds good, I can come up with a patch.

I think you already have what you need, look closer at how
e.g. the Tegra or i.MX driver does this. Or maybe I'm only
getting it backwards?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 10 06:59:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 12:59:32 +0200
Subject: [PATCH 06/11] gpio: em: do not discard em_gio_irq_domain_cleanup
In-Reply-To: <1344437248-20560-7-git-send-email-arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-7-git-send-email-arnd@arndb.de>
Message-ID: <CACRpkdZnaH3RXHqif7wiA5bor4vOcBndnabG-7QNLnmUc3Oj3Q@mail.gmail.com>

On Wed, Aug 8, 2012 at 4:47 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> The newly added gpio-em driver marks its em_gio_irq_domain_cleanup
> function as __devexit, which would lead to that function being
> discarded in case CONFIG_HOTPLUG is disabled. However, the function
> is also called by the error handling logic em_gio_probe, which
> would cause a jump into a NULL pointer if it was removed from the
> kernel or module.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Will you push this through the ARM SoC tree or do you want me
to apply it to my GPIO tree?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 10 07:01:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 13:01:35 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <20120809162742.GG25520@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120809162742.GG25520@pengutronix.de>
Message-ID: <CACRpkdaRLFzjq49pd=e7GzPmWuX5C2nWDWZitZV9e6AkHBK4DA@mail.gmail.com>

On Thu, Aug 9, 2012 at 6:27 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

>> +  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
>
> argh, I forgot to fix that (ie. s/53/35/). I won't resend just for that.
> Linus, assuming you intend to take the patch now, can you fix it up
> while commiting please?

Sure, but I want an ACK from a Freescale maintainer first ...

Linus Walleij


From arnd at arndb.de  Fri Aug 10 07:03:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 11:03:58 +0000
Subject: [PATCH 09/10] ARM: rpc: Fix building RiscPC
In-Reply-To: <20120809074754.GP18957@n2100.arm.linux.org.uk>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-10-git-send-email-arnd@arndb.de>
 <20120809074754.GP18957@n2100.arm.linux.org.uk>
Message-ID: <201208101103.58808.arnd@arndb.de>

On Thursday 09 August 2012, Russell King - ARM Linux wrote:
> On Wed, Aug 08, 2012 at 11:27:57PM +0200, Arnd Bergmann wrote:
> > ARMv3 support was removed in 357c9c1f07 "ARM: Remove support for ARMv3
> > ARM610 and ARM710 CPUs", which explicitly left parts of the CPU32v3
> > support in place for building RiscPC. However, this does not actually
> > build in my test setup.
> > 
> > This is probably not the right solution, but maybe someone has a better
> > idea for how to deal with this.
> 
> This isn't the right solution.  The RiscPC bus does not support half-word
> load/stores, so we must continue to build that target for the 32v3
> architecture (which is why I carefully left that stuff behind.)
> 
> The mistake is in what I did with arch/arm/lib - the armv3 code in there
> needs to be resurected instead.

Ok, I'll drop my patch from the series then and wait for you to
fix this properly.

	Arnd


From arnd at arndb.de  Fri Aug 10 07:12:20 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 11:12:20 +0000
Subject: [PATCH 04/10] ARM: pass -marm to gcc by default
In-Reply-To: <20120810095911.GA2157@linaro.org>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208091721460.5231@xanadu.home>
 <20120810095911.GA2157@linaro.org>
Message-ID: <201208101112.20416.arnd@arndb.de>

On Friday 10 August 2012, Dave Martin wrote:
> On Thu, Aug 09, 2012 at 05:22:30PM -0400, Nicolas Pitre wrote:
> > On Thu, 9 Aug 2012, Russell King - ARM Linux wrote:
> > 
> > > On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote:
> > > > CFLAGS_THUMB2 should probably be renamed to something more appropriate 
> > > > in this case, e.g. CFLAGS_MODE.
> > > 
> > > CFLAGS_ISA would be more relevant to it, because it's selecting the
> > > instruction set.
> > 
> > Agreed.  This particular TLA escaped my mind somehow.
> 
> Seems fair enough.  It doesn't quite match the official architectural
> terminology, but it clear enough what it means, and less cumbersome than
> the alternatives.
> 
> Best not to use MODE though.  That word is way too overloaded.

Ok. I already noticed that we already set -marm in KBUILD_CFLAGS but
not in the AFLAGS. This new version should cover all the issues
and make it more obvious what's actually going on.

	Arnd

8<----
From 34763772164d1442509f27d7f8a09326ff4b7878 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Mon, 30 Apr 2012 12:40:00 +0000
Subject: [PATCH] ARM: pass -marm to gcc by default for both C and assembler

The Linaro cross toolchain and probably others nowadays default to
building in THUMB2 mode. When building a kernel for a CPU that does
not support THUMB2, the compiler complains about incorrect flags.
We can work around this by setting -marm for all non-T2 builds.

Without this patch, building assabet_defconfig results in:

usr/initramfs_data.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
arch/arm/nwfpe/entry.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
firmware/cis/PCMLM28.cis.gen.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default]
(and many more)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Dave Martin <dave.martin at linaro.org>

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..ca0dabc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -21,8 +21,6 @@ endif
 OBJCOPYFLAGS	:=-O binary -R .comment -S
 GZFLAGS		:=-9
 #KBUILD_CFLAGS	+=-pipe
-# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
-KBUILD_CFLAGS	+=$(call cc-option,-marm,)
 
 # Never generate .eh_frame
 KBUILD_CFLAGS	+= $(call cc-option,-fno-dwarf2-cfi-asm)
@@ -105,17 +103,20 @@ endif
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
 AFLAGS_AUTOIT	:=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
 AFLAGS_NOWARN	:=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
-CFLAGS_THUMB2	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
-AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
+CFLAGS_ISA	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
+AFLAGS_ISA	:=$(CFLAGS_ISA) -Wa$(comma)-mthumb
 # Work around buggy relocation from gas if requested:
 ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)
 CFLAGS_MODULE	+=-fno-optimize-sibling-calls
 endif
+else
+CFLAGS_ISA	:=$(call cc-option,-marm,)
+AFLAGS_ISA	:=$(CFLAGS_ISA)
 endif
 
 # Need -Uarm for gcc < 3.x
-KBUILD_CFLAGS	+=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-KBUILD_AFLAGS	+=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
+KBUILD_CFLAGS	+=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
+KBUILD_AFLAGS	+=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
 
 CHECKFLAGS	+= -D__arm__
 


From marex at denx.de  Fri Aug 10 07:25:22 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 10 Aug 2012 13:25:22 +0200
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344568737-902-1-git-send-email-b32955@freescale.com>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
Message-ID: <201208101325.23075.marex@denx.de>

Dear Huang Shijie,

> Add NAND write verify support in gpmi-nand driver.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   17 +++++++++++++++++
>  1 files changed, 17 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..6394483 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1488,6 +1488,22 @@ static int gpmi_set_geometry(struct gpmi_nand_data
> *this) return gpmi_alloc_dma_buffer(this);
>  }
> 
> +#define MAX_PAGESIZE 8192

Use NAND_MAX_PAGESIZE, see include/linux/mtd/nand.h .

> +static uint8_t verify_buf[MAX_PAGESIZE];

What will happen when you have two NANDs attached to GPMI controller and they 
hit this place both at once? Race condition, causing this function to fail for 
both?

Possibly devm_kmalloc() such buffer per-controller?

> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
> len) +{
> +	struct nand_chip *nand = mtd->priv;
> +	int ret;
> +
> +	ret = gpmi_ecc_read_page(mtd, nand, verify_buf, 0, 0);

mtd->chip.ecc.read_page() ?

> +	if (ret)
> +		return -EFAULT;
> +	if (memcmp(buf, verify_buf, len))
> +		return -EFAULT;
> +	return 0;
> +}
> +
>  static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
>  {
>  	int ret;
> @@ -1556,6 +1572,7 @@ static int __devinit gpmi_nfc_init(struct
> gpmi_nand_data *this) chip->read_byte		= gpmi_read_byte;
>  	chip->read_buf		= gpmi_read_buf;
>  	chip->write_buf		= gpmi_write_buf;
> +	chip->verify_buf	= gpmi_verify_buf;
>  	chip->ecc.read_page	= gpmi_ecc_read_page;
>  	chip->ecc.write_page	= gpmi_ecc_write_page;
>  	chip->ecc.read_oob	= gpmi_ecc_read_oob;

Best regards,
Marek Vasut


From arnd at arndb.de  Fri Aug 10 07:33:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 11:33:08 +0000
Subject: [PATCH 06/11] gpio: em: do not discard em_gio_irq_domain_cleanup
In-Reply-To: <CACRpkdZnaH3RXHqif7wiA5bor4vOcBndnabG-7QNLnmUc3Oj3Q@mail.gmail.com>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <1344437248-20560-7-git-send-email-arnd@arndb.de>
 <CACRpkdZnaH3RXHqif7wiA5bor4vOcBndnabG-7QNLnmUc3Oj3Q@mail.gmail.com>
Message-ID: <201208101133.08945.arnd@arndb.de>

On Friday 10 August 2012, Linus Walleij wrote:
> On Wed, Aug 8, 2012 at 4:47 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> > The newly added gpio-em driver marks its em_gio_irq_domain_cleanup
> > function as __devexit, which would lead to that function being
> > discarded in case CONFIG_HOTPLUG is disabled. However, the function
> > is also called by the error handling logic em_gio_probe, which
> > would cause a jump into a NULL pointer if it was removed from the
> > kernel or module.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Will you push this through the ARM SoC tree or do you want me
> to apply it to my GPIO tree?

I'm about to send out the whole series to Torvalds, so I'll just
keep it in now.

	Arnd


From linus.walleij at linaro.org  Fri Aug 10 07:43:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 10 Aug 2012 13:43:56 +0200
Subject: [PATCH 1/6] ASoC: dapm: If one widget fails, do not force all
 subsequent widgets to fail too
In-Reply-To: <003901cd7073$d49cacc0$7dd60640$@se>
References: <1343741493-17671-1-git-send-email-lee.jones@linaro.org>
 <1343741493-17671-3-git-send-email-lee.jones@linaro.org>
 <20120731134214.GK4468@opensource.wolfsonmicro.com>
 <5017EAC3.3080504@linaro.org>
 <20120731142820.GW4468@opensource.wolfsonmicro.com>
 <5017EDCA.4020601@linaro.org>
 <20120731145443.GY4468@opensource.wolfsonmicro.com>
 <5017F68B.3060400@linaro.org>
 <20120731151819.GC4468@opensource.wolfsonmicro.com>
 <5018D880.5090306@linaro.org>
 <20120801132022.GS11892@opensource.wolfsonmicro.com>
 <003901cd7073$d49cacc0$7dd60640$@se>
Message-ID: <CACRpkdZeYAnqg7HLi_bH51_=s60OZB7ySn1W+YQ=H9fz8xZUCg@mail.gmail.com>

(As for the thread, which got flamy, let's put it to rest, and Ola:
 we are all impressed with your work on the ux500 ALSA SoC
 driver, no doubt about that, this was all ever about the DT
 patch set.)

On Thu, Aug 2, 2012 at 7:58 AM, Ola Lilja <olalilja at yahoo.se> wrote:

> Linus W. could probably shed some light of when the missing clocks are to
> be submitted.

Ulf Hansson is working on this but he's on vacation FTM.
However he has shown good progress and can probably present
a prototype clock driver when he arrives back. IIRC there was
some clock reparenting business left to sort out.

Yours,
Linus Walleij


From dave.martin at linaro.org  Fri Aug 10 07:53:24 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 10 Aug 2012 12:53:24 +0100
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
Message-ID: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>

Because FIQ handlers get copied straight into the vectors page to
the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
Thumb-2.

This patch adapts the mxc SSI FIQ code suitable for a Thumb-2
kernel.

The code contained use of r13 (sp) which isn't allowed in Thumb-2.
r11 and r13 have been swapped throughout the file to work around
this.

Currently, the way that the function to be copied is located using
labels is a bit ugly: we cannot annotate the FIQ handler properly
as a Thumb-2 function, because this would set bit 0 of the label
address seen by the linker, causing off-by-one errors when copying
the function.  Ideally, the copy would be done with fncpy(), but
this would require changes to the common set_fiq_handler()
function.  For now, we don't touch this.

References to locally-defined global symbols with adr and ldr may
not be accepted by the assembler in Thumb-2.  Local shadow symbols
are added to work around this.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
---

Note that while this code builds, I don't know the hardware well enough 
to be confident testing it.  Review and testing from anyone with
experience of imx SoC audio would be appreciated.

 arch/arm/plat-mxc/ssi-fiq.S |   89 ++++++++++++++++++++++++-------------------
 1 files changed, 50 insertions(+), 39 deletions(-)

diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2d..a8b93c5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
 		.global imx_ssi_fiq_rx_buffer
 		.global imx_ssi_fiq_tx_buffer
 
+/*
+ * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
+ * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
+ * mark the function body so that it can be copied to the FIQ vector in
+ * the vectors page.  imx_ssi_fiq_start should only be called as the result
+ * of an FIQ: calling it directly will not work.
+ */
 imx_ssi_fiq_start:
-		ldr r12, imx_ssi_fiq_base
+		ldr r12, .L_imx_ssi_fiq_base
 
 		/* TX */
-		ldr r11, imx_ssi_fiq_tx_buffer
+		ldr r13, .L_imx_ssi_fiq_tx_buffer
 
 		/* shall we send? */
-		ldr r13, [r12, #SSI_SIER]
-		tst r13, #SSI_SIER_TFE0_EN
+		ldr r11, [r12, #SSI_SIER]
+		tst r11, #SSI_SIER_TFE0_EN
 		beq 1f
 
 		/* TX FIFO empty? */
-		ldr r13, [r12, #SSI_SISR]
-		tst r13, #SSI_SISR_TFE0
+		ldr r11, [r12, #SSI_SISR]
+		tst r11, #SSI_SISR_TFE0
 		beq 1f
 
 		mov r10, #0x10000
 		sub r10, #1
 		and r10, r10, r8	/* r10: current buffer offset */
 
-		add r11, r11, r10
+		add r13, r13, r10
 
-		ldrh r13, [r11]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r11, [r13]
+		strh r11, [r12, #SSI_STX0]
 
-		ldrh r13, [r11, #2]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r11, [r13, #2]
+		strh r11, [r12, #SSI_STX0]
 
-		ldrh r13, [r11, #4]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r11, [r13, #4]
+		strh r11, [r12, #SSI_STX0]
 
-		ldrh r13, [r11, #6]
-		strh r13, [r12, #SSI_STX0]
+		ldrh r11, [r13, #6]
+		strh r11, [r12, #SSI_STX0]
 
 		add r10, #8
-		lsr r13, r8, #16	/* r13: buffer size */
-		cmp r10, r13
-		lslgt r8, r13, #16
+		lsr r11, r8, #16	/* r11: buffer size */
+		cmp r10, r11
+		lslgt r8, r11, #16
 		addle r8, #8
 1:
 		/* RX */
 
 		/* shall we receive? */
-		ldr r13, [r12, #SSI_SIER]
-		tst r13, #SSI_SIER_RFF0_EN
+		ldr r11, [r12, #SSI_SIER]
+		tst r11, #SSI_SIER_RFF0_EN
 		beq 1f
 
 		/* RX FIFO full? */
-		ldr r13, [r12, #SSI_SISR]
-		tst r13, #SSI_SISR_RFF0
+		ldr r11, [r12, #SSI_SISR]
+		tst r11, #SSI_SISR_RFF0
 		beq 1f
 
-		ldr r11, imx_ssi_fiq_rx_buffer
+		ldr r13, .L_imx_ssi_fiq_rx_buffer
 
 		mov r10, #0x10000
 		sub r10, #1
 		and r10, r10, r9	/* r10: current buffer offset */
 
-		add r11, r11, r10
+		add r13, r13, r10
 
-		ldr r13, [r12, #SSI_SACNT]
-		tst r13, #SSI_SACNT_AC97EN
+		ldr r11, [r12, #SSI_SACNT]
+		tst r11, #SSI_SACNT_AC97EN
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11]
+		ldr r11, [r12, #SSI_SRX0]
+		strh r11, [r13]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #2]
+		ldr r11, [r12, #SSI_SRX0]
+		strh r11, [r13, #2]
 
 		/* dummy read to skip slot 12 */
-		ldrne r13, [r12, #SSI_SRX0]
+		ldrne r11, [r12, #SSI_SRX0]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #4]
+		ldr r11, [r12, #SSI_SRX0]
+		strh r11, [r13, #4]
 
-		ldr r13, [r12, #SSI_SRX0]
-		strh r13, [r11, #6]
+		ldr r11, [r12, #SSI_SRX0]
+		strh r11, [r13, #6]
 
 		/* dummy read to skip slot 12 */
-		ldrne r13, [r12, #SSI_SRX0]
+		ldrne r11, [r12, #SSI_SRX0]
 
 		add r10, #8
-		lsr r13, r9, #16	/* r13: buffer size */
-		cmp r10, r13
-		lslgt r9, r13, #16
+		lsr r11, r9, #16	/* r11: buffer size */
+		cmp r10, r11
+		lslgt r9, r11, #16
 		addle r9, #8
 
 1:
@@ -126,11 +133,15 @@ imx_ssi_fiq_start:
 		subs	pc, lr, #4
 
 		.align
+.L_imx_ssi_fiq_base:
 imx_ssi_fiq_base:
 		.word 0x0
+.L_imx_ssi_fiq_rx_buffer:
 imx_ssi_fiq_rx_buffer:
 		.word 0x0
+.L_imx_ssi_fiq_tx_buffer:
 imx_ssi_fiq_tx_buffer:
 		.word 0x0
+.L_imx_ssi_fiq_end:
 imx_ssi_fiq_end:
 
-- 
1.7.4.1



From u.kleine-koenig at pengutronix.de  Fri Aug 10 08:18:31 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 10 Aug 2012 14:18:31 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <CACRpkdaRLFzjq49pd=e7GzPmWuX5C2nWDWZitZV9e6AkHBK4DA@mail.gmail.com>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120809162742.GG25520@pengutronix.de>
 <CACRpkdaRLFzjq49pd=e7GzPmWuX5C2nWDWZitZV9e6AkHBK4DA@mail.gmail.com>
Message-ID: <20120810121831.GJ25520@pengutronix.de>

Hallo Linus, 

On Fri, Aug 10, 2012 at 01:01:35PM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 6:27 PM, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
> 
> >> +  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
> >
> > argh, I forgot to fix that (ie. s/53/35/). I won't resend just for that.
> > Linus, assuming you intend to take the patch now, can you fix it up
> > while commiting please?
> 
> Sure, but I want an ACK from a Freescale maintainer first ...
I assume you saw the patch has Dong Aisheng's ack, so you want another
one by Shawn or Sascha?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From shawn.guo at linaro.org  Fri Aug 10 08:29:37 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 20:29:37 +0800
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <20120810121831.GJ25520@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120809162742.GG25520@pengutronix.de>
 <CACRpkdaRLFzjq49pd=e7GzPmWuX5C2nWDWZitZV9e6AkHBK4DA@mail.gmail.com>
 <20120810121831.GJ25520@pengutronix.de>
Message-ID: <20120810122935.GA3409@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 02:18:31PM +0200, Uwe Kleine-K?nig wrote:
> I assume you saw the patch has Dong Aisheng's ack, so you want another
> one by Shawn or Sascha?
> 
Acked-by: Shawn Guo <shawn.guo at linaro.org>

-- 
Regards,
Shawn



From knut.wohlrab at de.bosch.com  Fri Aug 10 08:30:59 2012
From: knut.wohlrab at de.bosch.com (Knut Wohlrab)
Date: Fri, 10 Aug 2012 14:30:59 +0200
Subject: How to define gpio irq with device tree
Message-ID: <5024FF03.1070805@de.bosch.com>

Hello,

I try the touch screen of a iMX6 SabreLite evaluation board. The used 
eGalax touch controller worked fine with a 3.2.x kernel [1]. As 
mentioned there [2] I merge the basic device tree support to the actual 
driver (see patch [4]) and add the touch definition to 
arch/arm/boot/dts/imx6q-sabrelite.dts [3].

The driver seems to start but the interrupt never occurs.

The pinmux and I2C configuration seems correct. I did a simple test with 
polling the interrupt gpio (see "POLLTEST" in patch [4]) and got 
coordinates matching to the movements on the screen.

How to configure the gpio irq correctly?

Anybody solved to work with the eGalax touch and iMX6 SabreLite with 
kernel > 3.2?

Thanks a lot for any information.


[1]
http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=shortlog;h=refs/heads/lt-3.2-imx6 


[2]
http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=blob;f=drivers/input/touchscreen/egalax_ts.c;h=58184dad7a2e1b6a42711acddb184d68ffceeb4c;hb=refs/heads/lt-3.2-imx6 


[3]
...
             i2c at 021a8000 { /* I2C3 */
                 status = "okay";
                 clock-frequency = <400000>;

                 egalax at 04 {
                     compatible = "eeti,egalax";
                     reg = <0x04>;
                     interrupt-parent = <&gpio1>;
                     interrupts = <9 0x08>;
                     interrupt-gpio = <&gpio1 9 0>;
                 };
...

[4]

diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
index 70524dd..653a97a 100644
--- a/drivers/input/touchscreen/egalax_ts.c
+++ b/drivers/input/touchscreen/egalax_ts.c
@@ -28,6 +28,9 @@
  #include <linux/slab.h>
  #include <linux/bitops.h>
  #include <linux/input/mt.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
  
  /*
   * Mouse Mode: some panel may configure the controller to mouse mode,
@@ -62,6 +65,7 @@
  struct egalax_ts {
  	struct i2c_client		*client;
  	struct input_dev		*input_dev;
+	int 					gpio_irq;
  };
  
  static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
@@ -122,7 +126,8 @@ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
  /* wake up controller by an falling edge of interrupt gpio.  */
  static int egalax_wake_up_device(struct i2c_client *client)
  {
-	int gpio = irq_to_gpio(client->irq);
+	struct egalax_ts *ts = i2c_get_clientdata(client);
+	int gpio = ts->gpio_irq;
  	int ret;
  
  	ret = gpio_request(gpio, "egalax_irq");
@@ -159,6 +164,7 @@ static int __devinit egalax_firmware_version(struct i2c_client *client)
  static int __devinit egalax_ts_probe(struct i2c_client *client,
  				       const struct i2c_device_id *id)
  {
+	struct device_node *n = client->dev.of_node;
  	struct egalax_ts *ts;
  	struct input_dev *input_dev;
  	int ret;
@@ -179,6 +185,13 @@ static int __devinit egalax_ts_probe(struct i2c_client *client,
  
  	ts->client = client;
  	ts->input_dev = input_dev;
+	ts->gpio_irq = of_get_named_gpio(n, "interrupt-gpio", 0);
+	if (!gpio_is_valid(ts->gpio_irq))
+		dev_warn(&client->dev, "invalid interrupt GPIO\n");
+	else
+		dev_info(&client->dev, "valid interrupt GPIO:%d\n", ts->gpio_irq);
+
+	i2c_set_clientdata(client, ts);
  
  	/* controller may be in sleep, wake it up. */
  	egalax_wake_up_device(client);
@@ -214,13 +227,31 @@ static int __devinit egalax_ts_probe(struct i2c_client *client,
  	if (error < 0) {
  		dev_err(&client->dev, "Failed to register interrupt\n");
  		goto err_free_dev;
+	}else{
+		dev_info(&client->dev, "register interrupt: %d\n", client->irq);
  	}
  
  	error = input_register_device(ts->input_dev);
  	if (error)
  		goto err_free_irq;
  
-	i2c_set_clientdata(client, ts);
+//#define POLLTEST
+#ifdef POLLTEST
+	while(1){
+		if(!gpio_get_value(ts->gpio_irq)){
+			u8 buf[MAX_I2C_DATA_LEN];
+			int i, ret, tries = 0;
+			do {
+				ret = i2c_master_recv(client, buf, MAX_I2C_DATA_LEN);
+
+				for(i=0; i<ret; ++i)
+					printk("0x%02X ", buf[i]);
+
+				printk("\n");
+			} while (ret == -EAGAIN && tries++ < EGALAX_MAX_TRIES);
+		}
+	}
+#endif
  	return 0;
  
  err_free_irq:
@@ -251,6 +282,12 @@ static const struct i2c_device_id egalax_ts_id[] = {
  };
  MODULE_DEVICE_TABLE(i2c, egalax_ts_id);
  
+static struct of_device_id egalax_dt_ids[] = {
+	{ .compatible = "eeti,egalax" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
+
  #ifdef CONFIG_PM_SLEEP
  static int egalax_ts_suspend(struct device *dev)
  {
@@ -279,6 +316,7 @@ static struct i2c_driver egalax_ts_driver = {
  		.name	= "egalax_ts",
  		.owner	= THIS_MODULE,
  		.pm	= &egalax_ts_pm_ops,
+		.of_match_table	= egalax_dt_ids,
  	},
  	.id_table	= egalax_ts_id,
  	.probe		= egalax_ts_probe,



From plagnioj at jcrosoft.com  Fri Aug 10 08:48:20 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 14:48:20 +0200
Subject: [PATCH 00/14] ARM: at91: add pinctrl support
Message-ID: <20120810124820.GA20557@game.jcrosoft.org>

Hi,

	This patch series introduce the pinctrl on AT91 on all the DT Soc.

	THe pinctrl is limited to only the DT. Old code still use the custom
	at91 pin mux api.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git j/pinctrl

for you to fetch changes up to 7ff6e8b37d1f334ef24b87661c40aaa548dd93f6:

  MTD: atmel_nand: add pinctrl consumer support (2012-08-10 20:46:24 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (14):
      ARM: at91: gpio: implement request and free
      at91: regroup gpio and pinctrl under a simple-bus
      arm: at91: at91sam9x5: fix gpio number per bank
      ARM: at91: add dummies pinctrl for non dt platform
      ARM: at91: add pinctrl support
      arm: at91: dt: at91sam9 add pinctrl support
      arm: at91: dt: at91sam9 add serial pinctrl support
      tty: atmel_serial: add pinctrl support
      arm: at91: dt: sam9m10g45ek: use rts/cts pinctrl group for uart1
      arm: at91: dt: sam9263ek: use rts/cts pinctrl group for uart0
      arm: at91: dt: sam9g20ek: use rts/cts/dtr/dsr/dcd/ri pinctrl group for uart0
      MTD: atmel nand: fix gpio missing request
      arm: at91: dt: at91sam9 add nand pinctrl support
      MTD: atmel_nand: add pinctrl consumer support

 Documentation/devicetree/bindings/gpio/gpio_atmel.txt            |    5 +
 Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt |   84 ++++++++
 arch/arm/Kconfig                                                 |    1 +
 arch/arm/boot/dts/at91sam9260.dtsi                               |  182 +++++++++++++---
 arch/arm/boot/dts/at91sam9263.dtsi                               |  164 +++++++++++----
 arch/arm/boot/dts/at91sam9263ek.dts                              |    1 +
 arch/arm/boot/dts/at91sam9g15.dtsi                               |   28 +++
 arch/arm/boot/dts/at91sam9g15ek.dts                              |   16 ++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi                      |    6 +
 arch/arm/boot/dts/at91sam9g25.dtsi                               |   28 +++
 arch/arm/boot/dts/at91sam9g25ek.dts                              |   37 +---
 arch/arm/boot/dts/at91sam9g35.dtsi                               |   28 +++
 arch/arm/boot/dts/at91sam9g35ek.dts                              |   16 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                               |  181 ++++++++++++----
 arch/arm/boot/dts/at91sam9m10g45ek.dts                           |    1 +
 arch/arm/boot/dts/at91sam9n12.dtsi                               |  173 +++++++++++++---
 arch/arm/boot/dts/at91sam9x25.dtsi                               |   28 +++
 arch/arm/boot/dts/at91sam9x25ek.dts                              |   16 ++
 arch/arm/boot/dts/at91sam9x35.dtsi                               |   28 +++
 arch/arm/boot/dts/at91sam9x35ek.dts                              |   16 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                                |  179 +++++++++++++---
 arch/arm/boot/dts/at91sam9x5ek.dtsi                              |   47 +++++
 arch/arm/configs/at91_dt_defconfig                               |    1 +
 arch/arm/mach-at91/Makefile.boot                                 |    4 +
 arch/arm/mach-at91/at91sam9263.c                                 |    5 +
 arch/arm/mach-at91/at91sam9g45.c                                 |    6 +
 arch/arm/mach-at91/at91sam9n12.c                                 |    3 -
 arch/arm/mach-at91/at91sam9x5.c                                  |    7 -
 arch/arm/mach-at91/board-dt.c                                    |    2 -
 arch/arm/mach-at91/gpio.c                                        |  197 ++++--------------
 arch/arm/mach-at91/setup.c                                       |    6 +-
 drivers/mtd/nand/atmel_nand.c                                    |   65 +++++-
 drivers/pinctrl/Kconfig                                          |    9 +
 drivers/pinctrl/Makefile                                         |    1 +
 drivers/pinctrl/pinctrl-at91.c                                   | 1448 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/tty/serial/atmel_serial.c                                |    8 +
 36 files changed, 2654 insertions(+), 373 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/at91sam9g15.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9g15ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9g25.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9g35.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9g35ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9x25.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x25ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9x35.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x35ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9x5ek.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-at91.c

Best Regards,
J.


From jarkko.nikula at bitmer.com  Fri Aug 10 09:00:04 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Fri, 10 Aug 2012 16:00:04 +0300
Subject: [alsa-devel] [PATCH 08/11] ARM: OMAP3: Remove callback for McBSP
 sidetone ICLK workaround
In-Reply-To: <50227104.3040506@ti.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>
 <502268B1.9040506@bitmer.com> <50227104.3040506@ti.com>
Message-ID: <502505D4.2030308@bitmer.com>

Hi Peter

On 08/08/2012 05:00 PM, Peter Ujfalusi wrote:
>> Are you sure it works without any changes to sidetone audio quality or
>> current consumption? What I remember idlemode was broken at least on
>> 3430 and caused bad sidetone audio if autoidle was set and a little bit
>> higher current consumption (something like 2-3 mA higher where reference
>> consumption was around 10 mA) when McBSP was set to no-idle.
> 
> Yes, the idelmode settings are still broken in the sidetone block. However we
> are toggling the SIDLEMODE of the corresponding McBSP instance where the ST
> block is attached.
> This should have the same effect as doing the same down in PRCM level since
> the McBSP SIDLEMODE does work correctly preventing ICLK to be gated when it is
> set to no-idle.
> 
> Unfortunately I can not get my BeagleBoard to start gating iclk even if I
> remove the ICLK gating prevention (on top of 3.6-rc1). So I can not really say
> for 100% this is equivalent to the the PRCM level workaround.
> However I have also spend long time hacking around in McBSP, and I know that
> the SIDLEMODE in McBSP is working correctly.
> Do you know how can I get OMAP3 to start gating the clocks (to idle)?
> 
I got some odd current consumption results from Beagle to really compare
different kernel versions but I was able get sensible results from N900.

I tested your set on top of 196973c of sound.git.

First consumption when using threshold based transfer has remained the
same between 2.6.38-3.6.0-rc1 (wau!). Active sidetone under "arecord -f
dat >/dev/null |aplay -f dat /dev/zero" test increases consumption from
plain playback about 17 mA in 3.4 and 3.6.0-rc1.

With your set applied consumption increases 28 mA when the sidetone is
active (i.e. +11 mA higher than on top of 196973c). Plain threshold
based playback remains still the same.

> I'm doing the same test on BeagleBoard, but this thing does not want to hit
> retention despite all the effort :(
> 
Could it be display subsystem which keeps it active? At least on N900 I
need to get DSS drivers activated in order to be able to blank the
display after bootloader and thus be able to reach the retention idle.

-- 
Jarkko


From plagnioj at jcrosoft.com  Fri Aug 10 09:01:59 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:01:59 +0200
Subject: [PATCH 02/14] at91: regroup gpio and pinctrl under a simple-bus
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-2-git-send-email-plagnioj@jcrosoft.com>

Fix also the reg size as we have 512 bytes bank not 256 bytes per gpio/mux
controller

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi |   54 ++++++++++++---------
 arch/arm/boot/dts/at91sam9263.dtsi |   93 +++++++++++++++++++-----------------
 arch/arm/boot/dts/at91sam9g45.dtsi |   87 ++++++++++++++++++---------------
 arch/arm/boot/dts/at91sam9n12.dtsi |   76 ++++++++++++++++-------------
 arch/arm/boot/dts/at91sam9x5.dtsi  |   70 +++++++++++++++------------
 5 files changed, 210 insertions(+), 170 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 66389c1..4aa155d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -97,31 +97,39 @@
 				interrupts = <26 4 0 27 4 0 28 4 0>;
 			};
 
-			pioA: gpio at fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+			pinctrl at fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				reg = <0xfffff400 0x600>;
+
+				pioA: gpio at fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioB: gpio at fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioB: gpio at fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioC: gpio at fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <4 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
+				pioC: gpio at fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 			};
 
 			dbgu: serial at fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index b460d6c..f1c838e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -88,49 +88,56 @@
 				reg = <0xfffffd10 0x10>;
 			};
 
-			pioA: gpio at fffff200 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff200 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioB: gpio at fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioC: gpio at fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <4 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioD: gpio at fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <4 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioE: gpio at fffffa00 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x100>;
-				interrupts = <4 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
+			pinctrl at fffff200 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				reg = <0xfffff200 0xa00>;
+
+				pioA: gpio at fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioB: gpio at fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioC: gpio at fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioD: gpio at fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioE: gpio at fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <4 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
 			};
 
 			dbgu: serial at ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bafa880..f04bc8d 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -106,49 +106,58 @@
 				interrupts = <21 4 0>;
 			};
 
-			pioA: gpio at fffff200 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff200 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+			pinctrl at fffff200 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+
+				reg = <0xfffff200 0xa00>;
+
+				pioA: gpio at fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioB: gpio at fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioB: gpio at fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioC: gpio at fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <4 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioC: gpio at fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioD: gpio at fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <5 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioD: gpio at fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <5 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioE: gpio at fffffa00 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x100>;
-				interrupts = <5 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
+				pioE: gpio at fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <5 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 			};
 
 			dbgu: serial at ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bfac0df..575c891 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -100,40 +100,48 @@
 				interrupts = <20 4 0>;
 			};
 
-			pioA: gpio at fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioB: gpio at fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioC: gpio at fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
-
-			pioD: gpio at fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
+			pinctrl at fffff400 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				reg = <0xfffff400 0x800>;
+
+				pioA: gpio at fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioB: gpio at fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioC: gpio at fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
+
+				pioD: gpio at fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 			};
 
 			dbgu: serial at fffff200 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 4a18c39..8c314d5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -108,40 +108,48 @@
 				interrupts = <21 4 0>;
 			};
 
-			pioA: gpio at fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+			pinctrl at fffff200 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+				reg = <0xfffff400 0x800>;
+
+				pioA: gpio at fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioB: gpio at fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <2 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioB: gpio at fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <2 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioC: gpio at fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-			};
+				pioC: gpio at fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 
-			pioD: gpio at fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x100>;
-				interrupts = <3 4 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
+				pioD: gpio at fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <3 4 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+				};
 			};
 
 			dbgu: serial at fffff200 {
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:01:58 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:01:58 +0200
Subject: [PATCH 01/14] ARM: at91: gpio: implement request and free
In-Reply-To: <20120810124820.GA20557@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
Message-ID: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>

Configure a gpio as input when freeing it to reduce power consumption/
Confire the pin as pio when requested.

This is need by DT as we do not mux them any more.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/gpio.c |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..3770d72 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -46,6 +46,8 @@ struct at91_gpio_chip {
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
 
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
+static void at91_gpiolib_free(struct gpio_chip *chip, unsigned offset);
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
@@ -59,6 +61,8 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 	{								\
 		.chip = {						\
 			.label		  = name,			\
+			.request	  = at91_gpiolib_request,	\
+			.free		  = at91_gpiolib_free,		\
 			.direction_input  = at91_gpiolib_direction_input, \
 			.direction_output = at91_gpiolib_direction_output, \
 			.get		  = at91_gpiolib_get,		\
@@ -862,6 +866,21 @@ void __init at91_gpio_irq_setup(void)
 }
 
 /* gpiolib support */
+static void at91_gpiolib_free(struct gpio_chip *chip, unsigned offset)
+{
+	at91_gpiolib_direction_input(chip, offset);
+}
+
+static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+	unsigned mask = 1 << offset;
+
+	__raw_writel(mask, pio + PIO_PER);
+	return 0;
+}
+
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
 					unsigned offset)
 {
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:01 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:01 +0200
Subject: [PATCH 04/14] ARM: at91: add dummies pinctrl for non dt platform
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-4-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/setup.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb..50c69b5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -10,6 +10,7 @@
 #include <linux/mm.h>
 #include <linux/pm.h>
 #include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -463,4 +464,6 @@ void __init at91_initialize(unsigned long main_clock)
 	at91_boot_soc.register_clocks();
 
 	at91_boot_soc.init();
+
+	pinctrl_provide_dummies();
 }
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:11 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:11 +0200
Subject: [PATCH 14/14] MTD: atmel_nand: add pinctrl consumer support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-14-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: linux-mtd at lists.infradead.org
---
Hi David,

	if you don't mind I would like to apply with the rest of the pinctrl
	patch series

Best Regards,
J.
 drivers/mtd/nand/atmel_nand.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index eef9f80..3f740fd 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -39,6 +39,7 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <linux/platform_data/atmel.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <mach/cpu.h>
 
@@ -539,6 +540,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	struct resource *mem;
 	struct mtd_part_parser_data ppdata = {};
 	int res;
+	struct pinctrl *pinctrl;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
@@ -583,6 +585,13 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	nand_chip->IO_ADDR_W = host->io_base;
 	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl)) {
+		dev_err(host->dev, "Failed to request pinctrl\n");
+		res = PTR_ERR(pinctrl);
+		goto err_ecc_ioremap;
+	}
+
 	if (gpio_is_valid(host->board.rdy_pin)) {
 		res = gpio_request(host->board.rdy_pin, "nand_rdy");
 		if (res < 0) {
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:00 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:00 +0200
Subject: [PATCH 03/14] arm: at91: at91sam9x5: fix gpio number per bank
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>

On the serie 5 bank b and d have 19 and 22 pins only.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 .../devicetree/bindings/gpio/gpio_atmel.txt        |    5 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    2 ++
 arch/arm/mach-at91/gpio.c                          |   33 +++++++++++++-------
 3 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
index 66efc80..f2caa9f 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
@@ -9,6 +9,10 @@ Required properties:
   unused).
 - gpio-controller: Marks the device node as a GPIO controller.
 
+optional properties:
+- gpio-nb: Number of gpio if absent 32.
+
+
 Example:
 	pioA: gpio at fffff200 {
 		compatible = "atmel,at91rm9200-gpio";
@@ -16,5 +20,6 @@ Example:
 		interrupts = <2 4>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		gpio-nb = <19>;
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8c314d5..8b56730 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -130,6 +130,7 @@
 					interrupts = <2 4 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
+					gpio-nb = <19>;
 					interrupt-controller;
 				};
 
@@ -148,6 +149,7 @@
 					interrupts = <3 4 1>;
 					#gpio-cells = <2>;
 					gpio-controller;
+					gpio-nb = <22>;
 					interrupt-controller;
 				};
 			};
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 3770d72..8b476fd 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -33,6 +33,8 @@
 
 #include "generic.h"
 
+#define MAX_NB_GPIO_PER_BANK	32
+
 struct at91_gpio_chip {
 	struct gpio_chip	chip;
 	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
@@ -57,7 +59,7 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
 					unsigned offset);
 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 
-#define AT91_GPIO_CHIP(name, nr_gpio)					\
+#define AT91_GPIO_CHIP(name)						\
 	{								\
 		.chip = {						\
 			.label		  = name,			\
@@ -69,16 +71,16 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 			.set		  = at91_gpiolib_set,		\
 			.dbg_show	  = at91_gpiolib_dbg_show,	\
 			.to_irq		  = at91_gpiolib_to_irq,	\
-			.ngpio		  = nr_gpio,			\
+			.ngpio		  = MAX_NB_GPIO_PER_BANK,	\
 		},							\
 	}
 
 static struct at91_gpio_chip gpio_chip[] = {
-	AT91_GPIO_CHIP("pioA", 32),
-	AT91_GPIO_CHIP("pioB", 32),
-	AT91_GPIO_CHIP("pioC", 32),
-	AT91_GPIO_CHIP("pioD", 32),
-	AT91_GPIO_CHIP("pioE", 32),
+	AT91_GPIO_CHIP("pioA"),
+	AT91_GPIO_CHIP("pioB"),
+	AT91_GPIO_CHIP("pioC"),
+	AT91_GPIO_CHIP("pioD"),
+	AT91_GPIO_CHIP("pioE"),
 };
 
 static int gpio_banks;
@@ -93,7 +95,7 @@ static unsigned long at91_gpio_caps;
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
-	pin /= 32;
+	pin /= MAX_NB_GPIO_PER_BANK;
 	if (likely(pin < gpio_banks))
 		return gpio_chip[pin].regbase;
 
@@ -102,7 +104,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
 
 static inline unsigned pin_to_mask(unsigned pin)
 {
-	return 1 << (pin % 32);
+	return 1 << (pin % MAX_NB_GPIO_PER_BANK);
 }
 
 
@@ -999,6 +1001,7 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
 {
 	int alias_idx;
 	struct at91_gpio_chip *at91_gpio;
+	uint32_t ngpio;
 
 	if (!np)
 		return;
@@ -1011,7 +1014,7 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
 	}
 
 	at91_gpio = &gpio_chip[alias_idx];
-	at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
+	at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
 
 	at91_gpio->regbase = of_iomap(np, 0);
 	if (!at91_gpio->regbase) {
@@ -1031,6 +1034,14 @@ static void __init of_at91_gpio_init_one(struct device_node *np)
 	if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
 		at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
 
+	if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
+		if (ngpio >= MAX_NB_GPIO_PER_BANK)
+			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
+			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
+		else
+			at91_gpio->chip.ngpio = ngpio;
+	}
+
 	/* Setup clock */
 	if (at91_gpio_setup_clk(alias_idx))
 		goto ioremap_err;
@@ -1068,7 +1079,7 @@ static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
 {
 	struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
 
-	at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+	at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
 	at91_gpio->pioc_hwirq = pioc_hwirq;
 	at91_gpio->pioc_idx = idx;
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:09 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:09 +0200
Subject: [PATCH 12/14] MTD: atmel nand: fix gpio missing request
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-12-git-send-email-plagnioj@jcrosoft.com>

without this the gpio will not be muxed as a gpio by the current custom pinmux
or later by the pinctrl

Cc: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/mtd/nand/atmel_nand.c |   56 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 97ac671..eef9f80 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -583,8 +583,39 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	nand_chip->IO_ADDR_W = host->io_base;
 	nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 
-	if (gpio_is_valid(host->board.rdy_pin))
+	if (gpio_is_valid(host->board.rdy_pin)) {
+		res = gpio_request(host->board.rdy_pin, "nand_rdy");
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request rdy gpio %d\n", host->board.rdy_pin);
+			goto err_ecc_ioremap;
+		}
+
+		res = gpio_direction_input(host->board.rdy_pin);
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request input direction rdy gpio %d\n", host->board.rdy_pin);
+			goto err_ecc_ioremap;
+		}
+
 		nand_chip->dev_ready = atmel_nand_device_ready;
+	}
+
+	if (gpio_is_valid(host->board.enable_pin)) {
+		res = gpio_request(host->board.enable_pin, "nand_enable");
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request enable gpio %d\n", host->board.enable_pin);
+			goto err_ecc_ioremap;
+		}
+
+		res = gpio_direction_output(host->board.enable_pin, 1);
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request output direction enable gpio %d\n", host->board.enable_pin);
+			goto err_ecc_ioremap;
+		}
+	}
 
 	nand_chip->ecc.mode = host->board.ecc_mode;
 
@@ -622,6 +653,20 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	atmel_nand_enable(host);
 
 	if (gpio_is_valid(host->board.det_pin)) {
+		res = gpio_request(host->board.det_pin, "nand_det");
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request det gpio %d\n", host->board.det_pin);
+			goto err_no_card;
+		}
+
+		res = gpio_direction_input(host->board.det_pin);
+		if (res < 0) {
+			dev_err(&pdev->dev,
+				"can't request input direction det gpio %d\n", host->board.det_pin);
+			goto err_no_card;
+		}
+
 		if (gpio_get_value(host->board.det_pin)) {
 			printk(KERN_INFO "No SmartMedia card inserted.\n");
 			res = -ENXIO;
@@ -738,6 +783,15 @@ static int __exit atmel_nand_remove(struct platform_device *pdev)
 
 	atmel_nand_disable(host);
 
+	if (gpio_is_valid(host->board.det_pin))
+		gpio_free(host->board.det_pin);
+
+	if (gpio_is_valid(host->board.enable_pin))
+		gpio_free(host->board.enable_pin);
+
+	if (gpio_is_valid(host->board.rdy_pin))
+		gpio_free(host->board.rdy_pin);
+
 	if (host->ecc)
 		iounmap(host->ecc);
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:10 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:10 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |   10 ++++++++++
 5 files changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 8ee7cd3..a4f4cba 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -208,6 +208,14 @@
 					};
 				};
 
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<2 13 0x0 0x1	/* PC13 gpio RDY pin pull_up */
+							 2 14 0x0 0x1>;	/* PC14 gpio enable pin pull_up */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -370,6 +378,8 @@
 			      >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 			gpios = <&pioC 13 0
 				 &pioC 14 0
 				 0
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 2d054c2..9314c32 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -155,6 +155,14 @@
 					};
 				};
 
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<0 22 0x0 0x1	/* PA22 gpio RDY pin pull_up*/
+							 3 15 0x0 0x1>;	/* PD15 gpio enable pin pull_up */
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
@@ -267,6 +275,8 @@
 			      >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 			gpios = <&pioA 22 0
 				 &pioD 15 0
 				 0
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index cfe197a..8863fd9 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -188,6 +188,14 @@
 					};
 				};
 
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<2 8 0x0 0x1	/* PC8 gpio RDY pin pull_up*/
+							 2 14 0x0 0x1>;	/* PC14 gpio enable pin pull_up */
+					};
+				};
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
@@ -341,6 +349,8 @@
 			      >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 			gpios = <&pioC 8 0
 				 &pioC 14 0
 				 0
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 36a6ce0..d1f5655 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -190,6 +190,14 @@
 					};
 				};
 
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<3 5 0x0 0x1	/* PD5 gpio RDY pin pull_up*/
+							 3 4 0x0 0x1>;	/* PD4 gpio enable pin pull_up */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -292,6 +300,8 @@
 			       >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 			gpios = <&pioD 5 0
 				 &pioD 4 0
 				 0
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c585f04..e58965d6 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -204,6 +204,14 @@
 					};
 				};
 
+				nand {
+					pinctrl_nand: nand-0 {
+						atmel,pins =
+							<3 4 0x0 0x1	/* PD5 gpio RDY pin pull_up */
+							 3 5 0x0 0x1>;	/* PD4 gpio enable pin pull_up */
+					};
+				};
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -346,6 +354,8 @@
 			      >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_nand>;
 			gpios = <&pioD 5 0
 				 &pioD 4 0
 				 0
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:07 +0200
Subject: [PATCH 10/14] arm: at91: dt: sam9263ek: use rts/cts pinctrl group for
 uart0
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-10-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9263ek.dts |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b..7cfe9d5 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -38,6 +38,7 @@
 			};
 
 			usart0: serial at fff8c000 {
+				pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart0_rts_cts>;
 				status = "okay";
 			};
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:08 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:08 +0200
Subject: [PATCH 11/14] arm: at91: dt: sam9g20ek: use rts/cts/dtr/dsr/dcd/ri
 pinctrl group for uart0
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-11-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index b06c0db..e33ab0a 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -35,6 +35,12 @@
 			};
 
 			usart0: serial at fffb0000 {
+				pinctrl-0 =
+					<&pinctrl_uart0
+					 &pinctrl_uart0_rts_cts
+					 &pinctrl_uart0_dtr_dsr
+					 &pinctrl_uart0_dcd
+					 &pinctrl_uart0_ri>;
 				status = "okay";
 			};
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:05 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:05 +0200
Subject: [PATCH 08/14] tty: atmel_serial: add pinctrl support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-8-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: linux-serial at vger.kernel.org
---
Hi Greg,

	if you don't mind I would like to apply with the rest of the pinctrl
	patch series

Best Regards,
J.
 drivers/tty/serial/atmel_serial.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee..65f891b 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -39,6 +39,7 @@
 #include <linux/atmel_pdc.h>
 #include <linux/atmel_serial.h>
 #include <linux/uaccess.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/io.h>
 #include <asm/ioctls.h>
@@ -1773,6 +1774,7 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
 	struct atmel_uart_data *pdata = pdev->dev.platform_data;
 	void *data;
 	int ret = -ENODEV;
+	struct pinctrl *pinctrl;
 
 	BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
 
@@ -1805,6 +1807,12 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
 
 	atmel_init_port(port, pdev);
 
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl)) {
+		ret = PTR_ERR(pinctrl);
+		goto err;
+	}
+
 	if (!atmel_use_dma_rx(&port->uart)) {
 		ret = -ENOMEM;
 		data = kmalloc(sizeof(struct atmel_uart_char)
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:06 +0200
Subject: [PATCH 09/14] arm: at91: dt: sam9m10g45ek: use rts/cts pinctrl group
 for uart1
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-9-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd..16a13cd 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -39,6 +39,7 @@
 			};
 
 			usart1: serial at fff90000 {
+				pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart1_rts_cts>;
 				status = "okay";
 			};
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:03 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:03 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi |    9 +++++++++
 arch/arm/boot/dts/at91sam9263.dtsi |   12 ++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |   11 +++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |   10 ++++++++++
 arch/arm/configs/at91_dt_defconfig |    1 +
 arch/arm/mach-at91/at91sam9263.c   |    5 +++++
 arch/arm/mach-at91/at91sam9g45.c   |    6 ++++++
 arch/arm/mach-at91/at91sam9n12.c   |    3 ---
 arch/arm/mach-at91/at91sam9x5.c    |    7 -------
 arch/arm/mach-at91/setup.c         |    3 ++-
 11 files changed, 66 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 4aa155d..353eb53 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -104,6 +104,15 @@
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				reg = <0xfffff400 0x600>;
 
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xffffffff 0xffc00c3b  /* pioA */
+				       0xffffffff 0x7fff3ccf  /* pioB */
+				       0xffffffff 0x007fffff  /* pioC */
+				      >;
+
+				/* shared pinctrl settings */
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index f1c838e..e52d5f8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -95,6 +95,17 @@
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				reg = <0xfffff200 0xa00>;
 
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xfffffffb 0xffffe07f  /* pioA */
+				       0x0007ffff 0x39072fff  /* pioB */
+				       0xffffffff 0x3ffffff8  /* pioC */
+				       0xfffffbff 0xffffffff  /* pioD */
+				       0xffe00fff 0xfbfcff00  /* pioE */
+				      >;
+
+				/* shared pinctrl settings */
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
@@ -138,6 +149,7 @@
 					#gpio-cells = <2>;
 					gpio-controller;
 					interrupt-controller;
+				};
 			};
 
 			dbgu: serial at ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index f04bc8d..0e64221 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -114,6 +114,17 @@
 
 				reg = <0xfffff200 0xa00>;
 
+				atmel,mux-mask = <
+				      /*    A         B     */
+				       0xffffffff 0xffc003ff  /* pioA */
+				       0xffffffff 0x800f8f00  /* pioB */
+				       0xffffffff 0x00000e00  /* pioC */
+				       0xffffffff 0xff0c1381  /* pioD */
+				       0xffffffff 0x81ffff81  /* pioE */
+				      >;
+
+				/* shared pinctrl settings */
+
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 575c891..ae23a03 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -107,6 +107,16 @@
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				reg = <0xfffff400 0x800>;
 
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe07983 0x00000000  /* pioA */
+				       0x00040000 0x00047e0f 0x00000000  /* pioB */
+				       0xfdffffff 0x07c00000 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+
+				/* shared pinctrl settings */
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8b56730..d1df4ea 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -115,6 +115,16 @@
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				reg = <0xfffff400 0x800>;
 
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe0399f 0xc000001c  /* pioA */
+				       0xffffffff 0xffc003ff 0xffc003ff  /* pioB */
+				       0xffffffff 0xffc003ff 0xffc003ff  /* pioC */
+				       0xffffffff 0xffc003ff 0xffc003ff  /* pioD */
+				      >;
+
+				/* shared pinctrl settings */
+
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 67bc571..b175577 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -111,6 +111,7 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b3810..ceef453 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -210,6 +210,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd..8322aa7 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -256,6 +256,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
+
 	CLKDEV_CON_ID("pioA", &pioA_clk),
 	CLKDEV_CON_ID("pioB", &pioB_clk),
 	CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..f4e0e60 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -221,9 +221,6 @@ static void __init at91sam9n12_map_io(void)
 void __init at91sam9n12_initialize(void)
 {
 	at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
-
-	/* Register GPIO subsystem (using DT) */
-	at91_gpio_init(NULL, 0);
 }
 
 struct at91_init_soc __initdata at91sam9n12_soc = {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..bbd2f8e 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -310,12 +310,6 @@ static void __init at91sam9x5_map_io(void)
 	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }
 
-void __init at91sam9x5_initialize(void)
-{
-	/* Register GPIO subsystem (using DT) */
-	at91_gpio_init(NULL, 0);
-}
-
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -323,5 +317,4 @@ void __init at91sam9x5_initialize(void)
 struct at91_init_soc __initdata at91sam9x5_soc = {
 	.map_io = at91sam9x5_map_io,
 	.register_clocks = at91sam9x5_register_clocks,
-	.init = at91sam9x5_initialize,
 };
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 50c69b5..fcb66ea 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -449,7 +449,8 @@ void __init at91_dt_initialize(void)
 	/* Register the processor-specific clocks */
 	at91_boot_soc.register_clocks();
 
-	at91_boot_soc.init();
+	if (at91_boot_soc.init)
+		at91_boot_soc.init();
 }
 #endif
 
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:04 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:04 +0200
Subject: [PATCH 07/14] arm: at91: dt: at91sam9 add serial pinctrl support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-7-git-send-email-plagnioj@jcrosoft.com>

Set the dbgu pinctrl config by default as we have only one possible config
For other uart set the rxd/txd by default.

For at91sam9x5ek create soc based dts as we need to include specific soc dtsi.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi                 |  109 ++++++++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi                 |   57 ++++++++++
 arch/arm/boot/dts/at91sam9g15.dtsi                 |   28 +++++
 arch/arm/boot/dts/at91sam9g15ek.dts                |   16 +++
 arch/arm/boot/dts/at91sam9g25.dtsi                 |   28 +++++
 arch/arm/boot/dts/at91sam9g25ek.dts                |   65 +++---------
 arch/arm/boot/dts/at91sam9g35.dtsi                 |   28 +++++
 arch/arm/boot/dts/at91sam9g35ek.dts                |   16 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   73 +++++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi                 |   83 +++++++++++++++
 arch/arm/boot/dts/at91sam9x25.dtsi                 |   28 +++++
 arch/arm/boot/dts/at91sam9x25ek.dts                |   16 +++
 arch/arm/boot/dts/at91sam9x35.dtsi                 |   28 +++++
 arch/arm/boot/dts/at91sam9x35ek.dts                |   16 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   93 ++++++++++++++++-
 .../dts/{at91sam9g25ek.dts => at91sam9x5ek.dtsi}   |    8 +-
 arch/arm/mach-at91/Makefile.boot                   |    4 +
 17 files changed, 639 insertions(+), 57 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9g15.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9g15ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9g25.dtsi
 rewrite arch/arm/boot/dts/at91sam9g25ek.dts (62%)
 create mode 100644 arch/arm/boot/dts/at91sam9g35.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9g35ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9x25.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x25ek.dts
 create mode 100644 arch/arm/boot/dts/at91sam9x35.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x35ek.dts
 rename arch/arm/boot/dts/{at91sam9g25ek.dts => at91sam9x5ek.dtsi} (75%)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 353eb53..8ee7cd3 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -112,6 +112,101 @@
 				      >;
 
 				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<1 14 0x1 0x0	/* PB14 periph A */
+							 1 15 0x1 0x1>;	/* PB15 periph with pullup */
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<1 4 0x1 0x0	/* PB4 periph A */
+							 1 5 0x1 0x0>;	/* PB5 periph A */
+					};
+
+					pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+						atmel,pins =
+							<1 26 0x1 0x0	/* PB26 periph A */
+							 1 27 0x1 0x0>;	/* PB27 periph A */
+					};
+
+					pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
+						atmel,pins =
+							<1 24 0x1 0x0	/* PB24 periph A */
+							 1 22 0x1 0x0>;	/* PB22 periph A */
+					};
+
+					pinctrl_uart0_dcd: uart0_dcd-0 {
+						atmel,pins =
+							<1 23 0x1 0x0>;	/* PB23 periph A */
+					};
+
+					pinctrl_uart0_ri: uart0_ri-0 {
+						atmel,pins =
+							<1 25 0x1 0x0>;	/* PB25 periph A */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<2 6 0x1 0x1	/* PB6 periph A with pullup */
+							 2 7 0x1 0x0>;	/* PB7 periph A */
+					};
+
+					pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
+						atmel,pins =
+							<1 28 0x1 0x0	/* PB28 periph A */
+							 1 29 0x1 0x0>;	/* PB29 periph A */
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2: uart2-0 {
+						atmel,pins =
+							<1 8 0x1 0x1	/* PB8 periph A with pullup */
+							 1 9 0x1 0x0>;	/* PB9 periph A */
+					};
+
+					pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+						atmel,pins =
+							<0 4 0x1 0x0	/* PA4 periph A */
+							 0 5 0x1 0x0>;	/* PA5 periph A */
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3: uart3-0 {
+						atmel,pins =
+							<2 10 0x1 0x1	/* PB10 periph A with pullup */
+							 2 11 0x1 0x0>;	/* PB11 periph A */
+					};
+
+					pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
+						atmel,pins =
+							<3 8 0x2 0x0	/* PB8 periph B */
+							 3 10 0x2 0x0>;	/* PB10 periph B */
+					};
+				};
+
+				uart4 {
+					pinctrl_uart4: uart4-0 {
+						atmel,pins =
+							<0 31 0x2 0x1	/* PA31 periph B with pullup */
+							 0 30 0x2 0x0>;	/* PA30 periph B */
+					};
+				};
+
+				uart5 {
+					pinctrl_uart5: uart5-0 {
+						atmel,pins =
+							<2 12 0x1 0x1	/* PB12 periph A with pullup */
+							 2 13 0x1 0x0>;	/* PB13 periph A */
+					};
+				};
 
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
@@ -145,6 +240,8 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
 				interrupts = <1 4 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
 			};
 
@@ -154,6 +251,8 @@
 				interrupts = <6 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
 				status = "disabled";
 			};
 
@@ -163,6 +262,8 @@
 				interrupts = <7 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
 				status = "disabled";
 			};
 
@@ -172,6 +273,8 @@
 				interrupts = <8 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2>;
 				status = "disabled";
 			};
 
@@ -181,6 +284,8 @@
 				interrupts = <23 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart3>;
 				status = "disabled";
 			};
 
@@ -190,6 +295,8 @@
 				interrupts = <24 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart4>;
 				status = "disabled";
 			};
 
@@ -199,6 +306,8 @@
 				interrupts = <25 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart5>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index e52d5f8..2d054c2 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -105,6 +105,55 @@
 				      >;
 
 				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<2 30 0x1 0x0	/* PC30 periph A */
+							 2 31 0x1 0x1>;	/* PC31 periph with pullup */
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<0 26 0x1 0x1	/* PA26 periph A with pullup */
+							 0 27 0x1 0x0>;	/* PA27 periph A */
+					};
+
+					pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+						atmel,pins =
+							<0 28 0x1 0x0	/* PA28 periph A */
+							 0 29 0x1 0x0>;	/* PA29 periph A */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<3 0 0x1 0x1	/* PD0 periph A with pullup */
+							 3 1 0x1 0x0>;	/* PD1 periph A */
+					};
+
+					pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
+						atmel,pins =
+							<3 7 0x2 0x0	/* PD7 periph B */
+							 3 8 0x2 0x0>;	/* PD8 periph B */
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2: uart2-0 {
+						atmel,pins =
+							<3 2 0x1 0x1	/* PD2 periph A with pullup */
+							 3 3 0x1 0x0>;	/* PD3 periph A */
+					};
+
+					pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+						atmel,pins =
+							<3 5 0x2 0x0	/* PD5 periph B */
+							 4 6 0x2 0x0>;	/* PD6 periph B */
+					};
+				};
 
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
@@ -156,6 +205,8 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
 				interrupts = <1 4 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
 			};
 
@@ -165,6 +216,8 @@
 				interrupts = <7 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
 				status = "disabled";
 			};
 
@@ -174,6 +227,8 @@
 				interrupts = <8 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
 				status = "disabled";
 			};
 
@@ -183,6 +238,8 @@
 				interrupts = <9 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
new file mode 100644
index 0000000..b0a86ab
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G15 SoC";
+	compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+
+	ahb {
+		apb {
+			pinctrl at fffff200 {
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe0399f 0x00000000  /* pioA */
+				       0x00040000 0x00047e3f 0x00000000  /* pioB */
+				       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
new file mode 100644
index 0000000..86dd3f6
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g15.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G25-EK";
+	compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
new file mode 100644
index 0000000..5886ac2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G25 SoC";
+	compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+
+	ahb {
+		apb {
+			pinctrl at fffff200 {
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe0399f 0xc000001c  /* pioA */
+				       0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
+				       0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
dissimilarity index 62%
index 7829a4d..c5ab16f 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -1,49 +1,16 @@
-/*
- * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
- *
- *  Copyright (C) 2012 Atmel,
- *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
- *
- * Licensed under GPLv2 or later.
- */
-/dts-v1/;
-/include/ "at91sam9x5.dtsi"
-/include/ "at91sam9x5cm.dtsi"
-
-/ {
-	model = "Atmel AT91SAM9G25-EK";
-	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
-
-	chosen {
-		bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
-	};
-
-	ahb {
-		apb {
-			dbgu: serial at fffff200 {
-				status = "okay";
-			};
-
-			usart0: serial at f801c000 {
-				status = "okay";
-			};
-
-			macb0: ethernet at f802c000 {
-				phy-mode = "rmii";
-				status = "okay";
-			};
-		};
-
-		usb0: ohci at 00600000 {
-			status = "okay";
-			num-ports = <2>;
-			atmel,vbus-gpio = <&pioD 19 1
-					   &pioD 20 1
-					  >;
-		};
-
-		usb1: ehci at 00700000 {
-			status = "okay";
-		};
-	};
-};
+/*
+ * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g25.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G25-EK";
+	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
new file mode 100644
index 0000000..9cc9446
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9rG5 SoC";
+	compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+
+	ahb {
+		apb {
+			pinctrl at fffff200 {
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe0399f 0xc000000c  /* pioA */
+				       0x000406ff 0x00047e3f 0x00000000  /* pioB */
+				       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
new file mode 100644
index 0000000..95944bd
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G35-EK";
+	compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 0e64221..cfe197a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -124,6 +124,69 @@
 				      >;
 
 				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<1 12 0x1 0x0	/* PB12 periph A */
+							 1 13 0x1 0x0>;	/* PB13 periph A */
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<1 19 0x1 0x1	/* PB19 periph A with pullup */
+							 1 18 0x1 0x0>;	/* PB18 periph A */
+					};
+
+					pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+						atmel,pins =
+							<1 17 0x2 0x0	/* PB17 periph B */
+							 1 15 0x2 0x0>;	/* PB15 periph B */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<1 4 0x1 0x1	/* PB4 periph A with pullup */
+							 1 5 0x1 0x0>;	/* PB5 periph A */
+					};
+
+					pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
+						atmel,pins =
+							<3 16 0x1 0x0	/* PD16 periph A */
+							 3 17 0x1 0x0>;	/* PD17 periph A */
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2: uart2-0 {
+						atmel,pins =
+							<1 6 0x1 0x1	/* PB6 periph A with pullup */
+							 1 7 0x1 0x0>;	/* PB7 periph A */
+					};
+
+					pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+						atmel,pins =
+							<2 9 0x2 0x0	/* PC9 periph B */
+							 2 11 0x2 0x0>;	/* PC11 periph B */
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3: uart3-0 {
+						atmel,pins =
+							<1 8 0x1 0x1	/* PB9 periph A with pullup */
+							 1 9 0x1 0x0>;	/* PB8 periph A */
+					};
+
+					pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
+						atmel,pins =
+							<0 23 0x2 0x0	/* PA23 periph B */
+							 0 24 0x2 0x0>;	/* PA24 periph B */
+					};
+				};
 
 				pioA: gpio at fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
@@ -175,6 +238,8 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xffffee00 0x200>;
 				interrupts = <1 4 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
 			};
 
@@ -184,6 +249,8 @@
 				interrupts = <7 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
 				status = "disabled";
 			};
 
@@ -193,6 +260,8 @@
 				interrupts = <8 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
 				status = "disabled";
 			};
 
@@ -202,6 +271,8 @@
 				interrupts = <9 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2>;
 				status = "disabled";
 			};
 
@@ -211,6 +282,8 @@
 				interrupts = <10 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart3>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ae23a03..36a6ce0 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -116,6 +116,79 @@
 				      >;
 
 				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<0 9 0x1 0x0	/* PA9 periph A */
+							 0 10 0x1 0x1>;	/* PA10 periph with pullup */
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<0 1 0x1 0x1	/* PA1 periph A with pullup */
+							 0 0 0x1 0x0>;	/* PA0 periph A */
+					};
+
+					pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+						atmel,pins =
+							<0 2 0x1 0x0	/* PA2 periph A */
+							 0 3 0x1 0x0>;	/* PA3 periph A */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<0 6 0x1 0x1	/* PA6 periph A with pullup */
+							 0 5 0x1 0x0>;	/* PA5 periph A */
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2: uart2-0 {
+						atmel,pins =
+							<0 8 0x1 0x1	/* PA8 periph A with pullup */
+							 0 7 0x1 0x0>;	/* PA7 periph A */
+					};
+
+					pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+						atmel,pins =
+							<1 0 0x2 0x0	/* PB0 periph B */
+							 1 1 0x2 0x0>;	/* PB1 periph B */
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3: uart3-0 {
+						atmel,pins =
+							<2 23 0x2 0x1	/* PC23 periph B with pullup */
+							 2 22 0x2 0x0>;	/* PC22 periph B */
+					};
+
+					pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
+						atmel,pins =
+							<2 24 0x2 0x0	/* PC24 periph B */
+							 2 25 0x2 0x0>;	/* PC25 periph B */
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<2 9 0x3 0x1	/* PC9 periph C with pullup */
+							 2 8 0x3 0x0>;	/* PC8 periph C */
+					};
+				};
+
+				usart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<2 16 0x3 0x1	/* PC17 periph C with pullup */
+							 2 17 0x3 0x0>;	/* PC16 periph C */
+					};
+				};
 
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
@@ -158,6 +231,8 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
 				interrupts = <1 4 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
 			};
 
@@ -167,6 +242,8 @@
 				interrupts = <5 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
 				status = "disabled";
 			};
 
@@ -176,6 +253,8 @@
 				interrupts = <6 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
 				status = "disabled";
 			};
 
@@ -185,6 +264,8 @@
 				interrupts = <7 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2>;
 				status = "disabled";
 			};
 
@@ -194,6 +275,8 @@
 				interrupts = <8 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart3>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
new file mode 100644
index 0000000..d03d734
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9X25 SoC";
+	compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+
+	ahb {
+		apb {
+			pinctrl at fffff200 {
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe03fff 0xc000001c  /* pioA */
+				       0x0007ffff 0x00047e3f 0x00000000  /* pioB */
+				       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
new file mode 100644
index 0000000..af907ea
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x25.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9G25-EK";
+	compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
new file mode 100644
index 0000000..139e67e
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -0,0 +1,28 @@
+/*
+ * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+/include/ "at91sam9x5.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9X35 SoC";
+	compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+
+	ahb {
+		apb {
+			pinctrl at fffff200 {
+				atmel,mux-mask = <
+				      /*    A         B          C     */
+				       0xffffffff 0xffe03fff 0xc000000c  /* pioA */
+				       0x000406ff 0x00047e3f 0x00000000  /* pioB */
+				       0xfdffffff 0x00000000 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
+				      >;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
new file mode 100644
index 0000000..5ccb607
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -0,0 +1,16 @@
+/*
+ * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x35.dtsi"
+/include/ "at91sam9x5ek.dtsi"
+
+/ {
+	model = "Atmel AT91SAM9X35-EK";
+	compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index d1df4ea..c585f04 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -118,12 +118,91 @@
 				atmel,mux-mask = <
 				      /*    A         B          C     */
 				       0xffffffff 0xffe0399f 0xc000001c  /* pioA */
-				       0xffffffff 0xffc003ff 0xffc003ff  /* pioB */
-				       0xffffffff 0xffc003ff 0xffc003ff  /* pioC */
-				       0xffffffff 0xffc003ff 0xffc003ff  /* pioD */
+				       0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
+				       0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
+				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 
 				/* shared pinctrl settings */
+				dbgu {
+					pinctrl_dbgu: dbgu-0 {
+						atmel,pins =
+							<0 9 0x1 0x0	/* PA9 periph A */
+							 0 10 0x1 0x1>;	/* PA10 periph A with pullup */
+					};
+				};
+
+				uart0 {
+					pinctrl_uart0: uart0-0 {
+						atmel,pins =
+							<0 0 0x1 0x1	/* PA0 periph A with pullup */
+							 0 1 0x1 0x0>;	/* PA1 periph A */
+					};
+
+					pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+						atmel,pins =
+							<0 2 0x1 0x0	/* PA2 periph A */
+							 0 3 0x1 0x0>;	/* PA3 periph A */
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1: uart1-0 {
+						atmel,pins =
+							<0 5 0x1 0x1	/* PA5 periph A with pullup */
+							 0 6 0x1 0x0>;	/* PA6 periph A */
+					};
+
+					pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
+						atmel,pins =
+							<3 27 0x3 0x0	/* PC27 periph C */
+							 3 28 0x3 0x0>;	/* PC28 periph C */
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2: uart2-0 {
+						atmel,pins =
+							<0 7 0x1 0x1	/* PA7 periph A with pullup */
+							 0 8 0x1 0x0>;	/* PA8 periph A */
+					};
+
+					pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+						atmel,pins =
+							<0 0 0x2 0x0	/* PB0 periph B */
+							 0 1 0x2 0x0>;	/* PB1 periph B */
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3: uart3-0 {
+						atmel,pins =
+							<3 23 0x2 0x1	/* PC22 periph B with pullup */
+							 3 23 0x2 0x0>;	/* PC23 periph B */
+					};
+
+					pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
+						atmel,pins =
+							<3 24 0x2 0x0	/* PC24 periph B */
+							 3 25 0x2 0x0>;	/* PC25 periph B */
+					};
+				};
+
+				usart0 {
+					pinctrl_usart0: usart0-0 {
+						atmel,pins =
+							<3 8 0x3 0x0	/* PC8 periph C */
+							 3 9 0x3 0x1>;	/* PC9 periph C with pullup */
+					};
+				};
+
+				usart1 {
+					pinctrl_usart1: usart1-0 {
+						atmel,pins =
+							<3 16 0x3 0x0	/* PC16 periph C */
+							 3 17 0x3 0x1>;	/* PC17 periph C with pullup */
+					};
+				};
 
 				pioA: gpio at fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
@@ -168,6 +247,8 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
 				interrupts = <1 4 7>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_dbgu>;
 				status = "disabled";
 			};
 
@@ -177,6 +258,8 @@
 				interrupts = <5 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart0>;
 				status = "disabled";
 			};
 
@@ -186,6 +269,8 @@
 				interrupts = <6 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1>;
 				status = "disabled";
 			};
 
@@ -195,6 +280,8 @@
 				interrupts = <7 4 5>;
 				atmel,use-dma-rx;
 				atmel,use-dma-tx;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9x5ek.dtsi
similarity index 75%
rename from arch/arm/boot/dts/at91sam9g25ek.dts
rename to arch/arm/boot/dts/at91sam9x5ek.dtsi
index 7829a4d..e5000a7 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -1,18 +1,16 @@
 /*
- * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
+ * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
  *
  *  Copyright (C) 2012 Atmel,
  *                2012 Nicolas Ferre <nicolas.ferre at atmel.com>
  *
  * Licensed under GPLv2 or later.
  */
-/dts-v1/;
-/include/ "at91sam9x5.dtsi"
 /include/ "at91sam9x5cm.dtsi"
 
 / {
-	model = "Atmel AT91SAM9G25-EK";
-	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+	model = "Atmel AT91SAM9X5-EK";
+	compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
 	chosen {
 		bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 30bb733..0838d30 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -35,4 +35,8 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
 # sam9n12
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
 # sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g15ek.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g35ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9x25ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9x35ek.dtb
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Fri Aug 10 09:02:02 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 10 Aug 2012 15:02:02 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>

This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.

This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 .../bindings/pinctrl/atmel,at91-pinctrl.txt        |   84 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/mach-at91/board-dt.c                      |    2 -
 arch/arm/mach-at91/gpio.c                          |  165 +--
 drivers/pinctrl/Kconfig                            |    9 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-at91.c                     | 1448 ++++++++++++++++++++
 7 files changed, 1548 insertions(+), 162 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-at91.c

diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
new file mode 100644
index 0000000..0296ef4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -0,0 +1,84 @@
+* Atmel AT91 Pinmux Controller
+
+The AT91 Pinmux Controler, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called periph modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the contoller controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Atmel AT91 pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'pins' selects the function mode(also named pin
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, multi drive, etc.
+
+Required properties for iomux controller:
+- compatible: "atmel,at91rm9200-pinctrl"
+- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
+  configured in this periph mode. All the periph and bank need to be describe.
+
+Required properties for pin configuration node:
+- atmel,pins: 4 integers array, represents a group of pins mux and config
+  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
+  The PERIPH 0 means gpio.
+
+Bits used for CONFIG:
+PULL_UP(1 << 0): indicate this pin need a pull up.
+MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.
+
+NOTE:
+Some requirements for using atmel,at91rm9200-pinctrl binding:
+1. We have pin function node defined under at91 controller node to represent
+   what pinmux functions this SoC supports.
+2. The pin configuration node intends to work on a specific function should
+   to be defined under that specific function node.
+   The function node's name should represent well about what function
+   this group of pins in this pin configuration node are working on.
+3. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux Iat91 pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+4. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+5. The gpio controller must be describe in the pinctrl simple-bus.
+
+Examples:
+
+pinctrl at fffff400 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+	reg = <0xfffff400 0x600>;
+
+	atmel,mux-mask = <
+	      /*    A         B     */
+	       0xffffffff 0xffc00c3b  /* pioA */
+	       0xffffffff 0x7fff3ccf  /* pioB */
+	       0xffffffff 0x007fffff  /* pioC */
+	      >;
+
+	/* shared pinctrl settings */
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins =
+				<1 14 0x1 0x0	/* PB14 periph A */
+				 1 15 0x1 0x1>;	/* PB15 periph with pullup */
+		};
+	};
+};
+
+dbgu: serial at fffff200 {
+	compatible = "atmel,at91sam9260-usart";
+	reg = <0xfffff200 0x200>;
+	interrupts = <1 4 7>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "disabled";
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..178a619 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -352,6 +352,7 @@ config ARCH_AT91
 	select CLKDEV_LOOKUP
 	select IRQ_DOMAIN
 	select NEED_MACH_IO_H if PCCARD
+	select PINCTRL
 	help
 	  This enables support for systems based on Atmel
 	  AT91RM9200 and AT91SAM9* processors.
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4..3b6a948 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -30,8 +30,6 @@
 static const struct of_device_id irq_of_match[] __initconst = {
 
 	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
-	{ .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
-	{ .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
 	{ /*sentinel*/ }
 };
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 8b476fd..67d7fab 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -23,8 +23,6 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
 
 #include <asm/mach/irq.h>
 
@@ -719,80 +717,6 @@ postcore_initcall(at91_gpio_debugfs_init);
  */
 static struct lock_class_key gpio_lock_class;
 
-#if defined(CONFIG_OF)
-static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-							irq_hw_number_t hw)
-{
-	struct at91_gpio_chip	*at91_gpio = h->host_data;
-
-	irq_set_lockdep_class(virq, &gpio_lock_class);
-
-	/*
-	 * Can use the "simple" and not "edge" handler since it's
-	 * shorter, and the AIC handles interrupts sanely.
-	 */
-	irq_set_chip_and_handler(virq, &gpio_irqchip,
-				 handle_simple_irq);
-	set_irq_flags(virq, IRQF_VALID);
-	irq_set_chip_data(virq, at91_gpio);
-
-	return 0;
-}
-
-static struct irq_domain_ops at91_gpio_ops = {
-	.map	= at91_gpio_irq_map,
-	.xlate	= irq_domain_xlate_twocell,
-};
-
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-				     struct device_node *parent)
-{
-	struct at91_gpio_chip	*prev = NULL;
-	int			alias_idx = of_alias_get_id(node, "gpio");
-	struct at91_gpio_chip	*at91_gpio = &gpio_chip[alias_idx];
-
-	/* Setup proper .irq_set_type function */
-	if (has_pio3())
-		gpio_irqchip.irq_set_type = alt_gpio_irq_type;
-	else
-		gpio_irqchip.irq_set_type = gpio_irq_type;
-
-	/* Disable irqs of this PIO controller */
-	__raw_writel(~0, at91_gpio->regbase + PIO_IDR);
-
-	/* Setup irq domain */
-	at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
-						&at91_gpio_ops, at91_gpio);
-	if (!at91_gpio->domain)
-		panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
-			at91_gpio->pioc_idx);
-
-	/* Setup chained handler */
-	if (at91_gpio->pioc_idx)
-		prev = &gpio_chip[at91_gpio->pioc_idx - 1];
-
-	/* The toplevel handler handles one bank of GPIOs, except
-	 * on some SoC it can handles up to three...
-	 * We only set up the handler for the first of the list.
-	 */
-	if (prev && prev->next == at91_gpio)
-		return 0;
-
-	at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
-							at91_gpio->pioc_hwirq);
-	irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
-	irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
-
-	return 0;
-}
-#else
-int __init at91_gpio_of_irq_setup(struct device_node *node,
-				     struct device_node *parent)
-{
-	return -EINVAL;
-}
-#endif
-
 /*
  * irqdomain initialization: pile up irqdomains on top of AIC range
  */
@@ -996,85 +920,6 @@ err:
 	return -EINVAL;
 }
 
-#ifdef CONFIG_OF_GPIO
-static void __init of_at91_gpio_init_one(struct device_node *np)
-{
-	int alias_idx;
-	struct at91_gpio_chip *at91_gpio;
-	uint32_t ngpio;
-
-	if (!np)
-		return;
-
-	alias_idx = of_alias_get_id(np, "gpio");
-	if (alias_idx >= MAX_GPIO_BANKS) {
-		pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
-						alias_idx, MAX_GPIO_BANKS);
-		return;
-	}
-
-	at91_gpio = &gpio_chip[alias_idx];
-	at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
-
-	at91_gpio->regbase = of_iomap(np, 0);
-	if (!at91_gpio->regbase) {
-		pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
-								alias_idx);
-		return;
-	}
-
-	/* Get the interrupts property */
-	if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
-		pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
-								alias_idx);
-		goto ioremap_err;
-	}
-
-	/* Get capabilities from compatibility property */
-	if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
-		at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
-
-	if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
-		if (ngpio >= MAX_NB_GPIO_PER_BANK)
-			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
-			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
-		else
-			at91_gpio->chip.ngpio = ngpio;
-	}
-
-	/* Setup clock */
-	if (at91_gpio_setup_clk(alias_idx))
-		goto ioremap_err;
-
-	at91_gpio->chip.of_node = np;
-	gpio_banks = max(gpio_banks, alias_idx + 1);
-	at91_gpio->pioc_idx = alias_idx;
-	return;
-
-ioremap_err:
-	iounmap(at91_gpio->regbase);
-}
-
-static int __init of_at91_gpio_init(void)
-{
-	struct device_node *np = NULL;
-
-	/*
-	 * This isn't ideal, but it gets things hooked up until this
-	 * driver is converted into a platform_device
-	 */
-	for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
-		of_at91_gpio_init_one(np);
-
-	return gpio_banks > 0 ? 0 : -EINVAL;
-}
-#else
-static int __init of_at91_gpio_init(void)
-{
-	return -EINVAL;
-}
-#endif
-
 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
 {
 	struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
@@ -1109,11 +954,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 
 	BUG_ON(nr_banks > MAX_GPIO_BANKS);
 
-	if (of_at91_gpio_init() < 0) {
-		/* No GPIO controller found in device tree */
-		for (i = 0; i < nr_banks; i++)
-			at91_gpio_init_one(i, data[i].regbase, data[i].id);
-	}
+	if (of_have_populated_dt())
+		return;
+
+	for (i = 0; i < nr_banks; i++)
+		at91_gpio_init_one(i, data[i].regbase, data[i].id);
 
 	for (i = 0; i < gpio_banks; i++) {
 		at91_gpio = &gpio_chip[i];
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..953932a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -26,6 +26,15 @@ config DEBUG_PINCTRL
 	help
 	  Say Y here to add some extra checks and diagnostics to PINCTRL calls.
 
+config PINCTRL_AT91
+	bool "AT91 pinctrl driver"
+	depends on OF
+	depends on ARCH_AT91
+	select PINMUX
+	select PINCONF
+	help
+	  Say Y here to enable the at91 pinctrl driver
+
 config PINCTRL_IMX
 	bool
 	select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..d3fda00 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
 obj-$(CONFIG_PINCTRL)		+= devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
+obj-$(CONFIG_PINCTRL_AT91)	+= pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_IMX)	+= pinctrl-imx.o
 obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 0000000..540943b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,1448 @@
+/*
+ * at91 pinctrl driver based on at91 pinmux core
+ *
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
+ * <plagnioj at jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#define DEBUG
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/irqdomain.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+/* Since we request GPIOs from ourself */
+#include <linux/pinctrl/consumer.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/at91_pio.h>
+
+#include "core.h"
+
+#define MAX_NB_GPIO_PER_BANK	32
+
+struct at91_gpio_chip {
+	struct gpio_chip	chip;
+	struct pinctrl_gpio_range range;
+	struct at91_gpio_chip	*next;		/* Bank sharing same clock */
+	int			pioc_hwirq;	/* PIO bank interrupt identifier on AIC */
+	int			pioc_virq;	/* PIO bank Linux virtual interrupt */
+	int			pioc_idx;	/* PIO bank index */
+	void __iomem		*regbase;	/* PIO bank virtual address */
+	struct clk		*clock;		/* associated clock */
+	struct irq_domain	*domain;	/* associated irq domain */
+};
+
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+static struct at91_gpio_chip *gpio_chip[MAX_GPIO_BANKS];
+
+static int gpio_banks;
+static unsigned long at91_gpio_caps;
+
+/* All PIO controllers support PIO3 features */
+#define AT91_GPIO_CAP_PIO3	(1 <<  0)
+
+#define has_pio3()	(at91_gpio_caps & AT91_GPIO_CAP_PIO3)
+
+
+#define PULL_UP		(0 << 1)
+#define MULTI_DRIVE	(1 << 1)
+
+/**
+ * struct at91_pmx_func - describes AT91 pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @ngroups: the number of groups
+ */
+struct at91_pmx_func {
+	const char *name;
+	const char **groups;
+	unsigned ngroups;
+};
+
+struct at91_pmx_pin {
+	uint32_t bank;
+	uint32_t pin;
+	uint32_t mux;
+	uint32_t pullup;
+	unsigned long conf;
+};
+
+/**
+ * struct at91_pin_group - describes an At91 pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of discrete physical pins used in this group, taken
+ *	from the driver-local pin enumeration space
+ * @npins: the number of pins in this group array, i.e. the number of
+ *	elements in .pins so we can iterate over that array
+ */
+struct at91_pin_group {
+	const char *name;
+	struct at91_pmx_pin *pins_conf;
+	unsigned int *pins;
+	unsigned npins;
+};
+
+struct at91_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+
+	int nbanks;
+
+	int nmux;
+	uint32_t *mux_mask;
+
+	struct at91_pmx_func *functions;
+	int nfunctions;
+
+	struct at91_pin_group *groups;
+	int ngroups;
+
+	void (*set_A_periph)(void __iomem *pio, unsigned mask);
+	void (*set_B_periph)(void __iomem *pio, unsigned mask);
+};
+
+static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
+				const struct at91_pinctrl *info,
+				const char *name)
+{
+	const struct at91_pin_group *grp = NULL;
+	int i;
+
+	for (i = 0; i < info->ngroups; i++) {
+		if (strcmp(info->groups[i].name, name))
+			continue;
+
+		grp = &info->groups[i];
+		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
+		break;
+	}
+
+	return grp;
+}
+
+static int at91_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	return info->ngroups;
+}
+
+static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
+				       unsigned selector)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	return info->groups[selector].name;
+}
+
+static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+			       const unsigned **pins,
+			       unsigned *npins)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	if (selector >= info->ngroups)
+		return -EINVAL;
+
+	*pins = info->groups[selector].pins;
+	*npins = info->groups[selector].npins;
+
+	return 0;
+}
+
+static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+		   unsigned offset)
+{
+	seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
+			struct device_node *np,
+			struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	const struct at91_pin_group *grp;
+	struct pinctrl_map *new_map;
+	struct device_node *parent;
+	int map_num = 1;
+	int i;
+	struct at91_pmx_pin *pin;
+
+	/*
+	 * first find the group of this node and check if we need create
+	 * config maps for pins
+	 */
+	grp = at91_pinctrl_find_group_by_name(info, np->name);
+	if (!grp) {
+		dev_err(info->dev, "unable to find group for node %s\n",
+			np->name);
+		return -EINVAL;
+	}
+
+	map_num += grp->npins;
+	new_map = kmalloc(sizeof(*new_map) * map_num, GFP_KERNEL);
+	if (!new_map)
+		return -ENOMEM;
+
+	*map = new_map;
+	*num_maps = map_num;
+
+	/* create mux map */
+	parent = of_get_parent(np);
+	if (!parent) {
+		kfree(new_map);
+		return -EINVAL;
+	}
+	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+	new_map[0].data.mux.function = parent->name;
+	new_map[0].data.mux.group = np->name;
+	of_node_put(parent);
+
+	/* create config map */
+	new_map++;
+	for (i = 0; i < grp->npins; i++) {
+		pin = &grp->pins_conf[i];
+
+		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+		new_map[i].data.configs.group_or_pin =
+				pin_get_name(pctldev, grp->pins[i]);
+		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
+		new_map[i].data.configs.num_configs = 1;
+	}
+
+	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+	return 0;
+}
+
+static void at91_dt_free_map(struct pinctrl_dev *pctldev,
+				struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
+static struct pinctrl_ops at91_pctrl_ops = {
+	.get_groups_count = at91_get_groups_count,
+	.get_group_name = at91_get_group_name,
+	.get_group_pins = at91_get_group_pins,
+	.pin_dbg_show = at91_pin_dbg_show,
+	.dt_node_to_map = at91_dt_node_to_map,
+	.dt_free_map = at91_dt_free_map,
+
+};
+
+static void __iomem * pin_to_controller(struct at91_pinctrl *info,
+				 unsigned int bank)
+{
+	return gpio_chip[bank]->regbase;
+}
+
+static inline int pin_to_bank(unsigned pin)
+{
+	return pin /= MAX_NB_GPIO_PER_BANK;
+}
+
+static unsigned pin_to_mask(unsigned int pin)
+{
+	return 1 << pin;
+}
+
+static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_IDR);
+}
+
+static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
+{
+	return (__raw_readl(pio + PIO_PUSR) >> pin) & 0x1;
+}
+
+static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, unsigned on)
+{
+	__raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
+}
+
+static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
+{
+	return (__raw_readl(pio + PIO_MDSR) >> pin) & 0x1;
+}
+
+static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, unsigned on)
+{
+	__raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
+}
+
+static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
+{
+
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+						pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+						pio + PIO_ABCDSR2);
+}
+
+static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_ASR);
+}
+
+static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_BSR);
+}
+
+static void at91_mux_set_C_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static void at91_mux_set_D_periph(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+	__raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+}
+
+static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
+{
+	if (pin->mux) {
+		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
+			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
+	} else {
+		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
+			pin->bank + 'A', pin->pin, pin->conf);
+	}
+}
+
+static int pin_check_config(struct at91_pinctrl *info, const char* name,
+			    int index, const struct at91_pmx_pin *pin)
+{
+	int mux;
+
+	/* check if it's a valid config */
+	if (pin->bank >= info->nbanks) {
+		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
+			name, index, pin->bank, info->nbanks);
+		return -EINVAL;
+	}
+
+	if (pin->pin >= 32) {
+		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= 32\n",
+			name, index, pin->pin);
+		return -EINVAL;
+	}
+
+	if (!pin->mux)
+		return 0;
+
+	mux = pin->mux - 1;
+
+	if (mux >= info->nmux) {
+		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
+			name, index, mux, info->nmux);
+		return -EINVAL;
+	}
+
+	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
+		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
+			name, index, mux, pin->bank + 'A', pin->pin);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
+{
+	__raw_writel(mask, pio + PIO_PDR);
+}
+
+static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, unsigned input)
+{
+	__raw_writel(mask, pio + PIO_PER);
+	__raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
+}
+
+static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+			   unsigned group)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
+	const struct at91_pmx_pin *pin;
+	uint32_t npins = info->groups[group].npins;
+	int i, ret;
+	unsigned mask;
+	void __iomem *pio;
+
+	dev_dbg(info->dev, "enable function %s group %s\n",
+		info->functions[selector].name, info->groups[group].name);
+
+	/* first check that all the pins of the group are valid with a valid
+	 * paramter */
+	for (i = 0; i < npins; i++) {
+		pin = &pins_conf[i];
+		ret = pin_check_config(info, info->groups[group].name, i, pin);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < npins; i++) {
+		pin = &pins_conf[i];
+		at91_pin_dbg(info->dev, pin);
+		pio = pin_to_controller(info, pin->bank);
+		mask = pin_to_mask(pin->pin);
+		at91_mux_disable_interrupt(pio, mask);
+		switch(pin->mux) {
+		case 0:
+			at91_mux_gpio_enable(pio, mask, 1);
+			break;
+		case 1:
+			info->set_A_periph(pio, mask);
+			break;
+		case 2:
+			info->set_B_periph(pio, mask);
+			break;
+		case 3:
+			at91_mux_set_C_periph(pio, mask);
+			break;
+		case 4:
+			at91_mux_set_D_periph(pio, mask);
+			break;
+		}
+		if (pin->mux)
+			at91_mux_gpio_disable(pio, mask);
+	}
+
+	return 0;
+}
+
+static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
+			   unsigned group)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
+	const struct at91_pmx_pin *pin;
+	uint32_t npins = info->groups[group].npins;
+	int i;
+	unsigned mask;
+	void __iomem *pio;
+
+	for (i = 0; i < npins; i++) {
+		pin = &pins_conf[i];
+		at91_pin_dbg(info->dev, pin);
+		pio = pin_to_controller(info, pin->bank);
+		mask = pin_to_mask(pin->pin);
+		at91_mux_gpio_enable(pio, mask, 1);
+	}
+}
+
+static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	return info->nfunctions;
+}
+
+static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
+					  unsigned selector)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	return info->functions[selector].name;
+}
+
+static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+			       const char * const **groups,
+			       unsigned * const num_groups)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+	*groups = info->functions[selector].groups;
+	*num_groups = info->functions[selector].ngroups;
+
+	return 0;
+}
+
+int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range,
+			    unsigned offset)
+{
+	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
+	struct at91_gpio_chip *at91_chip;
+	struct gpio_chip *chip;
+	unsigned mask;
+
+	if (!range) {
+		dev_err(npct->dev, "invalid range\n");
+		return -EINVAL;
+	}
+	if (!range->gc) {
+		dev_err(npct->dev, "missing GPIO chip in range\n");
+		return -EINVAL;
+	}
+	chip = range->gc;
+	at91_chip = container_of(chip, struct at91_gpio_chip, chip);
+
+	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
+
+	mask = 1 << (offset - chip->base);
+
+	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
+		offset, 'A' + range->id, offset - chip->base, mask);
+
+	__raw_writel(mask, at91_chip->regbase + PIO_PER);
+
+	return 0;
+}
+
+void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
+			   struct pinctrl_gpio_range *range,
+			   unsigned offset)
+{
+	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
+
+	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
+	/* Set the pin to some default state, GPIO is usually default */
+}
+
+static struct pinmux_ops at91_pmx_ops = {
+	.get_functions_count = at91_pmx_get_funcs_count,
+	.get_function_name = at91_pmx_get_func_name,
+	.get_function_groups = at91_pmx_get_groups,
+	.enable = at91_pmx_enable,
+	.disable = at91_pmx_disable,
+	.gpio_request_enable = at91_gpio_request_enable,
+	.gpio_disable_free = at91_gpio_disable_free,
+};
+
+static int at91_pinconf_get(struct pinctrl_dev *pctldev,
+			     unsigned pin_id, unsigned long *config)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	void __iomem *pio;
+	unsigned pin;
+
+	dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
+	pio = pin_to_controller(info, pin_to_bank(pin_id));
+	pin = pin_id % MAX_NB_GPIO_PER_BANK;
+
+	if (at91_mux_get_multidrive(pio, pin))
+		*config |= MULTI_DRIVE;
+
+	if (at91_mux_get_pullup(pio, pin))
+		*config |= PULL_UP;
+
+	return 0;
+}
+
+static int at91_pinconf_set(struct pinctrl_dev *pctldev,
+			     unsigned pin_id, unsigned long config)
+{
+	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+	unsigned mask;
+	void __iomem *pio;
+
+	dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
+	pio = pin_to_controller(info, pin_to_bank(pin_id));
+	mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
+
+	at91_mux_set_pullup(pio, mask, config & PULL_UP);
+	at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
+	return 0;
+}
+
+static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+				   struct seq_file *s, unsigned pin_id)
+{
+
+}
+
+static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+					 struct seq_file *s, unsigned group)
+{
+}
+
+struct pinconf_ops at91_pinconf_ops = {
+	.pin_config_get = at91_pinconf_get,
+	.pin_config_set = at91_pinconf_set,
+	.pin_config_dbg_show = at91_pinconf_dbg_show,
+	.pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc at91_pinctrl_desc = {
+	.pctlops = &at91_pctrl_ops,
+	.pmxops = &at91_pmx_ops,
+	.confops = &at91_pinconf_ops,
+	.owner = THIS_MODULE,
+};
+
+static const char *gpio_compat = "atmel,at91rm9200-gpio";
+
+static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
+					      struct device_node *np)
+{
+	struct device_node *child;
+
+	for_each_child_of_node(np, child) {
+		if (of_device_is_compatible(child, gpio_compat)) {
+			info->nbanks++;
+		} else {
+			info->nfunctions++;
+			info->ngroups += of_get_child_count(child);
+		}
+	}
+}
+
+static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
+					  struct device_node *np)
+{
+	int ret = 0;
+	int size;
+	const const __be32 *list;
+
+	list = of_get_property(np, "atmel,mux-mask", &size);
+	if (!list) {
+		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
+		return -EINVAL;
+	}
+
+	size /= sizeof(*list);
+	if (!size || size % info->nbanks) {
+		dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
+		return -EINVAL;
+	}
+	info->nmux = size / info->nbanks;
+
+	info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
+	if (!info->mux_mask) {
+		dev_err(info->dev, "could not alloc mux_mask\n");
+		return -ENOMEM;
+	}
+
+	ret = of_property_read_u32_array(np, "atmel,mux-mask",
+					  info->mux_mask, size);
+	if (ret)
+		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
+	return ret;
+}
+
+static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
+				struct at91_pin_group *grp,
+				struct at91_pinctrl *info,
+				u32 index)
+{
+	struct at91_pmx_pin *pin;
+	int size;
+	const const __be32 *list;
+	int i, j;
+
+	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+	/* Initialise group */
+	grp->name = np->name;
+
+	/*
+	 * the binding format is fsl,pins = <bank pin mux CONFIG ...>,
+	 * do sanity check and calculate pins number
+	 */
+	list = of_get_property(np, "atmel,pins", &size);
+	/* we do not check return since it's safe node passed down */
+	size /= sizeof(*list);
+	if (!size || size % 4) {
+		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
+		return -EINVAL;
+	}
+
+	grp->npins = size / 4;
+	pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
+				GFP_KERNEL);
+	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+				GFP_KERNEL);
+	if (!grp->pins_conf || !grp->pins)
+		return -ENOMEM;
+
+	for (i = 0, j = 0; i < size; i += 4, j++) {
+		pin->bank = be32_to_cpu(*list++);
+		pin->pin = be32_to_cpu(*list++);
+		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
+		pin->mux = be32_to_cpu(*list++);
+		pin->conf = be32_to_cpu(*list++);
+
+		at91_pin_dbg(info->dev, pin);
+		pin++;
+	}
+
+	return 0;
+}
+
+static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
+			struct at91_pinctrl *info, u32 index)
+{
+	struct device_node *child;
+	struct at91_pmx_func *func;
+	struct at91_pin_group *grp;
+	int ret;
+	static u32 grp_index;
+	u32 i = 0;
+
+	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+	func = &info->functions[index];
+
+	/* Initialise function */
+	func->name = np->name;
+	func->ngroups = of_get_child_count(np);
+	if (func->ngroups <= 0) {
+		dev_err(info->dev, "no groups defined\n");
+		return -EINVAL;
+	}
+	func->groups = devm_kzalloc(info->dev,
+			func->ngroups * sizeof(char *), GFP_KERNEL);
+	if (!func->groups)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, child) {
+		func->groups[i] = child->name;
+		grp = &info->groups[grp_index++];
+		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
+					   struct at91_pinctrl *info)
+{
+	int ret = 0;
+	int i, j;
+	uint32_t *tmp;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *child;
+
+	if (!np)
+		return -ENODEV;
+
+	info->dev = &pdev->dev;
+	at91_pinctrl_child_count(info, np);
+
+	if (info->nbanks < 1) {
+		dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
+		return -EINVAL;
+	}
+
+	ret = at91_pinctrl_mux_mask(info, np);
+	if (ret)
+		return ret;
+
+	dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
+
+	dev_dbg(&pdev->dev, "mux-mask\n");
+	tmp = info->mux_mask;
+	for (i = 0; i < info->nbanks; i++) {
+		for (j = 0; j < info->nmux; j++, tmp++) {
+			dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
+		}
+	}
+
+	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
+	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
+	info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
+					GFP_KERNEL);
+	if (!info->functions)
+		return -ENOMEM;
+
+	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
+					GFP_KERNEL);
+	if (!info->groups)
+		return -ENOMEM;
+
+	dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
+	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
+	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
+
+	i = 0;
+
+	for_each_child_of_node(np, child) {
+		if (of_device_is_compatible(child, gpio_compat))
+			continue;
+		ret = at91_pinctrl_parse_functions(child, info, i++);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to parse function\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
+{
+	struct at91_pinctrl *info;
+	struct pinctrl_pin_desc *pdesc;
+	int ret, i, j ,k;
+
+	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	ret = at91_pinctrl_probe_dt(pdev, info);
+	if (ret)
+		return ret;
+
+	/*
+	 * We need all the GPIO drivers to probe FIRST, or we will not be able
+	 * to obtain references to the struct gpio_chip * for them, and we
+	 * need this to proceed.
+	 */
+	for (i = 0; i < info->nbanks; i++) {
+		if (!gpio_chip[i]) {
+			dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
+			devm_kfree(&pdev->dev, info);
+			return -EPROBE_DEFER;
+		}
+	}
+
+	at91_pinctrl_desc.name = dev_name(&pdev->dev);
+	at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
+	at91_pinctrl_desc.pins = pdesc =
+		devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
+
+	if (!at91_pinctrl_desc.pins)
+		return -ENOMEM;
+
+	for (i = 0 , k = 0; i < info->nbanks; i++) {
+		for (j = 0; j < 32; j++, k++) {
+			pdesc->number = k;
+			pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
+			pdesc++;
+		}
+	}
+
+	info->set_A_periph = at91_mux_pio3_set_A_periph;
+	info->set_B_periph = at91_mux_pio3_set_B_periph;
+
+	if (has_pio3()) {
+		info->set_A_periph = at91_mux_set_A_periph;
+		info->set_B_periph = at91_mux_set_B_periph;
+	}
+
+	platform_set_drvdata(pdev, info);
+	info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
+
+	if (!info->pctl) {
+		dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* We will handle a range of GPIO pins */
+	for (i = 0; i < info->nbanks; i++)
+		pinctrl_add_gpio_range(info->pctl, &gpio_chip[i]->range);
+
+	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
+
+	return 0;
+
+err:
+	return ret;
+}
+
+int __devexit at91_pinctrl_remove(struct platform_device *pdev)
+{
+	struct at91_pinctrl *info = platform_get_drvdata(pdev);
+
+	pinctrl_unregister(info->pctl);
+
+	return 0;
+}
+
+static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	/*
+	 * Map back to global GPIO space and request muxing, the direction
+	 * parameter does not matter for this controller.
+	 */
+	int gpio = chip->base + offset;
+	int bank = chip->base / chip->ngpio;
+
+	dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
+		 'A' + bank, offset, gpio);
+
+	return pinctrl_request_gpio(gpio);
+}
+
+static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	int gpio = chip->base + offset;
+
+	pinctrl_free_gpio(gpio);
+}
+
+static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+	unsigned mask = 1 << offset;
+
+	__raw_writel(mask, pio + PIO_ODR);
+	return 0;
+}
+
+static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+	unsigned mask = 1 << offset;
+	u32 pdsr;
+
+	pdsr = __raw_readl(pio + PIO_PDSR);
+	return (pdsr & mask) != 0;
+}
+
+static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
+				int val)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+	unsigned mask = 1 << offset;
+
+	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
+}
+
+static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+				int val)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+	unsigned mask = 1 << offset;
+
+	__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
+	__raw_writel(mask, pio + PIO_OER);
+
+	return 0;
+}
+
+static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	int virq;
+
+	if (offset < chip->ngpio)
+		virq = irq_create_mapping(at91_gpio->domain, offset);
+	else
+		virq = -ENXIO;
+
+	dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+				chip->label, offset + chip->base, virq);
+	return virq;
+}
+
+static char peripheral_function(void __iomem *pio, unsigned mask)
+{
+	char	ret = 'X';
+	u8	select;
+
+	if (!pio)
+		return ret;
+
+	if (has_pio3()) {
+		select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
+		select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+		ret = 'A' + select;
+	} else {
+		ret = __raw_readl(pio + PIO_ABSR) & mask ?
+						'B' : 'A';
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+	int i;
+	struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+	void __iomem *pio = at91_gpio->regbase;
+
+	for (i = 0; i < chip->ngpio; i++) {
+		unsigned pin = chip->base + i;
+		unsigned mask = pin_to_mask(pin);
+		const char *gpio_label;
+		u32 pdsr;
+
+		gpio_label = gpiochip_is_requested(chip, i);
+		if (!gpio_label)
+			continue;
+
+		seq_printf(s, "[%s] GPIO%s%d: ",
+			   gpio_label, chip->label, i);
+		if (__raw_readl(pio + PIO_PSR) & mask) {
+			pdsr = __raw_readl(pio + PIO_PDSR);
+
+			seq_printf(s, "[gpio] %s\n",
+				   pdsr & mask ?
+				   "set" : "clear");
+		} else {
+			seq_printf(s, "[periph %c]\n",
+				   peripheral_function(pio, mask));
+		}
+	}
+}
+#else
+#define at91_gpio_dbg_show	NULL
+#endif
+
+/* Several AIC controller irqs are dispatched through this GPIO handler.
+ * To use any AT91_PIN_* as an externally triggered IRQ, first call
+ * at91_set_gpio_input() then maybe enable its glitch filter.
+ * Then just request_irq() with the pin ID; it works like any ARM IRQ
+ * handler.
+ * First implementation always triggers on rising and falling edges
+ * whereas the newer PIO3 can be additionally configured to trigger on
+ * level, edge with any polarity.
+ *
+ * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
+ * configuring them with at91_set_a_periph() or at91_set_b_periph().
+ * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
+ */
+
+static void gpio_irq_mask(struct irq_data *d)
+{
+	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+	void __iomem	*pio = at91_gpio->regbase;
+	unsigned	mask = 1 << d->hwirq;
+
+	if (pio)
+		__raw_writel(mask, pio + PIO_IDR);
+}
+
+static void gpio_irq_unmask(struct irq_data *d)
+{
+	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+	void __iomem	*pio = at91_gpio->regbase;
+	unsigned	mask = 1 << d->hwirq;
+
+	if (pio)
+		__raw_writel(mask, pio + PIO_IER);
+}
+
+static int gpio_irq_type(struct irq_data *d, unsigned type)
+{
+	switch (type) {
+	case IRQ_TYPE_NONE:
+	case IRQ_TYPE_EDGE_BOTH:
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+/* Alternate irq type for PIO3 support */
+static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+	void __iomem	*pio = at91_gpio->regbase;
+	unsigned	mask = 1 << d->hwirq;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		__raw_writel(mask, pio + PIO_ESR);
+		__raw_writel(mask, pio + PIO_REHLSR);
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		__raw_writel(mask, pio + PIO_ESR);
+		__raw_writel(mask, pio + PIO_FELLSR);
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		__raw_writel(mask, pio + PIO_LSR);
+		__raw_writel(mask, pio + PIO_FELLSR);
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		__raw_writel(mask, pio + PIO_LSR);
+		__raw_writel(mask, pio + PIO_REHLSR);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		/*
+		 * disable additional interrupt modes:
+		 * fall back to default behavior
+		 */
+		__raw_writel(mask, pio + PIO_AIMDR);
+		return 0;
+	case IRQ_TYPE_NONE:
+	default:
+		pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
+		return -EINVAL;
+	}
+
+	/* enable additional interrupt modes */
+	__raw_writel(mask, pio + PIO_AIMER);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static u32 wakeups[MAX_GPIO_BANKS];
+
+static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
+{
+	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+	unsigned	mask = 1 << d->hwirq;
+	unsigned	bank = at91_gpio->pioc_idx;
+
+	if (unlikely(bank >= MAX_GPIO_BANKS))
+		return -EINVAL;
+
+	if (state)
+		wakeups[bank] |= mask;
+	else
+		wakeups[bank] &= ~mask;
+
+	irq_set_irq_wake(at91_gpio->pioc_virq, state);
+
+	return 0;
+}
+#else
+#define gpio_irq_set_wake	NULL
+#endif
+
+static struct irq_chip gpio_irqchip = {
+	.name		= "GPIO",
+	.irq_disable	= gpio_irq_mask,
+	.irq_mask	= gpio_irq_mask,
+	.irq_unmask	= gpio_irq_unmask,
+	/* .irq_set_type is set dynamically */
+	.irq_set_wake	= gpio_irq_set_wake,
+};
+
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct irq_data *idata = irq_desc_get_irq_data(desc);
+	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
+	void __iomem	*pio = at91_gpio->regbase;
+	unsigned long	isr;
+	int		n;
+
+	chained_irq_enter(chip, desc);
+	for (;;) {
+		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
+		 * When there none are pending, we're finished unless we need
+		 * to process multiple banks (like ID_PIOCDE on sam9263).
+		 */
+		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
+		if (!isr) {
+			if (!at91_gpio->next)
+				break;
+			at91_gpio = at91_gpio->next;
+			pio = at91_gpio->regbase;
+			continue;
+		}
+
+		n = find_first_bit(&isr, BITS_PER_LONG);
+		while (n < BITS_PER_LONG) {
+			generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
+			n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
+		}
+	}
+	chained_irq_exit(chip, desc);
+	/* now it may re-trigger */
+}
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	struct at91_gpio_chip	*at91_gpio = h->host_data;
+
+	irq_set_lockdep_class(virq, &gpio_lock_class);
+
+	/*
+	 * Can use the "simple" and not "edge" handler since it's
+	 * shorter, and the AIC handles interrupts sanely.
+	 */
+	irq_set_chip_and_handler(virq, &gpio_irqchip,
+				 handle_simple_irq);
+	set_irq_flags(virq, IRQF_VALID);
+	irq_set_chip_data(virq, at91_gpio);
+
+	return 0;
+}
+
+static struct irq_domain_ops at91_gpio_ops = {
+	.map	= at91_gpio_irq_map,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static int at91_gpio_of_irq_setup(struct device_node *node,
+				  struct at91_gpio_chip *at91_gpio)
+{
+	struct at91_gpio_chip	*prev = NULL;
+	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
+
+	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
+
+	/* Setup proper .irq_set_type function */
+	if (has_pio3())
+		gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+	else
+		gpio_irqchip.irq_set_type = gpio_irq_type;
+
+	/* Disable irqs of this PIO controller */
+	__raw_writel(~0, at91_gpio->regbase + PIO_IDR);
+
+	/* Setup irq domain */
+	at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
+						&at91_gpio_ops, at91_gpio);
+	if (!at91_gpio->domain)
+		panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+			at91_gpio->pioc_idx);
+
+	/* Setup chained handler */
+	if (at91_gpio->pioc_idx)
+		prev = gpio_chip[at91_gpio->pioc_idx - 1];
+
+	/* The toplevel handler handles one bank of GPIOs, except
+	 * on some SoC it can handles up to three...
+	 * We only set up the handler for the first of the list.
+	 */
+	if (prev && prev->next == at91_gpio)
+		return 0;
+
+	irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
+	irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
+
+	return 0;
+}
+
+/* This structure is replicated for each GPIO block allocated at probe time */
+static struct gpio_chip at91_gpio_template = {
+	.request		= at91_gpio_request,
+	.free			= at91_gpio_free,
+	.direction_input	= at91_gpio_direction_input,
+	.get			= at91_gpio_get,
+	.direction_output	= at91_gpio_direction_output,
+	.set			= at91_gpio_set,
+	.to_irq			= at91_gpio_to_irq,
+	.dbg_show		= at91_gpio_dbg_show,
+	.can_sleep		= 0,
+	.ngpio			= 32,
+};
+
+static void __devinit at91_gpio_probe_fixup(void)
+{
+	unsigned i;
+	struct at91_gpio_chip *at91_gpio, *last = NULL;
+
+	for (i = 0; i < gpio_banks; i++) {
+		at91_gpio = gpio_chip[i];
+
+		/*
+		 * GPIO controller are grouped on some SoC:
+		 * PIOC, PIOD and PIOE can share the same IRQ line
+		 */
+		if (last && last->pioc_virq == at91_gpio->pioc_virq)
+			last->next = at91_gpio;
+		last = at91_gpio;
+	}
+}
+
+static int __devinit at91_gpio_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *res;
+	struct at91_gpio_chip *at91_chip = NULL;
+	struct gpio_chip *chip;
+	struct pinctrl_gpio_range *range;
+	int ret = 0;
+	int irq;
+	int alias_idx = of_alias_get_id(np, "gpio");
+	uint32_t ngpio;
+
+	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chip));
+	if (gpio_chip[alias_idx]) {
+		ret = -EBUSY;
+		goto err;
+	}
+
+	at91_gpio_caps = (unsigned long)np->data;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENOENT;
+		goto err;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		ret = irq;
+		goto err;
+	}
+
+	at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
+	if (!at91_chip) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
+	if (!at91_chip->regbase) {
+		dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	at91_chip->pioc_virq = irq;
+	at91_chip->pioc_idx = alias_idx;
+
+	at91_chip->clock = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(at91_chip->clock)) {
+		dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
+		goto err;
+	}
+
+	if (clk_prepare(at91_chip->clock))
+		goto clk_prep_err;
+
+	/* enable PIO controller's clock */
+	if (clk_enable(at91_chip->clock)) {
+		dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
+		goto clk_err;
+	}
+
+	at91_chip->chip = at91_gpio_template;
+
+	chip = &at91_chip->chip;
+	chip->of_node = np;
+	chip->label = dev_name(&pdev->dev);
+	chip->dev = &pdev->dev;
+	chip->owner = THIS_MODULE;
+	chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
+
+	if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
+		if (ngpio >= MAX_NB_GPIO_PER_BANK)
+			pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
+			       alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
+		else
+			chip->ngpio = ngpio;
+	}
+
+	range = &at91_chip->range;
+	range->name = chip->label;
+	range->id = alias_idx;
+	range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
+
+	range->npins = chip->ngpio;
+	range->gc = chip;
+
+	ret = gpiochip_add(chip);
+	if (ret)
+		goto clk_err;
+
+	gpio_chip[alias_idx] = at91_chip;
+	gpio_banks = max(gpio_banks, alias_idx + 1);
+
+	at91_gpio_probe_fixup();
+
+	at91_gpio_of_irq_setup(np, at91_chip);
+
+	dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
+
+	return 0;
+
+clk_err:
+	clk_unprepare(at91_chip->clock);
+clk_prep_err:
+	clk_put(at91_chip->clock);
+err:
+	dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
+
+	return ret;
+}
+
+static struct of_device_id at91_gpio_of_match[] __devinitdata = {
+	{ .compatible = "atmel,at91rm9200-gpio", },
+	{ .compatible = "atmel,at91sam9x5-gpio", .data = (void*)AT91_GPIO_CAP_PIO3, },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver at91_gpio_driver = {
+	.driver = {
+		.name = "gpio-at91",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(at91_gpio_of_match),
+	},
+	.probe = at91_gpio_probe,
+};
+
+static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "atmel,at91rm9200-pinctrl", },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver at91_pinctrl_driver = {
+	.driver = {
+		.name = "pinctrl-at91",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(at91_pinctrl_of_match),
+	},
+	.probe = at91_pinctrl_probe,
+	.remove = __devexit_p(at91_pinctrl_remove),
+};
+
+static int __init at91_pinctrl_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&at91_gpio_driver);
+	if (ret)
+		return ret;
+	return platform_driver_register(&at91_pinctrl_driver);
+}
+arch_initcall(at91_pinctrl_init);
+
+static void __exit at91_pinctrl_exit(void)
+{
+	platform_driver_unregister(&at91_pinctrl_driver);
+}
+
+module_exit(at91_pinctrl_exit);
+MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>");
+MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From jarkko.nikula at bitmer.com  Fri Aug 10 09:15:26 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Fri, 10 Aug 2012 16:15:26 +0300
Subject: [PATCH 00/11] ARM/ASoC: OMAP McBSP device tree support
In-Reply-To: <20120808112132.GN16861@opensource.wolfsonmicro.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <20120808112132.GN16861@opensource.wolfsonmicro.com>
Message-ID: <5025096E.8030300@bitmer.com>

On 08/08/2012 02:21 PM, Mark Brown wrote:
> On Wed, Aug 08, 2012 at 12:11:30PM +0300, Peter Ujfalusi wrote:
> 
>> The series changes McBSP related files mostly. It would be great if the whole
>> series could go via audio tree (if the patches are OK and it is fine by Tony).
> 
> I'm OK with all the patches, if Tony's happy with me applying them then
> I'll put them in a separate branch so they can easily be merged into the
> OMAP trees (or similarly if it's applied in an OMAP tree having a branch
> I can merge if needed would be good).

I suppose we could apply 1/11, 3-6/11 and 9-10 right away (2/11 perhaps
should go near 11/11?) and apply 7-8/11 (sidetone patches that increase
consumption) later?

My ack to patches 1, 3-6 and 9-10:

Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>


From ldewangan at nvidia.com  Fri Aug 10 09:03:02 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Fri, 10 Aug 2012 18:33:02 +0530
Subject: [PATCH] ARM: tegra: use IO_ADDRESS for getting virtual address
Message-ID: <1344603782-2541-1-git-send-email-ldewangan@nvidia.com>

Use macro IO_ADDRESS for getting virtual address of
corresponding physical address to make the consistency
with rest of Tegra code-base.
This macro calls the IO_TO_VIRT() which is defined in
arch/arm/mach-tegra/include/mach/iomap.h

Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
---
 arch/arm/mach-tegra/apbio.c |    4 ++--
 arch/arm/mach-tegra/fuse.c  |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index dc0fe38..643a378 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -293,12 +293,12 @@ static apbio_write_fptr apbio_write;
 
 static u32 tegra_apb_readl_direct(unsigned long offset)
 {
-	return readl(IO_TO_VIRT(offset));
+	return readl(IO_ADDRESS(offset));
 }
 
 static void tegra_apb_writel_direct(u32 value, unsigned long offset)
 {
-	writel(value, IO_TO_VIRT(offset));
+	writel(value, IO_ADDRESS(offset));
 }
 
 void tegra_apb_io_init(void)
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f946d12..0b7db17 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -93,9 +93,9 @@ void tegra_init_fuse(void)
 {
 	u32 id;
 
-	u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+	u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 	reg |= 1 << 28;
-	writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+	writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
 	reg = tegra_fuse_readl(FUSE_SKU_INFO);
 	tegra_sku_id = reg & 0xFF;
-- 
1.7.1.1



From matt at genesi-usa.com  Fri Aug 10 09:33:06 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Fri, 10 Aug 2012 08:33:06 -0500
Subject: imx6q restart is broken
In-Reply-To: <20120809210709.GV18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <CAKGA1b=--C_MEHgc4m2f4cQwkx-=njss7bpT+EzXgKZJ2v=+Hw@mail.gmail.com>
 <20120809210709.GV18957@n2100.arm.linux.org.uk>
Message-ID: <CAKGA1bnh9tD5hey3E2j6XhUqOFV=FgU1W13oSMfpXxxnV_MSfA@mail.gmail.com>

On Thu, Aug 9, 2012 at 4:07 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, Aug 09, 2012 at 02:03:13PM -0500, Matt Sealey wrote:
>> I have an irrelevant but possibly related question here; in
>> mm/proc-v7.S there's this snip of code;
>>
>> #ifdef CONFIG_SMP
>>         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
>>         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
>>         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
>>         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
>>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
>>         mcreq   p15, 0, r0, c1, c0, 1
>> #endif
>>
>> Which I am reading as, read the SMP bit from cp15 and see if it's
>> enabled, or on UP set the SMP bit and then write it back
>> regardless.
>>
>> On a system where !CONFIG_SMP but it's SMP-capable like i.MX6Q, ALT_UP
>> method will get used and the SMP bit will get
>> set regardless.
>
> I got here and stopped reading any further.  No, it doesn't work like
> that; you don't understand the assembly.
>
> Yes, you're right that the ALT_UP version will be used.  This sets r0
> to 1 << 6.  The very next instruction tests whether bit 6 is set in r0.
> The following three instructions will only be executed _if_ that bit
> was zero.

Right but, as I read it...

if (CONFIG_SMP)
   read cp15
else
   set bit to one to hack it
if (!smp)
  set smp
  write it back

So who unsets the SMP bit? When the core goes down does it clear it,
or are we just
being safe for CPU startup? Does it still have an effect in the chip
logic even if the core
is 'not plugged'?

What happens if you're in CONFIG_SMP and you say maxcpus=1?

> I'm assuming that the rest of your email is therefore irrelevant; I
> have no desire to continue reading such a long message when the premise
> it's (presumably) based upon is false.  If you have any further questions
> please restate them succinctly after taking on board the above.  Thanks.

Please read the rest... I just didn't write first my question properly.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From festevam at gmail.com  Fri Aug 10 09:35:36 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 10 Aug 2012 10:35:36 -0300
Subject: [PATCH v2 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CAOMZO5D2nwDa_20S1tjnCxxhHKaMvg60X5arS2m11cayR_ZdNQ@mail.gmail.com>

On 8/10/12, Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> wrote:

> +			serial at 43f90000 {
> +				status = "okay";
> +			};
> +
> +			serial at 43f94000 {
> +				status = "okay";
> +			};

On other i.MX boards the format is:


From matt at genesi-usa.com  Fri Aug 10 09:36:02 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Fri, 10 Aug 2012 08:36:02 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120810014119.GD19617@S2101-09.ap.freescale.net>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
 <20120810014119.GD19617@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 8:41 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Thu, Aug 09, 2012 at 09:29:39AM -0500, Matt Sealey wrote:
>> The reason the new kernel depends on the new U-Boot is we're trying to
>> do all pinmux configuration in U-Boot (and we do in-house, and it
>> works). No pinctrl stuff in the kernel or device tree is required at
>> this point. The Old Kernel will remux a few things redundantly or
>> change drive strengths or whatever or add hysteresis to the UART port
>> which is not board-burning but is not really necessary, but it will
>> work. The new kernel will just be able to do what it does out of the
>> box, which is how it should be (hence why I object to adding pinctrl
>> setup...)
>
> Then I will have to refuse to accept your patch, because I'm working on
> a series to remove pinctrl_provide_dummies() from imx51_dt_init().

Requiring it breaks the entire concept of the device tree to describe running
hardware. It is not a configuration script. pinctrl should be optional
- built in
always, but not necessary to turn a board on if it's already configured.

What would happen if a board were designed that only used the default ALT
settings on i.MX53 or so? You'd have to redefine every default IOMUX pad
just to get it to boot. That's intolerable.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From festevam at gmail.com  Fri Aug 10 09:38:02 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 10 Aug 2012 10:38:02 -0300
Subject: [PATCH v2 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CAOMZO5D=1XfV==+VvgzsJccLPiGd6xDCjVSRYxrH0VMzEtX_gg@mail.gmail.com>

On 8/10/12, Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> wrote:

> +			serial at 43f90000 {
> +				status = "okay";
> +			};
> +
> +			serial at 43f94000 {
> +				status = "okay";

On other i.mx boards the format is:

uart1: serial at 43f90000

Should the same be done here?

This would allow to quickly recognize the port number without having
to look at the datasheet or .dtsi file.

Regards,

Fabio Estevam


From linux at arm.linux.org.uk  Fri Aug 10 09:53:26 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 10 Aug 2012 14:53:26 +0100
Subject: imx6q restart is broken
In-Reply-To: <CAKGA1bnh9tD5hey3E2j6XhUqOFV=FgU1W13oSMfpXxxnV_MSfA@mail.gmail.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <CAKGA1b=--C_MEHgc4m2f4cQwkx-=njss7bpT+EzXgKZJ2v=+Hw@mail.gmail.com>
 <20120809210709.GV18957@n2100.arm.linux.org.uk>
 <CAKGA1bnh9tD5hey3E2j6XhUqOFV=FgU1W13oSMfpXxxnV_MSfA@mail.gmail.com>
Message-ID: <20120810135326.GY18957@n2100.arm.linux.org.uk>

On Fri, Aug 10, 2012 at 08:33:06AM -0500, Matt Sealey wrote:
> On Thu, Aug 9, 2012 at 4:07 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Thu, Aug 09, 2012 at 02:03:13PM -0500, Matt Sealey wrote:
> >> I have an irrelevant but possibly related question here; in
> >> mm/proc-v7.S there's this snip of code;
> >>
> >> #ifdef CONFIG_SMP
> >>         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
> >>         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
> >>         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
> >>         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
> >>         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
> >>         mcreq   p15, 0, r0, c1, c0, 1
> >> #endif
> >>
> >> Which I am reading as, read the SMP bit from cp15 and see if it's
> >> enabled, or on UP set the SMP bit and then write it back
> >> regardless.
> >>
> >> On a system where !CONFIG_SMP but it's SMP-capable like i.MX6Q, ALT_UP
> >> method will get used and the SMP bit will get
> >> set regardless.
> >
> > I got here and stopped reading any further.  No, it doesn't work like
> > that; you don't understand the assembly.
> >
> > Yes, you're right that the ALT_UP version will be used.  This sets r0
> > to 1 << 6.  The very next instruction tests whether bit 6 is set in r0.
> > The following three instructions will only be executed _if_ that bit
> > was zero.
> 
> Right but, as I read it...
> 
> if (CONFIG_SMP)
>    read cp15
> else
>    set bit to one to hack it
> if (!smp)
>   set smp
>   write it back

Thank you for not reading what I wrote (or maybe you can't write back
what I said correctly, but either way, it's just making me think that
replying is a waste of time.)

> So who unsets the SMP bit? When the core goes down does it clear it,
> or are we just
> being safe for CPU startup? Does it still have an effect in the chip
> logic even if the core
> is 'not plugged'?

Generally we don't.  Because on secure mode devices, we can't write the
register, and if we tried to we'd get an abort.

So, if we detect a SMP capable CPU, we will enable the SMP bit if it
wasn't already enabled, and never ever attempt to disable it.

> What happens if you're in CONFIG_SMP and you say maxcpus=1?
> 
> > I'm assuming that the rest of your email is therefore irrelevant; I
> > have no desire to continue reading such a long message when the premise
> > it's (presumably) based upon is false.  If you have any further questions
> > please restate them succinctly after taking on board the above.  Thanks.
> 
> Please read the rest... I just didn't write first my question properly.

No, unless you can say what you want more succinctly, I'm not going
to bother reading your (apparantly regular) massive emails.


From u.kleine-koenig at pengutronix.de  Fri Aug 10 09:58:29 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 10 Aug 2012 15:58:29 +0200
Subject: [PATCH v2 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <CAOMZO5D=1XfV==+VvgzsJccLPiGd6xDCjVSRYxrH0VMzEtX_gg@mail.gmail.com>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
 <CAOMZO5D=1XfV==+VvgzsJccLPiGd6xDCjVSRYxrH0VMzEtX_gg@mail.gmail.com>
Message-ID: <20120810135829.GK25520@pengutronix.de>

Hello Fabio,

On Fri, Aug 10, 2012 at 10:38:02AM -0300, Fabio Estevam wrote:
> On 8/10/12, Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> wrote:
> > +			serial at 43f90000 {
> > +				status = "okay";
> > +			};
> > +
> > +			serial at 43f94000 {
> > +				status = "okay";
> 
> On other i.mx boards the format is:
> 
> uart1: serial at 43f90000
> 
> Should the same be done here?
I don't care much, but I like to minimize duplication. As dtc bails out
if you get it wrong it would be ok for me to keep the label.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From shawn.guo at linaro.org  Fri Aug 10 10:04:08 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 22:04:08 +0800
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
 <20120810014119.GD19617@S2101-09.ap.freescale.net>
 <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>
Message-ID: <20120810140406.GB3409@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 08:36:02AM -0500, Matt Sealey wrote:
> Requiring it breaks the entire concept of the device tree to describe running
> hardware. It is not a configuration script. pinctrl should be optional
> - built in
> always, but not necessary to turn a board on if it's already configured.
> 
How would kernel know if it's already configured, correctly?

> What would happen if a board were designed that only used the default ALT
> settings on i.MX53 or so? You'd have to redefine every default IOMUX pad
> just to get it to boot. That's intolerable.
> 
Come on, even the pad configuration are all the default?  Even if that's
the case, yes, we still need to do it.  How do we know if firmware has
changed the settings or not.

-- 
Regards,
Shawn



From rogerq at ti.com  Fri Aug 10 10:05:58 2012
From: rogerq at ti.com (Roger Quadros)
Date: Fri, 10 Aug 2012 17:05:58 +0300
Subject: [PATCH] perf: Use pre-empt safe cpu_get/put insted of smp_processor_id
Message-ID: <1344607558-15481-1-git-send-email-rogerq@ti.com>

gets rid of below messages with CONFIG_DEBUG_PREEMPT enabled

[   28.832916] debug_smp_processor_id: 18 callbacks suppressed
[   28.832946] BUG: using smp_processor_id() in preemptible [00000000] code: modprobe/1763
[   28.841491] caller is pwrdm_set_next_pwrst+0x54/0x120

Signed-off-by: Roger Quadros <rogerq at ti.com>
---
 arch/arm/mach-omap2/clock.c       |    9 ++++++---
 arch/arm/mach-omap2/pm34xx.c      |   12 ++++++++----
 arch/arm/mach-omap2/powerdomain.c |    6 ++++--
 3 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..06747b6 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -285,7 +285,8 @@ void omap2_clk_disable(struct clk *clk)
 	pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
 	if (clk->ops && clk->ops->disable) {
-		trace_clock_disable(clk->name, 0, smp_processor_id());
+		trace_clock_disable(clk->name, 0, get_cpu());
+		put_cpu();
 		clk->ops->disable(clk);
 	}
 
@@ -339,7 +340,8 @@ int omap2_clk_enable(struct clk *clk)
 	}
 
 	if (clk->ops && clk->ops->enable) {
-		trace_clock_enable(clk->name, 1, smp_processor_id());
+		trace_clock_enable(clk->name, 1, get_cpu());
+		put_cpu();
 		ret = clk->ops->enable(clk);
 		if (ret) {
 			WARN(1, "clock: %s: could not enable: %d\n",
@@ -380,7 +382,8 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
 	/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
 	if (clk->set_rate) {
-		trace_clock_set_rate(clk->name, rate, smp_processor_id());
+		trace_clock_set_rate(clk->name, rate, get_cpu());
+		put_cpu();
 		ret = clk->set_rate(clk, rate);
 	}
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..81fec2e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,18 +357,22 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
+	unsigned cpu;
+
 	local_fiq_disable();
 
 	if (omap_irq_pending())
 		goto out;
 
-	trace_power_start(POWER_CSTATE, 1, smp_processor_id());
-	trace_cpu_idle(1, smp_processor_id());
+	cpu = get_cpu();
+	trace_power_start(POWER_CSTATE, 1, cpu);
+	trace_cpu_idle(1, cpu);
 
 	omap_sram_idle();
 
-	trace_power_end(smp_processor_id());
-	trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
+	trace_power_end(cpu);
+	trace_cpu_idle(PWR_EVENT_EXIT, cpu);
+	put_cpu();
 
 out:
 	local_fiq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..138bf86 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -169,7 +169,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 				       ((state & OMAP_POWERSTATE_MASK) << 8) |
 				       ((prev & OMAP_POWERSTATE_MASK) << 0));
 			trace_power_domain_target(pwrdm->name, trace_state,
-						  smp_processor_id());
+						  get_cpu());
+			put_cpu();
 		}
 		break;
 	default:
@@ -491,7 +492,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
 		/* Trace the pwrdm desired target state */
 		trace_power_domain_target(pwrdm->name, pwrst,
-					  smp_processor_id());
+					  get_cpu());
+		put_cpu();
 		/* Program the pwrdm desired target state */
 		ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
 	}
-- 
1.7.4.1



From shijie8 at gmail.com  Fri Aug 10 10:15:01 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Fri, 10 Aug 2012 10:15:01 -0400
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208101325.23075.marex@denx.de>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
 <201208101325.23075.marex@denx.de>
Message-ID: <CAMiH66FAVVPLZ9hCyRcNCm1Le2JrCc+55CUw7UCtPjw+31w5gw@mail.gmail.com>

On Fri, Aug 10, 2012 at 7:25 AM, Marek Vasut <marex at denx.de> wrote:
> Dear Huang Shijie,
>
>> Add NAND write verify support in gpmi-nand driver.
>>
>> Signed-off-by: Huang Shijie <b32955 at freescale.com>
>> ---
>>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   17 +++++++++++++++++
>>  1 files changed, 17 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..6394483 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> @@ -1488,6 +1488,22 @@ static int gpmi_set_geometry(struct gpmi_nand_data
>> *this) return gpmi_alloc_dma_buffer(this);
>>  }
>>
>> +#define MAX_PAGESIZE 8192
>
> Use NAND_MAX_PAGESIZE, see include/linux/mtd/nand.h .
>
>> +static uint8_t verify_buf[MAX_PAGESIZE];

ok, thanks.

>
> What will happen when you have two NANDs attached to GPMI controller and they
> hit this place both at once? Race condition, causing this function to fail for
> both?
>
Even there are two nand chips, there is only one gpmi controller.
And the current gpmi-nand does not support two nands now.
does the race occur with only one nand chip?


> Possibly devm_kmalloc() such buffer per-controller?
>
>> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
>> len) +{
>> +     struct nand_chip *nand = mtd->priv;
>> +     int ret;
>> +
>> +     ret = gpmi_ecc_read_page(mtd, nand, verify_buf, 0, 0);
>
> mtd->chip.ecc.read_page() ?
In actually, they are the same.


Best Regards
Huang Shijie


From will.deacon at arm.com  Fri Aug 10 10:22:09 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 15:22:09 +0100
Subject: [PATCH] mutex: place lock in contended state after fastpath_lock
 failure
Message-ID: <1344608529-2377-1-git-send-email-will.deacon@arm.com>

ARM recently moved to asm-generic/mutex-xchg.h for its mutex
implementation after the previous implementation was found to be missing
some crucial memory barriers. However, this has revealed some problems
running hackbench on SMP platforms due to the way in which the
MUTEX_SPIN_ON_OWNER code operates.

The symptoms are that a bunch of hackbench tasks are left waiting on an
unlocked mutex and therefore never get woken up to claim it. This boils
down to the following sequence of events:

        Task A        Task B        Task C        Lock value
0                                                     1
1       lock()                                        0
2                     lock()                          0
3                     spin(A)                         0
4       unlock()                                      1
5                                   lock()            0
6                     cmpxchg(1,0)                    0
7                     contended()                    -1
8       lock()                                        0
9       spin(C)                                       0
10                                  unlock()          1
11      cmpxchg(1,0)                                  0
12      unlock()                                      1

At this point, the lock is unlocked, but Task B is in an uninterruptible
sleep with nobody to wake it up.

This patch fixes the problem by ensuring we put the lock into the
contended state if we fail to acquire it on the fastpath, ensuring that
any blocked waiters are woken up when the mutex is released.

Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Chris Mason <chris.mason at fusionio.com>
Cc: Ingo Molnar <mingo at elte.hu>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: <stable at vger.kernel.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

Nico: Can I add your S-o-B to this please? Also, preliminary benchmarks
      are now showing a slight performance improvement on A15 if I use
      the -dec variant rather than -xchg. I'll follow up with a patch
      once I've got more numbers.

 include/asm-generic/mutex-xchg.h |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 580a6d3..c04e0db 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -26,7 +26,13 @@ static inline void
 __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
-		fail_fn(count);
+		/*
+		 * We failed to acquire the lock, so mark it contended
+		 * to ensure that any waiting tasks are woken up by the
+		 * unlock slow path.
+		 */
+		if (likely(atomic_xchg(count, -1) != 1))
+			fail_fn(count);
 }
 
 /**
@@ -43,7 +49,8 @@ static inline int
 __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
-		return fail_fn(count);
+		if (likely(atomic_xchg(count, -1) != 1))
+			return fail_fn(count);
 	return 0;
 }
 
-- 
1.7.4.1



From matt at genesi-usa.com  Fri Aug 10 10:26:36 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Fri, 10 Aug 2012 09:26:36 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120810140406.GB3409@S2101-09.ap.freescale.net>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
 <20120810014119.GD19617@S2101-09.ap.freescale.net>
 <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>
 <20120810140406.GB3409@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1b=bcV2RKDvv=hTjfCo+uTXgcvsTPP0pM-vZYUHLMcrRvg@mail.gmail.com>

On Fri, Aug 10, 2012 at 9:04 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Fri, Aug 10, 2012 at 08:36:02AM -0500, Matt Sealey wrote:
>> Requiring it breaks the entire concept of the device tree to describe running
>> hardware. It is not a configuration script. pinctrl should be optional
>> - built in
>> always, but not necessary to turn a board on if it's already configured.
>>
> How would kernel know if it's already configured, correctly?

Trust! When we release the new U-Boot, it will be already configured,
every pin in the schematic, every
pin from the old kernels (not mainline, some of that was wrong),
exactly the way it should be. There's
nothing new with the Efika MX.

If you try and boot it on the old Efika, it just won't work reliably
for any peripheral U-Boot didn't
already configure, but for the current version you'd get MMC, PATA,
serial port, SPI (NOR/PMIC)
which is all we configure in the DT right now anyway... this is only
going to be an issue once we
get to displays and USB (I2C isn't set up in the old one).

>> What would happen if a board were designed that only used the default ALT
>> settings on i.MX53 or so? You'd have to redefine every default IOMUX pad
>> just to get it to boot. That's intolerable.
>
> Come on, even the pad configuration are all the default?  Even if that's
> the case, yes, we still need to do it.  How do we know if firmware has
> changed the settings or not.

TRUST...

Maybe you can't rely on the development boards from Freescale, but we have to
do unit testing at every stage of operation for consumer devices. Once U-Boot
passes all tests, why bother re-testing the exact same configuration, now done
twice, in the kernel? I don't want to debug pad settings twice, and we shouldn't
need to.

If you really think it's necessary then fine, we'll do it.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From haojian.zhuang at gmail.com  Fri Aug 10 10:29:58 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 10 Aug 2012 22:29:58 +0800
Subject: [PATCH] ARM: mmp: fix potential NULL dereference
In-Reply-To: <1344416528-3586-1-git-send-email-yliu.null@gmail.com>
References: <1344416528-3586-1-git-send-email-yliu.null@gmail.com>
Message-ID: <CAN1soZxkvHOTXb0wfvRmi4DDasD=r9vfoj5uA0CVhAQt2jUkTg@mail.gmail.com>

On Wed, Aug 8, 2012 at 5:02 PM, Yuanhan Liu <yliu.null at gmail.com> wrote:
> Fix the wrong logic: we should use || instead of &&
>
> Cc: Leo Yan <leoy at marvell.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Signed-off-by: Yuanhan Liu <yliu.null at gmail.com>
> ---
>  arch/arm/mach-mmp/sram.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
Applied.

Thanks
Haojian


From shawn.guo at linaro.org  Fri Aug 10 10:40:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 10 Aug 2012 22:40:05 +0800
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1b=bcV2RKDvv=hTjfCo+uTXgcvsTPP0pM-vZYUHLMcrRvg@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
 <20120810014119.GD19617@S2101-09.ap.freescale.net>
 <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>
 <20120810140406.GB3409@S2101-09.ap.freescale.net>
 <CAKGA1b=bcV2RKDvv=hTjfCo+uTXgcvsTPP0pM-vZYUHLMcrRvg@mail.gmail.com>
Message-ID: <20120810144003.GC3409@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 09:26:36AM -0500, Matt Sealey wrote:
> If you really think it's necessary then fine, we'll do it.
> 
Yes, please do.

-- 
Regards,
Shawn



From matt at genesi-usa.com  Fri Aug 10 10:42:57 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Fri, 10 Aug 2012 09:42:57 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1b=bcV2RKDvv=hTjfCo+uTXgcvsTPP0pM-vZYUHLMcrRvg@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120808151555.GE14718@S2101-09.ap.freescale.net>
 <CAKGA1bkbp8_z+HSr97cp_jeCrdTHkQxuZPFu0QPWwnXphWVdZA@mail.gmail.com>
 <CAOMZO5DOEfV4wTSNW8ABaUhGwa_KG3Bkt0o-rs8k-cZk4P-=+A@mail.gmail.com>
 <CAKGA1bkOo=En2P18FaBpq_KAZ88kisikXhNTabvnDknQ-EwFjA@mail.gmail.com>
 <20120810014119.GD19617@S2101-09.ap.freescale.net>
 <CAKGA1bmd-53G=59F7Nsd3Sx2eEQgvcahnt3g5zxJAGawtc-gWQ@mail.gmail.com>
 <20120810140406.GB3409@S2101-09.ap.freescale.net>
 <CAKGA1b=bcV2RKDvv=hTjfCo+uTXgcvsTPP0pM-vZYUHLMcrRvg@mail.gmail.com>
Message-ID: <CAKGA1bkBtK4iWv-0sWHXBuNYeTOpPMZE=P-JCHBNe3_uwTYftQ@mail.gmail.com>

By the way just as an example, a board with the following could be
configured on i.MX53 without touching any IOMUX settings at all
besides DDR (which would get done at boot rom time through the dcd);

* Keypad (KPP)
* 24-bit Parallel display on IPU DI0
* GPIO6&7 pins 22 through 31, GPIO4 10 through 14, and a couple others
* Parallel camera on CSI0
* NAND
* Certain configurations of Ethernet
* PATA
* SD1 and SD2
* ESAI audio
* EIM bus
* CLKIH CLKIL and CLKO clocks

With discrete power (no PMIC), bitbang I2C and SPI to control whatever
minimal peripherals you need out there, this is basically a Smarttop.
Sure, it's not as fun as using the real SPI, I2C buses and you don't
get a UART, but it's possible.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Fri, Aug 10, 2012 at 9:26 AM, Matt Sealey <matt at genesi-usa.com> wrote:
> On Fri, Aug 10, 2012 at 9:04 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> On Fri, Aug 10, 2012 at 08:36:02AM -0500, Matt Sealey wrote:
>>> Requiring it breaks the entire concept of the device tree to describe running
>>> hardware. It is not a configuration script. pinctrl should be optional
>>> - built in
>>> always, but not necessary to turn a board on if it's already configured.
>>>
>> How would kernel know if it's already configured, correctly?
>
> Trust! When we release the new U-Boot, it will be already configured,
> every pin in the schematic, every
> pin from the old kernels (not mainline, some of that was wrong),
> exactly the way it should be. There's
> nothing new with the Efika MX.
>
> If you try and boot it on the old Efika, it just won't work reliably
> for any peripheral U-Boot didn't
> already configure, but for the current version you'd get MMC, PATA,
> serial port, SPI (NOR/PMIC)
> which is all we configure in the DT right now anyway... this is only
> going to be an issue once we
> get to displays and USB (I2C isn't set up in the old one).
>
>>> What would happen if a board were designed that only used the default ALT
>>> settings on i.MX53 or so? You'd have to redefine every default IOMUX pad
>>> just to get it to boot. That's intolerable.
>>
>> Come on, even the pad configuration are all the default?  Even if that's
>> the case, yes, we still need to do it.  How do we know if firmware has
>> changed the settings or not.
>
> TRUST...
>
> Maybe you can't rely on the development boards from Freescale, but we have to
> do unit testing at every stage of operation for consumer devices. Once U-Boot
> passes all tests, why bother re-testing the exact same configuration, now done
> twice, in the kernel? I don't want to debug pad settings twice, and we shouldn't
> need to.
>
> If you really think it's necessary then fine, we'll do it.
>
> --
> Matt Sealey <matt at genesi-usa.com>
> Product Development Analyst, Genesi USA, Inc.


From will.deacon at arm.com  Fri Aug 10 10:47:30 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 15:47:30 +0100
Subject: LPAE for outer caches functiopns (was Re: [RFC 3/6] arm:
 cache-l2x0: add support for Aurora L2 cache ctrl)
In-Reply-To: <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
References: <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20120810144730.GG2066@mudshark.cambridge.arm.com>

On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
> Hi Will,

Hi Gregory,

> You will find an updated version of this patch with LPAE support. I've
> tested with and without LPAE selected.

Thanks for the patches.

> Now I get some warning during compilation: "initialization from
> incompatible pointer type [enabled by default]"
> 
> It is because the outer_cache_fns struct still embed functions with
> unsigned long for address instead of phys_addr_t. You are aware of
> it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
> use phys_addr_t instead of unsigned long in outercache functions".

Correct, I just fixed up the wrapper functions in that patch since no outer
cache implementations required >32 bits of physical address. You're the
lucky guy with the first implementation of such a controller :)

> So a first step would be to update the definitions in struct
> outer_cache_fns and also in the files using this prototype, I found
> only 4 files:
> 
> git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
> arch/arm/mm/cache-feroceon-l2.c:
> arch/arm/mm/cache-l2x0.c:
> arch/arm/mm/cache-tauros2.c:
> arch/arm/mm/cache-xsc3l2.c:
> 
> But it is not enough we also fixed the call to theses functions:
> git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
> arch/arm/include/asm/outercache.h
> arch/arm/kernel/smp.c
> arch/arm/kernel/suspend.c
> arch/arm/mach-exynos/platsmp.c
> arch/arm/mach-highbank/highbank.c
> arch/arm/mach-msm/platsmp.c
> arch/arm/mach-omap2/omap-secure.c
> arch/arm/mach-ux500/platsmp.c
> arch/arm/mm/dma-mapping.c
> arch/arm/mm/fault-armv.c
> arch/arm/plat-versatile/platsmp.c
> 
> Most of them use __pa or directly __virt_to_phys, so once the patch
> "[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
> conversion" will be merged the correct type will be used.

Which patch is this? part of the keystone series?

> Finally the last file which need some change will be
> arch/arm/mm/dma-mapping.c.
> 
> Does it sound correct?
> 
> If it does, then I can prepare a patch for it.

Yes please, that sounds like the right direction for this. We should use
phys_addr_t wherever we're dealing with physical addresses.

Cheers,

Will


From will.deacon at arm.com  Fri Aug 10 10:49:22 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 15:49:22 +0100
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <50229944.60603@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <50229422.40305@free-electrons.com>
 <50229944.60603@free-electrons.com>
Message-ID: <20120810144922.GH2066@mudshark.cambridge.arm.com>

On Wed, Aug 08, 2012 at 05:52:20PM +0100, Gregory CLEMENT wrote:
> On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
> > Yes indeed this SoC support LPAE.
> 
> Well Armada XP supports LPAE but don't use any outer cache functions, he works
> with the Aurora cache controller on 'system cache'.
> Armada 370 uses this outer cache functions but doesn't support LPAE.

Can the Armada 370 be configured to use the co-processor interface to the
L2, or does only the Armada XP support that feature? What happens if you
build a single zImage supporting both of the SoCs?

Will


From gregory.clement at free-electrons.com  Fri Aug 10 11:02:50 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 10 Aug 2012 17:02:50 +0200
Subject: LPAE for outer caches functiopns (was Re: [RFC 3/6] arm:
 cache-l2x0: add support for Aurora L2 cache ctrl)
In-Reply-To: <20120810144730.GG2066@mudshark.cambridge.arm.com>
References: <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
 <20120810144730.GG2066@mudshark.cambridge.arm.com>
Message-ID: <5025229A.2090007@free-electrons.com>

On 08/10/2012 04:47 PM, Will Deacon wrote:
> On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
>> Hi Will,
> 
> Hi Gregory,
> 
>> You will find an updated version of this patch with LPAE support. I've
>> tested with and without LPAE selected.

Just a rectification, in fact I managed to build in both case, and to run
only without LPAE support. I didn't have the support for LPAE yet. I was
surprised that it worked out of the box, but in fact I tested the wrong
kernel! I realized this this morning.

> 
> Thanks for the patches.
> 
>> Now I get some warning during compilation: "initialization from
>> incompatible pointer type [enabled by default]"
>>
>> It is because the outer_cache_fns struct still embed functions with
>> unsigned long for address instead of phys_addr_t. You are aware of
>> it, as you started to work on it with your patch "ARM: 6671/1: LPAE:
>> use phys_addr_t instead of unsigned long in outercache functions".
> 
> Correct, I just fixed up the wrapper functions in that patch since no outer
> cache implementations required >32 bits of physical address. You're the
> lucky guy with the first implementation of such a controller :)
> 
>> So a first step would be to update the definitions in struct
>> outer_cache_fns and also in the files using this prototype, I found
>> only 4 files:
>>
>> git grep -w  outer_.*_range arch/arm | grep = | cut -f 1| uniq
>> arch/arm/mm/cache-feroceon-l2.c:
>> arch/arm/mm/cache-l2x0.c:
>> arch/arm/mm/cache-tauros2.c:
>> arch/arm/mm/cache-xsc3l2.c:
>>
>> But it is not enough we also fixed the call to theses functions:
>> git grep -w  outer_.*_range arch/arm | grep -v = | cut -f 1 -d: | uniq
>> arch/arm/include/asm/outercache.h
>> arch/arm/kernel/smp.c
>> arch/arm/kernel/suspend.c
>> arch/arm/mach-exynos/platsmp.c
>> arch/arm/mach-highbank/highbank.c
>> arch/arm/mach-msm/platsmp.c
>> arch/arm/mach-omap2/omap-secure.c
>> arch/arm/mach-ux500/platsmp.c
>> arch/arm/mm/dma-mapping.c
>> arch/arm/mm/fault-armv.c
>> arch/arm/plat-versatile/platsmp.c
>>
>> Most of them use __pa or directly __virt_to_phys, so once the patch
>> "[PATCH 03/22] ARM: LPAE: use phys_addr_t on virt <--> phys
>> conversion" will be merged the correct type will be used.
> 
> Which patch is this? part of the keystone series?

yes it is!

> 
>> Finally the last file which need some change will be
>> arch/arm/mm/dma-mapping.c.
>>
>> Does it sound correct?
>>
>> If it does, then I can prepare a patch for it.
> 
> Yes please, that sounds like the right direction for this. We should use
> phys_addr_t wherever we're dealing with physical addresses.
> 
> Cheers,
> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Fri Aug 10 11:13:41 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 10 Aug 2012 17:13:41 +0200
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <20120810144922.GH2066@mudshark.cambridge.arm.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <50229422.40305@free-electrons.com> <50229944.60603@free-electrons.com>
 <20120810144922.GH2066@mudshark.cambridge.arm.com>
Message-ID: <50252525.8050602@free-electrons.com>

On 08/10/2012 04:49 PM, Will Deacon wrote:
> On Wed, Aug 08, 2012 at 05:52:20PM +0100, Gregory CLEMENT wrote:
>> On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
>>> Yes indeed this SoC support LPAE.
>>
>> Well Armada XP supports LPAE but don't use any outer cache functions, he works
>> with the Aurora cache controller on 'system cache'.
>> Armada 370 uses this outer cache functions but doesn't support LPAE.
> 
> Can the Armada 370 be configured to use the co-processor interface to the
> L2, or does only the Armada XP support that feature? What happens if you
> build a single zImage supporting both of the SoCs?

About L2 cache we already use the same kernel on Armada 370 and Armada XP
and the differences are in the device tree.

Now if I understood correctly what the LPAE involved, I guess we can't have
a kernel with LAPE running on Armada 370.

> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From jonathan.austin at arm.com  Fri Aug 10 11:14:05 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 10 Aug 2012 16:14:05 +0100
Subject: Why the region area don't decrease 1 in function
 sanity_check_meminfo?
In-Reply-To: <CAKvkGKeqzAiqRAj+H+E-eoN9SOOMP-aMhUJYmUb0UK4ei=jouA@mail.gmail.com>
References: <CAKvkGKeqzAiqRAj+H+E-eoN9SOOMP-aMhUJYmUb0UK4ei=jouA@mail.gmail.com>
Message-ID: <5025253D.3010007@arm.com>

On 24/07/12 11:54, ??? wrote:

> I don't known why the memory region have not decrease 1, i think it
> should be decreased(like this , (__va(bank->start + bank->size
> -1))because in sparse memory system,  this address bank->start +
> bank->size is belong to another bank, so this method is not correctly.

I think you're right - we should have the '- 1' in there, although I 
don't think there currently exist any situations where this will cause
us grief. Here's a patch for correctness anyway...

> Please indicate whether my understanding is correct.
 

As far as I can see in all existing situations, the worst effect of this
will be truncating by a single byte a bank that doesn't actually need
truncating.

As you said in your following email, we would get trouble with this if
using SPARSEMEM in a situation where the physical to virtual address
conversion is not monotonic increasing.

Jonny

---8<---
From: Jonathan Austin <jonathan.austin at arm.com>
Date: Thu, 9 Aug 2012 15:59:16 +0100
Subject: [PATCH] arm: mm: Fix vmalloc overlap check for !HIGHMEM

With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
partially overlap the vmalloc region. The check for partial overlap checks
__va(bank->start + bank->size) > vmalloc_min, but the last address of the
bank is (bank->start + bank->size -1).

This doesn't cause serious issues for existing platforms, except to
truncate by a single byte a bank that doesn't actually need truncating if
it happens to finish at vmalloc_min -1.

However, theoretically, if using using SPARSEMEM in a situation where the
physical to virtual address conversion is not monotonic increasing, the
incorrect test could result in a bank not being truncated when it should be.

Reported-by: ??? (Steve) <zhanzhenbo at gmail.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---
 arch/arm/mm/mmu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d045..29f7084 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -961,8 +961,8 @@ void __init sanity_check_meminfo(void)
                 * Check whether this memory bank would partially overlap
                 * the vmalloc area.
                 */
-               if (__va(bank->start + bank->size) > vmalloc_min ||
-                   __va(bank->start + bank->size) < __va(bank->start)) {
+               if (__va(bank->start + bank->size - 1) > vmalloc_min ||
+                   __va(bank->start + bank->size - 1) < __va(bank->start)) {
                        unsigned long newsize = vmalloc_min - __va(bank->start);
                        printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
                               "to -%.8llx (vmalloc region overlap).\n",



From will.deacon at arm.com  Fri Aug 10 11:20:36 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 16:20:36 +0100
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <50252525.8050602@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <50229422.40305@free-electrons.com>
 <50229944.60603@free-electrons.com>
 <20120810144922.GH2066@mudshark.cambridge.arm.com>
 <50252525.8050602@free-electrons.com>
Message-ID: <20120810152036.GK2066@mudshark.cambridge.arm.com>

On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
> On 08/10/2012 04:49 PM, Will Deacon wrote:
> > Can the Armada 370 be configured to use the co-processor interface to the
> > L2, or does only the Armada XP support that feature? What happens if you
> > build a single zImage supporting both of the SoCs?
> 
> About L2 cache we already use the same kernel on Armada 370 and Armada XP
> and the differences are in the device tree.

Right, but I wonder whether you can end up using both the outer_cache
functions *and* the co-processor interface on the Armada XP by accident.
Ideally, we'd just use the co-processor interface on all platforms and
ignore the memory-mapped one. Is that possible on the 370?

> Now if I understood correctly what the LPAE involved, I guess we can't have
> a kernel with LAPE running on Armada 370.

Indeed, but you could still run with 2-level page tables on both SoCs (with
less memory on the XP).

Will


From vaibhav.bedia at ti.com  Fri Aug 10 11:21:57 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Fri, 10 Aug 2012 15:21:57 +0000
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433EB34624@DBDE01.ent.ti.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
 <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1208081411010.6819@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB34624@DBDE01.ent.ti.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D121433EB375A9@DBDE01.ent.ti.com>

Hi Paul,

[...]

> > > On Wed, Aug 08, 2012 at 19:35:50, Paul Walmsley wrote:
> > >
> > > > It doesn't seem to me that this would necessarily always be an error.  
> > > > Suppose some init code to create cpsw devices is running on an OMAP3430.  
> > > > Then a omap_hwmod_for_each_by_class() that doesn't locate anything 
> > > > wouldn't be an error, right?
> > > 
> > > Well, I think a failed lookup operation will be a bit expensive since it
> > > iterates over the whole list of registered hwmods and hence put in the
> > > pr_err().
> > 
> > If performance is a serious problem there, we can maintain a list of hwmod 
> > pointers inside each struct omap_hwmod_class, updated when the hwmods are 
> > registered.  But as far as I know, performance hasn't been an issue here 
> > yet.  If performance is the real motivation, I'd rather see an 
> > implementation of per-class lists as described above.
> > 
> 
> Ok. I'll try to do some profiling using a timer to see how much time we
> spend over here. On AM335x there are 2 such lookups, one for the dma
> and one for the mcbsp. I could get this done today but will get to it
> tomorrow. Based on how this goes I'll try out the omap_hwmod_class list
> like you suggested.
> 

I used a dmtimer clocked at 24MHz (41ns resolution) to get the time
spent in the lookup. There are two failed lookups that happen in AM335x
and following are the times taken

Run1
Lookup for dma - 435 cycles -> 17.835 usecs
Lookup for mcbsp - 83 cycles -> 3.4 usecs

Run2
Lookup for dma - 503 cycles -> 20.623 usecs
Lookup for mcbsp - 90 cycles -> 3.69 usescs

Run3
Lookup for dma - 375 cycles -> 15.375 usecs
Lookup for mcbsp - 91 cycles -> 3.731 usecs

The 2nd lookup happens immediately after the 1st one so probably
the difference is coming due to the data sitting in the cache?

The average times don't look too high to me but I guess you already
knew that ;)

If you are ok with a pr_debug() instead of a pr_err() I'll resubmit
the patch with this change.

Regards,
Vaibhav B.


From gregory.clement at free-electrons.com  Fri Aug 10 11:31:46 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 10 Aug 2012 17:31:46 +0200
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <20120810152036.GK2066@mudshark.cambridge.arm.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>
 <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <50229422.40305@free-electrons.com> <50229944.60603@free-electrons.com>
 <20120810144922.GH2066@mudshark.cambridge.arm.com>
 <50252525.8050602@free-electrons.com>
 <20120810152036.GK2066@mudshark.cambridge.arm.com>
Message-ID: <50252962.5090107@free-electrons.com>

On 08/10/2012 05:20 PM, Will Deacon wrote:
> On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
>> On 08/10/2012 04:49 PM, Will Deacon wrote:
>>> Can the Armada 370 be configured to use the co-processor interface to the
>>> L2, or does only the Armada XP support that feature? What happens if you
>>> build a single zImage supporting both of the SoCs?
>>
>> About L2 cache we already use the same kernel on Armada 370 and Armada XP
>> and the differences are in the device tree.
> 
> Right, but I wonder whether you can end up using both the outer_cache
> functions *and* the co-processor interface on the Armada XP by accident.

Well from what I know it should be possible to have both in the same time.
However we implement the support in a way that you won't have both in the
same time: if we use the "system cache" mode then we don't use any outer_cache
functions.

> Ideally, we'd just use the co-processor interface on all platforms and
> ignore the memory-mapped one. Is that possible on the 370?
> 
The 370 can't use the "system cache" mode (ie the co-processor).


__________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From linux at arm.linux.org.uk  Fri Aug 10 11:37:05 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 10 Aug 2012 16:37:05 +0100
Subject: Why the region area don't decrease 1 in function
 sanity_check_meminfo?
In-Reply-To: <5025253D.3010007@arm.com>
References: <CAKvkGKeqzAiqRAj+H+E-eoN9SOOMP-aMhUJYmUb0UK4ei=jouA@mail.gmail.com>
 <5025253D.3010007@arm.com>
Message-ID: <20120810153705.GZ18957@n2100.arm.linux.org.uk>

On Fri, Aug 10, 2012 at 04:14:05PM +0100, Jonathan Austin wrote:
> From: Jonathan Austin <jonathan.austin at arm.com>
> Date: Thu, 9 Aug 2012 15:59:16 +0100
> Subject: [PATCH] arm: mm: Fix vmalloc overlap check for !HIGHMEM
> 
> With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
> partially overlap the vmalloc region. The check for partial overlap checks
> __va(bank->start + bank->size) > vmalloc_min, but the last address of the
> bank is (bank->start + bank->size -1).

Erm.

Let's say you have a bank at 0x80000000, which maps to 0xc0000000 virtual.
This is 512MB in size (so it's last byte address is 0x9fffffff).  That
places it at at 0xdfffffff.  Now, let's say vmalloc_min is 0xe0000000.

"bank->start + bank->size" would be 0xa0000000, right ?

So, "__va(bank->start + bank->size)" would be 0xe0000000.

And "0xe0000000 > vmalloc_min" would be false.

> However, theoretically, if using using SPARSEMEM in a situation where the
> physical to virtual address conversion is not monotonic increasing, the
> incorrect test could result in a bank not being truncated when it should be.

Right, so what you're actually talking about is a non-linear translation
by __va() and friends.  In that case, what you actually need is:

	(__va(bank->start + bank->size - 1) + 1) > vmalloc_min
or
	__va(bank->start + bank->size - 1) >= vmalloc_min

and not

	__va(bank->start + bank->size - 1) > vmalloc_min


From peter.ujfalusi at ti.com  Fri Aug 10 11:39:11 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri, 10 Aug 2012 18:39:11 +0300
Subject: [alsa-devel] [PATCH 08/11] ARM: OMAP3: Remove callback for McBSP
 sidetone ICLK workaround
In-Reply-To: <502505D4.2030308@bitmer.com>
References: <1344417101-5015-1-git-send-email-peter.ujfalusi@ti.com>
 <1344417101-5015-9-git-send-email-peter.ujfalusi@ti.com>
 <502268B1.9040506@bitmer.com> <50227104.3040506@ti.com>
 <502505D4.2030308@bitmer.com>
Message-ID: <50252B1F.2040107@ti.com>

Hi Jarkko,

On 08/10/2012 04:00 PM, Jarkko Nikula wrote:
> I got some odd current consumption results from Beagle to really compare
> different kernel versions but I was able get sensible results from N900.

I still use my n900 as a main phone so I can not really hack on it :(

> I tested your set on top of 196973c of sound.git.
> 
> First consumption when using threshold based transfer has remained the
> same between 2.6.38-3.6.0-rc1 (wau!).

Cool!

> Active sidetone under "arecord -f
> dat >/dev/null |aplay -f dat /dev/zero" test increases consumption from
> plain playback about 17 mA in 3.4 and 3.6.0-rc1.
> 
> With your set applied consumption increases 28 mA when the sidetone is
> active (i.e. +11 mA higher than on top of 196973c). Plain threshold
> based playback remains still the same.

Oh. 11mA is huge... Really strange. I would expected smaller (actually zero)
difference since in essence both workaround should be doing the same.
Only if the OMAP pm core making different decisions runtime when it see that
the no-idle is selected in the SYSCONFIG register of McBSP2. But the
autogating of clocks should work without SW.

So it seams that we need to do this down at PRCM level?

>> I'm doing the same test on BeagleBoard, but this thing does not want to hit
>> retention despite all the effort :(
>>
> Could it be display subsystem which keeps it active? At least on N900 I
> need to get DSS drivers activated in order to be able to blank the
> display after bootloader and thus be able to reach the retention idle.

I tried that as well, but nothing helps. It must be something else which I
have overlooked...

-- 
P?ter


From marex at denx.de  Fri Aug 10 11:04:44 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 10 Aug 2012 17:04:44 +0200
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <CAMiH66FAVVPLZ9hCyRcNCm1Le2JrCc+55CUw7UCtPjw+31w5gw@mail.gmail.com>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
 <201208101325.23075.marex@denx.de>
 <CAMiH66FAVVPLZ9hCyRcNCm1Le2JrCc+55CUw7UCtPjw+31w5gw@mail.gmail.com>
Message-ID: <201208101704.44984.marex@denx.de>

Dear Huang Shijie,

> On Fri, Aug 10, 2012 at 7:25 AM, Marek Vasut <marex at denx.de> wrote:
> > Dear Huang Shijie,
> > 
> >> Add NAND write verify support in gpmi-nand driver.
> >> 
> >> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> >> ---
> >> 
> >>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   17 +++++++++++++++++
> >>  1 files changed, 17 insertions(+), 0 deletions(-)
> >> 
> >> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> >> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..6394483 100644
> >> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> >> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> >> @@ -1488,6 +1488,22 @@ static int gpmi_set_geometry(struct
> >> gpmi_nand_data *this) return gpmi_alloc_dma_buffer(this);
> >> 
> >>  }
> >> 
> >> +#define MAX_PAGESIZE 8192
> > 
> > Use NAND_MAX_PAGESIZE, see include/linux/mtd/nand.h .
> > 
> >> +static uint8_t verify_buf[MAX_PAGESIZE];
> 
> ok, thanks.
> 
> > What will happen when you have two NANDs attached to GPMI controller and
> > they hit this place both at once? Race condition, causing this function
> > to fail for both?
> 
> Even there are two nand chips, there is only one gpmi controller.

For now ... yes.

> And the current gpmi-nand does not support two nands now.
> does the race occur with only one nand chip?

With one chip and one GPMI controller, no ... but that's no reason to introduce 
crappy and error prone code!

> > Possibly devm_kmalloc() such buffer per-controller?
> > 
> >> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
> >> int len) +{
> >> +     struct nand_chip *nand = mtd->priv;
> >> +     int ret;
> >> +
> >> +     ret = gpmi_ecc_read_page(mtd, nand, verify_buf, 0, 0);
> > 
> > mtd->chip.ecc.read_page() ?
> 
> In actually, they are the same.

They are, but if you rename the function, this is one less place to care for.

> 
> Best Regards
> Huang Shijie

Best regards,
Marek Vasut


From paul at pwsan.com  Fri Aug 10 11:49:37 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 10 Aug 2012 09:49:37 -0600 (MDT)
Subject: [PATCH 1/1] ARM: OMAP2+: hwmod: Print an error message if no
 match exists for a hwmod class
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433EB375A9@DBDE01.ent.ti.com>
References: <1344422117-20707-1-git-send-email-vaibhav.bedia@ti.com>
 <alpine.DEB.2.00.1208080803560.5447@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB32ABA@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1208081411010.6819@utopia.booyaka.com>
 <B5906170F1614E41A8A28DE3B8D121433EB34624@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D121433EB375A9@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1208100946340.11420@utopia.booyaka.com>

Hello Vaibhav

On Fri, 10 Aug 2012, Bedia, Vaibhav wrote:

> > Ok. I'll try to do some profiling using a timer to see how much time we
> > spend over here. On AM335x there are 2 such lookups, one for the dma
> > and one for the mcbsp. I could get this done today but will get to it
> > tomorrow. Based on how this goes I'll try out the omap_hwmod_class list
> > like you suggested.
> 
> I used a dmtimer clocked at 24MHz (41ns resolution) to get the time
> spent in the lookup. There are two failed lookups that happen in AM335x
> and following are the times taken
> 
> Run1
> Lookup for dma - 435 cycles -> 17.835 usecs
> Lookup for mcbsp - 83 cycles -> 3.4 usecs
> 
> Run2
> Lookup for dma - 503 cycles -> 20.623 usecs
> Lookup for mcbsp - 90 cycles -> 3.69 usescs
> 
> Run3
> Lookup for dma - 375 cycles -> 15.375 usecs
> Lookup for mcbsp - 91 cycles -> 3.731 usecs
> 
> The 2nd lookup happens immediately after the 1st one so probably
> the difference is coming due to the data sitting in the cache?
> 
> The average times don't look too high to me but I guess you already
> knew that ;)
> 
> If you are ok with a pr_debug() instead of a pr_err() I'll resubmit
> the patch with this change.

Well I'd much rather see a patch that maintains a list of hwmods 
pertaining to each class.  That would solve the performance issue at 
fairly minimal cost (especially if those lists were freed after kernel 
init). 

It sounds like the basic difference in opinion is about whether an 
omap_hwmod_for_each_by_class() that doesn't find anything is an error 
condition or not.  My sense is that it is not.


- Paul


From will.deacon at arm.com  Fri Aug 10 11:51:28 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 16:51:28 +0100
Subject: Preliminary topic proposals for the ARM mini-summit
Message-ID: <20120810155128.GM2066@mudshark.cambridge.arm.com>

Hello,

By now, those of you on CC should have received your invitation codes for
the ARM mini-summit in a couple of weeks time. If not, please contact me
separately and I'll look into it [Magnus -- I'm aware you haven't
received anything yet, hopefully this will be fixed soon].

The invitation email was slightly misleading as it only referred to Tuesday
28 August, when in fact the mini-summit will be held on *both* Monday 27
and Tuesday 28. We will run topics in the morning (and allow an hour in
the afternoon for overflow discussion) and dedicate the rest of the time
to hacking. Initial topic proposals are:


Monday
------

Secure monitor APIs
Virtualisation (kvm/xen)
DMA mapping
Stable platform deprecation

Tuesday
-------

Single zImage
AArch64
big.LITTLE
DMA engine
arm-soc process review


This list of topics already fills the allocated time, but if there is
sufficient interest in discussing additional items, we can try to
prioritise.

We look forward to seeing you in San Diego!

Will [and the rest of the organisation group]


From haojian.zhuang at gmail.com  Fri Aug 10 11:52:07 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 10 Aug 2012 23:52:07 +0800
Subject: [PATCH] ARM: mmp: implement DEBUG_LL port choice
Message-ID: <1344613927-8238-1-git-send-email-haojian.zhuang@gmail.com>

DEBUG_LL port must be choiced in arch-mmp. DEBUG_LL port should be
UART2 in TTC DKB. And it should be UART3 in brownstone.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/Kconfig.debug                       |   14 ++++++++++++++
 arch/arm/mach-mmp/include/mach/debug-macro.S |   12 ++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f15f82b..0919191 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -224,6 +224,20 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX6Q UART4.
 
+	config DEBUG_MMP_UART2
+		bool "Kernel low-level debugging message via MMP UART2"
+		depends on ARCH_MMP
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on MMP UART2.
+
+	config DEBUG_MMP_UART3
+		bool "Kernel low-level debugging message via MMP UART3"
+		depends on ARCH_MMP
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on MMP UART3.
+
 	config DEBUG_MSM_UART1
 		bool "Kernel low-level debugging messages via MSM UART1"
 		depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index b6f14d2..5c3cc29 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -9,13 +9,21 @@
  * published by the Free Software Foundation.
  */
 
+#if defined(CONFIG_DEBUG_MMP_UART2)
+#define MMP_UART_OFFSET	0x00017000
+#elif defined(CONFIG_DEBUG_MMP_UART3)
+#define MMP_UART_OFFSET	0x00018000
+#else
+#error "Select uart for DEBUG_LL"
+#endif
+
 #include <mach/addr-map.h>
 
 		.macro	addruart, rp, rv, tmp
 		ldr	\rp, =APB_PHYS_BASE		@ physical
 		ldr	\rv, =APB_VIRT_BASE		@ virtual
-		orr	\rp, \rp, #0x00017000
-		orr	\rv, \rv, #0x00017000
+		orr	\rp, \rp, #MMP_UART_OFFSET
+		orr	\rv, \rv, #MMP_UART_OFFSET
 		.endm
 
 #define UART_SHIFT	2
-- 
1.7.9.5



From nico at fluxnic.net  Fri Aug 10 12:10:42 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 10 Aug 2012 12:10:42 -0400 (EDT)
Subject: [PATCH] mutex: place lock in contended state after fastpath_lock
 failure
In-Reply-To: <1344608529-2377-1-git-send-email-will.deacon@arm.com>
References: <1344608529-2377-1-git-send-email-will.deacon@arm.com>
Message-ID: <alpine.LFD.2.02.1208101208270.5231@xanadu.home>

On Fri, 10 Aug 2012, Will Deacon wrote:

> ARM recently moved to asm-generic/mutex-xchg.h for its mutex
> implementation after the previous implementation was found to be missing
> some crucial memory barriers. However, this has revealed some problems
> running hackbench on SMP platforms due to the way in which the
> MUTEX_SPIN_ON_OWNER code operates.
> 
> The symptoms are that a bunch of hackbench tasks are left waiting on an
> unlocked mutex and therefore never get woken up to claim it. This boils
> down to the following sequence of events:
> 
>         Task A        Task B        Task C        Lock value
> 0                                                     1
> 1       lock()                                        0
> 2                     lock()                          0
> 3                     spin(A)                         0
> 4       unlock()                                      1
> 5                                   lock()            0
> 6                     cmpxchg(1,0)                    0
> 7                     contended()                    -1
> 8       lock()                                        0
> 9       spin(C)                                       0
> 10                                  unlock()          1
> 11      cmpxchg(1,0)                                  0
> 12      unlock()                                      1
> 
> At this point, the lock is unlocked, but Task B is in an uninterruptible
> sleep with nobody to wake it up.
> 
> This patch fixes the problem by ensuring we put the lock into the
> contended state if we fail to acquire it on the fastpath, ensuring that
> any blocked waiters are woken up when the mutex is released.
> 
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Chris Mason <chris.mason at fusionio.com>
> Cc: Ingo Molnar <mingo at elte.hu>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Nicolas Pitre <nico at linaro.org>

> ---
> 
> Nico: Can I add your S-o-B to this please? Also, preliminary benchmarks
>       are now showing a slight performance improvement on A15 if I use
>       the -dec variant rather than -xchg. I'll follow up with a patch
>       once I've got more numbers.

Good.


> 
>  include/asm-generic/mutex-xchg.h |   11 +++++++++--
>  1 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> index 580a6d3..c04e0db 100644
> --- a/include/asm-generic/mutex-xchg.h
> +++ b/include/asm-generic/mutex-xchg.h
> @@ -26,7 +26,13 @@ static inline void
>  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
>  {
>  	if (unlikely(atomic_xchg(count, 0) != 1))
> -		fail_fn(count);
> +		/*
> +		 * We failed to acquire the lock, so mark it contended
> +		 * to ensure that any waiting tasks are woken up by the
> +		 * unlock slow path.
> +		 */
> +		if (likely(atomic_xchg(count, -1) != 1))
> +			fail_fn(count);
>  }
>  
>  /**
> @@ -43,7 +49,8 @@ static inline int
>  __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
>  {
>  	if (unlikely(atomic_xchg(count, 0) != 1))
> -		return fail_fn(count);
> +		if (likely(atomic_xchg(count, -1) != 1))
> +			return fail_fn(count);
>  	return 0;
>  }
>  
> -- 
> 1.7.4.1
> 


From gregkh at linuxfoundation.org  Fri Aug 10 12:10:46 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Fri, 10 Aug 2012 09:10:46 -0700
Subject: [PATCH 08/14] tty: atmel_serial: add pinctrl support
In-Reply-To: <1344603731-32667-8-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-8-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120810161046.GA2510@kroah.com>

On Fri, Aug 10, 2012 at 03:02:05PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-serial at vger.kernel.org
> ---
> Hi Greg,
> 
> 	if you don't mind I would like to apply with the rest of the pinctrl
> 	patch series

No objection from me:
	Acked-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>



From cov at codeaurora.org  Fri Aug 10 12:24:33 2012
From: cov at codeaurora.org (Christopher Covington)
Date: Fri, 10 Aug 2012 12:24:33 -0400
Subject: [36/36] AArch64: MAINTAINERS update
In-Reply-To: <1341608777-12982-37-git-send-email-catalin.marinas@arm.com>
References: <1341608777-12982-37-git-send-email-catalin.marinas@arm.com>
Message-ID: <502535C1.8060907@codeaurora.org>

Hi Catalin,

On 07/06/2012 05:06 PM, Catalin Marinas wrote:
> This patch updates the MAINTAINERS file for the AArch64 Linux kernel
> port.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> 
> ---
> MAINTAINERS |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index eb22272..50699f5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -192,6 +192,12 @@ S:	Supported
>  F:	Documentation/scsi/aacraid.txt
>  F:	drivers/scsi/aacraid/
>  
> +AARCH64 ARCHITECTURE
> +M:	Catalin Marinas <catalin.marinas at arm.com>
> +L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)

I think it's important to include the Linux ARM kernel mailing list as a recipient for these changes and I hope you'll do so in all future revisions of the 64-bit patches.

Thanks,
Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum


From swarren at wwwdotorg.org  Fri Aug 10 12:48:50 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 10:48:50 -0600
Subject: [PATCH] ARM: tegra: use IO_ADDRESS for getting virtual address
In-Reply-To: <1344603782-2541-1-git-send-email-ldewangan@nvidia.com>
References: <1344603782-2541-1-git-send-email-ldewangan@nvidia.com>
Message-ID: <50253B72.5030209@wwwdotorg.org>

On 08/10/2012 07:03 AM, Laxman Dewangan wrote:
> Use macro IO_ADDRESS for getting virtual address of
> corresponding physical address to make the consistency
> with rest of Tegra code-base.
> This macro calls the IO_TO_VIRT() which is defined in
> arch/arm/mach-tegra/include/mach/iomap.h

Thanks, applied to Tegra's for-3.7/fixes.


From swarren at wwwdotorg.org  Fri Aug 10 12:50:27 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 10:50:27 -0600
Subject: [PATCH] ARM: dt: tegra: paz00: add regulators
In-Reply-To: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>
References: <1343932593-999-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <50253BD3.2010103@wwwdotorg.org>

On 08/02/2012 12:36 PM, Stephen Warren wrote:
> The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this.

Applied to for-3.7/dt.


From swarren at wwwdotorg.org  Fri Aug 10 12:51:03 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 10:51:03 -0600
Subject: [PATCH V3] ARM: dt: tegra: seaboard: add regulators
In-Reply-To: <1344017330-29306-1-git-send-email-swarren@wwwdotorg.org>
References: <1344017330-29306-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <50253BF7.1030000@wwwdotorg.org>

On 08/03/2012 12:08 PM, Stephen Warren wrote:
> Seaboard uses a TPS6586x regulator. Instantiate this, and hook up a
> couple of fixed GPIO-controlled regulators too.

Applied to for-3.7/dt.


From swarren at wwwdotorg.org  Fri Aug 10 12:51:11 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 10:51:11 -0600
Subject: [PATCH V3] ARM: dt: tegra: ventana: add regulators
In-Reply-To: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
References: <1344017356-29352-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <50253BFF.8070606@wwwdotorg.org>

On 08/03/2012 12:09 PM, Stephen Warren wrote:
> Ventana uses a TPS6586x regulator. Instantiate this, and hook up a
> couple of fixed GPIO-controlled regulators too.

Applied to for-3.7/dt.



From festevam at gmail.com  Fri Aug 10 13:15:28 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 10 Aug 2012 14:15:28 -0300
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208101704.44984.marex@denx.de>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
 <201208101325.23075.marex@denx.de>
 <CAMiH66FAVVPLZ9hCyRcNCm1Le2JrCc+55CUw7UCtPjw+31w5gw@mail.gmail.com>
 <201208101704.44984.marex@denx.de>
Message-ID: <CAOMZO5C2qUNPCCbc4jW5+4HZuuhPQ=Lid6UsfgBXNpr44q2p2A@mail.gmail.com>

Hi Marek,

On Fri, Aug 10, 2012 at 12:04 PM, Marek Vasut <marex at denx.de> wrote:

>> Even there are two nand chips, there is only one gpmi controller.
>
> For now ... yes.

Does this look better?

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand
index 8c0d2f0..5262ef3 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1533,6 +1533,21 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
        gpmi_free_dma_buffer(this);
 }

+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+       struct nand_chip *nand = mtd->priv;
+       struct gpmi_nand_data *data = container_of(mtd, struct gpmi_nand_data,
+                                                                  mtd);
+       int ret;
+
+       ret = gpmi_ecc_read_page(mtd, nand, data->verify_buf, 0, 0);
+       if (ret)
+               return -EFAULT;
+       if (memcmp(buf, data->verify_buf, len))
+               return -EFAULT;
+       return 0;
+}
+
 static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 {
        struct mtd_info  *mtd = &this->mtd;
@@ -1555,6 +1570,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *
        chip->dev_ready         = gpmi_dev_ready;
        chip->read_byte         = gpmi_read_byte;
        chip->read_buf          = gpmi_read_buf;
+       chip->verify_buf        = gpmi_verify_buf;
        chip->write_buf         = gpmi_write_buf;
        chip->ecc.read_page     = gpmi_ecc_read_page;
        chip->ecc.write_page    = gpmi_ecc_write_page;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand
index 1547a60..cd9bdf7 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -148,6 +148,7 @@ struct gpmi_nand_data {
        /* General-use Variables */
        int                     current_chip;
        unsigned int            command_length;
+       uint8_t                 verify_buf[NAND_MAX_PAGESIZE];

        /* passed from upper layer */
        uint8_t                 *upper_buf;

and then I can also send this separate change to allow multi-instances:

@@ -1630,7 +1646,7 @@ static int __devinit gpmi_nand_probe(struct platform_devic
                return -ENOMEM;
        }

-       this = kzalloc(sizeof(*this), GFP_KERNEL);
+       this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
        if (!this) {
                pr_err("Failed to allocate per-device memory\n");
                return -ENOMEM;


From will.deacon at arm.com  Fri Aug 10 13:36:31 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:31 +0100
Subject: [PATCH 5/9] ARM: perf: remove mysterious compiler barrier
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-6-git-send-email-will.deacon@arm.com>

There's a rather strange compiler barrier in the PMU disabling code
which was presumably placed there by aliens. There's no valid reason for
the barrier and one can only suspect that it's up to no good.

This patch removes it before it has a chance to spread.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/perf_event.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 1ac1531..22ed512 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -223,7 +223,6 @@ armpmu_stop(struct perf_event *event, int flags)
 	 */
 	if (!(hwc->state & PERF_HES_STOPPED)) {
 		armpmu->disable(hwc, hwc->idx);
-		barrier(); /* why? */
 		armpmu_event_update(event, hwc, hwc->idx);
 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 	}
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:26 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:26 +0100
Subject: [PATCH 0/9] ARM perf updates for 3.7
Message-ID: <1344620195-22372-1-git-send-email-will.deacon@arm.com>

Hello,

This patch series contains the ARM perf updates I'd like to push for 3.7
Most of the code is cleanup in preparation for big.LITTLE PMU support,
where we will need to support different types of CPU PMU on the same SoC.

The PMU probing has changed so that we try to identify the PMU using its
DT binding before falling back to probing the current core. The unused
PMU registration mechanism is also removed and platforms registering
the device have been updated accordingly.

Given that this touches a few platforms, I anticipate sending it via
arm-soc.

All feedback welcome,

Will


Jon Hunter (1):
  ARM: PMU: Add runtime PM Support

Sudeep KarkadaNagesha (2):
  ARM: pmu: remove arm_pmu_type enumeration
  ARM: perf: move irq registration into pmu implementation

Will Deacon (6):
  ARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs
  ARM: pmu: remove unused reservation mechanism
  ARM: perf: remove mysterious compiler barrier
  ARM: perf: probe devicetree in preference to current CPU
  ARM: perf: prepare for moving CPU PMU code into separate file
  ARM: perf: move CPU-specific PMU handling code into separate file

 Documentation/devicetree/bindings/arm/pmu.txt |    4 +
 MAINTAINERS                                   |    1 -
 arch/arm/Kconfig                              |    8 +-
 arch/arm/include/asm/perf_event.h             |    9 +-
 arch/arm/include/asm/pmu.h                    |   77 ++----
 arch/arm/kernel/Makefile                      |    3 +-
 arch/arm/kernel/perf_event.c                  |  347 ++++---------------------
 arch/arm/kernel/perf_event_cpu.c              |  295 +++++++++++++++++++++
 arch/arm/kernel/perf_event_v6.c               |   12 +-
 arch/arm/kernel/perf_event_v7.c               |   32 ++--
 arch/arm/kernel/perf_event_xscale.c           |   10 +-
 arch/arm/kernel/pmu.c                         |   36 ---
 arch/arm/mach-bcmring/arch.c                  |    3 +-
 arch/arm/mach-omap2/devices.c                 |    3 +-
 arch/arm/mach-pxa/devices.c                   |    3 +-
 arch/arm/mach-realview/realview_eb.c          |    3 +-
 arch/arm/mach-realview/realview_pb1176.c      |    3 +-
 arch/arm/mach-realview/realview_pb11mp.c      |    3 +-
 arch/arm/mach-realview/realview_pba8.c        |    3 +-
 arch/arm/mach-realview/realview_pbx.c         |    3 +-
 arch/arm/mach-tegra/devices.c                 |    3 +-
 arch/arm/mach-ux500/cpu-db8500.c              |    3 +-
 arch/arm/mach-vexpress/ct-ca9x4.c             |    3 +-
 arch/arm/plat-iop/pmu.c                       |    3 +-
 arch/arm/plat-samsung/devs.c                  |    3 +-
 25 files changed, 424 insertions(+), 449 deletions(-)
 create mode 100644 arch/arm/kernel/perf_event_cpu.c
 delete mode 100644 arch/arm/kernel/pmu.c

-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:28 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:28 +0100
Subject: [PATCH 2/9] ARM: perf: add devicetree bindings for 11MPcore, A5,
 A7 and A15 PMUs
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-3-git-send-email-will.deacon@arm.com>

This patch adds separate devicetree bindings for 11MPcore and
Cortex-{A5,A7,A15} PMUs in preparation for improved devicetree parsing
in the ARM perf-event CPU PMU driver.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 Documentation/devicetree/bindings/arm/pmu.txt |    4 ++++
 arch/arm/kernel/perf_event.c                  |    6 +++++-
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 1c044eb..343781b 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,8 +7,12 @@ representation in the device tree should be done as under:-
 Required properties:
 
 - compatible : should be one of
+	"arm,cortex-a15-pmu"
 	"arm,cortex-a9-pmu"
 	"arm,cortex-a8-pmu"
+	"arm,cortex-a7-pmu"
+	"arm,cortex-a5-pmu"
+	"arm,arm11mpcore-pmu"
 	"arm,arm1176-pmu"
 	"arm,arm1136-pmu"
 - interrupts : 1 combined interrupt or 1 per core.
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index c44647e..3aa3388 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -646,10 +646,14 @@ arch_initcall(cpu_pmu_reset);
  * PMU platform driver and devicetree bindings.
  */
 static struct of_device_id armpmu_of_device_ids[] = {
+	{.compatible = "arm,cortex-a15-pmu"},
 	{.compatible = "arm,cortex-a9-pmu"},
 	{.compatible = "arm,cortex-a8-pmu"},
-	{.compatible = "arm,arm1136-pmu"},
+	{.compatible = "arm,cortex-a7-pmu"},
+	{.compatible = "arm,cortex-a5-pmu"},
+	{.compatible = "arm,arm11mpcore-pmu"},
 	{.compatible = "arm,arm1176-pmu"},
+	{.compatible = "arm,arm1136-pmu"},
 	{},
 };
 
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:27 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:27 +0100
Subject: [PATCH 1/9] ARM: PMU: Add runtime PM Support
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-2-git-send-email-will.deacon@arm.com>

From: Jon Hunter <jon-hunter at ti.com>

Add runtime PM support to the ARM PMU driver so that devices such as OMAP
supporting dynamic PM can use the platform->runtime_* hooks to initialise
hardware at runtime. Without having these runtime PM hooks in place any
configuration of the PMU hardware would be lost when low power states are
entered and hence would prevent PMU from working.

This change also replaces the PMU platform functions enable_irq and disable_irq
added by Ming Lei with runtime_resume and runtime_suspend funtions. Ming had
added the enable_irq and disable_irq functions as a method to configure the
cross trigger interface on OMAP4 for routing the PMU interrupts. By adding
runtime PM support, we can move the code called by enable_irq and disable_irq
into the runtime PM callbacks runtime_resume and runtime_suspend.

Cc: Ming Lei <ming.lei at canonical.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Kevin Hilman <khilman at ti.com>
Signed-off-by: Jon Hunter <jon-hunter at ti.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pmu.h   |   20 ++++++++++++--------
 arch/arm/kernel/perf_event.c |   41 +++++++++++++++++++++++++++++++++--------
 2 files changed, 45 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 4432305..40d7dff 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -31,18 +31,22 @@ enum arm_pmu_type {
  *	interrupt and passed the address of the low level handler,
  *	and can be used to implement any platform specific handling
  *	before or after calling it.
- * @enable_irq: an optional handler which will be called after
- *	request_irq and be used to handle some platform specific
- *	irq enablement
- * @disable_irq: an optional handler which will be called before
- *	free_irq and be used to handle some platform specific
- *	irq disablement
+ * @runtime_resume: an optional handler which will be called by the
+ *	runtime PM framework following a call to pm_runtime_get().
+ *	Note that if pm_runtime_get() is called more than once in
+ *	succession this handler will only be called once.
+ * @runtime_suspend: an optional handler which will be called by the
+ *	runtime PM framework following a call to pm_runtime_put().
+ *	Note that if pm_runtime_get() is called more than once in
+ *	succession this handler will only be called following the
+ *	final call to pm_runtime_put() that actually disables the
+ *	hardware.
  */
 struct arm_pmu_platdata {
 	irqreturn_t (*handle_irq)(int irq, void *dev,
 				  irq_handler_t pmu_handler);
-	void (*enable_irq)(int irq);
-	void (*disable_irq)(int irq);
+	int (*runtime_resume)(struct device *dev);
+	int (*runtime_suspend)(struct device *dev);
 };
 
 #ifdef CONFIG_CPU_HAS_PMU
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b8..c44647e 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/uaccess.h>
+#include <linux/pm_runtime.h>
 
 #include <asm/cputype.h>
 #include <asm/irq.h>
@@ -364,8 +365,6 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 {
 	int i, irq, irqs;
 	struct platform_device *pmu_device = armpmu->plat_device;
-	struct arm_pmu_platdata *plat =
-		dev_get_platdata(&pmu_device->dev);
 
 	irqs = min(pmu_device->num_resources, num_possible_cpus());
 
@@ -373,13 +372,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 		if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 			continue;
 		irq = platform_get_irq(pmu_device, i);
-		if (irq >= 0) {
-			if (plat && plat->disable_irq)
-				plat->disable_irq(irq);
+		if (irq >= 0)
 			free_irq(irq, armpmu);
-		}
 	}
 
+	pm_runtime_put_sync(&pmu_device->dev);
 	release_pmu(armpmu->type);
 }
 
@@ -412,6 +409,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
 		return -ENODEV;
 	}
 
+	pm_runtime_get_sync(&pmu_device->dev);
+
 	for (i = 0; i < irqs; ++i) {
 		err = 0;
 		irq = platform_get_irq(pmu_device, i);
@@ -437,8 +436,7 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
 				irq);
 			armpmu_release_hardware(armpmu);
 			return err;
-		} else if (plat && plat->enable_irq)
-			plat->enable_irq(irq);
+		}
 
 		cpumask_set_cpu(i, &armpmu->active_irqs);
 	}
@@ -581,6 +579,28 @@ static void armpmu_disable(struct pmu *pmu)
 	armpmu->stop();
 }
 
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+	struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+	if (plat && plat->runtime_resume)
+		return plat->runtime_resume(dev);
+
+	return 0;
+}
+
+static int armpmu_runtime_suspend(struct device *dev)
+{
+	struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+	if (plat && plat->runtime_suspend)
+		return plat->runtime_suspend(dev);
+
+	return 0;
+}
+#endif
+
 static void __init armpmu_init(struct arm_pmu *armpmu)
 {
 	atomic_set(&armpmu->active_events, 0);
@@ -647,9 +667,14 @@ static int __devinit armpmu_device_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct dev_pm_ops armpmu_dev_pm_ops = {
+	SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
 static struct platform_driver armpmu_driver = {
 	.driver		= {
 		.name	= "arm-pmu",
+		.pm	= &armpmu_dev_pm_ops,
 		.of_match_table = armpmu_of_device_ids,
 	},
 	.probe		= armpmu_device_probe,
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:35 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:35 +0100
Subject: [PATCH 9/9] ARM: perf: move irq registration into pmu implementation
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-10-git-send-email-will.deacon@arm.com>

From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>

This patch moves the CPU-specific IRQ registration and parsing code into
the CPU PMU backend. This is required because a PMU may have more than
one interrupt, which in turn can be either PPI (per-cpu) or SPI
(requiring strict affinity setting at the interrupt distributor).

Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
[will: cosmetic edits and reworked interrupt dispatching]
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pmu.h       |    2 +
 arch/arm/kernel/perf_event.c     |   72 ++++++-------------------------------
 arch/arm/kernel/perf_event_cpu.c |   66 ++++++++++++++++++++++++++++++++++-
 3 files changed, 79 insertions(+), 61 deletions(-)

diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index a993ad6..a26170d 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -78,6 +78,8 @@ struct arm_pmu {
 	void		(*start)(void);
 	void		(*stop)(void);
 	void		(*reset)(void *);
+	int		(*request_irq)(irq_handler_t handler);
+	void		(*free_irq)(void);
 	int		(*map_event)(struct perf_event *event);
 	int		num_events;
 	atomic_t	active_events;
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 86fd399..93971b1 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -297,87 +297,39 @@ validate_group(struct perf_event *event)
 	return 0;
 }
 
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
 	struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 	struct platform_device *plat_device = armpmu->plat_device;
 	struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 
-	return plat->handle_irq(irq, dev, armpmu->handle_irq);
+	if (plat && plat->handle_irq)
+		return plat->handle_irq(irq, dev, armpmu->handle_irq);
+	else
+		return armpmu->handle_irq(irq, dev);
 }
 
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-	int i, irq, irqs;
-	struct platform_device *pmu_device = armpmu->plat_device;
-
-	irqs = min(pmu_device->num_resources, num_possible_cpus());
-
-	for (i = 0; i < irqs; ++i) {
-		if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
-			continue;
-		irq = platform_get_irq(pmu_device, i);
-		if (irq >= 0)
-			free_irq(irq, armpmu);
-	}
-
-	pm_runtime_put_sync(&pmu_device->dev);
+	armpmu->free_irq();
+	pm_runtime_put_sync(&armpmu->plat_device->dev);
 }
 
 static int
 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
-	struct arm_pmu_platdata *plat;
-	irq_handler_t handle_irq;
-	int i, err, irq, irqs;
+	int err;
 	struct platform_device *pmu_device = armpmu->plat_device;
 
 	if (!pmu_device)
 		return -ENODEV;
 
-	plat = dev_get_platdata(&pmu_device->dev);
-	if (plat && plat->handle_irq)
-		handle_irq = armpmu_platform_irq;
-	else
-		handle_irq = armpmu->handle_irq;
-
-	irqs = min(pmu_device->num_resources, num_possible_cpus());
-	if (irqs < 1) {
-		pr_err("no irqs for PMUs defined\n");
-		return -ENODEV;
-	}
-
 	pm_runtime_get_sync(&pmu_device->dev);
-
-	for (i = 0; i < irqs; ++i) {
-		err = 0;
-		irq = platform_get_irq(pmu_device, i);
-		if (irq < 0)
-			continue;
-
-		/*
-		 * If we have a single PMU interrupt that we can't shift,
-		 * assume that we're running on a uniprocessor machine and
-		 * continue. Otherwise, continue without this interrupt.
-		 */
-		if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-			pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-				    irq, i);
-			continue;
-		}
-
-		err = request_irq(irq, handle_irq,
-				  IRQF_DISABLED | IRQF_NOBALANCING,
-				  "arm-pmu", armpmu);
-		if (err) {
-			pr_err("unable to request IRQ%d for ARM PMU counters\n",
-				irq);
-			armpmu_release_hardware(armpmu);
-			return err;
-		}
-
-		cpumask_set_cpu(i, &armpmu->active_irqs);
+	err = armpmu->request_irq(armpmu_dispatch_irq);
+	if (err) {
+		armpmu_release_hardware(armpmu);
+		return err;
 	}
 
 	return 0;
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 56ddc98..8d7d8d4 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -70,6 +70,67 @@ static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
 	return &__get_cpu_var(cpu_hw_events);
 }
 
+static void cpu_pmu_free_irq(void)
+{
+	int i, irq, irqs;
+	struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+	irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+	for (i = 0; i < irqs; ++i) {
+		if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+			continue;
+		irq = platform_get_irq(pmu_device, i);
+		if (irq >= 0)
+			free_irq(irq, cpu_pmu);
+	}
+}
+
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+	int i, err, irq, irqs;
+	struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+	if (!pmu_device)
+		return -ENODEV;
+
+	irqs = min(pmu_device->num_resources, num_possible_cpus());
+	if (irqs < 1) {
+		pr_err("no irqs for PMUs defined\n");
+		return -ENODEV;
+	}
+
+	for (i = 0; i < irqs; ++i) {
+		err = 0;
+		irq = platform_get_irq(pmu_device, i);
+		if (irq < 0)
+			continue;
+
+		/*
+		 * If we have a single PMU interrupt that we can't shift,
+		 * assume that we're running on a uniprocessor machine and
+		 * continue. Otherwise, continue without this interrupt.
+		 */
+		if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+			pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+				    irq, i);
+			continue;
+		}
+
+		err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+				  cpu_pmu);
+		if (err) {
+			pr_err("unable to request IRQ%d for ARM PMU counters\n",
+				irq);
+			return err;
+		}
+
+		cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+	}
+
+	return 0;
+}
+
 static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	int cpu;
@@ -79,7 +140,10 @@ static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
 		events->used_mask = per_cpu(used_mask, cpu);
 		raw_spin_lock_init(&events->pmu_lock);
 	}
-	cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
+
+	cpu_pmu->get_hw_events	= cpu_pmu_get_cpu_events;
+	cpu_pmu->request_irq	= cpu_pmu_request_irq;
+	cpu_pmu->free_irq	= cpu_pmu_free_irq;
 
 	/* Ensure the PMU has sane values out of reset. */
 	if (cpu_pmu && cpu_pmu->reset)
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:29 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:29 +0100
Subject: [PATCH 3/9] ARM: pmu: remove unused reservation mechanism
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-4-git-send-email-will.deacon@arm.com>

The PMU reservation mechanism was originally intended to allow OProfile
and perf-events to co-ordinate over access to the CPU PMU. Since then,
OProfile for ARM has moved to using perf as its backend, so the
reservation code is no longer used.

This patch removes the reservation code for the CPU PMU on ARM.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 MAINTAINERS                  |    1 -
 arch/arm/Kconfig             |    8 +-------
 arch/arm/include/asm/pmu.h   |   34 ----------------------------------
 arch/arm/kernel/Makefile     |    1 -
 arch/arm/kernel/perf_event.c |    8 --------
 arch/arm/kernel/pmu.c        |   36 ------------------------------------
 6 files changed, 1 insertions(+), 87 deletions(-)
 delete mode 100644 arch/arm/kernel/pmu.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 94b823f..9dcd1ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -595,7 +595,6 @@ M:	Will Deacon <will.deacon at arm.com>
 S:	Maintained
 F:	arch/arm/kernel/perf_event*
 F:	arch/arm/oprofile/common.c
-F:	arch/arm/kernel/pmu.c
 F:	arch/arm/include/asm/pmu.h
 F:	arch/arm/kernel/hw_breakpoint.c
 F:	arch/arm/include/asm/hw_breakpoint.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..ca05a95 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1185,12 +1185,6 @@ config XSCALE_PMU
 	depends on CPU_XSCALE
 	default y
 
-config CPU_HAS_PMU
-	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
-		   (!ARCH_OMAP3 || OMAP3_EMU)
-	default y
-	bool
-
 config MULTI_IRQ_HANDLER
 	bool
 	help
@@ -1763,7 +1757,7 @@ config HIGHPTE
 
 config HW_PERF_EVENTS
 	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS && CPU_HAS_PMU
+	depends on PERF_EVENTS
 	default y
 	help
 	  Enable hardware performance counter support for perf events. If
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 40d7dff..05e0401 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -49,40 +49,6 @@ struct arm_pmu_platdata {
 	int (*runtime_suspend)(struct device *dev);
 };
 
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
-	return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type)	{ }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
 #ifdef CONFIG_HW_PERF_EVENTS
 
 /* The events for a given PMU register set. */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..cfbe3b4 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -69,7 +69,6 @@ obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU)	+= pmu.o
 obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
 AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 3aa3388..1ac1531 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,7 +377,6 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 	}
 
 	pm_runtime_put_sync(&pmu_device->dev);
-	release_pmu(armpmu->type);
 }
 
 static int
@@ -391,12 +390,6 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
 	if (!pmu_device)
 		return -ENODEV;
 
-	err = reserve_pmu(armpmu->type);
-	if (err) {
-		pr_warning("unable to reserve pmu\n");
-		return err;
-	}
-
 	plat = dev_get_platdata(&pmu_device->dev);
 	if (plat && plat->handle_irq)
 		handle_irq = armpmu_platform_irq;
@@ -706,7 +699,6 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 		raw_spin_lock_init(&events->pmu_lock);
 	}
 	armpmu->get_hw_events = armpmu_get_cpu_events;
-	armpmu->type = ARM_PMU_DEVICE_CPU;
 }
 
 /*
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644
index 2334bf8..0000000
--- a/arch/arm/kernel/pmu.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/arch/arm/kernel/pmu.c
- *
- *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- *  Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/pmu.h>
-
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-
-int
-reserve_pmu(enum arm_pmu_type type)
-{
-	return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-
-void
-release_pmu(enum arm_pmu_type type)
-{
-	clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:33 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:33 +0100
Subject: [PATCH 7/9] ARM: perf: prepare for moving CPU PMU code into separate
 file
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-8-git-send-email-will.deacon@arm.com>

The CPU PMU code is tightly coupled with generic ARM PMU handling code.
This makes it cumbersome when trying to add support for other ARM PMUs
(e.g. interconnect, L2 cache controller, bus) as the generic parts of
the code are not readily reusable.

This patch cleans up perf_event.c so that reusable code is exposed via
header files to other potential PMU drivers. The CPU code is
consistently named to identify it as such and also to prepare for moving
it into a separate file.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/perf_event.h   |    9 ++++-
 arch/arm/include/asm/pmu.h          |   11 +++++-
 arch/arm/kernel/perf_event.c        |   69 ++++++++++++++---------------------
 arch/arm/kernel/perf_event_v6.c     |    4 +-
 arch/arm/kernel/perf_event_v7.c     |   10 +++---
 arch/arm/kernel/perf_event_xscale.c |    2 +-
 6 files changed, 53 insertions(+), 52 deletions(-)

diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948..625cd62 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS		32
+
+#define HW_OP_UNSUPPORTED		0xFFFF
+#define C(_x)				PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED		0xFFFF
 
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index fbec73a..a993ad6 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -89,7 +89,9 @@ struct arm_pmu {
 
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 
 u64 armpmu_event_update(struct perf_event *event,
 			struct hw_perf_event *hwc,
@@ -99,6 +101,13 @@ int armpmu_event_set_period(struct perf_event *event,
 			    struct hw_perf_event *hwc,
 			    int idx);
 
+int armpmu_map_event(struct perf_event *event,
+		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+						[PERF_COUNT_HW_CACHE_OP_MAX]
+						[PERF_COUNT_HW_CACHE_RESULT_MAX],
+		     u32 raw_event_mask);
+
 #endif /* CONFIG_HW_PERF_EVENTS */
 
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 7c29914..9e3afd1 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -29,26 +29,17 @@
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
 
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- *  cycle counter CCNT + 31 events counters CNT0..30.
- *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS		32
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
 
 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
 const char *perf_pmu_name(void)
 {
 	if (!cpu_pmu)
@@ -69,13 +60,6 @@ int perf_num_counters(void)
 }
 EXPORT_SYMBOL_GPL(perf_num_counters);
 
-#define HW_OP_UNSUPPORTED		0xFFFF
-
-#define C(_x) \
-	PERF_COUNT_HW_CACHE_##_x
-
-#define CACHE_OP_UNSUPPORTED		0xFFFF
-
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
 				      [PERF_COUNT_HW_CACHE_MAX]
@@ -106,7 +90,7 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 }
 
 static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
 	int mapping = (*event_map)[config];
 	return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -118,19 +102,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 	return (int)(config & raw_event_mask);
 }
 
-static int map_cpu_event(struct perf_event *event,
-			 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
-			 const unsigned (*cache_map)
-					[PERF_COUNT_HW_CACHE_MAX]
-					[PERF_COUNT_HW_CACHE_OP_MAX]
-					[PERF_COUNT_HW_CACHE_RESULT_MAX],
-			 u32 raw_event_mask)
+int
+armpmu_map_event(struct perf_event *event,
+		 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+		 const unsigned (*cache_map)
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX],
+		 u32 raw_event_mask)
 {
 	u64 config = event->attr.config;
 
 	switch (event->attr.type) {
 	case PERF_TYPE_HARDWARE:
-		return armpmu_map_event(event_map, config);
+		return armpmu_map_hw_event(event_map, config);
 	case PERF_TYPE_HW_CACHE:
 		return armpmu_map_cache_event(cache_map, config);
 	case PERF_TYPE_RAW:
@@ -594,6 +579,10 @@ static int armpmu_runtime_suspend(struct device *dev)
 }
 #endif
 
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+	SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
 static void __init armpmu_init(struct arm_pmu *armpmu)
 {
 	atomic_set(&armpmu->active_events, 0);
@@ -624,7 +613,7 @@ int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 #include "perf_event_v6.c"
 #include "perf_event_v7.c"
 
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
 {
 	return &__get_cpu_var(cpu_hw_events);
 }
@@ -638,7 +627,7 @@ static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
 		events->used_mask = per_cpu(used_mask, cpu);
 		raw_spin_lock_init(&events->pmu_lock);
 	}
-	cpu_pmu->get_hw_events = armpmu_get_cpu_events;
+	cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
 
 	/* Ensure the PMU has sane values out of reset. */
 	if (cpu_pmu && cpu_pmu->reset)
@@ -651,8 +640,8 @@ static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
  * junk values out of them.
  */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
-					unsigned long action, void *hcpu)
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+				    unsigned long action, void *hcpu)
 {
 	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
 		return NOTIFY_DONE;
@@ -663,12 +652,8 @@ static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
 	return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
-	.notifier_call = pmu_cpu_notify,
-};
-
-static const struct dev_pm_ops armpmu_dev_pm_ops = {
-	SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+	.notifier_call = cpu_pmu_notify,
 };
 
 /*
@@ -771,7 +756,7 @@ static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
 
 	cpu_pmu->plat_device = pdev;
 	cpu_pmu_init(cpu_pmu);
-	register_cpu_notifier(&pmu_cpu_notifier);
+	register_cpu_notifier(&cpu_pmu_hotplug_notifier);
 	armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
 
 	return 0;
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index a4328b1..6ccc079 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
 
 static int armv6_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv6_perf_map,
+	return armpmu_map_event(event, &armv6_perf_map,
 				&armv6_perf_cache_map, 0xFF);
 }
 
@@ -679,7 +679,7 @@ static struct arm_pmu *__devinit armv6pmu_init(void)
 
 static int armv6mpcore_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv6mpcore_perf_map,
+	return armpmu_map_event(event, &armv6mpcore_perf_map,
 				&armv6mpcore_perf_cache_map, 0xFF);
 }
 
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index d65a1b8..bd4b090 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info)
 
 static int armv7_a8_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv7_a8_perf_map,
+	return armpmu_map_event(event, &armv7_a8_perf_map,
 				&armv7_a8_perf_cache_map, 0xFF);
 }
 
 static int armv7_a9_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv7_a9_perf_map,
+	return armpmu_map_event(event, &armv7_a9_perf_map,
 				&armv7_a9_perf_cache_map, 0xFF);
 }
 
 static int armv7_a5_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv7_a5_perf_map,
+	return armpmu_map_event(event, &armv7_a5_perf_map,
 				&armv7_a5_perf_cache_map, 0xFF);
 }
 
 static int armv7_a15_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv7_a15_perf_map,
+	return armpmu_map_event(event, &armv7_a15_perf_map,
 				&armv7_a15_perf_cache_map, 0xFF);
 }
 
 static int armv7_a7_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &armv7_a7_perf_map,
+	return armpmu_map_event(event, &armv7_a7_perf_map,
 				&armv7_a7_perf_cache_map, 0xFF);
 }
 
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index dcc478c..426e19f 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val)
 
 static int xscale_map_event(struct perf_event *event)
 {
-	return map_cpu_event(event, &xscale_perf_map,
+	return armpmu_map_event(event, &xscale_perf_map,
 				&xscale_perf_cache_map, 0xFF);
 }
 
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:30 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:30 +0100
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-5-git-send-email-will.deacon@arm.com>

From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>

The arm_pmu_type enumeration was initially introduced to identify
different PMU types in the system, the usual one being that on the CPU
(ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
the introduction of devicetree bindings for the CPU PMU, the enumeration
is no longer required.

This patch removes the enumeration and updates the various CPU PMU
platform devices so that they no longer pass an .id field referring
to identify the PMU type.

Cc: JD Zheng <jdzheng at broadcom.com>
Cc: Jon Hunter <jon-hunter at ti.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Olof Johansson <olof at lixom.net>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Pawel Moll <pawel.moll at arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
[will: cosmetic edits and actual removal of the enum type]
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/pmu.h               |   10 ----------
 arch/arm/mach-bcmring/arch.c             |    3 +--
 arch/arm/mach-omap2/devices.c            |    3 +--
 arch/arm/mach-pxa/devices.c              |    3 +--
 arch/arm/mach-realview/realview_eb.c     |    3 +--
 arch/arm/mach-realview/realview_pb1176.c |    3 +--
 arch/arm/mach-realview/realview_pb11mp.c |    3 +--
 arch/arm/mach-realview/realview_pba8.c   |    3 +--
 arch/arm/mach-realview/realview_pbx.c    |    3 +--
 arch/arm/mach-tegra/devices.c            |    3 +--
 arch/arm/mach-ux500/cpu-db8500.c         |    3 +--
 arch/arm/mach-vexpress/ct-ca9x4.c        |    3 +--
 arch/arm/plat-iop/pmu.c                  |    3 +--
 arch/arm/plat-samsung/devs.c             |    3 +--
 14 files changed, 13 insertions(+), 36 deletions(-)

diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 05e0401..fbec73a 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -16,15 +16,6 @@
 #include <linux/perf_event.h>
 
 /*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
-	ARM_PMU_DEVICE_CPU	= 0,
-	ARM_NUM_PMU_DEVICES,
-};
-
-/*
  * struct arm_pmu_platdata - ARM PMU platform data
  *
  * @handle_irq: an optional handler which will be called from the
@@ -73,7 +64,6 @@ struct pmu_hw_events {
 
 struct arm_pmu {
 	struct pmu	pmu;
-	enum arm_pmu_type type;
 	cpumask_t	active_irqs;
 	char		*name;
 	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..76e7953 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -29,7 +29,6 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
-#include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
 #include <mach/dma.h>
@@ -116,7 +115,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.resource	= &pmu_resource,
 	.num_resources	= 1,
 };
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c00c689..02b9478 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,7 +23,6 @@
 #include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 
 #include "iomap.h"
 #include <plat/board.h>
@@ -448,7 +447,7 @@ static struct resource omap3_pmu_resource = {
 
 static struct platform_device omap_pmu_device = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.num_resources	= 1,
 };
 
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 166eee5..c1f3b12 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,7 +6,6 @@
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/i2c/pxa-i2c.h>
 
-#include <asm/pmu.h>
 #include <mach/udc.h>
 #include <mach/pxa3xx-u2d.h>
 #include <mach/pxafb.h>
@@ -42,7 +41,7 @@ static struct resource pxa_resource_pmu = {
 
 struct platform_device pxa_device_pmu = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.resource	= &pxa_resource_pmu,
 	.num_resources	= 1,
 };
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..d7a6e9c 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -32,7 +32,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -297,7 +296,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= ARRAY_SIZE(pmu_resources),
 	.resource		= pmu_resources,
 };
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..361f898 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -34,7 +34,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -280,7 +279,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= 1,
 	.resource		= &pmu_resource,
 };
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..c56bc8d 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -32,7 +32,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -263,7 +262,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= ARRAY_SIZE(pmu_resources),
 	.resource		= pmu_resources,
 };
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..0409375 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -31,7 +31,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 
@@ -241,7 +240,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= 1,
 	.resource		= &pmu_resource,
 };
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..97885dc 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -30,7 +30,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -280,7 +279,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= ARRAY_SIZE(pmu_resources),
 	.resource		= pmu_resources,
 };
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index c70e65f..61e9603 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -23,7 +23,6 @@
 #include <linux/fsl_devices.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
@@ -516,7 +515,7 @@ static struct resource tegra_pmu_resources[] = {
 
 struct platform_device tegra_pmu_device = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.num_resources	= ARRAY_SIZE(tegra_pmu_resources),
 	.resource	= tegra_pmu_resources,
 };
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d..3ee761d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -19,7 +19,6 @@
 #include <linux/mfd/abx500/ab8500.h>
 
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -122,7 +121,7 @@ struct arm_pmu_platdata db8500_pmu_platdata = {
 
 static struct platform_device db8500_pmu_device = {
 	.name			= "arm-pmu",
-	.id			= ARM_PMU_DEVICE_CPU,
+	.id			= -1,
 	.num_resources		= ARRAY_SIZE(db8500_pmu_resources),
 	.resource		= db8500_pmu_resources,
 	.dev.platform_data	= &db8500_pmu_platdata,
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c4924..e4073a6 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -13,7 +13,6 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
-#include <asm/pmu.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
@@ -144,7 +143,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.num_resources	= ARRAY_SIZE(pmu_resources),
 	.resource	= pmu_resources,
 };
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index a2024b8..ad9f974 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/platform_device.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 
 static struct resource pmu_resource = {
@@ -26,7 +25,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.resource	= &pmu_resource,
 	.num_resources	= 1,
 };
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..8154fab 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -33,7 +33,6 @@
 #include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/irq.h>
-#include <asm/pmu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -1105,7 +1104,7 @@ static struct resource s5p_pmu_resource[] = {
 
 static struct platform_device s5p_device_pmu = {
 	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
+	.id		= -1,
 	.num_resources	= ARRAY_SIZE(s5p_pmu_resource),
 	.resource	= s5p_pmu_resource,
 };
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:32 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:32 +0100
Subject: [PATCH 6/9] ARM: perf: probe devicetree in preference to current CPU
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-7-git-send-email-will.deacon@arm.com>

The CPU PMU is probed using the current cpuid information as part of the
early_initcall initialising the architecture perf backend. For
architectures without NMI (such as ARM), this does not need to be
performed early and can be deferred to the driver probe callback. This
also allows us to probe the devicetree in preference to parsing the
current cpuid, which may be invalid on a big.LITTLE multi-cluster
system.

This patch defers the PMU probing and uses the devicetree information
when available.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/perf_event.c        |  175 ++++++++++++++++++-----------------
 arch/arm/kernel/perf_event_v6.c     |    8 +-
 arch/arm/kernel/perf_event_v7.c     |   22 ++--
 arch/arm/kernel/perf_event_xscale.c |    8 +-
 4 files changed, 110 insertions(+), 103 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 22ed512..7c29914 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/export.h>
+#include <linux/of.h>
 #include <linux/perf_event.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
@@ -610,9 +611,11 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
 	};
 }
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 {
 	armpmu_init(armpmu);
+	pr_info("enabled with %s PMU driver, %d counters available\n",
+			armpmu->name, armpmu->num_events);
 	return perf_pmu_register(&armpmu->pmu, name, type);
 }
 
@@ -621,74 +624,12 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 #include "perf_event_v6.c"
 #include "perf_event_v7.c"
 
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
-	if (cpu_pmu && cpu_pmu->reset)
-		return on_each_cpu(cpu_pmu->reset, NULL, 1);
-	return 0;
-}
-arch_initcall(cpu_pmu_reset);
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
-	{.compatible = "arm,cortex-a15-pmu"},
-	{.compatible = "arm,cortex-a9-pmu"},
-	{.compatible = "arm,cortex-a8-pmu"},
-	{.compatible = "arm,cortex-a7-pmu"},
-	{.compatible = "arm,cortex-a5-pmu"},
-	{.compatible = "arm,arm11mpcore-pmu"},
-	{.compatible = "arm,arm1176-pmu"},
-	{.compatible = "arm,arm1136-pmu"},
-	{},
-};
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
-	{.name = "arm-pmu"},
-	{},
-};
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
-	if (!cpu_pmu)
-		return -ENODEV;
-
-	cpu_pmu->plat_device = pdev;
-	return 0;
-}
-
-static const struct dev_pm_ops armpmu_dev_pm_ops = {
-	SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
-};
-
-static struct platform_driver armpmu_driver = {
-	.driver		= {
-		.name	= "arm-pmu",
-		.pm	= &armpmu_dev_pm_ops,
-		.of_match_table = armpmu_of_device_ids,
-	},
-	.probe		= armpmu_device_probe,
-	.id_table	= armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
-	return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-
 static struct pmu_hw_events *armpmu_get_cpu_events(void)
 {
 	return &__get_cpu_var(cpu_hw_events);
 }
 
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	int cpu;
 	for_each_possible_cpu(cpu) {
@@ -697,7 +638,11 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 		events->used_mask = per_cpu(used_mask, cpu);
 		raw_spin_lock_init(&events->pmu_lock);
 	}
-	armpmu->get_hw_events = armpmu_get_cpu_events;
+	cpu_pmu->get_hw_events = armpmu_get_cpu_events;
+
+	/* Ensure the PMU has sane values out of reset. */
+	if (cpu_pmu && cpu_pmu->reset)
+		on_each_cpu(cpu_pmu->reset, NULL, 1);
 }
 
 /*
@@ -722,41 +667,68 @@ static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
 	.notifier_call = pmu_cpu_notify,
 };
 
+static const struct dev_pm_ops armpmu_dev_pm_ops = {
+	SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+	{.compatible = "arm,cortex-a15-pmu",	.data = armv7_a15_pmu_init},
+	{.compatible = "arm,cortex-a9-pmu",	.data = armv7_a9_pmu_init},
+	{.compatible = "arm,cortex-a8-pmu",	.data = armv7_a8_pmu_init},
+	{.compatible = "arm,cortex-a7-pmu",	.data = armv7_a7_pmu_init},
+	{.compatible = "arm,cortex-a5-pmu",	.data = armv7_a5_pmu_init},
+	{.compatible = "arm,arm11mpcore-pmu",	.data = armv6mpcore_pmu_init},
+	{.compatible = "arm,arm1176-pmu",	.data = armv6pmu_init},
+	{.compatible = "arm,arm1136-pmu",	.data = armv6pmu_init},
+	{},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+	{.name = "arm-pmu"},
+	{},
+};
+
 /*
- * CPU PMU identification and registration.
+ * CPU PMU identification and probing.
  */
-static int __init
-init_hw_perf_events(void)
+static struct arm_pmu *__devinit probe_current_pmu(void)
 {
+	struct arm_pmu *pmu = NULL;
+	int cpu = get_cpu();
 	unsigned long cpuid = read_cpuid_id();
 	unsigned long implementor = (cpuid & 0xFF000000) >> 24;
 	unsigned long part_number = (cpuid & 0xFFF0);
 
+	pr_info("probing PMU on CPU %d\n", cpu);
+
 	/* ARM Ltd CPUs. */
 	if (0x41 == implementor) {
 		switch (part_number) {
 		case 0xB360:	/* ARM1136 */
 		case 0xB560:	/* ARM1156 */
 		case 0xB760:	/* ARM1176 */
-			cpu_pmu = armv6pmu_init();
+			pmu = armv6pmu_init();
 			break;
 		case 0xB020:	/* ARM11mpcore */
-			cpu_pmu = armv6mpcore_pmu_init();
+			pmu = armv6mpcore_pmu_init();
 			break;
 		case 0xC080:	/* Cortex-A8 */
-			cpu_pmu = armv7_a8_pmu_init();
+			pmu = armv7_a8_pmu_init();
 			break;
 		case 0xC090:	/* Cortex-A9 */
-			cpu_pmu = armv7_a9_pmu_init();
+			pmu = armv7_a9_pmu_init();
 			break;
 		case 0xC050:	/* Cortex-A5 */
-			cpu_pmu = armv7_a5_pmu_init();
+			pmu = armv7_a5_pmu_init();
 			break;
 		case 0xC0F0:	/* Cortex-A15 */
-			cpu_pmu = armv7_a15_pmu_init();
+			pmu = armv7_a15_pmu_init();
 			break;
 		case 0xC070:	/* Cortex-A7 */
-			cpu_pmu = armv7_a7_pmu_init();
+			pmu = armv7_a7_pmu_init();
 			break;
 		}
 	/* Intel CPUs [xscale]. */
@@ -764,27 +736,62 @@ init_hw_perf_events(void)
 		part_number = (cpuid >> 13) & 0x7;
 		switch (part_number) {
 		case 1:
-			cpu_pmu = xscale1pmu_init();
+			pmu = xscale1pmu_init();
 			break;
 		case 2:
-			cpu_pmu = xscale2pmu_init();
+			pmu = xscale2pmu_init();
 			break;
 		}
 	}
 
+	put_cpu();
+	return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	struct arm_pmu *(*init_fn)(void);
+	struct device_node *node = pdev->dev.of_node;
+
 	if (cpu_pmu) {
-		pr_info("enabled with %s PMU driver, %d counters available\n",
-			cpu_pmu->name, cpu_pmu->num_events);
-		cpu_pmu_init(cpu_pmu);
-		register_cpu_notifier(&pmu_cpu_notifier);
-		armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+		pr_info("attempt to register multiple PMU devices!");
+		return -ENOSPC;
+	}
+
+	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+		init_fn = of_id->data;
+		cpu_pmu = init_fn();
 	} else {
-		pr_info("no hardware support available\n");
+		cpu_pmu = probe_current_pmu();
 	}
 
+	if (!cpu_pmu)
+		return -ENODEV;
+
+	cpu_pmu->plat_device = pdev;
+	cpu_pmu_init(cpu_pmu);
+	register_cpu_notifier(&pmu_cpu_notifier);
+	armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
 	return 0;
 }
-early_initcall(init_hw_perf_events);
+
+static struct platform_driver cpu_pmu_driver = {
+	.driver		= {
+		.name	= "arm-pmu",
+		.pm	= &armpmu_dev_pm_ops,
+		.of_match_table = cpu_pmu_of_device_ids,
+	},
+	.probe		= cpu_pmu_device_probe,
+	.id_table	= cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+	return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
 
 /*
  * Callchain handling code.
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index c90fcb2..a4328b1 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = {
 	.max_period		= (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
 	return &armv6pmu;
 }
@@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = {
 	.max_period		= (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
 	return &armv6mpcore_pmu;
 }
 #else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
 	return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f04070b..d65a1b8 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = {
 	.max_period		= (1LLU << 32) - 1,
 };
 
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
 {
 	u32 nb_cnt;
 
@@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void)
 	return nb_cnt + 1;
 }
 
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
 	armv7pmu.name		= "ARMv7 Cortex-A8";
 	armv7pmu.map_event	= armv7_a8_map_event;
@@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
 	return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
 	armv7pmu.name		= "ARMv7 Cortex-A9";
 	armv7pmu.map_event	= armv7_a9_map_event;
@@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
 	return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
 	armv7pmu.name		= "ARMv7 Cortex-A5";
 	armv7pmu.map_event	= armv7_a5_map_event;
@@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
 	return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
 	armv7pmu.name		= "ARMv7 Cortex-A15";
 	armv7pmu.map_event	= armv7_a15_map_event;
@@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
 	return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
 	armv7pmu.name		= "ARMv7 Cortex-A7";
 	armv7pmu.map_event	= armv7_a7_map_event;
@@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void)
 	return &armv7pmu;
 }
 #else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
 	return NULL;
 }
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index f759fe0..dcc478c 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = {
 	.max_period	= (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
 	return &xscale1pmu;
 }
@@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = {
 	.max_period	= (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
 	return &xscale2pmu;
 }
 #else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
 	return NULL;
 }
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
 	return NULL;
 }
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 10 13:36:34 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 10 Aug 2012 18:36:34 +0100
Subject: [PATCH 8/9] ARM: perf: move CPU-specific PMU handling code into
 separate file
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <1344620195-22372-9-git-send-email-will.deacon@arm.com>

This patch moves the CPU-specific PMU handling code out of perf_event.c
and into perf_event_cpu.c.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/Makefile         |    2 +-
 arch/arm/kernel/perf_event.c     |  211 +----------------------------------
 arch/arm/kernel/perf_event_cpu.c |  231 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 233 insertions(+), 211 deletions(-)
 create mode 100644 arch/arm/kernel/perf_event_cpu.c

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index cfbe3b4..1c43214 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -69,7 +69,7 @@ obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)		+= pj4-cp0.o
 obj-$(CONFIG_IWMMXT)		+= iwmmxt.o
-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
+obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o
 AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 9e3afd1..86fd399 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,54 +12,15 @@
  */
 #define pr_fmt(fmt) "hw perfevents: " fmt
 
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/of.h>
-#include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/uaccess.h>
 #include <linux/pm_runtime.h>
+#include <linux/uaccess.h>
 
-#include <asm/cputype.h>
-#include <asm/irq.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
 
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-
-/*
- * Despite the names, these two functions are CPU-specific and are used
- * by the OProfile/perf code.
- */
-const char *perf_pmu_name(void)
-{
-	if (!cpu_pmu)
-		return NULL;
-
-	return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
-	int max_events = 0;
-
-	if (cpu_pmu != NULL)
-		max_events = cpu_pmu->num_events;
-
-	return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
 				      [PERF_COUNT_HW_CACHE_MAX]
@@ -608,176 +569,6 @@ int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 	return perf_pmu_register(&armpmu->pmu, name, type);
 }
 
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-
-static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
-{
-	return &__get_cpu_var(cpu_hw_events);
-}
-
-static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
-{
-	int cpu;
-	for_each_possible_cpu(cpu) {
-		struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
-		events->events = per_cpu(hw_events, cpu);
-		events->used_mask = per_cpu(used_mask, cpu);
-		raw_spin_lock_init(&events->pmu_lock);
-	}
-	cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
-
-	/* Ensure the PMU has sane values out of reset. */
-	if (cpu_pmu && cpu_pmu->reset)
-		on_each_cpu(cpu_pmu->reset, NULL, 1);
-}
-
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
-				    unsigned long action, void *hcpu)
-{
-	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
-		return NOTIFY_DONE;
-
-	if (cpu_pmu && cpu_pmu->reset)
-		cpu_pmu->reset(NULL);
-
-	return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
-	.notifier_call = cpu_pmu_notify,
-};
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
-	{.compatible = "arm,cortex-a15-pmu",	.data = armv7_a15_pmu_init},
-	{.compatible = "arm,cortex-a9-pmu",	.data = armv7_a9_pmu_init},
-	{.compatible = "arm,cortex-a8-pmu",	.data = armv7_a8_pmu_init},
-	{.compatible = "arm,cortex-a7-pmu",	.data = armv7_a7_pmu_init},
-	{.compatible = "arm,cortex-a5-pmu",	.data = armv7_a5_pmu_init},
-	{.compatible = "arm,arm11mpcore-pmu",	.data = armv6mpcore_pmu_init},
-	{.compatible = "arm,arm1176-pmu",	.data = armv6pmu_init},
-	{.compatible = "arm,arm1136-pmu",	.data = armv6pmu_init},
-	{},
-};
-
-static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
-	{.name = "arm-pmu"},
-	{},
-};
-
-/*
- * CPU PMU identification and probing.
- */
-static struct arm_pmu *__devinit probe_current_pmu(void)
-{
-	struct arm_pmu *pmu = NULL;
-	int cpu = get_cpu();
-	unsigned long cpuid = read_cpuid_id();
-	unsigned long implementor = (cpuid & 0xFF000000) >> 24;
-	unsigned long part_number = (cpuid & 0xFFF0);
-
-	pr_info("probing PMU on CPU %d\n", cpu);
-
-	/* ARM Ltd CPUs. */
-	if (0x41 == implementor) {
-		switch (part_number) {
-		case 0xB360:	/* ARM1136 */
-		case 0xB560:	/* ARM1156 */
-		case 0xB760:	/* ARM1176 */
-			pmu = armv6pmu_init();
-			break;
-		case 0xB020:	/* ARM11mpcore */
-			pmu = armv6mpcore_pmu_init();
-			break;
-		case 0xC080:	/* Cortex-A8 */
-			pmu = armv7_a8_pmu_init();
-			break;
-		case 0xC090:	/* Cortex-A9 */
-			pmu = armv7_a9_pmu_init();
-			break;
-		case 0xC050:	/* Cortex-A5 */
-			pmu = armv7_a5_pmu_init();
-			break;
-		case 0xC0F0:	/* Cortex-A15 */
-			pmu = armv7_a15_pmu_init();
-			break;
-		case 0xC070:	/* Cortex-A7 */
-			pmu = armv7_a7_pmu_init();
-			break;
-		}
-	/* Intel CPUs [xscale]. */
-	} else if (0x69 == implementor) {
-		part_number = (cpuid >> 13) & 0x7;
-		switch (part_number) {
-		case 1:
-			pmu = xscale1pmu_init();
-			break;
-		case 2:
-			pmu = xscale2pmu_init();
-			break;
-		}
-	}
-
-	put_cpu();
-	return pmu;
-}
-
-static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
-{
-	const struct of_device_id *of_id;
-	struct arm_pmu *(*init_fn)(void);
-	struct device_node *node = pdev->dev.of_node;
-
-	if (cpu_pmu) {
-		pr_info("attempt to register multiple PMU devices!");
-		return -ENOSPC;
-	}
-
-	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
-		init_fn = of_id->data;
-		cpu_pmu = init_fn();
-	} else {
-		cpu_pmu = probe_current_pmu();
-	}
-
-	if (!cpu_pmu)
-		return -ENODEV;
-
-	cpu_pmu->plat_device = pdev;
-	cpu_pmu_init(cpu_pmu);
-	register_cpu_notifier(&cpu_pmu_hotplug_notifier);
-	armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
-
-	return 0;
-}
-
-static struct platform_driver cpu_pmu_driver = {
-	.driver		= {
-		.name	= "arm-pmu",
-		.pm	= &armpmu_dev_pm_ops,
-		.of_match_table = cpu_pmu_of_device_ids,
-	},
-	.probe		= cpu_pmu_device_probe,
-	.id_table	= cpu_pmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
-	return platform_driver_register(&cpu_pmu_driver);
-}
-device_initcall(register_pmu_driver);
-
 /*
  * Callchain handling code.
  */
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644
index 0000000..56ddc98
--- /dev/null
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -0,0 +1,231 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+	if (!cpu_pmu)
+		return NULL;
+
+	return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+	int max_events = 0;
+
+	if (cpu_pmu != NULL)
+		max_events = cpu_pmu->num_events;
+
+	return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+	return &__get_cpu_var(cpu_hw_events);
+}
+
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	int cpu;
+	for_each_possible_cpu(cpu) {
+		struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+		events->events = per_cpu(hw_events, cpu);
+		events->used_mask = per_cpu(used_mask, cpu);
+		raw_spin_lock_init(&events->pmu_lock);
+	}
+	cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
+
+	/* Ensure the PMU has sane values out of reset. */
+	if (cpu_pmu && cpu_pmu->reset)
+		on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+				    unsigned long action, void *hcpu)
+{
+	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+		return NOTIFY_DONE;
+
+	if (cpu_pmu && cpu_pmu->reset)
+		cpu_pmu->reset(NULL);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+	.notifier_call = cpu_pmu_notify,
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+	{.compatible = "arm,cortex-a15-pmu",	.data = armv7_a15_pmu_init},
+	{.compatible = "arm,cortex-a9-pmu",	.data = armv7_a9_pmu_init},
+	{.compatible = "arm,cortex-a8-pmu",	.data = armv7_a8_pmu_init},
+	{.compatible = "arm,cortex-a7-pmu",	.data = armv7_a7_pmu_init},
+	{.compatible = "arm,cortex-a5-pmu",	.data = armv7_a5_pmu_init},
+	{.compatible = "arm,arm11mpcore-pmu",	.data = armv6mpcore_pmu_init},
+	{.compatible = "arm,arm1176-pmu",	.data = armv6pmu_init},
+	{.compatible = "arm,arm1136-pmu",	.data = armv6pmu_init},
+	{},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+	{.name = "arm-pmu"},
+	{},
+};
+
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+	struct arm_pmu *pmu = NULL;
+	int cpu = get_cpu();
+	unsigned long cpuid = read_cpuid_id();
+	unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+	unsigned long part_number = (cpuid & 0xFFF0);
+
+	pr_info("probing PMU on CPU %d\n", cpu);
+
+	/* ARM Ltd CPUs. */
+	if (0x41 == implementor) {
+		switch (part_number) {
+		case 0xB360:	/* ARM1136 */
+		case 0xB560:	/* ARM1156 */
+		case 0xB760:	/* ARM1176 */
+			pmu = armv6pmu_init();
+			break;
+		case 0xB020:	/* ARM11mpcore */
+			pmu = armv6mpcore_pmu_init();
+			break;
+		case 0xC080:	/* Cortex-A8 */
+			pmu = armv7_a8_pmu_init();
+			break;
+		case 0xC090:	/* Cortex-A9 */
+			pmu = armv7_a9_pmu_init();
+			break;
+		case 0xC050:	/* Cortex-A5 */
+			pmu = armv7_a5_pmu_init();
+			break;
+		case 0xC0F0:	/* Cortex-A15 */
+			pmu = armv7_a15_pmu_init();
+			break;
+		case 0xC070:	/* Cortex-A7 */
+			pmu = armv7_a7_pmu_init();
+			break;
+		}
+	/* Intel CPUs [xscale]. */
+	} else if (0x69 == implementor) {
+		part_number = (cpuid >> 13) & 0x7;
+		switch (part_number) {
+		case 1:
+			pmu = xscale1pmu_init();
+			break;
+		case 2:
+			pmu = xscale2pmu_init();
+			break;
+		}
+	}
+
+	put_cpu();
+	return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *of_id;
+	struct arm_pmu *(*init_fn)(void);
+	struct device_node *node = pdev->dev.of_node;
+
+	if (cpu_pmu) {
+		pr_info("attempt to register multiple PMU devices!");
+		return -ENOSPC;
+	}
+
+	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+		init_fn = of_id->data;
+		cpu_pmu = init_fn();
+	} else {
+		cpu_pmu = probe_current_pmu();
+	}
+
+	if (!cpu_pmu)
+		return -ENODEV;
+
+	cpu_pmu->plat_device = pdev;
+	cpu_pmu_init(cpu_pmu);
+	register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+	armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
+	return 0;
+}
+
+static struct platform_driver cpu_pmu_driver = {
+	.driver		= {
+		.name	= "arm-pmu",
+		.pm	= &armpmu_dev_pm_ops,
+		.of_match_table = cpu_pmu_of_device_ids,
+	},
+	.probe		= cpu_pmu_device_probe,
+	.id_table	= cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+	return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
-- 
1.7.4.1



From jonathan.austin at arm.com  Fri Aug 10 13:43:56 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 10 Aug 2012 18:43:56 +0100
Subject: Why the region area don't decrease 1 in function
 sanity_check_meminfo?
In-Reply-To: <20120810153705.GZ18957@n2100.arm.linux.org.uk>
References: <CAKvkGKeqzAiqRAj+H+E-eoN9SOOMP-aMhUJYmUb0UK4ei=jouA@mail.gmail.com>
 <5025253D.3010007@arm.com> <20120810153705.GZ18957@n2100.arm.linux.org.uk>
Message-ID: <5025485C.80407@arm.com>

Hi Russell,

On 10/08/12 16:37, Russell King - ARM Linux wrote:

>> With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
>> partially overlap the vmalloc region. The check for partial overlap checks
>> __va(bank->start + bank->size) > vmalloc_min, but the last address of the
>> bank is (bank->start + bank->size -1).

> 
> Erm.
> 
> Let's say you have a bank at 0x80000000, which maps to 0xc0000000 virtual.
> This is 512MB in size (so it's last byte address is 0x9fffffff).  That
> places it at at 0xdfffffff.  Now, let's say vmalloc_min is 0xe0000000.
> 
> "bank->start + bank->size" would be 0xa0000000, right ?
> 
> So, "__va(bank->start + bank->size)" would be 0xe0000000.


Yep, except in our (hypothetical?) case below...
>

> And "0xe0000000 > vmalloc_min" would be false.
> 


Yup... My commit message is wrong. Sorry. The linear case is fine...

>> However, theoretically, if using using SPARSEMEM in a situation where the
>> physical to virtual address conversion is not monotonic increasing, the
>> incorrect test could result in a bank not being truncated when it should be.
> 
> Right, so what you're actually talking about is a non-linear translation
> by __va() and friends.  In that case, what you actually need is:
> 
> 	(__va(bank->start + bank->size - 1) + 1) > vmalloc_min
> or
> 	__va(bank->start + bank->size - 1) >= vmalloc_min
> 
> and not
> 
> 	__va(bank->start + bank->size - 1) > vmalloc_min
> 


Agreed. I prefer the second form, and there seems to be a precedent for
">=" further up in sanity_check_meminfo, too.

If you think it is worth fixing for this case, I'll make the fixes,
ensure the commit message is !wrong and submit this to the patch-system.

Jonny



From khilman at ti.com  Fri Aug 10 13:44:42 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 10 Aug 2012 10:44:42 -0700
Subject: [GIT PULL] ARM: OMAP: PM fixes for v3.6-rc
Message-ID: <878vdmfxpx.fsf@ti.com>

Tony,

Please pull the following PM related fixes for v3.6-rc.

One of them is a fix for drivers/cpufreq/omap-cpufreq.c, but it needs to
go along with the arch/arm change.  I'm listed in MAINTAINERS for the
OMAP CPUfreq driver now, so this should be OK.

Kevin

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.6/fixes/pm

for you to fetch changes up to 196449de0c886e64b48d01bd7ee153656db92884:

  ARM: OMAP4: Register the OPP table only for 4430 device (2012-08-09 08:07:54 -0700)

----------------------------------------------------------------
Kevin Hilman (2):
      ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled
      Revert "ARM: OMAP3: PM: call pre/post transition per powerdomain"

Rajendra Nayak (2):
      cpufreq: OMAP: Handle missing frequency table on SMP systems
      ARM: OMAP4: Register the OPP table only for 4430 device

Santosh Shilimkar (1):
      ARM: OMAP4: sleep: Save the complete used register stack frame

 arch/arm/mach-omap2/opp4xxx_data.c |    2 +-
 arch/arm/mach-omap2/pm34xx.c       |   19 ++++---------------
 arch/arm/mach-omap2/sleep44xx.S    |    8 ++++++--
 arch/arm/mach-omap2/twl-common.c   |    1 +
 drivers/cpufreq/omap-cpufreq.c     |    4 +++-
 5 files changed, 15 insertions(+), 19 deletions(-)


From khilman at ti.com  Fri Aug 10 14:39:10 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 10 Aug 2012 11:39:10 -0700
Subject: [PATCH v2 0/3] ARM: OMAP: omap_device: track driver bound status
Message-ID: <1344623953-26434-1-git-send-email-khilman@ti.com>

Add support for the omap_device layer to keep track of driver bound status.

This will be used to track whether or not a driver is bound in order
to make intelligent omap_device enable/idle decisions (e.g. ensuring
omap_devices are idled when no driver is present, or driver probe
fails.)

Also, the omap_device layer implements PM domains for all
omap_devices, and knowing whether or not a driver is bound is needed
to know whether or not a drivers callbacks are valid, especially in
cases of failed driver probe.

Kevin Hilman (3):
  ARM: OMAP: omap_device: keep track of driver bound status
  ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
  ARM: OMAP: omap_device: idle devices with no driver bound

 arch/arm/plat-omap/include/plat/omap_device.h |    2 +
 arch/arm/plat-omap/omap_device.c              |   56 ++++++++++++++++++++++---
 2 files changed, 53 insertions(+), 5 deletions(-)

-- 
1.7.9.2



From khilman at ti.com  Fri Aug 10 14:39:13 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 10 Aug 2012 11:39:13 -0700
Subject: [PATCH v2 3/3] ARM: OMAP: omap_device: idle devices with no driver
 bound
In-Reply-To: <1344623953-26434-1-git-send-email-khilman@ti.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
Message-ID: <1344623953-26434-4-git-send-email-khilman@ti.com>

Under some circumstances, drivers may leave an omap_device enabled due
to driver programming errors, or due to a failure in the drivers
probe method.

Using the recently added omap_device driver_status field, we can
detect conditions where an omap_device is enabled but has no driver
bound and then ensure that the device is properly idled until it can
be probed again.

The goal of this feature is not only to detect and warn on these error
conditions, but also to ensure that devices are properly put in
low-power states so they do not prevent SoC-wide low-power states.

Cc: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/plat-omap/omap_device.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 150112e..0693260 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1133,3 +1133,41 @@ static int __init omap_device_init(void)
 	return 0;
 }
 core_initcall(omap_device_init);
+
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *od = to_omap_device(pdev);
+
+	if (!od)
+		return 0;
+
+	/*
+	 * If omap_device state is enabled, but has no driver bound,
+	 * idle it.
+	 */
+	if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+		if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+			dev_warn(dev, "%s: enabled but no driver.  Idling\n",
+				__func__);
+			omap_device_idle(pdev);
+		}
+	}
+
+	return 0;
+}
+
+static int __init omap_device_late_init(void)
+{
+	bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+	return 0;
+}
+late_initcall(omap_device_late_init);
-- 
1.7.9.2



From khilman at ti.com  Fri Aug 10 14:39:12 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 10 Aug 2012 11:39:12 -0700
Subject: [PATCH v2 2/3] ARM: OMAP: omap_device: don't attempt late suspend if
 no driver bound
In-Reply-To: <1344623953-26434-1-git-send-email-khilman@ti.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
Message-ID: <1344623953-26434-3-git-send-email-khilman@ti.com>

Currently, the omap_device PM domain layer uses the late suspend and
early resume callbacks to ensure devices are in their low power
states.

However, this is attempted even in cases where a driver probe has
failed.  If a driver's ->probe() method fails, the driver is likely in
a state where it is not expecting its runtime PM callbacks to be
called, yet currently the omap_device PM domain code attempts to call
the drivers callbacks.

To fix, use the omap_device driver_status field to check whether a
driver is bound to the omap_device before attempting to trigger driver
callbacks.

Cc: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/plat-omap/omap_device.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 1d1b5ff..150112e 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -756,6 +756,10 @@ static int _od_suspend_noirq(struct device *dev)
 	struct omap_device *od = to_omap_device(pdev);
 	int ret;
 
+	/* Don't attempt late suspend on a driver that is not bound */
+	if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
+		return 0;
+
 	ret = pm_generic_suspend_noirq(dev);
 
 	if (!ret && !pm_runtime_status_suspended(dev)) {
-- 
1.7.9.2



From khilman at ti.com  Fri Aug 10 14:39:11 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 10 Aug 2012 11:39:11 -0700
Subject: [PATCH v2 1/3] ARM: OMAP: omap_device: keep track of driver bound
 status
In-Reply-To: <1344623953-26434-1-git-send-email-khilman@ti.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
Message-ID: <1344623953-26434-2-git-send-email-khilman@ti.com>

Use the bus notifier to keep track of driver bound status by adding a
new internal field to struct omap_device: _driver_status.

This will be useful for follow-up patches which need to know whether
or not a driver is bound in order to make intelligent omap_device
enable/idle decisions.

Cc: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/plat-omap/include/plat/omap_device.h |    2 ++
 arch/arm/plat-omap/omap_device.c              |   14 +++++++++-----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c..e7259c0 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
  * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
+ * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
  *
  * Integrates omap_hwmod data into Linux platform_device.
  *
@@ -73,6 +74,7 @@ struct omap_device {
 	struct omap_device_pm_latency	*pm_lats;
 	u32				dev_wakeup_lat;
 	u32				_dev_wakeup_lat_limit;
+	unsigned long			_driver_status;
 	u8				pm_lats_cnt;
 	s8				pm_lat_level;
 	u8				hwmods_cnt;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..1d1b5ff 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -385,17 +385,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
 				      unsigned long event, void *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *od;
 
 	switch (event) {
-	case BUS_NOTIFY_ADD_DEVICE:
-		if (pdev->dev.of_node)
-			omap_device_build_from_dt(pdev);
-		break;
-
 	case BUS_NOTIFY_DEL_DEVICE:
 		if (pdev->archdata.od)
 			omap_device_delete(pdev->archdata.od);
 		break;
+	case BUS_NOTIFY_ADD_DEVICE:
+		if (pdev->dev.of_node)
+			omap_device_build_from_dt(pdev);
+		/* fall through */
+	default:
+		od = to_omap_device(pdev);
+		if (od)
+			od->_driver_status = event;
 	}
 
 	return NOTIFY_DONE;
-- 
1.7.9.2



From robherring2 at gmail.com  Fri Aug 10 14:42:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 10 Aug 2012 13:42:17 -0500
Subject: [PATCH 2/9] ARM: perf: add devicetree bindings for 11MPcore,
 A5, A7 and A15 PMUs
In-Reply-To: <1344620195-22372-3-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-3-git-send-email-will.deacon@arm.com>
Message-ID: <50255609.50009@gmail.com>

On 08/10/2012 12:36 PM, Will Deacon wrote:
> This patch adds separate devicetree bindings for 11MPcore and
> Cortex-{A5,A7,A15} PMUs in preparation for improved devicetree parsing
> in the ARM perf-event CPU PMU driver.
> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---

Acked-by: Rob Herring <rob.herring at calxeda.com>


>  Documentation/devicetree/bindings/arm/pmu.txt |    4 ++++
>  arch/arm/kernel/perf_event.c                  |    6 +++++-
>  2 files changed, 9 insertions(+), 1 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
> index 1c044eb..343781b 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.txt
> +++ b/Documentation/devicetree/bindings/arm/pmu.txt
> @@ -7,8 +7,12 @@ representation in the device tree should be done as under:-
>  Required properties:
>  
>  - compatible : should be one of
> +	"arm,cortex-a15-pmu"
>  	"arm,cortex-a9-pmu"
>  	"arm,cortex-a8-pmu"
> +	"arm,cortex-a7-pmu"
> +	"arm,cortex-a5-pmu"
> +	"arm,arm11mpcore-pmu"
>  	"arm,arm1176-pmu"
>  	"arm,arm1136-pmu"
>  - interrupts : 1 combined interrupt or 1 per core.
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index c44647e..3aa3388 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -646,10 +646,14 @@ arch_initcall(cpu_pmu_reset);
>   * PMU platform driver and devicetree bindings.
>   */
>  static struct of_device_id armpmu_of_device_ids[] = {
> +	{.compatible = "arm,cortex-a15-pmu"},
>  	{.compatible = "arm,cortex-a9-pmu"},
>  	{.compatible = "arm,cortex-a8-pmu"},
> -	{.compatible = "arm,arm1136-pmu"},
> +	{.compatible = "arm,cortex-a7-pmu"},
> +	{.compatible = "arm,cortex-a5-pmu"},
> +	{.compatible = "arm,arm11mpcore-pmu"},
>  	{.compatible = "arm,arm1176-pmu"},
> +	{.compatible = "arm,arm1136-pmu"},
>  	{},
>  };
>  
> 



From arnd at arndb.de  Fri Aug 10 15:06:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 21:06:12 +0200
Subject: [GIT PULL 0/3] arm-soc updates
Message-ID: <1344625575-27560-1-git-send-email-arnd@arndb.de>

Hi Linus,

Here are three pull requests for you to consider for the next -rc.

The first one is our regular bug fix series, this time with a lot
of patches fixing build regressions. Please pull at least this one.

The other two are things that fell through the cracks in the v3.6
merge window because of communication problems between the arm-soc
team and our downstream maintainers. Neither of them is important,
but applying them should also be harmless. If you feel like making
an exception, please have a look and consider merging them as well,
but don't worry about them otherwise.

	Arnd


From s.hauer at pengutronix.de  Fri Aug 10 15:19:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 10 Aug 2012 21:19:37 +0200
Subject: [PATCH] ARM: plat-mxc: Remove unused imx_ioremap
In-Reply-To: <1344431176-10486-1-git-send-email-festevam@gmail.com>
References: <1344431176-10486-1-git-send-email-festevam@gmail.com>
Message-ID: <20120810191937.GE1451@pengutronix.de>

On Wed, Aug 08, 2012 at 10:06:16AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> imx_ioremap is no longer used on imx platforms, so remove it.
> 
> As the EXPORT_SYMBOL_GPL is removed, it is also safe to remove the module.h header.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks

Sascha

> ---
>  arch/arm/plat-mxc/system.c |    4 ----
>  1 files changed, 0 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
> index 1996c3e..3da78cf 100644
> --- a/arch/arm/plat-mxc/system.c
> +++ b/arch/arm/plat-mxc/system.c
> @@ -21,7 +21,6 @@
>  #include <linux/io.h>
>  #include <linux/err.h>
>  #include <linux/delay.h>
> -#include <linux/module.h>
>  
>  #include <mach/hardware.h>
>  #include <mach/common.h>
> @@ -29,9 +28,6 @@
>  #include <asm/proc-fns.h>
>  #include <asm/mach-types.h>
>  
> -void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
> -EXPORT_SYMBOL_GPL(imx_ioremap);
> -
>  static void __iomem *wdog_base;
>  
>  /*
> -- 
> 1.7.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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From marex at denx.de  Fri Aug 10 15:33:27 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 10 Aug 2012 21:33:27 +0200
Subject: [PATCH] mtd: gpmi: add NAND write verify support
In-Reply-To: <CAOMZO5C2qUNPCCbc4jW5+4HZuuhPQ=Lid6UsfgBXNpr44q2p2A@mail.gmail.com>
References: <1344568737-902-1-git-send-email-b32955@freescale.com>
 <201208101704.44984.marex@denx.de>
 <CAOMZO5C2qUNPCCbc4jW5+4HZuuhPQ=Lid6UsfgBXNpr44q2p2A@mail.gmail.com>
Message-ID: <201208102133.27634.marex@denx.de>

Dear Fabio Estevam,

> Hi Marek,
> 
> On Fri, Aug 10, 2012 at 12:04 PM, Marek Vasut <marex at denx.de> wrote:
> >> Even there are two nand chips, there is only one gpmi controller.
> > 
> > For now ... yes.
> 
> Does this look better?
> 
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> b/drivers/mtd/nand/gpmi-nand index 8c0d2f0..5262ef3 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1533,6 +1533,21 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
>         gpmi_free_dma_buffer(this);
>  }
> 
> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
> len) +{
> +       struct nand_chip *nand = mtd->priv;
> +       struct gpmi_nand_data *data = container_of(mtd, struct
> gpmi_nand_data, +                                                         
>         mtd); +       int ret;
> +
> +       ret = gpmi_ecc_read_page(mtd, nand, data->verify_buf, 0, 0);

You ignored my comment on this one.

> +       if (ret)
> +               return -EFAULT;
> +       if (memcmp(buf, data->verify_buf, len))
> +               return -EFAULT;
> +       return 0;
> +}
> +
>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
>  {
>         struct mtd_info  *mtd = &this->mtd;
> @@ -1555,6 +1570,7 @@ static int __devinit gpmi_nfc_init(struct
> gpmi_nand_data * chip->dev_ready         = gpmi_dev_ready;
>         chip->read_byte         = gpmi_read_byte;
>         chip->read_buf          = gpmi_read_buf;
> +       chip->verify_buf        = gpmi_verify_buf;
>         chip->write_buf         = gpmi_write_buf;
>         chip->ecc.read_page     = gpmi_ecc_read_page;
>         chip->ecc.write_page    = gpmi_ecc_write_page;
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> b/drivers/mtd/nand/gpmi-nand index 1547a60..cd9bdf7 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -148,6 +148,7 @@ struct gpmi_nand_data {
>         /* General-use Variables */
>         int                     current_chip;
>         unsigned int            command_length;
> +       uint8_t                 verify_buf[NAND_MAX_PAGESIZE];

Yes, this is definitelly better.

>         /* passed from upper layer */
>         uint8_t                 *upper_buf;
> 
> and then I can also send this separate change to allow multi-instances:
> 
> @@ -1630,7 +1646,7 @@ static int __devinit gpmi_nand_probe(struct
> platform_devic return -ENOMEM;
>         }
> 
> -       this = kzalloc(sizeof(*this), GFP_KERNEL);
> +       this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);

devm_clk_* functions could be used too from a quick glance ... devm_request_irq 
is in place iirc, but check that too.

>         if (!this) {
>                 pr_err("Failed to allocate per-device memory\n");
>                 return -ENOMEM;

Best regards,
Marek Vasut


From broonie at opensource.wolfsonmicro.com  Fri Aug 10 15:50:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 10 Aug 2012 20:50:08 +0100
Subject: Lockups reading from i.MX51 SSI registers
Message-ID: <20120810195005.GP24328@opensource.wolfsonmicro.com>

Hi,

I'm trying to use -next to test AC'97 register I/O on an i.MX51 board
but I'm seeing the CPU hang during probe at:

	lreg = (reg & 0x7f) <<  12 ;
	writel(lreg, base + SSI_SACADD);

in imx_ssi_ac97_read().  I'm somewhat suspicious this might be because
the IP block isn't clocked properly, I do notice the recent conversion
to the clock API which looks rather involved but it's possible something
else broke.  Does anyone have any bright ideas what might be going on
here?  The board doesn't have the reste functions defined so this is the
first interaction with the hardware block AFAICT.

Thanks,
Mark


From s.hauer at pengutronix.de  Fri Aug 10 15:56:38 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 10 Aug 2012 21:56:38 +0200
Subject: Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120810195005.GP24328@opensource.wolfsonmicro.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
Message-ID: <20120810195638.GF1451@pengutronix.de>

On Fri, Aug 10, 2012 at 08:50:08PM +0100, Mark Brown wrote:
> Hi,
> 
> I'm trying to use -next to test AC'97 register I/O on an i.MX51 board
> but I'm seeing the CPU hang during probe at:
> 
> 	lreg = (reg & 0x7f) <<  12 ;
> 	writel(lreg, base + SSI_SACADD);
> 
> in imx_ssi_ac97_read().  I'm somewhat suspicious this might be because
> the IP block isn't clocked properly, I do notice the recent conversion
> to the clock API which looks rather involved but it's possible something
> else broke.  Does anyone have any bright ideas what might be going on
> here?  The board doesn't have the reste functions defined so this is the
> first interaction with the hardware block AFAICT.

No idea currently, just adding Uwe to Cc because I think he has seen
something similar on an i.MX35 board recently.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From nsekhar at ti.com  Fri Aug 10 15:57:11 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Sat, 11 Aug 2012 01:27:11 +0530
Subject: [PATCH v3 0/6] omap-am33xx rtc dt support
In-Reply-To: <cover.1343383616.git.afzal@ti.com>
References: <cover.1343383616.git.afzal@ti.com>
Message-ID: <50256797.3020505@ti.com>

On 7/27/2012 5:53 PM, Afzal Mohammed wrote:
> Hi,
> 
> This series makes rtc-omap driver DT capable, adds AM33xx
> RTC DT support along with a few enchancments to the driver.
> 
> rtc-omap driver is made intelligent enough to handle kicker
> mechanism. This helps in removing kicker mechanism support
> done for DaVinci at platform level.
> 
> This has been tested on Beaglebone (AM33xx platform) and on
> DaVinci DA850 EVM.
> 
> This series is based over linux-omap master and can be
> directly applied over linux-next, except for
> [PATCH 6/6] arm/dts: am33xx rtc node.
> 
> PATCH 6/6 should go through linux-omap tree and needs
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg71644.html
> (arm/dts: am33xx wdt node) to get applied cleanly

I tested patches 1-5 on AM18x EVM using rtcwake and hwclock commands.
Also tested on DT enabled AM18x EVM using hwclock.

For patched 1-5:

Acked-by: Sekhar Nori <nsekhar at ti.com>

Alessandro,

I assume you would want me to queue 2/6 through DaVinci tree. That patch
depends on 1/6 being accepted and merged by you. Let me know how you
want to move forward here.

Thanks,
Sekhar


From u.kleine-koenig at pengutronix.de  Fri Aug 10 16:14:56 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 10 Aug 2012 22:14:56 +0200
Subject: Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120810195638.GF1451@pengutronix.de>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
Message-ID: <20120810201456.GL25520@pengutronix.de>

Hi,

On Fri, Aug 10, 2012 at 09:56:38PM +0200, Sascha Hauer wrote:
> On Fri, Aug 10, 2012 at 08:50:08PM +0100, Mark Brown wrote:
> > I'm trying to use -next to test AC'97 register I/O on an i.MX51 board
> > but I'm seeing the CPU hang during probe at:
> > 
> > 	lreg = (reg & 0x7f) <<  12 ;
> > 	writel(lreg, base + SSI_SACADD);
> > 
> > in imx_ssi_ac97_read().  I'm somewhat suspicious this might be because
> > the IP block isn't clocked properly, I do notice the recent conversion
> > to the clock API which looks rather involved but it's possible something
> > else broke.  Does anyone have any bright ideas what might be going on
> > here?  The board doesn't have the reste functions defined so this is the
> > first interaction with the hardware block AFAICT.
> 
> No idea currently, just adding Uwe to Cc because I think he has seen
> something similar on an i.MX35 board recently.
I havn't debugged that yet, but one issue I think needs to be solved is
that since the clk conversion there are two ssi clocks. And from a quick
look the ssi driver only handles one of them.

Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From s.hauer at pengutronix.de  Fri Aug 10 17:06:47 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 10 Aug 2012 23:06:47 +0200
Subject: Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120810201456.GL25520@pengutronix.de>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
Message-ID: <20120810210647.GG1451@pengutronix.de>

On Fri, Aug 10, 2012 at 10:14:56PM +0200, Uwe Kleine-K?nig wrote:
> Hi,
> 
> On Fri, Aug 10, 2012 at 09:56:38PM +0200, Sascha Hauer wrote:
> > On Fri, Aug 10, 2012 at 08:50:08PM +0100, Mark Brown wrote:
> > > I'm trying to use -next to test AC'97 register I/O on an i.MX51 board
> > > but I'm seeing the CPU hang during probe at:
> > > 
> > > 	lreg = (reg & 0x7f) <<  12 ;
> > > 	writel(lreg, base + SSI_SACADD);
> > > 
> > > in imx_ssi_ac97_read().  I'm somewhat suspicious this might be because
> > > the IP block isn't clocked properly, I do notice the recent conversion
> > > to the clock API which looks rather involved but it's possible something
> > > else broke.  Does anyone have any bright ideas what might be going on
> > > here?  The board doesn't have the reste functions defined so this is the
> > > first interaction with the hardware block AFAICT.
> > 
> > No idea currently, just adding Uwe to Cc because I think he has seen
> > something similar on an i.MX35 board recently.
> I havn't debugged that yet, but one issue I think needs to be solved is
> that since the clk conversion there are two ssi clocks. And from a quick
> look the ssi driver only handles one of them.

One clock is for the bus which must be turned on. The other is for the
bitclock which we currently can ignore since we only support clock slave
mode.
On an i.MX5 ssi[123]_ipg_gate must be turned on by the ssi driver. From
a quick look to the clock code it looks correct.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From rvaswani at codeaurora.org  Fri Aug 10 17:18:00 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Fri, 10 Aug 2012 14:18:00 -0700
Subject: [PATCH RESEND 1/2] msm: io: Remove 7x30 iomap region from 7x00
Message-ID: <1344633480-1815-1-git-send-email-rvaswani@codeaurora.org>

This is redundant code.

Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
---
 arch/arm/mach-msm/io.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index a1e7b11..2409c0b 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -51,9 +51,6 @@ static struct map_desc msm_io_desc[] __initdata = {
 	defined(CONFIG_DEBUG_MSM_UART3)
 	MSM_DEVICE(DEBUG_UART),
 #endif
-#ifdef CONFIG_ARCH_MSM7X30
-	MSM_DEVICE(GCC),
-#endif
 	{
 		.virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
 		.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
-- 
Sent by an employee of the Qualcomm Innovation Center,Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From rvaswani at codeaurora.org  Fri Aug 10 17:18:16 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Fri, 10 Aug 2012 14:18:16 -0700
Subject: [PATCH RESEND 2/2] msm: io: Change the default static iomappings to
 be shared
Message-ID: <1344633496-1873-1-git-send-email-rvaswani@codeaurora.org>

With 3.4 kernel the static iomappings can be shared with the ioremap
mappings. If ioremap is called with an address for which a static
mapping already exists, then that mapping should be used instead
of creating a new one.
However, the MT_DEVICE_NONSHARED flag prevents this. Hence, get rid
of this flag. Some targets (7X00) that require the static iomappings
to be NONSHARED use the MSM_DEVICE_TYPE and MSM_CHIP_DEVICE_TYPE macros.

Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
---
 arch/arm/mach-msm/io.c |   25 +++++++++++++++++--------
 1 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 2409c0b..5fc2e48 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -33,23 +33,32 @@
 		.virtual = (unsigned long) MSM_##name##_BASE, \
 		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
 		.length = chip##_##name##_SIZE, \
-		.type = MT_DEVICE_NONSHARED, \
+		.type = MT_DEVICE, \
+	 }
+
+#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {			      \
+		.virtual = (unsigned long) MSM_##name##_BASE, \
+		.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
+		.length = chip##_##name##_SIZE, \
+		.type = mem_type, \
 	 }
 
 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
+#define MSM_DEVICE_TYPE(name, mem_type) \
+		MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
 
 #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
 	|| defined(CONFIG_ARCH_MSM7X25)
 static struct map_desc msm_io_desc[] __initdata = {
-	MSM_DEVICE(VIC),
-	MSM_CHIP_DEVICE(CSR, MSM7X00),
-	MSM_DEVICE(DMOV),
-	MSM_CHIP_DEVICE(GPIO1, MSM7X00),
-	MSM_CHIP_DEVICE(GPIO2, MSM7X00),
-	MSM_DEVICE(CLK_CTL),
+	MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
+	MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
+	MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
+	MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
+	MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
+	MSM_CHIP_DEVICE_TYPE(CLK_CTL, MSM7X00, MT_DEVICE_NONSHARED),
 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
 	defined(CONFIG_DEBUG_MSM_UART3)
-	MSM_DEVICE(DEBUG_UART),
+	MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
 #endif
 	{
 		.virtual =  (unsigned long) MSM_SHARED_RAM_BASE,
-- 
Sent by an employee of the Qualcomm Innovation Center,Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From rvaswani at codeaurora.org  Fri Aug 10 17:57:34 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Fri, 10 Aug 2012 14:57:34 -0700
Subject: [PATCH 1/2] ARM: local timers: Unmask interrupt before new TVAL is set
Message-ID: <1344635854-5033-1-git-send-email-rvaswani@codeaurora.org>

Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
If this order is not followed, there are chances that on some
hardware you would not receive any timer interrupts.

Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
---
 arch/arm/kernel/arch_timer.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index dd58035..1d0d9df 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -126,8 +126,8 @@ static int arch_timer_set_next_event(unsigned long evt,
 	ctrl |= ARCH_TIMER_CTRL_ENABLE;
 	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 
-	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
 	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
 
 	return 0;
 }
-- 
Sent by an employee of the Qualcomm Innovation Center,Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From rvaswani at codeaurora.org  Fri Aug 10 17:58:41 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Fri, 10 Aug 2012 14:58:41 -0700
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
Message-ID: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>

The current arch_timer only support accessing through CP15 interface.
Add support for ARM processors that only support IO mapped register
interface

Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
---
 .../devicetree/bindings/arm/arch_timer.txt         |    7 +
 arch/arm/kernel/arch_timer.c                       |  259 ++++++++++++++++----
 2 files changed, 223 insertions(+), 43 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 52478c8..1c71799 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its per-processor interrupts.
 
 - clock-frequency : The frequency of the main counter, in Hz. Optional.
 
+- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI) interrupt
+  In the default case i.e without this property, the timer irq is treated as a
+  PPI interrupt. Optional.
+
+- If the node address and reg is specified, the arch_timer will try to use the memory
+  mapped timer. Optional.
+
 Example:
 
 	timer {
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 1d0d9df..09604b7 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -18,6 +18,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/io.h>
 
 #include <asm/cputype.h>
@@ -29,8 +30,17 @@
 static unsigned long arch_timer_rate;
 static int arch_timer_ppi;
 static int arch_timer_ppi2;
+static int is_irq_percpu;
 
 static struct clock_event_device __percpu **arch_timer_evt;
+static void __iomem *timer_base;
+
+struct arch_timer_operations {
+	void (*reg_write)(int, u32);
+	u32 (*reg_read)(int);
+	cycle_t (*get_cntpct)(void);
+	cycle_t (*get_cntvct)(void);
+};
 
 /*
  * Architected system timer support.
@@ -44,7 +54,29 @@ static struct clock_event_device __percpu **arch_timer_evt;
 #define ARCH_TIMER_REG_FREQ		1
 #define ARCH_TIMER_REG_TVAL		2
 
-static void arch_timer_reg_write(int reg, u32 val)
+/* Iomapped Register Offsets */
+#define ARCH_TIMER_CNTP_LOW_REG		0x000
+#define ARCH_TIMER_CNTP_HIGH_REG	0x004
+#define ARCH_TIMER_CNTV_LOW_REG		0x008
+#define ARCH_TIMER_CNTV_HIGH_REG	0x00C
+#define ARCH_TIMER_CTRL_REG		0x02C
+#define ARCH_TIMER_FREQ_REG		0x010
+#define ARCH_TIMER_CNTP_TVAL_REG	0x028
+#define ARCH_TIMER_CNTV_TVAL_REG	0x038
+
+static void timer_reg_write_mem(int reg, u32 val)
+{
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		__raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		__raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
+		break;
+	}
+}
+
+static void timer_reg_write_cp15(int reg, u32 val)
 {
 	switch (reg) {
 	case ARCH_TIMER_REG_CTRL:
@@ -58,7 +90,28 @@ static void arch_timer_reg_write(int reg, u32 val)
 	isb();
 }
 
-static u32 arch_timer_reg_read(int reg)
+static u32 timer_reg_read_mem(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		val = __raw_readl(timer_base + ARCH_TIMER_CTRL_REG);
+		break;
+	case ARCH_TIMER_REG_FREQ:
+		val = __raw_readl(timer_base + ARCH_TIMER_FREQ_REG);
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		val = __raw_readl(timer_base + ARCH_TIMER_CNTP_TVAL_REG);
+		break;
+	default:
+		BUG();
+	}
+
+	return val;
+}
+
+static u32 timer_reg_read_cp15(int reg)
 {
 	u32 val;
 
@@ -79,6 +132,103 @@ static u32 arch_timer_reg_read(int reg)
 	return val;
 }
 
+static cycle_t arch_counter_get_cntpct_mem(void)
+{
+	u32 cvall, cvalh, thigh;
+
+	do {
+		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
+		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTP_LOW_REG);
+		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
+	} while (cvalh != thigh);
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static cycle_t arch_counter_get_cntpct_cp15(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static cycle_t arch_counter_get_cntvct_mem(void)
+{
+	u32 cvall, cvalh, thigh;
+
+	do {
+		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
+		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTV_LOW_REG);
+		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
+	} while (cvalh != thigh);
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static cycle_t arch_counter_get_cntvct_cp15(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static struct arch_timer_operations arch_timer_ops_cp15 = {
+	.reg_read = &timer_reg_read_cp15,
+	.reg_write = &timer_reg_write_cp15,
+	.get_cntpct = &arch_counter_get_cntpct_cp15,
+	.get_cntvct = &arch_counter_get_cntvct_cp15,
+};
+
+static struct arch_timer_operations arch_timer_ops_mem = {
+	.reg_read = &timer_reg_read_mem,
+	.reg_write = &timer_reg_write_mem,
+	.get_cntpct = &arch_counter_get_cntpct_mem,
+	.get_cntvct = &arch_counter_get_cntvct_mem,
+};
+
+static struct arch_timer_operations *arch_specific_timer = &arch_timer_ops_cp15;
+
+static inline void arch_timer_reg_write(int reg, u32 val)
+{
+	arch_specific_timer->reg_write(reg, val);
+}
+
+static inline u32 arch_timer_reg_read(int reg)
+{
+	return arch_specific_timer->reg_read(reg);
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+	return arch_specific_timer->get_cntpct();
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	return arch_specific_timer->get_cntvct();
+}
+
+static u32 notrace arch_counter_get_cntvct32(void)
+{
+	cycle_t cntvct = arch_counter_get_cntpct();
+
+	/*
+	 * The sched_clock infrastructure only knows about counters
+	 * with at most 32bits. Forget about the upper 24 bits for the
+	 * time being...
+	 */
+	return (u32)(cntvct & (u32)~0);
+}
+
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+	return arch_counter_get_cntpct();
+}
+
 static irqreturn_t arch_timer_handler(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
@@ -167,7 +317,9 @@ static int arch_timer_available(void)
 {
 	unsigned long freq;
 
-	if (!local_timer_is_architected())
+	if (timer_base)
+		arch_specific_timer = &arch_timer_ops_mem;
+	else if (!local_timer_is_architected())
 		return -ENXIO;
 
 	if (arch_timer_rate == 0) {
@@ -188,41 +340,6 @@ static int arch_timer_available(void)
 	return 0;
 }
 
-static inline cycle_t arch_counter_get_cntpct(void)
-{
-	u32 cvall, cvalh;
-
-	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
-{
-	u32 cvall, cvalh;
-
-	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static u32 notrace arch_counter_get_cntvct32(void)
-{
-	cycle_t cntvct = arch_counter_get_cntvct();
-
-	/*
-	 * The sched_clock infrastructure only knows about counters
-	 * with at most 32bits. Forget about the upper 24 bits for the
-	 * time being...
-	 */
-	return (u32)(cntvct & (u32)~0);
-}
-
-static cycle_t arch_counter_read(struct clocksource *cs)
-{
-	return arch_counter_get_cntpct();
-}
-
 static struct clocksource clocksource_counter = {
 	.name	= "arch_sys_counter",
 	.rating	= 400,
@@ -262,8 +379,12 @@ static int __init arch_timer_register(void)
 
 	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 
-	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+	if (is_irq_percpu)
+		err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
 				 "arch_timer", arch_timer_evt);
+	else
+		err = request_irq(arch_timer_ppi, arch_timer_handler, 0,
+			"arch_timer", arch_timer_evt);
 	if (err) {
 		pr_err("arch_timer: can't register interrupt %d (%d)\n",
 		       arch_timer_ppi, err);
@@ -271,8 +392,13 @@ static int __init arch_timer_register(void)
 	}
 
 	if (arch_timer_ppi2) {
-		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-					 "arch_timer", arch_timer_evt);
+		if (is_irq_percpu)
+			err = request_percpu_irq(arch_timer_ppi2,
+					arch_timer_handler, "arch_timer",
+					arch_timer_evt);
+		else
+			err = request_irq(arch_timer_ppi2, arch_timer_handler,
+					0, "arch_timer", arch_timer_evt);
 		if (err) {
 			pr_err("arch_timer: can't register interrupt %d (%d)\n",
 			       arch_timer_ppi2, err);
@@ -314,10 +440,40 @@ static const struct of_device_id arch_timer_of_match[] __initconst = {
 	{},
 };
 
+static int __init arch_timer_base_init(void)
+{
+	struct device_node *np;
+
+	if (!timer_base) {
+		np = of_find_matching_node(NULL, arch_timer_of_match);
+		if (!np) {
+			pr_err("arch_timer: can't find DT node\n");
+			return -ENODEV;
+		}
+
+		if (of_get_address(np, 0, NULL, NULL)) {
+			timer_base = of_iomap(np, 0);
+			if (!timer_base) {
+				pr_err("arch_timer: cant map timer base\n");
+				return -ENOMEM;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static inline void __init arch_timer_base_free(void)
+{
+	if (timer_base)
+		iounmap(timer_base);
+}
+
 int __init arch_timer_of_register(void)
 {
 	struct device_node *np;
 	u32 freq;
+	int ret;
 
 	np = of_find_matching_node(NULL, arch_timer_of_match);
 	if (!np) {
@@ -331,20 +487,37 @@ int __init arch_timer_of_register(void)
 
 	arch_timer_ppi = irq_of_parse_and_map(np, 0);
 	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+
+	ret = arch_timer_base_init();
+	if (ret)
+		return ret;
+
+	is_irq_percpu = !(of_property_read_bool(np, "irq-is-not-percpu"));
+
 	pr_info("arch_timer: found %s irqs %d %d\n",
 		np->name, arch_timer_ppi, arch_timer_ppi2);
 
-	return arch_timer_register();
+	ret = arch_timer_register();
+	if (ret)
+		arch_timer_base_free();
+
+	return ret;
 }
 
 int __init arch_timer_sched_clock_init(void)
 {
 	int err;
 
-	err = arch_timer_available();
+	err = arch_timer_base_init();
 	if (err)
 		return err;
 
+	err = arch_timer_available();
+	if (err) {
+		arch_timer_base_free();
+		return err;
+	}
+
 	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
 	return 0;
 }
-- 
Sent by an employee of the Qualcomm Innovation Center,Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From robherring2 at gmail.com  Fri Aug 10 18:10:35 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 10 Aug 2012 17:10:35 -0500
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <502586DB.2000609@gmail.com>

On 08/10/2012 04:58 PM, Rohit Vaswani wrote:
> The current arch_timer only support accessing through CP15 interface.
> Add support for ARM processors that only support IO mapped register
> interface
> 
> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>  .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>  arch/arm/kernel/arch_timer.c                       |  259 ++++++++++++++++----
>  2 files changed, 223 insertions(+), 43 deletions(-)

The original file is 360 lines. It doesn't really seem like there's a
lot of overlap and I wonder if it is worth the extra overhead.

> 
> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
> index 52478c8..1c71799 100644
> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its per-processor interrupts.
>  
>  - clock-frequency : The frequency of the main counter, in Hz. Optional.
>  
> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI) interrupt
> +  In the default case i.e without this property, the timer irq is treated as a
> +  PPI interrupt. Optional.

The first field in the gic interrupts binding already defines this.

> +
> +- If the node address and reg is specified, the arch_timer will try to use the memory
> +  mapped timer. Optional.

This timer is fundamentally different h/w. You need a new compatible string.

> +
>  Example:
>  
>  	timer {
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index 1d0d9df..09604b7 100644
> --- a/arch/arm/kernel/arch_timer.c
> +++ b/arch/arm/kernel/arch_timer.c
> @@ -18,6 +18,7 @@
>  #include <linux/clockchips.h>
>  #include <linux/interrupt.h>
>  #include <linux/of_irq.h>
> +#include <linux/of_address.h>
>  #include <linux/io.h>
>  
>  #include <asm/cputype.h>
> @@ -29,8 +30,17 @@
>  static unsigned long arch_timer_rate;
>  static int arch_timer_ppi;
>  static int arch_timer_ppi2;
> +static int is_irq_percpu;
>  
>  static struct clock_event_device __percpu **arch_timer_evt;
> +static void __iomem *timer_base;
> +
> +struct arch_timer_operations {
> +	void (*reg_write)(int, u32);
> +	u32 (*reg_read)(int);
> +	cycle_t (*get_cntpct)(void);
> +	cycle_t (*get_cntvct)(void);
> +};
>  
>  /*
>   * Architected system timer support.
> @@ -44,7 +54,29 @@ static struct clock_event_device __percpu **arch_timer_evt;
>  #define ARCH_TIMER_REG_FREQ		1
>  #define ARCH_TIMER_REG_TVAL		2
>  
> -static void arch_timer_reg_write(int reg, u32 val)
> +/* Iomapped Register Offsets */
> +#define ARCH_TIMER_CNTP_LOW_REG		0x000
> +#define ARCH_TIMER_CNTP_HIGH_REG	0x004
> +#define ARCH_TIMER_CNTV_LOW_REG		0x008
> +#define ARCH_TIMER_CNTV_HIGH_REG	0x00C
> +#define ARCH_TIMER_CTRL_REG		0x02C
> +#define ARCH_TIMER_FREQ_REG		0x010
> +#define ARCH_TIMER_CNTP_TVAL_REG	0x028
> +#define ARCH_TIMER_CNTV_TVAL_REG	0x038
> +
> +static void timer_reg_write_mem(int reg, u32 val)
> +{
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;

This whole function seems a bit pointless as it only adds timer_base.

Rob

> +	}
> +}
> +
> +static void timer_reg_write_cp15(int reg, u32 val)
>  {
>  	switch (reg) {
>  	case ARCH_TIMER_REG_CTRL:
> @@ -58,7 +90,28 @@ static void arch_timer_reg_write(int reg, u32 val)
>  	isb();
>  }
>  
> -static u32 arch_timer_reg_read(int reg)
> +static u32 timer_reg_read_mem(int reg)
> +{
> +	u32 val;
> +
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_FREQ:
> +		val = __raw_readl(timer_base + ARCH_TIMER_FREQ_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;
> +	default:
> +		BUG();
> +	}
> +
> +	return val;
> +}
> +
> +static u32 timer_reg_read_cp15(int reg)
>  {
>  	u32 val;
>  
> @@ -79,6 +132,103 @@ static u32 arch_timer_reg_read(int reg)
>  	return val;
>  }
>  
> +static cycle_t arch_counter_get_cntpct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTP_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntpct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntvct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTV_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntvct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static struct arch_timer_operations arch_timer_ops_cp15 = {
> +	.reg_read = &timer_reg_read_cp15,
> +	.reg_write = &timer_reg_write_cp15,
> +	.get_cntpct = &arch_counter_get_cntpct_cp15,
> +	.get_cntvct = &arch_counter_get_cntvct_cp15,
> +};
> +
> +static struct arch_timer_operations arch_timer_ops_mem = {
> +	.reg_read = &timer_reg_read_mem,
> +	.reg_write = &timer_reg_write_mem,
> +	.get_cntpct = &arch_counter_get_cntpct_mem,
> +	.get_cntvct = &arch_counter_get_cntvct_mem,
> +};
> +
> +static struct arch_timer_operations *arch_specific_timer = &arch_timer_ops_cp15;
> +
> +static inline void arch_timer_reg_write(int reg, u32 val)
> +{
> +	arch_specific_timer->reg_write(reg, val);
> +}
> +
> +static inline u32 arch_timer_reg_read(int reg)
> +{
> +	return arch_specific_timer->reg_read(reg);
> +}
> +
> +static inline cycle_t arch_counter_get_cntpct(void)
> +{
> +	return arch_specific_timer->get_cntpct();
> +}
> +
> +static inline cycle_t arch_counter_get_cntvct(void)
> +{
> +	return arch_specific_timer->get_cntvct();
> +}
> +
> +static u32 notrace arch_counter_get_cntvct32(void)
> +{
> +	cycle_t cntvct = arch_counter_get_cntpct();
> +
> +	/*
> +	 * The sched_clock infrastructure only knows about counters
> +	 * with at most 32bits. Forget about the upper 24 bits for the
> +	 * time being...
> +	 */
> +	return (u32)(cntvct & (u32)~0);
> +}
> +
> +static cycle_t arch_counter_read(struct clocksource *cs)
> +{
> +	return arch_counter_get_cntpct();
> +}
> +
>  static irqreturn_t arch_timer_handler(int irq, void *dev_id)
>  {
>  	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> @@ -167,7 +317,9 @@ static int arch_timer_available(void)
>  {
>  	unsigned long freq;
>  
> -	if (!local_timer_is_architected())
> +	if (timer_base)
> +		arch_specific_timer = &arch_timer_ops_mem;
> +	else if (!local_timer_is_architected())
>  		return -ENXIO;
>  
>  	if (arch_timer_rate == 0) {
> @@ -188,41 +340,6 @@ static int arch_timer_available(void)
>  	return 0;
>  }
>  
> -static inline cycle_t arch_counter_get_cntpct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static inline cycle_t arch_counter_get_cntvct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static u32 notrace arch_counter_get_cntvct32(void)
> -{
> -	cycle_t cntvct = arch_counter_get_cntvct();
> -
> -	/*
> -	 * The sched_clock infrastructure only knows about counters
> -	 * with at most 32bits. Forget about the upper 24 bits for the
> -	 * time being...
> -	 */
> -	return (u32)(cntvct & (u32)~0);
> -}
> -
> -static cycle_t arch_counter_read(struct clocksource *cs)
> -{
> -	return arch_counter_get_cntpct();
> -}
> -
>  static struct clocksource clocksource_counter = {
>  	.name	= "arch_sys_counter",
>  	.rating	= 400,
> @@ -262,8 +379,12 @@ static int __init arch_timer_register(void)
>  
>  	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
>  
> -	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
> +	if (is_irq_percpu)
> +		err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
>  				 "arch_timer", arch_timer_evt);
> +	else
> +		err = request_irq(arch_timer_ppi, arch_timer_handler, 0,
> +			"arch_timer", arch_timer_evt);
>  	if (err) {
>  		pr_err("arch_timer: can't register interrupt %d (%d)\n",
>  		       arch_timer_ppi, err);
> @@ -271,8 +392,13 @@ static int __init arch_timer_register(void)
>  	}
>  
>  	if (arch_timer_ppi2) {
> -		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
> -					 "arch_timer", arch_timer_evt);
> +		if (is_irq_percpu)
> +			err = request_percpu_irq(arch_timer_ppi2,
> +					arch_timer_handler, "arch_timer",
> +					arch_timer_evt);
> +		else
> +			err = request_irq(arch_timer_ppi2, arch_timer_handler,
> +					0, "arch_timer", arch_timer_evt);
>  		if (err) {
>  			pr_err("arch_timer: can't register interrupt %d (%d)\n",
>  			       arch_timer_ppi2, err);
> @@ -314,10 +440,40 @@ static const struct of_device_id arch_timer_of_match[] __initconst = {
>  	{},
>  };
>  
> +static int __init arch_timer_base_init(void)
> +{
> +	struct device_node *np;
> +
> +	if (!timer_base) {
> +		np = of_find_matching_node(NULL, arch_timer_of_match);
> +		if (!np) {
> +			pr_err("arch_timer: can't find DT node\n");
> +			return -ENODEV;
> +		}
> +
> +		if (of_get_address(np, 0, NULL, NULL)) {
> +			timer_base = of_iomap(np, 0);
> +			if (!timer_base) {
> +				pr_err("arch_timer: cant map timer base\n");
> +				return -ENOMEM;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static inline void __init arch_timer_base_free(void)
> +{
> +	if (timer_base)
> +		iounmap(timer_base);
> +}
> +
>  int __init arch_timer_of_register(void)
>  {
>  	struct device_node *np;
>  	u32 freq;
> +	int ret;
>  
>  	np = of_find_matching_node(NULL, arch_timer_of_match);
>  	if (!np) {
> @@ -331,20 +487,37 @@ int __init arch_timer_of_register(void)
>  
>  	arch_timer_ppi = irq_of_parse_and_map(np, 0);
>  	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
> +
> +	ret = arch_timer_base_init();
> +	if (ret)
> +		return ret;
> +
> +	is_irq_percpu = !(of_property_read_bool(np, "irq-is-not-percpu"));
> +
>  	pr_info("arch_timer: found %s irqs %d %d\n",
>  		np->name, arch_timer_ppi, arch_timer_ppi2);
>  
> -	return arch_timer_register();
> +	ret = arch_timer_register();
> +	if (ret)
> +		arch_timer_base_free();
> +
> +	return ret;
>  }
>  
>  int __init arch_timer_sched_clock_init(void)
>  {
>  	int err;
>  
> -	err = arch_timer_available();
> +	err = arch_timer_base_init();
>  	if (err)
>  		return err;
>  
> +	err = arch_timer_available();
> +	if (err) {
> +		arch_timer_base_free();
> +		return err;
> +	}
> +
>  	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
>  	return 0;
>  }
> 


From paul at pwsan.com  Fri Aug 10 18:57:51 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 10 Aug 2012 16:57:51 -0600 (MDT)
Subject: [PATCH v2 0/3] ARM: OMAP: omap_device: track driver bound status
In-Reply-To: <1344623953-26434-1-git-send-email-khilman@ti.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
Message-ID: <alpine.DEB.2.00.1208101651220.29149@utopia.booyaka.com>

Hi Kevin,

On Fri, 10 Aug 2012, Kevin Hilman wrote:

> Add support for the omap_device layer to keep track of driver bound status.
> 
> This will be used to track whether or not a driver is bound in order
> to make intelligent omap_device enable/idle decisions (e.g. ensuring
> omap_devices are idled when no driver is present, or driver probe
> fails.)
> 
> Also, the omap_device layer implements PM domains for all
> omap_devices, and knowing whether or not a driver is bound is needed
> to know whether or not a drivers callbacks are valid, especially in
> cases of failed driver probe.
> 
> Kevin Hilman (3):
>   ARM: OMAP: omap_device: keep track of driver bound status
>   ARM: OMAP: omap_device: don't attempt late suspend if no driver bound
>   ARM: OMAP: omap_device: idle devices with no driver bound
> 
>  arch/arm/plat-omap/include/plat/omap_device.h |    2 +
>  arch/arm/plat-omap/omap_device.c              |   56 ++++++++++++++++++++++---
>  2 files changed, 53 insertions(+), 5 deletions(-)

Thanks, these have been queued for 3.7 with a couple of changes to patch 
3.  Those changes fix a checkpatch issue, and drop the superfluous blank 
line at the top of omap_device.c added by an earlier commit.


- Paul


From paul at pwsan.com  Fri Aug 10 18:59:31 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 10 Aug 2012 16:59:31 -0600 (MDT)
Subject: [PATCH v2 3/3] ARM: OMAP: omap_device: idle devices with no
 driver bound
In-Reply-To: <1344623953-26434-4-git-send-email-khilman@ti.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
 <1344623953-26434-4-git-send-email-khilman@ti.com>
Message-ID: <alpine.DEB.2.00.1208101658130.29149@utopia.booyaka.com>

On Fri, 10 Aug 2012, Kevin Hilman wrote:

> Under some circumstances, drivers may leave an omap_device enabled due
> to driver programming errors, or due to a failure in the drivers
> probe method.
> 
> Using the recently added omap_device driver_status field, we can
> detect conditions where an omap_device is enabled but has no driver
> bound and then ensure that the device is properly idled until it can
> be probed again.
> 
> The goal of this feature is not only to detect and warn on these error
> conditions, but also to ensure that devices are properly put in
> low-power states so they do not prevent SoC-wide low-power states.
> 
> Cc: Paul Walmsley <paul at pwsan.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>

Here's the queued version of this one.


- Paul

From: Kevin Hilman <khilman at ti.com>
Date: Fri, 10 Aug 2012 11:39:13 -0700
Subject: [PATCH] ARM: OMAP: omap_device: idle devices with no driver bound

Under some circumstances, drivers may leave an omap_device enabled due
to driver programming errors, or due to a failure in the drivers
probe method.

Using the recently added omap_device driver_status field, we can
detect conditions where an omap_device is enabled but has no driver
bound and then ensure that the device is properly idled until it can
be probed again.

The goal of this feature is not only to detect and warn on these error
conditions, but also to ensure that devices are properly put in
low-power states so they do not prevent SoC-wide low-power states.

Cc: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
[paul at pwsan.com: fixed checkpatch issue; removed blank line at top of 
 file]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/plat-omap/omap_device.c |   39 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 150112e..1f8d9c9 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
-
 /*
  * omap_device implementation
  *
@@ -1133,3 +1132,41 @@ static int __init omap_device_init(void)
 	return 0;
 }
 core_initcall(omap_device_init);
+
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *od = to_omap_device(pdev);
+
+	if (!od)
+		return 0;
+
+	/*
+	 * If omap_device state is enabled, but has no driver bound,
+	 * idle it.
+	 */
+	if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+		if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+			dev_warn(dev, "%s: enabled but no driver.  Idling\n",
+				 __func__);
+			omap_device_idle(pdev);
+		}
+	}
+
+	return 0;
+}
+
+static int __init omap_device_late_init(void)
+{
+	bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+	return 0;
+}
+late_initcall(omap_device_late_init);
-- 
1.7.10.4



From swarren at wwwdotorg.org  Fri Aug 10 19:15:40 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 17:15:40 -0600
Subject: [PATCH 1/2] pinctrl/nomadik: add STn8815 ASIC support
In-Reply-To: <1344552208-957-1-git-send-email-linus.walleij@linaro.org>
References: <1344552208-957-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <5025961C.8030009@wwwdotorg.org>

On 08/09/2012 04:43 PM, Linus Walleij wrote:
> This adds support for the STN8815 ASIC for the Nomadik pin
> controller.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>



From swarren at wwwdotorg.org  Fri Aug 10 19:18:33 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 10 Aug 2012 17:18:33 -0600
Subject: [PATCH 2/2] ARM: nomadik: configure Nomadik for pin control
In-Reply-To: <1344552220-995-1-git-send-email-linus.walleij@linaro.org>
References: <1344552220-995-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <502596C9.4010900@wwwdotorg.org>

On 08/09/2012 04:43 PM, Linus Walleij wrote:
> This converts the Nomadik to using pin control using the
> driver for the STN8815 ASIC.

> diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c

> +static inline void
> +cpu8815_add_pinctrl(struct device *parent, const char *name)
> +{
> +	struct platform_device_info pdevinfo = {
> +		.parent = parent,
> +		.name = name,
> +		.id = -1,
> +	};
> +
> +	platform_device_register_full(&pdevinfo);
> +}

Out of curiosity, why platform_device_register_full() not
platform_device_register() here?

Otherwise,
Acked-by: Stephen Warren <swarren at wwwdotorg.org>



From rvaswani at codeaurora.org  Fri Aug 10 19:37:42 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Fri, 10 Aug 2012 16:37:42 -0700
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <502586DB.2000609@gmail.com>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
 <502586DB.2000609@gmail.com>
Message-ID: <50259B46.1040402@codeaurora.org>

Thanks for your feedback Rob.

On 8/10/2012 3:10 PM, Rob Herring wrote:
> On 08/10/2012 04:58 PM, Rohit Vaswani wrote:
>> The current arch_timer only support accessing through CP15 interface.
>> Add support for ARM processors that only support IO mapped register
>> interface
>>
>> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
>> ---
>>   .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>>   arch/arm/kernel/arch_timer.c                       |  259 ++++++++++++++++----
>>   2 files changed, 223 insertions(+), 43 deletions(-)
> The original file is 360 lines. It doesn't really seem like there's a
> lot of overlap and I wonder if it is worth the extra overhead.
>
>> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> index 52478c8..1c71799 100644
>> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its per-processor interrupts.
>>   
>>   - clock-frequency : The frequency of the main counter, in Hz. Optional.
>>   
>> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI) interrupt
>> +  In the default case i.e without this property, the timer irq is treated as a
>> +  PPI interrupt. Optional.
> The first field in the gic interrupts binding already defines this.
Is there a generic way to extract that information from the interrupts 
binding. I saw Chris Smith's patch that adds irq_is_per_cpu function. 
Perhaps we can use that once it is merged ?
>
>> +
>> +- If the node address and reg is specified, the arch_timer will try to use the memory
>> +  mapped timer. Optional.
> This timer is fundamentally different h/w. You need a new compatible string.
I think that the timer is the same, but it just has a different 
interface. Do you still think we need a new compatible string ?
>
>> +
>>   Example:
>>   
>>   	timer {
>> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
>> index 1d0d9df..09604b7 100644
>> --- a/arch/arm/kernel/arch_timer.c
>> +++ b/arch/arm/kernel/arch_timer.c
>> @@ -18,6 +18,7 @@
>>   #include <linux/clockchips.h>
>>   #include <linux/interrupt.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>>   #include <linux/io.h>
>>   
>>   #include <asm/cputype.h>
>> @@ -29,8 +30,17 @@
>>   static unsigned long arch_timer_rate;
>>   static int arch_timer_ppi;
>>   static int arch_timer_ppi2;
>> +static int is_irq_percpu;
>>   
>>   static struct clock_event_device __percpu **arch_timer_evt;
>> +static void __iomem *timer_base;
>> +
>> +struct arch_timer_operations {
>> +	void (*reg_write)(int, u32);
>> +	u32 (*reg_read)(int);
>> +	cycle_t (*get_cntpct)(void);
>> +	cycle_t (*get_cntvct)(void);
>> +};
>>   
>>   /*
>>    * Architected system timer support.
>> @@ -44,7 +54,29 @@ static struct clock_event_device __percpu **arch_timer_evt;
>>   #define ARCH_TIMER_REG_FREQ		1
>>   #define ARCH_TIMER_REG_TVAL		2
>>   
>> -static void arch_timer_reg_write(int reg, u32 val)
>> +/* Iomapped Register Offsets */
>> +#define ARCH_TIMER_CNTP_LOW_REG		0x000
>> +#define ARCH_TIMER_CNTP_HIGH_REG	0x004
>> +#define ARCH_TIMER_CNTV_LOW_REG		0x008
>> +#define ARCH_TIMER_CNTV_HIGH_REG	0x00C
>> +#define ARCH_TIMER_CTRL_REG		0x02C
>> +#define ARCH_TIMER_FREQ_REG		0x010
>> +#define ARCH_TIMER_CNTP_TVAL_REG	0x028
>> +#define ARCH_TIMER_CNTV_TVAL_REG	0x038
>> +
>> +static void timer_reg_write_mem(int reg, u32 val)
>> +{
>> +	switch (reg) {
>> +	case ARCH_TIMER_REG_CTRL:
>> +		__raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
>> +		break;
>> +	case ARCH_TIMER_REG_TVAL:
>> +		__raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
>> +		break;
> This whole function seems a bit pointless as it only adds timer_base.
>
> Rob
I tried to the keep the functions similar to the cp15 interface ones. Is 
there something else you suggest doing ?

Thanks,
Rohit Vaswani

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From cyril at ti.com  Fri Aug 10 21:25:00 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:25:00 -0400
Subject: [PATCH v2 17/22] ARM: mm: clean up membank size limit checks
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-18-git-send-email-cyril@ti.com>

This patch cleans up the highmem sanity check code by simplifying the range
checks with a pre-calculated size_limit.  This patch should otherwise have no
functional impact on behavior.

This patch also removes a redundant (bank->start < vmalloc_limit) check, since
this is already covered by the !highmem condition.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/mm/mmu.c |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3d685c6..662684b 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -899,10 +899,15 @@ void __init sanity_check_meminfo(void)
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
+		phys_addr_t size_limit;
+
 		*bank = meminfo.bank[i];
+		size_limit = bank->size;
 
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
+		else
+			size_limit = vmalloc_limit - bank->start;
 
 		bank->highmem = highmem;
 
@@ -911,8 +916,7 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && bank->start < vmalloc_limit &&
-		    bank->size > vmalloc_limit - bank->start) {
+		if (!highmem && bank->size > size_limit) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -921,12 +925,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].size -= size_limit;
 				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_limit - bank->start;
+			bank->size = size_limit;
 		}
 #else
 		/*
@@ -944,14 +948,13 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (bank->start + bank->size > vmalloc_limit)
-			unsigned long newsize = vmalloc_limit - bank->start;
+		if (bank->size > size_limit) {
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
 			       (unsigned long long)bank->start + bank->size - 1,
-			       (unsigned long long)bank->start + newsize - 1);
-			bank->size = newsize;
+			       (unsigned long long)bank->start + size_limit - 1);
+			bank->size = size_limit;
 		}
 #endif
 		if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:57 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:57 -0400
Subject: [PATCH v2 14/22] ARM: LPAE: accomodate >32-bit addresses for page
 table base
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-15-git-send-email-cyril@ti.com>

This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems.  This allows for up to
38-bit physical addresses.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/memory.h |   15 +++++++++++++++
 arch/arm/kernel/head.S        |   10 ++++------
 arch/arm/kernel/smp.c         |   11 +++++++++--
 arch/arm/mm/proc-v7-3level.S  |    8 ++++++++
 4 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 64db5a4..e5d0cc8 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,7 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/cache.h>
 #include <asm/runtime-patch.h>
 
 #ifdef CONFIG_NEED_MACH_MEMORY_H
@@ -143,6 +144,20 @@
 #define page_to_phys(page)	(__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)	(pfn_to_page(__phys_to_pfn(phys)))
 
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT		L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT		0
+#endif
+#define ARCH_PGD_MASK		((1 << ARCH_PGD_SHIFT) - 1)
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 61fb8df..9664db0 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -152,7 +152,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
 	pgtbl	r4, r8				@ page table address
@@ -306,6 +306,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
 	sub	r4, r4, #0x1000		@ point to the PGD table
+	mov	r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
 	mov	pc, lr
 ENDPROC(__create_page_tables)
@@ -379,7 +380,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -398,10 +399,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
 	bic	r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-	mov	r5, #0
-	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
 	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..9831716 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -60,6 +60,13 @@ enum ipi_msg_type {
 
 static DECLARE_COMPLETION(cpu_running);
 
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+	phys_addr_t pgdir = virt_to_phys(pgd);
+	BUG_ON(pgdir & ARCH_PGD_MASK);
+	return pgdir >> ARCH_PGD_SHIFT;
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
 	int ret;
@@ -69,8 +76,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 	 * its stack and the page tables.
 	 */
 	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-	secondary_data.pgdir = virt_to_phys(idmap_pgd);
-	secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+	secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+	secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
 	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
 	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index e28383f..6fa0444 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -120,6 +120,7 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 	ldr	\tmp, =swapper_pg_dir		@ swapper_pg_dir virtual address
+	mov	\tmp, \tmp, lsr #ARCH_PGD_SHIFT
 	cmp	\ttbr1, \tmp			@ PHYS_OFFSET > PAGE_OFFSET? (branch below)
 	mrc	p15, 0, \tmp, c2, c0, 2		@ TTB control register
 	orr	\tmp, \tmp, #TTB_EAE
@@ -139,8 +140,15 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 */
 	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
 	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits
 	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
 	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits
+	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
+	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0
 	.endm
 
 	__CPUINIT
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:52 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:52 -0400
Subject: [PATCH v2 09/22] ARM: LPAE: use phys_addr_t for initrd location and
 size
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-10-git-send-email-cyril@ti.com>

From: Vitaly Andrianov <vitalya at ti.com>

This patch fixes the initrd setup code to use phys_addr_t instead of assuming
32-bit addressing.  Without this we cannot boot on systems where initrd is
located above the 4G physical address limit.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/mm/init.c |   13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 19ba70b..bae9d05 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 
 #include "mm.h"
 
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
 static int __init early_initrd(char *p)
 {
-	unsigned long start, size;
+	phys_addr_t start;
+	unsigned long size;
 	char *endp;
 
 	start = memparse(p, &endp);
@@ -347,14 +348,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (phys_initrd_size &&
 	    !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size &&
 	    memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-		pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-		       phys_initrd_start, phys_initrd_size);
+		pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+		       (u64)phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size) {
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:49 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:49 -0400
Subject: [PATCH v2 06/22] ARM: LPAE: use signed arithmetic for mask definitions
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-7-git-send-email-cyril@ti.com>

This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing
unsigned long math truncates the mask at the 32-bits.  This clearly does bad
things on PAE systems.

This patch fixes this problem by defining these masks as signed quantities.
We then rely on sign extension to do the right thing.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/page.h           |    2 +-
 arch/arm/include/asm/pgtable-3level.h |    6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ecf9019..1e0fe08 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT		12
 #define PAGE_SIZE		(_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK		(~(PAGE_SIZE-1))
+#define PAGE_MASK		(~((1 << PAGE_SHIFT) - 1))
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index b249035..ae39d11 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -48,16 +48,16 @@
 #define PMD_SHIFT		21
 
 #define PMD_SIZE		(1UL << PMD_SHIFT)
-#define PMD_MASK		(~(PMD_SIZE-1))
+#define PMD_MASK		(~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK		(~(PGDIR_SIZE-1))
+#define PGDIR_MASK		(~((1 << PGDIR_SHIFT) - 1))
 
 /*
  * section address mask and size definitions.
  */
 #define SECTION_SHIFT		21
 #define SECTION_SIZE		(1UL << SECTION_SHIFT)
-#define SECTION_MASK		(~(SECTION_SIZE-1))
+#define SECTION_MASK		(~((1 << SECTION_SHIFT) - 1))
 
 #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
 
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:46 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:46 -0400
Subject: [PATCH v2 03/22] ARM: use late patch framework for phys-virt patching
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-4-git-send-email-cyril@ti.com>

This patch replaces the original physical offset patching implementation
with one that uses the newly added patching framework.  In the process, we now
unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
head.S code.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/Kconfig              |    1 +
 arch/arm/include/asm/memory.h |   26 +++--------
 arch/arm/kernel/armksyms.c    |    4 --
 arch/arm/kernel/head.S        |   95 +++++++----------------------------------
 arch/arm/kernel/module.c      |    5 ---
 arch/arm/kernel/setup.c       |   12 ++++++
 arch/arm/kernel/vmlinux.lds.S |    5 ---
 7 files changed, 36 insertions(+), 112 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7e552dc..9ac86ea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -199,6 +199,7 @@ config ARM_PATCH_PHYS_VIRT
 	default y
 	depends on !XIP_KERNEL && MMU
 	depends on !ARCH_REALVIEW || !SPARSEMEM
+	select ARM_RUNTIME_PATCH
 	help
 	  Patch phys-to-virt and virt-to-phys translation functions at
 	  boot and module load time according to the position of the
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e965f1b..3d93779 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/runtime-patch.h>
+
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -151,35 +153,21 @@
 #ifndef __virt_to_phys
 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 
-/*
- * Constants used to force the right instruction encodings and shifts
- * so that all we need to do is modify the 8-bit constant field.
- */
-#define __PV_BITS_31_24	0x81000000
-
-extern unsigned long __pv_phys_offset;
-#define PHYS_OFFSET __pv_phys_offset
-
-#define __pv_stub(from,to,instr,type)			\
-	__asm__("@ __pv_stub\n"				\
-	"1:	" instr "	%0, %1, %2\n"		\
-	"	.pushsection .pv_table,\"a\"\n"		\
-	"	.long	1b\n"				\
-	"	.popsection\n"				\
-	: "=r" (to)					\
-	: "r" (from), "I" (type))
+extern unsigned long	__pv_offset;
+extern unsigned long	__pv_phys_offset;
+#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
 
 static inline unsigned long __virt_to_phys(unsigned long x)
 {
 	unsigned long t;
-	__pv_stub(x, t, "add", __PV_BITS_31_24);
+	early_patch_imm8("add", t, x, __pv_offset, 0);
 	return t;
 }
 
 static inline unsigned long __phys_to_virt(unsigned long x)
 {
 	unsigned long t;
-	__pv_stub(x, t, "sub", __PV_BITS_31_24);
+	early_patch_imm8("sub", t, x, __pv_offset, 0);
 	return t;
 }
 #else
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 60d3b73..6b388f8 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -152,7 +152,3 @@ EXPORT_SYMBOL(mcount);
 #endif
 EXPORT_SYMBOL(__gnu_mcount_nc);
 #endif
-
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
-EXPORT_SYMBOL(__pv_phys_offset);
-#endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3db960e..69a3c09 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -117,7 +117,7 @@ ENTRY(stext)
 	bl	__fixup_smp
 #endif
 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
-	bl	__fixup_pv_table
+	bl	__fixup_pv_offsets
 #endif
 	bl	__create_page_tables
 
@@ -511,92 +511,29 @@ ENDPROC(fixup_smp)
 
 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 
-/* __fixup_pv_table - patch the stub instructions with the delta between
- * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
- * can be expressed by an immediate shifter operand. The stub instruction
- * has a form of '(add|sub) rd, rn, #imm'.
+/*
+ * __fixup_pv_offsets - update __pv_offset and __pv_phys_offset based on the
+ * runtime location of the kernel.
  */
 	__HEAD
-__fixup_pv_table:
+__fixup_pv_offsets:
 	adr	r0, 1f
-	ldmia	r0, {r3-r5, r7}
+	ldmia	r0, {r3-r6}
 	sub	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
-	add	r4, r4, r3	@ adjust table start address
-	add	r5, r5, r3	@ adjust table end address
-	add	r7, r7, r3	@ adjust __pv_phys_offset address
-	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset
-	mov	r6, r3, lsr #24	@ constant for add/sub instructions
-	teq	r3, r6, lsl #24 @ must be 16MiB aligned
-THUMB(	it	ne		@ cross section branch )
-	bne	__error
-	str	r6, [r7, #4]	@ save to __pv_offset
-	b	__fixup_a_pv_table
-ENDPROC(__fixup_pv_table)
+	add	r4, r4, r3	@ virt_to_phys(__pv_phys_offset)
+	add	r5, r5, r3	@ virt_to_phys(__pv_offset)
+	add	r6, r6, r3	@ virt_to_phys(PAGE_OFFSET) = PHYS_OFFSET
+	str	r6, [r4]	@ save __pv_phys_offset
+	str	r3, [r5]	@ save __pv_offset
+	mov	pc, lr
+ENDPROC(__fixup_pv_offsets)
 
 	.align
 1:	.long	.
-	.long	__pv_table_begin
-	.long	__pv_table_end
-2:	.long	__pv_phys_offset
-
-	.text
-__fixup_a_pv_table:
-#ifdef CONFIG_THUMB2_KERNEL
-	lsls	r6, #24
-	beq	2f
-	clz	r7, r6
-	lsr	r6, #24
-	lsl	r6, r7
-	bic	r6, #0x0080
-	lsrs	r7, #1
-	orrcs	r6, #0x0080
-	orr	r6, r6, r7, lsl #12
-	orr	r6, #0x4000
-	b	2f
-1:	add     r7, r3
-	ldrh	ip, [r7, #2]
-	and	ip, 0x8f00
-	orr	ip, r6	@ mask in offset bits 31-24
-	strh	ip, [r7, #2]
-2:	cmp	r4, r5
-	ldrcc	r7, [r4], #4	@ use branch for delay slot
-	bcc	1b
-	bx	lr
-#else
-	b	2f
-1:	ldr	ip, [r7, r3]
-	bic	ip, ip, #0x000000ff
-	orr	ip, ip, r6	@ mask in offset bits 31-24
-	str	ip, [r7, r3]
-2:	cmp	r4, r5
-	ldrcc	r7, [r4], #4	@ use branch for delay slot
-	bcc	1b
-	mov	pc, lr
+	.long	__pv_phys_offset
+	.long	__pv_offset
+	.long	PAGE_OFFSET
 #endif
-ENDPROC(__fixup_a_pv_table)
-
-ENTRY(fixup_pv_table)
-	stmfd	sp!, {r4 - r7, lr}
-	ldr	r2, 2f			@ get address of __pv_phys_offset
-	mov	r3, #0			@ no offset
-	mov	r4, r0			@ r0 = table start
-	add	r5, r0, r1		@ r1 = table size
-	ldr	r6, [r2, #4]		@ get __pv_offset
-	bl	__fixup_a_pv_table
-	ldmfd	sp!, {r4 - r7, pc}
-ENDPROC(fixup_pv_table)
 
-	.align
-2:	.long	__pv_phys_offset
-
-	.data
-	.globl	__pv_phys_offset
-	.type	__pv_phys_offset, %object
-__pv_phys_offset:
-	.long	0
-	.size	__pv_phys_offset, . - __pv_phys_offset
-__pv_offset:
-	.long	0
-#endif
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index dcebf80..ac13dd5 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -317,11 +317,6 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
 					         maps[i].txt_sec->sh_addr,
 					         maps[i].txt_sec->sh_size);
 #endif
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
-	s = find_mod_section(hdr, sechdrs, ".pv_table");
-	if (s)
-		fixup_pv_table((void *)s->sh_addr, s->sh_size);
-#endif
 	s = find_mod_section(hdr, sechdrs, ".runtime.patch.table");
 	if (s)
 		runtime_patch((void *)s->sh_addr, s->sh_size);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 669bbf0..59e0f57 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -152,6 +152,18 @@ static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '
 
 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
 
+#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
+
+/*
+ * These are initialized in head.S code prior to BSS getting cleared out.
+ * The initializers here prevent these from landing in the BSS section.
+ */
+unsigned long __pv_offset = 0xdeadbeef;
+unsigned long __pv_phys_offset = 0xdeadbeef;
+EXPORT_SYMBOL(__pv_phys_offset);
+
+#endif
+
 /*
  * Standard memory resources
  */
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index ea35ca0..2080111 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -162,11 +162,6 @@ SECTIONS
 		__smpalt_end = .;
 	}
 #endif
-	.init.pv_table : {
-		__pv_table_begin = .;
-		*(.pv_table)
-		__pv_table_end = .;
-	}
 	.init.runtime_patch_table : {
 		__runtime_patch_table_begin = .;
 		*(.runtime.patch.table)
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:43 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:43 -0400
Subject: [PATCH v2 00/22] Introducing the TI Keystone platform
Message-ID: <1344648306-15619-1-git-send-email-cyril@ti.com>

This series is a follow on to the series posted earlier (archived at [1]).

Patches 01/22 .. 09/22 of this series have been pretty intensively reviewed;
thanks to all who helped.  We've modified per feedback, and these should be in
reasonable shape.

Patches 10/22 .. 19/22 of this series have not been very widely reviewed.
We'd very much appreciate eyeballs here.

Patches 20/22 .. 22/22 of this series are specific to the TI Keystone platform.
These are not ready to be merged in.  These are being provided here for the sake
of completeness, and to better illustrate the other patches in this series.
These are dependent on the smpops patches (see [2]).

These patches are also available on the following git repository:
git://arago-project.org/git/projects/linux-keystone.git keystone-v2


[1] - http://thread.gmane.org/gmane.linux.kernel/1336081
[2] - http://permalink.gmane.org/gmane.linux.ports.arm.kernel/171540


Series changelog:

(01/22) ARM: add mechanism for late code patching
  (v2)	pulled runtime patching code into separate source files
  (v2)	reordered arguments to patch macros for consistency with assembly
	"Rd, Rt, imm" ordering
  (v2)	added support for mov immediate patching
  (v2)	cache flush patched instructions instead of entire kernel code
  (v2)	pack patch table to reduce table volume
  (v2)	add to module vermagic to reflect abi change
  (v2)	misc. cleanups in naming and structure

(02/22) ARM: add self test for runtime patch mechanism
  (v2)	added init-time tests to verify instruction encoding

(03/22) ARM: use late patch framework for phys-virt patching
  (v2)	move __pv_offset and __pv_phys_offset to C code
  (v2)	restore conditional init of __pv_offset and __pv_phys_offset

(04/22) ARM: LPAE: use phys_addr_t on virt <--> phys conversion
  (v2)	fix patched __phys_to_virt() to use 32-bit operand
  (v2)	convert non-patch __phys_to_virt and __virt_to_phys to inlines to retain
	type checking

(05/22) ARM: LPAE: support 64-bit virt_to_phys patching
  (v2)	use phys_addr_t instead of split high/low phys_offsets
  (v2)	use mov immediate instead of add to zero when patching in high order
	physical address bits
  (v2)	fix __pv_phys_offset handling for big-endian
  (v2)	remove set_phys_offset()

(06/22) ARM: LPAE: use signed arithmetic for mask definitions
(07/22) ARM: LPAE: use phys_addr_t in alloc_init_pud()
(08/22) ARM: LPAE: use phys_addr_t in free_memmap()
  (v2)	unchanged from v1

(09/22) ARM: LPAE: use phys_addr_t for initrd location and size
  (v2)	revert to unsigned long for initrd size

(10/22) ARM: LPAE: use phys_addr_t in switch_mm()
  (v2)	use phys_addr_t instead of u64 in switch_mm()
  (v2)	revert on changes to v6 and v7-2level
  (v2)	fix register mapping for big-endian in v7-3level

(11/22) ARM: LPAE: use 64-bit accessors for TTBR registers
  (v2)	restore comment in cpu_set_reserved_ttbr0()

(12/22) ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem
(13/22) ARM: LPAE: factor out T1SZ and TTBR1 computations
  (v2)	unchanged from v1

(14/22) ARM: LPAE: accomodate >32-bit addresses for page table base
  (v2)	apply arch_pgd_shift only on lpae
  (v2)	move arch_pgd_shift definition to asm/memory.h
  (v2)	revert on changes to non-lpae procs
  (v2)	add check to ensure that the pgd physical address is aligned at an
	ARCH_PGD_SHIFT boundary

(15/22) ARM: mm: use physical addresses in highmem sanity checks
(16/22) ARM: mm: cleanup checks for membank overlap with vmalloc area
(17/22) ARM: mm: clean up membank size limit checks
(18/22) ARM: add virt_to_idmap for interconnect aliasing
  (v2)	unchanged from v1

(19/22) ARM: recreate kernel mappings in early_paging_init()
  (v2)	disable on !lpae at compile time


 arch/arm/Kconfig                                  |   36 ++++
 arch/arm/Makefile                                 |    1 +
 arch/arm/boot/dts/keystone-sim.dts                |   77 +++++++
 arch/arm/configs/keystone_defconfig               |   23 +++
 arch/arm/include/asm/mach/arch.h                  |    1 +
 arch/arm/include/asm/memory.h                     |   94 ++++++---
 arch/arm/include/asm/module.h                     |    7 +
 arch/arm/include/asm/page.h                       |    2 +-
 arch/arm/include/asm/pgtable-3level-hwdef.h       |   10 +
 arch/arm/include/asm/pgtable-3level.h             |    6 +-
 arch/arm/include/asm/proc-fns.h                   |   28 ++-
 arch/arm/include/asm/runtime-patch.h              |  175 ++++++++++++++++
 arch/arm/kernel/Makefile                          |    1 +
 arch/arm/kernel/armksyms.c                        |    4 -
 arch/arm/kernel/head.S                            |  107 +++-------
 arch/arm/kernel/module.c                          |    7 +-
 arch/arm/kernel/runtime-patch.c                   |  230 +++++++++++++++++++++
 arch/arm/kernel/setup.c                           |   18 ++
 arch/arm/kernel/smp.c                             |   11 +-
 arch/arm/kernel/vmlinux.lds.S                     |   13 +-
 arch/arm/mach-keystone/Makefile                   |    2 +
 arch/arm/mach-keystone/Makefile.boot              |    1 +
 arch/arm/mach-keystone/include/mach/debug-macro.S |   44 ++++
 arch/arm/mach-keystone/include/mach/memory.h      |   47 +++++
 arch/arm/mach-keystone/include/mach/timex.h       |   21 ++
 arch/arm/mach-keystone/include/mach/uncompress.h  |   24 +++
 arch/arm/mach-keystone/keystone.c                 |  124 +++++++++++
 arch/arm/mach-keystone/keystone.h                 |   23 +++
 arch/arm/mach-keystone/platsmp.c                  |   84 ++++++++
 arch/arm/mm/context.c                             |    9 +-
 arch/arm/mm/idmap.c                               |    4 +-
 arch/arm/mm/init.c                                |   19 +-
 arch/arm/mm/mmu.c                                 |  114 +++++++---
 arch/arm/mm/proc-v7-3level.S                      |   50 +++--
 34 files changed, 1214 insertions(+), 203 deletions(-)
 create mode 100644 arch/arm/boot/dts/keystone-sim.dts
 create mode 100644 arch/arm/configs/keystone_defconfig
 create mode 100644 arch/arm/include/asm/runtime-patch.h
 create mode 100644 arch/arm/kernel/runtime-patch.c
 create mode 100644 arch/arm/mach-keystone/Makefile
 create mode 100644 arch/arm/mach-keystone/Makefile.boot
 create mode 100644 arch/arm/mach-keystone/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-keystone/include/mach/memory.h
 create mode 100644 arch/arm/mach-keystone/include/mach/timex.h
 create mode 100644 arch/arm/mach-keystone/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-keystone/keystone.c
 create mode 100644 arch/arm/mach-keystone/keystone.h
 create mode 100644 arch/arm/mach-keystone/platsmp.c

-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:58 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:58 -0400
Subject: [PATCH v2 15/22] ARM: mm: use physical addresses in highmem sanity
 checks
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-16-git-send-email-cyril@ti.com>

This patch modifies the highmem sanity checking code to use physical addresses
instead.  This change eliminates the wrap-around problems associated with the
original virtual address based checks, and this simplifies the code a bit.

The one constraint imposed here is that low physical memory must be mapped in
a monotonically increasing fashion if there are multiple banks of memory,
i.e., x < y must => pa(x) < pa(y).

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/mm/mmu.c |   22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 53eeeb8..f764c03 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -895,6 +895,7 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
 	int i, j, highmem = 0;
+	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
 	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 		struct membank *bank = &meminfo.bank[j];
@@ -904,8 +905,7 @@ void __init sanity_check_meminfo(void)
 			highmem = 1;
 
 #ifdef CONFIG_HIGHMEM
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET)
+		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
@@ -914,8 +914,8 @@ void __init sanity_check_meminfo(void)
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
 		 */
-		if (!highmem && __va(bank->start) < vmalloc_min &&
-		    bank->size > vmalloc_min - __va(bank->start)) {
+		if (!highmem && bank->start < vmalloc_limit &&
+		    bank->size > vmalloc_limit - bank->start) {
 			if (meminfo.nr_banks >= NR_BANKS) {
 				printk(KERN_CRIT "NR_BANKS too low, "
 						 "ignoring high memory\n");
@@ -924,12 +924,12 @@ void __init sanity_check_meminfo(void)
 					(meminfo.nr_banks - i) * sizeof(*bank));
 				meminfo.nr_banks++;
 				i++;
-				bank[1].size -= vmalloc_min - __va(bank->start);
-				bank[1].start = __pa(vmalloc_min - 1) + 1;
+				bank[1].size -= vmalloc_limit - bank->start;
+				bank[1].start = vmalloc_limit;
 				bank[1].highmem = highmem = 1;
 				j++;
 			}
-			bank->size = vmalloc_min - __va(bank->start);
+			bank->size = vmalloc_limit - bank->start;
 		}
 #else
 		bank->highmem = highmem;
@@ -949,8 +949,7 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would entirely overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start) >= vmalloc_min ||
-		    __va(bank->start) < (void *)PAGE_OFFSET) {
+		if (bank->start >= vmalloc_limit) {
 			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
 			       "(vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
@@ -962,9 +961,8 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start + bank->size) > vmalloc_min ||
-		    __va(bank->start + bank->size) < __va(bank->start)) {
-			unsigned long newsize = vmalloc_min - __va(bank->start);
+		if (bank->start + bank->size > vmalloc_limit)
+			unsigned long newsize = vmalloc_limit - bank->start;
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
 			       (unsigned long long)bank->start,
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:25:02 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:25:02 -0400
Subject: [PATCH v2 19/22] ARM: recreate kernel mappings in early_paging_init()
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-20-git-send-email-cyril@ti.com>

This patch adds a step in the init sequence, in order to recreate the kernel
code/data page table mappings prior to full paging initialization.  This is
necessary on LPAE systems that run out of a physical address space outside the
4G limit.  On these systems, this implementation provides a machine descriptor
hook that allows the PHYS_OFFSET to be overridden in a machine specific
fashion.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/mach/arch.h |    1 +
 arch/arm/kernel/setup.c          |    3 ++
 arch/arm/mm/mmu.c                |   65 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 0b1c94b..2b9ecc5 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -37,6 +37,7 @@ struct machine_desc {
 	char			restart_mode;	/* default restart mode	*/
 	void			(*fixup)(struct tag *, char **,
 					 struct meminfo *);
+	void			(*init_meminfo)(void);
 	void			(*reserve)(void);/* reserve mem blocks	*/
 	void			(*map_io)(void);/* IO mapping function	*/
 	void			(*init_early)(void);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index edb4f42..e37cbaf 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -79,6 +79,7 @@ static int __init fpe_setup(char *line)
 __setup("fpe=", fpe_setup);
 #endif
 
+extern void early_paging_init(struct machine_desc *, struct proc_info_list *);
 extern void paging_init(struct machine_desc *desc);
 extern void sanity_check_meminfo(void);
 extern void reboot_setup(char *str);
@@ -978,6 +979,8 @@ void __init setup_arch(char **cmdline_p)
 	parse_early_param();
 
 	sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
+
+	early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
 	sanity_check_meminfo();
 	arm_memblock_init(&meminfo, mdesc);
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 662684b..5d240da 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -28,6 +28,7 @@
 #include <asm/highmem.h>
 #include <asm/system_info.h>
 #include <asm/traps.h>
+#include <asm/procinfo.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -1168,6 +1169,70 @@ static void __init map_lowmem(void)
 	}
 }
 
+#ifdef CONFIG_ARM_LPAE
+/*
+ * early_paging_init() recreates boot time page table setup, allowing machines
+ * to switch over to a high (>4G) address space on LPAE systems
+ */
+void __init early_paging_init(struct machine_desc *mdesc,
+			      struct proc_info_list *procinfo)
+{
+	pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
+	unsigned long map_start, map_end;
+	pgd_t *pgd0, *pgdk;
+	pud_t *pud0, *pudk;
+	pmd_t *pmd0, *pmdk;
+	phys_addr_t phys;
+	int i;
+
+	/* remap kernel code and data */
+	map_start = init_mm.start_code;
+	map_end   = init_mm.brk;
+
+	/* get a handle on things... */
+	pgd0 = pgd_offset_k(0);
+	pud0 = pud_offset(pgd0, 0);
+	pmd0 = pmd_offset(pud0, 0);
+
+	pgdk = pgd_offset_k(map_start);
+	pudk = pud_offset(pgdk, map_start);
+	pmdk = pmd_offset(pudk, map_start);
+
+	phys = PHYS_OFFSET;
+
+	if (mdesc->init_meminfo)
+		mdesc->init_meminfo();
+
+	/* remap level 1 table */
+	for (i = 0; i < PTRS_PER_PGD; i++) {
+		*pud0++ = __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER);
+		pmd0 += PTRS_PER_PMD;
+	}
+
+	/* remap pmds for kernel mapping */
+	phys = __pa(map_start) & PMD_MASK;
+	do {
+		*pmdk++ = __pmd(phys | pmdprot);
+		phys += PMD_SIZE;
+	} while (phys < map_end);
+
+	flush_cache_all();
+	cpu_set_ttbr(0, __pa(pgd0));
+	cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
+	local_flush_tlb_all();
+}
+
+#else
+
+void __init early_paging_init(struct machine_desc *mdesc,
+			      struct proc_info_list *procinfo)
+{
+	if (mdesc->init_meminfo)
+		mdesc->init_meminfo();
+}
+
+#endif
+
 /*
  * paging_init() sets up the page tables, initialises the zone memory
  * maps, and sets up the zero page, bad page and bad page tables.
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:55 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:55 -0400
Subject: [PATCH v2 12/22] ARM: LPAE: define ARCH_LOW_ADDRESS_LIMIT for bootmem
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-13-git-send-email-cyril@ti.com>

This patch adds an architecture defined override for ARCH_LOW_ADDRESS_LIMIT.
On PAE systems, the absence of this override causes bootmem to incorrectly
limit itself to 32-bit addressable physical memory.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/memory.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index dc5fbf3..64db5a4 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -292,6 +292,8 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define arch_is_coherent()		0
 #endif
 
+#define ARCH_LOW_ADDRESS_LIMIT		PHYS_MASK
+
 #endif
 
 #include <asm-generic/memory_model.h>
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:25:01 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:25:01 -0400
Subject: [PATCH v2 18/22] ARM: add virt_to_idmap for interconnect aliasing
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-19-git-send-email-cyril@ti.com>

From: Vitaly Andrianov <vitalya at ti.com>

On some PAE systems (e.g. TI Keystone), memory is above the 32-bit addressible
limit, and the interconnect provides an aliased view of parts of physical
memory in the 32-bit addressible space.  This alias is strictly for boot time
usage, and is not otherwise usable because of coherency limitations.

On such systems, the idmap mechanism needs to take this aliased mapping into
account.  This patch introduces a virt_to_idmap() macro, which can be used on
such sub-architectures to represent the interconnect supported boot time
alias.  Most other systems would leave this macro untouched, i.e., do a simply
virt_to_phys() and nothing more.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/include/asm/memory.h |    9 +++++++++
 arch/arm/kernel/smp.c         |    2 +-
 arch/arm/mm/idmap.c           |    4 ++--
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e5d0cc8..59f101c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -257,6 +257,15 @@ static inline void *phys_to_virt(phys_addr_t x)
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
 
 /*
+ * These are for systems that have a hardware interconnect supported alias of
+ * physical memory for idmap purposes.  Most cases should leave these
+ * untouched.
+ */
+#ifndef virt_to_idmap
+#define virt_to_idmap(x) virt_to_phys(x)
+#endif
+
+/*
  * Virtual <-> DMA view memory address translations
  * Again, these are *only* valid on the kernel direct mapped RAM
  * memory.  Use of these is *deprecated* (and that doesn't mean
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 9831716..628f895 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -62,7 +62,7 @@ static DECLARE_COMPLETION(cpu_running);
 
 static unsigned long get_arch_pgd(pgd_t *pgd)
 {
-	phys_addr_t pgdir = virt_to_phys(pgd);
+	phys_addr_t pgdir = virt_to_idmap(pgd);
 	BUG_ON(pgdir & ARCH_PGD_MASK);
 	return pgdir >> ARCH_PGD_SHIFT;
 }
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index ab88ed4..919cb6e 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -85,8 +85,8 @@ static int __init init_static_idmap(void)
 		return -ENOMEM;
 
 	/* Add an identity mapping for the physical address of the section. */
-	idmap_start = virt_to_phys((void *)__idmap_text_start);
-	idmap_end = virt_to_phys((void *)__idmap_text_end);
+	idmap_start = virt_to_idmap((void *)__idmap_text_start);
+	idmap_end = virt_to_idmap((void *)__idmap_text_end);
 
 	pr_info("Setting up static identity map for 0x%llx - 0x%llx\n",
 		(long long)idmap_start, (long long)idmap_end);
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:51 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:51 -0400
Subject: [PATCH v2 08/22] ARM: LPAE: use phys_addr_t in free_memmap()
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-9-git-send-email-cyril@ti.com>

From: Vitaly Andrianov <vitalya at ti.com>

The free_memmap() was mistakenly using unsigned long type to represent
physical addresses.  This breaks on PAE systems where memory could be placed
above the 32-bit addressible limit.

This patch fixes this function to properly use phys_addr_t instead.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/mm/init.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9aec41f..19ba70b 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -457,7 +457,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
 	struct page *start_pg, *end_pg;
-	unsigned long pg, pgend;
+	phys_addr_t pg, pgend;
 
 	/*
 	 * Convert start_pfn/end_pfn to a struct page pointer.
@@ -469,8 +469,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 	 * Convert to physical addresses, and
 	 * round start upwards and end downwards.
 	 */
-	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
-	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+	pg = PAGE_ALIGN(__pa(start_pg));
+	pgend = __pa(end_pg) & PAGE_MASK;
 
 	/*
 	 * If there are free pages between these,
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:54 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:54 -0400
Subject: [PATCH v2 11/22] ARM: LPAE: use 64-bit accessors for TTBR registers
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-12-git-send-email-cyril@ti.com>

This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
the LPAE version of cpu_set_reserved_ttbr0() to use these instead.

In the process, we also fix these functions to correctly handle cases
where the physical address lies beyond the 4G limit of 32-bit addressing.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/proc-fns.h |   24 +++++++++++++++++++-----
 arch/arm/mm/context.c           |    9 ++-------
 2 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 75b5f14..24224df 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -116,13 +116,27 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)					\
+	({							\
+		u64 ttbr;					\
+		__asm__("mrrc	p15, " #nr ", %Q0, %R0, c2"	\
+			: "=r" (ttbr)				\
+			: : "cc");				\
+		ttbr;						\
+	})
+
+#define cpu_set_ttbr(nr, val)					\
+	do {							\
+		u64 ttbr = val;					\
+		__asm__("mcrr	p15, " #nr ", %Q0, %R0, c2"	\
+			: : "r" (ttbr)				\
+			: "cc");				\
+	} while (0)
+
 #define cpu_get_pgd()	\
 	({						\
-		unsigned long pg, pg2;			\
-		__asm__("mrrc	p15, 0, %0, %1, c2"	\
-			: "=r" (pg), "=r" (pg2)		\
-			:				\
-			: "cc");			\
+		u64 pg = cpu_get_ttbr(0);		\
 		pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);	\
 		(pgd_t *)phys_to_virt(pg);		\
 	})
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 119bc52..cd27f35 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -16,6 +16,7 @@
 #include <asm/mmu_context.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
@@ -23,17 +24,11 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 #ifdef CONFIG_ARM_LPAE
 void cpu_set_reserved_ttbr0(void)
 {
-	unsigned long ttbl = __pa(swapper_pg_dir);
-	unsigned long ttbh = 0;
-
 	/*
 	 * Set TTBR0 to swapper_pg_dir which contains only global entries. The
 	 * ASID is set to 0.
 	 */
-	asm volatile(
-	"	mcrr	p15, 0, %0, %1, c2		@ set TTBR0\n"
-	:
-	: "r" (ttbl), "r" (ttbh));
+	cpu_set_ttbr(0, __pa(swapper_pg_dir));
 	isb();
 }
 #else
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:45 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:45 -0400
Subject: [PATCH v2 02/22] ARM: add self test for runtime patch mechanism
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-3-git-send-email-cyril@ti.com>

This patch adds basic sanity tests to ensure that the instruction patching
results in valid instruction encodings.  This is done by verifying the output
of the patch process against a vector of assembler generated instructions at
init time.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/Kconfig                |   12 ++++++++++++
 arch/arm/kernel/runtime-patch.c |   41 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d0a04ad..7e552dc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -211,6 +211,18 @@ config ARM_PATCH_PHYS_VIRT
 	  this feature (eg, building a kernel for a single machine) and
 	  you need to shrink the kernel to the minimal size.
 
+config ARM_RUNTIME_PATCH_TEST
+	bool "Self test runtime patching mechanism" if ARM_RUNTIME_PATCH
+	default y
+	help
+	  Select this to enable init time self checking for the runtime kernel
+	  patching mechanism.  This enables an ISA specific set of tests that
+	  ensure that the instructions generated by the patch process are
+	  consistent with those generated by the assembler at compile time.
+
+	  Only disable this option if you need to shrink the kernel to the
+	  minimal size.
+
 config NEED_MACH_IO_H
 	bool
 	help
diff --git a/arch/arm/kernel/runtime-patch.c b/arch/arm/kernel/runtime-patch.c
index fd37a2b..c471d8c 100644
--- a/arch/arm/kernel/runtime-patch.c
+++ b/arch/arm/kernel/runtime-patch.c
@@ -163,6 +163,44 @@ static int apply_patch_imm8(const struct patch_info *p)
 	return 0;
 }
 
+#ifdef CONFIG_ARM_RUNTIME_PATCH_TEST
+static void __init __used __naked __patch_test_code_imm8(void)
+{
+	__asm__ __volatile__ (
+		"	.irp	shift1, 0, 6, 12, 18\n"
+		"	.irp	shift2, 0, 1, 2, 3, 4, 5\n"
+		"	add     r1, r2, #(0x41 << (\\shift1 + \\shift2))\n"
+		"	.endr\n"
+		"	.endr\n"
+		"	.word	0\n"
+		: : :
+	);
+}
+
+static void __init test_patch_imm8(void)
+{
+	u32 test_code_addr = (u32)(&__patch_test_code_imm8);
+	u32 *test_code = (u32 *)(test_code_addr & ~0x3);
+	int i, ret;
+	u32 ninsn, insn;
+
+	insn = test_code[0];
+	for (i = 0; test_code[i]; i++) {
+		ret = do_patch_imm8(insn, 0x41 << i, &ninsn);
+		if (ret < 0)
+			pr_err("runtime patch (imm8): failed at shift %d\n", i);
+		else if (ninsn != test_code[i])
+			pr_err("runtime patch (imm8): failed, need %x got %x\n",
+			       test_code[i], ninsn);
+	}
+}
+
+static void __init runtime_patch_test(void)
+{
+	test_patch_imm8();
+}
+#endif
+
 int runtime_patch(const void *table, unsigned size)
 {
 	const struct patch_info *p = table, *end = (table + size);
@@ -185,5 +223,8 @@ void __init runtime_patch_kernel(void)
 	const void *start = &__runtime_patch_table_begin;
 	const void *end   = &__runtime_patch_table_end;
 
+#ifdef CONFIG_ARM_RUNTIME_PATCH_TEST
+	runtime_patch_test();
+#endif
 	BUG_ON(runtime_patch(start, end - start));
 }
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:59 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:59 -0400
Subject: [PATCH v2 16/22] ARM: mm: cleanup checks for membank overlap with
 vmalloc area
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-17-git-send-email-cyril@ti.com>

On Keystone platforms, physical memory is entirely outside the 32-bit
addressible range.  Therefore, the (bank->start > ULONG_MAX) check below marks
the entire system memory as highmem, and this causes unpleasentness all over.

This patch eliminates the extra bank start check (against ULONG_MAX) by
checking bank->start against the physical address corresponding to vmalloc_min
instead.

In the process, this patch also cleans up parts of the highmem sanity check
code by removing what has now become a redundant check for banks that entirely
overlap with the vmalloc range.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/mm/mmu.c |   19 +------------------
 1 file changed, 1 insertion(+), 18 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f764c03..3d685c6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -901,15 +901,12 @@ void __init sanity_check_meminfo(void)
 		struct membank *bank = &meminfo.bank[j];
 		*bank = meminfo.bank[i];
 
-		if (bank->start > ULONG_MAX)
-			highmem = 1;
-
-#ifdef CONFIG_HIGHMEM
 		if (bank->start >= vmalloc_limit)
 			highmem = 1;
 
 		bank->highmem = highmem;
 
+#ifdef CONFIG_HIGHMEM
 		/*
 		 * Split those memory banks which are partially overlapping
 		 * the vmalloc area greatly simplifying things later.
@@ -932,8 +929,6 @@ void __init sanity_check_meminfo(void)
 			bank->size = vmalloc_limit - bank->start;
 		}
 #else
-		bank->highmem = highmem;
-
 		/*
 		 * Highmem banks not allowed with !CONFIG_HIGHMEM.
 		 */
@@ -946,18 +941,6 @@ void __init sanity_check_meminfo(void)
 		}
 
 		/*
-		 * Check whether this memory bank would entirely overlap
-		 * the vmalloc area.
-		 */
-		if (bank->start >= vmalloc_limit) {
-			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-			       "(vmalloc region overlap).\n",
-			       (unsigned long long)bank->start,
-			       (unsigned long long)bank->start + bank->size - 1);
-			continue;
-		}
-
-		/*
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:50 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:50 -0400
Subject: [PATCH v2 07/22] ARM: LPAE: use phys_addr_t in alloc_init_pud()
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-8-git-send-email-cyril@ti.com>

From: Vitaly Andrianov <vitalya at ti.com>

This patch fixes the alloc_init_pud() function to use phys_addr_t instead of
unsigned long when passing in the phys argument.

This is an extension to commit 97092e0c56830457af0639f6bd904537a150ea4a (ARM:
pgtable: use phys_addr_t for physical addresses), which applied similar changes
elsewhere in the ARM memory management code.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/mm/mmu.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d045..53eeeb8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -622,7 +622,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-	unsigned long end, unsigned long phys, const struct mem_type *type)
+				  unsigned long end, phys_addr_t phys,
+				  const struct mem_type *type)
 {
 	pud_t *pud = pud_offset(pgd, addr);
 	unsigned long next;
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:53 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:53 -0400
Subject: [PATCH v2 10/22] ARM: LPAE: use phys_addr_t in switch_mm()
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-11-git-send-email-cyril@ti.com>

This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/proc-fns.h |    4 ++--
 arch/arm/mm/proc-v7-3level.S    |   26 ++++++++++++++++++++++----
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb..75b5f14 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
 	/*
 	 * Set the page table
 	 */
-	void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+	void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
 	/*
 	 * Set a possibly extended PTE.  Non-extended PTEs should
 	 * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 8de0f1d..78bd88c 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,22 @@
 #define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)
 
+#define rzero	r3
+#ifndef CONFIG_ARM_LPAE
+#  define rpgdl	r0
+#  define rpgdh	rzero
+#  define rmm	r1
+#else
+#  define rmm	r2
+#ifndef __ARMEB__
+#  define rpgdl	r0
+#  define rpgdh	r1
+#else
+#  define rpgdl	r1
+#  define rpgdh	r0
+#endif
+#endif
+
 /*
  * cpu_v7_switch_mm(pgd_phys, tsk)
  *
@@ -47,10 +63,12 @@
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	and	r3, r1, #0xff
-	mov	r3, r3, lsl #(48 - 32)		@ ASID
-	mcrr	p15, 0, r0, r3, c2		@ set TTB 0
+	mov	rzero, #0
+	ldr	rmm, [rmm, #MM_CONTEXT_ID]	@ get mm->context.id
+	and	rmm, rmm, #0xff
+	mov	rmm, rmm, lsl #(48 - 32)	@ ASID
+	orr	rpgdh, rpgdh, rmm		@ upper 32-bits of pgd phys
+	mcrr	p15, 0, rpgdl, rpgdh, c2	@ set TTB 0
 	isb
 #endif
 	mov	pc, lr
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:56 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:56 -0400
Subject: [PATCH v2 13/22] ARM: LPAE: factor out T1SZ and TTBR1 computations
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-14-git-send-email-cyril@ti.com>

This patch moves the TTBR1 offset calculation and the T1SZ calculation out
of the TTB setup assembly code.  This should not affect functionality in
any way, but improves code readability as well as readability of subsequent
patches in this series.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
---
 arch/arm/include/asm/pgtable-3level-hwdef.h |   10 ++++++++++
 arch/arm/mm/proc-v7-3level.S                |   16 ++++------------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index d795282..b501650 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -74,4 +74,14 @@
 #define PHYS_MASK_SHIFT		(40)
 #define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)
 
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET	(1 << 4)		/* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET	(4096 * (1 + 3))	/* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET	0
+#endif
+
+#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 78bd88c..e28383f 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -137,18 +137,10 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 * booting secondary CPUs would end up using TTBR1 for the identity
 	 * mapping set up in TTBR0.
 	 */
-	bhi	9001f				@ PHYS_OFFSET > PAGE_OFFSET?
-	orr	\tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-	/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-	add	\ttbr1, \ttbr1, #1 << 4		@ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-	/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-	add	\ttbr1, \ttbr1, #4096 * (1 + 3)	@ only L2 used, skip pgd+3*pmd
-#endif
-	/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:	mcr	p15, 0, \tmp, c2, c0, 2		@ TTB control register
-	mcrr	p15, 1, \ttbr1, \zero, c2	@ load TTBR1
+	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
+	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
+	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
 	.endm
 
 	__CPUINIT
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:47 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:47 -0400
Subject: [PATCH v2 04/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-5-git-send-email-cyril@ti.com>

This patch fixes up the types used when converting back and forth between
physical and virtual addresses.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/include/asm/memory.h |   26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 3d93779..81e1714 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -157,22 +157,32 @@ extern unsigned long	__pv_offset;
 extern unsigned long	__pv_phys_offset;
 #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
 
-static inline unsigned long __virt_to_phys(unsigned long x)
+static inline phys_addr_t __virt_to_phys(unsigned long x)
 {
 	unsigned long t;
 	early_patch_imm8("add", t, x, __pv_offset, 0);
 	return t;
 }
 
-static inline unsigned long __phys_to_virt(unsigned long x)
+static inline unsigned long __phys_to_virt(phys_addr_t x)
 {
-	unsigned long t;
-	early_patch_imm8("sub", t, x, __pv_offset, 0);
+	unsigned long t, xlo = x;
+	early_patch_imm8("sub", t, xlo, __pv_offset, 0);
 	return t;
 }
+
 #else
-#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
-#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
+
+static inline phys_addr_t __virt_to_phys(unsigned long x)
+{
+	return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
+}
+
+static inline unsigned long __phys_to_virt(phys_addr_t x)
+{
+	return x - PHYS_OFFSET + PAGE_OFFSET;
+}
+
 #endif
 #endif
 
@@ -207,14 +217,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
 
 static inline void *phys_to_virt(phys_addr_t x)
 {
-	return (void *)(__phys_to_virt((unsigned long)(x)));
+	return (void *)__phys_to_virt(x);
 }
 
 /*
  * Drivers should NOT use these either.
  */
 #define __pa(x)			__virt_to_phys((unsigned long)(x))
-#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
+#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
 
 /*
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:48 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:48 -0400
Subject: [PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-6-git-send-email-cyril@ti.com>

This patch adds support for 64-bit physical addresses in virt_to_phys()
patching.  This does not do real 64-bit add/sub, but instead patches in the
upper 32-bits of the phys_offset directly into the output of virt_to_phys.

There is no corresponding change on the phys_to_virt() side, because
computations on the upper 32-bits would be discarded anyway.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/include/asm/memory.h |   22 ++++++++++++++++++----
 arch/arm/kernel/head.S        |    4 ++++
 arch/arm/kernel/setup.c       |    2 +-
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 81e1714..dc5fbf3 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -154,14 +154,28 @@
 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 
 extern unsigned long	__pv_offset;
-extern unsigned long	__pv_phys_offset;
+extern phys_addr_t	__pv_phys_offset;
 #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
 
 static inline phys_addr_t __virt_to_phys(unsigned long x)
 {
-	unsigned long t;
-	early_patch_imm8("add", t, x, __pv_offset, 0);
-	return t;
+	unsigned long tlo, thi;
+
+	early_patch_imm8("add", tlo, x, __pv_offset, 0);
+
+#ifdef CONFIG_ARM_LPAE
+	/*
+	 * On LPAE, we do not _need_ to do 64-bit arithmetic because the high
+	 * order 32 bits are never changed by the phys-virt offset.  We simply
+	 * patch in the high order physical address bits instead.
+	 */
+#ifdef __ARMEB__
+	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
+#else
+	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
+#endif
+#endif
+	return (u64)tlo | (u64)thi << 32;
 }
 
 static inline unsigned long __phys_to_virt(phys_addr_t x)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 69a3c09..61fb8df 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -530,7 +530,11 @@ ENDPROC(__fixup_pv_offsets)
 
 	.align
 1:	.long	.
+#if defined(CONFIG_ARM_LPAE) && defined(__ARMEB__)
+	.long	__pv_phys_offset + 4
+#else
 	.long	__pv_phys_offset
+#endif
 	.long	__pv_offset
 	.long	PAGE_OFFSET
 #endif
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 59e0f57..edb4f42 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -159,7 +159,7 @@ DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
  * The initializers here prevent these from landing in the BSS section.
  */
 unsigned long __pv_offset = 0xdeadbeef;
-unsigned long __pv_phys_offset = 0xdeadbeef;
+phys_addr_t   __pv_phys_offset = 0xdeadbeef;
 EXPORT_SYMBOL(__pv_phys_offset);
 
 #endif
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:24:44 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 21:24:44 -0400
Subject: [PATCH v2 01/22] ARM: add mechanism for late code patching
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-2-git-send-email-cyril@ti.com>

The original phys_to_virt/virt_to_phys patching implementation relied on early
patching prior to MMU initialization.  On PAE systems running out of >4G
address space, this would have entailed an additional round of patching after
switching over to the high address space.

The approach implemented here conceptually extends the original PHYS_OFFSET
patching implementation with the introduction of "early" patch stubs.  Early
patch code is required to be functional out of the box, even before the patch
is applied.  This is implemented by inserting functional (but inefficient)
load code into the .runtime.patch.code init section.  Having functional code
out of the box then allows us to defer the init time patch application until
later in the init sequence.

In addition to fitting better with our need for physical address-space
switch-over, this implementation should be somewhat more extensible by virtue
of its more readable (and hackable) C implementation.  This should prove
useful for other similar init time specialization needs, especially in light
of our multi-platform kernel initiative.

This code has been boot tested in both ARM and Thumb-2 modes on an ARMv7
(Cortex-A8) device.

Note: the obtuse use of stringified symbols in patch_stub() and
early_patch_stub() is intentional.  Theoretically this should have been
accomplished with formal operands passed into the asm block, but this requires
the use of the 'c' modifier for instantiating the long (e.g. .long %c0).
However, the 'c' modifier has been found to ICE certain versions of GCC, and
therefore we resort to stringified symbols here.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/Kconfig                     |    3 +
 arch/arm/include/asm/module.h        |    7 ++
 arch/arm/include/asm/runtime-patch.h |  175 +++++++++++++++++++++++++++++++
 arch/arm/kernel/Makefile             |    1 +
 arch/arm/kernel/module.c             |    4 +
 arch/arm/kernel/runtime-patch.c      |  189 ++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c              |    3 +
 arch/arm/kernel/vmlinux.lds.S        |   10 ++
 8 files changed, 392 insertions(+)
 create mode 100644 arch/arm/include/asm/runtime-patch.h
 create mode 100644 arch/arm/kernel/runtime-patch.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..d0a04ad 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -61,6 +61,9 @@ config ARM
 config ARM_HAS_SG_CHAIN
 	bool
 
+config ARM_RUNTIME_PATCH
+	bool
+
 config NEED_SG_DMA_LENGTH
 	bool
 
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 6c6809f..2090486 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -43,9 +43,16 @@ struct mod_arch_specific {
 #define MODULE_ARCH_VERMAGIC_ARMTHUMB ""
 #endif
 
+#ifdef CONFIG_ARM_RUNTIME_PATCH
+#define MODULE_ARCH_VERMAGIC_RT_PATCH "rt-patch "
+#else
+#define MODULE_ARCH_VERMAGIC_RT_PATCH ""
+#endif
+
 #define MODULE_ARCH_VERMAGIC \
 	MODULE_ARCH_VERMAGIC_ARMVSN \
 	MODULE_ARCH_VERMAGIC_ARMTHUMB \
+	MODULE_ARCH_VERMAGIC_RT_PATCH \
 	MODULE_ARCH_VERMAGIC_P2V
 
 #endif /* _ASM_ARM_MODULE_H */
diff --git a/arch/arm/include/asm/runtime-patch.h b/arch/arm/include/asm/runtime-patch.h
new file mode 100644
index 0000000..6c6e8a2
--- /dev/null
+++ b/arch/arm/include/asm/runtime-patch.h
@@ -0,0 +1,175 @@
+/*
+ * arch/arm/include/asm/runtime-patch.h
+ * Note: this file should not be included by non-asm/.h files
+ *
+ * Copyright 2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ARM_RUNTIME_PATCH_H
+#define __ASM_ARM_RUNTIME_PATCH_H
+
+#include <linux/stringify.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ARM_RUNTIME_PATCH
+
+struct patch_info {
+	void	*insn;
+	u16	 type;
+	u8	 insn_size;
+	u8	 data_size;
+	u32	 data[0];
+};
+
+#define patch_next(p)		((void *)(p) + sizeof(*(p)) + (p)->data_size)
+
+#define PATCH_TYPE_MASK		0x00ff
+#define PATCH_IMM8		0x0001
+
+#define PATCH_EARLY		0x8000
+
+#define patch_stub(type, code, patch_data, ...)				\
+	__asm__("@ patch stub\n"					\
+		"1:\n"							\
+		code							\
+		"2:\n"							\
+		"	.pushsection .runtime.patch.table, \"a\"\n"	\
+		"3:\n"							\
+		"	.word 1b\n"					\
+		"	.hword (" __stringify(type) ")\n"		\
+		"	.byte (2b-1b)\n"				\
+		"	.byte (5f-4f)\n"				\
+		"4:\n"							\
+		patch_data						\
+		"	.align\n"					\
+		"5:\n"							\
+		"	.popsection\n"					\
+		__VA_ARGS__)
+
+#define early_patch_stub(type, code, patch_data, ...)			\
+	__asm__("@ patch stub\n"					\
+		"1:\n"							\
+		"	b	6f\n"					\
+		"2:\n"							\
+		"	.pushsection .runtime.patch.table, \"a\"\n"	\
+		"3:\n"							\
+		"	.word 1b\n"					\
+		"	.hword (" __stringify(type | PATCH_EARLY) ")\n"	\
+		"	.byte (2b-1b)\n"				\
+		"	.byte (5f-4f)\n"				\
+		"4:\n"							\
+		patch_data						\
+		"	.align\n"					\
+		"5:\n"							\
+		"	.popsection\n"					\
+		"	.pushsection .runtime.patch.code, \"ax\"\n"	\
+		"6:\n"							\
+		code							\
+		"	b 2b\n"						\
+		"	.popsection\n"					\
+		__VA_ARGS__)
+
+/* constant used to force encoding */
+#define __IMM8		(0x81 << 24)
+
+/*
+ * patch_imm8() - init-time specialized binary operation (imm8 operand)
+ *		  This effectively does: to = from "insn" sym,
+ *		  where the value of sym is fixed at init-time, and is patched
+ *		  in as an immediate operand.  This value must be
+ *		  representible as an 8-bit quantity with an optional
+ *		  rotation.
+ *
+ *		  The stub code produced by this variant is non-functional
+ *		  prior to patching.  Use early_patch_imm8() if you need the
+ *		  code to be functional early on in the init sequence.
+ */
+#define patch_imm8(insn, to, from, sym, offset)				\
+	patch_stub(PATCH_IMM8,						\
+		   /* code */						\
+		   insn " %0, %1, %2\n",				\
+		   /* patch_data */					\
+		   ".long " __stringify(sym + offset) "\n"		\
+		   insn " %0, %1, %2\n",				\
+		   : "=r" (to)						\
+		   : "r" (from), "I" (__IMM8), "m" (sym)		\
+		   : "cc")
+
+/*
+ * patch_imm8_mov() - same as patch_imm8(), but for mov/mvn instructions
+ */
+#define patch_imm8_mov(insn, to, sym, offset)				\
+	patch_stub(PATCH_IMM8,						\
+		   /* code */						\
+		   insn " %0, %1\n",					\
+		   /* patch_data */					\
+		   ".long " __stringify(sym + offset) "\n"		\
+		   insn " %0, %1\n",					\
+		   : "=r" (to)						\
+		   : "I" (__IMM8), "m" (sym)				\
+		   : "cc")
+
+/*
+ * early_patch_imm8() - early functional variant of patch_imm8() above.  The
+ *			same restrictions on the constant apply here.  This
+ *			version emits workable (albeit inefficient) code at
+ *			compile-time, and therefore functions even prior to
+ *			patch application.
+ */
+#define early_patch_imm8(insn, to, from, sym, offset)			\
+	early_patch_stub(PATCH_IMM8,					\
+			 /* code */					\
+			 "ldr	%0, =" __stringify(sym + offset) "\n"	\
+			 "ldr	%0, [%0]\n"				\
+			 insn " %0, %1, %0\n",				\
+			 /* patch_data */				\
+			 ".long " __stringify(sym + offset) "\n"	\
+			 insn " %0, %1, %2\n",				\
+			 : "=&r" (to)					\
+			 : "r" (from), "I" (__IMM8), "m" (sym)		\
+			 : "cc")
+
+#define early_patch_imm8_mov(insn, to, sym, offset)			\
+	early_patch_stub(PATCH_IMM8,					\
+			 /* code */					\
+			 "ldr	%0, =" __stringify(sym + offset) "\n"	\
+			 "ldr	%0, [%0]\n"				\
+			 insn " %0, %0\n",				\
+			 /* patch_data */				\
+			 ".long " __stringify(sym + offset) "\n"	\
+			 insn " %0, %1\n",				\
+			 : "=&r" (to)					\
+			 : "I" (__IMM8), "m" (sym)			\
+			 : "cc")
+
+int runtime_patch(const void *table, unsigned size);
+void runtime_patch_kernel(void);
+
+#else
+
+static inline int runtime_patch(const void *table, unsigned size)
+{
+	return 0;
+}
+
+static inline void runtime_patch_kernel(void)
+{
+}
+
+#endif /* CONFIG_ARM_RUNTIME_PATCH */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_RUNTIME_PATCH_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..12cc1e7 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -81,5 +81,6 @@ endif
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
+obj-$(CONFIG_ARM_RUNTIME_PATCH)	+= runtime-patch.o
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..dcebf80 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -24,6 +24,7 @@
 #include <asm/sections.h>
 #include <asm/smp_plat.h>
 #include <asm/unwind.h>
+#include <asm/runtime-patch.h>
 
 #ifdef CONFIG_XIP_KERNEL
 /*
@@ -321,6 +322,9 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
 	if (s)
 		fixup_pv_table((void *)s->sh_addr, s->sh_size);
 #endif
+	s = find_mod_section(hdr, sechdrs, ".runtime.patch.table");
+	if (s)
+		runtime_patch((void *)s->sh_addr, s->sh_size);
 	s = find_mod_section(hdr, sechdrs, ".alt.smp.init");
 	if (s && !is_smp())
 #ifdef CONFIG_SMP_ON_UP
diff --git a/arch/arm/kernel/runtime-patch.c b/arch/arm/kernel/runtime-patch.c
new file mode 100644
index 0000000..fd37a2b
--- /dev/null
+++ b/arch/arm/kernel/runtime-patch.c
@@ -0,0 +1,189 @@
+/*
+ * arch/arm/kernel/runtime-patch.c
+ *
+ * Copyright 2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+#include <asm/opcodes.h>
+#include <asm/cacheflush.h>
+#include <asm/runtime-patch.h>
+
+static inline void flush_icache_insn(void *insn_ptr, int bytes)
+{
+	unsigned long insn_addr = (unsigned long)insn_ptr;
+	flush_icache_range(insn_addr, insn_addr + bytes - 1);
+}
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+static int do_patch_imm8(u32 insn, u32 imm, u32 *ninsn)
+{
+	u32 op, rot, val;
+	const u32 supported_ops = (BIT(0)  | /* and */
+				   BIT(1)  | /* bic */
+				   BIT(2)  | /* orr/mov */
+				   BIT(3)  | /* orn/mvn */
+				   BIT(4)  | /* eor */
+				   BIT(8)  | /* add */
+				   BIT(10) | /* adc */
+				   BIT(11) | /* sbc */
+				   BIT(12) | /* sub */
+				   BIT(13)); /* rsb */
+
+	insn = __mem_to_opcode_thumb32(insn);
+
+	if (!__opcode_is_thumb32(insn)) {
+		pr_err("patch: invalid thumb2 insn %08x\n", insn);
+		return -EINVAL;
+	}
+
+	/* allow only data processing (immediate)
+	 * 1111 0x0x xxx0 xxxx 0xxx xxxx xxxx xxxx */
+	if ((insn & 0xfa008000) != 0xf0000000) {
+		pr_err("patch: unknown insn %08x\n", insn);
+		return -EINVAL;
+	}
+
+	/* extract op code */
+	op = (insn >> 21) & 0xf;
+
+	/* disallow unsupported opcodes */
+	if ((supported_ops & BIT(op)) == 0) {
+		pr_err("patch: unsupported opcode %x\n", op);
+		return -EINVAL;
+	}
+
+	if (imm <= 0xff) {
+		rot = 0;
+		val = imm;
+	} else {
+		rot = 32 - fls(imm); /* clz */
+		if (imm & ~(0xff000000 >> rot)) {
+			pr_err("patch: constant overflow %08x\n", imm);
+			return -EINVAL;
+		}
+		val  = (imm >> (24 - rot)) & 0x7f;
+		rot += 8; /* encoded i:imm3:a */
+
+		/* pack least-sig rot bit into most-sig val bit */
+		val |= (rot & 1) << 7;
+		rot >>= 1;
+	}
+
+	*ninsn  = insn & ~(BIT(26) | 0x7 << 12 | 0xff);
+	*ninsn |= (rot >> 3) << 26;	/* field "i" */
+	*ninsn |= (rot & 0x7) << 12;	/* field "imm3" */
+	*ninsn |= val;
+	*ninsn  = __opcode_to_mem_thumb32(*ninsn);
+
+	return 0;
+}
+
+#else
+
+static int do_patch_imm8(u32 insn, u32 imm, u32 *ninsn)
+{
+	u32 rot, val, op;
+
+	insn = __mem_to_opcode_arm(insn);
+
+	/* disallow special unconditional instructions
+	 * 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
+	if ((insn >> 24) == 0xf) {
+		pr_err("patch: unconditional insn %08x\n", insn);
+		return -EINVAL;
+	}
+
+	/* allow only data processing (immediate)
+	 * xxxx 001x xxxx xxxx xxxx xxxx xxxx xxxx */
+	if (((insn >> 25) & 0x3) != 1) {
+		pr_err("patch: unknown insn %08x\n", insn);
+		return -EINVAL;
+	}
+
+	/* extract op code */
+	op = (insn >> 20) & 0x1f;
+
+	/* disallow unsupported 10xxx op codes */
+	if (((op >> 3) & 0x3) == 2) {
+		pr_err("patch: unsupported opcode %08x\n", insn);
+		return -EINVAL;
+	}
+
+	rot = imm ? __ffs(imm) / 2 : 0;
+	val = imm >> (rot * 2);
+	rot = (-rot) & 0xf;
+
+	/* does this fit in 8-bit? */
+	if (val > 0xff) {
+		pr_err("patch: constant overflow %08x\n", imm);
+		return -EINVAL;
+	}
+
+	/* patch in new immediate and rotation */
+	*ninsn = (insn & ~0xfff) | (rot << 8) | val;
+	*ninsn = __opcode_to_mem_arm(*ninsn);
+
+	return 0;
+}
+
+#endif	/* CONFIG_THUMB2_KERNEL */
+
+static int apply_patch_imm8(const struct patch_info *p)
+{
+	u32 *insn_ptr = p->insn;
+	int ret;
+
+	if (p->insn_size != sizeof(u32) || p->data_size != 2 * sizeof(u32)) {
+		pr_err("patch: bad patch, insn size %d, data size %d\n",
+		       p->insn_size, p->data_size);
+		return -EINVAL;
+	}
+
+	ret = do_patch_imm8(p->data[1], *(u32 *)p->data[0], insn_ptr);
+	if (ret < 0)
+		return ret;
+
+	flush_icache_insn(insn_ptr, sizeof(u32));
+
+	return 0;
+}
+
+int runtime_patch(const void *table, unsigned size)
+{
+	const struct patch_info *p = table, *end = (table + size);
+
+	for (p = table; p < end; p = patch_next(p)) {
+		int type = p->type & PATCH_TYPE_MASK;
+		int ret = -EINVAL;
+
+		if (type == PATCH_IMM8)
+			ret = apply_patch_imm8(p);
+		if (ret < 0)
+			return ret;
+	}
+	return 0;
+}
+
+void __init runtime_patch_kernel(void)
+{
+	extern unsigned __runtime_patch_table_begin, __runtime_patch_table_end;
+	const void *start = &__runtime_patch_table_begin;
+	const void *end   = &__runtime_patch_table_end;
+
+	BUG_ON(runtime_patch(start, end - start));
+}
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcec..669bbf0 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -55,6 +55,7 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/memblock.h>
+#include <asm/runtime-patch.h>
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
@@ -998,6 +999,8 @@ void __init setup_arch(char **cmdline_p)
 
 	if (mdesc->init_early)
 		mdesc->init_early();
+
+	runtime_patch_kernel();
 }
 
 
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 36ff15b..ea35ca0 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -167,6 +167,16 @@ SECTIONS
 		*(.pv_table)
 		__pv_table_end = .;
 	}
+	.init.runtime_patch_table : {
+		__runtime_patch_table_begin = .;
+		*(.runtime.patch.table)
+		__runtime_patch_table_end = .;
+	}
+	.init.runtime_patch_code : {
+		__runtime_patch_code_begin = .;
+		*(.runtime.patch.code)
+		__runtime_patch_code_end = .;
+	}
 	.init.data : {
 #ifndef CONFIG_XIP_KERNEL
 		INIT_DATA
-- 
1.7.9.5



From jason at lakedaemon.net  Fri Aug 10 22:39:47 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 02:39:47 +0000
Subject: [PATCH 3/3] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <cover.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
Message-ID: <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>

Also, disable DEBUG_KERNEL, enable SERIAL_OF_PLATFORM, and enable EMBEDDED

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/configs/kirkwood_defconfig |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 5a494a3..0865d2e 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -3,6 +3,9 @@ CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_KPROBES=y
@@ -17,6 +20,13 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_DOCKSTAR=y
@@ -89,6 +99,7 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -157,7 +168,6 @@ CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-- 
1.7.8.6



From jason at lakedaemon.net  Fri Aug 10 22:39:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 02:39:44 +0000
Subject: [PATCH 0/3] ARM: Kirkwood: update defconfig and fix ts219 dtb
Message-ID: <cover.1344651264.git.jason@lakedaemon.net>

This is a small series to update kirkwood_defconfig to include all of the new
DT boards.  And, finally, SERIAL_OF_PLATFORM is enabled. ;-)

There is one small fix for ts219.  When it was revised to split into two dts
files, Makefile.boot wasn't updated.  This caused a build failure for
'make dtbs'

Jason Cooper (3):
  ARM: Kirkwood: update defconfig
  ARM: Kirkwood: ts219: fix Makefile.boot after dts was split in two
  ARM: Kirkwood: add DT boards to defconfig

 arch/arm/configs/kirkwood_defconfig  |   37 +++++++++++++++------------------
 arch/arm/mach-kirkwood/Makefile.boot |    2 +-
 2 files changed, 18 insertions(+), 21 deletions(-)

-- 
1.7.8.6



From jason at lakedaemon.net  Fri Aug 10 22:39:46 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 02:39:46 +0000
Subject: [PATCH 2/3] ARM: Kirkwood: ts219: fix Makefile.boot after dts was
 split in two
In-Reply-To: <cover.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
Message-ID: <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/Makefile.boot |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 2a576ab..2ad83e2 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -7,7 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
 dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
 dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
 dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
-dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
+dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6281.dtb kirkwood-ts219-6282.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
-- 
1.7.8.6



From jason at lakedaemon.net  Fri Aug 10 22:39:45 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 02:39:45 +0000
Subject: [PATCH 1/3] ARM: Kirkwood: update defconfig
In-Reply-To: <cover.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
Message-ID: <8f635f63d0de5505ca735cfed2028cd9a2fece09.1344651264.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/configs/kirkwood_defconfig |   25 ++++++-------------------
 1 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af5..5a494a3 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,9 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +31,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +47,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +67,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +75,20 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +98,6 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +113,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +140,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +149,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +161,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
-- 
1.7.8.6



From cyril at ti.com  Fri Aug 10 22:40:43 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Fri, 10 Aug 2012 22:40:43 -0400
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <5025C62B.10407@ti.com>

On 8/10/2012 5:58 PM, Rohit Vaswani wrote:
> The current arch_timer only support accessing through CP15 interface.
> Add support for ARM processors that only support IO mapped register
> interface
>

It looks like this patch attempts to address both (a) non-percpu arch 
timers, and (b) memory mapped arch timers in one go.  These should 
probably be broken out into two distinct logical changes.

More below...

> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>   .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>   arch/arm/kernel/arch_timer.c                       |  259 ++++++++++++++++----
>   2 files changed, 223 insertions(+), 43 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
> index 52478c8..1c71799 100644
> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its per-processor interrupts.
>
>   - clock-frequency : The frequency of the main counter, in Hz. Optional.
>
> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI) interrupt
> +  In the default case i.e without this property, the timer irq is treated as a
> +  PPI interrupt. Optional.
> +

The handling of non-percpu IRQs looks broken.  The code does 
(enable/disable)_percpu_irq() on IRQs that may no longer be percpu.

> +- If the node address and reg is specified, the arch_timer will try to use the memory
> +  mapped timer. Optional.
> +
>   Example:
>
>   	timer {
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index 1d0d9df..09604b7 100644
> --- a/arch/arm/kernel/arch_timer.c
> +++ b/arch/arm/kernel/arch_timer.c
> @@ -18,6 +18,7 @@
>   #include <linux/clockchips.h>
>   #include <linux/interrupt.h>
>   #include <linux/of_irq.h>
> +#include <linux/of_address.h>
>   #include <linux/io.h>
>
>   #include <asm/cputype.h>
> @@ -29,8 +30,17 @@
>   static unsigned long arch_timer_rate;
>   static int arch_timer_ppi;
>   static int arch_timer_ppi2;
> +static int is_irq_percpu;
>
>   static struct clock_event_device __percpu **arch_timer_evt;
> +static void __iomem *timer_base;
> +

Are percpu memory mapped arch timers an impossibility?

> +struct arch_timer_operations {
> +	void (*reg_write)(int, u32);
> +	u32 (*reg_read)(int);
> +	cycle_t (*get_cntpct)(void);
> +	cycle_t (*get_cntvct)(void);
> +};
>
>   /*
>    * Architected system timer support.
> @@ -44,7 +54,29 @@ static struct clock_event_device __percpu **arch_timer_evt;
>   #define ARCH_TIMER_REG_FREQ		1
>   #define ARCH_TIMER_REG_TVAL		2
>
> -static void arch_timer_reg_write(int reg, u32 val)
> +/* Iomapped Register Offsets */
> +#define ARCH_TIMER_CNTP_LOW_REG		0x000
> +#define ARCH_TIMER_CNTP_HIGH_REG	0x004
> +#define ARCH_TIMER_CNTV_LOW_REG		0x008
> +#define ARCH_TIMER_CNTV_HIGH_REG	0x00C
> +#define ARCH_TIMER_CTRL_REG		0x02C
> +#define ARCH_TIMER_FREQ_REG		0x010
> +#define ARCH_TIMER_CNTP_TVAL_REG	0x028
> +#define ARCH_TIMER_CNTV_TVAL_REG	0x038
> +

ARCH_TIMER_CNTV_TVAL_REG appears to be unused here.

> +static void timer_reg_write_mem(int reg, u32 val)
> +{
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;
> +	}
> +}
> +

Wouldn't an array of offsets to map from ARCH_TIMER_REG_* to these 
memory mapped registers eliminate the need to switch-case your way 
through each register?

> +static void timer_reg_write_cp15(int reg, u32 val)
>   {
>   	switch (reg) {
>   	case ARCH_TIMER_REG_CTRL:
> @@ -58,7 +90,28 @@ static void arch_timer_reg_write(int reg, u32 val)
>   	isb();
>   }
>
> -static u32 arch_timer_reg_read(int reg)
> +static u32 timer_reg_read_mem(int reg)
> +{
> +	u32 val;
> +
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_FREQ:
> +		val = __raw_readl(timer_base + ARCH_TIMER_FREQ_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;
> +	default:
> +		BUG();
> +	}
> +
> +	return val;
> +}
> +

Same as above.

> +static u32 timer_reg_read_cp15(int reg)
>   {
>   	u32 val;
>
> @@ -79,6 +132,103 @@ static u32 arch_timer_reg_read(int reg)
>   	return val;
>   }
>
> +static cycle_t arch_counter_get_cntpct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTP_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntpct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntvct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTV_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +

Repetitive - the logic is identical to arch_counter_get_cntpct_mem() above.

> +static cycle_t arch_counter_get_cntvct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static struct arch_timer_operations arch_timer_ops_cp15 = {
> +	.reg_read = &timer_reg_read_cp15,
> +	.reg_write = &timer_reg_write_cp15,
> +	.get_cntpct = &arch_counter_get_cntpct_cp15,
> +	.get_cntvct = &arch_counter_get_cntvct_cp15,
> +};
> +
> +static struct arch_timer_operations arch_timer_ops_mem = {
> +	.reg_read = &timer_reg_read_mem,
> +	.reg_write = &timer_reg_write_mem,
> +	.get_cntpct = &arch_counter_get_cntpct_mem,
> +	.get_cntvct = &arch_counter_get_cntvct_mem,
> +};
> +
> +static struct arch_timer_operations *arch_specific_timer = &arch_timer_ops_cp15;
> +
> +static inline void arch_timer_reg_write(int reg, u32 val)
> +{
> +	arch_specific_timer->reg_write(reg, val);
> +}
> +
> +static inline u32 arch_timer_reg_read(int reg)
> +{
> +	return arch_specific_timer->reg_read(reg);
> +}
> +
> +static inline cycle_t arch_counter_get_cntpct(void)
> +{
> +	return arch_specific_timer->get_cntpct();
> +}
> +
> +static inline cycle_t arch_counter_get_cntvct(void)
> +{
> +	return arch_specific_timer->get_cntvct();
> +}
> +

The 4 pointer chasers above could lose some verbosity by being #defines.

> +static u32 notrace arch_counter_get_cntvct32(void)
> +{
> +	cycle_t cntvct = arch_counter_get_cntpct();

Shouldn't that be arch_counter_get_cntvct() instead?

> +
> +	/*
> +	 * The sched_clock infrastructure only knows about counters
> +	 * with at most 32bits. Forget about the upper 24 bits for the
> +	 * time being...
> +	 */
> +	return (u32)(cntvct & (u32)~0);
> +}
> +
> +static cycle_t arch_counter_read(struct clocksource *cs)
> +{
> +	return arch_counter_get_cntpct();
> +}
> +

Did the code really need to be moved around?  Some of the functions in 
this file appear to be entirely unchanged, but show up as both added and 
removed lines.

>   static irqreturn_t arch_timer_handler(int irq, void *dev_id)
>   {
>   	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> @@ -167,7 +317,9 @@ static int arch_timer_available(void)
>   {
>   	unsigned long freq;
>
> -	if (!local_timer_is_architected())
> +	if (timer_base)
> +		arch_specific_timer = &arch_timer_ops_mem;
> +	else if (!local_timer_is_architected())
>   		return -ENXIO;
>
>   	if (arch_timer_rate == 0) {
> @@ -188,41 +340,6 @@ static int arch_timer_available(void)
>   	return 0;
>   }
>
> -static inline cycle_t arch_counter_get_cntpct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static inline cycle_t arch_counter_get_cntvct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static u32 notrace arch_counter_get_cntvct32(void)
> -{
> -	cycle_t cntvct = arch_counter_get_cntvct();
> -
> -	/*
> -	 * The sched_clock infrastructure only knows about counters
> -	 * with at most 32bits. Forget about the upper 24 bits for the
> -	 * time being...
> -	 */
> -	return (u32)(cntvct & (u32)~0);
> -}
> -
> -static cycle_t arch_counter_read(struct clocksource *cs)
> -{
> -	return arch_counter_get_cntpct();
> -}
> -
>   static struct clocksource clocksource_counter = {
>   	.name	= "arch_sys_counter",
>   	.rating	= 400,
> @@ -262,8 +379,12 @@ static int __init arch_timer_register(void)
>
>   	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
>
> -	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
> +	if (is_irq_percpu)
> +		err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
>   				 "arch_timer", arch_timer_evt);
> +	else
> +		err = request_irq(arch_timer_ppi, arch_timer_handler, 0,
> +			"arch_timer", arch_timer_evt);
>   	if (err) {
>   		pr_err("arch_timer: can't register interrupt %d (%d)\n",
>   		       arch_timer_ppi, err);
> @@ -271,8 +392,13 @@ static int __init arch_timer_register(void)
>   	}
>
>   	if (arch_timer_ppi2) {
> -		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
> -					 "arch_timer", arch_timer_evt);
> +		if (is_irq_percpu)
> +			err = request_percpu_irq(arch_timer_ppi2,
> +					arch_timer_handler, "arch_timer",
> +					arch_timer_evt);
> +		else
> +			err = request_irq(arch_timer_ppi2, arch_timer_handler,
> +					0, "arch_timer", arch_timer_evt);
>   		if (err) {
>   			pr_err("arch_timer: can't register interrupt %d (%d)\n",
>   			       arch_timer_ppi2, err);
> @@ -314,10 +440,40 @@ static const struct of_device_id arch_timer_of_match[] __initconst = {
>   	{},
>   };
>
> +static int __init arch_timer_base_init(void)
> +{
> +	struct device_node *np;
> +
> +	if (!timer_base) {
> +		np = of_find_matching_node(NULL, arch_timer_of_match);
> +		if (!np) {
> +			pr_err("arch_timer: can't find DT node\n");
> +			return -ENODEV;
> +		}
> +
> +		if (of_get_address(np, 0, NULL, NULL)) {
> +			timer_base = of_iomap(np, 0);
> +			if (!timer_base) {
> +				pr_err("arch_timer: cant map timer base\n");
> +				return -ENOMEM;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static inline void __init arch_timer_base_free(void)
> +{
> +	if (timer_base)
> +		iounmap(timer_base);
> +}
> +
>   int __init arch_timer_of_register(void)
>   {
>   	struct device_node *np;
>   	u32 freq;
> +	int ret;
>
>   	np = of_find_matching_node(NULL, arch_timer_of_match);
>   	if (!np) {
> @@ -331,20 +487,37 @@ int __init arch_timer_of_register(void)
>
>   	arch_timer_ppi = irq_of_parse_and_map(np, 0);
>   	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
> +
> +	ret = arch_timer_base_init();
> +	if (ret)
> +		return ret;
> +
> +	is_irq_percpu = !(of_property_read_bool(np, "irq-is-not-percpu"));
> +
>   	pr_info("arch_timer: found %s irqs %d %d\n",
>   		np->name, arch_timer_ppi, arch_timer_ppi2);
>
> -	return arch_timer_register();
> +	ret = arch_timer_register();
> +	if (ret)
> +		arch_timer_base_free();
> +
> +	return ret;
>   }
>
>   int __init arch_timer_sched_clock_init(void)
>   {
>   	int err;
>
> -	err = arch_timer_available();
> +	err = arch_timer_base_init();
>   	if (err)
>   		return err;
>
> +	err = arch_timer_available();
> +	if (err) {
> +		arch_timer_base_free();
> +		return err;
> +	}
> +
>   	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
>   	return 0;
>   }
>

-- 
Cheers
- Cyril


From shijie8 at gmail.com  Sat Aug 11 11:25:28 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 11:25:28 -0400
Subject: [PATCH v2] mtd: gpmi: add NAND write verify support
Message-ID: <1344698728-8709-1-git-send-email-shijie8@gmail.com>

Add NAND write verify support in gpmi-nand driver.

This patch fixes a kernel crash when we select
CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:

root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
[   41.070000] Unable to handle kernel NULL pointer dereference at virtual addr0
[   41.080000] pgd = c77ac000
[   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
[   41.090000] Internal error: Oops: 17 [#1] ARM
[   41.090000] Modules linked in:
[   41.090000] CPU: 0    Not tainted (3.6.0-rc1-next-20120809-00002-ga25d017-d)
[   41.090000] PC is at nand_verify_buf+0x18/0x5c
[   41.090000] LR is at nand_write_page+0xc0/0x140
[   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
[   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
[   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
[   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
[   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
[   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
[   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
[   41.090000] Stack: (0xc7779de4 to 0xc777a000)
	...

Cc: <stable at vger.kernel.org>
Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
change log:
    [1] use the mtd->writesize to allocate the verify buffer.
    [2] add new field `verify_buf` in gpmi_nand_data{}

    tested this patch on imx6q-arm2 board.
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   23 +++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 8c0d2f0..d98bdea 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
 	return nand_boot_init(this);
 }
 
+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct gpmi_nand_data *this = chip->priv;
+	int ret;
+
+	ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
+	if (ret)
+		return -EFAULT;
+	if (memcmp(buf, this->verify_buf, len))
+		return -EFAULT;
+	return 0;
+}
+
 static int gpmi_scan_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct gpmi_nand_data *this = chip->priv;
 	int ret;
 
+	/*
+	 * We have gotten the right page size now, use it to allocate
+	 * the proper verify buffer.
+	 */
+	this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
+	if (!this->verify_buf)
+		return -ENOMEM;
+
 	/* Prepare for the BBT scan. */
 	ret = gpmi_pre_bbt_scan(this);
 	if (ret)
@@ -1556,6 +1578,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 	chip->read_byte		= gpmi_read_byte;
 	chip->read_buf		= gpmi_read_buf;
 	chip->write_buf		= gpmi_write_buf;
+	chip->verify_buf	= gpmi_verify_buf;
 	chip->ecc.read_page	= gpmi_ecc_read_page;
 	chip->ecc.write_page	= gpmi_ecc_write_page;
 	chip->ecc.read_oob	= gpmi_ecc_read_oob;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 1547a60..8ddf115 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -144,6 +144,7 @@ struct gpmi_nand_data {
 	/* MTD / NAND */
 	struct nand_chip	nand;
 	struct mtd_info		mtd;
+	uint8_t			*verify_buf;
 
 	/* General-use Variables */
 	int			current_chip;
-- 
1.7.4.4



From shijie8 at gmail.com  Fri Aug 10 23:37:23 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 11:37:23 +0800
Subject: [PATCH v2] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
References: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
Message-ID: <CAMiH66GtE3sgyvo5Xt=wyR5CVerbzAdj=jm78VFjRQjX1Mf99A@mail.gmail.com>

sorry, I forgot to free the verify buffer.

send another patch as soon as possible.

On Sat, Aug 11, 2012 at 11:25 PM, Huang Shijie <shijie8 at gmail.com> wrote:
> Add NAND write verify support in gpmi-nand driver.
>
> This patch fixes a kernel crash when we select
> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
>
> root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
> [   41.070000] Unable to handle kernel NULL pointer dereference at virtual addr0
> [   41.080000] pgd = c77ac000
> [   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
> [   41.090000] Internal error: Oops: 17 [#1] ARM
> [   41.090000] Modules linked in:
> [   41.090000] CPU: 0    Not tainted (3.6.0-rc1-next-20120809-00002-ga25d017-d)
> [   41.090000] PC is at nand_verify_buf+0x18/0x5c
> [   41.090000] LR is at nand_write_page+0xc0/0x140
> [   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
> [   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
> [   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
> [   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
> [   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
> [   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
> [   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
> [   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
> [   41.090000] Stack: (0xc7779de4 to 0xc777a000)
>         ...
>
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
> ---
> change log:
>     [1] use the mtd->writesize to allocate the verify buffer.
>     [2] add new field `verify_buf` in gpmi_nand_data{}
>
>     tested this patch on imx6q-arm2 board.
> ---
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   23 +++++++++++++++++++++++
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
>  2 files changed, 24 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> index 8c0d2f0..d98bdea 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
>         return nand_boot_init(this);
>  }
>
> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct gpmi_nand_data *this = chip->priv;
> +       int ret;
> +
> +       ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
> +       if (ret)
> +               return -EFAULT;
> +       if (memcmp(buf, this->verify_buf, len))
> +               return -EFAULT;
> +       return 0;
> +}
> +
>  static int gpmi_scan_bbt(struct mtd_info *mtd)
>  {
>         struct nand_chip *chip = mtd->priv;
>         struct gpmi_nand_data *this = chip->priv;
>         int ret;
>
> +       /*
> +        * We have gotten the right page size now, use it to allocate
> +        * the proper verify buffer.
> +        */
> +       this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
> +       if (!this->verify_buf)
> +               return -ENOMEM;
> +
>         /* Prepare for the BBT scan. */
>         ret = gpmi_pre_bbt_scan(this);
>         if (ret)
> @@ -1556,6 +1578,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
>         chip->read_byte         = gpmi_read_byte;
>         chip->read_buf          = gpmi_read_buf;
>         chip->write_buf         = gpmi_write_buf;
> +       chip->verify_buf        = gpmi_verify_buf;
>         chip->ecc.read_page     = gpmi_ecc_read_page;
>         chip->ecc.write_page    = gpmi_ecc_write_page;
>         chip->ecc.read_oob      = gpmi_ecc_read_oob;
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> index 1547a60..8ddf115 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
>         /* MTD / NAND */
>         struct nand_chip        nand;
>         struct mtd_info         mtd;
> +       uint8_t                 *verify_buf;
>
>         /* General-use Variables */
>         int                     current_chip;
> --
> 1.7.4.4
>


From shijie8 at gmail.com  Sat Aug 11 11:50:31 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 11:50:31 -0400
Subject: [PATCH v3] mtd: gpmi: add NAND write verify support
Message-ID: <1344700231-12624-1-git-send-email-shijie8@gmail.com>

Add NAND write verify support in gpmi-nand driver.

This patch fixes a kernel crash when we select
CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:

root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
[   41.070000] Unable to handle kernel NULL pointer dereference at virtual addr0
[   41.080000] pgd = c77ac000
[   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
[   41.090000] Internal error: Oops: 17 [#1] ARM
[   41.090000] Modules linked in:
[   41.090000] CPU: 0    Not tainted (3.6.0-rc1-next-20120809-00002-ga25d017-d)
[   41.090000] PC is at nand_verify_buf+0x18/0x5c
[   41.090000] LR is at nand_write_page+0xc0/0x140
[   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
[   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
[   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
[   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
[   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
[   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
[   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
[   41.090000] Stack: (0xc7779de4 to 0xc777a000)
	...

Cc: <stable at vger.kernel.org>
Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
v2 --> v3:
    [1] free the verify_buf when we exit.

v1 --> v2:
    [1] use the mtd->writesize to allocate the verify buffer.
    [2] add new field `verify_buf` in gpmi_nand_data{}

    tested this patch on imx6q-arm2 board.
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 8c0d2f0..e1e4c51 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
 	return nand_boot_init(this);
 }
 
+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct gpmi_nand_data *this = chip->priv;
+	int ret;
+
+	ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
+	if (ret)
+		return -EFAULT;
+	if (memcmp(buf, this->verify_buf, len))
+		return -EFAULT;
+	return 0;
+}
+
 static int gpmi_scan_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct gpmi_nand_data *this = chip->priv;
 	int ret;
 
+	/*
+	 * We have gotten the right page size now, use it to allocate
+	 * the proper verify buffer.
+	 */
+	this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
+	if (!this->verify_buf)
+		return -ENOMEM;
+
 	/* Prepare for the BBT scan. */
 	ret = gpmi_pre_bbt_scan(this);
 	if (ret)
@@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
 {
 	nand_release(&this->mtd);
 	gpmi_free_dma_buffer(this);
+	kfree(this->verify_buf);
+	this->verify_buf = NULL;
 }
 
 static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
@@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 	chip->read_byte		= gpmi_read_byte;
 	chip->read_buf		= gpmi_read_buf;
 	chip->write_buf		= gpmi_write_buf;
+	chip->verify_buf	= gpmi_verify_buf;
 	chip->ecc.read_page	= gpmi_ecc_read_page;
 	chip->ecc.write_page	= gpmi_ecc_write_page;
 	chip->ecc.read_oob	= gpmi_ecc_read_oob;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 1547a60..8ddf115 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -144,6 +144,7 @@ struct gpmi_nand_data {
 	/* MTD / NAND */
 	struct nand_chip	nand;
 	struct mtd_info		mtd;
+	uint8_t			*verify_buf;
 
 	/* General-use Variables */
 	int			current_chip;
-- 
1.7.4.4



From kgene.kim at samsung.com  Sat Aug 11 01:08:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 11 Aug 2012 14:08:09 +0900
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <20120810100713.GH24328@opensource.wolfsonmicro.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
 <20120810100713.GH24328@opensource.wolfsonmicro.com>
Message-ID: <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>

Mark Brown wrote:
> 
> On Fri, Aug 10, 2012 at 01:56:23PM +0900, Kukjin Kim wrote:
> 
> > Probably, this patch needs following?
> 
> > If you're ok, I will fix build error by above when I apply.
> 
> Yes, thanks.

Applied.

BTW, don't you need to enable your Cragganmore board in the defconfig?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From: Kukjin Kim <kgene.kim at samsung.com>
Subject: [PATCH] ARM: s3c6400_defconfig: enable more boards in defconfig

This enables all of s3c64xx boards in the s3c6400_defconfig.
In this time, MINI6410, REAL6410, and WLF_CRAGG_6410 are
added in the defconfig.

Cc: Darius Augulis <augulis.darius at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/configs/s3c6400_defconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/s3c6400_defconfig
b/arch/arm/configs/s3c6400_defconfig
index ba6a515..3a186d6 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_MACH_SMDK6400=y
 CONFIG_MACH_ANW6410=y
+CONFIG_MACH_MINI6410=y
+CONFIG_MACH_REAL6410=y
 CONFIG_MACH_SMDK6410=y
 CONFIG_MACH_NCP=y
 CONFIG_MACH_HMT=y
 CONFIG_MACH_SMARTQ5=y
 CONFIG_MACH_SMARTQ7=y
+CONFIG_MACH_WLF_CRAGG_6410=y
 CONFIG_CPU_32v6K=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc
initrd=0x51000000,6M ramdisk_size=6144"
-- 
1.7.4.1



From andrew at lunn.ch  Sat Aug 11 02:16:16 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 11 Aug 2012 08:16:16 +0200
Subject: [PATCH 2/3] ARM: Kirkwood: ts219: fix Makefile.boot after dts
 was split in two
In-Reply-To: <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>
Message-ID: <20120811061616.GA30869@lunn.ch>

On Sat, Aug 11, 2012 at 02:39:46AM +0000, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/mach-kirkwood/Makefile.boot |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index 2a576ab..2ad83e2 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -7,7 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
>  dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
>  dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
>  dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
> -dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
> +dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6281.dtb kirkwood-ts219-6282.dtb

A fix for this has already been accepted into arm-soc for the next rc.

  Andrew

>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> -- 
> 1.7.8.6
> 


From andrew at lunn.ch  Sat Aug 11 02:21:11 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 11 Aug 2012 08:21:11 +0200
Subject: [PATCH 3/3] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
Message-ID: <20120811062111.GA30947@lunn.ch>

On Sat, Aug 11, 2012 at 02:39:47AM +0000, Jason Cooper wrote:
> Also, disable DEBUG_KERNEL, enable SERIAL_OF_PLATFORM, and enable EMBEDDED

Hi Jason

Why disable DEBUG_KERNEL. Most of the other defconfig files have it
enabled.



> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/configs/kirkwood_defconfig |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
> index 5a494a3..0865d2e 100644
> --- a/arch/arm/configs/kirkwood_defconfig
> +++ b/arch/arm/configs/kirkwood_defconfig
> @@ -3,6 +3,9 @@ CONFIG_SYSVIPC=y
>  CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
>  CONFIG_LOG_BUF_SHIFT=19
> +CONFIG_NAMESPACES=y
> +CONFIG_BLK_DEV_INITRD=y

Do we need these two as well? Namespaces seems a bit unusual for a
tiny embedded device.

     Andrew


From tony at atomide.com  Sat Aug 11 02:24:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 10 Aug 2012 23:24:27 -0700
Subject: [GIT PULL] ARM: OMAP: PM fixes for v3.6-rc
In-Reply-To: <878vdmfxpx.fsf@ti.com>
References: <878vdmfxpx.fsf@ti.com>
Message-ID: <20120811062427.GU11011@atomide.com>

* Kevin Hilman <khilman at ti.com> [120810 10:45]:
> Tony,
> 
> Please pull the following PM related fixes for v3.6-rc.
> 
> One of them is a fix for drivers/cpufreq/omap-cpufreq.c, but it needs to
> go along with the arch/arm change.  I'm listed in MAINTAINERS for the
> OMAP CPUfreq driver now, so this should be OK.

OK thanks pulling into fixes.

Tony


From bryan.wu at canonical.com  Sat Aug 11 02:57:18 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Sat, 11 Aug 2012 14:57:18 +0800
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
 <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
 <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>
Message-ID: <CAK5ve-+hFRkbZ1bmfKodzjZEyP8vTyxZzU96LnhYjp1Vn7OWcw@mail.gmail.com>

On Wed, Aug 1, 2012 at 1:10 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, Jul 31, 2012 at 9:59 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> On Wed, Aug 1, 2012 at 12:55 PM, Olof Johansson <olof at lixom.net> wrote:
>>> On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>>>> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>>>>> Russell, Arnd and Olof,
>>>>>
>>>>
>>>> I felt very sorry about this issue, the email was archived
>>>> automatically in my Gmail account. I found the root cause of the issue
>>>> Russell met and actually that code about trigger_data is totally
>>>> useless, which was removed just now. I pushed an update version again
>>>> to the same branch of my git tree. Please consider a pull. If I did
>>>> something bad, please let me know, I will fix it as soon as possible.
>>>
>>> Hi,
>>>
>>> We'll pull this in for staging again once the merge window is done.
>>> It's definitely not 3.6 material at this time.
>>>
>>
>> OK, I will rebase to 3.6-rc1 after merge window close and send out
>> pull request again.
>
> No need to rebase unless there are large merge conflicts.
>

Olof, could you please consider pull again this branch? I keep it
based on 3.5 release.

Thanks,
-Bryan


From thomas.petazzoni at free-electrons.com  Sat Aug 11 02:59:25 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 08:59:25 +0200
Subject: [GIT PULL] arm: documentation
Message-ID: <20120811085925.34bb8337@skate>

Arnd, Olof,

Please pull the following new documentation of Marvell SoC families
that has been Acked-by Arnd.

Thanks!

Thomas

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/MISL-EBU-System-SW/mainline-public.git marvell-doc

for you to fetch changes up to 9ee99783d7571d7e1ca8540e82b21f51b69595f4:

  arm: add documentation describing Marvell families of SoC (2012-08-11 08:52:32 +0200)

----------------------------------------------------------------
Thomas Petazzoni (1):
      arm: add documentation describing Marvell families of SoC

 Documentation/arm/Marvell/README |  232 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 232 insertions(+)
 create mode 100644 Documentation/arm/Marvell/README

-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From marex at denx.de  Sat Aug 11 03:13:54 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 11 Aug 2012 09:13:54 +0200
Subject: [PATCH v3] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344700231-12624-1-git-send-email-shijie8@gmail.com>
References: <1344700231-12624-1-git-send-email-shijie8@gmail.com>
Message-ID: <201208110913.54479.marex@denx.de>

Dear Huang Shijie,

Please re-add credit to Fabio. Also, Fabio fixed the subject to be more 
accurate. Your subject makes this sound like it's adding a feature that can be 
postponed, yet this fixes a serious problem with the driver.

> Add NAND write verify support in gpmi-nand driver.
> 
> This patch fixes a kernel crash when we select
> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
> 
> root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
> [   41.070000] Unable to handle kernel NULL pointer dereference at virtual
> addr0 [   41.080000] pgd = c77ac000
> [   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
> [   41.090000] Internal error: Oops: 17 [#1] ARM
> [   41.090000] Modules linked in:
> [   41.090000] CPU: 0    Not tainted
> (3.6.0-rc1-next-20120809-00002-ga25d017-d) [   41.090000] PC is at
> nand_verify_buf+0x18/0x5c
> [   41.090000] LR is at nand_write_page+0xc0/0x140
> [   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
> [   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
> [   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
> [   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
> [   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
> [   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment
> user [   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
> [   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
> [   41.090000] Stack: (0xc7779de4 to 0xc777a000)
> 	...
> 
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
> ---
> v2 --> v3:
>     [1] free the verify_buf when we exit.
> 
> v1 --> v2:
>     [1] use the mtd->writesize to allocate the verify buffer.
>     [2] add new field `verify_buf` in gpmi_nand_data{}
> 
>     tested this patch on imx6q-arm2 board.
> ---
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
>  2 files changed, 26 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..e1e4c51 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data 
> *this) return nand_boot_init(this);
>  }
> 
> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
> len) +{
> +	struct nand_chip *chip = mtd->priv;
> +	struct gpmi_nand_data *this = chip->priv;
> +	int ret;
> +
> +	ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
> +	if (ret)
> +		return -EFAULT;
> +	if (memcmp(buf, this->verify_buf, len))
> +		return -EFAULT;
> +	return 0;
> +}
> +
>  static int gpmi_scan_bbt(struct mtd_info *mtd)
>  {
>  	struct nand_chip *chip = mtd->priv;
>  	struct gpmi_nand_data *this = chip->priv;
>  	int ret;
> 
> +	/*
> +	 * We have gotten the right page size now, use it to allocate
> +	 * the proper verify buffer.
> +	 */
> +	this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);

devm_ will work here just fine.

> +	if (!this->verify_buf)
> +		return -ENOMEM;
> +
>  	/* Prepare for the BBT scan. */
>  	ret = gpmi_pre_bbt_scan(this);
>  	if (ret)
> @@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
>  {
>  	nand_release(&this->mtd);
>  	gpmi_free_dma_buffer(this);
> +	kfree(this->verify_buf);

Then you can drop this altogether.

> +	this->verify_buf = NULL;
>  }
> 
>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
> @@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct
> gpmi_nand_data *this) chip->read_byte		= gpmi_read_byte;
>  	chip->read_buf		= gpmi_read_buf;
>  	chip->write_buf		= gpmi_write_buf;
> +	chip->verify_buf	= gpmi_verify_buf;
>  	chip->ecc.read_page	= gpmi_ecc_read_page;
>  	chip->ecc.write_page	= gpmi_ecc_write_page;
>  	chip->ecc.read_oob	= gpmi_ecc_read_oob;
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60..8ddf115 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
>  	/* MTD / NAND */
>  	struct nand_chip	nand;
>  	struct mtd_info		mtd;
> +	uint8_t			*verify_buf;
> 
>  	/* General-use Variables */
>  	int			current_chip;

Best regards,
Marek Vasut


From andrew at lunn.ch  Sat Aug 11 03:51:14 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 11 Aug 2012 09:51:14 +0200
Subject: [PATCH 2/3] ARM: Kirkwood: ts219: fix Makefile.boot after dts
 was split in two
In-Reply-To: <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>
Message-ID: <20120811075114.GD30947@lunn.ch>

On Sat, Aug 11, 2012 at 02:39:46AM +0000, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/mach-kirkwood/Makefile.boot |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index 2a576ab..2ad83e2 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -7,7 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
>  dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
>  dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
>  dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
> -dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
> +dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6281.dtb kirkwood-ts219-6282.dtb

Hi Jason

There is the same fix from Arnaud Patard, which has been posted to the
list maybe a week ago.

We seem quite good at breaking Makefile.boot and not noticing it. Who
maintains kisskb? We should ask for make dtbs to be added to the end
of the build scripts.

   Andrew


From linux at arm.linux.org.uk  Sat Aug 11 04:04:29 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 11 Aug 2012 09:04:29 +0100
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code
 consolidation (v2)
In-Reply-To: <CAK5ve-+hFRkbZ1bmfKodzjZEyP8vTyxZzU96LnhYjp1Vn7OWcw@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
 <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
 <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>
 <CAK5ve-+hFRkbZ1bmfKodzjZEyP8vTyxZzU96LnhYjp1Vn7OWcw@mail.gmail.com>
Message-ID: <20120811080429.GA18957@n2100.arm.linux.org.uk>

On Sat, Aug 11, 2012 at 02:57:18PM +0800, Bryan Wu wrote:
> On Wed, Aug 1, 2012 at 1:10 PM, Olof Johansson <olof at lixom.net> wrote:
> > On Tue, Jul 31, 2012 at 9:59 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> >> On Wed, Aug 1, 2012 at 12:55 PM, Olof Johansson <olof at lixom.net> wrote:
> >>> On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> >>>> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> >>>>> Russell, Arnd and Olof,
> >>>>>
> >>>>
> >>>> I felt very sorry about this issue, the email was archived
> >>>> automatically in my Gmail account. I found the root cause of the issue
> >>>> Russell met and actually that code about trigger_data is totally
> >>>> useless, which was removed just now. I pushed an update version again
> >>>> to the same branch of my git tree. Please consider a pull. If I did
> >>>> something bad, please let me know, I will fix it as soon as possible.
> >>>
> >>> Hi,
> >>>
> >>> We'll pull this in for staging again once the merge window is done.
> >>> It's definitely not 3.6 material at this time.
> >>>
> >>
> >> OK, I will rebase to 3.6-rc1 after merge window close and send out
> >> pull request again.
> >
> > No need to rebase unless there are large merge conflicts.
> >
> 
> Olof, could you please consider pull again this branch? I keep it
> based on 3.5 release.

So what's the fix you've applied?  I don't think you've posted any patches.


From andrew at lunn.ch  Sat Aug 11 05:12:55 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 11 Aug 2012 11:12:55 +0200
Subject: [PATCH 1/6] ARM: dove: unify clock setup
In-Reply-To: <1344255815-4457-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344255815-4457-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20120811091255.GA31809@lunn.ch>

Hi Sebastian

> -static void __init clk_init(void)
> +static void __init dove_clk_init(void)
>  {
>  	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
> -				       get_tclk());
> +				       dove_tclk);
>  
>  	orion_clkdev_init(tclk);
> +
> +	/* Ensure tclk is always clocked */
> +	clk_prepare_enable(tclk);
>  }

"ticking" would be better than clocked. 

Since this is a root fixed clock, is it necessary to prepare_enable()
it? I think prepare and enable become NOPs in this situation.

    Andrew


From shijie8 at gmail.com  Sat Aug 11 05:25:49 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 17:25:49 +0800
Subject: [PATCH v3] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208110913.54479.marex@denx.de>
References: <1344700231-12624-1-git-send-email-shijie8@gmail.com>
 <201208110913.54479.marex@denx.de>
Message-ID: <CAMiH66GbOYDpo-RDUct2nCixaf+9vhmT8Ouz+YPx95Z1+g2B1Q@mail.gmail.com>

On Sat, Aug 11, 2012 at 3:13 PM, Marek Vasut <marex at denx.de> wrote:
> Dear Huang Shijie,
>
> Please re-add credit to Fabio. Also, Fabio fixed the subject to be more

sorry. Should I add "Reported by : Fabio ...." to the patch?

I really appriaciate Fabio's work, but I do not think Fabio's patch is
more accurate.
The nand chips can be 2K page, 4K page and 8K page. But most of the
time, the nand chip is 4K page.
If we fix the verify_buf to 8K size as Fabio's patch does. It will
waste much memory.
This is my concern now. :)

My patch maybe not good. So If Fabio also sends out a new patch which
allocates the verify_buf with the mtd->writesize size.
I will ack it.

> accurate. Your subject makes this sound like it's adding a feature that can be

Please check the code drivers/mtd/onenand/onenand_base.c: 4008.
This driver implements the verify_buf in a more smart way.
It does not waste much memory.

thanks
Huang Shijie

> postponed, yet this fixes a serious problem with the driver.
>
>> Add NAND write verify support in gpmi-nand driver.
>>
>> This patch fixes a kernel crash when we select
>> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
>>
>> root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
>> [   41.070000] Unable to handle kernel NULL pointer dereference at virtual
>> addr0 [   41.080000] pgd = c77ac000
>> [   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
>> [   41.090000] Internal error: Oops: 17 [#1] ARM
>> [   41.090000] Modules linked in:
>> [   41.090000] CPU: 0    Not tainted
>> (3.6.0-rc1-next-20120809-00002-ga25d017-d) [   41.090000] PC is at
>> nand_verify_buf+0x18/0x5c
>> [   41.090000] LR is at nand_write_page+0xc0/0x140
>> [   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
>> [   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
>> [   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
>> [   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
>> [   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
>> [   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment
>> user [   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
>> [   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
>> [   41.090000] Stack: (0xc7779de4 to 0xc777a000)
>>       ...
>>
>> Cc: <stable at vger.kernel.org>
>> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
>> ---
>> v2 --> v3:
>>     [1] free the verify_buf when we exit.
>>
>> v1 --> v2:
>>     [1] use the mtd->writesize to allocate the verify buffer.
>>     [2] add new field `verify_buf` in gpmi_nand_data{}
>>
>>     tested this patch on imx6q-arm2 board.
>> ---
>>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
>>  drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
>>  2 files changed, 26 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..e1e4c51 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> @@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data
>> *this) return nand_boot_init(this);
>>  }
>>
>> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
>> len) +{
>> +     struct nand_chip *chip = mtd->priv;
>> +     struct gpmi_nand_data *this = chip->priv;
>> +     int ret;
>> +
>> +     ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
>> +     if (ret)
>> +             return -EFAULT;
>> +     if (memcmp(buf, this->verify_buf, len))
>> +             return -EFAULT;
>> +     return 0;
>> +}
>> +
>>  static int gpmi_scan_bbt(struct mtd_info *mtd)
>>  {
>>       struct nand_chip *chip = mtd->priv;
>>       struct gpmi_nand_data *this = chip->priv;
>>       int ret;
>>
>> +     /*
>> +      * We have gotten the right page size now, use it to allocate
>> +      * the proper verify buffer.
>> +      */
>> +     this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
>
> devm_ will work here just fine.
>
>> +     if (!this->verify_buf)
>> +             return -ENOMEM;
>> +
>>       /* Prepare for the BBT scan. */
>>       ret = gpmi_pre_bbt_scan(this);
>>       if (ret)
>> @@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
>>  {
>>       nand_release(&this->mtd);
>>       gpmi_free_dma_buffer(this);
>> +     kfree(this->verify_buf);
>
> Then you can drop this altogether.
>
>> +     this->verify_buf = NULL;
>>  }
>>
>>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
>> @@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct
>> gpmi_nand_data *this) chip->read_byte         = gpmi_read_byte;
>>       chip->read_buf          = gpmi_read_buf;
>>       chip->write_buf         = gpmi_write_buf;
>> +     chip->verify_buf        = gpmi_verify_buf;
>>       chip->ecc.read_page     = gpmi_ecc_read_page;
>>       chip->ecc.write_page    = gpmi_ecc_write_page;
>>       chip->ecc.read_oob      = gpmi_ecc_read_oob;
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60..8ddf115 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
>>       /* MTD / NAND */
>>       struct nand_chip        nand;
>>       struct mtd_info         mtd;
>> +     uint8_t                 *verify_buf;
>>
>>       /* General-use Variables */
>>       int                     current_chip;
>
> Best regards,
> Marek Vasut


From sebastian.hesselbarth at gmail.com  Sat Aug 11 05:38:59 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 11:38:59 +0200
Subject: [PATCH 1/6] ARM: dove: unify clock setup
In-Reply-To: <20120811091255.GA31809@lunn.ch>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344255815-4457-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <20120811091255.GA31809@lunn.ch>
Message-ID: <50262833.2010601@gmail.com>

On 08/11/2012 11:12 AM, Andrew Lunn wrote:
>> +	/* Ensure tclk is always clocked */
>> +	clk_prepare_enable(tclk);
>>   }
>
> "ticking" would be better than clocked.
>
> Since this is a root fixed clock, is it necessary to prepare_enable()
> it? I think prepare and enable become NOPs in this situation.

Hi Andrew,

yes you are right, it is useless to prepare or enable a fixed rate clk.
I cannot be gated anyway. I'll update the patch and resend soon.

Sebastian



From marc.zyngier at arm.com  Sat Aug 11 06:04:15 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:15 +0200
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <6e478bc5efb598b4a15ff9d534b94001@localhost>

Hi Rohit,

On Fri, 10 Aug 2012 14:58:41 -0700, Rohit Vaswani
<rvaswani at codeaurora.org>
wrote:
> The current arch_timer only support accessing through CP15 interface.
> Add support for ARM processors that only support IO mapped register
> interface

This is quite a departure from the current implementation, which raises a
couple of questions:
- What does CP15 ID_PFR1[19:16] report? Can we easily detect that we do
not have the CP15 interface?
- What about HYP mode? Is there any way to control the access of the
physical timer at PL1?

> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>  .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>  arch/arm/kernel/arch_timer.c                       |  259
>  ++++++++++++++++----
>  2 files changed, 223 insertions(+), 43 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt
> b/Documentation/devicetree/bindings/arm/arch_timer.txt
> index 52478c8..1c71799 100644
> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its
> per-processor interrupts.
>  
>  - clock-frequency : The frequency of the main counter, in Hz. Optional.
>  
> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI)
> interrupt
> +  In the default case i.e without this property, the timer irq is
treated
> as a
> +  PPI interrupt. Optional.

Ouch! How do you specify the various interrupts for all CPUs? Do you end
up with 4 SPIs per CPU?

> +- If the node address and reg is specified, the arch_timer will try to
> use the memory
> +  mapped timer. Optional.
> +
>  Example:
>  
>  	timer {
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index 1d0d9df..09604b7 100644
> --- a/arch/arm/kernel/arch_timer.c
> +++ b/arch/arm/kernel/arch_timer.c
> @@ -18,6 +18,7 @@
>  #include <linux/clockchips.h>
>  #include <linux/interrupt.h>
>  #include <linux/of_irq.h>
> +#include <linux/of_address.h>
>  #include <linux/io.h>
>  
>  #include <asm/cputype.h>
> @@ -29,8 +30,17 @@
>  static unsigned long arch_timer_rate;
>  static int arch_timer_ppi;
>  static int arch_timer_ppi2;
> +static int is_irq_percpu;
>  
>  static struct clock_event_device __percpu **arch_timer_evt;
> +static void __iomem *timer_base;
> +
> +struct arch_timer_operations {
> +	void (*reg_write)(int, u32);
> +	u32 (*reg_read)(int);
> +	cycle_t (*get_cntpct)(void);
> +	cycle_t (*get_cntvct)(void);
> +};

I already have something similar in a patch series that I'd like to get
merged in 3.7, implementing support for the virtual timers (needed for
virtualisation). Have a look at:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
timers-next

>  /*
>   * Architected system timer support.
> @@ -44,7 +54,29 @@ static struct clock_event_device __percpu
> **arch_timer_evt;
>  #define ARCH_TIMER_REG_FREQ		1
>  #define ARCH_TIMER_REG_TVAL		2
>  
> -static void arch_timer_reg_write(int reg, u32 val)
> +/* Iomapped Register Offsets */
> +#define ARCH_TIMER_CNTP_LOW_REG		0x000
> +#define ARCH_TIMER_CNTP_HIGH_REG	0x004
> +#define ARCH_TIMER_CNTV_LOW_REG		0x008
> +#define ARCH_TIMER_CNTV_HIGH_REG	0x00C
> +#define ARCH_TIMER_CTRL_REG		0x02C
> +#define ARCH_TIMER_FREQ_REG		0x010
> +#define ARCH_TIMER_CNTP_TVAL_REG	0x028
> +#define ARCH_TIMER_CNTV_TVAL_REG	0x038
> +
> +static void timer_reg_write_mem(int reg, u32 val)
> +{
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		__raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;
> +	}
> +}
> +
> +static void timer_reg_write_cp15(int reg, u32 val)
>  {
>  	switch (reg) {
>  	case ARCH_TIMER_REG_CTRL:
> @@ -58,7 +90,28 @@ static void arch_timer_reg_write(int reg, u32 val)
>  	isb();
>  }
>  
> -static u32 arch_timer_reg_read(int reg)
> +static u32 timer_reg_read_mem(int reg)
> +{
> +	u32 val;
> +
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CTRL_REG);
> +		break;
> +	case ARCH_TIMER_REG_FREQ:
> +		val = __raw_readl(timer_base + ARCH_TIMER_FREQ_REG);
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		val = __raw_readl(timer_base + ARCH_TIMER_CNTP_TVAL_REG);
> +		break;
> +	default:
> +		BUG();
> +	}
> +
> +	return val;
> +}
> +
> +static u32 timer_reg_read_cp15(int reg)
>  {
>  	u32 val;
>  
> @@ -79,6 +132,103 @@ static u32 arch_timer_reg_read(int reg)
>  	return val;
>  }
>  
> +static cycle_t arch_counter_get_cntpct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTP_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntpct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntvct_mem(void)
> +{
> +	u32 cvall, cvalh, thigh;
> +
> +	do {
> +		cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +		cvall = __raw_readl(timer_base + ARCH_TIMER_CNTV_LOW_REG);
> +		thigh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
> +	} while (cvalh != thigh);
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static cycle_t arch_counter_get_cntvct_cp15(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static struct arch_timer_operations arch_timer_ops_cp15 = {
> +	.reg_read = &timer_reg_read_cp15,
> +	.reg_write = &timer_reg_write_cp15,
> +	.get_cntpct = &arch_counter_get_cntpct_cp15,
> +	.get_cntvct = &arch_counter_get_cntvct_cp15,
> +};
> +
> +static struct arch_timer_operations arch_timer_ops_mem = {
> +	.reg_read = &timer_reg_read_mem,
> +	.reg_write = &timer_reg_write_mem,
> +	.get_cntpct = &arch_counter_get_cntpct_mem,
> +	.get_cntvct = &arch_counter_get_cntvct_mem,
> +};
> +
> +static struct arch_timer_operations *arch_specific_timer =
> &arch_timer_ops_cp15;
> +
> +static inline void arch_timer_reg_write(int reg, u32 val)
> +{
> +	arch_specific_timer->reg_write(reg, val);
> +}
> +
> +static inline u32 arch_timer_reg_read(int reg)
> +{
> +	return arch_specific_timer->reg_read(reg);
> +}
> +
> +static inline cycle_t arch_counter_get_cntpct(void)
> +{
> +	return arch_specific_timer->get_cntpct();
> +}
> +
> +static inline cycle_t arch_counter_get_cntvct(void)
> +{
> +	return arch_specific_timer->get_cntvct();
> +}
> +
> +static u32 notrace arch_counter_get_cntvct32(void)
> +{
> +	cycle_t cntvct = arch_counter_get_cntpct();
> +
> +	/*
> +	 * The sched_clock infrastructure only knows about counters
> +	 * with at most 32bits. Forget about the upper 24 bits for the
> +	 * time being...
> +	 */
> +	return (u32)(cntvct & (u32)~0);
> +}
> +
> +static cycle_t arch_counter_read(struct clocksource *cs)
> +{
> +	return arch_counter_get_cntpct();
> +}
> +
>  static irqreturn_t arch_timer_handler(int irq, void *dev_id)
>  {
>  	struct clock_event_device *evt = *(struct clock_event_device
**)dev_id;
> @@ -167,7 +317,9 @@ static int arch_timer_available(void)
>  {
>  	unsigned long freq;
>  
> -	if (!local_timer_is_architected())
> +	if (timer_base)
> +		arch_specific_timer = &arch_timer_ops_mem;
> +	else if (!local_timer_is_architected())
>  		return -ENXIO;
>  
>  	if (arch_timer_rate == 0) {
> @@ -188,41 +340,6 @@ static int arch_timer_available(void)
>  	return 0;
>  }
>  
> -static inline cycle_t arch_counter_get_cntpct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static inline cycle_t arch_counter_get_cntvct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static u32 notrace arch_counter_get_cntvct32(void)
> -{
> -	cycle_t cntvct = arch_counter_get_cntvct();
> -
> -	/*
> -	 * The sched_clock infrastructure only knows about counters
> -	 * with at most 32bits. Forget about the upper 24 bits for the
> -	 * time being...
> -	 */
> -	return (u32)(cntvct & (u32)~0);
> -}
> -
> -static cycle_t arch_counter_read(struct clocksource *cs)
> -{
> -	return arch_counter_get_cntpct();
> -}
> -
>  static struct clocksource clocksource_counter = {
>  	.name	= "arch_sys_counter",
>  	.rating	= 400,
> @@ -262,8 +379,12 @@ static int __init arch_timer_register(void)
>  
>  	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
>  
> -	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
> +	if (is_irq_percpu)
> +		err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
>  				 "arch_timer", arch_timer_evt);
> +	else
> +		err = request_irq(arch_timer_ppi, arch_timer_handler, 0,
> +			"arch_timer", arch_timer_evt);

So you end up enabling the interrupt earlier than expected. Are you sure
this is safe?

>  	if (err) {
>  		pr_err("arch_timer: can't register interrupt %d (%d)\n",
>  		       arch_timer_ppi, err);
> @@ -271,8 +392,13 @@ static int __init arch_timer_register(void)
>  	}
>  
>  	if (arch_timer_ppi2) {
> -		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
> -					 "arch_timer", arch_timer_evt);
> +		if (is_irq_percpu)
> +			err = request_percpu_irq(arch_timer_ppi2,
> +					arch_timer_handler, "arch_timer",
> +					arch_timer_evt);
> +		else
> +			err = request_irq(arch_timer_ppi2, arch_timer_handler,
> +					0, "arch_timer", arch_timer_evt);
>  		if (err) {
>  			pr_err("arch_timer: can't register interrupt %d (%d)\n",
>  			       arch_timer_ppi2, err);
> @@ -314,10 +440,40 @@ static const struct of_device_id
> arch_timer_of_match[] __initconst = {
>  	{},
>  };
>  
> +static int __init arch_timer_base_init(void)
> +{
> +	struct device_node *np;
> +
> +	if (!timer_base) {
> +		np = of_find_matching_node(NULL, arch_timer_of_match);
> +		if (!np) {
> +			pr_err("arch_timer: can't find DT node\n");
> +			return -ENODEV;
> +		}
> +
> +		if (of_get_address(np, 0, NULL, NULL)) {
> +			timer_base = of_iomap(np, 0);
> +			if (!timer_base) {
> +				pr_err("arch_timer: cant map timer base\n");
> +				return -ENOMEM;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static inline void __init arch_timer_base_free(void)
> +{
> +	if (timer_base)
> +		iounmap(timer_base);
> +}
> +
>  int __init arch_timer_of_register(void)
>  {
>  	struct device_node *np;
>  	u32 freq;
> +	int ret;
>  
>  	np = of_find_matching_node(NULL, arch_timer_of_match);
>  	if (!np) {
> @@ -331,20 +487,37 @@ int __init arch_timer_of_register(void)
>  
>  	arch_timer_ppi = irq_of_parse_and_map(np, 0);
>  	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
> +
> +	ret = arch_timer_base_init();
> +	if (ret)
> +		return ret;
> +
> +	is_irq_percpu = !(of_property_read_bool(np, "irq-is-not-percpu"));
> +
>  	pr_info("arch_timer: found %s irqs %d %d\n",
>  		np->name, arch_timer_ppi, arch_timer_ppi2);
>  
> -	return arch_timer_register();
> +	ret = arch_timer_register();
> +	if (ret)
> +		arch_timer_base_free();
> +
> +	return ret;
>  }
>  
>  int __init arch_timer_sched_clock_init(void)
>  {
>  	int err;
>  
> -	err = arch_timer_available();
> +	err = arch_timer_base_init();
>  	if (err)
>  		return err;
>  
> +	err = arch_timer_available();
> +	if (err) {
> +		arch_timer_base_free();
> +		return err;
> +	}
> +
>  	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
>  	return 0;
>  }

-- 
Fast, cheap, reliable. Pick two.


From marc.zyngier at arm.com  Sat Aug 11 06:17:14 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:17:14 +0200
Subject: [PATCH 1/2] ARM: local timers: Unmask interrupt before new TVAL
 is set
In-Reply-To: <1344635854-5033-1-git-send-email-rvaswani@codeaurora.org>
References: <1344635854-5033-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <cdb51f00bafa8151a880d8cc7898631e@localhost>

On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
<rvaswani at codeaurora.org>
wrote:
> Level triggered interrupt is deasserted when a new TVAL is written
> only when the interrupt is unmasked. Make sure that the interrupt
> is unmasked in CTL register before TVAL is written.
> If this order is not followed, there are chances that on some
> hardware you would not receive any timer interrupts.
> 
> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>  arch/arm/kernel/arch_timer.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index dd58035..1d0d9df 100644
> --- a/arch/arm/kernel/arch_timer.c
> +++ b/arch/arm/kernel/arch_timer.c
> @@ -126,8 +126,8 @@ static int arch_timer_set_next_event(unsigned long
evt,
>  	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>  	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
>  
> -	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
>  	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
> +	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);

But by doing so, you're opening a window where TVAL can be negative (from
a previous timer trigger) and the interrupt unmasked, which would lead to
an immediate trigger, before TVAL is updated with the new value.

Does your hardware deassert the interrupt even when the enable bit is not
set? If so, would the following sequence work?

        ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK);
        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);

	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);

        ctrl |= ARCH_TIMER_CTRL_ENABLE;
        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);

Thanks,

        M.
-- 
Fast, cheap, reliable. Pick two.



From marc.zyngier at arm.com  Sat Aug 11 06:31:29 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 11:31:29 +0100
Subject: [PATCH v2 0/2] arch_timers patches to enable KVM support
Message-ID: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>

This series is aimed at offering the minimum level of support that KVM
needs when it comes to architected timers.

The first patch changes the driver to use the virtual timer by default
instead of the physical one (access to the later is conditioned by the
hypervisor settings, while the former is always available). This could
be required even if the kernel is not running as a guest.

The second patch exposes a clockcycle counter that can be used by
other subsystems.

Patches based on v3.6-rc1.


Marc Zyngier (2):
  ARM: arch_timers: enable the use of the virtual timer
  ARM: arch_timers: register a time/cycle counter

 arch/arm/include/asm/arch_timer.h |    7 +
 arch/arm/kernel/arch_timer.c      |  286 ++++++++++++++++++++++++++++--------
 2 files changed, 229 insertions(+), 64 deletions(-)

-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 06:31:31 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 11:31:31 +0100
Subject: [PATCH v2 2/2] ARM: arch_timers: register a time/cycle counter
In-Reply-To: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
References: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344681091-12652-3-git-send-email-marc.zyngier@arm.com>

Some subsystems (KVM for example) need access to a cycle counter.
In the KVM case, this is used to measure the time delta between
host and guest in order to accurately generate timer events for
the guest.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/arch_timer.h |    7 +++++++
 arch/arm/kernel/arch_timer.c      |   25 +++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e7547..ad9b155 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -2,11 +2,13 @@
 #define __ASMARM_ARCH_TIMER_H
 
 #include <asm/errno.h>
+#include <linux/clocksource.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
 #define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
+struct timecounter *arch_timer_get_timecounter(void);
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -17,6 +19,11 @@ static inline int arch_timer_sched_clock_init(void)
 {
 	return -ENXIO;
 }
+
+static inline struct timecounter *arch_timer_get_timecounter(void)
+{
+	return NULL;
+}
 #endif
 
 #endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 4a64733..f57e4b7 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -330,6 +330,15 @@ int read_current_timer(unsigned long *timer_val)
 	return 0;
 }
 
+static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+{
+	/*
+	 * Always use the physical counter for the clocksource.
+	 * CNTHCTL.PL1PCTEN must be set to 1.
+	 */
+	return arch_counter_get_cntpct();
+}
+
 static struct clocksource clocksource_counter = {
 	.name	= "arch_sys_counter",
 	.rating	= 400,
@@ -338,6 +347,18 @@ static struct clocksource clocksource_counter = {
 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct cyclecounter cyclecounter = {
+	.read	= arch_counter_read_cc,
+	.mask	= CLOCKSOURCE_MASK(56),
+};
+
+static struct timecounter timecounter;
+
+struct timecounter *arch_timer_get_timecounter(void)
+{
+	return &timecounter;
+}
+
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
 	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
@@ -381,6 +402,10 @@ static int __init arch_timer_register(void)
 	}
 
 	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+	cyclecounter.mult = clocksource_counter.mult;
+	cyclecounter.shift = clocksource_counter.shift;
+	timecounter_init(&timecounter, &cyclecounter,
+			 arch_counter_get_cntpct());
 
 	if (arch_timer_use_virtual) {
 		ppi = arch_timer_ppi[VIRT_PPI];
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 06:31:30 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 11:31:30 +0100
Subject: [PATCH v2 1/2] ARM: arch_timers: enable the use of the virtual timer
In-Reply-To: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
References: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>

At the moment, the arch_timer driver only uses the physical timer,
which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
which is likely in a virtualized environment. Instead, the virtual
timer is always available.

This patch enables the use of both the virtual timer, unless no
interrupt is provided in the DT for it, in which case is falls
back to the physical timer.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kernel/arch_timer.c |  261 +++++++++++++++++++++++++++++++----------
 1 files changed, 197 insertions(+), 64 deletions(-)

diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf25880..4a64733 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -27,13 +27,31 @@
 #include <asm/sched_clock.h>
 
 static unsigned long arch_timer_rate;
-static int arch_timer_ppi;
-static int arch_timer_ppi2;
+
+enum ppi_nr {
+	PHYS_SECURE_PPI,
+	PHYS_NONSECURE_PPI,
+	VIRT_PPI,
+	HYP_PPI,
+	MAX_TIMER_PPI
+};
+
+static int arch_timer_ppi[MAX_TIMER_PPI];
 
 static struct clock_event_device __percpu **arch_timer_evt;
 
 extern void init_current_timer_delay(unsigned long freq);
 
+static bool arch_timer_use_virtual = true;
+
+struct arch_timer_reg_ops {
+	void	(*reg_write)(int reg, u32 val);
+	u32	(*reg_read)(int reg);
+	cycle_t	(*counter_read)(void);
+};
+
+static struct arch_timer_reg_ops *arch_timer_reg_ops;
+
 /*
  * Architected system timer support.
  */
@@ -46,7 +64,37 @@ extern void init_current_timer_delay(unsigned long freq);
 #define ARCH_TIMER_REG_FREQ		1
 #define ARCH_TIMER_REG_TVAL		2
 
-static void arch_timer_reg_write(int reg, u32 val)
+static inline void arch_timer_reg_write(int reg, u32 val)
+{
+	arch_timer_reg_ops->reg_write(reg, val);
+}
+
+static inline u32 arch_timer_reg_read(int reg)
+{
+	return arch_timer_reg_ops->reg_read(reg);
+}
+
+static inline cycle_t arch_timer_counter_read(void)
+{
+	return arch_timer_reg_ops->counter_read();
+}
+
+static u32 arch_timer_common_reg_read(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_FREQ:
+		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+		break;
+	default:
+		BUG();
+	}
+
+	return val;
+}
+
+static void arch_timer_phys_reg_write(int reg, u32 val)
 {
 	switch (reg) {
 	case ARCH_TIMER_REG_CTRL:
@@ -60,7 +108,7 @@ static void arch_timer_reg_write(int reg, u32 val)
 	isb();
 }
 
-static u32 arch_timer_reg_read(int reg)
+static u32 arch_timer_phys_reg_read(int reg)
 {
 	u32 val;
 
@@ -68,19 +116,78 @@ static u32 arch_timer_reg_read(int reg)
 	case ARCH_TIMER_REG_CTRL:
 		asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
 		break;
-	case ARCH_TIMER_REG_FREQ:
-		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-		break;
 	case ARCH_TIMER_REG_TVAL:
 		asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
 		break;
 	default:
-		BUG();
+		val = arch_timer_common_reg_read(reg);
+	}
+
+	return val;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static struct arch_timer_reg_ops arch_timer_phys_ops = {
+	.reg_write	= arch_timer_phys_reg_write,
+	.reg_read	= arch_timer_phys_reg_read,
+	.counter_read	= arch_counter_get_cntpct,
+};
+
+static void arch_timer_virt_reg_write(int reg, u32 val)
+{
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+		break;
+	}
+
+	isb();
+}
+
+static u32 arch_timer_virt_reg_read(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+		break;
+	default:
+		val = arch_timer_common_reg_read(reg);
 	}
 
 	return val;
 }
 
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static struct arch_timer_reg_ops arch_timer_virt_ops = {
+	.reg_write	= arch_timer_virt_reg_write,
+	.reg_read	= arch_timer_virt_reg_read,
+	.counter_read	= arch_counter_get_cntvct,
+};
+
 static irqreturn_t arch_timer_handler(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
@@ -144,16 +251,19 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 	clk->rating = 450;
 	clk->set_mode = arch_timer_set_mode;
 	clk->set_next_event = arch_timer_set_next_event;
-	clk->irq = arch_timer_ppi;
+	clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
 
 	clockevents_config_and_register(clk, arch_timer_rate,
 					0xf, 0x7fffffff);
 
 	*__this_cpu_ptr(arch_timer_evt) = clk;
 
-	enable_percpu_irq(clk->irq, 0);
-	if (arch_timer_ppi2)
-		enable_percpu_irq(arch_timer_ppi2, 0);
+	if (arch_timer_use_virtual)
+		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
+	else {
+		enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
+		enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+	}
 
 	return 0;
 }
@@ -185,43 +295,30 @@ static int arch_timer_available(void)
 		arch_timer_rate = freq;
 	}
 
-	pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
-		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
+		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+		     arch_timer_use_virtual ? "virt" : "phys");
 	return 0;
 }
 
-static inline cycle_t arch_counter_get_cntpct(void)
-{
-	u32 cvall, cvalh;
-
-	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
+static u32 notrace arch_counter_get_cnt32(void)
 {
-	u32 cvall, cvalh;
-
-	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static u32 notrace arch_counter_get_cntvct32(void)
-{
-	cycle_t cntvct = arch_counter_get_cntvct();
+	cycle_t cnt = arch_timer_counter_read();
 
 	/*
 	 * The sched_clock infrastructure only knows about counters
 	 * with at most 32bits. Forget about the upper 24 bits for the
 	 * time being...
 	 */
-	return (u32)(cntvct & (u32)~0);
+	return (u32)(cnt & (u32)~0);
 }
 
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
+	/*
+	 * Always use the physical counter for the clocksource.
+	 * CNTHCTL.PL1PCTEN must be set to 1.
+	 */
 	return arch_counter_get_cntpct();
 }
 
@@ -245,9 +342,14 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
 	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 		 clk->irq, smp_processor_id());
-	disable_percpu_irq(clk->irq);
-	if (arch_timer_ppi2)
-		disable_percpu_irq(arch_timer_ppi2);
+
+	if (arch_timer_use_virtual)
+		disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
+	else {
+		disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
+		disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+	}
+
 	arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 }
 
@@ -261,36 +363,49 @@ static struct clock_event_device arch_timer_global_evt;
 static int __init arch_timer_register(void)
 {
 	int err;
+	int ppi;
+
+	if (arch_timer_use_virtual)
+		arch_timer_reg_ops = &arch_timer_virt_ops;
+	else
+		arch_timer_reg_ops = &arch_timer_phys_ops;
 
 	err = arch_timer_available();
 	if (err)
-		return err;
+		goto out;
 
 	arch_timer_evt = alloc_percpu(struct clock_event_device *);
-	if (!arch_timer_evt)
-		return -ENOMEM;
+	if (!arch_timer_evt) {
+		err = -ENOMEM;
+		goto out;
+	}
 
 	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 
-	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
-				 "arch_timer", arch_timer_evt);
+	if (arch_timer_use_virtual) {
+		ppi = arch_timer_ppi[VIRT_PPI];
+		err = request_percpu_irq(ppi, arch_timer_handler,
+					 "arch_timer", arch_timer_evt);
+	} else {
+		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
+		err = request_percpu_irq(ppi, arch_timer_handler,
+					 "arch_timer", arch_timer_evt);
+		if (!err) {
+			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+			err = request_percpu_irq(ppi, arch_timer_handler,
+						 "arch_timer", arch_timer_evt);
+			if (err)
+				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+						arch_timer_evt);
+		}
+	}
+
 	if (err) {
 		pr_err("arch_timer: can't register interrupt %d (%d)\n",
-		       arch_timer_ppi, err);
+		       ppi, err);
 		goto out_free;
 	}
 
-	if (arch_timer_ppi2) {
-		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-					 "arch_timer", arch_timer_evt);
-		if (err) {
-			pr_err("arch_timer: can't register interrupt %d (%d)\n",
-			       arch_timer_ppi2, err);
-			arch_timer_ppi2 = 0;
-			goto out_free_irq;
-		}
-	}
-
 	err = local_timer_register(&arch_timer_ops);
 	if (err) {
 		/*
@@ -310,13 +425,18 @@ static int __init arch_timer_register(void)
 	return 0;
 
 out_free_irq:
-	free_percpu_irq(arch_timer_ppi, arch_timer_evt);
-	if (arch_timer_ppi2)
-		free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+	if (arch_timer_use_virtual)
+		free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
+	else {
+		free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+				arch_timer_evt);
+		free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+				arch_timer_evt);
+	}
 
 out_free:
 	free_percpu(arch_timer_evt);
-
+out:
 	return err;
 }
 
@@ -329,6 +449,7 @@ int __init arch_timer_of_register(void)
 {
 	struct device_node *np;
 	u32 freq;
+	int i;
 
 	np = of_find_matching_node(NULL, arch_timer_of_match);
 	if (!np) {
@@ -340,10 +461,22 @@ int __init arch_timer_of_register(void)
 	if (!of_property_read_u32(np, "clock-frequency", &freq))
 		arch_timer_rate = freq;
 
-	arch_timer_ppi = irq_of_parse_and_map(np, 0);
-	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
-	pr_info("arch_timer: found %s irqs %d %d\n",
-		np->name, arch_timer_ppi, arch_timer_ppi2);
+	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+	/*
+	 * If no interrupt provided for virtual timer, we'll have to
+	 * stick to the physical timer. It'd better be accessible...
+	 */
+	if (!arch_timer_ppi[VIRT_PPI]) {
+		arch_timer_use_virtual = false;
+
+		if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+		    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+			pr_warn("arch_timer: No interrupt available, giving up\n");
+			return -EINVAL;
+		}
+	}
 
 	return arch_timer_register();
 }
@@ -356,6 +489,6 @@ int __init arch_timer_sched_clock_init(void)
 	if (err)
 		return err;
 
-	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+	setup_sched_clock(arch_counter_get_cnt32, 32, arch_timer_rate);
 	return 0;
 }
-- 
1.7.8.6



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:20 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:20 +0200
Subject: [PATCH v2 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds DT support for Marvell Dove SoC and three boards
equipped with this SoC. The work is based on device tree support for
Marvell Orion based SoCs introduced in 3.6-rc1.

The first three patches move mach-dove closer to Marvell Kirkwood's
setup code by unifying the clock setup routines, adding clock gating
control, and support for Marvell's crypto engine to mach-dove.

Patches 4 and 5 add a generic DT machine descriptor to mach-dove and
corresponding DT descriptors for the SoC and already supported boards.

Finally, the last patch adds a DT descriptor for the SolidRun CuBox,
a plug computer based on Marvell Dove.

This patch set relies on a DT support patch for sdhci-dove that has
been sent to the corresponding maintainers a few days ago.

Sebastian Hesselbarth (6):
  ARM: dove: unify clock setup
  ARM: dove: add clock gating control
  ARM: dove: add crypto engine
  ARM: dove: add device tree based machine descriptor
  ARM: dove: add device tree descriptors
  ARM: dove: SolidRun CuBox DT

 arch/arm/boot/dts/dove-cm-a510.dts   |   38 +++++++++
 arch/arm/boot/dts/dove-cubox.dts     |   42 +++++++++
 arch/arm/boot/dts/dove-dove-db.dts   |   38 +++++++++
 arch/arm/boot/dts/dove.dtsi          |  143 +++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Kconfig           |    7 ++
 arch/arm/mach-dove/Makefile.boot     |    4 +
 arch/arm/mach-dove/common.c          |  156 +++++++++++++++++++++++++++++++---
 arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++----
 8 files changed, 452 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>

v2: Removed clk_prepare_enable for tclk and updated subsequent patches
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:21 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:21 +0200
Subject: [PATCH v2 1/6] ARM: dove: unify clock setup
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch synchronizes the clock setup of dove with other orion-based
platforms.

In dove_find_tclk there was a note about DOVE_SAMPLE_HI/LO register to
detect tclk. While it might be possible to set a different tclk frequency
with reset strapping the Dove datasheets don't tell anything about tclk
frequency here. Therefore, I removed that comment.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>

v2: remove useless clk_prepare_enable for fixed rate tclk
---
 arch/arm/mach-dove/common.c |   19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 4db5de5..b6f092c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -33,8 +33,6 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -70,12 +68,13 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static void __init dove_clk_init(void)
 {
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-				       get_tclk());
+				       dove_tclk);
 
 	orion_clkdev_init(tclk);
 }
@@ -187,16 +186,16 @@ void __init dove_init_early(void)
 	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
 	return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+	dove_tclk = dove_find_tclk();
 	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_DOVE_BRIDGE, get_tclk());
+			IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -284,8 +283,8 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-	printk(KERN_INFO "Dove 88AP510 SoC, ");
-	printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init();
@@ -293,7 +292,7 @@ void __init dove_init(void)
 	dove_setup_cpu_mbus();
 
 	/* Setup root of clk tree */
-	clk_init();
+	dove_clk_init();
 
 	/* internal devices that every board has */
 	dove_rtc_init();
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:22 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:22 +0200
Subject: [PATCH v2 2/6] ARM: dove: add clock gating control
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-3-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds clock gates from the clock gating control register
available on dove. All clock gates are hooked up to tclk, except for
gigabit ethernet controller (ge) which is a child of gephy to allow
both enabled/disabled at the same time.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>

v2: adapted to removed clk_prepare_enable from patch 1
---
 arch/arm/mach-dove/common.c          |   59 +++++++++++++++++++++++++++++++++-
 arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++++++++++++++-----------
 2 files changed, 94 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index b6f092c..7281591 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/mv643xx_i2c.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,6 +25,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -31,6 +33,7 @@
 #include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
+#include <plat/mv_xor.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -69,14 +72,68 @@ void __init dove_map_io(void)
  * CLK tree
  ****************************************************************************/
 static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
+static struct clk __init *dove_register_gate(const char *name,
+					     const char *parent, u8 bit_idx)
+{
+	return clk_register_gate(NULL, name, parent, 0,
+				 (void __iomem *)CLOCK_GATING_CONTROL,
+				 bit_idx, 0, &gating_lock);
+}
+
 static void __init dove_clk_init(void)
 {
+	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+	struct clk *xor0, *xor1, *ge, *gephy;
+
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 				       dove_tclk);
 
-	orion_clkdev_init(tclk);
+	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+	pex0 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE0);
+	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+	orion_clkdev_add(NULL, "orion_spi.0", tclk);
+	orion_clkdev_add(NULL, "orion_spi.1", tclk);
+	orion_clkdev_add(NULL, "orion_wdt", tclk);
+	orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
+
+	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge);
+	orion_clkdev_add("0", "sata_mv.0", sata);
+	orion_clkdev_add("0", "pcie", pex0);
+	orion_clkdev_add("1", "pcie", pex1);
+	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+	orion_clkdev_add(NULL, "orion_nand", nand);
+	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+	orion_clkdev_add(NULL, "mv_crypto", crypto);
+	orion_clkdev_add(NULL, "dove-ac97", ac97);
+	orion_clkdev_add(NULL, "dove-pdma", pdma);
+	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
+	orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f94..7bcd0df 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL	(DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK		(1 << 0)
-#define  CLOCK_GATING_USB1_MASK		(1 << 1)
-#define  CLOCK_GATING_GBE_MASK		(1 << 2)
-#define  CLOCK_GATING_SATA_MASK		(1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK	(1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK	(1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK	(1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK	(1 << 9)
-#define  CLOCK_GATING_NAND_MASK		(1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK	(1 << 11)
-#define  CLOCK_GATING_I2S0_MASK		(1 << 12)
-#define  CLOCK_GATING_I2S1_MASK		(1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK	(1 << 15)
-#define  CLOCK_GATING_AC97_MASK		(1 << 21)
-#define  CLOCK_GATING_PDMA_MASK		(1 << 22)
-#define  CLOCK_GATING_XOR0_MASK		(1 << 23)
-#define  CLOCK_GATING_XOR1_MASK		(1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << 30)
+#define  CLOCK_GATING_BIT_USB0		0
+#define  CLOCK_GATING_BIT_USB1		1
+#define  CLOCK_GATING_BIT_GBE		2
+#define  CLOCK_GATING_BIT_SATA		3
+#define  CLOCK_GATING_BIT_PCIE0		4
+#define  CLOCK_GATING_BIT_PCIE1		5
+#define  CLOCK_GATING_BIT_SDIO0		8
+#define  CLOCK_GATING_BIT_SDIO1		9
+#define  CLOCK_GATING_BIT_NAND		10
+#define  CLOCK_GATING_BIT_CAMERA	11
+#define  CLOCK_GATING_BIT_I2S0		12
+#define  CLOCK_GATING_BIT_I2S1		13
+#define  CLOCK_GATING_BIT_CRYPTO	15
+#define  CLOCK_GATING_BIT_AC97		21
+#define  CLOCK_GATING_BIT_PDMA		22
+#define  CLOCK_GATING_BIT_XOR0		23
+#define  CLOCK_GATING_BIT_XOR1		24
+#define  CLOCK_GATING_BIT_GIGA_PHY	30
+#define  CLOCK_GATING_USB0_MASK		(1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK		(1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK		(1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK		(1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK	(1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK	(1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK	(1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK	(1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK		(1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK	(1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK		(1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK		(1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK	(1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK		(1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK		(1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK		(1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK		(1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE	(DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK	(DOVE_PMU_VIRT_BASE + 0x54)
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:23 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:23 +0200
Subject: [PATCH v2 3/6] ARM: dove: add crypto engine
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-4-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a dove specific setup function for the Marvell CESA
crypto engine available on orion based SoCs. Dove setup was just
missing a function to call orion_crypto_init with dove specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 7281591..88e3d91 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -260,6 +260,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+	orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+			  DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:25 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:25 +0200
Subject: [PATCH v2 5/6] ARM: dove: add device tree descriptors
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-6-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds device tree decriptors for dove SoC and currently
supported boards.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cm-a510.dts |   38 ++++++++++
 arch/arm/boot/dts/dove-dove-db.dts |   38 ++++++++++
 arch/arm/boot/dts/dove.dtsi        |  143 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot   |    3 +
 4 files changed, 222 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 0000000..61a8062
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Compulab CM-A510";
+	compatible = "compulab,cm-a510", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 0000000..e5a920b
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Marvell DB-MV88AP510-BP Development Board";
+	compatible = "marvell,dove-db", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash ST-M25P32-VMF6P */
+	spi-flash at 0 {
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 0000000..96fb824
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "marvell,dove";
+	model = "Marvell Armada 88AP510 SoC";
+
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller {
+		compatible = "marvell,orion-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xf1020204 0x04>,
+		      <0xf1020214 0x04>;
+	};
+
+	mbus at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0 0xf1000000 0x4000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <7>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart1: serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <8>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart2: serial at 12200 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <9>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart3: serial at 12300 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <10>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		wdt: wdt at 20300 {
+			compatible = "marvell,orion-wdt";
+			reg = <0x20300 0x28>;
+		};
+
+		gpio0: gpio at d0400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0400 0x20>;
+			ngpio = <32>;
+			interrupts = <12>, <13>, <14>, <60>;
+		};
+
+		gpio1: gpio at d0420 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0420 0x20>;
+			ngpio = <32>;
+			interrupts = <61>;
+		};
+
+		gpio2: gpio at e8400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xe8400 0x0c>;
+			ngpio = <8>;
+		};
+
+		spi0: spi at 10600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			interrupts = <6>;
+			reg = <0x10600 0x28>;
+			status = "disabled";
+		};
+
+		spi1: spi at 14600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			interrupts = <5>;
+			reg = <0x14600 0x28>;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11>;
+			clock-frequency = <400000>;
+			timeout-ms = <1000>;
+			status = "disabled";
+		};
+
+		sdio0: sdio at 92000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x92000 0x100>;
+			interrupts = <35>, <37>;
+			status = "disabled";
+		};
+
+		sdio1: sdio at 90000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x90000 0x100>;
+			interrupts = <36>, <38>;
+			status = "disabled";
+		};
+
+		sata0: sata at a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x2400>;
+			interrupts = <62>;
+			nr-ports = <1>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 760a0ef..94ab6b3 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -1,3 +1,6 @@
    zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:24 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:24 +0200
Subject: [PATCH v2 4/6] ARM: dove: add device tree based machine descriptor
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-5-git-send-email-sebastian.hesselbarth@gmail.com>

This adds a generic DT_MACHINE for mach-dove. As with other orion based
SoCs there still is some glue code required to make all internal devices
work, i.e. auxdata is provided to pass clocks to corresponding device
drivers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/Kconfig  |    7 +++++
 arch/arm/mach-dove/common.c |   67 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+)

diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c5..00154e7 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
 	  Say 'Y' here if you want your kernel to support the
 	  CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+	bool "Marvell Dove Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 88e3d91..d860f3b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -17,6 +17,8 @@
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -30,6 +32,7 @@
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
+#include <plat/irq.h>
 #include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -381,3 +384,67 @@ void dove_restart(char mode, const char *cmd)
 	while (1)
 		;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+	OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+	OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+		       NULL),
+	OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+	{},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+	tauros2_init();
+#endif
+	dove_setup_cpu_mbus();
+
+	/* Setup root of clk tree */
+	dove_clk_init();
+
+	/* Internal devices not ported to DT yet */
+	dove_rtc_init();
+	dove_xor0_init();
+	dove_xor1_init();
+
+	dove_ge00_init(&dove_dt_ge00_data);
+	dove_ehci0_init();
+	dove_ehci1_init();
+	dove_pcie_init(1, 1);
+	dove_crypto_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+	"marvell,dove",
+	NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+	.map_io		= dove_map_io,
+	.init_early	= dove_init_early,
+	.init_irq	= orion_dt_init_irq,
+	.timer		= &dove_timer,
+	.init_machine	= dove_dt_init,
+	.restart	= dove_restart,
+	.dt_compat	= dove_dt_board_compat,
+MACHINE_END
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 06:35:26 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 12:35:26 +0200
Subject: [PATCH v2 6/6] ARM: dove: SolidRun CuBox DT
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344681326-17946-7-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds basic support for the SolidRun CuBox to DT based
mach-dove. There are still some issues related to ongoing orion/mvebu
development, e.g. gpio-led will not work as there is no DT pinctrl
for dove yet and we don't have board specific setup code. Nevertheless,
the DT description is already introduced here.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cubox.dts |   42 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot |    1 +
 2 files changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 0000000..0adbd5a
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "SolidRun CuBox";
+	compatible = "solidrun,cubox", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		power {
+			label = "Power";
+			gpios = <&gpio0 18 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 94ab6b3..cfac9c5 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cubox.dtb
-- 
1.7.10.4



From marc.zyngier at arm.com  Sat Aug 11 07:04:34 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:34 +0100
Subject: [PATCH 4/7] ARM: virt: Update documentation for hyp mode entry support
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-5-git-send-email-marc.zyngier@arm.com>

From: Dave Martin <dave.martin at linaro.org>

Document the possibility of the kernel being entered in HYP mode.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 Documentation/arm/Booting |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
index a341d87..0c1f475 100644
--- a/Documentation/arm/Booting
+++ b/Documentation/arm/Booting
@@ -154,13 +154,33 @@ In either case, the following conditions must be met:
 
 - CPU mode
   All forms of interrupts must be disabled (IRQs and FIQs)
-  The CPU must be in SVC mode.  (A special exception exists for Angel)
+
+  For CPUs which do not include the ARM virtualization extensions, the
+  CPU must be in SVC mode.  (A special exception exists for Angel)
+
+  CPUs which include support for the virtualization extensions can be
+  entered in HYP mode in order to enable the kernel to make full use of
+  these extensions.  This is the recommended boot method for such CPUs,
+  unless the virtualisations are already in use by a pre-installed
+  hypervisor.
+
+  If the kernel is not entered in HYP mode for any reason, it must be
+  entered in SVC mode.
 
 - Caches, MMUs
   The MMU must be off.
   Instruction cache may be on or off.
   Data cache must be off.
 
+  If the kernel is entered in HYP mode, the above requirements apply to
+  the HYP mode configuration in addition to the ordinary PL1 (privileged
+  kernel modes) configuration.  In addition, all traps into the
+  hypervisor must be disabled, and PL1 access must be granted for all
+  peripherals and CPU resources for which this is architecturally
+  possible.  Except for entering in HYP mode, the system configuration
+  should be such that a kernel which does not include support for the
+  virtualization extensions can boot correctly without extra help.
+
 - The boot loader is expected to call the kernel image by jumping
   directly to the first instruction of the kernel image.
 
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:31 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:31 +0100
Subject: [PATCH 1/7] ARM: opcodes: add __ERET/__MSR_ELR_HYP instruction
 encoding
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-2-git-send-email-marc.zyngier@arm.com>

Enabling boot from HYP mode requires the use of some more
virt-specific instructions ("eret" and "msr elr_hyp, reg").

Add the necessary encoding to asm/opcode-virt.h.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/opcodes-virt.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
index b85665a..efcfdf9 100644
--- a/arch/arm/include/asm/opcodes-virt.h
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -26,4 +26,14 @@
 	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
 )
 
+#define __ERET	__inst_arm_thumb32(					\
+	0xE160006E,							\
+	0xF3DE8F00							\
+)
+
+#define __MSR_ELR_HYP(regnum)	__inst_arm_thumb32(			\
+	0xE12EF300 | regnum,						\
+	0xF3808E30 | (regnum << 16)					\
+)
+
 #endif /* ! __ASM_ARM_OPCODES_VIRT_H */
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:37 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:37 +0100
Subject: [PATCH 7/7] ARM: virt: arch_timers: enable access to physical timers
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-8-git-send-email-marc.zyngier@arm.com>

If booting in HYP mode, it makes sense to enable the use of the
physical timers, so the kernel can use them directly.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kernel/hyp-stub.S |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 4ff46fa..8c288ba 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -137,6 +137,19 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
 	mcr	p15, 4, r7, c1, c0, 0	@ HSCTLR
 	isb
 
+#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
+	@ make CNTP_* and CNTPCT accessible from PL1
+	mrc	p15, 0, r7, c0, c1, 1	@ ID_PFR1
+	lsr	r7, #16
+	and	r7, #0xf
+	cmp	r7, #1
+	bne	1f
+	mrc	p15, 4, r7, c14, c1, 0	@ CNTHCTL
+	orr	r7, r7, #3		@ PL1PCEN | PL1PCTEN
+	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
+1:
+#endif
+
 	bic	r7, r4, #MODE_MASK
 	orr	r7, r7, #SVC_MODE
 THUMB(	orr	r7, r7, #PSR_T_BIT	)
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:35 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:35 +0100
Subject: [PATCH 5/7] ARM: virt: Add boot-time diagnostics
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-6-git-send-email-marc.zyngier@arm.com>

From: Dave Martin <dave.martin at linaro.org>

In order to easily detect pathological cases, print some diagnostics
when the kernel boots.

This also provides helpers to detect that HYP mode is actually available,
which can be used by other subsystems to enable HYP specific features.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/virt.h |   17 +++++++++++++++++
 arch/arm/kernel/setup.c     |   20 ++++++++++++++++++++
 arch/arm/kernel/smp.c       |    3 +++
 3 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 0a99723..86164df 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -47,6 +47,23 @@ unsigned long __hyp_get_vectors(void);
 #define __boot_cpu_mode	(SVC_MODE)
 #endif
 
+#ifndef ZIMAGE
+void hyp_mode_check(void);
+
+/* Reports the availability of HYP mode */
+static inline bool is_hyp_mode_available(void)
+{
+	return ((__boot_cpu_mode & MODE_MASK) == HYP_MODE &&
+		!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH));
+}
+
+/* Check if the bootloader has booted CPUs in different modes */
+static inline bool is_hyp_mode_mismatched(void)
+{
+	return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH);
+}
+#endif
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* ! VIRT_H */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcec..04fd01f 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -55,6 +55,7 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/memblock.h>
+#include <asm/virt.h>
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
@@ -937,6 +938,21 @@ static int __init meminfo_cmp(const void *_a, const void *_b)
 	return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
 }
 
+void __init hyp_mode_check(void)
+{
+#ifdef CONFIG_ARM_VIRT_EXT
+	if (is_hyp_mode_available()) {
+		pr_info("CPU: All CPU(s) started in HYP mode.\n");
+		pr_info("CPU: Virtualization extensions available.\n");
+	} else if (is_hyp_mode_mismatched()) {
+		pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
+			__boot_cpu_mode & MODE_MASK);
+		pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
+	} else
+		pr_info("CPU: All CPU(s) started in SVC mode.\n");
+#endif
+}
+
 void __init setup_arch(char **cmdline_p)
 {
 	struct machine_desc *mdesc;
@@ -980,6 +996,10 @@ void __init setup_arch(char **cmdline_p)
 	if (is_smp())
 		smp_init_cpus();
 #endif
+
+	if (!is_smp())
+		hyp_mode_check();
+
 	reserve_crashkernel();
 
 	tcm_init();
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..adf226e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -42,6 +42,7 @@
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
 #include <asm/smp_plat.h>
+#include <asm/virt.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -287,6 +288,8 @@ void __init smp_cpus_done(unsigned int max_cpus)
 	       num_online_cpus(),
 	       bogosum / (500000/HZ),
 	       (bogosum / (5000/HZ)) % 100);
+
+	hyp_mode_check();
 }
 
 void __init smp_prepare_boot_cpu(void)
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:36 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:36 +0100
Subject: [PATCH 6/7] ARM: virt: Add CONFIG_ARM_VIRT_EXT option
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-7-git-send-email-marc.zyngier@arm.com>

From: Dave Martin <dave.martin at linaro.org>

It is now possible to enable the virtualization extention support.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/mm/Kconfig |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101b968..c9a4963 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -624,6 +624,23 @@ config ARM_THUMBEE
 	  Say Y here if you have a CPU with the ThumbEE extension and code to
 	  make use of it. Say N for code that can run on CPUs without ThumbEE.
 
+config ARM_VIRT_EXT
+	bool "Native support for the ARM Virtualization Extensions"
+	depends on MMU && CPU_V7
+	help
+	  Enable the kernel to make use of the ARM Virtualization
+	  Extensions to install hypervisors without run-time firmware
+	  assistance.
+
+	  A compliant bootloader is required in order to make maximum
+	  use of this feature.  Refer to Documentation/arm/Booting for
+	  details.
+
+	  It is safe to enable this option even if the kernel may not be
+	  booted in HYP mode, may not have support for the
+	  virtualization extensions, or may be booted with a
+	  non-compliant bootloader.
+
 config SWP_EMULATE
 	bool "Emulate SWP/SWPB instructions"
 	depends on !CPU_USE_DOMAINS && CPU_V7
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:30 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:30 +0100
Subject: [PATCH 0/7] Allow the kernel to be booted in HYP mode
Message-ID: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>

This patch series allows the kernel (and the decompressor) to be
entered in HYP mode, which is a requirement for supporting hypervisors
such as KVM.

The main idea is to have a stub hypervisor to go back and forth
between HYP and SVC modes, and let the kernel install a full blown
hypervisor if necessary. Also, we ensure that a kernel without virt
support can still be entered in HYP mode and safely go back to SVC.

Most of the heavy lifting has been done by Dave Martin, but all bugs
have been introduced by me while reworking it. This series also relies
on Dave's earlier opcode injection series :
http://comments.gmane.org/gmane.linux.ports.arm.kernel/180901

It's been tested on a variety of platforms (VE A9/A15, Fast Model)
with all combinaisons of entering in HYP or SVC, ARM or Thumb2
kernels.

Patches against 3.6-rc1.

Dave Martin (5):
  ARM: virt: allow the kernel to be entered in HYP mode
  ARM: zImage/virt: hyp mode entry support for the zImage loader
  ARM: virt: Update documentation for hyp mode entry support
  ARM: virt: Add boot-time diagnostics
  ARM: virt: Add CONFIG_ARM_VIRT_EXT option

Marc Zyngier (2):
  ARM: opcodes: add __ERET/__MSR_ELR_HYP instruction encoding
  ARM: virt: arch_timers: enable access to physical timers

 Documentation/arm/Booting           |   22 ++++-
 arch/arm/boot/compressed/.gitignore |    1 +
 arch/arm/boot/compressed/Makefile   |    9 ++-
 arch/arm/boot/compressed/head.S     |   71 ++++++++++-
 arch/arm/include/asm/assembler.h    |   28 +++++
 arch/arm/include/asm/opcodes-virt.h |   10 ++
 arch/arm/include/asm/ptrace.h       |    1 +
 arch/arm/include/asm/virt.h         |   69 +++++++++++
 arch/arm/kernel/Makefile            |    2 +
 arch/arm/kernel/head.S              |   14 ++-
 arch/arm/kernel/hyp-stub.S          |  218 +++++++++++++++++++++++++++++++++++
 arch/arm/kernel/setup.c             |   20 +++
 arch/arm/kernel/smp.c               |    3 +
 arch/arm/mm/Kconfig                 |   17 +++
 14 files changed, 473 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/include/asm/virt.h
 create mode 100644 arch/arm/kernel/hyp-stub.S

-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:33 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:33 +0100
Subject: [PATCH 3/7] ARM: zImage/virt: hyp mode entry support for the zImage
 loader
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-4-git-send-email-marc.zyngier@arm.com>

From: Dave Martin <dave.martin at linaro.org>

The zImage loader needs to turn on the MMU in order to take
advantage of caching while decompressing the zImage.  Running this
in hyp mode would require the LPAE pagetable format to be
supported; to avoid this complexity, this patch switches out of hyp
mode, and returns back to hyp mode just before booting the kernel.

This implementation assumes that the Hyp mode view of memory and the
PL1 view of memory are coherent, providing that the MMU and caches
are off in both, as required by the boot protocol.  The zImage
decompression code must drain the write buffer on completion anyway, and
entry into Hyp mode should flush any prefetch buffer, avoiding hazards
associated with local write buffers and the pipeline.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/boot/compressed/.gitignore |    1 +
 arch/arm/boot/compressed/Makefile   |    9 ++++-
 arch/arm/boot/compressed/head.S     |   71 +++++++++++++++++++++++++++++++---
 arch/arm/kernel/hyp-stub.S          |   18 +++++++++
 4 files changed, 91 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index d0d441c..f79a08e 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,6 +1,7 @@
 ashldi3.S
 font.c
 lib1funcs.S
+hyp-stub.S
 piggy.gzip
 piggy.lzo
 piggy.lzma
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index bb26756..a517153 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -30,6 +30,10 @@ FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
 OBJS		+= string.o
 CFLAGS_string.o	:= -Os
 
+ifeq ($(CONFIG_ARM_VIRT_EXT),y)
+OBJS		+= hyp-stub.o
+endif
+
 #
 # Architecture dependencies
 #
@@ -126,7 +130,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all
+asflags-y := -Wa,-march=all -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
@@ -198,3 +202,6 @@ $(obj)/font.c: $(FONTC)
 
 $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
 	@sed "$(SEDFLAGS)" < $< > $@
+
+$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S
+	$(call cmd,shipped)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b8c64b8..0749a61 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 /*
  * Debugging stuff
@@ -132,7 +133,12 @@ start:
 		.word	start			@ absolute load/run zImage address
 		.word	_edata			@ zImage end address
  THUMB(		.thumb			)
-1:		mov	r7, r1			@ save architecture ID
+1:
+		mrs	r9, cpsr
+#ifdef CONFIG_ARM_VIRT_EXT
+		bl	__hyp_stub_install	@ get into SVC mode, reversibly
+#endif
+		mov	r7, r1			@ save architecture ID
 		mov	r8, r2			@ save atags pointer
 
 #ifndef __ARM_ARCH_2__
@@ -148,9 +154,9 @@ start:
  ARM(		swi	0x123456	)	@ angel_SWI_ARM
  THUMB(		svc	0xab		)	@ angel_SWI_THUMB
 not_angel:
-		mrs	r2, cpsr		@ turn off interrupts to
-		orr	r2, r2, #0xc0		@ prevent angel from running
-		msr	cpsr_c, r2
+		safe_svcmode_maskall r0
+		msr	spsr_cxsf, r9		@ Save the CPU boot mode in
+						@ SPSR
 #else
 		teqp	pc, #0x0c000003		@ turn off interrupts
 #endif
@@ -350,6 +356,20 @@ dtb_check_done:
 		adr	r5, restart
 		bic	r5, r5, #31
 
+/* Relocate the hyp vector base if necessary */
+#ifdef CONFIG_ARM_VIRT_EXT
+		mrs	r0, spsr
+		and	r0, r0, #MODE_MASK
+		cmp	r0, #HYP_MODE
+		bne	1f
+
+		bl	__hyp_get_vectors
+		sub	r0, r0, r5
+		add	r0, r0, r10
+		bl	__hyp_set_vectors
+1:
+#endif
+
 		sub	r9, r6, r5		@ size to copy
 		add	r9, r9, #31		@ rounded up to a multiple
 		bic	r9, r9, #31		@ ... of 32 bytes
@@ -458,11 +478,29 @@ not_relocated:	mov	r0, #0
 		bl	decompress_kernel
 		bl	cache_clean_flush
 		bl	cache_off
-		mov	r0, #0			@ must be zero
 		mov	r1, r7			@ restore architecture number
 		mov	r2, r8			@ restore atags pointer
- ARM(		mov	pc, r4	)		@ call kernel
- THUMB(		bx	r4	)		@ entry point is always ARM
+
+#ifdef CONFIG_ARM_VIRT_EXT
+		mrs	r0, spsr		@ Get saved CPU boot mode
+		and	r0, r0, #MODE_MASK
+		cmp	r0, #HYP_MODE		@ if not booted in HYP mode...
+		bne	__enter_kernel		@ boot kernel directly
+
+		adr	r12, .L__hyp_reentry_vectors_offset
+		ldr	r0, [r12]
+		add	r0, r0, r12
+
+		bl	__hyp_set_vectors
+		__HVC(0)			@ otherwise bounce to hyp mode
+
+		b	.			@ should never be reached
+
+		.align	2
+.L__hyp_reentry_vectors_offset:	.long	__hyp_reentry_vectors - .
+#else
+		b	__enter_kernel
+#endif
 
 		.align	2
 		.type	LC0, #object
@@ -1191,6 +1229,25 @@ memdump:	mov	r12, r0
 #endif
 
 		.ltorg
+
+#ifdef CONFIG_ARM_VIRT_EXT
+.align 5
+__hyp_reentry_vectors:
+		W(b)	.			@ reset
+		W(b)	.			@ undef
+		W(b)	.			@ svc
+		W(b)	.			@ pabort
+		W(b)	.			@ dabort
+		W(b)	__enter_kernel		@ hyp
+		W(b)	.			@ irq
+		W(b)	.			@ fiq
+#endif /* CONFIG_ARM_VIRT_EXT */
+
+__enter_kernel:
+		mov	r0, #0			@ must be 0
+ ARM(		mov	pc, r4	)		@ call kernel
+ THUMB(		bx	r4	)		@ entry point is always ARM
+
 reloc_code_end:
 
 		.align
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 2d529d6..4ff46fa 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -21,6 +21,7 @@
 #include <asm/assembler.h>
 #include <asm/virt.h>
 
+#ifndef ZIMAGE
 /*
  * For the kernel proper, we need to find out the CPU boot mode long after
  * boot, so we need to store it in a writable variable.
@@ -59,6 +60,21 @@ ENTRY(__boot_cpu_mode)
 	strne	r7, [r5, r6]		@ record what happened and give up
 	.endm
 
+#else	/* ZIMAGE */
+
+	.macro	store_primary_cpu_mode	reg1:req, reg2:req, reg3:req
+	.endm
+
+/*
+ * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
+ * consistency checking:
+ */
+	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
+	cmp	\mode, \mode
+	.endm
+
+#endif /* ZIMAGE */
+
 /*
  * Hypervisor stub installation functions.
  *
@@ -169,9 +185,11 @@ ENTRY(__hyp_set_vectors)
 	bx	lr
 ENDPROC(__hyp_set_vectors)
 
+#ifndef ZIMAGE
 .align 2
 .L__boot_cpu_mode_offset:
 	.long	__boot_cpu_mode - .
+#endif
 
 .align 5
 __hyp_stub_vectors:
-- 
1.7.8.6



From marc.zyngier at arm.com  Sat Aug 11 07:04:32 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Sat, 11 Aug 2012 12:04:32 +0100
Subject: [PATCH 2/7] ARM: virt: allow the kernel to be entered in HYP mode
In-Reply-To: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
References: <1344683077-12841-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1344683077-12841-3-git-send-email-marc.zyngier@arm.com>

From: Dave Martin <dave.martin at linaro.org>

This patch does two things:

  * Ensure that asynchronous aborts are masked at kernel entry.
    The bootloader should be masking these anyway, but this reduces
    the damage window just in case it doesn't.

  * Enter svc mode via exception return to ensure that CPU state is
    properly serialised.  This does not matter when switching from
    an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C
    parlance), but it potentially does matter when switching from a
    another privileged mode such as hyp mode.

This should allow the kernel to boot safely either from svc mode or
hyp mode, even if no support for use of the ARM Virtualization
Extensions is built into the kernel.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/assembler.h |   28 ++++++
 arch/arm/include/asm/ptrace.h    |    1 +
 arch/arm/include/asm/virt.h      |   52 +++++++++++
 arch/arm/kernel/Makefile         |    2 +
 arch/arm/kernel/head.S           |   14 ++-
 arch/arm/kernel/hyp-stub.S       |  187 ++++++++++++++++++++++++++++++++++++++
 6 files changed, 281 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/include/asm/virt.h
 create mode 100644 arch/arm/kernel/hyp-stub.S

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 03fb936..658a15d 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -22,6 +22,7 @@
 
 #include <asm/ptrace.h>
 #include <asm/domain.h>
+#include <asm/opcodes-virt.h>
 
 #define IOMEM(x)	(x)
 
@@ -240,6 +241,33 @@
 #endif
 
 /*
+ * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
+ * a scratch register for the macro to overwrite.
+ *
+ * This macro is intended for forcing the CPU into SVC mode at boot time.
+ * you cannot return to the original mode.
+ *
+ * Beware, it also clobers LR.
+ */
+.macro safe_svcmode_maskall reg:req
+	mrs	\reg , cpsr
+	mov	lr , \reg
+	and	lr , lr , #MODE_MASK
+	cmp	lr , #HYP_MODE
+	orr	\reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
+	bic	\reg , \reg , #MODE_MASK
+	orr	\reg , \reg , #SVC_MODE
+THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
+	msr	spsr_cxsf, \reg
+	adr	lr, BSYM(2f)
+	bne	1f
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	movs	pc, lr
+2:
+.endm
+
+/*
  * STRT/LDRT access macros with ARM and Thumb-2 variants
  */
 #ifdef CONFIG_THUMB2_KERNEL
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 355ece5..91ef6c2 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -44,6 +44,7 @@
 #define IRQ_MODE	0x00000012
 #define SVC_MODE	0x00000013
 #define ABT_MODE	0x00000017
+#define HYP_MODE	0x0000001a
 #define UND_MODE	0x0000001b
 #define SYSTEM_MODE	0x0000001f
 #define MODE32_BIT	0x00000010
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
new file mode 100644
index 0000000..0a99723
--- /dev/null
+++ b/arch/arm/include/asm/virt.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2012 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef VIRT_H
+#define VIRT_H
+
+#include <asm/ptrace.h>
+
+/*
+ * Flag indicating that the kernel was not entered in the same mode on every
+ * CPU.  The zImage loader stashes this value in an SPSR, so we need an
+ * architecturally defined flag bit here (the N flag, as it happens)
+ */
+#define BOOT_CPU_MODE_MISMATCH (1<<31)
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ARM_VIRT_EXT
+/*
+ * __boot_cpu_mode records what mode the primary CPU was booted in.
+ * A correctly-implemented bootloader must start all CPUs in the same mode:
+ * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate
+ * that some CPU(s) were booted in a different mode.
+ *
+ * This allows the kernel to flag an error when the secondaries have come up.
+ */
+extern int __boot_cpu_mode;
+
+void __hyp_set_vectors(unsigned long phys_vector_base);
+unsigned long __hyp_get_vectors(void);
+#else
+#define __boot_cpu_mode	(SVC_MODE)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* ! VIRT_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..49b61a3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -82,4 +82,6 @@ head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 
+obj-$(CONFIG_ARM_VIRT_EXT)	+= hyp-stub.o
+
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3db960e..27093e4 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -83,8 +83,12 @@ ENTRY(stext)
  THUMB(	.thumb			)	@ switch to Thumb now.
  THUMB(1:			)
 
-	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
-						@ and irqs disabled
+#ifdef CONFIG_ARM_VIRT_EXT
+	bl	__hyp_stub_install
+#endif
+	@ ensure svc mode and all interrupts masked
+	safe_svcmode_maskall r9
+
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
@@ -326,7 +330,11 @@ ENTRY(secondary_startup)
 	 * the processor type - there is no need to check the machine type
 	 * as it has already been validated by the primary processor.
 	 */
-	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifdef CONFIG_ARM_VIRT_EXT
+	bl	__hyp_stub_install
+#endif
+	safe_svcmode_maskall r9
+
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type
 	movs	r10, r5				@ invalid processor?
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
new file mode 100644
index 0000000..2d529d6
--- /dev/null
+++ b/arch/arm/kernel/hyp-stub.S
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2012 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/virt.h>
+
+/*
+ * For the kernel proper, we need to find out the CPU boot mode long after
+ * boot, so we need to store it in a writable variable.
+ *
+ * This is not in .bss, because we set it sufficiently early that the boot-time
+ * zeroing of .bss would clobber it.
+ */
+.data
+ENTRY(__boot_cpu_mode)
+	.long	0
+.text
+
+	/*
+	 * Save the primary CPU boot mode. Requires 3 scratch registers.
+	 */
+	.macro	store_primary_cpu_mode	reg1, reg2, reg3
+	mrs	\reg1, cpsr
+	and	\reg1, \reg1, #MODE_MASK
+	adr	\reg2, .L__boot_cpu_mode_offset
+	ldr	\reg3, [\reg2]
+	str	\reg1, [\reg2, \reg3]
+	.endm
+
+	/*
+	 * Compare the current mode with the one saved on the primary CPU.
+	 * If they don't match, record that fact. The Z bit indicates
+	 * if there's a match or not.
+	 * Requires 3 additionnal scratch registers.
+	 */
+	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
+	adr	\reg2, .L__boot_cpu_mode_offset
+	ldr	\reg3, [\reg2]
+	ldr	\reg1, [\reg2, \reg3]
+	cmp	\mode, \reg1		@ matches primary CPU boot mode?
+	orrne	r7, r7, #BOOT_CPU_MODE_MISMATCH
+	strne	r7, [r5, r6]		@ record what happened and give up
+	.endm
+
+/*
+ * Hypervisor stub installation functions.
+ *
+ * These must be called with the MMU and D-cache off.
+ * They are not ABI compliant and are only intended to be called from the kernel
+ * entry points in head.S.
+ */
+@ Call this from the primary CPU
+ENTRY(__hyp_stub_install)
+	store_primary_cpu_mode	r4, r5, r6
+ENDPROC(__hyp_stub_install)
+
+	@ fall through...
+
+@ Secondary CPUs should call here
+ENTRY(__hyp_stub_install_secondary)
+	mrs	r4, cpsr
+	and	r4, r4, #MODE_MASK
+
+	/*
+	 * If the secondary has booted with a different mode, give up
+	 * immediately.
+	 */
+	compare_cpu_mode_with_primary	r4, r5, r6, r7
+	bxne	lr
+
+	/*
+	 * Once we have given up on one CPU, we do not try to install the
+	 * stub hypervisor on the remaining ones: because the saved boot mode
+	 * is modified, it can't compare equal to the CPSR mode field any
+	 * more.
+	 *
+	 * Otherwise...
+	 */
+
+	cmp	r4, #HYP_MODE
+	bxne	lr			@ give up if the CPU is not in HYP mode
+
+/*
+ * Configure HSCTLR to set correct exception endianness/instruction set
+ * state etc.
+ * Turn off all traps
+ * Eventually, CPU-specific code might be needed -- assume not for now
+ */
+	@ Now install the hypervisor stub:
+	adr	r7, __hyp_stub_vectors
+	mcr	p15, 4, r7, c12, c0, 0	@ set hypervisor vector base (HVBAR)
+
+	@ Disable all traps, so we don't get any nasty surprise
+	mov	r7, #0
+	mcr	p15, 4, r7, c1, c1, 0	@ HCR
+	mcr	p15, 4, r7, c1, c1, 1	@ HDCR
+	mcr	p15, 4, r7, c1, c1, 2	@ HCPTR
+	mcr	p15, 4, r7, c1, c1, 3	@ HSTR
+
+THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	orr	r7, #(1 << 9)		@ HSCTLR.EE
+#endif
+	mcr	p15, 4, r7, c1, c0, 0	@ HSCTLR
+	isb
+
+	bic	r7, r4, #MODE_MASK
+	orr	r7, r7, #SVC_MODE
+THUMB(	orr	r7, r7, #PSR_T_BIT	)
+	msr	spsr_cxsf, r7		@ This is SPSR_hyp.
+
+	__MSR_ELR_HYP(14)		@ msr elr_hyp, lr
+	__ERET				@ return, switching to SVC mode
+					@ The boot CPU mode is left in r4.
+ENDPROC(__hyp_stub_install_secondary)
+
+__hyp_stub_do_trap:
+	cmp	r0, #-1
+	mrceq	p15, 4, r0, c12, c0, 0	@ get HVBAR
+	mcrne	p15, 4, r0, c12, c0, 0	@ set HVBAR
+	__ERET
+ENDPROC(__hyp_stub_do_trap)
+
+/*
+ * __hyp_set_vectors: Call this after boot to set the initial hypervisor
+ * vectors as part of hypervisor installation.  On an SMP system, this should
+ * be called on each CPU.
+ *
+ * r0 must be the physical address of the new vector table (which must lie in
+ * the bottom 4GB of physical address space.
+ *
+ * r0 must be 32-byte aligned.
+ *
+ * Before calling this, you must check that the stub hypervisor is installed
+ * everywhere, by waiting for any secondary CPUs to be brought up and then
+ * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
+ *
+ * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
+ * something else went wrong... in such cases, trying to install a new
+ * hypervisor is unlikely to work as desired.
+ *
+ * When you call into your shiny new hypervisor, sp_hyp will contain junk,
+ * so you will need to set that to something sensible at the new hypervisor's
+ * initialisation entry point.
+ */
+ENTRY(__hyp_get_vectors)
+	mov	r0, #-1
+ENDPROC(__hyp_get_vectors)
+	@ fall through
+ENTRY(__hyp_set_vectors)
+	__HVC(0)
+	bx	lr
+ENDPROC(__hyp_set_vectors)
+
+.align 2
+.L__boot_cpu_mode_offset:
+	.long	__boot_cpu_mode - .
+
+.align 5
+__hyp_stub_vectors:
+__hyp_stub_reset:	W(b)	.
+__hyp_stub_und:		W(b)	.
+__hyp_stub_svc:		W(b)	.
+__hyp_stub_pabort:	W(b)	.
+__hyp_stub_dabort:	W(b)	.
+__hyp_stub_trap:	W(b)	__hyp_stub_do_trap
+__hyp_stub_irq:		W(b)	.
+__hyp_stub_fiq:		W(b)	.
+ENDPROC(__hyp_stub_vectors)
+
-- 
1.7.8.6



From marex at denx.de  Sat Aug 11 08:47:17 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 11 Aug 2012 14:47:17 +0200
Subject: [PATCH v3] mtd: gpmi: add NAND write verify support
In-Reply-To: <CAMiH66GbOYDpo-RDUct2nCixaf+9vhmT8Ouz+YPx95Z1+g2B1Q@mail.gmail.com>
References: <1344700231-12624-1-git-send-email-shijie8@gmail.com>
 <201208110913.54479.marex@denx.de>
 <CAMiH66GbOYDpo-RDUct2nCixaf+9vhmT8Ouz+YPx95Z1+g2B1Q@mail.gmail.com>
Message-ID: <201208111447.18076.marex@denx.de>

Dear Huang Shijie,

> On Sat, Aug 11, 2012 at 3:13 PM, Marek Vasut <marex at denx.de> wrote:
> > Dear Huang Shijie,
> > 
> > Please re-add credit to Fabio. Also, Fabio fixed the subject to be more
> 
> sorry. Should I add "Reported by : Fabio ...." to the patch?

Yes, at least.

> I really appriaciate Fabio's work, but I do not think Fabio's patch is
> more accurate.
> The nand chips can be 2K page, 4K page and 8K page. But most of the
> time, the nand chip is 4K page.
> If we fix the verify_buf to 8K size as Fabio's patch does. It will
> waste much memory.
> This is my concern now. :)

That's all right, but the rest of your patch is Fabio's work, correct me if I'm 
wrong. Just give the guy some credit, he found the flaw and diag'd it.

> My patch maybe not good. So If Fabio also sends out a new patch which
> allocates the verify_buf with the mtd->writesize size.
> I will ack it.

Either way is OK.

[...]

> > Best regards,
> > Marek Vasut


From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:38 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:38 +0200
Subject: [PATCH 00/11] pinctrl: mvebu: pinctrl driver
Message-ID: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
The SoC specific stubs use the pinctrl-mvebu core driver that handles
pinctrl API and register accesses for common pinctrl registers.

As especially Dove has some pinctrl registers that do not match the
common pinctrl register layout the core driver has been extended by
some callbacks to allow uncommon Dove pinctrl registers.

DT binding documentation is added for all supported SoCs but as
Dove and Kirkwood are not yet ready for full DT support, the pinctrl
driver is only activated for Armada 370 and XP.

The driver has been tested on Dove, 88f6281 variant of Kirkwood,
Armada 370, and XP.

Sebastian Hesselbarth (3):
  pinctrl: mvebu: pinctrl driver core
  pinctrl: mvebu: dove pinctrl driver
  pinctrl: mvebu: kirkwood pinctrl driver

Thomas Petazzoni (8):
  pinctrl: mvebu: add pinctrl driver for Armada 370
  pinctrl: mvebu: add pinctrl driver for Armada XP
  ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs
  ARM: mvebu: Add pinctrl support to Armada XP SoCs
  ARM: mvebu: Add pinctrl support to Armada 370 SoC
  ARM: mvebu: adjust Armada XP evaluation board DTS
  arm: mvebu: enable PINCTRL usage
  arm: mvebu: add pinctrl support in defconfig

 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   71 ++
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 +++++++
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   46 ++
 arch/arm/Kconfig                                   |    3 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    7 +
 arch/arm/boot/dts/armada-370.dtsi                  |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    4 +-
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   27 +
 arch/arm/configs/mvebu_defconfig                   |    2 +
 drivers/pinctrl/Kconfig                            |   34 +
 drivers/pinctrl/Makefile                           |    5 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 +++++++++++
 drivers/pinctrl/pinctrl-armada-xp.c                |  466 ++++++++++++
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++
 drivers/pinctrl/pinctrl-kirkwood.c                 |  460 ++++++++++++
 drivers/pinctrl/pinctrl-mvebu.c                    |  758 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  175 +++++
 21 files changed, 3631 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
 create mode 100644 drivers/pinctrl/pinctrl-dove.c
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:39 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:39 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   46 ++
 drivers/pinctrl/Kconfig                            |   10 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  758 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  175 +++++
 5 files changed, 990 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 0000000..b3e5066
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing to function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+	clock-frequency = <166666667>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..b968335 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,16 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool "Marvell SoC pin controller drivers"
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+	help
+	  Say yes here to support pinctrl driver on Marvell SoCs.
+	  This is only the driver core and additionally needs a SoC specific
+	  driver.
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..007ed32 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 0000000..09172be
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,758 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+struct mvebu_pinctrl_function {
+	unsigned fid;
+	const char *name;
+	const char *setting;
+	const char **groups;
+	unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+	const char *name;
+	struct mvebu_mpp_ctrl *ctrl;
+	struct mvebu_mpp_ctrl_setting *settings;
+	unsigned num_settings;
+	unsigned gid;
+	unsigned *pins;
+	unsigned npins;
+};
+
+struct mvebu_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_desc desc;
+	void __iomem *base;
+	struct mvebu_pinctrl_group *groups;
+	unsigned num_groups;
+	struct mvebu_pinctrl_function *functions;
+	unsigned num_functions;
+	unsigned variant;
+};
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+	struct mvebu_pinctrl *pctl, unsigned pid)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_groups; n++) {
+		if (pid >= pctl->groups[n].pins[0] &&
+		    pid < pctl->groups[n].pins[0] +
+			pctl->groups[n].npins)
+			return &pctl->groups[n];
+	}
+	return NULL;
+}
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+	struct mvebu_pinctrl *pctl, const char *name)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_groups; n++) {
+		if (strcmp(name, pctl->groups[n].name) == 0)
+			return &pctl->groups[n];
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+	unsigned long config)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (config == grp->settings[n].val) {
+			if (!pctl->variant || (pctl->variant &
+					       grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+	const char *name)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (strcmp(name, grp->settings[n].name) == 0) {
+			if (!pctl->variant || (pctl->variant &
+					       grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (grp->settings[n].flags &
+			(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+			if (!pctl->variant || (pctl->variant &
+						grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+	struct mvebu_pinctrl *pctl, const char *name)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_functions; n++) {
+		if (strcmp(name, pctl->functions[n].name) == 0)
+			return &pctl->functions[n];
+	}
+	return NULL;
+}
+
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+				struct mvebu_pinctrl_group *grp,
+				unsigned long *config)
+{
+	unsigned pin = grp->gid;
+	unsigned off = (pin / 8) * 4;
+	unsigned shift = (pin % 8) * 4;
+
+	*config = readl(pctl->base + off);
+	*config >>= shift;
+	*config &= 0xf;
+
+	return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+				struct mvebu_pinctrl_group *grp,
+				unsigned long config)
+{
+	unsigned pin = grp->gid;
+	unsigned off = (pin / 8) * 4;
+	unsigned shift = (pin % 8) * 4;
+	unsigned long reg;
+
+	reg = readl(pctl->base + off);
+	reg &= ~(0xf << shift);
+	reg |= (config << shift);
+	writel(reg, pctl->base + off);
+
+	return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+				unsigned gid, unsigned long *config)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+	if (!grp->ctrl)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_get)
+		return grp->ctrl->mpp_get(grp->ctrl, config);
+
+	return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+				unsigned gid, unsigned long config)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+	if (!grp->ctrl)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_set)
+		return grp->ctrl->mpp_set(grp->ctrl, config);
+
+	return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+					struct seq_file *s, unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+	struct mvebu_mpp_ctrl_setting *curr;
+	unsigned long config;
+	unsigned n;
+
+	if (mvebu_pinconf_group_get(pctldev, gid, &config))
+		return;
+
+	curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+	if (curr) {
+		seq_printf(s, "current: %s", curr->name);
+		if (curr->subname)
+			seq_printf(s, "(%s)", curr->subname);
+		if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+			seq_printf(s, "(");
+			if (curr->flags & MVEBU_SETTING_GPI)
+				seq_printf(s, "i");
+			if (curr->flags & MVEBU_SETTING_GPO)
+				seq_printf(s, "o");
+			seq_printf(s, ")");
+		}
+	} else
+		seq_printf(s, "current: UNKNOWN");
+
+	if (grp->num_settings > 1) {
+		seq_printf(s, ", available = [");
+		for (n = 0; n < grp->num_settings; n++) {
+			if (curr == &grp->settings[n])
+				continue;
+
+			/* skip unsupported settings for this variant */
+			if (pctl->variant &&
+			    !(pctl->variant & grp->settings[n].variant))
+				continue;
+
+			seq_printf(s, " %s", grp->settings[n].name);
+			if (grp->settings[n].subname)
+				seq_printf(s, "(%s)", grp->settings[n].subname);
+			if (grp->settings[n].flags &
+				(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+				seq_printf(s, "(");
+				if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+					seq_printf(s, "i");
+				if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+					seq_printf(s, "o");
+				seq_printf(s, ")");
+			}
+		}
+		seq_printf(s, " ]");
+	}
+	return;
+}
+
+struct pinconf_ops mvebu_pinconf_ops = {
+	.pin_config_group_get = mvebu_pinconf_group_get,
+	.pin_config_group_set = mvebu_pinconf_group_set,
+	.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+					unsigned fid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+				const char * const **groups,
+				unsigned * const num_groups)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	*groups = pctl->functions[fid].groups;
+	*num_groups = pctl->functions[fid].num_groups;
+	return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+			unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+	struct mvebu_mpp_ctrl_setting *setting;
+	int ret;
+
+	setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+						     func->setting);
+	if (!setting) {
+		dev_err(pctl->dev,
+			"unable to find setting %s in group %s\n",
+			func->setting, func->groups[gid]);
+		return -EINVAL;
+	}
+
+	ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+	if (ret) {
+		dev_err(pctl->dev, "cannot set group %s to %s\n",
+			func->groups[gid], func->setting);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+			struct pinctrl_gpio_range *range, unsigned offset)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp;
+	struct mvebu_mpp_ctrl_setting *setting;
+
+	grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_gpio_req)
+		return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+	setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+	if (!setting)
+		return -ENOTSUPP;
+
+	return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp;
+	struct mvebu_mpp_ctrl_setting *setting;
+
+	grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_gpio_dir)
+		return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+	setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+	if (!setting)
+		return -ENOTSUPP;
+
+	if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+	    (!input && (setting->flags & MVEBU_SETTING_GPO)))
+		return 0;
+
+	return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+	.get_functions_count = mvebu_pinmux_get_funcs_count,
+	.get_function_name = mvebu_pinmux_get_func_name,
+	.get_function_groups = mvebu_pinmux_get_groups,
+	.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+	.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+	.enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+						unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+					unsigned gid, const unsigned **pins,
+					unsigned *num_pins)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	*pins = pctl->groups[gid].pins;
+	*num_pins = pctl->groups[gid].npins;
+	return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+					struct device_node *np,
+					struct pinctrl_map **map,
+					unsigned *num_maps)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct property *prop;
+	const char *function;
+	const char *group;
+	int ret, nmaps, n;
+
+	*map = NULL;
+	*num_maps = 0;
+
+	ret = of_property_read_string(np, "marvell,function", &function);
+	if (ret) {
+		dev_err(pctl->dev,
+			"missing marvell,function in node %s\n", np->name);
+		return 0;
+	}
+
+	nmaps = of_property_count_strings(np, "marvell,pins");
+	if (nmaps < 0) {
+		dev_err(pctl->dev,
+			"missing marvell,pins in node %s\n", np->name);
+		return 0;
+	}
+
+	*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+	if (map == NULL) {
+		dev_err(pctl->dev,
+			"cannot allocate pinctrl_map memory for %s\n",
+			np->name);
+		return -ENOMEM;
+	}
+
+	n = 0;
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			continue;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				function, group);
+			continue;
+		}
+
+		(*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+		(*map)[n].data.mux.group = group;
+		(*map)[n].data.mux.function = np->name;
+		n++;
+	}
+
+	*num_maps = nmaps;
+
+	return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+				struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+	.get_groups_count = mvebu_pinctrl_get_groups_count,
+	.get_group_name = mvebu_pinctrl_get_group_name,
+	.get_group_pins = mvebu_pinctrl_get_group_pins,
+	.dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+	.dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+					struct device_node *np, unsigned idx)
+{
+	struct mvebu_pinctrl_function *func = &pctl->functions[idx];
+	struct property *prop;
+	const char *setting;
+	const char *group;
+	unsigned n = 0;
+	int ret, num_groups;
+
+	ret = of_property_read_string(np, "marvell,function", &setting);
+	if (ret) {
+		dev_err(pctl->dev,
+			"missing marvell,function in node %s\n", np->name);
+		return -EINVAL;
+	}
+
+	num_groups = of_property_count_strings(np, "marvell,pins");
+	if (num_groups <= 0) {
+		dev_err(pctl->dev,
+			"missing marvell,pins in node %s\n", np->name);
+		return -EINVAL;
+	}
+
+	func->fid = idx;
+	func->name = np->name;
+	func->setting = setting;
+	func->num_groups = num_groups;
+	func->groups = devm_kzalloc(pctl->dev, num_groups * sizeof(char *),
+				    GFP_KERNEL);
+	if (!func->groups) {
+		dev_err(pctl->dev,
+			"unable to alloc function groups\n");
+		return -ENOMEM;
+	}
+
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			return -EINVAL;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, setting)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				setting, group);
+			return -EINVAL;
+		}
+
+		func->groups[n++] = group;
+	}
+	return 0;
+}
+
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
+					struct mvebu_pinctrl *pctl)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct device_node *np;
+	unsigned nfuncs = 0, n = 0;
+	int ret;
+
+	if (!node)
+		return -ENODEV;
+
+	nfuncs = of_get_child_count(node);
+	if (nfuncs <= 0) {
+		dev_warn(pctl->dev, "no function defined in device node\n");
+		return 0;
+	}
+
+	pctl->num_functions = nfuncs;
+	pctl->functions = devm_kzalloc(&pdev->dev, nfuncs *
+				sizeof(struct mvebu_pinctrl_function),
+				GFP_KERNEL);
+	if (!pctl->functions) {
+		dev_err(pctl->dev, "unable to alloc functions\n");
+		return -ENOMEM;
+	}
+
+	for_each_child_of_node(node, np) {
+		ret = mvebu_pinctrl_dt_parse_function(pctl, np, n++);
+		if (ret) {
+			dev_warn(pctl->dev, "failed to parse function %s\n",
+				np->name);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+	struct mvebu_pinctrl *pctl;
+	struct resource *res;
+	void __iomem *iomem;
+	struct pinctrl_pin_desc *pdesc;
+	unsigned gid, n, k;
+	int ret;
+
+	if (!soc || !soc->controls || !soc->modes) {
+		dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "unable to get resource\n");
+		return -ENODEV;
+	}
+
+	iomem = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	if (!iomem) {
+		dev_err(&pdev->dev, "unable to ioremap\n");
+		return -ENODEV;
+	}
+
+	pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+			GFP_KERNEL);
+	if (!pctl) {
+		dev_err(&pdev->dev, "unable to alloc driver\n");
+		return -ENOMEM;
+	}
+
+	pctl->desc.name = dev_name(&pdev->dev);
+	pctl->desc.owner = THIS_MODULE;
+	pctl->desc.pctlops = &mvebu_pinctrl_ops;
+	pctl->desc.pmxops = &mvebu_pinmux_ops;
+	pctl->desc.confops = &mvebu_pinconf_ops;
+	pctl->variant = soc->variant;
+	pctl->base = iomem;
+	pctl->dev = &pdev->dev;
+	platform_set_drvdata(pdev, pctl);
+
+	/* count controls and create names for mvebu generic
+	   register controls; also does sanity checks */
+	pctl->num_groups = 0;
+	pctl->desc.npins = 0;
+	for (n = 0; n < soc->ncontrols; n++) {
+		struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+		char *names;
+
+		pctl->desc.npins += ctrl->npins;
+		/* initial control pins */
+		for (k = 0; k < ctrl->npins; k++)
+			ctrl->pins[k] = ctrl->pid + k;
+
+		/* special soc specific control */
+		if (ctrl->mpp_get || ctrl->mpp_set) {
+			if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+				dev_err(&pdev->dev, "wrong soc control info\n");
+				return -EINVAL;
+			}
+			pctl->num_groups += 1;
+			continue;
+		}
+
+		/* generic mvebu register control */
+		names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+		if (!names) {
+			dev_err(&pdev->dev, "failed to alloc mpp names\n");
+			return -ENOMEM;
+		}
+		for (k = 0; k < ctrl->npins; k++)
+			sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+		ctrl->name = names;
+		pctl->num_groups += ctrl->npins;
+	}
+
+	pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+			     sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+	if (!pdesc) {
+		dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+		return -ENOMEM;
+	}
+
+	for (n = 0; n < pctl->desc.npins; n++)
+		pdesc[n].number = n;
+	pctl->desc.pins = pdesc;
+
+	pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+			     sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+	if (!pctl->groups) {
+		dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+		return -ENOMEM;
+	}
+
+	/* assign mpp controls to groups */
+	gid = 0;
+	for (n = 0; n < soc->ncontrols; n++) {
+		struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+		pctl->groups[gid].gid = gid;
+		pctl->groups[gid].ctrl = ctrl;
+		pctl->groups[gid].name = ctrl->name;
+		pctl->groups[gid].pins = ctrl->pins;
+		pctl->groups[gid].npins = ctrl->npins;
+
+		/* generic mvebu register control maps to a number of groups */
+		if (!ctrl->mpp_get && !ctrl->mpp_set) {
+			pctl->groups[gid].npins = 1;
+
+			for (k = 1; k < ctrl->npins; k++) {
+				gid++;
+				pctl->groups[gid].gid = gid;
+				pctl->groups[gid].ctrl = ctrl;
+				pctl->groups[gid].name = &ctrl->name[8*k];
+				pctl->groups[gid].pins = &ctrl->pins[k];
+				pctl->groups[gid].npins = 1;
+			}
+		}
+		gid++;
+	}
+
+	/* assign mpp modes to groups */
+	for (n = 0; n < soc->nmodes; n++) {
+		struct mvebu_mpp_mode *mode = &soc->modes[n];
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+		unsigned num_settings;
+
+		if (!grp) {
+			dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+				mode->pid);
+			continue;
+		}
+
+		for (num_settings = 0; ;) {
+			struct mvebu_mpp_ctrl_setting *set =
+				&mode->settings[num_settings];
+
+			if (!set->name)
+				break;
+			num_settings++;
+
+			/* skip unsupported settings for this variant */
+			if (pctl->variant && !(pctl->variant & set->variant))
+				continue;
+
+			/* find gpio/gpo/gpi settings */
+			if (strcmp(set->name, "gpio") == 0)
+				set->flags = MVEBU_SETTING_GPI |
+					MVEBU_SETTING_GPO;
+			else if (strcmp(set->name, "gpo") == 0)
+				set->flags = MVEBU_SETTING_GPO;
+			else if (strcmp(set->name, "gpi") == 0)
+				set->flags = MVEBU_SETTING_GPI;
+		}
+
+		grp->settings = mode->settings;
+		grp->num_settings = num_settings;
+	}
+
+	ret = mvebu_pinctrl_dt_parse(pdev, pctl);
+	if (ret) {
+		/* look for pinmux functions in platform_device data */
+		dev_err(&pdev->dev, "unable to parse device tree\n");
+		return ret;
+	}
+
+	pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+	if (!pctl->pctldev) {
+		dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+	/* register gpio ranges */
+	for (n = 0; n < soc->ngpioranges; n++)
+		pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+	return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+	pinctrl_unregister(pctl->pctldev);
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 0000000..ee8057a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,175 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/*
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * if optional mpp_get/_set functions are set these
+ * are used to get/set a specific mode. Otherwise it is
+ * assumed that the mpp control is based on 4-bit groups
+ * in subsequent registers.
+ *
+ * mpp_gpio_req/_dir functions can be used to allow pin settings
+ * with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+	const char *name;
+	u8 pid;
+	u8 npins;
+	unsigned *pins;
+	int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+	int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+	int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+	int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/*
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * ctrl setting name will be used to switch to this setting in
+ * DT description, e.g. marvell,function = "uart2". subname
+ * is only for debugging purposes.
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization.
+ */
+struct mvebu_mpp_ctrl_setting {
+	u8 val;
+	const char *name;
+	const char *subname;
+	u8 variant;
+	u8 flags;
+#define  MVEBU_SETTING_GPO	(1 << 0)
+#define  MVEBU_SETTING_GPI	(1 << 1)
+};
+
+/*
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ */
+struct mvebu_mpp_mode {
+	u8 pid;
+	struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/*
+ * struct mvebu_pinctrl_soc_info -
+ *       SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ */
+struct mvebu_pinctrl_soc_info {
+	u8 variant;
+	struct mvebu_mpp_ctrl *controls;
+	int ncontrols;
+	struct mvebu_mpp_mode *modes;
+	int nmodes;
+	struct pinctrl_gpio_range *gpioranges;
+	int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh)				\
+	{							\
+		.name = NULL,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = NULL,				\
+		.mpp_set = NULL,				\
+		.mpp_gpio_req = NULL,				\
+		.mpp_gpio_dir = NULL,				\
+	}
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func)			\
+	{							\
+		.name = _name,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = _func ## _get,			\
+		.mpp_set = _func ## _set,			\
+		.mpp_gpio_req = NULL,				\
+		.mpp_gpio_dir = NULL,				\
+	}
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func)		\
+	{							\
+		.name = _name,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = _func ## _get,			\
+		.mpp_set = _func ## _set,			\
+		.mpp_gpio_req = _func ## _gpio_req,		\
+		.mpp_gpio_dir = _func ## _gpio_dir,		\
+	}
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	{							\
+		.val = _val,					\
+		.name = _name,					\
+		.subname = _subname,				\
+		.variant = _mask,				\
+		.flags = 0,					\
+	}
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname)			\
+	MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...)					\
+	{							\
+		.pid = _id,					\
+		.settings = (struct mvebu_mpp_ctrl_setting[]){	\
+			__VA_ARGS__, { } },			\
+	}
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins)	\
+	{							\
+		.name = "mvebu-gpio",				\
+		.id = _id,					\
+		.pin_base = _pinbase,				\
+		.base = _gpiobase,				\
+		.npins = _npins,				\
+	}
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:40 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:40 +0200
Subject: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-3-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   71 +++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    9 +-
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++++++
 5 files changed, 703 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 0000000..9e6eea2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,71 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..cd3d827 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -584,6 +584,7 @@ config ARCH_DOVE
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b968335..e2427eb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
 	bool "Marvell SoC pin controller drivers"
-	depends on ARCH_MVEBU
+	depends on ARCH_MVEBU || ARCH_DOVE
 	select PINMUX
 	select PINCONF
 	help
@@ -155,6 +155,13 @@ config PINCTRL_MVEBU
 	  This is only the driver core and additionally needs a SoC specific
 	  driver.
 
+config PINCTRL_DOVE
+	bool "Support for Marvell Dove SoCs"
+	depends on PINCTRL_MVEBU
+	help
+	  Say yes here to support pinctrl driver on Marvell Dove SoCs
+	  (88AP510).
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 007ed32..d1327df 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 0000000..b16de42
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,622 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE		0xfde00000
+#define DOVE_MPP_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL	(DOVE_MPP_VIRT_BASE + 0x10)
+#define  DOVE_AU0_AC97_SEL		(1 << 16)
+#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1	(1 << 7)
+#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2	(1 << 20)
+#define  DOVE_TWSI_ENABLE_OPTION3	(1 << 21)
+#define  DOVE_TWSI_OPTION3_GPIO		(1 << 22)
+#define DOVE_SSP_CTRL_STATUS_1		(DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1		(1 << 0)
+#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)
+#define  DOVE_NAND_GPIO_EN		(1 << 0)
+#define DOVE_GPIO_LO_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define  DOVE_SPI_GPIO_SEL		(1 << 5)
+#define  DOVE_UART1_GPIO_SEL		(1 << 4)
+#define  DOVE_AU1_GPIO_SEL		(1 << 3)
+#define  DOVE_CAM_GPIO_SEL		(1 << 2)
+#define  DOVE_SD1_GPIO_SEL		(1 << 1)
+#define  DOVE_SD0_GPIO_SEL		(1 << 0)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				 unsigned long *config)
+{
+	unsigned off = (ctrl->pid / 8) * 4;
+	unsigned shift = (ctrl->pid % 8) * 4;
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+	if (pmu & (1 << ctrl->pid))
+		*config = 0x10;
+	else
+		*config = (mpp >> shift) & 0xf;
+	return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				 unsigned long config)
+{
+	unsigned off = (ctrl->pid / 8) * 4;
+	unsigned shift = (ctrl->pid % 8) * 4;
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+	if (config == 0x10)
+		writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+	else {
+		writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+		mpp &= ~(0xf << shift);
+		mpp |= config << shift;
+		writel(mpp, DOVE_MPP_VIRT_BASE + off);
+	}
+	return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long mask;
+
+	if (ctrl->pid == 24)
+		mask = DOVE_CAM_GPIO_SEL;
+	else if (ctrl->pid == 40)
+		mask = DOVE_SD0_GPIO_SEL;
+	else if (ctrl->pid == 46)
+		mask = DOVE_SD1_GPIO_SEL;
+	else if (ctrl->pid == 58)
+		mask = DOVE_SPI_GPIO_SEL;
+	else if (ctrl->pid == 62)
+		mask = DOVE_UART1_GPIO_SEL;
+	else
+		return -EINVAL;
+
+	*config = ((mpp4 & mask) != 0);
+
+	return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long mask;
+
+	if (ctrl->pid == 24)
+		mask = DOVE_CAM_GPIO_SEL;
+	else if (ctrl->pid == 40)
+		mask = DOVE_SD0_GPIO_SEL;
+	else if (ctrl->pid == 46)
+		mask = DOVE_SD1_GPIO_SEL;
+	else if (ctrl->pid == 58)
+		mask = DOVE_SPI_GPIO_SEL;
+	else if (ctrl->pid == 62)
+		mask = DOVE_UART1_GPIO_SEL;
+	else
+		return -EINVAL;
+
+	mpp4 &= ~mask;
+	if (config)
+		mpp4 |= mask;
+
+	writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+	return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+	*config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+	return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long config)
+{
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+	gmpp &= ~DOVE_NAND_GPIO_EN;
+	if (config)
+		gmpp |= DOVE_NAND_GPIO_EN;
+
+	writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+	return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long *config)
+{
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+	*config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+	return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+	pmu &= ~DOVE_AU0_AC97_SEL;
+	if (config)
+		pmu |= DOVE_AU0_AC97_SEL;
+	writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+	return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long *config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	*config = 0;
+	if (mpp4 & DOVE_AU1_GPIO_SEL)
+		*config |= 0x8;
+	if (sspc1 & DOVE_SSP_ON_AU1)
+		*config |= 0x4;
+	if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+		*config |= 0x2;
+	if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+		*config |= 0x1;
+
+	/* SSP/TWSI only if I2S1 not set*/
+	if ((*config & 0x8) == 0)
+		*config &= ~(0x4 | 0x1);
+	/* TWSI only if SPDIFO not set*/
+	if ((*config & 0x2) == 0)
+		*config &= ~(0x1);
+	return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	if (config & 0x1)
+		gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+	if (config & 0x2)
+		gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+	if (config & 0x4)
+		sspc1 |= DOVE_SSP_ON_AU1;
+	if (config & 0x8)
+		mpp4 |= DOVE_AU1_GPIO_SEL;
+
+	writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+	writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+	writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+	return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+	unsigned long config;
+
+	dove_audio1_ctrl_get(ctrl, &config);
+
+	switch (config) {
+	/* mode 0x00 i2s1/spdifo : no gpio */
+	/* mode 0x0c ssp/spdifo  : no gpio */
+	/* mode 0x0f ssp/twsi    : no gpio */
+	case 0x00:
+	case 0x0c:
+	case 0x0f:
+		return -ENOTSUPP;
+
+	/* mode 0x02 i2s1 : gpio[56:57] */
+	/* mode 0x0e ssp  : gpio[56:57] */
+	case 0x02:
+	case 0x0e:
+		if (pid >= 56)
+			return 0;
+
+	/* mode 0x08 spdifo : gpio[52:55] */
+	/* mode 0x0b twsi   : gpio[52:55] */
+	case 0x08:
+	case 0x0b:
+		if (pid <= 55)
+			return 0;
+
+	/* mode 0x0a/gpio : all gpio */
+	case 0x0a:
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+				bool input)
+{
+	return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	*config = 0;
+	if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+		*config = 0x1;
+	else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+		*config = 0x2;
+	else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+		*config = 0x3;
+
+	return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+	gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+	switch (config) {
+	case 1:
+		gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+		break;
+	case 2:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+		break;
+	case 3:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+	return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+	MPP_REG_CTRL(16, 23),
+	MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+	MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+	MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+	MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+	MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(1,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "cts"),
+		MPP_FUNCTION(0x03, "sdio0", "wp"),
+		MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(2,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "prsnt"),
+		MPP_FUNCTION(0x02, "uart2", "txd"),
+		MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x04, "uart1", "rts"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(3,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "act"),
+		MPP_FUNCTION(0x02, "uart2", "rxd"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "uart1", "cts"),
+		MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(4,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rts"),
+		MPP_FUNCTION(0x03, "sdio1", "cd"),
+		MPP_FUNCTION(0x04, "spi1", "miso"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(5,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "cts"),
+		MPP_FUNCTION(0x03, "sdio1", "wp"),
+		MPP_FUNCTION(0x04, "spi1", "cs"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(6,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "txd"),
+		MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x04, "spi1", "mosi"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(7,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rxd"),
+		MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x04, "spi1", "sck"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(8,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "watchdog", "rstout"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(9,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x05, "pex1", "clkreq"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(10,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x05, "ssp", "sclk"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(11,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "prsnt"),
+		MPP_FUNCTION(0x02, "sata-1", "act"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x05, "pex0", "clkreq"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(12,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "act"),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "audio0", "extclk"),
+		MPP_FUNCTION(0x04, "sdio1", "cd"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(13,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "cts"),
+		MPP_FUNCTION(0x03, "audio1", "extclk"),
+		MPP_FUNCTION(0x04, "sdio1", "wp"),
+		MPP_FUNCTION(0x05, "ssp", "extclk"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(14,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "txd"),
+		MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x05, "ssp", "rxd"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(15,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rxd"),
+		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x05, "ssp", "sfrm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(16,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+		MPP_FUNCTION(0x05, "ac97", "sdi1")),
+	MPP_MODE(17,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+		MPP_FUNCTION(0x02, "uart3", "cts"),
+		MPP_FUNCTION(0x03, "sdio0", "wp"),
+		MPP_FUNCTION(0x04, "twsi", "sda"),
+		MPP_FUNCTION(0x05, "ac97", "sdi2")),
+	MPP_MODE(18,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "txd"),
+		MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x04, "lcd0", "pwm"),
+		MPP_FUNCTION(0x05, "ac97", "sdi3")),
+	MPP_MODE(19,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rxd"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "twsi", "sck")),
+	MPP_MODE(20,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "ac97", "sysclko"),
+		MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+		MPP_FUNCTION(0x03, "sdio1", "cd"),
+		MPP_FUNCTION(0x05, "sdio0", "cd"),
+		MPP_FUNCTION(0x06, "spi1", "miso")),
+	MPP_MODE(21,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "uart1", "rts"),
+		MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+		MPP_FUNCTION(0x03, "sdio1", "wp"),
+		MPP_FUNCTION(0x04, "ssp", "sfrm"),
+		MPP_FUNCTION(0x05, "sdio0", "wp"),
+		MPP_FUNCTION(0x06, "spi1", "cs")),
+	MPP_MODE(22,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "uart1", "cts"),
+		MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+		MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x04, "ssp", "txd"),
+		MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x06, "spi1", "mosi")),
+	MPP_MODE(23,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+		MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x04, "ssp", "sclk"),
+		MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x06, "spi1", "sck")),
+	MPP_MODE(24,
+		MPP_FUNCTION(0x00, "camera", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(40,
+		MPP_FUNCTION(0x00, "sdio0", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(46,
+		MPP_FUNCTION(0x00, "sdio1", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(52,
+		MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+		MPP_FUNCTION(0x02, "i2s1", NULL),
+		MPP_FUNCTION(0x08, "spdifo", NULL),
+		MPP_FUNCTION(0x0a, "gpio", NULL),
+		MPP_FUNCTION(0x0b, "twsi", NULL),
+		MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+		MPP_FUNCTION(0x0e, "ssp", NULL),
+		MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+	MPP_MODE(58,
+		MPP_FUNCTION(0x00, "spi0", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(62,
+		MPP_FUNCTION(0x00, "uart1", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(64,
+		MPP_FUNCTION(0x00, "nand", NULL),
+		MPP_FUNCTION(0x01, "gpo", NULL)),
+	MPP_MODE(72,
+		MPP_FUNCTION(0x00, "i2s", NULL),
+		MPP_FUNCTION(0x01, "ac97", NULL)),
+	MPP_MODE(73,
+		MPP_FUNCTION(0x00, "none", NULL),
+		MPP_FUNCTION(0x01, "opt1", NULL),
+		MPP_FUNCTION(0x02, "opt2", NULL),
+		MPP_FUNCTION(0x03, "opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32, 32),
+	MPP_GPIO_RANGE(2, 64, 64,  8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+	.controls = dove_mpp_controls,
+	.ncontrols = ARRAY_SIZE(dove_mpp_controls),
+	.modes = dove_mpp_modes,
+	.nmodes = ARRAY_SIZE(dove_mpp_modes),
+	.gpioranges = dove_mpp_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+	.variant = 0,
+};
+
+static struct clk *pdma_clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+	{ }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match =
+		of_match_device(dove_pinctrl_of_match, &pdev->dev);
+	int ret;
+
+	if (match)
+		pdev->dev.platform_data = match->data;
+
+	/*
+	 * General MPP Configuration Register is part of pdma registers.
+	 * grab clk to make sure it is clocked.
+	 */
+	pdma_clk = clk_get_sys("dove-pdma", NULL);
+	if (IS_ERR(pdma_clk)) {
+		dev_err(&pdev->dev, "unable to get pdma clk\n");
+		return -ENODEV;
+	}
+
+	clk_prepare_enable(pdma_clk);
+	ret = mvebu_pinctrl_probe(pdev);
+	if (!ret)
+		return 0;
+
+	clk_disable_unprepare(pdma_clk);
+	clk_put(pdma_clk);
+	return ret;
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+	int ret;
+
+	ret = mvebu_pinctrl_remove(pdev);
+	if (!IS_ERR(pdma_clk)) {
+		clk_disable_unprepare(pdma_clk);
+		clk_put(pdma_clk);
+	}
+	return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+	.driver = {
+		.name = "dove-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(dove_pinctrl_of_match),
+	},
+	.probe = dove_pinctrl_probe,
+	.remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:42 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:42 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 522 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 0000000..01ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1f84090..caa97cc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -169,6 +169,11 @@ config PINCTRL_KIRKWOOD
 	  Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
 	  (88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
 
+config PINCTRL_ARMADA_370
+	bool "Support for Marvell Armada 370 SoCs"
+	depends on PINCTRL_MVEBU
+	depends on MACH_ARMADA_370_XP
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3006294..e6d6667 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 0000000..b48f472
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+	MPP_MODE(0,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "uart0", "rxd")),
+	MPP_MODE(1,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "uart0", "txd")),
+	MPP_MODE(2,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "i2c0", "sck"),
+	   MPP_FUNCTION(0x2, "uart0", "txd")),
+	MPP_MODE(3,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "i2c0", "sda"),
+	   MPP_FUNCTION(0x2, "uart0", "rxd")),
+	MPP_MODE(4,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+	MPP_MODE(5,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txclko"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x4, "spi1", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "mclk")),
+	MPP_MODE(6,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd0"),
+	   MPP_FUNCTION(0x2, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x4, "tdm", "rst"),
+	   MPP_FUNCTION(0x5, "audio", "sdo")),
+	MPP_MODE(7,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd1"),
+	   MPP_FUNCTION(0x4, "tdm", "tdx"),
+	   MPP_FUNCTION(0x5, "audio", "lrclk")),
+	MPP_MODE(8,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd2"),
+	   MPP_FUNCTION(0x2, "uart0", "rts"),
+	   MPP_FUNCTION(0x4, "tdm", "drx"),
+	   MPP_FUNCTION(0x5, "audio", "bclk")),
+	MPP_MODE(9,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd3"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x3, "sd0", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "spdifo")),
+	MPP_MODE(10,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txctl"),
+	   MPP_FUNCTION(0x2, "uart0", "cts"),
+	   MPP_FUNCTION(0x4, "tdm", "fsync"),
+	   MPP_FUNCTION(0x5, "audio", "sdi")),
+	MPP_MODE(11,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd0"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "sd0", "cmd"),
+	   MPP_FUNCTION(0x4, "spi0", "cs1"),
+	   MPP_FUNCTION(0x5, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x6, "spi1", "cs1")),
+	MPP_MODE(12,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd1"),
+	   MPP_FUNCTION(0x2, "i2c1", "sda"),
+	   MPP_FUNCTION(0x3, "sd0", "d0"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0"),
+	   MPP_FUNCTION(0x5, "audio", "spdifi")),
+	MPP_MODE(13,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd2"),
+	   MPP_FUNCTION(0x2, "i2c1", "sck"),
+	   MPP_FUNCTION(0x3, "sd0", "d1"),
+	   MPP_FUNCTION(0x4, "tdm", "pclk"),
+	   MPP_FUNCTION(0x5, "audio", "rmclk")),
+	MPP_MODE(14,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd3"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x3, "sd0", "d2"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi"),
+	   MPP_FUNCTION(0x5, "spi0", "cs2")),
+	MPP_MODE(15,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxctl"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+	   MPP_FUNCTION(0x3, "sd0", "d3"),
+	   MPP_FUNCTION(0x4, "spi1", "miso"),
+	   MPP_FUNCTION(0x5, "spi0", "cs3")),
+	MPP_MODE(16,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxclk"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x4, "tdm", "int"),
+	   MPP_FUNCTION(0x5, "audio", "extclk")),
+	MPP_MODE(17,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge", "mdc")),
+	MPP_MODE(18,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge", "mdio")),
+	MPP_MODE(19,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txclk"),
+	   MPP_FUNCTION(0x2, "ge1", "txclkout"),
+	   MPP_FUNCTION(0x4, "tdm", "pclk")),
+	MPP_MODE(20,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd4"),
+	   MPP_FUNCTION(0x2, "ge1", "txd0")),
+	MPP_MODE(21,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd5"),
+	   MPP_FUNCTION(0x2, "ge1", "txd1"),
+	   MPP_FUNCTION(0x4, "uart1", "txd")),
+	MPP_MODE(22,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd6"),
+	   MPP_FUNCTION(0x2, "ge1", "txd2"),
+	   MPP_FUNCTION(0x4, "uart0", "rts")),
+	MPP_MODE(23,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd7"),
+	   MPP_FUNCTION(0x2, "ge1", "txd3"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi")),
+	MPP_MODE(24,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "col"),
+	   MPP_FUNCTION(0x2, "ge1", "txctl"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0")),
+	MPP_MODE(25,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxerr"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd0"),
+	   MPP_FUNCTION(0x4, "uart1", "rxd")),
+	MPP_MODE(26,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "crs"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd1"),
+	   MPP_FUNCTION(0x4, "spi1", "miso")),
+	MPP_MODE(27,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd4"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd2"),
+	   MPP_FUNCTION(0x4, "uart0", "cts")),
+	MPP_MODE(28,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd5"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd3")),
+	MPP_MODE(29,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd6"),
+	   MPP_FUNCTION(0x2, "ge1", "rxctl"),
+	   MPP_FUNCTION(0x4, "i2c1", "sda")),
+	MPP_MODE(30,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd7"),
+	   MPP_FUNCTION(0x2, "ge1", "rxclk"),
+	   MPP_FUNCTION(0x4, "i2c1", "sck")),
+	MPP_MODE(31,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x3, "tclk", NULL),
+	   MPP_FUNCTION(0x4, "ge0", "txerr")),
+	MPP_MODE(32,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "cs0")),
+	MPP_MODE(33,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "bootcs"),
+	   MPP_FUNCTION(0x2, "spi0", "cs0")),
+	MPP_MODE(34,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "wen0"),
+	   MPP_FUNCTION(0x2, "spi0", "mosi")),
+	MPP_MODE(35,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "oen"),
+	   MPP_FUNCTION(0x2, "spi0", "sck")),
+	MPP_MODE(36,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a1"),
+	   MPP_FUNCTION(0x2, "spi0", "miso")),
+	MPP_MODE(37,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a0"),
+	   MPP_FUNCTION(0x2, "sata0", "prsnt")),
+	MPP_MODE(38,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ready"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "uart0", "cts")),
+	MPP_MODE(39,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad0"),
+	   MPP_FUNCTION(0x2, "audio", "spdifo")),
+	MPP_MODE(40,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad1"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "uart0", "rts")),
+	MPP_MODE(41,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad2"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd")),
+	MPP_MODE(42,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad3"),
+	   MPP_FUNCTION(0x2, "uart1", "txd")),
+	MPP_MODE(43,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad4"),
+	   MPP_FUNCTION(0x2, "audio", "bclk")),
+	MPP_MODE(44,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad5"),
+	   MPP_FUNCTION(0x2, "audio", "mclk")),
+	MPP_MODE(45,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad6"),
+	   MPP_FUNCTION(0x2, "audio", "lrclk")),
+	MPP_MODE(46,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad7"),
+	   MPP_FUNCTION(0x2, "audio", "sdo")),
+	MPP_MODE(47,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad8"),
+	   MPP_FUNCTION(0x3, "sd0", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "spdifo")),
+	MPP_MODE(48,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad9"),
+	   MPP_FUNCTION(0x2, "uart0", "rts"),
+	   MPP_FUNCTION(0x3, "sd0", "cmd"),
+	   MPP_FUNCTION(0x4, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x5, "spi0", "cs1")),
+	MPP_MODE(49,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad10"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+	   MPP_FUNCTION(0x3, "sd0", "d0"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0"),
+	   MPP_FUNCTION(0x5, "audio", "spdifi")),
+	MPP_MODE(50,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad11"),
+	   MPP_FUNCTION(0x2, "uart0", "cts"),
+	   MPP_FUNCTION(0x3, "sd0", "d1"),
+	   MPP_FUNCTION(0x4, "spi1", "miso"),
+	   MPP_FUNCTION(0x5, "audio", "rmclk")),
+	MPP_MODE(51,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad12"),
+	   MPP_FUNCTION(0x2, "i2c1", "sda"),
+	   MPP_FUNCTION(0x3, "sd0", "d2"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi")),
+	MPP_MODE(52,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad13"),
+	   MPP_FUNCTION(0x2, "i2c1", "sck"),
+	   MPP_FUNCTION(0x3, "sd0", "d3"),
+	   MPP_FUNCTION(0x4, "spi1", "sck")),
+	MPP_MODE(53,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad14"),
+	   MPP_FUNCTION(0x2, "sd0", "clk"),
+	   MPP_FUNCTION(0x3, "tdm", "pclk"),
+	   MPP_FUNCTION(0x4, "spi0", "cs2"),
+	   MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+	MPP_MODE(54,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad15"),
+	   MPP_FUNCTION(0x3, "tdm", "dtx")),
+	MPP_MODE(55,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs1"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x3, "tdm", "rst"),
+	   MPP_FUNCTION(0x4, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x5, "sata0", "prsnt")),
+	MPP_MODE(56,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs2"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "uart0", "cts"),
+	   MPP_FUNCTION(0x4, "spi0", "cs3"),
+	   MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x6, "spi1", "cs1")),
+	MPP_MODE(57,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs3"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "tdm", "fsync"),
+	   MPP_FUNCTION(0x4, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x5, "audio", "sdo")),
+	MPP_MODE(58,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs0"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "tdm", "int"),
+	   MPP_FUNCTION(0x5, "audio", "extclk"),
+	   MPP_FUNCTION(0x6, "uart0", "rts")),
+	MPP_MODE(59,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ale0"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "uart0", "rts"),
+	   MPP_FUNCTION(0x5, "audio", "bclk")),
+	MPP_MODE(60,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ale1"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x4, "pcie", "rst-out"),
+	   MPP_FUNCTION(0x5, "audio", "sdi")),
+	MPP_MODE(61,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "wen1"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x5, "audio", "rclk")),
+	MPP_MODE(62,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a2"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "tdm", "drx"),
+	   MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x5, "audio", "mclk"),
+	   MPP_FUNCTION(0x6, "uart0", "cts")),
+	MPP_MODE(63,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "sck"),
+	   MPP_FUNCTION(0x2, "tclk", NULL)),
+	MPP_MODE(64,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "miso"),
+	   MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+	MPP_MODE(65,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "mosi"),
+	   MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,mv88f6710-pinctrl" },
+	{ },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+	MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+	soc->variant = 0;
+	soc->controls = mv88f6710_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+	soc->modes = mv88f6710_mpp_modes;
+	soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+	soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+	soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+	.driver = {
+		.name = "armada-370-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+	},
+	.probe = armada_370_pinctrl_probe,
+	.remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:41 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:41 +0200
Subject: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    9 +-
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  460 ++++++++++++++++++++
 5 files changed, 749 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 0000000..361bccb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd3d827..361f513 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e2427eb..1f84090 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
 	bool "Marvell SoC pin controller drivers"
-	depends on ARCH_MVEBU || ARCH_DOVE
+	depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
 	select PINMUX
 	select PINCONF
 	help
@@ -162,6 +162,13 @@ config PINCTRL_DOVE
 	  Say yes here to support pinctrl driver on Marvell Dove SoCs
 	  (88AP510).
 
+config PINCTRL_KIRKWOOD
+	bool "Support for Marvell Kirkwood SoCs"
+	depends on PINCTRL_MVEBU
+	help
+	  Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
+	  (88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d1327df..3006294 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 0000000..ef07f28
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,460 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282)		\
+	((f6180 << 0) | (f6190 << 1) | (f6192 << 2) |	\
+	 (f6281 << 3) | (f6282 << 4))
+
+#define VARIANT_MV88F6180	V(1, 0, 0, 0, 0)
+#define VARIANT_MV88F6190	V(0, 1, 0, 0, 0)
+#define VARIANT_MV88F6192	V(0, 0, 1, 0, 0)
+#define VARIANT_MV88F6281	V(0, 0, 0, 1, 0)
+#define VARIANT_MV88F6282	V(0, 0, 0, 0, 1)
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io2",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1))),
+	MPP_MODE(1,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io3",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "mosi",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(2,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io4",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(3,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io5",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(4,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io6",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0))),
+	MPP_MODE(5,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io7",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(6,
+		MPP_VAR_FUNCTION(0x0, "sysrst", "out",   V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "spi", "mosi",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(7,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "pex", "rsto",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(8,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sda",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(9,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sck",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "evreq",    V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(10,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0X3, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(11,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq",  V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xc, "ptp-2", "trig",   V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(12,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 0, 1)),
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "clk",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "mosi",     V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(13,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "cmd",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "rmclk",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(14,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d0",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "audio-1", "sdi",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(15,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d1",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "cs",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(16,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d2",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "extclk",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(17,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d3",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "sata1", "act",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(18,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io0",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "pex", "clkreq",   V(0, 0, 0, 0, 1))),
+	MPP_MODE(19,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io1",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(20,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d0",       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(1, 0, 0, 0, 0))),
+	MPP_MODE(21,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d1",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(22,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d2",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(23,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d3",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(24,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d4",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(25,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d5",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(26,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d6",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(27,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d7",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(28,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "col",      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d8",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(29,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d9",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(30,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d10",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(31,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d11",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(32,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclko",   V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d12",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(33,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d13",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(34,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txen",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d14",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(35,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxerr",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d15",      V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(36,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(37,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(38,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d18",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(39,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d19",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(40,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d20",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(41,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d21",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(42,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d22",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(43,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d23",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(44,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "clk",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(45,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "e",        V(0, 0, 0, 0, 1))),
+	MPP_MODE(46,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(47,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(48,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d16",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(49,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "ptp", "clk",      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0xa, "pex", "clkreq",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d17",      V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+	MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32,  4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,88f6180-pinctrl",
+					  .data = (void *)VARIANT_MV88F6180 },
+	{ .compatible = "marvell,88f6190-pinctrl",
+					  .data = (void *)VARIANT_MV88F6190 },
+	{ .compatible = "marvell,88f6192-pinctrl",
+					  .data = (void *)VARIANT_MV88F6192 },
+	{ .compatible = "marvell,88f6281-pinctrl",
+					  .data = (void *)VARIANT_MV88F6281 },
+	{ .compatible = "marvell,88f6282-pinctrl",
+					  .data = (void *)VARIANT_MV88F6282 },
+	{ }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+	if (match) {
+		soc->variant = (unsigned)match->data & 0xff;
+		switch (soc->variant) {
+		case VARIANT_MV88F6180:
+			soc->controls = mv88f6180_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f6180_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+			break;
+		case VARIANT_MV88F6190:
+		case VARIANT_MV88F6192:
+			soc->controls = mv88f619x_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f619x_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+			break;
+		case VARIANT_MV88F6281:
+		case VARIANT_MV88F6282:
+			soc->controls = mv88f628x_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f628x_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+			break;
+		}
+		pdev->dev.platform_data = soc;
+	}
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+	.driver = {
+		.name = "kirkwood-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+	},
+	.probe = kirkwood_pinctrl_probe,
+	.remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:44 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:44 +0200
Subject: [PATCH 06/11] ARM: mvebu: add pinctrl device in DT for Armada 370/XP
 SoCs
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-7-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

The Armada 370 and XP SoCs have configurable muxing for a certain
number of their pins, controlled through a pinctrl driver.

The 'compatible' property is defined in the SoC-specific .dtsi files,
since the compatible string identifies the number of pins and other
SoC-specific properties.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932..7c72a70 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,13 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+                pinctrl at d0018000 {
+                               reg = <0xd0018000 0x38>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges;
+                };
 	};
 };
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:46 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:46 +0200
Subject: [PATCH 08/11] ARM: mvebu: Add pinctrl support to Armada 370 SoC
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-9-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada 370 SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-370.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..875fcd8 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,5 +31,9 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+                pinctrl at d0018000 {
+			        compatible = "marvell,mv88f6710-pinctrl";
+	        };
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:43 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:43 +0200
Subject: [PATCH 05/11] pinctrl: mvebu: add pinctrl driver for Armada XP
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-6-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  466 ++++++++++++++++++++
 4 files changed, 572 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 0000000..bfa0a2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index caa97cc..5502539 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -174,6 +174,11 @@ config PINCTRL_ARMADA_370
 	depends on PINCTRL_MVEBU
 	depends on MACH_ARMADA_370_XP
 
+config PINCTRL_ARMADA_XP
+	bool "Support for Marvell Armada XP SoCs"
+	depends on PINCTRL_MVEBU
+	depends on MACH_ARMADA_370_XP
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e6d6667..f2ea050 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 0000000..21befef
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,466 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V_MV78230 (1 << 0)
+#define V_MV78260 (1 << 1)
+#define V_MV78460 (1 << 2)
+
+#define V_MV78230_PLUS (V_MV78230 | V_MV78260 | V_MV78460)
+#define V_MV78260_PLUS (V_MV78260 | V_MV78460)
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txclko",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d0",         V_MV78230_PLUS)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d1",         V_MV78230_PLUS)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d2",         V_MV78230_PLUS)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d3",         V_MV78230_PLUS)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d4",         V_MV78230_PLUS)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d5",         V_MV78230_PLUS)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d6",         V_MV78230_PLUS)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d7",         V_MV78230_PLUS)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d8",         V_MV78230_PLUS)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d9",         V_MV78230_PLUS)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d10",        V_MV78230_PLUS)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d11",        V_MV78230_PLUS)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "clkout",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d12",        V_MV78230_PLUS)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd5",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d13",        V_MV78230_PLUS)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd6",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d14",        V_MV78230_PLUS)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d15",        V_MV78230_PLUS)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d16",        V_MV78230_PLUS)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "col",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d17",        V_MV78230_PLUS)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "trig",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d18",        V_MV78230_PLUS)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "crs",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "evreq",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d19",        V_MV78230_PLUS)),
+	MPP_MODE(20,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d20",        V_MV78230_PLUS)),
+	MPP_MODE(21,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "mem", "bat",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d21",        V_MV78230_PLUS)),
+	MPP_MODE(22,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d22",        V_MV78230_PLUS)),
+	MPP_MODE(23,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d23",        V_MV78230_PLUS)),
+	MPP_MODE(24,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re",   V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "rst",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "hsync",      V_MV78230_PLUS)),
+	MPP_MODE(25,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we",   V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "pclk",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vsync",      V_MV78230_PLUS)),
+	MPP_MODE(26,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "fsync",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+	MPP_MODE(27,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "trig",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "dtx",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "e",          V_MV78230_PLUS)),
+	MPP_MODE(28,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "evreq",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "drx",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "pwm",        V_MV78230_PLUS)),
+	MPP_MODE(29,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(30,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int1",       V_MV78230_PLUS)),
+	MPP_MODE(31,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "cmd",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(32,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d0",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+	MPP_MODE(33,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d1",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS)),
+	MPP_MODE(34,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d2",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int5",       V_MV78230_PLUS)),
+	MPP_MODE(35,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d3",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int6",       V_MV78230_PLUS)),
+	MPP_MODE(36,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "mosi",       V_MV78230_PLUS)),
+	MPP_MODE(37,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "miso",       V_MV78230_PLUS)),
+	MPP_MODE(38,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "sck",        V_MV78230_PLUS)),
+	MPP_MODE(39,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs0",        V_MV78230_PLUS)),
+	MPP_MODE(40,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
+	MPP_MODE(41,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs2",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart2", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync",  V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1",   V_MV78230_PLUS)),
+	MPP_MODE(42,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "rxd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart0", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(43,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd",  V_MV78460)),
+	MPP_MODE(44,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart3", "rxd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs4",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2",   V_MV78230_PLUS)),
+	MPP_MODE(45,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart3", "txd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs5",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",    V_MV78230_PLUS)),
+	MPP_MODE(46,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart3", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart1", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs6",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",    V_MV78230_PLUS)),
+	MPP_MODE(47,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart3", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart1", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs7",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "ref", "clkout",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3",   V_MV78230_PLUS)),
+	MPP_MODE(48,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "tclk", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+	MPP_MODE(49,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "we3",        V_MV78260_PLUS)),
+	MPP_MODE(50,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "we2",        V_MV78260_PLUS)),
+	MPP_MODE(51,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad16",       V_MV78260_PLUS)),
+	MPP_MODE(52,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad17",       V_MV78260_PLUS)),
+	MPP_MODE(53,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad18",       V_MV78260_PLUS)),
+	MPP_MODE(54,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad19",       V_MV78260_PLUS)),
+	MPP_MODE(55,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd",    V_MV78260_PLUS)),
+	MPP_MODE(56,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd",    V_MV78260_PLUS)),
+	MPP_MODE(57,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd",  V_MV78460)),
+	MPP_MODE(58,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad23",       V_MV78260_PLUS)),
+	MPP_MODE(59,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad24",       V_MV78260_PLUS)),
+	MPP_MODE(60,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad25",       V_MV78260_PLUS)),
+	MPP_MODE(61,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad26",       V_MV78260_PLUS)),
+	MPP_MODE(62,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad27",       V_MV78260_PLUS)),
+	MPP_MODE(63,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad28",       V_MV78260_PLUS)),
+	MPP_MODE(64,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad29",       V_MV78260_PLUS)),
+	MPP_MODE(65,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad30",       V_MV78260_PLUS)),
+	MPP_MODE(66,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad31",       V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+	{
+		.compatible = "marvell,mv78230-pinctrl",
+		.data       = (void *) V_MV78230,
+	},
+	{
+		.compatible = "marvell,mv78260-pinctrl",
+		.data       = (void *) V_MV78260,
+	},
+	{
+		.compatible = "marvell,mv78460-pinctrl",
+		.data       = (void *) V_MV78460,
+	},
+	{ },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+	MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+	MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+	MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+	if (!match)
+		return -ENODEV;
+
+	soc->variant = (unsigned) match->data & 0xff;
+
+	switch (soc->variant) {
+	case V_MV78230:
+		soc->controls = mv78230_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78230_mpp_controls[0].npins;
+		soc->gpioranges = mv78230_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+		break;
+	case V_MV78260:
+		soc->controls = mv78260_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78260_mpp_controls[0].npins;
+		soc->gpioranges = mv78260_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+		break;
+	case V_MV78460:
+		soc->controls = mv78460_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78460_mpp_controls[0].npins;
+		soc->gpioranges = mv78460_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+		break;
+	}
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+	.driver = {
+		.name = "armada-xp-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+	},
+	.probe = armada_xp_pinctrl_probe,
+	.remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:47 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:47 +0200
Subject: [PATCH 09/11] ARM: mvebu: adjust Armada XP evaluation board DTS
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-10-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

The Armada XP evaluation board is based on the MV78460 Armava XP
SoC. Now that we have separate .dtsi files for the three different
SoCs of the Armada XP family, use the appropriate one as include for
the Armada XP evaluation board .dts file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d..b1fc728 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:49 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:49 +0200
Subject: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-12-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/configs/mvebu_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31..cb07e64 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:48 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:48 +0200
Subject: [PATCH 10/11] arm: mvebu: enable PINCTRL usage
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-11-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Now that we have a proper pinctrl driver for Marvell EBU platforms,
enable PINCTRL support in ARCH_MVEBU.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 361f513..95317a9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Sat Aug 11 08:56:45 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 11 Aug 2012 14:56:45 +0200
Subject: [PATCH 07/11] ARM: mvebu: Add pinctrl support to Armada XP SoCs
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344689809-6223-8-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.

Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 0000000..69ad287
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78230-pinctrl";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 0000000..0f38fa9
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78260-pinctrl";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 0000000..9e61836
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78460-pinctrl";
+		};
+	};
+ };
-- 
1.7.10.4



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:41 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:41 +0200
Subject: gpio: mvebu: new gpio driver for mvebu platforms
Message-ID: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This patch set adds a new GPIO driver for Marvell EBU SoCs, which aims
at replacing the existing GPIO driver from plat-orion/gpio.c. The
driver comes with the necessary DT changes to make it work on Armada
370 and Armada XP, and it has been tested successfully by Sebastian
Hesselbarth on Dove. It should also work flawlessly on other Marvell
EBU SoCs (Kirkwood, Orion, Discovery), but this remains to be tested
by the relevant maintainers.

This new driver reuses a lot of code from the existing
plat-orion/gpio.c driver, but has a number of advantages:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only. This driver has been submitted by
    Sebastian Hesselbarth today on the LAKML.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

Thanks,

Thomas

The following changes since commit 872b6be95abf9d57e0639d0345fa2b5a0e4fa0f4:

  arm: mvebu: add pinctrl support in defconfig (2012-08-11 11:27:33 +0200)

are available in the git repository at:

  git://github.com/MISL-EBU-System-SW/mainline-public.git mvebu-gpio

for you to fetch changes up to 92dffc2d360b84d154ffdc049346d5011592bc7f:

  arm: mvebu: add gpio support in defconfig (2012-08-11 15:20:55 +0200)

----------------------------------------------------------------
Thomas Petazzoni (5):
      gpio: introduce gpio-mvebu driver for Marvell SoCs
      Documentation: add description of DT binding for the gpio-mvebu driver
      arm: mvebu: use GPIO support now that a driver is available
      arm: mvebu: add DT information for GPIO banks on Armada 370 and XP
      arm: mvebu: add gpio support in defconfig

 .../devicetree/bindings/gpio/gpio-mvebu.txt        |   44 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370.dtsi                  |   30 +
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   22 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   33 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   33 +
 arch/arm/configs/mvebu_defconfig                   |    2 +
 arch/arm/mach-mvebu/include/mach/gpio.h            |    1 +
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-mvebu.c                          |  650 ++++++++++++++++++++
 11 files changed, 823 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h
 create mode 100644 drivers/gpio/gpio-mvebu.c



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:42 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:42 +0200
Subject: [PATCH 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs
In-Reply-To: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344691906-15985-2-git-send-email-thomas.petazzoni@free-electrons.com>

This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
and is designed to be compatible with all Marvell EBU SoCs: Orion,
Kirkwood, Dove, Armada 370/XP and Discovery.

It has been successfully tested on Dove and Armada XP at the moment.

Compared to the plat-orion driver, this new driver has the following
added benefits:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 drivers/gpio/Kconfig      |    6 +
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/gpio-mvebu.c |  650 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 657 insertions(+)
 create mode 100644 drivers/gpio/gpio-mvebu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..993b0c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -150,6 +150,12 @@ config GPIO_MSM_V2
 	  Qualcomm MSM chips.  Most of the pins on the MSM can be
 	  selected for GPIO, and are controlled by this driver.
 
+config GPIO_MVEBU
+	def_bool y
+	depends on ARCH_MVEBU
+	select GPIO_GENERIC
+	select GENERIC_IRQ_CHIP
+
 config GPIO_MXC
 	def_bool y
 	depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..1a33e67 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSIC)		+= gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)	+= gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2.o
+obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
 obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
new file mode 100644
index 0000000..d008e55
--- /dev/null
+++ b/drivers/gpio/gpio-mvebu.c
@@ -0,0 +1,650 @@
+/*
+ * GPIO driver for Marvell SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This driver is a fairly straightforward GPIO driver for the
+ * complete family of Marvell EBU SoC platforms (Orion, Dove,
+ * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
+ * driver is the different register layout that exists between the
+ * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
+ * platforms (MV78200 from the Discovery family and the Armada
+ * XP). Therefore, this driver handles three variants of the GPIO
+ * block:
+ * - the basic variant, called "orion-gpio", with the simplest
+ *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
+ *   non-SMP Discovery systems
+ * - the mv78200 variant for MV78200 Discovery systems. This variant
+ *   turns the edge mask and level mask registers into CPU0 edge
+ *   mask/level mask registers, and adds CPU1 edge mask/level mask
+ *   registers.
+ * - the armadaxp variant for Armada XP systems. This variant keeps
+ *   the normal cause/edge mask/level mask registers when the global
+ *   interrupts are used, but adds per-CPU cause/edge mask/level mask
+ *   registers n a separate memory area for the per-CPU GPIO
+ *   interrupts.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF		0x0000
+#define GPIO_IO_CONF_OFF	0x0004
+#define GPIO_BLINK_EN_OFF	0x0008
+#define GPIO_IN_POL_OFF		0x000c
+#define GPIO_DATA_IN_OFF	0x0010
+#define GPIO_EDGE_CAUSE_OFF	0x0014
+#define GPIO_EDGE_MASK_OFF	0x0018
+#define GPIO_LEVEL_MASK_OFF	0x001c
+
+/* The MV78200 has per-CPU registers for edge mask and level mask */
+#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
+#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
+
+/* The Armada XP has per-CPU registers for interrupt cause, interrupt
+ * mask and interrupt level mask. Those are relative to the
+ * percpu_membase. */
+#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
+#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
+#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
+
+#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
+#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
+#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+
+struct mvebu_gpio_chip {
+	struct gpio_chip   chip;
+	spinlock_t	   lock;
+	void __iomem	  *membase;
+	void __iomem	  *percpu_membase;
+	unsigned int       irqbase;
+	struct irq_domain *domain;
+	int                soc_variant;
+};
+
+/*
+ * Common functions to all SoCs
+ */
+static void __iomem *GPIO_OUT(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_OUT_OFF;
+}
+
+static void __iomem *GPIO_IO_CONF(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IO_CONF_OFF;
+}
+
+static void __iomem *GPIO_IN_POL(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IN_POL_OFF;
+}
+
+static void __iomem *GPIO_DATA_IN(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_DATA_IN_OFF;
+}
+
+static void __iomem *GPIO_EDGE_CAUSE(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static void __iomem *GPIO_EDGE_MASK(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_EDGE_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static void __iomem *GPIO_LEVEL_MASK(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_LEVEL_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+	return pinctrl_request_gpio(chip->base + pin);
+}
+
+void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
+{
+	pinctrl_free_gpio(chip->base + pin);
+}
+
+static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	u32 u;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_OUT(mvchip));
+	if (value)
+		u |= 1 << pin;
+	else
+		u &= ~(1 << pin);
+	writel(u, GPIO_OUT(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+}
+
+static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	u32 u;
+
+	if (readl(GPIO_IO_CONF(mvchip)) & (1 << pin)) {
+		u = readl(GPIO_DATA_IN(mvchip)) ^ readl(GPIO_IN_POL(mvchip));
+	} else {
+		u = readl(GPIO_OUT(mvchip));
+	}
+
+	return (u >> pin) & 1;
+}
+
+static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an input GPIO */
+	ret = pinctrl_gpio_direction_input(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_IO_CONF(mvchip));
+	u |= 1 << pin;
+	writel(u, GPIO_IO_CONF(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+				       int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an output GPIO */
+	ret = pinctrl_gpio_direction_output(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_IO_CONF(mvchip));
+	u &= ~(1 << pin);
+	writel(u, GPIO_IO_CONF(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	return irq_create_mapping(mvchip->domain, pin);
+}
+
+static void mvebu_gpio_irq_ack(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = ~(1 << (d->irq - gc->irq_base));
+
+	irq_gc_lock(gc);
+	writel(mask, GPIO_EDGE_CAUSE(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel(gc->mask_cache, GPIO_EDGE_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel(gc->mask_cache, GPIO_EDGE_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel(gc->mask_cache, GPIO_LEVEL_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel(gc->mask_cache, GPIO_LEVEL_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+/*****************************************************************************
+ * MVEBU GPIO IRQ
+ *
+ * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ *                     Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
+ *                     Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ *                     the polarity to catch the next line transaction.
+ *                     This is a race condition that might not perfectly
+ *                     work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ *                    EDGE  cause    mask
+ *        data-in   /--------| |-----| |----\
+ *     -----| |-----                         ---- to main cause reg
+ *           X      \----------------| |----/
+ *        polarity    LEVEL          mask
+ *
+ ****************************************************************************/
+
+static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct irq_chip_type *ct = irq_data_get_chip_type(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	int pin;
+	u32 u;
+
+	pin = d->hwirq - mvchip->irqbase;
+
+	u = readl(GPIO_IO_CONF(mvchip)) & (1 << pin);
+	if (!u) {
+		return -EINVAL;
+	}
+
+	type &= IRQ_TYPE_SENSE_MASK;
+	if (type == IRQ_TYPE_NONE)
+		return -EINVAL;
+
+	/* Check if we need to change chip and handler */
+	if (!(ct->type & type))
+		if (irq_setup_alt_chip(d, type))
+			return -EINVAL;
+
+	/*
+	 * Configure interrupt polarity.
+	 */
+	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
+		u = readl(GPIO_IN_POL(mvchip));
+		u &= ~(1 << pin);
+		writel(u, GPIO_IN_POL(mvchip));
+	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
+		u = readl(GPIO_IN_POL(mvchip));
+		u |= 1 << pin;
+		writel(u, GPIO_IN_POL(mvchip));
+	} else if (type == IRQ_TYPE_EDGE_BOTH) {
+		u32 v;
+
+		v = readl(GPIO_IN_POL(mvchip)) ^ readl(GPIO_DATA_IN(mvchip));
+
+		/*
+		 * set initial polarity based on current input level
+		 */
+		u = readl(GPIO_IN_POL(mvchip));
+		if (v & (1 << pin))
+			u |= 1 << pin;		/* falling */
+		else
+			u &= ~(1 << pin);	/* rising */
+		writel(u, GPIO_IN_POL(mvchip));
+	}
+	return 0;
+}
+
+static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+	u32 cause, type;
+	int i;
+
+	if (mvchip == NULL)
+		return;
+
+	cause = readl(GPIO_DATA_IN(mvchip)) & readl(GPIO_LEVEL_MASK(mvchip));
+	cause |= readl(GPIO_EDGE_CAUSE(mvchip)) & readl(GPIO_EDGE_MASK(mvchip));
+
+	for (i = 0; i < mvchip->chip.ngpio; i++) {
+		int irq;
+
+		irq = mvchip->irqbase + i;
+
+		if (!(cause & (1 << i)))
+			continue;
+
+		type = irqd_get_trigger_type(irq_get_irq_data(irq));
+		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+			/* Swap polarity (race with GPIO line) */
+			u32 polarity;
+
+			polarity = readl(GPIO_IN_POL(mvchip));
+			polarity ^= 1 << i;
+			writel(polarity, GPIO_IN_POL(mvchip));
+		}
+		generic_handle_irq(irq);
+	}
+}
+
+static struct platform_device_id mvebu_gpio_ids[] = {
+	{
+		.name = "orion-gpio",
+	}, {
+		.name = "mv78200-gpio",
+	}, {
+		.name = "armadaxp-gpio",
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
+
+static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
+	{
+		.compatible = "marvell,orion-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
+	},
+	{
+		.compatible = "marvell,mv78200-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
+	},
+	{
+		.compatible = "marvell,armadaxp-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
+	},
+	{
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
+
+static unsigned int mvebu_gpio_chip_count;
+
+static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
+{
+	struct mvebu_gpio_chip *mvchip;
+	const struct of_device_id *match;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *res;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	unsigned int ngpios;
+	int soc_variant;
+	int irqbase;
+	int i, cpu;
+
+	match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
+	if (match)
+		soc_variant = (int) match->data;
+	else
+		soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (! res) {
+		dev_err(&pdev->dev, "Cannot get memory resource\n");
+		return -ENODEV;
+	}
+
+	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
+	if (! mvchip){
+		dev_err(&pdev->dev, "Cannot allocate memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
+		dev_err(&pdev->dev, "Missing ngpios OF property\n");
+		return -ENODEV;
+	}
+
+	mvchip->soc_variant = soc_variant;
+	mvchip->chip.label = kasprintf(GFP_KERNEL, "mvebu-gpio%d", mvebu_gpio_chip_count);
+	mvchip->chip.dev = &pdev->dev;
+	mvchip->chip.request = mvebu_gpio_request;
+	mvchip->chip.direction_input = mvebu_gpio_direction_input;
+	mvchip->chip.get = mvebu_gpio_get;
+	mvchip->chip.direction_output = mvebu_gpio_direction_output;
+	mvchip->chip.set = mvebu_gpio_set;
+	mvchip->chip.to_irq = mvebu_gpio_to_irq;
+	mvchip->chip.base = mvebu_gpio_chip_count * 32;
+	mvchip->chip.ngpio = ngpios;
+	mvchip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+	mvchip->chip.of_node = np;
+#endif
+
+	spin_lock_init(&mvchip->lock);
+	mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
+	if (! mvchip->membase) {
+		dev_err(&pdev->dev, "Cannot ioremap\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	/* The Armada XP has a second range of registers for the
+	 * per-CPU registers */
+	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (! res) {
+			dev_err(&pdev->dev, "Cannot get memory resource\n");
+			kfree(mvchip->chip.label);
+			return -ENODEV;
+		}
+
+		mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
+		if (! mvchip->percpu_membase) {
+			dev_err(&pdev->dev, "Cannot ioremap\n");
+			kfree(mvchip->chip.label);
+			return -ENOMEM;
+		}
+	}
+
+	/*
+	 * Mask and clear GPIO interrupts.
+	 */
+	switch(soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		writel(0, GPIO_EDGE_CAUSE(mvchip));
+		for (cpu = 0; cpu < 2; cpu++) {
+			writel(0, mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu));
+			writel(0, mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu));
+		}
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		for (cpu = 0; cpu < 4; cpu++) {
+			writel(0, mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
+			writel(0, mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
+			writel(0, mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
+		}
+		break;
+	default:
+		BUG();
+	}
+
+	gpiochip_add(&mvchip->chip);
+
+	/* Setup the interrupt handlers. Each chip can have up to 4
+	 * interrupt handlers, with each handler dealing with 8 GPIO
+	 * pins. */
+	for (i = 0; i < 4; i++) {
+		int irq;
+		irq = platform_get_irq(pdev, i);
+		if (irq < 0)
+			continue;
+		irq_set_handler_data(irq, mvchip);
+		irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
+	}
+
+	irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
+	if (irqbase < 0) {
+		dev_err(&pdev->dev, "no irqs\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
+				    mvchip->membase, handle_level_irq);
+	if (! gc) {
+		dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc->private = mvchip;
+	ct = &gc->chip_types[0];
+	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->chip.name = mvchip->chip.label;
+
+	ct = &gc->chip_types[1];
+	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+	ct->chip.irq_ack = mvebu_gpio_irq_ack;
+	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->handler = handle_edge_irq;
+	ct->chip.name = mvchip->chip.label;
+
+	irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+	/* Setup irq domain on top of the generic chip. */
+	mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
+					       mvchip->irqbase, 0,
+					       &irq_domain_simple_ops,
+					       mvchip);
+	if (!mvchip->domain) {
+		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
+			mvchip->chip.label);
+		irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
+					IRQ_LEVEL | IRQ_NOPROBE);
+		kfree(gc);
+		kfree(mvchip->chip.label);
+		return -ENODEV;
+	}
+
+	mvebu_gpio_chip_count++;
+
+	return 0;
+}
+
+static struct platform_driver mvebu_gpio_driver = {
+	.driver		= {
+		.name	        = "mvebu-gpio",
+		.owner	        = THIS_MODULE,
+		.of_match_table = mvebu_gpio_of_match,
+	},
+	.probe		= mvebu_gpio_probe,
+	.id_table	= mvebu_gpio_ids,
+};
+
+static int __init mvebu_gpio_init(void)
+{
+	return platform_driver_register(&mvebu_gpio_driver);
+}
+postcore_initcall(mvebu_gpio_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:43 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:43 +0200
Subject: [PATCH 2/5] Documentation: add description of DT binding for the
 gpio-mvebu driver
In-Reply-To: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 .../devicetree/bindings/gpio/gpio-mvebu.txt        |   44 ++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 0000000..298436c
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,44 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
+  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
+  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
+  370. "marvell,mv78200-gpio" should be used for the Discovery
+  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
+  SoCs (MV78230, MV78260, MV78460).
+
+- reg: Address and length of the register set for the device. Only one
+  entry is expected, except for the "marvell,armadaxp-gpio" variant
+  for which two entries are expected: one for the general registers,
+  one for the per-cpu registers.
+
+- interrupts: The list of interrupts that are used for all the pins
+  managed by this GPIO bank. There can be more than one interrupt
+  (example: 1 interrupt per 8 pins on Armada XP, which means 4
+  interrupts per bank of 32 GPIOs).
+
+- interrupt-controller: identifies the node as an interrupt controller
+
+- #interrupt-cells: specifies the number of celles needed to encode an
+   interrupt source
+
+- gpio-controller: marks the device node as a gpio controller
+
+- ngpios: number of GPIOs this controller has
+
+- #gpio-cells: Should be one. It is the pin number.
+
+Example:
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:44 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:44 +0200
Subject: [PATCH 3/5] arm: mvebu: use GPIO support now that a driver is
 available
In-Reply-To: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344691906-15985-4-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig                        |    1 +
 arch/arm/mach-mvebu/include/mach/gpio.h |    1 +
 2 files changed, 2 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95317a9..15b224c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PINCTRL
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	help
 	  Support for the Marvell SoC Family with device tree support
 
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:45 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:45 +0200
Subject: [PATCH 4/5] arm: mvebu: add DT information for GPIO banks on Armada
 370 and XP
In-Reply-To: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344691906-15985-5-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/armada-370.dtsi        |   30 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   22 ++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   33 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   33 ++++++++++++++++++++++++++++++
 4 files changed, 118 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 875fcd8..b0c832c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -35,5 +35,35 @@
                 pinctrl at d0018000 {
 			        compatible = "marvell,mv88f6710-pinctrl";
 	        };
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018100 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <82>, <83>, <84>, <85>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018140 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <87>, <88>, <89>, <90>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018180 0x40>;
+			ngpios = <2>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <91>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 69ad287..081f3f7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -23,5 +23,27 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78230-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <17>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 0f38fa9..fa791fa 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -23,5 +23,38 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78260-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 9e61836..a372d13 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -23,5 +23,38 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78460-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
  };
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 09:31:46 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 15:31:46 +0200
Subject: [PATCH 5/5] arm: mvebu: add gpio support in defconfig
In-Reply-To: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344691906-15985-6-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/configs/mvebu_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index cb07e64..8dbb0bf 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -23,6 +23,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_PINCTRL_ARMADA_370=y
 CONFIG_PINCTRL_ARMADA_XP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-- 
1.7.9.5



From cyril at ti.com  Sat Aug 11 09:37:54 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 11 Aug 2012 09:37:54 -0400
Subject: [PATCH v2 1/2] ARM: arch_timers: enable the use of the virtual
 timer
In-Reply-To: <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>
References: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
 <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <50266032.9070702@ti.com>

Marc,

On 8/11/2012 6:31 AM, Marc Zyngier wrote:
> At the moment, the arch_timer driver only uses the physical timer,
> which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
> which is likely in a virtualized environment. Instead, the virtual
> timer is always available.
>
> This patch enables the use of both the virtual timer, unless no
> interrupt is provided in the DT for it, in which case is falls
> back to the physical timer.
>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
>   arch/arm/kernel/arch_timer.c |  261 +++++++++++++++++++++++++++++++----------
>   1 files changed, 197 insertions(+), 64 deletions(-)
>
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index cf25880..4a64733 100644
[...]
> +	if (arch_timer_use_virtual) {
> +		ppi = arch_timer_ppi[VIRT_PPI];
> +		err = request_percpu_irq(ppi, arch_timer_handler,
> +					 "arch_timer", arch_timer_evt);
> +	} else {
> +		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
> +		err = request_percpu_irq(ppi, arch_timer_handler,
> +					 "arch_timer", arch_timer_evt);
> +		if (!err) {
> +			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
> +			err = request_percpu_irq(ppi, arch_timer_handler,
> +						 "arch_timer", arch_timer_evt);
> +			if (err)
> +				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
> +						arch_timer_evt);
> +		}
> +	}
> +
>   	if (err) {
>   		pr_err("arch_timer: can't register interrupt %d (%d)\n",
> -		       arch_timer_ppi, err);
> +		       ppi, err);
>   		goto out_free;
>   	}
>
> -	if (arch_timer_ppi2) {
> -		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
> -					 "arch_timer", arch_timer_evt);
> -		if (err) {
> -			pr_err("arch_timer: can't register interrupt %d (%d)\n",
> -			       arch_timer_ppi2, err);
> -			arch_timer_ppi2 = 0;
> -			goto out_free_irq;
> -		}
> -	}
> -

In the original code, arch_timer_ppi2 appears to have been entirely 
optional.

With this change, the code appears to mandate that both nonsecure and 
secure PPIs be available (if !arch_timer_use_virtual).  Could you please 
explain this change?

-- 
Thanks
- Cyril


From shijie8 at gmail.com  Sat Aug 11 09:56:37 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 09:56:37 -0400
Subject: [PATCH v3] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208111447.18076.marex@denx.de>
References: <1344700231-12624-1-git-send-email-shijie8@gmail.com>
 <201208110913.54479.marex@denx.de>
 <CAMiH66GbOYDpo-RDUct2nCixaf+9vhmT8Ouz+YPx95Z1+g2B1Q@mail.gmail.com>
 <201208111447.18076.marex@denx.de>
Message-ID: <CAMiH66E+a=8cxj5wFwNVHRJ5DReEVQ0uwr5MBmdM6HqThbrbOQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 8:47 AM, Marek Vasut <marex at denx.de> wrote:
> Dear Huang Shijie,
>
>> On Sat, Aug 11, 2012 at 3:13 PM, Marek Vasut <marex at denx.de> wrote:
>> > Dear Huang Shijie,
>> >
>> > Please re-add credit to Fabio. Also, Fabio fixed the subject to be more
>>
>> sorry. Should I add "Reported by : Fabio ...." to the patch?
>
> Yes, at least.
>
>> I really appriaciate Fabio's work, but I do not think Fabio's patch is
>> more accurate.
>> The nand chips can be 2K page, 4K page and 8K page. But most of the
>> time, the nand chip is 4K page.
>> If we fix the verify_buf to 8K size as Fabio's patch does. It will
>> waste much memory.
>> This is my concern now. :)
>
> That's all right, but the rest of your patch is Fabio's work, correct me if I'm

Frankly speaking, this patch was finished after I read your comments,
and before Fabio sent out his patch.
I did not send it out, just because i did not test it on the imx6q-arm2 board.

thanks

Huang Shijie


From shijie8 at gmail.com  Sat Aug 11 22:07:55 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 22:07:55 -0400
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
Message-ID: <1344737275-18342-1-git-send-email-shijie8@gmail.com>

Add NAND write verify support in gpmi-nand driver.

This patch fixes a kernel crash when we select
CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:

root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
[   41.070000] Unable to handle kernel NULL pointer dereference at virtual addr0
[   41.080000] pgd = c77ac000
[   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
[   41.090000] Internal error: Oops: 17 [#1] ARM
[   41.090000] Modules linked in:
[   41.090000] CPU: 0    Not tainted (3.6.0-rc1-next-20120809-00002-ga25d017-d)
[   41.090000] PC is at nand_verify_buf+0x18/0x5c
[   41.090000] LR is at nand_write_page+0xc0/0x140
[   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
[   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
[   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
[   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
[   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
[   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
[   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
[   41.090000] Stack: (0xc7779de4 to 0xc777a000)
	...

	The crash log is fetched from Fabio's patch. thanks to Fabio's hard work.

Cc: <stable at vger.kernel.org>
Reported-by: Fabio Estevam <fabio.estevam at freescale.com>
Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
v3 --> v4:
    [1] add credit to Fabio.

v2 --> v3:
    [1] free the verify_buf when we exit.

v1 --> v2:
    [1] use the mtd->writesize to allocate the verify buffer.
    [2] add new field `verify_buf` in gpmi_nand_data{}

    tested this patch on imx6q-arm2 board.
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 8c0d2f0..e1e4c51 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data  *this)
 	return nand_boot_init(this);
 }
 
+static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct gpmi_nand_data *this = chip->priv;
+	int ret;
+
+	ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
+	if (ret)
+		return -EFAULT;
+	if (memcmp(buf, this->verify_buf, len))
+		return -EFAULT;
+	return 0;
+}
+
 static int gpmi_scan_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct gpmi_nand_data *this = chip->priv;
 	int ret;
 
+	/*
+	 * We have gotten the right page size now, use it to allocate
+	 * the proper verify buffer.
+	 */
+	this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
+	if (!this->verify_buf)
+		return -ENOMEM;
+
 	/* Prepare for the BBT scan. */
 	ret = gpmi_pre_bbt_scan(this);
 	if (ret)
@@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
 {
 	nand_release(&this->mtd);
 	gpmi_free_dma_buffer(this);
+	kfree(this->verify_buf);
+	this->verify_buf = NULL;
 }
 
 static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
@@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
 	chip->read_byte		= gpmi_read_byte;
 	chip->read_buf		= gpmi_read_buf;
 	chip->write_buf		= gpmi_write_buf;
+	chip->verify_buf	= gpmi_verify_buf;
 	chip->ecc.read_page	= gpmi_ecc_read_page;
 	chip->ecc.write_page	= gpmi_ecc_write_page;
 	chip->ecc.read_oob	= gpmi_ecc_read_oob;
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 1547a60..8ddf115 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -144,6 +144,7 @@ struct gpmi_nand_data {
 	/* MTD / NAND */
 	struct nand_chip	nand;
 	struct mtd_info		mtd;
+	uint8_t			*verify_buf;
 
 	/* General-use Variables */
 	int			current_chip;
-- 
1.7.4.4



From marex at denx.de  Sat Aug 11 10:10:44 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 11 Aug 2012 16:10:44 +0200
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
References: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
Message-ID: <201208111610.45107.marex@denx.de>

Dear Huang Shijie,

> Add NAND write verify support in gpmi-nand driver.
> 
> This patch fixes a kernel crash when we select
> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
> 
> root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
> [   41.070000] Unable to handle kernel NULL pointer dereference at virtual
> addr0 [   41.080000] pgd = c77ac000
> [   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
> [   41.090000] Internal error: Oops: 17 [#1] ARM
> [   41.090000] Modules linked in:
> [   41.090000] CPU: 0    Not tainted
> (3.6.0-rc1-next-20120809-00002-ga25d017-d) [   41.090000] PC is at
> nand_verify_buf+0x18/0x5c
> [   41.090000] LR is at nand_write_page+0xc0/0x140
> [   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
> [   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
> [   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
> [   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
> [   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
> [   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment
> user [   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
> [   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
> [   41.090000] Stack: (0xc7779de4 to 0xc777a000)
> 	...
> 
> 	The crash log is fetched from Fabio's patch. thanks to Fabio's hard 
work.
> 
> Cc: <stable at vger.kernel.org>
> Reported-by: Fabio Estevam <fabio.estevam at freescale.com>
> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
> ---
> v3 --> v4:
>     [1] add credit to Fabio.
> 
> v2 --> v3:
>     [1] free the verify_buf when we exit.
> 
> v1 --> v2:
>     [1] use the mtd->writesize to allocate the verify buffer.
>     [2] add new field `verify_buf` in gpmi_nand_data{}
> 
>     tested this patch on imx6q-arm2 board.
> ---
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
>  2 files changed, 26 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..e1e4c51 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data 
> *this) return nand_boot_init(this);
>  }
> 
> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
> len) +{
> +	struct nand_chip *chip = mtd->priv;
> +	struct gpmi_nand_data *this = chip->priv;
> +	int ret;
> +
> +	ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
> +	if (ret)
> +		return -EFAULT;
> +	if (memcmp(buf, this->verify_buf, len))
> +		return -EFAULT;
> +	return 0;
> +}
> +
>  static int gpmi_scan_bbt(struct mtd_info *mtd)
>  {
>  	struct nand_chip *chip = mtd->priv;
>  	struct gpmi_nand_data *this = chip->priv;
>  	int ret;
> 
> +	/*
> +	 * We have gotten the right page size now, use it to allocate
> +	 * the proper verify buffer.
> +	 */
> +	this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);

devm_

> +	if (!this->verify_buf)
> +		return -ENOMEM;
> +
>  	/* Prepare for the BBT scan. */
>  	ret = gpmi_pre_bbt_scan(this);
>  	if (ret)
> @@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
>  {
>  	nand_release(&this->mtd);
>  	gpmi_free_dma_buffer(this);
> +	kfree(this->verify_buf);
> +	this->verify_buf = NULL;

Then you won't have to care for this ... I told you at least once before.

>  }
> 
>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
> @@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct
> gpmi_nand_data *this) chip->read_byte		= gpmi_read_byte;
>  	chip->read_buf		= gpmi_read_buf;
>  	chip->write_buf		= gpmi_write_buf;
> +	chip->verify_buf	= gpmi_verify_buf;
>  	chip->ecc.read_page	= gpmi_ecc_read_page;
>  	chip->ecc.write_page	= gpmi_ecc_write_page;
>  	chip->ecc.read_oob	= gpmi_ecc_read_oob;
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60..8ddf115 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
>  	/* MTD / NAND */
>  	struct nand_chip	nand;
>  	struct mtd_info		mtd;
> +	uint8_t			*verify_buf;
> 
>  	/* General-use Variables */
>  	int			current_chip;


From bryan.wu at canonical.com  Sat Aug 11 10:23:20 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Sat, 11 Aug 2012 22:23:20 +0800
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <20120811080429.GA18957@n2100.arm.linux.org.uk>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
 <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
 <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>
 <CAK5ve-+hFRkbZ1bmfKodzjZEyP8vTyxZzU96LnhYjp1Vn7OWcw@mail.gmail.com>
 <20120811080429.GA18957@n2100.arm.linux.org.uk>
Message-ID: <CAK5ve-LX_q154+BYxzns38yAZ9BcLxsA26negXo9K4XMNxcrWA@mail.gmail.com>

On Sat, Aug 11, 2012 at 4:04 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Sat, Aug 11, 2012 at 02:57:18PM +0800, Bryan Wu wrote:
>> On Wed, Aug 1, 2012 at 1:10 PM, Olof Johansson <olof at lixom.net> wrote:
>> > On Tue, Jul 31, 2012 at 9:59 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> >> On Wed, Aug 1, 2012 at 12:55 PM, Olof Johansson <olof at lixom.net> wrote:
>> >>> On Tue, Jul 31, 2012 at 9:48 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> >>>> On Tue, Jul 31, 2012 at 9:46 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> >>>>> Russell, Arnd and Olof,
>> >>>>>
>> >>>>
>> >>>> I felt very sorry about this issue, the email was archived
>> >>>> automatically in my Gmail account. I found the root cause of the issue
>> >>>> Russell met and actually that code about trigger_data is totally
>> >>>> useless, which was removed just now. I pushed an update version again
>> >>>> to the same branch of my git tree. Please consider a pull. If I did
>> >>>> something bad, please let me know, I will fix it as soon as possible.
>> >>>
>> >>> Hi,
>> >>>
>> >>> We'll pull this in for staging again once the merge window is done.
>> >>> It's definitely not 3.6 material at this time.
>> >>>
>> >>
>> >> OK, I will rebase to 3.6-rc1 after merge window close and send out
>> >> pull request again.
>> >
>> > No need to rebase unless there are large merge conflicts.
>> >
>>
>> Olof, could you please consider pull again this branch? I keep it
>> based on 3.5 release.
>
> So what's the fix you've applied?  I don't think you've posted any patches.

I assume I need update my branch instead of posting some incremental
patches, since my branch was dropped. So I prepared a new branch
including the fixing.

Need I post my fix? But I don't keep the old version.
Olof and Arnd, maybe you guys keep my old version.

Thanks,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer    +86.186-168-78255 Mobile
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From cyril at ti.com  Sat Aug 11 10:28:51 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 11 Aug 2012 10:28:51 -0400
Subject: [PATCH v2 1/2] ARM: arch_timers: enable the use of the virtual
 timer
In-Reply-To: <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>
References: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
 <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <50266C23.7040802@ti.com>

On 8/11/2012 6:31 AM, Marc Zyngier wrote:
> At the moment, the arch_timer driver only uses the physical timer,
> which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
> which is likely in a virtualized environment. Instead, the virtual
> timer is always available.
>
> This patch enables the use of both the virtual timer, unless no
> interrupt is provided in the DT for it, in which case is falls
> back to the physical timer.
>

I'm curious about the cost of the added pointer chasing introduced by 
this patch.

The original code gets nicely inlined by the compiler, and this hides 
all the switch-case register index stuff.  For instance:

  10797 c001288c <arch_timer_set_next_event>:
  10798 c001288c:       ee1e3f32        mrc     15, 0, r3, cr14, cr2, {1}
  10799 c0012890:       e3c33002        bic     r3, r3, #2
  10800 c0012894:       ee0e0f12        mcr     15, 0, r0, cr14, cr2, {0}
  10801 c0012898:       f57ff06f        isb     sy
  10802 c001289c:       e3833001        orr     r3, r3, #1
  10803 c00128a0:       ee0e3f32        mcr     15, 0, r3, cr14, cr2, {1}
  10804 c00128a4:       f57ff06f        isb     sy
  10805 c00128a8:       e3a00000        mov     r0, #0
  10806 c00128ac:       e12fff1e        bx      lr

With the added pointer chasing, we unfortunately lose out on all the 
work that the compiler used to do for us.  We now end up having to snake 
our way through the following:

  10852 c0012958 <arch_timer_set_next_event>:
  10853 c0012958:       e92d4070        push    {r4, r5, r6, lr}
  10854 c001295c:       e3054400        movw    r4, #21504      ; 0x5400
  10855 c0012960:       e34c401f        movt    r4, #49183      ; 0xc01f
  10856 c0012964:       e1a06000        mov     r6, r0
  10857 c0012968:       e3a00000        mov     r0, #0
  10858 c001296c:       e5943000        ldr     r3, [r4]
  10859 c0012970:       e5933004        ldr     r3, [r3, #4]
  10860 c0012974:       e12fff33        blx     r3
  10861 c0012978:       e5943000        ldr     r3, [r4]
  10862 c001297c:       e3c05002        bic     r5, r0, #2
  10863 c0012980:       e1a01006        mov     r1, r6
  10864 c0012984:       e3a00002        mov     r0, #2
  10865 c0012988:       e5933000        ldr     r3, [r3]
  10866 c001298c:       e12fff33        blx     r3
  10867 c0012990:       e5943000        ldr     r3, [r4]
  10868 c0012994:       e3851001        orr     r1, r5, #1
  10869 c0012998:       e3a00000        mov     r0, #0
  10870 c001299c:       e5933000        ldr     r3, [r3]
  10871 c00129a0:       e12fff33        blx     r3
  10872 c00129a4:       e3a00000        mov     r0, #0
  10873 c00129a8:       e8bd8070        pop     {r4, r5, r6, pc}

  10908 c0012a18 <arch_timer_phys_reg_read>:
  10909 c0012a18:       e3500000        cmp     r0, #0
  10910 c0012a1c:       e92d4008        push    {r3, lr}
  10911 c0012a20:       1a000001        bne     c0012a2c
  10912 c0012a24:       ee1e0f32        mrc     15, 0, r0, cr14, cr2, {1}
  10913 c0012a28:       e8bd8008        pop     {r3, pc}
  10914 c0012a2c:       e3500002        cmp     r0, #2
  10915 c0012a30:       0a000002        beq     c0012a40
  10916 c0012a34:       e3500001        cmp     r0, #1
  10917 c0012a38:       0a000002        beq     c0012a48
  10918 c0012a3c:       eb053afb        bl      c0161630
  10919 c0012a40:       ee1e0f12        mrc     15, 0, r0, cr14, cr2, {0}
  10920 c0012a44:       e8bd8008        pop     {r3, pc}
  10921 c0012a48:       ee1e0f10        mrc     15, 0, r0, cr14, cr0, {0}
  10922 c0012a4c:       e8bd8008        pop     {r3, pc}

  10768 c0012840 <arch_timer_phys_reg_write>:
  10769 c0012840:       e3500000        cmp     r0, #0
  10770 c0012844:       1a000002        bne     c0012854
  10771 c0012848:       ee0e1f32        mcr     15, 0, r1, cr14, cr2, {1}
  10772 c001284c:       f57ff06f        isb     sy
  10773 c0012850:       e12fff1e        bx      lr
  10774 c0012854:       e3500002        cmp     r0, #2
  10775 c0012858:       1afffffb        bne     c001284c
  10776 c001285c:       ee0e1f12        mcr     15, 0, r1, cr14, cr2, {0}
  10777 c0012860:       f57ff06f        isb     sy
  10778 c0012864:       e12fff1e        bx      lr


I think we'd be better off separating between these (virt, phys, ...) 
implementations at a higher level of operations (set_mode, 
set_next_event, ...) rather than separating at a register operations 
level as you have in this patch.

-- 
Thanks
- Cyril


From ming.lei at canonical.com  Sat Aug 11 11:09:51 2012
From: ming.lei at canonical.com (Ming Lei)
Date: Sat, 11 Aug 2012 23:09:51 +0800
Subject: [PATCH 1/9] ARM: PMU: Add runtime PM Support
In-Reply-To: <1344620195-22372-2-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-2-git-send-email-will.deacon@arm.com>
Message-ID: <CACVXFVMg5Acx4_KGT5jn1JgO3JsXAjZzU8virR=B3+pBrT4o_A@mail.gmail.com>

On Sat, Aug 11, 2012 at 1:36 AM, Will Deacon <will.deacon at arm.com> wrote:
> From: Jon Hunter <jon-hunter at ti.com>
>
> Add runtime PM support to the ARM PMU driver so that devices such as OMAP
> supporting dynamic PM can use the platform->runtime_* hooks to initialise
> hardware at runtime. Without having these runtime PM hooks in place any
> configuration of the PMU hardware would be lost when low power states are
> entered and hence would prevent PMU from working.
>
> This change also replaces the PMU platform functions enable_irq and disable_irq
> added by Ming Lei with runtime_resume and runtime_suspend funtions. Ming had
> added the enable_irq and disable_irq functions as a method to configure the
> cross trigger interface on OMAP4 for routing the PMU interrupts. By adding
> runtime PM support, we can move the code called by enable_irq and disable_irq
> into the runtime PM callbacks runtime_resume and runtime_suspend.
>
> Cc: Ming Lei <ming.lei at canonical.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/include/asm/pmu.h   |   20 ++++++++++++--------
>  arch/arm/kernel/perf_event.c |   41 +++++++++++++++++++++++++++++++++--------
>  2 files changed, 45 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
> index 4432305..40d7dff 100644
> --- a/arch/arm/include/asm/pmu.h
> +++ b/arch/arm/include/asm/pmu.h
> @@ -31,18 +31,22 @@ enum arm_pmu_type {
>   *     interrupt and passed the address of the low level handler,
>   *     and can be used to implement any platform specific handling
>   *     before or after calling it.
> - * @enable_irq: an optional handler which will be called after
> - *     request_irq and be used to handle some platform specific
> - *     irq enablement
> - * @disable_irq: an optional handler which will be called before
> - *     free_irq and be used to handle some platform specific
> - *     irq disablement
> + * @runtime_resume: an optional handler which will be called by the
> + *     runtime PM framework following a call to pm_runtime_get().
> + *     Note that if pm_runtime_get() is called more than once in
> + *     succession this handler will only be called once.
> + * @runtime_suspend: an optional handler which will be called by the
> + *     runtime PM framework following a call to pm_runtime_put().
> + *     Note that if pm_runtime_get() is called more than once in
> + *     succession this handler will only be called following the
> + *     final call to pm_runtime_put() that actually disables the
> + *     hardware.
>   */
>  struct arm_pmu_platdata {
>         irqreturn_t (*handle_irq)(int irq, void *dev,
>                                   irq_handler_t pmu_handler);
> -       void (*enable_irq)(int irq);
> -       void (*disable_irq)(int irq);
> +       int (*runtime_resume)(struct device *dev);
> +       int (*runtime_suspend)(struct device *dev);
>  };
>
>  #ifdef CONFIG_CPU_HAS_PMU
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index ab243b8..c44647e 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -20,6 +20,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/spinlock.h>
>  #include <linux/uaccess.h>
> +#include <linux/pm_runtime.h>
>
>  #include <asm/cputype.h>
>  #include <asm/irq.h>
> @@ -364,8 +365,6 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
>  {
>         int i, irq, irqs;
>         struct platform_device *pmu_device = armpmu->plat_device;
> -       struct arm_pmu_platdata *plat =
> -               dev_get_platdata(&pmu_device->dev);
>
>         irqs = min(pmu_device->num_resources, num_possible_cpus());
>
> @@ -373,13 +372,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
>                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
>                         continue;
>                 irq = platform_get_irq(pmu_device, i);
> -               if (irq >= 0) {
> -                       if (plat && plat->disable_irq)
> -                               plat->disable_irq(irq);
> +               if (irq >= 0)
>                         free_irq(irq, armpmu);
> -               }
>         }
>
> +       pm_runtime_put_sync(&pmu_device->dev);

One question, each pmu is just inside one cpu core and should be
suspended individually, but looks the above don't support it, do it?

>         release_pmu(armpmu->type);
>  }
>
> @@ -412,6 +409,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
>                 return -ENODEV;
>         }
>
> +       pm_runtime_get_sync(&pmu_device->dev);

Similar with above.


Thanks,
--
Ming Lei


From shijie8 at gmail.com  Sat Aug 11 11:15:49 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 11 Aug 2012 11:15:49 -0400
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208111610.45107.marex@denx.de>
References: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
 <201208111610.45107.marex@denx.de>
Message-ID: <CAMiH66GopNVeKPRQn+KfwRHUoM-Lv8WitX0zAS=Vi=8QAvS-Pw@mail.gmail.com>

On Sat, Aug 11, 2012 at 10:10 AM, Marek Vasut <marex at denx.de> wrote:
> Dear Huang Shijie,
>
>> Add NAND write verify support in gpmi-nand driver.
>>
>> This patch fixes a kernel crash when we select
>> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
>>
>> root at freescale /$ dd if=/dev/zero of=/dev/mtd0 bs=128k count=1
>> [   41.070000] Unable to handle kernel NULL pointer dereference at virtual
>> addr0 [   41.080000] pgd = c77ac000
>> [   41.080000] [00000000] *pgd=4773c831, *pte=00000000, *ppte=00000000
>> [   41.090000] Internal error: Oops: 17 [#1] ARM
>> [   41.090000] Modules linked in:
>> [   41.090000] CPU: 0    Not tainted
>> (3.6.0-rc1-next-20120809-00002-ga25d017-d) [   41.090000] PC is at
>> nand_verify_buf+0x18/0x5c
>> [   41.090000] LR is at nand_write_page+0xc0/0x140
>> [   41.090000] pc : [<c023e7d4>]    lr : [<c023fcfc>]    psr: 20000013
>> [   41.090000] sp : c7779de4  ip : 00000000  fp : c6e60000
>> [   41.090000] r10: 00000000  r9 : 00020000  r8 : 00000000
>> [   41.090000] r7 : 00000000  r6 : c6e60000  r5 : c762cb10  r4 : 00000000
>> [   41.090000] r3 : c762c8a8  r2 : 00000800  r1 : c6e60000  r0 : 00000000
>> [   41.090000] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment
>> user [   41.090000] Control: 0005317f  Table: 477ac000  DAC: 00000015
>> [   41.090000] Process dd (pid: 427, stack limit = 0xc7778270)
>> [   41.090000] Stack: (0xc7779de4 to 0xc777a000)
>>       ...
>>
>>       The crash log is fetched from Fabio's patch. thanks to Fabio's hard
> work.
>>
>> Cc: <stable at vger.kernel.org>
>> Reported-by: Fabio Estevam <fabio.estevam at freescale.com>
>> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
>> ---
>> v3 --> v4:
>>     [1] add credit to Fabio.
>>
>> v2 --> v3:
>>     [1] free the verify_buf when we exit.
>>
>> v1 --> v2:
>>     [1] use the mtd->writesize to allocate the verify buffer.
>>     [2] add new field `verify_buf` in gpmi_nand_data{}
>>
>>     tested this patch on imx6q-arm2 board.
>> ---
>>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   25 +++++++++++++++++++++++++
>>  drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
>>  2 files changed, 26 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 8c0d2f0..e1e4c51 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> @@ -1512,12 +1512,34 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data
>> *this) return nand_boot_init(this);
>>  }
>>
>> +static int gpmi_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int
>> len) +{
>> +     struct nand_chip *chip = mtd->priv;
>> +     struct gpmi_nand_data *this = chip->priv;
>> +     int ret;
>> +
>> +     ret = chip->ecc.read_page(mtd, chip, this->verify_buf, 0, 0);
>> +     if (ret)
>> +             return -EFAULT;
>> +     if (memcmp(buf, this->verify_buf, len))
>> +             return -EFAULT;
>> +     return 0;
>> +}
>> +
>>  static int gpmi_scan_bbt(struct mtd_info *mtd)
>>  {
>>       struct nand_chip *chip = mtd->priv;
>>       struct gpmi_nand_data *this = chip->priv;
>>       int ret;
>>
>> +     /*
>> +      * We have gotten the right page size now, use it to allocate
>> +      * the proper verify buffer.
>> +      */
>> +     this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
>
> devm_

emm...
The devm_kzalloc() is the wrong choose in this case. It may makes we
waste much more memory when the NAND page is 8K.

Assume the gpmi uses a 8K page nand chip.  The devm_kzalloc() will
allocate (sizeof(struct devres) + 8K).
It's obvious that the size is bigger then the SLUB_MAX_SIZE. So the
kernel gets 2 with the
get_order(sizeof(struct devres) + 8K) which means we have to use 4
memory page for the verify_buf.
But in actually, we only use 8K memory. So the rest nearly 8K(
sizeof(struct devres) is very small) memory
is wasted.

So I prefer to use the kzalloc() here.

thanks
Huang Shijie



>
>> +     if (!this->verify_buf)
>> +             return -ENOMEM;
>> +
>>       /* Prepare for the BBT scan. */
>>       ret = gpmi_pre_bbt_scan(this);
>>       if (ret)
>> @@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
>>  {
>>       nand_release(&this->mtd);
>>       gpmi_free_dma_buffer(this);
>> +     kfree(this->verify_buf);
>> +     this->verify_buf = NULL;
>
> Then you won't have to care for this ... I told you at least once before.
>
>>  }
>>
>>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
>> @@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct
>> gpmi_nand_data *this) chip->read_byte         = gpmi_read_byte;
>>       chip->read_buf          = gpmi_read_buf;
>>       chip->write_buf         = gpmi_write_buf;
>> +     chip->verify_buf        = gpmi_verify_buf;
>>       chip->ecc.read_page     = gpmi_ecc_read_page;
>>       chip->ecc.write_page    = gpmi_ecc_write_page;
>>       chip->ecc.read_oob      = gpmi_ecc_read_oob;
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60..8ddf115 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
>>       /* MTD / NAND */
>>       struct nand_chip        nand;
>>       struct mtd_info         mtd;
>> +     uint8_t                 *verify_buf;
>>
>>       /* General-use Variables */
>>       int                     current_chip;


From jason at lakedaemon.net  Sat Aug 11 12:36:37 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 12:36:37 -0400
Subject: [PATCH 2/3] ARM: Kirkwood: ts219: fix Makefile.boot after dts
 was split in two
In-Reply-To: <20120811075114.GD30947@lunn.ch>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <4b59ab4618c9b9c055831f6b96636741bda5d42f.1344651264.git.jason@lakedaemon.net>
 <20120811075114.GD30947@lunn.ch>
Message-ID: <20120811163637.GD22226@titan.lakedaemon.net>

On Sat, Aug 11, 2012 at 09:51:14AM +0200, Andrew Lunn wrote:
> On Sat, Aug 11, 2012 at 02:39:46AM +0000, Jason Cooper wrote:
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/mach-kirkwood/Makefile.boot |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> > index 2a576ab..2ad83e2 100644
> > --- a/arch/arm/mach-kirkwood/Makefile.boot
> > +++ b/arch/arm/mach-kirkwood/Makefile.boot
> > @@ -7,7 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
> >  dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
> >  dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
> >  dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
> > -dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
> > +dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6281.dtb kirkwood-ts219-6282.dtb
> 
> Hi Jason
> 
> There is the same fix from Arnaud Patard, which has been posted to the
> list maybe a week ago.

dabbit!  I even have that flagged to pull in as a 3.6 fix.  I'll drop
mine, and use his.

> We seem quite good at breaking Makefile.boot and not noticing it. Who
> maintains kisskb? We should ask for make dtbs to be added to the end
> of the build scripts.

I have it in my build tests here (that's how it came up), but we'll see
if they are ammenable to adding 'make dtbs'.

thx,

Jason.


From jason at lakedaemon.net  Sat Aug 11 12:47:45 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 12:47:45 -0400
Subject: [PATCH 3/3] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <20120811062111.GA30947@lunn.ch>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
 <20120811062111.GA30947@lunn.ch>
Message-ID: <20120811164745.GE22226@titan.lakedaemon.net>

On Sat, Aug 11, 2012 at 08:21:11AM +0200, Andrew Lunn wrote:
> On Sat, Aug 11, 2012 at 02:39:47AM +0000, Jason Cooper wrote:
> > Also, disable DEBUG_KERNEL, enable SERIAL_OF_PLATFORM, and enable EMBEDDED
> 
> Why disable DEBUG_KERNEL. Most of the other defconfig files have it
> enabled.

I usually get burned on desktop kernels with ~90MB initrds filling up my
/boot partition, so I'm in the habit of disabling it.  It appears the
convention is to enable it for defconfigs (86 of 129 in v3.6-rc1), so
I'll re-enable it.

> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/configs/kirkwood_defconfig |   12 +++++++++++-
> >  1 files changed, 11 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
> > index 5a494a3..0865d2e 100644
> > --- a/arch/arm/configs/kirkwood_defconfig
> > +++ b/arch/arm/configs/kirkwood_defconfig
> > @@ -3,6 +3,9 @@ CONFIG_SYSVIPC=y
> >  CONFIG_NO_HZ=y
> >  CONFIG_HIGH_RES_TIMERS=y
> >  CONFIG_LOG_BUF_SHIFT=19
> > +CONFIG_NAMESPACES=y
> > +CONFIG_BLK_DEV_INITRD=y
> 
> Do we need these two as well? Namespaces seems a bit unusual for a
> tiny embedded device.

initrd is another thing I do out of habit.  I tend to use an initrd that
drops to a shell for testing.

I'll disable both.  Time for v2.

thx,

Jason.


From manabian at gmail.com  Sat Aug 11 13:06:18 2012
From: manabian at gmail.com (Joachim Eastwood)
Date: Sat, 11 Aug 2012 19:06:18 +0200
Subject: AT91 RM9200 hangs on delay loop calibration
Message-ID: <CAGhQ9Vyvr7bDU8cNirGuTkhsH1LhHPRjehftOwwSnox+i1b=5A@mail.gmail.com>

Hi,

My custom AT91 RM9200 board hangs on delay loop calibration. There it
seems to be stuck and the last message printed is:
[    0.000000] Calibrating delay loop...

Doing a manual bisect I can get the board to boot again when I revert
the following commits from Linus master:
14070ade02cc378bc30dae383532768a94805988 - ARM: at91: fix new build errors
c4b68520dc0ec96153bc0d87bca5ffba508edfcf - ARM: at91: add AIC5 support
4c6971a6debb340d487cf6189f15a1332702330f - ARM: at91: remove mach/irqs.h
8fe82a5550a8e97b3f59c74f994b88ed6b3544a3 - ARM: at91: sparse irq support
3e135466745a62b1814edef74c7b4a25e6bda707 - ARM: at91: at91 based
machines specify their own irq handler at run time

There may be some unnecessary reverts here but there are multiple
build failures between the different commits (grrrrr) which makes it
pain to filter it out.

I suspect that right now all AT91 RM9200 machines are broken by these
IRQ changes on AT91.

regards
Joachim Eastwood


From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:29 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:29 +0200
Subject: [v2] gpio: mvebu: new gpio driver for mvebu platforms
Message-ID: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

This patch set adds a new GPIO driver for Marvell EBU SoCs, which aims
at replacing the existing GPIO driver from plat-orion/gpio.c. The
driver comes with the necessary DT changes to make it work on Armada
370 and Armada XP, and it has been tested successfully by Sebastian
Hesselbarth on Dove. It should also work flawlessly on other Marvell
EBU SoCs (Kirkwood, Orion, Discovery), but this remains to be tested
by the relevant maintainers.

This new driver reuses a lot of code from the existing
plat-orion/gpio.c driver, but has a number of advantages:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only. This driver has been submitted by
    Sebastian Hesselbarth today on the LAKML.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

Changes since v1:
 * Added fixes for Dove from Sebastian Hesselbarth, and his Tested-by
   on the driver patch.

Thanks,

Thomas

The following changes since commit 872b6be95abf9d57e0639d0345fa2b5a0e4fa0f4:

  arm: mvebu: add pinctrl support in defconfig (2012-08-11 11:27:33 +0200)

are available in the git repository at:

  git://github.com/MISL-EBU-System-SW/mainline-public.git mvebu-gpio

for you to fetch changes up to c6347492639521d79e541a90fe2dfeec07d9b1a2:

  arm: mvebu: add gpio support in defconfig (2012-08-11 19:06:40 +0200)

----------------------------------------------------------------
Thomas Petazzoni (5):
      gpio: introduce gpio-mvebu driver for Marvell SoCs
      Documentation: add description of DT binding for the gpio-mvebu driver
      arm: mvebu: use GPIO support now that a driver is available
      arm: mvebu: add DT information for GPIO banks on Armada 370 and XP
      arm: mvebu: add gpio support in defconfig

 .../devicetree/bindings/gpio/gpio-mvebu.txt        |   44 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370.dtsi                  |   30 +
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   22 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   33 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   33 +
 arch/arm/configs/mvebu_defconfig                   |    2 +
 arch/arm/mach-mvebu/include/mach/gpio.h            |    1 +
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-mvebu.c                          |  656 ++++++++++++++++++++
 11 files changed, 829 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h
 create mode 100644 drivers/gpio/gpio-mvebu.c



From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:31 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:31 +0200
Subject: [PATCH 2/5] Documentation: add description of DT binding for the
 gpio-mvebu driver
In-Reply-To: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344705034-18173-3-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 .../devicetree/bindings/gpio/gpio-mvebu.txt        |   44 ++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 0000000..298436c
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,44 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
+  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
+  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
+  370. "marvell,mv78200-gpio" should be used for the Discovery
+  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
+  SoCs (MV78230, MV78260, MV78460).
+
+- reg: Address and length of the register set for the device. Only one
+  entry is expected, except for the "marvell,armadaxp-gpio" variant
+  for which two entries are expected: one for the general registers,
+  one for the per-cpu registers.
+
+- interrupts: The list of interrupts that are used for all the pins
+  managed by this GPIO bank. There can be more than one interrupt
+  (example: 1 interrupt per 8 pins on Armada XP, which means 4
+  interrupts per bank of 32 GPIOs).
+
+- interrupt-controller: identifies the node as an interrupt controller
+
+- #interrupt-cells: specifies the number of celles needed to encode an
+   interrupt source
+
+- gpio-controller: marks the device node as a gpio controller
+
+- ngpios: number of GPIOs this controller has
+
+- #gpio-cells: Should be one. It is the pin number.
+
+Example:
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:30 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:30 +0200
Subject: [PATCH 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs
In-Reply-To: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344705034-18173-2-git-send-email-thomas.petazzoni@free-electrons.com>

This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
and is designed to be compatible with all Marvell EBU SoCs: Orion,
Kirkwood, Dove, Armada 370/XP and Discovery.

It has been successfully tested on Dove and Armada XP at the moment.

Compared to the plat-orion driver, this new driver has the following
added benefits:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
 drivers/gpio/Kconfig      |    6 +
 drivers/gpio/Makefile     |    1 +
 drivers/gpio/gpio-mvebu.c |  656 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 663 insertions(+)
 create mode 100644 drivers/gpio/gpio-mvebu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..993b0c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -150,6 +150,12 @@ config GPIO_MSM_V2
 	  Qualcomm MSM chips.  Most of the pins on the MSM can be
 	  selected for GPIO, and are controlled by this driver.
 
+config GPIO_MVEBU
+	def_bool y
+	depends on ARCH_MVEBU
+	select GPIO_GENERIC
+	select GENERIC_IRQ_CHIP
+
 config GPIO_MXC
 	def_bool y
 	depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..1a33e67 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSIC)		+= gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)	+= gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2.o
+obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
 obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
new file mode 100644
index 0000000..892e3f1
--- /dev/null
+++ b/drivers/gpio/gpio-mvebu.c
@@ -0,0 +1,656 @@
+/*
+ * GPIO driver for Marvell SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ * Andrew Lunn <andrew at lunn.ch>
+ * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This driver is a fairly straightforward GPIO driver for the
+ * complete family of Marvell EBU SoC platforms (Orion, Dove,
+ * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
+ * driver is the different register layout that exists between the
+ * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
+ * platforms (MV78200 from the Discovery family and the Armada
+ * XP). Therefore, this driver handles three variants of the GPIO
+ * block:
+ * - the basic variant, called "orion-gpio", with the simplest
+ *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
+ *   non-SMP Discovery systems
+ * - the mv78200 variant for MV78200 Discovery systems. This variant
+ *   turns the edge mask and level mask registers into CPU0 edge
+ *   mask/level mask registers, and adds CPU1 edge mask/level mask
+ *   registers.
+ * - the armadaxp variant for Armada XP systems. This variant keeps
+ *   the normal cause/edge mask/level mask registers when the global
+ *   interrupts are used, but adds per-CPU cause/edge mask/level mask
+ *   registers n a separate memory area for the per-CPU GPIO
+ *   interrupts.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF		0x0000
+#define GPIO_IO_CONF_OFF	0x0004
+#define GPIO_BLINK_EN_OFF	0x0008
+#define GPIO_IN_POL_OFF		0x000c
+#define GPIO_DATA_IN_OFF	0x0010
+#define GPIO_EDGE_CAUSE_OFF	0x0014
+#define GPIO_EDGE_MASK_OFF	0x0018
+#define GPIO_LEVEL_MASK_OFF	0x001c
+
+/* The MV78200 has per-CPU registers for edge mask and level mask */
+#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
+#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
+
+/* The Armada XP has per-CPU registers for interrupt cause, interrupt
+ * mask and interrupt level mask. Those are relative to the
+ * percpu_membase. */
+#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
+#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
+#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
+
+#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
+#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
+#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+
+struct mvebu_gpio_chip {
+	struct gpio_chip   chip;
+	spinlock_t	   lock;
+	void __iomem	  *membase;
+	void __iomem	  *percpu_membase;
+	unsigned int       irqbase;
+	struct irq_domain *domain;
+	int                soc_variant;
+};
+
+/*
+ * Common functions to all SoCs
+ */
+static void __iomem *GPIO_OUT(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_OUT_OFF;
+}
+
+static void __iomem *GPIO_IO_CONF(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IO_CONF_OFF;
+}
+
+static void __iomem *GPIO_IN_POL(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_IN_POL_OFF;
+}
+
+static void __iomem *GPIO_DATA_IN(struct mvebu_gpio_chip *mvchip)
+{
+	return mvchip->membase + GPIO_DATA_IN_OFF;
+}
+
+static void __iomem *GPIO_EDGE_CAUSE(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static void __iomem *GPIO_EDGE_MASK(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_EDGE_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+static void __iomem *GPIO_LEVEL_MASK(struct mvebu_gpio_chip *mvchip)
+{
+	int cpu;
+
+	switch(mvchip->soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		return mvchip->membase + GPIO_LEVEL_MASK_OFF;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		cpu = smp_processor_id();
+		return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		cpu = smp_processor_id();
+		return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
+	default:
+		BUG();
+	}
+}
+
+int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+	return pinctrl_request_gpio(chip->base + pin);
+}
+
+void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
+{
+	pinctrl_free_gpio(chip->base + pin);
+}
+
+static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	u32 u;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_OUT(mvchip));
+	if (value)
+		u |= 1 << pin;
+	else
+		u &= ~(1 << pin);
+	writel(u, GPIO_OUT(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+}
+
+static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	u32 u;
+
+	if (readl(GPIO_IO_CONF(mvchip)) & (1 << pin)) {
+		u = readl(GPIO_DATA_IN(mvchip)) ^ readl(GPIO_IN_POL(mvchip));
+	} else {
+		u = readl(GPIO_OUT(mvchip));
+	}
+
+	return (u >> pin) & 1;
+}
+
+static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an input GPIO */
+	ret = pinctrl_gpio_direction_input(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_IO_CONF(mvchip));
+	u |= 1 << pin;
+	writel(u, GPIO_IO_CONF(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+				       int value)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	unsigned long flags;
+	int ret;
+	u32 u;
+
+	/* Check with the pinctrl driver whether this pin is usable as
+	 * an output GPIO */
+	ret = pinctrl_gpio_direction_output(chip->base + pin);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&mvchip->lock, flags);
+	u = readl(GPIO_IO_CONF(mvchip));
+	u &= ~(1 << pin);
+	writel(u, GPIO_IO_CONF(mvchip));
+	spin_unlock_irqrestore(&mvchip->lock, flags);
+
+	return 0;
+}
+
+static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+	struct mvebu_gpio_chip *mvchip =
+		container_of(chip, struct mvebu_gpio_chip, chip);
+	return irq_create_mapping(mvchip->domain, pin);
+}
+
+static void mvebu_gpio_irq_ack(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = ~(1 << (d->irq - gc->irq_base));
+
+	irq_gc_lock(gc);
+	writel(mask, GPIO_EDGE_CAUSE(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel(gc->mask_cache, GPIO_EDGE_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel(gc->mask_cache, GPIO_EDGE_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_mask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache &= ~mask;
+	writel(gc->mask_cache, GPIO_LEVEL_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	u32 mask = 1 << (d->irq - gc->irq_base);
+
+	irq_gc_lock(gc);
+	gc->mask_cache |= mask;
+	writel(gc->mask_cache, GPIO_LEVEL_MASK(mvchip));
+	irq_gc_unlock(gc);
+}
+
+/*****************************************************************************
+ * MVEBU GPIO IRQ
+ *
+ * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ *                     Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
+ *                     Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ *                     the polarity to catch the next line transaction.
+ *                     This is a race condition that might not perfectly
+ *                     work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ *                    EDGE  cause    mask
+ *        data-in   /--------| |-----| |----\
+ *     -----| |-----                         ---- to main cause reg
+ *           X      \----------------| |----/
+ *        polarity    LEVEL          mask
+ *
+ ****************************************************************************/
+
+static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+	struct irq_chip_type *ct = irq_data_get_chip_type(d);
+	struct mvebu_gpio_chip *mvchip = gc->private;
+	int pin;
+	u32 u;
+
+	pin = d->hwirq - mvchip->irqbase;
+
+	u = readl(GPIO_IO_CONF(mvchip)) & (1 << pin);
+	if (!u) {
+		return -EINVAL;
+	}
+
+	type &= IRQ_TYPE_SENSE_MASK;
+	if (type == IRQ_TYPE_NONE)
+		return -EINVAL;
+
+	/* Check if we need to change chip and handler */
+	if (!(ct->type & type))
+		if (irq_setup_alt_chip(d, type))
+			return -EINVAL;
+
+	/*
+	 * Configure interrupt polarity.
+	 */
+	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
+		u = readl(GPIO_IN_POL(mvchip));
+		u &= ~(1 << pin);
+		writel(u, GPIO_IN_POL(mvchip));
+	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
+		u = readl(GPIO_IN_POL(mvchip));
+		u |= 1 << pin;
+		writel(u, GPIO_IN_POL(mvchip));
+	} else if (type == IRQ_TYPE_EDGE_BOTH) {
+		u32 v;
+
+		v = readl(GPIO_IN_POL(mvchip)) ^ readl(GPIO_DATA_IN(mvchip));
+
+		/*
+		 * set initial polarity based on current input level
+		 */
+		u = readl(GPIO_IN_POL(mvchip));
+		if (v & (1 << pin))
+			u |= 1 << pin;		/* falling */
+		else
+			u &= ~(1 << pin);	/* rising */
+		writel(u, GPIO_IN_POL(mvchip));
+	}
+	return 0;
+}
+
+static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+	u32 cause, type;
+	int i;
+
+	if (mvchip == NULL)
+		return;
+
+	cause = readl(GPIO_DATA_IN(mvchip)) & readl(GPIO_LEVEL_MASK(mvchip));
+	cause |= readl(GPIO_EDGE_CAUSE(mvchip)) & readl(GPIO_EDGE_MASK(mvchip));
+
+	for (i = 0; i < mvchip->chip.ngpio; i++) {
+		int irq;
+
+		irq = mvchip->irqbase + i;
+
+		if (!(cause & (1 << i)))
+			continue;
+
+		type = irqd_get_trigger_type(irq_get_irq_data(irq));
+		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+			/* Swap polarity (race with GPIO line) */
+			u32 polarity;
+
+			polarity = readl(GPIO_IN_POL(mvchip));
+			polarity ^= 1 << i;
+			writel(polarity, GPIO_IN_POL(mvchip));
+		}
+		generic_handle_irq(irq);
+	}
+}
+
+static struct platform_device_id mvebu_gpio_ids[] = {
+	{
+		.name = "orion-gpio",
+	}, {
+		.name = "mv78200-gpio",
+	}, {
+		.name = "armadaxp-gpio",
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
+
+static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
+	{
+		.compatible = "marvell,orion-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
+	},
+	{
+		.compatible = "marvell,mv78200-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
+	},
+	{
+		.compatible = "marvell,armadaxp-gpio",
+		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
+	},
+	{
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
+
+static unsigned int mvebu_gpio_chip_count;
+
+static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
+{
+	struct mvebu_gpio_chip *mvchip;
+	const struct of_device_id *match;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *res;
+	struct irq_chip_generic *gc;
+	struct irq_chip_type *ct;
+	unsigned int ngpios;
+	int soc_variant;
+	int i, cpu;
+
+	match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
+	if (match)
+		soc_variant = (int) match->data;
+	else
+		soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (! res) {
+		dev_err(&pdev->dev, "Cannot get memory resource\n");
+		return -ENODEV;
+	}
+
+	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
+	if (! mvchip){
+		dev_err(&pdev->dev, "Cannot allocate memory\n");
+		return -ENOMEM;
+	}
+
+	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
+		dev_err(&pdev->dev, "Missing ngpios OF property\n");
+		return -ENODEV;
+	}
+
+	mvchip->soc_variant = soc_variant;
+	mvchip->chip.label = kasprintf(GFP_KERNEL, "mvebu-gpio%d", mvebu_gpio_chip_count);
+	mvchip->chip.dev = &pdev->dev;
+	mvchip->chip.request = mvebu_gpio_request;
+	mvchip->chip.direction_input = mvebu_gpio_direction_input;
+	mvchip->chip.get = mvebu_gpio_get;
+	mvchip->chip.direction_output = mvebu_gpio_direction_output;
+	mvchip->chip.set = mvebu_gpio_set;
+	mvchip->chip.to_irq = mvebu_gpio_to_irq;
+	mvchip->chip.base = mvebu_gpio_chip_count * 32;
+	mvchip->chip.ngpio = ngpios;
+	mvchip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+	mvchip->chip.of_node = np;
+#endif
+
+	spin_lock_init(&mvchip->lock);
+	mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
+	if (! mvchip->membase) {
+		dev_err(&pdev->dev, "Cannot ioremap\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	/* The Armada XP has a second range of registers for the
+	 * per-CPU registers */
+	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (! res) {
+			dev_err(&pdev->dev, "Cannot get memory resource\n");
+			kfree(mvchip->chip.label);
+			return -ENODEV;
+		}
+
+		mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
+		if (! mvchip->percpu_membase) {
+			dev_err(&pdev->dev, "Cannot ioremap\n");
+			kfree(mvchip->chip.label);
+			return -ENOMEM;
+		}
+	}
+
+	/*
+	 * Mask and clear GPIO interrupts.
+	 */
+	switch(soc_variant) {
+	case MVEBU_GPIO_SOC_VARIANT_ORION:
+		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_MV78200:
+		writel(0, GPIO_EDGE_CAUSE(mvchip));
+		for (cpu = 0; cpu < 2; cpu++) {
+			writel(0, mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu));
+			writel(0, mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu));
+		}
+		break;
+	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+		for (cpu = 0; cpu < 4; cpu++) {
+			writel(0, mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
+			writel(0, mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
+			writel(0, mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
+		}
+		break;
+	default:
+		BUG();
+	}
+
+	gpiochip_add(&mvchip->chip);
+
+	/* Some gpio controllers do not provide irq support */
+	if (!of_irq_count(np)) {
+		mvebu_gpio_chip_count++;
+		return 0;
+	}
+
+	/* Setup the interrupt handlers. Each chip can have up to 4
+	 * interrupt handlers, with each handler dealing with 8 GPIO
+	 * pins. */
+	for (i = 0; i < 4; i++) {
+		int irq;
+		irq = platform_get_irq(pdev, i);
+		if (irq < 0)
+			continue;
+		irq_set_handler_data(irq, mvchip);
+		irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
+	}
+
+	mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
+	if (mvchip->irqbase < 0) {
+		dev_err(&pdev->dev, "no irqs\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
+				    mvchip->membase, handle_level_irq);
+	if (! gc) {
+		dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
+		kfree(mvchip->chip.label);
+		return -ENOMEM;
+	}
+
+	gc->private = mvchip;
+	ct = &gc->chip_types[0];
+	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->chip.name = mvchip->chip.label;
+
+	ct = &gc->chip_types[1];
+	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+	ct->chip.irq_ack = mvebu_gpio_irq_ack;
+	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+	ct->handler = handle_edge_irq;
+	ct->chip.name = mvchip->chip.label;
+
+	irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+	/* Setup irq domain on top of the generic chip. */
+	mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
+					       mvchip->irqbase, 0,
+					       &irq_domain_simple_ops,
+					       mvchip);
+	if (!mvchip->domain) {
+		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
+			mvchip->chip.label);
+		irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
+					IRQ_LEVEL | IRQ_NOPROBE);
+		kfree(gc);
+		kfree(mvchip->chip.label);
+		return -ENODEV;
+	}
+
+	mvebu_gpio_chip_count++;
+
+	return 0;
+}
+
+static struct platform_driver mvebu_gpio_driver = {
+	.driver		= {
+		.name	        = "mvebu-gpio",
+		.owner	        = THIS_MODULE,
+		.of_match_table = mvebu_gpio_of_match,
+	},
+	.probe		= mvebu_gpio_probe,
+	.id_table	= mvebu_gpio_ids,
+};
+
+static int __init mvebu_gpio_init(void)
+{
+	return platform_driver_register(&mvebu_gpio_driver);
+}
+postcore_initcall(mvebu_gpio_init);
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:33 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:33 +0200
Subject: [PATCH 4/5] arm: mvebu: add DT information for GPIO banks on Armada
 370 and XP
In-Reply-To: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344705034-18173-5-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/boot/dts/armada-370.dtsi        |   30 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   22 ++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   33 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   33 ++++++++++++++++++++++++++++++
 4 files changed, 118 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 875fcd8..b0c832c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -35,5 +35,35 @@
                 pinctrl at d0018000 {
 			        compatible = "marvell,mv88f6710-pinctrl";
 	        };
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018100 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <82>, <83>, <84>, <85>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018140 0x40>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <87>, <88>, <89>, <90>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,orion-gpio";
+			reg = <0xd0018180 0x40>;
+			ngpios = <2>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <91>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 69ad287..081f3f7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -23,5 +23,27 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78230-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <17>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 0f38fa9..fa791fa 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -23,5 +23,38 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78260-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 9e61836..a372d13 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -23,5 +23,38 @@
 		pinctrl at d0018000 {
 			compatible = "marvell,mv78460-pinctrl";
 		};
+
+		gpio0: gpio at d0018100 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018100 0x40>,
+			    <0xd0018800 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <16>, <17>, <18>, <19>;
+		};
+
+		gpio1: gpio at d0018140 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018140 0x40>,
+			    <0xd0018840 0x30>;
+			ngpios = <32>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <20>, <21>, <22>, <23>;
+		};
+
+		gpio2: gpio at d0018180 {
+			compatible = "marvell,armadaxp-gpio";
+			reg = <0xd0018180 0x40>,
+			    <0xd0018870 0x30>;
+			ngpios = <3>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			interrupt-controller;
+			interrupts = <24>;
+		};
 	};
  };
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:32 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:32 +0200
Subject: [PATCH 3/5] arm: mvebu: use GPIO support now that a driver is
 available
In-Reply-To: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344705034-18173-4-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/Kconfig                        |    1 +
 arch/arm/mach-mvebu/include/mach/gpio.h |    1 +
 2 files changed, 2 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95317a9..15b224c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PINCTRL
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	help
 	  Support for the Marvell SoC Family with device tree support
 
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Sat Aug 11 13:10:34 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 11 Aug 2012 19:10:34 +0200
Subject: [PATCH 5/5] arm: mvebu: add gpio support in defconfig
In-Reply-To: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1344705034-18173-6-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory Clement <gregory.clement at free-electrons.com>
---
 arch/arm/configs/mvebu_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index cb07e64..8dbb0bf 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -23,6 +23,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_PINCTRL_ARMADA_370=y
 CONFIG_PINCTRL_ARMADA_XP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-- 
1.7.9.5



From andrew at lunn.ch  Sat Aug 11 18:06:45 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 12 Aug 2012 00:06:45 +0200
Subject: [PATCH 3/3] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
Message-ID: <20120811220645.GB2856@lunn.ch>

On Sat, Aug 11, 2012 at 02:39:47AM +0000, Jason Cooper wrote:
> Also, disable DEBUG_KERNEL, enable SERIAL_OF_PLATFORM, and enable EMBEDDED
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/configs/kirkwood_defconfig |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
> index 5a494a3..0865d2e 100644
> --- a/arch/arm/configs/kirkwood_defconfig
> +++ b/arch/arm/configs/kirkwood_defconfig
> @@ -3,6 +3,9 @@ CONFIG_SYSVIPC=y
>  CONFIG_NO_HZ=y
>  CONFIG_HIGH_RES_TIMERS=y
>  CONFIG_LOG_BUF_SHIFT=19
> +CONFIG_NAMESPACES=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_EMBEDDED=y
>  CONFIG_PROFILING=y
>  CONFIG_OPROFILE=y
>  CONFIG_KPROBES=y
> @@ -17,6 +20,13 @@ CONFIG_MACH_MV88F6281GTW_GE=y
>  CONFIG_MACH_SHEEVAPLUG=y
>  CONFIG_MACH_ESATA_SHEEVAPLUG=y
>  CONFIG_MACH_GURUPLUG=y
> +CONFIG_MACH_DREAMPLUG_DT=y
> +CONFIG_MACH_ICONNECT_DT=y
> +CONFIG_MACH_DLINK_KIRKWOOD_DT=y
> +CONFIG_MACH_IB62X0_DT=y
> +CONFIG_MACH_TS219_DT=y
> +CONFIG_MACH_GOFLEXNET_DT=y
> +CONFIG_MACH_LSXL_DT=y

Hi Jason

Depending on the order things get merged, it would be good if
Sebastians' and Ians' new boards are also enabled.

	    Andrew


From jason at lakedaemon.net  Sat Aug 11 18:33:15 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 22:33:15 +0000
Subject: [PATCH V2 0/3] ARM: Kirkwood: update defconfig, add dt boards
In-Reply-To: <cover.1344651264.git.jason@lakedaemon.net>
Message-ID: <cover.1344720707.git.jason@lakedaemon.net>

This is a small series to update kirkwood_defconfig to include all of the new
DT boards.  And, finally, SERIAL_OF_PLATFORM is enabled. ;-)

Changes from V1:

  - dropped fix for arch/arm/mach-kirkwood/Makefile.boot since the same patch
    was already posted.
  - removed unneeded defconfig changes so it's purely adding DT boards and
    SERIAL_OF_PLATFORM

Jason Cooper (2):
  ARM: Kirkwood: update defconfig
  ARM: Kirkwood: add DT boards to defconfig

 arch/arm/configs/kirkwood_defconfig |   33 ++++++++++++++-------------------
 1 files changed, 14 insertions(+), 19 deletions(-)

-- 
1.7.8.6



From jason at lakedaemon.net  Sat Aug 11 18:33:16 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 22:33:16 +0000
Subject: [PATCH 1/2] ARM: Kirkwood: update defconfig
In-Reply-To: <cover.1344720707.git.jason@lakedaemon.net>
References: <cover.1344720707.git.jason@lakedaemon.net>
Message-ID: <8f635f63d0de5505ca735cfed2028cd9a2fece09.1344720707.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
Changes from V1:
  - none.

 arch/arm/configs/kirkwood_defconfig |   25 ++++++-------------------
 1 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af5..5a494a3 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,9 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +31,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +47,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +67,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +75,20 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +98,6 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +113,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +140,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +149,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +161,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
-- 
1.7.8.6



From jason at lakedaemon.net  Sat Aug 11 18:33:17 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 22:33:17 +0000
Subject: [PATCH V2 2/2] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <cover.1344720707.git.jason@lakedaemon.net>
References: <cover.1344720707.git.jason@lakedaemon.net>
Message-ID: <32f2ace6ba20829a29786aa650df79a4c7c9b86d.1344720707.git.jason@lakedaemon.net>

Also, enable SERIAL_OF_PLATFORM

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
Changes from V1:
  - restrict changes to only DT boards and SERIAL_OF_PLATFORM

 arch/arm/configs/kirkwood_defconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 5a494a3..46e605f 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -17,6 +17,13 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_DOCKSTAR=y
@@ -89,6 +96,7 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-- 
1.7.8.6



From marex at denx.de  Sat Aug 11 19:11:51 2012
From: marex at denx.de (Marek Vasut)
Date: Sun, 12 Aug 2012 01:11:51 +0200
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <501F8509.1030903@metafoo.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-3-git-send-email-marex@denx.de>
 <501F8509.1030903@metafoo.de>
Message-ID: <201208120111.51639.marex@denx.de>

Dear Lars-Peter Clausen,

> On 08/03/2012 05:28 PM, Marek Vasut wrote:
> > This driver is very basic. It supports userland trigger, buffer and
> > raw access to channels. The support for delay channels is missing
> > altogether.
> 
> Looks mostly good to me. Some comments inline.
> 
> I think you need to provide a documentation for the devicetree binding,
> even though it's a rather simple binding.

Definitelly, will add it.

> > Signed-off-by: Marek Vasut <marex at denx.de>
> > Cc: Jonathan Cameron <jic23 at kernel.org>
> > Cc: Juergen Beisert <jbe at pengutronix.de>
> > Cc: Lars-Peter Clausen <lars at metafoo.de>
> > Cc: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Wolfgang Denk <wd at denx.de>
> > ---
> > 
> >  drivers/staging/iio/adc/Kconfig     |   12 +
> >  drivers/staging/iio/adc/Makefile    |    1 +
> >  drivers/staging/iio/adc/mxs-lradc.c |  591
> >  +++++++++++++++++++++++++++++++++++ 3 files changed, 604 insertions(+)
> >  create mode 100644 drivers/staging/iio/adc/mxs-lradc.c
> > 
> > V2: Use delay channel 0 in case of buffered sampling so the samples are
> > deployed
> > 
> >     continuously.
> >     Disallow RAW sampling while buffered mode is enabled to simplify
> >     code.
> > 
> > diff --git a/drivers/staging/iio/adc/Kconfig
> > b/drivers/staging/iio/adc/Kconfig index 67711b7..97ca697 100644
> > --- a/drivers/staging/iio/adc/Kconfig
> > +++ b/drivers/staging/iio/adc/Kconfig
> 
> [...]
> 
> > + */
> > +static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
> > +			const struct iio_chan_spec *chan,
> > +			int *val, int *val2, long m)
> > +{
> > [...]
> > +
> > +	init_completion(&lradc->completion);
> 
> This should rather be INIT_COMPLETION. init_completion should only called
> once in probe, since it will reinitialize the spinlock which opens up race
> conditions.
> 
> > [...]
> > +
> > +	/* Wait for completion on the channel, 1 second max. */
> > +	ret = wait_for_completion_killable_timeout(&lradc->completion,
> > +						msecs_to_jiffies(1000));
> 
> msecs_to_jiffies(1000) = HZ, but I guess both is OK.

Even on NOHZ kernel?

> > [...]
> > +}
> 
> [...]
> 
> > +
> > +static int __devinit mxs_lradc_probe(struct platform_device *pdev)
> > +{
> > [...]
> > +
> > +	/* Grab all IRQ sources */
> > +	for (i = 0; i < 13; i++) {
> > +		lradc->irq[i] = platform_get_irq(pdev, i);
> > +		if (lradc->irq[i] < 0) {
> > +			ret = -EINVAL;
> > +			goto err_addr;
> > +		}
> > +
> > +		ret = devm_request_irq(dev, lradc->irq[i],
> > +					mxs_lradc_handle_irq, 0,
> > +					mxs_lradc_irq_name[i], iio);
> 
> devm_request_irq is a bit dangerous as long we do not have a
> devm_iio_device_alloc. The IRQ will only be freed after the memory for the
> IIO device has been freed, which means there is a slight window where the
> IRQ could fire although the memory has already been freed.

The IRQ is disabled, see mxs_lradc_hw_stop(), so it should be all right.

> > +		if (ret)
> > +			goto err_addr;
> > +	}
> > +
> > +	dev_set_drvdata(&pdev->dev, iio);
> 
> platform_set_drvdata
> 
> > +
> > +	init_completion(&lradc->completion);
> > +	mutex_init(&lradc->lock);
> > +
> 
> [...]


From jason at lakedaemon.net  Sat Aug 11 19:18:55 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 11 Aug 2012 19:18:55 -0400
Subject: [PATCH 3/3] ARM: Kirkwood: add DT boards to defconfig
In-Reply-To: <20120811220645.GB2856@lunn.ch>
References: <cover.1344651264.git.jason@lakedaemon.net>
 <a0e20df2d8ad6dbcf66fa9a14482a305c4a109fe.1344651264.git.jason@lakedaemon.net>
 <20120811220645.GB2856@lunn.ch>
Message-ID: <20120811231855.GH22226@titan.lakedaemon.net>

On Sun, Aug 12, 2012 at 12:06:45AM +0200, Andrew Lunn wrote:
> On Sat, Aug 11, 2012 at 02:39:47AM +0000, Jason Cooper wrote:
> > Also, disable DEBUG_KERNEL, enable SERIAL_OF_PLATFORM, and enable EMBEDDED
> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/configs/kirkwood_defconfig |   12 +++++++++++-
> >  1 files changed, 11 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
> > index 5a494a3..0865d2e 100644
> > --- a/arch/arm/configs/kirkwood_defconfig
> > +++ b/arch/arm/configs/kirkwood_defconfig
> > @@ -3,6 +3,9 @@ CONFIG_SYSVIPC=y
> >  CONFIG_NO_HZ=y
> >  CONFIG_HIGH_RES_TIMERS=y
> >  CONFIG_LOG_BUF_SHIFT=19
> > +CONFIG_NAMESPACES=y
> > +CONFIG_BLK_DEV_INITRD=y
> > +CONFIG_EMBEDDED=y
> >  CONFIG_PROFILING=y
> >  CONFIG_OPROFILE=y
> >  CONFIG_KPROBES=y
> > @@ -17,6 +20,13 @@ CONFIG_MACH_MV88F6281GTW_GE=y
> >  CONFIG_MACH_SHEEVAPLUG=y
> >  CONFIG_MACH_ESATA_SHEEVAPLUG=y
> >  CONFIG_MACH_GURUPLUG=y
> > +CONFIG_MACH_DREAMPLUG_DT=y
> > +CONFIG_MACH_ICONNECT_DT=y
> > +CONFIG_MACH_DLINK_KIRKWOOD_DT=y
> > +CONFIG_MACH_IB62X0_DT=y
> > +CONFIG_MACH_TS219_DT=y
> > +CONFIG_MACH_GOFLEXNET_DT=y
> > +CONFIG_MACH_LSXL_DT=y
> 
> Depending on the order things get merged, it would be good if
> Sebastians' and Ians' new boards are also enabled.

Agreed, I'll hold off on this until we get theirs upstream, then I'll
push v3 including their boards.

In the future, new boards should include a change to the appropriate
defconfig to enable building them.  I'll make sure to mention it on
anything new coming in.

thx,

Jason.


From nicolas.pitre at linaro.org  Sat Aug 11 22:22:12 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 22:22:12 -0400 (EDT)
Subject: [PATCH v2 01/22] ARM: add mechanism for late code patching
In-Reply-To: <1344648306-15619-2-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-2-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112220400.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> The original phys_to_virt/virt_to_phys patching implementation relied on early
> patching prior to MMU initialization.  On PAE systems running out of >4G
> address space, this would have entailed an additional round of patching after
> switching over to the high address space.
> 
> The approach implemented here conceptually extends the original PHYS_OFFSET
> patching implementation with the introduction of "early" patch stubs.  Early
> patch code is required to be functional out of the box, even before the patch
> is applied.  This is implemented by inserting functional (but inefficient)
> load code into the .runtime.patch.code init section.  Having functional code
> out of the box then allows us to defer the init time patch application until
> later in the init sequence.
> 
> In addition to fitting better with our need for physical address-space
> switch-over, this implementation should be somewhat more extensible by virtue
> of its more readable (and hackable) C implementation.  This should prove
> useful for other similar init time specialization needs, especially in light
> of our multi-platform kernel initiative.
> 
> This code has been boot tested in both ARM and Thumb-2 modes on an ARMv7
> (Cortex-A8) device.
> 
> Note: the obtuse use of stringified symbols in patch_stub() and
> early_patch_stub() is intentional.  Theoretically this should have been
> accomplished with formal operands passed into the asm block, but this requires
> the use of the 'c' modifier for instantiating the long (e.g. .long %c0).
> However, the 'c' modifier has been found to ICE certain versions of GCC, and
> therefore we resort to stringified symbols here.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Reviewed-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/Kconfig                     |    3 +
>  arch/arm/include/asm/module.h        |    7 ++
>  arch/arm/include/asm/runtime-patch.h |  175 +++++++++++++++++++++++++++++++
>  arch/arm/kernel/Makefile             |    1 +
>  arch/arm/kernel/module.c             |    4 +
>  arch/arm/kernel/runtime-patch.c      |  189 ++++++++++++++++++++++++++++++++++
>  arch/arm/kernel/setup.c              |    3 +
>  arch/arm/kernel/vmlinux.lds.S        |   10 ++
>  8 files changed, 392 insertions(+)
>  create mode 100644 arch/arm/include/asm/runtime-patch.h
>  create mode 100644 arch/arm/kernel/runtime-patch.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..d0a04ad 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -61,6 +61,9 @@ config ARM
>  config ARM_HAS_SG_CHAIN
>  	bool
>  
> +config ARM_RUNTIME_PATCH
> +	bool
> +
>  config NEED_SG_DMA_LENGTH
>  	bool
>  
> diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
> index 6c6809f..2090486 100644
> --- a/arch/arm/include/asm/module.h
> +++ b/arch/arm/include/asm/module.h
> @@ -43,9 +43,16 @@ struct mod_arch_specific {
>  #define MODULE_ARCH_VERMAGIC_ARMTHUMB ""
>  #endif
>  
> +#ifdef CONFIG_ARM_RUNTIME_PATCH
> +#define MODULE_ARCH_VERMAGIC_RT_PATCH "rt-patch "
> +#else
> +#define MODULE_ARCH_VERMAGIC_RT_PATCH ""
> +#endif
> +
>  #define MODULE_ARCH_VERMAGIC \
>  	MODULE_ARCH_VERMAGIC_ARMVSN \
>  	MODULE_ARCH_VERMAGIC_ARMTHUMB \
> +	MODULE_ARCH_VERMAGIC_RT_PATCH \
>  	MODULE_ARCH_VERMAGIC_P2V
>  
>  #endif /* _ASM_ARM_MODULE_H */
> diff --git a/arch/arm/include/asm/runtime-patch.h b/arch/arm/include/asm/runtime-patch.h
> new file mode 100644
> index 0000000..6c6e8a2
> --- /dev/null
> +++ b/arch/arm/include/asm/runtime-patch.h
> @@ -0,0 +1,175 @@
> +/*
> + * arch/arm/include/asm/runtime-patch.h
> + * Note: this file should not be included by non-asm/.h files
> + *
> + * Copyright 2012 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_ARM_RUNTIME_PATCH_H
> +#define __ASM_ARM_RUNTIME_PATCH_H
> +
> +#include <linux/stringify.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#ifdef CONFIG_ARM_RUNTIME_PATCH
> +
> +struct patch_info {
> +	void	*insn;
> +	u16	 type;
> +	u8	 insn_size;
> +	u8	 data_size;
> +	u32	 data[0];
> +};
> +
> +#define patch_next(p)		((void *)(p) + sizeof(*(p)) + (p)->data_size)
> +
> +#define PATCH_TYPE_MASK		0x00ff
> +#define PATCH_IMM8		0x0001
> +
> +#define PATCH_EARLY		0x8000
> +
> +#define patch_stub(type, code, patch_data, ...)				\
> +	__asm__("@ patch stub\n"					\
> +		"1:\n"							\
> +		code							\
> +		"2:\n"							\
> +		"	.pushsection .runtime.patch.table, \"a\"\n"	\
> +		"3:\n"							\
> +		"	.word 1b\n"					\
> +		"	.hword (" __stringify(type) ")\n"		\
> +		"	.byte (2b-1b)\n"				\
> +		"	.byte (5f-4f)\n"				\
> +		"4:\n"							\
> +		patch_data						\
> +		"	.align\n"					\
> +		"5:\n"							\
> +		"	.popsection\n"					\
> +		__VA_ARGS__)
> +
> +#define early_patch_stub(type, code, patch_data, ...)			\
> +	__asm__("@ patch stub\n"					\
> +		"1:\n"							\
> +		"	b	6f\n"					\
> +		"2:\n"							\
> +		"	.pushsection .runtime.patch.table, \"a\"\n"	\
> +		"3:\n"							\
> +		"	.word 1b\n"					\
> +		"	.hword (" __stringify(type | PATCH_EARLY) ")\n"	\
> +		"	.byte (2b-1b)\n"				\
> +		"	.byte (5f-4f)\n"				\
> +		"4:\n"							\
> +		patch_data						\
> +		"	.align\n"					\
> +		"5:\n"							\
> +		"	.popsection\n"					\
> +		"	.pushsection .runtime.patch.code, \"ax\"\n"	\
> +		"6:\n"							\
> +		code							\
> +		"	b 2b\n"						\
> +		"	.popsection\n"					\
> +		__VA_ARGS__)
> +
> +/* constant used to force encoding */
> +#define __IMM8		(0x81 << 24)
> +
> +/*
> + * patch_imm8() - init-time specialized binary operation (imm8 operand)
> + *		  This effectively does: to = from "insn" sym,
> + *		  where the value of sym is fixed at init-time, and is patched
> + *		  in as an immediate operand.  This value must be
> + *		  representible as an 8-bit quantity with an optional
> + *		  rotation.
> + *
> + *		  The stub code produced by this variant is non-functional
> + *		  prior to patching.  Use early_patch_imm8() if you need the
> + *		  code to be functional early on in the init sequence.
> + */
> +#define patch_imm8(insn, to, from, sym, offset)				\
> +	patch_stub(PATCH_IMM8,						\
> +		   /* code */						\
> +		   insn " %0, %1, %2\n",				\
> +		   /* patch_data */					\
> +		   ".long " __stringify(sym + offset) "\n"		\
> +		   insn " %0, %1, %2\n",				\
> +		   : "=r" (to)						\
> +		   : "r" (from), "I" (__IMM8), "m" (sym)		\
> +		   : "cc")
> +
> +/*
> + * patch_imm8_mov() - same as patch_imm8(), but for mov/mvn instructions
> + */
> +#define patch_imm8_mov(insn, to, sym, offset)				\
> +	patch_stub(PATCH_IMM8,						\
> +		   /* code */						\
> +		   insn " %0, %1\n",					\
> +		   /* patch_data */					\
> +		   ".long " __stringify(sym + offset) "\n"		\
> +		   insn " %0, %1\n",					\
> +		   : "=r" (to)						\
> +		   : "I" (__IMM8), "m" (sym)				\
> +		   : "cc")
> +
> +/*
> + * early_patch_imm8() - early functional variant of patch_imm8() above.  The
> + *			same restrictions on the constant apply here.  This
> + *			version emits workable (albeit inefficient) code at
> + *			compile-time, and therefore functions even prior to
> + *			patch application.
> + */
> +#define early_patch_imm8(insn, to, from, sym, offset)			\
> +	early_patch_stub(PATCH_IMM8,					\
> +			 /* code */					\
> +			 "ldr	%0, =" __stringify(sym + offset) "\n"	\
> +			 "ldr	%0, [%0]\n"				\
> +			 insn " %0, %1, %0\n",				\
> +			 /* patch_data */				\
> +			 ".long " __stringify(sym + offset) "\n"	\
> +			 insn " %0, %1, %2\n",				\
> +			 : "=&r" (to)					\
> +			 : "r" (from), "I" (__IMM8), "m" (sym)		\
> +			 : "cc")
> +
> +#define early_patch_imm8_mov(insn, to, sym, offset)			\
> +	early_patch_stub(PATCH_IMM8,					\
> +			 /* code */					\
> +			 "ldr	%0, =" __stringify(sym + offset) "\n"	\
> +			 "ldr	%0, [%0]\n"				\
> +			 insn " %0, %0\n",				\
> +			 /* patch_data */				\
> +			 ".long " __stringify(sym + offset) "\n"	\
> +			 insn " %0, %1\n",				\
> +			 : "=&r" (to)					\
> +			 : "I" (__IMM8), "m" (sym)			\
> +			 : "cc")
> +
> +int runtime_patch(const void *table, unsigned size);
> +void runtime_patch_kernel(void);
> +
> +#else
> +
> +static inline int runtime_patch(const void *table, unsigned size)
> +{
> +	return 0;
> +}
> +
> +static inline void runtime_patch_kernel(void)
> +{
> +}
> +
> +#endif /* CONFIG_ARM_RUNTIME_PATCH */
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* __ASM_ARM_RUNTIME_PATCH_H */
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index 7ad2d5c..12cc1e7 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -81,5 +81,6 @@ endif
>  head-y			:= head$(MMUEXT).o
>  obj-$(CONFIG_DEBUG_LL)	+= debug.o
>  obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
> +obj-$(CONFIG_ARM_RUNTIME_PATCH)	+= runtime-patch.o
>  
>  extra-y := $(head-y) vmlinux.lds
> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index 1e9be5d..dcebf80 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -24,6 +24,7 @@
>  #include <asm/sections.h>
>  #include <asm/smp_plat.h>
>  #include <asm/unwind.h>
> +#include <asm/runtime-patch.h>
>  
>  #ifdef CONFIG_XIP_KERNEL
>  /*
> @@ -321,6 +322,9 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
>  	if (s)
>  		fixup_pv_table((void *)s->sh_addr, s->sh_size);
>  #endif
> +	s = find_mod_section(hdr, sechdrs, ".runtime.patch.table");
> +	if (s)
> +		runtime_patch((void *)s->sh_addr, s->sh_size);
>  	s = find_mod_section(hdr, sechdrs, ".alt.smp.init");
>  	if (s && !is_smp())
>  #ifdef CONFIG_SMP_ON_UP
> diff --git a/arch/arm/kernel/runtime-patch.c b/arch/arm/kernel/runtime-patch.c
> new file mode 100644
> index 0000000..fd37a2b
> --- /dev/null
> +++ b/arch/arm/kernel/runtime-patch.c
> @@ -0,0 +1,189 @@
> +/*
> + * arch/arm/kernel/runtime-patch.c
> + *
> + * Copyright 2012 Texas Instruments, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +
> +#include <asm/opcodes.h>
> +#include <asm/cacheflush.h>
> +#include <asm/runtime-patch.h>
> +
> +static inline void flush_icache_insn(void *insn_ptr, int bytes)
> +{
> +	unsigned long insn_addr = (unsigned long)insn_ptr;
> +	flush_icache_range(insn_addr, insn_addr + bytes - 1);
> +}
> +
> +#ifdef CONFIG_THUMB2_KERNEL
> +
> +static int do_patch_imm8(u32 insn, u32 imm, u32 *ninsn)
> +{
> +	u32 op, rot, val;
> +	const u32 supported_ops = (BIT(0)  | /* and */
> +				   BIT(1)  | /* bic */
> +				   BIT(2)  | /* orr/mov */
> +				   BIT(3)  | /* orn/mvn */
> +				   BIT(4)  | /* eor */
> +				   BIT(8)  | /* add */
> +				   BIT(10) | /* adc */
> +				   BIT(11) | /* sbc */
> +				   BIT(12) | /* sub */
> +				   BIT(13)); /* rsb */
> +
> +	insn = __mem_to_opcode_thumb32(insn);
> +
> +	if (!__opcode_is_thumb32(insn)) {
> +		pr_err("patch: invalid thumb2 insn %08x\n", insn);
> +		return -EINVAL;
> +	}
> +
> +	/* allow only data processing (immediate)
> +	 * 1111 0x0x xxx0 xxxx 0xxx xxxx xxxx xxxx */
> +	if ((insn & 0xfa008000) != 0xf0000000) {
> +		pr_err("patch: unknown insn %08x\n", insn);
> +		return -EINVAL;
> +	}
> +
> +	/* extract op code */
> +	op = (insn >> 21) & 0xf;
> +
> +	/* disallow unsupported opcodes */
> +	if ((supported_ops & BIT(op)) == 0) {
> +		pr_err("patch: unsupported opcode %x\n", op);
> +		return -EINVAL;
> +	}
> +
> +	if (imm <= 0xff) {
> +		rot = 0;
> +		val = imm;
> +	} else {
> +		rot = 32 - fls(imm); /* clz */
> +		if (imm & ~(0xff000000 >> rot)) {
> +			pr_err("patch: constant overflow %08x\n", imm);
> +			return -EINVAL;
> +		}
> +		val  = (imm >> (24 - rot)) & 0x7f;
> +		rot += 8; /* encoded i:imm3:a */
> +
> +		/* pack least-sig rot bit into most-sig val bit */
> +		val |= (rot & 1) << 7;
> +		rot >>= 1;
> +	}
> +
> +	*ninsn  = insn & ~(BIT(26) | 0x7 << 12 | 0xff);
> +	*ninsn |= (rot >> 3) << 26;	/* field "i" */
> +	*ninsn |= (rot & 0x7) << 12;	/* field "imm3" */
> +	*ninsn |= val;
> +	*ninsn  = __opcode_to_mem_thumb32(*ninsn);
> +
> +	return 0;
> +}
> +
> +#else
> +
> +static int do_patch_imm8(u32 insn, u32 imm, u32 *ninsn)
> +{
> +	u32 rot, val, op;
> +
> +	insn = __mem_to_opcode_arm(insn);
> +
> +	/* disallow special unconditional instructions
> +	 * 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
> +	if ((insn >> 24) == 0xf) {
> +		pr_err("patch: unconditional insn %08x\n", insn);
> +		return -EINVAL;
> +	}
> +
> +	/* allow only data processing (immediate)
> +	 * xxxx 001x xxxx xxxx xxxx xxxx xxxx xxxx */
> +	if (((insn >> 25) & 0x3) != 1) {
> +		pr_err("patch: unknown insn %08x\n", insn);
> +		return -EINVAL;
> +	}
> +
> +	/* extract op code */
> +	op = (insn >> 20) & 0x1f;
> +
> +	/* disallow unsupported 10xxx op codes */
> +	if (((op >> 3) & 0x3) == 2) {
> +		pr_err("patch: unsupported opcode %08x\n", insn);
> +		return -EINVAL;
> +	}
> +
> +	rot = imm ? __ffs(imm) / 2 : 0;
> +	val = imm >> (rot * 2);
> +	rot = (-rot) & 0xf;
> +
> +	/* does this fit in 8-bit? */
> +	if (val > 0xff) {
> +		pr_err("patch: constant overflow %08x\n", imm);
> +		return -EINVAL;
> +	}
> +
> +	/* patch in new immediate and rotation */
> +	*ninsn = (insn & ~0xfff) | (rot << 8) | val;
> +	*ninsn = __opcode_to_mem_arm(*ninsn);
> +
> +	return 0;
> +}
> +
> +#endif	/* CONFIG_THUMB2_KERNEL */
> +
> +static int apply_patch_imm8(const struct patch_info *p)
> +{
> +	u32 *insn_ptr = p->insn;
> +	int ret;
> +
> +	if (p->insn_size != sizeof(u32) || p->data_size != 2 * sizeof(u32)) {
> +		pr_err("patch: bad patch, insn size %d, data size %d\n",
> +		       p->insn_size, p->data_size);
> +		return -EINVAL;
> +	}
> +
> +	ret = do_patch_imm8(p->data[1], *(u32 *)p->data[0], insn_ptr);
> +	if (ret < 0)
> +		return ret;
> +
> +	flush_icache_insn(insn_ptr, sizeof(u32));
> +
> +	return 0;
> +}
> +
> +int runtime_patch(const void *table, unsigned size)
> +{
> +	const struct patch_info *p = table, *end = (table + size);
> +
> +	for (p = table; p < end; p = patch_next(p)) {
> +		int type = p->type & PATCH_TYPE_MASK;
> +		int ret = -EINVAL;
> +
> +		if (type == PATCH_IMM8)
> +			ret = apply_patch_imm8(p);
> +		if (ret < 0)
> +			return ret;
> +	}
> +	return 0;
> +}
> +
> +void __init runtime_patch_kernel(void)
> +{
> +	extern unsigned __runtime_patch_table_begin, __runtime_patch_table_end;
> +	const void *start = &__runtime_patch_table_begin;
> +	const void *end   = &__runtime_patch_table_end;
> +
> +	BUG_ON(runtime_patch(start, end - start));
> +}
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index a81dcec..669bbf0 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -55,6 +55,7 @@
>  #include <asm/traps.h>
>  #include <asm/unwind.h>
>  #include <asm/memblock.h>
> +#include <asm/runtime-patch.h>
>  
>  #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
>  #include "compat.h"
> @@ -998,6 +999,8 @@ void __init setup_arch(char **cmdline_p)
>  
>  	if (mdesc->init_early)
>  		mdesc->init_early();
> +
> +	runtime_patch_kernel();
>  }
>  
>  
> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
> index 36ff15b..ea35ca0 100644
> --- a/arch/arm/kernel/vmlinux.lds.S
> +++ b/arch/arm/kernel/vmlinux.lds.S
> @@ -167,6 +167,16 @@ SECTIONS
>  		*(.pv_table)
>  		__pv_table_end = .;
>  	}
> +	.init.runtime_patch_table : {
> +		__runtime_patch_table_begin = .;
> +		*(.runtime.patch.table)
> +		__runtime_patch_table_end = .;
> +	}
> +	.init.runtime_patch_code : {
> +		__runtime_patch_code_begin = .;
> +		*(.runtime.patch.code)
> +		__runtime_patch_code_end = .;
> +	}
>  	.init.data : {
>  #ifndef CONFIG_XIP_KERNEL
>  		INIT_DATA
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug 11 22:35:56 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 22:35:56 -0400 (EDT)
Subject: [PATCH v2 02/22] ARM: add self test for runtime patch
 mechanism
In-Reply-To: <1344648306-15619-3-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-3-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112226310.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch adds basic sanity tests to ensure that the instruction patching
> results in valid instruction encodings.  This is done by verifying the output
> of the patch process against a vector of assembler generated instructions at
> init time.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  arch/arm/Kconfig                |   12 ++++++++++++
>  arch/arm/kernel/runtime-patch.c |   41 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d0a04ad..7e552dc 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -211,6 +211,18 @@ config ARM_PATCH_PHYS_VIRT
>  	  this feature (eg, building a kernel for a single machine) and
>  	  you need to shrink the kernel to the minimal size.
>  
> +config ARM_RUNTIME_PATCH_TEST
> +	bool "Self test runtime patching mechanism" if ARM_RUNTIME_PATCH
> +	default y
> +	help
> +	  Select this to enable init time self checking for the runtime kernel
> +	  patching mechanism.  This enables an ISA specific set of tests that
> +	  ensure that the instructions generated by the patch process are
> +	  consistent with those generated by the assembler at compile time.
> +
> +	  Only disable this option if you need to shrink the kernel to the
> +	  minimal size.
> +
>  config NEED_MACH_IO_H
>  	bool
>  	help
> diff --git a/arch/arm/kernel/runtime-patch.c b/arch/arm/kernel/runtime-patch.c
> index fd37a2b..c471d8c 100644
> --- a/arch/arm/kernel/runtime-patch.c
> +++ b/arch/arm/kernel/runtime-patch.c
> @@ -163,6 +163,44 @@ static int apply_patch_imm8(const struct patch_info *p)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_ARM_RUNTIME_PATCH_TEST
> +static void __init __used __naked __patch_test_code_imm8(void)
> +{
> +	__asm__ __volatile__ (
> +		"	.irp	shift1, 0, 6, 12, 18\n"
> +		"	.irp	shift2, 0, 1, 2, 3, 4, 5\n"
> +		"	add     r1, r2, #(0x41 << (\\shift1 + \\shift2))\n"
> +		"	.endr\n"
> +		"	.endr\n"


Maybe adding a "add r1, r2 #0x81 << 24" here might be a good thing since 
this is the most used case but missing from the above.

> +		"	.word	0\n"
> +		: : :
> +	);
> +}
> +
> +static void __init test_patch_imm8(void)
> +{
> +	u32 test_code_addr = (u32)(&__patch_test_code_imm8);
> +	u32 *test_code = (u32 *)(test_code_addr & ~0x3);

Why this masking?  With Thumb2 you may find functions starting at 
halfword aligned addresses.  Only the LSB (indicating thumb mode) should 
be masked out.

> +	int i, ret;
> +	u32 ninsn, insn;
> +
> +	insn = test_code[0];
> +	for (i = 0; test_code[i]; i++) {
> +		ret = do_patch_imm8(insn, 0x41 << i, &ninsn);
> +		if (ret < 0)
> +			pr_err("runtime patch (imm8): failed at shift %d\n", i);
> +		else if (ninsn != test_code[i])
> +			pr_err("runtime patch (imm8): failed, need %x got %x\n",
> +			       test_code[i], ninsn);
> +	}
> +}
> +
> +static void __init runtime_patch_test(void)
> +{
> +	test_patch_imm8();
> +}
> +#endif
> +
>  int runtime_patch(const void *table, unsigned size)
>  {
>  	const struct patch_info *p = table, *end = (table + size);
> @@ -185,5 +223,8 @@ void __init runtime_patch_kernel(void)
>  	const void *start = &__runtime_patch_table_begin;
>  	const void *end   = &__runtime_patch_table_end;
>  
> +#ifdef CONFIG_ARM_RUNTIME_PATCH_TEST
> +	runtime_patch_test();
> +#endif
>  	BUG_ON(runtime_patch(start, end - start));
>  }
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug 11 23:03:09 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 23:03:09 -0400 (EDT)
Subject: [PATCH v2 03/22] ARM: use late patch framework for phys-virt
 patching
In-Reply-To: <1344648306-15619-4-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-4-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112238270.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch replaces the original physical offset patching implementation
> with one that uses the newly added patching framework.  In the process, we now
> unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
> head.S code.

This last sentence is now wrong.

[...]
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index e965f1b..3d93779 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -18,6 +18,8 @@
>  #include <linux/types.h>
>  #include <linux/sizes.h>
>  
> +#include <asm/runtime-patch.h>
> +
>  #ifdef CONFIG_NEED_MACH_MEMORY_H
>  #include <mach/memory.h>
>  #endif
> @@ -151,35 +153,21 @@
>  #ifndef __virt_to_phys
>  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>  
> -/*
> - * Constants used to force the right instruction encodings and shifts
> - * so that all we need to do is modify the 8-bit constant field.
> - */
> -#define __PV_BITS_31_24	0x81000000
> -
> -extern unsigned long __pv_phys_offset;
> -#define PHYS_OFFSET __pv_phys_offset
> -
> -#define __pv_stub(from,to,instr,type)			\
> -	__asm__("@ __pv_stub\n"				\
> -	"1:	" instr "	%0, %1, %2\n"		\
> -	"	.pushsection .pv_table,\"a\"\n"		\
> -	"	.long	1b\n"				\
> -	"	.popsection\n"				\
> -	: "=r" (to)					\
> -	: "r" (from), "I" (type))
> +extern unsigned long	__pv_offset;
> +extern unsigned long	__pv_phys_offset;
> +#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)

What was wrong with the former PHYS_OFFSET = __pv_phys_offset ?

If you really want to have it optimized at run time, you could simply 
use your new stub to patch a mov instruction instead of going through 
__virt_to_phys which uses and add on top of a constant.

>  static inline unsigned long __virt_to_phys(unsigned long x)
>  {
>  	unsigned long t;
> -	__pv_stub(x, t, "add", __PV_BITS_31_24);
> +	early_patch_imm8("add", t, x, __pv_offset, 0);
>  	return t;
>  }
>  
>  static inline unsigned long __phys_to_virt(unsigned long x)
>  {
>  	unsigned long t;
> -	__pv_stub(x, t, "sub", __PV_BITS_31_24);
> +	early_patch_imm8("sub", t, x, __pv_offset, 0);
>  	return t;
>  }
>  #else
> diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
> index 60d3b73..6b388f8 100644
> --- a/arch/arm/kernel/armksyms.c
> +++ b/arch/arm/kernel/armksyms.c
> @@ -152,7 +152,3 @@ EXPORT_SYMBOL(mcount);
>  #endif
>  EXPORT_SYMBOL(__gnu_mcount_nc);
>  #endif
> -
> -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> -EXPORT_SYMBOL(__pv_phys_offset);
> -#endif
> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> index 3db960e..69a3c09 100644
> --- a/arch/arm/kernel/head.S
> +++ b/arch/arm/kernel/head.S
> @@ -117,7 +117,7 @@ ENTRY(stext)
>  	bl	__fixup_smp
>  #endif
>  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> -	bl	__fixup_pv_table
> +	bl	__fixup_pv_offsets
>  #endif
>  	bl	__create_page_tables
>  
> @@ -511,92 +511,29 @@ ENDPROC(fixup_smp)
>  
>  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>  
> -/* __fixup_pv_table - patch the stub instructions with the delta between
> - * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
> - * can be expressed by an immediate shifter operand. The stub instruction
> - * has a form of '(add|sub) rd, rn, #imm'.
> +/*
> + * __fixup_pv_offsets - update __pv_offset and __pv_phys_offset based on the
> + * runtime location of the kernel.
>   */
>  	__HEAD
> -__fixup_pv_table:
> +__fixup_pv_offsets:
>  	adr	r0, 1f
> -	ldmia	r0, {r3-r5, r7}
> +	ldmia	r0, {r3-r6}
>  	sub	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
> -	add	r4, r4, r3	@ adjust table start address
> -	add	r5, r5, r3	@ adjust table end address
> -	add	r7, r7, r3	@ adjust __pv_phys_offset address
> -	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset
> -	mov	r6, r3, lsr #24	@ constant for add/sub instructions
> -	teq	r3, r6, lsl #24 @ must be 16MiB aligned
> -THUMB(	it	ne		@ cross section branch )
> -	bne	__error
> -	str	r6, [r7, #4]	@ save to __pv_offset
> -	b	__fixup_a_pv_table
> -ENDPROC(__fixup_pv_table)
> +	add	r4, r4, r3	@ virt_to_phys(__pv_phys_offset)
> +	add	r5, r5, r3	@ virt_to_phys(__pv_offset)
> +	add	r6, r6, r3	@ virt_to_phys(PAGE_OFFSET) = PHYS_OFFSET
> +	str	r6, [r4]	@ save __pv_phys_offset
> +	str	r3, [r5]	@ save __pv_offset
> +	mov	pc, lr
> +ENDPROC(__fixup_pv_offsets)
>  
>  	.align
>  1:	.long	.
> -	.long	__pv_table_begin
> -	.long	__pv_table_end
> -2:	.long	__pv_phys_offset
> -
> -	.text
> -__fixup_a_pv_table:
> -#ifdef CONFIG_THUMB2_KERNEL
> -	lsls	r6, #24
> -	beq	2f
> -	clz	r7, r6
> -	lsr	r6, #24
> -	lsl	r6, r7
> -	bic	r6, #0x0080
> -	lsrs	r7, #1
> -	orrcs	r6, #0x0080
> -	orr	r6, r6, r7, lsl #12
> -	orr	r6, #0x4000
> -	b	2f
> -1:	add     r7, r3
> -	ldrh	ip, [r7, #2]
> -	and	ip, 0x8f00
> -	orr	ip, r6	@ mask in offset bits 31-24
> -	strh	ip, [r7, #2]
> -2:	cmp	r4, r5
> -	ldrcc	r7, [r4], #4	@ use branch for delay slot
> -	bcc	1b
> -	bx	lr
> -#else
> -	b	2f
> -1:	ldr	ip, [r7, r3]
> -	bic	ip, ip, #0x000000ff
> -	orr	ip, ip, r6	@ mask in offset bits 31-24
> -	str	ip, [r7, r3]
> -2:	cmp	r4, r5
> -	ldrcc	r7, [r4], #4	@ use branch for delay slot
> -	bcc	1b
> -	mov	pc, lr
> +	.long	__pv_phys_offset
> +	.long	__pv_offset
> +	.long	PAGE_OFFSET
>  #endif
> -ENDPROC(__fixup_a_pv_table)
> -
> -ENTRY(fixup_pv_table)
> -	stmfd	sp!, {r4 - r7, lr}
> -	ldr	r2, 2f			@ get address of __pv_phys_offset
> -	mov	r3, #0			@ no offset
> -	mov	r4, r0			@ r0 = table start
> -	add	r5, r0, r1		@ r1 = table size
> -	ldr	r6, [r2, #4]		@ get __pv_offset
> -	bl	__fixup_a_pv_table
> -	ldmfd	sp!, {r4 - r7, pc}
> -ENDPROC(fixup_pv_table)
>  
> -	.align
> -2:	.long	__pv_phys_offset
> -
> -	.data
> -	.globl	__pv_phys_offset
> -	.type	__pv_phys_offset, %object
> -__pv_phys_offset:
> -	.long	0
> -	.size	__pv_phys_offset, . - __pv_phys_offset
> -__pv_offset:
> -	.long	0
> -#endif
>  
>  #include "head-common.S"
> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index dcebf80..ac13dd5 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -317,11 +317,6 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
>  					         maps[i].txt_sec->sh_addr,
>  					         maps[i].txt_sec->sh_size);
>  #endif
> -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> -	s = find_mod_section(hdr, sechdrs, ".pv_table");
> -	if (s)
> -		fixup_pv_table((void *)s->sh_addr, s->sh_size);
> -#endif
>  	s = find_mod_section(hdr, sechdrs, ".runtime.patch.table");
>  	if (s)
>  		runtime_patch((void *)s->sh_addr, s->sh_size);

I missed this in the previous patch, but could you fail the module 
loading by returning an error if runtime_patch() fails?  That would take 
care of not accepting modules that might have been compiled with future 
runtime patching extensions that are not yet supported in an earlier 
kernel.

You also should remove the MODULE_ARCH_VERMAGIC_P2V definitions now that 
the corresponding code is no longer there.


Nicolas


From nicolas.pitre at linaro.org  Sat Aug 11 23:04:49 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 23:04:49 -0400 (EDT)
Subject: [PATCH v2 04/22] ARM: LPAE: use phys_addr_t on virt <--> phys
 conversion
In-Reply-To: <1344648306-15619-5-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-5-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112304130.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch fixes up the types used when converting back and forth between
> physical and virtual addresses.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Reviewed-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/memory.h |   26 ++++++++++++++++++--------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 3d93779..81e1714 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -157,22 +157,32 @@ extern unsigned long	__pv_offset;
>  extern unsigned long	__pv_phys_offset;
>  #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
>  
> -static inline unsigned long __virt_to_phys(unsigned long x)
> +static inline phys_addr_t __virt_to_phys(unsigned long x)
>  {
>  	unsigned long t;
>  	early_patch_imm8("add", t, x, __pv_offset, 0);
>  	return t;
>  }
>  
> -static inline unsigned long __phys_to_virt(unsigned long x)
> +static inline unsigned long __phys_to_virt(phys_addr_t x)
>  {
> -	unsigned long t;
> -	early_patch_imm8("sub", t, x, __pv_offset, 0);
> +	unsigned long t, xlo = x;
> +	early_patch_imm8("sub", t, xlo, __pv_offset, 0);
>  	return t;
>  }
> +
>  #else
> -#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
> -#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
> +
> +static inline phys_addr_t __virt_to_phys(unsigned long x)
> +{
> +	return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
> +}
> +
> +static inline unsigned long __phys_to_virt(phys_addr_t x)
> +{
> +	return x - PHYS_OFFSET + PAGE_OFFSET;
> +}
> +
>  #endif
>  #endif
>  
> @@ -207,14 +217,14 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
>  
>  static inline void *phys_to_virt(phys_addr_t x)
>  {
> -	return (void *)(__phys_to_virt((unsigned long)(x)));
> +	return (void *)__phys_to_virt(x);
>  }
>  
>  /*
>   * Drivers should NOT use these either.
>   */
>  #define __pa(x)			__virt_to_phys((unsigned long)(x))
> -#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
> +#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
>  #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
>  
>  /*
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug 11 23:39:06 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 23:39:06 -0400 (EDT)
Subject: [PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching
In-Reply-To: <1344648306-15619-6-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-6-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112316560.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch adds support for 64-bit physical addresses in virt_to_phys()
> patching.  This does not do real 64-bit add/sub, but instead patches in the
> upper 32-bits of the phys_offset directly into the output of virt_to_phys.
> 
> There is no corresponding change on the phys_to_virt() side, because
> computations on the upper 32-bits would be discarded anyway.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> ---
>  arch/arm/include/asm/memory.h |   22 ++++++++++++++++++----
>  arch/arm/kernel/head.S        |    4 ++++
>  arch/arm/kernel/setup.c       |    2 +-
>  3 files changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 81e1714..dc5fbf3 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -154,14 +154,28 @@
>  #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>  
>  extern unsigned long	__pv_offset;
> -extern unsigned long	__pv_phys_offset;
> +extern phys_addr_t	__pv_phys_offset;
>  #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
>  
>  static inline phys_addr_t __virt_to_phys(unsigned long x)
>  {
> -	unsigned long t;
> -	early_patch_imm8("add", t, x, __pv_offset, 0);
> -	return t;
> +	unsigned long tlo, thi;
> +
> +	early_patch_imm8("add", tlo, x, __pv_offset, 0);
> +
> +#ifdef CONFIG_ARM_LPAE
> +	/*
> +	 * On LPAE, we do not _need_ to do 64-bit arithmetic because the high
> +	 * order 32 bits are never changed by the phys-virt offset.  We simply
> +	 * patch in the high order physical address bits instead.
> +	 */
> +#ifdef __ARMEB__
> +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
> +#else
> +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
> +#endif
> +#endif
> +	return (u64)tlo | (u64)thi << 32;
>  }

Hmmm...  I'm afraid this is going to be suboptimal when LPAE is not 
selected.

First of all, you do not need to cast tlo to a u64 in the return value.

Then, I'm not sure if the compiler is smart enough to see that the 
returned value is a phys_addr_t which can be a u32, and in this case the 
(u64)thi << 32 is going to be truncated right away, and therefore there 
is no point in emiting the corresponding instructions.

Furthermore, if LPAE is not defined, then thi never gets initialized and 
should produce a warning. Did you test compilation of the code with LPAE 
turned off?

I'd prefer something like this where more stuff is validated by the 
compiler:

static inline phys_addr_t __virt_to_phys(unsigned long x)
{
	unsigned long tlo, thi;
	phys_addr_t ret;

	early_patch_imm8("add", tlo, x, __pv_offset, 0);
	ret = tlo;

	if (sizeof(phys_addr_t) > 4) {
#ifdef __ARMEB__
		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
#else
		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
#endif
		ret |= ((u64)thi) << 32;
	}

	return ret);
}

This should let the compiler optimize things whether LPAE is enabledor 
not while validating both cases.


Nicolas


From nicolas.pitre at linaro.org  Sat Aug 11 23:57:41 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 23:57:41 -0400 (EDT)
Subject: [PATCH v2 06/22] ARM: LPAE: use signed arithmetic for mask
 definitions
In-Reply-To: <1344648306-15619-7-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-7-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112356470.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch applies to PAGE_MASK, PMD_MASK, and PGDIR_MASK, where forcing
> unsigned long math truncates the mask at the 32-bits.  This clearly does bad
> things on PAE systems.
> 
> This patch fixes this problem by defining these masks as signed quantities.
> We then rely on sign extension to do the right thing.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>

Reviewed-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/page.h           |    2 +-
>  arch/arm/include/asm/pgtable-3level.h |    6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
> index ecf9019..1e0fe08 100644
> --- a/arch/arm/include/asm/page.h
> +++ b/arch/arm/include/asm/page.h
> @@ -13,7 +13,7 @@
>  /* PAGE_SHIFT determines the page size */
>  #define PAGE_SHIFT		12
>  #define PAGE_SIZE		(_AC(1,UL) << PAGE_SHIFT)
> -#define PAGE_MASK		(~(PAGE_SIZE-1))
> +#define PAGE_MASK		(~((1 << PAGE_SHIFT) - 1))
>  
>  #ifndef __ASSEMBLY__
>  
> diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
> index b249035..ae39d11 100644
> --- a/arch/arm/include/asm/pgtable-3level.h
> +++ b/arch/arm/include/asm/pgtable-3level.h
> @@ -48,16 +48,16 @@
>  #define PMD_SHIFT		21
>  
>  #define PMD_SIZE		(1UL << PMD_SHIFT)
> -#define PMD_MASK		(~(PMD_SIZE-1))
> +#define PMD_MASK		(~((1 << PMD_SHIFT) - 1))
>  #define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
> -#define PGDIR_MASK		(~(PGDIR_SIZE-1))
> +#define PGDIR_MASK		(~((1 << PGDIR_SHIFT) - 1))
>  
>  /*
>   * section address mask and size definitions.
>   */
>  #define SECTION_SHIFT		21
>  #define SECTION_SIZE		(1UL << SECTION_SHIFT)
> -#define SECTION_MASK		(~(SECTION_SIZE-1))
> +#define SECTION_MASK		(~((1 << SECTION_SHIFT) - 1))
>  
>  #define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)
>  
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sat Aug 11 23:58:41 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sat, 11 Aug 2012 23:58:41 -0400 (EDT)
Subject: [PATCH v2 09/22] ARM: LPAE: use phys_addr_t for initrd location
 and size
In-Reply-To: <1344648306-15619-10-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-10-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208112358160.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> From: Vitaly Andrianov <vitalya at ti.com>
> 
> This patch fixes the initrd setup code to use phys_addr_t instead of assuming
> 32-bit addressing.  Without this we cannot boot on systems where initrd is
> located above the 4G physical address limit.
> 
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mm/init.c |   13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index 19ba70b..bae9d05 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -36,12 +36,13 @@
>  
>  #include "mm.h"
>  
> -static unsigned long phys_initrd_start __initdata = 0;
> +static phys_addr_t phys_initrd_start __initdata = 0;
>  static unsigned long phys_initrd_size __initdata = 0;
>  
>  static int __init early_initrd(char *p)
>  {
> -	unsigned long start, size;
> +	phys_addr_t start;
> +	unsigned long size;
>  	char *endp;
>  
>  	start = memparse(p, &endp);
> @@ -347,14 +348,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
>  #ifdef CONFIG_BLK_DEV_INITRD
>  	if (phys_initrd_size &&
>  	    !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
> -		pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
> -		       phys_initrd_start, phys_initrd_size);
> +		pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
> +		       (u64)phys_initrd_start, phys_initrd_size);
>  		phys_initrd_start = phys_initrd_size = 0;
>  	}
>  	if (phys_initrd_size &&
>  	    memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
> -		pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
> -		       phys_initrd_start, phys_initrd_size);
> +		pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
> +		       (u64)phys_initrd_start, phys_initrd_size);
>  		phys_initrd_start = phys_initrd_size = 0;
>  	}
>  	if (phys_initrd_size) {
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sun Aug 12 00:04:59 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:04:59 -0400 (EDT)
Subject: [PATCH v2 10/22] ARM: LPAE: use phys_addr_t in switch_mm()
In-Reply-To: <1344648306-15619-11-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-11-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208120000000.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch modifies the switch_mm() processor functions to use phys_addr_t.
> On LPAE systems, we now honor the upper 32-bits of the physical address that
> is being passed in, and program these into TTBR as expected.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> ---
>  arch/arm/include/asm/proc-fns.h |    4 ++--
>  arch/arm/mm/proc-v7-3level.S    |   26 ++++++++++++++++++++++----
>  2 files changed, 24 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
> index f3628fb..75b5f14 100644
> --- a/arch/arm/include/asm/proc-fns.h
> +++ b/arch/arm/include/asm/proc-fns.h
> @@ -60,7 +60,7 @@ extern struct processor {
>  	/*
>  	 * Set the page table
>  	 */
> -	void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
> +	void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
>  	/*
>  	 * Set a possibly extended PTE.  Non-extended PTEs should
>  	 * ignore 'ext'.
> @@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
>  extern void cpu_proc_fin(void);
>  extern int cpu_do_idle(void);
>  extern void cpu_dcache_clean_area(void *, int);
> -extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
> +extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
>  #ifdef CONFIG_ARM_LPAE
>  extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
>  #else
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 8de0f1d..78bd88c 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -39,6 +39,22 @@
>  #define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
>  #define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)
>  
> +#define rzero	r3
> +#ifndef CONFIG_ARM_LPAE
> +#  define rpgdl	r0
> +#  define rpgdh	rzero
> +#  define rmm	r1
> +#else
> +#  define rmm	r2
> +#ifndef __ARMEB__
> +#  define rpgdl	r0
> +#  define rpgdh	r1
> +#else
> +#  define rpgdl	r1
> +#  define rpgdh	r0
> +#endif
> +#endif

Given proc-v7-3level.S is used only when CONFIG_ARM_LPAE is defined, you 
shouldn't need all the above.

>  /*
>   * cpu_v7_switch_mm(pgd_phys, tsk)
>   *
> @@ -47,10 +63,12 @@
>   */
>  ENTRY(cpu_v7_switch_mm)
>  #ifdef CONFIG_MMU
> -	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
> -	and	r3, r1, #0xff
> -	mov	r3, r3, lsl #(48 - 32)		@ ASID
> -	mcrr	p15, 0, r0, r3, c2		@ set TTB 0
> +	mov	rzero, #0
> +	ldr	rmm, [rmm, #MM_CONTEXT_ID]	@ get mm->context.id
> +	and	rmm, rmm, #0xff
> +	mov	rmm, rmm, lsl #(48 - 32)	@ ASID
> +	orr	rpgdh, rpgdh, rmm		@ upper 32-bits of pgd phys
> +	mcrr	p15, 0, rpgdl, rpgdh, c2	@ set TTB 0
>  	isb
>  #endif
>  	mov	pc, lr
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sun Aug 12 00:11:33 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:11:33 -0400 (EDT)
Subject: [PATCH v2 11/22] ARM: LPAE: use 64-bit accessors for TTBR
 registers
In-Reply-To: <1344648306-15619-12-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-12-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208120008380.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch adds TTBR accessor macros, and modifies cpu_get_pgd() and
> the LPAE version of cpu_set_reserved_ttbr0() to use these instead.
> 
> In the process, we also fix these functions to correctly handle cases
> where the physical address lies beyond the 4G limit of 32-bit addressing.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> ---
>  arch/arm/include/asm/proc-fns.h |   24 +++++++++++++++++++-----
>  arch/arm/mm/context.c           |    9 ++-------
>  2 files changed, 21 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
> index 75b5f14..24224df 100644
> --- a/arch/arm/include/asm/proc-fns.h
> +++ b/arch/arm/include/asm/proc-fns.h
> @@ -116,13 +116,27 @@ extern void cpu_resume(void);
>  #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
>  
>  #ifdef CONFIG_ARM_LPAE
> +
> +#define cpu_get_ttbr(nr)					\
> +	({							\
> +		u64 ttbr;					\
> +		__asm__("mrrc	p15, " #nr ", %Q0, %R0, c2"	\
> +			: "=r" (ttbr)				\
> +			: : "cc");				\
> +		ttbr;						\
> +	})

I don't think you have to clobber the condition code (cc) here.  It has 
been a long while since the ability to pass a condition code inside an 
inline assembly statement was removed from gcc.

Other that that...

Acked-by: Nicolas Pitre <nico at linaro.org>


Nicolas


From nicolas.pitre at linaro.org  Sun Aug 12 00:19:14 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:19:14 -0400 (EDT)
Subject: [PATCH v2 13/22] ARM: LPAE: factor out T1SZ and TTBR1 computations
In-Reply-To: <1344648306-15619-14-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-14-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208120016010.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch moves the TTBR1 offset calculation and the T1SZ calculation out
> of the TTB setup assembly code.  This should not affect functionality in
> any way, but improves code readability as well as readability of subsequent
> patches in this series.
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/include/asm/pgtable-3level-hwdef.h |   10 ++++++++++
>  arch/arm/mm/proc-v7-3level.S                |   16 ++++------------
>  2 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
> index d795282..b501650 100644
> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
> @@ -74,4 +74,14 @@
>  #define PHYS_MASK_SHIFT		(40)
>  #define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)
>  
> +#if defined CONFIG_VMSPLIT_2G
> +#define TTBR1_OFFSET	(1 << 4)		/* skip two L1 entries */
> +#elif defined CONFIG_VMSPLIT_3G
> +#define TTBR1_OFFSET	(4096 * (1 + 3))	/* only L2, skip pgd + 3*pmd */
> +#else
> +#define TTBR1_OFFSET	0
> +#endif
> +
> +#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)
> +
>  #endif
> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
> index 78bd88c..e28383f 100644
> --- a/arch/arm/mm/proc-v7-3level.S
> +++ b/arch/arm/mm/proc-v7-3level.S
> @@ -137,18 +137,10 @@ ENDPROC(cpu_v7_set_pte_ext)
>  	 * booting secondary CPUs would end up using TTBR1 for the identity
>  	 * mapping set up in TTBR0.
>  	 */
> -	bhi	9001f				@ PHYS_OFFSET > PAGE_OFFSET?
> -	orr	\tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
> -#if defined CONFIG_VMSPLIT_2G
> -	/* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
> -	add	\ttbr1, \ttbr1, #1 << 4		@ skip two L1 entries
> -#elif defined CONFIG_VMSPLIT_3G
> -	/* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
> -	add	\ttbr1, \ttbr1, #4096 * (1 + 3)	@ only L2 used, skip pgd+3*pmd
> -#endif
> -	/* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
> -9001:	mcr	p15, 0, \tmp, c2, c0, 2		@ TTB control register
> -	mcrr	p15, 1, \ttbr1, \zero, c2	@ load TTBR1
> +	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
> +	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
> +	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
> +	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1
>  	.endm
>  
>  	__CPUINIT
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sun Aug 12 00:29:54 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:29:54 -0400 (EDT)
Subject: [PATCH v2 15/22] ARM: mm: use physical addresses in highmem
 sanity checks
In-Reply-To: <1344648306-15619-16-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-16-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208120029110.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> This patch modifies the highmem sanity checking code to use physical addresses
> instead.  This change eliminates the wrap-around problems associated with the
> original virtual address based checks, and this simplifies the code a bit.
> 
> The one constraint imposed here is that low physical memory must be mapped in
> a monotonically increasing fashion if there are multiple banks of memory,
> i.e., x < y must => pa(x) < pa(y).
> 
> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/mm/mmu.c |   22 ++++++++++------------
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 53eeeb8..f764c03 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -895,6 +895,7 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
>  void __init sanity_check_meminfo(void)
>  {
>  	int i, j, highmem = 0;
> +	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
>  
>  	for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
>  		struct membank *bank = &meminfo.bank[j];
> @@ -904,8 +905,7 @@ void __init sanity_check_meminfo(void)
>  			highmem = 1;
>  
>  #ifdef CONFIG_HIGHMEM
> -		if (__va(bank->start) >= vmalloc_min ||
> -		    __va(bank->start) < (void *)PAGE_OFFSET)
> +		if (bank->start >= vmalloc_limit)
>  			highmem = 1;
>  
>  		bank->highmem = highmem;
> @@ -914,8 +914,8 @@ void __init sanity_check_meminfo(void)
>  		 * Split those memory banks which are partially overlapping
>  		 * the vmalloc area greatly simplifying things later.
>  		 */
> -		if (!highmem && __va(bank->start) < vmalloc_min &&
> -		    bank->size > vmalloc_min - __va(bank->start)) {
> +		if (!highmem && bank->start < vmalloc_limit &&
> +		    bank->size > vmalloc_limit - bank->start) {
>  			if (meminfo.nr_banks >= NR_BANKS) {
>  				printk(KERN_CRIT "NR_BANKS too low, "
>  						 "ignoring high memory\n");
> @@ -924,12 +924,12 @@ void __init sanity_check_meminfo(void)
>  					(meminfo.nr_banks - i) * sizeof(*bank));
>  				meminfo.nr_banks++;
>  				i++;
> -				bank[1].size -= vmalloc_min - __va(bank->start);
> -				bank[1].start = __pa(vmalloc_min - 1) + 1;
> +				bank[1].size -= vmalloc_limit - bank->start;
> +				bank[1].start = vmalloc_limit;
>  				bank[1].highmem = highmem = 1;
>  				j++;
>  			}
> -			bank->size = vmalloc_min - __va(bank->start);
> +			bank->size = vmalloc_limit - bank->start;
>  		}
>  #else
>  		bank->highmem = highmem;
> @@ -949,8 +949,7 @@ void __init sanity_check_meminfo(void)
>  		 * Check whether this memory bank would entirely overlap
>  		 * the vmalloc area.
>  		 */
> -		if (__va(bank->start) >= vmalloc_min ||
> -		    __va(bank->start) < (void *)PAGE_OFFSET) {
> +		if (bank->start >= vmalloc_limit) {
>  			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
>  			       "(vmalloc region overlap).\n",
>  			       (unsigned long long)bank->start,
> @@ -962,9 +961,8 @@ void __init sanity_check_meminfo(void)
>  		 * Check whether this memory bank would partially overlap
>  		 * the vmalloc area.
>  		 */
> -		if (__va(bank->start + bank->size) > vmalloc_min ||
> -		    __va(bank->start + bank->size) < __va(bank->start)) {
> -			unsigned long newsize = vmalloc_min - __va(bank->start);
> +		if (bank->start + bank->size > vmalloc_limit)
> +			unsigned long newsize = vmalloc_limit - bank->start;
>  			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
>  			       "to -%.8llx (vmalloc region overlap).\n",
>  			       (unsigned long long)bank->start,
> -- 
> 1.7.9.5
> 


From nicolas.pitre at linaro.org  Sun Aug 12 00:36:21 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:36:21 -0400 (EDT)
Subject: [PATCH v2 16/22] ARM: mm: cleanup checks for membank overlap
 with vmalloc area
In-Reply-To: <1344648306-15619-17-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-17-git-send-email-cyril@ti.com>
Message-ID: <alpine.LFD.2.02.1208120034220.5231@xanadu.home>

On Fri, 10 Aug 2012, Cyril Chemparathy wrote:

> On Keystone platforms, physical memory is entirely outside the 32-bit
> addressible range.  Therefore, the (bank->start > ULONG_MAX) check below marks
> the entire system memory as highmem, and this causes unpleasentness all over.
> 
> This patch eliminates the extra bank start check (against ULONG_MAX) by
> checking bank->start against the physical address corresponding to vmalloc_min
> instead.
> 
> In the process, this patch also cleans up parts of the highmem sanity check
> code by removing what has now become a redundant check for banks that entirely
> overlap with the vmalloc range.

Are you sure of this?  The code that you removed not only checks for 
banks that fall into the vmalloc area, but it also skipp them.  This is 
now lost.

> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> ---
>  arch/arm/mm/mmu.c |   19 +------------------
>  1 file changed, 1 insertion(+), 18 deletions(-)
> 
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index f764c03..3d685c6 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -901,15 +901,12 @@ void __init sanity_check_meminfo(void)
>  		struct membank *bank = &meminfo.bank[j];
>  		*bank = meminfo.bank[i];
>  
> -		if (bank->start > ULONG_MAX)
> -			highmem = 1;
> -
> -#ifdef CONFIG_HIGHMEM
>  		if (bank->start >= vmalloc_limit)
>  			highmem = 1;
>  
>  		bank->highmem = highmem;
>  
> +#ifdef CONFIG_HIGHMEM
>  		/*
>  		 * Split those memory banks which are partially overlapping
>  		 * the vmalloc area greatly simplifying things later.
> @@ -932,8 +929,6 @@ void __init sanity_check_meminfo(void)
>  			bank->size = vmalloc_limit - bank->start;
>  		}
>  #else
> -		bank->highmem = highmem;
> -
>  		/*
>  		 * Highmem banks not allowed with !CONFIG_HIGHMEM.
>  		 */
> @@ -946,18 +941,6 @@ void __init sanity_check_meminfo(void)
>  		}
>  
>  		/*
> -		 * Check whether this memory bank would entirely overlap
> -		 * the vmalloc area.
> -		 */
> -		if (bank->start >= vmalloc_limit) {
> -			printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
> -			       "(vmalloc region overlap).\n",
> -			       (unsigned long long)bank->start,
> -			       (unsigned long long)bank->start + bank->size - 1);
> -			continue;
> -		}
> -
> -		/*
>  		 * Check whether this memory bank would partially overlap
>  		 * the vmalloc area.
>  		 */
> -- 
> 1.7.9.5
> 


From nico at fluxnic.net  Sun Aug 12 00:51:40 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Sun, 12 Aug 2012 00:51:40 -0400 (EDT)
Subject: [GIT PULL] LED CPU trigger driver and ARM LED code consolidation
 (v2)
In-Reply-To: <CAK5ve-LX_q154+BYxzns38yAZ9BcLxsA26negXo9K4XMNxcrWA@mail.gmail.com>
References: <CAK5ve-KjK2mU0qjdp2HK5CdrM=eQ-hN0nw-0cJj7HGuRyGjH8w@mail.gmail.com>
 <CAK5ve-+wWWARGz4ky_VW2AK7hHLXENkw2ANToLztcDjsegubsw@mail.gmail.com>
 <CAOesGMhK3bkk+86jDM7bd6rFUE_RuTGWiWsB7SYJ=i2NocOiLA@mail.gmail.com>
 <CAK5ve-KuB=5evdiJDSQbN0N=56fofNeaof==GuRXFWhA44KcAw@mail.gmail.com>
 <CAOesGMi8UeX8fLba4F+Jo0VNadcBHbUsnc0HHA=SNx0S7=EFJw@mail.gmail.com>
 <CAK5ve-+hFRkbZ1bmfKodzjZEyP8vTyxZzU96LnhYjp1Vn7OWcw@mail.gmail.com>
 <20120811080429.GA18957@n2100.arm.linux.org.uk>
 <CAK5ve-LX_q154+BYxzns38yAZ9BcLxsA26negXo9K4XMNxcrWA@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208120048390.5231@xanadu.home>

On Sat, 11 Aug 2012, Bryan Wu wrote:

> On Sat, Aug 11, 2012 at 4:04 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Sat, Aug 11, 2012 at 02:57:18PM +0800, Bryan Wu wrote:
> >> Olof, could you please consider pull again this branch? I keep it
> >> based on 3.5 release.
> >
> > So what's the fix you've applied?  I don't think you've posted any patches.
> 
> I assume I need update my branch instead of posting some incremental
> patches, since my branch was dropped. So I prepared a new branch
> including the fixing.
> 
> Need I post my fix? But I don't keep the old version.
> Olof and Arnd, maybe you guys keep my old version.

You should post the new version of the patch that Russell previously 
objected to.


Nicolas


From lars at metafoo.de  Sun Aug 12 05:27:59 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Sun, 12 Aug 2012 11:27:59 +0200
Subject: [PATCH 2/3 V2] IIO: Add basic MXS LRADC driver
In-Reply-To: <201208120111.51639.marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
 <1344007721-11595-3-git-send-email-marex@denx.de>
 <501F8509.1030903@metafoo.de> <201208120111.51639.marex@denx.de>
Message-ID: <5027771F.7060500@metafoo.de>

On 08/12/2012 01:11 AM, Marek Vasut wrote:
> Dear Lars-Peter Clausen,
> 
>> On 08/03/2012 05:28 PM, Marek Vasut wrote:
>>> This driver is very basic. It supports userland trigger, buffer and
>>> raw access to channels. The support for delay channels is missing
>>> altogether.
>>
>> Looks mostly good to me. Some comments inline.
>>
>> I think you need to provide a documentation for the devicetree binding,
>> even though it's a rather simple binding.
> 
> Definitelly, will add it.
> 
>>> Signed-off-by: Marek Vasut <marex at denx.de>
>>> Cc: Jonathan Cameron <jic23 at kernel.org>
>>> Cc: Juergen Beisert <jbe at pengutronix.de>
>>> Cc: Lars-Peter Clausen <lars at metafoo.de>
>>> Cc: Shawn Guo <shawn.guo at linaro.org>
>>> Cc: Wolfgang Denk <wd at denx.de>
>>> ---
>>>
>>>  drivers/staging/iio/adc/Kconfig     |   12 +
>>>  drivers/staging/iio/adc/Makefile    |    1 +
>>>  drivers/staging/iio/adc/mxs-lradc.c |  591
>>>  +++++++++++++++++++++++++++++++++++ 3 files changed, 604 insertions(+)
>>>  create mode 100644 drivers/staging/iio/adc/mxs-lradc.c
>>>
>>> V2: Use delay channel 0 in case of buffered sampling so the samples are
>>> deployed
>>>
>>>     continuously.
>>>     Disallow RAW sampling while buffered mode is enabled to simplify
>>>     code.
>>>
>>> diff --git a/drivers/staging/iio/adc/Kconfig
>>> b/drivers/staging/iio/adc/Kconfig index 67711b7..97ca697 100644
>>> --- a/drivers/staging/iio/adc/Kconfig
>>> +++ b/drivers/staging/iio/adc/Kconfig
>>
>> [...]
>>
>>> + */
>>> +static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
>>> +			const struct iio_chan_spec *chan,
>>> +			int *val, int *val2, long m)
>>> +{
>>> [...]
>>> +
>>> +	init_completion(&lradc->completion);
>>
>> This should rather be INIT_COMPLETION. init_completion should only called
>> once in probe, since it will reinitialize the spinlock which opens up race
>> conditions.
>>
>>> [...]
>>> +
>>> +	/* Wait for completion on the channel, 1 second max. */
>>> +	ret = wait_for_completion_killable_timeout(&lradc->completion,
>>> +						msecs_to_jiffies(1000));
>>
>> msecs_to_jiffies(1000) = HZ, but I guess both is OK.
> 
> Even on NOHZ kernel?

Yes HZ is always the number of jiffies per second.

> 
>>> [...]
>>> +}
>>
>> [...]
>>
>>> +
>>> +static int __devinit mxs_lradc_probe(struct platform_device *pdev)
>>> +{
>>> [...]
>>> +
>>> +	/* Grab all IRQ sources */
>>> +	for (i = 0; i < 13; i++) {
>>> +		lradc->irq[i] = platform_get_irq(pdev, i);
>>> +		if (lradc->irq[i] < 0) {
>>> +			ret = -EINVAL;
>>> +			goto err_addr;
>>> +		}
>>> +
>>> +		ret = devm_request_irq(dev, lradc->irq[i],
>>> +					mxs_lradc_handle_irq, 0,
>>> +					mxs_lradc_irq_name[i], iio);
>>
>> devm_request_irq is a bit dangerous as long we do not have a
>> devm_iio_device_alloc. The IRQ will only be freed after the memory for the
>> IIO device has been freed, which means there is a slight window where the
>> IRQ could fire although the memory has already been freed.
> 
> The IRQ is disabled, see mxs_lradc_hw_stop(), so it should be all right.

Ok.


From linux at arm.linux.org.uk  Sun Aug 12 06:57:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 12 Aug 2012 11:57:08 +0100
Subject: [PATCH] Allow memblock steal operations to remove memory from anywhere
Message-ID: <20120812105708.GD18957@n2100.arm.linux.org.uk>

Found this with the cubox, which wants to obtain large blocks of
RAM for the GPU and VPU devices at boot time.  I don't believe
any other platforms care where the memory comes from, so I think
this is safe.

However, OMAP and iMX folk should check this patch - thanks.

8<===
From: Russell King <rmk+kernel at arm.linux.org.uk>
Subject: ARM: Allow arm_memblock_steal() to remove memory from any RAM region

Allow arm_memblock_steal() to remove memory from any RAM region,
including highmem areas.  This allows memory to be stolen from the
very top of declared memory, including highmem areas, rather than
our precious lowmem.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mm/init.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f54d592..04632f3 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
 
 	BUG_ON(!arm_memblock_steal_permitted);
 
-	phys = memblock_alloc(size, align);
+	phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
 	memblock_free(phys, size);
 	memblock_remove(phys, size);
 


From cavokz at gmail.com  Sun Aug 12 07:24:33 2012
From: cavokz at gmail.com (Domenico Andreoli)
Date: Sun, 12 Aug 2012 13:24:33 +0200
Subject: [PATCH V3] CS89x0 : Use ioread16/iowrite16 on all platforms
In-Reply-To: <20120517.190346.175685939436302276.davem@davemloft.net>
References: <1337274702-19536-1-git-send-email-jaccon.bastiaansen@gmail.com>
 <20120517.190346.175685939436302276.davem@davemloft.net>
Message-ID: <20120812112433.GA31699@glitch>

On Thu, May 17, 2012 at 07:03:46PM -0400, David Miller wrote:
> From: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> Date: Thu, 17 May 2012 19:11:42 +0200
> 
> > The use of the inw/outw functions by the cs89x0 platform driver
> > results in NULL pointer references on ARM platforms and
> > platforms that do not provide ISA-style programmed I/O accessors.
> > 
> > Using inw/outw also accesses the wrong address space on platforms
> > that have a PCI I/O space that is not identity-mapped into the
> > physical address space.
> > 
> > Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> 
> I could nit-pick more on this patch, but it's such a significant
> improvement I'm just going to apply this V3 as-is to net-next.

Is this going into v3.6 or v3.7?

cheers,
Domenico


From s.hauer at pengutronix.de  Sun Aug 12 08:07:59 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 12 Aug 2012 14:07:59 +0200
Subject: [PATCH] Allow memblock steal operations to remove memory from
 anywhere
In-Reply-To: <20120812105708.GD18957@n2100.arm.linux.org.uk>
References: <20120812105708.GD18957@n2100.arm.linux.org.uk>
Message-ID: <20120812120759.GH1451@pengutronix.de>

On Sun, Aug 12, 2012 at 11:57:08AM +0100, Russell King - ARM Linux wrote:
> Found this with the cubox, which wants to obtain large blocks of
> RAM for the GPU and VPU devices at boot time.  I don't believe
> any other platforms care where the memory comes from, so I think
> this is safe.
> 
> However, OMAP and iMX folk should check this patch - thanks.
> 
> 8<===
> From: Russell King <rmk+kernel at arm.linux.org.uk>
> Subject: ARM: Allow arm_memblock_steal() to remove memory from any RAM region
> 
> Allow arm_memblock_steal() to remove memory from any RAM region,
> including highmem areas.  This allows memory to be stolen from the
> very top of declared memory, including highmem areas, rather than
> our precious lowmem.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>

There shouldn't be any problems with this on i.MX.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>


> ---
>  arch/arm/mm/init.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index f54d592..04632f3 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
>  
>  	BUG_ON(!arm_memblock_steal_permitted);
>  
> -	phys = memblock_alloc(size, align);
> +	phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
>  	memblock_free(phys, size);
>  	memblock_remove(phys, size);
>  
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From santosh.shilimkar at ti.com  Sun Aug 12 08:46:57 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Sun, 12 Aug 2012 18:16:57 +0530
Subject: [PATCH] Allow memblock steal operations to remove memory from
 anywhere
In-Reply-To: <20120812105708.GD18957@n2100.arm.linux.org.uk>
References: <20120812105708.GD18957@n2100.arm.linux.org.uk>
Message-ID: <CAMQu2gz=omKAEv+obBW8EuS_ug=dZUkeXb_iP21-JLTxPNj3dw@mail.gmail.com>

On Sun, Aug 12, 2012 at 4:27 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> Found this with the cubox, which wants to obtain large blocks of
> RAM for the GPU and VPU devices at boot time.  I don't believe
> any other platforms care where the memory comes from, so I think
> this is safe.
>
Agree.

> However, OMAP and iMX folk should check this patch - thanks.
>
Works for OMAP without any issues.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

> 8<===
> From: Russell King <rmk+kernel at arm.linux.org.uk>
> Subject: ARM: Allow arm_memblock_steal() to remove memory from any RAM region
>
> Allow arm_memblock_steal() to remove memory from any RAM region,
> including highmem areas.  This allows memory to be stolen from the
> very top of declared memory, including highmem areas, rather than
> our precious lowmem.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  arch/arm/mm/init.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> index f54d592..04632f3 100644
> --- a/arch/arm/mm/init.c
> +++ b/arch/arm/mm/init.c
> @@ -324,7 +324,7 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
>
>         BUG_ON(!arm_memblock_steal_permitted);
>
> -       phys = memblock_alloc(size, align);
> +       phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
>         memblock_free(phys, size);
>         memblock_remove(phys, size);
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From marex at denx.de  Sun Aug 12 10:23:54 2012
From: marex at denx.de (Marek Vasut)
Date: Sun, 12 Aug 2012 16:23:54 +0200
Subject: [PATCH 0/3] i.MX28 LRADC driver
In-Reply-To: <1344007721-11595-1-git-send-email-marex@denx.de>
References: <1344007721-11595-1-git-send-email-marex@denx.de>
Message-ID: <201208121623.54801.marex@denx.de>

Dear Marek Vasut,

> Introduce the i.MX28 LRADC driver and support tech that comes with it.
> 
> Marek Vasut (3):
>   IIO: Add 4-byte unsigned reads into generic-buffer example
>   IIO: Add basic MXS LRADC driver
>   IIO: arm: Add LRADC to i.MX28 dts

What about 1/3 btw? Can that be applied ?

>  arch/arm/boot/dts/imx28.dtsi                       |    3 +
>  drivers/staging/iio/Documentation/generic_buffer.c |   10 +
>  drivers/staging/iio/adc/Kconfig                    |   12 +
>  drivers/staging/iio/adc/Makefile                   |    1 +
>  drivers/staging/iio/adc/mxs-lradc.c                |  591
> ++++++++++++++++++++ 5 files changed, 617 insertions(+)
>  create mode 100644 drivers/staging/iio/adc/mxs-lradc.c
> 
> Cc: Jonathan Cameron <jic23 at kernel.org>
> Cc: Juergen Beisert <jbe at pengutronix.de>
> Cc: Lars-Peter Clausen <lars at metafoo.de>
> Cc: Wolfgang Denk <wd at denx.de>

Best regards,
Marek Vasut


From andrew at lunn.ch  Sun Aug 12 11:22:07 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 12 Aug 2012 17:22:07 +0200
Subject: [PATCH v2 2/6] ARM: dove: add clock gating control
In-Reply-To: <1344681326-17946-3-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344255815-4457-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344681326-17946-3-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20120812152207.GA6340@lunn.ch>

On Sat, Aug 11, 2012 at 12:35:22PM +0200, Sebastian Hesselbarth wrote:
> This patch adds clock gates from the clock gating control register
> available on dove. All clock gates are hooked up to tclk, except for
> gigabit ethernet controller (ge) which is a child of gephy to allow
> both enabled/disabled at the same time.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> Cc: Rabeeh Khoury <rabeeh at solid-run.com>
> Cc: Ian Molton <ian.molton at codethink.co.uk>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Maen Suleiman <maen at marvell.com>
> Cc: Olof Johansson <olof at lixom.net>
> 
> v2: adapted to removed clk_prepare_enable from patch 1
> ---
>  arch/arm/mach-dove/common.c          |   59 +++++++++++++++++++++++++++++++++-
>  arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++++++++++++++-----------
>  2 files changed, 94 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
> index b6f092c..7281591 100644
> --- a/arch/arm/mach-dove/common.c
> +++ b/arch/arm/mach-dove/common.c
> @@ -16,6 +16,7 @@
>  #include <linux/clk-provider.h>
>  #include <linux/ata_platform.h>
>  #include <linux/gpio.h>
> +#include <linux/mv643xx_i2c.h>
>  #include <asm/page.h>
>  #include <asm/setup.h>
>  #include <asm/timex.h>
> @@ -24,6 +25,7 @@
>  #include <asm/mach/time.h>
>  #include <asm/mach/pci.h>
>  #include <mach/dove.h>
> +#include <mach/pm.h>
>  #include <mach/bridge-regs.h>
>  #include <asm/mach/arch.h>
>  #include <linux/irq.h>
> @@ -31,6 +33,7 @@
>  #include <plat/ehci-orion.h>
>  #include <plat/common.h>
>  #include <plat/addr-map.h>
> +#include <plat/mv_xor.h>
>  #include "common.h"
>  
>  /*****************************************************************************
> @@ -69,14 +72,68 @@ void __init dove_map_io(void)
>   * CLK tree
>   ****************************************************************************/
>  static int dove_tclk;
> +
> +static DEFINE_SPINLOCK(gating_lock);
>  static struct clk *tclk;
>  
> +static struct clk __init *dove_register_gate(const char *name,
> +					     const char *parent, u8 bit_idx)
> +{
> +	return clk_register_gate(NULL, name, parent, 0,
> +				 (void __iomem *)CLOCK_GATING_CONTROL,
> +				 bit_idx, 0, &gating_lock);
> +}
> +
>  static void __init dove_clk_init(void)
>  {
> +	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
> +	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
> +	struct clk *xor0, *xor1, *ge, *gephy;
> +
>  	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
>  				       dove_tclk);
>  
> -	orion_clkdev_init(tclk);
> +	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
> +	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
> +	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
> +	pex0 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE0);
> +	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
> +	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
> +	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
> +	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
> +	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
> +	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
> +	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
> +	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
> +	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
> +	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
> +	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
> +	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
> +	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
> +	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
> +
> +	orion_clkdev_add(NULL, "orion_spi.0", tclk);
> +	orion_clkdev_add(NULL, "orion_spi.1", tclk);
> +	orion_clkdev_add(NULL, "orion_wdt", tclk);
> +	orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
> +
> +	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
> +	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
> +	orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge);

Hi Sebastian

Take a look at the patch [PATCH v3 7/7] NET: mv643xx: remove device
name macro, from Ian Molten, and the discussion around the macro
MV643XX_ETH_NAME and its friend.

It is probably best to not use the I2C and XOR macro as well.

		 Andrew


From cyril at ti.com  Sun Aug 12 12:32:47 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 12 Aug 2012 12:32:47 -0400
Subject: [PATCH v2 02/22] ARM: add self test for runtime patch mechanism
In-Reply-To: <alpine.LFD.2.02.1208112226310.5231@xanadu.home>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-3-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112226310.5231@xanadu.home>
Message-ID: <5027DAAF.2060406@ti.com>

On 08/11/12 22:35, Nicolas Pitre wrote:
> On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
>
>> This patch adds basic sanity tests to ensure that the instruction patching
>> results in valid instruction encodings.  This is done by verifying the output
>> of the patch process against a vector of assembler generated instructions at
>> init time.
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
[...]
>> +	__asm__ __volatile__ (
>> +		"	.irp	shift1, 0, 6, 12, 18\n"
>> +		"	.irp	shift2, 0, 1, 2, 3, 4, 5\n"
>> +		"	add     r1, r2, #(0x41 << (\\shift1 + \\shift2))\n"
>> +		"	.endr\n"
>> +		"	.endr\n"
>
>
> Maybe adding a "add r1, r2 #0x81 << 24" here might be a good thing since
> this is the most used case but missing from the above.
>

Indeed.  I've now replaced this with something a bit more extensive. 
Does the following look better?

+struct patch_test_imm8 {
+       u16     imm;
+       u16     shift;
+       u32     insn;
+};
+
+static void __init __used __naked __patch_test_code_imm8(void)
+{
+       __asm__ __volatile__ (
+
+               /* a single test case */
+               "       .macro          test_one, imm, sft\n"
+               "       .hword          \\imm\n"
+               "       .hword          \\sft\n"
+               "       add             r1, r2, #(\\imm << \\sft)\n"
+               "       .endm\n"
+
+               /* a sequence of tests at 'inc' increments of shift */
+               "       .macro          test_seq, imm, sft, max, inc\n"
+               "       test_one        \\imm, \\sft\n"
+               "       .if             \\sft < \\max\n"
+               "       test_seq        \\imm, (\\sft + \\inc), \\max, 
\\inc\n"
+               "       .endif\n"
+               "       .endm\n"
+
+               /* an empty record to mark the end */
+               "       .macro          test_end\n"
+               "       .hword          0, 0\n"
+               "       .word           0\n"
+               "       .endm\n"
+
+               /* finally generate the test sequences */
+               "       test_seq        0x41, 0, 24, 1\n"
+               "       test_seq        0x81, 0, 24, 2\n"
+               "       test_end\n"
+               : : :
+       );
+}
+

[...]
>> +	u32 test_code_addr = (u32)(&__patch_test_code_imm8);
>> +	u32 *test_code = (u32 *)(test_code_addr & ~0x3);
>
> Why this masking?  With Thumb2 you may find functions starting at
> halfword aligned addresses.  Only the LSB (indicating thumb mode) should
> be masked out.
>

Fixed.  Thanks.

Thanks
-- Cyril.


From cyril at ti.com  Sun Aug 12 13:34:06 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 12 Aug 2012 13:34:06 -0400
Subject: [PATCH v2 03/22] ARM: use late patch framework for phys-virt
 patching
In-Reply-To: <alpine.LFD.2.02.1208112238270.5231@xanadu.home>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-4-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112238270.5231@xanadu.home>
Message-ID: <5027E90E.2000604@ti.com>

On 08/11/12 23:03, Nicolas Pitre wrote:
> On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
>
>> This patch replaces the original physical offset patching implementation
>> with one that uses the newly added patching framework.  In the process, we now
>> unconditionally initialize the __pv_phys_offset and __pv_offset globals in the
>> head.S code.
>
> This last sentence is now wrong.
>

Removed.

[...]
>> -extern unsigned long __pv_phys_offset;
>> -#define PHYS_OFFSET __pv_phys_offset
[...]
>> +#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
>
> What was wrong with the former PHYS_OFFSET = __pv_phys_offset ?
>
> If you really want to have it optimized at run time, you could simply
> use your new stub to patch a mov instruction instead of going through
> __virt_to_phys which uses and add on top of a constant.
>

The intent was to optimize out the load(s) on references to PHYS_OFFSET, 
but is it worth it?  If so, we could go with a patched mov (or two) with 
the necessary endian fixups.  If not, we could revert to 
__pv_phys_offset loads as before.

[...]
>>   	s = find_mod_section(hdr, sechdrs, ".runtime.patch.table");
>>   	if (s)
>>   		runtime_patch((void *)s->sh_addr, s->sh_size);
>
> I missed this in the previous patch, but could you fail the module
> loading by returning an error if runtime_patch() fails?  That would take
> care of not accepting modules that might have been compiled with future
> runtime patching extensions that are not yet supported in an earlier
> kernel.
>

Sure.  Thanks.

> You also should remove the MODULE_ARCH_VERMAGIC_P2V definitions now that
> the corresponding code is no longer there.
>

Hmm...

"rt-patch" needs to be in vermagic to prevent modules built against the 
new code from being loaded on older kernels that used the traditional 
patch code.

"p2v" needs to be in there as well, because it should be possible to 
build without PATCH_PHYS_VIRT, but with RUNTIME_PATCH as and when there 
are other users for this.

Thanks
-- Cyril.


From cyril at ti.com  Sun Aug 12 14:13:57 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 12 Aug 2012 14:13:57 -0400
Subject: [PATCH v2 01/22] ARM: add mechanism for late code patching
In-Reply-To: <alpine.LFD.2.02.1208112220400.5231@xanadu.home>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-2-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112220400.5231@xanadu.home>
Message-ID: <5027F265.4030501@ti.com>

On 08/11/12 22:22, Nicolas Pitre wrote:
> On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
>
>> The original phys_to_virt/virt_to_phys patching implementation relied on early
>> patching prior to MMU initialization.  On PAE systems running out of >4G
>> address space, this would have entailed an additional round of patching after
>> switching over to the high address space.
>>
>> The approach implemented here conceptually extends the original PHYS_OFFSET
>> patching implementation with the introduction of "early" patch stubs.  Early
>> patch code is required to be functional out of the box, even before the patch
>> is applied.  This is implemented by inserting functional (but inefficient)
>> load code into the .runtime.patch.code init section.  Having functional code
>> out of the box then allows us to defer the init time patch application until
>> later in the init sequence.
>>
>> In addition to fitting better with our need for physical address-space
>> switch-over, this implementation should be somewhat more extensible by virtue
>> of its more readable (and hackable) C implementation.  This should prove
>> useful for other similar init time specialization needs, especially in light
>> of our multi-platform kernel initiative.
>>
>> This code has been boot tested in both ARM and Thumb-2 modes on an ARMv7
>> (Cortex-A8) device.
>>
>> Note: the obtuse use of stringified symbols in patch_stub() and
>> early_patch_stub() is intentional.  Theoretically this should have been
>> accomplished with formal operands passed into the asm block, but this requires
>> the use of the 'c' modifier for instantiating the long (e.g. .long %c0).
>> However, the 'c' modifier has been found to ICE certain versions of GCC, and
>> therefore we resort to stringified symbols here.
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>
> Reviewed-by: Nicolas Pitre <nico at linaro.org>
>

Thanks.

I've been looking at the compiler emitted code, and had to make a couple 
of changes to keep things streamlined...

[...]
>> +#define early_patch_imm8(insn, to, from, sym, offset)			\
>> +	early_patch_stub(PATCH_IMM8,					\
>> +			 /* code */					\
>> +			 "ldr	%0, =" __stringify(sym + offset) "\n"	\
>> +			 "ldr	%0, [%0]\n"				\
>> +			 insn " %0, %1, %0\n",				\
>> +			 /* patch_data */				\
>> +			 ".long " __stringify(sym + offset) "\n"	\
>> +			 insn " %0, %1, %2\n",				\
>> +			 : "=&r" (to)					\
>> +			 : "r" (from), "I" (__IMM8), "m" (sym)		\
>> +			 : "cc")

First, the "m" operand modifier for "sym" forces GCC to emit code to 
load the address of the symbol into a register.  I've replaced this with 
"i" (&(sym) to make that go away.  With this, the emitted code doesn't 
contain any such unexpected nonsense.

Second, marking the "to" operand as early clobber makes the compiler 
generate horrid register moves around the assembly block, even when it 
has registers to spare.  Simply adding a temporary variable does a much 
much better job, especially since this temporary register is used only 
in the patched-out "early" code.

Thanks
-- Cyril.


From broonie at opensource.wolfsonmicro.com  Sun Aug 12 14:50:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 12 Aug 2012 19:50:12 +0100
Subject: [PATCH 04/11] MFD: twl4030-audio: Add DT support
In-Reply-To: <5023C0D6.8040600@ti.com>
References: <20120808131356.GS16861@opensource.wolfsonmicro.com>
 <50226CF4.1010202@ti.com>
 <20120808135253.GC16861@opensource.wolfsonmicro.com>
 <502274DA.9020204@ti.com>
 <20120808141849.GA24328@opensource.wolfsonmicro.com>
 <50227837.10400@ti.com>
 <20120808144933.GC24328@opensource.wolfsonmicro.com>
 <50238E8A.5030902@ti.com>
 <20120809103600.GI24328@opensource.wolfsonmicro.com>
 <5023C0D6.8040600@ti.com>
Message-ID: <20120812185012.GB10627@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 04:53:26PM +0300, Peter Ujfalusi wrote:
> On 08/09/2012 01:36 PM, Mark Brown wrote:

> > Is there any actual case where an external mute is supplied via a
> > mechanism other than a GPIO, and if there is would it not either need
> > its own DT property or already need to interact with the driver from
> > code, making the DT property redundant?

> Not with my knowledge. The only board using it is the zoom2 upstream. I know
> other boards (not in upstream) which either uses the internal mute or GPIO.

OK, so we can probably only support GPIO for now then worry about other
external mutes when there's something to work with.


From marex at denx.de  Sun Aug 12 15:14:46 2012
From: marex at denx.de (Marek Vasut)
Date: Sun, 12 Aug 2012 21:14:46 +0200
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
In-Reply-To: <CAMiH66GopNVeKPRQn+KfwRHUoM-Lv8WitX0zAS=Vi=8QAvS-Pw@mail.gmail.com>
References: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
 <201208111610.45107.marex@denx.de>
 <CAMiH66GopNVeKPRQn+KfwRHUoM-Lv8WitX0zAS=Vi=8QAvS-Pw@mail.gmail.com>
Message-ID: <201208122114.46901.marex@denx.de>

Dear Huang Shijie,

[...]

> >> +     this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
> > 
> > devm_
> 
> emm...
> The devm_kzalloc() is the wrong choose in this case. It may makes we
> waste much more memory when the NAND page is 8K.
> 
> Assume the gpmi uses a 8K page nand chip.  The devm_kzalloc() will
> allocate (sizeof(struct devres) + 8K).

Don't forget the malloc header and padding around malloc()'d space. So you're 
behind the 2 * PAGESIZE anyway.

> It's obvious that the size is bigger then the SLUB_MAX_SIZE. So the
> kernel gets 2 with the
> get_order(sizeof(struct devres) + 8K) which means we have to use 4
> memory page for the verify_buf.
> But in actually, we only use 8K memory. So the rest nearly 8K(
> sizeof(struct devres) is very small) memory
> is wasted.
> 
> So I prefer to use the kzalloc() here.
> 
> thanks
> Huang Shijie
> 
> >> +     if (!this->verify_buf)
> >> +             return -ENOMEM;
> >> +
> >> 
> >>       /* Prepare for the BBT scan. */
> >>       ret = gpmi_pre_bbt_scan(this);
> >>       if (ret)
> >> 
> >> @@ -1531,6 +1553,8 @@ void gpmi_nfc_exit(struct gpmi_nand_data *this)
> >> 
> >>  {
> >>  
> >>       nand_release(&this->mtd);
> >>       gpmi_free_dma_buffer(this);
> >> 
> >> +     kfree(this->verify_buf);
> >> +     this->verify_buf = NULL;
> > 
> > Then you won't have to care for this ... I told you at least once before.
> > 
> >>  }
> >>  
> >>  static int __devinit gpmi_nfc_init(struct gpmi_nand_data *this)
> >> 
> >> @@ -1556,6 +1580,7 @@ static int __devinit gpmi_nfc_init(struct
> >> gpmi_nand_data *this) chip->read_byte         = gpmi_read_byte;
> >> 
> >>       chip->read_buf          = gpmi_read_buf;
> >>       chip->write_buf         = gpmi_write_buf;
> >> 
> >> +     chip->verify_buf        = gpmi_verify_buf;
> >> 
> >>       chip->ecc.read_page     = gpmi_ecc_read_page;
> >>       chip->ecc.write_page    = gpmi_ecc_write_page;
> >>       chip->ecc.read_oob      = gpmi_ecc_read_oob;
> >> 
> >> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> >> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h index 1547a60..8ddf115 100644
> >> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> >> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> >> @@ -144,6 +144,7 @@ struct gpmi_nand_data {
> >> 
> >>       /* MTD / NAND */
> >>       struct nand_chip        nand;
> >>       struct mtd_info         mtd;
> >> 
> >> +     uint8_t                 *verify_buf;
> >> 
> >>       /* General-use Variables */
> >>       int                     current_chip;


From cyril at ti.com  Sun Aug 12 19:27:49 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sun, 12 Aug 2012 19:27:49 -0400
Subject: [PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching
In-Reply-To: <alpine.LFD.2.02.1208112316560.5231@xanadu.home>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-6-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112316560.5231@xanadu.home>
Message-ID: <50283BF5.1050908@ti.com>

On 08/11/12 23:39, Nicolas Pitre wrote:
> On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
>
>> This patch adds support for 64-bit physical addresses in virt_to_phys()
>> patching.  This does not do real 64-bit add/sub, but instead patches in the
>> upper 32-bits of the phys_offset directly into the output of virt_to_phys.
>>
>> There is no corresponding change on the phys_to_virt() side, because
>> computations on the upper 32-bits would be discarded anyway.
>>
>> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
>> ---
>>   arch/arm/include/asm/memory.h |   22 ++++++++++++++++++----
>>   arch/arm/kernel/head.S        |    4 ++++
>>   arch/arm/kernel/setup.c       |    2 +-
>>   3 files changed, 23 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
>> index 81e1714..dc5fbf3 100644
>> --- a/arch/arm/include/asm/memory.h
>> +++ b/arch/arm/include/asm/memory.h
>> @@ -154,14 +154,28 @@
>>   #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
>>
>>   extern unsigned long	__pv_offset;
>> -extern unsigned long	__pv_phys_offset;
>> +extern phys_addr_t	__pv_phys_offset;
>>   #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
>>
>>   static inline phys_addr_t __virt_to_phys(unsigned long x)
>>   {
>> -	unsigned long t;
>> -	early_patch_imm8("add", t, x, __pv_offset, 0);
>> -	return t;
>> +	unsigned long tlo, thi;
>> +
>> +	early_patch_imm8("add", tlo, x, __pv_offset, 0);
>> +
>> +#ifdef CONFIG_ARM_LPAE
>> +	/*
>> +	 * On LPAE, we do not _need_ to do 64-bit arithmetic because the high
>> +	 * order 32 bits are never changed by the phys-virt offset.  We simply
>> +	 * patch in the high order physical address bits instead.
>> +	 */
>> +#ifdef __ARMEB__
>> +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
>> +#else
>> +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
>> +#endif
>> +#endif
>> +	return (u64)tlo | (u64)thi << 32;
>>   }
>
> Hmmm...  I'm afraid this is going to be suboptimal when LPAE is not
> selected.
>

I understand your concern, but I don't see the sub-optimality.  I tested 
the following function with GCC versions 4.3.3 and 4.7.  This is after 
the other changes that I mentioned in my previous email, but with the 
__virt_to_phys() code itself unchanged:

phys_addr_t ____test_virt_to_phys(unsigned long addr)
{
         return __virt_to_phys(addr);
}

The resulting code in both cases looks like:

<____test_virt_to_phys>:
	b       c04f0528
	bx      lr

[the branch of course gets patched to an add]

> First of all, you do not need to cast tlo to a u64 in the return value.
>

True enough.

> Then, I'm not sure if the compiler is smart enough to see that the
> returned value is a phys_addr_t which can be a u32, and in this case the
> (u64)thi << 32 is going to be truncated right away, and therefore there
> is no point in emiting the corresponding instructions.
>

In this case, it appears to be smart enough.  However, I agree that 
relying on compiler smarts is probably not the best thing for us to do.

> Furthermore, if LPAE is not defined, then thi never gets initialized and
> should produce a warning. Did you test compilation of the code with LPAE
> turned off?
>

Sure.  One of our test platforms is non-LPAE.  The compiler does not 
produce warnings on this, and this is consistent across both compiler 
versions.

> I'd prefer something like this where more stuff is validated by the
> compiler:
>
> static inline phys_addr_t __virt_to_phys(unsigned long x)
> {
> 	unsigned long tlo, thi;
> 	phys_addr_t ret;
>
> 	early_patch_imm8("add", tlo, x, __pv_offset, 0);
> 	ret = tlo;
>
> 	if (sizeof(phys_addr_t) > 4) {
> #ifdef __ARMEB__
> 		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
> #else
> 		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
> #endif
> 		ret |= ((u64)thi) << 32;
> 	}
>
> 	return ret);
> }
>
> This should let the compiler optimize things whether LPAE is enabledor
> not while validating both cases.
>

Agreed on the principal, but more below...


I've meanwhile been chasing down another problem - the code generated 
for the LPAE case.  The original code resulted in the following:

<____test_virt_to_phys>:
         mov     r2, #0
         b       c01bc800	# patch: add r1, r0, __pv_offset
         b       c01bc810	# patch: mov r0, __phys_offset_high
         orr     r2, r2, r1
         mov     r3, r0
         mov     r1, r3
         mov     r0, r2
         bx      lr

Yikes! This code does a bunch of futile register shuffling and a 
pointless or, all in the name of generating the result in a 64-bit 
register-pair from the 32-bit halves.

In order to get past this, I tried adding operand qualifiers (R = upper 
32-bits, Q = lower 32-bits) in the patch macros, in the hope that 
treating these as native 64-bit register pairs would eliminate the need 
to shuffle them around after the inline assembly blocks.  This then 
allows us to implement __virt_to_phys() as follows:

static inline phys_addr_t __virt_to_phys(unsigned long x)
{
         phys_addr_t t;

         if (sizeof(t) == 4) {
		t = x;
                 early_patch_imm8("add", t, "", t, __pv_offset, 0);
                 return t;
         }

         /*
          * On LPAE, we do not _need_ to do 64-bit arithmetic because
          * the high order 32 bits are never changed by the phys-virt
          * offset.  We simply patch in the high order physical address
          * bits instead.
          *
          * Note: the mov _must_ be first here.  From the compiler's
          * perspective, this is the initializer for the variable. The
          * mov itself initializes only the upper half. The subsequent
          * add treats t as a read/write operand and initializes the
          * lower half.
          */
#ifdef __ARMEB__
         early_patch_imm8_mov("mov", t, "R", __pv_phys_offset, 0);
#else
         early_patch_imm8_mov("mov", t, "R", __pv_phys_offset, 4);
#endif
         early_patch_imm8("add", t, "Q", x, __pv_offset, 0);

         return t;
}

With this, we get significantly better looking generated code:

<____test_virt_to_phys>:
	b       c01d519c	# patch: mov r3, __phys_offset_high
	b       c01d51ac	# patch: add r2, r0, __phys_offset_high
	mov     r0, r2
	mov     r1, r3
	bx      lr

This is about as far along as I've been able to proceed.  I still 
haven't figured out a way to get it to patch in place without an extra 
register pair.

Overall, this is still a bit too kludgy for my liking.  In particular, 
the read/write operand forces add/sub/... users to initialize the result 
variable.  I am currently leaning towards adding native support for 
64-bit operations in the runtime patch code, instead of having to hack 
around it with 32-bit primitives.  Better ideas, any one?

Thanks
-- Cyril.


From b32955 at freescale.com  Sun Aug 12 22:21:15 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 13 Aug 2012 10:21:15 +0800
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208122114.46901.marex@denx.de>
References: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
 <201208111610.45107.marex@denx.de>
 <CAMiH66GopNVeKPRQn+KfwRHUoM-Lv8WitX0zAS=Vi=8QAvS-Pw@mail.gmail.com>
 <201208122114.46901.marex@denx.de>
Message-ID: <5028649B.10109@freescale.com>

? 2012?08?13? 03:14, Marek Vasut ??:
> Don't forget the malloc header and padding around malloc()'d space. So you're
> behind the 2 * PAGESIZE anyway.
If we use the kzalloc(). There is no malloc header and padding. We get 
the memory by
the __get_free_pages(). So we do _NOT_ behind the 2*PAGE. We use exactly 
the 2*PAGE.


thanks
Huang Shijie



From b32955 at freescale.com  Sun Aug 12 22:35:14 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 13 Aug 2012 10:35:14 +0800
Subject: [PATCH v4] mtd: gpmi: add NAND write verify support
In-Reply-To: <201208122114.46901.marex@denx.de>
References: <1344737275-18342-1-git-send-email-shijie8@gmail.com>
 <201208111610.45107.marex@denx.de>
 <CAMiH66GopNVeKPRQn+KfwRHUoM-Lv8WitX0zAS=Vi=8QAvS-Pw@mail.gmail.com>
 <201208122114.46901.marex@denx.de>
Message-ID: <502867E2.8020405@freescale.com>

? 2012?08?13? 03:14, Marek Vasut ??:
> Don't forget the malloc header and padding around malloc()'d space. So you're
> behind the 2 * PAGESIZE anyway.
>
sorry, I misunderstood your meaning. My meaning is even the SLUB maybe 
costs some extra memory, it still save much memory
then we use the devm_kzalloc().

thanks
Huang Shijie



From festevam at gmail.com  Sun Aug 12 23:06:49 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 13 Aug 2012 00:06:49 -0300
Subject: [PATCH] clk: mxs: Register USB clocks for mx23
In-Reply-To: <20120806030014.GB22302@S2101-09.ap.freescale.net>
References: <1340148392-9847-1-git-send-email-festevam@gmail.com>
 <20120620143830.GF2253@S2101-09.ap.freescale.net>
 <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>
 <20120806030014.GB22302@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5AME0NXarMF_rarYJeQ4-rGc+DpV7nvL4OeQj+LfkLLQw@mail.gmail.com>

Shawn,

On Mon, Aug 6, 2012 at 12:00 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Probably, no, as I plan to freeze the addition to clkdev lookup table
> and replace it with DT clock lookup.

Could you please suggest how can I register the USB clocks for mx23?
Any example I can refer to implement a "DT clock lookup"?

Regards,

Fabio Estevam


From nicolas.pitre at linaro.org  Sun Aug 12 23:19:48 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 23:19:48 -0400 (EDT)
Subject: [PATCH v2 02/22] ARM: add self test for runtime patch
 mechanism
In-Reply-To: <5027DAAF.2060406@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-3-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112226310.5231@xanadu.home> <5027DAAF.2060406@ti.com>
Message-ID: <alpine.LFD.2.02.1208122314160.5231@xanadu.home>

On Sun, 12 Aug 2012, Cyril Chemparathy wrote:

> On 08/11/12 22:35, Nicolas Pitre wrote:
> > On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
> > 
> > > This patch adds basic sanity tests to ensure that the instruction patching
> > > results in valid instruction encodings.  This is done by verifying the
> > > output
> > > of the patch process against a vector of assembler generated instructions
> > > at
> > > init time.
> > > 
> > > Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> > > ---
> [...]
> > > +	__asm__ __volatile__ (
> > > +		"	.irp	shift1, 0, 6, 12, 18\n"
> > > +		"	.irp	shift2, 0, 1, 2, 3, 4, 5\n"
> > > +		"	add     r1, r2, #(0x41 << (\\shift1 + \\shift2))\n"
> > > +		"	.endr\n"
> > > +		"	.endr\n"
> > 
> > 
> > Maybe adding a "add r1, r2 #0x81 << 24" here might be a good thing since
> > this is the most used case but missing from the above.
> > 
> 
> Indeed.  I've now replaced this with something a bit more extensive. Does the
> following look better?
> 
> +struct patch_test_imm8 {
> +       u16     imm;
> +       u16     shift;
> +       u32     insn;
> +};
> +
> +static void __init __used __naked __patch_test_code_imm8(void)
> +{
> +       __asm__ __volatile__ (
> +
> +               /* a single test case */
> +               "       .macro          test_one, imm, sft\n"
> +               "       .hword          \\imm\n"
> +               "       .hword          \\sft\n"
> +               "       add             r1, r2, #(\\imm << \\sft)\n"
> +               "       .endm\n"
> +
> +               /* a sequence of tests at 'inc' increments of shift */
> +               "       .macro          test_seq, imm, sft, max, inc\n"
> +               "       test_one        \\imm, \\sft\n"
> +               "       .if             \\sft < \\max\n"
> +               "       test_seq        \\imm, (\\sft + \\inc), \\max,
> \\inc\n"
> +               "       .endif\n"
> +               "       .endm\n"
> +
> +               /* an empty record to mark the end */
> +               "       .macro          test_end\n"
> +               "       .hword          0, 0\n"
> +               "       .word           0\n"
> +               "       .endm\n"
> +
> +               /* finally generate the test sequences */
> +               "       test_seq        0x41, 0, 24, 1\n"
> +               "       test_seq        0x81, 0, 24, 2\n"
> +               "       test_end\n"
> +               : : :
> +       );
> +}

Yes, this is certainly quite extensive.  :-)


Nicolas


From nicolas.pitre at linaro.org  Sun Aug 12 23:32:44 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 12 Aug 2012 23:32:44 -0400 (EDT)
Subject: [PATCH v2 03/22] ARM: use late patch framework for phys-virt
 patching
In-Reply-To: <5027E90E.2000604@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-4-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112238270.5231@xanadu.home> <5027E90E.2000604@ti.com>
Message-ID: <alpine.LFD.2.02.1208122320310.5231@xanadu.home>

On Sun, 12 Aug 2012, Cyril Chemparathy wrote:

> On 08/11/12 23:03, Nicolas Pitre wrote:
> > On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
> > 
> > > -extern unsigned long __pv_phys_offset;
> > > -#define PHYS_OFFSET __pv_phys_offset
> [...]
> > > +#define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
> > 
> > What was wrong with the former PHYS_OFFSET = __pv_phys_offset ?
> > 
> > If you really want to have it optimized at run time, you could simply
> > use your new stub to patch a mov instruction instead of going through
> > __virt_to_phys which uses and add on top of a constant.
> > 
> 
> The intent was to optimize out the load(s) on references to PHYS_OFFSET, but
> is it worth it?  If so, we could go with a patched mov (or two) with the
> necessary endian fixups.  If not, we could revert to __pv_phys_offset loads as
> before.

If you want to do better than the load, then you'd better go all the way 
with the patched move.

> > You also should remove the MODULE_ARCH_VERMAGIC_P2V definitions now that
> > the corresponding code is no longer there.
> > 
> 
> Hmm...
> 
> "rt-patch" needs to be in vermagic to prevent modules built against the new
> code from being loaded on older kernels that used the traditional patch code.

Right.

> "p2v" needs to be in there as well, because it should be possible to build
> without PATCH_PHYS_VIRT, but with RUNTIME_PATCH as and when there are other
> users for this.

That doesn't matter if there are other users.  As soon as there is a 
.init.runtime_patch_table that needs to be processed then "rt-patch" 
flags it.  Whether this is used for PATCH_PHYS_VIRT or other purposes is 
irrelevant.

However there isn't any pv_table anymore, so "p2v" should go as there is 
no more code to process those tables if they're ever encountered.


Nicolas


From nicolas.pitre at linaro.org  Mon Aug 13 00:03:47 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 13 Aug 2012 00:03:47 -0400 (EDT)
Subject: [PATCH v2 05/22] ARM: LPAE: support 64-bit virt_to_phys patching
In-Reply-To: <50283BF5.1050908@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
 <1344648306-15619-6-git-send-email-cyril@ti.com>
 <alpine.LFD.2.02.1208112316560.5231@xanadu.home> <50283BF5.1050908@ti.com>
Message-ID: <alpine.LFD.2.02.1208122336260.5231@xanadu.home>

On Sun, 12 Aug 2012, Cyril Chemparathy wrote:

> On 08/11/12 23:39, Nicolas Pitre wrote:
> > On Fri, 10 Aug 2012, Cyril Chemparathy wrote:
> > 
> > > This patch adds support for 64-bit physical addresses in virt_to_phys()
> > > patching.  This does not do real 64-bit add/sub, but instead patches in
> > > the
> > > upper 32-bits of the phys_offset directly into the output of virt_to_phys.
> > > 
> > > There is no corresponding change on the phys_to_virt() side, because
> > > computations on the upper 32-bits would be discarded anyway.
> > > 
> > > Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> > > ---
> > >   arch/arm/include/asm/memory.h |   22 ++++++++++++++++++----
> > >   arch/arm/kernel/head.S        |    4 ++++
> > >   arch/arm/kernel/setup.c       |    2 +-
> > >   3 files changed, 23 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> > > index 81e1714..dc5fbf3 100644
> > > --- a/arch/arm/include/asm/memory.h
> > > +++ b/arch/arm/include/asm/memory.h
> > > @@ -154,14 +154,28 @@
> > >   #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
> > > 
> > >   extern unsigned long	__pv_offset;
> > > -extern unsigned long	__pv_phys_offset;
> > > +extern phys_addr_t	__pv_phys_offset;
> > >   #define PHYS_OFFSET	__virt_to_phys(PAGE_OFFSET)
> > > 
> > >   static inline phys_addr_t __virt_to_phys(unsigned long x)
> > >   {
> > > -	unsigned long t;
> > > -	early_patch_imm8("add", t, x, __pv_offset, 0);
> > > -	return t;
> > > +	unsigned long tlo, thi;
> > > +
> > > +	early_patch_imm8("add", tlo, x, __pv_offset, 0);
> > > +
> > > +#ifdef CONFIG_ARM_LPAE
> > > +	/*
> > > +	 * On LPAE, we do not _need_ to do 64-bit arithmetic because the high
> > > +	 * order 32 bits are never changed by the phys-virt offset.  We simply
> > > +	 * patch in the high order physical address bits instead.
> > > +	 */
> > > +#ifdef __ARMEB__
> > > +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
> > > +#else
> > > +	early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
> > > +#endif
> > > +#endif
> > > +	return (u64)tlo | (u64)thi << 32;
> > >   }
> > 
> > Hmmm...  I'm afraid this is going to be suboptimal when LPAE is not
> > selected.
> > 
> 
> I understand your concern, but I don't see the sub-optimality.  I tested the
> following function with GCC versions 4.3.3 and 4.7.  This is after the other
> changes that I mentioned in my previous email, but with the __virt_to_phys()
> code itself unchanged:
> 
> phys_addr_t ____test_virt_to_phys(unsigned long addr)
> {
>         return __virt_to_phys(addr);
> }
> 
> The resulting code in both cases looks like:
> 
> <____test_virt_to_phys>:
> 	b       c04f0528
> 	bx      lr
> 
> [the branch of course gets patched to an add]

OK.  Please add such information and results in your commit log.

> > First of all, you do not need to cast tlo to a u64 in the return value.
> > 
> 
> True enough.
> 
> > Then, I'm not sure if the compiler is smart enough to see that the
> > returned value is a phys_addr_t which can be a u32, and in this case the
> > (u64)thi << 32 is going to be truncated right away, and therefore there
> > is no point in emiting the corresponding instructions.
> > 
> 
> In this case, it appears to be smart enough.  However, I agree that relying on
> compiler smarts is probably not the best thing for us to do.

Well, we do rely on a lot of compiler smarts in the kernel.  As long as 
sufficiently old compiler versions do get it right then it should be 
fine.

> > Furthermore, if LPAE is not defined, then thi never gets initialized and
> > should produce a warning. Did you test compilation of the code with LPAE
> > turned off?
> > 
> 
> Sure.  One of our test platforms is non-LPAE.  The compiler does not produce
> warnings on this, and this is consistent across both compiler versions.

That is odd.  I still prefer my version nevertheless so to avoid this 
potential issue in the future.

> > I'd prefer something like this where more stuff is validated by the
> > compiler:
> > 
> > static inline phys_addr_t __virt_to_phys(unsigned long x)
> > {
> > 	unsigned long tlo, thi;
> > 	phys_addr_t ret;
> > 
> > 	early_patch_imm8("add", tlo, x, __pv_offset, 0);
> > 	ret = tlo;
> > 
> > 	if (sizeof(phys_addr_t) > 4) {
> > #ifdef __ARMEB__
> > 		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 0);
> > #else
> > 		early_patch_imm8_mov("mov", thi, __pv_phys_offset, 4);
> > #endif
> > 		ret |= ((u64)thi) << 32;
> > 	}
> > 
> > 	return ret);
> > }
> > 
> > This should let the compiler optimize things whether LPAE is enabledor
> > not while validating both cases.
> > 
> 
> Agreed on the principal, but more below...
> 
> 
> I've meanwhile been chasing down another problem - the code generated for the
> LPAE case.  The original code resulted in the following:
> 
> <____test_virt_to_phys>:
>         mov     r2, #0
>         b       c01bc800	# patch: add r1, r0, __pv_offset
>         b       c01bc810	# patch: mov r0, __phys_offset_high
>         orr     r2, r2, r1
>         mov     r3, r0
>         mov     r1, r3
>         mov     r0, r2
>         bx      lr
> 
> Yikes! This code does a bunch of futile register shuffling and a pointless or,
> all in the name of generating the result in a 64-bit register-pair from the
> 32-bit halves.
> 
> In order to get past this, I tried adding operand qualifiers (R = upper
> 32-bits, Q = lower 32-bits) in the patch macros, in the hope that treating
> these as native 64-bit register pairs would eliminate the need to shuffle them
> around after the inline assembly blocks.  This then allows us to implement
> __virt_to_phys() as follows:
> 
> static inline phys_addr_t __virt_to_phys(unsigned long x)
> {
>         phys_addr_t t;
> 
>         if (sizeof(t) == 4) {
> 		t = x;
>                 early_patch_imm8("add", t, "", t, __pv_offset, 0);
>                 return t;
>         }
> 
>         /*
>          * On LPAE, we do not _need_ to do 64-bit arithmetic because
>          * the high order 32 bits are never changed by the phys-virt
>          * offset.  We simply patch in the high order physical address
>          * bits instead.
>          *
>          * Note: the mov _must_ be first here.  From the compiler's
>          * perspective, this is the initializer for the variable. The
>          * mov itself initializes only the upper half. The subsequent
>          * add treats t as a read/write operand and initializes the
>          * lower half.
>          */
> #ifdef __ARMEB__
>         early_patch_imm8_mov("mov", t, "R", __pv_phys_offset, 0);
> #else
>         early_patch_imm8_mov("mov", t, "R", __pv_phys_offset, 4);
> #endif
>         early_patch_imm8("add", t, "Q", x, __pv_offset, 0);
> 
>         return t;
> }
> 
> With this, we get significantly better looking generated code:
> 
> <____test_virt_to_phys>:
> 	b       c01d519c	# patch: mov r3, __phys_offset_high
> 	b       c01d51ac	# patch: add r2, r0, __phys_offset_high
> 	mov     r0, r2
> 	mov     r1, r3
> 	bx      lr
> 
> This is about as far along as I've been able to proceed.  I still haven't
> figured out a way to get it to patch in place without an extra register pair.
> 
> Overall, this is still a bit too kludgy for my liking.  In particular, the
> read/write operand forces add/sub/... users to initialize the result variable.
> I am currently leaning towards adding native support for 64-bit operations in
> the runtime patch code, instead of having to hack around it with 32-bit
> primitives.  Better ideas, any one?

The best I've come up with is this:

//typedef unsigned long phys_addr_t;
typedef unsigned long long phys_addr_t;

phys_addr_t __virt_to_phys(unsigned long v)
{
	phys_addr_t p;

	if (sizeof(phys_addr_t) > 4) {
		asm ("add %Q0, %1, #PV_OFFSET" : "=r" (p) : "r" (v));
		asm ("mov %R0, #PHYS_HIGHBITS" : "+r" (p));
	} else {
		asm ("add %0, %1, #PV_OFFSET" : "=r" (p) : "r" (v));
	}

	return p;
}

The add is done first as this reduce the life span of the v variable.  
Because p is listed as an early clobber, then in theory the register 
holding v could be used to store the low part of p right away.  If you 
put the mov first then you can't do that especially on big endian.

It seems that there is no clean way to combine the LPAE and non LPAE 
cases.


Nicolas


From anilkumar at ti.com  Mon Aug 13 00:33:59 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Mon, 13 Aug 2012 04:33:59 +0000
Subject: [PATCH RESEND v2 1/2] arm/dts: Add AM33XX basic pinctrl support
In-Reply-To: <50225618.9070501@ti.com>
References: <1343144719-26352-1-git-send-email-anilkumar@ti.com>
 <1343144719-26352-2-git-send-email-anilkumar@ti.com>
 <50125B1C.8000209@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA06E4B@DBDE01.ent.ti.com>
 <50225618.9070501@ti.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA10824@DBDE01.ent.ti.com>

Peter,

On Wed, Aug 08, 2012 at 17:35:44, Ujfalusi, Peter wrote:
> On 07/31/2012 04:37 PM, AnilKumar, Chimata wrote:
> >> I'm just curious about the size here: how it ended up as 0x0338?
> >> While looking at the TRM of AM335x I can come up with 0x0238 (0x44e10800 -
> >> 0x44e10a38), but I don't see any sings of the remaining 0x0100 to be
> >> documented at least.
> > 
> > No, pinmux registers are available till 0x44E10B38, look at AM335x latest TRM
> > or pinmux utility (we cannot find the exact offsets but pins we can find after
> > 0x0A38, conf_ddr_resetn) at http://www.ti.com/tool/pinmuxtool
> 
> I have looked at the latest TRM (Rev F, SPRUH73F -  public TRM) and there is
> not mention of registers between 0x0a34 and 0x0e00.
> I can not even find any reference of conf_ddr_resetn register either in the TRM.
> I can not check with the pinmuxtool since it is crashing with wine under Linux.
> There could be registers after 0x0a34, but they are not publicly documented...
> 

Thanks for pointing this, I was referring older version (Rev C) of TRM which have
the details which is not present in latest TRM. These pins are dedicated ones so
pinmuxing is not required. I will submit new version.

Thanks
AnilKumar


From dedekind1 at gmail.com  Mon Aug 13 00:44:43 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 13 Aug 2012 07:44:43 +0300
Subject: [PATCH v2] mtd: gpmi: add NAND write verify support
In-Reply-To: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
References: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
Message-ID: <CAF4G-tKN683_EQCGcG4G8jMU5K6TamaHUv__3ugGUoEg_LPrcQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 6:25 PM, Huang Shijie <shijie8 at gmail.com> wrote:
> Add NAND write verify support in gpmi-nand driver.
>
> This patch fixes a kernel crash when we select
> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:

I would just kill ONFIG_MTD_NAND_VERIFY_WRITE entirely. Some drivers
do not support it and it does not work for sub-pages for long time.
Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature.

I am also removing the -stable mailing list - ne need to spam it.

-- 
Best Regards,
Artem Bityutskiy (???????? ?????)


From b32955 at freescale.com  Mon Aug 13 01:09:34 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 13 Aug 2012 13:09:34 +0800
Subject: [PATCH v2] mtd: gpmi: add NAND write verify support
In-Reply-To: <CAF4G-tKN683_EQCGcG4G8jMU5K6TamaHUv__3ugGUoEg_LPrcQ@mail.gmail.com>
References: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
 <CAF4G-tKN683_EQCGcG4G8jMU5K6TamaHUv__3ugGUoEg_LPrcQ@mail.gmail.com>
Message-ID: <50288C0E.5060400@freescale.com>

? 2012?08?13? 12:44, Artem Bityutskiy ??:
> On Sat, Aug 11, 2012 at 6:25 PM, Huang Shijie<shijie8 at gmail.com>  wrote:
>> Add NAND write verify support in gpmi-nand driver.
>>
>> This patch fixes a kernel crash when we select
>> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
> I would just kill ONFIG_MTD_NAND_VERIFY_WRITE entirely. Some drivers
> do not support it and it does not work for sub-pages for long time.
> Both UBI and JFFS2 are able to read verify what they wrote already.
> There are also MTD tests which do this verification. So I think there
> is no reason to keep this in the NAND layer, let alone wasting RAM in
> the driver to support this feature.
>
> I am also removing the -stable mailing list - ne need to spam it.
>
thanks a lot. Maybe we should send a patch to remove the 
CONFIG_MTD_NAND_VERIFY_WRITE feature entirely.

Huang Shijie



From plagnioj at jcrosoft.com  Mon Aug 13 01:18:09 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 13 Aug 2012 07:18:09 +0200
Subject: [PATCH 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs
In-Reply-To: <1344705034-18173-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1344705034-18173-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120813051809.GA8836@game.jcrosoft.org>

On 19:10 Sat 11 Aug     , Thomas Petazzoni wrote:
> This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
> and is designed to be compatible with all Marvell EBU SoCs: Orion,
> Kirkwood, Dove, Armada 370/XP and Discovery.
> 
> It has been successfully tested on Dove and Armada XP at the moment.
> 
> Compared to the plat-orion driver, this new driver has the following
> added benefits:
> 
>  *) Support for Armada 370 and Armada XP
>  *) It is integrated with the mvebu pinctrl driver so that GPIO pins
>     are properly muxed, and the GPIO driver knows which GPIO pins are
>     output-only or input-only.
>  *) Properly placed in drivers/gpio
>  *) More extensible mechanism to support platform differences. The
>     plat-orion driver uses a simple mask-offset DT property, which
>     works fine for Discovery MV78200 but not for Armada XP. The new
>     driver uses different compatible strings to identify the different
>     variants of the GPIO controllers.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
>  drivers/gpio/Kconfig      |    6 +
>  drivers/gpio/Makefile     |    1 +
>  drivers/gpio/gpio-mvebu.c |  656 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 663 insertions(+)
>  create mode 100644 drivers/gpio/gpio-mvebu.c
> 
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index b16c8a7..993b0c4 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -150,6 +150,12 @@ config GPIO_MSM_V2
>  	  Qualcomm MSM chips.  Most of the pins on the MSM can be
>  	  selected for GPIO, and are controlled by this driver.
>  
> +config GPIO_MVEBU
> +	def_bool y
> +	depends on ARCH_MVEBU
> +	select GPIO_GENERIC
> +	select GENERIC_IRQ_CHIP
> +
>  config GPIO_MXC
>  	def_bool y
>  	depends on ARCH_MXC
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 153cace..1a33e67 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
>  obj-$(CONFIG_GPIO_MSIC)		+= gpio-msic.o
>  obj-$(CONFIG_GPIO_MSM_V1)	+= gpio-msm-v1.o
>  obj-$(CONFIG_GPIO_MSM_V2)	+= gpio-msm-v2.o
> +obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
>  obj-$(CONFIG_GPIO_MXC)		+= gpio-mxc.o
>  obj-$(CONFIG_GPIO_MXS)		+= gpio-mxs.o
>  obj-$(CONFIG_ARCH_OMAP)		+= gpio-omap.o
> diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
> new file mode 100644
> index 0000000..892e3f1
> --- /dev/null
> +++ b/drivers/gpio/gpio-mvebu.c
> @@ -0,0 +1,656 @@
> +/*
> + * GPIO driver for Marvell SoCs
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> + * Andrew Lunn <andrew at lunn.ch>
> + * Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + *
> + * This driver is a fairly straightforward GPIO driver for the
> + * complete family of Marvell EBU SoC platforms (Orion, Dove,
> + * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
> + * driver is the different register layout that exists between the
> + * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
> + * platforms (MV78200 from the Discovery family and the Armada
> + * XP). Therefore, this driver handles three variants of the GPIO
> + * block:
> + * - the basic variant, called "orion-gpio", with the simplest
> + *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
> + *   non-SMP Discovery systems
> + * - the mv78200 variant for MV78200 Discovery systems. This variant
> + *   turns the edge mask and level mask registers into CPU0 edge
> + *   mask/level mask registers, and adds CPU1 edge mask/level mask
> + *   registers.
> + * - the armadaxp variant for Armada XP systems. This variant keeps
> + *   the normal cause/edge mask/level mask registers when the global
> + *   interrupts are used, but adds per-CPU cause/edge mask/level mask
> + *   registers n a separate memory area for the per-CPU GPIO
> + *   interrupts.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/gpio.h>
> +#include <linux/irq.h>
> +#include <linux/slab.h>
> +#include <linux/irqdomain.h>
> +#include <linux/io.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/consumer.h>
> +
> +/*
> + * GPIO unit register offsets.
> + */
> +#define GPIO_OUT_OFF		0x0000
> +#define GPIO_IO_CONF_OFF	0x0004
> +#define GPIO_BLINK_EN_OFF	0x0008
> +#define GPIO_IN_POL_OFF		0x000c
> +#define GPIO_DATA_IN_OFF	0x0010
> +#define GPIO_EDGE_CAUSE_OFF	0x0014
> +#define GPIO_EDGE_MASK_OFF	0x0018
> +#define GPIO_LEVEL_MASK_OFF	0x001c
> +
> +/* The MV78200 has per-CPU registers for edge mask and level mask */
> +#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
> +#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
> +
> +/* The Armada XP has per-CPU registers for interrupt cause, interrupt
> + * mask and interrupt level mask. Those are relative to the
> + * percpu_membase. */
> +#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
> +#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
> +#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
> +
> +#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
> +#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
> +#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
> +
> +struct mvebu_gpio_chip {
> +	struct gpio_chip   chip;
> +	spinlock_t	   lock;
> +	void __iomem	  *membase;
> +	void __iomem	  *percpu_membase;
> +	unsigned int       irqbase;
> +	struct irq_domain *domain;
> +	int                soc_variant;
> +};
> +
> +/*
> + * Common functions to all SoCs
> + */
> +static void __iomem *GPIO_OUT(struct mvebu_gpio_chip *mvchip)
please use inline and do not use upper case for function

in the code pelease use relaxed readl/writel
> +{
> +	return mvchip->membase + GPIO_OUT_OFF;
> +}
> +
> +static void __iomem *GPIO_IO_CONF(struct mvebu_gpio_chip *mvchip)
> +{
> +	return mvchip->membase + GPIO_IO_CONF_OFF;
> +}
> +
> +static void __iomem *GPIO_IN_POL(struct mvebu_gpio_chip *mvchip)
> +{
> +	return mvchip->membase + GPIO_IN_POL_OFF;
> +}
> +
> +static void __iomem *GPIO_DATA_IN(struct mvebu_gpio_chip *mvchip)
> +{
> +	return mvchip->membase + GPIO_DATA_IN_OFF;
> +}
> +
> +static void __iomem *GPIO_EDGE_CAUSE(struct mvebu_gpio_chip *mvchip)
> +{
> +	int cpu;
> +
> +	switch(mvchip->soc_variant) {
> +	case MVEBU_GPIO_SOC_VARIANT_ORION:
> +	case MVEBU_GPIO_SOC_VARIANT_MV78200:
> +		return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
> +	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
> +		cpu = smp_processor_id();
> +		return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
> +	default:
> +		BUG();
> +	}
> +}
> +
> +
> +static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
> +{
> +	struct mvebu_gpio_chip *mvchip =
> +		container_of(chip, struct mvebu_gpio_chip, chip);
> +	unsigned long flags;
> +	int ret;
> +	u32 u;
> +
> +	/* Check with the pinctrl driver whether this pin is usable as
> +	 * an input GPIO */
> +	ret = pinctrl_gpio_direction_input(chip->base + pin);
this will de the configuration
> +	if (ret)
> +		return ret;
> +
> +	spin_lock_irqsave(&mvchip->lock, flags);
> +	u = readl(GPIO_IO_CONF(mvchip));
> +	u |= 1 << pin;
> +	writel(u, GPIO_IO_CONF(mvchip));
why this?
> +	spin_unlock_irqrestore(&mvchip->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
> +				       int value)
> +{
> +	struct mvebu_gpio_chip *mvchip =
> +		container_of(chip, struct mvebu_gpio_chip, chip);
> +	unsigned long flags;
> +	int ret;
> +	u32 u;
> +
> +	/* Check with the pinctrl driver whether this pin is usable as
> +	 * an output GPIO */
> +	ret = pinctrl_gpio_direction_output(chip->base + pin);
> +	if (ret)
> +		return ret;
> +
> +	spin_lock_irqsave(&mvchip->lock, flags);
> +	u = readl(GPIO_IO_CONF(mvchip));
> +	u &= ~(1 << pin);
> +	writel(u, GPIO_IO_CONF(mvchip));
> +	spin_unlock_irqrestore(&mvchip->lock, flags);
> +
> +	return 0;
> +}
> +

 +
> +	/* Check if we need to change chip and handler */
> +	if (!(ct->type & type))
> +		if (irq_setup_alt_chip(d, type))
> +			return -EINVAL;
> +
> +	/*
> +	 * Configure interrupt polarity.
> +	 */
> +	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
> +		u = readl(GPIO_IN_POL(mvchip));
> +		u &= ~(1 << pin);
> +		writel(u, GPIO_IN_POL(mvchip));
> +	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
> +		u = readl(GPIO_IN_POL(mvchip));
> +		u |= 1 << pin;
> +		writel(u, GPIO_IN_POL(mvchip));
> +	} else if (type == IRQ_TYPE_EDGE_BOTH) {
> +		u32 v;
switch will make the code cleaner
> +
> +		v = readl(GPIO_IN_POL(mvchip)) ^ readl(GPIO_DATA_IN(mvchip));
> +
> +		/*
> +		 * set initial polarity based on current input level
> +		 */
> +		u = readl(GPIO_IN_POL(mvchip));
> +		if (v & (1 << pin))
> +			u |= 1 << pin;		/* falling */
> +		else
> +			u &= ~(1 << pin);	/* rising */
> +		writel(u, GPIO_IN_POL(mvchip));
> +	}
> +	return 0;
> +}
> +
> +static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> +{
> +	struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
> +	u32 cause, type;
> +	int i;
> +
> +	if (mvchip == NULL)
> +		return;
> +
> +	cause = readl(GPIO_DATA_IN(mvchip)) & readl(GPIO_LEVEL_MASK(mvchip));
> +	cause |= readl(GPIO_EDGE_CAUSE(mvchip)) & readl(GPIO_EDGE_MASK(mvchip));
> +
> +	for (i = 0; i < mvchip->chip.ngpio; i++) {
> +		int irq;
> +
> +		irq = mvchip->irqbase + i;
> +
> +		if (!(cause & (1 << i)))
> +			continue;
> +
> +		type = irqd_get_trigger_type(irq_get_irq_data(irq));
> +		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
> +			/* Swap polarity (race with GPIO line) */
> +			u32 polarity;
> +
> +			polarity = readl(GPIO_IN_POL(mvchip));
> +			polarity ^= 1 << i;
> +			writel(polarity, GPIO_IN_POL(mvchip));
> +		}
> +		generic_handle_irq(irq);
> +	}
> +}
> +
> +static struct platform_device_id mvebu_gpio_ids[] = {
> +	{
> +		.name = "orion-gpio",
> +	}, {
> +		.name = "mv78200-gpio",
> +	}, {
> +		.name = "armadaxp-gpio",
why here to0?
you already detect it via DT
> +	}, {
> +		/* sentinel */
> +	},
> +};
> +MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
> +
> +static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
> +	{
> +		.compatible = "marvell,orion-gpio",
> +		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
> +	},
> +	{
> +		.compatible = "marvell,mv78200-gpio",
> +		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
> +	},
> +	{
> +		.compatible = "marvell,armadaxp-gpio",
> +		.data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
> +	},
> +	{
> +		/* sentinel */
> +	},
> +};
> +MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
> +
> +static unsigned int mvebu_gpio_chip_count;
> +
> +static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
> +{
> +	struct mvebu_gpio_chip *mvchip;
> +	const struct of_device_id *match;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct resource *res;
> +	struct irq_chip_generic *gc;
> +	struct irq_chip_type *ct;
> +	unsigned int ngpios;
> +	int soc_variant;
> +	int i, cpu;
> +
> +	match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
> +	if (match)
> +		soc_variant = (int) match->data;
> +	else
> +		soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (! res) {
> +		dev_err(&pdev->dev, "Cannot get memory resource\n");
> +		return -ENODEV;
> +	}
> +
> +	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
> +	if (! mvchip){
> +		dev_err(&pdev->dev, "Cannot allocate memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
> +		dev_err(&pdev->dev, "Missing ngpios OF property\n");
> +		return -ENODEV;
> +	}
> +
> +	mvchip->soc_variant = soc_variant;
> +	mvchip->chip.label = kasprintf(GFP_KERNEL, "mvebu-gpio%d", mvebu_gpio_chip_count);
> +	mvchip->chip.dev = &pdev->dev;
> +	mvchip->chip.request = mvebu_gpio_request;
> +	mvchip->chip.direction_input = mvebu_gpio_direction_input;
> +	mvchip->chip.get = mvebu_gpio_get;
> +	mvchip->chip.direction_output = mvebu_gpio_direction_output;
> +	mvchip->chip.set = mvebu_gpio_set;
> +	mvchip->chip.to_irq = mvebu_gpio_to_irq;
> +	mvchip->chip.base = mvebu_gpio_chip_count * 32;
why you don't use the auto allocated gpio number?
> +	mvchip->chip.ngpio = ngpios;
> +	mvchip->chip.can_sleep = 0;
> +#ifdef CONFIG_OF
> +	mvchip->chip.of_node = np;
> +#endif
> +
> +	spin_lock_init(&mvchip->lock);
> +	mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
> +	if (! mvchip->membase) {
> +		dev_err(&pdev->dev, "Cannot ioremap\n");
> +		kfree(mvchip->chip.label);
> +		return -ENOMEM;
> +	}
> +
> +	/* The Armada XP has a second range of registers for the
> +	 * per-CPU registers */
> +	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +		if (! res) {
> +			dev_err(&pdev->dev, "Cannot get memory resource\n");
> +			kfree(mvchip->chip.label);
> +			return -ENODEV;
> +		}
> +
> +		mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
> +		if (! mvchip->percpu_membase) {
> +			dev_err(&pdev->dev, "Cannot ioremap\n");
> +			kfree(mvchip->chip.label);
> +			return -ENOMEM;
> +		}
> +	}
> +
> +	/*
> +	 * Mask and clear GPIO interrupts.
> +	 */
> +	switch(soc_variant) {
> +	case MVEBU_GPIO_SOC_VARIANT_ORION:
> +		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
> +		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
> +		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
> +		break;
> +	case MVEBU_GPIO_SOC_VARIANT_MV78200:
> +		writel(0, GPIO_EDGE_CAUSE(mvchip));
> +		for (cpu = 0; cpu < 2; cpu++) {
> +			writel(0, mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu));
> +			writel(0, mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu));
> +		}
> +		break;
> +	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
> +		writel(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
> +		writel(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
> +		writel(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
> +		for (cpu = 0; cpu < 4; cpu++) {
> +			writel(0, mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
> +			writel(0, mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
> +			writel(0, mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
> +		}
> +		break;
> +	default:
> +		BUG();
> +	}
> +
> +	gpiochip_add(&mvchip->chip);
> +
> +	/* Some gpio controllers do not provide irq support */
> +	if (!of_irq_count(np)) {
> +		mvebu_gpio_chip_count++;
> +		return 0;
> +	}
> +
> +	/* Setup the interrupt handlers. Each chip can have up to 4
> +	 * interrupt handlers, with each handler dealing with 8 GPIO
> +	 * pins. */
> +	for (i = 0; i < 4; i++) {
> +		int irq;
> +		irq = platform_get_irq(pdev, i);
> +		if (irq < 0)
> +			continue;
> +		irq_set_handler_data(irq, mvchip);
> +		irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
> +	}
> +
> +	mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
> +	if (mvchip->irqbase < 0) {
> +		dev_err(&pdev->dev, "no irqs\n");
> +		kfree(mvchip->chip.label);
> +		return -ENOMEM;
> +	}
> +
> +	gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
> +				    mvchip->membase, handle_level_irq);
> +	if (! gc) {
> +		dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
> +		kfree(mvchip->chip.label);
> +		return -ENOMEM;
> +	}
> +
> +	gc->private = mvchip;
> +	ct = &gc->chip_types[0];
> +	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
> +	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
> +	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
> +	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
> +	ct->chip.name = mvchip->chip.label;
> +
> +	ct = &gc->chip_types[1];
> +	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
> +	ct->chip.irq_ack = mvebu_gpio_irq_ack;
> +	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
> +	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
> +	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
> +	ct->handler = handle_edge_irq;
> +	ct->chip.name = mvchip->chip.label;
> +
> +	irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
> +			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
> +
> +	/* Setup irq domain on top of the generic chip. */
> +	mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
> +					       mvchip->irqbase, 0,
> +					       &irq_domain_simple_ops,
> +					       mvchip);
> +	if (!mvchip->domain) {
> +		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
> +			mvchip->chip.label);
> +		irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
> +					IRQ_LEVEL | IRQ_NOPROBE);
> +		kfree(gc);
> +		kfree(mvchip->chip.label);
> +		return -ENODEV;
> +	}
> +
> +	mvebu_gpio_chip_count++;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver mvebu_gpio_driver = {
> +	.driver		= {
> +		.name	        = "mvebu-gpio",
> +		.owner	        = THIS_MODULE,
> +		.of_match_table = mvebu_gpio_of_match,
> +	},
> +	.probe		= mvebu_gpio_probe,
> +	.id_table	= mvebu_gpio_ids,
> +};
> +
> +static int __init mvebu_gpio_init(void)
> +{
> +	return platform_driver_register(&mvebu_gpio_driver);
> +}
> +postcore_initcall(mvebu_gpio_init);
> -- 
> 1.7.9.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From santosh.shilimkar at ti.com  Mon Aug 13 01:27:06 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 13 Aug 2012 10:57:06 +0530
Subject: [PATCH v4 4/4] memory: emif: add device tree support to emif
 driver
In-Reply-To: <CAMQu2gy5dkzoUDy0eFXAKqA-GkBvmmBdQwkfHUaySuKGqF9MKw@mail.gmail.com>
References: <1340977407-7594-1-git-send-email-santosh.shilimkar@ti.com>
 <1340977407-7594-5-git-send-email-santosh.shilimkar@ti.com>
 <CAMQu2gz6jdcR4hQPPbmyO8vrkdmppHeCkZmV3_9w27LOzKrUuA@mail.gmail.com>
 <20120630042356.GC1816@kroah.com>
 <CAMQu2gy0MmP4JLW4P1FreJqMMEBYSTjkLHJb8WX=aXLA6hxtZg@mail.gmail.com>
 <CAMQu2gxZ-tWJXAOeh20NsF1uyvs9fqwYtggFv=d7-qX+WFumRQ@mail.gmail.com>
 <CAMQu2gw_ZB7gVyL95B-h27B1fQh0d-YB3weaWRN6DNaGtSypDw@mail.gmail.com>
 <20120717163602.GA7167@kroah.com>
 <CAMQu2gw2Zt3E8byD=_nUXya-xU=gOA71arbbSh7gzxQhet0Vtg@mail.gmail.com>
 <20120717175832.GA20806@kroah.com>
 <CAMQu2gy5dkzoUDy0eFXAKqA-GkBvmmBdQwkfHUaySuKGqF9MKw@mail.gmail.com>
Message-ID: <CAMQu2gyBQ-iJCLCtPziX8eRm6_eXZfAoDDO0DusKCBQYpaR8jQ@mail.gmail.com>

Greg,

On Wed, Jul 18, 2012 at 12:14 PM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> On Tue, Jul 17, 2012 at 11:28 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
>> On Tue, Jul 17, 2012 at 10:37:45PM +0530, Shilimkar, Santosh wrote:
>>> On Tue, Jul 17, 2012 at 10:06 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
>>> > On Mon, Jul 09, 2012 at 07:02:36PM +0530, Shilimkar, Santosh wrote:
>>> >> Greg,
>>> >>
>
> [..]
>
>>> >From 74688a87fd490909e9122bf757c0096480e9fc11 Mon Sep 17 00:00:00 2001
>>> From: Aneesh V <aneesh at ti.com>
>>> Date: Mon, 30 Jan 2012 20:06:30 +0530
>>> Subject: [PATCH 4/4] memory: emif: add device tree support to emif driver
>>>
>>> Device tree support for the EMIF driver. LPDDR2 generic timings
>>> extraction from device is managed using couple of helper
>>> functions which can be used by other memory controller
>>> drivers.
>>>
>>> Reviewed-by: Benoit Cousson <b-cousson at ti.com>
>>> Reviewed-by: Grant Likely <grant.likely at secretlab.ca>
>>> Tested-by: Lokesh Vutla <lokeshvutla at ti.com>
>>> Signed-off-by: Aneesh V <aneesh at ti.com>
>>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
>>> ---
>>>  drivers/memory/Makefile    |    1 +
>>>  drivers/memory/emif.c      |  182 +++++++++++++++++++++++++++++++++++++++++++-
>>>  drivers/memory/of_memory.c |  153 +++++++++++++++++++++++++++++++++++++
>>>  drivers/memory/of_memory.h |   36 +++++++++
>>>  4 files changed, 371 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/memory/of_memory.c
>>>  create mode 100644 drivers/memory/of_memory.h
>>>
>>> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
>>> index 42b3ce9..cd8486b 100644
>>> --- a/drivers/memory/Makefile
>>> +++ b/drivers/memory/Makefile
>>> @@ -2,6 +2,7 @@
>>>  # Makefile for memory devices
>>>  #
>>>
>>> +obj-$(CONFIG_OF)             += of_memory.o
>>>  obj-$(CONFIG_TI_EMIF)                += emif.o
>>>  obj-$(CONFIG_TEGRA20_MC)     += tegra20-mc.o
>>>  obj-$(CONFIG_TEGRA30_MC)     += tegra30-mc.o
>>> diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
>>> index 33a4396..06b4eb7 100644
>>> --- a/drivers/memory/emif.c
>>> +++ b/drivers/memory/emif.c
>>> @@ -18,6 +18,7 @@
>>>  #include <linux/platform_device.h>
>>>  #include <linux/interrupt.h>
>>>  #include <linux/slab.h>
>>> +#include <linux/of.h>
>>>  #include <linux/debugfs.h>
>>>  #include <linux/seq_file.h>
>>>  #include <linux/module.h>
>>> @@ -25,6 +26,7 @@
>>>  #include <linux/spinlock.h>
>>>  #include <memory/jedec_ddr.h>
>>>  #include "emif.h"
>>> +#include "of_memory.h"
>>>
>>>  /**
>>>   * struct emif_data - Per device static data for driver's use
>>> @@ -49,6 +51,7 @@
>>>   *                           frequency in effect at the moment)
>>>   * @plat_data:                       Pointer to saved platform data.
>>>   * @debugfs_root:            dentry to the root folder for EMIF in debugfs
>>> + * @np_ddr:                  Pointer to ddr device tree node
>>>   */
>>>  struct emif_data {
>>>       u8                              duplicate;
>>> @@ -63,6 +66,7 @@ struct emif_data {
>>>       struct emif_regs                *curr_regs;
>>>       struct emif_platform_data       *plat_data;
>>>       struct dentry                   *debugfs_root;
>>> +     struct device_node              *np_ddr;
>>>  };
>>>
>>>  static struct emif_data *emif1;
>>> @@ -1148,6 +1152,168 @@ static int is_custom_config_valid(struct
>>> emif_custom_configs *cust_cfgs,
>>>       return valid;
>>>  }
>>>
>>> +#if defined(CONFIG_OF)
>>> +static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
>>> +             struct emif_data *emif)
>>
>> Why can't all of this code be in the of_memory.c file?
>>
> Primarily because the parameters are very much specific to EMIF
> memory controller and won't be of much use for other memory controllers.
>
> Currently the information extracted from DT with these function is like:
> - EMIF controller IP version : EMIF_4D or EMIF_4D5
> - Which analog phy is integrated : EMIF_ATTILAPHY or EMIF_ATTILAPHY
> - IP hardware interface: EMIF Low latency port or sys port interface.
> - EMIF connections - Whether EMIF1 only, EMIF2 only or EMIF1 & EMIF2
> - Memory connections to EMIF - Same type and size memories or asymmetric
> - Chip select usage per controller: Whether CS0, CS1, CS0 & CS1
> - ZQ calibration - Per chip select or enable EMIF dual calibration feature.
> - Enable/disable EMIF Low power mode and temperature alerts.
> - EMIF low power mode configuration:
>       - Clock stop, self refresh, Deep power down.
>       - Low power time out values for performance and power mode.
>       - DDR frequency threshold to switch between power and
> performance settings.
> - EMIF temperature polling cycle configuration.
>
> As you can see these are very specific to the EMIF memory controller and hence
> I didn't move them to of_memory.c
>
Do you have any more comment on this patch? If not, I can go ahead and
post the refreshed version of the patch.

Regards
Santosh


From bryan.wu at canonical.com  Mon Aug 13 01:51:24 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:24 +0800
Subject: [PATCH v10 00/18] Introduce a led trigger for CPU activity and
 consolidate LED driver in ARM
Message-ID: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>

Based on Linus Walleij's ARM LED consolidation work, this patchset introduce a
new generic led trigger for CPU not only for ARM but also for others.

For enabling CPU idle event, CPU arch code should call ledtrig_cpu() stub to
trigger idle start or idle end event.

These patches convert old style LED driver in arch/arm to gpio_led or new led
driver interface. Against 3.5 release and build successfully for all the machines.

Test ledtrig-cpu driver on OMAP4 Panda board.

Please find these patches here:
       git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git for-arm-soc

v9 --> v10
 * fix compiling issue on versatile_defconfig reported by Russell King
 * rebase to 3.5 kernel and move patches to new git tree

v8 --> v9:
 * use mutex to replace rw_sema pointed out by Tim Gardner
 * add a new struct led_trigger_cpu
 * add lock_is_inited to record mutex lock initialization

v6 --> v7:
 * add a patch to unify the led-trigger name
 * fix some typo pointed
 * use BUG_ON to detect CPU numbers during building stage

v5 --> v6:
 * replace  __get_cpu_var() to per_cpu()
 * remove smp_processor_id() which is wrong with for_each_possible_cpu()
 * test on real OMAP4 Panda board
 * add comments about CPU hotplug in the CPU LED trigger driver

v4 --> v5:
 * rebase all the patches on top of latest linux-next
 * replace on_each_cpu() with for_each_possible_cpu()
 * add some description of ledtrig_cpu() API
 * remove old leds code from driver nwflash.c, which should use a new led trigger then
 * this trigger driver can be built as module now

v3 --> v4:
 * fix a typo pointed by Jochen Friedrich
 * fix some building errors
 * add Reviewed-by and Tested-by into patch log

v2 --> v3:
 * almost rewrote the whole ledtrig-cpu driver, which is more simple
 * every CPU will have a per-CPU trigger
 * cpu trigger can be assigned to any leds
 * fix a lockdep issue in led-trigger common code
 * other fix according to review

v1 --> v2:
 * remove select operations in Kconfig of every machines
 * add back supporting of led in core module of mach-integrator
 * solidate name scheme in ledtrig-cpu.c
 * add comments of CPU_LED_* cpu led events
 * fold patches of RealView and Versatile together
 * add machine_is_ check during assabet led driver init
 * add some Acked-by in patch logs
 * remove code for simpad machine in machine-sa11000, since Jochen Friedrich
 introduced gpiolib and gpio-led driver for simpad
 * on Assabet and Netwinder machine, LED operations is reversed like:
 setting bit means turn off leds
 clearing bit means turn on leds
 * add a new function to read CM_CTRL register for led driver

Bryan Wu (18):
  led-triggers: create a trigger for CPU activity
  ARM: at91: convert old leds drivers to gpio_led and led_trigger
    drivers
  ARM: mach-realview and mach-versatile: retire custom LED code
  ARM: mach-ks8695: remove leds driver, since nobody use it
  ARM: mach-shark: retire custom LED code
  ARM: mach-orion5x: convert custom LED code to gpio_led and LED CPU
    trigger
  ARM: mach-integrator: move CM_CTRL to header file for accessing by
    other functions
  ARM: mach-integrator: retire custom LED code
  ARM: mach-clps711x: retire custom LED code of P720T machine
  ARM: mach-ebsa110: retire custom LED code
  ARM: mach-footbridge: retire custom LED code
  char: nwflash: remove old led event code
  ARM: mach-pxa: retire custom LED code
  ARM: plat-samsung: remove including old leds event API header file
  ARM: mach-pnx4008: remove including old leds event API header file
  ARM: mach-omap1: retire custom LED code
  ARM: mach-sa1100: retire custom LED code
  ARM: use new LEDS CPU trigger stub to replace old one

 arch/arm/Kconfig                             |  53 -----
 arch/arm/include/asm/leds.h                  |  50 -----
 arch/arm/kernel/Makefile                     |   1 -
 arch/arm/kernel/leds.c                       | 121 -----------
 arch/arm/kernel/process.c                    |   6 +-
 arch/arm/kernel/time.c                       |  17 --
 arch/arm/mach-at91/board-csb337.c            |   2 -
 arch/arm/mach-at91/board-ecbat91.c           |  18 +-
 arch/arm/mach-at91/board-eco920.c            |  22 +-
 arch/arm/mach-at91/board-kafa.c              |  17 +-
 arch/arm/mach-at91/board-kb9202.c            |  23 ++-
 arch/arm/mach-at91/board-rm9200dk.c          |   3 -
 arch/arm/mach-at91/board-rm9200ek.c          |   3 -
 arch/arm/mach-at91/board-rsi-ews.c           |   3 -
 arch/arm/mach-at91/board-sam9-l9260.c        |  23 ++-
 arch/arm/mach-at91/board-sam9261ek.c         |   3 -
 arch/arm/mach-at91/board-yl-9200.c           |   3 -
 arch/arm/mach-at91/include/mach/board.h      |   1 -
 arch/arm/mach-at91/leds.c                    | 105 ----------
 arch/arm/mach-clps711x/Makefile              |   2 -
 arch/arm/mach-clps711x/common.c              |   1 -
 arch/arm/mach-clps711x/p720t-leds.c          |  63 ------
 arch/arm/mach-clps711x/p720t.c               |  61 ++++++
 arch/arm/mach-ebsa110/Makefile               |   4 +-
 arch/arm/mach-ebsa110/leds.c                 |  81 +++++---
 arch/arm/mach-footbridge/Makefile            |   4 -
 arch/arm/mach-footbridge/ebsa285-leds.c      | 138 -------------
 arch/arm/mach-footbridge/ebsa285.c           |  81 ++++++++
 arch/arm/mach-footbridge/netwinder-hw.c      | 112 ++++++++--
 arch/arm/mach-footbridge/netwinder-leds.c    | 138 -------------
 arch/arm/mach-integrator/Makefile            |   3 +-
 arch/arm/mach-integrator/core.c              |   3 -
 arch/arm/mach-integrator/include/mach/cm.h   |   2 +
 arch/arm/mach-integrator/leds.c              | 161 +++++++++------
 arch/arm/mach-ks8695/Makefile                |   3 -
 arch/arm/mach-ks8695/devices.c               |  21 --
 arch/arm/mach-ks8695/include/mach/devices.h  |   5 -
 arch/arm/mach-ks8695/leds.c                  |  92 ---------
 arch/arm/mach-omap1/Makefile                 |   8 -
 arch/arm/mach-omap1/board-h2.c               |  32 +++
 arch/arm/mach-omap1/board-h3.c               |  32 +++
 arch/arm/mach-omap1/board-osk.c              |  33 +++
 arch/arm/mach-omap1/leds-h2p2-debug.c        | 166 ---------------
 arch/arm/mach-omap1/leds-innovator.c         |  98 ---------
 arch/arm/mach-omap1/leds-osk.c               | 113 -----------
 arch/arm/mach-omap1/leds.c                   |  69 -------
 arch/arm/mach-omap1/leds.h                   |   3 -
 arch/arm/mach-omap1/time.c                   |   1 -
 arch/arm/mach-omap1/timer32k.c               |   1 -
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |   1 -
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c  |   1 -
 arch/arm/mach-orion5x/rd88f5182-setup.c      |  72 ++-----
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c |   1 -
 arch/arm/mach-pnx4008/time.c                 |   1 -
 arch/arm/mach-pxa/Makefile                   |   8 -
 arch/arm/mach-pxa/idp.c                      |  81 ++++++++
 arch/arm/mach-pxa/leds-idp.c                 | 115 -----------
 arch/arm/mach-pxa/leds-lubbock.c             | 124 ------------
 arch/arm/mach-pxa/leds-mainstone.c           | 119 -----------
 arch/arm/mach-pxa/leds.c                     |  32 ---
 arch/arm/mach-pxa/leds.h                     |  13 --
 arch/arm/mach-pxa/lubbock.c                  |  95 +++++++++
 arch/arm/mach-pxa/mainstone.c                |  94 +++++++++
 arch/arm/mach-realview/core.c                |  39 ----
 arch/arm/mach-realview/core.h                |   2 -
 arch/arm/mach-realview/realview_eb.c         |   5 -
 arch/arm/mach-realview/realview_pb1176.c     |   5 -
 arch/arm/mach-realview/realview_pb11mp.c     |   5 -
 arch/arm/mach-realview/realview_pba8.c       |   5 -
 arch/arm/mach-realview/realview_pbx.c        |   5 -
 arch/arm/mach-sa1100/Makefile                |   9 -
 arch/arm/mach-sa1100/assabet.c               |  85 ++++++++
 arch/arm/mach-sa1100/badge4.c                |  30 +++
 arch/arm/mach-sa1100/cerf.c                  |  42 ++++
 arch/arm/mach-sa1100/hackkit.c               |  32 +++
 arch/arm/mach-sa1100/lart.c                  |  26 +++
 arch/arm/mach-sa1100/leds-assabet.c          | 113 -----------
 arch/arm/mach-sa1100/leds-badge4.c           | 110 ----------
 arch/arm/mach-sa1100/leds-cerf.c             | 109 ----------
 arch/arm/mach-sa1100/leds-hackkit.c          | 111 ----------
 arch/arm/mach-sa1100/leds-lart.c             | 100 ---------
 arch/arm/mach-sa1100/leds.c                  |  50 -----
 arch/arm/mach-sa1100/leds.h                  |  13 --
 arch/arm/mach-shark/Makefile                 |   4 +-
 arch/arm/mach-shark/core.c                   |   1 -
 arch/arm/mach-shark/leds.c                   | 220 ++++++++------------
 arch/arm/mach-versatile/core.c               |   5 -
 arch/arm/plat-omap/Kconfig                   |   3 +-
 arch/arm/plat-omap/debug-leds.c              | 293 ++++++---------------------
 arch/arm/plat-samsung/time.c                 |   1 -
 arch/arm/plat-versatile/Kconfig              |   4 +-
 arch/arm/plat-versatile/leds.c               |   8 +-
 drivers/char/nwflash.c                       |  34 ----
 drivers/leds/Kconfig                         |  10 +
 drivers/leds/Makefile                        |   1 +
 drivers/leds/ledtrig-cpu.c                   | 163 +++++++++++++++
 include/linux/leds.h                         |  16 ++
 97 files changed, 1440 insertions(+), 2981 deletions(-)
 delete mode 100644 arch/arm/include/asm/leds.h
 delete mode 100644 arch/arm/kernel/leds.c
 delete mode 100644 arch/arm/mach-clps711x/p720t-leds.c
 delete mode 100644 arch/arm/mach-footbridge/ebsa285-leds.c
 delete mode 100644 arch/arm/mach-footbridge/netwinder-leds.c
 delete mode 100644 arch/arm/mach-ks8695/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds-h2p2-debug.c
 delete mode 100644 arch/arm/mach-omap1/leds-innovator.c
 delete mode 100644 arch/arm/mach-omap1/leds-osk.c
 delete mode 100644 arch/arm/mach-omap1/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds.h
 delete mode 100644 arch/arm/mach-pxa/leds-idp.c
 delete mode 100644 arch/arm/mach-pxa/leds-lubbock.c
 delete mode 100644 arch/arm/mach-pxa/leds-mainstone.c
 delete mode 100644 arch/arm/mach-pxa/leds.c
 delete mode 100644 arch/arm/mach-pxa/leds.h
 delete mode 100644 arch/arm/mach-sa1100/leds-assabet.c
 delete mode 100644 arch/arm/mach-sa1100/leds-badge4.c
 delete mode 100644 arch/arm/mach-sa1100/leds-cerf.c
 delete mode 100644 arch/arm/mach-sa1100/leds-hackkit.c
 delete mode 100644 arch/arm/mach-sa1100/leds-lart.c
 delete mode 100644 arch/arm/mach-sa1100/leds.c
 delete mode 100644 arch/arm/mach-sa1100/leds.h
 create mode 100644 drivers/leds/ledtrig-cpu.c

-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:25 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:25 +0800
Subject: [PATCH 01/18] led-triggers: create a trigger for CPU activity
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-2-git-send-email-bryan.wu@canonical.com>

Attempting to consolidate the ARM LED code, this removes the
custom RealView LED trigger code to turn LEDs on and off in
response to CPU activity and replace it with a standard trigger.

(bryan.wu at canonical.com:
It introduces several syscore stubs into this trigger.
It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
Although it was inspired by ARM work, it can be used in other arch.)

Cc: Richard Purdie <rpurdie at rpsys.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Reviewed-by: Jamie Iles <jamie at jamieiles.com>
Tested-by: Jochen Friedrich <jochen at scram.de>
---
 drivers/leds/Kconfig       |  10 +++
 drivers/leds/Makefile      |   1 +
 drivers/leds/ledtrig-cpu.c | 163 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/leds.h       |  16 +++++
 4 files changed, 190 insertions(+)
 create mode 100644 drivers/leds/ledtrig-cpu.c

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 12b2b55..c96fd29 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -469,6 +469,16 @@ config LEDS_TRIGGER_BACKLIGHT
 
 	  If unsure, say N.
 
+config LEDS_TRIGGER_CPU
+	bool "LED CPU Trigger"
+	depends on LEDS_TRIGGERS
+	help
+	  This allows LEDs to be controlled by active CPUs. This shows
+	  the active CPUs across an array of LEDs so you can see which
+	  CPUs are active on the system at any given moment.
+
+	  If unsure, say N.
+
 config LEDS_TRIGGER_GPIO
 	tristate "LED GPIO Trigger"
 	depends on LEDS_TRIGGERS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index f8958cd..fa0f536 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -57,5 +57,6 @@ obj-$(CONFIG_LEDS_TRIGGER_IDE_DISK)	+= ledtrig-ide-disk.o
 obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT)	+= ledtrig-heartbeat.o
 obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT)	+= ledtrig-backlight.o
 obj-$(CONFIG_LEDS_TRIGGER_GPIO)		+= ledtrig-gpio.o
+obj-$(CONFIG_LEDS_TRIGGER_CPU)		+= ledtrig-cpu.o
 obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
 obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT)	+= ledtrig-transient.o
diff --git a/drivers/leds/ledtrig-cpu.c b/drivers/leds/ledtrig-cpu.c
new file mode 100644
index 0000000..b312056
--- /dev/null
+++ b/drivers/leds/ledtrig-cpu.c
@@ -0,0 +1,163 @@
+/*
+ * ledtrig-cpu.c - LED trigger based on CPU activity
+ *
+ * This LED trigger will be registered for each possible CPU and named as
+ * cpu0, cpu1, cpu2, cpu3, etc.
+ *
+ * It can be bound to any LED just like other triggers using either a
+ * board file or via sysfs interface.
+ *
+ * An API named ledtrig_cpu is exported for any user, who want to add CPU
+ * activity indication in their code
+ *
+ * Copyright 2011 Linus Walleij <linus.walleij at linaro.org>
+ * Copyright 2011 - 2012 Bryan Wu <bryan.wu at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/percpu.h>
+#include <linux/syscore_ops.h>
+#include <linux/rwsem.h>
+#include "leds.h"
+
+#define MAX_NAME_LEN	8
+
+struct led_trigger_cpu {
+	char name[MAX_NAME_LEN];
+	struct led_trigger *_trig;
+	struct mutex lock;
+	int lock_is_inited;
+};
+
+static DEFINE_PER_CPU(struct led_trigger_cpu, cpu_trig);
+
+/**
+ * ledtrig_cpu - emit a CPU event as a trigger
+ * @evt: CPU event to be emitted
+ *
+ * Emit a CPU event on a CPU core, which will trigger a
+ * binded LED to turn on or turn off.
+ */
+void ledtrig_cpu(enum cpu_led_event ledevt)
+{
+	struct led_trigger_cpu *trig = &__get_cpu_var(cpu_trig);
+
+	/* mutex lock should be initialized before calling mutex_call() */
+	if (!trig->lock_is_inited)
+		return;
+
+	mutex_lock(&trig->lock);
+
+	/* Locate the correct CPU LED */
+	switch (ledevt) {
+	case CPU_LED_IDLE_END:
+	case CPU_LED_START:
+		/* Will turn the LED on, max brightness */
+		led_trigger_event(trig->_trig, LED_FULL);
+		break;
+
+	case CPU_LED_IDLE_START:
+	case CPU_LED_STOP:
+	case CPU_LED_HALTED:
+		/* Will turn the LED off */
+		led_trigger_event(trig->_trig, LED_OFF);
+		break;
+
+	default:
+		/* Will leave the LED as it is */
+		break;
+	}
+
+	mutex_unlock(&trig->lock);
+}
+EXPORT_SYMBOL(ledtrig_cpu);
+
+static int ledtrig_cpu_syscore_suspend(void)
+{
+	ledtrig_cpu(CPU_LED_STOP);
+	return 0;
+}
+
+static void ledtrig_cpu_syscore_resume(void)
+{
+	ledtrig_cpu(CPU_LED_START);
+}
+
+static void ledtrig_cpu_syscore_shutdown(void)
+{
+	ledtrig_cpu(CPU_LED_HALTED);
+}
+
+static struct syscore_ops ledtrig_cpu_syscore_ops = {
+	.shutdown	= ledtrig_cpu_syscore_shutdown,
+	.suspend	= ledtrig_cpu_syscore_suspend,
+	.resume		= ledtrig_cpu_syscore_resume,
+};
+
+static int __init ledtrig_cpu_init(void)
+{
+	int cpu;
+
+	/* Supports up to 9999 cpu cores */
+	BUILD_BUG_ON(CONFIG_NR_CPUS > 9999);
+
+	/*
+	 * Registering CPU led trigger for each CPU core here
+	 * ignores CPU hotplug, but after this CPU hotplug works
+	 * fine with this trigger.
+	 */
+	for_each_possible_cpu(cpu) {
+		struct led_trigger_cpu *trig = &per_cpu(cpu_trig, cpu);
+
+		mutex_init(&trig->lock);
+
+		snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu);
+
+		mutex_lock(&trig->lock);
+		led_trigger_register_simple(trig->name, &trig->_trig);
+		trig->lock_is_inited = 1;
+		mutex_unlock(&trig->lock);
+	}
+
+	register_syscore_ops(&ledtrig_cpu_syscore_ops);
+
+	pr_info("ledtrig-cpu: registered to indicate activity on CPUs\n");
+
+	return 0;
+}
+module_init(ledtrig_cpu_init);
+
+static void __exit ledtrig_cpu_exit(void)
+{
+	int cpu;
+
+	for_each_possible_cpu(cpu) {
+		struct led_trigger_cpu *trig = &per_cpu(cpu_trig, cpu);
+
+		mutex_lock(&trig->lock);
+
+		led_trigger_unregister_simple(trig->_trig);
+		trig->_trig = NULL;
+		memset(trig->name, 0, MAX_NAME_LEN);
+		trig->lock_is_inited = 0;
+
+		mutex_unlock(&trig->lock);
+		mutex_destroy(&trig->lock);
+	}
+
+	unregister_syscore_ops(&ledtrig_cpu_syscore_ops);
+}
+module_exit(ledtrig_cpu_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij at linaro.org>");
+MODULE_AUTHOR("Bryan Wu <bryan.wu at canonical.com>");
+MODULE_DESCRIPTION("CPU LED trigger");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 39eee41..cd54558 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -212,4 +212,20 @@ struct gpio_led_platform_data {
 struct platform_device *gpio_led_register_device(
 		int id, const struct gpio_led_platform_data *pdata);
 
+enum cpu_led_event {
+	CPU_LED_IDLE_START,	/* CPU enters idle */
+	CPU_LED_IDLE_END,	/* CPU idle ends */
+	CPU_LED_START,		/* Machine starts, especially resume */
+	CPU_LED_STOP,		/* Machine stops, especially suspend */
+	CPU_LED_HALTED,		/* Machine shutdown */
+};
+#ifdef CONFIG_LEDS_TRIGGER_CPU
+extern void ledtrig_cpu(enum cpu_led_event evt);
+#else
+static inline void ledtrig_cpu(enum cpu_led_event evt)
+{
+	return;
+}
+#endif
+
 #endif		/* __LINUX_LEDS_H_INCLUDED */
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:26 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:26 +0800
Subject: [PATCH 02/18] ARM: at91: convert old leds drivers to gpio_led and
 led_trigger drivers
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-3-git-send-email-bryan.wu@canonical.com>

Build with at91 defconfigs successfully

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/board-csb337.c       |   2 -
 arch/arm/mach-at91/board-ecbat91.c      |  18 +++++-
 arch/arm/mach-at91/board-eco920.c       |  22 ++++++-
 arch/arm/mach-at91/board-kafa.c         |  17 +++++-
 arch/arm/mach-at91/board-kb9202.c       |  23 ++++++-
 arch/arm/mach-at91/board-rm9200dk.c     |   3 -
 arch/arm/mach-at91/board-rm9200ek.c     |   3 -
 arch/arm/mach-at91/board-rsi-ews.c      |   3 -
 arch/arm/mach-at91/board-sam9-l9260.c   |  23 ++++++-
 arch/arm/mach-at91/board-sam9261ek.c    |   3 -
 arch/arm/mach-at91/board-yl-9200.c      |   3 -
 arch/arm/mach-at91/include/mach/board.h |   1 -
 arch/arm/mach-at91/leds.c               | 105 --------------------------------
 13 files changed, 89 insertions(+), 137 deletions(-)

diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index cd81336..4993f1b 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -219,8 +219,6 @@ static struct gpio_led csb_leds[] = {
 
 static void __init csb337_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
 	/* Serial */
 	/* DBGU on ttyS0 */
 	at91_register_uart(0, 0, 0);
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 89cc372..f9a4ab9 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -137,11 +137,20 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
 	},
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led ecb_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PC7,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	}
+};
+
 static void __init ecb_at91board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
@@ -164,6 +173,9 @@ static void __init ecb_at91board_init(void)
 
 	/* SPI */
 	at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+
+	/* LEDs */
+	at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
 }
 
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 558546c..76cc826 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -92,10 +92,26 @@ static struct spi_board_info eco920_spi_devices[] = {
 	},
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led eco920_leds[] = {
+	{       /* D1 */
+		.name                   = "led1",
+		.gpio                   = AT91_PIN_PB0,
+		.active_low             = 1,
+		.default_trigger        = "heartbeat",
+	},
+	{       /* D2 */
+		.name                   = "led2",
+		.gpio                   = AT91_PIN_PB1,
+		.active_low             = 1,
+		.default_trigger        = "timer",
+	}
+};
+
 static void __init eco920_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
 	/* DBGU on ttyS0. (Rx & Tx only */
 	at91_register_uart(0, 0, 0);
 	at91_add_device_serial();
@@ -126,6 +142,8 @@ static void __init eco920_board_init(void)
 	);
 
 	at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
+	/* LEDs */
+	at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
 }
 
 MACHINE_START(ECO920, "eco920")
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index f260657..8db11f4 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -65,11 +65,20 @@ static struct at91_udc_data __initdata kafa_udc_data = {
 	.pullup_pin	= AT91_PIN_PB7,
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kafa_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PB4,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+};
+
 static void __init kafa_board_init(void)
 {
-	/* Set up the LEDs */
-	at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
@@ -87,6 +96,8 @@ static void __init kafa_board_init(void)
 	at91_add_device_i2c(NULL, 0);
 	/* SPI */
 	at91_add_device_spi(NULL, 0);
+	/* LEDs */
+	at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
 }
 
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index ba39db5..4e362b8 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -95,11 +95,26 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
 	.num_parts	= ARRAY_SIZE(kb9202_nand_partition),
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kb9202_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PC19,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+	{	/* D2 */
+		.name			= "led2",
+		.gpio			= AT91_PIN_PC18,
+		.active_low		= 1,
+		.default_trigger	= "timer",
+	}
+};
+
 static void __init kb9202_board_init(void)
 {
-	/* Set up the LEDs */
-	at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
@@ -127,6 +142,8 @@ static void __init kb9202_board_init(void)
 	at91_add_device_spi(NULL, 0);
 	/* NAND */
 	at91_add_device_nand(&kb9202_nand_data);
+	/* LEDs */
+	at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
 }
 
 MACHINE_START(KB9200, "KB920x")
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index afd7a47..7417b7c 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -176,9 +176,6 @@ static struct gpio_led dk_leds[] = {
 
 static void __init dk_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 2b15b8a..18b2ec0 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -147,9 +147,6 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index 24ab9be..32342b8 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -184,9 +184,6 @@ static struct platform_device rsiews_nor_flash = {
  */
 static void __init rsi_ews_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	/* This one is for debugging */
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index cdd21f2..ef982f8 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -165,11 +165,26 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 	.vcc_pin	= -EINVAL,
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PA9,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+	{	/* D2 */
+		.name			= "led2",
+		.gpio			= AT91_PIN_PA6,
+		.active_low		= 1,
+		.default_trigger	= "timer",
+	}
+};
+
 static void __init ek_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
@@ -196,6 +211,8 @@ static void __init ek_board_init(void)
 	at91_add_device_mmc(0, &ek_mmc_data);
 	/* I2C */
 	at91_add_device_i2c(NULL, 0);
+	/* LEDs */
+	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2736453..0b4501c 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -568,9 +568,6 @@ static struct gpio_led ek_leds[] = {
 
 static void __init ek_board_init(void)
 {
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index d56665e..cc05dd1 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -540,9 +540,6 @@ void __init yl9200_add_device_video(void) {}
 
 static void __init yl9200_board_init(void)
 {
-	/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
-	at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
-
 	/* Serial */
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 369afc2..c55a436 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -187,7 +187,6 @@ struct at91_can_data {
 extern void __init at91_add_device_can(struct at91_can_data *data);
 
  /* LEDs */
-extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..1b1e62b 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -90,108 +90,3 @@ void __init at91_pwm_leds(struct gpio_led *leds, int nr)
 #else
 void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
 #endif
-
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-
-#include <asm/leds.h>
-
-/*
- * Old ARM-specific LED framework; not fully functional when generic time is
- * in use.
- */
-
-static u8 at91_leds_cpu;
-static u8 at91_leds_timer;
-
-static inline void at91_led_on(unsigned int led)
-{
-	at91_set_gpio_value(led, 0);
-}
-
-static inline void at91_led_off(unsigned int led)
-{
-	at91_set_gpio_value(led, 1);
-}
-
-static inline void at91_led_toggle(unsigned int led)
-{
-	unsigned long is_off = at91_get_gpio_value(led);
-	if (is_off)
-		at91_led_on(led);
-	else
-		at91_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void at91_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:		/* System startup */
-		at91_led_on(at91_leds_cpu);
-		break;
-
-	case led_stop:		/* System stop / suspend */
-		at91_led_off(at91_leds_cpu);
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:		/* Every 50 timer ticks */
-		at91_led_toggle(at91_leds_timer);
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:	/* Entering idle state */
-		at91_led_off(at91_leds_cpu);
-		break;
-
-	case led_idle_end:	/* Exit idle state */
-		at91_led_on(at91_leds_cpu);
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-	if (!at91_leds_timer || !at91_leds_cpu)
-		return -ENODEV;
-
-	leds_event = at91_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(leds_init);
-
-
-void __init at91_init_leds(u8 cpu_led, u8 timer_led)
-{
-	/* Enable GPIO to access the LEDs */
-	at91_set_gpio_output(cpu_led, 1);
-	at91_set_gpio_output(timer_led, 1);
-
-	at91_leds_cpu	= cpu_led;
-	at91_leds_timer	= timer_led;
-}
-
-#else
-void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:27 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:27 +0800
Subject: [PATCH 03/18] ARM: mach-realview and mach-versatile: retire custom
 LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-4-git-send-email-bryan.wu@canonical.com>

This replaces the custom LED trigger code in mach-realview with
some overarching platform code for the plat-versatile family that
will lock down LEDs 2 thru 5 for CPU activity indication. The
day we have 8 core ARM systems the plat-versatile code will have
to become more elaborate.

Tested on RealView PB11MPCore by invoking four different CPU
hogs (yes > /dev/null&) and see the LEDs go on one at a time.
They all go off as the hogs are killed. Tested on the PB1176
as well - just one activity led (led 2) goes on and off with
CPU activity.

(bryan.wu at canonical.com: use ledtrig-cpu instead of ledtrig-arm-cpu)

Cc: Richard Purdie <rpurdie at rpsys.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-realview/core.c            | 39 --------------------------------
 arch/arm/mach-realview/core.h            |  2 --
 arch/arm/mach-realview/realview_eb.c     |  5 ----
 arch/arm/mach-realview/realview_pb1176.c |  5 ----
 arch/arm/mach-realview/realview_pb11mp.c |  5 ----
 arch/arm/mach-realview/realview_pba8.c   |  5 ----
 arch/arm/mach-realview/realview_pbx.c    |  5 ----
 arch/arm/mach-versatile/core.c           |  5 ----
 arch/arm/plat-versatile/Kconfig          |  4 +++-
 arch/arm/plat-versatile/leds.c           |  8 +++----
 10 files changed, 7 insertions(+), 76 deletions(-)

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb..d22dee9 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -35,7 +35,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
@@ -436,44 +435,6 @@ struct clcd_board clcd_plat_data = {
 	.remove		= versatile_clcd_remove_dma,
 };
 
-#ifdef CONFIG_LEDS
-#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-
-void realview_leds_event(led_event_t ledevt)
-{
-	unsigned long flags;
-	u32 val;
-	u32 led = 1 << smp_processor_id();
-
-	local_irq_save(flags);
-	val = readl(VA_LEDS_BASE);
-
-	switch (ledevt) {
-	case led_idle_start:
-		val = val & ~led;
-		break;
-
-	case led_idle_end:
-		val = val | led;
-		break;
-
-	case led_timer:
-		val = val ^ REALVIEW_SYS_LED7;
-		break;
-
-	case led_halted:
-		val = 0;
-		break;
-
-	default:
-		break;
-	}
-
-	writel(val, VA_LEDS_BASE);
-	local_irq_restore(flags);
-}
-#endif	/* CONFIG_LEDS */
-
 /*
  * Where is the timer (VA)?
  */
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index f8f2c0a..f2141ae 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 
 #include <asm/setup.h>
-#include <asm/leds.h>
 
 #define APB_DEVICE(name, busid, base, plat)			\
 static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
@@ -47,7 +46,6 @@ extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
 extern void __iomem *timer3_va_base;
 
-extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..21661ad 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -30,7 +30,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -462,10 +461,6 @@ static void __init realview_eb_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..c0ff882 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -32,7 +32,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -375,10 +374,6 @@ static void __init realview_pb1176_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..30779ae 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -30,7 +30,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -357,10 +356,6 @@ static void __init realview_pb11mp_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..081cd72 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,7 +29,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -299,10 +298,6 @@ static void __init realview_pba8_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..1ce62b9 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/smp_twd.h>
@@ -394,10 +393,6 @@ static void __init realview_pbx_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index cd8ea35..855ca02 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -37,7 +37,6 @@
 #include <linux/mtd/physmap.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
@@ -763,10 +762,6 @@ void __init versatile_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = versatile_leds_event;
-#endif
 }
 
 /*
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 81ee7cc..5c73e31 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -13,8 +13,10 @@ config PLAT_VERSATILE_FPGA_IRQ_NR
        depends on PLAT_VERSATILE_FPGA_IRQ
 
 config PLAT_VERSATILE_LEDS
-	def_bool y if LEDS_CLASS
+	def_bool y if NEW_LEDS
 	depends on ARCH_REALVIEW || ARCH_VERSATILE
+	select LEDS_CLASS
+	select LEDS_TRIGGER
 
 config PLAT_VERSATILE_SCHED_CLOCK
 	def_bool y
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
index 3169fa5..d2490d0 100644
--- a/arch/arm/plat-versatile/leds.c
+++ b/arch/arm/plat-versatile/leds.c
@@ -37,10 +37,10 @@ static const struct {
 } versatile_leds[] = {
 	{ "versatile:0", "heartbeat", },
 	{ "versatile:1", "mmc0", },
-	{ "versatile:2", },
-	{ "versatile:3", },
-	{ "versatile:4", },
-	{ "versatile:5", },
+	{ "versatile:2", "cpu0" },
+	{ "versatile:3", "cpu1" },
+	{ "versatile:4", "cpu2" },
+	{ "versatile:5", "cpu3" },
 	{ "versatile:6", },
 	{ "versatile:7", },
 };
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:28 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:28 +0800
Subject: [PATCH 04/18] ARM: mach-ks8695: remove leds driver,
 since nobody use it
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-5-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Andrew Victor <linux at maxim.org.za>
---
 arch/arm/mach-ks8695/Makefile               |  3 -
 arch/arm/mach-ks8695/devices.c              | 21 -------
 arch/arm/mach-ks8695/include/mach/devices.h |  5 --
 arch/arm/mach-ks8695/leds.c                 | 92 -----------------------------
 4 files changed, 121 deletions(-)
 delete mode 100644 arch/arm/mach-ks8695/leds.c

diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 853efd9..9324ef9 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,9 +11,6 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)		+= pci.o
 
-# LEDs
-obj-$(CONFIG_LEDS)		+= leds.o
-
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)	+= board-micrel.o
 obj-$(CONFIG_MACH_DSM320)	+= board-dsm320.o
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 73bd638..47399bc 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -182,27 +182,6 @@ static void __init ks8695_add_device_watchdog(void)
 }
 
 
-/* --------------------------------------------------------------------
- *  LEDs
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-short ks8695_leds_cpu = -1;
-short ks8695_leds_timer = -1;
-
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
-{
-	/* Enable GPIO to access the LEDs */
-	gpio_direction_output(cpu_led, 1);
-	gpio_direction_output(timer_led, 1);
-
-	ks8695_leds_cpu	  = cpu_led;
-	ks8695_leds_timer = timer_led;
-}
-#else
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
-
 /* -------------------------------------------------------------------- */
 
 /*
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h
index 85a3c9a..1e6594a 100644
--- a/arch/arm/mach-ks8695/include/mach/devices.h
+++ b/arch/arm/mach-ks8695/include/mach/devices.h
@@ -18,11 +18,6 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
 
- /* LEDs */
-extern short ks8695_leds_cpu;
-extern short ks8695_leds_timer;
-extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
-
  /* PCI */
 #define KS8695_MODE_PCI		0
 #define KS8695_MODE_MINIPCI	1
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
deleted file mode 100644
index 4bd7075..0000000
--- a/arch/arm/mach-ks8695/leds.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * LED driver for KS8695-based boards.
- *
- * Copyright (C) Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <mach/devices.h>
-
-
-static inline void ks8695_led_on(unsigned int led)
-{
-	gpio_set_value(led, 0);
-}
-
-static inline void ks8695_led_off(unsigned int led)
-{
-	gpio_set_value(led, 1);
-}
-
-static inline void ks8695_led_toggle(unsigned int led)
-{
-	unsigned long is_off = gpio_get_value(led);
-	if (is_off)
-		ks8695_led_on(led);
-	else
-		ks8695_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void ks8695_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:		/* System startup */
-		ks8695_led_on(ks8695_leds_cpu);
-		break;
-
-	case led_stop:		/* System stop / suspend */
-		ks8695_led_off(ks8695_leds_cpu);
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:		/* Every 50 timer ticks */
-		ks8695_led_toggle(ks8695_leds_timer);
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:	/* Entering idle state */
-		ks8695_led_off(ks8695_leds_cpu);
-		break;
-
-	case led_idle_end:	/* Exit idle state */
-		ks8695_led_on(ks8695_leds_cpu);
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-	if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
-		return -ENODEV;
-
-	leds_event = ks8695_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(leds_init);
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:29 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:29 +0800
Subject: [PATCH 05/18] ARM: mach-shark: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-6-git-send-email-bryan.wu@canonical.com>

The CPU activity LED is now handled by the trigger in the leds
subsystem, retire this old CONFIG_LEDS-based code.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-shark/Makefile |   4 +-
 arch/arm/mach-shark/core.c   |   1 -
 arch/arm/mach-shark/leds.c   | 220 +++++++++++++++++--------------------------
 3 files changed, 87 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile
index 45be9b0..2965718 100644
--- a/arch/arm/mach-shark/Makefile
+++ b/arch/arm/mach-shark/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o dma.o irq.o pci.o
+obj-y			:= core.o dma.o irq.o pci.o leds.o
 obj-m			:=
 obj-n			:=
 obj-			:=
-
-obj-$(CONFIG_LEDS)	+= leds.o
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 2704bcd..c709979 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -13,7 +13,6 @@
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/param.h>
 #include <asm/system_misc.h>
 
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 2560907..081c778 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -1,165 +1,117 @@
 /*
- * arch/arm/mach-shark/leds.c
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/kernel/leds-footbridge.c
- * Copyright (C) 1998-1999 Russell King
- *
  * DIGITAL Shark LED control routines.
  *
- * The leds use is as follows:
- *  - Green front - toggles state every 50 timer interrupts
- *  - Amber front - Unused, this is a dual color led (Amber/Green)
- *  - Amber back  - On if system is not idle
+ * Driver for the 3 user LEDs found on the Shark
+ * Based on Versatile and RealView machine LED code
  *
- * Changelog:
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/ioport.h>
 #include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <asm/leds.h>
+#include <asm/mach-types.h>
 
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct shark_led {
+	struct led_classdev cdev;
+	u8 mask;
+};
 
-#define SEQUOIA_LED_GREEN       (1<<6)
-#define SEQUOIA_LED_AMBER       (1<<5)
-#define SEQUOIA_LED_BACK        (1<<7)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} shark_leds[] = {
+	{ "shark:amber0", "default-on", },	/* Bit 5 */
+	{ "shark:green", "heartbeat", },	/* Bit 6 */
+	{ "shark:amber1", "cpu0" },		/* Bit 7 */
+};
+
+static u16 led_reg_read(void)
+{
+	outw(0x09, 0x24);
+	return inw(0x26);
+}
 
-static char led_state;
-static short hw_led_state;
-static short saved_state;
+static void led_reg_write(u16 value)
+{
+	outw(0x09, 0x24);
+	outw(value, 0x26);
+}
 
-static DEFINE_RAW_SPINLOCK(leds_lock);
+static void shark_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct shark_led *led = container_of(cdev,
+						 struct shark_led, cdev);
+	u16 reg = led_reg_read();
 
-short sequoia_read(int addr) {
-  outw(addr,0x24);
-  return inw(0x26);
-}
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
 
-void sequoia_write(short value,short addr) {
-  outw(addr,0x24);
-  outw(value,0x26);
+	led_reg_write(reg);
 }
 
-static void sequoia_leds_event(led_event_t evt)
+static enum led_brightness shark_led_get(struct led_classdev *cdev)
 {
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&leds_lock, flags);
+	struct shark_led *led = container_of(cdev,
+						 struct shark_led, cdev);
+	u16 reg = led_reg_read();
 
-	hw_led_state = sequoia_read(0x09);
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
 
-	switch (evt) {
-	case led_start:
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-#ifdef CONFIG_LEDS_CPU
-		hw_led_state |= SEQUOIA_LED_BACK;
-#else
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-#endif
-		led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		saved_state = hw_led_state;
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = saved_state;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= SEQUOIA_LED_GREEN;
-		break;
-#endif
+static int __init shark_leds_init(void)
+{
+	int i;
+	u16 reg;
 
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~SEQUOIA_LED_BACK;
-		break;
+	if (!machine_is_shark())
+		return -ENODEV;
 
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= SEQUOIA_LED_BACK;
-		break;
-#endif
+	for (i = 0; i < ARRAY_SIZE(shark_leds); i++) {
+		struct shark_led *led;
 
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_AMBER;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_BACK;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_BACK;
-		break;
-
-	default:
-		break;
-	}
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
 
-	if  (led_state & LED_STATE_ENABLED)
-		sequoia_write(hw_led_state,0x09);
+		led->cdev.name = shark_leds[i].name;
+		led->cdev.brightness_set = shark_led_set;
+		led->cdev.brightness_get = shark_led_get;
+		led->cdev.default_trigger = shark_leds[i].trigger;
 
-	raw_spin_unlock_irqrestore(&leds_lock, flags);
-}
+		/* Count in 5 bits offset */
+		led->mask = BIT(i + 5);
 
-static int __init leds_init(void)
-{
-	extern void (*leds_event)(led_event_t);
-	short temp;
-	
-	leds_event = sequoia_leds_event;
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
 
 	/* Make LEDs independent of power-state */
-	request_region(0x24,4,"sequoia");
-	temp = sequoia_read(0x09);
-	temp |= 1<<10;
-	sequoia_write(temp,0x09);
-	leds_event(led_start);
+	request_region(0x24, 4, "led_reg");
+	reg = led_reg_read();
+	reg |= 1 << 10;
+	led_reg_write(reg);
+
 	return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(shark_leds_init);
+#endif
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:30 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:30 +0800
Subject: [PATCH 06/18] ARM: mach-orion5x: convert custom LED code to gpio_led
 and LED CPU trigger
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-7-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Nicolas Pitre <nico at fluxnic.net>
---
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |  1 -
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c  |  1 -
 arch/arm/mach-orion5x/rd88f5182-setup.c      | 72 +++++++++-------------------
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c |  1 -
 4 files changed, 22 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 78a6a11..9b1c953 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -18,7 +18,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 2f5dc54..51ba2b8 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -19,7 +19,6 @@
 #include <linux/i2c.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 399130f..0a56b94 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
@@ -53,12 +53,6 @@
 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6
 
-/*
- * GPIO Debug LED
- */
-
-#define RD88F5182_GPIO_DBG_LED		0
-
 /*****************************************************************************
  * 16M NOR Flash on Device bus CS1
  ****************************************************************************/
@@ -83,55 +77,32 @@ static struct platform_device rd88f5182_nor_flash = {
 	.resource		= &rd88f5182_nor_flash_resource,
 };
 
-#ifdef CONFIG_LEDS
-
 /*****************************************************************************
- * Use GPIO debug led as CPU active indication
+ * Use GPIO LED as CPU active indication
  ****************************************************************************/
 
-static void rd88f5182_dbgled_event(led_event_t evt)
-{
-	int val;
-
-	if (evt == led_idle_end)
-		val = 1;
-	else if (evt == led_idle_start)
-		val = 0;
-	else
-		return;
-
-	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
-}
-
-static int __init rd88f5182_dbgled_init(void)
-{
-	int pin;
-
-	if (machine_is_rd88f5182()) {
-		pin = RD88F5182_GPIO_DBG_LED;
+#define RD88F5182_GPIO_LED		0
 
-		if (gpio_request(pin, "DBGLED") == 0) {
-			if (gpio_direction_output(pin, 0) != 0) {
-				printk(KERN_ERR "rd88f5182_dbgled_init failed "
-						"to set output pin %d\n", pin);
-				gpio_free(pin);
-				return 0;
-			}
-		} else {
-			printk(KERN_ERR "rd88f5182_dbgled_init failed "
-					"to request gpio %d\n", pin);
-			return 0;
-		}
-
-		leds_event = rd88f5182_dbgled_event;
-	}
-
-	return 0;
-}
+static struct gpio_led rd88f5182_gpio_led_pins[] = {
+	{
+		.name		= "rd88f5182:cpu",
+		.default_trigger = "cpu0",
+		.gpio		= RD88F5182_GPIO_LED,
+	},
+};
 
-__initcall(rd88f5182_dbgled_init);
+static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
+	.leds		= rd88f5182_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(rd88f5182_gpio_led_pins),
+};
 
-#endif
+static struct platform_device rd88f5182_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &rd88f5182_gpio_led_data,
+	},
+};
 
 /*****************************************************************************
  * PCI
@@ -298,6 +269,7 @@ static void __init rd88f5182_init(void)
 
 	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
 	platform_device_register(&rd88f5182_nor_flash);
+	platform_device_register(&rd88f5182_gpio_leds);
 
 	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
 }
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 92df49c..ed50910 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -20,7 +20,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:31 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:31 +0800
Subject: [PATCH 07/18] ARM: mach-integrator: move CM_CTRL to header file for
 accessing by other functions
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-8-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-integrator/core.c            | 2 --
 arch/arm/mach-integrator/include/mach/cm.h | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index eaf6c63..8c53562 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -172,8 +172,6 @@ static struct amba_pl010_data integrator_uart_data = {
 	.set_mctrl = integrator_uart_set_mctrl,
 };
 
-#define CM_CTRL	IO_ADDRESS(INTEGRATOR_HDR_CTRL)
-
 static DEFINE_RAW_SPINLOCK(cm_lock);
 
 /**
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 445d57a..1a78692e 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
@@ -3,6 +3,8 @@
  */
 void cm_control(u32, u32);
 
+#define CM_CTRL	IO_ADDRESS(INTEGRATOR_HDR_CTRL)
+
 #define CM_CTRL_LED			(1 << 0)
 #define CM_CTRL_nMBDET			(1 << 1)
 #define CM_CTRL_REMAP			(1 << 2)
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:32 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:32 +0800
Subject: [PATCH 08/18] ARM: mach-integrator: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-9-git-send-email-bryan.wu@canonical.com>

Use the LED in core module for CPU activity and also enable 4
debugging LEDs in baseboard.

The CPU activity LED is now handled by the trigger in the leds
subsystem, retire this old CONFIG_LEDS-based code.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-integrator/Makefile |   3 +-
 arch/arm/mach-integrator/core.c   |   1 -
 arch/arm/mach-integrator/leds.c   | 161 +++++++++++++++++++++++---------------
 3 files changed, 99 insertions(+), 66 deletions(-)

diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebeef96..5521d18 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,11 +4,10 @@
 
 # Object file lists.
 
-obj-y					:= core.o lm.o
+obj-y					:= core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)	+= integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)	+= integrator_cp.o
 
-obj-$(CONFIG_LEDS)			+= leds.o
 obj-$(CONFIG_PCI)			+= pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)	+= cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)		+= impd1.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 8c53562..0c7c4ef 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -28,7 +28,6 @@
 #include <mach/cm.h>
 #include <mach/irqs.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 466defa..7a7f6d3 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -1,90 +1,125 @@
 /*
- *  linux/arch/arm/mach-integrator/leds.c
+ * Driver for the 4 user LEDs found on the Integrator AP/CP baseboard
+ * Based on Versatile and RealView machine LED code
  *
- *  Integrator/AP and Integrator/CP LED control routines
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
+#include <mach/cm.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <mach/cm.h>
 
-static int saved_leds;
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+
+#define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
+#define LEDREG	(__io_address(INTEGRATOR_DBG_BASE) + INTEGRATOR_DBG_LEDS_OFFSET)
 
-static void integrator_leds_event(led_event_t ledevt)
+struct integrator_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} integrator_leds[] = {
+	{ "integrator:green0", "heartbeat", },
+	{ "integrator:yellow", },
+	{ "integrator:red", },
+	{ "integrator:green1", },
+	{ "integrator:core_module", "cpu0", },
+};
+
+static void integrator_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	unsigned long flags;
-	const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE);
-	unsigned int update_alpha_leds;
+	struct integrator_led *led = container_of(cdev,
+						 struct integrator_led, cdev);
+	u32 reg = __raw_readl(LEDREG);
 
-	// yup, change the LEDs
-	local_irq_save(flags);
-	update_alpha_leds = 0;
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
 
-	switch(ledevt) {
-	case led_idle_start:
-		cm_control(CM_CTRL_LED, 0);
-		break;
+	while (__raw_readl(ALPHA_REG) & 1)
+		cpu_relax();
 
-	case led_idle_end:
-		cm_control(CM_CTRL_LED, CM_CTRL_LED);
-		break;
+	__raw_writel(reg, LEDREG);
+}
 
-	case led_timer:
-		saved_leds ^= GREEN_LED;
-		update_alpha_leds = 1;
-		break;
+static enum led_brightness integrator_led_get(struct led_classdev *cdev)
+{
+	struct integrator_led *led = container_of(cdev,
+						 struct integrator_led, cdev);
+	u32 reg = __raw_readl(LEDREG);
 
-	case led_red_on:
-		saved_leds |= RED_LED;
-		update_alpha_leds = 1;
-		break;
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
 
-	case led_red_off:
-		saved_leds &= ~RED_LED;
-		update_alpha_leds = 1;
-		break;
+static void cm_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	if (b != LED_OFF)
+		cm_control(CM_CTRL_LED, CM_CTRL_LED);
+	else
+		cm_control(CM_CTRL_LED, 0);
+}
 
-	default:
-		break;
-	}
+static enum led_brightness cm_led_get(struct led_classdev *cdev)
+{
+	u32 reg = readl(CM_CTRL);
 
-	if (update_alpha_leds) {
-		while (__raw_readl(dbg_base + INTEGRATOR_DBG_ALPHA_OFFSET) & 1);
-		__raw_writel(saved_leds, dbg_base + INTEGRATOR_DBG_LEDS_OFFSET);
-	}
-	local_irq_restore(flags);
+	return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init integrator_leds_init(void)
 {
-	if (machine_is_integrator() || machine_is_cintegrator())
-		leds_event = integrator_leds_event;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(integrator_leds); i++) {
+		struct integrator_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+
+		led->cdev.name = integrator_leds[i].name;
+
+		if (i == 4) { /* Setting for LED in core module */
+			led->cdev.brightness_set = cm_led_set;
+			led->cdev.brightness_get = cm_led_get;
+		} else {
+			led->cdev.brightness_set = integrator_led_set;
+			led->cdev.brightness_get = integrator_led_get;
+		}
+
+		led->cdev.default_trigger = integrator_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
 
 	return 0;
 }
 
-core_initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(integrator_leds_init);
+#endif
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:33 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:33 +0800
Subject: [PATCH 09/18] ARM: mach-clps711x: retire custom LED code of P720T
 machine
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-10-git-send-email-bryan.wu@canonical.com>

Add tigger based LED driver into board file of P720T.
Remove old LED driver file.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-clps711x/Makefile     |  2 --
 arch/arm/mach-clps711x/common.c     |  1 -
 arch/arm/mach-clps711x/p720t-leds.c | 63 -------------------------------------
 arch/arm/mach-clps711x/p720t.c      | 61 +++++++++++++++++++++++++++++++++++
 4 files changed, 61 insertions(+), 66 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/p720t-leds.c

diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f2f0256..5872b49 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -16,5 +16,3 @@ obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
 obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
 obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
 obj-$(CONFIG_ARCH_P720T)    += p720t.o
-leds-$(CONFIG_ARCH_P720T)   += p720t-leds.o
-obj-$(CONFIG_LEDS)          += $(leds-y)
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index c965fd8..1e1ae48 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -31,7 +31,6 @@
 #include <asm/sizes.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
deleted file mode 100644
index bbc449f..0000000
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/leds.c
- *
- *  Integrator LED control routines
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-static void p720t_leds_event(led_event_t ledevt)
-{
-	unsigned long flags;
-	u32 pddr;
-
-	local_irq_save(flags);
-	switch(ledevt) {
-	case led_idle_start:
-		break;
-
-	case led_idle_end:
-		break;
-
-	case led_timer:
-		pddr = clps_readb(PDDR);
-		clps_writeb(pddr ^ 1, PDDR);
-		break;
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_p720t())
-		leds_event = p720t_leds_event;
-
-	return 0;
-}
-
-arch_initcall(leds_init);
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 42ee8f3..09113a9 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
@@ -34,6 +36,8 @@
 #include <asm/mach/map.h>
 #include <mach/syspld.h>
 
+#include <asm/hardware/clps7111.h>
+
 #include "common.h"
 
 /*
@@ -121,3 +125,60 @@ static int p720t_hw_init(void)
 
 __initcall(p720t_hw_init);
 
+/*
+ * LED controled by CPLD
+ */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void p720t_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	u8 reg = clps_readb(PDDR);
+
+	if (b != LED_OFF)
+		reg |= 0x1;
+	else
+		reg &= ~0x1;
+
+	clps_writeb(reg, PDDR);
+}
+
+static enum led_brightness p720t_led_get(struct led_classdev *cdev)
+{
+	u8 reg = clps_readb(PDDR);
+
+	return (reg & 0x1) ? LED_FULL : LED_OFF;
+}
+
+static int __init p720t_leds_init(void)
+{
+
+	struct led_classdev *cdev;
+	int ret;
+
+	if (!machine_is_p720t())
+		return -ENODEV;
+
+	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+	if (!cdev)
+		return -ENOMEM;
+
+	cdev->name = "p720t:0";
+	cdev->brightness_set = p720t_led_set;
+	cdev->brightness_get = p720t_led_get;
+	cdev->default_trigger = "heartbeat";
+
+	ret = led_classdev_register(NULL, cdev);
+	if (ret	< 0) {
+		kfree(cdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(p720t_leds_init);
+#endif
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:34 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:34 +0800
Subject: [PATCH 10/18] ARM: mach-ebsa110: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-11-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-ebsa110/Makefile |  4 +--
 arch/arm/mach-ebsa110/leds.c   | 81 ++++++++++++++++++++++++++----------------
 2 files changed, 51 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-ebsa110/Makefile b/arch/arm/mach-ebsa110/Makefile
index 6520ac8..935e4af 100644
--- a/arch/arm/mach-ebsa110/Makefile
+++ b/arch/arm/mach-ebsa110/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o io.o
+obj-y			:= core.o io.o leds.o
 obj-m			:=
 obj-n			:=
 obj-			:=
-
-obj-$(CONFIG_LEDS)	+= leds.o
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 99e14e3..0398258 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -1,52 +1,71 @@
 /*
- *  linux/arch/arm/mach-ebsa110/leds.c
+ * Driver for the LED found on the EBSA110 machine
+ * Based on Versatile and RealView machine LED code
  *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA-110 LED control routines.  We use the led as follows:
- *
- *   - Red - toggles state every 50 timer interrupts
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
-#include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include "core.h"
 
-static spinlock_t leds_lock;
-
-static void ebsa110_leds_event(led_event_t ledevt)
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+static void ebsa110_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	unsigned long flags;
+	u8 reg = __raw_readb(SOFT_BASE);
 
-	spin_lock_irqsave(&leds_lock, flags);
+	if (b != LED_OFF)
+		reg |= 0x80;
+	else
+		reg &= ~0x80;
 
-	switch(ledevt) {
-	case led_timer:
-		*(volatile unsigned char *)SOFT_BASE ^= 128;
-		break;
+	__raw_writeb(reg, SOFT_BASE);
+}
 
-	default:
-		break;
-	}
+static enum led_brightness ebsa110_led_get(struct led_classdev *cdev)
+{
+	u8 reg = __raw_readb(SOFT_BASE);
 
-	spin_unlock_irqrestore(&leds_lock, flags);
+	return (reg & 0x80) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init ebsa110_leds_init(void)
 {
-	if (machine_is_ebsa110())
-		leds_event = ebsa110_leds_event;
+
+	struct led_classdev *cdev;
+	int ret;
+
+	if (!machine_is_ebsa110())
+		return -ENODEV;
+
+	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+	if (!cdev)
+		return -ENOMEM;
+
+	cdev->name = "ebsa110:0";
+	cdev->brightness_set = ebsa110_led_set;
+	cdev->brightness_get = ebsa110_led_get;
+	cdev->default_trigger = "heartbeat";
+
+	ret = led_classdev_register(NULL, cdev);
+	if (ret	< 0) {
+		kfree(cdev);
+		return ret;
+	}
 
 	return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa110_leds_init);
+#endif
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:35 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:35 +0800
Subject: [PATCH 11/18] ARM: mach-footbridge: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-12-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-footbridge/Makefile         |   4 -
 arch/arm/mach-footbridge/ebsa285-leds.c   | 138 ------------------------------
 arch/arm/mach-footbridge/ebsa285.c        |  81 ++++++++++++++++++
 arch/arm/mach-footbridge/netwinder-hw.c   | 112 +++++++++++++++++++++---
 arch/arm/mach-footbridge/netwinder-leds.c | 138 ------------------------------
 5 files changed, 179 insertions(+), 294 deletions(-)
 delete mode 100644 arch/arm/mach-footbridge/ebsa285-leds.c
 delete mode 100644 arch/arm/mach-footbridge/netwinder-leds.c

diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 3afb1b2..0b64dd4 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,15 +14,11 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
 
-leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
-leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
-
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
 
 obj-$(CONFIG_PCI)	+=$(pci-y)
-obj-$(CONFIG_LEDS)	+=$(leds-y)
 
 obj-$(CONFIG_ISA)	+= isa.o isa-rtc.o
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
deleted file mode 100644
index 5bd2667..0000000
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/ebsa285-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * EBSA-285 control routines.
- *
- * The EBSA-285 uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Amber - On if system is not idle
- *  - Red   - currently unused
- *
- * Changelog:
- *   02-05-1999	RMK	Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_SPINLOCK(leds_lock);
-
-static void ebsa285_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&leds_lock, flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN;
-#ifndef CONFIG_LEDS_CPU
-		hw_led_state |= XBUS_LED_AMBER;
-#endif
-		led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= XBUS_LED_GREEN;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= XBUS_LED_AMBER;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~XBUS_LED_AMBER;
-		break;
-#endif
-
-	case led_halted:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~XBUS_LED_RED;
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_AMBER;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_AMBER;
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_RED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_RED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		*XBUS_LEDS = hw_led_state;
-
-	spin_unlock_irqrestore(&leds_lock, flags);
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_ebsa285())
-		leds_event = ebsa285_leds_event;
-
-	leds_event(led_start);
-
-	return 0;
-}
-
-__initcall(leds_init);
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 27716a7..b09551e 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -5,6 +5,8 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach-types.h>
@@ -13,6 +15,85 @@
 
 #include "common.h"
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct ebsa285_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} ebsa285_leds[] = {
+	{ "ebsa285:amber", "heartbeat", },
+	{ "ebsa285:green", "cpu0", },
+	{ "ebsa285:red",},
+};
+
+static void ebsa285_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct ebsa285_led *led = container_of(cdev,
+			struct ebsa285_led, cdev);
+
+	if (b != LED_OFF)
+		*XBUS_LEDS |= led->mask;
+	else
+		*XBUS_LEDS &= ~led->mask;
+}
+
+static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
+{
+	struct ebsa285_led *led = container_of(cdev,
+			struct ebsa285_led, cdev);
+
+	return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init ebsa285_leds_init(void)
+{
+	int i;
+
+	if (machine_is_ebsa285())
+		return -ENODEV;
+
+	/* 3 LEDS All ON */
+	*XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
+
+	for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
+		struct ebsa285_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = ebsa285_leds[i].name;
+		led->cdev.brightness_set = ebsa285_led_set;
+		led->cdev.brightness_get = ebsa285_led_get;
+		led->cdev.default_trigger = ebsa285_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa285_leds_init);
+#endif
+
 MACHINE_START(EBSA285, "EBSA285")
 	/* Maintainer: Russell King */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index cac9f67..d2d1433 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -12,9 +12,10 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
@@ -27,13 +28,6 @@
 #define GP1_IO_BASE		0x338
 #define GP2_IO_BASE		0x33a
 
-
-#ifdef CONFIG_LEDS
-#define DEFAULT_LEDS	0
-#else
-#define DEFAULT_LEDS	GPIO_GREEN_LED
-#endif
-
 /*
  * Winbond WB83977F accessibility stuff
  */
@@ -611,15 +605,9 @@ static void __init rwa010_init(void)
 static int __init nw_hw_init(void)
 {
 	if (machine_is_netwinder()) {
-		unsigned long flags;
-
 		wb977_init();
 		cpld_init();
 		rwa010_init();
-
-		raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-		nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
-		raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 	}
 	return 0;
 }
@@ -672,6 +660,102 @@ static void netwinder_restart(char mode, const char *cmd)
 	}
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct netwinder_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} netwinder_leds[] = {
+	{ "netwinder:green", "heartbeat", },
+	{ "netwinder:red", "cpu0", },
+};
+
+/*
+ * The LED control in Netwinder is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void netwinder_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct netwinder_led *led = container_of(cdev,
+			struct netwinder_led, cdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&nw_gpio_lock, flags);
+	reg = nw_gpio_read();
+	if (b != LED_OFF)
+		reg &= ~led->mask;
+	else
+		reg |= led->mask;
+	nw_gpio_modify_op(led->mask, reg);
+	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+}
+
+static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
+{
+	struct netwinder_led *led = container_of(cdev,
+			struct netwinder_led, cdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&nw_gpio_lock, flags);
+	reg = nw_gpio_read();
+	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+
+	return (reg & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init netwinder_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_netwinder())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
+		struct netwinder_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = netwinder_leds[i].name;
+		led->cdev.brightness_set = netwinder_led_set;
+		led->cdev.brightness_get = netwinder_led_get;
+		led->cdev.default_trigger = netwinder_leds[i].trigger;
+
+		if (i == 0)
+			led->mask = GPIO_GREEN_LED;
+		else
+			led->mask = GPIO_RED_LED;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(netwinder_leds_init);
+#endif
+
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
 	/* Maintainer: Russell King/Rebel.com */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
deleted file mode 100644
index 5a2bd89..0000000
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/netwinder-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * NetWinder LED control routines.
- *
- * The Netwinder uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Red   - On if the system is not idle
- *
- * Changelog:
- *   02-05-1999	RMK	Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_RAW_SPINLOCK(leds_lock);
-
-static void netwinder_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&leds_lock, flags);
-
-	switch (evt) {
-	case led_start:
-		led_state |= LED_STATE_ENABLED;
-		hw_led_state = GPIO_GREEN_LED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= GPIO_GREEN_LED;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~GPIO_RED_LED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= GPIO_RED_LED;
-		break;
-#endif
-
-	case led_halted:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= GPIO_RED_LED;
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_GREEN_LED;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~GPIO_GREEN_LED;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_GREEN_LED | GPIO_RED_LED;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~(GPIO_GREEN_LED | GPIO_RED_LED);
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_RED_LED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~GPIO_RED_LED;
-		break;
-
-	default:
-		break;
-	}
-
-	raw_spin_unlock_irqrestore(&leds_lock, flags);
-
-	if  (led_state & LED_STATE_ENABLED) {
-		raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-		nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
-		raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-	}
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_netwinder())
-		leds_event = netwinder_leds_event;
-
-	leds_event(led_start);
-
-	return 0;
-}
-
-__initcall(leds_init);
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:36 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:36 +0800
Subject: [PATCH 12/18] char: nwflash: remove old led event code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-13-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 drivers/char/nwflash.c | 34 ----------------------------------
 1 file changed, 34 deletions(-)

diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c
index d45c334..a0e2f7d 100644
--- a/drivers/char/nwflash.c
+++ b/drivers/char/nwflash.c
@@ -30,7 +30,6 @@
 
 #include <asm/hardware/dec21285.h>
 #include <asm/io.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 
@@ -179,9 +178,6 @@ static ssize_t flash_write(struct file *file, const char __user *buf,
 
 	written = 0;
 
-	leds_event(led_claim);
-	leds_event(led_green_on);
-
 	nBlock = (int) p >> 16;	//block # of 64K bytes
 
 	/*
@@ -258,11 +254,6 @@ static ssize_t flash_write(struct file *file, const char __user *buf,
 			printk(KERN_DEBUG "flash_write: written 0x%X bytes OK.\n", written);
 	}
 
-	/*
-	 * restore reg on exit
-	 */
-	leds_event(led_release);
-
 	mutex_unlock(&nwflash_mutex);
 
 	return written;
@@ -334,11 +325,6 @@ static int erase_block(int nBlock)
 	int temp, temp1;
 
 	/*
-	 * orange LED == erase
-	 */
-	leds_event(led_amber_on);
-
-	/*
 	 * reset footbridge to the correct offset 0 (...0..3)
 	 */
 	*CSR_ROMWRITEREG = 0;
@@ -446,12 +432,6 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 	unsigned long timeout;
 	unsigned long timeout1;
 
-	/*
-	 * red LED == write
-	 */
-	leds_event(led_amber_off);
-	leds_event(led_red_on);
-
 	pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
 
 	/*
@@ -558,17 +538,9 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 					       pWritePtr - FLASH_BASE);
 
 				/*
-				 * no LED == waiting
-				 */
-				leds_event(led_amber_off);
-				/*
 				 * wait couple ms
 				 */
 				msleep(10);
-				/*
-				 * red LED == write
-				 */
-				leds_event(led_red_on);
 
 				goto WriteRetry;
 			} else {
@@ -583,12 +555,6 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 		}
 	}
 
-	/*
-	 * green LED == read/verify
-	 */
-	leds_event(led_amber_off);
-	leds_event(led_green_on);
-
 	msleep(10);
 
 	pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:37 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:37 +0800
Subject: [PATCH 13/18] ARM: mach-pxa: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-14-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-pxa/Makefile         |   8 ---
 arch/arm/mach-pxa/idp.c            |  81 ++++++++++++++++++++++++
 arch/arm/mach-pxa/leds-idp.c       | 115 ----------------------------------
 arch/arm/mach-pxa/leds-lubbock.c   | 124 -------------------------------------
 arch/arm/mach-pxa/leds-mainstone.c | 119 -----------------------------------
 arch/arm/mach-pxa/leds.c           |  32 ----------
 arch/arm/mach-pxa/leds.h           |  13 ----
 arch/arm/mach-pxa/lubbock.c        |  95 ++++++++++++++++++++++++++++
 arch/arm/mach-pxa/mainstone.c      |  94 ++++++++++++++++++++++++++++
 9 files changed, 270 insertions(+), 411 deletions(-)
 delete mode 100644 arch/arm/mach-pxa/leds-idp.c
 delete mode 100644 arch/arm/mach-pxa/leds-lubbock.c
 delete mode 100644 arch/arm/mach-pxa/leds-mainstone.c
 delete mode 100644 arch/arm/mach-pxa/leds.c
 delete mode 100644 arch/arm/mach-pxa/leds.h

diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df..d4337e3 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -95,12 +95,4 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)	+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)	+= raumfeld.o
 obj-$(CONFIG_MACH_ZIPIT2)	+= z2.o
 
-# Support for blinky lights
-led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK)	+= leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE)	+= leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP)	+= leds-idp.o
-
-obj-$(CONFIG_LEDS)		+= $(led-y)
-
 obj-$(CONFIG_TOSA_BT)		+= tosa-bt.o
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 6ff466b..ae1e997 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -191,6 +191,87 @@ static void __init idp_map_io(void)
 	iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct idp_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} idp_leds[] = {
+	{ "idp:green", "heartbeat", },
+	{ "idp:red", "cpu0", },
+};
+
+static void idp_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct idp_led *led = container_of(cdev,
+			struct idp_led, cdev);
+	u32 reg = IDP_CPLD_LED_CONTROL;
+
+	if (b != LED_OFF)
+		reg &= ~led->mask;
+	else
+		reg |= led->mask;
+
+	IDP_CPLD_LED_CONTROL = reg;
+}
+
+static enum led_brightness idp_led_get(struct led_classdev *cdev)
+{
+	struct idp_led *led = container_of(cdev,
+			struct idp_led, cdev);
+
+	return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init idp_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_pxa_idp())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
+		struct idp_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = idp_leds[i].name;
+		led->cdev.brightness_set = idp_led_set;
+		led->cdev.brightness_get = idp_led_get;
+		led->cdev.default_trigger = idp_leds[i].trigger;
+
+		if (i == 0)
+			led->mask = IDP_HB_LED;
+		else
+			led->mask = IDP_BUSY_LED;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(idp_leds_init);
+#endif
 
 MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
 	/* Maintainer: Vibren Technologies */
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
deleted file mode 100644
index 06b0600..0000000
--- a/arch/arm/mach-pxa/leds-idp.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-idp.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs at accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Macros for actual LED manipulation should be in machine specific
- * files in this 'mach' directory.
- */
-
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa25x.h>
-#include <mach/idp.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void idp_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= IDP_HB_LED;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~IDP_BUSY_LED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= IDP_BUSY_LED;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= IDP_HB_LED;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~IDP_HB_LED;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= IDP_BUSY_LED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~IDP_BUSY_LED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		IDP_CPLD_LED_CONTROL = ( (IDP_CPLD_LED_CONTROL | IDP_LEDS_MASK) & ~hw_led_state);
-	else
-		IDP_CPLD_LED_CONTROL |= IDP_LEDS_MASK;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
deleted file mode 100644
index 0bd85c8..0000000
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-lubbock.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs at accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Major surgery on April 2004 by Nicolas Pitre for less global
- * namespace collision.  Mostly adapted the Mainstone version.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa25x.h>
-#include <mach/lubbock.h>
-
-#include "leds.h"
-
-/*
- * 8 discrete leds available for general use:
- *
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-
-#define D28			(1 << 0)
-#define D27			(1 << 1)
-#define D26			(1 << 2)
-#define D25			(1 << 3)
-#define D24			(1 << 4)
-#define D23			(1 << 5)
-#define D22			(1 << 6)
-#define D21			(1 << 7)
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void lubbock_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		hw_led_state ^= D26;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		hw_led_state &= ~D27;
-		break;
-
-	case led_idle_end:
-		hw_led_state |= D27;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		hw_led_state |= D21;
-		break;
-
-	case led_green_off:
-		hw_led_state &= ~D21;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= D22;
-		break;
-
-	case led_amber_off:
-		hw_led_state &= ~D22;
-		break;
-
-	case led_red_on:
-		hw_led_state |= D23;
-		break;
-
-	case led_red_off:
-		hw_led_state &= ~D23;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		LUB_DISC_BLNK_LED = (LUB_DISC_BLNK_LED | 0xff) & ~hw_led_state;
-	else
-		LUB_DISC_BLNK_LED |= 0xff;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
deleted file mode 100644
index 4058ab3..0000000
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-mainstone.c
- *
- * Author:     Nicolas Pitre
- * Created:    Nov 05, 2002
- * Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa27x.h>
-#include <mach/mainstone.h>
-
-#include "leds.h"
-
-
-/* 8 discrete leds available for general use: */
-#define D28			(1 << 0)
-#define D27			(1 << 1)
-#define D26			(1 << 2)
-#define D25			(1 << 3)
-#define D24			(1 << 4)
-#define D23			(1 << 5)
-#define D22			(1 << 6)
-#define D21			(1 << 7)
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void mainstone_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		hw_led_state ^= D26;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		hw_led_state &= ~D27;
-		break;
-
-	case led_idle_end:
-		hw_led_state |= D27;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		hw_led_state |= D21;
-		break;
-
-	case led_green_off:
-		hw_led_state &= ~D21;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= D22;
-		break;
-
-	case led_amber_off:
-		hw_led_state &= ~D22;
-		break;
-
-	case led_red_on:
-		hw_led_state |= D23;
-		break;
-
-	case led_red_off:
-		hw_led_state &= ~D23;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		MST_LEDCTRL = (MST_LEDCTRL | 0xff) & ~hw_led_state;
-	else
-		MST_LEDCTRL |= 0xff;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
deleted file mode 100644
index bbe4d5f..0000000
--- a/arch/arm/mach-pxa/leds.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds.c
- *
- * xscale LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-pxa_leds_init(void)
-{
-	if (machine_is_lubbock())
-		leds_event = lubbock_leds_event;
-	if (machine_is_mainstone())
-		leds_event = mainstone_leds_event;
-	if (machine_is_pxa_idp())
-		leds_event = idp_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-core_initcall(pxa_leds_init);
diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
deleted file mode 100644
index 7f0dfe0..0000000
--- a/arch/arm/mach-pxa/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-pxa/leds.h
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- *
- * blinky lights for various PXA-based systems:
- *
- */
-
-extern void idp_leds_event(led_event_t evt);
-extern void lubbock_leds_event(led_event_t evt);
-extern void mainstone_leds_event(led_event_t evt);
-extern void trizeps4_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 6bb3f47..4350283 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/major.h>
@@ -23,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/smc91x.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -549,6 +552,98 @@ static void __init lubbock_map_io(void)
 	PCFR |= PCFR_OPDE;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct lubbock_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} lubbock_leds[] = {
+	{ "lubbock:D28", "default-on", },
+	{ "lubbock:D27", "cpu0", },
+	{ "lubbock:D26", "heartbeat" },
+	{ "lubbock:D25", },
+	{ "lubbock:D24", },
+	{ "lubbock:D23", },
+	{ "lubbock:D22", },
+	{ "lubbock:D21", },
+};
+
+static void lubbock_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct lubbock_led *led = container_of(cdev,
+					 struct lubbock_led, cdev);
+	u32 reg = LUB_DISC_BLNK_LED;
+
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
+
+	LUB_DISC_BLNK_LED = reg;
+}
+
+static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
+{
+	struct lubbock_led *led = container_of(cdev,
+					 struct lubbock_led, cdev);
+	u32 reg = LUB_DISC_BLNK_LED;
+
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init lubbock_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_lubbock())
+		return -ENODEV;
+
+	/* All ON */
+	LUB_DISC_BLNK_LED |= 0xff;
+	for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
+		struct lubbock_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = lubbock_leds[i].name;
+		led->cdev.brightness_set = lubbock_led_set;
+		led->cdev.brightness_get = lubbock_led_get;
+		led->cdev.default_trigger = lubbock_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(lubbock_leds_init);
+#endif
+
 MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
 	/* Maintainer: MontaVista Software Inc. */
 	.map_io		= lubbock_map_io,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 1aebaf7..bdc6c33 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -28,6 +28,8 @@
 #include <linux/pwm_backlight.h>
 #include <linux/smc91x.h>
 #include <linux/i2c/pxa-i2c.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -613,6 +615,98 @@ static void __init mainstone_map_io(void)
  	PCFR = 0x66;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct mainstone_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} mainstone_leds[] = {
+	{ "mainstone:D28", "default-on", },
+	{ "mainstone:D27", "cpu0", },
+	{ "mainstone:D26", "heartbeat" },
+	{ "mainstone:D25", },
+	{ "mainstone:D24", },
+	{ "mainstone:D23", },
+	{ "mainstone:D22", },
+	{ "mainstone:D21", },
+};
+
+static void mainstone_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct mainstone_led *led = container_of(cdev,
+					 struct mainstone_led, cdev);
+	u32 reg = MST_LEDCTRL;
+
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
+
+	MST_LEDCTRL = reg;
+}
+
+static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
+{
+	struct mainstone_led *led = container_of(cdev,
+					 struct mainstone_led, cdev);
+	u32 reg = MST_LEDCTRL;
+
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init mainstone_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_mainstone())
+		return -ENODEV;
+
+	/* All ON */
+	MST_LEDCTRL |= 0xff;
+	for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
+		struct mainstone_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = mainstone_leds[i].name;
+		led->cdev.brightness_set = mainstone_led_set;
+		led->cdev.brightness_get = mainstone_led_get;
+		led->cdev.default_trigger = mainstone_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(mainstone_leds_init);
+#endif
+
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
 	/* Maintainer: MontaVista Software Inc. */
 	.atag_offset	= 0x100,	/* BLOB boot parameter setting */
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:38 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:38 +0800
Subject: [PATCH 14/18] ARM: plat-samsung: remove including old leds event API
 header file
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-15-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/plat-samsung/time.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 4dcb11c..60552e2 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <asm/irq.h>
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:39 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:39 +0800
Subject: [PATCH 15/18] ARM: mach-pnx4008: remove including old leds event API
 header file
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-16-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-pnx4008/time.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 0cfe8af..47a7ae9 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -25,7 +25,6 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach/time.h>
 #include <asm/errno.h>
 
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:40 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:40 +0800
Subject: [PATCH 16/18] ARM: mach-omap1: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-17-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/Makefile          |   8 -
 arch/arm/mach-omap1/board-h2.c        |  32 ++++
 arch/arm/mach-omap1/board-h3.c        |  32 ++++
 arch/arm/mach-omap1/board-osk.c       |  33 ++++
 arch/arm/mach-omap1/leds-h2p2-debug.c | 166 -------------------
 arch/arm/mach-omap1/leds-innovator.c  |  98 ------------
 arch/arm/mach-omap1/leds-osk.c        | 113 -------------
 arch/arm/mach-omap1/leds.c            |  69 --------
 arch/arm/mach-omap1/leds.h            |   3 -
 arch/arm/mach-omap1/time.c            |   1 -
 arch/arm/mach-omap1/timer32k.c        |   1 -
 arch/arm/plat-omap/Kconfig            |   3 +-
 arch/arm/plat-omap/debug-leds.c       | 293 ++++++++--------------------------
 13 files changed, 165 insertions(+), 687 deletions(-)
 delete mode 100644 arch/arm/mach-omap1/leds-h2p2-debug.c
 delete mode 100644 arch/arm/mach-omap1/leds-innovator.c
 delete mode 100644 arch/arm/mach-omap1/leds-osk.c
 delete mode 100644 arch/arm/mach-omap1/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds.h

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 398e9e5..cd169c3 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -61,14 +61,6 @@ obj-$(CONFIG_ARCH_OMAP850)		+= gpio7xx.o
 obj-$(CONFIG_ARCH_OMAP15XX)		+= gpio15xx.o
 obj-$(CONFIG_ARCH_OMAP16XX)		+= gpio16xx.o
 
-# LEDs support
-led-$(CONFIG_MACH_OMAP_H2)		+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_H3)		+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_INNOVATOR)	+= leds-innovator.o
-led-$(CONFIG_MACH_OMAP_PERSEUS2)	+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_OSK)		+= leds-osk.o
-obj-$(CONFIG_LEDS)			+= $(led-y)
-
 ifneq ($(CONFIG_FB_OMAP),)
 obj-y += lcd_dma.o
 endif
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index a28e989..bf88046 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/leds.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -306,12 +307,39 @@ static struct platform_device h2_irda_device = {
 	.resource	= h2_irda_resources,
 };
 
+static struct gpio_led h2_gpio_led_pins[] = {
+	{
+		.name		= "h2:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "h2:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data h2_gpio_led_data = {
+	.leds		= h2_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(h2_gpio_led_pins),
+};
+
+static struct platform_device h2_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &h2_gpio_led_data,
+	},
+};
+
 static struct platform_device *h2_devices[] __initdata = {
 	&h2_nor_device,
 	&h2_nand_device,
 	&h2_smc91x_device,
 	&h2_irda_device,
 	&h2_kp_device,
+	&h2_gpio_leds,
 };
 
 static void __init h2_init_smc91x(void)
@@ -406,6 +434,10 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	/* GPIO based LEDs */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	h2_smc91x_resources[1].start = gpio_to_irq(0);
 	h2_smc91x_resources[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 108a864..c6ec9b4 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/leds.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -324,6 +325,32 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 	},
 };
 
+static struct gpio_led h3_gpio_led_pins[] = {
+	{
+		.name		= "h3:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "h3:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data h3_gpio_led_data = {
+	.leds		= h3_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(h3_gpio_led_pins),
+};
+
+static struct platform_device h3_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &h3_gpio_led_data,
+	},
+};
+
 static struct platform_device *devices[] __initdata = {
 	&nor_device,
 	&nand_device,
@@ -331,6 +358,7 @@ static struct platform_device *devices[] __initdata = {
 	&intlat_device,
 	&h3_kp_device,
 	&h3_lcd_device,
+	&h3_gpio_leds,
 };
 
 static struct omap_usb_config h3_usb_config __initdata = {
@@ -398,6 +426,10 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	/* GPIO based LEDs */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	smc91x_resources[1].start = gpio_to_irq(40);
 	smc91x_resources[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index da8d872..043412c 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -380,10 +380,37 @@ static struct platform_device osk5912_lcd_device = {
 	.id		= -1,
 };
 
+static struct gpio_led mistral_gpio_led_pins[] = {
+	{
+		.name		= "mistral:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "mistral:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data mistral_gpio_led_data = {
+	.leds		= mistral_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(mistral_gpio_led_pins),
+};
+
+static struct platform_device mistral_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &mistral_gpio_led_data,
+	},
+};
+
 static struct platform_device *mistral_devices[] __initdata = {
 	&osk5912_kp_device,
 	&mistral_bl_device,
 	&osk5912_lcd_device,
+	&mistral_gpio_leds,
 };
 
 static int mistral_get_pendown_state(void)
@@ -508,6 +535,12 @@ static void __init osk_mistral_init(void)
 	if (gpio_request(2, "lcd_pwr") == 0)
 		gpio_direction_output(2, 1);
 
+	/*
+	 * GPIO based LEDs
+	 */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	i2c_register_board_info(1, mistral_i2c_board_info,
 			ARRAY_SIZE(mistral_i2c_board_info));
 
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
deleted file mode 100644
index f6b14a1..0000000
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-h2p2-debug.c
- *
- * Copyright 2003 by Texas Instruments Incorporated
- *
- * There are 16 LEDs on the debug board (all green); four may be used
- * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <plat/fpga.h>
-
-#include "leds.h"
-
-
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-
-#define LED_STATE_ENABLED	0x01
-#define LED_STATE_CLAIMED	0x02
-#define LED_TIMER_ON		0x04
-
-#define GPIO_IDLE		GPIO_LED_GREEN
-#define GPIO_TIMER		GPIO_LED_RED
-
-
-void h2p2_dbg_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	static struct h2p2_dbg_fpga __iomem *fpga;
-	static u16 led_state, hw_led_state;
-
-	local_irq_save(flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	switch (evt) {
-	case led_start:
-		if (!fpga)
-			fpga = ioremap(H2P2_DBG_FPGA_START,
-						H2P2_DBG_FPGA_SIZE);
-		if (fpga) {
-			led_state |= LED_STATE_ENABLED;
-			__raw_writew(~0, &fpga->leds);
-		}
-		break;
-
-	case led_stop:
-	case led_halted:
-		/* all leds off during suspend or shutdown */
-
-		if (! machine_is_omap_perseus2()) {
-			gpio_set_value(GPIO_TIMER, 0);
-			gpio_set_value(GPIO_IDLE, 0);
-		}
-
-		__raw_writew(~0, &fpga->leds);
-		led_state &= ~LED_STATE_ENABLED;
-		if (evt == led_halted) {
-			iounmap(fpga);
-			fpga = NULL;
-		}
-
-		goto done;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		led_state ^= LED_TIMER_ON;
-
-		if (machine_is_omap_perseus2())
-			hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-		else {
-			gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON);
-			goto done;
-		}
-
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (machine_is_omap_perseus2())
-			hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 1);
-			goto done;
-		}
-
-		break;
-
-	case led_idle_end:
-		if (machine_is_omap_perseus2())
-			hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 0);
-			goto done;
-		}
-
-		break;
-#endif
-
-	case led_green_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-		break;
-	case led_green_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-		break;
-	case led_amber_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-		break;
-	case led_red_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-		break;
-
-	case led_blue_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-		break;
-	case led_blue_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-		break;
-
-	default:
-		break;
-	}
-
-
-	/*
-	 *  Actually burn the LEDs
-	 */
-	if (led_state & LED_STATE_ENABLED)
-		__raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
deleted file mode 100644
index 3a066ee..0000000
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-innovator.c
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void innovator_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = 0;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= 0;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= 0;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~0;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~0;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= 0;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~0;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= 0;
-		break;
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
deleted file mode 100644
index 936ed42..0000000
--- a/arch/arm/mach-omap1/leds-osk.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-osk.c
- *
- * LED driver for OSK with optional Mistral QVGA board
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	(1 << 0)
-#define LED_STATE_CLAIMED	(1 << 1)
-static u8 led_state;
-
-#define	TIMER_LED		(1 << 3)	/* Mistral board */
-#define	IDLE_LED		(1 << 4)	/* Mistral board */
-static u8 hw_led_state;
-
-
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-
-/* For now, all system indicators require the Mistral board, since that
- * LED can be manipulated without a task context.  This LED is either red,
- * or green, but not both; it can't give the full "disco led" effect.
- */
-
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-static void mistral_setled(void)
-{
-	int	red = 0;
-	int	green = 0;
-
-	if (hw_led_state & TIMER_LED)
-		red = 1;
-	else if (hw_led_state & IDLE_LED)
-		green = 1;
-	/* else both sides are disabled */
-
-	gpio_set_value(GPIO_LED_GREEN, green);
-	gpio_set_value(GPIO_LED_RED, red);
-}
-
-#endif
-
-void osk_leds_event(led_event_t evt)
-{
-	unsigned long	flags;
-	u16		leds;
-
-	local_irq_save(flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	leds = hw_led_state;
-	switch (evt) {
-	case led_start:
-		led_state |= LED_STATE_ENABLED;
-		hw_led_state = 0;
-		leds = ~0;
-		break;
-
-	case led_halted:
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = 0;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		leds = ~0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-
-	case led_timer:
-		hw_led_state ^= TIMER_LED;
-		mistral_setled();
-		break;
-
-	case led_idle_start:	/* idle == off */
-		hw_led_state &= ~IDLE_LED;
-		mistral_setled();
-		break;
-
-	case led_idle_end:
-		hw_led_state |= IDLE_LED;
-		mistral_setled();
-		break;
-
-#endif	/* CONFIG_OMAP_OSK_MISTRAL */
-
-	default:
-		break;
-	}
-
-	leds ^= hw_led_state;
-
-done:
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
deleted file mode 100644
index ae6dd93..0000000
--- a/arch/arm/mach-omap1/leds.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds.c
- *
- * OMAP LEDs dispatcher
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <plat/mux.h>
-
-#include "leds.h"
-
-static int __init
-omap_leds_init(void)
-{
-	if (!cpu_class_is_omap1())
-		return -ENODEV;
-
-	if (machine_is_omap_innovator())
-		leds_event = innovator_leds_event;
-
-	else if (machine_is_omap_h2()
-			|| machine_is_omap_h3()
-			|| machine_is_omap_perseus2())
-		leds_event = h2p2_dbg_leds_event;
-
-	else if (machine_is_omap_osk())
-		leds_event = osk_leds_event;
-
-	else
-		return -1;
-
-	if (machine_is_omap_h2()
-			|| machine_is_omap_h3()
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-			|| machine_is_omap_osk()
-#endif
-			) {
-
-		/* LED1/LED2 pins can be used as GPIO (as done here), or by
-		 * the LPG (works even in deep sleep!), to drive a bicolor
-		 * LED on the H2 sample board, and another on the H2/P2
-		 * "surfer" expansion board.
-		 *
-		 * The same pins drive a LED on the OSK Mistral board, but
-		 * that's a different kind of LED (just one color at a time).
-		 */
-		omap_cfg_reg(P18_1610_GPIO3);
-		if (gpio_request(3, "LED red") == 0)
-			gpio_direction_output(3, 1);
-		else
-			printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
-
-		omap_cfg_reg(MPUIO4);
-		if (gpio_request(OMAP_MPUIO(4), "LED green") == 0)
-			gpio_direction_output(OMAP_MPUIO(4), 1);
-		else
-			printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
-	}
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(omap_leds_init);
diff --git a/arch/arm/mach-omap1/leds.h b/arch/arm/mach-omap1/leds.h
deleted file mode 100644
index a1e9fed..0000000
--- a/arch/arm/mach-omap1/leds.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern void innovator_leds_event(led_event_t evt);
-extern void h2p2_dbg_leds_event(led_event_t evt);
-extern void osk_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4062480..4d4816f 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
 
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index eae49c3..7452954 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a..aa8e668 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -41,9 +41,8 @@ config OMAP_DEBUG_DEVICES
 	  For debug cards on TI reference boards.
 
 config OMAP_DEBUG_LEDS
-	bool
+	def_bool y if NEW_LEDS
 	depends on OMAP_DEBUG_DEVICES
-	default y if LEDS_CLASS
 
 config OMAP_SMARTREFLEX
 	bool "SmartReflex support"
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cb..24e23f3 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -1,279 +1,118 @@
 /*
  * linux/arch/arm/plat-omap/debug-leds.c
  *
+ * Copyright 2011 by Bryan Wu <bryan.wu at canonical.com>
  * Copyright 2003 by Texas Instruments Incorporated
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/gpio.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
 
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
  * debug board (all green), accessed through FPGA registers.
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators
- * in preference to the ones on the debug board, for a "Disco LED" effect.
- *
- * This driver exports either the original ARM LED API, the new generic
- * one, or both.
- */
-
-static spinlock_t			lock;
-static struct h2p2_dbg_fpga __iomem	*fpga;
-static u16				led_state, hw_led_state;
-
-
-#ifdef	CONFIG_OMAP_DEBUG_LEDS
-#define new_led_api()	1
-#else
-#define new_led_api()	0
-#endif
-
-
-/*-------------------------------------------------------------------------*/
-
-/* original ARM debug LED API:
- *  - timer and idle leds (some boards use non-FPGA leds here);
- *  - up to 4 generic leds, easily accessed in-kernel (any context)
  */
 
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-#define LED_STATE_ENABLED	0x01
-#define LED_STATE_CLAIMED	0x02
-#define LED_TIMER_ON		0x04
-
-#define GPIO_IDLE		GPIO_LED_GREEN
-#define GPIO_TIMER		GPIO_LED_RED
-
-static void h2p2_dbg_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&lock, flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	switch (evt) {
-	case led_start:
-		if (fpga)
-			led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-	case led_halted:
-		/* all leds off during suspend or shutdown */
-
-		if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
-			gpio_set_value(GPIO_TIMER, 0);
-			gpio_set_value(GPIO_IDLE, 0);
-		}
-
-		__raw_writew(~0, &fpga->leds);
-		led_state &= ~LED_STATE_ENABLED;
-		goto done;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		led_state ^= LED_TIMER_ON;
-
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-		else {
-			gpio_set_value(GPIO_TIMER,
-					led_state & LED_TIMER_ON);
-			goto done;
-		}
-
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	/* LED lit iff busy */
-	case led_idle_start:
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 1);
-			goto done;
-		}
-
-		break;
+static struct h2p2_dbg_fpga __iomem *fpga;
 
-	case led_idle_end:
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 0);
-			goto done;
-		}
-
-		break;
-#endif
-
-	case led_green_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-		break;
-	case led_green_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-		break;
-	case led_amber_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-		break;
-	case led_red_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-		break;
-
-	case led_blue_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-		break;
-	case led_blue_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-		break;
-
-	default:
-		break;
-	}
-
-
-	/*
-	 *  Actually burn the LEDs
-	 */
-	if (led_state & LED_STATE_ENABLED)
-		__raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-	spin_unlock_irqrestore(&lock, flags);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* "new" LED API
- *  - with syfs access and generic triggering
- *  - not readily accessible to in-kernel drivers
- */
+static u16 fpga_led_state;
 
 struct dbg_led {
 	struct led_classdev	cdev;
 	u16			mask;
 };
 
-static struct dbg_led dbg_leds[] = {
-	/* REVISIT at least H2 uses different timer & cpu leds... */
-#ifndef CONFIG_LEDS_TIMER
-	{ .mask = 1 << 0,  .cdev.name =  "d4:green",
-		.cdev.default_trigger = "heartbeat", },
-#endif
-#ifndef CONFIG_LEDS_CPU
-	{ .mask = 1 << 1,  .cdev.name =  "d5:green", },		/* !idle */
-#endif
-	{ .mask = 1 << 2,  .cdev.name =  "d6:green", },
-	{ .mask = 1 << 3,  .cdev.name =  "d7:green", },
-
-	{ .mask = 1 << 4,  .cdev.name =  "d8:green", },
-	{ .mask = 1 << 5,  .cdev.name =  "d9:green", },
-	{ .mask = 1 << 6,  .cdev.name = "d10:green", },
-	{ .mask = 1 << 7,  .cdev.name = "d11:green", },
-
-	{ .mask = 1 << 8,  .cdev.name = "d12:green", },
-	{ .mask = 1 << 9,  .cdev.name = "d13:green", },
-	{ .mask = 1 << 10, .cdev.name = "d14:green", },
-	{ .mask = 1 << 11, .cdev.name = "d15:green", },
-
-#ifndef	CONFIG_LEDS
-	{ .mask = 1 << 12, .cdev.name = "d16:green", },
-	{ .mask = 1 << 13, .cdev.name = "d17:green", },
-	{ .mask = 1 << 14, .cdev.name = "d18:green", },
-	{ .mask = 1 << 15, .cdev.name = "d19:green", },
-#endif
+static const struct {
+	const char *name;
+	const char *trigger;
+} dbg_leds[] = {
+	{ "dbg:d4", "heartbeat", },
+	{ "dbg:d5", "cpu0", },
+	{ "dbg:d6", "default-on", },
+	{ "dbg:d7", },
+	{ "dbg:d8", },
+	{ "dbg:d9", },
+	{ "dbg:d10", },
+	{ "dbg:d11", },
+	{ "dbg:d12", },
+	{ "dbg:d13", },
+	{ "dbg:d14", },
+	{ "dbg:d15", },
+	{ "dbg:d16", },
+	{ "dbg:d17", },
+	{ "dbg:d18", },
+	{ "dbg:d19", },
 };
 
-static void
-fpga_led_set(struct led_classdev *cdev, enum led_brightness value)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static void dbg_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	struct dbg_led	*led = container_of(cdev, struct dbg_led, cdev);
-	unsigned long	flags;
+	struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+	u16 reg;
 
-	spin_lock_irqsave(&lock, flags);
-	if (value == LED_OFF)
-		hw_led_state &= ~led->mask;
+	reg = __raw_readw(&fpga->leds);
+	if (b != LED_OFF)
+		reg |= led->mask;
 	else
-		hw_led_state |= led->mask;
-	__raw_writew(~hw_led_state, &fpga->leds);
-	spin_unlock_irqrestore(&lock, flags);
+		reg &= ~led->mask;
+	__raw_writew(reg, &fpga->leds);
 }
 
-static void __init newled_init(struct device *dev)
+static enum led_brightness dbg_led_get(struct led_classdev *cdev)
 {
-	unsigned	i;
-	struct dbg_led	*led;
-	int		status;
+	struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+	u16 reg;
 
-	for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) {
-		led->cdev.brightness_set = fpga_led_set;
-		status = led_classdev_register(dev, &led->cdev);
-		if (status < 0)
-			break;
-	}
-	return;
+	reg = __raw_readw(&fpga->leds);
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
 
-
-/*-------------------------------------------------------------------------*/
-
-static int /* __init */ fpga_probe(struct platform_device *pdev)
+static int fpga_probe(struct platform_device *pdev)
 {
 	struct resource	*iomem;
-
-	spin_lock_init(&lock);
+	int i;
 
 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iomem)
 		return -ENODEV;
 
 	fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
-	__raw_writew(~0, &fpga->leds);
+	__raw_writew(0xff, &fpga->leds);
+
+	for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
+		struct dbg_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
 
-#ifdef	CONFIG_LEDS
-	leds_event = h2p2_dbg_leds_event;
-	leds_event(led_start);
-#endif
+		led->cdev.name = dbg_leds[i].name;
+		led->cdev.brightness_set = dbg_led_set;
+		led->cdev.brightness_get = dbg_led_get;
+		led->cdev.default_trigger = dbg_leds[i].trigger;
+		led->mask = BIT(i);
 
-	if (new_led_api()) {
-		newled_init(&pdev->dev);
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
 	}
 
 	return 0;
@@ -281,13 +120,15 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
 
 static int fpga_suspend_noirq(struct device *dev)
 {
-	__raw_writew(~0, &fpga->leds);
+	fpga_led_state = __raw_readw(&fpga->leds);
+	__raw_writew(0xff, &fpga->leds);
+
 	return 0;
 }
 
 static int fpga_resume_noirq(struct device *dev)
 {
-	__raw_writew(~hw_led_state, &fpga->leds);
+	__raw_writew(~fpga_led_state, &fpga->leds);
 	return 0;
 }
 
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:41 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:41 +0800
Subject: [PATCH 17/18] ARM: mach-sa1100: retire custom LED code
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-18-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-sa1100/Makefile       |   9 ---
 arch/arm/mach-sa1100/assabet.c      |  85 +++++++++++++++++++++++++++
 arch/arm/mach-sa1100/badge4.c       |  30 ++++++++++
 arch/arm/mach-sa1100/cerf.c         |  42 ++++++++++++++
 arch/arm/mach-sa1100/hackkit.c      |  32 ++++++++++
 arch/arm/mach-sa1100/lart.c         |  26 +++++++++
 arch/arm/mach-sa1100/leds-assabet.c | 113 ------------------------------------
 arch/arm/mach-sa1100/leds-badge4.c  | 110 -----------------------------------
 arch/arm/mach-sa1100/leds-cerf.c    | 109 ----------------------------------
 arch/arm/mach-sa1100/leds-hackkit.c | 111 -----------------------------------
 arch/arm/mach-sa1100/leds-lart.c    | 100 -------------------------------
 arch/arm/mach-sa1100/leds.c         |  50 ----------------
 arch/arm/mach-sa1100/leds.h         |  13 -----
 13 files changed, 215 insertions(+), 615 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/leds-assabet.c
 delete mode 100644 arch/arm/mach-sa1100/leds-badge4.c
 delete mode 100644 arch/arm/mach-sa1100/leds-cerf.c
 delete mode 100644 arch/arm/mach-sa1100/leds-hackkit.c
 delete mode 100644 arch/arm/mach-sa1100/leds-lart.c
 delete mode 100644 arch/arm/mach-sa1100/leds.c
 delete mode 100644 arch/arm/mach-sa1100/leds.h

diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 60b97ec..1aed9e7 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -7,21 +7,17 @@ obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
-led-y := leds.o
 
 obj-$(CONFIG_CPU_FREQ_SA1100)		+= cpu-sa1100.o
 obj-$(CONFIG_CPU_FREQ_SA1110)		+= cpu-sa1110.o
 
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)		+= assabet.o
-led-$(CONFIG_SA1100_ASSABET)		+= leds-assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET)		+= neponset.o
 
 obj-$(CONFIG_SA1100_BADGE4)		+= badge4.o
-led-$(CONFIG_SA1100_BADGE4)		+= leds-badge4.o
 
 obj-$(CONFIG_SA1100_CERF)		+= cerf.o
-led-$(CONFIG_SA1100_CERF)		+= leds-cerf.o
 
 obj-$(CONFIG_SA1100_COLLIE)		+= collie.o
 
@@ -29,13 +25,11 @@ obj-$(CONFIG_SA1100_H3100)		+= h3100.o h3xxx.o
 obj-$(CONFIG_SA1100_H3600)		+= h3600.o h3xxx.o
 
 obj-$(CONFIG_SA1100_HACKKIT)		+= hackkit.o
-led-$(CONFIG_SA1100_HACKKIT)		+= leds-hackkit.o
 
 obj-$(CONFIG_SA1100_JORNADA720)		+= jornada720.o
 obj-$(CONFIG_SA1100_JORNADA720_SSP)	+= jornada720_ssp.o
 
 obj-$(CONFIG_SA1100_LART)		+= lart.o
-led-$(CONFIG_SA1100_LART)		+= leds-lart.o
 
 obj-$(CONFIG_SA1100_NANOENGINE)		+= nanoengine.o
 obj-$(CONFIG_PCI_NANOENGINE)		+= pci-nanoengine.o
@@ -46,9 +40,6 @@ obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
 
 obj-$(CONFIG_SA1100_SIMPAD)		+= simpad.o
 
-# LEDs support
-obj-$(CONFIG_LEDS) += $(led-y)
-
 # Miscellaneous functions
 obj-$(CONFIG_PM)			+= pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)		+= ssp.o
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d1dc7f1..0359a66 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
 
 #include <video/sa1100fb.h>
 
@@ -529,6 +531,89 @@ static void __init assabet_map_io(void)
 	sa1100_register_uart(2, 3);
 }
 
+/* LEDs */
+#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+struct assabet_led {
+	struct led_classdev cdev;
+	u32 mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} assabet_leds[] = {
+	{ "assabet:red", "cpu0",},
+	{ "assabet:green", "heartbeat", },
+};
+
+/*
+ * The LED control in Assabet is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void assabet_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct assabet_led *led = container_of(cdev,
+			struct assabet_led, cdev);
+
+	if (b != LED_OFF)
+		ASSABET_BCR_clear(led->mask);
+	else
+		ASSABET_BCR_set(led->mask);
+}
+
+static enum led_brightness assabet_led_get(struct led_classdev *cdev)
+{
+	struct assabet_led *led = container_of(cdev,
+			struct assabet_led, cdev);
+
+	return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init assabet_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_assabet())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
+		struct assabet_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = assabet_leds[i].name;
+		led->cdev.brightness_set = assabet_led_set;
+		led->cdev.brightness_get = assabet_led_get;
+		led->cdev.default_trigger = assabet_leds[i].trigger;
+
+		if (!i)
+			led->mask = ASSABET_BCR_LED_RED;
+		else
+			led->mask = ASSABET_BCR_LED_GREEN;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(assabet_leds_init);
+#endif
 
 MACHINE_START(ASSABET, "Intel-Assabet")
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b30fb99..038df48 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -22,6 +22,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -76,8 +78,36 @@ static struct platform_device sa1111_device = {
 	.resource	= sa1111_resources,
 };
 
+/* LEDs */
+struct gpio_led badge4_gpio_leds[] = {
+	{
+		.name			= "badge4:red",
+		.default_trigger	= "heartbeat",
+		.gpio			= 7,
+	},
+	{
+		.name			= "badge4:green",
+		.default_trigger	= "cpu0",
+		.gpio			= 9,
+	},
+};
+
+static struct gpio_led_platform_data badge4_gpio_led_info = {
+	.leds		= badge4_gpio_leds,
+	.num_leds	= ARRAY_SIZE(badge4_gpio_leds),
+};
+
+static struct platform_device badge4_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &badge4_gpio_led_info,
+	}
+};
+
 static struct platform_device *devices[] __initdata = {
 	&sa1111_device,
+	&badge4_leds,
 };
 
 static int __init badge4_sa1111_init(void)
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 09d7f4b..5240f10 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -17,6 +17,8 @@
 #include <linux/irq.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -43,8 +45,48 @@ static struct platform_device cerfuart2_device = {
 	.resource	= cerfuart2_resources,
 };
 
+/* LEDs */
+struct gpio_led cerf_gpio_leds[] = {
+	{
+		.name			= "cerf:d0",
+		.default_trigger	= "heartbeat",
+		.gpio			= 0,
+	},
+	{
+		.name			= "cerf:d1",
+		.default_trigger	= "cpu0",
+		.gpio			= 1,
+	},
+	{
+		.name			= "cerf:d2",
+		.default_trigger	= "default-on",
+		.gpio			= 2,
+	},
+	{
+		.name			= "cerf:d3",
+		.default_trigger	= "default-on",
+		.gpio			= 3,
+	},
+
+};
+
+static struct gpio_led_platform_data cerf_gpio_led_info = {
+	.leds		= cerf_gpio_leds,
+	.num_leds	= ARRAY_SIZE(cerf_gpio_leds),
+};
+
+static struct platform_device cerf_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &cerf_gpio_led_info,
+	}
+};
+
+
 static struct platform_device *cerf_devices[] __initdata = {
 	&cerfuart2_device,
+	&cerf_leds,
 };
 
 #ifdef CONFIG_SA1100_CERF_FLASH_32MB
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 7f86bd9..fc106aa 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -21,6 +21,10 @@
 #include <linux/serial_core.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -183,9 +187,37 @@ static struct flash_platform_data hackkit_flash_data = {
 static struct resource hackkit_flash_resource =
 	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
+/* LEDs */
+struct gpio_led hackkit_gpio_leds[] = {
+	{
+		.name			= "hackkit:red",
+		.default_trigger	= "cpu0",
+		.gpio			= 22,
+	},
+	{
+		.name			= "hackkit:green",
+		.default_trigger	= "heartbeat",
+		.gpio			= 23,
+	},
+};
+
+static struct gpio_led_platform_data hackkit_gpio_led_info = {
+	.leds		= hackkit_gpio_leds,
+	.num_leds	= ARRAY_SIZE(hackkit_gpio_leds),
+};
+
+static struct platform_device hackkit_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &hackkit_gpio_led_info,
+	}
+};
+
 static void __init hackkit_init(void)
 {
 	sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
+	platform_device_register(&hackkit_leds);
 }
 
 /**********************************************************************
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index b775a0a..b2ce04b 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -5,6 +5,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <video/sa1100fb.h>
 
@@ -126,6 +129,27 @@ static struct map_desc lart_io_desc[] __initdata = {
 	}
 };
 
+/* LEDs */
+struct gpio_led lart_gpio_leds[] = {
+	{
+		.name			= "lart:red",
+		.default_trigger	= "cpu0",
+		.gpio			= 23,
+	},
+};
+
+static struct gpio_led_platform_data lart_gpio_led_info = {
+	.leds		= lart_gpio_leds,
+	.num_leds	= ARRAY_SIZE(lart_gpio_leds),
+};
+
+static struct platform_device lart_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &lart_gpio_led_info,
+	}
+};
 static void __init lart_map_io(void)
 {
 	sa1100_map_io();
@@ -139,6 +163,8 @@ static void __init lart_map_io(void)
 	GPDR |= GPIO_UART_TXD;
 	GPDR &= ~GPIO_UART_RXD;
 	PPAR |= PPAR_UPR;
+
+	platform_device_register(&lart_leds);
 }
 
 MACHINE_START(LART, "LART")
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
deleted file mode 100644
index 3699176..0000000
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-assabet.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Assabet uses the LEDs as follows:
- *   - Green - toggles state every 50 timer interrupts
- *   - Red   - on if system is not idle
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/assabet.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define ASSABET_BCR_LED_MASK	(ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED)
-
-void assabet_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= ASSABET_BCR_LED_GREEN;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= ASSABET_BCR_LED_RED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~ASSABET_BCR_LED_RED;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~ASSABET_BCR_LED_RED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= ASSABET_BCR_LED_RED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
deleted file mode 100644
index f99fac3..0000000
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-badge4.c
- *
- * Author: Christopher Hoover <ch at hpl.hp.com>
- * Copyright (C) 2002 Hewlett-Packard Company
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_RED		GPIO_GPIO(7)
-#define LED_GREEN       GPIO_GPIO(9)
-#define LED_MASK	(LED_RED|LED_GREEN)
-
-#define LED_IDLE	LED_GREEN
-#define LED_TIMER	LED_RED
-
-void badge4_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-	local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-		GPDR |= LED_MASK;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_TIMER;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-		/* LED off when system is idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_IDLE;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_IDLE;
-                break;
-#endif
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_RED;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_RED;
-                break;
-
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_GREEN;
-                break;
-
-	default:
-		break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
deleted file mode 100644
index 040540f..0000000
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-cerf.c
- *
- * Author: ???
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_D0          GPIO_GPIO(0)
-#define LED_D1          GPIO_GPIO(1)
-#define LED_D2          GPIO_GPIO(2)
-#define LED_D3          GPIO_GPIO(3)
-#define LED_MASK        (LED_D0|LED_D1|LED_D2|LED_D3)
-
-void cerf_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-	local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_D0;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-#endif
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D2;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D2;
-                break;
-
-        case led_amber_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D3;
-                break;
-
-        case led_amber_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D3;
-                break;
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
deleted file mode 100644
index 6a23524..0000000
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-hackkit.c
- *
- * based on leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw at its.tudelft.nl), April 21, 2000
- * (C) Stefan Eletzhofer <stefan.eletzhofer at eletztrick.de>, 2002
- *
- * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used
- * as cpu led, the green one is used as timer led.
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_GREEN    GPIO_GPIO23
-#define LED_RED    GPIO_GPIO22
-#define LED_MASK  (LED_RED | LED_GREEN)
-
-void hackkit_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-		case led_start:
-			/* pin 22/23 are outputs */
-			GPDR |= LED_MASK;
-			hw_led_state = LED_MASK;
-			led_state = LED_STATE_ENABLED;
-			break;
-
-		case led_stop:
-			led_state &= ~LED_STATE_ENABLED;
-			break;
-
-		case led_claim:
-			led_state |= LED_STATE_CLAIMED;
-			hw_led_state = LED_MASK;
-			break;
-
-		case led_release:
-			led_state &= ~LED_STATE_CLAIMED;
-			hw_led_state = LED_MASK;
-			break;
-
-#ifdef CONFIG_LEDS_TIMER
-		case led_timer:
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state ^= LED_GREEN;
-			break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-		case led_idle_start:
-			/* The LART people like the LED to be off when the
-			   system is idle... */
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state &= ~LED_RED;
-			break;
-
-		case led_idle_end:
-			/* ... and on if the system is not idle */
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state |= LED_RED;
-			break;
-#endif
-
-		case led_red_on:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state &= ~LED_RED;
-			break;
-
-		case led_red_off:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state |= LED_RED;
-			break;
-
-		case led_green_on:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state &= ~LED_GREEN;
-			break;
-
-		case led_green_off:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state |= LED_GREEN;
-			break;
-
-		default:
-			break;
-	}
-
-	/* Now set the GPIO state, or nothing will happen at all */
-	if (led_state & LED_STATE_ENABLED) {
-		GPSR = hw_led_state;
-		GPCR = hw_led_state ^ LED_MASK;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
deleted file mode 100644
index a51830c..0000000
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw at its.tudelft.nl), April 21, 2000
- *
- * LART uses the LED as follows:
- *   - GPIO23 is the LED, on if system is not idle
- *  You can use both CONFIG_LEDS_CPU and CONFIG_LEDS_TIMER at the same
- *  time, but in that case the timer events will still dictate the
- *  pace of the LED.
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_23    GPIO_GPIO23
-#define LED_MASK  (LED_23)
-
-void lart_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:
-		/* pin 23 is output pin */
-		GPDR |= LED_23;
-		hw_led_state = LED_MASK;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = LED_MASK;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = LED_MASK;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= LED_23;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		/* The LART people like the LED to be off when the
-                   system is idle... */
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~LED_23;
-		break;
-
-	case led_idle_end:
-		/* ... and on if the system is not idle */
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= LED_23;
-		break;
-#endif
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~LED_23;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= LED_23;
-		break;
-
-	default:
-		break;
-	}
-
-	/* Now set the GPIO state, or nothing will happen at all */
-	if (led_state & LED_STATE_ENABLED) {
-		GPSR = hw_led_state;
-		GPCR = hw_led_state ^ LED_MASK;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c
deleted file mode 100644
index 5fe71a0..0000000
--- a/arch/arm/mach-sa1100/leds.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds.c
- *
- * SA1100 LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-sa1100_leds_init(void)
-{
-	if (machine_is_assabet())
-		leds_event = assabet_leds_event;
-	if (machine_is_consus())
-		leds_event = consus_leds_event;
-	if (machine_is_badge4())
-		leds_event = badge4_leds_event;
-	if (machine_is_brutus())
-		leds_event = brutus_leds_event;
-	if (machine_is_cerf())
-		leds_event = cerf_leds_event;
-	if (machine_is_flexanet())
-		leds_event = flexanet_leds_event;
-	if (machine_is_graphicsclient())
-		leds_event = graphicsclient_leds_event;
-	if (machine_is_hackkit())
-		leds_event = hackkit_leds_event;
-	if (machine_is_lart())
-		leds_event = lart_leds_event;
-	if (machine_is_pfs168())
-		leds_event = pfs168_leds_event;
-	if (machine_is_graphicsmaster())
-		leds_event = graphicsmaster_leds_event;
-	if (machine_is_adsbitsy())
-		leds_event = adsbitsy_leds_event;
-	if (machine_is_pt_system3())
-		leds_event = system3_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-core_initcall(sa1100_leds_init);
diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h
deleted file mode 100644
index 776b602..0000000
--- a/arch/arm/mach-sa1100/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern void assabet_leds_event(led_event_t evt);
-extern void badge4_leds_event(led_event_t evt);
-extern void consus_leds_event(led_event_t evt);
-extern void brutus_leds_event(led_event_t evt);
-extern void cerf_leds_event(led_event_t evt);
-extern void flexanet_leds_event(led_event_t evt);
-extern void graphicsclient_leds_event(led_event_t evt);
-extern void hackkit_leds_event(led_event_t evt);
-extern void lart_leds_event(led_event_t evt);
-extern void pfs168_leds_event(led_event_t evt);
-extern void graphicsmaster_leds_event(led_event_t evt);
-extern void adsbitsy_leds_event(led_event_t evt);
-extern void system3_leds_event(led_event_t evt);
-- 
1.7.11.4



From bryan.wu at canonical.com  Mon Aug 13 01:51:42 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 13 Aug 2012 13:51:42 +0800
Subject: [PATCH 18/18] ARM: use new LEDS CPU trigger stub to replace old one
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1344837102-11850-19-git-send-email-bryan.wu@canonical.com>

Cc:  Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/Kconfig            |  53 -------------------
 arch/arm/include/asm/leds.h |  50 ------------------
 arch/arm/kernel/Makefile    |   1 -
 arch/arm/kernel/leds.c      | 121 --------------------------------------------
 arch/arm/kernel/process.c   |   6 +--
 arch/arm/kernel/time.c      |  17 -------
 6 files changed, 3 insertions(+), 245 deletions(-)
 delete mode 100644 arch/arm/include/asm/leds.h
 delete mode 100644 arch/arm/kernel/leds.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c..dc57d37 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1739,59 +1739,6 @@ config FORCE_MAX_ZONEORDER
 	  This config option is actually maximum order plus one. For example,
 	  a value of 11 means that the largest free memory block is 2^10 pages.
 
-config LEDS
-	bool "Timer and CPU usage LEDs"
-	depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-		   ARCH_EBSA285 || ARCH_INTEGRATOR || \
-		   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
-		   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
-		   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-		   ARCH_AT91 || ARCH_DAVINCI || \
-		   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
-	help
-	  If you say Y here, the LEDs on your machine will be used
-	  to provide useful information about your current system status.
-
-	  If you are compiling a kernel for a NetWinder or EBSA-285, you will
-	  be able to select which LEDs are active using the options below. If
-	  you are compiling a kernel for the EBSA-110 or the LART however, the
-	  red LED will simply flash regularly to indicate that the system is
-	  still functional. It is safe to say Y here if you have a CATS
-	  system, but the driver will do nothing.
-
-config LEDS_TIMER
-	bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
-			    OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-			    || MACH_OMAP_PERSEUS2
-	depends on LEDS
-	depends on !GENERIC_CLOCKEVENTS
-	default y if ARCH_EBSA110
-	help
-	  If you say Y here, one of the system LEDs (the green one on the
-	  NetWinder, the amber one on the EBSA285, or the red one on the LART)
-	  will flash regularly to indicate that the system is still
-	  operational. This is mainly useful to kernel hackers who are
-	  debugging unstable kernels.
-
-	  The LART uses the same LED for both Timer LED and CPU usage LED
-	  functions. You may choose to use both, but the Timer LED function
-	  will overrule the CPU usage LED.
-
-config LEDS_CPU
-	bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
-			!ARCH_OMAP) \
-			|| OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-			|| MACH_OMAP_PERSEUS2
-	depends on LEDS
-	help
-	  If you say Y here, the red LED will be used to give a good real
-	  time indication of CPU usage, by lighting whenever the idle task
-	  is not currently executing.
-
-	  The LART uses the same LED for both Timer LED and CPU usage LED
-	  functions. You may choose to use both, but the Timer LED function
-	  will overrule the CPU usage LED.
-
 config ALIGNMENT_TRAP
 	bool
 	depends on CPU_CP15_MMU
diff --git a/arch/arm/include/asm/leds.h b/arch/arm/include/asm/leds.h
deleted file mode 100644
index c545739..0000000
--- a/arch/arm/include/asm/leds.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/include/asm/leds.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Event-driven interface for LEDs on machines
- *  Added led_start and led_stop- Alex Holden, 28th Dec 1998.
- */
-#ifndef ASM_ARM_LEDS_H
-#define ASM_ARM_LEDS_H
-
-
-typedef enum {
-	led_idle_start,
-	led_idle_end,
-	led_timer,
-	led_start,
-	led_stop,
-	led_claim,		/* override idle & timer leds */
-	led_release,		/* restore idle & timer leds */
-	led_start_timer_mode,
-	led_stop_timer_mode,
-	led_green_on,
-	led_green_off,
-	led_amber_on,
-	led_amber_off,
-	led_red_on,
-	led_red_off,
-	led_blue_on,
-	led_blue_off,
-	/*
-	 * I want this between led_timer and led_start, but
-	 * someone has decided to export this to user space
-	 */
-	led_halted
-} led_event_t;
-
-/* Use this routine to handle LEDs */
-
-#ifdef CONFIG_LEDS
-extern void (*leds_event)(led_event_t);
-#else
-#define leds_event(e)
-#endif
-
-#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..8951577 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -21,7 +21,6 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
 
-obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)		+= etm.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)	+= dma.o
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
deleted file mode 100644
index 1911dae..0000000
--- a/arch/arm/kernel/leds.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * LED support code, ripped out of arch/arm/kernel/time.c
- *
- *  Copyright (C) 1994-2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/string.h>
-
-#include <asm/leds.h>
-
-static void dummy_leds_event(led_event_t evt)
-{
-}
-
-void (*leds_event)(led_event_t) = dummy_leds_event;
-
-struct leds_evt_name {
-	const char	name[8];
-	int		on;
-	int		off;
-};
-
-static const struct leds_evt_name evt_names[] = {
-	{ "amber", led_amber_on, led_amber_off },
-	{ "blue",  led_blue_on,  led_blue_off  },
-	{ "green", led_green_on, led_green_off },
-	{ "red",   led_red_on,   led_red_off   },
-};
-
-static ssize_t leds_store(struct device *dev,
-			struct device_attribute *attr,
-			const char *buf, size_t size)
-{
-	int ret = -EINVAL, len = strcspn(buf, " ");
-
-	if (len > 0 && buf[len] == '\0')
-		len--;
-
-	if (strncmp(buf, "claim", len) == 0) {
-		leds_event(led_claim);
-		ret = size;
-	} else if (strncmp(buf, "release", len) == 0) {
-		leds_event(led_release);
-		ret = size;
-	} else {
-		int i;
-
-		for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-			if (strlen(evt_names[i].name) != len ||
-			    strncmp(buf, evt_names[i].name, len) != 0)
-				continue;
-			if (strncmp(buf+len, " on", 3) == 0) {
-				leds_event(evt_names[i].on);
-				ret = size;
-			} else if (strncmp(buf+len, " off", 4) == 0) {
-				leds_event(evt_names[i].off);
-				ret = size;
-			}
-			break;
-		}
-	}
-	return ret;
-}
-
-static DEVICE_ATTR(event, 0200, NULL, leds_store);
-
-static struct bus_type leds_subsys = {
-	.name		= "leds",
-	.dev_name	= "leds",
-};
-
-static struct device leds_device = {
-	.id		= 0,
-	.bus		= &leds_subsys,
-};
-
-static int leds_suspend(void)
-{
-	leds_event(led_stop);
-	return 0;
-}
-
-static void leds_resume(void)
-{
-	leds_event(led_start);
-}
-
-static void leds_shutdown(void)
-{
-	leds_event(led_halted);
-}
-
-static struct syscore_ops leds_syscore_ops = {
-	.shutdown	= leds_shutdown,
-	.suspend	= leds_suspend,
-	.resume		= leds_resume,
-};
-
-static int __init leds_init(void)
-{
-	int ret;
-	ret = subsys_system_register(&leds_subsys, NULL);
-	if (ret == 0)
-		ret = device_register(&leds_device);
-	if (ret == 0)
-		ret = device_create_file(&leds_device, &dev_attr_event);
-	if (ret == 0)
-		register_syscore_ops(&leds_syscore_ops);
-	return ret;
-}
-
-device_initcall(leds_init);
-
-EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 19c95ea..864580a 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -31,9 +31,9 @@
 #include <linux/random.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
+#include <linux/leds.h>
 
 #include <asm/cacheflush.h>
-#include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
@@ -189,7 +189,7 @@ void cpu_idle(void)
 	while (1) {
 		tick_nohz_idle_enter();
 		rcu_idle_enter();
-		leds_event(led_idle_start);
+		ledtrig_cpu(CPU_LED_IDLE_START);
 		while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
 			if (cpu_is_offline(smp_processor_id()))
@@ -220,7 +220,7 @@ void cpu_idle(void)
 			} else
 				local_irq_enable();
 		}
-		leds_event(led_idle_end);
+		ledtrig_cpu(CPU_LED_IDLE_END);
 		rcu_idle_exit();
 		tick_nohz_idle_exit();
 		schedule_preempt_disabled();
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index af2afb0..09be0c3 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -25,7 +25,6 @@
 #include <linux/timer.h>
 #include <linux/irq.h>
 
-#include <asm/leds.h>
 #include <asm/thread_info.h>
 #include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
@@ -80,21 +79,6 @@ u32 arch_gettimeoffset(void)
 }
 #endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
 
-#ifdef CONFIG_LEDS_TIMER
-static inline void do_leds(void)
-{
-	static unsigned int count = HZ/2;
-
-	if (--count == 0) {
-		count = HZ/2;
-		leds_event(led_timer);
-	}
-}
-#else
-#define	do_leds()
-#endif
-
-
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
  * Kernel system timer support.
@@ -102,7 +86,6 @@ static inline void do_leds(void)
 void timer_tick(void)
 {
 	profile_tick(CPU_PROFILING);
-	do_leds();
 	xtime_update(1);
 #ifndef CONFIG_SMP
 	update_process_times(user_mode(get_irq_regs()));
-- 
1.7.11.4



From m.szyprowski at samsung.com  Mon Aug 13 02:15:22 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 13 Aug 2012 08:15:22 +0200
Subject: [RFC PATCH] ARM: add coherent dma ops
In-Reply-To: <1344490622-20029-1-git-send-email-robherring2@gmail.com>
References: <1344490622-20029-1-git-send-email-robherring2@gmail.com>
Message-ID: <007b01cd791b$07adc900$17095b00$%szyprowski@samsung.com>

Hi Rob,

On Thursday, August 09, 2012 7:37 AM Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> arch_is_coherent is problematic as it is a global symbol. This
> doesn't work for multi-platform kernels or platforms which can support
> per device coherent DMA.
> 
> This adds arm_coherent_dma_ops to be used for devices which connected
> coherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops
> are modified at boot when arch_is_coherent is true.

Thanks for the patch. I had something similar on my TODO list, but had not enough time for
it. I like this patch but I have some comments.
 
> This does not address arch_is_coherent used in iommu dma ops.

In the initial version we might get rid of arch_is_coherent() usage in iommu dma ops and
implement it when a real coherent hw with iommu will be available.

> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Marek Szyprowski <m.szyprowski at samsung.com>
> ---
> Compile tested only.

>  arch/arm/mm/dma-mapping.c |   89 +++++++++++++++++++++++++++++++++++++++------
>  1 file changed, 77 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index c2cdf65..8875cd4 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -73,11 +73,18 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
>  	     unsigned long offset, size_t size, enum dma_data_direction dir,
>  	     struct dma_attrs *attrs)
>  {
> -	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
> +	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
>  		__dma_page_cpu_to_dev(page, offset, size, dir);
>  	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
>  }
> 
> +static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
> +	     unsigned long offset, size_t size, enum dma_data_direction dir,
> +	     struct dma_attrs *attrs)
> +{
> +	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
> +}
> +
>  /**
>   * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
>   * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> @@ -96,7 +103,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
>  		size_t size, enum dma_data_direction dir,
>  		struct dma_attrs *attrs)
>  {
> -	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
> +	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
>  		__dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
>  				      handle & ~PAGE_MASK, size, dir);
>  }
> @@ -106,8 +113,7 @@ static void arm_dma_sync_single_for_cpu(struct device *dev,
>  {
>  	unsigned int offset = handle & (PAGE_SIZE - 1);
>  	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
> -	if (!arch_is_coherent())
> -		__dma_page_dev_to_cpu(page, offset, size, dir);
> +	__dma_page_dev_to_cpu(page, offset, size, dir);
>  }
> 
>  static void arm_dma_sync_single_for_device(struct device *dev,
> @@ -115,8 +121,7 @@ static void arm_dma_sync_single_for_device(struct device *dev,
>  {
>  	unsigned int offset = handle & (PAGE_SIZE - 1);
>  	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
> -	if (!arch_is_coherent())
> -		__dma_page_cpu_to_dev(page, offset, size, dir);
> +	__dma_page_cpu_to_dev(page, offset, size, dir);
>  }
> 
>  static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
> @@ -138,6 +143,40 @@ struct dma_map_ops arm_dma_ops = {
>  };
>  EXPORT_SYMBOL(arm_dma_ops);
> 
> +static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
> +	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
> +static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +				  dma_addr_t handle, struct dma_attrs *attrs);
> +
> +struct dma_map_ops arm_coherent_dma_ops = {
> +	.alloc			= arm_coherent_dma_alloc,
> +	.free			= arm_coherent_dma_free,
> +	.mmap			= arm_dma_mmap,
> +	.get_sgtable		= arm_dma_get_sgtable,
> +	.map_page		= arm_coherent_dma_map_page,
> +	.map_sg			= arm_dma_map_sg,
> +	.set_dma_mask		= arm_dma_set_mask,
> +};
> +EXPORT_SYMBOL(arm_coherent_dma_ops);
> +
> +static int __init dma_map_init(void)
> +{
> +	if (!arch_is_coherent())
> +		return 0;
> +
> +	arm_dma_ops.map_page = arm_coherent_dma_map_page;
> +	arm_dma_ops.unmap_page = NULL;
> +	arm_dma_ops.map_sg = NULL;
> +	arm_dma_ops.unmap_sg = NULL;
> +	arm_dma_ops.sync_single_for_cpu = NULL;
> +	arm_dma_ops.sync_single_for_device = NULL;
> +	arm_dma_ops.sync_sg_for_cpu = NULL;
> +	arm_dma_ops.sync_sg_for_device = NULL;
> +	arm_dma_ops.alloc = arm_coherent_dma_alloc;
> +	arm_dma_ops.free = arm_coherent_dma_free;
> +}
> +core_initcall(dma_map_init);

I would implement it in a bit different way. Overwriting structure entries is not the 
cleanest approach and might lead to some misunderstandings. I would rather change 
get_dma_ops() function in arch/arm/include/asm/dma-mapping.h to something like this:

static inline struct dma_map_ops *get_dma_ops(struct device *dev)
{
        if (dev && dev->archdata.dma_ops)
                return dev->archdata.dma_ops;
        return !arch_is_coherent() ? &arm_dma_ops : &arm_coherent_dma_ops;
}

This way the code is easy to understand and compiler can easily optimize out the above 
check for 99% of architectures which are either coherent or not. In case of partially 
coherent architectures, arch_is_coherent() will probably return false and coherent 
devices will get their dma_map_ops initialized by platform code.

> +
>  static u64 get_coherent_dma_mask(struct device *dev)
>  {
>  	u64 mask = (u64)arm_dma_limit;
> @@ -538,7 +577,7 @@ static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t
> gfp,
> 
> 
>  static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
> -			 gfp_t gfp, pgprot_t prot, const void *caller)
> +			 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
>  {
>  	u64 mask = get_coherent_dma_mask(dev);
>  	struct page *page;
> @@ -571,7 +610,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t
> *handle,
>  	*handle = DMA_ERROR_CODE;
>  	size = PAGE_ALIGN(size);
> 
> -	if (arch_is_coherent() || nommu())
> +	if (is_coherent || nommu())
>  		addr = __alloc_simple_buffer(dev, size, gfp, &page);
>  	else if (gfp & GFP_ATOMIC)
>  		addr = __alloc_from_pool(size, &page);
> @@ -599,7 +638,20 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
>  	if (dma_alloc_from_coherent(dev, size, handle, &memory))
>  		return memory;
> 
> -	return __dma_alloc(dev, size, handle, gfp, prot,
> +	return __dma_alloc(dev, size, handle, gfp, prot, false,
> +			   __builtin_return_address(0));
> +}
> +
> +static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
> +	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
> +{
> +	pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
> +	void *memory;
> +
> +	if (dma_alloc_from_coherent(dev, size, handle, &memory))
> +		return memory;
> +
> +	return __dma_alloc(dev, size, handle, gfp, prot, true,
>  			   __builtin_return_address(0));
>  }
> 
> @@ -636,8 +688,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
>  /*
>   * Free a buffer as defined by the above mapping.
>   */
> -void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> -		  dma_addr_t handle, struct dma_attrs *attrs)
> +static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +			   dma_addr_t handle, struct dma_attrs *attrs,
> +			   bool is_coherent)
>  {
>  	struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
> 
> @@ -646,7 +699,7 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> 
>  	size = PAGE_ALIGN(size);
> 
> -	if (arch_is_coherent() || nommu()) {
> +	if (is_coherent || nommu()) {
>  		__dma_free_buffer(page, size);
>  	} else if (!IS_ENABLED(CONFIG_CMA)) {
>  		__dma_free_remap(cpu_addr, size);
> @@ -662,6 +715,18 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
>  	}
>  }
> 
> +void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +		  dma_addr_t handle, struct dma_attrs *attrs)
> +{
> +	__arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
> +}
> +
> +static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +				  dma_addr_t handle, struct dma_attrs *attrs)
> +{
> +	__arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
> +}
> +
>  int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
>  		 void *cpu_addr, dma_addr_t handle, size_t size,
>  		 struct dma_attrs *attrs)
> --
> 1.7.9.5


Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From shiraz.linux.kernel at gmail.com  Mon Aug 13 03:21:14 2012
From: shiraz.linux.kernel at gmail.com (shiraz hashim)
Date: Mon, 13 Aug 2012 12:51:14 +0530
Subject: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller)
 AuxCtlr register
In-Reply-To: <1289984848.2351.2.camel@e102109-lin.cambridge.arm.com>
References: <1289976931-9759-1-git-send-email-kgene.kim@samsung.com>
 <1289984848.2351.2.camel@e102109-lin.cambridge.arm.com>
Message-ID: <CAPub14_9vNoiOMEeBDSkJo6NQaazcNvAYu8oD_E2ReEYLfrX+A@mail.gmail.com>

Hi Catalin,

On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
>
> On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > --- a/arch/arm/mach-s5pv310/cpu.c
> > +++ b/arch/arm/mach-s5pv310/cpu.c
> > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> >         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> >                      S5P_VA_L2CC + L2X0_POWER_CTRL);
> >
> > -       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > +       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
>
> The patch is fine.
>
> But I think we should also set this bit in the cache-l2x0.c file if
> PL310. That's such a fundamental issue and it's easy to miss in the
> platform code.

Sorry for reviving this old patch but any reasons why it didn't
go to the cache-l2x0.c directly (for PL310).

--
regards
Shiraz Hashim


From catalin.marinas at arm.com  Mon Aug 13 03:39:44 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 13 Aug 2012 08:39:44 +0100
Subject: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache
 controller) AuxCtlr register
In-Reply-To: <CAPub14_9vNoiOMEeBDSkJo6NQaazcNvAYu8oD_E2ReEYLfrX+A@mail.gmail.com>
References: <1289976931-9759-1-git-send-email-kgene.kim@samsung.com>
 <1289984848.2351.2.camel@e102109-lin.cambridge.arm.com>
 <CAPub14_9vNoiOMEeBDSkJo6NQaazcNvAYu8oD_E2ReEYLfrX+A@mail.gmail.com>
Message-ID: <20120813073944.GA13508@arm.com>

On Mon, Aug 13, 2012 at 08:21:14AM +0100, shiraz hashim wrote:
> On Wed, Nov 17, 2010 at 2:37 PM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> >
> > On Wed, 2010-11-17 at 06:55 +0000, Kukjin Kim wrote:
> > > --- a/arch/arm/mach-s5pv310/cpu.c
> > > +++ b/arch/arm/mach-s5pv310/cpu.c
> > > @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
> > >         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
> > >                      S5P_VA_L2CC + L2X0_POWER_CTRL);
> > >
> > > -       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
> > > +       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
> >
> > The patch is fine.
> >
> > But I think we should also set this bit in the cache-l2x0.c file if
> > PL310. That's such a fundamental issue and it's easy to miss in the
> > platform code.
> 
> Sorry for reviving this old patch but any reasons why it didn't
> go to the cache-l2x0.c directly (for PL310).

The cache-l2x0.c patch has been around for a while:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1

It may no longer apply cleanly but I haven't revived it since it wasn't
accepted at the time.

-- 
Catalin


From shawn.guo at linaro.org  Mon Aug 13 04:15:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 16:15:21 +0800
Subject: [PATCH v2 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120813081518.GA27480@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 11:32:49AM +0200, Uwe Kleine-K?nig wrote:
> From: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> 
> This patch adds basic support for imx35-based devices to the kernel.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> --
> Changes since implict v1
> (id:1343922986-32469-1-git-send-email-u.kleine-koenig at pengutronix.de)
> 
>  - add aliases for gpio devices
>  - drop calling irq_domain_add_legacy
>  - drop soc/cpus from device tree
>  - rename uart entries to serial
>  - drop "status = "disabled"" from watchdog node
>  - drop fallback compatibility entries for fsl,mx35-sdhc
>  - put nand below a new emi node
>  - fix register range for aips1
>  - add ssi1
>  - gpio controllers have two interrupt cells
>  - register additional clklookups instead of using auxdata lookup
> 
>  arch/arm/boot/dts/imx35.dtsi            |  253 +++++++++++++++++++++++++++++++
>  arch/arm/configs/imx_v6_v7_defconfig    |    1 +
>  arch/arm/mach-imx/Kconfig               |   12 ++
>  arch/arm/mach-imx/Makefile              |    1 +
>  arch/arm/mach-imx/clk-imx35.c           |   14 ++
>  arch/arm/mach-imx/imx35-dt.c            |   56 +++++++
>  arch/arm/plat-mxc/include/mach/common.h |    1 +
>  7 files changed, 338 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx35.dtsi
>  create mode 100644 arch/arm/mach-imx/imx35-dt.c
> 
> diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
> new file mode 100644
> index 0000000..05f906f
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx35.dtsi
> @@ -0,0 +1,253 @@
> +/*
> + * Copyright 2012 Steffen Trumtrar, Pengutronix
> + *
> + * based on imx27.dtsi
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	aliases {
> +		serial0 = &uart1;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +	};
> +
> +	avic: avic-interrupt-controller at 68000000 {
> +		compatible = "fsl,imx35-avic", "fsl,avic";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		reg = <0x68000000 0x10000000>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ckil {
> +			compatible = "fsl,imx-ckil", "fixed-clock";
> +			clock-frequency = <32768>;
> +		};
> +
> +		osc {
> +			compatible = "fsl,imx-osc", "fixed-clock";
> +			clock-frequency = <24000000>;
> +		};
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&avic>;
> +		ranges;
> +
> +		aips at 40000000 { /* AIPS1 */
> +			compatible = "fsl,aips", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x43f00000 0x100000>;

The address in "reg" property should match the one in node name.

> +			ranges;
> +
> +			i2c1: i2c at 43f80000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f80000 0x4000>;
> +				interrupts = <10>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c at 43f84000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f84000 0x4000>;
> +				interrupts = <3>;
> +				status = "disabled";
> +			};
> +
> +			uart1: serial at 43f90000 {
> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x43f90000 0x4000>;
> +				interrupts = <45>;
> +				status = "disabled";
> +			};
> +
> +			uart2: serial at 43f94000 {
> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x43f94000 0x4000>;
> +				interrupts = <32>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c at 43f98000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
> +				reg = <0x43f98000 0x4000>;
> +				interrupts = <4>;
> +				status = "disabled";
> +			};
> +
> +			ssi1: ssi at 43fa0000 {
> +				compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
> +				reg = <0x43fa0000 0x4000>;
> +				interrupts = <11>;
> +				fsl,ssi-dma-events = <29 28 27 26>;
> +				status = "disabled";
> +			};

New line.

> +			iomuxc at 43fac000 {
> +				compatible = "fsl,imx35-iomuxc";
> +				reg = <0x43fac000 0x4000>;
> +
> +				i2c3 {
> +					pinctrl_i2c3_1: i2c3grp-1 {
> +						fsl,pins = <773 0x1c0 /* MX35_PAD_ATA_DATA12__I2C3_SCL */
> +							777 0x1c0>; /* MX35_PAD_ATA_DATA13__I2C3_SDA */
> +					};
> +				};
> +
> +				can1 {
> +					pinctrl_can1_1: can1grp-1 {
> +						fsl,pins = <223 0x1c0 /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
> +							228 0x1c0>; /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
> +					};
> +				};
> +
> +				can2 {
> +					pinctrl_can2_1: can2grp-1 {
> +						fsl,pins = <291 0x1c0 /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
> +							298 0x1c0>; /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
> +					};
> +				};
> +
> +			};
> +		};
> +
> +		spba at 50000000 {

SPBA bus should not be at the same level as AIPS bus.  Instead, it's
under AIPS, as core accesses SPBA blocks through AIPS too.

> +			compatible = "fsl,spba-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x50000000 0x100000>;
> +			ranges;
> +
> +			uart3: serial at 5000c000 {
> +				compatible = "fsl,imx35-uart", "fsl,imx21-uart";
> +				reg = <0x5000c000 0x4000>;
> +				interrupts = <18>;
> +				status = "disabled";
> +			};
> +
> +			fec: fec at 50038000 {

Nit: The label is quite pointless here.  No one refers to this node,
and it does not document the block instance like some other labels do.

> +				compatible = "fsl,imx35-fec", "fsl,imx27-fec";
> +				reg = <0x50038000 0x4000>;
> +				interrupts = <57>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		aips at 53f00000 { /* AIPS2 */
> +			compatible = "fsl,aips", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x53f00000 0xffc0000>;
> +			ranges;
> +
> +			gpio3: gpio at 0x53fa4000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";

Again, this should just be "fsl,imx35-gpio"

> +				reg = <0x53fa4000 0x4000>;
> +				interrupts = <56>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			esdhc1: esdhc at 53fb4000 {
> +				compatible = "fsl,mx35-sdhc";

Again, this should be compatible = "fsl,imx35-esdhc"

I'm wondering if I'm actually looking at the v2 :)

> +				reg = <0x53fb4000 0x4000>;
> +				interrupts = <7>;
> +				status = "disabled";
> +			};
> +
> +			esdhc2: esdhc at 53fb8000 {
> +				compatible = "fsl,mx35-sdhc";
> +				reg = <0x53fb8000 0x4000>;
> +				interrupts = <8>;
> +				status = "disabled";
> +			};
> +
> +			esdhc3: esdhc at 53fbc000 {
> +				compatible = "fsl,mx35-sdhc";
> +				reg = <0x53fbc000 0x4000>;
> +				interrupts = <9>;
> +				status = "disabled";
> +			};
> +
> +			gpio1: gpio at 0x53fcc000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> +				reg = <0x53fcc000 0x4000>;
> +				interrupts = <52>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio2: gpio at 0x53fd0000 {
> +				compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
> +				reg = <0x53fd0000 0x4000>;
> +				interrupts = <51>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			wdog at 53fdc000 {
> +				compatible = "fsl,imx35-wdt", "fsl,imx2-wdt";
> +				reg = <0x53fdc000 0x4000>;
> +				interrupts = <55>;
> +			};
> +
> +			can at 53fe4000 {
> +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> +				reg = <0x53fe4000 0x1000>;
> +				interrupts = <43>;
> +				status = "disabled";
> +			};

New line.

> +			can at 53fe8000 {
> +				compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
> +				reg = <0x53fe8000 0x1000>;
> +				interrupts = <44>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		emi at 80000000 { /* External Memory Interface */
> +			compatible = "fsl,emi", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80000000 0x40000000>;
> +			ranges;
> +
> +			nand at bb000000 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
These should not be needed, until you will have sub-nodes with "reg"
property.

> +				compatible = "fsl,imx35-nand", "fsl,imx25-nand";
> +				reg = <0xbb000000 0x2000>;
> +				interrupts = <33>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
> index f725b96..d27a3e2 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -28,6 +28,7 @@ CONFIG_MACH_ARMADILLO5X0=y
>  CONFIG_MACH_KZM_ARM11_01=y
>  CONFIG_MACH_PCM043=y
>  CONFIG_MACH_MX35_3DS=y
> +CONFIG_MACH_IMX35_DT=y
>  CONFIG_MACH_VPR200=y
>  CONFIG_MACH_IMX51_DT=y
>  CONFIG_MACH_MX51_3DS=y
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 156c986..0d9bf22 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -653,6 +653,18 @@ config MACH_VPR200
>  	  Include support for VPR200 platform. This includes specific
>  	  configurations for the board and its peripherals.
>  
> +config MACH_IMX35_DT
> +	bool "Support i.MX35 platforms from device tree"
> +	select SOC_IMX35
> +	select IMX_HAVE_PLATFORM_MXC_NAND
> +	select IMX_HAVE_PLATFORM_SPI_IMX
> +	select IMX_HAVE_PLATFORM_IMX2_WDT

At least put a comment saying why these are needed for DT?

> +	select PINCTRL
> +	select PINCTRL_IMX35
> +	help
> +	  Include support for Freescale i.MX35 based platforms
> +	  using the device tree for discovery
> +
>  comment "i.MX5 platforms:"
>  
>  config MACH_MX50_RDP
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 07f7c22..c68a925 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
>  obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
>  obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
>  obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
> +obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
>  
>  obj-$(CONFIG_DEBUG_LL) += lluart.o
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index 83d614c..323907e 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -202,7 +202,9 @@ int __init mx35_clocks_init()
>  				i, PTR_ERR(clk[i]));
>  
>  	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
> +	clk_register_clkdev(clk[can1_gate], NULL, "53fe4000.can");
>  	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
> +	clk_register_clkdev(clk[can2_gate], NULL, "53fe8000.can");
>  	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
>  	clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
>  	clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
> @@ -219,12 +221,16 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
>  	clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
>  	clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
> +	clk_register_clkdev(clk[fec_gate], NULL, "50038000.fec");
>  	/* i.mx35 has the i.mx27 type fec */
>  	clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
>  	clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
> +	clk_register_clkdev(clk[i2c1_gate], NULL, "43f80000.i2c");
>  	clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
> +	clk_register_clkdev(clk[i2c2_gate], NULL, "43f98000.i2c");
>  	clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
> +	clk_register_clkdev(clk[i2c3_gate], NULL, "43f84000.i2c");
>  	clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
>  	clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
>  	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
> @@ -234,6 +240,12 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
>  	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[uart1_gate], "per", "43f90000.serial");
> +	clk_register_clkdev(clk[ipg], "ipg", "43f90000.serial");
> +	clk_register_clkdev(clk[uart2_gate], "per", "43f94000.serial");
> +	clk_register_clkdev(clk[ipg], "ipg", "43f94000.serial");
> +	clk_register_clkdev(clk[uart3_gate], "per", "5000c000.serial");
> +	clk_register_clkdev(clk[ipg], "ipg", "5000c000.serial");
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> @@ -253,7 +265,9 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
>  	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
>  	clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
> +	clk_register_clkdev(clk[wdog_gate], NULL, "53fdc000.wdog");
>  	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
> +	clk_register_clkdev(clk[nfc_div], NULL, "bb000000.nand");
>  	clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
>  
>  	clk_prepare_enable(clk[spba_gate]);
> diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
> new file mode 100644
> index 0000000..52b619a
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx35-dt.c
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright 2012 Steffen Trumtrar, Pengutronix
> + *
> + * based on imx27-dt.c
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/pinctrl/machine.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +#include <mach/mx35.h>
> +#include <mach/hardware.h>
> +#include <linux/gpio.h>

This one is not well sorted.  Actually, I have seen some of the headers
are not needed now.

> +
> +static void __init imx35_dt_init(void)
> +{
> +	/* Some mx35 have problems when the cache is not initialized
> +	 * FIXME: ultimatly this belongs in the oftree definition
> +	 */

/*
 * Multiple line comments
 */

> +	imx3_init_l2x0();

Any problem with using l2x0_of_init instead here?

> +	pinctrl_provide_dummies();

Ideally, we should not have this.  But at least have a comment saying
this is a stop-gap solution before pinctrl is ready, and should be
removed once pinctrl is in place.

Regards,
Shawn

> +
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}
> +
> +static void __init imx35_timer_init(void)
> +{
> +	mx35_clocks_init();
> +}
> +
> +static struct sys_timer imx35_timer = {
> +	.init = imx35_timer_init,
> +};
> +
> +static const char *imx35_dt_board_compat[] __initdata = {
> +	"fsl,imx35",
> +	NULL
> +};
> +
> +DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
> +	.map_io		= mx35_map_io,
> +	.init_early	= imx35_init_early,
> +	.init_irq	= mx35_init_irq,
> +	.handle_irq	= imx35_handle_irq,
> +	.timer		= &imx35_timer,
> +	.init_machine	= imx35_dt_init,
> +	.dt_compat	= imx35_dt_board_compat,
> +	.restart	= mxc_restart,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> index 7128e97..82b0a57 100644
> --- a/arch/arm/plat-mxc/include/mach/common.h
> +++ b/arch/arm/plat-mxc/include/mach/common.h
> @@ -50,6 +50,7 @@ extern void imx25_soc_init(void);
>  extern void imx27_soc_init(void);
>  extern void imx31_soc_init(void);
>  extern void imx35_soc_init(void);
> +extern void imx3_init_l2x0(void);
>  extern void imx50_soc_init(void);
>  extern void imx51_soc_init(void);
>  extern void imx53_soc_init(void);
> -- 
> 1.7.10.4
> 



From a.p.zijlstra at chello.nl  Mon Aug 13 04:15:04 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Mon, 13 Aug 2012 10:15:04 +0200
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
Message-ID: <1344845704.31459.11.camel@twins>

On Thu, 2012-08-09 at 12:57 -0400, Nicolas Pitre wrote:
> 
> In other words, I think this should look like this:
> 
> diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> index 580a6d35c7..44a66c99c8 100644
> --- a/include/asm-generic/mutex-xchg.h
> +++ b/include/asm-generic/mutex-xchg.h
> @@ -25,8 +25,11 @@
>  static inline void
>  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
>  {
> -       if (unlikely(atomic_xchg(count, 0) != 1))
> -               fail_fn(count);
> +       if (unlikely(atomic_xchg(count, 0) != 1)) {
> +               /* Mark lock contention explicitly */
> +               if (likely(atomic_xchg(count, -1) != 1))
> +                       fail_fn(count);
> +       }
>  } 

OK, I like this.. Thanks guys! Will will you send a final and complete
patch?


From jason77.wang at gmail.com  Mon Aug 13 05:11:37 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Mon, 13 Aug 2012 17:11:37 +0800
Subject: [PATCH 0/9] ARM perf updates for 3.7
In-Reply-To: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
Message-ID: <5028C4C9.6020002@gmail.com>

Hi Will Deacon,

For SMP platforms, each CPU core has an independent PMU, and each PMU 
has a dedicated irq (SPI or PPI). Current perf subsystem framework only 
supports each PMU to have a dedicated SPI irq, and it will support each 
PMU to have a PPI irq (i have seen someone has sent out the patches), 
but there is a situation the subsystem doesn't support yet, the 
situation is multi PMUs share one same SPI irq, e.g. the i.MX6Quad CPU 
has 4 cortex-a9 cores, each core has a PMU, all PMU irqs are routed 
(ORed) to one SPI irq, do you know how to support this situation?

Regards,
Hui.




Will Deacon wrote:
> Hello,
>
> This patch series contains the ARM perf updates I'd like to push for 3.7
> Most of the code is cleanup in preparation for big.LITTLE PMU support,
> where we will need to support different types of CPU PMU on the same SoC.
>
> The PMU probing has changed so that we try to identify the PMU using its
> DT binding before falling back to probing the current core. The unused
> PMU registration mechanism is also removed and platforms registering
> the device have been updated accordingly.
>
> Given that this touches a few platforms, I anticipate sending it via
> arm-soc.
>
> All feedback welcome,
>
> Will
>
>
> Jon Hunter (1):
>   ARM: PMU: Add runtime PM Support
>
> Sudeep KarkadaNagesha (2):
>   ARM: pmu: remove arm_pmu_type enumeration
>   ARM: perf: move irq registration into pmu implementation
>
> Will Deacon (6):
>   ARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs
>   ARM: pmu: remove unused reservation mechanism
>   ARM: perf: remove mysterious compiler barrier
>   ARM: perf: probe devicetree in preference to current CPU
>   ARM: perf: prepare for moving CPU PMU code into separate file
>   ARM: perf: move CPU-specific PMU handling code into separate file
>
>  Documentation/devicetree/bindings/arm/pmu.txt |    4 +
>  MAINTAINERS                                   |    1 -
>  arch/arm/Kconfig                              |    8 +-
>  arch/arm/include/asm/perf_event.h             |    9 +-
>  arch/arm/include/asm/pmu.h                    |   77 ++----
>  arch/arm/kernel/Makefile                      |    3 +-
>  arch/arm/kernel/perf_event.c                  |  347 ++++---------------------
>  arch/arm/kernel/perf_event_cpu.c              |  295 +++++++++++++++++++++
>  arch/arm/kernel/perf_event_v6.c               |   12 +-
>  arch/arm/kernel/perf_event_v7.c               |   32 ++--
>  arch/arm/kernel/perf_event_xscale.c           |   10 +-
>  arch/arm/kernel/pmu.c                         |   36 ---
>  arch/arm/mach-bcmring/arch.c                  |    3 +-
>  arch/arm/mach-omap2/devices.c                 |    3 +-
>  arch/arm/mach-pxa/devices.c                   |    3 +-
>  arch/arm/mach-realview/realview_eb.c          |    3 +-
>  arch/arm/mach-realview/realview_pb1176.c      |    3 +-
>  arch/arm/mach-realview/realview_pb11mp.c      |    3 +-
>  arch/arm/mach-realview/realview_pba8.c        |    3 +-
>  arch/arm/mach-realview/realview_pbx.c         |    3 +-
>  arch/arm/mach-tegra/devices.c                 |    3 +-
>  arch/arm/mach-ux500/cpu-db8500.c              |    3 +-
>  arch/arm/mach-vexpress/ct-ca9x4.c             |    3 +-
>  arch/arm/plat-iop/pmu.c                       |    3 +-
>  arch/arm/plat-samsung/devs.c                  |    3 +-
>  25 files changed, 424 insertions(+), 449 deletions(-)
>  create mode 100644 arch/arm/kernel/perf_event_cpu.c
>  delete mode 100644 arch/arm/kernel/pmu.c
>
>   



From will.deacon at arm.com  Mon Aug 13 05:13:49 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 10:13:49 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <1344845704.31459.11.camel@twins>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <1344845704.31459.11.camel@twins>
Message-ID: <20120813091349.GA19113@mudshark.cambridge.arm.com>

Hi Peter,

On Mon, Aug 13, 2012 at 09:15:04AM +0100, Peter Zijlstra wrote:
> On Thu, 2012-08-09 at 12:57 -0400, Nicolas Pitre wrote:
> > 
> > In other words, I think this should look like this:
> > 
> > diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
> > index 580a6d35c7..44a66c99c8 100644
> > --- a/include/asm-generic/mutex-xchg.h
> > +++ b/include/asm-generic/mutex-xchg.h
> > @@ -25,8 +25,11 @@
> >  static inline void
> >  __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
> >  {
> > -       if (unlikely(atomic_xchg(count, 0) != 1))
> > -               fail_fn(count);
> > +       if (unlikely(atomic_xchg(count, 0) != 1)) {
> > +               /* Mark lock contention explicitly */
> > +               if (likely(atomic_xchg(count, -1) != 1))
> > +                       fail_fn(count);
> > +       }
> >  } 
> 
> OK, I like this.. Thanks guys! Will will you send a final and complete
> patch?

I sent one out on Friday but somehow managed to drop you from CC -- sorry
about that:

  http://thread.gmane.org/gmane.linux.kernel/1341305

Cheers,

Will


From will.deacon at arm.com  Mon Aug 13 05:32:01 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 10:32:01 +0100
Subject: [PATCH 0/9] ARM perf updates for 3.7
In-Reply-To: <5028C4C9.6020002@gmail.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <5028C4C9.6020002@gmail.com>
Message-ID: <20120813093201.GB19113@mudshark.cambridge.arm.com>

On Mon, Aug 13, 2012 at 10:11:37AM +0100, Hui Wang wrote:
> Hi Will Deacon,

Hello,

> For SMP platforms, each CPU core has an independent PMU, and each PMU 
> has a dedicated irq (SPI or PPI). Current perf subsystem framework only 
> supports each PMU to have a dedicated SPI irq, and it will support each 
> PMU to have a PPI irq (i have seen someone has sent out the patches), 
> but there is a situation the subsystem doesn't support yet, the 
> situation is multi PMUs share one same SPI irq, e.g. the i.MX6Quad CPU 
> has 4 cortex-a9 cores, each core has a PMU, all PMU irqs are routed 
> (ORed) to one SPI irq, do you know how to support this situation?

That's what I like to call a braindead, broken system. Seriously, CPU PMU
interrupts *can only* be handled on the CPU which raised them -- ORing these
things together means ping-ponging the interrupt affinity around until we
find the right guy. There's also the fun case where multiple PMUs assert
simultaneously and I've even heard about platforms where they OR in the
bloody L2 PMU interrupt as well for good measure!

If you have to support such a device, take a look at the ux500 code
(db8500_pmu_handler), but please take all of your profiling numbers with a
pinch of salt. For a quad-core processor, the numbers will probably be even
less accurate.

Also, please go ahead and inflict sufficient injuries to your hardware guys
that they stop this madness!

Will


From zonque at gmail.com  Mon Aug 13 05:43:01 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 13 Aug 2012 11:43:01 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <CACRpkda0443PF-SwNaiJCO9RmdCFqw1+OtLgTBoTfZzwnFjJ4w@mail.gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
 <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>
 <5023C923.3080808@gmail.com>
 <CACRpkda0443PF-SwNaiJCO9RmdCFqw1+OtLgTBoTfZzwnFjJ4w@mail.gmail.com>
Message-ID: <5028CC25.5040707@gmail.com>

On 10.08.2012 12:56, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 4:28 PM, Daniel Mack <zonque at gmail.com> wrote:
> 
>> I am looking at the generic pinctrl code right now
> 
> Sweet!
> 
>> and I wonder if the following approach would be ok:
>>
>> - each driver that calls pinctrl_register() has its own dt_match_table
>> entry, so the 'compatible' part of the bindings is specific to a pin
>> controller chip.
> 
> Yep.
> 
>> - introduce a pinctrl_parse_of(struct of_node *) and call that after the
>> driver has added all its pins. That function walks all the children of
>> the given node and uses the callbacks provided by the driver to do the
>> actual work.
> 
> Isn't that already how it works? Maybe I misunderstand, do you mean
> that you want to pass the DT node to pinctrl_register()?

To parse the generic bits, yes. But I realized only now that we already
have dt_to_map_one_config()

> Are you talking about using pinctrl hogs to set up the default
> configuration and muxing? That can already be done today,
> and has nothing to do with whether you use generic pin config
> or not.
> 
> This uses the .dt_node_to_map() and .dt_free_map() callbacks
> in the pinctrl_ops vtable to generate a map from the device tree,
> in any way you want.

Yes, I see. And this is where duplication emerges, or, where
consolidation would need to be done. If we want to standardize the way
pins are set up in terms of bias, pullup/pulldown and all that, we would
just need to map generic DT entries to PIN_CONFIG_* and call the pin
controllers specific functions.

> So the infrastructure I think already exists, but whereas all
> current driver have their own config and mux (etc) parsing
> code, pinconf-generic could provide something that would
> be common for all driver using generic pin config.

Exactly. And then the question is whether we want implicit behaviour.
IOW - let dt_to_map_one_config() parse the generic bits and then call
the driver specific augmentation code, if any.


Daniel



From ian.molton at codethink.co.uk  Mon Aug 13 06:00:32 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Mon, 13 Aug 2012 11:00:32 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <201208101049.57586.arnd@arndb.de>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <201208091143.32972.arnd@arndb.de> <5023D577.8090001@codethink.co.uk>
 <201208101049.57586.arnd@arndb.de>
Message-ID: <5028D040.60604@codethink.co.uk>

On 10/08/12 11:49, Arnd Bergmann wrote:
> On Thursday 09 August 2012, Ian Molton wrote:
>>>  The driver
>>> already knows all those offsets and they are always the same
>>> for all variants of mv643xx, right?
>> Yes, but its not clean. And no amount of refactoring is
>> really going to make a nice driver that also fits the ancient
>> (and badly thought out) OF bindings.
> In what way is it badly though out, or not clean? The use of
> underscores in the properties, and the way that the sram
> is configured is problematic, I agree. But The way that
> the three ports are addressed and how the PHY is found
> seems quite clever.

It forces one to load the MDIO driver first, because it maps ALL the
registers for both itself and all the ports, and the MDIO driver has no
way of knowing how many ethernet blocks are present (I have a device
here with two, and another with four). Thats anywhere from 1 to 12
ports, split across 1 to 4 address ranges, and theres a big gap in the
address range between controllers 0,1 and 2,3. *ALL* the devices on the
board are sharing ethernet block 0's MDIO bus. By pure luck it happens
to work, because the blocks 2,3 have an alias of the MDIO registers from
blocks 0,1.

Having the MDIO driver map the ethernet drivers memory is a terrible
solution, IMO. Ethernet drivers should map their own memory, and that
introduces the n-ports-per-block problem, because their address ranges
overlap.

I think the best solution is to make each ethernet block register 3 ports.

the PPC code can simply generate different fixups so that instead of
creating 3 devices, it creates one, with three ports.

>> If we have to break things, we can at least go for a nice
>> clean design, surely?
>>
>> The ports arent really child devices of the MAC. The MAC
>> just has 3 ports.
> I don't see the difference between those two things.

The ports are at best 'pseudodevices'. Real devices have registers of
their own.

>> We're going to have to maintain a legacy
>> platform_device -> DT bindings hack somewhere anyway,
>> at least until the remaining other users of the driver
>> convert to D-T.
> I don't understand why you describe the method used in
> powerpc as a hack. It was the normal way to introduce
> DT support for platform devices back when it was implemented.

Just because its normal doesn't mean its not a hack :)

> It also had the advantage of not requiring any modifications
> to the generic driver, because it was shared between one
> architecture using DT (powerpc) and one that didn't (ARM).

It /did/ spawn a pretty hideous driver, though...

-Ian


From sourav.poddar at ti.com  Mon Aug 13 06:05:11 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:35:11 +0530
Subject: [PATCHv2 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>

Add tmp102 temperature sensor data in omap5 evm dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39a..45a8aeb 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -18,3 +18,12 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 };
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	tmp102 at 48{
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Mon Aug 13 06:05:09 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:35:09 +0530
Subject: [PATCHv2 0/4] Add device tree data for omap5
Message-ID: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>

The following patch series add i2c support for omap5.
As well as enable I2C based devices like pressure and temperature
through device tree. Also add onchip keypad dts data.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>

Sourav Poddar (4):
  arm/dts: omap5-evm: Add I2C support
  arm/dts: omap5-evm: Add tmp102 sensor support
  arm/dts: omap5-evm: Add keypad data
  arm/dts: omap5-evm: Add bmp085 sensor support

 arch/arm/boot/dts/omap5-evm.dts |   30 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 0 deletions(-)



From sourav.poddar at ti.com  Mon Aug 13 06:05:10 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:35:10 +0530
Subject: [PATCHv2 1/4] arm/dts: omap5-evm: Add I2C support
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344852313-30484-2-git-send-email-sourav.poddar@ti.com>

Add I2C data node in omap5 device tree file.

Tested on omap5430 evm.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..6b68dfe 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -145,6 +145,41 @@
 			#interrupt-cells = <1>;
 		};
 
+		i2c1: i2c at 48070000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c1";
+		};
+
+		i2c2: i2c at 48072000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c2";
+		};
+
+		i2c3: i2c at 48060000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c3";
+		};
+
+		i2c4: i2c at 4807A000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c4";
+		};
+
+		i2c5: i2c at 4807C000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c5";
+		};
+
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			ti,hwmods = "uart1";
-- 
1.7.1



From sourav.poddar at ti.com  Mon Aug 13 06:05:13 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:35:13 +0530
Subject: [PATCH 4/4] arm/dts: omap5-evm: Add bmp085 sensor support
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344852313-30484-5-git-send-email-sourav.poddar@ti.com>

Add bmp085 pressure sensor data in omap5 evm dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index c2ea189..18e499c 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -39,3 +39,12 @@
 		reg = <0x48>;
 	};
 };
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	bmp085 at 77 {
+		compatible = "bosch,bmp085";
+		reg = <0x77>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Mon Aug 13 06:05:12 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:35:12 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344852313-30484-4-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap5 device tree file.
Also fill the device tree binding parameters
with the required value in "omap5-evm" dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
v1->v2
Add key names as comments
 arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |    5 +++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 45a8aeb..c2ea189 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,6 +17,18 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	keypad {
+		keypad,num-rows = <8>;
+		keypad,num-columns = <8>;
+		linux,keymap = < 0x02020073  /* VOLUP */
+			0x02030072  /* VOLDOWM */
+			0x020400e7  /* SEND */
+			0x02050066  /* HOME */
+			0x0206006b  /* END */
+			0x020700d9 >; /* SEARCH */
+		linux,input-no-autorepeat;
+	};
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6b68dfe..c38b823 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -216,4 +216,9 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	keypad {
+		compatible = "ti,omap4-keypad";
+		ti,hwmods = "kbd";
+	};
 };
-- 
1.7.1



From dedekind1 at gmail.com  Mon Aug 13 06:20:27 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 13 Aug 2012 13:20:27 +0300
Subject: [PATCH v2] mtd: gpmi: add NAND write verify support
In-Reply-To: <50288C0E.5060400@freescale.com>
References: <1344698728-8709-1-git-send-email-shijie8@gmail.com>
 <CAF4G-tKN683_EQCGcG4G8jMU5K6TamaHUv__3ugGUoEg_LPrcQ@mail.gmail.com>
 <50288C0E.5060400@freescale.com>
Message-ID: <1344853227.3393.7.camel@sauron.fi.intel.com>

On Mon, 2012-08-13 at 13:09 +0800, Huang Shijie wrote:
> ? 2012?08?13? 12:44, Artem Bityutskiy ??:
> > On Sat, Aug 11, 2012 at 6:25 PM, Huang Shijie<shijie8 at gmail.com>  wrote:
> >> Add NAND write verify support in gpmi-nand driver.
> >>
> >> This patch fixes a kernel crash when we select
> >> CONFIG_MTD_NAND_VERIFY_WRITE=y, and do some write tests:
> > I would just kill ONFIG_MTD_NAND_VERIFY_WRITE entirely. Some drivers
> > do not support it and it does not work for sub-pages for long time.
> > Both UBI and JFFS2 are able to read verify what they wrote already.
> > There are also MTD tests which do this verification. So I think there
> > is no reason to keep this in the NAND layer, let alone wasting RAM in
> > the driver to support this feature.
> >
> > I am also removing the -stable mailing list - ne need to spam it.
> >
> thanks a lot. Maybe we should send a patch to remove the 
> CONFIG_MTD_NAND_VERIFY_WRITE feature entirely.

I'd suggest that instead. I have huge back-log, so wouldn't be able to
process it quickly, but at some point I would take it to the l2 tree.

-- 
Best Regards,
Artem Bityutskiy
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From artem.bityutskiy at linux.intel.com  Mon Aug 13 06:22:56 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Mon, 13 Aug 2012 13:22:56 +0300
Subject: [PATCH 6/6] ARM: imx: gpmi-nand depends on mxs-dma
In-Reply-To: <CAOMZO5BtStkEWGRWi7LcVT_DK0C2WnjPiCOh2ZriVzrP+1NW3g@mail.gmail.com>
References: <1344430493-5304-1-git-send-email-arnd@arndb.de>
 <1344430493-5304-7-git-send-email-arnd@arndb.de>
 <CAOMZO5CZ7mJd89cN_S0KBS74mc5qTzvrfRbmHVX3nmEakx19ow@mail.gmail.com>
 <50226409.1060800@de.bosch.com>
 <CAOMZO5BtStkEWGRWi7LcVT_DK0C2WnjPiCOh2ZriVzrP+1NW3g@mail.gmail.com>
Message-ID: <1344853376.3393.8.camel@sauron.fi.intel.com>

On Wed, 2012-08-08 at 10:18 -0300, Fabio Estevam wrote:
> On Wed, Aug 8, 2012 at 10:05 AM, Dirk Behme <dirk.behme at de.bosch.com> wrote:
> 
> > Yes. But it seems it's not handled there? I'm trying since ~2 weeks to get
> > something like your patch applied to get the broken mainline fixed, but
> > unfortunately without success so far.
> 
> Let's try once again.
> 
> Artem,
> 
> Could https://patchwork.kernel.org/patch/1236551/ be applied?

I will get to that. I was busy and also having vacation, so I have a
huge back-log, sorry.

-- 
Best Regards,
Artem Bityutskiy
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From sourav.poddar at ti.com  Mon Aug 13 06:28:55 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:58:55 +0530
Subject: [PATCHv2 4/4] arm/dts: omap5-evm: Add bmp085 sensor support
In-Reply-To: <1344853735-16313-1-git-send-email-sourav.poddar@ti.com>
References: <1344853735-16313-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344853735-16313-2-git-send-email-sourav.poddar@ti.com>

Add bmp085 pressure sensor data in omap5 evm dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index c2ea189..18e499c 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -39,3 +39,12 @@
 		reg = <0x48>;
 	};
 };
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	bmp085 at 77 {
+		compatible = "bosch,bmp085";
+		reg = <0x77>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Mon Aug 13 06:28:54 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 13 Aug 2012 15:58:54 +0530
Subject: [PATCHv2 3/4] arm/dts: omap5-evm: Add keypad data
Message-ID: <1344853735-16313-1-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap5 device tree file.
Also fill the device tree binding parameters
with the required value in "omap5-evm" dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
v1->v2
Add key names as comments
 arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |    5 +++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 45a8aeb..c2ea189 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,6 +17,18 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	keypad {
+		keypad,num-rows = <8>;
+		keypad,num-columns = <8>;
+		linux,keymap = < 0x02020073  /* VOLUP */
+			0x02030072  /* VOLDOWM */
+			0x020400e7  /* SEND */
+			0x02050066  /* HOME */
+			0x0206006b  /* END */
+			0x020700d9 >; /* SEARCH */
+		linux,input-no-autorepeat;
+	};
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6b68dfe..c38b823 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -216,4 +216,9 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	keypad {
+		compatible = "ti,omap4-keypad";
+		ti,hwmods = "kbd";
+	};
 };
-- 
1.7.1



From will.deacon at arm.com  Mon Aug 13 06:40:06 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 11:40:06 +0100
Subject: [PATCH 1/9] ARM: PMU: Add runtime PM Support
In-Reply-To: <CACVXFVMg5Acx4_KGT5jn1JgO3JsXAjZzU8virR=B3+pBrT4o_A@mail.gmail.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-2-git-send-email-will.deacon@arm.com>
 <CACVXFVMg5Acx4_KGT5jn1JgO3JsXAjZzU8virR=B3+pBrT4o_A@mail.gmail.com>
Message-ID: <20120813104006.GA20537@mudshark.cambridge.arm.com>

On Sat, Aug 11, 2012 at 04:09:51PM +0100, Ming Lei wrote:
> On Sat, Aug 11, 2012 at 1:36 AM, Will Deacon <will.deacon at arm.com> wrote:
> > +       pm_runtime_put_sync(&pmu_device->dev);
> 
> One question, each pmu is just inside one cpu core and should be
> suspended individually, but looks the above don't support it, do it?

I'll let Jon elaborate, but I'm not sure that suspending the individual PMUs
makes much sense if one of them is being used (other than taking the whole
CPU offline). Given that tasks can migrate and perf-events can be across
multiple CPUs, it makes it a lot easier to treat them as a single entity. It
also allows us to implement mutual exclusion using the same hooks and to
manage any common IP (e.g. CTI) at the same time, without having to keep
track of things like the last man standing.

So, unless Jon has some ideas here, it's not something that I consider to be
a real problem.

Will


From veli-pekka.peltola at bluegiga.com  Mon Aug 13 06:44:11 2012
From: veli-pekka.peltola at bluegiga.com (Veli-Pekka Peltola)
Date: Mon, 13 Aug 2012 13:44:11 +0300
Subject: Problem: CONFIG_KALLSYMS is not set + kernel/module.c
In-Reply-To: <50155655.9070002@gmail.com>
References: <50155655.9070002@gmail.com>
Message-ID: <5028DA7B.4010901@bluegiga.com>

Hi Mark,

On 07/29/2012 06:27 PM, Mark Hinds wrote:
>
> In linux-3.2.xx I've been getting kernel dumps when I modprobe some
> modules with CONFIG_KALLSYMS diabled - nls_base.ko for example.
> I traced the problem to kernel/module.c, line 2607 or there about.
>
> Starting with:
> ptr = module_alloc_update_bounds(mod->init_size);
>
> If mod->init_size == 0 then foobar happens. I assume that there is
> no init section in some modules when CONFIG_KALLSYMS is disabled.

A while ago I hit the same problem I guess. Could you check out if my 
fix[1] does the job for you?

--
Veli-Pekka Peltola

[1] https://lkml.org/lkml/2012/3/7/193

> Here is my fix:
>
> Index: kernel/module.c
> ===================================================================
> --- kernel/module.c    (.../linux-3.2.24/kernel/module.c)    (revision
> 9084)
> +++ kernel/module.c    (.../linux-3.2.24-ces/kernel/module.c)
> (working copy)
> @@ -2604,20 +2604,24 @@
>       memset(ptr, 0, mod->core_size);
>       mod->module_core = ptr;
>
> -    ptr = module_alloc_update_bounds(mod->init_size);
> -    /*
> -     * The pointer to this block is stored in the module structure
> -     * which is inside the block. This block doesn't need to be
> -     * scanned as it contains data and code that will be freed
> -     * after the module is initialized.
> -     */
> -    kmemleak_ignore(ptr);
> -    if (!ptr && mod->init_size) {
> -        module_free(mod, mod->module_core);
> -        return -ENOMEM;
> +#warning ### CES/zoro fix problem with mod->init_size == 0
> +    if (mod->init_size) {
> +        ptr = module_alloc_update_bounds(mod->init_size);
> +        /*
> +         * The pointer to this block is stored in the module structure
> +         * which is inside the block. This block doesn't need to be
> +         * scanned as it contains data and code that will be freed
> +         * after the module is initialized.
> +         */
> +        kmemleak_ignore(ptr);
> +        if (!ptr) {
> +            module_free(mod, mod->module_core);
> +            return -ENOMEM;
> +        }
> +        memset(ptr, 0, mod->init_size);
> +        mod->module_init = ptr;
>       }
> -    memset(ptr, 0, mod->init_size);
> -    mod->module_init = ptr;
> +    else mod->module_init = NULL;
>
>       /* Transfer each section which specifies SHF_ALLOC */
>       DEBUGP("final section addresses:\n");
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From will.deacon at arm.com  Mon Aug 13 06:44:23 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 11:44:23 +0100
Subject: LPAE for outer caches functiopns (was Re: [RFC 3/6] arm:
 cache-l2x0: add support for Aurora L2 cache ctrl)
In-Reply-To: <5025229A.2090007@free-electrons.com>
References: <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
 <20120810144730.GG2066@mudshark.cambridge.arm.com>
 <5025229A.2090007@free-electrons.com>
Message-ID: <20120813104422.GB20537@mudshark.cambridge.arm.com>

On Fri, Aug 10, 2012 at 04:02:50PM +0100, Gregory CLEMENT wrote:
> On 08/10/2012 04:47 PM, Will Deacon wrote:
> > On Thu, Aug 09, 2012 at 05:48:44PM +0100, Gregory CLEMENT wrote:
> >> You will find an updated version of this patch with LPAE support. I've
> >> tested with and without LPAE selected.
> 
> Just a rectification, in fact I managed to build in both case, and to run
> only without LPAE support. I didn't have the support for LPAE yet. I was
> surprised that it worked out of the box, but in fact I tested the wrong
> kernel! I realized this this morning.

Ok, please keep me updated with how you get on. I can't shake this nagging
feeling that the memory-mapped interface is restricted to 32-bit addresses,
which is why the XP has the option to treat the L2 as an inner-cache...

</speculation>

Will


From linux at arm.linux.org.uk  Mon Aug 13 06:52:45 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 13 Aug 2012 11:52:45 +0100
Subject: [PATCH 09/10] ARM: rpc: Fix building RiscPC
In-Reply-To: <201208101103.58808.arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-10-git-send-email-arnd@arndb.de>
 <20120809074754.GP18957@n2100.arm.linux.org.uk>
 <201208101103.58808.arnd@arndb.de>
Message-ID: <20120813105245.GE18957@n2100.arm.linux.org.uk>

On Fri, Aug 10, 2012 at 11:03:58AM +0000, Arnd Bergmann wrote:
> On Thursday 09 August 2012, Russell King - ARM Linux wrote:
> > On Wed, Aug 08, 2012 at 11:27:57PM +0200, Arnd Bergmann wrote:
> > > ARMv3 support was removed in 357c9c1f07 "ARM: Remove support for ARMv3
> > > ARM610 and ARM710 CPUs", which explicitly left parts of the CPU32v3
> > > support in place for building RiscPC. However, this does not actually
> > > build in my test setup.
> > > 
> > > This is probably not the right solution, but maybe someone has a better
> > > idea for how to deal with this.
> > 
> > This isn't the right solution.  The RiscPC bus does not support half-word
> > load/stores, so we must continue to build that target for the 32v3
> > architecture (which is why I carefully left that stuff behind.)
> > 
> > The mistake is in what I did with arch/arm/lib - the armv3 code in there
> > needs to be resurected instead.
> 
> Ok, I'll drop my patch from the series then and wait for you to
> fix this properly.

I've just reverted the arch/arm/lib part of
357c9c1f07d4546bc3fbc0fd1044d96b114d14ed (ARM: Remove support for ARMv3
ARM610 and ARM710 CPUs) so when I push my fixes branch this should resolve
your build error.


From gcembed at gmail.com  Mon Aug 13 07:19:59 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Mon, 13 Aug 2012 13:19:59 +0200
Subject: [PATCH 1/2] ARM: mx27pdk: Add audio support
In-Reply-To: <20120803135956.GT1451@pengutronix.de>
References: <1341341098-9510-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5BXQ2OQVC6nXeo_yJB=SBC=sv=ez9k6uo3gLNkWnC0Gyg@mail.gmail.com>
 <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
 <20120803135956.GT1451@pengutronix.de>
Message-ID: <5028E2DF.6060409@gmail.com>

Hi,
On 08/03/2012 03:59 PM, Sascha Hauer wrote:
> On Tue, Jul 31, 2012 at 09:49:13AM -0300, Fabio Estevam wrote:
>> Sascha,
>>
>> On 7/25/12, Fabio Estevam <festevam at gmail.com> wrote:
>>> Hi Sascha,
>>>
>>> On Tue, Jul 3, 2012 at 3:44 PM, Fabio Estevam
>>> <fabio.estevam at freescale.com> wrote:
>>>> mx27pdk has a mc13783 audio codec.
>>>>
>>>> Add support for it.
>>>>
>>>> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>>>
>>> Is this patch OK? Can it be applied?
>>
>> Could this get into 3.6?
>
> Applied now. Sorry, missed this one.
>
> Sascha
>
Is this patch will be applied on linux-next tree ?
Newer patch "[PATCH v2] ASoC: imx-ssi: Remove mono support" is already 
applied (I know that is not for the same branch) but not this one. Is 
there a problem with this patch ?
Best regards,
Ga?tan Carlier


From tobetter at gmail.com  Mon Aug 13 07:24:04 2012
From: tobetter at gmail.com (tobetter at gmail.com)
Date: Mon, 13 Aug 2012 20:24:04 +0900
Subject: [PATCH] ARM: EXYNOS: Add audio I2S clock control
Message-ID: <1344857054-6688-1-git-send-email-dongjin.kim@agreeyamobility.net>

From: Dongjin Kim <dongjin.kim at agreeyamobility.net>

This patch adds the clock controls for the audio subsystem channel 0,
and fixes invalid clock gating for i2s.0.

Signed-off-by: Dongjin Kim <dongjin.kim at agreeyamobility.net>
---
 arch/arm/mach-exynos/clock-exynos4.c           |  254 +++++++++++++++++++++++-
 arch/arm/mach-exynos/common.c                  |    5 +
 arch/arm/mach-exynos/include/mach/map.h        |    2 +
 arch/arm/mach-exynos/include/mach/regs-audss.h |    6 +
 arch/arm/plat-samsung/include/plat/map-s5p.h   |    2 +
 5 files changed, 263 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 2dc96f4..a3478db 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -24,6 +24,7 @@
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-audss.h>
 #include <mach/sysmmu.h>
 
 #include "common.h"
@@ -198,6 +199,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
+static int exynos4_clk_vpll_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_VPLL_CON0, clk, enable);
+}
+
 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
@@ -213,6 +219,16 @@ static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 }
 
+static int exynos4_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+int exynos4_clk_audss_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos4_clk_mout_apll = {
@@ -451,6 +467,25 @@ static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 };
 
+static struct clk *exynos4_clkset_mout_audss_list[] = {
+	&clk_ext_xtal_mux,
+	&clk_fout_epll,
+};
+
+static struct clksrc_sources clkset_mout_audss = {
+	.sources	= exynos4_clkset_mout_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_audss_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_audss = {
+	.clk	= {
+		.name		= "mout_audss",
+	},
+	.sources = &clkset_mout_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 },
+};
+
+
 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 	.clk	= {
 		.name		= "sclk_vpll",
@@ -459,6 +494,43 @@ static struct clksrc_clk exynos4_clk_sclk_vpll = {
 	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
+static struct clksrc_clk exynos4_clk_dout_audss_srp = {
+	.clk	= {
+		.name		= "dout_srp",
+		.parent		= &exynos4_clk_mout_audss.clk,
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audss_bus = {
+	.clk	= {
+		.name		= "busclk",
+		.parent		= &exynos4_clk_dout_audss_srp.clk,
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= (1 << 2),
+	},
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 },
+};
+
+static struct clk exynos4_init_audss_clocks[] = {
+	{
+		.name		= "srpclk",
+		.enable		= exynos4_clk_audss_ctrl,
+		.parent		= &exynos4_clk_dout_audss_srp.clk,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.0",
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= (1 << 3) | (1 << 2),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.0",
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= (1 << 5),
+	},
+};
+
 static struct clk exynos4_init_clocks_off[] = {
 	{
 		.name		= "timers",
@@ -601,11 +673,6 @@ static struct clk exynos4_init_clocks_off[] = {
 		.ctrlbit	= (1 << 18),
 	}, {
 		.name		= "iis",
-		.devname	= "samsung-i2s.0",
-		.enable		= exynos4_clk_ip_peril_ctrl,
-		.ctrlbit	= (1 << 19),
-	}, {
-		.name		= "iis",
 		.devname	= "samsung-i2s.1",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 20),
@@ -728,7 +795,65 @@ static struct clk exynos4_init_clocks_off[] = {
 		.devname	= SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 		.enable		= exynos4_clk_ip_lcd0_ctrl,
 		.ctrlbit	= (1 << 4),
-	}
+	},
+};
+
+struct clksrc_clk exynos4_clk_audiocdclk0 = {
+	.clk	= {
+		.name		= "audiocdclk",
+		.rate		= 16934400,
+	},
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+	[0] = &exynos4_clk_audiocdclk0.clk,
+	[1] = NULL,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &clk_ext_xtal_mux,
+	[5] = &clk_xusbxti,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audio0 = {
+	.sources	= clkset_sclk_audio0_list,
+	.nr_sources	= ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audio0 = {
+	.clk	= {
+		.name		= "audio-bus",
+		.enable		= exynos4_clksrc_mask_maudio_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos4_clkset_sclk_audio0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_audss_list[] = {
+	&exynos4_clk_mout_audss.clk,
+	&exynos4_clk_audiocdclk0.clk,
+	&exynos4_clk_sclk_audio0.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_audss = {
+	.sources	= exynos4_clkset_sclk_audss_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_audss_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_audss_i2s = {
+	.clk		= {
+		.name		= "i2sclk",
+		.parent		= &exynos4_clk_mout_audss.clk,
+		.enable		= exynos4_clk_audss_ctrl,
+		.ctrlbit	= (1 << 3),
+	},
+	.sources = &exynos4_clkset_sclk_audss,
+	.reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 },
+	.reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 8, .size = 4 },
 };
 
 static struct clk exynos4_init_clocks_on[] = {
@@ -1271,6 +1396,14 @@ static struct clksrc_clk exynos4_clk_sclk_spi2 = {
 	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
 };
 
+static struct clksrc_clk exynos4_clk_sclk_pcm0 = {
+	.clk	= {
+		.name		= "sclk_pcm",
+		.parent		= &exynos4_clk_sclk_audio0.clk,
+	},
+	.reg_div = { .reg = EXYNOS4_CLKDIV_MAUDIO, .shift = 4, .size = 8 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *exynos4_sysclks[] = {
 	&exynos4_clk_mout_apll,
@@ -1303,6 +1436,13 @@ static struct clksrc_clk *exynos4_sysclks[] = {
 	&exynos4_clk_dout_mmc4,
 	&exynos4_clk_mout_mfc0,
 	&exynos4_clk_mout_mfc1,
+	&exynos4_clk_audiocdclk0,
+	&exynos4_clk_mout_audss,
+	&exynos4_clk_sclk_audss_bus,
+	&exynos4_clk_sclk_audss_i2s,
+	&exynos4_clk_dout_audss_srp,
+	&exynos4_clk_sclk_audio0,
+	&exynos4_clk_sclk_pcm0,
 };
 
 static struct clk *exynos4_clk_cdev[] = {
@@ -1430,6 +1570,92 @@ static struct clk_ops exynos4_vpll_ops = {
 	.set_rate = exynos4_vpll_set_rate,
 };
 
+static unsigned long exynos4_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static u32 epll_div[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos4_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+
+	epll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k = epll_div[i][5] << 0;
+			epll_con |= epll_div[i][1] << 27;
+			epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		pr_err("%s: Invalid Clock EPLL Frequency\n", __func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS4_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS4_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS4_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos4_epll_ops = {
+	.get_rate = exynos4_epll_get_rate,
+	.set_rate = exynos4_epll_set_rate,
+};
+
 void __init_or_cpufreq exynos4_setup_clocks(void)
 {
 	struct clk *xtal_clk;
@@ -1486,6 +1712,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 
 	clk_fout_apll.ops = &exynos4_fout_apll_ops;
 	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.ops = &exynos4_epll_ops;
 	clk_fout_epll.rate = epll;
 	clk_fout_vpll.ops = &exynos4_vpll_ops;
 	clk_fout_vpll.rate = vpll;
@@ -1510,6 +1737,16 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	clk_h.rate = sclk_dmc;
 	clk_p.rate = aclk_100;
 
+	clk_set_parent(&exynos4_clk_mout_audss.clk, &clk_fout_epll);
+	clk_set_parent(&exynos4_clk_sclk_audio0.clk,
+			&exynos4_clk_mout_epll.clk);
+	clk_set_parent(&exynos4_clk_mout_epll.clk, &clk_fout_epll);
+
+	clk_fout_vpll.enable = exynos4_clk_vpll_ctrl;
+	clk_fout_vpll.ops = &exynos4_vpll_ops;
+
+	clk_set_rate(&exynos4_clk_sclk_apll.clk, 100000000);
+
 	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
 		s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
 }
@@ -1569,6 +1806,11 @@ void __init exynos4_register_clocks(void)
 	s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
 	clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
 
+	s3c_register_clocks(exynos4_init_audss_clocks,
+				ARRAY_SIZE(exynos4_init_audss_clocks));
+	s3c_disable_clocks(exynos4_init_audss_clocks,
+				ARRAY_SIZE(exynos4_init_audss_clocks));
+
 	register_syscore_ops(&exynos4_clock_syscore_ops);
 	s3c24xx_register_clock(&dummy_apb_pclk);
 
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 94d58af..9450651 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -198,6 +198,11 @@ static struct map_desc exynos4_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual        = (unsigned long)S5P_VA_AUDSS,
+		.pfn            = __phys_to_pfn(EXYNOS4_PA_AUDSS),
+		.length         = SZ_4K,
+		.type           = MT_DEVICE,
 	},
 };
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..2f8a16f 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,8 @@
 
 #define EXYNOS4_PA_JPEG			0x11840000
 
+#define EXYNOS4_PA_AUDSS		0x03810000
+
 /* x = 0...1 */
 #define EXYNOS4_PA_FIMC_LITE(x)		(0x12390000 + ((x) * 0x10000))
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h
index ca5a8b6..e75b959 100644
--- a/arch/arm/mach-exynos/include/mach/regs-audss.h
+++ b/arch/arm/mach-exynos/include/mach/regs-audss.h
@@ -15,4 +15,10 @@
 
 #define EXYNOS4_AUDSS_INT_MEM	(0x03000000)
 
+#define EXYNOS4_AUDSSREG(x)	(S5P_VA_AUDSS + (x))
+
+#define S5P_CLKSRC_AUDSS	EXYNOS4_AUDSSREG(0x0)
+#define S5P_CLKDIV_AUDSS	EXYNOS4_AUDSSREG(0x4)
+#define S5P_CLKGATE_AUDSS	EXYNOS4_AUDSSREG(0x8)
+
 #endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bda..3558277 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -40,6 +40,8 @@
 #define S5P_VA_GIC_CPU		S3C_ADDR(0x02810000)
 #define S5P_VA_GIC_DIST		S3C_ADDR(0x02820000)
 
+#define S5P_VA_AUDSS		S3C_ADDR(0x02910000)
+
 #define VA_VIC(x)		(S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0			VA_VIC(0)
 #define VA_VIC1			VA_VIC(1)
-- 
1.7.9.5



From linus.walleij at linaro.org  Mon Aug 13 07:38:10 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 Aug 2012 13:38:10 +0200
Subject: [GIT PULL] Ux500 ASIC ID patches
Message-ID: <CACRpkdZ1+vjrTQC9-M9icO7p9POg-zcR_gUpkyemF4da3jny2w@mail.gmail.com>

Hi ARM SoC maintainers,

could you please pull the following patch set into ARM SoC as a first
step for the
next merge window. This cleans up, updates and structure the use of some ASIC ID
detection macros so they are understandable and consistent.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
ux500-core

for you to fetch changes up to 1d3266ecca67066e537fe0e0669bed77d355f886:

  ARM: ux500: add detection for DB8500 ASIC v2.2 (2012-08-09 17:48:45 +0200)

----------------------------------------------------------------
Linus Walleij (4):
      ARM: ux500: delete remnant U5500 macros
      ARM: ux500: add a U8520 detection macro
      ARM: ux500: reform Ux500 family names
      ARM: ux500: add detection for DB8500 ASIC v2.2

 arch/arm/mach-ux500/cache-l2x0.c      |  2 +-
 arch/arm/mach-ux500/cpu-db8500.c      |  2 +-
 arch/arm/mach-ux500/cpu.c             |  2 +-
 arch/arm/mach-ux500/include/mach/id.h | 44
+++++++++++++++-----------------------------
 arch/arm/mach-ux500/platsmp.c         |  2 +-
 5 files changed, 19 insertions(+), 33 deletions(-)

Yours,
Linus Walleij


From santosh.shilimkar at ti.com  Mon Aug 13 07:39:54 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 13 Aug 2012 17:09:54 +0530
Subject: [PATCHv2 0/4] Add device tree data for omap5
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <CAMQu2gwbG4XSBQvvbMJ8aKRy=LRG44dKv+feSo-mso_jju71oQ@mail.gmail.com>

Sourav,

On Mon, Aug 13, 2012 at 3:35 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>
> The following patch series add i2c support for omap5.
> As well as enable I2C based devices like pressure and temperature
> through device tree. Also add onchip keypad dts data.
>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> Sourav Poddar (4):
>   arm/dts: omap5-evm: Add I2C support
>   arm/dts: omap5-evm: Add tmp102 sensor support
>   arm/dts: omap5-evm: Add keypad data
>   arm/dts: omap5-evm: Add bmp085 sensor support
>
>  arch/arm/boot/dts/omap5-evm.dts |   30 +++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap5.dtsi    |   40
> +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 70 insertions(+), 0 deletions(-)
>
The entire series looks fine to me.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From linus.walleij at stericsson.com  Mon Aug 13 07:57:40 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:57:40 +0200
Subject: [PATCH 1/7] ARM: u300: retire ancient platforms
Message-ID: <1344859061-29296-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This retires the B26/S26, B330/S330 and B365/S365 boards from
the U300 platform. The only board really used anywhere today
is the S335 so let's concentrate any efforts on that one board.
Also the board variants are selected at compile-time, which is
strictly a no-no these days, if multi-board support is to be
brought back it need to happen using run-time and device tree.

My work on ARM Linux started on the B26/S26 so it's a bit sad
to see it go, but there is a time to move on with all things
in life.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/Kconfig                     | 43 +---------------
 arch/arm/mach-u300/core.c                      | 70 +-------------------------
 arch/arm/mach-u300/i2c.c                       |  6 +--
 arch/arm/mach-u300/include/mach/dma_channels.h | 11 +---
 arch/arm/mach-u300/include/mach/irqs.h         | 34 +------------
 arch/arm/mach-u300/include/mach/syscon.h       | 32 ++----------
 arch/arm/mach-u300/include/mach/u300-regs.h    | 19 +------
 arch/arm/mach-u300/u300-gpio.h                 | 46 +----------------
 arch/arm/mach-u300/u300.c                      | 18 +------
 9 files changed, 14 insertions(+), 265 deletions(-)

diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34..f7e12ed 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_U300
 
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
@@ -10,46 +10,7 @@ config MACH_U300
 	select PINCTRL_U300
 	select PINCTRL_COH901
 
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
-
-choice
-	prompt "U300/U330/U335/U365 system type"
-	default MACH_U300_BS2X
-	---help---
-	You need to select the target system, i.e. the
-	U300/U330/U335/U365 board that you want to compile your kernel
-	for.
-
-config MACH_U300_BS2X
-	bool "S26/S26/B25/B26 Test Products"
-	depends on MACH_U300
-	help
-		Select this if you're developing on the
-		S26/S25 test products. (Also works on
-		B26/B25 big boards.)
-
-config MACH_U300_BS330
-	bool "S330/B330 Test Products"
-	depends on MACH_U300
-	help
-		Select this if you're developing on the
-		S330/B330 test products.
-
-config MACH_U300_BS335
-	bool "S335/B335 Test Products"
-	depends on MACH_U300
-	help
-		Select this if you're developing on the
-		S335/B335 test products.
-
-config MACH_U300_BS365
-	bool "S365/B365 Test Products"
-	depends on MACH_U300
-	help
-		Select this if you're developing on the
-		S365/B365 test products.
-
-endchoice
+comment "ST-Ericsson U300/U335 Feature Selections"
 
 config U300_DEBUG
 	bool "Debug support for U300"
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf18..1794075 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij at stericsson.com>
@@ -101,7 +101,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 	{ IRQ_U300_UART0 }, &uart0_plat_data);
 
 /* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
 	.dma_filter = coh901318_filter_id,
@@ -113,7 +112,6 @@ static struct amba_pl011_data uart1_plat_data = {
 /* Fast device at 0x7000 offset */
 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 	{ IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
 
 /* AHB device at 0x4000 offset */
 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +150,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
  */
 static struct amba_device *amba_devs[] __initdata = {
 	&uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
 	&uart1_device,
-#endif
 	&pl022_device,
 	&pl172_device,
 	&mmcsd_device,
@@ -188,7 +184,6 @@ static struct resource gpio_resources[] = {
 		.end   = IRQ_U300_GPIO_PORT2,
 		.flags = IORESOURCE_IRQ,
 	},
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 	{
 		.name  = "gpio3",
 		.start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +196,6 @@ static struct resource gpio_resources[] = {
 		.end   = IRQ_U300_GPIO_PORT4,
 		.flags = IORESOURCE_IRQ,
 	},
-#endif
-#ifdef CONFIG_MACH_U300_BS335
 	{
 		.name  = "gpio5",
 		.start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +208,6 @@ static struct resource gpio_resources[] = {
 		.end   = IRQ_U300_GPIO_PORT6,
 		.flags = IORESOURCE_IRQ,
 	},
-#endif /* CONFIG_MACH_U300_BS335 */
 };
 
 static struct resource keypad_resources[] = {
@@ -323,7 +315,6 @@ static struct resource dma_resource[] = {
 	}
 };
 
-#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
  * Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +327,6 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
 	U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 
-#else /* CONFIG_MACH_U300_BS335 */
-
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
-	U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-
-#endif
-
 /** register dma for memory access
  *
  * active  1 means dma intends to access memory
@@ -1395,7 +1378,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 		.param.ctrl_lli = flags_memcpy_lli,
 		.param.ctrl_lli_last = flags_memcpy_lli_last,
 	},
-#ifdef CONFIG_MACH_U300_BS335
 	{
 		.number = U300_DMA_UART1_TX,
 		.name = "UART1 TX",
@@ -1406,28 +1388,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 		.name = "UART1 RX",
 		.priority_high = 0,
 	}
-#else
-	{
-		.number = U300_DMA_GENERAL_PURPOSE_9,
-		.name = "GENERAL 09",
-		.priority_high = 0,
-
-		.param.config = flags_memcpy_config,
-		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
-		.param.ctrl_lli = flags_memcpy_lli,
-		.param.ctrl_lli_last = flags_memcpy_lli_last,
-	},
-	{
-		.number = U300_DMA_GENERAL_PURPOSE_10,
-		.name = "GENERAL 10",
-		.priority_high = 0,
-
-		.param.config = flags_memcpy_config,
-		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
-		.param.ctrl_lli = flags_memcpy_lli,
-		.param.ctrl_lli_last = flags_memcpy_lli_last,
-	}
-#endif
 };
 
 
@@ -1480,18 +1440,8 @@ static struct platform_device pinctrl_device = {
  * GPIO block, with different number of ports.
  */
 static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-	.variant = U300_GPIO_COH901335,
-	.ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
 	.variant = U300_GPIO_COH901571_3_BS335,
 	.ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-	.variant = U300_GPIO_COH901571_3_BS365,
-	.ports = 5,
-#endif
 	.gpio_base = 0,
 	.gpio_irq_base = IRQ_U300_GPIO_BASE,
 	.pinctrl_device = &pinctrl_device,
@@ -1756,29 +1706,11 @@ static void __init u300_init_check_chip(void)
 	printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
 	       "(chip ID 0x%04x)\n", chipname, val);
 
-#ifdef CONFIG_MACH_U300_BS330
-	if ((val & 0xFF00U) != 0xd800) {
-		printk(KERN_ERR "Platform configured for BS330 " \
-		       "with DB3200 but %s detected, expect problems!",
-		       chipname);
-	}
-#endif
-#ifdef CONFIG_MACH_U300_BS335
 	if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
 		printk(KERN_ERR "Platform configured for BS335 " \
 		       " with DB3350 but %s detected, expect problems!",
 		       chipname);
 	}
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-	if ((val & 0xFF00U) != 0xe800) {
-		printk(KERN_ERR "Platform configured for BS365 " \
-		       "with DB3210 but %s detected, expect problems!",
-		       chipname);
-	}
-#endif
-
-
 }
 
 /*
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index cb04bd6..0d4620e 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-u300/i2c.c
  *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  *
  * Register board i2c devices
@@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
 	{
 		.type = "fwcam",
 		.addr = 0x10,
@@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
 		.type = "fwcam",
 		.addr = 0x5d,
 	},
-#else
-	{ },
-#endif
 };
 
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
index b239149..4e8a88f 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/dma_channels.h
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
  * Map file for the U300 dma driver.
  * Author: Per Friden <per.friden at stericsson.com>
@@ -50,19 +50,10 @@
 #define U300_DMA_GENERAL_PURPOSE_6    35
 #define U300_DMA_GENERAL_PURPOSE_7    36
 #define U300_DMA_GENERAL_PURPOSE_8    37
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_UART1_TX             38
 #define U300_DMA_UART1_RX             39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9    38
-#define U300_DMA_GENERAL_PURPOSE_10   39
-#endif
 
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_DEVICE_CHANNELS      32
-#else
-#define U300_DMA_DEVICE_CHANNELS      30
-#endif
 #define U300_DMA_CHANNELS             40
 
 
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e..c09386b 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/irqs.h
  *
  *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * IRQ channel definitions for the U300 platforms.
  * Author: Linus Walleij <linus.walleij at stericsson.com>
@@ -31,10 +31,6 @@
 #define IRQ_U300_XGAM_GAMCON		14
 #define IRQ_U300_XGAM_CDI		15
 #define IRQ_U300_XGAM_CDICON		16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC		17
-#endif
 #define IRQ_U300_XGAM_PDI		18
 #define IRQ_U300_XGAM_PDICON		19
 #define IRQ_U300_XGAM_GAMEACC		20
@@ -55,8 +51,6 @@
 #define IRQ_U300_GPIO_PORT1		34
 #define IRQ_U300_GPIO_PORT2		35
 
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
-    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
 #define IRQ_U300_WDOG			36
 #define IRQ_U300_EVHIST			37
@@ -68,15 +62,8 @@
 #define IRQ_U300_RTC			43
 #define IRQ_U300_NFIF			44
 #define IRQ_U300_NFIF2			45
-#endif
-
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END		46
-#endif
 
 /* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
 #define IRQ_U300_ISP_F0			46
 #define IRQ_U300_ISP_F1			47
 #define IRQ_U300_ISP_F2			48
@@ -89,25 +76,6 @@
 #define IRQ_U300_GPIO_PORT5		55
 #define IRQ_U300_GPIO_PORT6		56
 #define U300_VIC_IRQS_END		57
-#endif
-
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3		36
-#define IRQ_U300_GPIO_PORT4		37
-#define IRQ_U300_WDOG			38
-#define IRQ_U300_EVHIST			39
-#define IRQ_U300_MSPRO			40
-#define IRQ_U300_MMCSD_MCIINTR0		41
-#define IRQ_U300_MMCSD_MCIINTR1		42
-#define IRQ_U300_I2C0			43
-#define IRQ_U300_I2C1			44
-#define IRQ_U300_RTC			45
-#define IRQ_U300_NFIF			46
-#define IRQ_U300_NFIF2			47
-#define IRQ_U300_SYSCON_PLL_LOCK	48
-#define U300_VIC_IRQS_END		49
-#endif
 
 /* Maximum 8*7 GPIO lines */
 #ifdef CONFIG_PINCTRL_COH901
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07..10bdd0b 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/syscon.h
  *
  *
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
  *
  * Author: Rickard Andersson <rickard.andersson at stericsson.com>
  */
@@ -36,9 +36,7 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND				(0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR						(0x0014)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN				(0x0200)
-#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN			(0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN			(0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN				(0x0040)
@@ -50,9 +48,7 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN			(0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR						(0x0018)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE			(0x0080)
-#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE			(0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE			(0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE			(0x0010)
@@ -62,10 +58,8 @@
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE		(0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR						(0x001c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN				(0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN				(0x2000)
-#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN				(0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN				(0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN				(0x0100)
@@ -79,9 +73,7 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN				(0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR					(0x0020)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN				(0x0200)
-#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN				(0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN				(0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN				(0x0040)
@@ -92,24 +84,20 @@
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN			(0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR					(0x0024)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN				(0x0200)
-#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN			(0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN			(0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN				(0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN				(0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN    			(0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN     			(0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN     			(0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN     			(0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN				(0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN				(0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN				(0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN				(0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN			(0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR					(0x0028)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN				(0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN				(0x1000)
-#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN				(0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN		(0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN				(0x0200)
@@ -124,9 +112,7 @@
 #define U300_SYSCON_CERR_AAIF_CLK_EN				(0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER					(0x002c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN				(0x0009)
-#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN			(0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN			(0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN				(0x0006)
@@ -135,9 +121,7 @@
 #define U300_SYSCON_SBCER_BTR_CLK_EN				(0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN				(0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN			(0x0000)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN				(0x0019)
-#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN			(0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN			(0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN				(0x0016)
@@ -147,10 +131,8 @@
 #define U300_SYSCON_SBCER_I2C1_CLK_EN				(0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN				(0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN			(0x0010)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN				(0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN				(0x002C)
-#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN				(0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN		(0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN				(0x0029)
@@ -168,9 +150,7 @@
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR					(0x003c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN			(0x0200)
-#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN			(0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN			(0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN			(0x0020)
@@ -184,10 +164,8 @@
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR					(0x44)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN			(0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN			(0x1000)
-#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN			(0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN		(0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN			(0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c5..1e49d90 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
 #define PLAT_NAND_CLE			(1 << 16)
 #define PLAT_NAND_ALE			(1 << 17)
 
-
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE		0xa0000000
 #define U300_AHB_PER_VIRT_BASE		0xff010000
@@ -46,11 +45,7 @@
 #define U300_BOOTROM_VIRT_BASE		0xffff0000
 
 /* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE		0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE		0x30000000
-#endif
 
 /*
  * AHB peripherals
@@ -99,10 +94,8 @@
 /* SPI controller */
 #define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)
 
-#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
 
 /*
  * SLOW peripherals
@@ -151,10 +144,8 @@
  * REST peripherals
  */
 
-/* ISP (image signal processor) is only available in U335 */
-#ifdef CONFIG_MACH_U300_BS335
+/* ISP (image signal processor) */
 #define U300_ISP_BASE			(0xA0008000)
-#endif
 
 /* DMA Controller base */
 #define U300_DMAC_BASE			(0xC0020000)
@@ -166,17 +157,9 @@
 #define U300_APEX_BASE			(0xc0030000)
 
 /* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE		(0xc0080000)
-#else
-#define U300_VIDEOENC_BASE		(0xc0040000)
-#endif
 
 /* XGAM Base */
 #define U300_XGAM_BASE			(0xd0000000)
 
-/*
- * Virtual accessor macros for static devices
- */
-
 #endif
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
index 847dc25..83f5077 100644
--- a/arch/arm/mach-u300/u300-gpio.h
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -1,50 +1,11 @@
 /*
- * Individual pin assignments for the B26/S26. Notice that the
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX		0
-#define U300_GPIO_PIN_UART_TX		1
-#define U300_GPIO_PIN_GPIO02		2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03		3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP		4
-#define U300_GPIO_PIN_CAM_REG_EN	5
-#define U300_GPIO_PIN_GPIO06		6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07		7  /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO08		8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09		9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE		10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET	11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD		12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE		13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14		14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15		15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16		16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17		17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18		18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19		19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20		20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21		21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22		22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23		23 /* Unrouted */
-#endif
-
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
+ * Individual pin assignments for the B335/S335.
  * Notice that the actual usage of these pins depends on the
  * PAD MUX settings, that is why the same number can potentially
  * appear several times. In the reference design each pin is only
  * used for one purpose. These were determined by inspecting the
  * S365 schematic.
  */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
 #define U300_GPIO_PIN_UART_RX		0
 #define U300_GPIO_PIN_UART_TX		1
 #define U300_GPIO_PIN_UART_CTS		2
@@ -90,8 +51,6 @@
 #define U300_GPIO_PIN_GPIO38		38 /* Unrouted */
 #define U300_GPIO_PIN_GPIO39		39 /* Unrouted */
 
-#ifdef CONFIG_MACH_U300_BS335
-
 #define U300_GPIO_PIN_GPIO40		40 /* Unrouted */
 #define U300_GPIO_PIN_GPIO41		41 /* Unrouted */
 #define U300_GPIO_PIN_GPIO42		42 /* Unrouted */
@@ -109,6 +68,3 @@
 #define U300_GPIO_PIN_GPIO53		53 /* Unrouted */
 #define U300_GPIO_PIN_GPIO54		54 /* Unrouted */
 #define U300_GPIO_PIN_GPIO55		55 /* Unrouted */
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index f30c69d..4e56e8c 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -29,23 +29,7 @@ static void __init u300_init_machine(void)
 	u300_init_devices();
 }
 
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-
-MACHINE_START(U300, MACH_U300_STRING)
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
 	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
 	.atag_offset	= 0x100,
 	.map_io		= u300_map_io,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:57:31 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:57:31 +0200
Subject: [PATCH 0/7] U300 cleanup patch series
Message-ID: <1344859051-29259-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This patch series clean up the U300 platform by:
- Deleting ancient platforms, including portions of
  the pinctrl driver
- Consolidating the platform and get rid of excess
  headers in <mach/*>
- Convert to sparse IRQs like everyone else (so we can
  do stuff like Device Tree and single zImage, if we want).

Linus Walleij (7):
  ARM: u300: retire ancient platforms
  pinctrl/coh901: retire ancient GPIO block versions
  pinctrl/coh901: move header to platform data dir
  ARM: u300: merge u300.c into core.c and rid headers
  ARM: u300: delete remnant clkdev.h file
  ARM: u300: move DMA channel header into mach-u300
  ARM: u300: convert to sparse IRQs

 arch/arm/Kconfig                               |   1 +
 arch/arm/mach-u300/Kconfig                     |  43 +----
 arch/arm/mach-u300/Makefile                    |   1 -
 arch/arm/mach-u300/core.c                      | 100 +++--------
 arch/arm/mach-u300/dma_channels.h              |  60 +++++++
 arch/arm/mach-u300/i2c.c                       |   6 +-
 arch/arm/mach-u300/include/mach/clkdev.h       |   7 -
 arch/arm/mach-u300/include/mach/dma_channels.h |  69 --------
 arch/arm/mach-u300/include/mach/gpio-u300.h    |  37 -----
 arch/arm/mach-u300/include/mach/irqs.h         |  36 +---
 arch/arm/mach-u300/include/mach/platform.h     |  20 ---
 arch/arm/mach-u300/include/mach/syscon.h       |  32 +---
 arch/arm/mach-u300/include/mach/u300-regs.h    |  19 +--
 arch/arm/mach-u300/spi.c                       |   2 +-
 arch/arm/mach-u300/timer.c                     |   5 +-
 arch/arm/mach-u300/timer.h                     |   1 +
 arch/arm/mach-u300/u300-gpio.h                 |  46 +-----
 arch/arm/mach-u300/u300.c                      |  57 -------
 drivers/pinctrl/pinctrl-coh901.c               | 220 +++++--------------------
 include/linux/platform_data/pinctrl-coh901.h   |  26 +++
 20 files changed, 171 insertions(+), 617 deletions(-)
 create mode 100644 arch/arm/mach-u300/dma_channels.h
 delete mode 100644 arch/arm/mach-u300/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-u300/include/mach/dma_channels.h
 delete mode 100644 arch/arm/mach-u300/include/mach/gpio-u300.h
 delete mode 100644 arch/arm/mach-u300/include/mach/platform.h
 create mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300.c
 create mode 100644 include/linux/platform_data/pinctrl-coh901.h

-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:57:53 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:57:53 +0200
Subject: [PATCH 3/7] pinctrl/coh901: move header to platform data dir
Message-ID: <1344859073-29370-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Move the platform-specific COH901 pin control header out of the
ARM tree and down into the proper platform data include
directory.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                    |  2 +-
 arch/arm/mach-u300/include/mach/gpio-u300.h  | 26 --------------------------
 drivers/pinctrl/pinctrl-coh901.c             |  2 +-
 include/linux/platform_data/pinctrl-coh901.h | 26 ++++++++++++++++++++++++++
 4 files changed, 28 insertions(+), 28 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/gpio-u300.h
 create mode 100644 include/linux/platform_data/pinctrl-coh901.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 883d5c2..0158189 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -31,6 +31,7 @@
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -43,7 +44,6 @@
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include <mach/dma_channels.h>
-#include <mach/gpio-u300.h>
 
 #include "spi.h"
 #include "i2c.h"
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
deleted file mode 100644
index 30dea25..0000000
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * GPIO block resgister definitions and inline macros for
- * U300 GPIO COH 901 335 or COH 901 571/3
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __MACH_U300_GPIO_U300_H
-#define __MACH_U300_GPIO_U300_H
-
-/**
- * struct u300_gpio_platform - U300 GPIO platform data
- * @ports: number of GPIO block ports
- * @gpio_base: first GPIO number for this block (use a free range)
- * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
- * @pinctrl_device: pin control device to spawn as child
- */
-struct u300_gpio_platform {
-	u8 ports;
-	int gpio_base;
-	int gpio_irq_base;
-	struct platform_device *pinctrl_device;
-};
-
-#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 91a5dc7..b446c96 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -21,7 +21,7 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <mach/gpio-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
 #define U300_GPIO_PORT_STRIDE				(0x30)
diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h
new file mode 100644
index 0000000..30dea25
--- /dev/null
+++ b/include/linux/platform_data/pinctrl-coh901.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2007-2012 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * GPIO block resgister definitions and inline macros for
+ * U300 GPIO COH 901 335 or COH 901 571/3
+ * Author: Linus Walleij <linus.walleij at stericsson.com>
+ */
+
+#ifndef __MACH_U300_GPIO_U300_H
+#define __MACH_U300_GPIO_U300_H
+
+/**
+ * struct u300_gpio_platform - U300 GPIO platform data
+ * @ports: number of GPIO block ports
+ * @gpio_base: first GPIO number for this block (use a free range)
+ * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
+ * @pinctrl_device: pin control device to spawn as child
+ */
+struct u300_gpio_platform {
+	u8 ports;
+	int gpio_base;
+	int gpio_irq_base;
+	struct platform_device *pinctrl_device;
+};
+
+#endif /* __MACH_U300_GPIO_U300_H */
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:57:47 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:57:47 +0200
Subject: [PATCH 2/7] pinctrl/coh901: retire ancient GPIO block versions
Message-ID: <1344859067-29332-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

As the non-U335 U300 variants are retired from the ARM tree,
also delete the pinctrl driver codepaths for these variants.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                   |   1 -
 arch/arm/mach-u300/include/mach/gpio-u300.h |  13 +-
 drivers/pinctrl/pinctrl-coh901.c            | 218 ++++++----------------------
 3 files changed, 43 insertions(+), 189 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1794075..883d5c2 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1440,7 +1440,6 @@ static struct platform_device pinctrl_device = {
  * GPIO block, with different number of ports.
  */
 static struct u300_gpio_platform u300_gpio_plat = {
-	.variant = U300_GPIO_COH901571_3_BS335,
 	.ports = 7,
 	.gpio_base = 0,
 	.gpio_irq_base = IRQ_U300_GPIO_BASE,
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index e81400c..30dea25 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * GPIO block resgister definitions and inline macros for
  * U300 GPIO COH 901 335 or COH 901 571/3
@@ -10,24 +10,13 @@
 #define __MACH_U300_GPIO_U300_H
 
 /**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
-	U300_GPIO_COH901335,
-	U300_GPIO_COH901571_3_BS335,
-	U300_GPIO_COH901571_3_BS365,
-};
-
-/**
  * struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
  * @ports: number of GPIO block ports
  * @gpio_base: first GPIO number for this block (use a free range)
  * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
  * @pinctrl_device: pin control device to spawn as child
  */
 struct u300_gpio_platform {
-	enum u300_gpio_variant variant;
 	u8 ports;
 	int gpio_base;
 	int gpio_irq_base;
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cc0f00d..91a5dc7 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -1,11 +1,8 @@
 /*
  * U300 GPIO module.
  *
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  * Author: Linus Walleij <linus.walleij at linaro.org>
  * Author: Jonas Aaberg <jonas.aberg at stericsson.com>
@@ -27,16 +24,19 @@
 #include <mach/gpio-u300.h>
 #include "pinctrl-coh901.h"
 
+#define U300_GPIO_PORT_STRIDE				(0x30)
 /*
- * Register definitions for COH 901 335 variant
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2  (mask 0x000001FC) contains the core version ID.
  */
-#define U300_335_PORT_STRIDE				(0x1C)
-/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
-#define U300_335_PXPDIR					(0x00)
-#define U300_335_PXPDOR					(0x00)
-/* Port X Pin Config Register 32bit (R/W) */
-#define U300_335_PXPCR					(0x04)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_CR					(0x00)
+#define U300_GPIO_CR_SYNC_SEL_ENABLE			(0x00000002UL)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE			(0x00000001UL)
+#define U300_GPIO_PXPDIR				(0x04)
+#define U300_GPIO_PXPDOR				(0x08)
+#define U300_GPIO_PXPCR					(0x0C)
 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK		(0x0000FFFFUL)
 #define U300_GPIO_PXPCR_PIN_MODE_MASK			(0x00000003UL)
 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT			(0x00000002UL)
@@ -44,53 +44,17 @@
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL	(0x00000001UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN	(0x00000002UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE	(0x00000003UL)
-/* Port X Interrupt Event Register 32bit (R/W) */
-#define U300_335_PXIEV					(0x08)
-/* Port X Interrupt Enable Register 32bit (R/W) */
-#define U300_335_PXIEN					(0x0C)
-/* Port X Interrupt Force Register 32bit (R/W) */
-#define U300_335_PXIFR					(0x10)
-/* Port X Interrupt Config Register 32bit (R/W) */
-#define U300_335_PXICR					(0x14)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_PXPER					(0x10)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK	(0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE			(0x00000001UL)
+#define U300_GPIO_PXIEV					(0x14)
+#define U300_GPIO_PXIEN					(0x18)
+#define U300_GPIO_PXIFR					(0x1C)
+#define U300_GPIO_PXICR					(0x20)
 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK		(0x000000FFUL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK			(0x00000001UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE		(0x00000000UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE		(0x00000001UL)
-/* Port X Pull-up Enable Register 32bit (R/W) */
-#define U300_335_PXPER					(0x18)
-/* This register layout is the same in both blocks */
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK	(0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE			(0x00000001UL)
-/* Control Register 32bit (R/W) */
-#define U300_335_CR					(0x54)
-#define U300_335_CR_BLOCK_CLOCK_ENABLE			(0x00000001UL)
-
-/*
- * Register definitions for COH 901 571 / 3 variant
- */
-#define U300_571_PORT_STRIDE				(0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_571_CR					(0x00)
-#define U300_571_CR_SYNC_SEL_ENABLE			(0x00000002UL)
-#define U300_571_CR_BLOCK_CLKRQ_ENABLE			(0x00000001UL)
-/*
- * These registers have the same layout and function as the corresponding
- * COH 901 335 registers, just at different offset.
- */
-#define U300_571_PXPDIR					(0x04)
-#define U300_571_PXPDOR					(0x08)
-#define U300_571_PXPCR					(0x0C)
-#define U300_571_PXPER					(0x10)
-#define U300_571_PXIEV					(0x14)
-#define U300_571_PXIEN					(0x18)
-#define U300_571_PXIFR					(0x1C)
-#define U300_571_PXICR					(0x20)
 
 /* 8 bits per port, no version has more than 7 ports */
 #define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@ struct u300_gpio_confdata {
 
 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 #define BS335_GPIO_NUM_PORTS 7
-/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
-#define BS365_GPIO_NUM_PORTS 5
 
 #define U300_FLOATING_INPUT { \
 	.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@ struct u300_gpio_confdata {
 	.outval = 1, \
 }
 
-
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 	}
 };
 
-static const struct __initconst u300_gpio_confdata
-bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-	/* Port 0, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 1, pins 0-7 */
-	{
-		U300_OUTPUT_LOW,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_HIGH,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	},
-	/* Port 2, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-	},
-	/* Port 3, pins 0-7 */
-	{
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-	},
-	/* Port 4, pins 0-7 */
-	{
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		U300_PULL_UP_INPUT,
-		/* These 4 pins doesn't exist on DB3210 */
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	}
-};
-
 /**
  * to_u300_gpio() - get the pointer to u300_gpio
  * @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
 			const struct u300_gpio_confdata *conf;
 			int offset = (i*8) + j;
 
-			if (plat->variant == U300_GPIO_COH901571_3_BS335)
-				conf = &bs335_gpio_config[i][j];
-			else if (plat->variant == U300_GPIO_COH901571_3_BS365)
-				conf = &bs365_gpio_config[i][j];
-			else
-				break;
-
+			conf = &bs335_gpio_config[i][j];
 			u300_gpio_init_pin(gpio, offset, conf);
 		}
 	}
@@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
 		goto err_no_ioremap;
 	}
 
-	if (plat->variant == U300_GPIO_COH901335) {
-		dev_info(gpio->dev,
-			 "initializing GPIO Controller COH 901 335\n");
-		gpio->stride = U300_335_PORT_STRIDE;
-		gpio->pcr = U300_335_PXPCR;
-		gpio->dor = U300_335_PXPDOR;
-		gpio->dir = U300_335_PXPDIR;
-		gpio->per = U300_335_PXPER;
-		gpio->icr = U300_335_PXICR;
-		gpio->ien = U300_335_PXIEN;
-		gpio->iev = U300_335_PXIEV;
-		ifr = U300_335_PXIFR;
-
-		/* Turn on the GPIO block */
-		writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
-		       gpio->base + U300_335_CR);
-	} else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-		   plat->variant == U300_GPIO_COH901571_3_BS365) {
-		dev_info(gpio->dev,
-			 "initializing GPIO Controller COH 901 571/3\n");
-		gpio->stride = U300_571_PORT_STRIDE;
-		gpio->pcr = U300_571_PXPCR;
-		gpio->dor = U300_571_PXPDOR;
-		gpio->dir = U300_571_PXPDIR;
-		gpio->per = U300_571_PXPER;
-		gpio->icr = U300_571_PXICR;
-		gpio->ien = U300_571_PXIEN;
-		gpio->iev = U300_571_PXIEV;
-		ifr = U300_571_PXIFR;
-
-		val = readl(gpio->base + U300_571_CR);
-		dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-			 "number of cores: %d totalling %d pins\n",
-			 ((val & 0x000001FC) >> 2),
-			 ((val & 0x0000FE00) >> 9),
-			 ((val & 0x0000FE00) >> 9) * 8);
-		writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
-		       gpio->base + U300_571_CR);
-		u300_gpio_init_coh901571(gpio, plat);
-	} else {
-		dev_err(gpio->dev, "unknown block variant\n");
-		err = -ENODEV;
-		goto err_unknown_variant;
-	}
+	dev_info(gpio->dev,
+		 "initializing GPIO Controller COH 901 571/3\n");
+	gpio->stride = U300_GPIO_PORT_STRIDE;
+	gpio->pcr = U300_GPIO_PXPCR;
+	gpio->dor = U300_GPIO_PXPDOR;
+	gpio->dir = U300_GPIO_PXPDIR;
+	gpio->per = U300_GPIO_PXPER;
+	gpio->icr = U300_GPIO_PXICR;
+	gpio->ien = U300_GPIO_PXIEN;
+	gpio->iev = U300_GPIO_PXIEV;
+	ifr = U300_GPIO_PXIFR;
+
+	val = readl(gpio->base + U300_GPIO_CR);
+	dev_info(gpio->dev, "COH901571/3 block version: %d, " \
+		 "number of cores: %d totalling %d pins\n",
+		 ((val & 0x000001FC) >> 2),
+		 ((val & 0x0000FE00) >> 9),
+		 ((val & 0x0000FE00) >> 9) * 8);
+	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
+	       gpio->base + U300_GPIO_CR);
+	u300_gpio_init_coh901571(gpio, plat);
 
 	/* Add each port with its IRQ separately */
 	INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@ err_no_pinctrl:
 err_no_chip:
 err_no_port:
 	u300_gpio_free_ports(gpio);
-err_unknown_variant:
 	iounmap(gpio->base);
 err_no_ioremap:
 	release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@ err_no_clk:
 
 static int __exit u300_gpio_remove(struct platform_device *pdev)
 {
-	struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 	struct u300_gpio *gpio = platform_get_drvdata(pdev);
 	int err;
 
 	/* Turn off the GPIO block */
-	if (plat->variant == U300_GPIO_COH901335)
-		writel(0x00000000U, gpio->base + U300_335_CR);
-	if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-	    plat->variant == U300_GPIO_COH901571_3_BS365)
-		writel(0x00000000U, gpio->base + U300_571_CR);
+	writel(0x00000000U, gpio->base + U300_GPIO_CR);
 
 	err = gpiochip_remove(&gpio->chip);
 	if (err < 0) {
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:58:00 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:58:00 +0200
Subject: [PATCH 4/7] ARM: u300: merge u300.c into core.c and rid headers
Message-ID: <1344859080-29408-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This gets rid of the separate u300.c file in mach-u300 since
it can just as well live right in core.c, then we also get
rid of the broadcasted <mach/platform.h> file that is not
helping anyone. Put the interface to the system timer into
a separate header.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/Makefile                |  1 -
 arch/arm/mach-u300/core.c                  | 22 +++++++++++++---
 arch/arm/mach-u300/include/mach/platform.h | 20 ---------------
 arch/arm/mach-u300/timer.c                 |  2 ++
 arch/arm/mach-u300/timer.h                 |  1 +
 arch/arm/mach-u300/u300.c                  | 41 ------------------------------
 6 files changed, 21 insertions(+), 66 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/platform.h
 create mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300.c

diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 7e47d37..5a86c58 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,6 @@ obj-m		:=
 obj-n		:=
 obj-		:=
 
-obj-$(CONFIG_ARCH_U300)	          += u300.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 0158189..bc23391 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -39,12 +39,15 @@
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include <mach/dma_channels.h>
 
+#include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
@@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
 	},
 };
 
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
 {
 	iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 	/* We enable a real big DMA buffer if need be. */
@@ -1600,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = {
  * together so some interrupts are connected to the first one and some
  * to the second one.
  */
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
 {
 	u32 mask[2] = {0, 0};
 	struct clk *clk;
@@ -1742,7 +1745,7 @@ static void __init u300_assign_physmem(void)
 	}
 }
 
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
 {
 	int i;
 	u16 val;
@@ -1783,7 +1786,7 @@ void __init u300_init_devices(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
 {
 	switch (mode) {
 	case 's':
@@ -1799,3 +1802,14 @@ void u300_restart(char mode, const char *cmd)
 	/* Wait for system do die/reset. */
 	while (1);
 }
+
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
+	.atag_offset	= 0x100,
+	.map_io		= u300_map_io,
+	.init_irq	= u300_init_irq,
+	.handle_irq	= vic_handle_irq,
+	.timer		= &u300_timer,
+	.init_machine	= u300_init_machine,
+	.restart	= u300_restart,
+MACHINE_END
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644
index 096333f..0000000
--- a/arch/arm/mach-u300/include/mach/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-
-#ifndef __ASSEMBLY__
-
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 56ac06d..146e815 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -26,6 +26,8 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
+#include "timer.h"
+
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644
index 0000000..b5e9791
--- /dev/null
+++ b/arch/arm/mach-u300/timer.h
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644
index 4e56e8c..0000000
--- a/arch/arm/mach-u300/u300.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-
-static void __init u300_init_machine(void)
-{
-	u300_init_devices();
-}
-
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
-	.atag_offset	= 0x100,
-	.map_io		= u300_map_io,
-	.init_irq	= u300_init_irq,
-	.handle_irq	= vic_handle_irq,
-	.timer		= &u300_timer,
-	.init_machine	= u300_init_machine,
-	.restart	= u300_restart,
-MACHINE_END
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:58:07 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:58:07 +0200
Subject: [PATCH 5/7] ARM: u300: delete remnant clkdev.h file
Message-ID: <1344859087-29444-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The U300 now uses common clk, delete this leftover.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/include/mach/clkdev.h | 7 -------
 1 file changed, 7 deletions(-)
 delete mode 100644 arch/arm/mach-u300/include/mach/clkdev.h

diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644
index 92e3cc8..0000000
--- a/arch/arm/mach-u300/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-
-#endif
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:58:14 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:58:14 +0200
Subject: [PATCH 6/7] ARM: u300: move DMA channel header into mach-u300
Message-ID: <1344859094-29480-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We were broadcasting <mach/dma_channels.h> to the entire kernel
for no reason at all, push this down into the machine folder
where it belongs.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c                      |  2 +-
 arch/arm/mach-u300/dma_channels.h              | 60 ++++++++++++++++++++++++++
 arch/arm/mach-u300/include/mach/dma_channels.h | 60 --------------------------
 arch/arm/mach-u300/spi.c                       |  2 +-
 4 files changed, 62 insertions(+), 62 deletions(-)
 create mode 100644 arch/arm/mach-u300/dma_channels.h
 delete mode 100644 arch/arm/mach-u300/include/mach/dma_channels.h

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index bc23391..31cc926 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -45,12 +45,12 @@
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/dma_channels.h>
 
 #include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
+#include "dma_channels.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
diff --git a/arch/arm/mach-u300/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
new file mode 100644
index 0000000..4e8a88f
--- /dev/null
+++ b/arch/arm/mach-u300/dma_channels.h
@@ -0,0 +1,60 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/dma_channels.h
+ *
+ *
+ * Copyright (C) 2007-2012 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Map file for the U300 dma driver.
+ * Author: Per Friden <per.friden at stericsson.com>
+ */
+
+#ifndef DMA_CHANNELS_H
+#define DMA_CHANNELS_H
+
+#define U300_DMA_MSL_TX_0             0
+#define U300_DMA_MSL_TX_1             1
+#define U300_DMA_MSL_TX_2             2
+#define U300_DMA_MSL_TX_3             3
+#define U300_DMA_MSL_TX_4             4
+#define U300_DMA_MSL_TX_5             5
+#define U300_DMA_MSL_TX_6             6
+#define U300_DMA_MSL_RX_0             7
+#define U300_DMA_MSL_RX_1             8
+#define U300_DMA_MSL_RX_2             9
+#define U300_DMA_MSL_RX_3             10
+#define U300_DMA_MSL_RX_4             11
+#define U300_DMA_MSL_RX_5             12
+#define U300_DMA_MSL_RX_6             13
+#define U300_DMA_MMCSD_RX_TX          14
+#define U300_DMA_MSPRO_TX             15
+#define U300_DMA_MSPRO_RX             16
+#define U300_DMA_UART0_TX             17
+#define U300_DMA_UART0_RX             18
+#define U300_DMA_APEX_TX              19
+#define U300_DMA_APEX_RX              20
+#define U300_DMA_PCM_I2S0_TX          21
+#define U300_DMA_PCM_I2S0_RX          22
+#define U300_DMA_PCM_I2S1_TX          23
+#define U300_DMA_PCM_I2S1_RX          24
+#define U300_DMA_XGAM_CDI             25
+#define U300_DMA_XGAM_PDI             26
+#define U300_DMA_SPI_TX               27
+#define U300_DMA_SPI_RX               28
+#define U300_DMA_GENERAL_PURPOSE_0    29
+#define U300_DMA_GENERAL_PURPOSE_1    30
+#define U300_DMA_GENERAL_PURPOSE_2    31
+#define U300_DMA_GENERAL_PURPOSE_3    32
+#define U300_DMA_GENERAL_PURPOSE_4    33
+#define U300_DMA_GENERAL_PURPOSE_5    34
+#define U300_DMA_GENERAL_PURPOSE_6    35
+#define U300_DMA_GENERAL_PURPOSE_7    36
+#define U300_DMA_GENERAL_PURPOSE_8    37
+#define U300_DMA_UART1_TX             38
+#define U300_DMA_UART1_RX             39
+
+#define U300_DMA_DEVICE_CHANNELS      32
+#define U300_DMA_CHANNELS             40
+
+
+#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
deleted file mode 100644
index 4e8a88f..0000000
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/dma_channels.h
- *
- *
- * Copyright (C) 2007-2012 ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- * Map file for the U300 dma driver.
- * Author: Per Friden <per.friden at stericsson.com>
- */
-
-#ifndef DMA_CHANNELS_H
-#define DMA_CHANNELS_H
-
-#define U300_DMA_MSL_TX_0             0
-#define U300_DMA_MSL_TX_1             1
-#define U300_DMA_MSL_TX_2             2
-#define U300_DMA_MSL_TX_3             3
-#define U300_DMA_MSL_TX_4             4
-#define U300_DMA_MSL_TX_5             5
-#define U300_DMA_MSL_TX_6             6
-#define U300_DMA_MSL_RX_0             7
-#define U300_DMA_MSL_RX_1             8
-#define U300_DMA_MSL_RX_2             9
-#define U300_DMA_MSL_RX_3             10
-#define U300_DMA_MSL_RX_4             11
-#define U300_DMA_MSL_RX_5             12
-#define U300_DMA_MSL_RX_6             13
-#define U300_DMA_MMCSD_RX_TX          14
-#define U300_DMA_MSPRO_TX             15
-#define U300_DMA_MSPRO_RX             16
-#define U300_DMA_UART0_TX             17
-#define U300_DMA_UART0_RX             18
-#define U300_DMA_APEX_TX              19
-#define U300_DMA_APEX_RX              20
-#define U300_DMA_PCM_I2S0_TX          21
-#define U300_DMA_PCM_I2S0_RX          22
-#define U300_DMA_PCM_I2S1_TX          23
-#define U300_DMA_PCM_I2S1_RX          24
-#define U300_DMA_XGAM_CDI             25
-#define U300_DMA_XGAM_PDI             26
-#define U300_DMA_SPI_TX               27
-#define U300_DMA_SPI_RX               28
-#define U300_DMA_GENERAL_PURPOSE_0    29
-#define U300_DMA_GENERAL_PURPOSE_1    30
-#define U300_DMA_GENERAL_PURPOSE_2    31
-#define U300_DMA_GENERAL_PURPOSE_3    32
-#define U300_DMA_GENERAL_PURPOSE_4    33
-#define U300_DMA_GENERAL_PURPOSE_5    34
-#define U300_DMA_GENERAL_PURPOSE_6    35
-#define U300_DMA_GENERAL_PURPOSE_7    36
-#define U300_DMA_GENERAL_PURPOSE_8    37
-#define U300_DMA_UART1_TX             38
-#define U300_DMA_UART1_RX             39
-
-#define U300_DMA_DEVICE_CHANNELS      32
-#define U300_DMA_CHANNELS             40
-
-
-#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index a1affac..02e6659 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
 
 /*
  * The following is for the actual devices on the SSP/SPI bus
-- 
1.7.11.3



From linus.walleij at stericsson.com  Mon Aug 13 07:58:23 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 13 Aug 2012 13:58:23 +0200
Subject: [PATCH 7/7] ARM: u300: convert to sparse IRQs
Message-ID: <1344859103-29517-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the U300 to use sparse IRQs, which is simple now
that the number of machines are reduced.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                       | 1 +
 arch/arm/mach-u300/core.c              | 3 ++-
 arch/arm/mach-u300/include/mach/irqs.h | 2 +-
 arch/arm/mach-u300/timer.c             | 3 ++-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..0fb682d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -937,6 +937,7 @@ config ARCH_U300
 	select COMMON_CLK
 	select GENERIC_GPIO
 	select ARCH_REQUIRE_GPIOLIB
+	select SPARSE_IRQ
 	help
 	  Support for ST-Ericsson U300 series mobile platforms.
 
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 31cc926..ef6f602 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -38,13 +38,13 @@
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
+#include <mach/irqs.h>
 
 #include "timer.h"
 #include "spi.h"
@@ -1807,6 +1807,7 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
 	/* Maintainer: Linus Walleij <linus.walleij at stericsson.com> */
 	.atag_offset	= 0x100,
 	.map_io		= u300_map_io,
+	.nr_irqs	= NR_IRQS_U300,
 	.init_irq	= u300_init_irq,
 	.handle_irq	= vic_handle_irq,
 	.timer		= &u300_timer,
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index c09386b..e27425a 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -85,6 +85,6 @@
 #define IRQ_U300_GPIO_END		(U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS				(IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300			(IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 146e815..1da10e2 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -17,14 +17,15 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
 
 #include "timer.h"
 
-- 
1.7.11.3



From broonie at opensource.wolfsonmicro.com  Mon Aug 13 08:24:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 13 Aug 2012 13:24:00 +0100
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
 <20120810100713.GH24328@opensource.wolfsonmicro.com>
 <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>
Message-ID: <20120813122359.GA13446@opensource.wolfsonmicro.com>

On Sat, Aug 11, 2012 at 02:08:09PM +0900, Kukjin Kim wrote:

> BTW, don't you need to enable your Cragganmore board in the defconfig?

Well, it doesn't really matter that much to us - it's more a question
for whoever uses the defconfig.


From broonie at opensource.wolfsonmicro.com  Mon Aug 13 08:51:58 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 13 Aug 2012 13:51:58 +0100
Subject: [PATCH 00/10 V3] MXS SPI driver
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <20120813125158.GE13446@opensource.wolfsonmicro.com>

On Fri, Aug 03, 2012 at 05:26:05PM +0200, Marek Vasut wrote:
> This patchset adds SPI master support for Freescale i.MX233/i.MX28.
> This is rebased on top of next-20120713. Please consider applying,
> bugs shall now be squashed during the previous two review rounds.

Do we have any ETA for review from the MMC side?  I'd like to get these
patches out of my queue one way or another, it seems like for the simple
code motion bits at least we should be easy enough to get out of the
way.


From shawn.guo at linaro.org  Mon Aug 13 09:05:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:21 +0800
Subject: [PATCH 01/17] ARM: dts: imx6q: improve indentation for fsl,pins
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-2-git-send-email-shawn.guo@linaro.org>

Change the indentation for property fsl,pins a little bit, so that
the first and the last line get the same indentation with all other
lines.  Then it will be easier to copy and past any of these lines.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    6 +-
 arch/arm/boot/dts/imx6q.dtsi          |  114 ++++++++++++++++++--------------
 2 files changed, 67 insertions(+), 53 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d42e851..ee5de8f 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -51,9 +51,9 @@
 				gpios {
 					pinctrl_gpio_hog: gpiohog {
 						fsl,pins = <
-							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-							   >;
+							144 0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+							121 0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+						>;
 					};
 				};
 			};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 28b6a62..bd72a4f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -506,86 +506,100 @@
 				/* shared pinctrl settings */
 				audmux {
 					pinctrl_audmux_1: audmux-1 {
-						fsl,pins = <18   0x80000000	/* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
-							    1586 0x80000000	/* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
-							    11   0x80000000	/* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
-							    3    0x80000000>;	/* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+						fsl,pins = <
+							18   0x80000000	/* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+							1586 0x80000000	/* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+							11   0x80000000	/* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+							3    0x80000000	/* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+						>;
 					};
 				};
 
 				gpmi-nand {
 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
-						fsl,pins = <1328 0xb0b1		/* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
-							    1336 0xb0b1		/* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
-							    1344 0xb0b1		/* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
-							    1352 0xb000		/* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
-							    1360 0xb0b1		/* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
-							    1365 0xb0b1		/* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
-							    1371 0xb0b1		/* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
-							    1378 0xb0b1		/* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
-							    1387 0xb0b1		/* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
-							    1393 0xb0b1		/* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
-							    1397 0xb0b1		/* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
-							    1405 0xb0b1		/* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
-							    1413 0xb0b1		/* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
-							    1421 0xb0b1		/* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
-							    1429 0xb0b1		/* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
-							    1437 0xb0b1		/* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
-							    1445 0xb0b1		/* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
-							    1453 0xb0b1		/* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
-							    1463 0x00b1>;	/* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+						fsl,pins = <
+							1328 0xb0b1	/* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+							1336 0xb0b1	/* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+							1344 0xb0b1	/* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+							1352 0xb000	/* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+							1360 0xb0b1	/* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+							1365 0xb0b1	/* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+							1371 0xb0b1	/* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+							1378 0xb0b1	/* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+							1387 0xb0b1	/* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+							1393 0xb0b1	/* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+							1397 0xb0b1	/* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+							1405 0xb0b1	/* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+							1413 0xb0b1	/* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+							1421 0xb0b1	/* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+							1429 0xb0b1	/* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+							1437 0xb0b1	/* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+							1445 0xb0b1	/* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+							1453 0xb0b1	/* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+							1463 0x00b1	/* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+						>;
 					};
 				};
 
 				i2c1 {
 					pinctrl_i2c1_1: i2c1grp-1 {
-						fsl,pins = <137 0x4001b8b1	/* MX6Q_PAD_EIM_D21__I2C1_SCL */
-							    196 0x4001b8b1>;	/* MX6Q_PAD_EIM_D28__I2C1_SDA */
+						fsl,pins = <
+							137 0x4001b8b1	/* MX6Q_PAD_EIM_D21__I2C1_SCL */
+							196 0x4001b8b1	/* MX6Q_PAD_EIM_D28__I2C1_SDA */
+						>;
 					};
 				};
 
 				serial2 {
 					pinctrl_serial2_1: serial2grp-1 {
-						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
-							    191 0x1b0b1>;	/* MX6Q_PAD_EIM_D27__UART2_RXD */
+						fsl,pins = <
+							183 0x1b0b1	/* MX6Q_PAD_EIM_D26__UART2_TXD */
+							191 0x1b0b1	/* MX6Q_PAD_EIM_D27__UART2_RXD */
+						>;
 					};
 				};
 
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
-						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-							    1281 0x10059	/* MX6Q_PAD_SD3_CLK__USDHC3_CLK	*/
-							    1289 0x17059	/* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-							    1297 0x17059	/* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-							    1305 0x17059	/* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-							    1312 0x17059	/* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
-							    1265 0x17059	/* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
-							    1257 0x17059	/* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
-							    1249 0x17059	/* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
-							    1241 0x17059>;	/* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+						fsl,pins = <
+							1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+							1281 0x10059	/* MX6Q_PAD_SD3_CLK__USDHC3_CLK	*/
+							1289 0x17059	/* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+							1297 0x17059	/* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+							1305 0x17059	/* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+							1312 0x17059	/* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+							1265 0x17059	/* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+							1257 0x17059	/* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+							1249 0x17059	/* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+							1241 0x17059	/* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+						>;
 					};
 				};
 
 				usdhc4 {
 					pinctrl_usdhc4_1: usdhc4grp-1 {
-						fsl,pins = <1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-							    1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/
-							    1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-							    1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-							    1478 0x17059	/* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-							    1486 0x17059	/* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-							    1493 0x17059	/* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-							    1501 0x17059	/* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-							    1509 0x17059	/* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-							    1517 0x17059>;	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+						fsl,pins = <
+							1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+							1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/
+							1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+							1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+							1478 0x17059	/* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+							1486 0x17059	/* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+							1493 0x17059	/* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+							1501 0x17059	/* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+							1509 0x17059	/* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+							1517 0x17059	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+						>;
 					};
 				};
 
 				ecspi1 {
 					pinctrl_ecspi1_1: ecspi1grp-1 {
-						fsl,pins = <101 0x100b1		/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
-							    109 0x100b1		/* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-							    94  0x100b1>;	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+						fsl,pins = <
+							101 0x100b1	/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+							109 0x100b1	/* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+							94  0x100b1	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+						>;
 					};
 				};
 			};
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:20 +0800
Subject: [PATCH 00/17] ARM: imx: add pinctrl settings for DT boot
Message-ID: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>

The series adds pinctrl settings for imx6q, imx53 and imx51 booting
from DT.  As the results, the dummy pinctrl state gets removed from
these DT images, and all imx53 board files get removed from the tree.
Therefore, imx53 becomes the second DT only i.MX SoC besides imx6q.

Shawn Guo (17):
  ARM: dts: imx6q: improve indentation for fsl,pins
  ARM: dts: imx6q: name iomuxc sub-nodes following pin function
  ARM: dts: imx6q: sort iomuxc sub-nodes in name
  ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet
  ARM: dts: imx6q-arm2: add pinctrl for uart and enet
  ARM: dts: imx6q-sabresd: add pinctrl settings
  ARM: imx6q: remove dummy pinctrl state
  ARM: dts: imx53-qsb: add pinctrl settings
  ARM: dts: imx53-ard: add pinctrl settings
  ARM: dts: imx53-evk: add pinctrl settings
  ARM: dts: imx53-smd: add pinctrl settings
  ARM: imx53: build in pinctrl support
  ARM: imx53: decouple device tree boot from board files
  ARM: imx53: support device tree boot only
  ARM: imx53: remove unneeded files and functions
  ARM: dts: imx51-babbage: add pinctrl settings
  ARM: imx51: build in pinctrl support

 arch/arm/boot/dts/imx51-babbage.dts            |   36 +-
 arch/arm/boot/dts/imx51.dtsi                   |  116 +++
 arch/arm/boot/dts/imx53-ard.dts                |   49 +-
 arch/arm/boot/dts/imx53-evk.dts                |   31 +-
 arch/arm/boot/dts/imx53-qsb.dts                |   34 +-
 arch/arm/boot/dts/imx53-smd.dts                |   38 +-
 arch/arm/boot/dts/imx53.dtsi                   |  155 +++
 arch/arm/boot/dts/imx6q-arm2.dts               |   21 +
 arch/arm/boot/dts/imx6q-sabrelite.dts          |   19 +-
 arch/arm/boot/dts/imx6q-sabresd.dts            |   25 +-
 arch/arm/boot/dts/imx6q.dtsi                   |  223 ++++--
 arch/arm/configs/imx_v6_v7_defconfig           |    2 +-
 arch/arm/mach-imx/Kconfig                      |   79 +--
 arch/arm/mach-imx/Makefile                     |    6 +-
 arch/arm/mach-imx/Makefile.boot                |    8 +-
 arch/arm/mach-imx/devices-imx53.h              |   48 -
 arch/arm/mach-imx/imx51-dt.c                   |    3 -
 arch/arm/mach-imx/{imx53-dt.c => mach-imx53.c} |   23 -
 arch/arm/mach-imx/mach-imx6q.c                 |    7 -
 arch/arm/mach-imx/mach-mx53_ard.c              |  272 ------
 arch/arm/mach-imx/mach-mx53_evk.c              |  179 ----
 arch/arm/mach-imx/mach-mx53_loco.c             |  321 -------
 arch/arm/mach-imx/mach-mx53_smd.c              |  168 ----
 arch/arm/mach-imx/mm-imx5.c                    |   47 -
 arch/arm/plat-mxc/include/mach/common.h        |    5 -
 arch/arm/plat-mxc/include/mach/iomux-mx53.h    | 1219 ------------------------
 26 files changed, 697 insertions(+), 2437 deletions(-)
 delete mode 100644 arch/arm/mach-imx/devices-imx53.h
 rename arch/arm/mach-imx/{imx53-dt.c => mach-imx53.c} (82%)
 delete mode 100644 arch/arm/mach-imx/mach-mx53_ard.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_evk.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_loco.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_smd.c
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h

-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:22 +0800
Subject: [PATCH 02/17] ARM: dts: imx6q: name iomuxc sub-nodes following pin
 function
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-3-git-send-email-shawn.guo@linaro.org>

Name iomuxc sub-nodes following pin function and hardware manual.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    2 +-
 arch/arm/boot/dts/imx6q.dtsi          |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index ee5de8f..1a99257 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -98,7 +98,7 @@
 			uart2: serial at 021e8000 {
 				status = "okay";
 				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_serial2_1>;
+				pinctrl-0 = <&pinctrl_uart2_1>;
 			};
 
 			i2c at 021a0000 { /* I2C1 */
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bd72a4f..a078436 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -550,8 +550,8 @@
 					};
 				};
 
-				serial2 {
-					pinctrl_serial2_1: serial2grp-1 {
+				uart2 {
+					pinctrl_uart2_1: uart2grp-1 {
 						fsl,pins = <
 							183 0x1b0b1	/* MX6Q_PAD_EIM_D26__UART2_TXD */
 							191 0x1b0b1	/* MX6Q_PAD_EIM_D27__UART2_RXD */
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:24 +0800
Subject: [PATCH 04/17] ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and
 enet
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-5-git-send-email-shawn.guo@linaro.org>

Add missing pinctrl of usdhc and enet for imx6q-sabrelite board.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |   15 +++++++++-
 arch/arm/boot/dts/imx6q.dtsi          |   44 +++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 1a99257..6d8f68d 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -51,8 +51,13 @@
 				gpios {
 					pinctrl_gpio_hog: gpiohog {
 						fsl,pins = <
-							144 0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-							121 0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+							1450 0x80000000	/* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+							1458 0x80000000	/* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+							121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+							144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+							152  0x80000000	/* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+							1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+							1270 0x1f0b0	/* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
 						>;
 					};
 				};
@@ -70,12 +75,16 @@
 			};
 
 			ethernet at 02188000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_enet_1>;
 				phy-mode = "rgmii";
 				phy-reset-gpios = <&gpio3 23 0>;
 				status = "okay";
 			};
 
 			usdhc at 02198000 { /* uSDHC3 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usdhc3_2>;
 				cd-gpios = <&gpio7 0 0>;
 				wp-gpios = <&gpio7 1 0>;
 				vmmc-supply = <&reg_3p3v>;
@@ -83,6 +92,8 @@
 			};
 
 			usdhc at 0219c000 { /* uSDHC4 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usdhc4_2>;
 				cd-gpios = <&gpio2 6 0>;
 				wp-gpios = <&gpio2 7 0>;
 				vmmc-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e8595fa..6bdfeea 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -525,6 +525,28 @@
 					};
 				};
 
+				enet {
+					pinctrl_enet_1: enetgrp-1 {
+						fsl,pins = <
+							695 0x1b0b0	/* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+							756 0x1b0b0	/* MX6Q_PAD_ENET_MDC__ENET_MDC */
+							24  0x1b0b0	/* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+							30  0x1b0b0	/* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+							34  0x1b0b0	/* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+							39  0x1b0b0	/* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+							44  0x1b0b0	/* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+							56  0x1b0b0	/* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+							702 0x1b0b0	/* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+							74  0x1b0b0	/* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+							52  0x1b0b0	/* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+							61  0x1b0b0	/* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+							66  0x1b0b0	/* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+							70  0x1b0b0	/* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+							48  0x1b0b0	/* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+						>;
+					};
+				};
+
 				gpmi-nand {
 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
 						fsl,pins = <
@@ -584,6 +606,17 @@
 							1241 0x17059	/* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
 						>;
 					};
+
+					pinctrl_usdhc3_2: usdhc3grp-2 {
+						fsl,pins = <
+							1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+							1281 0x10059	/* MX6Q_PAD_SD3_CLK__USDHC3_CLK	*/
+							1289 0x17059	/* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+							1297 0x17059	/* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+							1305 0x17059	/* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+							1312 0x17059	/* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+						>;
+					};
 				};
 
 				usdhc4 {
@@ -601,6 +634,17 @@
 							1517 0x17059	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
 						>;
 					};
+
+					pinctrl_usdhc4_2: usdhc4grp-2 {
+						fsl,pins = <
+							1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+							1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/
+							1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+							1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+							1478 0x17059	/* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+							1486 0x17059	/* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+						>;
+					};
 				};
 			};
 
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:23 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:23 +0800
Subject: [PATCH 03/17] ARM: dts: imx6q: sort iomuxc sub-nodes in name
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-4-git-send-email-shawn.guo@linaro.org>

Sort iomuxc sub-nodes in name so that the node can be located a little
bit easier.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index a078436..e8595fa 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -515,6 +515,16 @@
 					};
 				};
 
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							101 0x100b1	/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+							109 0x100b1	/* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+							94  0x100b1	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+						>;
+					};
+				};
+
 				gpmi-nand {
 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
 						fsl,pins = <
@@ -592,16 +602,6 @@
 						>;
 					};
 				};
-
-				ecspi1 {
-					pinctrl_ecspi1_1: ecspi1grp-1 {
-						fsl,pins = <
-							101 0x100b1	/* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
-							109 0x100b1	/* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-							94  0x100b1	/* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
-						>;
-					};
-				};
 			};
 
 			dcic at 020e4000 { /* DCIC1 */
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:27 +0800
Subject: [PATCH 07/17] ARM: imx6q: remove dummy pinctrl state
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-8-git-send-email-shawn.guo@linaro.org>

As all imx6q boards have pinctrl set up in device tree, it's time to
remove the dummy pinctrl state.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-imx6q.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..946cfcc 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,7 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/anatop.h>
@@ -159,12 +158,6 @@ static void __init imx6q_usb_init(void)
 
 static void __init imx6q_init_machine(void)
 {
-	/*
-	 * This should be removed when all imx6q boards have pinctrl
-	 * states for devices defined in device tree.
-	 */
-	pinctrl_provide_dummies();
-
 	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 		imx6q_sabrelite_init();
 
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:29 +0800
Subject: [PATCH 09/17] ARM: dts: imx53-ard: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-10-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for the exsiting devices in imx53-ard.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx53-ard.dts |   49 +++++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/imx53.dtsi    |   22 +++++++++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index b548b9c..0433056 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,6 +25,8 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc1_2>;
 					cd-gpios = <&gpio1 1 0>;
 					wp-gpios = <&gpio1 9 0>;
 					status = "okay";
@@ -32,11 +34,54 @@
 			};
 
 			iomuxc at 53fa8000 {
-				compatible = "fsl,imx53-iomuxc-ard";
-				reg = <0x53fa8000 0x4000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							1077 0x80000000	/* MX53_PAD_GPIO_1__GPIO1_1 */
+							1085 0x80000000	/* MX53_PAD_GPIO_9__GPIO1_9 */
+							486  0x80000000	/* MX53_PAD_EIM_EB3__GPIO2_31 */
+							739  0x80000000	/* MX53_PAD_GPIO_10__GPIO4_0 */
+							218  0x80000000	/* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+							226  0x80000000	/* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+							233  0x80000000	/* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+							241  0x80000000	/* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+							429  0x80000000	/* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+							435  0x80000000	/* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+							441  0x80000000	/* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+							448  0x80000000	/* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+							456  0x80000000	/* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+							464  0x80000000	/* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+							471  0x80000000	/* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+							477  0x80000000	/* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+							492  0x80000000	/* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+							500  0x80000000	/* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+							508  0x80000000	/* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+							516  0x80000000	/* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+							524  0x80000000	/* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+							532  0x80000000	/* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+							540  0x80000000	/* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+							548  0x80000000	/* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+							637  0x80000000	/* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+							642  0x80000000	/* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+							647  0x80000000	/* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+							652  0x80000000	/* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+							657  0x80000000	/* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+							662  0x80000000	/* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+							667  0x80000000	/* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+							611  0x80000000	/* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+							616  0x80000000	/* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+							607  0x80000000	/* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 53fbc000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1_2>;
 				status = "okay";
 			};
 		};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 35d102d..9721e16 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -224,6 +224,21 @@
 							1018 0x1d5	/* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 						>;
 					};
+
+					pinctrl_esdhc1_2: esdhc1grp-2 {
+						fsl,pins = <
+							995  0x1d5	/* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+							1000 0x1d5	/* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+							1010 0x1d5	/* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+							1024 0x1d5	/* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+							941  0x1d5	/* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+							948  0x1d5	/* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+							955  0x1d5	/* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+							962  0x1d5	/* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+							1005 0x1d5	/* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+							1018 0x1d5	/* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+						>;
+					};
 				};
 
 				esdhc3 {
@@ -268,6 +283,13 @@
 							354 0x1c5	/* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
 						>;
 					};
+
+					pinctrl_uart1_2: uart1grp-2 {
+						fsl,pins = <
+							828 0x1c5	/* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+							832 0x1c5	/* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+						>;
+					};
 				};
 			};
 
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:26 +0800
Subject: [PATCH 06/17] ARM: dts: imx6q-sabresd: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-7-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for existing devices in imx6q-sabresd.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q-sabresd.dts |   25 ++++++++++++++++++++++++-
 arch/arm/boot/dts/imx6q.dtsi        |   26 ++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a1..e596c28c 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
 	};
 
 	soc {
-
 		aips-bus at 02000000 { /* AIPS1 */
 			spba-bus at 02000000 {
 				uart1: serial at 02020000 {
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_uart1_1>;
 					status = "okay";
 				};
 			};
+
+			iomuxc at 020e0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							1402 0x80000000	/* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+							1410 0x80000000	/* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+							1418 0x80000000	/* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+							1426 0x80000000	/* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+						>;
+					};
+				};
+			};
 		};
 
 		aips-bus at 02100000 { /* AIPS2 */
 			ethernet at 02188000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_enet_1>;
 				phy-mode = "rgmii";
 				status = "okay";
 			};
 
 			usdhc at 02194000 { /* uSDHC2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usdhc2_1>;
 				cd-gpios = <&gpio2 2 0>;
 				wp-gpios = <&gpio2 3 0>;
 				status = "okay";
 			};
 
 			usdhc at 02198000 { /* uSDHC3 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usdhc3_1>;
 				cd-gpios = <&gpio2 0 0>;
 				wp-gpios = <&gpio2 1 0>;
 				status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 23d680a..3b97212 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -602,6 +602,15 @@
 					};
 				};
 
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							1140 0x1b0b1	/* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+							1148 0x1b0b1	/* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+						>;
+					};
+				};
+
 				uart2 {
 					pinctrl_uart2_1: uart2grp-1 {
 						fsl,pins = <
@@ -620,6 +629,23 @@
 					};
 				};
 
+				usdhc2 {
+					pinctrl_usdhc2_1: usdhc2grp-1 {
+						fsl,pins = <
+							1577 0x17059	/* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+							1569 0x10059	/* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+							16   0x17059	/* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+							0    0x17059	/* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+							8    0x17059	/* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+							1583 0x17059	/* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+							1430 0x17059	/* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+							1438 0x17059	/* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+							1446 0x17059	/* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+							1454 0x17059	/* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+						>;
+					};
+				};
+
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
 						fsl,pins = <
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:30 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:30 +0800
Subject: [PATCH 10/17] ARM: dts: imx53-evk: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-11-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for the exsiting devices in imx53-evk.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx53-evk.dts |   31 +++++++++++++++++++++++++++++--
 arch/arm/boot/dts/imx53.dtsi    |   10 ++++++++++
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 86aebc5..43f8f03 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc1_1>;
 					cd-gpios = <&gpio3 13 0>;
 					wp-gpios = <&gpio3 14 0>;
 					status = "okay";
 				};
 
 				ecspi at 50010000 { /* ECSPI1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_ecspi1_1>;
 					fsl,spi-num-chipselects = <2>;
 					cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
 					status = "okay";
@@ -56,6 +60,8 @@
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc3_1>;
 					cd-gpios = <&gpio3 11 0>;
 					wp-gpios = <&gpio3 12 0>;
 					status = "okay";
@@ -63,17 +69,36 @@
 			};
 
 			iomuxc at 53fa8000 {
-				compatible = "fsl,imx53-iomuxc-evk";
-				reg = <0x53fa8000 0x4000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							424 0x80000000	/* MX53_PAD_EIM_EB2__GPIO2_30 */
+							449 0x80000000	/* MX53_PAD_EIM_D19__GPIO3_19 */
+							693 0x80000000	/* MX53_PAD_EIM_DA11__GPIO3_11 */
+							697 0x80000000	/* MX53_PAD_EIM_DA12__GPIO3_12 */
+							701 0x80000000	/* MX53_PAD_EIM_DA13__GPIO3_13 */
+							705 0x80000000	/* MX53_PAD_EIM_DA14__GPIO3_14 */
+							868 0x80000000	/* MX53_PAD_PATA_DA_0__GPIO7_6 */
+							873 0x80000000	/* MX53_PAD_PATA_DA_1__GPIO7_7 */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 53fbc000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1_1>;
 				status = "okay";
 			};
 		};
 
 		aips at 60000000 {	/* AIPS2 */
 			i2c at 63fc4000 { /* I2C2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c2_1>;
 				status = "okay";
 
 				pmic: mc13892 at 08 {
@@ -88,6 +113,8 @@
 			};
 
 			ethernet at 63fec000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_fec_1>;
 				phy-mode = "rmii";
 				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 9721e16..e91cbc0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -213,6 +213,16 @@
 					};
 				};
 
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							433 0x80000000	/* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+							439 0x80000000	/* MX53_PAD_EIM_D17__ECSPI1_MISO */
+							445 0x80000000	/* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+						>;
+					};
+				};
+
 				esdhc1 {
 					pinctrl_esdhc1_1: esdhc1grp-1 {
 						fsl,pins = <
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:25 +0800
Subject: [PATCH 05/17] ARM: dts: imx6q-arm2: add pinctrl for uart and enet
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-6-git-send-email-shawn.guo@linaro.org>

Add missing pinctrl of uart and enet for imx6q-arm2 board.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q-arm2.dts |   21 +++++++++++++++++++++
 arch/arm/boot/dts/imx6q.dtsi     |   29 +++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581..15df4c1 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
 			status = "disabled"; /* gpmi nand conflicts with SD */
 		};
 
+		aips-bus at 02000000 { /* AIPS1 */
+			iomuxc at 020e0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							176  0x80000000	/* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+							1363 0x80000000	/* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+							1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+						>;
+					};
+				};
+			};
+		};
+
 		aips-bus at 02100000 { /* AIPS2 */
 			ethernet at 02188000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_enet_2>;
 				phy-mode = "rgmii";
 				status = "okay";
 			};
@@ -52,6 +71,8 @@
 			};
 
 			uart4: serial at 021f0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart4_1>;
 				status = "okay";
 			};
 		};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 6bdfeea..23d680a 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -545,6 +545,26 @@
 							48  0x1b0b0	/* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
 						>;
 					};
+
+					pinctrl_enet_2: enetgrp-2 {
+						fsl,pins = <
+							890 0x1b0b0	/* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+							909 0x1b0b0	/* MX6Q_PAD_KEY_COL2__ENET_MDC */
+							24  0x1b0b0	/* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+							30  0x1b0b0	/* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+							34  0x1b0b0	/* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+							39  0x1b0b0	/* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+							44  0x1b0b0	/* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+							56  0x1b0b0	/* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+							702 0x1b0b0	/* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+							74  0x1b0b0	/* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+							52  0x1b0b0	/* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+							61  0x1b0b0	/* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+							66  0x1b0b0	/* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+							70  0x1b0b0	/* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+							48  0x1b0b0	/* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+						>;
+					};
 				};
 
 				gpmi-nand {
@@ -591,6 +611,15 @@
 					};
 				};
 
+				uart4 {
+					pinctrl_uart4_1: uart4grp-1 {
+						fsl,pins = <
+							877 0x1b0b1	/* MX6Q_PAD_KEY_COL0__UART4_TXD */
+							885 0x1b0b1	/* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+						>;
+					};
+				};
+
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
 						fsl,pins = <
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:28 +0800
Subject: [PATCH 08/17] ARM: dts: imx53-qsb: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-9-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for existing devices in imx53-qsb.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx53-qsb.dts |   34 ++++++++++++++-
 arch/arm/boot/dts/imx53.dtsi    |   90 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index a0e816f..08948af 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc1_1>;
 					cd-gpios = <&gpio3 13 0>;
 					status = "okay";
 				};
@@ -35,6 +37,8 @@
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc3_1>;
 					cd-gpios = <&gpio3 11 0>;
 					wp-gpios = <&gpio3 12 0>;
 					status = "okay";
@@ -42,17 +46,37 @@
 			};
 
 			iomuxc at 53fa8000 {
-				compatible = "fsl,imx53-iomuxc-qsb";
-				reg = <0x53fa8000 0x4000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							1071 0x80000000	/* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+							1141 0x80000000	/* MX53_PAD_GPIO_8__GPIO1_8 */
+							982  0x80000000	/* MX53_PAD_PATA_DATA14__GPIO2_14 */
+							989  0x80000000	/* MX53_PAD_PATA_DATA15__GPIO2_15 */
+							693  0x80000000	/* MX53_PAD_EIM_DA11__GPIO3_11 */
+							697  0x80000000	/* MX53_PAD_EIM_DA12__GPIO3_12 */
+							701  0x80000000	/* MX53_PAD_EIM_DA13__GPIO3_13 */
+							868  0x80000000	/* MX53_PAD_PATA_DA_0__GPIO7_6 */
+							873  0x80000000	/* MX53_PAD_PATA_DA_1__GPIO7_7 */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 53fbc000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1_1>;
 				status = "okay";
 			};
 		};
 
 		aips at 60000000 {	/* AIPS2 */
 			i2c at 63fc4000 { /* I2C2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c2_1>;
 				status = "okay";
 
 				sgtl5000: codec at 0a {
@@ -64,6 +88,8 @@
 			};
 
 			i2c at 63fc8000 { /* I2C1 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c1_1>;
 				status = "okay";
 
 				accelerometer: mma8450 at 1c {
@@ -150,10 +176,14 @@
 			};
 
 			audmux at 63fd0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_audmux_1>;
 				status = "okay";
 			};
 
 			ethernet at 63fec000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_fec_1>;
 				phy-mode = "rmii";
 				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 0b928fe..35d102d 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -181,6 +181,96 @@
 				status = "disabled";
 			};
 
+			iomuxc at 53fa8000 {
+				compatible = "fsl,imx53-iomuxc";
+				reg = <0x53fa8000 0x4000>;
+
+				audmux {
+					pinctrl_audmux_1: audmuxgrp-1 {
+						fsl,pins = <
+							10 0x80000000	/* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+							17 0x80000000	/* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+							23 0x80000000	/* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+							30 0x80000000	/* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+						>;
+					};
+				};
+
+				fec {
+					pinctrl_fec_1: fecgrp-1 {
+						fsl,pins = <
+							820 0x80000000	/* MX53_PAD_FEC_MDC__FEC_MDC */
+							779 0x80000000	/* MX53_PAD_FEC_MDIO__FEC_MDIO */
+							786 0x80000000	/* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+							791 0x80000000	/* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+							796 0x80000000	/* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+							799 0x80000000	/* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+							804 0x80000000	/* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+							808 0x80000000	/* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+							811 0x80000000	/* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+							816 0x80000000	/* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+						>;
+					};
+				};
+
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp-1 {
+						fsl,pins = <
+							995  0x1d5	/* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+							1000 0x1d5	/* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+							1010 0x1d5	/* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+							1024 0x1d5	/* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+							1005 0x1d5	/* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+							1018 0x1d5	/* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+						>;
+					};
+				};
+
+				esdhc3 {
+					pinctrl_esdhc3_1: esdhc3grp-1 {
+						fsl,pins = <
+							943 0x1d5	/* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+							950 0x1d5	/* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+							957 0x1d5	/* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+							964 0x1d5	/* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+							893 0x1d5	/* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+							900 0x1d5	/* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+							906 0x1d5	/* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+							912 0x1d5	/* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+							857 0x1d5	/* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+							863 0x1d5	/* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+						>;
+					};
+				};
+
+				i2c1 {
+					pinctrl_i2c1_1: i2c1grp-1 {
+						fsl,pins = <
+							333 0xc0000000	/* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+							341 0xc0000000	/* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+						>;
+					};
+				};
+
+				i2c2 {
+					pinctrl_i2c2_1: i2c2grp-1 {
+						fsl,pins = <
+							61 0xc0000000	/* MX53_PAD_KEY_ROW3__I2C2_SDA */
+							53 0xc0000000	/* MX53_PAD_KEY_COL3__I2C2_SCL */
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							346 0x1c5	/* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+							354 0x1c5	/* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+						>;
+					};
+				};
+			};
+
 			uart1: serial at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:31 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:31 +0800
Subject: [PATCH 11/17] ARM: dts: imx53-smd: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-12-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for the exsiting devices in imx53-smd.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx53-smd.dts |   38 ++++++++++++++++++++++++++++++++++++--
 arch/arm/boot/dts/imx53.dtsi    |   33 +++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 8cdf0a2..dd7e792 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
 		aips at 50000000 { /* AIPS1 */
 			spba at 50000000 {
 				esdhc at 50004000 { /* ESDHC1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc1_1>;
 					cd-gpios = <&gpio3 13 0>;
 					wp-gpios = <&gpio4 11 0>;
 					status = "okay";
 				};
 
 				esdhc at 50008000 { /* ESDHC2 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc2_1>;
 					non-removable;
 					status = "okay";
 				};
 
 				uart3: serial at 5000c000 {
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_uart3_1>;
 					fsl,uart-has-rtscts;
 					status = "okay";
 				};
 
 				ecspi at 50010000 { /* ECSPI1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_ecspi1_1>;
 					fsl,spi-num-chipselects = <2>;
 					cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
 					status = "okay";
@@ -72,27 +80,49 @@
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc3_1>;
 					non-removable;
 					status = "okay";
 				};
 			};
 
 			iomuxc at 53fa8000 {
-				compatible = "fsl,imx53-iomuxc-smd";
-				reg = <0x53fa8000 0x4000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							982 0x80000000	/* MX53_PAD_PATA_DATA14__GPIO2_14 */
+							989 0x80000000	/* MX53_PAD_PATA_DATA15__GPIO2_15 */
+							424 0x80000000	/* MX53_PAD_EIM_EB2__GPIO2_30 */
+							701 0x80000000	/* MX53_PAD_EIM_DA13__GPIO3_13 */
+							449 0x80000000	/* MX53_PAD_EIM_D19__GPIO3_19 */
+							43  0x80000000	/* MX53_PAD_KEY_ROW2__GPIO4_11 */
+							868 0x80000000	/* MX53_PAD_PATA_DA_0__GPIO7_6 */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 53fbc000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1_1>;
 				status = "okay";
 			};
 
 			uart2: serial at 53fc0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2_1>;
 				status = "okay";
 			};
 		};
 
 		aips at 60000000 {	/* AIPS2 */
 			i2c at 63fc4000 { /* I2C2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c2_1>;
 				status = "okay";
 
 				codec: sgtl5000 at 0a {
@@ -112,6 +142,8 @@
 			};
 
 			i2c at 63fc8000 { /* I2C1 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c1_1>;
 				status = "okay";
 
 				accelerometer: mma8450 at 1c {
@@ -131,6 +163,8 @@
 			};
 
 			ethernet at 63fec000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_fec_1>;
 				phy-mode = "rmii";
 				phy-reset-gpios = <&gpio7 6 0>;
 				status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e91cbc0..a8df8a4 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -251,6 +251,19 @@
 					};
 				};
 
+				esdhc2 {
+					pinctrl_esdhc2_1: esdhc2grp-1 {
+						fsl,pins = <
+							1038 0x1d5	/* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+							1032 0x1d5	/* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+							1062 0x1d5	/* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+							1056 0x1d5	/* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+							1050 0x1d5	/* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+							1044 0x1d5	/* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+						>;
+					};
+				};
+
 				esdhc3 {
 					pinctrl_esdhc3_1: esdhc3grp-1 {
 						fsl,pins = <
@@ -301,6 +314,26 @@
 						>;
 					};
 				};
+
+				uart2 {
+					pinctrl_uart2_1: uart2grp-1 {
+						fsl,pins = <
+							841 0x1c5	/* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+							836 0x1c5	/* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+						>;
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3_1: uart3grp-1 {
+						fsl,pins = <
+							884 0x1c5	/* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+							888 0x1c5	/* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+							875 0x1c5	/* MX53_PAD_PATA_DA_1__UART3_CTS */
+							880 0x1c5	/* MX53_PAD_PATA_DA_2__UART3_RTS */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 53fbc000 {
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:34 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:34 +0800
Subject: [PATCH 14/17] ARM: imx53: support device tree boot only
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-15-git-send-email-shawn.guo@linaro.org>

With device tree kernel provides the equal support as those imx53 board
files, it's time to remove the board files and get imx53 support device
tree only.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/configs/imx_v6_v7_defconfig           |    2 +-
 arch/arm/mach-imx/Kconfig                      |   79 +-----
 arch/arm/mach-imx/Makefile                     |    6 +-
 arch/arm/mach-imx/Makefile.boot                |    8 +-
 arch/arm/mach-imx/{imx53-dt.c => mach-imx53.c} |    0
 arch/arm/mach-imx/mach-mx53_ard.c              |  272 --------------------
 arch/arm/mach-imx/mach-mx53_evk.c              |  179 -------------
 arch/arm/mach-imx/mach-mx53_loco.c             |  321 ------------------------
 arch/arm/mach-imx/mach-mx53_smd.c              |  168 -------------
 9 files changed, 18 insertions(+), 1017 deletions(-)
 rename arch/arm/mach-imx/{imx53-dt.c => mach-imx53.c} (100%)
 delete mode 100644 arch/arm/mach-imx/mach-mx53_ard.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_evk.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_loco.c
 delete mode 100644 arch/arm/mach-imx/mach-mx53_smd.c

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 81817d0..8e865c0 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,7 +32,7 @@ CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_IMX53_DT=y
+CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1afdc67..374fcc2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -102,15 +102,6 @@ config	SOC_IMX51
 	select ARCH_MX5
 	select ARCH_MX51
 
-config	SOC_IMX53
-	bool
-	select SOC_IMX5
-	select ARCH_MX5
-	select ARCH_MX53
-	select HAVE_CAN_FLEXCAN if CAN
-	select PINCTRL
-	select PINCTRL_IMX53
-
 if ARCH_IMX_V4_V5
 
 comment "MX1 platforms:"
@@ -738,69 +729,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-comment "i.MX53 machines:"
-
-config MACH_IMX53_DT
-	bool "Support i.MX53 platforms from device tree"
-	select SOC_IMX53
-	select MACH_MX53_ARD
-	select MACH_MX53_EVK
-	select MACH_MX53_LOCO
-	select MACH_MX53_SMD
-	help
-	  Include support for Freescale i.MX53 based platforms
-	  using the device tree for discovery
-
-config MACH_MX53_EVK
-	bool "Support MX53 EVK platforms"
-	select SOC_IMX53
-	select IMX_HAVE_PLATFORM_IMX2_WDT
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_IMX_I2C
-	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-	select IMX_HAVE_PLATFORM_SPI_IMX
-	select LEDS_GPIO_REGISTER
-	help
-	  Include support for MX53 EVK platform. This includes specific
-	  configurations for the board and its peripherals.
-
-config MACH_MX53_SMD
-	bool "Support MX53 SMD platforms"
-	select SOC_IMX53
-	select IMX_HAVE_PLATFORM_IMX2_WDT
-	select IMX_HAVE_PLATFORM_IMX_I2C
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-	help
-	  Include support for MX53 SMD platform. This includes specific
-	  configurations for the board and its peripherals.
+comment "Device tree only"
 
-config MACH_MX53_LOCO
-	bool "Support MX53 LOCO platforms"
-	select SOC_IMX53
-	select IMX_HAVE_PLATFORM_IMX2_WDT
-	select IMX_HAVE_PLATFORM_IMX_I2C
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-	select IMX_HAVE_PLATFORM_GPIO_KEYS
-	select LEDS_GPIO_REGISTER
-	help
-	  Include support for MX53 LOCO platform. This includes specific
-	  configurations for the board and its peripherals.
+config	SOC_IMX53
+	bool "i.MX53 support"
+	select SOC_IMX5
+	select ARCH_MX5
+	select ARCH_MX53
+	select HAVE_CAN_FLEXCAN if CAN
+	select PINCTRL
+	select PINCTRL_IMX53
 
-config MACH_MX53_ARD
-	bool "Support MX53 ARD platforms"
-	select SOC_IMX53
-	select IMX_HAVE_PLATFORM_IMX2_WDT
-	select IMX_HAVE_PLATFORM_IMX_I2C
-	select IMX_HAVE_PLATFORM_IMX_UART
-	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-	select IMX_HAVE_PLATFORM_GPIO_KEYS
 	help
-	  Include support for MX53 ARD platform. This includes specific
-	  configurations for the board and its peripherals.
-
-comment "i.MX6 family:"
+	  This enables support for Freescale i.MX53 processor.
 
 config SOC_IMX6Q
 	bool "i.MX6 Quad support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 88b756c..58dc7c6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,13 +83,9 @@ endif
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf..c609676 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10800000
 
 dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
-dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
-			       imx53-qsb.dtb imx53-smd.dtb
+
+dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \
+			   imx53-evk.dtb \
+			   imx53-qsb.dtb \
+			   imx53-smd.dtb \
+
 dtb-$(CONFIG_SOC_IMX6Q)	+= imx6q-arm2.dtb \
 			   imx6q-sabrelite.dtb \
 			   imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
similarity index 100%
rename from arch/arm/mach-imx/imx53-dt.c
rename to arch/arm/mach-imx/mach-imx53.c
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65..0000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define ARD_ETHERNET_INT_B	IMX_GPIO_NR(2, 31)
-#define ARD_SD1_CD		IMX_GPIO_NR(1, 1)
-#define ARD_SD1_WP		IMX_GPIO_NR(1, 9)
-#define ARD_I2CPORTEXP_B	IMX_GPIO_NR(2, 3)
-#define ARD_VOLUMEDOWN		IMX_GPIO_NR(4, 0)
-#define ARD_HOME			IMX_GPIO_NR(5, 10)
-#define ARD_BACK			IMX_GPIO_NR(5, 11)
-#define ARD_PROG			IMX_GPIO_NR(5, 12)
-#define ARD_VOLUMEUP		IMX_GPIO_NR(5, 13)
-
-static iomux_v3_cfg_t mx53_ard_pads[] = {
-	/* UART1 */
-	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-	/* WEIM for CS1 */
-	MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
-	MX53_PAD_EIM_D16__EMI_WEIM_D_16,
-	MX53_PAD_EIM_D17__EMI_WEIM_D_17,
-	MX53_PAD_EIM_D18__EMI_WEIM_D_18,
-	MX53_PAD_EIM_D19__EMI_WEIM_D_19,
-	MX53_PAD_EIM_D20__EMI_WEIM_D_20,
-	MX53_PAD_EIM_D21__EMI_WEIM_D_21,
-	MX53_PAD_EIM_D22__EMI_WEIM_D_22,
-	MX53_PAD_EIM_D23__EMI_WEIM_D_23,
-	MX53_PAD_EIM_D24__EMI_WEIM_D_24,
-	MX53_PAD_EIM_D25__EMI_WEIM_D_25,
-	MX53_PAD_EIM_D26__EMI_WEIM_D_26,
-	MX53_PAD_EIM_D27__EMI_WEIM_D_27,
-	MX53_PAD_EIM_D28__EMI_WEIM_D_28,
-	MX53_PAD_EIM_D29__EMI_WEIM_D_29,
-	MX53_PAD_EIM_D30__EMI_WEIM_D_30,
-	MX53_PAD_EIM_D31__EMI_WEIM_D_31,
-	MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
-	MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
-	MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
-	MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
-	MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
-	MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
-	MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
-	MX53_PAD_EIM_OE__EMI_WEIM_OE,
-	MX53_PAD_EIM_RW__EMI_WEIM_RW,
-	MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
-	/* SDHC1 */
-	MX53_PAD_SD1_CMD__ESDHC1_CMD,
-	MX53_PAD_SD1_CLK__ESDHC1_CLK,
-	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-	MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
-	MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
-	MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
-	MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
-	MX53_PAD_GPIO_1__GPIO1_1,
-	MX53_PAD_GPIO_9__GPIO1_9,
-	/* I2C2 */
-	MX53_PAD_EIM_EB2__I2C2_SCL,
-	MX53_PAD_KEY_ROW3__I2C2_SDA,
-	/* I2C3 */
-	MX53_PAD_GPIO_3__I2C3_SCL,
-	MX53_PAD_GPIO_16__I2C3_SDA,
-	/* GPIO */
-	MX53_PAD_DISP0_DAT16__GPIO5_10,	/* home */
-	MX53_PAD_DISP0_DAT17__GPIO5_11,	/* back */
-	MX53_PAD_DISP0_DAT18__GPIO5_12,	/* prog */
-	MX53_PAD_DISP0_DAT19__GPIO5_13,	/* vol up */
-	MX53_PAD_GPIO_10__GPIO4_0,		/* vol down */
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)	\
-{							\
-	.gpio		= gpio_num,				\
-	.type		= EV_KEY,				\
-	.code		= ev_code,				\
-	.active_low	= act_low,				\
-	.desc		= "btn " descr,			\
-	.wakeup		= wake,					\
-}
-
-static struct gpio_keys_button ard_buttons[] = {
-	GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
-	GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
-	GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
-	GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
-	GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data ard_button_data __initconst = {
-	.buttons        = ard_buttons,
-	.nbuttons       = ARRAY_SIZE(ard_buttons),
-};
-
-static struct resource ard_smsc911x_resources[] = {
-	{
-		.start = MX53_CS1_64MB_BASE_ADDR,
-		.end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		/* irq number is run-time assigned */
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct smsc911x_platform_config ard_smsc911x_config = {
-	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags = SMSC911X_USE_32BIT,
-};
-
-static struct platform_device ard_smsc_lan9220_device = {
-	.name = "smsc911x",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(ard_smsc911x_resources),
-	.resource = ard_smsc911x_resources,
-	.dev = {
-		.platform_data = &ard_smsc911x_config,
-	},
-};
-
-static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
-	.cd_gpio = ARD_SD1_CD,
-	.wp_gpio = ARD_SD1_WP,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c2_data = {
-	.bitrate = 50000,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c3_data = {
-	.bitrate = 400000,
-};
-
-static void __init mx53_ard_io_init(void)
-{
-	gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
-	gpio_direction_input(ARD_ETHERNET_INT_B);
-
-	gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
-	gpio_direction_output(ARD_I2CPORTEXP_B, 1);
-}
-
-/* Config CS1 settings for ethernet controller */
-static int weim_cs_config(void)
-{
-	u32 reg;
-	void __iomem *weim_base, *iomuxc_base;
-
-	weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
-	if (!weim_base)
-		return -ENOMEM;
-
-	iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
-	if (!iomuxc_base) {
-		iounmap(weim_base);
-		return -ENOMEM;
-	}
-
-	/* CS1 timings for LAN9220 */
-	writel(0x20001, (weim_base + 0x18));
-	writel(0x0, (weim_base + 0x1C));
-	writel(0x16000202, (weim_base + 0x20));
-	writel(0x00000002, (weim_base + 0x24));
-	writel(0x16002082, (weim_base + 0x28));
-	writel(0x00000000, (weim_base + 0x2C));
-	writel(0x00000000, (weim_base + 0x90));
-
-	/* specify 64 MB on CS1 and CS0 on GPR1 */
-	reg = readl(iomuxc_base + 0x4);
-	reg &= ~0x3F;
-	reg |= 0x1B;
-	writel(reg, (iomuxc_base + 0x4));
-
-	iounmap(iomuxc_base);
-	iounmap(weim_base);
-
-	return 0;
-}
-
-static struct regulator_consumer_supply dummy_supplies[] = {
-	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-	REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-void __init imx53_ard_common_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-					 ARRAY_SIZE(mx53_ard_pads));
-	weim_cs_config();
-}
-
-static struct platform_device *devices[] __initdata = {
-	&ard_smsc_lan9220_device,
-};
-
-static void __init mx53_ard_board_init(void)
-{
-	imx53_soc_init();
-	imx53_add_imx_uart(0, NULL);
-
-	imx53_ard_common_init();
-	mx53_ard_io_init();
-	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-	ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
-	ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-	imx53_add_imx2_wdt(0);
-	imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
-	imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
-	imx_add_gpio_keys(&ard_button_data);
-	imx53_add_ahci_imx();
-}
-
-static void __init mx53_ard_timer_init(void)
-{
-	mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_ard_timer = {
-	.init	= mx53_ard_timer_init,
-};
-
-MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
-	.map_io = mx53_map_io,
-	.init_early = imx53_init_early,
-	.init_irq = mx53_init_irq,
-	.handle_irq = imx53_handle_irq,
-	.timer = &mx53_ard_timer,
-	.init_machine = mx53_ard_board_init,
-	.init_late	= imx53_init_late,
-	.restart	= mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe219..0000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Yong Shen. <Yong.Shen at linaro.org>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/iomux-mx53.h>
-
-#define MX53_EVK_FEC_PHY_RST	IMX_GPIO_NR(7, 6)
-#define EVK_ECSPI1_CS0		IMX_GPIO_NR(2, 30)
-#define EVK_ECSPI1_CS1		IMX_GPIO_NR(3, 19)
-#define MX53EVK_LED		IMX_GPIO_NR(7, 7)
-
-#include "devices-imx53.h"
-
-static iomux_v3_cfg_t mx53_evk_pads[] = {
-	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-	MX53_PAD_PATA_DIOR__UART2_RTS,
-	MX53_PAD_PATA_INTRQ__UART2_CTS,
-
-	MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-	MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-
-	MX53_PAD_EIM_D16__ECSPI1_SCLK,
-	MX53_PAD_EIM_D17__ECSPI1_MISO,
-	MX53_PAD_EIM_D18__ECSPI1_MOSI,
-
-	/* ecspi chip select lines */
-	MX53_PAD_EIM_EB2__GPIO2_30,
-	MX53_PAD_EIM_D19__GPIO3_19,
-	/* LED */
-	MX53_PAD_PATA_DA_1__GPIO7_7,
-};
-
-static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct gpio_led mx53evk_leds[] __initconst = {
-	{
-		.name			= "green",
-		.default_trigger	= "heartbeat",
-		.gpio			= MX53EVK_LED,
-	},
-};
-
-static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
-	.leds		= mx53evk_leds,
-	.num_leds	= ARRAY_SIZE(mx53evk_leds),
-};
-
-static inline void mx53_evk_init_uart(void)
-{
-	imx53_add_imx_uart(0, NULL);
-	imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-	imx53_add_imx_uart(2, NULL);
-}
-
-static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
-	.bitrate = 100000,
-};
-
-static inline void mx53_evk_fec_reset(void)
-{
-	int ret;
-
-	/* reset FEC PHY */
-	ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
-							"fec-phy-reset");
-	if (ret) {
-		printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-		return;
-	}
-	msleep(1);
-	gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
-	{
-		.modalias = "mtd_dataflash",
-		.max_speed_hz = 25000000,
-		.bus_num = 0,
-		.chip_select = 1,
-		.mode = SPI_MODE_0,
-		.platform_data = NULL,
-	},
-};
-
-static int mx53_evk_spi_cs[] = {
-	EVK_ECSPI1_CS0,
-	EVK_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx53_evk_spi_data __initconst = {
-	.chipselect     = mx53_evk_spi_cs,
-	.num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
-};
-
-void __init imx53_evk_common_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-					 ARRAY_SIZE(mx53_evk_pads));
-}
-
-static void __init mx53_evk_board_init(void)
-{
-	imx53_soc_init();
-	imx53_evk_common_init();
-
-	mx53_evk_init_uart();
-	mx53_evk_fec_reset();
-	imx53_add_fec(&mx53_evk_fec_pdata);
-
-	imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
-	imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
-
-	imx53_add_sdhci_esdhc_imx(0, NULL);
-	imx53_add_sdhci_esdhc_imx(1, NULL);
-
-	spi_register_board_info(mx53_evk_spi_board_info,
-		ARRAY_SIZE(mx53_evk_spi_board_info));
-	imx53_add_ecspi(0, &mx53_evk_spi_data);
-	imx53_add_imx2_wdt(0);
-	gpio_led_register_device(-1, &mx53evk_leds_data);
-}
-
-static void __init mx53_evk_timer_init(void)
-{
-	mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_evk_timer = {
-	.init	= mx53_evk_timer_init,
-};
-
-MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
-	.map_io = mx53_map_io,
-	.init_early = imx53_init_early,
-	.init_irq = mx53_init_irq,
-	.handle_irq = imx53_handle_irq,
-	.timer = &mx53_evk_timer,
-	.init_machine = mx53_evk_board_init,
-	.init_late	= imx53_init_late,
-	.restart	= mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c..0000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define MX53_LOCO_POWER			IMX_GPIO_NR(1, 8)
-#define MX53_LOCO_UI1			IMX_GPIO_NR(2, 14)
-#define MX53_LOCO_UI2			IMX_GPIO_NR(2, 15)
-#define LOCO_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
-#define LOCO_LED			IMX_GPIO_NR(7, 7)
-#define LOCO_SD3_CD			IMX_GPIO_NR(3, 11)
-#define LOCO_SD3_WP			IMX_GPIO_NR(3, 12)
-#define LOCO_SD1_CD			IMX_GPIO_NR(3, 13)
-#define LOCO_ACCEL_EN			IMX_GPIO_NR(6, 14)
-
-static iomux_v3_cfg_t mx53_loco_pads[] = {
-	/* FEC */
-	MX53_PAD_FEC_MDC__FEC_MDC,
-	MX53_PAD_FEC_MDIO__FEC_MDIO,
-	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-	MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-	MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-	MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-	MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-	/* FEC_nRST */
-	MX53_PAD_PATA_DA_0__GPIO7_6,
-	/* FEC_nINT */
-	MX53_PAD_PATA_DATA4__GPIO2_4,
-	/* AUDMUX5 */
-	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
-	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
-	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
-	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
-	/* I2C1 */
-	MX53_PAD_CSI0_DAT8__I2C1_SDA,
-	MX53_PAD_CSI0_DAT9__I2C1_SCL,
-	MX53_PAD_NANDF_CS1__GPIO6_14,	/* Accelerometer Enable */
-	/* I2C2 */
-	MX53_PAD_KEY_COL3__I2C2_SCL,
-	MX53_PAD_KEY_ROW3__I2C2_SDA,
-	/* SD1 */
-	MX53_PAD_SD1_CMD__ESDHC1_CMD,
-	MX53_PAD_SD1_CLK__ESDHC1_CLK,
-	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-	/* SD1_CD */
-	MX53_PAD_EIM_DA13__GPIO3_13,
-	/* SD3 */
-	MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-	MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-	MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-	MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-	MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-	MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-	MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-	MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-	MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-	MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-	/* SD3_CD */
-	MX53_PAD_EIM_DA11__GPIO3_11,
-	/* SD3_WP */
-	MX53_PAD_EIM_DA12__GPIO3_12,
-	/* VGA */
-	MX53_PAD_EIM_OE__IPU_DI1_PIN7,
-	MX53_PAD_EIM_RW__IPU_DI1_PIN8,
-	/* DISPLB */
-	MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
-	MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
-	MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
-	MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
-	/* DISP0_POWER_EN */
-	MX53_PAD_EIM_D24__GPIO3_24,
-	/* DISP0 DET INT */
-	MX53_PAD_EIM_D31__GPIO3_31,
-	/* LVDS */
-	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
-	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
-	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
-	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
-	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
-	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
-	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
-	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
-	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
-	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
-	/* I2C1 */
-	MX53_PAD_CSI0_DAT8__I2C1_SDA,
-	MX53_PAD_CSI0_DAT9__I2C1_SCL,
-	/* UART1 */
-	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-	/* CSI0 */
-	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-	/* DISPLAY */
-	MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-	MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-	MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-	MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-	MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-	MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-	MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-	MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-	MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-	MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-	MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-	MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-	MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-	MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-	MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-	MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-	MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-	MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-	MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-	MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-	MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-	MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-	MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-	MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-	MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-	MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-	MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-	MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-	/* Audio CLK*/
-	MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
-	/* PWM */
-	MX53_PAD_GPIO_1__PWM2_PWMO,
-	/* SPDIF */
-	MX53_PAD_GPIO_7__SPDIF_PLOCK,
-	MX53_PAD_GPIO_17__SPDIF_OUT1,
-	/* GPIO */
-	MX53_PAD_PATA_DA_1__GPIO7_7,		/* LED */
-	MX53_PAD_PATA_DA_2__GPIO7_8,
-	MX53_PAD_PATA_DATA5__GPIO2_5,
-	MX53_PAD_PATA_DATA6__GPIO2_6,
-	MX53_PAD_PATA_DATA14__GPIO2_14,
-	MX53_PAD_PATA_DATA15__GPIO2_15,
-	MX53_PAD_PATA_INTRQ__GPIO7_2,
-	MX53_PAD_EIM_WAIT__GPIO5_0,
-	MX53_PAD_NANDF_WP_B__GPIO6_9,
-	MX53_PAD_NANDF_RB0__GPIO6_10,
-	MX53_PAD_NANDF_CS1__GPIO6_14,
-	MX53_PAD_NANDF_CS2__GPIO6_15,
-	MX53_PAD_NANDF_CS3__GPIO6_16,
-	MX53_PAD_GPIO_5__GPIO1_5,
-	MX53_PAD_GPIO_16__GPIO7_11,
-	MX53_PAD_GPIO_8__GPIO1_8,
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)	\
-{								\
-	.gpio		= gpio_num,				\
-	.type		= EV_KEY,				\
-	.code		= ev_code,				\
-	.active_low	= act_low,				\
-	.desc		= "btn " descr,				\
-	.wakeup		= wake,					\
-}
-
-static struct gpio_keys_button loco_buttons[] = {
-	GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
-	GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
-	GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data loco_button_data __initconst = {
-	.buttons        = loco_buttons,
-	.nbuttons       = ARRAY_SIZE(loco_buttons),
-};
-
-static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
-	.cd_gpio = LOCO_SD1_CD,
-	.cd_type = ESDHC_CD_GPIO,
-	.wp_type = ESDHC_WP_NONE,
-};
-
-static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
-	.cd_gpio = LOCO_SD3_CD,
-	.wp_gpio = LOCO_SD3_WP,
-	.cd_type = ESDHC_CD_GPIO,
-	.wp_type = ESDHC_WP_GPIO,
-};
-
-static inline void mx53_loco_fec_reset(void)
-{
-	int ret;
-
-	/* reset FEC PHY */
-	ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
-	if (ret) {
-		printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-		return;
-	}
-	gpio_direction_output(LOCO_FEC_PHY_RST, 0);
-	msleep(1);
-	gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_loco_fec_data __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
-	.bitrate = 100000,
-};
-
-static const struct gpio_led mx53loco_leds[] __initconst = {
-	{
-		.name			= "green",
-		.default_trigger	= "heartbeat",
-		.gpio			= LOCO_LED,
-	},
-};
-
-static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
-	.leds		= mx53loco_leds,
-	.num_leds	= ARRAY_SIZE(mx53loco_leds),
-};
-
-void __init imx53_qsb_common_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-					 ARRAY_SIZE(mx53_loco_pads));
-}
-
-static struct i2c_board_info mx53loco_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("mma8450", 0x1C),
-	},
-};
-
-static void __init mx53_loco_board_init(void)
-{
-	int ret;
-	imx53_soc_init();
-	imx53_qsb_common_init();
-
-	imx53_add_imx_uart(0, NULL);
-	mx53_loco_fec_reset();
-	imx53_add_fec(&mx53_loco_fec_data);
-	imx53_add_imx2_wdt(0);
-
-	ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
-	if (ret)
-		pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
-
-	i2c_register_board_info(0, mx53loco_i2c_devices,
-				ARRAY_SIZE(mx53loco_i2c_devices));
-	imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
-	imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-	imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
-	imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
-	imx_add_gpio_keys(&loco_button_data);
-	gpio_led_register_device(-1, &mx53loco_leds_data);
-	imx53_add_ahci_imx();
-}
-
-static void __init mx53_loco_timer_init(void)
-{
-	mx53_clocks_init(32768, 24000000, 0, 0);
-}
-
-static struct sys_timer mx53_loco_timer = {
-	.init	= mx53_loco_timer_init,
-};
-
-MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
-	.map_io = mx53_map_io,
-	.init_early = imx53_init_early,
-	.init_irq = mx53_init_irq,
-	.handle_irq = imx53_handle_irq,
-	.timer = &mx53_loco_timer,
-	.init_machine = mx53_loco_board_init,
-	.init_late	= imx53_init_late,
-	.restart	= mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6..0000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define SMD_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
-#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
-
-static iomux_v3_cfg_t mx53_smd_pads[] = {
-	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-
-	MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-	MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-	MX53_PAD_PATA_DA_1__UART3_CTS,
-	MX53_PAD_PATA_DA_2__UART3_RTS,
-	/* I2C1 */
-	MX53_PAD_CSI0_DAT8__I2C1_SDA,
-	MX53_PAD_CSI0_DAT9__I2C1_SCL,
-	/* SD1 */
-	MX53_PAD_SD1_CMD__ESDHC1_CMD,
-	MX53_PAD_SD1_CLK__ESDHC1_CLK,
-	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-	/* SD2 */
-	MX53_PAD_SD2_CMD__ESDHC2_CMD,
-	MX53_PAD_SD2_CLK__ESDHC2_CLK,
-	MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
-	MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
-	MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
-	MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
-	/* SD3 */
-	MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-	MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-	MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-	MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-	MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-	MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-	MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-	MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-	MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-	MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-
-static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_smd_init_uart(void)
-{
-	imx53_add_imx_uart(0, NULL);
-	imx53_add_imx_uart(1, NULL);
-	imx53_add_imx_uart(2, &mx53_smd_uart_data);
-}
-
-static inline void mx53_smd_fec_reset(void)
-{
-	int ret;
-
-	/* reset FEC PHY */
-	ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
-	if (ret) {
-		printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-		return;
-	}
-	gpio_direction_output(SMD_FEC_PHY_RST, 0);
-	msleep(1);
-	gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_smd_fec_data __initconst = {
-	.phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
-	.bitrate = 100000,
-};
-
-static inline void mx53_smd_ahci_pwr_on(void)
-{
-	int ret;
-
-	/* Enable SATA PWR */
-	ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
-			GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
-	if (ret) {
-		pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
-		return;
-	}
-}
-
-void __init imx53_smd_common_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-					 ARRAY_SIZE(mx53_smd_pads));
-}
-
-static void __init mx53_smd_board_init(void)
-{
-	imx53_soc_init();
-	imx53_smd_common_init();
-
-	mx53_smd_init_uart();
-	mx53_smd_fec_reset();
-	imx53_add_fec(&mx53_smd_fec_data);
-	imx53_add_imx2_wdt(0);
-	imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
-	imx53_add_sdhci_esdhc_imx(0, NULL);
-	imx53_add_sdhci_esdhc_imx(1, NULL);
-	imx53_add_sdhci_esdhc_imx(2, NULL);
-	mx53_smd_ahci_pwr_on();
-	imx53_add_ahci_imx();
-}
-
-static void __init mx53_smd_timer_init(void)
-{
-	mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_smd_timer = {
-	.init	= mx53_smd_timer_init,
-};
-
-MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
-	.map_io = mx53_map_io,
-	.init_early = imx53_init_early,
-	.init_irq = mx53_init_irq,
-	.handle_irq = imx53_handle_irq,
-	.timer = &mx53_smd_timer,
-	.init_machine = mx53_smd_board_init,
-	.init_late	= imx53_init_late,
-	.restart	= mxc_restart,
-MACHINE_END
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:36 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:36 +0800
Subject: [PATCH 16/17] ARM: dts: imx51-babbage: add pinctrl settings
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-17-git-send-email-shawn.guo@linaro.org>

Add pinctrl settings for the exsiting devices in imx51-babbage.dts.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx51-babbage.dts |   36 ++++++++++-
 arch/arm/boot/dts/imx51.dtsi        |  116 +++++++++++++++++++++++++++++++++++
 2 files changed, 150 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index b2de32b..e010ae4 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
 		aips at 70000000 { /* aips-1 */
 			spba at 70000000 {
 				esdhc at 70004000 { /* ESDHC1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc1_1>;
 					fsl,cd-internal;
 					fsl,wp-internal;
 					status = "okay";
 				};
 
 				esdhc at 70008000 { /* ESDHC2 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_esdhc2_1>;
 					cd-gpios = <&gpio1 6 0>;
 					wp-gpios = <&gpio1 5 0>;
 					status = "okay";
 				};
 
 				uart3: serial at 7000c000 {
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_uart3_1>;
 					fsl,uart-has-rtscts;
 					status = "okay";
 				};
 
 				ecspi at 70010000 { /* ECSPI1 */
+					pinctrl-names = "default";
+					pinctrl-0 = <&pinctrl_ecspi1_1>;
 					fsl,spi-num-chipselects = <2>;
 					cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
 					status = "okay";
@@ -170,22 +178,42 @@
 			};
 
 			iomuxc at 73fa8000 {
-				compatible = "fsl,imx51-iomuxc-babbage";
-				reg = <0x73fa8000 0x4000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_hog>;
+
+				hog {
+					pinctrl_hog: hoggrp {
+						fsl,pins = <
+							694 0x85	/* MX51_PAD_GPIO1_0__SD1_CD */
+							697 0x85	/* MX51_PAD_GPIO1_1__SD1_WP */
+							737 0x85	/* MX51_PAD_GPIO1_5__GPIO1_5 */
+							740 0x85	/* MX51_PAD_GPIO1_6__GPIO1_6 */
+							121 0x5		/* MX51_PAD_EIM_A27__GPIO2_21 */
+							402 0x85	/* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+							405 0x85	/* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+						>;
+					};
+				};
 			};
 
 			uart1: serial at 73fbc000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart1_1>;
 				fsl,uart-has-rtscts;
 				status = "okay";
 			};
 
 			uart2: serial at 73fc0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_uart2_1>;
 				status = "okay";
 			};
 		};
 
 		aips at 80000000 {	/* aips-2 */
 			i2c at 83fc4000 { /* I2C2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c2_1>;
 				status = "okay";
 
 				sgtl5000: codec at 0a {
@@ -198,10 +226,14 @@
 			};
 
 			audmux at 83fd0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_audmux_1>;
 				status = "okay";
 			};
 
 			ethernet at 83fec000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_fec_1>;
 				phy-mode = "mii";
 				status = "okay";
 			};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 86ca287..58b0c05 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -179,6 +179,122 @@
 				status = "disabled";
 			};
 
+			iomuxc at 73fa8000 {
+				compatible = "fsl,imx51-iomuxc";
+				reg = <0x73fa8000 0x4000>;
+
+				audmux {
+					pinctrl_audmux_1: audmuxgrp-1 {
+						fsl,pins = <
+							384 0x80000000	/* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+							386 0x80000000	/* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+							389 0x80000000	/* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+							391 0x80000000	/* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+						>;
+					};
+				};
+
+				fec {
+					pinctrl_fec_1: fecgrp-1 {
+						fsl,pins = <
+							128 0x80000000	/* MX51_PAD_EIM_EB2__FEC_MDIO */
+							134 0x80000000	/* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+							146 0x80000000	/* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+							152 0x80000000	/* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+							158 0x80000000	/* MX51_PAD_EIM_CS4__FEC_RX_ER */
+							165 0x80000000	/* MX51_PAD_EIM_CS5__FEC_CRS */
+							206 0x80000000	/* MX51_PAD_NANDF_RB2__FEC_COL */
+							213 0x80000000	/* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+							293 0x80000000	/* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+							298 0x80000000	/* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+							225 0x80000000	/* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+							231 0x80000000	/* MX51_PAD_NANDF_CS3__FEC_MDC */
+							237 0x80000000	/* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+							243 0x80000000	/* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+							250 0x80000000	/* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+							255 0x80000000	/* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+							260 0x80000000	/* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+						>;
+					};
+				};
+
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							398 0x185	/* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+							394 0x185	/* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+							409 0x185	/* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+						>;
+					};
+				};
+
+				esdhc1 {
+					pinctrl_esdhc1_1: esdhc1grp-1 {
+						fsl,pins = <
+							666 0x400020d5	/* MX51_PAD_SD1_CMD__SD1_CMD */
+							669 0x20d5	/* MX51_PAD_SD1_CLK__SD1_CLK */
+							672 0x20d5	/* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+							678 0x20d5	/* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+							684 0x20d5	/* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+							691 0x20d5	/* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+						>;
+					};
+				};
+
+				esdhc2 {
+					pinctrl_esdhc2_1: esdhc2grp-1 {
+						fsl,pins = <
+							704 0x400020d5	/* MX51_PAD_SD2_CMD__SD2_CMD */
+							707 0x20d5	/* MX51_PAD_SD2_CLK__SD2_CLK */
+							710 0x20d5	/* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+							712 0x20d5	/* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+							715 0x20d5	/* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+							719 0x20d5	/* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+						>;
+					};
+				};
+
+				i2c2 {
+					pinctrl_i2c2_1: i2c2grp-1 {
+						fsl,pins = <
+							449 0x400001ed	/* MX51_PAD_KEY_COL4__I2C2_SCL */
+							454 0x400001ed	/* MX51_PAD_KEY_COL5__I2C2_SDA */
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							413 0x1c5	/* MX51_PAD_UART1_RXD__UART1_RXD */
+							416 0x1c5	/* MX51_PAD_UART1_TXD__UART1_TXD */
+							418 0x1c5	/* MX51_PAD_UART1_RTS__UART1_RTS */
+							420 0x1c5	/* MX51_PAD_UART1_CTS__UART1_CTS */
+						>;
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2_1: uart2grp-1 {
+						fsl,pins = <
+							423 0x1c5	/* MX51_PAD_UART2_RXD__UART2_RXD */
+							426 0x1c5	/* MX51_PAD_UART2_TXD__UART2_TXD */
+						>;
+					};
+				};
+
+				uart3 {
+					pinctrl_uart3_1: uart3grp-1 {
+						fsl,pins = <
+							54 0x1c5	/* MX51_PAD_EIM_D25__UART3_RXD */
+							59 0x1c5	/* MX51_PAD_EIM_D26__UART3_TXD */
+							65 0x1c5	/* MX51_PAD_EIM_D27__UART3_RTS */
+							49 0x1c5	/* MX51_PAD_EIM_D24__UART3_CTS */
+						>;
+					};
+				};
+			};
+
 			uart1: serial at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:32 +0800
Subject: [PATCH 12/17] ARM: imx53: build in pinctrl support
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-13-git-send-email-shawn.guo@linaro.org>

As all imx53 boards booting from device tree have pinctrl set up in dts,
it's time to remove the dummy pinctrl state and build in the real imx53
pinctrl support.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig    |    2 ++
 arch/arm/mach-imx/imx53-dt.c |    3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e4aa082..1afdc67 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -108,6 +108,8 @@ config	SOC_IMX53
 	select ARCH_MX5
 	select ARCH_MX53
 	select HAVE_CAN_FLEXCAN if CAN
+	select PINCTRL
+	select PINCTRL_IMX53
 
 if ARCH_IMX_V4_V5
 
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 1b7a2fc..7f47391 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -17,7 +17,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -78,8 +77,6 @@ static void __init imx53_dt_init(void)
 	const struct of_device_id *of_id;
 	void (*func)(void);
 
-	pinctrl_provide_dummies();
-
 	node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
 	if (node) {
 		of_id = of_match_node(imx53_iomuxc_of_match, node);
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:37 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:37 +0800
Subject: [PATCH 17/17] ARM: imx51: build in pinctrl support
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-18-git-send-email-shawn.guo@linaro.org>

With the imx51 DT board having pinctrl setup define in device tree,
it's time to remove dummy pinctrl state and build in the real imx51
pinctrl support.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig    |    2 ++
 arch/arm/mach-imx/imx51-dt.c |    3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 374fcc2..7ca5fe4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,6 +101,8 @@ config	SOC_IMX51
 	select SOC_IMX5
 	select ARCH_MX5
 	select ARCH_MX51
+	select PINCTRL
+	select PINCTRL_IMX51
 
 if ARCH_IMX_V4_V5
 
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe..f5261e6 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -55,8 +54,6 @@ static void __init imx51_dt_init(void)
 	const struct of_device_id *of_id;
 	void (*func)(void);
 
-	pinctrl_provide_dummies();
-
 	node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
 	if (node) {
 		of_id = of_match_node(imx51_iomuxc_of_match, node);
-- 
1.7.5.4




From shawn.guo at linaro.org  Mon Aug 13 09:05:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:05:33 +0800
Subject: [PATCH 13/17] ARM: imx53: decouple device tree boot from board files
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-14-git-send-email-shawn.guo@linaro.org>

Now, imx53 device tree kernel calls pinctrl to set up pins.  The
functions used to hook up non-DT pin setup is not needed for DT boot
any more.  Remove them from DT image.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/imx53-dt.c            |   20 --------------------
 arch/arm/plat-mxc/include/mach/common.h |    4 ----
 2 files changed, 0 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 7f47391..f577b5d 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -50,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
-	{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
-	{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
-	{ .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
-	{ .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
-	{ /* sentinel */ }
-};
-
 static void __init imx53_qsb_init(void)
 {
 	struct clk *clk;
@@ -73,18 +65,6 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
-	struct device_node *node;
-	const struct of_device_id *of_id;
-	void (*func)(void);
-
-	node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
-	if (node) {
-		of_id = of_match_node(imx53_iomuxc_of_match, node);
-		func = of_id->data;
-		func();
-		of_node_put(node);
-	}
-
 	if (of_machine_is_compatible("fsl,imx53-qsb"))
 		imx53_qsb_init();
 
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e97..96fa702 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -138,10 +138,6 @@ extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
 extern void imx51_babbage_common_init(void);
-extern void imx53_ard_common_init(void);
-extern void imx53_evk_common_init(void);
-extern void imx53_qsb_common_init(void);
-extern void imx53_smd_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_clock_map_io(void);
 
-- 
1.7.5.4




From arnd at arndb.de  Mon Aug 13 09:12:15 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 13 Aug 2012 13:12:15 +0000
Subject: [PATCH v2 1/4] dmaengine: mmp-pdma support
In-Reply-To: <1344395701-30888-2-git-send-email-zhangfei.gao@marvell.com>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
 <1344395701-30888-2-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <201208131312.15180.arnd@arndb.de>

On Wednesday 08 August 2012, Zhangfei Gao wrote:
> 1. virtual channel vs. physical channel
> Virtual channel is managed by dmaengine
> Physical channel handling resource, such as irq
> Physical channel is alloced dynamically as descending priority,
> freed immediately when irq done.
> The availble highest priority physically channel will alwayes be alloced
> 
> Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel
> 
> 2. list: running list & pending list
> submit: desc list -> pending list
> issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
> irq: free running list (IDLE)
>      check pendlist -> pending list -> running list; free pending list (RUN)
> 
> 3. irq:
> Each list generate one irq, calling callback
> One list may contain several desc chain, in such case, make sure only the last desc list generate irq.
> 
> 4. async
> Submit will add desc chain to pending list, which can be multi-called
> If multi desc chain is submitted, only the last desc would generate irq -> call back
> If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
> If RUN, irq will start pending list
> 
> 5. test
> 5.1 pxa3xx_nand on pxa910
> 5.2 insmod dmatest.ko (threads_per_chan=y)
> By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel
> 
> Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>

Looks all good to, the entire series, except one very small point:

> +Required properties:
> +- compatible: Should be "marvell,pdma-1.0"
> +- reg: Should contain DMA registers location and length.
> +- interrupts: Either contain all of the per-channel DMA interrupts
> +               or one irq for pdma device
> +- dma-channels: Number of DMA channels supported by the controller.

I think the last one should be "#dma-channels", not "dma-channels", since it's
counting the channels. I think we use the "#" version in the preliminary binding
for the generic dma channel assignment in DT.

	Arnd


From shawn.guo at linaro.org  Mon Aug 13 09:17:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 21:17:43 +0800
Subject: [PATCH 18/18] ARM: imx51: decouple device tree boot from board files
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863863-9094-1-git-send-email-shawn.guo@linaro.org>

Now, imx51 device tree kernel calls pinctrl to set up pins.  The
function used to hook up non-DT pin setup is not needed for DT boot
any more.  Remove it from DT image.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/imx51-dt.c            |   17 -----------------
 arch/arm/plat-mxc/include/mach/common.h |    1 -
 2 files changed, 0 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index f5261e6..bcf7f69 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -43,25 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
-	{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
-	{ /* sentinel */ }
-};
-
 static void __init imx51_dt_init(void)
 {
-	struct device_node *node;
-	const struct of_device_id *of_id;
-	void (*func)(void);
-
-	node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
-	if (node) {
-		of_id = of_match_node(imx51_iomuxc_of_match, node);
-		func = of_id->data;
-		func();
-		of_node_put(node);
-	}
-
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     imx51_auxdata_lookup, NULL);
 }
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 0932fc6..28ba09f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -136,7 +136,6 @@ extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
-extern void imx51_babbage_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_clock_map_io(void);
 
-- 
1.7.5.4




From linus.walleij at linaro.org  Mon Aug 13 09:57:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 Aug 2012 15:57:49 +0200
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <CACRpkdZGG8ZysHe=JAdoyrfaome+cFDNLkco3uukQVOThbf8Tg@mail.gmail.com>

On Thu, Aug 9, 2012 at 6:23 PM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

> This is mostly cut'n'paste from the imx51 pinctrl driver. The data was
> generated using sed and awk on
> arch/arm/plat-mxc/include/mach/iomux-mx35.h.

OK, applied this version with the small doc fixup requested by Uwe, and
added Shawn's ACK too.

Yours,
Linus Walleij


From a.p.zijlstra at chello.nl  Mon Aug 13 10:05:17 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Mon, 13 Aug 2012 16:05:17 +0200
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <alpine.LFD.2.02.1208130931530.5231@xanadu.home>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <1344845704.31459.11.camel@twins>
 <alpine.LFD.2.02.1208130931530.5231@xanadu.home>
Message-ID: <1344866717.31459.32.camel@twins>

On Mon, 2012-08-13 at 09:35 -0400, Nicolas Pitre wrote:
> Date: Fri, 10 Aug 2012 15:22:09 +0100
> From: Will Deacon <will.deacon at arm.com>
> Subject: [PATCH] mutex: place lock in contended state after fastpath_lock failure
> 
> ARM recently moved to asm-generic/mutex-xchg.h for its mutex
> implementation after the previous implementation was found to be missing
> some crucial memory barriers. However, this has revealed some problems
> running hackbench on SMP platforms due to the way in which the
> MUTEX_SPIN_ON_OWNER code operates.
> 
> The symptoms are that a bunch of hackbench tasks are left waiting on an
> unlocked mutex and therefore never get woken up to claim it. This boils
> down to the following sequence of events:
> 
>         Task A        Task B        Task C        Lock value
> 0                                                     1
> 1       lock()                                        0
> 2                     lock()                          0
> 3                     spin(A)                         0
> 4       unlock()                                      1
> 5                                   lock()            0
> 6                     cmpxchg(1,0)                    0
> 7                     contended()                    -1
> 8       lock()                                        0
> 9       spin(C)                                       0
> 10                                  unlock()          1
> 11      cmpxchg(1,0)                                  0
> 12      unlock()                                      1
> 
> At this point, the lock is unlocked, but Task B is in an uninterruptible
> sleep with nobody to wake it up.
> 
> This patch fixes the problem by ensuring we put the lock into the
> contended state if we fail to acquire it on the fastpath, ensuring that
> any blocked waiters are woken up when the mutex is released.
> 
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Chris Mason <chris.mason at fusionio.com>
> Cc: Ingo Molnar <mingo at elte.hu>
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Reviewed-by: Nicolas Pitre <nico at linaro.org> 

Acked-by: Peter Zijlstra <a.p.zijlstra at chello.nl>


Will you carry this through the ARM tree or do you want me/Ingo to take
it?




From shawn.guo at linaro.org  Mon Aug 13 10:08:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 22:08:05 +0800
Subject: [PATCH 00/10 V3] MXS SPI driver
In-Reply-To: <20120813125158.GE13446@opensource.wolfsonmicro.com>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
 <20120813125158.GE13446@opensource.wolfsonmicro.com>
Message-ID: <20120813140803.GB6407@S2101-09.ap.freescale.net>

On Mon, Aug 13, 2012 at 01:51:58PM +0100, Mark Brown wrote:
> Do we have any ETA for review from the MMC side?  I'd like to get these
> patches out of my queue one way or another, it seems like for the simple
> code motion bits at least we should be easy enough to get out of the
> way.

For mxs-mmc part:

Reviewed-by: Shawn Guo <shawn.guo at linaro.org>

Chris,

Can you take a look at the series and give your ACK to bless it go via
SPI tree?

-- 
Regards,
Shawn



From linus.walleij at linaro.org  Mon Aug 13 10:11:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 Aug 2012 16:11:32 +0200
Subject: [PATCH 6/6] ARM: dts: add pinctrl in PXA DT files
In-Reply-To: <5028CC25.5040707@gmail.com>
References: <1343458722-17127-1-git-send-email-haojian.zhuang@gmail.com>
 <1343458722-17127-7-git-send-email-haojian.zhuang@gmail.com>
 <201208060844.29333.arnd@arndb.de>
 <CACRpkdayqp0ptdURHtYWC6G5pk1rNaAiWZkc7bdhv2osY1MaHA@mail.gmail.com>
 <5023C923.3080808@gmail.com>
 <CACRpkda0443PF-SwNaiJCO9RmdCFqw1+OtLgTBoTfZzwnFjJ4w@mail.gmail.com>
 <5028CC25.5040707@gmail.com>
Message-ID: <CACRpkdY+zLKYEqrt8+gBM5QAFDaOjuw0ka5CTcbH5b7HfE10dA@mail.gmail.com>

On Mon, Aug 13, 2012 at 11:43 AM, Daniel Mack <zonque at gmail.com> wrote:
> On 10.08.2012 12:56, Linus Walleij wrote:

>> So the infrastructure I think already exists, but whereas all
>> current driver have their own config and mux (etc) parsing
>> code, pinconf-generic could provide something that would
>> be common for all driver using generic pin config.
>
> Exactly. And then the question is whether we want implicit behaviour.
> IOW - let dt_to_map_one_config() parse the generic bits and then call
> the driver specific augmentation code, if any.

Well if you make a patch I think we can see pretty clear
from the code what the best way of doing this will be.

Yours,
Linus Walleij


From will.deacon at arm.com  Mon Aug 13 10:11:57 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 15:11:57 +0100
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <1344866717.31459.32.camel@twins>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <1344845704.31459.11.camel@twins>
 <alpine.LFD.2.02.1208130931530.5231@xanadu.home>
 <1344866717.31459.32.camel@twins>
Message-ID: <20120813141156.GC20537@mudshark.cambridge.arm.com>

On Mon, Aug 13, 2012 at 03:05:17PM +0100, Peter Zijlstra wrote:
> Acked-by: Peter Zijlstra <a.p.zijlstra at chello.nl>

Thanks Peter.

> Will you carry this through the ARM tree or do you want me/Ingo to take
> it?

Please can you guys take it? The move to mutex-dec can go through the ARM
tree but it's probably best if you take the core change.

Cheers,

Will


From linus.walleij at linaro.org  Mon Aug 13 10:17:53 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 Aug 2012 16:17:53 +0200
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-5-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
Message-ID: <CACRpkdYicRVoXb2VPDvHV4PwUfzYW7-JRSLQZh-nTswWWh7kVQ@mail.gmail.com>

On Fri, Aug 10, 2012 at 7:36 PM, Will Deacon <will.deacon at arm.com> wrote:

> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
>
> The arm_pmu_type enumeration was initially introduced to identify
> different PMU types in the system, the usual one being that on the CPU
> (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
> the introduction of devicetree bindings for the CPU PMU, the enumeration
> is no longer required.
>
> This patch removes the enumeration and updates the various CPU PMU
> platform devices so that they no longer pass an .id field referring
> to identify the PMU type.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From shawn.guo at linaro.org  Mon Aug 13 10:18:52 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 22:18:52 +0800
Subject: [PATCH] pinctrl: imx51: fix .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSI
Message-ID: <1344867532-27068-1-git-send-email-shawn.guo@linaro.org>

The .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSI should be 0x7bc rather
than NO_PAD.  This error will cause SD2 probe failure.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
Hi Linus,

Please send this fix for -rc, so that my imx51 pinctrl series can get
a fixed base.

Regards,
Shawn

 drivers/pinctrl/pinctrl-imx51.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 689b3c8..9fd0216 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -974,7 +974,7 @@ static struct imx_pin_reg imx51_pin_regs[] = {
 	IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
 	IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
 	IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
-	IMX_PIN_REG(MX51_PAD_SD2_CMD, NO_PAD, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
+	IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
 	IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
 	IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
 	IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
-- 
1.7.5.4




From linus.walleij at linaro.org  Mon Aug 13 10:20:10 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 13 Aug 2012 16:20:10 +0200
Subject: [PATCH] pinctrl: imx51: fix .conf_reg of
 MX51_PAD_SD2_CMD__CSPI_MOSI
In-Reply-To: <1344867532-27068-1-git-send-email-shawn.guo@linaro.org>
References: <1344867532-27068-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZB_NvS+PVY8fGuJggK3FhE_--MuBYXVAVDDmsPBjcvGA@mail.gmail.com>

On Mon, Aug 13, 2012 at 4:18 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> The .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSI should be 0x7bc rather
> than NO_PAD.  This error will cause SD2 probe failure.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied to fixes.

Yours,
Linus Walleij


From peter.ujfalusi at ti.com  Mon Aug 13 10:22:41 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:41 +0300
Subject: [PATCH v2 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-3-git-send-email-peter.ujfalusi@ti.com>

On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
the FIFO for the audio stack.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index ebc801e..6e046e1 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -151,7 +151,10 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
 		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
 
-	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
+		/* The FIFO has 128 locations */
+		pdata->buffer_size = 0x80;
+	} else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
 		if (id == 2)
 			/* The FIFO has 1024 + 256 locations */
 			pdata->buffer_size = 0x500;
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:39 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:39 +0300
Subject: [PATCH v2 0/9] ARM/ASoC: OMAP McBSP device tree support
Message-ID: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v1:
- ICLK workaround for the sidetone module has been kept for legacy mode.

Intro mail ffrom v1 (updated):

in order to be able to add DT support for the McBSP driver which is used on all
OMAP platforms (OMAP1/2/3/4/5) I needed to make some cleanups to the stack:
- Removing callbacks used by the driver for
 - clock re-parenting (code moved to sound driver)
 - FSR/CLKR mux configuration (from now on it need to be done at board level)
   This mux is board specific and depends on the wiring.
- Replaced the cpu_is_omap* checks with future proof check.
- The FIFO was not enabled on OMAP2430 SoC

It has been tested on BeagleBoard (with legacy and DT boot).

The series changes McBSP related files mostly. It would be great if the whole
series could go via audio tree (if the patches are OK and it is fine by Tony).

For DT booted kernel on OMAP3 proper ICLK woraround need to be implemented. At
the moment I don't see this as a stopper since we can not properly boot OMAP3
devices (especially rx51 which is using the ST). Other OMAP revisions does not
have ST block so the missing workaround is not going to hurt them.
I'm working on a solution which can replace the current workaround with a
generic implementation to support DT and non DT booted kernels.

Regards,
Peter
---
Peter Ujfalusi (9):
  ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code to ASoC driver
  ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
  ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR signal source
  ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR signal muxing
  ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux configuration code
  ASoC: omap-mcbsp: Remove unused defines
  ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the code
  ARM: OMAP2+: McBSP: Do not create legacy devices when booting with DT
    data
  ASoC: omap-mcbsp: Add device tree bindings

 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 +++++++
 arch/arm/mach-omap2/board-am3517evm.c              |   13 ++
 arch/arm/mach-omap2/mcbsp.c                        |  126 +------------------
 arch/arm/plat-omap/include/plat/mcbsp.h            |    2 -
 sound/soc/omap/am3517evm.c                         |   20 +---
 sound/soc/omap/mcbsp.c                             |   54 ++++-----
 sound/soc/omap/mcbsp.h                             |    3 -
 sound/soc/omap/omap-mcbsp.c                        |  106 +++++++++++-----
 sound/soc/omap/omap-mcbsp.h                        |   20 ---
 9 files changed, 162 insertions(+), 227 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:40 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:40 +0300
Subject: [PATCH v2 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code
 to ASoC driver
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-2-git-send-email-peter.ujfalusi@ti.com>

Move the McBSP CLKS re-parenting code to ASoC driver from
arch/arm/mach-omap2.
The call fort the re-parenting has been already limited to OMAP2+ SoC in
the ASoC driver. There is no longer need to have callback function for it.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   40 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ++++++++++++++++++++----
 3 files changed, 26 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77..ebc801e 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -101,45 +101,6 @@ static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
 	return 0;
 }
 
-/* McBSP CLKS source switching function */
-static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-				   const char *src)
-{
-	struct clk *fck_src;
-	char *fck_src_name;
-	int r;
-
-	if (!strcmp(src, "clks_ext"))
-		fck_src_name = "pad_fck";
-	else if (!strcmp(src, "clks_fclk"))
-		fck_src_name = "prcm_fck";
-	else
-		return -EINVAL;
-
-	fck_src = clk_get(dev, fck_src_name);
-	if (IS_ERR_OR_NULL(fck_src)) {
-		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
-		       fck_src_name);
-		return -EINVAL;
-	}
-
-	pm_runtime_put_sync(dev);
-
-	r = clk_set_parent(clk, fck_src);
-	if (IS_ERR_VALUE(r)) {
-		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
-		       "clks", fck_src_name);
-		clk_put(fck_src);
-		return -EINVAL;
-	}
-
-	pm_runtime_get_sync(dev);
-
-	clk_put(fck_src);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -181,7 +142,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->reg_size = 4;
 		pdata->has_ccr = true;
 	}
-	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
 
 	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
 	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 1881412..0a7d5ca 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
 	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index d33c48b..d901fc0 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <plat/mcbsp.h>
 
@@ -726,19 +727,39 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 {
+	struct clk *fck_src;
 	const char *src;
+	int r;
 
 	if (fck_src_id == MCBSP_CLKS_PAD_SRC)
-		src = "clks_ext";
+		src = "pad_fck";
 	else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
-		src = "clks_fclk";
+		src = "prcm_fck";
 	else
 		return -EINVAL;
 
-	if (mcbsp->pdata->set_clk_src)
-		return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
-	else
+	fck_src = clk_get(mcbsp->dev, src);
+	if (IS_ERR_OR_NULL(fck_src)) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
 		return -EINVAL;
+	}
+
+	pm_runtime_put_sync(mcbsp->dev);
+
+	r = clk_set_parent(mcbsp->fclk, fck_src);
+	if (r) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
+			src);
+		clk_put(fck_src);
+		return r;
+	}
+
+	pm_runtime_get_sync(mcbsp->dev);
+
+	clk_put(fck_src);
+
+	return 0;
+
 }
 
 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:42 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:42 +0300
Subject: [PATCH v2 3/9] ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR
 signal source
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-4-git-send-email-peter.ujfalusi@ti.com>

am3517evm board uses McBSP1 for audio with 4pin configuration.
The CLKR/FSR signals need to be connected to CLKX/FSX pin of the SoC in
this case.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/board-am3517evm.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f6010..592812a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -264,6 +264,16 @@ static __init void am3517_evm_musb_init(void)
 	usb_musb_init(&musb_board_data);
 }
 
+static __init void am3517_evm_mcbsp1_init(void)
+{
+	u32 devconf0;
+
+	/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
+	devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
+	omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
+}
+
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -373,6 +383,9 @@ static void __init am3517_evm_init(void)
 	/* MUSB */
 	am3517_evm_musb_init();
 
+	/* McBSP1 */
+	am3517_evm_mcbsp1_init();
+
 	/* MMC init function */
 	omap_hsmmc_init(mmc);
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:44 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:44 +0300
Subject: [PATCH v2 5/9] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux
 configuration code
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-6-git-send-email-peter.ujfalusi@ti.com>

Remove the feature to configure the CLKR/FSR mux on McBSP port with 6pin
configuration.
When moving to devicetree these callback can no longer be used in a clean
way anymore.
If a board require to change the 6pin port to work in 4pin setup it needs
to set up the mux in the board file.
For OMAP2/3:
u32 devconf0;

/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);

For OMAP4:
u32 mcbsp_pad;

/* McBSP4 CLKR/FSR signal to be connected to CLKX/FSX pin */
mcbsp_pad = omap4_ctrl_pad_readl(OMAP2_CONTROL_DEVCONF0);
mcbsp_pad |=  ((1 << 31) | (1 << 30));
omap4_ctrl_pad_writel(mcbsp_pad, OMAP2_CONTROL_DEVCONF0);

In case when the kernel is booted with DT blob the pinctrl-single will be
provided as soon as it is enabled on the platform.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   77 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ------------
 sound/soc/omap/mcbsp.h                  |    3 -
 sound/soc/omap/omap-mcbsp.c             |   32 +------------
 sound/soc/omap/omap-mcbsp.h             |    4 --
 6 files changed, 3 insertions(+), 145 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 6e046e1..660e00b 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,8 +25,6 @@
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-#include "control.h"
-
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,73 +32,6 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP2_MCBSP1_CLKR_MASK;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP2_MCBSP1_CLKR_MASK;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP2_MCBSP1_FSR_MASK;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP2_MCBSP1_FSR_MASK;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-
-	return 0;
-}
-
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	/*
-	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
-	 * mux) is used */
-	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -143,14 +74,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->has_ccr = true;
 	}
 
-	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
-	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
-
-	/* On OMAP4 the McBSP4 port has 6 pin configuration */
-	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
-
 	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
 		/* The FIFO has 128 locations */
 		pdata->buffer_size = 0x80;
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 0a7d5ca..c78d90b 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
 /**
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index d901fc0..c870023 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -762,37 +762,6 @@ int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 
 }
 
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-{
-	const char *signal, *src;
-
-	if (!mcbsp->pdata->mux_signal)
-		return -EINVAL;
-
-	switch (mux) {
-	case CLKR_SRC_CLKR:
-		signal = "clkr";
-		src = "clkr";
-		break;
-	case CLKR_SRC_CLKX:
-		signal = "clkr";
-		src = "clkx";
-		break;
-	case FSR_SRC_FSR:
-		signal = "fsr";
-		src = "fsr";
-		break;
-	case FSR_SRC_FSX:
-		signal = "fsr";
-		src = "fsx";
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
-}
-
 #define max_thres(m)			(mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)		((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)					\
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index 262a615..49a6725 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -334,9 +334,6 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
 /* McBSP functional clock source changing function */
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
 
-/* McBSP signal muxing API */
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux);
-
 /* Sidetone specific API */
 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain);
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 1046083..5061594 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -516,21 +516,9 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 			return -EBUSY;
 	}
 
-	if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
-		mcbsp->in_freq = freq;
-		regs->srgr2	&= ~CLKSM;
-		regs->pcr0	&= ~SCLKME;
-	} else if (cpu_class_is_omap1()) {
-		/*
-		 * McBSP CLKR/FSR signal muxing functions are only available on
-		 * OMAP2 or newer versions
-		 */
-		return -EINVAL;
-	}
+	mcbsp->in_freq = freq;
+	regs->srgr2 &= ~CLKSM;
+	regs->pcr0 &= ~SCLKME;
 
 	switch (clk_id) {
 	case OMAP_MCBSP_SYSCLK_CLK:
@@ -558,20 +546,6 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 		regs->pcr0	|= SCLKME;
 		break;
-
-
-	case OMAP_MCBSP_CLKR_SRC_CLKR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
-		break;
-	case OMAP_MCBSP_CLKR_SRC_CLKX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
-		break;
 	default:
 		err = -ENODEV;
 	}
diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index f877b16..baebcee 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -32,10 +32,6 @@ enum omap_mcbsp_clksrg_clk {
 	OMAP_MCBSP_SYSCLK_CLK,		/* Internal ICLK */
 	OMAP_MCBSP_SYSCLK_CLKX_EXT,	/* External CLKX pin */
 	OMAP_MCBSP_SYSCLK_CLKR_EXT,	/* External CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKR,	/* CLKR from CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKX,	/* CLKR from CLKX pin */
-	OMAP_MCBSP_FSR_SRC_FSR,		/* FSR from FSR pin */
-	OMAP_MCBSP_FSR_SRC_FSX,		/* FSR from FSX pin */
 };
 
 /* McBSP dividers */
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:45 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:45 +0300
Subject: [PATCH v2 6/9] ASoC: omap-mcbsp: Remove unused defines
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-7-git-send-email-peter.ujfalusi@ti.com>

NUM_LINKS is no longer in use by the code.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/omap-mcbsp.h |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index baebcee..ba8386a 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -39,22 +39,6 @@ enum omap_mcbsp_div {
 	OMAP_MCBSP_CLKGDV,		/* Sample rate generator divider */
 };
 
-#if defined(CONFIG_SOC_OMAP2420)
-#define NUM_LINKS	2
-#endif
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-#undef  NUM_LINKS
-#define NUM_LINKS	3
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#undef  NUM_LINKS
-#define NUM_LINKS	4
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430)
-#undef  NUM_LINKS
-#define NUM_LINKS	5
-#endif
-
 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd);
 
 #endif
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:46 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:46 +0300
Subject: [PATCH v2 7/9] ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the
 code
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-8-git-send-email-peter.ujfalusi@ti.com>

We can use the has_ccr flag to replace the cpu_is_omap* checks.
This provides future proof implementation and we do not need to update the
code if new OMAP revision starts to use the McBSP driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/omap-mcbsp.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 5061594..b9770ee 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -398,12 +398,14 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	/* Generic McBSP register settings */
 	regs->spcr2	|= XINTM(3) | FREE;
 	regs->spcr1	|= RINTM(3);
-	/* RFIG and XFIG are not defined in 34xx */
-	if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
+	/* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
+	if (!mcbsp->pdata->has_ccr) {
 		regs->rcr2	|= RFIG;
 		regs->xcr2	|= XFIG;
 	}
-	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+
+	/* Configure XCCR/RCCR only for revisions which have ccr registers */
+	if (mcbsp->pdata->has_ccr) {
 		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 	}
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:47 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:47 +0300
Subject: [PATCH v2 8/9] ARM: OMAP2+: McBSP: Do not create legacy devices when
 booting with DT data
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-9-git-send-email-peter.ujfalusi@ti.com>

Only create the devices in a legacy way if we do not have the DT data.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 660e00b..d57a357 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -113,7 +114,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 
 static int __init omap2_mcbsp_init(void)
 {
-	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+	if (!of_have_populated_dt())
+		omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
 	return 0;
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:48 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:48 +0300
Subject: [PATCH v2 9/9] ASoC: omap-mcbsp: Add device tree bindings
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-10-git-send-email-peter.ujfalusi@ti.com>

Device tree support for McBSP modules on OMAP2+ SoC.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 +++++++++++++
 sound/soc/omap/omap-mcbsp.c                        |   66 +++++++++++++++++++-
 2 files changed, 110 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
new file mode 100644
index 0000000..447cb13
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -0,0 +1,45 @@
+* Texas Instruments OMAP2+ McBSP module
+
+Required properties:
+- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
+	      "ti,omap2430-mcbsp" for McBSP on OMAP2430
+	      "ti,omap3-mcbsp" for McBSP on OMAP3
+	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
+- reg: Register location and size, for OMAP4+ as an array:
+       <MPU access base address, size>,
+       <L3 interconnect address, size>;
+- interrupts: Interrupt numbers for the McBSP port, as an array in case the
+	      McBSP IP have more interrupt lines:
+	<OCP compliant irq>,
+	<TX irq>,
+	<RX irq>;
+- interrupt-parent: The parent interrupt controller
+- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
+- ti,hwmods: Name of the hwmod associated to the McBSP port
+
+Sidetone support for OMAP3 McBSP2 and 3 ports:
+- sidetone { }: Within this section the following parameters are required:
+- reg: Register location and size for the ST block
+- interrupts: The interrupt number for the ST block
+- interrupt-parent: The parent interrupt controller for the ST block
+
+Example:
+
+mcbsp2: mcbsp at 49022000 {
+	compatible = "ti,omap3-mcbsp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0x49022000 0xff>;
+	interrupts = <0 17 0x4>, /* OCP compliant interrup */
+		     <0 62 0x4>, /* TX interrup */
+		     <0 63 0x4>; /* RX interrup */
+	interrupt-parent = <&intc>;
+	ti,buffer-size = <1280>;
+	ti,hwmods = "mcbsp2";
+
+	sidetone {
+		reg = <0x49028000 0xff>;
+		interrupts = <0 4 0x4>;
+		interrupt-parent = <&intc>;
+	};
+};
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index b9770ee..2e1750e 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -26,6 +26,8 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -737,13 +739,74 @@ int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 }
 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 
+static struct omap_mcbsp_platform_data omap2420_pdata = {
+	.reg_step = 4,
+	.reg_size = 2,
+};
+
+static struct omap_mcbsp_platform_data omap2430_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+};
+
+static struct omap_mcbsp_platform_data omap3_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static struct omap_mcbsp_platform_data omap4_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static const struct of_device_id omap_mcbsp_of_match[] = {
+	{
+		.compatible = "ti,omap2420-mcbsp",
+		.data = &omap2420_pdata,
+	},
+	{
+		.compatible = "ti,omap2430-mcbsp",
+		.data = &omap2430_pdata,
+	},
+	{
+		.compatible = "ti,omap3-mcbsp",
+		.data = &omap3_pdata,
+	},
+	{
+		.compatible = "ti,omap4-mcbsp",
+		.data = &omap4_pdata,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
+
 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 {
 	struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 	struct omap_mcbsp *mcbsp;
+	const struct of_device_id *match;
 	int ret;
 
-	if (!pdata) {
+	match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
+	if (match) {
+		struct device_node *node = pdev->dev.of_node;
+		int buffer_size;
+
+		pdata = devm_kzalloc(&pdev->dev,
+				     sizeof(struct omap_mcbsp_platform_data),
+				     GFP_KERNEL);
+		if (!pdata)
+			return -ENOMEM;
+
+		memcpy(pdata, match->data, sizeof(*pdata));
+		if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
+			pdata->buffer_size = buffer_size;
+	} else if (!pdata) {
 		dev_err(&pdev->dev, "missing platform data.\n");
 		return -EINVAL;
 	}
@@ -785,6 +848,7 @@ static struct platform_driver asoc_mcbsp_driver = {
 	.driver = {
 			.name = "omap-mcbsp",
 			.owner = THIS_MODULE,
+			.of_match_table = omap_mcbsp_of_match,
 	},
 
 	.probe = asoc_mcbsp_probe,
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Mon Aug 13 10:22:43 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 13 Aug 2012 17:22:43 +0300
Subject: [PATCH v2 4/9] ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR
 signal muxing
In-Reply-To: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344867768-26335-5-git-send-email-peter.ujfalusi@ti.com>

The muxing is done at board level, no need to do it in the ASoC machine
driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/am3517evm.c |   20 ++------------------
 1 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/sound/soc/omap/am3517evm.c b/sound/soc/omap/am3517evm.c
index 009533a..a997988 100644
--- a/sound/soc/omap/am3517evm.c
+++ b/sound/soc/omap/am3517evm.c
@@ -47,26 +47,10 @@ static int am3517evm_hw_params(struct snd_pcm_substream *substream,
 	/* Set the codec system clock for DAC and ADC */
 	ret = snd_soc_dai_set_sysclk(codec_dai, 0,
 			CODEC_CLOCK, SND_SOC_CLOCK_IN);
-	if (ret < 0) {
+	if (ret < 0)
 		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_CLKR_SRC_CLKX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_CLKR_SRC_CLKX\n");
-		return ret;
-	}
 
-	snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_FSR_SRC_FSX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_FSR_SRC_FSX\n");
-		return ret;
-	}
-
-	return 0;
+	return ret;
 }
 
 static struct snd_soc_ops am3517evm_ops = {
-- 
1.7.8.6



From andrew at lunn.ch  Mon Aug 13 10:33:19 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 13 Aug 2012 16:33:19 +0200
Subject: [patch] ARM: Kirkwood: Fix iconnect leds
In-Reply-To: <20120805203610.540496769@rtp-net.org>
References: <20120805203610.540496769@rtp-net.org>
Message-ID: <20120813143319.GF12756@lunn.ch>

On Sun, Aug 05, 2012 at 10:35:56PM +0200, Arnaud Patard wrote:
> While converting, a led has been missed leading to wrong power blue led
> definition. Add it back and fix the gpio used on the power blue led.

Acked-by: Andrew Lunn <andrew at lunn.ch>

Jason, please channel this towards t3.6-rc2

       Andrew

> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>
> Index: alunn/arch/arm/boot/dts/kirkwood-iconnect.dts
> ===================================================================
> --- alunn.orig/arch/arm/boot/dts/kirkwood-iconnect.dts	2012-07-20 09:14:45.000000000 +0200
> +++ alunn/arch/arm/boot/dts/kirkwood-iconnect.dts	2012-07-25 23:46:51.039862074 +0200
> @@ -41,9 +41,13 @@
>  		};
>  		power-blue {
>  			label = "power:blue";
> -			gpios = <&gpio1 11 0>;
> +			gpios = <&gpio1 10 0>;
>  			linux,default-trigger = "timer";
>  		};
> +		power-red {
> +			label = "power:red";
> +			gpios = <&gpio1 11 0>;
> +		};
>  		usb1 {
>  			label = "usb1:blue";
>  			gpios = <&gpio1 12 0>;
> 
> 


From andrew at lunn.ch  Mon Aug 13 10:33:47 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 13 Aug 2012 16:33:47 +0200
Subject: [patch] ARM: Kirkwood: fix Makefile.boot
In-Reply-To: <20120805203610.644315269@rtp-net.org>
References: <20120805203555.457907381@rtp-net.org>
 <20120805203610.644315269@rtp-net.org>
Message-ID: <20120813143347.GG12756@lunn.ch>

On Sun, Aug 05, 2012 at 10:35:57PM +0200, Arnaud Patard wrote:
> While building the dtbs target, one is getting:
> 
> make dtbs
> make[1]: *** No rule to make target `arch/arm/boot/kirkwood-qnap-ts219.dtb', needed by `arch/arm/boot/dtbs'.  Stop.
> make: *** [dtbs] Error 2
> 
> The reason is that there's no kirkwood-qnap-ts219.dts file. Update Makefile.boot
> to reflect the dts files present.

Acked-by: Andrew Lunn <andrew at lunn.ch>

Jason, please channel this towards t3.6-rc2

> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>
> Index: alunn/arch/arm/mach-kirkwood/Makefile.boot
> ===================================================================
> --- alunn.orig/arch/arm/mach-kirkwood/Makefile.boot	2012-07-20 09:14:46.010289974 +0200
> +++ alunn/arch/arm/mach-kirkwood/Makefile.boot	2012-07-26 00:13:14.983792385 +0200
> @@ -7,7 +7,8 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) +=
>  dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
>  dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
>  dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
> -dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
> +dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6281.dtb
> +dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6282.dtb
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> 
> 


From nico at fluxnic.net  Mon Aug 13 09:35:10 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 13 Aug 2012 09:35:10 -0400 (EDT)
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <1344845704.31459.11.camel@twins>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <1344845704.31459.11.camel@twins>
Message-ID: <alpine.LFD.2.02.1208130931530.5231@xanadu.home>

On Mon, 13 Aug 2012, Peter Zijlstra wrote:

> OK, I like this.. Thanks guys! Will will you send a final and complete
> patch?

Here it is:

--- >8

Date: Fri, 10 Aug 2012 15:22:09 +0100
From: Will Deacon <will.deacon at arm.com>
Subject: [PATCH] mutex: place lock in contended state after fastpath_lock failure

ARM recently moved to asm-generic/mutex-xchg.h for its mutex
implementation after the previous implementation was found to be missing
some crucial memory barriers. However, this has revealed some problems
running hackbench on SMP platforms due to the way in which the
MUTEX_SPIN_ON_OWNER code operates.

The symptoms are that a bunch of hackbench tasks are left waiting on an
unlocked mutex and therefore never get woken up to claim it. This boils
down to the following sequence of events:

        Task A        Task B        Task C        Lock value
0                                                     1
1       lock()                                        0
2                     lock()                          0
3                     spin(A)                         0
4       unlock()                                      1
5                                   lock()            0
6                     cmpxchg(1,0)                    0
7                     contended()                    -1
8       lock()                                        0
9       spin(C)                                       0
10                                  unlock()          1
11      cmpxchg(1,0)                                  0
12      unlock()                                      1

At this point, the lock is unlocked, but Task B is in an uninterruptible
sleep with nobody to wake it up.

This patch fixes the problem by ensuring we put the lock into the
contended state if we fail to acquire it on the fastpath, ensuring that
any blocked waiters are woken up when the mutex is released.

Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Chris Mason <chris.mason at fusionio.com>
Cc: Ingo Molnar <mingo at elte.hu>
Cc: <stable at vger.kernel.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
---

 include/asm-generic/mutex-xchg.h |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h
index 580a6d3..c04e0db 100644
--- a/include/asm-generic/mutex-xchg.h
+++ b/include/asm-generic/mutex-xchg.h
@@ -26,7 +26,13 @@ static inline void
 __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
-		fail_fn(count);
+		/*
+		 * We failed to acquire the lock, so mark it contended
+		 * to ensure that any waiting tasks are woken up by the
+		 * unlock slow path.
+		 */
+		if (likely(atomic_xchg(count, -1) != 1))
+			fail_fn(count);
 }
 
 /**
@@ -43,7 +49,8 @@ static inline int
 __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
 {
 	if (unlikely(atomic_xchg(count, 0) != 1))
-		return fail_fn(count);
+		if (likely(atomic_xchg(count, -1) != 1))
+			return fail_fn(count);
 	return 0;
 }
 


From arnd at arndb.de  Mon Aug 13 10:41:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 13 Aug 2012 14:41:40 +0000
Subject: [GIT PULL] arm: documentation
In-Reply-To: <20120811085925.34bb8337@skate>
References: <20120811085925.34bb8337@skate>
Message-ID: <201208131441.40364.arnd@arndb.de>

On Saturday 11 August 2012, Thomas Petazzoni wrote:
> Arnd, Olof,
> 
> Please pull the following new documentation of Marvell SoC families
> that has been Acked-by Arnd.
> 

Pulled, thanks!

	Arnd


From jonathan.austin at arm.com  Mon Aug 13 10:42:52 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Mon, 13 Aug 2012 15:42:52 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <1613427331.1190769.1344577949008.JavaMail.root@mozilla.com>
References: <1613427331.1190769.1344577949008.JavaMail.root@mozilla.com>
Message-ID: <5029126C.5000202@arm.com>

Hi Martin,

On 10/08/12 06:52, Martin Rosenberg wrote:

> A couple of days ago, I started a project to coalesce calls to
> cachefush in mozilla's JIT.  After working out most of the bugs that
> I could find, there were still some lingering failures, which I
> believe finally tracked down to do_cache_op, where it looks like only
> the first contiguous region of virtual memory is consulted.  I don't
> actually know about any of the functions that are being called, nor
> exactly what the datastructures represent, but if my understanding of
> the code is correct, then it is at odds with the documentation that
> is available (namely, man cacheflush(2)).  Is there something I've
> overlooked, any suggested workarounds?  Thanks --Marty
> 


On my system the cacheflush(2) documentation suggests it is MIPS only:
"This  Linux-specific  system call is only available on MIPS based
systems.  It should not be used in programs intended to be portable."

As you've established by looking at the code, on ARM we intentionally
attempt to flush only the part of the given range that occurs inside the
vma containing 'start'.

When flushing some huge range that spans multiple vmas, there might be
junk in the middle that it doesn't make sense to flush (eg devices), so
a fix that guarantees to flush an entire range isn't trivial and there
need to be some decisions about how to handle nonsensical requests. If
it is *really* necessary to flush large ranges like this it would be
good to understand why.

That said, now that it is possible to return errors from the cache
flushing syscalls[1] we should probably at least consider returning
something to report that the range had been truncated. There'd need to
be some thought given to how to represent errors where the range is
truncated *and* the flush_cache_user_range() function returns an error,
as well as a justification of why reporting truncation is
useful/necessary: For example the gcc builtin function:

    void __builtin___clear_cache (char *begin, char *end) )

has no return value to propagate error data[2], so it is unlikely that
much of userspace could take advantage of the return codes. There's some
historical discussion of this issue at [3]

Hope that helps,

Jonny

[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-April/096299.html
which was committed as c5102f593550 - ARM: 7408/1: cacheflush: return
error to userspace when flushing syscall fails)
[2] http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
[3]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-April/094869.html






From a.p.zijlstra at chello.nl  Mon Aug 13 10:45:29 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Mon, 13 Aug 2012 16:45:29 +0200
Subject: RFC: mutex: hung tasks on SMP platforms with
 asm-generic/mutex-xchg.h
In-Reply-To: <20120813141156.GC20537@mudshark.cambridge.arm.com>
References: <20120807115647.GA12828@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208090029460.5231@xanadu.home>
 <20120809144953.GC18486@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208091201380.5231@xanadu.home>
 <alpine.LFD.2.02.1208091243080.5231@xanadu.home>
 <1344845704.31459.11.camel@twins>
 <alpine.LFD.2.02.1208130931530.5231@xanadu.home>
 <1344866717.31459.32.camel@twins>
 <20120813141156.GC20537@mudshark.cambridge.arm.com>
Message-ID: <1344869129.31459.33.camel@twins>

On Mon, 2012-08-13 at 15:11 +0100, Will Deacon wrote:
> 
> > Will you carry this through the ARM tree or do you want me/Ingo to take
> > it?
> 
> Please can you guys take it? The move to mutex-dec can go through the ARM
> tree but it's probably best if you take the core change. 

OK, done. Thanks!


From shawn.guo at linaro.org  Mon Aug 13 10:47:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 22:47:58 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
Message-ID: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>

Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
pinctrl drivers number pad from 1.  It causes problem/confusion when
driver accesses imx51_pinctrl_pads array using pin ID as the index.

Change imx51_pads and imx53_pads numbering start from 0.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/pinctrl/pinctrl-imx51.c |  490 +++++++++++++++++++-------------------
 drivers/pinctrl/pinctrl-imx53.c |  402 ++++++++++++++++----------------
 2 files changed, 446 insertions(+), 446 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index 9fd0216..fb84689 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -23,251 +23,251 @@
 #include "pinctrl-imx.h"
 
 enum imx51_pads {
-	MX51_PAD_EIM_D16 = 1,
-	MX51_PAD_EIM_D17 = 2,
-	MX51_PAD_EIM_D18 = 3,
-	MX51_PAD_EIM_D19 = 4,
-	MX51_PAD_EIM_D20 = 5,
-	MX51_PAD_EIM_D21 = 6,
-	MX51_PAD_EIM_D22 = 7,
-	MX51_PAD_EIM_D23 = 8,
-	MX51_PAD_EIM_D24 = 9,
-	MX51_PAD_EIM_D25 = 10,
-	MX51_PAD_EIM_D26 = 11,
-	MX51_PAD_EIM_D27 = 12,
-	MX51_PAD_EIM_D28 = 13,
-	MX51_PAD_EIM_D29 = 14,
-	MX51_PAD_EIM_D30 = 15,
-	MX51_PAD_EIM_D31 = 16,
-	MX51_PAD_EIM_A16 = 17,
-	MX51_PAD_EIM_A17 = 18,
-	MX51_PAD_EIM_A18 = 19,
-	MX51_PAD_EIM_A19 = 20,
-	MX51_PAD_EIM_A20 = 21,
-	MX51_PAD_EIM_A21 = 22,
-	MX51_PAD_EIM_A22 = 23,
-	MX51_PAD_EIM_A23 = 24,
-	MX51_PAD_EIM_A24 = 25,
-	MX51_PAD_EIM_A25 = 26,
-	MX51_PAD_EIM_A26 = 27,
-	MX51_PAD_EIM_A27 = 28,
-	MX51_PAD_EIM_EB0 = 29,
-	MX51_PAD_EIM_EB1 = 30,
-	MX51_PAD_EIM_EB2 = 31,
-	MX51_PAD_EIM_EB3 = 32,
-	MX51_PAD_EIM_OE = 33,
-	MX51_PAD_EIM_CS0 = 34,
-	MX51_PAD_EIM_CS1 = 35,
-	MX51_PAD_EIM_CS2 = 36,
-	MX51_PAD_EIM_CS3 = 37,
-	MX51_PAD_EIM_CS4 = 38,
-	MX51_PAD_EIM_CS5 = 39,
-	MX51_PAD_EIM_DTACK = 40,
-	MX51_PAD_EIM_LBA = 41,
-	MX51_PAD_EIM_CRE = 42,
-	MX51_PAD_DRAM_CS1 = 43,
-	MX51_PAD_NANDF_WE_B = 44,
-	MX51_PAD_NANDF_RE_B = 45,
-	MX51_PAD_NANDF_ALE = 46,
-	MX51_PAD_NANDF_CLE = 47,
-	MX51_PAD_NANDF_WP_B = 48,
-	MX51_PAD_NANDF_RB0 = 49,
-	MX51_PAD_NANDF_RB1 = 50,
-	MX51_PAD_NANDF_RB2 = 51,
-	MX51_PAD_NANDF_RB3 = 52,
-	MX51_PAD_GPIO_NAND = 53,
-	MX51_PAD_NANDF_CS0 = 54,
-	MX51_PAD_NANDF_CS1 = 55,
-	MX51_PAD_NANDF_CS2 = 56,
-	MX51_PAD_NANDF_CS3 = 57,
-	MX51_PAD_NANDF_CS4 = 58,
-	MX51_PAD_NANDF_CS5 = 59,
-	MX51_PAD_NANDF_CS6 = 60,
-	MX51_PAD_NANDF_CS7 = 61,
-	MX51_PAD_NANDF_RDY_INT = 62,
-	MX51_PAD_NANDF_D15 = 63,
-	MX51_PAD_NANDF_D14 = 64,
-	MX51_PAD_NANDF_D13 = 65,
-	MX51_PAD_NANDF_D12 = 66,
-	MX51_PAD_NANDF_D11 = 67,
-	MX51_PAD_NANDF_D10 = 68,
-	MX51_PAD_NANDF_D9 = 69,
-	MX51_PAD_NANDF_D8 = 70,
-	MX51_PAD_NANDF_D7 = 71,
-	MX51_PAD_NANDF_D6 = 72,
-	MX51_PAD_NANDF_D5 = 73,
-	MX51_PAD_NANDF_D4 = 74,
-	MX51_PAD_NANDF_D3 = 75,
-	MX51_PAD_NANDF_D2 = 76,
-	MX51_PAD_NANDF_D1 = 77,
-	MX51_PAD_NANDF_D0 = 78,
-	MX51_PAD_CSI1_D8 = 79,
-	MX51_PAD_CSI1_D9 = 80,
-	MX51_PAD_CSI1_D10 = 81,
-	MX51_PAD_CSI1_D11 = 82,
-	MX51_PAD_CSI1_D12 = 83,
-	MX51_PAD_CSI1_D13 = 84,
-	MX51_PAD_CSI1_D14 = 85,
-	MX51_PAD_CSI1_D15 = 86,
-	MX51_PAD_CSI1_D16 = 87,
-	MX51_PAD_CSI1_D17 = 88,
-	MX51_PAD_CSI1_D18 = 89,
-	MX51_PAD_CSI1_D19 = 90,
-	MX51_PAD_CSI1_VSYNC = 91,
-	MX51_PAD_CSI1_HSYNC = 92,
-	MX51_PAD_CSI1_PIXCLK = 93,
-	MX51_PAD_CSI1_MCLK = 94,
-	MX51_PAD_CSI2_D12 = 95,
-	MX51_PAD_CSI2_D13 = 96,
-	MX51_PAD_CSI2_D14 = 97,
-	MX51_PAD_CSI2_D15 = 98,
-	MX51_PAD_CSI2_D16 = 99,
-	MX51_PAD_CSI2_D17 = 100,
-	MX51_PAD_CSI2_D18 = 101,
-	MX51_PAD_CSI2_D19 = 102,
-	MX51_PAD_CSI2_VSYNC = 103,
-	MX51_PAD_CSI2_HSYNC = 104,
-	MX51_PAD_CSI2_PIXCLK = 105,
-	MX51_PAD_I2C1_CLK = 106,
-	MX51_PAD_I2C1_DAT = 107,
-	MX51_PAD_AUD3_BB_TXD = 108,
-	MX51_PAD_AUD3_BB_RXD = 109,
-	MX51_PAD_AUD3_BB_CK = 110,
-	MX51_PAD_AUD3_BB_FS = 111,
-	MX51_PAD_CSPI1_MOSI = 112,
-	MX51_PAD_CSPI1_MISO = 113,
-	MX51_PAD_CSPI1_SS0 = 114,
-	MX51_PAD_CSPI1_SS1 = 115,
-	MX51_PAD_CSPI1_RDY = 116,
-	MX51_PAD_CSPI1_SCLK = 117,
-	MX51_PAD_UART1_RXD = 118,
-	MX51_PAD_UART1_TXD = 119,
-	MX51_PAD_UART1_RTS = 120,
-	MX51_PAD_UART1_CTS = 121,
-	MX51_PAD_UART2_RXD = 122,
-	MX51_PAD_UART2_TXD = 123,
-	MX51_PAD_UART3_RXD = 124,
-	MX51_PAD_UART3_TXD = 125,
-	MX51_PAD_OWIRE_LINE = 126,
-	MX51_PAD_KEY_ROW0 = 127,
-	MX51_PAD_KEY_ROW1 = 128,
-	MX51_PAD_KEY_ROW2 = 129,
-	MX51_PAD_KEY_ROW3 = 130,
-	MX51_PAD_KEY_COL0 = 131,
-	MX51_PAD_KEY_COL1 = 132,
-	MX51_PAD_KEY_COL2 = 133,
-	MX51_PAD_KEY_COL3 = 134,
-	MX51_PAD_KEY_COL4 = 135,
-	MX51_PAD_KEY_COL5 = 136,
-	MX51_PAD_USBH1_CLK = 137,
-	MX51_PAD_USBH1_DIR = 138,
-	MX51_PAD_USBH1_STP = 139,
-	MX51_PAD_USBH1_NXT = 140,
-	MX51_PAD_USBH1_DATA0 = 141,
-	MX51_PAD_USBH1_DATA1 = 142,
-	MX51_PAD_USBH1_DATA2 = 143,
-	MX51_PAD_USBH1_DATA3 = 144,
-	MX51_PAD_USBH1_DATA4 = 145,
-	MX51_PAD_USBH1_DATA5 = 146,
-	MX51_PAD_USBH1_DATA6 = 147,
-	MX51_PAD_USBH1_DATA7 = 148,
-	MX51_PAD_DI1_PIN11 = 149,
-	MX51_PAD_DI1_PIN12 = 150,
-	MX51_PAD_DI1_PIN13 = 151,
-	MX51_PAD_DI1_D0_CS = 152,
-	MX51_PAD_DI1_D1_CS = 153,
-	MX51_PAD_DISPB2_SER_DIN = 154,
-	MX51_PAD_DISPB2_SER_DIO = 155,
-	MX51_PAD_DISPB2_SER_CLK = 156,
-	MX51_PAD_DISPB2_SER_RS = 157,
-	MX51_PAD_DISP1_DAT0 = 158,
-	MX51_PAD_DISP1_DAT1 = 159,
-	MX51_PAD_DISP1_DAT2 = 160,
-	MX51_PAD_DISP1_DAT3 = 161,
-	MX51_PAD_DISP1_DAT4 = 162,
-	MX51_PAD_DISP1_DAT5 = 163,
-	MX51_PAD_DISP1_DAT6 = 164,
-	MX51_PAD_DISP1_DAT7 = 165,
-	MX51_PAD_DISP1_DAT8 = 166,
-	MX51_PAD_DISP1_DAT9 = 167,
-	MX51_PAD_DISP1_DAT10 = 168,
-	MX51_PAD_DISP1_DAT11 = 169,
-	MX51_PAD_DISP1_DAT12 = 170,
-	MX51_PAD_DISP1_DAT13 = 171,
-	MX51_PAD_DISP1_DAT14 = 172,
-	MX51_PAD_DISP1_DAT15 = 173,
-	MX51_PAD_DISP1_DAT16 = 174,
-	MX51_PAD_DISP1_DAT17 = 175,
-	MX51_PAD_DISP1_DAT18 = 176,
-	MX51_PAD_DISP1_DAT19 = 177,
-	MX51_PAD_DISP1_DAT20 = 178,
-	MX51_PAD_DISP1_DAT21 = 179,
-	MX51_PAD_DISP1_DAT22 = 180,
-	MX51_PAD_DISP1_DAT23 = 181,
-	MX51_PAD_DI1_PIN3 = 182,
-	MX51_PAD_DI1_PIN2 = 183,
-	MX51_PAD_DI_GP2 = 184,
-	MX51_PAD_DI_GP3 = 185,
-	MX51_PAD_DI2_PIN4 = 186,
-	MX51_PAD_DI2_PIN2 = 187,
-	MX51_PAD_DI2_PIN3 = 188,
-	MX51_PAD_DI2_DISP_CLK = 189,
-	MX51_PAD_DI_GP4 = 190,
-	MX51_PAD_DISP2_DAT0 = 191,
-	MX51_PAD_DISP2_DAT1 = 192,
-	MX51_PAD_DISP2_DAT2 = 193,
-	MX51_PAD_DISP2_DAT3 = 194,
-	MX51_PAD_DISP2_DAT4 = 195,
-	MX51_PAD_DISP2_DAT5 = 196,
-	MX51_PAD_DISP2_DAT6 = 197,
-	MX51_PAD_DISP2_DAT7 = 198,
-	MX51_PAD_DISP2_DAT8 = 199,
-	MX51_PAD_DISP2_DAT9 = 200,
-	MX51_PAD_DISP2_DAT10 = 201,
-	MX51_PAD_DISP2_DAT11 = 202,
-	MX51_PAD_DISP2_DAT12 = 203,
-	MX51_PAD_DISP2_DAT13 = 204,
-	MX51_PAD_DISP2_DAT14 = 205,
-	MX51_PAD_DISP2_DAT15 = 206,
-	MX51_PAD_SD1_CMD = 207,
-	MX51_PAD_SD1_CLK = 208,
-	MX51_PAD_SD1_DATA0 = 209,
-	MX51_PAD_EIM_DA0 = 210,
-	MX51_PAD_EIM_DA1 = 211,
-	MX51_PAD_EIM_DA2 = 212,
-	MX51_PAD_EIM_DA3 = 213,
-	MX51_PAD_SD1_DATA1 = 214,
-	MX51_PAD_EIM_DA4 = 215,
-	MX51_PAD_EIM_DA5 = 216,
-	MX51_PAD_EIM_DA6 = 217,
-	MX51_PAD_EIM_DA7 = 218,
-	MX51_PAD_SD1_DATA2 = 219,
-	MX51_PAD_EIM_DA10 = 220,
-	MX51_PAD_EIM_DA11 = 221,
-	MX51_PAD_EIM_DA8 = 222,
-	MX51_PAD_EIM_DA9 = 223,
-	MX51_PAD_SD1_DATA3 = 224,
-	MX51_PAD_GPIO1_0 = 225,
-	MX51_PAD_GPIO1_1 = 226,
-	MX51_PAD_EIM_DA12 = 227,
-	MX51_PAD_EIM_DA13 = 228,
-	MX51_PAD_EIM_DA14 = 229,
-	MX51_PAD_EIM_DA15 = 230,
-	MX51_PAD_SD2_CMD = 231,
-	MX51_PAD_SD2_CLK = 232,
-	MX51_PAD_SD2_DATA0 = 233,
-	MX51_PAD_SD2_DATA1 = 234,
-	MX51_PAD_SD2_DATA2 = 235,
-	MX51_PAD_SD2_DATA3 = 236,
-	MX51_PAD_GPIO1_2 = 237,
-	MX51_PAD_GPIO1_3 = 238,
-	MX51_PAD_PMIC_INT_REQ = 239,
-	MX51_PAD_GPIO1_4 = 240,
-	MX51_PAD_GPIO1_5 = 241,
-	MX51_PAD_GPIO1_6 = 242,
-	MX51_PAD_GPIO1_7 = 243,
-	MX51_PAD_GPIO1_8 = 244,
-	MX51_PAD_GPIO1_9 = 245,
+	MX51_PAD_EIM_D16 = 0,
+	MX51_PAD_EIM_D17 = 1,
+	MX51_PAD_EIM_D18 = 2,
+	MX51_PAD_EIM_D19 = 3,
+	MX51_PAD_EIM_D20 = 4,
+	MX51_PAD_EIM_D21 = 5,
+	MX51_PAD_EIM_D22 = 6,
+	MX51_PAD_EIM_D23 = 7,
+	MX51_PAD_EIM_D24 = 8,
+	MX51_PAD_EIM_D25 = 9,
+	MX51_PAD_EIM_D26 = 10,
+	MX51_PAD_EIM_D27 = 11,
+	MX51_PAD_EIM_D28 = 12,
+	MX51_PAD_EIM_D29 = 13,
+	MX51_PAD_EIM_D30 = 14,
+	MX51_PAD_EIM_D31 = 15,
+	MX51_PAD_EIM_A16 = 16,
+	MX51_PAD_EIM_A17 = 17,
+	MX51_PAD_EIM_A18 = 18,
+	MX51_PAD_EIM_A19 = 19,
+	MX51_PAD_EIM_A20 = 20,
+	MX51_PAD_EIM_A21 = 21,
+	MX51_PAD_EIM_A22 = 22,
+	MX51_PAD_EIM_A23 = 23,
+	MX51_PAD_EIM_A24 = 24,
+	MX51_PAD_EIM_A25 = 25,
+	MX51_PAD_EIM_A26 = 26,
+	MX51_PAD_EIM_A27 = 27,
+	MX51_PAD_EIM_EB0 = 28,
+	MX51_PAD_EIM_EB1 = 29,
+	MX51_PAD_EIM_EB2 = 30,
+	MX51_PAD_EIM_EB3 = 31,
+	MX51_PAD_EIM_OE = 32,
+	MX51_PAD_EIM_CS0 = 33,
+	MX51_PAD_EIM_CS1 = 34,
+	MX51_PAD_EIM_CS2 = 35,
+	MX51_PAD_EIM_CS3 = 36,
+	MX51_PAD_EIM_CS4 = 37,
+	MX51_PAD_EIM_CS5 = 38,
+	MX51_PAD_EIM_DTACK = 39,
+	MX51_PAD_EIM_LBA = 40,
+	MX51_PAD_EIM_CRE = 41,
+	MX51_PAD_DRAM_CS1 = 42,
+	MX51_PAD_NANDF_WE_B = 43,
+	MX51_PAD_NANDF_RE_B = 44,
+	MX51_PAD_NANDF_ALE = 45,
+	MX51_PAD_NANDF_CLE = 46,
+	MX51_PAD_NANDF_WP_B = 47,
+	MX51_PAD_NANDF_RB0 = 48,
+	MX51_PAD_NANDF_RB1 = 49,
+	MX51_PAD_NANDF_RB2 = 50,
+	MX51_PAD_NANDF_RB3 = 51,
+	MX51_PAD_GPIO_NAND = 52,
+	MX51_PAD_NANDF_CS0 = 53,
+	MX51_PAD_NANDF_CS1 = 54,
+	MX51_PAD_NANDF_CS2 = 55,
+	MX51_PAD_NANDF_CS3 = 56,
+	MX51_PAD_NANDF_CS4 = 57,
+	MX51_PAD_NANDF_CS5 = 58,
+	MX51_PAD_NANDF_CS6 = 59,
+	MX51_PAD_NANDF_CS7 = 60,
+	MX51_PAD_NANDF_RDY_INT = 61,
+	MX51_PAD_NANDF_D15 = 62,
+	MX51_PAD_NANDF_D14 = 63,
+	MX51_PAD_NANDF_D13 = 64,
+	MX51_PAD_NANDF_D12 = 65,
+	MX51_PAD_NANDF_D11 = 66,
+	MX51_PAD_NANDF_D10 = 67,
+	MX51_PAD_NANDF_D9 = 68,
+	MX51_PAD_NANDF_D8 = 69,
+	MX51_PAD_NANDF_D7 = 70,
+	MX51_PAD_NANDF_D6 = 71,
+	MX51_PAD_NANDF_D5 = 72,
+	MX51_PAD_NANDF_D4 = 73,
+	MX51_PAD_NANDF_D3 = 74,
+	MX51_PAD_NANDF_D2 = 75,
+	MX51_PAD_NANDF_D1 = 76,
+	MX51_PAD_NANDF_D0 = 77,
+	MX51_PAD_CSI1_D8 = 78,
+	MX51_PAD_CSI1_D9 = 79,
+	MX51_PAD_CSI1_D10 = 80,
+	MX51_PAD_CSI1_D11 = 81,
+	MX51_PAD_CSI1_D12 = 82,
+	MX51_PAD_CSI1_D13 = 83,
+	MX51_PAD_CSI1_D14 = 84,
+	MX51_PAD_CSI1_D15 = 85,
+	MX51_PAD_CSI1_D16 = 86,
+	MX51_PAD_CSI1_D17 = 87,
+	MX51_PAD_CSI1_D18 = 88,
+	MX51_PAD_CSI1_D19 = 89,
+	MX51_PAD_CSI1_VSYNC = 90,
+	MX51_PAD_CSI1_HSYNC = 91,
+	MX51_PAD_CSI1_PIXCLK = 92,
+	MX51_PAD_CSI1_MCLK = 93,
+	MX51_PAD_CSI2_D12 = 94,
+	MX51_PAD_CSI2_D13 = 95,
+	MX51_PAD_CSI2_D14 = 96,
+	MX51_PAD_CSI2_D15 = 97,
+	MX51_PAD_CSI2_D16 = 98,
+	MX51_PAD_CSI2_D17 = 99,
+	MX51_PAD_CSI2_D18 = 100,
+	MX51_PAD_CSI2_D19 = 101,
+	MX51_PAD_CSI2_VSYNC = 102,
+	MX51_PAD_CSI2_HSYNC = 103,
+	MX51_PAD_CSI2_PIXCLK = 104,
+	MX51_PAD_I2C1_CLK = 105,
+	MX51_PAD_I2C1_DAT = 106,
+	MX51_PAD_AUD3_BB_TXD = 107,
+	MX51_PAD_AUD3_BB_RXD = 108,
+	MX51_PAD_AUD3_BB_CK = 109,
+	MX51_PAD_AUD3_BB_FS = 110,
+	MX51_PAD_CSPI1_MOSI = 111,
+	MX51_PAD_CSPI1_MISO = 112,
+	MX51_PAD_CSPI1_SS0 = 113,
+	MX51_PAD_CSPI1_SS1 = 114,
+	MX51_PAD_CSPI1_RDY = 115,
+	MX51_PAD_CSPI1_SCLK = 116,
+	MX51_PAD_UART1_RXD = 117,
+	MX51_PAD_UART1_TXD = 118,
+	MX51_PAD_UART1_RTS = 119,
+	MX51_PAD_UART1_CTS = 120,
+	MX51_PAD_UART2_RXD = 121,
+	MX51_PAD_UART2_TXD = 122,
+	MX51_PAD_UART3_RXD = 123,
+	MX51_PAD_UART3_TXD = 124,
+	MX51_PAD_OWIRE_LINE = 125,
+	MX51_PAD_KEY_ROW0 = 126,
+	MX51_PAD_KEY_ROW1 = 127,
+	MX51_PAD_KEY_ROW2 = 128,
+	MX51_PAD_KEY_ROW3 = 129,
+	MX51_PAD_KEY_COL0 = 130,
+	MX51_PAD_KEY_COL1 = 131,
+	MX51_PAD_KEY_COL2 = 132,
+	MX51_PAD_KEY_COL3 = 133,
+	MX51_PAD_KEY_COL4 = 134,
+	MX51_PAD_KEY_COL5 = 135,
+	MX51_PAD_USBH1_CLK = 136,
+	MX51_PAD_USBH1_DIR = 137,
+	MX51_PAD_USBH1_STP = 138,
+	MX51_PAD_USBH1_NXT = 139,
+	MX51_PAD_USBH1_DATA0 = 140,
+	MX51_PAD_USBH1_DATA1 = 141,
+	MX51_PAD_USBH1_DATA2 = 142,
+	MX51_PAD_USBH1_DATA3 = 143,
+	MX51_PAD_USBH1_DATA4 = 144,
+	MX51_PAD_USBH1_DATA5 = 145,
+	MX51_PAD_USBH1_DATA6 = 146,
+	MX51_PAD_USBH1_DATA7 = 147,
+	MX51_PAD_DI1_PIN11 = 148,
+	MX51_PAD_DI1_PIN12 = 149,
+	MX51_PAD_DI1_PIN13 = 150,
+	MX51_PAD_DI1_D0_CS = 151,
+	MX51_PAD_DI1_D1_CS = 152,
+	MX51_PAD_DISPB2_SER_DIN = 153,
+	MX51_PAD_DISPB2_SER_DIO = 154,
+	MX51_PAD_DISPB2_SER_CLK = 155,
+	MX51_PAD_DISPB2_SER_RS = 156,
+	MX51_PAD_DISP1_DAT0 = 157,
+	MX51_PAD_DISP1_DAT1 = 158,
+	MX51_PAD_DISP1_DAT2 = 159,
+	MX51_PAD_DISP1_DAT3 = 160,
+	MX51_PAD_DISP1_DAT4 = 161,
+	MX51_PAD_DISP1_DAT5 = 162,
+	MX51_PAD_DISP1_DAT6 = 163,
+	MX51_PAD_DISP1_DAT7 = 164,
+	MX51_PAD_DISP1_DAT8 = 165,
+	MX51_PAD_DISP1_DAT9 = 166,
+	MX51_PAD_DISP1_DAT10 = 167,
+	MX51_PAD_DISP1_DAT11 = 168,
+	MX51_PAD_DISP1_DAT12 = 169,
+	MX51_PAD_DISP1_DAT13 = 170,
+	MX51_PAD_DISP1_DAT14 = 171,
+	MX51_PAD_DISP1_DAT15 = 172,
+	MX51_PAD_DISP1_DAT16 = 173,
+	MX51_PAD_DISP1_DAT17 = 174,
+	MX51_PAD_DISP1_DAT18 = 175,
+	MX51_PAD_DISP1_DAT19 = 176,
+	MX51_PAD_DISP1_DAT20 = 177,
+	MX51_PAD_DISP1_DAT21 = 178,
+	MX51_PAD_DISP1_DAT22 = 179,
+	MX51_PAD_DISP1_DAT23 = 180,
+	MX51_PAD_DI1_PIN3 = 181,
+	MX51_PAD_DI1_PIN2 = 182,
+	MX51_PAD_DI_GP2 = 183,
+	MX51_PAD_DI_GP3 = 184,
+	MX51_PAD_DI2_PIN4 = 185,
+	MX51_PAD_DI2_PIN2 = 186,
+	MX51_PAD_DI2_PIN3 = 187,
+	MX51_PAD_DI2_DISP_CLK = 188,
+	MX51_PAD_DI_GP4 = 189,
+	MX51_PAD_DISP2_DAT0 = 190,
+	MX51_PAD_DISP2_DAT1 = 191,
+	MX51_PAD_DISP2_DAT2 = 192,
+	MX51_PAD_DISP2_DAT3 = 193,
+	MX51_PAD_DISP2_DAT4 = 194,
+	MX51_PAD_DISP2_DAT5 = 195,
+	MX51_PAD_DISP2_DAT6 = 196,
+	MX51_PAD_DISP2_DAT7 = 197,
+	MX51_PAD_DISP2_DAT8 = 198,
+	MX51_PAD_DISP2_DAT9 = 199,
+	MX51_PAD_DISP2_DAT10 = 200,
+	MX51_PAD_DISP2_DAT11 = 201,
+	MX51_PAD_DISP2_DAT12 = 202,
+	MX51_PAD_DISP2_DAT13 = 203,
+	MX51_PAD_DISP2_DAT14 = 204,
+	MX51_PAD_DISP2_DAT15 = 205,
+	MX51_PAD_SD1_CMD = 206,
+	MX51_PAD_SD1_CLK = 207,
+	MX51_PAD_SD1_DATA0 = 208,
+	MX51_PAD_EIM_DA0 = 209,
+	MX51_PAD_EIM_DA1 = 210,
+	MX51_PAD_EIM_DA2 = 211,
+	MX51_PAD_EIM_DA3 = 212,
+	MX51_PAD_SD1_DATA1 = 213,
+	MX51_PAD_EIM_DA4 = 214,
+	MX51_PAD_EIM_DA5 = 215,
+	MX51_PAD_EIM_DA6 = 216,
+	MX51_PAD_EIM_DA7 = 217,
+	MX51_PAD_SD1_DATA2 = 218,
+	MX51_PAD_EIM_DA10 = 219,
+	MX51_PAD_EIM_DA11 = 220,
+	MX51_PAD_EIM_DA8 = 221,
+	MX51_PAD_EIM_DA9 = 222,
+	MX51_PAD_SD1_DATA3 = 223,
+	MX51_PAD_GPIO1_0 = 224,
+	MX51_PAD_GPIO1_1 = 225,
+	MX51_PAD_EIM_DA12 = 226,
+	MX51_PAD_EIM_DA13 = 227,
+	MX51_PAD_EIM_DA14 = 228,
+	MX51_PAD_EIM_DA15 = 229,
+	MX51_PAD_SD2_CMD = 230,
+	MX51_PAD_SD2_CLK = 231,
+	MX51_PAD_SD2_DATA0 = 232,
+	MX51_PAD_SD2_DATA1 = 233,
+	MX51_PAD_SD2_DATA2 = 234,
+	MX51_PAD_SD2_DATA3 = 235,
+	MX51_PAD_GPIO1_2 = 236,
+	MX51_PAD_GPIO1_3 = 237,
+	MX51_PAD_PMIC_INT_REQ = 238,
+	MX51_PAD_GPIO1_4 = 239,
+	MX51_PAD_GPIO1_5 = 240,
+	MX51_PAD_GPIO1_6 = 241,
+	MX51_PAD_GPIO1_7 = 242,
+	MX51_PAD_GPIO1_8 = 243,
+	MX51_PAD_GPIO1_9 = 244,
 };
 
 /* imx51 register maps */
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 1f49e16..783feb1 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -23,207 +23,207 @@
 #include "pinctrl-imx.h"
 
 enum imx53_pads {
-	MX53_PAD_GPIO_19 = 1,
-	MX53_PAD_KEY_COL0 = 2,
-	MX53_PAD_KEY_ROW0 = 3,
-	MX53_PAD_KEY_COL1 = 4,
-	MX53_PAD_KEY_ROW1 = 5,
-	MX53_PAD_KEY_COL2 = 6,
-	MX53_PAD_KEY_ROW2 = 7,
-	MX53_PAD_KEY_COL3 = 8,
-	MX53_PAD_KEY_ROW3 = 9,
-	MX53_PAD_KEY_COL4 = 10,
-	MX53_PAD_KEY_ROW4 = 11,
-	MX53_PAD_DI0_DISP_CLK = 12,
-	MX53_PAD_DI0_PIN15 = 13,
-	MX53_PAD_DI0_PIN2 = 14,
-	MX53_PAD_DI0_PIN3 = 15,
-	MX53_PAD_DI0_PIN4 = 16,
-	MX53_PAD_DISP0_DAT0 = 17,
-	MX53_PAD_DISP0_DAT1 = 18,
-	MX53_PAD_DISP0_DAT2 = 19,
-	MX53_PAD_DISP0_DAT3 = 20,
-	MX53_PAD_DISP0_DAT4 = 21,
-	MX53_PAD_DISP0_DAT5 = 22,
-	MX53_PAD_DISP0_DAT6 = 23,
-	MX53_PAD_DISP0_DAT7 = 24,
-	MX53_PAD_DISP0_DAT8 = 25,
-	MX53_PAD_DISP0_DAT9 = 26,
-	MX53_PAD_DISP0_DAT10 = 27,
-	MX53_PAD_DISP0_DAT11 = 28,
-	MX53_PAD_DISP0_DAT12 = 29,
-	MX53_PAD_DISP0_DAT13 = 30,
-	MX53_PAD_DISP0_DAT14 = 31,
-	MX53_PAD_DISP0_DAT15 = 32,
-	MX53_PAD_DISP0_DAT16 = 33,
-	MX53_PAD_DISP0_DAT17 = 34,
-	MX53_PAD_DISP0_DAT18 = 35,
-	MX53_PAD_DISP0_DAT19 = 36,
-	MX53_PAD_DISP0_DAT20 = 37,
-	MX53_PAD_DISP0_DAT21 = 38,
-	MX53_PAD_DISP0_DAT22 = 39,
-	MX53_PAD_DISP0_DAT23 = 40,
-	MX53_PAD_CSI0_PIXCLK = 41,
-	MX53_PAD_CSI0_MCLK = 42,
-	MX53_PAD_CSI0_DATA_EN = 43,
-	MX53_PAD_CSI0_VSYNC = 44,
-	MX53_PAD_CSI0_DAT4 = 45,
-	MX53_PAD_CSI0_DAT5 = 46,
-	MX53_PAD_CSI0_DAT6 = 47,
-	MX53_PAD_CSI0_DAT7 = 48,
-	MX53_PAD_CSI0_DAT8 = 49,
-	MX53_PAD_CSI0_DAT9 = 50,
-	MX53_PAD_CSI0_DAT10 = 51,
-	MX53_PAD_CSI0_DAT11 = 52,
-	MX53_PAD_CSI0_DAT12 = 53,
-	MX53_PAD_CSI0_DAT13 = 54,
-	MX53_PAD_CSI0_DAT14 = 55,
-	MX53_PAD_CSI0_DAT15 = 56,
-	MX53_PAD_CSI0_DAT16 = 57,
-	MX53_PAD_CSI0_DAT17 = 58,
-	MX53_PAD_CSI0_DAT18 = 59,
-	MX53_PAD_CSI0_DAT19 = 60,
-	MX53_PAD_EIM_A25 = 61,
-	MX53_PAD_EIM_EB2 = 62,
-	MX53_PAD_EIM_D16 = 63,
-	MX53_PAD_EIM_D17 = 64,
-	MX53_PAD_EIM_D18 = 65,
-	MX53_PAD_EIM_D19 = 66,
-	MX53_PAD_EIM_D20 = 67,
-	MX53_PAD_EIM_D21 = 68,
-	MX53_PAD_EIM_D22 = 69,
-	MX53_PAD_EIM_D23 = 70,
-	MX53_PAD_EIM_EB3 = 71,
-	MX53_PAD_EIM_D24 = 72,
-	MX53_PAD_EIM_D25 = 73,
-	MX53_PAD_EIM_D26 = 74,
-	MX53_PAD_EIM_D27 = 75,
-	MX53_PAD_EIM_D28 = 76,
-	MX53_PAD_EIM_D29 = 77,
-	MX53_PAD_EIM_D30 = 78,
-	MX53_PAD_EIM_D31 = 79,
-	MX53_PAD_EIM_A24 = 80,
-	MX53_PAD_EIM_A23 = 81,
-	MX53_PAD_EIM_A22 = 82,
-	MX53_PAD_EIM_A21 = 83,
-	MX53_PAD_EIM_A20 = 84,
-	MX53_PAD_EIM_A19 = 85,
-	MX53_PAD_EIM_A18 = 86,
-	MX53_PAD_EIM_A17 = 87,
-	MX53_PAD_EIM_A16 = 88,
-	MX53_PAD_EIM_CS0 = 89,
-	MX53_PAD_EIM_CS1 = 90,
-	MX53_PAD_EIM_OE = 91,
-	MX53_PAD_EIM_RW = 92,
-	MX53_PAD_EIM_LBA = 93,
-	MX53_PAD_EIM_EB0 = 94,
-	MX53_PAD_EIM_EB1 = 95,
-	MX53_PAD_EIM_DA0 = 96,
-	MX53_PAD_EIM_DA1 = 97,
-	MX53_PAD_EIM_DA2 = 98,
-	MX53_PAD_EIM_DA3 = 99,
-	MX53_PAD_EIM_DA4 = 100,
-	MX53_PAD_EIM_DA5 = 101,
-	MX53_PAD_EIM_DA6 = 102,
-	MX53_PAD_EIM_DA7 = 103,
-	MX53_PAD_EIM_DA8 = 104,
-	MX53_PAD_EIM_DA9 = 105,
-	MX53_PAD_EIM_DA10 = 106,
-	MX53_PAD_EIM_DA11 = 107,
-	MX53_PAD_EIM_DA12 = 108,
-	MX53_PAD_EIM_DA13 = 109,
-	MX53_PAD_EIM_DA14 = 110,
-	MX53_PAD_EIM_DA15 = 111,
-	MX53_PAD_NANDF_WE_B = 112,
-	MX53_PAD_NANDF_RE_B = 113,
-	MX53_PAD_EIM_WAIT = 114,
-	MX53_PAD_LVDS1_TX3_P = 115,
-	MX53_PAD_LVDS1_TX2_P = 116,
-	MX53_PAD_LVDS1_CLK_P = 117,
-	MX53_PAD_LVDS1_TX1_P = 118,
-	MX53_PAD_LVDS1_TX0_P = 119,
-	MX53_PAD_LVDS0_TX3_P = 120,
-	MX53_PAD_LVDS0_CLK_P = 121,
-	MX53_PAD_LVDS0_TX2_P = 122,
-	MX53_PAD_LVDS0_TX1_P = 123,
-	MX53_PAD_LVDS0_TX0_P = 124,
-	MX53_PAD_GPIO_10 = 125,
-	MX53_PAD_GPIO_11 = 126,
-	MX53_PAD_GPIO_12 = 127,
-	MX53_PAD_GPIO_13 = 128,
-	MX53_PAD_GPIO_14 = 129,
-	MX53_PAD_NANDF_CLE = 130,
-	MX53_PAD_NANDF_ALE = 131,
-	MX53_PAD_NANDF_WP_B = 132,
-	MX53_PAD_NANDF_RB0 = 133,
-	MX53_PAD_NANDF_CS0 = 134,
-	MX53_PAD_NANDF_CS1 = 135,
-	MX53_PAD_NANDF_CS2 = 136,
-	MX53_PAD_NANDF_CS3 = 137,
-	MX53_PAD_FEC_MDIO = 138,
-	MX53_PAD_FEC_REF_CLK = 139,
-	MX53_PAD_FEC_RX_ER = 140,
-	MX53_PAD_FEC_CRS_DV = 141,
-	MX53_PAD_FEC_RXD1 = 142,
-	MX53_PAD_FEC_RXD0 = 143,
-	MX53_PAD_FEC_TX_EN = 144,
-	MX53_PAD_FEC_TXD1 = 145,
-	MX53_PAD_FEC_TXD0 = 146,
-	MX53_PAD_FEC_MDC = 147,
-	MX53_PAD_PATA_DIOW = 148,
-	MX53_PAD_PATA_DMACK = 149,
-	MX53_PAD_PATA_DMARQ = 150,
-	MX53_PAD_PATA_BUFFER_EN = 151,
-	MX53_PAD_PATA_INTRQ = 152,
-	MX53_PAD_PATA_DIOR = 153,
-	MX53_PAD_PATA_RESET_B = 154,
-	MX53_PAD_PATA_IORDY = 155,
-	MX53_PAD_PATA_DA_0 = 156,
-	MX53_PAD_PATA_DA_1 = 157,
-	MX53_PAD_PATA_DA_2 = 158,
-	MX53_PAD_PATA_CS_0 = 159,
-	MX53_PAD_PATA_CS_1 = 160,
-	MX53_PAD_PATA_DATA0 = 161,
-	MX53_PAD_PATA_DATA1 = 162,
-	MX53_PAD_PATA_DATA2 = 163,
-	MX53_PAD_PATA_DATA3 = 164,
-	MX53_PAD_PATA_DATA4 = 165,
-	MX53_PAD_PATA_DATA5 = 166,
-	MX53_PAD_PATA_DATA6 = 167,
-	MX53_PAD_PATA_DATA7 = 168,
-	MX53_PAD_PATA_DATA8 = 169,
-	MX53_PAD_PATA_DATA9 = 170,
-	MX53_PAD_PATA_DATA10 = 171,
-	MX53_PAD_PATA_DATA11 = 172,
-	MX53_PAD_PATA_DATA12 = 173,
-	MX53_PAD_PATA_DATA13 = 174,
-	MX53_PAD_PATA_DATA14 = 175,
-	MX53_PAD_PATA_DATA15 = 176,
-	MX53_PAD_SD1_DATA0 = 177,
-	MX53_PAD_SD1_DATA1 = 178,
-	MX53_PAD_SD1_CMD = 179,
-	MX53_PAD_SD1_DATA2 = 180,
-	MX53_PAD_SD1_CLK = 181,
-	MX53_PAD_SD1_DATA3 = 182,
-	MX53_PAD_SD2_CLK = 183,
-	MX53_PAD_SD2_CMD = 184,
-	MX53_PAD_SD2_DATA3 = 185,
-	MX53_PAD_SD2_DATA2 = 186,
-	MX53_PAD_SD2_DATA1 = 187,
-	MX53_PAD_SD2_DATA0 = 188,
-	MX53_PAD_GPIO_0 = 189,
-	MX53_PAD_GPIO_1 = 190,
-	MX53_PAD_GPIO_9 = 191,
-	MX53_PAD_GPIO_3 = 192,
-	MX53_PAD_GPIO_6 = 193,
-	MX53_PAD_GPIO_2 = 194,
-	MX53_PAD_GPIO_4 = 195,
-	MX53_PAD_GPIO_5 = 196,
-	MX53_PAD_GPIO_7 = 197,
-	MX53_PAD_GPIO_8 = 198,
-	MX53_PAD_GPIO_16 = 199,
-	MX53_PAD_GPIO_17 = 200,
-	MX53_PAD_GPIO_18 = 201,
+	MX53_PAD_GPIO_19 = 0,
+	MX53_PAD_KEY_COL0 = 1,
+	MX53_PAD_KEY_ROW0 = 2,
+	MX53_PAD_KEY_COL1 = 3,
+	MX53_PAD_KEY_ROW1 = 4,
+	MX53_PAD_KEY_COL2 = 5,
+	MX53_PAD_KEY_ROW2 = 6,
+	MX53_PAD_KEY_COL3 = 7,
+	MX53_PAD_KEY_ROW3 = 8,
+	MX53_PAD_KEY_COL4 = 9,
+	MX53_PAD_KEY_ROW4 = 10,
+	MX53_PAD_DI0_DISP_CLK = 11,
+	MX53_PAD_DI0_PIN15 = 12,
+	MX53_PAD_DI0_PIN2 = 13,
+	MX53_PAD_DI0_PIN3 = 14,
+	MX53_PAD_DI0_PIN4 = 15,
+	MX53_PAD_DISP0_DAT0 = 16,
+	MX53_PAD_DISP0_DAT1 = 17,
+	MX53_PAD_DISP0_DAT2 = 18,
+	MX53_PAD_DISP0_DAT3 = 19,
+	MX53_PAD_DISP0_DAT4 = 20,
+	MX53_PAD_DISP0_DAT5 = 21,
+	MX53_PAD_DISP0_DAT6 = 22,
+	MX53_PAD_DISP0_DAT7 = 23,
+	MX53_PAD_DISP0_DAT8 = 24,
+	MX53_PAD_DISP0_DAT9 = 25,
+	MX53_PAD_DISP0_DAT10 = 26,
+	MX53_PAD_DISP0_DAT11 = 27,
+	MX53_PAD_DISP0_DAT12 = 28,
+	MX53_PAD_DISP0_DAT13 = 29,
+	MX53_PAD_DISP0_DAT14 = 30,
+	MX53_PAD_DISP0_DAT15 = 31,
+	MX53_PAD_DISP0_DAT16 = 32,
+	MX53_PAD_DISP0_DAT17 = 33,
+	MX53_PAD_DISP0_DAT18 = 34,
+	MX53_PAD_DISP0_DAT19 = 35,
+	MX53_PAD_DISP0_DAT20 = 36,
+	MX53_PAD_DISP0_DAT21 = 37,
+	MX53_PAD_DISP0_DAT22 = 38,
+	MX53_PAD_DISP0_DAT23 = 39,
+	MX53_PAD_CSI0_PIXCLK = 40,
+	MX53_PAD_CSI0_MCLK = 41,
+	MX53_PAD_CSI0_DATA_EN = 42,
+	MX53_PAD_CSI0_VSYNC = 43,
+	MX53_PAD_CSI0_DAT4 = 44,
+	MX53_PAD_CSI0_DAT5 = 45,
+	MX53_PAD_CSI0_DAT6 = 46,
+	MX53_PAD_CSI0_DAT7 = 47,
+	MX53_PAD_CSI0_DAT8 = 48,
+	MX53_PAD_CSI0_DAT9 = 49,
+	MX53_PAD_CSI0_DAT10 = 50,
+	MX53_PAD_CSI0_DAT11 = 51,
+	MX53_PAD_CSI0_DAT12 = 52,
+	MX53_PAD_CSI0_DAT13 = 53,
+	MX53_PAD_CSI0_DAT14 = 54,
+	MX53_PAD_CSI0_DAT15 = 55,
+	MX53_PAD_CSI0_DAT16 = 56,
+	MX53_PAD_CSI0_DAT17 = 57,
+	MX53_PAD_CSI0_DAT18 = 58,
+	MX53_PAD_CSI0_DAT19 = 59,
+	MX53_PAD_EIM_A25 = 60,
+	MX53_PAD_EIM_EB2 = 61,
+	MX53_PAD_EIM_D16 = 62,
+	MX53_PAD_EIM_D17 = 63,
+	MX53_PAD_EIM_D18 = 64,
+	MX53_PAD_EIM_D19 = 65,
+	MX53_PAD_EIM_D20 = 66,
+	MX53_PAD_EIM_D21 = 67,
+	MX53_PAD_EIM_D22 = 68,
+	MX53_PAD_EIM_D23 = 69,
+	MX53_PAD_EIM_EB3 = 70,
+	MX53_PAD_EIM_D24 = 71,
+	MX53_PAD_EIM_D25 = 72,
+	MX53_PAD_EIM_D26 = 73,
+	MX53_PAD_EIM_D27 = 74,
+	MX53_PAD_EIM_D28 = 75,
+	MX53_PAD_EIM_D29 = 76,
+	MX53_PAD_EIM_D30 = 77,
+	MX53_PAD_EIM_D31 = 78,
+	MX53_PAD_EIM_A24 = 79,
+	MX53_PAD_EIM_A23 = 80,
+	MX53_PAD_EIM_A22 = 81,
+	MX53_PAD_EIM_A21 = 82,
+	MX53_PAD_EIM_A20 = 83,
+	MX53_PAD_EIM_A19 = 84,
+	MX53_PAD_EIM_A18 = 85,
+	MX53_PAD_EIM_A17 = 86,
+	MX53_PAD_EIM_A16 = 87,
+	MX53_PAD_EIM_CS0 = 88,
+	MX53_PAD_EIM_CS1 = 89,
+	MX53_PAD_EIM_OE = 90,
+	MX53_PAD_EIM_RW = 91,
+	MX53_PAD_EIM_LBA = 92,
+	MX53_PAD_EIM_EB0 = 93,
+	MX53_PAD_EIM_EB1 = 94,
+	MX53_PAD_EIM_DA0 = 95,
+	MX53_PAD_EIM_DA1 = 96,
+	MX53_PAD_EIM_DA2 = 97,
+	MX53_PAD_EIM_DA3 = 98,
+	MX53_PAD_EIM_DA4 = 99,
+	MX53_PAD_EIM_DA5 = 100,
+	MX53_PAD_EIM_DA6 = 101,
+	MX53_PAD_EIM_DA7 = 102,
+	MX53_PAD_EIM_DA8 = 103,
+	MX53_PAD_EIM_DA9 = 104,
+	MX53_PAD_EIM_DA10 = 105,
+	MX53_PAD_EIM_DA11 = 106,
+	MX53_PAD_EIM_DA12 = 107,
+	MX53_PAD_EIM_DA13 = 108,
+	MX53_PAD_EIM_DA14 = 109,
+	MX53_PAD_EIM_DA15 = 110,
+	MX53_PAD_NANDF_WE_B = 111,
+	MX53_PAD_NANDF_RE_B = 112,
+	MX53_PAD_EIM_WAIT = 113,
+	MX53_PAD_LVDS1_TX3_P = 114,
+	MX53_PAD_LVDS1_TX2_P = 115,
+	MX53_PAD_LVDS1_CLK_P = 116,
+	MX53_PAD_LVDS1_TX1_P = 117,
+	MX53_PAD_LVDS1_TX0_P = 118,
+	MX53_PAD_LVDS0_TX3_P = 119,
+	MX53_PAD_LVDS0_CLK_P = 120,
+	MX53_PAD_LVDS0_TX2_P = 121,
+	MX53_PAD_LVDS0_TX1_P = 122,
+	MX53_PAD_LVDS0_TX0_P = 123,
+	MX53_PAD_GPIO_10 = 124,
+	MX53_PAD_GPIO_11 = 125,
+	MX53_PAD_GPIO_12 = 126,
+	MX53_PAD_GPIO_13 = 127,
+	MX53_PAD_GPIO_14 = 128,
+	MX53_PAD_NANDF_CLE = 129,
+	MX53_PAD_NANDF_ALE = 130,
+	MX53_PAD_NANDF_WP_B = 131,
+	MX53_PAD_NANDF_RB0 = 132,
+	MX53_PAD_NANDF_CS0 = 133,
+	MX53_PAD_NANDF_CS1 = 134,
+	MX53_PAD_NANDF_CS2 = 135,
+	MX53_PAD_NANDF_CS3 = 136,
+	MX53_PAD_FEC_MDIO = 137,
+	MX53_PAD_FEC_REF_CLK = 138,
+	MX53_PAD_FEC_RX_ER = 139,
+	MX53_PAD_FEC_CRS_DV = 140,
+	MX53_PAD_FEC_RXD1 = 141,
+	MX53_PAD_FEC_RXD0 = 142,
+	MX53_PAD_FEC_TX_EN = 143,
+	MX53_PAD_FEC_TXD1 = 144,
+	MX53_PAD_FEC_TXD0 = 145,
+	MX53_PAD_FEC_MDC = 146,
+	MX53_PAD_PATA_DIOW = 147,
+	MX53_PAD_PATA_DMACK = 148,
+	MX53_PAD_PATA_DMARQ = 149,
+	MX53_PAD_PATA_BUFFER_EN = 150,
+	MX53_PAD_PATA_INTRQ = 151,
+	MX53_PAD_PATA_DIOR = 152,
+	MX53_PAD_PATA_RESET_B = 153,
+	MX53_PAD_PATA_IORDY = 154,
+	MX53_PAD_PATA_DA_0 = 155,
+	MX53_PAD_PATA_DA_1 = 156,
+	MX53_PAD_PATA_DA_2 = 157,
+	MX53_PAD_PATA_CS_0 = 158,
+	MX53_PAD_PATA_CS_1 = 159,
+	MX53_PAD_PATA_DATA0 = 160,
+	MX53_PAD_PATA_DATA1 = 161,
+	MX53_PAD_PATA_DATA2 = 162,
+	MX53_PAD_PATA_DATA3 = 163,
+	MX53_PAD_PATA_DATA4 = 164,
+	MX53_PAD_PATA_DATA5 = 165,
+	MX53_PAD_PATA_DATA6 = 166,
+	MX53_PAD_PATA_DATA7 = 167,
+	MX53_PAD_PATA_DATA8 = 168,
+	MX53_PAD_PATA_DATA9 = 169,
+	MX53_PAD_PATA_DATA10 = 170,
+	MX53_PAD_PATA_DATA11 = 171,
+	MX53_PAD_PATA_DATA12 = 172,
+	MX53_PAD_PATA_DATA13 = 173,
+	MX53_PAD_PATA_DATA14 = 174,
+	MX53_PAD_PATA_DATA15 = 175,
+	MX53_PAD_SD1_DATA0 = 176,
+	MX53_PAD_SD1_DATA1 = 177,
+	MX53_PAD_SD1_CMD = 178,
+	MX53_PAD_SD1_DATA2 = 179,
+	MX53_PAD_SD1_CLK = 180,
+	MX53_PAD_SD1_DATA3 = 181,
+	MX53_PAD_SD2_CLK = 182,
+	MX53_PAD_SD2_CMD = 183,
+	MX53_PAD_SD2_DATA3 = 184,
+	MX53_PAD_SD2_DATA2 = 185,
+	MX53_PAD_SD2_DATA1 = 186,
+	MX53_PAD_SD2_DATA0 = 187,
+	MX53_PAD_GPIO_0 = 188,
+	MX53_PAD_GPIO_1 = 189,
+	MX53_PAD_GPIO_9 = 190,
+	MX53_PAD_GPIO_3 = 191,
+	MX53_PAD_GPIO_6 = 192,
+	MX53_PAD_GPIO_2 = 193,
+	MX53_PAD_GPIO_4 = 194,
+	MX53_PAD_GPIO_5 = 195,
+	MX53_PAD_GPIO_7 = 196,
+	MX53_PAD_GPIO_8 = 197,
+	MX53_PAD_GPIO_16 = 198,
+	MX53_PAD_GPIO_17 = 199,
+	MX53_PAD_GPIO_18 = 200,
 };
 
 /* imx53 register maps */
-- 
1.7.5.4




From arnd.bergmann at linaro.org  Mon Aug 13 10:52:08 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Mon, 13 Aug 2012 14:52:08 +0000
Subject: [PATCH v10 00/18] Introduce a led trigger for CPU activity and
 consolidate LED driver in ARM
In-Reply-To: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
References: <1344837102-11850-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <201208131452.08879.arnd.bergmann@linaro.org>

On Monday 13 August 2012, Bryan Wu wrote:
> Based on Linus Walleij's ARM LED consolidation work, this patchset introduce a
> new generic led trigger for CPU not only for ARM but also for others.
> 
> For enabling CPU idle event, CPU arch code should call ledtrig_cpu() stub to
> trigger idle start or idle end event.
> 
> These patches convert old style LED driver in arch/arm to gpio_led or new led
> driver interface. Against 3.5 release and build successfully for all the machines.
> 
> Test ledtrig-cpu driver on OMAP4 Panda board.
> 
> Please find these patches here:
>        git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git for-arm-soc
> 

Pulled into the next/drivers branch again, and I verified that there
are no new build warnings or errors against v3.6-rc1 that are introduced
by this series. I got one simple merge conflict, see below for the
resolution.

Thanks for your persistence!

	Arnd

commit 19e4ab54e7f5fe46a3c931afa7e786f11d57b558
Merge: 0d7614f fa8bbb1
Author: Arnd Bergmann <arnd at arndb.de>
Date:   Mon Aug 13 16:45:48 2012 +0200

    Merge branch 'for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds into next/drivers
    
    From Bryan Wu <bryan.wu at canonical.com>:
    
    Based on Linus Walleij's ARM LED consolidation work, this patchset introduce a
    new generic led trigger for CPU not only for ARM but also for others.
    
    For enabling CPU idle event, CPU arch code should call ledtrig_cpu() stub to
    trigger idle start or idle end event.
    
    These patches convert old style LED driver in arch/arm to gpio_led or new led
    driver interface. Against 3.5 release and build successfully for all the machines.
    
    Test ledtrig-cpu driver on OMAP4 Panda board.
    
    v9 --> v10
     * fix compiling issue on versatile_defconfig reported by Russell King
     * rebase to 3.5 kernel and move patches to new git tree
    
    v8 --> v9:
     * use mutex to replace rw_sema pointed out by Tim Gardner
     * add a new struct led_trigger_cpu
     * add lock_is_inited to record mutex lock initialization
    
    v6 --> v7:
     * add a patch to unify the led-trigger name
     * fix some typo pointed
     * use BUG_ON to detect CPU numbers during building stage
    
    v5 --> v6:
     * replace  __get_cpu_var() to per_cpu()
     * remove smp_processor_id() which is wrong with for_each_possible_cpu()
     * test on real OMAP4 Panda board
     * add comments about CPU hotplug in the CPU LED trigger driver
    
    v4 --> v5:
     * rebase all the patches on top of latest linux-next
     * replace on_each_cpu() with for_each_possible_cpu()
     * add some description of ledtrig_cpu() API
     * remove old leds code from driver nwflash.c, which should use a new led trigger then
     * this trigger driver can be built as module now
    
    v3 --> v4:
     * fix a typo pointed by Jochen Friedrich
     * fix some building errors
     * add Reviewed-by and Tested-by into patch log
    
    v2 --> v3:
     * almost rewrote the whole ledtrig-cpu driver, which is more simple
     * every CPU will have a per-CPU trigger
     * cpu trigger can be assigned to any leds
     * fix a lockdep issue in led-trigger common code
     * other fix according to review
    
    v1 --> v2:
     * remove select operations in Kconfig of every machines
     * add back supporting of led in core module of mach-integrator
     * solidate name scheme in ledtrig-cpu.c
     * add comments of CPU_LED_* cpu led events
     * fold patches of RealView and Versatile together
     * add machine_is_ check during assabet led driver init
     * add some Acked-by in patch logs
     * remove code for simpad machine in machine-sa11000, since Jochen Friedrich
       introduced gpiolib and gpio-led driver for simpad
     * on Assabet and Netwinder machine, LED operations is reversed like:
       setting bit means turn off leds
       clearing bit means turn on leds
     * add a new function to read CM_CTRL register for led driver
    
    * 'for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds:
      ARM: use new LEDS CPU trigger stub to replace old one
      ARM: mach-sa1100: retire custom LED code
      ARM: mach-omap1: retire custom LED code
      ARM: mach-pnx4008: remove including old leds event API header file
      ARM: plat-samsung: remove including old leds event API header file
      ARM: mach-pxa: retire custom LED code
      char: nwflash: remove old led event code
      ARM: mach-footbridge: retire custom LED code
      ARM: mach-ebsa110: retire custom LED code
      ARM: mach-clps711x: retire custom LED code of P720T machine
      ARM: mach-integrator: retire custom LED code
      ARM: mach-integrator: move CM_CTRL to header file for accessing by other functions
      ARM: mach-orion5x: convert custom LED code to gpio_led and LED CPU trigger
      ARM: mach-shark: retire custom LED code
      ARM: mach-ks8695: remove leds driver, since nobody use it
      ARM: mach-realview and mach-versatile: retire custom LED code
      ARM: at91: convert old leds drivers to gpio_led and led_trigger drivers
      led-triggers: create a trigger for CPU activity
    
    Conflicts:
    	arch/arm/mach-clps711x/p720t.c
    	arch/arm/mach-sa1100/leds-cerf.c
    	arch/arm/mach-sa1100/leds-lart.c
    
    Let's hope this is the last time we pull this and it doesn't cause
    more trouble. I have verified that version 10 causes no build
    warnings or errors any more, and the patches still look good.
    
    Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --cc arch/arm/mach-clps711x/p720t.c
index f266d90,09113a9..b752b58
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@@ -101,19 -115,70 +105,77 @@@ static void __init p720t_init_early(voi
  	PLD_CODEC = 0;
  	PLD_TCH   = 0;
  	PLD_SPI   = 0;
 -#ifndef CONFIG_DEBUG_LL
 -	PLD_COM2  = 0;
 -	PLD_COM1  = 0;
 -#endif
 -
 -	return 0;
 +	if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
 +		PLD_COM2 = 0;
 +		PLD_COM1 = 0;
 +	}
  }
  
 -__initcall(p720t_hw_init);
 -
+ /*
+  * LED controled by CPLD
+  */
+ #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
+ static void p720t_led_set(struct led_classdev *cdev,
+ 			      enum led_brightness b)
+ {
+ 	u8 reg = clps_readb(PDDR);
+ 
+ 	if (b != LED_OFF)
+ 		reg |= 0x1;
+ 	else
+ 		reg &= ~0x1;
+ 
+ 	clps_writeb(reg, PDDR);
+ }
+ 
+ static enum led_brightness p720t_led_get(struct led_classdev *cdev)
+ {
+ 	u8 reg = clps_readb(PDDR);
+ 
+ 	return (reg & 0x1) ? LED_FULL : LED_OFF;
+ }
+ 
+ static int __init p720t_leds_init(void)
+ {
+ 
+ 	struct led_classdev *cdev;
+ 	int ret;
+ 
+ 	if (!machine_is_p720t())
+ 		return -ENODEV;
+ 
+ 	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+ 	if (!cdev)
+ 		return -ENOMEM;
+ 
+ 	cdev->name = "p720t:0";
+ 	cdev->brightness_set = p720t_led_set;
+ 	cdev->brightness_get = p720t_led_get;
+ 	cdev->default_trigger = "heartbeat";
+ 
+ 	ret = led_classdev_register(NULL, cdev);
+ 	if (ret	< 0) {
+ 		kfree(cdev);
+ 		return ret;
+ 	}
+ 
+ 	return 0;
+ }
+ 
+ /*
+  * Since we may have triggers on any subsystem, defer registration
+  * until after subsystem_init.
+  */
+ fs_initcall(p720t_leds_init);
+ #endif
++
 +MACHINE_START(P720T, "ARM-Prospector720T")
 +	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 +	.atag_offset	= 0x100,
 +	.fixup		= fixup_p720t,
 +	.init_early	= p720t_init_early,
 +	.map_io		= p720t_map_io,
 +	.init_irq	= clps711x_init_irq,
 +	.timer		= &clps711x_timer,
 +	.restart	= clps711x_restart,
 +MACHINE_END


From richard.genoud at gmail.com  Mon Aug 13 10:53:52 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 13 Aug 2012 16:53:52 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACQ1gAjPGcnOGh9iMxKUH1FA6rHBcuOzgR_A+wkbFWYkazQPxw@mail.gmail.com>

2012/8/10 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> This is also include the gpio controller as the IP share both.
> Each soc will have to describe the SoC limitation and pin configuration via
> DT.
>
> This will allow to do not need to touch the C code when adding new SoC if the
> IP version is supported.
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  .../bindings/pinctrl/atmel,at91-pinctrl.txt        |   84 ++
>  arch/arm/Kconfig                                   |    1 +
>  arch/arm/mach-at91/board-dt.c                      |    2 -
>  arch/arm/mach-at91/gpio.c                          |  165 +--
>  drivers/pinctrl/Kconfig                            |    9 +
>  drivers/pinctrl/Makefile                           |    1 +
>  drivers/pinctrl/pinctrl-at91.c                     | 1448 ++++++++++++++++++++
>  7 files changed, 1548 insertions(+), 162 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
>  create mode 100644 drivers/pinctrl/pinctrl-at91.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> new file mode 100644
> index 0000000..0296ef4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> @@ -0,0 +1,84 @@
> +* Atmel AT91 Pinmux Controller
> +
> +The AT91 Pinmux Controler, enables the IC
> +to share one PAD to several functional blocks. The sharing is done by
> +multiplexing the PAD input/output signals. For each PAD there are up to
> +8 muxing options (called periph modes). Since different modules require
> +different PAD settings (like pull up, keeper, etc) the contoller controls
> +also the PAD settings parameters.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +Atmel AT91 pin configuration node is a node of a group of pins which can be
> +used for a specific device or function. This node represents both mux and config
> +of the pins in that group. The 'pins' selects the function mode(also named pin
> +mode) this pin can work on and the 'config' configures various pad settings
> +such as pull-up, multi drive, etc.
> +
> +Required properties for iomux controller:
> +- compatible: "atmel,at91rm9200-pinctrl"
> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
> +  configured in this periph mode. All the periph and bank need to be describe.
> +
> +Required properties for pin configuration node:
> +- atmel,pins: 4 integers array, represents a group of pins mux and config
> +  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
> +  The PERIPH 0 means gpio.
> +
> +Bits used for CONFIG:
> +PULL_UP(1 << 0): indicate this pin need a pull up.
> +MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.
> +
> +NOTE:
> +Some requirements for using atmel,at91rm9200-pinctrl binding:
> +1. We have pin function node defined under at91 controller node to represent
> +   what pinmux functions this SoC supports.
> +2. The pin configuration node intends to work on a specific function should
> +   to be defined under that specific function node.
> +   The function node's name should represent well about what function
> +   this group of pins in this pin configuration node are working on.
> +3. The driver can use the function node's name and pin configuration node's
> +   name describe the pin function and group hierarchy.
> +   For example, Linux Iat91 pinctrl driver takes the function node's name
It seems to be a typo : Iat91

> +   as the function name and pin configuration node's name as group name to
> +   create the map table.
> +4. Each pin configuration node should have a phandle, devices can set pins
> +   configurations by referring to the phandle of that pin configuration node.
> +5. The gpio controller must be describe in the pinctrl simple-bus.
> +
> +Examples:
> +
> +pinctrl at fffff400 {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       ranges;
> +       compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +       reg = <0xfffff400 0x600>;
> +
> +       atmel,mux-mask = <
> +             /*    A         B     */
> +              0xffffffff 0xffc00c3b  /* pioA */
> +              0xffffffff 0x7fff3ccf  /* pioB */
> +              0xffffffff 0x007fffff  /* pioC */
> +             >;
> +
> +       /* shared pinctrl settings */
> +       dbgu {
> +               pinctrl_dbgu: dbgu-0 {
> +                       atmel,pins =
> +                               <1 14 0x1 0x0   /* PB14 periph A */
> +                                1 15 0x1 0x1>; /* PB15 periph with pullup */
> +               };
> +       };
> +};
> +
> +dbgu: serial at fffff200 {
> +       compatible = "atmel,at91sam9260-usart";
> +       reg = <0xfffff200 0x200>;
> +       interrupts = <1 4 7>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_dbgu>;
> +       status = "disabled";
> +};
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..178a619 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -352,6 +352,7 @@ config ARCH_AT91
>         select CLKDEV_LOOKUP
>         select IRQ_DOMAIN
>         select NEED_MACH_IO_H if PCCARD
> +       select PINCTRL
>         help
>           This enables support for systems based on Atmel
>           AT91RM9200 and AT91SAM9* processors.
There's a problem with this: if CONFIG_PINCRTL is forced on ARCH_AT91
and PINCTRL_AT91 is not selected,
all calls to devm_pinctrl_get_select_default() will fail. => no
serial, no nand etc..
IMHO, CONFIG_PINCTRL should not be forced, otherwise it will break
configs that don't want pinctrl
Or, if pinctrl is the new and only way, PINCTRL_AT91 should also be
forced on ARCH_AT91

> diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
> index e8f45c4..3b6a948 100644
> --- a/arch/arm/mach-at91/board-dt.c
> +++ b/arch/arm/mach-at91/board-dt.c
> @@ -30,8 +30,6 @@
>  static const struct of_device_id irq_of_match[] __initconst = {
>
>         { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
> -       { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
> -       { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
>         { /*sentinel*/ }
>  };
>
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index 8b476fd..67d7fab 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -23,8 +23,6 @@
>  #include <linux/io.h>
>  #include <linux/irqdomain.h>
>  #include <linux/of_address.h>
> -#include <linux/of_irq.h>
> -#include <linux/of_gpio.h>
>
>  #include <asm/mach/irq.h>
>
> @@ -719,80 +717,6 @@ postcore_initcall(at91_gpio_debugfs_init);
>   */
>  static struct lock_class_key gpio_lock_class;
>
> -#if defined(CONFIG_OF)
> -static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
> -                                                       irq_hw_number_t hw)
> -{
> -       struct at91_gpio_chip   *at91_gpio = h->host_data;
> -
> -       irq_set_lockdep_class(virq, &gpio_lock_class);
> -
> -       /*
> -        * Can use the "simple" and not "edge" handler since it's
> -        * shorter, and the AIC handles interrupts sanely.
> -        */
> -       irq_set_chip_and_handler(virq, &gpio_irqchip,
> -                                handle_simple_irq);
> -       set_irq_flags(virq, IRQF_VALID);
> -       irq_set_chip_data(virq, at91_gpio);
> -
> -       return 0;
> -}
> -
> -static struct irq_domain_ops at91_gpio_ops = {
> -       .map    = at91_gpio_irq_map,
> -       .xlate  = irq_domain_xlate_twocell,
> -};
> -
> -int __init at91_gpio_of_irq_setup(struct device_node *node,
> -                                    struct device_node *parent)
> -{
> -       struct at91_gpio_chip   *prev = NULL;
> -       int                     alias_idx = of_alias_get_id(node, "gpio");
> -       struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
> -
> -       /* Setup proper .irq_set_type function */
> -       if (has_pio3())
> -               gpio_irqchip.irq_set_type = alt_gpio_irq_type;
> -       else
> -               gpio_irqchip.irq_set_type = gpio_irq_type;
> -
> -       /* Disable irqs of this PIO controller */
> -       __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
> -
> -       /* Setup irq domain */
> -       at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
> -                                               &at91_gpio_ops, at91_gpio);
> -       if (!at91_gpio->domain)
> -               panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
> -                       at91_gpio->pioc_idx);
> -
> -       /* Setup chained handler */
> -       if (at91_gpio->pioc_idx)
> -               prev = &gpio_chip[at91_gpio->pioc_idx - 1];
> -
> -       /* The toplevel handler handles one bank of GPIOs, except
> -        * on some SoC it can handles up to three...
> -        * We only set up the handler for the first of the list.
> -        */
> -       if (prev && prev->next == at91_gpio)
> -               return 0;
> -
> -       at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
> -                                                       at91_gpio->pioc_hwirq);
> -       irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
> -       irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
> -
> -       return 0;
> -}
> -#else
> -int __init at91_gpio_of_irq_setup(struct device_node *node,
> -                                    struct device_node *parent)
> -{
> -       return -EINVAL;
> -}
> -#endif
> -
>  /*
>   * irqdomain initialization: pile up irqdomains on top of AIC range
>   */
> @@ -996,85 +920,6 @@ err:
>         return -EINVAL;
>  }
>
> -#ifdef CONFIG_OF_GPIO
> -static void __init of_at91_gpio_init_one(struct device_node *np)
> -{
> -       int alias_idx;
> -       struct at91_gpio_chip *at91_gpio;
> -       uint32_t ngpio;
> -
> -       if (!np)
> -               return;
> -
> -       alias_idx = of_alias_get_id(np, "gpio");
> -       if (alias_idx >= MAX_GPIO_BANKS) {
> -               pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
> -                                               alias_idx, MAX_GPIO_BANKS);
> -               return;
> -       }
> -
> -       at91_gpio = &gpio_chip[alias_idx];
> -       at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
> -
> -       at91_gpio->regbase = of_iomap(np, 0);
> -       if (!at91_gpio->regbase) {
> -               pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
> -                                                               alias_idx);
> -               return;
> -       }
> -
> -       /* Get the interrupts property */
> -       if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
> -               pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
> -                                                               alias_idx);
> -               goto ioremap_err;
> -       }
> -
> -       /* Get capabilities from compatibility property */
> -       if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
> -               at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
> -
> -       if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
> -               if (ngpio >= MAX_NB_GPIO_PER_BANK)
> -                       pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
> -                              alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
> -               else
> -                       at91_gpio->chip.ngpio = ngpio;
> -       }
> -
> -       /* Setup clock */
> -       if (at91_gpio_setup_clk(alias_idx))
> -               goto ioremap_err;
> -
> -       at91_gpio->chip.of_node = np;
> -       gpio_banks = max(gpio_banks, alias_idx + 1);
> -       at91_gpio->pioc_idx = alias_idx;
> -       return;
> -
> -ioremap_err:
> -       iounmap(at91_gpio->regbase);
> -}
> -
> -static int __init of_at91_gpio_init(void)
> -{
> -       struct device_node *np = NULL;
> -
> -       /*
> -        * This isn't ideal, but it gets things hooked up until this
> -        * driver is converted into a platform_device
> -        */
> -       for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
> -               of_at91_gpio_init_one(np);
> -
> -       return gpio_banks > 0 ? 0 : -EINVAL;
> -}
> -#else
> -static int __init of_at91_gpio_init(void)
> -{
> -       return -EINVAL;
> -}
> -#endif
> -
>  static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
>  {
>         struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
> @@ -1109,11 +954,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
>
>         BUG_ON(nr_banks > MAX_GPIO_BANKS);
>
> -       if (of_at91_gpio_init() < 0) {
> -               /* No GPIO controller found in device tree */
> -               for (i = 0; i < nr_banks; i++)
> -                       at91_gpio_init_one(i, data[i].regbase, data[i].id);
> -       }
> +       if (of_have_populated_dt())
> +               return;
> +
> +       for (i = 0; i < nr_banks; i++)
> +               at91_gpio_init_one(i, data[i].regbase, data[i].id);
>
>         for (i = 0; i < gpio_banks; i++) {
>                 at91_gpio = &gpio_chip[i];
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 54e3588..953932a 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -26,6 +26,15 @@ config DEBUG_PINCTRL
>         help
>           Say Y here to add some extra checks and diagnostics to PINCTRL calls.
>
> +config PINCTRL_AT91
> +       bool "AT91 pinctrl driver"
> +       depends on OF
> +       depends on ARCH_AT91
> +       select PINMUX
> +       select PINCONF
> +       help
> +         Say Y here to enable the at91 pinctrl driver
> +
>  config PINCTRL_IMX
>         bool
>         select PINMUX
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index f40b1f8..d3fda00 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
>  obj-$(CONFIG_PINCTRL)          += devicetree.o
>  endif
>  obj-$(CONFIG_GENERIC_PINCONF)  += pinconf-generic.o
> +obj-$(CONFIG_PINCTRL_AT91)     += pinctrl-at91.o
>  obj-$(CONFIG_PINCTRL_IMX)      += pinctrl-imx.o
>  obj-$(CONFIG_PINCTRL_IMX51)    += pinctrl-imx51.o
>  obj-$(CONFIG_PINCTRL_IMX53)    += pinctrl-imx53.o
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> new file mode 100644
> index 0000000..540943b
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -0,0 +1,1448 @@
> +/*
> + * at91 pinctrl driver based on at91 pinmux core
> + *
> + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
> + * <plagnioj at jcrosoft.com>
> + *
> + * Under GPLv2 only
> + */
> +
> +#define DEBUG
Please remove that, it's already handled in CONFIG_DEBUG_PINCTRL option.

> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +#include <linux/irqdomain.h>
> +#include <linux/pinctrl/machine.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +/* Since we request GPIOs from ourself */
> +#include <linux/pinctrl/consumer.h>
> +
> +#include <asm/mach/irq.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/at91_pio.h>
> +
> +#include "core.h"
> +
> +#define MAX_NB_GPIO_PER_BANK   32
This can be factorized with the same define in arch/arm/mach-at91/gpio.c

> +
> +struct at91_gpio_chip {
> +       struct gpio_chip        chip;
> +       struct pinctrl_gpio_range range;
> +       struct at91_gpio_chip   *next;          /* Bank sharing same clock */
> +       int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
> +       int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
> +       int                     pioc_idx;       /* PIO bank index */
> +       void __iomem            *regbase;       /* PIO bank virtual address */
> +       struct clk              *clock;         /* associated clock */
> +       struct irq_domain       *domain;        /* associated irq domain */
> +};
> +
> +#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
> +
> +static struct at91_gpio_chip *gpio_chip[MAX_GPIO_BANKS];
> +
> +static int gpio_banks;
> +static unsigned long at91_gpio_caps;
> +
> +/* All PIO controllers support PIO3 features */
> +#define AT91_GPIO_CAP_PIO3     (1 <<  0)
> +
> +#define has_pio3()     (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
> +
> +
> +#define PULL_UP                (0 << 1)
> +#define MULTI_DRIVE    (1 << 1)
> +
> +/**
> + * struct at91_pmx_func - describes AT91 pinmux functions
> + * @name: the name of this specific function
> + * @groups: corresponding pin groups
> + * @ngroups: the number of groups
> + */
> +struct at91_pmx_func {
> +       const char *name;
> +       const char **groups;
> +       unsigned ngroups;
> +};
> +
> +struct at91_pmx_pin {
> +       uint32_t bank;
> +       uint32_t pin;
> +       uint32_t mux;
> +       uint32_t pullup;
> +       unsigned long conf;
> +};
> +
> +/**
> + * struct at91_pin_group - describes an At91 pin group
> + * @name: the name of this specific pin group
> + * @pins: an array of discrete physical pins used in this group, taken
> + *     from the driver-local pin enumeration space
> + * @npins: the number of pins in this group array, i.e. the number of
> + *     elements in .pins so we can iterate over that array
> + */
> +struct at91_pin_group {
> +       const char *name;
> +       struct at91_pmx_pin *pins_conf;
> +       unsigned int *pins;
> +       unsigned npins;
> +};
> +
> +struct at91_pinctrl {
> +       struct device *dev;
> +       struct pinctrl_dev *pctl;
> +
> +       int nbanks;
> +
> +       int nmux;
> +       uint32_t *mux_mask;
> +
> +       struct at91_pmx_func *functions;
> +       int nfunctions;
> +
> +       struct at91_pin_group *groups;
> +       int ngroups;
> +
> +       void (*set_A_periph)(void __iomem *pio, unsigned mask);
> +       void (*set_B_periph)(void __iomem *pio, unsigned mask);
> +};
> +
> +static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
> +                               const struct at91_pinctrl *info,
> +                               const char *name)
> +{
> +       const struct at91_pin_group *grp = NULL;
> +       int i;
> +
> +       for (i = 0; i < info->ngroups; i++) {
> +               if (strcmp(info->groups[i].name, name))
> +                       continue;
> +
> +               grp = &info->groups[i];
> +               dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
> +               break;
> +       }
> +
> +       return grp;
> +}
> +
> +static int at91_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       return info->ngroups;
> +}
> +
> +static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
> +                                      unsigned selector)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       return info->groups[selector].name;
> +}
> +
> +static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
> +                              const unsigned **pins,
> +                              unsigned *npins)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       if (selector >= info->ngroups)
> +               return -EINVAL;
> +
> +       *pins = info->groups[selector].pins;
> +       *npins = info->groups[selector].npins;
> +
> +       return 0;
> +}
> +
> +static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
> +                  unsigned offset)
> +{
> +       seq_printf(s, "%s", dev_name(pctldev->dev));
> +}
> +
> +static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
> +                       struct device_node *np,
> +                       struct pinctrl_map **map, unsigned *num_maps)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       const struct at91_pin_group *grp;
> +       struct pinctrl_map *new_map;
> +       struct device_node *parent;
> +       int map_num = 1;
> +       int i;
> +       struct at91_pmx_pin *pin;
> +
> +       /*
> +        * first find the group of this node and check if we need create
> +        * config maps for pins
> +        */
> +       grp = at91_pinctrl_find_group_by_name(info, np->name);
> +       if (!grp) {
> +               dev_err(info->dev, "unable to find group for node %s\n",
> +                       np->name);
> +               return -EINVAL;
> +       }
> +
> +       map_num += grp->npins;
> +       new_map = kmalloc(sizeof(*new_map) * map_num, GFP_KERNEL);
> +       if (!new_map)
> +               return -ENOMEM;
> +
> +       *map = new_map;
> +       *num_maps = map_num;
> +
> +       /* create mux map */
> +       parent = of_get_parent(np);
> +       if (!parent) {
> +               kfree(new_map);
> +               return -EINVAL;
> +       }
> +       new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
> +       new_map[0].data.mux.function = parent->name;
> +       new_map[0].data.mux.group = np->name;
> +       of_node_put(parent);
> +
> +       /* create config map */
> +       new_map++;
> +       for (i = 0; i < grp->npins; i++) {
> +               pin = &grp->pins_conf[i];
> +
> +               new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
> +               new_map[i].data.configs.group_or_pin =
> +                               pin_get_name(pctldev, grp->pins[i]);
> +               new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
> +               new_map[i].data.configs.num_configs = 1;
> +       }
> +
> +       dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
> +               (*map)->data.mux.function, (*map)->data.mux.group, map_num);
> +
> +       return 0;
> +}
> +
> +static void at91_dt_free_map(struct pinctrl_dev *pctldev,
> +                               struct pinctrl_map *map, unsigned num_maps)
> +{
> +       kfree(map);
> +}
> +
> +static struct pinctrl_ops at91_pctrl_ops = {
> +       .get_groups_count = at91_get_groups_count,
> +       .get_group_name = at91_get_group_name,
> +       .get_group_pins = at91_get_group_pins,
> +       .pin_dbg_show = at91_pin_dbg_show,
> +       .dt_node_to_map = at91_dt_node_to_map,
> +       .dt_free_map = at91_dt_free_map,
> +
> +};
> +
> +static void __iomem * pin_to_controller(struct at91_pinctrl *info,
> +                                unsigned int bank)
> +{
> +       return gpio_chip[bank]->regbase;
> +}
> +
> +static inline int pin_to_bank(unsigned pin)
> +{
> +       return pin /= MAX_NB_GPIO_PER_BANK;
> +}
> +
> +static unsigned pin_to_mask(unsigned int pin)
> +{
> +       return 1 << pin;
> +}
> +
> +static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_IDR);
> +}
> +
> +static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
> +{
> +       return (__raw_readl(pio + PIO_PUSR) >> pin) & 0x1;
> +}
> +
> +static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, unsigned on)
> +{
> +       __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
> +}
> +
> +static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
> +{
> +       return (__raw_readl(pio + PIO_MDSR) >> pin) & 0x1;
> +}
> +
> +static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, unsigned on)
> +{
> +       __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
> +}
> +
> +static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
> +{
> +
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
> +                                               pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> +                                               pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
> +                                               pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> +                                               pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_ASR);
> +}
> +
> +static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_BSR);
> +}
> +
> +static void at91_mux_set_C_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_set_D_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
> +{
> +       if (pin->mux) {
> +               dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
> +                       pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
> +       } else {
> +               dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
> +                       pin->bank + 'A', pin->pin, pin->conf);
> +       }
> +}
> +
> +static int pin_check_config(struct at91_pinctrl *info, const char* name,
> +                           int index, const struct at91_pmx_pin *pin)
> +{
> +       int mux;
> +
> +       /* check if it's a valid config */
> +       if (pin->bank >= info->nbanks) {
> +               dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
> +                       name, index, pin->bank, info->nbanks);
> +               return -EINVAL;
> +       }
> +
> +       if (pin->pin >= 32) {
> +               dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= 32\n",
> +                       name, index, pin->pin);
> +               return -EINVAL;
> +       }
> +
> +       if (!pin->mux)
> +               return 0;
> +
> +       mux = pin->mux - 1;
> +
> +       if (mux >= info->nmux) {
> +               dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
> +                       name, index, mux, info->nmux);
> +               return -EINVAL;
> +       }
> +
> +       if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
> +               dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
> +                       name, index, mux, pin->bank + 'A', pin->pin);
> +               return -EINVAL;
> +       }
> +
> +       return 0;
> +}
> +
> +static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_PDR);
> +}
> +
> +static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, unsigned input)
> +{
> +       __raw_writel(mask, pio + PIO_PER);
> +       __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
> +}
> +
> +static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
> +                          unsigned group)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
> +       const struct at91_pmx_pin *pin;
> +       uint32_t npins = info->groups[group].npins;
> +       int i, ret;
> +       unsigned mask;
> +       void __iomem *pio;
> +
> +       dev_dbg(info->dev, "enable function %s group %s\n",
> +               info->functions[selector].name, info->groups[group].name);
> +
> +       /* first check that all the pins of the group are valid with a valid
> +        * paramter */
> +       for (i = 0; i < npins; i++) {
> +               pin = &pins_conf[i];
> +               ret = pin_check_config(info, info->groups[group].name, i, pin);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       for (i = 0; i < npins; i++) {
> +               pin = &pins_conf[i];
> +               at91_pin_dbg(info->dev, pin);
> +               pio = pin_to_controller(info, pin->bank);
> +               mask = pin_to_mask(pin->pin);
> +               at91_mux_disable_interrupt(pio, mask);
> +               switch(pin->mux) {
> +               case 0:
> +                       at91_mux_gpio_enable(pio, mask, 1);
> +                       break;
> +               case 1:
> +                       info->set_A_periph(pio, mask);
> +                       break;
> +               case 2:
> +                       info->set_B_periph(pio, mask);
> +                       break;
> +               case 3:
> +                       at91_mux_set_C_periph(pio, mask);
> +                       break;
> +               case 4:
> +                       at91_mux_set_D_periph(pio, mask);
> +                       break;
> +               }
> +               if (pin->mux)
> +                       at91_mux_gpio_disable(pio, mask);
> +       }
> +
> +       return 0;
> +}
> +
> +static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
> +                          unsigned group)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
> +       const struct at91_pmx_pin *pin;
> +       uint32_t npins = info->groups[group].npins;
> +       int i;
> +       unsigned mask;
> +       void __iomem *pio;
> +
> +       for (i = 0; i < npins; i++) {
> +               pin = &pins_conf[i];
> +               at91_pin_dbg(info->dev, pin);
> +               pio = pin_to_controller(info, pin->bank);
> +               mask = pin_to_mask(pin->pin);
> +               at91_mux_gpio_enable(pio, mask, 1);
> +       }
> +}
> +
> +static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       return info->nfunctions;
> +}
> +
> +static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
> +                                         unsigned selector)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       return info->functions[selector].name;
> +}
> +
> +static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
> +                              const char * const **groups,
> +                              unsigned * const num_groups)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +
> +       *groups = info->functions[selector].groups;
> +       *num_groups = info->functions[selector].ngroups;
> +
> +       return 0;
> +}
> +
> +int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
> +                           struct pinctrl_gpio_range *range,
> +                           unsigned offset)
> +{
> +       struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
> +       struct at91_gpio_chip *at91_chip;
> +       struct gpio_chip *chip;
> +       unsigned mask;
> +
> +       if (!range) {
> +               dev_err(npct->dev, "invalid range\n");
> +               return -EINVAL;
> +       }
> +       if (!range->gc) {
> +               dev_err(npct->dev, "missing GPIO chip in range\n");
> +               return -EINVAL;
> +       }
> +       chip = range->gc;
> +       at91_chip = container_of(chip, struct at91_gpio_chip, chip);
> +
> +       dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
> +
> +       mask = 1 << (offset - chip->base);
> +
> +       dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
> +               offset, 'A' + range->id, offset - chip->base, mask);
> +
> +       __raw_writel(mask, at91_chip->regbase + PIO_PER);
> +
> +       return 0;
> +}
> +
> +void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
> +                          struct pinctrl_gpio_range *range,
> +                          unsigned offset)
> +{
> +       struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
> +
> +       dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
> +       /* Set the pin to some default state, GPIO is usually default */
> +}
> +
> +static struct pinmux_ops at91_pmx_ops = {
> +       .get_functions_count = at91_pmx_get_funcs_count,
> +       .get_function_name = at91_pmx_get_func_name,
> +       .get_function_groups = at91_pmx_get_groups,
> +       .enable = at91_pmx_enable,
> +       .disable = at91_pmx_disable,
> +       .gpio_request_enable = at91_gpio_request_enable,
> +       .gpio_disable_free = at91_gpio_disable_free,
> +};
> +
> +static int at91_pinconf_get(struct pinctrl_dev *pctldev,
> +                            unsigned pin_id, unsigned long *config)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       void __iomem *pio;
> +       unsigned pin;
> +
> +       dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
> +       pio = pin_to_controller(info, pin_to_bank(pin_id));
> +       pin = pin_id % MAX_NB_GPIO_PER_BANK;
> +
> +       if (at91_mux_get_multidrive(pio, pin))
> +               *config |= MULTI_DRIVE;
> +
> +       if (at91_mux_get_pullup(pio, pin))
> +               *config |= PULL_UP;
> +
> +       return 0;
> +}
> +
> +static int at91_pinconf_set(struct pinctrl_dev *pctldev,
> +                            unsigned pin_id, unsigned long config)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       unsigned mask;
> +       void __iomem *pio;
> +
> +       dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, config);
> +       pio = pin_to_controller(info, pin_to_bank(pin_id));
> +       mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
> +
> +       at91_mux_set_pullup(pio, mask, config & PULL_UP);
> +       at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
> +       return 0;
> +}
> +
> +static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> +                                  struct seq_file *s, unsigned pin_id)
> +{
> +
> +}
> +
> +static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
> +                                        struct seq_file *s, unsigned group)
> +{
> +}
> +
> +struct pinconf_ops at91_pinconf_ops = {
> +       .pin_config_get = at91_pinconf_get,
> +       .pin_config_set = at91_pinconf_set,
> +       .pin_config_dbg_show = at91_pinconf_dbg_show,
> +       .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
> +};
> +
> +static struct pinctrl_desc at91_pinctrl_desc = {
> +       .pctlops = &at91_pctrl_ops,
> +       .pmxops = &at91_pmx_ops,
> +       .confops = &at91_pinconf_ops,
> +       .owner = THIS_MODULE,
> +};
> +
> +static const char *gpio_compat = "atmel,at91rm9200-gpio";
> +
> +static void __devinit at91_pinctrl_child_count(struct at91_pinctrl *info,
> +                                             struct device_node *np)
> +{
> +       struct device_node *child;
> +
> +       for_each_child_of_node(np, child) {
> +               if (of_device_is_compatible(child, gpio_compat)) {
> +                       info->nbanks++;
> +               } else {
> +                       info->nfunctions++;
> +                       info->ngroups += of_get_child_count(child);
> +               }
> +       }
> +}
> +
> +static int __devinit at91_pinctrl_mux_mask(struct at91_pinctrl *info,
> +                                         struct device_node *np)
> +{
> +       int ret = 0;
> +       int size;
> +       const const __be32 *list;
> +
> +       list = of_get_property(np, "atmel,mux-mask", &size);
> +       if (!list) {
> +               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
> +               return -EINVAL;
> +       }
> +
> +       size /= sizeof(*list);
> +       if (!size || size % info->nbanks) {
> +               dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
> +               return -EINVAL;
> +       }
> +       info->nmux = size / info->nbanks;
> +
> +       info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
> +       if (!info->mux_mask) {
> +               dev_err(info->dev, "could not alloc mux_mask\n");
> +               return -ENOMEM;
> +       }
> +
> +       ret = of_property_read_u32_array(np, "atmel,mux-mask",
> +                                         info->mux_mask, size);
> +       if (ret)
> +               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
> +       return ret;
> +}
> +
> +static int __devinit at91_pinctrl_parse_groups(struct device_node *np,
> +                               struct at91_pin_group *grp,
> +                               struct at91_pinctrl *info,
> +                               u32 index)
> +{
> +       struct at91_pmx_pin *pin;
> +       int size;
> +       const const __be32 *list;
> +       int i, j;
> +
> +       dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
> +
> +       /* Initialise group */
> +       grp->name = np->name;
> +
> +       /*
> +        * the binding format is fsl,pins = <bank pin mux CONFIG ...>,
> +        * do sanity check and calculate pins number
> +        */
> +       list = of_get_property(np, "atmel,pins", &size);
> +       /* we do not check return since it's safe node passed down */
> +       size /= sizeof(*list);
> +       if (!size || size % 4) {
> +               dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
> +               return -EINVAL;
> +       }
> +
> +       grp->npins = size / 4;
> +       pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
> +                               GFP_KERNEL);
> +       grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
> +                               GFP_KERNEL);
> +       if (!grp->pins_conf || !grp->pins)
> +               return -ENOMEM;
> +
> +       for (i = 0, j = 0; i < size; i += 4, j++) {
> +               pin->bank = be32_to_cpu(*list++);
> +               pin->pin = be32_to_cpu(*list++);
> +               grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
> +               pin->mux = be32_to_cpu(*list++);
> +               pin->conf = be32_to_cpu(*list++);
> +
> +               at91_pin_dbg(info->dev, pin);
> +               pin++;
> +       }
> +
> +       return 0;
> +}
> +
> +static int __devinit at91_pinctrl_parse_functions(struct device_node *np,
> +                       struct at91_pinctrl *info, u32 index)
> +{
> +       struct device_node *child;
> +       struct at91_pmx_func *func;
> +       struct at91_pin_group *grp;
> +       int ret;
> +       static u32 grp_index;
> +       u32 i = 0;
> +
> +       dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
> +
> +       func = &info->functions[index];
> +
> +       /* Initialise function */
> +       func->name = np->name;
> +       func->ngroups = of_get_child_count(np);
> +       if (func->ngroups <= 0) {
> +               dev_err(info->dev, "no groups defined\n");
> +               return -EINVAL;
> +       }
> +       func->groups = devm_kzalloc(info->dev,
> +                       func->ngroups * sizeof(char *), GFP_KERNEL);
> +       if (!func->groups)
> +               return -ENOMEM;
> +
> +       for_each_child_of_node(np, child) {
> +               func->groups[i] = child->name;
> +               grp = &info->groups[grp_index++];
> +               ret = at91_pinctrl_parse_groups(child, grp, info, i++);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
> +                                          struct at91_pinctrl *info)
> +{
> +       int ret = 0;
> +       int i, j;
> +       uint32_t *tmp;
> +       struct device_node *np = pdev->dev.of_node;
> +       struct device_node *child;
> +
> +       if (!np)
> +               return -ENODEV;
> +
> +       info->dev = &pdev->dev;
> +       at91_pinctrl_child_count(info, np);
> +
> +       if (info->nbanks < 1) {
> +               dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
> +               return -EINVAL;
> +       }
> +
> +       ret = at91_pinctrl_mux_mask(info, np);
> +       if (ret)
> +               return ret;
> +
> +       dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
> +
> +       dev_dbg(&pdev->dev, "mux-mask\n");
> +       tmp = info->mux_mask;
> +       for (i = 0; i < info->nbanks; i++) {
> +               for (j = 0; j < info->nmux; j++, tmp++) {
> +                       dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
> +               }
> +       }
> +
> +       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
> +       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
> +       info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
> +                                       GFP_KERNEL);
> +       if (!info->functions)
> +               return -ENOMEM;
> +
> +       info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
> +                                       GFP_KERNEL);
> +       if (!info->groups)
> +               return -ENOMEM;
> +
> +       dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
> +       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
> +       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
> +
> +       i = 0;
> +
> +       for_each_child_of_node(np, child) {
> +               if (of_device_is_compatible(child, gpio_compat))
> +                       continue;
> +               ret = at91_pinctrl_parse_functions(child, info, i++);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "failed to parse function\n");
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int __devinit at91_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct at91_pinctrl *info;
> +       struct pinctrl_pin_desc *pdesc;
> +       int ret, i, j ,k;
> +
> +       info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
> +       if (!info)
> +               return -ENOMEM;
> +
> +       ret = at91_pinctrl_probe_dt(pdev, info);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * We need all the GPIO drivers to probe FIRST, or we will not be able
> +        * to obtain references to the struct gpio_chip * for them, and we
> +        * need this to proceed.
> +        */
> +       for (i = 0; i < info->nbanks; i++) {
> +               if (!gpio_chip[i]) {
> +                       dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
> +                       devm_kfree(&pdev->dev, info);
> +                       return -EPROBE_DEFER;
> +               }
> +       }
> +
> +       at91_pinctrl_desc.name = dev_name(&pdev->dev);
> +       at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
> +       at91_pinctrl_desc.pins = pdesc =
> +               devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
> +
> +       if (!at91_pinctrl_desc.pins)
> +               return -ENOMEM;
> +
> +       for (i = 0 , k = 0; i < info->nbanks; i++) {
> +               for (j = 0; j < 32; j++, k++) {
> +                       pdesc->number = k;
> +                       pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
> +                       pdesc++;
> +               }
> +       }
> +
> +       info->set_A_periph = at91_mux_pio3_set_A_periph;
> +       info->set_B_periph = at91_mux_pio3_set_B_periph;
> +
> +       if (has_pio3()) {
> +               info->set_A_periph = at91_mux_set_A_periph;
> +               info->set_B_periph = at91_mux_set_B_periph;
> +       }
> +
> +       platform_set_drvdata(pdev, info);
> +       info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
> +
> +       if (!info->pctl) {
> +               dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
> +               ret = -EINVAL;
> +               goto err;
> +       }
> +
> +       /* We will handle a range of GPIO pins */
> +       for (i = 0; i < info->nbanks; i++)
> +               pinctrl_add_gpio_range(info->pctl, &gpio_chip[i]->range);
> +
> +       dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
> +
> +       return 0;
> +
> +err:
> +       return ret;
> +}
> +
> +int __devexit at91_pinctrl_remove(struct platform_device *pdev)
> +{
> +       struct at91_pinctrl *info = platform_get_drvdata(pdev);
> +
> +       pinctrl_unregister(info->pctl);
> +
> +       return 0;
> +}
> +
> +static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
> +{
> +       /*
> +        * Map back to global GPIO space and request muxing, the direction
> +        * parameter does not matter for this controller.
> +        */
> +       int gpio = chip->base + offset;
> +       int bank = chip->base / chip->ngpio;
> +
> +       dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
> +                'A' + bank, offset, gpio);
> +
> +       return pinctrl_request_gpio(gpio);
> +}
> +
> +static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
> +{
> +       int gpio = chip->base + offset;
> +
> +       pinctrl_free_gpio(gpio);
> +}
> +
> +static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
> +{
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       void __iomem *pio = at91_gpio->regbase;
> +       unsigned mask = 1 << offset;
> +
> +       __raw_writel(mask, pio + PIO_ODR);
> +       return 0;
> +}
> +
> +static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
> +{
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       void __iomem *pio = at91_gpio->regbase;
> +       unsigned mask = 1 << offset;
> +       u32 pdsr;
> +
> +       pdsr = __raw_readl(pio + PIO_PDSR);
> +       return (pdsr & mask) != 0;
> +}
> +
> +static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
> +                               int val)
> +{
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       void __iomem *pio = at91_gpio->regbase;
> +       unsigned mask = 1 << offset;
> +
> +       __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
> +}
> +
> +static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
> +                               int val)
> +{
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       void __iomem *pio = at91_gpio->regbase;
> +       unsigned mask = 1 << offset;
> +
> +       __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
> +       __raw_writel(mask, pio + PIO_OER);
> +
> +       return 0;
> +}
> +
> +static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
> +{
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       int virq;
> +
> +       if (offset < chip->ngpio)
> +               virq = irq_create_mapping(at91_gpio->domain, offset);
> +       else
> +               virq = -ENXIO;
> +
> +       dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
> +                               chip->label, offset + chip->base, virq);
> +       return virq;
> +}
> +
> +static char peripheral_function(void __iomem *pio, unsigned mask)
> +{
> +       char    ret = 'X';
> +       u8      select;
> +
> +       if (!pio)
> +               return ret;
> +
> +       if (has_pio3()) {
> +               select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
> +               select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
> +               ret = 'A' + select;
> +       } else {
> +               ret = __raw_readl(pio + PIO_ABSR) & mask ?
> +                                               'B' : 'A';
> +       }
> +
> +       return ret;
> +}
> +
> +#ifdef CONFIG_DEBUG_FS
> +static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> +{
> +       int i;
> +       struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
> +       void __iomem *pio = at91_gpio->regbase;
> +
> +       for (i = 0; i < chip->ngpio; i++) {
> +               unsigned pin = chip->base + i;
> +               unsigned mask = pin_to_mask(pin);
> +               const char *gpio_label;
> +               u32 pdsr;
> +
> +               gpio_label = gpiochip_is_requested(chip, i);
> +               if (!gpio_label)
> +                       continue;
> +
> +               seq_printf(s, "[%s] GPIO%s%d: ",
> +                          gpio_label, chip->label, i);
> +               if (__raw_readl(pio + PIO_PSR) & mask) {
> +                       pdsr = __raw_readl(pio + PIO_PDSR);
> +
> +                       seq_printf(s, "[gpio] %s\n",
> +                                  pdsr & mask ?
> +                                  "set" : "clear");
> +               } else {
> +                       seq_printf(s, "[periph %c]\n",
> +                                  peripheral_function(pio, mask));
> +               }
> +       }
> +}
> +#else
> +#define at91_gpio_dbg_show     NULL
> +#endif
> +
> +/* Several AIC controller irqs are dispatched through this GPIO handler.
> + * To use any AT91_PIN_* as an externally triggered IRQ, first call
> + * at91_set_gpio_input() then maybe enable its glitch filter.
> + * Then just request_irq() with the pin ID; it works like any ARM IRQ
> + * handler.
> + * First implementation always triggers on rising and falling edges
> + * whereas the newer PIO3 can be additionally configured to trigger on
> + * level, edge with any polarity.
> + *
> + * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
> + * configuring them with at91_set_a_periph() or at91_set_b_periph().
> + * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
> + */
> +
> +static void gpio_irq_mask(struct irq_data *d)
> +{
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> +       void __iomem    *pio = at91_gpio->regbase;
> +       unsigned        mask = 1 << d->hwirq;
> +
> +       if (pio)
> +               __raw_writel(mask, pio + PIO_IDR);
> +}
> +
> +static void gpio_irq_unmask(struct irq_data *d)
> +{
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> +       void __iomem    *pio = at91_gpio->regbase;
> +       unsigned        mask = 1 << d->hwirq;
> +
> +       if (pio)
> +               __raw_writel(mask, pio + PIO_IER);
> +}
> +
> +static int gpio_irq_type(struct irq_data *d, unsigned type)
> +{
> +       switch (type) {
> +       case IRQ_TYPE_NONE:
> +       case IRQ_TYPE_EDGE_BOTH:
> +               return 0;
> +       default:
> +               return -EINVAL;
> +       }
> +}
> +
> +/* Alternate irq type for PIO3 support */
> +static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
> +{
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> +       void __iomem    *pio = at91_gpio->regbase;
> +       unsigned        mask = 1 << d->hwirq;
> +
> +       switch (type) {
> +       case IRQ_TYPE_EDGE_RISING:
> +               __raw_writel(mask, pio + PIO_ESR);
> +               __raw_writel(mask, pio + PIO_REHLSR);
> +               break;
> +       case IRQ_TYPE_EDGE_FALLING:
> +               __raw_writel(mask, pio + PIO_ESR);
> +               __raw_writel(mask, pio + PIO_FELLSR);
> +               break;
> +       case IRQ_TYPE_LEVEL_LOW:
> +               __raw_writel(mask, pio + PIO_LSR);
> +               __raw_writel(mask, pio + PIO_FELLSR);
> +               break;
> +       case IRQ_TYPE_LEVEL_HIGH:
> +               __raw_writel(mask, pio + PIO_LSR);
> +               __raw_writel(mask, pio + PIO_REHLSR);
> +               break;
> +       case IRQ_TYPE_EDGE_BOTH:
> +               /*
> +                * disable additional interrupt modes:
> +                * fall back to default behavior
> +                */
> +               __raw_writel(mask, pio + PIO_AIMDR);
> +               return 0;
> +       case IRQ_TYPE_NONE:
> +       default:
> +               pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
> +               return -EINVAL;
> +       }
> +
> +       /* enable additional interrupt modes */
> +       __raw_writel(mask, pio + PIO_AIMER);
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static u32 wakeups[MAX_GPIO_BANKS];
> +
> +static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
> +{
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> +       unsigned        mask = 1 << d->hwirq;
> +       unsigned        bank = at91_gpio->pioc_idx;
> +
> +       if (unlikely(bank >= MAX_GPIO_BANKS))
> +               return -EINVAL;
> +
> +       if (state)
> +               wakeups[bank] |= mask;
> +       else
> +               wakeups[bank] &= ~mask;
> +
> +       irq_set_irq_wake(at91_gpio->pioc_virq, state);
> +
> +       return 0;
> +}
> +#else
> +#define gpio_irq_set_wake      NULL
> +#endif
> +
> +static struct irq_chip gpio_irqchip = {
> +       .name           = "GPIO",
> +       .irq_disable    = gpio_irq_mask,
> +       .irq_mask       = gpio_irq_mask,
> +       .irq_unmask     = gpio_irq_unmask,
> +       /* .irq_set_type is set dynamically */
> +       .irq_set_wake   = gpio_irq_set_wake,
> +};
> +
> +static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
> +{
> +       struct irq_chip *chip = irq_desc_get_chip(desc);
> +       struct irq_data *idata = irq_desc_get_irq_data(desc);
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
> +       void __iomem    *pio = at91_gpio->regbase;
> +       unsigned long   isr;
> +       int             n;
> +
> +       chained_irq_enter(chip, desc);
> +       for (;;) {
> +               /* Reading ISR acks pending (edge triggered) GPIO interrupts.
> +                * When there none are pending, we're finished unless we need
> +                * to process multiple banks (like ID_PIOCDE on sam9263).
> +                */
> +               isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
> +               if (!isr) {
> +                       if (!at91_gpio->next)
> +                               break;
> +                       at91_gpio = at91_gpio->next;
> +                       pio = at91_gpio->regbase;
> +                       continue;
> +               }
> +
> +               n = find_first_bit(&isr, BITS_PER_LONG);
> +               while (n < BITS_PER_LONG) {
> +                       generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
> +                       n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
> +               }
> +       }
> +       chained_irq_exit(chip, desc);
> +       /* now it may re-trigger */
> +}
> +
> +/*
> + * This lock class tells lockdep that GPIO irqs are in a different
> + * category than their parents, so it won't report false recursion.
> + */
> +static struct lock_class_key gpio_lock_class;
> +
> +static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
> +                                                       irq_hw_number_t hw)
> +{
> +       struct at91_gpio_chip   *at91_gpio = h->host_data;
> +
> +       irq_set_lockdep_class(virq, &gpio_lock_class);
> +
> +       /*
> +        * Can use the "simple" and not "edge" handler since it's
> +        * shorter, and the AIC handles interrupts sanely.
> +        */
> +       irq_set_chip_and_handler(virq, &gpio_irqchip,
> +                                handle_simple_irq);
> +       set_irq_flags(virq, IRQF_VALID);
> +       irq_set_chip_data(virq, at91_gpio);
> +
> +       return 0;
> +}
> +
> +static struct irq_domain_ops at91_gpio_ops = {
> +       .map    = at91_gpio_irq_map,
> +       .xlate  = irq_domain_xlate_twocell,
> +};
> +
> +static int at91_gpio_of_irq_setup(struct device_node *node,
> +                                 struct at91_gpio_chip *at91_gpio)
> +{
> +       struct at91_gpio_chip   *prev = NULL;
> +       struct irq_data         *d = irq_get_irq_data(at91_gpio->pioc_virq);
> +
> +       at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
> +
> +       /* Setup proper .irq_set_type function */
> +       if (has_pio3())
> +               gpio_irqchip.irq_set_type = alt_gpio_irq_type;
> +       else
> +               gpio_irqchip.irq_set_type = gpio_irq_type;
> +
> +       /* Disable irqs of this PIO controller */
> +       __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
> +
> +       /* Setup irq domain */
> +       at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
> +                                               &at91_gpio_ops, at91_gpio);
> +       if (!at91_gpio->domain)
> +               panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
> +                       at91_gpio->pioc_idx);
> +
> +       /* Setup chained handler */
> +       if (at91_gpio->pioc_idx)
> +               prev = gpio_chip[at91_gpio->pioc_idx - 1];
> +
> +       /* The toplevel handler handles one bank of GPIOs, except
> +        * on some SoC it can handles up to three...
> +        * We only set up the handler for the first of the list.
> +        */
> +       if (prev && prev->next == at91_gpio)
> +               return 0;
> +
> +       irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
> +       irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
> +
> +       return 0;
> +}
> +
> +/* This structure is replicated for each GPIO block allocated at probe time */
> +static struct gpio_chip at91_gpio_template = {
> +       .request                = at91_gpio_request,
> +       .free                   = at91_gpio_free,
> +       .direction_input        = at91_gpio_direction_input,
> +       .get                    = at91_gpio_get,
> +       .direction_output       = at91_gpio_direction_output,
> +       .set                    = at91_gpio_set,
> +       .to_irq                 = at91_gpio_to_irq,
> +       .dbg_show               = at91_gpio_dbg_show,
> +       .can_sleep              = 0,
> +       .ngpio                  = 32,
> +};
> +
> +static void __devinit at91_gpio_probe_fixup(void)
> +{
> +       unsigned i;
> +       struct at91_gpio_chip *at91_gpio, *last = NULL;
> +
> +       for (i = 0; i < gpio_banks; i++) {
> +               at91_gpio = gpio_chip[i];
> +
> +               /*
> +                * GPIO controller are grouped on some SoC:
> +                * PIOC, PIOD and PIOE can share the same IRQ line
> +                */
> +               if (last && last->pioc_virq == at91_gpio->pioc_virq)
> +                       last->next = at91_gpio;
> +               last = at91_gpio;
> +       }
> +}
> +
> +static int __devinit at91_gpio_probe(struct platform_device *pdev)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       struct resource *res;
> +       struct at91_gpio_chip *at91_chip = NULL;
> +       struct gpio_chip *chip;
> +       struct pinctrl_gpio_range *range;
> +       int ret = 0;
> +       int irq;
> +       int alias_idx = of_alias_get_id(np, "gpio");
> +       uint32_t ngpio;
> +
> +       BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chip));
> +       if (gpio_chip[alias_idx]) {
> +               ret = -EBUSY;
> +               goto err;
> +       }
> +
> +       at91_gpio_caps = (unsigned long)np->data;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       if (!res) {
> +               ret = -ENOENT;
> +               goto err;
> +       }
> +
> +       irq = platform_get_irq(pdev, 0);
> +       if (irq < 0) {
> +               ret = irq;
> +               goto err;
> +       }
> +
> +       at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
> +       if (!at91_chip) {
> +               ret = -ENOMEM;
> +               goto err;
> +       }
> +
> +       at91_chip->regbase = devm_request_and_ioremap(&pdev->dev, res);
> +       if (!at91_chip->regbase) {
> +               dev_err(&pdev->dev, "failed to map registers, ignoring.\n");
> +               ret = -EBUSY;
> +               goto err;
> +       }
> +
> +       at91_chip->pioc_virq = irq;
> +       at91_chip->pioc_idx = alias_idx;
> +
> +       at91_chip->clock = clk_get(&pdev->dev, NULL);
> +       if (IS_ERR(at91_chip->clock)) {
> +               dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
> +               goto err;
> +       }
> +
> +       if (clk_prepare(at91_chip->clock))
> +               goto clk_prep_err;
> +
> +       /* enable PIO controller's clock */
> +       if (clk_enable(at91_chip->clock)) {
> +               dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
> +               goto clk_err;
> +       }
> +
> +       at91_chip->chip = at91_gpio_template;
> +
> +       chip = &at91_chip->chip;
> +       chip->of_node = np;
> +       chip->label = dev_name(&pdev->dev);
> +       chip->dev = &pdev->dev;
> +       chip->owner = THIS_MODULE;
> +       chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
> +
> +       if (!of_property_read_u32(np, "gpio-nb", &ngpio)) {
> +               if (ngpio >= MAX_NB_GPIO_PER_BANK)
> +                       pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
> +                              alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
> +               else
> +                       chip->ngpio = ngpio;
> +       }
> +
> +       range = &at91_chip->range;
> +       range->name = chip->label;
> +       range->id = alias_idx;
> +       range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
> +
> +       range->npins = chip->ngpio;
> +       range->gc = chip;
> +
> +       ret = gpiochip_add(chip);
> +       if (ret)
> +               goto clk_err;
> +
> +       gpio_chip[alias_idx] = at91_chip;
> +       gpio_banks = max(gpio_banks, alias_idx + 1);
> +
> +       at91_gpio_probe_fixup();
> +
> +       at91_gpio_of_irq_setup(np, at91_chip);
> +
> +       dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
> +
> +       return 0;
> +
> +clk_err:
> +       clk_unprepare(at91_chip->clock);
> +clk_prep_err:
> +       clk_put(at91_chip->clock);
> +err:
> +       dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
> +
> +       return ret;
> +}
> +
> +static struct of_device_id at91_gpio_of_match[] __devinitdata = {
> +       { .compatible = "atmel,at91rm9200-gpio", },
> +       { .compatible = "atmel,at91sam9x5-gpio", .data = (void*)AT91_GPIO_CAP_PIO3, },
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver at91_gpio_driver = {
> +       .driver = {
> +               .name = "gpio-at91",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(at91_gpio_of_match),
> +       },
> +       .probe = at91_gpio_probe,
> +};
> +
> +static struct of_device_id at91_pinctrl_of_match[] __devinitdata = {
> +       { .compatible = "atmel,at91rm9200-pinctrl", },
> +       { /* sentinel */ }
> +};
> +
> +static struct platform_driver at91_pinctrl_driver = {
> +       .driver = {
> +               .name = "pinctrl-at91",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(at91_pinctrl_of_match),
> +       },
> +       .probe = at91_pinctrl_probe,
> +       .remove = __devexit_p(at91_pinctrl_remove),
> +};
> +
> +static int __init at91_pinctrl_init(void)
> +{
> +       int ret;
> +
> +       ret = platform_driver_register(&at91_gpio_driver);
> +       if (ret)
> +               return ret;
> +       return platform_driver_register(&at91_pinctrl_driver);
> +}
> +arch_initcall(at91_pinctrl_init);
> +
> +static void __exit at91_pinctrl_exit(void)
> +{
> +       platform_driver_unregister(&at91_pinctrl_driver);
> +}
> +
> +module_exit(at91_pinctrl_exit);
> +MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>");
> +MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.10.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


I tested it with a at91sam9g35-ek board, and it hangs before the dbgu
line is configured.
( with at91_dt_defconfig and at91sam9g35ek.dts )

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From andrew at lunn.ch  Mon Aug 13 10:59:24 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 13 Aug 2012 16:59:24 +0200
Subject: [PATCH 03/10] ARM: mv78xx0: fix win_cfg_base prototype
In-Reply-To: <1344461278-28245-4-git-send-email-arnd@arndb.de>
References: <1344461278-28245-1-git-send-email-arnd@arndb.de>
 <1344461278-28245-4-git-send-email-arnd@arndb.de>
Message-ID: <20120813145924.GI12756@lunn.ch>

On Wed, Aug 08, 2012 at 11:27:51PM +0200, Arnd Bergmann wrote:
> Patch b6d1c33a31 "ARM: Orion: Consolidate the address map setup" tried
> to merge the address map for the four orion platforms, but apparently
> got it wrong for mv78xx0. Admittedly I don't understand what this
> code actually does, but it's clear that the current version is
> wrong.
> 
> Without this patch, building mv78xx0_defconfig results in:
> 
> arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: initialization from incompatible pointer type [enabled by default]
> arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Michael Walle <michael at walle.cc>
> Cc: Nicolas Pitre <nico at linaro.org>
> ---
>  arch/arm/mach-mv78xx0/addr-map.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
> index 62b53d7..a9bc841 100644
> --- a/arch/arm/mach-mv78xx0/addr-map.c
> +++ b/arch/arm/mach-mv78xx0/addr-map.c
> @@ -37,7 +37,7 @@
>  #define WIN0_OFF(n)		(BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
>  #define WIN8_OFF(n)		(BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
>  
> -static void __init __iomem *win_cfg_base(int win)
> +static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
>  {
>  	/*
>  	 * Find the control register base address for this window.
> -- 
> 1.7.10
> 

Acked-by: Andrew Lunn <andrew at lunn.ch>

	  Andrew


From shawn.guo at linaro.org  Mon Aug 13 11:04:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 23:04:53 +0800
Subject: [PATCH v2 2/2] ARM: imx/pcm043: add oftree support
In-Reply-To: <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1344591170-13638-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120813150450.GA27393@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 11:32:50AM +0200, Uwe Kleine-K?nig wrote:
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> 
> --
> changes since (implicit) v1
> (id:1343922986-32469-2-git-send-email-u.kleine-koenig at pengutronix.de)
> 
>  - add newlines between nodes
>  - adapt to changes in patch 1
> ---
>  arch/arm/boot/dts/phytec-pcm043.dtsi |   57 ++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
>  create mode 100644 arch/arm/boot/dts/phytec-pcm043.dtsi
> 
Follow the imx dts naming pattern to name it imx35-phytec-pcm043.dtsi?

-- 
Regards,
Shawn



From matt at genesi-usa.com  Mon Aug 13 11:12:38 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 13 Aug 2012 10:12:38 -0500
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>

I have a minor nit; while renumbering the pinctrl definitions is
laudable and device trees can match, there are 16 other pin controls
below EIM_D16 - this makes the start of the IOMUXC pin definitions
actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
(pin_id*4)).

While this works, it's fine, but it would be more reasonable/correct
to number pin indices from the first configurable pad and not by a
hardcoded magic offset into the base. The EIM_DA* pins below the
current EIM_D16 are only configurable as CoreSight trace signals but
it would save trouble later if anyone wanted to use these for example
on a prototype board configured as those trace pads if they didn't
have to renumber all the pins again. Nobody currently uses them in the
tree but it makes more sense to me to count from the first
configurable pad, than the first currently-used-in-the-tree
configurable pad.

Therefore I propose;

* add MX51_PAD_EIM_DA0 through DA15 as index 0-15 (same for any
differences in other i.MX etc.)
* move all the pin indices currently defined up by 16 for MX51 (same for above)
* _then_ renumber the current device trees..

That way churn is minimized in the future and we don't end up changing
trees and definitions again in the future in the event that someone
DOES want to use those pads in a shippable product with mainline Linux
support (and sees fit to enable TPIU_TRACE_EN for some reason and has
the hardware to use it).

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Mon, Aug 13, 2012 at 9:47 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
> pinctrl drivers number pad from 1.  It causes problem/confusion when
> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>
> Change imx51_pads and imx53_pads numbering start from 0.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/pinctrl/pinctrl-imx51.c |  490 +++++++++++++++++++-------------------
>  drivers/pinctrl/pinctrl-imx53.c |  402 ++++++++++++++++----------------
>  2 files changed, 446 insertions(+), 446 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
> index 9fd0216..fb84689 100644
> --- a/drivers/pinctrl/pinctrl-imx51.c
> +++ b/drivers/pinctrl/pinctrl-imx51.c
> @@ -23,251 +23,251 @@
>  #include "pinctrl-imx.h"
>
>  enum imx51_pads {
> -       MX51_PAD_EIM_D16 = 1,
> -       MX51_PAD_EIM_D17 = 2,
> -       MX51_PAD_EIM_D18 = 3,
> -       MX51_PAD_EIM_D19 = 4,
> -       MX51_PAD_EIM_D20 = 5,
> -       MX51_PAD_EIM_D21 = 6,
> -       MX51_PAD_EIM_D22 = 7,
> -       MX51_PAD_EIM_D23 = 8,
> -       MX51_PAD_EIM_D24 = 9,
> -       MX51_PAD_EIM_D25 = 10,
> -       MX51_PAD_EIM_D26 = 11,
> -       MX51_PAD_EIM_D27 = 12,
> -       MX51_PAD_EIM_D28 = 13,
> -       MX51_PAD_EIM_D29 = 14,
> -       MX51_PAD_EIM_D30 = 15,
> -       MX51_PAD_EIM_D31 = 16,
> -       MX51_PAD_EIM_A16 = 17,
> -       MX51_PAD_EIM_A17 = 18,
> -       MX51_PAD_EIM_A18 = 19,
> -       MX51_PAD_EIM_A19 = 20,
> -       MX51_PAD_EIM_A20 = 21,
> -       MX51_PAD_EIM_A21 = 22,
> -       MX51_PAD_EIM_A22 = 23,
> -       MX51_PAD_EIM_A23 = 24,
> -       MX51_PAD_EIM_A24 = 25,
> -       MX51_PAD_EIM_A25 = 26,
> -       MX51_PAD_EIM_A26 = 27,
> -       MX51_PAD_EIM_A27 = 28,
> -       MX51_PAD_EIM_EB0 = 29,
> -       MX51_PAD_EIM_EB1 = 30,
> -       MX51_PAD_EIM_EB2 = 31,
> -       MX51_PAD_EIM_EB3 = 32,
> -       MX51_PAD_EIM_OE = 33,
> -       MX51_PAD_EIM_CS0 = 34,
> -       MX51_PAD_EIM_CS1 = 35,
> -       MX51_PAD_EIM_CS2 = 36,
> -       MX51_PAD_EIM_CS3 = 37,
> -       MX51_PAD_EIM_CS4 = 38,
> -       MX51_PAD_EIM_CS5 = 39,
> -       MX51_PAD_EIM_DTACK = 40,
> -       MX51_PAD_EIM_LBA = 41,
> -       MX51_PAD_EIM_CRE = 42,
> -       MX51_PAD_DRAM_CS1 = 43,
> -       MX51_PAD_NANDF_WE_B = 44,
> -       MX51_PAD_NANDF_RE_B = 45,
> -       MX51_PAD_NANDF_ALE = 46,
> -       MX51_PAD_NANDF_CLE = 47,
> -       MX51_PAD_NANDF_WP_B = 48,
> -       MX51_PAD_NANDF_RB0 = 49,
> -       MX51_PAD_NANDF_RB1 = 50,
> -       MX51_PAD_NANDF_RB2 = 51,
> -       MX51_PAD_NANDF_RB3 = 52,
> -       MX51_PAD_GPIO_NAND = 53,
> -       MX51_PAD_NANDF_CS0 = 54,
> -       MX51_PAD_NANDF_CS1 = 55,
> -       MX51_PAD_NANDF_CS2 = 56,
> -       MX51_PAD_NANDF_CS3 = 57,
> -       MX51_PAD_NANDF_CS4 = 58,
> -       MX51_PAD_NANDF_CS5 = 59,
> -       MX51_PAD_NANDF_CS6 = 60,
> -       MX51_PAD_NANDF_CS7 = 61,
> -       MX51_PAD_NANDF_RDY_INT = 62,
> -       MX51_PAD_NANDF_D15 = 63,
> -       MX51_PAD_NANDF_D14 = 64,
> -       MX51_PAD_NANDF_D13 = 65,
> -       MX51_PAD_NANDF_D12 = 66,
> -       MX51_PAD_NANDF_D11 = 67,
> -       MX51_PAD_NANDF_D10 = 68,
> -       MX51_PAD_NANDF_D9 = 69,
> -       MX51_PAD_NANDF_D8 = 70,
> -       MX51_PAD_NANDF_D7 = 71,
> -       MX51_PAD_NANDF_D6 = 72,
> -       MX51_PAD_NANDF_D5 = 73,
> -       MX51_PAD_NANDF_D4 = 74,
> -       MX51_PAD_NANDF_D3 = 75,
> -       MX51_PAD_NANDF_D2 = 76,
> -       MX51_PAD_NANDF_D1 = 77,
> -       MX51_PAD_NANDF_D0 = 78,
> -       MX51_PAD_CSI1_D8 = 79,
> -       MX51_PAD_CSI1_D9 = 80,
> -       MX51_PAD_CSI1_D10 = 81,
> -       MX51_PAD_CSI1_D11 = 82,
> -       MX51_PAD_CSI1_D12 = 83,
> -       MX51_PAD_CSI1_D13 = 84,
> -       MX51_PAD_CSI1_D14 = 85,
> -       MX51_PAD_CSI1_D15 = 86,
> -       MX51_PAD_CSI1_D16 = 87,
> -       MX51_PAD_CSI1_D17 = 88,
> -       MX51_PAD_CSI1_D18 = 89,
> -       MX51_PAD_CSI1_D19 = 90,
> -       MX51_PAD_CSI1_VSYNC = 91,
> -       MX51_PAD_CSI1_HSYNC = 92,
> -       MX51_PAD_CSI1_PIXCLK = 93,
> -       MX51_PAD_CSI1_MCLK = 94,
> -       MX51_PAD_CSI2_D12 = 95,
> -       MX51_PAD_CSI2_D13 = 96,
> -       MX51_PAD_CSI2_D14 = 97,
> -       MX51_PAD_CSI2_D15 = 98,
> -       MX51_PAD_CSI2_D16 = 99,
> -       MX51_PAD_CSI2_D17 = 100,
> -       MX51_PAD_CSI2_D18 = 101,
> -       MX51_PAD_CSI2_D19 = 102,
> -       MX51_PAD_CSI2_VSYNC = 103,
> -       MX51_PAD_CSI2_HSYNC = 104,
> -       MX51_PAD_CSI2_PIXCLK = 105,
> -       MX51_PAD_I2C1_CLK = 106,
> -       MX51_PAD_I2C1_DAT = 107,
> -       MX51_PAD_AUD3_BB_TXD = 108,
> -       MX51_PAD_AUD3_BB_RXD = 109,
> -       MX51_PAD_AUD3_BB_CK = 110,
> -       MX51_PAD_AUD3_BB_FS = 111,
> -       MX51_PAD_CSPI1_MOSI = 112,
> -       MX51_PAD_CSPI1_MISO = 113,
> -       MX51_PAD_CSPI1_SS0 = 114,
> -       MX51_PAD_CSPI1_SS1 = 115,
> -       MX51_PAD_CSPI1_RDY = 116,
> -       MX51_PAD_CSPI1_SCLK = 117,
> -       MX51_PAD_UART1_RXD = 118,
> -       MX51_PAD_UART1_TXD = 119,
> -       MX51_PAD_UART1_RTS = 120,
> -       MX51_PAD_UART1_CTS = 121,
> -       MX51_PAD_UART2_RXD = 122,
> -       MX51_PAD_UART2_TXD = 123,
> -       MX51_PAD_UART3_RXD = 124,
> -       MX51_PAD_UART3_TXD = 125,
> -       MX51_PAD_OWIRE_LINE = 126,
> -       MX51_PAD_KEY_ROW0 = 127,
> -       MX51_PAD_KEY_ROW1 = 128,
> -       MX51_PAD_KEY_ROW2 = 129,
> -       MX51_PAD_KEY_ROW3 = 130,
> -       MX51_PAD_KEY_COL0 = 131,
> -       MX51_PAD_KEY_COL1 = 132,
> -       MX51_PAD_KEY_COL2 = 133,
> -       MX51_PAD_KEY_COL3 = 134,
> -       MX51_PAD_KEY_COL4 = 135,
> -       MX51_PAD_KEY_COL5 = 136,
> -       MX51_PAD_USBH1_CLK = 137,
> -       MX51_PAD_USBH1_DIR = 138,
> -       MX51_PAD_USBH1_STP = 139,
> -       MX51_PAD_USBH1_NXT = 140,
> -       MX51_PAD_USBH1_DATA0 = 141,
> -       MX51_PAD_USBH1_DATA1 = 142,
> -       MX51_PAD_USBH1_DATA2 = 143,
> -       MX51_PAD_USBH1_DATA3 = 144,
> -       MX51_PAD_USBH1_DATA4 = 145,
> -       MX51_PAD_USBH1_DATA5 = 146,
> -       MX51_PAD_USBH1_DATA6 = 147,
> -       MX51_PAD_USBH1_DATA7 = 148,
> -       MX51_PAD_DI1_PIN11 = 149,
> -       MX51_PAD_DI1_PIN12 = 150,
> -       MX51_PAD_DI1_PIN13 = 151,
> -       MX51_PAD_DI1_D0_CS = 152,
> -       MX51_PAD_DI1_D1_CS = 153,
> -       MX51_PAD_DISPB2_SER_DIN = 154,
> -       MX51_PAD_DISPB2_SER_DIO = 155,
> -       MX51_PAD_DISPB2_SER_CLK = 156,
> -       MX51_PAD_DISPB2_SER_RS = 157,
> -       MX51_PAD_DISP1_DAT0 = 158,
> -       MX51_PAD_DISP1_DAT1 = 159,
> -       MX51_PAD_DISP1_DAT2 = 160,
> -       MX51_PAD_DISP1_DAT3 = 161,
> -       MX51_PAD_DISP1_DAT4 = 162,
> -       MX51_PAD_DISP1_DAT5 = 163,
> -       MX51_PAD_DISP1_DAT6 = 164,
> -       MX51_PAD_DISP1_DAT7 = 165,
> -       MX51_PAD_DISP1_DAT8 = 166,
> -       MX51_PAD_DISP1_DAT9 = 167,
> -       MX51_PAD_DISP1_DAT10 = 168,
> -       MX51_PAD_DISP1_DAT11 = 169,
> -       MX51_PAD_DISP1_DAT12 = 170,
> -       MX51_PAD_DISP1_DAT13 = 171,
> -       MX51_PAD_DISP1_DAT14 = 172,
> -       MX51_PAD_DISP1_DAT15 = 173,
> -       MX51_PAD_DISP1_DAT16 = 174,
> -       MX51_PAD_DISP1_DAT17 = 175,
> -       MX51_PAD_DISP1_DAT18 = 176,
> -       MX51_PAD_DISP1_DAT19 = 177,
> -       MX51_PAD_DISP1_DAT20 = 178,
> -       MX51_PAD_DISP1_DAT21 = 179,
> -       MX51_PAD_DISP1_DAT22 = 180,
> -       MX51_PAD_DISP1_DAT23 = 181,
> -       MX51_PAD_DI1_PIN3 = 182,
> -       MX51_PAD_DI1_PIN2 = 183,
> -       MX51_PAD_DI_GP2 = 184,
> -       MX51_PAD_DI_GP3 = 185,
> -       MX51_PAD_DI2_PIN4 = 186,
> -       MX51_PAD_DI2_PIN2 = 187,
> -       MX51_PAD_DI2_PIN3 = 188,
> -       MX51_PAD_DI2_DISP_CLK = 189,
> -       MX51_PAD_DI_GP4 = 190,
> -       MX51_PAD_DISP2_DAT0 = 191,
> -       MX51_PAD_DISP2_DAT1 = 192,
> -       MX51_PAD_DISP2_DAT2 = 193,
> -       MX51_PAD_DISP2_DAT3 = 194,
> -       MX51_PAD_DISP2_DAT4 = 195,
> -       MX51_PAD_DISP2_DAT5 = 196,
> -       MX51_PAD_DISP2_DAT6 = 197,
> -       MX51_PAD_DISP2_DAT7 = 198,
> -       MX51_PAD_DISP2_DAT8 = 199,
> -       MX51_PAD_DISP2_DAT9 = 200,
> -       MX51_PAD_DISP2_DAT10 = 201,
> -       MX51_PAD_DISP2_DAT11 = 202,
> -       MX51_PAD_DISP2_DAT12 = 203,
> -       MX51_PAD_DISP2_DAT13 = 204,
> -       MX51_PAD_DISP2_DAT14 = 205,
> -       MX51_PAD_DISP2_DAT15 = 206,
> -       MX51_PAD_SD1_CMD = 207,
> -       MX51_PAD_SD1_CLK = 208,
> -       MX51_PAD_SD1_DATA0 = 209,
> -       MX51_PAD_EIM_DA0 = 210,
> -       MX51_PAD_EIM_DA1 = 211,
> -       MX51_PAD_EIM_DA2 = 212,
> -       MX51_PAD_EIM_DA3 = 213,
> -       MX51_PAD_SD1_DATA1 = 214,
> -       MX51_PAD_EIM_DA4 = 215,
> -       MX51_PAD_EIM_DA5 = 216,
> -       MX51_PAD_EIM_DA6 = 217,
> -       MX51_PAD_EIM_DA7 = 218,
> -       MX51_PAD_SD1_DATA2 = 219,
> -       MX51_PAD_EIM_DA10 = 220,
> -       MX51_PAD_EIM_DA11 = 221,
> -       MX51_PAD_EIM_DA8 = 222,
> -       MX51_PAD_EIM_DA9 = 223,
> -       MX51_PAD_SD1_DATA3 = 224,
> -       MX51_PAD_GPIO1_0 = 225,
> -       MX51_PAD_GPIO1_1 = 226,
> -       MX51_PAD_EIM_DA12 = 227,
> -       MX51_PAD_EIM_DA13 = 228,
> -       MX51_PAD_EIM_DA14 = 229,
> -       MX51_PAD_EIM_DA15 = 230,
> -       MX51_PAD_SD2_CMD = 231,
> -       MX51_PAD_SD2_CLK = 232,
> -       MX51_PAD_SD2_DATA0 = 233,
> -       MX51_PAD_SD2_DATA1 = 234,
> -       MX51_PAD_SD2_DATA2 = 235,
> -       MX51_PAD_SD2_DATA3 = 236,
> -       MX51_PAD_GPIO1_2 = 237,
> -       MX51_PAD_GPIO1_3 = 238,
> -       MX51_PAD_PMIC_INT_REQ = 239,
> -       MX51_PAD_GPIO1_4 = 240,
> -       MX51_PAD_GPIO1_5 = 241,
> -       MX51_PAD_GPIO1_6 = 242,
> -       MX51_PAD_GPIO1_7 = 243,
> -       MX51_PAD_GPIO1_8 = 244,
> -       MX51_PAD_GPIO1_9 = 245,
> +       MX51_PAD_EIM_D16 = 0,
> +       MX51_PAD_EIM_D17 = 1,
> +       MX51_PAD_EIM_D18 = 2,
> +       MX51_PAD_EIM_D19 = 3,
> +       MX51_PAD_EIM_D20 = 4,
> +       MX51_PAD_EIM_D21 = 5,
> +       MX51_PAD_EIM_D22 = 6,
> +       MX51_PAD_EIM_D23 = 7,
> +       MX51_PAD_EIM_D24 = 8,
> +       MX51_PAD_EIM_D25 = 9,
> +       MX51_PAD_EIM_D26 = 10,
> +       MX51_PAD_EIM_D27 = 11,
> +       MX51_PAD_EIM_D28 = 12,
> +       MX51_PAD_EIM_D29 = 13,
> +       MX51_PAD_EIM_D30 = 14,
> +       MX51_PAD_EIM_D31 = 15,
> +       MX51_PAD_EIM_A16 = 16,
> +       MX51_PAD_EIM_A17 = 17,
> +       MX51_PAD_EIM_A18 = 18,
> +       MX51_PAD_EIM_A19 = 19,
> +       MX51_PAD_EIM_A20 = 20,
> +       MX51_PAD_EIM_A21 = 21,
> +       MX51_PAD_EIM_A22 = 22,
> +       MX51_PAD_EIM_A23 = 23,
> +       MX51_PAD_EIM_A24 = 24,
> +       MX51_PAD_EIM_A25 = 25,
> +       MX51_PAD_EIM_A26 = 26,
> +       MX51_PAD_EIM_A27 = 27,
> +       MX51_PAD_EIM_EB0 = 28,
> +       MX51_PAD_EIM_EB1 = 29,
> +       MX51_PAD_EIM_EB2 = 30,
> +       MX51_PAD_EIM_EB3 = 31,
> +       MX51_PAD_EIM_OE = 32,
> +       MX51_PAD_EIM_CS0 = 33,
> +       MX51_PAD_EIM_CS1 = 34,
> +       MX51_PAD_EIM_CS2 = 35,
> +       MX51_PAD_EIM_CS3 = 36,
> +       MX51_PAD_EIM_CS4 = 37,
> +       MX51_PAD_EIM_CS5 = 38,
> +       MX51_PAD_EIM_DTACK = 39,
> +       MX51_PAD_EIM_LBA = 40,
> +       MX51_PAD_EIM_CRE = 41,
> +       MX51_PAD_DRAM_CS1 = 42,
> +       MX51_PAD_NANDF_WE_B = 43,
> +       MX51_PAD_NANDF_RE_B = 44,
> +       MX51_PAD_NANDF_ALE = 45,
> +       MX51_PAD_NANDF_CLE = 46,
> +       MX51_PAD_NANDF_WP_B = 47,
> +       MX51_PAD_NANDF_RB0 = 48,
> +       MX51_PAD_NANDF_RB1 = 49,
> +       MX51_PAD_NANDF_RB2 = 50,
> +       MX51_PAD_NANDF_RB3 = 51,
> +       MX51_PAD_GPIO_NAND = 52,
> +       MX51_PAD_NANDF_CS0 = 53,
> +       MX51_PAD_NANDF_CS1 = 54,
> +       MX51_PAD_NANDF_CS2 = 55,
> +       MX51_PAD_NANDF_CS3 = 56,
> +       MX51_PAD_NANDF_CS4 = 57,
> +       MX51_PAD_NANDF_CS5 = 58,
> +       MX51_PAD_NANDF_CS6 = 59,
> +       MX51_PAD_NANDF_CS7 = 60,
> +       MX51_PAD_NANDF_RDY_INT = 61,
> +       MX51_PAD_NANDF_D15 = 62,
> +       MX51_PAD_NANDF_D14 = 63,
> +       MX51_PAD_NANDF_D13 = 64,
> +       MX51_PAD_NANDF_D12 = 65,
> +       MX51_PAD_NANDF_D11 = 66,
> +       MX51_PAD_NANDF_D10 = 67,
> +       MX51_PAD_NANDF_D9 = 68,
> +       MX51_PAD_NANDF_D8 = 69,
> +       MX51_PAD_NANDF_D7 = 70,
> +       MX51_PAD_NANDF_D6 = 71,
> +       MX51_PAD_NANDF_D5 = 72,
> +       MX51_PAD_NANDF_D4 = 73,
> +       MX51_PAD_NANDF_D3 = 74,
> +       MX51_PAD_NANDF_D2 = 75,
> +       MX51_PAD_NANDF_D1 = 76,
> +       MX51_PAD_NANDF_D0 = 77,
> +       MX51_PAD_CSI1_D8 = 78,
> +       MX51_PAD_CSI1_D9 = 79,
> +       MX51_PAD_CSI1_D10 = 80,
> +       MX51_PAD_CSI1_D11 = 81,
> +       MX51_PAD_CSI1_D12 = 82,
> +       MX51_PAD_CSI1_D13 = 83,
> +       MX51_PAD_CSI1_D14 = 84,
> +       MX51_PAD_CSI1_D15 = 85,
> +       MX51_PAD_CSI1_D16 = 86,
> +       MX51_PAD_CSI1_D17 = 87,
> +       MX51_PAD_CSI1_D18 = 88,
> +       MX51_PAD_CSI1_D19 = 89,
> +       MX51_PAD_CSI1_VSYNC = 90,
> +       MX51_PAD_CSI1_HSYNC = 91,
> +       MX51_PAD_CSI1_PIXCLK = 92,
> +       MX51_PAD_CSI1_MCLK = 93,
> +       MX51_PAD_CSI2_D12 = 94,
> +       MX51_PAD_CSI2_D13 = 95,
> +       MX51_PAD_CSI2_D14 = 96,
> +       MX51_PAD_CSI2_D15 = 97,
> +       MX51_PAD_CSI2_D16 = 98,
> +       MX51_PAD_CSI2_D17 = 99,
> +       MX51_PAD_CSI2_D18 = 100,
> +       MX51_PAD_CSI2_D19 = 101,
> +       MX51_PAD_CSI2_VSYNC = 102,
> +       MX51_PAD_CSI2_HSYNC = 103,
> +       MX51_PAD_CSI2_PIXCLK = 104,
> +       MX51_PAD_I2C1_CLK = 105,
> +       MX51_PAD_I2C1_DAT = 106,
> +       MX51_PAD_AUD3_BB_TXD = 107,
> +       MX51_PAD_AUD3_BB_RXD = 108,
> +       MX51_PAD_AUD3_BB_CK = 109,
> +       MX51_PAD_AUD3_BB_FS = 110,
> +       MX51_PAD_CSPI1_MOSI = 111,
> +       MX51_PAD_CSPI1_MISO = 112,
> +       MX51_PAD_CSPI1_SS0 = 113,
> +       MX51_PAD_CSPI1_SS1 = 114,
> +       MX51_PAD_CSPI1_RDY = 115,
> +       MX51_PAD_CSPI1_SCLK = 116,
> +       MX51_PAD_UART1_RXD = 117,
> +       MX51_PAD_UART1_TXD = 118,
> +       MX51_PAD_UART1_RTS = 119,
> +       MX51_PAD_UART1_CTS = 120,
> +       MX51_PAD_UART2_RXD = 121,
> +       MX51_PAD_UART2_TXD = 122,
> +       MX51_PAD_UART3_RXD = 123,
> +       MX51_PAD_UART3_TXD = 124,
> +       MX51_PAD_OWIRE_LINE = 125,
> +       MX51_PAD_KEY_ROW0 = 126,
> +       MX51_PAD_KEY_ROW1 = 127,
> +       MX51_PAD_KEY_ROW2 = 128,
> +       MX51_PAD_KEY_ROW3 = 129,
> +       MX51_PAD_KEY_COL0 = 130,
> +       MX51_PAD_KEY_COL1 = 131,
> +       MX51_PAD_KEY_COL2 = 132,
> +       MX51_PAD_KEY_COL3 = 133,
> +       MX51_PAD_KEY_COL4 = 134,
> +       MX51_PAD_KEY_COL5 = 135,
> +       MX51_PAD_USBH1_CLK = 136,
> +       MX51_PAD_USBH1_DIR = 137,
> +       MX51_PAD_USBH1_STP = 138,
> +       MX51_PAD_USBH1_NXT = 139,
> +       MX51_PAD_USBH1_DATA0 = 140,
> +       MX51_PAD_USBH1_DATA1 = 141,
> +       MX51_PAD_USBH1_DATA2 = 142,
> +       MX51_PAD_USBH1_DATA3 = 143,
> +       MX51_PAD_USBH1_DATA4 = 144,
> +       MX51_PAD_USBH1_DATA5 = 145,
> +       MX51_PAD_USBH1_DATA6 = 146,
> +       MX51_PAD_USBH1_DATA7 = 147,
> +       MX51_PAD_DI1_PIN11 = 148,
> +       MX51_PAD_DI1_PIN12 = 149,
> +       MX51_PAD_DI1_PIN13 = 150,
> +       MX51_PAD_DI1_D0_CS = 151,
> +       MX51_PAD_DI1_D1_CS = 152,
> +       MX51_PAD_DISPB2_SER_DIN = 153,
> +       MX51_PAD_DISPB2_SER_DIO = 154,
> +       MX51_PAD_DISPB2_SER_CLK = 155,
> +       MX51_PAD_DISPB2_SER_RS = 156,
> +       MX51_PAD_DISP1_DAT0 = 157,
> +       MX51_PAD_DISP1_DAT1 = 158,
> +       MX51_PAD_DISP1_DAT2 = 159,
> +       MX51_PAD_DISP1_DAT3 = 160,
> +       MX51_PAD_DISP1_DAT4 = 161,
> +       MX51_PAD_DISP1_DAT5 = 162,
> +       MX51_PAD_DISP1_DAT6 = 163,
> +       MX51_PAD_DISP1_DAT7 = 164,
> +       MX51_PAD_DISP1_DAT8 = 165,
> +       MX51_PAD_DISP1_DAT9 = 166,
> +       MX51_PAD_DISP1_DAT10 = 167,
> +       MX51_PAD_DISP1_DAT11 = 168,
> +       MX51_PAD_DISP1_DAT12 = 169,
> +       MX51_PAD_DISP1_DAT13 = 170,
> +       MX51_PAD_DISP1_DAT14 = 171,
> +       MX51_PAD_DISP1_DAT15 = 172,
> +       MX51_PAD_DISP1_DAT16 = 173,
> +       MX51_PAD_DISP1_DAT17 = 174,
> +       MX51_PAD_DISP1_DAT18 = 175,
> +       MX51_PAD_DISP1_DAT19 = 176,
> +       MX51_PAD_DISP1_DAT20 = 177,
> +       MX51_PAD_DISP1_DAT21 = 178,
> +       MX51_PAD_DISP1_DAT22 = 179,
> +       MX51_PAD_DISP1_DAT23 = 180,
> +       MX51_PAD_DI1_PIN3 = 181,
> +       MX51_PAD_DI1_PIN2 = 182,
> +       MX51_PAD_DI_GP2 = 183,
> +       MX51_PAD_DI_GP3 = 184,
> +       MX51_PAD_DI2_PIN4 = 185,
> +       MX51_PAD_DI2_PIN2 = 186,
> +       MX51_PAD_DI2_PIN3 = 187,
> +       MX51_PAD_DI2_DISP_CLK = 188,
> +       MX51_PAD_DI_GP4 = 189,
> +       MX51_PAD_DISP2_DAT0 = 190,
> +       MX51_PAD_DISP2_DAT1 = 191,
> +       MX51_PAD_DISP2_DAT2 = 192,
> +       MX51_PAD_DISP2_DAT3 = 193,
> +       MX51_PAD_DISP2_DAT4 = 194,
> +       MX51_PAD_DISP2_DAT5 = 195,
> +       MX51_PAD_DISP2_DAT6 = 196,
> +       MX51_PAD_DISP2_DAT7 = 197,
> +       MX51_PAD_DISP2_DAT8 = 198,
> +       MX51_PAD_DISP2_DAT9 = 199,
> +       MX51_PAD_DISP2_DAT10 = 200,
> +       MX51_PAD_DISP2_DAT11 = 201,
> +       MX51_PAD_DISP2_DAT12 = 202,
> +       MX51_PAD_DISP2_DAT13 = 203,
> +       MX51_PAD_DISP2_DAT14 = 204,
> +       MX51_PAD_DISP2_DAT15 = 205,
> +       MX51_PAD_SD1_CMD = 206,
> +       MX51_PAD_SD1_CLK = 207,
> +       MX51_PAD_SD1_DATA0 = 208,
> +       MX51_PAD_EIM_DA0 = 209,
> +       MX51_PAD_EIM_DA1 = 210,
> +       MX51_PAD_EIM_DA2 = 211,
> +       MX51_PAD_EIM_DA3 = 212,
> +       MX51_PAD_SD1_DATA1 = 213,
> +       MX51_PAD_EIM_DA4 = 214,
> +       MX51_PAD_EIM_DA5 = 215,
> +       MX51_PAD_EIM_DA6 = 216,
> +       MX51_PAD_EIM_DA7 = 217,
> +       MX51_PAD_SD1_DATA2 = 218,
> +       MX51_PAD_EIM_DA10 = 219,
> +       MX51_PAD_EIM_DA11 = 220,
> +       MX51_PAD_EIM_DA8 = 221,
> +       MX51_PAD_EIM_DA9 = 222,
> +       MX51_PAD_SD1_DATA3 = 223,
> +       MX51_PAD_GPIO1_0 = 224,
> +       MX51_PAD_GPIO1_1 = 225,
> +       MX51_PAD_EIM_DA12 = 226,
> +       MX51_PAD_EIM_DA13 = 227,
> +       MX51_PAD_EIM_DA14 = 228,
> +       MX51_PAD_EIM_DA15 = 229,
> +       MX51_PAD_SD2_CMD = 230,
> +       MX51_PAD_SD2_CLK = 231,
> +       MX51_PAD_SD2_DATA0 = 232,
> +       MX51_PAD_SD2_DATA1 = 233,
> +       MX51_PAD_SD2_DATA2 = 234,
> +       MX51_PAD_SD2_DATA3 = 235,
> +       MX51_PAD_GPIO1_2 = 236,
> +       MX51_PAD_GPIO1_3 = 237,
> +       MX51_PAD_PMIC_INT_REQ = 238,
> +       MX51_PAD_GPIO1_4 = 239,
> +       MX51_PAD_GPIO1_5 = 240,
> +       MX51_PAD_GPIO1_6 = 241,
> +       MX51_PAD_GPIO1_7 = 242,
> +       MX51_PAD_GPIO1_8 = 243,
> +       MX51_PAD_GPIO1_9 = 244,
>  };
>
>  /* imx51 register maps */
> diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
> index 1f49e16..783feb1 100644
> --- a/drivers/pinctrl/pinctrl-imx53.c
> +++ b/drivers/pinctrl/pinctrl-imx53.c
> @@ -23,207 +23,207 @@
>  #include "pinctrl-imx.h"
>
>  enum imx53_pads {
> -       MX53_PAD_GPIO_19 = 1,
> -       MX53_PAD_KEY_COL0 = 2,
> -       MX53_PAD_KEY_ROW0 = 3,
> -       MX53_PAD_KEY_COL1 = 4,
> -       MX53_PAD_KEY_ROW1 = 5,
> -       MX53_PAD_KEY_COL2 = 6,
> -       MX53_PAD_KEY_ROW2 = 7,
> -       MX53_PAD_KEY_COL3 = 8,
> -       MX53_PAD_KEY_ROW3 = 9,
> -       MX53_PAD_KEY_COL4 = 10,
> -       MX53_PAD_KEY_ROW4 = 11,
> -       MX53_PAD_DI0_DISP_CLK = 12,
> -       MX53_PAD_DI0_PIN15 = 13,
> -       MX53_PAD_DI0_PIN2 = 14,
> -       MX53_PAD_DI0_PIN3 = 15,
> -       MX53_PAD_DI0_PIN4 = 16,
> -       MX53_PAD_DISP0_DAT0 = 17,
> -       MX53_PAD_DISP0_DAT1 = 18,
> -       MX53_PAD_DISP0_DAT2 = 19,
> -       MX53_PAD_DISP0_DAT3 = 20,
> -       MX53_PAD_DISP0_DAT4 = 21,
> -       MX53_PAD_DISP0_DAT5 = 22,
> -       MX53_PAD_DISP0_DAT6 = 23,
> -       MX53_PAD_DISP0_DAT7 = 24,
> -       MX53_PAD_DISP0_DAT8 = 25,
> -       MX53_PAD_DISP0_DAT9 = 26,
> -       MX53_PAD_DISP0_DAT10 = 27,
> -       MX53_PAD_DISP0_DAT11 = 28,
> -       MX53_PAD_DISP0_DAT12 = 29,
> -       MX53_PAD_DISP0_DAT13 = 30,
> -       MX53_PAD_DISP0_DAT14 = 31,
> -       MX53_PAD_DISP0_DAT15 = 32,
> -       MX53_PAD_DISP0_DAT16 = 33,
> -       MX53_PAD_DISP0_DAT17 = 34,
> -       MX53_PAD_DISP0_DAT18 = 35,
> -       MX53_PAD_DISP0_DAT19 = 36,
> -       MX53_PAD_DISP0_DAT20 = 37,
> -       MX53_PAD_DISP0_DAT21 = 38,
> -       MX53_PAD_DISP0_DAT22 = 39,
> -       MX53_PAD_DISP0_DAT23 = 40,
> -       MX53_PAD_CSI0_PIXCLK = 41,
> -       MX53_PAD_CSI0_MCLK = 42,
> -       MX53_PAD_CSI0_DATA_EN = 43,
> -       MX53_PAD_CSI0_VSYNC = 44,
> -       MX53_PAD_CSI0_DAT4 = 45,
> -       MX53_PAD_CSI0_DAT5 = 46,
> -       MX53_PAD_CSI0_DAT6 = 47,
> -       MX53_PAD_CSI0_DAT7 = 48,
> -       MX53_PAD_CSI0_DAT8 = 49,
> -       MX53_PAD_CSI0_DAT9 = 50,
> -       MX53_PAD_CSI0_DAT10 = 51,
> -       MX53_PAD_CSI0_DAT11 = 52,
> -       MX53_PAD_CSI0_DAT12 = 53,
> -       MX53_PAD_CSI0_DAT13 = 54,
> -       MX53_PAD_CSI0_DAT14 = 55,
> -       MX53_PAD_CSI0_DAT15 = 56,
> -       MX53_PAD_CSI0_DAT16 = 57,
> -       MX53_PAD_CSI0_DAT17 = 58,
> -       MX53_PAD_CSI0_DAT18 = 59,
> -       MX53_PAD_CSI0_DAT19 = 60,
> -       MX53_PAD_EIM_A25 = 61,
> -       MX53_PAD_EIM_EB2 = 62,
> -       MX53_PAD_EIM_D16 = 63,
> -       MX53_PAD_EIM_D17 = 64,
> -       MX53_PAD_EIM_D18 = 65,
> -       MX53_PAD_EIM_D19 = 66,
> -       MX53_PAD_EIM_D20 = 67,
> -       MX53_PAD_EIM_D21 = 68,
> -       MX53_PAD_EIM_D22 = 69,
> -       MX53_PAD_EIM_D23 = 70,
> -       MX53_PAD_EIM_EB3 = 71,
> -       MX53_PAD_EIM_D24 = 72,
> -       MX53_PAD_EIM_D25 = 73,
> -       MX53_PAD_EIM_D26 = 74,
> -       MX53_PAD_EIM_D27 = 75,
> -       MX53_PAD_EIM_D28 = 76,
> -       MX53_PAD_EIM_D29 = 77,
> -       MX53_PAD_EIM_D30 = 78,
> -       MX53_PAD_EIM_D31 = 79,
> -       MX53_PAD_EIM_A24 = 80,
> -       MX53_PAD_EIM_A23 = 81,
> -       MX53_PAD_EIM_A22 = 82,
> -       MX53_PAD_EIM_A21 = 83,
> -       MX53_PAD_EIM_A20 = 84,
> -       MX53_PAD_EIM_A19 = 85,
> -       MX53_PAD_EIM_A18 = 86,
> -       MX53_PAD_EIM_A17 = 87,
> -       MX53_PAD_EIM_A16 = 88,
> -       MX53_PAD_EIM_CS0 = 89,
> -       MX53_PAD_EIM_CS1 = 90,
> -       MX53_PAD_EIM_OE = 91,
> -       MX53_PAD_EIM_RW = 92,
> -       MX53_PAD_EIM_LBA = 93,
> -       MX53_PAD_EIM_EB0 = 94,
> -       MX53_PAD_EIM_EB1 = 95,
> -       MX53_PAD_EIM_DA0 = 96,
> -       MX53_PAD_EIM_DA1 = 97,
> -       MX53_PAD_EIM_DA2 = 98,
> -       MX53_PAD_EIM_DA3 = 99,
> -       MX53_PAD_EIM_DA4 = 100,
> -       MX53_PAD_EIM_DA5 = 101,
> -       MX53_PAD_EIM_DA6 = 102,
> -       MX53_PAD_EIM_DA7 = 103,
> -       MX53_PAD_EIM_DA8 = 104,
> -       MX53_PAD_EIM_DA9 = 105,
> -       MX53_PAD_EIM_DA10 = 106,
> -       MX53_PAD_EIM_DA11 = 107,
> -       MX53_PAD_EIM_DA12 = 108,
> -       MX53_PAD_EIM_DA13 = 109,
> -       MX53_PAD_EIM_DA14 = 110,
> -       MX53_PAD_EIM_DA15 = 111,
> -       MX53_PAD_NANDF_WE_B = 112,
> -       MX53_PAD_NANDF_RE_B = 113,
> -       MX53_PAD_EIM_WAIT = 114,
> -       MX53_PAD_LVDS1_TX3_P = 115,
> -       MX53_PAD_LVDS1_TX2_P = 116,
> -       MX53_PAD_LVDS1_CLK_P = 117,
> -       MX53_PAD_LVDS1_TX1_P = 118,
> -       MX53_PAD_LVDS1_TX0_P = 119,
> -       MX53_PAD_LVDS0_TX3_P = 120,
> -       MX53_PAD_LVDS0_CLK_P = 121,
> -       MX53_PAD_LVDS0_TX2_P = 122,
> -       MX53_PAD_LVDS0_TX1_P = 123,
> -       MX53_PAD_LVDS0_TX0_P = 124,
> -       MX53_PAD_GPIO_10 = 125,
> -       MX53_PAD_GPIO_11 = 126,
> -       MX53_PAD_GPIO_12 = 127,
> -       MX53_PAD_GPIO_13 = 128,
> -       MX53_PAD_GPIO_14 = 129,
> -       MX53_PAD_NANDF_CLE = 130,
> -       MX53_PAD_NANDF_ALE = 131,
> -       MX53_PAD_NANDF_WP_B = 132,
> -       MX53_PAD_NANDF_RB0 = 133,
> -       MX53_PAD_NANDF_CS0 = 134,
> -       MX53_PAD_NANDF_CS1 = 135,
> -       MX53_PAD_NANDF_CS2 = 136,
> -       MX53_PAD_NANDF_CS3 = 137,
> -       MX53_PAD_FEC_MDIO = 138,
> -       MX53_PAD_FEC_REF_CLK = 139,
> -       MX53_PAD_FEC_RX_ER = 140,
> -       MX53_PAD_FEC_CRS_DV = 141,
> -       MX53_PAD_FEC_RXD1 = 142,
> -       MX53_PAD_FEC_RXD0 = 143,
> -       MX53_PAD_FEC_TX_EN = 144,
> -       MX53_PAD_FEC_TXD1 = 145,
> -       MX53_PAD_FEC_TXD0 = 146,
> -       MX53_PAD_FEC_MDC = 147,
> -       MX53_PAD_PATA_DIOW = 148,
> -       MX53_PAD_PATA_DMACK = 149,
> -       MX53_PAD_PATA_DMARQ = 150,
> -       MX53_PAD_PATA_BUFFER_EN = 151,
> -       MX53_PAD_PATA_INTRQ = 152,
> -       MX53_PAD_PATA_DIOR = 153,
> -       MX53_PAD_PATA_RESET_B = 154,
> -       MX53_PAD_PATA_IORDY = 155,
> -       MX53_PAD_PATA_DA_0 = 156,
> -       MX53_PAD_PATA_DA_1 = 157,
> -       MX53_PAD_PATA_DA_2 = 158,
> -       MX53_PAD_PATA_CS_0 = 159,
> -       MX53_PAD_PATA_CS_1 = 160,
> -       MX53_PAD_PATA_DATA0 = 161,
> -       MX53_PAD_PATA_DATA1 = 162,
> -       MX53_PAD_PATA_DATA2 = 163,
> -       MX53_PAD_PATA_DATA3 = 164,
> -       MX53_PAD_PATA_DATA4 = 165,
> -       MX53_PAD_PATA_DATA5 = 166,
> -       MX53_PAD_PATA_DATA6 = 167,
> -       MX53_PAD_PATA_DATA7 = 168,
> -       MX53_PAD_PATA_DATA8 = 169,
> -       MX53_PAD_PATA_DATA9 = 170,
> -       MX53_PAD_PATA_DATA10 = 171,
> -       MX53_PAD_PATA_DATA11 = 172,
> -       MX53_PAD_PATA_DATA12 = 173,
> -       MX53_PAD_PATA_DATA13 = 174,
> -       MX53_PAD_PATA_DATA14 = 175,
> -       MX53_PAD_PATA_DATA15 = 176,
> -       MX53_PAD_SD1_DATA0 = 177,
> -       MX53_PAD_SD1_DATA1 = 178,
> -       MX53_PAD_SD1_CMD = 179,
> -       MX53_PAD_SD1_DATA2 = 180,
> -       MX53_PAD_SD1_CLK = 181,
> -       MX53_PAD_SD1_DATA3 = 182,
> -       MX53_PAD_SD2_CLK = 183,
> -       MX53_PAD_SD2_CMD = 184,
> -       MX53_PAD_SD2_DATA3 = 185,
> -       MX53_PAD_SD2_DATA2 = 186,
> -       MX53_PAD_SD2_DATA1 = 187,
> -       MX53_PAD_SD2_DATA0 = 188,
> -       MX53_PAD_GPIO_0 = 189,
> -       MX53_PAD_GPIO_1 = 190,
> -       MX53_PAD_GPIO_9 = 191,
> -       MX53_PAD_GPIO_3 = 192,
> -       MX53_PAD_GPIO_6 = 193,
> -       MX53_PAD_GPIO_2 = 194,
> -       MX53_PAD_GPIO_4 = 195,
> -       MX53_PAD_GPIO_5 = 196,
> -       MX53_PAD_GPIO_7 = 197,
> -       MX53_PAD_GPIO_8 = 198,
> -       MX53_PAD_GPIO_16 = 199,
> -       MX53_PAD_GPIO_17 = 200,
> -       MX53_PAD_GPIO_18 = 201,
> +       MX53_PAD_GPIO_19 = 0,
> +       MX53_PAD_KEY_COL0 = 1,
> +       MX53_PAD_KEY_ROW0 = 2,
> +       MX53_PAD_KEY_COL1 = 3,
> +       MX53_PAD_KEY_ROW1 = 4,
> +       MX53_PAD_KEY_COL2 = 5,
> +       MX53_PAD_KEY_ROW2 = 6,
> +       MX53_PAD_KEY_COL3 = 7,
> +       MX53_PAD_KEY_ROW3 = 8,
> +       MX53_PAD_KEY_COL4 = 9,
> +       MX53_PAD_KEY_ROW4 = 10,
> +       MX53_PAD_DI0_DISP_CLK = 11,
> +       MX53_PAD_DI0_PIN15 = 12,
> +       MX53_PAD_DI0_PIN2 = 13,
> +       MX53_PAD_DI0_PIN3 = 14,
> +       MX53_PAD_DI0_PIN4 = 15,
> +       MX53_PAD_DISP0_DAT0 = 16,
> +       MX53_PAD_DISP0_DAT1 = 17,
> +       MX53_PAD_DISP0_DAT2 = 18,
> +       MX53_PAD_DISP0_DAT3 = 19,
> +       MX53_PAD_DISP0_DAT4 = 20,
> +       MX53_PAD_DISP0_DAT5 = 21,
> +       MX53_PAD_DISP0_DAT6 = 22,
> +       MX53_PAD_DISP0_DAT7 = 23,
> +       MX53_PAD_DISP0_DAT8 = 24,
> +       MX53_PAD_DISP0_DAT9 = 25,
> +       MX53_PAD_DISP0_DAT10 = 26,
> +       MX53_PAD_DISP0_DAT11 = 27,
> +       MX53_PAD_DISP0_DAT12 = 28,
> +       MX53_PAD_DISP0_DAT13 = 29,
> +       MX53_PAD_DISP0_DAT14 = 30,
> +       MX53_PAD_DISP0_DAT15 = 31,
> +       MX53_PAD_DISP0_DAT16 = 32,
> +       MX53_PAD_DISP0_DAT17 = 33,
> +       MX53_PAD_DISP0_DAT18 = 34,
> +       MX53_PAD_DISP0_DAT19 = 35,
> +       MX53_PAD_DISP0_DAT20 = 36,
> +       MX53_PAD_DISP0_DAT21 = 37,
> +       MX53_PAD_DISP0_DAT22 = 38,
> +       MX53_PAD_DISP0_DAT23 = 39,
> +       MX53_PAD_CSI0_PIXCLK = 40,
> +       MX53_PAD_CSI0_MCLK = 41,
> +       MX53_PAD_CSI0_DATA_EN = 42,
> +       MX53_PAD_CSI0_VSYNC = 43,
> +       MX53_PAD_CSI0_DAT4 = 44,
> +       MX53_PAD_CSI0_DAT5 = 45,
> +       MX53_PAD_CSI0_DAT6 = 46,
> +       MX53_PAD_CSI0_DAT7 = 47,
> +       MX53_PAD_CSI0_DAT8 = 48,
> +       MX53_PAD_CSI0_DAT9 = 49,
> +       MX53_PAD_CSI0_DAT10 = 50,
> +       MX53_PAD_CSI0_DAT11 = 51,
> +       MX53_PAD_CSI0_DAT12 = 52,
> +       MX53_PAD_CSI0_DAT13 = 53,
> +       MX53_PAD_CSI0_DAT14 = 54,
> +       MX53_PAD_CSI0_DAT15 = 55,
> +       MX53_PAD_CSI0_DAT16 = 56,
> +       MX53_PAD_CSI0_DAT17 = 57,
> +       MX53_PAD_CSI0_DAT18 = 58,
> +       MX53_PAD_CSI0_DAT19 = 59,
> +       MX53_PAD_EIM_A25 = 60,
> +       MX53_PAD_EIM_EB2 = 61,
> +       MX53_PAD_EIM_D16 = 62,
> +       MX53_PAD_EIM_D17 = 63,
> +       MX53_PAD_EIM_D18 = 64,
> +       MX53_PAD_EIM_D19 = 65,
> +       MX53_PAD_EIM_D20 = 66,
> +       MX53_PAD_EIM_D21 = 67,
> +       MX53_PAD_EIM_D22 = 68,
> +       MX53_PAD_EIM_D23 = 69,
> +       MX53_PAD_EIM_EB3 = 70,
> +       MX53_PAD_EIM_D24 = 71,
> +       MX53_PAD_EIM_D25 = 72,
> +       MX53_PAD_EIM_D26 = 73,
> +       MX53_PAD_EIM_D27 = 74,
> +       MX53_PAD_EIM_D28 = 75,
> +       MX53_PAD_EIM_D29 = 76,
> +       MX53_PAD_EIM_D30 = 77,
> +       MX53_PAD_EIM_D31 = 78,
> +       MX53_PAD_EIM_A24 = 79,
> +       MX53_PAD_EIM_A23 = 80,
> +       MX53_PAD_EIM_A22 = 81,
> +       MX53_PAD_EIM_A21 = 82,
> +       MX53_PAD_EIM_A20 = 83,
> +       MX53_PAD_EIM_A19 = 84,
> +       MX53_PAD_EIM_A18 = 85,
> +       MX53_PAD_EIM_A17 = 86,
> +       MX53_PAD_EIM_A16 = 87,
> +       MX53_PAD_EIM_CS0 = 88,
> +       MX53_PAD_EIM_CS1 = 89,
> +       MX53_PAD_EIM_OE = 90,
> +       MX53_PAD_EIM_RW = 91,
> +       MX53_PAD_EIM_LBA = 92,
> +       MX53_PAD_EIM_EB0 = 93,
> +       MX53_PAD_EIM_EB1 = 94,
> +       MX53_PAD_EIM_DA0 = 95,
> +       MX53_PAD_EIM_DA1 = 96,
> +       MX53_PAD_EIM_DA2 = 97,
> +       MX53_PAD_EIM_DA3 = 98,
> +       MX53_PAD_EIM_DA4 = 99,
> +       MX53_PAD_EIM_DA5 = 100,
> +       MX53_PAD_EIM_DA6 = 101,
> +       MX53_PAD_EIM_DA7 = 102,
> +       MX53_PAD_EIM_DA8 = 103,
> +       MX53_PAD_EIM_DA9 = 104,
> +       MX53_PAD_EIM_DA10 = 105,
> +       MX53_PAD_EIM_DA11 = 106,
> +       MX53_PAD_EIM_DA12 = 107,
> +       MX53_PAD_EIM_DA13 = 108,
> +       MX53_PAD_EIM_DA14 = 109,
> +       MX53_PAD_EIM_DA15 = 110,
> +       MX53_PAD_NANDF_WE_B = 111,
> +       MX53_PAD_NANDF_RE_B = 112,
> +       MX53_PAD_EIM_WAIT = 113,
> +       MX53_PAD_LVDS1_TX3_P = 114,
> +       MX53_PAD_LVDS1_TX2_P = 115,
> +       MX53_PAD_LVDS1_CLK_P = 116,
> +       MX53_PAD_LVDS1_TX1_P = 117,
> +       MX53_PAD_LVDS1_TX0_P = 118,
> +       MX53_PAD_LVDS0_TX3_P = 119,
> +       MX53_PAD_LVDS0_CLK_P = 120,
> +       MX53_PAD_LVDS0_TX2_P = 121,
> +       MX53_PAD_LVDS0_TX1_P = 122,
> +       MX53_PAD_LVDS0_TX0_P = 123,
> +       MX53_PAD_GPIO_10 = 124,
> +       MX53_PAD_GPIO_11 = 125,
> +       MX53_PAD_GPIO_12 = 126,
> +       MX53_PAD_GPIO_13 = 127,
> +       MX53_PAD_GPIO_14 = 128,
> +       MX53_PAD_NANDF_CLE = 129,
> +       MX53_PAD_NANDF_ALE = 130,
> +       MX53_PAD_NANDF_WP_B = 131,
> +       MX53_PAD_NANDF_RB0 = 132,
> +       MX53_PAD_NANDF_CS0 = 133,
> +       MX53_PAD_NANDF_CS1 = 134,
> +       MX53_PAD_NANDF_CS2 = 135,
> +       MX53_PAD_NANDF_CS3 = 136,
> +       MX53_PAD_FEC_MDIO = 137,
> +       MX53_PAD_FEC_REF_CLK = 138,
> +       MX53_PAD_FEC_RX_ER = 139,
> +       MX53_PAD_FEC_CRS_DV = 140,
> +       MX53_PAD_FEC_RXD1 = 141,
> +       MX53_PAD_FEC_RXD0 = 142,
> +       MX53_PAD_FEC_TX_EN = 143,
> +       MX53_PAD_FEC_TXD1 = 144,
> +       MX53_PAD_FEC_TXD0 = 145,
> +       MX53_PAD_FEC_MDC = 146,
> +       MX53_PAD_PATA_DIOW = 147,
> +       MX53_PAD_PATA_DMACK = 148,
> +       MX53_PAD_PATA_DMARQ = 149,
> +       MX53_PAD_PATA_BUFFER_EN = 150,
> +       MX53_PAD_PATA_INTRQ = 151,
> +       MX53_PAD_PATA_DIOR = 152,
> +       MX53_PAD_PATA_RESET_B = 153,
> +       MX53_PAD_PATA_IORDY = 154,
> +       MX53_PAD_PATA_DA_0 = 155,
> +       MX53_PAD_PATA_DA_1 = 156,
> +       MX53_PAD_PATA_DA_2 = 157,
> +       MX53_PAD_PATA_CS_0 = 158,
> +       MX53_PAD_PATA_CS_1 = 159,
> +       MX53_PAD_PATA_DATA0 = 160,
> +       MX53_PAD_PATA_DATA1 = 161,
> +       MX53_PAD_PATA_DATA2 = 162,
> +       MX53_PAD_PATA_DATA3 = 163,
> +       MX53_PAD_PATA_DATA4 = 164,
> +       MX53_PAD_PATA_DATA5 = 165,
> +       MX53_PAD_PATA_DATA6 = 166,
> +       MX53_PAD_PATA_DATA7 = 167,
> +       MX53_PAD_PATA_DATA8 = 168,
> +       MX53_PAD_PATA_DATA9 = 169,
> +       MX53_PAD_PATA_DATA10 = 170,
> +       MX53_PAD_PATA_DATA11 = 171,
> +       MX53_PAD_PATA_DATA12 = 172,
> +       MX53_PAD_PATA_DATA13 = 173,
> +       MX53_PAD_PATA_DATA14 = 174,
> +       MX53_PAD_PATA_DATA15 = 175,
> +       MX53_PAD_SD1_DATA0 = 176,
> +       MX53_PAD_SD1_DATA1 = 177,
> +       MX53_PAD_SD1_CMD = 178,
> +       MX53_PAD_SD1_DATA2 = 179,
> +       MX53_PAD_SD1_CLK = 180,
> +       MX53_PAD_SD1_DATA3 = 181,
> +       MX53_PAD_SD2_CLK = 182,
> +       MX53_PAD_SD2_CMD = 183,
> +       MX53_PAD_SD2_DATA3 = 184,
> +       MX53_PAD_SD2_DATA2 = 185,
> +       MX53_PAD_SD2_DATA1 = 186,
> +       MX53_PAD_SD2_DATA0 = 187,
> +       MX53_PAD_GPIO_0 = 188,
> +       MX53_PAD_GPIO_1 = 189,
> +       MX53_PAD_GPIO_9 = 190,
> +       MX53_PAD_GPIO_3 = 191,
> +       MX53_PAD_GPIO_6 = 192,
> +       MX53_PAD_GPIO_2 = 193,
> +       MX53_PAD_GPIO_4 = 194,
> +       MX53_PAD_GPIO_5 = 195,
> +       MX53_PAD_GPIO_7 = 196,
> +       MX53_PAD_GPIO_8 = 197,
> +       MX53_PAD_GPIO_16 = 198,
> +       MX53_PAD_GPIO_17 = 199,
> +       MX53_PAD_GPIO_18 = 200,
>  };
>
>  /* imx53 register maps */
> --
> 1.7.5.4
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From shawn.guo at linaro.org  Mon Aug 13 11:15:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 23:15:11 +0800
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <20120705074623.GG10610@S2101-09.ap.freescale.net>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705071318.GO30009@pengutronix.de>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
Message-ID: <20120813151509.GB27393@S2101-09.ap.freescale.net>

On Thu, Jul 05, 2012 at 03:46:23PM +0800, Shawn Guo wrote:
> On Thu, Jul 05, 2012 at 09:13:18AM +0200, Sascha Hauer wrote:
> > Shawn,
> > 
> > Is this ok with you?
> > 
> No.
> 
> http://thread.gmane.org/gmane.linux.ports.arm.kernel/172558/focus=172703
> 
I change my mind.  Though it's really a pity to lose a concentrated
place maintaining a full list of compatible strings of all supported
board, I'm more concerned by the dt_board_compat matching efficiency
when the table gets longer.

So, Fabio, can you please resend the patches against v3.6-rc?

-- 
Regards,
Shawn



From marex at denx.de  Mon Aug 13 11:18:14 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 13 Aug 2012 17:18:14 +0200
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <20120813151509.GB27393@S2101-09.ap.freescale.net>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
Message-ID: <201208131718.14546.marex@denx.de>

Dear Shawn Guo,

> On Thu, Jul 05, 2012 at 03:46:23PM +0800, Shawn Guo wrote:
> > On Thu, Jul 05, 2012 at 09:13:18AM +0200, Sascha Hauer wrote:
> > > Shawn,
> > > 
> > > Is this ok with you?
> > 
> > No.
> > 
> > http://thread.gmane.org/gmane.linux.ports.arm.kernel/172558/focus=172703
> 
> I change my mind.  Though it's really a pity to lose a concentrated
> place maintaining a full list of compatible strings of all supported
> board, I'm more concerned by the dt_board_compat matching efficiency
> when the table gets longer.
> 
> So, Fabio, can you please resend the patches against v3.6-rc?

What about the board quirks that are present there?

Best regards,
Marek Vasut


From cjb at laptop.org  Mon Aug 13 11:23:38 2012
From: cjb at laptop.org (Chris Ball)
Date: Mon, 13 Aug 2012 11:23:38 -0400
Subject: [PATCH 00/10 V3] MXS SPI driver
In-Reply-To: <20120813140803.GB6407@S2101-09.ap.freescale.net> (Shawn Guo's
 message of "Mon, 13 Aug 2012 22:08:05 +0800")
References: <1344007575-11448-1-git-send-email-marex@denx.de>
 <20120813125158.GE13446@opensource.wolfsonmicro.com>
 <20120813140803.GB6407@S2101-09.ap.freescale.net>
Message-ID: <87sjbqlssl.fsf@octavius.laptop.org>

Hi,

On Mon, Aug 13 2012, Shawn Guo wrote:
> On Mon, Aug 13, 2012 at 01:51:58PM +0100, Mark Brown wrote:
>> Do we have any ETA for review from the MMC side?  I'd like to get these
>> patches out of my queue one way or another, it seems like for the simple
>> code motion bits at least we should be easy enough to get out of the
>> way.
>
> For mxs-mmc part:
>
> Reviewed-by: Shawn Guo <shawn.guo at linaro.org>
>
> Chris,
>
> Can you take a look at the series and give your ACK to bless it go via
> SPI tree?

Thanks, looks good.  For the SPI tree:

Acked-by: Chris Ball <cjb at laptop.org>

-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From marc.zyngier at arm.com  Mon Aug 13 11:30:23 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Mon, 13 Aug 2012 16:30:23 +0100
Subject: [PATCH v2 1/2] ARM: arch_timers: enable the use of the virtual
 timer
In-Reply-To: <50266C23.7040802@ti.com>
References: <1344681091-12652-1-git-send-email-marc.zyngier@arm.com>
 <1344681091-12652-2-git-send-email-marc.zyngier@arm.com>
 <50266C23.7040802@ti.com>
Message-ID: <50291D8F.8000103@arm.com>

On 11/08/12 15:28, Cyril Chemparathy wrote:
> On 8/11/2012 6:31 AM, Marc Zyngier wrote:
>> At the moment, the arch_timer driver only uses the physical timer,
>> which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
>> which is likely in a virtualized environment. Instead, the virtual
>> timer is always available.
>>
>> This patch enables the use of both the virtual timer, unless no
>> interrupt is provided in the DT for it, in which case is falls
>> back to the physical timer.
>>
> 
> I'm curious about the cost of the added pointer chasing introduced by 
> this patch.
> 
> The original code gets nicely inlined by the compiler, and this hides 
> all the switch-case register index stuff.  For instance:
> 
>   10797 c001288c <arch_timer_set_next_event>:
>   10798 c001288c:       ee1e3f32        mrc     15, 0, r3, cr14, cr2, {1}
>   10799 c0012890:       e3c33002        bic     r3, r3, #2
>   10800 c0012894:       ee0e0f12        mcr     15, 0, r0, cr14, cr2, {0}
>   10801 c0012898:       f57ff06f        isb     sy
>   10802 c001289c:       e3833001        orr     r3, r3, #1
>   10803 c00128a0:       ee0e3f32        mcr     15, 0, r3, cr14, cr2, {1}
>   10804 c00128a4:       f57ff06f        isb     sy
>   10805 c00128a8:       e3a00000        mov     r0, #0
>   10806 c00128ac:       e12fff1e        bx      lr
> 
> With the added pointer chasing, we unfortunately lose out on all the 
> work that the compiler used to do for us.  We now end up having to snake 
> our way through the following:

[...]

Yup, that doesn't look too good.

> I think we'd be better off separating between these (virt, phys, ...) 
> implementations at a higher level of operations (set_mode, 
> set_next_event, ...) rather than separating at a register operations 
> level as you have in this patch.

This approach leads to a lot of code duplication, unless we do some ugly
preprocessor hackery (see patch attached). I then get much better code
(smaller, faster), but I'm not sure we want to live with this...

	M.
-- 
Jazz is not dead. It just smells funny...
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From u.kleine-koenig at pengutronix.de  Mon Aug 13 11:35:03 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 13 Aug 2012 17:35:03 +0200
Subject: [PATCH v2 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120813081518.GA27480@S2101-09.ap.freescale.net>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120813081518.GA27480@S2101-09.ap.freescale.net>
Message-ID: <20120813153503.GC2232@pengutronix.de>

Hi Shawn,

On Mon, Aug 13, 2012 at 04:15:21PM +0800, Shawn Guo wrote:
> On Fri, Aug 10, 2012 at 11:32:49AM +0200, Uwe Kleine-K?nig wrote:
> > +		emi at 80000000 { /* External Memory Interface */
> > +			compatible = "fsl,emi", "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x80000000 0x40000000>;
> > +			ranges;
> > +
> > +			nand at bb000000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <1>;
> > +
> These should not be needed, until you will have sub-nodes with "reg"
> property.

The obvious sub-nodes are partitions. I thought it sensible to already
add #address-cells and #size-cells because they are identical for all
users and so repeating is minimized.

> > +				compatible = "fsl,imx35-nand", "fsl,imx25-nand";
> > +				reg = <0xbb000000 0x2000>;
> > +				interrupts = <33>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +	};
> > +};
> > [...]
> > +	imx3_init_l2x0();
> 
> Any problem with using l2x0_of_init instead here?
Yeah, the problem is that I never used l2x0_of_init and so it's
unimplemented and untested on i.MX35 :-)

I will take a look.

> > +	pinctrl_provide_dummies();
> 
> Ideally, we should not have this.  But at least have a comment saying
> this is a stop-gap solution before pinctrl is ready, and should be
> removed once pinctrl is in place.
I will look into this, too.

Thanks for your feedback,
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linux at arm.linux.org.uk  Mon Aug 13 11:35:54 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 13 Aug 2012 16:35:54 +0100
Subject: [PATCH v2 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock
 parenting code to ASoC driver
In-Reply-To: <1344867768-26335-2-git-send-email-peter.ujfalusi@ti.com>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
 <1344867768-26335-2-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120813153554.GA31662@n2100.arm.linux.org.uk>

On Mon, Aug 13, 2012 at 05:22:40PM +0300, Peter Ujfalusi wrote:
> +	fck_src = clk_get(mcbsp->dev, src);
> +	if (IS_ERR_OR_NULL(fck_src)) {

I know the same error is in the original code, but let's stop propagating
it.  IS_ERR() only here please.


From ludovic.desroches at atmel.com  Mon Aug 13 11:38:53 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Mon, 13 Aug 2012 17:38:53 +0200
Subject: [PATCH 0/1] ARM: at91: fix drivers broken because of sparse irq
 support
Message-ID: <1344872334-1532-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Hello,

This patch fixes the rm9200 breakage (introduced by sparse irq support) reported
by Joachim Eastwood.

Regards

Ludovic

Ludovic Desroches (1):
  ARM: at91: fix drivers broken because of sparse irq support

 arch/arm/mach-at91/at91rm9200_time.c |  2 +-
 drivers/rtc/rtc-at91sam9.c           | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

-- 
1.7.11.3



From ludovic.desroches at atmel.com  Mon Aug 13 11:38:54 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Mon, 13 Aug 2012 17:38:54 +0200
Subject: [PATCH] ARM: at91: fix drivers broken because of sparse irq support
In-Reply-To: <1344872334-1532-1-git-send-email-ludovic.desroches@atmel.com>
References: <1344872334-1532-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1344872334-1532-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Some drivers directly use AT91_ID_SYS as virq so they are broken because of
the NR_IRQS_LEGACY virq offset introduced with sparse irq support.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: stable at vger.kernel.org
---
 arch/arm/mach-at91/at91rm9200_time.c |  2 +-
 drivers/rtc/rtc-at91sam9.c           | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40..aaa443b 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
 	at91_st_read(AT91_ST_SR);
 
 	/* Make IRQs happen for the system timer */
-	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
+	setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
 
 	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
 	 * directly for the clocksource and all clockevents, after adjusting
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 8318689..2969047 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -345,11 +345,12 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
 	}
 
 	/* register irq handler after we know what name we'll use */
-	ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
+	ret = request_irq(NR_IRQS_LEGACY + AT91_ID_SYS, at91_rtc_interrupt,
 				IRQF_SHARED,
 				dev_name(&rtc->rtcdev->dev), rtc);
 	if (ret) {
-		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", AT91_ID_SYS);
+		dev_dbg(&pdev->dev, "can't share IRQ %d?\n",
+			NR_IRQS_LEGACY + AT91_ID_SYS);
 		rtc_device_unregister(rtc->rtcdev);
 		goto fail_register;
 	}
@@ -386,7 +387,7 @@ static int __devexit at91_rtc_remove(struct platform_device *pdev)
 
 	/* disable all interrupts */
 	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
-	free_irq(AT91_ID_SYS, rtc);
+	free_irq(NR_IRQS_LEGACY + AT91_ID_SYS, rtc);
 
 	rtc_device_unregister(rtc->rtcdev);
 
@@ -423,7 +424,7 @@ static int at91_rtc_suspend(struct platform_device *pdev,
 	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
 	if (rtc->imr) {
 		if (device_may_wakeup(&pdev->dev) && (mr & AT91_RTT_ALMIEN)) {
-			enable_irq_wake(AT91_ID_SYS);
+			enable_irq_wake(NR_IRQS_LEGACY + AT91_ID_SYS);
 			/* don't let RTTINC cause wakeups */
 			if (mr & AT91_RTT_RTTINCIEN)
 				rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
@@ -441,7 +442,7 @@ static int at91_rtc_resume(struct platform_device *pdev)
 
 	if (rtc->imr) {
 		if (device_may_wakeup(&pdev->dev))
-			disable_irq_wake(AT91_ID_SYS);
+			disable_irq_wake(NR_IRQS_LEGACY + AT91_ID_SYS);
 		mr = rtt_readl(rtc, MR);
 		rtt_writel(rtc, MR, mr | rtc->imr);
 	}
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Mon Aug 13 11:43:30 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 13 Aug 2012 17:43:30 +0200
Subject: AT91 RM9200 hangs on delay loop calibration
In-Reply-To: <CAGhQ9Vyvr7bDU8cNirGuTkhsH1LhHPRjehftOwwSnox+i1b=5A@mail.gmail.com>
References: <CAGhQ9Vyvr7bDU8cNirGuTkhsH1LhHPRjehftOwwSnox+i1b=5A@mail.gmail.com>
Message-ID: <502920A2.9090100@atmel.com>

Hi Joachim,

Le 08/11/2012 07:06 PM, Joachim Eastwood a ?crit :
> Hi,
>
> My custom AT91 RM9200 board hangs on delay loop calibration. There it
> seems to be stuck and the last message printed is:
> [    0.000000] Calibrating delay loop...
>
> Doing a manual bisect I can get the board to boot again when I revert
> the following commits from Linus master:
> 14070ade02cc378bc30dae383532768a94805988 - ARM: at91: fix new build errors
> c4b68520dc0ec96153bc0d87bca5ffba508edfcf - ARM: at91: add AIC5 support
> 4c6971a6debb340d487cf6189f15a1332702330f - ARM: at91: remove mach/irqs.h
> 8fe82a5550a8e97b3f59c74f994b88ed6b3544a3 - ARM: at91: sparse irq support
> 3e135466745a62b1814edef74c7b4a25e6bda707 - ARM: at91: at91 based
> machines specify their own irq handler at run time
>
> There may be some unnecessary reverts here but there are multiple
> build failures between the different commits (grrrrr) which makes it
> pain to filter it out.
>
> I suspect that right now all AT91 RM9200 machines are broken by these
> IRQ changes on AT91.
>
> regards
> Joachim Eastwood
>
>

Thanks for this report. I have just sent a patch to correct the rm9200 
breakage.

Regards

Ludovic



From matt at genesi-usa.com  Mon Aug 13 11:42:58 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 13 Aug 2012 10:42:58 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120809101947.GA8474@sirena.org.uk>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120809101947.GA8474@sirena.org.uk>
Message-ID: <CAKGA1bkwMvDW7nMWxUbNm3_0ZTR2+uKs8UL_HuisJe7cd8POBA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:19 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Aug 07, 2012 at 04:46:18PM -0500, Matt Sealey wrote:
>
> Yay for indentation!  It'd be good to rewrite your DT so you could cut
> down on that, at the minute it's not good for legibility.
>
>> +                                                     sw1_reg: sw1 {
>> +                                                             regulator-min-microvolt = <600000>;
>> +                                                             regulator-max-microvolt = <1375000>;
>> +                                                             regulator-boot-on;
>> +                                                             regulator-always-on;
>> +                                                     };
>
> This and many of your other regulators have voltage ranges specified but
> no consumers which doesn't make sense.  It looks awfully like you've
> just typed in the maximum range supported by the regulator which is most
> likely broken.

Okay I have a question about this; some of the regulators (SW1
especially) are obviously consumed by the CPU core complex so that
when DVFS gives us a hint we can clock down and reduce voltage. How on
earth do we implement that?

We can drop the maximum range to be better for the CPU (1.3V is too
high, I think this is legacy from when we may have had a sorted 1GHz
MX51 coming out) but I can't find any source for where this is hooked
in.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From linux at arm.linux.org.uk  Mon Aug 13 12:00:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 13 Aug 2012 17:00:08 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <5029126C.5000202@arm.com>
References: <1613427331.1190769.1344577949008.JavaMail.root@mozilla.com>
 <5029126C.5000202@arm.com>
Message-ID: <20120813160008.GA30302@n2100.arm.linux.org.uk>

On Mon, Aug 13, 2012 at 03:42:52PM +0100, Jonathan Austin wrote:
> On my system the cacheflush(2) documentation suggests it is MIPS only:
> "This  Linux-specific  system call is only available on MIPS based
> systems.  It should not be used in programs intended to be portable."

It's been part of the ARM kernel API for a very long time.

> As you've established by looking at the code, on ARM we intentionally
> attempt to flush only the part of the given range that occurs inside the
> vma containing 'start'.

It's intention is to support self-modifying userspace code only and also
intended to be used over a _short_ range of addresses only - it works by
flushing each _individual_ cache line over the range of addreses
requested.

If it's going to be used for significantly larger areas, then we need to
think about imposing a limit, upon which we just flush the entire cache
and be done with it.


From festevam at gmail.com  Mon Aug 13 12:56:40 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 13 Aug 2012 13:56:40 -0300
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <20120813151509.GB27393@S2101-09.ap.freescale.net>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705071318.GO30009@pengutronix.de>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
Message-ID: <CAOMZO5C4f11jyvk_5sHAfwUKmybmgX91de3Mv+jaEmTuSMGpnA@mail.gmail.com>

On Mon, Aug 13, 2012 at 12:15 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> So, Fabio, can you please resend the patches against v3.6-rc?

Which branch at git.linaro.org should I use it to rebase?

Regards,

Fabio Estevam


From wade_farnsworth at mentor.com  Mon Aug 13 13:03:39 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 13 Aug 2012 10:03:39 -0700
Subject: [PATCH] ARM: support syscall tracing
Message-ID: <5029336B.2050305@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
__sys_trace was modified to call trace_sys_enter and
trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
---

This patch is an update of one I posted some months ago.  It has been
rebased to Linus's current HEAD.

 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    2 ++
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |   12 +++++++++++-
 arch/arm/kernel/ptrace.c           |   23 ++++++++++++++++++-----
 6 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..983e9eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bd..d3e4410 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -154,6 +154,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_RESTORE_SIGMASK	20
 #define TIF_SECCOMP		21
 #define TIF_SWITCH_MM		22	/* deferred switch_mm */
+#define TIF_SYSCALL_TRACEPOINT	23
 
 #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
@@ -163,6 +164,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 
 /* Checks for any syscall work in entry-common.S */
 #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0cab47d..a566ec2 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac5..51b64c1 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
@@ -415,7 +424,8 @@ local_restart:
 1:
 #endif
 
-	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	tst     r10, #_TIF_SYSCALL_WORK
+	tsteq   r10, #_TIF_SYSCALL_TRACEPOINT
 	bne	__sys_trace
 
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f..a2d46ed 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -918,7 +921,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
 	unsigned long ip;
 
-	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
+	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 		return scno;
 
 	current_thread_info()->syscall = scno;
@@ -930,10 +934,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 	ip = regs->ARM_ip;
 	regs->ARM_ip = dir;
 
-	if (dir == PTRACE_SYSCALL_EXIT)
-		tracehook_report_syscall_exit(regs, 0);
-	else if (tracehook_report_syscall_entry(regs))
-		current_thread_info()->syscall = -1;
+	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+		if (dir == PTRACE_SYSCALL_EXIT)
+			tracehook_report_syscall_exit(regs, 0);
+		else if (tracehook_report_syscall_entry(regs))
+			current_thread_info()->syscall = -1;
+	}
+
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) {
+		if (dir == PTRACE_SYSCALL_EXIT)
+			trace_sys_exit(regs, scno);
+		else
+			trace_sys_enter(regs, scno);
+	}
 
 	regs->ARM_ip = ip;
 	return current_thread_info()->syscall;
-- 
1.7.0.4



From thomas.petazzoni at free-electrons.com  Mon Aug 13 13:34:41 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 13 Aug 2012 19:34:41 +0200
Subject: [PATCH 1/5] gpio: introduce gpio-mvebu driver for Marvell SoCs
In-Reply-To: <20120813051809.GA8836@game.jcrosoft.org>
References: <1344705034-18173-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1344705034-18173-2-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120813051809.GA8836@game.jcrosoft.org>
Message-ID: <20120813193441.16abed76@skate>

Hello,

Thanks Jean-Christophe for this review!

Le Mon, 13 Aug 2012 07:18:09 +0200,
Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> a ?crit :

> > +/*
> > + * Common functions to all SoCs
> > + */
> > +static void __iomem *GPIO_OUT(struct mvebu_gpio_chip *mvchip)
> please use inline and do not use upper case for function

Yes agreed. Those upper-case functions come directly from the previous
driver in plat-orion/gpio.c, but I was also not really happy with them.
Will change it for the next version.

> in the code pelease use relaxed readl/writel

Ok.

> > +	/* Check with the pinctrl driver whether this pin is usable as
> > +	 * an input GPIO */
> > +	ret = pinctrl_gpio_direction_input(chip->base + pin);
> this will de the configuration

No, it will not do the configuration. On Marvell SoCs:

 * The MPP unit allows to configure the pin muxing only. This unit is
   managed by the pinctrl driver.

 * The GPIO unit allows to configure whether a GPIO is input/output,
   set the level, configure GPIO interrupts. This unit is managed by
   the GPIO driver.

Those two units have distinct register ranges, so we cannot easily
migrate the GPIO direction configuration to the pinctrl driver without
doing some ugly things.

So, in terms of GPIO direction, the pinctrl driver is only responsible
for telling the GPIO driver whether a particular pin *can* be
configured as input or output (because this is something we encode in
the pinctrl driver in the pins list). However, *configuring* the
direction must be done by the GPIO driver.

> > +	if (ret)
> > +		return ret;
> > +
> > +	spin_lock_irqsave(&mvchip->lock, flags);
> > +	u = readl(GPIO_IO_CONF(mvchip));
> > +	u |= 1 << pin;
> > +	writel(u, GPIO_IO_CONF(mvchip));
> why this?

See above, it configures the GPIO direction.

> > +	/*
> > +	 * Configure interrupt polarity.
> > +	 */
> > +	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
> > +		u = readl(GPIO_IN_POL(mvchip));
> > +		u &= ~(1 << pin);
> > +		writel(u, GPIO_IN_POL(mvchip));
> > +	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
> > +		u = readl(GPIO_IN_POL(mvchip));
> > +		u |= 1 << pin;
> > +		writel(u, GPIO_IN_POL(mvchip));
> > +	} else if (type == IRQ_TYPE_EDGE_BOTH) {
> > +		u32 v;
> switch will make the code cleaner

Agreed, will change.

> > +static struct platform_device_id mvebu_gpio_ids[] = {
> > +	{
> > +		.name = "orion-gpio",
> > +	}, {
> > +		.name = "mv78200-gpio",
> > +	}, {
> > +		.name = "armadaxp-gpio",
> why here to0?

to0 ?

> you already detect it via DT

Hmm, not sure what you mean here. Can you expand a bit your comment?

> > +	mvchip->chip.to_irq = mvebu_gpio_to_irq;
> > +	mvchip->chip.base = mvebu_gpio_chip_count * 32;
> why you don't use the auto allocated gpio number?

Ah, didn't know there was one. Will look into this!

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From manabian at gmail.com  Mon Aug 13 13:37:54 2012
From: manabian at gmail.com (Joachim Eastwood)
Date: Mon, 13 Aug 2012 19:37:54 +0200
Subject: [PATCH] ARM: at91: fix drivers broken because of sparse irq
 support
In-Reply-To: <1344872334-1532-2-git-send-email-ludovic.desroches@atmel.com>
References: <1344872334-1532-1-git-send-email-ludovic.desroches@atmel.com>
 <1344872334-1532-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <CAGhQ9Vw_CvC71n=9Pr6SY0qsSmFVFTn76BVRbh64RP80G6pyZQ@mail.gmail.com>

Hi Ludovic,

On Mon, Aug 13, 2012 at 5:38 PM,  <ludovic.desroches at atmel.com> wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Some drivers directly use AT91_ID_SYS as virq so they are broken because of
> the NR_IRQS_LEGACY virq offset introduced with sparse irq support.

This patch makes my board boot again. Thanks.

Feel free to add;
Tested-by: Joachim Eastwood <joachim.eastwood at jotron.com>

> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: stable at vger.kernel.org

Why are you sending this to stable?
This is a regression only in 3.6 and should go upstream ASAP.

regards
Joachim Eastwood


From broonie at opensource.wolfsonmicro.com  Mon Aug 13 13:38:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 13 Aug 2012 18:38:47 +0100
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <CAKGA1bkwMvDW7nMWxUbNm3_0ZTR2+uKs8UL_HuisJe7cd8POBA@mail.gmail.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120809101947.GA8474@sirena.org.uk>
 <CAKGA1bkwMvDW7nMWxUbNm3_0ZTR2+uKs8UL_HuisJe7cd8POBA@mail.gmail.com>
Message-ID: <20120813173847.GH13446@opensource.wolfsonmicro.com>

On Mon, Aug 13, 2012 at 10:42:58AM -0500, Matt Sealey wrote:
> On Thu, Aug 9, 2012 at 5:19 AM, Mark Brown

> > This and many of your other regulators have voltage ranges specified but
> > no consumers which doesn't make sense.  It looks awfully like you've
> > just typed in the maximum range supported by the regulator which is most
> > likely broken.

> Okay I have a question about this; some of the regulators (SW1
> especially) are obviously consumed by the CPU core complex so that
> when DVFS gives us a hint we can clock down and reduce voltage. How on
> earth do we implement that?

> We can drop the maximum range to be better for the CPU (1.3V is too
> high, I think this is legacy from when we may have had a sorted 1GHz
> MX51 coming out) but I can't find any source for where this is hooked
> in.

DVFS doesn't use the device model in Linux (yet!) so there's no device
node and it's all a bit messy.  Shawn Guo is working on some generic DT
bindings for it which should solve that problem but for now in the
specific case of CPU bindings it's OK to not have an consumer, it's
understandable what's going on there.


From thierry.reding at avionic-design.de  Mon Aug 13 13:40:03 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 13 Aug 2012 19:40:03 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <50201E1D.5060200@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
Message-ID: <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> > This patch series adds support for device tree based probing of the PCIe
> > controller found on Tegra SoCs.
> 
> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed that
> PCIe doesn't work on TrimSlice when booting use device tree. I think I
> found the cause, and I can't see why the same problem doesn't affect
> this series. Perhaps you can enlighten me?
> 
> When booting TrimSlice (or Harmony) using board files, Tegra's PCIe is
> initialized using a subsys_initcall to tegra_pcie_init() directly (or
> for Harmony to harmony_pcie_init() which then calls tegra_pcie_init()).
> 
> The final thing tegra_pcie_init() does is call pci_common_init(). This
> calls pcibios_init_hw() which calls hw->scan() which calls
> pci_scan_root_bus() which adds a device object for each device on the
> PCIe bus. However, since this happens very early in the boot sequence, I
> believe the enumerated PCIe devices don't immediately get probed.
> Instead, control gets returned to pci_common_init() which I believe then
> calls pci_bus_assign_resources() which actually sets up the resources
> for those devices. Later, the PCIe devices actually get probed, and
> everything works.
> 
> However, when booting using device tree, with the code currently in
> v3.6-rc1, tegra_pcie_init() is called late in the boot sequence, and so
> in the sequence described above, as soon as pci_scan_root_bus() adds a
> device, it gets probed, before the device object's resources have been
> set up, which results in the following failure:
> 
> PCI: Device 0000:01:00.0 not available because of resource collisions
> 
> ... because of the following code in pcibios_enable_device():
> 
> > 	for (idx = 0; idx < 6; idx++) {
> > 		/* Only set up the requested stuff */
> > 		if (!(mask & (1 << idx)))
> > 			continue;
> > 
> > 		r = dev->resource + idx;
> > 		if (!r->start && r->end) {
> > 			printk(KERN_ERR "PCI: Device %s not available because"
> > 			       " of resource collisions\n", pci_name(dev));
> 
> Doesn't this same problem exist when instantiating the PCIe device
> itself from device tree as in your patch series? If not, can you explain
> why?
> 
> Now, the obvious solution in v3.6 would be to simply have
> tegra_pcie_init() be called at the same early stage in the boot process
> when booting using device tree as it is when booting using board files.
> This works for TrimSlice.
> 
> However, on Harmony, it doesn't work, because PCIe on Harmony depends on
> regulators, and the regulators are accessed using an I2C bus that is
> instantiated from DT, and the instantiation of the I2C bus happens
> fairly late in the boot process so can't be found early during the boot
> sequence. See harmony_regulator_init() for the failing code.
> 
> Does anyone have any good ideas (small, self-contained patches) for
> solving this in v3.6 in such a way that PCIe works on both TrimSlice and
> Harmony?
> 
> Thanks.

I've looked into this a bit, and it seems like ARM is using an open-
coded version of the pci_enable_resources() function here, with the only
difference being the unconditional enabling of both I/O and memory-
mapped access for bridges. On Tegra there is already a PCI fixup to do
this, so pci_enable_resources() can be used as-is. I came up with the
attached patch but haven't been able to test it yet.

Thierry
-------------- next part --------------
From ebd69ae0a3d076e574da74d963cb3834b71dc6ad Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding at avionic-design.de>
Date: Mon, 13 Aug 2012 18:49:28 +0200
Subject: [PATCH] ARM: PCI: refactor pcibios_enable_device()

The implementation is an open-coded version on pci_enable_resources()
with a special case to enable I/O and memory-mapped functionality on
bridges. This commit reuses the existing PCI core implementation of the
pci_enable_resources() function. This also means that bridges no longer
enable I/O and memory-mapped functionality unconditionally. Platforms
where this is really required can add a corresponding fixup.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 arch/arm/kernel/bios32.c | 36 +-----------------------------------
 1 file changed, 1 insertion(+), 35 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 13fd97b..dfe25f7 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -601,41 +601,7 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  */
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
-	u16 cmd, old_cmd;
-	int idx;
-	struct resource *r;
-
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	old_cmd = cmd;
-	for (idx = 0; idx < 6; idx++) {
-		/* Only set up the requested stuff */
-		if (!(mask & (1 << idx)))
-			continue;
-
-		r = dev->resource + idx;
-		if (!r->start && r->end) {
-			printk(KERN_ERR "PCI: Device %s not available because"
-			       " of resource collisions\n", pci_name(dev));
-			return -EINVAL;
-		}
-		if (r->flags & IORESOURCE_IO)
-			cmd |= PCI_COMMAND_IO;
-		if (r->flags & IORESOURCE_MEM)
-			cmd |= PCI_COMMAND_MEMORY;
-	}
-
-	/*
-	 * Bridges (eg, cardbus bridges) need to be fully enabled
-	 */
-	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
-		cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-
-	if (cmd != old_cmd) {
-		printk("PCI: enabling device %s (%04x -> %04x)\n",
-		       pci_name(dev), old_cmd, cmd);
-		pci_write_config_word(dev, PCI_COMMAND, cmd);
-	}
-	return 0;
+	return pci_enable_resources(dev, mask);
 }
 
 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
-- 
1.7.11.4

-------------- next part --------------
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From will.deacon at arm.com  Mon Aug 13 13:38:48 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 13 Aug 2012 18:38:48 +0100
Subject: [PATCH] ARM: mutex: use generic atomic_dec-based implementation for
 ARMv6+
Message-ID: <1344879528-24897-1-git-send-email-will.deacon@arm.com>

Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based
implementation for ARMv6+") removed the barrier-less, ARM-specific
mutex implementation in favour of the generic xchg-based code.

Since then, a bug was uncovered in the xchg code when running on SMP
platforms, due to interactions between the locking paths and the
MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place
lock in contended state after fastpath_lock failure"), however, the
atomic_dec-based mutex algorithm is now marginally more efficient for
ARM (~0.5% improvement in hackbench scores on dual A15).

This patch moves ARMv6+ platforms to the atomic_dec-based mutex code.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/mutex.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index b1479fd..d69ebc7 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -9,8 +9,12 @@
 #define _ASM_MUTEX_H
 /*
  * On pre-ARMv6 hardware this results in a swp-based implementation,
- * which is the most efficient. For ARMv6+, we emit a pair of exclusive
- * accesses instead.
+ * which is the most efficient. For ARMv6+, we have exclusive memory
+ * accessors and use atomic_dec to avoid the extra xchg operations
+ * on the locking slowpaths.
  */
+#if __LINUX_ARM_ARCH < 6
 #include <asm-generic/mutex-xchg.h>
+#else
+#include <asm-generic/mutex-dec.h>
 #endif
-- 
1.7.4.1



From nico at fluxnic.net  Mon Aug 13 14:14:48 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 13 Aug 2012 14:14:48 -0400 (EDT)
Subject: [PATCH] ARM: mutex: use generic atomic_dec-based implementation
 for ARMv6+
In-Reply-To: <1344879528-24897-1-git-send-email-will.deacon@arm.com>
References: <1344879528-24897-1-git-send-email-will.deacon@arm.com>
Message-ID: <alpine.LFD.2.02.1208131412130.5231@xanadu.home>

On Mon, 13 Aug 2012, Will Deacon wrote:

> Commit a76d7bd96d65 ("ARM: 7467/1: mutex: use generic xchg-based
> implementation for ARMv6+") removed the barrier-less, ARM-specific
> mutex implementation in favour of the generic xchg-based code.
> 
> Since then, a bug was uncovered in the xchg code when running on SMP
> platforms, due to interactions between the locking paths and the
> MUTEX_SPIN_ON_OWNER code. This was fixed in 0bce9c46bf3b ("mutex: place
> lock in contended state after fastpath_lock failure"), however, the
> atomic_dec-based mutex algorithm is now marginally more efficient for
> ARM (~0.5% improvement in hackbench scores on dual A15).
> 
> This patch moves ARMv6+ platforms to the atomic_dec-based mutex code.
> 
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/mutex.h |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
> index b1479fd..d69ebc7 100644
> --- a/arch/arm/include/asm/mutex.h
> +++ b/arch/arm/include/asm/mutex.h
> @@ -9,8 +9,12 @@
>  #define _ASM_MUTEX_H
>  /*
>   * On pre-ARMv6 hardware this results in a swp-based implementation,
> - * which is the most efficient. For ARMv6+, we emit a pair of exclusive
> - * accesses instead.
> + * which is the most efficient. For ARMv6+, we have exclusive memory
> + * accessors and use atomic_dec to avoid the extra xchg operations
> + * on the locking slowpaths.
>   */
> +#if __LINUX_ARM_ARCH < 6
>  #include <asm-generic/mutex-xchg.h>
> +#else
> +#include <asm-generic/mutex-dec.h>
>  #endif
> -- 
> 1.7.4.1
> 



From swarren at wwwdotorg.org  Mon Aug 13 14:47:38 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 13 Aug 2012 12:47:38 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
Message-ID: <50294BCA.1070807@wwwdotorg.org>

On 08/13/2012 11:40 AM, Thierry Reding wrote:
> On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
>>> This patch series adds support for device tree based probing of
>>> the PCIe controller found on Tegra SoCs.
>> 
>> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
>> that PCIe doesn't work on TrimSlice when booting use device tree.
>> I think I found the cause, and I can't see why the same problem
>> doesn't affect this series. Perhaps you can enlighten me?
...
>> PCI: Device 0000:01:00.0 not available because of resource
>> collisions
...
> I've looked into this a bit, and it seems like ARM is using an
> open- coded version of the pci_enable_resources() function here,
> with the only difference being the unconditional enabling of both
> I/O and memory- mapped access for bridges. On Tegra there is
> already a PCI fixup to do this, so pci_enable_resources() can be
> used as-is. I came up with the attached patch but haven't been able
> to test it yet.

Thanks very much for looking into this.

The patch did alter the behavior a little for TrimSlice, but didn't
solve the problem. The old error messages:

> [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
> [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
> [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22

Were replaced with the following with your patch:

> [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
> [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
> [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22

This message appears from drivers/pci/setup-res.c pci_enable_resources()
due to:

> 		if (!r->parent) {
> 			dev_err(&dev->dev, "device not available "
> 				"(can't reserve %pR)\n", r);
> 			return -EINVAL;
> 		}

That check doesn't appear in ARM's custom pcibios_enable_device().
Disabling that check yields:

> [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
> [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16

I think that's because the pci_dev's resources are initially assigned
PCI-aperture-relative addresses, and then these are later patched up to
take account of where the aperture is mapped into the CPU's address space.

Boot log using board files:

> [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
...
> [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
... (I added some extra printks:)
> [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
> [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
> [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]

whereas for a device tree boot:

(same):
> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
... (request region happens early)
> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
... (same, just happens too late)
> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]

I suspect this is all still related to the PCI devices themselves being
probed much earlier in the overall PCI initialization sequence when the
PCI controller is probed later in the boot sequence, whereas PCI device
probe is deferred until the overall PCI initialization sequence is
complete if the PCI controller is probed very early in the boot sequence.

Does anyone know where/what that "probe now" vs. "probe later" decision
point is? I'll try and track it down if nobody beats me to it.


From s.hauer at pengutronix.de  Mon Aug 13 14:58:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 Aug 2012 20:58:17 +0200
Subject: [GIT PULL 0/3] arm-soc updates
In-Reply-To: <1344625575-27560-1-git-send-email-arnd@arndb.de>
References: <1344625575-27560-1-git-send-email-arnd@arndb.de>
Message-ID: <20120813185817.GA17342@pengutronix.de>

Hi Arnd,

On Fri, Aug 10, 2012 at 09:06:12PM +0200, Arnd Bergmann wrote:
> Hi Linus,
> 
> Here are three pull requests for you to consider for the next -rc.

How do you send multiple pull requests? Is there some git foo available
or do you do this manually?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Aug 13 14:58:25 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 Aug 2012 20:58:25 +0200
Subject: [PATCH 1/2] ARM: mx27pdk: Add audio support
In-Reply-To: <5028E2DF.6060409@gmail.com>
References: <1341341098-9510-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5BXQ2OQVC6nXeo_yJB=SBC=sv=ez9k6uo3gLNkWnC0Gyg@mail.gmail.com>
 <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
 <20120803135956.GT1451@pengutronix.de> <5028E2DF.6060409@gmail.com>
Message-ID: <20120813185825.GS1451@pengutronix.de>

On Mon, Aug 13, 2012 at 01:19:59PM +0200, Ga?tan Carlier wrote:
> Hi,
> On 08/03/2012 03:59 PM, Sascha Hauer wrote:
> >On Tue, Jul 31, 2012 at 09:49:13AM -0300, Fabio Estevam wrote:
> >>Sascha,
> >>
> >>On 7/25/12, Fabio Estevam <festevam at gmail.com> wrote:
> >>>Hi Sascha,
> >>>
> >>>On Tue, Jul 3, 2012 at 3:44 PM, Fabio Estevam
> >>><fabio.estevam at freescale.com> wrote:
> >>>>mx27pdk has a mc13783 audio codec.
> >>>>
> >>>>Add support for it.
> >>>>
> >>>>Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> >>>
> >>>Is this patch OK? Can it be applied?
> >>
> >>Could this get into 3.6?
> >
> >Applied now. Sorry, missed this one.
> >
> >Sascha
> >
> Is this patch will be applied on linux-next tree ?

This will be in linux-next once I send a pull request to Arnd. I do not
have a branch in linux-next.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From gcembed at gmail.com  Mon Aug 13 15:13:25 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Mon, 13 Aug 2012 21:13:25 +0200
Subject: [PATCH 1/2] ARM: mx27pdk: Add audio support
In-Reply-To: <20120813185825.GS1451@pengutronix.de>
References: <1341341098-9510-1-git-send-email-fabio.estevam@freescale.com>
 <CAOMZO5BXQ2OQVC6nXeo_yJB=SBC=sv=ez9k6uo3gLNkWnC0Gyg@mail.gmail.com>
 <CAOMZO5Am433CAWOWCLQ7QkEJRTF1qon+qM0RA2PPtC8uLPGUWA@mail.gmail.com>
 <20120803135956.GT1451@pengutronix.de> <5028E2DF.6060409@gmail.com>
 <20120813185825.GS1451@pengutronix.de>
Message-ID: <502951D5.1040403@gmail.com>

Hi,
On 08/13/2012 08:58 PM, Sascha Hauer wrote:
> On Mon, Aug 13, 2012 at 01:19:59PM +0200, Ga?tan Carlier wrote:
>> Hi,
>> On 08/03/2012 03:59 PM, Sascha Hauer wrote:
>>> On Tue, Jul 31, 2012 at 09:49:13AM -0300, Fabio Estevam wrote:
>>>> Sascha,
>>>>
>>>> On 7/25/12, Fabio Estevam <festevam at gmail.com> wrote:
>>>>> Hi Sascha,
>>>>>
>>>>> On Tue, Jul 3, 2012 at 3:44 PM, Fabio Estevam
>>>>> <fabio.estevam at freescale.com> wrote:
>>>>>> mx27pdk has a mc13783 audio codec.
>>>>>>
>>>>>> Add support for it.
>>>>>>
>>>>>> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
>>>>>
>>>>> Is this patch OK? Can it be applied?
>>>>
>>>> Could this get into 3.6?
>>>
>>> Applied now. Sorry, missed this one.
>>>
>>> Sascha
>>>
>> Is this patch will be applied on linux-next tree ?
>
> This will be in linux-next once I send a pull request to Arnd. I do not
> have a branch in linux-next.
>
> Sascha
>
Ok, thanks a lot.
Ga?tan Carlier


From troy.kisky at boundarydevices.com  Mon Aug 13 15:26:10 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Mon, 13 Aug 2012 12:26:10 -0700
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <502954D2.908@boundarydevices.com>

On 8/13/2012 7:47 AM, Shawn Guo wrote:
> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
> pinctrl drivers number pad from 1.  It causes problem/confusion when
> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>
> Change imx51_pads and imx53_pads numbering start from 0.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>   drivers/pinctrl/pinctrl-imx51.c |  490 +++++++++++++++++++-------------------
>   drivers/pinctrl/pinctrl-imx53.c |  402 ++++++++++++++++----------------
>   2 files changed, 446 insertions(+), 446 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
> index 9fd0216..fb84689 100644
> --- a/drivers/pinctrl/pinctrl-imx51.c
> +++ b/drivers/pinctrl/pinctrl-imx51.c
> @@ -23,251 +23,251 @@
>   #include "pinctrl-imx.h"
>   
>   enum imx51_pads {
> -	MX51_PAD_EIM_D16 = 1,
> -	MX51_PAD_EIM_D17 = 2,
> -	MX51_PAD_EIM_D18 = 3,
> -	MX51_PAD_EIM_D19 = 4,
> -	MX51_PAD_EIM_D20 = 5,
> -	MX51_PAD_EIM_D21 = 6,
> -	MX51_PAD_EIM_D22 = 7,
> -	MX51_PAD_EIM_D23 = 8,
> -	MX51_PAD_EIM_D24 = 9,
> -	MX51_PAD_EIM_D25 = 10,
> -	MX51_PAD_EIM_D26 = 11,
> -	MX51_PAD_EIM_D27 = 12,
> -	MX51_PAD_EIM_D28 = 13,
> -	MX51_PAD_EIM_D29 = 14,
> -	MX51_PAD_EIM_D30 = 15,
> -	MX51_PAD_EIM_D31 = 16,
> -	MX51_PAD_EIM_A16 = 17,
> -	MX51_PAD_EIM_A17 = 18,
> -	MX51_PAD_EIM_A18 = 19,
> -	MX51_PAD_EIM_A19 = 20,
> -	MX51_PAD_EIM_A20 = 21,
> -	MX51_PAD_EIM_A21 = 22,
> -	MX51_PAD_EIM_A22 = 23,
> -	MX51_PAD_EIM_A23 = 24,
> -	MX51_PAD_EIM_A24 = 25,
> -	MX51_PAD_EIM_A25 = 26,
> -	MX51_PAD_EIM_A26 = 27,
> -	MX51_PAD_EIM_A27 = 28,
> -	MX51_PAD_EIM_EB0 = 29,
> -	MX51_PAD_EIM_EB1 = 30,
> -	MX51_PAD_EIM_EB2 = 31,
> -	MX51_PAD_EIM_EB3 = 32,
> -	MX51_PAD_EIM_OE = 33,
> -	MX51_PAD_EIM_CS0 = 34,
> -	MX51_PAD_EIM_CS1 = 35,
> -	MX51_PAD_EIM_CS2 = 36,
> -	MX51_PAD_EIM_CS3 = 37,
> -	MX51_PAD_EIM_CS4 = 38,
> -	MX51_PAD_EIM_CS5 = 39,
> -	MX51_PAD_EIM_DTACK = 40,
> -	MX51_PAD_EIM_LBA = 41,
> -	MX51_PAD_EIM_CRE = 42,
> -	MX51_PAD_DRAM_CS1 = 43,
> -	MX51_PAD_NANDF_WE_B = 44,
> -	MX51_PAD_NANDF_RE_B = 45,
> -	MX51_PAD_NANDF_ALE = 46,
> -	MX51_PAD_NANDF_CLE = 47,
> -	MX51_PAD_NANDF_WP_B = 48,
> -	MX51_PAD_NANDF_RB0 = 49,
> -	MX51_PAD_NANDF_RB1 = 50,
> -	MX51_PAD_NANDF_RB2 = 51,
> -	MX51_PAD_NANDF_RB3 = 52,
> -	MX51_PAD_GPIO_NAND = 53,
> -	MX51_PAD_NANDF_CS0 = 54,
> -	MX51_PAD_NANDF_CS1 = 55,
> -	MX51_PAD_NANDF_CS2 = 56,
> -	MX51_PAD_NANDF_CS3 = 57,
> -	MX51_PAD_NANDF_CS4 = 58,
> -	MX51_PAD_NANDF_CS5 = 59,
> -	MX51_PAD_NANDF_CS6 = 60,
> -	MX51_PAD_NANDF_CS7 = 61,
> -	MX51_PAD_NANDF_RDY_INT = 62,
> -	MX51_PAD_NANDF_D15 = 63,
> -	MX51_PAD_NANDF_D14 = 64,
> -	MX51_PAD_NANDF_D13 = 65,
> -	MX51_PAD_NANDF_D12 = 66,
> -	MX51_PAD_NANDF_D11 = 67,
> -	MX51_PAD_NANDF_D10 = 68,
> -	MX51_PAD_NANDF_D9 = 69,
> -	MX51_PAD_NANDF_D8 = 70,
> -	MX51_PAD_NANDF_D7 = 71,
> -	MX51_PAD_NANDF_D6 = 72,
> -	MX51_PAD_NANDF_D5 = 73,
> -	MX51_PAD_NANDF_D4 = 74,
> -	MX51_PAD_NANDF_D3 = 75,
> -	MX51_PAD_NANDF_D2 = 76,
> -	MX51_PAD_NANDF_D1 = 77,
> -	MX51_PAD_NANDF_D0 = 78,
> -	MX51_PAD_CSI1_D8 = 79,
> -	MX51_PAD_CSI1_D9 = 80,
> -	MX51_PAD_CSI1_D10 = 81,
> -	MX51_PAD_CSI1_D11 = 82,
> -	MX51_PAD_CSI1_D12 = 83,
> -	MX51_PAD_CSI1_D13 = 84,
> -	MX51_PAD_CSI1_D14 = 85,
> -	MX51_PAD_CSI1_D15 = 86,
> -	MX51_PAD_CSI1_D16 = 87,
> -	MX51_PAD_CSI1_D17 = 88,
> -	MX51_PAD_CSI1_D18 = 89,
> -	MX51_PAD_CSI1_D19 = 90,
> -	MX51_PAD_CSI1_VSYNC = 91,
> -	MX51_PAD_CSI1_HSYNC = 92,
> -	MX51_PAD_CSI1_PIXCLK = 93,
> -	MX51_PAD_CSI1_MCLK = 94,
> -	MX51_PAD_CSI2_D12 = 95,
> -	MX51_PAD_CSI2_D13 = 96,
> -	MX51_PAD_CSI2_D14 = 97,
> -	MX51_PAD_CSI2_D15 = 98,
> -	MX51_PAD_CSI2_D16 = 99,
> -	MX51_PAD_CSI2_D17 = 100,
> -	MX51_PAD_CSI2_D18 = 101,
> -	MX51_PAD_CSI2_D19 = 102,
> -	MX51_PAD_CSI2_VSYNC = 103,
> -	MX51_PAD_CSI2_HSYNC = 104,
> -	MX51_PAD_CSI2_PIXCLK = 105,
> -	MX51_PAD_I2C1_CLK = 106,
> -	MX51_PAD_I2C1_DAT = 107,
> -	MX51_PAD_AUD3_BB_TXD = 108,
> -	MX51_PAD_AUD3_BB_RXD = 109,
> -	MX51_PAD_AUD3_BB_CK = 110,
> -	MX51_PAD_AUD3_BB_FS = 111,
> -	MX51_PAD_CSPI1_MOSI = 112,
> -	MX51_PAD_CSPI1_MISO = 113,
> -	MX51_PAD_CSPI1_SS0 = 114,
> -	MX51_PAD_CSPI1_SS1 = 115,
> -	MX51_PAD_CSPI1_RDY = 116,
> -	MX51_PAD_CSPI1_SCLK = 117,
> -	MX51_PAD_UART1_RXD = 118,
> -	MX51_PAD_UART1_TXD = 119,
> -	MX51_PAD_UART1_RTS = 120,
> -	MX51_PAD_UART1_CTS = 121,
> -	MX51_PAD_UART2_RXD = 122,
> -	MX51_PAD_UART2_TXD = 123,
> -	MX51_PAD_UART3_RXD = 124,
> -	MX51_PAD_UART3_TXD = 125,
> -	MX51_PAD_OWIRE_LINE = 126,
> -	MX51_PAD_KEY_ROW0 = 127,
> -	MX51_PAD_KEY_ROW1 = 128,
> -	MX51_PAD_KEY_ROW2 = 129,
> -	MX51_PAD_KEY_ROW3 = 130,
> -	MX51_PAD_KEY_COL0 = 131,
> -	MX51_PAD_KEY_COL1 = 132,
> -	MX51_PAD_KEY_COL2 = 133,
> -	MX51_PAD_KEY_COL3 = 134,
> -	MX51_PAD_KEY_COL4 = 135,
> -	MX51_PAD_KEY_COL5 = 136,
> -	MX51_PAD_USBH1_CLK = 137,
> -	MX51_PAD_USBH1_DIR = 138,
> -	MX51_PAD_USBH1_STP = 139,
> -	MX51_PAD_USBH1_NXT = 140,
> -	MX51_PAD_USBH1_DATA0 = 141,
> -	MX51_PAD_USBH1_DATA1 = 142,
> -	MX51_PAD_USBH1_DATA2 = 143,
> -	MX51_PAD_USBH1_DATA3 = 144,
> -	MX51_PAD_USBH1_DATA4 = 145,
> -	MX51_PAD_USBH1_DATA5 = 146,
> -	MX51_PAD_USBH1_DATA6 = 147,
> -	MX51_PAD_USBH1_DATA7 = 148,
> -	MX51_PAD_DI1_PIN11 = 149,
> -	MX51_PAD_DI1_PIN12 = 150,
> -	MX51_PAD_DI1_PIN13 = 151,
> -	MX51_PAD_DI1_D0_CS = 152,
> -	MX51_PAD_DI1_D1_CS = 153,
> -	MX51_PAD_DISPB2_SER_DIN = 154,
> -	MX51_PAD_DISPB2_SER_DIO = 155,
> -	MX51_PAD_DISPB2_SER_CLK = 156,
> -	MX51_PAD_DISPB2_SER_RS = 157,
> -	MX51_PAD_DISP1_DAT0 = 158,
> -	MX51_PAD_DISP1_DAT1 = 159,
> -	MX51_PAD_DISP1_DAT2 = 160,
> -	MX51_PAD_DISP1_DAT3 = 161,
> -	MX51_PAD_DISP1_DAT4 = 162,
> -	MX51_PAD_DISP1_DAT5 = 163,
> -	MX51_PAD_DISP1_DAT6 = 164,
> -	MX51_PAD_DISP1_DAT7 = 165,
> -	MX51_PAD_DISP1_DAT8 = 166,
> -	MX51_PAD_DISP1_DAT9 = 167,
> -	MX51_PAD_DISP1_DAT10 = 168,
> -	MX51_PAD_DISP1_DAT11 = 169,
> -	MX51_PAD_DISP1_DAT12 = 170,
> -	MX51_PAD_DISP1_DAT13 = 171,
> -	MX51_PAD_DISP1_DAT14 = 172,
> -	MX51_PAD_DISP1_DAT15 = 173,
> -	MX51_PAD_DISP1_DAT16 = 174,
> -	MX51_PAD_DISP1_DAT17 = 175,
> -	MX51_PAD_DISP1_DAT18 = 176,
> -	MX51_PAD_DISP1_DAT19 = 177,
> -	MX51_PAD_DISP1_DAT20 = 178,
> -	MX51_PAD_DISP1_DAT21 = 179,
> -	MX51_PAD_DISP1_DAT22 = 180,
> -	MX51_PAD_DISP1_DAT23 = 181,
> -	MX51_PAD_DI1_PIN3 = 182,
> -	MX51_PAD_DI1_PIN2 = 183,
> -	MX51_PAD_DI_GP2 = 184,
> -	MX51_PAD_DI_GP3 = 185,
> -	MX51_PAD_DI2_PIN4 = 186,
> -	MX51_PAD_DI2_PIN2 = 187,
> -	MX51_PAD_DI2_PIN3 = 188,
> -	MX51_PAD_DI2_DISP_CLK = 189,
> -	MX51_PAD_DI_GP4 = 190,
> -	MX51_PAD_DISP2_DAT0 = 191,
> -	MX51_PAD_DISP2_DAT1 = 192,
> -	MX51_PAD_DISP2_DAT2 = 193,
> -	MX51_PAD_DISP2_DAT3 = 194,
> -	MX51_PAD_DISP2_DAT4 = 195,
> -	MX51_PAD_DISP2_DAT5 = 196,
> -	MX51_PAD_DISP2_DAT6 = 197,
> -	MX51_PAD_DISP2_DAT7 = 198,
> -	MX51_PAD_DISP2_DAT8 = 199,
> -	MX51_PAD_DISP2_DAT9 = 200,
> -	MX51_PAD_DISP2_DAT10 = 201,
> -	MX51_PAD_DISP2_DAT11 = 202,
> -	MX51_PAD_DISP2_DAT12 = 203,
> -	MX51_PAD_DISP2_DAT13 = 204,
> -	MX51_PAD_DISP2_DAT14 = 205,
> -	MX51_PAD_DISP2_DAT15 = 206,
> -	MX51_PAD_SD1_CMD = 207,
> -	MX51_PAD_SD1_CLK = 208,
> -	MX51_PAD_SD1_DATA0 = 209,
> -	MX51_PAD_EIM_DA0 = 210,
> -	MX51_PAD_EIM_DA1 = 211,
> -	MX51_PAD_EIM_DA2 = 212,
> -	MX51_PAD_EIM_DA3 = 213,
> -	MX51_PAD_SD1_DATA1 = 214,
> -	MX51_PAD_EIM_DA4 = 215,
> -	MX51_PAD_EIM_DA5 = 216,
> -	MX51_PAD_EIM_DA6 = 217,
> -	MX51_PAD_EIM_DA7 = 218,
> -	MX51_PAD_SD1_DATA2 = 219,
> -	MX51_PAD_EIM_DA10 = 220,
> -	MX51_PAD_EIM_DA11 = 221,
> -	MX51_PAD_EIM_DA8 = 222,
> -	MX51_PAD_EIM_DA9 = 223,
> -	MX51_PAD_SD1_DATA3 = 224,
> -	MX51_PAD_GPIO1_0 = 225,
> -	MX51_PAD_GPIO1_1 = 226,
> -	MX51_PAD_EIM_DA12 = 227,
> -	MX51_PAD_EIM_DA13 = 228,
> -	MX51_PAD_EIM_DA14 = 229,
> -	MX51_PAD_EIM_DA15 = 230,
> -	MX51_PAD_SD2_CMD = 231,
> -	MX51_PAD_SD2_CLK = 232,
> -	MX51_PAD_SD2_DATA0 = 233,
> -	MX51_PAD_SD2_DATA1 = 234,
> -	MX51_PAD_SD2_DATA2 = 235,
> -	MX51_PAD_SD2_DATA3 = 236,
> -	MX51_PAD_GPIO1_2 = 237,
> -	MX51_PAD_GPIO1_3 = 238,
> -	MX51_PAD_PMIC_INT_REQ = 239,
> -	MX51_PAD_GPIO1_4 = 240,
> -	MX51_PAD_GPIO1_5 = 241,
> -	MX51_PAD_GPIO1_6 = 242,
> -	MX51_PAD_GPIO1_7 = 243,
> -	MX51_PAD_GPIO1_8 = 244,
> -	MX51_PAD_GPIO1_9 = 245,
> +	MX51_PAD_EIM_D16 = 0,
> +	MX51_PAD_EIM_D17 = 1,
> +	MX51_PAD_EIM_D18 = 2,
> +	MX51_PAD_EIM_D19 = 3,
> +	MX51_PAD_EIM_D20 = 4,
> +	MX51_PAD_EIM_D21 = 5,
> +	MX51_PAD_EIM_D22 = 6,
> +	MX51_PAD_EIM_D23 = 7,
> +	MX51_PAD_EIM_D24 = 8,
> +	MX51_PAD_EIM_D25 = 9,
> +	MX51_PAD_EIM_D26 = 10,
> +	MX51_PAD_EIM_D27 = 11,
> +	MX51_PAD_EIM_D28 = 12,
> +	MX51_PAD_EIM_D29 = 13,
> +	MX51_PAD_EIM_D30 = 14,
> +	MX51_PAD_EIM_D31 = 15,
> +	MX51_PAD_EIM_A16 = 16,
> +	MX51_PAD_EIM_A17 = 17,
> +	MX51_PAD_EIM_A18 = 18,
> +	MX51_PAD_EIM_A19 = 19,
> +	MX51_PAD_EIM_A20 = 20,
> +	MX51_PAD_EIM_A21 = 21,
> +	MX51_PAD_EIM_A22 = 22,
> +	MX51_PAD_EIM_A23 = 23,
> +	MX51_PAD_EIM_A24 = 24,
> +	MX51_PAD_EIM_A25 = 25,
> +	MX51_PAD_EIM_A26 = 26,
> +	MX51_PAD_EIM_A27 = 27,
> +	MX51_PAD_EIM_EB0 = 28,
> +	MX51_PAD_EIM_EB1 = 29,
> +	MX51_PAD_EIM_EB2 = 30,
> +	MX51_PAD_EIM_EB3 = 31,
> +	MX51_PAD_EIM_OE = 32,
> +	MX51_PAD_EIM_CS0 = 33,
> +	MX51_PAD_EIM_CS1 = 34,
> +	MX51_PAD_EIM_CS2 = 35,
> +	MX51_PAD_EIM_CS3 = 36,
> +	MX51_PAD_EIM_CS4 = 37,
> +	MX51_PAD_EIM_CS5 = 38,
> +	MX51_PAD_EIM_DTACK = 39,
> +	MX51_PAD_EIM_LBA = 40,
> +	MX51_PAD_EIM_CRE = 41,
> +	MX51_PAD_DRAM_CS1 = 42,
> +	MX51_PAD_NANDF_WE_B = 43,
> +	MX51_PAD_NANDF_RE_B = 44,
> +	MX51_PAD_NANDF_ALE = 45,
> +	MX51_PAD_NANDF_CLE = 46,
> +	MX51_PAD_NANDF_WP_B = 47,
> +	MX51_PAD_NANDF_RB0 = 48,
> +	MX51_PAD_NANDF_RB1 = 49,
> +	MX51_PAD_NANDF_RB2 = 50,
> +	MX51_PAD_NANDF_RB3 = 51,
> +	MX51_PAD_GPIO_NAND = 52,
> +	MX51_PAD_NANDF_CS0 = 53,
> +	MX51_PAD_NANDF_CS1 = 54,
> +	MX51_PAD_NANDF_CS2 = 55,
> +	MX51_PAD_NANDF_CS3 = 56,
> +	MX51_PAD_NANDF_CS4 = 57,
> +	MX51_PAD_NANDF_CS5 = 58,
> +	MX51_PAD_NANDF_CS6 = 59,
> +	MX51_PAD_NANDF_CS7 = 60,
> +	MX51_PAD_NANDF_RDY_INT = 61,
> +	MX51_PAD_NANDF_D15 = 62,
> +	MX51_PAD_NANDF_D14 = 63,
> +	MX51_PAD_NANDF_D13 = 64,
> +	MX51_PAD_NANDF_D12 = 65,
> +	MX51_PAD_NANDF_D11 = 66,
> +	MX51_PAD_NANDF_D10 = 67,
> +	MX51_PAD_NANDF_D9 = 68,
> +	MX51_PAD_NANDF_D8 = 69,
> +	MX51_PAD_NANDF_D7 = 70,
> +	MX51_PAD_NANDF_D6 = 71,
> +	MX51_PAD_NANDF_D5 = 72,
> +	MX51_PAD_NANDF_D4 = 73,
> +	MX51_PAD_NANDF_D3 = 74,
> +	MX51_PAD_NANDF_D2 = 75,
> +	MX51_PAD_NANDF_D1 = 76,
> +	MX51_PAD_NANDF_D0 = 77,
> +	MX51_PAD_CSI1_D8 = 78,
> +	MX51_PAD_CSI1_D9 = 79,
> +	MX51_PAD_CSI1_D10 = 80,
> +	MX51_PAD_CSI1_D11 = 81,
> +	MX51_PAD_CSI1_D12 = 82,
> +	MX51_PAD_CSI1_D13 = 83,
> +	MX51_PAD_CSI1_D14 = 84,
> +	MX51_PAD_CSI1_D15 = 85,
> +	MX51_PAD_CSI1_D16 = 86,
> +	MX51_PAD_CSI1_D17 = 87,
> +	MX51_PAD_CSI1_D18 = 88,
> +	MX51_PAD_CSI1_D19 = 89,
> +	MX51_PAD_CSI1_VSYNC = 90,
> +	MX51_PAD_CSI1_HSYNC = 91,
> +	MX51_PAD_CSI1_PIXCLK = 92,
> +	MX51_PAD_CSI1_MCLK = 93,
> +	MX51_PAD_CSI2_D12 = 94,
> +	MX51_PAD_CSI2_D13 = 95,
> +	MX51_PAD_CSI2_D14 = 96,
> +	MX51_PAD_CSI2_D15 = 97,
> +	MX51_PAD_CSI2_D16 = 98,
> +	MX51_PAD_CSI2_D17 = 99,
> +	MX51_PAD_CSI2_D18 = 100,
> +	MX51_PAD_CSI2_D19 = 101,
> +	MX51_PAD_CSI2_VSYNC = 102,
> +	MX51_PAD_CSI2_HSYNC = 103,
> +	MX51_PAD_CSI2_PIXCLK = 104,
> +	MX51_PAD_I2C1_CLK = 105,
> +	MX51_PAD_I2C1_DAT = 106,
> +	MX51_PAD_AUD3_BB_TXD = 107,
> +	MX51_PAD_AUD3_BB_RXD = 108,
> +	MX51_PAD_AUD3_BB_CK = 109,
> +	MX51_PAD_AUD3_BB_FS = 110,
> +	MX51_PAD_CSPI1_MOSI = 111,
> +	MX51_PAD_CSPI1_MISO = 112,
> +	MX51_PAD_CSPI1_SS0 = 113,
> +	MX51_PAD_CSPI1_SS1 = 114,
> +	MX51_PAD_CSPI1_RDY = 115,
> +	MX51_PAD_CSPI1_SCLK = 116,
> +	MX51_PAD_UART1_RXD = 117,
> +	MX51_PAD_UART1_TXD = 118,
> +	MX51_PAD_UART1_RTS = 119,
> +	MX51_PAD_UART1_CTS = 120,
> +	MX51_PAD_UART2_RXD = 121,
> +	MX51_PAD_UART2_TXD = 122,
> +	MX51_PAD_UART3_RXD = 123,
> +	MX51_PAD_UART3_TXD = 124,
> +	MX51_PAD_OWIRE_LINE = 125,
> +	MX51_PAD_KEY_ROW0 = 126,
> +	MX51_PAD_KEY_ROW1 = 127,
> +	MX51_PAD_KEY_ROW2 = 128,
> +	MX51_PAD_KEY_ROW3 = 129,
> +	MX51_PAD_KEY_COL0 = 130,
> +	MX51_PAD_KEY_COL1 = 131,
> +	MX51_PAD_KEY_COL2 = 132,
> +	MX51_PAD_KEY_COL3 = 133,
> +	MX51_PAD_KEY_COL4 = 134,
> +	MX51_PAD_KEY_COL5 = 135,
> +	MX51_PAD_USBH1_CLK = 136,
> +	MX51_PAD_USBH1_DIR = 137,
> +	MX51_PAD_USBH1_STP = 138,
> +	MX51_PAD_USBH1_NXT = 139,
> +	MX51_PAD_USBH1_DATA0 = 140,
> +	MX51_PAD_USBH1_DATA1 = 141,
> +	MX51_PAD_USBH1_DATA2 = 142,
> +	MX51_PAD_USBH1_DATA3 = 143,
> +	MX51_PAD_USBH1_DATA4 = 144,
> +	MX51_PAD_USBH1_DATA5 = 145,
> +	MX51_PAD_USBH1_DATA6 = 146,
> +	MX51_PAD_USBH1_DATA7 = 147,
> +	MX51_PAD_DI1_PIN11 = 148,
> +	MX51_PAD_DI1_PIN12 = 149,
> +	MX51_PAD_DI1_PIN13 = 150,
> +	MX51_PAD_DI1_D0_CS = 151,
> +	MX51_PAD_DI1_D1_CS = 152,
> +	MX51_PAD_DISPB2_SER_DIN = 153,
> +	MX51_PAD_DISPB2_SER_DIO = 154,
> +	MX51_PAD_DISPB2_SER_CLK = 155,
> +	MX51_PAD_DISPB2_SER_RS = 156,
> +	MX51_PAD_DISP1_DAT0 = 157,
> +	MX51_PAD_DISP1_DAT1 = 158,
> +	MX51_PAD_DISP1_DAT2 = 159,
> +	MX51_PAD_DISP1_DAT3 = 160,
> +	MX51_PAD_DISP1_DAT4 = 161,
> +	MX51_PAD_DISP1_DAT5 = 162,
> +	MX51_PAD_DISP1_DAT6 = 163,
> +	MX51_PAD_DISP1_DAT7 = 164,
> +	MX51_PAD_DISP1_DAT8 = 165,
> +	MX51_PAD_DISP1_DAT9 = 166,
> +	MX51_PAD_DISP1_DAT10 = 167,
> +	MX51_PAD_DISP1_DAT11 = 168,
> +	MX51_PAD_DISP1_DAT12 = 169,
> +	MX51_PAD_DISP1_DAT13 = 170,
> +	MX51_PAD_DISP1_DAT14 = 171,
> +	MX51_PAD_DISP1_DAT15 = 172,
> +	MX51_PAD_DISP1_DAT16 = 173,
> +	MX51_PAD_DISP1_DAT17 = 174,
> +	MX51_PAD_DISP1_DAT18 = 175,
> +	MX51_PAD_DISP1_DAT19 = 176,
> +	MX51_PAD_DISP1_DAT20 = 177,
> +	MX51_PAD_DISP1_DAT21 = 178,
> +	MX51_PAD_DISP1_DAT22 = 179,
> +	MX51_PAD_DISP1_DAT23 = 180,
> +	MX51_PAD_DI1_PIN3 = 181,
> +	MX51_PAD_DI1_PIN2 = 182,
> +	MX51_PAD_DI_GP2 = 183,
> +	MX51_PAD_DI_GP3 = 184,
> +	MX51_PAD_DI2_PIN4 = 185,
> +	MX51_PAD_DI2_PIN2 = 186,
> +	MX51_PAD_DI2_PIN3 = 187,
> +	MX51_PAD_DI2_DISP_CLK = 188,
> +	MX51_PAD_DI_GP4 = 189,
> +	MX51_PAD_DISP2_DAT0 = 190,
> +	MX51_PAD_DISP2_DAT1 = 191,
> +	MX51_PAD_DISP2_DAT2 = 192,
> +	MX51_PAD_DISP2_DAT3 = 193,
> +	MX51_PAD_DISP2_DAT4 = 194,
> +	MX51_PAD_DISP2_DAT5 = 195,
> +	MX51_PAD_DISP2_DAT6 = 196,
> +	MX51_PAD_DISP2_DAT7 = 197,
> +	MX51_PAD_DISP2_DAT8 = 198,
> +	MX51_PAD_DISP2_DAT9 = 199,
> +	MX51_PAD_DISP2_DAT10 = 200,
> +	MX51_PAD_DISP2_DAT11 = 201,
> +	MX51_PAD_DISP2_DAT12 = 202,
> +	MX51_PAD_DISP2_DAT13 = 203,
> +	MX51_PAD_DISP2_DAT14 = 204,
> +	MX51_PAD_DISP2_DAT15 = 205,
> +	MX51_PAD_SD1_CMD = 206,
> +	MX51_PAD_SD1_CLK = 207,
> +	MX51_PAD_SD1_DATA0 = 208,
> +	MX51_PAD_EIM_DA0 = 209,
> +	MX51_PAD_EIM_DA1 = 210,
> +	MX51_PAD_EIM_DA2 = 211,
> +	MX51_PAD_EIM_DA3 = 212,
> +	MX51_PAD_SD1_DATA1 = 213,
> +	MX51_PAD_EIM_DA4 = 214,
> +	MX51_PAD_EIM_DA5 = 215,
> +	MX51_PAD_EIM_DA6 = 216,
> +	MX51_PAD_EIM_DA7 = 217,
> +	MX51_PAD_SD1_DATA2 = 218,
> +	MX51_PAD_EIM_DA10 = 219,
> +	MX51_PAD_EIM_DA11 = 220,
> +	MX51_PAD_EIM_DA8 = 221,
> +	MX51_PAD_EIM_DA9 = 222,
> +	MX51_PAD_SD1_DATA3 = 223,
> +	MX51_PAD_GPIO1_0 = 224,
> +	MX51_PAD_GPIO1_1 = 225,
> +	MX51_PAD_EIM_DA12 = 226,
> +	MX51_PAD_EIM_DA13 = 227,
> +	MX51_PAD_EIM_DA14 = 228,
> +	MX51_PAD_EIM_DA15 = 229,
> +	MX51_PAD_SD2_CMD = 230,
> +	MX51_PAD_SD2_CLK = 231,
> +	MX51_PAD_SD2_DATA0 = 232,
> +	MX51_PAD_SD2_DATA1 = 233,
> +	MX51_PAD_SD2_DATA2 = 234,
> +	MX51_PAD_SD2_DATA3 = 235,
> +	MX51_PAD_GPIO1_2 = 236,
> +	MX51_PAD_GPIO1_3 = 237,
> +	MX51_PAD_PMIC_INT_REQ = 238,
> +	MX51_PAD_GPIO1_4 = 239,
> +	MX51_PAD_GPIO1_5 = 240,
> +	MX51_PAD_GPIO1_6 = 241,
> +	MX51_PAD_GPIO1_7 = 242,
> +	MX51_PAD_GPIO1_8 = 243,
> +	MX51_PAD_GPIO1_9 = 244,
>   };
>   
>   /* imx51 register maps */
> diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
> index 1f49e16..783feb1 100644
> --- a/drivers/pinctrl/pinctrl-imx53.c
> +++ b/drivers/pinctrl/pinctrl-imx53.c
> @@ -23,207 +23,207 @@
>   #include "pinctrl-imx.h"
>   
>   enum imx53_pads {
> -	MX53_PAD_GPIO_19 = 1,
> -	MX53_PAD_KEY_COL0 = 2,
> -	MX53_PAD_KEY_ROW0 = 3,
> -	MX53_PAD_KEY_COL1 = 4,
> -	MX53_PAD_KEY_ROW1 = 5,
> -	MX53_PAD_KEY_COL2 = 6,
> -	MX53_PAD_KEY_ROW2 = 7,
> -	MX53_PAD_KEY_COL3 = 8,
> -	MX53_PAD_KEY_ROW3 = 9,
> -	MX53_PAD_KEY_COL4 = 10,
> -	MX53_PAD_KEY_ROW4 = 11,
> -	MX53_PAD_DI0_DISP_CLK = 12,
> -	MX53_PAD_DI0_PIN15 = 13,
> -	MX53_PAD_DI0_PIN2 = 14,
> -	MX53_PAD_DI0_PIN3 = 15,
> -	MX53_PAD_DI0_PIN4 = 16,
> -	MX53_PAD_DISP0_DAT0 = 17,
> -	MX53_PAD_DISP0_DAT1 = 18,
> -	MX53_PAD_DISP0_DAT2 = 19,
> -	MX53_PAD_DISP0_DAT3 = 20,
> -	MX53_PAD_DISP0_DAT4 = 21,
> -	MX53_PAD_DISP0_DAT5 = 22,
> -	MX53_PAD_DISP0_DAT6 = 23,
> -	MX53_PAD_DISP0_DAT7 = 24,
> -	MX53_PAD_DISP0_DAT8 = 25,
> -	MX53_PAD_DISP0_DAT9 = 26,
> -	MX53_PAD_DISP0_DAT10 = 27,
> -	MX53_PAD_DISP0_DAT11 = 28,
> -	MX53_PAD_DISP0_DAT12 = 29,
> -	MX53_PAD_DISP0_DAT13 = 30,
> -	MX53_PAD_DISP0_DAT14 = 31,
> -	MX53_PAD_DISP0_DAT15 = 32,
> -	MX53_PAD_DISP0_DAT16 = 33,
> -	MX53_PAD_DISP0_DAT17 = 34,
> -	MX53_PAD_DISP0_DAT18 = 35,
> -	MX53_PAD_DISP0_DAT19 = 36,
> -	MX53_PAD_DISP0_DAT20 = 37,
> -	MX53_PAD_DISP0_DAT21 = 38,
> -	MX53_PAD_DISP0_DAT22 = 39,
> -	MX53_PAD_DISP0_DAT23 = 40,
> -	MX53_PAD_CSI0_PIXCLK = 41,
> -	MX53_PAD_CSI0_MCLK = 42,
> -	MX53_PAD_CSI0_DATA_EN = 43,
> -	MX53_PAD_CSI0_VSYNC = 44,
> -	MX53_PAD_CSI0_DAT4 = 45,
> -	MX53_PAD_CSI0_DAT5 = 46,
> -	MX53_PAD_CSI0_DAT6 = 47,
> -	MX53_PAD_CSI0_DAT7 = 48,
> -	MX53_PAD_CSI0_DAT8 = 49,
> -	MX53_PAD_CSI0_DAT9 = 50,
> -	MX53_PAD_CSI0_DAT10 = 51,
> -	MX53_PAD_CSI0_DAT11 = 52,
> -	MX53_PAD_CSI0_DAT12 = 53,
> -	MX53_PAD_CSI0_DAT13 = 54,
> -	MX53_PAD_CSI0_DAT14 = 55,
> -	MX53_PAD_CSI0_DAT15 = 56,
> -	MX53_PAD_CSI0_DAT16 = 57,
> -	MX53_PAD_CSI0_DAT17 = 58,
> -	MX53_PAD_CSI0_DAT18 = 59,
> -	MX53_PAD_CSI0_DAT19 = 60,
> -	MX53_PAD_EIM_A25 = 61,
> -	MX53_PAD_EIM_EB2 = 62,
> -	MX53_PAD_EIM_D16 = 63,
> -	MX53_PAD_EIM_D17 = 64,
> -	MX53_PAD_EIM_D18 = 65,
> -	MX53_PAD_EIM_D19 = 66,
> -	MX53_PAD_EIM_D20 = 67,
> -	MX53_PAD_EIM_D21 = 68,
> -	MX53_PAD_EIM_D22 = 69,
> -	MX53_PAD_EIM_D23 = 70,
> -	MX53_PAD_EIM_EB3 = 71,
> -	MX53_PAD_EIM_D24 = 72,
> -	MX53_PAD_EIM_D25 = 73,
> -	MX53_PAD_EIM_D26 = 74,
> -	MX53_PAD_EIM_D27 = 75,
> -	MX53_PAD_EIM_D28 = 76,
> -	MX53_PAD_EIM_D29 = 77,
> -	MX53_PAD_EIM_D30 = 78,
> -	MX53_PAD_EIM_D31 = 79,
> -	MX53_PAD_EIM_A24 = 80,
> -	MX53_PAD_EIM_A23 = 81,
> -	MX53_PAD_EIM_A22 = 82,
> -	MX53_PAD_EIM_A21 = 83,
> -	MX53_PAD_EIM_A20 = 84,
> -	MX53_PAD_EIM_A19 = 85,
> -	MX53_PAD_EIM_A18 = 86,
> -	MX53_PAD_EIM_A17 = 87,
> -	MX53_PAD_EIM_A16 = 88,
> -	MX53_PAD_EIM_CS0 = 89,
> -	MX53_PAD_EIM_CS1 = 90,
> -	MX53_PAD_EIM_OE = 91,
> -	MX53_PAD_EIM_RW = 92,
> -	MX53_PAD_EIM_LBA = 93,
> -	MX53_PAD_EIM_EB0 = 94,
> -	MX53_PAD_EIM_EB1 = 95,
> -	MX53_PAD_EIM_DA0 = 96,
> -	MX53_PAD_EIM_DA1 = 97,
> -	MX53_PAD_EIM_DA2 = 98,
> -	MX53_PAD_EIM_DA3 = 99,
> -	MX53_PAD_EIM_DA4 = 100,
> -	MX53_PAD_EIM_DA5 = 101,
> -	MX53_PAD_EIM_DA6 = 102,
> -	MX53_PAD_EIM_DA7 = 103,
> -	MX53_PAD_EIM_DA8 = 104,
> -	MX53_PAD_EIM_DA9 = 105,
> -	MX53_PAD_EIM_DA10 = 106,
> -	MX53_PAD_EIM_DA11 = 107,
> -	MX53_PAD_EIM_DA12 = 108,
> -	MX53_PAD_EIM_DA13 = 109,
> -	MX53_PAD_EIM_DA14 = 110,
> -	MX53_PAD_EIM_DA15 = 111,
> -	MX53_PAD_NANDF_WE_B = 112,
> -	MX53_PAD_NANDF_RE_B = 113,
> -	MX53_PAD_EIM_WAIT = 114,
> -	MX53_PAD_LVDS1_TX3_P = 115,
> -	MX53_PAD_LVDS1_TX2_P = 116,
> -	MX53_PAD_LVDS1_CLK_P = 117,
> -	MX53_PAD_LVDS1_TX1_P = 118,
> -	MX53_PAD_LVDS1_TX0_P = 119,
> -	MX53_PAD_LVDS0_TX3_P = 120,
> -	MX53_PAD_LVDS0_CLK_P = 121,
> -	MX53_PAD_LVDS0_TX2_P = 122,
> -	MX53_PAD_LVDS0_TX1_P = 123,
> -	MX53_PAD_LVDS0_TX0_P = 124,
> -	MX53_PAD_GPIO_10 = 125,
> -	MX53_PAD_GPIO_11 = 126,
> -	MX53_PAD_GPIO_12 = 127,
> -	MX53_PAD_GPIO_13 = 128,
> -	MX53_PAD_GPIO_14 = 129,
> -	MX53_PAD_NANDF_CLE = 130,
> -	MX53_PAD_NANDF_ALE = 131,
> -	MX53_PAD_NANDF_WP_B = 132,
> -	MX53_PAD_NANDF_RB0 = 133,
> -	MX53_PAD_NANDF_CS0 = 134,
> -	MX53_PAD_NANDF_CS1 = 135,
> -	MX53_PAD_NANDF_CS2 = 136,
> -	MX53_PAD_NANDF_CS3 = 137,
> -	MX53_PAD_FEC_MDIO = 138,
> -	MX53_PAD_FEC_REF_CLK = 139,
> -	MX53_PAD_FEC_RX_ER = 140,
> -	MX53_PAD_FEC_CRS_DV = 141,
> -	MX53_PAD_FEC_RXD1 = 142,
> -	MX53_PAD_FEC_RXD0 = 143,
> -	MX53_PAD_FEC_TX_EN = 144,
> -	MX53_PAD_FEC_TXD1 = 145,
> -	MX53_PAD_FEC_TXD0 = 146,
> -	MX53_PAD_FEC_MDC = 147,
> -	MX53_PAD_PATA_DIOW = 148,
> -	MX53_PAD_PATA_DMACK = 149,
> -	MX53_PAD_PATA_DMARQ = 150,
> -	MX53_PAD_PATA_BUFFER_EN = 151,
> -	MX53_PAD_PATA_INTRQ = 152,
> -	MX53_PAD_PATA_DIOR = 153,
> -	MX53_PAD_PATA_RESET_B = 154,
> -	MX53_PAD_PATA_IORDY = 155,
> -	MX53_PAD_PATA_DA_0 = 156,
> -	MX53_PAD_PATA_DA_1 = 157,
> -	MX53_PAD_PATA_DA_2 = 158,
> -	MX53_PAD_PATA_CS_0 = 159,
> -	MX53_PAD_PATA_CS_1 = 160,
> -	MX53_PAD_PATA_DATA0 = 161,
> -	MX53_PAD_PATA_DATA1 = 162,
> -	MX53_PAD_PATA_DATA2 = 163,
> -	MX53_PAD_PATA_DATA3 = 164,
> -	MX53_PAD_PATA_DATA4 = 165,
> -	MX53_PAD_PATA_DATA5 = 166,
> -	MX53_PAD_PATA_DATA6 = 167,
> -	MX53_PAD_PATA_DATA7 = 168,
> -	MX53_PAD_PATA_DATA8 = 169,
> -	MX53_PAD_PATA_DATA9 = 170,
> -	MX53_PAD_PATA_DATA10 = 171,
> -	MX53_PAD_PATA_DATA11 = 172,
> -	MX53_PAD_PATA_DATA12 = 173,
> -	MX53_PAD_PATA_DATA13 = 174,
> -	MX53_PAD_PATA_DATA14 = 175,
> -	MX53_PAD_PATA_DATA15 = 176,
> -	MX53_PAD_SD1_DATA0 = 177,
> -	MX53_PAD_SD1_DATA1 = 178,
> -	MX53_PAD_SD1_CMD = 179,
> -	MX53_PAD_SD1_DATA2 = 180,
> -	MX53_PAD_SD1_CLK = 181,
> -	MX53_PAD_SD1_DATA3 = 182,
> -	MX53_PAD_SD2_CLK = 183,
> -	MX53_PAD_SD2_CMD = 184,
> -	MX53_PAD_SD2_DATA3 = 185,
> -	MX53_PAD_SD2_DATA2 = 186,
> -	MX53_PAD_SD2_DATA1 = 187,
> -	MX53_PAD_SD2_DATA0 = 188,
> -	MX53_PAD_GPIO_0 = 189,
> -	MX53_PAD_GPIO_1 = 190,
> -	MX53_PAD_GPIO_9 = 191,
> -	MX53_PAD_GPIO_3 = 192,
> -	MX53_PAD_GPIO_6 = 193,
> -	MX53_PAD_GPIO_2 = 194,
> -	MX53_PAD_GPIO_4 = 195,
> -	MX53_PAD_GPIO_5 = 196,
> -	MX53_PAD_GPIO_7 = 197,
> -	MX53_PAD_GPIO_8 = 198,
> -	MX53_PAD_GPIO_16 = 199,
> -	MX53_PAD_GPIO_17 = 200,
> -	MX53_PAD_GPIO_18 = 201,
> +	MX53_PAD_GPIO_19 = 0,
> +	MX53_PAD_KEY_COL0 = 1,

Why not skip the = xx altogether??  The enum will auto-increment.

> +	MX53_PAD_KEY_ROW0 = 2,
> +	MX53_PAD_KEY_COL1 = 3,
> +	MX53_PAD_KEY_ROW1 = 4,
> +	MX53_PAD_KEY_COL2 = 5,
> +	MX53_PAD_KEY_ROW2 = 6,
> +	MX53_PAD_KEY_COL3 = 7,
> +	MX53_PAD_KEY_ROW3 = 8,
> +	MX53_PAD_KEY_COL4 = 9,
> +	MX53_PAD_KEY_ROW4 = 10,
> +	MX53_PAD_DI0_DISP_CLK = 11,
> +	MX53_PAD_DI0_PIN15 = 12,
> +	MX53_PAD_DI0_PIN2 = 13,
> +	MX53_PAD_DI0_PIN3 = 14,
> +	MX53_PAD_DI0_PIN4 = 15,
> +	MX53_PAD_DISP0_DAT0 = 16,
> +	MX53_PAD_DISP0_DAT1 = 17,
> +	MX53_PAD_DISP0_DAT2 = 18,
> +	MX53_PAD_DISP0_DAT3 = 19,
> +	MX53_PAD_DISP0_DAT4 = 20,
> +	MX53_PAD_DISP0_DAT5 = 21,
> +	MX53_PAD_DISP0_DAT6 = 22,
> +	MX53_PAD_DISP0_DAT7 = 23,
> +	MX53_PAD_DISP0_DAT8 = 24,
> +	MX53_PAD_DISP0_DAT9 = 25,
> +	MX53_PAD_DISP0_DAT10 = 26,
> +	MX53_PAD_DISP0_DAT11 = 27,
> +	MX53_PAD_DISP0_DAT12 = 28,
> +	MX53_PAD_DISP0_DAT13 = 29,
> +	MX53_PAD_DISP0_DAT14 = 30,
> +	MX53_PAD_DISP0_DAT15 = 31,
> +	MX53_PAD_DISP0_DAT16 = 32,
> +	MX53_PAD_DISP0_DAT17 = 33,
> +	MX53_PAD_DISP0_DAT18 = 34,
> +	MX53_PAD_DISP0_DAT19 = 35,
> +	MX53_PAD_DISP0_DAT20 = 36,
> +	MX53_PAD_DISP0_DAT21 = 37,
> +	MX53_PAD_DISP0_DAT22 = 38,
> +	MX53_PAD_DISP0_DAT23 = 39,
> +	MX53_PAD_CSI0_PIXCLK = 40,
> +	MX53_PAD_CSI0_MCLK = 41,
> +	MX53_PAD_CSI0_DATA_EN = 42,
> +	MX53_PAD_CSI0_VSYNC = 43,
> +	MX53_PAD_CSI0_DAT4 = 44,
> +	MX53_PAD_CSI0_DAT5 = 45,
> +	MX53_PAD_CSI0_DAT6 = 46,
> +	MX53_PAD_CSI0_DAT7 = 47,
> +	MX53_PAD_CSI0_DAT8 = 48,
> +	MX53_PAD_CSI0_DAT9 = 49,
> +	MX53_PAD_CSI0_DAT10 = 50,
> +	MX53_PAD_CSI0_DAT11 = 51,
> +	MX53_PAD_CSI0_DAT12 = 52,
> +	MX53_PAD_CSI0_DAT13 = 53,
> +	MX53_PAD_CSI0_DAT14 = 54,
> +	MX53_PAD_CSI0_DAT15 = 55,
> +	MX53_PAD_CSI0_DAT16 = 56,
> +	MX53_PAD_CSI0_DAT17 = 57,
> +	MX53_PAD_CSI0_DAT18 = 58,
> +	MX53_PAD_CSI0_DAT19 = 59,
> +	MX53_PAD_EIM_A25 = 60,
> +	MX53_PAD_EIM_EB2 = 61,
> +	MX53_PAD_EIM_D16 = 62,
> +	MX53_PAD_EIM_D17 = 63,
> +	MX53_PAD_EIM_D18 = 64,
> +	MX53_PAD_EIM_D19 = 65,
> +	MX53_PAD_EIM_D20 = 66,
> +	MX53_PAD_EIM_D21 = 67,
> +	MX53_PAD_EIM_D22 = 68,
> +	MX53_PAD_EIM_D23 = 69,
> +	MX53_PAD_EIM_EB3 = 70,
> +	MX53_PAD_EIM_D24 = 71,
> +	MX53_PAD_EIM_D25 = 72,
> +	MX53_PAD_EIM_D26 = 73,
> +	MX53_PAD_EIM_D27 = 74,
> +	MX53_PAD_EIM_D28 = 75,
> +	MX53_PAD_EIM_D29 = 76,
> +	MX53_PAD_EIM_D30 = 77,
> +	MX53_PAD_EIM_D31 = 78,
> +	MX53_PAD_EIM_A24 = 79,
> +	MX53_PAD_EIM_A23 = 80,
> +	MX53_PAD_EIM_A22 = 81,
> +	MX53_PAD_EIM_A21 = 82,
> +	MX53_PAD_EIM_A20 = 83,
> +	MX53_PAD_EIM_A19 = 84,
> +	MX53_PAD_EIM_A18 = 85,
> +	MX53_PAD_EIM_A17 = 86,
> +	MX53_PAD_EIM_A16 = 87,
> +	MX53_PAD_EIM_CS0 = 88,
> +	MX53_PAD_EIM_CS1 = 89,
> +	MX53_PAD_EIM_OE = 90,
> +	MX53_PAD_EIM_RW = 91,
> +	MX53_PAD_EIM_LBA = 92,
> +	MX53_PAD_EIM_EB0 = 93,
> +	MX53_PAD_EIM_EB1 = 94,
> +	MX53_PAD_EIM_DA0 = 95,
> +	MX53_PAD_EIM_DA1 = 96,
> +	MX53_PAD_EIM_DA2 = 97,
> +	MX53_PAD_EIM_DA3 = 98,
> +	MX53_PAD_EIM_DA4 = 99,
> +	MX53_PAD_EIM_DA5 = 100,
> +	MX53_PAD_EIM_DA6 = 101,
> +	MX53_PAD_EIM_DA7 = 102,
> +	MX53_PAD_EIM_DA8 = 103,
> +	MX53_PAD_EIM_DA9 = 104,
> +	MX53_PAD_EIM_DA10 = 105,
> +	MX53_PAD_EIM_DA11 = 106,
> +	MX53_PAD_EIM_DA12 = 107,
> +	MX53_PAD_EIM_DA13 = 108,
> +	MX53_PAD_EIM_DA14 = 109,
> +	MX53_PAD_EIM_DA15 = 110,
> +	MX53_PAD_NANDF_WE_B = 111,
> +	MX53_PAD_NANDF_RE_B = 112,
> +	MX53_PAD_EIM_WAIT = 113,
> +	MX53_PAD_LVDS1_TX3_P = 114,
> +	MX53_PAD_LVDS1_TX2_P = 115,
> +	MX53_PAD_LVDS1_CLK_P = 116,
> +	MX53_PAD_LVDS1_TX1_P = 117,
> +	MX53_PAD_LVDS1_TX0_P = 118,
> +	MX53_PAD_LVDS0_TX3_P = 119,
> +	MX53_PAD_LVDS0_CLK_P = 120,
> +	MX53_PAD_LVDS0_TX2_P = 121,
> +	MX53_PAD_LVDS0_TX1_P = 122,
> +	MX53_PAD_LVDS0_TX0_P = 123,
> +	MX53_PAD_GPIO_10 = 124,
> +	MX53_PAD_GPIO_11 = 125,
> +	MX53_PAD_GPIO_12 = 126,
> +	MX53_PAD_GPIO_13 = 127,
> +	MX53_PAD_GPIO_14 = 128,
> +	MX53_PAD_NANDF_CLE = 129,
> +	MX53_PAD_NANDF_ALE = 130,
> +	MX53_PAD_NANDF_WP_B = 131,
> +	MX53_PAD_NANDF_RB0 = 132,
> +	MX53_PAD_NANDF_CS0 = 133,
> +	MX53_PAD_NANDF_CS1 = 134,
> +	MX53_PAD_NANDF_CS2 = 135,
> +	MX53_PAD_NANDF_CS3 = 136,
> +	MX53_PAD_FEC_MDIO = 137,
> +	MX53_PAD_FEC_REF_CLK = 138,
> +	MX53_PAD_FEC_RX_ER = 139,
> +	MX53_PAD_FEC_CRS_DV = 140,
> +	MX53_PAD_FEC_RXD1 = 141,
> +	MX53_PAD_FEC_RXD0 = 142,
> +	MX53_PAD_FEC_TX_EN = 143,
> +	MX53_PAD_FEC_TXD1 = 144,
> +	MX53_PAD_FEC_TXD0 = 145,
> +	MX53_PAD_FEC_MDC = 146,
> +	MX53_PAD_PATA_DIOW = 147,
> +	MX53_PAD_PATA_DMACK = 148,
> +	MX53_PAD_PATA_DMARQ = 149,
> +	MX53_PAD_PATA_BUFFER_EN = 150,
> +	MX53_PAD_PATA_INTRQ = 151,
> +	MX53_PAD_PATA_DIOR = 152,
> +	MX53_PAD_PATA_RESET_B = 153,
> +	MX53_PAD_PATA_IORDY = 154,
> +	MX53_PAD_PATA_DA_0 = 155,
> +	MX53_PAD_PATA_DA_1 = 156,
> +	MX53_PAD_PATA_DA_2 = 157,
> +	MX53_PAD_PATA_CS_0 = 158,
> +	MX53_PAD_PATA_CS_1 = 159,
> +	MX53_PAD_PATA_DATA0 = 160,
> +	MX53_PAD_PATA_DATA1 = 161,
> +	MX53_PAD_PATA_DATA2 = 162,
> +	MX53_PAD_PATA_DATA3 = 163,
> +	MX53_PAD_PATA_DATA4 = 164,
> +	MX53_PAD_PATA_DATA5 = 165,
> +	MX53_PAD_PATA_DATA6 = 166,
> +	MX53_PAD_PATA_DATA7 = 167,
> +	MX53_PAD_PATA_DATA8 = 168,
> +	MX53_PAD_PATA_DATA9 = 169,
> +	MX53_PAD_PATA_DATA10 = 170,
> +	MX53_PAD_PATA_DATA11 = 171,
> +	MX53_PAD_PATA_DATA12 = 172,
> +	MX53_PAD_PATA_DATA13 = 173,
> +	MX53_PAD_PATA_DATA14 = 174,
> +	MX53_PAD_PATA_DATA15 = 175,
> +	MX53_PAD_SD1_DATA0 = 176,
> +	MX53_PAD_SD1_DATA1 = 177,
> +	MX53_PAD_SD1_CMD = 178,
> +	MX53_PAD_SD1_DATA2 = 179,
> +	MX53_PAD_SD1_CLK = 180,
> +	MX53_PAD_SD1_DATA3 = 181,
> +	MX53_PAD_SD2_CLK = 182,
> +	MX53_PAD_SD2_CMD = 183,
> +	MX53_PAD_SD2_DATA3 = 184,
> +	MX53_PAD_SD2_DATA2 = 185,
> +	MX53_PAD_SD2_DATA1 = 186,
> +	MX53_PAD_SD2_DATA0 = 187,
> +	MX53_PAD_GPIO_0 = 188,
> +	MX53_PAD_GPIO_1 = 189,
> +	MX53_PAD_GPIO_9 = 190,
> +	MX53_PAD_GPIO_3 = 191,
> +	MX53_PAD_GPIO_6 = 192,
> +	MX53_PAD_GPIO_2 = 193,
> +	MX53_PAD_GPIO_4 = 194,
> +	MX53_PAD_GPIO_5 = 195,
> +	MX53_PAD_GPIO_7 = 196,
> +	MX53_PAD_GPIO_8 = 197,
> +	MX53_PAD_GPIO_16 = 198,
> +	MX53_PAD_GPIO_17 = 199,
> +	MX53_PAD_GPIO_18 = 200,
>   };
>   
>   /* imx53 register maps */



From s.hauer at pengutronix.de  Mon Aug 13 15:35:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 13 Aug 2012 21:35:17 +0200
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
In-Reply-To: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
References: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
Message-ID: <20120813193517.GU1451@pengutronix.de>

Hi Dave,

On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:
> Because FIQ handlers get copied straight into the vectors page to
> the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
> start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
> Thumb-2.

I finally came along testing this. I have no Thumb2 capable hardware
to test if it works in thumb2 mode, but at least in Arm mode it works.
This is enough to not introduce a regression, so we can go for this.
I'll add it to my tree with a

Tested-by: Sascha Hauer <s.hauer at pengutronix.de>

Thanks
 Sascha

> 
> This patch adapts the mxc SSI FIQ code suitable for a Thumb-2
> kernel.
> 
> The code contained use of r13 (sp) which isn't allowed in Thumb-2.
> r11 and r13 have been swapped throughout the file to work around
> this.
> 
> Currently, the way that the function to be copied is located using
> labels is a bit ugly: we cannot annotate the FIQ handler properly
> as a Thumb-2 function, because this would set bit 0 of the label
> address seen by the linker, causing off-by-one errors when copying
> the function.  Ideally, the copy would be done with fncpy(), but
> this would require changes to the common set_fiq_handler()
> function.  For now, we don't touch this.
> 
> References to locally-defined global symbols with adr and ldr may
> not be accepted by the assembler in Thumb-2.  Local shadow symbols
> are added to work around this.
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>
> ---
> 
> Note that while this code builds, I don't know the hardware well enough 
> to be confident testing it.  Review and testing from anyone with
> experience of imx SoC audio would be appreciated.
> 
>  arch/arm/plat-mxc/ssi-fiq.S |   89 ++++++++++++++++++++++++-------------------
>  1 files changed, 50 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
> index 8397a2d..a8b93c5 100644
> --- a/arch/arm/plat-mxc/ssi-fiq.S
> +++ b/arch/arm/plat-mxc/ssi-fiq.S
> @@ -34,91 +34,98 @@
>  		.global imx_ssi_fiq_rx_buffer
>  		.global imx_ssi_fiq_tx_buffer
>  
> +/*
> + * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
> + * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
> + * mark the function body so that it can be copied to the FIQ vector in
> + * the vectors page.  imx_ssi_fiq_start should only be called as the result
> + * of an FIQ: calling it directly will not work.
> + */
>  imx_ssi_fiq_start:
> -		ldr r12, imx_ssi_fiq_base
> +		ldr r12, .L_imx_ssi_fiq_base
>  
>  		/* TX */
> -		ldr r11, imx_ssi_fiq_tx_buffer
> +		ldr r13, .L_imx_ssi_fiq_tx_buffer
>  
>  		/* shall we send? */
> -		ldr r13, [r12, #SSI_SIER]
> -		tst r13, #SSI_SIER_TFE0_EN
> +		ldr r11, [r12, #SSI_SIER]
> +		tst r11, #SSI_SIER_TFE0_EN
>  		beq 1f
>  
>  		/* TX FIFO empty? */
> -		ldr r13, [r12, #SSI_SISR]
> -		tst r13, #SSI_SISR_TFE0
> +		ldr r11, [r12, #SSI_SISR]
> +		tst r11, #SSI_SISR_TFE0
>  		beq 1f
>  
>  		mov r10, #0x10000
>  		sub r10, #1
>  		and r10, r10, r8	/* r10: current buffer offset */
>  
> -		add r11, r11, r10
> +		add r13, r13, r10
>  
> -		ldrh r13, [r11]
> -		strh r13, [r12, #SSI_STX0]
> +		ldrh r11, [r13]
> +		strh r11, [r12, #SSI_STX0]
>  
> -		ldrh r13, [r11, #2]
> -		strh r13, [r12, #SSI_STX0]
> +		ldrh r11, [r13, #2]
> +		strh r11, [r12, #SSI_STX0]
>  
> -		ldrh r13, [r11, #4]
> -		strh r13, [r12, #SSI_STX0]
> +		ldrh r11, [r13, #4]
> +		strh r11, [r12, #SSI_STX0]
>  
> -		ldrh r13, [r11, #6]
> -		strh r13, [r12, #SSI_STX0]
> +		ldrh r11, [r13, #6]
> +		strh r11, [r12, #SSI_STX0]
>  
>  		add r10, #8
> -		lsr r13, r8, #16	/* r13: buffer size */
> -		cmp r10, r13
> -		lslgt r8, r13, #16
> +		lsr r11, r8, #16	/* r11: buffer size */
> +		cmp r10, r11
> +		lslgt r8, r11, #16
>  		addle r8, #8
>  1:
>  		/* RX */
>  
>  		/* shall we receive? */
> -		ldr r13, [r12, #SSI_SIER]
> -		tst r13, #SSI_SIER_RFF0_EN
> +		ldr r11, [r12, #SSI_SIER]
> +		tst r11, #SSI_SIER_RFF0_EN
>  		beq 1f
>  
>  		/* RX FIFO full? */
> -		ldr r13, [r12, #SSI_SISR]
> -		tst r13, #SSI_SISR_RFF0
> +		ldr r11, [r12, #SSI_SISR]
> +		tst r11, #SSI_SISR_RFF0
>  		beq 1f
>  
> -		ldr r11, imx_ssi_fiq_rx_buffer
> +		ldr r13, .L_imx_ssi_fiq_rx_buffer
>  
>  		mov r10, #0x10000
>  		sub r10, #1
>  		and r10, r10, r9	/* r10: current buffer offset */
>  
> -		add r11, r11, r10
> +		add r13, r13, r10
>  
> -		ldr r13, [r12, #SSI_SACNT]
> -		tst r13, #SSI_SACNT_AC97EN
> +		ldr r11, [r12, #SSI_SACNT]
> +		tst r11, #SSI_SACNT_AC97EN
>  
> -		ldr r13, [r12, #SSI_SRX0]
> -		strh r13, [r11]
> +		ldr r11, [r12, #SSI_SRX0]
> +		strh r11, [r13]
>  
> -		ldr r13, [r12, #SSI_SRX0]
> -		strh r13, [r11, #2]
> +		ldr r11, [r12, #SSI_SRX0]
> +		strh r11, [r13, #2]
>  
>  		/* dummy read to skip slot 12 */
> -		ldrne r13, [r12, #SSI_SRX0]
> +		ldrne r11, [r12, #SSI_SRX0]
>  
> -		ldr r13, [r12, #SSI_SRX0]
> -		strh r13, [r11, #4]
> +		ldr r11, [r12, #SSI_SRX0]
> +		strh r11, [r13, #4]
>  
> -		ldr r13, [r12, #SSI_SRX0]
> -		strh r13, [r11, #6]
> +		ldr r11, [r12, #SSI_SRX0]
> +		strh r11, [r13, #6]
>  
>  		/* dummy read to skip slot 12 */
> -		ldrne r13, [r12, #SSI_SRX0]
> +		ldrne r11, [r12, #SSI_SRX0]
>  
>  		add r10, #8
> -		lsr r13, r9, #16	/* r13: buffer size */
> -		cmp r10, r13
> -		lslgt r9, r13, #16
> +		lsr r11, r9, #16	/* r11: buffer size */
> +		cmp r10, r11
> +		lslgt r9, r11, #16
>  		addle r9, #8
>  
>  1:
> @@ -126,11 +133,15 @@ imx_ssi_fiq_start:
>  		subs	pc, lr, #4
>  
>  		.align
> +.L_imx_ssi_fiq_base:
>  imx_ssi_fiq_base:
>  		.word 0x0
> +.L_imx_ssi_fiq_rx_buffer:
>  imx_ssi_fiq_rx_buffer:
>  		.word 0x0
> +.L_imx_ssi_fiq_tx_buffer:
>  imx_ssi_fiq_tx_buffer:
>  		.word 0x0
> +.L_imx_ssi_fiq_end:
>  imx_ssi_fiq_end:
>  
> -- 
> 1.7.4.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From manabian at gmail.com  Mon Aug 13 15:59:10 2012
From: manabian at gmail.com (Joachim Eastwood)
Date: Mon, 13 Aug 2012 21:59:10 +0200
Subject: [PATCH] atmel-ssc: include linux/io.h for raw io
Message-ID: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>

Include linux/io.h for raw io operations in atmel-scc header.

This fixes the following build error:
  CC [M]  sound/soc/atmel/atmel_ssc_dai.o
sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'

Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
---
 include/linux/atmel-ssc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
index 0602339..4eb3175 100644
--- a/include/linux/atmel-ssc.h
+++ b/include/linux/atmel-ssc.h
@@ -3,6 +3,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
 struct ssc_device {
 	struct list_head	list;
-- 
1.7.11



From g.liakhovetski at gmx.de  Mon Aug 13 16:12:27 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Mon, 13 Aug 2012 22:12:27 +0200 (CEST)
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120810155128.GM2066@mudshark.cambridge.arm.com>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
Message-ID: <Pine.LNX.4.64.1208132210590.17448@axis700.grange>

Hi all

On Fri, 10 Aug 2012, Will Deacon wrote:

> Hello,
> 
> By now, those of you on CC should have received your invitation codes for
> the ARM mini-summit in a couple of weeks time. If not, please contact me
> separately and I'll look into it [Magnus -- I'm aware you haven't
> received anything yet, hopefully this will be fixed soon].
> 
> The invitation email was slightly misleading as it only referred to Tuesday
> 28 August, when in fact the mini-summit will be held on *both* Monday 27
> and Tuesday 28. We will run topics in the morning (and allow an hour in
> the afternoon for overflow discussion) and dedicate the rest of the time
> to hacking. Initial topic proposals are:
> 
> 
> Monday
> ------
> 
> Secure monitor APIs
> Virtualisation (kvm/xen)
> DMA mapping
> Stable platform deprecation
> 
> Tuesday
> -------
> 
> Single zImage
> AArch64
> big.LITTLE
> DMA engine

Depending on the exact contents of the above topic and the V4L schedule, I 
might be interested and able to participate. However, it seems, the V4L 
schedule is going to be quite full too.

Thanks
Guennadi

> arm-soc process review
> 
> 
> This list of topics already fills the allocated time, but if there is
> sufficient interest in discussing additional items, we can try to
> prioritise.
> 
> We look forward to seeing you in San Diego!
> 
> Will [and the rest of the organisation group]
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From gmbnomis at gmail.com  Mon Aug 13 16:15:35 2012
From: gmbnomis at gmail.com (Simon Baatz)
Date: Mon, 13 Aug 2012 22:15:35 +0200
Subject: [RESEND PATCH] ARM: Handle user space mapped pages in
 flush_kernel_dcache_page
In-Reply-To: <20120728205509.GA3676@schnuecks.de>
References: <1343464914-31084-1-git-send-email-gmbnomis@gmail.com>
 <20120728112707.GE6802@n2100.arm.linux.org.uk>
 <20120728205509.GA3676@schnuecks.de>
Message-ID: <20120813201534.GA3989@schnuecks.de>

On Sat, Jul 28, 2012 at 10:55:09PM +0200, Simon Baatz wrote:
> Hi Russel,
> 
> On Sat, Jul 28, 2012 at 12:27:07PM +0100, Russell King - ARM Linux wrote:
> > On Sat, Jul 28, 2012 at 10:41:54AM +0200, Simon Baatz wrote:
> > > a while ago I sent the patch above to fix a data corruption problem
> > > on VIVT architectures (and probably VIPT aliasing).  There has been a
> > > bit of discussion with Catalin, but there was no real conclusion on
> > > how to proceed.  (See
> > > http://www.spinics.net/lists/arm-kernel/msg176913.html for the
> > > original post)
> > 
> > Going back to that post:
> > 
> >  However, this assumption is not true for direct IO or SG_IO (see
> >  e.g. [1] and [2]). This is why vgchange fails with mv_cesa as reported
> >  by me in [3]. (Btw., flush_kernel_dcache_page is also called from
> >  "copy_strings" in fs/exec.c when copying env/arg strings between
> >  processes. Thus, its use is not restricted to device drivers.)
> > 
> > The calls from copy_strings is not a problem - because the newly allocated
> > pages will have PG_arch_1 clear, and when the page is passed to set_pte(),
> > it will be flushed.
> 
> I was not implying that copy_strings has a problem. But, from
> copy_string's comment:
> 
> /*
>  * 'copy_strings()' copies argument/environment strings from the old
>  * processes's memory to the new process's stack. ...
> 
> 
> You said below that flush_kernel_dcache_page() is supposed to be
> called for page cache pages only.  Hmm, in the new process's stack?
> 
>  
> > We _certainly_ do not want to make flush_kernel_dcache_page() do what you're
> > doing, because it will mean we're over-flushing *all* pages on VIVT caches.
> > Not only will we be flushing them for DMA, but we'll then do it again
> > when flush_kernel_dcache_page() is invoked, and then possibly again when
> > the page eventually ends up being visible to userspace.
> 
> Why should flush_kernel_dcache_page() be invoked at all for DMAed
> pages?  If you state that this patch over-flushes *all* pages, I
> assume that you _certainly_ do not understand the mapping == NULL
> case.  ;-)
> 
> Can a page in the page cache have page->mapping == NULL? If not
> page_mapping() only returns NULL in the anon case.
> 
> I found this strange myself, but this is the way I thought
> flush_dcache_page() handles this.  But now I realized it's probably
> just a bug in that function, because flush_dcache_page() is not
> supposed to handle anon pages at all.  (However, it flushes the
> kernel mapping currently, since mapping == NULL for these pages.)
> 
> If we find out that flush_kernel_dcache_page() needs to handle
> anonymous pages, it should do this explicitly.
> 
> > > The case is not hit too often apparently; the ingredients are PIO
> > > (like) driver, use of flush_kernel_dcache_page(), and direct I/O. 
> > 
> > Right, so we need to analyse the direct IO paths and work out whether
> > they're using the flush_* interfaces correctly, and even whether they're
> > using the correct interfaces.

Ok, I digged a little, but came to the same conclusion as before:

   O_DIRECT uses "get_user_pages()" pages (user mapped pages) to feed
   the block layer with rather than pagecache pages.  However
   pagecache pages can also be user mapped, so I'm thinking there
   should be enough cache flushing APIs to be able to handle either
   case.

(from https://lkml.org/lkml/2008/11/20/20)
 
flush_anon_page() and flush_kernel_dcache_page() were introduced
in the same patch set:

   Currently, get_user_pages() returns fully coherent pages to the
   kernel for anything other than anonymous pages.  This is a problem
   for things like fuse and the SCSI generic ioctl SG_IO which can
   potentially wish to do DMA to anonymous pages passed in by users.

   The fix is to add a new memory management API: flush_anon_page()
   which is used in get_user_pages() to make anonymous pages
   coherent.

(from https://lkml.org/lkml/2006/3/21/363)

   We have a problem in a lot of emulated storage in that it takes a
   page from get_user_pages() and does something like

   kmap_atomic(page)
   modify page
   kunmap_atomic(page)

   However, nothing has flushed the kernel cache view of the page
   before the kunmap.  We need a lightweight API to do this, so this
   new API would specifically be for flushing the kernel cache view
   of a user page which the kernel has modified.  The driver would
   need to add flush_kernel_dcache_page(page) before the final
   kunmap.

(from https://lkml.org/lkml/2006/3/21/364)

I have seen much discussion whether this make sense, but no changes
to this approach.

Thus:

- When using O_DIRECT, the block layer sees pages from get_user_pages()

- get_user_pages() is supposed to handle anonymous pages as well as
  user mapped page cache pages.

-> the block layer (and thus device drivers) will see these types of
   pages in this case.

- flush_kernel_dcache_page()'s intention is to handle these user pages


As said before, I tried to be least intrusive with my patch. Leave
the common case completely untouched (page cache page with no user
mappings). Don't flush and don't do anything to PG_dcache_clean.

However, in case of an anonymous page or a page cache page with user
mappings, just flush the page. I don't think setting PG_dcache_clean
is of much value here (the page already has user mappings).

However, if the patch should be more explicit, I can change that of
course, i.e. mimic flush_dcache_page, but only for the kernel
mapping. 


A different story is whether PIO device drivers (instead of emulated
storage ones) should use flush_kernel_dcache_page() or
flush_dache_page().  In almost all cases, they seem to use
flush_dcache_page() today, which is not supposed to handle anonymous
pages (but does at least for the kernel mapping). 

- Simon


> I agree. I am not claiming that my patch is necessarily correct; this
> is a tangled mess for me.  But hey, it got the discussion finally
> going.
>  
> > Note that flush_*dcache_page() are supposed to only be concerned with
> > page cache pages, not anonymous pages.  flush_anon_page() is all about
> > anonymous pages only.
> 
> May be, may be not. From Documentation/cachetlb.txt:
> 
>   void flush_dcache_page(struct page *page)
> 
> 	Any time the kernel writes to a page cache page, _OR_
> 	the kernel is about to read from a page cache page and
> 	user space shared/writable mappings of this page potentially
> 	exist, this routine is called.
> 
>   void flush_kernel_dcache_page(struct page *page)
> 	When the kernel needs to modify a user page is has obtained
> 	with kmap, it calls this function after all modifications are
> 	complete (but before kunmapping it) to bring the underlying
> 	page up to date.
> 



From thierry.reding at avionic-design.de  Mon Aug 13 16:33:00 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 13 Aug 2012 22:33:00 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <50294BCA.1070807@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
Message-ID: <20120813203300.GA8891@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 13, 2012 at 12:47:38PM -0600, Stephen Warren wrote:
> On 08/13/2012 11:40 AM, Thierry Reding wrote:
> > On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
> >> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> >>> This patch series adds support for device tree based probing of
> >>> the PCIe controller found on Tegra SoCs.
> >> 
> >> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
> >> that PCIe doesn't work on TrimSlice when booting use device tree.
> >> I think I found the cause, and I can't see why the same problem
> >> doesn't affect this series. Perhaps you can enlighten me?
> ...
> >> PCI: Device 0000:01:00.0 not available because of resource
> >> collisions
> ...
> > I've looked into this a bit, and it seems like ARM is using an
> > open- coded version of the pci_enable_resources() function here,
> > with the only difference being the unconditional enabling of both
> > I/O and memory- mapped access for bridges. On Tegra there is
> > already a PCI fixup to do this, so pci_enable_resources() can be
> > used as-is. I came up with the attached patch but haven't been able
> > to test it yet.
> 
> Thanks very much for looking into this.
> 
> The patch did alter the behavior a little for TrimSlice, but didn't
> solve the problem. The old error messages:
> 
> > [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
> > [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
> > [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22
> 
> Were replaced with the following with your patch:
> 
> > [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
> > [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
> > [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22
> 
> This message appears from drivers/pci/setup-res.c pci_enable_resources()
> due to:
> 
> > 		if (!r->parent) {
> > 			dev_err(&dev->dev, "device not available "
> > 				"(can't reserve %pR)\n", r);
> > 			return -EINVAL;
> > 		}

Looking at the code some more, this may be caused by the pci_remap_io()
patch series, so you might want to revert that patch and see if it fixes
the I/O resources.

> That check doesn't appear in ARM's custom pcibios_enable_device().
> Disabling that check yields:
> 
> > [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
> > [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> > [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> > [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16
> 
> I think that's because the pci_dev's resources are initially assigned
> PCI-aperture-relative addresses, and then these are later patched up to
> take account of where the aperture is mapped into the CPU's address space.
> 
> Boot log using board files:
> 
> > [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> > [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> > [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> > [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> ...
> > [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> > [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> > [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> > [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> ... (I added some extra printks:)
> > [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
> > [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
> > [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]
> 
> whereas for a device tree boot:
> 
> (same):
> > [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> > [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> > [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> > [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> ... (request region happens early)
> > [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
> > [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
> > [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> > [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> ... (same, just happens too late)
> > [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> > [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> > [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> > [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> 
> I suspect this is all still related to the PCI devices themselves being
> probed much earlier in the overall PCI initialization sequence when the
> PCI controller is probed later in the boot sequence, whereas PCI device
> probe is deferred until the overall PCI initialization sequence is
> complete if the PCI controller is probed very early in the boot sequence.
> 
> Does anyone know where/what that "probe now" vs. "probe later" decision
> point is? I'll try and track it down if nobody beats me to it.

There's the io_offset and mem_offset fields that I've completely ignored
up to now. Can you try the patch below to see if it changes anything?
I'm sorry but I can't test any of this myself right now.

Thierry
-------------- next part --------------
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 3463fb5..9b9b3e0 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -395,7 +395,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
 	pp->res[0].flags = IORESOURCE_MEM;
 	if (request_resource(&iomem_resource, &pp->res[0]))
 		panic("Request PCIe Memory resource failed\n");
-	pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
+	pci_add_resource_offset(&sys->resources, &pp->res[0], pp->res[0].start);
 
 	/*
 	 * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -414,7 +414,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
 	pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 	if (request_resource(&iomem_resource, &pp->res[1]))
 		panic("Request PCIe Prefetch Memory resource failed\n");
-	pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+	pci_add_resource_offset(&sys->resources, &pp->res[1], pp->res[1].start);
 
 	return 1;
 }
-------------- next part --------------
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From m-karicheri2 at ti.com  Mon Aug 13 17:13:29 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Mon, 13 Aug 2012 21:13:29 +0000
Subject: [linux-keystone] Re: [PATCH] arm:davinci: clk - migrate to new
 common clock API
In-Reply-To: <20120802212025.GI29410@gmail.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
 <20120802212025.GI29410@gmail.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041A0544@DFLE12.ent.ti.com>

>> -----Original Message-----
>> From: Turquette, Mike
>> Sent: Thursday, August 02, 2012 5:20 PM
>> To: Karicheri, Muralidharan
>> Cc: linux-arm-kernel at lists.infradead.org; davinci-linux-open-
>> source at linux.davincidsp.com; linux-keystone at list.ti.com - Linux developers for Keystone
>> family of devices (May contain non-TIers); Chemparathy, Cyril; Nori, Sekhar;
>> linux at arm.linux.org.uk
>> Subject: [linux-keystone] Re: [PATCH] arm:davinci: clk - migrate to new common clock
>> API
>> 
>> On 20120802-12:53, Murali Karicheri wrote:
>> > As a first step towards migrating davinci platforms to use common clock
>> > framework, replace all instances of clk_enable() with clk_prepare_enable()
>> > and clk_disable() with clk_disable_unprepare(). Until the platform is
>> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> > adds a might_sleep() call and would work without any issues.
>> >
>> > This will make it easy later to switch to common clk based implementation
>> > of clk driver from DaVinci specific driver.
>> >
>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> 
>> Murali,
>> 
>> The important thing to know about clk_prepare is that it might sleep.
>> All of the functions below look like initialization functions for code
>> that is never run in interrupt context.  If you can confirm that this is
>> true then feel free to add my,
>> 

Mike,

I believe they are. I will double check and then post the patch again. If they are called under
interrupt context, basically I need to make two API calls instead as below right?

clk_prepare()
clk_enable()

Murali Karicheri
Software Design Engineer


>> Reviewed-by: Mike Turquette <mturquette at linaro.org>
>> 
>> Regards,
>> Mike
>> 
>> > ---
>> >  arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
>> >  arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
>> >  arch/arm/mach-davinci/board-dm365-evm.c     |    4 ++--
>> >  arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
>> >  arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
>> >  arch/arm/mach-davinci/devices-da8xx.c       |    6 +++---
>> >  arch/arm/mach-davinci/serial.c              |    2 +-
>> >  arch/arm/mach-davinci/time.c                |    4 ++--
>> >  8 files changed, 12 insertions(+), 12 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-
>> davinci/board-dm355-evm.c
>> > index 1c7b1f4..4821fba 100644
>> > --- a/arch/arm/mach-davinci/board-dm355-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm355-evm.c
>> > @@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
>> >  	if (IS_ERR(aemif))
>> >  		WARN("%s: unable to get AEMIF clock\n", __func__);
>> >  	else
>> > -		clk_enable(aemif);
>> > +		clk_prepare_enable(aemif);
>> >
>> >  	platform_add_devices(davinci_evm_devices,
>> >  			     ARRAY_SIZE(davinci_evm_devices));
>> > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-
>> davinci/board-dm355-leopard.c
>> > index 8e77032..b754ccf 100644
>> > --- a/arch/arm/mach-davinci/board-dm355-leopard.c
>> > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
>> > @@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
>> >  	if (IS_ERR(aemif))
>> >  		WARN("%s: unable to get AEMIF clock\n", __func__);
>> >  	else
>> > -		clk_enable(aemif);
>> > +		clk_prepare_enable(aemif);
>> >
>> >  	platform_add_devices(davinci_leopard_devices,
>> >  			     ARRAY_SIZE(davinci_leopard_devices));
>> > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-
>> davinci/board-dm365-evm.c
>> > index 2830692..3a4743b 100644
>> > --- a/arch/arm/mach-davinci/board-dm365-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm365-evm.c
>> > @@ -481,7 +481,7 @@ static void __init evm_init_cpld(void)
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> >  	if (IS_ERR(aemif_clk))
>> >  		return;
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
>> >  			"cpld") == NULL)
>> > @@ -492,7 +492,7 @@ static void __init evm_init_cpld(void)
>> >  				SECTION_SIZE);
>> >  fail:
>> >  		pr_err("ERROR: can't map CPLD\n");
>> > -		clk_disable(aemif_clk);
>> > +		clk_disable_unprepare(aemif_clk);
>> >  		return;
>> >  	}
>> >
>> > diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-
>> davinci/board-dm644x-evm.c
>> > index d34ed55..04ef708 100644
>> > --- a/arch/arm/mach-davinci/board-dm644x-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
>> > @@ -775,7 +775,7 @@ static __init void davinci_evm_init(void)
>> >  	struct davinci_soc_info *soc_info = &davinci_soc_info;
>> >
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (HAS_ATA) {
>> >  		if (HAS_NAND || HAS_NOR)
>> > diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-
>> davinci/board-neuros-osd2.c
>> > index 5de69f2..7fdd0a7b 100644
>> > --- a/arch/arm/mach-davinci/board-neuros-osd2.c
>> > +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
>> > @@ -221,7 +221,7 @@ static __init void davinci_ntosd2_init(void)
>> >  	int	status;
>> >
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (HAS_ATA) {
>> >  		if (HAS_NAND)
>> > diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-
>> da8xx.c
>> > index d1624a3..20141f5 100644
>> > --- a/arch/arm/mach-davinci/devices-da8xx.c
>> > +++ b/arch/arm/mach-davinci/devices-da8xx.c
>> > @@ -905,7 +905,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>> *addr)
>> >  	if (IS_ERR(da850_sata_clk))
>> >  		return PTR_ERR(da850_sata_clk);
>> >
>> > -	ret = clk_enable(da850_sata_clk);
>> > +	ret = clk_prepare_enable(da850_sata_clk);
>> >  	if (ret)
>> >  		goto err0;
>> >
>> > @@ -936,7 +936,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>> *addr)
>> >  	return 0;
>> >
>> >  err1:
>> > -	clk_disable(da850_sata_clk);
>> > +	clk_disable_unprepare(da850_sata_clk);
>> >  err0:
>> >  	clk_put(da850_sata_clk);
>> >  	return ret;
>> > @@ -944,7 +944,7 @@ err0:
>> >
>> >  static void da850_sata_exit(struct device *dev)
>> >  {
>> > -	clk_disable(da850_sata_clk);
>> > +	clk_disable_unprepare(da850_sata_clk);
>> >  	clk_put(da850_sata_clk);
>> >  }
>> >
>> > diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
>> > index 1875740..24ddb0d 100644
>> > --- a/arch/arm/mach-davinci/serial.c
>> > +++ b/arch/arm/mach-davinci/serial.c
>> > @@ -95,7 +95,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
>> >  			continue;
>> >  		}
>> >
>> > -		clk_enable(uart_clk);
>> > +		clk_prepare_enable(uart_clk);
>> >  		p->uartclk = clk_get_rate(uart_clk);
>> >
>> >  		if (!p->membase && p->mapbase) {
>> > diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
>> > index 75da315..9847938 100644
>> > --- a/arch/arm/mach-davinci/time.c
>> > +++ b/arch/arm/mach-davinci/time.c
>> > @@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
>> >
>> >  	timer_clk = clk_get(NULL, "timer0");
>> >  	BUG_ON(IS_ERR(timer_clk));
>> > -	clk_enable(timer_clk);
>> > +	clk_prepare_enable(timer_clk);
>> >
>> >  	/* init timer hw */
>> >  	timer_init();
>> > @@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
>> >  	wd_clk = clk_get(&pdev->dev, NULL);
>> >  	if (WARN_ON(IS_ERR(wd_clk)))
>> >  		return;
>> > -	clk_enable(wd_clk);
>> > +	clk_prepare_enable(wd_clk);
>> >
>> >  	/* disable, internal clock source */
>> >  	__raw_writel(0, base + TCR);
>> > --
>> > 1.7.9.5
>> >


From olof at lixom.net  Mon Aug 13 17:13:55 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 13 Aug 2012 14:13:55 -0700
Subject: [GIT PULL 0/3] arm-soc updates
In-Reply-To: <20120813185817.GA17342@pengutronix.de>
References: <1344625575-27560-1-git-send-email-arnd@arndb.de>
 <20120813185817.GA17342@pengutronix.de>
Message-ID: <CAOesGMjcSw1vUJ8nn4TakrRxEonryc=Oo-uhRxML=HwJpZQ8hQ@mail.gmail.com>

On Mon, Aug 13, 2012 at 11:58 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi Arnd,
>
> On Fri, Aug 10, 2012 at 09:06:12PM +0200, Arnd Bergmann wrote:
>> Hi Linus,
>>
>> Here are three pull requests for you to consider for the next -rc.
>
> How do you send multiple pull requests? Is there some git foo available
> or do you do this manually?

For truly trivial multi-branch pulls, I just generate each
individually. For the merge windows we tend to have several branches
touching the same files, so diffstats would be harder to compare that
way.

So, this is my workflow. I think Arnd's is quite similar since my
script is based on an early version of what I got from him:

* Start a dummy branch based on latest upstream version
* For each branch to pull:
  - Merge in the branch to make sure you document/resolve conflicts
  - Generate pull request email (save to file)
  - Push resolved branch (if you want to provide that)
* Edit the saved pull requests to modify the x/y fields
* Send them (with git send-mail --annotate for cover letter)


I have a script that generates the pull-request email in a format that
git send-email accepts (i.e. it has a From/Subject header). It's not
very pretty, but for reference I included a copy below.


#!/bin/sh

# Usage: my-request-pull <tagname>, run from a branch that is checked out
# with the branch you wish to request pulled merged in as the top commit.

echo "From: $(git config --get user.name) <$(git config --get user.email)>"
echo -n Subject: [GIT PULL x/y]\
git tag -n20 -l $1 | sed -e 's:^[-a-z0-9]* *::g'

echo
echo "----------------------------------------------------------------"
echo

SHA=$(git log --pretty=oneline -1 HEAD~ | cut -d' ' -f 1)
DESC=$(git log --pretty=oneline -1 HEAD~ | cut -d' ' -f 1 --complement)

echo "The following changes since commit $SHA:"
echo
echo "  $DESC"
echo
echo "are available in the git repository at:"
echo
echo "  git://EDIT_YOUR_URL_IN_HERE tags/$1"
echo

SHA=$(git log --pretty=oneline -1 $1 | cut -d' ' -f 1)
DESC=$(git log --pretty=oneline -1 $1 | cut -d' ' -f 1 --complement)

echo "for you to fetch changes up to $SHA:"
echo
echo "  $DESC"
echo
echo "----------------------------------------------------------------"
echo

git shortlog HEAD~..$1
echo
git diff -M --stat=75 --summary HEAD~ | cat


From m-karicheri2 at ti.com  Mon Aug 13 17:15:15 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Mon, 13 Aug 2012 21:15:15 +0000
Subject: [PATCH] arm:davinci: clk - migrate to new common clock API
In-Reply-To: <20120802212818.GJ29410@gmail.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
 <20120802212818.GJ29410@gmail.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041A056C@DFLE12.ent.ti.com>

>> -----Original Message-----
>> From: Turquette, Mike
>> Sent: Thursday, August 02, 2012 5:28 PM
>> To: Karicheri, Muralidharan
>> Cc: linux-arm-kernel at lists.infradead.org; davinci-linux-open-
>> source at linux.davincidsp.com; linux-keystone at list.ti.com - Linux developers for Keystone
>> family of devices (May contain non-TIers); Chemparathy, Cyril; Nori, Sekhar;
>> linux at arm.linux.org.uk
>> Subject: Re: [PATCH] arm:davinci: clk - migrate to new common clock API
>> 
>> On 20120802-12:53, Murali Karicheri wrote:
>> > As a first step towards migrating davinci platforms to use common clock
>> > framework, replace all instances of clk_enable() with clk_prepare_enable()
>> > and clk_disable() with clk_disable_unprepare(). Until the platform is
>> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> > adds a might_sleep() call and would work without any issues.
>> >
>> > This will make it easy later to switch to common clk based implementation
>> > of clk driver from DaVinci specific driver.
>> >
>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> 
>> Murali,
>> 
>> The patch $subject is a bit misleading.  This patch is preparation for
>> converting davinci over to the common clk framework.  How about:
>> 
>> arm: davinci: clk: call clk_prepare_enable
>> 

Ok

>> Also, the important thing to know about clk_prepare is that it might
>> sleep.  All of the functions below look like initialization functions
>> for code that is never run in interrupt context.  If you can confirm
>> that this is true then feel free to add my,
>> 

Will investigate and repost as appropriate.

Murali Karicheri
Software Design Engineer

>> Reviewed-by: Mike Turquette <mturquette at linaro.org>
>> 
>> Regards,
>> Mike
>> 
>> > ---
>> >  arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
>> >  arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
>> >  arch/arm/mach-davinci/board-dm365-evm.c     |    4 ++--
>> >  arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
>> >  arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
>> >  arch/arm/mach-davinci/devices-da8xx.c       |    6 +++---
>> >  arch/arm/mach-davinci/serial.c              |    2 +-
>> >  arch/arm/mach-davinci/time.c                |    4 ++--
>> >  8 files changed, 12 insertions(+), 12 deletions(-)
>> >
>> > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-
>> davinci/board-dm355-evm.c
>> > index 1c7b1f4..4821fba 100644
>> > --- a/arch/arm/mach-davinci/board-dm355-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm355-evm.c
>> > @@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
>> >  	if (IS_ERR(aemif))
>> >  		WARN("%s: unable to get AEMIF clock\n", __func__);
>> >  	else
>> > -		clk_enable(aemif);
>> > +		clk_prepare_enable(aemif);
>> >
>> >  	platform_add_devices(davinci_evm_devices,
>> >  			     ARRAY_SIZE(davinci_evm_devices));
>> > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-
>> davinci/board-dm355-leopard.c
>> > index 8e77032..b754ccf 100644
>> > --- a/arch/arm/mach-davinci/board-dm355-leopard.c
>> > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
>> > @@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
>> >  	if (IS_ERR(aemif))
>> >  		WARN("%s: unable to get AEMIF clock\n", __func__);
>> >  	else
>> > -		clk_enable(aemif);
>> > +		clk_prepare_enable(aemif);
>> >
>> >  	platform_add_devices(davinci_leopard_devices,
>> >  			     ARRAY_SIZE(davinci_leopard_devices));
>> > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-
>> davinci/board-dm365-evm.c
>> > index 2830692..3a4743b 100644
>> > --- a/arch/arm/mach-davinci/board-dm365-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm365-evm.c
>> > @@ -481,7 +481,7 @@ static void __init evm_init_cpld(void)
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> >  	if (IS_ERR(aemif_clk))
>> >  		return;
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
>> >  			"cpld") == NULL)
>> > @@ -492,7 +492,7 @@ static void __init evm_init_cpld(void)
>> >  				SECTION_SIZE);
>> >  fail:
>> >  		pr_err("ERROR: can't map CPLD\n");
>> > -		clk_disable(aemif_clk);
>> > +		clk_disable_unprepare(aemif_clk);
>> >  		return;
>> >  	}
>> >
>> > diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-
>> davinci/board-dm644x-evm.c
>> > index d34ed55..04ef708 100644
>> > --- a/arch/arm/mach-davinci/board-dm644x-evm.c
>> > +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
>> > @@ -775,7 +775,7 @@ static __init void davinci_evm_init(void)
>> >  	struct davinci_soc_info *soc_info = &davinci_soc_info;
>> >
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (HAS_ATA) {
>> >  		if (HAS_NAND || HAS_NOR)
>> > diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-
>> davinci/board-neuros-osd2.c
>> > index 5de69f2..7fdd0a7b 100644
>> > --- a/arch/arm/mach-davinci/board-neuros-osd2.c
>> > +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
>> > @@ -221,7 +221,7 @@ static __init void davinci_ntosd2_init(void)
>> >  	int	status;
>> >
>> >  	aemif_clk = clk_get(NULL, "aemif");
>> > -	clk_enable(aemif_clk);
>> > +	clk_prepare_enable(aemif_clk);
>> >
>> >  	if (HAS_ATA) {
>> >  		if (HAS_NAND)
>> > diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-
>> da8xx.c
>> > index d1624a3..20141f5 100644
>> > --- a/arch/arm/mach-davinci/devices-da8xx.c
>> > +++ b/arch/arm/mach-davinci/devices-da8xx.c
>> > @@ -905,7 +905,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>> *addr)
>> >  	if (IS_ERR(da850_sata_clk))
>> >  		return PTR_ERR(da850_sata_clk);
>> >
>> > -	ret = clk_enable(da850_sata_clk);
>> > +	ret = clk_prepare_enable(da850_sata_clk);
>> >  	if (ret)
>> >  		goto err0;
>> >
>> > @@ -936,7 +936,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>> *addr)
>> >  	return 0;
>> >
>> >  err1:
>> > -	clk_disable(da850_sata_clk);
>> > +	clk_disable_unprepare(da850_sata_clk);
>> >  err0:
>> >  	clk_put(da850_sata_clk);
>> >  	return ret;
>> > @@ -944,7 +944,7 @@ err0:
>> >
>> >  static void da850_sata_exit(struct device *dev)
>> >  {
>> > -	clk_disable(da850_sata_clk);
>> > +	clk_disable_unprepare(da850_sata_clk);
>> >  	clk_put(da850_sata_clk);
>> >  }
>> >
>> > diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
>> > index 1875740..24ddb0d 100644
>> > --- a/arch/arm/mach-davinci/serial.c
>> > +++ b/arch/arm/mach-davinci/serial.c
>> > @@ -95,7 +95,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
>> >  			continue;
>> >  		}
>> >
>> > -		clk_enable(uart_clk);
>> > +		clk_prepare_enable(uart_clk);
>> >  		p->uartclk = clk_get_rate(uart_clk);
>> >
>> >  		if (!p->membase && p->mapbase) {
>> > diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
>> > index 75da315..9847938 100644
>> > --- a/arch/arm/mach-davinci/time.c
>> > +++ b/arch/arm/mach-davinci/time.c
>> > @@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
>> >
>> >  	timer_clk = clk_get(NULL, "timer0");
>> >  	BUG_ON(IS_ERR(timer_clk));
>> > -	clk_enable(timer_clk);
>> > +	clk_prepare_enable(timer_clk);
>> >
>> >  	/* init timer hw */
>> >  	timer_init();
>> > @@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
>> >  	wd_clk = clk_get(&pdev->dev, NULL);
>> >  	if (WARN_ON(IS_ERR(wd_clk)))
>> >  		return;
>> > -	clk_enable(wd_clk);
>> > +	clk_prepare_enable(wd_clk);
>> >
>> >  	/* disable, internal clock source */
>> >  	__raw_writel(0, base + TCR);
>> > --
>> > 1.7.9.5
>> >


From matt at genesi-usa.com  Mon Aug 13 17:37:38 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 13 Aug 2012 16:37:38 -0500
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <201208131718.14546.marex@denx.de>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
 <201208131718.14546.marex@denx.de>
Message-ID: <CAKGA1bmYyvW6pWEbLGwRc-H2uWOF19nAt-de-WBqvhbOrGDqMA@mail.gmail.com>

On Mon, Aug 13, 2012 at 10:18 AM, Marek Vasut <marex at denx.de> wrote:
> Dear Shawn Guo,
>
>> On Thu, Jul 05, 2012 at 03:46:23PM +0800, Shawn Guo wrote:
>> > On Thu, Jul 05, 2012 at 09:13:18AM +0200, Sascha Hauer wrote:
>> > > Shawn,
>> > >
>> > > Is this ok with you?
>> >
>> > No.
>> >
>> > http://thread.gmane.org/gmane.linux.ports.arm.kernel/172558/focus=172703
>>
>> I change my mind.  Though it's really a pity to lose a concentrated
>> place maintaining a full list of compatible strings of all supported
>> board, I'm more concerned by the dt_board_compat matching efficiency
>> when the table gets longer.
>>
>> So, Fabio, can you please resend the patches against v3.6-rc?
>
> What about the board quirks that are present there?

They don't need to be done since they're usually driver-specific or
unit-specific; DTs should include these at the appropriate places. For
the MX51 Babbage entry all it did was set up all the iomux which is
now done via pinctrl and DT, so it can go. The rest, well, this is
more a quirk of the chip, and what should happen is, if it can be
moved to a bootloader, do it, and set up a quirk as a property in that
device like fsl,mc13xxx-uses-rtc - although in that particular example
I dare say that should be an rtc node under the pmic entry rather than
a property, at least for now it shows you can pick up a property that
changes the behavior of a device without it being in a mach-specific
file.

There may actually be some boards that need some specific, low-level
hacks to make work that will need entering but, for now, this doesn't
need to be. They can be removed and when those specific hacks appear,
their compatibles and new code to support the hacks can be added back
in.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From robherring2 at gmail.com  Mon Aug 13 17:38:45 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 16:38:45 -0500
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <20120813203300.GA8891@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <20120813203300.GA8891@avionic-0098.mockup.avionic-design.de>
Message-ID: <502973E5.6000303@gmail.com>

On 08/13/2012 03:33 PM, Thierry Reding wrote:
> On Mon, Aug 13, 2012 at 12:47:38PM -0600, Stephen Warren wrote:
>> On 08/13/2012 11:40 AM, Thierry Reding wrote:
>>> On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
>>>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
>>>>> This patch series adds support for device tree based probing of
>>>>> the PCIe controller found on Tegra SoCs.
>>>>
>>>> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
>>>> that PCIe doesn't work on TrimSlice when booting use device tree.
>>>> I think I found the cause, and I can't see why the same problem
>>>> doesn't affect this series. Perhaps you can enlighten me?
>> ...
>>>> PCI: Device 0000:01:00.0 not available because of resource
>>>> collisions
>> ...
>>> I've looked into this a bit, and it seems like ARM is using an
>>> open- coded version of the pci_enable_resources() function here,
>>> with the only difference being the unconditional enabling of both
>>> I/O and memory- mapped access for bridges. On Tegra there is
>>> already a PCI fixup to do this, so pci_enable_resources() can be
>>> used as-is. I came up with the attached patch but haven't been able
>>> to test it yet.
>>
>> Thanks very much for looking into this.
>>
>> The patch did alter the behavior a little for TrimSlice, but didn't
>> solve the problem. The old error messages:
>>
>>> [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
>>> [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
>>> [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22
>>
>> Were replaced with the following with your patch:
>>
>>> [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
>>> [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
>>> [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22
>>
>> This message appears from drivers/pci/setup-res.c pci_enable_resources()
>> due to:
>>
>>> 		if (!r->parent) {
>>> 			dev_err(&dev->dev, "device not available "
>>> 				"(can't reserve %pR)\n", r);
>>> 			return -EINVAL;
>>> 		}
> 
> Looking at the code some more, this may be caused by the pci_remap_io()
> patch series, so you might want to revert that patch and see if it fixes
> the I/O resources.
> 

Humm... But this patch deals with the i/o space and it is failing below
on the memory space.

>> That check doesn't appear in ARM's custom pcibios_enable_device().
>> Disabling that check yields:
>>
>>> [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
>>> [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>>> [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16
>>
>> I think that's because the pci_dev's resources are initially assigned
>> PCI-aperture-relative addresses, and then these are later patched up to
>> take account of where the aperture is mapped into the CPU's address space.
>>
>> Boot log using board files:
>>
>>> [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>> [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>> [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>> [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>> ...
>>> [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>> [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>> [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>> [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>> ... (I added some extra printks:)
>>> [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
>>> [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
>>> [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]
>>
>> whereas for a device tree boot:
>>
>> (same):
>>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>> ... (request region happens early)
>>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>> ... (same, just happens too late)
>>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>>
>> I suspect this is all still related to the PCI devices themselves being
>> probed much earlier in the overall PCI initialization sequence when the
>> PCI controller is probed later in the boot sequence, whereas PCI device
>> probe is deferred until the overall PCI initialization sequence is
>> complete if the PCI controller is probed very early in the boot sequence.
>>
>> Does anyone know where/what that "probe now" vs. "probe later" decision
>> point is? I'll try and track it down if nobody beats me to it.
> 
> There's the io_offset and mem_offset fields that I've completely ignored
> up to now. Can you try the patch below to see if it changes anything?
> I'm sorry but I can't test any of this myself right now.

Arnd and I discussed io_offset some. I don't think either of us can
figure out when it should be anything but 0 at least if pci i/o bus
addresses start at 0.

I don't think mem_offset is the issue. I think perhaps you need to set
pcibios_min_mem to the memory window base (0xa0000000), but that's just
a guess.

Rob

> 
> Thierry
> 
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 



From mturquette at ti.com  Mon Aug 13 17:44:24 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 13 Aug 2012 14:44:24 -0700
Subject: [linux-keystone] Re: [PATCH] arm:davinci: clk - migrate to new
 common clock API
In-Reply-To: <3E54258959B69E4282D79E01AB1F32B7041A0544@DFLE12.ent.ti.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
 <20120802212025.GI29410@gmail.com>
 <3E54258959B69E4282D79E01AB1F32B7041A0544@DFLE12.ent.ti.com>
Message-ID: <CAJOA=zN=koJ0C741skpJ1n0pH_BhR4V-7y4q0B6pBVNj_APO3Q@mail.gmail.com>

On Mon, Aug 13, 2012 at 2:13 PM, Karicheri, Muralidharan
<m-karicheri2 at ti.com> wrote:
>>> -----Original Message-----
>>> From: Turquette, Mike
>>> Sent: Thursday, August 02, 2012 5:20 PM
>>> To: Karicheri, Muralidharan
>>> Cc: linux-arm-kernel at lists.infradead.org; davinci-linux-open-
>>> source at linux.davincidsp.com; linux-keystone at list.ti.com - Linux developers for Keystone
>>> family of devices (May contain non-TIers); Chemparathy, Cyril; Nori, Sekhar;
>>> linux at arm.linux.org.uk
>>> Subject: [linux-keystone] Re: [PATCH] arm:davinci: clk - migrate to new common clock
>>> API
>>>
>>> On 20120802-12:53, Murali Karicheri wrote:
>>> > As a first step towards migrating davinci platforms to use common clock
>>> > framework, replace all instances of clk_enable() with clk_prepare_enable()
>>> > and clk_disable() with clk_disable_unprepare(). Until the platform is
>>> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>>> > adds a might_sleep() call and would work without any issues.
>>> >
>>> > This will make it easy later to switch to common clk based implementation
>>> > of clk driver from DaVinci specific driver.
>>> >
>>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>>>
>>> Murali,
>>>
>>> The important thing to know about clk_prepare is that it might sleep.
>>> All of the functions below look like initialization functions for code
>>> that is never run in interrupt context.  If you can confirm that this is
>>> true then feel free to add my,
>>>
>
> Mike,
>
> I believe they are. I will double check and then post the patch again. If they are called under
> interrupt context, basically I need to make two API calls instead as below right?
>
> clk_prepare()
> clk_enable()
>

This is correct.  You must insure that clk_prepare is called (and will
complete) before clk_enable is called.  clk_prepare must be run from
process context.  It is still OK to call clk_enable/clk_disable from
interrupt context as needed.

Regards,
Mike

> Murali Karicheri
> Software Design Engineer
>
>
>>> Reviewed-by: Mike Turquette <mturquette at linaro.org>
>>>
>>> Regards,
>>> Mike
>>>
>>> > ---
>>> >  arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
>>> >  arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
>>> >  arch/arm/mach-davinci/board-dm365-evm.c     |    4 ++--
>>> >  arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
>>> >  arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
>>> >  arch/arm/mach-davinci/devices-da8xx.c       |    6 +++---
>>> >  arch/arm/mach-davinci/serial.c              |    2 +-
>>> >  arch/arm/mach-davinci/time.c                |    4 ++--
>>> >  8 files changed, 12 insertions(+), 12 deletions(-)
>>> >
>>> > diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-
>>> davinci/board-dm355-evm.c
>>> > index 1c7b1f4..4821fba 100644
>>> > --- a/arch/arm/mach-davinci/board-dm355-evm.c
>>> > +++ b/arch/arm/mach-davinci/board-dm355-evm.c
>>> > @@ -324,7 +324,7 @@ static __init void dm355_evm_init(void)
>>> >    if (IS_ERR(aemif))
>>> >            WARN("%s: unable to get AEMIF clock\n", __func__);
>>> >    else
>>> > -          clk_enable(aemif);
>>> > +          clk_prepare_enable(aemif);
>>> >
>>> >    platform_add_devices(davinci_evm_devices,
>>> >                         ARRAY_SIZE(davinci_evm_devices));
>>> > diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-
>>> davinci/board-dm355-leopard.c
>>> > index 8e77032..b754ccf 100644
>>> > --- a/arch/arm/mach-davinci/board-dm355-leopard.c
>>> > +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
>>> > @@ -246,7 +246,7 @@ static __init void dm355_leopard_init(void)
>>> >    if (IS_ERR(aemif))
>>> >            WARN("%s: unable to get AEMIF clock\n", __func__);
>>> >    else
>>> > -          clk_enable(aemif);
>>> > +          clk_prepare_enable(aemif);
>>> >
>>> >    platform_add_devices(davinci_leopard_devices,
>>> >                         ARRAY_SIZE(davinci_leopard_devices));
>>> > diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-
>>> davinci/board-dm365-evm.c
>>> > index 2830692..3a4743b 100644
>>> > --- a/arch/arm/mach-davinci/board-dm365-evm.c
>>> > +++ b/arch/arm/mach-davinci/board-dm365-evm.c
>>> > @@ -481,7 +481,7 @@ static void __init evm_init_cpld(void)
>>> >    aemif_clk = clk_get(NULL, "aemif");
>>> >    if (IS_ERR(aemif_clk))
>>> >            return;
>>> > -  clk_enable(aemif_clk);
>>> > +  clk_prepare_enable(aemif_clk);
>>> >
>>> >    if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
>>> >                    "cpld") == NULL)
>>> > @@ -492,7 +492,7 @@ static void __init evm_init_cpld(void)
>>> >                            SECTION_SIZE);
>>> >  fail:
>>> >            pr_err("ERROR: can't map CPLD\n");
>>> > -          clk_disable(aemif_clk);
>>> > +          clk_disable_unprepare(aemif_clk);
>>> >            return;
>>> >    }
>>> >
>>> > diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-
>>> davinci/board-dm644x-evm.c
>>> > index d34ed55..04ef708 100644
>>> > --- a/arch/arm/mach-davinci/board-dm644x-evm.c
>>> > +++ b/arch/arm/mach-davinci/board-dm644x-evm.c
>>> > @@ -775,7 +775,7 @@ static __init void davinci_evm_init(void)
>>> >    struct davinci_soc_info *soc_info = &davinci_soc_info;
>>> >
>>> >    aemif_clk = clk_get(NULL, "aemif");
>>> > -  clk_enable(aemif_clk);
>>> > +  clk_prepare_enable(aemif_clk);
>>> >
>>> >    if (HAS_ATA) {
>>> >            if (HAS_NAND || HAS_NOR)
>>> > diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-
>>> davinci/board-neuros-osd2.c
>>> > index 5de69f2..7fdd0a7b 100644
>>> > --- a/arch/arm/mach-davinci/board-neuros-osd2.c
>>> > +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
>>> > @@ -221,7 +221,7 @@ static __init void davinci_ntosd2_init(void)
>>> >    int     status;
>>> >
>>> >    aemif_clk = clk_get(NULL, "aemif");
>>> > -  clk_enable(aemif_clk);
>>> > +  clk_prepare_enable(aemif_clk);
>>> >
>>> >    if (HAS_ATA) {
>>> >            if (HAS_NAND)
>>> > diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-
>>> da8xx.c
>>> > index d1624a3..20141f5 100644
>>> > --- a/arch/arm/mach-davinci/devices-da8xx.c
>>> > +++ b/arch/arm/mach-davinci/devices-da8xx.c
>>> > @@ -905,7 +905,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>>> *addr)
>>> >    if (IS_ERR(da850_sata_clk))
>>> >            return PTR_ERR(da850_sata_clk);
>>> >
>>> > -  ret = clk_enable(da850_sata_clk);
>>> > +  ret = clk_prepare_enable(da850_sata_clk);
>>> >    if (ret)
>>> >            goto err0;
>>> >
>>> > @@ -936,7 +936,7 @@ static int da850_sata_init(struct device *dev, void __iomem
>>> *addr)
>>> >    return 0;
>>> >
>>> >  err1:
>>> > -  clk_disable(da850_sata_clk);
>>> > +  clk_disable_unprepare(da850_sata_clk);
>>> >  err0:
>>> >    clk_put(da850_sata_clk);
>>> >    return ret;
>>> > @@ -944,7 +944,7 @@ err0:
>>> >
>>> >  static void da850_sata_exit(struct device *dev)
>>> >  {
>>> > -  clk_disable(da850_sata_clk);
>>> > +  clk_disable_unprepare(da850_sata_clk);
>>> >    clk_put(da850_sata_clk);
>>> >  }
>>> >
>>> > diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
>>> > index 1875740..24ddb0d 100644
>>> > --- a/arch/arm/mach-davinci/serial.c
>>> > +++ b/arch/arm/mach-davinci/serial.c
>>> > @@ -95,7 +95,7 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
>>> >                    continue;
>>> >            }
>>> >
>>> > -          clk_enable(uart_clk);
>>> > +          clk_prepare_enable(uart_clk);
>>> >            p->uartclk = clk_get_rate(uart_clk);
>>> >
>>> >            if (!p->membase && p->mapbase) {
>>> > diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
>>> > index 75da315..9847938 100644
>>> > --- a/arch/arm/mach-davinci/time.c
>>> > +++ b/arch/arm/mach-davinci/time.c
>>> > @@ -379,7 +379,7 @@ static void __init davinci_timer_init(void)
>>> >
>>> >    timer_clk = clk_get(NULL, "timer0");
>>> >    BUG_ON(IS_ERR(timer_clk));
>>> > -  clk_enable(timer_clk);
>>> > +  clk_prepare_enable(timer_clk);
>>> >
>>> >    /* init timer hw */
>>> >    timer_init();
>>> > @@ -429,7 +429,7 @@ void davinci_watchdog_reset(struct platform_device *pdev)
>>> >    wd_clk = clk_get(&pdev->dev, NULL);
>>> >    if (WARN_ON(IS_ERR(wd_clk)))
>>> >            return;
>>> > -  clk_enable(wd_clk);
>>> > +  clk_prepare_enable(wd_clk);
>>> >
>>> >    /* disable, internal clock source */
>>> >    __raw_writel(0, base + TCR);
>>> > --
>>> > 1.7.9.5
>>> >


From robherring2 at gmail.com  Mon Aug 13 17:48:11 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 16:48:11 -0500
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <20120813151509.GB27393@S2101-09.ap.freescale.net>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705071318.GO30009@pengutronix.de>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
Message-ID: <5029761B.9080502@gmail.com>

On 08/13/2012 10:15 AM, Shawn Guo wrote:
> On Thu, Jul 05, 2012 at 03:46:23PM +0800, Shawn Guo wrote:
>> On Thu, Jul 05, 2012 at 09:13:18AM +0200, Sascha Hauer wrote:
>>> Shawn,
>>>
>>> Is this ok with you?
>>>
>> No.
>>
>> http://thread.gmane.org/gmane.linux.ports.arm.kernel/172558/focus=172703
>>
> I change my mind.  Though it's really a pity to lose a concentrated
> place maintaining a full list of compatible strings of all supported
> board, I'm more concerned by the dt_board_compat matching efficiency
> when the table gets longer.
> 

I think this is needless churn. You can't say board entries are never
needed. Perhaps we've been overly active in adding all compatible
strings before they are needed. When you add a new board, it is fine to
match against the soc string without changing the kernel, but the dtb
should still have a more specific string. Then if you need to add
something board specific later, you can add the match entry and
corresponding board specific code.

Rob


From jdzheng at broadcom.com  Mon Aug 13 17:57:12 2012
From: jdzheng at broadcom.com (Jiandong Zheng)
Date: Mon, 13 Aug 2012 14:57:12 -0700
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-5-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
Message-ID: <50297838.7080208@broadcom.com>

On 8/10/2012 10:36 AM, Will Deacon wrote:
> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
>
> The arm_pmu_type enumeration was initially introduced to identify
> different PMU types in the system, the usual one being that on the CPU
> (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
> the introduction of devicetree bindings for the CPU PMU, the enumeration
> is no longer required.
>
> This patch removes the enumeration and updates the various CPU PMU
> platform devices so that they no longer pass an .id field referring
> to identify the PMU type.
>
> Cc: JD Zheng <jdzheng at broadcom.com>
> Cc: Jon Hunter <jon-hunter at ti.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Pawel Moll <pawel.moll at arm.com>
> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
> [will: cosmetic edits and actual removal of the enum type]
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>   arch/arm/include/asm/pmu.h               |   10 ----------
>   arch/arm/mach-bcmring/arch.c             |    3 +--
>   arch/arm/mach-omap2/devices.c            |    3 +--
>   arch/arm/mach-pxa/devices.c              |    3 +--
>   arch/arm/mach-realview/realview_eb.c     |    3 +--
>   arch/arm/mach-realview/realview_pb1176.c |    3 +--
>   arch/arm/mach-realview/realview_pb11mp.c |    3 +--
>   arch/arm/mach-realview/realview_pba8.c   |    3 +--
>   arch/arm/mach-realview/realview_pbx.c    |    3 +--
>   arch/arm/mach-tegra/devices.c            |    3 +--
>   arch/arm/mach-ux500/cpu-db8500.c         |    3 +--
>   arch/arm/mach-vexpress/ct-ca9x4.c        |    3 +--
>   arch/arm/plat-iop/pmu.c                  |    3 +--
>   arch/arm/plat-samsung/devs.c             |    3 +--
>   14 files changed, 13 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
> index 05e0401..fbec73a 100644
> --- a/arch/arm/include/asm/pmu.h
> +++ b/arch/arm/include/asm/pmu.h
> @@ -16,15 +16,6 @@
>   #include <linux/perf_event.h>
>   
>   /*
> - * Types of PMUs that can be accessed directly and require mutual
> - * exclusion between profiling tools.
> - */
> -enum arm_pmu_type {
> -	ARM_PMU_DEVICE_CPU	= 0,
> -	ARM_NUM_PMU_DEVICES,
> -};
> -
> -/*
>    * struct arm_pmu_platdata - ARM PMU platform data
>    *
>    * @handle_irq: an optional handler which will be called from the
> @@ -73,7 +64,6 @@ struct pmu_hw_events {
>   
>   struct arm_pmu {
>   	struct pmu	pmu;
> -	enum arm_pmu_type type;
>   	cpumask_t	active_irqs;
>   	char		*name;
>   	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
> diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
> index 45c97b1..76e7953 100644
> --- a/arch/arm/mach-bcmring/arch.c
> +++ b/arch/arm/mach-bcmring/arch.c
> @@ -29,7 +29,6 @@
>   #include <asm/setup.h>
>   #include <asm/mach-types.h>
>   #include <asm/mach/time.h>
> -#include <asm/pmu.h>
>   
>   #include <asm/mach/arch.h>
>   #include <mach/dma.h>
> @@ -116,7 +115,7 @@ static struct resource pmu_resource = {
>   
>   static struct platform_device pmu_device = {
>   	.name		= "arm-pmu",
> -	.id		= ARM_PMU_DEVICE_CPU,
> +	.id		= -1,
>   	.resource	= &pmu_resource,
>   	.num_resources	= 1,
>   };
>
Isn't it clearer to define a meaningful name for "-1", esp. if "-1" is 
being checked somewhere else?

Regards,
JD



From matt at genesi-usa.com  Mon Aug 13 18:05:52 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 13 Aug 2012 17:05:52 -0500
Subject: [PATCH] efikamx: reintroduce Genesi Efika MX Smarttop via device
 tree
In-Reply-To: <20120813173847.GH13446@opensource.wolfsonmicro.com>
References: <1344375978-29981-1-git-send-email-matt@genesi-usa.com>
 <20120809101947.GA8474@sirena.org.uk>
 <CAKGA1bkwMvDW7nMWxUbNm3_0ZTR2+uKs8UL_HuisJe7cd8POBA@mail.gmail.com>
 <20120813173847.GH13446@opensource.wolfsonmicro.com>
Message-ID: <CAKGA1b=ANojue-ZDxmocDhzTcQPuOVocs9yCjezhJrGqsOXEHA@mail.gmail.com>

On Mon, Aug 13, 2012 at 12:38 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Aug 13, 2012 at 10:42:58AM -0500, Matt Sealey wrote:
>> On Thu, Aug 9, 2012 at 5:19 AM, Mark Brown
>
>> > This and many of your other regulators have voltage ranges specified but
>> > no consumers which doesn't make sense.  It looks awfully like you've
>> > just typed in the maximum range supported by the regulator which is most
>> > likely broken.
>
>> Okay I have a question about this; some of the regulators (SW1
>> especially) are obviously consumed by the CPU core complex so that
>> when DVFS gives us a hint we can clock down and reduce voltage. How on
>> earth do we implement that?
>
>> We can drop the maximum range to be better for the CPU (1.3V is too
>> high, I think this is legacy from when we may have had a sorted 1GHz
>> MX51 coming out) but I can't find any source for where this is hooked
>> in.
>
> DVFS doesn't use the device model in Linux (yet!) so there's no device
> node and it's all a bit messy.  Shawn Guo is working on some generic DT
> bindings for it which should solve that problem but for now in the
> specific case of CPU bindings it's OK to not have an consumer, it's
> understandable what's going on there.

Going over the regulators, what I have so far is every regulator
properly specced with their fixed voltages where it never changes
(which is everything but SW1 and SW2).

There are still a lot of always-on and boot-on regulators since the
design is pretty poor - some pmic regulators that should have specific
consumers have been re-used in other places to supplement other
regulators or derive other voltages for parts of the board you would
usually have discrete logic to support. In this sense, a lot of the
board remains powered or it will just act weird, and a couple of very
specific ones can be turned on and off and don't need to be enabled
for the boot process, but they will be referenced by a metric f&%@ton
of devices as being a consumer so it's unlikely they'll ever actually
power down. In this case I found one always-on and boot-on that
actually doesn't need to be, but for the most part it stays as it is
with refined voltages.

I'm a little confused by the SW1 and SW2 ->VDDGP,VCC sourcing and what
that's actually supplying and what the voltage ranges SHOULD be - as I
think both need to be ranges. VDDGP should probably not be any more
flexible than 0.85V-1.1V.

That said, VCC seems to be only required to be a fixed 1.225V in the
datasheet? 0.9V to 1.85V seems excessive, but it's actually dependent
on load. I don't think anyone ever changes it, it was one of those
things your average board designer would sit down and say, this is
what it needs to be, and it might get bumped when it turns out
something on the board needs more power than the spec. I have NO idea
what this should be. I could just nail it to 1.225V and cover all
bases at the cost of possibly burning a ton of power. I'm looking into
what it's ACTUALLY running at in the old kernels.

It'll take some digging through the old Freescale code about where
they turn regulators on and off in the fixed board files to find this
out and what the original intent was. In the meantime I might be able
to refine the VDDGP/SW2 source. Shawn, any input? And does mainline
care about MX51 TO2 enough that we'd need to implement the voltage
bumps for that?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From sboyd at codeaurora.org  Mon Aug 13 18:09:56 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 13 Aug 2012 15:09:56 -0700
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>
Message-ID: <50297B34.5090504@codeaurora.org>

On 08/07/12 23:52, Magnus Damm wrote:
> So I finally managed to try this out on my KZM9D board. The SMP bring
> up code continues to work as expected, so it seems that SGI0 can be
> used instead of SGI1 on EMEV2. Let's just say that the boot protocol
> implemented by the mask ROM is rather poorly documented. Anyway, to
> test I used the following patch on top of linux git 42a579a.
>
> --- 0001/arch/arm/mach-shmobile/smp-emev2.c
> +++ work/arch/arm/mach-shmobile/smp-emev2.c	2012-08-08 15:42:54.000000000 +0900
> @@ -82,7 +82,7 @@ int __cpuinit emev2_boot_secondary(unsig
>  	/* Tell ROM loader about our vector (in headsmp.S) */
>  	emev2_set_boot_vector(__pa(shmobile_secondary_vector));
>
> -	gic_raise_softirq(cpumask_of(cpu), 1);
> +	gic_raise_softirq(cpumask_of(cpu), 0);
>  	return 0;
>  }
>
> So if/where needed, please add my:
>
> Acked-by: Magnus Damm <damm at opensource.se>
>

Thanks Magnus, would you be able to merge this through the shmobile
tree? Otherwise I can put it in the patch tracker.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From matt at genesi-usa.com  Mon Aug 13 18:28:17 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 13 Aug 2012 17:28:17 -0500
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
In-Reply-To: <20120813193517.GU1451@pengutronix.de>
References: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
 <20120813193517.GU1451@pengutronix.de>
Message-ID: <CAKGA1bnRA61JT8tQoHBay+6BSxDO5egiagQm1v05L7Asf+qJ+Q@mail.gmail.com>

 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /*
MX51_PAD_EIM_DA15__EIM_DA15 */



On Mon, Aug 13, 2012 at 2:35 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi Dave,
>
> On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:
>> Because FIQ handlers get copied straight into the vectors page to
>> the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
>> start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
>> Thumb-2.
>
> I finally came along testing this. I have no Thumb2 capable hardware
> to test if it works in thumb2 mode, but at least in Arm mode it works.
> This is enough to not introduce a regression, so we can go for this.

This is the interesting dichotomy; the code is only required truly on
devices where Thumb2 isn't available, right?

What we're after here is a build fix more than anything due to an
overzealous, over-inclusive configuration that can't be easily split.
If the ARM code works on the devices it's intended for, excellent. We
can fix the weird inclusions of the code later (and maybe if we're
splitting v6_v7 into just v6 and v7 configs for some other reason, and
all the users go away, maybe we should bump v7 to default to Thumb2?
:)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From robherring2 at gmail.com  Mon Aug 13 18:35:45 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 17:35:45 -0500
Subject: [RFC PATCH] ARM: add coherent dma ops
In-Reply-To: <007b01cd791b$07adc900$17095b00$%szyprowski@samsung.com>
References: <1344490622-20029-1-git-send-email-robherring2@gmail.com>
 <007b01cd791b$07adc900$17095b00$%szyprowski@samsung.com>
Message-ID: <50298141.2090606@gmail.com>

On 08/13/2012 01:15 AM, Marek Szyprowski wrote:
> Hi Rob,
> 
> On Thursday, August 09, 2012 7:37 AM Rob Herring wrote:
> 
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> arch_is_coherent is problematic as it is a global symbol. This
>> doesn't work for multi-platform kernels or platforms which can support
>> per device coherent DMA.
>>
>> This adds arm_coherent_dma_ops to be used for devices which connected
>> coherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops
>> are modified at boot when arch_is_coherent is true.
> 
> Thanks for the patch. I had something similar on my TODO list, but had not enough time for
> it. I like this patch but I have some comments.
>  
>> This does not address arch_is_coherent used in iommu dma ops.
> 
> In the initial version we might get rid of arch_is_coherent() usage in iommu dma ops and
> implement it when a real coherent hw with iommu will be available.

Well, if you are fine with the overall approach, then I can update iommu
functions too.


>> +static int __init dma_map_init(void)
>> +{
>> +	if (!arch_is_coherent())
>> +		return 0;
>> +
>> +	arm_dma_ops.map_page = arm_coherent_dma_map_page;
>> +	arm_dma_ops.unmap_page = NULL;
>> +	arm_dma_ops.map_sg = NULL;
>> +	arm_dma_ops.unmap_sg = NULL;
>> +	arm_dma_ops.sync_single_for_cpu = NULL;
>> +	arm_dma_ops.sync_single_for_device = NULL;
>> +	arm_dma_ops.sync_sg_for_cpu = NULL;
>> +	arm_dma_ops.sync_sg_for_device = NULL;
>> +	arm_dma_ops.alloc = arm_coherent_dma_alloc;
>> +	arm_dma_ops.free = arm_coherent_dma_free;
>> +}
>> +core_initcall(dma_map_init);
> 
> I would implement it in a bit different way. Overwriting structure entries is not the 
> cleanest approach and might lead to some misunderstandings. I would rather change 
> get_dma_ops() function in arch/arm/include/asm/dma-mapping.h to something like this:
> 
> static inline struct dma_map_ops *get_dma_ops(struct device *dev)
> {
>         if (dev && dev->archdata.dma_ops)
>                 return dev->archdata.dma_ops;
>         return !arch_is_coherent() ? &arm_dma_ops : &arm_coherent_dma_ops;
> }
> 
> This way the code is easy to understand and compiler can easily optimize out the above 
> check for 99% of architectures which are either coherent or not. In case of partially 
> coherent architectures, arch_is_coherent() will probably return false and coherent 
> devices will get their dma_map_ops initialized by platform code.

Yes, that's much better.

Rob


From bhelgaas at google.com  Mon Aug 13 19:18:16 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Mon, 13 Aug 2012 16:18:16 -0700
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <50294BCA.1070807@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
Message-ID: <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>

On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/13/2012 11:40 AM, Thierry Reding wrote:
>> On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
>>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
>>>> This patch series adds support for device tree based probing of
>>>> the PCIe controller found on Tegra SoCs.
>>>
>>> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
>>> that PCIe doesn't work on TrimSlice when booting use device tree.
>>> I think I found the cause, and I can't see why the same problem
>>> doesn't affect this series. Perhaps you can enlighten me?
> ...
>>> PCI: Device 0000:01:00.0 not available because of resource
>>> collisions
> ...
>> I've looked into this a bit, and it seems like ARM is using an
>> open- coded version of the pci_enable_resources() function here,
>> with the only difference being the unconditional enabling of both
>> I/O and memory- mapped access for bridges. On Tegra there is
>> already a PCI fixup to do this, so pci_enable_resources() can be
>> used as-is.

I'd prefer that bridge I/O & memory access enabling be done in a
mainline path, not in a fixup.  Fixups are intended for working around
defects in specific devices, not for the normal path.  I know various
architectures have fixups that are used in the normal path, but I've
been working on eliminating them.

> The patch did alter the behavior a little for TrimSlice, but didn't
> solve the problem. The old error messages:
>
>> [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
>> [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
>> [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22
>
> Were replaced with the following with your patch:
>
>> [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
>> [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
>> [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22
>
> This message appears from drivers/pci/setup-res.c pci_enable_resources()
> due to:
>
>>               if (!r->parent) {
>>                       dev_err(&dev->dev, "device not available "
>>                               "(can't reserve %pR)\n", r);
>>                       return -EINVAL;
>>               }
>
> That check doesn't appear in ARM's custom pcibios_enable_device().
> Disabling that check yields:
>
>> [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
>> [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>> [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>> [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16
>
> I think that's because the pci_dev's resources are initially assigned
> PCI-aperture-relative addresses, and then these are later patched up to
> take account of where the aperture is mapped into the CPU's address space.

We definitely shouldn't be calling the driver probe routine before the
device BARs are assigned.

> Boot log using board files:
>
>> [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>> [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>> [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>> [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> ...
>> [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>> [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>> [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>> [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> ... (I added some extra printks:)
>> [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
>> [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
>> [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]
>
> whereas for a device tree boot:
>
> (same):
>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> ... (request region happens early)
>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> ... (same, just happens too late)
>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>
> I suspect this is all still related to the PCI devices themselves being
> probed much earlier in the overall PCI initialization sequence when the
> PCI controller is probed later in the boot sequence, whereas PCI device
> probe is deferred until the overall PCI initialization sequence is
> complete if the PCI controller is probed very early in the boot sequence.

I don't know what to apply your patches to (they don't apply cleanly
to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
like you might be calling pci_bus_add_devices() before
pci_bus_assign_resource(), which isn't going to work.

I don't know what it means to probe PCI devices before probing the PCI
controller (the host bridge) -- that shouldn't happen either.  In
order to probe PCI devices, we have to first know about the host
bridge so we know how to do config accesses and what the bridge
apertures are.


From shawn.guo at linaro.org  Mon Aug 13 21:26:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 09:26:51 +0800
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <5029761B.9080502@gmail.com>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705071318.GO30009@pengutronix.de>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
 <5029761B.9080502@gmail.com>
Message-ID: <20120814012649.GA27792@S2101-09.ap.freescale.net>

On Mon, Aug 13, 2012 at 04:48:11PM -0500, Rob Herring wrote:
> I think this is needless churn. You can't say board entries are never
> needed. Perhaps we've been overly active in adding all compatible
> strings before they are needed. When you add a new board, it is fine to
> match against the soc string without changing the kernel, but the dtb
> should still have a more specific string. Then if you need to add
> something board specific later, you can add the match entry and
> corresponding board specific code.
> 
I probably haven't made myself clear.  What I'm asking for is merely
removing the board compatible string from dt_board_compat, not from
dtb.  Every single board will still have its specific compatible string
defined in its dts.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Mon Aug 13 21:28:08 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 09:28:08 +0800
Subject: [PATCH 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
In-Reply-To: <CAOMZO5C4f11jyvk_5sHAfwUKmybmgX91de3Mv+jaEmTuSMGpnA@mail.gmail.com>
References: <1339941856-2836-1-git-send-email-festevam@gmail.com>
 <20120705071318.GO30009@pengutronix.de>
 <20120705074623.GG10610@S2101-09.ap.freescale.net>
 <20120813151509.GB27393@S2101-09.ap.freescale.net>
 <CAOMZO5C4f11jyvk_5sHAfwUKmybmgX91de3Mv+jaEmTuSMGpnA@mail.gmail.com>
Message-ID: <20120814012806.GB27792@S2101-09.ap.freescale.net>

On Mon, Aug 13, 2012 at 01:56:40PM -0300, Fabio Estevam wrote:
> On Mon, Aug 13, 2012 at 12:15 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > So, Fabio, can you please resend the patches against v3.6-rc?
> 
> Which branch at git.linaro.org should I use it to rebase?
> 
Just against mainline v3.6-rc.

-- 
Regards,
Shawn



From shawn.guo at linaro.org  Mon Aug 13 21:35:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 09:35:19 +0800
Subject: [PATCH v2 1/2] ARM: i.MX35: Add kernel oftree support
In-Reply-To: <20120813153503.GC2232@pengutronix.de>
References: <1344591170-13638-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120813081518.GA27480@S2101-09.ap.freescale.net>
 <20120813153503.GC2232@pengutronix.de>
Message-ID: <20120814013517.GC27792@S2101-09.ap.freescale.net>

On Mon, Aug 13, 2012 at 05:35:03PM +0200, Uwe Kleine-K?nig wrote:
> Hi Shawn,
> 
> On Mon, Aug 13, 2012 at 04:15:21PM +0800, Shawn Guo wrote:
> > On Fri, Aug 10, 2012 at 11:32:49AM +0200, Uwe Kleine-K?nig wrote:
> > > +		emi at 80000000 { /* External Memory Interface */
> > > +			compatible = "fsl,emi", "simple-bus";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0x80000000 0x40000000>;
> > > +			ranges;
> > > +
> > > +			nand at bb000000 {
> > > +				#address-cells = <1>;
> > > +				#size-cells = <1>;
> > > +
> > These should not be needed, until you will have sub-nodes with "reg"
> > property.
> 
> The obvious sub-nodes are partitions. I thought it sensible to already
> add #address-cells and #size-cells because they are identical for all
> users and so repeating is minimized.
> 
Yes, you are right.  How did I forget such an obvious use case?

-- 
Regards,
Shawn



From jason77.wang at gmail.com  Mon Aug 13 21:46:04 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Tue, 14 Aug 2012 09:46:04 +0800
Subject: [PATCH 0/9] ARM perf updates for 3.7
In-Reply-To: <20120813093201.GB19113@mudshark.cambridge.arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <5028C4C9.6020002@gmail.com>
 <20120813093201.GB19113@mudshark.cambridge.arm.com>
Message-ID: <5029ADDC.10908@gmail.com>

Will Deacon wrote:
> On Mon, Aug 13, 2012 at 10:11:37AM +0100, Hui Wang wrote:
>   
>> Hi Will Deacon,
>>     
>
> Hello,
>
>   
>> For SMP platforms, each CPU core has an independent PMU, and each PMU 
>> has a dedicated irq (SPI or PPI). Current perf subsystem framework only 
>> supports each PMU to have a dedicated SPI irq, and it will support each 
>> PMU to have a PPI irq (i have seen someone has sent out the patches), 
>> but there is a situation the subsystem doesn't support yet, the 
>> situation is multi PMUs share one same SPI irq, e.g. the i.MX6Quad CPU 
>> has 4 cortex-a9 cores, each core has a PMU, all PMU irqs are routed 
>> (ORed) to one SPI irq, do you know how to support this situation?
>>     
>
> That's what I like to call a braindead, broken system. Seriously, CPU PMU
> interrupts *can only* be handled on the CPU which raised them -- ORing these
> things together means ping-ponging the interrupt affinity around until we
> find the right guy. There's also the fun case where multiple PMUs assert
> simultaneously and I've even heard about platforms where they OR in the
> bloody L2 PMU interrupt as well for good measure!
>
> If you have to support such a device, take a look at the ux500 code
> (db8500_pmu_handler), but please take all of your profiling numbers with a
> pinch of salt. For a quad-core processor, the numbers will probably be even
> less accurate.
>
> Also, please go ahead and inflict sufficient injuries to your hardware guys
> that they stop this madness!
>   
Got it, thanks for the information, it is very useful.

Regards,
Hui.


> Will
>
>   



From plagnioj at jcrosoft.com  Mon Aug 13 22:28:30 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 Aug 2012 04:28:30 +0200
Subject: [PATCH] ARM: at91: fix drivers broken because of sparse irq
 support
In-Reply-To: <1344872334-1532-2-git-send-email-ludovic.desroches@atmel.com>
References: <1344872334-1532-1-git-send-email-ludovic.desroches@atmel.com>
 <1344872334-1532-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120814022830.GB8836@game.jcrosoft.org>

On 17:38 Mon 13 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Some drivers directly use AT91_ID_SYS as virq so they are broken because of
> the NR_IRQS_LEGACY virq offset introduced with sparse irq support.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: stable at vger.kernel.org
> ---
>  arch/arm/mach-at91/at91rm9200_time.c |  2 +-
>  drivers/rtc/rtc-at91sam9.c           | 11 ++++++-----
>  2 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index 104ca40..aaa443b 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
>  	at91_st_read(AT91_ST_SR);
>  
>  	/* Make IRQs happen for the system timer */
> -	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
> +	setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
>  
>  	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
>  	 * directly for the clocksource and all clockevents, after adjusting
> diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
> index 8318689..2969047 100644
> --- a/drivers/rtc/rtc-at91sam9.c
> +++ b/drivers/rtc/rtc-at91sam9.c
> @@ -345,11 +345,12 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
>  	}
>  
>  	/* register irq handler after we know what name we'll use */
> -	ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
> +	ret = request_irq(NR_IRQS_LEGACY + AT91_ID_SYS, at91_rtc_interrupt,
the irq need to be pass by resources and not hardcoded

Best Regrds,
J.


From plagnioj at jcrosoft.com  Mon Aug 13 22:37:58 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 Aug 2012 04:37:58 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <CACQ1gAjPGcnOGh9iMxKUH1FA6rHBcuOzgR_A+wkbFWYkazQPxw@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjPGcnOGh9iMxKUH1FA6rHBcuOzgR_A+wkbFWYkazQPxw@mail.gmail.com>
Message-ID: <20120814023758.GC8836@game.jcrosoft.org>

> > +
> > +dbgu: serial at fffff200 {
> > +       compatible = "atmel,at91sam9260-usart";
> > +       reg = <0xfffff200 0x200>;
> > +       interrupts = <1 4 7>;
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_dbgu>;
> > +       status = "disabled";
> > +};
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index e91c7cd..178a619 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -352,6 +352,7 @@ config ARCH_AT91
> >         select CLKDEV_LOOKUP
> >         select IRQ_DOMAIN
> >         select NEED_MACH_IO_H if PCCARD
> > +       select PINCTRL
> >         help
> >           This enables support for systems based on Atmel
> >           AT91RM9200 and AT91SAM9* processors.
> There's a problem with this: if CONFIG_PINCRTL is forced on ARCH_AT91
> and PINCTRL_AT91 is not selected,
> all calls to devm_pinctrl_get_select_default() will fail. => no
> serial, no nand etc..
> IMHO, CONFIG_PINCTRL should not be forced, otherwise it will break
> configs that don't want pinctrl
> Or, if pinctrl is the new and only way, PINCTRL_AT91 should also be
> forced on ARCH_AT91
no pinctrl MUST be forced as we provide pinctrl dummies
which will provide dummy config so not break

and if you want the gpio you need to enable the pinctrl on at91 otherwise you
not have it we can force PINCRTL_AT91 on DT but now the pinctrl need to always
be enabled
> > --
> > 1.7.10.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 
> I tested it with a at91sam9g35-ek board, and it hangs before the dbgu
> line is configured.
> ( with at91_dt_defconfig and at91sam9g35ek.dts )
did you update you dtb before booting?

Best Regards,
J.


From robherring2 at gmail.com  Mon Aug 13 23:49:03 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 22:49:03 -0500
Subject: [PATCH 0/4] Per device coherent DMA map ops
Message-ID: <1344916147-13546-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This is series adds coherent DMA map operations which can be set per device.
Expanding on the first RFC[1], this version adds iommu ops and implements
support on highbank platform.

arch_is_coherent is never defined true since removing ixp2xxx, so we can 
remove it altogether.

Rob

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/113921.html

Rob Herring (4):
  ARM: add coherent dma ops
  ARM: add coherent iommu dma ops
  ARM: kill off arch_is_coherent
  ARM: highbank: add coherent DMA setup

 .../devicetree/bindings/ata/ahci-platform.txt      |    3 +
 .../devicetree/bindings/dma/arm-pl330.txt          |    3 +
 .../devicetree/bindings/net/calxeda-xgmac.txt      |    3 +
 arch/arm/boot/dts/highbank.dts                     |    1 +
 arch/arm/include/asm/barrier.h                     |    7 +-
 arch/arm/include/asm/dma-mapping.h                 |    1 +
 arch/arm/include/asm/memory.h                      |    8 -
 arch/arm/mach-highbank/highbank.c                  |   52 ++++
 arch/arm/mm/dma-mapping.c                          |  254 ++++++++++++++++----
 arch/arm/mm/mmu.c                                  |   17 +-
 10 files changed, 271 insertions(+), 78 deletions(-)

-- 
1.7.9.5



From robherring2 at gmail.com  Mon Aug 13 23:49:04 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 22:49:04 -0500
Subject: [PATCH 1/4] ARM: add coherent dma ops
In-Reply-To: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344916147-13546-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

arch_is_coherent is problematic as it is a global symbol. This
doesn't work for multi-platform kernels or platforms which can support
per device coherent DMA.

This adds arm_coherent_dma_ops to be used for devices which connected
coherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops
are modified at boot when arch_is_coherent is true.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/include/asm/dma-mapping.h |    1 +
 arch/arm/mm/dma-mapping.c          |   71 ++++++++++++++++++++++++++++++------
 2 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 2ae842d..c27d855 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -13,6 +13,7 @@
 
 #define DMA_ERROR_CODE	(~0)
 extern struct dma_map_ops arm_dma_ops;
+extern struct dma_map_ops arm_coherent_dma_ops;
 
 static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 {
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c2cdf65..c14e37e 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -73,11 +73,18 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
 	     unsigned long offset, size_t size, enum dma_data_direction dir,
 	     struct dma_attrs *attrs)
 {
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_cpu_to_dev(page, offset, size, dir);
 	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
 }
 
+static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
+	     unsigned long offset, size_t size, enum dma_data_direction dir,
+	     struct dma_attrs *attrs)
+{
+	return pfn_to_dma(dev, page_to_pfn(page)) + offset;
+}
+
 /**
  * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -96,7 +103,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
 		size_t size, enum dma_data_direction dir,
 		struct dma_attrs *attrs)
 {
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
 				      handle & ~PAGE_MASK, size, dir);
 }
@@ -106,8 +113,7 @@ static void arm_dma_sync_single_for_cpu(struct device *dev,
 {
 	unsigned int offset = handle & (PAGE_SIZE - 1);
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-	if (!arch_is_coherent())
-		__dma_page_dev_to_cpu(page, offset, size, dir);
+	__dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
 static void arm_dma_sync_single_for_device(struct device *dev,
@@ -115,8 +121,7 @@ static void arm_dma_sync_single_for_device(struct device *dev,
 {
 	unsigned int offset = handle & (PAGE_SIZE - 1);
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
-	if (!arch_is_coherent())
-		__dma_page_cpu_to_dev(page, offset, size, dir);
+	__dma_page_cpu_to_dev(page, offset, size, dir);
 }
 
 static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
@@ -138,6 +143,22 @@ struct dma_map_ops arm_dma_ops = {
 };
 EXPORT_SYMBOL(arm_dma_ops);
 
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+				  dma_addr_t handle, struct dma_attrs *attrs);
+
+struct dma_map_ops arm_coherent_dma_ops = {
+	.alloc			= arm_coherent_dma_alloc,
+	.free			= arm_coherent_dma_free,
+	.mmap			= arm_dma_mmap,
+	.get_sgtable		= arm_dma_get_sgtable,
+	.map_page		= arm_coherent_dma_map_page,
+	.map_sg			= arm_dma_map_sg,
+	.set_dma_mask		= arm_dma_set_mask,
+};
+EXPORT_SYMBOL(arm_coherent_dma_ops);
+
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = (u64)arm_dma_limit;
@@ -538,7 +559,7 @@ static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
 
 
 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
-			 gfp_t gfp, pgprot_t prot, const void *caller)
+			 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
 {
 	u64 mask = get_coherent_dma_mask(dev);
 	struct page *page;
@@ -571,7 +592,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 	*handle = DMA_ERROR_CODE;
 	size = PAGE_ALIGN(size);
 
-	if (arch_is_coherent() || nommu())
+	if (is_coherent || nommu())
 		addr = __alloc_simple_buffer(dev, size, gfp, &page);
 	else if (gfp & GFP_ATOMIC)
 		addr = __alloc_from_pool(size, &page);
@@ -599,7 +620,20 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 	if (dma_alloc_from_coherent(dev, size, handle, &memory))
 		return memory;
 
-	return __dma_alloc(dev, size, handle, gfp, prot,
+	return __dma_alloc(dev, size, handle, gfp, prot, false,
+			   __builtin_return_address(0));
+}
+
+static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
+	dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
+{
+	pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
+	void *memory;
+
+	if (dma_alloc_from_coherent(dev, size, handle, &memory))
+		return memory;
+
+	return __dma_alloc(dev, size, handle, gfp, prot, true,
 			   __builtin_return_address(0));
 }
 
@@ -636,8 +670,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 /*
  * Free a buffer as defined by the above mapping.
  */
-void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
-		  dma_addr_t handle, struct dma_attrs *attrs)
+static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+			   dma_addr_t handle, struct dma_attrs *attrs,
+			   bool is_coherent)
 {
 	struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
 
@@ -646,7 +681,7 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 
 	size = PAGE_ALIGN(size);
 
-	if (arch_is_coherent() || nommu()) {
+	if (is_coherent || nommu()) {
 		__dma_free_buffer(page, size);
 	} else if (!IS_ENABLED(CONFIG_CMA)) {
 		__dma_free_remap(cpu_addr, size);
@@ -662,6 +697,18 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 	}
 }
 
+void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
+		  dma_addr_t handle, struct dma_attrs *attrs)
+{
+	__arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
+}
+
+static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
+				  dma_addr_t handle, struct dma_attrs *attrs)
+{
+	__arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
+}
+
 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
 		 void *cpu_addr, dma_addr_t handle, size_t size,
 		 struct dma_attrs *attrs)
-- 
1.7.9.5



From robherring2 at gmail.com  Mon Aug 13 23:49:05 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 22:49:05 -0500
Subject: [PATCH 2/4] ARM: add coherent iommu dma ops
In-Reply-To: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344916147-13546-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Remove arch_is_coherent() from iommu dma ops and implement separate
coherent ops functions.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mm/dma-mapping.c |  183 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 143 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c14e37e..29c3b3a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1254,7 +1254,8 @@ static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
  */
 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
 			  size_t size, dma_addr_t *handle,
-			  enum dma_data_direction dir, struct dma_attrs *attrs)
+			  enum dma_data_direction dir, struct dma_attrs *attrs,
+			  bool is_coherent)
 {
 	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
 	dma_addr_t iova, iova_base;
@@ -1273,8 +1274,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
 		phys_addr_t phys = page_to_phys(sg_page(s));
 		unsigned int len = PAGE_ALIGN(s->offset + s->length);
 
-		if (!arch_is_coherent() &&
-		    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+		if (!is_coherent &&
+			!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 			__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 
 		ret = iommu_map(mapping->domain, iova, phys, len, 0);
@@ -1292,20 +1293,9 @@ fail:
 	return ret;
 }
 
-/**
- * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
- * @dev: valid struct device pointer
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Map a set of buffers described by scatterlist in streaming mode for DMA.
- * The scatter gather list elements are merged together (if possible) and
- * tagged with the appropriate dma address and length. They are obtained via
- * sg_dma_{address,length}.
- */
-int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-		     enum dma_data_direction dir, struct dma_attrs *attrs)
+static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+		     enum dma_data_direction dir, struct dma_attrs *attrs,
+		     bool is_coherent)
 {
 	struct scatterlist *s = sg, *dma = sg, *start = sg;
 	int i, count = 0;
@@ -1321,7 +1311,7 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 
 		if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
 			if (__map_sg_chunk(dev, start, size, &dma->dma_address,
-			    dir, attrs) < 0)
+			    dir, attrs, is_coherent) < 0)
 				goto bad_mapping;
 
 			dma->dma_address += offset;
@@ -1334,7 +1324,8 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 		}
 		size += s->length;
 	}
-	if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0)
+	if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
+		is_coherent) < 0)
 		goto bad_mapping;
 
 	dma->dma_address += offset;
@@ -1349,17 +1340,44 @@ bad_mapping:
 }
 
 /**
- * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  * @dev: valid struct device pointer
  * @sg: list of buffers
- * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
- * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
  *
- * Unmap a set of streaming mode DMA translations.  Again, CPU access
- * rules concerning calls here are the same as for dma_unmap_single().
+ * Map a set of i/o coherent buffers described by scatterlist in streaming
+ * mode for DMA. The scatter gather list elements are merged together (if
+ * possible) and tagged with the appropriate dma address and length. They are
+ * obtained via sg_dma_{address,length}.
  */
-void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
-			enum dma_data_direction dir, struct dma_attrs *attrs)
+int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+		int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+	return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
+}
+
+/**
+ * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Map a set of buffers described by scatterlist in streaming mode for DMA.
+ * The scatter gather list elements are merged together (if possible) and
+ * tagged with the appropriate dma address and length. They are obtained via
+ * sg_dma_{address,length}.
+ */
+int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+		int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+	return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
+}
+
+static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+		int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
+		bool is_coherent)
 {
 	struct scatterlist *s;
 	int i;
@@ -1368,7 +1386,7 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 		if (sg_dma_len(s))
 			__iommu_remove_mapping(dev, sg_dma_address(s),
 					       sg_dma_len(s));
-		if (!arch_is_coherent() &&
+		if (!is_coherent &&
 		    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 			__dma_page_dev_to_cpu(sg_page(s), s->offset,
 					      s->length, dir);
@@ -1376,6 +1394,38 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 }
 
 /**
+ * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
+		int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+	__iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
+}
+
+/**
+ * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+			enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+	__iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
+}
+
+/**
  * arm_iommu_sync_sg_for_cpu
  * @dev: valid struct device pointer
  * @sg: list of buffers
@@ -1389,8 +1439,7 @@ void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 	int i;
 
 	for_each_sg(sg, s, nents, i)
-		if (!arch_is_coherent())
-			__dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
+		__dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
 
 }
 
@@ -1408,22 +1457,21 @@ void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 	int i;
 
 	for_each_sg(sg, s, nents, i)
-		if (!arch_is_coherent())
-			__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
+		__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 }
 
 
 /**
- * arm_iommu_map_page
+ * arm_coherent_iommu_map_page
  * @dev: valid struct device pointer
  * @page: page that buffer resides in
  * @offset: offset into page for start of buffer
  * @size: size of buffer to map
  * @dir: DMA transfer direction
  *
- * IOMMU aware version of arm_dma_map_page()
+ * Coherent IOMMU aware version of arm_dma_map_page()
  */
-static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
 	     unsigned long offset, size_t size, enum dma_data_direction dir,
 	     struct dma_attrs *attrs)
 {
@@ -1431,9 +1479,6 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
 	dma_addr_t dma_addr;
 	int ret, len = PAGE_ALIGN(size + offset);
 
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
-		__dma_page_cpu_to_dev(page, offset, size, dir);
-
 	dma_addr = __alloc_iova(mapping, len);
 	if (dma_addr == DMA_ERROR_CODE)
 		return dma_addr;
@@ -1449,6 +1494,52 @@ fail:
 }
 
 /**
+ * arm_iommu_map_page
+ * @dev: valid struct device pointer
+ * @page: page that buffer resides in
+ * @offset: offset into page for start of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * IOMMU aware version of arm_dma_map_page()
+ */
+static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
+	     unsigned long offset, size_t size, enum dma_data_direction dir,
+	     struct dma_attrs *attrs)
+{
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+		__dma_page_cpu_to_dev(page, offset, size, dir);
+
+	return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
+}
+
+/**
+ * arm_coherent_iommu_unmap_page
+ * @dev: valid struct device pointer
+ * @handle: DMA address of buffer
+ * @size: size of buffer (same as passed to dma_map_page)
+ * @dir: DMA transfer direction (same as passed to dma_map_page)
+ *
+ * Coherent IOMMU aware version of arm_dma_unmap_page()
+ */
+static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
+		size_t size, enum dma_data_direction dir,
+		struct dma_attrs *attrs)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+	dma_addr_t iova = handle & PAGE_MASK;
+	struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
+	int offset = handle & ~PAGE_MASK;
+	int len = PAGE_ALIGN(size + offset);
+
+	if (!iova)
+		return;
+
+	iommu_unmap(mapping->domain, iova, len);
+	__free_iova(mapping, iova, len);
+}
+
+/**
  * arm_iommu_unmap_page
  * @dev: valid struct device pointer
  * @handle: DMA address of buffer
@@ -1470,7 +1561,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 	if (!iova)
 		return;
 
-	if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_dev_to_cpu(page, offset, size, dir);
 
 	iommu_unmap(mapping->domain, iova, len);
@@ -1488,8 +1579,7 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
 	if (!iova)
 		return;
 
-	if (!arch_is_coherent())
-		__dma_page_dev_to_cpu(page, offset, size, dir);
+	__dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
 static void arm_iommu_sync_single_for_device(struct device *dev,
@@ -1523,6 +1613,19 @@ struct dma_map_ops iommu_ops = {
 	.sync_sg_for_device	= arm_iommu_sync_sg_for_device,
 };
 
+struct dma_map_ops iommu_coherent_ops = {
+	.alloc		= arm_iommu_alloc_attrs,
+	.free		= arm_iommu_free_attrs,
+	.mmap		= arm_iommu_mmap_attrs,
+	.get_sgtable	= arm_iommu_get_sgtable,
+
+	.map_page	= arm_coherent_iommu_map_page,
+	.unmap_page	= arm_coherent_iommu_unmap_page,
+
+	.map_sg		= arm_coherent_iommu_map_sg,
+	.unmap_sg	= arm_coherent_iommu_unmap_sg,
+};
+
 /**
  * arm_iommu_create_mapping
  * @bus: pointer to the bus holding the client device (for IOMMU calls)
-- 
1.7.9.5



From robherring2 at gmail.com  Mon Aug 13 23:49:06 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 22:49:06 -0500
Subject: [PATCH 3/4] ARM: kill off arch_is_coherent
In-Reply-To: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344916147-13546-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

With ixp2xxx removed, there are no platforms that define arch_is_coherent,
so the last occurrences of arch_is_coherent can be removed. Any new
platform with coherent i/o should use coherent dma mapping functions.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/include/asm/barrier.h |    7 +++----
 arch/arm/include/asm/memory.h  |    8 --------
 arch/arm/mm/mmu.c              |   17 +++--------------
 3 files changed, 6 insertions(+), 26 deletions(-)

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 0511238..8dcd9c7 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -44,10 +44,9 @@
 #define rmb()		dsb()
 #define wmb()		mb()
 #else
-#include <asm/memory.h>
-#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define mb()		barrier()
+#define rmb()		barrier()
+#define wmb()		barrier()
 #endif
 
 #ifndef CONFIG_SMP
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e965f1b..93ff0f1 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -272,14 +272,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)	((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
-/*
- * Optional coherency support.  Currently used only by selected
- * Intel XSC3-based systems.
- */
-#ifndef arch_is_coherent
-#define arch_is_coherent()		0
-#endif
-
 #endif
 
 #include <asm-generic/memory_model.h>
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d045..ee2a6f0 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -216,7 +216,7 @@ static struct mem_type mem_types[] = {
 		.prot_l1	= PMD_TYPE_TABLE,
 		.prot_sect	= PROT_SECT_DEVICE | PMD_SECT_WB,
 		.domain		= DOMAIN_IO,
-	},	
+	},
 	[MT_DEVICE_WC] = {	/* ioremap_wc */
 		.prot_pte	= PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 		.prot_l1	= PMD_TYPE_TABLE,
@@ -422,17 +422,6 @@ static void __init build_mem_type_table(void)
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
 	/*
-	 * Enable CPU-specific coherency if supported.
-	 * (Only available on XSC3 at the moment.)
-	 */
-	if (arch_is_coherent() && cpu_is_xsc3()) {
-		mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
-		mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-		mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
-	}
-	/*
 	 * ARMv6 and above have extended page tables.
 	 */
 	if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
@@ -777,8 +766,8 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 		create_mapping(md);
 		vm->addr = (void *)(md->virtual & PAGE_MASK);
 		vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
-		vm->phys_addr = __pfn_to_phys(md->pfn); 
-		vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
+		vm->phys_addr = __pfn_to_phys(md->pfn);
+		vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 		vm->flags |= VM_ARM_MTYPE(md->type);
 		vm->caller = iotable_init;
 		vm_area_add_early(vm++);
-- 
1.7.9.5



From robherring2 at gmail.com  Mon Aug 13 23:49:07 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 13 Aug 2012 22:49:07 -0500
Subject: [PATCH 4/4] ARM: highbank: add coherent DMA setup
In-Reply-To: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
Message-ID: <1344916147-13546-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Some highbank DMA masters can support coherent (ACP) or non-coherent DMA.
This sets up dma_map_ops for masters which are configured for coherent DMA.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 .../devicetree/bindings/ata/ahci-platform.txt      |    3 ++
 .../devicetree/bindings/dma/arm-pl330.txt          |    3 ++
 .../devicetree/bindings/net/calxeda-xgmac.txt      |    3 ++
 arch/arm/boot/dts/highbank.dts                     |    1 +
 arch/arm/mach-highbank/highbank.c                  |   52 ++++++++++++++++++++
 5 files changed, 62 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 8bb8a76..6c1ad01 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -8,6 +8,9 @@ Required properties:
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 
+Optional properties:
+- dma-coherent      : Present if dma operations are coherent
+
 Example:
         sata at ffe08000 {
 		compatible = "calxeda,hb-ahci";
diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt
index a4cd273..36e27d5 100644
--- a/Documentation/devicetree/bindings/dma/arm-pl330.txt
+++ b/Documentation/devicetree/bindings/dma/arm-pl330.txt
@@ -9,6 +9,9 @@ Required properties:
     region.
   - interrupts: interrupt number to the cpu.
 
+Optional properties:
+- dma-coherent      : Present if dma operations are coherent
+
 Example:
 
 	pdma0: pdma at 12680000 {
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
index 411727a..c8ae996 100644
--- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
+++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
@@ -6,6 +6,9 @@ Required properties:
 - interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
   The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
 
+Optional properties:
+- dma-coherent      : Present if dma operations are coherent
+
 Example:
 
 ethernet at fff50000 {
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 9fecf1a..7414577 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -121,6 +121,7 @@
 			compatible = "calxeda,hb-ahci";
 			reg = <0xffe08000 0x10000>;
 			interrupts = <0 83 4>;
+			dma-coherent;
 		};
 
 		sdhci at ffe0e000 {
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index d75b0a7..93617d6 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -15,6 +15,7 @@
  */
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
@@ -23,6 +24,7 @@
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/amba/bus.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -149,10 +151,60 @@ static void highbank_power_off(void)
 		cpu_do_idle();
 }
 
+static int highbank_platform_notifier(struct notifier_block *nb,
+				  unsigned long event, void *__dev)
+{
+	struct resource *res;
+	int reg = -1;
+	struct device *dev = __dev;
+
+	if (event != BUS_NOTIFY_ADD_DEVICE)
+		return NOTIFY_DONE;
+
+	if (of_device_is_compatible(dev->of_node, "calxeda,hb-ahci"))
+		reg = 0xc;
+	else if (of_device_is_compatible(dev->of_node, "calxeda,hb-sdhci"))
+		reg = 0x18;
+	else if (of_device_is_compatible(dev->of_node, "arm,pl330"))
+		reg = 0x20;
+	else if (of_device_is_compatible(dev->of_node, "calxeda,hb-xgmac")) {
+		res = platform_get_resource(to_platform_device(dev),
+					    IORESOURCE_MEM, 0);
+		if (res) {
+			if (res->start == 0xfff50000)
+				reg = 0;
+			else if (res->start == 0xfff51000)
+				reg = 4;
+		}
+	}
+
+	if (reg < 0)
+		return NOTIFY_DONE;
+
+	if (of_property_read_bool(dev->of_node, "dma-coherent")) {
+		writel(0xff31, sregs_base + reg);
+		set_dma_ops(dev, &arm_coherent_dma_ops);
+	} else
+		writel(0, sregs_base + reg);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block highbank_amba_nb = {
+	.notifier_call = highbank_platform_notifier,
+};
+
+static struct notifier_block highbank_platform_nb = {
+	.notifier_call = highbank_platform_notifier,
+};
+
 static void __init highbank_init(void)
 {
 	pm_power_off = highbank_power_off;
 
+	bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
+	bus_register_notifier(&amba_bustype, &highbank_amba_nb);
+
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.7.9.5



From zhangfei.gao at gmail.com  Tue Aug 14 00:02:32 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Tue, 14 Aug 2012 12:02:32 +0800
Subject: [PATCH v2 1/4] dmaengine: mmp-pdma support
In-Reply-To: <201208131312.15180.arnd@arndb.de>
References: <1344395701-30888-1-git-send-email-zhangfei.gao@marvell.com>
 <1344395701-30888-2-git-send-email-zhangfei.gao@marvell.com>
 <201208131312.15180.arnd@arndb.de>
Message-ID: <CAMj5Bkh0VvWLXdfgtOVcKudv+FdRDYJoR1=+V-EeJLRA5Aox6w@mail.gmail.com>

>
>> +Required properties:
>> +- compatible: Should be "marvell,pdma-1.0"
>> +- reg: Should contain DMA registers location and length.
>> +- interrupts: Either contain all of the per-channel DMA interrupts
>> +               or one irq for pdma device
>> +- dma-channels: Number of DMA channels supported by the controller.
>
> I think the last one should be "#dma-channels", not "dma-channels", since it's
> counting the channels. I think we use the "#" version in the preliminary binding
> for the generic dma channel assignment in DT.
>
>         Arnd
>

Thanks Arnd for careful review, will update with "#dma-channels" in v3.

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From shawn.guo at linaro.org  Tue Aug 14 00:18:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 12:18:43 +0800
Subject: How to define gpio irq with device tree
In-Reply-To: <5024FF03.1070805@de.bosch.com>
References: <5024FF03.1070805@de.bosch.com>
Message-ID: <20120814041841.GA30782@S2101-09.ap.freescale.net>

On Fri, Aug 10, 2012 at 02:30:59PM +0200, Knut Wohlrab wrote:
> Hello,
> 
> I try the touch screen of a iMX6 SabreLite evaluation board. The
> used eGalax touch controller worked fine with a 3.2.x kernel [1]. As
> mentioned there [2] I merge the basic device tree support to the
> actual driver (see patch [4]) and add the touch definition to
> arch/arm/boot/dts/imx6q-sabrelite.dts [3].
> 
> The driver seems to start but the interrupt never occurs.
> 
> The pinmux and I2C configuration seems correct. I did a simple test
> with polling the interrupt gpio (see "POLLTEST" in patch [4]) and
> got coordinates matching to the movements on the screen.
> 
> How to configure the gpio irq correctly?
> 
> Anybody solved to work with the eGalax touch and iMX6 SabreLite with
> kernel > 3.2?
> 
I'm not interested in reviewing those out-of-tree codes to see what
goes wrong there.  But I just quickly enabled the driver for
imx6q-sabrelite board with the following changes against latest
mainline.  And the interrupt seems working for me.

Regards,
Shawn

--8<---

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..c8511c1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -115,6 +115,21 @@
 					VDDIO-supply = <&reg_3p3v>;
 				};
 			};
+
+			i2c at 021a8000 { /* I2C3 */
+				status = "okay";
+				clock-frequency = <400000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c3_1>;
+
+				egalax at 04 {
+					compatible = "eeti,egalax";
+					reg = <0x04>;
+					interrupt-parent = <&gpio1>;
+					interrupts = <9 0x8>;
+					wakeup-gpios = <&gpio1 9 0>;
+				};
+			};
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d3c64b..bbf5196 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -545,6 +545,13 @@
 					};
 				};
 
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <1013 0x4001b8b1	/* MX6Q_PAD_GPIO_5__I2C3_SCL */
+							    1037 0x4001b8b1>;	/* MX6Q_PAD_GPIO_16__I2C3_SDA */
+					};
+				};
+
 				serial2 {
 					pinctrl_serial2_1: serial2grp-1 {
 						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
index 70524dd..013011d 100644
--- a/drivers/input/touchscreen/egalax_ts.c
+++ b/drivers/input/touchscreen/egalax_ts.c
@@ -28,6 +28,8 @@
 #include <linux/slab.h>
 #include <linux/bitops.h>
 #include <linux/input/mt.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
 
 /*
  * Mouse Mode: some panel may configure the controller to mouse mode,
@@ -122,7 +124,7 @@ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
 /* wake up controller by an falling edge of interrupt gpio.  */
 static int egalax_wake_up_device(struct i2c_client *client)
 {
-	int gpio = irq_to_gpio(client->irq);
+	int gpio = of_get_named_gpio(client->dev.of_node, "wakeup-gpios", 0);
 	int ret;
 
 	ret = gpio_request(gpio, "egalax_irq");
@@ -251,6 +253,12 @@ static const struct i2c_device_id egalax_ts_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, egalax_ts_id);
 
+static struct of_device_id egalax_ts_dt_ids[] = {
+	{ .compatible = "eeti,egalax" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, egalax_ts_dt_ids);
+
 #ifdef CONFIG_PM_SLEEP
 static int egalax_ts_suspend(struct device *dev)
 {
@@ -279,6 +287,7 @@ static struct i2c_driver egalax_ts_driver = {
 		.name	= "egalax_ts",
 		.owner	= THIS_MODULE,
 		.pm	= &egalax_ts_pm_ops,
+		.of_match_table	= egalax_ts_dt_ids,
 	},
 	.id_table	= egalax_ts_id,
 	.probe		= egalax_ts_probe,
-- 
1.7.5.4




From zhangfei.gao at marvell.com  Tue Aug 14 00:11:55 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Tue, 14 Aug 2012 12:11:55 +0800
Subject: [PATCH v3 0/4]  dmaengine: add support mmp-pdma
Message-ID: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>

v2->v3 
Use "#dma-channels", instead of "dma-channels", suggested by Arnd

v1->v2
Sync with Arnd and Haojoan, change compatible name to "marvell,pdma-1.0"
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
Use IP name rather than platform name

v0->v1
Update dt member and desc according to Arnd's suggestion
Use dma_slave_config.slave_id to transfer drcmr followed Vinod's suggestion

Patch 4 is upload as example
mtd: pxa3xx-nand: replace pxa_request_dma with dmaengine
We would like hold this patch currently
since pdma will grab irq and disable pxa_init_dma. 


mmp-pdma is added under dmaengine framework.
The final purpose is replacing arch/arm/plat-pxa/dma.c

Test on pxa910 with pxa3xx-nand and dmatest.ko

Zhangfei Gao (4):
  dmaengine: mmp-pdma support
  dmaengine: mmp_tdma: add dt support
  dmatest: add dmaengine_slave_config for DMA_MEMCPY
  mtd: pxa3xx-nand: replace pxa_request_dma with dmaengine

 Documentation/devicetree/bindings/dma/mmp-dma.txt |   75 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/dmatest.c                             |    4 +
 drivers/dma/mmp_pdma.c                            |  873 +++++++++++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +-
 drivers/mtd/nand/pxa3xx_nand.c                    |  113 ++--
 include/linux/platform_data/mmp_dma.h             |   19 +
 8 files changed, 1073 insertions(+), 70 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h



From zhangfei.gao at marvell.com  Tue Aug 14 00:11:56 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Tue, 14 Aug 2012 12:11:56 +0800
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>

1. virtual channel vs. physical channel
Virtual channel is managed by dmaengine
Physical channel handling resource, such as irq
Physical channel is alloced dynamically as descending priority,
freed immediately when irq done.
The availble highest priority physically channel will alwayes be alloced

Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel

2. list: running list & pending list
submit: desc list -> pending list
issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
irq: free running list (IDLE)
     check pendlist -> pending list -> running list; free pending list (RUN)

3. irq:
Each list generate one irq, calling callback
One list may contain several desc chain, in such case, make sure only the last desc list generate irq.

4. async
Submit will add desc chain to pending list, which can be multi-called
If multi desc chain is submitted, only the last desc would generate irq -> call back
If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
If RUN, irq will start pending list

5. test
5.1 pxa3xx_nand on pxa910
5.2 insmod dmatest.ko (threads_per_chan=y)
By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   45 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/mmp_pdma.c                            |  873 +++++++++++++++++++++
 include/linux/platform_data/mmp_dma.h             |   19 +
 5 files changed, 945 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
new file mode 100644
index 0000000..cbf40d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -0,0 +1,45 @@
+* MARVELL MMP DMA controller
+
+Marvell Peripheral DMA Controller
+Used platfroms: pxa688, pxa910, pxa3xx, etc
+
+Required properties:
+- compatible: Should be "marvell,pdma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for pdma device
+- #dma-channels: Number of DMA channels supported by the controller.
+
+"marvell,pdma-1.0"
+Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
+
+Examples:
+
+/*
+ * Each channel has specific irq
+ * ICU parse out irq channel from ICU register,
+ * while DMA controller may not able to distinguish the irq channel
+ * Using this method, interrupt-parent is required as demuxer
+ * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
+ * 18~21 is ADMA irq
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+	      interrupt-parent = <&intcmux32>;
+	      #dma-channels = <16>;
+      };
+
+/*
+ * One irq for all channels
+ * Dmaengine driver (DMA controller) distinguish irq channel via
+ * parsing internal register
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <47>;
+	      #dma-channels = <16>;
+      };
+
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8904bb6..663e26b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -292,6 +292,13 @@ config MMP_TDMA
 
 	  Say Y here if you enabled MMP ADMA, otherwise say N.
 
+config MMP_PDMA
+	bool "MMP PDMA support"
+	depends on (ARCH_MMP || ARCH_PXA)
+	select DMA_ENGINE
+	help
+	  Support the MMP PDMA engine for PXA and MMP platfrom.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index eabe13c..27bd86e 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
+obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
new file mode 100644
index 0000000..ee82170
--- /dev/null
+++ b/drivers/dma/mmp_pdma.c
@@ -0,0 +1,873 @@
+/*
+ * Copyright 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/platform_data/mmp_dma.h>
+#include <linux/dmapool.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+
+#include "dmaengine.h"
+
+#define DCSR		0x0000
+#define DALGN		0x00a0  /* DMA Alignment Register */
+#define DINT		0x00f0  /* DMA Interrupt Register */
+#define DDADR		0x0200
+#define DSADR		0x0204
+#define DTADR		0x0208
+#define DCMD		0x020c
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN	(1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR	(1 << 9)        /* The end of Receive */
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x1f		/* mask for Channel Number (read / write) */
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+#define PDMA_ALIGNMENT		3
+#define PDMA_MAX_DESC_BYTES	0x1000
+
+struct mmp_pdma_desc_hw {
+	u32 ddadr;	/* Points to the next descriptor + flags */
+	u32 dsadr;	/* DSADR value for the current transfer */
+	u32 dtadr;	/* DTADR value for the current transfer */
+	u32 dcmd;	/* DCMD value for the current transfer */
+} __aligned(32);
+
+struct mmp_pdma_desc_sw {
+	struct mmp_pdma_desc_hw desc;
+	struct list_head node;
+	struct list_head tx_list;
+	struct dma_async_tx_descriptor async_tx;
+};
+
+struct mmp_pdma_phy;
+
+struct mmp_pdma_chan {
+	struct device *dev;		/* Channel device */
+	struct dma_chan chan;		/* DMA common channel */
+	struct dma_async_tx_descriptor desc;
+	struct mmp_pdma_phy *phy;
+	enum dma_transfer_direction dir;
+
+	/* channel's basic info */
+	struct tasklet_struct tasklet;
+	u32 dcmd;
+	u32 drcmr;
+	u32 dev_addr;
+
+	/* list for desc */
+	spinlock_t desc_lock;		/* Descriptor list lock */
+	struct list_head chain_pending;	/* Link descriptors queue for pending */
+	struct list_head chain_running;	/* Link descriptors queue for running */
+	bool idle;			/* channel statue machine */
+
+	struct dma_pool *desc_pool;	/* Descriptors pool */
+};
+
+struct mmp_pdma_phy {
+	int idx;
+	void __iomem *base;
+	struct mmp_pdma_chan *vchan;
+};
+
+struct mmp_pdma_device {
+	int				dma_channels;
+	void __iomem			*base;
+	struct device			*dev;
+	struct dma_device		device;
+	struct mmp_pdma_phy		*phy;
+};
+
+#define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)
+#define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)
+#define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)
+#define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)
+
+static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
+{
+	u32 reg = (phy->idx << 4) + DDADR;
+
+	writel(addr, phy->base + reg);
+}
+
+static void enable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (!phy->vchan)
+		return;
+
+	reg = phy->vchan->drcmr;
+	reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
+	writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
+
+	reg = (phy->idx << 2) + DCSR;
+	writel(readl(phy->base + reg) | DCSR_RUN,
+					phy->base + reg);
+}
+
+static void disable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (phy) {
+		reg = (phy->idx << 2) + DCSR;
+		writel(readl(phy->base + reg) & ~DCSR_RUN,
+						phy->base + reg);
+	}
+}
+
+static int clear_chan_irq(struct mmp_pdma_phy *phy)
+{
+	u32 dcsr;
+	u32 dint = readl(phy->base + DINT);
+	u32 reg = (phy->idx << 2) + DCSR;
+
+	if (dint & BIT(phy->idx)) {
+		/* clear irq */
+		dcsr = readl(phy->base + reg);
+		writel(dcsr, phy->base + reg);
+		if ((dcsr & DCSR_BUSERR) && (phy->vchan))
+			dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
+		return 0;
+	}
+	return -EAGAIN;
+}
+
+static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_phy *phy = dev_id;
+
+	if (clear_chan_irq(phy) == 0) {
+		tasklet_schedule(&phy->vchan->tasklet);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_device *pdev = dev_id;
+	struct mmp_pdma_phy *phy;
+	u32 dint = readl(pdev->base + DINT);
+	int i, ret;
+	int irq_num = 0;
+
+	while (dint) {
+		i = __ffs(dint);
+		dint &= (dint - 1);
+		phy = &pdev->phy[i];
+		ret = mmp_pdma_chan_handler(irq, phy);
+		if (ret == IRQ_HANDLED)
+			irq_num++;
+	}
+
+	if (irq_num)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+/* lookup free phy channel as descending priority */
+static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
+{
+	int prio, i;
+	struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
+	struct mmp_pdma_phy *phy;
+
+	/*
+	 * dma channel priorities
+	 * ch 0 - 3,  16 - 19  <--> (0)
+	 * ch 4 - 7,  20 - 23  <--> (1)
+	 * ch 8 - 11, 24 - 27  <--> (2)
+	 * ch 12 - 15, 28 - 31  <--> (3)
+	 */
+	for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) {
+		for (i = 0; i < pdev->dma_channels; i++) {
+			if (prio != ((i & 0xf) >> 2))
+				continue;
+			phy = &pdev->phy[i];
+			if (!phy->vchan) {
+				phy->vchan = pchan;
+				return phy;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+/* desc->tx_list ==> pending list */
+static void append_pending_queue(struct mmp_pdma_chan *chan,
+					struct mmp_pdma_desc_sw *desc)
+{
+	struct mmp_pdma_desc_sw *tail =
+				to_mmp_pdma_desc(chan->chain_pending.prev);
+
+	if (list_empty(&chan->chain_pending))
+		goto out_splice;
+
+	/* one irq per queue, even appended */
+	tail->desc.ddadr = desc->async_tx.phys;
+	tail->desc.dcmd &= ~DCMD_ENDIRQEN;
+
+	/* softly link to pending list */
+out_splice:
+	list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
+}
+
+/**
+ * start_pending_queue - transfer any pending transactions
+ * pending list ==> running list
+ */
+static void start_pending_queue(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+
+	/* still in running, irq will start the pending list */
+	if (!chan->idle) {
+		dev_dbg(chan->dev, "DMA controller still busy\n");
+		return;
+	}
+
+	if (list_empty(&chan->chain_pending)) {
+		/* chance to re-fetch phy channel with higher prio */
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		dev_dbg(chan->dev, "no pending list\n");
+		return;
+	}
+
+	if (!chan->phy) {
+		chan->phy = lookup_phy(chan);
+		if (!chan->phy) {
+			dev_dbg(chan->dev, "no free dma channel\n");
+			return;
+		}
+	}
+
+	/*
+	 * pending -> running
+	 * reintilize pending list
+	 */
+	desc = list_first_entry(&chan->chain_pending,
+				struct mmp_pdma_desc_sw, node);
+	list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
+
+	/*
+	 * Program the descriptor's address into the DMA controller,
+	 * then start the DMA transaction
+	 */
+	set_desc(chan->phy, desc->async_tx.phys);
+	enable_chan(chan->phy);
+	chan->idle = false;
+}
+
+
+/* desc->tx_list ==> pending list */
+static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
+	struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
+	struct mmp_pdma_desc_sw *child;
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	list_for_each_entry(child, &desc->tx_list, node) {
+		cookie = dma_cookie_assign(&child->async_tx);
+	}
+
+	append_pending_queue(chan, desc);
+
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return cookie;
+}
+
+struct mmp_pdma_desc_sw *mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+	dma_addr_t pdesc;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
+	if (!desc) {
+		dev_err(chan->dev, "out of memory for link descriptor\n");
+		return NULL;
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	INIT_LIST_HEAD(&desc->tx_list);
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
+	/* each desc has submit */
+	desc->async_tx.tx_submit = mmp_pdma_tx_submit;
+	desc->async_tx.phys = pdesc;
+
+	return desc;
+}
+
+/**
+ * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
+ *
+ * This function will create a dma pool for descriptor allocation.
+ * Request irq only when channel is requested
+ * Return - The number of allocated descriptors.
+ */
+
+static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+
+	if (chan->desc_pool)
+		return 1;
+
+	chan->desc_pool =
+		dma_pool_create(dev_name(&dchan->dev->device), chan->dev,
+				  sizeof(struct mmp_pdma_desc_sw),
+				  __alignof__(struct mmp_pdma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate descriptor pool\n");
+		return -ENOMEM;
+	}
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	chan->idle = true;
+	chan->dev_addr = 0;
+	return 1;
+}
+
+static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
+				  struct list_head *list)
+{
+	struct mmp_pdma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+
+	}
+}
+
+static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+	mmp_pdma_free_desc_list(chan, &chan->chain_running);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+	chan->idle = true;
+	chan->dev_addr = 0;
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	return;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_memcpy(struct dma_chan *dchan,
+	dma_addr_t dma_dst, dma_addr_t dma_src,
+	size_t len, unsigned long flags)
+{
+	struct mmp_pdma_chan *chan;
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
+	size_t copy = 0;
+
+	if (!dchan)
+		return NULL;
+
+	if (!len)
+		return NULL;
+
+	chan = to_mmp_pdma_chan(dchan);
+
+	do {
+		/* Allocate the link descriptor from DMA pool */
+		new = mmp_pdma_alloc_descriptor(chan);
+		if (!new) {
+			dev_err(chan->dev, "no memory for desc\n");
+			goto fail;
+		}
+
+		copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
+
+		new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
+		new->desc.dsadr = dma_src;
+		new->desc.dtadr = dma_dst;
+
+		if (!first)
+			first = new;
+		else
+			prev->desc.ddadr = new->async_tx.phys;
+
+		new->async_tx.cookie = 0;
+		async_tx_ack(&new->async_tx);
+
+		prev = new;
+		len -= copy;
+
+		if (chan->dir == DMA_MEM_TO_DEV) {
+			dma_src += copy;
+		} else if (chan->dir == DMA_DEV_TO_MEM) {
+			dma_dst += copy;
+		} else if (chan->dir == DMA_MEM_TO_MEM) {
+			dma_src += copy;
+			dma_dst += copy;
+		}
+
+		/* Insert the link descriptor to the LD ring */
+		list_add_tail(&new->node, &first->tx_list);
+	} while (len);
+
+	first->async_tx.flags = flags; /* client is in control of this ack */
+	first->async_tx.cookie = -EBUSY;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
+			 unsigned int sg_len, enum dma_transfer_direction dir,
+			 unsigned long flags, void *context)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
+	size_t len, avail;
+	struct scatterlist *sg;
+	dma_addr_t addr;
+	int i;
+
+	if ((sgl == NULL) || (sg_len == 0))
+		return NULL;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		addr = sg_dma_address(sg);
+		avail = sg_dma_len(sgl);
+
+		do {
+			len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
+
+			/* allocate and populate the descriptor */
+			new = mmp_pdma_alloc_descriptor(chan);
+			if (!new) {
+				dev_err(chan->dev, "no memory for desc\n");
+				goto fail;
+			}
+
+			new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
+			if (dir == DMA_MEM_TO_DEV) {
+				new->desc.dsadr = addr;
+				new->desc.dtadr = chan->dev_addr;
+			} else {
+				new->desc.dsadr = chan->dev_addr;
+				new->desc.dtadr = addr;
+			}
+
+			if (!first)
+				first = new;
+			else
+				prev->desc.ddadr = new->async_tx.phys;
+
+			new->async_tx.cookie = 0;
+			async_tx_ack(&new->async_tx);
+			prev = new;
+
+			/* Insert the link descriptor to the LD ring */
+			list_add_tail(&new->node, &first->tx_list);
+
+			/* update metadata */
+			addr += len;
+			avail -= len;
+		} while (avail);
+	}
+
+	first->async_tx.cookie = -EBUSY;
+	first->async_tx.flags = flags;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
+		unsigned long arg)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct dma_slave_config *cfg = (void *)arg;
+	unsigned long flags;
+	int ret = 0;
+	u32 maxburst = 0, addr = 0;
+	enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+
+	if (!dchan)
+		return -EINVAL;
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		disable_chan(chan->phy);
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		spin_lock_irqsave(&chan->desc_lock, flags);
+		mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+		mmp_pdma_free_desc_list(chan, &chan->chain_running);
+		spin_unlock_irqrestore(&chan->desc_lock, flags);
+		chan->idle = true;
+		break;
+	case DMA_SLAVE_CONFIG:
+		if (cfg->direction == DMA_DEV_TO_MEM) {
+			chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
+			maxburst = cfg->src_maxburst;
+			width = cfg->src_addr_width;
+			addr = cfg->src_addr;
+		} else if (cfg->direction == DMA_MEM_TO_DEV) {
+			chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
+			maxburst = cfg->dst_maxburst;
+			width = cfg->dst_addr_width;
+			addr = cfg->dst_addr;
+		} else if (cfg->direction == DMA_MEM_TO_MEM) {
+			chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
+			width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+			maxburst = 32;
+		}
+
+		if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+			chan->dcmd |= DCMD_WIDTH1;
+		else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+			chan->dcmd |= DCMD_WIDTH2;
+		else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
+			chan->dcmd |= DCMD_WIDTH4;
+
+		if (maxburst == 8)
+			chan->dcmd |= DCMD_BURST8;
+		else if (maxburst == 16)
+			chan->dcmd |= DCMD_BURST16;
+		else if (maxburst == 32)
+			chan->dcmd |= DCMD_BURST32;
+
+		if (cfg) {
+			chan->dir = cfg->direction;
+			chan->drcmr = cfg->slave_id;
+		}
+		chan->dev_addr = addr;
+		break;
+	default:
+		return -ENOSYS;
+	}
+
+	return ret;
+}
+
+static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
+			dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	enum dma_status ret;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	ret = dma_cookie_status(dchan, cookie, txstate);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return ret;
+}
+
+/**
+ * mmp_pdma_issue_pending - Issue the DMA start command
+ * pending list ==> running list
+ */
+static void mmp_pdma_issue_pending(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+}
+
+/*
+ * dma_do_tasklet
+ * Do call back
+ * Start pending list
+ */
+static void dma_do_tasklet(unsigned long data)
+{
+	struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
+	struct mmp_pdma_desc_sw *desc, *_desc;
+	LIST_HEAD(chain_cleanup);
+	unsigned long flags;
+
+	/* submit pending list; callback for each desc; free desc */
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	/* update the cookie if we have some descriptors to cleanup */
+	if (!list_empty(&chan->chain_running)) {
+		dma_cookie_t cookie;
+
+		desc = to_mmp_pdma_desc(chan->chain_running.prev);
+		cookie = desc->async_tx.cookie;
+		dma_cookie_complete(&desc->async_tx);
+
+		dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
+	}
+
+	/*
+	 * move the descriptors to a temporary list so we can drop the lock
+	 * during the entire cleanup operation
+	 */
+	list_splice_tail_init(&chan->chain_running, &chain_cleanup);
+
+	/* the hardware is now idle and ready for more */
+	chan->idle = true;
+
+	/* Start any pending transactions automatically */
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	/* Run the callback for each descriptor, in order */
+	list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
+		struct dma_async_tx_descriptor *txd = &desc->async_tx;
+
+		/* Remove from the list of transactions */
+		list_del(&desc->node);
+		/* Run the link descriptor callback function */
+		if (txd->callback)
+			txd->callback(txd->callback_param);
+
+		dma_pool_free(chan->desc_pool, desc, txd->phys);
+	}
+}
+
+static int __devexit mmp_pdma_remove(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev = platform_get_drvdata(op);
+
+	dma_async_device_unregister(&pdev->device);
+	return 0;
+}
+
+static int __devinit mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
+							int idx, int irq)
+{
+	struct mmp_pdma_phy *phy  = &pdev->phy[idx];
+	struct mmp_pdma_chan *chan;
+	int ret;
+
+	chan = devm_kzalloc(pdev->dev,
+			sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (chan == NULL)
+		return -ENOMEM;
+
+	phy->idx = idx;
+	phy->base = pdev->base;
+
+	if (irq) {
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
+		if (ret) {
+			dev_err(pdev->dev, "channel request irq fail!\n");
+			return ret;
+		}
+	}
+
+	spin_lock_init(&chan->desc_lock);
+	chan->dev = pdev->dev;
+	chan->chan.device = &pdev->device;
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+	INIT_LIST_HEAD(&chan->chain_pending);
+	INIT_LIST_HEAD(&chan->chain_running);
+
+	/* register virt channel to dma engine */
+	list_add_tail(&chan->chan.device_node,
+			&pdev->device.channels);
+
+	return 0;
+}
+
+static struct of_device_id mmp_pdma_dt_ids[] = {
+	{ .compatible = "marvell,pdma-1.0", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
+
+static int __devinit mmp_pdma_probe(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev;
+	const struct of_device_id *of_id;
+	struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
+	struct resource *iores;
+	int i, ret, irq = 0;
+	int dma_channels = 0, irq_num = 0;
+
+	pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+	pdev->dev = &op->dev;
+
+	iores = platform_get_resource(op, IORESOURCE_MEM, 0);
+	if (!iores)
+		return -EINVAL;
+
+	pdev->base = devm_request_and_ioremap(pdev->dev, iores);
+	if (!pdev->base)
+		return -EADDRNOTAVAIL;
+
+	of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
+	if (of_id)
+		of_property_read_u32(pdev->dev->of_node,
+				"#dma-channels", &dma_channels);
+	else if (pdata && pdata->dma_channels)
+		dma_channels = pdata->dma_channels;
+	else
+		dma_channels = 32;	/* default 32 channel */
+	pdev->dma_channels = dma_channels;
+
+	for (i = 0; i < dma_channels; i++) {
+		if (platform_get_irq(op, i) > 0)
+			irq_num++;
+	}
+
+	pdev->phy = devm_kzalloc(pdev->dev,
+		dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (pdev->phy == NULL)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&pdev->device.channels);
+
+	if (irq_num != dma_channels) {
+		/* all chan share one irq, demux inside */
+		irq = platform_get_irq(op, 0);
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < dma_channels; i++) {
+		irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
+		ret = mmp_pdma_chan_init(pdev, i, irq);
+		if (ret)
+			return ret;
+	}
+
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	pdev->device.dev = &op->dev;
+	pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
+	pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
+	pdev->device.device_tx_status = mmp_pdma_tx_status;
+	pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
+	pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
+	pdev->device.device_issue_pending = mmp_pdma_issue_pending;
+	pdev->device.device_control = mmp_pdma_control;
+	pdev->device.copy_align = PDMA_ALIGNMENT;
+
+	if (pdev->dev->coherent_dma_mask)
+		dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
+	else
+		dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
+
+	ret = dma_async_device_register(&pdev->device);
+	if (ret) {
+		dev_err(pdev->device.dev, "unable to register\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct platform_device_id mmp_pdma_id_table[] = {
+	{ "mmp-pdma", },
+	{ },
+};
+
+static struct platform_driver mmp_pdma_driver = {
+	.driver		= {
+		.name	= "mmp-pdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = mmp_pdma_dt_ids,
+	},
+	.id_table	= mmp_pdma_id_table,
+	.probe		= mmp_pdma_probe,
+	.remove		= __devexit_p(mmp_pdma_remove),
+};
+
+module_platform_driver(mmp_pdma_driver);
+
+MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/mmp_dma.h b/include/linux/platform_data/mmp_dma.h
new file mode 100644
index 0000000..2a330ec
--- /dev/null
+++ b/include/linux/platform_data/mmp_dma.h
@@ -0,0 +1,19 @@
+/*
+ *  MMP Platform DMA Management
+ *
+ *  Copyright (c) 2011 Marvell Semiconductors Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#ifndef MMP_DMA_H
+#define MMP_DMA_H
+
+struct mmp_dma_platdata {
+	int dma_channels;
+};
+
+#endif /* MMP_DMA_H */
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug 14 00:11:57 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Tue, 14 Aug 2012 12:11:57 +0800
Subject: [PATCH v3 2/4] dmaengine: mmp_tdma: add dt support
In-Reply-To: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344917519-9505-3-git-send-email-zhangfei.gao@marvell.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   30 ++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +++++++++++++--------
 2 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
index cbf40d6..36254c4 100644
--- a/Documentation/devicetree/bindings/dma/mmp-dma.txt
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -43,3 +43,33 @@ pdma: dma-controller at d4000000 {
 	      #dma-channels = <16>;
       };
 
+
+Marvell Two Channel DMA Controller used specifically for audio
+Used platfroms: pxa688, pxa910
+
+Required properties:
+- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for dma device
+
+"marvell,adma-1.0" used on pxa688
+"marvell,pxa910-squ" used on pxa910
+
+Examples:
+
+/* each channel has specific irq */
+adma0: dma-controller at d42a0800 {
+	      compatible = "marvell,adma-1.0";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <18 19>;
+	      interrupt-parent = <&intcmux32>;
+      };
+
+/* One irq for all channels */
+squ: dma-controller at d42a0800 {
+	      compatible = "marvell,pxa910-squ";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <46>;
+      };
+
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
index 8a15cf2..b93d73c 100644
--- a/drivers/dma/mmp_tdma.c
+++ b/drivers/dma/mmp_tdma.c
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <mach/regs-icu.h>
 #include <mach/sram.h>
+#include <linux/of_device.h>
 
 #include "dmaengine.h"
 
@@ -127,7 +128,6 @@ struct mmp_tdma_device {
 	void __iomem			*base;
 	struct dma_device		device;
 	struct mmp_tdma_chan		*tdmac[TDMA_CHANNEL_NUM];
-	int				irq;
 };
 
 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
@@ -492,7 +492,7 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 		return -ENOMEM;
 	}
 	if (irq)
-		tdmac->irq = irq + idx;
+		tdmac->irq = irq;
 	tdmac->dev	   = tdev->dev;
 	tdmac->chan.device = &tdev->device;
 	tdmac->idx	   = idx;
@@ -505,34 +505,43 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 	/* add the channel to tdma_chan list */
 	list_add_tail(&tdmac->chan.device_node,
 			&tdev->device.channels);
-
 	return 0;
 }
 
+static struct of_device_id mmp_tdma_dt_ids[] = {
+	{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
+	{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
+
 static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 {
-	const struct platform_device_id *id = platform_get_device_id(pdev);
-	enum mmp_tdma_type type = id->driver_data;
+	enum mmp_tdma_type type;
+	const struct of_device_id *of_id;
 	struct mmp_tdma_device *tdev;
 	struct resource *iores;
 	int i, ret;
-	int irq = 0;
+	int irq = 0, irq_num = 0;
 	int chan_num = TDMA_CHANNEL_NUM;
 
+	of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
+	if (of_id)
+		type = (enum mmp_tdma_type) of_id->data;
+	else
+		type = platform_get_device_id(pdev)->driver_data;
+
 	/* always have couple channels */
 	tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
 	if (!tdev)
 		return -ENOMEM;
 
 	tdev->dev = &pdev->dev;
-	iores = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!iores)
-		return -EINVAL;
 
-	if (resource_size(iores) != chan_num)
-		tdev->irq = iores->start;
-	else
-		irq = iores->start;
+	for (i = 0; i < chan_num; i++) {
+		if (platform_get_irq(pdev, i) > 0)
+			irq_num++;
+	}
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iores)
@@ -542,25 +551,26 @@ static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 	if (!tdev->base)
 		return -EADDRNOTAVAIL;
 
-	if (tdev->irq) {
-		ret = devm_request_irq(&pdev->dev, tdev->irq,
+	INIT_LIST_HEAD(&tdev->device.channels);
+
+	if (irq_num != chan_num) {
+		irq = platform_get_irq(pdev, 0);
+		ret = devm_request_irq(&pdev->dev, irq,
 			mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
 		if (ret)
 			return ret;
 	}
 
-	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
-	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
-
-	INIT_LIST_HEAD(&tdev->device.channels);
-
 	/* initialize channel parameters */
 	for (i = 0; i < chan_num; i++) {
+		irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
 		ret = mmp_tdma_chan_init(tdev, i, irq, type);
 		if (ret)
 			return ret;
 	}
 
+	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
+	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
 	tdev->device.dev = &pdev->dev;
 	tdev->device.device_alloc_chan_resources =
 					mmp_tdma_alloc_chan_resources;
@@ -595,6 +605,7 @@ static struct platform_driver mmp_tdma_driver = {
 	.driver		= {
 		.name	= "mmp-tdma",
 		.owner  = THIS_MODULE,
+		.of_match_table = mmp_tdma_dt_ids,
 	},
 	.id_table	= mmp_tdma_id_table,
 	.probe		= mmp_tdma_probe,
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug 14 00:11:58 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Tue, 14 Aug 2012 12:11:58 +0800
Subject: [PATCH v3 3/4] dmatest: add dmaengine_slave_config for DMA_MEMCPY
In-Reply-To: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344917519-9505-4-git-send-email-zhangfei.gao@marvell.com>

Set direction to DMA_MEM_TO_MEM
DMA driver may require such configure info

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 drivers/dma/dmatest.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 24225f0..73bab68 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -261,6 +261,9 @@ static int dmatest_func(void *data)
 	int			src_cnt;
 	int			dst_cnt;
 	int			i;
+	struct dma_slave_config conf = {
+		.direction = DMA_MEM_TO_MEM,
+	};
 
 	thread_name = current->comm;
 	set_freezable();
@@ -361,6 +364,7 @@ static int dmatest_func(void *data)
 						     DMA_BIDIRECTIONAL);
 		}
 
+		dmaengine_slave_config(chan, &conf);
 
 		if (thread->type == DMA_MEMCPY)
 			tx = dev->device_prep_dma_memcpy(chan,
-- 
1.7.1



From zhangfei.gao at marvell.com  Tue Aug 14 00:11:59 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Tue, 14 Aug 2012 12:11:59 +0800
Subject: [PATCH v3 4/4] mtd: pxa3xx-nand: replace pxa_request_dma with
 dmaengine
In-Reply-To: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1344917519-9505-5-git-send-email-zhangfei.gao@marvell.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  113 ++++++++++++++++++++++------------------
 1 files changed, 63 insertions(+), 50 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c5ea313..2768826 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,8 +22,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
+#include <linux/dmaengine.h>
 
-#include <mach/dma.h>
 #include <plat/pxa3xx_nand.h>
 
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
@@ -162,8 +162,7 @@ struct pxa3xx_nand_info {
 	unsigned char		*data_buff;
 	unsigned char		*oob_buff;
 	dma_addr_t 		data_buff_phys;
-	int 			data_dma_ch;
-	struct pxa_dma_desc	*data_desc;
+	struct dma_chan		*data_dma_ch;
 	dma_addr_t 		data_desc_addr;
 
 	struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
@@ -332,14 +331,6 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 	nand_writel(info, NDSR, NDSR_MASK);
 }
 
-static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
-{
-	uint32_t ndcr;
-
-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~int_mask);
-}
-
 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 {
 	uint32_t ndcr;
@@ -372,24 +363,38 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
 	}
 }
 
+static void dma_complete_func(void *data)
+{
+	struct pxa3xx_nand_info *info = data;
+
+	info->state = STATE_DMA_DONE;
+}
+
 static void start_data_dma(struct pxa3xx_nand_info *info)
 {
-	struct pxa_dma_desc *desc = info->data_desc;
+	struct dma_device *dma_dev;
+	struct dma_async_tx_descriptor *tx = NULL;
+	dma_addr_t dma_src_addr, dma_dst_addr;
+	dma_cookie_t cookie;
 	int dma_len = ALIGN(info->data_size + info->oob_size, 32);
+	struct dma_slave_config conf;
 
-	desc->ddadr = DDADR_STOP;
-	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
+	dma_dev = info->data_dma_ch->device;
 
 	switch (info->state) {
 	case STATE_DMA_WRITING:
-		desc->dsadr = info->data_buff_phys;
-		desc->dtadr = info->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
+		dma_src_addr = info->data_buff_phys;
+		dma_dst_addr = info->mmio_phys + NDDB;
+		conf.direction = DMA_MEM_TO_DEV;
+		conf.dst_maxburst = 32;
+		conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	case STATE_DMA_READING:
-		desc->dtadr = info->data_buff_phys;
-		desc->dsadr = info->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
+		dma_src_addr = info->mmio_phys + NDDB;
+		dma_dst_addr = info->data_buff_phys;
+		conf.direction = DMA_DEV_TO_MEM;
+		conf.src_maxburst = 32;
+		conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	default:
 		dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
@@ -397,26 +402,27 @@ static void start_data_dma(struct pxa3xx_nand_info *info)
 		BUG();
 	}
 
-	DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
-	DDADR(info->data_dma_ch) = info->data_desc_addr;
-	DCSR(info->data_dma_ch) |= DCSR_RUN;
-}
-
-static void pxa3xx_nand_data_dma_irq(int channel, void *data)
-{
-	struct pxa3xx_nand_info *info = data;
-	uint32_t dcsr;
+	conf.slave_id = info->drcmr_dat;
+	dmaengine_slave_config(info->data_dma_ch, &conf);
+	tx = dma_dev->device_prep_dma_memcpy(info->data_dma_ch, dma_dst_addr,
+					     dma_src_addr, dma_len, 0);
+	if (!tx) {
+		dev_err(&info->pdev->dev, "Failed to prepare DMA memcpy\n");
+		return;
+	}
 
-	dcsr = DCSR(channel);
-	DCSR(channel) = dcsr;
+	tx->callback = dma_complete_func;
+	tx->callback_param = info;
 
-	if (dcsr & DCSR_BUSERR) {
-		info->retcode = ERR_DMABUSERR;
+	cookie = tx->tx_submit(tx);
+	if (dma_submit_error(cookie)) {
+		dev_err(&info->pdev->dev, "Failed to do DMA tx_submit\n");
+		return;
 	}
 
-	info->state = STATE_DMA_DONE;
-	enable_int(info, NDCR_INT_MASK);
-	nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
+	dma_async_issue_pending(info->data_dma_ch);
+
+	return;
 }
 
 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
@@ -434,6 +440,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	}
 
 	status = nand_readl(info, NDSR);
+	nand_writel(info, NDSR, status);
 
 	if (status & NDSR_DBERR)
 		info->retcode = ERR_DBERR;
@@ -442,7 +449,6 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 		/* whether use dma to transfer data */
 		if (info->use_dma) {
-			disable_int(info, NDCR_INT_MASK);
 			info->state = (status & NDSR_RDDREQ) ?
 				      STATE_DMA_READING : STATE_DMA_WRITING;
 			start_data_dma(info);
@@ -757,6 +763,9 @@ static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
+	if (len > mtd->oobsize)
+		info->use_dma = use_dma;
+
 	memcpy(buf, info->data_buff + info->buf_start, real_len);
 	info->buf_start += real_len;
 }
@@ -768,6 +777,9 @@ static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
+	if (len > mtd->oobsize)
+		info->use_dma = use_dma;
+
 	memcpy(info->data_buff + info->buf_start, buf, real_len);
 	info->buf_start += real_len;
 }
@@ -886,7 +898,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 {
 	struct platform_device *pdev = info->pdev;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
+	dma_cap_mask_t mask;
 
 	if (use_dma == 0) {
 		info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
@@ -902,19 +914,20 @@ static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 		return -ENOMEM;
 	}
 
-	info->data_desc = (void *)info->data_buff + data_desc_offset;
-	info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 
-	info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
-				pxa3xx_nand_data_dma_irq, info);
-	if (info->data_dma_ch < 0) {
-		dev_err(&pdev->dev, "failed to request data dma\n");
-		dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
-				info->data_buff, info->data_buff_phys);
-		return info->data_dma_ch;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_MEMCPY, mask);
+	info->data_dma_ch = dma_request_channel(mask, NULL, NULL);
+	if (!info->data_dma_ch) {
+		dev_info(&pdev->dev, "Failed to request DMA channel\n");
+		goto dma_request_fail;
 	}
-
 	return 0;
+
+dma_request_fail:
+	dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			info->data_buff, info->data_buff_phys);
+	return -EAGAIN;
 }
 
 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
@@ -1149,7 +1162,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
 fail_free_buf:
 	free_irq(irq, info);
 	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
+		dma_release_channel(info->data_dma_ch);
 		dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 			info->data_buff, info->data_buff_phys);
 	} else
@@ -1183,7 +1196,7 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
 	if (irq >= 0)
 		free_irq(irq, info);
 	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
+		dma_release_channel(info->data_dma_ch);
 		dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
 				info->data_buff, info->data_buff_phys);
 	} else
-- 
1.7.1



From bhelgaas at google.com  Tue Aug 14 01:00:45 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Mon, 13 Aug 2012 22:00:45 -0700
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>

On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> This commit adds a new flag that allows marking resources as PCI
> configuration space.
>
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v3:
> - new patch
>
>  include/linux/ioport.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/ioport.h b/include/linux/ioport.h
> index 589e0e7..3314843 100644
> --- a/include/linux/ioport.h
> +++ b/include/linux/ioport.h
> @@ -102,7 +102,7 @@ struct resource {
>
>  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
>  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
> -
> +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */

What is the purpose of this?  It seems that you are marking regions
that we call MMCONFIG on x86, or ECAM-type regions in the language of
the PCIe spec.  I see that you set it in several places, but I don't
see anything that ever looks for it.  Do you have plans to use it in
the future?  If it really does correspond to MMCONFIG/ECAM, we should
handle those regions consistently across all architectures.

>  /* helpers to define resources */
>  #define DEFINE_RES_NAMED(_start, _size, _name, _flags)                 \
> --
> 1.7.11.2
>


From bhelgaas at google.com  Tue Aug 14 01:06:38 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Mon, 13 Aug 2012 22:06:38 -0700
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <CAErSpo5YDwstHv7B7LEbDQmnHnuVsMA2ibTFNLkiCKmkkeE4Zw@mail.gmail.com>

On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> When using deferred driver probing, PCI host controller drivers may
> actually require this function after the init stage.

Yes, this is a bug.  Actually, there's still another bug here: if we
hot-add a device, we won't do pdev_fixup_irq() for it.  But your
change is worthwhile even without fixing that other bug.

Normally I would include this in my PCI tree since it's under
drivers/pci.  That would make it easier for somebody to fix the
hotplug problem in this cycle.  Would having it in my PCI tree make
things harder for you?

> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Acked-by: Bjorn Helgaas <bhelgaas at google.com>

> ---
> Changes in v3:
> - none
>
> Changes in v2:
> - use __devinit annotations
>
>  drivers/pci/setup-irq.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
> index eb219a1..f0bcd56 100644
> --- a/drivers/pci/setup-irq.c
> +++ b/drivers/pci/setup-irq.c
> @@ -18,7 +18,7 @@
>  #include <linux/cache.h>
>
>
> -static void __init
> +static void __devinit
>  pdev_fixup_irq(struct pci_dev *dev,
>                u8 (*swizzle)(struct pci_dev *, u8 *),
>                int (*map_irq)(const struct pci_dev *, u8, u8))
> @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev,
>         pcibios_update_irq(dev, irq);
>  }
>
> -void __init
> +void __devinit
>  pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
>                int (*map_irq)(const struct pci_dev *, u8, u8))
>  {
> --
> 1.7.11.2
>


From thierry.reding at avionic-design.de  Tue Aug 14 01:37:55 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 07:37:55 +0200
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <CAErSpo5YDwstHv7B7LEbDQmnHnuVsMA2ibTFNLkiCKmkkeE4Zw@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo5YDwstHv7B7LEbDQmnHnuVsMA2ibTFNLkiCKmkkeE4Zw@mail.gmail.com>
Message-ID: <20120814053755.GA16181@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 13, 2012 at 10:06:38PM -0700, Bjorn Helgaas wrote:
> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > When using deferred driver probing, PCI host controller drivers may
> > actually require this function after the init stage.
> 
> Yes, this is a bug.  Actually, there's still another bug here: if we
> hot-add a device, we won't do pdev_fixup_irq() for it.  But your
> change is worthwhile even without fixing that other bug.
> 
> Normally I would include this in my PCI tree since it's under
> drivers/pci.  That would make it easier for somebody to fix the
> hotplug problem in this cycle.  Would having it in my PCI tree make
> things harder for you?

No, not at all.

> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> 
> Acked-by: Bjorn Helgaas <bhelgaas at google.com>

Thierry
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From jason77.wang at gmail.com  Tue Aug 14 01:46:46 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Tue, 14 Aug 2012 13:46:46 +0800
Subject: How to define gpio irq with device tree
In-Reply-To: <20120814041841.GA30782@S2101-09.ap.freescale.net>
References: <5024FF03.1070805@de.bosch.com>
 <20120814041841.GA30782@S2101-09.ap.freescale.net>
Message-ID: <5029E646.5090900@gmail.com>

Shawn Guo wrote:
> On Fri, Aug 10, 2012 at 02:30:59PM +0200, Knut Wohlrab wrote:
>   
>> Hello,
>>
>> I try the touch screen of a iMX6 SabreLite evaluation board. The
>> used eGalax touch controller worked fine with a 3.2.x kernel [1]. As
>> mentioned there [2] I merge the basic device tree support to the
>> actual driver (see patch [4]) and add the touch definition to
>> arch/arm/boot/dts/imx6q-sabrelite.dts [3].
>>
>> The driver seems to start but the interrupt never occurs.
>>
>> The pinmux and I2C configuration seems correct. I did a simple test
>> with polling the interrupt gpio (see "POLLTEST" in patch [4]) and
>> got coordinates matching to the movements on the screen.
>>
>> How to configure the gpio irq correctly?
>>
>> Anybody solved to work with the eGalax touch and iMX6 SabreLite with
>> kernel > 3.2?
>>
>>     
> I'm not interested in reviewing those out-of-tree codes to see what
> goes wrong there.  But I just quickly enabled the driver for
> imx6q-sabrelite board with the following changes against latest
> mainline.  And the interrupt seems working for me.
>
>   
I generated a similar patch on the last week, only the linux-input part. 
please refer to https://patchwork.kernel.org/patch/1293451/

For mach dts part:

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts 
b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d42e851..71fcd12 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -53,6 +53,7 @@
fsl,pins = <
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+ 972 0x10 /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
 >;
};
};
@@ -114,6 +115,21 @@
VDDIO-supply = <&reg_3p3v>;
};
};
+
+ i2c at 021a8000 { /* I2C3 */
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_1>;
+
+ egalax_ts at 04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 2>;
+ irq-gpio = <&gpio1 9 0>;
+ };
+ };
};
};

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d3c64b..ebbd624 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -545,6 +545,14 @@
};
};

+
+ i2c3 {
+ pinctrl_i2c3_1: i2c3grp-1 {
+ fsl,pins = <1013 0x4001b8b1 /* MX6Q_PAD_GPIO_5__I2C3_SCL */
+ 1037 0x4001b8b1>; /* MX6Q_PAD_GPIO_16__I2C3_SDA */
+ };
+ };
+
serial2 {
pinctrl_serial2_1: serial2grp-1 {
fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */

> Regards,
> Shawn
>
> --8<---
>
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index 72f30f3..c8511c1 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -115,6 +115,21 @@
>  					VDDIO-supply = <&reg_3p3v>;
>  				};
>  			};
> +
> +			i2c at 021a8000 { /* I2C3 */
> +				status = "okay";
> +				clock-frequency = <400000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_i2c3_1>;
> +
> +				egalax at 04 {
> +					compatible = "eeti,egalax";
> +					reg = <0x04>;
> +					interrupt-parent = <&gpio1>;
> +					interrupts = <9 0x8>;
> +					wakeup-gpios = <&gpio1 9 0>;
> +				};
> +			};
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 3d3c64b..bbf5196 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -545,6 +545,13 @@
>  					};
>  				};
>  
> +				i2c3 {
> +					pinctrl_i2c3_1: i2c3grp-1 {
> +						fsl,pins = <1013 0x4001b8b1	/* MX6Q_PAD_GPIO_5__I2C3_SCL */
> +							    1037 0x4001b8b1>;	/* MX6Q_PAD_GPIO_16__I2C3_SDA */
> +					};
> +				};
> +
>  				serial2 {
>  					pinctrl_serial2_1: serial2grp-1 {
>  						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
> diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
> index 70524dd..013011d 100644
> --- a/drivers/input/touchscreen/egalax_ts.c
> +++ b/drivers/input/touchscreen/egalax_ts.c
> @@ -28,6 +28,8 @@
>  #include <linux/slab.h>
>  #include <linux/bitops.h>
>  #include <linux/input/mt.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
>  
>  /*
>   * Mouse Mode: some panel may configure the controller to mouse mode,
> @@ -122,7 +124,7 @@ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
>  /* wake up controller by an falling edge of interrupt gpio.  */
>  static int egalax_wake_up_device(struct i2c_client *client)
>  {
> -	int gpio = irq_to_gpio(client->irq);
> +	int gpio = of_get_named_gpio(client->dev.of_node, "wakeup-gpios", 0);
>  	int ret;
>  
>  	ret = gpio_request(gpio, "egalax_irq");
> @@ -251,6 +253,12 @@ static const struct i2c_device_id egalax_ts_id[] = {
>  };
>  MODULE_DEVICE_TABLE(i2c, egalax_ts_id);
>  
> +static struct of_device_id egalax_ts_dt_ids[] = {
> +	{ .compatible = "eeti,egalax" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, egalax_ts_dt_ids);
> +
>  #ifdef CONFIG_PM_SLEEP
>  static int egalax_ts_suspend(struct device *dev)
>  {
> @@ -279,6 +287,7 @@ static struct i2c_driver egalax_ts_driver = {
>  		.name	= "egalax_ts",
>  		.owner	= THIS_MODULE,
>  		.pm	= &egalax_ts_pm_ops,
> +		.of_match_table	= egalax_ts_dt_ids,
>  	},
>  	.id_table	= egalax_ts_id,
>  	.probe		= egalax_ts_probe,
>   



From gerg at snapgear.com  Tue Aug 14 01:48:43 2012
From: gerg at snapgear.com (gerg at snapgear.com)
Date: Tue, 14 Aug 2012 15:48:43 +1000
Subject: [PATCH] ARM: ixp4xx: move fixed mapping of internal devices into
 vmalloc region
Message-ID: <1344923323-10327-1-git-send-email-gerg@snapgear.com>

From: Greg Ungerer <gerg at uclinux.org>

The current fixed physical/virtual mappings for the internal peripherals
of the ixp4xx SoC devices is using a virtual address outside of the vmalloc
region. This results in kernel warnings like this on the boot console:

  BUG: mapping for 0xc8000000 at 0xffbeb000 out of vmalloc space
  BUG: mapping for 0xc4000000 at 0xffbfe000 out of vmalloc space
  BUG: mapping for 0xc0000000 at 0xffbff000 out of vmalloc space

The virtual kernel memory layout lists this for the vmalloc region:

    ...
    vmalloc : 0xc2800000 - 0xff000000   ( 968 MB)
    ...

With a little adjustment to the virtual address used we can map these
internal devices in the vmalloc region.

Signed-off-by: Greg Ungerer <gerg at uclinux.org>
---
 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 97c530f..ad66605 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -32,11 +32,11 @@
  *
  * 0x6000000	0x00004000	ioremap'd	QMgr
  *
- * 0xC0000000	0x00001000	0xffbff000	PCI CFG
+ * 0xC0000000	0x00001000	0xfebff000	PCI CFG
  *
- * 0xC4000000	0x00001000	0xffbfe000	EXP CFG
+ * 0xC4000000	0x00001000	0xfebfe000	EXP CFG
  *
- * 0xC8000000	0x00013000	0xffbeb000	On-Chip Peripherals
+ * 0xC8000000	0x00013000	0xfebeb000	On-Chip Peripherals
  */
 
 /*
@@ -49,21 +49,21 @@
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT	(0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT	(0xFEBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE	(0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFF000)
+#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFEBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE	(0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT	(0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT	(0xFEBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE	(0x00013000)
 
 /*
@@ -73,7 +73,7 @@
  * aligned so that it * can be used with the low-level debug code.
  */
 #define	IXP4XX_DEBUG_UART_BASE_PHYS	(0xC8000000)
-#define	IXP4XX_DEBUG_UART_BASE_VIRT	(0xffb00000)
+#define	IXP4XX_DEBUG_UART_BASE_VIRT	(0xfeb00000)
 #define	IXP4XX_DEBUG_UART_REGION_SIZE	(0x00001000)
 
 #define IXP4XX_EXP_CS0_OFFSET	0x00
-- 
1.7.0.4



From thierry.reding at avionic-design.de  Tue Aug 14 01:55:42 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 07:55:42 +0200
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
Message-ID: <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 13, 2012 at 10:00:45PM -0700, Bjorn Helgaas wrote:
> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > This commit adds a new flag that allows marking resources as PCI
> > configuration space.
> >
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v3:
> > - new patch
> >
> >  include/linux/ioport.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/linux/ioport.h b/include/linux/ioport.h
> > index 589e0e7..3314843 100644
> > --- a/include/linux/ioport.h
> > +++ b/include/linux/ioport.h
> > @@ -102,7 +102,7 @@ struct resource {
> >
> >  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
> >  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
> > -
> > +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */
> 
> What is the purpose of this?  It seems that you are marking regions
> that we call MMCONFIG on x86, or ECAM-type regions in the language of
> the PCIe spec.  I see that you set it in several places, but I don't
> see anything that ever looks for it.  Do you have plans to use it in
> the future?  If it really does correspond to MMCONFIG/ECAM, we should
> handle those regions consistently across all architectures.

The purpose is ultimately to obtain the MMCONFIG/ECAM resources assigned
to a PCI host controller. I've used this in the of_pci_parse_ranges()
and in the static board setup code to mark ranges as such. Perhaps
IORESOURCE_ECAM or IORESOURCE_MMCONFIG might have been better names. I
also just noticed that I'm not using this anywhere, but the plan was to
eventually use it with platform_get_resource(). However that doesn't
seem to work either because the lower bits of the flags aren't use for
comparison in that function.

Any other ideas how that could be handled? Basically what I need is a
way to mark a resource as an MMCONFIG/ECAM range so that it can be used
to program the PCI host controller accordingly. I don't know how these
are assigned on x86. I was under the impression that the MMCONFIG/ECAM
space was accessed through a single single address/data register pair.

On Tegra 20 this region can be anywhere in the upper 1 GiB of the 4 GiB
address space, while on Tegra 30 it can be anywhere in the lower 1 GiB,
so they can be freely assigned.

Thierry
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From thierry.reding at avionic-design.de  Tue Aug 14 02:14:08 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 08:14:08 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502973E5.6000303@gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <20120813203300.GA8891@avionic-0098.mockup.avionic-design.de>
 <502973E5.6000303@gmail.com>
Message-ID: <20120814061408.GC16181@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 13, 2012 at 04:38:45PM -0500, Rob Herring wrote:
> On 08/13/2012 03:33 PM, Thierry Reding wrote:
> > On Mon, Aug 13, 2012 at 12:47:38PM -0600, Stephen Warren wrote:
> >> On 08/13/2012 11:40 AM, Thierry Reding wrote:
> >>> On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
> >>>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> >>>>> This patch series adds support for device tree based probing of
> >>>>> the PCIe controller found on Tegra SoCs.
> >>>>
> >>>> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
> >>>> that PCIe doesn't work on TrimSlice when booting use device tree.
> >>>> I think I found the cause, and I can't see why the same problem
> >>>> doesn't affect this series. Perhaps you can enlighten me?
> >> ...
> >>>> PCI: Device 0000:01:00.0 not available because of resource
> >>>> collisions
> >> ...
> >>> I've looked into this a bit, and it seems like ARM is using an
> >>> open- coded version of the pci_enable_resources() function here,
> >>> with the only difference being the unconditional enabling of both
> >>> I/O and memory- mapped access for bridges. On Tegra there is
> >>> already a PCI fixup to do this, so pci_enable_resources() can be
> >>> used as-is. I came up with the attached patch but haven't been able
> >>> to test it yet.
> >>
> >> Thanks very much for looking into this.
> >>
> >> The patch did alter the behavior a little for TrimSlice, but didn't
> >> solve the problem. The old error messages:
> >>
> >>> [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
> >>> [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
> >>> [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22
> >>
> >> Were replaced with the following with your patch:
> >>
> >>> [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
> >>> [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
> >>> [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22
> >>
> >> This message appears from drivers/pci/setup-res.c pci_enable_resources()
> >> due to:
> >>
> >>> 		if (!r->parent) {
> >>> 			dev_err(&dev->dev, "device not available "
> >>> 				"(can't reserve %pR)\n", r);
> >>> 			return -EINVAL;
> >>> 		}
> > 
> > Looking at the code some more, this may be caused by the pci_remap_io()
> > patch series, so you might want to revert that patch and see if it fixes
> > the I/O resources.
> > 
> 
> Humm... But this patch deals with the i/o space and it is failing below
> on the memory space.

But above it also fails for I/O. Looking at this some more, it seems
like your patch isn't at fault. Rather there seems to be a general
resource assignment problem.

> 
> >> That check doesn't appear in ARM's custom pcibios_enable_device().
> >> Disabling that check yields:
> >>
> >>> [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
> >>> [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> >>> [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16
> >>
> >> I think that's because the pci_dev's resources are initially assigned
> >> PCI-aperture-relative addresses, and then these are later patched up to
> >> take account of where the aperture is mapped into the CPU's address space.
> >>
> >> Boot log using board files:
> >>
> >>> [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> >>> [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> >>> [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> >> ...
> >>> [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> >>> [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> >>> [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> >>> [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> >> ... (I added some extra printks:)
> >>> [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
> >>> [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
> >>> [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]
> >>
> >> whereas for a device tree boot:
> >>
> >> (same):
> >>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> >>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> >>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> >> ... (request region happens early)
> >>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
> >>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> >> ... (same, just happens too late)
> >>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> >>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> >>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> >>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> >>
> >> I suspect this is all still related to the PCI devices themselves being
> >> probed much earlier in the overall PCI initialization sequence when the
> >> PCI controller is probed later in the boot sequence, whereas PCI device
> >> probe is deferred until the overall PCI initialization sequence is
> >> complete if the PCI controller is probed very early in the boot sequence.
> >>
> >> Does anyone know where/what that "probe now" vs. "probe later" decision
> >> point is? I'll try and track it down if nobody beats me to it.
> > 
> > There's the io_offset and mem_offset fields that I've completely ignored
> > up to now. Can you try the patch below to see if it changes anything?
> > I'm sorry but I can't test any of this myself right now.
> 
> Arnd and I discussed io_offset some. I don't think either of us can
> figure out when it should be anything but 0 at least if pci i/o bus
> addresses start at 0.
> 
> I don't think mem_offset is the issue. I think perhaps you need to set
> pcibios_min_mem to the memory window base (0xa0000000), but that's just
> a guess.

I'm having trouble understanding how that's supposed to work for regions
of prefetchable memory. At least on Tegra these can arbitrarily assigned
and I thought I had seen other platforms where this was also the case.

However the pcibios_min_mem (or the equivalent macro PCIBIOS_MIN_MEM) is
used while assigning the resources in the __pci_assign_resources() in
drivers/pci/setup-res.c, so it may influence things.

But I think the more fundamental issue here is that BARs are assigned
properly, only they are assigned too late in the DT case as opposed to
the board files case. I don't understand why that happens.

Thierry
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From peter.ujfalusi at ti.com  Tue Aug 14 02:14:50 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 09:14:50 +0300
Subject: [PATCH v2 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting
 code to ASoC driver
In-Reply-To: <20120813153554.GA31662@n2100.arm.linux.org.uk>
References: <1344867768-26335-1-git-send-email-peter.ujfalusi@ti.com>
 <1344867768-26335-2-git-send-email-peter.ujfalusi@ti.com>
 <20120813153554.GA31662@n2100.arm.linux.org.uk>
Message-ID: <5029ECDA.5020405@ti.com>

On 08/13/2012 06:35 PM, Russell King - ARM Linux wrote:
> I know the same error is in the original code, but let's stop propagating
> it.  IS_ERR() only here please.

I have overlooked this. I'll include the fix in v3.

-- 
P?ter


From sourav.poddar at ti.com  Tue Aug 14 02:23:18 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 14 Aug 2012 11:53:18 +0530
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <1342780715-25618-1-git-send-email-sourav.poddar@ti.com>
References: <1342780715-25618-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <CAKdam54ifAW=W86qLj3+JR6k7i00EjDSQgK5B1X--NCg18jJmw@mail.gmail.com>

Hi,

On Fri, Jul 20, 2012 at 4:08 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
> Add keypad data node in omap4 device tree file.
> Also fill the device tree binding parameters
> with the required value in "omap4-sdp" dts file.
>
> Tested on omap4430 sdp with 3.5-rc6 kernel.
>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
> Changes since v6:
> -remove address from the node since reg property
> is not used.
>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>  2 files changed, 75 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> index 72216e9..80cd016 100644
> --- a/arch/arm/boot/dts/omap4-sdp.dts
> +++ b/arch/arm/boot/dts/omap4-sdp.dts
> @@ -113,6 +113,76 @@
>                         "DMic", "Digital Mic",
>                         "Digital Mic", "Digital Mic1 Bias";
>         };
> +
> +       keypad {
> +               keypad,num-rows = <8>;
> +               keypad,num-columns = <8>;
> +               linux,keymap = < 0x00000012
> +                       0x00010013
> +                       0x00020014
> +                       0x00030066
> +                       0x0004003f
> +                       0x000500f0
> +                       0x00060017
> +                       0x0007002a
> +                       0x01000020
> +                       0x01010021
> +                       0x01020022
> +                       0x010300e7
> +                       0x01040040
> +                       0x010500f0
> +                       0x01060025
> +                       0x0107001c
> +                       0x0200002d
> +                       0x0201002e
> +                       0x0202002f
> +                       0x0203006b
> +                       0x02040041
> +                       0x020500f0
> +                       0x02060034
> +                       0x0207003a
> +                       0x0300002c
> +                       0x0301004e
> +                       0x03020030
> +                       0x0303003b
> +                       0x03040042
> +                       0x030500f0
> +                       0x03060018
> +                       0x03070039
> +                       0x04000011
> +                       0x04010015
> +                       0x04020016
> +                       0x0403003c
> +                       0x04040073
> +                       0x040500f0
> +                       0x04060026
> +                       0x04070069
> +                       0x0500001f
> +                       0x05010023
> +                       0x05020024
> +                       0x0503003d
> +                       0x05040043
> +                       0x05050072
> +                       0x05060032
> +                       0x0507006a
> +                       0x06000010
> +                       0x0601001e
> +                       0x06020031
> +                       0x0603009e
> +                       0x0604000e
> +                       0x060500f0
> +                       0x06060019
> +                       0x06070067
> +                       0x07000094
> +                       0x07010095
> +                       0x070200ca
> +                       0x070300cb
> +                       0x0704003e
> +                       0x070500f0
> +                       0x07060160
> +                       0x0707006c >;
> +               linux,input-no-autorepeat;
> +       };
>  };
>
>  &i2c1 {
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 04cbbcb..e78a1f1 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -296,4 +296,9 @@
>                         ti,hwmods = "dmic";
>                 };
>         };
> +
> +       keypad {
> +               compatible = "ti,omap4-keypad";
> +               ti,hwmods = "kbd";
> +       };
>  };
> --
> 1.7.1
>
Any more comments on this patch?

~Sourav


From thierry.reding at avionic-design.de  Tue Aug 14 02:29:45 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 08:29:45 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
Message-ID: <20120814062945.GD16181@avionic-0098.mockup.avionic-design.de>

On Mon, Aug 13, 2012 at 04:18:16PM -0700, Bjorn Helgaas wrote:
> On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> > On 08/13/2012 11:40 AM, Thierry Reding wrote:
> >> On Mon, Aug 06, 2012 at 01:42:21PM -0600, Stephen Warren wrote:
> >>> On 07/26/2012 01:55 PM, Thierry Reding wrote:
> >>>> This patch series adds support for device tree based probing of
> >>>> the PCIe controller found on Tegra SoCs.
> >>>
> >>> Thierry, I just tested all Tegra boards in v3.6-rc1, and noticed
> >>> that PCIe doesn't work on TrimSlice when booting use device tree.
> >>> I think I found the cause, and I can't see why the same problem
> >>> doesn't affect this series. Perhaps you can enlighten me?
> > ...
> >>> PCI: Device 0000:01:00.0 not available because of resource
> >>> collisions
> > ...
> >> I've looked into this a bit, and it seems like ARM is using an
> >> open- coded version of the pci_enable_resources() function here,
> >> with the only difference being the unconditional enabling of both
> >> I/O and memory- mapped access for bridges. On Tegra there is
> >> already a PCI fixup to do this, so pci_enable_resources() can be
> >> used as-is.
> 
> I'd prefer that bridge I/O & memory access enabling be done in a
> mainline path, not in a fixup.  Fixups are intended for working around
> defects in specific devices, not for the normal path.  I know various
> architectures have fixups that are used in the normal path, but I've
> been working on eliminating them.

I understand. Perhaps it should be added to the pci_enable_resources()
function?

> > The patch did alter the behavior a little for TrimSlice, but didn't
> > solve the problem. The old error messages:
> >
> >> [    2.173971] PCI: Device 0000:01:00.0 not available because of resource collisions
> >> [    2.181453] r8169 0000:01:00.0: (unregistered net_device): enable failure
> >> [    2.188254] r8169: probe of 0000:01:00.0 failed with error -22
> >
> > Were replaced with the following with your patch:
> >
> >> [    2.174010] r8169 0000:01:00.0: device not available (can't reserve [io  0x0000-0x00ff])
> >> [    2.182098] r8169 0000:01:00.0: (unregistered net_device): enable failure
> >> [    2.188900] r8169: probe of 0000:01:00.0 failed with error -22
> >
> > This message appears from drivers/pci/setup-res.c pci_enable_resources()
> > due to:
> >
> >>               if (!r->parent) {
> >>                       dev_err(&dev->dev, "device not available "
> >>                               "(can't reserve %pR)\n", r);
> >>                       return -EINVAL;
> >>               }
> >
> > That check doesn't appear in ARM's custom pcibios_enable_device().
> > Disabling that check yields:
> >
> >> [    2.174192] r8169 0000:01:00.0: enabling device (0140 -> 0143)
> >> [    2.180041] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> >> [    2.188386] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> >> [    2.196140] r8169: probe of 0000:01:00.0 failed with error -16
> >
> > I think that's because the pci_dev's resources are initially assigned
> > PCI-aperture-relative addresses, and then these are later patched up to
> > take account of where the aperture is mapped into the CPU's address space.
> 
> We definitely shouldn't be calling the driver probe routine before the
> device BARs are assigned.
> 
> > Boot log using board files:
> >
> >> [    1.146145] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> >> [    1.151745] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> >> [    1.159007] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> >> [    1.166270] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> > ...
> >> [    1.217829] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> >> [    1.225264] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> >> [    1.233236] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> >> [    1.241206] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> > ... (I added some extra printks:)
> >> [    1.488007] r8169 0000:01:00.0: BAR 0: requesting [io  0x1000-0x10ff]
> >> [    1.501483] r8169 0000:01:00.0: BAR 2: requesting [mem 0xa0024000-0xa0024fff 64bit pref]
> >> [    1.516611] r8169 0000:01:00.0: BAR 4: requesting [mem 0xa0020000-0xa0023fff 64bit pref]
> >
> > whereas for a device tree boot:
> >
> > (same):
> >> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> >> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> >> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> >> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> > ... (request region happens early)
> >> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
> >> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
> >> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> >> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> > ... (same, just happens too late)
> >> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> >> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> >> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> >> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> >
> > I suspect this is all still related to the PCI devices themselves being
> > probed much earlier in the overall PCI initialization sequence when the
> > PCI controller is probed later in the boot sequence, whereas PCI device
> > probe is deferred until the overall PCI initialization sequence is
> > complete if the PCI controller is probed very early in the boot sequence.
> 
> I don't know what to apply your patches to (they don't apply cleanly
> to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
> like you might be calling pci_bus_add_devices() before
> pci_bus_assign_resource(), which isn't going to work.

The patch was on top of this series, which in turn is based on -next.
However the patch doesn't actually change anything in the ordering of
the initialization sequence, it just replaces the ARM implementation
of pcibios_enable_device() to reuse pci_enable_resources().

ARM's main PCI entry point, arch/arm/kernel/bios32.c:pci_common_init(),
does call the correct sequence: pci_bus_assign_resources() followed by
pci_bus_add_devices(), so the sequence looks correct. However, judging
by the logs Stephen posted, the BAR assignment is too late, after the
driver has been probed.

> I don't know what it means to probe PCI devices before probing the PCI
> controller (the host bridge) -- that shouldn't happen either.  In
> order to probe PCI devices, we have to first know about the host
> bridge so we know how to do config accesses and what the bridge
> apertures are.

Right. I don't think this can happen. If the bridge hasn't been probed,
then the devices shouldn't be there anyway.

Thierry
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From nsekhar at ti.com  Tue Aug 14 02:30:17 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue, 14 Aug 2012 12:00:17 +0530
Subject: [PATCH] arm:davinci: clk - migrate to new common clock API
In-Reply-To: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
Message-ID: <5029F079.8010901@ti.com>


Hi Murali,

On 8/2/2012 10:23 PM, Murali Karicheri wrote:
> As a first step towards migrating davinci platforms to use common clock
> framework, replace all instances of clk_enable() with clk_prepare_enable()
> and clk_disable() with clk_disable_unprepare(). Until the platform is
> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
> adds a might_sleep() call and would work without any issues.
> 
> This will make it easy later to switch to common clk based implementation
> of clk driver from DaVinci specific driver.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>

Queuing this patch for v3.7. The subject line should have ARM in
capitals for consistency. Also, you are not really migrating to new API
in this patch - just preparing for migration so I prefer:

"ARM: davinci: convert platform code to use clk_prepare/clk_unprepare"

I will make this change while committing.

Thanks,
Sekhar


From shawn.guo at linaro.org  Tue Aug 14 02:46:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 14:46:16 +0800
Subject: How to define gpio irq with device tree
In-Reply-To: <5029E646.5090900@gmail.com>
References: <5024FF03.1070805@de.bosch.com>
 <20120814041841.GA30782@S2101-09.ap.freescale.net>
 <5029E646.5090900@gmail.com>
Message-ID: <20120814064614.GA2734@S2101-09.ap.freescale.net>

On Tue, Aug 14, 2012 at 01:46:46PM +0800, Hui Wang wrote:
> I generated a similar patch on the last week, only the linux-input
> part. please refer to https://patchwork.kernel.org/patch/1293451/
> 
Ok.  But can you rename property "irq-gpio" to "wakeup-gpios"?
Firstly, the idiom of gpio naming in DT is *-gpios, even though
most of time, it could be just one gpio.  Secondly, as the pin is
accessed as a gpio only in egalax_wake_up_device for waking up the
device, "wakeup-gpios" sounds better?

-- 
Regards,
Shawn



From jason77.wang at gmail.com  Tue Aug 14 02:54:27 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Tue, 14 Aug 2012 14:54:27 +0800
Subject: How to define gpio irq with device tree
In-Reply-To: <20120814064614.GA2734@S2101-09.ap.freescale.net>
References: <5024FF03.1070805@de.bosch.com>
 <20120814041841.GA30782@S2101-09.ap.freescale.net>
 <5029E646.5090900@gmail.com>
 <20120814064614.GA2734@S2101-09.ap.freescale.net>
Message-ID: <5029F623.7070806@gmail.com>

Shawn Guo wrote:
> On Tue, Aug 14, 2012 at 01:46:46PM +0800, Hui Wang wrote:
>   
>> I generated a similar patch on the last week, only the linux-input
>> part. please refer to https://patchwork.kernel.org/patch/1293451/
>>
>>     
> Ok.  But can you rename property "irq-gpio" to "wakeup-gpios"?
> Firstly, the idiom of gpio naming in DT is *-gpios, even though
> most of time, it could be just one gpio.  Secondly, as the pin is
> accessed as a gpio only in egalax_wake_up_device for waking up the
> device, "wakeup-gpios" sounds better?
>
>   
Both accepted.

Thanks,
Hui.



From anilkumar at ti.com  Tue Aug 14 02:55:54 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 14 Aug 2012 06:55:54 +0000
Subject: [PATCH] arm/dts: AM33XX: Set the default status of module to
 "disabled" state
In-Reply-To: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>
References: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA121C9@DBDE01.ent.ti.com>

Hi Vaibhav,

On Mon, Aug 06, 2012 at 16:59:04, Hiremath, Vaibhav wrote:
> Ideally in common SoC dtsi file we should set all modules
> to "disabled" state and it should get enabled in respective
> EVM/Board dts file as per usage.
> 
> This patch sets default status of all modules to "disabled"
> state in am33xx.dtsi file, and as per board requirement, enabled
> in board dts file (like, bone, evm, etc...).
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Arnd Bergmann <arnd at arndb.de>
> CC: Tony Lindgren <tony at atomide.com>
> ---
> This patch is tested on BeagleBone platform.
> 
>  arch/arm/boot/dts/am335x-bone.dts |    6 ++++++
>  arch/arm/boot/dts/am335x-evm.dts  |    6 ++++++
>  arch/arm/boot/dts/am33xx.dtsi     |    9 +++++++++
>  3 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
> index a9af4db..df672b4 100644
> --- a/arch/arm/boot/dts/am335x-bone.dts
> +++ b/arch/arm/boot/dts/am335x-bone.dts
> @@ -17,4 +17,10 @@
>  		device_type = "memory";
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
> +
> +	ocp {
> +		uart1: serial at 44E09000 {
> +			       status = "okay";
> +		       };

Minor change, correct indentation here.

> +	};
>  };
> diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> index d6a97d9..00bbae8 100644
> --- a/arch/arm/boot/dts/am335x-evm.dts
> +++ b/arch/arm/boot/dts/am335x-evm.dts
> @@ -17,4 +17,10 @@
>  		device_type = "memory";
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
> +
> +	ocp {
> +		uart1: serial at 44E09000 {
> +			       status = "okay";
> +		       };

ditto

Regards
AnilKumar


From dong.aisheng at linaro.org  Tue Aug 14 03:20:42 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Tue, 14 Aug 2012 15:20:42 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
Message-ID: <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>

On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
> I have a minor nit; while renumbering the pinctrl definitions is
> laudable and device trees can match, there are 16 other pin controls
> below EIM_D16 - this makes the start of the IOMUXC pin definitions
> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
> (pin_id*4)).
>
What do you mean of this value calculated?
Pin id or pin register(mux or config) offset?
This is for mx51, right? then why 0x300?

> While this works, it's fine, but it would be more reasonable/correct
> to number pin indices from the first configurable pad and not by a
Yes, the data is originally get from:
arch/arm/plat-mxc/include/mach/iomux-mx51.h
So i just followed that sequence to index pin id and currently it
seems i didn't see
any big problem using this way.

> hardcoded magic offset into the base. The EIM_DA* pins below the
> current EIM_D16 are only configurable as CoreSight trace signals but
> it would save trouble later if anyone wanted to use these for example
> on a prototype board configured as those trace pads if they didn't
> have to renumber all the pins again. Nobody currently uses them in the
> tree but it makes more sense to me to count from the first
> configurable pad, than the first currently-used-in-the-tree
> configurable pad.
What trouble do you mean?
Those pins, EIM_DA*, are already defined but just on a different pin id.
Can't user use it in this way?

>
> Therefore I propose;
>
> * add MX51_PAD_EIM_DA0 through DA15 as index 0-15 (same for any
> differences in other i.MX etc.)
Hmm, as i said above, those pins are already defined.
See:
        MX51_PAD_SD1_DATA0 = 209,
        MX51_PAD_EIM_DA0 = 210,
        MX51_PAD_EIM_DA1 = 211,
        MX51_PAD_EIM_DA2 = 212,
        MX51_PAD_EIM_DA3 = 213,

> * move all the pin indices currently defined up by 16 for MX51 (same for above)
> * _then_ renumber the current device trees..
>
I did not quite understand, remove other pin ids up by 16? why?

> That way churn is minimized in the future and we don't end up changing
> trees and definitions again in the future in the event that someone
> DOES want to use those pads in a shippable product with mainline Linux
> support (and sees fit to enable TPIU_TRACE_EN for some reason and has
> the hardware to use it).
>
Why we may want to change the definitions again?
Since we already have those pins EIM_DA* defined, it looks to me user could use
it, the only difference is the id is different, i still can't see any
trouble to use it
Can you help detail a bit more if any trouble?

Regards
Dong Aisheng


From richard.genoud at gmail.com  Tue Aug 14 03:24:14 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 09:24:14 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <20120814023758.GC8836@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjPGcnOGh9iMxKUH1FA6rHBcuOzgR_A+wkbFWYkazQPxw@mail.gmail.com>
 <20120814023758.GC8836@game.jcrosoft.org>
Message-ID: <CACQ1gAiDxMds_YrOw5zYRvvMqysERi=uRbRJL+2Cf1U7uYUD+Q@mail.gmail.com>

2012/8/14 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> no pinctrl MUST be forced as we provide pinctrl dummies
> which will provide dummy config so not break
>
> and if you want the gpio you need to enable the pinctrl on at91 otherwise you
> not have it we can force PINCRTL_AT91 on DT but now the pinctrl need to always
> be enabled
ok, so I think it's better to force PINCTRL_AT91 :
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..178a619 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -352,6 +352,7 @@ config ARCH_AT91
 	select CLKDEV_LOOKUP
 	select IRQ_DOMAIN
 	select NEED_MACH_IO_H if PCCARD
+	select PINCTRL
+	select PINCTRL_AT91
 	help
 	  This enables support for systems based on Atmel
 	  AT91RM9200 and AT91SAM9* processors.
This way, older configurations will not break by selecting by default
only PINCTRL and not PINCTRL_AT91.

>>
>> I tested it with a at91sam9g35-ek board, and it hangs before the dbgu
>> line is configured.
>> ( with at91_dt_defconfig and at91sam9g35ek.dts )
> did you update you dtb before booting?
I used the one provided with your patch:
git checkout linux-at91/j/pinctrl
ARCH=arm make clean
ARCH=arm make at91_dt_defconfig
ARCH=arm make -k -j8 zImage
./scripts/dtc/dtc -I dts -O dtb arch/arm/boot/dts/at91sam9g35ek.dts -o
at91sam9g35ek.dtb
cat arch/arm/boot/zImage at91sam9g35ek.dtb > zImage.dtb
./scripts/mkuboot.sh -A arm -O linux -C none  -T kernel -a 0x20008000
-e 0x20008000 -n 'Linux-3.6-rc1+pinctrl' -d zImage.dtb uImage.bin

and I've got nothing from the kernel:
Uncompressing Linux... done, booting the kernel.

As the pinmux is still already done by the bootloader, I tried to
suppress the lines:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
in the DTS, but it's the same.

But the config is ok with 3.6-rc1:
git checkout v3.6-rc1
ARCH=arm make clean
ARCH=arm make -k -j8 zImage
cat arch/arm/boot/zImage at91sam9g35ek.dtb > zImage.dtb # it's the DTB
build previously
./scripts/mkuboot.sh -A arm -O linux -C none  -T kernel -a 0x20008000
-e 0x20008000 -n 'Linux-3.6-rc1' -d zImage.dtb uImage.bin
Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0
Linux version 3.6.0-rc1 (rgenoud at lnx-rg) (gcc version 4.5.3 (Buildroot
2012.05) ) #525 Tue Aug 14 09:07:43 CEST 2012
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
[...]

>
> Best Regards,
> J.
Best regads.
Richard.

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From dong.aisheng at linaro.org  Tue Aug 14 03:30:40 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Tue, 14 Aug 2012 15:30:40 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <502954D2.908@boundarydevices.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <502954D2.908@boundarydevices.com>
Message-ID: <CAP1dx+wm=Lj6WXWTiRk3JfqAomr8_mfjZpmToht2bb4paEYXjQ@mail.gmail.com>

On 14 August 2012 03:26, Troy Kisky <troy.kisky at boundarydevices.com> wrote:
> On 8/13/2012 7:47 AM, Shawn Guo wrote:
>>
>> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
>> pinctrl drivers number pad from 1.  It causes problem/confusion when
>> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>>
>> Change imx51_pads and imx53_pads numbering start from 0.
>>
>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>> ---
>>   drivers/pinctrl/pinctrl-imx51.c |  490
>> +++++++++++++++++++-------------------
>>   drivers/pinctrl/pinctrl-imx53.c |  402 ++++++++++++++++----------------
>>   2 files changed, 446 insertions(+), 446 deletions(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-imx51.c
>> b/drivers/pinctrl/pinctrl-imx51.c
>> index 9fd0216..fb84689 100644
>> --- a/drivers/pinctrl/pinctrl-imx51.c
>> +++ b/drivers/pinctrl/pinctrl-imx51.c
>> @@ -23,251 +23,251 @@
>>   #include "pinctrl-imx.h"
>>     enum imx51_pads {
>> -       MX51_PAD_EIM_D16 = 1,
>> -       MX51_PAD_EIM_D17 = 2,
...
>> +       MX53_PAD_GPIO_19 = 0,
>> +       MX53_PAD_KEY_COL0 = 1,
>
>
> Why not skip the = xx altogether??  The enum will auto-increment.
Personally i'd like to keep it.
The reason is that pin id is basic property of a pin per pinctrl
subsystem's design
so explicitly define it looks more clear to me and i'm not sure but
it's possible that
the pin id may be used in device tree in the future(maybe some other
soc already uses it),
And defining it has no big harming.

Regards
Dong Aisheng


From hvaibhav at ti.com  Tue Aug 14 03:37:32 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Tue, 14 Aug 2012 07:37:32 +0000
Subject: [PATCH] arm/dts: AM33XX: Set the default status of module to
 "disabled" state
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA121C9@DBDE01.ent.ti.com>
References: <1344252544-26130-1-git-send-email-hvaibhav@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA121C9@DBDE01.ent.ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA8E243@DBDE01.ent.ti.com>

On Tue, Aug 14, 2012 at 12:25:54, AnilKumar, Chimata wrote:
> Hi Vaibhav,
> 
> On Mon, Aug 06, 2012 at 16:59:04, Hiremath, Vaibhav wrote:
> > Ideally in common SoC dtsi file we should set all modules
> > to "disabled" state and it should get enabled in respective
> > EVM/Board dts file as per usage.
> > 
> > This patch sets default status of all modules to "disabled"
> > state in am33xx.dtsi file, and as per board requirement, enabled
> > in board dts file (like, bone, evm, etc...).
> > 
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > CC: Tony Lindgren <tony at atomide.com>
> > ---
> > This patch is tested on BeagleBone platform.
> > 
> >  arch/arm/boot/dts/am335x-bone.dts |    6 ++++++
> >  arch/arm/boot/dts/am335x-evm.dts  |    6 ++++++
> >  arch/arm/boot/dts/am33xx.dtsi     |    9 +++++++++
> >  3 files changed, 21 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
> > index a9af4db..df672b4 100644
> > --- a/arch/arm/boot/dts/am335x-bone.dts
> > +++ b/arch/arm/boot/dts/am335x-bone.dts
> > @@ -17,4 +17,10 @@
> >  		device_type = "memory";
> >  		reg = <0x80000000 0x10000000>; /* 256 MB */
> >  	};
> > +
> > +	ocp {
> > +		uart1: serial at 44E09000 {
> > +			       status = "okay";
> > +		       };
> 
> Minor change, correct indentation here.
> 

Thanks Anil for pointing me to this, my vi rules screwed up here,
I will correct it and send next version with Ack-by Arnd.

Thanks,
Vaibhav

> > +	};
> >  };
> > diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> > index d6a97d9..00bbae8 100644
> > --- a/arch/arm/boot/dts/am335x-evm.dts
> > +++ b/arch/arm/boot/dts/am335x-evm.dts
> > @@ -17,4 +17,10 @@
> >  		device_type = "memory";
> >  		reg = <0x80000000 0x10000000>; /* 256 MB */
> >  	};
> > +
> > +	ocp {
> > +		uart1: serial at 44E09000 {
> > +			       status = "okay";
> > +		       };
> 
> ditto
> 
> Regards
> AnilKumar
> 



From josephl at nvidia.com  Tue Aug 14 04:07:19 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:19 +0800
Subject: [PATCH 0/5] ARM: tegra: add CPU hotplug support
Message-ID: <1344931644-3927-1-git-send-email-josephl@nvidia.com>

This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.

The first 3 patches make the CPU clock and reset control be a module and
the abstraction APIs for TegraXX SoCs. And clean up some codes for later
usage. Then add CPU hotplug support for Tegra20 and Tegra30.

Verified on Seaboard(Tegra20) and Cardhu(Tegra30)

Joseph Lo (5):
  ARM: tegra: introduce tegra_cpu_car_ops structures
  ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
  ARM: tegra: clean up the common assembly macros into sleep.h
  ARM: tegra30: add CPU hotplug support
  ARM: tegra20: add CPU hotplug support

 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/common.c              |    3 +
 arch/arm/mach-tegra/headsmp.S             |    6 +-
 arch/arm/mach-tegra/hotplug.c             |  118 ++++++++---------------------
 arch/arm/mach-tegra/platsmp.c             |   29 +------
 arch/arm/mach-tegra/sleep-t20.S           |   82 ++++++++++++++++++++
 arch/arm/mach-tegra/sleep-t30.S           |  107 ++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.S               |   33 +--------
 arch/arm/mach-tegra/sleep.h               |   80 +++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 +++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++
 15 files changed, 551 insertions(+), 147 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S
 create mode 100644 arch/arm/mach-tegra/sleep.h
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h



From josephl at nvidia.com  Tue Aug 14 04:07:20 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:20 +0800
Subject: [PATCH 1/5] ARM: tegra: introduce tegra_cpu_car_ops structures
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <1344931644-3927-2-git-send-email-josephl@nvidia.com>

The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 ++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++++++++++
 6 files changed, 238 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 632133f..fd82085 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -31,6 +31,10 @@
 
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 
 /*
  * Locking:
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index a1e0f8a..b073396 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -33,6 +33,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
 
 #define RST_DEVICES			0x004
 #define RST_DEVICES_SET			0x300
@@ -152,6 +153,14 @@
 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT	16
 #define PMC_BLINK_TIMER_DATA_OFF_MASK	0xffff
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 
@@ -1524,3 +1533,64 @@ struct clk_ops tegra_cdev_clk_ops = {
 	.disable = tegra20_cdev_clk_disable,
 	.recalc_rate = tegra20_cdev_recalc_rate,
 };
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg & ~CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	barrier();
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+	.wait_for_reset	= tegra20_wait_cpu_in_reset,
+	.put_in_reset	= tegra20_put_cpu_in_reset,
+	.out_of_reset	= tegra20_cpu_out_of_reset,
+	.enable_clock	= tegra20_enable_cpu_clock,
+	.disable_clock	= tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index b5c518e..56552f9 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "tegra2_emc.h"
 #include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
 
 /* Clock definitions */
 
@@ -1110,4 +1111,5 @@ void __init tegra2_init_clocks(void)
 	}
 
 	init_audio_sync_clock_mux();
+	tegra20_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index a9fa8ea..b2d0864 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -35,6 +35,7 @@
 
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY		100
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR	0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -2221,3 +2232,64 @@ struct clk_ops tegra_cml_clk_ops = {
 struct clk_ops tegra_pciex_clk_ops = {
 	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
+
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra30_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra30_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra30_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	writel(CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	reg = readl(reg_clk_base +
+		    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
+
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
+
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+	.wait_for_reset	= tegra30_wait_cpu_in_reset,
+	.put_in_reset	= tegra30_put_cpu_in_reset,
+	.out_of_reset	= tegra30_cpu_out_of_reset,
+	.enable_clock	= tegra30_enable_cpu_clock,
+	.disable_clock	= tegra30_disable_cpu_clock,
+};
+
+void __init tegra30_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index c924240..8252f88 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -32,6 +32,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
 
 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,		\
 		   _parent_names, _parents, _parent)		\
@@ -1367,4 +1368,6 @@ void __init tegra30_init_clocks(void)
 
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
 		tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+	tegra30_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 0000000..30d063a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *	keep waiting until the CPU in reset state
+ * put_in_reset:
+ *	put the CPU in reset state
+ * out_of_reset:
+ *	release the CPU from reset state
+ * enable_clock:
+ *	CPU clock un-gate
+ * disable_clock:
+ *	CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+	void (*wait_for_reset)(u32 cpu);
+	void (*put_in_reset)(u32 cpu);
+	void (*out_of_reset)(u32 cpu);
+	void (*enable_clock)(u32 cpu);
+	void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+		return;
+
+	tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+		return;
+
+	tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+		return;
+
+	tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+		return;
+
+	tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+		return;
+
+	tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
-- 
1.7.0.4



From josephl at nvidia.com  Tue Aug 14 04:07:21 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:21 +0800
Subject: [PATCH 2/5] ARM: tegra: replace the CPU CAR access code by
 tegra_cpu_car_ops
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <1344931644-3927-3-git-send-email-josephl@nvidia.com>

Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/platsmp.c |   29 +++++------------------------
 1 files changed, 5 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208db..96ed171 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
 
 extern void tegra_secondary_startup(void);
 
@@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
 	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu)	(0x1<<(8+cpu))
-#define CPU_RESET(cpu)	(0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
-
 	/* Enable the CPU clock. */
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	barrier();
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	tegra_enable_cpu_clock(cpu);
 
 	/* Clear flow controller CSR. */
 	flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
 	int ret, pwrgateid;
 	unsigned long timeout;
 
@@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
 	}
 
 	/* CPU partition is powered. Enable the CPU clock. */
-	writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	tegra_enable_cpu_clock(cpu);
 	udelay(10);
 
 	/* Remove I/O clamps. */
@@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * via the flow controller). This will have no effect on first boot
 	 * of the CPU since it should already be in reset.
 	 */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-	dmb();
+	tegra_put_cpu_in_reset(cpu);
 
 	/*
 	 * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		goto done;
 
 	/* Take the CPU out of reset. */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-	wmb();
+	tegra_cpu_out_of_reset(cpu);
 done:
 	return status;
 }
-- 
1.7.0.4



From josephl at nvidia.com  Tue Aug 14 04:07:22 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:22 +0800
Subject: [PATCH 3/5] ARM: tegra: clean up the common assembly macros into
 sleep.h
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <1344931644-3927-4-git-send-email-josephl@nvidia.com>

There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/headsmp.S |    6 +---
 arch/arm/mach-tegra/sleep.S   |   33 +-----------------------
 arch/arm/mach-tegra/sleep.h   |   56 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep.h

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c..6addc78 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 
 #define APB_MISC_GP_HIDREV	0x804
 #define PMC_SCRATCH41	0x140
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
 
-	.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-	.endm
-
         .section ".text.head", "ax"
 	__CPUINIT
 
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156..ea81554 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
+#include "sleep.h"
 
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-					+ IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x14
-	moveq	\rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x18
-	moveq	\rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-	mrc	p15, 0, \rd, c0, c0, 5
-	and	\rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 0000000..d0c7a8b
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x14
+	moveq	\rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x18
+	moveq	\rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+	mrc	p15, 0, \rd, c0, c0, 5
+	and	\rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+	movw	\reg, #:lower16:\val
+	movt	\reg, #:upper16:\val
+.endm
+#endif
+#endif
-- 
1.7.0.4



From josephl at nvidia.com  Tue Aug 14 04:07:24 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:24 +0800
Subject: [PATCH 5/5] ARM: tegra20: add CPU hotplug support
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <1344931644-3927-6-git-send-email-josephl@nvidia.com>

Hotplug function put CPU in offline or online mode at runtime.
When the CPU been put into offline, it was been clock gated. The
offline CPU can be power gated, when the remaining CPU goes into
LP2.

Based on the worked by:
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    1 +
 arch/arm/mach-tegra/hotplug.c   |    8 ++++
 arch/arm/mach-tegra/sleep-t20.S |   82 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |    3 +
 5 files changed, 95 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 211e279..959a429 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0652056..0560538 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -136,6 +136,7 @@ void __init tegra20_init_early(void)
 	tegra_init_cache(0x331, 0x441);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d72ed2b..1383180 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -56,6 +56,14 @@ int platform_cpu_disable(unsigned int cpu)
 	return cpu == 0 ? -EPERM : 0;
 }
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 extern void tegra30_hotplug_shutdown(void);
 void __init tegra30_hotplug_init(void)
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 0000000..a36ae41
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross at android.com>
+ *         Gary King <gking at nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Put this CPU down */
+	cpu_id	r0
+	bl	tegra20_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+	cmp	r0, #0
+	moveq	pc, lr			@ must not be called for CPU 0
+
+	cpu_to_halt_reg r1, r0
+	ldr	r3, =TEGRA_FLOW_CTRL_VIRT
+	mov	r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+	str	r2, [r3, r1]		@ put flow controller in wait event mode
+	ldr	r2, [r3, r1]
+	isb
+	dsb
+	movw	r1, 0x1011
+	mov	r1, r1, lsl r0
+	ldr	r3, =TEGRA_CLK_RESET_VIRT
+	str	r1, [r3, #0x340]	@ put slave CPU in reset
+	isb
+	dsb
+	cpu_id	r3
+	cmp	r3, r0
+	beq	.
+	mov	pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2ad9b6d..42236e1 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -23,6 +23,8 @@
 					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
 
 #ifdef __ASSEMBLY__
 /* returns the offset of the flow controller halt register for a cpu */
@@ -71,6 +73,7 @@
 .endm
 #else
 
+void tegra20_hotplug_init(void);
 void tegra30_hotplug_init(void);
 
 #endif
-- 
1.7.0.4



From josephl at nvidia.com  Tue Aug 14 04:07:23 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Tue, 14 Aug 2012 16:07:23 +0800
Subject: [PATCH 4/5] ARM: tegra30: add CPU hotplug support
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <1344931644-3927-5-git-send-email-josephl@nvidia.com>

Hotplug function put CPUs in offline or online state at runtime.
When the CPU been put in the offline state, it was been clock and
power gated. Except primary CPU other CPUs can be hotplugged.

Based on the work by:
Scott Williams <scwilliams at nvidia.com>
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    2 +
 arch/arm/mach-tegra/hotplug.c   |  110 +++++++++------------------------------
 arch/arm/mach-tegra/sleep-t30.S |  107 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |   21 +++++++
 5 files changed, 155 insertions(+), 86 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 060592a..211e279 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f3654f8..0652056 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -147,6 +148,7 @@ void __init tegra30_init_early(void)
 	tegra_init_cache(0x441, 0x551);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra30_hotplug_init();
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9dd..d72ed2b 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,94 +1,32 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
 
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
+#include "sleep.h"
+#include "tegra_cpu_car.h"
 
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
+static void (*tegra_hotplug_shutdown)(void);
 
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+int platform_cpu_kill(unsigned int cpu)
 {
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
+	cpu = cpu_logical_map(cpu);
 
-		/*if (pen_release == cpu) {*/
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		/*}*/
+	/* Clock gate the CPU */
+	tegra_wait_cpu_in_reset(cpu);
+	tegra_disable_cpu_clock(cpu);
 
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
 	return 1;
 }
 
@@ -99,22 +37,14 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-	int spurious = 0;
-
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
+	/* Flush the L1 data cache. */
+	flush_cache_all();
 
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
+	/* Shut down the current CPU. */
+	tegra_hotplug_shutdown();
 
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+	/* Should never return here. */
+	BUG();
 }
 
 int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,11 @@ int platform_cpu_disable(unsigned int cpu)
 	 */
 	return cpu == 0 ? -EPERM : 0;
 }
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 0000000..777d9ce
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Powergate this CPU */
+	mov	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	bl	tegra30_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+	cpu_id	r3
+	cmp	r3, #0
+	moveq	pc, lr		@ Must never be called for CPU 0
+
+	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
+	cpu_to_csr_reg r1, r3
+	add	r1, r1, r12	@ virtual CSR address for this CPU
+	cpu_to_halt_reg r2, r3
+	add	r2, r2, r12	@ virtual HALT_EVENTS address for this CPU
+
+	/*
+	 * Clear this CPU's "event" and "interrupt" flags and power gate
+	 * it when halting but not before it is in the "WFE" state.
+	 */
+	movw	r12, \
+		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+		FLOW_CTRL_CSR_ENABLE
+	mov	r4, #(1 << 4)
+	orr	r12, r12, r4, lsl r3
+	str	r12, [r1]
+
+	/* Halt this CPU. */
+	mov	r3, #0x400
+delay_1:
+	subs	r3, r3, #1			@ delay as a part of wfe war.
+	bge	delay_1;
+	cpsid	a				@ disable imprecise aborts.
+	ldr	r3, [r1]			@ read CSR
+	str	r3, [r1]			@ clear CSR
+	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	str	r3, [r2]
+	ldr	r0, [r2]
+	b	wfe_war
+
+__cpu_reset_again:
+	dsb
+	.align 5
+	wfe					@ CPU should be power gated here
+wfe_war:
+	b	__cpu_reset_again
+
+	/*
+	 * 38 nop's, which fills reset of wfe cache line and
+	 * 4 more cachelines with nop
+	 */
+	.rept 38
+	nop
+	.endr
+	b	.				@ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index d0c7a8b..2ad9b6d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -19,6 +19,8 @@
 
 #include <mach/iomap.h>
 
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
 
@@ -52,5 +54,24 @@
 	movw	\reg, #:lower16:\val
 	movt	\reg, #:upper16:\val
 .endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
+	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	isb
+	cpu_id	\tmp1
+	mov	\tmp1, \tmp1, lsl #2
+	mov	\tmp2, #0xf
+	mov	\tmp2, \tmp2, lsl \tmp1
+	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
+	dsb
+.endm
+#else
+
+void tegra30_hotplug_init(void);
+
 #endif
 #endif
-- 
1.7.0.4



From linus.walleij at linaro.org  Tue Aug 14 04:13:12 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:13:12 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZL6efwvUyW1+2j8253WRXm3WYyDUw8rN_o9QE=HER4wA@mail.gmail.com>

On Mon, Aug 13, 2012 at 4:47 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
> pinctrl drivers number pad from 1.  It causes problem/confusion when
> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>
> Change imx51_pads and imx53_pads numbering start from 0.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Looks like a good idea.

Since I just merged the imx53 driver which *again* start numbering on
1, can I have a patch that fixes that driver also?

Uwe, you OK with this?

Yours,
Linus Walleij


From shawn.guo at linaro.org  Tue Aug 14 04:15:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 16:15:56 +0800
Subject: [PATCH] ARM: imx6q: register fixed clocks in the common way
Message-ID: <1344932156-8275-1-git-send-email-shawn.guo@linaro.org>

With DT clock support in place, we can register fixed clocks in DT
standard way.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi  |   11 +++++++----
 arch/arm/mach-imx/clk-imx6q.c |   21 +++++++--------------
 2 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 3d3c64b..0052fe7 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -65,17 +65,20 @@
 		#size-cells = <0>;
 
 		ckil {
-			compatible = "fsl,imx-ckil", "fixed-clock";
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
 			clock-frequency = <32768>;
 		};
 
-		ckih1 {
-			compatible = "fsl,imx-ckih1", "fixed-clock";
+		ckih {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
 			clock-frequency = <0>;
 		};
 
 		osc {
-			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
 		};
 	};
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520..475bc93 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -162,27 +162,20 @@ static enum mx6q_clks const clks_init_on[] __initconst = {
 	mmdc_ch0_axi, rom,
 };
 
+static const struct of_device_id clk_match[] __initconst = {
+	{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{ /* sentinel */ }
+};
+
 int __init mx6q_clocks_init(void)
 {
 	struct device_node *np;
 	void __iomem *base;
 	int i, irq;
 
-	clk[dummy] = imx_clk_fixed("dummy", 0);
+	of_clk_init(clk_match);
 
-	/* retrieve the freqency of fixed clocks from device tree */
-	for_each_compatible_node(np, NULL, "fixed-clock") {
-		u32 rate;
-		if (of_property_read_u32(np, "clock-frequency", &rate))
-			continue;
-
-		if (of_device_is_compatible(np, "fsl,imx-ckil"))
-			clk[ckil] = imx_clk_fixed("ckil", rate);
-		else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-			clk[ckih] = imx_clk_fixed("ckih", rate);
-		else if (of_device_is_compatible(np, "fsl,imx-osc"))
-			clk[osc] = imx_clk_fixed("osc", rate);
-	}
+	clk[dummy] = imx_clk_fixed("dummy", 0);
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
 	base = of_iomap(np, 0);
-- 
1.7.5.4




From linus.walleij at linaro.org  Tue Aug 14 04:17:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:17:08 +0200
Subject: [PATCH 1/8] of/irq: Create stub for of_irq_find_parent when
 !CONFIG_OF
In-Reply-To: <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb2MKgaoknHcWjrQqXPr6dXRsPjDxCwzNvGahJ48wMzdA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> of_irq_find_parent is a handy function to use outside the confines of
> the Open Firmware subsystem. One such use-case is when the IRQ Domain
> wishes to find an IRQ domain for a given device node. Currently it can
> not take any notice of the 'interrupt-parent' property. Instead it
> just uses the first IRQ controller as it climbs the Device Tree. If
> we were to use this as a precursor the resultant controller is more
> likely to be correct.
>
> CC: Rob Herring <rob.herring at calxeda.com>
> CC: devicetree-discuss at lists.ozlabs.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This is clever.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:19:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:19:08 +0200
Subject: [PATCH 2/8] irqdomain: Take interrupt-parent property into
 account if specified
In-Reply-To: <1344527635-6163-3-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZMoisfUD_NSkVy2w-jZVUDGn0E8LmvKSWnJ0YRGZO-tQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> irq_find_host() currently ignores the 'interrupt-parent' property
> even if it's specified in the Device Tree. Meaning that a node can
> match to a domain in its hierarchy even if it doesn't belong to it.
> By searching for the parent first using of_irq_find_parent() we
> insist that the 'interrupt-parent' property is taken into account
> ensuring a greater chance of returning the correct domain.
>
> CC: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> CC: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This (with 1/8) is the right solution. Thanks, and I think
Mark may want to look at this too since I recognize he asked
you to work in this direction.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:19:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:19:43 +0200
Subject: [PATCH 3/8] ARM: ux500: Identify the PRCMU as an interrupt
 controller
In-Reply-To: <1344527635-6163-4-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYeo6jnVshj5n9kkBtj3ztxNUr-su6A9-ChQUqJaayhTg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> We're just about to provide the DB8500-PRCMU with its own IRQ domain,
> so that its subordinate drivers can use it as an interrupt controller.
> It's obligatory for all IRQ controllers to reference themselves as
> such from its own node in Device Tree. This patch does just that.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:20:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:20:36 +0200
Subject: [PATCH 4/8] ARM: ux500: Force AB8500 to use the GIC as its
 interrupt controller
In-Reply-To: <1344527635-6163-5-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbuXDAMF95V-X-rNdWnkm0maQFH1OM047=KdBrjm33duw@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It's understood that the AB8500 should be subordinate to the DB8500;
> however, the AB8500 uses the GIC as it's interrupt controller. If
> we do not specify which IRQ controller to use the default is to use
> the next encountered IRQ controller as we climb the tree. This would
> be the DB8500. This patch ensures the AB8500 makes use of the correct
> interrupt controller.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Tue Aug 14 04:20:47 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 14 Aug 2012 09:20:47 +0100
Subject: [PATCH v3 3/4] dmatest: add dmaengine_slave_config for DMA_MEMCPY
In-Reply-To: <1344917519-9505-4-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-4-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <20120814082047.GF18957@n2100.arm.linux.org.uk>

On Tue, Aug 14, 2012 at 12:11:58PM +0800, Zhangfei Gao wrote:
> Set direction to DMA_MEM_TO_MEM
> DMA driver may require such configure info

No, this is wrong.  By default, any channel being asked to do memcpy
should deal with the channel configuration itself and not require it
to be set - otherwise this breaks the async_tx API.

So consider that dma-test found a bug in your driver which needs fixing.


From linus.walleij at linaro.org  Tue Aug 14 04:22:01 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:22:01 +0200
Subject: [PATCH 6/8] mfd: Use interrupt-parent as IRQ controller if
 specified in DT
In-Reply-To: <1344527635-6163-7-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ9sVEM08HkZWnVCLt9kZ2NX-Fk+Jy_AZ65P3vSWk_UGQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Without this patch the default behaviour is to climb the Device
> Tree and use the first encountered interrupt controller. This
> does not take into account if a device node has specified to use
> a particular IRQ controller using the interrupt-parent property.
> This patch ensures that property is adhered to.
>
> CC: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Mark & Rob may want to check this out too.

Yours,
Linus Walleij


From shawn.guo at linaro.org  Tue Aug 14 04:22:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 14 Aug 2012 16:22:53 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CACRpkdZL6efwvUyW1+2j8253WRXm3WYyDUw8rN_o9QE=HER4wA@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CACRpkdZL6efwvUyW1+2j8253WRXm3WYyDUw8rN_o9QE=HER4wA@mail.gmail.com>
Message-ID: <CAAQ0ZWSuAguQwZkQzkUPqJF5ZBSc5Ekiq6mvtwvp98tuu5noLg@mail.gmail.com>

On 14 August 2012 16:13, Linus Walleij <linus.walleij at linaro.org> wrote:
> Since I just merged the imx53 driver which *again* start numbering on
> 1, can I have a patch that fixes that driver also?
>
What Uwe added is imx35 (vs. imx53 :) driver, which already numbers pad from 0.

Regards,
Shawn

> Uwe, you OK with this?
>


From linus.walleij at linaro.org  Tue Aug 14 04:25:59 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:25:59 +0200
Subject: [PATCH 7/8] mfd: Use the AB8500's IRQ domain to convert hwirq to
 virq
In-Reply-To: <1344527635-6163-8-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbYP3FNNC1nR9c6aYRsqpeaBJjQO4GKeuk05NUBkNcRpg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Before the AB8500 had its own IRQ domain, the IRQ handler would take
> the fired local IRQ (hwirq) and add it to the irq_base to convert it
> to an IRQ number which Linux would understand (virq). However, the
> IRQ base is not always used anymore since we can make use of Linear
> domains. It's better to use the AB8500 hwirq -> virq mapping helper
> function to convert them instead. That's what we do here.
>
> CC: Samuel Ortiz <sameo at linux.intel.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This looks better that what was in there before so
Acked-by: Linus Walleij <linus.walleij at linaro.org>

However:

> @@ -501,8 +501,9 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
>                 do {
>                         int bit = __ffs(value);
>                         int line = i * 8 + bit;
> +                       int virq = ab8500_irq_get_virq(ab8500, line);
>
> -                       handle_nested_irq(ab8500->irq_base + line);
> +                       handle_nested_irq(virq);
>                         value &= ~(1 << bit);

Still this ab8500_irq_get_virq() business. But is this a static local function
in the ab8500-core.c now? Then it's fine, it's the kernel-wide interface
that is the problem.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:29:14 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:29:14 +0200
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> +static struct irq_domain *db8500_irq_domain;

So this is a good idea.

> +int db8500_irq_get_virq(int irq);

And I'm sceptic about this business. Why isn't this physical-to virtual
mapping business confined to the core MFD driver? But enlighten me.

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Tue Aug 14 04:30:26 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 14 Aug 2012 09:30:26 +0100
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <20120814083026.GG18957@n2100.arm.linux.org.uk>

Please consider looking at the virtual dma channel support, which I've
recently added.  This removes the burden of managing the descriptor
lists from the driver, deals with the workqueues for completing
descriptors, etc.

All you need to do is to build the descriptors for the DMA operation,
manage the scheduling of virtual channels onto physical channels,
calculate the position of DMA, and starting off and handling the DMA
hardware.

"virtual dma channel support" is probably something of a misnomer though;
it can also be used for situations where there's a 1:1 binding between
virtual and physical dma channels (iow, no virtual channels at all.)


From linus.walleij at linaro.org  Tue Aug 14 04:31:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:31:08 +0200
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> There was a plan to place ab8500_irq_get_virq() calls in each AB8500
> child device prior to requesting an IRQ, but as we're no longer using
> Device Tree to collect our IRQ numbers, it's actually better to allow
> the core to do this during device registration time. So the IRQ number
> we pull from its resource has already been converted to a virtual IRQ.
>
> CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
> CC: linux-input at vger.kernel.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This is looking good, I guess you need all patches to go in at the
same time so Dmitry's ACK is required.

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

BTW: this makes me suspect that the public ab8500_irq_get_virq()
interface can be *deleted* and the function made static in the
AB8500 driver, right?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:32:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:32:02 +0200
Subject: [rtc-linux] [PATCH 1/1] drivers/rtc/rtc-ab8500.c: Revoke Device
 Tree enablement
In-Reply-To: <1344527828-6283-3-git-send-email-lee.jones@linaro.org>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
 <1344527828-6283-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZa-72QogrZ-P5jbDHTTX64babZo3ydjzfgC-4LWUBfMg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:

> All AB8500 devices are now registered via MFD core, so Device Tree
> capability is no longer required for probing. Here we pull the DT
> match table to ensure we're no longer probed during Device Tree
> start-up.
>
> CC: Alessandro Zummo <a.zummo at towertech.it>
> CC: rtc-linux at googlegroups.com
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:32:38 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:32:38 +0200
Subject: [PATCH 1/1] ARM: ux500: Match Power-On-Key MFD and DTS compatible
 strings
In-Reply-To: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb2O4wTei75dnDnszzg7u1JMJZkkH3xs_34rVaQxW1zYw@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The compatible string found in the Power-On-Key's MFD cell matches
> the device name provided in the driver. Keeping this naming convention
> seems like a good idea, so we're changing the one found in the DTS
> file to match.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:33:09 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:33:09 +0200
Subject: [PATCH 1/1] ARM: ux500: Remove unused snowball_of_platform_devs
 struct
In-Reply-To: <1344527828-6283-2-git-send-email-lee.jones@linaro.org>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
 <1344527828-6283-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbaXHqPUDYFHWgMwu-g3kHyZsHWvGq3_dR_wjQddgeUoA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This was left over during a recent clean-up which removed Device Tree
> helper structs. There is no longer a requirement for it, so we can just
> remove it.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:38:41 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:38:41 +0200
Subject: [PATCH 01/22] ARM: ux500: Fix merge error, no matching driver
 name for 'snd_soc_u8500'
In-Reply-To: <1344527268-5964-2-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb1CeoLa-+FAKRFwbXVbup_KFM_WTMrKUEGXtXqogZhWg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The platform attempts to register platform device 'snd_soc_u8500'
> which doesn't actually exist. Here we change the reference to the
> correct one 'snd_soc_mop500'.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to fixes. I will send this upstream for the -rc:s.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:40:09 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:40:09 +0200
Subject: [PATCH 02/22] ARM: ux500: Ensure probing of Audio devices when
 Device Tree is enabled
In-Reply-To: <1344527268-5964-3-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ9XBTx_MQ9eDN_wOpeAXVt2REa7yr4ngd-0MDhsvZN3w@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Previous attempts to add platform probing of the Audio related devices
> only call from non-DT initialisation functions. This patch extends that
> functionality to the Device Tree related ones too.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to ux500 fixes. Will send upstream for the -rc:s.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:40:46 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:40:46 +0200
Subject: [PATCH 03/22] ASoC: ab8500: Inform SoC Core that we have our own
 I/O arrangements
In-Reply-To: <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY9L_-RwV6xWV9ta+qubWce0ZH0+FXaCHkeaWRvSYUhKQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> If codec->control_data is not populated SoC Core assumes we want to
> use regmap, which fails catastrophically, as we don't have one:
>
> Unable to handle kernel NULL pointer dereference at virtual address 00000080
> pgd = c0004000
> [00000080] *pgd=00000000
> Internal error: Oops: 17 [#1] PREEMPT SMP ARM
> Modules linked in:
> CPU: 1    Not tainted  (3.5.0-rc6-00884-g0b2419e-dirty #130)
> PC is at regmap_read+0x10/0x5c
> LR is at hw_read+0x80/0x90
> pc : [<c01a91b8>]    lr : [<c0216804>]    psr: 60000013
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

No clue on this one, have to refer to Mark...

Linus Walleij


From tony at atomide.com  Tue Aug 14 04:43:14 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 14 Aug 2012 01:43:14 -0700
Subject: [GIT PULL] omap fixes for v3.6-rc1
Message-ID: <20120814084314.GH11011@atomide.com>

Hi Arnd & Olof,

Here are some omap fixes, these are probably too late for -rc1,
we're fine getting them in for -rc2 as well.

Regards,

Tony


The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-fixes-for-v3.6-rc1

for you to fetch changes up to c5491d1ae1946d394389b83b31b87708e86dc4cf:

  ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*() (2012-08-13 06:23:16 -0700)

----------------------------------------------------------------
Omap fixes for issues noted during the merge window, mostly
PM related.

----------------------------------------------------------------
Afzal Mohammed (1):
      arm/dts: Fix am33xx wdt node

Domenico Andreoli (1):
      OMAP: remove unused parameter arch_id from uncompress.h

Igor Grinberg (1):
      Revert "ARM: OMAP3530evm: set pendown_state and debounce time for ads7846"

Jan Luebbe (1):
      omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX are selected

Javier Martinez Canillas (1):
      ARM: OMAP3: igep0020: set GPIO mode for mux mcspi1_cs2 pin

Jon Hunter (1):
      ARM: OMAP2+: Fix dmtimer set source clock failure

Kevin Hilman (2):
      ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled
      Revert "ARM: OMAP3: PM: call pre/post transition per powerdomain"

Michael Jones (1):
      omap2: mux: remove comment for nonexistent member

Rajendra Nayak (3):
      arm/dts: Mark vcxio, v2v1 and v1v8 regulators as always on
      cpufreq: OMAP: Handle missing frequency table on SMP systems
      ARM: OMAP4: Register the OPP table only for 4430 device

Santosh Shilimkar (2):
      OMAP2+: Fix random config build break with !ARM_CPU_SUSPEND
      ARM: OMAP4: sleep: Save the complete used register stack frame

Timo Kokkonen (1):
      ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*()

Tony Lindgren (2):
      Merge branch 'for_3.6/fixes/ads7846-2' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes
      Merge branch 'for_3.6/fixes/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes

Vaibhav Hiremath (1):
      ARM: OMAP2+: cpu: Add am33xx device under cpu_class_is_omap2

 arch/arm/boot/dts/am33xx.dtsi                |    5 +++++
 arch/arm/boot/dts/twl6030.dtsi               |    3 +++
 arch/arm/mach-omap2/Kconfig                  |    1 +
 arch/arm/mach-omap2/board-igep0020.c         |    2 ++
 arch/arm/mach-omap2/board-omap3evm.c         |    1 +
 arch/arm/mach-omap2/common-board-devices.c   |   11 -----------
 arch/arm/mach-omap2/common-board-devices.h   |    1 -
 arch/arm/mach-omap2/mux.h                    |    1 -
 arch/arm/mach-omap2/opp4xxx_data.c           |    2 +-
 arch/arm/mach-omap2/pm34xx.c                 |   19 ++++---------------
 arch/arm/mach-omap2/sleep44xx.S              |    8 ++++++--
 arch/arm/mach-omap2/twl-common.c             |    1 +
 arch/arm/plat-omap/dmtimer.c                 |    6 +++---
 arch/arm/plat-omap/include/plat/cpu.h        |    3 ++-
 arch/arm/plat-omap/include/plat/multi.h      |    9 +++++++++
 arch/arm/plat-omap/include/plat/uncompress.h |    4 +---
 drivers/cpufreq/omap-cpufreq.c               |    4 +++-
 17 files changed, 42 insertions(+), 39 deletions(-)


From Sudeep.KarkadaNagesha at arm.com  Tue Aug 14 04:43:12 2012
From: Sudeep.KarkadaNagesha at arm.com (Sudeep KarkadaNagesha)
Date: Tue, 14 Aug 2012 09:43:12 +0100
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <50297838.7080208@broadcom.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
 <50297838.7080208@broadcom.com>
Message-ID: <502A0FA0.3010602@arm.com>

Hi Jiandong,

On 13/08/12 22:57, Jiandong Zheng wrote:
> On 8/10/2012 10:36 AM, Will Deacon wrote:
>> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
>>    static struct platform_device pmu_device = {
>>    	.name		= "arm-pmu",
>> -	.id		= ARM_PMU_DEVICE_CPU,
>> +	.id		= -1,
>>    	.resource	= &pmu_resource,
>>    	.num_resources	= 1,
>>    };
>>
> Isn't it clearer to define a meaningful name for "-1", esp. if "-1" is
> being checked somewhere else?

No platform_device->id is not being referred anywhere. 
ARM_PMU_DEVICE_CPU was initially assigned to id to identify different 
PMU types through platform_device->id variable but was never used.

Also for all new platforms that might support multiple PMUs, we can use 
device tree to identify them.

Regards,
Sudeep




From linus.walleij at linaro.org  Tue Aug 14 04:51:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:51:02 +0200
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> In the initial submission of the MSP driver msp1 and msp3's associated
> pinctrl mechanism was passed back to platform code using a plat_init()
> call-back routine, but it has no place in platform code. The MSP driver
> should set this up for the appropriate ports. Instead we use a use_pinctrl
> identifier which is passed from platform_data/Device Tree which indicates
> which ports should use pinctrl.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This is very good because it rids platform code and makes the driver
self-contained without strange platform data hooks.

Now details...

> +/* MSP1/3 Tx/Rx usage protection */
> +static DEFINE_SPINLOCK(msp_rxtx_lock);
> +
> +/* Pin modes */
> +struct pinctrl *pinctrl_p;
> +struct pinctrl_state *pinctrl_def;
> +struct pinctrl_state *pinctrl_sleep;
> +
> +/* Reference Count */
> +int pinctrl_rxtx_ref;


But wait. These are just local statics. Surelty you can put these into
struct ux500_msp instead? Here it looks like these will be used for
all ports, so MSP2 will enable the pins requested by MSP1 etc
completely broken. So put it into the struct ux500_msp state
container from ux500_msp_i2s.h where it belongs.

Refer to drivers/tty/serial/amba-pl011.c when in trouble. This
one is a good pinctrl example.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:52:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:52:23 +0200
Subject: [PATCH 05/22] ASoC: Ux500: Enable MOP500 driver for Device Tree
In-Reply-To: <1344527268-5964-6-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-6-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ+zgEf48qpCRg_fz9=_oSGohuSsFLQoC3BzTgSDdNnZA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Here we ensure that the MOP500 audio driver will be probed during a
> Device Tree boot. We also parse the sound node to link together the
> codec, dma and the CPU-side Digital Audio Interface.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

But only if Mark agrees with the overall approach.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 04:55:59 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 10:55:59 +0200
Subject: [PATCH 06/22] ASoC: Ux500: Enable ux500 MSP driver for Device Tree
In-Reply-To: <1344527268-5964-7-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdb09UnPj6xV-rNxoeUS2yPLurA+n6zygWEA3_7OQfb0nA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Register both parts of the MSP driver from Device Tree so that they
> are probed when Device Tree is enabled. Also, as there is platform
> data involved, we ensure that there is allocated memory to place the
> configuration into and that the correct information is extracted from
> the DT binary.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Looks like it's doing what's intended...
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Tue Aug 14 04:57:21 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 14 Aug 2012 10:57:21 +0200
Subject: [PATCH] pinctrl/nomadik: add kp_b_2 keyboard function group list
Message-ID: <1344934641-16043-1-git-send-email-linus.walleij@stericsson.com>

From: Patrice Chotard <patrice.chotard at stericsson.com>

There is yet another way to mux the keyboard, so fix up that
group.

Signed-off-by: Patrice Chotard <patrice.chotard at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinctrl-nomadik-db8500.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
index 5f3e9d0..a39fb7a 100644
--- a/drivers/pinctrl/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -505,6 +505,8 @@ static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
 	DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
 	DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
 	DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
+static const unsigned kp_b_2_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
+	DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_F4, DB8500_PIN_E3};
 static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
 	DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
 	DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
@@ -662,6 +664,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
 	DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
 	DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
 	DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
+	DB8500_PIN_GROUP(kp_b_2, NMK_GPIO_ALT_B),
 	DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
 	DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
 	DB8500_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
@@ -751,7 +754,7 @@ DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
 DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
 DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
 	"lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
-DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
+DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_b_2", "kp_c_1", "kp_oc1_1");
 DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
 DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
 DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
-- 
1.7.11.3



From peter.ujfalusi at ti.com  Tue Aug 14 05:07:55 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 12:07:55 +0300
Subject: [PATCH v2 0/4] ASoC machine driver for simple SoC with twl4030
Message-ID: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v1:
- Card name for cm-t35 is "cm-t3x"
- Added Ack from Tony for the OMAP patch
- Codec sysclock no longer needed by the machine driver
  The codec itself must know the mclk since it needs it for initial
  configuration and also in case only the vibra functionality is used.
  The codec driver ignores the machine driver provided clock, it always uses the
  mclk freq it got from the MFD core driver.

Intro mail from v1:

Create new unified ASoC machine driver (with DT support) for boards using simple
configuration for audio and using the twl4030 codec.
This driver will replace the following machine drivers (since they are basically
the same):
igep0020, omap3beagle, omap3evm and overo.

This series will switch the boards I can identify to use the new unified ASoC
machine driver.

Changes under arch/arm/mach-omap2/ are trivial, I don't expect merge issues
later. If it is OK for the maintainers I would like this to go via audio tree
(with the McBSP and the twl4030-audio stack DT support).

The series has been tested on BeagleBoard (with the McBSP and twl4030-audio DT
support).

Regards,
Peter
---
Peter Ujfalusi (4):
  ASoC: omap-twl4030: Simple machine driver for TI SoC with twl4030
    codec
  ARM: OMAP: twl-common: Add helper function to register the
    omap-twl4030 audio driver
  ARM: OMAP3: Switch to use the unified audio driver (omap-twl4030) for
    selected boards
  ASoC: Remove obsolete OMAP3 machine drivers

 .../devicetree/bindings/sound/omap-twl4030.txt     |   17 ++
 arch/arm/mach-omap2/board-cm-t35.c                 |    1 +
 arch/arm/mach-omap2/board-devkit8000.c             |    1 +
 arch/arm/mach-omap2/board-igep0020.c               |    1 +
 arch/arm/mach-omap2/board-omap3beagle.c            |    1 +
 arch/arm/mach-omap2/board-omap3evm.c               |    1 +
 arch/arm/mach-omap2/board-overo.c                  |    1 +
 arch/arm/mach-omap2/twl-common.c                   |   27 +++
 arch/arm/mach-omap2/twl-common.h                   |    2 +
 include/linux/platform_data/omap-twl4030.h         |   32 ++++
 sound/soc/omap/Kconfig                             |   48 ++----
 sound/soc/omap/Makefile                            |   10 +-
 sound/soc/omap/igep0020.c                          |  120 -------------
 sound/soc/omap/omap-twl4030.c                      |  188 ++++++++++++++++++++
 sound/soc/omap/omap3beagle.c                       |  150 ----------------
 sound/soc/omap/omap3evm.c                          |  118 ------------
 sound/soc/omap/overo.c                             |  122 -------------
 17 files changed, 287 insertions(+), 553 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-twl4030.txt
 create mode 100644 include/linux/platform_data/omap-twl4030.h
 delete mode 100644 sound/soc/omap/igep0020.c
 create mode 100644 sound/soc/omap/omap-twl4030.c
 delete mode 100644 sound/soc/omap/omap3beagle.c
 delete mode 100644 sound/soc/omap/omap3evm.c
 delete mode 100644 sound/soc/omap/overo.c

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 05:07:56 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 12:07:56 +0300
Subject: [PATCH v2 1/4] ASoC: omap-twl4030: Simple machine driver for TI SoC
 with twl4030 codec
In-Reply-To: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344935279-32364-2-git-send-email-peter.ujfalusi@ti.com>

Machine driver to handle simple devices using twl4030 as audio codec.
The driver supports the following boards:
- Beagleboard or Devkit8000
- Gumstix Overo or CompuLab CM-T35/CM-T3730
- IGEP v2
- OMAP3EVM

All of these boards can be switched to use this driver since their setup is
identical.
Devicetree support for the omap-twl4030 machine driver also implemented.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/sound/omap-twl4030.txt     |   17 ++
 include/linux/platform_data/omap-twl4030.h         |   32 ++++
 sound/soc/omap/Kconfig                             |   13 ++
 sound/soc/omap/Makefile                            |    2 +
 sound/soc/omap/omap-twl4030.c                      |  188 ++++++++++++++++++++
 5 files changed, 252 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-twl4030.txt
 create mode 100644 include/linux/platform_data/omap-twl4030.h
 create mode 100644 sound/soc/omap/omap-twl4030.c

diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
new file mode 100644
index 0000000..6fae51c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
@@ -0,0 +1,17 @@
+* Texas Instruments SoC with twl4030 based audio setups
+
+Required properties:
+- compatible: "ti,omap-twl4030"
+- ti,model: Name of the sound card (for example "omap3beagle")
+- ti,mcbsp: phandle for the McBSP node
+- ti,codec: phandle for the twl4030 audio node
+
+Example:
+
+sound {
+	compatible = "ti,omap-twl4030";
+	ti,model = "omap3beagle";
+
+	ti,mcbsp = <&mcbsp2>;
+	ti,codec = <&twl_audio>;
+};
diff --git a/include/linux/platform_data/omap-twl4030.h b/include/linux/platform_data/omap-twl4030.h
new file mode 100644
index 0000000..c7bef78
--- /dev/null
+++ b/include/linux/platform_data/omap-twl4030.h
@@ -0,0 +1,32 @@
+/**
+ * omap-twl4030.h - ASoC machine driver for TI SoC based boards with twl4030
+ *		    codec, header.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Author: Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef _OMAP_TWL4030_H_
+#define _OMAP_TWL4030_H_
+
+struct omap_tw4030_pdata {
+	const char *card_name;
+};
+
+#endif /* _OMAP_TWL4030_H_ */
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 57a2fa7..fc83d74 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -95,6 +95,19 @@ config SND_OMAP_SOC_SDP3430
 	  Say Y if you want to add support for SoC audio on Texas Instruments
 	  SDP3430.
 
+config SND_OMAP_SOC_OMAP_TWL4030
+	tristate "SoC Audio support for TI SoC based boards with twl4030 codec"
+	depends on TWL4030_CORE && SND_OMAP_SOC
+	select SND_OMAP_SOC_MCBSP
+	select SND_SOC_TWL4030
+	help
+	  Say Y if you want to add support for SoC audio on TI SoC based boards
+	  using twl4030 as c codec. This driver currently supports:
+	  - Beagleboard or Devkit8000
+	  - Gumstix Overo or CompuLab CM-T35/CM-T3730
+	  - IGEP v2
+	  - OMAP3EVM
+
 config SND_OMAP_SOC_OMAP_ABE_TWL6040
 	tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec"
 	depends on TWL6040_CORE && SND_OMAP_SOC && ARCH_OMAP4
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 0e14dd3..861e640 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -21,6 +21,7 @@ snd-soc-omap3evm-objs := omap3evm.o
 snd-soc-am3517evm-objs := am3517evm.o
 snd-soc-sdp3430-objs := sdp3430.o
 snd-soc-omap-abe-twl6040-objs := omap-abe-twl6040.o
+snd-soc-omap-twl4030-objs := omap-twl4030.o
 snd-soc-omap3pandora-objs := omap3pandora.o
 snd-soc-omap3beagle-objs := omap3beagle.o
 snd-soc-zoom2-objs := zoom2.o
@@ -37,6 +38,7 @@ obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
 obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o
 obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040) += snd-soc-omap-abe-twl6040.o
+obj-$(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) += snd-soc-omap-twl4030.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
 obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o
diff --git a/sound/soc/omap/omap-twl4030.c b/sound/soc/omap/omap-twl4030.c
new file mode 100644
index 0000000..3b97b879
--- /dev/null
+++ b/sound/soc/omap/omap-twl4030.c
@@ -0,0 +1,188 @@
+/*
+ * omap-twl4030.c  --  SoC audio for TI SoC based boards with twl4030 codec
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Author: Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This driver replaces the following machine drivers:
+ * omap3beagle (Author: Steve Sakoman <steve at sakoman.com>)
+ * omap3evm (Author: Anuj Aggarwal <anuj.aggarwal at ti.com>)
+ * overo (Author: Steve Sakoman <steve at sakoman.com>)
+ * igep0020 (Author: Enric Balletbo i Serra <eballetbo at iseebcn.com>)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/platform_data/omap-twl4030.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#include "omap-mcbsp.h"
+#include "omap-pcm.h"
+
+static int omap_twl4030_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_card *card = codec->card;
+	unsigned int fmt;
+	int ret;
+
+	switch (params_channels(params)) {
+	case 2: /* Stereo I2S mode */
+		fmt =	SND_SOC_DAIFMT_I2S |
+			SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBM_CFM;
+		break;
+	case 4: /* Four channel TDM mode */
+		fmt =	SND_SOC_DAIFMT_DSP_A |
+			SND_SOC_DAIFMT_IB_NF |
+			SND_SOC_DAIFMT_CBM_CFM;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set codec DAI configuration */
+	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
+	if (ret < 0) {
+		dev_err(card->dev, "can't set codec DAI configuration\n");
+		return ret;
+	}
+
+	/* Set cpu DAI configuration */
+	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
+	if (ret < 0) {
+		dev_err(card->dev, "can't set cpu DAI configuration\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops omap_twl4030_ops = {
+	.hw_params = omap_twl4030_hw_params,
+};
+
+/* Digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link omap_twl4030_dai_links[] = {
+	{
+		.name = "TWL4030",
+		.stream_name = "TWL4030",
+		.cpu_dai_name = "omap-mcbsp.2",
+		.codec_dai_name = "twl4030-hifi",
+		.platform_name = "omap-pcm-audio",
+		.codec_name = "twl4030-codec",
+		.ops = &omap_twl4030_ops,
+	},
+};
+
+/* Audio machine driver */
+static struct snd_soc_card omap_twl4030_card = {
+	.owner = THIS_MODULE,
+	.dai_link = omap_twl4030_dai_links,
+	.num_links = ARRAY_SIZE(omap_twl4030_dai_links),
+};
+
+static __devinit int omap_twl4030_probe(struct platform_device *pdev)
+{
+	struct omap_tw4030_pdata *pdata = dev_get_platdata(&pdev->dev);
+	struct device_node *node = pdev->dev.of_node;
+	struct snd_soc_card *card = &omap_twl4030_card;
+	int ret = 0;
+
+	card->dev = &pdev->dev;
+
+	if (node) {
+		struct device_node *dai_node;
+
+		if (snd_soc_of_parse_card_name(card, "ti,model")) {
+			dev_err(&pdev->dev, "Card name is not provided\n");
+			return -ENODEV;
+		}
+
+		dai_node = of_parse_phandle(node, "ti,mcbsp", 0);
+		if (!dai_node) {
+			dev_err(&pdev->dev, "McBSP node is not provided\n");
+			return -EINVAL;
+		}
+		omap_twl4030_dai_links[0].cpu_dai_name  = NULL;
+		omap_twl4030_dai_links[0].cpu_of_node = dai_node;
+
+	} else if (pdata) {
+		if (pdata->card_name) {
+			card->name = pdata->card_name;
+		} else {
+			dev_err(&pdev->dev, "Card name is not provided\n");
+			return -ENODEV;
+		}
+	} else {
+		dev_err(&pdev->dev, "Missing pdata\n");
+		return -ENODEV;
+	}
+
+	ret = snd_soc_register_card(card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
+			ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit omap_twl4030_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(card);
+
+	return 0;
+}
+
+static const struct of_device_id omap_twl4030_of_match[] = {
+	{.compatible = "ti,omap-twl4030", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, omap_twl4030_of_match);
+
+static struct platform_driver omap_twl4030_driver = {
+	.driver = {
+		.name = "omap-twl4030",
+		.owner = THIS_MODULE,
+		.pm = &snd_soc_pm_ops,
+		.of_match_table = omap_twl4030_of_match,
+	},
+	.probe = omap_twl4030_probe,
+	.remove = __devexit_p(omap_twl4030_remove),
+};
+
+module_platform_driver(omap_twl4030_driver);
+
+MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi at ti.com>");
+MODULE_DESCRIPTION("ALSA SoC for TI SoC based boards with twl4030 codec");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:omap-twl4030");
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 05:07:57 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 12:07:57 +0300
Subject: [PATCH v2 2/4] ARM: OMAP: twl-common: Add helper function to register
 the omap-twl4030 audio driver
In-Reply-To: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344935279-32364-3-git-send-email-peter.ujfalusi@ti.com>

Since several OMAP3 based boards will be using the unified simple audio
driver it is better to not have duplicated code in the board files for this
purpose.
Board files can call omap_twl4030_audio_init(); to set up the needed device
for the audio support.

For example:
omap_twl4030_audio_init("omap3beagle", 26000000);

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/twl-common.c |   27 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/twl-common.h |    2 ++
 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index d52be85..1c6045a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -522,3 +522,30 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 		pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
+
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) || \
+	defined(CONFIG_SND_OMAP_SOC_OMAP_TWL4030_MODULE)
+#include <linux/platform_data/omap-twl4030.h>
+
+static struct omap_tw4030_pdata omap_twl4030_audio_data;
+
+static struct platform_device audio_device = {
+	.name		= "omap-twl4030",
+	.id		= -1,
+	.dev = {
+		.platform_data = &omap_twl4030_audio_data,
+	},
+};
+
+void __init omap_twl4030_audio_init(char *card_name)
+{
+	omap_twl4030_audio_data.card_name = card_name;
+	platform_device_register(&audio_device);
+}
+
+#else /* SOC_OMAP_TWL4030 */
+void __init omap_twl4030_audio_init(char *card_name, int codec_sysclk)
+{
+	return;
+}
+#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index de062c7..b86c676 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -60,4 +60,6 @@ void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 			   u32 pdata_flags, u32 regulators_flags);
 
+void omap_twl4030_audio_init(char *card_name);
+
 #endif /* __OMAP_PMIC_COMMON__ */
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 05:07:58 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 12:07:58 +0300
Subject: [PATCH v2 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344935279-32364-4-git-send-email-peter.ujfalusi@ti.com>

These boards have similar audio setup and they can all use the same driver
for audio support if it is enabled in the kernel config.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Igor Grinberg <grinberg at compulab.co.il>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-cm-t35.c      |    1 +
 arch/arm/mach-omap2/board-devkit8000.c  |    1 +
 arch/arm/mach-omap2/board-igep0020.c    |    1 +
 arch/arm/mach-omap2/board-omap3beagle.c |    1 +
 arch/arm/mach-omap2/board-omap3evm.c    |    1 +
 arch/arm/mach-omap2/board-overo.c       |    1 +
 6 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 97d7190..188cc4e 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -731,6 +731,7 @@ static void __init cm_t3x_common_init(void)
 	cm_t35_init_ethernet();
 	cm_t35_init_led();
 	cm_t35_init_display();
+	omap_twl4030_audio_init("cm-t3x");
 
 	usb_musb_init(NULL);
 	cm_t35_init_usbh();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1c..4cd804f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -630,6 +630,7 @@ static void __init devkit8000_init(void)
 	usbhs_init(&usbhs_bdata);
 	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
 			     ARRAY_SIZE(devkit8000_nand_partitions));
+	omap_twl4030_audio_init("omap3beagle");
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 7491529..293fc9c 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -626,6 +626,7 @@ static void __init igep_init(void)
 
 	igep_flash_init();
 	igep_leds_init();
+	omap_twl4030_audio_init("igep2");
 
 	/*
 	 * WLAN-BT combo module from MuRata which has a Marvell WLAN
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc7..3ccfa5b 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -519,6 +519,7 @@ static void __init omap3_beagle_init(void)
 	usbhs_init(&usbhs_bdata);
 	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
 			     ARRAY_SIZE(omap3beagle_nand_partitions));
+	omap_twl4030_audio_init("omap3beagle");
 
 	/* Ensure msecure is mux'd to be able to set the RTC. */
 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0..46e6eca 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -736,6 +736,7 @@ static void __init omap3_evm_init(void)
 	omap3evm_init_smsc911x();
 	omap3_evm_display_init();
 	omap3_evm_wl12xx_init();
+	omap_twl4030_audio_init("omap3evm");
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d..fe674d0 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -509,6 +509,7 @@ static void __init overo_init(void)
 	overo_display_init();
 	overo_init_led();
 	overo_init_keys();
+	omap_twl4030_audio_init("overo");
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 05:07:59 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 12:07:59 +0300
Subject: [PATCH v2 4/4] ASoC: Remove obsolete OMAP3 machine drivers
In-Reply-To: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344935279-32364-5-git-send-email-peter.ujfalusi@ti.com>

The new omap-twl4030 handles the boards used the following drivers:
igep0020, omap3beagle, omap3evm and overo.
Remove these drivers since they are mostly identical and we already have
drop in replacement for all of them.

Note: Earlier patch added the needed code for the board files to retain the
audio support for boards I can identify that used one of the removed
drivers.
If I missed something please take a look at for example:
arch/arm/mach-omap2/board-omap3beagle.c on how add support for omap-twl4030
audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/Kconfig       |   35 ----------
 sound/soc/omap/Makefile      |    8 --
 sound/soc/omap/igep0020.c    |  120 ---------------------------------
 sound/soc/omap/omap3beagle.c |  150 ------------------------------------------
 sound/soc/omap/omap3evm.c    |  118 ---------------------------------
 sound/soc/omap/overo.c       |  122 ----------------------------------
 6 files changed, 0 insertions(+), 553 deletions(-)
 delete mode 100644 sound/soc/omap/igep0020.c
 delete mode 100644 sound/soc/omap/omap3beagle.c
 delete mode 100644 sound/soc/omap/omap3evm.c
 delete mode 100644 sound/soc/omap/overo.c

diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index fc83d74..2c484a5 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -60,23 +60,6 @@ config SND_OMAP_SOC_OSK5912
 	help
 	  Say Y if you want to add support for SoC audio on osk5912.
 
-config SND_OMAP_SOC_OVERO
-	tristate "SoC Audio support for Gumstix Overo and CompuLab CM-T35"
-	depends on TWL4030_CORE && SND_OMAP_SOC && (MACH_OVERO || MACH_CM_T35)
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the
-	  Gumstix Overo or CompuLab CM-T35
-
-config SND_OMAP_SOC_OMAP3EVM
-	tristate "SoC Audio support for OMAP3EVM board"
-	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP3EVM
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the omap3evm board.
-
 config SND_OMAP_SOC_AM3517EVM
 	tristate "SoC Audio support for OMAP3517 / AM3517 EVM"
 	depends on SND_OMAP_SOC && MACH_OMAP3517EVM && I2C
@@ -140,16 +123,6 @@ config SND_OMAP_SOC_OMAP3_PANDORA
 	help
 	  Say Y if you want to add support for SoC audio on the OMAP3 Pandora.
 
-config SND_OMAP_SOC_OMAP3_BEAGLE
-	tristate "SoC Audio support for OMAP3 Beagle and Devkit8000"
-	depends on TWL4030_CORE && SND_OMAP_SOC
-	depends on (MACH_OMAP3_BEAGLE || MACH_DEVKIT8000)
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for SoC audio on the Beagleboard or
-	  the clone Devkit8000.
-
 config SND_OMAP_SOC_ZOOM2
 	tristate "SoC Audio support for Zoom2"
 	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_ZOOM2
@@ -157,11 +130,3 @@ config SND_OMAP_SOC_ZOOM2
 	select SND_SOC_TWL4030
 	help
 	  Say Y if you want to add support for Soc audio on Zoom2 board.
-
-config SND_OMAP_SOC_IGEP0020
-	tristate "SoC Audio support for IGEP v2"
-	depends on TWL4030_CORE && SND_OMAP_SOC && MACH_IGEP0020
-	select SND_OMAP_SOC_MCBSP
-	select SND_SOC_TWL4030
-	help
-	  Say Y if you want to add support for Soc audio on IGEP v2 board.
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 861e640..19637e5 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -16,31 +16,23 @@ snd-soc-n810-objs := n810.o
 snd-soc-rx51-objs := rx51.o
 snd-soc-ams-delta-objs := ams-delta.o
 snd-soc-osk5912-objs := osk5912.o
-snd-soc-overo-objs := overo.o
-snd-soc-omap3evm-objs := omap3evm.o
 snd-soc-am3517evm-objs := am3517evm.o
 snd-soc-sdp3430-objs := sdp3430.o
 snd-soc-omap-abe-twl6040-objs := omap-abe-twl6040.o
 snd-soc-omap-twl4030-objs := omap-twl4030.o
 snd-soc-omap3pandora-objs := omap3pandora.o
-snd-soc-omap3beagle-objs := omap3beagle.o
 snd-soc-zoom2-objs := zoom2.o
-snd-soc-igep0020-objs := igep0020.o
 snd-soc-omap-hdmi-card-objs := omap-hdmi-card.o
 
 obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
 obj-$(CONFIG_SND_OMAP_SOC_RX51) += snd-soc-rx51.o
 obj-$(CONFIG_SND_OMAP_SOC_AMS_DELTA) += snd-soc-ams-delta.o
 obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o
-obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP2EVM) += snd-soc-omap2evm.o
-obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
 obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o
 obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040) += snd-soc-omap-abe-twl6040.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_TWL4030) += snd-soc-omap-twl4030.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o
-obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o
 obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o
-obj-$(CONFIG_SND_OMAP_SOC_IGEP0020) += snd-soc-igep0020.o
 obj-$(CONFIG_SND_OMAP_SOC_OMAP_HDMI) += snd-soc-omap-hdmi-card.o
diff --git a/sound/soc/omap/igep0020.c b/sound/soc/omap/igep0020.c
deleted file mode 100644
index e835781..0000000
--- a/sound/soc/omap/igep0020.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * igep0020.c  --  SoC audio for IGEP v2
- *
- * Based on sound/soc/omap/overo.c by Steve Sakoman
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int igep2_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-					    SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops igep2_ops = {
-	.hw_params = igep2_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link igep2_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops = &igep2_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_card_igep2 = {
-	.name = "igep2",
-	.owner = THIS_MODULE,
-	.dai_link = &igep2_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *igep2_snd_device;
-
-static int __init igep2_soc_init(void)
-{
-	int ret;
-
-	if (!machine_is_igep0020())
-		return -ENODEV;
-	printk(KERN_INFO "IGEP v2 SoC init\n");
-
-	igep2_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!igep2_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(igep2_snd_device, &snd_soc_card_igep2);
-
-	ret = platform_device_add(igep2_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(igep2_snd_device);
-
-	return ret;
-}
-module_init(igep2_soc_init);
-
-static void __exit igep2_soc_exit(void)
-{
-	platform_device_unregister(igep2_snd_device);
-}
-module_exit(igep2_soc_exit);
-
-MODULE_AUTHOR("Enric Balletbo i Serra <eballetbo at iseebcn.com>");
-MODULE_DESCRIPTION("ALSA SoC IGEP v2");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
deleted file mode 100644
index 2830dfd..0000000
--- a/sound/soc/omap/omap3beagle.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * omap3beagle.c  --  SoC audio for OMAP3 Beagle
- *
- * Author: Steve Sakoman <steve at sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int omap3beagle_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-	unsigned int fmt;
-	int ret;
-
-	switch (params_channels(params)) {
-	case 2: /* Stereo I2S mode */
-		fmt =	SND_SOC_DAIFMT_I2S |
-			SND_SOC_DAIFMT_NB_NF |
-			SND_SOC_DAIFMT_CBM_CFM;
-		break;
-	case 4: /* Four channel TDM mode */
-		fmt =	SND_SOC_DAIFMT_DSP_A |
-			SND_SOC_DAIFMT_IB_NF |
-			SND_SOC_DAIFMT_CBM_CFM;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* Set codec DAI configuration */
-	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec DAI configuration\n");
-		return ret;
-	}
-
-	/* Set cpu DAI configuration */
-	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set cpu DAI configuration\n");
-		return ret;
-	}
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-				     SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops omap3beagle_ops = {
-	.hw_params = omap3beagle_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link omap3beagle_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.platform_name = "omap-pcm-audio",
-	.codec_dai_name = "twl4030-hifi",
-	.codec_name = "twl4030-codec",
-	.ops = &omap3beagle_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_omap3beagle = {
-	.name = "omap3beagle",
-	.owner = THIS_MODULE,
-	.dai_link = &omap3beagle_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *omap3beagle_snd_device;
-
-static int __init omap3beagle_soc_init(void)
-{
-	int ret;
-
-	if (!(machine_is_omap3_beagle() || machine_is_devkit8000()))
-		return -ENODEV;
-	pr_info("OMAP3 Beagle/Devkit8000 SoC init\n");
-
-	omap3beagle_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!omap3beagle_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(omap3beagle_snd_device, &snd_soc_omap3beagle);
-
-	ret = platform_device_add(omap3beagle_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(omap3beagle_snd_device);
-
-	return ret;
-}
-
-static void __exit omap3beagle_soc_exit(void)
-{
-	platform_device_unregister(omap3beagle_snd_device);
-}
-
-module_init(omap3beagle_soc_init);
-module_exit(omap3beagle_soc_exit);
-
-MODULE_AUTHOR("Steve Sakoman <steve at sakoman.com>");
-MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle");
-MODULE_LICENSE("GPL");
diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
deleted file mode 100644
index 3d468c9..0000000
--- a/sound/soc/omap/omap3evm.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * omap3evm.c  -- ALSA SoC support for OMAP3 EVM
- *
- * Author: Anuj Aggarwal <anuj.aggarwal at ti.com>
- *
- * Based on sound/soc/omap/beagle.c by Steve Sakoman
- *
- * Copyright (C) 2008 Texas Instruments, Incorporated
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
- * whether express or implied; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int omap3evm_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-				     SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "Can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops omap3evm_ops = {
-	.hw_params = omap3evm_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link omap3evm_dai = {
-	.name 		= "TWL4030",
-	.stream_name 	= "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops 		= &omap3evm_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_omap3evm = {
-	.name = "omap3evm",
-	.owner = THIS_MODULE,
-	.dai_link = &omap3evm_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *omap3evm_snd_device;
-
-static int __init omap3evm_soc_init(void)
-{
-	int ret;
-
-	if (!machine_is_omap3evm())
-		return -ENODEV;
-	pr_info("OMAP3 EVM SoC init\n");
-
-	omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!omap3evm_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(omap3evm_snd_device, &snd_soc_omap3evm);
-	ret = platform_device_add(omap3evm_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(omap3evm_snd_device);
-
-	return ret;
-}
-
-static void __exit omap3evm_soc_exit(void)
-{
-	platform_device_unregister(omap3evm_snd_device);
-}
-
-module_init(omap3evm_soc_init);
-module_exit(omap3evm_soc_exit);
-
-MODULE_AUTHOR("Anuj Aggarwal <anuj.aggarwal at ti.com>");
-MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
-MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/omap/overo.c b/sound/soc/omap/overo.c
deleted file mode 100644
index 6ac3e0c..0000000
--- a/sound/soc/omap/overo.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * overo.c  --  SoC audio for Gumstix Overo
- *
- * Author: Steve Sakoman <steve at sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <sound/core.h>
-#include <sound/pcm.h>
-#include <sound/soc.h>
-
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <plat/mcbsp.h>
-
-#include "omap-mcbsp.h"
-#include "omap-pcm.h"
-
-static int overo_hw_params(struct snd_pcm_substream *substream,
-	struct snd_pcm_hw_params *params)
-{
-	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-	int ret;
-
-	/* Set the codec system clock for DAC and ADC */
-	ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
-					    SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static struct snd_soc_ops overo_ops = {
-	.hw_params = overo_hw_params,
-};
-
-/* Digital audio interface glue - connects codec <--> CPU */
-static struct snd_soc_dai_link overo_dai = {
-	.name = "TWL4030",
-	.stream_name = "TWL4030",
-	.cpu_dai_name = "omap-mcbsp.2",
-	.codec_dai_name = "twl4030-hifi",
-	.platform_name = "omap-pcm-audio",
-	.codec_name = "twl4030-codec",
-	.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-		   SND_SOC_DAIFMT_CBM_CFM,
-	.ops = &overo_ops,
-};
-
-/* Audio machine driver */
-static struct snd_soc_card snd_soc_card_overo = {
-	.name = "overo",
-	.owner = THIS_MODULE,
-	.dai_link = &overo_dai,
-	.num_links = 1,
-};
-
-static struct platform_device *overo_snd_device;
-
-static int __init overo_soc_init(void)
-{
-	int ret;
-
-	if (!(machine_is_overo() || machine_is_cm_t35())) {
-		pr_debug("Incomatible machine!\n");
-		return -ENODEV;
-	}
-	printk(KERN_INFO "overo SoC init\n");
-
-	overo_snd_device = platform_device_alloc("soc-audio", -1);
-	if (!overo_snd_device) {
-		printk(KERN_ERR "Platform device allocation failed\n");
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(overo_snd_device, &snd_soc_card_overo);
-
-	ret = platform_device_add(overo_snd_device);
-	if (ret)
-		goto err1;
-
-	return 0;
-
-err1:
-	printk(KERN_ERR "Unable to add platform device\n");
-	platform_device_put(overo_snd_device);
-
-	return ret;
-}
-module_init(overo_soc_init);
-
-static void __exit overo_soc_exit(void)
-{
-	platform_device_unregister(overo_snd_device);
-}
-module_exit(overo_soc_exit);
-
-MODULE_AUTHOR("Steve Sakoman <steve at sakoman.com>");
-MODULE_DESCRIPTION("ALSA SoC overo");
-MODULE_LICENSE("GPL");
-- 
1.7.8.6



From will.deacon at arm.com  Tue Aug 14 05:14:07 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 14 Aug 2012 10:14:07 +0100
Subject: [GIT PULL] io.h clean-up for PCI
In-Reply-To: <CAOesGMiWuqqprQ8GGzAgpFNE7k=qvPJpsx7MiVv2CKsSqyiQiw@mail.gmail.com>
References: <50049285.1060100@gmail.com> <50130F36.4090902@gmail.com>
 <CAOesGMiWuqqprQ8GGzAgpFNE7k=qvPJpsx7MiVv2CKsSqyiQiw@mail.gmail.com>
Message-ID: <20120814091407.GB26070@mudshark.cambridge.arm.com>

On Mon, Jul 30, 2012 at 12:07:56AM +0100, Olof Johansson wrote:
> > On 07/16/2012 05:15 PM, Rob Herring wrote:
> > The following changes since commit 84a1caf1453c3d44050bd22db958af4a7f99315c:
> >
> >   Linux 3.5-rc7 (2012-07-14 15:40:28 -0700)
> >
> > are available in the git repository at:
> >
> >   git://sources.calxeda.com/kernel/linux.git io-cleanup-pci-v2
> 
> I have replaced the current staging/io-cleanup-pci contents with the
> above branch. Ideally I'd like to see a fix to the issues on
> integrator before we send it up though.

I *finally* got to the bottom of the issues I was seeing on my integrator
board with these patches. The ATX PSU I was using doesn't have a thumping
great resistor across it and, since the board draws very little current, the
voltage is all over the shop. Of the 3 PCI slots, this made one completely
unusable, one slightly temperamental and the other `rock solid'.

I was using the temperamental slot and the probing of the VGA console
combined with the later PCI initialisation somehow pushes it over the edge
and locks up the board. Swapping the PSU for one with an artifical load
across it makes all of the slots jump into life.

Late in the day, but I worked for this!:

Tested-by: Will Deacon <will.deacon at arm.com>

Will


From ludovic.desroches at atmel.com  Tue Aug 14 05:19:20 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 14 Aug 2012 11:19:20 +0200
Subject: [PATCH v2 0/2] ARM: at91: fix drivers broken because of sparse irq
 support
Message-ID: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Hello,

The first patch fixes the rm9200 breakage (introduced by sparse irq support)
reported by Joachim Eastwood.
The second path fixes an other breakage also introduced by sparse irq support,
it concerns rtc driver.

Changes
v2:
- split in two patches
- take the opportunity of getting irq from resources for the rtc driver

Ludovic Desroches (2):
  ARM: at91: fix system timer irq issue due to sparse irq support
  ARM: at91: fix rtc-at91sam9 irq issue due to sparse irq support

 arch/arm/mach-at91/at91rm9200_time.c     |  2 +-
 arch/arm/mach-at91/at91sam9260_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9261_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9263_devices.c | 10 ++++++++--
 arch/arm/mach-at91/at91sam9g45_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9rl_devices.c  |  6 +++++-
 drivers/rtc/rtc-at91sam9.c               | 22 +++++++++++++++-------
 7 files changed, 44 insertions(+), 14 deletions(-)

-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 14 05:19:21 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 14 Aug 2012 11:19:21 +0200
Subject: [PATCH v2 1/2] ARM: at91: fix system timer irq issue due to sparse
 irq support
In-Reply-To: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
References: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1344935962-18871-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

AT91_ID_SYS as virq is incorrect because of spare irq support which
introduces NR_IRQS_LEGACY offset.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Tested-by: Joachim Eastwood <joachim.eastwood at jotron.com>
---
 arch/arm/mach-at91/at91rm9200_time.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40..aaa443b 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
 	at91_st_read(AT91_ST_SR);
 
 	/* Make IRQs happen for the system timer */
-	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
+	setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
 
 	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
 	 * directly for the clocksource and all clockevents, after adjusting
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 14 05:19:22 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 14 Aug 2012 11:19:22 +0200
Subject: [PATCH v2 2/2] ARM: at91: fix rtc-at91sam9 irq issue due to sparse
 irq support
In-Reply-To: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
References: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1344935962-18871-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

AT91_ID_SYS as virq is incorrect because of spare irq support which
introduces NR_IRQS_LEGACY offset. It modifies rtc-at91sam9 driver in
order to get irq from resources.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9260_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9261_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9263_devices.c | 10 ++++++++--
 arch/arm/mach-at91/at91sam9g45_devices.c |  6 +++++-
 arch/arm/mach-at91/at91sam9rl_devices.c  |  6 +++++-
 drivers/rtc/rtc-at91sam9.c               | 22 +++++++++++++++-------
 6 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..bce572a 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -726,6 +726,8 @@ static struct resource rtt_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	},
 };
 
@@ -744,10 +746,12 @@ static void __init at91_add_device_rtt_rtc(void)
 	 * The second resource is needed:
 	 * GPBR will serve as the storage for RTC time offset
 	 */
-	at91sam9260_rtt_device.num_resources = 2;
+	at91sam9260_rtt_device.num_resources = 3;
 	rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
 				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
 	rtt_resources[1].end = rtt_resources[1].start + 3;
+	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8df5c1b..bc2590d 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -609,6 +609,8 @@ static struct resource rtt_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	}
 };
 
@@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void)
 	 * The second resource is needed:
 	 * GPBR will serve as the storage for RTC time offset
 	 */
-	at91sam9261_rtt_device.num_resources = 2;
+	at91sam9261_rtt_device.num_resources = 3;
 	rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
 				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
 	rtt_resources[1].end = rtt_resources[1].start + 3;
+	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..9b6ca73 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -990,6 +990,8 @@ static struct resource rtt0_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	}
 };
 
@@ -1006,6 +1008,8 @@ static struct resource rtt1_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	}
 };
 
@@ -1027,14 +1031,14 @@ static void __init at91_add_device_rtt_rtc(void)
 		 * The second resource is needed only for the chosen RTT:
 		 * GPBR will serve as the storage for RTC time offset
 		 */
-		at91sam9263_rtt0_device.num_resources = 2;
+		at91sam9263_rtt0_device.num_resources = 3;
 		at91sam9263_rtt1_device.num_resources = 1;
 		pdev = &at91sam9263_rtt0_device;
 		r = rtt0_resources;
 		break;
 	case 1:
 		at91sam9263_rtt0_device.num_resources = 1;
-		at91sam9263_rtt1_device.num_resources = 2;
+		at91sam9263_rtt1_device.num_resources = 3;
 		pdev = &at91sam9263_rtt1_device;
 		r = rtt1_resources;
 		break;
@@ -1047,6 +1051,8 @@ static void __init at91_add_device_rtt_rtc(void)
 	pdev->name = "rtc-at91sam9";
 	r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
 	r[1].end = r[1].start + 3;
+	r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+	r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 0607399..1b47319 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -1293,6 +1293,8 @@ static struct resource rtt_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	}
 };
 
@@ -1310,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void)
 	 * The second resource is needed:
 	 * GPBR will serve as the storage for RTC time offset
 	 */
-	at91sam9g45_rtt_device.num_resources = 2;
+	at91sam9g45_rtt_device.num_resources = 3;
 	rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
 				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
 	rtt_resources[1].end = rtt_resources[1].start + 3;
+	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..b3d365d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -688,6 +688,8 @@ static struct resource rtt_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	}, {
 		.flags	= IORESOURCE_MEM,
+	}, {
+		.flags  = IORESOURCE_IRQ,
 	}
 };
 
@@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void)
 	 * The second resource is needed:
 	 * GPBR will serve as the storage for RTC time offset
 	 */
-	at91sam9rl_rtt_device.num_resources = 2;
+	at91sam9rl_rtt_device.num_resources = 3;
 	rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
 				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
 	rtt_resources[1].end = rtt_resources[1].start + 3;
+	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 8318689..1dd61f4 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -58,6 +58,7 @@ struct sam9_rtc {
 	struct rtc_device	*rtcdev;
 	u32			imr;
 	void __iomem		*gpbr;
+	int 			irq;
 };
 
 #define rtt_readl(rtc, field) \
@@ -292,7 +293,7 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
 {
 	struct resource	*r, *r_gpbr;
 	struct sam9_rtc	*rtc;
-	int		ret;
+	int		ret, irq;
 	u32		mr;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -302,10 +303,18 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "failed to get interrupt resource\n");
+		return irq;
+	}
+
 	rtc = kzalloc(sizeof *rtc, GFP_KERNEL);
 	if (!rtc)
 		return -ENOMEM;
 
+	rtc->irq = irq;
+
 	/* platform setup code should have handled this; sigh */
 	if (!device_can_wakeup(&pdev->dev))
 		device_init_wakeup(&pdev->dev, 1);
@@ -345,11 +354,10 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
 	}
 
 	/* register irq handler after we know what name we'll use */
-	ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
-				IRQF_SHARED,
+	ret = request_irq(rtc->irq, at91_rtc_interrupt, IRQF_SHARED,
 				dev_name(&rtc->rtcdev->dev), rtc);
 	if (ret) {
-		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", AT91_ID_SYS);
+		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
 		rtc_device_unregister(rtc->rtcdev);
 		goto fail_register;
 	}
@@ -386,7 +394,7 @@ static int __devexit at91_rtc_remove(struct platform_device *pdev)
 
 	/* disable all interrupts */
 	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
-	free_irq(AT91_ID_SYS, rtc);
+	free_irq(rtc->irq, rtc);
 
 	rtc_device_unregister(rtc->rtcdev);
 
@@ -423,7 +431,7 @@ static int at91_rtc_suspend(struct platform_device *pdev,
 	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
 	if (rtc->imr) {
 		if (device_may_wakeup(&pdev->dev) && (mr & AT91_RTT_ALMIEN)) {
-			enable_irq_wake(AT91_ID_SYS);
+			enable_irq_wake(rtc->irq);
 			/* don't let RTTINC cause wakeups */
 			if (mr & AT91_RTT_RTTINCIEN)
 				rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
@@ -441,7 +449,7 @@ static int at91_rtc_resume(struct platform_device *pdev)
 
 	if (rtc->imr) {
 		if (device_may_wakeup(&pdev->dev))
-			disable_irq_wake(AT91_ID_SYS);
+			disable_irq_wake(rtc->irq);
 		mr = rtt_readl(rtc, MR);
 		rtt_writel(rtc, MR, mr | rtc->imr);
 	}
-- 
1.7.11.3



From b-cousson at ti.com  Tue Aug 14 05:20:51 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Tue, 14 Aug 2012 11:20:51 +0200
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <CAKdam54ifAW=W86qLj3+JR6k7i00EjDSQgK5B1X--NCg18jJmw@mail.gmail.com>
References: <1342780715-25618-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam54ifAW=W86qLj3+JR6k7i00EjDSQgK5B1X--NCg18jJmw@mail.gmail.com>
Message-ID: <502A1873.90304@ti.com>

Hi Sourav

On 08/14/2012 08:23 AM, Poddar, Sourav wrote:
> Hi,
> 
> On Fri, Jul 20, 2012 at 4:08 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>> Add keypad data node in omap4 device tree file.
>> Also fill the device tree binding parameters
>> with the required value in "omap4-sdp" dts file.
>>
>> Tested on omap4430 sdp with 3.5-rc6 kernel.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>> Changes since v6:
>> -remove address from the node since reg property
>> is not used.
>>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>>  2 files changed, 75 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
>> index 72216e9..80cd016 100644
>> --- a/arch/arm/boot/dts/omap4-sdp.dts
>> +++ b/arch/arm/boot/dts/omap4-sdp.dts
>> @@ -113,6 +113,76 @@
>>                         "DMic", "Digital Mic",
>>                         "Digital Mic", "Digital Mic1 Bias";
>>         };
>> +
>> +       keypad {
>> +               keypad,num-rows = <8>;
>> +               keypad,num-columns = <8>;
>> +               linux,keymap = < 0x00000012
>> +                       0x00010013
>> +                       0x00020014
>> +                       0x00030066
>> +                       0x0004003f
>> +                       0x000500f0
>> +                       0x00060017
>> +                       0x0007002a
>> +                       0x01000020
>> +                       0x01010021
>> +                       0x01020022
>> +                       0x010300e7
>> +                       0x01040040
>> +                       0x010500f0
>> +                       0x01060025
>> +                       0x0107001c
>> +                       0x0200002d
>> +                       0x0201002e
>> +                       0x0202002f
>> +                       0x0203006b
>> +                       0x02040041
>> +                       0x020500f0
>> +                       0x02060034
>> +                       0x0207003a
>> +                       0x0300002c
>> +                       0x0301004e
>> +                       0x03020030
>> +                       0x0303003b
>> +                       0x03040042
>> +                       0x030500f0
>> +                       0x03060018
>> +                       0x03070039
>> +                       0x04000011
>> +                       0x04010015
>> +                       0x04020016
>> +                       0x0403003c
>> +                       0x04040073
>> +                       0x040500f0
>> +                       0x04060026
>> +                       0x04070069
>> +                       0x0500001f
>> +                       0x05010023
>> +                       0x05020024
>> +                       0x0503003d
>> +                       0x05040043
>> +                       0x05050072
>> +                       0x05060032
>> +                       0x0507006a
>> +                       0x06000010
>> +                       0x0601001e
>> +                       0x06020031
>> +                       0x0603009e
>> +                       0x0604000e
>> +                       0x060500f0
>> +                       0x06060019
>> +                       0x06070067
>> +                       0x07000094
>> +                       0x07010095
>> +                       0x070200ca
>> +                       0x070300cb
>> +                       0x0704003e
>> +                       0x070500f0
>> +                       0x07060160
>> +                       0x0707006c >;

I know that the hex value are faster to parse than the explicit
information, but maybe you could at least comment each entry?

Otherwise is looks fine to me.

Thanks,
Benoit

>> +               linux,input-no-autorepeat;
>> +       };
>>  };
>>
>>  &i2c1 {
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 04cbbcb..e78a1f1 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -296,4 +296,9 @@
>>                         ti,hwmods = "dmic";
>>                 };
>>         };
>> +
>> +       keypad {
>> +               compatible = "ti,omap4-keypad";
>> +               ti,hwmods = "kbd";
>> +       };
>>  };
>> --
>> 1.7.1
>>
> Any more comments on this patch?
> 
> ~Sourav
> 



From sourav.poddar at ti.com  Tue Aug 14 05:23:48 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 14 Aug 2012 14:53:48 +0530
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <502A1873.90304@ti.com>
References: <1342780715-25618-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam54ifAW=W86qLj3+JR6k7i00EjDSQgK5B1X--NCg18jJmw@mail.gmail.com>
 <502A1873.90304@ti.com>
Message-ID: <CAKdam54MCq8CNn0Vnd1ZV1MPTuuTmCMJ1LO1q083X18TsTswZg@mail.gmail.com>

Hi Benoit,

On Tue, Aug 14, 2012 at 2:50 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Sourav
>
> On 08/14/2012 08:23 AM, Poddar, Sourav wrote:
>> Hi,
>>
>> On Fri, Jul 20, 2012 at 4:08 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>>> Add keypad data node in omap4 device tree file.
>>> Also fill the device tree binding parameters
>>> with the required value in "omap4-sdp" dts file.
>>>
>>> Tested on omap4430 sdp with 3.5-rc6 kernel.
>>>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> Cc: Felipe Balbi <balbi at ti.com>
>>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>>> ---
>>> Changes since v6:
>>> -remove address from the node since reg property
>>> is not used.
>>>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>>>  2 files changed, 75 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
>>> index 72216e9..80cd016 100644
>>> --- a/arch/arm/boot/dts/omap4-sdp.dts
>>> +++ b/arch/arm/boot/dts/omap4-sdp.dts
>>> @@ -113,6 +113,76 @@
>>>                         "DMic", "Digital Mic",
>>>                         "Digital Mic", "Digital Mic1 Bias";
>>>         };
>>> +
>>> +       keypad {
>>> +               keypad,num-rows = <8>;
>>> +               keypad,num-columns = <8>;
>>> +               linux,keymap = < 0x00000012
>>> +                       0x00010013
>>> +                       0x00020014
>>> +                       0x00030066
>>> +                       0x0004003f
>>> +                       0x000500f0
>>> +                       0x00060017
>>> +                       0x0007002a
>>> +                       0x01000020
>>> +                       0x01010021
>>> +                       0x01020022
>>> +                       0x010300e7
>>> +                       0x01040040
>>> +                       0x010500f0
>>> +                       0x01060025
>>> +                       0x0107001c
>>> +                       0x0200002d
>>> +                       0x0201002e
>>> +                       0x0202002f
>>> +                       0x0203006b
>>> +                       0x02040041
>>> +                       0x020500f0
>>> +                       0x02060034
>>> +                       0x0207003a
>>> +                       0x0300002c
>>> +                       0x0301004e
>>> +                       0x03020030
>>> +                       0x0303003b
>>> +                       0x03040042
>>> +                       0x030500f0
>>> +                       0x03060018
>>> +                       0x03070039
>>> +                       0x04000011
>>> +                       0x04010015
>>> +                       0x04020016
>>> +                       0x0403003c
>>> +                       0x04040073
>>> +                       0x040500f0
>>> +                       0x04060026
>>> +                       0x04070069
>>> +                       0x0500001f
>>> +                       0x05010023
>>> +                       0x05020024
>>> +                       0x0503003d
>>> +                       0x05040043
>>> +                       0x05050072
>>> +                       0x05060032
>>> +                       0x0507006a
>>> +                       0x06000010
>>> +                       0x0601001e
>>> +                       0x06020031
>>> +                       0x0603009e
>>> +                       0x0604000e
>>> +                       0x060500f0
>>> +                       0x06060019
>>> +                       0x06070067
>>> +                       0x07000094
>>> +                       0x07010095
>>> +                       0x070200ca
>>> +                       0x070300cb
>>> +                       0x0704003e
>>> +                       0x070500f0
>>> +                       0x07060160
>>> +                       0x0707006c >;
>
> I know that the hex value are faster to parse than the explicit
> information, but maybe you could at least comment each entry?
>
Yes, will add the comment and post a new version.

Thanks,
Sourav
> Otherwise is looks fine to me.
>

> Thanks,
> Benoit
>
>>> +               linux,input-no-autorepeat;
>>> +       };
>>>  };
>>>
>>>  &i2c1 {
>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>> index 04cbbcb..e78a1f1 100644
>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>> @@ -296,4 +296,9 @@
>>>                         ti,hwmods = "dmic";
>>>                 };
>>>         };
>>> +
>>> +       keypad {
>>> +               compatible = "ti,omap4-keypad";
>>> +               ti,hwmods = "kbd";
>>> +       };
>>>  };
>>> --
>>> 1.7.1
>>>
>> Any more comments on this patch?
>>
>> ~Sourav
>>
>


From arnd at arndb.de  Tue Aug 14 05:33:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 14 Aug 2012 09:33:25 +0000
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <201208140933.26061.arnd@arndb.de>

On Tuesday 14 August 2012, Zhangfei Gao wrote:
> 1. virtual channel vs. physical channel
> Virtual channel is managed by dmaengine
> Physical channel handling resource, such as irq
> Physical channel is alloced dynamically as descending priority,
> freed immediately when irq done.
> The availble highest priority physically channel will alwayes be alloced
> 
> Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel
> 
> 2. list: running list & pending list
> submit: desc list -> pending list
> issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
> irq: free running list (IDLE)
>      check pendlist -> pending list -> running list; free pending list (RUN)
> 
> 3. irq:
> Each list generate one irq, calling callback
> One list may contain several desc chain, in such case, make sure only the last desc list generate irq.
> 
> 4. async
> Submit will add desc chain to pending list, which can be multi-called
> If multi desc chain is submitted, only the last desc would generate irq -> call back
> If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
> If RUN, irq will start pending list
> 
> 5. test
> 5.1 pxa3xx_nand on pxa910
> 5.2 insmod dmatest.ko (threads_per_chan=y)
> By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel
> 
> Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Tue Aug 14 05:34:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 14 Aug 2012 09:34:11 +0000
Subject: [PATCH v3 2/4] dmaengine: mmp_tdma: add dt support
In-Reply-To: <1344917519-9505-3-git-send-email-zhangfei.gao@marvell.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-3-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <201208140934.11774.arnd@arndb.de>

On Tuesday 14 August 2012, Zhangfei Gao wrote:
> Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
> ---
>  Documentation/devicetree/bindings/dma/mmp-dma.txt |   30 ++++++++++++
>  drivers/dma/mmp_tdma.c                            |   51 +++++++++++++--------
>  2 files changed, 61 insertions(+), 20 deletions(-)

Acked-by: Arnd Bergmann <arnd at arndb.de>

but please add a changelog text for this patch and every other one you do.


From arnd at arndb.de  Tue Aug 14 05:37:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 14 Aug 2012 09:37:46 +0000
Subject: [GIT PULL] io.h clean-up for PCI
In-Reply-To: <20120814091407.GB26070@mudshark.cambridge.arm.com>
References: <50049285.1060100@gmail.com>
 <CAOesGMiWuqqprQ8GGzAgpFNE7k=qvPJpsx7MiVv2CKsSqyiQiw@mail.gmail.com>
 <20120814091407.GB26070@mudshark.cambridge.arm.com>
Message-ID: <201208140937.46974.arnd@arndb.de>

On Tuesday 14 August 2012, Will Deacon wrote:
> On Mon, Jul 30, 2012 at 12:07:56AM +0100, Olof Johansson wrote:
> > > On 07/16/2012 05:15 PM, Rob Herring wrote:
> > > The following changes since commit 84a1caf1453c3d44050bd22db958af4a7f99315c:
> > >
> > >   Linux 3.5-rc7 (2012-07-14 15:40:28 -0700)
> > >
> > > are available in the git repository at:
> > >
> > >   git://sources.calxeda.com/kernel/linux.git io-cleanup-pci-v2
> > 
> > I have replaced the current staging/io-cleanup-pci contents with the
> > above branch. Ideally I'd like to see a fix to the issues on
> > integrator before we send it up though.
> 
> I finally got to the bottom of the issues I was seeing on my integrator
> board with these patches. The ATX PSU I was using doesn't have a thumping
> great resistor across it and, since the board draws very little current, the
> voltage is all over the shop. Of the 3 PCI slots, this made one completely
> unusable, one slightly temperamental and the other `rock solid'.
> 
> I was using the temperamental slot and the probing of the VGA console
> combined with the later PCI initialisation somehow pushes it over the edge
> and locks up the board. Swapping the PSU for one with an artifical load
> across it makes all of the slots jump into life.
> 
> Late in the day, but I worked for this!:
> 
> Tested-by: Will Deacon <will.deacon at arm.com>

Just to let you know, I've started getting the arm-soc tree into shape
for v3.7, and the series is now scheduled for integration in the next
merge window as a regular branch.

	Arnd


From arnd at arndb.de  Tue Aug 14 05:42:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 14 Aug 2012 09:42:54 +0000
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
Message-ID: <201208140942.54773.arnd@arndb.de>

On Tuesday 14 August 2012, Linus Walleij wrote:
> 
> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > +static struct irq_domain *db8500_irq_domain;
> 
> So this is a good idea.
> 
> > +int db8500_irq_get_virq(int irq);
> 
> And I'm sceptic about this business. Why isn't this physical-to virtual
> mapping business confined to the core MFD driver? But enlighten me.
> 

I believe MFD does not (yet) know about IRQ domains. The wm8994
and 88pm80x drivers do this slightly different by exporting
a foo_request_irq() function that performs the mapping.

Traditionally, an MFD would add an offset to the local IRQ number
to put the VIRQ into the IRQ resource, but this doesn't work when
you have domains other than legacy.

	Arnd


From linus.walleij at linaro.org  Tue Aug 14 05:48:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 11:48:02 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAAQ0ZWSuAguQwZkQzkUPqJF5ZBSc5Ekiq6mvtwvp98tuu5noLg@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CACRpkdZL6efwvUyW1+2j8253WRXm3WYyDUw8rN_o9QE=HER4wA@mail.gmail.com>
 <CAAQ0ZWSuAguQwZkQzkUPqJF5ZBSc5Ekiq6mvtwvp98tuu5noLg@mail.gmail.com>
Message-ID: <CACRpkdZn5DFNssCNPvBwXt3AYhXnn6qi1+DXEwjCbqUL65gPOw@mail.gmail.com>

On Tue, Aug 14, 2012 at 10:22 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On 14 August 2012 16:13, Linus Walleij <linus.walleij at linaro.org> wrote:
>> Since I just merged the imx53 driver which *again* start numbering on
>> 1, can I have a patch that fixes that driver also?
>>
> What Uwe added is imx35 (vs. imx53 :) driver, which already numbers pad from 0.

Yes I was confused... I mixed up imx35 and imx53 again.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 05:50:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 11:50:13 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdZ22K9yyqVD0_ae7pQPpsBP1t2rVE50S2J7y1EW6LVNAQ@mail.gmail.com>

On Mon, Aug 13, 2012 at 4:47 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
> pinctrl drivers number pad from 1.  It causes problem/confusion when
> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>
> Change imx51_pads and imx53_pads numbering start from 0.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Applied.

Yours,
Linus Walleij


From b-cousson at ti.com  Tue Aug 14 05:56:45 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Tue, 14 Aug 2012 11:56:45 +0200
Subject: [PATCHv2 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
 <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>
Message-ID: <502A20DD.5030707@ti.com>

On 08/13/2012 12:05 PM, Sourav Poddar wrote:
> Add tmp102 temperature sensor data in omap5 evm dts file.
> 
> Tested on omap5430 evm with 3.5 custom kernel.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
> index 200c39a..45a8aeb 100644
> --- a/arch/arm/boot/dts/omap5-evm.dts
> +++ b/arch/arm/boot/dts/omap5-evm.dts
> @@ -18,3 +18,12 @@
>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>  	};
>  };
> +
> +&i2c4 {
> +	clock-frequency = <400000>;

Have you checked if we cannot run at faster speed? Reducing the speed
will impact every devices on the bus.
It might be needed, I just wanted to be sure.

You should maybe just add a small comment to explain what the device is
doing with potentially a link to the HW spec if available.

The same comments are applicable to the bmp085 patch.

Regards,
Benoit



From balbi at ti.com  Tue Aug 14 05:59:26 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 14 Aug 2012 12:59:26 +0300
Subject: [PATCHv2 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <502A20DD.5030707@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
 <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>
 <502A20DD.5030707@ti.com>
Message-ID: <20120814095923.GB11416@arwen.pp.htv.fi>

On Tue, Aug 14, 2012 at 11:56:45AM +0200, Benoit Cousson wrote:
> On 08/13/2012 12:05 PM, Sourav Poddar wrote:
> > Add tmp102 temperature sensor data in omap5 evm dts file.
> > 
> > Tested on omap5430 evm with 3.5 custom kernel.
> > 
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > Acked-by: Felipe Balbi <balbi at ti.com>
> > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> > ---
> >  arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
> >  1 files changed, 9 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
> > index 200c39a..45a8aeb 100644
> > --- a/arch/arm/boot/dts/omap5-evm.dts
> > +++ b/arch/arm/boot/dts/omap5-evm.dts
> > @@ -18,3 +18,12 @@
> >  		reg = <0x80000000 0x40000000>; /* 1 GB */
> >  	};
> >  };
> > +
> > +&i2c4 {
> > +	clock-frequency = <400000>;
> 
> Have you checked if we cannot run at faster speed? Reducing the speed
> will impact every devices on the bus.
> It might be needed, I just wanted to be sure.
> 
> You should maybe just add a small comment to explain what the device is
> doing with potentially a link to the HW spec if available.
> 
> The same comments are applicable to the bmp085 patch.

that sort of information should be placed on
Documentation/devicetree/bindings/*/$device.txt, right ? Why should we
replicate it on all dts files ? Besides, there are only two such entries
on all ARM DTS files. Do we really want to make dts files bigger with
links to documentation which can even be moved at any time to other
location by the manufacturer's choice ? Will anyone actually keep track
of such links to make sure they aren't broken ? And even if someone does
track those links, do we really want to keep sending such patches for
the dts files ?

-- 
balbi
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From b-cousson at ti.com  Tue Aug 14 06:21:23 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Tue, 14 Aug 2012 12:21:23 +0200
Subject: [PATCHv2 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <20120814095923.GB11416@arwen.pp.htv.fi>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
 <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>
 <502A20DD.5030707@ti.com> <20120814095923.GB11416@arwen.pp.htv.fi>
Message-ID: <502A26A3.5090100@ti.com>

Hi Felipe,

On 08/14/2012 11:59 AM, Felipe Balbi wrote:
> On Tue, Aug 14, 2012 at 11:56:45AM +0200, Benoit Cousson wrote:
>> On 08/13/2012 12:05 PM, Sourav Poddar wrote:
>>> Add tmp102 temperature sensor data in omap5 evm dts file.
>>>
>>> Tested on omap5430 evm with 3.5 custom kernel.
>>>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Felipe Balbi <balbi at ti.com>
>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>> Acked-by: Felipe Balbi <balbi at ti.com>
>>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>>> ---
>>>  arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
>>>  1 files changed, 9 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
>>> index 200c39a..45a8aeb 100644
>>> --- a/arch/arm/boot/dts/omap5-evm.dts
>>> +++ b/arch/arm/boot/dts/omap5-evm.dts
>>> @@ -18,3 +18,12 @@
>>>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>>>  	};
>>>  };
>>> +
>>> +&i2c4 {
>>> +	clock-frequency = <400000>;
>>
>> Have you checked if we cannot run at faster speed? Reducing the speed
>> will impact every devices on the bus.
>> It might be needed, I just wanted to be sure.
>>
>> You should maybe just add a small comment to explain what the device is
>> doing with potentially a link to the HW spec if available.
>>
>> The same comments are applicable to the bmp085 patch.
> 
> that sort of information should be placed on
> Documentation/devicetree/bindings/*/$device.txt, right ? Why should we
> replicate it on all dts files ? 

Well in that case, this is not part of the binding documentation, but
that can be a good idea to update the documentation indeed.

> Besides, there are only two such entries
> on all ARM DTS files. Do we really want to make dts files bigger with
> links to documentation which can even be moved at any time to other
> location by the manufacturer's choice ? Will anyone actually keep track
> of such links to make sure they aren't broken ? And even if someone does
> track those links, do we really want to keep sending such patches for
> the dts files ?

A little bit of comment and documentation will never hurt anybody and
will not have any impact on the DTB size. If that can save us some time
to avoid googling to know what device we are taking about, it is already
better than nothing.

Regards,
Benoit



From b-cousson at ti.com  Tue Aug 14 06:24:00 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Tue, 14 Aug 2012 12:24:00 +0200
Subject: [PATCHv2 0/4] Add device tree data for omap5
In-Reply-To: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <502A2740.9000206@ti.com>

Hi Sourav,

On 08/13/2012 12:05 PM, Sourav Poddar wrote:
> The following patch series add i2c support for omap5.
> As well as enable I2C based devices like pressure and temperature
> through device tree. Also add onchip keypad dts data.

That series does not seems to apply on top of 3.6-rc1, what based did
you use?

Benoit


> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> 
> Sourav Poddar (4):
>   arm/dts: omap5-evm: Add I2C support
>   arm/dts: omap5-evm: Add tmp102 sensor support
>   arm/dts: omap5-evm: Add keypad data
>   arm/dts: omap5-evm: Add bmp085 sensor support
> 
>  arch/arm/boot/dts/omap5-evm.dts |   30 +++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 70 insertions(+), 0 deletions(-)
> 



From sourav.poddar at ti.com  Tue Aug 14 06:27:50 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 14 Aug 2012 15:57:50 +0530
Subject: [PATCHv2 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <502A20DD.5030707@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
 <1344852313-30484-3-git-send-email-sourav.poddar@ti.com>
 <502A20DD.5030707@ti.com>
Message-ID: <CAKdam57ri9HxCt5q1yhJzRFfHkVk2oGO8=aqLvYqwWWoYASdVw@mail.gmail.com>

Hi Benoit,

On Tue, Aug 14, 2012 at 3:26 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> On 08/13/2012 12:05 PM, Sourav Poddar wrote:
>> Add tmp102 temperature sensor data in omap5 evm dts file.
>>
>> Tested on omap5430 evm with 3.5 custom kernel.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Acked-by: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>>  arch/arm/boot/dts/omap5-evm.dts |    9 +++++++++
>>  1 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
>> index 200c39a..45a8aeb 100644
>> --- a/arch/arm/boot/dts/omap5-evm.dts
>> +++ b/arch/arm/boot/dts/omap5-evm.dts
>> @@ -18,3 +18,12 @@
>>               reg = <0x80000000 0x40000000>; /* 1 GB */
>>       };
>>  };
>> +
>> +&i2c4 {
>> +     clock-frequency = <400000>;
>
> Have you checked if we cannot run at faster speed? Reducing the speed
> will impact every devices on the bus.
> It might be needed, I just wanted to be sure.
>
Indeed, tmp 102(i2c4) and bmp085(i2c2) can run at speed upto 3.4 MHz.

Though, there are other devices on i2c2(tsl2771) and i2c4
(touchscreen) that will eventually come, support upto
400 KHz.  May be I will change this to 3.4 MHz for now?And when
tsl2771 and touch device are added, I will
change it back to 400 kHz??

~Sourav
> You should maybe just add a small comment to explain what the device is
> doing with potentially a link to the HW spec if available.
>
> The same comments are applicable to the bmp085 patch.
>
> Regards,
> Benoit
>


From sourav.poddar at ti.com  Tue Aug 14 06:34:16 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 14 Aug 2012 16:04:16 +0530
Subject: [PATCHv2 0/4] Add device tree data for omap5
In-Reply-To: <502A2740.9000206@ti.com>
References: <1344852313-30484-1-git-send-email-sourav.poddar@ti.com>
 <502A2740.9000206@ti.com>
Message-ID: <CAKdam56A+Fa2pLT2fnV3sHq--PUwjdUX1U4_4JM=_g9KWoW3kw@mail.gmail.com>

Hi Benoit,

On Tue, Aug 14, 2012 at 3:54 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Sourav,
>
> On 08/13/2012 12:05 PM, Sourav Poddar wrote:
>> The following patch series add i2c support for omap5.
>> As well as enable I2C based devices like pressure and temperature
>> through device tree. Also add onchip keypad dts data.
>
> That series does not seems to apply on top of 3.6-rc1, what based did
> you use?
>
My Bad. Send it on top of the testing branch (3.5-rc7).
Will rebase and send it on a 3.6-rc1.
> Benoit
>
>
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>
>> Sourav Poddar (4):
>>   arm/dts: omap5-evm: Add I2C support
>>   arm/dts: omap5-evm: Add tmp102 sensor support
>>   arm/dts: omap5-evm: Add keypad data
>>   arm/dts: omap5-evm: Add bmp085 sensor support
>>
>>  arch/arm/boot/dts/omap5-evm.dts |   30 +++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 70 insertions(+), 0 deletions(-)
>>
>


From linus.walleij at linaro.org  Tue Aug 14 06:44:37 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 12:44:37 +0200
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <201208140942.54773.arnd@arndb.de>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
Message-ID: <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>

On Tue, Aug 14, 2012 at 11:42 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 14 August 2012, Linus Walleij wrote:
>> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > +int db8500_irq_get_virq(int irq);
>>
>> And I'm sceptic about this business. Why isn't this physical-to virtual
>> mapping business confined to the core MFD driver? But enlighten me.
>
> Traditionally, an MFD would add an offset to the local IRQ number
> to put the VIRQ into the IRQ resource, but this doesn't work when
> you have domains other than legacy.

Yes but I think I saw this other patch set from Lee, hitting
irqdomain, OF and MFD to actually fix this ... or did I get
it wrong?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 06:55:16 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 12:55:16 +0200
Subject: RFC: changing DMA slave configuration API
In-Reply-To: <1339390249.1927.1623.camel@vkoul-udesk3>
References: <20120610102023.GC11404@n2100.arm.linux.org.uk>
 <CAGsJ_4xHNdEcfsmtypDHcJ0uyhtFz43xBojgHw2RSvrH8ohRcA@mail.gmail.com>
 <20120610112217.GD11404@n2100.arm.linux.org.uk>
 <1339390249.1927.1623.camel@vkoul-udesk3>
Message-ID: <CACRpkdYxg5sXGhk5ZDNtACyrE7ZffpZA4RR1zJcbfkQv-fi=CA@mail.gmail.com>

On Mon, Jun 11, 2012 at 6:50 AM, Vinod Koul <vinod.koul at linux.intel.com> wrote:

> Do we have any users of peripheral to peripheral slave dma?
> IIRC  that is not the case, or does anyone know of existence or plans
> for such a h/w?

The U300 (COH901318) device can do this.

The usecase is basically that the modem CPU sets up a PCM
stream on the high-speed serial link (called MSL) and the DMA
controller reads 16 bit words from this link and routes it directly
to a PCM sink on an I2S hardware.

Actually it runs in both directions during a voicecall, you can
probably see the gain in power and CPU unload this will gain
on a phone.

However this is all out-of-tree code and not that big deal as
it's a legacy platform.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:00:42 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:00:42 +0200
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <20120314150533.GA8757@fifo99.com>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
 <4F5F41AF.1090907@codeaurora.org>
 <20120314150533.GA8757@fifo99.com>
Message-ID: <CACRpkdbNVV6keGj3mCG4D8ohY4dySEwDreRV5JPrW+Vq8tM6jw@mail.gmail.com>

On Wed, Mar 14, 2012 at 4:05 PM, Daniel Walker <dwalker at fifo99.com> wrote:
> On Tue, Mar 13, 2012 at 06:16:39PM +0530, Ravi Kumar V wrote:
>>
>> There is a MSM DMA driver in arch/arm/mach-msm/ which is not in
>> dmaengine framework standards, but that driver is been used by
>> client drivers nand, eMMC and serial drivers. Now if we implement
>> the whole dma driver using dmaengine framework then nand, eMMC like
>> drivers will be failed as they are using old dma driver API's, so
>> instead of implementing new driver from scratch we are keeping the
>> old dma API's as it is and using those API's in new dmaengine
>> framework.So that we can convert clients drivers to use dma engine
>> framework.
>
> Did you investigate converting the drivers (nand, eMMC, serial) ? It
> seems like there would be a 1:1 mapping between the API's , so it might
> only be a find->replace operation.

The eMMC i.e. drivers/mmc/host/msm_sdcc.c should preferably
not be converted, instead switch the platforms over to using
drivers/mmc/host/mmci.c which is already very well enabled for
DMA engine.

Augment it with Qualcomm silicon differences as needed, I do
not think they will be major.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:08:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:08:23 +0200
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The PCM is a pseudo-device. It doesn't have any of it's own registers
> or hardware. It rather acts as a layer of abstraction for DMA
> transfers. Hence, instead of classifying it as a device in its own
> right, we call the initialisation from the MSP driver.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I'd prefer to have Ola LILJA review this patch, but it looks alright to me.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:09:33 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:09:33 +0200
Subject: [PATCH 08/22] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZtfmsSUxn91ebArALT6gyTg_59EcRhqZVzP=Ff11dhYw@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> We continue to allow the AB8500 CODEC to be registered via the AB8500
> Multi Functional Device API, only this time we extract its configuration
> from the Device Tree binary.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Also for Ola to look at, and/or ACK.
I dare not even ACK patches like this.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:12:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:12:36 +0200
Subject: [PATCH 11/22] ARM: ux500: Clean-up MSP platform code
In-Reply-To: <1344527268-5964-12-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-12-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbYD8vr_bk1=YfkQ9Yv1Hns5Etvdqf-ZYtKjYQC6-db=w@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch contains a couple of general MSP clean-ups pertaining to
> layout changes and changing functions to be void instead of int instead
> of regardlessly returning '0'.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

OK with me but also want Ola to look at this one.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:13:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:13:49 +0200
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> We've done this before and it worked well last time. Here we're
> duplicating a complex registration function to ease the process
> of enabling it for Device Tree. As there are quite a few steps
> taken during the registration process, it makes sense to break
> them up into more manageable chunks. This patch will aid us.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

I understand you have used this approach before so:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:14:46 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:14:46 +0200
Subject: [PATCH 14/22] ARM: ux500: Pass MSP DMA platform data though
 AUXDATA
In-Reply-To: <1344527268-5964-15-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-15-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbA87mRK23=t0vXg4jXNw-cW3Pepz5J3brBtbtJAz0saQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> It isn't currently possible to pass all platform specific configuration
> though Device Tree. Thinks like device names used in the clock
> infrastructure, call-backs and DMA information have to be passed in via
> AUXDATA structures and the MSP is no exception. Here we're passing DMA
> settings.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From sourav.poddar at ti.com  Tue Aug 14 07:15:37 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 16:45:37 +0530
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
Message-ID: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap4 device tree file.
Also fill the device tree binding parameters
with the required value in "omap4-sdp" dts file.

Tested on omap4430 sdp.

Cc: Tony Lindgren <tony at atomide.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
v6->v7
Add key name as a comment. 
 arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi    |    5 +++
 2 files changed, 75 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e9..8e200f4 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -113,6 +113,76 @@
 			"DMic", "Digital Mic",
 			"Digital Mic", "Digital Mic1 Bias";
 	};
+
+	keypad {
+		keypad,num-rows = <8>;
+		keypad,num-columns = <8>;
+		linux,keymap = < 0x00000012 /* KEY_E */
+			0x00010013 /* KEY_R */
+			0x00020014 /* KEY_T */
+			0x00030066 /* KEY_HOME */
+			0x0004003f /* KEY_F5 */
+			0x000500f0 /* KEY_UNKNOWN */
+			0x00060017 /* KEY_I */
+			0x0007002a /* KEY_LEFTSHIFT */
+			0x01000020 /* KEY_D*/
+			0x01010021 /* KEY_F */
+			0x01020022 /* KEY_G */
+			0x010300e7 /* KEY_SEND */
+			0x01040040 /* KEY_F6 */
+			0x010500f0 /* KEY_UNKNOWN */
+			0x01060025 /* KEY_K */
+			0x0107001c /* KEY_ENTER */
+			0x0200002d /* KEY_X */
+			0x0201002e /* KEY_C */
+			0x0202002f /* KEY_V */
+			0x0203006b /* KEY_END */
+			0x02040041 /* KEY_F7 */
+			0x020500f0 /* KEY_UNKNOWN */
+			0x02060034 /* KEY_DOT */
+			0x0207003a /* KEY_CAPSLOCK */
+			0x0300002c /* KEY_Z */
+			0x0301004e /* KEY_KPLUS */
+			0x03020030 /* KEY_B */
+			0x0303003b /* KEY_F1 */
+			0x03040042 /* KEY_F8 */
+			0x030500f0 /* KEY_UNKNOWN */
+			0x03060018 /* KEY_O */
+			0x03070039 /* KEY_SPACE */
+			0x04000011 /* KEY_W */
+			0x04010015 /* KEY_Y */
+			0x04020016 /* KEY_U */
+			0x0403003c /* KEY_F2 */
+			0x04040073 /* KEY_VOLUMEUP */
+			0x040500f0 /* KEY_UNKNOWN */
+			0x04060026 /* KEY_L */
+			0x04070069 /* KEY_LEFT */
+			0x0500001f /* KEY_S */
+			0x05010023 /* KEY_H */
+			0x05020024 /* KEY_J */
+			0x0503003d /* KEY_F3 */
+			0x05040043 /* KEY_F9 */
+			0x05050072 /* KEY_VOLUMEDOWN */
+			0x05060032 /* KEY_M */
+			0x0507006a /* KEY_RIGHT */
+			0x06000010 /* KEY_Q */
+			0x0601001e /* KEY_A */
+			0x06020031 /* KEY_N */
+			0x0603009e /* KEY_BACK */
+			0x0604000e /* KEY_BACKSPACE */
+			0x060500f0 /* KEY_UNKNOWN */
+			0x06060019 /* KEY_P */
+			0x06070067 /* KEY_UP */
+			0x07000094 /* KEY_PROG1 */
+			0x07010095 /* KEY_PROG2 */
+			0x070200ca /* KEY_PROG3 */
+			0x070300cb /* KEY_PROG4 */
+			0x0704003e /* KEY_F4 */
+			0x070500f0 /* KEY_UNKNOWN */
+			0x07060160 /* KEY_OK */
+			0x0707006c >; /* KEY_DOWN */
+		linux,input-no-autorepeat;
+	};
 };
 
 &i2c1 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..e78a1f1 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -296,4 +296,9 @@
 			ti,hwmods = "dmic";
 		};
 	};
+
+	keypad {
+		compatible = "ti,omap4-keypad";
+		ti,hwmods = "kbd";
+	};
 };
-- 
1.7.1



From linus.walleij at linaro.org  Tue Aug 14 07:16:16 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:16:16 +0200
Subject: [PATCH 15/22] ARM: ux500: Stop registering the MOP500 Audio
 driver from platform code
In-Reply-To: <1344527268-5964-16-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-16-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdabmQaQeSuwoBY7DxvSOyPDRWvSBDm+Yn-fJP5eWybuMQ@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> In this patch we prevent MOP500 driver registration from platform
> code and rely solely on Device Tree to do the probing for us.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:16:57 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:16:57 +0200
Subject: [PATCH 16/22] ARM: ux500: Stop registering the PCM driver from
 platform code
In-Reply-To: <1344527268-5964-17-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-17-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaGN3nh03sqvTic8oNXPmQisURJVx3nFZm7scuFzonN2A@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> We now initialise the PCM driver through the MSP DAI, so there is
> no need to register it though platform code anymore. This patch
> strips out all PCM platform registration.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:18:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:18:55 +0200
Subject: [PATCH 17/22] ARM: ux500: Remove platform registration of MSP
 devices
In-Reply-To: <1344527268-5964-18-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-18-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdayCNFq9_evUdyNTuXaJacnk1sHqOqebnOgvLYhYqxj8Q@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch removes platform device registration of all 4 MSP
> devices. It also takes care of all redundant infrastructure now
> that each of the ux500 audio components have been Device Tree
> enabled.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

NOTE: it seems this patch set contains some churn. First you
add in the forked device init, put in a big chunk of code and
then in the *same* patch set delete it again. It's not like
we're dying to see all the development history... can this
be squashed down a bit?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:20:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:20:32 +0200
Subject: [PATCH 18/22] ARM: ux500: Rename MSP board file to something more
 meaningful
In-Reply-To: <1344527268-5964-19-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-19-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaJcfLNzZ4s4NOyBLROjNbNfP8m0EewFkwe6tTrCS-Hog@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> The 'msp' board file does more than just register MSP devices. It
> also registers some other components necessary to get audio working
> on ux500 based platforms; such as the PCM and Machine Drivers. For
> that reason we're changing the filename to be more encompassing -
> 'audio'.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Ideally I want Ola to confirm this but it looks OK to me.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Consider using git format-patch -m which detects renames
and makes for much more compact patches.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:22:20 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:22:20 +0200
Subject: [PATCH 19/22] ARM: ux500: Rename db8500.dtsi to dbx5x0.dtsi to
 encompass the u9500, u8540 and u9540
In-Reply-To: <1344527268-5964-20-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-20-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYjEi7Kefc3wW-+d=RoFx4zT9j6BjqRHy5jr6RB_=fyzg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

This patch has nothing to do with the other patches in this series.

Send it to the ARM SoC maintainers as a separate patch and
use git format-patch -m, because git is good at detecting renames.

Atleast move it to the beginning of the patch series.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:23:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:23:22 +0200
Subject: [PATCH 20/22] ARM: ux500: Add nodes for the MSP into Device Tree
In-Reply-To: <1344527268-5964-21-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-21-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZFfV7uM75Xq=V-E2H_7LsX9dfmXNatWpBOiN4acJO9yA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch inserts all known MSP devices into the DBx5x0 Device Tree
> disabled and enables the two important ones for the Snowball low-cost
> development board.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:23:54 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:23:54 +0200
Subject: [PATCH 21/22] ARM: ux500: Add all encompassing sound node to the
 Snowball Device Tree
In-Reply-To: <1344527268-5964-22-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-22-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZzq_zrC247iFFf4UE-5hXZzTxZwqqDTDy6j2ez4ArfEw@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This is where we link together all of the SoC sound components for
> a given platform. This all encompassing sound node is only found
> in the very lowest hierarchical DTS file, since the component mix may
> well change from board variant to board variant.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:24:34 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:24:34 +0200
Subject: [PATCH 22/22] Documentation: Add the AB8500 CODEC device to the
 MFD AB8500 doc
In-Reply-To: <1344527268-5964-23-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-23-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ14n+V0buCnk1OiCDEpWC-1X+Qz32vpwi3DU+D7xgFXA@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Here we document the AB8500 Audio CODEC in the existing MFD AB8500 document.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 14 07:34:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 14 Aug 2012 13:34:22 +0200
Subject: [PATCH 00/22] mop500 related Audio reorganisation and fixups
In-Reply-To: <20120809185029.GC24328@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <20120809185029.GC24328@opensource.wolfsonmicro.com>
Message-ID: <CACRpkdZMyR3FXcoRHEAuoyx8B6+4sMuKjeRdg9+TD14XzqO7Yg@mail.gmail.com>

On Thu, Aug 9, 2012 at 8:50 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:

> On Thu, Aug 09, 2012 at 04:47:26PM +0100, Lee Jones wrote:
>> Another fine instalment of Audio fixes and Device Tree enablement
>> surrounding the mop500 sound driver. Hopefully containing all of
>> the recommendations suggested by Mark Brown.
>
> Can we have some review of this from the ARM side please?  It's pretty
> big...

I looked over it, merged two patches to ux500 fixes and ACKed these
I understand. For the patches mainly dealing with ALSA SoC I get
confused so would prefer to have Ola Lilja comment on those once
he's available.

Yours,
Linus Walleij


From s.hauer at pengutronix.de  Tue Aug 14 07:40:59 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 14 Aug 2012 13:40:59 +0200
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
In-Reply-To: <CAKGA1bnRA61JT8tQoHBay+6BSxDO5egiagQm1v05L7Asf+qJ+Q@mail.gmail.com>
References: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
 <20120813193517.GU1451@pengutronix.de>
 <CAKGA1bnRA61JT8tQoHBay+6BSxDO5egiagQm1v05L7Asf+qJ+Q@mail.gmail.com>
Message-ID: <20120814114059.GX1451@pengutronix.de>

On Mon, Aug 13, 2012 at 05:28:17PM -0500, Matt Sealey wrote:
>  IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /*
> MX51_PAD_EIM_DA15__EIM_DA15 */
> 
> 
> 
> On Mon, Aug 13, 2012 at 2:35 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > Hi Dave,
> >
> > On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:
> >> Because FIQ handlers get copied straight into the vectors page to
> >> the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
> >> start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
> >> Thumb-2.
> >
> > I finally came along testing this. I have no Thumb2 capable hardware
> > to test if it works in thumb2 mode, but at least in Arm mode it works.
> > This is enough to not introduce a regression, so we can go for this.
> 
> This is the interesting dichotomy; the code is only required truly on
> devices where Thumb2 isn't available, right?

It is also used on the i.MX51 Eukrea board. I asked Eric (Cced) to test
it in thumb2 mode, no response so far. I don't know the reason why he
uses FIQ mode instead of SDMA, maybe simply historical reasons.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tixy at linaro.org  Tue Aug 14 07:52:31 2012
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Tue, 14 Aug 2012 12:52:31 +0100
Subject: [PATCH] cpuidle: Prevent null pointer dereference in
 cpuidle_coupled_cpu_notify
Message-ID: <1344945151.2674.56.camel@linaro1.home>

When a kernel is built to support multiple hardware types it's possible
that CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is set but the hardware the
kernel is run on doesn't support cpuidle and therefore doesn't load a
driver for it. In this case, when the system is shut down,
cpuidle_coupled_cpu_notify() gets called with cpuidle_devices set to
NULL. There are quite possibly other circumstances where this
situation can also occur and we should check for it.

Signed-off-by: Jon Medhurst <tixy at linaro.org>
---

Would a better fix be to delay registering the notifier until
cpuidle_coupled_register_device() is called? Though following through
with that logic would require unregistering the notifier when cpuidle
driver is unregistered and it still seems possible that there would
still be a window of opportunity for things to go wrong.


 drivers/cpuidle/coupled.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 2c9bf26..c78a5ff 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -681,7 +681,7 @@ static int cpuidle_coupled_cpu_notify(struct notifier_block *nb,
 	mutex_lock(&cpuidle_lock);
 
 	dev = per_cpu(cpuidle_devices, cpu);
-	if (!dev->coupled)
+	if (!dev || !dev->coupled)
 		goto out;
 
 	switch (action & ~CPU_TASKS_FROZEN) {
-- 
1.7.10.4






From tiwai at suse.de  Tue Aug 14 08:17:18 2012
From: tiwai at suse.de (Takashi Iwai)
Date: Tue, 14 Aug 2012 14:17:18 +0200
Subject: [alsa-devel] [PATCH 08/22] ASoC: codecs: Enable AB8500 CODEC
 for	Device Tree
In-Reply-To: <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
Message-ID: <s5h628lu0q9.wl%tiwai@suse.de>

At Thu,  9 Aug 2012 16:47:34 +0100,
Lee Jones wrote:
> @@ -2407,6 +2464,30 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
>  	/* Setup AB8500 according to board-settings */
>  	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
>  
> +	if (np) {
> +		if (!pdata)
> +			pdata = devm_kzalloc(dev,
> +					sizeof(struct ab8500_platform_data),
> +					GFP_KERNEL);
> +
> +		if (!pdata->codec)

The NULL check of pdata must be before pdata->codec access.


Takashi

> +			pdata->codec
> +				= devm_kzalloc(dev,
> +					sizeof(struct ab8500_codec_platform_data),
> +					GFP_KERNEL);
> +
> +		if (!(pdata && pdata->codec))
> +			return -ENOMEM;
> +
> +		ab8500_codec_of_probe(dev, np, pdata->codec);
> +
> +	} else {
> +		if (!(pdata && pdata->codec)) {
> +			dev_err(dev, "No codec platform data or DT found\n");
> +			return -EINVAL;
> +		}
> +	}
> +
>  	/* Inform SoC Core that we have our own I/O arrangements. */
>  	codec->control_data = (void *)true;
>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
> 


From tiwai at suse.de  Tue Aug 14 08:17:15 2012
From: tiwai at suse.de (Takashi Iwai)
Date: Tue, 14 Aug 2012 14:17:15 +0200
Subject: [alsa-devel] [PATCH 03/22] ASoC: ab8500: Inform SoC Core that
 we	have our own I/O arrangements
In-Reply-To: <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
Message-ID: <s5h7gt1u0qc.wl%tiwai@suse.de>

At Thu,  9 Aug 2012 16:47:29 +0100,
Lee Jones wrote:
> 
> If codec->control_data is not populated SoC Core assumes we want to
> use regmap, which fails catastrophically, as we don't have one:
> 
> Unable to handle kernel NULL pointer dereference at virtual address 00000080
> pgd = c0004000
> [00000080] *pgd=00000000
> Internal error: Oops: 17 [#1] PREEMPT SMP ARM
> Modules linked in:
> CPU: 1    Not tainted  (3.5.0-rc6-00884-g0b2419e-dirty #130)
> PC is at regmap_read+0x10/0x5c
> LR is at hw_read+0x80/0x90
> pc : [<c01a91b8>]    lr : [<c0216804>]    psr: 60000013
> 
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

This was already fixed in ASoC core on Linus tree...


Takashi

> ---
>  sound/soc/codecs/ab8500-codec.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
> index 3c79592..23b4018 100644
> --- a/sound/soc/codecs/ab8500-codec.c
> +++ b/sound/soc/codecs/ab8500-codec.c
> @@ -2406,6 +2406,10 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
>  
>  	/* Setup AB8500 according to board-settings */
>  	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
> +
> +	/* Inform SoC Core that we have our own I/O arrangements. */
> +	codec->control_data = (void *)true;
> +
>  	status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
>  	if (status < 0) {
>  		pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
> 


From nsekhar at ti.com  Tue Aug 14 08:28:20 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue, 14 Aug 2012 17:58:20 +0530
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions
 for VPIF
In-Reply-To: <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
Message-ID: <502A4464.3020706@ti.com>

Hi Prabhakar,

On 7/24/2012 1:13 PM, Prabhakar Lad wrote:
> From: Manjunath Hadli <manjunath.hadli at ti.com>
> 
> Add clock, pin mux definitions and registration function for
> VPIF capture and display driver on DA850/OMAP-L138 SoC.
> 
> Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
> Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> ---
>  arch/arm/mach-davinci/da850.c              |  256 ++++++++++++++++++++++++++++
>  arch/arm/mach-davinci/include/mach/da8xx.h |   11 ++
>  arch/arm/mach-davinci/include/mach/mux.h   |   42 +++++
>  arch/arm/mach-davinci/include/mach/psc.h   |    1 +
>  4 files changed, 310 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index b44dc84..c864431 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -347,6 +347,13 @@ static struct clk spi1_clk = {
>  	.flags		= DA850_CLK_ASYNC3,
>  };
>  
> +static struct clk vpif_clk = {
> +	.name		= "vpif",
> +	.parent		= &pll0_sysclk2,
> +	.lpsc		= DA850_LPSC1_VPIF,
> +	.gpsc		= 1,
> +};
> +
>  static struct clk sata_clk = {
>  	.name		= "sata",
>  	.parent		= &pll0_sysclk2,
> @@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = {
>  	CLK(NULL,		"usb20",	&usb20_clk),
>  	CLK("spi_davinci.0",	NULL,		&spi0_clk),
>  	CLK("spi_davinci.1",	NULL,		&spi1_clk),
> +	CLK(NULL,		"vpif",		&vpif_clk),

You should dev_id for lookup instead of con_id. Looking at
drivers/media/video/davinci/vpif.c, there is a single clock that VPIF
needs, so con_id can actually be passed as NULL.

>  	CLK("ahci",		NULL,		&sata_clk),
>  	CLK(NULL,		NULL,		NULL),
>  };
> @@ -573,6 +581,46 @@ static const struct mux_config da850_pins[] = {
>  	MUX_CFG(DA850, GPIO6_10,	13,	20,	15,	8,	false)
>  	MUX_CFG(DA850, GPIO6_13,	13,	8,	15,	8,	false)
>  	MUX_CFG(DA850, RTC_ALARM,	0,	28,	15,	2,	false)
> +	/* VPIF Capture */
> +	MUX_CFG(DA850, VPIF_DIN0,	15,	4,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN1,	15,	0,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN2,	14,	28,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN3,	14,	24,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN4,	14,	20,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN5,	14,	16,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN6,	14,	12,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN7,	14,	8,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN8,	16,	4,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN9,	16,	0,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN10,	15,	28,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN11,	15,	24,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN12,	15,	20,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN13,	15,	16,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN14,	15,	12,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DIN15,	15,	8,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKIN0,	14,	0,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKIN1,	14,	4,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKIN2,	19,	8,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKIN3,	19,	16,	15,	1,	false)
> +	/* VPIF Display */
> +	MUX_CFG(DA850, VPIF_DOUT0,	17,	4,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT1,	17,	0,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT2,	16,	28,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT3,	16,	24,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT4,	16,	20,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT5,	16,	16,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT6,	16,	12,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT7,	16,	8,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT8,	18,	4,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT9,	18,	0,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT10,	17,	28,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT11,	17,	24,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT12,	17,	20,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT13,	17,	16,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT14,	17,	12,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_DOUT15,	17,	8,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKO2,	19,	12,	15,	1,	false)
> +	MUX_CFG(DA850, VPIF_CLKO3,	19,	20,	15,	1,	false)
>  #endif
>  };
>  
> @@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initdata = {
>  	-1
>  };
>  
> +const short da850_vpif_capture_pins[] __initdata = {
> +	DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
> +	DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
> +	DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
> +	DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
> +	DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
> +	DA850_VPIF_CLKIN3,
> +	-1
> +};
> +
> +const short da850_vpif_display_pins[] __initdata = {
> +	DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
> +	DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
> +	DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
> +	DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
> +	DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
> +	DA850_VPIF_CLKO3,
> +	-1
> +};
> +
>  /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
>  static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
>  	[IRQ_DA8XX_COMMTX]		= 7,
> @@ -1064,6 +1132,194 @@ no_ddrpll_mem:
>  	return ret;
>  }
>  
> +/* VPIF resource, platform data */
> +static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
> +
> +static struct resource da850_vpif_resource[] = {
> +	{
> +		.start	= DA8XX_VPIF_BASE,
> +		.end	= DA8XX_VPIF_BASE + 0xfff,
> +		.flags	= IORESOURCE_MEM,
> +	}
> +};
> +
> +static struct platform_device da850_vpif_dev = {
> +	.name		= "vpif",
> +	.id		= -1,
> +	.dev		= {
> +			.dma_mask		= &da850_vpif_dma_mask,
> +			.coherent_dma_mask	= DMA_BIT_MASK(32),
> +	},
> +	.resource	= da850_vpif_resource,
> +	.num_resources	= ARRAY_SIZE(da850_vpif_resource),
> +};
> +
> +static unsigned long vpif_disp_cont_buf_offset;
> +
> +static int __init cfg_vpif_disp_cont_buf_offset(char *p)
> +{
> +	if (!p)
> +		return 0;
> +
> +	return kstrtoul(p, 10, &vpif_disp_cont_buf_offset);
> +}
> +early_param("vpif_disp_cont_buf_offset", cfg_vpif_disp_cont_buf_offset);
> +
> +static unsigned long vpif_disp_cont_bufsize;
> +
> +static int __init cfg_vpif_disp_cont_bufsize(char *p)
> +{
> +	if (!p)
> +		return 0;
> +
> +	return kstrtoul(p, 10, &vpif_disp_cont_bufsize);
> +}
> +early_param("vpif_disp_cont_bufsize", cfg_vpif_disp_cont_bufsize);
> +
> +static unsigned long vpif_cap_cont_buf_offset;
> +
> +static int __init cfg_vpif_cap_cont_buf_offset(char *p)
> +{
> +	if (!p)
> +		return 0;
> +
> +	return kstrtoul(p, 10, &vpif_cap_cont_buf_offset);
> +}
> +early_param("vpif_cap_cont_buf_offset", cfg_vpif_cap_cont_buf_offset);
> +
> +static unsigned long vpif_cap_cont_bufsize;
> +
> +static int __init cfg_vpif_cap_cont_bufsize(char *p)
> +{
> +	if (!p)
> +		return 0;
> +
> +	return kstrtoul(p, 10, &vpif_cap_cont_bufsize);
> +}
> +early_param("vpif_cap_cont_bufsize", cfg_vpif_cap_cont_bufsize);


All these kernel parameters will need to be documented in
Documentation/kernel-parameters.txt. I suspect they should rather be
module parameters?

> +
> +static struct platform_device da850_vpif_display_dev = {
> +	.name		= "vpif_display",
> +	.id		= -1,
> +	.dev		= {
> +		.dma_mask		= &da850_vpif_dma_mask,
> +		.coherent_dma_mask	= DMA_BIT_MASK(32),
> +	},
> +};
> +
> +static struct platform_device da850_vpif_capture_dev = {
> +	.name		= "vpif_capture",
> +	.id		= -1,
> +	.dev		= {
> +		.dma_mask		= &da850_vpif_dma_mask,
> +		.coherent_dma_mask	= DMA_BIT_MASK(32),
> +	},
> +};
> +
> +int __init da850_register_vpif(void)
> +{
> +	return platform_device_register(&da850_vpif_dev);
> +}
> +
> +int __init da850_register_vpif_display(struct vpif_display_config
> +						*display_config)
> +{
> +	struct resource da850_vpif_display_resource[] = {
> +		{
> +			.start = IRQ_DA850_VPIFINT,
> +			.end   = IRQ_DA850_VPIFINT,
> +			.flags = IORESOURCE_IRQ,
> +		},
> +		{},
> +	};
> +	unsigned long phys_end_kernel;
> +	int ret;
> +
> +	if (vpif_disp_cont_bufsize) {
> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
> +					(num_physpages << PAGE_SHIFT);
> +		phys_end_kernel += vpif_disp_cont_buf_offset;
> +		da850_vpif_display_resource[1].start = phys_end_kernel;
> +		da850_vpif_display_resource[1].end = phys_end_kernel +
> +						vpif_disp_cont_bufsize - 1;
> +		da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
> +
> +		if (!request_mem_region(da850_vpif_display_resource[1].start,
> +				resource_size(&da850_vpif_display_resource[1]),
> +				da850_vpif_display_dev.name)) {
> +			pr_err("region already claimed.\n");
> +			return -EBUSY;
> +		}
> +		ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
> +				phys_end_kernel, phys_end_kernel,
> +				vpif_disp_cont_bufsize,
> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +
> +		if (!ret)
> +			return -ENOMEM;
> +	}
> +	ret = platform_device_add_resources(&da850_vpif_display_dev,
> +				da850_vpif_display_resource,
> +				ARRAY_SIZE(da850_vpif_display_resource));

You are taking memory at the end of RAM and passing it as a IO resource
to the driver. This is not correct. For contiguous memory needs can you
look at the recently merged CMA framework (include/linux/dma-contiguous.h)

> +	if (ret)
> +		return -EINVAL;
> +
> +	da850_vpif_display_dev.dev.platform_data = display_config;
> +	return platform_device_register(&da850_vpif_display_dev);
> +}
> +
> +int __init da850_register_vpif_capture(struct vpif_capture_config
> +							*capture_config)
> +{
> +	static struct resource da850_vpif_capture_resource[] = {
> +		{
> +			.start = IRQ_DA850_VPIFINT,
> +			.end   = IRQ_DA850_VPIFINT,
> +			.flags = IORESOURCE_IRQ,
> +		},
> +		{
> +			.start = IRQ_DA850_VPIFINT,
> +			.end   = IRQ_DA850_VPIFINT,
> +			.flags = IORESOURCE_IRQ,
> +		},
> +		{},
> +	};
> +	unsigned long phys_end_kernel;
> +	int ret;
> +
> +	if (vpif_cap_cont_bufsize) {
> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
> +					(num_physpages << PAGE_SHIFT);
> +		phys_end_kernel += vpif_cap_cont_buf_offset;
> +		da850_vpif_capture_resource[2].start = phys_end_kernel;
> +		da850_vpif_capture_resource[2].end = phys_end_kernel +
> +						vpif_cap_cont_bufsize - 1;
> +		da850_vpif_capture_resource[2].flags = IORESOURCE_MEM;
> +
> +		if (!request_mem_region(da850_vpif_capture_resource[2].start,
> +				resource_size(&da850_vpif_capture_resource[2]),
> +				da850_vpif_capture_dev.name)) {
> +			pr_err("region already claimed.\n");
> +			return -EBUSY;
> +		}
> +		ret = dma_declare_coherent_memory(&da850_vpif_capture_dev.dev,
> +				phys_end_kernel, phys_end_kernel,
> +				vpif_cap_cont_bufsize, DMA_MEMORY_MAP |
> +				DMA_MEMORY_EXCLUSIVE);
> +
> +		if (!ret)
> +			return -ENOMEM;
> +	}
> +	ret = platform_device_add_resources(&da850_vpif_capture_dev,
> +				da850_vpif_capture_resource,
> +				ARRAY_SIZE(da850_vpif_capture_resource));

The capture has the same problems as the display part above.

> +	if (ret)
> +		return -EINVAL;
> +
> +	da850_vpif_capture_dev.dev.platform_data = capture_config;
> +	return platform_device_register(&da850_vpif_capture_dev);
> +}
> +
>  static struct davinci_soc_info davinci_soc_info_da850 = {
>  	.io_desc		= da850_io_desc,
>  	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
> diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
> index a2f1f27..0028bd7 100644
> --- a/arch/arm/mach-davinci/include/mach/da8xx.h
> +++ b/arch/arm/mach-davinci/include/mach/da8xx.h
> @@ -16,6 +16,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/davinci_emac.h>
>  #include <linux/spi/spi.h>
> +#include <linux/videodev2.h>
>  
>  #include <mach/serial.h>
>  #include <mach/edma.h>
> @@ -26,6 +27,8 @@
>  #include <mach/pm.h>
>  #include <mach/spi.h>
>  
> +#include <media/davinci/vpif_types.h>
> +
>  extern void __iomem *da8xx_syscfg0_base;
>  extern void __iomem *da8xx_syscfg1_base;
>  
> @@ -69,6 +72,7 @@ extern unsigned int da850_max_speed;
>  #define DA8XX_AEMIF_CS3_BASE	0x62000000
>  #define DA8XX_AEMIF_CTL_BASE	0x68000000
>  #define DA8XX_ARM_RAM_BASE	0xffff0000
> +#define DA8XX_VPIF_BASE		0x01e17000

These are sorted in increasing order of address. This helps avoid
duplicates.

Thanks,
Sekhar


From tony at atomide.com  Tue Aug 14 04:29:12 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 14 Aug 2012 01:29:12 -0700
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
Message-ID: <20120814082911.GG11011@atomide.com>

Hi,

* Paul Walmsley <paul at pwsan.com> [120726 13:07]:
> On Wed, 25 Jul 2012, Paul Walmsley wrote:
> 
> > These IP blocks and the ECAP IP blocks have periods in their names.
> > The rest of the IP block named in the file don't use periods -- which
> > is also the style used by the rest of the OMAP SoCs.  Is there
> > some reason that these have periods in their names?
> 
> I've changed those to match the rest of the names, and queued the 
> following for 3.7.
> 
> Thanks again for all the hard work you all put into this.  I realize that 
> with all the upstream changes, this was probably a little painful for you. 
> But from my perspective you've been a pleasure to work with through the 
> process.

As am33xx and omap5 are DT only, we should start moving towards getting
rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
data from .dtsi files instead.

Alternatively we could get rid of the names and match the module based on
pa_start and pa_end.

Regards,

Tony


From js at sig21.net  Tue Aug 14 08:39:37 2012
From: js at sig21.net (Johannes Stezenbach)
Date: Tue, 14 Aug 2012 14:39:37 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <50299142.2030504@oberhumer.com>
References: <50299142.2030504@oberhumer.com>
Message-ID: <20120814123937.GA14756@sig21.net>

On Tue, Aug 14, 2012 at 01:44:02AM +0200, Markus F.X.J. Oberhumer wrote:
> On 2012-07-16 20:30, Markus F.X.J. Oberhumer wrote:
> >
> > As stated in the README this version is significantly faster (typically more
> > than 2 times faster!) than the current version, has been thoroughly tested on
> > x86_64/i386/powerpc platforms and is intended to get included into the
> > official Linux 3.6 or 3.7 release.
> >
> > I encourage all compression users to test and benchmark this new version,
> > and I also would ask some official LZO maintainer to convert the updated
> > source files into a GIT commit and possibly push it to Linus or linux-next.

Sorry for not reporting earlier, but I didn't have time to do real
benchmarks, just a quick test on ARM926EJ-S using barebox,
and found in the new version decompression is slower:
http://lists.infradead.org/pipermail/barebox/2012-July/008268.html

BTW, do you have userspace code matching the old and new
lzo versions?  It would be easier to benchmark.

Unfortunately I cannot claim high confidence in my benchmark results
due to missing time to do it properly, it would be useful if
someone else could do some benchmarks on ARM before merging this.


Johannes


From gururaja.hebbar at ti.com  Tue Aug 14 08:42:05 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:05 +0530
Subject: [PATCH 5/5] ASoC: tlv320aic3x: Add device tree bindings
In-Reply-To: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344948125-5649-6-git-send-email-gururaja.hebbar@ti.com>

Device tree support for tlv320aic3x CODEC driver.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:000000 100644 0000000... f4dee26... A	Documentation/devicetree/bindings/sound/tlv320aic3x.txt
:100644 100644 01485bd... 91fc421... M	sound/soc/codecs/tlv320aic3x.c
 .../devicetree/bindings/sound/tlv320aic3x.txt      |   18 ++++++++++++
 sound/soc/codecs/tlv320aic3x.c                     |   30 ++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
new file mode 100644
index 0000000..f4dee26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
@@ -0,0 +1,18 @@
+Texas Instruments - tlv320aic3x Codec module
+
+The tlv320aic3x serial control bus communicates through I2C protocols
+
+Required properties:
+- compatible - "string" -  "ti,tlv320aic3x"
+- reg - <int> -  I2C slave address
+- gpio-reset - <int> -  gpio pin number used for codec reset
+- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
+
+Example:
+
+tlv320aic3x: tlv320aic3x at 1b {
+	compatible = "ti,tlv320aic3x";
+	reg = <0x1b>;
+	gpio-reset = <60>;
+	ai3x-gpio-func = <0 5>;
+};
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 01485bd..91fc421 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -1457,6 +1457,9 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
 {
 	struct aic3x_pdata *pdata = i2c->dev.platform_data;
 	struct aic3x_priv *aic3x;
+	struct aic3x_setup_data *ai3x_setup;
+	struct device_node *np = i2c->dev.of_node;
+	u32 val;
 	int ret;
 
 	aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
@@ -1471,6 +1474,24 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
 	if (pdata) {
 		aic3x->gpio_reset = pdata->gpio_reset;
 		aic3x->setup = pdata->setup;
+	} else if (np) {
+		ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
+								GFP_KERNEL);
+		if (ai3x_setup == NULL) {
+			dev_err(&i2c->dev, "failed to create private data\n");
+			return -ENOMEM;
+		}
+
+		if (of_property_read_u32(np, "gpio-reset", &val) >= 0)
+			aic3x->gpio_reset = val;
+		else
+			aic3x->gpio_reset = -1;
+
+		if (of_property_read_u32_array(np, "ai3x-gpio-func",
+					ai3x_setup->gpio_func, 2) >= 0) {
+			aic3x->setup = ai3x_setup;
+		}
+
 	} else {
 		aic3x->gpio_reset = -1;
 	}
@@ -1488,11 +1509,20 @@ static int aic3x_i2c_remove(struct i2c_client *client)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id tlv320aic3x_of_match[] = {
+	{ .compatible = "ti,tlv320aic3x", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
+#endif
+
 /* machine i2c codec control layer */
 static struct i2c_driver aic3x_i2c_driver = {
 	.driver = {
 		.name = "tlv320aic3x-codec",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(tlv320aic3x_of_match),
 	},
 	.probe	= aic3x_i2c_probe,
 	.remove = aic3x_i2c_remove,
-- 
1.7.1



From gururaja.hebbar at ti.com  Tue Aug 14 08:42:04 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:04 +0530
Subject: [PATCH 4/5] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344948125-5649-5-git-send-email-gururaja.hebbar@ti.com>

Device tree support for tlv320aic3x CODEC driver

When the board boots with device tree, the driver will receive card,
codec, dai interface details (like the card name, DAPM routing map,
phandle for the audio components described in the dts file, codec mclk
speed).

The card will be set up based on this information.
Since the routing is provided via DT we can mark the card fully routed
so core can take care of disconnecting the unused pins.

When here, code indentation and comment style is also fixed

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:000000 100644 0000000... d1cd767... A	Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
:100644 100644 0a95c0c... be8e4ed... M	sound/soc/davinci/davinci-evm.c
 .../bindings/sound/davinci-evm-audio.txt           |   52 ++++++
 sound/soc/davinci/davinci-evm.c                    |  187 +++++++++++++++++--
 2 files changed, 219 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
new file mode 100644
index 0000000..d1cd767
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -0,0 +1,52 @@
+* Texas Instruments SoC audio setups with TLV320AIC3X Codec
+
+Required properties:
+- compatible : "ti,davinci-evm-audio"
+- ti,model : The user-visible name of this sound complex.
+- ti,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the codec's pins, and the jacks on the board:
+
+  Codec pins:
+
+  * MIC3L
+  * MIC3R
+  * LINE1L
+  * LINE2L
+  * LINE1R
+  * LINE2R
+
+  Board connectors:
+
+  * Headphone Jack
+  * Line Out
+  * Mic Jack
+
+- ti,mcasp-controller : The phandle of the McASP controller
+- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
+- ti,pcm-node : The phandle of the pcm device
+- ti,codec-clock : The Codec Clock from the board
+
+- dai-data		: A list of DAI data used by SOC code to register
+			  DAI, Codecs platform.
+			  The string index "should" be as shown below.
+dai-data =
+"<DAI Name>", 		"<DAI Stream Name>",
+"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
+"<evm ops required, evm_ops or evm_spdif_ops>";
+
+Example:
+
+sound {
+	compatible = "ti,davinci-evm-audio";
+	ti,model = "DA830 EVM";
+	ti,audio-codec = <&tlv320aic3x>;
+	ti,mcasp-controller = <&mcasp1>;
+	ti,pcm-node = <&pcm>;
+	ti,codec-clock = <12000000>;
+	dai-data =
+		"TLV320AIC3X", 		"AIC3X",
+		"tlv320aic3x-hifi",	"true",
+		"evm-ops";
+};
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 0a95c0c..be8e4ed 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -34,27 +34,38 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_card *soc_card = codec->card;
+	struct device_node *np = soc_card->dev->of_node;
 	int ret = 0;
 	unsigned sysclk;
 
-	/* ASP1 on DM355 EVM is clocked by an external oscillator */
-	if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
-	    machine_is_davinci_dm365_evm())
-		sysclk = 27000000;
-
-	/* ASP0 in DM6446 EVM is clocked by U55, as configured by
-	 * board-dm644x-evm.c using GPIOs from U18.  There are six
-	 * options; here we "know" we use a 48 KHz sample rate.
-	 */
-	else if (machine_is_davinci_evm())
-		sysclk = 12288000;
-
-	else if (machine_is_davinci_da830_evm() ||
-				machine_is_davinci_da850_evm())
-		sysclk = 24576000;
-
-	else
-		return -EINVAL;
+	if (np) {
+		ret = of_property_read_u32(np, "ti,codec-clock", &sysclk);
+		if (ret < 0)
+			return ret;
+	} else {
+		/* ASP1 on DM355 EVM is clocked by an external oscillator */
+		if (machine_is_davinci_dm355_evm() ||
+			machine_is_davinci_dm6467_evm() ||
+			machine_is_davinci_dm365_evm())
+			sysclk = 27000000;
+
+		/*
+		 * ASP0 in DM6446 EVM is clocked by U55, as configured by
+		 * board-dm644x-evm.c using GPIOs from U18.  There are six
+		 * options; here we "know" we use a 48 KHz sample rate.
+		 */
+		else if (machine_is_davinci_evm())
+			sysclk = 12288000;
+
+		else if (machine_is_davinci_da830_evm() ||
+					machine_is_davinci_da850_evm())
+			sysclk = 24576000;
+
+		else
+			return -EINVAL;
+	}
 
 	/* set codec DAI configuration */
 	ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
@@ -127,13 +138,22 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_codec *codec = rtd->codec;
 	struct snd_soc_dapm_context *dapm = &codec->dapm;
+	struct device_node *np = codec->card->dev->of_node;
+	int ret;
 
 	/* Add davinci-evm specific widgets */
 	snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
 				  ARRAY_SIZE(aic3x_dapm_widgets));
 
-	/* Set up davinci-evm specific audio path audio_map */
-	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	if (np) {
+		ret = snd_soc_of_parse_audio_routing(codec->card,
+							"ti,audio-routing");
+		if (ret)
+			return ret;
+	} else {
+		/* Set up davinci-evm specific audio path audio_map */
+		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	}
 
 	/* not connected */
 	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
@@ -281,6 +301,115 @@ static struct snd_soc_card da850_snd_soc_card = {
 	.num_links = 1,
 };
 
+#if defined(CONFIG_OF)
+/*
+ * This struct is just used as place holder. It will be filled with
+ * data from dt node
+ */
+static struct snd_soc_dai_link evm_dai = {
+};
+
+/* davinci evm audio machine driver */
+static struct snd_soc_card evm_soc_card = {
+	.owner = THIS_MODULE,
+	.dai_link = &evm_dai,
+	.num_links = 1,
+};
+
+static int davinci_evm_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const char *stringPtr, *propname;
+	u32 val;
+	int ret = 0;
+
+	propname = "dai-data";
+	val = of_property_count_strings(np, propname);
+	if (val < 0)
+		return val;
+
+	ret = of_property_read_string_index(np, propname, 0, &evm_dai.name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 1,
+						&evm_dai.stream_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 2,
+						&evm_dai.codec_dai_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 3, &stringPtr);
+	if (ret < 0)
+		return ret;
+	else
+		if (strcasecmp(stringPtr, "true") == 0)
+			evm_dai.init = evm_aic3x_init;
+
+	ret = of_property_read_string_index(np, propname, 4, &stringPtr);
+	if (ret < 0) {
+		return ret;
+	} else {
+		if (strcasecmp(stringPtr, "evm-ops") == 0)
+			evm_dai.ops = &evm_ops;
+		else if (strcasecmp(stringPtr, "evm-spdif-ops") == 0)
+			evm_dai.ops = &evm_spdif_ops;
+	}
+
+	evm_dai.codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
+	if (!evm_dai.codec_of_node)
+		return -EINVAL;
+
+	evm_dai.cpu_dai_of_node = of_parse_phandle(np,
+						"ti,mcasp-controller", 0);
+	if (!evm_dai.cpu_dai_of_node)
+		return -EINVAL;
+
+	evm_dai.platform_of_node = of_parse_phandle(np, "ti,pcm-node", 0);
+	if (!evm_dai.platform_of_node)
+		return -EINVAL;
+
+	evm_soc_card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
+	if (ret)
+		return ret;
+
+	ret = snd_soc_register_card(&evm_soc_card);
+	if (ret)
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+
+	return ret;
+}
+
+static int __devexit davinci_evm_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(card);
+
+	return 0;
+}
+
+static const struct of_device_id davinci_evm_dt_ids[] = {
+	{ .compatible = "ti,davinci-evm-audio", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, davinci_mcasp_dt_ids);
+
+static struct platform_driver davinci_evm_driver = {
+	.probe		= davinci_evm_probe,
+	.remove		= __devexit_p(davinci_evm_remove),
+	.driver		= {
+		.name	= "davinci_evm",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(davinci_evm_dt_ids),
+	},
+};
+#endif
+
 static struct platform_device *evm_snd_device;
 
 static int __init evm_init(void)
@@ -288,6 +417,14 @@ static int __init evm_init(void)
 	struct snd_soc_card *evm_snd_dev_data;
 	int index;
 	int ret;
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		return platform_driver_register(&davinci_evm_driver);
+	}
+#endif
 
 	if (machine_is_davinci_evm()) {
 		evm_snd_dev_data = &dm6446_snd_soc_card_evm;
@@ -324,6 +461,16 @@ static int __init evm_init(void)
 
 static void __exit evm_exit(void)
 {
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		platform_driver_unregister(&davinci_evm_driver);
+		return;
+	}
+#endif
+
 	platform_device_unregister(evm_snd_device);
 }
 
-- 
1.7.1



From gururaja.hebbar at ti.com  Tue Aug 14 08:42:01 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:01 +0530
Subject: [PATCH 1/5] ASoC/ARM: Davinci: McASP: split asp header into platform
 and audio specific
In-Reply-To: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>

Davinci McASP header & driver are shared by few OMAP platforms (like
TI81xx, AM335x). Splitting asp header into Davinci platform specific
header and Audio specific header helps to share them across platforms.

Audio specific defines is moved to to common
<linux/platform_data/davinci_asp.h> so that the header can be
accessed by all related platforms.

While here, correct the header usage (remove multiple header
re-definitions and unused headers) and remove platform names from
structures comments and enum

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
---
:000000 100644 0000000... 8fd5238... A	arch/arm/mach-davinci/asp.h
:100644 100644 8db0fc6... 8661b20... M	arch/arm/mach-davinci/davinci.h
:100644 100644 783eab6... 593764c... M	arch/arm/mach-davinci/devices-da8xx.c
:100644 100644 678cd99... e47a3f0... M	arch/arm/mach-davinci/dm355.c
:100644 100644 a50d49de.. f473745... M	arch/arm/mach-davinci/dm365.c
:100644 100644 c8b8666... 0755d46... M	arch/arm/mach-davinci/dm644x.c
:100644 100644 9eb87c1... 97c0f8e... M	arch/arm/mach-davinci/dm646x.c
:100644 100644 a2f1f27... c74a6ab... M	arch/arm/mach-davinci/include/mach/da8xx.h
:100644 100644 9aa2409... 79c26aa... R056	arch/arm/mach-davinci/include/mach/asp.h	include/linux/platform_data/davinci_asp.h
:100644 100644 c80c20a... 0a95c0c... M	sound/soc/davinci/davinci-evm.c
:100644 100644 0a74b95... 6e281a7... M	sound/soc/davinci/davinci-i2s.c
:100644 100644 51479f9... 0de9ed6... M	sound/soc/davinci/davinci-mcasp.h
:100644 100644 97d77b2... fefb3d4... M	sound/soc/davinci/davinci-pcm.c
:100644 100644 c0d6c9b... faac225... M	sound/soc/davinci/davinci-pcm.h
 arch/arm/mach-davinci/asp.h                        |   49 +++++++++++++
 arch/arm/mach-davinci/davinci.h                    |    3 +-
 arch/arm/mach-davinci/devices-da8xx.c              |    1 +
 arch/arm/mach-davinci/dm355.c                      |    2 +-
 arch/arm/mach-davinci/dm365.c                      |    2 +-
 arch/arm/mach-davinci/dm644x.c                     |    2 +-
 arch/arm/mach-davinci/dm646x.c                     |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h         |    2 +-
 .../linux/platform_data/davinci_asp.h              |   73 ++++++--------------
 sound/soc/davinci/davinci-evm.c                    |    3 -
 sound/soc/davinci/davinci-i2s.c                    |    3 +-
 sound/soc/davinci/davinci-mcasp.h                  |    3 +-
 sound/soc/davinci/davinci-pcm.c                    |    1 -
 sound/soc/davinci/davinci-pcm.h                    |    3 +-
 14 files changed, 81 insertions(+), 68 deletions(-)

diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
new file mode 100644
index 0000000..8fd5238
--- /dev/null
+++ b/arch/arm/mach-davinci/asp.h
@@ -0,0 +1,49 @@
+/*
+ * TI DaVinci Audio definitions
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE	0x01E02000
+#define DAVINCI_ASP1_BASE	0x01E04000
+
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE	0x01D02000
+
+/* Bases of dm646x register banks */
+#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
+
+/* Bases of da850/da830 McASP0  register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX	2
+#define DAVINCI_DMA_ASP0_RX	3
+#define DAVINCI_DMA_ASP1_TX	8
+#define DAVINCI_DMA_ASP1_RX	9
+
+/* EDMA channels of dm646x */
+#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
+#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
+#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
+#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
+
+/* EDMA channels of da830 McASP1 */
+#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
+#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6..8661b20 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -22,10 +22,11 @@
 #include <linux/davinci_emac.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/hardware.h>
+#include <mach/edma.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 783eab6..593764c 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,6 +24,7 @@
 #include <mach/cpuidle.h>
 
 #include "clock.h"
+#include "asp.h"
 
 #define DA8XX_TPCC_BASE			0x01c00000
 #define DA8XX_TPTC0_BASE		0x01c08000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..e47a3f0 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -26,13 +26,13 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM355_UART2_BASE	(IO_PHYS + 0x206000)
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49d..f473745 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -29,7 +29,6 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
@@ -37,6 +36,7 @@
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..0755d46 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -23,12 +23,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 /*
  * Device specific clocks
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1..97c0f8e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -24,12 +24,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
 
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f27..c74a6ab 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -16,11 +16,11 @@
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
-#include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 #include <mach/pm.h>
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/include/linux/platform_data/davinci_asp.h
similarity index 56%
rename from arch/arm/mach-davinci/include/mach/asp.h
rename to include/linux/platform_data/davinci_asp.h
index 9aa2409..79c26aa 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -1,59 +1,26 @@
 /*
- * <mach/asp.h> - DaVinci Audio Serial Port support
+ * TI DaVinci Audio Serial Port support
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
  */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE	0x01E02000
-#define DAVINCI_ASP1_BASE	0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE	0x01D02000
-
-/* Bases of dm646x register banks */
-#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
-
-/* Bases of da850/da830 McASP0  register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX	2
-#define DAVINCI_DMA_ASP0_RX	3
-#define DAVINCI_DMA_ASP1_TX	8
-#define DAVINCI_DMA_ASP1_RX	9
-
-/* EDMA channels of dm646x */
-#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
-#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
-#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
-#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
-
-/* EDMA channels of da830 McASP1 */
-#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
-#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
+#ifndef __DAVINCI_ASP_H
+#define __DAVINCI_ASP_H
 
 struct snd_platform_data {
 	u32 tx_dma_offset;
 	u32 rx_dma_offset;
-	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
-	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
+	int asp_chan_q;	/* event queue number for ASP channel */
+	int ram_chan_q;	/* event queue number for RAM channel */
 	unsigned int codec_fmt;
 	/*
 	 * Allowing this is more efficient and eliminates left and right swaps
@@ -70,7 +37,7 @@ struct snd_platform_data {
 	 * and MCBSP_CLKS.
 	 * Depending on different hardware connections it is possible
 	 * to use this setting to change the behaviour of McBSP
-	 * driver. The dm365_clk_input_pin enum is available for dm365
+	 * driver.
 	 */
 	int clk_input_pin;
 
@@ -122,8 +89,8 @@ enum {
 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
 };
 
-enum dm365_clk_input_pin {
-	MCBSP_CLKR = 0,		/* DM365 */
+enum mcbsp_clk_input_pin {
+	MCBSP_CLKR = 0,		/* as in DM365 */
 	MCBSP_CLKS,
 };
 
@@ -134,4 +101,4 @@ enum dm365_clk_input_pin {
 #define DAVINCI_MCASP_IIS_MODE	0
 #define DAVINCI_MCASP_DIT_MODE	1
 
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
+#endif
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index c80c20a..0a95c0c 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -22,9 +22,6 @@
 #include <asm/dma.h>
 #include <asm/mach-types.h>
 
-#include <mach/asp.h>
-#include <mach/edma.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 #include "davinci-mcasp.h"
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 0a74b95..6e281a7 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -16,6 +16,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -23,8 +24,6 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <mach/asp.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
index 51479f9..0de9ed6 100644
--- a/sound/soc/davinci/davinci-mcasp.h
+++ b/sound/soc/davinci/davinci-mcasp.h
@@ -19,7 +19,8 @@
 #define DAVINCI_MCASP_H
 
 #include <linux/io.h>
-#include <mach/asp.h>
+#include <linux/platform_data/davinci_asp.h>
+
 #include "davinci-pcm.h"
 
 #define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_96000
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index 97d77b2..fefb3d4 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -23,7 +23,6 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
-#include <mach/edma.h>
 #include <mach/sram.h>
 
 #include "davinci-pcm.h"
diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
index c0d6c9b..faac225 100644
--- a/sound/soc/davinci/davinci-pcm.h
+++ b/sound/soc/davinci/davinci-pcm.h
@@ -12,9 +12,8 @@
 #ifndef _DAVINCI_PCM_H
 #define _DAVINCI_PCM_H
 
+#include <linux/platform_data/davinci_asp.h>
 #include <mach/edma.h>
-#include <mach/asp.h>
-
 
 struct davinci_pcm_dma_params {
 	int channel;			/* sync dma channel ID */
-- 
1.7.1



From gururaja.hebbar at ti.com  Tue Aug 14 08:42:00 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:00 +0530
Subject: [PATCH 0/5] ARM/ASoC: Davinci: Add Device Tree Support
Message-ID: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>

This patch-set is a cumulative of below tasks
1. Split asp header into platform and audio specific
   Davinci driver is shared by few OMAP platforms (like TI81xx, AM335x).
   Splitting asp header into Davinci platform specific and Audio specific helps
   to share them across platforms.

2. Add DT support for Davinci Audio Module (McASP, machine, pcm & Codec)


This patch was tested on AM18x Board (Tested to check if the commits doesn't
break on compile or runtime) and is based on repo at 
http://git.kernel.org/?p=linux/kernel/git/broonie/sound.git;
a=shortlog;h=refs/heads/for-3.7

Note:
Matt Porter from TI is working on DMA engine conversion of DaVinci EDMA
support and DT conversion of DMA parts will be taken up post that is
complete.
Since Audio requires DMA to work, this patch set does not yet provide
complete functionality required to use sound on DT-based platforms, but
is a step towards that direction.

Hebbar, Gururaja (5):
  ASoC/ARM: Davinci: McASP: split asp header into platform and audio
    specific
  ASoC: Davinci: McASP: add device tree support for McASP
  ASoC: Davinci: pcm: Add device tree bindings
  ASoC: Davinci: machine: Add device tree binding
  ASoC: tlv320aic3x: Add device tree bindings

 .../bindings/sound/davinci-evm-audio.txt           |   52 ++++++
 .../bindings/sound/davinci-mcasp-audio.txt         |   43 +++++
 .../devicetree/bindings/sound/davinci-pcm.txt      |   13 ++
 .../devicetree/bindings/sound/tlv320aic3x.txt      |   18 ++
 arch/arm/mach-davinci/asp.h                        |   49 +++++
 arch/arm/mach-davinci/davinci.h                    |    3 +-
 arch/arm/mach-davinci/devices-da8xx.c              |    1 +
 arch/arm/mach-davinci/dm355.c                      |    2 +-
 arch/arm/mach-davinci/dm365.c                      |    2 +-
 arch/arm/mach-davinci/dm644x.c                     |    2 +-
 arch/arm/mach-davinci/dm646x.c                     |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h         |    2 +-
 .../linux/platform_data/davinci_asp.h              |   73 ++------
 sound/soc/codecs/tlv320aic3x.c                     |   30 +++
 sound/soc/davinci/davinci-evm.c                    |  190 +++++++++++++++++---
 sound/soc/davinci/davinci-i2s.c                    |    3 +-
 sound/soc/davinci/davinci-mcasp.c                  |  113 ++++++++++++-
 sound/soc/davinci/davinci-mcasp.h                  |    3 +-
 sound/soc/davinci/davinci-pcm.c                    |   12 ++-
 sound/soc/davinci/davinci-pcm.h                    |    3 +-
 20 files changed, 527 insertions(+), 89 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
 create mode 100644 Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
 create mode 100644 Documentation/devicetree/bindings/sound/davinci-pcm.txt
 create mode 100644 Documentation/devicetree/bindings/sound/tlv320aic3x.txt
 create mode 100644 arch/arm/mach-davinci/asp.h
 rename arch/arm/mach-davinci/include/mach/asp.h => include/linux/platform_data/davinci_asp.h (56%)



From gururaja.hebbar at ti.com  Tue Aug 14 08:42:03 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:03 +0530
Subject: [PATCH 3/5] ASoC: Davinci: pcm: Add device tree bindings
In-Reply-To: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>

Device tree support for Davinci/OMAP2+ pcm driver.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:000000 100644 0000000... be494bb... A	Documentation/devicetree/bindings/sound/davinci-pcm.txt
:100644 100644 fefb3d4... 0765101... M	sound/soc/davinci/davinci-pcm.c
 .../devicetree/bindings/sound/davinci-pcm.txt      |   13 +++++++++++++
 sound/soc/davinci/davinci-pcm.c                    |   11 +++++++++++
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-pcm.txt b/Documentation/devicetree/bindings/sound/davinci-pcm.txt
new file mode 100644
index 0000000..be494bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-pcm.txt
@@ -0,0 +1,13 @@
+Texas Instruments - Davinci/OMAP2+ PCM module
+
+PCM module doesn't use/require any platform data. Hence only
+compatible field needs to be populated.
+
+Required properties:
+- compatible: "ti,davinci-pcm-audio"
+
+Example:
+
+pcm: davinci-pcm-audio {
+	compatible = "ti,davinci-pcm-audio";
+};
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index fefb3d4..0765101 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -16,6 +16,8 @@
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -874,10 +876,19 @@ static int __devexit davinci_soc_platform_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id davinci_pcm_dt_ids[] = {
+	{ .compatible = "ti,davinci-pcm-audio", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, davinci_pcm_dt_ids);
+#endif
+
 static struct platform_driver davinci_pcm_driver = {
 	.driver = {
 			.name = "davinci-pcm-audio",
 			.owner = THIS_MODULE,
+			.of_match_table = of_match_ptr(davinci_pcm_dt_ids),
 	},
 
 	.probe = davinci_soc_platform_probe,
-- 
1.7.1



From gururaja.hebbar at ti.com  Tue Aug 14 08:42:02 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 14 Aug 2012 18:12:02 +0530
Subject: [PATCH 2/5] ASoC: Davinci: McASP: add device tree support for McASP
In-Reply-To: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1344948125-5649-3-git-send-email-gururaja.hebbar@ti.com>

Add device tree probe for McASP driver.

Note:
DMA parameters are not populated from DT and will be done later.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:000000 100644 0000000... 692659e... A	Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
:100644 100644 6a2c54c... db7756a... M	sound/soc/davinci/davinci-mcasp.c
 .../bindings/sound/davinci-mcasp-audio.txt         |   43 ++++++++
 sound/soc/davinci/davinci-mcasp.c                  |  113 +++++++++++++++++++-
 2 files changed, 155 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
new file mode 100644
index 0000000..692659e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
@@ -0,0 +1,43 @@
+Texas Instruments McASP controller
+
+Required properties:
+- compatible :
+	"ti,dm646x-mcasp-audio"	: for DM646x platforms
+	"ti,da830-mcasp-audio"	: for both DA830 & DA850 platforms
+
+- reg : Should contain McASP registers offset and length
+- interrupts : Interrupt number for McASP
+- op-mode : I2S/DIT ops mode.
+- tdm-slots : Slots for TDM operation.
+- num-serializer : Serializers used by McASP.
+- serial-dir : A list of serializer pin mode. The list number should be equal
+		to "num-serializer" parameter. Each entry is a number indication
+		serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
+
+
+Optional properties:
+
+- ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0
+- tx-num-evt : FIFO levels.
+- rx-num-evt : FIFO levels.
+
+
+Example:
+
+mcasp0: mcasp0 at 1d00000 {
+	compatible = "ti,da830-mcasp-audio";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x100000 0x3000>;
+	interrupts = <82 83>;
+	op-mode = <0>;		/* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	num-serializer = <16>;
+	serial-dir = <
+			0 0 0 0	/* 0: INACTIVE, 1: TX, 2: RX */
+			0 0 0 0
+			0 0 0 1
+			2 0 0 0 >;
+	tx-num-evt = <1>;
+	rx-num-evt = <1>;
+};
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 6a2c54c..db7756a 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -22,6 +22,9 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -862,19 +865,127 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
 
 };
 
+static const struct of_device_id mcasp_dt_ids[] = {
+	{
+		.compatible = "ti,dm646x-mcasp-audio",
+		.data = (void *)MCASP_VERSION_1,
+	},
+	{
+		.compatible = "ti,da830-mcasp-audio",
+		.data = (void *)MCASP_VERSION_2,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
+
+static u8 of_serial_dir[16];
+
+static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
+						struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct snd_platform_data *pdata = NULL;
+	const struct of_device_id *match =
+			of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
+
+	const u32 *of_serial_dir32;
+	u32 val;
+	int i, ret = 0;
+
+	if (pdev->dev.platform_data) {
+		pdata = pdev->dev.platform_data;
+		return pdata;
+	} else if (match) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata) {
+			ret = -ENOMEM;
+			goto nodata;
+		}
+	} else {
+		/* control shouldn't reach here. something is wrong */
+		ret = -EINVAL;
+		goto nodata;
+	}
+
+	if (match->data)
+		pdata->version = (u8)((int)match->data);
+
+	ret = of_property_read_u32(np, "op-mode", &val);
+	if (ret < 0)
+		goto nodata;
+	pdata->op_mode = val;
+
+	ret = of_property_read_u32(np, "tdm-slots", &pdata->tdm_slots);
+	if (ret < 0)
+		goto nodata;
+
+	ret = of_property_read_u32(np, "num-serializer", &val);
+	if (ret < 0)
+		goto nodata;
+	pdata->num_serializer = val;
+
+	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
+	val /= sizeof(u32);
+	if (val != pdata->num_serializer) {
+		ret = -EINVAL;
+		goto nodata;
+	}
+
+	if (of_serial_dir32) {
+		for (i = 0; i < pdata->num_serializer; i++)
+			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
+
+		pdata->serial_dir = of_serial_dir;
+	}
+
+	ret = of_property_read_u32(np, "tx-num-evt", &val);
+	if (ret >= 0)
+		pdata->txnumevt = val;
+
+	ret = of_property_read_u32(np, "rx-num-evt", &val);
+	if (ret >= 0)
+		pdata->rxnumevt = val;
+
+	ret = of_property_read_u32(np, "sram-size-playback", &val);
+	if (ret >= 0)
+		pdata->sram_size_playback = val;
+
+	ret = of_property_read_u32(np, "sram-size-capture", &val);
+	if (ret >= 0)
+		pdata->sram_size_capture = val;
+
+nodata:
+	if (ret < 0)
+		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
+			ret);
+	return  pdata;
+}
+
 static int davinci_mcasp_probe(struct platform_device *pdev)
 {
 	struct davinci_pcm_dma_params *dma_data;
 	struct resource *mem, *ioarea, *res;
 	struct snd_platform_data *pdata;
 	struct davinci_audio_dev *dev;
+
 	int ret;
 
+	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
+		dev_err(&pdev->dev, "No platform data supplied\n");
+		return -EINVAL;
+	}
+
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
 			   GFP_KERNEL);
 	if (!dev)
 		return	-ENOMEM;
 
+	pdata = davinci_mcasp_set_pdata_from_of(pdev);
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data\n");
+		return -EINVAL;
+	}
+
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
 		dev_err(&pdev->dev, "no mem resource?\n");
@@ -888,7 +999,6 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	pdata = pdev->dev.platform_data;
 	pm_runtime_enable(&pdev->dev);
 
 	ret = pm_runtime_get_sync(&pdev->dev);
@@ -976,6 +1086,7 @@ static struct platform_driver davinci_mcasp_driver = {
 	.driver		= {
 		.name	= "davinci-mcasp",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mcasp_dt_ids),
 	},
 };
 
-- 
1.7.1



From nsekhar at ti.com  Tue Aug 14 09:00:43 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Tue, 14 Aug 2012 18:30:43 +0530
Subject: [PATCH 2/2] ARM: da850/omap-l138: Add EVM specific code for VPIF
 to work
In-Reply-To: <1343115786-15801-3-git-send-email-prabhakar.lad@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-3-git-send-email-prabhakar.lad@ti.com>
Message-ID: <502A4BFB.9020407@ti.com>

Hi Prabhakar,

On 7/24/2012 1:13 PM, Prabhakar Lad wrote:
> From: Manjunath Hadli <manjunath.hadli at ti.com>
> 
> Include the expander settings to select VPIF peripheral on
> UI card and add registration call in EVM init. Also add platform
> data to configure display and capture devices.
> 
> Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
> Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> ---
>  arch/arm/mach-davinci/Kconfig           |    9 ++
>  arch/arm/mach-davinci/board-da850-evm.c |  195 +++++++++++++++++++++++++++++++
>  2 files changed, 204 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
> index 32d837d..19ee4ee 100644
> --- a/arch/arm/mach-davinci/Kconfig
> +++ b/arch/arm/mach-davinci/Kconfig
> @@ -190,6 +190,15 @@ config DA850_UI_RMII
>  	  NOTE: Please take care while choosing this option, MII PHY will
>  	  not be functional if RMII mode is selected.
>  
> +config DA850_UI_SD_VIDEO_PORT
> +	bool "Video Port Interface"
> +	help
> +	  Say Y if you want to use Video Port Interface (VPIF) on the
> +	  DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
> +	  UI daughter card that is supplied with the EVM.
> +	  NOTE: Please make sure to disable RMII and CLCD options when you
> +	  select Video Port Interface.

RMII is in the same choice block as this so it is not possible to have
RMII enabled along with video port selection. On the CLCD, it will be
good to register only one of CLCD or video and print a warning if user
enabled both. davinci_evm_init() in
arch/arm/mach-davinci/board-dm644x-evm.c has an example of this.

> +
>  endchoice
>  
>  config DA850_WL12XX
> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> index 0149fb4..1f5d2c1 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -45,6 +45,8 @@
>  #include <mach/aemif.h>
>  #include <mach/spi.h>
>  
> +#include <media/tvp514x.h>
> +
>  #define DA850_EVM_PHY_ID		"davinci_mdio-0:00"
>  #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
>  #define DA850_LCD_BL_PIN		GPIO_TO_PIN(2, 15)
> @@ -121,6 +123,12 @@ static struct spi_board_info da850evm_spi_info[] = {
>  	},
>  };
>  
> +#define TVP5147_CH0		"tvp514x-0"
> +#define TVP5147_CH1		"tvp514x-1"
> +
> +#define VPIF_STATUS		0x002c
> +#define VPIF_STATUS_CLR		0x0030
> +
>  #ifdef CONFIG_MTD
>  static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
>  {
> @@ -452,6 +460,15 @@ static void da850_evm_ui_keys_init(unsigned gpio)
>  	}
>  }
>  
> +#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
> +static inline void da850_evm_setup_video_port(int video_sel)
> +{
> +	gpio_set_value_cansleep(video_sel, 0);
> +}
> +#else
> +static inline void da850_evm_setup_video_port(int video_sel) { }
> +#endif
> +
>  static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
>  						unsigned ngpio, void *c)
>  {
> @@ -497,6 +514,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
>  
>  	da850_evm_setup_emac_rmii(sel_a);
>  
> +	da850_evm_setup_video_port(sel_c);
> +
>  	return 0;
>  
>  exp_setup_keys_fail:
> @@ -1149,6 +1168,151 @@ static __init int da850_evm_init_cpufreq(void)
>  static __init int da850_evm_init_cpufreq(void) { return 0; }
>  #endif
>  
> +/* Retaining these APIs, since the VPIF drivers do not check NULL handlers */
> +static int da850_set_vpif_clock(int mux_mode, int hd)
> +{
> +	return 0;
> +}
> +
> +static int da850_setup_vpif_input_channel_mode(int mux_mode)
> +{
> +	return 0;
> +}
> +
> +int da850_vpif_setup_input_path(int ch, const char *name)
> +{
> +	return 0;
> +}

Why not enhance the VPIF driver to handle NULL values for these instead?

> +
> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
> +/* VPIF capture configuration */
> +static struct tvp514x_platform_data tvp5146_pdata = {
> +	.clk_polarity = 0,
> +	.hs_polarity = 1,
> +	.vs_polarity = 1
> +};
> +#endif
> +
> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
> +
> +static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)

Why not just continue with the previous #ifdef
CONFIG_DA850_UI_SD_VIDEO_PORT?

> +	{
> +		.name	= TVP5147_CH0,
> +		.board_info = {
> +			I2C_BOARD_INFO("tvp5146", 0x5d),
> +			.platform_data = &tvp5146_pdata,
> +		},
> +		.input = INPUT_CVBS_VI2B,
> +		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> +		.can_route = 1,
> +		.vpif_if = {
> +			.if_type = VPIF_IF_BT656,
> +			.hd_pol = 1,
> +			.vd_pol = 1,
> +			.fid_pol = 0,
> +		},
> +	},
> +	{
> +		.name	= TVP5147_CH1,
> +		.board_info = {
> +			I2C_BOARD_INFO("tvp5146", 0x5c),
> +			.platform_data = &tvp5146_pdata,
> +		},
> +		.input = INPUT_SVIDEO_VI2C_VI1C,
> +		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
> +		.can_route = 1,
> +		.vpif_if = {
> +			.if_type = VPIF_IF_BT656,
> +			.hd_pol = 1,
> +			.vd_pol = 1,
> +			.fid_pol = 0,
> +		},
> +	},
> +#endif
> +};
> +
> +static const struct vpif_input da850_ch0_inputs[] = {
> +	{
> +		.input = {
> +			.index = 0,
> +			.name = "Composite",
> +			.type = V4L2_INPUT_TYPE_CAMERA,
> +			.std = TVP514X_STD_ALL,
> +		},
> +		.subdev_name = TVP5147_CH0,
> +	},
> +};
> +
> +static const struct vpif_input da850_ch1_inputs[] = {
> +	{
> +		.input = {
> +			.index = 0,
> +			.name = "S-Video",
> +			.type = V4L2_INPUT_TYPE_CAMERA,
> +			.std = TVP514X_STD_ALL,
> +		},
> +		.subdev_name = TVP5147_CH1,
> +	},
> +};
> +
> +static struct vpif_capture_config da850_vpif_capture_config = {
> +	.setup_input_channel_mode = da850_setup_vpif_input_channel_mode,
> +	.setup_input_path = da850_vpif_setup_input_path,
> +	.subdev_info = da850_vpif_capture_sdev_info,
> +	.subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)

Same here.

> +	.chan_config[0] = {
> +		.inputs = da850_ch0_inputs,
> +		.input_count = ARRAY_SIZE(da850_ch0_inputs),
> +	},
> +	.chan_config[1] = {
> +		.inputs = da850_ch1_inputs,
> +		.input_count = ARRAY_SIZE(da850_ch1_inputs),
> +	},
> +#endif
> +	.card_name      = "DA850/OMAP-L138 Video Capture",
> +};
> +
> +/* VPIF display configuration */
> +static struct vpif_subdev_info da850_vpif_subdev[] = {
> +	{
> +		.name	= "adv7343",
> +		.board_info = {
> +			I2C_BOARD_INFO("adv7343", 0x2a),
> +		},
> +	},
> +};
> +
> +static const char const *vpif_output[] = {
> +	"Composite",
> +	"Component",
> +	"S-Video",
> +};
> +
> +static struct vpif_display_config da850_vpif_display_config = {
> +	.set_clock	= da850_set_vpif_clock,
> +	.subdevinfo	= da850_vpif_subdev,
> +	.subdev_count	= ARRAY_SIZE(da850_vpif_subdev),
> +	.output		= vpif_output,
> +	.output_count	= ARRAY_SIZE(vpif_output),
> +	.card_name	= "DA850/OMAP-L138 Video Display",
> +};
> +
> +#if defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) ||\
> +		defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY_MODULE)
> +#define HAS_VPIF_DISPLAY 1
> +#else
> +#define HAS_VPIF_DISPLAY 0
> +#endif
> +
> +#if defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) ||\
> +		defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE_MODULE)
> +#define HAS_VPIF_CAPTURE 1
> +#else
> +#define HAS_VPIF_CAPTURE 0
> +#endif
> +
>  #ifdef CONFIG_DA850_WL12XX
>  
>  static void wl12xx_set_power(int index, bool power_on)
> @@ -1375,6 +1539,37 @@ static __init void da850_evm_init(void)
>  		pr_warning("da850_evm_init: suspend registration failed: %d\n",
>  				ret);
>  
> +	if (HAS_VPIF_DISPLAY || HAS_VPIF_CAPTURE) {
> +		ret = da850_register_vpif();
> +		if (ret)
> +			pr_warn("da850_evm_init: VPIF setup failed: %d\n",
> +				   ret);
> +	}
> +
> +	if (HAS_VPIF_CAPTURE) {
> +		ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
> +		if (ret)
> +			pr_warn("da850_evm_init: VPIF capture mux failed:%d\n",
> +					ret);
> +
> +		ret = da850_register_vpif_capture(&da850_vpif_capture_config);
> +		if (ret)
> +			pr_warn("da850_evm_init: VPIF capture setup" \
> +			" failed: %d\n", ret);

Please don't break print messages.

> +	}
> +
> +	if (HAS_VPIF_DISPLAY) {
> +		ret = davinci_cfg_reg_list(da850_vpif_display_pins);
> +		if (ret)
> +			pr_warn("da850_evm_init : VPIF capture mux failed" \
> +			": %d\n", ret);
> +
> +		ret = da850_register_vpif_display(&da850_vpif_display_config);
> +		if (ret)
> +			pr_warn("da850_evm_init: VPIF display setup" \
> +			" failed: %d\n", ret);

Same here.

Thanks,
Sekhar


From richard.genoud at gmail.com  Tue Aug 14 09:49:14 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:14 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
Message-ID: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>

Nicolas,
I said that I had some work done on sam9g35-ek, here is the spi part, based
on your and Jean-Christophe work.
You have to enable CONFIG_ARCH_AT91SAM9X5 to get it work.

The goal of this patchset is to share the work I've done, it's not ready
for upstream, but it may save some time.

It's based on 3.6-rc1 + Jean-Christophe's pinctrl patchset.

Best Regards,
Richard.

Jean-Christophe PLAGNIOL-VILLARD (3):
  of: add dma-mask binding
  of_spi: add generic binding support to specify cs gpio
  spi/atmel: add DT support

Nicolas Ferre (6):
  spi/atmel_spi: trivial: change some comments
  spi/atmel_spi: add physical base address
  spi/atmel_spi: call unmapping on transfers buffers
  spi/atmel_spi: status information passed through controller data
  spi/atmel_spi: add flag to controller data for lock operations
  spi/atmel_spi: add dmaengine support

Richard Genoud (14):
  spi-atmel: update with dmaengine interface
  spi-atmel: fix __init/__devinit sections mismatch
  spi-atmel: Fix spi-atmel driver to adapt to slave_config changes
  AT91 DMA OF support
  add at91sam9x5 Kconfig ARCH/SOC link
  spi-atmel: add DMA OF support
  [BUG] SPI: array out of bound => no CS
  [BUG] atmel-spi && DMA: OOPS if buffer > 4400 bytes
  sam9x5: declare SPI clocks
  spi-atmel: add sam9x5 SPI in device tree
  spi-atmel: add dma support in sam9x5 device tree
  spi-atmel OF: complete documentation
  spi-atmel: complete DMA slave OF documentation
  sam9x5ek DTS: enable SPI dataflash

 Documentation/devicetree/bindings/spi/spi-bus.txt  |    6 +
 .../devicetree/bindings/spi/spi_atmel.txt          |   46 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   42 ++
 arch/arm/boot/dts/at91sam9x5ek.dtsi                |   10 +
 arch/arm/mach-at91/Kconfig                         |    4 +
 arch/arm/mach-at91/at91sam9x5.c                    |    3 +
 arch/arm/mach-at91/include/mach/at_hdmac.h         |    1 +
 drivers/of/Kconfig                                 |    4 +
 drivers/of/Makefile                                |    1 +
 drivers/of/of_atmel.c                              |  111 ++++
 drivers/of/platform.c                              |   23 +-
 drivers/spi/Kconfig                                |    9 +
 drivers/spi/spi-atmel.c                            |  611 ++++++++++++++++++--
 drivers/spi/spi.c                                  |   55 ++-
 include/linux/of_atmel.h                           |   29 +
 include/linux/spi/spi.h                            |    3 +
 16 files changed, 914 insertions(+), 44 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
 create mode 100644 drivers/of/of_atmel.c
 create mode 100644 include/linux/of_atmel.h

-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:15 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:15 +0200
Subject: [PATCH 01/23] of: add dma-mask binding
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-2-git-send-email-richard.genoud@gmail.com>

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

This will allow each device to specify its dma-mask for this we use the
coherent_dma_mask as pointer. By default the dma-mask will be set to
DMA_BIT_MASK(32).
The microblaze architecture hook is drop

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/of/platform.c |   23 ++++++++++++++++-------
 1 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index e44f8c2..11c765c 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -121,6 +121,21 @@ void of_device_make_bus_id(struct device *dev)
 	dev_set_name(dev, "%s.%d", node->name, magic - 1);
 }
 
+static void of_get_dma_mask(struct device *dev, struct device_node *np)
+{
+	const __be32 *prop;
+	int len;
+
+	prop = of_get_property(np, "dma-mask", &len);
+
+	dev->dma_mask = &dev->coherent_dma_mask;
+
+	if (!prop)
+		dev->coherent_dma_mask = DMA_BIT_MASK(32);
+	else
+		dev->coherent_dma_mask = of_read_number(prop, len / 4);
+}
+
 /**
  * of_device_alloc - Allocate and initialize an of_device
  * @np: device node to assign to device
@@ -161,10 +176,8 @@ struct platform_device *of_device_alloc(struct device_node *np,
 		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
 	}
 
+	of_get_dma_mask(&dev->dev, np);
 	dev->dev.of_node = of_node_get(np);
-#if defined(CONFIG_MICROBLAZE)
-	dev->dev.dma_mask = &dev->archdata.dma_mask;
-#endif
 	dev->dev.parent = parent;
 
 	if (bus_id)
@@ -201,10 +214,6 @@ struct platform_device *of_platform_device_create_pdata(
 	if (!dev)
 		return NULL;
 
-#if defined(CONFIG_MICROBLAZE)
-	dev->archdata.dma_mask = 0xffffffffUL;
-#endif
-	dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 	dev->dev.bus = &platform_bus_type;
 	dev->dev.platform_data = platform_data;
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:17 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:17 +0200
Subject: [PATCH 03/23] spi/atmel_spi: trivial: change some comments
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-4-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

To be accurate with introduction of dmaengine enabled driver.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/spi-atmel.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 16d6a83..7c41b07 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -201,6 +201,7 @@ struct atmel_spi {
 	struct spi_transfer	*next_transfer;
 	unsigned long		next_remaining_bytes;
 
+	/* scratch buffer */
 	void			*buffer;
 	dma_addr_t		buffer_dma;
 };
@@ -364,7 +365,7 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
 }
 
 /*
- * Submit next transfer for DMA.
+ * Submit next transfer for PDC.
  * lock is held, spi irq is blocked
  */
 static void atmel_spi_next_xfer(struct spi_master *master,
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:16 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:16 +0200
Subject: [PATCH 02/23] of_spi: add generic binding support to specify cs gpio
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-3-git-send-email-richard.genoud@gmail.com>

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

This will allow to use gpio for chip select with no modification in the
driver binding

When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
 Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
 drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
 include/linux/spi/spi.h                           |    3 +
 3 files changed, 61 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..c253379 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
     		recommended practice.
+- cs-gpios	  - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
 chip selects.  Individual drivers can define additional properties to
 support describing the chip select layout.
 
+If cs-gpios is used the number of chip select will automatically increased.
+
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
 - spi-cs-high     - (optional) Empty property indicating device requires
     		chip select active high
 
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
 SPI example for an MPC5200 SPI bus:
 	spi at f00 {
 		#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 84c2861..3fb5b6d 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -30,6 +30,7 @@
 #include <linux/slab.h>
 #include <linux/mod_devicetable.h>
 #include <linux/spi/spi.h>
+#include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 #include <linux/export.h>
 #include <linux/sched.h>
@@ -327,6 +328,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
 	spi->dev.parent = &master->dev;
 	spi->dev.bus = &spi_bus_type;
 	spi->dev.release = spidev_release;
+	spi->cs_gpio = -EINVAL;
 	device_initialize(&spi->dev);
 	return spi;
 }
@@ -344,15 +346,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
 int spi_add_device(struct spi_device *spi)
 {
 	static DEFINE_MUTEX(spi_add_lock);
-	struct device *dev = spi->master->dev.parent;
+	struct spi_master *master = spi->master;
+	struct device *dev = master->dev.parent;
 	struct device *d;
 	int status;
 
 	/* Chipselects are numbered 0..max; validate. */
-	if (spi->chip_select >= spi->master->num_chipselect) {
+	if (spi->chip_select >= master->num_chipselect) {
 		dev_err(dev, "cs%d >= max %d\n",
 			spi->chip_select,
-			spi->master->num_chipselect);
+			master->num_chipselect);
 		return -EINVAL;
 	}
 
@@ -376,6 +379,9 @@ int spi_add_device(struct spi_device *spi)
 		goto done;
 	}
 
+	if (master->cs_gpios)
+		spi->cs_gpio = master->cs_gpios[spi->chip_select];
+
 	/* Drivers may modify this initial i/o setup, but will
 	 * normally rely on the device being setup.  Devices
 	 * using SPI_CS_HIGH can't coexist well otherwise...
@@ -946,6 +952,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
 }
 EXPORT_SYMBOL_GPL(spi_alloc_master);
 
+#ifdef CONFIG_OF
+static int of_spi_register_master(struct spi_master *master)
+{
+	int nb, i;
+	int *cs;
+	struct device_node *np = master->dev.of_node;
+
+	if (!np)
+		return 0;
+
+	nb = of_gpio_named_count(np, "cs-gpios");
+
+	if (nb < 1)
+		return 0;
+
+	cs = devm_kzalloc(&master->dev,
+			  sizeof(int) * (master->num_chipselect + nb),
+			  GFP_KERNEL);
+	master->cs_gpios = cs;
+
+	if (!master->cs_gpios)
+		return -ENOMEM;
+
+	memset(cs, -EINVAL, master->num_chipselect);
+	master->num_chipselect += nb;
+	cs += master->num_chipselect;
+
+	for (i = 0; i < nb; i++)
+		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
+
+	return 0;
+}
+#else
+static int of_spi_register_master(struct spi_master *master)
+{
+	return 0;
+}
+#endif
+
 /**
  * spi_register_master - register SPI master controller
  * @master: initialized master, originally from spi_alloc_master()
@@ -977,6 +1022,10 @@ int spi_register_master(struct spi_master *master)
 	if (!dev)
 		return -ENODEV;
 
+	status = of_spi_register_master(master);
+	if (status)
+		return status;
+
 	/* even if it's just one always-selected device, there must
 	 * be at least one chipselect
 	 */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index fa702ae..f629189 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -90,6 +90,7 @@ struct spi_device {
 	void			*controller_state;
 	void			*controller_data;
 	char			modalias[SPI_NAME_SIZE];
+	int			cs_gpio;	/* chip select gpio */
 
 	/*
 	 * likely need more hooks for more protocol options affecting how
@@ -362,6 +363,8 @@ struct spi_master {
 	int (*transfer_one_message)(struct spi_master *master,
 				    struct spi_message *mesg);
 	int (*unprepare_transfer_hardware)(struct spi_master *master);
+	/* gpio chip select */
+	int			*cs_gpios;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:18 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:18 +0200
Subject: [PATCH 04/23] spi/atmel_spi: add physical base address
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-5-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

Needed for future use with dmaengine enabled driver.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/spi-atmel.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 7c41b07..a83f470 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -188,6 +188,7 @@
 struct atmel_spi {
 	spinlock_t		lock;
 
+	resource_size_t		phybase;
 	void __iomem		*regs;
 	int			irq;
 	struct clk		*clk;
@@ -962,6 +963,7 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	as->regs = ioremap(regs->start, resource_size(regs));
 	if (!as->regs)
 		goto out_free_buffer;
+	as->phybase = regs->start;
 	as->irq = irq;
 	as->clk = clk;
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:20 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:20 +0200
Subject: [PATCH 06/23] spi/atmel_spi: status information passed through
 controller data
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-7-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

The status of transfer is stored in controller data structure
so that it can be used not only by atmel_spi_msg_done() function.
This will be useful for upcoming dmaengine enabled driver.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/spi-atmel.c |   13 ++++++++-----
 1 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 39285ef..49a7f4f 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -201,6 +201,7 @@ struct atmel_spi {
 	unsigned long		current_remaining_bytes;
 	struct spi_transfer	*next_transfer;
 	unsigned long		next_remaining_bytes;
+	int			done_status;
 
 	/* scratch buffer */
 	void			*buffer;
@@ -545,15 +546,15 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 
 static void
 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
-		struct spi_message *msg, int status, int stay)
+		struct spi_message *msg, int stay)
 {
-	if (!stay || status < 0)
+	if (!stay || as->done_status < 0)
 		cs_deactivate(as, msg->spi);
 	else
 		as->stay = msg->spi;
 
 	list_del(&msg->queue);
-	msg->status = status;
+	msg->status = as->done_status;
 
 	dev_dbg(master->dev.parent,
 		"xfer complete: %u bytes transferred\n",
@@ -565,6 +566,7 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 
 	as->current_transfer = NULL;
 	as->next_transfer = NULL;
+	as->done_status = 0;
 
 	/* continue if needed */
 	if (list_empty(&as->queue) || as->stopping)
@@ -642,7 +644,8 @@ atmel_spi_interrupt(int irq, void *dev_id)
 		/* Clear any overrun happening while cleaning up */
 		spi_readl(as, SR);
 
-		atmel_spi_msg_done(master, as, msg, -EIO, 0);
+		as->done_status = -EIO;
+		atmel_spi_msg_done(master, as, msg, 0);
 	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 		ret = IRQ_HANDLED;
 
@@ -660,7 +663,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
 
 			if (atmel_spi_xfer_is_last(msg, xfer)) {
 				/* report completed message */
-				atmel_spi_msg_done(master, as, msg, 0,
+				atmel_spi_msg_done(master, as, msg,
 						xfer->cs_change);
 			} else {
 				if (xfer->cs_change) {
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:19 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:19 +0200
Subject: [PATCH 05/23] spi/atmel_spi: call unmapping on transfers buffers
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-6-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/spi-atmel.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index a83f470..39285ef 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1011,6 +1011,7 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
 	struct spi_master	*master = platform_get_drvdata(pdev);
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 	struct spi_message	*msg;
+	struct spi_transfer	*xfer;
 
 	/* reset the hardware and block queue progress */
 	spin_lock_irq(&as->lock);
@@ -1022,9 +1023,10 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
 
 	/* Terminate remaining queued transfers */
 	list_for_each_entry(msg, &as->queue, queue) {
-		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
-		 * but we shouldn't depend on that...
-		 */
+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+			if (!msg->is_dma_mapped)
+				atmel_spi_dma_unmap_xfer(master, xfer);
+		}
 		msg->status = -ESHUTDOWN;
 		msg->complete(msg->context);
 	}
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:22 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:22 +0200
Subject: [PATCH 08/23] spi/atmel: add DT support
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-9-git-send-email-richard.genoud@gmail.com>

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

The atmel_spi use only gpio for chip select.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
 .../devicetree/bindings/spi/spi_atmel.txt          |    6 +++++
 drivers/spi/spi-atmel.c                            |   21 ++++++++++++++++---
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644
index 0000000..7ec3d8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -0,0 +1,6 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 70f7bfa..ad47b6d 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/io.h>
 #include <mach/board.h>
@@ -711,7 +712,7 @@ static int atmel_spi_setup(struct spi_device *spi)
 	u32			scbr, csr;
 	unsigned int		bits = spi->bits_per_word;
 	unsigned long		bus_hz;
-	unsigned int		npcs_pin;
+	int			npcs_pin;
 	int			ret;
 
 	as = spi_master_get_devdata(spi->master);
@@ -783,7 +784,9 @@ static int atmel_spi_setup(struct spi_device *spi)
 	csr |= SPI_BF(DLYBCT, 0);
 
 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
-	npcs_pin = (unsigned int)spi->controller_data;
+	if (!gpio_is_valid(spi->cs_gpio))
+		spi->cs_gpio = (int)spi->controller_data;
+	npcs_pin = spi->cs_gpio;
 	asd = spi->controller_state;
 	if (!asd) {
 		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
@@ -900,7 +903,7 @@ static void atmel_spi_cleanup(struct spi_device *spi)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
 	struct atmel_spi_device	*asd = spi->controller_state;
-	unsigned		gpio = (unsigned) spi->controller_data;
+	unsigned		gpio = spi->cs_gpio;
 
 	if (!asd)
 		return;
@@ -950,7 +953,8 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	master->bus_num = pdev->id;
-	master->num_chipselect = 4;
+	master->dev.of_node = pdev->dev.of_node;
+	master->num_chipselect = master->dev.of_node ? 0 : 4;
 	master->setup = atmel_spi_setup;
 	master->transfer = atmel_spi_transfer;
 	master->cleanup = atmel_spi_cleanup;
@@ -1079,11 +1083,20 @@ static int atmel_spi_resume(struct platform_device *pdev)
 #define	atmel_spi_resume	NULL
 #endif
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_spi_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-spi" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
+#endif
 
 static struct platform_driver atmel_spi_driver = {
 	.driver		= {
 		.name	= "atmel_spi",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_spi_dt_ids),
 	},
 	.suspend	= atmel_spi_suspend,
 	.resume		= atmel_spi_resume,
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:21 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:21 +0200
Subject: [PATCH 07/23] spi/atmel_spi: add flag to controller data for lock
 operations
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-8-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

Will allow to drop the lock during DMA operations.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/spi-atmel.c |   31 +++++++++++++++++++------------
 1 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 49a7f4f..70f7bfa 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -187,6 +187,7 @@
  */
 struct atmel_spi {
 	spinlock_t		lock;
+	unsigned long		flags;
 
 	resource_size_t		phybase;
 	void __iomem		*regs;
@@ -324,6 +325,16 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 		gpio_set_value(asd->npcs_pin, !active);
 }
 
+static void atmel_spi_lock(struct atmel_spi *as)
+{
+		spin_lock_irqsave(&as->lock, as->flags);
+}
+
+static void atmel_spi_unlock(struct atmel_spi *as)
+{
+		spin_unlock_irqrestore(&as->lock, as->flags);
+}
+
 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 					struct spi_transfer *xfer)
 {
@@ -560,9 +571,9 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 		"xfer complete: %u bytes transferred\n",
 		msg->actual_length);
 
-	spin_unlock(&as->lock);
+	atmel_spi_unlock(as);
 	msg->complete(msg->context);
-	spin_lock(&as->lock);
+	atmel_spi_lock(as);
 
 	as->current_transfer = NULL;
 	as->next_transfer = NULL;
@@ -789,13 +800,11 @@ static int atmel_spi_setup(struct spi_device *spi)
 		spi->controller_state = asd;
 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 	} else {
-		unsigned long		flags;
-
-		spin_lock_irqsave(&as->lock, flags);
+		atmel_spi_lock(as);
 		if (as->stay == spi)
 			as->stay = NULL;
 		cs_deactivate(as, spi);
-		spin_unlock_irqrestore(&as->lock, flags);
+		atmel_spi_unlock(as);
 	}
 
 	asd->csr = csr;
@@ -814,7 +823,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 {
 	struct atmel_spi	*as;
 	struct spi_transfer	*xfer;
-	unsigned long		flags;
 	struct device		*controller = spi->master->dev.parent;
 	u8			bits;
 	struct atmel_spi_device	*asd;
@@ -879,11 +887,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 	msg->status = -EINPROGRESS;
 	msg->actual_length = 0;
 
-	spin_lock_irqsave(&as->lock, flags);
+	atmel_spi_lock(as);
 	list_add_tail(&msg->queue, &as->queue);
 	if (!as->current_transfer)
 		atmel_spi_next_message(spi->master);
-	spin_unlock_irqrestore(&as->lock, flags);
+	atmel_spi_unlock(as);
 
 	return 0;
 }
@@ -893,17 +901,16 @@ static void atmel_spi_cleanup(struct spi_device *spi)
 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
 	struct atmel_spi_device	*asd = spi->controller_state;
 	unsigned		gpio = (unsigned) spi->controller_data;
-	unsigned long		flags;
 
 	if (!asd)
 		return;
 
-	spin_lock_irqsave(&as->lock, flags);
+	atmel_spi_lock(as);
 	if (as->stay == spi) {
 		as->stay = NULL;
 		cs_deactivate(as, spi);
 	}
-	spin_unlock_irqrestore(&as->lock, flags);
+	atmel_spi_unlock(as);
 
 	spi->controller_state = NULL;
 	gpio_free(gpio);
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:24 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:24 +0200
Subject: [PATCH 10/23] spi-atmel: update with dmaengine interface
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-11-git-send-email-richard.genoud@gmail.com>

commit 185ecb5f4fd43911c35956d4cc7d94a1da30417f changed dmaengine
interface.
=> we have to update spi-atmel accordingly

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/spi/spi-atmel.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 9456fca..48bf3bc 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -542,7 +542,8 @@ static int atmel_spi_next_xfer_dma(struct spi_master *master,
 					&as->dma.sgrx,
 					1,
 					DMA_FROM_DEVICE,
-					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+					NULL);
 	if (!rxdesc)
 		goto err_dma;
 
@@ -550,7 +551,8 @@ static int atmel_spi_next_xfer_dma(struct spi_master *master,
 					&as->dma.sgtx,
 					1,
 					DMA_TO_DEVICE,
-					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+					NULL);
 	if (!txdesc)
 		goto err_dma;
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:26 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:26 +0200
Subject: [PATCH 12/23] spi-atmel: Fix spi-atmel driver to adapt to
 slave_config changes
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-13-git-send-email-richard.genoud@gmail.com>

This is the following of the patch e2b35f3dbfc080f15b72834d08f04f0269dbe9be

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/spi/spi-atmel.c |   45 ++++++++++++++++++++++++++++++++++++---------
 1 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index d90e8fb..28a00ab 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -399,17 +399,24 @@ static int __devinit atmel_spi_configure_dma(struct spi_master *master)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 	struct device		*controller = master->dev.parent;
+	struct dma_slave_config slave_config;
 	struct at_dma_slave	*sdata;
+	int err;
 
 	sdata = controller->platform_data;
 
+	memset(&slave_config, 0, sizeof(slave_config));
+	slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
+	slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
+	slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	slave_config.src_maxburst = 1;
+	slave_config.dst_maxburst = 1;
+	slave_config.device_fc = false;
+
 	if (sdata && sdata->dma_dev) {
 		dma_cap_mask_t mask;
 
-		/* setup DMA addresses */
-		sdata->rx_reg = (dma_addr_t)as->phybase + SPI_RDR;
-		sdata->tx_reg = (dma_addr_t)as->phybase + SPI_TDR;
-
 		/* Try to grab two DMA channels */
 		dma_cap_zero(mask);
 		dma_cap_set(DMA_SLAVE, mask);
@@ -417,14 +424,28 @@ static int __devinit atmel_spi_configure_dma(struct spi_master *master)
 		if (as->dma.chan_tx)
 			as->dma.chan_rx = dma_request_channel(mask, filter, sdata);
 	}
+
 	if (!as->dma.chan_rx || !as->dma.chan_tx) {
-		if (as->dma.chan_rx)
-			dma_release_channel(as->dma.chan_rx);
-		if (as->dma.chan_tx)
-			dma_release_channel(as->dma.chan_tx);
 		dev_err(&as->pdev->dev, "DMA channel not available, "
 					"unable to use SPI\n");
-		return -EBUSY;
+		err = -EBUSY;
+		goto error;
+	}
+
+	slave_config.direction = DMA_TO_DEVICE;
+	if (dmaengine_slave_config(as->dma.chan_tx, &slave_config)) {
+		dev_err(&as->pdev->dev,
+			"failed to configure tx dma channel\n");
+		err = -EINVAL;
+		goto error;
+	}
+
+	slave_config.direction = DMA_FROM_DEVICE;
+	if (dmaengine_slave_config(as->dma.chan_rx, &slave_config)) {
+		dev_err(&as->pdev->dev,
+			"failed to configure rx dma channel\n");
+		err = -EINVAL;
+		goto error;
 	}
 
 	dev_info(&as->pdev->dev, "Using %s (tx) and "
@@ -433,6 +454,12 @@ static int __devinit atmel_spi_configure_dma(struct spi_master *master)
 				dma_chan_name(as->dma.chan_rx));
 
 	return 0;
+error:
+	if (as->dma.chan_rx)
+		dma_release_channel(as->dma.chan_rx);
+	if (as->dma.chan_tx)
+		dma_release_channel(as->dma.chan_tx);
+	return err;
 }
 
 static void atmel_spi_stop_dma(struct atmel_spi *as)
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:25 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:25 +0200
Subject: [PATCH 11/23] spi-atmel: fix __init/__devinit sections mismatch
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-12-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/spi/spi-atmel.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 48bf3bc..d90e8fb 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -383,7 +383,7 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 }
 
 #if defined(CONFIG_SPI_ATMEL_DMA)
-static bool __init filter(struct dma_chan *chan, void *slave)
+static bool filter(struct dma_chan *chan, void *slave)
 {
 	struct	at_dma_slave		*sl = slave;
 
@@ -395,7 +395,7 @@ static bool __init filter(struct dma_chan *chan, void *slave)
 	}
 }
 
-static int __init atmel_spi_configure_dma(struct spi_master *master)
+static int __devinit atmel_spi_configure_dma(struct spi_master *master)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 	struct device		*controller = master->dev.parent;
@@ -628,7 +628,7 @@ static void atmel_spi_disable_dma_irq(struct atmel_spi *as)
 	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 }
 
-static int __init atmel_spi_configure_dma(struct spi_master *master)
+static int __devinit atmel_spi_configure_dma(struct spi_master *master)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:27 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:27 +0200
Subject: [PATCH 13/23] AT91 DMA OF support
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-14-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/mach-at91/include/mach/at_hdmac.h |    1 +
 drivers/of/Kconfig                         |    4 +
 drivers/of/Makefile                        |    1 +
 drivers/of/of_atmel.c                      |  112 ++++++++++++++++++++++++++++
 include/linux/of_atmel.h                   |   29 +++++++
 5 files changed, 147 insertions(+), 0 deletions(-)
 create mode 100644 drivers/of/of_atmel.c
 create mode 100644 include/linux/of_atmel.h

diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
index cab0997..35667bd 100644
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -52,6 +52,7 @@ struct at_dma_slave {
 #define		ATC_LOCK_IF_L_CHUNK	(0x0 << 22)
 #define		ATC_LOCK_IF_L_BUFFER	(0x1 << 22)
 #define	ATC_AHB_PROT_MASK	(0x7 << 24)	/* AHB Protection */
+#define	ATC_AHB_PROT(h)		(((h) <<  24) && ATC_AHB_PROT_MASK)
 #define	ATC_FIFOCFG_MASK	(0x3 << 28)	/* FIFO Request Configuration */
 #define		ATC_FIFOCFG_LARGESTBURST	(0x0 << 28)
 #define		ATC_FIFOCFG_HALFFIFO		(0x1 << 28)
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index dfba3e6..4667960 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -83,4 +83,8 @@ config OF_MTD
 	depends on MTD
 	def_bool y
 
+config OF_ATMEL
+	depends on AT_HDMAC
+	def_bool y
+
 endmenu # OF
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index e027f44..897de3b 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
 obj-$(CONFIG_OF_PCI)	+= of_pci.o
 obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
 obj-$(CONFIG_OF_MTD)	+= of_mtd.o
+obj-$(CONFIG_OF_ATMEL)	+= of_atmel.o
diff --git a/drivers/of/of_atmel.c b/drivers/of/of_atmel.c
new file mode 100644
index 0000000..bcd3c54a
--- /dev/null
+++ b/drivers/of/of_atmel.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2012 Richard Genoud, Paratronic S.A.
+ *                    <richard.genoud at gmail.com>
+ *
+ * Atmel specifics OF helpers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/printk.h>
+#include <linux/byteorder/generic.h>
+#include <mach/at_hdmac.h>
+#include <linux/of.h>
+
+static int of_dev_node_match(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+/**
+ * of_create_at_dma_slave - Alloc and initialize the struct at_dma_slave
+ * @np: pointer to node to create the struct for
+ * @bus: pointer to the bus type of the DMA device.
+ *
+ * Returns pointer to created DMA slave structure, or NULL in case of error.
+ */
+struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
+					    struct bus_type *bus)
+{
+	struct at_dma_slave *atslave;
+	struct device_node *n;
+	struct property *prop;
+	const __be32 *dma_list;
+	phandle phandle;
+	int size;
+	int err = -1;
+	u32 val;
+
+	atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
+	if (unlikely(!atslave)) {
+		pr_err("cannot allocate memory\n");
+		goto error;
+	}
+
+	atslave->cfg |= of_property_read_bool(np, "atc_src_rep") ? ATC_SRC_REP : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_dst_rep") ? ATC_DST_REP : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_src_h2sel_hw") ? ATC_SRC_H2SEL_HW : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_dst_h2sel_hw") ? ATC_DST_H2SEL_HW : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_sod") ? ATC_SOD : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_lock_if") ? ATC_LOCK_IF : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_lock_b") ? ATC_LOCK_B : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l") ? ATC_LOCK_IF_L : 0;
+	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l_buffer") ? ATC_LOCK_IF_L_BUFFER : 0;
+	if (of_property_read_bool(np, "atc_fifocfg_halffifo"))
+		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_HALFFIFO;
+	if (of_property_read_bool(np, "atc_fifocfg_enoughspace"))
+		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_ENOUGHSPACE;
+	if (of_property_read_bool(np, "atc_fifocfg_largestburst"))
+		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_LARGESTBURST;
+	if (!of_property_read_u32(np, "atc_ahb_prot", &val))
+		atslave->cfg |= ATC_AHB_PROT(val);
+	if (!of_property_read_u32(np, "atc_src_per", &val))
+		atslave->cfg |= ATC_SRC_PER(val);
+	if (!of_property_read_u32(np, "atc_dst_per", &val))
+		atslave->cfg |= ATC_DST_PER(val);
+
+	/* we need to associate the wanted dma struct device to
+	 * atslave->dma_dev. This is needed when searching for
+	 * a free dma channel
+	 */
+	prop = of_find_property(np, "dma", &size);
+	if (!prop) {
+		pr_err("can't find the dma child node\n");
+		goto error;
+	}
+	dma_list = prop->value;
+	size /= sizeof(*dma_list);
+	if (size != 1) {
+		pr_err("only one dma handle is supported\n");
+		goto error;
+	}
+
+	phandle = be32_to_cpup(dma_list);
+	n = of_find_node_by_phandle(phandle);
+	if (!n) {
+		pr_err("unable to find dma device: invalid phandle %s\n",
+		       prop->name);
+		goto error;
+	}
+
+	atslave->dma_dev = bus_find_device(bus, NULL, n, of_dev_node_match);
+	if (!atslave->dma_dev) {
+		pr_err("can't find struct device for DMA %s\n", prop->name);
+		goto error;
+	}
+
+	pr_debug("DMA cfg register=0x%x DMA device path=%s\n",
+		 atslave->cfg, prop->name);
+	err = 0;
+error:
+	if (err)
+		kfree(atslave);
+	return atslave;
+}
+EXPORT_SYMBOL_GPL(of_create_at_dma_slave);
+
diff --git a/include/linux/of_atmel.h b/include/linux/of_atmel.h
new file mode 100644
index 0000000..256f336
--- /dev/null
+++ b/include/linux/of_atmel.h
@@ -0,0 +1,29 @@
+#ifndef _LINUX_OF_ATMEL_H
+#define _LINUX_OF_ATMEL_H
+/*
+ * Copyright (C) 2012 Richard Genoud, Paratronic S.A.
+ *                    <richard.genoud at gmail.com>
+ *
+ * Atmel specifics OF helpers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/of.h>
+#include <linux/device.h>
+#include <mach/at_hdmac.h>
+
+#ifdef CONFIG_OF_ATMEL
+extern struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
+						   struct bus_type *bus);
+#else
+static struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
+						   struct bus_type *bus)
+{
+	return NULL;
+}
+#endif /* CONFIG_OF_ATMEL */
+
+#endif	/* _LINUX_OF_ATMEL_H */
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:30 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:30 +0200
Subject: [PATCH 16/23] [BUG] SPI: array out of bound => no CS
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-17-git-send-email-richard.genoud@gmail.com>

---
 drivers/spi/spi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 3fb5b6d..74e6577 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -976,8 +976,8 @@ static int of_spi_register_master(struct spi_master *master)
 		return -ENOMEM;
 
 	memset(cs, -EINVAL, master->num_chipselect);
-	master->num_chipselect += nb;
 	cs += master->num_chipselect;
+	master->num_chipselect += nb;
 
 	for (i = 0; i < nb; i++)
 		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:29 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:29 +0200
Subject: [PATCH 15/23] spi-atmel: add DMA OF support
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-16-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/of/of_atmel.c   |    1 -
 drivers/spi/spi-atmel.c |   22 ++++++++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/drivers/of/of_atmel.c b/drivers/of/of_atmel.c
index bcd3c54a..a59b9ced 100644
--- a/drivers/of/of_atmel.c
+++ b/drivers/of/of_atmel.c
@@ -55,7 +55,6 @@ struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
 	atslave->cfg |= of_property_read_bool(np, "atc_sod") ? ATC_SOD : 0;
 	atslave->cfg |= of_property_read_bool(np, "atc_lock_if") ? ATC_LOCK_IF : 0;
 	atslave->cfg |= of_property_read_bool(np, "atc_lock_b") ? ATC_LOCK_B : 0;
-	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l") ? ATC_LOCK_IF_L : 0;
 	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l_buffer") ? ATC_LOCK_IF_L_BUFFER : 0;
 	if (of_property_read_bool(np, "atc_fifocfg_halffifo"))
 		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_HALFFIFO;
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 28a00ab..d629422 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -21,6 +21,7 @@
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/of_atmel.h>
 
 #include <asm/io.h>
 #include <mach/board.h>
@@ -1411,6 +1412,8 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	int			ret;
 	struct spi_master	*master;
 	struct atmel_spi	*as;
+	struct bus_type		*bus = pdev->dev.bus;
+	struct device_node	*of = pdev->dev.of_node;
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs)
@@ -1430,6 +1433,17 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	if (!master)
 		goto out_free;
 
+
+	/* populate platform_data from device tree */
+	if (of) {
+		pdev->dev.platform_data = of_create_at_dma_slave(of, bus);
+		if (!pdev->dev.platform_data) {
+			dev_err(&pdev->dev, "could not get DMA\n");
+			ret = -EINVAL;
+			goto out_free;
+		}
+	}
+
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
@@ -1504,6 +1518,10 @@ out_free_buffer:
 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 			as->buffer_dma);
 out_free:
+	if (of) {
+		kfree((struct at_dma_slave*)(pdev->dev.platform_data));
+		pdev->dev.platform_data = NULL;
+	}
 	clk_put(clk);
 	spi_master_put(master);
 	return ret;
@@ -1546,6 +1564,10 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
 	iounmap(as->regs);
 
 	spi_unregister_master(master);
+	if (pdev->dev.of_node) {
+		kfree((struct at_dma_slave*)(pdev->dev.platform_data));
+		pdev->dev.platform_data = NULL;
+	}
 
 	return 0;
 }
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:32 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:32 +0200
Subject: [PATCH 18/23] sam9x5: declare SPI clocks
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-19-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/mach-at91/at91sam9x5.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index bbd2f8e..e213e2d 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -16,6 +16,7 @@
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 #include <mach/board.h>
+#include <mach/gpio.h>
 
 #include "soc.h"
 #include "generic.h"
@@ -231,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:28 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:28 +0200
Subject: [PATCH 14/23] add at91sam9x5 Kconfig ARCH/SOC link
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-15-git-send-email-richard.genoud@gmail.com>

---
 arch/arm/mach-at91/Kconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8050b1..c6eb877 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -141,6 +141,10 @@ config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
 	select SOC_AT91SAM9G45
 
+config ARCH_AT91SAM9X5
+	bool "AT91SAM9x5"
+	select SOC_AT91SAM9X5
+
 config ARCH_AT91X40
 	bool "AT91x40"
 	depends on !MMU
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:23 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:23 +0200
Subject: [PATCH 09/23] spi/atmel_spi: add dmaengine support
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-10-git-send-email-richard.genoud@gmail.com>

From: Nicolas Ferre <nicolas.ferre at atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 drivers/spi/Kconfig     |    9 +
 drivers/spi/spi-atmel.c |  483 ++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 482 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b55..169592a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,6 +74,15 @@ config SPI_ATMEL
 	  This selects a driver for the Atmel SPI Controller, present on
 	  many AT32 (AVR32) and AT91 (ARM) chips.
 
+config SPI_ATMEL_DMA
+	bool "Atmel SPI DMA support"
+	depends on SPI_ATMEL && (ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5) && DMA_ENGINE && EXPERIMENTAL
+	default y
+	help
+	  Say Y here if you want the Atmel SPI driver to use the DMA engine. Data transfers
+	  will be handled by the DMA controller: it will increase throughput and reduce
+	  CPU utilization.
+
 config SPI_BFIN5XX
 	tristate "SPI controller driver for ADI Blackfin5xx"
 	depends on BLACKFIN
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index ad47b6d..9456fca 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
@@ -25,6 +26,7 @@
 #include <mach/board.h>
 #include <asm/gpio.h>
 #include <mach/cpu.h>
+#include <mach/at_hdmac.h>
 
 /* SPI register offsets */
 #define SPI_CR					0x0000
@@ -181,6 +183,22 @@
 	__raw_writel((value), (port)->regs + SPI_##reg)
 
 
+#if defined(CONFIG_SPI_ATMEL_DMA)
+/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
+ * cache operations; better heuristics consider wordsize and bitrate.
+ */
+#define DMA_MIN_BYTES	16
+
+struct atmel_spi_dma {
+	struct dma_chan			*chan_rx;
+	struct dma_chan			*chan_tx;
+	struct scatterlist		sgrx;
+	struct scatterlist		sgtx;
+	struct dma_async_tx_descriptor	*data_desc_rx;
+	struct dma_async_tx_descriptor	*data_desc_tx;
+};
+#endif
+
 /*
  * The core SPI transfer engine just talks to a register bank to set up
  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
@@ -199,6 +217,7 @@ struct atmel_spi {
 
 	u8			stopping;
 	struct list_head	queue;
+	struct tasklet_struct	tasklet;
 	struct spi_transfer	*current_transfer;
 	unsigned long		current_remaining_bytes;
 	struct spi_transfer	*next_transfer;
@@ -208,6 +227,11 @@ struct atmel_spi {
 	/* scratch buffer */
 	void			*buffer;
 	dma_addr_t		buffer_dma;
+
+#if defined(CONFIG_SPI_ATMEL_DMA)
+	/* dmaengine data */
+	struct atmel_spi_dma	dma;
+#endif
 };
 
 /* Controller-specific per-slave state */
@@ -336,6 +360,17 @@ static void atmel_spi_unlock(struct atmel_spi *as)
 		spin_unlock_irqrestore(&as->lock, as->flags);
 }
 
+static inline bool atmel_spi_use_dma(struct spi_transfer *xfer)
+{
+#if defined(CONFIG_SPI_ATMEL_DMA)
+	if (xfer->len < DMA_MIN_BYTES)
+		return false;
+	return true;
+#else
+	return false;
+#endif
+}
+
 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 					struct spi_transfer *xfer)
 {
@@ -347,6 +382,258 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 	return xfer->delay_usecs == 0 && !xfer->cs_change;
 }
 
+#if defined(CONFIG_SPI_ATMEL_DMA)
+static bool __init filter(struct dma_chan *chan, void *slave)
+{
+	struct	at_dma_slave		*sl = slave;
+
+	if (sl->dma_dev == chan->device->dev) {
+		chan->private = sl;
+		return true;
+	} else {
+		return false;
+	}
+}
+
+static int __init atmel_spi_configure_dma(struct spi_master *master)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct device		*controller = master->dev.parent;
+	struct at_dma_slave	*sdata;
+
+	sdata = controller->platform_data;
+
+	if (sdata && sdata->dma_dev) {
+		dma_cap_mask_t mask;
+
+		/* setup DMA addresses */
+		sdata->rx_reg = (dma_addr_t)as->phybase + SPI_RDR;
+		sdata->tx_reg = (dma_addr_t)as->phybase + SPI_TDR;
+
+		/* Try to grab two DMA channels */
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_SLAVE, mask);
+		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
+		if (as->dma.chan_tx)
+			as->dma.chan_rx = dma_request_channel(mask, filter, sdata);
+	}
+	if (!as->dma.chan_rx || !as->dma.chan_tx) {
+		if (as->dma.chan_rx)
+			dma_release_channel(as->dma.chan_rx);
+		if (as->dma.chan_tx)
+			dma_release_channel(as->dma.chan_tx);
+		dev_err(&as->pdev->dev, "DMA channel not available, "
+					"unable to use SPI\n");
+		return -EBUSY;
+	}
+
+	dev_info(&as->pdev->dev, "Using %s (tx) and "
+				" %s (rx) for DMA transfers\n",
+				dma_chan_name(as->dma.chan_tx),
+				dma_chan_name(as->dma.chan_rx));
+
+	return 0;
+}
+
+static void atmel_spi_stop_dma(struct atmel_spi *as)
+{
+	if (as->dma.chan_rx)
+		as->dma.chan_rx->device->device_control(as->dma.chan_rx,
+							DMA_TERMINATE_ALL, 0);
+	if (as->dma.chan_tx)
+		as->dma.chan_tx->device->device_control(as->dma.chan_tx,
+							DMA_TERMINATE_ALL, 0);
+}
+
+static void atmel_spi_release_dma(struct atmel_spi *as)
+{
+	if (as->dma.chan_rx)
+		dma_release_channel(as->dma.chan_rx);
+	if (as->dma.chan_tx)
+		dma_release_channel(as->dma.chan_tx);
+}
+
+/* This function is called by the DMA driver from tasklet context */
+static void dma_callback(void *data)
+{
+	struct spi_master	*master = data;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+
+	/* trigger SPI tasklet */
+	tasklet_schedule(&as->tasklet);
+}
+
+/*
+ * Next transfer using PIO.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_next_xfer_pio(struct spi_master *master,
+				struct spi_transfer *xfer)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+
+	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
+
+	as->current_remaining_bytes = xfer->len;
+
+	/* Make sure data is not remaining in RDR */
+	spi_readl(as, RDR);
+	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
+		spi_readl(as, RDR);
+		cpu_relax();
+	}
+
+	if (xfer->tx_buf)
+		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
+	else
+		spi_writel(as, TDR, 0);
+
+	dev_dbg(master->dev.parent,
+		"  start pio xfer %p: len %u tx %p rx %p\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
+
+	/* Enable relevant interrupts */
+	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
+}
+
+/*
+ * Submit next transfer for DMA.
+ * lock is held, spi tasklet is blocked
+ */
+static int atmel_spi_next_xfer_dma(struct spi_master *master,
+				struct spi_transfer *xfer)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct dma_chan		*rxchan = as->dma.chan_rx;
+	struct dma_chan		*txchan = as->dma.chan_tx;
+	struct dma_async_tx_descriptor *rxdesc;
+	struct dma_async_tx_descriptor *txdesc;
+	dma_cookie_t		cookie;
+
+	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma\n");
+
+	/* Check that the channels are available */
+	if (!rxchan || !txchan)
+		return -ENODEV;
+
+	/* release lock for DMA operations */
+	atmel_spi_unlock(as);
+
+	/* prepare the RX dma transfer */
+	sg_init_table(&as->dma.sgrx, 1);
+	sg_dma_len(&as->dma.sgrx) = xfer->len;
+	if (xfer->rx_buf)
+		as->dma.sgrx.dma_address = xfer->rx_dma;
+	else
+		as->dma.sgrx.dma_address = as->buffer_dma;
+
+	/* prepare the TX dma transfer */
+	sg_init_table(&as->dma.sgtx, 1);
+	sg_dma_len(&as->dma.sgtx) = xfer->len;
+	if (xfer->tx_buf) {
+		as->dma.sgtx.dma_address = xfer->tx_dma;
+	} else {
+		as->dma.sgtx.dma_address = as->buffer_dma;
+		memset(as->buffer, 0, xfer->len);
+	}
+
+	/* Send both scatterlists */
+	rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
+					&as->dma.sgrx,
+					1,
+					DMA_FROM_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!rxdesc)
+		goto err_dma;
+
+	txdesc = txchan->device->device_prep_slave_sg(txchan,
+					&as->dma.sgtx,
+					1,
+					DMA_TO_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!txdesc)
+		goto err_dma;
+
+	dev_dbg(master->dev.parent,
+		"  start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
+		xfer->rx_buf, xfer->rx_dma);
+
+	/* Enable relevant interrupts */
+	spi_writel(as, IER, SPI_BIT(OVRES));
+
+	/* Put the callback on the RX transfer only, that should finish last */
+	rxdesc->callback = dma_callback;
+	rxdesc->callback_param = master;
+
+	/* Submit and fire RX and TX with TX last so we're ready to read! */
+	cookie = rxdesc->tx_submit(rxdesc);
+	if (dma_submit_error(cookie))
+		goto err_dma;
+	cookie = txdesc->tx_submit(txdesc);
+	if (dma_submit_error(cookie))
+		goto err_dma;
+	rxchan->device->device_issue_pending(rxchan);
+	txchan->device->device_issue_pending(txchan);
+
+	/* take back lock */
+	atmel_spi_lock(as);
+	return 0;
+
+err_dma:
+	spi_writel(as, IDR, SPI_BIT(OVRES));
+	atmel_spi_stop_dma(as);
+	atmel_spi_lock(as);
+	return -ENOMEM;
+}
+
+/*
+ * Choose way to submit next transfer and start it.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_next_xfer(struct spi_master *master,
+				struct spi_message *msg)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct spi_transfer	*xfer;
+
+	dev_vdbg(&msg->spi->dev, "atmel_spi_next_xfer\n");
+
+	if (!as->current_transfer)
+		xfer = list_entry(msg->transfers.next,
+				struct spi_transfer, transfer_list);
+	else
+		xfer = list_entry(as->current_transfer->transfer_list.next,
+				struct spi_transfer, transfer_list);
+
+	as->current_transfer = xfer;
+
+	if (atmel_spi_use_dma(xfer)) {
+		if (!atmel_spi_next_xfer_dma(master, xfer))
+			return;
+		else
+			dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
+	}
+
+	/* use PIO if xfer is short or error appened using DMA */
+	atmel_spi_next_xfer_pio(master, xfer);
+}
+
+static void atmel_spi_disable_dma_irq(struct atmel_spi *as) {}
+#else
+static void atmel_spi_disable_dma_irq(struct atmel_spi *as)
+{
+	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+}
+
+static int __init atmel_spi_configure_dma(struct spi_master *master)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+
+	atmel_spi_disable_dma_irq(as);
+	return 0;
+}
+
 static void atmel_spi_next_xfer_data(struct spi_master *master,
 				struct spi_transfer *xfer,
 				dma_addr_t *tx_dma,
@@ -479,6 +766,10 @@ static void atmel_spi_next_xfer(struct spi_master *master,
 	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 }
 
+static void atmel_spi_stop_dma(struct atmel_spi *as) {}
+static void atmel_spi_release_dma(struct atmel_spi *as) {}
+#endif
+
 static void atmel_spi_next_message(struct spi_master *master)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
@@ -582,11 +873,175 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 
 	/* continue if needed */
 	if (list_empty(&as->queue) || as->stopping)
-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+		atmel_spi_disable_dma_irq(as);
 	else
 		atmel_spi_next_message(master);
 }
 
+#if defined(CONFIG_SPI_ATMEL_DMA)
+/* Called from IRQ
+ * lock is held
+ *
+ * Must update "current_remaining_bytes" to keep track of data
+ * to transfer.
+ */
+static void
+atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
+{
+	u8		*txp;
+	u8		*rxp;
+	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
+
+	if (xfer->rx_buf) {
+		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
+		*rxp = spi_readl(as, RDR);
+	} else {
+		spi_readl(as, RDR);
+	}
+
+	as->current_remaining_bytes--;
+
+	if (as->current_remaining_bytes) {
+		if (xfer->tx_buf) {
+			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
+			spi_writel(as, TDR, *txp);
+		} else {
+			spi_writel(as, TDR, 0);
+		}
+	}
+}
+
+/* Tasklet
+ * Called from DMA callback + pio transfer and overrun IRQ.
+ */
+static void atmel_spi_tasklet_func(unsigned long data)
+{
+	struct spi_master	*master = (struct spi_master *)data;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct spi_message	*msg;
+	struct spi_transfer	*xfer;
+
+	dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
+
+	atmel_spi_lock(as);
+
+	xfer = as->current_transfer;
+
+	if (xfer == NULL)
+		/* already been there */
+		goto tasklet_out;
+
+	msg = list_entry(as->queue.next, struct spi_message, queue);
+
+	if (as->done_status < 0) {
+		/* error happened (overrun) */
+		if (atmel_spi_use_dma(xfer))
+			atmel_spi_stop_dma(as);
+	} else {
+		/* only update length if no error */
+		msg->actual_length += xfer->len;
+	}
+
+	if (atmel_spi_use_dma(xfer)) {
+		if (!msg->is_dma_mapped)
+			atmel_spi_dma_unmap_xfer(master, xfer);
+	}
+
+	if (xfer->delay_usecs)
+		udelay(xfer->delay_usecs);
+
+	if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
+		/* report completed (or erroneous) message */
+		atmel_spi_msg_done(master, as, msg, xfer->cs_change);
+	} else {
+		if (xfer->cs_change) {
+			cs_deactivate(as, msg->spi);
+			udelay(1);
+			cs_activate(as, msg->spi);
+		}
+
+		/*
+		 * Not done yet. Submit the next transfer.
+		 *
+		 * FIXME handle protocol options for xfer
+		 */
+		atmel_spi_next_xfer(master, msg);
+	}
+
+tasklet_out:
+	atmel_spi_unlock(as);
+}
+
+
+/* Interrupt with DMA engine management
+ *
+ * No need for locking in this Interrupt handler: done_status is the
+ * only information modified. What we need is the update of this field
+ * before tasklet runs. This is ensured by using barrier.
+ */
+static irqreturn_t
+atmel_spi_interrupt(int irq, void *dev_id)
+{
+	struct spi_master	*master = dev_id;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	u32			status, pending, imr;
+	struct spi_transfer	*xfer;
+	int			ret = IRQ_NONE;
+
+	imr = spi_readl(as, IMR);
+	status = spi_readl(as, SR);
+	pending = status & imr;
+
+	if (pending & SPI_BIT(OVRES)) {
+		ret = IRQ_HANDLED;
+		spi_writel(as, IDR, SPI_BIT(OVRES));
+		dev_warn(master->dev.parent, "overrun\n");
+
+		/*
+		 * When we get an overrun, we disregard the current
+		 * transfer. Data will not be copied back from any
+		 * bounce buffer and msg->actual_len will not be
+		 * updated with the last xfer.
+		 *
+		 * We will also not process any remaning transfers in
+		 * the message.
+		 *
+		 * All actions are done in tasklet with done_status indication
+		 */
+		as->done_status = -EIO;
+		smp_wmb();
+
+		/* Clear any overrun happening while cleaning up */
+		spi_readl(as, SR);
+
+		tasklet_schedule(&as->tasklet);
+
+	} else if (pending & SPI_BIT(RDRF)) {
+		atmel_spi_lock(as);
+
+		if (as->current_remaining_bytes) {
+			ret = IRQ_HANDLED;
+			xfer = as->current_transfer;
+			atmel_spi_pump_pio_data(as, xfer);
+			if (!as->current_remaining_bytes) {
+				/* no more data to xfer, kick tasklet */
+				spi_writel(as, IDR, pending);
+				tasklet_schedule(&as->tasklet);
+			}
+		}
+
+		atmel_spi_unlock(as);
+	} else {
+		WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
+		ret = IRQ_HANDLED;
+		spi_writel(as, IDR, pending);
+	}
+
+	return ret;
+}
+#else
+static void atmel_spi_tasklet_func(unsigned long data) {}
+
 static irqreturn_t
 atmel_spi_interrupt(int irq, void *dev_id)
 {
@@ -704,6 +1159,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
 
 	return ret;
 }
+#endif
 
 static int atmel_spi_setup(struct spi_device *spi)
 {
@@ -865,13 +1321,9 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 
 		/*
 		 * DMA map early, for performance (empties dcache ASAP) and
-		 * better fault reporting.  This is a DMA-only driver.
-		 *
-		 * NOTE that if dma_unmap_single() ever starts to do work on
-		 * platforms supported by this driver, we would need to clean
-		 * up mappings for previously-mapped transfers.
+		 * better fault reporting.
 		 */
-		if (!msg->is_dma_mapped) {
+		if (!msg->is_dma_mapped && atmel_spi_use_dma(xfer)) {
 			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 				return -ENOMEM;
 		}
@@ -973,6 +1425,7 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 
 	spin_lock_init(&as->lock);
 	INIT_LIST_HEAD(&as->queue);
+	tasklet_init(&as->tasklet, atmel_spi_tasklet_func, (unsigned long)master);
 	as->pdev = pdev;
 	as->regs = ioremap(regs->start, resource_size(regs));
 	if (!as->regs)
@@ -991,7 +1444,11 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 	spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
-	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+
+	ret = atmel_spi_configure_dma(master);
+	if (ret)
+		goto out_reset_hw;
+
 	spi_writel(as, CR, SPI_BIT(SPIEN));
 
 	/* go! */
@@ -1000,10 +1457,12 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 
 	ret = spi_register_master(master);
 	if (ret)
-		goto out_reset_hw;
+		goto out_free_dma;
 
 	return 0;
 
+out_free_dma:
+	atmel_spi_release_dma(as);
 out_reset_hw:
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
@@ -1012,6 +1471,7 @@ out_reset_hw:
 out_unmap_regs:
 	iounmap(as->regs);
 out_free_buffer:
+	tasklet_kill(&as->tasklet);
 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 			as->buffer_dma);
 out_free:
@@ -1030,6 +1490,8 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
 	/* reset the hardware and block queue progress */
 	spin_lock_irq(&as->lock);
 	as->stopping = 1;
+	atmel_spi_stop_dma(as);
+	atmel_spi_release_dma(as);
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 	spi_readl(as, SR);
@@ -1038,13 +1500,14 @@ static int __devexit atmel_spi_remove(struct platform_device *pdev)
 	/* Terminate remaining queued transfers */
 	list_for_each_entry(msg, &as->queue, queue) {
 		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-			if (!msg->is_dma_mapped)
+			if (!msg->is_dma_mapped && atmel_spi_use_dma(xfer))
 				atmel_spi_dma_unmap_xfer(master, xfer);
 		}
 		msg->status = -ESHUTDOWN;
 		msg->complete(msg->context);
 	}
 
+	tasklet_kill(&as->tasklet);
 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 			as->buffer_dma);
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:31 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:31 +0200
Subject: [PATCH 17/23] [BUG] atmel-spi && DMA: OOPS if buffer > 4400 bytes
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-18-git-send-email-richard.genoud@gmail.com>

this is just a quick and suboptimal workaround
---
 drivers/spi/spi-atmel.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index d629422..0899da2 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -638,7 +638,8 @@ static void atmel_spi_next_xfer(struct spi_master *master,
 
 	as->current_transfer = xfer;
 
-	if (atmel_spi_use_dma(xfer)) {
+	/* quick (and *really* not optimal) workaround for DMA BUG */
+	if (atmel_spi_use_dma(xfer) && (xfer->len < BUFFER_SIZE)) {
 		if (!atmel_spi_next_xfer_dma(master, xfer))
 			return;
 		else
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:33 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:33 +0200
Subject: [PATCH 19/23] spi-atmel: add sam9x5 SPI in device tree
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-20-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e58965d6..8cb8b0d 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -344,6 +344,36 @@
 					trigger-value = <0x6>;
 				};
 			};
+
+			spi0: spi at f0000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0000000 0x100>;
+				interrupts = <13 4 3>;
+				cs-gpios = <&pioA 14 0
+					    &pioA 7 0 /* conflicts with TXD2 */
+					    &pioA 1 0 /* conflicts with RXD0 */
+					    &pioB 3 0 /* conflicts with ERXDV */
+					   >;
+				dma-mask = <0xffffffff>;
+				status = "disabled";
+			};
+
+			spi1: spi at f0004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0004000 0x100>;
+				interrupts = <14 4 3>;
+				cs-gpios = <&pioA 8 0 /* conflitcs with RXD2 */
+					    &pioA 0 0 /* conflitcs with TXD0 */
+					    &pioA 31 0 /* conflitcs with TWCK0 */
+					    &pioA 30 0 /* conflitcs with TWD0 */
+					   >;
+				dma-mask = <0xffffffff>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:34 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:34 +0200
Subject: [PATCH 20/23] spi-atmel: add dma support in sam9x5 device tree
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-21-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 8cb8b0d..ef09816 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -357,6 +357,12 @@
 					    &pioB 3 0 /* conflicts with ERXDV */
 					   >;
 				dma-mask = <0xffffffff>;
+				dma = <&dma0>;
+				atc_src_per = <2>; /* AT_DMA_ID_SPI0_RX */
+				atc_dst_per = <1>; /* AT_DMA_ID_SPI0_TX */
+				atc_fifocfg_halffifo;
+				atc_src_h2sel_hw;
+				atc_dst_h2sel_hw;
 				status = "disabled";
 			};
 
@@ -372,6 +378,12 @@
 					    &pioA 30 0 /* conflitcs with TWD0 */
 					   >;
 				dma-mask = <0xffffffff>;
+				dma = <&dma0>;
+				atc_src_per = <4>; /* AT_DMA_ID_SPI1_RX */
+				atc_dst_per = <3>; /* AT_DMA_ID_SPI1_TX */
+				atc_fifocfg_halffifo;
+				atc_src_h2sel_hw;
+				atc_dst_h2sel_hw;
 				status = "disabled";
 			};
 		};
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:35 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:35 +0200
Subject: [PATCH 21/23] spi-atmel OF: complete documentation
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-22-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 .../devicetree/bindings/spi/spi_atmel.txt          |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index 7ec3d8d..6d2e5e1 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -4,3 +4,18 @@ Required properties:
 - compatible : should be "atmel,at91rm9200-spi".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
+- cs-gpio: Should contain the GPIOs used for chipselect.
+
+spi0: spi at f0000000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "atmel,at91rm9200-spi";
+	reg = <0xf0000000 0x100>;
+	interrupts = <13 4>;
+	cs-gpios = <&pioA 14 0
+		    &pioA 7 0 /* conflicts with TXD2 */
+		    &pioA 1 0 /* conflicts with RXD0 */
+		    &pioB 3 0 /* conflicts with ERXDV */
+		   >;
+	status = "disabled";
+};
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:36 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:36 +0200
Subject: [PATCH 22/23] spi-atmel: complete DMA slave OF documentation
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-23-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 .../devicetree/bindings/spi/spi_atmel.txt          |   25 ++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index 6d2e5e1..b5d8082 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -5,6 +5,24 @@ Required properties:
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
 - cs-gpio: Should contain the GPIOs used for chipselect.
+- dma-mask: device coherent dma mask.
+/* dma transfer configuration. Cf DMA Channel configuration register */
+- dma: handle to the dma controller that should be used.
+- atc_src_per: source channel for DMA operation.
+- atc_dst_per: destination channel for DMA operation.
+- atc_src_h2sel_hw: Hardware handshaking interface is used to trigger a
+transfer request.
+- atc_dst_h2sel_hw: Hardware handshaking interface is used to trigger a
+transfer request.
+- atc_sod: STOP ON DONE activated.
+- atc_lock_if: Interface Lock capability is enabled.
+- atc_lock_b: AHB Bus Locking capability is enabled.
+- atc_lock_if_l_buffer: The Master Interface Arbiter is locked by the channel x for a buffer transfer.
+- atc_fifocfg_halffifo: When half FIFO size is available/filled, a source/destination request is serviced.
+- atc_fifocfg_enoughspace: When there is enough space/data available to perform a single AHB access, then the request is serviced.
+- atc_fifocfg_largestburst: The largest defined length AHB burst is performed on the destination AHB interface.
+- atc_ahb_prot: AHB Protection value. (cf release manual)
+
 
 spi0: spi at f0000000 {
 	#address-cells = <1>;
@@ -17,5 +35,12 @@ spi0: spi at f0000000 {
 		    &pioA 1 0 /* conflicts with RXD0 */
 		    &pioB 3 0 /* conflicts with ERXDV */
 		   >;
+	dma-mask = <0xffffffff>;
+	dma = <&dma0>;
+	atc_src_per = <2>; /* AT_DMA_ID_SPI0_RX */
+	atc_dst_per = <1>; /* AT_DMA_ID_SPI0_TX */
+	atc_fifocfg_halffifo;
+	atc_src_h2sel_hw;
+	atc_dst_h2sel_hw;
 	status = "disabled";
 };
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 09:49:37 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 15:49:37 +0200
Subject: [PATCH 23/23] sam9x5ek DTS: enable SPI dataflash
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1344952177-18385-24-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/boot/dts/at91sam9x5ek.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index e5000a7..c99f1cc 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -30,6 +30,16 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			spi0: spi at f0000000 {
+				status = "okay";
+				cs-gpios = <&pioA 14 0>;
+				m25p80 at 0 {
+					compatible = "atmel,at25df321a";
+					spi-max-frequency = <50000000>;
+					reg = <0>;
+				};
+			};
 		};
 
 		usb0: ohci at 00600000 {
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Aug 14 10:16:19 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 14 Aug 2012 16:16:19 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <CACQ1gAhPySejdoFfSW0chSF_5fHv9D5DYHb0D65xbExdb0n-7g@mail.gmail.com>

2012/8/14 Richard Genoud <richard.genoud at gmail.com>:
> Nicolas,
> I said that I had some work done on sam9g35-ek, here is the spi part, based
> on your and Jean-Christophe work.
> You have to enable CONFIG_ARCH_AT91SAM9X5 to get it work.
I forgot something:
As I didn't get pinctrl to work, on top of this patchset, I did a
revert of "ARM: at91: add pinctrl support"
and I made this change :
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e213e2d..bc3fdbf 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -313,6 +313,13 @@ static void __init at91sam9x5_map_io(void)
 	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }

+
+void __init at91sam9x5_initialize(void)
+{
+	/* Register GPIO subsystem (using DT) */
+	at91_gpio_init(NULL, 0);
+}
+
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
@@ -320,4 +327,5 @@ static void __init at91sam9x5_map_io(void)
 struct at91_init_soc __initdata at91sam9x5_soc = {
 	.map_io = at91sam9x5_map_io,
 	.register_clocks = at91sam9x5_register_clocks,
+	.init = at91sam9x5_initialize,
 };

I also enabled the spi controller in the DTS:
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi
b/arch/arm/boot/dts/at91sam9x5.dtsi
index ef09816..cc1c830 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -363,7 +363,7 @@
 				atc_fifocfg_halffifo;
 				atc_src_h2sel_hw;
 				atc_dst_h2sel_hw;
-				status = "disabled";
+				status = "okay";
 			};

 			spi1: spi at f0004000 {

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From shubhrajyoti at ti.com  Tue Aug 14 10:19:00 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:00 +0530
Subject: [PATCHv6 18/24] i2c: omap: remove redundant status read
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-19-git-send-email-shubhrajyoti@ti.com>

Remove the redundant read of the status register.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dfdcc2b..2dd2301 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -946,7 +946,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 				num_bytes = dev->buf_len;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
-			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
 				goto out;
 
@@ -962,7 +961,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 				num_bytes = dev->threshold;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
-			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
 				goto out;
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:50 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:50 +0530
Subject: [PATCHv6 08/24] i2c: omap: re-factor receive/transmit data loop
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-9-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

re-factor the common parts to a separate function,
so that code is easier to read and understand.

No functional changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |  204 ++++++++++++++++------------------------
 1 files changed, 82 insertions(+), 122 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0067875..d4b6f7d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -752,12 +752,81 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev)
 	return 0;
 }
 
+static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
+		bool is_rdr)
+{
+	u16		w;
+
+	while (num_bytes--) {
+		if (!dev->buf_len) {
+			dev_err(dev->dev, "%s without data",
+					is_rdr ? "RDR" : "RRDY");
+			break;
+		}
+
+		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+		*dev->buf++ = w;
+		dev->buf_len--;
+
+		/*
+		 * Data reg in 2430, omap3 and
+		 * omap4 is 8 bit wide
+		 */
+		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+			if (dev->buf_len) {
+				*dev->buf++ = w >> 8;
+				dev->buf_len--;
+			}
+		}
+	}
+}
+
+static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
+		bool is_xdr)
+{
+	u16		w;
+
+	while (num_bytes--) {
+		if (!dev->buf_len) {
+			dev_err(dev->dev, "%s without data",
+					is_xdr ? "XDR" : "XRDY");
+			break;
+		}
+
+		w = *dev->buf++;
+		dev->buf_len--;
+
+		/*
+		 * Data reg in 2430, omap3 and
+		 * omap4 is 8 bit wide
+		 */
+		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+			if (dev->buf_len) {
+				w |= *dev->buf++ << 8;
+				dev->buf_len--;
+			}
+		}
+
+		if (dev->errata & I2C_OMAP_ERRATA_I462) {
+			int ret;
+
+			ret = errata_omap3_i462(dev);
+			if (ret < 0)
+				return ret;
+		}
+
+		omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+	}
+
+	return 0;
+}
+
 static irqreturn_t
 omap_i2c_isr(int this_irq, void *dev_id)
 {
 	struct omap_i2c_dev *dev = dev_id;
 	u16 bits;
-	u16 stat, w;
+	u16 stat;
 	int err, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
@@ -810,30 +879,7 @@ complete:
 			if (dev->fifo_size)
 				num_bytes = dev->buf_len;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"RDR IRQ while no data"
-							" requested\n");
-					break;
-				}
-
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				*dev->buf++ = w;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						*dev->buf++ = w >> 8;
-						dev->buf_len--;
-					}
-				}
-			}
+			omap_i2c_receive_data(dev, num_bytes, true);
 
 			if (dev->errata & I2C_OMAP_ERRATA_I207)
 				i2c_omap_errata_i207(dev, stat);
@@ -848,77 +894,22 @@ complete:
 			if (dev->fifo_size)
 				num_bytes = dev->fifo_size;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"RRDY IRQ while no data"
-							" requested\n");
-					break;
-				}
-
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				*dev->buf++ = w;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						*dev->buf++ = w >> 8;
-						dev->buf_len--;
-					}
-				}
-			}
-
+			omap_i2c_receive_data(dev, num_bytes, false);
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 			continue;
 		}
 
 		if (stat & OMAP_I2C_STAT_XDR) {
 			u8 num_bytes = 1;
+			int ret;
 
 			if (dev->fifo_size)
 				num_bytes = dev->buf_len;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"XDR IRQ while no "
-							"data to send\n");
-					break;
-				}
-
-				w = *dev->buf++;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						w |= *dev->buf++ << 8;
-						dev->buf_len--;
-					}
-				}
-
-				if (dev->errata & I2C_OMAP_ERRATA_I462) {
-					int ret;
-
-					ret = errata_omap3_i462(dev);
-					stat = omap_i2c_read_reg(dev,
-							OMAP_I2C_STAT_REG);
-
-					if (ret < 0)
-						goto complete;
-				}
-
-				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
-			}
+			ret = omap_i2c_transmit_data(dev, num_bytes, true);
+			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+			if (ret < 0)
+				goto complete;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
 			continue;
@@ -926,46 +917,15 @@ complete:
 
 		if (stat & OMAP_I2C_STAT_XRDY) {
 			u8 num_bytes = 1;
+			int ret;
 
 			if (dev->fifo_size)
 				num_bytes = dev->fifo_size;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"XRDY IRQ while no "
-							"data to send\n");
-					break;
-				}
-
-				w = *dev->buf++;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						w |= *dev->buf++ << 8;
-						dev->buf_len--;
-					}
-				}
-
-				if (dev->errata & I2C_OMAP_ERRATA_I462) {
-					int ret;
-
-					ret = errata_omap3_i462(dev);
-					stat = omap_i2c_read_reg(dev,
-							OMAP_I2C_STAT_REG);
-
-					if (ret < 0)
-						goto complete;
-				}
-
-				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
-			}
+			ret = omap_i2c_transmit_data(dev, num_bytes, false);
+			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+			if (ret < 0)
+				goto complete;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:52 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:52 +0530
Subject: [PATCHv6 10/24] i2c: omap: ack IRQ in parts
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-11-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

According to flow diagrams on OMAP TRMs,
we should ACK the IRQ as they happen.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Ack the stat OMAP_I2C_STAT_AL in case of arbitration lost]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   28 ++++++++++++++++------------
 1 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8b80799..0adbfb1 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -850,21 +850,19 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		}
 
 complete:
-		/*
-		 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
-		 * acked after the data operation is complete.
-		 * Ref: TRM SWPU114Q Figure 18-31
-		 */
-		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
-				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
-
-		if (stat & OMAP_I2C_STAT_NACK)
+		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
+		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
 		/*
@@ -941,12 +939,18 @@ complete:
 
 		if (stat & OMAP_I2C_STAT_ROVR) {
 			dev_err(dev->dev, "Receive overrun\n");
-			dev->cmd_err |= OMAP_I2C_STAT_ROVR;
+			err |= OMAP_I2C_STAT_ROVR;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
-			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
+			err |= OMAP_I2C_STAT_XUDF;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 	} while (stat);
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:54 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:54 +0530
Subject: [PATCHv6 12/24] i2c: omap: bus: add a receiver flag
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-13-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that way we can ignore TX IRQs while in receiver
mode and ignore RX IRQs while in transmitter mode.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Remove unnecessary braces]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e9907b5..fa54d41 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -199,6 +199,7 @@ struct omap_i2c_dev {
 						 */
 	u8			rev;
 	unsigned		b_hw:1;		/* bad h/w fixes */
+	unsigned		receiver:1;	/* true when we're in receiver mode */
 	u16			iestate;	/* Saved interrupt register */
 	u16			pscstate;
 	u16			scllstate;
@@ -492,6 +493,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 
 	INIT_COMPLETION(dev->cmd_complete);
 	dev->cmd_err = 0;
+	dev->receiver = !!(msg->flags & I2C_M_RD);
 
 	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 
@@ -837,6 +839,12 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 		stat &= bits;
 
+		/* If we're in receiver mode, ignore XDR/XRDY */
+		if (dev->receiver)
+			stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
+		else
+			stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
+
 		if (!stat) {
 			/* my work here is done */
 			return IRQ_HANDLED;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:44 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:44 +0530
Subject: [PATCHv6 02/24] i2c: omap: simplify num_bytes handling
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-3-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

trivial patch, no functional changes

If the fifo is disabled or fifo_size is 0 the num_bytes
is set to 1. Else it is set to fifo_size or in case of a
draining interrupt the remaining bytes in the buff stat.
So the zero check is redundant and can be safely optimised.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 6449383..9b003a3 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -812,8 +812,7 @@ complete:
 							OMAP_I2C_BUFSTAT_REG)
 							>> 8) & 0x3F;
 			}
-			while (num_bytes) {
-				num_bytes--;
+			while (num_bytes--) {
 				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 				if (dev->buf_len) {
 					*dev->buf++ = w;
@@ -855,8 +854,7 @@ complete:
 							OMAP_I2C_BUFSTAT_REG)
 							& 0x3F;
 			}
-			while (num_bytes) {
-				num_bytes--;
+			while (num_bytes--) {
 				w = 0;
 				if (dev->buf_len) {
 					w = *dev->buf++;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:49 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:49 +0530
Subject: [PATCHv6 07/24] i2c: omap: improve i462 errata handling
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-8-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

Make it not depend on ISR's local variables
in order to make it easier to re-factor the
transmit data loop.
Also since we are waiting for XUDF(Transmitter underflow) just before
writing data lets not flag the underflow.
This is anyways going to go once we write
the data.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   43 ++++++++++++++++++++++++++++------------
 1 files changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 139602f..0067875 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -725,27 +725,30 @@ omap_i2c_omap1_isr(int this_irq, void *dev_id)
  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
  * them from the memory to the I2C interface.
  */
-static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err)
+static int errata_omap3_i462(struct omap_i2c_dev *dev)
 {
 	unsigned long timeout = 10000;
+	u16 stat;
 
-	while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
-		if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+	do {
+		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		if (stat & OMAP_I2C_STAT_XUDF)
+			break;
+
+		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
-			return -ETIMEDOUT;
+			return -EIO;
 		}
 
 		cpu_relax();
-		*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-	}
+	} while (--timeout);
 
 	if (!timeout) {
 		dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 		return 0;
 	}
 
-	*err |= OMAP_I2C_STAT_XUDF;
 	return 0;
 }
 
@@ -903,9 +906,16 @@ complete:
 					}
 				}
 
-				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
-				    errata_omap3_i462(dev, &stat, &err))
-					goto complete;
+				if (dev->errata & I2C_OMAP_ERRATA_I462) {
+					int ret;
+
+					ret = errata_omap3_i462(dev);
+					stat = omap_i2c_read_reg(dev,
+							OMAP_I2C_STAT_REG);
+
+					if (ret < 0)
+						goto complete;
+				}
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
@@ -943,9 +953,16 @@ complete:
 					}
 				}
 
-				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
-				    errata_omap3_i462(dev, &stat, &err))
-					goto complete;
+				if (dev->errata & I2C_OMAP_ERRATA_I462) {
+					int ret;
+
+					ret = errata_omap3_i462(dev);
+					stat = omap_i2c_read_reg(dev,
+							OMAP_I2C_STAT_REG);
+
+					if (ret < 0)
+						goto complete;
+				}
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:55 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:55 +0530
Subject: [PATCHv6 13/24] i2c: omap: simplify errata check
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-14-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

omap_i2c_dev is allocated with kzalloc(),
so we need not initialize b_hw to zero.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index fa54d41..80ebcf5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1095,9 +1095,7 @@ omap_i2c_probe(struct platform_device *pdev)
 
 		dev->fifo_size = (dev->fifo_size / 2);
 
-		if (dev->rev >= OMAP_I2C_REV_ON_3630_4430)
-			dev->b_hw = 0; /* Disable hardware fixes */
-		else
+		if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
 			dev->b_hw = 1; /* Enable hardware fixes */
 
 		/* calculate wakeup latency constraint for MPU */
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:47 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:47 +0530
Subject: [PATCHv6 05/24] i2c: omap: simplify omap_i2c_ack_stat()
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-6-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

stat & BIT(1) is the same as BIT(1), so let's
simplify things a bit by removing "stat &" from
all omap_i2c_ack_stat() calls.

Code snippet (extremely simplified):

if (stat & NACK) {
        ...
        omap_i2c_ack_stat(dev, stat & NACK);
}

if (stat & RDR) {
        ...
        omap_i2c_ack_stat(dev, stat & RDR);
}

and so on. The tricky place is only WRT errata handling, for example:

if (*stat & (NACK | AL)) {
        omap_i2c_ack_stat(dev, *stat & (XRDY | XDR));
        ...
}

but in this case, the errata says we must clear XRDY and XDR if that
errata triggers, so if they just got enabled or not, it doesn't matter.

Another tricky place is RDR | RRDY (likewise for XDR | XRDY):

if (stat & (RDR | RRDY)) {
        ...
        omap_i2c_ack_stat(dev, stat & (RDR | RRDY));
}

again here there will be no issues because those IRQs never fire
simultaneously and one will only after after we have handled the
previous, that's because the same FIFO is used anyway and we won't shift
data into FIFO until we tell the IP "hey, I'm done with the FIFO, you
can shift more data"

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
[Added the explaination from the discurssion to the commit logs]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   19 ++++++++++---------
 1 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dbc5a3c..8009095 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -731,7 +731,7 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err)
 
 	while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 		if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
 			return -ETIMEDOUT;
 		}
@@ -792,10 +792,11 @@ complete:
 		 */
 		if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 					OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, stat &
-				(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
-				OMAP_I2C_STAT_ARDY));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
+						OMAP_I2C_STAT_RDR |
+						OMAP_I2C_STAT_XRDY |
+						OMAP_I2C_STAT_XDR |
+						OMAP_I2C_STAT_ARDY));
 			omap_i2c_complete_cmd(dev, err);
 			return IRQ_HANDLED;
 		}
@@ -842,8 +843,8 @@ complete:
 					}
 				}
 			}
-			omap_i2c_ack_stat(dev,
-				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
+						OMAP_I2C_STAT_RDR));
 			continue;
 		}
 
@@ -890,8 +891,8 @@ complete:
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-			omap_i2c_ack_stat(dev,
-				stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
+						OMAP_I2C_STAT_XDR));
 			continue;
 		}
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:56 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:56 +0530
Subject: [PATCHv6 14/24] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-15-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

otherwise we could get our IRQ line disabled due
to many spurious IRQs.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 80ebcf5..eb6898b 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -962,7 +962,7 @@ complete:
 		}
 	} while (stat);
 
-	return count ? IRQ_HANDLED : IRQ_NONE;
+	return IRQ_HANDLED;
 }
 
 static const struct i2c_algorithm omap_i2c_algo = {
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:59 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:59 +0530
Subject: [PATCHv6 17/24] i2c: omap: get rid of the "complete" label
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-18-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

we can ack stat and complete the command from
the errata handling itself.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dfbf667..dfdcc2b 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -775,6 +775,17 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev)
 		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
+			if (stat & OMAP_I2C_STAT_NACK) {
+				dev->cmd_err |= OMAP_I2C_STAT_NACK;
+				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			}
+
+			if (stat & OMAP_I2C_STAT_AL) {
+				dev_err(dev->dev, "Arbitration lost\n");
+				dev->cmd_err |= OMAP_I2C_STAT_AL;
+				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			}
+
 			return -EIO;
 		}
 
@@ -875,7 +886,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 			goto out;
 		}
 
-complete:
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
@@ -938,7 +948,7 @@ complete:
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
-				goto complete;
+				goto out;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
 			continue;
@@ -954,7 +964,7 @@ complete:
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
-				goto complete;
+				goto out;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:01 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:01 +0530
Subject: [PATCHv6 19/24] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-20-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

even if our clocks are disabled, we still
handled the IRQ, so we should return IRQ_HANDLED.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2dd2301..f5eafb7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -862,7 +862,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	int err = 0, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
-		return IRQ_NONE;
+		return IRQ_HANDLED;
 
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:03 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:03 +0530
Subject: [PATCHv6 21/24] i2c: omap: remove unnecessary pm_runtime_suspended
 check
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-22-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

before starting any messages we call pm_runtime_get_sync()
which will make sure that by the time we program a transfer
and our IRQ handler gets called, we're not suspended
anymore.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 39e5d36..2d5db56 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -883,9 +883,6 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 	u16 stat;
 	int err = 0, count = 0;
 
-	if (pm_runtime_suspended(dev->dev))
-		return IRQ_HANDLED;
-
 	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:53 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:53 +0530
Subject: [PATCHv6 11/24] i2c: omap: switch to platform_get_irq()
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-12-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that's a nice helper from drivers core which
will give us the exact IRQ number, instead
of a pointer to an IRQ resource.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0adbfb1..e9907b5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -993,11 +993,12 @@ omap_i2c_probe(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev;
 	struct i2c_adapter	*adap;
-	struct resource		*mem, *irq;
+	struct resource		*mem;
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
 	irq_handler_t isr;
+	int irq;
 	int r;
 
 	/* NOTE: driver uses the static register mapping */
@@ -1006,10 +1007,11 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "no mem resource?\n");
 		return -ENODEV;
 	}
-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!irq) {
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
 		dev_err(&pdev->dev, "no irq resource?\n");
-		return -ENODEV;
+		return irq;
 	}
 
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
@@ -1043,7 +1045,7 @@ omap_i2c_probe(struct platform_device *pdev)
 	}
 
 	dev->dev = &pdev->dev;
-	dev->irq = irq->start;
+	dev->irq = irq;
 
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:02 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:02 +0530
Subject: [PATCHv6 20/24] i2c: omap: switch to threaded IRQ support
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-21-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

for OMAP2, we can easily switch over to threaded
IRQs on the I2C driver. This will allow us to
spend less time in hardirq context.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Trivial formating changes]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   43 +++++++++++++++++++++++++++++++++++-----
 1 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f5eafb7..39e5d36 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -176,6 +176,7 @@ enum {
 #define I2C_OMAP_ERRATA_I462		(1 << 1)
 
 struct omap_i2c_dev {
+	spinlock_t		lock;		/* IRQ synchronization */
 	struct device		*dev;
 	void __iomem		*base;		/* virtual */
 	int			irq;
@@ -854,9 +855,30 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 }
 
 static irqreturn_t
-omap_i2c_isr(int this_irq, void *dev_id)
+omap_i2c_isr(int irq, void *dev_id)
 {
 	struct omap_i2c_dev *dev = dev_id;
+	irqreturn_t ret = IRQ_HANDLED;
+	u16 mask;
+	u16 stat;
+
+	spin_lock(&dev->lock);
+	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+
+	if (stat & mask)
+		ret = IRQ_WAKE_THREAD;
+
+	spin_unlock(&dev->lock);
+
+	return ret;
+}
+
+static irqreturn_t
+omap_i2c_isr_thread(int this_irq, void *dev_id)
+{
+	struct omap_i2c_dev *dev = dev_id;
+	unsigned long flags;
 	u16 bits;
 	u16 stat;
 	int err = 0, count = 0;
@@ -864,6 +886,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	if (pm_runtime_suspended(dev->dev))
 		return IRQ_HANDLED;
 
+	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
@@ -877,6 +900,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
+			spin_unlock_irqrestore(&dev->lock, flags);
 			return IRQ_HANDLED;
 		}
 
@@ -985,6 +1009,8 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 out:
 	omap_i2c_complete_cmd(dev, err);
+	spin_unlock_irqrestore(&dev->lock, flags);
+
 	return IRQ_HANDLED;
 }
 
@@ -1028,7 +1054,6 @@ omap_i2c_probe(struct platform_device *pdev)
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
-	irq_handler_t isr;
 	int irq;
 	int r;
 
@@ -1078,6 +1103,8 @@ omap_i2c_probe(struct platform_device *pdev)
 	dev->dev = &pdev->dev;
 	dev->irq = irq;
 
+	spin_lock_init(&dev->lock);
+
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
 
@@ -1130,10 +1157,14 @@ omap_i2c_probe(struct platform_device *pdev)
 	/* reset ASAP, clearing any IRQs */
 	omap_i2c_init(dev);
 
-	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
-								   omap_i2c_isr;
-	r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
-			     pdev->name, dev);
+	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
+		r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
+				IRQF_NO_SUSPEND, pdev->name, dev);
+	else
+		r = devm_request_threaded_irq(&pdev->dev, dev->irq,
+				omap_i2c_isr, omap_i2c_isr_thread,
+				IRQF_NO_SUSPEND | IRQF_ONESHOT,
+				pdev->name, dev);
 
 	if (r) {
 		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:58 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:58 +0530
Subject: [PATCHv6 16/24] i2c: omap: resize fifos before each message
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-17-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

This patch will try to avoid the usage of
draining feature by reconfiguring the FIFO
the start condition of each message based
on the message's size.

By doing that, we will be better utilizing
the FIFO when doing big transfers.

While at that also drop the now unneeded
check for dev->buf_len as we always know
the amount of data to be transmitted.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   83 +++++++++++++++++++++++++----------------
 1 files changed, 51 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index b0b1705..dfbf667 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -193,6 +193,7 @@ struct omap_i2c_dev {
 	u8			*regs;
 	size_t			buf_len;
 	struct i2c_adapter	adapter;
+	u8			threshold;
 	u8			fifo_size;	/* use as flag and value
 						 * fifo_size==0 implies no fifo
 						 * if set, should be trsh+1
@@ -418,13 +419,6 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 
-	if (dev->fifo_size) {
-		/* Note: setup required fifo size - 1. RTRSH and XTRSH */
-		buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
-			(dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
-		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
-	}
-
 	/* Take the I2C module out of reset: */
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 
@@ -462,6 +456,45 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 	return 0;
 }
 
+static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
+{
+	u16		buf;
+
+	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
+		return;
+
+	/*
+	 * Set up notification threshold based on message size. We're doing
+	 * this to try and avoid draining feature as much as possible. Whenever
+	 * we have big messages to transfer (bigger than our total fifo size)
+	 * then we might use draining feature to transfer the remaining bytes.
+	 */
+
+	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
+
+	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
+
+	if (is_rx) {
+		/* Clear RX Threshold */
+		buf &= ~(0x3f << 8);
+		buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
+	} else {
+		/* Clear TX Threshold */
+		buf &= ~0x3f;
+		buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
+	}
+
+	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
+
+	if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
+		dev->b_hw = 1; /* Enable hardware fixes */
+
+	/* calculate wakeup latency constraint for MPU */
+	if (dev->set_mpu_wkup_lat != NULL)
+		dev->latency = (1000000 * dev->threshold) /
+			(1000 * dev->speed / 8);
+}
+
 /*
  * Low level master read/write transaction.
  */
@@ -478,6 +511,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 	if (msg->len == 0)
 		return -EINVAL;
 
+	dev->receiver = !!(msg->flags & I2C_M_RD);
+	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
+
 	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 
 	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
@@ -493,7 +529,6 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 
 	INIT_COMPLETION(dev->cmd_complete);
 	dev->cmd_err = 0;
-	dev->receiver = !!(msg->flags & I2C_M_RD);
 
 	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 
@@ -760,12 +795,6 @@ static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
 	u16		w;
 
 	while (num_bytes--) {
-		if (!dev->buf_len) {
-			dev_err(dev->dev, "%s without data",
-					is_rdr ? "RDR" : "RRDY");
-			break;
-		}
-
 		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 		*dev->buf++ = w;
 		dev->buf_len--;
@@ -775,10 +804,8 @@ static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
 		 * omap4 is 8 bit wide
 		 */
 		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			if (dev->buf_len) {
-				*dev->buf++ = w >> 8;
-				dev->buf_len--;
-			}
+			*dev->buf++ = w >> 8;
+			dev->buf_len--;
 		}
 	}
 }
@@ -789,12 +816,6 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 	u16		w;
 
 	while (num_bytes--) {
-		if (!dev->buf_len) {
-			dev_err(dev->dev, "%s without data",
-					is_xdr ? "XDR" : "XRDY");
-			break;
-		}
-
 		w = *dev->buf++;
 		dev->buf_len--;
 
@@ -803,10 +824,8 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 		 * omap4 is 8 bit wide
 		 */
 		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			if (dev->buf_len) {
-				w |= *dev->buf++ << 8;
-				dev->buf_len--;
-			}
+			w |= *dev->buf++ << 8;
+			dev->buf_len--;
 		}
 
 		if (dev->errata & I2C_OMAP_ERRATA_I462) {
@@ -901,8 +920,8 @@ complete:
 		if (stat & OMAP_I2C_STAT_RRDY) {
 			u8 num_bytes = 1;
 
-			if (dev->fifo_size)
-				num_bytes = dev->fifo_size;
+			if (dev->threshold)
+				num_bytes = dev->threshold;
 
 			omap_i2c_receive_data(dev, num_bytes, false);
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
@@ -929,8 +948,8 @@ complete:
 			u8 num_bytes = 1;
 			int ret;
 
-			if (dev->fifo_size)
-				num_bytes = dev->fifo_size;
+			if (dev->threshold)
+				num_bytes = dev->threshold;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:43 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:43 +0530
Subject: [PATCHv6 01/24] i2c: omap: switch to devm_* API
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-2-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that helps deleting some boiler plate code
and lets driver-core manage our resources
for us.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   41 ++++++++++++-----------------------------
 1 files changed, 12 insertions(+), 29 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 6849635..6449383 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -943,7 +943,7 @@ omap_i2c_probe(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev;
 	struct i2c_adapter	*adap;
-	struct resource		*mem, *irq, *ioarea;
+	struct resource		*mem, *irq;
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
@@ -962,17 +962,16 @@ omap_i2c_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	ioarea = request_mem_region(mem->start, resource_size(mem),
-			pdev->name);
-	if (!ioarea) {
-		dev_err(&pdev->dev, "I2C region already claimed\n");
-		return -EBUSY;
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "Menory allocation failed\n");
+		return -ENOMEM;
 	}
 
-	dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
-	if (!dev) {
-		r = -ENOMEM;
-		goto err_release_region;
+	dev->base = devm_request_and_ioremap(&pdev->dev, mem);
+	if (!dev->base) {
+		dev_err(&pdev->dev, "I2C region already claimed\n");
+		return -ENOMEM;
 	}
 
 	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
@@ -995,11 +994,6 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	dev->dev = &pdev->dev;
 	dev->irq = irq->start;
-	dev->base = ioremap(mem->start, resource_size(mem));
-	if (!dev->base) {
-		r = -ENOMEM;
-		goto err_free_mem;
-	}
 
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
@@ -1057,7 +1051,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
 								   omap_i2c_isr;
-	r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev);
+	r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
+			     pdev->name, dev);
 
 	if (r) {
 		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
@@ -1081,7 +1076,7 @@ omap_i2c_probe(struct platform_device *pdev)
 	r = i2c_add_numbered_adapter(adap);
 	if (r) {
 		dev_err(dev->dev, "failure adding adapter\n");
-		goto err_free_irq;
+		goto err_unuse_clocks;
 	}
 
 	of_i2c_register_devices(adap);
@@ -1090,18 +1085,12 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	return 0;
 
-err_free_irq:
-	free_irq(dev->irq, dev);
 err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(dev->dev);
-	iounmap(dev->base);
 	pm_runtime_disable(&pdev->dev);
 err_free_mem:
 	platform_set_drvdata(pdev, NULL);
-	kfree(dev);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
 
 	return r;
 }
@@ -1109,12 +1098,10 @@ err_release_region:
 static int __devexit omap_i2c_remove(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
-	struct resource		*mem;
 	int ret;
 
 	platform_set_drvdata(pdev, NULL);
 
-	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (IS_ERR_VALUE(ret))
@@ -1123,10 +1110,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
-	iounmap(dev->base);
-	kfree(dev);
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
 	return 0;
 }
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:46 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:46 +0530
Subject: [PATCHv6 04/24] i2c: omap: add blank lines
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-5-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

trivial patch to aid readability. No functional
changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 81ef0a7..dbc5a3c 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -786,6 +786,7 @@ complete:
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 		}
+
 		/*
 		 * ProDB0017052: Clear ARDY bit twice
 		 */
@@ -798,6 +799,7 @@ complete:
 			omap_i2c_complete_cmd(dev, err);
 			return IRQ_HANDLED;
 		}
+
 		if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 			u8 num_bytes = 1;
 
@@ -844,6 +846,7 @@ complete:
 				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 			continue;
 		}
+
 		if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 			u8 num_bytes = 1;
 			if (dev->fifo_size) {
@@ -891,10 +894,12 @@ complete:
 				stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 			continue;
 		}
+
 		if (stat & OMAP_I2C_STAT_ROVR) {
 			dev_err(dev->dev, "Receive overrun\n");
 			dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 		}
+
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:45 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:45 +0530
Subject: [PATCHv6 03/24] i2c: omap: decrease indentation level on data handling
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-4-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

The patch intends to decrease the indentation level on the
data handling
by using the fact that else of if (dev->buf_len) is same as
if (!dev->buf_len)

if (dev->buf_len) {
	aaa;
} else {
	bbb;
	break;
}

to

if (!dev->buf_len) {
        bbb;
        break;
}
aaa;

Hence no functional changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   63 ++++++++++++++++++++---------------------
 1 files changed, 31 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 9b003a3..81ef0a7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -813,22 +813,7 @@ complete:
 							>> 8) & 0x3F;
 			}
 			while (num_bytes--) {
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				if (dev->buf_len) {
-					*dev->buf++ = w;
-					dev->buf_len--;
-					/*
-					 * Data reg in 2430, omap3 and
-					 * omap4 is 8 bit wide
-					 */
-					if (dev->flags &
-						 OMAP_I2C_FLAG_16BIT_DATA_REG) {
-						if (dev->buf_len) {
-							*dev->buf++ = w >> 8;
-							dev->buf_len--;
-						}
-					}
-				} else {
+				if (!dev->buf_len) {
 					if (stat & OMAP_I2C_STAT_RRDY)
 						dev_err(dev->dev,
 							"RRDY IRQ while no data"
@@ -839,6 +824,21 @@ complete:
 								" requested\n");
 					break;
 				}
+
+				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+				*dev->buf++ = w;
+				dev->buf_len--;
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						*dev->buf++ = w >> 8;
+						dev->buf_len--;
+					}
+				}
 			}
 			omap_i2c_ack_stat(dev,
 				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
@@ -855,22 +855,7 @@ complete:
 							& 0x3F;
 			}
 			while (num_bytes--) {
-				w = 0;
-				if (dev->buf_len) {
-					w = *dev->buf++;
-					dev->buf_len--;
-					/*
-					 * Data reg in 2430, omap3 and
-					 * omap4 is 8 bit wide
-					 */
-					if (dev->flags &
-						 OMAP_I2C_FLAG_16BIT_DATA_REG) {
-						if (dev->buf_len) {
-							w |= *dev->buf++ << 8;
-							dev->buf_len--;
-						}
-					}
-				} else {
+				if (!dev->buf_len) {
 					if (stat & OMAP_I2C_STAT_XRDY)
 						dev_err(dev->dev,
 							"XRDY IRQ while no "
@@ -882,6 +867,20 @@ complete:
 					break;
 				}
 
+				w = *dev->buf++;
+				dev->buf_len--;
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						w |= *dev->buf++ << 8;
+						dev->buf_len--;
+					}
+				}
+
 				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
 				    errata_omap3_i462(dev, &stat, &err))
 					goto complete;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:51 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:51 +0530
Subject: [PATCHv6 09/24] i2c: omap: switch over to do {} while loop
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-10-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

this will make sure that we execute at least once.
No functional changes otherwise.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index d4b6f7d..8b80799 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -827,20 +827,28 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	struct omap_i2c_dev *dev = dev_id;
 	u16 bits;
 	u16 stat;
-	int err, count = 0;
+	int err = 0, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
 		return IRQ_NONE;
 
-	bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-	while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
+	do {
+		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		stat &= bits;
+
+		if (!stat) {
+			/* my work here is done */
+			return IRQ_HANDLED;
+		}
+
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			break;
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
-		err = 0;
 complete:
 		/*
 		 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
@@ -940,7 +948,7 @@ complete:
 			dev_err(dev->dev, "Transmit underflow\n");
 			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 		}
-	}
+	} while (stat);
 
 	return count ? IRQ_HANDLED : IRQ_NONE;
 }
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:48 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:48 +0530
Subject: [PATCHv6 06/24] i2c: omap: split out [XR]DR and [XR]RDY
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-7-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

While they do pretty much the same thing, there
are a few peculiarities. Specially WRT erratas,
it's best to split those out and re-factor the
read/write loop to another function which both
cases call.

This last part will be done on another patch.

While at that, also avoid an unncessary register
read since dev->fifo_len will always contain the
correct amount of data to be transferred.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |  126 ++++++++++++++++++++++++++++++-----------
 1 files changed, 92 insertions(+), 34 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8009095..139602f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -801,36 +801,62 @@ complete:
 			return IRQ_HANDLED;
 		}
 
-		if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
+		if (stat & OMAP_I2C_STAT_RDR) {
 			u8 num_bytes = 1;
 
+			if (dev->fifo_size)
+				num_bytes = dev->buf_len;
+
+			while (num_bytes--) {
+				if (!dev->buf_len) {
+					dev_err(dev->dev,
+							"RDR IRQ while no data"
+							" requested\n");
+					break;
+				}
+
+				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+				*dev->buf++ = w;
+				dev->buf_len--;
+
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						*dev->buf++ = w >> 8;
+						dev->buf_len--;
+					}
+				}
+			}
+
 			if (dev->errata & I2C_OMAP_ERRATA_I207)
 				i2c_omap_errata_i207(dev, stat);
 
-			if (dev->fifo_size) {
-				if (stat & OMAP_I2C_STAT_RRDY)
-					num_bytes = dev->fifo_size;
-				else    /* read RXSTAT on RDR interrupt */
-					num_bytes = (omap_i2c_read_reg(dev,
-							OMAP_I2C_BUFSTAT_REG)
-							>> 8) & 0x3F;
-			}
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
+			continue;
+		}
+
+		if (stat & OMAP_I2C_STAT_RRDY) {
+			u8 num_bytes = 1;
+
+			if (dev->fifo_size)
+				num_bytes = dev->fifo_size;
+
 			while (num_bytes--) {
 				if (!dev->buf_len) {
-					if (stat & OMAP_I2C_STAT_RRDY)
-						dev_err(dev->dev,
+					dev_err(dev->dev,
 							"RRDY IRQ while no data"
-								" requested\n");
-					if (stat & OMAP_I2C_STAT_RDR)
-						dev_err(dev->dev,
-							"RDR IRQ while no data"
-								" requested\n");
+							" requested\n");
 					break;
 				}
 
 				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 				*dev->buf++ = w;
 				dev->buf_len--;
+
 				/*
 				 * Data reg in 2430, omap3 and
 				 * omap4 is 8 bit wide
@@ -843,36 +869,68 @@ complete:
 					}
 				}
 			}
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
-						OMAP_I2C_STAT_RDR));
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 			continue;
 		}
 
-		if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
+		if (stat & OMAP_I2C_STAT_XDR) {
 			u8 num_bytes = 1;
-			if (dev->fifo_size) {
-				if (stat & OMAP_I2C_STAT_XRDY)
-					num_bytes = dev->fifo_size;
-				else    /* read TXSTAT on XDR interrupt */
-					num_bytes = omap_i2c_read_reg(dev,
-							OMAP_I2C_BUFSTAT_REG)
-							& 0x3F;
+
+			if (dev->fifo_size)
+				num_bytes = dev->buf_len;
+
+			while (num_bytes--) {
+				if (!dev->buf_len) {
+					dev_err(dev->dev,
+							"XDR IRQ while no "
+							"data to send\n");
+					break;
+				}
+
+				w = *dev->buf++;
+				dev->buf_len--;
+
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						w |= *dev->buf++ << 8;
+						dev->buf_len--;
+					}
+				}
+
+				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
+				    errata_omap3_i462(dev, &stat, &err))
+					goto complete;
+
+				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
+			continue;
+		}
+
+		if (stat & OMAP_I2C_STAT_XRDY) {
+			u8 num_bytes = 1;
+
+			if (dev->fifo_size)
+				num_bytes = dev->fifo_size;
+
 			while (num_bytes--) {
 				if (!dev->buf_len) {
-					if (stat & OMAP_I2C_STAT_XRDY)
-						dev_err(dev->dev,
+					dev_err(dev->dev,
 							"XRDY IRQ while no "
 							"data to send\n");
-					if (stat & OMAP_I2C_STAT_XDR)
-						dev_err(dev->dev,
-							"XDR IRQ while no "
-							"data to send\n");
 					break;
 				}
 
 				w = *dev->buf++;
 				dev->buf_len--;
+
 				/*
 				 * Data reg in 2430, omap3 and
 				 * omap4 is 8 bit wide
@@ -891,8 +949,8 @@ complete:
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
-						OMAP_I2C_STAT_XDR));
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
 		}
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:42 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:42 +0530
Subject: [PATCHv6 00/24] I2C big cleanup
Message-ID: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>

Changes since v1:
       - removed tabification on patch 6/17
       - removed dev_err() which was introduced on patch 09/17
Changes since v2:
        - do not set full fifo depth in the RDR interrupt.
        - some changelog updates.
        - rebase to the Wolfram's tree.
Changes since v3:
        - Remove a redundant read of status register
        - Read the dev->buf_len variable instead of the register
        as the information of the remaining bytes is there.
Changes since v4:
        - Ack the arbitration lost.
        - Rebase to the i2c-embedded/for-next branch.
Changes since v5:
        - Rebase to latest mainline
        - Added some more cleanup patches so as have a consolidated series.


Tested on omap4sdp and 3430sdp.
Functional testing.
Also did suspend resume test.


Previous disscurssion
http://www.spinics.net/lists/linux-i2c/msg09304.html

The following changes since commit 3bf671af14d591ede9251acb0085e8017f3705e7:

  Merge branch 'fixes-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds (2012-08-13 09:59:04 +0300)

are available in the git repository at:

  git://gitorious.org/linus-tree/linus-tree.git for_3.6/i2c/big_cleanup



Felipe Balbi (22):
  i2c: omap: switch to devm_* API
  i2c: omap: simplify num_bytes handling
  i2c: omap: decrease indentation level on data handling
  i2c: omap: add blank lines
  i2c: omap: simplify omap_i2c_ack_stat()
  i2c: omap: split out [XR]DR and [XR]RDY
  i2c: omap: improve i462 errata handling
  i2c: omap: re-factor receive/transmit data loop
  i2c: omap: switch over to do {} while loop
  i2c: omap: ack IRQ in parts
  i2c: omap: switch to platform_get_irq()
  i2c: omap: bus: add a receiver flag
  i2c: omap: simplify errata check
  i2c: omap: always return IRQ_HANDLED
  i2c: omap: simplify IRQ exit path
  i2c: omap: resize fifos before each message
  i2c: omap: get rid of the "complete" label
  i2c: omap: always return IRQ_HANDLED
  i2c: omap: switch to threaded IRQ support
  i2c: omap: remove unnecessary pm_runtime_suspended check
  i2c: omap: switch over to autosuspend API
  i2c: omap: sanitize exit path

Shubhrajyoti D (2):
  i2c: omap: remove redundant status read
  i2c: omap: Prevent NULL pointer dereference in remove

 drivers/i2c/busses/i2c-omap.c |  446 +++++++++++++++++++++++++----------------
 1 files changed, 273 insertions(+), 173 deletions(-)

-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:05 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:05 +0530
Subject: [PATCHv6 23/24] i2c: omap: sanitize exit path
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-24-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

move the goto out label one line down, so that
it can be used when stat is read as zero. All
other exits, can be done with a break statement.

While at that, also break out as soon as we
complete draining IRQ, since at that time
we know we transferred everything there was
to be transferred.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index d81189a..3df6f92 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -901,27 +901,26 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
-			spin_unlock_irqrestore(&dev->lock, flags);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
-			goto out;
+			break;
 		}
 
 		/*
@@ -934,7 +933,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 						OMAP_I2C_STAT_ARDY));
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RDR) {
@@ -949,7 +948,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 				i2c_omap_errata_i207(dev, stat);
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RRDY) {
@@ -972,10 +971,10 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XRDY) {
@@ -987,7 +986,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
@@ -997,19 +996,20 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 			dev_err(dev->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
-			goto out;
+			break;
 		}
 	} while (stat);
 
-out:
 	omap_i2c_complete_cmd(dev, err);
+
+out:
 	spin_unlock_irqrestore(&dev->lock, flags);
 
 	return IRQ_HANDLED;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:04 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:04 +0530
Subject: [PATCHv6 22/24] i2c: omap: switch over to autosuspend API
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-23-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message starting soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2d5db56..d81189a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -55,6 +55,9 @@
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
 
+/* timeout for pm runtime autosuspend */
+#define OMAP_I2C_PM_TIMEOUT		1000	/* ms */
+
 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
 enum {
 	OMAP_I2C_REV_REG = 0,
@@ -645,7 +648,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1117,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1190,7 +1197,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:18:57 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:48:57 +0530
Subject: [PATCHv6 15/24] i2c: omap: simplify IRQ exit path
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-16-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

instead of having multiple return points, use
a goto statement to make that clearer.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   20 ++++++++------------
 1 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index eb6898b..b0b1705 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -853,24 +853,21 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 complete:
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		/*
@@ -883,8 +880,7 @@ complete:
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 						OMAP_I2C_STAT_ARDY));
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_RDR) {
@@ -949,19 +945,19 @@ complete:
 			dev_err(dev->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 	} while (stat);
 
+out:
+	omap_i2c_complete_cmd(dev, err);
 	return IRQ_HANDLED;
 }
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Tue Aug 14 10:19:06 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Tue, 14 Aug 2012 19:49:06 +0530
Subject: [PATCHv6 24/24] i2c: omap: Prevent NULL pointer dereference in remove
In-Reply-To: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1344953946-13005-25-git-send-email-shubhrajyoti@ti.com>

Prevent the NULL pointer access by moving the platform_set_drvdata function
after the access of the pdev.

[  654.961761] Unable to handle kernel NULL pointer dereference at virtual address 00000070
[  654.970611] pgd = df254000
[  654.973480] [00000070] *pgd=9f1da831, *pte=00000000, *ppte=00000000
[  654.980163] Internal error: Oops: 17 [#1] SMP ARM
[  654.985076] Modules linked in:
[  654.988281] CPU: 1    Not tainted  (3.6.0-rc1-00031-ge547de1-dirty #339)
[  654.995330] PC is at omap_i2c_runtime_resume+0x8/0x148
[  655.000732] LR is at omap_i2c_runtime_resume+0x8/0x148

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 3df6f92..49dbff1 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1217,8 +1217,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
 	int ret;
 
-	platform_set_drvdata(pdev, NULL);
-
 	i2c_del_adapter(&dev->adapter);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (IS_ERR_VALUE(ret))
@@ -1227,6 +1225,8 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
+	platform_set_drvdata(pdev, NULL);
+
 	return 0;
 }
 
-- 
1.7.5.4



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:28 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:28 +0300
Subject: [PATCH v2 00/14] MFD/ASoC/Input: twl4030-audio submodule DT support
Message-ID: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v1:
- Get the MCLK frequencey from twl-core driver (via new API)
- hs_extmute_disable_level parameter has been removed
- empty of_find_node_by_name() in of.h for !CONFIG_OF builds

Mark: the extmute GPIO handling (when it is used) remained in the codec driver
for now. I can think more on how to add support for this type of mute control.
If you can point me to other codec needing this it would help on designing
something which is common enough for other users.
As for now I have a separate series to add GPIO controlled output amps (hp/spk).
I will send that to review soon.

Introl mail from v1:

The following series adds DT support for the twl4030 audio submodule which
provides audio codec and vibra functionality.

The MFD core driver is probed via DT, it will create the needed child devices
based on the provided information in the DT blob.
Child drivers (vibra, ASoC codec) will parse the core's node if needed to get
the needed parameters for their configuration.

In the ASoC codec driver the hs_extmute callback (which was used to toggle a
GPIO line) has been removed. The codec driver will receive the GPIO number
(if it is needed on the platform).

If the series is OK (and no objections from the maintainers), it would be good
if this can go via audio. Changed files are well contained within the
twl4030-audio stack so I do not expect merge issues later.

The series has been tested on BeagleBoard (with the McBSP DT series, and with
the upcoming DT audio support for BeagleBoard).

Regards,
Peter
---
Peter Ujfalusi (14):
  MFD: twl4030-audio: Clean up MODULE_* and platform_driver part
  MFD: twl4030-audio: Convert to use devm_kzalloc
  MFD: twl4030-audio: Rearange and clean-up the probe function
  MFD: twl-core: Add API to query the HFCLK rate
  MFD: twl4030-audio: Get audio MCLK via twl-core API instead of pdata
  dt: Add empty of_find_node_by_name() function
  MFD: twl4030-audio: Add DT support
  Input: twl4030-vibra: Support for DT booted kernel
  ASoC: twl4030: Move hs_extmute GPIO handling to driver
  ARM: OMAP/ASoC: Zoom2: Let the codec to handle the hs_extmute GPIO
  ASoC/MFD: twl4030: Remove set_hs_extmute callback from platform data
  ASoC: twl4030: Convert to use devm_kzalloc
  ASoC: twl4030: Add pointer to pdata within the private data
  ASoC: twl4030: Support for DT booted kernel

 .../devicetree/bindings/mfd/twl4030-audio.txt      |   46 +++++++++
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    9 +--
 arch/arm/mach-omap2/include/mach/board-zoom.h      |    2 -
 drivers/input/misc/twl4030-vibra.c                 |   20 ++++-
 drivers/mfd/twl-core.c                             |   32 ++++++
 drivers/mfd/twl4030-audio.c                        |  107 +++++++++++++-------
 include/linux/i2c/twl.h                            |    3 +-
 include/linux/of.h                                 |    6 +
 sound/soc/codecs/twl4030.c                         |  103 +++++++++++++++----
 sound/soc/omap/zoom2.c                             |    4 -
 10 files changed, 261 insertions(+), 71 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:29 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:29 +0300
Subject: [PATCH v2 01/14] MFD: twl4030-audio: Clean up MODULE_* and
 platform_driver part
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-2-git-send-email-peter.ujfalusi@ti.com>

Place the MODULE_* lines in the same block and add MODULE_DESCRIPTION.
Rearange the platform_driver structure at the same time.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index 838ce4e..ac04b4f 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -250,18 +250,18 @@ static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 	return 0;
 }
 
-MODULE_ALIAS("platform:twl4030-audio");
-
 static struct platform_driver twl4030_audio_driver = {
-	.probe		= twl4030_audio_probe,
-	.remove		= __devexit_p(twl4030_audio_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "twl4030-audio",
 	},
+	.probe		= twl4030_audio_probe,
+	.remove		= __devexit_p(twl4030_audio_remove),
 };
 
 module_platform_driver(twl4030_audio_driver);
 
 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi at ti.com>");
+MODULE_DESCRIPTION("TWL4030 audio block MFD driver");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:twl4030-audio");
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:30 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:30 +0300
Subject: [PATCH v2 02/14] MFD: twl4030-audio: Convert to use devm_kzalloc
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-3-git-send-email-peter.ujfalusi@ti.com>

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |   15 ++++++---------
 1 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index ac04b4f..efa2d42 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -188,7 +188,8 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
 					val, TWL4030_REG_APLL_CTL);
 
-	audio = kzalloc(sizeof(struct twl4030_audio), GFP_KERNEL);
+	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
+			     GFP_KERNEL);
 	if (!audio)
 		return -ENOMEM;
 
@@ -229,22 +230,18 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		ret = -ENODEV;
 	}
 
-	if (!ret)
-		return 0;
+	if (ret) {
+		platform_set_drvdata(pdev, NULL);
+		twl4030_audio_dev = NULL;
+	}
 
-	platform_set_drvdata(pdev, NULL);
-	kfree(audio);
-	twl4030_audio_dev = NULL;
 	return ret;
 }
 
 static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 {
-	struct twl4030_audio *audio = platform_get_drvdata(pdev);
-
 	mfd_remove_devices(&pdev->dev);
 	platform_set_drvdata(pdev, NULL);
-	kfree(audio);
 	twl4030_audio_dev = NULL;
 
 	return 0;
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:31 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:31 +0300
Subject: [PATCH v2 03/14] MFD: twl4030-audio: Rearange and clean-up the probe
 function
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-4-git-send-email-peter.ujfalusi@ti.com>

To facilitate the device tree support the probe function need to be rearanged.
Small cleanup in the APLL frequency selection part as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |   34 ++++++++++++++++------------------
 1 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index efa2d42..ca2d669 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -169,35 +169,30 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
+			     GFP_KERNEL);
+	if (!audio)
+		return -ENOMEM;
+
+	mutex_init(&audio->mutex);
+	audio->audio_mclk = pdata->audio_mclk;
+
 	/* Configure APLL_INFREQ and disable APLL if enabled */
-	val = 0;
-	switch (pdata->audio_mclk) {
+	switch (audio->audio_mclk) {
 	case 19200000:
-		val |= TWL4030_APLL_INFREQ_19200KHZ;
+		val = TWL4030_APLL_INFREQ_19200KHZ;
 		break;
 	case 26000000:
-		val |= TWL4030_APLL_INFREQ_26000KHZ;
+		val = TWL4030_APLL_INFREQ_26000KHZ;
 		break;
 	case 38400000:
-		val |= TWL4030_APLL_INFREQ_38400KHZ;
+		val = TWL4030_APLL_INFREQ_38400KHZ;
 		break;
 	default:
 		dev_err(&pdev->dev, "Invalid audio_mclk\n");
 		return -EINVAL;
 	}
-	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
-					val, TWL4030_REG_APLL_CTL);
-
-	audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
-			     GFP_KERNEL);
-	if (!audio)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, audio);
-
-	twl4030_audio_dev = pdev;
-	mutex_init(&audio->mutex);
-	audio->audio_mclk = pdata->audio_mclk;
+	twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, val, TWL4030_REG_APLL_CTL);
 
 	/* Codec power */
 	audio->resource[TWL4030_AUDIO_RES_POWER].reg = TWL4030_REG_CODEC_MODE;
@@ -222,6 +217,9 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		childs++;
 	}
 
+	platform_set_drvdata(pdev, audio);
+	twl4030_audio_dev = pdev;
+
 	if (childs)
 		ret = mfd_add_devices(&pdev->dev, pdev->id, audio->cells,
 				      childs, NULL, 0);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:32 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:32 +0300
Subject: [PATCH v2 04/14] MFD: twl-core: Add API to query the HFCLK rate
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-5-git-send-email-peter.ujfalusi@ti.com>

CFG_BOOT register's HFCLK_FREQ field hold information about the used HFCLK
frequency.
Add possibility for users to get the configured rate based on this
register.
This register was configured during boot, without it the chip would not
operate correctly, so we can trust on this information.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl-core.c  |   32 ++++++++++++++++++++++++++++++++
 include/linux/i2c/twl.h |    1 +
 2 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 1c32afe..f162b68 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -552,6 +552,38 @@ int twl_get_version(void)
 }
 EXPORT_SYMBOL_GPL(twl_get_version);
 
+/**
+ * twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
+ *
+ * Api to get the TWL HFCLK rate based on BOOT_CFG register.
+ */
+int twl_get_hfclk_rate(void)
+{
+	u8 ctrl;
+	int rate;
+
+	twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
+
+	switch (ctrl & 0x3) {
+	case HFCLK_FREQ_19p2_MHZ:
+		rate = 19200000;
+		break;
+	case HFCLK_FREQ_26_MHZ:
+		rate = 26000000;
+		break;
+	case HFCLK_FREQ_38p4_MHZ:
+		rate = 38400000;
+		break;
+	default:
+		pr_err("TWL4030: HFCLK is not configured\n");
+		rate = -EINVAL;
+		break;
+	}
+
+	return rate;
+}
+EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
+
 static struct device *
 add_numbered_child(unsigned chip, const char *name, int num,
 		void *pdata, unsigned pdata_len,
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 7ea898c..ac6488c 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -188,6 +188,7 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
 
 int twl_get_type(void);
 int twl_get_version(void);
+int twl_get_hfclk_rate(void);
 
 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:34 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:34 +0300
Subject: [PATCH v2 06/14] dt: Add empty of_find_node_by_name() function
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-7-git-send-email-peter.ujfalusi@ti.com>

This commit adds an empty of_find_node_by_name() function for !CONFIG_OF
builds.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/of.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/linux/of.h b/include/linux/of.h
index 5919ee3..c90e59a 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -308,6 +308,12 @@ static inline const char* of_node_full_name(struct device_node *np)
 	return "<no-node>";
 }
 
+static inline device_node *of_find_node_by_name(struct device_node *from,
+	const char *name)
+{
+	return NULL;
+}
+
 static inline bool of_have_populated_dt(void)
 {
 	return false;
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:36 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:36 +0300
Subject: [PATCH v2 08/14] Input: twl4030-vibra: Support for DT booted kernel
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-9-git-send-email-peter.ujfalusi@ti.com>

Add support when the kernel has been booted with DT blob. In this case the
pdata is NULL, we need to reach up to the core node and check if the codec
part has been enabled to determine if we need to coexist with the codec or
not.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/input/misc/twl4030-vibra.c |   20 ++++++++++++++++++--
 1 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/input/misc/twl4030-vibra.c b/drivers/input/misc/twl4030-vibra.c
index d1e1a7e..2cfc6c7 100644
--- a/drivers/input/misc/twl4030-vibra.c
+++ b/drivers/input/misc/twl4030-vibra.c
@@ -26,6 +26,7 @@
 #include <linux/module.h>
 #include <linux/jiffies.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/workqueue.h>
 #include <linux/i2c/twl.h>
 #include <linux/mfd/twl4030-audio.h>
@@ -194,13 +195,28 @@ static int twl4030_vibra_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(twl4030_vibra_pm_ops,
 			 twl4030_vibra_suspend, twl4030_vibra_resume);
 
+static bool twl4030_vibra_check_coexist(struct twl4030_vibra_data *pdata,
+			      struct device_node *node)
+{
+	if (pdata && pdata->coexist)
+		return true;
+
+#ifdef CONFIG_OF
+	if (of_find_node_by_name(node, "codec"))
+		return true;
+#endif
+
+	return false;
+}
+
 static int __devinit twl4030_vibra_probe(struct platform_device *pdev)
 {
 	struct twl4030_vibra_data *pdata = pdev->dev.platform_data;
+	struct device_node *twl4030_core_node = pdev->dev.parent->of_node;
 	struct vibra_info *info;
 	int ret;
 
-	if (!pdata) {
+	if (!pdata && !twl4030_core_node) {
 		dev_dbg(&pdev->dev, "platform_data not available\n");
 		return -EINVAL;
 	}
@@ -210,7 +226,7 @@ static int __devinit twl4030_vibra_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	info->dev = &pdev->dev;
-	info->coexist = pdata->coexist;
+	info->coexist = twl4030_vibra_check_coexist(pdata, twl4030_core_node);
 	INIT_WORK(&info->play_work, vibra_play_work);
 
 	info->input_dev = input_allocate_device();
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:33 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:33 +0300
Subject: [PATCH v2 05/14] MFD: twl4030-audio: Get audio MCLK via twl-core API
 instead of pdata
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-6-git-send-email-peter.ujfalusi@ti.com>

twl-core has API to get the boot time configured HFCLK rate which has the
same rate as the audio MCLK.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl4030-audio.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index ca2d669..a48bf3a 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -175,7 +175,7 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	mutex_init(&audio->mutex);
-	audio->audio_mclk = pdata->audio_mclk;
+	audio->audio_mclk = twl_get_hfclk_rate();
 
 	/* Configure APLL_INFREQ and disable APLL if enabled */
 	switch (audio->audio_mclk) {
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:35 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:35 +0300
Subject: [PATCH v2 07/14] MFD: twl4030-audio: Add DT support
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-8-git-send-email-peter.ujfalusi@ti.com>

Support for loading the twl4030 audio module via devicetree.
Sub devices for codec and vibra will be created as mfd devices once the
core MFD driver is loaded when the kernel is booted with a DT blob.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/mfd/twl4030-audio.txt      |   46 ++++++++++++++++
 drivers/mfd/twl4030-audio.c                        |   56 +++++++++++++++++---
 2 files changed, 95 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt

diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
new file mode 100644
index 0000000..414d2ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt
@@ -0,0 +1,46 @@
+Texas Instruments TWL family (twl4030) audio module
+
+The audio module inside the TWL family consist of an audio codec and a vibra
+driver.
+
+Required properties:
+- compatible : must be "ti,twl4030-audio"
+
+Optional properties, nodes:
+
+Audio functionality:
+- codec { }: Need to be present if the audio functionality is used. Within this
+	     section the following options can be used:
+- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts
+		    from the start of the recorded sample (in ms)
+-ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise
+-ti,hs_extmute: Use external mute for HS pop reduction
+-ti,hs_extmute_gpio: Use external GPIO to control the external mute
+-ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
+		      valid values.
+
+Vibra functionality
+- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if
+		   missing or it is 0, the vibra functionality is disabled.
+
+Example:
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl at 48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+
+			ti,enable-vibra = <1>;
+
+			codec {
+				ti,ramp_delay_value = <3>;
+			};
+
+		};
+	};
+};
diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c
index a48bf3a..ed9c5d9 100644
--- a/drivers/mfd/twl4030-audio.c
+++ b/drivers/mfd/twl4030-audio.c
@@ -28,6 +28,8 @@
 #include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/i2c/twl.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/twl4030-audio.h>
@@ -156,15 +158,44 @@ unsigned int twl4030_audio_get_mclk(void)
 }
 EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk);
 
+static bool twl4030_audio_has_codec(struct twl4030_audio_data *pdata,
+			      struct device_node *node)
+{
+	if (pdata && pdata->codec)
+		return true;
+
+#ifdef CONFIG_OF
+	if (of_find_node_by_name(node, "codec"))
+		return true;
+#endif
+
+	return false;
+}
+
+static bool twl4030_audio_has_vibra(struct twl4030_audio_data *pdata,
+			      struct device_node *node)
+{
+	int vibra;
+
+	if (pdata && pdata->vibra)
+		return true;
+
+	if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
+		return true;
+
+	return false;
+}
+
 static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 {
 	struct twl4030_audio *audio;
 	struct twl4030_audio_data *pdata = pdev->dev.platform_data;
+	struct device_node *node = pdev->dev.of_node;
 	struct mfd_cell *cell = NULL;
 	int ret, childs = 0;
 	u8 val;
 
-	if (!pdata) {
+	if (!pdata && !node) {
 		dev_err(&pdev->dev, "Platform data is missing\n");
 		return -EINVAL;
 	}
@@ -202,18 +233,22 @@ static int __devinit twl4030_audio_probe(struct platform_device *pdev)
 	audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL;
 	audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN;
 
-	if (pdata->codec) {
+	if (twl4030_audio_has_codec(pdata, node)) {
 		cell = &audio->cells[childs];
 		cell->name = "twl4030-codec";
-		cell->platform_data = pdata->codec;
-		cell->pdata_size = sizeof(*pdata->codec);
+		if (pdata) {
+			cell->platform_data = pdata->codec;
+			cell->pdata_size = sizeof(*pdata->codec);
+		}
 		childs++;
 	}
-	if (pdata->vibra) {
+	if (twl4030_audio_has_vibra(pdata, node)) {
 		cell = &audio->cells[childs];
 		cell->name = "twl4030-vibra";
-		cell->platform_data = pdata->vibra;
-		cell->pdata_size = sizeof(*pdata->vibra);
+		if (pdata) {
+			cell->platform_data = pdata->vibra;
+			cell->pdata_size = sizeof(*pdata->vibra);
+		}
 		childs++;
 	}
 
@@ -245,10 +280,17 @@ static int __devexit twl4030_audio_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id twl4030_audio_of_match[] = {
+	{.compatible = "ti,twl4030-audio", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, twl4030_audio_of_match);
+
 static struct platform_driver twl4030_audio_driver = {
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "twl4030-audio",
+		.of_match_table = twl4030_audio_of_match,
 	},
 	.probe		= twl4030_audio_probe,
 	.remove		= __devexit_p(twl4030_audio_remove),
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:39 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:39 +0300
Subject: [PATCH v2 11/14] ASoC/MFD: twl4030: Remove set_hs_extmute callback
 from platform data
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-12-git-send-email-peter.ujfalusi@ti.com>

We no longer have users for the set_hs_extmute callback which has been
replaced by hs_extmute_gpio so the codec driver can handle the external
mute if it is needed by the board.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/i2c/twl.h    |    2 --
 sound/soc/codecs/twl4030.c |    6 ------
 2 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 2040309..a4885a6 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -667,8 +667,6 @@ struct twl4030_codec_data {
 	unsigned int check_defaults:1;
 	unsigned int reset_registers:1;
 	unsigned int hs_extmute:1;
-	void (*set_hs_extmute)(int mute); /* Deprecated, use hs_extmute_gpio and
-					     hs_extmute_disable_level */
 	int hs_extmute_gpio;
 };
 
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 5fc271a..27ccea4 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -767,9 +767,6 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 	if (pdata && pdata->hs_extmute) {
 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
 			gpio_set_value(pdata->hs_extmute_gpio, 1);
-		} else if (pdata->set_hs_extmute) {
-			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
-			pdata->set_hs_extmute(1);
 		} else {
 			hs_pop |= TWL4030_EXTMUTE;
 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
@@ -808,9 +805,6 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 	if (pdata && pdata->hs_extmute) {
 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
 			gpio_set_value(pdata->hs_extmute_gpio, 0);
-		} else if (pdata->set_hs_extmute) {
-			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
-			pdata->set_hs_extmute(0);
 		} else {
 			hs_pop &= ~TWL4030_EXTMUTE;
 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:38 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:38 +0300
Subject: [PATCH v2 10/14] ARM: OMAP/ASoC: Zoom2: Let the codec to handle the
 hs_extmute GPIO
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-11-git-send-email-peter.ujfalusi@ti.com>

Remove the use of set_hs_extmute callback and let the codec driver to
handle the extmute GPIO.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/board-zoom-peripherals.c  |    9 ++-------
 arch/arm/mach-omap2/include/mach/board-zoom.h |    2 --
 sound/soc/omap/zoom2.c                        |    4 ----
 3 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index b797cb2..a7d3b04 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -34,6 +34,7 @@
 #include "common-board-devices.h"
 
 #define OMAP_ZOOM_WLAN_PMENA_GPIO	(101)
+#define ZOOM2_HEADSET_EXTMUTE_GPIO	(153)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO		(162)
 
 #define LCD_PANEL_ENABLE_GPIO		(7 + OMAP_MAX_GPIO_LINES)
@@ -244,12 +245,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
 	return ret;
 }
 
-/* EXTMUTE callback function */
-static void zoom2_set_hs_extmute(int mute)
-{
-	gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
-}
-
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
 	.gpio_base	= OMAP_MAX_GPIO_LINES,
 	.irq_base	= TWL4030_GPIO_IRQ_BASE,
@@ -279,7 +274,7 @@ static int __init omap_i2c_init(void)
 
 		codec_data->ramp_delay_value = 3;	/* 161 ms */
 		codec_data->hs_extmute = 1;
-		codec_data->set_hs_extmute = zoom2_set_hs_extmute;
+		codec_data->hs_extmute_gpio = ZOOM2_HEADSET_EXTMUTE_GPIO;
 	}
 	omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
 	omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 775fdc3..2e94869 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -8,5 +8,3 @@
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
 extern void __init zoom_display_init(void);
-
-#define ZOOM2_HEADSET_EXTMUTE_GPIO	153
diff --git a/sound/soc/omap/zoom2.c b/sound/soc/omap/zoom2.c
index 920e0d9..df97a41 100644
--- a/sound/soc/omap/zoom2.c
+++ b/sound/soc/omap/zoom2.c
@@ -191,9 +191,6 @@ static int __init zoom2_soc_init(void)
 	BUG_ON(gpio_request(ZOOM2_HEADSET_MUX_GPIO, "hs_mux") < 0);
 	gpio_direction_output(ZOOM2_HEADSET_MUX_GPIO, 0);
 
-	BUG_ON(gpio_request(ZOOM2_HEADSET_EXTMUTE_GPIO, "ext_mute") < 0);
-	gpio_direction_output(ZOOM2_HEADSET_EXTMUTE_GPIO, 0);
-
 	return 0;
 
 err1:
@@ -207,7 +204,6 @@ module_init(zoom2_soc_init);
 static void __exit zoom2_soc_exit(void)
 {
 	gpio_free(ZOOM2_HEADSET_MUX_GPIO);
-	gpio_free(ZOOM2_HEADSET_EXTMUTE_GPIO);
 
 	platform_device_unregister(zoom2_snd_device);
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:37 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:37 +0300
Subject: [PATCH v2 09/14] ASoC: twl4030: Move hs_extmute GPIO handling to
 driver
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-10-git-send-email-peter.ujfalusi@ti.com>

The external mute (if it is in use) is handled by a GPIO line. Prepare to
remove the set_hs_extmute callback and replace it with:
hs_extmute_gpio: the GPIO number to use for external mute

When the users of set_hs_extmute has been converted the callback can be removed.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/i2c/twl.h    |    4 +++-
 sound/soc/codecs/twl4030.c |   32 ++++++++++++++++++++++++++++++--
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index ac6488c..2040309 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -667,7 +667,9 @@ struct twl4030_codec_data {
 	unsigned int check_defaults:1;
 	unsigned int reset_registers:1;
 	unsigned int hs_extmute:1;
-	void (*set_hs_extmute)(int mute);
+	void (*set_hs_extmute)(int mute); /* Deprecated, use hs_extmute_gpio and
+					     hs_extmute_disable_level */
+	int hs_extmute_gpio;
 };
 
 struct twl4030_vibra_data {
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 391fcfc..5fc271a 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -28,6 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c/twl.h>
 #include <linux/slab.h>
+#include <linux/gpio.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -302,6 +303,22 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
 	u8 reg, byte;
 	int i = 0;
 
+	if (pdata && pdata->hs_extmute &&
+	    gpio_is_valid(pdata->hs_extmute_gpio)) {
+		int ret;
+
+		if (!pdata->hs_extmute_gpio)
+			dev_warn(codec->dev,
+				 "Extmute GPIO is 0 is this correct?\n");
+
+		ret = gpio_request_one(pdata->hs_extmute_gpio,
+				       GPIOF_OUT_INIT_LOW, "hs_extmute");
+		if (ret) {
+			dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
+			pdata->hs_extmute_gpio = -1;
+		}
+	}
+
 	/* Check defaults, if instructed before anything else */
 	if (pdata && pdata->check_defaults)
 		twl4030_check_defaults(codec);
@@ -748,7 +765,10 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 	/* Enable external mute control, this dramatically reduces
 	 * the pop-noise */
 	if (pdata && pdata->hs_extmute) {
-		if (pdata->set_hs_extmute) {
+		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
+			gpio_set_value(pdata->hs_extmute_gpio, 1);
+		} else if (pdata->set_hs_extmute) {
+			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
 			pdata->set_hs_extmute(1);
 		} else {
 			hs_pop |= TWL4030_EXTMUTE;
@@ -786,7 +806,10 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 
 	/* Disable external mute */
 	if (pdata && pdata->hs_extmute) {
-		if (pdata->set_hs_extmute) {
+		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
+			gpio_set_value(pdata->hs_extmute_gpio, 0);
+		} else if (pdata->set_hs_extmute) {
+			dev_warn(codec->dev, "set_hs_extmute is deprecated\n");
 			pdata->set_hs_extmute(0);
 		} else {
 			hs_pop &= ~TWL4030_EXTMUTE;
@@ -2230,12 +2253,17 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 
 static int twl4030_soc_remove(struct snd_soc_codec *codec)
 {
+	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
 	twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
 	kfree(twl4030);
+
+	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
+		gpio_free(pdata->hs_extmute_gpio);
+
 	return 0;
 }
 
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:40 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:40 +0300
Subject: [PATCH v2 12/14] ASoC: twl4030: Convert to use devm_kzalloc
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-13-git-send-email-peter.ujfalusi@ti.com>

Allocate the private data with devm_kzalloc.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 27ccea4..413e698 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -2231,7 +2231,8 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 {
 	struct twl4030_priv *twl4030;
 
-	twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
+	twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
+			       GFP_KERNEL);
 	if (twl4030 == NULL) {
 		dev_err(codec->dev, "Can not allocate memory\n");
 		return -ENOMEM;
@@ -2253,7 +2254,6 @@ static int twl4030_soc_remove(struct snd_soc_codec *codec)
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
 	twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
-	kfree(twl4030);
 
 	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
 		gpio_free(pdata->hs_extmute_gpio);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:41 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:41 +0300
Subject: [PATCH v2 13/14] ASoC: twl4030: Add pointer to pdata within the
 private data
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-14-git-send-email-peter.ujfalusi@ti.com>

Access the pdata via a pointer within the twl4030_priv structure.
In preparation for DeviceTree support.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 413e698..8b13d50 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -153,8 +153,7 @@ struct twl4030_priv {
 	u8 predrivel_enabled, predriver_enabled;
 	u8 carkitl_enabled, carkitr_enabled;
 
-	/* Delay needed after enabling the digimic interface */
-	unsigned int digimic_delay;
+	struct twl4030_codec_data *pdata;
 };
 
 /*
@@ -348,7 +347,7 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
 	if (!pdata)
 		return;
 
-	twl4030->digimic_delay = pdata->digimic_delay;
+	twl4030->pdata = pdata;
 
 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
 	reg &= ~TWL4030_RAMP_DELAY;
@@ -749,9 +748,9 @@ static int aif_event(struct snd_soc_dapm_widget *w,
 
 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
 {
-	struct twl4030_codec_data *pdata = codec->dev->platform_data;
 	unsigned char hs_gain, hs_pop;
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 	/* Base values for ramp delay calculation: 2^19 - 2^26 */
 	unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
 				    8388608, 16777216, 33554432, 67108864};
@@ -864,9 +863,10 @@ static int digimic_event(struct snd_soc_dapm_widget *w,
 		struct snd_kcontrol *kcontrol, int event)
 {
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 
-	if (twl4030->digimic_delay)
-		twl4030_wait_ms(twl4030->digimic_delay);
+	if (pdata && pdata->digimic_delay)
+		twl4030_wait_ms(pdata->digimic_delay);
 	return 0;
 }
 
@@ -2248,8 +2248,8 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
 
 static int twl4030_soc_remove(struct snd_soc_codec *codec)
 {
-	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
+	struct twl4030_codec_data *pdata = twl4030->pdata;
 
 	/* Reset registers to their chip default before leaving */
 	twl4030_reset_registers(codec);
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Tue Aug 14 10:22:42 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 14 Aug 2012 17:22:42 +0300
Subject: [PATCH v2 14/14] ASoC: twl4030: Support for DT booted kernel
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1344954162-7985-15-git-send-email-peter.ujfalusi@ti.com>

When the kernel has been booted with DT blob the platform data is NULL for
the driver.
We need to construct the pdata based on the DT information for runtime use.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/twl4030.c |   57 +++++++++++++++++++++++++++++++++++++------
 1 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 8b13d50..f13c91a 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -26,6 +26,8 @@
 #include <linux/pm.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/slab.h>
 #include <linux/gpio.h>
@@ -295,13 +297,59 @@ static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
 
 }
 
-static void twl4030_init_chip(struct snd_soc_codec *codec)
+static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
+				   struct device_node *node)
+{
+	int value;
+
+	of_property_read_u32(node, "ti,digimic_delay",
+			     &pdata->digimic_delay);
+	of_property_read_u32(node, "ti,ramp_delay_value",
+			     &pdata->ramp_delay_value);
+	of_property_read_u32(node, "ti,offset_cncl_path",
+			     &pdata->offset_cncl_path);
+	if (!of_property_read_u32(node, "ti,hs_extmute", &value))
+		pdata->hs_extmute = value;
+
+	pdata->hs_extmute_gpio = of_get_named_gpio(node,
+						   "ti,hs_extmute_gpio", 0);
+	if (gpio_is_valid(pdata->hs_extmute_gpio))
+		pdata->hs_extmute = 1;
+}
+
+static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
 {
 	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
+	struct device_node *twl4030_codec_node = NULL;
+
+#ifdef CONFIG_OF
+	twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
+						  "codec");
+#endif
+
+	if (!pdata && twl4030_codec_node) {
+		pdata = devm_kzalloc(codec->dev,
+				     sizeof(struct twl4030_codec_data),
+				     GFP_KERNEL);
+		if (!pdata) {
+			dev_err(codec->dev, "Can not allocate memory\n");
+			return NULL;
+		}
+		twl4030_setup_pdata_of(pdata, twl4030_codec_node);
+	}
+
+	return pdata;
+}
+
+static void twl4030_init_chip(struct snd_soc_codec *codec)
+{
+	struct twl4030_codec_data *pdata;
 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
 	u8 reg, byte;
 	int i = 0;
 
+	pdata = twl4030_get_pdata(codec);
+
 	if (pdata && pdata->hs_extmute &&
 	    gpio_is_valid(pdata->hs_extmute_gpio)) {
 		int ret;
@@ -2284,13 +2332,6 @@ static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
 
 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
 {
-	struct twl4030_codec_data *pdata = pdev->dev.platform_data;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "platform_data is missing\n");
-		return -EINVAL;
-	}
-
 	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
 			twl4030_dai, ARRAY_SIZE(twl4030_dai));
 }
-- 
1.7.8.6



From anilkumar at ti.com  Tue Aug 14 10:25:11 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 14 Aug 2012 14:25:11 +0000
Subject: [PATCH v2 0/4] Add AM33XX regulators device tree data
In-Reply-To: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA12932@DBDE01.ent.ti.com>

Hi Mark,

On Tue, Jul 24, 2012 at 11:48:51, AnilKumar, Chimata wrote:
> This patch series add AM33XX regulators (tps65910/tps65217) device
> tree data to am335x-evm and am335x-bone dts files. These patches
> are based on Tony L "devel-dt" tree and tested on AM335x EVM and
> Bone devices.
> 
> Changes from v1:
> 	- Incorporated all Mark Brown's review comments on v1 by
> 	  * moving all the regulator constraints to corresponding
> 	    DTS file
> 	  * Regulator constraints are added according to board.
> 	- regulator name is added.
> 
> AnilKumar Ch (4):
>   ARM: OMAP2+: AM33XX: Add tps65910 device tree data
>   ARM: OMAP2+: AM33XX: Add tps65217 device tree data
>   arm/dts: Add tps65910 regulator DT data to am335x-evm.dts
>   arm/dts: Add tps65217 regulator DT data to am335x-bone.dts
> 
>  arch/arm/boot/dts/am335x-bone.dts |   28 ++++++++++++
>  arch/arm/boot/dts/am335x-evm.dts  |   28 ++++++++++++
>  arch/arm/boot/dts/tps65217.dtsi   |   56 ++++++++++++++++++++++++
>  arch/arm/boot/dts/tps65910.dtsi   |   86 +++++++++++++++++++++++++++++++++++++
>  4 files changed, 198 insertions(+)
>  create mode 100644 arch/arm/boot/dts/tps65217.dtsi
>  create mode 100644 arch/arm/boot/dts/tps65910.dtsi
> 
> -- 
> 1.7.9.5

With the recent changes in the regulator core driver which disables all
the regulators if always-on flag is not present. So I have to update
these patch to add all the regulator nodes with always-on flag.

I will submit the updated version of patch series.

Regards
AnilKumar


From anilkumar at ti.com  Tue Aug 14 10:25:18 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 14 Aug 2012 14:25:18 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <1343110735-10640-4-git-send-email-anilkumar@ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>

Hi Mark,

On Tue, Jul 24, 2012 at 11:48:54, AnilKumar, Chimata wrote:
> Add tps65910 regulator device tree data to AM335x-EVM by adding
> regulator consumers with tightened constraints and regulator-name.
> TPS65910 regulator handle can be obtained by using this regulator
> name.
> 
> This patch also add I2C node with I2C frequency and tps65910 PMIC
> I2C slave address.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  arch/arm/boot/dts/am335x-evm.dts |   28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> index d6a97d9..e4e1ccb 100644
> --- a/arch/arm/boot/dts/am335x-evm.dts
> +++ b/arch/arm/boot/dts/am335x-evm.dts
> @@ -18,3 +18,31 @@
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
>  };
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +
> +	tps: tps at 2D {
> +		reg = <0x2D>;
> +	};
> +};
> +
> +/include/ "tps65910.dtsi"
> +
> +&vdd1_reg {
> +	/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
> +	regulator-name = "vdd_mpu";
> +	regulator-min-microvolt = <912500>;
> +	regulator-max-microvolt = <1312500>;
> +	regulator-boot-on;
> +	regulator-always-on;
> +};

I want to understand how to add parent regulator nodes? Like input-supply
node to regulators.

With "regulator: tps65910: add support for input supply" patch, regulator
registration fails if we are not providing the input_supply node with
proper input supply name.

AM335x EVM have one dedicated input supply which provide supplies to all
the PMIC regulators. According to tps65910 "VDD1 regulator" input supply
is from vcc1 so we have to create a dummy/parent/some node to handle this.
Example below has the details.

In am335x-evm.dts file

vcc1_supply: fixedregulator at 0 {
                compatible = "regulator-fixed";
                regulator-name = "vcc1";
                regulator-boot-on;
};

/include/ "tps65910.dtsi"

&tps {
	regulators {
		vcc1-supply = <&vcc1_supply>;
		...
	};
};

Similarly we have to add 7 more fixed regulators entries to provide input
supply to different PMIC regulators.

Am I doing correct thing? Or is there any better way to handle this?

Regards
AnilKumar


From shijie8 at gmail.com  Tue Aug 14 22:38:45 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Tue, 14 Aug 2012 22:38:45 -0400
Subject: [PATCH] mtd: kill MTD_NAND_VERIFY_WRITE
Message-ID: <1344998325-3279-1-git-send-email-shijie8@gmail.com>

Just as Artem suggested:

"Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature."

So kill MTD_NAND_VERIFY_WRITE entirely.

Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
 drivers/mtd/nand/Kconfig         |    9 -----
 drivers/mtd/nand/ams-delta.c     |   13 --------
 drivers/mtd/nand/au1550nd.c      |   46 ---------------------------
 drivers/mtd/nand/bcm_umi_nand.c  |   22 -------------
 drivers/mtd/nand/cafe_nand.c     |    7 ----
 drivers/mtd/nand/cmx270_nand.c   |   13 --------
 drivers/mtd/nand/diskonchip.c    |   63 --------------------------------------
 drivers/mtd/nand/fsl_elbc_nand.c |   36 ---------------------
 drivers/mtd/nand/fsl_ifc_nand.c  |   41 ------------------------
 drivers/mtd/nand/gpio.c          |   39 -----------------------
 drivers/mtd/nand/lpc32xx_slc.c   |   19 -----------
 drivers/mtd/nand/mpc5121_nfc.c   |   22 -------------
 drivers/mtd/nand/mxc_nand.c      |    9 -----
 drivers/mtd/nand/nand_base.c     |   53 --------------------------------
 drivers/mtd/nand/nandsim.c       |   16 ---------
 drivers/mtd/nand/ndfc.c          |   13 --------
 drivers/mtd/nand/nuc900_nand.c   |   17 ----------
 drivers/mtd/nand/omap2.c         |   23 --------------
 drivers/mtd/nand/pxa3xx_nand.c   |    7 ----
 drivers/mtd/nand/r852.c          |   22 -------------
 drivers/mtd/nand/sh_flctl.c      |   11 ------
 drivers/mtd/nand/socrates_nand.c |   19 -----------
 drivers/mtd/nand/tmio_nand.c     |   13 --------
 drivers/mtd/nand/txx9ndfmc.c     |   13 --------
 include/linux/mtd/nand.h         |    3 --
 25 files changed, 0 insertions(+), 549 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 588e989..0ca7257 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -22,15 +22,6 @@ menuconfig MTD_NAND
 
 if MTD_NAND
 
-config MTD_NAND_VERIFY_WRITE
-	bool "Verify NAND page writes"
-	help
-	  This adds an extra check when data is written to the flash. The
-	  NAND flash device internally checks only bits transitioning
-	  from 1 to 0. There is a rare possibility that even though the
-	  device thinks the write was successful, a bit could have been
-	  flipped accidentally due to device wear or something else.
-
 config MTD_NAND_BCH
 	tristate
 	select BCH
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 861ca8f..2d73f23 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -103,18 +103,6 @@ static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 		buf[i] = ams_delta_read_byte(mtd);
 }
 
-static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf,
-				int len)
-{
-	int i;
-
-	for (i=0; i<len; i++)
-		if (buf[i] != ams_delta_read_byte(mtd))
-			return -EFAULT;
-
-	return 0;
-}
-
 /*
  * Command control function
  *
@@ -233,7 +221,6 @@ static int __devinit ams_delta_init(struct platform_device *pdev)
 	this->read_byte = ams_delta_read_byte;
 	this->write_buf = ams_delta_write_buf;
 	this->read_buf = ams_delta_read_buf;
-	this->verify_buf = ams_delta_verify_buf;
 	this->cmd_ctrl = ams_delta_hwcontrol;
 	if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
 		this->dev_ready = ams_delta_nand_ready;
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 9f609d2..5c47b20 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -141,28 +141,6 @@ static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 }
 
 /**
- * au_verify_buf -  Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
- *
- * verify function for 8bit buswidth
- */
-static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-	struct nand_chip *this = mtd->priv;
-
-	for (i = 0; i < len; i++) {
-		if (buf[i] != readb(this->IO_ADDR_R))
-			return -EFAULT;
-		au_sync();
-	}
-
-	return 0;
-}
-
-/**
  * au_write_buf16 -  write buffer to chip
  * @mtd:	MTD device structure
  * @buf:	data buffer
@@ -205,29 +183,6 @@ static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 	}
 }
 
-/**
- * au_verify_buf16 -  Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
- *
- * verify function for 16bit buswidth
- */
-static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-	struct nand_chip *this = mtd->priv;
-	u16 *p = (u16 *) buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++) {
-		if (p[i] != readw(this->IO_ADDR_R))
-			return -EFAULT;
-		au_sync();
-	}
-	return 0;
-}
-
 /* Select the chip by setting nCE to low */
 #define NAND_CTL_SETNCE		1
 /* Deselect the chip by setting nCE to high */
@@ -516,7 +471,6 @@ static int __devinit au1550nd_probe(struct platform_device *pdev)
 	this->read_word = au_read_word;
 	this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
 	this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
-	this->verify_buf = (pd->devwidth) ? au_verify_buf16 : au_verify_buf;
 
 	ret = nand_scan(&ctx->info, 1);
 	if (ret) {
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index c855e7c..3fcbcbc 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -332,27 +332,6 @@ static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
 #endif
 }
 
-static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
-static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
-				   int len)
-{
-	/*
-	 * Try to readback page with ECC correction. This is necessary
-	 * for MLC parts which may have permanently stuck bits.
-	 */
-	struct nand_chip *chip = mtd->priv;
-	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
-	if (ret < 0)
-		return -EFAULT;
-	else {
-		if (memcmp(readbackbuf, buf, len) == 0)
-			return 0;
-
-		return -EFAULT;
-	}
-	return 0;
-}
-
 static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
 {
 	struct nand_chip *this;
@@ -416,7 +395,6 @@ static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
 
 	this->write_buf = bcm_umi_nand_write_buf;
 	this->read_buf = bcm_umi_nand_read_buf;
-	this->verify_buf = bcm_umi_nand_verify_buf;
 
 	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
 	this->ecc.mode = NAND_ECC_HW;
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index 08248a0..2bb7170 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -576,13 +576,6 @@ static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 		status = chip->waitfunc(mtd, chip);
 	}
 
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-	/* Send command to read back the data */
-	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
-	if (chip->verify_buf(mtd, buf, mtd->writesize))
-		return -EIO;
-#endif
 	return 0;
 }
 
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c
index 1024bfc..39b2ef8 100644
--- a/drivers/mtd/nand/cmx270_nand.c
+++ b/drivers/mtd/nand/cmx270_nand.c
@@ -76,18 +76,6 @@ static void cmx270_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 		*buf++ = readl(this->IO_ADDR_R) >> 16;
 }
 
-static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-	struct nand_chip *this = mtd->priv;
-
-	for (i=0; i<len; i++)
-		if (buf[i] != (u_char)(readl(this->IO_ADDR_R) >> 16))
-			return -EFAULT;
-
-	return 0;
-}
-
 static inline void nand_cs_on(void)
 {
 	gpio_set_value(GPIO_NAND_CS, 0);
@@ -209,7 +197,6 @@ static int __init cmx270_init(void)
 	this->read_byte = cmx270_read_byte;
 	this->read_buf = cmx270_read_buf;
 	this->write_buf = cmx270_write_buf;
-	this->verify_buf = cmx270_verify_buf;
 
 	/* Scan to find existence of the device */
 	if (nand_scan (cmx270_nand_mtd, 1)) {
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index e2ca067..256eb30 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -376,19 +376,6 @@ static void doc2000_readbuf_dword(struct mtd_info *mtd, u_char *buf, int len)
 	}
 }
 
-static int doc2000_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *this = mtd->priv;
-	struct doc_priv *doc = this->priv;
-	void __iomem *docptr = doc->virtadr;
-	int i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO))
-			return -EFAULT;
-	return 0;
-}
-
 static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
 {
 	struct nand_chip *this = mtd->priv;
@@ -526,26 +513,6 @@ static void doc2001_readbuf(struct mtd_info *mtd, u_char *buf, int len)
 	buf[i] = ReadDOC(docptr, LastDataRead);
 }
 
-static int doc2001_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *this = mtd->priv;
-	struct doc_priv *doc = this->priv;
-	void __iomem *docptr = doc->virtadr;
-	int i;
-
-	/* Start read pipeline */
-	ReadDOC(docptr, ReadPipeInit);
-
-	for (i = 0; i < len - 1; i++)
-		if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
-			ReadDOC(docptr, LastDataRead);
-			return i;
-		}
-	if (buf[i] != ReadDOC(docptr, LastDataRead))
-		return i;
-	return 0;
-}
-
 static u_char doc2001plus_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *this = mtd->priv;
@@ -610,33 +577,6 @@ static void doc2001plus_readbuf(struct mtd_info *mtd, u_char *buf, int len)
 		printk("\n");
 }
 
-static int doc2001plus_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *this = mtd->priv;
-	struct doc_priv *doc = this->priv;
-	void __iomem *docptr = doc->virtadr;
-	int i;
-
-	if (debug)
-		printk("verifybuf of %d bytes: ", len);
-
-	/* Start read pipeline */
-	ReadDOC(docptr, Mplus_ReadPipeInit);
-	ReadDOC(docptr, Mplus_ReadPipeInit);
-
-	for (i = 0; i < len - 2; i++)
-		if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
-			ReadDOC(docptr, Mplus_LastDataRead);
-			ReadDOC(docptr, Mplus_LastDataRead);
-			return i;
-		}
-	if (buf[len - 2] != ReadDOC(docptr, Mplus_LastDataRead))
-		return len - 2;
-	if (buf[len - 1] != ReadDOC(docptr, Mplus_LastDataRead))
-		return len - 1;
-	return 0;
-}
-
 static void doc2001plus_select_chip(struct mtd_info *mtd, int chip)
 {
 	struct nand_chip *this = mtd->priv;
@@ -1432,7 +1372,6 @@ static inline int __init doc2000_init(struct mtd_info *mtd)
 	this->read_byte = doc2000_read_byte;
 	this->write_buf = doc2000_writebuf;
 	this->read_buf = doc2000_readbuf;
-	this->verify_buf = doc2000_verifybuf;
 	this->scan_bbt = nftl_scan_bbt;
 
 	doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO;
@@ -1449,7 +1388,6 @@ static inline int __init doc2001_init(struct mtd_info *mtd)
 	this->read_byte = doc2001_read_byte;
 	this->write_buf = doc2001_writebuf;
 	this->read_buf = doc2001_readbuf;
-	this->verify_buf = doc2001_verifybuf;
 
 	ReadDOC(doc->virtadr, ChipID);
 	ReadDOC(doc->virtadr, ChipID);
@@ -1480,7 +1418,6 @@ static inline int __init doc2001plus_init(struct mtd_info *mtd)
 	this->read_byte = doc2001plus_read_byte;
 	this->write_buf = doc2001plus_writebuf;
 	this->read_buf = doc2001plus_readbuf;
-	this->verify_buf = doc2001plus_verifybuf;
 	this->scan_bbt = inftl_scan_bbt;
 	this->cmd_ctrl = NULL;
 	this->select_chip = doc2001plus_select_chip;
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 8143873..cc1480a 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -614,41 +614,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 		        len, avail);
 }
 
-/*
- * Verify buffer against the FCM Controller Data Buffer
- */
-static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
-	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
-	int i;
-
-	if (len < 0) {
-		dev_err(priv->dev, "write_buf of %d bytes", len);
-		return -EINVAL;
-	}
-
-	if ((unsigned int)len >
-			elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
-		dev_err(priv->dev,
-			"verify_buf beyond end of buffer "
-			"(%d requested, %u available)\n",
-			len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
-
-		elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
-		return -EINVAL;
-	}
-
-	for (i = 0; i < len; i++)
-		if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
-				!= buf[i])
-			break;
-
-	elbc_fcm_ctrl->index += len;
-	return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
-}
-
 /* This function is called after Program and Erase Operations to
  * check for success or failure.
  */
@@ -798,7 +763,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 	chip->read_byte = fsl_elbc_read_byte;
 	chip->write_buf = fsl_elbc_write_buf;
 	chip->read_buf = fsl_elbc_read_buf;
-	chip->verify_buf = fsl_elbc_verify_buf;
 	chip->select_chip = fsl_elbc_select_chip;
 	chip->cmdfunc = fsl_elbc_cmdfunc;
 	chip->waitfunc = fsl_elbc_wait;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 1f71b54..e92d223 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -627,46 +627,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 }
 
 /*
- * Verify buffer against the IFC Controller Data Buffer
- */
-static int fsl_ifc_verify_buf(struct mtd_info *mtd,
-			       const u_char *buf, int len)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
-	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
-	struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
-	int i;
-
-	if (len < 0) {
-		dev_err(priv->dev, "%s: write_buf of %d bytes", __func__, len);
-		return -EINVAL;
-	}
-
-	if ((unsigned int)len > nctrl->read_bytes - nctrl->index) {
-		dev_err(priv->dev,
-			"%s: beyond end of buffer (%d requested, %u available)\n",
-			__func__, len, nctrl->read_bytes - nctrl->index);
-
-		nctrl->index = nctrl->read_bytes;
-		return -EINVAL;
-	}
-
-	for (i = 0; i < len; i++)
-		if (in_8(&nctrl->addr[nctrl->index + i]) != buf[i])
-			break;
-
-	nctrl->index += len;
-
-	if (i != len)
-		return -EIO;
-	if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
-		return -EIO;
-
-	return 0;
-}
-
-/*
  * This function is called after Program and Erase Operations to
  * check for success or failure.
  */
@@ -796,7 +756,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 
 	chip->write_buf = fsl_ifc_write_buf;
 	chip->read_buf = fsl_ifc_read_buf;
-	chip->verify_buf = fsl_ifc_verify_buf;
 	chip->select_chip = fsl_ifc_select_chip;
 	chip->cmdfunc = fsl_ifc_cmdfunc;
 	chip->waitfunc = fsl_ifc_wait;
diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c
index 27000a5..ce6a284 100644
--- a/drivers/mtd/nand/gpio.c
+++ b/drivers/mtd/nand/gpio.c
@@ -100,23 +100,6 @@ static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len)
 	readsb(this->IO_ADDR_R, buf, len);
 }
 
-static int gpio_nand_verifybuf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct nand_chip *this = mtd->priv;
-	unsigned char read, *p = (unsigned char *) buf;
-	int i, err = 0;
-
-	for (i = 0; i < len; i++) {
-		read = readb(this->IO_ADDR_R);
-		if (read != p[i]) {
-			pr_debug("%s: err at %d (read %04x vs %04x)\n",
-			       __func__, i, read, p[i]);
-			err = -EFAULT;
-		}
-	}
-	return err;
-}
-
 static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf,
 				 int len)
 {
@@ -148,26 +131,6 @@ static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len)
 	}
 }
 
-static int gpio_nand_verifybuf16(struct mtd_info *mtd, const u_char *buf,
-				 int len)
-{
-	struct nand_chip *this = mtd->priv;
-	unsigned short read, *p = (unsigned short *) buf;
-	int i, err = 0;
-	len >>= 1;
-
-	for (i = 0; i < len; i++) {
-		read = readw(this->IO_ADDR_R);
-		if (read != p[i]) {
-			pr_debug("%s: err at %d (read %04x vs %04x)\n",
-			       __func__, i, read, p[i]);
-			err = -EFAULT;
-		}
-	}
-	return err;
-}
-
-
 static int gpio_nand_devready(struct mtd_info *mtd)
 {
 	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
@@ -391,11 +354,9 @@ static int __devinit gpio_nand_probe(struct platform_device *dev)
 	if (this->options & NAND_BUSWIDTH_16) {
 		this->read_buf   = gpio_nand_readbuf16;
 		this->write_buf  = gpio_nand_writebuf16;
-		this->verify_buf = gpio_nand_verifybuf16;
 	} else {
 		this->read_buf   = gpio_nand_readbuf;
 		this->write_buf  = gpio_nand_writebuf;
-		this->verify_buf = gpio_nand_verifybuf;
 	}
 
 	/* set the mtd private data for the nand driver */
diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c
index c8c1d06..6d7d3cb 100644
--- a/drivers/mtd/nand/lpc32xx_slc.c
+++ b/drivers/mtd/nand/lpc32xx_slc.c
@@ -368,24 +368,6 @@ static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int
 }
 
 /*
- * Verify data in buffer to data on device
- */
-static int lpc32xx_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct lpc32xx_nand_host *host = chip->priv;
-	int i;
-
-	/* DATA register must be read as 32 bits or it will fail */
-	for (i = 0; i < len; i++) {
-		if (buf[i] != (uint8_t)readl(SLC_DATA(host->io_base)))
-			return -EFAULT;
-	}
-
-	return 0;
-}
-
-/*
  * Read the OOB data from the device without ECC using FIFO method
  */
 static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
@@ -862,7 +844,6 @@ static int __devinit lpc32xx_nand_probe(struct platform_device *pdev)
 	chip->ecc.correct = nand_correct_data;
 	chip->ecc.strength = 1;
 	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
-	chip->verify_buf = lpc32xx_verify_buf;
 
 	/* bitflip_threshold's default is defined as ecc_strength anyway.
 	 * Unfortunately, it is set only later at add_mtd_device(). Meanwhile
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index c259c24..f776c85 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -506,27 +506,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
 	mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
 }
 
-/* Compare buffer with NAND flash */
-static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
-						const u_char *buf, int len)
-{
-	u_char tmp[256];
-	uint bsize;
-
-	while (len) {
-		bsize = min(len, 256);
-		mpc5121_nfc_read_buf(mtd, tmp, bsize);
-
-		if (memcmp(buf, tmp, bsize))
-			return 1;
-
-		buf += bsize;
-		len -= bsize;
-	}
-
-	return 0;
-}
-
 /* Read byte from NFC buffers */
 static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
 {
@@ -732,7 +711,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	chip->read_word = mpc5121_nfc_read_word;
 	chip->read_buf = mpc5121_nfc_read_buf;
 	chip->write_buf = mpc5121_nfc_write_buf;
-	chip->verify_buf = mpc5121_nfc_verify_buf;
 	chip->select_chip = mpc5121_nfc_select_chip;
 	chip->bbt_options = NAND_BBT_USE_FLASH;
 	chip->ecc.mode = NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 3f94e1f..bfee9eb 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -746,14 +746,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	host->buf_start += n;
 }
 
-/* Used by the upper layer to verify the data in NAND Flash
- * with the data in the buf. */
-static int mxc_nand_verify_buf(struct mtd_info *mtd,
-				const u_char *buf, int len)
-{
-	return -EFAULT;
-}
-
 /* This function is used by upper layer for select and
  * deselect of the NAND chip */
 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
@@ -1406,7 +1398,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	this->read_word = mxc_nand_read_word;
 	this->write_buf = mxc_nand_write_buf;
 	this->read_buf = mxc_nand_read_buf;
-	this->verify_buf = mxc_nand_verify_buf;
 
 	host->clk = devm_clk_get(&pdev->dev, "nfc");
 	if (IS_ERR(host->clk))
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ead301a..5a1689a 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -243,25 +243,6 @@ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 }
 
 /**
- * nand_verify_buf - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 8bit buswidth.
- */
-static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *chip = mtd->priv;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != readb(chip->IO_ADDR_R))
-			return -EFAULT;
-	return 0;
-}
-
-/**
  * nand_write_buf16 - [DEFAULT] write buffer to chip
  * @mtd: MTD device structure
  * @buf: data buffer
@@ -301,28 +282,6 @@ static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 }
 
 /**
- * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 16bit buswidth.
- */
-static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *chip = mtd->priv;
-	u16 *p = (u16 *) buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++)
-		if (p[i] != readw(chip->IO_ADDR_R))
-			return -EFAULT;
-
-	return 0;
-}
-
-/**
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  * @mtd: MTD device structure
  * @ofs: offset from device start
@@ -2120,16 +2079,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 		status = chip->waitfunc(mtd, chip);
 	}
 
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-	/* Send command to read back the data */
-	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
-	if (chip->verify_buf(mtd, buf, mtd->writesize))
-		return -EIO;
-
-	/* Make sure the next page prog is preceded by a status read */
-	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-#endif
 	return 0;
 }
 
@@ -2804,8 +2753,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
 		chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
 	if (!chip->read_buf)
 		chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
-	if (!chip->verify_buf)
-		chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
 	if (!chip->scan_bbt)
 		chip->scan_bbt = nand_default_bbt;
 
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index cf0cd31..21e64b5 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -447,8 +447,6 @@ static unsigned int rptwear_cnt = 0;
 /* MTD structure for NAND controller */
 static struct mtd_info *nsmtd;
 
-static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
-
 /*
  * Allocate array of page pointers, create slab allocation for an array
  * and initialize the array by NULL pointers.
@@ -2189,19 +2187,6 @@ static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	return;
 }
 
-static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
-
-	if (!memcmp(buf, &ns_verify_buf[0], len)) {
-		NS_DBG("verify_buf: the buffer is OK\n");
-		return 0;
-	} else {
-		NS_DBG("verify_buf: the buffer is wrong\n");
-		return -EFAULT;
-	}
-}
-
 /*
  * Module initialization function
  */
@@ -2236,7 +2221,6 @@ static int __init ns_init_module(void)
 	chip->dev_ready  = ns_device_ready;
 	chip->write_buf  = ns_nand_write_buf;
 	chip->read_buf   = ns_nand_read_buf;
-	chip->verify_buf = ns_nand_verify_buf;
 	chip->read_word  = ns_nand_read_word;
 	chip->ecc.mode   = NAND_ECC_SOFT;
 	/* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 2b6f632..5fd3f01 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -140,18 +140,6 @@ static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 		out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
 }
 
-static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct ndfc_controller *ndfc = chip->priv;
-	uint32_t *p = (uint32_t *) buf;
-
-	for(;len > 0; len -= 4)
-		if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
-			return -EFAULT;
-	return 0;
-}
-
 /*
  * Initialize chip structure
  */
@@ -172,7 +160,6 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
 	chip->controller = &ndfc->ndfc_control;
 	chip->read_buf = ndfc_read_buf;
 	chip->write_buf = ndfc_write_buf;
-	chip->verify_buf = ndfc_verify_buf;
 	chip->ecc.correct = nand_correct_data;
 	chip->ecc.hwctl = ndfc_enable_hwecc;
 	chip->ecc.calculate = ndfc_calculate_ecc;
diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c
index 8febe46..94dc46b 100644
--- a/drivers/mtd/nand/nuc900_nand.c
+++ b/drivers/mtd/nand/nuc900_nand.c
@@ -112,22 +112,6 @@ static void nuc900_nand_write_buf(struct mtd_info *mtd,
 		write_data_reg(nand, buf[i]);
 }
 
-static int nuc900_verify_buf(struct mtd_info *mtd,
-			     const unsigned char *buf, int len)
-{
-	int i;
-	struct nuc900_nand *nand;
-
-	nand = container_of(mtd, struct nuc900_nand, mtd);
-
-	for (i = 0; i < len; i++) {
-		if (buf[i] != (unsigned char)read_data_reg(nand))
-			return -EFAULT;
-	}
-
-	return 0;
-}
-
 static int nuc900_check_rb(struct nuc900_nand *nand)
 {
 	unsigned int val;
@@ -292,7 +276,6 @@ static int __devinit nuc900_nand_probe(struct platform_device *pdev)
 	chip->read_byte		= nuc900_nand_read_byte;
 	chip->write_buf		= nuc900_nand_write_buf;
 	chip->read_buf		= nuc900_nand_read_buf;
-	chip->verify_buf	= nuc900_verify_buf;
 	chip->chip_delay	= 50;
 	chip->options		= 0;
 	chip->ecc.mode		= NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index ac4fd75..1c46300 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -614,27 +614,6 @@ out_copy:
 }
 
 /**
- * omap_verify_buf - Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- */
-static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
-{
-	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-							mtd);
-	u16 *p = (u16 *) buf;
-
-	len >>= 1;
-	while (len--) {
-		if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
-			return -EFAULT;
-	}
-
-	return 0;
-}
-
-/**
  * gen_true_ecc - This function will generate true ECC value
  * @ecc_buf: buffer to store ecc code
  *
@@ -1285,8 +1264,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 		goto out_release_mem_region;
 	}
 
-	info->nand.verify_buf = omap_verify_buf;
-
 	/* selsect the ecc type */
 	if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
 		info->nand.ecc.mode = NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e8a1ae9..5df91d5 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -771,12 +771,6 @@ static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 	info->buf_start += real_len;
 }
 
-static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
-		const uint8_t *buf, int len)
-{
-	return 0;
-}
-
 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 {
 	return;
@@ -1069,7 +1063,6 @@ static int alloc_nand_resource(struct platform_device *pdev)
 		chip->read_byte		= pxa3xx_nand_read_byte;
 		chip->read_buf		= pxa3xx_nand_read_buf;
 		chip->write_buf		= pxa3xx_nand_write_buf;
-		chip->verify_buf	= pxa3xx_nand_verify_buf;
 	}
 
 	spin_lock_init(&chip->controller->lock);
diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c
index 8cb6277..4495f85 100644
--- a/drivers/mtd/nand/r852.c
+++ b/drivers/mtd/nand/r852.c
@@ -309,27 +309,6 @@ static uint8_t r852_read_byte(struct mtd_info *mtd)
 	return r852_read_reg(dev, R852_DATALINE);
 }
 
-
-/*
- * Readback the buffer to verify it
- */
-int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	struct r852_device *dev = r852_get_dev(mtd);
-
-	/* We can't be sure about anything here... */
-	if (dev->card_unstable)
-		return -1;
-
-	/* This will never happen, unless you wired up a nand chip
-		with > 512 bytes page size to the reader */
-	if (len > SM_SECTOR_SIZE)
-		return 0;
-
-	r852_read_buf(mtd, dev->tmp_buffer, len);
-	return memcmp(buf, dev->tmp_buffer, len);
-}
-
 /*
  * Control several chip lines & send commands
  */
@@ -882,7 +861,6 @@ int  r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
 	chip->read_byte = r852_read_byte;
 	chip->read_buf = r852_read_buf;
 	chip->write_buf = r852_write_buf;
-	chip->verify_buf = r852_verify_buf;
 
 	/* ecc */
 	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 0b798fb..319ffb4 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -788,16 +788,6 @@ static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 	flctl->index += len;
 }
 
-static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		if (buf[i] != flctl_read_byte(mtd))
-			return -EFAULT;
-	return 0;
-}
-
 static int flctl_chip_init_tail(struct mtd_info *mtd)
 {
 	struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -931,7 +921,6 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	nand->read_byte = flctl_read_byte;
 	nand->write_buf = flctl_write_buf;
 	nand->read_buf = flctl_read_buf;
-	nand->verify_buf = flctl_verify_buf;
 	nand->select_chip = flctl_select_chip;
 	nand->cmdfunc = flctl_cmdfunc;
 
diff --git a/drivers/mtd/nand/socrates_nand.c b/drivers/mtd/nand/socrates_nand.c
index e02b08b..f3f28fa 100644
--- a/drivers/mtd/nand/socrates_nand.c
+++ b/drivers/mtd/nand/socrates_nand.c
@@ -98,24 +98,6 @@ static uint16_t socrates_nand_read_word(struct mtd_info *mtd)
 	return word;
 }
 
-/**
- * socrates_nand_verify_buf -  Verify chip data against buffer
- * @mtd:	MTD device structure
- * @buf:	buffer containing the data to compare
- * @len:	number of bytes to compare
- */
-static int socrates_nand_verify_buf(struct mtd_info *mtd, const u8 *buf,
-		int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		if (buf[i] != socrates_nand_read_byte(mtd))
-			return -EFAULT;
-	}
-	return 0;
-}
-
 /*
  * Hardware specific access to control-lines
  */
@@ -201,7 +183,6 @@ static int __devinit socrates_nand_probe(struct platform_device *ofdev)
 	nand_chip->read_word = socrates_nand_read_word;
 	nand_chip->write_buf = socrates_nand_write_buf;
 	nand_chip->read_buf = socrates_nand_read_buf;
-	nand_chip->verify_buf = socrates_nand_verify_buf;
 	nand_chip->dev_ready = socrates_nand_device_ready;
 
 	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
diff --git a/drivers/mtd/nand/tmio_nand.c b/drivers/mtd/nand/tmio_nand.c
index 5aa5180..508e9e0 100644
--- a/drivers/mtd/nand/tmio_nand.c
+++ b/drivers/mtd/nand/tmio_nand.c
@@ -256,18 +256,6 @@ static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
 }
 
-static int
-tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	struct tmio_nand *tmio = mtd_to_tmio(mtd);
-	u16				*p = (u16 *) buf;
-
-	for (len >>= 1; len; len--)
-		if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA))
-			return -EFAULT;
-	return 0;
-}
-
 static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct tmio_nand *tmio = mtd_to_tmio(mtd);
@@ -424,7 +412,6 @@ static int tmio_probe(struct platform_device *dev)
 	nand_chip->read_byte = tmio_nand_read_byte;
 	nand_chip->write_buf = tmio_nand_write_buf;
 	nand_chip->read_buf = tmio_nand_read_buf;
-	nand_chip->verify_buf = tmio_nand_verify_buf;
 
 	/* set eccmode using hardware ECC */
 	nand_chip->ecc.mode = NAND_ECC_HW;
diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c
index 26398dc..e3d7266 100644
--- a/drivers/mtd/nand/txx9ndfmc.c
+++ b/drivers/mtd/nand/txx9ndfmc.c
@@ -131,18 +131,6 @@ static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 		*buf++ = __raw_readl(ndfdtr);
 }
 
-static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
-				int len)
-{
-	struct platform_device *dev = mtd_to_platdev(mtd);
-	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
-
-	while (len--)
-		if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
-			return -EFAULT;
-	return 0;
-}
-
 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 			       unsigned int ctrl)
 {
@@ -346,7 +334,6 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
 		chip->read_byte = txx9ndfmc_read_byte;
 		chip->read_buf = txx9ndfmc_read_buf;
 		chip->write_buf = txx9ndfmc_write_buf;
-		chip->verify_buf = txx9ndfmc_verify_buf;
 		chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
 		chip->dev_ready = txx9ndfmc_dev_ready;
 		chip->ecc.calculate = txx9ndfmc_calculate_ecc;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 6dce5a7..9be3873 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -397,8 +397,6 @@ struct nand_buffers {
  * @read_word:		[REPLACEABLE] read one word from the chip
  * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
  * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
- * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip
- *			data.
  * @select_chip:	[REPLACEABLE] select chip nr
  * @block_bad:		[REPLACEABLE] check, if the block is bad
  * @block_markbad:	[REPLACEABLE] mark the block bad
@@ -481,7 +479,6 @@ struct nand_chip {
 	u16 (*read_word)(struct mtd_info *mtd);
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
-	int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
 	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
-- 
1.7.4.4



From nicolas.ferre at atmel.com  Tue Aug 14 10:47:05 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 Aug 2012 16:47:05 +0200
Subject: [PATCH 13/23] AT91 DMA OF support
In-Reply-To: <1344952177-18385-14-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
 <1344952177-18385-14-git-send-email-richard.genoud@gmail.com>
Message-ID: <502A64E9.2050706@atmel.com>

Hi Richard,

I am not sure that this one will go further: there is an initiative to
build a pretty generic DMA OF support... It takes time but it is
progressing...

Anyway, there may have some bits to integrate in at_hdmac.c driver: I
will have a closer look later.

Thanks,

On 08/14/2012 03:49 PM, Richard Genoud :
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
> ---
>  arch/arm/mach-at91/include/mach/at_hdmac.h |    1 +
>  drivers/of/Kconfig                         |    4 +
>  drivers/of/Makefile                        |    1 +
>  drivers/of/of_atmel.c                      |  112 ++++++++++++++++++++++++++++
>  include/linux/of_atmel.h                   |   29 +++++++
>  5 files changed, 147 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/of/of_atmel.c
>  create mode 100644 include/linux/of_atmel.h
> 
> diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
> index cab0997..35667bd 100644
> --- a/arch/arm/mach-at91/include/mach/at_hdmac.h
> +++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
> @@ -52,6 +52,7 @@ struct at_dma_slave {
>  #define		ATC_LOCK_IF_L_CHUNK	(0x0 << 22)
>  #define		ATC_LOCK_IF_L_BUFFER	(0x1 << 22)
>  #define	ATC_AHB_PROT_MASK	(0x7 << 24)	/* AHB Protection */
> +#define	ATC_AHB_PROT(h)		(((h) <<  24) && ATC_AHB_PROT_MASK)
>  #define	ATC_FIFOCFG_MASK	(0x3 << 28)	/* FIFO Request Configuration */
>  #define		ATC_FIFOCFG_LARGESTBURST	(0x0 << 28)
>  #define		ATC_FIFOCFG_HALFFIFO		(0x1 << 28)
> diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> index dfba3e6..4667960 100644
> --- a/drivers/of/Kconfig
> +++ b/drivers/of/Kconfig
> @@ -83,4 +83,8 @@ config OF_MTD
>  	depends on MTD
>  	def_bool y
>  
> +config OF_ATMEL
> +	depends on AT_HDMAC
> +	def_bool y
> +
>  endmenu # OF
> diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> index e027f44..897de3b 100644
> --- a/drivers/of/Makefile
> +++ b/drivers/of/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
>  obj-$(CONFIG_OF_PCI)	+= of_pci.o
>  obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
>  obj-$(CONFIG_OF_MTD)	+= of_mtd.o
> +obj-$(CONFIG_OF_ATMEL)	+= of_atmel.o
> diff --git a/drivers/of/of_atmel.c b/drivers/of/of_atmel.c
> new file mode 100644
> index 0000000..bcd3c54a
> --- /dev/null
> +++ b/drivers/of/of_atmel.c
> @@ -0,0 +1,112 @@
> +/*
> + * Copyright (C) 2012 Richard Genoud, Paratronic S.A.
> + *                    <richard.genoud at gmail.com>
> + *
> + * Atmel specifics OF helpers
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +#include <linux/kernel.h>
> +#include <linux/export.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/printk.h>
> +#include <linux/byteorder/generic.h>
> +#include <mach/at_hdmac.h>
> +#include <linux/of.h>
> +
> +static int of_dev_node_match(struct device *dev, void *data)
> +{
> +	return dev->of_node == data;
> +}
> +
> +/**
> + * of_create_at_dma_slave - Alloc and initialize the struct at_dma_slave
> + * @np: pointer to node to create the struct for
> + * @bus: pointer to the bus type of the DMA device.
> + *
> + * Returns pointer to created DMA slave structure, or NULL in case of error.
> + */
> +struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
> +					    struct bus_type *bus)
> +{
> +	struct at_dma_slave *atslave;
> +	struct device_node *n;
> +	struct property *prop;
> +	const __be32 *dma_list;
> +	phandle phandle;
> +	int size;
> +	int err = -1;
> +	u32 val;
> +
> +	atslave = kzalloc(sizeof(struct at_dma_slave), GFP_KERNEL);
> +	if (unlikely(!atslave)) {
> +		pr_err("cannot allocate memory\n");
> +		goto error;
> +	}
> +
> +	atslave->cfg |= of_property_read_bool(np, "atc_src_rep") ? ATC_SRC_REP : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_dst_rep") ? ATC_DST_REP : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_src_h2sel_hw") ? ATC_SRC_H2SEL_HW : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_dst_h2sel_hw") ? ATC_DST_H2SEL_HW : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_sod") ? ATC_SOD : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_lock_if") ? ATC_LOCK_IF : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_lock_b") ? ATC_LOCK_B : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l") ? ATC_LOCK_IF_L : 0;
> +	atslave->cfg |= of_property_read_bool(np, "atc_lock_if_l_buffer") ? ATC_LOCK_IF_L_BUFFER : 0;
> +	if (of_property_read_bool(np, "atc_fifocfg_halffifo"))
> +		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_HALFFIFO;
> +	if (of_property_read_bool(np, "atc_fifocfg_enoughspace"))
> +		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_ENOUGHSPACE;
> +	if (of_property_read_bool(np, "atc_fifocfg_largestburst"))
> +		atslave->cfg = (atslave->cfg & ~ATC_FIFOCFG_MASK) | ATC_FIFOCFG_LARGESTBURST;
> +	if (!of_property_read_u32(np, "atc_ahb_prot", &val))
> +		atslave->cfg |= ATC_AHB_PROT(val);
> +	if (!of_property_read_u32(np, "atc_src_per", &val))
> +		atslave->cfg |= ATC_SRC_PER(val);
> +	if (!of_property_read_u32(np, "atc_dst_per", &val))
> +		atslave->cfg |= ATC_DST_PER(val);
> +
> +	/* we need to associate the wanted dma struct device to
> +	 * atslave->dma_dev. This is needed when searching for
> +	 * a free dma channel
> +	 */
> +	prop = of_find_property(np, "dma", &size);
> +	if (!prop) {
> +		pr_err("can't find the dma child node\n");
> +		goto error;
> +	}
> +	dma_list = prop->value;
> +	size /= sizeof(*dma_list);
> +	if (size != 1) {
> +		pr_err("only one dma handle is supported\n");
> +		goto error;
> +	}
> +
> +	phandle = be32_to_cpup(dma_list);
> +	n = of_find_node_by_phandle(phandle);
> +	if (!n) {
> +		pr_err("unable to find dma device: invalid phandle %s\n",
> +		       prop->name);
> +		goto error;
> +	}
> +
> +	atslave->dma_dev = bus_find_device(bus, NULL, n, of_dev_node_match);
> +	if (!atslave->dma_dev) {
> +		pr_err("can't find struct device for DMA %s\n", prop->name);
> +		goto error;
> +	}
> +
> +	pr_debug("DMA cfg register=0x%x DMA device path=%s\n",
> +		 atslave->cfg, prop->name);
> +	err = 0;
> +error:
> +	if (err)
> +		kfree(atslave);
> +	return atslave;
> +}
> +EXPORT_SYMBOL_GPL(of_create_at_dma_slave);
> +
> diff --git a/include/linux/of_atmel.h b/include/linux/of_atmel.h
> new file mode 100644
> index 0000000..256f336
> --- /dev/null
> +++ b/include/linux/of_atmel.h
> @@ -0,0 +1,29 @@
> +#ifndef _LINUX_OF_ATMEL_H
> +#define _LINUX_OF_ATMEL_H
> +/*
> + * Copyright (C) 2012 Richard Genoud, Paratronic S.A.
> + *                    <richard.genoud at gmail.com>
> + *
> + * Atmel specifics OF helpers
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +#include <linux/of.h>
> +#include <linux/device.h>
> +#include <mach/at_hdmac.h>
> +
> +#ifdef CONFIG_OF_ATMEL
> +extern struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
> +						   struct bus_type *bus);
> +#else
> +static struct at_dma_slave *of_create_at_dma_slave(struct device_node *np,
> +						   struct bus_type *bus)
> +{
> +	return NULL;
> +}
> +#endif /* CONFIG_OF_ATMEL */
> +
> +#endif	/* _LINUX_OF_ATMEL_H */
> 


-- 
Nicolas Ferre


From will.deacon at arm.com  Tue Aug 14 10:59:26 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 14 Aug 2012 15:59:26 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_ accessors
Message-ID: <1344956366-32574-1-git-send-email-will.deacon@arm.com>

Data aborts taken to hyp mode do not provide a valid instruction
syndrome field in the HSR if the faulting instruction is a memory
access using a writeback addressing mode.

For hypervisors emulating MMIO accesses to virtual peripherals, taking
such an exception requires disassembling the faulting instruction in
order to determine the behaviour of the access. Since this requires
manually walking the two stages of translation, the world must be
stopped to prevent races against page aging in the guest, where the
first-stage translation is invalidated after the hypervisor has
translated to an IPA and the physical page is reused for something else.

This patch avoids taking this heavy performance penalty when running
Linux as a guest by ensuring that our I/O accessors do not make use of
writeback addressing modes.

Tested-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/io.h |   55 ++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669..b54d687 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,56 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v)))
-#define __raw_writew(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
-#define __raw_writel(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v)))
+#if __LINUX_ARM_ARCH__ < 6
+/*
+ * Half-word accesses are problematic with RiscPC due to limitations of
+ * the bus. Rather than special-case the machine, just let the compiler
+ * generate the access for CPUs prior to ARMv6.
+ */
+#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#else
+/*
+ * When running under a hypervisor, we want to avoid I/O accesses with
+ * writeback addressing modes as these incur a significant performance
+ * overhead (the address generation must be emulated in software).
+ */
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+	asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 val;
+	asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+#endif
 
-#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
-#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
-#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+	asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+	asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 val;
+	asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 val;
+	asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
 
 /*
  * Architecture ioremap implementation.
-- 
1.7.4.1



From nicolas.ferre at atmel.com  Tue Aug 14 11:29:48 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 Aug 2012 17:29:48 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
In-Reply-To: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <502A6EEC.2010807@atmel.com>

On 08/14/2012 03:49 PM, Richard Genoud :
> Nicolas,
> I said that I had some work done on sam9g35-ek, here is the spi part, based
> on your and Jean-Christophe work.
> You have to enable CONFIG_ARCH_AT91SAM9X5 to get it work.
> 
> The goal of this patchset is to share the work I've done, it's not ready
> for upstream, but it may save some time.
> 
> It's based on 3.6-rc1 + Jean-Christophe's pinctrl patchset.
> 
> Best Regards,

Richard,

Thanks a lot for updating this material: We really appreciate.

We will try to review this material together with Jean-Christophe and
colleagues @ Atmel. I hope that we will go forward with this collected
material in the near future.

Maybe DMA OF part will not be upstreamed as-is because of an ongoing
initiative to build a generic dmaengine OF support.

> Jean-Christophe PLAGNIOL-VILLARD (3):
>   of: add dma-mask binding
>   of_spi: add generic binding support to specify cs gpio

I know that Jean-Christophe has had difficulties to have feedback on
there parts...

>   spi/atmel: add DT support
> 
> Nicolas Ferre (6):
>   spi/atmel_spi: trivial: change some comments
>   spi/atmel_spi: add physical base address
>   spi/atmel_spi: call unmapping on transfers buffers
>   spi/atmel_spi: status information passed through controller data
>   spi/atmel_spi: add flag to controller data for lock operations
>   spi/atmel_spi: add dmaengine support
> 
> Richard Genoud (14):
>   spi-atmel: update with dmaengine interface

This will certainly be squashed in previous path.

>   spi-atmel: fix __init/__devinit sections mismatch

This one also: but it is good to have them separated at fist.

>   spi-atmel: Fix spi-atmel driver to adapt to slave_config changes
>   AT91 DMA OF support
>   add at91sam9x5 Kconfig ARCH/SOC link

Is it fixup for a bug? Jean-Christophe, a though about this one?

>   spi-atmel: add DMA OF support
>   [BUG] SPI: array out of bound => no CS
>   [BUG] atmel-spi && DMA: OOPS if buffer > 4400 bytes
>   sam9x5: declare SPI clocks
>   spi-atmel: add sam9x5 SPI in device tree
>   spi-atmel: add dma support in sam9x5 device tree
>   spi-atmel OF: complete documentation

Maybe documentation has to be folded in the patch that actually adds the
OF support.

>   spi-atmel: complete DMA slave OF documentation
>   sam9x5ek DTS: enable SPI dataflash
> 
>  Documentation/devicetree/bindings/spi/spi-bus.txt  |    6 +
>  .../devicetree/bindings/spi/spi_atmel.txt          |   46 ++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |   42 ++
>  arch/arm/boot/dts/at91sam9x5ek.dtsi                |   10 +
>  arch/arm/mach-at91/Kconfig                         |    4 +
>  arch/arm/mach-at91/at91sam9x5.c                    |    3 +
>  arch/arm/mach-at91/include/mach/at_hdmac.h         |    1 +
>  drivers/of/Kconfig                                 |    4 +
>  drivers/of/Makefile                                |    1 +
>  drivers/of/of_atmel.c                              |  111 ++++
>  drivers/of/platform.c                              |   23 +-
>  drivers/spi/Kconfig                                |    9 +
>  drivers/spi/spi-atmel.c                            |  611 ++++++++++++++++++--
>  drivers/spi/spi.c                                  |   55 ++-
>  include/linux/of_atmel.h                           |   29 +
>  include/linux/spi/spi.h                            |    3 +
>  16 files changed, 914 insertions(+), 44 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
>  create mode 100644 drivers/of/of_atmel.c
>  create mode 100644 include/linux/of_atmel.h
> 


-- 
Nicolas Ferre


From will.deacon at arm.com  Tue Aug 14 12:11:57 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 14 Aug 2012 17:11:57 +0100
Subject: [PATCH] ARM: support syscall tracing
In-Reply-To: <5029336B.2050305@mentor.com>
References: <5029336B.2050305@mentor.com>
Message-ID: <20120814161157.GJ26070@mudshark.cambridge.arm.com>

Hi Wade,

Thanks for the new patch. A few comments inline.

On Mon, Aug 13, 2012 at 06:03:39PM +0100, Wade Farnsworth wrote:
> diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
> index af7b0bd..d3e4410 100644
> --- a/arch/arm/include/asm/thread_info.h
> +++ b/arch/arm/include/asm/thread_info.h
> @@ -154,6 +154,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
>  #define TIF_RESTORE_SIGMASK	20
>  #define TIF_SECCOMP		21
>  #define TIF_SWITCH_MM		22	/* deferred switch_mm */
> +#define TIF_SYSCALL_TRACEPOINT	23
>  
>  #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
>  #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
> @@ -163,6 +164,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
>  #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
>  #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
>  #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
> +#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)

Can you add this to the definition of _TIF_SYSCALL_WORK as well please?

> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> index 978eac5..51b64c1 100644
> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
>  	.equ NR_syscalls,0
>  #define CALL(x) .equ NR_syscalls,NR_syscalls+1
>  #include "calls.S"
> +
> +/*
> + * Ensure that the system call table is equal to __NR_syscalls,
> + * which is the value the rest of the system sees
> + */
> +.ifne NR_syscalls - __NR_syscalls
> +.error "__NR_syscalls is not equal to the size of the syscall table"
> +.endif
> +
>  #undef CALL
>  #define CALL(x) .long x
>  
> @@ -415,7 +424,8 @@ local_restart:
>  1:
>  #endif
>  
> -	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
> +	tst     r10, #_TIF_SYSCALL_WORK
> +	tsteq   r10, #_TIF_SYSCALL_TRACEPOINT
>  	bne	__sys_trace

Then we don't need this hunk.

> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
> index 3e0fc5f..a2d46ed 100644
> --- a/arch/arm/kernel/ptrace.c
> +++ b/arch/arm/kernel/ptrace.c
> @@ -30,6 +30,9 @@
>  #include <asm/pgtable.h>
>  #include <asm/traps.h>
>  
> +#define CREATE_TRACE_POINTS
> +#include <trace/events/syscalls.h>
> +
>  #define REG_PC	15
>  #define REG_PSR	16
>  /*
> @@ -918,7 +921,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  {
>  	unsigned long ip;
>  
> -	if (!test_thread_flag(TIF_SYSCALL_TRACE))
> +	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
> +	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
>  		return scno;
>  
>  	current_thread_info()->syscall = scno;
> @@ -930,10 +934,19 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  	ip = regs->ARM_ip;
>  	regs->ARM_ip = dir;
>  
> -	if (dir == PTRACE_SYSCALL_EXIT)
> -		tracehook_report_syscall_exit(regs, 0);
> -	else if (tracehook_report_syscall_entry(regs))
> -		current_thread_info()->syscall = -1;
> +	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
> +		if (dir == PTRACE_SYSCALL_EXIT)
> +			tracehook_report_syscall_exit(regs, 0);
> +		else if (tracehook_report_syscall_entry(regs))
> +			current_thread_info()->syscall = -1;
> +	}
> +
> +	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) {
> +		if (dir == PTRACE_SYSCALL_EXIT)
> +			trace_sys_exit(regs, scno);
> +		else
> +			trace_sys_enter(regs, scno);
> +	}

I reckon the TRACEPOINT stuff would be better off inside the
syscall_trace_{enter,exit} functions. They don't modify the syscall number,
so they can just use the return value from ptrace_syscall_trace before the
audit hook invoked.

Will


From sourav.poddar at ti.com  Tue Aug 14 12:23:32 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:53:32 +0530
Subject: [PATCH] Documentation: dt: hwmon: Update for tmp102
Message-ID: <1344961412-13622-1-git-send-email-sourav.poddar@ti.com>

Add Documentation for tmp102 temperature sensor.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 Documentation/devicetree/bindings/hwmon/tmp102.txt |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/hwmon/tmp102.txt

diff --git a/Documentation/devicetree/bindings/hwmon/tmp102.txt b/Documentation/devicetree/bindings/hwmon/tmp102.txt
new file mode 100644
index 0000000..df1342b
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/tmp102.txt
@@ -0,0 +1,11 @@
+TMP102 Temperature sensor
+
+Required properties:
+- compatible: ti,tmp102
+
+Example:
+
+tmp102 at 48 {
+        compatible = "ti,tmp102";
+        reg = <0x48>;
+};
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 14 12:24:29 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:54:29 +0530
Subject: [PATCHv3 0/4] Add device tree data for omap5
Message-ID: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>

The following patch series add i2c support for omap5.
As well as enable I2C based devices like pressure and temperature
through device tree. Also add onchip keypad dts data.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>

Sourav Poddar (4):
  arm/dts: omap5-evm: Add I2C support
  arm/dts: omap5-evm: Add tmp102 sensor support
  arm/dts: omap5-evm: Add keypad data
  arm/dts: omap5-evm: Add bmp085 sensor support

v2->v3
- Rebased on 3.6-rc1
- Add comments for tmp102 and bmp085
 arch/arm/boot/dts/omap5-evm.dts |   32 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 0 deletions(-)



From sourav.poddar at ti.com  Tue Aug 14 12:24:30 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:54:30 +0530
Subject: [PATCHv3 1/4] arm/dts: omap5-evm: Add I2C support
In-Reply-To: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344961473-13675-2-git-send-email-sourav.poddar@ti.com>

Add I2C data node in omap5 device tree file.

Tested on omap5430 evm.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..6b68dfe 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -145,6 +145,41 @@
 			#interrupt-cells = <1>;
 		};
 
+		i2c1: i2c at 48070000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c1";
+		};
+
+		i2c2: i2c at 48072000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c2";
+		};
+
+		i2c3: i2c at 48060000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c3";
+		};
+
+		i2c4: i2c at 4807A000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c4";
+		};
+
+		i2c5: i2c at 4807C000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c5";
+		};
+
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			ti,hwmods = "uart1";
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 14 12:24:31 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:54:31 +0530
Subject: [PATCHv3 2/4] arm/dts: omap5-evm: Add tmp102 sensor support
In-Reply-To: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344961473-13675-3-git-send-email-sourav.poddar@ti.com>

Add tmp102 temperature sensor data in omap5 evm dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39a..b302802 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -18,3 +18,13 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 };
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	/* Temperature Sensor */
+	tmp102 at 48{
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 14 12:24:33 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:54:33 +0530
Subject: [PATCHv3 4/4] arm/dts: omap5-evm: Add bmp085 sensor support
In-Reply-To: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344961473-13675-5-git-send-email-sourav.poddar@ti.com>

Add bmp085 pressure sensor data in omap5 evm dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 8835026..378ccc2 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -40,3 +40,13 @@
 		reg = <0x48>;
 	};
 };
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	/* Pressure Sensor */
+	bmp085 at 77 {
+		compatible = "bosch,bmp085";
+		reg = <0x77>;
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 14 12:24:32 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 14 Aug 2012 21:54:32 +0530
Subject: [PATCHv3 3/4] arm/dts: omap5-evm: Add keypad data
In-Reply-To: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1344961473-13675-4-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap5 device tree file.
Also fill the device tree binding parameters
with the required value in "omap5-evm" dts file.

Tested on omap5430 evm with 3.5 custom kernel.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   12 ++++++++++++
 arch/arm/boot/dts/omap5.dtsi    |    5 +++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index b302802..8835026 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,6 +17,18 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	keypad {
+		keypad,num-rows = <8>;
+		keypad,num-columns = <8>;
+		linux,keymap = < 0x02020073  /* VOLUP */
+			0x02030072  /* VOLDOWM */
+			0x020400e7  /* SEND */
+			0x02050066  /* HOME */
+			0x0206006b  /* END */
+			0x020700d9 >; /* SEARCH */
+		linux,input-no-autorepeat;
+	};
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6b68dfe..c38b823 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -216,4 +216,9 @@
 			clock-frequency = <48000000>;
 		};
 	};
+
+	keypad {
+		compatible = "ti,omap4-keypad";
+		ti,hwmods = "kbd";
+	};
 };
-- 
1.7.1



From jdzheng at broadcom.com  Tue Aug 14 12:53:54 2012
From: jdzheng at broadcom.com (Jiandong Zheng)
Date: Tue, 14 Aug 2012 09:53:54 -0700
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <502A0FA0.3010602@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
 <50297838.7080208@broadcom.com> <502A0FA0.3010602@arm.com>
Message-ID: <502A82A2.9090307@broadcom.com>

On 8/14/2012 1:43 AM, Sudeep KarkadaNagesha wrote:
> Hi Jiandong,
>
> On 13/08/12 22:57, Jiandong Zheng wrote:
>> On 8/10/2012 10:36 AM, Will Deacon wrote:
>>> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
>>>    static struct platform_device pmu_device = {
>>>        .name        = "arm-pmu",
>>> -    .id        = ARM_PMU_DEVICE_CPU,
>>> +    .id        = -1,
>>>        .resource    = &pmu_resource,
>>>        .num_resources    = 1,
>>>    };
>>>
>> Isn't it clearer to define a meaningful name for "-1", esp. if "-1" is
>> being checked somewhere else?
>
> No platform_device->id is not being referred anywhere. 
> ARM_PMU_DEVICE_CPU was initially assigned to id to identify different 
> PMU types through platform_device->id variable but was never used.
>
> Also for all new platforms that might support multiple PMUs, we can 
> use device tree to identify them.
>
Seems it is just a field not in use. Even though I still prefer 
something like "ARM_PMU_DEFAULT_ID" to "-1", I am OK with "-1" as well.

Acked-by: Jiandong Zheng <jdzheng at broadcom.com>

Thanks,
JD



From bhelgaas at google.com  Tue Aug 14 13:38:08 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 14 Aug 2012 10:38:08 -0700
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>

On Mon, Aug 13, 2012 at 10:55 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Mon, Aug 13, 2012 at 10:00:45PM -0700, Bjorn Helgaas wrote:
>> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>> > This commit adds a new flag that allows marking resources as PCI
>> > configuration space.
>> >
>> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>> > ---
>> > Changes in v3:
>> > - new patch
>> >
>> >  include/linux/ioport.h | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/include/linux/ioport.h b/include/linux/ioport.h
>> > index 589e0e7..3314843 100644
>> > --- a/include/linux/ioport.h
>> > +++ b/include/linux/ioport.h
>> > @@ -102,7 +102,7 @@ struct resource {
>> >
>> >  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
>> >  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
>> > -
>> > +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */
>>
>> What is the purpose of this?  It seems that you are marking regions
>> that we call MMCONFIG on x86, or ECAM-type regions in the language of
>> the PCIe spec.  I see that you set it in several places, but I don't
>> see anything that ever looks for it.  Do you have plans to use it in
>> the future?  If it really does correspond to MMCONFIG/ECAM, we should
>> handle those regions consistently across all architectures.
>
> The purpose is ultimately to obtain the MMCONFIG/ECAM resources assigned
> to a PCI host controller. I've used this in the of_pci_parse_ranges()
> and in the static board setup code to mark ranges as such. Perhaps
> IORESOURCE_ECAM or IORESOURCE_MMCONFIG might have been better names. I
> also just noticed that I'm not using this anywhere, but the plan was to
> eventually use it with platform_get_resource(). However that doesn't
> seem to work either because the lower bits of the flags aren't use for
> comparison in that function.
>
> Any other ideas how that could be handled? Basically what I need is a
> way to mark a resource as an MMCONFIG/ECAM range so that it can be used
> to program the PCI host controller accordingly. I don't know how these
> are assigned on x86. I was under the impression that the MMCONFIG/ECAM
> space was accessed through a single single address/data register pair.

The legacy config access mechanism (CF8h/CFCh registers described in
PCI 3.0 spec sec 3.2.2.3.2) is a single address/data pair, but this is
mostly x86-specific.  The ECAM mechanism (described in the PCIe 3.0
spec sec 7.2.2) is not a single address/data pair; instead, each byte
of config space is directly mapped into the host's MMIO space.

Here's what we do on x86 (omitting some historical grunge that
complicates things):

  - Discover the host bridge via a PNP0A08 device in the ACPI namespace.
  - Discover the bus number range behind the bridge using a _CRS
method in the PNP0A08 device.
  - Discover the ECAM space for those buses via a _CBA method in the
PNP0A08 device.
  - Tell the config accessors (struct pci_ops) that the ECAM space for
buses A-B is at address X.
  - Enumerate the devices behind the host bridge by calling
pci_scan_root_bus(), passing the config accessors.

It sounds like you want a way to parse the resources at one point,
saving them and marking the ECAM region, then at a later point, look
up the ECAM from a saved list.  We don't do that on x86 because the
config accessors keep an internal list of the ECAM area for each bus.

We do of course want to put this ECAM space in the IORESOURCE_MEM tree
because it consumes address space and we have to make sure we don't
put anything else on top of it.  But we don't have any reason to
describe the MMIO -> config space function in that tree.  From the
point of view of the rest of the system, it's just MMIO space that's
consumed by the PCI host bridge, just like any other device-specific
MMIO area.

Bjorn


From plagnioj at jcrosoft.com  Tue Aug 14 13:44:25 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 14 Aug 2012 19:44:25 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
In-Reply-To: <502A6EEC.2010807@atmel.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
 <502A6EEC.2010807@atmel.com>
Message-ID: <20120814174425.GD8836@game.jcrosoft.org>

On 17:29 Tue 14 Aug     , Nicolas Ferre wrote:
> On 08/14/2012 03:49 PM, Richard Genoud :
> > Nicolas,
> > I said that I had some work done on sam9g35-ek, here is the spi part, based
> > on your and Jean-Christophe work.
> > You have to enable CONFIG_ARCH_AT91SAM9X5 to get it work.
> > 
> > The goal of this patchset is to share the work I've done, it's not ready
> > for upstream, but it may save some time.
> > 
> > It's based on 3.6-rc1 + Jean-Christophe's pinctrl patchset.
> > 
> > Best Regards,
> 
> Richard,
> 
> Thanks a lot for updating this material: We really appreciate.
> 
> We will try to review this material together with Jean-Christophe and
> colleagues @ Atmel. I hope that we will go forward with this collected
> material in the near future.
> 
> Maybe DMA OF part will not be upstreamed as-is because of an ongoing
> initiative to build a generic dmaengine OF support.
> 
> > Jean-Christophe PLAGNIOL-VILLARD (3):
> >   of: add dma-mask binding
> >   of_spi: add generic binding support to specify cs gpio
> 
> I know that Jean-Christophe has had difficulties to have feedback on
> there parts...
yes I need to re-write it as suggest by Grant

will take a look later next week on this
> 
> >   spi/atmel: add DT support
> > 
> > Nicolas Ferre (6):
> >   spi/atmel_spi: trivial: change some comments
> >   spi/atmel_spi: add physical base address
> >   spi/atmel_spi: call unmapping on transfers buffers
> >   spi/atmel_spi: status information passed through controller data
> >   spi/atmel_spi: add flag to controller data for lock operations
> >   spi/atmel_spi: add dmaengine support
> > 
> > Richard Genoud (14):
> >   spi-atmel: update with dmaengine interface
> 
> This will certainly be squashed in previous path.
> 
> >   spi-atmel: fix __init/__devinit sections mismatch
> 
> This one also: but it is good to have them separated at fist.
> 
> >   spi-atmel: Fix spi-atmel driver to adapt to slave_config changes
> >   AT91 DMA OF support
> >   add at91sam9x5 Kconfig ARCH/SOC link
> 
> Is it fixup for a bug? Jean-Christophe, a though about this one?
no the ARCH_xxx is old style can not be used on DT only soc

this patch need to be droped

Best Regards,
J.


From nicolas.ferre at atmel.com  Tue Aug 14 13:48:12 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 14 Aug 2012 19:48:12 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
In-Reply-To: <20120814174425.GD8836@game.jcrosoft.org>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
 <502A6EEC.2010807@atmel.com> <20120814174425.GD8836@game.jcrosoft.org>
Message-ID: <502A8F5C.6000303@atmel.com>

On 08/14/2012 07:44 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On 17:29 Tue 14 Aug     , Nicolas Ferre wrote:
>> On 08/14/2012 03:49 PM, Richard Genoud :
>>> Nicolas,
>>> I said that I had some work done on sam9g35-ek, here is the spi part, based
>>> on your and Jean-Christophe work.
>>> You have to enable CONFIG_ARCH_AT91SAM9X5 to get it work.
>>>
>>> The goal of this patchset is to share the work I've done, it's not ready
>>> for upstream, but it may save some time.
>>>
>>> It's based on 3.6-rc1 + Jean-Christophe's pinctrl patchset.
>>>
>>> Best Regards,
>>
>> Richard,
>>
>> Thanks a lot for updating this material: We really appreciate.
>>
>> We will try to review this material together with Jean-Christophe and
>> colleagues @ Atmel. I hope that we will go forward with this collected
>> material in the near future.
>>
>> Maybe DMA OF part will not be upstreamed as-is because of an ongoing
>> initiative to build a generic dmaengine OF support.
>>
>>> Jean-Christophe PLAGNIOL-VILLARD (3):
>>>   of: add dma-mask binding
>>>   of_spi: add generic binding support to specify cs gpio
>>
>> I know that Jean-Christophe has had difficulties to have feedback on
>> there parts...
> yes I need to re-write it as suggest by Grant
> 
> will take a look later next week on this
>>
>>>   spi/atmel: add DT support
>>>
>>> Nicolas Ferre (6):
>>>   spi/atmel_spi: trivial: change some comments
>>>   spi/atmel_spi: add physical base address
>>>   spi/atmel_spi: call unmapping on transfers buffers
>>>   spi/atmel_spi: status information passed through controller data
>>>   spi/atmel_spi: add flag to controller data for lock operations
>>>   spi/atmel_spi: add dmaengine support
>>>
>>> Richard Genoud (14):
>>>   spi-atmel: update with dmaengine interface
>>
>> This will certainly be squashed in previous path.
>>
>>>   spi-atmel: fix __init/__devinit sections mismatch
>>
>> This one also: but it is good to have them separated at fist.
>>
>>>   spi-atmel: Fix spi-atmel driver to adapt to slave_config changes
>>>   AT91 DMA OF support
>>>   add at91sam9x5 Kconfig ARCH/SOC link
>>
>> Is it fixup for a bug? Jean-Christophe, a though about this one?
> no the ARCH_xxx is old style can not be used on DT only soc
> 
> this patch need to be droped

That is what I suspected, thanks J.

Bye,
-- 
Nicolas Ferre


From matt at genesi-usa.com  Tue Aug 14 13:49:43 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue, 14 Aug 2012 12:49:43 -0500
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
In-Reply-To: <20120814114059.GX1451@pengutronix.de>
References: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
 <20120813193517.GU1451@pengutronix.de>
 <CAKGA1bnRA61JT8tQoHBay+6BSxDO5egiagQm1v05L7Asf+qJ+Q@mail.gmail.com>
 <20120814114059.GX1451@pengutronix.de>
Message-ID: <CAKGA1bmk2TqDwxR=RT+z3y8XaSpcW+kHsaQfmdrHVqTD9Uxv5A@mail.gmail.com>

On Tue, Aug 14, 2012 at 6:40 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Mon, Aug 13, 2012 at 05:28:17PM -0500, Matt Sealey wrote:
>>  IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /*
>> MX51_PAD_EIM_DA15__EIM_DA15 */
>>
>>
>>
>> On Mon, Aug 13, 2012 at 2:35 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > Hi Dave,
>> >
>> > On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:
>> >> Because FIQ handlers get copied straight into the vectors page to
>> >> the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
>> >> start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
>> >> Thumb-2.
>> >
>> > I finally came along testing this. I have no Thumb2 capable hardware
>> > to test if it works in thumb2 mode, but at least in Arm mode it works.
>> > This is enough to not introduce a regression, so we can go for this.
>>
>> This is the interesting dichotomy; the code is only required truly on
>> devices where Thumb2 isn't available, right?
>
> It is also used on the i.MX51 Eukrea board. I asked Eric (Cced) to test
> it in thumb2 mode, no response so far. I don't know the reason why he
> uses FIQ mode instead of SDMA, maybe simply historical reasons.

If we can lose that requirement then the only thing in the way is the
phyCORE support, which goes away on a "pure" v7 config anyway,
correct? I was just thinking, why not split v6_v7_defconfig into a
v7_defconfig losing those boards anyway and enable Thumb2 by default
while we're at it? It would mean more testing gets done and this error
would crop up both more often, but be less surprising and won't take a
year to revisit ;)

Pure v7 config would still include Tegra, OMAP3/4, i.MX5 onwards and
the newer chips. One zImage for v6_v7 is still possible but I don't
know if anyone really has the idea in their heads that you'd want to
boot the same kernel on i.MX3 as well as i.MX6Q even if they do share
drivers to some degree.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From catalin.marinas at arm.com  Tue Aug 14 13:52:01 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:01 +0100
Subject: [PATCH v2 00/31] AArch64 Linux kernel port
Message-ID: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>

This is the 2nd version of the set of patches implementing Linux kernel
support for the 64-bit ARM architecture (AArch64). Thanks to all who
provided feedback on the previous version.

The Linux kernel patches are available on this tree:

git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git upstream

The "master" branch in the above repository tracks the development
history.

Main changes from the previous version (for the full log see the
"master" branch above):

- Kernel port directory and related functions renamed to "arm64".
  "uname -m" reports "aarch64" as per the official name.
- NO_BOOTMEM enabled.
- "mem=" is now used for limiting the amount of memory rather than
  specifying the memory banks (already done via FDT).
- struct mem_type removed as static definitions are enough for
  ioremap().
- Support for ZONE_DMA32.
- Replaced "user_debug" with "/proc/sys/debug/exception-trace".
- Added a generic defconfig file.
- More clean-up (comments, code) and bug-fixes.

The generic patches were dropped from this series as they have been pushed
separately (and most of them already merged into mainline).


Background to the 64-bit ARM architecture:

ARM introduced AArch64 as part of the ARMv8 architecture and consists of
a substantially revised exception model (with 4 exception levels: EL0 -
user, EL1 - kernel, EL2 - hypervisor, EL3 - secure monitor), new A64
instruction set based on larger register file, new FP/SIMD instructions.
The new ABI is LP64 and takes advantage of the larger register file. It
also mandates FP.

AArch64 documentation currently available (publicly, though
click-through agreement required):

- Instruction Set Overview:
http://infocenter.arm.com/help/topic/com.arm.doc.genc010197a/index.html

- ABI (PCS, ELF, DWARF, C++):
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0059a/index.html


Regards,

Catalin


Catalin Marinas (23):
  arm64: Assembly macros and definitions
  arm64: Kernel booting and initialisation
  arm64: Exception handling
  arm64: MMU definitions
  arm64: MMU initialisation
  arm64: MMU fault handling and page table management
  arm64: Process management
  arm64: CPU support
  arm64: Cache maintenance routines
  arm64: TLB maintenance functionality
  arm64: Atomic operations
  arm64: Device specific operations
  arm64: DMA mapping API
  arm64: SMP support
  arm64: ELF definitions
  arm64: System calls handling
  arm64: Signal handling support
  arm64: User access library functions
  arm64: Floating point and SIMD
  arm64: Add support for /proc/sys/debug/exception-trace
  arm64: Miscellaneous header files
  arm64: Build infrastructure
  arm64: MAINTAINERS update

Marc Zyngier (3):
  arm64: IRQ handling
  arm64: Miscellaneous library functions
  arm64: Generic timers support

Will Deacon (5):
  arm64: VDSO support
  arm64: 32-bit (compat) applications support
  arm64: Debugging support
  arm64: Performance counters support
  arm64: Loadable modules

 Documentation/arm64/booting.txt               |  141 +++
 Documentation/arm64/memory.txt                |   69 ++
 MAINTAINERS                                   |    6 +
 arch/arm64/Kconfig                            |  261 +++++
 arch/arm64/Kconfig.debug                      |   27 +
 arch/arm64/Makefile                           |   71 ++
 arch/arm64/boot/.gitignore                    |    2 +
 arch/arm64/boot/Makefile                      |   38 +
 arch/arm64/boot/install.sh                    |   52 +
 arch/arm64/configs/generic_defconfig          |   85 ++
 arch/arm64/include/asm/Kbuild                 |   51 +
 arch/arm64/include/asm/asm-offsets.h          |    1 +
 arch/arm64/include/asm/assembler.h            |  109 ++
 arch/arm64/include/asm/atomic.h               |  306 ++++++
 arch/arm64/include/asm/auxvec.h               |   22 +
 arch/arm64/include/asm/barrier.h              |   52 +
 arch/arm64/include/asm/bitops.h               |   74 ++
 arch/arm64/include/asm/bitsperlong.h          |   23 +
 arch/arm64/include/asm/byteorder.h            |   21 +
 arch/arm64/include/asm/cache.h                |   32 +
 arch/arm64/include/asm/cacheflush.h           |  209 ++++
 arch/arm64/include/asm/cachetype.h            |   48 +
 arch/arm64/include/asm/cmpxchg.h              |  180 ++++
 arch/arm64/include/asm/compat.h               |  232 +++++
 arch/arm64/include/asm/compiler.h             |   30 +
 arch/arm64/include/asm/cputype.h              |   49 +
 arch/arm64/include/asm/debug-monitors.h       |   88 ++
 arch/arm64/include/asm/device.h               |   26 +
 arch/arm64/include/asm/dma-mapping.h          |  124 +++
 arch/arm64/include/asm/elf.h                  |  176 ++++
 arch/arm64/include/asm/exception.h            |   23 +
 arch/arm64/include/asm/exec.h                 |   23 +
 arch/arm64/include/asm/fb.h                   |   34 +
 arch/arm64/include/asm/fcntl.h                |   29 +
 arch/arm64/include/asm/fpsimd.h               |   64 ++
 arch/arm64/include/asm/futex.h                |  134 +++
 arch/arm64/include/asm/hardirq.h              |   52 +
 arch/arm64/include/asm/hw_breakpoint.h        |  137 +++
 arch/arm64/include/asm/hwcap.h                |   57 +
 arch/arm64/include/asm/io.h                   |  263 +++++
 arch/arm64/include/asm/irq.h                  |    8 +
 arch/arm64/include/asm/irqflags.h             |   91 ++
 arch/arm64/include/asm/memblock.h             |   21 +
 arch/arm64/include/asm/memory.h               |  144 +++
 arch/arm64/include/asm/mmu.h                  |   27 +
 arch/arm64/include/asm/mmu_context.h          |  152 +++
 arch/arm64/include/asm/module.h               |   23 +
 arch/arm64/include/asm/page.h                 |   67 ++
 arch/arm64/include/asm/param.h                |   23 +
 arch/arm64/include/asm/perf_event.h           |   22 +
 arch/arm64/include/asm/pgalloc.h              |  113 ++
 arch/arm64/include/asm/pgtable-2level-hwdef.h |   43 +
 arch/arm64/include/asm/pgtable-2level-types.h |   60 ++
 arch/arm64/include/asm/pgtable-3level-hwdef.h |   50 +
 arch/arm64/include/asm/pgtable-3level-types.h |   66 ++
 arch/arm64/include/asm/pgtable-hwdef.h        |   94 ++
 arch/arm64/include/asm/pgtable.h              |  328 ++++++
 arch/arm64/include/asm/pmu.h                  |   82 ++
 arch/arm64/include/asm/proc-fns.h             |   51 +
 arch/arm64/include/asm/processor.h            |  174 ++++
 arch/arm64/include/asm/procinfo.h             |   44 +
 arch/arm64/include/asm/prom.h                 |    1 +
 arch/arm64/include/asm/ptrace.h               |  206 ++++
 arch/arm64/include/asm/setup.h                |   26 +
 arch/arm64/include/asm/shmparam.h             |   28 +
 arch/arm64/include/asm/sigcontext.h           |   69 ++
 arch/arm64/include/asm/siginfo.h              |   23 +
 arch/arm64/include/asm/signal.h               |   24 +
 arch/arm64/include/asm/signal32.h             |   54 +
 arch/arm64/include/asm/smp.h                  |   69 ++
 arch/arm64/include/asm/sparsemem.h            |   24 +
 arch/arm64/include/asm/spinlock.h             |  199 ++++
 arch/arm64/include/asm/spinlock_types.h       |   38 +
 arch/arm64/include/asm/stacktrace.h           |   29 +
 arch/arm64/include/asm/stat.h                 |   63 ++
 arch/arm64/include/asm/statfs.h               |   23 +
 arch/arm64/include/asm/syscall.h              |  101 ++
 arch/arm64/include/asm/syscalls.h             |   40 +
 arch/arm64/include/asm/system_misc.h          |   54 +
 arch/arm64/include/asm/thread_info.h          |  124 +++
 arch/arm64/include/asm/timex.h                |   32 +
 arch/arm64/include/asm/tlb.h                  |  190 ++++
 arch/arm64/include/asm/tlbflush.h             |  123 +++
 arch/arm64/include/asm/traps.h                |   30 +
 arch/arm64/include/asm/uaccess.h              |  377 +++++++
 arch/arm64/include/asm/ucontext.h             |   30 +
 arch/arm64/include/asm/unistd.h               |   27 +
 arch/arm64/include/asm/unistd32.h             |  758 ++++++++++++++
 arch/arm64/include/asm/vdso.h                 |   41 +
 arch/arm64/include/asm/vdso_datapage.h        |   43 +
 arch/arm64/kernel/.gitignore                  |    1 +
 arch/arm64/kernel/Makefile                    |   27 +
 arch/arm64/kernel/arm64ksyms.c                |   55 +
 arch/arm64/kernel/asm-offsets.c               |  108 ++
 arch/arm64/kernel/debug-monitors.c            |  288 ++++++
 arch/arm64/kernel/elf.c                       |   41 +
 arch/arm64/kernel/entry-fpsimd.S              |   80 ++
 arch/arm64/kernel/entry.S                     |  695 +++++++++++++
 arch/arm64/kernel/fpsimd.c                    |  106 ++
 arch/arm64/kernel/head.S                      |  521 ++++++++++
 arch/arm64/kernel/hw_breakpoint.c             |  880 ++++++++++++++++
 arch/arm64/kernel/io.c                        |   64 ++
 arch/arm64/kernel/irq.c                       |   84 ++
 arch/arm64/kernel/kuser32.S                   |   77 ++
 arch/arm64/kernel/module.c                    |  456 ++++++++
 arch/arm64/kernel/perf_event.c                | 1368 +++++++++++++++++++++++++
 arch/arm64/kernel/process.c                   |  416 ++++++++
 arch/arm64/kernel/ptrace.c                    |  834 +++++++++++++++
 arch/arm64/kernel/setup.c                     |  357 +++++++
 arch/arm64/kernel/signal.c                    |  436 ++++++++
 arch/arm64/kernel/signal32.c                  |  876 ++++++++++++++++
 arch/arm64/kernel/smp.c                       |  469 +++++++++
 arch/arm64/kernel/stacktrace.c                |  127 +++
 arch/arm64/kernel/sys.c                       |  138 +++
 arch/arm64/kernel/sys32.S                     |  283 +++++
 arch/arm64/kernel/sys_compat.c                |  177 ++++
 arch/arm64/kernel/time.c                      |   65 ++
 arch/arm64/kernel/traps.c                     |  357 +++++++
 arch/arm64/kernel/vdso.c                      |  261 +++++
 arch/arm64/kernel/vdso/.gitignore             |    2 +
 arch/arm64/kernel/vdso/Makefile               |   63 ++
 arch/arm64/kernel/vdso/gen_vdso_offsets.sh    |   15 +
 arch/arm64/kernel/vdso/gettimeofday.S         |  242 +++++
 arch/arm64/kernel/vdso/note.S                 |   28 +
 arch/arm64/kernel/vdso/sigreturn.S            |   37 +
 arch/arm64/kernel/vdso/vdso.S                 |   33 +
 arch/arm64/kernel/vdso/vdso.lds.S             |  100 ++
 arch/arm64/kernel/vmlinux.lds.S               |  146 +++
 arch/arm64/lib/Makefile                       |    5 +
 arch/arm64/lib/bitops.c                       |   25 +
 arch/arm64/lib/clear_page.S                   |   39 +
 arch/arm64/lib/clear_user.S                   |   58 ++
 arch/arm64/lib/copy_from_user.S               |   66 ++
 arch/arm64/lib/copy_in_user.S                 |   63 ++
 arch/arm64/lib/copy_page.S                    |   46 +
 arch/arm64/lib/copy_to_user.S                 |   61 ++
 arch/arm64/lib/delay.c                        |   55 +
 arch/arm64/lib/getuser.S                      |   75 ++
 arch/arm64/lib/putuser.S                      |   73 ++
 arch/arm64/lib/strncpy_from_user.S            |   50 +
 arch/arm64/lib/strnlen_user.S                 |   47 +
 arch/arm64/mm/Kconfig                         |    5 +
 arch/arm64/mm/Makefile                        |    6 +
 arch/arm64/mm/cache.S                         |  279 +++++
 arch/arm64/mm/context.c                       |  159 +++
 arch/arm64/mm/copypage.c                      |   34 +
 arch/arm64/mm/dma-mapping.c                   |  208 ++++
 arch/arm64/mm/extable.c                       |   17 +
 arch/arm64/mm/fault.c                         |  534 ++++++++++
 arch/arm64/mm/flush.c                         |  132 +++
 arch/arm64/mm/init.c                          |  416 ++++++++
 arch/arm64/mm/ioremap.c                       |   84 ++
 arch/arm64/mm/mm.h                            |    2 +
 arch/arm64/mm/mmap.c                          |  144 +++
 arch/arm64/mm/mmu.c                           |  395 +++++++
 arch/arm64/mm/pgd.c                           |   49 +
 arch/arm64/mm/proc-macros.S                   |   55 +
 arch/arm64/mm/proc-syms.c                     |   31 +
 arch/arm64/mm/proc.S                          |  193 ++++
 arch/arm64/mm/tlb.S                           |   71 ++
 drivers/clocksource/Kconfig                   |    5 +
 drivers/clocksource/Makefile                  |    1 +
 drivers/clocksource/arm_generic.c             |  309 ++++++
 include/clocksource/arm_generic.h             |   21 +
 init/Kconfig                                  |    3 +-
 kernel/sysctl.c                               |    2 +-
 lib/Kconfig.debug                             |    6 +-
 tools/perf/perf.h                             |    6 +
 168 files changed, 22089 insertions(+), 4 deletions(-)



From catalin.marinas at arm.com  Tue Aug 14 13:52:06 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:06 +0100
Subject: [PATCH v2 05/31] arm64: MMU initialisation
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>

This patch contains the initialisation of the memory blocks, MMU
attributes and the memory map. Only five memory types are defined:
Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
Cache policies are supported via the memory attributes register
(MAIR_EL1) and only affect the Normal Cacheable mappings.

This patch also adds the SPARSEMEM_VMEMMAP initialisation.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/memblock.h |   21 ++
 arch/arm64/mm/init.c              |  416 +++++++++++++++++++++++++++++++++++++
 arch/arm64/mm/mmu.c               |  395 +++++++++++++++++++++++++++++++++++
 3 files changed, 832 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/memblock.h
 create mode 100644 arch/arm64/mm/init.c
 create mode 100644 arch/arm64/mm/mmu.c

diff --git a/arch/arm64/include/asm/memblock.h b/arch/arm64/include/asm/memblock.h
new file mode 100644
index 0000000..6afeed2
--- /dev/null
+++ b/arch/arm64/include/asm/memblock.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_MEMBLOCK_H
+#define __ASM_MEMBLOCK_H
+
+extern void arm64_memblock_init(void);
+
+#endif
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
new file mode 100644
index 0000000..c87583d
--- /dev/null
+++ b/arch/arm64/mm/init.c
@@ -0,0 +1,416 @@
+/*
+ * Based on arch/arm/mm/init.c
+ *
+ * Copyright (C) 1995-2005 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/errno.h>
+#include <linux/swap.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/mman.h>
+#include <linux/nodemask.h>
+#include <linux/initrd.h>
+#include <linux/gfp.h>
+#include <linux/memblock.h>
+#include <linux/sort.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/sizes.h>
+#include <asm/tlb.h>
+
+#include "mm.h"
+
+static unsigned long phys_initrd_start __initdata = 0;
+static unsigned long phys_initrd_size __initdata = 0;
+
+phys_addr_t memstart_addr __read_mostly = 0;
+
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+					    unsigned long end)
+{
+	phys_initrd_start = start;
+	phys_initrd_size = end - start;
+}
+
+static int __init early_initrd(char *p)
+{
+	unsigned long start, size;
+	char *endp;
+
+	start = memparse(p, &endp);
+	if (*endp == ',') {
+		size = memparse(endp + 1, NULL);
+
+		phys_initrd_start = start;
+		phys_initrd_size = size;
+	}
+	return 0;
+}
+early_param("initrd", early_initrd);
+
+#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
+
+static void __init zone_sizes_init(unsigned long min, unsigned long max)
+{
+	unsigned long zone_size[MAX_NR_ZONES];
+	unsigned long max_dma32 = min;
+
+	memset(zone_size, 0, sizeof(zone_size));
+
+	zone_size[0] = max - min;
+#ifdef CONFIG_ZONE_DMA32
+	/* 4GB maximum for 32-bit only capable devices */
+	max_dma32 = min(max, MAX_DMA32_PFN);
+	zone_size[ZONE_DMA32] = max_dma32 - min;
+#endif
+	zone_size[ZONE_NORMAL] = max - max_dma32;
+
+	free_area_init(zone_size);
+}
+
+#ifdef CONFIG_HAVE_ARCH_PFN_VALID
+int pfn_valid(unsigned long pfn)
+{
+	return memblock_is_memory(pfn << PAGE_SHIFT);
+}
+EXPORT_SYMBOL(pfn_valid);
+#endif
+
+#ifndef CONFIG_SPARSEMEM
+static void arm64_memory_present(void)
+{
+}
+#else
+static void arm64_memory_present(void)
+{
+	struct memblock_region *reg;
+
+	for_each_memblock(memory, reg)
+		memory_present(0, memblock_region_memory_base_pfn(reg),
+			       memblock_region_memory_end_pfn(reg));
+}
+#endif
+
+void __init arm64_memblock_init(void)
+{
+	u64 *reserve_map, base, size;
+
+	/* Register the kernel text, kernel data and initrd with memblock */
+	memblock_reserve(__pa(_text), _end - _text);
+#ifdef CONFIG_BLK_DEV_INITRD
+	if (phys_initrd_size) {
+		memblock_reserve(phys_initrd_start, phys_initrd_size);
+
+		/* Now convert initrd to virtual addresses */
+		initrd_start = __phys_to_virt(phys_initrd_start);
+		initrd_end = initrd_start + phys_initrd_size;
+	}
+#endif
+
+	/*
+	 * Reserve the page tables.  These are already in use,
+	 * and can only be in node 0.
+	 */
+	memblock_reserve(__pa(swapper_pg_dir), SWAPPER_DIR_SIZE);
+	memblock_reserve(__pa(idmap_pg_dir), IDMAP_DIR_SIZE);
+
+	/* Reserve the dtb region */
+	memblock_reserve(virt_to_phys(initial_boot_params),
+			 be32_to_cpu(initial_boot_params->totalsize));
+
+	/*
+	 * Process the reserve map.  This will probably overlap the initrd
+	 * and dtb locations which are already reserved, but overlapping
+	 * doesn't hurt anything
+	 */
+	reserve_map = ((void*)initial_boot_params) +
+			be32_to_cpu(initial_boot_params->off_mem_rsvmap);
+	while (1) {
+		base = be64_to_cpup(reserve_map++);
+		size = be64_to_cpup(reserve_map++);
+		if (!size)
+			break;
+		memblock_reserve(base, size);
+	}
+
+	memblock_allow_resize();
+	memblock_dump_all();
+}
+
+void __init bootmem_init(void)
+{
+	unsigned long min, max;
+
+	min = PFN_UP(memblock_start_of_DRAM());
+	max = PFN_DOWN(memblock_end_of_DRAM());
+
+	/*
+	 * Sparsemem tries to allocate bootmem in memory_present(), so must be
+	 * done after the fixed reservations.
+	 */
+	arm64_memory_present();
+
+	sparse_init();
+	zone_sizes_init(min, max);
+
+	high_memory = __va((max << PAGE_SHIFT) - 1) + 1;
+	max_pfn = max_low_pfn = max;
+}
+
+static inline int free_area(unsigned long pfn, unsigned long end, char *s)
+{
+	unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
+
+	for (; pfn < end; pfn++) {
+		struct page *page = pfn_to_page(pfn);
+		ClearPageReserved(page);
+		init_page_count(page);
+		__free_page(page);
+		pages++;
+	}
+
+	if (size && s)
+		pr_info("Freeing %s memory: %dK\n", s, size);
+
+	return pages;
+}
+
+/*
+ * Poison init memory with an undefined instruction (0x0).
+ */
+static inline void poison_init_mem(void *s, size_t count)
+{
+	memset(s, 0, count);
+}
+
+#ifndef CONFIG_SPARSEMEM_VMEMMAP
+static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
+{
+	struct page *start_pg, *end_pg;
+	unsigned long pg, pgend;
+
+	/*
+	 * Convert start_pfn/end_pfn to a struct page pointer.
+	 */
+	start_pg = pfn_to_page(start_pfn - 1) + 1;
+	end_pg = pfn_to_page(end_pfn - 1) + 1;
+
+	/*
+	 * Convert to physical addresses, and round start upwards and end
+	 * downwards.
+	 */
+	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
+	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+
+	/*
+	 * If there are free pages between these, free the section of the
+	 * memmap array.
+	 */
+	if (pg < pgend)
+		free_bootmem(pg, pgend - pg);
+}
+
+/*
+ * The mem_map array can get very big. Free the unused area of the memory map.
+ */
+static void __init free_unused_memmap(void)
+{
+	unsigned long start, prev_end = 0;
+	struct memblock_region *reg;
+
+	for_each_memblock(memory, reg) {
+		start = __phys_to_pfn(reg->base);
+
+#ifdef CONFIG_SPARSEMEM
+		/*
+		 * Take care not to free memmap entries that don't exist due
+		 * to SPARSEMEM sections which aren't present.
+		 */
+		start = min(start, ALIGN(prev_end, PAGES_PER_SECTION));
+#endif
+		/*
+		 * If we had a previous bank, and there is a space between the
+		 * current bank and the previous, free it.
+		 */
+		if (prev_end && prev_end < start)
+			free_memmap(prev_end, start);
+
+		/*
+		 * Align up here since the VM subsystem insists that the
+		 * memmap entries are valid from the bank end aligned to
+		 * MAX_ORDER_NR_PAGES.
+		 */
+		prev_end = ALIGN(start + __phys_to_pfn(reg->size),
+				 MAX_ORDER_NR_PAGES);
+	}
+
+#ifdef CONFIG_SPARSEMEM
+	if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION))
+		free_memmap(prev_end, ALIGN(prev_end, PAGES_PER_SECTION));
+#endif
+}
+#endif	/* !CONFIG_SPARSEMEM_VMEMMAP */
+
+/*
+ * mem_init() marks the free areas in the mem_map and tells us how much memory
+ * is free.  This is done after various parts of the system have claimed their
+ * memory after the kernel image.
+ */
+void __init mem_init(void)
+{
+	unsigned long reserved_pages, free_pages;
+	struct memblock_region *reg;
+
+#if CONFIG_SWIOTLB
+	extern void __init arm64_swiotlb_init(size_t max_size);
+	arm64_swiotlb_init(max_pfn << (PAGE_SHIFT - 1));
+#endif
+
+	max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
+
+#ifndef CONFIG_SPARSEMEM_VMEMMAP
+	/* this will put all unused low memory onto the freelists */
+	free_unused_memmap();
+#endif
+
+	totalram_pages += free_all_bootmem();
+
+	reserved_pages = free_pages = 0;
+
+	for_each_memblock(memory, reg) {
+		unsigned int pfn1, pfn2;
+		struct page *page, *end;
+
+		pfn1 = __phys_to_pfn(reg->base);
+		pfn2 = pfn1 + __phys_to_pfn(reg->size);
+
+		page = pfn_to_page(pfn1);
+		end  = pfn_to_page(pfn2 - 1) + 1;
+
+		do {
+			if (PageReserved(page))
+				reserved_pages++;
+			else if (!page_count(page))
+				free_pages++;
+			page++;
+		} while (page < end);
+	}
+
+	/*
+	 * Since our memory may not be contiguous, calculate the real number
+	 * of pages we have in this system.
+	 */
+	pr_info("Memory:");
+	num_physpages = 0;
+	for_each_memblock(memory, reg) {
+		unsigned long pages = memblock_region_memory_end_pfn(reg) -
+			memblock_region_memory_base_pfn(reg);
+		num_physpages += pages;
+		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
+	}
+	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
+
+	pr_notice("Memory: %luk/%luk available, %luk reserved\n",
+		  nr_free_pages() << (PAGE_SHIFT-10),
+		  free_pages << (PAGE_SHIFT-10),
+		  reserved_pages << (PAGE_SHIFT-10));
+
+#define MLK(b, t) b, t, ((t) - (b)) >> 10
+#define MLM(b, t) b, t, ((t) - (b)) >> 20
+#define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K)
+
+	pr_notice("Virtual kernel memory layout:\n"
+		  "    vmalloc : 0x%16lx - 0x%16lx   (%6ld MB)\n"
+#ifdef CONFIG_SPARSEMEM_VMEMMAP
+		  "    vmemmap : 0x%16lx - 0x%16lx   (%6ld MB)\n"
+#endif
+		  "    modules : 0x%16lx - 0x%16lx   (%6ld MB)\n"
+		  "    memory  : 0x%16lx - 0x%16lx   (%6ld MB)\n"
+		  "      .init : 0x%p" " - 0x%p" "   (%6ld kB)\n"
+		  "      .text : 0x%p" " - 0x%p" "   (%6ld kB)\n"
+		  "      .data : 0x%p" " - 0x%p" "   (%6ld kB)\n",
+		  MLM(VMALLOC_START, VMALLOC_END),
+#ifdef CONFIG_SPARSEMEM_VMEMMAP
+		  MLM((unsigned long)virt_to_page(PAGE_OFFSET),
+		      (unsigned long)virt_to_page(high_memory)),
+#endif
+		  MLM(MODULES_VADDR, MODULES_END),
+		  MLM(PAGE_OFFSET, (unsigned long)high_memory),
+
+		  MLK_ROUNDUP(__init_begin, __init_end),
+		  MLK_ROUNDUP(_text, _etext),
+		  MLK_ROUNDUP(_sdata, _edata));
+
+#undef MLK
+#undef MLM
+#undef MLK_ROUNDUP
+
+	/*
+	 * Check boundaries twice: Some fundamental inconsistencies can be
+	 * detected at build time already.
+	 */
+#ifdef CONFIG_AARCH32_EMULATION
+	BUILD_BUG_ON(TASK_SIZE_32			> TASK_SIZE_64);
+#endif
+	BUILD_BUG_ON(TASK_SIZE_64			> MODULES_VADDR);
+	BUG_ON(TASK_SIZE_64				> MODULES_VADDR);
+
+	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+		extern int sysctl_overcommit_memory;
+		/*
+		 * On a machine this small we won't get anywhere without
+		 * overcommit, so turn it on by default.
+		 */
+		sysctl_overcommit_memory = OVERCOMMIT_ALWAYS;
+	}
+}
+
+void free_initmem(void)
+{
+	poison_init_mem(__init_begin, __init_end - __init_begin);
+	totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)),
+				    __phys_to_pfn(__pa(__init_end)),
+				    "init");
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+
+static int keep_initrd;
+
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+	if (!keep_initrd) {
+		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
+		totalram_pages += free_area(__phys_to_pfn(__pa(start)),
+					    __phys_to_pfn(__pa(end)),
+					    "initrd");
+	}
+}
+
+static int __init keepinitrd_setup(char *__unused)
+{
+	keep_initrd = 1;
+	return 1;
+}
+
+__setup("keepinitrd", keepinitrd_setup);
+#endif
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
new file mode 100644
index 0000000..d2dd438
--- /dev/null
+++ b/arch/arm64/mm/mmu.c
@@ -0,0 +1,395 @@
+/*
+ * Based on arch/arm/mm/mmu.c
+ *
+ * Copyright (C) 1995-2005 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/mman.h>
+#include <linux/nodemask.h>
+#include <linux/memblock.h>
+#include <linux/fs.h>
+
+#include <asm/cputype.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/sizes.h>
+#include <asm/tlb.h>
+#include <asm/mmu_context.h>
+
+#include "mm.h"
+
+/*
+ * Empty_zero_page is a special page that is used for zero-initialized data
+ * and COW.
+ */
+struct page *empty_zero_page;
+EXPORT_SYMBOL(empty_zero_page);
+
+pgprot_t pgprot_default;
+EXPORT_SYMBOL(pgprot_default);
+
+static pmdval_t prot_sect_kernel;
+
+struct cachepolicy {
+	const char	policy[16];
+	u64		mair;
+	u64		tcr;
+};
+
+static struct cachepolicy cache_policies[] __initdata = {
+	{
+		.policy		= "uncached",
+		.mair		= 0x44,			/* inner, outer non-cacheable */
+		.tcr		= TCR_IRGN_NC | TCR_ORGN_NC,
+	}, {
+		.policy		= "writethrough",
+		.mair		= 0xaa,			/* inner, outer write-through, read-allocate */
+		.tcr		= TCR_IRGN_WT | TCR_ORGN_WT,
+	}, {
+		.policy		= "writeback",
+		.mair		= 0xee,			/* inner, outer write-back, read-allocate */
+		.tcr		= TCR_IRGN_WBnWA | TCR_ORGN_WBnWA,
+	}
+};
+
+/*
+ * These are useful for identifying cache coherency problems by allowing the
+ * cache or the cache and writebuffer to be turned off. It changes the Normal
+ * memory caching attributes in the MAIR_EL1 register.
+ */
+static int __init early_cachepolicy(char *p)
+{
+	int i;
+	u64 tmp;
+
+	for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
+		int len = strlen(cache_policies[i].policy);
+
+		if (memcmp(p, cache_policies[i].policy, len) == 0)
+			break;
+	}
+	if (i == ARRAY_SIZE(cache_policies)) {
+		pr_err("ERROR: unknown or unsupported cache policy: %s\n", p);
+		return 0;
+	}
+
+	flush_cache_all();
+
+	/*
+	 * Modify MT_NORMAL attributes in MAIR_EL1.
+	 */
+	asm volatile(
+	"	mrs	%0, mair_el1\n"
+	"	bfi	%0, %1, #%2, #8\n"
+	"	msr	mair_el1, %0\n"
+	"	isb\n"
+	: "=&r" (tmp)
+	: "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8));
+
+	/*
+	 * Modify TCR PTW cacheability attributes.
+	 */
+	asm volatile(
+	"	mrs	%0, tcr_el1\n"
+	"	bic	%0, %0, %2\n"
+	"	orr	%0, %0, %1\n"
+	"	msr	tcr_el1, %0\n"
+	"	isb\n"
+	: "=&r" (tmp)
+	: "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK | TCR_ORGN_MASK));
+
+	flush_cache_all();
+
+	return 0;
+}
+early_param("cachepolicy", early_cachepolicy);
+
+/*
+ * Adjust the PMD section entries according to the CPU in use.
+ */
+static void __init init_mem_pgprot(void)
+{
+	pteval_t default_pgprot;
+	int i;
+
+	default_pgprot = PTE_ATTRINDX(MT_NORMAL);
+	prot_sect_kernel = PMD_TYPE_SECT | PMD_SECT_AF | PMD_ATTRINDX(MT_NORMAL);
+
+#ifdef CONFIG_SMP
+	/*
+	 * Mark memory with the "shared" attribute for SMP systems
+	 */
+	default_pgprot |= PTE_SHARED;
+	prot_sect_kernel |= PMD_SECT_S;
+#endif
+
+	for (i = 0; i < 16; i++) {
+		unsigned long v = pgprot_val(protection_map[i]);
+		protection_map[i] = __pgprot(v | default_pgprot);
+	}
+
+	pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot);
+}
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+			      unsigned long size, pgprot_t vma_prot)
+{
+	if (!pfn_valid(pfn))
+		return pgprot_noncached(vma_prot);
+	else if (file->f_flags & O_SYNC)
+		return pgprot_writecombine(vma_prot);
+	return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);
+
+static void __init *early_alloc(unsigned long sz)
+{
+	void *ptr = __va(memblock_alloc(sz, sz));
+	memset(ptr, 0, sz);
+	return ptr;
+}
+
+static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
+				  unsigned long end, unsigned long pfn)
+{
+	pte_t *pte;
+
+	if (pmd_none(*pmd)) {
+		pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t));
+		__pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE);
+	}
+	BUG_ON(pmd_bad(*pmd));
+
+	pte = pte_offset_kernel(pmd, addr);
+	do {
+		set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC));
+		pfn++;
+	} while (pte++, addr += PAGE_SIZE, addr != end);
+}
+
+static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
+				  unsigned long end, phys_addr_t phys)
+{
+	pmd_t *pmd;
+	unsigned long next;
+
+	/*
+	 * Check for initial section mappings in the pgd/pud and remove them.
+	 */
+	if (pud_none(*pud) || pud_bad(*pud)) {
+		pmd = early_alloc(PTRS_PER_PMD * sizeof(pmd_t));
+		pud_populate(&init_mm, pud, pmd);
+	}
+
+	pmd = pmd_offset(pud, addr);
+	do {
+		next = pmd_addr_end(addr, end);
+		/* try section mapping first */
+		if (((addr | next | phys) & ~SECTION_MASK) == 0)
+			set_pmd(pmd, __pmd(phys | prot_sect_kernel));
+		else
+			alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys));
+		phys += next - addr;
+	} while (pmd++, addr = next, addr != end);
+}
+
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
+				  unsigned long end, unsigned long phys)
+{
+	pud_t *pud = pud_offset(pgd, addr);
+	unsigned long next;
+
+	do {
+		next = pud_addr_end(addr, end);
+		alloc_init_pmd(pud, addr, next, phys);
+		phys += next - addr;
+	} while (pud++, addr = next, addr != end);
+}
+
+/*
+ * Create the page directory entries and any necessary page tables for the
+ * mapping specified by 'md'.
+ */
+static void __init create_mapping(phys_addr_t phys, unsigned long virt,
+				  phys_addr_t size)
+{
+	unsigned long addr, length, end, next;
+	pgd_t *pgd;
+
+	if (virt < VMALLOC_START) {
+		pr_warning("BUG: not creating mapping for 0x%016llx at 0x%016lx - outside kernel range\n",
+			   phys, virt);
+		return;
+	}
+
+	addr = virt & PAGE_MASK;
+	length = PAGE_ALIGN(size + (virt & ~PAGE_MASK));
+
+	pgd = pgd_offset_k(addr);
+	end = addr + length;
+	do {
+		next = pgd_addr_end(addr, end);
+		alloc_init_pud(pgd, addr, next, phys);
+		phys += next - addr;
+	} while (pgd++, addr = next, addr != end);
+}
+
+static void __init map_mem(void)
+{
+	struct memblock_region *reg;
+
+	/* map all the memory banks */
+	for_each_memblock(memory, reg) {
+		phys_addr_t start = reg->base;
+		phys_addr_t end = start + reg->size;
+
+		if (start >= end)
+			break;
+
+		create_mapping(start, __phys_to_virt(start), end - start);
+	}
+}
+
+/*
+ * paging_init() sets up the page tables, initialises the zone memory
+ * maps and sets up the zero page.
+ */
+void __init paging_init(void)
+{
+	void *zero_page;
+
+	/*
+	 * Maximum PGDIR_SIZE addressable via the initial direct kernel
+	 * mapping in swapper_pg_dir.
+	 */
+	memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
+
+	init_mem_pgprot();
+	map_mem();
+
+	/*
+	 * Finally flush the caches and tlb to ensure that we're in a
+	 * consistent state.
+	 */
+	flush_cache_all();
+	flush_tlb_all();
+
+	/* allocate the zero page. */
+	zero_page = early_alloc(PAGE_SIZE);
+
+	bootmem_init();
+
+	empty_zero_page = virt_to_page(zero_page);
+	__flush_dcache_page(NULL, empty_zero_page);
+
+	/*
+	 * TTBR0 is only used for the identity mapping at this stage. Make it
+	 * point to zero page to avoid speculatively fetching new entries.
+	 */
+	cpu_set_reserved_ttbr0();
+	flush_tlb_all();
+}
+
+/*
+ * Enable the identity mapping to allow the MMU disabling.
+ */
+void setup_mm_for_reboot(void)
+{
+	cpu_switch_mm(idmap_pg_dir, &init_mm);
+	flush_tlb_all();
+}
+
+/*
+ * Check whether a kernel address is valid (derived from arch/x86/).
+ */
+int kern_addr_valid(unsigned long addr)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	if ((((long)addr) >> VA_BITS) != -1UL)
+		return 0;
+
+	pgd = pgd_offset_k(addr);
+	if (pgd_none(*pgd))
+		return 0;
+
+	pud = pud_offset(pgd, addr);
+	if (pud_none(*pud))
+		return 0;
+
+	pmd = pmd_offset(pud, addr);
+	if (pmd_none(*pmd))
+		return 0;
+
+	pte = pte_offset_kernel(pmd, addr);
+	if (pte_none(*pte))
+		return 0;
+
+	return pfn_valid(pte_pfn(*pte));
+}
+#ifdef CONFIG_SPARSEMEM_VMEMMAP
+#ifdef CONFIG_ARM64_64K_PAGES
+int __meminit vmemmap_populate(struct page *start_page,
+			       unsigned long size, int node)
+{
+	return vmemmap_populate_basepages(start_page, size, node);
+}
+#else	/* !CONFIG_ARM64_64K_PAGES */
+int __meminit vmemmap_populate(struct page *start_page,
+			       unsigned long size, int node)
+{
+	unsigned long addr = (unsigned long)start_page;
+	unsigned long end = (unsigned long)(start_page + size);
+	unsigned long next;
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+
+	do {
+		next = pmd_addr_end(addr, end);
+
+		pgd = vmemmap_pgd_populate(addr, node);
+		if (!pgd)
+			return -ENOMEM;
+
+		pud = vmemmap_pud_populate(pgd, addr, node);
+		if (!pud)
+			return -ENOMEM;
+
+		pmd = pmd_offset(pud, addr);
+		if (pmd_none(*pmd)) {
+			void *p = NULL;
+
+			p = vmemmap_alloc_block_buf(PMD_SIZE, node);
+			if (!p)
+				return -ENOMEM;
+
+			set_pmd(pmd, __pmd(__pa(p) | prot_sect_kernel));
+		} else
+			vmemmap_verify((pte_t *)pmd, node, addr, next);
+	} while (addr = next, addr != end);
+
+	return 0;
+}
+#endif	/* CONFIG_ARM64_64K_PAGES */
+#endif	/* CONFIG_SPARSEMEM_VMEMMAP */



From catalin.marinas at arm.com  Tue Aug 14 13:52:02 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:02 +0100
Subject: [PATCH v2 01/31] arm64: Assembly macros and definitions
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-2-git-send-email-catalin.marinas@arm.com>

This patch introduces several assembly macros and definitions used in
the .S files across arch/arm64/ like IRQ disabling/enabling, together
with asm-offsets.c.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/asm-offsets.h |    1 +
 arch/arm64/include/asm/assembler.h   |  109 ++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/asm-offsets.c      |  108 +++++++++++++++++++++++++++++++++
 arch/arm64/mm/proc-macros.S          |   55 +++++++++++++++++
 4 files changed, 273 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/asm-offsets.h
 create mode 100644 arch/arm64/include/asm/assembler.h
 create mode 100644 arch/arm64/kernel/asm-offsets.c
 create mode 100644 arch/arm64/mm/proc-macros.S

diff --git a/arch/arm64/include/asm/asm-offsets.h b/arch/arm64/include/asm/asm-offsets.h
new file mode 100644
index 0000000..d370ee3
--- /dev/null
+++ b/arch/arm64/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
new file mode 100644
index 0000000..da2a13e
--- /dev/null
+++ b/arch/arm64/include/asm/assembler.h
@@ -0,0 +1,109 @@
+/*
+ * Based on arch/arm/include/asm/assembler.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
+
+#include <asm/ptrace.h>
+
+/*
+ * Stack pushing/popping (register pairs only). Equivalent to store decrement
+ * before, load increment after.
+ */
+	.macro	push, xreg1, xreg2
+	stp	\xreg1, \xreg2, [sp, #-16]!
+	.endm
+
+	.macro	pop, xreg1, xreg2
+	ldp	\xreg1, \xreg2, [sp], #16
+	.endm
+
+/*
+ * Enable and disable interrupts.
+ */
+	.macro	disable_irq
+	msr	daifset, #2
+	.endm
+
+	.macro	enable_irq
+	msr	daifclr, #2
+	.endm
+
+/*
+ * Save/disable and restore interrupts.
+ */
+	.macro	save_and_disable_irqs, olddaif
+	mrs	\olddaif, daif
+	disable_irq
+	.endm
+
+	.macro	restore_irqs, olddaif
+	msr	daif, \olddaif
+	.endm
+
+/*
+ * Enable and disable debug exceptions.
+ */
+	.macro	disable_dbg
+	msr	daifset, #8
+	.endm
+
+	.macro	enable_dbg
+	msr	daifclr, #8
+	.endm
+
+	.macro	disable_step, tmp
+	mrs	\tmp, mdscr_el1
+	bic	\tmp, \tmp, #1
+	msr	mdscr_el1, \tmp
+	.endm
+
+	.macro	enable_step, tmp
+	mrs	\tmp, mdscr_el1
+	orr	\tmp, \tmp, #1
+	msr	mdscr_el1, \tmp
+	.endm
+
+	.macro	enable_dbg_if_not_stepping, tmp
+	mrs	\tmp, mdscr_el1
+	tbnz	\tmp, #1, 9990f
+	enable_dbg
+9990:
+	.endm
+
+/*
+ * SMP data memory barrier
+ */
+	.macro	smp_dmb, opt
+#ifdef CONFIG_SMP
+	dmb	\opt
+#endif
+	.endm
+
+#define USER(l, x...)				\
+9999:	x;					\
+	.section __ex_table,"a";		\
+	.align	3;				\
+	.quad	9999b,l;			\
+	.previous
+
+/*
+ * Register aliases.
+ */
+lr	.req	x30		// link register
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
new file mode 100644
index 0000000..5120e51
--- /dev/null
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -0,0 +1,108 @@
+/*
+ * Based on arch/arm/kernel/asm-offsets.c
+ *
+ * Copyright (C) 1995-2003 Russell King
+ *               2001-2002 Keith Owens
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+#include <asm/thread_info.h>
+#include <asm/memory.h>
+#include <asm/procinfo.h>
+#include <asm/vdso_datapage.h>
+#include <linux/kbuild.h>
+
+int main(void)
+{
+  DEFINE(TSK_ACTIVE_MM,		offsetof(struct task_struct, active_mm));
+  BLANK();
+  DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
+  DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
+  DEFINE(TI_ADDR_LIMIT,		offsetof(struct thread_info, addr_limit));
+  DEFINE(TI_TASK,		offsetof(struct thread_info, task));
+  DEFINE(TI_EXEC_DOMAIN,	offsetof(struct thread_info, exec_domain));
+  DEFINE(TI_CPU,		offsetof(struct thread_info, cpu));
+  BLANK();
+  DEFINE(THREAD_CPU_CONTEXT,	offsetof(struct task_struct, thread.cpu_context));
+  BLANK();
+  DEFINE(S_X0,			offsetof(struct pt_regs, regs[0]));
+  DEFINE(S_X1,			offsetof(struct pt_regs, regs[1]));
+  DEFINE(S_X2,			offsetof(struct pt_regs, regs[2]));
+  DEFINE(S_X3,			offsetof(struct pt_regs, regs[3]));
+  DEFINE(S_X4,			offsetof(struct pt_regs, regs[4]));
+  DEFINE(S_X5,			offsetof(struct pt_regs, regs[5]));
+  DEFINE(S_X6,			offsetof(struct pt_regs, regs[6]));
+  DEFINE(S_X7,			offsetof(struct pt_regs, regs[7]));
+  DEFINE(S_LR,			offsetof(struct pt_regs, regs[30]));
+  DEFINE(S_SP,			offsetof(struct pt_regs, sp));
+#ifdef CONFIG_AARCH32_EMULATION
+  DEFINE(S_COMPAT_SP,		offsetof(struct pt_regs, compat_sp));
+#endif
+  DEFINE(S_PSTATE,		offsetof(struct pt_regs, pstate));
+  DEFINE(S_PC,			offsetof(struct pt_regs, pc));
+  DEFINE(S_ORIG_X0,		offsetof(struct pt_regs, orig_x0));
+  DEFINE(S_SYSCALLNO,		offsetof(struct pt_regs, syscallno));
+  DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
+  BLANK();
+  DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id));
+  BLANK();
+  DEFINE(VMA_VM_MM,		offsetof(struct vm_area_struct, vm_mm));
+  DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags));
+  BLANK();
+  DEFINE(VM_EXEC,	       	VM_EXEC);
+  BLANK();
+  DEFINE(PAGE_SZ,	       	PAGE_SIZE);
+  BLANK();
+  DEFINE(PROC_INFO_SZ,		sizeof(struct proc_info_list));
+  DEFINE(PROCINFO_INITFUNC,	offsetof(struct proc_info_list, __cpu_flush));
+  BLANK();
+  DEFINE(DMA_BIDIRECTIONAL,	DMA_BIDIRECTIONAL);
+  DEFINE(DMA_TO_DEVICE,		DMA_TO_DEVICE);
+  DEFINE(DMA_FROM_DEVICE,	DMA_FROM_DEVICE);
+  BLANK();
+  DEFINE(CLOCK_REALTIME,	CLOCK_REALTIME);
+  DEFINE(CLOCK_MONOTONIC,	CLOCK_MONOTONIC);
+  DEFINE(CLOCK_REALTIME_RES,	MONOTONIC_RES_NSEC);
+  DEFINE(CLOCK_REALTIME_COARSE,	CLOCK_REALTIME_COARSE);
+  DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
+  DEFINE(CLOCK_COARSE_RES,	LOW_RES_NSEC);
+  DEFINE(NSEC_PER_SEC,		NSEC_PER_SEC);
+  BLANK();
+  DEFINE(VDSO_CS_CYCLE_LAST,	offsetof(struct vdso_data, cs_cycle_last));
+  DEFINE(VDSO_XTIME_CLK_SEC,	offsetof(struct vdso_data, xtime_clock_sec));
+  DEFINE(VDSO_XTIME_CLK_NSEC,	offsetof(struct vdso_data, xtime_clock_nsec));
+  DEFINE(VDSO_XTIME_CRS_SEC,	offsetof(struct vdso_data, xtime_coarse_sec));
+  DEFINE(VDSO_XTIME_CRS_NSEC,	offsetof(struct vdso_data, xtime_coarse_nsec));
+  DEFINE(VDSO_WTM_CLK_SEC,	offsetof(struct vdso_data, wtm_clock_sec));
+  DEFINE(VDSO_WTM_CLK_NSEC,	offsetof(struct vdso_data, wtm_clock_nsec));
+  DEFINE(VDSO_TB_SEQ_COUNT,	offsetof(struct vdso_data, tb_seq_count));
+  DEFINE(VDSO_CS_MULT,		offsetof(struct vdso_data, cs_mult));
+  DEFINE(VDSO_CS_SHIFT,		offsetof(struct vdso_data, cs_shift));
+  DEFINE(VDSO_TZ_MINWEST,	offsetof(struct vdso_data, tz_minuteswest));
+  DEFINE(VDSO_TZ_DSTTIME,	offsetof(struct vdso_data, tz_dsttime));
+  DEFINE(VDSO_USE_SYSCALL,	offsetof(struct vdso_data, use_syscall));
+  BLANK();
+  DEFINE(TVAL_TV_SEC,		offsetof(struct timeval, tv_sec));
+  DEFINE(TVAL_TV_USEC,		offsetof(struct timeval, tv_usec));
+  DEFINE(TSPEC_TV_SEC,		offsetof(struct timespec, tv_sec));
+  DEFINE(TSPEC_TV_NSEC,		offsetof(struct timespec, tv_nsec));
+  BLANK();
+  DEFINE(TZ_MINWEST,		offsetof(struct timezone, tz_minuteswest));
+  DEFINE(TZ_DSTTIME,		offsetof(struct timezone, tz_dsttime));
+  return 0;
+}
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
new file mode 100644
index 0000000..8957b82
--- /dev/null
+++ b/arch/arm64/mm/proc-macros.S
@@ -0,0 +1,55 @@
+/*
+ * Based on arch/arm/mm/proc-macros.S
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+
+/*
+ * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
+ */
+	.macro	vma_vm_mm, rd, rn
+	ldr	\rd, [\rn, #VMA_VM_MM]
+	.endm
+
+/*
+ * mmid - get context id from mm pointer (mm->context.id)
+ */
+	.macro	mmid, rd, rn
+	ldr	\rd, [\rn, #MM_CONTEXT_ID]
+	.endm
+
+/*
+ * dcache_line_size - get the minimum D-cache line size from the CTR register.
+ */
+	.macro	dcache_line_size, reg, tmp
+	mrs	\tmp, ctr_el0			// read CTR
+	lsr	\tmp, \tmp, #16
+	and	\tmp, \tmp, #0xf		// cache line size encoding
+	mov	\reg, #4			// bytes per word
+	lsl	\reg, \reg, \tmp		// actual cache line size
+	.endm
+
+/*
+ * icache_line_size - get the minimum I-cache line size from the CTR register.
+ */
+	.macro	icache_line_size, reg, tmp
+	mrs	\tmp, ctr_el0			// read CTR
+	and	\tmp, \tmp, #0xf		// cache line size encoding
+	mov	\reg, #4			// bytes per word
+	lsl	\reg, \reg, \tmp		// actual cache line size
+	.endm



From catalin.marinas at arm.com  Tue Aug 14 13:52:11 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:11 +0100
Subject: [PATCH v2 10/31] arm64: TLB maintenance functionality
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-11-git-send-email-catalin.marinas@arm.com>

This patch adds the TLB maintenance functions. There is no distinction
made between the I and D TLBs. TLB maintenance operations are
automatically broadcast between CPUs in hardware. The inner-shareable
operations are always present, even on UP systems.

NOTE: Large part of this patch to be dropped once Peter Z's generic
mmu_gather patches are merged.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/tlb.h      |  190 +++++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/tlbflush.h |  123 ++++++++++++++++++++++++
 arch/arm64/mm/tlb.S               |   71 ++++++++++++++
 3 files changed, 384 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/tlb.h
 create mode 100644 arch/arm64/include/asm/tlbflush.h
 create mode 100644 arch/arm64/mm/tlb.S

diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
new file mode 100644
index 0000000..654f096
--- /dev/null
+++ b/arch/arm64/include/asm/tlb.h
@@ -0,0 +1,190 @@
+/*
+ * Based on arch/arm/include/asm/tlb.h
+ *
+ * Copyright (C) 2002 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+#include <linux/pagemap.h>
+#include <linux/swap.h>
+
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+#define MMU_GATHER_BUNDLE	8
+
+/*
+ * TLB handling.  This allows us to remove pages from the page
+ * tables, and efficiently handle the TLB issues.
+ */
+struct mmu_gather {
+	struct mm_struct	*mm;
+	unsigned int		fullmm;
+	struct vm_area_struct	*vma;
+	unsigned long		range_start;
+	unsigned long		range_end;
+	unsigned int		nr;
+	unsigned int		max;
+	struct page		**pages;
+	struct page		*local[MMU_GATHER_BUNDLE];
+};
+
+/*
+ * This is unnecessarily complex.  There's three ways the TLB shootdown
+ * code is used:
+ *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
+ *     tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.
+ *  2. Unmapping all vmas.  See exit_mmap().
+ *     tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.  Additionally, page tables will be freed.
+ *  3. Unmapping argument pages.  See shift_arg_pages().
+ *     tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
+ *     tlb->vma will be NULL.
+ */
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+	if (tlb->fullmm || !tlb->vma)
+		flush_tlb_mm(tlb->mm);
+	else if (tlb->range_end > 0) {
+		flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
+		tlb->range_start = TASK_SIZE;
+		tlb->range_end = 0;
+	}
+}
+
+static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
+{
+	if (!tlb->fullmm) {
+		if (addr < tlb->range_start)
+			tlb->range_start = addr;
+		if (addr + PAGE_SIZE > tlb->range_end)
+			tlb->range_end = addr + PAGE_SIZE;
+	}
+}
+
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
+{
+	unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+
+	if (addr) {
+		tlb->pages = (void *)addr;
+		tlb->max = PAGE_SIZE / sizeof(struct page *);
+	}
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+	tlb_flush(tlb);
+	free_pages_and_swap_cache(tlb->pages, tlb->nr);
+	tlb->nr = 0;
+	if (tlb->pages == tlb->local)
+		__tlb_alloc_page(tlb);
+}
+
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm)
+{
+	tlb->mm = mm;
+	tlb->fullmm = fullmm;
+	tlb->vma = NULL;
+	tlb->max = ARRAY_SIZE(tlb->local);
+	tlb->pages = tlb->local;
+	tlb->nr = 0;
+	__tlb_alloc_page(tlb);
+}
+
+static inline void
+tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
+{
+	tlb_flush_mmu(tlb);
+
+	/* keep the page table cache within bounds */
+	check_pgt_cache();
+
+	if (tlb->pages != tlb->local)
+		free_pages((unsigned long)tlb->pages, 0);
+}
+
+/*
+ * Memorize the range for the TLB flush.
+ */
+static inline void
+tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
+{
+	tlb_add_flush(tlb, addr);
+}
+
+/*
+ * In the case of tlb vma handling, we can optimise these away in the
+ * case where we're doing a full MM flush.  When we're doing a munmap,
+ * the vmas are adjusted to only cover the region to be torn down.
+ */
+static inline void
+tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
+{
+	if (!tlb->fullmm) {
+		tlb->vma = vma;
+		tlb->range_start = TASK_SIZE;
+		tlb->range_end = 0;
+	}
+}
+
+static inline void
+tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
+{
+	if (!tlb->fullmm)
+		tlb_flush(tlb);
+}
+
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+	tlb->pages[tlb->nr++] = page;
+	VM_BUG_ON(tlb->nr > tlb->max);
+	return tlb->max - tlb->nr;
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+	if (!__tlb_remove_page(tlb, page))
+		tlb_flush_mmu(tlb);
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
+	unsigned long addr)
+{
+	pgtable_page_dtor(pte);
+	tlb_add_flush(tlb, addr);
+	tlb_remove_page(tlb, pte);
+}
+
+#ifndef CONFIG_ARM64_64K_PAGES
+static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
+				  unsigned long addr)
+{
+	tlb_add_flush(tlb, addr);
+	tlb_remove_page(tlb, virt_to_page(pmdp));
+}
+#endif
+
+#define pte_free_tlb(tlb, ptep, addr)	__pte_free_tlb(tlb, ptep, addr)
+#define pmd_free_tlb(tlb, pmdp, addr)	__pmd_free_tlb(tlb, pmdp, addr)
+#define pud_free_tlb(tlb, pudp, addr)	pud_free((tlb)->mm, pudp)
+
+#define tlb_migrate_finish(mm)		do { } while (0)
+
+#endif
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
new file mode 100644
index 0000000..615d131
--- /dev/null
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -0,0 +1,123 @@
+/*
+ * Based on arch/arm/include/asm/tlbflush.h
+ *
+ * Copyright (C) 1999-2003 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_TLBFLUSH_H
+#define __ASM_TLBFLUSH_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sched.h>
+#include <asm/cputype.h>
+
+extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
+extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
+
+extern struct cpu_tlb_fns cpu_tlb;
+
+/*
+ *	TLB Management
+ *	==============
+ *
+ *	The arch/arm/mm/tlb-*.S files implement these methods.
+ *
+ *	The TLB specific code is expected to perform whatever tests it
+ *	needs to determine if it should invalidate the TLB for each
+ *	call.  Start addresses are inclusive and end addresses are
+ *	exclusive; it is safe to round these addresses down.
+ *
+ *	flush_tlb_all()
+ *
+ *		Invalidate the entire TLB.
+ *
+ *	flush_tlb_mm(mm)
+ *
+ *		Invalidate all TLB entries in a particular address
+ *		space.
+ *		- mm	- mm_struct describing address space
+ *
+ *	flush_tlb_range(mm,start,end)
+ *
+ *		Invalidate a range of TLB entries in the specified
+ *		address space.
+ *		- mm	- mm_struct describing address space
+ *		- start - start address (may not be aligned)
+ *		- end	- end address (exclusive, may not be aligned)
+ *
+ *	flush_tlb_page(vaddr,vma)
+ *
+ *		Invalidate the specified page in the specified address range.
+ *		- vaddr - virtual address (may not be aligned)
+ *		- vma	- vma_struct describing address range
+ *
+ *	flush_kern_tlb_page(kaddr)
+ *
+ *		Invalidate the TLB entry for the specified page.  The address
+ *		will be in the kernels virtual memory space.  Current uses
+ *		only require the D-TLB to be invalidated.
+ *		- kaddr - Kernel virtual memory address
+ */
+static inline void flush_tlb_all(void)
+{
+	dsb();
+	asm("tlbi	vmalle1is");
+	dsb();
+	isb();
+}
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+	unsigned long asid = (unsigned long)ASID(mm) << 48;
+
+	dsb();
+	asm("tlbi	aside1is, %0" : : "r" (asid));
+	dsb();
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+				  unsigned long uaddr)
+{
+	unsigned long addr = uaddr >> 12 |
+		((unsigned long)ASID(vma->vm_mm) << 48);
+
+	dsb();
+	asm("tlbi	vae1is, %0" : : "r" (addr));
+	dsb();
+}
+
+/*
+ * Convert calls to our calling convention.
+ */
+#define flush_tlb_range(vma,start,end)	__cpu_flush_user_tlb_range(start,end,vma)
+#define flush_tlb_kernel_range(s,e)	__cpu_flush_kern_tlb_range(s,e)
+
+/*
+ * On AArch64, the cache coherency is handled via the set_pte_at() function.
+ */
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+	/*
+	 * set_pte() does not have a DSB, so make sure that the page table
+	 * write is visible.
+	 */
+	dsb();
+}
+
+#endif
+
+#endif
diff --git a/arch/arm64/mm/tlb.S b/arch/arm64/mm/tlb.S
new file mode 100644
index 0000000..8ae80a1
--- /dev/null
+++ b/arch/arm64/mm/tlb.S
@@ -0,0 +1,71 @@
+/*
+ * Based on arch/arm/mm/tlb.S
+ *
+ * Copyright (C) 1997-2002 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ * Written by Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+#include <asm/tlbflush.h>
+#include "proc-macros.S"
+
+/*
+ *	__cpu_flush_user_tlb_range(start, end, vma)
+ *
+ *	Invalidate a range of TLB entries in the specified address space.
+ *
+ *	- start - start address (may not be aligned)
+ *	- end   - end address (exclusive, may not be aligned)
+ *	- vma   - vma_struct describing address range
+ */
+ENTRY(__cpu_flush_user_tlb_range)
+	vma_vm_mm x3, x2			// get vma->vm_mm
+	mmid	x3, x3				// get vm_mm->context.id
+	dsb	sy
+	lsr	x0, x0, #12			// align address
+	lsr	x1, x1, #12
+	bfi	x0, x3, #48, #16		// start VA and ASID
+	bfi	x1, x3, #48, #16		// end VA and ASID
+1:	tlbi	vae1is, x0			// TLB invalidate by address and ASID
+	add	x0, x0, #1
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(__cpu_flush_user_tlb_range)
+
+/*
+ *	__cpu_flush_kern_tlb_range(start,end)
+ *
+ *	Invalidate a range of kernel TLB entries.
+ *
+ *	- start - start address (may not be aligned)
+ *	- end   - end address (exclusive, may not be aligned)
+ */
+ENTRY(__cpu_flush_kern_tlb_range)
+	dsb	sy
+	lsr	x0, x0, #12			// align address
+	lsr	x1, x1, #12
+1:	tlbi	vaae1is, x0			// TLB invalidate by address
+	add	x0, x0, #1
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	isb
+	ret
+ENDPROC(__cpu_flush_kern_tlb_range)



From catalin.marinas at arm.com  Tue Aug 14 13:52:25 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:25 +0100
Subject: [PATCH v2 24/31] arm64: Add support for
 /proc/sys/debug/exception-trace
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-25-git-send-email-catalin.marinas@arm.com>

This patch allows setting of the show_unhandled_signals variable via
/proc/sys/debug/exception-trace. The default value is currently 1
showing unhandled user faults (undefined instructions, data aborts) and
invalid signal stack frames.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 kernel/sysctl.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 87174ef..79dcb00 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -1544,7 +1544,7 @@ static struct ctl_table fs_table[] = {
 
 static struct ctl_table debug_table[] = {
 #if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) || \
-    defined(CONFIG_S390) || defined(CONFIG_TILE)
+    defined(CONFIG_S390) || defined(CONFIG_TILE) || defined(CONFIG_ARM64)
 	{
 		.procname	= "exception-trace",
 		.data		= &show_unhandled_signals,



From catalin.marinas at arm.com  Tue Aug 14 13:52:32 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:32 +0100
Subject: [PATCH v2 31/31] arm64: MAINTAINERS update
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-32-git-send-email-catalin.marinas@arm.com>

This patch updates the MAINTAINERS file for the AArch64 Linux kernel
port.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 MAINTAINERS |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 94b823f..6d7c5f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1204,6 +1204,12 @@ S:	Maintained
 F:	arch/arm/mach-pxa/z2.c
 F:	arch/arm/mach-pxa/include/mach/z2.h
 
+ARM64 PORT (AARCH64 ARCHITECTURE)
+M:	Catalin Marinas <catalin.marinas at arm.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm64/
+
 ASC7621 HARDWARE MONITOR DRIVER
 M:	George Joseph <george.joseph at fairview5.com>
 L:	lm-sensors at lm-sensors.org



From catalin.marinas at arm.com  Tue Aug 14 13:52:27 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:27 +0100
Subject: [PATCH v2 26/31] arm64: Miscellaneous library functions
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-27-git-send-email-catalin.marinas@arm.com>

From: Marc Zyngier <marc.zyngier at arm.com>

This patch adds udelay, memory and bit operations together with the
ksyms exports.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/bitops.h  |   74 ++++++++++++++++++++++++++++
 arch/arm64/include/asm/syscall.h |  101 ++++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/arm64ksyms.c   |   55 ++++++++++++++++++++
 arch/arm64/lib/Makefile          |    5 ++
 arch/arm64/lib/bitops.c          |   25 +++++++++
 arch/arm64/lib/clear_page.S      |   39 +++++++++++++++
 arch/arm64/lib/copy_page.S       |   46 +++++++++++++++++
 arch/arm64/lib/delay.c           |   55 ++++++++++++++++++++
 8 files changed, 400 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/bitops.h
 create mode 100644 arch/arm64/include/asm/syscall.h
 create mode 100644 arch/arm64/kernel/arm64ksyms.c
 create mode 100644 arch/arm64/lib/Makefile
 create mode 100644 arch/arm64/lib/bitops.c
 create mode 100644 arch/arm64/lib/clear_page.S
 create mode 100644 arch/arm64/lib/copy_page.S
 create mode 100644 arch/arm64/lib/delay.c

diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h
new file mode 100644
index 0000000..67df4d2
--- /dev/null
+++ b/arch/arm64/include/asm/bitops.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_BITOPS_H
+#define __ASM_BITOPS_H
+
+#include <linux/compiler.h>
+
+#include <asm/barrier.h>
+
+/*
+ * clear_bit may not imply a memory barrier
+ */
+#ifndef smp_mb__before_clear_bit
+#define smp_mb__before_clear_bit()	smp_mb()
+#define smp_mb__after_clear_bit()	smp_mb()
+#endif
+
+/*
+ * Use compiler builtins for simple inline operations.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+	return __builtin_ffsl(word) - 1;
+}
+
+static inline int ffs(int x)
+{
+	return __builtin_ffs(x);
+}
+
+static inline unsigned long __fls(unsigned long word)
+{
+	return BITS_PER_LONG - 1 - __builtin_clzl(word);
+}
+
+static inline int fls(int x)
+{
+	return x ? sizeof(x) * BITS_PER_BYTE - __builtin_clz(x) : 0;
+}
+
+/*
+ * Mainly use the generic routines for now.
+ */
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
+
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/lock.h>
+
+#include <asm-generic/bitops/atomic.h>
+#include <asm-generic/bitops/non-atomic.h>
+#include <asm-generic/bitops/le.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+
+#endif /* __ASM_BITOPS_H */
diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/syscall.h
new file mode 100644
index 0000000..89c047f
--- /dev/null
+++ b/arch/arm64/include/asm/syscall.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include <linux/err.h>
+
+
+static inline int syscall_get_nr(struct task_struct *task,
+				 struct pt_regs *regs)
+{
+	return regs->syscallno;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+				    struct pt_regs *regs)
+{
+	regs->regs[0] = regs->orig_x0;
+}
+
+
+static inline long syscall_get_error(struct task_struct *task,
+				     struct pt_regs *regs)
+{
+	unsigned long error = regs->regs[0];
+	return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+					    struct pt_regs *regs)
+{
+	return regs->regs[0];
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+					    struct pt_regs *regs,
+					    int error, long val)
+{
+	regs->regs[0] = (long) error ? error : val;
+}
+
+#define SYSCALL_MAX_ARGS 6
+
+static inline void syscall_get_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+		unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		memset(args_bad, 0, n_bad * sizeof(args[0]));
+	}
+
+	if (i == 0) {
+		args[0] = regs->orig_x0;
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(args, &regs->regs[i], n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 const unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		n = SYSCALL_MAX_ARGS - i;
+	}
+
+	if (i == 0) {
+		regs->orig_x0 = args[0];
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(&regs->regs[i], args, n * sizeof(args[0]));
+}
+
+#endif	/* __ASM_SYSCALL_H */
diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
new file mode 100644
index 0000000..4631573
--- /dev/null
+++ b/arch/arm64/kernel/arm64ksyms.c
@@ -0,0 +1,55 @@
+/*
+ * Based on arch/arm/kernel/armksyms.c
+ *
+ * Copyright (C) 2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/cryptohash.h>
+#include <linux/delay.h>
+#include <linux/in6.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#include <asm/checksum.h>
+
+	/* user mem (segment) */
+EXPORT_SYMBOL(__strnlen_user);
+EXPORT_SYMBOL(__strncpy_from_user);
+
+EXPORT_SYMBOL(copy_page);
+
+EXPORT_SYMBOL(__copy_from_user);
+EXPORT_SYMBOL(__copy_to_user);
+EXPORT_SYMBOL(__clear_user);
+
+EXPORT_SYMBOL(__get_user_1);
+EXPORT_SYMBOL(__get_user_2);
+EXPORT_SYMBOL(__get_user_4);
+
+EXPORT_SYMBOL(__put_user_1);
+EXPORT_SYMBOL(__put_user_2);
+EXPORT_SYMBOL(__put_user_4);
+EXPORT_SYMBOL(__put_user_8);
+
+	/* bitops */
+EXPORT_SYMBOL(__atomic_hash);
+
+	/* physical memory */
+EXPORT_SYMBOL(memstart_addr);
diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile
new file mode 100644
index 0000000..ae71bae
--- /dev/null
+++ b/arch/arm64/lib/Makefile
@@ -0,0 +1,5 @@
+lib-y		:= bitops.o delay.o					\
+		   strncpy_from_user.o strnlen_user.o			\
+		   clear_user.o getuser.o putuser.o			\
+		   copy_from_user.o copy_to_user.o copy_in_user.o	\
+		   copy_page.o clear_page.o
diff --git a/arch/arm64/lib/bitops.c b/arch/arm64/lib/bitops.c
new file mode 100644
index 0000000..aa4965e
--- /dev/null
+++ b/arch/arm64/lib/bitops.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/atomic.h>
+
+#ifdef CONFIG_SMP
+arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
+       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
+};
+#endif
diff --git a/arch/arm64/lib/clear_page.S b/arch/arm64/lib/clear_page.S
new file mode 100644
index 0000000..ef08e90
--- /dev/null
+++ b/arch/arm64/lib/clear_page.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/assembler.h>
+#include <asm/page.h>
+
+/*
+ * Clear page @dest
+ *
+ * Parameters:
+ *	x0 - dest
+ */
+ENTRY(clear_page)
+	mrs	x1, dczid_el0
+	and	w1, w1, #0xf
+	mov	x2, #4
+	lsl	x1, x2, x1
+
+1:	dc	zva, x0
+	add	x0, x0, x1
+	tst	x0, #(PAGE_SIZE - 1)
+	b.ne	1b
+	ret
+ENDPROC(clear_page)
diff --git a/arch/arm64/lib/copy_page.S b/arch/arm64/lib/copy_page.S
new file mode 100644
index 0000000..512b9a7
--- /dev/null
+++ b/arch/arm64/lib/copy_page.S
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/assembler.h>
+#include <asm/page.h>
+
+/*
+ * Copy a page from src to dest (both are page aligned)
+ *
+ * Parameters:
+ *	x0 - dest
+ *	x1 - src
+ */
+ENTRY(copy_page)
+	/* Assume cache line size is 64 bytes. */
+	prfm	pldl1strm, [x1, #64]
+1:	ldp	x2, x3, [x1]
+	ldp	x4, x5, [x1, #16]
+	ldp	x6, x7, [x1, #32]
+	ldp	x8, x9, [x1, #48]
+	add	x1, x1, #64
+	prfm	pldl1strm, [x1, #64]
+	stnp	x2, x3, [x0]
+	stnp	x4, x5, [x0, #16]
+	stnp	x6, x7, [x0, #32]
+	stnp	x8, x9, [x0, #48]
+	add	x0, x0, #64
+	tst	x1, #(PAGE_SIZE - 1)
+	b.ne	1b
+	ret
+ENDPROC(copy_page)
diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c
new file mode 100644
index 0000000..dad4ec9
--- /dev/null
+++ b/arch/arm64/lib/delay.c
@@ -0,0 +1,55 @@
+/*
+ * Delay loops based on the OpenRISC implementation.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/timex.h>
+
+void __delay(unsigned long cycles)
+{
+	cycles_t start = get_cycles();
+
+	while ((get_cycles() - start) < cycles)
+		cpu_relax();
+}
+EXPORT_SYMBOL(__delay);
+
+inline void __const_udelay(unsigned long xloops)
+{
+	unsigned long loops;
+
+	loops = xloops * loops_per_jiffy * HZ;
+	__delay(loops >> 32);
+}
+EXPORT_SYMBOL(__const_udelay);
+
+void __udelay(unsigned long usecs)
+{
+	__const_udelay(usecs * 0x10C7UL); /* 2**32 / 1000000 (rounded up) */
+}
+EXPORT_SYMBOL(__udelay);
+
+void __ndelay(unsigned long nsecs)
+{
+	__const_udelay(nsecs * 0x5UL); /* 2**32 / 1000000000 (rounded up) */
+}
+EXPORT_SYMBOL(__ndelay);



From catalin.marinas at arm.com  Tue Aug 14 13:52:23 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:23 +0100
Subject: [PATCH v2 22/31] arm64: Floating point and SIMD
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-23-git-send-email-catalin.marinas@arm.com>

This patch adds support for FP/ASIMD register bank saving and restoring
during context switch and FP exception handling to generate SIGFPE.
There are 32 128-bit registers and the context switching is currently
done non-lazily. Benchmarks on real hardware are required before
implementing lazy FP state saving/restoring.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/fpsimd.h  |   64 +++++++++++++++++++++++
 arch/arm64/kernel/entry-fpsimd.S |   80 ++++++++++++++++++++++++++++
 arch/arm64/kernel/fpsimd.c       |  106 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 250 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/fpsimd.h
 create mode 100644 arch/arm64/kernel/entry-fpsimd.S
 create mode 100644 arch/arm64/kernel/fpsimd.c

diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
new file mode 100644
index 0000000..7ea4711
--- /dev/null
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_FP_H
+#define __ASM_FP_H
+
+#include <asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * FP/SIMD storage area has:
+ *  - FPSR and FPCR
+ *  - 32 128-bit data registers
+ *
+ * Note that user_fp forms a prefix of this structure, which is relied
+ * upon in the ptrace FP/SIMD accessors. struct user_fpsimd_state must
+ * form a prefix of struct fpsimd_state.
+ */
+struct fpsimd_state {
+	union {
+		struct user_fpsimd_state user_fpsimd;
+		struct {
+			__uint128_t vregs[32];
+			u32 fpsr;
+			u32 fpcr;
+		};
+	};
+};
+
+#if defined(__KERNEL__) && defined(CONFIG_AARCH32_EMULATION)
+/* Masks for extracting the FPSR and FPCR from the FPSCR */
+#define VFP_FPSCR_STAT_MASK	0xf800009f
+#define VFP_FPSCR_CTRL_MASK	0x07f79f00
+/*
+ * The VFP state has 32x64-bit registers and a single 32-bit
+ * control/status register.
+ */
+#define VFP_STATE_SIZE		((32 * 8) + 4)
+#endif
+
+struct task_struct;
+
+extern void fpsimd_save_state(struct fpsimd_state *state);
+extern void fpsimd_load_state(struct fpsimd_state *state);
+
+extern void fpsimd_thread_switch(struct task_struct *next);
+extern void fpsimd_flush_thread(void);
+
+#endif
+
+#endif
diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S
new file mode 100644
index 0000000..17988a6
--- /dev/null
+++ b/arch/arm64/kernel/entry-fpsimd.S
@@ -0,0 +1,80 @@
+/*
+ * FP/SIMD state saving and restoring
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+/*
+ * Save the FP registers.
+ *
+ * x0 - pointer to struct fpsimd_state
+ */
+ENTRY(fpsimd_save_state)
+	stp	q0, q1, [x0, #16 * 0]
+	stp	q2, q3, [x0, #16 * 2]
+	stp	q4, q5, [x0, #16 * 4]
+	stp	q6, q7, [x0, #16 * 6]
+	stp	q8, q9, [x0, #16 * 8]
+	stp	q10, q11, [x0, #16 * 10]
+	stp	q12, q13, [x0, #16 * 12]
+	stp	q14, q15, [x0, #16 * 14]
+	stp	q16, q17, [x0, #16 * 16]
+	stp	q18, q19, [x0, #16 * 18]
+	stp	q20, q21, [x0, #16 * 20]
+	stp	q22, q23, [x0, #16 * 22]
+	stp	q24, q25, [x0, #16 * 24]
+	stp	q26, q27, [x0, #16 * 26]
+	stp	q28, q29, [x0, #16 * 28]
+	stp	q30, q31, [x0, #16 * 30]!
+	mrs	x8, fpsr
+	str	w8, [x0, #16 * 2]
+	mrs	x8, fpcr
+	str	w8, [x0, #16 * 2 + 4]
+	ret
+ENDPROC(fpsimd_save_state)
+
+/*
+ * Load the FP registers.
+ *
+ * x0 - pointer to struct fpsimd_state
+ */
+ENTRY(fpsimd_load_state)
+	ldp	q0, q1, [x0, #16 * 0]
+	ldp	q2, q3, [x0, #16 * 2]
+	ldp	q4, q5, [x0, #16 * 4]
+	ldp	q6, q7, [x0, #16 * 6]
+	ldp	q8, q9, [x0, #16 * 8]
+	ldp	q10, q11, [x0, #16 * 10]
+	ldp	q12, q13, [x0, #16 * 12]
+	ldp	q14, q15, [x0, #16 * 14]
+	ldp	q16, q17, [x0, #16 * 16]
+	ldp	q18, q19, [x0, #16 * 18]
+	ldp	q20, q21, [x0, #16 * 20]
+	ldp	q22, q23, [x0, #16 * 22]
+	ldp	q24, q25, [x0, #16 * 24]
+	ldp	q26, q27, [x0, #16 * 26]
+	ldp	q28, q29, [x0, #16 * 28]
+	ldp	q30, q31, [x0, #16 * 30]!
+	ldr	w8, [x0, #16 * 2]
+	ldr	w9, [x0, #16 * 2 + 4]
+	msr	fpsr, x8
+	msr	fpcr, x9
+	ret
+ENDPROC(fpsimd_load_state)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
new file mode 100644
index 0000000..e8b8357
--- /dev/null
+++ b/arch/arm64/kernel/fpsimd.c
@@ -0,0 +1,106 @@
+/*
+ * FP/SIMD context switching and fault handling
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+
+#include <asm/fpsimd.h>
+#include <asm/cputype.h>
+
+#define FPEXC_IOF	(1 << 0)
+#define FPEXC_DZF	(1 << 1)
+#define FPEXC_OFF	(1 << 2)
+#define FPEXC_UFF	(1 << 3)
+#define FPEXC_IXF	(1 << 4)
+#define FPEXC_IDF	(1 << 7)
+
+/*
+ * Trapped FP/ASIMD access.
+ */
+void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs)
+{
+	/* TODO: implement lazy context saving/restoring */
+	WARN_ON(1);
+}
+
+/*
+ * Raise a SIGFPE for the current process.
+ */
+void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
+{
+	siginfo_t info;
+	unsigned int si_code = 0;
+
+	if (esr & FPEXC_IOF)
+		si_code = FPE_FLTINV;
+	else if (esr & FPEXC_DZF)
+		si_code = FPE_FLTDIV;
+	else if (esr & FPEXC_OFF)
+		si_code = FPE_FLTOVF;
+	else if (esr & FPEXC_UFF)
+		si_code = FPE_FLTUND;
+	else if (esr & FPEXC_IXF)
+		si_code = FPE_FLTRES;
+
+	memset(&info, 0, sizeof(info));
+	info.si_signo = SIGFPE;
+	info.si_code = si_code;
+	info.si_addr = (void __user *)instruction_pointer(regs);
+
+	send_sig_info(SIGFPE, &info, current);
+}
+
+void fpsimd_thread_switch(struct task_struct *next)
+{
+	/* check if not kernel threads */
+	if (current->mm)
+		fpsimd_save_state(&current->thread.fpsimd_state);
+	if (next->mm)
+		fpsimd_load_state(&next->thread.fpsimd_state);
+}
+
+void fpsimd_flush_thread(void)
+{
+	memset(&current->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
+	fpsimd_load_state(&current->thread.fpsimd_state);
+}
+
+/*
+ * FP/SIMD support code initialisation.
+ */
+static int __init fpsimd_init(void)
+{
+	u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
+
+	if (pfr & (0xf << 16)) {
+		pr_notice("Floating-point is not implemented\n");
+		return 0;
+	}
+	elf_hwcap |= HWCAP_FP;
+
+	if (pfr & (0xf << 20))
+		pr_notice("Advanced SIMD is not implemented\n");
+	else
+		elf_hwcap |= HWCAP_ASIMD;
+
+	return 0;
+}
+late_initcall(fpsimd_init);



From catalin.marinas at arm.com  Tue Aug 14 13:52:30 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:30 +0100
Subject: [PATCH v2 29/31] arm64: Miscellaneous header files
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-30-git-send-email-catalin.marinas@arm.com>

This patch introduces a few AArch64-specific header files together with
Kbuild entries for generic headers.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/Kbuild        |   51 ++++++++++
 arch/arm64/include/asm/barrier.h     |   52 ++++++++++
 arch/arm64/include/asm/bitsperlong.h |   23 +++++
 arch/arm64/include/asm/byteorder.h   |   21 ++++
 arch/arm64/include/asm/cmpxchg.h     |  180 ++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/compiler.h    |   30 ++++++
 arch/arm64/include/asm/exception.h   |   23 +++++
 arch/arm64/include/asm/exec.h        |   23 +++++
 arch/arm64/include/asm/fcntl.h       |   29 ++++++
 arch/arm64/include/asm/system_misc.h |   54 ++++++++++
 10 files changed, 486 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/Kbuild
 create mode 100644 arch/arm64/include/asm/barrier.h
 create mode 100644 arch/arm64/include/asm/bitsperlong.h
 create mode 100644 arch/arm64/include/asm/byteorder.h
 create mode 100644 arch/arm64/include/asm/cmpxchg.h
 create mode 100644 arch/arm64/include/asm/compiler.h
 create mode 100644 arch/arm64/include/asm/exception.h
 create mode 100644 arch/arm64/include/asm/exec.h
 create mode 100644 arch/arm64/include/asm/fcntl.h
 create mode 100644 arch/arm64/include/asm/system_misc.h

diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
new file mode 100644
index 0000000..35924a5
--- /dev/null
+++ b/arch/arm64/include/asm/Kbuild
@@ -0,0 +1,51 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += hwcap.h
+
+generic-y += bug.h
+generic-y += bugs.h
+generic-y += checksum.h
+generic-y += cputime.h
+generic-y += current.h
+generic-y += delay.h
+generic-y += div64.h
+generic-y += dma.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += ftrace.h
+generic-y += hw_irq.h
+generic-y += ioctl.h
+generic-y += ioctls.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += linkage.h
+generic-y += local.h
+generic-y += local64.h
+generic-y += mman.h
+generic-y += msgbuf.h
+generic-y += mutex.h
+generic-y += pci.h
+generic-y += percpu.h
+generic-y += poll.h
+generic-y += posix_types.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += sections.h
+generic-y += segment.h
+generic-y += sembuf.h
+generic-y += serial.h
+generic-y += shmbuf.h
+generic-y += sizes.h
+generic-y += socket.h
+generic-y += sockios.h
+generic-y += string.h
+generic-y += switch_to.h
+generic-y += swab.h
+generic-y += termbits.h
+generic-y += termios.h
+generic-y += topology.h
+generic-y += types.h
+generic-y += unaligned.h
+generic-y += user.h
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
new file mode 100644
index 0000000..d4a6333
--- /dev/null
+++ b/arch/arm64/include/asm/barrier.h
@@ -0,0 +1,52 @@
+/*
+ * Based on arch/arm/include/asm/barrier.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+
+#define sev()		asm volatile("sev" : : : "memory")
+#define wfe()		asm volatile("wfe" : : : "memory")
+#define wfi()		asm volatile("wfi" : : : "memory")
+
+#define isb()		asm volatile("isb" : : : "memory")
+#define dsb()		asm volatile("dsb sy" : : : "memory")
+
+#define mb()		dsb()
+#define rmb()		asm volatile("dsb ld" : : : "memory")
+#define wmb()		asm volatile("dsb st" : : : "memory")
+
+#ifndef CONFIG_SMP
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#else
+#define smp_mb()	asm volatile("dmb ish" : : : "memory")
+#define smp_rmb()	asm volatile("dmb ishld" : : : "memory")
+#define smp_wmb()	asm volatile("dmb ishst" : : : "memory")
+#endif
+
+#define read_barrier_depends()		do { } while(0)
+#define smp_read_barrier_depends()	do { } while(0)
+
+#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
+#define nop()		asm volatile("nop");
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* __ASM_BARRIER_H */
diff --git a/arch/arm64/include/asm/bitsperlong.h b/arch/arm64/include/asm/bitsperlong.h
new file mode 100644
index 0000000..fce9c29
--- /dev/null
+++ b/arch/arm64/include/asm/bitsperlong.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_BITSPERLONG_H
+#define __ASM_BITSPERLONG_H
+
+#define __BITS_PER_LONG 64
+
+#include <asm-generic/bitsperlong.h>
+
+#endif	/* __ASM_BITSPERLONG_H */
diff --git a/arch/arm64/include/asm/byteorder.h b/arch/arm64/include/asm/byteorder.h
new file mode 100644
index 0000000..2b92046
--- /dev/null
+++ b/arch/arm64/include/asm/byteorder.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_BYTEORDER_H
+#define __ASM_BYTEORDER_H
+
+#include <linux/byteorder/little_endian.h>
+
+#endif	/* __ASM_BYTEORDER_H */
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
new file mode 100644
index 0000000..dc50de7
--- /dev/null
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -0,0 +1,180 @@
+/*
+ * Based on arch/arm/include/asm/cmpxchg.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret, tmp;
+
+	switch (size) {
+	case 1:
+		asm volatile("//	__xchg1\n"
+		"1:	ldaxrb	%w0, [%3]\n"
+		"	stlxrb	%w1, %w2, [%3]\n"
+		"	cbnz	%w1, 1b\n"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 2:
+		asm volatile("//	__xchg2\n"
+		"1:	ldaxrh	%w0, [%3]\n"
+		"	stlxrh	%w1, %w2, [%3]\n"
+		"	cbnz	%w1, 1b\n"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 4:
+		asm volatile("//	__xchg4\n"
+		"1:	ldaxr	%w0, [%3]\n"
+		"	stlxr	%w1, %w2, [%3]\n"
+		"	cbnz	%w1, 1b\n"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 8:
+		asm volatile("//	__xchg8\n"
+		"1:	ldaxr	%0, [%3]\n"
+		"	stlxr	%w1, %2, [%3]\n"
+		"	cbnz	%w1, 1b\n"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	default:
+		__bad_xchg(ptr, size), ret = 0;
+		break;
+	}
+
+	return ret;
+}
+
+#define xchg(ptr,x) \
+	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+/*
+ * cmpxchg operations.
+ */
+extern void __bad_cmpxchg(volatile void *ptr, int size);
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+				      unsigned long new, int size)
+{
+	unsigned long oldval, res;
+
+	switch (size) {
+	case 1:
+		do {
+			asm volatile("// __cmpxchg1\n"
+			"	ldxrb	%w1, [%2]\n"
+			"	mov	%w0, #0\n"
+			"	cmp	%w1, %w3\n"
+			"	b.ne	1f\n"
+			"	stxrb	%w0, %w4, [%2]\n"
+			"1:\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "cc");
+		} while (res);
+		break;
+
+	case 2:
+		do {
+			asm volatile("// __cmpxchg2\n"
+			"	ldxrh	%w1, [%2]\n"
+			"	mov	%w0, #0\n"
+			"	cmp	%w1, %w3\n"
+			"	b.ne	1f\n"
+			"	stxrh	%w0, %w4, [%2]\n"
+			"1:\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+
+	case 4:
+		do {
+			asm volatile("// __cmpxchg4\n"
+			"	ldxr	%w1, [%2]\n"
+			"	mov	%w0, #0\n"
+			"	cmp	%w1, %w3\n"
+			"	b.ne	1f\n"
+			"	stxr	%w0, %w4, [%2]\n"
+			"1:\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "cc");
+		} while (res);
+		break;
+
+	case 8:
+		do {
+			asm volatile("// __cmpxchg8\n"
+			"	ldxr	%1, [%2]\n"
+			"	mov	%w0, #0\n"
+			"	cmp	%1, %3\n"
+			"	b.ne	1f\n"
+			"	stxr	%w0, %4, [%2]\n"
+			"1:\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "cc");
+		} while (res);
+		break;
+
+	default:
+		__bad_cmpxchg(ptr, size);
+		oldval = 0;
+	}
+
+	return oldval;
+}
+
+static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
+					 unsigned long new, int size)
+{
+	unsigned long ret;
+
+	smp_mb();
+	ret = __cmpxchg(ptr, old, new, size);
+	smp_mb();
+
+	return ret;
+}
+
+#define cmpxchg(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
+					  (unsigned long)(o),		\
+					  (unsigned long)(n),		\
+					  sizeof(*(ptr))))
+
+#define cmpxchg_local(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg((ptr),				\
+				       (unsigned long)(o),		\
+				       (unsigned long)(n),		\
+				       sizeof(*(ptr))))
+
+#endif	/* __ASM_CMPXCHG_H */
diff --git a/arch/arm64/include/asm/compiler.h b/arch/arm64/include/asm/compiler.h
new file mode 100644
index 0000000..ee35fd0
--- /dev/null
+++ b/arch/arm64/include/asm/compiler.h
@@ -0,0 +1,30 @@
+/*
+ * Based on arch/arm/include/asm/compiler.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_COMPILER_H
+#define __ASM_COMPILER_H
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust the
+ * compiler from one version to another so a bit of paranoia won't hurt.  This
+ * string is meant to be concatenated with the inline asm string and will
+ * cause compilation to stop on mismatch.  (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#endif	/* __ASM_COMPILER_H */
diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h
new file mode 100644
index 0000000..ac63519
--- /dev/null
+++ b/arch/arm64/include/asm/exception.h
@@ -0,0 +1,23 @@
+/*
+ * Based on arch/arm/include/asm/exception.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_EXCEPTION_H
+#define __ASM_EXCEPTION_H
+
+#define __exception	__attribute__((section(".exception.text")))
+
+#endif	/* __ASM_EXCEPTION_H */
diff --git a/arch/arm64/include/asm/exec.h b/arch/arm64/include/asm/exec.h
new file mode 100644
index 0000000..db0563c
--- /dev/null
+++ b/arch/arm64/include/asm/exec.h
@@ -0,0 +1,23 @@
+/*
+ * Based on arch/arm/include/asm/exec.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_EXEC_H
+#define __ASM_EXEC_H
+
+extern unsigned long arch_align_stack(unsigned long sp);
+
+#endif	/* __ASM_EXEC_H */
diff --git a/arch/arm64/include/asm/fcntl.h b/arch/arm64/include/asm/fcntl.h
new file mode 100644
index 0000000..cd2e630
--- /dev/null
+++ b/arch/arm64/include/asm/fcntl.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_FCNTL_H
+#define __ASM_FCNTL_H
+
+/*
+ * Using our own definitions for AArch32 (compat) support.
+ */
+#define O_DIRECTORY	 040000	/* must be a directory */
+#define O_NOFOLLOW	0100000	/* don't follow links */
+#define O_DIRECT	0200000	/* direct disk access hint - currently ignored */
+#define O_LARGEFILE	0400000
+
+#include <asm-generic/fcntl.h>
+
+#endif
diff --git a/arch/arm64/include/asm/system_misc.h b/arch/arm64/include/asm/system_misc.h
new file mode 100644
index 0000000..95e4072
--- /dev/null
+++ b/arch/arm64/include/asm/system_misc.h
@@ -0,0 +1,54 @@
+/*
+ * Based on arch/arm/include/asm/system_misc.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SYSTEM_MISC_H
+#define __ASM_SYSTEM_MISC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/irqflags.h>
+
+struct pt_regs;
+
+void die(const char *msg, struct pt_regs *regs, int err);
+
+struct siginfo;
+void arm64_notify_die(const char *str, struct pt_regs *regs,
+		      struct siginfo *info, int err);
+
+void hook_debug_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
+					     struct pt_regs *),
+			   int sig, int code, const char *name);
+
+struct mm_struct;
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+extern void __show_regs(struct pt_regs *);
+
+void soft_restart(unsigned long);
+extern void (*pm_restart)(const char *cmd);
+
+#define UDBG_UNDEFINED	(1 << 0)
+#define UDBG_SYSCALL	(1 << 1)
+#define UDBG_BADABORT	(1 << 2)
+#define UDBG_SEGV	(1 << 3)
+#define UDBG_BUS	(1 << 4)
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* __ASM_SYSTEM_MISC_H */



From catalin.marinas at arm.com  Tue Aug 14 13:52:28 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:28 +0100
Subject: [PATCH v2 27/31] arm64: Loadable modules
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-28-git-send-email-catalin.marinas@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds support for loadable modules. Loadable modules are
loaded 64MB below the kernel image due to branch relocation restrictions
(see Documentation/arm64/memory.txt).

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/module.h |   23 ++
 arch/arm64/kernel/module.c      |  456 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 479 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/module.h
 create mode 100644 arch/arm64/kernel/module.c

diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h
new file mode 100644
index 0000000..e80e232
--- /dev/null
+++ b/arch/arm64/include/asm/module.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_MODULE_H
+#define __ASM_MODULE_H
+
+#include <asm-generic/module.h>
+
+#define MODULE_ARCH_VERMAGIC	"aarch64"
+
+#endif /* __ASM_MODULE_H */
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
new file mode 100644
index 0000000..ca0e3d5
--- /dev/null
+++ b/arch/arm64/kernel/module.c
@@ -0,0 +1,456 @@
+/*
+ * AArch64 loadable module support.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/elf.h>
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/moduleloader.h>
+#include <linux/vmalloc.h>
+
+void *module_alloc(unsigned long size)
+{
+	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+				    GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
+				    __builtin_return_address(0));
+}
+
+enum aarch64_reloc_op {
+	RELOC_OP_NONE,
+	RELOC_OP_ABS,
+	RELOC_OP_PREL,
+	RELOC_OP_PAGE,
+};
+
+static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val)
+{
+	switch (reloc_op) {
+	case RELOC_OP_ABS:
+		return val;
+	case RELOC_OP_PREL:
+		return val - (u64)place;
+	case RELOC_OP_PAGE:
+		return (val & ~0xfff) - ((u64)place & ~0xfff);
+	case RELOC_OP_NONE:
+		return 0;
+	}
+
+	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
+	return 0;
+}
+
+static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
+{
+	u64 imm_mask = (1 << len) - 1;
+	s64 sval = do_reloc(op, place, val);
+
+	switch (len) {
+	case 16:
+		*(s16 *)place = sval;
+		break;
+	case 32:
+		*(s32 *)place = sval;
+		break;
+	case 64:
+		*(s64 *)place = sval;
+		break;
+	default:
+		pr_err("Invalid length (%d) for data relocation\n", len);
+		return 0;
+	}
+
+	/*
+	 * Extract the upper value bits (including the sign bit) and
+	 * shift them to bit 0.
+	 */
+	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
+
+	/*
+	 * Overflow has occurred if the value is not representable in
+	 * len bits (i.e the bottom len bits are not sign-extended and
+	 * the top bits are not all zero).
+	 */
+	if ((u64)(sval + 1) > 2)
+		return -ERANGE;
+
+	return 0;
+}
+
+enum aarch64_imm_type {
+	INSN_IMM_MOVNZ,
+	INSN_IMM_MOVK,
+	INSN_IMM_ADR,
+	INSN_IMM_26,
+	INSN_IMM_19,
+	INSN_IMM_16,
+	INSN_IMM_14,
+	INSN_IMM_12,
+	INSN_IMM_9,
+};
+
+static u32 encode_insn_immediate(enum aarch64_imm_type type, u32 insn, u64 imm)
+{
+	u32 immlo, immhi, lomask, himask, mask;
+	int shift;
+
+	switch (type) {
+	case INSN_IMM_MOVNZ:
+		/*
+		 * For signed MOVW relocations, we have to manipulate the
+		 * instruction encoding depending on whether or not the
+		 * immediate is less than zero.
+		 */
+		insn &= ~(3 << 29);
+		if ((s64)imm >= 0) {
+			/* >=0: Set the instruction to MOVZ (opcode 10b). */
+			insn |= 2 << 29;
+		} else {
+			/*
+			 * <0: Set the instruction to MOVN (opcode 00b).
+			 *     Since we've masked the opcode already, we
+			 *     don't need to do anything other than
+			 *     inverting the new immediate field.
+			 */
+			imm = ~imm;
+		}
+	case INSN_IMM_MOVK:
+		mask = BIT(16) - 1;
+		shift = 5;
+		break;
+	case INSN_IMM_ADR:
+		lomask = 0x3;
+		himask = 0x7ffff;
+		immlo = imm & lomask;
+		imm >>= 2;
+		immhi = imm & himask;
+		imm = (immlo << 24) | (immhi);
+		mask = (lomask << 24) | (himask);
+		shift = 5;
+		break;
+	case INSN_IMM_26:
+		mask = BIT(26) - 1;
+		shift = 0;
+		break;
+	case INSN_IMM_19:
+		mask = BIT(19) - 1;
+		shift = 5;
+		break;
+	case INSN_IMM_16:
+		mask = BIT(16) - 1;
+		shift = 5;
+		break;
+	case INSN_IMM_14:
+		mask = BIT(14) - 1;
+		shift = 5;
+		break;
+	case INSN_IMM_12:
+		mask = BIT(12) - 1;
+		shift = 10;
+		break;
+	case INSN_IMM_9:
+		mask = BIT(9) - 1;
+		shift = 12;
+		break;
+	default:
+		pr_err("encode_insn_immediate: unknown immediate encoding %d\n",
+			type);
+		return 0;
+	}
+
+	/* Update the immediate field. */
+	insn &= ~(mask << shift);
+	insn |= (imm & mask) << shift;
+
+	return insn;
+}
+
+static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val,
+			   int lsb, enum aarch64_imm_type imm_type)
+{
+	u64 imm, limit = 0;
+	s64 sval;
+	u32 insn = *(u32 *)place;
+
+	sval = do_reloc(op, place, val);
+	sval >>= lsb;
+	imm = sval & 0xffff;
+
+	/* Update the instruction with the new encoding. */
+	*(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
+
+	/* Shift out the immediate field. */
+	sval >>= 16;
+
+	/*
+	 * For unsigned immediates, the overflow check is straightforward.
+	 * For signed immediates, the sign bit is actually the bit past the
+	 * most significant bit of the field.
+	 * The INSN_IMM_16 immediate type is unsigned.
+	 */
+	if (imm_type != INSN_IMM_16) {
+		sval++;
+		limit++;
+	}
+
+	/* Check the upper bits depending on the sign of the immediate. */
+	if ((u64)sval > limit)
+		return -ERANGE;
+
+	return 0;
+}
+
+static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val,
+			  int lsb, int len, enum aarch64_imm_type imm_type)
+{
+	u64 imm, imm_mask;
+	s64 sval;
+	u32 insn = *(u32 *)place;
+
+	/* Calculate the relocation value. */
+	sval = do_reloc(op, place, val);
+	sval >>= lsb;
+
+	/* Extract the value bits and shift them to bit 0. */
+	imm_mask = (BIT(lsb + len) - 1) >> lsb;
+	imm = sval & imm_mask;
+
+	/* Update the instruction's immediate field. */
+	*(u32 *)place = encode_insn_immediate(imm_type, insn, imm);
+
+	/*
+	 * Extract the upper value bits (including the sign bit) and
+	 * shift them to bit 0.
+	 */
+	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
+
+	/*
+	 * Overflow has occurred if the upper bits are not all equal to
+	 * the sign bit of the value.
+	 */
+	if ((u64)(sval + 1) >= 2)
+		return -ERANGE;
+
+	return 0;
+}
+
+int apply_relocate_add(Elf64_Shdr *sechdrs,
+		       const char *strtab,
+		       unsigned int symindex,
+		       unsigned int relsec,
+		       struct module *me)
+{
+	unsigned int i;
+	int ovf;
+	bool overflow_check;
+	Elf64_Sym *sym;
+	void *loc;
+	u64 val;
+	Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
+
+	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
+		/* loc corresponds to P in the AArch64 ELF document. */
+		loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+			+ rel[i].r_offset;
+
+		/* sym is the ELF symbol we're referring to. */
+		sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
+			+ ELF64_R_SYM(rel[i].r_info);
+
+		/* val corresponds to (S + A) in the AArch64 ELF document. */
+		val = sym->st_value + rel[i].r_addend;
+
+		/* Check for overflow by default. */
+		overflow_check = true;
+
+		/* Perform the static relocation. */
+		switch (ELF64_R_TYPE(rel[i].r_info)) {
+		/* Null relocations. */
+		case R_ARM_NONE:
+		case R_AARCH64_NONE:
+			ovf = 0;
+			break;
+
+		/* Data relocations. */
+		case R_AARCH64_ABS64:
+			overflow_check = false;
+			ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
+			break;
+		case R_AARCH64_ABS32:
+			ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
+			break;
+		case R_AARCH64_ABS16:
+			ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
+			break;
+		case R_AARCH64_PREL64:
+			overflow_check = false;
+			ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
+			break;
+		case R_AARCH64_PREL32:
+			ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
+			break;
+		case R_AARCH64_PREL16:
+			ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
+			break;
+
+		/* MOVW instruction relocations. */
+		case R_AARCH64_MOVW_UABS_G0_NC:
+			overflow_check = false;
+		case R_AARCH64_MOVW_UABS_G0:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
+					      INSN_IMM_16);
+			break;
+		case R_AARCH64_MOVW_UABS_G1_NC:
+			overflow_check = false;
+		case R_AARCH64_MOVW_UABS_G1:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
+					      INSN_IMM_16);
+			break;
+		case R_AARCH64_MOVW_UABS_G2_NC:
+			overflow_check = false;
+		case R_AARCH64_MOVW_UABS_G2:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
+					      INSN_IMM_16);
+			break;
+		case R_AARCH64_MOVW_UABS_G3:
+			/* We're using the top bits so we can't overflow. */
+			overflow_check = false;
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
+					      INSN_IMM_16);
+			break;
+		case R_AARCH64_MOVW_SABS_G0:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_SABS_G1:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_SABS_G2:
+			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_PREL_G0_NC:
+			overflow_check = false;
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
+					      INSN_IMM_MOVK);
+			break;
+		case R_AARCH64_MOVW_PREL_G0:
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_PREL_G1_NC:
+			overflow_check = false;
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
+					      INSN_IMM_MOVK);
+			break;
+		case R_AARCH64_MOVW_PREL_G1:
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_PREL_G2_NC:
+			overflow_check = false;
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
+					      INSN_IMM_MOVK);
+			break;
+		case R_AARCH64_MOVW_PREL_G2:
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
+					      INSN_IMM_MOVNZ);
+			break;
+		case R_AARCH64_MOVW_PREL_G3:
+			/* We're using the top bits so we can't overflow. */
+			overflow_check = false;
+			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
+					      INSN_IMM_MOVNZ);
+			break;
+
+		/* Immediate instruction relocations. */
+		case R_AARCH64_LD_PREL_LO19:
+			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
+					     INSN_IMM_19);
+			break;
+		case R_AARCH64_ADR_PREL_LO21:
+			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
+					     INSN_IMM_ADR);
+			break;
+		case R_AARCH64_ADR_PREL_PG_HI21_NC:
+			overflow_check = false;
+		case R_AARCH64_ADR_PREL_PG_HI21:
+			ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21,
+					     INSN_IMM_ADR);
+			break;
+		case R_AARCH64_ADD_ABS_LO12_NC:
+		case R_AARCH64_LDST8_ABS_LO12_NC:
+			overflow_check = false;
+			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
+					     INSN_IMM_12);
+			break;
+		case R_AARCH64_LDST16_ABS_LO12_NC:
+			overflow_check = false;
+			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
+					     INSN_IMM_12);
+			break;
+		case R_AARCH64_LDST32_ABS_LO12_NC:
+			overflow_check = false;
+			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
+					     INSN_IMM_12);
+			break;
+		case R_AARCH64_LDST64_ABS_LO12_NC:
+			overflow_check = false;
+			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
+					     INSN_IMM_12);
+			break;
+		case R_AARCH64_LDST128_ABS_LO12_NC:
+			overflow_check = false;
+			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
+					     INSN_IMM_12);
+			break;
+		case R_AARCH64_TSTBR14:
+			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
+					     INSN_IMM_14);
+			break;
+		case R_AARCH64_CONDBR19:
+			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
+					     INSN_IMM_19);
+			break;
+		case R_AARCH64_JUMP26:
+		case R_AARCH64_CALL26:
+			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
+					     INSN_IMM_26);
+			break;
+
+		default:
+			pr_err("module %s: unsupported RELA relocation: %llu\n",
+			       me->name, ELF64_R_TYPE(rel[i].r_info));
+			return -ENOEXEC;
+		}
+
+		if (overflow_check && ovf == -ERANGE)
+			goto overflow;
+
+	}
+
+	return 0;
+
+overflow:
+	pr_err("module %s: overflow in relocation type %d val %Lx\n",
+	       me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
+	return -ENOEXEC;
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:31 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:31 +0100
Subject: [PATCH v2 30/31] arm64: Build infrastructure
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>

This patch adds Makefile and Kconfig files required for building an
AArch64 kernel.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/Kconfig                   |  261 ++++++++++++++++++++++++++++++++++
 arch/arm64/Kconfig.debug             |   27 ++++
 arch/arm64/Makefile                  |   71 +++++++++
 arch/arm64/boot/.gitignore           |    2 +
 arch/arm64/boot/Makefile             |   38 +++++
 arch/arm64/boot/install.sh           |   52 +++++++
 arch/arm64/configs/generic_defconfig |   85 +++++++++++
 arch/arm64/include/asm/prom.h        |    1 +
 arch/arm64/kernel/.gitignore         |    1 +
 arch/arm64/kernel/Makefile           |   27 ++++
 arch/arm64/kernel/vmlinux.lds.S      |  146 +++++++++++++++++++
 arch/arm64/mm/Kconfig                |    5 +
 arch/arm64/mm/Makefile               |    6 +
 init/Kconfig                         |    3 +-
 lib/Kconfig.debug                    |    6 +-
 15 files changed, 728 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/Kconfig
 create mode 100644 arch/arm64/Kconfig.debug
 create mode 100644 arch/arm64/Makefile
 create mode 100644 arch/arm64/boot/.gitignore
 create mode 100644 arch/arm64/boot/Makefile
 create mode 100644 arch/arm64/boot/install.sh
 create mode 100644 arch/arm64/configs/generic_defconfig
 create mode 100644 arch/arm64/include/asm/prom.h
 create mode 100644 arch/arm64/kernel/.gitignore
 create mode 100644 arch/arm64/kernel/Makefile
 create mode 100644 arch/arm64/kernel/vmlinux.lds.S
 create mode 100644 arch/arm64/mm/Kconfig
 create mode 100644 arch/arm64/mm/Makefile

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
new file mode 100644
index 0000000..1ce3d04
--- /dev/null
+++ b/arch/arm64/Kconfig
@@ -0,0 +1,261 @@
+config ARM64
+	def_bool y
+	select OF
+	select OF_EARLY_FLATTREE
+	select IRQ_DOMAIN
+	select HAVE_AOUT
+	select HAVE_DMA_ATTRS
+	select HAVE_DMA_API_DEBUG
+	select HAVE_IDE
+	select HAVE_MEMBLOCK
+	select RTC_LIB
+	select SYS_SUPPORTS_APM_EMULATION
+	select HAVE_GENERIC_DMA_COHERENT
+	select GENERIC_IOMAP
+	select HAVE_IRQ_WORK
+	select HAVE_PERF_EVENTS
+	select HAVE_ARCH_TRACEHOOK
+	select PERF_USE_VMALLOC
+	select HAVE_HW_BREAKPOINT if PERF_EVENTS
+	select HAVE_GENERIC_HARDIRQS
+	select GENERIC_HARDIRQS_NO_DEPRECATED
+	select HAVE_SPARSE_IRQ
+	select SPARSE_IRQ
+	select GENERIC_IRQ_SHOW
+	select GENERIC_SMP_IDLE_THREAD
+	select NO_BOOTMEM
+	help
+	  ARM 64-bit (AArch64) Linux support.
+
+config 64BIT
+	def_bool y
+
+config ARCH_PHYS_ADDR_T_64BIT
+	def_bool y
+
+config HAVE_PWM
+	bool
+
+config SYS_SUPPORTS_APM_EMULATION
+	bool
+
+config NO_IOPORT
+	def_bool y
+
+config GENERIC_GPIO
+	bool
+
+config GENERIC_TIME_VSYSCALL
+	def_bool y
+
+config GENERIC_CLOCKEVENTS
+	def_bool y
+
+config STACKTRACE_SUPPORT
+	def_bool y
+
+config LOCKDEP_SUPPORT
+	def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+	def_bool y
+
+config HARDIRQS_SW_RESEND
+	def_bool y
+
+config GENERIC_IRQ_PROBE
+	def_bool y
+
+config GENERIC_LOCKBREAK
+	def_bool y
+	depends on SMP && PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+	def_bool y
+
+config RWSEM_XCHGADD_ALGORITHM
+	bool
+
+config ARCH_HAS_ILOG2_U32
+	bool
+
+config ARCH_HAS_ILOG2_U64
+	bool
+
+config ARCH_HAS_CPUFREQ
+	bool
+	help
+	  Internal node to signify that the ARCH has CPUFREQ support
+	  and that the relevant menu configurations are displayed for
+	  it.
+
+config GENERIC_HWEIGHT
+	def_bool y
+
+config GENERIC_CSUM
+        def_bool y
+
+config GENERIC_CALIBRATE_DELAY
+	def_bool y
+
+config ZONE_DMA32
+	def_bool y
+
+config ARCH_DMA_ADDR_T_64BIT
+	def_bool y
+
+config NEED_DMA_MAP_STATE
+	def_bool y
+
+config NEED_SG_DMA_LENGTH
+	def_bool y
+
+config SWIOTLB
+	def_bool y
+
+config IOMMU_HELPER
+	def_bool SWIOTLB
+
+source "init/Kconfig"
+
+source "kernel/Kconfig.freezer"
+
+menu "System Type"
+
+source "arch/arm64/mm/Kconfig"
+
+endmenu
+
+menu "Bus support"
+
+config ARM_AMBA
+	bool
+
+endmenu
+
+menu "Kernel Features"
+
+source "kernel/time/Kconfig"
+
+config ARM64_64K_PAGES
+	bool "Enable 64KB pages support"
+	help
+	  This feature enables 64KB pages support (4KB by default)
+	  allowing only two levels of page tables and faster TLB
+	  look-up. AArch32 emulation is not available when this feature
+	  is enabled.
+
+config SMP
+	bool "Symmetric Multi-Processing"
+	depends on GENERIC_CLOCKEVENTS
+	select USE_GENERIC_SMP_HELPERS
+	help
+	  This enables support for systems with more than one CPU.  If
+	  you say N here, the kernel will run on single and
+	  multiprocessor machines, but will use only one CPU of a
+	  multiprocessor machine. If you say Y here, the kernel will run
+	  on many, but not all, single processor machines. On a single
+	  processor machine, the kernel will run faster if you say N
+	  here.
+
+	  If you don't know what to do here, say N.
+
+config NR_CPUS
+	int "Maximum number of CPUs (2-32)"
+	range 2 32
+	depends on SMP
+	default "4"
+
+source kernel/Kconfig.preempt
+
+config HZ
+	int
+	default 100
+
+config ARCH_HAS_HOLES_MEMORYMODEL
+	def_bool y if SPARSEMEM
+
+config ARCH_SPARSEMEM_ENABLE
+	def_bool y
+	select SPARSEMEM_VMEMMAP_ENABLE
+
+config ARCH_SPARSEMEM_DEFAULT
+	def_bool ARCH_SPARSEMEM_ENABLE
+
+config ARCH_SELECT_MEMORY_MODEL
+	def_bool ARCH_SPARSEMEM_ENABLE
+
+config HAVE_ARCH_PFN_VALID
+	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
+
+config HW_PERF_EVENTS
+	bool "Enable hardware performance counter support for perf events"
+	depends on PERF_EVENTS
+	default y
+	help
+	  Enable hardware performance counter support for perf events. If
+	  disabled, perf events will use software events only.
+
+source "mm/Kconfig"
+
+endmenu
+
+menu "Boot options"
+
+config CMDLINE
+	string "Default kernel command string"
+	default ""
+	help
+	  Provide a set of default command-line options at build time by
+	  entering them here. As a minimum, you should specify the the
+	  root device (e.g. root=/dev/nfs).
+
+config CMDLINE_FORCE
+	bool "Always use the default kernel command string"
+	help
+	  Always use the default kernel command string, even if the boot
+	  loader passes other arguments to the kernel.
+	  This is useful if you cannot or don't want to change the
+	  command-line options your boot loader passes to the kernel.
+
+endmenu
+
+menu "Userspace binary formats"
+
+source "fs/Kconfig.binfmt"
+
+config AARCH32_EMULATION
+	bool "Kernel support for 32-bit EL0"
+	depends on !ARM64_64K_PAGES
+	select COMPAT_BINFMT_ELF
+	help
+	  This option enables support for a 32-bit EL0 running under a 64-bit
+	  kernel at EL1. AArch32-specific components such as system calls,
+	  the user helper functions, VFP support and the ptrace interface are
+	  handled appropriately by the kernel.
+
+	  If you want to execute 32-bit userspace applications, say Y.
+
+config COMPAT
+	def_bool y
+	depends on AARCH32_EMULATION
+
+config SYSVIPC_COMPAT
+	def_bool y
+	depends on COMPAT && SYSVIPC
+
+endmenu
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "arch/arm64/Kconfig.debug"
+
+source "security/Kconfig"
+
+source "crypto/Kconfig"
+
+source "lib/Kconfig"
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
new file mode 100644
index 0000000..d7553f2
--- /dev/null
+++ b/arch/arm64/Kconfig.debug
@@ -0,0 +1,27 @@
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config FRAME_POINTER
+	bool
+	default y
+
+config DEBUG_ERRORS
+	bool "Verbose kernel error messages"
+	depends on DEBUG_KERNEL
+	help
+	  This option controls verbose debugging information which can be
+	  printed when the kernel detects an internal error. This debugging
+	  information is useful to kernel hackers when tracking down problems,
+	  but mostly meaningless to other people. It's safe to say Y unless
+	  you are concerned with the code size or don't want to see these
+	  messages.
+
+config DEBUG_STACK_USAGE
+	bool "Enable stack utilization instrumentation"
+	depends on DEBUG_KERNEL
+	help
+	  Enables the display of the minimum amount of free stack which each
+	  task has ever had available in the sysrq-T output.
+
+endmenu
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
new file mode 100644
index 0000000..831bd41
--- /dev/null
+++ b/arch/arm64/Makefile
@@ -0,0 +1,71 @@
+#
+# arch/arm64/Makefile
+#
+# This file is included by the global makefile so that you can add your own
+# architecture-specific flags and dependencies.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995-2001 by Russell King
+
+LDFLAGS_vmlinux	:=-p --no-undefined -X
+CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
+OBJCOPYFLAGS	:=-O binary -R .note -R .note.gnu.build-id -R .comment -S
+GZFLAGS		:=-9
+
+LIBGCC 		:= $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
+
+KBUILD_DEFCONFIG := generic_defconfig
+
+KBUILD_CFLAGS	+= -mgeneral-regs-only
+KBUILD_CPPFLAGS	+= -mlittle-endian
+AS		+= -EL
+LD		+= -EL
+
+comma = ,
+
+CHECKFLAGS	+= -D__aarch64__
+
+# Default value
+head-y		:= arch/arm64/kernel/head.o
+
+# The byte offset of the kernel image in RAM from the start of RAM.
+TEXT_OFFSET := 0x00080000
+
+export	TEXT_OFFSET GZFLAGS
+
+core-y		+= arch/arm64/kernel/ arch/arm64/mm/
+libs-y		:= arch/arm64/lib/ $(libs-y)
+libs-y		+= $(LIBGCC)
+
+# Default target when executing plain make
+KBUILD_IMAGE := Image.gz
+
+all:	$(KBUILD_IMAGE)
+
+boot := arch/arm64/boot
+
+Image Image.gz: vmlinux
+	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
+
+zinstall install: vmlinux
+	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
+
+%.dtb:
+	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
+
+# We use MRPROPER_FILES and CLEAN_FILES now
+archclean:
+	$(Q)$(MAKE) $(clean)=$(boot)
+
+define archhelp
+  echo  '* Image.gz      - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'
+  echo  '  Image         - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
+  echo  '  install       - Install uncompressed kernel'
+  echo  '  zinstall      - Install compressed kernel'
+  echo  '                  Install using (your) ~/bin/installkernel or'
+  echo  '                  (distribution) /sbin/installkernel or'
+  echo  '                  install to $$(INSTALL_PATH) and run lilo'
+endef
diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore
new file mode 100644
index 0000000..8dab0bb
--- /dev/null
+++ b/arch/arm64/boot/.gitignore
@@ -0,0 +1,2 @@
+Image
+Image.gz
diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile
new file mode 100644
index 0000000..15a58a8
--- /dev/null
+++ b/arch/arm64/boot/Makefile
@@ -0,0 +1,38 @@
+#
+# arch/arm64/boot/Makefile
+#
+# This file is included by the global makefile so that you can add your own
+# architecture-specific flags and dependencies.
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2012, ARM Ltd.
+# Author: Will Deacon <will.deacon at arm.com>
+#
+# Based on the ia64 boot/Makefile.
+#
+
+targets := Image Image.gz
+
+$(obj)/Image: vmlinux FORCE
+	$(call if_changed,objcopy)
+	@echo '  Kernel: $@ is ready'
+
+$(obj)/Image.gz: $(obj)/Image FORCE
+	$(call if_changed,gzip)
+	@echo '  Kernel: $@ is ready'
+
+$(obj)/%.dtb: $(src)/dts/%.dts
+	$(call cmd,dtc)
+
+install: $(obj)/Image
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+	$(obj)/Image System.map "$(INSTALL_PATH)"
+
+zinstall: $(obj)/Image.gz
+	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+	$(obj)/Image.gz System.map "$(INSTALL_PATH)"
+
+clean-files += *.dtb
diff --git a/arch/arm64/boot/install.sh b/arch/arm64/boot/install.sh
new file mode 100644
index 0000000..9151e21
--- /dev/null
+++ b/arch/arm64/boot/install.sh
@@ -0,0 +1,52 @@
+#!/bin/sh
+#
+# arch/arm64/boot/install.sh
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995 by Linus Torvalds
+#
+# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
+# Adapted from code in arch/i386/boot/install.sh by Russell King
+#
+# "make install" script for the AArch64 Linux port
+#
+# Arguments:
+#   $1 - kernel version
+#   $2 - kernel image file
+#   $3 - kernel map file
+#   $4 - default install path (blank if root directory)
+#
+
+# User may have a custom install script
+if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
+if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi
+
+if [ "$(basename $2)" = "Image.gz" ]; then
+# Compressed install
+  echo "Installing compressed kernel"
+  base=vmlinuz
+else
+# Normal install
+  echo "Installing normal kernel"
+  base=vmlinux
+fi
+
+if [ -f $4/$base-$1 ]; then
+  mv $4/$base-$1 $4/$base-$1.old
+fi
+cat $2 > $4/$base-$1
+
+# Install system map file
+if [ -f $4/System.map-$1 ]; then
+  mv $4/System.map-$1 $4/System.map-$1.old
+fi
+cp $3 $4/System.map-$1
+
+if [ -x /sbin/loadmap ]; then
+  /sbin/loadmap
+else
+  echo "You have to install it yourself"
+fi
diff --git a/arch/arm64/configs/generic_defconfig b/arch/arm64/configs/generic_defconfig
new file mode 100644
index 0000000..d9aac95
--- /dev/null
+++ b/arch/arm64/configs/generic_defconfig
@@ -0,0 +1,85 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_SMP=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_CMDLINE="console=ttyAMA0"
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_AARCH32_EMULATION=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm64/include/asm/prom.h b/arch/arm64/include/asm/prom.h
new file mode 100644
index 0000000..68b90e6
--- /dev/null
+++ b/arch/arm64/include/asm/prom.h
@@ -0,0 +1 @@
+/* Empty for now */
diff --git a/arch/arm64/kernel/.gitignore b/arch/arm64/kernel/.gitignore
new file mode 100644
index 0000000..c5f676c
--- /dev/null
+++ b/arch/arm64/kernel/.gitignore
@@ -0,0 +1 @@
+vmlinux.lds
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
new file mode 100644
index 0000000..59fbdef
--- /dev/null
+++ b/arch/arm64/kernel/Makefile
@@ -0,0 +1,27 @@
+#
+# Makefile for the linux kernel.
+#
+
+CPPFLAGS_vmlinux.lds	:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+AFLAGS_head.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+
+# Object file lists.
+arm64-obj-y		:= debug-monitors.o elf.o entry.o irq.o	fpsimd.o	\
+			   entry-fpsimd.o process.o ptrace.o setup.o signal.o	\
+			   sys.o stacktrace.o time.o traps.o io.o vdso.o
+
+arm64-obj-$(CONFIG_AARCH32_EMULATION)	+= sys32.o kuser32.o signal32.o 	\
+					   sys_compat.o
+arm64-obj-$(CONFIG_MODULES)		+= arm64ksyms.o module.o
+arm64-obj-$(CONFIG_SMP)			+= smp.o
+arm64-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
+arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
+
+obj-y					+= $(arm64-obj-y) vdso/
+obj-m					+= $(arm64-obj-m)
+head-y					:= head.o
+extra-y					:= $(head-y) vmlinux.lds
+
+# vDSO - this must be built first to generate the symbol offsets
+$(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h
+$(obj)/vdso/vdso-offsets.h: $(obj)/vdso
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
new file mode 100644
index 0000000..5eab87b
--- /dev/null
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -0,0 +1,146 @@
+/*
+ * ld script to make ARM Linux kernel
+ * taken from the i386 version by Russell King
+ * Written by Martin Mares <mj at atrey.karlin.mff.cuni.cz>
+ */
+
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/thread_info.h>
+#include <asm/memory.h>
+#include <asm/page.h>
+
+#define PROC_INFO							\
+	VMLINUX_SYMBOL(__proc_info_begin) = .;				\
+	*(.proc.info.init)						\
+	VMLINUX_SYMBOL(__proc_info_end) = .;
+
+#define ARM_CPU_DISCARD(x)	x
+#define ARM_CPU_KEEP(x)
+
+#define ARM_EXIT_KEEP(x)
+#define ARM_EXIT_DISCARD(x)	x
+
+OUTPUT_ARCH(aarch64)
+ENTRY(stext)
+
+jiffies = jiffies_64;
+
+SECTIONS
+{
+	/*
+	 * XXX: The linker does not define how output sections are
+	 * assigned to input sections when there are multiple statements
+	 * matching the same input section name.  There is no documented
+	 * order of matching.
+	 */
+	/DISCARD/ : {
+		ARM_EXIT_DISCARD(EXIT_TEXT)
+		ARM_EXIT_DISCARD(EXIT_DATA)
+		EXIT_CALL
+		*(.discard)
+		*(.discard.*)
+	}
+
+	. = PAGE_OFFSET + TEXT_OFFSET;
+
+	.head.text : {
+		_text = .;
+		HEAD_TEXT
+	}
+	.text : {			/* Real text segment		*/
+		_stext = .;		/* Text and read-only data	*/
+			*(.smp.pen.text)
+			__exception_text_start = .;
+			*(.exception.text)
+			__exception_text_end = .;
+			IRQENTRY_TEXT
+			TEXT_TEXT
+			SCHED_TEXT
+			LOCK_TEXT
+			*(.fixup)
+			*(.gnu.warning)
+		. = ALIGN(16);
+		*(.got)			/* Global offset table		*/
+			ARM_CPU_KEEP(PROC_INFO)
+	}
+
+	RO_DATA(PAGE_SIZE)
+
+	_etext = .;			/* End of text and rodata section */
+
+	. = ALIGN(PAGE_SIZE);
+	__init_begin = .;
+
+	INIT_TEXT_SECTION(8)
+	.exit.text : {
+		ARM_EXIT_KEEP(EXIT_TEXT)
+	}
+	. = ALIGN(16);
+	.init.proc.info : {
+		ARM_CPU_DISCARD(PROC_INFO)
+	}
+	. = ALIGN(16);
+	.init.data : {
+		INIT_DATA
+		INIT_SETUP(16)
+		INIT_CALLS
+		CON_INITCALL
+		SECURITY_INITCALL
+		INIT_RAM_FS
+	}
+	.exit.data : {
+		ARM_EXIT_KEEP(EXIT_DATA)
+	}
+
+	PERCPU_SECTION(64)
+
+	__init_end = .;
+	. = ALIGN(THREAD_SIZE);
+	__data_loc = .;
+
+	.data : AT(__data_loc) {
+		_data = .;		/* address in memory */
+		_sdata = .;
+
+		/*
+		 * first, the init task union, aligned
+		 * to an 8192 byte boundary.
+		 */
+		INIT_TASK_DATA(THREAD_SIZE)
+		NOSAVE_DATA
+		CACHELINE_ALIGNED_DATA(64)
+		READ_MOSTLY_DATA(64)
+
+		/*
+		 * The exception fixup table (might need resorting at runtime)
+		 */
+		. = ALIGN(32);
+		__start___ex_table = .;
+		*(__ex_table)
+		__stop___ex_table = .;
+
+		/*
+		 * and the usual data section
+		 */
+		DATA_DATA
+		CONSTRUCTORS
+
+		_edata = .;
+	}
+	_edata_loc = __data_loc + SIZEOF(.data);
+
+	NOTES
+
+	BSS_SECTION(0, 0, 0)
+	_end = .;
+
+	STABS_DEBUG
+	.comment 0 : { *(.comment) }
+}
+
+/*
+ * These must never be empty
+ * If you have to comment these two assert statements out, your
+ * binutils is too old (for other reasons as well)
+ */
+ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
diff --git a/arch/arm64/mm/Kconfig b/arch/arm64/mm/Kconfig
new file mode 100644
index 0000000..8e94e52
--- /dev/null
+++ b/arch/arm64/mm/Kconfig
@@ -0,0 +1,5 @@
+config MMU
+	def_bool y
+
+config CPU_64
+	def_bool y
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
new file mode 100644
index 0000000..81a9d8b
--- /dev/null
+++ b/arch/arm64/mm/Makefile
@@ -0,0 +1,6 @@
+obj-y				:= dma-mapping.o extable.o fault.o init.o \
+				   cache.o copypage.o flush.o \
+				   ioremap.o mmap.o pgd.o mmu.o \
+				   context.o tlb.o proc.o
+
+obj-$(CONFIG_MODULES)		+= proc-syms.o
diff --git a/init/Kconfig b/init/Kconfig
index af6c7f8..8bfda46 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1153,7 +1153,8 @@ menuconfig EXPERT
 
 config UID16
 	bool "Enable 16-bit UID system calls" if EXPERT
-	depends on ARM || BLACKFIN || CRIS || FRV || H8300 || X86_32 || M68K || (S390 && !64BIT) || SUPERH || SPARC32 || (SPARC64 && COMPAT) || UML || (X86_64 && IA32_EMULATION)
+	depends on ARM || BLACKFIN || CRIS || FRV || H8300 || X86_32 || M68K || (S390 && !64BIT) || SUPERH || SPARC32 || (SPARC64 && COMPAT) || UML || (X86_64 && IA32_EMULATION) \
+		|| AARCH32_EMULATION
 	default y
 	help
 	  This enables the legacy 16-bit UID syscall wrappers.
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 2403a63..cfb4578 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -452,7 +452,8 @@ config SLUB_STATS
 config DEBUG_KMEMLEAK
 	bool "Kernel memory leak detector"
 	depends on DEBUG_KERNEL && EXPERIMENTAL && \
-		(X86 || ARM || PPC || MIPS || S390 || SPARC64 || SUPERH || MICROBLAZE || TILE)
+		(X86 || ARM || PPC || MIPS || S390 || SPARC64 || SUPERH || \
+		 MICROBLAZE || TILE || ARM64)
 
 	select DEBUG_FS
 	select STACKTRACE if STACKTRACE_SUPPORT
@@ -739,7 +740,8 @@ config DEBUG_BUGVERBOSE
 	bool "Verbose BUG() reporting (adds 70K)" if DEBUG_KERNEL && EXPERT
 	depends on BUG
 	depends on ARM || AVR32 || M32R || M68K || SPARC32 || SPARC64 || \
-		   FRV || SUPERH || GENERIC_BUG || BLACKFIN || MN10300 || TILE
+		   FRV || SUPERH || GENERIC_BUG || BLACKFIN || MN10300 || \
+		   TILE || ARM64
 	default y
 	help
 	  Say Y here to make BUG() panics output the file name and line number



From catalin.marinas at arm.com  Tue Aug 14 13:52:05 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:05 +0100
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>

The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions for
the 4KB and 64KB translation table configurations. The SECTION_SIZE is
2MB with 4KB page and 512MB with 64KB page configuration.

PHYS_OFFSET is calculated at run-time and stored in a variable (no
run-time code patching at this stage).

On the current implementation, both user and kernel address spaces are
512G (39-bit) each with a maximum of 256G for the RAM linear mapping.
Linux uses 3 levels of translation tables with the 4K page configuration
and 2 levels with the 64K configuration. Extending the memory space
beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an
additional level of translation tables.

The SPARSEMEM configuration is global to all AArch64 platforms and
allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 Documentation/arm64/memory.txt                |   69 +++++
 arch/arm64/include/asm/memory.h               |  144 +++++++++++
 arch/arm64/include/asm/mmu.h                  |   27 ++
 arch/arm64/include/asm/pgtable-2level-hwdef.h |   43 ++++
 arch/arm64/include/asm/pgtable-2level-types.h |   60 +++++
 arch/arm64/include/asm/pgtable-3level-hwdef.h |   50 ++++
 arch/arm64/include/asm/pgtable-3level-types.h |   66 +++++
 arch/arm64/include/asm/pgtable-hwdef.h        |   94 +++++++
 arch/arm64/include/asm/pgtable.h              |  328 +++++++++++++++++++++++++
 arch/arm64/include/asm/sparsemem.h            |   24 ++
 10 files changed, 905 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/arm64/memory.txt
 create mode 100644 arch/arm64/include/asm/memory.h
 create mode 100644 arch/arm64/include/asm/mmu.h
 create mode 100644 arch/arm64/include/asm/pgtable-2level-hwdef.h
 create mode 100644 arch/arm64/include/asm/pgtable-2level-types.h
 create mode 100644 arch/arm64/include/asm/pgtable-3level-hwdef.h
 create mode 100644 arch/arm64/include/asm/pgtable-3level-types.h
 create mode 100644 arch/arm64/include/asm/pgtable-hwdef.h
 create mode 100644 arch/arm64/include/asm/pgtable.h
 create mode 100644 arch/arm64/include/asm/sparsemem.h

diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
new file mode 100644
index 0000000..7210af7
--- /dev/null
+++ b/Documentation/arm64/memory.txt
@@ -0,0 +1,69 @@
+		     Memory Layout on AArch64 Linux
+		     ==============================
+
+Author: Catalin Marinas <catalin.marinas at arm.com>
+Date  : 20 February 2012
+
+This document describes the virtual memory layout used by the AArch64
+Linux kernel. The architecture allows up to 4 levels of translation
+tables with a 4KB page size and up to 3 levels with a 64KB page size.
+
+AArch64 Linux uses 3 levels of translation tables with the 4KB page
+configuration, allowing 39-bit (512GB) virtual addresses for both user
+and kernel. With 64KB pages, only 2 levels of translation tables are
+used but the memory layout is the same.
+
+User addresses have bits 63:39 set to 0 while the kernel addresses have
+the same bits set to 1. TTBRx selection is given by bit 63 of the
+virtual address. The swapper_pg_dir contains only kernel (global)
+mappings while the user pgd contains only user (non-global) mappings.
+The swapper_pgd_dir address is written to TTBR1 and never written to
+TTBR0.
+
+
+AArch64 Linux memory layout:
+
+Start			End			Size		Use
+-----------------------------------------------------------------------
+0000000000000000	0000007fffffffff	 512GB		user
+
+ffffff8000000000	ffffffbbfffeffff	~240GB		vmalloc
+
+ffffffbbffff0000	ffffffbcffffffff	  64KB		[guard page]
+
+ffffffbc00000000	ffffffbdffffffff	   8GB		vmemmap
+
+ffffffbe00000000	ffffffbffbffffff	  ~8GB		[guard, future vmmemap]
+
+ffffffbffc000000	ffffffbfffffffff	  64MB		modules
+
+ffffffc000000000	ffffffffffffffff	 256GB		memory
+
+
+Translation table lookup with 4KB pages:
+
++--------+--------+--------+--------+--------+--------+--------+--------+
+|63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
++--------+--------+--------+--------+--------+--------+--------+--------+
+ |                 |         |         |         |         |
+ |                 |         |         |         |         v
+ |                 |         |         |         |   [11:0]  in-page offset
+ |                 |         |         |         +-> [20:12] L3 index
+ |                 |         |         +-----------> [29:21] L2 index
+ |                 |         +---------------------> [38:30] L1 index
+ |                 +-------------------------------> [47:39] L0 index (not used)
+ +-------------------------------------------------> [63] TTBR0/1
+
+
+Translation table lookup with 64KB pages:
+
++--------+--------+--------+--------+--------+--------+--------+--------+
+|63    56|55    48|47    40|39    32|31    24|23    16|15     8|7      0|
++--------+--------+--------+--------+--------+--------+--------+--------+
+ |                 |    |               |              |
+ |                 |    |               |              v
+ |                 |    |               |            [15:0]  in-page offset
+ |                 |    |               +----------> [28:16] L3 index
+ |                 |    +--------------------------> [41:29] L2 index (only 38:29 used)
+ |                 +-------------------------------> [47:42] L1 index (not used)
+ +-------------------------------------------------> [63] TTBR0/1
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
new file mode 100644
index 0000000..3cfdc4b
--- /dev/null
+++ b/arch/arm64/include/asm/memory.h
@@ -0,0 +1,144 @@
+/*
+ * Based on arch/arm/include/asm/memory.h
+ *
+ * Copyright (C) 2000-2002 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_MEMORY_H
+#define __ASM_MEMORY_H
+
+#include <linux/compiler.h>
+#include <linux/const.h>
+#include <linux/types.h>
+#include <asm/sizes.h>
+
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#define UL(x) _AC(x, UL)
+
+/*
+ * PAGE_OFFSET - the virtual address of the start of the kernel image.
+ * VA_BITS - the maximum number of bits for virtual addresses.
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
+ * The module space lives between the addresses given by TASK_SIZE
+ * and PAGE_OFFSET - it must be within 128MB of the kernel text.
+ */
+#define PAGE_OFFSET		UL(0xffffffc000000000)
+#define MODULES_END		(PAGE_OFFSET)
+#define MODULES_VADDR		(MODULES_END - SZ_64M)
+#define VA_BITS			(39)
+#define TASK_SIZE_64		(UL(1) << VA_BITS)
+
+#ifdef CONFIG_AARCH32_EMULATION
+#define TASK_SIZE_32		UL(0x100000000)
+#define TASK_SIZE		(test_thread_flag(TIF_32BIT) ? \
+				TASK_SIZE_32 : TASK_SIZE_64)
+#else
+#define TASK_SIZE		TASK_SIZE_64
+#endif /* CONFIG_AARCH32_EMULATION */
+
+#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 4))
+
+#if TASK_SIZE_64 > MODULES_VADDR
+#error Top of 64-bit user space clashes with start of module space
+#endif
+
+/*
+ * Physical vs virtual RAM address space conversion.  These are
+ * private definitions which should NOT be used outside memory.h
+ * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+#define __virt_to_phys(x)	(((phys_addr_t)(x) - PAGE_OFFSET + PHYS_OFFSET))
+#define __phys_to_virt(x)	((unsigned long)((x) - PHYS_OFFSET + PAGE_OFFSET))
+
+/*
+ * Convert a physical address to a Page Frame Number and back
+ */
+#define	__phys_to_pfn(paddr)	((unsigned long)((paddr) >> PAGE_SHIFT))
+#define	__pfn_to_phys(pfn)	((phys_addr_t)(pfn) << PAGE_SHIFT)
+
+/*
+ * Convert a page to/from a physical address
+ */
+#define page_to_phys(page)	(__pfn_to_phys(page_to_pfn(page)))
+#define phys_to_page(phys)	(pfn_to_page(__phys_to_pfn(phys)))
+
+/*
+ * Memory types available.
+ */
+#define MT_DEVICE_nGnRnE	0
+#define MT_DEVICE_nGnRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL		4
+
+#ifndef __ASSEMBLY__
+
+extern phys_addr_t		memstart_addr;
+/* PHYS_OFFSET - the physical address of the start of memory. */
+#define PHYS_OFFSET		({ memstart_addr; })
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view.  We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * Note: Drivers should NOT use these.  They are the wrong
+ * translation for translating DMA addresses.  Use the driver
+ * DMA support - see dma-mapping.h.
+ */
+static inline phys_addr_t virt_to_phys(const volatile void *x)
+{
+	return __virt_to_phys((unsigned long)(x));
+}
+
+static inline void *phys_to_virt(phys_addr_t x)
+{
+	return (void *)(__phys_to_virt(x));
+}
+
+/*
+ * Drivers should NOT use these either.
+ */
+#define __pa(x)			__virt_to_phys((unsigned long)(x))
+#define __va(x)			((void *)__phys_to_virt((phys_addr_t)(x)))
+#define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
+
+/*
+ *  virt_to_page(k)	convert a _valid_ virtual address to struct page *
+ *  virt_addr_valid(k)	indicates whether a virtual address is valid
+ */
+#define ARCH_PFN_OFFSET		PHYS_PFN_OFFSET
+
+#define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define	virt_addr_valid(kaddr)	(((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
+				 ((void *)(kaddr) < (void *)high_memory))
+
+#endif
+
+#include <asm-generic/memory_model.h>
+
+#endif
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
new file mode 100644
index 0000000..981498a
--- /dev/null
+++ b/arch/arm64/include/asm/mmu.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+typedef struct {
+	unsigned int id;
+	spinlock_t id_lock;
+	void *vdso;
+} mm_context_t;
+
+#define ASID(mm)	((mm)->context.id & 0xffff)
+
+#endif
diff --git a/arch/arm64/include/asm/pgtable-2level-hwdef.h b/arch/arm64/include/asm/pgtable-2level-hwdef.h
new file mode 100644
index 0000000..0a8ed3f
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-2level-hwdef.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_2LEVEL_HWDEF_H
+#define __ASM_PGTABLE_2LEVEL_HWDEF_H
+
+/*
+ * With LPAE and 64KB pages, there are 2 levels of page tables. Each level has
+ * 8192 entries of 8 bytes each, occupying a 64KB page. Levels 0 and 1 are not
+ * used. The 2nd level table (PGD for Linux) can cover a range of 4TB, each
+ * entry representing 512MB. The user and kernel address spaces are limited to
+ * 512GB and therefore we only use 1024 entries in the PGD.
+ */
+#define PTRS_PER_PTE		8192
+#define PTRS_PER_PGD		1024
+
+/*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map.
+ */
+#define PGDIR_SHIFT		29
+#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
+#define PGDIR_MASK		(~(PGDIR_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT		29
+#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
+#define SECTION_MASK		(~(SECTION_SIZE-1))
+
+#endif
diff --git a/arch/arm64/include/asm/pgtable-2level-types.h b/arch/arm64/include/asm/pgtable-2level-types.h
new file mode 100644
index 0000000..3c3ca7d
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-2level-types.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_2LEVEL_TYPES_H
+#define __ASM_PGTABLE_2LEVEL_TYPES_H
+
+typedef u64 pteval_t;
+typedef u64 pgdval_t;
+typedef pgdval_t pmdval_t;
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pteval_t pte; } pte_t;
+typedef struct { pgdval_t pgd; } pgd_t;
+typedef struct { pteval_t pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pgd_val(x)	((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pgd(x)	((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else	/* !STRICT_MM_TYPECHECKS */
+
+typedef pteval_t pte_t;
+typedef pgdval_t pgd_t;
+typedef pteval_t pgprot_t;
+
+#define pte_val(x)	(x)
+#define pgd_val(x)	(x)
+#define pgprot_val(x)	(x)
+
+#define __pte(x)	(x)
+#define __pgd(x)	(x)
+#define __pgprot(x)	(x)
+
+#endif	/* STRICT_MM_TYPECHECKS */
+
+#include <asm-generic/pgtable-nopmd.h>
+
+#endif	/* __ASM_PGTABLE_2LEVEL_TYPES_H */
diff --git a/arch/arm64/include/asm/pgtable-3level-hwdef.h b/arch/arm64/include/asm/pgtable-3level-hwdef.h
new file mode 100644
index 0000000..3dbf941
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-3level-hwdef.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_3LEVEL_HWDEF_H
+#define __ASM_PGTABLE_3LEVEL_HWDEF_H
+
+/*
+ * With LPAE and 4KB pages, there are 3 levels of page tables. Each level has
+ * 512 entries of 8 bytes each, occupying a 4K page. The first level table
+ * covers a range of 512GB, each entry representing 1GB. The user and kernel
+ * address spaces are limited to 512GB each.
+ */
+#define PTRS_PER_PTE		512
+#define PTRS_PER_PMD		512
+#define PTRS_PER_PGD		512
+
+/*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map.
+ */
+#define PGDIR_SHIFT		30
+#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
+#define PGDIR_MASK		(~(PGDIR_SIZE-1))
+
+/*
+ * PMD_SHIFT determines the size a middle-level page table entry can map.
+ */
+#define PMD_SHIFT		21
+#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
+#define PMD_MASK		(~(PMD_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT		21
+#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
+#define SECTION_MASK		(~(SECTION_SIZE-1))
+
+#endif
diff --git a/arch/arm64/include/asm/pgtable-3level-types.h b/arch/arm64/include/asm/pgtable-3level-types.h
new file mode 100644
index 0000000..4489615
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-3level-types.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_3LEVEL_TYPES_H
+#define __ASM_PGTABLE_3LEVEL_TYPES_H
+
+typedef u64 pteval_t;
+typedef u64 pmdval_t;
+typedef u64 pgdval_t;
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pteval_t pte; } pte_t;
+typedef struct { pmdval_t pmd; } pmd_t;
+typedef struct { pgdval_t pgd; } pgd_t;
+typedef struct { pteval_t pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)	((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)	((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else	/* !STRICT_MM_TYPECHECKS */
+
+typedef pteval_t pte_t;
+typedef pmdval_t pmd_t;
+typedef pgdval_t pgd_t;
+typedef pteval_t pgprot_t;
+
+#define pte_val(x)	(x)
+#define pmd_val(x)	(x)
+#define pgd_val(x)	(x)
+#define pgprot_val(x)	(x)
+
+#define __pte(x)	(x)
+#define __pmd(x)	(x)
+#define __pgd(x)	(x)
+#define __pgprot(x)	(x)
+
+#endif	/* STRICT_MM_TYPECHECKS */
+
+#include <asm-generic/pgtable-nopud.h>
+
+#endif	/* __ASM_PGTABLE_3LEVEL_TYPES_H */
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
new file mode 100644
index 0000000..561fb08
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_HWDEF_H
+#define __ASM_PGTABLE_HWDEF_H
+
+#ifdef CONFIG_ARM64_64K_PAGES
+#include <asm/pgtable-2level-hwdef.h>
+#else
+#include <asm/pgtable-3level-hwdef.h>
+#endif
+
+/*
+ * Hardware page table definitions.
+ *
+ * Level 2 descriptor (PMD).
+ */
+#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
+#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
+
+/*
+ * Section
+ */
+#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
+#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
+#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
+#define PMD_SECT_XN		(_AT(pmdval_t, 1) << 54)
+
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
+#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)
+
+/*
+ * Level 3 descriptor (PTE).
+ */
+#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
+#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
+#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
+#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
+#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
+#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
+#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
+#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
+#define PTE_XN			(_AT(pteval_t, 1) << 54)	/* XN */
+
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
+#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
+
+/*
+ * 40-bit physical address supported.
+ */
+#define PHYS_MASK_SHIFT		(40)
+#define PHYS_MASK		((1UL << PHYS_MASK_SHIFT) - 1)
+
+/*
+ * TCR flags.
+ */
+#define TCR_TxSZ(x)		(((64 - (x)) << 16) | ((64 - (x)) << 0))
+#define TCR_IRGN_NC		((0 << 8) | (0 << 24))
+#define TCR_IRGN_WBWA		((1 << 8) | (1 << 24))
+#define TCR_IRGN_WT		((2 << 8) | (2 << 24))
+#define TCR_IRGN_WBnWA		((3 << 8) | (3 << 24))
+#define TCR_IRGN_MASK		((3 << 8) | (3 << 24))
+#define TCR_ORGN_NC		((0 << 10) | (0 << 26))
+#define TCR_ORGN_WBWA		((1 << 10) | (1 << 26))
+#define TCR_ORGN_WT		((2 << 10) | (2 << 26))
+#define TCR_ORGN_WBnWA		((3 << 10) | (3 << 26))
+#define TCR_ORGN_MASK		((3 << 10) | (3 << 26))
+#define TCR_SHARED		((3 << 12) | (3 << 28))
+#define TCR_TG0_64K		(1 << 14)
+#define TCR_TG1_64K		(1 << 30)
+#define TCR_IPS_40BIT		(2 << 32)
+#define TCR_ASID16		(1 << 36)
+
+#endif
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
new file mode 100644
index 0000000..6981da0
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGTABLE_H
+#define __ASM_PGTABLE_H
+
+#include <asm/proc-fns.h>
+
+#include <asm/memory.h>
+#include <asm/pgtable-hwdef.h>
+
+/*
+ * Software defined PTE bits definition.
+ */
+#define PTE_VALID		(_AT(pteval_t, 1) << 0)	/* pte_present() check */
+#define PTE_FILE		(_AT(pteval_t, 1) << 2)	/* only when !pte_present() */
+#define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
+#define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
+
+/*
+ * VMALLOC and SPARSEMEM_VMEMMAP ranges.
+ */
+#define VMALLOC_START		UL(0xffffff8000000000)
+#define VMALLOC_END		(PAGE_OFFSET - UL(0x400000000) - SZ_64K)
+
+#define vmemmap			((struct page *)(VMALLOC_END + SZ_64K))
+
+#define FIRST_USER_ADDRESS	0
+
+#ifndef __ASSEMBLY__
+extern void __pte_error(const char *file, int line, unsigned long val);
+extern void __pmd_error(const char *file, int line, unsigned long val);
+extern void __pgd_error(const char *file, int line, unsigned long val);
+
+#define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte_val(pte))
+#ifndef CONFIG_ARM64_64K_PAGES
+#define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd_val(pmd))
+#endif
+#define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd_val(pgd))
+
+/*
+ * The pgprot_* and protection_map entries will be fixed up at runtime to
+ * include the cachable and bufferable bits based on memory policy, as well as
+ * any architecture dependent bits like global/ASID and SMP shared mapping
+ * bits.
+ */
+#define _PAGE_DEFAULT		PTE_TYPE_PAGE | PTE_AF
+
+extern pgprot_t pgprot_default;
+
+#define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))
+
+#define PAGE_NONE		_MOD_PROT(pgprot_default, PTE_NG | PTE_XN | PTE_RDONLY)
+#define PAGE_SHARED		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN)
+#define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_default, PTE_USER | PTE_NG)
+#define PAGE_COPY		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
+#define PAGE_COPY_EXEC		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY)
+#define PAGE_READONLY		_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
+#define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_RDONLY)
+#define PAGE_KERNEL		_MOD_PROT(pgprot_default, PTE_XN | PTE_DIRTY)
+#define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_default, PTE_DIRTY)
+
+#define __PAGE_NONE		__pgprot(_PAGE_DEFAULT | PTE_NG | PTE_XN | PTE_RDONLY)
+#define __PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN)
+#define __PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG)
+#define __PAGE_COPY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
+#define __PAGE_COPY_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY)
+#define __PAGE_READONLY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_XN | PTE_RDONLY)
+#define __PAGE_READONLY_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_RDONLY)
+
+#endif /* __ASSEMBLY__ */
+
+#define __P000  __PAGE_NONE
+#define __P001  __PAGE_READONLY
+#define __P010  __PAGE_COPY
+#define __P011  __PAGE_COPY
+#define __P100  __PAGE_READONLY_EXEC
+#define __P101  __PAGE_READONLY_EXEC
+#define __P110  __PAGE_COPY_EXEC
+#define __P111  __PAGE_COPY_EXEC
+
+#define __S000  __PAGE_NONE
+#define __S001  __PAGE_READONLY
+#define __S010  __PAGE_SHARED
+#define __S011  __PAGE_SHARED
+#define __S100  __PAGE_READONLY_EXEC
+#define __S101  __PAGE_READONLY_EXEC
+#define __S110  __PAGE_SHARED_EXEC
+#define __S111  __PAGE_SHARED_EXEC
+
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern struct page *empty_zero_page;
+#define ZERO_PAGE(vaddr)	(empty_zero_page)
+
+#define pte_pfn(pte)		((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
+
+#define pfn_pte(pfn,prot)	(__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+
+#define pte_none(pte)		(!pte_val(pte))
+#define pte_clear(mm,addr,ptep)	set_pte(ptep, __pte(0))
+#define pte_page(pte)		(pfn_to_page(pte_pfn(pte)))
+#define pte_offset_kernel(dir,addr)	(pmd_page_vaddr(*(dir)) + __pte_index(addr))
+
+#define pte_offset_map(dir,addr)	pte_offset_kernel((dir), (addr))
+#define pte_offset_map_nested(dir,addr)	pte_offset_kernel((dir), (addr))
+#define pte_unmap(pte)			do { } while (0)
+#define pte_unmap_nested(pte)		do { } while (0)
+
+/*
+ * The following only work if pte_present(). Undefined behaviour otherwise.
+ */
+#define pte_present(pte)	(pte_val(pte) & PTE_VALID)
+#define pte_dirty(pte)		(pte_val(pte) & PTE_DIRTY)
+#define pte_young(pte)		(pte_val(pte) & PTE_AF)
+#define pte_special(pte)	(pte_val(pte) & PTE_SPECIAL)
+#define pte_write(pte)		(!(pte_val(pte) & PTE_RDONLY))
+#define pte_exec(pte)		(!(pte_val(pte) & PTE_XN))
+
+#define pte_present_exec_user(pte) \
+	((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_XN)) == \
+	 (PTE_VALID | PTE_USER))
+
+#define PTE_BIT_FUNC(fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+PTE_BIT_FUNC(wrprotect, |= PTE_RDONLY);
+PTE_BIT_FUNC(mkwrite,   &= ~PTE_RDONLY);
+PTE_BIT_FUNC(mkclean,   &= ~PTE_DIRTY);
+PTE_BIT_FUNC(mkdirty,   |= PTE_DIRTY);
+PTE_BIT_FUNC(mkold,     &= ~PTE_AF);
+PTE_BIT_FUNC(mkyoung,   |= PTE_AF);
+PTE_BIT_FUNC(mkspecial, |= PTE_SPECIAL);
+
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+	*ptep = pte;
+}
+
+extern void __sync_icache_dcache(pte_t pteval);
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pte)
+{
+	if (pte_present_exec_user(pte))
+		__sync_icache_dcache(pte);
+	set_pte(ptep, pte);
+}
+
+/*
+ * Huge pte definitions.
+ */
+#define pte_huge(pte)		((pte_val(pte) & PTE_TYPE_MASK) == PTE_TYPE_HUGEPAGE)
+#define pte_mkhuge(pte)		(__pte((pte_val(pte) & ~PTE_TYPE_MASK) | PTE_TYPE_HUGEPAGE))
+
+#define __pgprot_modify(prot,mask,bits)		\
+	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
+
+#define __HAVE_ARCH_PTE_SPECIAL
+
+/*
+ * Mark the prot value as uncacheable and unbufferable.
+ */
+#define pgprot_noncached(prot) \
+	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
+#define pgprot_writecombine(prot) \
+	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
+#define pgprot_dmacoherent(prot) \
+	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+				     unsigned long size, pgprot_t vma_prot);
+
+#define pmd_none(pmd)		(!pmd_val(pmd))
+#define pmd_present(pmd)	(pmd_val(pmd))
+
+#define pmd_bad(pmd)		(!(pmd_val(pmd) & 2))
+
+static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
+{
+	*pmdp = pmd;
+	dsb();
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+	set_pmd(pmdp, __pmd(0));
+}
+
+static inline pte_t *pmd_page_vaddr(pmd_t pmd)
+{
+	return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
+}
+
+#define pmd_page(pmd)		pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page,prot)	pfn_pte(page_to_pfn(page),prot)
+
+#ifndef CONFIG_ARM64_64K_PAGES
+
+#define pud_none(pud)		(!pud_val(pud))
+#define pud_bad(pud)		(!(pud_val(pud) & 2))
+#define pud_present(pud)	(pud_val(pud))
+
+static inline void set_pud(pud_t *pudp, pud_t pud)
+{
+	*pudp = pud;
+	dsb();
+}
+
+static inline void pud_clear(pud_t *pudp)
+{
+	set_pud(pudp, __pud(0));
+}
+
+static inline pmd_t *pud_page_vaddr(pud_t pud)
+{
+	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
+}
+
+#endif	/* CONFIG_ARM64_64K_PAGES */
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(addr)		(((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+
+#define pgd_offset(mm, addr)	((mm)->pgd+pgd_index(addr))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr)	pgd_offset(&init_mm, addr)
+
+/* Find an entry in the second-level page table.. */
+#ifndef CONFIG_ARM64_64K_PAGES
+#define pmd_index(addr)		(((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
+{
+	return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
+}
+#endif
+
+/* Find an entry in the third-level page table.. */
+#define __pte_index(addr)	(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+	const pteval_t mask = PTE_USER | PTE_XN | PTE_RDONLY;
+	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
+	return pte;
+}
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
+
+#define SWAPPER_DIR_SIZE	(3 * PAGE_SIZE)
+#define IDMAP_DIR_SIZE		(2 * PAGE_SIZE)
+
+/*
+ * Encode and decode a swap entry:
+ *	bits 0-1:	present (must be zero)
+ *	bit  2:		PTE_FILE
+ *	bits 3-8:	swap type
+ *	bits 9-63:	swap offset
+ */
+#define __SWP_TYPE_SHIFT	3
+#define __SWP_TYPE_BITS		6
+#define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
+#define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
+
+#define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
+#define __swp_offset(x)		((x).val >> __SWP_OFFSET_SHIFT)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
+
+#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(swp)	((pte_t) { (swp).val })
+
+/*
+ * Ensure that there are not more swap files than can be encoded in the kernel
+ * the PTEs.
+ */
+#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
+
+/*
+ * Encode and decode a file entry:
+ *	bits 0-1:	present (must be zero)
+ *	bit  2:		PTE_FILE
+ *	bits 3-63:	file offset / PAGE_SIZE
+ */
+#define pte_file(pte)		(pte_val(pte) & PTE_FILE)
+#define pte_to_pgoff(x)		(pte_val(x) >> 3)
+#define pgoff_to_pte(x)		__pte(((x) << 3) | PTE_FILE)
+
+#define PTE_FILE_MAX_BITS	61
+
+extern int kern_addr_valid(unsigned long addr);
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * remap a physical page `pfn' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+#define io_remap_pfn_range(vma,from,pfn,size,prot) \
+		remap_pfn_range(vma, from, pfn, size, prot)
+
+#define pgtable_cache_init() do { } while (0)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_PGTABLE_H */
diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h
new file mode 100644
index 0000000..1be62bc
--- /dev/null
+++ b/arch/arm64/include/asm/sparsemem.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SPARSEMEM_H
+#define __ASM_SPARSEMEM_H
+
+#ifdef CONFIG_SPARSEMEM
+#define MAX_PHYSMEM_BITS	40
+#define SECTION_SIZE_BITS	30
+#endif
+
+#endif



From catalin.marinas at arm.com  Tue Aug 14 13:52:24 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:24 +0100
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-24-git-send-email-catalin.marinas@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds ptrace, debug monitors and hardware breakpoints support.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/debug-monitors.h |   88 +++
 arch/arm64/include/asm/hw_breakpoint.h  |  137 +++++
 arch/arm64/kernel/debug-monitors.c      |  288 ++++++++++
 arch/arm64/kernel/hw_breakpoint.c       |  880 +++++++++++++++++++++++++++++++
 arch/arm64/kernel/ptrace.c              |  834 +++++++++++++++++++++++++++++
 5 files changed, 2227 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/debug-monitors.h
 create mode 100644 arch/arm64/include/asm/hw_breakpoint.h
 create mode 100644 arch/arm64/kernel/debug-monitors.c
 create mode 100644 arch/arm64/kernel/hw_breakpoint.c
 create mode 100644 arch/arm64/kernel/ptrace.c

diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
new file mode 100644
index 0000000..7eaa0b3
--- /dev/null
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_DEBUG_MONITORS_H
+#define __ASM_DEBUG_MONITORS_H
+
+#ifdef __KERNEL__
+
+#define	DBG_ESR_EVT(x)		(((x) >> 27) & 0x7)
+
+/* AArch64 */
+#define DBG_ESR_EVT_HWBP	0x0
+#define DBG_ESR_EVT_HWSS	0x1
+#define DBG_ESR_EVT_HWWP	0x2
+#define DBG_ESR_EVT_BRK		0x6
+
+enum debug_el {
+	DBG_ACTIVE_EL0 = 0,
+	DBG_ACTIVE_EL1,
+};
+
+/* AArch32 */
+#define DBG_ESR_EVT_BKPT	0x4
+#define DBG_ESR_EVT_VECC	0x5
+
+#define AARCH32_BREAK_ARM	0x07f001f0
+#define AARCH32_BREAK_THUMB	0xde01
+#define AARCH32_BREAK_THUMB2_LO	0xf7f0
+#define AARCH32_BREAK_THUMB2_HI	0xa000
+
+#ifndef __ASSEMBLY__
+struct task_struct;
+
+#define local_dbg_save(flags)							\
+	do {									\
+		typecheck(unsigned long, flags);				\
+		asm volatile(							\
+		"mrs	%0, daif			// local_dbg_save\n"	\
+		"msr	daifset, #8"						\
+		: "=r" (flags) : : "memory");					\
+	} while (0)
+
+#define local_dbg_restore(flags)						\
+	do {									\
+		typecheck(unsigned long, flags);				\
+		asm volatile(							\
+		"msr	daif, %0			// local_dbg_restore\n"	\
+		: : "r" (flags) : "memory");					\
+	} while (0)
+
+#define DBG_ARCH_ID_RESERVED	0	/* In case of ptrace ABI updates. */
+
+u8 debug_monitors_arch(void);
+
+void enable_debug_monitors(enum debug_el el);
+void disable_debug_monitors(enum debug_el el);
+
+void user_rewind_single_step(struct task_struct *task);
+void user_fastforward_single_step(struct task_struct *task);
+
+void kernel_enable_single_step(struct pt_regs *regs);
+void kernel_disable_single_step(void);
+int kernel_active_single_step(void);
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+int reinstall_suspended_bps(struct pt_regs *regs);
+#else
+static inline int reinstall_suspended_bps(struct pt_regs *regs)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif	/* __ASSEMBLY */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_DEBUG_MONITORS_H */
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
new file mode 100644
index 0000000..d064047
--- /dev/null
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_HW_BREAKPOINT_H
+#define __ASM_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+
+struct arch_hw_breakpoint_ctrl {
+	u32 __reserved	: 19,
+	len		: 8,
+	type		: 2,
+	privilege	: 2,
+	enabled		: 1;
+};
+
+struct arch_hw_breakpoint {
+	u64 address;
+	u64 trigger;
+	struct arch_hw_breakpoint_ctrl ctrl;
+};
+
+static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
+{
+	return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
+		ctrl.enabled;
+}
+
+static inline void decode_ctrl_reg(u32 reg,
+				   struct arch_hw_breakpoint_ctrl *ctrl)
+{
+	ctrl->enabled	= reg & 0x1;
+	reg >>= 1;
+	ctrl->privilege	= reg & 0x3;
+	reg >>= 2;
+	ctrl->type	= reg & 0x3;
+	reg >>= 2;
+	ctrl->len	= reg & 0xff;
+}
+
+/* Breakpoint */
+#define ARM_BREAKPOINT_EXECUTE	0
+
+/* Watchpoints */
+#define ARM_BREAKPOINT_LOAD	1
+#define ARM_BREAKPOINT_STORE	2
+#define AARCH64_ESR_ACCESS_MASK	(1 << 6)
+
+/* Privilege Levels */
+#define AARCH64_BREAKPOINT_EL1	1
+#define AARCH64_BREAKPOINT_EL0	2
+
+/* Lengths */
+#define ARM_BREAKPOINT_LEN_1	0x1
+#define ARM_BREAKPOINT_LEN_2	0x3
+#define ARM_BREAKPOINT_LEN_4	0xf
+#define ARM_BREAKPOINT_LEN_8	0xff
+
+/* Kernel stepping */
+#define ARM_KERNEL_STEP_NONE	0
+#define ARM_KERNEL_STEP_ACTIVE	1
+#define ARM_KERNEL_STEP_SUSPEND	2
+
+/*
+ * Limits.
+ * Changing these will require modifications to the register accessors.
+ */
+#define ARM_MAX_BRP		16
+#define ARM_MAX_WRP		16
+#define ARM_MAX_HBP_SLOTS	(ARM_MAX_BRP + ARM_MAX_WRP)
+
+/* Virtual debug register bases. */
+#define AARCH64_DBG_REG_BVR	0
+#define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
+#define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
+#define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
+
+/* Debug register names. */
+#define AARCH64_DBG_REG_NAME_BVR	"bvr"
+#define AARCH64_DBG_REG_NAME_BCR	"bcr"
+#define AARCH64_DBG_REG_NAME_WVR	"wvr"
+#define AARCH64_DBG_REG_NAME_WCR	"wcr"
+
+/* Accessor macros for the debug registers. */
+#define AARCH64_DBG_READ(N, REG, VAL) do {\
+	asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
+} while (0)
+
+#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
+	asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
+} while (0)
+
+struct task_struct;
+struct notifier_block;
+struct perf_event;
+struct pmu;
+
+extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+				  int *gen_len, int *gen_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+					   unsigned long val, void *data);
+
+extern int arch_install_hw_breakpoint(struct perf_event *bp);
+extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+extern void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern int hw_breakpoint_slots(int type);
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+extern void hw_breakpoint_thread_switch(struct task_struct *next);
+extern void ptrace_hw_copy_thread(struct task_struct *task);
+#else
+static inline void hw_breakpoint_thread_switch(struct task_struct *next)
+{
+}
+static inline void ptrace_hw_copy_thread(struct task_struct *task)
+{
+}
+#endif
+
+extern struct pmu perf_ops_bp;
+
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_BREAKPOINT_H */
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
new file mode 100644
index 0000000..0c3ba9f
--- /dev/null
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -0,0 +1,288 @@
+/*
+ * ARMv8 single-step debug support and mdscr context switching.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
+#include <linux/hardirq.h>
+#include <linux/init.h>
+#include <linux/ptrace.h>
+#include <linux/stat.h>
+
+#include <asm/debug-monitors.h>
+#include <asm/local.h>
+#include <asm/cputype.h>
+#include <asm/system_misc.h>
+
+/* Low-level stepping controls. */
+#define DBG_MDSCR_SS		(1 << 0)
+#define DBG_SPSR_SS		(1 << 21)
+
+/* MDSCR_EL1 enabling bits */
+#define DBG_MDSCR_KDE		(1 << 13)
+#define DBG_MDSCR_MDE		(1 << 15)
+#define DBG_MDSCR_MASK		~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
+
+/* Determine debug architecture. */
+u8 debug_monitors_arch(void)
+{
+	return read_cpuid(ID_AA64DFR0_EL1) & 0xf;
+}
+
+/*
+ * MDSCR access routines.
+ */
+static void mdscr_write(u32 mdscr)
+{
+	unsigned long flags;
+	local_dbg_save(flags);
+	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
+	local_dbg_restore(flags);
+}
+
+static u32 mdscr_read(void)
+{
+	u32 mdscr;
+	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
+	return mdscr;
+}
+
+/*
+ * Allow root to disable self-hosted debug from userspace.
+ * This is useful if you want to connect an external JTAG debugger.
+ */
+static u32 debug_enabled = 1;
+
+static int create_debug_debugfs_entry(void)
+{
+	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
+	return 0;
+}
+fs_initcall(create_debug_debugfs_entry);
+
+static int __init early_debug_disable(char *buf)
+{
+	debug_enabled = 0;
+	return 0;
+}
+
+early_param("nodebugmon", early_debug_disable);
+
+/*
+ * Keep track of debug users on each core.
+ * The ref counts are per-cpu so we use a local_t type.
+ */
+static DEFINE_PER_CPU(local_t, mde_ref_count);
+static DEFINE_PER_CPU(local_t, kde_ref_count);
+
+void enable_debug_monitors(enum debug_el el)
+{
+	u32 mdscr, enable = 0;
+
+	WARN_ON(preemptible());
+
+	if (local_inc_return(&__get_cpu_var(mde_ref_count)) == 1)
+		enable = DBG_MDSCR_MDE;
+
+	if (el == DBG_ACTIVE_EL1 &&
+	    local_inc_return(&__get_cpu_var(kde_ref_count)) == 1)
+		enable |= DBG_MDSCR_KDE;
+
+	if (enable && debug_enabled) {
+		mdscr = mdscr_read();
+		mdscr |= enable;
+		mdscr_write(mdscr);
+	}
+}
+
+void disable_debug_monitors(enum debug_el el)
+{
+	u32 mdscr, disable = 0;
+
+	WARN_ON(preemptible());
+
+	if (local_dec_and_test(&__get_cpu_var(mde_ref_count)))
+		disable = ~DBG_MDSCR_MDE;
+
+	if (el == DBG_ACTIVE_EL1 &&
+	    local_dec_and_test(&__get_cpu_var(kde_ref_count)))
+		disable &= ~DBG_MDSCR_KDE;
+
+	if (disable) {
+		mdscr = mdscr_read();
+		mdscr &= disable;
+		mdscr_write(mdscr);
+	}
+}
+
+/*
+ * OS lock clearing.
+ */
+static void clear_os_lock(void *unused)
+{
+	asm volatile("msr mdscr_el1, %0" : : "r" (0));
+	isb();
+	asm volatile("msr oslar_el1, %0" : : "r" (0));
+	isb();
+}
+
+static int __cpuinit os_lock_notify(struct notifier_block *self,
+				    unsigned long action, void *data)
+{
+	int cpu = (unsigned long)data;
+	if (action == CPU_ONLINE)
+		smp_call_function_single(cpu, clear_os_lock, NULL, 1);
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata os_lock_nb = {
+	.notifier_call = os_lock_notify,
+};
+
+static int __cpuinit debug_monitors_init(void)
+{
+	/* Clear the OS lock. */
+	smp_call_function(clear_os_lock, NULL, 1);
+	clear_os_lock(NULL);
+
+	/* Register hotplug handler. */
+	register_cpu_notifier(&os_lock_nb);
+	return 0;
+}
+postcore_initcall(debug_monitors_init);
+
+/*
+ * Single step API and exception handling.
+ */
+static void set_regs_spsr_ss(struct pt_regs *regs)
+{
+	unsigned long spsr;
+
+	spsr = regs->pstate;
+	spsr &= ~DBG_SPSR_SS;
+	spsr |= DBG_SPSR_SS;
+	regs->pstate = spsr;
+}
+
+static void clear_regs_spsr_ss(struct pt_regs *regs)
+{
+	unsigned long spsr;
+
+	spsr = regs->pstate;
+	spsr &= ~DBG_SPSR_SS;
+	regs->pstate = spsr;
+}
+
+static int single_step_handler(unsigned long addr, unsigned int esr,
+			       struct pt_regs *regs)
+{
+	siginfo_t info;
+
+	/*
+	 * If we are stepping a pending breakpoint, call the hw_breakpoint
+	 * handler first.
+	 */
+	if (!reinstall_suspended_bps(regs))
+		return 0;
+
+	if (user_mode(regs)) {
+		info.si_signo = SIGTRAP;
+		info.si_errno = 0;
+		info.si_code  = TRAP_HWBKPT;
+		info.si_addr  = (void __user *)instruction_pointer(regs);
+		force_sig_info(SIGTRAP, &info, current);
+
+		/*
+		 * ptrace will disable single step unless explicitly
+		 * asked to re-enable it. For other clients, it makes
+		 * sense to leave it enabled (i.e. rewind the controls
+		 * to the active-not-pending state).
+		 */
+		user_rewind_single_step(current);
+	} else {
+		/* TODO: route to KGDB */
+		pr_warning("Unexpected kernel single-step exception at EL1\n");
+		/*
+		 * Re-enable stepping since we know that we will be
+		 * returning to regs.
+		 */
+		set_regs_spsr_ss(regs);
+	}
+
+	return 0;
+}
+
+static int __init single_step_init(void)
+{
+	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
+			      TRAP_HWBKPT, "single-step handler");
+	return 0;
+}
+arch_initcall(single_step_init);
+
+/* Re-enable single step for syscall restarting. */
+void user_rewind_single_step(struct task_struct *task)
+{
+	/*
+	 * If single step is active for this thread, then set SPSR.SS
+	 * to 1 to avoid returning to the active-pending state.
+	 */
+	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
+		set_regs_spsr_ss(task_pt_regs(task));
+}
+
+void user_fastforward_single_step(struct task_struct *task)
+{
+	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
+		clear_regs_spsr_ss(task_pt_regs(task));
+}
+
+/* Kernel API */
+void kernel_enable_single_step(struct pt_regs *regs)
+{
+	WARN_ON(!irqs_disabled());
+	set_regs_spsr_ss(regs);
+	mdscr_write(mdscr_read() | DBG_MDSCR_SS);
+	enable_debug_monitors(DBG_ACTIVE_EL1);
+}
+
+void kernel_disable_single_step(void)
+{
+	WARN_ON(!irqs_disabled());
+	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
+	disable_debug_monitors(DBG_ACTIVE_EL1);
+}
+
+int kernel_active_single_step(void)
+{
+	WARN_ON(!irqs_disabled());
+	return mdscr_read() & DBG_MDSCR_SS;
+}
+
+/* ptrace API */
+void user_enable_single_step(struct task_struct *task)
+{
+	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
+	set_regs_spsr_ss(task_pt_regs(task));
+}
+
+void user_disable_single_step(struct task_struct *task)
+{
+	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
+}
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
new file mode 100644
index 0000000..5ab825c
--- /dev/null
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -0,0 +1,880 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers.
+ *
+ * Copyright (C) 2012 ARM Limited
+ * Author: Will Deacon <will.deacon at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define pr_fmt(fmt) "hw-breakpoint: " fmt
+
+#include <linux/errno.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/perf_event.h>
+#include <linux/ptrace.h>
+#include <linux/smp.h>
+
+#include <asm/compat.h>
+#include <asm/current.h>
+#include <asm/debug-monitors.h>
+#include <asm/hw_breakpoint.h>
+#include <asm/kdebug.h>
+#include <asm/traps.h>
+#include <asm/cputype.h>
+#include <asm/system_misc.h>
+
+/* Breakpoint currently in use for each BRP. */
+static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
+
+/* Watchpoint currently in use for each WRP. */
+static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
+
+/* Currently stepping a per-CPU kernel breakpoint. */
+static DEFINE_PER_CPU(int, stepping_kernel_bp);
+
+/* Number of BRP/WRP registers on this CPU. */
+static int core_num_brps;
+static int core_num_wrps;
+
+/* Determine number of BRP registers available. */
+static int get_num_brps(void)
+{
+	return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
+}
+
+/* Determine number of WRP registers available. */
+static int get_num_wrps(void)
+{
+	return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
+}
+
+int hw_breakpoint_slots(int type)
+{
+	/*
+	 * We can be called early, so don't rely on
+	 * our static variables being initialised.
+	 */
+	switch (type) {
+	case TYPE_INST:
+		return get_num_brps();
+	case TYPE_DATA:
+		return get_num_wrps();
+	default:
+		pr_warning("unknown slot type: %d\n", type);
+		return 0;
+	}
+}
+
+#define READ_WB_REG_CASE(OFF, N, REG, VAL)	\
+	case (OFF + N):				\
+		AARCH64_DBG_READ(N, REG, VAL);	\
+		break
+
+#define WRITE_WB_REG_CASE(OFF, N, REG, VAL)	\
+	case (OFF + N):				\
+		AARCH64_DBG_WRITE(N, REG, VAL);	\
+		break
+
+#define GEN_READ_WB_REG_CASES(OFF, REG, VAL)	\
+	READ_WB_REG_CASE(OFF,  0, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  1, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  2, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  3, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  4, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  5, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  6, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  7, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  8, REG, VAL);	\
+	READ_WB_REG_CASE(OFF,  9, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 10, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 11, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 12, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 13, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 14, REG, VAL);	\
+	READ_WB_REG_CASE(OFF, 15, REG, VAL)
+
+#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL)	\
+	WRITE_WB_REG_CASE(OFF,  0, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  1, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  2, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  3, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  4, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  5, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  6, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  7, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  8, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF,  9, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 10, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 11, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 12, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 13, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 14, REG, VAL);	\
+	WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
+
+static u64 read_wb_reg(int reg, int n)
+{
+	u64 val = 0;
+
+	switch (reg + n) {
+	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
+	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
+	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
+	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
+	default:
+		pr_warning("attempt to read from unknown breakpoint register %d\n", n);
+	}
+
+	return val;
+}
+
+static void write_wb_reg(int reg, int n, u64 val)
+{
+	switch (reg + n) {
+	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
+	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
+	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
+	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
+	default:
+		pr_warning("attempt to write to unknown breakpoint register %d\n", n);
+	}
+	isb();
+}
+
+/*
+ * Convert a breakpoint privilege level to the corresponding exception
+ * level.
+ */
+static enum debug_el debug_exception_level(int privilege)
+{
+	switch (privilege) {
+	case AARCH64_BREAKPOINT_EL0:
+		return DBG_ACTIVE_EL0;
+	case AARCH64_BREAKPOINT_EL1:
+		return DBG_ACTIVE_EL1;
+	default:
+		pr_warning("invalid breakpoint privilege level %d\n", privilege);
+		return -EINVAL;
+	}
+}
+
+/*
+ * Install a perf counter breakpoint.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	struct perf_event **slot, **slots;
+	struct debug_info *debug_info = &current->thread.debug;
+	int i, max_slots, ctrl_reg, val_reg, reg_enable;
+	u32 ctrl;
+
+	if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+		/* Breakpoint */
+		ctrl_reg = AARCH64_DBG_REG_BCR;
+		val_reg = AARCH64_DBG_REG_BVR;
+		slots = __get_cpu_var(bp_on_reg);
+		max_slots = core_num_brps;
+		reg_enable = !debug_info->bps_disabled;
+	} else {
+		/* Watchpoint */
+		ctrl_reg = AARCH64_DBG_REG_WCR;
+		val_reg = AARCH64_DBG_REG_WVR;
+		slots = __get_cpu_var(wp_on_reg);
+		max_slots = core_num_wrps;
+		reg_enable = !debug_info->wps_disabled;
+	}
+
+	for (i = 0; i < max_slots; ++i) {
+		slot = &slots[i];
+
+		if (!*slot) {
+			*slot = bp;
+			break;
+		}
+	}
+
+	if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
+		return -ENOSPC;
+
+	/* Ensure debug monitors are enabled at the correct exception level.  */
+	enable_debug_monitors(debug_exception_level(info->ctrl.privilege));
+
+	/* Setup the address register. */
+	write_wb_reg(val_reg, i, info->address);
+
+	/* Setup the control register. */
+	ctrl = encode_ctrl_reg(info->ctrl);
+	write_wb_reg(ctrl_reg, i, reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
+
+	return 0;
+}
+
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	struct perf_event **slot, **slots;
+	int i, max_slots, base;
+
+	if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+		/* Breakpoint */
+		base = AARCH64_DBG_REG_BCR;
+		slots = __get_cpu_var(bp_on_reg);
+		max_slots = core_num_brps;
+	} else {
+		/* Watchpoint */
+		base = AARCH64_DBG_REG_WCR;
+		slots = __get_cpu_var(wp_on_reg);
+		max_slots = core_num_wrps;
+	}
+
+	/* Remove the breakpoint. */
+	for (i = 0; i < max_slots; ++i) {
+		slot = &slots[i];
+
+		if (*slot == bp) {
+			*slot = NULL;
+			break;
+		}
+	}
+
+	if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
+		return;
+
+	/* Reset the control register. */
+	write_wb_reg(base, i, 0);
+
+	/* Release the debug monitors for the correct exception level.  */
+	disable_debug_monitors(debug_exception_level(info->ctrl.privilege));
+}
+
+static int get_hbp_len(u8 hbp_len)
+{
+	unsigned int len_in_bytes = 0;
+
+	switch (hbp_len) {
+	case ARM_BREAKPOINT_LEN_1:
+		len_in_bytes = 1;
+		break;
+	case ARM_BREAKPOINT_LEN_2:
+		len_in_bytes = 2;
+		break;
+	case ARM_BREAKPOINT_LEN_4:
+		len_in_bytes = 4;
+		break;
+	case ARM_BREAKPOINT_LEN_8:
+		len_in_bytes = 8;
+		break;
+	}
+
+	return len_in_bytes;
+}
+
+/*
+ * Check whether bp virtual address is in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+	unsigned int len;
+	unsigned long va;
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+	va = info->address;
+	len = get_hbp_len(info->ctrl.len);
+
+	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
+}
+
+/*
+ * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
+ * Hopefully this will disappear when ptrace can bypass the conversion
+ * to generic breakpoint descriptions.
+ */
+int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+			   int *gen_len, int *gen_type)
+{
+	/* Type */
+	switch (ctrl.type) {
+	case ARM_BREAKPOINT_EXECUTE:
+		*gen_type = HW_BREAKPOINT_X;
+		break;
+	case ARM_BREAKPOINT_LOAD:
+		*gen_type = HW_BREAKPOINT_R;
+		break;
+	case ARM_BREAKPOINT_STORE:
+		*gen_type = HW_BREAKPOINT_W;
+		break;
+	case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
+		*gen_type = HW_BREAKPOINT_RW;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Len */
+	switch (ctrl.len) {
+	case ARM_BREAKPOINT_LEN_1:
+		*gen_len = HW_BREAKPOINT_LEN_1;
+		break;
+	case ARM_BREAKPOINT_LEN_2:
+		*gen_len = HW_BREAKPOINT_LEN_2;
+		break;
+	case ARM_BREAKPOINT_LEN_4:
+		*gen_len = HW_BREAKPOINT_LEN_4;
+		break;
+	case ARM_BREAKPOINT_LEN_8:
+		*gen_len = HW_BREAKPOINT_LEN_8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * Construct an arch_hw_breakpoint from a perf_event.
+ */
+static int arch_build_bp_info(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+	/* Type */
+	switch (bp->attr.bp_type) {
+	case HW_BREAKPOINT_X:
+		info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
+		break;
+	case HW_BREAKPOINT_R:
+		info->ctrl.type = ARM_BREAKPOINT_LOAD;
+		break;
+	case HW_BREAKPOINT_W:
+		info->ctrl.type = ARM_BREAKPOINT_STORE;
+		break;
+	case HW_BREAKPOINT_RW:
+		info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Len */
+	switch (bp->attr.bp_len) {
+	case HW_BREAKPOINT_LEN_1:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_1;
+		break;
+	case HW_BREAKPOINT_LEN_2:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_2;
+		break;
+	case HW_BREAKPOINT_LEN_4:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_4;
+		break;
+	case HW_BREAKPOINT_LEN_8:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*
+	 * On AArch64, we only permit breakpoints of length 4, whereas
+	 * AArch32 also requires breakpoints of length 2 for Thumb.
+	 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
+	 */
+	if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+		if (is_compat_task()) {
+			if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
+			    info->ctrl.len != ARM_BREAKPOINT_LEN_4)
+				return -EINVAL;
+		} else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
+			/*
+			 * FIXME: Some tools (I'm looking at you perf) assume
+			 *	  that breakpoints should be sizeof(long). This
+			 *	  is nonsense. For now, we fix up the parameter
+			 *	  but we should probably return -EINVAL instead.
+			 */
+			info->ctrl.len = ARM_BREAKPOINT_LEN_4;
+		}
+	}
+
+	/* Address */
+	info->address = bp->attr.bp_addr;
+
+	/*
+	 * Privilege
+	 * Note that we disallow combined EL0/EL1 breakpoints because
+	 * that would complicate the stepping code.
+	 */
+	if (arch_check_bp_in_kernelspace(bp))
+		info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
+	else
+		info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
+
+	/* Enabled? */
+	info->ctrl.enabled = !bp->attr.disabled;
+
+	return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings.
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	int ret;
+	u64 alignment_mask, offset;
+
+	/* Build the arch_hw_breakpoint. */
+	ret = arch_build_bp_info(bp);
+	if (ret)
+		return ret;
+
+	/*
+	 * Check address alignment.
+	 * We don't do any clever alignment correction for watchpoints
+	 * because using 64-bit unaligned addresses is deprecated for
+	 * AArch64.
+	 *
+	 * AArch32 tasks expect some simple alignment fixups, so emulate
+	 * that here.
+	 */
+	if (is_compat_task()) {
+		if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
+			alignment_mask = 0x7;
+		else
+			alignment_mask = 0x3;
+		offset = info->address & alignment_mask;
+		switch (offset) {
+		case 0:
+			/* Aligned */
+			break;
+		case 1:
+			/* Allow single byte watchpoint. */
+			if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
+				break;
+		case 2:
+			/* Allow halfword watchpoints and breakpoints. */
+			if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
+				break;
+		default:
+			return -EINVAL;
+		}
+
+		info->address &= ~alignment_mask;
+		info->ctrl.len <<= offset;
+	} else {
+		if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
+			alignment_mask = 0x3;
+		else
+			alignment_mask = 0x7;
+		if (info->address & alignment_mask)
+			return -EINVAL;
+	}
+
+	/*
+	 * Disallow per-task kernel breakpoints since these would
+	 * complicate the stepping code.
+	 */
+	if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.bp_target)
+		return -EINVAL;
+
+	return 0;
+}
+
+/*
+ * Enable/disable all of the breakpoints active at the specified
+ * exception level at the register level.
+ * This is used when single-stepping after a breakpoint exception.
+ */
+static void toggle_bp_registers(int reg, enum debug_el el, int enable)
+{
+	int i, max_slots, privilege;
+	u32 ctrl;
+	struct perf_event **slots;
+
+	switch (reg) {
+	case AARCH64_DBG_REG_BCR:
+		slots = __get_cpu_var(bp_on_reg);
+		max_slots = core_num_brps;
+		break;
+	case AARCH64_DBG_REG_WCR:
+		slots = __get_cpu_var(wp_on_reg);
+		max_slots = core_num_wrps;
+		break;
+	default:
+		return;
+	}
+
+	for (i = 0; i < max_slots; ++i) {
+		if (!slots[i])
+			continue;
+
+		privilege = counter_arch_bp(slots[i])->ctrl.privilege;
+		if (debug_exception_level(privilege) != el)
+			continue;
+
+		ctrl = read_wb_reg(reg, i);
+		if (enable)
+			ctrl |= 0x1;
+		else
+			ctrl &= ~0x1;
+		write_wb_reg(reg, i, ctrl);
+	}
+}
+
+/*
+ * Debug exception handlers.
+ */
+static int breakpoint_handler(unsigned long unused, unsigned int esr,
+			      struct pt_regs *regs)
+{
+	int i, step = 0, *kernel_step;
+	u32 ctrl_reg;
+	u64 addr, val;
+	struct perf_event *bp, **slots;
+	struct debug_info *debug_info;
+	struct arch_hw_breakpoint_ctrl ctrl;
+
+	slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+	addr = instruction_pointer(regs);
+	debug_info = &current->thread.debug;
+
+	for (i = 0; i < core_num_brps; ++i) {
+		rcu_read_lock();
+
+		bp = slots[i];
+
+		if (bp == NULL)
+			goto unlock;
+
+		/* Check if the breakpoint value matches. */
+		val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
+		if (val != (addr & ~0x3))
+			goto unlock;
+
+		/* Possible match, check the byte address select to confirm. */
+		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
+		decode_ctrl_reg(ctrl_reg, &ctrl);
+		if (!((1 << (addr & 0x3)) & ctrl.len))
+			goto unlock;
+
+		counter_arch_bp(bp)->trigger = addr;
+		perf_bp_event(bp, regs);
+
+		/* Do we need to handle the stepping? */
+		if (!bp->overflow_handler)
+			step = 1;
+unlock:
+		rcu_read_unlock();
+	}
+
+	if (!step)
+		return 0;
+
+	if (user_mode(regs)) {
+		debug_info->bps_disabled = 1;
+		toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
+
+		/* If we're already stepping a watchpoint, just return. */
+		if (debug_info->wps_disabled)
+			return 0;
+
+		if (test_thread_flag(TIF_SINGLESTEP))
+			debug_info->suspended_step = 1;
+		else
+			user_enable_single_step(current);
+	} else {
+		toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
+		kernel_step = &__get_cpu_var(stepping_kernel_bp);
+
+		if (*kernel_step != ARM_KERNEL_STEP_NONE)
+			return 0;
+
+		if (kernel_active_single_step()) {
+			*kernel_step = ARM_KERNEL_STEP_SUSPEND;
+		} else {
+			*kernel_step = ARM_KERNEL_STEP_ACTIVE;
+			kernel_enable_single_step(regs);
+		}
+	}
+
+	return 0;
+}
+
+static int watchpoint_handler(unsigned long addr, unsigned int esr,
+			      struct pt_regs *regs)
+{
+	int i, step = 0, *kernel_step, access;
+	u32 ctrl_reg;
+	u64 val, alignment_mask;
+	struct perf_event *wp, **slots;
+	struct debug_info *debug_info;
+	struct arch_hw_breakpoint *info;
+	struct arch_hw_breakpoint_ctrl ctrl;
+
+	slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
+	debug_info = &current->thread.debug;
+
+	for (i = 0; i < core_num_wrps; ++i) {
+		rcu_read_lock();
+
+		wp = slots[i];
+
+		if (wp == NULL)
+			goto unlock;
+
+		info = counter_arch_bp(wp);
+		/* AArch32 watchpoints are either 4 or 8 bytes aligned. */
+		if (is_compat_task()) {
+			if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
+				alignment_mask = 0x7;
+			else
+				alignment_mask = 0x3;
+		} else {
+			alignment_mask = 0x7;
+		}
+
+		/* Check if the watchpoint value matches. */
+		val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
+		if (val != (addr & ~alignment_mask))
+			goto unlock;
+
+		/* Possible match, check the byte address select to confirm. */
+		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
+		decode_ctrl_reg(ctrl_reg, &ctrl);
+		if (!((1 << (addr & alignment_mask)) & ctrl.len))
+			goto unlock;
+
+		/*
+		 * Check that the access type matches.
+		 * 0 => load, otherwise => store
+		 */
+		access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
+			 HW_BREAKPOINT_R;
+		if (!(access & hw_breakpoint_type(wp)))
+			goto unlock;
+
+		info->trigger = addr;
+		perf_bp_event(wp, regs);
+
+		/* Do we need to handle the stepping? */
+		if (!wp->overflow_handler)
+			step = 1;
+
+unlock:
+		rcu_read_unlock();
+	}
+
+	if (!step)
+		return 0;
+
+	/*
+	 * We always disable EL0 watchpoints because the kernel can
+	 * cause these to fire via an unprivileged access.
+	 */
+	toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
+
+	if (user_mode(regs)) {
+		debug_info->wps_disabled = 1;
+
+		/* If we're already stepping a breakpoint, just return. */
+		if (debug_info->bps_disabled)
+			return 0;
+
+		if (test_thread_flag(TIF_SINGLESTEP))
+			debug_info->suspended_step = 1;
+		else
+			user_enable_single_step(current);
+	} else {
+		toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
+		kernel_step = &__get_cpu_var(stepping_kernel_bp);
+
+		if (*kernel_step != ARM_KERNEL_STEP_NONE)
+			return 0;
+
+		if (kernel_active_single_step()) {
+			*kernel_step = ARM_KERNEL_STEP_SUSPEND;
+		} else {
+			*kernel_step = ARM_KERNEL_STEP_ACTIVE;
+			kernel_enable_single_step(regs);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Handle single-step exception.
+ */
+int reinstall_suspended_bps(struct pt_regs *regs)
+{
+	struct debug_info *debug_info = &current->thread.debug;
+	int handled_exception = 0, *kernel_step;
+
+	kernel_step = &__get_cpu_var(stepping_kernel_bp);
+
+	/*
+	 * Called from single-step exception handler.
+	 * Return 0 if execution can resume, 1 if a SIGTRAP should be
+	 * reported.
+	 */
+	if (user_mode(regs)) {
+		if (debug_info->bps_disabled) {
+			debug_info->bps_disabled = 0;
+			toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
+			handled_exception = 1;
+		}
+
+		if (debug_info->wps_disabled) {
+			debug_info->wps_disabled = 0;
+			toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
+			handled_exception = 1;
+		}
+
+		if (handled_exception) {
+			if (debug_info->suspended_step) {
+				debug_info->suspended_step = 0;
+				/* Allow exception handling to fall-through. */
+				handled_exception = 0;
+			} else {
+				user_disable_single_step(current);
+			}
+		}
+	} else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
+		toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
+		toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
+
+		if (!debug_info->wps_disabled)
+			toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
+
+		if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
+			kernel_disable_single_step();
+			handled_exception = 1;
+		} else {
+			handled_exception = 0;
+		}
+
+		*kernel_step = ARM_KERNEL_STEP_NONE;
+	}
+
+	return !handled_exception;
+}
+
+/*
+ * Context-switcher for restoring suspended breakpoints.
+ */
+void hw_breakpoint_thread_switch(struct task_struct *next)
+{
+	/*
+	 *           current        next
+	 * disabled: 0              0     => The usual case, NOTIFY_DONE
+	 *           0              1     => Disable the registers
+	 *           1              0     => Enable the registers
+	 *           1              1     => NOTIFY_DONE. per-task bps will
+	 *                                   get taken care of by perf.
+	 */
+
+	struct debug_info *current_debug_info, *next_debug_info;
+
+	current_debug_info = &current->thread.debug;
+	next_debug_info = &next->thread.debug;
+
+	/* Update breakpoints. */
+	if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
+		toggle_bp_registers(AARCH64_DBG_REG_BCR,
+				    DBG_ACTIVE_EL0,
+				    !next_debug_info->bps_disabled);
+
+	/* Update watchpoints. */
+	if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
+		toggle_bp_registers(AARCH64_DBG_REG_WCR,
+				    DBG_ACTIVE_EL0,
+				    !next_debug_info->wps_disabled);
+}
+
+/*
+ * CPU initialisation.
+ */
+static void reset_ctrl_regs(void *unused)
+{
+	int i;
+
+	for (i = 0; i < core_num_brps; ++i) {
+		write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
+		write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
+	}
+
+	for (i = 0; i < core_num_wrps; ++i) {
+		write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
+		write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
+	}
+}
+
+static int __cpuinit hw_breakpoint_reset_notify(struct notifier_block *self,
+						unsigned long action,
+						void *hcpu)
+{
+	int cpu = (long)hcpu;
+	if (action == CPU_ONLINE)
+		smp_call_function_single(cpu, reset_ctrl_regs, NULL, 1);
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata hw_breakpoint_reset_nb = {
+	.notifier_call = hw_breakpoint_reset_notify,
+};
+
+/*
+ * One-time initialisation.
+ */
+static int __init arch_hw_breakpoint_init(void)
+{
+	core_num_brps = get_num_brps();
+	core_num_wrps = get_num_wrps();
+
+	pr_info("found %d breakpoint and %d watchpoint registers.\n",
+		core_num_brps, core_num_wrps);
+
+	/*
+	 * Reset the breakpoint resources. We assume that a halting
+	 * debugger will leave the world in a nice state for us.
+	 */
+	smp_call_function(reset_ctrl_regs, NULL, 1);
+	reset_ctrl_regs(NULL);
+
+	/* Register debug fault handlers. */
+	hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
+			      TRAP_HWBKPT, "hw-breakpoint handler");
+	hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
+			      TRAP_HWBKPT, "hw-watchpoint handler");
+
+	/* Register hotplug notifier. */
+	register_cpu_notifier(&hw_breakpoint_reset_nb);
+
+	return 0;
+}
+arch_initcall(arch_hw_breakpoint_init);
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+}
+
+/*
+ * Dummy function to register with die_notifier.
+ */
+int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+				    unsigned long val, void *data)
+{
+	return NOTIFY_DONE;
+}
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
new file mode 100644
index 0000000..816b1b5
--- /dev/null
+++ b/arch/arm64/kernel/ptrace.c
@@ -0,0 +1,834 @@
+/*
+ * Based on arch/arm/kernel/ptrace.c
+ *
+ * By Ross Biro 1/23/92
+ * edited by Linus Torvalds
+ * ARM modifications Copyright (C) 2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/security.h>
+#include <linux/init.h>
+#include <linux/signal.h>
+#include <linux/uaccess.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/regset.h>
+#include <linux/tracehook.h>
+#include <linux/elf.h>
+
+#include <asm/compat.h>
+#include <asm/debug-monitors.h>
+#include <asm/pgtable.h>
+#include <asm/traps.h>
+#include <asm/system_misc.h>
+
+/*
+ * TODO: does not yet catch signals sent when the child dies.
+ * in exit.c or in signal.c.
+ */
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ */
+void ptrace_disable(struct task_struct *child)
+{
+}
+
+/*
+ * Handle hitting a breakpoint.
+ */
+static int ptrace_break(struct pt_regs *regs)
+{
+	siginfo_t info;
+
+	info.si_signo = SIGTRAP;
+	info.si_errno = 0;
+	info.si_code  = TRAP_BRKPT;
+	info.si_addr  = (void __user *)instruction_pointer(regs);
+
+	force_sig_info(SIGTRAP, &info, current);
+	return 0;
+}
+
+static int arm64_break_trap(unsigned long addr, unsigned int esr,
+			    struct pt_regs *regs)
+{
+	return ptrace_break(regs);
+}
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+/*
+ * Convert a virtual register number into an index for a thread_info
+ * breakpoint array. Breakpoints are identified using positive numbers
+ * whilst watchpoints are negative. The registers are laid out as pairs
+ * of (address, control), each pair mapping to a unique hw_breakpoint struct.
+ * Register 0 is reserved for describing resource information.
+ */
+static int ptrace_hbp_num_to_idx(long num)
+{
+	if (num < 0)
+		num = (ARM_MAX_BRP << 1) - num;
+	return (num - 1) >> 1;
+}
+
+/*
+ * Returns the virtual register number for the address of the
+ * breakpoint at index idx.
+ */
+static long ptrace_hbp_idx_to_num(int idx)
+{
+	long mid = ARM_MAX_BRP << 1;
+	long num = (idx << 1) + 1;
+	return num > mid ? mid - num : num;
+}
+
+/*
+ * Handle hitting a HW-breakpoint.
+ */
+static void ptrace_hbptriggered(struct perf_event *bp,
+				struct perf_sample_data *data,
+				struct pt_regs *regs)
+{
+	struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
+	long num;
+	int i;
+	siginfo_t info;
+
+	for (i = 0; i < ARM_MAX_HBP_SLOTS; ++i)
+		if (current->thread.debug.hbp[i] == bp)
+			break;
+
+	num = (i == ARM_MAX_HBP_SLOTS) ? 0 : ptrace_hbp_idx_to_num(i);
+
+	info.si_signo	= SIGTRAP;
+	info.si_errno	= (int)num;
+	info.si_code	= TRAP_HWBKPT;
+	info.si_addr	= (void __user *)(bkpt->trigger);
+
+	force_sig_info(SIGTRAP, &info, current);
+}
+
+/*
+ * Unregister breakpoints from this task and reset the pointers in
+ * the thread_struct.
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+	int i;
+	struct thread_struct *t = &tsk->thread;
+
+	for (i = 0; i < ARM_MAX_HBP_SLOTS; i++) {
+		if (t->debug.hbp[i]) {
+			unregister_hw_breakpoint(t->debug.hbp[i]);
+			t->debug.hbp[i] = NULL;
+		}
+	}
+}
+
+void ptrace_hw_copy_thread(struct task_struct *task)
+{
+	memset(&task->thread.debug, 0, sizeof(struct debug_info));
+}
+
+static u32 ptrace_get_hbp_resource_info(void)
+{
+	u8 num_brps, num_wrps, debug_arch, wp_len;
+	u32 reg = 0;
+
+	num_brps	= hw_breakpoint_slots(TYPE_INST);
+	num_wrps	= hw_breakpoint_slots(TYPE_DATA);
+
+	debug_arch	= debug_monitors_arch();
+	wp_len		= 8;		/* Reserved on AArch64 */
+	reg		|= debug_arch;
+	reg		<<= 8;
+	reg		|= wp_len;
+	reg		<<= 8;
+	reg		|= num_wrps;
+	reg		<<= 8;
+	reg		|= num_brps;
+
+	return reg;
+}
+
+static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
+{
+	struct perf_event_attr attr;
+
+	ptrace_breakpoint_init(&attr);
+
+	/*
+	 * Initialise fields to sane defaults
+	 * (i.e. values that will pass validation).
+	 */
+	attr.bp_addr	= 0;
+	attr.bp_len	= HW_BREAKPOINT_LEN_4;
+	attr.bp_type	= type;
+	attr.disabled	= 1;
+
+	return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
+					   tsk);
+}
+
+static int ptrace_gethbpregs(struct task_struct *tsk, long num,
+			     unsigned long  __user *data)
+{
+	u64 addr_reg;
+	u32 ctrl_reg;
+	int idx, ret = 0;
+	struct perf_event *bp;
+	struct arch_hw_breakpoint_ctrl arch_ctrl;
+
+	if (num == 0) {
+		ctrl_reg = ptrace_get_hbp_resource_info();
+		if (put_user(ctrl_reg, (u32 __user *)data))
+			ret = -EFAULT;
+	} else {
+		idx = ptrace_hbp_num_to_idx(num);
+		if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS)
+			return -EINVAL;
+
+		bp = tsk->thread.debug.hbp[idx];
+		arch_ctrl = counter_arch_bp(bp)->ctrl;
+
+		if (is_compat_task()) {
+			/*
+			 * Fix up the len because we may have adjusted
+			 * it to compensate for an unaligned address.
+			 */
+			while (!(arch_ctrl.len & 0x1))
+				arch_ctrl.len >>= 1;
+		}
+
+		if (num & 0x1) {
+			addr_reg = bp ? bp->attr.bp_addr : 0;
+			if (put_user(addr_reg, data))
+				ret = -EFAULT;
+		} else {
+			ctrl_reg = bp ? encode_ctrl_reg(arch_ctrl) : 0;
+			if (put_user(ctrl_reg, (u32 __user *)data))
+				ret = -EFAULT;
+		}
+	}
+
+	return ret;
+}
+
+static int ptrace_sethbpregs(struct task_struct *tsk, long num,
+			     unsigned long __user *data)
+{
+	int idx, gen_len, gen_type, implied_type, ret;
+	u64 user_addr;
+	u32 user_ctrl;
+	struct perf_event *bp;
+	struct arch_hw_breakpoint_ctrl ctrl;
+	struct perf_event_attr attr;
+
+	if (num == 0)
+		return 0;
+	else if (num < 0)
+		implied_type = HW_BREAKPOINT_RW;
+	else
+		implied_type = HW_BREAKPOINT_X;
+
+	idx = ptrace_hbp_num_to_idx(num);
+	if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS)
+		return -EFAULT;
+
+	bp = tsk->thread.debug.hbp[idx];
+	if (!bp) {
+		bp = ptrace_hbp_create(tsk, implied_type);
+		if (IS_ERR(bp))
+			return PTR_ERR(bp);
+		tsk->thread.debug.hbp[idx] = bp;
+	}
+
+	attr = bp->attr;
+
+	if (num & 0x1) {
+		/* Address */
+		if (get_user(user_addr, data))
+			return -EFAULT;
+		attr.bp_addr = user_addr;
+	} else {
+		/* Control */
+		if (get_user(user_ctrl, (u32 __user *)data))
+			return -EFAULT;
+		decode_ctrl_reg(user_ctrl, &ctrl);
+		ret = arch_bp_generic_fields(ctrl, &gen_len, &gen_type);
+		if (ret)
+			return ret;
+
+		if ((gen_type & implied_type) != gen_type)
+			return -EINVAL;
+
+		attr.bp_len	= gen_len;
+		attr.bp_type	= gen_type;
+		attr.disabled	= !ctrl.enabled;
+	}
+
+	return modify_user_hw_breakpoint(bp, &attr);
+}
+#endif	/* CONFIG_HAVE_HW_BREAKPOINT */
+
+static int gpr_get(struct task_struct *target,
+		   const struct user_regset *regset,
+		   unsigned int pos, unsigned int count,
+		   void *kbuf, void __user *ubuf)
+{
+	struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs;
+	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset *regset,
+		   unsigned int pos, unsigned int count,
+		   const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+	struct user_pt_regs newregs;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
+	if (ret)
+		return ret;
+
+	if (!valid_user_regs(&newregs))
+		return -EINVAL;
+
+	task_pt_regs(target)->user_regs = newregs;
+	return 0;
+}
+
+/*
+ * TODO: update fp accessors for lazy context switching (sync/flush hwstate)
+ */
+static int fpr_get(struct task_struct *target, const struct user_regset *regset,
+		   unsigned int pos, unsigned int count,
+		   void *kbuf, void __user *ubuf)
+{
+	struct user_fpsimd_state *uregs;
+	uregs = &target->thread.fpsimd_state.user_fpsimd;
+	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);
+}
+
+static int fpr_set(struct task_struct *target, const struct user_regset *regset,
+		   unsigned int pos, unsigned int count,
+		   const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+	struct user_fpsimd_state newstate;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
+	if (ret)
+		return ret;
+
+	target->thread.fpsimd_state.user_fpsimd = newstate;
+	return ret;
+}
+
+enum aarch64_regset {
+	REGSET_GPR,
+	REGSET_FPR,
+};
+
+static const struct user_regset aarch64_regsets[] = {
+	[REGSET_GPR] = {
+		.core_note_type = NT_PRSTATUS,
+		.n = sizeof(struct user_pt_regs) / sizeof(u64),
+		.size = sizeof(u64),
+		.align = sizeof(u64),
+		.get = gpr_get,
+		.set = gpr_set
+	},
+	[REGSET_FPR] = {
+		.core_note_type = NT_PRFPREG,
+		.n = sizeof(struct user_fpsimd_state) / sizeof(u32),
+		/*
+		 * We pretend we have 32-bit registers because the fpsr and
+		 * fpcr are 32-bits wide.
+		 */
+		.size = sizeof(u32),
+		.align = sizeof(u32),
+		.get = fpr_get,
+		.set = fpr_set
+	},
+};
+
+static const struct user_regset_view user_aarch64_view = {
+	.name = "aarch64", .e_machine = EM_AARCH64,
+	.regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets)
+};
+
+#ifdef CONFIG_AARCH32_EMULATION
+enum compat_regset {
+	REGSET_COMPAT_GPR,
+	REGSET_COMPAT_VFP,
+};
+
+static int compat_gpr_get(struct task_struct *target,
+			  const struct user_regset *regset,
+			  unsigned int pos, unsigned int count,
+			  void *kbuf, void __user *ubuf)
+{
+	int ret = 0;
+	unsigned int i, start, num_regs;
+
+	/* Calculate the number of AArch32 registers contained in count */
+	num_regs = count / regset->size;
+
+	/* Convert pos into an register number */
+	start = pos / regset->size;
+
+	if (start + num_regs > regset->n)
+		return -EIO;
+
+	for (i = 0; i < num_regs; ++i) {
+		unsigned int idx = start + i;
+		void *reg;
+
+		switch (idx) {
+		case 15:
+			reg = (void *)&task_pt_regs(target)->pc;
+			break;
+		case 16:
+			reg = (void *)&task_pt_regs(target)->pstate;
+			break;
+		case 17:
+			reg = (void *)&task_pt_regs(target)->orig_x0;
+			break;
+		default:
+			reg = (void *)&task_pt_regs(target)->regs[idx];
+		}
+
+		ret = copy_to_user(ubuf, reg, sizeof(compat_ulong_t));
+
+		if (ret)
+			break;
+		else
+			ubuf += sizeof(compat_ulong_t);
+	}
+
+	return ret;
+}
+
+static int compat_gpr_set(struct task_struct *target,
+			  const struct user_regset *regset,
+			  unsigned int pos, unsigned int count,
+			  const void *kbuf, const void __user *ubuf)
+{
+	struct pt_regs newregs;
+	int ret = 0;
+	unsigned int i, start, num_regs;
+
+	/* Calculate the number of AArch32 registers contained in count */
+	num_regs = count / regset->size;
+
+	/* Convert pos into an register number */
+	start = pos / regset->size;
+
+	if (start + num_regs > regset->n)
+		return -EIO;
+
+	newregs = *task_pt_regs(target);
+
+	for (i = 0; i < num_regs; ++i) {
+		unsigned int idx = start + i;
+		void *reg;
+
+		switch (idx) {
+		case 15:
+			reg = (void *)&newregs.pc;
+			break;
+		case 16:
+			reg = (void *)&newregs.pstate;
+			break;
+		case 17:
+			reg = (void *)&newregs.orig_x0;
+			break;
+		default:
+			reg = (void *)&newregs.regs[idx];
+		}
+
+		ret = copy_from_user(reg, ubuf, sizeof(compat_ulong_t));
+
+		if (ret)
+			goto out;
+		else
+			ubuf += sizeof(compat_ulong_t);
+	}
+
+	if (valid_user_regs(&newregs.user_regs))
+		*task_pt_regs(target) = newregs;
+	else
+		ret = -EINVAL;
+
+out:
+	return ret;
+}
+
+static int compat_vfp_get(struct task_struct *target,
+			  const struct user_regset *regset,
+			  unsigned int pos, unsigned int count,
+			  void *kbuf, void __user *ubuf)
+{
+	struct user_fpsimd_state *uregs;
+	compat_ulong_t fpscr;
+	int ret;
+
+	uregs = &target->thread.fpsimd_state.user_fpsimd;
+
+	/*
+	 * The VFP registers are packed into the fpsimd_state, so they all sit
+	 * nicely together for us. We just need to create the fpscr separately.
+	 */
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
+				  VFP_STATE_SIZE - sizeof(compat_ulong_t));
+
+	if (count && !ret) {
+		fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) |
+			(uregs->fpcr & VFP_FPSCR_CTRL_MASK);
+		ret = put_user(fpscr, (compat_ulong_t *)ubuf);
+	}
+
+	return ret;
+}
+
+static int compat_vfp_set(struct task_struct *target,
+			  const struct user_regset *regset,
+			  unsigned int pos, unsigned int count,
+			  const void *kbuf, const void __user *ubuf)
+{
+	struct user_fpsimd_state *uregs;
+	compat_ulong_t fpscr;
+	int ret;
+
+	if (pos + count > VFP_STATE_SIZE)
+		return -EIO;
+
+	uregs = &target->thread.fpsimd_state.user_fpsimd;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
+				 VFP_STATE_SIZE - sizeof(compat_ulong_t));
+
+	if (count && !ret) {
+		ret = get_user(fpscr, (compat_ulong_t *)ubuf);
+		uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK;
+		uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK;
+	}
+
+	return ret;
+}
+
+static const struct user_regset aarch32_regsets[] = {
+	[REGSET_COMPAT_GPR] = {
+		.core_note_type = NT_PRSTATUS,
+		.n = COMPAT_ELF_NGREG,
+		.size = sizeof(compat_elf_greg_t),
+		.align = sizeof(compat_elf_greg_t),
+		.get = compat_gpr_get,
+		.set = compat_gpr_set
+	},
+	[REGSET_COMPAT_VFP] = {
+		.core_note_type = NT_ARM_VFP,
+		.n = VFP_STATE_SIZE / sizeof(compat_ulong_t),
+		.size = sizeof(compat_ulong_t),
+		.align = sizeof(compat_ulong_t),
+		.get = compat_vfp_get,
+		.set = compat_vfp_set
+	},
+};
+
+static const struct user_regset_view user_aarch32_view = {
+	.name = "aarch32", .e_machine = EM_ARM,
+	.regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets)
+};
+#endif /* CONFIG_AARCH32_EMULATION */
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+#ifdef CONFIG_AARCH32_EMULATION
+	if (test_tsk_thread_flag(task, TIF_32BIT))
+		return &user_aarch32_view;
+#endif
+	return &user_aarch64_view;
+}
+
+long arch_ptrace(struct task_struct *child, long request,
+		 unsigned long addr, unsigned long data)
+{
+	int ret;
+	unsigned long *datap = (unsigned long __user *)data;
+
+	switch (request) {
+		case PTRACE_GET_THREAD_AREA:
+			ret = put_user(child->thread.tp_value, datap);
+			break;
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+		case PTRACE_GETHBPREGS:
+			ret = ptrace_gethbpregs(child, addr, datap);
+			break;
+
+		case PTRACE_SETHBPREGS:
+			ret = ptrace_sethbpregs(child, addr, datap);
+			break;
+#endif
+
+		default:
+			ret = ptrace_request(child, request, addr, data);
+			break;
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_AARCH32_EMULATION
+
+#include <linux/compat.h>
+
+int aarch32_break_trap(struct pt_regs *regs)
+{
+	unsigned int instr;
+	bool bp = false;
+	void __user *pc = (void __user *)instruction_pointer(regs);
+
+	if (compat_thumb_mode(regs)) {
+		/* get 16-bit Thumb instruction */
+		get_user(instr, (u16 __user *)pc);
+		if (instr == AARCH32_BREAK_THUMB2_LO) {
+			/* get second half of 32-bit Thumb-2 instruction */
+			get_user(instr, (u16 __user *)(pc + 2));
+			bp = instr == AARCH32_BREAK_THUMB2_HI;
+		} else {
+			bp = instr == AARCH32_BREAK_THUMB;
+		}
+	} else {
+		/* 32-bit ARM instruction */
+		get_user(instr, (u32 __user *)pc);
+		bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM;
+	}
+
+	if (bp)
+		return ptrace_break(regs);
+	return 1;
+}
+
+static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off,
+				   compat_ulong_t __user *ret)
+{
+	compat_ulong_t tmp;
+
+	if (off & 3)
+		return -EIO;
+
+	if (off == PT_TEXT_ADDR)
+		tmp = tsk->mm->start_code;
+	else if (off == PT_DATA_ADDR)
+		tmp = tsk->mm->start_data;
+	else if (off == PT_TEXT_END_ADDR)
+		tmp = tsk->mm->end_code;
+	else if (off < sizeof(compat_elf_gregset_t))
+		return copy_regset_to_user(tsk, &user_aarch32_view,
+					   REGSET_COMPAT_GPR, off,
+					   sizeof(compat_ulong_t), ret);
+	else if (off >= COMPAT_USER_SZ)
+		return -EIO;
+	else
+		tmp = 0;
+
+	return put_user(tmp, ret);
+}
+
+static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off,
+				    compat_ulong_t val)
+{
+	int ret;
+
+	if (off & 3 || off >= COMPAT_USER_SZ)
+		return -EIO;
+
+	if (off >= sizeof(compat_elf_gregset_t))
+		return 0;
+
+	ret = copy_regset_from_user(tsk, &user_aarch32_view,
+				    REGSET_COMPAT_GPR, off,
+				    sizeof(compat_ulong_t),
+				    &val);
+	return ret;
+}
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num,
+				    compat_ulong_t __user *data)
+{
+	int ret;
+	unsigned long kdata;
+
+	mm_segment_t old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	ret = ptrace_gethbpregs(tsk, (long)num, &kdata);
+	set_fs(old_fs);
+
+	if (!ret)
+		ret = put_user(kdata, data);
+
+	return ret;
+}
+
+static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num,
+				    compat_ulong_t __user *data)
+{
+	int ret;
+	unsigned long kdata = 0;
+	mm_segment_t old_fs = get_fs();
+
+	ret = get_user(kdata, data);
+
+	if (!ret) {
+		set_fs(KERNEL_DS);
+		ret = ptrace_sethbpregs(tsk, (long)num, &kdata);
+		set_fs(old_fs);
+	}
+
+	return ret;
+}
+#endif	/* CONFIG_HAVE_HW_BREAKPOINT */
+
+long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+			compat_ulong_t caddr, compat_ulong_t cdata)
+{
+	unsigned long addr = caddr;
+	unsigned long data = cdata;
+	void __user *datap = compat_ptr(data);
+	int ret;
+
+	switch (request) {
+		case PTRACE_PEEKUSR:
+			ret = compat_ptrace_read_user(child, addr, datap);
+			break;
+
+		case PTRACE_POKEUSR:
+			ret = compat_ptrace_write_user(child, addr, data);
+			break;
+
+		case PTRACE_GETREGS:
+			ret = copy_regset_to_user(child,
+						  &user_aarch32_view,
+						  REGSET_COMPAT_GPR,
+						  0, sizeof(compat_elf_gregset_t),
+						  datap);
+			break;
+
+		case PTRACE_SETREGS:
+			ret = copy_regset_from_user(child,
+						    &user_aarch32_view,
+						    REGSET_COMPAT_GPR,
+						    0, sizeof(compat_elf_gregset_t),
+						    datap);
+			break;
+
+		case PTRACE_GET_THREAD_AREA:
+			ret = put_user((compat_ulong_t)child->thread.tp_value,
+				       (compat_ulong_t __user *)datap);
+			break;
+
+		case PTRACE_SET_SYSCALL:
+			task_pt_regs(child)->syscallno = data;
+			ret = 0;
+			break;
+
+		case COMPAT_PTRACE_GETVFPREGS:
+			ret = copy_regset_to_user(child,
+						  &user_aarch32_view,
+						  REGSET_COMPAT_VFP,
+						  0, VFP_STATE_SIZE,
+						  datap);
+			break;
+
+		case COMPAT_PTRACE_SETVFPREGS:
+			ret = copy_regset_from_user(child,
+						    &user_aarch32_view,
+						    REGSET_COMPAT_VFP,
+						    0, VFP_STATE_SIZE,
+						    datap);
+			break;
+
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+		case PTRACE_GETHBPREGS:
+			ret = compat_ptrace_gethbpregs(child, addr, datap);
+			break;
+
+		case PTRACE_SETHBPREGS:
+			ret = compat_ptrace_sethbpregs(child, addr, datap);
+			break;
+#endif
+
+		default:
+			ret = compat_ptrace_request(child, request, addr,
+						    data);
+			break;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_AARCH32_EMULATION */
+
+static int __init ptrace_break_init(void)
+{
+	hook_debug_fault_code(DBG_ESR_EVT_BRK, arm64_break_trap, SIGTRAP,
+			      TRAP_BRKPT, "ptrace BRK handler");
+	return 0;
+}
+core_initcall(ptrace_break_init);
+
+
+asmlinkage int syscall_trace(int dir, struct pt_regs *regs)
+{
+	unsigned long saved_reg;
+
+	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+		return regs->syscallno;
+
+	if (test_thread_flag(TIF_32BIT)) {
+		/* AArch32 uses ip (r12) for scratch */
+		saved_reg = regs->regs[12];
+		regs->regs[12] = dir;
+	} else {
+		/*
+		 * Save X7. X7 is used to denote syscall entry/exit:
+		 *   X7 = 0 -> entry, = 1 -> exit
+		 */
+		saved_reg = regs->regs[7];
+		regs->regs[7] = dir;
+	}
+
+	if (dir)
+		tracehook_report_syscall_exit(regs, 0);
+	else if (tracehook_report_syscall_entry(regs))
+		regs->syscallno = ~0UL;
+
+	if (test_thread_flag(TIF_32BIT))
+		regs->regs[12] = saved_reg;
+	else
+		regs->regs[7] = saved_reg;
+
+	return regs->syscallno;
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:22 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:22 +0100
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds support for 32-bit applications. The vectors page is a
binary blob mapped into the application user space at 0xffff0000 (the
AArch64 toolchain does not support compilation of AArch32 code). Full
compatibility with ARMv7 user space is supported. The use of deprecated
ARMv7 functionality (SWP, CP15 barriers) has been disabled by default on
AArch64 kernels and unaligned LDM/STM is not supported.

Please note that only the ARM 32-bit EABI is supported, so no OABI
compatibility.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/compat.h   |  232 ++++++++++
 arch/arm64/include/asm/signal32.h |   54 +++
 arch/arm64/include/asm/unistd32.h |  758 ++++++++++++++++++++++++++++++++
 arch/arm64/kernel/kuser32.S       |   77 ++++
 arch/arm64/kernel/signal32.c      |  876 +++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/sys32.S         |  283 ++++++++++++
 arch/arm64/kernel/sys_compat.c    |  177 ++++++++
 7 files changed, 2457 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/compat.h
 create mode 100644 arch/arm64/include/asm/signal32.h
 create mode 100644 arch/arm64/include/asm/unistd32.h
 create mode 100644 arch/arm64/kernel/kuser32.S
 create mode 100644 arch/arm64/kernel/signal32.c
 create mode 100644 arch/arm64/kernel/sys32.S
 create mode 100644 arch/arm64/kernel/sys_compat.c

diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
new file mode 100644
index 0000000..91e72b7
--- /dev/null
+++ b/arch/arm64/include/asm/compat.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_COMPAT_H
+#define __ASM_COMPAT_H
+#ifdef __KERNEL__
+#ifdef CONFIG_COMPAT
+
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+#include <linux/sched.h>
+
+#define COMPAT_USER_HZ		100
+#define COMPAT_UTS_MACHINE	"armv8l\0\0"
+
+typedef u32		compat_size_t;
+typedef s32		compat_ssize_t;
+typedef s32		compat_time_t;
+typedef s32		compat_clock_t;
+typedef s32		compat_pid_t;
+typedef u32		__compat_uid_t;
+typedef u32		__compat_gid_t;
+typedef u32		__compat_uid32_t;
+typedef u32		__compat_gid32_t;
+typedef u32		compat_mode_t;
+typedef u32		compat_ino_t;
+typedef u32		compat_dev_t;
+typedef s32		compat_off_t;
+typedef s64		compat_loff_t;
+typedef s16		compat_nlink_t;
+typedef u16		compat_ipc_pid_t;
+typedef s32		compat_daddr_t;
+typedef u32		compat_caddr_t;
+typedef __kernel_fsid_t	compat_fsid_t;
+typedef s32		compat_key_t;
+typedef s32		compat_timer_t;
+
+typedef s32		compat_int_t;
+typedef s32		compat_long_t;
+typedef s64		compat_s64;
+typedef u32		compat_uint_t;
+typedef u32		compat_ulong_t;
+typedef u64		compat_u64;
+
+struct compat_timespec {
+	compat_time_t	tv_sec;
+	s32		tv_nsec;
+};
+
+struct compat_timeval {
+	compat_time_t	tv_sec;
+	s32		tv_usec;
+};
+
+struct compat_stat {
+	compat_dev_t	st_dev;
+	compat_ino_t	st_ino;
+	compat_mode_t	st_mode;
+	compat_nlink_t	st_nlink;
+	__compat_uid32_t	st_uid;
+	__compat_gid32_t	st_gid;
+	compat_dev_t	st_rdev;
+	compat_off_t	st_size;
+	compat_off_t	st_blksize;
+	compat_off_t	st_blocks;
+	compat_time_t	st_atime;
+	u32		st_atime_nsec;
+	compat_time_t	st_mtime;
+	u32		st_mtime_nsec;
+	compat_time_t	st_ctime;
+	u32		st_ctime_nsec;
+	u32		__unused4[2];
+};
+
+struct compat_flock {
+	short		l_type;
+	short		l_whence;
+	compat_off_t	l_start;
+	compat_off_t	l_len;
+	compat_pid_t	l_pid;
+};
+
+#define F_GETLK64	12	/*  using 'struct flock64' */
+#define F_SETLK64	13
+#define F_SETLKW64	14
+
+struct compat_flock64 {
+	short		l_type;
+	short		l_whence;
+	compat_loff_t	l_start;
+	compat_loff_t	l_len;
+	compat_pid_t	l_pid;
+};
+
+struct compat_statfs {
+	int		f_type;
+	int		f_bsize;
+	int		f_blocks;
+	int		f_bfree;
+	int		f_bavail;
+	int		f_files;
+	int		f_ffree;
+	compat_fsid_t	f_fsid;
+	int		f_namelen;	/* SunOS ignores this field. */
+	int		f_frsize;
+	int		f_flags;
+	int		f_spare[4];
+};
+
+#define COMPAT_RLIM_INFINITY		0xffffffff
+
+typedef u32		compat_old_sigset_t;
+
+#define _COMPAT_NSIG		64
+#define _COMPAT_NSIG_BPW	32
+
+typedef u32		compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX	0x7fffffff
+#define COMPAT_LOFF_T_MAX	0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef	u32		compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+	return (void __user *)(unsigned long)uptr;
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+	return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *arch_compat_alloc_user_space(long len)
+{
+	struct pt_regs *regs = task_pt_regs(current);
+	return (void __user *)regs->compat_sp - len;
+}
+
+struct compat_ipc64_perm {
+	compat_key_t key;
+	__compat_uid32_t uid;
+	__compat_gid32_t gid;
+	__compat_uid32_t cuid;
+	__compat_gid32_t cgid;
+	unsigned short mode;
+	unsigned short __pad1;
+	unsigned short seq;
+	unsigned short __pad2;
+	compat_ulong_t unused1;
+	compat_ulong_t unused2;
+};
+
+struct compat_semid64_ds {
+	struct compat_ipc64_perm sem_perm;
+	compat_time_t  sem_otime;
+	compat_ulong_t __unused1;
+	compat_time_t  sem_ctime;
+	compat_ulong_t __unused2;
+	compat_ulong_t sem_nsems;
+	compat_ulong_t __unused3;
+	compat_ulong_t __unused4;
+};
+
+struct compat_msqid64_ds {
+	struct compat_ipc64_perm msg_perm;
+	compat_time_t  msg_stime;
+	compat_ulong_t __unused1;
+	compat_time_t  msg_rtime;
+	compat_ulong_t __unused2;
+	compat_time_t  msg_ctime;
+	compat_ulong_t __unused3;
+	compat_ulong_t msg_cbytes;
+	compat_ulong_t msg_qnum;
+	compat_ulong_t msg_qbytes;
+	compat_pid_t   msg_lspid;
+	compat_pid_t   msg_lrpid;
+	compat_ulong_t __unused4;
+	compat_ulong_t __unused5;
+};
+
+struct compat_shmid64_ds {
+	struct compat_ipc64_perm shm_perm;
+	compat_size_t  shm_segsz;
+	compat_time_t  shm_atime;
+	compat_ulong_t __unused1;
+	compat_time_t  shm_dtime;
+	compat_ulong_t __unused2;
+	compat_time_t  shm_ctime;
+	compat_ulong_t __unused3;
+	compat_pid_t   shm_cpid;
+	compat_pid_t   shm_lpid;
+	compat_ulong_t shm_nattch;
+	compat_ulong_t __unused4;
+	compat_ulong_t __unused5;
+};
+
+static inline int is_compat_task(void)
+{
+	return test_thread_flag(TIF_32BIT);
+}
+
+#else /* !CONFIG_COMPAT */
+
+static inline int is_compat_task(void)
+{
+	return 0;
+}
+
+#endif /* CONFIG_COMPAT */
+#endif /* __KERNEL__ */
+#endif /* __ASM_COMPAT_H */
diff --git a/arch/arm64/include/asm/signal32.h b/arch/arm64/include/asm/signal32.h
new file mode 100644
index 0000000..f9cf9e1
--- /dev/null
+++ b/arch/arm64/include/asm/signal32.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SIGNAL32_H
+#define __ASM_SIGNAL32_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_AARCH32_EMULATION
+#include <linux/compat.h>
+
+#define AARCH32_KERN_SIGRET_CODE_OFFSET	0x500
+
+extern const compat_ulong_t aarch32_sigret_code[6];
+
+int compat_setup_frame(int usig, struct k_sigaction *ka, sigset_t *set,
+		       struct pt_regs *regs);
+int compat_setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
+			  sigset_t *set, struct pt_regs *regs);
+
+void compat_setup_restart_syscall(struct pt_regs *regs);
+#else
+
+static inline int compat_setup_frame(int usid, struct k_sigaction *ka,
+				     sigset_t *set, struct pt_regs *regs)
+{
+	BUG();
+}
+
+static inline int compat_setup_rt_frame(int usig, struct k_sigaction *ka,
+					siginfo_t *info, sigset_t *set,
+					struct pt_regs *regs)
+{
+	BUG();
+}
+
+static inline void compat_setup_restart_syscall(struct pt_regs *regs)
+{
+	BUG();
+}
+#endif /* CONFIG_AARCH32_EMULATION */
+#endif /* __KERNEL__ */
+#endif /* __ASM_SIGNAL32_H */
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
new file mode 100644
index 0000000..a50405f
--- /dev/null
+++ b/arch/arm64/include/asm/unistd32.h
@@ -0,0 +1,758 @@
+/*
+ * Based on arch/arm/include/asm/unistd.h
+ *
+ * Copyright (C) 2001-2005 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#if !defined(__ASM_UNISTD32_H) || defined(__SYSCALL)
+#define __ASM_UNISTD32_H
+
+#ifndef __SYSCALL
+#define __SYSCALL(x, y)
+#endif
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#ifdef __SYSCALL_COMPAT
+
+#define __NR_restart_syscall		0
+__SYSCALL(__NR_restart_syscall, sys_restart_syscall)
+#define __NR_exit			1
+__SYSCALL(__NR_exit, sys_exit)
+#define __NR_fork			2
+__SYSCALL(__NR_fork, sys_fork)
+#define __NR_read			3
+__SYSCALL(__NR_read, sys_read)
+#define __NR_write			4
+__SYSCALL(__NR_write, sys_write)
+#define __NR_open			5
+__SYSCALL(__NR_open, sys_open)
+#define __NR_close			6
+__SYSCALL(__NR_close, sys_close)
+__SYSCALL(7, sys_ni_syscall)		/* 7 was sys_waitpid */
+#define __NR_creat			8
+__SYSCALL(__NR_creat, sys_creat)
+#define __NR_link			9
+__SYSCALL(__NR_link, sys_link)
+#define __NR_unlink			10
+__SYSCALL(__NR_unlink, sys_unlink)
+#define __NR_execve			11
+__SYSCALL(__NR_execve, sys_execve)
+#define __NR_chdir			12
+__SYSCALL(__NR_chdir, sys_chdir)
+__SYSCALL(13, sys_ni_syscall)		/* 13 was sys_time */
+#define __NR_mknod			14
+__SYSCALL(__NR_mknod, sys_mknod)
+#define __NR_chmod			15
+__SYSCALL(__NR_chmod, sys_chmod)
+#define __NR_lchown			16
+__SYSCALL(__NR_lchown, sys_lchown16)
+__SYSCALL(17, sys_ni_syscall)		/* 17 was sys_break */
+__SYSCALL(18, sys_ni_syscall)		/* 18 was sys_stat */
+#define __NR_lseek			19
+__SYSCALL(__NR_lseek, sys_lseek)
+#define __NR_getpid			20
+__SYSCALL(__NR_getpid, sys_getpid)
+#define __NR_mount			21
+__SYSCALL(__NR_mount, sys_mount)
+__SYSCALL(22, sys_ni_syscall)		/* 22 was sys_umount */
+#define __NR_setuid			23
+__SYSCALL(__NR_setuid, sys_setuid16)
+#define __NR_getuid			24
+__SYSCALL(__NR_getuid, sys_getuid16)
+__SYSCALL(25, sys_ni_syscall)		/* 25 was sys_stime */
+#define __NR_ptrace			26
+__SYSCALL(__NR_ptrace, sys_ptrace)
+__SYSCALL(27, sys_ni_syscall)		/* 27 was sys_alarm */
+__SYSCALL(28, sys_ni_syscall)		/* 28 was sys_fstat */
+#define __NR_pause			29
+__SYSCALL(__NR_pause, sys_pause)
+__SYSCALL(30, sys_ni_syscall)		/* 30 was sys_utime */
+__SYSCALL(31, sys_ni_syscall)		/* 31 was sys_stty */
+__SYSCALL(32, sys_ni_syscall)		/* 32 was sys_gtty */
+#define __NR_access			33
+__SYSCALL(__NR_access, sys_access)
+#define __NR_nice			34
+__SYSCALL(__NR_nice, sys_nice)
+__SYSCALL(35, sys_ni_syscall)		/* 35 was sys_ftime */
+#define __NR_sync			36
+__SYSCALL(__NR_sync, sys_sync)
+#define __NR_kill			37
+__SYSCALL(__NR_kill, sys_kill)
+#define __NR_rename			38
+__SYSCALL(__NR_rename, sys_rename)
+#define __NR_mkdir			39
+__SYSCALL(__NR_mkdir, sys_mkdir)
+#define __NR_rmdir			40
+__SYSCALL(__NR_rmdir, sys_rmdir)
+#define __NR_dup			41
+__SYSCALL(__NR_dup, sys_dup)
+#define __NR_pipe			42
+__SYSCALL(__NR_pipe, sys_pipe)
+#define __NR_times			43
+__SYSCALL(__NR_times, sys_times)
+__SYSCALL(44, sys_ni_syscall)		/* 44 was sys_prof */
+#define __NR_brk			45
+__SYSCALL(__NR_brk, sys_brk)
+#define __NR_setgid			46
+__SYSCALL(__NR_setgid, sys_setgid16)
+#define __NR_getgid			47
+__SYSCALL(__NR_getgid, sys_getgid16)
+__SYSCALL(48, sys_ni_syscall)		/* 48 was sys_signal */
+#define __NR_geteuid			49
+__SYSCALL(__NR_geteuid, sys_geteuid16)
+#define __NR_getegid			50
+__SYSCALL(__NR_getegid, sys_getegid16)
+#define __NR_acct			51
+__SYSCALL(__NR_acct, sys_acct)
+#define __NR_umount2			52
+__SYSCALL(__NR_umount2, sys_umount)
+__SYSCALL(53, sys_ni_syscall)		/* 53 was sys_lock */
+#define __NR_ioctl			54
+__SYSCALL(__NR_ioctl, sys_ioctl)
+#define __NR_fcntl			55
+__SYSCALL(__NR_fcntl, sys_fcntl)
+__SYSCALL(56, sys_ni_syscall)		/* 56 was sys_mpx */
+#define __NR_setpgid			57
+__SYSCALL(__NR_setpgid, sys_setpgid)
+__SYSCALL(58, sys_ni_syscall)		/* 58 was sys_ulimit */
+__SYSCALL(59, sys_ni_syscall)		/* 59 was sys_olduname */
+#define __NR_umask			60
+__SYSCALL(__NR_umask, sys_umask)
+#define __NR_chroot			61
+__SYSCALL(__NR_chroot, sys_chroot)
+#define __NR_ustat			62
+__SYSCALL(__NR_ustat, sys_ustat)
+#define __NR_dup2			63
+__SYSCALL(__NR_dup2, sys_dup2)
+#define __NR_getppid			64
+__SYSCALL(__NR_getppid, sys_getppid)
+#define __NR_getpgrp			65
+__SYSCALL(__NR_getpgrp, sys_getpgrp)
+#define __NR_setsid			66
+__SYSCALL(__NR_setsid, sys_setsid)
+#define __NR_sigaction			67
+__SYSCALL(__NR_sigaction, sys_sigaction)
+__SYSCALL(68, sys_ni_syscall)		/* 68 was sys_sgetmask */
+__SYSCALL(69, sys_ni_syscall)		/* 69 was sys_ssetmask */
+#define __NR_setreuid			70
+__SYSCALL(__NR_setreuid, sys_setreuid16)
+#define __NR_setregid			71
+__SYSCALL(__NR_setregid, sys_setregid16)
+#define __NR_sigsuspend			72
+__SYSCALL(__NR_sigsuspend, sys_sigsuspend)
+#define __NR_sigpending			73
+__SYSCALL(__NR_sigpending, sys_sigpending)
+#define __NR_sethostname		74
+__SYSCALL(__NR_sethostname, sys_sethostname)
+#define __NR_setrlimit			75
+__SYSCALL(__NR_setrlimit, sys_setrlimit)
+__SYSCALL(76, sys_ni_syscall)		/* 76 was sys_getrlimit */
+#define __NR_getrusage			77
+__SYSCALL(__NR_getrusage, sys_getrusage)
+#define __NR_gettimeofday		78
+__SYSCALL(__NR_gettimeofday, sys_gettimeofday)
+#define __NR_settimeofday		79
+__SYSCALL(__NR_settimeofday, sys_settimeofday)
+#define __NR_getgroups			80
+__SYSCALL(__NR_getgroups, sys_getgroups16)
+#define __NR_setgroups			81
+__SYSCALL(__NR_setgroups, sys_setgroups16)
+__SYSCALL(82, sys_ni_syscall)		/* 82 was sys_select */
+#define __NR_symlink			83
+__SYSCALL(__NR_symlink, sys_symlink)
+__SYSCALL(84, sys_ni_syscall)		/* 84 was sys_lstat */
+#define __NR_readlink			85
+__SYSCALL(__NR_readlink, sys_readlink)
+#define __NR_uselib			86
+__SYSCALL(__NR_uselib, sys_uselib)
+#define __NR_swapon			87
+__SYSCALL(__NR_swapon, sys_swapon)
+#define __NR_reboot			88
+__SYSCALL(__NR_reboot, sys_reboot)
+__SYSCALL(89, sys_ni_syscall)		/* 89 was sys_readdir */
+__SYSCALL(90, sys_ni_syscall)		/* 90 was sys_mmap */
+#define __NR_munmap			91
+__SYSCALL(__NR_munmap, sys_munmap)
+#define __NR_truncate			92
+__SYSCALL(__NR_truncate, sys_truncate)
+#define __NR_ftruncate			93
+__SYSCALL(__NR_ftruncate, sys_ftruncate)
+#define __NR_fchmod			94
+__SYSCALL(__NR_fchmod, sys_fchmod)
+#define __NR_fchown			95
+__SYSCALL(__NR_fchown, sys_fchown16)
+#define __NR_getpriority		96
+__SYSCALL(__NR_getpriority, sys_getpriority)
+#define __NR_setpriority		97
+__SYSCALL(__NR_setpriority, sys_setpriority)
+__SYSCALL(98, sys_ni_syscall)		/* 98 was sys_profil */
+#define __NR_statfs			99
+__SYSCALL(__NR_statfs, sys_statfs)
+#define __NR_fstatfs			100
+__SYSCALL(__NR_fstatfs, sys_fstatfs)
+__SYSCALL(101, sys_ni_syscall)		/* 101 was sys_ioperm */
+__SYSCALL(102, sys_ni_syscall)		/* 102 was sys_socketcall */
+#define __NR_syslog			103
+__SYSCALL(__NR_syslog, sys_syslog)
+#define __NR_setitimer			104
+__SYSCALL(__NR_setitimer, sys_setitimer)
+#define __NR_getitimer			105
+__SYSCALL(__NR_getitimer, sys_getitimer)
+#define __NR_stat			106
+__SYSCALL(__NR_stat, sys_newstat)
+#define __NR_lstat			107
+__SYSCALL(__NR_lstat, sys_newlstat)
+#define __NR_fstat			108
+__SYSCALL(__NR_fstat, sys_newfstat)
+__SYSCALL(109, sys_ni_syscall)		/* 109 was sys_uname */
+__SYSCALL(110, sys_ni_syscall)		/* 110 was sys_iopl */
+#define __NR_vhangup			111
+__SYSCALL(__NR_vhangup, sys_vhangup)
+__SYSCALL(112, sys_ni_syscall)		/* 112 was sys_idle */
+__SYSCALL(113, sys_ni_syscall)		/* 113 was sys_syscall */
+#define __NR_wait4			114
+__SYSCALL(__NR_wait4, sys_wait4)
+#define __NR_swapoff			115
+__SYSCALL(__NR_swapoff, sys_swapoff)
+#define __NR_sysinfo			116
+__SYSCALL(__NR_sysinfo, sys_sysinfo)
+__SYSCALL(117, sys_ni_syscall)		/* 117 was sys_ipc */
+#define __NR_fsync			118
+__SYSCALL(__NR_fsync, sys_fsync)
+#define __NR_sigreturn			119
+__SYSCALL(__NR_sigreturn, sys_sigreturn)
+#define __NR_clone			120
+__SYSCALL(__NR_clone, sys_clone)
+#define __NR_setdomainname		121
+__SYSCALL(__NR_setdomainname, sys_setdomainname)
+#define __NR_uname			122
+__SYSCALL(__NR_uname, sys_newuname)
+__SYSCALL(123, sys_ni_syscall)		/* 123 was sys_modify_ldt */
+#define __NR_adjtimex			124
+__SYSCALL(__NR_adjtimex, sys_adjtimex)
+#define __NR_mprotect			125
+__SYSCALL(__NR_mprotect, sys_mprotect)
+#define __NR_sigprocmask		126
+__SYSCALL(__NR_sigprocmask, sys_sigprocmask)
+__SYSCALL(127, sys_ni_syscall)		/* 127 was sys_create_module */
+#define __NR_init_module		128
+__SYSCALL(__NR_init_module, sys_init_module)
+#define __NR_delete_module		129
+__SYSCALL(__NR_delete_module, sys_delete_module)
+__SYSCALL(130, sys_ni_syscall)		/* 130 was sys_get_kernel_syms */
+#define __NR_quotactl			131
+__SYSCALL(__NR_quotactl, sys_quotactl)
+#define __NR_getpgid			132
+__SYSCALL(__NR_getpgid, sys_getpgid)
+#define __NR_fchdir			133
+__SYSCALL(__NR_fchdir, sys_fchdir)
+#define __NR_bdflush			134
+__SYSCALL(__NR_bdflush, sys_bdflush)
+#define __NR_sysfs			135
+__SYSCALL(__NR_sysfs, sys_sysfs)
+#define __NR_personality		136
+__SYSCALL(__NR_personality, sys_personality)
+__SYSCALL(137, sys_ni_syscall)		/* 137 was sys_afs_syscall */
+#define __NR_setfsuid			138
+__SYSCALL(__NR_setfsuid, sys_setfsuid16)
+#define __NR_setfsgid			139
+__SYSCALL(__NR_setfsgid, sys_setfsgid16)
+#define __NR__llseek			140
+__SYSCALL(__NR__llseek, sys_llseek)
+#define __NR_getdents			141
+__SYSCALL(__NR_getdents, sys_getdents)
+#define __NR__newselect			142
+__SYSCALL(__NR__newselect, sys_select)
+#define __NR_flock			143
+__SYSCALL(__NR_flock, sys_flock)
+#define __NR_msync			144
+__SYSCALL(__NR_msync, sys_msync)
+#define __NR_readv			145
+__SYSCALL(__NR_readv, sys_readv)
+#define __NR_writev			146
+__SYSCALL(__NR_writev, sys_writev)
+#define __NR_getsid			147
+__SYSCALL(__NR_getsid, sys_getsid)
+#define __NR_fdatasync			148
+__SYSCALL(__NR_fdatasync, sys_fdatasync)
+#define __NR__sysctl			149
+__SYSCALL(__NR__sysctl, sys_sysctl)
+#define __NR_mlock			150
+__SYSCALL(__NR_mlock, sys_mlock)
+#define __NR_munlock			151
+__SYSCALL(__NR_munlock, sys_munlock)
+#define __NR_mlockall			152
+__SYSCALL(__NR_mlockall, sys_mlockall)
+#define __NR_munlockall			153
+__SYSCALL(__NR_munlockall, sys_munlockall)
+#define __NR_sched_setparam		154
+__SYSCALL(__NR_sched_setparam, sys_sched_setparam)
+#define __NR_sched_getparam		155
+__SYSCALL(__NR_sched_getparam, sys_sched_getparam)
+#define __NR_sched_setscheduler		156
+__SYSCALL(__NR_sched_setscheduler, sys_sched_setscheduler)
+#define __NR_sched_getscheduler		157
+__SYSCALL(__NR_sched_getscheduler, sys_sched_getscheduler)
+#define __NR_sched_yield		158
+__SYSCALL(__NR_sched_yield, sys_sched_yield)
+#define __NR_sched_get_priority_max	159
+__SYSCALL(__NR_sched_get_priority_max, sys_sched_get_priority_max)
+#define __NR_sched_get_priority_min	160
+__SYSCALL(__NR_sched_get_priority_min, sys_sched_get_priority_min)
+#define __NR_sched_rr_get_interval	161
+__SYSCALL(__NR_sched_rr_get_interval, sys_sched_rr_get_interval)
+#define __NR_nanosleep			162
+__SYSCALL(__NR_nanosleep, sys_nanosleep)
+#define __NR_mremap			163
+__SYSCALL(__NR_mremap, sys_mremap)
+#define __NR_setresuid			164
+__SYSCALL(__NR_setresuid, sys_setresuid16)
+#define __NR_getresuid			165
+__SYSCALL(__NR_getresuid, sys_getresuid16)
+__SYSCALL(166, sys_ni_syscall)		/* 166 was sys_vm86 */
+__SYSCALL(167, sys_ni_syscall)		/* 167 was sys_query_module */
+#define __NR_poll			168
+__SYSCALL(__NR_poll, sys_poll)
+#define __NR_nfsservctl			169
+__SYSCALL(__NR_nfsservctl, sys_ni_syscall)
+#define __NR_setresgid			170
+__SYSCALL(__NR_setresgid, sys_setresgid16)
+#define __NR_getresgid			171
+__SYSCALL(__NR_getresgid, sys_getresgid16)
+#define __NR_prctl			172
+__SYSCALL(__NR_prctl, sys_prctl)
+#define __NR_rt_sigreturn		173
+__SYSCALL(__NR_rt_sigreturn, sys_rt_sigreturn)
+#define __NR_rt_sigaction		174
+__SYSCALL(__NR_rt_sigaction, sys_rt_sigaction)
+#define __NR_rt_sigprocmask		175
+__SYSCALL(__NR_rt_sigprocmask, sys_rt_sigprocmask)
+#define __NR_rt_sigpending		176
+__SYSCALL(__NR_rt_sigpending, sys_rt_sigpending)
+#define __NR_rt_sigtimedwait		177
+__SYSCALL(__NR_rt_sigtimedwait, sys_rt_sigtimedwait)
+#define __NR_rt_sigqueueinfo		178
+__SYSCALL(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo)
+#define __NR_rt_sigsuspend		179
+__SYSCALL(__NR_rt_sigsuspend, sys_rt_sigsuspend)
+#define __NR_pread64			180
+__SYSCALL(__NR_pread64, sys_pread64)
+#define __NR_pwrite64			181
+__SYSCALL(__NR_pwrite64, sys_pwrite64)
+#define __NR_chown			182
+__SYSCALL(__NR_chown, sys_chown16)
+#define __NR_getcwd			183
+__SYSCALL(__NR_getcwd, sys_getcwd)
+#define __NR_capget			184
+__SYSCALL(__NR_capget, sys_capget)
+#define __NR_capset			185
+__SYSCALL(__NR_capset, sys_capset)
+#define __NR_sigaltstack		186
+__SYSCALL(__NR_sigaltstack, sys_sigaltstack)
+#define __NR_sendfile			187
+__SYSCALL(__NR_sendfile, sys_sendfile)
+__SYSCALL(188, sys_ni_syscall)		/* 188 reserved */
+__SYSCALL(189, sys_ni_syscall)		/* 189 reserved */
+#define __NR_vfork			190
+__SYSCALL(__NR_vfork, sys_vfork)
+#define __NR_ugetrlimit			191	/* SuS compliant getrlimit */
+__SYSCALL(__NR_ugetrlimit, sys_getrlimit)
+#define __NR_mmap2			192
+__SYSCALL(__NR_mmap2, sys_mmap2)
+#define __NR_truncate64			193
+__SYSCALL(__NR_truncate64, sys_truncate64)
+#define __NR_ftruncate64		194
+__SYSCALL(__NR_ftruncate64, sys_ftruncate64)
+#define __NR_stat64			195
+__SYSCALL(__NR_stat64, sys_stat64)
+#define __NR_lstat64			196
+__SYSCALL(__NR_lstat64, sys_lstat64)
+#define __NR_fstat64			197
+__SYSCALL(__NR_fstat64, sys_fstat64)
+#define __NR_lchown32			198
+__SYSCALL(__NR_lchown32, sys_lchown)
+#define __NR_getuid32			199
+__SYSCALL(__NR_getuid32, sys_getuid)
+#define __NR_getgid32			200
+__SYSCALL(__NR_getgid32, sys_getgid)
+#define __NR_geteuid32			201
+__SYSCALL(__NR_geteuid32, sys_geteuid)
+#define __NR_getegid32			202
+__SYSCALL(__NR_getegid32, sys_getegid)
+#define __NR_setreuid32			203
+__SYSCALL(__NR_setreuid32, sys_setreuid)
+#define __NR_setregid32			204
+__SYSCALL(__NR_setregid32, sys_setregid)
+#define __NR_getgroups32		205
+__SYSCALL(__NR_getgroups32, sys_getgroups)
+#define __NR_setgroups32		206
+__SYSCALL(__NR_setgroups32, sys_setgroups)
+#define __NR_fchown32			207
+__SYSCALL(__NR_fchown32, sys_fchown)
+#define __NR_setresuid32		208
+__SYSCALL(__NR_setresuid32, sys_setresuid)
+#define __NR_getresuid32		209
+__SYSCALL(__NR_getresuid32, sys_getresuid)
+#define __NR_setresgid32		210
+__SYSCALL(__NR_setresgid32, sys_setresgid)
+#define __NR_getresgid32		211
+__SYSCALL(__NR_getresgid32, sys_getresgid)
+#define __NR_chown32			212
+__SYSCALL(__NR_chown32, sys_chown)
+#define __NR_setuid32			213
+__SYSCALL(__NR_setuid32, sys_setuid)
+#define __NR_setgid32			214
+__SYSCALL(__NR_setgid32, sys_setgid)
+#define __NR_setfsuid32			215
+__SYSCALL(__NR_setfsuid32, sys_setfsuid)
+#define __NR_setfsgid32			216
+__SYSCALL(__NR_setfsgid32, sys_setfsgid)
+#define __NR_getdents64			217
+__SYSCALL(__NR_getdents64, sys_getdents64)
+#define __NR_pivot_root			218
+__SYSCALL(__NR_pivot_root, sys_pivot_root)
+#define __NR_mincore			219
+__SYSCALL(__NR_mincore, sys_mincore)
+#define __NR_madvise			220
+__SYSCALL(__NR_madvise, sys_madvise)
+#define __NR_fcntl64			221
+__SYSCALL(__NR_fcntl64, sys_fcntl64)
+__SYSCALL(222, sys_ni_syscall)		/* 222 for tux */
+__SYSCALL(223, sys_ni_syscall)		/* 223 is unused */
+#define __NR_gettid			224
+__SYSCALL(__NR_gettid, sys_gettid)
+#define __NR_readahead			225
+__SYSCALL(__NR_readahead, sys_readahead)
+#define __NR_setxattr			226
+__SYSCALL(__NR_setxattr, sys_setxattr)
+#define __NR_lsetxattr			227
+__SYSCALL(__NR_lsetxattr, sys_lsetxattr)
+#define __NR_fsetxattr			228
+__SYSCALL(__NR_fsetxattr, sys_fsetxattr)
+#define __NR_getxattr			229
+__SYSCALL(__NR_getxattr, sys_getxattr)
+#define __NR_lgetxattr			230
+__SYSCALL(__NR_lgetxattr, sys_lgetxattr)
+#define __NR_fgetxattr			231
+__SYSCALL(__NR_fgetxattr, sys_fgetxattr)
+#define __NR_listxattr			232
+__SYSCALL(__NR_listxattr, sys_listxattr)
+#define __NR_llistxattr			233
+__SYSCALL(__NR_llistxattr, sys_llistxattr)
+#define __NR_flistxattr			234
+__SYSCALL(__NR_flistxattr, sys_flistxattr)
+#define __NR_removexattr		235
+__SYSCALL(__NR_removexattr, sys_removexattr)
+#define __NR_lremovexattr		236
+__SYSCALL(__NR_lremovexattr, sys_lremovexattr)
+#define __NR_fremovexattr		237
+__SYSCALL(__NR_fremovexattr, sys_fremovexattr)
+#define __NR_tkill			238
+__SYSCALL(__NR_tkill, sys_tkill)
+#define __NR_sendfile64			239
+__SYSCALL(__NR_sendfile64, sys_sendfile64)
+#define __NR_futex			240
+__SYSCALL(__NR_futex, sys_futex)
+#define __NR_sched_setaffinity		241
+__SYSCALL(__NR_sched_setaffinity, sys_sched_setaffinity)
+#define __NR_sched_getaffinity		242
+__SYSCALL(__NR_sched_getaffinity, sys_sched_getaffinity)
+#define __NR_io_setup			243
+__SYSCALL(__NR_io_setup, sys_io_setup)
+#define __NR_io_destroy			244
+__SYSCALL(__NR_io_destroy, sys_io_destroy)
+#define __NR_io_getevents		245
+__SYSCALL(__NR_io_getevents, sys_io_getevents)
+#define __NR_io_submit			246
+__SYSCALL(__NR_io_submit, sys_io_submit)
+#define __NR_io_cancel			247
+__SYSCALL(__NR_io_cancel, sys_io_cancel)
+#define __NR_exit_group			248
+__SYSCALL(__NR_exit_group, sys_exit_group)
+#define __NR_lookup_dcookie		249
+__SYSCALL(__NR_lookup_dcookie, sys_lookup_dcookie)
+#define __NR_epoll_create		250
+__SYSCALL(__NR_epoll_create, sys_epoll_create)
+#define __NR_epoll_ctl			251
+__SYSCALL(__NR_epoll_ctl, sys_epoll_ctl)
+#define __NR_epoll_wait			252
+__SYSCALL(__NR_epoll_wait, sys_epoll_wait)
+#define __NR_remap_file_pages		253
+__SYSCALL(__NR_remap_file_pages, sys_remap_file_pages)
+__SYSCALL(254, sys_ni_syscall)		/* 254 for set_thread_area */
+__SYSCALL(255, sys_ni_syscall)		/* 255 for get_thread_area */
+#define __NR_set_tid_address		256
+__SYSCALL(__NR_set_tid_address, sys_set_tid_address)
+#define __NR_timer_create		257
+__SYSCALL(__NR_timer_create, sys_timer_create)
+#define __NR_timer_settime		258
+__SYSCALL(__NR_timer_settime, sys_timer_settime)
+#define __NR_timer_gettime		259
+__SYSCALL(__NR_timer_gettime, sys_timer_gettime)
+#define __NR_timer_getoverrun		260
+__SYSCALL(__NR_timer_getoverrun, sys_timer_getoverrun)
+#define __NR_timer_delete		261
+__SYSCALL(__NR_timer_delete, sys_timer_delete)
+#define __NR_clock_settime		262
+__SYSCALL(__NR_clock_settime, sys_clock_settime)
+#define __NR_clock_gettime		263
+__SYSCALL(__NR_clock_gettime, sys_clock_gettime)
+#define __NR_clock_getres		264
+__SYSCALL(__NR_clock_getres, sys_clock_getres)
+#define __NR_clock_nanosleep		265
+__SYSCALL(__NR_clock_nanosleep, sys_clock_nanosleep)
+#define __NR_statfs64			266
+__SYSCALL(__NR_statfs64, sys_statfs64)
+#define __NR_fstatfs64			267
+__SYSCALL(__NR_fstatfs64, sys_fstatfs64)
+#define __NR_tgkill			268
+__SYSCALL(__NR_tgkill, sys_tgkill)
+#define __NR_utimes			269
+__SYSCALL(__NR_utimes, sys_utimes)
+#define __NR_fadvise64			270
+__SYSCALL(__NR_fadvise64, sys_fadvise64_64)
+#define __NR_pciconfig_iobase		271
+__SYSCALL(__NR_pciconfig_iobase, sys_pciconfig_iobase)
+#define __NR_pciconfig_read		272
+__SYSCALL(__NR_pciconfig_read, sys_pciconfig_read)
+#define __NR_pciconfig_write		273
+__SYSCALL(__NR_pciconfig_write, sys_pciconfig_write)
+#define __NR_mq_open			274
+__SYSCALL(__NR_mq_open, sys_mq_open)
+#define __NR_mq_unlink			275
+__SYSCALL(__NR_mq_unlink, sys_mq_unlink)
+#define __NR_mq_timedsend		276
+__SYSCALL(__NR_mq_timedsend, sys_mq_timedsend)
+#define __NR_mq_timedreceive		277
+__SYSCALL(__NR_mq_timedreceive, sys_mq_timedreceive)
+#define __NR_mq_notify			278
+__SYSCALL(__NR_mq_notify, sys_mq_notify)
+#define __NR_mq_getsetattr		279
+__SYSCALL(__NR_mq_getsetattr, sys_mq_getsetattr)
+#define __NR_waitid			280
+__SYSCALL(__NR_waitid, sys_waitid)
+#define __NR_socket			281
+__SYSCALL(__NR_socket, sys_socket)
+#define __NR_bind			282
+__SYSCALL(__NR_bind, sys_bind)
+#define __NR_connect			283
+__SYSCALL(__NR_connect, sys_connect)
+#define __NR_listen			284
+__SYSCALL(__NR_listen, sys_listen)
+#define __NR_accept			285
+__SYSCALL(__NR_accept, sys_accept)
+#define __NR_getsockname		286
+__SYSCALL(__NR_getsockname, sys_getsockname)
+#define __NR_getpeername		287
+__SYSCALL(__NR_getpeername, sys_getpeername)
+#define __NR_socketpair			288
+__SYSCALL(__NR_socketpair, sys_socketpair)
+#define __NR_send			289
+__SYSCALL(__NR_send, sys_send)
+#define __NR_sendto			290
+__SYSCALL(__NR_sendto, sys_sendto)
+#define __NR_recv			291
+__SYSCALL(__NR_recv, sys_recv)
+#define __NR_recvfrom			292
+__SYSCALL(__NR_recvfrom, sys_recvfrom)
+#define __NR_shutdown			293
+__SYSCALL(__NR_shutdown, sys_shutdown)
+#define __NR_setsockopt			294
+__SYSCALL(__NR_setsockopt, sys_setsockopt)
+#define __NR_getsockopt			295
+__SYSCALL(__NR_getsockopt, sys_getsockopt)
+#define __NR_sendmsg			296
+__SYSCALL(__NR_sendmsg, sys_sendmsg)
+#define __NR_recvmsg			297
+__SYSCALL(__NR_recvmsg, sys_recvmsg)
+#define __NR_semop			298
+__SYSCALL(__NR_semop, sys_semop)
+#define __NR_semget			299
+__SYSCALL(__NR_semget, sys_semget)
+#define __NR_semctl			300
+__SYSCALL(__NR_semctl, sys_semctl)
+#define __NR_msgsnd			301
+__SYSCALL(__NR_msgsnd, sys_msgsnd)
+#define __NR_msgrcv			302
+__SYSCALL(__NR_msgrcv, sys_msgrcv)
+#define __NR_msgget			303
+__SYSCALL(__NR_msgget, sys_msgget)
+#define __NR_msgctl			304
+__SYSCALL(__NR_msgctl, sys_msgctl)
+#define __NR_shmat			305
+__SYSCALL(__NR_shmat, sys_shmat)
+#define __NR_shmdt			306
+__SYSCALL(__NR_shmdt, sys_shmdt)
+#define __NR_shmget			307
+__SYSCALL(__NR_shmget, sys_shmget)
+#define __NR_shmctl			308
+__SYSCALL(__NR_shmctl, sys_shmctl)
+#define __NR_add_key			309
+__SYSCALL(__NR_add_key, sys_add_key)
+#define __NR_request_key		310
+__SYSCALL(__NR_request_key, sys_request_key)
+#define __NR_keyctl			311
+__SYSCALL(__NR_keyctl, sys_keyctl)
+#define __NR_semtimedop			312
+__SYSCALL(__NR_semtimedop, sys_semtimedop)
+#define __NR_vserver			313
+__SYSCALL(__NR_vserver, sys_ni_syscall)
+#define __NR_ioprio_set			314
+__SYSCALL(__NR_ioprio_set, sys_ioprio_set)
+#define __NR_ioprio_get			315
+__SYSCALL(__NR_ioprio_get, sys_ioprio_get)
+#define __NR_inotify_init		316
+__SYSCALL(__NR_inotify_init, sys_inotify_init)
+#define __NR_inotify_add_watch		317
+__SYSCALL(__NR_inotify_add_watch, sys_inotify_add_watch)
+#define __NR_inotify_rm_watch		318
+__SYSCALL(__NR_inotify_rm_watch, sys_inotify_rm_watch)
+#define __NR_mbind			319
+__SYSCALL(__NR_mbind, sys_mbind)
+#define __NR_get_mempolicy		320
+__SYSCALL(__NR_get_mempolicy, sys_get_mempolicy)
+#define __NR_set_mempolicy		321
+__SYSCALL(__NR_set_mempolicy, sys_set_mempolicy)
+#define __NR_openat			322
+__SYSCALL(__NR_openat, sys_openat)
+#define __NR_mkdirat			323
+__SYSCALL(__NR_mkdirat, sys_mkdirat)
+#define __NR_mknodat			324
+__SYSCALL(__NR_mknodat, sys_mknodat)
+#define __NR_fchownat			325
+__SYSCALL(__NR_fchownat, sys_fchownat)
+#define __NR_futimesat			326
+__SYSCALL(__NR_futimesat, sys_futimesat)
+#define __NR_fstatat64			327
+__SYSCALL(__NR_fstatat64, sys_fstatat64)
+#define __NR_unlinkat			328
+__SYSCALL(__NR_unlinkat, sys_unlinkat)
+#define __NR_renameat			329
+__SYSCALL(__NR_renameat, sys_renameat)
+#define __NR_linkat			330
+__SYSCALL(__NR_linkat, sys_linkat)
+#define __NR_symlinkat			331
+__SYSCALL(__NR_symlinkat, sys_symlinkat)
+#define __NR_readlinkat			332
+__SYSCALL(__NR_readlinkat, sys_readlinkat)
+#define __NR_fchmodat			333
+__SYSCALL(__NR_fchmodat, sys_fchmodat)
+#define __NR_faccessat			334
+__SYSCALL(__NR_faccessat, sys_faccessat)
+#define __NR_pselect6			335
+__SYSCALL(__NR_pselect6, sys_pselect6)
+#define __NR_ppoll			336
+__SYSCALL(__NR_ppoll, sys_ppoll)
+#define __NR_unshare			337
+__SYSCALL(__NR_unshare, sys_unshare)
+#define __NR_set_robust_list		338
+__SYSCALL(__NR_set_robust_list, sys_set_robust_list)
+#define __NR_get_robust_list		339
+__SYSCALL(__NR_get_robust_list, sys_get_robust_list)
+#define __NR_splice			340
+__SYSCALL(__NR_splice, sys_splice)
+#define __NR_sync_file_range2		341
+__SYSCALL(__NR_sync_file_range2, sys_sync_file_range2)
+#define __NR_tee			342
+__SYSCALL(__NR_tee, sys_tee)
+#define __NR_vmsplice			343
+__SYSCALL(__NR_vmsplice, sys_vmsplice)
+#define __NR_move_pages			344
+__SYSCALL(__NR_move_pages, sys_move_pages)
+#define __NR_getcpu			345
+__SYSCALL(__NR_getcpu, sys_getcpu)
+#define __NR_epoll_pwait		346
+__SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
+#define __NR_kexec_load			347
+__SYSCALL(__NR_kexec_load, sys_kexec_load)
+#define __NR_utimensat			348
+__SYSCALL(__NR_utimensat, sys_utimensat)
+#define __NR_signalfd			349
+__SYSCALL(__NR_signalfd, sys_signalfd)
+#define __NR_timerfd_create		350
+__SYSCALL(__NR_timerfd_create, sys_timerfd_create)
+#define __NR_eventfd			351
+__SYSCALL(__NR_eventfd, sys_eventfd)
+#define __NR_fallocate			352
+__SYSCALL(__NR_fallocate, sys_fallocate)
+#define __NR_timerfd_settime		353
+__SYSCALL(__NR_timerfd_settime, sys_timerfd_settime)
+#define __NR_timerfd_gettime		354
+__SYSCALL(__NR_timerfd_gettime, sys_timerfd_gettime)
+#define __NR_signalfd4			355
+__SYSCALL(__NR_signalfd4, sys_signalfd4)
+#define __NR_eventfd2			356
+__SYSCALL(__NR_eventfd2, sys_eventfd2)
+#define __NR_epoll_create1		357
+__SYSCALL(__NR_epoll_create1, sys_epoll_create1)
+#define __NR_dup3			358
+__SYSCALL(__NR_dup3, sys_dup3)
+#define __NR_pipe2			359
+__SYSCALL(__NR_pipe2, sys_pipe2)
+#define __NR_inotify_init1		360
+__SYSCALL(__NR_inotify_init1, sys_inotify_init1)
+#define __NR_preadv			361
+__SYSCALL(__NR_preadv, sys_preadv)
+#define __NR_pwritev			362
+__SYSCALL(__NR_pwritev, sys_pwritev)
+#define __NR_rt_tgsigqueueinfo		363
+__SYSCALL(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo)
+#define __NR_perf_event_open		364
+__SYSCALL(__NR_perf_event_open, sys_perf_event_open)
+#define __NR_recvmmsg			365
+__SYSCALL(__NR_recvmmsg, sys_recvmmsg)
+#define __NR_accept4			366
+__SYSCALL(__NR_accept4, sys_accept4)
+#define __NR_fanotify_init		367
+__SYSCALL(__NR_fanotify_init, sys_fanotify_init)
+#define __NR_fanotify_mark		368
+__SYSCALL(__NR_fanotify_mark, sys_fanotify_mark)
+#define __NR_prlimit64			369
+__SYSCALL(__NR_prlimit64, sys_prlimit64)
+#define __NR_name_to_handle_at		370
+__SYSCALL(__NR_name_to_handle_at, sys_name_to_handle_at)
+#define __NR_open_by_handle_at		371
+__SYSCALL(__NR_open_by_handle_at, sys_open_by_handle_at)
+#define __NR_clock_adjtime		372
+__SYSCALL(__NR_clock_adjtime, sys_clock_adjtime)
+#define __NR_syncfs			373
+__SYSCALL(__NR_syncfs, sys_syncfs)
+
+/*
+ * The following SVCs are ARM private.
+ */
+#define __ARM_NR_COMPAT_BASE		0x0f0000
+#define __ARM_NR_compat_cacheflush	(__ARM_NR_COMPAT_BASE+2)
+#define __ARM_NR_compat_set_tls		(__ARM_NR_COMPAT_BASE+5)
+
+#endif	/* __SYSCALL_COMPAT */
+
+#define __NR_compat_syscalls		374
+
+#define __ARCH_WANT_COMPAT_IPC_PARSE_VERSION
+#define __ARCH_WANT_COMPAT_STAT64
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
+
+#endif /* __ASM_UNISTD32_H */
diff --git a/arch/arm64/kernel/kuser32.S b/arch/arm64/kernel/kuser32.S
new file mode 100644
index 0000000..c3bab17
--- /dev/null
+++ b/arch/arm64/kernel/kuser32.S
@@ -0,0 +1,77 @@
+/*
+ * Low-level user helpers placed in the vectors page for AArch32.
+ *
+ * Copyright (C) 1996-2000 Russell King.
+ * Copyright (C) 2012 ARM Ltd
+ * Author: Will Deacon <will.deacon at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * AArch32 user helpers.
+ *
+ * Each segment is 32-byte aligned and will be moved to the top of the high
+ * vector page.  New segments (if ever needed) must be added in front of
+ * existing ones.  This mechanism should be used only for things that are
+ * really small and justified, and not be abused freely.
+ *
+ * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
+ */
+	.align	5
+	.globl	__kuser_helper_start
+__kuser_helper_start:
+
+__kuser_cmpxchg64:			// 0xffff0f60
+	.inst	0xe92d00f0		//	push		{r4, r5, r6, r7}
+	.inst	0xe1c040d0		//	ldrd		r4, r5, [r0]
+	.inst	0xe1c160d0		//	ldrd		r6, r7, [r1]
+	.inst	0xf57ff05f		//	dmb		sy
+	.inst	0xe1b20f9f		// 1:	ldrexd		r0, r1, [r2]
+	.inst	0xe0303004		//	eors		r3, r0, r4
+	.inst	0x00313005		//	eoreqs		r3, r1, r5
+	.inst	0x01a23f96		//	strexdeq	r3, r6, [r2]
+	.inst	0x03330001		//	teqeq		r3, #1
+	.inst	0x0afffff9		//	beq		1b
+	.inst	0xf57ff05f		//	dmb		sy
+	.inst	0xe2730000		//	rsbs		r0, r3, #0
+	.inst	0xe8bd00f0		//	pop		{r4, r5, r6, r7}
+	.inst	0xe12fff1e		//	bx		lr
+
+	.align	5
+__kuser_memory_barrier:			// 0xffff0fa0
+	.inst	0xf57ff05f		// dmb	sy
+	.inst	0xe12fff1e		// bx	lr
+
+	.align	5
+__kuser_cmpxchg:			// 0xffff0fc0
+	.inst	0xf57ff05f		//	dmb		sy
+	.inst	0xe1923f9f		// 1:	ldrex		r3, [r2]
+	.inst	0xe0533000		//	subs		r3, r3, r0
+	.inst	0x01823f91		//	strexeq	r3, r1, [r2]
+	.inst	0x03330001		//	teqeq		r3, #1
+	.inst	0x0afffffa		//	beq		1b
+	.inst	0xe2730000		//	rsbs		r0, r3, #0
+	.inst	0xeaffffef		//	b		<__kuser_memory_barrier>
+
+	.align	5
+__kuser_get_tls:			// 0xffff0fe0
+	.inst	0xee1d0f70		// mrc	p15, 0, r0, c13, c0, 3
+	.inst	0xe12fff1e		// bx	lr
+	.rep	5
+	.word	0
+	.endr
+
+__kuser_helper_version:			// 0xffff0ffc
+	.word	((__kuser_helper_end - __kuser_helper_start) >> 5)
+	.globl	__kuser_helper_end
+__kuser_helper_end:
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
new file mode 100644
index 0000000..4bb754c
--- /dev/null
+++ b/arch/arm64/kernel/signal32.c
@@ -0,0 +1,876 @@
+/*
+ * Based on arch/arm/kernel/signal.c
+ *
+ * Copyright (C) 1995-2009 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ * Modified by Will Deacon <will.deacon at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define __SYSCALL_COMPAT
+
+#include <linux/compat.h>
+#include <linux/signal.h>
+#include <linux/syscalls.h>
+#include <linux/ratelimit.h>
+
+#include <asm/fpsimd.h>
+#include <asm/signal32.h>
+#include <asm/uaccess.h>
+#include <asm/unistd.h>
+
+typedef struct compat_siginfo {
+	int si_signo;
+	int si_errno;
+	int si_code;
+
+	union {
+		/* The padding is the same size as AArch64. */
+		int _pad[SI_PAD_SIZE];
+
+		/* kill() */
+		struct {
+			compat_pid_t _pid;	/* sender's pid */
+			__compat_uid32_t _uid;	/* sender's uid */
+		} _kill;
+
+		/* POSIX.1b timers */
+		struct {
+			compat_timer_t _tid;	/* timer id */
+			int _overrun;		/* overrun count */
+			compat_sigval_t _sigval;	/* same as below */
+			int _sys_private;       /* not to be passed to user */
+		} _timer;
+
+		/* POSIX.1b signals */
+		struct {
+			compat_pid_t _pid;	/* sender's pid */
+			__compat_uid32_t _uid;	/* sender's uid */
+			compat_sigval_t _sigval;
+		} _rt;
+
+		/* SIGCHLD */
+		struct {
+			compat_pid_t _pid;	/* which child */
+			__compat_uid32_t _uid;	/* sender's uid */
+			int _status;		/* exit code */
+			compat_clock_t _utime;
+			compat_clock_t _stime;
+		} _sigchld;
+
+		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+		struct {
+			compat_uptr_t _addr; /* faulting insn/memory ref. */
+			short _addr_lsb; /* LSB of the reported address */
+		} _sigfault;
+
+		/* SIGPOLL */
+		struct {
+			compat_long_t _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
+			int _fd;
+		} _sigpoll;
+	} _sifields;
+} compat_siginfo_t;
+
+struct compat_sigaction {
+	compat_uptr_t			sa_handler;
+	compat_ulong_t			sa_flags;
+	compat_uptr_t			sa_restorer;
+	compat_sigset_t			sa_mask;
+};
+
+struct compat_old_sigaction {
+	compat_uptr_t			sa_handler;
+	compat_old_sigset_t		sa_mask;
+	compat_ulong_t			sa_flags;
+	compat_uptr_t			sa_restorer;
+};
+
+typedef struct compat_sigaltstack {
+	compat_uptr_t			ss_sp;
+	int				ss_flags;
+	compat_size_t			ss_size;
+} compat_stack_t;
+
+struct compat_sigcontext {
+	/* We always set these two fields to 0 */
+	compat_ulong_t			trap_no;
+	compat_ulong_t			error_code;
+
+	compat_ulong_t			oldmask;
+	compat_ulong_t			arm_r0;
+	compat_ulong_t			arm_r1;
+	compat_ulong_t			arm_r2;
+	compat_ulong_t			arm_r3;
+	compat_ulong_t			arm_r4;
+	compat_ulong_t			arm_r5;
+	compat_ulong_t			arm_r6;
+	compat_ulong_t			arm_r7;
+	compat_ulong_t			arm_r8;
+	compat_ulong_t			arm_r9;
+	compat_ulong_t			arm_r10;
+	compat_ulong_t			arm_fp;
+	compat_ulong_t			arm_ip;
+	compat_ulong_t			arm_sp;
+	compat_ulong_t			arm_lr;
+	compat_ulong_t			arm_pc;
+	compat_ulong_t			arm_cpsr;
+	compat_ulong_t			fault_address;
+};
+
+struct compat_ucontext {
+	compat_ulong_t			uc_flags;
+	struct compat_ucontext		*uc_link;
+	compat_stack_t			uc_stack;
+	struct compat_sigcontext	uc_mcontext;
+	compat_sigset_t			uc_sigmask;
+	int		__unused[32 - (sizeof (compat_sigset_t) / sizeof (int))];
+	compat_ulong_t	uc_regspace[128] __attribute__((__aligned__(8)));
+};
+
+struct compat_vfp_sigframe {
+	compat_ulong_t	magic;
+	compat_ulong_t	size;
+	struct compat_user_vfp {
+		compat_u64	fpregs[32];
+		compat_ulong_t	fpscr;
+	} ufp;
+	struct compat_user_vfp_exc {
+		compat_ulong_t	fpexc;
+		compat_ulong_t	fpinst;
+		compat_ulong_t	fpinst2;
+	} ufp_exc;
+} __attribute__((__aligned__(8)));
+
+#define VFP_MAGIC		0x56465001
+#define VFP_STORAGE_SIZE	sizeof(struct compat_vfp_sigframe)
+
+struct compat_aux_sigframe {
+	struct compat_vfp_sigframe	vfp;
+
+	/* Something that isn't a valid magic number for any coprocessor.  */
+	unsigned long			end_magic;
+} __attribute__((__aligned__(8)));
+
+struct compat_sigframe {
+	struct compat_ucontext	uc;
+	compat_ulong_t		retcode[2];
+};
+
+struct compat_rt_sigframe {
+	struct compat_siginfo info;
+	struct compat_sigframe sig;
+};
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+/*
+ * For ARM syscalls, the syscall number has to be loaded into r7.
+ * We do not support an OABI userspace.
+ */
+#define MOV_R7_NR_SIGRETURN	(0xe3a07000 | __NR_sigreturn)
+#define SVC_SYS_SIGRETURN	(0xef000000 | __NR_sigreturn)
+#define MOV_R7_NR_RT_SIGRETURN	(0xe3a07000 | __NR_rt_sigreturn)
+#define SVC_SYS_RT_SIGRETURN	(0xef000000 | __NR_rt_sigreturn)
+
+/*
+ * For Thumb syscalls, we also pass the syscall number via r7. We therefore
+ * need two 16-bit instructions.
+ */
+#define SVC_THUMB_SIGRETURN	(((0xdf00 | __NR_sigreturn) << 16) | \
+				   0x2700 | __NR_sigreturn)
+#define SVC_THUMB_RT_SIGRETURN	(((0xdf00 | __NR_rt_sigreturn) << 16) | \
+				   0x2700 | __NR_rt_sigreturn)
+
+const compat_ulong_t aarch32_sigret_code[6] = {
+	/*
+	 * AArch32 sigreturn code.
+	 * We don't construct an OABI SWI - instead we just set the imm24 field
+	 * to the EABI syscall number so that we create a sane disassembly.
+	 */
+	MOV_R7_NR_SIGRETURN,    SVC_SYS_SIGRETURN,    SVC_THUMB_SIGRETURN,
+	MOV_R7_NR_RT_SIGRETURN, SVC_SYS_RT_SIGRETURN, SVC_THUMB_RT_SIGRETURN,
+};
+
+static inline int put_sigset_t(compat_sigset_t __user *uset, sigset_t *set)
+{
+	compat_sigset_t	cset;
+
+	cset.sig[0] = set->sig[0] & 0xffffffffull;
+	cset.sig[1] = set->sig[0] >> 32;
+
+	return copy_to_user(uset, &cset, sizeof(*uset));
+}
+
+static inline int get_sigset_t(sigset_t *set,
+			       const compat_sigset_t __user *uset)
+{
+	compat_sigset_t s32;
+
+	if (copy_from_user(&s32, uset, sizeof(*uset)))
+		return -EFAULT;
+
+	set->sig[0] = s32.sig[0] | (((long)s32.sig[1]) << 32);
+	return 0;
+}
+
+int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
+{
+	int err;
+
+	if (!access_ok(VERIFY_WRITE, to, sizeof(*to)))
+		return -EFAULT;
+
+	/* If you change siginfo_t structure, please be sure
+	 * this code is fixed accordingly.
+	 * It should never copy any pad contained in the structure
+	 * to avoid security leaks, but must copy the generic
+	 * 3 ints plus the relevant union member.
+	 * This routine must convert siginfo from 64bit to 32bit as well
+	 * at the same time.
+	 */
+	err = __put_user(from->si_signo, &to->si_signo);
+	err |= __put_user(from->si_errno, &to->si_errno);
+	err |= __put_user((short)from->si_code, &to->si_code);
+	if (from->si_code < 0)
+		err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad,
+				      SI_PAD_SIZE);
+	else switch (from->si_code & __SI_MASK) {
+	case __SI_KILL:
+		err |= __put_user(from->si_pid, &to->si_pid);
+		err |= __put_user(from->si_uid, &to->si_uid);
+		break;
+	case __SI_TIMER:
+		 err |= __put_user(from->si_tid, &to->si_tid);
+		 err |= __put_user(from->si_overrun, &to->si_overrun);
+		 err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr,
+				   &to->si_ptr);
+		break;
+	case __SI_POLL:
+		err |= __put_user(from->si_band, &to->si_band);
+		err |= __put_user(from->si_fd, &to->si_fd);
+		break;
+	case __SI_FAULT:
+		err |= __put_user((compat_uptr_t)(unsigned long)from->si_addr,
+				  &to->si_addr);
+#ifdef BUS_MCEERR_AO
+		/*
+		 * Other callers might not initialize the si_lsb field,
+		 * so check explicitely for the right codes here.
+		 */
+		if (from->si_code == BUS_MCEERR_AR || from->si_code == BUS_MCEERR_AO)
+			err |= __put_user(from->si_addr_lsb, &to->si_addr_lsb);
+#endif
+		break;
+	case __SI_CHLD:
+		err |= __put_user(from->si_pid, &to->si_pid);
+		err |= __put_user(from->si_uid, &to->si_uid);
+		err |= __put_user(from->si_status, &to->si_status);
+		err |= __put_user(from->si_utime, &to->si_utime);
+		err |= __put_user(from->si_stime, &to->si_stime);
+		break;
+	case __SI_RT: /* This is not generated by the kernel as of now. */
+	case __SI_MESGQ: /* But this is */
+		err |= __put_user(from->si_pid, &to->si_pid);
+		err |= __put_user(from->si_uid, &to->si_uid);
+		err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, &to->si_ptr);
+		break;
+	default: /* this is just in case for now ... */
+		err |= __put_user(from->si_pid, &to->si_pid);
+		err |= __put_user(from->si_uid, &to->si_uid);
+		break;
+	}
+	return err;
+}
+
+int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
+{
+	memset(to, 0, sizeof *to);
+
+	if (copy_from_user(to, from, __ARCH_SI_PREAMBLE_SIZE) ||
+	    copy_from_user(to->_sifields._pad,
+			   from->_sifields._pad, SI_PAD_SIZE))
+		return -EFAULT;
+
+	return 0;
+}
+
+/*
+ * VFP save/restore code.
+ */
+static int compat_preserve_vfp_context(struct compat_vfp_sigframe __user *frame)
+{
+	struct fpsimd_state *fpsimd = &current->thread.fpsimd_state;
+	compat_ulong_t magic = VFP_MAGIC;
+	compat_ulong_t size = VFP_STORAGE_SIZE;
+	compat_ulong_t fpscr, fpexc;
+	int err = 0;
+
+	/*
+	 * Save the hardware registers to the fpsimd_state structure.
+	 * Note that this also saves V16-31, which aren't visible
+	 * in AArch32.
+	 */
+	fpsimd_save_state(fpsimd);
+
+	/* Place structure header on the stack */
+	__put_user_error(magic, &frame->magic, err);
+	__put_user_error(size, &frame->size, err);
+
+	/*
+	 * Now copy the FP registers. Since the registers are packed,
+	 * we can copy the prefix we want (V0-V15) as it is.
+	 * FIXME: Won't work if big endian.
+	 */
+	err |= __copy_to_user(&frame->ufp.fpregs, fpsimd->vregs,
+			      sizeof(frame->ufp.fpregs));
+
+	/* Create an AArch32 fpscr from the fpsr and the fpcr. */
+	fpscr = (fpsimd->fpsr & VFP_FPSCR_STAT_MASK) |
+		(fpsimd->fpcr & VFP_FPSCR_CTRL_MASK);
+	__put_user_error(fpscr, &frame->ufp.fpscr, err);
+
+	/*
+	 * The exception register aren't available so we fake up a
+	 * basic FPEXC and zero everything else.
+	 */
+	fpexc = (1 << 30);
+	__put_user_error(fpexc, &frame->ufp_exc.fpexc, err);
+	__put_user_error(0, &frame->ufp_exc.fpinst, err);
+	__put_user_error(0, &frame->ufp_exc.fpinst2, err);
+
+	return err ? -EFAULT : 0;
+}
+
+static int compat_restore_vfp_context(struct compat_vfp_sigframe __user *frame)
+{
+	struct fpsimd_state fpsimd;
+	compat_ulong_t magic = VFP_MAGIC;
+	compat_ulong_t size = VFP_STORAGE_SIZE;
+	compat_ulong_t fpscr;
+	int err = 0;
+
+	__get_user_error(magic, &frame->magic, err);
+	__get_user_error(size, &frame->size, err);
+
+	if (err)
+		return -EFAULT;
+	if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
+		return -EINVAL;
+
+	/*
+	 * Copy the FP registers into the start of the fpsimd_state.
+	 * FIXME: Won't work if big endian.
+	 */
+	err |= __copy_from_user(fpsimd.vregs, frame->ufp.fpregs,
+				sizeof(frame->ufp.fpregs));
+
+	/* Extract the fpsr and the fpcr from the fpscr */
+	__get_user_error(fpscr, &frame->ufp.fpscr, err);
+	fpsimd.fpsr = fpscr & VFP_FPSCR_STAT_MASK;
+	fpsimd.fpcr = fpscr & VFP_FPSCR_CTRL_MASK;
+
+	/*
+	 * We don't need to touch the exception register, so
+	 * reload the hardware state.
+	 */
+	if (!err) {
+		preempt_disable();
+		fpsimd_load_state(&fpsimd);
+		preempt_enable();
+	}
+
+	return err ? -EFAULT : 0;
+}
+
+/*
+ * atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage int compat_sys_sigsuspend(int restart, compat_ulong_t oldmask,
+				     compat_old_sigset_t mask)
+{
+	sigset_t blocked;
+
+	siginitset(&current->blocked, mask);
+	return sigsuspend(&blocked);
+}
+
+asmlinkage int compat_sys_sigaction(int sig,
+				    const struct compat_old_sigaction __user *act,
+				    struct compat_old_sigaction __user *oact)
+{
+	struct k_sigaction new_ka, old_ka;
+	int ret;
+	compat_old_sigset_t mask;
+	compat_uptr_t handler, restorer;
+
+	if (act) {
+		if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
+		    __get_user(handler, &act->sa_handler) ||
+		    __get_user(restorer, &act->sa_restorer) ||
+		    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+		    __get_user(mask, &act->sa_mask))
+			return -EFAULT;
+
+		new_ka.sa.sa_handler = compat_ptr(handler);
+		new_ka.sa.sa_restorer = compat_ptr(restorer);
+		siginitset(&new_ka.sa.sa_mask, mask);
+	}
+
+	ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+
+	if (!ret && oact) {
+		if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
+		    __put_user(ptr_to_compat(old_ka.sa.sa_handler),
+			       &oact->sa_handler) ||
+		    __put_user(ptr_to_compat(old_ka.sa.sa_restorer),
+			       &oact->sa_restorer) ||
+		    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+		    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
+			return -EFAULT;
+	}
+
+	return ret;
+}
+
+asmlinkage int compat_sys_rt_sigaction(int sig,
+				       const struct compat_sigaction __user *act,
+				       struct compat_sigaction __user *oact,
+				       compat_size_t sigsetsize)
+{
+	struct k_sigaction new_ka, old_ka;
+	int ret;
+
+	/* XXX: Don't preclude handling different sized sigset_t's.  */
+	if (sigsetsize != sizeof(compat_sigset_t))
+		return -EINVAL;
+
+	if (act) {
+		compat_uptr_t handler, restorer;
+
+		ret = get_user(handler, &act->sa_handler);
+		new_ka.sa.sa_handler = compat_ptr(handler);
+		ret |= get_user(restorer, &act->sa_restorer);
+		new_ka.sa.sa_restorer = compat_ptr(restorer);
+		ret |= get_sigset_t(&new_ka.sa.sa_mask, &act->sa_mask);
+		ret |= __get_user(new_ka.sa.sa_flags, &act->sa_flags);
+		if (ret)
+			return -EFAULT;
+	}
+
+	ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+	if (!ret && oact) {
+		ret = put_user(ptr_to_compat(old_ka.sa.sa_handler), &oact->sa_handler);
+		ret |= put_sigset_t(&oact->sa_mask, &old_ka.sa.sa_mask);
+		ret |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
+	}
+	return ret;
+}
+
+int compat_do_sigaltstack(compat_uptr_t compat_uss, compat_uptr_t compat_uoss,
+			  compat_ulong_t sp)
+{
+	compat_stack_t __user *newstack = compat_ptr(compat_uss);
+	compat_stack_t __user *oldstack = compat_ptr(compat_uoss);
+	compat_uptr_t ss_sp;
+	int ret;
+	mm_segment_t old_fs;
+	stack_t uss, uoss;
+
+	/* Marshall the compat new stack into a stack_t */
+	if (newstack) {
+		if (get_user(ss_sp, &newstack->ss_sp) ||
+		    __get_user(uss.ss_flags, &newstack->ss_flags) ||
+		    __get_user(uss.ss_size, &newstack->ss_size))
+			return -EFAULT;
+		uss.ss_sp = compat_ptr(ss_sp);
+	}
+
+	old_fs = get_fs();
+	set_fs(KERNEL_DS);
+	/* The __user pointer casts are valid because of the set_fs() */
+	ret = do_sigaltstack(
+		newstack ? (stack_t __user *) &uss : NULL,
+		oldstack ? (stack_t __user *) &uoss : NULL,
+		(unsigned long)sp);
+	set_fs(old_fs);
+
+	/* Convert the old stack_t into a compat stack. */
+	if (!ret && oldstack &&
+		(put_user(ptr_to_compat(uoss.ss_sp), &oldstack->ss_sp) ||
+		 __put_user(uoss.ss_flags, &oldstack->ss_flags) ||
+		 __put_user(uoss.ss_size, &oldstack->ss_size)))
+		return -EFAULT;
+	return ret;
+}
+
+static int compat_restore_sigframe(struct pt_regs *regs,
+				   struct compat_sigframe __user *sf)
+{
+	int err;
+	sigset_t set;
+	struct compat_aux_sigframe __user *aux;
+
+	err = get_sigset_t(&set, &sf->uc.uc_sigmask);
+	if (err == 0) {
+		sigdelsetmask(&set, ~_BLOCKABLE);
+		set_current_blocked(&set);
+	}
+
+	__get_user_error(regs->regs[0], &sf->uc.uc_mcontext.arm_r0, err);
+	__get_user_error(regs->regs[1], &sf->uc.uc_mcontext.arm_r1, err);
+	__get_user_error(regs->regs[2], &sf->uc.uc_mcontext.arm_r2, err);
+	__get_user_error(regs->regs[3], &sf->uc.uc_mcontext.arm_r3, err);
+	__get_user_error(regs->regs[4], &sf->uc.uc_mcontext.arm_r4, err);
+	__get_user_error(regs->regs[5], &sf->uc.uc_mcontext.arm_r5, err);
+	__get_user_error(regs->regs[6], &sf->uc.uc_mcontext.arm_r6, err);
+	__get_user_error(regs->regs[7], &sf->uc.uc_mcontext.arm_r7, err);
+	__get_user_error(regs->regs[8], &sf->uc.uc_mcontext.arm_r8, err);
+	__get_user_error(regs->regs[9], &sf->uc.uc_mcontext.arm_r9, err);
+	__get_user_error(regs->regs[10], &sf->uc.uc_mcontext.arm_r10, err);
+	__get_user_error(regs->regs[11], &sf->uc.uc_mcontext.arm_fp, err);
+	__get_user_error(regs->regs[12], &sf->uc.uc_mcontext.arm_ip, err);
+	__get_user_error(regs->compat_sp, &sf->uc.uc_mcontext.arm_sp, err);
+	__get_user_error(regs->compat_lr, &sf->uc.uc_mcontext.arm_lr, err);
+	__get_user_error(regs->pc, &sf->uc.uc_mcontext.arm_pc, err);
+	__get_user_error(regs->pstate, &sf->uc.uc_mcontext.arm_cpsr, err);
+
+	/*
+	 * Avoid compat_sys_sigreturn() restarting.
+	 */
+	regs->syscallno = ~0UL;
+
+	err |= !valid_user_regs(&regs->user_regs);
+
+	aux = (struct compat_aux_sigframe __user *) sf->uc.uc_regspace;
+	if (err == 0)
+		err |= compat_restore_vfp_context(&aux->vfp);
+
+	return err;
+}
+
+asmlinkage int compat_sys_sigreturn(struct pt_regs *regs)
+{
+	struct compat_sigframe __user *frame;
+
+	/* Always make any pending restarted system calls return -EINTR */
+	current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+	/*
+	 * Since we stacked the signal on a 64-bit boundary,
+	 * then 'sp' should be word aligned here.  If it's
+	 * not, then the user is trying to mess with us.
+	 */
+	if (regs->compat_sp & 7)
+		goto badframe;
+
+	frame = (struct compat_sigframe __user *)regs->compat_sp;
+
+	if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
+		goto badframe;
+
+	if (compat_restore_sigframe(regs, frame))
+		goto badframe;
+
+	return regs->regs[0];
+
+badframe:
+	if (show_unhandled_signals)
+		printk_ratelimited(KERN_INFO "%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
+				   current->comm, task_pid_nr(current), __func__,
+				   regs->pc, regs->sp);
+	force_sig(SIGSEGV, current);
+	return 0;
+}
+
+asmlinkage int compat_sys_rt_sigreturn(struct pt_regs *regs)
+{
+	struct compat_rt_sigframe __user *frame;
+
+	/* Always make any pending restarted system calls return -EINTR */
+	current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+	/*
+	 * Since we stacked the signal on a 64-bit boundary,
+	 * then 'sp' should be word aligned here.  If it's
+	 * not, then the user is trying to mess with us.
+	 */
+	if (regs->compat_sp & 7)
+		goto badframe;
+
+	frame = (struct compat_rt_sigframe __user *)regs->compat_sp;
+
+	if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
+		goto badframe;
+
+	if (compat_restore_sigframe(regs, &frame->sig))
+		goto badframe;
+
+	if (compat_do_sigaltstack(ptr_to_compat(&frame->sig.uc.uc_stack),
+				 ptr_to_compat((void __user *)NULL),
+				 regs->compat_sp) == -EFAULT)
+		goto badframe;
+
+	return regs->regs[0];
+
+badframe:
+	if (show_unhandled_signals)
+		printk_ratelimited(KERN_INFO "%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
+				   current->comm, task_pid_nr(current), __func__,
+				   regs->pc, regs->sp);
+	force_sig(SIGSEGV, current);
+	return 0;
+}
+
+static inline void __user *compat_get_sigframe(struct k_sigaction *ka,
+					       struct pt_regs *regs,
+					       int framesize)
+{
+	compat_ulong_t sp = regs->compat_sp;
+	void __user *frame;
+
+	/*
+	 * This is the X/Open sanctioned signal stack switching.
+	 */
+	if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp))
+		sp = current->sas_ss_sp + current->sas_ss_size;
+
+	/*
+	 * ATPCS B01 mandates 8-byte alignment
+	 */
+	frame = compat_ptr((compat_uptr_t)((sp - framesize) & ~7));
+
+	/*
+	 * Check that we can actually write to the signal frame.
+	 */
+	if (!access_ok(VERIFY_WRITE, frame, framesize))
+		frame = NULL;
+
+	return frame;
+}
+
+static int compat_setup_return(struct pt_regs *regs, struct k_sigaction *ka,
+			       compat_ulong_t __user *rc, void __user *frame,
+			       int usig)
+{
+	compat_ulong_t handler = ptr_to_compat(ka->sa.sa_handler);
+	compat_ulong_t retcode;
+	compat_ulong_t spsr = regs->pstate & ~PSR_f;
+	int thumb;
+
+	/* Check if the handler is written for ARM or Thumb */
+	thumb = handler & 1;
+
+	if (thumb) {
+		spsr |= COMPAT_PSR_T_BIT;
+		spsr &= ~COMPAT_PSR_IT_MASK;
+	} else {
+		spsr &= ~COMPAT_PSR_T_BIT;
+	}
+
+	if (ka->sa.sa_flags & SA_RESTORER) {
+		retcode = ptr_to_compat(ka->sa.sa_restorer);
+	} else {
+		/* Set up sigreturn pointer */
+		unsigned int idx = thumb << 1;
+
+		if (ka->sa.sa_flags & SA_SIGINFO)
+			idx += 3;
+
+		retcode = AARCH32_VECTORS_BASE +
+			  AARCH32_KERN_SIGRET_CODE_OFFSET +
+			  (idx << 2) + thumb;
+	}
+
+	regs->regs[0]	= usig;
+	regs->compat_sp	= ptr_to_compat(frame);
+	regs->compat_lr	= retcode;
+	regs->pc	= handler;
+	regs->pstate	= spsr;
+
+	return 0;
+}
+
+static int compat_setup_sigframe(struct compat_sigframe __user *sf,
+				 struct pt_regs *regs, sigset_t *set)
+{
+	struct compat_aux_sigframe __user *aux;
+	int err = 0;
+
+	__put_user_error(regs->regs[0], &sf->uc.uc_mcontext.arm_r0, err);
+	__put_user_error(regs->regs[1], &sf->uc.uc_mcontext.arm_r1, err);
+	__put_user_error(regs->regs[2], &sf->uc.uc_mcontext.arm_r2, err);
+	__put_user_error(regs->regs[3], &sf->uc.uc_mcontext.arm_r3, err);
+	__put_user_error(regs->regs[4], &sf->uc.uc_mcontext.arm_r4, err);
+	__put_user_error(regs->regs[5], &sf->uc.uc_mcontext.arm_r5, err);
+	__put_user_error(regs->regs[6], &sf->uc.uc_mcontext.arm_r6, err);
+	__put_user_error(regs->regs[7], &sf->uc.uc_mcontext.arm_r7, err);
+	__put_user_error(regs->regs[8], &sf->uc.uc_mcontext.arm_r8, err);
+	__put_user_error(regs->regs[9], &sf->uc.uc_mcontext.arm_r9, err);
+	__put_user_error(regs->regs[10], &sf->uc.uc_mcontext.arm_r10, err);
+	__put_user_error(regs->regs[11], &sf->uc.uc_mcontext.arm_fp, err);
+	__put_user_error(regs->regs[12], &sf->uc.uc_mcontext.arm_ip, err);
+	__put_user_error(regs->compat_sp, &sf->uc.uc_mcontext.arm_sp, err);
+	__put_user_error(regs->compat_lr, &sf->uc.uc_mcontext.arm_lr, err);
+	__put_user_error(regs->pc, &sf->uc.uc_mcontext.arm_pc, err);
+	__put_user_error(regs->pstate, &sf->uc.uc_mcontext.arm_cpsr, err);
+
+	__put_user_error((compat_ulong_t)0, &sf->uc.uc_mcontext.trap_no, err);
+	__put_user_error((compat_ulong_t)0, &sf->uc.uc_mcontext.error_code, err);
+	__put_user_error(current->thread.fault_address, &sf->uc.uc_mcontext.fault_address, err);
+	__put_user_error(set->sig[0], &sf->uc.uc_mcontext.oldmask, err);
+
+	err |= put_sigset_t(&sf->uc.uc_sigmask, set);
+
+	aux = (struct compat_aux_sigframe __user *) sf->uc.uc_regspace;
+
+	if (err == 0)
+		err |= compat_preserve_vfp_context(&aux->vfp);
+	__put_user_error(0, &aux->end_magic, err);
+
+	return err;
+}
+
+/*
+ * 32-bit signal handling routines called from signal.c
+ */
+int compat_setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
+			  sigset_t *set, struct pt_regs *regs)
+{
+	struct compat_rt_sigframe __user *frame;
+	compat_stack_t stack;
+	int err = 0;
+
+	frame = compat_get_sigframe(ka, regs, sizeof(*frame));
+
+	if (!frame)
+		return 1;
+
+	err |= copy_siginfo_to_user32(&frame->info, info);
+
+	__put_user_error(0, &frame->sig.uc.uc_flags, err);
+	__put_user_error(NULL, &frame->sig.uc.uc_link, err);
+
+	memset(&stack, 0, sizeof(stack));
+	stack.ss_sp = (compat_uptr_t)current->sas_ss_sp;
+	stack.ss_flags = sas_ss_flags(regs->compat_sp);
+	stack.ss_size = current->sas_ss_size;
+	err |= __copy_to_user(&frame->sig.uc.uc_stack, &stack, sizeof(stack));
+
+	err |= compat_setup_sigframe(&frame->sig, regs, set);
+	if (err == 0)
+		err = compat_setup_return(regs, ka, frame->sig.retcode, frame,
+					  usig);
+
+	if (err == 0) {
+		regs->regs[1] = (compat_ulong_t)(unsigned long)&frame->info;
+		regs->regs[2] = (compat_ulong_t)(unsigned long)&frame->sig.uc;
+	}
+
+	return err;
+}
+
+int compat_setup_frame(int usig, struct k_sigaction *ka, sigset_t *set,
+		       struct pt_regs *regs)
+{
+	struct compat_sigframe __user *frame;
+	int err = 0;
+
+	frame = compat_get_sigframe(ka, regs, sizeof(*frame));
+
+	if (!frame)
+		return 1;
+
+	__put_user_error(0x5ac3c35a, &frame->uc.uc_flags, err);
+
+	err |= compat_setup_sigframe(frame, regs, set);
+	if (err == 0)
+		err = compat_setup_return(regs, ka, frame->retcode, frame, usig);
+
+	return err;
+}
+
+/*
+ * RT signals don't have generic compat wrappers.
+ * See arch/powerpc/kernel/signal_32.c
+ */
+asmlinkage int compat_sys_rt_sigprocmask(int how, compat_sigset_t __user *set,
+					 compat_sigset_t __user *oset,
+					 compat_size_t sigsetsize)
+{
+	sigset_t s;
+	sigset_t __user *up;
+	int ret;
+	mm_segment_t old_fs = get_fs();
+
+	if (set) {
+		if (get_sigset_t(&s, set))
+			return -EFAULT;
+	}
+
+	set_fs(KERNEL_DS);
+	/* This is valid because of the set_fs() */
+	up = (sigset_t __user *) &s;
+	ret = sys_rt_sigprocmask(how, set ? up : NULL, oset ? up : NULL,
+				 sigsetsize);
+	set_fs(old_fs);
+	if (ret)
+		return ret;
+	if (oset) {
+		if (put_sigset_t(oset, &s))
+			return -EFAULT;
+	}
+	return 0;
+}
+
+asmlinkage int compat_sys_rt_sigpending(compat_sigset_t __user *set,
+					compat_size_t sigsetsize)
+{
+	sigset_t s;
+	int ret;
+	mm_segment_t old_fs = get_fs();
+
+	set_fs(KERNEL_DS);
+	/* The __user pointer cast is valid because of the set_fs() */
+	ret = sys_rt_sigpending((sigset_t __user *) &s, sigsetsize);
+	set_fs(old_fs);
+	if (!ret) {
+		if (put_sigset_t(set, &s))
+			return -EFAULT;
+	}
+	return ret;
+}
+
+asmlinkage int compat_sys_rt_sigqueueinfo(int pid, int sig,
+					  compat_siginfo_t __user *uinfo)
+{
+	siginfo_t info;
+	int ret;
+	mm_segment_t old_fs = get_fs();
+
+	ret = copy_siginfo_from_user32(&info, uinfo);
+	if (unlikely(ret))
+		return ret;
+
+	set_fs (KERNEL_DS);
+	/* The __user pointer cast is valid because of the set_fs() */
+	ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *) &info);
+	set_fs (old_fs);
+	return ret;
+}
+
+void compat_setup_restart_syscall(struct pt_regs *regs)
+{
+       regs->regs[7] = __NR_restart_syscall;
+}
diff --git a/arch/arm64/kernel/sys32.S b/arch/arm64/kernel/sys32.S
new file mode 100644
index 0000000..fc764c1
--- /dev/null
+++ b/arch/arm64/kernel/sys32.S
@@ -0,0 +1,283 @@
+/*
+ * Compat system call wrappers
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Authors: Will Deacon <will.deacon at arm.com>
+ *	    Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * System call wrappers for the AArch32 compatibility layer.
+ */
+compat_sys_fork_wrapper:
+	mov	x0, sp
+	b	compat_sys_fork
+ENDPROC(compat_sys_fork_wrapper)
+
+compat_sys_vfork_wrapper:
+	mov	x0, sp
+	b	compat_sys_vfork
+ENDPROC(compat_sys_vfork_wrapper)
+
+compat_sys_execve_wrapper:
+	mov	x3, sp
+	b	compat_sys_execve
+ENDPROC(compat_sys_execve_wrapper)
+
+compat_sys_clone_wrapper:
+	mov	x5, sp
+	b	compat_sys_clone
+ENDPROC(compat_sys_clone_wrapper)
+
+compat_sys_sigreturn_wrapper:
+	mov	x0, sp
+	mov	x27, #0		// prevent syscall restart handling (why)
+	b	compat_sys_sigreturn
+ENDPROC(compat_sys_sigreturn_wrapper)
+
+compat_sys_rt_sigreturn_wrapper:
+	mov	x0, sp
+	mov	x27, #0		// prevent syscall restart handling (why)
+	b	compat_sys_rt_sigreturn
+ENDPROC(compat_sys_rt_sigreturn_wrapper)
+
+compat_sys_sigaltstack_wrapper:
+	ldr	x2, [sp, #S_COMPAT_SP]
+	b	compat_do_sigaltstack
+ENDPROC(compat_sys_sigaltstack_wrapper)
+
+compat_sys_statfs64_wrapper:
+	mov	w3, #84
+	cmp	w1, #88
+	csel	w1, w3, w1, eq
+	b	compat_sys_statfs64
+ENDPROC(compat_sys_statfs64_wrapper)
+
+compat_sys_fstatfs64_wrapper:
+	mov	w3, #84
+	cmp	w1, #88
+	csel	w1, w3, w1, eq
+	b	compat_sys_fstatfs64
+ENDPROC(compat_sys_fstatfs64_wrapper)
+
+/*
+ * Wrappers for AArch32 syscalls that either take 64-bit parameters
+ * in registers or that take 32-bit parameters which require sign
+ * extension.
+ */
+compat_sys_lseek_wrapper:
+	sxtw	x1, w1
+	b	sys_lseek
+ENDPROC(compat_sys_lseek_wrapper)
+
+compat_sys_pread64_wrapper:
+	orr	x3, x4, x5, lsl #32
+	b	sys_pread64
+ENDPROC(compat_sys_pread64_wrapper)
+
+compat_sys_pwrite64_wrapper:
+	orr	x3, x4, x5, lsl #32
+	b	sys_pwrite64
+ENDPROC(compat_sys_pwrite64_wrapper)
+
+compat_sys_truncate64_wrapper:
+	orr	x1, x2, x3, lsl #32
+	b	sys_truncate
+ENDPROC(compat_sys_truncate64_wrapper)
+
+compat_sys_ftruncate64_wrapper:
+	orr	x1, x2, x3, lsl #32
+	b	sys_ftruncate
+ENDPROC(compat_sys_ftruncate64_wrapper)
+
+compat_sys_readahead_wrapper:
+	orr	x1, x2, x3, lsl #32
+	mov	w2, w4
+	b	sys_readahead
+ENDPROC(compat_sys_readahead_wrapper)
+
+compat_sys_lookup_dcookie:
+	orr	x0, x0, x1, lsl #32
+	mov	w1, w2
+	mov	w2, w3
+	b	sys_lookup_dcookie
+ENDPROC(compat_sys_lookup_dcookie)
+
+compat_sys_fadvise64_64_wrapper:
+	mov	w6, w1
+	orr	x1, x2, x3, lsl #32
+	orr	x2, x4, x5, lsl #32
+	mov	w3, w6
+	b	sys_fadvise64_64
+ENDPROC(compat_sys_fadvise64_64_wrapper)
+
+compat_sys_sync_file_range2_wrapper:
+	orr	x2, x2, x3, lsl #32
+	orr	x3, x4, x5, lsl #32
+	b	sys_sync_file_range2
+ENDPROC(compat_sys_sync_file_range2_wrapper)
+
+compat_sys_fallocate_wrapper:
+	orr	x2, x2, x3, lsl #32
+	orr	x3, x4, x5, lsl #32
+	b	sys_fallocate
+ENDPROC(compat_sys_fallocate_wrapper)
+
+compat_sys_fanotify_mark_wrapper:
+	orr	x2, x2, x3, lsl #32
+	mov	w3, w4
+	mov	w4, w5
+	b	sys_fanotify_mark
+ENDPROC(compat_sys_fanotify_mark_wrapper)
+
+/*
+ * Use the compat system call wrappers.
+ */
+#define sys_fork		compat_sys_fork_wrapper
+#define sys_open		compat_sys_open
+#define sys_execve		compat_sys_execve_wrapper
+#define sys_lseek		compat_sys_lseek_wrapper
+#define sys_mount		compat_sys_mount
+#define sys_ptrace		compat_sys_ptrace
+#define sys_times		compat_sys_times
+#define sys_ioctl		compat_sys_ioctl
+#define sys_fcntl		compat_sys_fcntl
+#define sys_ustat		compat_sys_ustat
+#define sys_sigaction		compat_sys_sigaction
+#define sys_sigsuspend		compat_sys_sigsuspend
+#define sys_sigpending		compat_sys_sigpending
+#define sys_setrlimit		compat_sys_setrlimit
+#define sys_getrusage		compat_sys_getrusage
+#define sys_gettimeofday	compat_sys_gettimeofday
+#define sys_settimeofday	compat_sys_settimeofday
+#define sys_statfs		compat_sys_statfs
+#define sys_fstatfs		compat_sys_fstatfs
+#define sys_setitimer		compat_sys_setitimer
+#define sys_getitimer		compat_sys_getitimer
+#define sys_newstat		compat_sys_newstat
+#define sys_newlstat		compat_sys_newlstat
+#define sys_newfstat		compat_sys_newfstat
+#define sys_wait4		compat_sys_wait4
+#define sys_sysinfo		compat_sys_sysinfo
+#define sys_sigreturn		compat_sys_sigreturn_wrapper
+#define sys_clone		compat_sys_clone_wrapper
+#define sys_adjtimex		compat_sys_adjtimex
+#define sys_sigprocmask		compat_sys_sigprocmask
+#define sys_personality		compat_sys_personality
+#define sys_getdents		compat_sys_getdents
+#define sys_select		compat_sys_select
+#define sys_readv		compat_sys_readv
+#define sys_writev		compat_sys_writev
+#define sys_sysctl		compat_sys_sysctl
+#define sys_sched_rr_get_interval compat_sys_sched_rr_get_interval
+#define sys_nanosleep		compat_sys_nanosleep
+#define sys_rt_sigreturn	compat_sys_rt_sigreturn_wrapper
+#define sys_rt_sigaction	compat_sys_rt_sigaction
+#define sys_rt_sigprocmask	compat_sys_rt_sigprocmask
+#define sys_rt_sigpending	compat_sys_rt_sigpending
+#define sys_rt_sigtimedwait	compat_sys_rt_sigtimedwait
+#define sys_rt_sigqueueinfo	compat_sys_rt_sigqueueinfo
+#define sys_rt_sigsuspend	compat_sys_rt_sigsuspend
+#define sys_pread64		compat_sys_pread64_wrapper
+#define sys_pwrite64		compat_sys_pwrite64_wrapper
+#define sys_sigaltstack		compat_sys_sigaltstack_wrapper
+#define sys_sendfile		compat_sys_sendfile
+#define sys_vfork		compat_sys_vfork_wrapper
+#define sys_getrlimit		compat_sys_getrlimit
+#define sys_mmap2		sys_mmap_pgoff
+#define sys_truncate64		compat_sys_truncate64_wrapper
+#define sys_ftruncate64		compat_sys_ftruncate64_wrapper
+#define sys_getdents64		compat_sys_getdents64
+#define sys_fcntl64		compat_sys_fcntl64
+#define sys_readahead		compat_sys_readahead_wrapper
+#define sys_futex		compat_sys_futex
+#define sys_sched_setaffinity	compat_sys_sched_setaffinity
+#define sys_sched_getaffinity	compat_sys_sched_getaffinity
+#define sys_io_setup		compat_sys_io_setup
+#define sys_io_getevents	compat_sys_io_getevents
+#define sys_io_submit		compat_sys_io_submit
+#define sys_lookup_dcookie	compat_sys_lookup_dcookie
+#define sys_timer_create	compat_sys_timer_create
+#define sys_timer_settime	compat_sys_timer_settime
+#define sys_timer_gettime	compat_sys_timer_gettime
+#define sys_clock_settime	compat_sys_clock_settime
+#define sys_clock_gettime	compat_sys_clock_gettime
+#define sys_clock_getres	compat_sys_clock_getres
+#define sys_clock_nanosleep	compat_sys_clock_nanosleep
+#define sys_statfs64		compat_sys_statfs64_wrapper
+#define sys_fstatfs64		compat_sys_fstatfs64_wrapper
+#define sys_utimes		compat_sys_utimes
+#define sys_fadvise64_64	compat_sys_fadvise64_64_wrapper
+#define sys_mq_open		compat_sys_mq_open
+#define sys_mq_timedsend	compat_sys_mq_timedsend
+#define sys_mq_timedreceive	compat_sys_mq_timedreceive
+#define sys_mq_notify		compat_sys_mq_notify
+#define sys_mq_getsetattr	compat_sys_mq_getsetattr
+#define sys_waitid		compat_sys_waitid
+#define sys_recv		compat_sys_recv
+#define sys_recvfrom		compat_sys_recvfrom
+#define sys_setsockopt		compat_sys_setsockopt
+#define sys_getsockopt		compat_sys_getsockopt
+#define sys_sendmsg		compat_sys_sendmsg
+#define sys_recvmsg		compat_sys_recvmsg
+#define sys_semctl		compat_sys_semctl
+#define sys_msgsnd		compat_sys_msgsnd
+#define sys_msgrcv		compat_sys_msgrcv
+#define sys_msgctl		compat_sys_msgctl
+#define sys_shmat		compat_sys_shmat
+#define sys_shmctl		compat_sys_shmctl
+#define sys_keyctl		compat_sys_keyctl
+#define sys_semtimedop		compat_sys_semtimedop
+#define sys_mbind		compat_sys_mbind
+#define sys_get_mempolicy	compat_sys_get_mempolicy
+#define sys_set_mempolicy	compat_sys_set_mempolicy
+#define sys_openat		compat_sys_openat
+#define sys_futimesat		compat_sys_futimesat
+#define sys_pselect6		compat_sys_pselect6
+#define sys_ppoll		compat_sys_ppoll
+#define sys_set_robust_list	compat_sys_set_robust_list
+#define sys_get_robust_list	compat_sys_get_robust_list
+#define sys_sync_file_range2	compat_sys_sync_file_range2_wrapper
+#define sys_vmsplice		compat_sys_vmsplice
+#define sys_move_pages		compat_sys_move_pages
+#define sys_epoll_pwait		compat_sys_epoll_pwait
+#define sys_kexec_load		compat_sys_kexec_load
+#define sys_utimensat		compat_sys_utimensat
+#define sys_signalfd		compat_sys_signalfd
+#define sys_fallocate		compat_sys_fallocate_wrapper
+#define sys_timerfd_settime	compat_sys_timerfd_settime
+#define sys_timerfd_gettime	compat_sys_timerfd_gettime
+#define sys_signalfd4		compat_sys_signalfd4
+#define sys_preadv		compat_sys_preadv
+#define sys_pwritev		compat_sys_pwritev
+#define sys_rt_tgsigqueueinfo	compat_sys_rt_tgsigqueueinfo
+#define sys_recvmmsg		compat_sys_recvmmsg
+#define sys_fanotify_mark	compat_sys_fanotify_mark_wrapper
+
+#undef __SYSCALL
+#define __SYSCALL(x, y)		.quad	y	// x
+#define __SYSCALL_COMPAT
+
+/*
+ * The system calls table must be 4KB aligned.
+ */
+	.align	12
+ENTRY(compat_sys_call_table)
+#include <asm/unistd.h>
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
new file mode 100644
index 0000000..025ec0a
--- /dev/null
+++ b/arch/arm64/kernel/sys_compat.c
@@ -0,0 +1,177 @@
+/*
+ * Based on arch/arm/kernel/sys_arm.c
+ *
+ * Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c
+ * Copyright (C) 1995, 1996 Russell King.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define __SYSCALL_COMPAT
+
+#include <linux/compat.h>
+#include <linux/personality.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+
+#include <asm/cacheflush.h>
+#include <asm/unistd.h>
+
+asmlinkage int compat_sys_fork(struct pt_regs *regs)
+{
+	return do_fork(SIGCHLD, regs->compat_sp, regs, 0, NULL, NULL);
+}
+
+asmlinkage int compat_sys_clone(unsigned long clone_flags, unsigned long newsp,
+			  int __user *parent_tidptr, int tls_val,
+			  int __user *child_tidptr, struct pt_regs *regs)
+{
+	if (!newsp)
+		newsp = regs->compat_sp;
+
+	return do_fork(clone_flags, newsp, regs, 0, parent_tidptr, child_tidptr);
+}
+
+asmlinkage int compat_sys_vfork(struct pt_regs *regs)
+{
+	return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->compat_sp,
+		       regs, 0, NULL, NULL);
+}
+
+asmlinkage int compat_sys_execve(const char __user *filenamei,
+				 compat_uptr_t argv, compat_uptr_t envp,
+				 struct pt_regs *regs)
+{
+	int error;
+	char * filename;
+
+	filename = getname(filenamei);
+	error = PTR_ERR(filename);
+	if (IS_ERR(filename))
+		goto out;
+	error = compat_do_execve(filename, compat_ptr(argv), compat_ptr(envp),
+				 regs);
+	putname(filename);
+out:
+	return error;
+}
+
+asmlinkage int compat_sys_sched_rr_get_interval(compat_pid_t pid,
+						struct compat_timespec __user *interval)
+{
+	struct timespec t;
+	int ret;
+	mm_segment_t old_fs = get_fs();
+
+	set_fs(KERNEL_DS);
+	ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
+	set_fs(old_fs);
+	if (put_compat_timespec(&t, interval))
+		return -EFAULT;
+	return ret;
+}
+
+asmlinkage int compat_sys_personality(compat_ulong_t personality)
+{
+	int ret;
+
+	if (personality(current->personality) == PER_LINUX32 &&
+		personality == PER_LINUX)
+		personality = PER_LINUX32;
+	ret = sys_personality(personality);
+	if (ret == PER_LINUX32)
+		ret = PER_LINUX;
+	return ret;
+}
+
+asmlinkage int compat_sys_sendfile(int out_fd, int in_fd,
+				   compat_off_t __user *offset, s32 count)
+{
+	mm_segment_t old_fs = get_fs();
+	int ret;
+	off_t of;
+
+	if (offset && get_user(of, offset))
+		return -EFAULT;
+
+	set_fs(KERNEL_DS);
+	ret = sys_sendfile(out_fd, in_fd, offset ? (off_t __user *)&of : NULL,
+			   count);
+	set_fs(old_fs);
+
+	if (offset && put_user(of, offset))
+		return -EFAULT;
+	return ret;
+}
+
+static inline void
+do_compat_cache_op(unsigned long start, unsigned long end, int flags)
+{
+	struct mm_struct *mm = current->active_mm;
+	struct vm_area_struct *vma;
+
+	if (end < start || flags)
+		return;
+
+	down_read(&mm->mmap_sem);
+	vma = find_vma(mm, start);
+	if (vma && vma->vm_start < end) {
+		if (start < vma->vm_start)
+			start = vma->vm_start;
+		if (end > vma->vm_end)
+			end = vma->vm_end;
+		up_read(&mm->mmap_sem);
+		flush_cache_user_range(start, end);
+		return;
+	}
+	up_read(&mm->mmap_sem);
+}
+
+/*
+ * Handle all unrecognised system calls.
+ */
+long compat_arm_syscall(struct pt_regs *regs)
+{
+	unsigned int no = regs->regs[7];
+
+	switch (no) {
+	/*
+	 * Flush a region from virtual address 'r0' to virtual address 'r1'
+	 * _exclusive_.  There is no alignment requirement on either address;
+	 * user space does not need to know the hardware cache layout.
+	 *
+	 * r2 contains flags.  It should ALWAYS be passed as ZERO until it
+	 * is defined to be something else.  For now we ignore it, but may
+	 * the fires of hell burn in your belly if you break this rule. ;)
+	 *
+	 * (at a later date, we may want to allow this call to not flush
+	 * various aspects of the cache.  Passing '0' will guarantee that
+	 * everything necessary gets flushed to maintain consistency in
+	 * the specified region).
+	 */
+	case __ARM_NR_compat_cacheflush:
+		do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
+		return 0;
+
+	case __ARM_NR_compat_set_tls:
+		current->thread.tp_value = regs->regs[0];
+		asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
+		return 0;
+
+	default:
+		return -ENOSYS;
+	}
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:04 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:04 +0100
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>

The patch contains the exception entry code (kernel/entry.S), pt_regs
structure and related accessors, undefined instruction trapping and
stack tracing.

AArch64 Linux kernel (including kernel threads) runs in EL1 mode using
the SP1 stack. The vectors don't have a fixed address, only alignment
(2^11) requirements.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/ptrace.h     |  206 +++++++++++
 arch/arm64/include/asm/stacktrace.h |   29 ++
 arch/arm64/include/asm/traps.h      |   30 ++
 arch/arm64/kernel/entry.S           |  695 +++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/stacktrace.c      |  127 +++++++
 arch/arm64/kernel/traps.c           |  357 ++++++++++++++++++
 6 files changed, 1444 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/ptrace.h
 create mode 100644 arch/arm64/include/asm/stacktrace.h
 create mode 100644 arch/arm64/include/asm/traps.h
 create mode 100644 arch/arm64/kernel/entry.S
 create mode 100644 arch/arm64/kernel/stacktrace.c
 create mode 100644 arch/arm64/kernel/traps.c

diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
new file mode 100644
index 0000000..a9abace
--- /dev/null
+++ b/arch/arm64/include/asm/ptrace.h
@@ -0,0 +1,206 @@
+/*
+ * Based on arch/arm/include/asm/ptrace.h
+ *
+ * Copyright (C) 1996-2003 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PTRACE_H
+#define __ASM_PTRACE_H
+
+#include <linux/types.h>
+
+#include <asm/hwcap.h>
+
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13
+#define PTRACE_GETFPSIMDREGS	14
+#define PTRACE_SETFPSIMDREGS	15
+/* PTRACE_ATTACH is 16 */
+/* PTRACE_DETACH is 17 */
+#define PTRACE_GET_THREAD_AREA	22
+#define PTRACE_SET_SYSCALL	23
+#define PTRACE_GETHBPREGS	29
+#define PTRACE_SETHBPREGS	30
+
+/* AArch32-specific ptrace requests */
+#define COMPAT_PTRACE_GETVFPREGS	27
+#define COMPAT_PTRACE_SETVFPREGS	28
+
+/*
+ * PSR bits
+ */
+#define PSR_MODE_EL0t	0x00000000
+#define PSR_MODE_EL1t	0x00000004
+#define PSR_MODE_EL1h	0x00000005
+#define PSR_MODE_EL2t	0x00000008
+#define PSR_MODE_EL2h	0x00000009
+#define PSR_MODE_EL3t	0x0000000c
+#define PSR_MODE_EL3h	0x0000000d
+#define PSR_MODE_MASK	0x0000000f
+
+/* AArch32 CPSR bits */
+#define PSR_MODE32_BIT		0x00000010
+#define COMPAT_PSR_MODE_USR	0x00000010
+#define COMPAT_PSR_T_BIT	0x00000020
+#define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
+
+/* AArch64 SPSR bits */
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_A_BIT	0x00000100
+#define PSR_D_BIT	0x00000200
+#define PSR_Q_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
+
+/*
+ * Groups of PSR bits
+ */
+#define PSR_f		0xff000000	/* Flags		*/
+#define PSR_s		0x00ff0000	/* Status		*/
+#define PSR_x		0x0000ff00	/* Extension		*/
+#define PSR_c		0x000000ff	/* Control		*/
+
+/*
+ * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
+ * process is located in memory.
+ */
+#define PT_TEXT_ADDR		0x10000
+#define PT_DATA_ADDR		0x10004
+#define PT_TEXT_END_ADDR	0x10008
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose and floating point registers.
+ */
+struct user_pt_regs {
+	__u64		regs[31];
+	__u64		sp;
+	__u64		pc;
+	__u64		pstate;
+};
+
+struct user_fpsimd_state {
+	__uint128_t	vregs[32];
+	__u32		fpsr;
+	__u32		fpcr;
+};
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_AARCH32_EMULATION
+/* sizeof(struct user) for AArch32 */
+#define COMPAT_USER_SZ	296
+/* AArch32 uses x13 as the stack pointer... */
+#define compat_sp	regs[13]
+/* ... and x14 as the link register. */
+#define compat_lr	regs[14]
+#endif
+
+/*
+ * This struct defines the way the registers are stored on the stack during an
+ * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
+ * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
+ */
+struct pt_regs {
+	union {
+		struct user_pt_regs user_regs;
+		struct {
+			u64 regs[31];
+			u64 sp;
+			u64 pc;
+			u64 pstate;
+		};
+	};
+	u64 orig_x0;
+	u64 syscallno;
+};
+
+#define arch_has_single_step()	(1)
+
+#ifdef CONFIG_AARCH32_EMULATION
+#define compat_thumb_mode(regs) \
+	(((regs)->pstate & COMPAT_PSR_T_BIT))
+#else
+#define compat_thumb_mode(regs) (0)
+#endif
+
+#define user_mode(regs)	\
+	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
+
+#define compat_user_mode(regs)	\
+	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
+	 (PSR_MODE32_BIT | PSR_MODE_EL0t))
+
+#define processor_mode(regs) \
+	((regs)->pstate & PSR_MODE_MASK)
+
+#define interrupts_enabled(regs) \
+	(!((regs)->pstate & PSR_I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+	(!((regs)->pstate & PSR_F_BIT))
+
+#define user_stack_pointer(regs) \
+	((regs)->sp)
+
+/*
+ * Are the current registers suitable for user mode? (used to maintain
+ * security in signal handlers)
+ */
+static inline int valid_user_regs(struct user_pt_regs *regs)
+{
+	if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
+		regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
+
+		/* The T bit is reserved for AArch64 */
+		if (!(regs->pstate & PSR_MODE32_BIT))
+			regs->pstate &= ~COMPAT_PSR_T_BIT;
+
+		return 1;
+	}
+
+	/*
+	 * Force PSR to something logical...
+	 */
+	regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
+			COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
+
+	if (!(regs->pstate & PSR_MODE32_BIT)) {
+		regs->pstate &= ~COMPAT_PSR_T_BIT;
+		regs->pstate |= PSR_MODE_EL0t;
+	}
+
+	return 0;
+}
+
+#define instruction_pointer(regs)	(regs)->pc
+
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *regs);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+
+extern int aarch32_break_trap(struct pt_regs *regs);
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm64/include/asm/stacktrace.h b/arch/arm64/include/asm/stacktrace.h
new file mode 100644
index 0000000..7318f6d
--- /dev/null
+++ b/arch/arm64/include/asm/stacktrace.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_STACKTRACE_H
+#define __ASM_STACKTRACE_H
+
+struct stackframe {
+	unsigned long fp;
+	unsigned long sp;
+	unsigned long pc;
+};
+
+extern int unwind_frame(struct stackframe *frame);
+extern void walk_stackframe(struct stackframe *frame,
+			    int (*fn)(struct stackframe *, void *), void *data);
+
+#endif	/* __ASM_STACKTRACE_H */
diff --git a/arch/arm64/include/asm/traps.h b/arch/arm64/include/asm/traps.h
new file mode 100644
index 0000000..10ca8ff
--- /dev/null
+++ b/arch/arm64/include/asm/traps.h
@@ -0,0 +1,30 @@
+/*
+ * Based on arch/arm/include/asm/traps.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_TRAP_H
+#define __ASM_TRAP_H
+
+static inline int in_exception_text(unsigned long ptr)
+{
+	extern char __exception_text_start[];
+	extern char __exception_text_end[];
+
+	return ptr >= (unsigned long)&__exception_text_start &&
+	       ptr < (unsigned long)&__exception_text_end;
+}
+
+#endif
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
new file mode 100644
index 0000000..32b96ab
--- /dev/null
+++ b/arch/arm64/kernel/entry.S
@@ -0,0 +1,695 @@
+/*
+ * Low-level exception handling code
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Authors:	Catalin Marinas <catalin.marinas at arm.com>
+ *		Will Deacon <will.deacon at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/errno.h>
+#include <asm/thread_info.h>
+#include <asm/unistd.h>
+
+/*
+ * Bad Abort numbers
+ *-----------------
+ */
+#define BAD_SYNC	0
+#define BAD_IRQ		1
+#define BAD_FIQ		2
+#define BAD_ERROR	3
+
+	.macro	kernel_entry, el, regsize = 64
+	sub	sp, sp, #S_FRAME_SIZE - S_LR	// room for LR, SP, SPSR, ELR
+	.if	\regsize == 32
+	mov	w0, w0				// zero upper 32 bits of x0
+	.endif
+	push	x28, x29
+	push	x26, x27
+	push	x24, x25
+	push	x22, x23
+	push	x20, x21
+	push	x18, x19
+	push	x16, x17
+	push	x14, x15
+	push	x12, x13
+	push	x10, x11
+	push	x8, x9
+	push	x6, x7
+	push	x4, x5
+	push	x2, x3
+	push	x0, x1
+	.if	\el == 0
+	mrs	x21, sp_el0
+	.else
+	add	x21, sp, #S_FRAME_SIZE
+	.endif
+	mrs	x22, elr_el1
+	mrs	x23, spsr_el1
+	stp	lr, x21, [sp, #S_LR]
+	stp	x22, x23, [sp, #S_PC]
+
+	/*
+	 * Set syscallno to -1 by default (overridden later if real syscall).
+	 */
+	.if	\el == 0
+	mvn	x21, xzr
+	str	x21, [sp, #S_SYSCALLNO]
+	.endif
+
+	/*
+	 * Registers that may be useful after this macro is invoked:
+	 *
+	 * x21 - aborted SP
+	 * x22 - aborted PC
+	 * x23 - aborted PSTATE
+	*/
+	.endm
+
+	.macro	kernel_exit, el, ret = 0
+	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR
+	.if	\el == 0
+	ldr	x23, [sp, #S_SP]		// load return stack pointer
+	.endif
+	.if	\ret
+	ldr	x1, [sp, #S_X1]			// preserve x0 (syscall return)
+	add	sp, sp, S_X2
+	.else
+	pop	x0, x1
+	.endif
+	pop	x2, x3				// load the rest of the registers
+	pop	x4, x5
+	pop	x6, x7
+	pop	x8, x9
+	msr	elr_el1, x21			// set up the return data
+	msr	spsr_el1, x22
+	.if	\el == 0
+	msr	sp_el0, x23
+	.endif
+	pop	x10, x11
+	pop	x12, x13
+	pop	x14, x15
+	pop	x16, x17
+	pop	x18, x19
+	pop	x20, x21
+	pop	x22, x23
+	pop	x24, x25
+	pop	x26, x27
+	pop	x28, x29
+	ldr	lr, [sp], #S_FRAME_SIZE - S_LR	// load LR and restore SP
+	eret					// return to kernel
+	.endm
+
+	.macro	get_thread_info, rd
+	mov	\rd, sp
+	and	\rd, \rd, #~((1 << 13) - 1)	// top of 8K stack
+	.endm
+
+/*
+ * These are the registers used in the syscall handler, and allow us to
+ * have in theory up to 7 arguments to a function - x0 to x6.
+ *
+ * x7 is reserved for the system call number in 32-bit mode.
+ */
+sc_nr	.req	x25		// number of system calls
+scno	.req	x26		// syscall number
+stbl	.req	x27		// syscall table pointer
+tsk	.req	x28		// current thread_info
+
+/*
+ * Interrupt handling.
+ */
+	.macro	irq_handler
+	ldr	x1, handle_arch_irq
+	mov	x0, sp
+	blr	x1
+	.endm
+
+	.text
+
+/*
+ * Exception vectors.
+ */
+	.macro	ventry	label
+	.align	7
+	b	\label
+	.endm
+
+	.align	11
+ENTRY(vectors)
+	ventry	el1_sync_invalid		// Synchronous EL1t
+	ventry	el1_irq_invalid			// IRQ EL1t
+	ventry	el1_fiq_invalid			// FIQ EL1t
+	ventry	el1_error_invalid		// Error EL1t
+
+	ventry	el1_sync			// Synchronous EL1h
+	ventry	el1_irq				// IRQ EL1h
+	ventry	el1_fiq_invalid			// FIQ EL1h
+	ventry	el1_error_invalid		// Error EL1h
+
+	ventry	el0_sync			// Synchronous 64-bit EL0
+	ventry	el0_irq				// IRQ 64-bit EL0
+	ventry	el0_fiq_invalid			// FIQ 64-bit EL0
+	ventry	el0_error_invalid		// Error 64-bit EL0
+
+#ifdef CONFIG_AARCH32_EMULATION
+	ventry	el0_sync_compat			// Synchronous 32-bit EL0
+	ventry	el0_irq_compat			// IRQ 32-bit EL0
+	ventry	el0_fiq_invalid_compat		// FIQ 32-bit EL0
+	ventry	el0_error_invalid_compat	// Error 32-bit EL0
+#else
+	ventry	el0_sync_invalid		// Synchronous 32-bit EL0
+	ventry	el0_irq_invalid			// IRQ 32-bit EL0
+	ventry	el0_fiq_invalid			// FIQ 32-bit EL0
+	ventry	el0_error_invalid		// Error 32-bit EL0
+#endif
+END(vectors)
+
+/*
+ * Invalid mode handlers
+ */
+	.macro	inv_entry, el, reason, regsize = 64
+	kernel_entry el, \regsize
+	mov	x0, sp
+	mov	x1, #\reason
+	mrs	x2, esr_el1
+	b	bad_mode
+	.endm
+
+el0_sync_invalid:
+	inv_entry 0, BAD_SYNC
+ENDPROC(el0_sync_invalid)
+
+el0_irq_invalid:
+	inv_entry 0, BAD_IRQ
+ENDPROC(el0_irq_invalid)
+
+el0_fiq_invalid:
+	inv_entry 0, BAD_FIQ
+ENDPROC(el0_fiq_invalid)
+
+el0_error_invalid:
+	inv_entry 0, BAD_ERROR
+ENDPROC(el0_error_invalid)
+
+#ifdef CONFIG_AARCH32_EMULATION
+el0_fiq_invalid_compat:
+	inv_entry 0, BAD_FIQ, 32
+ENDPROC(el0_fiq_invalid_compat)
+
+el0_error_invalid_compat:
+	inv_entry 0, BAD_ERROR, 32
+ENDPROC(el0_error_invalid_compat)
+#endif
+
+el1_sync_invalid:
+	inv_entry 1, BAD_SYNC
+ENDPROC(el1_sync_invalid)
+
+el1_irq_invalid:
+	inv_entry 1, BAD_IRQ
+ENDPROC(el1_irq_invalid)
+
+el1_fiq_invalid:
+	inv_entry 1, BAD_FIQ
+ENDPROC(el1_fiq_invalid)
+
+el1_error_invalid:
+	inv_entry 1, BAD_ERROR
+ENDPROC(el1_error_invalid)
+
+/*
+ * EL1 mode handlers.
+ */
+	.align	6
+el1_sync:
+	kernel_entry 1
+	mrs	x1, esr_el1			// read the syndrome register
+	lsr	x24, x1, #26			// exception class
+	cmp	x24, #0x25			// data abort in EL1
+	b.eq	el1_da
+	cmp	x24, #0x18			// configurable trap
+	b.eq	el1_undef
+	cmp	x24, #0x26			// stack alignment exception
+	b.eq	el1_sp_pc
+	cmp	x24, #0x22			// pc alignment exception
+	b.eq	el1_sp_pc
+	cmp	x24, #0x00			// unknown exception in EL1
+	b.eq	el1_undef
+	cmp	x24, #0x30			// debug exception in EL1
+	b.ge	el1_dbg
+	b	el1_inv
+el1_da:
+	/*
+	 * Data abort handling
+	 */
+	mrs	x0, far_el1
+	enable_dbg_if_not_stepping x2
+	// re-enable interrupts if they were enabled in the aborted context
+	tbnz	x23, #7, 1f			// PSR_I_BIT
+	enable_irq
+1:
+	mov	x2, sp				// struct pt_regs
+	bl	do_mem_abort
+
+	// disable interrupts before pulling preserved data off the stack
+	disable_irq
+	kernel_exit 1
+el1_sp_pc:
+	/*
+	 *Stack or PC alignment exception handling
+	 */
+	mrs	x0, far_el1
+	mov	x1, x25
+	mov	x2, sp
+	b	do_sp_pc_abort
+el1_undef:
+	/*
+	 *Undefined instruction
+	 */
+	mov	x0, sp
+	b	do_undefinstr
+el1_dbg:
+	/*
+	 * Debug exception handling
+	 */
+	tbz	x24, #0, el1_inv		// EL1 only
+	mrs	x0, far_el1
+	mov	x2, sp				// struct pt_regs
+	bl	do_debug_exception
+
+	kernel_exit 1
+el1_inv:
+	// TODO: add support for undefined instructions in kernel mode
+	mov	x0, sp
+	mov	x1, #BAD_SYNC
+	mrs	x2, esr_el1
+	b	bad_mode
+ENDPROC(el1_sync)
+
+	.align	6
+el1_irq:
+	kernel_entry 1
+	enable_dbg_if_not_stepping x0
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_off
+#endif
+#ifdef CONFIG_PREEMPT
+	get_thread_info tsk
+	ldr	x24, [tsk, #TI_PREEMPT]		// get preempt count
+	add	x0, x24, #1			// increment it
+	str	x0, [tsk, #TI_PREEMPT]
+#endif
+	irq_handler
+#ifdef CONFIG_PREEMPT
+	str	x24, [tsk, #TI_PREEMPT]		// restore preempt count
+	cbnz	x24, 1f				// preempt count != 0
+	ldr	x0, [tsk, #TI_FLAGS]		// get flags
+	tbz	x0, #TIF_NEED_RESCHED, 1f	// needs rescheduling?
+	bl	el1_preempt
+1:
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_on
+#endif
+	kernel_exit 1
+ENDPROC(el1_irq)
+
+#ifdef CONFIG_PREEMPT
+el1_preempt:
+	mov	x24, lr
+1:	enable_dbg
+	bl	preempt_schedule_irq		// irq en/disable is done inside
+	ldr	x0, [tsk, #TI_FLAGS]		// get new tasks TI_FLAGS
+	tbnz	x0, #TIF_NEED_RESCHED, 1b	// needs rescheduling?
+	ret	x24
+#endif
+
+/*
+ * EL0 mode handlers.
+ */
+	.align	6
+el0_sync:
+	kernel_entry 0
+	mrs	x25, esr_el1			// read the syndrome register
+	lsr	x24, x25, #26			// exception class
+	cmp	x24, #0x15			// SVC in 64-bit state
+	b.eq	el0_svc
+	adr	lr, ret_from_exception
+	cmp	x24, #0x24			// data abort in EL0
+	b.eq	el0_da
+	cmp	x24, #0x20			// instruction abort in EL0
+	b.eq	el0_ia
+	cmp	x24, #0x07			// FP/ASIMD access
+	b.eq	el0_fpsimd_acc
+	cmp	x24, #0x2c			// FP/ASIMD exception
+	b.eq	el0_fpsimd_exc
+	cmp	x24, #0x18			// configurable trap
+	b.eq	el0_undef
+	cmp	x24, #0x26			// stack alignment exception
+	b.eq	el0_sp_pc
+	cmp	x24, #0x22			// pc alignment exception
+	b.eq	el0_sp_pc
+	cmp	x24, #0x00			// unknown exception in EL0
+	b.eq	el0_undef
+	cmp	x24, #0x30			// debug exception in EL0
+	b.ge	el0_dbg
+	b	el0_inv
+
+#ifdef CONFIG_AARCH32_EMULATION
+	.align	6
+el0_sync_compat:
+	kernel_entry 0, 32
+	mrs	x25, esr_el1			// read the syndrome register
+	lsr	x24, x25, #26			// exception class
+	cmp	x24, #0x11			// SVC in 32-bit state
+	b.eq	el0_svc_compat
+	adr	lr, ret_from_exception
+	cmp	x24, #0x24			// data abort in EL0
+	b.eq	el0_da
+	cmp	x24, #0x20			// instruction abort in EL0
+	b.eq	el0_ia
+	cmp	x24, #0x07			// FP/ASIMD access
+	b.eq	el0_fpsimd_acc
+	cmp	x24, #0x28			// FP/ASIMD exception
+	b.eq	el0_fpsimd_exc
+	cmp	x24, #0x00			// unknown exception in EL0
+	b.eq	el0_undef
+	cmp	x24, #0x30			// debug exception in EL0
+	b.ge	el0_dbg
+	b	el0_inv
+el0_svc_compat:
+	/*
+	 * AArch32 syscall handling
+	 */
+	adr	stbl, compat_sys_call_table	// load compat syscall table pointer
+	uxtw	scno, w7			// syscall number in w7 (r7)
+	mov     sc_nr, #__NR_compat_syscalls
+	b	el0_svc_naked
+
+	.align	6
+el0_irq_compat:
+	kernel_entry 0, 32
+	b	el0_irq_naked
+#endif
+
+el0_da:
+	/*
+	 * Data abort handling
+	 */
+	mrs	x0, far_el1
+	disable_step x1
+	isb
+	enable_dbg
+	// enable interrupts before calling the main handler
+	enable_irq
+	mov	x1, x25
+	mov	x2, sp
+	b	do_mem_abort
+el0_ia:
+	/*
+	 * Instruction abort handling
+	 */
+	mrs	x0, far_el1
+	disable_step x1
+	isb
+	enable_dbg
+	// enable interrupts before calling the main handler
+	enable_irq
+	orr	x1, x25, #1 << 24		// use reserved ISS bit for instruction aborts
+	mov	x2, sp
+	b	do_mem_abort
+el0_fpsimd_acc:
+	/*
+	 * Floating Point or Advanced SIMD access
+	 */
+	mov	x0, x25
+	mov	x1, sp
+	b	do_fpsimd_acc
+el0_fpsimd_exc:
+	/*
+	 * Floating Point or Advanced SIMD exception
+	 */
+	mov	x0, x25
+	mov	x1, sp
+	b	do_fpsimd_exc
+el0_sp_pc:
+	/*
+	 * Stack or PC alignment exception handling
+	 */
+	mrs	x0, far_el1
+	disable_step x1
+	isb
+	enable_dbg
+	// enable interrupts before calling the main handler
+	enable_irq
+	mov	x1, x25
+	mov	x2, sp
+	b	do_sp_pc_abort
+el0_undef:
+	/*
+	 *Undefined instruction
+	 */
+	mov	x0, sp
+	b	do_undefinstr
+el0_dbg:
+	/*
+	 * Debug exception handling
+	 */
+	tbnz	x24, #0, el0_inv		// EL0 only
+	mrs	x0, far_el1
+	disable_step x1
+	mov	x1, x25
+	mov	x2, sp
+	b	do_debug_exception
+el0_inv:
+	mov	x0, sp
+	mov	x1, #BAD_SYNC
+	mrs	x2, esr_el1
+	b	bad_mode
+ENDPROC(el0_sync)
+
+	.align	6
+el0_irq:
+	kernel_entry 0
+el0_irq_naked:
+	disable_step x1
+	isb
+	enable_dbg
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_off
+#endif
+	get_thread_info tsk
+#ifdef CONFIG_PREEMPT
+	ldr	x24, [tsk, #TI_PREEMPT]		// get preempt count
+	add	x23, x24, #1			// increment it
+	str	x23, [tsk, #TI_PREEMPT]
+#endif
+	irq_handler
+#ifdef CONFIG_PREEMPT
+	ldr	x0, [tsk, #TI_PREEMPT]
+	str	x24, [tsk, #TI_PREEMPT]
+	cmp	x0, x23
+	b.eq	1f
+	mov	x1, #0
+	str	x1, [x1]			// BUG
+1:
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_on
+#endif
+	b	ret_to_user
+ENDPROC(el0_irq)
+
+/*
+ * This is the return code to user mode for abort handlers
+ */
+ENTRY(ret_from_exception)
+	get_thread_info tsk
+	b	ret_to_user
+ENDPROC(ret_from_exception)
+
+/*
+ * Register switch for AArch64. The callee-saved registers need to be saved
+ * and restored. On entry:
+ *   x0 = previous task_struct (must be preserved across the switch)
+ *   x1 = next task_struct
+ * Previous and next are guaranteed not to be the same.
+ *
+ */
+ENTRY(cpu_switch_to)
+	add	x8, x0, #THREAD_CPU_CONTEXT
+	mov	x9, sp
+	stp	x19, x20, [x8], #16		// store callee-saved registers
+	stp	x21, x22, [x8], #16
+	stp	x23, x24, [x8], #16
+	stp	x25, x26, [x8], #16
+	stp	x27, x28, [x8], #16
+	stp	x29, x9, [x8], #16
+	str	lr, [x8]
+	add	x8, x1, #THREAD_CPU_CONTEXT
+	ldp	x19, x20, [x8], #16		// restore callee-saved registers
+	ldp	x21, x22, [x8], #16
+	ldp	x23, x24, [x8], #16
+	ldp	x25, x26, [x8], #16
+	ldp	x27, x28, [x8], #16
+	ldp	x29, x9, [x8], #16
+	ldr	lr, [x8]
+	mov	sp, x9
+	ret
+ENDPROC(cpu_switch_to)
+
+/*
+ * This is the fast syscall return path.  We do as little as possible here,
+ * and this includes saving x0 back into the kernel stack.
+ */
+ret_fast_syscall:
+	disable_irq				// disable interrupts
+	ldr	x1, [tsk, #TI_FLAGS]
+	and	x2, x1, #_TIF_WORK_MASK
+	cbnz	x2, fast_work_pending
+	tbz	x1, #TIF_SINGLESTEP, fast_exit
+	disable_dbg
+	enable_step x2
+fast_exit:
+	kernel_exit 0, ret = 1
+
+/*
+ * Ok, we need to do extra processing, enter the slow path.
+ */
+fast_work_pending:
+	str	x0, [sp, #S_X0]			// returned x0
+work_pending:
+	tbnz	x1, #TIF_NEED_RESCHED, work_resched
+	/* TIF_SIGPENDING or TIF_NOTIFY_RESUME case */
+	ldr	x2, [sp, #S_PSTATE]
+	mov	x0, sp				// 'regs'
+	tst	x2, #PSR_MODE_MASK		// user mode regs?
+	b.ne	no_work_pending			// returning to kernel
+	bl	do_notify_resume
+	b	ret_to_user
+work_resched:
+	enable_dbg
+	bl	schedule
+
+/*
+ * "slow" syscall return path.
+ */
+ENTRY(ret_to_user)
+	disable_irq				// disable interrupts
+	ldr	x1, [tsk, #TI_FLAGS]
+	and	x2, x1, #_TIF_WORK_MASK
+	cbnz	x2, work_pending
+	tbz	x1, #TIF_SINGLESTEP, no_work_pending
+	disable_dbg
+	enable_step x2
+no_work_pending:
+	kernel_exit 0, ret = 0
+ENDPROC(ret_to_user)
+
+/*
+ * This is how we return from a fork.
+ */
+ENTRY(ret_from_fork)
+	bl	schedule_tail
+	get_thread_info tsk
+	b	ret_to_user
+ENDPROC(ret_from_fork)
+
+/*
+ * SVC handler.
+ */
+	.align	6
+ENTRY(el0_svc)
+	adrp	stbl, sys_call_table		// load syscall table pointer
+	uxtw	scno, w8			// syscall number in w8
+	mov	sc_nr, #__NR_syscalls
+el0_svc_naked:					// compat entry point
+	stp	x0, scno, [sp, #S_ORIG_X0]	// save the original x0 and syscall number
+	disable_step x16
+	isb
+	enable_dbg
+	enable_irq
+
+	get_thread_info tsk
+	ldr	x16, [tsk, #TI_FLAGS]		// check for syscall tracing
+	tbnz	x16, #TIF_SYSCALL_TRACE, __sys_trace // are we tracing syscalls?
+	adr	lr, ret_fast_syscall		// return address
+	cmp     scno, sc_nr                     // check upper syscall limit
+	b.hs	ni_sys
+	ldr	x16, [stbl, scno, lsl #3]	// address in the syscall table
+	br	x16				// call sys_* routine
+ni_sys:
+	mov	x0, sp
+	b	do_ni_syscall
+ENDPROC(el0_svc)
+
+	/*
+	 * This is the really slow path.  We're going to be doing context
+	 * switches, and waiting for our parent to respond.
+	 */
+__sys_trace:
+	mov	x1, sp
+	mov	w0, #0				// trace entry
+	bl	syscall_trace
+	adr	lr, __sys_trace_return		// return address
+	uxtw	scno, w0			// syscall number (possibly new)
+	mov	x1, sp				// pointer to regs
+	cmp	scno, sc_nr			// check upper syscall limit
+	b.hs	ni_sys
+	ldp	x0, x1, [sp]			// restore the syscall args
+	ldp	x2, x3, [sp, #S_X2]
+	ldp	x4, x5, [sp, #S_X4]
+	ldp	x6, x7, [sp, #S_X6]
+	ldr	x16, [stbl, scno, lsl #3]	// address in the syscall table
+	br	x16				// call sys_* routine
+
+__sys_trace_return:
+	str	x0, [sp]			// save returned x0
+	mov	x1, sp
+	mov	w0, #1				// trace exit
+	bl	syscall_trace
+	b	ret_to_user
+
+/*
+ * Special system call wrappers.
+ */
+ENTRY(sys_execve_wrapper)
+	mov	x3, sp
+	b	sys_execve
+ENDPROC(sys_execve_wrapper)
+
+ENTRY(sys_clone_wrapper)
+	mov	x5, sp
+	b	sys_clone
+ENDPROC(sys_clone_wrapper)
+
+ENTRY(sys_rt_sigreturn_wrapper)
+	mov	x0, sp
+	b	sys_rt_sigreturn
+ENDPROC(sys_rt_sigreturn_wrapper)
+
+ENTRY(sys_sigaltstack_wrapper)
+	ldr	x2, [sp, #S_SP]
+	b	sys_sigaltstack
+ENDPROC(sys_sigaltstack_wrapper)
+
+ENTRY(handle_arch_irq)
+	.quad	0
diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
new file mode 100644
index 0000000..d25459f
--- /dev/null
+++ b/arch/arm64/kernel/stacktrace.c
@@ -0,0 +1,127 @@
+/*
+ * Stack tracing support
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+
+#include <asm/stacktrace.h>
+
+/*
+ * AArch64 PCS assigns the frame pointer to x29.
+ *
+ * A simple function prologue looks like this:
+ * 	sub	sp, sp, #0x10
+ *   	stp	x29, x30, [sp]
+ *	mov	x29, sp
+ *
+ * A simple function epilogue looks like this:
+ *	mov	sp, x29
+ *	ldp	x29, x30, [sp]
+ *	add	sp, sp, #0x10
+ */
+int unwind_frame(struct stackframe *frame)
+{
+	unsigned long high, low;
+	unsigned long fp = frame->fp;
+
+	low  = frame->sp;
+	high = ALIGN(low, THREAD_SIZE);
+
+	if (fp < low || fp > high || fp & 0xf)
+		return -EINVAL;
+
+	frame->sp = fp + 0x10;
+	frame->fp = *(unsigned long *)(fp);
+	frame->pc = *(unsigned long *)(fp + 8);
+
+	return 0;
+}
+
+void notrace walk_stackframe(struct stackframe *frame,
+		     int (*fn)(struct stackframe *, void *), void *data)
+{
+	while (1) {
+		int ret;
+
+		if (fn(frame, data))
+			break;
+		ret = unwind_frame(frame);
+		if (ret < 0)
+			break;
+	}
+}
+EXPORT_SYMBOL(walk_stackframe);
+
+#ifdef CONFIG_STACKTRACE
+struct stack_trace_data {
+	struct stack_trace *trace;
+	unsigned int no_sched_functions;
+	unsigned int skip;
+};
+
+static int save_trace(struct stackframe *frame, void *d)
+{
+	struct stack_trace_data *data = d;
+	struct stack_trace *trace = data->trace;
+	unsigned long addr = frame->pc;
+
+	if (data->no_sched_functions && in_sched_functions(addr))
+		return 0;
+	if (data->skip) {
+		data->skip--;
+		return 0;
+	}
+
+	trace->entries[trace->nr_entries++] = addr;
+
+	return trace->nr_entries >= trace->max_entries;
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+	struct stack_trace_data data;
+	struct stackframe frame;
+
+	data.trace = trace;
+	data.skip = trace->skip;
+
+	if (tsk != current) {
+		data.no_sched_functions = 1;
+		frame.fp = thread_saved_fp(tsk);
+		frame.sp = thread_saved_sp(tsk);
+		frame.pc = thread_saved_pc(tsk);
+	} else {
+		register unsigned long current_sp asm("sp");
+		data.no_sched_functions = 0;
+		frame.fp = (unsigned long)__builtin_frame_address(0);
+		frame.sp = current_sp;
+		frame.pc = (unsigned long)save_stack_trace_tsk;
+	}
+
+	walk_stackframe(&frame, save_trace, &data);
+	if (trace->nr_entries < trace->max_entries)
+		trace->entries[trace->nr_entries++] = ULONG_MAX;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+	save_stack_trace_tsk(current, trace);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+#endif
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
new file mode 100644
index 0000000..8712a8e
--- /dev/null
+++ b/arch/arm64/kernel/traps.c
@@ -0,0 +1,357 @@
+/*
+ * Based on arch/arm/kernel/traps.c
+ *
+ * Copyright (C) 1995-2009 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/signal.h>
+#include <linux/personality.h>
+#include <linux/kallsyms.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/module.h>
+#include <linux/kexec.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/syscalls.h>
+
+#include <asm/atomic.h>
+#include <asm/traps.h>
+#include <asm/stacktrace.h>
+#include <asm/exception.h>
+#include <asm/system_misc.h>
+
+static const char *handler[]= {
+	"Synchronous Abort",
+	"IRQ",
+	"FIQ",
+	"Error"
+};
+
+int show_unhandled_signals = 1;
+
+/*
+ * Dump out the contents of some memory nicely...
+ */
+static void dump_mem(const char *lvl, const char *str, unsigned long bottom,
+		     unsigned long top)
+{
+	unsigned long first;
+	mm_segment_t fs;
+	int i;
+
+	/*
+	 * We need to switch to kernel mode so that we can use __get_user
+	 * to safely read from kernel space.  Note that we now dump the
+	 * code first, just in case the backtrace kills us.
+	 */
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	printk("%s%s(0x%016lx to 0x%016lx)\n", lvl, str, bottom, top);
+
+	for (first = bottom & ~31; first < top; first += 32) {
+		unsigned long p;
+		char str[sizeof(" 12345678") * 8 + 1];
+
+		memset(str, ' ', sizeof(str));
+		str[sizeof(str) - 1] = '\0';
+
+		for (p = first, i = 0; i < 8 && p < top; i++, p += 4) {
+			if (p >= bottom && p < top) {
+				unsigned int val;
+				if (__get_user(val, (unsigned int *)p) == 0)
+					sprintf(str + i * 9, " %08x", val);
+				else
+					sprintf(str + i * 9, " ????????");
+			}
+		}
+		printk("%s%04lx:%s\n", lvl, first & 0xffff, str);
+	}
+
+	set_fs(fs);
+}
+
+static void dump_backtrace_entry(unsigned long where, unsigned long stack)
+{
+	print_ip_sym(where);
+	if (in_exception_text(where))
+		dump_mem("", "Exception stack", stack,
+			 stack + sizeof(struct pt_regs));
+}
+
+static void dump_instr(const char *lvl, struct pt_regs *regs)
+{
+	unsigned long addr = instruction_pointer(regs);
+	mm_segment_t fs;
+	char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+	int i;
+
+	/*
+	 * We need to switch to kernel mode so that we can use __get_user
+	 * to safely read from kernel space.  Note that we now dump the
+	 * code first, just in case the backtrace kills us.
+	 */
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	for (i = -4; i < 1; i++) {
+		unsigned int val, bad;
+
+		bad = __get_user(val, &((u32 *)addr)[i]);
+
+		if (!bad)
+			p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
+		else {
+			p += sprintf(p, "bad PC value");
+			break;
+		}
+	}
+	printk("%sCode: %s\n", lvl, str);
+
+	set_fs(fs);
+}
+
+static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+{
+	struct stackframe frame;
+	const register unsigned long current_sp asm ("sp");
+
+	pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
+
+	if (!tsk)
+		tsk = current;
+
+	if (regs) {
+		frame.fp = regs->regs[29];
+		frame.sp = regs->sp;
+		frame.pc = regs->pc;
+	} else if (tsk == current) {
+		frame.fp = (unsigned long)__builtin_frame_address(0);
+		frame.sp = current_sp;
+		frame.pc = (unsigned long)dump_backtrace;
+	} else {
+		/*
+		 * task blocked in __switch_to
+		 */
+		frame.fp = thread_saved_fp(tsk);
+		frame.sp = thread_saved_sp(tsk);
+		frame.pc = thread_saved_pc(tsk);
+	}
+
+	printk("Call trace:\n");
+	while (1) {
+		unsigned long where = frame.pc;
+		int ret;
+
+		ret = unwind_frame(&frame);
+		if (ret < 0)
+			break;
+		dump_backtrace_entry(where, frame.sp);
+	}
+}
+
+void dump_stack(void)
+{
+	dump_backtrace(NULL, NULL);
+}
+
+EXPORT_SYMBOL(dump_stack);
+
+void show_stack(struct task_struct *tsk, unsigned long *sp)
+{
+	dump_backtrace(NULL, tsk);
+	barrier();
+}
+
+#ifdef CONFIG_PREEMPT
+#define S_PREEMPT " PREEMPT"
+#else
+#define S_PREEMPT ""
+#endif
+#ifdef CONFIG_SMP
+#define S_SMP " SMP"
+#else
+#define S_SMP ""
+#endif
+
+static int __die(const char *str, int err, struct thread_info *thread,
+		 struct pt_regs *regs)
+{
+	struct task_struct *tsk = thread->task;
+	static int die_counter;
+	int ret;
+
+	pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
+		 str, err, ++die_counter);
+
+	/* trap and error numbers are mostly meaningless on ARM */
+	ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
+	if (ret == NOTIFY_STOP)
+		return ret;
+
+	print_modules();
+	__show_regs(regs);
+	pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
+		 TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1);
+
+	if (!user_mode(regs) || in_interrupt()) {
+		dump_mem(KERN_EMERG, "Stack: ", regs->sp,
+			 THREAD_SIZE + (unsigned long)task_stack_page(tsk));
+		dump_backtrace(regs, tsk);
+		dump_instr(KERN_EMERG, regs);
+	}
+
+	return ret;
+}
+
+DEFINE_SPINLOCK(die_lock);
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+	struct thread_info *thread = current_thread_info();
+	int ret;
+
+	oops_enter();
+
+	spin_lock_irq(&die_lock);
+	console_verbose();
+	bust_spinlocks(1);
+	ret = __die(str, err, thread, regs);
+
+	if (regs && kexec_should_crash(thread->task))
+		crash_kexec(regs);
+
+	bust_spinlocks(0);
+	add_taint(TAINT_DIE);
+	spin_unlock_irq(&die_lock);
+	oops_exit();
+
+	if (in_interrupt())
+		panic("Fatal exception in interrupt");
+	if (panic_on_oops)
+		panic("Fatal exception");
+	if (ret != NOTIFY_STOP)
+		do_exit(SIGSEGV);
+}
+
+void arm64_notify_die(const char *str, struct pt_regs *regs,
+		      struct siginfo *info, int err)
+{
+	if (user_mode(regs))
+		force_sig_info(info->si_signo, info, current);
+	else
+		die(str, regs, err);
+}
+
+asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
+{
+	siginfo_t info;
+	void __user *pc = (void __user *)instruction_pointer(regs);
+
+#ifdef CONFIG_AARCH32_EMULATION
+	/* check for AArch32 breakpoint instructions */
+	if (compat_user_mode(regs) && aarch32_break_trap(regs) == 0)
+		return;
+#endif
+
+	if (show_unhandled_signals) {
+		pr_info("%s[%d]: undefined instruction: pc=%p\n",
+			current->comm, task_pid_nr(current), pc);
+		dump_instr(KERN_INFO, regs);
+	}
+
+	info.si_signo = SIGILL;
+	info.si_errno = 0;
+	info.si_code  = ILL_ILLOPC;
+	info.si_addr  = pc;
+
+	arm64_notify_die("Oops - undefined instruction", regs, &info, 0);
+}
+
+long compat_arm_syscall(struct pt_regs *regs);
+
+asmlinkage long do_ni_syscall(struct pt_regs *regs)
+{
+#ifdef CONFIG_AARCH32_EMULATION
+	long ret;
+	if (is_compat_task()) {
+		ret = compat_arm_syscall(regs);
+		if (ret != -ENOSYS)
+			return ret;
+	}
+#endif
+
+	if (show_unhandled_signals) {
+		pr_info("%s[%d]: syscall %d\n", current->comm,
+			task_pid_nr(current), (int)regs->syscallno);
+		dump_instr("", regs);
+		if (user_mode(regs))
+			__show_regs(regs);
+	}
+
+	return sys_ni_syscall();
+}
+
+/*
+ * bad_mode handles the impossible case in the exception vector.
+ */
+asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
+{
+	console_verbose();
+
+	pr_crit("Bad mode in %s handler detected, code 0x%08x\n",
+		handler[reason], esr);
+
+	die("Oops - bad mode", regs, 0);
+	local_irq_disable();
+	panic("bad mode");
+}
+
+
+void __bad_xchg(volatile void *ptr, int size)
+{
+	printk("xchg: bad data size: pc 0x%p, ptr 0x%p, size %d\n",
+		__builtin_return_address(0), ptr, size);
+	BUG();
+}
+EXPORT_SYMBOL(__bad_xchg);
+
+void __pte_error(const char *file, int line, unsigned long val)
+{
+	printk("%s:%d: bad pte %016lx.\n", file, line, val);
+}
+
+void __pmd_error(const char *file, int line, unsigned long val)
+{
+	printk("%s:%d: bad pmd %016lx.\n", file, line, val);
+}
+
+void __pgd_error(const char *file, int line, unsigned long val)
+{
+	printk("%s:%d: bad pgd %016lx.\n", file, line, val);
+}
+
+void __init trap_init(void)
+{
+	return;
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:07 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:07 +0100
Subject: [PATCH v2 06/31] arm64: MMU fault handling and page table management
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-7-git-send-email-catalin.marinas@arm.com>

This patch adds support for the handling of the MMU faults (exception
entry code introduced by a previous patch) and page table management.

The user translation table is pointed to by TTBR0 and the kernel one
(swapper_pg_dir) by TTBR1. There is no translation information shared or
address space overlapping between user and kernel page tables.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/page.h    |   67 +++++
 arch/arm64/include/asm/pgalloc.h |  113 ++++++++
 arch/arm64/mm/copypage.c         |   34 +++
 arch/arm64/mm/extable.c          |   17 ++
 arch/arm64/mm/fault.c            |  534 ++++++++++++++++++++++++++++++++++++++
 arch/arm64/mm/mm.h               |    2 +
 arch/arm64/mm/mmap.c             |  144 ++++++++++
 arch/arm64/mm/pgd.c              |   49 ++++
 8 files changed, 960 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/page.h
 create mode 100644 arch/arm64/include/asm/pgalloc.h
 create mode 100644 arch/arm64/mm/copypage.c
 create mode 100644 arch/arm64/mm/extable.c
 create mode 100644 arch/arm64/mm/fault.c
 create mode 100644 arch/arm64/mm/mm.h
 create mode 100644 arch/arm64/mm/mmap.c
 create mode 100644 arch/arm64/mm/pgd.c

diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
new file mode 100644
index 0000000..46bf666
--- /dev/null
+++ b/arch/arm64/include/asm/page.h
@@ -0,0 +1,67 @@
+/*
+ * Based on arch/arm/include/asm/page.h
+ *
+ * Copyright (C) 1995-2003 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PAGE_H
+#define __ASM_PAGE_H
+
+/* PAGE_SHIFT determines the page size */
+#ifdef CONFIG_ARM64_64K_PAGES
+#define PAGE_SHIFT		16
+#else
+#define PAGE_SHIFT		12
+#endif
+#define PAGE_SIZE		(_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE-1))
+
+/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
+#define __HAVE_ARCH_GATE_AREA		1
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ARM64_64K_PAGES
+#include <asm/pgtable-2level-types.h>
+#else
+#include <asm/pgtable-3level-types.h>
+#endif
+
+extern void __cpu_clear_user_page(void *p, unsigned long user);
+extern void __cpu_copy_user_page(void *to, const void *from,
+				 unsigned long user);
+extern void copy_page(void *to, const void *from);
+extern void clear_page(void *to);
+
+#define clear_user_page(addr,vaddr,pg)  __cpu_clear_user_page(addr, vaddr)
+#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr)
+
+typedef struct page *pgtable_t;
+
+#ifdef CONFIG_HAVE_ARCH_PFN_VALID
+extern int pfn_valid(unsigned long);
+#endif
+
+#include <asm/memory.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS \
+	(((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
+	 VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/getorder.h>
+
+#endif
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
new file mode 100644
index 0000000..f214069
--- /dev/null
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -0,0 +1,113 @@
+/*
+ * Based on arch/arm/include/asm/pgalloc.h
+ *
+ * Copyright (C) 2000-2001 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PGALLOC_H
+#define __ASM_PGALLOC_H
+
+#include <asm/pgtable-hwdef.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+#define check_pgt_cache()		do { } while (0)
+
+#ifndef CONFIG_ARM64_64K_PAGES
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+	return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+	BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
+	free_page((unsigned long)pmd);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+	set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
+}
+
+#endif	/* CONFIG_ARM64_64K_PAGES */
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
+
+#define PGALLOC_GFP	(GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
+
+static inline pte_t *
+pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
+{
+	return (pte_t *)__get_free_page(PGALLOC_GFP);
+}
+
+static inline pgtable_t
+pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+	struct page *pte;
+
+	pte = alloc_pages(PGALLOC_GFP, 0);
+	if (pte)
+		pgtable_page_ctor(pte);
+
+	return pte;
+}
+
+/*
+ * Free a PTE table.
+ */
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+	if (pte)
+		free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+	pgtable_page_dtor(pte);
+	__free_page(pte);
+}
+
+static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
+				  pmdval_t prot)
+{
+	set_pmd(pmdp, __pmd(pte | prot));
+}
+
+/*
+ * Populate the pmdp entry with a pointer to the pte.  This pmd is part
+ * of the mm address space.
+ */
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
+{
+	/*
+	 * The pmd must be loaded with the physical address of the PTE table
+	 */
+	__pmd_populate(pmdp, __pa(ptep), PMD_TYPE_TABLE);
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep)
+{
+	__pmd_populate(pmdp, page_to_phys(ptep), PMD_TYPE_TABLE);
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+#endif
diff --git a/arch/arm64/mm/copypage.c b/arch/arm64/mm/copypage.c
new file mode 100644
index 0000000..9361662
--- /dev/null
+++ b/arch/arm64/mm/copypage.c
@@ -0,0 +1,34 @@
+/*
+ * Based on arch/arm/mm/copypage.c
+ *
+ * Copyright (C) 2002 Deep Blue Solutions Ltd, All Rights Reserved.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+
+void __cpu_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
+{
+	copy_page(kto, kfrom);
+	__cpuc_flush_dcache_area(kto, PAGE_SIZE);
+}
+
+void __cpu_clear_user_page(void *kaddr, unsigned long vaddr)
+{
+	clear_page(kaddr);
+}
diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c
new file mode 100644
index 0000000..7944427
--- /dev/null
+++ b/arch/arm64/mm/extable.c
@@ -0,0 +1,17 @@
+/*
+ * Based on arch/arm/mm/extable.c
+ */
+
+#include <linux/module.h>
+#include <linux/uaccess.h>
+
+int fixup_exception(struct pt_regs *regs)
+{
+	const struct exception_table_entry *fixup;
+
+	fixup = search_exception_tables(instruction_pointer(regs));
+	if (fixup)
+		regs->pc = fixup->fixup;
+
+	return fixup != NULL;
+}
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
new file mode 100644
index 0000000..1909a69
--- /dev/null
+++ b/arch/arm64/mm/fault.c
@@ -0,0 +1,534 @@
+/*
+ * Based on arch/arm/mm/fault.c
+ *
+ * Copyright (C) 1995  Linus Torvalds
+ * Copyright (C) 1995-2004 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/mm.h>
+#include <linux/hardirq.h>
+#include <linux/init.h>
+#include <linux/kprobes.h>
+#include <linux/uaccess.h>
+#include <linux/page-flags.h>
+#include <linux/sched.h>
+#include <linux/highmem.h>
+#include <linux/perf_event.h>
+
+#include <asm/exception.h>
+#include <asm/debug-monitors.h>
+#include <asm/system_misc.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Dump out the page tables associated with 'addr' in mm 'mm'.
+ */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{
+	pgd_t *pgd;
+
+	if (!mm)
+		mm = &init_mm;
+
+	pr_alert("pgd = %p\n", mm->pgd);
+	pgd = pgd_offset(mm, addr);
+	pr_alert("[%08lx] *pgd=%016llx", addr, pgd_val(*pgd));
+
+	do {
+		pud_t *pud;
+		pmd_t *pmd;
+		pte_t *pte;
+
+		if (pgd_none_or_clear_bad(pgd))
+			break;
+
+		pud = pud_offset(pgd, addr);
+		if (pud_none_or_clear_bad(pud))
+			break;
+
+		pmd = pmd_offset(pud, addr);
+		printk(", *pmd=%016llx", pmd_val(*pmd));
+		if (pmd_none_or_clear_bad(pmd))
+			break;
+
+		pte = pte_offset_map(pmd, addr);
+		printk(", *pte=%016llx", pte_val(*pte));
+		pte_unmap(pte);
+	} while(0);
+
+	printk("\n");
+}
+
+/*
+ * The kernel tried to access some page that wasn't present.
+ */
+static void __do_kernel_fault(struct mm_struct *mm, unsigned long addr,
+			      unsigned int esr, struct pt_regs *regs)
+{
+	/*
+	 * Are we prepared to handle this kernel fault?
+	 */
+	if (fixup_exception(regs))
+		return;
+
+	/*
+	 * No handler, we'll have to terminate things with extreme prejudice.
+	 */
+	bust_spinlocks(1);
+	pr_alert("Unable to handle kernel %s at virtual address %08lx\n",
+		 (addr < PAGE_SIZE) ? "NULL pointer dereference" :
+		 "paging request", addr);
+
+	show_pte(mm, addr);
+	die("Oops", regs, esr);
+	bust_spinlocks(0);
+	do_exit(SIGKILL);
+}
+
+/*
+ * Something tried to access memory that isn't in our memory map. User mode
+ * accesses just cause a SIGSEGV
+ */
+static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
+			    unsigned int esr, unsigned int sig, int code,
+			    struct pt_regs *regs)
+{
+	struct siginfo si;
+
+	if (show_unhandled_signals) {
+		pr_info("%s[%d]: unhandled page fault (%d) at 0x%08lx, code 0x%03x\n",
+			tsk->comm, task_pid_nr(tsk), sig, addr, esr);
+		show_pte(tsk->mm, addr);
+		show_regs(regs);
+	}
+
+	tsk->thread.fault_address = addr;
+	si.si_signo = sig;
+	si.si_errno = 0;
+	si.si_code = code;
+	si.si_addr = (void __user *)addr;
+	force_sig_info(sig, &si, tsk);
+}
+
+void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
+{
+	struct task_struct *tsk = current;
+	struct mm_struct *mm = tsk->active_mm;
+
+	/*
+	 * If we are in kernel mode at this point, we have no context to
+	 * handle this fault with.
+	 */
+	if (user_mode(regs))
+		__do_user_fault(tsk, addr, esr, SIGSEGV, SEGV_MAPERR, regs);
+	else
+		__do_kernel_fault(mm, addr, esr, regs);
+}
+
+#define VM_FAULT_BADMAP		0x010000
+#define VM_FAULT_BADACCESS	0x020000
+
+#define ESR_WRITE		(1 << 6)
+#define ESR_LNX_EXEC		(1 << 24)
+
+/*
+ * Check that the permissions on the VMA allow for the fault which occurred.
+ * If we encountered a write fault, we must have write permission, otherwise
+ * we allow any permission.
+ */
+static inline bool access_error(unsigned int esr, struct vm_area_struct *vma)
+{
+	unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+
+	if (esr & ESR_WRITE)
+		mask = VM_WRITE;
+	if (esr & ESR_LNX_EXEC)
+		mask = VM_EXEC;
+
+	return vma->vm_flags & mask ? false : true;
+}
+
+static int __do_page_fault(struct mm_struct *mm, unsigned long addr,
+			   unsigned int esr, unsigned int flags,
+			   struct task_struct *tsk)
+{
+	struct vm_area_struct *vma;
+	int fault;
+
+	vma = find_vma(mm, addr);
+	fault = VM_FAULT_BADMAP;
+	if (unlikely(!vma))
+		goto out;
+	if (unlikely(vma->vm_start > addr))
+		goto check_stack;
+
+	/*
+	 * Ok, we have a good vm_area for this memory access, so we can handle
+	 * it.
+	 */
+good_area:
+	if (access_error(esr, vma)) {
+		fault = VM_FAULT_BADACCESS;
+		goto out;
+	}
+
+	return handle_mm_fault(mm, vma, addr & PAGE_MASK, flags);
+
+check_stack:
+	if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr))
+		goto good_area;
+out:
+	return fault;
+}
+
+static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
+				   struct pt_regs *regs)
+{
+	struct task_struct *tsk;
+	struct mm_struct *mm;
+	int fault, sig, code;
+	int write = esr & ESR_WRITE;
+	unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
+		(write ? FAULT_FLAG_WRITE : 0);
+
+	tsk = current;
+	mm  = tsk->mm;
+
+	/* Enable interrupts if they were enabled in the parent context. */
+	if (interrupts_enabled(regs))
+		local_irq_enable();
+
+	/*
+	 * If we're in an interrupt or have no user context, we must not take
+	 * the fault.
+	 */
+	if (in_atomic() || !mm)
+		goto no_context;
+
+	/*
+	 * As per x86, we may deadlock here. However, since the kernel only
+	 * validly references user space from well defined areas of the code,
+	 * we can bug out early if this is from code which shouldn't.
+	 */
+	if (!down_read_trylock(&mm->mmap_sem)) {
+		if (!user_mode(regs) && !search_exception_tables(regs->pc))
+			goto no_context;
+retry:
+		down_read(&mm->mmap_sem);
+	} else {
+		/*
+		 * The above down_read_trylock() might have succeeded in which
+		 * case, we'll have missed the might_sleep() from down_read().
+		 */
+		might_sleep();
+#ifdef CONFIG_DEBUG_VM
+		if (!user_mode(regs) && !search_exception_tables(regs->pc))
+			goto no_context;
+#endif
+	}
+
+	fault = __do_page_fault(mm, addr, esr, flags, tsk);
+
+	/*
+	 * If we need to retry but a fatal signal is pending, handle the
+	 * signal first. We do not need to release the mmap_sem because it
+	 * would already be released in __lock_page_or_retry in mm/filemap.c.
+	 */
+	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+		return 0;
+
+	/*
+	 * Major/minor page fault accounting is only done on the initial
+	 * attempt. If we go through a retry, it is extremely likely that the
+	 * page will be found in page cache at that point.
+	 */
+
+	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
+	if (flags & FAULT_FLAG_ALLOW_RETRY) {
+		if (fault & VM_FAULT_MAJOR) {
+			tsk->maj_flt++;
+			perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs,
+				      addr);
+		} else {
+			tsk->min_flt++;
+			perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs,
+				      addr);
+		}
+		if (fault & VM_FAULT_RETRY) {
+			/*
+			 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of
+			 * starvation.
+			 */
+			flags &= ~FAULT_FLAG_ALLOW_RETRY;
+			goto retry;
+		}
+	}
+
+	up_read(&mm->mmap_sem);
+
+	/*
+	 * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
+	 */
+	if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP |
+			      VM_FAULT_BADACCESS))))
+		return 0;
+
+	if (fault & VM_FAULT_OOM) {
+		/*
+		 * We ran out of memory, call the OOM killer, and return to
+		 * userspace (which will retry the fault, or kill us if we got
+		 * oom-killed).
+		 */
+		pagefault_out_of_memory();
+		return 0;
+	}
+
+	/*
+	 * If we are in kernel mode at this point, we have no context to
+	 * handle this fault with.
+	 */
+	if (!user_mode(regs))
+		goto no_context;
+
+	if (fault & VM_FAULT_SIGBUS) {
+		/*
+		 * We had some memory, but were unable to successfully fix up
+		 * this page fault.
+		 */
+		sig = SIGBUS;
+		code = BUS_ADRERR;
+	} else {
+		/*
+		 * Something tried to access memory that isn't in our memory
+		 * map.
+		 */
+		sig = SIGSEGV;
+		code = fault == VM_FAULT_BADACCESS ?
+			SEGV_ACCERR : SEGV_MAPERR;
+	}
+
+	__do_user_fault(tsk, addr, esr, sig, code, regs);
+	return 0;
+
+no_context:
+	__do_kernel_fault(mm, addr, esr, regs);
+	return 0;
+}
+
+/*
+ * First Level Translation Fault Handler
+ *
+ * We enter here because the first level page table doesn't contain a valid
+ * entry for the address.
+ *
+ * If the address is in kernel space (>= TASK_SIZE), then we are probably
+ * faulting in the vmalloc() area.
+ *
+ * If the init_task's first level page tables contains the relevant entry, we
+ * copy the it to this task.  If not, we send the process a signal, fixup the
+ * exception, or oops the kernel.
+ *
+ * NOTE! We MUST NOT take any locks for this case. We may be in an interrupt
+ * or a critical region, and should only copy the information from the master
+ * page table, nothing more.
+ */
+static int __kprobes do_translation_fault(unsigned long addr,
+					  unsigned int esr,
+					  struct pt_regs *regs)
+{
+	if (addr < TASK_SIZE)
+		return do_page_fault(addr, esr, regs);
+
+	do_bad_area(addr, esr, regs);
+	return 0;
+}
+
+/*
+ * Some section permission faults need to be handled gracefully.  They can
+ * happen due to a __{get,put}_user during an oops.
+ */
+static int do_sect_fault(unsigned long addr, unsigned int esr,
+			 struct pt_regs *regs)
+{
+	do_bad_area(addr, esr, regs);
+	return 0;
+}
+
+/*
+ * This abort handler always returns "fault".
+ */
+static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
+{
+	return 1;
+}
+
+static struct fault_info {
+	int	(*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs);
+	int	sig;
+	int	code;
+	const char *name;
+} fault_info[] = {
+	{ do_bad,		SIGBUS,  0,		"ttbr address size fault"	},
+	{ do_bad,		SIGBUS,  0,		"level 1 address size fault"	},
+	{ do_bad,		SIGBUS,  0,		"level 2 address size fault"	},
+	{ do_bad,		SIGBUS,  0,		"level 3 address size fault"	},
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"input address range fault"	},
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 1 translation fault"	},
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"level 2 translation fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"level 3 translation fault"	},
+	{ do_bad,		SIGBUS,  0,		"reserved access flag fault"	},
+	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 access flag fault"	},
+	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 2 access flag fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 access flag fault"	},
+	{ do_bad,		SIGBUS,  0,		"reserved permission fault"	},
+	{ do_bad,		SIGSEGV, SEGV_ACCERR,	"level 1 permission fault"	},
+	{ do_sect_fault,	SIGSEGV, SEGV_ACCERR,	"level 2 permission fault"	},
+	{ do_page_fault,	SIGSEGV, SEGV_ACCERR,	"level 3 permission fault"	},
+	{ do_bad,		SIGBUS,  0,		"synchronous external abort"	},
+	{ do_bad,		SIGBUS,  0,		"asynchronous external abort"	},
+	{ do_bad,		SIGBUS,  0,		"unknown 18"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 19"			},
+	{ do_bad,		SIGBUS,  0,		"synchronous abort (translation table walk)" },
+	{ do_bad,		SIGBUS,  0,		"synchronous abort (translation table walk)" },
+	{ do_bad,		SIGBUS,  0,		"synchronous abort (translation table walk)" },
+	{ do_bad,		SIGBUS,  0,		"synchronous abort (translation table walk)" },
+	{ do_bad,		SIGBUS,  0,		"synchronous parity error"	},
+	{ do_bad,		SIGBUS,  0,		"asynchronous parity error"	},
+	{ do_bad,		SIGBUS,  0,		"unknown 26"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 27"			},
+	{ do_bad,		SIGBUS,  0,		"synchronous parity error (translation table walk" },
+	{ do_bad,		SIGBUS,  0,		"synchronous parity error (translation table walk" },
+	{ do_bad,		SIGBUS,  0,		"synchronous parity error (translation table walk" },
+	{ do_bad,		SIGBUS,  0,		"synchronous parity error (translation table walk" },
+	{ do_bad,		SIGBUS,  0,		"unknown 32"			},
+	{ do_bad,		SIGBUS,  BUS_ADRALN,	"alignment fault"		},
+	{ do_bad,		SIGBUS,  0,		"debug event"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 35"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 36"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 37"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 38"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 39"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 40"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 41"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 42"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 43"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 44"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 45"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 46"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 47"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 48"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 49"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 50"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 51"			},
+	{ do_bad,		SIGBUS,  0,		"implementation fault (lockdown abort)" },
+	{ do_bad,		SIGBUS,  0,		"unknown 53"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 54"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 55"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 56"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 57"			},
+	{ do_bad,		SIGBUS,  0,		"implementation fault (coprocessor abort)" },
+	{ do_bad,		SIGBUS,  0,		"unknown 59"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 60"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 61"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 62"			},
+	{ do_bad,		SIGBUS,  0,		"unknown 63"			},
+};
+
+/*
+ * Dispatch a data abort to the relevant handler.
+ */
+asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr,
+					 struct pt_regs *regs)
+{
+	const struct fault_info *inf = fault_info + (esr & 63);
+	struct siginfo info;
+
+	if (!inf->fn(addr, esr, regs))
+		return;
+
+	pr_alert("Unhandled fault: %s (0x%08x) at 0x%016lx\n",
+		 inf->name, esr, addr);
+
+	info.si_signo = inf->sig;
+	info.si_errno = 0;
+	info.si_code  = inf->code;
+	info.si_addr  = (void __user *)addr;
+	arm64_notify_die("", regs, &info, esr);
+}
+
+/*
+ * Handle stack alignment exceptions.
+ */
+asmlinkage void __exception do_sp_pc_abort(unsigned long addr,
+					   unsigned int esr,
+					   struct pt_regs *regs)
+{
+	struct siginfo info;
+
+	info.si_signo = SIGBUS;
+	info.si_errno = 0;
+	info.si_code  = BUS_ADRALN;
+	info.si_addr  = (void __user *)addr;
+	arm64_notify_die("", regs, &info, esr);
+}
+
+static struct fault_info debug_fault_info[] = {
+	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware breakpoint"	},
+	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware single-step"	},
+	{ do_bad,	SIGTRAP,	TRAP_HWBKPT,	"hardware watchpoint"	},
+	{ do_bad,	SIGBUS,		0,		"unknown 3"		},
+	{ do_bad,	SIGTRAP,	TRAP_BRKPT,	"aarch32 BKPT"		},
+	{ do_bad,	SIGTRAP,	0,		"aarch32 vector catch"	},
+	{ do_bad,	SIGTRAP,	TRAP_BRKPT,	"aarch64 BRK"		},
+	{ do_bad,	SIGBUS,		0,		"unknown 7"		},
+};
+
+void __init hook_debug_fault_code(int nr,
+				  int (*fn)(unsigned long, unsigned int, struct pt_regs *),
+				  int sig, int code, const char *name)
+{
+	BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info));
+
+	debug_fault_info[nr].fn		= fn;
+	debug_fault_info[nr].sig	= sig;
+	debug_fault_info[nr].code	= code;
+	debug_fault_info[nr].name	= name;
+}
+
+asmlinkage int __exception do_debug_exception(unsigned long addr,
+					      unsigned int esr,
+					      struct pt_regs *regs)
+{
+	const struct fault_info *inf = debug_fault_info + DBG_ESR_EVT(esr);
+	struct siginfo info;
+
+	if (!inf->fn(addr, esr, regs))
+		return 1;
+
+	pr_alert("Unhandled debug exception: %s (0x%08x) at 0x%016lx\n",
+		 inf->name, esr, addr);
+
+	info.si_signo = inf->sig;
+	info.si_errno = 0;
+	info.si_code  = inf->code;
+	info.si_addr  = (void __user *)addr;
+	arm64_notify_die("", regs, &info, esr);
+
+	return 0;
+}
diff --git a/arch/arm64/mm/mm.h b/arch/arm64/mm/mm.h
new file mode 100644
index 0000000..c84f68b
--- /dev/null
+++ b/arch/arm64/mm/mm.h
@@ -0,0 +1,2 @@
+extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
+extern void __init bootmem_init(void);
diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c
new file mode 100644
index 0000000..7c7be78
--- /dev/null
+++ b/arch/arm64/mm/mmap.c
@@ -0,0 +1,144 @@
+/*
+ * Based on arch/arm/mm/mmap.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/elf.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/export.h>
+#include <linux/shm.h>
+#include <linux/sched.h>
+#include <linux/io.h>
+#include <linux/personality.h>
+#include <linux/random.h>
+
+#include <asm/cputype.h>
+
+/*
+ * Leave enough space between the mmap area and the stack to honour ulimit in
+ * the face of randomisation.
+ */
+#define MIN_GAP (SZ_128M + ((STACK_RND_MASK << PAGE_SHIFT) + 1))
+#define MAX_GAP	(STACK_TOP/6*5)
+
+static int mmap_is_legacy(void)
+{
+	if (current->personality & ADDR_COMPAT_LAYOUT)
+		return 1;
+
+	if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
+		return 1;
+
+	return sysctl_legacy_va_layout;
+}
+
+/*
+ * Since get_random_int() returns the same value within a 1 jiffy window, we
+ * will almost always get the same randomisation for the stack and mmap
+ * region. This will mean the relative distance between stack and mmap will be
+ * the same.
+ *
+ * To avoid this we can shift the randomness by 1 bit.
+ */
+static unsigned long mmap_rnd(void)
+{
+	unsigned long rnd = 0;
+
+	if (current->flags & PF_RANDOMIZE)
+		rnd = (long)get_random_int() & (STACK_RND_MASK >> 1);
+
+	return rnd << (PAGE_SHIFT + 1);
+}
+
+static unsigned long mmap_base(void)
+{
+	unsigned long gap = rlimit(RLIMIT_STACK);
+
+	if (gap < MIN_GAP)
+		gap = MIN_GAP;
+	else if (gap > MAX_GAP)
+		gap = MAX_GAP;
+
+	return PAGE_ALIGN(STACK_TOP - gap - mmap_rnd());
+}
+
+/*
+ * This function, called very early during the creation of a new process VM
+ * image, sets up which VM layout function to use:
+ */
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+	/*
+	 * Fall back to the standard layout if the personality bit is set, or
+	 * if the expected stack growth is unlimited:
+	 */
+	if (mmap_is_legacy()) {
+		mm->mmap_base = TASK_UNMAPPED_BASE;
+		mm->get_unmapped_area = arch_get_unmapped_area;
+		mm->unmap_area = arch_unmap_area;
+	} else {
+		mm->mmap_base = mmap_base();
+		mm->get_unmapped_area = arch_get_unmapped_area_topdown;
+		mm->unmap_area = arch_unmap_area_topdown;
+	}
+}
+EXPORT_SYMBOL_GPL(arch_pick_mmap_layout);
+
+
+/*
+ * You really shouldn't be using read() or write() on /dev/mem.  This might go
+ * away in the future.
+ */
+int valid_phys_addr_range(unsigned long addr, size_t size)
+{
+	if (addr < PHYS_OFFSET)
+		return 0;
+	if (addr + size > __pa(high_memory - 1) + 1)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Do not allow /dev/mem mappings beyond the supported physical range.
+ */
+int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
+{
+	return !(((pfn << PAGE_SHIFT) + size) & ~PHYS_MASK);
+}
+
+#ifdef CONFIG_STRICT_DEVMEM
+
+#include <linux/ioport.h>
+
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain address
+ * is valid. The argument is a physical page number.  We mimic x86 here by
+ * disallowing access to system RAM as well as device-exclusive MMIO regions.
+ * This effectively disable read()/write() on /dev/mem.
+ */
+int devmem_is_allowed(unsigned long pfn)
+{
+	if (iomem_is_exclusive(pfn << PAGE_SHIFT))
+		return 0;
+	if (!page_is_ram(pfn))
+		return 1;
+	return 0;
+}
+
+#endif
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
new file mode 100644
index 0000000..7a7b0e9
--- /dev/null
+++ b/arch/arm64/mm/pgd.c
@@ -0,0 +1,49 @@
+/*
+ * PGD allocation/freeing
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/gfp.h>
+#include <linux/highmem.h>
+#include <linux/slab.h>
+
+#include <asm/pgalloc.h>
+#include <asm/page.h>
+#include <asm/tlbflush.h>
+
+#include "mm.h"
+
+#define PGD_ORDER	0
+
+pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+	pgd_t *new_pgd;
+
+	new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, PGD_ORDER);
+	if (!new_pgd)
+		return NULL;
+
+	memset(new_pgd, 0, PAGE_SIZE << PGD_ORDER);
+
+	return new_pgd;
+}
+
+void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+	free_pages((unsigned long)pgd, PGD_ORDER);
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:08 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:08 +0100
Subject: [PATCH v2 07/31] arm64: Process management
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>

The patch adds support for thread creation and context switching. The
context switching CPU specific code is introduced with the CPU support
patch (part of the arch/arm64/mm/proc.S file). AArch64 supports
ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable
via the ID_AA64AFR0_EL1 register).

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/mmu_context.h |  152 +++++++++++++
 arch/arm64/include/asm/thread_info.h |  124 ++++++++++
 arch/arm64/kernel/process.c          |  416 ++++++++++++++++++++++++++++++++++
 arch/arm64/mm/context.c              |  159 +++++++++++++
 4 files changed, 851 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/mmu_context.h
 create mode 100644 arch/arm64/include/asm/thread_info.h
 create mode 100644 arch/arm64/kernel/process.c
 create mode 100644 arch/arm64/mm/context.c

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
new file mode 100644
index 0000000..f68465d
--- /dev/null
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -0,0 +1,152 @@
+/*
+ * Based on arch/arm/include/asm/mmu_context.h
+ *
+ * Copyright (C) 1996 Russell King.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_MMU_CONTEXT_H
+#define __ASM_MMU_CONTEXT_H
+
+#include <linux/compiler.h>
+#include <linux/sched.h>
+
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm-generic/mm_hooks.h>
+#include <asm/cputype.h>
+#include <asm/pgtable.h>
+
+#define MAX_ASID_BITS	16
+
+extern unsigned int cpu_last_asid;
+
+void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+void __new_context(struct mm_struct *mm);
+
+/*
+ * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
+ */
+static inline void cpu_set_reserved_ttbr0(void)
+{
+	unsigned long ttbr = page_to_phys(empty_zero_page);
+
+	asm(
+	"	msr	ttbr0_el1, %0			// set TTBR0\n"
+	"	isb"
+	:
+	: "r" (ttbr));
+}
+
+static inline void switch_new_context(struct mm_struct *mm)
+{
+	unsigned long flags;
+
+	__new_context(mm);
+
+	local_irq_save(flags);
+	cpu_switch_mm(mm->pgd, mm);
+	local_irq_restore(flags);
+}
+
+static inline void check_and_switch_context(struct mm_struct *mm,
+					    struct task_struct *tsk)
+{
+	/*
+	 * Required during context switch to avoid speculative page table
+	 * walking with the wrong TTBR.
+	 */
+	cpu_set_reserved_ttbr0();
+
+	if (!((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS))
+		/*
+		 * The ASID is from the current generation, just switch to the
+		 * new pgd. This condition is only true for calls from
+		 * context_switch() and interrupts are already disabled.
+		 */
+		cpu_switch_mm(mm->pgd, mm);
+	else if (irqs_disabled())
+		/*
+		 * Defer the new ASID allocation until after the context
+		 * switch critical region since __new_context() cannot be
+		 * called with interrupts disabled.
+		 */
+		set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+	else
+		/*
+		 * That is a direct call to switch_mm() or activate_mm() with
+		 * interrupts enabled and a new context.
+		 */
+		switch_new_context(mm);
+}
+
+#define init_new_context(tsk,mm)	(__init_new_context(tsk,mm),0)
+#define destroy_context(mm)		do { } while(0)
+
+#define finish_arch_post_lock_switch \
+	finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
+{
+	if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
+		struct mm_struct *mm = current->mm;
+		unsigned long flags;
+
+		__new_context(mm);
+
+		local_irq_save(flags);
+		cpu_switch_mm(mm->pgd, mm);
+		local_irq_restore(flags);
+	}
+}
+
+/*
+ * This is called when "tsk" is about to enter lazy TLB mode.
+ *
+ * mm:  describes the currently active mm context
+ * tsk: task which is entering lazy tlb
+ * cpu: cpu number which is entering lazy tlb
+ *
+ * tsk->mm will be NULL
+ */
+static inline void
+enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ * This is the actual mm switch as far as the scheduler
+ * is concerned.  No registers are touched.  We avoid
+ * calling the CPU specific function when the mm hasn't
+ * actually changed.
+ */
+static inline void
+switch_mm(struct mm_struct *prev, struct mm_struct *next,
+	  struct task_struct *tsk)
+{
+	unsigned int cpu = smp_processor_id();
+
+#ifdef CONFIG_SMP
+	/* check for possible thread migration */
+	if (!cpumask_empty(mm_cpumask(next)) &&
+	    !cpumask_test_cpu(cpu, mm_cpumask(next)))
+		__flush_icache_all();
+#endif
+	if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
+		check_and_switch_context(next, tsk);
+}
+
+#define deactivate_mm(tsk,mm)	do { } while (0)
+#define activate_mm(prev,next)	switch_mm(prev, next, NULL)
+
+#endif
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
new file mode 100644
index 0000000..4f909a3
--- /dev/null
+++ b/arch/arm64/include/asm/thread_info.h
@@ -0,0 +1,124 @@
+/*
+ * Based on arch/arm/include/asm/thread_info.h
+ *
+ * Copyright (C) 2002 Russell King.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_THREAD_INFO_H
+#define __ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+
+#define THREAD_SIZE_ORDER	1
+#define THREAD_SIZE		8192
+#define THREAD_START_SP		(THREAD_SIZE - 16)
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+struct exec_domain;
+
+#include <asm/types.h>
+
+typedef unsigned long mm_segment_t;
+
+/*
+ * low level task data that entry.S needs immediate access to.
+ * __switch_to() assumes cpu_context follows immediately after cpu_domain.
+ */
+struct thread_info {
+	unsigned long		flags;		/* low level flags */
+	mm_segment_t		addr_limit;	/* address limit */
+	struct task_struct	*task;		/* main task structure */
+	struct exec_domain	*exec_domain;	/* execution domain */
+	struct restart_block	restart_block;
+	int			preempt_count;	/* 0 => preemptable, <0 => bug */
+	int			cpu;		/* cpu */
+};
+
+#define INIT_THREAD_INFO(tsk)						\
+{									\
+	.task		= &tsk,						\
+	.exec_domain	= &default_exec_domain,				\
+	.flags		= 0,						\
+	.preempt_count	= INIT_PREEMPT_COUNT,				\
+	.addr_limit	= KERNEL_DS,					\
+	.restart_block	= {						\
+		.fn	= do_no_restart_syscall,			\
+	},								\
+}
+
+#define init_thread_info	(init_thread_union.thread_info)
+#define init_stack		(init_thread_union.stack)
+
+/*
+ * how to get the thread information struct from C
+ */
+static inline struct thread_info *current_thread_info(void) __attribute_const__;
+
+static inline struct thread_info *current_thread_info(void)
+{
+	register unsigned long sp asm ("sp");
+	return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
+}
+
+#define thread_saved_pc(tsk)	\
+	((unsigned long)(tsk->thread.cpu_context.pc))
+#define thread_saved_sp(tsk)	\
+	((unsigned long)(tsk->thread.cpu_context.sp))
+#define thread_saved_fp(tsk)	\
+	((unsigned long)(tsk->thread.cpu_context.fp))
+
+#endif
+
+/*
+ * We use bit 30 of the preempt_count to indicate that kernel
+ * preemption is occurring.  See <asm/hardirq.h>.
+ */
+#define PREEMPT_ACTIVE	0x40000000
+
+/*
+ * thread information flags:
+ *  TIF_SYSCALL_TRACE	- syscall trace active
+ *  TIF_SIGPENDING	- signal pending
+ *  TIF_NEED_RESCHED	- rescheduling necessary
+ *  TIF_NOTIFY_RESUME	- callback before returning to user
+ *  TIF_USEDFPU		- FPU was used by this task this quantum (SMP)
+ *  TIF_POLLING_NRFLAG	- true if poll_idle() is polling TIF_NEED_RESCHED
+ */
+#define TIF_SIGPENDING		0
+#define TIF_NEED_RESCHED	1
+#define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
+#define TIF_SYSCALL_TRACE	8
+#define TIF_POLLING_NRFLAG	16
+#define TIF_MEMDIE		18	/* is terminating due to OOM killer */
+#define TIF_FREEZE		19
+#define TIF_RESTORE_SIGMASK	20
+#define TIF_SINGLESTEP		21
+#define TIF_32BIT		22	/* 32bit process */
+#define TIF_SWITCH_MM		23	/* deferred switch_mm */
+
+#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+#define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
+#define _TIF_32BIT		(1 << TIF_32BIT)
+
+#define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
+				 _TIF_NOTIFY_RESUME)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_THREAD_INFO_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
new file mode 100644
index 0000000..c4a4e1c
--- /dev/null
+++ b/arch/arm64/kernel/process.c
@@ -0,0 +1,416 @@
+/*
+ * Based on arch/arm/kernel/process.c
+ *
+ * Original Copyright (C) 1995  Linus Torvalds
+ * Copyright (C) 1996-2000 Russell King - Converted to ARM.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdarg.h>
+
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/user.h>
+#include <linux/delay.h>
+#include <linux/reboot.h>
+#include <linux/interrupt.h>
+#include <linux/kallsyms.h>
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/elfcore.h>
+#include <linux/pm.h>
+#include <linux/tick.h>
+#include <linux/utsname.h>
+#include <linux/uaccess.h>
+#include <linux/random.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/personality.h>
+#include <linux/notifier.h>
+
+#include <asm/cacheflush.h>
+#include <asm/processor.h>
+#include <asm/stacktrace.h>
+#include <asm/fpsimd.h>
+
+extern void setup_mm_for_reboot(void);
+
+static void setup_restart(void)
+{
+	/*
+	 * Tell the mm system that we are going to reboot -
+	 * we may need it to insert some 1:1 mappings so that
+	 * soft boot works.
+	 */
+	setup_mm_for_reboot();
+
+	/* Clean and invalidate caches */
+	flush_cache_all();
+
+	/* Turn off caching */
+	cpu_proc_fin();
+
+	/* Push out any further dirty data, and ensure cache is empty */
+	flush_cache_all();
+}
+
+void soft_restart(unsigned long addr)
+{
+	setup_restart();
+	cpu_reset(addr);
+}
+
+/*
+ * Function pointers to optional machine specific functions
+ */
+void (*pm_power_off)(void);
+EXPORT_SYMBOL(pm_power_off);
+
+void (*pm_restart)(const char *cmd);
+EXPORT_SYMBOL_GPL(pm_restart);
+
+
+/*
+ * This is our default idle handler.
+ */
+static void default_idle(void)
+{
+	/*
+	 * This should do all the clock switching and wait for interrupt
+	 * tricks
+	 */
+	cpu_do_idle();
+	local_irq_enable();
+}
+
+void (*pm_idle)(void) = default_idle;
+EXPORT_SYMBOL(pm_idle);
+
+/*
+ * The idle thread, has rather strange semantics for calling pm_idle,
+ * but this is what x86 does and we need to do the same, so that
+ * things like cpuidle get called in the same way.  The only difference
+ * is that we always respect 'hlt_counter' to prevent low power idle.
+ */
+void cpu_idle(void)
+{
+	local_fiq_enable();
+
+	/* endless idle loop with no priority at all */
+	while (1) {
+		tick_nohz_idle_enter();
+		rcu_idle_enter();
+		while (!need_resched()) {
+			/*
+			 * We need to disable interrupts here to ensure
+			 * we don't miss a wakeup call.
+			 */
+			local_irq_disable();
+			if (!need_resched()) {
+				stop_critical_timings();
+				pm_idle();
+				start_critical_timings();
+				/*
+				 * pm_idle functions should always return
+				 * with IRQs enabled.
+				 */
+				WARN_ON(irqs_disabled());
+			} else {
+				local_irq_enable();
+			}
+		}
+		rcu_idle_exit();
+		tick_nohz_idle_exit();
+		preempt_enable_no_resched();
+		schedule();
+		preempt_disable();
+	}
+}
+
+void machine_shutdown(void)
+{
+#ifdef CONFIG_SMP
+	smp_send_stop();
+#endif
+}
+
+void machine_halt(void)
+{
+	machine_shutdown();
+	while (1);
+}
+
+void machine_power_off(void)
+{
+	machine_shutdown();
+	if (pm_power_off)
+		pm_power_off();
+}
+
+void machine_restart(char *cmd)
+{
+	machine_shutdown();
+
+	/* Disable interrupts first */
+	local_irq_disable();
+	local_fiq_disable();
+
+	/* Now call the architecture specific reboot code. */
+	if (pm_restart)
+		pm_restart(cmd);
+
+	/*
+	 * Whoops - the architecture was unable to reboot.
+	 * Tell the user!
+	 */
+	mdelay(1000);
+	printk("Reboot failed -- System halted\n");
+	while (1);
+}
+
+void __show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printk("CPU: %d    %s  (%s %.*s)\n",
+		raw_smp_processor_id(), print_tainted(),
+		init_utsname()->release,
+		(int)strcspn(init_utsname()->version, " "),
+		init_utsname()->version);
+	print_symbol("PC is at %s\n", instruction_pointer(regs));
+	print_symbol("LR is at %s\n", regs->regs[30]);
+	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
+	       regs->pc, regs->regs[30], regs->pstate);
+	printk("sp : %016llx\n", regs->sp);
+	for (i = 29; i >= 0; i--) {
+		printk("x%-2d: %016llx ", i, regs->regs[i]);
+		if (i % 2 == 0)
+			printk("\n");
+	}
+	printk("\n");
+}
+
+void show_regs(struct pt_regs * regs)
+{
+	printk("\n");
+	printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm);
+	__show_regs(regs);
+}
+
+/*
+ * Free current thread data structures etc..
+ */
+void exit_thread(void)
+{
+}
+
+void flush_thread(void)
+{
+	fpsimd_flush_thread();
+	flush_ptrace_hw_breakpoint(current);
+}
+
+void release_thread(struct task_struct *dead_task)
+{
+}
+
+int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
+{
+	fpsimd_save_state(&current->thread.fpsimd_state);
+	*dst = *src;
+	return 0;
+}
+
+asmlinkage void ret_from_fork(void) asm("ret_from_fork");
+
+int copy_thread(unsigned long clone_flags, unsigned long stack_start,
+		unsigned long stk_sz, struct task_struct *p,
+		struct pt_regs *regs)
+{
+	struct pt_regs *childregs = task_pt_regs(p);
+	unsigned long tls = p->thread.tp_value;
+
+	*childregs = *regs;
+	childregs->regs[0] = 0;
+
+#ifdef CONFIG_AARCH32_EMULATION
+	if (test_ti_thread_flag(task_thread_info(p), TIF_32BIT))
+		childregs->compat_sp = stack_start;
+	else
+#endif
+	{
+		/*
+		 * Read the current TLS pointer from tpidr_el0 as it may be
+		 * out-of-sync with the saved value.
+		 */
+		asm("mrs %0, tpidr_el0" : "=r" (tls));
+		childregs->sp = stack_start;
+	}
+
+	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
+	p->thread.cpu_context.sp = (unsigned long)childregs;
+	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
+
+	/* If a TLS pointer was passed to clone, use that for the new thread. */
+	if (clone_flags & CLONE_SETTLS)
+		tls = regs->regs[3];
+	p->thread.tp_value = tls;
+
+	ptrace_hw_copy_thread(p);
+
+	return 0;
+}
+
+static void tls_thread_switch(struct task_struct *next)
+{
+	unsigned long tpidr, tpidrro;
+
+	if (!test_thread_flag(TIF_32BIT)) {
+		asm("mrs %0, tpidr_el0" : "=r" (tpidr));
+		current->thread.tp_value = tpidr;
+	}
+
+	if (test_ti_thread_flag(task_thread_info(next), TIF_32BIT)) {
+		tpidr = 0;
+		tpidrro = next->thread.tp_value;
+	} else {
+		tpidr = next->thread.tp_value;
+		tpidrro = 0;
+	}
+
+	asm(
+	"	msr	tpidr_el0, %0\n"
+	"	msr	tpidrro_el0, %1"
+	: : "r" (tpidr), "r" (tpidrro));
+}
+
+/*
+ * Thread switching.
+ */
+struct task_struct *__switch_to(struct task_struct *prev,
+				struct task_struct *next)
+{
+	struct task_struct *last;
+
+	fpsimd_thread_switch(next);
+	tls_thread_switch(next);
+	hw_breakpoint_thread_switch(next);
+
+	/* the actual thread switch */
+	last = cpu_switch_to(prev, next);
+
+	return last;
+}
+
+/*
+ * Fill in the task's elfregs structure for a core dump.
+ */
+int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
+{
+	elf_core_copy_regs(elfregs, task_pt_regs(t));
+	return 1;
+}
+
+/*
+ * fill in the fpe structure for a core dump...
+ */
+int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
+{
+	return 0;
+}
+EXPORT_SYMBOL(dump_fpu);
+
+/*
+ * Shuffle the argument into the correct register before calling the
+ * thread function.  x1 is the thread argument, x2 is the pointer to
+ * the thread function, and x3 points to the exit function.
+ */
+extern void kernel_thread_helper(void);
+asm(	".section .text\n"
+"	.align\n"
+"	.type	kernel_thread_helper, #function\n"
+"kernel_thread_helper:\n"
+"	mov	x0, x1\n"
+"	mov	x30, x3\n"
+"	br	x2\n"
+"	.size	kernel_thread_helper, . - kernel_thread_helper\n"
+"	.previous");
+
+#define kernel_thread_exit	do_exit
+
+/*
+ * Create a kernel thread.
+ */
+pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
+{
+	struct pt_regs regs;
+
+	memset(&regs, 0, sizeof(regs));
+
+	regs.regs[1] = (unsigned long)arg;
+	regs.regs[2] = (unsigned long)fn;
+	regs.regs[3] = (unsigned long)kernel_thread_exit;
+	regs.pc = (unsigned long)kernel_thread_helper;
+	regs.pstate = PSR_MODE_EL1h;
+
+	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
+}
+EXPORT_SYMBOL(kernel_thread);
+
+unsigned long get_wchan(struct task_struct *p)
+{
+	struct stackframe frame;
+	int count = 0;
+	if (!p || p == current || p->state == TASK_RUNNING)
+		return 0;
+
+	frame.fp = thread_saved_fp(p);
+	frame.sp = thread_saved_sp(p);
+	frame.pc = thread_saved_pc(p);
+	do {
+		int ret = unwind_frame(&frame);
+		if (ret < 0)
+			return 0;
+		if (!in_sched_functions(frame.pc))
+			return frame.pc;
+	} while (count ++ < 16);
+	return 0;
+}
+
+unsigned long arch_align_stack(unsigned long sp)
+{
+	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
+		sp -= get_random_int() & ~PAGE_MASK;
+	return sp & ~0xf;
+}
+
+static unsigned long randomize_base(unsigned long base)
+{
+	unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
+	return randomize_range(base, range_end, 0) ? : base;
+}
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+	return randomize_base(mm->brk);
+}
+
+unsigned long randomize_et_dyn(unsigned long base)
+{
+	return randomize_base(base);
+}
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
new file mode 100644
index 0000000..e06f47a
--- /dev/null
+++ b/arch/arm64/mm/context.c
@@ -0,0 +1,159 @@
+/*
+ * Based on arch/arm/mm/context.c
+ *
+ * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
+
+#include <asm/mmu_context.h>
+#include <asm/tlbflush.h>
+#include <asm/cachetype.h>
+
+#define asid_bits(reg) \
+	(((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
+
+#define ASID_FIRST_VERSION	(1 << MAX_ASID_BITS)
+
+static DEFINE_SPINLOCK(cpu_asid_lock);
+unsigned int cpu_last_asid = ASID_FIRST_VERSION;
+
+/*
+ * We fork()ed a process, and we need a new context for the child to run in.
+ */
+void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+	mm->context.id = 0;
+	spin_lock_init(&mm->context.id_lock);
+}
+
+static void flush_context(void)
+{
+	/* set the reserved TTBR0 before flushing the TLB */
+	cpu_set_reserved_ttbr0();
+	flush_tlb_all();
+	if (icache_is_aivivt())
+		__flush_icache_all();
+}
+
+#ifdef CONFIG_SMP
+
+static void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+	unsigned long flags;
+
+	/*
+	 * Locking needed for multi-threaded applications where the same
+	 * mm->context.id could be set from different CPUs during the
+	 * broadcast. This function is also called via IPI so the
+	 * mm->context.id_lock has to be IRQ-safe.
+	 */
+	spin_lock_irqsave(&mm->context.id_lock, flags);
+	if (likely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
+		/*
+		 * Old version of ASID found. Set the new one and reset
+		 * mm_cpumask(mm).
+		 */
+		mm->context.id = asid;
+		cpumask_clear(mm_cpumask(mm));
+	}
+	spin_unlock_irqrestore(&mm->context.id_lock, flags);
+
+	/*
+	 * Set the mm_cpumask(mm) bit for the current CPU.
+	 */
+	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+}
+
+/*
+ * Reset the ASID on the current CPU. This function call is broadcast from the
+ * CPU handling the ASID rollover and holding cpu_asid_lock.
+ */
+static void reset_context(void *info)
+{
+	unsigned int asid;
+	unsigned int cpu = smp_processor_id();
+	struct mm_struct *mm = current->active_mm;
+
+	smp_rmb();
+	asid = cpu_last_asid + cpu;
+
+	flush_context();
+	set_mm_context(mm, asid);
+
+	/* set the new ASID */
+	cpu_switch_mm(mm->pgd, mm);
+}
+
+#else
+
+static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+	mm->context.id = asid;
+	cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
+}
+
+#endif
+
+void __new_context(struct mm_struct *mm)
+{
+	unsigned int asid;
+	unsigned int bits = asid_bits();
+
+	spin_lock(&cpu_asid_lock);
+#ifdef CONFIG_SMP
+	/*
+	 * Check the ASID again, in case the change was broadcast from another
+	 * CPU before we acquired the lock.
+	 */
+	if (!unlikely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
+		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+		spin_unlock(&cpu_asid_lock);
+		return;
+	}
+#endif
+	/*
+	 * At this point, it is guaranteed that the current mm (with an old
+	 * ASID) isn't active on any other CPU since the ASIDs are changed
+	 * simultaneously via IPI.
+	 */
+	asid = ++cpu_last_asid;
+
+	/*
+	 * If we've used up all our ASIDs, we need to start a new version and
+	 * flush the TLB.
+	 */
+	if (unlikely((asid & ((1 << bits) - 1)) == 0)) {
+		/* increment the ASID version */
+		cpu_last_asid += (1 << MAX_ASID_BITS) - (1 << bits);
+		if (cpu_last_asid == 0)
+			cpu_last_asid = ASID_FIRST_VERSION;
+		asid = cpu_last_asid + smp_processor_id();
+		flush_context();
+#ifdef CONFIG_SMP
+		smp_wmb();
+		smp_call_function(reset_context, NULL, 1);
+#endif
+		cpu_last_asid += NR_CPUS - 1;
+	}
+
+	set_mm_context(mm, asid);
+	spin_unlock(&cpu_asid_lock);
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:26 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:26 +0100
Subject: [PATCH v2 25/31] arm64: Performance counters support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-26-git-send-email-catalin.marinas@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds support for the AArch64 performance counters.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/perf_event.h |   22 +
 arch/arm64/include/asm/pmu.h        |   82 +++
 arch/arm64/kernel/perf_event.c      | 1368 +++++++++++++++++++++++++++++++++++
 tools/perf/perf.h                   |    6 +
 4 files changed, 1478 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/perf_event.h
 create mode 100644 arch/arm64/include/asm/pmu.h
 create mode 100644 arch/arm64/kernel/perf_event.c

diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
new file mode 100644
index 0000000..a6fffd5
--- /dev/null
+++ b/arch/arm64/include/asm/perf_event.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_PERF_EVENT_H
+#define __ASM_PERF_EVENT_H
+
+/* It's quiet around here... */
+
+#endif
diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
new file mode 100644
index 0000000..e6f0878
--- /dev/null
+++ b/arch/arm64/include/asm/pmu.h
@@ -0,0 +1,82 @@
+/*
+ * Based on arch/arm/include/asm/pmu.h
+ *
+ * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PMU_H
+#define __ASM_PMU_H
+
+#ifdef CONFIG_HW_PERF_EVENTS
+
+/* The events for a given PMU register set. */
+struct pmu_hw_events {
+	/*
+	 * The events that are active on the PMU for the given index.
+	 */
+	struct perf_event	**events;
+
+	/*
+	 * A 1 bit for an index indicates that the counter is being used for
+	 * an event. A 0 means that the counter can be used.
+	 */
+	unsigned long           *used_mask;
+
+	/*
+	 * Hardware lock to serialize accesses to PMU registers. Needed for the
+	 * read/modify/write sequences.
+	 */
+	raw_spinlock_t		pmu_lock;
+};
+
+struct arm_pmu {
+	struct pmu		pmu;
+	cpumask_t		active_irqs;
+	const char		*name;
+	irqreturn_t		(*handle_irq)(int irq_num, void *dev);
+	void			(*enable)(struct hw_perf_event *evt, int idx);
+	void			(*disable)(struct hw_perf_event *evt, int idx);
+	int			(*get_event_idx)(struct pmu_hw_events *hw_events,
+						 struct hw_perf_event *hwc);
+	int			(*set_event_filter)(struct hw_perf_event *evt,
+						    struct perf_event_attr *attr);
+	u32			(*read_counter)(int idx);
+	void			(*write_counter)(int idx, u32 val);
+	void			(*start)(void);
+	void			(*stop)(void);
+	void			(*reset)(void *);
+	int			(*map_event)(struct perf_event *event);
+	int			num_events;
+	atomic_t		active_events;
+	struct mutex		reserve_mutex;
+	u64			max_period;
+	struct platform_device	*plat_device;
+	struct pmu_hw_events	*(*get_hw_events)(void);
+};
+
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
+
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+
+u64 armpmu_event_update(struct perf_event *event,
+			struct hw_perf_event *hwc,
+			int idx);
+
+int armpmu_event_set_period(struct perf_event *event,
+			    struct hw_perf_event *hwc,
+			    int idx);
+
+#endif /* CONFIG_HW_PERF_EVENTS */
+#endif /* __ASM_PMU_H */
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
new file mode 100644
index 0000000..ecbf2d8
--- /dev/null
+++ b/arch/arm64/kernel/perf_event.c
@@ -0,0 +1,1368 @@
+/*
+ * PMU support
+ *
+ * Copyright (C) 2012 ARM Limited
+ * Author: Will Deacon <will.deacon at arm.com>
+ *
+ * This code is based heavily on the ARMv7 perf event code.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#define pr_fmt(fmt) "hw perfevents: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/perf_event.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+
+#include <asm/cputype.h>
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+#include <asm/stacktrace.h>
+
+/*
+ * ARMv8 supports a maximum of 32 events.
+ * The cycle counter is included in this total.
+ */
+#define ARMPMU_MAX_HWEVENTS		32
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+int
+armpmu_get_max_events(void)
+{
+	int max_events = 0;
+
+	if (cpu_pmu != NULL)
+		max_events = cpu_pmu->num_events;
+
+	return max_events;
+}
+EXPORT_SYMBOL_GPL(armpmu_get_max_events);
+
+int perf_num_counters(void)
+{
+	return armpmu_get_max_events();
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+#define HW_OP_UNSUPPORTED		0xFFFF
+
+#define C(_x) \
+	PERF_COUNT_HW_CACHE_##_x
+
+#define CACHE_OP_UNSUPPORTED		0xFFFF
+
+static int
+armpmu_map_cache_event(const unsigned (*cache_map)
+				      [PERF_COUNT_HW_CACHE_MAX]
+				      [PERF_COUNT_HW_CACHE_OP_MAX]
+				      [PERF_COUNT_HW_CACHE_RESULT_MAX],
+		       u64 config)
+{
+	unsigned int cache_type, cache_op, cache_result, ret;
+
+	cache_type = (config >>  0) & 0xff;
+	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+		return -EINVAL;
+
+	cache_op = (config >>  8) & 0xff;
+	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+		return -EINVAL;
+
+	cache_result = (config >> 16) & 0xff;
+	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+		return -EINVAL;
+
+	ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
+
+	if (ret == CACHE_OP_UNSUPPORTED)
+		return -ENOENT;
+
+	return ret;
+}
+
+static int
+armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+{
+	int mapping = (*event_map)[config];
+	return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
+}
+
+static int
+armpmu_map_raw_event(u32 raw_event_mask, u64 config)
+{
+	return (int)(config & raw_event_mask);
+}
+
+static int map_cpu_event(struct perf_event *event,
+			 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+			 const unsigned (*cache_map)
+					[PERF_COUNT_HW_CACHE_MAX]
+					[PERF_COUNT_HW_CACHE_OP_MAX]
+					[PERF_COUNT_HW_CACHE_RESULT_MAX],
+			 u32 raw_event_mask)
+{
+	u64 config = event->attr.config;
+
+	switch (event->attr.type) {
+	case PERF_TYPE_HARDWARE:
+		return armpmu_map_event(event_map, config);
+	case PERF_TYPE_HW_CACHE:
+		return armpmu_map_cache_event(cache_map, config);
+	case PERF_TYPE_RAW:
+		return armpmu_map_raw_event(raw_event_mask, config);
+	}
+
+	return -ENOENT;
+}
+
+int
+armpmu_event_set_period(struct perf_event *event,
+			struct hw_perf_event *hwc,
+			int idx)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	s64 left = local64_read(&hwc->period_left);
+	s64 period = hwc->sample_period;
+	int ret = 0;
+
+	if (unlikely(left <= -period)) {
+		left = period;
+		local64_set(&hwc->period_left, left);
+		hwc->last_period = period;
+		ret = 1;
+	}
+
+	if (unlikely(left <= 0)) {
+		left += period;
+		local64_set(&hwc->period_left, left);
+		hwc->last_period = period;
+		ret = 1;
+	}
+
+	if (left > (s64)armpmu->max_period)
+		left = armpmu->max_period;
+
+	local64_set(&hwc->prev_count, (u64)-left);
+
+	armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
+
+	perf_event_update_userpage(event);
+
+	return ret;
+}
+
+u64
+armpmu_event_update(struct perf_event *event,
+		    struct hw_perf_event *hwc,
+		    int idx)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	u64 delta, prev_raw_count, new_raw_count;
+
+again:
+	prev_raw_count = local64_read(&hwc->prev_count);
+	new_raw_count = armpmu->read_counter(idx);
+
+	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+			     new_raw_count) != prev_raw_count)
+		goto again;
+
+	delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
+
+	local64_add(delta, &event->count);
+	local64_sub(delta, &hwc->period_left);
+
+	return new_raw_count;
+}
+
+static void
+armpmu_read(struct perf_event *event)
+{
+	struct hw_perf_event *hwc = &event->hw;
+
+	/* Don't read disabled counters! */
+	if (hwc->idx < 0)
+		return;
+
+	armpmu_event_update(event, hwc, hwc->idx);
+}
+
+static void
+armpmu_stop(struct perf_event *event, int flags)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct hw_perf_event *hwc = &event->hw;
+
+	/*
+	 * ARM pmu always has to update the counter, so ignore
+	 * PERF_EF_UPDATE, see comments in armpmu_start().
+	 */
+	if (!(hwc->state & PERF_HES_STOPPED)) {
+		armpmu->disable(hwc, hwc->idx);
+		barrier(); /* why? */
+		armpmu_event_update(event, hwc, hwc->idx);
+		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
+	}
+}
+
+static void
+armpmu_start(struct perf_event *event, int flags)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct hw_perf_event *hwc = &event->hw;
+
+	/*
+	 * ARM pmu always has to reprogram the period, so ignore
+	 * PERF_EF_RELOAD, see the comment below.
+	 */
+	if (flags & PERF_EF_RELOAD)
+		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+
+	hwc->state = 0;
+	/*
+	 * Set the period again. Some counters can't be stopped, so when we
+	 * were stopped we simply disabled the IRQ source and the counter
+	 * may have been left counting. If we don't do this step then we may
+	 * get an interrupt too soon or *way* too late if the overflow has
+	 * happened since disabling.
+	 */
+	armpmu_event_set_period(event, hwc, hwc->idx);
+	armpmu->enable(hwc, hwc->idx);
+}
+
+static void
+armpmu_del(struct perf_event *event, int flags)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+	struct hw_perf_event *hwc = &event->hw;
+	int idx = hwc->idx;
+
+	WARN_ON(idx < 0);
+
+	armpmu_stop(event, PERF_EF_UPDATE);
+	hw_events->events[idx] = NULL;
+	clear_bit(idx, hw_events->used_mask);
+
+	perf_event_update_userpage(event);
+}
+
+static int
+armpmu_add(struct perf_event *event, int flags)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+	struct hw_perf_event *hwc = &event->hw;
+	int idx;
+	int err = 0;
+
+	perf_pmu_disable(event->pmu);
+
+	/* If we don't have a space for the counter then finish early. */
+	idx = armpmu->get_event_idx(hw_events, hwc);
+	if (idx < 0) {
+		err = idx;
+		goto out;
+	}
+
+	/*
+	 * If there is an event in the counter we are going to use then make
+	 * sure it is disabled.
+	 */
+	event->hw.idx = idx;
+	armpmu->disable(hwc, idx);
+	hw_events->events[idx] = event;
+
+	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+	if (flags & PERF_EF_START)
+		armpmu_start(event, PERF_EF_RELOAD);
+
+	/* Propagate our changes to the userspace mapping. */
+	perf_event_update_userpage(event);
+
+out:
+	perf_pmu_enable(event->pmu);
+	return err;
+}
+
+static int
+validate_event(struct pmu_hw_events *hw_events,
+	       struct perf_event *event)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct hw_perf_event fake_event = event->hw;
+	struct pmu *leader_pmu = event->group_leader->pmu;
+
+	if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
+		return 1;
+
+	return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
+}
+
+static int
+validate_group(struct perf_event *event)
+{
+	struct perf_event *sibling, *leader = event->group_leader;
+	struct pmu_hw_events fake_pmu;
+	DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
+
+	/*
+	 * Initialise the fake PMU. We only need to populate the
+	 * used_mask for the purposes of validation.
+	 */
+	memset(fake_used_mask, 0, sizeof(fake_used_mask));
+	fake_pmu.used_mask = fake_used_mask;
+
+	if (!validate_event(&fake_pmu, leader))
+		return -EINVAL;
+
+	list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+		if (!validate_event(&fake_pmu, sibling))
+			return -EINVAL;
+	}
+
+	if (!validate_event(&fake_pmu, event))
+		return -EINVAL;
+
+	return 0;
+}
+
+static void
+armpmu_release_hardware(struct arm_pmu *armpmu)
+{
+	int i, irq, irqs;
+	struct platform_device *pmu_device = armpmu->plat_device;
+
+	irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+	for (i = 0; i < irqs; ++i) {
+		if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
+			continue;
+		irq = platform_get_irq(pmu_device, i);
+		if (irq >= 0)
+			free_irq(irq, armpmu);
+	}
+}
+
+static int
+armpmu_reserve_hardware(struct arm_pmu *armpmu)
+{
+	int i, err, irq, irqs;
+	struct platform_device *pmu_device = armpmu->plat_device;
+
+	if (!pmu_device) {
+		pr_err("no PMU device registered\n");
+		return -ENODEV;
+	}
+
+	irqs = min(pmu_device->num_resources, num_possible_cpus());
+	if (irqs < 1) {
+		pr_err("no irqs for PMUs defined\n");
+		return -ENODEV;
+	}
+
+	for (i = 0; i < irqs; ++i) {
+		err = 0;
+		irq = platform_get_irq(pmu_device, i);
+		if (irq < 0)
+			continue;
+
+		/*
+		 * If we have a single PMU interrupt that we can't shift,
+		 * assume that we're running on a uniprocessor machine and
+		 * continue. Otherwise, continue without this interrupt.
+		 */
+		if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+			pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+				    irq, i);
+			continue;
+		}
+
+		err = request_irq(irq, armpmu->handle_irq,
+				  IRQF_NOBALANCING,
+				  "arm-pmu", armpmu);
+		if (err) {
+			pr_err("unable to request IRQ%d for ARM PMU counters\n",
+				irq);
+			armpmu_release_hardware(armpmu);
+			return err;
+		}
+
+		cpumask_set_cpu(i, &armpmu->active_irqs);
+	}
+
+	return 0;
+}
+
+static void
+hw_perf_event_destroy(struct perf_event *event)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	atomic_t *active_events	 = &armpmu->active_events;
+	struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
+
+	if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
+		armpmu_release_hardware(armpmu);
+		mutex_unlock(pmu_reserve_mutex);
+	}
+}
+
+static int
+event_requires_mode_exclusion(struct perf_event_attr *attr)
+{
+	return attr->exclude_idle || attr->exclude_user ||
+	       attr->exclude_kernel || attr->exclude_hv;
+}
+
+static int
+__hw_perf_event_init(struct perf_event *event)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	struct hw_perf_event *hwc = &event->hw;
+	int mapping, err;
+
+	mapping = armpmu->map_event(event);
+
+	if (mapping < 0) {
+		pr_debug("event %x:%llx not supported\n", event->attr.type,
+			 event->attr.config);
+		return mapping;
+	}
+
+	/*
+	 * We don't assign an index until we actually place the event onto
+	 * hardware. Use -1 to signify that we haven't decided where to put it
+	 * yet. For SMP systems, each core has it's own PMU so we can't do any
+	 * clever allocation or constraints checking at this point.
+	 */
+	hwc->idx		= -1;
+	hwc->config_base	= 0;
+	hwc->config		= 0;
+	hwc->event_base		= 0;
+
+	/*
+	 * Check whether we need to exclude the counter from certain modes.
+	 */
+	if ((!armpmu->set_event_filter ||
+	     armpmu->set_event_filter(hwc, &event->attr)) &&
+	     event_requires_mode_exclusion(&event->attr)) {
+		pr_debug("ARM performance counters do not support mode exclusion\n");
+		return -EPERM;
+	}
+
+	/*
+	 * Store the event encoding into the config_base field.
+	 */
+	hwc->config_base	    |= (unsigned long)mapping;
+
+	if (!hwc->sample_period) {
+		/*
+		 * For non-sampling runs, limit the sample_period to half
+		 * of the counter width. That way, the new counter value
+		 * is far less likely to overtake the previous one unless
+		 * you have some serious IRQ latency issues.
+		 */
+		hwc->sample_period  = armpmu->max_period >> 1;
+		hwc->last_period    = hwc->sample_period;
+		local64_set(&hwc->period_left, hwc->sample_period);
+	}
+
+	err = 0;
+	if (event->group_leader != event) {
+		err = validate_group(event);
+		if (err)
+			return -EINVAL;
+	}
+
+	return err;
+}
+
+static int armpmu_event_init(struct perf_event *event)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+	int err = 0;
+	atomic_t *active_events = &armpmu->active_events;
+
+	if (armpmu->map_event(event) == -ENOENT)
+		return -ENOENT;
+
+	event->destroy = hw_perf_event_destroy;
+
+	if (!atomic_inc_not_zero(active_events)) {
+		mutex_lock(&armpmu->reserve_mutex);
+		if (atomic_read(active_events) == 0)
+			err = armpmu_reserve_hardware(armpmu);
+
+		if (!err)
+			atomic_inc(active_events);
+		mutex_unlock(&armpmu->reserve_mutex);
+	}
+
+	if (err)
+		return err;
+
+	err = __hw_perf_event_init(event);
+	if (err)
+		hw_perf_event_destroy(event);
+
+	return err;
+}
+
+static void armpmu_enable(struct pmu *pmu)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(pmu);
+	struct pmu_hw_events *hw_events = armpmu->get_hw_events();
+	int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
+
+	if (enabled)
+		armpmu->start();
+}
+
+static void armpmu_disable(struct pmu *pmu)
+{
+	struct arm_pmu *armpmu = to_arm_pmu(pmu);
+	armpmu->stop();
+}
+
+static void __init armpmu_init(struct arm_pmu *armpmu)
+{
+	atomic_set(&armpmu->active_events, 0);
+	mutex_init(&armpmu->reserve_mutex);
+
+	armpmu->pmu = (struct pmu) {
+		.pmu_enable	= armpmu_enable,
+		.pmu_disable	= armpmu_disable,
+		.event_init	= armpmu_event_init,
+		.add		= armpmu_add,
+		.del		= armpmu_del,
+		.start		= armpmu_start,
+		.stop		= armpmu_stop,
+		.read		= armpmu_read,
+	};
+}
+
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+{
+	armpmu_init(armpmu);
+	return perf_pmu_register(&armpmu->pmu, name, type);
+}
+
+/*
+ * ARMv8 PMUv3 Performance Events handling code.
+ * Common event types.
+ */
+enum armv8_pmuv3_perf_types {
+	/* Required events. */
+	ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR			= 0x00,
+	ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL			= 0x03,
+	ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS			= 0x04,
+	ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED			= 0x10,
+	ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES			= 0x11,
+	ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED			= 0x12,
+
+	/* At least one of the following is required. */
+	ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED			= 0x08,
+	ARMV8_PMUV3_PERFCTR_OP_SPEC				= 0x1B,
+
+	/* Common architectural events. */
+	ARMV8_PMUV3_PERFCTR_MEM_READ				= 0x06,
+	ARMV8_PMUV3_PERFCTR_MEM_WRITE				= 0x07,
+	ARMV8_PMUV3_PERFCTR_EXC_TAKEN				= 0x09,
+	ARMV8_PMUV3_PERFCTR_EXC_EXECUTED			= 0x0A,
+	ARMV8_PMUV3_PERFCTR_CID_WRITE				= 0x0B,
+	ARMV8_PMUV3_PERFCTR_PC_WRITE				= 0x0C,
+	ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH			= 0x0D,
+	ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN			= 0x0E,
+	ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS		= 0x0F,
+	ARMV8_PMUV3_PERFCTR_TTBR_WRITE				= 0x1C,
+
+	/* Common microarchitectural events. */
+	ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL			= 0x01,
+	ARMV8_PMUV3_PERFCTR_ITLB_REFILL				= 0x02,
+	ARMV8_PMUV3_PERFCTR_DTLB_REFILL				= 0x05,
+	ARMV8_PMUV3_PERFCTR_MEM_ACCESS				= 0x13,
+	ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS			= 0x14,
+	ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB			= 0x15,
+	ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS			= 0x16,
+	ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL			= 0x17,
+	ARMV8_PMUV3_PERFCTR_L2_CACHE_WB				= 0x18,
+	ARMV8_PMUV3_PERFCTR_BUS_ACCESS				= 0x19,
+	ARMV8_PMUV3_PERFCTR_MEM_ERROR				= 0x1A,
+	ARMV8_PMUV3_PERFCTR_BUS_CYCLES				= 0x1D,
+
+	/*
+	 * This isn't an architected event.
+	 * We detect this event number and use the cycle counter instead.
+	 */
+	ARMV8_PMUV3_PERFCTR_CPU_CYCLES				= 0xFF,
+};
+
+/* PMUv3 HW events mapping. */
+static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
+	[PERF_COUNT_HW_CPU_CYCLES]		= ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
+	[PERF_COUNT_HW_INSTRUCTIONS]		= ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
+	[PERF_COUNT_HW_CACHE_REFERENCES]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
+	[PERF_COUNT_HW_CACHE_MISSES]		= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_BRANCH_MISSES]		= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
+	[PERF_COUNT_HW_BUS_CYCLES]		= HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= HW_OP_UNSUPPORTED,
+	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+						[PERF_COUNT_HW_CACHE_OP_MAX]
+						[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+	[C(L1D)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
+			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(L1I)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(LL)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(DTLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(ITLB)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(BPU)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
+			[C(RESULT_MISS)]	= ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+	[C(NODE)] = {
+		[C(OP_READ)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_WRITE)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+		[C(OP_PREFETCH)] = {
+			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
+			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
+		},
+	},
+};
+
+/*
+ * Perf Events' indices
+ */
+#define	ARMV8_IDX_CYCLE_COUNTER	0
+#define	ARMV8_IDX_COUNTER0	1
+#define	ARMV8_IDX_COUNTER_LAST	(ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
+
+#define	ARMV8_MAX_COUNTERS	32
+#define	ARMV8_COUNTER_MASK	(ARMV8_MAX_COUNTERS - 1)
+
+/*
+ * ARMv8 low level PMU access
+ */
+
+/*
+ * Perf Event to low level counters mapping
+ */
+#define	ARMV8_IDX_TO_COUNTER(x)	\
+	(((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
+
+/*
+ * Per-CPU PMCR: config reg
+ */
+#define ARMV8_PMCR_E		(1 << 0) /* Enable all counters */
+#define ARMV8_PMCR_P		(1 << 1) /* Reset all counters */
+#define ARMV8_PMCR_C		(1 << 2) /* Cycle counter reset */
+#define ARMV8_PMCR_D		(1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV8_PMCR_X		(1 << 4) /* Export to ETM */
+#define ARMV8_PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
+#define	ARMV8_PMCR_N_SHIFT	11	 /* Number of counters supported */
+#define	ARMV8_PMCR_N_MASK	0x1f
+#define	ARMV8_PMCR_MASK		0x3f	 /* Mask for writable bits */
+
+/*
+ * PMOVSR: counters overflow flag status reg
+ */
+#define	ARMV8_OVSR_MASK		0xffffffff	/* Mask for writable bits */
+#define	ARMV8_OVERFLOWED_MASK	ARMV8_OVSR_MASK
+
+/*
+ * PMXEVTYPER: Event selection reg
+ */
+#define	ARMV8_EVTYPE_MASK	0xc00000ff	/* Mask for writable bits */
+#define	ARMV8_EVTYPE_EVENT	0xff		/* Mask for EVENT bits */
+
+/*
+ * Event filters for PMUv3
+ */
+#define	ARMV8_EXCLUDE_EL1	(1 << 31)
+#define	ARMV8_EXCLUDE_EL0	(1 << 30)
+#define	ARMV8_INCLUDE_EL2	(1 << 27)
+
+static inline u32 armv8pmu_pmcr_read(void)
+{
+	u32 val;
+	asm volatile("mrs %0, pmcr_el0" : "=r" (val));
+	return val;
+}
+
+static inline void armv8pmu_pmcr_write(u32 val)
+{
+	val &= ARMV8_PMCR_MASK;
+	isb();
+	asm volatile("msr pmcr_el0, %0" :: "r" (val));
+}
+
+static inline int armv8pmu_has_overflowed(u32 pmovsr)
+{
+	return pmovsr & ARMV8_OVERFLOWED_MASK;
+}
+
+static inline int armv8pmu_counter_valid(int idx)
+{
+	return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
+}
+
+static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
+{
+	int ret = 0;
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u checking wrong counter %d overflow status\n",
+			smp_processor_id(), idx);
+	} else {
+		counter = ARMV8_IDX_TO_COUNTER(idx);
+		ret = pmnc & BIT(counter);
+	}
+
+	return ret;
+}
+
+static inline int armv8pmu_select_counter(int idx)
+{
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u selecting wrong PMNC counter %d\n",
+			smp_processor_id(), idx);
+		return -EINVAL;
+	}
+
+	counter = ARMV8_IDX_TO_COUNTER(idx);
+	asm volatile("msr pmselr_el0, %0" :: "r" (counter));
+	isb();
+
+	return idx;
+}
+
+static inline u32 armv8pmu_read_counter(int idx)
+{
+	u32 value = 0;
+
+	if (!armv8pmu_counter_valid(idx))
+		pr_err("CPU%u reading wrong counter %d\n",
+			smp_processor_id(), idx);
+	else if (idx == ARMV8_IDX_CYCLE_COUNTER)
+		asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
+	else if (armv8pmu_select_counter(idx) == idx)
+		asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
+
+	return value;
+}
+
+static inline void armv8pmu_write_counter(int idx, u32 value)
+{
+	if (!armv8pmu_counter_valid(idx))
+		pr_err("CPU%u writing wrong counter %d\n",
+			smp_processor_id(), idx);
+	else if (idx == ARMV8_IDX_CYCLE_COUNTER)
+		asm volatile("msr pmccntr_el0, %0" :: "r" (value));
+	else if (armv8pmu_select_counter(idx) == idx)
+		asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
+}
+
+static inline void armv8pmu_write_evtype(int idx, u32 val)
+{
+	if (armv8pmu_select_counter(idx) == idx) {
+		val &= ARMV8_EVTYPE_MASK;
+		asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
+	}
+}
+
+static inline int armv8pmu_enable_counter(int idx)
+{
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u enabling wrong PMNC counter %d\n",
+			smp_processor_id(), idx);
+		return -EINVAL;
+	}
+
+	counter = ARMV8_IDX_TO_COUNTER(idx);
+	asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
+	return idx;
+}
+
+static inline int armv8pmu_disable_counter(int idx)
+{
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u disabling wrong PMNC counter %d\n",
+			smp_processor_id(), idx);
+		return -EINVAL;
+	}
+
+	counter = ARMV8_IDX_TO_COUNTER(idx);
+	asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
+	return idx;
+}
+
+static inline int armv8pmu_enable_intens(int idx)
+{
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
+			smp_processor_id(), idx);
+		return -EINVAL;
+	}
+
+	counter = ARMV8_IDX_TO_COUNTER(idx);
+	asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
+	return idx;
+}
+
+static inline int armv8pmu_disable_intens(int idx)
+{
+	u32 counter;
+
+	if (!armv8pmu_counter_valid(idx)) {
+		pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
+			smp_processor_id(), idx);
+		return -EINVAL;
+	}
+
+	counter = ARMV8_IDX_TO_COUNTER(idx);
+	asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
+	isb();
+	/* Clear the overflow flag in case an interrupt is pending. */
+	asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
+	isb();
+	return idx;
+}
+
+static inline u32 armv8pmu_getreset_flags(void)
+{
+	u32 value;
+
+	/* Read */
+	asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
+
+	/* Write to clear flags */
+	value &= ARMV8_OVSR_MASK;
+	asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
+
+	return value;
+}
+
+static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+	unsigned long flags;
+	struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+
+	/*
+	 * Enable counter and interrupt, and set the counter to count
+	 * the event that we're interested in.
+	 */
+	raw_spin_lock_irqsave(&events->pmu_lock, flags);
+
+	/*
+	 * Disable counter
+	 */
+	armv8pmu_disable_counter(idx);
+
+	/*
+	 * Set event (if destined for PMNx counters).
+	 */
+	armv8pmu_write_evtype(idx, hwc->config_base);
+
+	/*
+	 * Enable interrupt for this counter
+	 */
+	armv8pmu_enable_intens(idx);
+
+	/*
+	 * Enable counter
+	 */
+	armv8pmu_enable_counter(idx);
+
+	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+	unsigned long flags;
+	struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+
+	/*
+	 * Disable counter and interrupt
+	 */
+	raw_spin_lock_irqsave(&events->pmu_lock, flags);
+
+	/*
+	 * Disable counter
+	 */
+	armv8pmu_disable_counter(idx);
+
+	/*
+	 * Disable interrupt for this counter
+	 */
+	armv8pmu_disable_intens(idx);
+
+	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
+{
+	u32 pmovsr;
+	struct perf_sample_data data;
+	struct pmu_hw_events *cpuc;
+	struct pt_regs *regs;
+	int idx;
+
+	/*
+	 * Get and reset the IRQ flags
+	 */
+	pmovsr = armv8pmu_getreset_flags();
+
+	/*
+	 * Did an overflow occur?
+	 */
+	if (!armv8pmu_has_overflowed(pmovsr))
+		return IRQ_NONE;
+
+	/*
+	 * Handle the counter(s) overflow(s)
+	 */
+	regs = get_irq_regs();
+
+	cpuc = &__get_cpu_var(cpu_hw_events);
+	for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
+		struct perf_event *event = cpuc->events[idx];
+		struct hw_perf_event *hwc;
+
+		/* Ignore if we don't have an event. */
+		if (!event)
+			continue;
+
+		/*
+		 * We have a single interrupt for all counters. Check that
+		 * each counter has overflowed before we process it.
+		 */
+		if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
+			continue;
+
+		hwc = &event->hw;
+		armpmu_event_update(event, hwc, idx);
+		perf_sample_data_init(&data, 0, hwc->last_period);
+		if (!armpmu_event_set_period(event, hwc, idx))
+			continue;
+
+		if (perf_event_overflow(event, &data, regs))
+			cpu_pmu->disable(hwc, idx);
+	}
+
+	/*
+	 * Handle the pending perf events.
+	 *
+	 * Note: this call *must* be run with interrupts disabled. For
+	 * platforms that can have the PMU interrupts raised as an NMI, this
+	 * will not work.
+	 */
+	irq_work_run();
+
+	return IRQ_HANDLED;
+}
+
+static void armv8pmu_start(void)
+{
+	unsigned long flags;
+	struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+
+	raw_spin_lock_irqsave(&events->pmu_lock, flags);
+	/* Enable all counters */
+	armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
+	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static void armv8pmu_stop(void)
+{
+	unsigned long flags;
+	struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+
+	raw_spin_lock_irqsave(&events->pmu_lock, flags);
+	/* Disable all counters */
+	armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
+	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
+				  struct hw_perf_event *event)
+{
+	int idx;
+	unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
+
+	/* Always place a cycle counter into the cycle counter. */
+	if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
+		if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
+			return -EAGAIN;
+
+		return ARMV8_IDX_CYCLE_COUNTER;
+	}
+
+	/*
+	 * For anything other than a cycle counter, try and use
+	 * the events counters
+	 */
+	for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
+		if (!test_and_set_bit(idx, cpuc->used_mask))
+			return idx;
+	}
+
+	/* The counters are all in use. */
+	return -EAGAIN;
+}
+
+/*
+ * Add an event filter to a given event. This will only work for PMUv2 PMUs.
+ */
+static int armv8pmu_set_event_filter(struct hw_perf_event *event,
+				     struct perf_event_attr *attr)
+{
+	unsigned long config_base = 0;
+
+	if (attr->exclude_idle)
+		return -EPERM;
+	if (attr->exclude_user)
+		config_base |= ARMV8_EXCLUDE_EL0;
+	if (attr->exclude_kernel)
+		config_base |= ARMV8_EXCLUDE_EL1;
+	if (!attr->exclude_hv)
+		config_base |= ARMV8_INCLUDE_EL2;
+
+	/*
+	 * Install the filter into config_base as this is used to
+	 * construct the event type.
+	 */
+	event->config_base = config_base;
+
+	return 0;
+}
+
+static void armv8pmu_reset(void *info)
+{
+	u32 idx, nb_cnt = cpu_pmu->num_events;
+
+	/* The counter and interrupt enable registers are unknown at reset. */
+	for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
+		armv8pmu_disable_event(NULL, idx);
+
+	/* Initialize & Reset PMNC: C and P bits. */
+	armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
+
+	/* Disable access from userspace. */
+	asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
+}
+
+static int armv8_pmuv3_map_event(struct perf_event *event)
+{
+	return map_cpu_event(event, &armv8_pmuv3_perf_map,
+				&armv8_pmuv3_perf_cache_map, 0xFF);
+}
+
+static struct arm_pmu armv8pmu = {
+	.handle_irq		= armv8pmu_handle_irq,
+	.enable			= armv8pmu_enable_event,
+	.disable		= armv8pmu_disable_event,
+	.read_counter		= armv8pmu_read_counter,
+	.write_counter		= armv8pmu_write_counter,
+	.get_event_idx		= armv8pmu_get_event_idx,
+	.start			= armv8pmu_start,
+	.stop			= armv8pmu_stop,
+	.reset			= armv8pmu_reset,
+	.max_period		= (1LLU << 32) - 1,
+};
+
+static u32 __init armv8pmu_read_num_pmnc_events(void)
+{
+	u32 nb_cnt;
+
+	/* Read the nb of CNTx counters supported from PMNC */
+	nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
+
+	/* Add the CPU cycles counter and return */
+	return nb_cnt + 1;
+}
+
+static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
+{
+	armv8pmu.name			= "arm/armv8-pmuv3";
+	armv8pmu.map_event		= armv8_pmuv3_map_event;
+	armv8pmu.num_events		= armv8pmu_read_num_pmnc_events();
+	armv8pmu.set_event_filter	= armv8pmu_set_event_filter;
+	return &armv8pmu;
+}
+
+/*
+ * Ensure the PMU has sane values out of reset.
+ * This requires SMP to be available, so exists as a separate initcall.
+ */
+static int __init
+cpu_pmu_reset(void)
+{
+	if (cpu_pmu && cpu_pmu->reset)
+		return on_each_cpu(cpu_pmu->reset, NULL, 1);
+	return 0;
+}
+arch_initcall(cpu_pmu_reset);
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id armpmu_of_device_ids[] = {
+	{.compatible = "arm,armv8-pmuv3"},
+	{},
+};
+
+static int __devinit armpmu_device_probe(struct platform_device *pdev)
+{
+	if (!cpu_pmu)
+		return -ENODEV;
+
+	cpu_pmu->plat_device = pdev;
+	return 0;
+}
+
+static struct platform_driver armpmu_driver = {
+	.driver		= {
+		.name	= "arm-pmu",
+		.of_match_table = armpmu_of_device_ids,
+	},
+	.probe		= armpmu_device_probe,
+};
+
+static int __init register_pmu_driver(void)
+{
+	return platform_driver_register(&armpmu_driver);
+}
+device_initcall(register_pmu_driver);
+
+static struct pmu_hw_events *armpmu_get_cpu_events(void)
+{
+	return &__get_cpu_var(cpu_hw_events);
+}
+
+static void __init cpu_pmu_init(struct arm_pmu *armpmu)
+{
+	int cpu;
+	for_each_possible_cpu(cpu) {
+		struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+		events->events = per_cpu(hw_events, cpu);
+		events->used_mask = per_cpu(used_mask, cpu);
+		raw_spin_lock_init(&events->pmu_lock);
+	}
+	armpmu->get_hw_events = armpmu_get_cpu_events;
+}
+
+static int __init init_hw_perf_events(void)
+{
+	u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
+
+	switch ((dfr >> 8) & 0xf) {
+	case 0x1:	/* PMUv3 */
+		cpu_pmu = armv8_pmuv3_pmu_init();
+		break;
+	}
+
+	if (cpu_pmu) {
+		pr_info("enabled with %s PMU driver, %d counters available\n",
+			cpu_pmu->name, cpu_pmu->num_events);
+		cpu_pmu_init(cpu_pmu);
+		armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
+	} else {
+		pr_info("no hardware support available\n");
+	}
+
+	return 0;
+}
+early_initcall(init_hw_perf_events);
+
+/*
+ * Callchain handling code.
+ */
+struct frame_tail {
+	struct frame_tail   __user *fp;
+	unsigned long	    lr;
+} __attribute__((packed));
+
+/*
+ * Get the return address for a single stackframe and return a pointer to the
+ * next frame tail.
+ */
+static struct frame_tail __user *
+user_backtrace(struct frame_tail __user *tail,
+	       struct perf_callchain_entry *entry)
+{
+	struct frame_tail buftail;
+	unsigned long err;
+
+	/* Also check accessibility of one struct frame_tail beyond */
+	if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
+		return NULL;
+
+	pagefault_disable();
+	err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
+	pagefault_enable();
+
+	if (err)
+		return NULL;
+
+	perf_callchain_store(entry, buftail.lr);
+
+	/*
+	 * Frame pointers should strictly progress back up the stack
+	 * (towards higher addresses).
+	 */
+	if (tail >= buftail.fp)
+		return NULL;
+
+	return buftail.fp;
+}
+
+void perf_callchain_user(struct perf_callchain_entry *entry,
+			 struct pt_regs *regs)
+{
+	struct frame_tail __user *tail;
+
+	tail = (struct frame_tail __user *)regs->regs[29];
+
+	while (entry->nr < PERF_MAX_STACK_DEPTH &&
+	       tail && !((unsigned long)tail & 0xf))
+		tail = user_backtrace(tail, entry);
+}
+
+/*
+ * Gets called by walk_stackframe() for every stackframe. This will be called
+ * whist unwinding the stackframe and is like a subroutine return so we use
+ * the PC.
+ */
+static int callchain_trace(struct stackframe *frame, void *data)
+{
+	struct perf_callchain_entry *entry = data;
+	perf_callchain_store(entry, frame->pc);
+	return 0;
+}
+
+void perf_callchain_kernel(struct perf_callchain_entry *entry,
+			   struct pt_regs *regs)
+{
+	struct stackframe frame;
+
+	frame.fp = regs->regs[29];
+	frame.sp = regs->sp;
+	frame.pc = regs->pc;
+	walk_stackframe(&frame, callchain_trace, entry);
+}
diff --git a/tools/perf/perf.h b/tools/perf/perf.h
index f960ccb..8c36763 100644
--- a/tools/perf/perf.h
+++ b/tools/perf/perf.h
@@ -88,6 +88,12 @@ void get_term_dimensions(struct winsize *ws);
 #define CPUINFO_PROC	"Processor"
 #endif
 
+#ifdef __aarch64__
+#include "../../arch/arm64/include/asm/unistd.h"
+#define rmb()		asm volatile("dmb ld" ::: "memory")
+#define cpu_relax()	asm volatile("yield" ::: "memory")
+#endif
+
 #ifdef __mips__
 #include "../../arch/mips/include/asm/unistd.h"
 #define rmb()		asm volatile(					\



From catalin.marinas at arm.com  Tue Aug 14 13:52:12 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:12 +0100
Subject: [PATCH v2 11/31] arm64: IRQ handling
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-12-git-send-email-catalin.marinas@arm.com>

From: Marc Zyngier <marc.zyngier at arm.com>

This patch adds the support for IRQ handling. The actual interrupt
controller will be part of a separate patch (going into
drivers/irqchip/).

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/hardirq.h  |   47 +++++++++++++++++++
 arch/arm64/include/asm/irq.h      |    8 +++
 arch/arm64/include/asm/irqflags.h |   91 +++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/irq.c           |   84 ++++++++++++++++++++++++++++++++++
 4 files changed, 230 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/hardirq.h
 create mode 100644 arch/arm64/include/asm/irq.h
 create mode 100644 arch/arm64/include/asm/irqflags.h
 create mode 100644 arch/arm64/kernel/irq.c

diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
new file mode 100644
index 0000000..c6c9514
--- /dev/null
+++ b/arch/arm64/include/asm/hardirq.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_HARDIRQ_H
+#define __ASM_HARDIRQ_H
+
+#include <linux/cache.h>
+#include <linux/threads.h>
+#include <asm/irq.h>
+
+typedef struct {
+	unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
+
+#define __inc_irq_stat(cpu, member)	__IRQ_STAT(cpu, member)++
+#define __get_irq_stat(cpu, member)	__IRQ_STAT(cpu, member)
+
+#ifdef CONFIG_SMP
+u64 smp_irq_stat_cpu(unsigned int cpu);
+#define arch_irq_stat_cpu	smp_irq_stat_cpu
+#endif
+
+#define __ARCH_IRQ_EXIT_IRQS_DISABLED	1
+
+static inline void ack_bad_irq(unsigned int irq)
+{
+	extern unsigned long irq_err_count;
+	irq_err_count++;
+}
+
+extern void handle_IRQ(unsigned int, struct pt_regs *);
+
+#endif /* __ASM_HARDIRQ_H */
diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
new file mode 100644
index 0000000..a4e1cad
--- /dev/null
+++ b/arch/arm64/include/asm/irq.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_IRQ_H
+#define __ASM_IRQ_H
+
+#include <asm-generic/irq.h>
+
+extern void (*handle_arch_irq)(struct pt_regs *);
+
+#endif
diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h
new file mode 100644
index 0000000..aa11943
--- /dev/null
+++ b/arch/arm64/include/asm/irqflags.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_IRQFLAGS_H
+#define __ASM_IRQFLAGS_H
+
+#ifdef __KERNEL__
+
+#include <asm/ptrace.h>
+
+/*
+ * CPU interrupt mask handling.
+ */
+static inline unsigned long arch_local_irq_save(void)
+{
+	unsigned long flags;
+	asm volatile(
+		"mrs	%0, daif		// arch_local_irq_save\n"
+		"msr	daifset, #2"
+		: "=r" (flags)
+		:
+		: "memory");
+	return flags;
+}
+
+static inline void arch_local_irq_enable(void)
+{
+	asm volatile(
+		"msr	daifclr, #2		// arch_local_irq_enable"
+		:
+		:
+		: "memory");
+}
+
+static inline void arch_local_irq_disable(void)
+{
+	asm volatile(
+		"msr	daifset, #2		// arch_local_irq_disable"
+		:
+		:
+		: "memory");
+}
+
+#define local_fiq_enable()	asm("msr	daifclr, #1" : : : "memory")
+#define local_fiq_disable()	asm("msr	daifset, #1" : : : "memory")
+
+/*
+ * Save the current interrupt enable state.
+ */
+static inline unsigned long arch_local_save_flags(void)
+{
+	unsigned long flags;
+	asm volatile(
+		"mrs	%0, daif		// arch_local_save_flags"
+		: "=r" (flags)
+		:
+		: "memory");
+	return flags;
+}
+
+/*
+ * restore saved IRQ state
+ */
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+	asm volatile(
+		"msr	daif, %0		// arch_local_irq_restore"
+	:
+	: "r" (flags)
+	: "memory");
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+	return flags & PSR_I_BIT;
+}
+
+#endif
+#endif
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
new file mode 100644
index 0000000..d346241
--- /dev/null
+++ b/arch/arm64/kernel/irq.c
@@ -0,0 +1,84 @@
+/*
+ * Based on arch/arm/kernel/irq.c
+ *
+ * Copyright (C) 1992 Linus Torvalds
+ * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
+ * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
+ * Dynamic Tick Timer written by Tony Lindgren <tony at atomide.com> and
+ * Tuukka Tikkanen <tuukka.tikkanen at elektrobit.com>.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel_stat.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/seq_file.h>
+
+unsigned long irq_err_count;
+
+int arch_show_interrupts(struct seq_file *p, int prec)
+{
+#ifdef CONFIG_SMP
+	show_ipi_list(p, prec);
+#endif
+	seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
+	return 0;
+}
+
+/*
+ * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
+ * not come via this function.  Instead, they should provide their
+ * own 'handler'.  Used by platform code implementing C-based 1st
+ * level decoding.
+ */
+void handle_IRQ(unsigned int irq, struct pt_regs *regs)
+{
+	struct pt_regs *old_regs = set_irq_regs(regs);
+
+	irq_enter();
+
+	/*
+	 * Some hardware gives randomly wrong interrupts.  Rather
+	 * than crashing, do something sensible.
+	 */
+	if (unlikely(irq >= nr_irqs)) {
+		if (printk_ratelimit())
+			pr_warning("Bad IRQ%u\n", irq);
+		ack_bad_irq(irq);
+	} else {
+		generic_handle_irq(irq);
+	}
+
+	irq_exit();
+	set_irq_regs(old_regs);
+}
+
+/*
+ * Interrupt controllers supported by the kernel.
+ */
+static const struct of_device_id intctrl_of_match[] __initconst = {
+	/* IRQ controllers { .compatible, .data } info to go here */
+	{}
+};
+
+void __init init_IRQ(void)
+{
+	of_irq_init(intctrl_of_match);
+
+	if (!handle_arch_irq)
+		panic("No interrupt controller found.");
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:09 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:09 +0100
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>

This patch adds AArch64 CPU specific functionality. It assumes that the
implementation is generic to AArch64 and does not require specific
identification. Different CPU implementations may require the setting of
various ACTLR_EL1 bits but such information is not currently available
and it should ideally be pushed to firmware.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/cputype.h   |   49 +++++++++
 arch/arm64/include/asm/proc-fns.h  |   51 ++++++++++
 arch/arm64/include/asm/processor.h |  174 ++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/procinfo.h  |   44 ++++++++
 arch/arm64/mm/proc-syms.c          |   31 ++++++
 arch/arm64/mm/proc.S               |  193 ++++++++++++++++++++++++++++++++++++
 6 files changed, 542 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/cputype.h
 create mode 100644 arch/arm64/include/asm/proc-fns.h
 create mode 100644 arch/arm64/include/asm/processor.h
 create mode 100644 arch/arm64/include/asm/procinfo.h
 create mode 100644 arch/arm64/mm/proc-syms.c
 create mode 100644 arch/arm64/mm/proc.S

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
new file mode 100644
index 0000000..ef54125
--- /dev/null
+++ b/arch/arm64/include/asm/cputype.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_CPUTYPE_H
+#define __ASM_CPUTYPE_H
+
+#define ID_MIDR_EL1		"midr_el1"
+#define ID_CTR_EL0		"ctr_el0"
+
+#define ID_AA64PFR0_EL1		"id_aa64pfr0_el1"
+#define ID_AA64DFR0_EL1		"id_aa64dfr0_el1"
+#define ID_AA64AFR0_EL1		"id_aa64afr0_el1"
+#define ID_AA64ISAR0_EL1	"id_aa64isar0_el1"
+#define ID_AA64MMFR0_EL1	"id_aa64mmfr0_el1"
+
+#define read_cpuid(reg) ({						\
+	u64 __val;							\
+	asm("mrs	%0, " reg : "=r" (__val));			\
+	__val;								\
+})
+
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant.  Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline u32 __attribute_const__ read_cpuid_id(void)
+{
+	return read_cpuid(ID_MIDR_EL1);
+}
+
+static inline u32 __attribute_const__ read_cpuid_cachetype(void)
+{
+	return read_cpuid(ID_CTR_EL0);
+}
+
+#endif
diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h
new file mode 100644
index 0000000..520331b
--- /dev/null
+++ b/arch/arm64/include/asm/proc-fns.h
@@ -0,0 +1,51 @@
+/*
+ * Based on arch/arm/include/asm/proc-fns.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PROCFNS_H
+#define __ASM_PROCFNS_H
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#include <asm/page.h>
+
+struct mm_struct;
+
+extern void cpu_proc_init(void);
+extern void cpu_proc_fin(void);
+extern void cpu_do_idle(void);
+extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+
+#include <asm/memory.h>
+
+#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
+
+#define cpu_get_pgd()					\
+({							\
+	unsigned long pg;				\
+	asm("mrs	%0, ttbr0_el1\n"		\
+	    : "=r" (pg));				\
+	pg &= ~0xffff000000003ffful;			\
+	(pgd_t *)phys_to_virt(pg);			\
+})
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_PROCFNS_H */
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
new file mode 100644
index 0000000..ebf2b22
--- /dev/null
+++ b/arch/arm64/include/asm/processor.h
@@ -0,0 +1,174 @@
+/*
+ * Based on arch/arm/include/asm/processor.h
+ *
+ * Copyright (C) 1995-1999 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PROCESSOR_H
+#define __ASM_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include <linux/string.h>
+
+#include <asm/fpsimd.h>
+#include <asm/hw_breakpoint.h>
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX		TASK_SIZE_64
+#ifdef CONFIG_AARCH32_EMULATION
+#define AARCH32_VECTORS_BASE	0xffff0000
+#define STACK_TOP		(test_thread_flag(TIF_32BIT) ? \
+				AARCH32_VECTORS_BASE : STACK_TOP_MAX)
+#else
+#define STACK_TOP		STACK_TOP_MAX
+#endif /* CONFIG_AARCH32_EMULATION */
+#endif /* __KERNEL__ */
+
+struct debug_info {
+	/* Have we suspended stepping by a debugger? */
+	int			suspended_step;
+	/* Allow breakpoints and watchpoints to be disabled for this thread. */
+	int			bps_disabled;
+	int			wps_disabled;
+	/* Hardware breakpoints pinned to this task. */
+	struct perf_event	*hbp[ARM_MAX_HBP_SLOTS];
+};
+
+struct cpu_context {
+	unsigned long x19;
+	unsigned long x20;
+	unsigned long x21;
+	unsigned long x22;
+	unsigned long x23;
+	unsigned long x24;
+	unsigned long x25;
+	unsigned long x26;
+	unsigned long x27;
+	unsigned long x28;
+	unsigned long fp;
+	unsigned long sp;
+	unsigned long pc;
+};
+
+struct thread_struct {
+	struct cpu_context	cpu_context;	/* cpu context */
+	unsigned long		tp_value;
+	struct fpsimd_state	fpsimd_state;
+	unsigned long		fault_address;	/* fault info */
+	struct debug_info	debug;		/* debugging */
+};
+
+#define INIT_THREAD  {	}
+
+static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
+{
+	memset(regs, 0, sizeof(*regs));
+	regs->syscallno = ~0UL;
+	regs->pc = pc;
+}
+
+static inline void start_thread(struct pt_regs *regs, unsigned long pc,
+				unsigned long sp)
+{
+	unsigned long *stack = (unsigned long *)sp;
+
+	start_thread_common(regs, pc);
+	regs->pstate = PSR_MODE_EL0t;
+	regs->sp = sp;
+	regs->regs[2] = stack[2];	/* x2 (envp) */
+	regs->regs[1] = stack[1];	/* x1 (argv) */
+	regs->regs[0] = stack[0];	/* x0 (argc) */
+}
+
+#ifdef CONFIG_AARCH32_EMULATION
+static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
+				       unsigned long sp)
+{
+	unsigned int *stack = (unsigned int *)sp;
+
+	start_thread_common(regs, pc);
+	regs->pstate = COMPAT_PSR_MODE_USR;
+	if (pc & 1)
+		regs->pstate |= COMPAT_PSR_T_BIT;
+	regs->compat_sp = sp;
+	regs->regs[2] = stack[2];	/* x2 (envp) */
+	regs->regs[1] = stack[1];	/* x1 (argv) */
+	regs->regs[0] = stack[0];	/* x0 (argc) */
+}
+#endif
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)	do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()			barrier()
+
+/* Thread switching */
+extern struct task_struct *cpu_switch_to(struct task_struct *prev,
+					 struct task_struct *next);
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+#define task_pt_regs(p) \
+	((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
+
+#define KSTK_EIP(tsk)	task_pt_regs(tsk)->pc
+#define KSTK_ESP(tsk)	task_pt_regs(tsk)->sp
+
+/*
+ * Prefetching support
+ */
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *ptr)
+{
+	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
+}
+
+#define ARCH_HAS_PREFETCHW
+static inline void prefetchw(const void *ptr)
+{
+	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
+}
+
+#define ARCH_HAS_SPINLOCK_PREFETCH
+static inline void spin_lock_prefetch(const void *x)
+{
+	prefetchw(x);
+}
+
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+#endif
+
+#endif /* __ASM_PROCESSOR_H */
diff --git a/arch/arm64/include/asm/procinfo.h b/arch/arm64/include/asm/procinfo.h
new file mode 100644
index 0000000..81fece9
--- /dev/null
+++ b/arch/arm64/include/asm/procinfo.h
@@ -0,0 +1,44 @@
+/*
+ * Based on arch/arm/include/asm/procinfo.h
+ *
+ * Copyright (C) 1996-1999 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PROCINFO_H
+#define __ASM_PROCINFO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Note!  struct processor is always defined if we're
+ * using MULTI_CPU, otherwise this entry is unused,
+ * but still exists.
+ *
+ * NOTE! The following structure is defined by assembly
+ * language, NOT C code.  For more information, check:
+ *  arch/arm/mm/proc-*.S and arch/arm/kernel/head.S
+ */
+struct proc_info_list {
+	unsigned int		cpu_val;
+	unsigned int		cpu_mask;
+	unsigned long		__cpu_flush;		/* used by head.S */
+	const char		*cpu_name;
+};
+
+#else	/* __KERNEL__ */
+#include <asm/elf.h>
+#warning "Please include asm/elf.h instead"
+#endif	/* __KERNEL__ */
+#endif
diff --git a/arch/arm64/mm/proc-syms.c b/arch/arm64/mm/proc-syms.c
new file mode 100644
index 0000000..2d99ef9
--- /dev/null
+++ b/arch/arm64/mm/proc-syms.c
@@ -0,0 +1,31 @@
+/*
+ * Based on arch/arm/mm/proc-syms.c
+ *
+ * Copyright (C) 2000-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/mm.h>
+
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+
+EXPORT_SYMBOL(__cpuc_flush_kern_all);
+EXPORT_SYMBOL(__cpuc_flush_user_all);
+EXPORT_SYMBOL(__cpuc_flush_user_range);
+EXPORT_SYMBOL(__cpuc_coherent_kern_range);
+EXPORT_SYMBOL(__cpuc_flush_dcache_area);
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
new file mode 100644
index 0000000..453f517
--- /dev/null
+++ b/arch/arm64/mm/proc.S
@@ -0,0 +1,193 @@
+/*
+ * Based on arch/arm/mm/proc.S
+ *
+ * Copyright (C) 2001 Deep Blue Solutions Ltd.
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/hwcap.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+
+#include "proc-macros.S"
+
+#ifndef CONFIG_SMP
+/* PTWs cacheable, inner/outer WBWA not shareable */
+#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
+#else
+/* PTWs cacheable, inner/outer WBWA shareable */
+#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
+#endif
+
+#define MAIR(attr, mt)	((attr) << ((mt) * 8))
+
+ENTRY(cpu_proc_init)
+	ret
+ENDPROC(cpu_proc_init)
+
+ENTRY(cpu_proc_fin)
+	ret
+ENDPROC(cpu_proc_fin)
+
+/*
+ *	cpu_reset(loc)
+ *
+ *	Perform a soft reset of the system.  Put the CPU into the same state
+ *	as it would be if it had been reset, and branch to what would be the
+ *	reset vector. It must be executed with the flat identity mapping.
+ *
+ *	- loc   - location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_reset)
+	mrs	x1, sctlr_el1
+	bic	x1, x1, #1
+	msr	sctlr_el1, x1			// disable the MMU
+	isb
+	ret	x0
+ENDPROC(cpu_reset)
+
+/*
+ *	cpu_do_idle()
+ *
+ *	Idle the processor (wait for interrupt).
+ */
+ENTRY(cpu_do_idle)
+	dsb	sy				// WFI may enter a low-power mode
+	wfi
+	ret
+ENDPROC(cpu_do_idle)
+
+/*
+ *	cpu_switch_mm(pgd_phys, tsk)
+ *
+ *	Set the translation table base pointer to be pgd_phys.
+ *
+ *	- pgd_phys - physical address of new TTB
+ */
+ENTRY(cpu_do_switch_mm)
+	mmid	w1, x1				// get mm->context.id
+	bfi	x0, x1, #48, #16		// set the ASID
+	msr	ttbr0_el1, x0			// set TTBR0
+	isb
+	ret
+ENDPROC(cpu_do_switch_mm)
+
+cpu_name:
+	.ascii	"AArch64 Processor"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+/*
+ *	__cpu_setup
+ *
+ *	Initialise the processor for turning the MMU on.  Return in x0 the
+ *	value of the SCTLR_EL1 register.
+ */
+__cpu_setup:
+#ifdef CONFIG_SMP
+	/* TODO: only do this for certain CPUs */
+	/*
+	 * Enable SMP/nAMP mode.
+	 */
+	mrs	x0, actlr_el1
+	tbnz	x0, #6, 1f			// already enabled?
+	orr	x0, x0, #1 << 6
+	msr	actlr_el1, x0
+1:
+#endif
+	/*
+	 * Preserve the link register across the function call.
+	 */
+	mov	x28, lr
+	bl	__cpuc_flush_dcache_all
+	mov	lr, x28
+	ic	iallu				// I+BTB cache invalidate
+	dsb	sy
+
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0			// Enable FP/ASIMD
+	mov	x0, #1
+	msr	oslar_el1, x0			// Set the debug OS lock
+	tlbi	vmalle1is			// invalidate I + D TLBs
+	/*
+	 * Memory region attributes for LPAE:
+	 *
+	 *   n = AttrIndx[2:0]
+	 *			n	MAIR
+	 *   DEVICE_nGnRnE	000	00000000
+	 *   DEVICE_nGnRE	001	00000100
+	 *   DEVICE_GRE		010	00001100
+	 *   NORMAL_NC		011	01000100
+	 *   NORMAL		100	11111111
+	 */
+	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
+		     MAIR(0x04, MT_DEVICE_nGnRE) | \
+		     MAIR(0x0c, MT_DEVICE_GRE) | \
+		     MAIR(0x44, MT_NORMAL_NC) | \
+		     MAIR(0xff, MT_NORMAL)
+	msr	mair_el1, x5
+	/*
+	 * Prepare SCTLR
+	 */
+	adr	x5, crval
+	ldp	w5, w6, [x5]
+	mrs	x0, sctlr_el1
+	bic	x0, x0, x5			// clear bits
+	orr	x0, x0, x6			// set bits
+	/*
+	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
+	 * both user and kernel.
+	 */
+	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
+		      TCR_ASID16 | (1 << 31)
+#ifdef CONFIG_ARM64_64K_PAGES
+	orr	x10, x10, TCR_TG0_64K
+	orr	x10, x10, TCR_TG1_64K
+#endif
+	msr	tcr_el1, x10
+	ret					// return to head.S
+ENDPROC(__cpu_setup)
+
+	/*
+	 *                 n n            T
+	 *       U E      WT T UD     US IHBS
+	 *       CE0      XWHW CZ     ME TEEA S
+	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
+	 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
+	 * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
+	 */
+	.type	crval, #object
+crval:
+	.word	0x030802e2			// clear
+	.word	0x0405d11d			// set
+
+	.section ".proc.info.init", #alloc, #execinstr
+
+	.type	__v8_proc_info, #object
+__v8_proc_info:
+	.long	0x000f0000			// Required ID value
+	.long	0x000f0000			// Mask for ID
+	b	__cpu_setup
+	nop
+	.quad	cpu_name
+	.long	0
+	.size	__v8_proc_info, . - __v8_proc_info



From catalin.marinas at arm.com  Tue Aug 14 13:52:18 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:18 +0100
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-18-git-send-email-catalin.marinas@arm.com>

This patch adds support for system calls coming from 64-bit
applications. It uses the asm-generic/unistd.h definitions with the
canonical set of system calls. The private system calls are only used
for 32-bit (compat) applications as 64-bit ones can set the TLS and
flush the caches entirely from user space.

The sys_call_table is just an array defined in a C file and it contains
pointers to the syscall functions. The array is 4KB aligned to allow the
use of the ADRP instruction (longer range ADR) in entry.S.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/stat.h     |   63 +++++++++++++++++
 arch/arm64/include/asm/statfs.h   |   23 ++++++
 arch/arm64/include/asm/syscalls.h |   40 +++++++++++
 arch/arm64/include/asm/unistd.h   |   27 +++++++
 arch/arm64/kernel/sys.c           |  138 +++++++++++++++++++++++++++++++++++++
 5 files changed, 291 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/stat.h
 create mode 100644 arch/arm64/include/asm/statfs.h
 create mode 100644 arch/arm64/include/asm/syscalls.h
 create mode 100644 arch/arm64/include/asm/unistd.h
 create mode 100644 arch/arm64/kernel/sys.c

diff --git a/arch/arm64/include/asm/stat.h b/arch/arm64/include/asm/stat.h
new file mode 100644
index 0000000..f63a680
--- /dev/null
+++ b/arch/arm64/include/asm/stat.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_STAT_H
+#define __ASM_STAT_H
+
+#include <asm-generic/stat.h>
+
+#if defined(__KERNEL__) && defined(CONFIG_AARCH32_EMULATION)
+
+#include <asm/compat.h>
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ * Note: The kernel zero's the padded region because glibc might read them
+ * in the hope that the kernel has stretched to using larger sizes.
+ */
+struct stat64 {
+	compat_u64	st_dev;
+	unsigned char   __pad0[4];
+
+#define STAT64_HAS_BROKEN_ST_INO	1
+	compat_ulong_t	__st_ino;
+	compat_uint_t	st_mode;
+	compat_uint_t	st_nlink;
+
+	compat_ulong_t	st_uid;
+	compat_ulong_t	st_gid;
+
+	compat_u64	st_rdev;
+	unsigned char   __pad3[4];
+
+	compat_s64	st_size;
+	compat_ulong_t	st_blksize;
+	compat_u64	st_blocks;	/* Number 512-byte blocks allocated. */
+
+	compat_ulong_t	st_atime;
+	compat_ulong_t	st_atime_nsec;
+
+	compat_ulong_t	st_mtime;
+	compat_ulong_t	st_mtime_nsec;
+
+	compat_ulong_t	st_ctime;
+	compat_ulong_t	st_ctime_nsec;
+
+	compat_u64	st_ino;
+};
+
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/statfs.h b/arch/arm64/include/asm/statfs.h
new file mode 100644
index 0000000..6f62190
--- /dev/null
+++ b/arch/arm64/include/asm/statfs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_STATFS_H
+#define __ASM_STATFS_H
+
+#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
+
+#include <asm-generic/statfs.h>
+
+#endif
diff --git a/arch/arm64/include/asm/syscalls.h b/arch/arm64/include/asm/syscalls.h
new file mode 100644
index 0000000..09ff335
--- /dev/null
+++ b/arch/arm64/include/asm/syscalls.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SYSCALLS_H
+#define __ASM_SYSCALLS_H
+
+#include <linux/linkage.h>
+#include <linux/compiler.h>
+#include <linux/signal.h>
+
+/*
+ * System call wrappers implemented in kernel/entry.S.
+ */
+asmlinkage long sys_execve_wrapper(const char __user *filename,
+				   const char __user *const __user *argv,
+				   const char __user *const __user *envp);
+asmlinkage long sys_clone_wrapper(unsigned long clone_flags,
+				  unsigned long newsp,
+				  void __user *parent_tid,
+				  unsigned long tls_val,
+				  void __user *child_tid);
+asmlinkage long sys_rt_sigreturn_wrapper(void);
+asmlinkage long sys_sigaltstack_wrapper(const stack_t __user *uss,
+					stack_t __user *uoss);
+
+#include <asm-generic/syscalls.h>
+
+#endif	/* __ASM_SYSCALLS_H */
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
new file mode 100644
index 0000000..b00718c
--- /dev/null
+++ b/arch/arm64/include/asm/unistd.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#if !defined(__ASM_UNISTD_H) || defined(__SYSCALL)
+#define __ASM_UNISTD_H
+
+#ifndef __SYSCALL_COMPAT
+#include <asm-generic/unistd.h>
+#endif
+
+#if defined(__KERNEL__) && defined(CONFIG_AARCH32_EMULATION)
+#include <asm/unistd32.h>
+#endif
+
+#endif /* __ASM_UNISTD_H */
diff --git a/arch/arm64/kernel/sys.c b/arch/arm64/kernel/sys.c
new file mode 100644
index 0000000..905fcfb
--- /dev/null
+++ b/arch/arm64/kernel/sys.c
@@ -0,0 +1,138 @@
+/*
+ * AArch64-specific system calls implementation
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/syscalls.h>
+
+/*
+ * Clone a task - this clones the calling program thread.
+ */
+asmlinkage long sys_clone(unsigned long clone_flags, unsigned long newsp,
+			  int __user *parent_tidptr, unsigned long tls_val,
+			  int __user *child_tidptr, struct pt_regs *regs)
+{
+	if (!newsp)
+		newsp = regs->sp;
+	/* 16-byte aligned stack mandatory on AArch64 */
+	if (newsp & 15)
+		return -EINVAL;
+	return do_fork(clone_flags, newsp, regs, 0, parent_tidptr, child_tidptr);
+}
+
+/*
+ * sys_execve() executes a new program.
+ */
+asmlinkage long sys_execve(const char __user *filenamei,
+			   const char __user *const __user *argv,
+			   const char __user *const __user *envp,
+			   struct pt_regs *regs)
+{
+	long error;
+	char * filename;
+
+	filename = getname(filenamei);
+	error = PTR_ERR(filename);
+	if (IS_ERR(filename))
+		goto out;
+	error = do_execve(filename, argv, envp, regs);
+	putname(filename);
+out:
+	return error;
+}
+
+int kernel_execve(const char *filename,
+		  const char *const argv[],
+		  const char *const envp[])
+{
+	struct pt_regs regs;
+	int ret;
+
+	memset(&regs, 0, sizeof(struct pt_regs));
+	ret = do_execve(filename,
+			(const char __user *const __user *)argv,
+			(const char __user *const __user *)envp, &regs);
+	if (ret < 0)
+		goto out;
+
+	/*
+	 * Save argc to the register structure for userspace.
+	 */
+	regs.regs[0] = ret;
+
+	/*
+	 * We were successful.  We won't be returning to our caller, but
+	 * instead to user space by manipulating the kernel stack.
+	 */
+	asm(	"add	x0, %0, %1\n\t"
+		"mov	x1, %2\n\t"
+		"mov	x2, %3\n\t"
+		"bl	memmove\n\t"	/* copy regs to top of stack */
+		"mov	x27, #0\n\t"	/* not a syscall */
+		"mov	x28, %0\n\t"	/* thread structure */
+		"mov	sp, x0\n\t"	/* reposition stack pointer */
+		"b	ret_to_user"
+		:
+		: "r" (current_thread_info()),
+		  "Ir" (THREAD_START_SP - sizeof(regs)),
+		  "r" (&regs),
+		  "Ir" (sizeof(regs))
+		: "x0", "x1", "x2", "x27", "x28", "x30", "memory");
+
+ out:
+	return ret;
+}
+EXPORT_SYMBOL(kernel_execve);
+
+asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
+			 unsigned long prot, unsigned long flags,
+			 unsigned long fd, off_t off)
+{
+	if (offset_in_page(off) != 0)
+		return -EINVAL;
+
+	return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+}
+
+/*
+ * Wrappers to pass the pt_regs argument.
+ */
+#define sys_execve		sys_execve_wrapper
+#define sys_clone		sys_clone_wrapper
+#define sys_rt_sigreturn	sys_rt_sigreturn_wrapper
+#define sys_sigaltstack		sys_sigaltstack_wrapper
+
+#include <asm/syscalls.h>
+
+#undef __SYSCALL
+#define __SYSCALL(nr, sym)	[nr] = sym,
+
+/*
+ * The sys_call_table array must be 4K aligned to be accessible from
+ * kernel/entry.S.
+ */
+void *sys_call_table[__NR_syscalls] __aligned(4096) = {
+	[0 ... __NR_syscalls - 1] = sys_ni_syscall,
+#include <asm/unistd.h>
+};



From catalin.marinas at arm.com  Tue Aug 14 13:52:15 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:15 +0100
Subject: [PATCH v2 14/31] arm64: DMA mapping API
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>

This patch adds support for the DMA mapping API. It uses dma_map_ops for
flexibility and it currently supports swiotlb. This patch could be
simplified further if the DMA accesses are coherent (not mandated by the
architecture) or if corresponding hooks are placed in the generic
swiotlb code to deal with cache maintenance.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/dma-mapping.h |  124 ++++++++++++++++++++
 arch/arm64/mm/dma-mapping.c          |  208 ++++++++++++++++++++++++++++++++++
 2 files changed, 332 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/dma-mapping.h
 create mode 100644 arch/arm64/mm/dma-mapping.c

diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
new file mode 100644
index 0000000..538f4b4
--- /dev/null
+++ b/arch/arm64/include/asm/dma-mapping.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_DMA_MAPPING_H
+#define __ASM_DMA_MAPPING_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/vmalloc.h>
+
+#include <asm-generic/dma-coherent.h>
+
+#define ARCH_HAS_DMA_GET_REQUIRED_MASK
+
+extern struct dma_map_ops *dma_ops;
+
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+	if (unlikely(!dev) || !dev->archdata.dma_ops)
+		return dma_ops;
+	else
+		return dev->archdata.dma_ops;
+}
+
+#include <asm-generic/dma-mapping-common.h>
+
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+	return (dma_addr_t)paddr;
+}
+
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
+{
+	return (phys_addr_t)dev_addr;
+}
+
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dev_addr)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	return ops->mapping_error(dev, dev_addr);
+}
+
+static inline int dma_supported(struct device *dev, u64 mask)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	return ops->dma_supported(dev, mask);
+}
+
+static inline int dma_set_mask(struct device *dev, u64 mask)
+{
+	if (!dev->dma_mask || !dma_supported(dev, mask))
+		return -EIO;
+	*dev->dma_mask = mask;
+
+	return 0;
+}
+
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+	if (!dev->dma_mask)
+		return 0;
+
+	return addr + size - 1 <= *dev->dma_mask;
+}
+
+static inline void dma_mark_clean(void *addr, size_t size)
+{
+}
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+				       dma_addr_t *dma_handle, gfp_t flags)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	void *vaddr;
+
+	if (dma_alloc_from_coherent(dev, size, dma_handle, &vaddr))
+		return vaddr;
+
+	vaddr = ops->alloc(dev, size, dma_handle, flags, NULL);
+	debug_dma_alloc_coherent(dev, size, *dma_handle, vaddr);
+	return vaddr;
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+				     void *vaddr, dma_addr_t dev_addr)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+
+	if (dma_release_from_coherent(dev, get_order(size), vaddr))
+		return;
+
+	debug_dma_free_coherent(dev, size, vaddr, dev_addr);
+	ops->free(dev, size, vaddr, dev_addr, NULL);
+}
+
+/*
+ * There is no dma_cache_sync() implementation, so just return NULL here.
+ */
+static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
+					  dma_addr_t *handle, gfp_t flags)
+{
+	return NULL;
+}
+
+static inline void dma_free_noncoherent(struct device *dev, size_t size,
+					void *cpu_addr, dma_addr_t handle)
+{
+}
+
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_DMA_MAPPING_H */
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
new file mode 100644
index 0000000..4e5871d
--- /dev/null
+++ b/arch/arm64/mm/dma-mapping.c
@@ -0,0 +1,208 @@
+/*
+ * SWIOTLB-based DMA API implementation
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/gfp.h>
+#include <linux/export.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
+#include <linux/swiotlb.h>
+
+#include <asm/cacheflush.h>
+
+struct dma_map_ops *dma_ops;
+EXPORT_SYMBOL(dma_ops);
+
+static void *arm64_swiotlb_alloc_coherent(struct device *dev, size_t size,
+					  dma_addr_t *dma_handle, gfp_t flags,
+					  struct dma_attrs *attrs)
+{
+	struct page *page, **map;
+	void *ptr;
+	int order = get_order(size);
+	int i;
+
+	if (dev->coherent_dma_mask != DMA_BIT_MASK(64))
+		flags |= GFP_DMA;
+
+	ptr = swiotlb_alloc_coherent(dev, size, dma_handle, flags);
+	if (!ptr)
+		goto no_mem;
+	map = kmalloc(sizeof(struct page *) << order, flags & ~GFP_DMA);
+	if (!map)
+		goto no_map;
+
+	/* remove any dirty cache lines on the kernel alias */
+	dmac_flush_range(ptr, ptr + size);
+
+	/* create a coherent mapping */
+	page = virt_to_page(ptr);
+	for (i = 0; i < (size >> PAGE_SHIFT); i++)
+		map[i] = page + i;
+	ptr = vmap(map, size >> PAGE_SHIFT, VM_MAP,
+		   pgprot_dmacoherent(pgprot_default)); kfree(map);
+	if (!ptr)
+		goto no_map;
+
+	return ptr;
+
+no_map:
+	swiotlb_free_coherent(dev, size, ptr, *dma_handle);
+no_mem:
+	*dma_handle = ~0;
+	return NULL;
+}
+
+static void arm64_swiotlb_free_coherent(struct device *dev, size_t size,
+					void *vaddr, dma_addr_t dma_handle,
+					struct dma_attrs *attrs)
+{
+	vunmap(vaddr);
+	swiotlb_free_coherent(dev, size, vaddr, dma_handle);
+}
+
+static dma_addr_t arm64_swiotlb_map_page(struct device *dev,
+					 struct page *page,
+					 unsigned long offset, size_t size,
+					 enum dma_data_direction dir,
+					 struct dma_attrs *attrs)
+{
+	dma_addr_t dev_addr;
+
+	dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs);
+	dmac_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
+
+	return dev_addr;
+}
+
+
+static void arm64_swiotlb_unmap_page(struct device *dev, dma_addr_t dev_addr,
+				     size_t size, enum dma_data_direction dir,
+				     struct dma_attrs *attrs)
+{
+	dmac_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
+	swiotlb_unmap_page(dev, dev_addr, size, dir, attrs);
+}
+
+static int arm64_swiotlb_map_sg_attrs(struct device *dev,
+				      struct scatterlist *sgl, int nelems,
+				      enum dma_data_direction dir,
+				      struct dma_attrs *attrs)
+{
+	struct scatterlist *sg;
+	int i, ret;
+
+	ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs);
+	for_each_sg(sgl, sg, ret, i)
+		dmac_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
+			      sg->length, dir);
+
+	return ret;
+}
+
+static void arm64_swiotlb_unmap_sg_attrs(struct device *dev,
+					 struct scatterlist *sgl, int nelems,
+					 enum dma_data_direction dir,
+					 struct dma_attrs *attrs)
+{
+	struct scatterlist *sg;
+	int i;
+
+	for_each_sg(sgl, sg, nelems, i)
+		dmac_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
+				sg->length, dir);
+	swiotlb_unmap_sg_attrs(dev, sgl, nelems, dir, attrs);
+}
+
+static void arm64_swiotlb_sync_single_for_cpu(struct device *dev,
+					      dma_addr_t dev_addr,
+					      size_t size,
+					      enum dma_data_direction dir)
+{
+	dmac_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
+	swiotlb_sync_single_for_cpu(dev, dev_addr, size, dir);
+}
+
+static void arm64_swiotlb_sync_single_for_device(struct device *dev,
+						 dma_addr_t dev_addr,
+						 size_t size,
+						 enum dma_data_direction dir)
+{
+	swiotlb_sync_single_for_device(dev, dev_addr, size, dir);
+	dmac_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
+}
+
+static void arm64_swiotlb_sync_sg_for_cpu(struct device *dev,
+					  struct scatterlist *sgl, int nelems,
+					  enum dma_data_direction dir)
+{
+	struct scatterlist *sg;
+	int i;
+
+	for_each_sg(sgl, sg, nelems, i)
+		dmac_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
+				sg->length, dir);
+	swiotlb_sync_sg_for_cpu(dev, sgl, nelems, dir);
+}
+
+static void arm64_swiotlb_sync_sg_for_device(struct device *dev,
+					     struct scatterlist *sgl,
+					     int nelems,
+					     enum dma_data_direction dir)
+{
+	struct scatterlist *sg;
+	int i;
+
+	swiotlb_sync_sg_for_device(dev, sgl, nelems, dir);
+	for_each_sg(sgl, sg, nelems, i)
+		dmac_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
+			      sg->length, dir);
+}
+
+static struct dma_map_ops arm64_swiotlb_dma_ops = {
+	.alloc = arm64_swiotlb_alloc_coherent,
+	.free = arm64_swiotlb_free_coherent,
+	.map_page = arm64_swiotlb_map_page,
+	.unmap_page = arm64_swiotlb_unmap_page,
+	.map_sg = arm64_swiotlb_map_sg_attrs,
+	.unmap_sg = arm64_swiotlb_unmap_sg_attrs,
+	.sync_single_for_cpu = arm64_swiotlb_sync_single_for_cpu,
+	.sync_single_for_device = arm64_swiotlb_sync_single_for_device,
+	.sync_sg_for_cpu = arm64_swiotlb_sync_sg_for_cpu,
+	.sync_sg_for_device = arm64_swiotlb_sync_sg_for_device,
+	.dma_supported = swiotlb_dma_supported,
+	.mapping_error = swiotlb_dma_mapping_error,
+};
+
+void __init swiotlb_init_with_default_size(size_t default_size, int verbose);
+
+void __init arm64_swiotlb_init(size_t max_size)
+{
+	dma_ops = &arm64_swiotlb_dma_ops;
+	swiotlb_init_with_default_size(min((size_t)SZ_64M, max_size), 1);
+}
+
+#define PREALLOC_DMA_DEBUG_ENTRIES	4096
+
+static int __init dma_debug_do_init(void)
+{
+	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+	return 0;
+}
+fs_initcall(dma_debug_do_init);



From catalin.marinas at arm.com  Tue Aug 14 13:52:03 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:03 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>

The patch adds the kernel booting and the initial setup code.
Documentation/arm64/booting.txt describes the booting protocol on the
AArch64 Linux kernel. This is subject to change following the work on
boot standardisation, ACPI.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 Documentation/arm64/booting.txt |  141 +++++++++++
 arch/arm64/include/asm/setup.h  |   26 ++
 arch/arm64/kernel/head.S        |  521 +++++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/setup.c       |  357 +++++++++++++++++++++++++++
 4 files changed, 1045 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/arm64/booting.txt
 create mode 100644 arch/arm64/include/asm/setup.h
 create mode 100644 arch/arm64/kernel/head.S
 create mode 100644 arch/arm64/kernel/setup.c

diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt
new file mode 100644
index 0000000..3197820
--- /dev/null
+++ b/Documentation/arm64/booting.txt
@@ -0,0 +1,141 @@
+			Booting AArch64 Linux
+			=====================
+
+Author: Will Deacon <will.deacon at arm.com>
+Date  : 25 April 2012
+
+This document is based on the ARM booting document by Russell King and
+is relevant to all public releases of the AArch64 Linux kernel.
+
+The AArch64 exception model is made up of a number of exception levels
+(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
+counterpart.  EL2 is the hypervisor level and exists only in non-secure
+mode. EL3 is the highest priority level and exists only in secure mode.
+
+For the purposes of this document, we will use the term `boot loader'
+simply to define all software that executes on the CPU(s) before control
+is passed to the Linux kernel.  This may include secure monitor and
+hypervisor code, or it may just be a handful of instructions for
+preparing a minimal boot environment.
+
+Essentially, the boot loader should provide (as a minimum) the
+following:
+
+1. Setup and initialise the RAM
+2. Setup the device tree
+3. Decompress the kernel image
+4. Call the kernel image
+
+
+1. Setup and initialise RAM
+---------------------------
+
+Requirement: MANDATORY
+
+The boot loader is expected to find and initialise all RAM that the
+kernel will use for volatile data storage in the system.  It performs
+this in a machine dependent manner.  (It may use internal algorithms
+to automatically locate and size all RAM, or it may use knowledge of
+the RAM in the machine, or any other method the boot loader designer
+sees fit.)
+
+
+2. Setup the device tree
+-------------------------
+
+Requirement: MANDATORY
+
+The device tree blob (dtb) must be no bigger than 2 megabytes in size
+and placed at a 2-megabyte boundary within the first 512 megabytes from
+the start of the kernel image. This is to allow the kernel to map the
+blob using a single section mapping in the initial page tables.
+
+
+3. Decompress the kernel image
+------------------------------
+
+Requirement: OPTIONAL
+
+The AArch64 kernel does not provide a decompressor and therefore
+requires gzip decompression to be performed by the boot loader if the
+default Image.gz target is used.  For bootloaders that do not implement
+this requirement, the larger Image target is available instead.
+
+
+4. Call the kernel image
+------------------------
+
+Requirement: MANDATORY
+
+The decompressed kernel image contains a 32-byte header as follows:
+
+  u32 magic	= 0x14000008;	/* branch to stext, little-endian */
+  u32 res0	= 0;		/* reserved */
+  u64 text_offset;		/* Image load offset */
+  u64 res1	= 0;		/* reserved */
+  u64 res2	= 0;		/* reserved */
+
+The image must be placed at the specified offset (currently 0x80000)
+from the start of the system RAM and called there. The start of the
+system RAM must be aligned to 2MB.
+
+Before jumping into the kernel, the following conditions must be met:
+
+- Quiesce all DMA capable devices so that memory does not get
+  corrupted by bogus network packets or disk data.  This will save
+  you many hours of debug.
+
+- Primary CPU general-purpose register settings
+  x0 = physical address of device tree blob (dtb) in system RAM.
+
+- CPU mode
+  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
+  IRQ and FIQ).
+  The CPU must be in either EL2 (RECOMMENDED in order to have access to
+  the virtualisation extensions) or non-secure EL1.
+
+- Caches, MMUs
+  The MMU must be off.
+  Instruction cache may be on or off.
+  Data cache must be off and invalidated.
+
+- Architected timers
+  CNTFRQ must be programmed with the timer frequency.
+  If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
+  set where available.
+
+- Coherency
+  All CPUs to be booted by the kernel must be part of the same coherency
+  domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
+  initialisation to enable the receiving of maintenance operations on
+  each CPU.
+
+- System registers
+  All writable architected system registers at the exception level where
+  the kernel image will be entered must be initialised by software at a
+  higher exception level to prevent execution in an UNKNOWN state.
+
+The boot loader is expected to enter the kernel on each CPU in the
+following manner:
+
+- The primary CPU must jump directly to the first instruction of the
+  kernel image.  The device tree blob passed by this CPU must contain
+  for each CPU node:
+
+    1. An 'enable-method' property. Currently, the only supported value
+       for this field is the string "spin-table".
+
+    2. A 'cpu-release-addr' property identifying a 64-bit,
+       zero-initialised memory location.
+
+  It is expected that the bootloader will generate these device tree
+  properties and insert them into the blob prior to kernel entry.
+
+- Any secondary CPUs must spin outside of the kernel in a reserved area
+  of memory (communicated to the kernel by a /memreserve/ region in the
+  device tree) polling their cpu-release-addr location, which must be
+  contained in the reserved region.  A wfe instruction may be inserted
+  to reduce the overhead of the busy-loop and a sev will be issued by
+  the primary CPU.  When a read of the location pointed to by the
+  cpu-release-addr returns a non-zero value, the CPU must jump directly
+  to this value.
diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h
new file mode 100644
index 0000000..d766493
--- /dev/null
+++ b/arch/arm64/include/asm/setup.h
@@ -0,0 +1,26 @@
+/*
+ * Based on arch/arm/include/asm/setup.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SETUP_H
+#define __ASM_SETUP_H
+
+#include <linux/types.h>
+
+#define COMMAND_LINE_SIZE 1024
+
+#endif
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
new file mode 100644
index 0000000..34ccdc0
--- /dev/null
+++ b/arch/arm64/kernel/head.S
@@ -0,0 +1,521 @@
+/*
+ * Low-level CPU initialisation
+ * Based on arch/arm/kernel/head.S
+ *
+ * Copyright (C) 1994-2002 Russell King
+ * Copyright (C) 2003-2012 ARM Ltd.
+ * Authors:	Catalin Marinas <catalin.marinas at arm.com>
+ *		Will Deacon <will.deacon at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+#include <asm/assembler.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/memory.h>
+#include <asm/thread_info.h>
+#include <asm/pgtable-hwdef.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+/*
+ * swapper_pg_dir is the virtual address of the initial page table. We place
+ * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
+ * 2 pages and is placed below swapper_pg_dir.
+ */
+#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
+
+#if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
+#error KERNEL_RAM_VADDR must start at 0xXXX80000
+#endif
+
+#define SWAPPER_DIR_SIZE	(3 * PAGE_SIZE)
+#define IDMAP_DIR_SIZE		(2 * PAGE_SIZE)
+
+	.globl	swapper_pg_dir
+	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
+
+	.globl	idmap_pg_dir
+	.equ	idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
+
+	.macro	pgtbl, ttb0, ttb1, phys
+	add	\ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
+	sub	\ttb0, \ttb1, #IDMAP_DIR_SIZE
+	.endm
+
+#ifdef CONFIG_ARM64_64K_PAGES
+#define BLOCK_SHIFT	PAGE_SHIFT
+#define BLOCK_SIZE	PAGE_SIZE
+#else
+#define BLOCK_SHIFT	SECTION_SHIFT
+#define BLOCK_SIZE	SECTION_SIZE
+#endif
+
+#define KERNEL_START	KERNEL_RAM_VADDR
+#define KERNEL_END	_end
+
+/*
+ * Initial memory map attributes.
+ */
+#ifndef CONFIG_SMP
+#define PTE_FLAGS	PTE_ATTRINDX(MT_NORMAL) | PTE_AF
+#define PMD_FLAGS	PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_AF
+#else
+#define PTE_FLAGS	PTE_ATTRINDX(MT_NORMAL) | PTE_AF | PTE_SHARED
+#define PMD_FLAGS	PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_AF | PMD_SECT_S
+#endif
+
+#ifdef CONFIG_ARM64_64K_PAGES
+#define MM_MMUFLAGS	PTE_TYPE_PAGE | PTE_FLAGS
+#define IO_MMUFLAGS	PTE_TYPE_PAGE | PTE_XN | PTE_FLAGS
+#else
+#define MM_MMUFLAGS	PMD_TYPE_SECT | PMD_FLAGS
+#define IO_MMUFLAGS	PMD_TYPE_SECT | PMD_SECT_XN | PMD_FLAGS
+#endif
+
+/*
+ * Kernel startup entry point.
+ * ---------------------------
+ *
+ * The requirements are:
+ *   MMU = off, D-cache = off, I-cache = on or off,
+ *   x0 = physical address to the FDT blob.
+ *
+ * This code is mostly position independent so you call this at
+ * __pa(PAGE_OFFSET + TEXT_OFFSET).
+ *
+ * Note that the callee-saved registers are used for storing variables
+ * that are useful before the MMU is enabled. The allocations are described
+ * in the entry routines.
+ */
+	__HEAD
+
+	/*
+	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
+	 */
+	b	stext				// branch to kernel start, magic
+	.long	0				// reserved
+	.quad	TEXT_OFFSET			// Image load offset from start of RAM
+	.quad	0				// reserved
+	.quad	0				// reserved
+
+ENTRY(stext)
+	mov	x21, x0				// x21=FDT
+	bl	el2_setup			// Drop to EL1
+	mrs	x22, midr_el1			// x22=cpuid
+	mov	x0, x22
+	bl	__lookup_processor_type
+	mov	x23, x0				// x23=procinfo
+	cbz	x23, __error_p			// invalid processor (x23=0)?
+	bl	__calc_phys_offset		// x24=phys offset
+	bl	__vet_fdt
+	bl	__create_page_tables		// x25=TTBR0, x26=TTBR1
+	/*
+	 * The following calls CPU specific code in a position independent
+	 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
+	 * cpu_proc_info structure selected by __lookup_processor_type above.
+	 * On return, the CPU will be ready for the MMU to be turned on and
+	 * the TCR will have been set.
+	 */
+	ldr	x27, __switch_data		// address to jump to after
+						// MMU has been enabled
+	adr	lr, __enable_mmu		// return (PIC) address
+	add	x12, x23, #PROCINFO_INITFUNC
+	br	x12				// initialise processor
+ENDPROC(stext)
+
+/*
+ * If we're fortunate enough to boot at EL2, ensure that the world is
+ * sane before dropping to EL1.
+ */
+ENTRY(el2_setup)
+	mrs	x0, CurrentEL
+	cmp	x0, #PSR_MODE_EL2t
+	ccmp	x0, #PSR_MODE_EL2h, #0x4, ne
+	b.eq	1f
+	ret
+
+	/* Hyp configuration. */
+1:	mov	x0, #(1 << 31)			// 64-bit EL1
+	msr	hcr_el2, x0
+
+	/* Generic timers. */
+	mrs	x0, cnthctl_el2
+	orr	x0, x0, #3			// Enable EL1 physical timers
+	msr	cnthctl_el2, x0
+
+	/* Populate ID registers. */
+	mrs	x0, midr_el1
+	mrs	x1, mpidr_el1
+	msr	vpidr_el2, x0
+	msr	vmpidr_el2, x1
+
+	/* sctlr_el1 */
+	mov	x0, #0x0800			// Set/clear RES{1,0} bits
+	movk	x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	/* Coprocessor traps. */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0			// Disable copro. traps to EL2
+
+#ifdef CONFIG_AARCH32_EMULATION
+	msr	hstr_el2, xzr			// Disable CP15 traps to EL2
+#endif
+
+	/* spsr */
+	mov	x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
+		      PSR_MODE_EL1h)
+	msr	spsr_el2, x0
+	msr	elr_el2, lr
+	eret
+ENDPROC(el2_setup)
+
+	.align	3
+2:	.quad	.
+	.quad	PAGE_OFFSET
+
+#ifdef CONFIG_SMP
+	.pushsection    .smp.pen.text, "ax"
+	.align	3
+1:	.quad	.
+	.quad	secondary_holding_pen_release
+
+	/*
+	 * This provides a "holding pen" for platforms to hold all secondary
+	 * cores are held until we're ready for them to initialise.
+	 */
+ENTRY(secondary_holding_pen)
+	bl	el2_setup			// Drop to EL1
+	mrs	x0, mpidr_el1
+	and	x0, x0, #15			// CPU number
+	adr	x1, 1b
+	ldp	x2, x3, [x1]
+	sub	x1, x1, x2
+	add	x3, x3, x1
+pen:	ldr	x4, [x3]
+	cmp	x4, x0
+	b.eq	secondary_startup
+	wfe
+	b	pen
+ENDPROC(secondary_holding_pen)
+	.popsection
+
+ENTRY(secondary_startup)
+	/*
+	 * Common entry point for secondary CPUs.
+	 */
+	mrs	x22, midr_el1			// x22=cpuid
+	mov	x0, x22
+	bl	__lookup_processor_type
+	mov	x23, x0				// x23=procinfo
+	cbz	x23, __error_p			// invalid processor (x23=0)?
+
+	bl	__calc_phys_offset		// x24=phys offset
+	pgtbl	x25, x26, x24			// x25=TTBR0, x26=TTBR1
+	add	x12, x23, #PROCINFO_INITFUNC
+	blr	x12				// initialise processor
+
+	ldr	x21, =secondary_data
+	ldr	x27, =__secondary_switched	// address to jump to after enabling the MMU
+	b	__enable_mmu
+ENDPROC(secondary_startup)
+
+ENTRY(__secondary_switched)
+	ldr	x0, [x21]			// get secondary_data.stack
+	mov	sp, x0
+	mov	x29, #0
+	b	secondary_start_kernel
+ENDPROC(__secondary_switched)
+#endif	/* CONFIG_SMP */
+
+/*
+ * Setup common bits before finally enabling the MMU. Essentially this is just
+ * loading the page table pointer and vector base registers.
+ *
+ * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
+ * the MMU.
+ */
+__enable_mmu:
+	ldr	x5, =vectors
+	msr	vbar_el1, x5
+	msr	ttbr0_el1, x25			// load TTBR0
+	msr	ttbr1_el1, x26			// load TTBR1
+	isb
+	b	__turn_mmu_on
+ENDPROC(__enable_mmu)
+
+/*
+ * Enable the MMU. This completely changes the structure of the visible memory
+ * space. You will not be able to trace execution through this.
+ *
+ *  x0  = system control register
+ *  x27 = *virtual* address to jump to upon completion
+ *
+ * other registers depend on the function called upon completion
+ */
+	.align	6
+__turn_mmu_on:
+	msr	sctlr_el1, x0
+	isb
+	br	x27
+ENDPROC(__turn_mmu_on)
+
+/*
+ * Calculate the start of physical memory.
+ */
+__calc_phys_offset:
+	adr	x0, 1f
+	ldp	x1, x2, [x0]
+	sub	x3, x0, x1			// PHYS_OFFSET - PAGE_OFFSET
+	add	x24, x2, x3			// x24=PHYS_OFFSET
+	ret
+ENDPROC(__calc_phys_offset)
+
+	.align 3
+1:	.quad	.
+	.quad	PAGE_OFFSET
+
+/*
+ * Macro to populate the PGD for the corresponding block entry in the next
+ * level (tbl) for the given virtual address.
+ *
+ * Preserves:	pgd, tbl, virt
+ * Corrupts:	tmp1, tmp2
+ */
+	.macro	create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
+	lsr	\tmp1, \virt, #PGDIR_SHIFT
+	and	\tmp1, \tmp1, #PTRS_PER_PGD - 1	// PGD index
+	orr	\tmp2, \tbl, #3			// PGD entry table type
+	str	\tmp2, [\pgd, \tmp1, lsl #3]
+	.endm
+
+/*
+ * Macro to populate block entries in the page table for the start..end
+ * virtual range (inclusive).
+ *
+ * Preserves:	tbl, flags
+ * Corrupts:	phys, start, end, pstate
+ */
+	.macro	create_block_map, tbl, flags, phys, start, end, idmap=0
+	lsr	\phys, \phys, #BLOCK_SHIFT
+	.if	\idmap
+	and	\start, \phys, #PTRS_PER_PTE - 1	// table index
+	.else
+	lsr	\start, \start, #BLOCK_SHIFT
+	and	\start, \start, #PTRS_PER_PTE - 1	// table index
+	.endif
+	orr	\phys, \flags, \phys, lsl #BLOCK_SHIFT	// table entry
+	.ifnc	\start,\end
+	lsr	\end, \end, #BLOCK_SHIFT
+	and	\end, \end, #PTRS_PER_PTE - 1		// table end index
+	.endif
+9999:	str	\phys, [\tbl, \start, lsl #3]		// store the entry
+	.ifnc	\start,\end
+	add	\start, \start, #1			// next entry
+	add	\phys, \phys, #BLOCK_SIZE		// next block
+	cmp	\start, \end
+	b.ls	9999b
+	.endif
+	.endm
+
+/*
+ * Setup the initial page tables. We only setup the barest amount which is
+ * required to get the kernel running. The following sections are required:
+ *   - identity mapping to enable the MMU (low address, TTBR0)
+ *   - first few MB of the kernel linear mapping to jump to once the MMU has
+ *     been enabled, including the FDT blob (TTBR1)
+ */
+__create_page_tables:
+	pgtbl	x25, x26, x24			// idmap_pg_dir and swapper_pg_dir addresses
+
+	/*
+	 * Clear the idmap and swapper page tables.
+	 */
+	mov	x0, x25
+	add	x6, x26, #SWAPPER_DIR_SIZE
+1:	stp	xzr, xzr, [x0], #16
+	stp	xzr, xzr, [x0], #16
+	stp	xzr, xzr, [x0], #16
+	stp	xzr, xzr, [x0], #16
+	cmp	x0, x6
+	b.lo	1b
+
+	ldr	x7, =MM_MMUFLAGS
+
+	/*
+	 * Create the identity mapping.
+	 */
+	add	x0, x25, #PAGE_SIZE		// section table address
+	adr	x3, __turn_mmu_on		// virtual/physical address
+	create_pgd_entry x25, x0, x3, x5, x6
+	create_block_map x0, x7, x3, x5, x5, idmap=1
+
+	/*
+	 * Map the kernel image (starting with PHYS_OFFSET).
+	 */
+	add	x0, x26, #PAGE_SIZE		// section table address
+	mov	x5, #PAGE_OFFSET
+	create_pgd_entry x26, x0, x5, x3, x6
+	ldr	x6, =KERNEL_END - 1
+	mov	x3, x24				// phys offset
+	create_block_map x0, x7, x3, x5, x6
+
+	/*
+	 * Map the FDT blob (maximum 2MB; must be within 512MB of
+	 * PHYS_OFFSET).
+	 */
+	mov	x3, x21				// FDT phys address
+	and	x3, x3, #~((1 << 21) - 1)	// 2MB aligned
+	mov	x6, #PAGE_OFFSET
+	sub	x5, x3, x24			// subtract PHYS_OFFSET
+	tst	x5, #~((1 << 29) - 1)		// within 512MB?
+	csel	x21, xzr, x21, ne		// zero the FDT pointer
+	b.ne	1f
+	add	x5, x5, x6			// __va(FDT blob)
+	add	x6, x5, #1 << 21		// 2MB for the FDT blob
+	sub	x6, x6, #1			// inclusive range
+	create_block_map x0, x7, x3, x5, x6
+1:
+	ret
+ENDPROC(__create_page_tables)
+	.ltorg
+
+	.align	3
+	.type	__switch_data, %object
+__switch_data:
+	.quad	__mmap_switched
+	.quad	__data_loc			// x4
+	.quad	_data				// x5
+	.quad	__bss_start			// x6
+	.quad	_end				// x7
+	.quad	processor_id			// x4
+	.quad	__fdt_pointer			// x5
+	.quad	memstart_addr			// x6
+	.quad	init_thread_union + THREAD_START_SP // sp
+
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode, and
+ * uses absolute addresses; this is not position independent.
+ */
+__mmap_switched:
+	adr	x3, __switch_data + 8
+
+	ldp	x4, x5, [x3], #16
+	ldp	x6, x7, [x3], #16
+	cmp	x4, x5				// Copy data segment if needed
+1:	ccmp	x5, x6, #4, ne
+	b.eq	2f
+	ldr	x16, [x4], #8
+	str	x16, [x5], #8
+	b	1b
+2:
+1:	cmp	x6, x7
+	b.hs	2f
+	str	xzr, [x6], #8			// Clear BSS
+	b	1b
+2:
+	ldp	x4, x5, [x3], #16
+	ldr	x6, [x3], #8
+	ldr	x16, [x3]
+	mov	sp, x16
+	str	x22, [x4]			// Save processor ID
+	str	x21, [x5]			// Save FDT pointer
+	str	x24, [x6]			// Save PHYS_OFFSET
+	mov	x29, #0
+	b	start_kernel
+ENDPROC(__mmap_switched)
+
+/*
+ * Exception handling. Something went wrong and we can't proceed. We ought to
+ * tell the user, but since we don't have any guarantee that we're even
+ * running on the right architecture, we do virtually nothing.
+ */
+__error_p:
+ENDPROC(__error_p)
+
+__error:
+1:	nop
+	b	1b
+ENDPROC(__error)
+
+/*
+ * Read processor ID register and look up in the linker-built supported
+ * processor list. Note that we can't use the absolute addresses for the
+ * __proc_info lists since we aren't running with the MMU on (and therefore,
+ * we are not in the correct address space). We have to calculate the offset.
+ *
+ * This routine can be called via C code, so to avoid needlessly saving
+ * callee-saved registers, we take the CPUID in x0 and return the physical
+ * proc_info pointer in x0 as well.
+ */
+__lookup_processor_type:
+	adr	x1, __lookup_processor_type_data
+	ldr	x2, [x1]
+	ldp	x3, x4, [x1, #8]
+	sub	x1, x1, x2			// get offset between virt&phys
+	add	x3, x3, x1			// convert virt addresses to
+	add	x4, x4, x1			// physical address space
+1:
+	ldp	w5, w6, [x3]			// load cpu_val and cpu_mask
+	and	x6, x6, x0
+	cmp	x5, x6
+	b.eq	2f
+	add	x3, x3, #PROC_INFO_SZ
+	cmp	x4, x4
+	b.ne	1b
+	mov	x3, #0				// unknown processor
+2:
+	mov	x0, x3
+	ret
+ENDPROC(__lookup_processor_type)
+
+/*
+ * This provides a C-API version of the above function.
+ */
+ENTRY(lookup_processor_type)
+	mov	x8, lr
+	bl	__lookup_processor_type
+	ret	x8
+ENDPROC(lookup_processor_type)
+
+	.align	3
+	.type	__lookup_processor_type_data, %object
+__lookup_processor_type_data:
+	.quad	.
+	.quad	__proc_info_begin
+	.quad	__proc_info_end
+	.size	__lookup_processor_type_data, . - __lookup_processor_type_data
+
+/*
+ * Determine validity of the x21 FDT pointer.
+ * The dtb must be 8-byte aligned and live in the first 512M of memory.
+ */
+__vet_fdt:
+	tst	x21, #0x7
+	b.ne	1f
+	cmp	x21, x24
+	b.lt	1f
+	mov	x0, #(1 << 29)
+	add	x0, x0, x24
+	cmp	x21, x0
+	b.ge	1f
+	ret
+1:
+	mov	x21, #0
+	ret
+ENDPROC(__vet_fdt)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
new file mode 100644
index 0000000..f25186f
--- /dev/null
+++ b/arch/arm64/kernel/setup.c
@@ -0,0 +1,357 @@
+/*
+ * Based on arch/arm/kernel/setup.c
+ *
+ * Copyright (C) 1995-2001 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/utsname.h>
+#include <linux/initrd.h>
+#include <linux/console.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <linux/screen_info.h>
+#include <linux/init.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
+#include <linux/root_dev.h>
+#include <linux/cpu.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/memblock.h>
+#include <linux/of_fdt.h>
+
+#include <asm/cputype.h>
+#include <asm/elf.h>
+#include <asm/procinfo.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/traps.h>
+#include <asm/memblock.h>
+
+extern void paging_init(void);
+
+unsigned int processor_id;
+EXPORT_SYMBOL(processor_id);
+
+unsigned int elf_hwcap __read_mostly;
+EXPORT_SYMBOL(elf_hwcap);
+
+static const char *cpu_name;
+static const char *machine_name;
+phys_addr_t __fdt_pointer __initdata;
+
+/*
+ * Standard memory resources
+ */
+static struct resource mem_res[] = {
+	{
+		.name = "Kernel code",
+		.start = 0,
+		.end = 0,
+		.flags = IORESOURCE_MEM
+	},
+	{
+		.name = "Kernel data",
+		.start = 0,
+		.end = 0,
+		.flags = IORESOURCE_MEM
+	}
+};
+
+#define kernel_code mem_res[0]
+#define kernel_data mem_res[1]
+
+/*
+ * These functions re-use the assembly code in head.S, which
+ * already provide the required functionality.
+ */
+extern struct proc_info_list *lookup_processor_type(unsigned int);
+
+void __init early_print(const char *str, ...)
+{
+	char buf[256];
+	va_list ap;
+
+	va_start(ap, str);
+	vsnprintf(buf, sizeof(buf), str, ap);
+	va_end(ap);
+
+	printk("%s", buf);
+}
+
+static void __init setup_processor(void)
+{
+	struct proc_info_list *list;
+
+	/*
+	 * locate processor in the list of supported processor
+	 * types.  The linker builds this table for us from the
+	 * entries in arch/arm/mm/proc.S
+	 */
+	list = lookup_processor_type(read_cpuid_id());
+	if (!list) {
+		printk("CPU configuration botched (ID %08x), unable to continue.\n",
+		       read_cpuid_id());
+		while (1);
+	}
+
+	cpu_name = list->cpu_name;
+
+	printk("CPU: %s [%08x] revision %d\n",
+	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
+
+	sprintf(init_utsname()->machine, "aarch64");
+	elf_hwcap = 0;
+
+	cpu_proc_init();
+}
+
+static void __init setup_machine_fdt(phys_addr_t dt_phys)
+{
+	struct boot_param_header *devtree;
+	unsigned long dt_root;
+
+	/* Check we have a non-NULL DT pointer */
+	if (!dt_phys) {
+		early_print("\n"
+			"Error: NULL or invalid device tree blob\n"
+			"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
+			"\nPlease check your bootloader.\n");
+
+		while (true)
+			cpu_relax();
+
+	}
+
+	devtree = phys_to_virt(dt_phys);
+
+	/* Check device tree validity */
+	if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) {
+		early_print("\n"
+			"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
+			"Expected 0x%x, found 0x%x\n"
+			"\nPlease check your bootloader.\n",
+			dt_phys, devtree, OF_DT_HEADER,
+			be32_to_cpu(devtree->magic));
+
+		while (true)
+			cpu_relax();
+	}
+
+	initial_boot_params = devtree;
+	dt_root = of_get_flat_dt_root();
+
+	machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
+	if (!machine_name)
+		machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
+	if (!machine_name)
+		machine_name = "<unknown>";
+	pr_info("Machine: %s\n", machine_name);
+
+	/* Retrieve various information from the /chosen node */
+	of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
+	/* Initialize {size,address}-cells info */
+	of_scan_flat_dt(early_init_dt_scan_root, NULL);
+	/* Setup memory, calling early_init_dt_add_memory_arch */
+	of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+}
+
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+	size &= PAGE_MASK;
+	memblock_add(base, size);
+}
+
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+	return __va(memblock_alloc(size, align));
+}
+
+/*
+ * Limit the memory size that was specified via FDT.
+ */
+static int __init early_mem(char *p)
+{
+	phys_addr_t limit;
+
+	if (!p)
+		return 1;
+
+	limit = memparse(p, &p) & PAGE_MASK;
+	pr_notice("Memory limited to %lldMB\n", limit >> 20);
+
+	memblock_enforce_memory_limit(limit);
+
+	return 0;
+}
+early_param("mem", early_mem);
+
+static void __init request_standard_resources(void)
+{
+	struct memblock_region *region;
+	struct resource *res;
+
+	kernel_code.start   = virt_to_phys(_text);
+	kernel_code.end     = virt_to_phys(_etext - 1);
+	kernel_data.start   = virt_to_phys(_sdata);
+	kernel_data.end     = virt_to_phys(_end - 1);
+
+	for_each_memblock(memory, region) {
+		res = alloc_bootmem_low(sizeof(*res));
+		res->name  = "System RAM";
+		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
+		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
+		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+
+		request_resource(&iomem_resource, res);
+
+		if (kernel_code.start >= res->start &&
+		    kernel_code.end <= res->end)
+			request_resource(res, &kernel_code);
+		if (kernel_data.start >= res->start &&
+		    kernel_data.end <= res->end)
+			request_resource(res, &kernel_data);
+	}
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+	setup_processor();
+
+	setup_machine_fdt(__fdt_pointer);
+
+	init_mm.start_code = (unsigned long) _text;
+	init_mm.end_code   = (unsigned long) _etext;
+	init_mm.end_data   = (unsigned long) _edata;
+	init_mm.brk	   = (unsigned long) _end;
+
+	*cmdline_p = boot_command_line;
+
+	parse_early_param();
+
+	arm64_memblock_init();
+
+	paging_init();
+	request_standard_resources();
+
+	unflatten_device_tree();
+
+#ifdef CONFIG_SMP
+	smp_init_cpus();
+#endif
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+	conswitchp = &vga_con;
+#elif defined(CONFIG_DUMMY_CONSOLE)
+	conswitchp = &dummy_con;
+#endif
+#endif
+}
+
+static DEFINE_PER_CPU(struct cpu, cpu_data);
+
+static int __init topology_init(void)
+{
+	int i;
+
+	for_each_possible_cpu(i) {
+		struct cpu *cpu = &per_cpu(cpu_data, i);
+		cpu->hotpluggable = 1;
+		register_cpu(cpu, i);
+	}
+
+	return 0;
+}
+subsys_initcall(topology_init);
+
+static const char *hwcap_str[] = {
+	"fp",
+	"asimd",
+	NULL
+};
+
+static int c_show(struct seq_file *m, void *v)
+{
+	int i;
+
+	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
+		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
+
+	for_each_online_cpu(i) {
+		/*
+		 * glibc reads /proc/cpuinfo to determine the number of
+		 * online processors, looking for lines beginning with
+		 * "processor".  Give glibc what it expects.
+		 */
+#ifdef CONFIG_SMP
+		seq_printf(m, "processor\t: %d\n", i);
+#endif
+		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
+			   loops_per_jiffy / (500000UL/HZ),
+			   loops_per_jiffy / (5000UL/HZ) % 100);
+	}
+
+	/* dump out the processor features */
+	seq_puts(m, "Features\t: ");
+
+	for (i = 0; hwcap_str[i]; i++)
+		if (elf_hwcap & (1 << i))
+			seq_printf(m, "%s ", hwcap_str[i]);
+
+	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
+	seq_printf(m, "CPU architecture: AArch64\n");
+	seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
+	seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
+	seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
+
+	seq_puts(m, "\n");
+
+	seq_printf(m, "Hardware\t: %s\n", machine_name);
+
+	return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+	return *pos < 1 ? (void *)1 : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+	++*pos;
+	return NULL;
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+const struct seq_operations cpuinfo_op = {
+	.start	= c_start,
+	.next	= c_next,
+	.stop	= c_stop,
+	.show	= c_show
+};



From catalin.marinas at arm.com  Tue Aug 14 13:52:14 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:14 +0100
Subject: [PATCH v2 13/31] arm64: Device specific operations
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>

This patch adds several definitions for device communication, including
I/O accessors and ioremap(). The __raw_* accessors are implemented as
inline asm to avoid compiler generation of post-indexed accesses (less
efficient to emulate in a virtualised environment).

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/device.h |   26 ++++
 arch/arm64/include/asm/fb.h     |   34 +++++
 arch/arm64/include/asm/io.h     |  263 +++++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/io.c          |   64 ++++++++++
 arch/arm64/mm/ioremap.c         |   84 +++++++++++++
 5 files changed, 471 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/device.h
 create mode 100644 arch/arm64/include/asm/fb.h
 create mode 100644 arch/arm64/include/asm/io.h
 create mode 100644 arch/arm64/kernel/io.c
 create mode 100644 arch/arm64/mm/ioremap.c

diff --git a/arch/arm64/include/asm/device.h b/arch/arm64/include/asm/device.h
new file mode 100644
index 0000000..0d8453c
--- /dev/null
+++ b/arch/arm64/include/asm/device.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_DEVICE_H
+#define __ASM_DEVICE_H
+
+struct dev_archdata {
+	struct dma_map_ops *dma_ops;
+};
+
+struct pdev_archdata {
+};
+
+#endif
diff --git a/arch/arm64/include/asm/fb.h b/arch/arm64/include/asm/fb.h
new file mode 100644
index 0000000..adb88a6
--- /dev/null
+++ b/arch/arm64/include/asm/fb.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_FB_H_
+#define __ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+				unsigned long off)
+{
+	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+	return 0;
+}
+
+#endif /* __ASM_FB_H_ */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
new file mode 100644
index 0000000..48fa83f
--- /dev/null
+++ b/arch/arm64/include/asm/io.h
@@ -0,0 +1,263 @@
+/*
+ * Based on arch/arm/include/asm/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_IO_H
+#define __ASM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+
+#include <asm/byteorder.h>
+#include <asm/barrier.h>
+#include <asm/pgtable.h>
+
+/*
+ * Generic IO read/write.  These perform native-endian accesses.
+ */
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+	asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+	asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+	asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
+{
+	asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 val;
+	asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 val;
+	asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 val;
+	asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+	u64 val;
+	asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+	return val;
+}
+
+/* IO barriers */
+#define __iormb()		rmb()
+#define __iowmb()		wmb()
+
+#define mmiowb()		do { } while (0)
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c)	({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)	({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c)	({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
+
+#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+
+/*
+ * I/O memory access primitives. Reads are ordered relative to any
+ * following Normal memory access. Writes are ordered relative to any prior
+ * Normal memory access.
+ */
+#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
+
+/*
+ *  I/O port access primitives.
+ */
+#define IO_SPACE_LIMIT		0xffff
+
+/*
+ * We currently don't have any platform with PCI support, so just leave this
+ * defined to 0 until needed.
+ */
+#define PCI_IOBASE		((void __iomem *)0)
+
+static inline u8 inb(unsigned long addr)
+{
+	return readb(addr + PCI_IOBASE);
+}
+
+static inline u16 inw(unsigned long addr)
+{
+	return readw(addr + PCI_IOBASE);
+}
+
+static inline u32 inl(unsigned long addr)
+{
+	return readl(addr + PCI_IOBASE);
+}
+
+static inline void outb(u8 b, unsigned long addr)
+{
+	writeb(b, addr + PCI_IOBASE);
+}
+
+static inline void outw(u16 b, unsigned long addr)
+{
+	writew(b, addr + PCI_IOBASE);
+}
+
+static inline void outl(u32 b, unsigned long addr)
+{
+	writel(b, addr + PCI_IOBASE);
+}
+
+#define inb_p(addr)	inb(addr)
+#define inw_p(addr)	inw(addr)
+#define inl_p(addr)	inl(addr)
+
+#define outb_p(x, addr)	outb((x), (addr))
+#define outw_p(x, addr)	outw((x), (addr))
+#define outl_p(x, addr)	outl((x), (addr))
+
+static inline void insb(unsigned long addr, void *buffer, int count)
+{
+	u8 *buf = buffer;
+	while (count--)
+		*buf++ = __raw_readb(addr + PCI_IOBASE);
+}
+
+static inline void insw(unsigned long addr, void *buffer, int count)
+{
+	u16 *buf = buffer;
+	while (count--)
+		*buf++ = __raw_readw(addr + PCI_IOBASE);
+}
+
+static inline void insl(unsigned long addr, void *buffer, int count)
+{
+	u32 *buf = buffer;
+	while (count--)
+		*buf++ = __raw_readl(addr + PCI_IOBASE);
+}
+
+static inline void outsb(unsigned long addr, const void *buffer, int count)
+{
+	const u8 *buf = buffer;
+	while (count--)
+		__raw_writeb(*buf++, addr + PCI_IOBASE);
+}
+
+static inline void outsw(unsigned long addr, const void *buffer, int count)
+{
+	const u16 *buf = buffer;
+	while (count--)
+		__raw_writew(*buf++, addr + PCI_IOBASE);
+}
+
+static inline void outsl(unsigned long addr, const void *buffer, int count)
+{
+	const u32 *buf = buffer;
+	while (count--)
+		__raw_writel(*buf++, addr + PCI_IOBASE);
+}
+
+#define insb_p(port,to,len)	insb(port,to,len)
+#define insw_p(port,to,len)	insw(port,to,len)
+#define insl_p(port,to,len)	insl(port,to,len)
+
+#define outsb_p(port,from,len)	outsb(port,from,len)
+#define outsw_p(port,from,len)	outsw(port,from,len)
+#define outsl_p(port,from,len)	outsl(port,from,len)
+
+/*
+ * String version of I/O memory access operations.
+ */
+extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
+extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
+extern void __memset_io(volatile void __iomem *, int, size_t);
+
+#define memset_io(c,v,l)	__memset_io((c),(v),(l))
+#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
+#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))
+
+/*
+ * I/O memory mapping functions.
+ */
+extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
+extern void __iounmap(volatile void __iomem *addr);
+
+#define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
+#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_XN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
+
+#define ioremap(addr, size)		__ioremap((addr), (size), PROT_DEVICE_nGnRE)
+#define ioremap_nocache(addr, size)	__ioremap((addr), (size), PROT_DEVICE_nGnRE)
+#define ioremap_wc(addr, size)		__ioremap((addr), (size), PROT_NORMAL_NC)
+#define iounmap				__iounmap
+
+#define ARCH_HAS_IOREMAP_WC
+#include <asm-generic/iomap.h>
+
+/*
+ * More restrictive address range checking than the default implementation
+ * (PHYS_OFFSET and PHYS_MASK taken into account).
+ */
+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+extern int valid_phys_addr_range(unsigned long addr, size_t size);
+extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+
+extern int devmem_is_allowed(unsigned long pfn);
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)	__va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)	p
+
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_IO_H */
diff --git a/arch/arm64/kernel/io.c b/arch/arm64/kernel/io.c
new file mode 100644
index 0000000..7d37ead
--- /dev/null
+++ b/arch/arm64/kernel/io.c
@@ -0,0 +1,64 @@
+/*
+ * Based on arch/arm/kernel/io.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+/*
+ * Copy data from IO memory space to "real" memory space.
+ */
+void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
+{
+	unsigned char *t = to;
+	while (count) {
+		count--;
+		*t = readb(from);
+		t++;
+		from++;
+	}
+}
+EXPORT_SYMBOL(__memcpy_fromio);
+
+/*
+ * Copy data from "real" memory space to IO memory space.
+ */
+void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
+{
+	const unsigned char *f = from;
+	while (count) {
+		count--;
+		writeb(*f, to);
+		f++;
+		to++;
+	}
+}
+EXPORT_SYMBOL(__memcpy_toio);
+
+/*
+ * "memset" on IO memory space.
+ */
+void __memset_io(volatile void __iomem *dst, int c, size_t count)
+{
+	while (count) {
+		count--;
+		writeb(c, dst);
+		dst++;
+	}
+}
+EXPORT_SYMBOL(__memset_io);
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
new file mode 100644
index 0000000..1725cd6
--- /dev/null
+++ b/arch/arm64/mm/ioremap.c
@@ -0,0 +1,84 @@
+/*
+ * Based on arch/arm/mm/ioremap.c
+ *
+ * (C) Copyright 1995 1996 Linus Torvalds
+ * Hacked for ARM by Phil Blundell <philb at gnu.org>
+ * Hacked to allow all architectures to build, and various cleanups
+ * by Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/io.h>
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+				      pgprot_t prot, void *caller)
+{
+	unsigned long last_addr;
+	unsigned long offset = phys_addr & ~PAGE_MASK;
+	int err;
+	unsigned long addr;
+	struct vm_struct *area;
+
+	/*
+	 * Page align the mapping address and size, taking account of any
+	 * offset.
+	 */
+	phys_addr &= PAGE_MASK;
+	size = PAGE_ALIGN(size + offset);
+
+	/*
+	 * Don't allow wraparound, zero size or outside PHYS_MASK.
+	 */
+	last_addr = phys_addr + size - 1;
+	if (!size || last_addr < phys_addr || (last_addr & ~PHYS_MASK))
+		return NULL;
+
+	/*
+	 * Don't allow RAM to be mapped.
+	 */
+	if (WARN_ON(pfn_valid(__phys_to_pfn(phys_addr))))
+		return NULL;
+
+	area = get_vm_area_caller(size, VM_IOREMAP, caller);
+	if (!area)
+		return NULL;
+	addr = (unsigned long)area->addr;
+
+	err = ioremap_page_range(addr, addr + size, phys_addr, prot);
+	if (err) {
+		vunmap((void *)addr);
+		return NULL;
+	}
+
+	return (void __iomem *)(offset + addr);
+}
+
+void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot)
+{
+	return __ioremap_caller(phys_addr, size, prot,
+				__builtin_return_address(0));
+}
+EXPORT_SYMBOL(__ioremap);
+
+void __iounmap(volatile void __iomem *io_addr)
+{
+	void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
+
+	vunmap(addr);
+}
+EXPORT_SYMBOL(__iounmap);



From catalin.marinas at arm.com  Tue Aug 14 13:52:10 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:10 +0100
Subject: [PATCH v2 09/31] arm64: Cache maintenance routines
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-10-git-send-email-catalin.marinas@arm.com>

The patch adds functionality required for cache maintenance. The AArch64
architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
are automatically broadcast in hardware between CPUs.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/cache.h      |   32 ++++
 arch/arm64/include/asm/cacheflush.h |  209 ++++++++++++++++++++++++++
 arch/arm64/include/asm/cachetype.h  |   48 ++++++
 arch/arm64/mm/cache.S               |  279 +++++++++++++++++++++++++++++++++++
 arch/arm64/mm/flush.c               |  132 +++++++++++++++++
 5 files changed, 700 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/cache.h
 create mode 100644 arch/arm64/include/asm/cacheflush.h
 create mode 100644 arch/arm64/include/asm/cachetype.h
 create mode 100644 arch/arm64/mm/cache.S
 create mode 100644 arch/arm64/mm/flush.c

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
new file mode 100644
index 0000000..390308a
--- /dev/null
+++ b/arch/arm64/include/asm/cache.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_CACHE_H
+#define __ASM_CACHE_H
+
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+
+/*
+ * Memory returned by kmalloc() may be used for DMA, so we must make
+ * sure that all such allocations are cache aligned. Otherwise,
+ * unrelated code may cause parts of the buffer to be read into the
+ * cache before the transfer is done, causing old data to be seen by
+ * the CPU.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+#define ARCH_SLAB_MINALIGN	8
+
+#endif
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
new file mode 100644
index 0000000..93b5590
--- /dev/null
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -0,0 +1,209 @@
+/*
+ * Based on arch/arm/include/asm/cacheflush.h
+ *
+ * Copyright (C) 1999-2002 Russell King.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_CACHEFLUSH_H
+#define __ASM_CACHEFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
+ */
+#define PG_dcache_clean PG_arch_1
+
+/*
+ *	MM Cache Management
+ *	===================
+ *
+ *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
+ *	implement these methods.
+ *
+ *	Start addresses are inclusive and end addresses are exclusive;
+ *	start addresses should be rounded down, end addresses up.
+ *
+ *	See Documentation/cachetlb.txt for more information.
+ *	Please note that the implementation of these, and the required
+ *	effects are cache-type (VIVT/VIPT/PIPT) specific.
+ *
+ *	flush_cache_kern_all()
+ *
+ *		Unconditionally clean and invalidate the entire cache.
+ *
+ *	flush_cache_user_mm(mm)
+ *
+ *		Clean and invalidate all user space cache entries
+ *		before a change of page tables.
+ *
+ *	flush_cache_user_range(start, end, flags)
+ *
+ *		Clean and invalidate a range of cache entries in the
+ *		specified address space before a change of page tables.
+ *		- start - user start address (inclusive, page aligned)
+ *		- end   - user end address   (exclusive, page aligned)
+ *		- flags - vma->vm_flags field
+ *
+ *	coherent_kern_range(start, end)
+ *
+ *		Ensure coherency between the Icache and the Dcache in the
+ *		region described by start, end.  If you have non-snooping
+ *		Harvard caches, you need to implement this function.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
+ *	coherent_user_range(start, end)
+ *
+ *		Ensure coherency between the Icache and the Dcache in the
+ *		region described by start, end.  If you have non-snooping
+ *		Harvard caches, you need to implement this function.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
+ *	flush_kern_dcache_area(kaddr, size)
+ *
+ *		Ensure that the data held in page is written back.
+ *		- kaddr  - page address
+ *		- size   - region size
+ *
+ *	DMA Cache Coherency
+ *	===================
+ *
+ *	dma_flush_range(start, end)
+ *
+ *		Clean and invalidate the specified virtual address range.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ */
+extern void __cpuc_flush_kern_all(void);
+extern void __cpuc_flush_user_all(void);
+extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
+extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
+extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
+extern void __cpuc_flush_dcache_area(void *, size_t);
+
+/*
+ * These are private to the dma-mapping API.  Do not use directly.
+ * Their sole purpose is to ensure that data held in the cache
+ * is visible to DMA, or data written by DMA to system memory is
+ * visible to the CPU.
+ */
+extern void dmac_map_area(const void *, size_t, int);
+extern void dmac_unmap_area(const void *, size_t, int);
+extern void dmac_flush_range(const void *, const void *);
+
+/*
+ * Copy user data from/to a page which is mapped into a different
+ * processes address space.  Really, we want to allow our "user
+ * space" model to handle this.
+ */
+extern void copy_to_user_page(struct vm_area_struct *, struct page *,
+	unsigned long, void *, const void *, unsigned long);
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+	do {							\
+		memcpy(dst, src, len);				\
+	} while (0)
+
+/*
+ * Convert calls to our calling convention.
+ */
+#define flush_cache_all()		__cpuc_flush_kern_all()
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
+
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+
+/*
+ * flush_cache_user_range is used when we want to ensure that the
+ * Harvard caches are synchronised for the user space address range.
+ * This is used for the ARM private sys_cacheflush system call.
+ */
+#define flush_cache_user_range(start, end) \
+	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
+
+/*
+ * Perform necessary cache operations to ensure that data previously
+ * stored within this range of addresses can be executed by the CPU.
+ */
+#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)
+
+/*
+ * flush_dcache_page is used when the kernel has written to the page
+ * cache page at virtual address page->virtual.
+ *
+ * If this page isn't mapped (ie, page_mapping == NULL), or it might
+ * have userspace mappings, then we _must_ always clean + invalidate
+ * the dcache entries associated with the kernel mapping.
+ *
+ * Otherwise we can defer the operation, and clean the cache when we are
+ * about to change to user space.  This is the same method as used on SPARC64.
+ * See update_mmu_cache for the user space part.
+ */
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+static inline void __flush_icache_all(void)
+{
+	asm("ic	ialluis");
+}
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+static inline void flush_anon_page(struct vm_area_struct *vma,
+			 struct page *page, unsigned long vmaddr)
+{
+	extern void __flush_anon_page(struct vm_area_struct *vma,
+				struct page *, unsigned long);
+	if (PageAnon(page))
+		__flush_anon_page(vma, page, vmaddr);
+}
+
+#define flush_dcache_mmap_lock(mapping) \
+	spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) \
+	spin_unlock_irq(&(mapping)->tree_lock)
+
+#define flush_icache_user_range(vma,page,addr,len) \
+	flush_dcache_page(page)
+
+/*
+ * We don't appear to need to do anything here.  In fact, if we did, we'd
+ * duplicate cache flushing elsewhere performed by flush_dcache_page().
+ */
+#define flush_icache_page(vma,page)	do { } while (0)
+
+/*
+ * flush_cache_vmap() is used when creating mappings (eg, via vmap,
+ * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
+ * caches, since the direct-mappings of these pages may contain cached
+ * data, we need to do a full cache flush to ensure that writebacks
+ * don't corrupt data placed into these pages via the new mappings.
+ */
+static inline void flush_cache_vmap(unsigned long start, unsigned long end)
+{
+	/*
+	 * set_pte_at() called from vmap_pte_range() does not
+	 * have a DSB after cleaning the cache line.
+	 */
+	dsb();
+}
+
+static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
+{
+}
+
+#endif
diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
new file mode 100644
index 0000000..85f5f51
--- /dev/null
+++ b/arch/arm64/include/asm/cachetype.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_CACHETYPE_H
+#define __ASM_CACHETYPE_H
+
+#include <asm/cputype.h>
+
+#define CTR_L1IP_SHIFT		14
+#define CTR_L1IP_MASK		3
+
+#define ICACHE_POLICY_RESERVED	0
+#define ICACHE_POLICY_AIVIVT	1
+#define ICACHE_POLICY_VIPT	2
+#define ICACHE_POLICY_PIPT	3
+
+static inline u32 icache_policy(void)
+{
+	return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK;
+}
+
+/*
+ * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
+ * permitted in the I-cache.
+ */
+static inline int icache_is_aliasing(void)
+{
+	return icache_policy() != ICACHE_POLICY_PIPT;
+}
+
+static inline int icache_is_aivivt(void)
+{
+	return icache_policy() == ICACHE_POLICY_AIVIVT;
+}
+
+#endif	/* __ASM_CACHETYPE_H */
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
new file mode 100644
index 0000000..f4efa04
--- /dev/null
+++ b/arch/arm64/mm/cache.S
@@ -0,0 +1,279 @@
+/*
+ * Cache maintenance
+ *
+ * Copyright (C) 2001 Deep Blue Solutions Ltd.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+#include "proc-macros.S"
+
+/*
+ *	__cpuc_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: x0-x7, x9-x11
+ */
+ENTRY(__cpuc_flush_dcache_all)
+	dsb	sy				// ensure ordering with previous memory accesses
+	mrs	x0, clidr_el1			// read clidr
+	and	x3, x0, #0x7000000		// extract loc from clidr
+	lsr	x3, x3, #23			// left align loc bit field
+	cbz	x3, finished			// if loc is 0, then no need to clean
+	mov	x10, #0				// start clean at cache level 0
+loop1:
+	add	x2, x10, x10, lsr #1		// work out 3x current cache level
+	lsr	x1, x0, x2			// extract cache type bits from clidr
+	and	x1, x1, #7			// mask of the bits for current cache only
+	cmp	x1, #2				// see what cache we have at this level
+	b.lt	skip				// skip if no cache, or just i-cache
+	save_and_disable_irqs x9		// make CSSELR and CCSIDR access atomic
+	msr	csselr_el1, x10			// select current cache level in csselr
+	isb					// isb to sych the new cssr&csidr
+	mrs	x1, ccsidr_el1			// read the new ccsidr
+	restore_irqs x9
+	and	x2, x1, #7			// extract the length of the cache lines
+	add	x2, x2, #4			// add 4 (line length offset)
+	mov	x4, #0x3ff
+	and	x4, x4, x1, lsr #3		// find maximum number on the way size
+	clz	x5, x4				// find bit position of way size increment
+	mov	x7, #0x7fff
+	and	x7, x7, x1, lsr #13		// extract max number of the index size
+loop2:
+	mov	x9, x4				// create working copy of max way size
+loop3:
+	lsl	x6, x9, x5
+	orr	x11, x10, x6			// factor way and cache number into x11
+	lsl	x6, x7, x2
+	orr	x11, x11, x6			// factor index number into x11
+	dc	cisw, x11			// clean & invalidate by set/way
+	subs	x9, x9, #1			// decrement the way
+	b.ge	loop3
+	subs	x7, x7, #1			// decrement the index
+	b.ge	loop2
+skip:
+	add	x10, x10, #2			// increment cache number
+	cmp	x3, x10
+	b.gt	loop1
+finished:
+	mov	x10, #0				// swith back to cache level 0
+	msr	csselr_el1, x10			// select current cache level in csselr
+	dsb	sy
+	isb
+	ret
+ENDPROC(__cpuc_flush_dcache_all)
+
+/*
+ *	__cpuc_flush_cache_all()
+ *
+ *	Flush the entire cache system.  The data cache flush is now achieved
+ *	using atomic clean / invalidates working outwards from L1 cache. This
+ *	is done using Set/Way based cache maintainance instructions.  The
+ *	instruction cache can still be invalidated back to the point of
+ *	unification in a single instruction.
+ */
+ENTRY(__cpuc_flush_kern_all)
+	mov	x12, lr
+	bl	__cpuc_flush_dcache_all
+	mov	x0, #0
+	ic	ialluis				// I+BTB cache invalidate
+	ret	x12
+ENDPROC(__cpuc_flush_kern_all)
+
+/*
+ *	__cpuc_flush_cache_all()
+ *
+ *	Flush all TLB entries in a particular address space
+ */
+ENTRY(__cpuc_flush_user_all)
+	/*FALLTHROUGH*/
+
+/*
+ *	__cpuc_flush_cache_range(start, end, flags)
+ *
+ *	Flush a range of TLB entries in the specified address space.
+ *
+ *	- start - start address (may not be aligned)
+ *	- end   - end address (exclusive, may not be aligned)
+ *	- flags	- vm_area_struct flags describing address space
+ */
+ENTRY(__cpuc_flush_user_range)
+	ret
+ENDPROC(__cpuc_flush_user_all)
+ENDPROC(__cpuc_flush_user_range)
+
+/*
+ *	__cpuc_coherent_kern_range(start,end)
+ *
+ *	Ensure that the I and D caches are coherent within specified region.
+ *	This is typically used when code has been written to a memory region,
+ *	and will be executed.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(__cpuc_coherent_kern_range)
+	/* FALLTHROUGH */
+
+/*
+ *	__cpuc_coherent_user_range(start,end)
+ *
+ *	Ensure that the I and D caches are coherent within specified region.
+ *	This is typically used when code has been written to a memory region,
+ *	and will be executed.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(__cpuc_coherent_user_range)
+	dcache_line_size x2, x3
+	sub	x3, x2, #1
+	bic	x4, x0, x3
+1:
+USER(9f, dc	cvau, x4	)		// clean D line to PoU
+	add	x4, x4, x2
+	cmp	x4, x1
+	b.lo	1b
+	dsb	sy
+
+	icache_line_size x2, x3
+	sub	x3, x2, #1
+	bic	x4, x0, x3
+1:
+USER(9f, ic	ivau, x4	)		// invalidate I line PoU
+	add	x4, x4, x2
+	cmp	x4, x1
+	b.lo	1b
+9:						// ignore any faulting cache operation
+	dsb	sy
+	isb
+	ret
+ENDPROC(__cpuc_coherent_kern_range)
+ENDPROC(__cpuc_coherent_user_range)
+
+	.section .fixup,"ax"
+	.align	0
+9001:	ret
+	.previous
+
+
+/*
+ *	__cpuc_flush_kern_dcache_page(kaddr)
+ *
+ *	Ensure that the data held in the page kaddr is written back to the
+ *	page in question.
+ *
+ *	- kaddr   - kernel address
+ *	- size    - size in question
+ */
+ENTRY(__cpuc_flush_dcache_area)
+	dcache_line_size x2, x3
+	add	x1, x0, x1
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	civac, x0			// clean & invalidate D line / unified line
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(__cpuc_flush_dcache_area)
+
+/*
+ *	dmac_inv_range(start,end)
+ *
+ *	Invalidate the data cache within the specified region; we will be
+ *	performing a DMA operation in this region and we want to purge old
+ *	data in the cache.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(dmac_inv_range)
+	dcache_line_size x2, x3
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+	bic	x1, x1, x3
+1:	dc	ivac, x0			// invalidate D / U line
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(dmac_inv_range)
+
+/*
+ *	dmac_clean_range(start,end)
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(dmac_clean_range)
+	dcache_line_size x2, x3
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	cvac, x0			// clean D / U line
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(dmac_clean_range)
+
+/*
+ *	dmac_flush_range(start,end)
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(dmac_flush_range)
+	dcache_line_size x2, x3
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	civac, x0			// clean & invalidate D / U line
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(dmac_flush_range)
+
+/*
+ *	dmac_map_area(start, size, dir)
+ *	- start	- kernel virtual start address
+ *	- size	- size of region
+ *	- dir	- DMA direction
+ */
+ENTRY(dmac_map_area)
+	add	x1, x1, x0
+	cmp	x2, #DMA_FROM_DEVICE
+	b.eq	dmac_inv_range
+	b	dmac_clean_range
+ENDPROC(dmac_map_area)
+
+/*
+ *	dmac_unmap_area(start, size, dir)
+ *	- start	- kernel virtual start address
+ *	- size	- size of region
+ *	- dir	- DMA direction
+ */
+ENTRY(dmac_unmap_area)
+	add	x1, x1, x0
+	cmp	x2, #DMA_TO_DEVICE
+	b.ne	dmac_inv_range
+	ret
+ENDPROC(dmac_unmap_area)
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
new file mode 100644
index 0000000..44f9e5c
--- /dev/null
+++ b/arch/arm64/mm/flush.c
@@ -0,0 +1,132 @@
+/*
+ * Based on arch/arm/mm/flush.c
+ *
+ * Copyright (C) 1995-2002 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cachetype.h>
+#include <asm/tlbflush.h>
+
+#include "mm.h"
+
+void flush_cache_mm(struct mm_struct *mm)
+{
+}
+
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+		       unsigned long end)
+{
+	if (vma->vm_flags & VM_EXEC)
+		__flush_icache_all();
+}
+
+void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr,
+		      unsigned long pfn)
+{
+}
+
+static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+				unsigned long uaddr, void *kaddr,
+				unsigned long len)
+{
+	if (vma->vm_flags & VM_EXEC) {
+		unsigned long addr = (unsigned long)kaddr;
+		if (icache_is_aliasing()) {
+			__cpuc_flush_dcache_area(kaddr, len);
+			__flush_icache_all();
+		} else {
+			__cpuc_coherent_kern_range(addr, addr + len);
+		}
+	}
+}
+
+/*
+ * Copy user data from/to a page which is mapped into a different processes
+ * address space.  Really, we want to allow our "user space" model to handle
+ * this.
+ *
+ * Note that this code needs to run on the current CPU.
+ */
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+		       unsigned long uaddr, void *dst, const void *src,
+		       unsigned long len)
+{
+#ifdef CONFIG_SMP
+	preempt_disable();
+#endif
+	memcpy(dst, src, len);
+	flush_ptrace_access(vma, page, uaddr, dst, len);
+#ifdef CONFIG_SMP
+	preempt_enable();
+#endif
+}
+
+void __flush_dcache_page(struct address_space *mapping, struct page *page)
+{
+	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+}
+
+void __sync_icache_dcache(pte_t pte)
+{
+	unsigned long pfn;
+	struct page *page;
+
+	pfn = pte_pfn(pte);
+	if (!pfn_valid(pfn))
+		return;
+
+	page = pfn_to_page(pfn);
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+		__flush_dcache_page(NULL, page);
+	__flush_icache_all();
+}
+
+/*
+ * Ensure cache coherency between kernel mapping and userspace mapping of this
+ * page.
+ */
+void flush_dcache_page(struct page *page)
+{
+	struct address_space *mapping;
+
+	/*
+	 * The zero page is never written to, so never has any dirty cache
+	 * lines, and therefore never needs to be flushed.
+	 */
+	if (page == ZERO_PAGE(0))
+		return;
+
+	mapping = page_mapping(page);
+
+	if (mapping && !mapping_mapped(mapping))
+		clear_bit(PG_dcache_clean, &page->flags);
+	else {
+		__flush_dcache_page(mapping, page);
+		if (mapping)
+			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
+}
+EXPORT_SYMBOL(flush_dcache_page);
+
+void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
+{
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:13 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:13 +0100
Subject: [PATCH v2 12/31] arm64: Atomic operations
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-13-git-send-email-catalin.marinas@arm.com>

This patch introduces the atomic, mutex and futex operations. Many
atomic operations use the load-acquire and store-release operations
which imply barriers, avoiding the need for explicit DMB.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/atomic.h |  306 +++++++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/futex.h  |  134 +++++++++++++++++
 2 files changed, 440 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/atomic.h
 create mode 100644 arch/arm64/include/asm/futex.h

diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
new file mode 100644
index 0000000..fa60c8b
--- /dev/null
+++ b/arch/arm64/include/asm/atomic.h
@@ -0,0 +1,306 @@
+/*
+ * Based on arch/arm/include/asm/atomic.h
+ *
+ * Copyright (C) 1996 Russell King.
+ * Copyright (C) 2002 Deep Blue Solutions Ltd.
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ATOMIC_H
+#define __ASM_ATOMIC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#ifdef __KERNEL__
+
+/*
+ * On ARM, ordinary assignment (str instruction) doesn't clear the local
+ * strex/ldrex monitor on some implementations. The reason we can use it for
+ * atomic_set() is the clrex or dummy strex done on every exception return.
+ */
+#define atomic_read(v)	(*(volatile int *)&(v)->counter)
+#define atomic_set(v,i)	(((v)->counter) = (i))
+
+/*
+ * AArch64 UP and SMP safe atomic ops.  We use load exclusive and
+ * store exclusive to ensure that these are atomic.  We may loop
+ * to ensure that the update happens.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+	unsigned long tmp;
+	int result;
+
+	asm volatile("// atomic_add\n"
+"1:	ldxr	%w0, [%3]\n"
+"	add	%w0, %w0, %w4\n"
+"	stxr	%w1, %w0, [%3]\n"
+"	cbnz	%w1,1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+	unsigned long tmp;
+	int result;
+
+	asm volatile("// atomic_add_return\n"
+"1:	ldaxr	%w0, [%3]\n"
+"	add	%w0, %w0, %w4\n"
+"	stlxr	%w1, %w0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+
+	return result;
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+	unsigned long tmp;
+	int result;
+
+	asm volatile("// atomic_sub\n"
+"1:	ldxr	%w0, [%3]\n"
+"	sub	%w0, %w0, %w4\n"
+"	stxr	%w1, %w0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+	unsigned long tmp;
+	int result;
+
+	asm volatile("// atomic_sub_return\n"
+"1:	ldaxr	%w0, [%3]\n"
+"	sub	%w0, %w0, %w4\n"
+"	stlxr	%w1, %w0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+
+	return result;
+}
+
+static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
+{
+	unsigned long tmp;
+	int oldval;
+
+	asm volatile("// atomic_cmpxchg\n"
+"1:	ldaxr	%w1, [%3]\n"
+"	cmp	%w1, %w4\n"
+"	b.ne	2f\n"
+"	stlxr	%w0, %w5, [%3]\n"
+"	cbnz	%w0, 1b\n"
+"2:"
+	: "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
+	: "r" (&ptr->counter), "Ir" (old), "r" (new)
+	: "cc");
+
+	return oldval;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+	unsigned long tmp, tmp2;
+
+	asm volatile("// atomic_clear_mask\n"
+"1:	ldxr	%0, [%3]\n"
+"	bic	%0, %0, %4\n"
+"	stxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
+	: "r" (addr), "Ir" (mask)
+	: "cc");
+}
+
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+	int c, old;
+
+	c = atomic_read(v);
+	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
+		c = old;
+	return c;
+}
+
+#define atomic_inc(v)		atomic_add(1, v)
+#define atomic_dec(v)		atomic_sub(1, v)
+
+#define atomic_inc_and_test(v)	(atomic_add_return(1, v) == 0)
+#define atomic_dec_and_test(v)	(atomic_sub_return(1, v) == 0)
+#define atomic_inc_return(v)    (atomic_add_return(1, v))
+#define atomic_dec_return(v)    (atomic_sub_return(1, v))
+#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
+
+#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
+
+#define smp_mb__before_atomic_dec()	smp_mb()
+#define smp_mb__after_atomic_dec()	smp_mb()
+#define smp_mb__before_atomic_inc()	smp_mb()
+#define smp_mb__after_atomic_inc()	smp_mb()
+
+/*
+ * 64-bit atomic operations.
+ */
+#define ATOMIC64_INIT(i) { (i) }
+
+#define atomic64_read(v)	(*(volatile long long *)&(v)->counter)
+#define atomic64_set(v,i)	(((v)->counter) = (i))
+
+static inline void atomic64_add(u64 i, atomic64_t *v)
+{
+	long result;
+	unsigned long tmp;
+
+	asm volatile("// atomic64_add\n"
+"1:	ldxr	%0, [%3]\n"
+"	add	%0, %0, %4\n"
+"	stxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+}
+
+static inline long atomic64_add_return(long i, atomic64_t *v)
+{
+	long result;
+	unsigned long tmp;
+
+	asm volatile("// atomic64_add_return\n"
+"1:	ldaxr	%0, [%3]\n"
+"	add	%0, %0, %4\n"
+"	stlxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+
+	return result;
+}
+
+static inline void atomic64_sub(u64 i, atomic64_t *v)
+{
+	long result;
+	unsigned long tmp;
+
+	asm volatile("// atomic64_sub\n"
+"1:	ldxr	%0, [%3]\n"
+"	sub	%0, %0, %4\n"
+"	stxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+}
+
+static inline long atomic64_sub_return(long i, atomic64_t *v)
+{
+	long result;
+	unsigned long tmp;
+
+	asm volatile("// atomic64_sub_return\n"
+"1:	ldaxr	%0, [%3]\n"
+"	sub	%0, %0, %4\n"
+"	stlxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter), "Ir" (i)
+	: "cc");
+
+	return result;
+}
+
+static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
+{
+	long oldval;
+	unsigned long res;
+
+	asm volatile("// atomic64_cmpxchg\n"
+"1:	ldaxr	%1, [%3]\n"
+"	cmp	%1, %4\n"
+"	b.ne	2f\n"
+"	stlxr	%w0, %5, [%3]\n"
+"	cbnz	%w0, 1b\n"
+"2:"
+	: "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
+	: "r" (&ptr->counter), "Ir" (old), "r" (new)
+	: "cc");
+
+	return oldval;
+}
+
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
+static inline long atomic64_dec_if_positive(atomic64_t *v)
+{
+	long result;
+	unsigned long tmp;
+
+	asm volatile("// atomic64_dec_if_positive\n"
+"1:	ldaxr	%0, [%3]\n"
+"	subs	%0, %0, #1\n"
+"	b.mi	2f\n"
+"	stlxr	%w1, %0, [%3]\n"
+"	cbnz	%w1, 1b\n"
+"2:"
+	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
+	: "r" (&v->counter)
+	: "cc");
+
+	return result;
+}
+
+static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+	long c, old;
+
+	c = atomic64_read(v);
+	while (c != u && (old = atomic64_cmpxchg((v), c, c + a)) != c)
+		c = old;
+
+	return c != u;
+}
+
+#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)
+#define atomic64_inc(v)			atomic64_add(1LL, (v))
+#define atomic64_inc_return(v)		atomic64_add_return(1LL, (v))
+#define atomic64_inc_and_test(v)	(atomic64_inc_return(v) == 0)
+#define atomic64_sub_and_test(a, v)	(atomic64_sub_return((a), (v)) == 0)
+#define atomic64_dec(v)			atomic64_sub(1LL, (v))
+#define atomic64_dec_return(v)		atomic64_sub_return(1LL, (v))
+#define atomic64_dec_and_test(v)	(atomic64_dec_return((v)) == 0)
+#define atomic64_inc_not_zero(v)	atomic64_add_unless((v), 1LL, 0LL)
+
+#endif
+#endif
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
new file mode 100644
index 0000000..0745e82
--- /dev/null
+++ b/arch/arm64/include/asm/futex.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_FUTEX_H
+#define __ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg)		\
+	asm volatile(							\
+"1:	ldaxr	%w1, %2\n"						\
+	insn "\n"							\
+"2:	stlxr	%w3, %w0, %2\n"						\
+"	cbnz	%w3, 1b\n"						\
+"3:	.pushsection __ex_table,\"a\"\n"				\
+"	.align	3\n"							\
+"	.quad	1b, 4f, 2b, 4f\n"					\
+"	.popsection\n"							\
+"	.pushsection .fixup,\"ax\"\n"					\
+"4:	mov	%w0, %w5\n"						\
+"	b	3b\n"							\
+"	.popsection"							\
+	: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)	\
+	: "r" (oparg), "Ir" (-EFAULT)					\
+	: "cc")
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
+{
+	int op = (encoded_op >> 28) & 7;
+	int cmp = (encoded_op >> 24) & 15;
+	int oparg = (encoded_op << 8) >> 20;
+	int cmparg = (encoded_op << 20) >> 20;
+	int oldval = 0, ret, tmp;
+
+	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+		oparg = 1 << oparg;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+		return -EFAULT;
+
+	pagefault_disable();	/* implies preempt_disable() */
+
+	switch (op) {
+	case FUTEX_OP_SET:
+		__futex_atomic_op("mov	%w0, %w4",
+				  ret, oldval, uaddr, tmp, oparg);
+		break;
+	case FUTEX_OP_ADD:
+		__futex_atomic_op("add	%w0, %w1, %w4",
+				  ret, oldval, uaddr, tmp, oparg);
+		break;
+	case FUTEX_OP_OR:
+		__futex_atomic_op("orr	%w0, %w1, %w4",
+				  ret, oldval, uaddr, tmp, oparg);
+		break;
+	case FUTEX_OP_ANDN:
+		__futex_atomic_op("and	%w0, %w1, %w4",
+				  ret, oldval, uaddr, tmp, ~oparg);
+		break;
+	case FUTEX_OP_XOR:
+		__futex_atomic_op("eor	%w0, %w1, %w4",
+				  ret, oldval, uaddr, tmp, oparg);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	pagefault_enable();	/* subsumes preempt_enable() */
+
+	if (!ret) {
+		switch (cmp) {
+		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+		default: ret = -ENOSYS;
+		}
+	}
+	return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+			      u32 oldval, u32 newval)
+{
+	int ret = 0;
+	u32 val, tmp;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+		return -EFAULT;
+
+	asm volatile("// futex_atomic_cmpxchg_inatomic\n"
+"1:	ldaxr	%w1, %2\n"
+"	sub	%w3, %w1, %w4\n"
+"	cbnz	%w3, 3f\n"
+"2:	stlxr	%w3, %w5, %2\n"
+"	cbnz	%w3, 1b\n"
+"3:	.pushsection __ex_table,\"a\"\n"
+"	.align	3\n"
+"	.quad	1b, 4f, 2b, 4f\n"
+"	.popsection\n"
+"	.pushsection .fixup,\"ax\"\n"
+"4:	mov	%w0, %w6\n"
+"	b	3b\n"
+"	.popsection"
+	: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
+	: "r" (oldval), "r" (newval), "Ir" (-EFAULT)
+	: "cc", "memory");
+
+	*uval = val;
+	return ret;
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_FUTEX_H */



From catalin.marinas at arm.com  Tue Aug 14 13:52:17 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:17 +0100
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-17-git-send-email-catalin.marinas@arm.com>

This patch adds definitions for the ELF format, including personality
personality setting and EXEC_PAGESIZE. The are only two hwcap
definitions for 64-bit applications - HWCAP_FP and HWCAP_ASIMD.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/auxvec.h   |   22 +++++
 arch/arm64/include/asm/elf.h      |  176 +++++++++++++++++++++++++++++++++++++
 arch/arm64/include/asm/hwcap.h    |   57 ++++++++++++
 arch/arm64/include/asm/param.h    |   23 +++++
 arch/arm64/include/asm/shmparam.h |   28 ++++++
 arch/arm64/kernel/elf.c           |   41 +++++++++
 6 files changed, 347 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/auxvec.h
 create mode 100644 arch/arm64/include/asm/elf.h
 create mode 100644 arch/arm64/include/asm/hwcap.h
 create mode 100644 arch/arm64/include/asm/param.h
 create mode 100644 arch/arm64/include/asm/shmparam.h
 create mode 100644 arch/arm64/kernel/elf.c

diff --git a/arch/arm64/include/asm/auxvec.h b/arch/arm64/include/asm/auxvec.h
new file mode 100644
index 0000000..22d6d88
--- /dev/null
+++ b/arch/arm64/include/asm/auxvec.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_AUXVEC_H
+#define __ASM_AUXVEC_H
+
+/* vDSO location */
+#define AT_SYSINFO_EHDR	33
+
+#endif
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
new file mode 100644
index 0000000..9d62a7a
--- /dev/null
+++ b/arch/arm64/include/asm/elf.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_ELF_H
+#define __ASM_ELF_H
+
+#include <asm/hwcap.h>
+
+/*
+ * ELF register definitions..
+ */
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_fp elf_fpregset_t;
+
+#define EM_AARCH64		183
+
+/*
+ * AArch64 static relocation types.
+ */
+
+/* Miscellaneous. */
+#define R_ARM_NONE			0
+#define R_AARCH64_NONE			256
+
+/* Data. */
+#define R_AARCH64_ABS64			257
+#define R_AARCH64_ABS32			258
+#define R_AARCH64_ABS16			259
+#define R_AARCH64_PREL64		260
+#define R_AARCH64_PREL32		261
+#define R_AARCH64_PREL16		262
+
+/* Instructions. */
+#define R_AARCH64_MOVW_UABS_G0		263
+#define R_AARCH64_MOVW_UABS_G0_NC	264
+#define R_AARCH64_MOVW_UABS_G1		265
+#define R_AARCH64_MOVW_UABS_G1_NC	266
+#define R_AARCH64_MOVW_UABS_G2		267
+#define R_AARCH64_MOVW_UABS_G2_NC	268
+#define R_AARCH64_MOVW_UABS_G3		269
+
+#define R_AARCH64_MOVW_SABS_G0		270
+#define R_AARCH64_MOVW_SABS_G1		271
+#define R_AARCH64_MOVW_SABS_G2		272
+
+#define R_AARCH64_LD_PREL_LO19		273
+#define R_AARCH64_ADR_PREL_LO21		274
+#define R_AARCH64_ADR_PREL_PG_HI21	275
+#define R_AARCH64_ADR_PREL_PG_HI21_NC	276
+#define R_AARCH64_ADD_ABS_LO12_NC	277
+#define R_AARCH64_LDST8_ABS_LO12_NC	278
+
+#define R_AARCH64_TSTBR14		279
+#define R_AARCH64_CONDBR19		280
+#define R_AARCH64_JUMP26		282
+#define R_AARCH64_CALL26		283
+#define R_AARCH64_LDST16_ABS_LO12_NC	284
+#define R_AARCH64_LDST32_ABS_LO12_NC	285
+#define R_AARCH64_LDST64_ABS_LO12_NC	286
+#define R_AARCH64_LDST128_ABS_LO12_NC	299
+
+#define R_AARCH64_MOVW_PREL_G0		287
+#define R_AARCH64_MOVW_PREL_G0_NC	288
+#define R_AARCH64_MOVW_PREL_G1		289
+#define R_AARCH64_MOVW_PREL_G1_NC	290
+#define R_AARCH64_MOVW_PREL_G2		291
+#define R_AARCH64_MOVW_PREL_G2_NC	292
+#define R_AARCH64_MOVW_PREL_G3		293
+
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS	ELFCLASS64
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_AARCH64
+
+#define ELF_PLATFORM_SIZE	16
+#define ELF_PLATFORM		("aarch64")
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)		((x)->e_machine == EM_AARCH64)
+
+#define elf_read_implies_exec(ex,stk)	(stk != EXSTACK_DISABLE_X)
+
+#define CORE_DUMP_USE_REGSET
+#define ELF_EXEC_PAGESIZE	PAGE_SIZE
+
+/*
+ * This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+ * use of this is to invoke "./ld.so someprog" to test out a new version of
+ * the loader.  We need to make sure that it is out of the way of the program
+ * that it will "exec", and that there is sufficient room for the brk.
+ */
+extern unsigned long randomize_et_dyn(unsigned long base);
+#define ELF_ET_DYN_BASE	(randomize_et_dyn(2 * TASK_SIZE_64 / 3))
+
+/*
+ * When the program starts, a1 contains a pointer to a function to be
+ * registered with atexit, as per the SVR4 ABI.  A value of 0 means we have no
+ * such handler.
+ */
+#define ELF_PLAT_INIT(_r, load_addr)	(_r)->regs[0] = 0
+
+extern void				elf_set_personality(int personality);
+#define SET_PERSONALITY(ex)		elf_set_personality(PER_LINUX)
+
+#define ARCH_DLINFO							\
+do {									\
+	NEW_AUX_ENT(AT_SYSINFO_EHDR,					\
+		    (elf_addr_t)current->mm->context.vdso);		\
+} while (0)
+
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
+struct linux_binprm;
+extern int arch_setup_additional_pages(struct linux_binprm *bprm,
+				       int uses_interp);
+
+/* 1GB of VA */
+#define STACK_RND_MASK			(test_thread_flag(TIF_32BIT) ? \
+						0x7ff >> (PAGE_SHIFT - 12) : \
+						0x3ffff >> (PAGE_SHIFT - 12))
+
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
+#ifdef CONFIG_AARCH32_EMULATION
+#define EM_ARM				40
+#define COMPAT_ELF_PLATFORM		("v8l")
+
+#define COMPAT_ELF_ET_DYN_BASE		(randomize_et_dyn(2 * TASK_SIZE_32 / 3))
+
+/* AArch32 registers. */
+#define COMPAT_ELF_NGREG		18
+typedef unsigned int			compat_elf_greg_t;
+typedef compat_elf_greg_t		compat_elf_gregset_t[COMPAT_ELF_NGREG];
+
+/* AArch32 EABI. */
+#define EF_ARM_EABI_MASK		0xff000000
+#define compat_elf_check_arch(x)	(((x)->e_machine == EM_ARM) && \
+					 ((x)->e_flags & EF_ARM_EABI_MASK))
+
+#define compat_start_thread		compat_start_thread
+#define COMPAT_SET_PERSONALITY(ex)	elf_set_personality(PER_LINUX32)
+#define COMPAT_ARCH_DLINFO
+extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
+				      int uses_interp);
+#define compat_arch_setup_additional_pages \
+					aarch32_setup_vectors_page
+
+#endif /* CONFIG_AARCH32_EMULATION */
+
+#endif
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
new file mode 100644
index 0000000..0cc7c03
--- /dev/null
+++ b/arch/arm64/include/asm/hwcap.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_HWCAP_H
+#define __ASM_HWCAP_H
+
+/*
+ * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
+ */
+#define HWCAP_FP		(1 << 0)
+#define HWCAP_ASIMD		(1 << 1)
+
+#ifdef CONFIG_AARCH32_EMULATION
+#define COMPAT_HWCAP_HALF	(1 << 1)
+#define COMPAT_HWCAP_THUMB	(1 << 2)
+#define COMPAT_HWCAP_FAST_MULT	(1 << 4)
+#define COMPAT_HWCAP_VFP	(1 << 6)
+#define COMPAT_HWCAP_EDSP	(1 << 7)
+#define COMPAT_HWCAP_NEON	(1 << 12)
+#define COMPAT_HWCAP_VFPv3	(1 << 13)
+#define COMPAT_HWCAP_TLS	(1 << 15)
+#define COMPAT_HWCAP_VFPv4	(1 << 16)
+#define COMPAT_HWCAP_IDIVA	(1 << 17)
+#define COMPAT_HWCAP_IDIVT	(1 << 18)
+#define COMPAT_HWCAP_IDIV	(COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
+
+#endif /* CONFIG_AARCH32_EMULATION */
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this cpu supports.
+ */
+#define ELF_HWCAP		(elf_hwcap)
+#ifdef CONFIG_AARCH32_EMULATION
+#define COMPAT_ELF_HWCAP	(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
+				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
+				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
+				 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
+				 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
+#endif
+extern unsigned int elf_hwcap;
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/param.h b/arch/arm64/include/asm/param.h
new file mode 100644
index 0000000..8e3a281
--- /dev/null
+++ b/arch/arm64/include/asm/param.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_PARAM_H
+#define __ASM_PARAM_H
+
+#define EXEC_PAGESIZE	65536
+
+#include <asm-generic/param.h>
+
+#endif
diff --git a/arch/arm64/include/asm/shmparam.h b/arch/arm64/include/asm/shmparam.h
new file mode 100644
index 0000000..4df608a
--- /dev/null
+++ b/arch/arm64/include/asm/shmparam.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SHMPARAM_H
+#define __ASM_SHMPARAM_H
+
+/*
+ * For IPC syscalls from compat tasks, we need to use the legacy 16k
+ * alignment value. Since we don't have aliasing D-caches, the rest of
+ * the time we can safely use PAGE_SIZE.
+ */
+#define COMPAT_SHMLBA	0x4000
+
+#include <asm-generic/shmparam.h>
+
+#endif /* __ASM_SHMPARAM_H */
diff --git a/arch/arm64/kernel/elf.c b/arch/arm64/kernel/elf.c
new file mode 100644
index 0000000..6f98076
--- /dev/null
+++ b/arch/arm64/kernel/elf.c
@@ -0,0 +1,41 @@
+/*
+ * ELF personality setting
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/personality.h>
+#include <linux/binfmts.h>
+#include <linux/elf.h>
+
+void elf_set_personality(int personality)
+{
+	switch (personality & PER_MASK) {
+	case PER_LINUX:
+		clear_thread_flag(TIF_32BIT);
+		break;
+	case PER_LINUX32:
+		set_thread_flag(TIF_32BIT);
+		break;
+	default:
+		pr_warning("Process %s tried to assume unknown personality %d\n",
+			   current->comm, personality);
+		return;
+	}
+
+	current->personality = personality;
+}
+EXPORT_SYMBOL(elf_set_personality);



From catalin.marinas at arm.com  Tue Aug 14 13:52:29 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:29 +0100
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>

From: Marc Zyngier <marc.zyngier at arm.com>

This patch adds support for the ARM generic timers with A64 instructions
for accessing the timer registers. It uses the physical counter as the
clock source and the virtual counter as sched_clock.

The timer frequency can be specified via DT or read from the CNTFRQ_EL0
register. The physical counter is also accessible from user space
allowing fast gettimeofday() implementation.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/timex.h    |   32 ++++
 arch/arm64/kernel/time.c          |   65 ++++++++
 drivers/clocksource/Kconfig       |    5 +
 drivers/clocksource/Makefile      |    1 +
 drivers/clocksource/arm_generic.c |  309 +++++++++++++++++++++++++++++++++++++
 include/clocksource/arm_generic.h |   21 +++
 6 files changed, 433 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/timex.h
 create mode 100644 arch/arm64/kernel/time.c
 create mode 100644 drivers/clocksource/arm_generic.c
 create mode 100644 include/clocksource/arm_generic.h

diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
new file mode 100644
index 0000000..88f74de
--- /dev/null
+++ b/arch/arm64/include/asm/timex.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_TIMEX_H
+#define __ASM_TIMEX_H
+
+/*
+ * Use the current timer as a cycle counter since this is what we use for
+ * the delay loop.
+ */
+#define get_cycles()	({ cycles_t c; read_current_timer(&c); c; })
+
+#include <asm-generic/timex.h>
+
+#define ARCH_HAS_READ_CURRENT_TIMER
+
+/* This isn't really used any more */
+#define CLOCK_TICK_RATE 1000
+
+#endif
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
new file mode 100644
index 0000000..3b4b725
--- /dev/null
+++ b/arch/arm64/kernel/time.c
@@ -0,0 +1,65 @@
+/*
+ * Based on arch/arm/kernel/time.c
+ *
+ * Copyright (C) 1991, 1992, 1995  Linus Torvalds
+ * Modifications for ARM (C) 1994-2001 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/timex.h>
+#include <linux/errno.h>
+#include <linux/profile.h>
+#include <linux/syscore_ops.h>
+#include <linux/timer.h>
+#include <linux/irq.h>
+
+#include <clocksource/arm_generic.h>
+
+#include <asm/thread_info.h>
+#include <asm/stacktrace.h>
+
+#ifdef CONFIG_SMP
+unsigned long profile_pc(struct pt_regs *regs)
+{
+	struct stackframe frame;
+
+	if (!in_lock_functions(regs->pc))
+		return regs->pc;
+
+	frame.fp = regs->regs[29];
+	frame.sp = regs->sp;
+	frame.pc = regs->pc;
+	do {
+		int ret = unwind_frame(&frame);
+		if (ret < 0)
+			return 0;
+	} while (in_lock_functions(frame.pc));
+
+	return frame.pc;
+}
+EXPORT_SYMBOL(profile_pc);
+#endif
+
+void __init time_init(void)
+{
+	arm_generic_timer_init();
+}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d53cd0a..6a78073 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -35,3 +35,8 @@ config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
 	default y
 	help
 	  Use the always on PRCMU Timer as sched_clock
+
+config CLKSRC_ARM_GENERIC
+	def_bool y if ARM64
+	help
+	  This option enables support for the ARM generic timer.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index b65d0c5..6591990 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)	+= clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)	+= time-armada-370-xp.o
+obj-$(CONFIG_CLKSRC_ARM_GENERIC)	+= arm_generic.o
diff --git a/drivers/clocksource/arm_generic.c b/drivers/clocksource/arm_generic.c
new file mode 100644
index 0000000..05c898c
--- /dev/null
+++ b/drivers/clocksource/arm_generic.c
@@ -0,0 +1,309 @@
+/*
+ * Generic timers support
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/cpu.h>
+#include <linux/jiffies.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+
+#include <clocksource/arm_generic.h>
+
+static u32 arch_timer_rate;
+static u64 sched_clock_mult __read_mostly;
+static DEFINE_PER_CPU(struct clock_event_device, arch_timer_evt);
+static int arch_timer_ppi;
+
+/*
+ * Architected system timer support.
+ */
+
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK		(1 << 1)
+
+#define ARCH_TIMER_REG_CTRL		0
+#define ARCH_TIMER_REG_FREQ		1
+#define ARCH_TIMER_REG_TVAL		2
+
+static void arch_timer_reg_write(int reg, u32 val)
+{
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
+		break;
+	default:
+		BUG();
+	}
+
+	isb();
+}
+
+static u32 arch_timer_reg_read(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_FREQ:
+		asm volatile("mrs %0,   cntfrq_el0" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
+		break;
+	default:
+		BUG();
+	}
+
+	return val;
+}
+
+static irqreturn_t arch_timer_handle_irq(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	if (ctrl & 0x4) {
+		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+		evt->event_handler(evt);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static void arch_timer_stop(void)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+}
+
+static void arch_timer_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *clk)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		arch_timer_stop();
+		break;
+	default:
+		break;
+	}
+}
+
+static int arch_timer_set_next_event(unsigned long evt,
+				     struct clock_event_device *unused)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+
+	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+
+	return 0;
+}
+
+static void __cpuinit arch_counter_enable_user_access(void)
+{
+	u32 cntkctl;
+
+	/* Disable user access to the timers and the virtual counter. */
+	asm volatile("mrs	%0, cntkctl_el1" : "=r" (cntkctl));
+	cntkctl &= ~((3 << 8) | (1 << 1));
+
+	/* Enable user access to the physical counter and frequency. */
+	cntkctl |= 1;
+	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
+}
+
+static void __cpuinit arch_timer_setup(struct clock_event_device *clk)
+{
+	/* Let's make sure the timer is off before doing anything else */
+	arch_timer_stop();
+
+	clk->features = CLOCK_EVT_FEAT_ONESHOT;
+	clk->name = "arch_sys_timer";
+	clk->rating = 400;
+	clk->set_mode = arch_timer_set_mode;
+	clk->set_next_event = arch_timer_set_next_event;
+	clk->irq = arch_timer_ppi;
+	clk->cpumask = cpumask_of(smp_processor_id());
+
+	clockevents_config_and_register(clk, arch_timer_rate,
+					0xf, 0x7fffffff);
+
+	enable_percpu_irq(clk->irq, 0);
+
+	/* Ensure the physical counter is visible to userspace for the vDSO. */
+	arch_counter_enable_user_access();
+}
+
+static void __init arch_timer_calibrate(void)
+{
+	if (arch_timer_rate == 0) {
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+		arch_timer_rate = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+
+		/* Check the timer frequency. */
+		if (arch_timer_rate == 0)
+			panic("Architected timer frequency is set to zero.\n"
+			      "You must set this in your .dts file\n");
+	}
+
+	/* Cache the sched_clock multiplier to save a divide in the hot path. */
+
+	sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
+
+	pr_info("Architected local timer running at %u.%02uMHz.\n",
+		 arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+	cycle_t cval;
+
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
+
+	return cval;
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	cycle_t cval;
+
+	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
+
+	return cval;
+}
+
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+	return arch_counter_get_cntpct();
+}
+
+static struct clocksource clocksource_counter = {
+	.name	= "arch_sys_counter",
+	.rating	= 400,
+	.read	= arch_counter_read,
+	.mask	= CLOCKSOURCE_MASK(56),
+	.flags	= (CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES),
+};
+
+int read_current_timer(unsigned long *timer_value)
+{
+	*timer_value = arch_counter_get_cntpct();
+	return 0;
+}
+
+unsigned long long notrace sched_clock(void)
+{
+	return arch_counter_get_cntvct() * sched_clock_mult;
+}
+
+static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
+					   unsigned long action, void *hcpu)
+{
+	int cpu = (long)hcpu;
+	struct clock_event_device *clk = per_cpu_ptr(&arch_timer_evt, cpu);
+
+	switch(action) {
+	case CPU_STARTING:
+	case CPU_STARTING_FROZEN:
+		arch_timer_setup(clk);
+		break;
+
+	case CPU_DYING:
+	case CPU_DYING_FROZEN:
+		pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
+			 clk->irq, cpu);
+		disable_percpu_irq(clk->irq);
+		arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+		break;
+	}
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata arch_timer_cpu_nb = {
+	.notifier_call = arch_timer_cpu_notify,
+};
+
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+	{ .compatible = "arm,armv8-timer" },
+	{},
+};
+
+int __init arm_generic_timer_init(void)
+{
+	struct device_node *np;
+	int err;
+	u32 freq;
+
+	np = of_find_matching_node(NULL, arch_timer_of_match);
+	if (!np) {
+		pr_err("arch_timer: can't find DT node\n");
+		return -ENODEV;
+	}
+
+	/* Try to determine the frequency from the device tree or CNTFRQ */
+	if (!of_property_read_u32(np, "clock-frequency", &freq))
+		arch_timer_rate = freq;
+	arch_timer_calibrate();
+
+	arch_timer_ppi = irq_of_parse_and_map(np, 0);
+	pr_info("arch_timer: found %s irq %d\n", np->name, arch_timer_ppi);
+
+	err = request_percpu_irq(arch_timer_ppi, arch_timer_handle_irq,
+				 np->name, &arch_timer_evt);
+	if (err) {
+		pr_err("arch_timer: can't register interrupt %d (%d)\n",
+		       arch_timer_ppi, err);
+		return err;
+	}
+
+	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+
+	/* Calibrate the delay loop directly */
+	lpj_fine = arch_timer_rate / HZ;
+
+	/* Immediately configure the timer on the boot CPU */
+	arch_timer_setup(per_cpu_ptr(&arch_timer_evt, smp_processor_id()));
+
+	register_cpu_notifier(&arch_timer_cpu_nb);
+
+	return 0;
+}
diff --git a/include/clocksource/arm_generic.h b/include/clocksource/arm_generic.h
new file mode 100644
index 0000000..5b41b0d
--- /dev/null
+++ b/include/clocksource/arm_generic.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CLKSOURCE_ARM_GENERIC_H
+#define __CLKSOURCE_ARM_GENERIC_H
+
+extern int arm_generic_timer_init(void);
+
+#endif



From catalin.marinas at arm.com  Tue Aug 14 13:52:20 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:20 +0100
Subject: [PATCH v2 19/31] arm64: Signal handling support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-20-git-send-email-catalin.marinas@arm.com>

This patch adds support for signal handling. The sigreturn is done via
VDSO, introduced by a previous patch. The SA_RESTORER is still defined
as it is required for 32-bit (compat) support but it is not to be used
for 64-bit applications.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/sigcontext.h |   69 ++++++
 arch/arm64/include/asm/siginfo.h    |   23 ++
 arch/arm64/include/asm/signal.h     |   24 ++
 arch/arm64/include/asm/ucontext.h   |   30 +++
 arch/arm64/kernel/signal.c          |  436 +++++++++++++++++++++++++++++++++++
 5 files changed, 582 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/sigcontext.h
 create mode 100644 arch/arm64/include/asm/siginfo.h
 create mode 100644 arch/arm64/include/asm/signal.h
 create mode 100644 arch/arm64/include/asm/ucontext.h
 create mode 100644 arch/arm64/kernel/signal.c

diff --git a/arch/arm64/include/asm/sigcontext.h b/arch/arm64/include/asm/sigcontext.h
new file mode 100644
index 0000000..573cec7
--- /dev/null
+++ b/arch/arm64/include/asm/sigcontext.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SIGCONTEXT_H
+#define __ASM_SIGCONTEXT_H
+
+#include <linux/types.h>
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.
+ */
+struct sigcontext {
+	__u64 fault_address;
+	/* AArch64 registers */
+	__u64 regs[31];
+	__u64 sp;
+	__u64 pc;
+	__u64 pstate;
+	/* 4K reserved for FP/SIMD state and future expansion */
+	__u8 __reserved[4096] __attribute__((__aligned__(16)));
+};
+
+/*
+ * Header to be used at the beginning of structures extending the user
+ * context. Such structures must be placed after the rt_sigframe on the stack
+ * and be 16-byte aligned. The last structure must be a dummy one with the
+ * magic and size set to 0.
+ */
+struct _aarch64_ctx {
+	__u32 magic;
+	__u32 size;
+};
+
+#define FPSIMD_MAGIC	0x46508001
+
+struct fpsimd_context {
+	struct _aarch64_ctx head;
+	__u32 fpsr;
+	__u32 fpcr;
+	__uint128_t vregs[32];
+};
+
+#ifdef __KERNEL__
+/*
+ * Auxiliary context saved in the sigcontext.__reserved array. Not exported to
+ * user space as it will change with the addition of new context. User space
+ * should check the magic/size information.
+ */
+struct aux_context {
+	struct fpsimd_context fpsimd;
+	/* additional context to be added before "end" */
+	struct _aarch64_ctx end;
+};
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/siginfo.h b/arch/arm64/include/asm/siginfo.h
new file mode 100644
index 0000000..5a74a08
--- /dev/null
+++ b/arch/arm64/include/asm/siginfo.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SIGINFO_H
+#define __ASM_SIGINFO_H
+
+#define __ARCH_SI_PREAMBLE_SIZE	(4 * sizeof(int))
+
+#include <asm-generic/siginfo.h>
+
+#endif
diff --git a/arch/arm64/include/asm/signal.h b/arch/arm64/include/asm/signal.h
new file mode 100644
index 0000000..8d1e723
--- /dev/null
+++ b/arch/arm64/include/asm/signal.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SIGNAL_H
+#define __ASM_SIGNAL_H
+
+/* Required for AArch32 compatibility. */
+#define SA_RESTORER	0x04000000
+
+#include <asm-generic/signal.h>
+
+#endif
diff --git a/arch/arm64/include/asm/ucontext.h b/arch/arm64/include/asm/ucontext.h
new file mode 100644
index 0000000..bde9607
--- /dev/null
+++ b/arch/arm64/include/asm/ucontext.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_UCONTEXT_H
+#define __ASM_UCONTEXT_H
+
+struct ucontext {
+	unsigned long	  uc_flags;
+	struct ucontext	 *uc_link;
+	stack_t		  uc_stack;
+	sigset_t	  uc_sigmask;
+	/* glibc uses a 1024-bit sigset_t */
+	__u8		  __unused[(1024 - sizeof(sigset_t)) / 8];
+	/* last for future expansion */
+	struct sigcontext uc_mcontext;
+};
+
+#endif /* __ASM_UCONTEXT_H */
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
new file mode 100644
index 0000000..a8f29d2
--- /dev/null
+++ b/arch/arm64/kernel/signal.c
@@ -0,0 +1,436 @@
+/*
+ * Based on arch/arm/kernel/signal.c
+ *
+ * Copyright (C) 1995-2009 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/personality.h>
+#include <linux/freezer.h>
+#include <linux/uaccess.h>
+#include <linux/tracehook.h>
+#include <linux/ratelimit.h>
+
+#include <asm/debug-monitors.h>
+#include <asm/elf.h>
+#include <asm/cacheflush.h>
+#include <asm/ucontext.h>
+#include <asm/unistd.h>
+#include <asm/fpsimd.h>
+#include <asm/signal32.h>
+#include <asm/vdso.h>
+
+/*
+ * Do a signal return; undo the signal stack. These are aligned to 128-bit.
+ */
+struct rt_sigframe {
+	struct siginfo info;
+	struct ucontext uc;
+};
+
+static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
+{
+	struct fpsimd_state *fpsimd = &current->thread.fpsimd_state;
+	int err;
+
+	/* dump the hardware registers to the fpsimd_state structure */
+	fpsimd_save_state(fpsimd);
+
+	/* copy the FP and status/control registers */
+	err = __copy_to_user(ctx->vregs, fpsimd->vregs, sizeof(fpsimd->vregs));
+	__put_user_error(fpsimd->fpsr, &ctx->fpsr, err);
+	__put_user_error(fpsimd->fpcr, &ctx->fpcr, err);
+
+	/* copy the magic/size information */
+	__put_user_error(FPSIMD_MAGIC, &ctx->head.magic, err);
+	__put_user_error(sizeof(struct fpsimd_context), &ctx->head.size, err);
+
+	return err ? -EFAULT : 0;
+}
+
+static int restore_fpsimd_context(struct fpsimd_context __user *ctx)
+{
+	struct fpsimd_state fpsimd;
+	__u32 magic, size;
+	int err = 0;
+
+	/* check the magic/size information */
+	__get_user_error(magic, &ctx->head.magic, err);
+	__get_user_error(size, &ctx->head.size, err);
+	if (err)
+		return -EFAULT;
+	if (magic != FPSIMD_MAGIC || size != sizeof(struct fpsimd_context))
+		return -EINVAL;
+
+	/* copy the FP and status/control registers */
+	err = __copy_from_user(fpsimd.vregs, ctx->vregs,
+			       sizeof(fpsimd.vregs));
+	__get_user_error(fpsimd.fpsr, &ctx->fpsr, err);
+	__get_user_error(fpsimd.fpcr, &ctx->fpcr, err);
+
+	/* load the hardware registers from the fpsimd_state structure */
+	if (!err) {
+		preempt_disable();
+		fpsimd_load_state(&fpsimd);
+		preempt_enable();
+	}
+
+	return err ? -EFAULT : 0;
+}
+
+static int restore_sigframe(struct pt_regs *regs,
+			    struct rt_sigframe __user *sf)
+{
+	sigset_t set;
+	int i, err;
+	struct aux_context __user *aux =
+		(struct aux_context __user *)sf->uc.uc_mcontext.__reserved;
+
+	err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
+	if (err == 0)
+		set_current_blocked(&set);
+
+	for (i = 0; i < 31; i++)
+		__get_user_error(regs->regs[i], &sf->uc.uc_mcontext.regs[i],
+				 err);
+	__get_user_error(regs->sp, &sf->uc.uc_mcontext.sp, err);
+	__get_user_error(regs->pc, &sf->uc.uc_mcontext.pc, err);
+	__get_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err);
+
+	/*
+	 * Avoid sys_rt_sigreturn() restarting.
+	 */
+	regs->syscallno = ~0UL;
+
+	err |= !valid_user_regs(&regs->user_regs);
+
+	if (err == 0)
+		err |= restore_fpsimd_context(&aux->fpsimd);
+
+	return err;
+}
+
+asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
+{
+	struct rt_sigframe __user *frame;
+
+	/* Always make any pending restarted system calls return -EINTR */
+	current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+	/*
+	 * Since we stacked the signal on a 128-bit boundary, then 'sp' should
+	 * be word aligned here.
+	 */
+	if (regs->sp & 15)
+		goto badframe;
+
+	frame = (struct rt_sigframe __user *)regs->sp;
+
+	if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
+		goto badframe;
+
+	if (restore_sigframe(regs, frame))
+		goto badframe;
+
+	if (do_sigaltstack(&frame->uc.uc_stack,
+			   NULL, regs->sp) == -EFAULT)
+		goto badframe;
+
+	return regs->regs[0];
+
+badframe:
+	if (show_unhandled_signals)
+		printk_ratelimited(KERN_INFO "%s[%d]: bad frame in %s: pc=%08llx sp=%08llx\n",
+				   current->comm, task_pid_nr(current), __func__,
+				   regs->pc, regs->sp);
+	force_sig(SIGSEGV, current);
+	return 0;
+}
+
+asmlinkage long sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
+				unsigned long sp)
+{
+	return do_sigaltstack(uss, uoss, sp);
+}
+
+static int setup_sigframe(struct rt_sigframe __user *sf,
+			  struct pt_regs *regs, sigset_t *set)
+{
+	int i, err = 0;
+	struct aux_context __user *aux =
+		(struct aux_context __user *)sf->uc.uc_mcontext.__reserved;
+
+	for (i = 0; i < 31; i++)
+		__put_user_error(regs->regs[i], &sf->uc.uc_mcontext.regs[i],
+				 err);
+	__put_user_error(regs->sp, &sf->uc.uc_mcontext.sp, err);
+	__put_user_error(regs->pc, &sf->uc.uc_mcontext.pc, err);
+	__put_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err);
+
+	__put_user_error(current->thread.fault_address, &sf->uc.uc_mcontext.fault_address, err);
+
+	err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set));
+
+	if (err == 0)
+		err |= preserve_fpsimd_context(&aux->fpsimd);
+
+	/* set the "end" magic */
+	__put_user_error(0, &aux->end.magic, err);
+	__put_user_error(0, &aux->end.size, err);
+
+	return err;
+}
+
+static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
+				 int framesize)
+{
+	unsigned long sp, sp_top;
+	void __user *frame;
+
+	sp = sp_top = regs->sp;
+
+	/*
+	 * This is the X/Open sanctioned signal stack switching.
+	 */
+	if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp))
+		sp = sp_top = current->sas_ss_sp + current->sas_ss_size;
+
+	/* room for stack frame (FP, LR) */
+	sp -= 16;
+
+	sp = (sp - framesize) & ~15;
+	frame = (void __user *)sp;
+
+	/*
+	 * Check that we can actually write to the signal frame.
+	 */
+	if (!access_ok(VERIFY_WRITE, frame, sp_top - sp))
+		frame = NULL;
+
+	return frame;
+}
+
+static int setup_return(struct pt_regs *regs, struct k_sigaction *ka,
+			void __user *frame, int usig)
+{
+	int err = 0;
+	__sigrestore_t sigtramp;
+	unsigned long __user *sp = (unsigned long __user *)regs->sp;
+
+	/* set up the stack frame */
+	__put_user_error(regs->regs[29], sp - 2, err);
+	__put_user_error(regs->regs[30], sp - 1, err);
+
+	regs->regs[0] = usig;
+	regs->regs[29] = regs->sp - 16;
+	regs->sp = (unsigned long)frame;
+	regs->pc = (unsigned long)ka->sa.sa_handler;
+
+	if (ka->sa.sa_flags & SA_RESTORER)
+		sigtramp = ka->sa.sa_restorer;
+	else
+		sigtramp = VDSO_SYMBOL(current->mm->context.vdso, sigtramp);
+
+	regs->regs[30] = (unsigned long)sigtramp;
+
+	return err;
+}
+
+static int setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
+			  sigset_t *set, struct pt_regs *regs)
+{
+	struct rt_sigframe __user *frame;
+	stack_t stack;
+	int err = 0;
+
+	frame = get_sigframe(ka, regs, sizeof(*frame));
+	if (!frame)
+		return 1;
+
+	__put_user_error(0, &frame->uc.uc_flags, err);
+	__put_user_error(NULL, &frame->uc.uc_link, err);
+
+	memset(&stack, 0, sizeof(stack));
+	stack.ss_sp = (void __user *)current->sas_ss_sp;
+	stack.ss_flags = sas_ss_flags(regs->sp);
+	stack.ss_size = current->sas_ss_size;
+	err |= __copy_to_user(&frame->uc.uc_stack, &stack, sizeof(stack));
+
+	err |= setup_sigframe(frame, regs, set);
+	if (err == 0)
+		err = setup_return(regs, ka, frame, usig);
+
+	if (err == 0 && ka->sa.sa_flags & SA_SIGINFO) {
+		err |= copy_siginfo_to_user(&frame->info, info);
+		regs->regs[1] = (unsigned long)&frame->info;
+		regs->regs[2] = (unsigned long)&frame->uc;
+	}
+
+	return err;
+}
+
+static void setup_restart_syscall(struct pt_regs *regs)
+{
+	if (test_thread_flag(TIF_32BIT))
+		compat_setup_restart_syscall(regs);
+	else
+		regs->regs[8] = __NR_restart_syscall;
+}
+
+/*
+ * OK, we're invoking a handler
+ */
+static void handle_signal(unsigned long sig, struct k_sigaction *ka,
+			  siginfo_t *info, struct pt_regs *regs)
+{
+	struct thread_info *thread = current_thread_info();
+	struct task_struct *tsk = current;
+	sigset_t *oldset = sigmask_to_save();
+	int usig = sig;
+	int ret;
+
+	/*
+	 * translate the signal
+	 */
+	if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap)
+		usig = thread->exec_domain->signal_invmap[usig];
+
+	/*
+	 * Set up the stack frame
+	 */
+	if (test_thread_flag(TIF_32BIT)) {
+		if (ka->sa.sa_flags & SA_SIGINFO)
+			ret = compat_setup_rt_frame(usig, ka, info, oldset,
+						    regs);
+		else
+			ret = compat_setup_frame(usig, ka, oldset, regs);
+	} else {
+		ret = setup_rt_frame(usig, ka, info, oldset, regs);
+	}
+
+	/*
+	 * Check that the resulting registers are actually sane.
+	 */
+	ret |= !valid_user_regs(&regs->user_regs);
+
+	if (ret != 0) {
+		force_sigsegv(sig, tsk);
+		return;
+	}
+
+	/*
+	 * Fast forward the stepping logic so we step into the signal
+	 * handler.
+	 */
+	user_fastforward_single_step(tsk);
+
+	signal_delivered(sig, info, ka, regs, 0);
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ *
+ * Note that we go through the signals twice: once to check the signals that
+ * the kernel can handle, and then we build all the user-level signal handling
+ * stack-frames in one go after that.
+ */
+static void do_signal(struct pt_regs *regs)
+{
+	unsigned long continue_addr = 0, restart_addr = 0;
+	struct k_sigaction ka;
+	siginfo_t info;
+	int signr, retval = 0;
+	int syscall = (int)regs->syscallno;
+
+	/*
+	 * If we were from a system call, check for system call restarting...
+	 */
+	if (syscall >= 0) {
+		continue_addr = regs->pc;
+		restart_addr = continue_addr - (compat_thumb_mode(regs) ? 2 : 4);
+		retval = regs->regs[0];
+
+		/*
+		 * Avoid additional syscall restarting via ret_to_user.
+		 */
+		regs->syscallno = ~0UL;
+
+		/*
+		 * Prepare for system call restart. We do this here so that a
+		 * debugger will see the already changed PC.
+		 */
+		switch (retval) {
+		case -ERESTARTNOHAND:
+		case -ERESTARTSYS:
+		case -ERESTARTNOINTR:
+		case -ERESTART_RESTARTBLOCK:
+			regs->regs[0] = regs->orig_x0;
+			regs->pc = restart_addr;
+			break;
+		}
+	}
+
+	/*
+	 * Get the signal to deliver. When running under ptrace, at this point
+	 * the debugger may change all of our registers.
+	 */
+	signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+	if (signr > 0) {
+		/*
+		 * Depending on the signal settings, we may need to revert the
+		 * decision to restart the system call, but skip this if a
+		 * debugger has chosen to restart at a different PC.
+		 */
+		if (regs->pc == restart_addr &&
+		    (retval == -ERESTARTNOHAND ||
+		     retval == -ERESTART_RESTARTBLOCK ||
+		     (retval == -ERESTARTSYS &&
+		      !(ka.sa.sa_flags & SA_RESTART)))) {
+			regs->regs[0] = -EINTR;
+			regs->pc = continue_addr;
+		}
+
+		handle_signal(signr, &ka, &info, regs);
+		return;
+	}
+
+	/*
+	 * Handle restarting a different system call. As above, if a debugger
+	 * has chosen to restart at a different PC, ignore the restart.
+	 */
+	if (syscall >= 0 && regs->pc == restart_addr) {
+		if (retval == -ERESTART_RESTARTBLOCK)
+			setup_restart_syscall(regs);
+		user_rewind_single_step(current);
+	}
+
+	restore_saved_sigmask();
+}
+
+asmlinkage void do_notify_resume(struct pt_regs *regs,
+				 unsigned int thread_flags)
+{
+	if (thread_flags & _TIF_SIGPENDING)
+		do_signal(regs);
+
+	if (thread_flags & _TIF_NOTIFY_RESUME) {
+		clear_thread_flag(TIF_NOTIFY_RESUME);
+		tracehook_notify_resume(regs);
+	}
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:16 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:16 +0100
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>

This patch adds SMP initialisation and spinlocks implementation for
AArch64. The spinlock support uses the new load-acquire/store-release
instructions to avoid explicit barriers. The architecture also specifies
that an event is automatically generated when clearing the exclusive
monitor state to wake up processors in WFE, so there is no need for an
explicit DSB/SEV instruction sequence. The SEVL instruction is used to
set the exclusive monitor locally as there is no conditional WFE and a
branch is more expensive.

For the SMP booting protocol, see Documentation/arm64/booting.txt.

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/hardirq.h        |    5 +
 arch/arm64/include/asm/smp.h            |   69 +++++
 arch/arm64/include/asm/spinlock.h       |  199 +++++++++++++
 arch/arm64/include/asm/spinlock_types.h |   38 +++
 arch/arm64/kernel/smp.c                 |  469 +++++++++++++++++++++++++++++++
 5 files changed, 780 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/smp.h
 create mode 100644 arch/arm64/include/asm/spinlock.h
 create mode 100644 arch/arm64/include/asm/spinlock_types.h
 create mode 100644 arch/arm64/kernel/smp.c

diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index c6c9514..5075463 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -20,8 +20,13 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
+#define NR_IPI	4
+
 typedef struct {
 	unsigned int __softirq_pending;
+#ifdef CONFIG_SMP
+	unsigned int ipi_irqs[NR_IPI];
+#endif
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
new file mode 100644
index 0000000..7e34295
--- /dev/null
+++ b/arch/arm64/include/asm/smp.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SMP_H
+#define __ASM_SMP_H
+
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/thread_info.h>
+
+#ifndef CONFIG_SMP
+# error "<asm/smp.h> included in non-SMP build"
+#endif
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+struct seq_file;
+
+/*
+ * generate IPI list text
+ */
+extern void show_ipi_list(struct seq_file *p, int prec);
+
+/*
+ * Called from C code, this handles an IPI.
+ */
+extern void handle_IPI(int ipinr, struct pt_regs *regs);
+
+/*
+ * Setup the set of possible CPUs (via set_cpu_possible)
+ */
+extern void smp_init_cpus(void);
+
+/*
+ * Provide a function to raise an IPI cross call on CPUs in callmap.
+ */
+extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
+
+/*
+ * Called from the secondary holding pen, this is the secondary CPU entry point.
+ */
+asmlinkage void secondary_start_kernel(void);
+
+/*
+ * Initial data for bringing up a secondary CPU.
+ */
+struct secondary_data {
+	void *stack;
+};
+extern struct secondary_data secondary_data;
+extern void secondary_holding_pen(void);
+extern volatile unsigned long secondary_holding_pen_release;
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+
+#endif /* ifndef __ASM_SMP_H */
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
new file mode 100644
index 0000000..34a37fb
--- /dev/null
+++ b/arch/arm64/include/asm/spinlock.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+
+#include <asm/spinlock_types.h>
+#include <asm/processor.h>
+
+/*
+ * AArch64 Spin-locking.
+ *
+ * We exclusively read the old value.  If it is zero, we may have
+ * won the lock, so we try exclusively storing it.  A memory barrier
+ * is required after we get a lock, and before we release it, because
+ * V6 CPUs are assumed to have weakly ordered memory.
+ *
+ * Unlocked value: 0
+ * Locked value: 1
+ */
+
+#define arch_spin_is_locked(x)		((x)->lock != 0)
+#define arch_spin_unlock_wait(lock) \
+	do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
+
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+
+static inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+	unsigned int tmp;
+
+	asm volatile(
+	"	sevl\n"
+	"1:	wfe\n"
+	"2:	ldaxr	%w0, [%1]\n"
+	"	cbnz	%w0, 1b\n"
+	"	stxr	%w0, %w2, [%1]\n"
+	"	cbnz	%w0, 2b\n"
+	: "=&r" (tmp)
+	: "r" (&lock->lock), "r" (1)
+	: "memory");
+}
+
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
+{
+	unsigned int tmp;
+
+	asm volatile(
+	"	ldaxr	%w0, [%1]\n"
+	"	cbnz	%w0, 1f\n"
+	"	stxr	%w0, %w2, [%1]\n"
+	"1:\n"
+	: "=&r" (tmp)
+	: "r" (&lock->lock), "r" (1)
+	: "memory");
+
+	return !tmp;
+}
+
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
+{
+	asm volatile(
+	"	stlr	%w1, [%0]\n"
+	: : "r" (&lock->lock), "r" (0) : "memory");
+}
+
+/*
+ * RWLOCKS
+ *
+ *
+ * Write locks are easy - we just set bit 31.  When unlocking, we can
+ * just write zero since the lock is exclusively held.
+ */
+
+static inline void arch_write_lock(arch_rwlock_t *rw)
+{
+	unsigned int tmp;
+
+	asm volatile(
+	"	sevl\n"
+	"1:	wfe\n"
+	"2:	ldaxr	%w0, [%1]\n"
+	"	cbnz	%w0, 1b\n"
+	"	stxr	%w0, %w2, [%1]\n"
+	"	cbnz	%w0, 2b\n"
+	: "=&r" (tmp)
+	: "r" (&rw->lock), "r" (0x80000000)
+	: "memory");
+}
+
+static inline int arch_write_trylock(arch_rwlock_t *rw)
+{
+	unsigned int tmp;
+
+	asm volatile(
+	"	ldaxr	%w0, [%1]\n"
+	"	cbnz	%w0, 1f\n"
+	"	stxr	%w0, %w2, [%1]\n"
+	"1:\n"
+	: "=&r" (tmp)
+	: "r" (&rw->lock), "r" (0x80000000)
+	: "memory");
+
+	return !tmp;
+}
+
+static inline void arch_write_unlock(arch_rwlock_t *rw)
+{
+	asm volatile(
+	"	stlr	%w1, [%0]\n"
+	: : "r" (&rw->lock), "r" (0) : "memory");
+}
+
+/* write_can_lock - would write_trylock() succeed? */
+#define arch_write_can_lock(x)		((x)->lock == 0)
+
+/*
+ * Read locks are a bit more hairy:
+ *  - Exclusively load the lock value.
+ *  - Increment it.
+ *  - Store new lock value if positive, and we still own this location.
+ *    If the value is negative, we've already failed.
+ *  - If we failed to store the value, we want a negative result.
+ *  - If we failed, try again.
+ * Unlocking is similarly hairy.  We may have multiple read locks
+ * currently active.  However, we know we won't have any write
+ * locks.
+ */
+static inline void arch_read_lock(arch_rwlock_t *rw)
+{
+	unsigned int tmp, tmp2;
+
+	asm volatile(
+	"	sevl\n"
+	"1:	wfe\n"
+	"2:	ldaxr	%w0, [%2]\n"
+	"	add	%w0, %w0, #1\n"
+	"	tbnz	%w0, #31, 1b\n"
+	"	stxr	%w1, %w0, [%2]\n"
+	"	cbnz	%w1, 2b\n"
+	: "=&r" (tmp), "=&r" (tmp2)
+	: "r" (&rw->lock)
+	: "memory");
+}
+
+static inline void arch_read_unlock(arch_rwlock_t *rw)
+{
+	unsigned int tmp, tmp2;
+
+	asm volatile(
+	"1:	ldxr	%w0, [%2]\n"
+	"	sub	%w0, %w0, #1\n"
+	"	stlxr	%w1, %w0, [%2]\n"
+	"	cbnz	%w1, 1b\n"
+	: "=&r" (tmp), "=&r" (tmp2)
+	: "r" (&rw->lock)
+	: "memory");
+}
+
+static inline int arch_read_trylock(arch_rwlock_t *rw)
+{
+	unsigned int tmp, tmp2 = 1;
+
+	asm volatile(
+	"	ldaxr	%w0, [%2]\n"
+	"	add	%w0, %w0, #1\n"
+	"	tbnz	%w0, #31, 1f\n"
+	"	stxr	%w1, %w0, [%2]\n"
+	"1:\n"
+	: "=&r" (tmp), "+r" (tmp2)
+	: "r" (&rw->lock)
+	: "memory");
+
+	return !tmp2;
+}
+
+/* read_can_lock - would read_trylock() succeed? */
+#define arch_read_can_lock(x)		((x)->lock < 0x80000000)
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)	cpu_relax()
+#define arch_read_relax(lock)	cpu_relax()
+#define arch_write_relax(lock)	cpu_relax()
+
+#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/arm64/include/asm/spinlock_types.h b/arch/arm64/include/asm/spinlock_types.h
new file mode 100644
index 0000000..9a49434
--- /dev/null
+++ b/arch/arm64/include/asm/spinlock_types.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_SPINLOCK_TYPES_H
+#define __ASM_SPINLOCK_TYPES_H
+
+#if !defined(__LINUX_SPINLOCK_TYPES_H) && !defined(__ASM_SPINLOCK_H)
+# error "please don't include this file directly"
+#endif
+
+/* We only require natural alignment for exclusive accesses. */
+#define __lock_aligned
+
+typedef struct {
+	volatile unsigned int lock;
+} arch_spinlock_t;
+
+#define __ARCH_SPIN_LOCK_UNLOCKED	{ 0 }
+
+typedef struct {
+	volatile unsigned int lock;
+} arch_rwlock_t;
+
+#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }
+
+#endif
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
new file mode 100644
index 0000000..0b03e77
--- /dev/null
+++ b/arch/arm64/kernel/smp.c
@@ -0,0 +1,469 @@
+/*
+ * SMP initialisation and IPI support
+ * Based on arch/arm/kernel/smp.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/cache.h>
+#include <linux/profile.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/err.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
+#include <linux/seq_file.h>
+#include <linux/irq.h>
+#include <linux/percpu.h>
+#include <linux/clockchips.h>
+#include <linux/completion.h>
+#include <linux/of.h>
+
+#include <asm/atomic.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/mmu_context.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/processor.h>
+#include <asm/sections.h>
+#include <asm/tlbflush.h>
+#include <asm/ptrace.h>
+#include <asm/mmu_context.h>
+
+/*
+ * as from 2.5, kernels no longer have an init_tasks structure
+ * so we need some other way of telling a new secondary core
+ * where to place its SVC stack
+ */
+struct secondary_data secondary_data;
+volatile unsigned long secondary_holding_pen_release;
+
+enum ipi_msg_type {
+	IPI_RESCHEDULE,
+	IPI_CALL_FUNC,
+	IPI_CALL_FUNC_SINGLE,
+	IPI_CPU_STOP,
+};
+
+static DEFINE_SPINLOCK(boot_lock);
+
+/*
+ * Write secondary_holding_pen_release in a way that is guaranteed to be
+ * visible to all observers, irrespective of whether they're taking part
+ * in coherency or not.  This is necessary for the hotplug code to work
+ * reliably.
+ */
+static void __cpuinit write_pen_release(int val)
+{
+	void *start = (void *)&secondary_holding_pen_release;
+	unsigned long size = sizeof(secondary_holding_pen_release);
+
+	secondary_holding_pen_release = val;
+	__cpuc_flush_dcache_area(start, size);
+}
+
+/*
+ * Boot a secondary CPU, and assign it the specified idle task.
+ * This also gives us the initial stack to use for this CPU.
+ */
+static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * Update the pen release flag.
+	 */
+	write_pen_release(cpu);
+
+	/*
+	 * Send an event, causing the secondaries to read pen_release.
+	 */
+	sev();
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		if (secondary_holding_pen_release == -1UL)
+			break;
+		udelay(10);
+	}
+
+	/*
+	 * Now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return secondary_holding_pen_release != -1 ? -ENOSYS : 0;
+}
+
+static DECLARE_COMPLETION(cpu_running);
+
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
+{
+	int ret;
+
+	/*
+	 * We need to tell the secondary core where to find its stack and the
+	 * page tables.
+	 */
+	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
+	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
+
+	/*
+	 * Now bring the CPU into our world.
+	 */
+	ret = boot_secondary(cpu, idle);
+	if (ret == 0) {
+		/*
+		 * CPU was successfully started, wait for it to come online or
+		 * time out.
+		 */
+		wait_for_completion_timeout(&cpu_running,
+					    msecs_to_jiffies(1000));
+
+		if (!cpu_online(cpu)) {
+			pr_crit("CPU%u: failed to come online\n", cpu);
+			ret = -EIO;
+		}
+	} else {
+		pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
+	}
+
+	secondary_data.stack = NULL;
+
+	return ret;
+}
+
+/*
+ * This is the secondary CPU boot entry.  We're using this CPUs
+ * idle thread stack, but a set of temporary page tables.
+ */
+asmlinkage void __cpuinit secondary_start_kernel(void)
+{
+	struct mm_struct *mm = &init_mm;
+	unsigned int cpu = smp_processor_id();
+
+	printk("CPU%u: Booted secondary processor\n", cpu);
+
+	/*
+	 * All kernel threads share the same mm context; grab a
+	 * reference and switch to it.
+	 */
+	atomic_inc(&mm->mm_count);
+	current->active_mm = mm;
+	cpumask_set_cpu(cpu, mm_cpumask(mm));
+
+	/*
+	 * TTBR0 is only used for the identity mapping at this stage. Make it
+	 * point to zero page to avoid speculatively fetching new entries.
+	 */
+	cpu_set_reserved_ttbr0();
+	flush_tlb_all();
+
+	preempt_disable();
+	trace_hardirqs_off();
+
+	/*
+	 * Let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+
+	/*
+	 * Enable local interrupts.
+	 */
+	notify_cpu_starting(cpu);
+	local_irq_enable();
+	local_fiq_enable();
+
+	/*
+	 * OK, now it's safe to let the boot CPU continue.  Wait for
+	 * the CPU migration code to notice that the CPU is online
+	 * before we continue.
+	 */
+	set_cpu_online(cpu, true);
+	while (!cpu_active(cpu))
+		cpu_relax();
+
+	/*
+	 * OK, it's off to the idle thread for us
+	 */
+	cpu_idle();
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+	unsigned long bogosum = loops_per_jiffy * num_online_cpus();
+
+	pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
+		num_online_cpus(), bogosum / (500000/HZ),
+		(bogosum / (5000/HZ)) % 100);
+}
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+static void (*smp_cross_call)(const struct cpumask *, unsigned int);
+static phys_addr_t cpu_release_addr[NR_CPUS];
+
+/*
+ * Enumerate the possible CPU set from the device tree.
+ */
+void __init smp_init_cpus(void)
+{
+	const char *enable_method;
+	struct device_node *dn = NULL;
+	int cpu = 0;
+
+	while ((dn = of_find_node_by_type(dn, "cpu"))) {
+		if (cpu >= NR_CPUS)
+			goto next;
+
+		/*
+		 * We currently support only the "spin-table" enable-method.
+		 */
+		enable_method = of_get_property(dn, "enable-method", NULL);
+		if (!enable_method || strcmp(enable_method, "spin-table")) {
+			pr_err("CPU %d: missing or invalid enable-method property: %s\n",
+			       cpu, enable_method);
+			goto next;
+		}
+
+		/*
+		 * Determine the address from which the CPU is polling.
+		 */
+		if (of_property_read_u64(dn, "cpu-release-addr",
+					 &cpu_release_addr[cpu])) {
+			pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
+			       cpu);
+			goto next;
+		}
+
+		set_cpu_possible(cpu, true);
+next:
+		cpu++;
+	}
+
+	/* sanity check */
+	if (cpu > NR_CPUS)
+		pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
+			   cpu, NR_CPUS);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	int cpu;
+	void **release_addr;
+	unsigned int ncores = num_possible_cpus();
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map (which describes the set of CPUs
+	 * actually populated at the present time) and release the
+	 * secondaries from the bootloader.
+	 */
+	for_each_possible_cpu(cpu) {
+		if (max_cpus == 0)
+			break;
+
+		if (!cpu_release_addr[cpu])
+			continue;
+
+		release_addr = __va(cpu_release_addr[cpu]);
+		release_addr[0] = (void *)__pa(secondary_holding_pen);
+		__cpuc_flush_dcache_area(release_addr, sizeof(release_addr[0]));
+
+		set_cpu_present(cpu, true);
+		max_cpus--;
+	}
+
+	/*
+	 * Send an event to wake up the secondaries.
+	 */
+	sev();
+}
+
+
+void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
+{
+	smp_cross_call = fn;
+}
+
+void arch_send_call_function_ipi_mask(const struct cpumask *mask)
+{
+	smp_cross_call(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+	smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
+}
+
+static const char *ipi_types[NR_IPI] = {
+#define S(x,s)	[x - IPI_RESCHEDULE] = s
+	S(IPI_RESCHEDULE, "Rescheduling interrupts"),
+	S(IPI_CALL_FUNC, "Function call interrupts"),
+	S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
+	S(IPI_CPU_STOP, "CPU stop interrupts"),
+};
+
+void show_ipi_list(struct seq_file *p, int prec)
+{
+	unsigned int cpu, i;
+
+	for (i = 0; i < NR_IPI; i++) {
+		seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
+			   prec >= 4 ? " " : "");
+		for_each_present_cpu(cpu)
+			seq_printf(p, "%10u ",
+				   __get_irq_stat(cpu, ipi_irqs[i]));
+		seq_printf(p, "      %s\n", ipi_types[i]);
+	}
+}
+
+u64 smp_irq_stat_cpu(unsigned int cpu)
+{
+	u64 sum = 0;
+	int i;
+
+	for (i = 0; i < NR_IPI; i++)
+		sum += __get_irq_stat(cpu, ipi_irqs[i]);
+
+	return sum;
+}
+
+static DEFINE_SPINLOCK(stop_lock);
+
+/*
+ * ipi_cpu_stop - handle IPI from smp_send_stop()
+ */
+static void ipi_cpu_stop(unsigned int cpu)
+{
+	if (system_state == SYSTEM_BOOTING ||
+	    system_state == SYSTEM_RUNNING) {
+		spin_lock(&stop_lock);
+		pr_crit("CPU%u: stopping\n", cpu);
+		dump_stack();
+		spin_unlock(&stop_lock);
+	}
+
+	set_cpu_online(cpu, false);
+
+	local_fiq_disable();
+	local_irq_disable();
+
+	while (1)
+		cpu_relax();
+}
+
+/*
+ * Main handler for inter-processor interrupts
+ */
+void handle_IPI(int ipinr, struct pt_regs *regs)
+{
+	unsigned int cpu = smp_processor_id();
+	struct pt_regs *old_regs = set_irq_regs(regs);
+
+	if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
+		__inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
+
+	switch (ipinr) {
+	case IPI_RESCHEDULE:
+		scheduler_ipi();
+		break;
+
+	case IPI_CALL_FUNC:
+		irq_enter();
+		generic_smp_call_function_interrupt();
+		irq_exit();
+		break;
+
+	case IPI_CALL_FUNC_SINGLE:
+		irq_enter();
+		generic_smp_call_function_single_interrupt();
+		irq_exit();
+		break;
+
+	case IPI_CPU_STOP:
+		irq_enter();
+		ipi_cpu_stop(cpu);
+		irq_exit();
+		break;
+
+	default:
+		pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
+		break;
+	}
+	set_irq_regs(old_regs);
+}
+
+void smp_send_reschedule(int cpu)
+{
+	smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void smp_send_stop(void)
+{
+	unsigned long timeout;
+
+	if (num_online_cpus() > 1) {
+		cpumask_t mask;
+
+		cpumask_copy(&mask, cpu_online_mask);
+		cpu_clear(smp_processor_id(), mask);
+
+		smp_cross_call(&mask, IPI_CPU_STOP);
+	}
+
+	/* Wait up to one second for other CPUs to stop */
+	timeout = USEC_PER_SEC;
+	while (num_online_cpus() > 1 && timeout--)
+		udelay(1);
+
+	if (num_online_cpus() > 1)
+		pr_warning("SMP: failed to stop secondary CPUs\n");
+}
+
+/*
+ * not supported here
+ */
+int setup_profiling_timer(unsigned int multiplier)
+{
+	return -EINVAL;
+}



From catalin.marinas at arm.com  Tue Aug 14 13:52:19 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:19 +0100
Subject: [PATCH v2 18/31] arm64: VDSO support
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-19-git-send-email-catalin.marinas@arm.com>

From: Will Deacon <will.deacon at arm.com>

This patch adds VDSO support for 64-bit applications. The VDSO code is
currently used for sys_rt_sigreturn() and optimised gettimeofday()
(using the user-accessible generic counter).

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/vdso.h              |   41 +++++
 arch/arm64/include/asm/vdso_datapage.h     |   43 +++++
 arch/arm64/kernel/vdso.c                   |  261 ++++++++++++++++++++++++++++
 arch/arm64/kernel/vdso/.gitignore          |    2 +
 arch/arm64/kernel/vdso/Makefile            |   63 +++++++
 arch/arm64/kernel/vdso/gen_vdso_offsets.sh |   15 ++
 arch/arm64/kernel/vdso/gettimeofday.S      |  242 ++++++++++++++++++++++++++
 arch/arm64/kernel/vdso/note.S              |   28 +++
 arch/arm64/kernel/vdso/sigreturn.S         |   37 ++++
 arch/arm64/kernel/vdso/vdso.S              |   33 ++++
 arch/arm64/kernel/vdso/vdso.lds.S          |  100 +++++++++++
 11 files changed, 865 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/vdso.h
 create mode 100644 arch/arm64/include/asm/vdso_datapage.h
 create mode 100644 arch/arm64/kernel/vdso.c
 create mode 100644 arch/arm64/kernel/vdso/.gitignore
 create mode 100644 arch/arm64/kernel/vdso/Makefile
 create mode 100755 arch/arm64/kernel/vdso/gen_vdso_offsets.sh
 create mode 100644 arch/arm64/kernel/vdso/gettimeofday.S
 create mode 100644 arch/arm64/kernel/vdso/note.S
 create mode 100644 arch/arm64/kernel/vdso/sigreturn.S
 create mode 100644 arch/arm64/kernel/vdso/vdso.S
 create mode 100644 arch/arm64/kernel/vdso/vdso.lds.S

diff --git a/arch/arm64/include/asm/vdso.h b/arch/arm64/include/asm/vdso.h
new file mode 100644
index 0000000..839ce00
--- /dev/null
+++ b/arch/arm64/include/asm/vdso.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Default link address for the vDSO.
+ * Since we randomise the VDSO mapping, there's little point in trying
+ * to prelink this.
+ */
+#define VDSO_LBASE	0x0
+
+#ifndef __ASSEMBLY__
+
+#include <generated/vdso-offsets.h>
+
+#define VDSO_SYMBOL(base, name)						   \
+({									   \
+	(void *)(vdso_offset_##name - VDSO_LBASE + (unsigned long)(base)); \
+})
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/arm64/include/asm/vdso_datapage.h b/arch/arm64/include/asm/vdso_datapage.h
new file mode 100644
index 0000000..de66199
--- /dev/null
+++ b/arch/arm64/include/asm/vdso_datapage.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_VDSO_DATAPAGE_H
+#define __ASM_VDSO_DATAPAGE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct vdso_data {
+	__u64 cs_cycle_last;	/* Timebase at clocksource init */
+	__u64 xtime_clock_sec;	/* Kernel time */
+	__u64 xtime_clock_nsec;
+	__u64 xtime_coarse_sec;	/* Coarse time */
+	__u64 xtime_coarse_nsec;
+	__u64 wtm_clock_sec;	/* Wall to monotonic time */
+	__u64 wtm_clock_nsec;
+	__u32 tb_seq_count;	/* Timebase sequence counter */
+	__u32 cs_mult;		/* Clocksource multiplier */
+	__u32 cs_shift;		/* Clocksource shift */
+	__u32 tz_minuteswest;	/* Whacky timezone stuff */
+	__u32 tz_dsttime;
+	__u32 use_syscall;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_DATAPAGE_H */
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
new file mode 100644
index 0000000..8d8a365
--- /dev/null
+++ b/arch/arm64/kernel/vdso.c
@@ -0,0 +1,261 @@
+/*
+ * VDSO implementation for AArch64 and vector page setup for AArch32.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/clocksource.h>
+#include <linux/elf.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/gfp.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#include <asm/cacheflush.h>
+#include <asm/signal32.h>
+#include <asm/vdso.h>
+#include <asm/vdso_datapage.h>
+
+extern char vdso_start, vdso_end;
+static unsigned long vdso_pages;
+static struct page **vdso_pagelist;
+
+/*
+ * The vDSO data page.
+ */
+static union {
+	struct vdso_data	data;
+	u8			page[PAGE_SIZE];
+} vdso_data_store __page_aligned_data;
+struct vdso_data *vdso_data = &vdso_data_store.data;
+
+#ifdef CONFIG_AARCH32_EMULATION
+/*
+ * Create and map the vectors page for AArch32 tasks.
+ */
+static struct page *vectors_page[1];
+
+static int alloc_vectors_page(void)
+{
+	extern char __kuser_helper_start[], __kuser_helper_end[];
+	int kuser_sz = __kuser_helper_end - __kuser_helper_start;
+	unsigned long vpage;
+
+	vpage = get_zeroed_page(GFP_ATOMIC);
+
+	if (!vpage)
+		return -ENOMEM;
+
+	/* kuser helpers */
+	memcpy((void *)vpage + 0x1000 - kuser_sz, __kuser_helper_start,
+		kuser_sz);
+
+	/* sigreturn code */
+	memcpy((void *)vpage + AARCH32_KERN_SIGRET_CODE_OFFSET,
+		aarch32_sigret_code, sizeof(aarch32_sigret_code));
+
+	flush_icache_range(vpage, vpage + PAGE_SIZE);
+	vectors_page[0] = virt_to_page(vpage);
+
+	return 0;
+}
+arch_initcall(alloc_vectors_page);
+
+int aarch32_setup_vectors_page(struct linux_binprm *bprm, int uses_interp)
+{
+	struct mm_struct *mm = current->mm;
+	unsigned long addr = AARCH32_VECTORS_BASE;
+	int ret;
+
+	down_write(&mm->mmap_sem);
+	current->mm->context.vdso = (void *)addr;
+
+	/* Map vectors page at the high address. */
+	ret = install_special_mapping(mm, addr, PAGE_SIZE,
+				      VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYEXEC,
+				      vectors_page);
+
+	up_write(&mm->mmap_sem);
+
+	return ret;
+}
+#endif /* CONFIG_AARCH32_EMULATION */
+
+static int __init vdso_init(void)
+{
+	struct page *pg;
+	char *vbase;
+	int i, ret = 0;
+
+	vdso_pages = (&vdso_end - &vdso_start) >> PAGE_SHIFT;
+	pr_info("vdso: %ld pages (%ld code, %ld data) at base %p\n",
+		vdso_pages + 1, vdso_pages, 1L, &vdso_start);
+
+	/* Allocate the vDSO pagelist, plus a page for the data. */
+	vdso_pagelist = kzalloc(sizeof(struct page *) * (vdso_pages + 1),
+				GFP_KERNEL);
+	if (vdso_pagelist == NULL) {
+		pr_err("Failed to allocate vDSO pagelist!\n");
+		return -ENOMEM;
+	}
+
+	/* Grab the vDSO code pages. */
+	for (i = 0; i < vdso_pages; i++) {
+		pg = virt_to_page(&vdso_start + i*PAGE_SIZE);
+		ClearPageReserved(pg);
+		get_page(pg);
+		vdso_pagelist[i] = pg;
+	}
+
+	/* Sanity check the shared object header. */
+	vbase = vmap(vdso_pagelist, 1, 0, PAGE_KERNEL);
+	if (vbase == NULL) {
+		pr_err("Failed to map vDSO pagelist!\n");
+		return -ENOMEM;
+	} else if (memcmp(vbase, "\177ELF", 4)) {
+		pr_err("vDSO is not a valid ELF object!\n");
+		ret = -EINVAL;
+		goto unmap;
+	}
+
+	/* Grab the vDSO data page. */
+	pg = virt_to_page(vdso_data);
+	get_page(pg);
+	vdso_pagelist[i] = pg;
+
+unmap:
+	vunmap(vbase);
+	return ret;
+}
+arch_initcall(vdso_init);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm,
+				int uses_interp)
+{
+	struct mm_struct *mm = current->mm;
+	unsigned long vdso_base, vdso_mapping_len;
+	int ret;
+
+	/* Be sure to map the data page */
+	vdso_mapping_len = (vdso_pages + 1) << PAGE_SHIFT;
+
+	down_write(&mm->mmap_sem);
+	vdso_base = get_unmapped_area(NULL, 0, vdso_mapping_len, 0, 0);
+	if (IS_ERR_VALUE(vdso_base)) {
+		ret = vdso_base;
+		goto up_fail;
+	}
+	mm->context.vdso = (void *)vdso_base;
+
+	ret = install_special_mapping(mm, vdso_base, vdso_mapping_len,
+				      VM_READ|VM_EXEC|
+				      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+				      vdso_pagelist);
+	if (ret) {
+		mm->context.vdso = NULL;
+		goto up_fail;
+	}
+
+up_fail:
+	up_write(&mm->mmap_sem);
+
+	return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+	/*
+	 * We can re-use the vdso pointer in mm_context_t for identifying
+	 * the vectors page for compat applications. The vDSO will always
+	 * sit above TASK_UNMAPPED_BASE and so we don't need to worry about
+	 * it conflicting with the vectors base.
+	 */
+	if (vma->vm_mm && vma->vm_start == (long)vma->vm_mm->context.vdso) {
+#ifdef CONFIG_AARCH32_EMULATION
+		if (vma->vm_start == AARCH32_VECTORS_BASE)
+			return "[vectors]";
+#endif
+		return "[vdso]";
+	}
+
+	return NULL;
+}
+
+/*
+ * We define AT_SYSINFO_EHDR, so we need these function stubs to keep
+ * Linux happy.
+ */
+int in_gate_area_no_mm(unsigned long addr)
+{
+	return 0;
+}
+
+int in_gate_area(struct mm_struct *mm, unsigned long addr)
+{
+	return 0;
+}
+
+struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
+{
+	return NULL;
+}
+
+/*
+ * Update the vDSO data page to keep in sync with kernel timekeeping.
+ */
+void update_vsyscall(struct timespec *ts, struct timespec *wtm,
+		     struct clocksource *clock, u32 mult)
+{
+	struct timespec xtime_coarse;
+	u32 use_syscall = strcmp(clock->name, "arch_sys_counter");
+
+	++vdso_data->tb_seq_count;
+	smp_wmb();
+
+	xtime_coarse = __current_kernel_time();
+	vdso_data->use_syscall			= use_syscall;
+	vdso_data->xtime_coarse_sec		= xtime_coarse.tv_sec;
+	vdso_data->xtime_coarse_nsec		= xtime_coarse.tv_nsec;
+
+	if (!use_syscall) {
+		vdso_data->cs_cycle_last	= clock->cycle_last;
+		vdso_data->xtime_clock_sec	= ts->tv_sec;
+		vdso_data->xtime_clock_nsec	= ts->tv_nsec;
+		vdso_data->cs_mult		= mult;
+		vdso_data->cs_shift		= clock->shift;
+		vdso_data->wtm_clock_sec	= wtm->tv_sec;
+		vdso_data->wtm_clock_nsec	= wtm->tv_nsec;
+	}
+
+	smp_wmb();
+	++vdso_data->tb_seq_count;
+}
+
+void update_vsyscall_tz(void)
+{
+	++vdso_data->tb_seq_count;
+	smp_wmb();
+	vdso_data->tz_minuteswest	= sys_tz.tz_minuteswest;
+	vdso_data->tz_dsttime		= sys_tz.tz_dsttime;
+	smp_wmb();
+	++vdso_data->tb_seq_count;
+}
diff --git a/arch/arm64/kernel/vdso/.gitignore b/arch/arm64/kernel/vdso/.gitignore
new file mode 100644
index 0000000..b8cc94e
--- /dev/null
+++ b/arch/arm64/kernel/vdso/.gitignore
@@ -0,0 +1,2 @@
+vdso.lds
+vdso-offsets.h
diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile
new file mode 100644
index 0000000..d8064af
--- /dev/null
+++ b/arch/arm64/kernel/vdso/Makefile
@@ -0,0 +1,63 @@
+#
+# Building a vDSO image for AArch64.
+#
+# Author: Will Deacon <will.deacon at arm.com>
+# Heavily based on the vDSO Makefiles for other archs.
+#
+
+obj-vdso := gettimeofday.o note.o sigreturn.o
+
+# Build rules
+targets := $(obj-vdso) vdso.so vdso.so.dbg
+obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
+
+ccflags-y := -shared -fno-common -fno-builtin
+ccflags-y += -nostdlib -Wl,-soname=linux-vdso.so.1 \
+		$(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
+
+obj-y += vdso.o
+extra-y += vdso.lds vdso-offsets.h
+CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
+
+# Force dependency (incbin is bad)
+$(obj)/vdso.o : $(obj)/vdso.so
+
+# Link rule for the .so file, .lds has to be first
+$(obj)/vdso.so.dbg: $(src)/vdso.lds $(obj-vdso)
+	$(call if_changed,vdsold)
+
+# Strip rule for the .so file
+$(obj)/%.so: OBJCOPYFLAGS := -S
+$(obj)/%.so: $(obj)/%.so.dbg FORCE
+	$(call if_changed,objcopy)
+
+# Generate VDSO offsets using helper script
+gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh
+quiet_cmd_vdsosym = VDSOSYM $@
+define cmd_vdsosym
+	$(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ && \
+	cp $@ include/generated/
+endef
+
+$(obj)/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE
+	$(call if_changed,vdsosym)
+
+# Assembly rules for the .S files
+$(obj-vdso): %.o: %.S
+	$(call if_changed_dep,vdsoas)
+
+# Actual build commands
+quiet_cmd_vdsold = VDSOL $@
+      cmd_vdsold = $(CC) $(c_flags) -Wl,-T $^ -o $@
+quiet_cmd_vdsoas = VDSOA $@
+      cmd_vdsoas = $(CC) $(a_flags) -c -o $@ $<
+
+# Install commands for the unstripped file
+quiet_cmd_vdso_install = INSTALL $@
+      cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@
+
+vdso.so: $(obj)/vdso.so.dbg
+	@mkdir -p $(MODLIB)/vdso
+	$(call cmd,vdso_install)
+
+vdso_install: vdso.so
diff --git a/arch/arm64/kernel/vdso/gen_vdso_offsets.sh b/arch/arm64/kernel/vdso/gen_vdso_offsets.sh
new file mode 100755
index 0000000..01924ff
--- /dev/null
+++ b/arch/arm64/kernel/vdso/gen_vdso_offsets.sh
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+#
+# Match symbols in the DSO that look like VDSO_*; produce a header file
+# of constant offsets into the shared object.
+#
+# Doing this inside the Makefile will break the $(filter-out) function,
+# causing Kbuild to rebuild the vdso-offsets header file every time.
+#
+# Author: Will Deacon <will.deacon at arm.com
+#
+
+LC_ALL=C
+sed -n -e 's/^00*/0/' -e \
+'s/^\([0-9a-fA-F]*\) . VDSO_\([a-zA-Z0-9_]*\)$/\#define vdso_offset_\2\t0x\1/p'
diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S
new file mode 100644
index 0000000..dcb8c20
--- /dev/null
+++ b/arch/arm64/kernel/vdso/gettimeofday.S
@@ -0,0 +1,242 @@
+/*
+ * Userspace implementations of gettimeofday() and friends.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/unistd.h>
+
+#define NSEC_PER_SEC_LO16	0xca00
+#define NSEC_PER_SEC_HI16	0x3b9a
+
+vdso_data	.req	x6
+use_syscall	.req	w7
+seqcnt		.req	w8
+
+	.macro	seqcnt_acquire
+9999:	ldr	seqcnt, [vdso_data, #VDSO_TB_SEQ_COUNT]
+	tbnz	seqcnt, #0, 9999b
+	dmb	ishld
+	ldr	use_syscall, [vdso_data, #VDSO_USE_SYSCALL]
+	.endm
+
+	.macro	seqcnt_read, cnt
+	dmb	ishld
+	ldr	\cnt, [vdso_data, #VDSO_TB_SEQ_COUNT]
+	.endm
+
+	.macro	seqcnt_check, cnt, fail
+	cmp	\cnt, seqcnt
+	b.ne	\fail
+	.endm
+
+	.text
+
+/* int __kernel_gettimeofday(struct timeval *tv, struct timezone *tz); */
+ENTRY(__kernel_gettimeofday)
+	.cfi_startproc
+	mov	x2, x30
+	.cfi_register x30, x2
+
+	/* Acquire the sequence counter and get the timespec. */
+	adr	vdso_data, _vdso_data
+1:	seqcnt_acquire
+	cbnz	use_syscall, 4f
+
+	/* If tv is NULL, skip to the timezone code. */
+	cbz	x0, 2f
+	bl	__do_get_tspec
+	seqcnt_check w13, 1b
+
+	/* Convert ns to us. */
+	mov	x11, #1000
+	udiv	x10, x10, x11
+	stp	x9, x10, [x0, #TVAL_TV_SEC]
+2:
+	/* If tz is NULL, return 0. */
+	cbz	x1, 3f
+	ldp	w4, w5, [vdso_data, #VDSO_TZ_MINWEST]
+	seqcnt_read w13
+	seqcnt_check w13, 1b
+	stp	w4, w5, [x1, #TZ_MINWEST]
+3:
+	mov	x0, xzr
+	ret	x2
+4:
+	/* Syscall fallback. */
+	mov	x8, #__NR_gettimeofday
+	svc	#0
+	ret	x2
+	.cfi_endproc
+ENDPROC(__kernel_gettimeofday)
+
+/* int __kernel_clock_gettime(clockid_t clock_id, struct timespec *tp); */
+ENTRY(__kernel_clock_gettime)
+	.cfi_startproc
+	cmp	w0, #CLOCK_REALTIME
+	ccmp	w0, #CLOCK_MONOTONIC, #0x4, ne
+	b.ne	2f
+
+	mov	x2, x30
+	.cfi_register x30, x2
+
+	/* Get kernel timespec. */
+	adr	vdso_data, _vdso_data
+1:	seqcnt_acquire
+	cbnz	use_syscall, 7f
+
+	bl	__do_get_tspec
+	seqcnt_check w13, 1b
+
+	cmp	w0, #CLOCK_MONOTONIC
+	b.ne	6f
+
+	/* Get wtm timespec. */
+	ldp	x14, x15, [vdso_data, #VDSO_WTM_CLK_SEC]
+
+	/* Check the sequence counter. */
+	seqcnt_read w13
+	seqcnt_check w13, 1b
+	b	4f
+2:
+	cmp	w0, #CLOCK_REALTIME_COARSE
+	ccmp	w0, #CLOCK_MONOTONIC_COARSE, #0x4, ne
+	b.ne	8f
+
+	/* Get coarse timespec. */
+	adr	vdso_data, _vdso_data
+3:	seqcnt_acquire
+	ldp	x9, x10, [vdso_data, #VDSO_XTIME_CRS_SEC]
+
+	cmp	w0, #CLOCK_MONOTONIC_COARSE
+	b.ne	6f
+
+	/* Get wtm timespec. */
+	ldp	x14, x15, [vdso_data, #VDSO_WTM_CLK_SEC]
+
+	/* Check the sequence counter. */
+	seqcnt_read w13
+	seqcnt_check w13, 3b
+4:
+	/* Add on wtm timespec. */
+	add	x9, x9, x14
+	add	x10, x10, x15
+
+	/* Normalise the new timespec. */
+	mov	x14, #NSEC_PER_SEC_LO16
+	movk	x14, #NSEC_PER_SEC_HI16, lsl #16
+	cmp	x10, x14
+	b.lt	5f
+	sub	x10, x10, x14
+	add	x9, x9, #1
+5:
+	cmp	x10, #0
+	b.ge	6f
+	add	x10, x10, x14
+	sub	x9, x9, #1
+
+6:	/* Store to the user timespec. */
+	stp	x9, x10, [x1, #TSPEC_TV_SEC]
+	mov	x0, xzr
+	ret	x2
+7:
+	mov	x30, x2
+8:	/* Syscall fallback. */
+	mov	x8, #__NR_clock_gettime
+	svc	#0
+	ret
+	.cfi_endproc
+ENDPROC(__kernel_clock_gettime)
+
+/* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res); */
+ENTRY(__kernel_clock_getres)
+	.cfi_startproc
+	cbz	w1, 3f
+
+	cmp	w0, #CLOCK_REALTIME
+	ccmp	w0, #CLOCK_MONOTONIC, #0x4, ne
+	b.ne	1f
+
+	ldr	x2, 5f
+	b	2f
+1:
+	cmp	w0, #CLOCK_REALTIME_COARSE
+	ccmp	w0, #CLOCK_MONOTONIC_COARSE, #0x4, ne
+	b.ne	4f
+	ldr	x2, 6f
+2:
+	stp	xzr, x2, [x1]
+
+3:	/* res == NULL. */
+	mov	w0, wzr
+	ret
+
+4:	/* Syscall fallback. */
+	mov	x8, #__NR_clock_getres
+	svc	#0
+	ret
+5:
+	.quad	CLOCK_REALTIME_RES
+6:
+	.quad	CLOCK_COARSE_RES
+	.cfi_endproc
+ENDPROC(__kernel_clock_getres)
+
+/*
+ * Read the current time from the architected counter.
+ * Expects vdso_data to be initialised.
+ * Clobbers the temporary registers (x9 - x15).
+ * Returns:
+ *  - (x9, x10) = (ts->tv_sec, ts->tv_nsec)
+ *  - (x11, x12) = (xtime->tv_sec, xtime->tv_nsec)
+ *  - w13 = vDSO sequence counter
+ */
+ENTRY(__do_get_tspec)
+	.cfi_startproc
+
+	/* Read from the vDSO data page. */
+	ldr	x10, [vdso_data, #VDSO_CS_CYCLE_LAST]
+	ldp	x11, x12, [vdso_data, #VDSO_XTIME_CLK_SEC]
+	ldp	w14, w15, [vdso_data, #VDSO_CS_MULT]
+	seqcnt_read w13
+
+	/* Read the physical counter. */
+	isb
+	mrs	x9, cntpct_el0
+
+	/* Calculate cycle delta and convert to ns. */
+	sub	x10, x9, x10
+	/* We can only guarantee 56 bits of precision. */
+	movn	x9, #0xff0, lsl #48
+	and	x10, x9, x10
+	mul	x10, x10, x14
+	lsr	x10, x10, x15
+
+	/* Use the kernel time to calculate the new timespec. */
+	add	x10, x12, x10
+	mov	x14, #NSEC_PER_SEC_LO16
+	movk	x14, #NSEC_PER_SEC_HI16, lsl #16
+	udiv	x15, x10, x14
+	add	x9, x15, x11
+	mul	x14, x14, x15
+	sub	x10, x10, x14
+
+	ret
+	.cfi_endproc
+ENDPROC(__do_get_tspec)
diff --git a/arch/arm64/kernel/vdso/note.S b/arch/arm64/kernel/vdso/note.S
new file mode 100644
index 0000000..b82c85e
--- /dev/null
+++ b/arch/arm64/kernel/vdso/note.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ *
+ * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text.
+ * Here we can supply some information useful to userland.
+ */
+
+#include <linux/uts.h>
+#include <linux/version.h>
+#include <linux/elfnote.h>
+
+ELFNOTE_START(Linux, 0, "a")
+	.long LINUX_VERSION_CODE
+ELFNOTE_END
diff --git a/arch/arm64/kernel/vdso/sigreturn.S b/arch/arm64/kernel/vdso/sigreturn.S
new file mode 100644
index 0000000..20d98ef
--- /dev/null
+++ b/arch/arm64/kernel/vdso/sigreturn.S
@@ -0,0 +1,37 @@
+/*
+ * Sigreturn trampoline for returning from a signal when the SA_RESTORER
+ * flag is not set.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+
+	.text
+
+	nop
+ENTRY(__kernel_rt_sigreturn)
+	.cfi_startproc
+	.cfi_signal_frame
+	.cfi_def_cfa	x29, 0
+	.cfi_offset	x29, 0 * 8
+	.cfi_offset	x30, 1 * 8
+	mov	x8, #__NR_rt_sigreturn
+	svc	#0
+	.cfi_endproc
+ENDPROC(__kernel_rt_sigreturn)
diff --git a/arch/arm64/kernel/vdso/vdso.S b/arch/arm64/kernel/vdso/vdso.S
new file mode 100644
index 0000000..60c1db5
--- /dev/null
+++ b/arch/arm64/kernel/vdso/vdso.S
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/page.h>
+
+	__PAGE_ALIGNED_DATA
+
+	.globl vdso_start, vdso_end
+	.balign PAGE_SIZE
+vdso_start:
+	.incbin "arch/arm64/kernel/vdso/vdso.so"
+	.balign PAGE_SIZE
+vdso_end:
+
+	.previous
diff --git a/arch/arm64/kernel/vdso/vdso.lds.S b/arch/arm64/kernel/vdso/vdso.lds.S
new file mode 100644
index 0000000..8154b8d
--- /dev/null
+++ b/arch/arm64/kernel/vdso/vdso.lds.S
@@ -0,0 +1,100 @@
+/*
+ * GNU linker script for the VDSO library.
+*
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ * Heavily based on the vDSO linker scripts for other archs.
+ */
+
+#include <linux/const.h>
+#include <asm/page.h>
+#include <asm/vdso.h>
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-bigaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+
+SECTIONS
+{
+	. = VDSO_LBASE + SIZEOF_HEADERS;
+
+	.hash		: { *(.hash) }			:text
+	.gnu.hash	: { *(.gnu.hash) }
+	.dynsym		: { *(.dynsym) }
+	.dynstr		: { *(.dynstr) }
+	.gnu.version	: { *(.gnu.version) }
+	.gnu.version_d	: { *(.gnu.version_d) }
+	.gnu.version_r	: { *(.gnu.version_r) }
+
+	.note		: { *(.note.*) }		:text	:note
+
+	. = ALIGN(16);
+
+	.text		: { *(.text*) }			:text	=0xd503201f
+	PROVIDE (__etext = .);
+	PROVIDE (_etext = .);
+	PROVIDE (etext = .);
+
+	.eh_frame_hdr	: { *(.eh_frame_hdr) }		:text	:eh_frame_hdr
+	.eh_frame	: { KEEP (*(.eh_frame)) }	:text
+
+	.dynamic	: { *(.dynamic) }		:text	:dynamic
+
+	.rodata		: { *(.rodata*) }		:text
+
+	_end = .;
+	PROVIDE(end = .);
+
+	. = ALIGN(PAGE_SIZE);
+	PROVIDE(_vdso_data = .);
+
+	/DISCARD/	: {
+		*(.note.GNU-stack)
+		*(.data .data.* .gnu.linkonce.d.* .sdata*)
+		*(.bss .sbss .dynbss .dynsbss)
+	}
+}
+
+/*
+ * We must supply the ELF program headers explicitly to get just one
+ * PT_LOAD segment, and set the flags explicitly to make segments read-only.
+ */
+PHDRS
+{
+	text		PT_LOAD		FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */
+	dynamic		PT_DYNAMIC	FLAGS(4);		/* PF_R */
+	note		PT_NOTE		FLAGS(4);		/* PF_R */
+	eh_frame_hdr	PT_GNU_EH_FRAME;
+}
+
+/*
+ * This controls what symbols we export from the DSO.
+ */
+VERSION
+{
+	LINUX_2.6.39 {
+	global:
+		__kernel_rt_sigreturn;
+		__kernel_gettimeofday;
+		__kernel_clock_gettime;
+		__kernel_clock_getres;
+	local: *;
+	};
+}
+
+/*
+ * Make the sigreturn code visible to the kernel.
+ */
+VDSO_sigtramp		= __kernel_rt_sigreturn;



From catalin.marinas at arm.com  Tue Aug 14 13:52:21 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 14 Aug 2012 18:52:21 +0100
Subject: [PATCH v2 20/31] arm64: User access library functions
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <1344966752-16102-21-git-send-email-catalin.marinas@arm.com>

This patch add support for various user access functions. These
functions use the standard LDR/STR instructions and not the LDRT/STRT
variants in order to allow kernel addresses (after set_fs(KERNEL_DS)).

Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm64/include/asm/uaccess.h   |  377 ++++++++++++++++++++++++++++++++++++
 arch/arm64/lib/clear_user.S        |   58 ++++++
 arch/arm64/lib/copy_from_user.S    |   66 +++++++
 arch/arm64/lib/copy_in_user.S      |   63 ++++++
 arch/arm64/lib/copy_to_user.S      |   61 ++++++
 arch/arm64/lib/getuser.S           |   75 +++++++
 arch/arm64/lib/putuser.S           |   73 +++++++
 arch/arm64/lib/strncpy_from_user.S |   50 +++++
 arch/arm64/lib/strnlen_user.S      |   47 +++++
 9 files changed, 870 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/include/asm/uaccess.h
 create mode 100644 arch/arm64/lib/clear_user.S
 create mode 100644 arch/arm64/lib/copy_from_user.S
 create mode 100644 arch/arm64/lib/copy_in_user.S
 create mode 100644 arch/arm64/lib/copy_to_user.S
 create mode 100644 arch/arm64/lib/getuser.S
 create mode 100644 arch/arm64/lib/putuser.S
 create mode 100644 arch/arm64/lib/strncpy_from_user.S
 create mode 100644 arch/arm64/lib/strnlen_user.S

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
new file mode 100644
index 0000000..09d7b53
--- /dev/null
+++ b/arch/arm64/include/asm/uaccess.h
@@ -0,0 +1,377 @@
+/*
+ * Based on arch/arm/include/asm/uaccess.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_UACCESS_H
+#define __ASM_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/string.h>
+#include <linux/thread_info.h>
+
+#include <asm/ptrace.h>
+#include <asm/errno.h>
+#include <asm/memory.h>
+#include <asm/compiler.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+	unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+/*
+ * These two are intentionally not defined anywhere - if the kernel
+ * code generates any references to them, that's a bug.
+ */
+extern long __get_user_bad(void);
+extern long __put_user_bad(void);
+
+#define KERNEL_DS	(-1UL)
+#define get_ds()	(KERNEL_DS)
+
+#define USER_DS		TASK_SIZE_64
+#define get_fs()	(current_thread_info()->addr_limit)
+
+static inline void set_fs(mm_segment_t fs)
+{
+	current_thread_info()->addr_limit = fs;
+}
+
+#define segment_eq(a,b)	((a) == (b))
+
+/*
+ * Return 1 if addr < current->addr_limit, 0 otherwise.
+ */
+#define __addr_ok(addr)							\
+({									\
+	unsigned long flag;						\
+	asm("cmp %1, %0; cset %0, lo"				\
+		: "=&r" (flag)						\
+		: "r" (addr), "0" (current_thread_info()->addr_limit)	\
+		: "cc");						\
+	flag;								\
+})
+
+/*
+ * Test whether a block of memory is a valid user space address.
+ * Returns 1 if the range is valid, 0 otherwise.
+ *
+ * This is equivalent to the following test:
+ * (u65)addr + (u65)size < (u65)current->addr_limit
+ *
+ * This needs 65-bit arithmetic.
+ */
+#define __range_ok(addr,size)						\
+({									\
+	unsigned long flag, roksum;					\
+	__chk_user_ptr(addr);						\
+	asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, cc"	\
+		: "=&r" (flag), "=&r" (roksum)				\
+		: "1" (addr), "Ir" (size),				\
+		  "r" (current_thread_info()->addr_limit)		\
+		: "cc");						\
+	flag;								\
+})
+
+/*
+ * Single-value transfer routines.  They automatically use the right
+ * size if we just have the right pointer type.  Note that the functions
+ * which read from user space (*get_*) need to take care not to leak
+ * kernel data even if the calling code is buggy and fails to check
+ * the return value.  This means zeroing out the destination variable
+ * or buffer on error.  Normally this is done out of line by the
+ * fixup code, but there are a few places where it intrudes on the
+ * main code path.  When we only write to user space, there is no
+ * problem.
+ */
+extern long __get_user_1(void *);
+extern long __get_user_2(void *);
+extern long __get_user_4(void *);
+extern long __get_user_8(void *);
+
+#define __get_user_x(__r2,__p,__e,__s,__i...)				\
+	   asm volatile(						\
+		__asmeq("%0", "x0") __asmeq("%1", "x2")			\
+		"bl	__get_user_" #__s				\
+		: "=&r" (__e), "=r" (__r2)				\
+		: "0" (__p)						\
+		: __i, "cc")
+
+#define get_user(x,p)							\
+	({								\
+		register const typeof(*(p)) __user *__p asm("x0") = (p);\
+		register unsigned long __r2 asm("x2");			\
+		register long __e asm("x0");				\
+		switch (sizeof(*(__p))) {				\
+		case 1:							\
+			__get_user_x(__r2, __p, __e, 1, "x30");		\
+			break;						\
+		case 2:							\
+			__get_user_x(__r2, __p, __e, 2, "x3", "x30");	\
+			break;						\
+		case 4:							\
+			__get_user_x(__r2, __p, __e, 4, "x30");		\
+			break;						\
+		case 8:							\
+			__get_user_x(__r2, __p, __e, 8, "x30");		\
+			break;						\
+		default: __e = __get_user_bad(); break;			\
+		}							\
+		x = (typeof(*(p))) __r2;				\
+		__e;							\
+	})
+
+#define __get_user_unaligned __get_user
+
+extern long __put_user_1(void *, unsigned long);
+extern long __put_user_2(void *, unsigned long);
+extern long __put_user_4(void *, unsigned long);
+extern long __put_user_8(void *, unsigned long);
+
+#define __put_user_x(__r2,__p,__e,__s)					\
+	   asm volatile(						\
+		__asmeq("%0", "x0") __asmeq("%2", "x2")			\
+		"bl	__put_user_" #__s				\
+		: "=&r" (__e)						\
+		: "0" (__p), "r" (__r2)					\
+		: "x8", "x30", "cc")
+
+#define put_user(x,p)							\
+	({								\
+		register const typeof(*(p)) __r2 asm("x2") = (x);	\
+		register const typeof(*(p)) __user *__p asm("x0") = (p);\
+		register long __e asm("x0");				\
+		switch (sizeof(*(__p))) {				\
+		case 1:							\
+			__put_user_x(__r2, __p, __e, 1);		\
+			break;						\
+		case 2:							\
+			__put_user_x(__r2, __p, __e, 2);		\
+			break;						\
+		case 4:							\
+			__put_user_x(__r2, __p, __e, 4);		\
+			break;						\
+		case 8:							\
+			__put_user_x(__r2, __p, __e, 8);		\
+			break;						\
+		default: __e = __put_user_bad(); break;			\
+		}							\
+		__e;							\
+	})
+
+#define __put_user_unaligned __put_user
+
+#define access_ok(type,addr,size)	__range_ok(addr,size)
+
+/*
+ * The "__xxx" versions of the user access functions do not verify the
+ * address space - it must have been done previously with a separate
+ * "access_ok()" call.
+ *
+ * The "xxx_error" versions set the third argument to EFAULT if an
+ * error occurs, and leave it unchanged on success.  Note that these
+ * versions are void (ie, don't return a value as such).
+ */
+#define __get_user(x,ptr)						\
+({									\
+	long __gu_err = 0;						\
+	__get_user_err((x),(ptr),__gu_err);				\
+	__gu_err;							\
+})
+
+#define __get_user_error(x,ptr,err)					\
+({									\
+	__get_user_err((x),(ptr),err);					\
+	(void) 0;							\
+})
+
+#define __get_user_err(x,ptr,err)					\
+do {									\
+	unsigned long __gu_addr = (unsigned long)(ptr);			\
+	unsigned long __gu_val;						\
+	__chk_user_ptr(ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		__get_user_asm("ldrb", "%w", __gu_val, __gu_addr, err);	\
+		break;							\
+	case 2:								\
+		__get_user_asm("ldrh", "%w", __gu_val, __gu_addr, err);	\
+		break;							\
+	case 4:								\
+		__get_user_asm("ldr", "%w", __gu_val, __gu_addr, err);	\
+		break;							\
+	case 8:								\
+		__get_user_asm("ldr", "%",  __gu_val, __gu_addr, err);	\
+		break;							\
+	default:							\
+		(__gu_val) = __get_user_bad();				\
+	}								\
+	(x) = (__typeof__(*(ptr)))__gu_val;				\
+} while (0)
+
+#define __get_user_asm(instr, reg, x, addr, err)			\
+	asm volatile(							\
+	"1:	" instr "	" reg "1, [%2]\n"			\
+	"2:\n"								\
+	"	.section .fixup, \"ax\"\n"				\
+	"	.align	2\n"						\
+	"3:	mov	%0, %3\n"					\
+	"	mov	%1, #0\n"					\
+	"	b	2b\n"						\
+	"	.previous\n"						\
+	"	.section __ex_table,\"a\"\n"				\
+	"	.align	3\n"						\
+	"	.quad	1b, 3b\n"					\
+	"	.previous"						\
+	: "+r" (err), "=&r" (x)						\
+	: "r" (addr), "i" (-EFAULT)					\
+	: "cc")
+
+#define __put_user(x,ptr)						\
+({									\
+	long __pu_err = 0;						\
+	__put_user_err((x),(ptr),__pu_err);				\
+	__pu_err;							\
+})
+
+#define __put_user_error(x,ptr,err)					\
+({									\
+	__put_user_err((x),(ptr),err);					\
+	(void) 0;							\
+})
+
+#define __put_user_err(x,ptr,err)					\
+do {									\
+	unsigned long __pu_addr = (unsigned long)(ptr);			\
+	__typeof__(*(ptr)) __pu_val = (x);				\
+	__chk_user_ptr(ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		__put_user_asm("strb", "%w", __pu_val, __pu_addr, err);	\
+		break;							\
+	case 2:								\
+		__put_user_asm("strh", "%w", __pu_val, __pu_addr, err);	\
+		break;							\
+	case 4:								\
+		__put_user_asm("str",  "%w", __pu_val, __pu_addr, err);	\
+		break;							\
+	case 8:								\
+		__put_user_asm("str",  "%",  __pu_val, __pu_addr, err);	\
+		break;							\
+	default:							\
+		__put_user_bad();					\
+	}								\
+} while (0)
+
+#define __put_user_asm(instr, reg, x, __pu_addr, err)			\
+	asm volatile(							\
+	"1:	" instr "	" reg "1, [%2]\n"			\
+	"2:\n"								\
+	"	.section .fixup,\"ax\"\n"				\
+	"	.align	2\n"						\
+	"3:	mov	%0, %3\n"					\
+	"	b	2b\n"						\
+	"	.previous\n"						\
+	"	.section __ex_table,\"a\"\n"				\
+	"	.align	3\n"						\
+	"	.quad	1b, 3b\n"					\
+	"	.previous"						\
+	: "+r" (err)							\
+	: "r" (x), "r" (__pu_addr), "i" (-EFAULT)			\
+	: "cc")
+
+extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
+extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
+extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n);
+extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
+
+extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count);
+extern unsigned long __must_check __strnlen_user(const char __user *s, long n);
+
+static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+	if (access_ok(VERIFY_READ, from, n))
+		n = __copy_from_user(to, from, n);
+	else /* security hole - plug it */
+		memset(to, 0, n);
+	return n;
+}
+
+static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+	if (access_ok(VERIFY_WRITE, to, n))
+		n = __copy_to_user(to, from, n);
+	return n;
+}
+
+static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n)
+{
+	if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n))
+		n = __copy_in_user(to, from, n);
+	return n;
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+static inline unsigned long __must_check clear_user(void __user *to, unsigned long n)
+{
+	if (access_ok(VERIFY_WRITE, to, n))
+		n = __clear_user(to, n);
+	return n;
+}
+
+static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count)
+{
+	long res = -EFAULT;
+	if (access_ok(VERIFY_READ, src, 1))
+		res = __strncpy_from_user(dst, src, count);
+	return res;
+}
+
+#define strlen_user(s)	strnlen_user(s, ~0UL >> 1)
+
+static inline long __must_check strnlen_user(const char __user *s, long n)
+{
+	unsigned long res = 0;
+
+	if (__addr_ok(s))
+		res = __strnlen_user(s, n);
+
+	return res;
+}
+
+#endif /* __ASM_UACCESS_H */
diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S
new file mode 100644
index 0000000..6e0ed93
--- /dev/null
+++ b/arch/arm64/lib/clear_user.S
@@ -0,0 +1,58 @@
+/*
+ * Based on arch/arm/lib/clear_user.S
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+	.text
+
+/* Prototype: int __clear_user(void *addr, size_t sz)
+ * Purpose  : clear some user memory
+ * Params   : addr - user memory address to clear
+ *          : sz   - number of bytes to clear
+ * Returns  : number of bytes NOT cleared
+ *
+ * Alignment fixed up by hardware.
+ */
+ENTRY(__clear_user)
+	mov	x2, x1			// save the size for fixup return
+	subs	x1, x1, #8
+	b.mi	2f
+1:
+USER(9f, str	xzr, [x0], #8	)
+	subs	x1, x1, #8
+	b.pl	1b
+2:	adds	x1, x1, #4
+	b.mi	3f
+USER(9f, str	wzr, [x0], #4	)
+	sub	x1, x1, #4
+3:	adds	x1, x1, #2
+	b.mi	4f
+USER(9f, strh	wzr, [x0], #2	)
+	sub	x1, x1, #2
+4:	adds	x1, x1, #1
+	b.mi	5f
+	strb	wzr, [x0]
+5:	mov	x0, #0
+	ret
+ENDPROC(__clear_user)
+
+	.section .fixup,"ax"
+	.align	2
+9:	mov	x0, x2			// return the original size
+	ret
+	.previous
diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S
new file mode 100644
index 0000000..5e27add
--- /dev/null
+++ b/arch/arm64/lib/copy_from_user.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Copy from user space to a kernel buffer (alignment handled by the hardware)
+ *
+ * Parameters:
+ *	x0 - to
+ *	x1 - from
+ *	x2 - n
+ * Returns:
+ *	x0 - bytes not copied
+ */
+ENTRY(__copy_from_user)
+	add	x4, x1, x2			// upper user buffer boundary
+	subs	x2, x2, #8
+	b.mi	2f
+1:
+USER(9f, ldr	x3, [x1], #8	)
+	subs	x2, x2, #8
+	str	x3, [x0], #8
+	b.pl	1b
+2:	adds	x2, x2, #4
+	b.mi	3f
+USER(9f, ldr	w3, [x1], #4	)
+	sub	x2, x2, #4
+	str	w3, [x0], #4
+3:	adds	x2, x2, #2
+	b.mi	4f
+USER(9f, ldrh	w3, [x1], #2	)
+	sub	x2, x2, #2
+	strh	w3, [x0], #2
+4:	adds	x2, x2, #1
+	b.mi	5f
+USER(9f, ldrb	w3, [x1]	)
+	strb	w3, [x0]
+5:	mov	x0, #0
+	ret
+ENDPROC(__copy_from_user)
+
+	.section .fixup,"ax"
+	.align	2
+9:	sub	x2, x4, x1
+	mov	x3, x2
+10:	strb	wzr, [x0], #1			// zero remaining buffer space
+	subs	x3, x3, #1
+	b.ne	10b
+	mov	x0, x2				// bytes not copied
+	ret
+	.previous
diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S
new file mode 100644
index 0000000..84b6c9b
--- /dev/null
+++ b/arch/arm64/lib/copy_in_user.S
@@ -0,0 +1,63 @@
+/*
+ * Copy from user space to user space
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Copy from user space to user space (alignment handled by the hardware)
+ *
+ * Parameters:
+ *	x0 - to
+ *	x1 - from
+ *	x2 - n
+ * Returns:
+ *	x0 - bytes not copied
+ */
+ENTRY(__copy_in_user)
+	add	x4, x0, x2			// upper user buffer boundary
+	subs	x2, x2, #8
+	b.mi	2f
+1:
+USER(9f, ldr	x3, [x1], #8	)
+	subs	x2, x2, #8
+USER(9f, str	x3, [x0], #8	)
+	b.pl	1b
+2:	adds	x2, x2, #4
+	b.mi	3f
+USER(9f, ldr	w3, [x1], #4	)
+	sub	x2, x2, #4
+USER(9f, str	w3, [x0], #4	)
+3:	adds	x2, x2, #2
+	b.mi	4f
+USER(9f, ldrh	w3, [x1], #2	)
+	sub	x2, x2, #2
+USER(9f, strh	w3, [x0], #2	)
+4:	adds	x2, x2, #1
+	b.mi	5f
+USER(9f, ldrb	w3, [x1]	)
+USER(9f, strb	w3, [x0]	)
+5:	mov	x0, #0
+	ret
+ENDPROC(__copy_in_user)
+
+	.section .fixup,"ax"
+	.align	2
+9:	sub	x0, x4, x0			// bytes not copied
+	ret
+	.previous
diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S
new file mode 100644
index 0000000..a0aeeb9
--- /dev/null
+++ b/arch/arm64/lib/copy_to_user.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Copy to user space from a kernel buffer (alignment handled by the hardware)
+ *
+ * Parameters:
+ *	x0 - to
+ *	x1 - from
+ *	x2 - n
+ * Returns:
+ *	x0 - bytes not copied
+ */
+ENTRY(__copy_to_user)
+	add	x4, x0, x2			// upper user buffer boundary
+	subs	x2, x2, #8
+	b.mi	2f
+1:
+	ldr	x3, [x1], #8
+	subs	x2, x2, #8
+USER(9f, str	x3, [x0], #8	)
+	b.pl	1b
+2:	adds	x2, x2, #4
+	b.mi	3f
+	ldr	w3, [x1], #4
+	sub	x2, x2, #4
+USER(9f, str	w3, [x0], #4	)
+3:	adds	x2, x2, #2
+	b.mi	4f
+	ldrh	w3, [x1], #2
+	sub	x2, x2, #2
+USER(9f, strh	w3, [x0], #2	)
+4:	adds	x2, x2, #1
+	b.mi	5f
+	ldrb	w3, [x1]
+USER(9f, strb	w3, [x0]	)
+5:	mov	x0, #0
+	ret
+ENDPROC(__copy_to_user)
+
+	.section .fixup,"ax"
+	.align	2
+9:	sub	x0, x4, x0			// bytes not copied
+	ret
+	.previous
diff --git a/arch/arm64/lib/getuser.S b/arch/arm64/lib/getuser.S
new file mode 100644
index 0000000..1b4da22
--- /dev/null
+++ b/arch/arm64/lib/getuser.S
@@ -0,0 +1,75 @@
+/*
+ * Based on arch/arm/lib/getuser.S
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Idea from x86 version, (C) Copyright 1998 Linus Torvalds
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * These functions have a non-standard call interface to make them more
+ * efficient, especially as they return an error value in addition to
+ * the "real" return value.
+ *
+ * __get_user_X
+ *
+ * Inputs:	x0 contains the address
+ * Outputs:	x0 is the error code
+ *		x2, x3 contains the zero-extended value
+ *		lr corrupted
+ *
+ * No other registers must be altered.  (see <asm/uaccess.h>
+ * for specific ASM register usage).
+ *
+ * Note also that it is intended that __get_user_bad is not global.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+
+ENTRY(__get_user_1)
+1:	ldrb	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__get_user_1)
+
+ENTRY(__get_user_2)
+2:	ldrh	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__get_user_2)
+
+ENTRY(__get_user_4)
+3:	ldr	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__get_user_4)
+
+ENTRY(__get_user_8)
+4:	ldr	x2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__get_user_4)
+
+__get_user_bad:
+	mov	x2, #0
+	mov	x0, #-EFAULT
+	ret
+ENDPROC(__get_user_bad)
+
+.section __ex_table, "a"
+	.quad	1b, __get_user_bad
+	.quad	2b, __get_user_bad
+	.quad	3b, __get_user_bad
+	.quad	4b, __get_user_bad
+.previous
diff --git a/arch/arm64/lib/putuser.S b/arch/arm64/lib/putuser.S
new file mode 100644
index 0000000..62d4a42
--- /dev/null
+++ b/arch/arm64/lib/putuser.S
@@ -0,0 +1,73 @@
+/*
+ * Based on arch/arm/lib/putuser.S
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Idea from x86 version, (C) Copyright 1998 Linus Torvalds
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * These functions have a non-standard call interface to make
+ * them more efficient, especially as they return an error
+ * value in addition to the "real" return value.
+ *
+ * __put_user_X
+ *
+ * Inputs:	x0 contains the address
+ *		x2, x3 contains the value
+ * Outputs:	x0 is the error code
+ *		lr corrupted
+ *
+ * No other registers must be altered.  (see <asm/uaccess.h>
+ * for specific ASM register usage).
+ *
+ * Note that it is intended that __put_user_bad is not global.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+
+ENTRY(__put_user_1)
+1:	strb	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__put_user_1)
+
+ENTRY(__put_user_2)
+2:	strh	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__put_user_2)
+
+ENTRY(__put_user_4)
+3:	str	w2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__put_user_4)
+
+ENTRY(__put_user_8)
+4:	str	x2, [x0]
+	mov	x0, #0
+	ret
+ENDPROC(__put_user_8)
+
+__put_user_bad:
+	mov	x0, #-EFAULT
+	ret
+ENDPROC(__put_user_bad)
+
+.section __ex_table, "a"
+	.quad	1b, __put_user_bad
+	.quad	2b, __put_user_bad
+	.quad	3b, __put_user_bad
+	.quad	4b, __put_user_bad
+.previous
diff --git a/arch/arm64/lib/strncpy_from_user.S b/arch/arm64/lib/strncpy_from_user.S
new file mode 100644
index 0000000..56e448a
--- /dev/null
+++ b/arch/arm64/lib/strncpy_from_user.S
@@ -0,0 +1,50 @@
+/*
+ * Based on arch/arm/lib/strncpy_from_user.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+	.text
+	.align	5
+
+/*
+ * Copy a string from user space to kernel space.
+ *  x0 = dst, x1 = src, x2 = byte length
+ * returns the number of characters copied (strlen of copied string),
+ *  -EFAULT on exception, or "len" if we fill the whole buffer
+ */
+ENTRY(__strncpy_from_user)
+	mov	x4, x1
+1:	subs	x2, x2, #1
+	bmi	2f
+USER(9f, ldrb	w3, [x1], #1	)
+	strb	w3, [x0], #1
+	cbnz	w3, 1b
+	sub	x1, x1, #1	// take NUL character out of count
+2:	sub	x0, x1, x4
+	ret
+ENDPROC(__strncpy_from_user)
+
+	.section .fixup,"ax"
+	.align	0
+9:	strb	wzr, [x0]	// null terminate
+	mov	x0, #-EFAULT
+	ret
+	.previous
diff --git a/arch/arm64/lib/strnlen_user.S b/arch/arm64/lib/strnlen_user.S
new file mode 100644
index 0000000..7f7b176
--- /dev/null
+++ b/arch/arm64/lib/strnlen_user.S
@@ -0,0 +1,47 @@
+/*
+ * Based on arch/arm/lib/strnlen_user.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+	.text
+	.align	5
+
+/* Prototype: unsigned long __strnlen_user(const char *str, long n)
+ * Purpose  : get length of a string in user memory
+ * Params   : str - address of string in user memory
+ * Returns  : length of string *including terminator*
+ *	      or zero on exception, or n if too long
+ */
+ENTRY(__strnlen_user)
+	mov	x2, x0
+1:	subs	x1, x1, #1
+	b.mi	2f
+USER(9f, ldrb	w3, [x0], #1	)
+	cbnz	w3, 1b
+2:	sub	x0, x0, x2
+	ret
+ENDPROC(__strnlen_user)
+
+	.section .fixup,"ax"
+	.align	0
+9:	mov	x0, #0
+	ret
+	.previous



From thierry.reding at avionic-design.de  Tue Aug 14 14:01:42 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 20:01:42 +0200
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
Message-ID: <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>

On Tue, Aug 14, 2012 at 10:38:08AM -0700, Bjorn Helgaas wrote:
> On Mon, Aug 13, 2012 at 10:55 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Mon, Aug 13, 2012 at 10:00:45PM -0700, Bjorn Helgaas wrote:
> >> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > This commit adds a new flag that allows marking resources as PCI
> >> > configuration space.
> >> >
> >> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> >> > ---
> >> > Changes in v3:
> >> > - new patch
> >> >
> >> >  include/linux/ioport.h | 2 +-
> >> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >> >
> >> > diff --git a/include/linux/ioport.h b/include/linux/ioport.h
> >> > index 589e0e7..3314843 100644
> >> > --- a/include/linux/ioport.h
> >> > +++ b/include/linux/ioport.h
> >> > @@ -102,7 +102,7 @@ struct resource {
> >> >
> >> >  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
> >> >  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
> >> > -
> >> > +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */
> >>
> >> What is the purpose of this?  It seems that you are marking regions
> >> that we call MMCONFIG on x86, or ECAM-type regions in the language of
> >> the PCIe spec.  I see that you set it in several places, but I don't
> >> see anything that ever looks for it.  Do you have plans to use it in
> >> the future?  If it really does correspond to MMCONFIG/ECAM, we should
> >> handle those regions consistently across all architectures.
> >
> > The purpose is ultimately to obtain the MMCONFIG/ECAM resources assigned
> > to a PCI host controller. I've used this in the of_pci_parse_ranges()
> > and in the static board setup code to mark ranges as such. Perhaps
> > IORESOURCE_ECAM or IORESOURCE_MMCONFIG might have been better names. I
> > also just noticed that I'm not using this anywhere, but the plan was to
> > eventually use it with platform_get_resource(). However that doesn't
> > seem to work either because the lower bits of the flags aren't use for
> > comparison in that function.
> >
> > Any other ideas how that could be handled? Basically what I need is a
> > way to mark a resource as an MMCONFIG/ECAM range so that it can be used
> > to program the PCI host controller accordingly. I don't know how these
> > are assigned on x86. I was under the impression that the MMCONFIG/ECAM
> > space was accessed through a single single address/data register pair.
> 
> The legacy config access mechanism (CF8h/CFCh registers described in
> PCI 3.0 spec sec 3.2.2.3.2) is a single address/data pair, but this is
> mostly x86-specific.  The ECAM mechanism (described in the PCIe 3.0
> spec sec 7.2.2) is not a single address/data pair; instead, each byte
> of config space is directly mapped into the host's MMIO space.
> 
> Here's what we do on x86 (omitting some historical grunge that
> complicates things):
> 
>   - Discover the host bridge via a PNP0A08 device in the ACPI namespace.
>   - Discover the bus number range behind the bridge using a _CRS
> method in the PNP0A08 device.
>   - Discover the ECAM space for those buses via a _CBA method in the
> PNP0A08 device.
>   - Tell the config accessors (struct pci_ops) that the ECAM space for
> buses A-B is at address X.
>   - Enumerate the devices behind the host bridge by calling
> pci_scan_root_bus(), passing the config accessors.
> 
> It sounds like you want a way to parse the resources at one point,
> saving them and marking the ECAM region, then at a later point, look
> up the ECAM from a saved list.  We don't do that on x86 because the
> config accessors keep an internal list of the ECAM area for each bus.
> 
> We do of course want to put this ECAM space in the IORESOURCE_MEM tree
> because it consumes address space and we have to make sure we don't
> put anything else on top of it.  But we don't have any reason to
> describe the MMIO -> config space function in that tree.  From the
> point of view of the rest of the system, it's just MMIO space that's
> consumed by the PCI host bridge, just like any other device-specific
> MMIO area.

What I currently do is pass the ECAM space as a resource to the PCI host
bridge platform device. Regular and extended configuration spaces are
given by the third and fourth resources, respectively. If I understand
correctly, you're saying that nothing beyond that needs to be encoded.
In other words it is enough for the PCI host bridge driver to know where
to take the data from.

I'll have to see what this means for the DT binding. There are other
issues that I need to think about, like for example how to pass the ECAM
space from the PCI host controller to each of the two bridges via the
ranges property. This no longer makes sense in the current form, as the
ECAM covers the configuration spaces for devices of both bridges and
cannot really be split among them.

Thierry
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From troy.kisky at boundarydevices.com  Tue Aug 14 14:09:58 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Tue, 14 Aug 2012 11:09:58 -0700
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAP1dx+wm=Lj6WXWTiRk3JfqAomr8_mfjZpmToht2bb4paEYXjQ@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <502954D2.908@boundarydevices.com>
 <CAP1dx+wm=Lj6WXWTiRk3JfqAomr8_mfjZpmToht2bb4paEYXjQ@mail.gmail.com>
Message-ID: <502A9476.1040500@boundarydevices.com>

On 8/14/2012 12:30 AM, Dong Aisheng wrote:
> On 14 August 2012 03:26, Troy Kisky <troy.kisky at boundarydevices.com> wrote:
>> On 8/13/2012 7:47 AM, Shawn Guo wrote:
>>> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
>>> pinctrl drivers number pad from 1.  It causes problem/confusion when
>>> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>>>
>>> Change imx51_pads and imx53_pads numbering start from 0.
>>>
>>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>>> ---
>>>    drivers/pinctrl/pinctrl-imx51.c |  490
>>> +++++++++++++++++++-------------------
>>>    drivers/pinctrl/pinctrl-imx53.c |  402 ++++++++++++++++----------------
>>>    2 files changed, 446 insertions(+), 446 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/pinctrl-imx51.c
>>> b/drivers/pinctrl/pinctrl-imx51.c
>>> index 9fd0216..fb84689 100644
>>> --- a/drivers/pinctrl/pinctrl-imx51.c
>>> +++ b/drivers/pinctrl/pinctrl-imx51.c
>>> @@ -23,251 +23,251 @@
>>>    #include "pinctrl-imx.h"
>>>      enum imx51_pads {
>>> -       MX51_PAD_EIM_D16 = 1,
>>> -       MX51_PAD_EIM_D17 = 2,
> ...
>>> +       MX53_PAD_GPIO_19 = 0,
>>> +       MX53_PAD_KEY_COL0 = 1,
>>
>> Why not skip the = xx altogether??  The enum will auto-increment.
> Personally i'd like to keep it.
> The reason is that pin id is basic property of a pin per pinctrl
> subsystem's design
> so explicitly define it looks more clear to me and i'm not sure but
> it's possible that
> the pin id may be used in device tree in the future(maybe some other
> soc already uses it),
> And defining it has no big harming.
>
> Regards
> Dong Aisheng
> .
>
Then maybe #defines should be used, so that device tree can include this 
file and be run through C pre-processor?

Thanks
Troy



From jason at lakedaemon.net  Tue Aug 14 14:23:24 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 14:23:24 -0400
Subject: [patch v2 1/1] ARM: Orion: Set eth packet size csum offload limit
In-Reply-To: <20120726101601.284809510@rtp-net.org>
References: <20120726101601.284809510@rtp-net.org>
Message-ID: <20120814182324.GO22226@titan.lakedaemon.net>

On Thu, Jul 26, 2012 at 12:15:46PM +0200, Arnaud Patard wrote:
> The mv643xx ethernet controller limits the packet size for the TX
> checksum offloading. This patch sets this limits for Kirkwood and
> Dove which have smaller limits that the default.
> 
> As a side note, this patch is an updated version of a patch sent some years
> ago: http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017320.html
> which seems to have been lost.
> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>

Applied to:

git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

thx,

Jason.


From swarren at wwwdotorg.org  Tue Aug 14 14:32:45 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 Aug 2012 12:32:45 -0600
Subject: [PATCH 0/5] ARM: tegra: add CPU hotplug support
In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
Message-ID: <502A99CD.3060400@wwwdotorg.org>

On 08/14/2012 02:07 AM, Joseph Lo wrote:
> This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
> 
> The first 3 patches make the CPU clock and reset control be a module and
> the abstraction APIs for TegraXX SoCs. And clean up some codes for later
> usage. Then add CPU hotplug support for Tegra20 and Tegra30.
> 
> Verified on Seaboard(Tegra20) and Cardhu(Tegra30)

There are two problems with this series:

1) It doesn't compile if CONFIG_HOTPLUG_CPU isn't enabled. Please also
make sure that Tegra20-only and Tegra30-only kernels compile (I didn't
check this, so it may well already be the case).

2) It prevents the "reboot" from working; the kernel hangs as it
attempts to do the reboot. I've confirmed this isn't the case without
this patch series, even if CONFIG_HOTPLUG_CPU is enabled.

I assume we'll want to enable CONFIG_HOTPLUG_CPU in tegra_defconfig once
this is checked in?


From rvaswani at codeaurora.org  Tue Aug 14 14:49:01 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Tue, 14 Aug 2012 11:49:01 -0700
Subject: [PATCH 1/2] ARM: local timers: Unmask interrupt before new TVAL
 is set
In-Reply-To: <cdb51f00bafa8151a880d8cc7898631e@localhost>
References: <1344635854-5033-1-git-send-email-rvaswani@codeaurora.org>
 <cdb51f00bafa8151a880d8cc7898631e@localhost>
Message-ID: <502A9D9D.7070901@codeaurora.org>

On 8/11/2012 3:17 AM, Marc Zyngier wrote:
> On Fri, 10 Aug 2012 14:57:34 -0700, Rohit Vaswani
> <rvaswani at codeaurora.org>
> wrote:
>> Level triggered interrupt is deasserted when a new TVAL is written
>> only when the interrupt is unmasked. Make sure that the interrupt
>> is unmasked in CTL register before TVAL is written.
>> If this order is not followed, there are chances that on some
>> hardware you would not receive any timer interrupts.
>>
>> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
>> ---
>>   arch/arm/kernel/arch_timer.c |    2 +-
>>   1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
>> index dd58035..1d0d9df 100644
>> --- a/arch/arm/kernel/arch_timer.c
>> +++ b/arch/arm/kernel/arch_timer.c
>> @@ -126,8 +126,8 @@ static int arch_timer_set_next_event(unsigned long
> evt,
>>   	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>>   	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
>>   
>> -	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
>>   	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
>> +	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
> But by doing so, you're opening a window where TVAL can be negative (from
> a previous timer trigger) and the interrupt unmasked, which would lead to
> an immediate trigger, before TVAL is updated with the new value.
>
> Does your hardware deassert the interrupt even when the enable bit is not
> set? If so, would the following sequence work?
>
>          ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK);
>          arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
>
> 	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
>
>          ctrl |= ARCH_TIMER_CTRL_ENABLE;
>          arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
>
> Thanks,
>
>          M.
Thanks Marc, this works. I will re-send the patch with these changes.

Thanks,
Rohit Vaswani

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From jason at lakedaemon.net  Tue Aug 14 15:20:49 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:20:49 -0400
Subject: [PATCH] arm: add documentation describing Marvell families of SoC
In-Reply-To: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344115004-7886-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120814192049.GR22226@titan.lakedaemon.net>

On Sat, Aug 04, 2012 at 11:16:44PM +0200, Thomas Petazzoni wrote:
> As stated in the introduction of the document, the families of ARM
> SoCs at Marvell are very complicated, and it is difficult for
> newcomers to understand the organization of this SoC family and how it
> relates to the Linux kernel support for those hardware platforms.
> 
> This document is only at RFC stage for now, it requires reviews and
> comments from the Marvell maintainers, the PXA maintainers and the MMP
> maintainers. For correctness of course, but also to add any other
> information that would be useful. For example, one of the thing that
> wasn't clear how to detail in the documentation is how the SoCs relate
> to each other in terms of hardware IP blocks. For example, most of the
> Kirkwood/Dove/Armada 370-XP/etc. hardware IPs (I2C, SPI, USB, SATA,
> etc.) are identical, while the PXA and MMP families are completely
> separate.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Lior Amsalem <alior at marvell.com>
> Cc: Maen Suleiman <maen at marvell.com>
> Cc: Tawfik Bayouk <tawfik at marvell.com>
> Cc: Shadi Ammouri <shadi at marvell.com>
> Cc: Eran Ben-Avi <benavi at marvell.com>

Added Arnd's Acked-by: and applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 14 15:36:13 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:36:13 -0400
Subject: [PATCH 2/2] ARM: kirkwood: DT descriptor for Seagate FreeAgent
 Dockstar
In-Reply-To: <1344177973-6505-2-git-send-email-sebastian.hesselbarth@googlemail.com>
References: <1344177973-6505-1-git-send-email-sebastian.hesselbarth@googlemail.com>
 <1344177973-6505-2-git-send-email-sebastian.hesselbarth@googlemail.com>
Message-ID: <20120814193613.GS22226@titan.lakedaemon.net>

On Sun, Aug 05, 2012 at 04:46:13PM +0200, Sebastian Hesselbarth wrote:
> This adds the corresponding device tree descriptor for the
> Seagate FreeAgent Dockstar based on Kirkwood DT.
> 
> Please note that this patch requires the mach-kirkwood Makefile.boot typo
> fix to fully apply.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at googlemail.com>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
...
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index a571755..2c2edfb 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb

This series looks great, but will go in after the above line is fixed.
Can you correct and resubmit so we don't get a conflict down the road?

You can just do a v2 of this patch in-reply-to this one.

thx,

Jason.


From matt at genesi-usa.com  Tue Aug 14 15:37:52 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Tue, 14 Aug 2012 14:37:52 -0500
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
Message-ID: <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>

On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
>> I have a minor nit; while renumbering the pinctrl definitions is
>> laudable and device trees can match, there are 16 other pin controls
>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
>> (pin_id*4)).
>
> What do you mean of this value calculated?

Well, it just seems the datasheet has been read from the point of view
of the SW_CTRL settings (pad pullups, drive strength etc.) to define
the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
I mistyped) has been entered as an enum into this list. Then a table
has been generated using these enums to supply a pin id. Then this pin
id is not relevant anymore; it actually gets referenced by it's
*offset into the table*.

In this case, basically the code misses a few pins which have ALT
settings but perhaps not always the ability to change pad control -
EIM_DA5 to 15 are a good example.

Probably better would be to define the binding almost exactly as it
was done in the old method; iomux_v3_cfg_t took into account the three
register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
and the three values to be put into those registers.

This has been reduced down in pinctrl to what I find quite strange,
which is a completely arbitrary pin "id" mapping, which indirectly
references an entry in a table by index which is why pin 1 as a start
looks odd.

If the binding is entirely i.MX-specific or even i.MX51-specific then
why not define the pins in the device tree the "old" iomux_v3_cfg_t
way, which is the way they are in the table of imx_pin_regs;

      IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
MX51_PAD_EIM_D16__AUD4_RXFS */

0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
0x000 is the IPP reg, and 0 the IPP value.

So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
mode/sion, IPP, select - in that order) would be a valid pin
definition and require no table. Sure, the offsets are device specific
but then the arbitrary numbering is too. This way old iomux controls
can be re-derived for people who use the old method in old kernels, or
use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
porting the Efika to it on MX5 for U-Boot right now). Also that huge
table goes away - it can be built at runtime, along with the
PAD_NAME__ALT_MODE_NAME description.

It would also remove any arbitrary indexes, and allow lookup based on
an actual documented value (which is listed at the top of every page
of Appendix A register definitions), cross-referencing with the manual
on the actual register settings etc.  It is certainly less confusing
than <0 0x17058> or so, which says nothing without a comment, and the
value listed is entirely arbitrary encoding of the PAD_CTL values.

For a different way of explaining and another example of what is
wrong, in the current binding doc for example;

        1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */

1386 is a pin index, correct? But it's a pin index into the
imx_pin_regs array. It has no relation to the enums at the top of
pinctrl-imx6q.c, which is only used to refer to the pin_desc
structure.

        IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0),
/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */

So the enums at the top of the file don't even define the pin number.
You have to COUNT inside this file, or look at the binding which
someone has written by doing the counting by hand or script. Change
the array, change the binding. This is terrible, terrible design.
There should be one point of reference, and if possible, the binding
should be totally obvious without cross-reference.

The docs then say 0x17059 defines the pin control settings (hysteresis
etc.) - MUX_MODE (ALT) is inferred from this database inside the
kernel.

If you need to add more items in the list (for instance if MX7 gains
an extra set of configuration registers for each pin), this is what
#size-cells property is for in the device tree, or better yet why not
walk the tree to find the machine compatible?

> What trouble do you mean?
> Those pins, EIM_DA*, are already defined but just on a different pin id.
> Can't user use it in this way?

Yuck.

>> Therefore I propose;
>>
>> * add MX51_PAD_EIM_DA0 through DA15 as index 0-15 (same for any
>> differences in other i.MX etc.)
> Hmm, as i said above, those pins are already defined.
> See:
>         MX51_PAD_SD1_DATA0 = 209,
>         MX51_PAD_EIM_DA0 = 210,
>         MX51_PAD_EIM_DA1 = 211,
>         MX51_PAD_EIM_DA2 = 212,
>         MX51_PAD_EIM_DA3 = 213,

Where are 4 through 15?

> I did not quite understand, remove other pin ids up by 16? why?

See above.

> Why we may want to change the definitions again?

If you got ANYTHING at all wrong. Shawn already sent a patch to change
a definition. What if the order in the table changes? Where is the
note above the table that says the order of the table is tied directly
to the binding and no order changes or inserts-in-the-middle should be
made?

> Since we already have those pins EIM_DA* defined, it looks to me user could use

No.. because there are 12 pins missing. I don't know how many others
might be missing, but the implementation as a whole is too arbitrary
and too abstract. You do not need to implement indirection in the
device tree.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From swarren at wwwdotorg.org  Tue Aug 14 15:39:23 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 Aug 2012 13:39:23 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
Message-ID: <502AA96B.2050709@wwwdotorg.org>

On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
> On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
...
>> whereas for a device tree boot:
>>
>> (same):
>>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>> ... (request region happens early)
>>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>> ... (same, just happens too late)
>>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>>
>> I suspect this is all still related to the PCI devices themselves being
>> probed much earlier in the overall PCI initialization sequence when the
>> PCI controller is probed later in the boot sequence, whereas PCI device
>> probe is deferred until the overall PCI initialization sequence is
>> complete if the PCI controller is probed very early in the boot sequence.
> 
> I don't know what to apply your patches to (they don't apply cleanly
> to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
> like you might be calling pci_bus_add_devices() before
> pci_bus_assign_resource(), which isn't going to work.

Yes, that's exactly what is happening.

PCIe initialization starts in arch/arm/mach-tegra/pci.e
tegra_pcie_init() which calls arch/arm/kernel/bios32.c
pci_common_init(). That function first calls pcibios_init_hw() (in the
same file, more about this later) and then loops over PCI buses, calling
amongst other things pci_bus_assign_resources() then pci_bus_add_devices().

The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
(or a host-driver-specific function which that also calls
pci_scan_root_bus() in Tegra's case) which in turn calls
pci_bus_add_devices() right at the end, before control has returned to
pci_common_init() and hence before pci_bus_assign_resources() has been
called.

If I modify pci_scan_root_bus() and remove the call to
pci_bus_add_devices(), everything works as expected.

So, I guess the question is: Should ARM's pcibios_init_hw() not be
calling pci_scan_root_bus(), or at least presumably the ARM PCI code
needs to do things in a slightly different order?


From jason at lakedaemon.net  Tue Aug 14 15:40:30 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:40:30 -0400
Subject: [patch] ARM: Kirkwood: Fix iconnect leds
In-Reply-To: <20120805203610.540496769@rtp-net.org>
References: <20120805203610.540496769@rtp-net.org>
Message-ID: <20120814194030.GT22226@titan.lakedaemon.net>

On Sun, Aug 05, 2012 at 10:35:56PM +0200, Arnaud Patard wrote:
> While converting, a led has been missed leading to wrong power blue led
> definition. Add it back and fix the gpio used on the power blue led.
> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>

added Acked-By: from Andrew Lunn and applied to:

git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 14 15:43:11 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:43:11 -0400
Subject: [patch] ARM: Kirkwood: fix Makefile.boot
In-Reply-To: <20120805203610.644315269@rtp-net.org>
References: <20120805203555.457907381@rtp-net.org>
 <20120805203610.644315269@rtp-net.org>
Message-ID: <20120814194311.GU22226@titan.lakedaemon.net>

On Sun, Aug 05, 2012 at 10:35:57PM +0200, Arnaud Patard wrote:
> While building the dtbs target, one is getting:
> 
> make dtbs
> make[1]: *** No rule to make target `arch/arm/boot/kirkwood-qnap-ts219.dtb', needed by `arch/arm/boot/dtbs'.  Stop.
> make: *** [dtbs] Error 2
> 
> The reason is that there's no kirkwood-qnap-ts219.dts file. Update Makefile.boot
> to reflect the dts files present.
> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>

added Acked-By from Andrew Lunn and applied to:

git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 14 15:46:30 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:46:30 -0400
Subject: [patch 1/2] ARM: Kirkwood: Describe iconnect keys in DT.
In-Reply-To: <20120805203920.804712126@rtp-net.org>
References: <20120805203920.804712126@rtp-net.org>
Message-ID: <20120814194630.GV22226@titan.lakedaemon.net>

On Sun, Aug 05, 2012 at 10:39:12PM +0200, Arnaud Patard wrote:
> Define the 2 keys found on iconnect in DT. It's also changing the keycodes/
> switches to use better ones.
> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>

applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 14 15:48:53 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 15:48:53 -0400
Subject: [patch 2/2] ARM: Kirkwood: Describe iconnect nand in DT.
In-Reply-To: <20120805203920.908663535@rtp-net.org>
References: <20120805203911.915580862@rtp-net.org>
 <20120805203920.908663535@rtp-net.org>
Message-ID: <20120814194853.GW22226@titan.lakedaemon.net>

On Sun, Aug 05, 2012 at 10:39:13PM +0200, Arnaud Patard wrote:
> Define the nand and its partitions in DT and remove them from cmdline
> 
> Signed-off-by: Arnaud Patard <arnaud.patard at rtp-net.org>

applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

thx,

Jason.


From linux at roeck-us.net  Tue Aug 14 15:51:15 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Tue, 14 Aug 2012 12:51:15 -0700
Subject: [PATCH] Documentation: dt: hwmon: Update for tmp102
In-Reply-To: <1344961412-13622-1-git-send-email-sourav.poddar@ti.com>
References: <1344961412-13622-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120814195115.GA17168@roeck-us.net>

On Tue, Aug 14, 2012 at 09:53:32PM +0530, Sourav Poddar wrote:
> Add Documentation for tmp102 temperature sensor.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  Documentation/devicetree/bindings/hwmon/tmp102.txt |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/hwmon/tmp102.txt
> 
> diff --git a/Documentation/devicetree/bindings/hwmon/tmp102.txt b/Documentation/devicetree/bindings/hwmon/tmp102.txt
> new file mode 100644
> index 0000000..df1342b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/tmp102.txt
> @@ -0,0 +1,11 @@
> +TMP102 Temperature sensor
> +
> +Required properties:
> +- compatible: ti,tmp102
> +
> +Example:
> +
> +tmp102 at 48 {
> +        compatible = "ti,tmp102";
> +        reg = <0x48>;
> +};
> -- 

It would be simpler to just add a single line to
	Documentation/devicetree/bindings/i2c/trivial-devices.txt

Guenter


From thierry.reding at avionic-design.de  Tue Aug 14 15:58:34 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 21:58:34 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502AA96B.2050709@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
Message-ID: <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>

On Tue, Aug 14, 2012 at 01:39:23PM -0600, Stephen Warren wrote:
> On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
> > On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> ...
> >> whereas for a device tree boot:
> >>
> >> (same):
> >>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
> >>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
> >>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
> >> ... (request region happens early)
> >>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
> >>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
> >>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
> >> ... (same, just happens too late)
> >>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
> >>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
> >>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
> >>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
> >>
> >> I suspect this is all still related to the PCI devices themselves being
> >> probed much earlier in the overall PCI initialization sequence when the
> >> PCI controller is probed later in the boot sequence, whereas PCI device
> >> probe is deferred until the overall PCI initialization sequence is
> >> complete if the PCI controller is probed very early in the boot sequence.
> > 
> > I don't know what to apply your patches to (they don't apply cleanly
> > to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
> > like you might be calling pci_bus_add_devices() before
> > pci_bus_assign_resource(), which isn't going to work.
> 
> Yes, that's exactly what is happening.
> 
> PCIe initialization starts in arch/arm/mach-tegra/pci.e
> tegra_pcie_init() which calls arch/arm/kernel/bios32.c
> pci_common_init(). That function first calls pcibios_init_hw() (in the
> same file, more about this later) and then loops over PCI buses, calling
> amongst other things pci_bus_assign_resources() then pci_bus_add_devices().
> 
> The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
> (or a host-driver-specific function which that also calls
> pci_scan_root_bus() in Tegra's case) which in turn calls
> pci_bus_add_devices() right at the end, before control has returned to
> pci_common_init() and hence before pci_bus_assign_resources() has been
> called.
> 
> If I modify pci_scan_root_bus() and remove the call to
> pci_bus_add_devices(), everything works as expected.
> 
> So, I guess the question is: Should ARM's pcibios_init_hw() not be
> calling pci_scan_root_bus(), or at least presumably the ARM PCI code
> needs to do things in a slightly different order?

Maybe pci_scan_root_bus() should be calling pci_bus_assign_resources()?
Or a new function could be added which also assigns the resources.

Thierry
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From alanbutty12 at gmail.com  Tue Aug 14 16:06:16 2012
From: alanbutty12 at gmail.com (Ownerx35)
Date: Tue, 14 Aug 2012 21:06:16 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
Message-ID: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>

I have created a patch and have tested it myself that create a board setup file for the Iomega StoreCenter IX2-200, create a dts file and insert the appropriate lines into the common.h, makefile, makefile.boot, kconfig and board-ft files.

But am unsure how to properly submit it should i just post it here? or is there a specific place i should post?

From thierry.reding at avionic-design.de  Tue Aug 14 16:12:15 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 14 Aug 2012 22:12:15 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>

On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index a094c97..c886dff 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -199,6 +199,68 @@
>  		#size-cells = <0>;
>  	};
>  
> +	pcie-controller {
> +		compatible = "nvidia,tegra20-pcie";
> +		reg = <0x80003000 0x00000800   /* PADS registers */
> +		       0x80003800 0x00000200   /* AFI registers */
> +		       0x81000000 0x01000000   /* configuration space */
> +		       0x90000000 0x10000000>; /* extended configuration space */
> +		interrupts = <0 98 0x04   /* controller interrupt */
> +		              0 99 0x04>; /* MSI interrupt */
> +		status = "disabled";
> +
> +		ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
> +			  0 1 0  0x81000000 0x00800000   /* port 0 config space */
> +			  0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
> +			  0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
> +			  0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
> +			  0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
> +
> +			  1 0 0  0x80001000 0x00001000   /* root port 1 */
> +			  1 1 0  0x81800000 0x00800000   /* port 1 config space */
> +			  1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
> +			  1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
> +			  1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
> +			  1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */

I've been thinking about this some more. The translations for both the
regular and extended configuration spaces are configured in the top-
level PCIe controller. It is therefore wrong how they are passed to the
PCI host bridges via the ranges property.

I remember Mitch saying that it should be passed down to the children
because it is partitioned among them, but since the layout is compatible
with ECAM, the partitioning isn't as simple as what's in the tree. In
fact the partitions will be dependent on the number of devices attached
to the host bridges.

> +
> +		#address-cells = <3>;
> +		#size-cells = <1>;
> +
> +		pci at 0 {
> +			device_type = "pciex";
> +			reg = <0 0 0 0x1000>;
> +			status = "disabled";
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			ranges = <0x80000000 0 0  0 1 0  0 0x00800000   /* config space */
> +				  0x90000000 0 0  0 2 0  0 0x08000000   /* ext config space */
> +				  0x81000000 0 0  0 3 0  0 0x00010000   /* I/O */
> +				  0x82000000 0 0  0 4 0  0 0x08000000   /* non-prefetchable memory */
> +				  0xc2000000 0 0  0 5 0  0 0x08000000>; /* prefetchable memory */
> +
> +			nvidia,num-lanes = <2>;
> +		};
> +
> +		pci at 1 {
> +			device_type = "pciex";
> +			reg = <1 0 0 0x1000>;
> +			status = "disabled";
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			ranges = <0x80000000 0 0  1 1 0  0 0x00800000   /* config space */
> +				  0x90000000 0 0  1 2 0  0 0x08000000   /* ext config space */
> +				  0x81000000 0 0  1 3 0  0 0x00010000   /* I/O */
> +				  0x82000000 0 0  1 4 0  0 0x08000000   /* non-prefetchable memory */
> +				  0xc2000000 0 0  1 5 0  0 0x08000000>; /* prefetchable memory */
> +
> +			nvidia,num-lanes = <2>;
> +		};
> +	};

The same is true for the ranges properties of the PCI host bridge nodes.
Which part of the configuration spaces maps to the children of the
respective host bridge depends on the actual device hierarchy.

Would it be possible to alternatively pass the complete range to the
children without further partitioning?

The driver doesn't actually care about the ranges property and only uses
the values specified in the reg property of the pcie-controller node.

Thierry
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From s.hauer at pengutronix.de  Tue Aug 14 16:32:24 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 14 Aug 2012 22:32:24 +0200
Subject: [PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible
In-Reply-To: <CAKGA1bmk2TqDwxR=RT+z3y8XaSpcW+kHsaQfmdrHVqTD9Uxv5A@mail.gmail.com>
References: <1344599604-9623-1-git-send-email-dave.martin@linaro.org>
 <20120813193517.GU1451@pengutronix.de>
 <CAKGA1bnRA61JT8tQoHBay+6BSxDO5egiagQm1v05L7Asf+qJ+Q@mail.gmail.com>
 <20120814114059.GX1451@pengutronix.de>
 <CAKGA1bmk2TqDwxR=RT+z3y8XaSpcW+kHsaQfmdrHVqTD9Uxv5A@mail.gmail.com>
Message-ID: <20120814203224.GF1451@pengutronix.de>

On Tue, Aug 14, 2012 at 12:49:43PM -0500, Matt Sealey wrote:
> On Tue, Aug 14, 2012 at 6:40 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Mon, Aug 13, 2012 at 05:28:17PM -0500, Matt Sealey wrote:
> >>  IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /*
> >> MX51_PAD_EIM_DA15__EIM_DA15 */
> >>
> >>
> >>
> >> On Mon, Aug 13, 2012 at 2:35 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >> > Hi Dave,
> >> >
> >> > On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:
> >> >> Because FIQ handlers get copied straight into the vectors page to
> >> >> the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
> >> >> start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
> >> >> Thumb-2.
> >> >
> >> > I finally came along testing this. I have no Thumb2 capable hardware
> >> > to test if it works in thumb2 mode, but at least in Arm mode it works.
> >> > This is enough to not introduce a regression, so we can go for this.
> >>
> >> This is the interesting dichotomy; the code is only required truly on
> >> devices where Thumb2 isn't available, right?
> >
> > It is also used on the i.MX51 Eukrea board. I asked Eric (Cced) to test
> > it in thumb2 mode, no response so far. I don't know the reason why he
> > uses FIQ mode instead of SDMA, maybe simply historical reasons.
> 
> If we can lose that requirement then the only thing in the way is the
> phyCORE support, which goes away on a "pure" v7 config anyway,
> correct? I was just thinking, why not split v6_v7_defconfig into a
> v7_defconfig losing those boards anyway and enable Thumb2 by default
> while we're at it? It would mean more testing gets done and this error
> would crop up both more often, but be less surprising and won't take a
> year to revisit ;)

It took a long time until all people have realized that their code may
not only run on the SoC they are currently working on, but also on other
SoCs. Having many SoCs in a single defconfig makes this fact more
obvious and often breaks compilation if their code is not multi SoC
safe. I don't really want to lose this.

Hopefully we will soon only have a handfull of ARM defconfigs anyway.
Until this is the case I vote for not splitting up defconfigs. Then we
can have things like thumb2_defconfig, armv6_defconfig,...

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sebastian.hesselbarth at gmail.com  Tue Aug 14 16:43:41 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 14 Aug 2012 22:43:41 +0200
Subject: [PATCH v2 1/2] ARM: kirkwood: DT board setup for Seagate FreeAgent
 Dockstar
In-Reply-To: <20120814193613.GS22226@titan.lakedaemon.net>
References: <20120814193613.GS22226@titan.lakedaemon.net>
Message-ID: <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>

This add a DT compatible board specific setup for the Seagate
FreeAgent Dockstar.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org

v2: rebased on git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

 arch/arm/mach-kirkwood/Kconfig          |    7 ++++
 arch/arm/mach-kirkwood/Makefile         |    1 +
 arch/arm/mach-kirkwood/board-dockstar.c |   61 +++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c       |    4 ++
 arch/arm/mach-kirkwood/common.h         |    6 +++
 5 files changed, 79 insertions(+)
 create mode 100644 arch/arm/mach-kirkwood/board-dockstar.c

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..4eaeb93 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
 	  or MV6282. If you have the wrong one, the buttons will not
 	  work.
 
+config MACH_DOCKSTAR_DT
+	bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Seagate FreeAgent Dockstar (Flattened Device Tree).
+
 config MACH_GOFLEXNET_DT
 	bool "Seagate GoFlex Net (Flattened Device Tree)"
 	select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..42e48cf 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)	+= board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)		+= board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 0000000..6b9560b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs at gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+	MPP29_GPIO,	/* USB Power Enable */
+	MPP46_GPIO,	/* LED green */
+	MPP47_GPIO,	/* LED orange */
+	0
+};
+
+void __init dockstar_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(dockstar_mpp_config);
+
+	if (gpio_request(29, "USB Power Enable") != 0 ||
+	    gpio_direction_output(29, 1) != 0)
+		pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+	kirkwood_ehci_init();
+
+	kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..4693fad 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -81,6 +81,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("qnap,ts219"))
 		qnap_dt_ts219_init();
 
+	if (of_machine_is_compatible("seagate,dockstar"))
+		dockstar_init();
+
 	if (of_machine_is_compatible("seagate,goflexnet"))
 		goflexnet_init();
 
@@ -98,6 +101,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"iom,iconnect",
 	"raidsonic,ib-nas62x0",
 	"qnap,ts219",
+	"seagate,dockstar",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
 	NULL
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..dc73ff3 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_init(void);
+#else
+static inline void dockstar_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Tue Aug 14 16:43:42 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 14 Aug 2012 22:43:42 +0200
Subject: [PATCH v2 2/2] ARM: kirkwood: DT descriptor for Seagate FreeAgent
 Dockstar
In-Reply-To: <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20120814193613.GS22226@titan.lakedaemon.net>
 <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1344977022-29037-2-git-send-email-sebastian.hesselbarth@gmail.com>

This adds the corresponding device tree descriptor for the
Seagate FreeAgent Dockstar based on Kirkwood DT.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org

v2: rebased on git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

 arch/arm/boot/dts/kirkwood-dockstar.dts |   57 +++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Makefile.boot    |    1 +
 2 files changed, 58 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-dockstar.dts

diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 0000000..08a5824
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Seagate FreeAgent Dockstar";
+	compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x400000>;
+			};
+
+			partition at 500000 {
+				label = "data";
+				reg = <0x0500000 0xfb00000>;
+			};
+		};
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		health {
+			label = "status:green:health";
+			gpios = <&gpio1 14 1>;
+			linux,default-trigger = "default-on";
+		};
+		fault {
+			label = "status:orange:fault";
+			gpios = <&gpio1 15 1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index e2ad358..ce1a285 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -12,3 +12,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-ts219-6282.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_DOCKSTAR_DT) += kirkwood-dockstar.dtb
-- 
1.7.10.4



From sam at ravnborg.org  Tue Aug 14 17:01:02 2012
From: sam at ravnborg.org (Sam Ravnborg)
Date: Tue, 14 Aug 2012 23:01:02 +0200
Subject: [PATCH v2 30/31] arm64: Build infrastructure
In-Reply-To: <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120814210102.GA4386@merkur.ravnborg.org>

> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> new file mode 100644
> index 0000000..1ce3d04
> --- /dev/null
> +++ b/arch/arm64/Kconfig
> @@ -0,0 +1,261 @@
> +config ARM64
> +	def_bool y
> +	select OF
> +	select OF_EARLY_FLATTREE
> +	select IRQ_DOMAIN
> +	select HAVE_AOUT
> +	select HAVE_DMA_ATTRS
> +	select HAVE_DMA_API_DEBUG
> +	select HAVE_IDE
> +	select HAVE_MEMBLOCK
> +	select RTC_LIB
> +	select SYS_SUPPORTS_APM_EMULATION
> +	select HAVE_GENERIC_DMA_COHERENT
> +	select GENERIC_IOMAP
> +	select HAVE_IRQ_WORK
> +	select HAVE_PERF_EVENTS
> +	select HAVE_ARCH_TRACEHOOK
> +	select PERF_USE_VMALLOC
> +	select HAVE_HW_BREAKPOINT if PERF_EVENTS
> +	select HAVE_GENERIC_HARDIRQS
> +	select GENERIC_HARDIRQS_NO_DEPRECATED
> +	select HAVE_SPARSE_IRQ
> +	select SPARSE_IRQ
> +	select GENERIC_IRQ_SHOW
> +	select GENERIC_SMP_IDLE_THREAD
> +	select NO_BOOTMEM

If you keep this list sorted then merge conflicts are less likely.


> +	help
> +	  ARM 64-bit (AArch64) Linux support.
> +
> +config 64BIT
> +	def_bool y
> +
> +config ARCH_PHYS_ADDR_T_64BIT
> +	def_bool y
> +
> +config HAVE_PWM
> +	bool
> +
> +config SYS_SUPPORTS_APM_EMULATION
> +	bool
> +
> +config NO_IOPORT
> +	def_bool y
> +
> +config GENERIC_GPIO
> +	bool
> +
> +config GENERIC_TIME_VSYSCALL
> +	def_bool y
Please use select like all other archs do.


> +
> +config GENERIC_CLOCKEVENTS
> +	def_bool y
Again - please use select.

> +
> +config STACKTRACE_SUPPORT
> +	def_bool y
> +
> +config LOCKDEP_SUPPORT
> +	def_bool y
> +
> +config TRACE_IRQFLAGS_SUPPORT
> +	def_bool y
> +
> +config HARDIRQS_SW_RESEND
> +	def_bool y
Please use select.

> +
> +config GENERIC_IRQ_PROBE
> +	def_bool y
Please use select.

> +
> +config GENERIC_LOCKBREAK
> +	def_bool y
> +	depends on SMP && PREEMPT
> +
> +config RWSEM_GENERIC_SPINLOCK
> +	def_bool y
> +
> +config RWSEM_XCHGADD_ALGORITHM
> +	bool
> +
> +config ARCH_HAS_ILOG2_U32
> +	bool
> +
> +config ARCH_HAS_ILOG2_U64
> +	bool
> +
> +config ARCH_HAS_CPUFREQ
> +	bool
> +	help
> +	  Internal node to signify that the ARCH has CPUFREQ support
> +	  and that the relevant menu configurations are displayed for
> +	  it.
> +
> +config GENERIC_HWEIGHT
> +	def_bool y
> +
> +config GENERIC_CSUM
> +        def_bool y
> +
> +config GENERIC_CALIBRATE_DELAY
> +	def_bool y
> +
> +config ZONE_DMA32
> +	def_bool y
> +
> +config ARCH_DMA_ADDR_T_64BIT
> +	def_bool y
> +
> +config NEED_DMA_MAP_STATE
> +	def_bool y
> +
> +config NEED_SG_DMA_LENGTH
> +	def_bool y
> +
> +config SWIOTLB
> +	def_bool y
> +
> +config IOMMU_HELPER
> +	def_bool SWIOTLB
> +


	Sam


From bhelgaas at google.com  Tue Aug 14 17:44:24 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 14 Aug 2012 14:44:24 -0700
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
 <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo4Efy-Dt67rktzNiYfZfOTSu=pmYtyGd3tR-zZQ3jDGtA@mail.gmail.com>

On Tue, Aug 14, 2012 at 11:01 AM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Tue, Aug 14, 2012 at 10:38:08AM -0700, Bjorn Helgaas wrote:
>> On Mon, Aug 13, 2012 at 10:55 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>> > On Mon, Aug 13, 2012 at 10:00:45PM -0700, Bjorn Helgaas wrote:
>> >> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
>> >> <thierry.reding at avionic-design.de> wrote:
>> >> > This commit adds a new flag that allows marking resources as PCI
>> >> > configuration space.
>> >> >
>> >> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>> >> > ---
>> >> > Changes in v3:
>> >> > - new patch
>> >> >
>> >> >  include/linux/ioport.h | 2 +-
>> >> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >> >
>> >> > diff --git a/include/linux/ioport.h b/include/linux/ioport.h
>> >> > index 589e0e7..3314843 100644
>> >> > --- a/include/linux/ioport.h
>> >> > +++ b/include/linux/ioport.h
>> >> > @@ -102,7 +102,7 @@ struct resource {
>> >> >
>> >> >  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
>> >> >  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
>> >> > -
>> >> > +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */
>> >>
>> >> What is the purpose of this?  It seems that you are marking regions
>> >> that we call MMCONFIG on x86, or ECAM-type regions in the language of
>> >> the PCIe spec.  I see that you set it in several places, but I don't
>> >> see anything that ever looks for it.  Do you have plans to use it in
>> >> the future?  If it really does correspond to MMCONFIG/ECAM, we should
>> >> handle those regions consistently across all architectures.
>> >
>> > The purpose is ultimately to obtain the MMCONFIG/ECAM resources assigned
>> > to a PCI host controller. I've used this in the of_pci_parse_ranges()
>> > and in the static board setup code to mark ranges as such. Perhaps
>> > IORESOURCE_ECAM or IORESOURCE_MMCONFIG might have been better names. I
>> > also just noticed that I'm not using this anywhere, but the plan was to
>> > eventually use it with platform_get_resource(). However that doesn't
>> > seem to work either because the lower bits of the flags aren't use for
>> > comparison in that function.
>> >
>> > Any other ideas how that could be handled? Basically what I need is a
>> > way to mark a resource as an MMCONFIG/ECAM range so that it can be used
>> > to program the PCI host controller accordingly. I don't know how these
>> > are assigned on x86. I was under the impression that the MMCONFIG/ECAM
>> > space was accessed through a single single address/data register pair.
>>
>> The legacy config access mechanism (CF8h/CFCh registers described in
>> PCI 3.0 spec sec 3.2.2.3.2) is a single address/data pair, but this is
>> mostly x86-specific.  The ECAM mechanism (described in the PCIe 3.0
>> spec sec 7.2.2) is not a single address/data pair; instead, each byte
>> of config space is directly mapped into the host's MMIO space.
>>
>> Here's what we do on x86 (omitting some historical grunge that
>> complicates things):
>>
>>   - Discover the host bridge via a PNP0A08 device in the ACPI namespace.
>>   - Discover the bus number range behind the bridge using a _CRS
>> method in the PNP0A08 device.
>>   - Discover the ECAM space for those buses via a _CBA method in the
>> PNP0A08 device.
>>   - Tell the config accessors (struct pci_ops) that the ECAM space for
>> buses A-B is at address X.
>>   - Enumerate the devices behind the host bridge by calling
>> pci_scan_root_bus(), passing the config accessors.
>>
>> It sounds like you want a way to parse the resources at one point,
>> saving them and marking the ECAM region, then at a later point, look
>> up the ECAM from a saved list.  We don't do that on x86 because the
>> config accessors keep an internal list of the ECAM area for each bus.
>>
>> We do of course want to put this ECAM space in the IORESOURCE_MEM tree
>> because it consumes address space and we have to make sure we don't
>> put anything else on top of it.  But we don't have any reason to
>> describe the MMIO -> config space function in that tree.  From the
>> point of view of the rest of the system, it's just MMIO space that's
>> consumed by the PCI host bridge, just like any other device-specific
>> MMIO area.
>
> What I currently do is pass the ECAM space as a resource to the PCI host
> bridge platform device. Regular and extended configuration spaces are
> given by the third and fourth resources, respectively. If I understand
> correctly, you're saying that nothing beyond that needs to be encoded.
> In other words it is enough for the PCI host bridge driver to know where
> to take the data from.

Yes, I think so.

I'd like to someday make ECAM support generic, since it's specified by
the PCIe spec.  The spec doesn't differentiate between PCI
configuration space (offsets 0-0xff) and PCI Express *extended*
configuration space (offsets 0x100-0xfff).  But it sounds like Tegra
might have a memory-mapped configuration mechanism that is similar to
ECAM but with a different address map, since you mention two resources
(third and fourth).  That's not a problem, since you're doing a
Tegra-specific solution right now anyway, but something to keep in the
back of your mind if we ever do make a generic ECAM solution.

> I'll have to see what this means for the DT binding. There are other
> issues that I need to think about, like for example how to pass the ECAM
> space from the PCI host controller to each of the two bridges via the
> ranges property. This no longer makes sense in the current form, as the
> ECAM covers the configuration spaces for devices of both bridges and
> cannot really be split among them.

We have the same situation on x86.  Part of the historical grunge that
I omitted is that there's a static ACPI table (MCFG) that can tell you
the ECAM range for a bus number range.  Often that bus number range
includes several host bridges.  On x86, we have a single set of ECAM
config accessors (see pci_mmcfg), and they maintain a list of "bus
number -> ECAM addr" mappings internally, independent of which host
bridge leads to the buses.

Bjorn


From bhelgaas at google.com  Tue Aug 14 17:55:07 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 14 Aug 2012 14:55:07 -0700
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>

On Tue, Aug 14, 2012 at 12:58 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Tue, Aug 14, 2012 at 01:39:23PM -0600, Stephen Warren wrote:
>> On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
>> > On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> ...
>> >> whereas for a device tree boot:
>> >>
>> >> (same):
>> >>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>> >>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>> >>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>> >>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>> >> ... (request region happens early)
>> >>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>> >>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>> >>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>> >>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>> >> ... (same, just happens too late)
>> >>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>> >>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>> >>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>> >>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>> >>
>> >> I suspect this is all still related to the PCI devices themselves being
>> >> probed much earlier in the overall PCI initialization sequence when the
>> >> PCI controller is probed later in the boot sequence, whereas PCI device
>> >> probe is deferred until the overall PCI initialization sequence is
>> >> complete if the PCI controller is probed very early in the boot sequence.
>> >
>> > I don't know what to apply your patches to (they don't apply cleanly
>> > to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
>> > like you might be calling pci_bus_add_devices() before
>> > pci_bus_assign_resource(), which isn't going to work.
>>
>> Yes, that's exactly what is happening.
>>
>> PCIe initialization starts in arch/arm/mach-tegra/pci.e
>> tegra_pcie_init() which calls arch/arm/kernel/bios32.c
>> pci_common_init(). That function first calls pcibios_init_hw() (in the
>> same file, more about this later) and then loops over PCI buses, calling
>> amongst other things pci_bus_assign_resources() then pci_bus_add_devices().
>>
>> The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
>> (or a host-driver-specific function which that also calls
>> pci_scan_root_bus() in Tegra's case) which in turn calls
>> pci_bus_add_devices() right at the end, before control has returned to
>> pci_common_init() and hence before pci_bus_assign_resources() has been
>> called.
>>
>> If I modify pci_scan_root_bus() and remove the call to
>> pci_bus_add_devices(), everything works as expected.
>>
>> So, I guess the question is: Should ARM's pcibios_init_hw() not be
>> calling pci_scan_root_bus(), or at least presumably the ARM PCI code
>> needs to do things in a slightly different order?

I think you need to do something like this instead of using pci_scan_root_bus():

    pci_create_root_bus()
    pci_scan_child_bus()
    pci_bus_assign_resources()
    pci_bus_add_devices()

This is the effective order used by most of the pci_create_root_bus() callers.

> Maybe pci_scan_root_bus() should be calling pci_bus_assign_resources()?
> Or a new function could be added which also assigns the resources.

Yes, it probably should.  I'm nervous about just throwing it in there
without quite a bit more analysis, but that's definitely the direction
I think we should be heading.

Bjorn


From swarren at wwwdotorg.org  Tue Aug 14 18:58:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 Aug 2012 16:58:55 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
Message-ID: <502AD82F.3080702@wwwdotorg.org>

On 08/14/2012 03:55 PM, Bjorn Helgaas wrote:
> On Tue, Aug 14, 2012 at 12:58 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
>> On Tue, Aug 14, 2012 at 01:39:23PM -0600, Stephen Warren wrote:
>>> On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
>>>> On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>> ...
>>>>> whereas for a device tree boot:
>>>>>
>>>>> (same):
>>>>>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>>>>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>>>>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>>>>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>>>>> ... (request region happens early)
>>>>>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>>>>>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>>>>>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>>>>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>>>>> ... (same, just happens too late)
>>>>>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>>>>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>>>>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>>>>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>>>>>
>>>>> I suspect this is all still related to the PCI devices themselves being
>>>>> probed much earlier in the overall PCI initialization sequence when the
>>>>> PCI controller is probed later in the boot sequence, whereas PCI device
>>>>> probe is deferred until the overall PCI initialization sequence is
>>>>> complete if the PCI controller is probed very early in the boot sequence.
>>>>
>>>> I don't know what to apply your patches to (they don't apply cleanly
>>>> to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
>>>> like you might be calling pci_bus_add_devices() before
>>>> pci_bus_assign_resource(), which isn't going to work.
>>>
>>> Yes, that's exactly what is happening.
>>>
>>> PCIe initialization starts in arch/arm/mach-tegra/pci.e
>>> tegra_pcie_init() which calls arch/arm/kernel/bios32.c
>>> pci_common_init(). That function first calls pcibios_init_hw() (in the
>>> same file, more about this later) and then loops over PCI buses, calling
>>> amongst other things pci_bus_assign_resources() then pci_bus_add_devices().
>>>
>>> The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
>>> (or a host-driver-specific function which that also calls
>>> pci_scan_root_bus() in Tegra's case) which in turn calls
>>> pci_bus_add_devices() right at the end, before control has returned to
>>> pci_common_init() and hence before pci_bus_assign_resources() has been
>>> called.
>>>
>>> If I modify pci_scan_root_bus() and remove the call to
>>> pci_bus_add_devices(), everything works as expected.
>>>
>>> So, I guess the question is: Should ARM's pcibios_init_hw() not be
>>> calling pci_scan_root_bus(), or at least presumably the ARM PCI code
>>> needs to do things in a slightly different order?
> 
> I think you need to do something like this instead of using pci_scan_root_bus():
> 
>     pci_create_root_bus()
>     pci_scan_child_bus()
>     pci_bus_assign_resources()
>     pci_bus_add_devices()
> 
> This is the effective order used by most of the pci_create_root_bus() callers.

That would pretty much duplicate everything in pci_scan_root_bus(). That
might cause divergence down the road.

Can't we make the call to pci_bus_add_devices() optional in
pci_scan_root_bus() somehow; one of:

* Add a parameter to pci_scan_root_bus() controlling this.

(rather a large patch)

* Split pci_scan_root_bus() into pci_scan_root_bus() and
pci_scan_root_bus_no_add(), such that pci_scan_root_bus() is just a
wrapper that calls pci_scan_root_bus_no_add() then pci_bus_add_devices().

(very simple patch, and the new function can easily be used as/when it's
needed, e.g. enabled just for Tegra in 3.6 to reduce risk of regressions)

* Add a flag to struct pci_bus that requests pci_scan_root_bus() skip
the call to pci_bus_add_devices().

(a flag in the bus struct just for one function seems a little
circuitous, but perhaps OK)

* ifdef out the call to pci_bus_add_devices(), if building for ARM.

(very simple, and probably correct)

Actually, I'm not totally convinced some other archs shouldn't skip this
too; while I couldn't find any other arch that explicitly calls
pci_bus_assign_resources() and pci_bus_add_devices() after
pci_scan_root_bus(), I did see some that call
pci_assign_unassigned_resources() which seems like it might be due to a
similar situation?

* Add another pcibios_*() callback that pci_scan_root_bus() calls to
determine whether to call pci_bus_add_devices(), with default
implementation.


From olof at lixom.net  Tue Aug 14 19:06:45 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 16:06:45 -0700
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120814230645.GA19607@quad.lixom.net>

Hi,


On Tue, Aug 14, 2012 at 06:52:03PM +0100, Catalin Marinas wrote:

> +Before jumping into the kernel, the following conditions must be met:
> +
> +- Quiesce all DMA capable devices so that memory does not get
> +  corrupted by bogus network packets or disk data.  This will save
> +  you many hours of debug.
> +
> +- Primary CPU general-purpose register settings
> +  x0 = physical address of device tree blob (dtb) in system RAM.
> +
> +- CPU mode
> +  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> +  IRQ and FIQ).
> +  The CPU must be in either EL2 (RECOMMENDED in order to have access to
> +  the virtualisation extensions) or non-secure EL1.
> +
> +- Caches, MMUs
> +  The MMU must be off.
> +  Instruction cache may be on or off.
> +  Data cache must be off and invalidated.
> +
> +- Architected timers
> +  CNTFRQ must be programmed with the timer frequency.
> +  If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
> +  set where available.
> +
> +- Coherency
> +  All CPUs to be booted by the kernel must be part of the same coherency
> +  domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
> +  initialisation to enable the receiving of maintenance operations on
> +  each CPU.
> +
> +- System registers
> +  All writable architected system registers at the exception level where
> +  the kernel image will be entered must be initialised by software at a
> +  higher exception level to prevent execution in an UNKNOWN state.

Given the recent development of ARM platforms, you might want to mandate
the state of IOMMUs as well (they should probably be off, since there
should be no active DMA activity). Graphics would be the exception to
this, since if you want to keep scanning out a splash screen, you'll
have to keep doing DMA...

> +- The primary CPU must jump directly to the first instruction of the
> +  kernel image.  The device tree blob passed by this CPU must contain
> +  for each CPU node:
> +
> +    1. An 'enable-method' property. Currently, the only supported value
> +       for this field is the string "spin-table".
> +
> +    2. A 'cpu-release-addr' property identifying a 64-bit,
> +       zero-initialised memory location.

These would be good to have documented in the
Documentation/devicetree/bindings hierarchy as well.

> index 0000000..d766493
> --- /dev/null
> +++ b/arch/arm64/include/asm/setup.h
> @@ -0,0 +1,26 @@
> +/*
> + * Based on arch/arm/include/asm/setup.h
> + *
> + * Copyright (C) 1997-1999 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_SETUP_H
> +#define __ASM_SETUP_H
> +
> +#include <linux/types.h>
> +
> +#define COMMAND_LINE_SIZE 1024

Probably not a huge deal, and other architectures seem to be all over
the map on this, but you might want to go with a larger value now rather
than later. 2048 or 4096 perhaps?

> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> new file mode 100644
> index 0000000..34ccdc0
> --- /dev/null
> +++ b/arch/arm64/kernel/head.S

[...]

> +/*
> + * Setup common bits before finally enabling the MMU. Essentially this is just
> + * loading the page table pointer and vector base registers.
> + *
> + * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
> + * the MMU.
> + */
> +__enable_mmu:

ENTRY()?

> +	ldr	x5, =vectors
> +	msr	vbar_el1, x5
> +	msr	ttbr0_el1, x25			// load TTBR0
> +	msr	ttbr1_el1, x26			// load TTBR1
> +	isb
> +	b	__turn_mmu_on
> +ENDPROC(__enable_mmu)

...or just END()? Same for a few of the other functions below.

> diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> new file mode 100644
> index 0000000..f25186f
> --- /dev/null
> +++ b/arch/arm64/kernel/setup.c

[...]

> +static void __init setup_processor(void)
> +{
> +	struct proc_info_list *list;
> +
> +	/*
> +	 * locate processor in the list of supported processor
> +	 * types.  The linker builds this table for us from the
> +	 * entries in arch/arm/mm/proc.S
> +	 */

Probably from arch/arm64/... somewhere?


[...]

> +	printk("CPU: %s [%08x] revision %d\n",
> +	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
> +
> +	sprintf(init_utsname()->machine, "aarch64");

> +	initial_boot_params = devtree;
> +	dt_root = of_get_flat_dt_root();
> +
> +	machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
> +	if (!machine_name)
> +		machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
> +	if (!machine_name)
> +		machine_name = "<unknown>";
> +	pr_info("Machine: %s\n", machine_name);

This property is an array of strings. It would be more valuable to print out
the entry that was matched for a platform instead of the provided one from the
device tree.


-Olof


From jason at lakedaemon.net  Tue Aug 14 19:22:56 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 19:22:56 -0400
Subject: [PATCH v2 1/2] ARM: kirkwood: DT board setup for Seagate
 FreeAgent Dockstar
In-Reply-To: <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <20120814193613.GS22226@titan.lakedaemon.net>
 <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <20120814232256.GX22226@titan.lakedaemon.net>

On Tue, Aug 14, 2012 at 10:43:41PM +0200, Sebastian Hesselbarth wrote:
> This add a DT compatible board specific setup for the Seagate
> FreeAgent Dockstar.
> 
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> ---
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> 
> v2: rebased on git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

patches [1/2] and [2/2] of this series applied to:

  git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

patch [2/2] depends upon:

  bda63c1 ARM: Kirkwood: fix Makefile.boot

which should be in an upcoming v3.6-rc

thx,

Jason.


From aaro.koskinen at iki.fi  Tue Aug 14 19:22:50 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed, 15 Aug 2012 02:22:50 +0300
Subject: [PATCH v2 11/31] arm64: IRQ handling
In-Reply-To: <1344966752-16102-12-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-12-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120814232250.GB747@harshnoise.musicnaut.iki.fi>

Hi,

On Tue, Aug 14, 2012 at 06:52:12PM +0100, Catalin Marinas wrote:
> +void handle_IRQ(unsigned int irq, struct pt_regs *regs)
> +{
> +	struct pt_regs *old_regs = set_irq_regs(regs);
> +
> +	irq_enter();
> +
> +	/*
> +	 * Some hardware gives randomly wrong interrupts.  Rather
> +	 * than crashing, do something sensible.
> +	 */
> +	if (unlikely(irq >= nr_irqs)) {
> +		if (printk_ratelimit())
> +			pr_warning("Bad IRQ%u\n", irq);

I guess pr_warn_ratelimited() should be used for new code.

(See include/linux/printk.h, "Please don't use printk_ratelimit()...")

A.


From olof at lixom.net  Tue Aug 14 19:29:07 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 16:29:07 -0700
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120814232907.GB19607@quad.lixom.net>

Hi,

This one is a bit denser, so just a quick first pass with a couple of minor
comments. I'll revisit the rest.

On Tue, Aug 14, 2012 at 06:52:04PM +0100, Catalin Marinas wrote:

> +el1_sp_pc:
> +	/*
> +	 *Stack or PC alignment exception handling
> +	 */
> +	mrs	x0, far_el1
> +	mov	x1, x25
> +	mov	x2, sp
> +	b	do_sp_pc_abort
> +el1_undef:
> +	/*
> +	 *Undefined instruction
> +	 */

Nit: Missing spaces in the comment here and the one above.

> +el0_undef:
> +	/*
> +	 *Undefined instruction
> +	 */
> +	mov	x0, sp
> +	b	do_undefinstr

Here too.

> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> new file mode 100644
> index 0000000..8712a8e
> --- /dev/null
> +++ b/arch/arm64/kernel/traps.c
[...]
> +DEFINE_SPINLOCK(die_lock);

Should probably be static.



From jason at lakedaemon.net  Tue Aug 14 19:44:42 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 19:44:42 -0400
Subject: [GIT PULL] orion/kirkwood fixes for v3.6
Message-ID: <20120814234442.GZ22226@titan.lakedaemon.net>

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

Arnaud Patard (3):
      ARM: Orion: Set eth packet size csum offload limit
      ARM: Kirkwood: Fix iconnect leds
      ARM: Kirkwood: fix Makefile.boot

 arch/arm/boot/dts/kirkwood-iconnect.dts   |    6 +++++-
 arch/arm/mach-dove/common.c               |    3 ++-
 arch/arm/mach-kirkwood/Makefile.boot      |    3 ++-
 arch/arm/mach-kirkwood/common.c           |    4 ++--
 arch/arm/mach-mv78xx0/common.c            |    6 ++++--
 arch/arm/mach-orion5x/common.c            |    3 ++-
 arch/arm/plat-orion/common.c              |    8 ++++++--
 arch/arm/plat-orion/include/plat/common.h |    6 ++++--
 include/linux/mv643xx_eth.h               |    2 ++
 9 files changed, 29 insertions(+), 12 deletions(-)


From tglx at linutronix.de  Tue Aug 14 19:47:15 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 15 Aug 2012 01:47:15 +0200 (CEST)
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <20120814232907.GB19607@quad.lixom.net>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
 <20120814232907.GB19607@quad.lixom.net>
Message-ID: <alpine.LFD.2.02.1208150146460.32033@ionos>

On Tue, 14 Aug 2012, Olof Johansson wrote:
> > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> > new file mode 100644
> > index 0000000..8712a8e
> > --- /dev/null
> > +++ b/arch/arm64/kernel/traps.c
> [...]
> > +DEFINE_SPINLOCK(die_lock);
> 
> Should probably be static.

And RAW_


From olof at lixom.net  Tue Aug 14 19:50:13 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 16:50:13 -0700
Subject: [PATCH v2 07/31] arm64: Process management
In-Reply-To: <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120814235013.GC19607@quad.lixom.net>

Hi,

On Tue, Aug 14, 2012 at 06:52:08PM +0100, Catalin Marinas wrote:

> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
> new file mode 100644
> index 0000000..c4a4e1c
> --- /dev/null
> +++ b/arch/arm64/kernel/process.c
> @@ -0,0 +1,416 @@

[...]
> +/*
> + * Function pointers to optional machine specific functions
> + */
> +void (*pm_power_off)(void);
> +EXPORT_SYMBOL(pm_power_off);
> +
> +void (*pm_restart)(const char *cmd);
> +EXPORT_SYMBOL_GPL(pm_restart);
[...]
> +void (*pm_idle)(void) = default_idle;
> +EXPORT_SYMBOL(pm_idle);

Does it really make sense to export these to modules?

I find the powerpc way of having a machine descriptor structure with these
(and other) function pointers in it a bit cleaner, since it gives you
one place to plug it all in. I'd recommend that you consider doing that
here as well, for these three and potentially other cases in the future.

(See arch/powerpc/include/asm/machdep.h, struct machdep_calls).

> +void machine_halt(void)
> +{
> +	machine_shutdown();
> +	while (1);
> +}
> +
> +void machine_power_off(void)
> +{
> +	machine_shutdown();
> +	if (pm_power_off)
> +		pm_power_off();
> +}

Printing something here along the lines of "System halted, OK to power off"
is useful.


-Olof


From bhelgaas at google.com  Tue Aug 14 19:50:26 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 14 Aug 2012 16:50:26 -0700
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>

On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
>> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
>> index a094c97..c886dff 100644
>> --- a/arch/arm/boot/dts/tegra20.dtsi
>> +++ b/arch/arm/boot/dts/tegra20.dtsi
>> @@ -199,6 +199,68 @@
>>               #size-cells = <0>;
>>       };
>>
>> +     pcie-controller {
>> +             compatible = "nvidia,tegra20-pcie";
>> +             reg = <0x80003000 0x00000800   /* PADS registers */
>> +                    0x80003800 0x00000200   /* AFI registers */
>> +                    0x81000000 0x01000000   /* configuration space */
>> +                    0x90000000 0x10000000>; /* extended configuration space */
>> +             interrupts = <0 98 0x04   /* controller interrupt */
>> +                           0 99 0x04>; /* MSI interrupt */
>> +             status = "disabled";
>> +
>> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
>> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
>> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
>> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
>> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
>> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
>> +
>> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
>> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
>> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
>> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
>> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
>> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
>
> I've been thinking about this some more. The translations for both the
> regular and extended configuration spaces are configured in the top-
> level PCIe controller. It is therefore wrong how they are passed to the
> PCI host bridges via the ranges property.
>
> I remember Mitch saying that it should be passed down to the children
> because it is partitioned among them, but since the layout is compatible
> with ECAM, the partitioning isn't as simple as what's in the tree. In
> fact the partitions will be dependent on the number of devices attached
> to the host bridges.

I don't understand this last bit about the number of devices attached
to the host bridges.  Logically, the host bridge has a bus number
aperture that you can know up front, even before you know anything
about what devices are below it.  On x86, for example, the ACPI _CRS
method has something like "[bus 00-7f]" in it, which means that any
buses in that range are below this bridge.  That doesn't tell us
anything about which buses actually have devices on them, of course;
it's just analogous to the secondary and subordinate bus number
registers in a P2P bridge.

>> +
>> +             #address-cells = <3>;
>> +             #size-cells = <1>;
>> +
>> +             pci at 0 {
>> +                     device_type = "pciex";
>> +                     reg = <0 0 0 0x1000>;
>> +                     status = "disabled";
>> +
>> +                     #address-cells = <3>;
>> +                     #size-cells = <2>;
>> +
>> +                     ranges = <0x80000000 0 0  0 1 0  0 0x00800000   /* config space */
>> +                               0x90000000 0 0  0 2 0  0 0x08000000   /* ext config space */
>> +                               0x81000000 0 0  0 3 0  0 0x00010000   /* I/O */
>> +                               0x82000000 0 0  0 4 0  0 0x08000000   /* non-prefetchable memory */
>> +                               0xc2000000 0 0  0 5 0  0 0x08000000>; /* prefetchable memory */
>> +
>> +                     nvidia,num-lanes = <2>;
>> +             };
>> +
>> +             pci at 1 {
>> +                     device_type = "pciex";
>> +                     reg = <1 0 0 0x1000>;
>> +                     status = "disabled";
>> +
>> +                     #address-cells = <3>;
>> +                     #size-cells = <2>;
>> +
>> +                     ranges = <0x80000000 0 0  1 1 0  0 0x00800000   /* config space */
>> +                               0x90000000 0 0  1 2 0  0 0x08000000   /* ext config space */
>> +                               0x81000000 0 0  1 3 0  0 0x00010000   /* I/O */
>> +                               0x82000000 0 0  1 4 0  0 0x08000000   /* non-prefetchable memory */
>> +                               0xc2000000 0 0  1 5 0  0 0x08000000>; /* prefetchable memory */
>> +
>> +                     nvidia,num-lanes = <2>;
>> +             };
>> +     };
>
> The same is true for the ranges properties of the PCI host bridge nodes.
> Which part of the configuration spaces maps to the children of the
> respective host bridge depends on the actual device hierarchy.
>
> Would it be possible to alternatively pass the complete range to the
> children without further partitioning?
>
> The driver doesn't actually care about the ranges property and only uses
> the values specified in the reg property of the pcie-controller node.
>
> Thierry


From swarren at wwwdotorg.org  Tue Aug 14 19:51:33 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 14 Aug 2012 17:51:33 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502AD82F.3080702@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org>
Message-ID: <502AE485.8060307@wwwdotorg.org>

On 08/14/2012 04:58 PM, Stephen Warren wrote:
> On 08/14/2012 03:55 PM, Bjorn Helgaas wrote:
>> On Tue, Aug 14, 2012 at 12:58 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>>> On Tue, Aug 14, 2012 at 01:39:23PM -0600, Stephen Warren wrote:
>>>> On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
>>>>> On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>>> ...
>>>>>> whereas for a device tree boot:
>>>>>>
>>>>>> (same):
>>>>>>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>>>>>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>>>>>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>>>>>> ... (request region happens early)
>>>>>>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>>>>>>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>>>>>> ... (same, just happens too late)
>>>>>>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>>>>>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>>>>>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>>>>>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>>>>>>
>>>>>> I suspect this is all still related to the PCI devices themselves being
>>>>>> probed much earlier in the overall PCI initialization sequence when the
>>>>>> PCI controller is probed later in the boot sequence, whereas PCI device
>>>>>> probe is deferred until the overall PCI initialization sequence is
>>>>>> complete if the PCI controller is probed very early in the boot sequence.
>>>>>
>>>>> I don't know what to apply your patches to (they don't apply cleanly
>>>>> to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
>>>>> like you might be calling pci_bus_add_devices() before
>>>>> pci_bus_assign_resource(), which isn't going to work.
>>>>
>>>> Yes, that's exactly what is happening.
>>>>
>>>> PCIe initialization starts in arch/arm/mach-tegra/pci.e
>>>> tegra_pcie_init() which calls arch/arm/kernel/bios32.c
>>>> pci_common_init(). That function first calls pcibios_init_hw() (in the
>>>> same file, more about this later) and then loops over PCI buses, calling
>>>> amongst other things pci_bus_assign_resources() then pci_bus_add_devices().
>>>>
>>>> The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
>>>> (or a host-driver-specific function which that also calls
>>>> pci_scan_root_bus() in Tegra's case) which in turn calls
>>>> pci_bus_add_devices() right at the end, before control has returned to
>>>> pci_common_init() and hence before pci_bus_assign_resources() has been
>>>> called.
>>>>
>>>> If I modify pci_scan_root_bus() and remove the call to
>>>> pci_bus_add_devices(), everything works as expected.
>>>>
>>>> So, I guess the question is: Should ARM's pcibios_init_hw() not be
>>>> calling pci_scan_root_bus(), or at least presumably the ARM PCI code
>>>> needs to do things in a slightly different order?
>>
>> I think you need to do something like this instead of using pci_scan_root_bus():
>>
>>     pci_create_root_bus()
>>     pci_scan_child_bus()
>>     pci_bus_assign_resources()
>>     pci_bus_add_devices()
>>
>> This is the effective order used by most of the pci_create_root_bus() callers.
> 
> That would pretty much duplicate everything in pci_scan_root_bus(). That
> might cause divergence down the road.
> 
> Can't we make the call to pci_bus_add_devices() optional in
> pci_scan_root_bus() somehow; one of:

Sigh, that turns out not to work correctly; it solves at least this part
of the problem when booting using device tree, but when booting using a
board file, it causes the IRQ number passed to the PCIe device to be
bogus:-(

I give up for now.


From jason at lakedaemon.net  Tue Aug 14 19:56:53 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 14 Aug 2012 19:56:53 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
Message-ID: <20120814235653.GA22226@titan.lakedaemon.net>

On Tue, Aug 14, 2012 at 09:06:16PM +0100, Ownerx35 wrote:
> I have created a patch and have tested it myself that create a board
> setup file for the Iomega StoreCenter IX2-200, create a dts file and
> insert the appropriate lines into the common.h, makefile,
> makefile.boot, kconfig and board-ft files.

Awesome!

> But am unsure how to properly submit it should i just post it here? or
> is there a specific place i should post?

Take a look at /path/to/linux_src/Documentation/SubmittingPatches .

If you prefer working with git, the two commands I use are format-patch
and then send-email.

Assuming the board is ARM based (most likely), then you've found the
correct list.

Just post the series here and we'll offer helpful comments ;-)

Also, please check MAINTAINERS for the directories you are changing and
include the maintainers in the CC: or TO:.  Most likely, that'll be
myself and Andrew Lunn (kirkwood / orion boards).

hth,

Jason.


From josh.coombs at gmail.com  Tue Aug 14 19:59:00 2012
From: josh.coombs at gmail.com (Josh Coombs)
Date: Tue, 14 Aug 2012 19:59:00 -0400
Subject: Potential Regression in 3.6-rc1 - Kirkwood SATA
Message-ID: <CAMW5UfZ_kVz_b4_98zPdY2RFjTMN9H2OzjYcRQrCTgA1xqdmPw@mail.gmail.com>

I finally got a chance to test 3.6-rc1 after having my GoFlex Net
support patch accepted for the 3.6 release train.  Included in 3.6-rc1
was an update for Kirkwoods switching SATA to DT which was not part of
my original testing.  It seems something with this change has
partially broken the GoFlex and a couple other Kirkwood based devices.

The key factor is the number of SATA ports defined in the dts:

		sata at 80000 {
			status = "okay";
			nr-ports = <2>;
		};

If set at the correct number for my device, 2, my GFN does not
complete kernel init, hanging here:

<SNIP>
[   15.287832] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[   15.296545] jffs2: version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
[   15.303202] msgmni has been set to 240
[   15.308503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major )
[   15.316021] io scheduler noop registered
[   15.320149] io scheduler deadline registered
[   15.324558] io scheduler cfq registered (default)
[   15.329462] mv_xor_shared mv_xor_shared.0: Marvell shared XOR driver
[   15.335962] mv_xor_shared mv_xor_shared.1: Marvell shared XOR driver
[   15.376751] mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
[   15.416736] mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )
[   15.456735] mv_xor mv_xor.2: Marvell XOR: ( xor cpy )
[   15.496734] mv_xor mv_xor.3: Marvell XOR: ( xor fill cpy )
[   15.506309] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[   15.509111] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
[   15.509141] console [ttyS0] enabled, bootconsole disabled
[   15.518967] brd: module loaded
[   15.524991] loop: module loaded
[   15.528584] sata_mv sata_mv.0: cannot get optional clkdev
[   15.534180] sata_mv sata_mv.0: slots 32 ports 2

If you set nr-ports to 1 the unit boots cleanly, save for only
detecting one functional SATA port.  Another user has confirmed this
behavior on an Iomega IX2-200.

I bounced this off Andrew before bringing it to the list proper.  His
initial hunch puts the culprit in or around:


#if defined(CONFIG_HAVE_CLK)
        hpriv->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(hpriv->clk))
                dev_notice(&pdev->dev, "cannot get optional clkdev\n");
        else
                clk_prepare_enable(hpriv->clk);

        for (port = 0; port < n_ports; port++) {
                char port_number[16];
                sprintf(port_number, "%d", port);
                hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
                if (!IS_ERR(hpriv->port_clks[port]))
                        clk_prepare_enable(hpriv->port_clks[port]);
        }
#endif

I haven't had a chance to play with this yet to see if I can figure it
out, something about having the second port enabled seems to be
mucking with the clocks on Kirkwoods.

Joshua Coombs


From akpm at linux-foundation.org  Tue Aug 14 20:03:00 2012
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 14 Aug 2012 17:03:00 -0700
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120814170300.8f97afcf.akpm@linux-foundation.org>

On Fri, 13 Jul 2012 15:31:03 +0800
Shawn Guo <shawn.guo at linaro.org> wrote:

> +static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
> +{
> +	unsigned long timeout = jiffies + msecs_to_jiffies(1);
> +	unsigned long flags;
> +	u32 lpcr;
> +
> +	spin_lock_irqsave(&data->lock, flags);
> +
> +	lpcr = readl(data->ioaddr + SNVS_LPCR);
> +	if (enable)
> +		lpcr |= SNVS_LPCR_SRTC_ENV;
> +	else
> +		lpcr &= ~SNVS_LPCR_SRTC_ENV;
> +	writel(lpcr, data->ioaddr + SNVS_LPCR);
> +
> +	spin_unlock_irqrestore(&data->lock, flags);
> +
> +	while (1) {
> +		lpcr = readl(data->ioaddr + SNVS_LPCR);
> +
> +		if (enable) {
> +			if (lpcr & SNVS_LPCR_SRTC_ENV)
> +				break;
> +		} else {
> +			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
> +				break;
> +		}
> +
> +		if (time_after(jiffies, timeout))
> +			return -ETIMEDOUT;
> +	}
> +
> +	return 0;
> +}

The timeout code here is fragile.  If acquiring the spinlock takes more
than a millisecond or if this thread gets interrupted or preempted then
we could easily execute that loop just a single time, and fail.

It would be better to retry a fixed number of times, say 1000?  That
would take around 1 millisecond, but might be overkill.



From bhelgaas at google.com  Tue Aug 14 20:08:33 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 14 Aug 2012 17:08:33 -0700
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502AD82F.3080702@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org>
Message-ID: <CAErSpo40sydj+ufaqXu_iGFncJWuQGAkc-+ucesXJasb7js5-g@mail.gmail.com>

On Tue, Aug 14, 2012 at 3:58 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/14/2012 03:55 PM, Bjorn Helgaas wrote:
>> On Tue, Aug 14, 2012 at 12:58 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>>> On Tue, Aug 14, 2012 at 01:39:23PM -0600, Stephen Warren wrote:
>>>> On 08/13/2012 05:18 PM, Bjorn Helgaas wrote:
>>>>> On Mon, Aug 13, 2012 at 11:47 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>>>> ...
>>>>>> whereas for a device tree boot:
>>>>>>
>>>>>> (same):
>>>>>>> [    2.112217] pci 0000:01:00.0: reg 10: [io  0x0000-0x00ff]
>>>>>>> [    2.117635] pci 0000:01:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.124690] pci 0000:01:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref]
>>>>>>> [    2.131731] pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0001ffff pref]
>>>>>> ... (request region happens early)
>>>>>>> [    2.179838] r8169 0000:01:00.0: BAR 0: requesting [io  0x0000-0x00ff]
>>>>>>> [    2.193312] r8169 0000:01:00.0: BAR 2: requesting [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.201397] r8169 0000:01:00.0: BAR 2: can't reserve [mem 0x00000000-0x00000fff 64bit pref]
>>>>>>> [    2.209742] r8169 0000:01:00.0: (unregistered net_device): could not request regions
>>>>>> ... (same, just happens too late)
>>>>>>> [    2.236818] pci 0000:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa001ffff pref]
>>>>>>> [    2.244027] pci 0000:01:00.0: BAR 4: assigned [mem 0xa0020000-0xa0023fff 64bit pref]
>>>>>>> [    2.251794] pci 0000:01:00.0: BAR 2: assigned [mem 0xa0024000-0xa0024fff 64bit pref]
>>>>>>> [    2.259542] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
>>>>>>
>>>>>> I suspect this is all still related to the PCI devices themselves being
>>>>>> probed much earlier in the overall PCI initialization sequence when the
>>>>>> PCI controller is probed later in the boot sequence, whereas PCI device
>>>>>> probe is deferred until the overall PCI initialization sequence is
>>>>>> complete if the PCI controller is probed very early in the boot sequence.
>>>>>
>>>>> I don't know what to apply your patches to (they don't apply cleanly
>>>>> to v3.6-rc2), so I can't see exactly what you're doing.  But it looks
>>>>> like you might be calling pci_bus_add_devices() before
>>>>> pci_bus_assign_resource(), which isn't going to work.
>>>>
>>>> Yes, that's exactly what is happening.
>>>>
>>>> PCIe initialization starts in arch/arm/mach-tegra/pci.e
>>>> tegra_pcie_init() which calls arch/arm/kernel/bios32.c
>>>> pci_common_init(). That function first calls pcibios_init_hw() (in the
>>>> same file, more about this later) and then loops over PCI buses, calling
>>>> amongst other things pci_bus_assign_resources() then pci_bus_add_devices().
>>>>
>>>> The problem is that ARM's pcibios_init_hw() calls pci_scan_root_bus()
>>>> (or a host-driver-specific function which that also calls
>>>> pci_scan_root_bus() in Tegra's case) which in turn calls
>>>> pci_bus_add_devices() right at the end, before control has returned to
>>>> pci_common_init() and hence before pci_bus_assign_resources() has been
>>>> called.
>>>>
>>>> If I modify pci_scan_root_bus() and remove the call to
>>>> pci_bus_add_devices(), everything works as expected.
>>>>
>>>> So, I guess the question is: Should ARM's pcibios_init_hw() not be
>>>> calling pci_scan_root_bus(), or at least presumably the ARM PCI code
>>>> needs to do things in a slightly different order?
>>
>> I think you need to do something like this instead of using pci_scan_root_bus():
>>
>>     pci_create_root_bus()
>>     pci_scan_child_bus()
>>     pci_bus_assign_resources()
>>     pci_bus_add_devices()
>>
>> This is the effective order used by most of the pci_create_root_bus() callers.
>
> That would pretty much duplicate everything in pci_scan_root_bus(). That
> might cause divergence down the road.

That's true, but it is what most other architectures do, and if you do
it the same way, we'll be able to converge things more easily later.

> Can't we make the call to pci_bus_add_devices() optional in
> pci_scan_root_bus() somehow; one of:
>
> * Add a parameter to pci_scan_root_bus() controlling this.
>
> (rather a large patch)
>
> * Split pci_scan_root_bus() into pci_scan_root_bus() and
> pci_scan_root_bus_no_add(), such that pci_scan_root_bus() is just a
> wrapper that calls pci_scan_root_bus_no_add() then pci_bus_add_devices().
>
> (very simple patch, and the new function can easily be used as/when it's
> needed, e.g. enabled just for Tegra in 3.6 to reduce risk of regressions)
>
> * Add a flag to struct pci_bus that requests pci_scan_root_bus() skip
> the call to pci_bus_add_devices().
>
> (a flag in the bus struct just for one function seems a little
> circuitous, but perhaps OK)
>
> * ifdef out the call to pci_bus_add_devices(), if building for ARM.
>
> (very simple, and probably correct)

I'd rather not add more variants of pci_scan_root_bus().  We already
have several very similar things in drivers/pci/probe.c:

  pci_scan_bus()
  pci_scan_bus_parented()
  pci_scan_root_bus()

And in addition, we have many callers of pci_create_root_bus() that
look very much like one of these.  I'm trying to consolidate all this,
but there's a fair amount of work, and I think the simplest thing is
to just use pci_create_root_bus() for now.

> Actually, I'm not totally convinced some other archs shouldn't skip this
> too; while I couldn't find any other arch that explicitly calls
> pci_bus_assign_resources() and pci_bus_add_devices() after
> pci_scan_root_bus(), I did see some that call
> pci_assign_unassigned_resources() which seems like it might be due to a
> similar situation?

Yes, that does sound like a similar problem.  In the past, resource
assignment has been pretty much separate from enumeration, with the
arch having the responsibility to enumerate, assign, then add devices.
 But that is error-prone and needlessly arch-specific, and I'd like to
pull it into generic code.  It's just not done yet :)

> * Add another pcibios_*() callback that pci_scan_root_bus() calls to
> determine whether to call pci_bus_add_devices(), with default
> implementation.


From olof at lixom.net  Tue Aug 14 20:10:43 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 17:10:43 -0700
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120815001043.GD19607@quad.lixom.net>

Hi,

On Tue, Aug 14, 2012 at 06:52:09PM +0100, Catalin Marinas wrote:

> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> new file mode 100644
> index 0000000..ef54125
> --- /dev/null
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_CPUTYPE_H
> +#define __ASM_CPUTYPE_H
> +
> +#define ID_MIDR_EL1		"midr_el1"
> +#define ID_CTR_EL0		"ctr_el0"
> +
> +#define ID_AA64PFR0_EL1		"id_aa64pfr0_el1"
> +#define ID_AA64DFR0_EL1		"id_aa64dfr0_el1"
> +#define ID_AA64AFR0_EL1		"id_aa64afr0_el1"
> +#define ID_AA64ISAR0_EL1	"id_aa64isar0_el1"
> +#define ID_AA64MMFR0_EL1	"id_aa64mmfr0_el1"
> +
> +#define read_cpuid(reg) ({						\
> +	u64 __val;							\
> +	asm("mrs	%0, " reg : "=r" (__val));			\
> +	__val;								\
> +})
> +
> +/*
> + * The CPU ID never changes at run time, so we might as well tell the
> + * compiler that it's constant.  Use this function to read the CPU ID
> + * rather than directly reading processor_id or read_cpuid() directly.
> + */
> +static inline u32 __attribute_const__ read_cpuid_id(void)
> +{
> +	return read_cpuid(ID_MIDR_EL1);
> +}
> +
> +static inline u32 __attribute_const__ read_cpuid_cachetype(void)
> +{
> +	return read_cpuid(ID_CTR_EL0);
> +}

Is this perhaps a carry-over from arch/arm? Abstracting out read_cpuid()
doesn't seem to buy anything here, just opencode the one-line assembly
in each.

Might as well cleanup the naming a little too while you're at it, i.e.
read_cpu_id() and read_cpu_cachetype().


> diff --git a/arch/arm64/include/asm/procinfo.h b/arch/arm64/include/asm/procinfo.h
> new file mode 100644
> index 0000000..81fece9
> --- /dev/null
> +++ b/arch/arm64/include/asm/procinfo.h
> @@ -0,0 +1,44 @@
> +/*
> + * Based on arch/arm/include/asm/procinfo.h
> + *
> + * Copyright (C) 1996-1999 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_PROCINFO_H
> +#define __ASM_PROCINFO_H
> +
> +#ifdef __KERNEL__
> +
> +/*
> + * Note!  struct processor is always defined if we're
> + * using MULTI_CPU, otherwise this entry is unused,
> + * but still exists.

Stale comment?

> + *
> + * NOTE! The following structure is defined by assembly
> + * language, NOT C code.  For more information, check:
> + *  arch/arm/mm/proc-*.S and arch/arm/kernel/head.S

Stale references. Also, no current arm64 implementation uses this. Premature
abstraction perhaps?

> +struct proc_info_list {
> +	unsigned int		cpu_val;
> +	unsigned int		cpu_mask;
> +	unsigned long		__cpu_flush;		/* used by head.S */
> +	const char		*cpu_name;
> +};
> +
> +#else	/* __KERNEL__ */
> +#include <asm/elf.h>
> +#warning "Please include asm/elf.h instead"
> +#endif	/* __KERNEL__ */
> +#endif
> diff --git a/arch/arm64/mm/proc-syms.c b/arch/arm64/mm/proc-syms.c
> new file mode 100644
> index 0000000..2d99ef9
> --- /dev/null
> +++ b/arch/arm64/mm/proc-syms.c
> @@ -0,0 +1,31 @@
> +/*
> + * Based on arch/arm/mm/proc-syms.c
> + *
> + * Copyright (C) 2000-2002 Russell King
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/export.h>
> +#include <linux/mm.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/proc-fns.h>
> +#include <asm/tlbflush.h>
> +#include <asm/page.h>
> +
> +EXPORT_SYMBOL(__cpuc_flush_kern_all);
> +EXPORT_SYMBOL(__cpuc_flush_user_all);
> +EXPORT_SYMBOL(__cpuc_flush_user_range);
> +EXPORT_SYMBOL(__cpuc_coherent_kern_range);
> +EXPORT_SYMBOL(__cpuc_flush_dcache_area);

See comment on other email about putting function pointers in a struct
instead.

> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> new file mode 100644
> index 0000000..453f517
> --- /dev/null
> +++ b/arch/arm64/mm/proc.S
> @@ -0,0 +1,193 @@
> +	.section ".proc.info.init", #alloc, #execinstr
> +
> +	.type	__v8_proc_info, #object
> +__v8_proc_info:
> +	.long	0x000f0000			// Required ID value
> +	.long	0x000f0000			// Mask for ID
> +	b	__cpu_setup
> +	nop
> +	.quad	cpu_name
> +	.long	0
> +	.size	__v8_proc_info, . - __v8_proc_info

I know this is a carry-over from arch/arm, but how about moving this
to more of a C construct similar to arch/powerpc/kernel/cputable.c
instead? It's considerably easier to read that way, and it's convenient
to have the definitions all in one place, making it easier to share some
of the functions, etc.


-Olof


From olof at lixom.net  Tue Aug 14 20:21:30 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 17:21:30 -0700
Subject: [PATCH v2 12/31] arm64: Atomic operations
In-Reply-To: <1344966752-16102-13-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-13-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120815002130.GE19607@quad.lixom.net>

Hi,

On Tue, Aug 14, 2012 at 06:52:13PM +0100, Catalin Marinas wrote:
> This patch introduces the atomic, mutex and futex operations. Many
> atomic operations use the load-acquire and store-release operations
> which imply barriers, avoiding the need for explicit DMB.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> ---
>  arch/arm64/include/asm/atomic.h |  306 +++++++++++++++++++++++++++++++++++++++
>  arch/arm64/include/asm/futex.h  |  134 +++++++++++++++++
>  2 files changed, 440 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm64/include/asm/atomic.h
>  create mode 100644 arch/arm64/include/asm/futex.h
> 
> diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
> new file mode 100644
> index 0000000..fa60c8b
> --- /dev/null
> +++ b/arch/arm64/include/asm/atomic.h
> @@ -0,0 +1,306 @@
> +/*
> + * Based on arch/arm/include/asm/atomic.h
> + *
> + * Copyright (C) 1996 Russell King.
> + * Copyright (C) 2002 Deep Blue Solutions Ltd.
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_ATOMIC_H
> +#define __ASM_ATOMIC_H
> +
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +
> +#include <asm/barrier.h>
> +#include <asm/cmpxchg.h>
> +
> +#define ATOMIC_INIT(i)	{ (i) }
> +
> +#ifdef __KERNEL__
> +
> +/*
> + * On ARM, ordinary assignment (str instruction) doesn't clear the local
> + * strex/ldrex monitor on some implementations. The reason we can use it for
> + * atomic_set() is the clrex or dummy strex done on every exception return.
> + */
> +#define atomic_read(v)	(*(volatile int *)&(v)->counter)
> +#define atomic_set(v,i)	(((v)->counter) = (i))
> +
> +/*
> + * AArch64 UP and SMP safe atomic ops.  We use load exclusive and
> + * store exclusive to ensure that these are atomic.  We may loop
> + * to ensure that the update happens.
> + */
> +static inline void atomic_add(int i, atomic_t *v)
> +{
> +	unsigned long tmp;
> +	int result;
> +
> +	asm volatile("// atomic_add\n"
> +"1:	ldxr	%w0, [%3]\n"
> +"	add	%w0, %w0, %w4\n"
> +"	stxr	%w1, %w0, [%3]\n"
> +"	cbnz	%w1,1b"

Nit: space before 1b

[...]

> diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
> new file mode 100644
> index 0000000..0745e82
> --- /dev/null
> +++ b/arch/arm64/include/asm/futex.h
> @@ -0,0 +1,134 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_FUTEX_H
> +#define __ASM_FUTEX_H
> +
> +#ifdef __KERNEL__
> +
> +#include <linux/futex.h>
> +#include <linux/uaccess.h>
> +#include <asm/errno.h>
> +
> +#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg)		\
> +	asm volatile(							\
> +"1:	ldaxr	%w1, %2\n"						\
> +	insn "\n"							\
> +"2:	stlxr	%w3, %w0, %2\n"						\
> +"	cbnz	%w3, 1b\n"						\
> +"3:	.pushsection __ex_table,\"a\"\n"				\
> +"	.align	3\n"							\
> +"	.quad	1b, 4f, 2b, 4f\n"					\
> +"	.popsection\n"							\
> +"	.pushsection .fixup,\"ax\"\n"					\

Moving the exception table below the body of the code makes the flow easier to
read, please do that.

Also, don't you need a barrier here?

> +"4:	mov	%w0, %w5\n"						\
> +"	b	3b\n"							\
> +"	.popsection"							\
> +	: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)	\
> +	: "r" (oparg), "Ir" (-EFAULT)					\
> +	: "cc")
> +
> +static inline int
> +futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
> +{
> +	int op = (encoded_op >> 28) & 7;
> +	int cmp = (encoded_op >> 24) & 15;
> +	int oparg = (encoded_op << 8) >> 20;
> +	int cmparg = (encoded_op << 20) >> 20;
> +	int oldval = 0, ret, tmp;
> +
> +	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
> +		oparg = 1 << oparg;
> +
> +	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
> +		return -EFAULT;
> +
> +	pagefault_disable();	/* implies preempt_disable() */
> +
> +	switch (op) {
> +	case FUTEX_OP_SET:
> +		__futex_atomic_op("mov	%w0, %w4",
> +				  ret, oldval, uaddr, tmp, oparg);
> +		break;
> +	case FUTEX_OP_ADD:
> +		__futex_atomic_op("add	%w0, %w1, %w4",
> +				  ret, oldval, uaddr, tmp, oparg);
> +		break;
> +	case FUTEX_OP_OR:
> +		__futex_atomic_op("orr	%w0, %w1, %w4",
> +				  ret, oldval, uaddr, tmp, oparg);
> +		break;
> +	case FUTEX_OP_ANDN:
> +		__futex_atomic_op("and	%w0, %w1, %w4",
> +				  ret, oldval, uaddr, tmp, ~oparg);
> +		break;
> +	case FUTEX_OP_XOR:
> +		__futex_atomic_op("eor	%w0, %w1, %w4",
> +				  ret, oldval, uaddr, tmp, oparg);
> +		break;
> +	default:
> +		ret = -ENOSYS;
> +	}
> +
> +	pagefault_enable();	/* subsumes preempt_enable() */
> +
> +	if (!ret) {
> +		switch (cmp) {
> +		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
> +		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
> +		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
> +		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
> +		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
> +		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
> +		default: ret = -ENOSYS;
> +		}
> +	}
> +	return ret;
> +}
> +
> +static inline int
> +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
> +			      u32 oldval, u32 newval)
> +{
> +	int ret = 0;
> +	u32 val, tmp;
> +
> +	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
> +		return -EFAULT;
> +
> +	asm volatile("// futex_atomic_cmpxchg_inatomic\n"
> +"1:	ldaxr	%w1, %2\n"
> +"	sub	%w3, %w1, %w4\n"
> +"	cbnz	%w3, 3f\n"
> +"2:	stlxr	%w3, %w5, %2\n"
> +"	cbnz	%w3, 1b\n"
> +"3:	.pushsection __ex_table,\"a\"\n"
> +"	.align	3\n"
> +"	.quad	1b, 4f, 2b, 4f\n"
> +"	.popsection\n"
> +"	.pushsection .fixup,\"ax\"\n"

Same here w.r.t. exception table location and barrier.

> +"4:	mov	%w0, %w6\n"
> +"	b	3b\n"
> +"	.popsection"
> +	: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
> +	: "r" (oldval), "r" (newval), "Ir" (-EFAULT)
> +	: "cc", "memory");
> +
> +	*uval = val;
> +	return ret;
> +}
> +
> +#endif /* __KERNEL__ */
> +#endif /* __ASM_FUTEX_H */


-Olof


From aaro.koskinen at iki.fi  Tue Aug 14 20:25:36 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed, 15 Aug 2012 03:25:36 +0300
Subject: Potential Regression in 3.6-rc1 - Kirkwood SATA
In-Reply-To: <CAMW5UfZ_kVz_b4_98zPdY2RFjTMN9H2OzjYcRQrCTgA1xqdmPw@mail.gmail.com>
References: <CAMW5UfZ_kVz_b4_98zPdY2RFjTMN9H2OzjYcRQrCTgA1xqdmPw@mail.gmail.com>
Message-ID: <20120815002536.GC747@harshnoise.musicnaut.iki.fi>

Him

On Tue, Aug 14, 2012 at 07:59:00PM -0400, Josh Coombs wrote:
> I finally got a chance to test 3.6-rc1 after having my GoFlex Net
> support patch accepted for the 3.6 release train.  Included in 3.6-rc1
> was an update for Kirkwoods switching SATA to DT which was not part of
> my original testing.  It seems something with this change has
> partially broken the GoFlex and a couple other Kirkwood based devices.
> 
> The key factor is the number of SATA ports defined in the dts:
> 
> 		sata at 80000 {
> 			status = "okay";
> 			nr-ports = <2>;
> 		};
> 
> If set at the correct number for my device, 2, my GFN does not
> complete kernel init, hanging here:
> 
> <SNIP>
> [   15.287832] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
> [   15.296545] jffs2: version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
> [   15.303202] msgmni has been set to 240
> [   15.308503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major )
> [   15.316021] io scheduler noop registered
> [   15.320149] io scheduler deadline registered
> [   15.324558] io scheduler cfq registered (default)
> [   15.329462] mv_xor_shared mv_xor_shared.0: Marvell shared XOR driver
> [   15.335962] mv_xor_shared mv_xor_shared.1: Marvell shared XOR driver
> [   15.376751] mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
> [   15.416736] mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )
> [   15.456735] mv_xor mv_xor.2: Marvell XOR: ( xor cpy )
> [   15.496734] mv_xor mv_xor.3: Marvell XOR: ( xor fill cpy )
> [   15.506309] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> [   15.509111] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
> [   15.509141] console [ttyS0] enabled, bootconsole disabled
> [   15.518967] brd: module loaded
> [   15.524991] loop: module loaded
> [   15.528584] sata_mv sata_mv.0: cannot get optional clkdev
> [   15.534180] sata_mv sata_mv.0: slots 32 ports 2
> 
> If you set nr-ports to 1 the unit boots cleanly, save for only
> detecting one functional SATA port.  Another user has confirmed this
> behavior on an Iomega IX2-200.

Try booting with "coherent_pool=1M" (or bigger) kernel parameter. I think
with the recent DMA mapping changes, the default 256 KB coherent pool may
be too small, mv_xor and sata_mv together needs more. (I'm not sure how
it actually worked before commit e9da6e9905e639b0f842a244bc770b48ad0523e9,
but it seems this is the cuase).

It should be noted that dma_pool_alloc() uses GFP_ATOMIC always, and if
drivers exhaust the coherent pool already during the boot that function
just keeps looping forever. Users only see boot hanging with no clue
what to do. I would say it's quite a poor error handling...

A.


From olof at lixom.net  Tue Aug 14 20:33:55 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 17:33:55 -0700
Subject: [PATCH v2 13/31] arm64: Device specific operations
In-Reply-To: <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120815003355.GF19607@quad.lixom.net>

On Tue, Aug 14, 2012 at 06:52:14PM +0100, Catalin Marinas wrote:
> This patch adds several definitions for device communication, including
> I/O accessors and ioremap(). The __raw_* accessors are implemented as
> inline asm to avoid compiler generation of post-indexed accesses (less
> efficient to emulate in a virtualised environment).
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> ---
>  arch/arm64/include/asm/device.h |   26 ++++
>  arch/arm64/include/asm/fb.h     |   34 +++++
>  arch/arm64/include/asm/io.h     |  263 +++++++++++++++++++++++++++++++++++++++
>  arch/arm64/kernel/io.c          |   64 ++++++++++
>  arch/arm64/mm/ioremap.c         |   84 +++++++++++++
>  5 files changed, 471 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm64/include/asm/device.h
>  create mode 100644 arch/arm64/include/asm/fb.h
>  create mode 100644 arch/arm64/include/asm/io.h
>  create mode 100644 arch/arm64/kernel/io.c
>  create mode 100644 arch/arm64/mm/ioremap.c
> 
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> new file mode 100644
> index 0000000..48fa83f
> --- /dev/null
> +++ b/arch/arm64/include/asm/io.h

[...]

> +/*
> + *  I/O port access primitives.
> + */
> +#define IO_SPACE_LIMIT		0xffff
> +
> +/*
> + * We currently don't have any platform with PCI support, so just leave this
> + * defined to 0 until needed.
> + */
> +#define PCI_IOBASE		((void __iomem *)0)

You could just leave out the PCI / I/O code alltogether instead.

> diff --git a/arch/arm64/kernel/io.c b/arch/arm64/kernel/io.c
> new file mode 100644
> index 0000000..7d37ead
> --- /dev/null
> +++ b/arch/arm64/kernel/io.c
> @@ -0,0 +1,64 @@
> +/*
> + * Based on arch/arm/kernel/io.c
> + *
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/export.h>
> +#include <linux/types.h>
> +#include <linux/io.h>
> +
> +/*
> + * Copy data from IO memory space to "real" memory space.
> + */
> +void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
> +{
> +	unsigned char *t = to;
> +	while (count) {
> +		count--;
> +		*t = readb(from);
> +		t++;
> +		from++;
> +	}
> +}
> +EXPORT_SYMBOL(__memcpy_fromio);
> +
> +/*
> + * Copy data from "real" memory space to IO memory space.
> + */
> +void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
> +{
> +	const unsigned char *f = from;
> +	while (count) {
> +		count--;
> +		writeb(*f, to);
> +		f++;
> +		to++;
> +	}
> +}
> +EXPORT_SYMBOL(__memcpy_toio);
> +
> +/*
> + * "memset" on IO memory space.
> + */
> +void __memset_io(volatile void __iomem *dst, int c, size_t count)
> +{
> +	while (count) {
> +		count--;
> +		writeb(c, dst);
> +		dst++;
> +	}
> +}
> +EXPORT_SYMBOL(__memset_io);

Doing all of the above a byte at a time is horribly inefficient. Feel
free to borrow the implementations from arch/powerpc/kernel/io.c instead
of from ARM.


-Olof


From olof at lixom.net  Tue Aug 14 20:40:06 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 17:40:06 -0700
Subject: [PATCH v2 14/31] arm64: DMA mapping API
In-Reply-To: <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120815004006.GG19607@quad.lixom.net>

Hi,


On Tue, Aug 14, 2012 at 06:52:15PM +0100, Catalin Marinas wrote:
> This patch adds support for the DMA mapping API. It uses dma_map_ops for
> flexibility and it currently supports swiotlb. This patch could be
> simplified further if the DMA accesses are coherent (not mandated by the
> architecture) or if corresponding hooks are placed in the generic
> swiotlb code to deal with cache maintenance.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> ---
>  arch/arm64/include/asm/dma-mapping.h |  124 ++++++++++++++++++++
>  arch/arm64/mm/dma-mapping.c          |  208 ++++++++++++++++++++++++++++++++++
>  2 files changed, 332 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm64/include/asm/dma-mapping.h
>  create mode 100644 arch/arm64/mm/dma-mapping.c
> 
> diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
> new file mode 100644
> index 0000000..538f4b4
> --- /dev/null
> +++ b/arch/arm64/include/asm/dma-mapping.h
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_DMA_MAPPING_H
> +#define __ASM_DMA_MAPPING_H
> +
> +#ifdef __KERNEL__
> +
> +#include <linux/types.h>
> +#include <linux/vmalloc.h>
> +
> +#include <asm-generic/dma-coherent.h>
> +
> +#define ARCH_HAS_DMA_GET_REQUIRED_MASK
> +
> +extern struct dma_map_ops *dma_ops;
> 
> +static inline struct dma_map_ops *get_dma_ops(struct device *dev)
> +{
> +	if (unlikely(!dev) || !dev->archdata.dma_ops)
> +		return dma_ops;
> +	else
> +		return dev->archdata.dma_ops;
> +}

Does it make sense to add the concept of a global dma ops on arm64,
instead of requiring the dma ops pointer per device similar to how
some other platforms do it (including powerpc)? For devices that lack
archdata.dma_ops, dma_supported() should return 0 (and the other ops
should return error).



-Olof


From josh.coombs at gmail.com  Tue Aug 14 20:47:32 2012
From: josh.coombs at gmail.com (Josh Coombs)
Date: Tue, 14 Aug 2012 20:47:32 -0400
Subject: Potential Regression in 3.6-rc1 - Kirkwood SATA
In-Reply-To: <20120815002536.GC747@harshnoise.musicnaut.iki.fi>
References: <CAMW5UfZ_kVz_b4_98zPdY2RFjTMN9H2OzjYcRQrCTgA1xqdmPw@mail.gmail.com>
 <20120815002536.GC747@harshnoise.musicnaut.iki.fi>
Message-ID: <CAMW5Ufa8YwhVbCtQwswVBi8VXiTDWFPz9Kfj3NYxF7VrWz5t=w@mail.gmail.com>

On Tue, Aug 14, 2012 at 8:25 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> Him
>
> On Tue, Aug 14, 2012 at 07:59:00PM -0400, Josh Coombs wrote:
>> I finally got a chance to test 3.6-rc1 after having my GoFlex Net
>> support patch accepted for the 3.6 release train.  Included in 3.6-rc1
>> was an update for Kirkwoods switching SATA to DT which was not part of
>> my original testing.  It seems something with this change has
>> partially broken the GoFlex and a couple other Kirkwood based devices.
>>
>> The key factor is the number of SATA ports defined in the dts:
>>
>>               sata at 80000 {
>>                       status = "okay";
>>                       nr-ports = <2>;
>>               };
>>
>> If set at the correct number for my device, 2, my GFN does not
>> complete kernel init, hanging here:
>>
>> <SNIP>
>> [   15.287832] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
>> [   15.296545] jffs2: version 2.2. (NAND) ?? 2001-2006 Red Hat, Inc.
>> [   15.303202] msgmni has been set to 240
>> [   15.308503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major )
>> [   15.316021] io scheduler noop registered
>> [   15.320149] io scheduler deadline registered
>> [   15.324558] io scheduler cfq registered (default)
>> [   15.329462] mv_xor_shared mv_xor_shared.0: Marvell shared XOR driver
>> [   15.335962] mv_xor_shared mv_xor_shared.1: Marvell shared XOR driver
>> [   15.376751] mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
>> [   15.416736] mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )
>> [   15.456735] mv_xor mv_xor.2: Marvell XOR: ( xor cpy )
>> [   15.496734] mv_xor mv_xor.3: Marvell XOR: ( xor fill cpy )
>> [   15.506309] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
>> [   15.509111] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
>> [   15.509141] console [ttyS0] enabled, bootconsole disabled
>> [   15.518967] brd: module loaded
>> [   15.524991] loop: module loaded
>> [   15.528584] sata_mv sata_mv.0: cannot get optional clkdev
>> [   15.534180] sata_mv sata_mv.0: slots 32 ports 2
>>
>> If you set nr-ports to 1 the unit boots cleanly, save for only
>> detecting one functional SATA port.  Another user has confirmed this
>> behavior on an Iomega IX2-200.
>
> Try booting with "coherent_pool=1M" (or bigger) kernel parameter. I think
> with the recent DMA mapping changes, the default 256 KB coherent pool may
> be too small, mv_xor and sata_mv together needs more. (I'm not sure how
> it actually worked before commit e9da6e9905e639b0f842a244bc770b48ad0523e9,
> but it seems this is the cuase).
>
> It should be noted that dma_pool_alloc() uses GFP_ATOMIC always, and if
> drivers exhaust the coherent pool already during the boot that function
> just keeps looping forever. Users only see boot hanging with no clue
> what to do. I would say it's quite a poor error handling...
>
> A.

I can confirm that fixes my GoFlex.  Would this justify raising the
default for Kirkwoods, or just for specific devices within the family?

Josh C


From olof at lixom.net  Tue Aug 14 20:49:14 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 14 Aug 2012 17:49:14 -0700
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120815004914.GH19607@quad.lixom.net>

Hi,

On Tue, Aug 14, 2012 at 06:52:16PM +0100, Catalin Marinas wrote:
> This patch adds SMP initialisation and spinlocks implementation for
> AArch64. The spinlock support uses the new load-acquire/store-release
> instructions to avoid explicit barriers. The architecture also specifies
> that an event is automatically generated when clearing the exclusive
> monitor state to wake up processors in WFE, so there is no need for an
> explicit DSB/SEV instruction sequence. The SEVL instruction is used to
> set the exclusive monitor locally as there is no conditional WFE and a
> branch is more expensive.
> 
> For the SMP booting protocol, see Documentation/arm64/booting.txt.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> ---

> diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
> new file mode 100644
> index 0000000..34a37fb
> --- /dev/null
> +++ b/arch/arm64/include/asm/spinlock.h
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_SPINLOCK_H
> +#define __ASM_SPINLOCK_H
> +
> +#include <asm/spinlock_types.h>
> +#include <asm/processor.h>
> +
> +/*
> + * AArch64 Spin-locking.
> + *
> + * We exclusively read the old value.  If it is zero, we may have
> + * won the lock, so we try exclusively storing it.  A memory barrier
> + * is required after we get a lock, and before we release it, because
> + * V6 CPUs are assumed to have weakly ordered memory.

This comment should be updated, to mention the implicit locking and remove the
reference to V6?

Also, ignore previous questions on another reply about need for barriers,
obviously not needed given the load-acquire/store-release semantics.



-Olof


From dong.aisheng at linaro.org  Tue Aug 14 23:59:18 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Wed, 15 Aug 2012 11:59:18 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
Message-ID: <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>

On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
> On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
>> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
>>> I have a minor nit; while renumbering the pinctrl definitions is
>>> laudable and device trees can match, there are 16 other pin controls
>>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
>>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
>>> (pin_id*4)).
>>
>> What do you mean of this value calculated?
>
> Well, it just seems the datasheet has been read from the point of view
> of the SW_CTRL settings (pad pullups, drive strength etc.) to define
> the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
> I mistyped) has been entered as an enum into this list. Then a table
> has been generated using these enums to supply a pin id. Then this pin
> id is not relevant anymore; it actually gets referenced by it's
> *offset into the table*.
>
Not exactly, probably.
Basically we follow the mux reigster offset to define pin id, however,
there're also some pads may not have mux function but only config
which also has a pin id
and vice versa.
Those pins are not ordered by it's mux regsiter offset.

Actually I did not manually search all those pins, instead, i just
using the exist ones:
arch/arm/plat-mxc/include/mach/iomux-mx51.h
Since this exist headfile already covers this case.

> In this case, basically the code misses a few pins which have ALT
> settings but perhaps not always the ability to change pad control -
> EIM_DA5 to 15 are a good example.
>
As i said, we already defined those pin ids.

> Probably better would be to define the binding almost exactly as it
> was done in the old method; iomux_v3_cfg_t took into account the three
> register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
> and the three values to be put into those registers.
>
> This has been reduced down in pinctrl to what I find quite strange,
> which is a completely arbitrary pin "id" mapping, which indirectly
> references an entry in a table by index which is why pin 1 as a start
> looks odd.
>
Start with pin 1 is a bug which caused by my mistake during the early
data conversion.

> If the binding is entirely i.MX-specific or even i.MX51-specific then
> why not define the pins in the device tree the "old" iomux_v3_cfg_t
> way, which is the way they are in the table of imx_pin_regs;
>
>       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
> MX51_PAD_EIM_D16__AUD4_RXFS */
>
> 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
> 0x000 is the IPP reg, and 0 the IPP value.
>
> So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
> mode/sion, IPP, select - in that order) would be a valid pin
> definition and require no table. Sure, the offsets are device specific
> but then the arbitrary numbering is too.
> This way old iomux controls
> can be re-derived for people who use the old method in old kernels, or
> use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
> porting the Efika to it on MX5 for U-Boot right now). Also that huge
> table goes away - it can be built at runtime, along with the
> PAD_NAME__ALT_MODE_NAME description.
>
I can't agree this is better than the exist one now.
It's hard to use in device tree.
And how would you parse the pin id from this data array?

If really in that way, i feel like it's pure register write and does not require
any subsystem or driver.

> It would also remove any arbitrary indexes, and allow lookup based on
> an actual documented value (which is listed at the top of every page
> of Appendix A register definitions), cross-referencing with the manual
> on the actual register settings etc.  It is certainly less confusing
> than <0 0x17058> or so, which says nothing without a comment, and the
> value listed is entirely arbitrary encoding of the PAD_CTL values.
>
> For a different way of explaining and another example of what is
> wrong, in the current binding doc for example;
>
>         1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
>
> 1386 is a pin index, correct? But it's a pin index into the
No, like every device else, you should refer to the binding doc for the detailed
binding details rather than assuming ourselves.

> imx_pin_regs array. It has no relation to the enums at the top of
> pinctrl-imx6q.c, which is only used to refer to the pin_desc
> structure.
>
>         IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0),
> /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
>
> So the enums at the top of the file don't even define the pin number.
> You have to COUNT inside this file, or look at the binding which
> someone has written by doing the counting by hand or script.
They're different things.
The enum imx51_pads is the pin id definitions.
The 'MX6Q_PAD_SD4_CMD__USDHC4_CMD' is the pin func id definition.
See binding doc: fsl,mxs-pinctrl.txt

> Change
> the array, change the binding. This is terrible, terrible design.
No, the binding is driver independant.
The array you said here is implementation and should not affect binding.

> There should be one point of reference, and if possible, the binding
> should be totally obvious without cross-reference.
I agree.
Can you point out the exist one?

>
> The docs then say 0x17059 defines the pin control settings (hysteresis
> etc.) - MUX_MODE (ALT) is inferred from this database inside the
> kernel.
>
> If you need to add more items in the list (for instance if MX7 gains
> an extra set of configuration registers for each pin), this is what
> #size-cells property is for in the device tree, or better yet why not
> walk the tree to find the machine compatible?
>
>> What trouble do you mean?
>> Those pins, EIM_DA*, are already defined but just on a different pin id.
>> Can't user use it in this way?
>
> Yuck.
>
>>> Therefore I propose;
>>>
>>> * add MX51_PAD_EIM_DA0 through DA15 as index 0-15 (same for any
>>> differences in other i.MX etc.)
>> Hmm, as i said above, those pins are already defined.
>> See:
>>         MX51_PAD_SD1_DATA0 = 209,
>>         MX51_PAD_EIM_DA0 = 210,
>>         MX51_PAD_EIM_DA1 = 211,
>>         MX51_PAD_EIM_DA2 = 212,
>>         MX51_PAD_EIM_DA3 = 213,
>
> Where are 4 through 15?
>
b29396 at shlinux2:~/upstream/linux-2.6-linus-imx$ grep -rn
MX51_PAD_EIM_DA drivers/pinctrl/pinctrl-imx51.c
235:    MX51_PAD_EIM_DA0 = 210,
236:    MX51_PAD_EIM_DA1 = 211,
237:    MX51_PAD_EIM_DA2 = 212,
238:    MX51_PAD_EIM_DA3 = 213,
240:    MX51_PAD_EIM_DA4 = 215,
241:    MX51_PAD_EIM_DA5 = 216,
242:    MX51_PAD_EIM_DA6 = 217,
243:    MX51_PAD_EIM_DA7 = 218,
245:    MX51_PAD_EIM_DA10 = 220,
246:    MX51_PAD_EIM_DA11 = 221,
247:    MX51_PAD_EIM_DA8 = 222,
248:    MX51_PAD_EIM_DA9 = 223,
252:    MX51_PAD_EIM_DA12 = 227,
253:    MX51_PAD_EIM_DA13 = 228,
254:    MX51_PAD_EIM_DA14 = 229,
255:    MX51_PAD_EIM_DA15 = 230,

>> I did not quite understand, remove other pin ids up by 16? why?
>
> See above.
>
>> Why we may want to change the definitions again?
>
> If you got ANYTHING at all wrong. Shawn already sent a patch to change
> a definition. What if the order in the table changes? Where is the
> note above the table that says the order of the table is tied directly
> to the binding and no order changes or inserts-in-the-middle should be
> made?
>
I think the binding imx pinctrl used is not pin id dependent since it
only tells the
pin func id(which hw pin used in which function, pin id is linux abstract),
how to define the pin id or how to parse the pin id from pin func id
is driver specific.
That means you can define pin id in a arbitrary number as you want.
Anyway, i could double check it later.

>> Since we already have those pins EIM_DA* defined, it looks to me user could use
>
> No.. because there are 12 pins missing. I don't know how many others
> might be missing,
Can you point out the exact missing pins you found?

> but the implementation as a whole is too arbitrary
> and too abstract. You do not need to implement indirection in the
> device tree.
>
I just chose a better way to use.
Current i did not see any big issue, anyway, i will think a bit more according
to your comments.

Regards
Dong Aisheng


From dong.aisheng at linaro.org  Wed Aug 15 00:00:42 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Wed, 15 Aug 2012 12:00:42 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <502A9476.1040500@boundarydevices.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <502954D2.908@boundarydevices.com>
 <CAP1dx+wm=Lj6WXWTiRk3JfqAomr8_mfjZpmToht2bb4paEYXjQ@mail.gmail.com>
 <502A9476.1040500@boundarydevices.com>
Message-ID: <CAP1dx+xGbnnU-+uQ7BPpzXEgpE50_xC9v8ZsmkfmxDmqC168Bg@mail.gmail.com>

On 15 August 2012 02:09, Troy Kisky <troy.kisky at boundarydevices.com> wrote:
> On 8/14/2012 12:30 AM, Dong Aisheng wrote:
>>
>> On 14 August 2012 03:26, Troy Kisky <troy.kisky at boundarydevices.com>
>> wrote:
>>>
>>> On 8/13/2012 7:47 AM, Shawn Guo wrote:
>>>>
>>>> Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5
>>>> pinctrl drivers number pad from 1.  It causes problem/confusion when
>>>> driver accesses imx51_pinctrl_pads array using pin ID as the index.
>>>>
>>>> Change imx51_pads and imx53_pads numbering start from 0.
>>>>
>>>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>>>> ---
>>>>    drivers/pinctrl/pinctrl-imx51.c |  490
>>>> +++++++++++++++++++-------------------
>>>>    drivers/pinctrl/pinctrl-imx53.c |  402
>>>> ++++++++++++++++----------------
>>>>    2 files changed, 446 insertions(+), 446 deletions(-)
>>>>
>>>> diff --git a/drivers/pinctrl/pinctrl-imx51.c
>>>> b/drivers/pinctrl/pinctrl-imx51.c
>>>> index 9fd0216..fb84689 100644
>>>> --- a/drivers/pinctrl/pinctrl-imx51.c
>>>> +++ b/drivers/pinctrl/pinctrl-imx51.c
>>>> @@ -23,251 +23,251 @@
>>>>    #include "pinctrl-imx.h"
>>>>      enum imx51_pads {
>>>> -       MX51_PAD_EIM_D16 = 1,
>>>> -       MX51_PAD_EIM_D17 = 2,
>>
>> ...
>>>>
>>>> +       MX53_PAD_GPIO_19 = 0,
>>>> +       MX53_PAD_KEY_COL0 = 1,
>>>
>>>
>>> Why not skip the = xx altogether??  The enum will auto-increment.
>>
>> Personally i'd like to keep it.
>> The reason is that pin id is basic property of a pin per pinctrl
>> subsystem's design
>> so explicitly define it looks more clear to me and i'm not sure but
>> it's possible that
>> the pin id may be used in device tree in the future(maybe some other
>> soc already uses it),
>> And defining it has no big harming.
>>
>> Regards
>> Dong Aisheng
>> .
>>
> Then maybe #defines should be used, so that device tree can include this
> file and be run through C pre-processor?
>
Maybe one day device tree supports include c headfile,
we can do like that.

Regards
Dong Aisheng


From u.kleine-koenig at pengutronix.de  Wed Aug 15 01:44:36 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 15 Aug 2012 07:44:36 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
Message-ID: <20120815054436.GK2232@pengutronix.de>

Hello,

(Cc += devicetree-discuss at lists.ozlabs.org)

On Wed, Aug 15, 2012 at 11:59:18AM +0800, Dong Aisheng wrote:
> On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
> > On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
> >> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
> >>> I have a minor nit; while renumbering the pinctrl definitions is
> >>> laudable and device trees can match, there are 16 other pin controls
> >>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
> >>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
> >>> (pin_id*4)).
> >>
> >> What do you mean of this value calculated?
> >
> > Well, it just seems the datasheet has been read from the point of view
> > of the SW_CTRL settings (pad pullups, drive strength etc.) to define
> > the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
> > I mistyped) has been entered as an enum into this list. Then a table
> > has been generated using these enums to supply a pin id. Then this pin
> > id is not relevant anymore; it actually gets referenced by it's
> > *offset into the table*.
> >
> Not exactly, probably.
> Basically we follow the mux reigster offset to define pin id, however,
> there're also some pads may not have mux function but only config
> which also has a pin id
> and vice versa.
> Those pins are not ordered by it's mux regsiter offset.
> 
> Actually I did not manually search all those pins, instead, i just
> using the exist ones:
> arch/arm/plat-mxc/include/mach/iomux-mx51.h
> Since this exist headfile already covers this case.
> 
> > In this case, basically the code misses a few pins which have ALT
> > settings but perhaps not always the ability to change pad control -
> > EIM_DA5 to 15 are a good example.
> >
> As i said, we already defined those pin ids.
> 
> > Probably better would be to define the binding almost exactly as it
> > was done in the old method; iomux_v3_cfg_t took into account the three
> > register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
> > and the three values to be put into those registers.
> >
> > This has been reduced down in pinctrl to what I find quite strange,
> > which is a completely arbitrary pin "id" mapping, which indirectly
> > references an entry in a table by index which is why pin 1 as a start
> > looks odd.
> >
> Start with pin 1 is a bug which caused by my mistake during the early
> data conversion.
> 
> > If the binding is entirely i.MX-specific or even i.MX51-specific then
> > why not define the pins in the device tree the "old" iomux_v3_cfg_t
> > way, which is the way they are in the table of imx_pin_regs;
> >
> >       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
> > MX51_PAD_EIM_D16__AUD4_RXFS */
> >
> > 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
> > 0x000 is the IPP reg, and 0 the IPP value.
> >
> > So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
> > mode/sion, IPP, select - in that order) would be a valid pin
> > definition and require no table. Sure, the offsets are device specific
> > but then the arbitrary numbering is too.
> > This way old iomux controls
> > can be re-derived for people who use the old method in old kernels, or
> > use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
> > porting the Efika to it on MX5 for U-Boot right now). Also that huge
> > table goes away - it can be built at runtime, along with the
> > PAD_NAME__ALT_MODE_NAME description.
> >
> I can't agree this is better than the exist one now.
> It's hard to use in device tree.
> And how would you parse the pin id from this data array?
I admit I didn't follow completely the calculation suggestion by Matt,
but I think in general he has a point. This is more or less what I
thought when I built the imx35 pinctrl driver.

With the current approach (i.e. put the pinfuncs in some order that
seems sensible today and then referencing them by index according to
that ordering) you really get into troubles if you have to add a new
function. You have to add it to the end to not break existing device
trees and so the ordering is broken.

Also "11" has no obvious relation to MX35_PAD_COMPARE__SDMA_EXTDMA_2
other than a match if you grep over the binding docs (or the driver).
While "0x32c, 0x008, 7, 0x0, 0" is longer and looks more ugly the
mapping is obvious and so IMHO preferable.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From balbi at ti.com  Wed Aug 15 02:03:13 2012
From: balbi at ti.com (Felipe Balbi)
Date: Wed, 15 Aug 2012 09:03:13 +0300
Subject: [PATCHv6 24/24] i2c: omap: Prevent NULL pointer dereference in
 remove
In-Reply-To: <1344953946-13005-25-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
 <1344953946-13005-25-git-send-email-shubhrajyoti@ti.com>
Message-ID: <20120815060312.GE23637@arwen.pp.htv.fi>

On Tue, Aug 14, 2012 at 07:49:06PM +0530, Shubhrajyoti D wrote:
> Prevent the NULL pointer access by moving the platform_set_drvdata function
> after the access of the pdev.
> 
> [  654.961761] Unable to handle kernel NULL pointer dereference at virtual address 00000070
> [  654.970611] pgd = df254000
> [  654.973480] [00000070] *pgd=9f1da831, *pte=00000000, *ppte=00000000
> [  654.980163] Internal error: Oops: 17 [#1] SMP ARM
> [  654.985076] Modules linked in:
> [  654.988281] CPU: 1    Not tainted  (3.6.0-rc1-00031-ge547de1-dirty #339)
> [  654.995330] PC is at omap_i2c_runtime_resume+0x8/0x148
> [  655.000732] LR is at omap_i2c_runtime_resume+0x8/0x148
> 
> Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> ---
>  drivers/i2c/busses/i2c-omap.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 3df6f92..49dbff1 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -1217,8 +1217,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
>  	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
>  	int ret;
>  
> -	platform_set_drvdata(pdev, NULL);
> -
>  	i2c_del_adapter(&dev->adapter);
>  	ret = pm_runtime_get_sync(&pdev->dev);
>  	if (IS_ERR_VALUE(ret))
> @@ -1227,6 +1225,8 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
>  	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
>  	pm_runtime_put(&pdev->dev);
>  	pm_runtime_disable(&pdev->dev);
> +	platform_set_drvdata(pdev, NULL);

in fact this platform_set_drvdata(pdev, NULL) can be removed. The
platform_device object will be destroyed anyway.

-- 
balbi
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From thierry.reding at avionic-design.de  Wed Aug 15 02:37:18 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 08:37:18 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
Message-ID: <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>

On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> >> index a094c97..c886dff 100644
> >> --- a/arch/arm/boot/dts/tegra20.dtsi
> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
> >> @@ -199,6 +199,68 @@
> >>               #size-cells = <0>;
> >>       };
> >>
> >> +     pcie-controller {
> >> +             compatible = "nvidia,tegra20-pcie";
> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
> >> +                    0x80003800 0x00000200   /* AFI registers */
> >> +                    0x81000000 0x01000000   /* configuration space */
> >> +                    0x90000000 0x10000000>; /* extended configuration space */
> >> +             interrupts = <0 98 0x04   /* controller interrupt */
> >> +                           0 99 0x04>; /* MSI interrupt */
> >> +             status = "disabled";
> >> +
> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
> >> +
> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
> >
> > I've been thinking about this some more. The translations for both the
> > regular and extended configuration spaces are configured in the top-
> > level PCIe controller. It is therefore wrong how they are passed to the
> > PCI host bridges via the ranges property.
> >
> > I remember Mitch saying that it should be passed down to the children
> > because it is partitioned among them, but since the layout is compatible
> > with ECAM, the partitioning isn't as simple as what's in the tree. In
> > fact the partitions will be dependent on the number of devices attached
> > to the host bridges.
> 
> I don't understand this last bit about the number of devices attached
> to the host bridges.  Logically, the host bridge has a bus number
> aperture that you can know up front, even before you know anything
> about what devices are below it.  On x86, for example, the ACPI _CRS
> method has something like "[bus 00-7f]" in it, which means that any
> buses in that range are below this bridge.  That doesn't tell us
> anything about which buses actually have devices on them, of course;
> it's just analogous to the secondary and subordinate bus number
> registers in a P2P bridge.

That's one of the issues I still need to take care of. Currently no bus
resource is attached to the individual bridges (nor the PCI controller
for that matter), so the PCI core will assign them dynamically. If this
range is known at boot time we could assign ECAM ranges based on the bus
numbers. Standard ECAM ranges, that is. On Tegra this won't work because
as Stephen mentioned in a previous mail, the bus field is not the top
field in the ECAM addresses. Basically what you have is this:

	[27:24] upper 4 bits of the register address for extended
	        configuration space
	[23:16] bus number
	[15:11] device number
	[10: 8] device function
	[ 8: 0] register

So the ECAM space cannot be partitioned by bus number.

Thierry
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From thierry.reding at avionic-design.de  Wed Aug 15 02:49:02 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 08:49:02 +0200
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <CAErSpo4Efy-Dt67rktzNiYfZfOTSu=pmYtyGd3tR-zZQ3jDGtA@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
 <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Efy-Dt67rktzNiYfZfOTSu=pmYtyGd3tR-zZQ3jDGtA@mail.gmail.com>
Message-ID: <20120815064902.GB15665@avionic-0098.mockup.avionic-design.de>

On Tue, Aug 14, 2012 at 02:44:24PM -0700, Bjorn Helgaas wrote:
> On Tue, Aug 14, 2012 at 11:01 AM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Tue, Aug 14, 2012 at 10:38:08AM -0700, Bjorn Helgaas wrote:
> >> On Mon, Aug 13, 2012 at 10:55 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > On Mon, Aug 13, 2012 at 10:00:45PM -0700, Bjorn Helgaas wrote:
> >> >> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> >> >> <thierry.reding at avionic-design.de> wrote:
> >> >> > This commit adds a new flag that allows marking resources as PCI
> >> >> > configuration space.
> >> >> >
> >> >> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> >> >> > ---
> >> >> > Changes in v3:
> >> >> > - new patch
> >> >> >
> >> >> >  include/linux/ioport.h | 2 +-
> >> >> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >> >> >
> >> >> > diff --git a/include/linux/ioport.h b/include/linux/ioport.h
> >> >> > index 589e0e7..3314843 100644
> >> >> > --- a/include/linux/ioport.h
> >> >> > +++ b/include/linux/ioport.h
> >> >> > @@ -102,7 +102,7 @@ struct resource {
> >> >> >
> >> >> >  /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
> >> >> >  #define IORESOURCE_PCI_FIXED           (1<<4)  /* Do not move resource */
> >> >> > -
> >> >> > +#define IORESOURCE_PCI_CS              (1<<5)  /* PCI configuration space */
> >> >>
> >> >> What is the purpose of this?  It seems that you are marking regions
> >> >> that we call MMCONFIG on x86, or ECAM-type regions in the language of
> >> >> the PCIe spec.  I see that you set it in several places, but I don't
> >> >> see anything that ever looks for it.  Do you have plans to use it in
> >> >> the future?  If it really does correspond to MMCONFIG/ECAM, we should
> >> >> handle those regions consistently across all architectures.
> >> >
> >> > The purpose is ultimately to obtain the MMCONFIG/ECAM resources assigned
> >> > to a PCI host controller. I've used this in the of_pci_parse_ranges()
> >> > and in the static board setup code to mark ranges as such. Perhaps
> >> > IORESOURCE_ECAM or IORESOURCE_MMCONFIG might have been better names. I
> >> > also just noticed that I'm not using this anywhere, but the plan was to
> >> > eventually use it with platform_get_resource(). However that doesn't
> >> > seem to work either because the lower bits of the flags aren't use for
> >> > comparison in that function.
> >> >
> >> > Any other ideas how that could be handled? Basically what I need is a
> >> > way to mark a resource as an MMCONFIG/ECAM range so that it can be used
> >> > to program the PCI host controller accordingly. I don't know how these
> >> > are assigned on x86. I was under the impression that the MMCONFIG/ECAM
> >> > space was accessed through a single single address/data register pair.
> >>
> >> The legacy config access mechanism (CF8h/CFCh registers described in
> >> PCI 3.0 spec sec 3.2.2.3.2) is a single address/data pair, but this is
> >> mostly x86-specific.  The ECAM mechanism (described in the PCIe 3.0
> >> spec sec 7.2.2) is not a single address/data pair; instead, each byte
> >> of config space is directly mapped into the host's MMIO space.
> >>
> >> Here's what we do on x86 (omitting some historical grunge that
> >> complicates things):
> >>
> >>   - Discover the host bridge via a PNP0A08 device in the ACPI namespace.
> >>   - Discover the bus number range behind the bridge using a _CRS
> >> method in the PNP0A08 device.
> >>   - Discover the ECAM space for those buses via a _CBA method in the
> >> PNP0A08 device.
> >>   - Tell the config accessors (struct pci_ops) that the ECAM space for
> >> buses A-B is at address X.
> >>   - Enumerate the devices behind the host bridge by calling
> >> pci_scan_root_bus(), passing the config accessors.
> >>
> >> It sounds like you want a way to parse the resources at one point,
> >> saving them and marking the ECAM region, then at a later point, look
> >> up the ECAM from a saved list.  We don't do that on x86 because the
> >> config accessors keep an internal list of the ECAM area for each bus.
> >>
> >> We do of course want to put this ECAM space in the IORESOURCE_MEM tree
> >> because it consumes address space and we have to make sure we don't
> >> put anything else on top of it.  But we don't have any reason to
> >> describe the MMIO -> config space function in that tree.  From the
> >> point of view of the rest of the system, it's just MMIO space that's
> >> consumed by the PCI host bridge, just like any other device-specific
> >> MMIO area.
> >
> > What I currently do is pass the ECAM space as a resource to the PCI host
> > bridge platform device. Regular and extended configuration spaces are
> > given by the third and fourth resources, respectively. If I understand
> > correctly, you're saying that nothing beyond that needs to be encoded.
> > In other words it is enough for the PCI host bridge driver to know where
> > to take the data from.
> 
> Yes, I think so.
> 
> I'd like to someday make ECAM support generic, since it's specified by
> the PCIe spec.  The spec doesn't differentiate between PCI
> configuration space (offsets 0-0xff) and PCI Express *extended*
> configuration space (offsets 0x100-0xfff).  But it sounds like Tegra
> might have a memory-mapped configuration mechanism that is similar to
> ECAM but with a different address map, since you mention two resources
> (third and fourth).  That's not a problem, since you're doing a
> Tegra-specific solution right now anyway, but something to keep in the
> back of your mind if we ever do make a generic ECAM solution.

Something that's kept me wondering is why there actually need to be two
separate regions. Since the extended configuration space is a superset
of the regular configuration space it should be possible to access the
regular registers via the extended configuration space as well.

Stephen: Could you try to find out whether the regular configuration
space translation can just be omitted if we already set up the one for
the extended configuration space? In tegra_pcie_setup_translations(),
BAR 0 is setup for regular configuration space (which requires a 16 MiB
region), while BAR 1 is setup for the extended configuration space
(requiring a full 256 MiB region). However, if I understand correctly,
each of the registers that can be accessed via the BAR 0 translation can
also be accessed via the BAR 1 translation. That seems like we're
wasting the 16 MiB set aside for the BAR 0 mapping.

> > I'll have to see what this means for the DT binding. There are other
> > issues that I need to think about, like for example how to pass the ECAM
> > space from the PCI host controller to each of the two bridges via the
> > ranges property. This no longer makes sense in the current form, as the
> > ECAM covers the configuration spaces for devices of both bridges and
> > cannot really be split among them.
> 
> We have the same situation on x86.  Part of the historical grunge that
> I omitted is that there's a static ACPI table (MCFG) that can tell you
> the ECAM range for a bus number range.  Often that bus number range
> includes several host bridges.  On x86, we have a single set of ECAM
> config accessors (see pci_mmcfg), and they maintain a list of "bus
> number -> ECAM addr" mappings internally, independent of which host
> bridge leads to the buses.

That's very similar to how things work on Tegra. Configuration space
accesses to the host bridges are done via their respective memory-mapped
register spaces. All other accesses use either the BAR 0 or BAR 1
translations as I described above. These translations however are unique
and only a single set of accessors are provided.

Given that and what I said in the other mail about the implementation of
ECAM on Tegra any CS range we pass to the host bridges via the DT ranges
property is actually wrong.

Thierry
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From b29396 at freescale.com  Wed Aug 15 02:55:27 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 15 Aug 2012 14:55:27 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815054436.GK2232@pengutronix.de>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
Message-ID: <20120815065526.GG19681@shlinux2.ap.freescale.net>

On Wed, Aug 15, 2012 at 07:44:36AM +0200, Uwe Kleine-K?nig wrote:
> Hello,
> 
> (Cc += devicetree-discuss at lists.ozlabs.org)
> 
> On Wed, Aug 15, 2012 at 11:59:18AM +0800, Dong Aisheng wrote:
> > On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
> > > On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
> > >> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
> > >>> I have a minor nit; while renumbering the pinctrl definitions is
> > >>> laudable and device trees can match, there are 16 other pin controls
> > >>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
> > >>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
> > >>> (pin_id*4)).
> > >>
> > >> What do you mean of this value calculated?
> > >
> > > Well, it just seems the datasheet has been read from the point of view
> > > of the SW_CTRL settings (pad pullups, drive strength etc.) to define
> > > the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
> > > I mistyped) has been entered as an enum into this list. Then a table
> > > has been generated using these enums to supply a pin id. Then this pin
> > > id is not relevant anymore; it actually gets referenced by it's
> > > *offset into the table*.
> > >
> > Not exactly, probably.
> > Basically we follow the mux reigster offset to define pin id, however,
> > there're also some pads may not have mux function but only config
> > which also has a pin id
> > and vice versa.
> > Those pins are not ordered by it's mux regsiter offset.
> > 
> > Actually I did not manually search all those pins, instead, i just
> > using the exist ones:
> > arch/arm/plat-mxc/include/mach/iomux-mx51.h
> > Since this exist headfile already covers this case.
> > 
> > > In this case, basically the code misses a few pins which have ALT
> > > settings but perhaps not always the ability to change pad control -
> > > EIM_DA5 to 15 are a good example.
> > >
> > As i said, we already defined those pin ids.
> > 
> > > Probably better would be to define the binding almost exactly as it
> > > was done in the old method; iomux_v3_cfg_t took into account the three
> > > register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
> > > and the three values to be put into those registers.
> > >
> > > This has been reduced down in pinctrl to what I find quite strange,
> > > which is a completely arbitrary pin "id" mapping, which indirectly
> > > references an entry in a table by index which is why pin 1 as a start
> > > looks odd.
> > >
> > Start with pin 1 is a bug which caused by my mistake during the early
> > data conversion.
> > 
> > > If the binding is entirely i.MX-specific or even i.MX51-specific then
> > > why not define the pins in the device tree the "old" iomux_v3_cfg_t
> > > way, which is the way they are in the table of imx_pin_regs;
> > >
> > >       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
> > > MX51_PAD_EIM_D16__AUD4_RXFS */
> > >
> > > 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
> > > 0x000 is the IPP reg, and 0 the IPP value.
> > >
> > > So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
> > > mode/sion, IPP, select - in that order) would be a valid pin
> > > definition and require no table. Sure, the offsets are device specific
> > > but then the arbitrary numbering is too.
> > > This way old iomux controls
> > > can be re-derived for people who use the old method in old kernels, or
> > > use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
> > > porting the Efika to it on MX5 for U-Boot right now). Also that huge
> > > table goes away - it can be built at runtime, along with the
> > > PAD_NAME__ALT_MODE_NAME description.
> > >
> > I can't agree this is better than the exist one now.
> > It's hard to use in device tree.
> > And how would you parse the pin id from this data array?
> I admit I didn't follow completely the calculation suggestion by Matt,
> but I think in general he has a point. This is more or less what I
> thought when I built the imx35 pinctrl driver.
> 
> With the current approach (i.e. put the pinfuncs in some order that
> seems sensible today and then referencing them by index according to
> that ordering) you really get into troubles if you have to add a new
> function. You have to add it to the end to not break existing device
> trees and so the ordering is broken.
> 
Actually, we do not mean to maintain the ordering in driver.
It just needs to be align with the pin func ids definitions in binding
doc. So the ordering broken in driver is not an issue, it just looks
not so better if we really have to add a new pin function to the end
due to mistake but this does not break anything to work.

> Also "11" has no obvious relation to MX35_PAD_COMPARE__SDMA_EXTDMA_2
> other than a match if you grep over the binding docs (or the driver).
> While "0x32c, 0x008, 7, 0x0, 0" is longer and looks more ugly the
> mapping is obvious and so IMHO preferable.
> 
Also, don't you think this is hard to use for devicetree?
And we need to reference datasheet to fill these values.

I just keep using as the old way at best and i remember Sascha also suggested
before that we don't want to lose using the macro way as
MX35_PAD_COMPARE__SDMA_EXTDMA_2 to make easy use.
In the future, we will switch to macro when dt supports.
For the way "0x32c, 0x008, 7, 0x0, 0", it's very unconveniently to use macro.

Regards
Dong Aisheng



From zhangfei.gao at gmail.com  Wed Aug 15 03:29:16 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Wed, 15 Aug 2012 15:29:16 +0800
Subject: [PATCH v3 3/4] dmatest: add dmaengine_slave_config for DMA_MEMCPY
In-Reply-To: <20120814082047.GF18957@n2100.arm.linux.org.uk>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-4-git-send-email-zhangfei.gao@marvell.com>
 <20120814082047.GF18957@n2100.arm.linux.org.uk>
Message-ID: <CAMj5Bkg7sOf39AkpW1An5gTNEbKmFvqVNfXjkFXu6MhSAkYCCg@mail.gmail.com>

On Tue, Aug 14, 2012 at 4:20 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Aug 14, 2012 at 12:11:58PM +0800, Zhangfei Gao wrote:
>> Set direction to DMA_MEM_TO_MEM
>> DMA driver may require such configure info
>
> No, this is wrong.  By default, any channel being asked to do memcpy
> should deal with the channel configuration itself and not require it
> to be set - otherwise this breaks the async_tx API.
>
> So consider that dma-test found a bug in your driver which needs fixing.

Thanks Russell for the info.

Really not know DMA_MEM_TO_MEM should be set as default.
>From include/linux/dmaengine.h only find "DMA_ASYNC_TX capability
is automatically set as dma devices are registered".

Will change driver and set config as DMA_MEM_TO_MEM as default setting.

Thanks


From zhangfei.gao at gmail.com  Wed Aug 15 03:44:35 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Wed, 15 Aug 2012 15:44:35 +0800
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <20120814083026.GG18957@n2100.arm.linux.org.uk>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
 <20120814083026.GG18957@n2100.arm.linux.org.uk>
Message-ID: <CAMj5Bkhu2r_R6q3g2aJk1r9Ytz+1eK7gfy6vWuAg1+OPUN7z8Q@mail.gmail.com>

On Tue, Aug 14, 2012 at 4:30 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> Please consider looking at the virtual dma channel support, which I've
> recently added.  This removes the burden of managing the descriptor
> lists from the driver, deals with the workqueues for completing
> descriptors, etc.
>
> All you need to do is to build the descriptors for the DMA operation,
> manage the scheduling of virtual channels onto physical channels,
> calculate the position of DMA, and starting off and handling the DMA
> hardware.
>
> "virtual dma channel support" is probably something of a misnomer though;
> it can also be used for situations where there's a 1:1 binding between
> virtual and physical dma channels (iow, no virtual channels at all.)
>

Thanks Russell.

Have noticed virt-dma.c before.
The reason not use it is I thought it would be simpler
and easy-debugging to manage virt-channel via two lists:
pending and running lists.

Still have one question.
vchan_tx_submit is sending vd node to submitted list.
list_add_tail(&vd->node, &vc->desc_submitted);

While what we want is send the desc chain, including many nodes,
and the first desc will have call back.
chain 1: first -> desc -> desc -> desc
chain 2: first -> desc -> desc -> desc
Once the dma chain done, irq happen and call back from first desc.

Is that mean vchan_tx_submit is not covering this situation?

Thanks


From zhangfei.gao at gmail.com  Wed Aug 15 03:47:48 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Wed, 15 Aug 2012 15:47:48 +0800
Subject: [PATCH v3 2/4] dmaengine: mmp_tdma: add dt support
In-Reply-To: <201208140934.11774.arnd@arndb.de>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-3-git-send-email-zhangfei.gao@marvell.com>
 <201208140934.11774.arnd@arndb.de>
Message-ID: <CAMj5Bkjub2CUQZkse1MY_dn1CtKUmUwErYV-GQ1YYALHmWM9sQ@mail.gmail.com>

On Tue, Aug 14, 2012 at 5:34 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 14 August 2012, Zhangfei Gao wrote:
>> Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
>> ---
>>  Documentation/devicetree/bindings/dma/mmp-dma.txt |   30 ++++++++++++
>>  drivers/dma/mmp_tdma.c                            |   51 +++++++++++++--------
>>  2 files changed, 61 insertions(+), 20 deletions(-)
>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
>
> but please add a changelog text for this patch and every other one you do.

Thanks Arnd, will take care later.


From u.kleine-koenig at pengutronix.de  Wed Aug 15 03:51:17 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 15 Aug 2012 09:51:17 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815065526.GG19681@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
Message-ID: <20120815075117.GL2232@pengutronix.de>

Hello,

On Wed, Aug 15, 2012 at 02:55:27PM +0800, Dong Aisheng wrote:
> On Wed, Aug 15, 2012 at 07:44:36AM +0200, Uwe Kleine-K?nig wrote:
> > Hello,
> > 
> > (Cc += devicetree-discuss at lists.ozlabs.org)
> > 
> > On Wed, Aug 15, 2012 at 11:59:18AM +0800, Dong Aisheng wrote:
> > > On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
> > > > On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
> > > >> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
> > > >>> I have a minor nit; while renumbering the pinctrl definitions is
> > > >>> laudable and device trees can match, there are 16 other pin controls
> > > >>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
> > > >>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
> > > >>> (pin_id*4)).
> > > >>
> > > >> What do you mean of this value calculated?
> > > >
> > > > Well, it just seems the datasheet has been read from the point of view
> > > > of the SW_CTRL settings (pad pullups, drive strength etc.) to define
> > > > the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
> > > > I mistyped) has been entered as an enum into this list. Then a table
> > > > has been generated using these enums to supply a pin id. Then this pin
> > > > id is not relevant anymore; it actually gets referenced by it's
> > > > *offset into the table*.
> > > >
> > > Not exactly, probably.
> > > Basically we follow the mux reigster offset to define pin id, however,
> > > there're also some pads may not have mux function but only config
> > > which also has a pin id
> > > and vice versa.
> > > Those pins are not ordered by it's mux regsiter offset.
> > > 
> > > Actually I did not manually search all those pins, instead, i just
> > > using the exist ones:
> > > arch/arm/plat-mxc/include/mach/iomux-mx51.h
> > > Since this exist headfile already covers this case.
> > > 
> > > > In this case, basically the code misses a few pins which have ALT
> > > > settings but perhaps not always the ability to change pad control -
> > > > EIM_DA5 to 15 are a good example.
> > > >
> > > As i said, we already defined those pin ids.
> > > 
> > > > Probably better would be to define the binding almost exactly as it
> > > > was done in the old method; iomux_v3_cfg_t took into account the three
> > > > register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
> > > > and the three values to be put into those registers.
> > > >
> > > > This has been reduced down in pinctrl to what I find quite strange,
> > > > which is a completely arbitrary pin "id" mapping, which indirectly
> > > > references an entry in a table by index which is why pin 1 as a start
> > > > looks odd.
> > > >
> > > Start with pin 1 is a bug which caused by my mistake during the early
> > > data conversion.
> > > 
> > > > If the binding is entirely i.MX-specific or even i.MX51-specific then
> > > > why not define the pins in the device tree the "old" iomux_v3_cfg_t
> > > > way, which is the way they are in the table of imx_pin_regs;
> > > >
> > > >       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
> > > > MX51_PAD_EIM_D16__AUD4_RXFS */
> > > >
> > > > 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
> > > > 0x000 is the IPP reg, and 0 the IPP value.
> > > >
> > > > So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
> > > > mode/sion, IPP, select - in that order) would be a valid pin
> > > > definition and require no table. Sure, the offsets are device specific
> > > > but then the arbitrary numbering is too.
> > > > This way old iomux controls
> > > > can be re-derived for people who use the old method in old kernels, or
> > > > use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
> > > > porting the Efika to it on MX5 for U-Boot right now). Also that huge
> > > > table goes away - it can be built at runtime, along with the
> > > > PAD_NAME__ALT_MODE_NAME description.
> > > >
> > > I can't agree this is better than the exist one now.
> > > It's hard to use in device tree.
> > > And how would you parse the pin id from this data array?
> > I admit I didn't follow completely the calculation suggestion by Matt,
> > but I think in general he has a point. This is more or less what I
> > thought when I built the imx35 pinctrl driver.
> > 
> > With the current approach (i.e. put the pinfuncs in some order that
> > seems sensible today and then referencing them by index according to
> > that ordering) you really get into troubles if you have to add a new
> > function. You have to add it to the end to not break existing device
> > trees and so the ordering is broken.
> > 
> Actually, we do not mean to maintain the ordering in driver.
> It just needs to be align with the pin func ids definitions in binding
> doc. So the ordering broken in driver is not an issue, it just looks
> not so better if we really have to add a new pin function to the end
> due to mistake but this does not break anything to work.
Well, if you add a function between say current function 11 and 12 all
device trees need fixing, i.e. increase all function ids >= 12 by one.
You obviously cannot fix out-of-tree users and even fixing the in-tree
users is ugly.
 
> > Also "11" has no obvious relation to MX35_PAD_COMPARE__SDMA_EXTDMA_2
> > other than a match if you grep over the binding docs (or the driver).
> > While "0x32c, 0x008, 7, 0x0, 0" is longer and looks more ugly the
> > mapping is obvious and so IMHO preferable.
> > 
> Also, don't you think this is hard to use for devicetree?
Not harder than the current approach. Obviously macro support would be
nice, but this applies to both approaches.

> And we need to reference datasheet to fill these values.
I'd list the explicit values in the binding docs as the indexes are
documented there now. So the difference for a device-tree writer is just
the content that is copy-and-pasted.

> I just keep using as the old way at best and i remember Sascha also suggested
> before that we don't want to lose using the macro way as
> MX35_PAD_COMPARE__SDMA_EXTDMA_2 to make easy use.
> In the future, we will switch to macro when dt supports.
> For the way "0x32c, 0x008, 7, 0x0, 0", it's very unconveniently to use macro.
That is just

	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11

vs.

	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0

isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
different story.)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linux at arm.linux.org.uk  Wed Aug 15 04:04:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 Aug 2012 09:04:16 +0100
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <CAMj5Bkhu2r_R6q3g2aJk1r9Ytz+1eK7gfy6vWuAg1+OPUN7z8Q@mail.gmail.com>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
 <20120814083026.GG18957@n2100.arm.linux.org.uk>
 <CAMj5Bkhu2r_R6q3g2aJk1r9Ytz+1eK7gfy6vWuAg1+OPUN7z8Q@mail.gmail.com>
Message-ID: <20120815080416.GH18957@n2100.arm.linux.org.uk>

On Wed, Aug 15, 2012 at 03:44:35PM +0800, zhangfei gao wrote:
> Still have one question.
> vchan_tx_submit is sending vd node to submitted list.
> list_add_tail(&vd->node, &vc->desc_submitted);
> 
> While what we want is send the desc chain, including many nodes,
> and the first desc will have call back.
> chain 1: first -> desc -> desc -> desc
> chain 2: first -> desc -> desc -> desc
> Once the dma chain done, irq happen and call back from first desc.

I don't understand why you want a DMA engine descriptor to represent
one single DMA hardware scatterlist entry.  This makes much more
difficult when reporting status, especially the DMA residue (which
your existing driver does not support.)

Why not hang several DMA hardware scatterlist entries off the same
DMA engine descriptor?


From linus.walleij at linaro.org  Wed Aug 15 04:10:54 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:10:54 +0200
Subject: [GIT PULL] U300 cleanups and sparseirq
Message-ID: <CACRpkdb6wB1QVNqn8_sHB8LH0To=aP_8+iocE8JZ2jKC5f_bYg@mail.gmail.com>

Hi ARM SoC maintainers,

could you please pull the following patch set sent out for review the other day
doing a number of cleanups and a minor improvement to U300, paving the
way for single zImage and device tree:

- Deprecate ancient platforms to make the following patches easier to
  make...
- Move out one header to platform data and one to the mach-u300 proper
  to depopulate <mach/*>
- Consolidate core machine files
- Convert to sparse IRQs

Please pull! Thanks.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
u300-cleanup

for you to fetch changes up to a4fe292fa75baaa9cfb1a7224614f31fcd0d9a7b:

  ARM: u300: convert to sparse IRQs (2012-08-13 13:53:07 +0200)

----------------------------------------------------------------
Linus Walleij (7):
      ARM: u300: retire ancient platforms
      pinctrl/coh901: retire ancient GPIO block versions
      pinctrl/coh901: move header to platform data dir
      ARM: u300: merge u300.c into core.c and rid headers
      ARM: u300: delete remnant clkdev.h file
      ARM: u300: move DMA channel header into mach-u300
      ARM: u300: convert to sparse IRQs

 arch/arm/Kconfig                                   |   1 +
 arch/arm/mach-u300/Kconfig                         |  43 +---
 arch/arm/mach-u300/Makefile                        |   1 -
 arch/arm/mach-u300/core.c                          | 100 +++-------
 .../mach-u300/{include/mach => }/dma_channels.h    |  11 +-
 arch/arm/mach-u300/i2c.c                           |   6 +-
 arch/arm/mach-u300/include/mach/clkdev.h           |   7 -
 arch/arm/mach-u300/include/mach/irqs.h             |  36 +---
 arch/arm/mach-u300/include/mach/platform.h         |  20 --
 arch/arm/mach-u300/include/mach/syscon.h           |  32 +--
 arch/arm/mach-u300/include/mach/u300-regs.h        |  19 +-
 arch/arm/mach-u300/spi.c                           |   2 +-
 arch/arm/mach-u300/timer.c                         |   5 +-
 arch/arm/mach-u300/timer.h                         |   1 +
 arch/arm/mach-u300/u300-gpio.h                     |  46 +----
 arch/arm/mach-u300/u300.c                          |  57 ------
 drivers/pinctrl/pinctrl-coh901.c                   | 220 ++++-----------------
 .../linux/platform_data/pinctrl-coh901.h           |  13 +-
 18 files changed, 87 insertions(+), 533 deletions(-)
 rename arch/arm/mach-u300/{include/mach => }/dma_channels.h (88%)
 delete mode 100644 arch/arm/mach-u300/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-u300/include/mach/platform.h
 create mode 100644 arch/arm/mach-u300/timer.h
 delete mode 100644 arch/arm/mach-u300/u300.c
 rename arch/arm/mach-u300/include/mach/gpio-u300.h =>
include/linux/platform_data/pinctrl-coh901.h (72%)

Yours,
Linus Walleij


From alanbutty12 at gmail.com  Wed Aug 15 04:36:57 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Wed, 15 Aug 2012 09:36:57 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120814235653.GA22226@titan.lakedaemon.net>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
Message-ID: <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>


On 15 Aug 2012, at 00:56, Jason Cooper <jason at lakedaemon.net> wrote:

> On Tue, Aug 14, 2012 at 09:06:16PM +0100, Ownerx35 wrote:
>> I have created a patch and have tested it myself that create a board
>> setup file for the Iomega StoreCenter IX2-200, create a dts file and
>> insert the appropriate lines into the common.h, makefile,
>> makefile.boot, kconfig and board-ft files.
> 
> Awesome!
> 
>> But am unsure how to properly submit it should i just post it here? or
>> is there a specific place i should post?
> 
> Take a look at /path/to/linux_src/Documentation/SubmittingPatches .
> 
> If you prefer working with git, the two commands I use are format-patch
> and then send-email.
> 
> Assuming the board is ARM based (most likely), then you've found the
> correct list.
> 
> Just post the series here and we'll offer helpful comments ;-)
> 
> Also, please check MAINTAINERS for the directories you are changing and
> include the maintainers in the CC: or TO:.  Most likely, that'll be
> myself and Andrew Lunn (kirkwood / orion boards).
> 
> hth,
> 
> Jason.

Sorry i meant board-dt in the previous message and the name just getting used to the mail program on os x aswel. I have run through the checkpatch.pl script and it tells me there are no errors but i just found out a few minutes ago theres a fix for the 2 sata ports not working (on all kirkwood devices as far as i know) so i am going to test that now as it envolves modifying a line in the dts file.

Also it is defiantly an arm kirkwood device. My patch also does not modify any driver's or anything else just create's the appropriate file in the arch/am/boot/dts directory and the board config in the arch/arm/mach-kirkwood directory along with adding the lines to the appropriate files in that directory. So do i need to inform anyone else? the maintainers file is pretty long and i am unsure of what / who i am looking for in it.

It's also a single patch so i just copy and paste the patch text into a reply like this and send it?

From linus.walleij at linaro.org  Wed Aug 15 04:51:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:51:36 +0200
Subject: [PATCH 01/14] ARM: at91: gpio: implement request and free
In-Reply-To: <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdasfFL15qHxucycjNjDeBddo_577W8fuedcU8WN-+JcTw@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:01 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Configure a gpio as input when freeing it to reduce power consumption/
> Confire the pin as pio when requested.
>
> This is need by DT as we do not mux them any more.
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Seems straight-forward and I guess this driver will eventually be
superseded by the new pinctrl driver.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 04:52:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:52:49 +0200
Subject: [PATCH 02/14] at91: regroup gpio and pinctrl under a simple-bus
In-Reply-To: <1344603731-32667-2-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdaP1qu5ZAn0-17U-Y_2_d-KoSLszm79HQS8RjBKW0+iSQ@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:01 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Fix also the reg size as we have 512 bytes bank not 256 bytes per gpio/mux
> controller
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Not that I understand device tree, so you rpobably want
Nicolas to review this one rather than me, but FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 04:54:17 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:54:17 +0200
Subject: [PATCH 03/14] arm: at91: at91sam9x5: fix gpio number per bank
In-Reply-To: <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdYUcuuCL1hxv4GNsi+0NUXf=-yeHKN8okn9ZuF2_iHg+g@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> On the serie 5 bank b and d have 19 and 22 pins only.
>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Again Nicolas' thing but FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 04:55:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:55:08 +0200
Subject: [PATCH 04/14] ARM: at91: add dummies pinctrl for non dt platform
In-Reply-To: <1344603731-32667-4-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-4-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkda01nrCX55D1hUbQa10Emim8gKbtBh7JvsVbksm4avA=Q@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

This approach is becoming popular and seems to work, so
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Wed Aug 15 04:57:09 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 Aug 2012 09:57:09 +0100
Subject: [PATCH] ARM: Dove: allow PCI to be disabled
Message-ID: <20120815085709.GI18957@n2100.arm.linux.org.uk>

Allow PCI support for Dove to be disabled.  Some platforms do not have
anything connected to the PCIe ports, so requiring PCI support to be
built into the kernel just wastes space, and presents a lot more config
options than are necessary.

However, select USB_ARCH_HAS_EHCI so that we can still have EHCI
support.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/Kconfig            |    3 ++-
 arch/arm/mach-dove/Makefile |    3 ++-
 arch/arm/mach-dove/common.h |    4 ++++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 27f5b2c..344d40e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -536,14 +536,15 @@ config ARCH_IXP4XX
 config ARCH_DOVE
 	bool "Marvell Dove"
 	select CPU_V7
-	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
+	select MIGHT_HAVE_PCI
 	select NEED_MACH_IO_H
 	select PLAT_ORION
 	select CLKDEV_LOOKUP
 	select NEED_MACH_MEMORY_H
 	select COMMON_CLK
+	select USB_ARCH_HAS_EHCI
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 7d89269..b5a5773 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,5 @@
-obj-y				+= common.o addr-map.o irq.o pcie.o mpp.o clock.o dump_cp15_regs.o
+obj-y				+= common.o addr-map.o irq.o mpp.o clock.o dump_cp15_regs.o
+obj-$(CONFIG_PCI)		+= pcie.o
 
 obj-$(CONFIG_MACH_DOVE_DB)	+= dove-db-setup.o
 obj-$(CONFIG_MACH_CM_A510)	+= cm-a510.o
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 2ea271d..17404a0 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -29,7 +29,11 @@ void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_hwmon_init(void);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONfig_PCI
 void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
 void dove_ehci0_init(void);
 void dove_ehci1_init(void);
 void dove_uart0_init(void);


From linus.walleij at linaro.org  Wed Aug 15 04:57:58 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 10:57:58 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdY2HjwOBy7P8mZ81f8bYU4V2=taXzqv03q9NWqbfMVQ4A@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> +                               atmel,mux-mask = <
> +                                     /*    A         B     */
> +                                      0xffffffff 0xffc00c3b  /* pioA */
> +                                      0xffffffff 0x7fff3ccf  /* pioB */
> +                                      0xffffffff 0x007fffff  /* pioC */
> +                                     >;

If I read a devcie tree like this it will be a bit hard to understand what is
happening. But again Nicolas is maintaining the AT91 DT.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:00:31 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:00:31 +0200
Subject: [PATCH 07/14] arm: at91: dt: at91sam9 add serial pinctrl support
In-Reply-To: <1344603731-32667-7-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-7-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdbknWyukz3k3VCTySe=7igvB5EsYaEim=hcNV0QHcTznw@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Set the dbgu pinctrl config by default as we have only one possible config
> For other uart set the rxd/txd by default.
>
> For at91sam9x5ek create soc based dts as we need to include specific soc dtsi.

Some things I understand, like this:

> @@ -145,6 +240,8 @@
>                                 compatible = "atmel,at91sam9260-usart";
>                                 reg = <0xfffff200 0x200>;
>                                 interrupts = <1 4 7>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&pinctrl_dbgu>;
>                                 status = "disabled";
>                         };

And that looks good ...

But the magic hex values I have no clue about so prefer to leave this
to Nicolas.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:01:28 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:01:28 +0200
Subject: [PATCH 08/14] tty: atmel_serial: add pinctrl support
In-Reply-To: <1344603731-32667-8-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-8-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdbPUTGYUR4iVaJ39zZjadtkDBjGDCYLZhksgMXTGnsqPA@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-serial at vger.kernel.org

Looking good,
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:02:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:02:02 +0200
Subject: [PATCH 09/14] arm: at91: dt: sam9m10g45ek: use rts/cts pinctrl
 group for uart1
In-Reply-To: <1344603731-32667-9-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-9-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdYh=acbdEs1Am7-W=okRLUeMTHZCRO1AzJYqNMWTQ-qwA@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:02:29 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:02:29 +0200
Subject: [PATCH 10/14] arm: at91: dt: sam9263ek: use rts/cts pinctrl group
 for uart0
In-Reply-To: <1344603731-32667-10-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-10-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdZjP5xOXQasoFA0aaRHUjhHOTDTeLm928P2-iKs3nOssw@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:03:01 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:03:01 +0200
Subject: [PATCH 11/14] arm: at91: dt: sam9g20ek: use rts/cts/dtr/dsr/dcd/ri
 pinctrl group for uart0
In-Reply-To: <1344603731-32667-11-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-11-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdYrOzTh6GLW-P7eindij7NndhBfahb8h=pdiu=-gx9WGQ@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:05:03 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:05:03 +0200
Subject: [PATCH 12/14] MTD: atmel nand: fix gpio missing request
In-Reply-To: <1344603731-32667-12-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-12-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdanYZ3CFjFYzeBZanJaCsK6+YGLETRV3wPu8BTLq6D=FA@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> without this the gpio will not be muxed as a gpio by the current custom pinmux
> or later by the pinctrl
(...)
> +       if (gpio_is_valid(host->board.det_pin))
> +               gpio_free(host->board.det_pin);
> +
> +       if (gpio_is_valid(host->board.enable_pin))
> +               gpio_free(host->board.enable_pin);
> +
> +       if (gpio_is_valid(host->board.rdy_pin))
> +               gpio_free(host->board.rdy_pin);
> +

If you use devm_gpio_request() you can probably get rid of this block of
code, but no big deal so:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:06:15 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:06:15 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
(...)
> +                               nand {
> +                                       pinctrl_nand: nand-0 {
> +                                               atmel,pins =
> +                                                       <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
> +                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
> +                                       };
> +                               };

Again magic hex I don't understand so skipping this patch -> Nicolas.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 05:07:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 11:07:00 +0200
Subject: [PATCH 14/14] MTD: atmel_nand: add pinctrl consumer support
In-Reply-To: <1344603731-32667-14-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-14-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdaH8xTMfY45zdZAymahMZcm-0UDPqmfvLzpg5uaicv3yQ@mail.gmail.com>

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-mtd at lists.infradead.org

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From zhangfei.gao at gmail.com  Wed Aug 15 05:09:56 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Wed, 15 Aug 2012 17:09:56 +0800
Subject: [PATCH v3 1/4] dmaengine: mmp-pdma support
In-Reply-To: <20120815080416.GH18957@n2100.arm.linux.org.uk>
References: <1344917519-9505-1-git-send-email-zhangfei.gao@marvell.com>
 <1344917519-9505-2-git-send-email-zhangfei.gao@marvell.com>
 <20120814083026.GG18957@n2100.arm.linux.org.uk>
 <CAMj5Bkhu2r_R6q3g2aJk1r9Ytz+1eK7gfy6vWuAg1+OPUN7z8Q@mail.gmail.com>
 <20120815080416.GH18957@n2100.arm.linux.org.uk>
Message-ID: <CAMj5BkgzMTCThfHw7jd01KsECCWO5Uaw2dZNrDGrrGiXoaRmFA@mail.gmail.com>

On Wed, Aug 15, 2012 at 4:04 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Wed, Aug 15, 2012 at 03:44:35PM +0800, zhangfei gao wrote:
>> Still have one question.
>> vchan_tx_submit is sending vd node to submitted list.
>> list_add_tail(&vd->node, &vc->desc_submitted);
>>
>> While what we want is send the desc chain, including many nodes,
>> and the first desc will have call back.
>> chain 1: first -> desc -> desc -> desc
>> chain 2: first -> desc -> desc -> desc
>> Once the dma chain done, irq happen and call back from first desc.
>
> I don't understand why you want a DMA engine descriptor to represent
> one single DMA hardware scatterlist entry.  This makes much more
> difficult when reporting status, especially the DMA residue (which
> your existing driver does not support.)
>
> Why not hang several DMA hardware scatterlist entries off the same
> DMA engine descriptor?

The cookie can be used to compute tx_status.
For example, one descriptor chain has 10 descriptor, with cookie++.
tx_submit will return final cookie=9.
dma_async_is_tx_complete will use this cookie to check the status.

If using single descriptor describing big chunc of data, with only cookie.
Then driver has to directly check the dma register to get status.

I think the residue may only meaningful to cyclic dma, for audio.
For peripheral dma, irq after one descriptor chain, do we have to set it?
If needed it, how about get such info in irq.

Thanks


From hvaibhav at ti.com  Wed Aug 15 05:10:57 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 15 Aug 2012 09:10:57 +0000
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <20120814082911.GG11011@atomide.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>

On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> Hi,
> 
> * Paul Walmsley <paul at pwsan.com> [120726 13:07]:
> > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > 
> > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > The rest of the IP block named in the file don't use periods -- which
> > > is also the style used by the rest of the OMAP SoCs.  Is there
> > > some reason that these have periods in their names?
> > 
> > I've changed those to match the rest of the names, and queued the 
> > following for 3.7.
> > 
> > Thanks again for all the hard work you all put into this.  I realize that 
> > with all the upstream changes, this was probably a little painful for you. 
> > But from my perspective you've been a pleasure to work with through the 
> > process.
> 
> As am33xx and omap5 are DT only, we should start moving towards getting
> rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> data from .dtsi files instead.
> 

It may not be so straight, given the fact that hwmod layer 
requires these resources, as hwmod is responsible to configure SYSCONF 
register of the device (happens very early at core_init level).

Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
core_init call, which will take DT resources and initialize accordingly.

Another dependency we will have is on system timers, Jon has already done 
some initial work on this, but I believe we did not concluded on the it.
I will re-start the thread again, since in any case DT support in timer is 
required.


> Alternatively we could get rid of the names and match the module based on
> pa_start and pa_end.
> 

Just FYI, from resource perspective, I have changed omap_device layer for DT 
resources only (still need hwmod resources as explained above) and patch 
looks something like (and it works) -


diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..cb481fe 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -528,10 +528,15 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
         * HACK: Ideally the resources from DT should match, and hwmod
         * should just add the missing ones. Since the name is not
         * properly populated by DT, stick to hwmod resources only.
+        *
+        * But in case of all new devices, like AM33XX and OMAP5, where
+        * only DT boot is supported,  stick to DT resources only.
         */
-       if (pdev->num_resources && pdev->resource)
+       if (pdev->num_resources && pdev->resource) {
                dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
                        __func__, pdev->num_resources);
+               goto skip_res_override;
+       }

        res_count = omap_device_count_resources(od);
        if (res_count > 0) {
@@ -550,6 +555,7 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
                        goto oda_exit3;
        }

+skip_res_override:
        if (!pm_lats) {
                pm_lats = omap_default_latency;
                pm_lats_cnt = ARRAY_SIZE(omap_default_latency);


Thanks,
Vaibhav


From hvaibhav at ti.com  Wed Aug 15 05:11:57 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 15 Aug 2012 14:41:57 +0530
Subject: [RFC RESEND 1/4] arm/dts: OMAP: Add timer nodes
In-Reply-To: <500D6CAB.4030504@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-2-git-send-email-jon-hunter@ti.com>
 <5000D647.4090200@gmail.com> <500439A8.1050705@ti.com>
 <500D6CAB.4030504@ti.com>
Message-ID: <502B67DD.6050904@ti.com>



On 7/23/2012 8:54 PM, Jon Hunter wrote:
> Hi Rob,
> 
> On 07/16/2012 10:56 AM, Jon Hunter wrote:
>> Hi Rob,
>>
>> On 07/13/2012 09:15 PM, Rob Herring wrote:
>>> On 07/13/2012 05:26 PM, Jon Hunter wrote:
>>>> Add the 12 GP timers nodes present in OMAP3.
>>>> Add the 11 GP timers nodes present in OMAP4.
>>>>
>>>> Add documentation for timer properties specific to OMAP.
>>>>
>>>> For each timer an alias is being added. The purpose for doing this is because
>>>> the OMAP dmtimer driver uses an ID to distinguish between the different timer
>>>> instances. For example, a timer can be requested by its ID. By adding an alias
>>>> for each timer we can then use the function of_alias_get_id() to extract the
>>>> ID for each timer from the alias name. The same method is used for the TTY
>>>> serial devices. If it is preferred that such an alias is not added and there
>>>> is a better way to pass an ID from device-tree let me know.
>>>
>>> I'm not sure this is really a good use of aliases. UARTs use aliases
>>> because it is important that the UART number to tty number is known and
>>> fixed. IIUC, as an example you are picking timer1 because it has
>>> properties X, Y and Z. If so, then you should describe those h/w
>>> properties within the timer nodes so you can pick which timer to use
>>> based on it's h/w properties.
>>
>> Thanks for the feedback. What you suggest could definitely work for most
>> timers. The only item that I would need to resolve here is the handling
>> of system timers (ie. those used for clockevents and clocksource). These
>> system timers (for OMAP) are reserved during early boot based upon the
>> timer ID today and so this is before the actual main timer driver has
>> been probed and all the attributes of the timers has been read for
>> device-tree.
>>
>> One thought would be to move the reservation of the system timers out of
>> the kernel and into device-tree itself. Then we query device tree on
>> start-up to see which we should use. I am wondering if this could be a
>> better use of alias? For example, say I want to use timer1 as my
>> clockevent timer and so I could have an alias of ...
>>
>> alias {
>> 	clockevent_timer = &timer1;
>> }
>>
>> However, I am not sure if this is even correct, because there does not
>> appear to be an API to search the aliases by name and return the
>> phandle, just of_alias_get_id(). Alternatively, I could add another
>> property called "ti,timer-clockevent" that is populated for the timer
>> used as the clockevent timer.
> 
> Do you have any inputs on the above? Does it make sense to reserve timer
> resources for kernel system timers in device-tree?
> 

Hey Jon,

Did we get conclude on this? I haven't got anything further on this
thread, this may block baseport support for the new devices in omap2
family, like AM33xx and OMAP5.


Thanks,
Vaibhav

> Cheers
> Jon
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 


From hvaibhav at ti.com  Wed Aug 15 05:13:28 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 15 Aug 2012 14:43:28 +0530
Subject: [RFC RESEND 2/4] ARM: OMAP3: Dynamically disable secure timer
 nodes for secure devices
In-Reply-To: <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
Message-ID: <502B6838.9080907@ti.com>



On 7/14/2012 3:56 AM, Jon Hunter wrote:
> OMAP3 devices may or may not have security features enabled. Security enabled
> devices are known as high-secure (HS) and devices without security are known as
> general purpose (GP).
> 
> For OMAP3 devices there are 12 general purpose timers available. On secure
> devices the 12th timer is reserved for secure usage and so cannot be used by
> the kernel, where as for a GP device it is available. We can detect the OMAP
> device type, secure or GP, at runtime via an on-chip register. Today, when not
> using DT, we do not register the 12th timer as a linux device if the device is
> secure.
> 
> When using device tree, device tree is going to register all the timer devices
> it finds in the device tree blob. To prevent device tree from registering 12th
> timer on a secure OMAP3 device we can add a status property to the timer
> binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
> device has a property "ti,timer-secure" to indicate that it will not be
> available on a secure device and so for secure OMAP3 devices, we search for
> timers with this property and then disable them. Using the prom_add_property()
> function to dynamically add a property was a recommended approach suggested by
> Rob Herring [1].
> 
> I have tested this on an OMAP3 GP device and faking it to pretend to be a
> secure device to ensure that any timers marked with "ti,timer-secure" are not
> registered on boot. I have also made sure that all timers are registered as
> expected on a GP device by default.
> 
> [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
> 
> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> ---
>  arch/arm/mach-omap2/board-generic.c |    1 +
>  arch/arm/mach-omap2/common.h        |    1 +
>  arch/arm/mach-omap2/timer.c         |   36 +++++++++++++++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index 6f93a20..20124d7 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>  static void __init omap_generic_init(void)
>  {
>  	omap_sdrc_init(NULL, NULL);
> +	omap_dmtimer_init();
>  
>  	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
>  }
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index 1f65b18..d6a4875 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>  				      struct omap_sdrc_params *sdrc_cs1);
>  struct omap2_hsmmc_info;
>  extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
> +extern void omap_dmtimer_init(void);
>  
>  #endif /* __ASSEMBLER__ */
>  #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 13d20c8..e3b9931 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -36,6 +36,7 @@
>  #include <linux/clocksource.h>
>  #include <linux/clockchips.h>
>  #include <linux/slab.h>
> +#include <linux/of.h>
>  
>  #include <asm/mach/time.h>
>  #include <plat/dmtimer.h>
> @@ -482,6 +483,41 @@ static int __init omap2_dm_timer_init(void)
>  }
>  arch_initcall(omap2_dm_timer_init);
>  
> +static struct property timer_disabled = {
> +	.name = "status",
> +	.length = sizeof("disabled"),
> +	.value = "disabled",
> +};
> +
> +static struct of_device_id omap3_timer_match[] __initdata = {
> +	{ .compatible = "ti,omap3-timer", },
> +	{ }
> +};
> +
> +/**
> + * omap_dmtimer_init - initialisation function when device tree is used
> + *
> + * For secure OMAP3 devices, timers with device type "timer-secure" cannot
> + * be used by the kernel as they are reserved. Therefore, to prevent the
> + * kernel registering these devices remove them dynamically from the device
> + * tree on boot.
> + */
> +void __init omap_dmtimer_init(void)
> +{
> +	struct device_node *np;
> +
> +	if (!cpu_is_omap34xx())
> +		return;
> +

Sorry for responding so late, but why only omap34xx check here?
Isn't this applicable to all omap & non-omap devices?

Thanks,
Vaibhav

> +	/* If we are a secure device, remove any secure timer nodes */
> +	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
> +		for_each_matching_node(np, omap3_timer_match) {
> +			if (of_get_property(np, "ti,timer-secure", NULL))
> +				prom_add_property(np, &timer_disabled);
> +		}
> +	}
> +}
> +
>  /**
>   * omap2_override_clocksource - clocksource override with user configuration
>   *
> 


From josephl at nvidia.com  Wed Aug 15 05:14:51 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:14:51 +0800
Subject: [PATCH 0/5] ARM: tegra: add CPU hotplug support
In-Reply-To: <502A99CD.3060400@wwwdotorg.org>
References: <1344931644-3927-1-git-send-email-josephl@nvidia.com>
 <502A99CD.3060400@wwwdotorg.org>
Message-ID: <1345022091.25319.158.camel@jlo-ubuntu-64.nvidia.com>

Hi Stephen,

Thanks for your review.

On Wed, 2012-08-15 at 02:32 +0800, Stephen Warren wrote:
> On 08/14/2012 02:07 AM, Joseph Lo wrote:
> > This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
> > 
> > The first 3 patches make the CPU clock and reset control be a module and
> > the abstraction APIs for TegraXX SoCs. And clean up some codes for later
> > usage. Then add CPU hotplug support for Tegra20 and Tegra30.
> > 
> > Verified on Seaboard(Tegra20) and Cardhu(Tegra30)
> 
> There are two problems with this series:
> 
> 1) It doesn't compile if CONFIG_HOTPLUG_CPU isn't enabled. Please also
> make sure that Tegra20-only and Tegra30-only kernels compile (I didn't
> check this, so it may well already be the case).

I will add one more patch to enable HOTPLUG_CPU in this patch set.

I also verified the compiling and functionality of the Tegra20-only and
Tegra30-only kernels. It's OK.
> 
> 2) It prevents the "reboot" from working; the kernel hangs as it
> attempts to do the reboot. I've confirmed this isn't the case without
> this patch series, even if CONFIG_HOTPLUG_CPU is enabled.

I just found during the reboot process. It will call to
"platfor_cpu_kill" before assert the reset. But in this patch, the
"platform_cpu_kill" can't just be called along. It must be called after
"platform_cpu_die". So I will move all the SoC specific CPU shutdown
code into "platform_cpu_die" not separate into two functions. It will
prevent the system hang when calling to "smp_send_stop". (the flow for
your reference,
sys_reboot->machine_restart->smp_send_stop->smp_kill_cpus->platform_cpu_kill.)
> 
> I assume we'll want to enable CONFIG_HOTPLUG_CPU in tegra_defconfig once
> this is checked in?

Thanks,
Joseph

--
nvpublic



From hvaibhav at ti.com  Wed Aug 15 05:21:27 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 15 Aug 2012 14:51:27 +0530
Subject: [PATCH] ARM: AM33XX: board-generic: Add of_dev_auxdata to fix
 dev_id for CAN module
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA897EA@DBDE01.ent.ti.com>
References: <1344346636-28072-1-git-send-email-hvaibhav@ti.com>
 <50213214.7050505@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA88BDF@DBDE01.ent.ti.com>
 <5021CA01.2020206@gmail.com>
 <79CD15C6BA57404B839C016229A409A83EA897EA@DBDE01.ent.ti.com>
Message-ID: <502B6A17.7040800@ti.com>



On 8/8/2012 5:13 PM, Hiremath, Vaibhav wrote:
> On Wed, Aug 08, 2012 at 07:38:01, Rob Herring wrote:
>> On 08/07/2012 10:53 AM, Hiremath, Vaibhav wrote:
>>> On Tue, Aug 07, 2012 at 20:49:48, Rob Herring wrote:
>>>> On 08/07/2012 08:37 AM, Vaibhav Hiremath wrote:
>>>>> If the module requires only one clocksource to function, then
>>>>> driver can very well call clk_get() api with "con_id = NULL",
>>>>>
>>>>>        clk = clk_get(dev, NULL);
>>>>>
>>>>> And platform code should respect this and return valid clk handle.
>>>>> That means, now the clk_get() api would rely on dev_id, and platform
>>>>> code should either have clk node with matching dev_id (with con_id=NULL)
>>>>> or return dummy clk node.
>>>>>
>>>>> With DT support, we can fix the dev_id for particular module
>>>>> using "struct of_dev_auxdata" to satisfy above clk framework requirement.
>>>>>
>>>>> In case of AM33XX, we required this for the DCAN module, so this
>>>>> patch adds "of_dev_auxdata" for both DCAN_0/1 instances.
>>>>>
>>>>> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
>>>>> Cc: Tony Lindgren <tony at atomide.com>
>>>>> Cc: Paul Walmsley <paul at pwsan.com>
>>>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>>>> ---
>>>>> This patch is boot tested on BeagleBone platform, and checked for
>>>>> clk_get() return value in d_can module driver.
>>>>>
>>>>>  arch/arm/mach-omap2/board-generic.c |   18 +++++++++++++++++-
>>>>>  1 files changed, 17 insertions(+), 1 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
>>>>> index 6f93a20..c9b7903 100644
>>>>> --- a/arch/arm/mach-omap2/board-generic.c
>>>>> +++ b/arch/arm/mach-omap2/board-generic.c
>>>>> @@ -37,11 +37,27 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>>>>>  	{ }
>>>>>  };
>>>>>
>>>>> +/*
>>>>> + * Lookup table for attaching a specific name and platform_data pointer to
>>>>> + * devices as they get created by of_platform_populate(). Ideally this table
>>>>> + * would not exist, but the current clock implementation depends on some devices
>>>>> + * having a specific name OR to satisfy NULL con_id requirement from driver.
>>>>> + */
>>>>> +static const struct of_dev_auxdata am33xx_auxdata_lookup[] __initconst = {
>>>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481cc000, "d_can.0", NULL),
>>>>> +	OF_DEV_AUXDATA("bosch,d_can", 0x481d0000, "d_can.1", NULL),
>>>>> +	{ },
>>>>> +};
>>>>
>>>> Adding an additional clkdev lookup accomplishes the same thing and is a
>>>> cleaner solution.
>>>>
>>>
>>> That is also required and I have submitted patch for the same -
>>>
>>> http://www.spinics.net/lists/arm-kernel/msg187998.html
>>
>> That only adds the non-DT name. What I'm saying is you can have 2 lookup
>> names for the same clock.
>>
>>>
>>> With DT support, I am getting dev_id as -
>>>
>>>  - Without "reg" property: d_can.16 and d_can.17,
>>>    (I believe it changes dynamically here)
>>>
>>>  - With "reg" property: 481cc000.d_can and 481d0000.d_can
>>>
>>> Which is not so intuitive, I would like to see them as per Spec/TRM, so 
>>> doesn't this patch make sense?
>>
>> The spec doesn't have a base address for the module? This name is going
>> to get used in sysfs anyway, and the old name should be going away.
>>
> 
> This is certainly going to change user interface change, and I thought we 
> should not change the user interface irrespective of whether it is DT or 
> non-DT.
> Few points, which I do care about, are,
> 
> 1. request_irq():
>    For the driver if I am using dev_name(dev) as for the 3rd argument, which 
>    will now different with DT support - brings change in user interface.
> 
>    Non-DT:
>     #cat /proc/interrupts
>                CPU0
>     52:          0      INTC  xxx0
>     55:          0      INTC  xxx1
> 
>    DT:
>     #cat /proc/interrupts
>                CPU0
>     52:          0      INTC  481cc000.xxx
>     55:          0      INTC  481d0000.xxx
> 
> 
> 2. SYSFS:
>    For example,
>    Without auxdata:
>      /sys/devices/481cc000.xxx/
>      /sys/devices/481d0000.xxx/
> 
>    With auxdata:
>      /sys/devices/xxx.0/
>      /sys/devices/xxx.1/
> 
>    From user perspective, I still would not want to change the existing 
>    naming convention.
> 
> 3. Certainly I don't want user to go back to spec everytime to find out 
>    which address is mapped to which instance of module.
>    Also, in addition to that, in case of SoC's like AM33xx (for that matter, 
>    any embedded SoC) we have different domains and modules are placed in 
>    different domains as per use-cases.
>    For example, in this case, can0 is places in wakeup domain and can1 is 
>    placed in per-domain. Some boards might use only one instance or some 
>    board might use both of them.
> 
>    I still would like to keep instance number wherever user interface comes 
>    into picture and populate base address as an additional info to user.
> 
> 
> I may be missing something, may be I am not able to see the bigger picture 
> here.
> 
> Grant/Benoit, May be you can conform and put your opinion on this.
> 

Rob,

I think we do not have any conclusion on this, so here should I assume
that I should just simply add another clk node entry in clock-tree, like
below -

CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),



Thanks,
Vaibhav


From josephl at nvidia.com  Wed Aug 15 05:22:28 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:28 +0800
Subject: [PATCH V2 0/6] ARM: tegra: add CPU hotplug support
Message-ID: <1345022554-26292-1-git-send-email-josephl@nvidia.com>

This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.

The first 3 patches make the CPU clock and reset control be a module and
the abstraction APIs for TegraXX SoCs. And clean up some codes for later
usage. Then add CPU hotplug support for Tegra20 and Tegra30.

Verified on Seaboard(Tegra20) and Cardhu(Tegra30)

V2:
* add one more patch for enable HOTPLUG_CPU [6/6]
* move all the SoC specific CPU shutdown code into platform_cpu_die [4/6]

Joseph Lo (6):
  ARM: tegra: introduce tegra_cpu_car_ops structures
  ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
  ARM: tegra: clean up the common assembly macros into sleep.h
  ARM: tegra30: add CPU hotplug support
  ARM: tegra20: add CPU hotplug support
  ARM: tegra: defconfig: enable HOTPLUG_CPU

 arch/arm/configs/tegra_defconfig          |    1 +
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/common.c              |    3 +
 arch/arm/mach-tegra/headsmp.S             |    6 +-
 arch/arm/mach-tegra/hotplug.c             |  118 ++++++++---------------------
 arch/arm/mach-tegra/platsmp.c             |   29 +------
 arch/arm/mach-tegra/sleep-t20.S           |   82 ++++++++++++++++++++
 arch/arm/mach-tegra/sleep-t30.S           |  107 ++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.S               |   33 +--------
 arch/arm/mach-tegra/sleep.h               |   80 +++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 +++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++
 16 files changed, 552 insertions(+), 147 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S
 create mode 100644 arch/arm/mach-tegra/sleep.h
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h



From josephl at nvidia.com  Wed Aug 15 05:22:29 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:29 +0800
Subject: [PATCH V2 1/6] ARM: tegra: introduce tegra_cpu_car_ops structures
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-2-git-send-email-josephl@nvidia.com>

The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 ++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++++++++++
 6 files changed, 238 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 632133f..fd82085 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -31,6 +31,10 @@
 
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 
 /*
  * Locking:
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index a1e0f8a..b073396 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -33,6 +33,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
 
 #define RST_DEVICES			0x004
 #define RST_DEVICES_SET			0x300
@@ -152,6 +153,14 @@
 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT	16
 #define PMC_BLINK_TIMER_DATA_OFF_MASK	0xffff
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 
@@ -1524,3 +1533,64 @@ struct clk_ops tegra_cdev_clk_ops = {
 	.disable = tegra20_cdev_clk_disable,
 	.recalc_rate = tegra20_cdev_recalc_rate,
 };
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg & ~CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	barrier();
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+	.wait_for_reset	= tegra20_wait_cpu_in_reset,
+	.put_in_reset	= tegra20_put_cpu_in_reset,
+	.out_of_reset	= tegra20_cpu_out_of_reset,
+	.enable_clock	= tegra20_enable_cpu_clock,
+	.disable_clock	= tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index b5c518e..56552f9 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "tegra2_emc.h"
 #include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
 
 /* Clock definitions */
 
@@ -1110,4 +1111,5 @@ void __init tegra2_init_clocks(void)
 	}
 
 	init_audio_sync_clock_mux();
+	tegra20_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index a9fa8ea..b2d0864 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -35,6 +35,7 @@
 
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY		100
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR	0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -2221,3 +2232,64 @@ struct clk_ops tegra_cml_clk_ops = {
 struct clk_ops tegra_pciex_clk_ops = {
 	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
+
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra30_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra30_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra30_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	writel(CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	reg = readl(reg_clk_base +
+		    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
+
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
+
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+	.wait_for_reset	= tegra30_wait_cpu_in_reset,
+	.put_in_reset	= tegra30_put_cpu_in_reset,
+	.out_of_reset	= tegra30_cpu_out_of_reset,
+	.enable_clock	= tegra30_enable_cpu_clock,
+	.disable_clock	= tegra30_disable_cpu_clock,
+};
+
+void __init tegra30_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index c924240..8252f88 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -32,6 +32,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
 
 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,		\
 		   _parent_names, _parents, _parent)		\
@@ -1367,4 +1368,6 @@ void __init tegra30_init_clocks(void)
 
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
 		tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+	tegra30_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 0000000..30d063a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *	keep waiting until the CPU in reset state
+ * put_in_reset:
+ *	put the CPU in reset state
+ * out_of_reset:
+ *	release the CPU from reset state
+ * enable_clock:
+ *	CPU clock un-gate
+ * disable_clock:
+ *	CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+	void (*wait_for_reset)(u32 cpu);
+	void (*put_in_reset)(u32 cpu);
+	void (*out_of_reset)(u32 cpu);
+	void (*enable_clock)(u32 cpu);
+	void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+		return;
+
+	tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+		return;
+
+	tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+		return;
+
+	tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+		return;
+
+	tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+		return;
+
+	tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
-- 
1.7.0.4



From josephl at nvidia.com  Wed Aug 15 05:22:30 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:30 +0800
Subject: [PATCH V2 2/6] ARM: tegra: replace the CPU CAR access code by
 tegra_cpu_car_ops
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-3-git-send-email-josephl@nvidia.com>

Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/platsmp.c |   29 +++++------------------------
 1 files changed, 5 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208db..96ed171 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
 
 extern void tegra_secondary_startup(void);
 
@@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
 	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu)	(0x1<<(8+cpu))
-#define CPU_RESET(cpu)	(0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
-
 	/* Enable the CPU clock. */
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	barrier();
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	tegra_enable_cpu_clock(cpu);
 
 	/* Clear flow controller CSR. */
 	flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
 	int ret, pwrgateid;
 	unsigned long timeout;
 
@@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
 	}
 
 	/* CPU partition is powered. Enable the CPU clock. */
-	writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	tegra_enable_cpu_clock(cpu);
 	udelay(10);
 
 	/* Remove I/O clamps. */
@@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * via the flow controller). This will have no effect on first boot
 	 * of the CPU since it should already be in reset.
 	 */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-	dmb();
+	tegra_put_cpu_in_reset(cpu);
 
 	/*
 	 * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		goto done;
 
 	/* Take the CPU out of reset. */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-	wmb();
+	tegra_cpu_out_of_reset(cpu);
 done:
 	return status;
 }
-- 
1.7.0.4



From josephl at nvidia.com  Wed Aug 15 05:22:31 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:31 +0800
Subject: [PATCH V2 3/6] ARM: tegra: clean up the common assembly macros into
 sleep.h
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-4-git-send-email-josephl@nvidia.com>

There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/headsmp.S |    6 +---
 arch/arm/mach-tegra/sleep.S   |   33 +-----------------------
 arch/arm/mach-tegra/sleep.h   |   56 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep.h

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c..6addc78 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 
 #define APB_MISC_GP_HIDREV	0x804
 #define PMC_SCRATCH41	0x140
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
 
-	.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-	.endm
-
         .section ".text.head", "ax"
 	__CPUINIT
 
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156..ea81554 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
+#include "sleep.h"
 
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-					+ IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x14
-	moveq	\rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x18
-	moveq	\rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-	mrc	p15, 0, \rd, c0, c0, 5
-	and	\rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 0000000..d0c7a8b
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x14
+	moveq	\rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x18
+	moveq	\rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+	mrc	p15, 0, \rd, c0, c0, 5
+	and	\rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+	movw	\reg, #:lower16:\val
+	movt	\reg, #:upper16:\val
+.endm
+#endif
+#endif
-- 
1.7.0.4



From josephl at nvidia.com  Wed Aug 15 05:22:33 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:33 +0800
Subject: [PATCH V2 5/6] ARM: tegra20: add CPU hotplug support
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-6-git-send-email-josephl@nvidia.com>

Hotplug function put CPU in offline or online mode at runtime.
When the CPU been put into offline, it was been clock gated. The
offline CPU can be power gated, when the remaining CPU goes into
LP2.

Based on the worked by:
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    1 +
 arch/arm/mach-tegra/hotplug.c   |    8 ++++
 arch/arm/mach-tegra/sleep-t20.S |   82 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |    3 +
 5 files changed, 95 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 211e279..959a429 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0652056..0560538 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -136,6 +136,7 @@ void __init tegra20_init_early(void)
 	tegra_init_cache(0x331, 0x441);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index be92d4c..d02a354 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -56,6 +56,14 @@ int platform_cpu_disable(unsigned int cpu)
 	return cpu == 0 ? -EPERM : 0;
 }
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 extern void tegra30_hotplug_shutdown(void);
 void __init tegra30_hotplug_init(void)
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 0000000..a36ae41
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross at android.com>
+ *         Gary King <gking at nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Put this CPU down */
+	cpu_id	r0
+	bl	tegra20_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+	cmp	r0, #0
+	moveq	pc, lr			@ must not be called for CPU 0
+
+	cpu_to_halt_reg r1, r0
+	ldr	r3, =TEGRA_FLOW_CTRL_VIRT
+	mov	r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+	str	r2, [r3, r1]		@ put flow controller in wait event mode
+	ldr	r2, [r3, r1]
+	isb
+	dsb
+	movw	r1, 0x1011
+	mov	r1, r1, lsl r0
+	ldr	r3, =TEGRA_CLK_RESET_VIRT
+	str	r1, [r3, #0x340]	@ put slave CPU in reset
+	isb
+	dsb
+	cpu_id	r3
+	cmp	r3, r0
+	beq	.
+	mov	pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2ad9b6d..42236e1 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -23,6 +23,8 @@
 					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
 
 #ifdef __ASSEMBLY__
 /* returns the offset of the flow controller halt register for a cpu */
@@ -71,6 +73,7 @@
 .endm
 #else
 
+void tegra20_hotplug_init(void);
 void tegra30_hotplug_init(void);
 
 #endif
-- 
1.7.0.4



From josephl at nvidia.com  Wed Aug 15 05:22:32 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:32 +0800
Subject: [PATCH V2 4/6] ARM: tegra30: add CPU hotplug support
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-5-git-send-email-josephl@nvidia.com>

Hotplug function put CPUs in offline or online state at runtime.
When the CPU been put in the offline state, it was been clock and
power gated. Except primary CPU other CPUs can be hotplugged.

Based on the work by:
Scott Williams <scwilliams at nvidia.com>
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    2 +
 arch/arm/mach-tegra/hotplug.c   |  110 +++++++++------------------------------
 arch/arm/mach-tegra/sleep-t30.S |  107 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |   21 +++++++
 5 files changed, 155 insertions(+), 86 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 060592a..211e279 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f3654f8..0652056 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -147,6 +148,7 @@ void __init tegra30_init_early(void)
 	tegra_init_cache(0x441, 0x551);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra30_hotplug_init();
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9dd..be92d4c 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,91 +1,23 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
 
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
+#include "sleep.h"
+#include "tegra_cpu_car.h"
 
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
-
-		/*if (pen_release == cpu) {*/
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		/*}*/
-
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
+static void (*tegra_hotplug_shutdown)(void);
 
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -99,22 +31,20 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-	int spurious = 0;
+	cpu = cpu_logical_map(cpu);
 
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
+	/* Flush the L1 data cache. */
+	flush_cache_all();
 
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
+	/* Shut down the current CPU. */
+	tegra_hotplug_shutdown();
+
+	/* Clock gate the CPU */
+	tegra_wait_cpu_in_reset(cpu);
+	tegra_disable_cpu_clock(cpu);
 
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+	/* Should never return here. */
+	BUG();
 }
 
 int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,11 @@ int platform_cpu_disable(unsigned int cpu)
 	 */
 	return cpu == 0 ? -EPERM : 0;
 }
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 0000000..777d9ce
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Powergate this CPU */
+	mov	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	bl	tegra30_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+	cpu_id	r3
+	cmp	r3, #0
+	moveq	pc, lr		@ Must never be called for CPU 0
+
+	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
+	cpu_to_csr_reg r1, r3
+	add	r1, r1, r12	@ virtual CSR address for this CPU
+	cpu_to_halt_reg r2, r3
+	add	r2, r2, r12	@ virtual HALT_EVENTS address for this CPU
+
+	/*
+	 * Clear this CPU's "event" and "interrupt" flags and power gate
+	 * it when halting but not before it is in the "WFE" state.
+	 */
+	movw	r12, \
+		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+		FLOW_CTRL_CSR_ENABLE
+	mov	r4, #(1 << 4)
+	orr	r12, r12, r4, lsl r3
+	str	r12, [r1]
+
+	/* Halt this CPU. */
+	mov	r3, #0x400
+delay_1:
+	subs	r3, r3, #1			@ delay as a part of wfe war.
+	bge	delay_1;
+	cpsid	a				@ disable imprecise aborts.
+	ldr	r3, [r1]			@ read CSR
+	str	r3, [r1]			@ clear CSR
+	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	str	r3, [r2]
+	ldr	r0, [r2]
+	b	wfe_war
+
+__cpu_reset_again:
+	dsb
+	.align 5
+	wfe					@ CPU should be power gated here
+wfe_war:
+	b	__cpu_reset_again
+
+	/*
+	 * 38 nop's, which fills reset of wfe cache line and
+	 * 4 more cachelines with nop
+	 */
+	.rept 38
+	nop
+	.endr
+	b	.				@ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index d0c7a8b..2ad9b6d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -19,6 +19,8 @@
 
 #include <mach/iomap.h>
 
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
 
@@ -52,5 +54,24 @@
 	movw	\reg, #:lower16:\val
 	movt	\reg, #:upper16:\val
 .endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
+	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	isb
+	cpu_id	\tmp1
+	mov	\tmp1, \tmp1, lsl #2
+	mov	\tmp2, #0xf
+	mov	\tmp2, \tmp2, lsl \tmp1
+	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
+	dsb
+.endm
+#else
+
+void tegra30_hotplug_init(void);
+
 #endif
 #endif
-- 
1.7.0.4



From josephl at nvidia.com  Wed Aug 15 05:22:34 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Wed, 15 Aug 2012 17:22:34 +0800
Subject: [PATCH V2 6/6] ARM: tegra: defconfig: enable HOTPLUG_CPU
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345022554-26292-7-git-send-email-josephl@nvidia.com>

Enable HOTPLUG_CPU after the SoC specific code to hotplug a CPU
been merged.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/configs/tegra_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db22453..e16fd61 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -31,6 +31,7 @@ CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
+CONFIG_HOTPLUG_CPU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-- 
1.7.0.4



From b32955 at freescale.com  Wed Aug 15 05:12:10 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 15 Aug 2012 17:12:10 +0800
Subject: [PATCH] kconfig: remove CONFIG_MTD_NAND_VERIFY_WRITE
Message-ID: <1345021930-5033-1-git-send-email-b32955@freescale.com>

Just as Artem suggested:

"Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature."

So kill MTD_NAND_VERIFY_WRITE entirely. Please see the patch:
http://lists.infradead.org/pipermail/linux-mtd/2012-August/043189.html
  
This patch removes the CONFIG_MTD_NAND_VERIFY_WRITE in the defconfigs.


Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 arch/arm/configs/bcmring_defconfig              |    1 -
 arch/arm/configs/cam60_defconfig                |    1 -
 arch/arm/configs/corgi_defconfig                |    1 -
 arch/arm/configs/ep93xx_defconfig               |    1 -
 arch/arm/configs/mini2440_defconfig             |    1 -
 arch/arm/configs/mv78xx0_defconfig              |    1 -
 arch/arm/configs/nhk8815_defconfig              |    1 -
 arch/arm/configs/orion5x_defconfig              |    1 -
 arch/arm/configs/pxa3xx_defconfig               |    1 -
 arch/arm/configs/spitz_defconfig                |    1 -
 arch/blackfin/configs/BF561-ACVILON_defconfig   |    1 -
 arch/mips/configs/rb532_defconfig               |    1 -
 arch/powerpc/configs/83xx/mpc8313_rdb_defconfig |    1 -
 arch/powerpc/configs/83xx/mpc8315_rdb_defconfig |    1 -
 arch/powerpc/configs/mpc83xx_defconfig          |    1 -
 15 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
index 9e6a8fe..6c389d9 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -44,7 +44,6 @@ CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_BCM_UMI=y
 CONFIG_MTD_NAND_BCM_UMI_HWCS=y
 # CONFIG_MISC_DEVICES is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
index cedc92e..1457971 100644
--- a/arch/arm/configs/cam60_defconfig
+++ b/arch/arm/configs/cam60_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PLATRAM=m
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e53c475..4b8a25d 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -97,7 +97,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_SHARPSL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_IDE=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 8e97b2f..806005a 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -61,7 +61,6 @@ CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_SCSI=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 082175c..00630e6 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -102,7 +102,6 @@ CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_S3C2410=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_LPDDR=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 7305ebd..1f08219 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -49,7 +49,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_SCSI_PROC_FS is not set
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index bf123c5..240b25e 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -57,7 +57,6 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_NOMADIK=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index a288d70..cd5e6ba 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -72,7 +72,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 1677a06..60e3138 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -36,7 +36,6 @@ CONFIG_MTD_CONCAT=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PXA3xx=y
 CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
 CONFIG_MTD_ONENAND=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index 7015827..df77931 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -94,7 +94,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_SHARPSL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_IDE=y
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
index 0fdc4ec..9198837 100644
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ b/arch/blackfin/configs/BF561-ACVILON_defconfig
@@ -57,7 +57,6 @@ CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_PHRAM=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index 55902d9..b85b121 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -119,7 +119,6 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_ATA=y
 # CONFIG_ATA_VERBOSE_ERROR is not set
diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index 126ef1b..e4ad2e2 100644
--- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -38,7 +38,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index abcf00a..34ff568 100644
--- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
@@ -37,7 +37,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 5aac9a8..f6fc66c 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -52,7 +52,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 15 05:25:40 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 15 Aug 2012 17:25:40 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815075117.GL2232@pengutronix.de>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
Message-ID: <20120815092539.GH19681@shlinux2.ap.freescale.net>

On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
> Hello,
> 
> On Wed, Aug 15, 2012 at 02:55:27PM +0800, Dong Aisheng wrote:
> > On Wed, Aug 15, 2012 at 07:44:36AM +0200, Uwe Kleine-K?nig wrote:
> > > Hello,
> > > 
> > > (Cc += devicetree-discuss at lists.ozlabs.org)
> > > 
> > > On Wed, Aug 15, 2012 at 11:59:18AM +0800, Dong Aisheng wrote:
> > > > On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
> > > > > On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
> > > > >> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
> > > > >>> I have a minor nit; while renumbering the pinctrl definitions is
> > > > >>> laudable and device trees can match, there are 16 other pin controls
> > > > >>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
> > > > >>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
> > > > >>> (pin_id*4)).
> > > > >>
> > > > >> What do you mean of this value calculated?
> > > > >
> > > > > Well, it just seems the datasheet has been read from the point of view
> > > > > of the SW_CTRL settings (pad pullups, drive strength etc.) to define
> > > > > the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
> > > > > I mistyped) has been entered as an enum into this list. Then a table
> > > > > has been generated using these enums to supply a pin id. Then this pin
> > > > > id is not relevant anymore; it actually gets referenced by it's
> > > > > *offset into the table*.
> > > > >
> > > > Not exactly, probably.
> > > > Basically we follow the mux reigster offset to define pin id, however,
> > > > there're also some pads may not have mux function but only config
> > > > which also has a pin id
> > > > and vice versa.
> > > > Those pins are not ordered by it's mux regsiter offset.
> > > > 
> > > > Actually I did not manually search all those pins, instead, i just
> > > > using the exist ones:
> > > > arch/arm/plat-mxc/include/mach/iomux-mx51.h
> > > > Since this exist headfile already covers this case.
> > > > 
> > > > > In this case, basically the code misses a few pins which have ALT
> > > > > settings but perhaps not always the ability to change pad control -
> > > > > EIM_DA5 to 15 are a good example.
> > > > >
> > > > As i said, we already defined those pin ids.
> > > > 
> > > > > Probably better would be to define the binding almost exactly as it
> > > > > was done in the old method; iomux_v3_cfg_t took into account the three
> > > > > register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
> > > > > and the three values to be put into those registers.
> > > > >
> > > > > This has been reduced down in pinctrl to what I find quite strange,
> > > > > which is a completely arbitrary pin "id" mapping, which indirectly
> > > > > references an entry in a table by index which is why pin 1 as a start
> > > > > looks odd.
> > > > >
> > > > Start with pin 1 is a bug which caused by my mistake during the early
> > > > data conversion.
> > > > 
> > > > > If the binding is entirely i.MX-specific or even i.MX51-specific then
> > > > > why not define the pins in the device tree the "old" iomux_v3_cfg_t
> > > > > way, which is the way they are in the table of imx_pin_regs;
> > > > >
> > > > >       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
> > > > > MX51_PAD_EIM_D16__AUD4_RXFS */
> > > > >
> > > > > 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
> > > > > 0x000 is the IPP reg, and 0 the IPP value.
> > > > >
> > > > > So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
> > > > > mode/sion, IPP, select - in that order) would be a valid pin
> > > > > definition and require no table. Sure, the offsets are device specific
> > > > > but then the arbitrary numbering is too.
> > > > > This way old iomux controls
> > > > > can be re-derived for people who use the old method in old kernels, or
> > > > > use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
> > > > > porting the Efika to it on MX5 for U-Boot right now). Also that huge
> > > > > table goes away - it can be built at runtime, along with the
> > > > > PAD_NAME__ALT_MODE_NAME description.
> > > > >
> > > > I can't agree this is better than the exist one now.
> > > > It's hard to use in device tree.
> > > > And how would you parse the pin id from this data array?
> > > I admit I didn't follow completely the calculation suggestion by Matt,
> > > but I think in general he has a point. This is more or less what I
> > > thought when I built the imx35 pinctrl driver.
> > > 
> > > With the current approach (i.e. put the pinfuncs in some order that
> > > seems sensible today and then referencing them by index according to
> > > that ordering) you really get into troubles if you have to add a new
> > > function. You have to add it to the end to not break existing device
> > > trees and so the ordering is broken.
> > > 
> > Actually, we do not mean to maintain the ordering in driver.
> > It just needs to be align with the pin func ids definitions in binding
> > doc. So the ordering broken in driver is not an issue, it just looks
> > not so better if we really have to add a new pin function to the end
> > due to mistake but this does not break anything to work.
> Well, if you add a function between say current function 11 and 12 all
> device trees need fixing, i.e. increase all function ids >= 12 by one.
> You obviously cannot fix out-of-tree users and even fixing the in-tree
> users is ugly.
>  
For such case, we should add it to the end since the exist ids are already
taken. It will not break any user.

> > > Also "11" has no obvious relation to MX35_PAD_COMPARE__SDMA_EXTDMA_2
> > > other than a match if you grep over the binding docs (or the driver).
> > > While "0x32c, 0x008, 7, 0x0, 0" is longer and looks more ugly the
> > > mapping is obvious and so IMHO preferable.
> > > 
> > Also, don't you think this is hard to use for devicetree?
> Not harder than the current approach. Obviously macro support would be
> nice, but this applies to both approaches.
> 
> > And we need to reference datasheet to fill these values.
> I'd list the explicit values in the binding docs as the indexes are
> documented there now. So the difference for a device-tree writer is just
> the content that is copy-and-pasted.
> 
> > I just keep using as the old way at best and i remember Sascha also suggested
> > before that we don't want to lose using the macro way as
> > MX35_PAD_COMPARE__SDMA_EXTDMA_2 to make easy use.
> > In the future, we will switch to macro when dt supports.
> > For the way "0x32c, 0x008, 7, 0x0, 0", it's very unconveniently to use macro.
> That is just
> 
> 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
> 
> vs.
> 
> 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0
> 
> isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
> different story.)
> 
Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
Grant,
Do you know if dt macro can support it?

Now I'm a bit intend to admit that we probably could do like that if it supports.
The benefit i see is that it could save much code lines in driver while having
no using experience downgrade.

The left question is that how do we get the pin id from this kind of format data
(0x32c, 0x008, 7, 0x0, 0), probably one way may be:
For normal pads and NO_CONFIG pads, we could get it via:
mux_reg_offset / 4
for NO_MUX pads but have CONFIG pads, we may get it via:
mux_reg_offset / 4 + PIN_NO_MUX_ID_BASE + config_reg_offset /4
That may fix getting pin id issue from dt.

Another known issue is that via this way, that means the pinctrl subsystem
can only see the using pads, this is a bit not align with the pinctrl
subsystem design. No sure if Linus would like to see it.

Regards
Dong Aisheng



From s.trumtrar at pengutronix.de  Wed Aug 15 06:00:16 2012
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed, 15 Aug 2012 12:00:16 +0200
Subject: [PATCH] ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path
Message-ID: <1345024816-6368-1-git-send-email-s.trumtrar@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

The ldb_di[01]_podf is implemented as a clk-divider that
divides by 1 or 2. In reality, the ldb_di[01]_ipu_div
dividers divide by either 3.5 or 7. Adding a fixed factor
of 1/3.5 fixes their children's clock rates.

This should probably be converted to rate table based dividers,
once available.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx6q.c |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520..4233d9e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -152,7 +152,7 @@ enum mx6q_clks {
 	ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
 	usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
 	pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
-	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
+	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
 	clk_max
 };
 
@@ -288,8 +288,10 @@ int __init mx6q_clocks_init(void)
 	clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
 	clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
 	clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-	clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_sel",       base + 0x20, 10, 1);
-	clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_sel",       base + 0x20, 11, 1);
+	clk[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+	clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_div_3_5",       base + 0x20, 10, 1);
+	clk[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+	clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_div_3_5",   base + 0x20, 11, 1);
 	clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
 	clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
 	clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
-- 
1.7.10.4



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:40 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:40 +0200
Subject: [PATCH v5 0/8] ARM: OMAP2+: PM: introduce the power domains
 functional states
Message-ID: <1345024968-28951-1-git-send-email-j-pihet@ti.com>

Here is a re-spin after some comments and suggestions after review.

Implement the functional states for the power domains:
- unify the API to use the functional states. pwrdm_set_next_fpwrst
  now is the function to control the power domains power and logic
  states,
- reorganize the powerdomain API in internal and external parts,
  in powerdomain.h [1]
- protect the power domain state change by a lock in
  pwrdm_set_next_fpwrst,
- introduce the functional states for power domains power states and
  logic power states, and the conversion functions between the
  functional and internal states,
- program the logic power state of power domains from the functional
  states, in pwrdm_set_next_fpwrst
- convert the OMAP2/3/4 PM code to use the updated API,
- provide the power domains statistics by functional states,
- provide ftrace tracepoints with the functional state,
- provide error logs in critical code, which makes the development
  easier.

Note: [1] the physical split of internal and external APIs into
      different header files is not part of this series, it comes as
      a separate patch set.


Based on mainline kernel 3.6.0-rc1.

Tested on OMAP3 Beagleboard, with suspend and cpuidle in RET and
OFF modes.


History:
 v5:
 - complete rework after review and suggestions,
 - improved locking on next state read/write; spinlock instead of mutex
 - added more error logging in critical code,

 v4:
 - reworked the code after internal review and testing with OMAP3&4 device
   OFF,
 - fixed the tracepoints generation code,
 - introduce a function that returns power domains achievable functional
   states, in order to return a valid state for power domains that only
   support some of the power states. Although it has been tested OK the
   code is in RFC state.

 v3:
 - fix a bug in OMAP3 cpuidle which prevented the IO wake-ups in PER

 v2:
 - add the logic power states,
 - provide the power domains statistics by functional states

 v1:
 - initial implementation, in RFC state


Jean Pihet (7):
  ARM: OMAP2+: PM: introduce power domains functional states
  ARM: OMAP2+: PM: introduce power domains achievable functional states
  ARM: OMAP2+: PM: add a lock to protect the powerdomains next state
  ARM: OMAP2+: PM: use the functional power states API
  ARM: OMAP2+: PM: use power domain functional state in stats counters
  ARM: OMAP2+: PM debug: trace the functional power domains states
  ARM: OMAP2+: PM: reorganize the powerdomain API in public and private
    parts

Nishanth Menon (1):
  ARM: OMAP2+: powerdomain: add error logs

 arch/arm/mach-omap2/cpuidle34xx.c          |   58 ++--
 arch/arm/mach-omap2/cpuidle44xx.c          |   24 +-
 arch/arm/mach-omap2/omap-hotplug.c         |    2 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c  |   39 ++--
 arch/arm/mach-omap2/pm-debug.c             |   15 +-
 arch/arm/mach-omap2/pm24xx.c               |   14 +-
 arch/arm/mach-omap2/pm34xx.c               |   79 +++---
 arch/arm/mach-omap2/pm44xx.c               |   24 +-
 arch/arm/mach-omap2/powerdomain-common.c   |   99 ++++++
 arch/arm/mach-omap2/powerdomain.c          |  456 +++++++++++++++++++++++++---
 arch/arm/mach-omap2/powerdomain.h          |  152 ++++++---
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c |    6 +
 arch/arm/mach-omap2/powerdomain44xx.c      |    3 +
 13 files changed, 753 insertions(+), 218 deletions(-)

-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:43 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:43 +0200
Subject: [PATCH 3/8] ARM: OMAP2+: PM: add a lock to protect the powerdomains
 next state
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-4-git-send-email-j-pihet@ti.com>

pwrdm_set_next_fpwrst and pwrdm_read_next_fpwrst are intented
to be the only API to program and request the next state of a power
domain.
This patch protects the power domain next state settings and structs
from concurrent accesses by the use of a lock.

A spinlock is used since pwrdm_set_next_fpwrst and
pwrdm_read_next_fpwrst can be called from atomic context
(.i.e) either from cpuidle path or suspend path.

[ambresh at ti.com: reported the atomic context issue and suggested
to replace the mutex with a spinlock]

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Reported-by: Ambresh K <ambresh at ti.com>
---
 arch/arm/mach-omap2/powerdomain.c |   36 +++++++++++++++++++++++++++++++-----
 arch/arm/mach-omap2/powerdomain.h |    3 +++
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 3a1f56c..a8f7a81 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
 	INIT_LIST_HEAD(&pwrdm->voltdm_node);
 	voltdm_add_pwrdm(voltdm, pwrdm);
 
+	spin_lock_init(&pwrdm->lock);
 	list_add(&pwrdm->node, &pwrdm_list);
 
 	/* Initialize the powerdomain's state counter */
@@ -601,6 +602,22 @@ int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
 }
 
 /**
+ * _pwrdm_read_next_fpwrst - get next powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get power state
+ *
+ * Return the powerdomain @pwrdm's next functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns
+ * the next power state upon success.
+ */
+int _pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
+{
+	int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+	int next_logic = pwrdm_read_logic_retst(pwrdm);
+
+	return pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+}
+
+/**
  * pwrdm_get_achievable_fpwrst() - Provide achievable functional state
  * @pwrdm: struct powerdomain * to set
  * @fpwrst: minimum functional state we would like to hit
@@ -670,6 +687,7 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 	int sleep_switch = -1, ret = 0, hwsup = 0;
 	int new_fpwrst, next_fpwrst, pwrst, logic;
 	u8 curr_pwrst;
+	unsigned long flags;
 
 	if (!pwrdm || IS_ERR(pwrdm)) {
 		pr_debug("%s: invalid params: pwrdm=%p\n", __func__, pwrdm);
@@ -678,13 +696,15 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 
 	pr_debug("%s(%s, fpwrst=%0x)\n", __func__, pwrdm->name, fpwrst);
 
+	spin_lock_irqsave(&pwrdm->lock, flags);
+
 	new_fpwrst = pwrdm_get_achievable_fpwrst(pwrdm, fpwrst);
 	pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, new_fpwrst);
 	logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, new_fpwrst);
 
-	next_fpwrst = pwrdm_read_next_fpwrst(pwrdm);
+	next_fpwrst = _pwrdm_read_next_fpwrst(pwrdm);
 	if (new_fpwrst == next_fpwrst)
-		return ret;
+		goto out;
 
 	curr_pwrst = pwrdm_read_pwrst(pwrdm);
 	if (curr_pwrst < PWRDM_POWER_ON) {
@@ -732,6 +752,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 		break;
 	}
 
+out:
+	spin_unlock_irqrestore(&pwrdm->lock, flags);
 	return ret;
 }
 
@@ -801,10 +823,14 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
 {
-	int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
-	int next_logic = pwrdm_read_logic_retst(pwrdm);
+	int ret;
+	unsigned long flags;
 
-	return pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+	spin_lock_irqsave(&pwrdm->lock, flags);
+	ret = _pwrdm_read_next_fpwrst(pwrdm);
+	spin_unlock_irqrestore(&pwrdm->lock, flags);
+
+	return ret;
 }
 
 /**
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 45c449d..23b9da9 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -17,6 +17,7 @@
 #include <linux/types.h>
 #include <linux/list.h>
 
+#include <linux/spinlock.h>
 #include <linux/atomic.h>
 
 #include <plat/cpu.h>
@@ -109,6 +110,7 @@ struct powerdomain;
  * @pwrdm_clkdms: Clockdomains in this powerdomain
  * @node: list_head linking all powerdomains
  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @lock: powerdomain next state registers protection lock
  * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
  * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
  * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
@@ -142,6 +144,7 @@ struct powerdomain {
 	struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
 	struct list_head node;
 	struct list_head voltdm_node;
+	spinlock_t lock;
 	int state;
 	unsigned state_counter[PWRDM_MAX_PWRSTS];
 	unsigned ret_logic_off_counter;
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:42 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:42 +0200
Subject: [PATCH 2/8] ARM: OMAP2+: PM: introduce power domains achievable
 functional states
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-3-git-send-email-j-pihet@ti.com>

Note: the patch is in RFC state because the state machine for setting
the next power domain states needs more discussion. Validated on OMAP3&4
with cpuidle and suspend/resume, though.

Power domains have varied capabilities. When attempting a low power
state such as OFF/RET, a specific min requested state may not be
supported on the power domain. This is because a combination
of system power states where the parent PD's state is not in line
with expectation can result in system instabilities.

This patch provides a function that returns the achievable functional
power state for a power domain and its use by pwrdm_set_next_fpwrst.
The achievable power state is first looked for in the lower power
states in order to maximize the power savings, then if not found
in the higher power states.

Inspired from Tero's work on OMAP4 device OFF support, generalized
to the functional power states and reworked as per Nishant's
suggestions.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Tero Kristo <t-kristo at ti.com>
Cc: Nishanth Menon <nm at ti.com>
---
 arch/arm/mach-omap2/powerdomain.c |  152 +++++++++++++++++++++++++++++++------
 arch/arm/mach-omap2/powerdomain.h |    1 +
 2 files changed, 130 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 6fc3c84..3a1f56c 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -199,6 +199,53 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 	return 0;
 }
 
+/**
+ * Search down then up for a valid state from a list of allowed states.
+ * Used by pwrdm_get_achievable_fpwrst to look for allowed power and
+ * logic states for a powerdomain.
+ *
+ * @pwrsts: list of allowed states, defined as a bitmask
+ * @pwrst: initial state to be used as a starting point
+ * @min: minimum allowed state
+ * @max: maximum allowed state
+ *
+ * Returns the matching allowed state.
+ */
+static inline int _match_pwrst(u32 pwrsts, int pwrst, int min, int max)
+{
+	int found = 1, new_pwrst = pwrst;
+
+	/*
+	 * Search lower: if the requested state is not supported
+	 * try the lower states, stopping at the minimum allowed
+	 * state
+	 */
+	while (!(pwrsts & (1 << new_pwrst))) {
+		if (new_pwrst <= min) {
+			found = 0;
+			break;
+		}
+		new_pwrst--;
+	}
+
+	/*
+	 * Search higher: if no lower state found fallback to the higher
+	 * states, stopping at the maximum allowed state
+	 */
+	if (!found) {
+		new_pwrst = pwrst;
+		while (!(pwrsts & (1 << new_pwrst))) {
+			if (new_pwrst >= max) {
+				new_pwrst = max;
+				break;
+			}
+			new_pwrst++;
+		}
+	}
+
+	return new_pwrst;
+}
+
 /* Public functions */
 
 /**
@@ -553,6 +600,57 @@ int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
 	return ret;
 }
 
+/**
+ * pwrdm_get_achievable_fpwrst() - Provide achievable functional state
+ * @pwrdm: struct powerdomain * to set
+ * @fpwrst: minimum functional state we would like to hit
+ * (one of the PWRDM_FUNC_* macros)
+ *
+ * Power domains have varied capabilities. When attempting a low power
+ * state such as OFF/RET, a specific min requested state may not be
+ * supported on the power domain. This is because a combination
+ * of system power states where the parent PD's state is not in line
+ * with expectation can result in system instabilities.
+ *
+ * The achievable power state is first looked for in the lower power
+ * states in order to maximize the power savings, then if not found
+ * in the higher power states.
+ *
+ * Returns the achievable functional power state, or -EINVAL in case of
+ * invalid parameters.
+ */
+int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+	int pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
+	int logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
+	int new_fpwrst, new_pwrst, new_logic;
+
+	if (!pwrdm || IS_ERR(pwrdm)) {
+		pr_debug("%s: invalid params: pwrdm=%p, fpwrst=%0x\n",
+			 __func__, pwrdm, fpwrst);
+		return -EINVAL;
+	}
+
+	if ((pwrst < 0) || (logic < 0)) {
+		pr_debug("%s: invalid params for pwrdm %s, fpwrst=%0x\n",
+			 __func__, pwrdm->name, fpwrst);
+		return PWRDM_FUNC_PWRST_ON;
+	}
+
+	new_pwrst = _match_pwrst(pwrdm->pwrsts, pwrst, PWRDM_POWER_OFF,
+				 PWRDM_POWER_ON);
+	new_logic = _match_pwrst(pwrdm->pwrsts_logic_ret, logic,
+				 PWRDM_LOGIC_MEM_PWRST_OFF,
+				 PWRDM_LOGIC_MEM_PWRST_RET);
+
+	new_fpwrst = pwrdm_pwrst_to_fpwrst(pwrdm, new_pwrst, new_logic);
+
+	pr_debug("%s(%s, fpwrst=%0x) returns %0x\n", __func__,
+		 pwrdm->name, fpwrst, new_fpwrst);
+
+	return new_fpwrst;
+}
+
 /* Types of sleep_switch used in pwrdm_set_next_fpwrst */
 #define FORCEWAKEUP_SWITCH	0
 #define LOWPOWERSTATE_SWITCH	1
@@ -562,34 +660,30 @@ int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
  * @pwrdm: struct powerdomain * to set
  * @fpwrst: power domain functional state, one of the PWRDM_FUNC_* macros
  *
- * This programs the pwrdm next functional state, sets the dependencies
- * and waits for the state to be applied.
+ * This looks for the more suited (or achievable) next functional power
+ * state, programs it, sets the dependencies and waits for the state to
+ * be applied to the power domain.
  */
 int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 			  enum pwrdm_func_state fpwrst)
 {
-	u8 curr_pwrst, next_pwrst;
-	int pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
-	int logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
 	int sleep_switch = -1, ret = 0, hwsup = 0;
+	int new_fpwrst, next_fpwrst, pwrst, logic;
+	u8 curr_pwrst;
 
-	if (!pwrdm || IS_ERR(pwrdm) || (pwrst < 0) || (logic < 0)) {
-		pr_debug("%s: invalid params: pwrdm=%p, fpwrst=%0x\n",
-			 __func__, pwrdm, fpwrst);
+	if (!pwrdm || IS_ERR(pwrdm)) {
+		pr_debug("%s: invalid params: pwrdm=%p\n", __func__, pwrdm);
 		return -EINVAL;
 	}
 
-	pr_debug("%s: set fpwrst %0x to pwrdm %s\n",
-		 __func__, fpwrst, pwrdm->name);
+	pr_debug("%s(%s, fpwrst=%0x)\n", __func__, pwrdm->name, fpwrst);
 
-	while (!(pwrdm->pwrsts & (1 << pwrst))) {
-		if (pwrst == PWRDM_POWER_OFF)
-			return ret;
-		pwrst--;
-	}
+	new_fpwrst = pwrdm_get_achievable_fpwrst(pwrdm, fpwrst);
+	pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, new_fpwrst);
+	logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, new_fpwrst);
 
-	next_pwrst = pwrdm_read_next_pwrst(pwrdm);
-	if (next_pwrst == pwrst)
+	next_fpwrst = pwrdm_read_next_fpwrst(pwrdm);
+	if (new_fpwrst == next_fpwrst)
 		return ret;
 
 	curr_pwrst = pwrdm_read_pwrst(pwrdm);
@@ -604,13 +698,25 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 		}
 	}
 
-	if (logic != pwrdm_read_logic_retst(pwrdm))
-		pwrdm_set_logic_retst(pwrdm, logic);
+	pr_debug("%s: set fpwrst %0x (%0x,%0x) to pwrdm %s\n",
+		 __func__, new_fpwrst, pwrst, logic, pwrdm->name);
+
+	/* Trace the pwrdm desired target state */
+	trace_power_domain_target(pwrdm->name, new_fpwrst,
+				  smp_processor_id());
+
+	/* Program next power state */
+	if (pwrst != pwrdm_fpwrst_to_pwrst(pwrdm, next_fpwrst)) {
+		ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
+		if (ret)
+			pr_err("%s: unable to set power state of powerdomain: %s\n",
+			       __func__, pwrdm->name);
+	}
 
-	ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
-	if (ret)
-		pr_err("%s: unable to set power state of powerdomain: %s\n",
-		       __func__, pwrdm->name);
+	/* Program RET logic state */
+	if ((pwrst == PWRDM_POWER_RET) &&
+	    (logic != pwrdm_fpwrst_to_logic_pwrst(pwrdm, next_fpwrst)))
+		pwrdm_set_logic_retst(pwrdm, logic);
 
 	switch (sleep_switch) {
 	case FORCEWAKEUP_SWITCH:
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index aa9f9b9..45c449d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -239,6 +239,7 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm);
 int pwrdm_read_fpwrst(struct powerdomain *pwrdm);
 int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst);
 int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
 int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
 int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic);
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:46 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:46 +0200
Subject: [PATCH 6/8] ARM: OMAP2+: PM debug: trace the functional power domains
 states
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-7-git-send-email-j-pihet@ti.com>

Trace the power domain transitions using the functional power states,
which include the power and logic states.

While at it, fix the trace in the case a power domain did not hit
the desired state, as reported by Paul Walmsley.

Reported-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/powerdomain.c |   15 +++++----------
 1 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 6b8580b..06a566b 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -144,7 +144,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
 static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 {
 
-	int prev, state, trace_state = 0;
+	int prev, next, state, trace_state;
 
 	if (pwrdm == NULL)
 		return -EINVAL;
@@ -165,10 +165,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 		 * If the power domain did not hit the desired state,
 		 * generate a trace event with both the desired and hit states
 		 */
-		if (state != prev) {
+		next = pwrdm_read_next_fpwrst(pwrdm);
+		if (next != prev) {
 			trace_state = (PWRDM_TRACE_STATES_FLAG |
-				       ((state & OMAP_POWERSTATE_MASK) << 8) |
-				       ((prev & OMAP_POWERSTATE_MASK) << 0));
+				       (next << 8) | (prev << 0));
 			trace_power_domain_target(pwrdm->name, trace_state,
 						  smp_processor_id());
 		}
@@ -781,13 +781,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
 		 pwrdm->name, pwrst);
 
-	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
-		/* Trace the pwrdm desired target state */
-		trace_power_domain_target(pwrdm->name, pwrst,
-					  smp_processor_id());
-		/* Program the pwrdm desired target state */
+	if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
 		ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
-	}
 
 	return ret;
 }
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:45 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:45 +0200
Subject: [PATCH 5/8] ARM: OMAP2+: PM: use power domain functional state in
 stats counters
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-6-git-send-email-j-pihet@ti.com>

The PM code uses some counters to keep track of the power domains
transitions, in order to provide the information to drivers (in
pwrdm_get_context_loss_count) and to expose the information to
sysfs for debug purpose.

This patch provides the information for each functional state.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/pm-debug.c    |   15 ++++++++-------
 arch/arm/mach-omap2/powerdomain.c |   12 ++++++------
 arch/arm/mach-omap2/powerdomain.h |    4 ++--
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd9..8eaa3f2 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -53,9 +53,10 @@ enum {
 	DEBUG_FILE_TIMERS,
 };
 
-static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
+static const char pwrdm_state_names[][PWRDM_MAX_FUNC_PWRSTS] = {
 	"OFF",
-	"RET",
+	"OSWR",
+	"CSWR",
 	"INA",
 	"ON"
 };
@@ -102,13 +103,13 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
 		strncmp(pwrdm->name, "dpll", 4) == 0)
 		return 0;
 
-	if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
+	if (pwrdm->state != pwrdm_read_fpwrst(pwrdm))
 		printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
-			pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
+		       pwrdm->name, pwrdm->state, pwrdm_read_fpwrst(pwrdm));
 
 	seq_printf(s, "%s (%s)", pwrdm->name,
 			pwrdm_state_names[pwrdm->state]);
-	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+	for (i = 0; i < PWRDM_MAX_FUNC_PWRSTS; i++)
 		seq_printf(s, ",%s:%d", pwrdm_state_names[i],
 			pwrdm->state_counter[i]);
 
@@ -137,7 +138,7 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
 	seq_printf(s, "%s (%s)", pwrdm->name,
 		pwrdm_state_names[pwrdm->state]);
 
-	for (i = 0; i < 4; i++)
+	for (i = 0; i < PWRDM_MAX_FUNC_PWRSTS; i++)
 		seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
 			pwrdm->state_timer[i]);
 
@@ -211,7 +212,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
 
 	t = sched_clock();
 
-	for (i = 0; i < 4; i++)
+	for (i = 0; i < PWRDM_MAX_FUNC_PWRSTS; i++)
 		pwrdm->state_timer[i] = 0;
 
 	pwrdm->timer = t;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1f9ed2c..6b8580b 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -106,7 +106,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
 	list_add(&pwrdm->node, &pwrdm_list);
 
 	/* Initialize the powerdomain's state counter */
-	for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+	for (i = 0; i < PWRDM_MAX_FUNC_PWRSTS; i++)
 		pwrdm->state_counter[i] = 0;
 
 	pwrdm->ret_logic_off_counter = 0;
@@ -114,7 +114,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
 		pwrdm->ret_mem_off_counter[i] = 0;
 
 	pwrdm_wait_transition(pwrdm);
-	pwrdm->state = pwrdm_read_pwrst(pwrdm);
+	pwrdm->state = pwrdm_read_fpwrst(pwrdm);
 	pwrdm->state_counter[pwrdm->state] = 1;
 
 	pr_debug("powerdomain: registered %s\n", pwrdm->name);
@@ -149,17 +149,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 	if (pwrdm == NULL)
 		return -EINVAL;
 
-	state = pwrdm_read_pwrst(pwrdm);
+	state = pwrdm_read_fpwrst(pwrdm);
 
 	switch (flag) {
 	case PWRDM_STATE_NOW:
 		prev = pwrdm->state;
 		break;
 	case PWRDM_STATE_PREV:
-		prev = pwrdm_read_prev_pwrst(pwrdm);
+		prev = pwrdm_read_prev_fpwrst(pwrdm);
 		if (pwrdm->state != prev)
 			pwrdm->state_counter[prev]++;
-		if (prev == PWRDM_POWER_RET)
+		if (prev == PWRDM_FUNC_PWRST_OSWR)
 			_update_logic_membank_counters(pwrdm);
 		/*
 		 * If the power domain did not hit the desired state,
@@ -1367,7 +1367,7 @@ int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
 		return -ENODEV;
 	}
 
-	count = pwrdm->state_counter[PWRDM_POWER_OFF];
+	count = pwrdm->state_counter[PWRDM_FUNC_PWRST_OFF];
 	count += pwrdm->ret_logic_off_counter;
 
 	for (i = 0; i < pwrdm->banks; i++)
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 23b9da9..df83c7c 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -146,7 +146,7 @@ struct powerdomain {
 	struct list_head voltdm_node;
 	spinlock_t lock;
 	int state;
-	unsigned state_counter[PWRDM_MAX_PWRSTS];
+	unsigned state_counter[PWRDM_MAX_FUNC_PWRSTS];
 	unsigned ret_logic_off_counter;
 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
 
@@ -160,7 +160,7 @@ struct powerdomain {
 
 #ifdef CONFIG_PM_DEBUG
 	s64 timer;
-	s64 state_timer[PWRDM_MAX_PWRSTS];
+	s64 state_timer[PWRDM_MAX_FUNC_PWRSTS];
 #endif
 };
 
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:41 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:41 +0200
Subject: [PATCH 1/8] ARM: OMAP2+: PM: introduce power domains functional states
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-2-git-send-email-j-pihet@ti.com>

Introduce the functional states for power domains, which include
the power states and the logic states.
This patch provides the API functions to set and read the power
domains settings and to convert between the functional (i.e. logical)
and the internal (or registers) values.
OMAP2, OMAP3 and OMAP4 platforms are using common conversion routines.

In the new API only the function pwrdm_set_next_fpwrst shall be used
to change a power domain target state, along with the associated
PWRDM_FUNC_* and PWRDM_LOGIC_* macros as the state parameters.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/powerdomain-common.c   |   99 ++++++++++++
 arch/arm/mach-omap2/powerdomain.c          |  225 +++++++++++++++++++++++++++-
 arch/arm/mach-omap2/powerdomain.h          |   45 +++++-
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c |    6 +
 arch/arm/mach-omap2/powerdomain44xx.c      |    3 +
 5 files changed, 368 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabf..a0fcee3 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -108,3 +108,102 @@ u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
 	return 0;
 }
 
+/**
+ * omap2_pwrdm_fpwrst_to_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains states.
+ * @struct powerdomain * to convert the values for
+ * @fpwrst: functional power state
+ *
+ * Returns the internal power state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+	int ret;
+
+	switch (fpwrst) {
+	case PWRDM_FUNC_PWRST_ON:
+		ret = PWRDM_POWER_ON;
+		break;
+	case PWRDM_FUNC_PWRST_INACTIVE:
+		ret = PWRDM_POWER_INACTIVE;
+		break;
+	case PWRDM_FUNC_PWRST_CSWR:
+	case PWRDM_FUNC_PWRST_OSWR:
+		ret = PWRDM_POWER_RET;
+		break;
+	case PWRDM_FUNC_PWRST_OFF:
+		ret = PWRDM_POWER_OFF;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/**
+ * omap2_pwrdm_fpwrst_to_logic_pwrst - Convert functional (i.e. logical) to
+ * internal (i.e. registers) values for the power domains logic states.
+ * @struct powerdomain * to convert the values for
+ * @pwrst: functional power state
+ *
+ * Returns the internal logic state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+	int ret;
+
+	switch (fpwrst) {
+	case PWRDM_FUNC_PWRST_ON:
+	case PWRDM_FUNC_PWRST_INACTIVE:
+	case PWRDM_FUNC_PWRST_CSWR:
+		ret = PWRDM_LOGIC_MEM_PWRST_RET;
+		break;
+	case PWRDM_FUNC_PWRST_OSWR:
+	case PWRDM_FUNC_PWRST_OFF:
+		ret = PWRDM_LOGIC_MEM_PWRST_OFF;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/**
+ * omap2_pwrdm_pwrst_to_fpwrst - Convert internal (i.e. registers) to
+ * functional (i.e. logical) values for the power domains states.
+ * @struct powerdomain * to convert the values for
+ * @pwrst: internal power state
+ *
+ * Returns the functional power state value for the power domain, or
+ * -EINVAL in case of invalid parameters passed in.
+ */
+int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
+{
+	int ret;
+
+	switch (pwrst) {
+	case PWRDM_POWER_ON:
+		ret = PWRDM_FUNC_PWRST_ON;
+		break;
+	case PWRDM_POWER_INACTIVE:
+		ret = PWRDM_FUNC_PWRST_INACTIVE;
+		break;
+	case PWRDM_POWER_RET:
+		if (logic == PWRDM_LOGIC_MEM_PWRST_RET)
+			ret = PWRDM_FUNC_PWRST_CSWR;
+		else
+			ret = PWRDM_FUNC_PWRST_OSWR;
+		break;
+	case PWRDM_POWER_OFF:
+		ret = PWRDM_FUNC_PWRST_OFF;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..6fc3c84 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -1,7 +1,7 @@
 /*
  * OMAP powerdomain control
  *
- * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2011-2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -128,14 +128,14 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
 
 	prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
 	if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
-	    (prev_logic_pwrst == PWRDM_POWER_OFF))
+	    (prev_logic_pwrst == PWRDM_LOGIC_MEM_PWRST_OFF))
 		pwrdm->ret_logic_off_counter++;
 
 	for (i = 0; i < pwrdm->banks; i++) {
 		prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i);
 
 		if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) &&
-		    (prev_mem_pwrst == PWRDM_POWER_OFF))
+		    (prev_mem_pwrst == PWRDM_LOGIC_MEM_PWRST_OFF))
 			pwrdm->ret_mem_off_counter[i]++;
 	}
 }
@@ -465,6 +465,171 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_fpwrst_to_pwrst - get the internal (i.e. registers) value mapped
+ * to the functional state
+ * @pwrdm: struct powerdomain * to query
+ * @fpwrst: functional power state
+ *
+ * Convert the functional power state to the platform specific power
+ * domain state value.
+ * Returns the internal power domain state value or -EINVAL in case
+ * of invalid parameters passed in.
+ */
+int pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+	int ret = fpwrst;
+
+	if ((!pwrdm) || (fpwrst >= PWRDM_MAX_FUNC_PWRSTS))
+		return -EINVAL;
+
+	if (arch_pwrdm && arch_pwrdm->pwrdm_fpwrst_to_pwrst)
+		ret = arch_pwrdm->pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
+
+	pr_debug("powerdomain: convert fwrst %0x to pwrst %0x for %s\n",
+		 fpwrst, ret, pwrdm->name);
+
+	return ret;
+}
+
+/**
+ * pwrdm_fpwrst_to_logic_pwrst - get the internal (i.e. registers) value
+ * of the logic state mapped to the functional state
+ * @pwrdm: struct powerdomain * to query
+ * @pwrst: functional power state
+ *
+ * Convert the functional power state to the platform specific power
+ * domain logic state value.
+ * Returns the internal power domain logic state value or -EINVAL in
+ * case of invalid parameters passed in.
+ */
+int pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst)
+{
+	int ret = fpwrst;
+
+	if ((!pwrdm) || (fpwrst >= PWRDM_MAX_FUNC_PWRSTS))
+		return -EINVAL;
+
+	if (arch_pwrdm && arch_pwrdm->pwrdm_fpwrst_to_logic_pwrst)
+		ret = arch_pwrdm->pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
+
+	pr_debug("powerdomain: convert fpwrst %0x to logic %0x pwrst for %s\n",
+		 fpwrst, ret, pwrdm->name);
+
+	return ret;
+}
+
+/**
+ * pwrdm_pwrst_to_fpwrst - get the functional (i.e. logical) value mapped
+ * to the internal state
+ * @pwrdm: struct powerdomain * to query
+ * @pwrst: internal power state
+ * @logic: internal logic state
+ *
+ * Convert the internal power state and logic power state
+ * to the power domain functional value.
+ * Returns the functional power domain state value or -EINVAL in case
+ * of invalid parameters passed in.
+ */
+int pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic)
+{
+	int ret = pwrst;
+
+	if ((!pwrdm) || (pwrst >= PWRDM_MAX_PWRSTS) ||
+	    (logic >= PWRDM_MAX_LOGIC_MEM_PWRST))
+		return -EINVAL;
+
+	while (!(pwrdm->pwrsts_logic_ret & (1 << logic))) {
+		if (logic == PWRDM_LOGIC_MEM_PWRST_RET)
+			break;
+		logic++;
+	}
+
+	if (arch_pwrdm && arch_pwrdm->pwrdm_pwrst_to_fpwrst)
+		ret = arch_pwrdm->pwrdm_pwrst_to_fpwrst(pwrdm, pwrst, logic);
+
+	pr_debug("powerdomain: convert pwrst (%0x,%0x) to fpwrst %0x for %s\n",
+		 pwrst, logic, ret, pwrdm->name);
+
+	return ret;
+}
+
+/* Types of sleep_switch used in pwrdm_set_next_fpwrst */
+#define FORCEWAKEUP_SWITCH	0
+#define LOWPOWERSTATE_SWITCH	1
+
+/**
+ * pwrdm_set_next_fpwrst - program next powerdomain functional power state
+ * @pwrdm: struct powerdomain * to set
+ * @fpwrst: power domain functional state, one of the PWRDM_FUNC_* macros
+ *
+ * This programs the pwrdm next functional state, sets the dependencies
+ * and waits for the state to be applied.
+ */
+int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
+			  enum pwrdm_func_state fpwrst)
+{
+	u8 curr_pwrst, next_pwrst;
+	int pwrst = pwrdm_fpwrst_to_pwrst(pwrdm, fpwrst);
+	int logic = pwrdm_fpwrst_to_logic_pwrst(pwrdm, fpwrst);
+	int sleep_switch = -1, ret = 0, hwsup = 0;
+
+	if (!pwrdm || IS_ERR(pwrdm) || (pwrst < 0) || (logic < 0)) {
+		pr_debug("%s: invalid params: pwrdm=%p, fpwrst=%0x\n",
+			 __func__, pwrdm, fpwrst);
+		return -EINVAL;
+	}
+
+	pr_debug("%s: set fpwrst %0x to pwrdm %s\n",
+		 __func__, fpwrst, pwrdm->name);
+
+	while (!(pwrdm->pwrsts & (1 << pwrst))) {
+		if (pwrst == PWRDM_POWER_OFF)
+			return ret;
+		pwrst--;
+	}
+
+	next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+	if (next_pwrst == pwrst)
+		return ret;
+
+	curr_pwrst = pwrdm_read_pwrst(pwrdm);
+	if (curr_pwrst < PWRDM_POWER_ON) {
+		if ((curr_pwrst > pwrst) &&
+			(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+			sleep_switch = LOWPOWERSTATE_SWITCH;
+		} else {
+			hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
+			clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+			sleep_switch = FORCEWAKEUP_SWITCH;
+		}
+	}
+
+	if (logic != pwrdm_read_logic_retst(pwrdm))
+		pwrdm_set_logic_retst(pwrdm, logic);
+
+	ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
+	if (ret)
+		pr_err("%s: unable to set power state of powerdomain: %s\n",
+		       __func__, pwrdm->name);
+
+	switch (sleep_switch) {
+	case FORCEWAKEUP_SWITCH:
+		if (hwsup)
+			clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+		else
+			clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+		break;
+	case LOWPOWERSTATE_SWITCH:
+		pwrdm_set_lowpwrstchange(pwrdm);
+		pwrdm_wait_transition(pwrdm);
+		pwrdm_state_switch(pwrdm);
+		break;
+	}
+
+	return ret;
+}
+
+/**
  * pwrdm_set_next_pwrst - set next powerdomain power state
  * @pwrdm: struct powerdomain * to set
  * @pwrst: one of the PWRDM_POWER_* macros
@@ -521,6 +686,22 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_read_next_fpwrst - get next powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get power state
+ *
+ * Return the powerdomain @pwrdm's next functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns
+ * the next power state upon success.
+ */
+int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm)
+{
+	int next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+	int next_logic = pwrdm_read_logic_retst(pwrdm);
+
+	return pwrdm_pwrst_to_fpwrst(pwrdm, next_pwrst, next_logic);
+}
+
+/**
  * pwrdm_read_pwrst - get current powerdomain power state
  * @pwrdm: struct powerdomain * to get power state
  *
@@ -546,6 +727,22 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_read_fpwrst - get current powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get power state
+ *
+ * Return the powerdomain @pwrdm's current functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns
+ * the current power state upon success.
+ */
+int pwrdm_read_fpwrst(struct powerdomain *pwrdm)
+{
+	int pwrst = pwrdm_read_pwrst(pwrdm);
+	int logic = pwrdm_read_logic_pwrst(pwrdm);
+
+	return pwrdm_pwrst_to_fpwrst(pwrdm, pwrst, logic);
+}
+
+/**
  * pwrdm_read_prev_pwrst - get previous powerdomain power state
  * @pwrdm: struct powerdomain * to get previous power state
  *
@@ -567,9 +764,25 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 }
 
 /**
+ * pwrdm_read_prev_fpwrst - get previous powerdomain functional power state
+ * @pwrdm: struct powerdomain * to get previous power state
+ *
+ * Return the powerdomain @pwrdm's previous functional power state.
+ * Returns -EINVAL if the powerdomain pointer is null or returns the
+ * previous power state upon success.
+ */
+int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm)
+{
+	int prev_pwrst = pwrdm_read_prev_pwrst(pwrdm);
+	int prev_logic = pwrdm_read_prev_logic_pwrst(pwrdm);
+
+	return pwrdm_pwrst_to_fpwrst(pwrdm, prev_pwrst, prev_logic);
+}
+
+/**
  * pwrdm_set_logic_retst - set powerdomain logic power state upon retention
  * @pwrdm: struct powerdomain * to set
- * @pwrst: one of the PWRDM_POWER_* macros
+ * @pwrst: one of the PWRDM_LOGIC_MEM_PWRST_* macros
  *
  * Set the next power state @pwrst that the logic portion of the
  * powerdomain @pwrdm will enter when the powerdomain enters retention.
@@ -600,7 +813,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
  * pwrdm_set_mem_onst - set memory power state while powerdomain ON
  * @pwrdm: struct powerdomain * to set
  * @bank: memory bank number to set (0-3)
- * @pwrst: one of the PWRDM_POWER_* macros
+ * @pwrst: one of the PWRDM_LOGIC_MEM_PWRST_* macros
  *
  * Set the next power state @pwrst that memory bank @bank of the
  * powerdomain @pwrdm will enter when the powerdomain enters the ON
@@ -637,7 +850,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  * pwrdm_set_mem_retst - set memory power state while powerdomain in RET
  * @pwrdm: struct powerdomain * to set
  * @bank: memory bank number to set (0-3)
- * @pwrst: one of the PWRDM_POWER_* macros
+ * @pwrst: one of the PWRDM_LOGIC_MEM_PWRST_* macros
  *
  * Set the next power state @pwrst that memory bank @bank of the
  * powerdomain @pwrdm will enter when the powerdomain enters the
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index baee906..aa9f9b9 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3/4 powerdomain control
  *
- * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley
@@ -9,9 +9,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * XXX This should be moved to the mach-omap2/ directory at the earliest
- * opportunity.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
@@ -26,6 +23,26 @@
 
 #include "voltage.h"
 
+/* Powerdomain functional power states, used by the external API functions */
+enum pwrdm_func_state {
+	PWRDM_FUNC_PWRST_OFF		= 0x0,
+	PWRDM_FUNC_PWRST_OSWR,
+	PWRDM_FUNC_PWRST_CSWR,
+	PWRDM_FUNC_PWRST_INACTIVE,
+	PWRDM_FUNC_PWRST_ON,
+	PWRDM_MAX_FUNC_PWRSTS		/* Last value, used as the max value */
+};
+
+/*
+ * Powerdomains logic and memory functional power states,
+ * used by the external API functions
+ */
+enum pwrdm_logic_mem_state {
+	PWRDM_LOGIC_MEM_PWRST_OFF	= 0x0,
+	PWRDM_LOGIC_MEM_PWRST_RET,
+	PWRDM_MAX_LOGIC_MEM_PWRST	/* Last value, used as the max value */
+};
+
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF		0x0
 #define PWRDM_POWER_RET		0x1
@@ -146,6 +163,12 @@ struct powerdomain {
 
 /**
  * struct pwrdm_ops - Arch specific function implementations
+ * @pwrdm_fpwrst_to_pwrst: Convert the pd functional power state to
+ *  the internal state
+ * @pwrdm_fpwrst_to_logic_pwrst: Convert the pd functional power state
+ *  to the internal logic state
+ * @pwrdm_pwrst_to_fpwrst: Convert the pd internal and logic power state to
+ *  the functional state
  * @pwrdm_set_next_pwrst: Set the target power state for a pd
  * @pwrdm_read_next_pwrst: Read the target power state set for a pd
  * @pwrdm_read_pwrst: Read the current power state of a pd
@@ -166,6 +189,11 @@ struct powerdomain {
  * @pwrdm_wait_transition: Wait for a pd state transition to complete
  */
 struct pwrdm_ops {
+	int	(*pwrdm_fpwrst_to_pwrst)(struct powerdomain *pwrdm, u8 fpwrst);
+	int	(*pwrdm_fpwrst_to_logic_pwrst)(struct powerdomain *pwrdm,
+					       u8 fpwrst);
+	int	(*pwrdm_pwrst_to_fpwrst)(struct powerdomain *pwrdm, u8 fpwrst,
+					 u8 logic);
 	int	(*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
 	int	(*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
 	int	(*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
@@ -206,6 +234,15 @@ struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
 
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
+int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
+			  enum pwrdm_func_state fpwrst);
+int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm);
+int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic);
+
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 0f0a9f1..aa883aa 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -210,6 +210,9 @@ static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 }
 
 struct pwrdm_ops omap2_pwrdm_operations = {
+	.pwrdm_fpwrst_to_pwrst	= omap2_pwrdm_fpwrst_to_pwrst,
+	.pwrdm_fpwrst_to_logic_pwrst	= omap2_pwrdm_fpwrst_to_logic_pwrst,
+	.pwrdm_pwrst_to_fpwrst	= omap2_pwrdm_pwrst_to_fpwrst,
 	.pwrdm_set_next_pwrst	= omap2_pwrdm_set_next_pwrst,
 	.pwrdm_read_next_pwrst	= omap2_pwrdm_read_next_pwrst,
 	.pwrdm_read_pwrst	= omap2_pwrdm_read_pwrst,
@@ -222,6 +225,9 @@ struct pwrdm_ops omap2_pwrdm_operations = {
 };
 
 struct pwrdm_ops omap3_pwrdm_operations = {
+	.pwrdm_fpwrst_to_pwrst	= omap2_pwrdm_fpwrst_to_pwrst,
+	.pwrdm_fpwrst_to_logic_pwrst	= omap2_pwrdm_fpwrst_to_logic_pwrst,
+	.pwrdm_pwrst_to_fpwrst	= omap2_pwrdm_pwrst_to_fpwrst,
 	.pwrdm_set_next_pwrst	= omap2_pwrdm_set_next_pwrst,
 	.pwrdm_read_next_pwrst	= omap2_pwrdm_read_next_pwrst,
 	.pwrdm_read_pwrst	= omap2_pwrdm_read_pwrst,
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 601325b..8c37cc9 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -209,6 +209,9 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 }
 
 struct pwrdm_ops omap4_pwrdm_operations = {
+	.pwrdm_fpwrst_to_pwrst	= omap2_pwrdm_fpwrst_to_pwrst,
+	.pwrdm_fpwrst_to_logic_pwrst	= omap2_pwrdm_fpwrst_to_logic_pwrst,
+	.pwrdm_pwrst_to_fpwrst	= omap2_pwrdm_pwrst_to_fpwrst,
 	.pwrdm_set_next_pwrst	= omap4_pwrdm_set_next_pwrst,
 	.pwrdm_read_next_pwrst	= omap4_pwrdm_read_next_pwrst,
 	.pwrdm_read_pwrst	= omap4_pwrdm_read_pwrst,
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:47 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:47 +0200
Subject: [PATCH 7/8] ARM: OMAP2+: powerdomain: add error logs
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-8-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

Silent failure makes debug hard. So, provide rate limited error
messages in functional and oft-used code to prevent spam
when something goes wrong..

Signed-off-by: Nishanth Menon <nm at ti.com>
---
 arch/arm/mach-omap2/powerdomain.c |   72 +++++++++++++++++++++++++++++-------
 1 files changed, 58 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 06a566b..691247e 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/string.h>
+#include <linux/ratelimit.h>
 #include <trace/events/power.h>
 
 #include "cm2xxx_3xxx.h"
@@ -146,8 +147,12 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 
 	int prev, next, state, trace_state;
 
-	if (pwrdm == NULL)
+	if (pwrdm == NULL) {
+		WARN_ONCE(1, "null pwrdm\n");
+		pr_err_ratelimited("%s: powerdomain: null pwrdm param\n",
+				   __func__);
 		return -EINVAL;
+	}
 
 	state = pwrdm_read_fpwrst(pwrdm);
 
@@ -174,6 +179,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
 		}
 		break;
 	default:
+		pr_err_ratelimited("%s: powerdomain %s: bad flag %d\n",
+				   __func__, pwrdm->name, flag);
 		return -EINVAL;
 	}
 
@@ -690,7 +697,8 @@ int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
 	unsigned long flags;
 
 	if (!pwrdm || IS_ERR(pwrdm)) {
-		pr_debug("%s: invalid params: pwrdm=%p\n", __func__, pwrdm);
+		pr_err_ratelimited("%s: invalid params: pwrdm=%p\n",
+				   __func__, pwrdm);
 		return -EINVAL;
 	}
 
@@ -775,8 +783,11 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 	if (!pwrdm)
 		return -EINVAL;
 
-	if (!(pwrdm->pwrsts & (1 << pwrst)))
+	if (!(pwrdm->pwrsts & (1 << pwrst))) {
+		pr_err_ratelimited("%s: powerdomain %s: bad pwrst %d\n",
+				   __func__, pwrdm->name, pwrst);
 		return -EINVAL;
+	}
 
 	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
 		 pwrdm->name, pwrst);
@@ -924,8 +935,11 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 	if (!pwrdm)
 		return -EINVAL;
 
-	if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
+	if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst))) {
+		pr_err_ratelimited("%s: powerdomain %s: bad pwrst %d\n",
+				   __func__, pwrdm->name, pwrst);
 		return -EINVAL;
+	}
 
 	pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
 		 pwrdm->name, pwrst);
@@ -958,11 +972,17 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 	if (!pwrdm)
 		return -EINVAL;
 
-	if (pwrdm->banks < (bank + 1))
+	if (pwrdm->banks < (bank + 1)) {
+		pr_err_ratelimited("%s: powerdomain %s: bad bank %d\n",
+				   __func__, pwrdm->name, bank);
 		return -EEXIST;
+	}
 
-	if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
+	if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) {
+		pr_err_ratelimited("%s: powerdomain %s: bank %d bad pwrst %d\n",
+				   __func__, pwrdm->name, bank, pwrst);
 		return -EINVAL;
+	}
 
 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
 		 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
@@ -996,11 +1016,17 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 	if (!pwrdm)
 		return -EINVAL;
 
-	if (pwrdm->banks < (bank + 1))
+	if (pwrdm->banks < (bank + 1)) {
+		pr_err_ratelimited("%s: powerdomain %s: bad bank %d\n",
+				   __func__, pwrdm->name, bank);
 		return -EEXIST;
+	}
 
-	if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
+	if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) {
+		pr_err_ratelimited("%s: powerdomain %s: bank %d bad pwrst %d\n",
+				   __func__, pwrdm->name, bank, pwrst);
 		return -EINVAL;
+	}
 
 	pr_debug("powerdomain: setting next memory powerstate for domain %s "
 		 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
@@ -1092,8 +1118,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 	if (!pwrdm)
 		return ret;
 
-	if (pwrdm->banks < (bank + 1))
+	if (pwrdm->banks < (bank + 1)) {
+		pr_err_ratelimited("%s: powerdomain %s: bad bank %d\n",
+				   __func__, pwrdm->name, bank);
 		return ret;
+	}
 
 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
 		bank = 1;
@@ -1122,8 +1151,11 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 	if (!pwrdm)
 		return ret;
 
-	if (pwrdm->banks < (bank + 1))
+	if (pwrdm->banks < (bank + 1)) {
+		pr_err_ratelimited("%s: powerdomain %s: bad bank %d\n",
+				   __func__, pwrdm->name, bank);
 		return ret;
+	}
 
 	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
 		bank = 1;
@@ -1151,8 +1183,11 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 	if (!pwrdm)
 		return ret;
 
-	if (pwrdm->banks < (bank + 1))
+	if (pwrdm->banks < (bank + 1)) {
+		pr_err_ratelimited("%s: powerdomain %s: bad bank %d\n",
+				   __func__, pwrdm->name, bank);
 		return ret;
+	}
 
 	if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst)
 		ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);
@@ -1208,8 +1243,11 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 	if (!pwrdm)
 		return ret;
 
-	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) {
+		pr_err_ratelimited("%s: powerdomain %s: no HDSAR in flag %d\n",
+				   __func__, pwrdm->name, pwrdm->flags);
 		return ret;
+	}
 
 	pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
 		 pwrdm->name);
@@ -1238,8 +1276,11 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 	if (!pwrdm)
 		return ret;
 
-	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
+	if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) {
+		pr_err_ratelimited("%s: powerdomain %s: no HDSAR in flag %d\n",
+				   __func__, pwrdm->name, pwrdm->flags);
 		return ret;
+	}
 
 	pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
 		 pwrdm->name);
@@ -1279,8 +1320,11 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 	if (!pwrdm)
 		return -EINVAL;
 
-	if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
+	if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+		pr_err_ratelimited("%s: powerdomain %s:no lowpwrch in flag%d\n",
+				   __func__, pwrdm->name, pwrdm->flags);
 		return -EINVAL;
+	}
 
 	pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
 		 pwrdm->name);
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:48 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:48 +0200
Subject: [PATCH 8/8] ARM: OMAP2+: PM: reorganize the powerdomain API in public
 and private parts
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-9-git-send-email-j-pihet@ti.com>

The newly added code for functional power states re-defines the
API to query and control the power domains settings.

The API is now split in the following parts in powerdomain.h:
- the public or external API, to be used by external PM components:
  cpuidle, suspend, pmxxxx, clock* etc.
- the private or internal API, to be used by the low level PM code
  only: powerdomain*, pm-debug, hwmod, voltage, clockdomainxxxx.

No functional change is introduced by this patch.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/powerdomain.h |  119 ++++++++++++++++++++-----------------
 1 files changed, 65 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index df83c7c..0bf613c 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -24,6 +24,11 @@
 
 #include "voltage.h"
 
+/***************************************************************
+ * External API, to be used by external PM components: cpuidle,
+ * suspend, pmxxxx, clock* etc.
+ ***************************************************************/
+
 /* Powerdomain functional power states, used by the external API functions */
 enum pwrdm_func_state {
 	PWRDM_FUNC_PWRST_OFF		= 0x0,
@@ -44,6 +49,62 @@ enum pwrdm_logic_mem_state {
 	PWRDM_MAX_LOGIC_MEM_PWRST	/* Last value, used as the max value */
 };
 
+struct clockdomain;
+struct powerdomain;
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+			void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+			void *user);
+
+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+			 int (*fn)(struct powerdomain *pwrdm,
+				   struct clockdomain *clkdm));
+struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+/* Functions that query and control the power domain state setings */
+int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
+			  enum pwrdm_func_state fpwrst);
+int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
+int pwrdm_pre_transition(struct powerdomain *pwrdm);
+int pwrdm_post_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+
+extern void omap242x_powerdomains_init(void);
+extern void omap243x_powerdomains_init(void);
+extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
+extern void omap44xx_powerdomains_init(void);
+
+
+/***************************************************************
+ * Internal API, to be included by the low level PM code only:
+ * powerdomain*, pm-debug, hwmod, voltage, clockdomainxxxx
+ ***************************************************************/
+
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF		0x0
 #define PWRDM_POWER_RET		0x1
@@ -92,9 +153,6 @@ enum pwrdm_logic_mem_state {
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
 
-struct clockdomain;
-struct powerdomain;
-
 /**
  * struct powerdomain - OMAP powerdomain
  * @name: Powerdomain name
@@ -221,67 +279,17 @@ int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
 int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
 int pwrdm_complete_init(void);
 
-struct powerdomain *pwrdm_lookup(const char *name);
-
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
-			void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
-			void *user);
-
-int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
-			 int (*fn)(struct powerdomain *pwrdm,
-				   struct clockdomain *clkdm));
-struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
-
-int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
-
-int pwrdm_set_next_fpwrst(struct powerdomain *pwrdm,
-			  enum pwrdm_func_state fpwrst);
-int pwrdm_read_prev_fpwrst(struct powerdomain *pwrdm);
-int pwrdm_read_fpwrst(struct powerdomain *pwrdm);
-int pwrdm_read_next_fpwrst(struct powerdomain *pwrdm);
-int pwrdm_get_achievable_fpwrst(struct powerdomain *pwrdm, u8 fpwrst);
-int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
-int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
-int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic);
-
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
-int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
-
 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
 int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
-int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-
-int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
-bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
-
-int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_pre_transition(struct powerdomain *pwrdm);
-int pwrdm_post_transition(struct powerdomain *pwrdm);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
-int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
-bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
-
-extern void omap242x_powerdomains_init(void);
-extern void omap243x_powerdomains_init(void);
-extern void omap3xxx_powerdomains_init(void);
-extern void am33xx_powerdomains_init(void);
-extern void omap44xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
@@ -293,8 +301,11 @@ extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
 extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
 extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
 
+int omap2_pwrdm_fpwrst_to_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int omap2_pwrdm_fpwrst_to_logic_pwrst(struct powerdomain *pwrdm, u8 fpwrst);
+int omap2_pwrdm_pwrst_to_fpwrst(struct powerdomain *pwrdm, u8 pwrst, u8 logic);
+
 extern struct powerdomain wkup_omap2_pwrdm;
 extern struct powerdomain gfx_omap2_pwrdm;
 
-
 #endif
-- 
1.7.7.6



From jean.pihet at newoldbits.com  Wed Aug 15 06:02:44 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 15 Aug 2012 12:02:44 +0200
Subject: [PATCH 4/8] ARM: OMAP2+: PM: use the functional power states API
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <1345024968-28951-5-git-send-email-j-pihet@ti.com>

Use the functional power states as the API to control power
domains:
- use the PWRDM_FUNC_PWRST_* and PWRDM_LOGIC_MEM_PWRST_*
  macros for the power states and logic settings,
- the pwrdm_set_next_fpwrst function, which controls
  the power states and logic settings of power domains, shall
  be used instead of pwrdm_set_next_pwrst to program the power
  domains next states.

Note: the internal code for power domains state management still
uses the internal power states.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/cpuidle34xx.c         |   58 +++++++++++-----------
 arch/arm/mach-omap2/cpuidle44xx.c         |   24 +++------
 arch/arm/mach-omap2/omap-hotplug.c        |    2 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c |   39 +++++++-------
 arch/arm/mach-omap2/pm24xx.c              |   14 ++---
 arch/arm/mach-omap2/pm34xx.c              |   79 +++++++++++++++--------------
 arch/arm/mach-omap2/pm44xx.c              |   24 +++------
 arch/arm/mach-omap2/powerdomain.c         |    2 +-
 8 files changed, 116 insertions(+), 126 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a4..4ca37d2 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -44,32 +44,32 @@ struct omap3_idle_statedata {
 
 static struct omap3_idle_statedata omap3_idle_data[] = {
 	{
-		.mpu_state = PWRDM_POWER_ON,
-		.core_state = PWRDM_POWER_ON,
+		.mpu_state = PWRDM_FUNC_PWRST_ON,
+		.core_state = PWRDM_FUNC_PWRST_ON,
 	},
 	{
-		.mpu_state = PWRDM_POWER_ON,
-		.core_state = PWRDM_POWER_ON,
+		.mpu_state = PWRDM_FUNC_PWRST_ON,
+		.core_state = PWRDM_FUNC_PWRST_ON,
 	},
 	{
-		.mpu_state = PWRDM_POWER_RET,
-		.core_state = PWRDM_POWER_ON,
+		.mpu_state = PWRDM_FUNC_PWRST_CSWR,
+		.core_state = PWRDM_FUNC_PWRST_ON,
 	},
 	{
-		.mpu_state = PWRDM_POWER_OFF,
-		.core_state = PWRDM_POWER_ON,
+		.mpu_state = PWRDM_FUNC_PWRST_OFF,
+		.core_state = PWRDM_FUNC_PWRST_ON,
 	},
 	{
-		.mpu_state = PWRDM_POWER_RET,
-		.core_state = PWRDM_POWER_RET,
+		.mpu_state = PWRDM_FUNC_PWRST_CSWR,
+		.core_state = PWRDM_FUNC_PWRST_CSWR,
 	},
 	{
-		.mpu_state = PWRDM_POWER_OFF,
-		.core_state = PWRDM_POWER_RET,
+		.mpu_state = PWRDM_FUNC_PWRST_OFF,
+		.core_state = PWRDM_FUNC_PWRST_CSWR,
 	},
 	{
-		.mpu_state = PWRDM_POWER_OFF,
-		.core_state = PWRDM_POWER_OFF,
+		.mpu_state = PWRDM_FUNC_PWRST_OFF,
+		.core_state = PWRDM_FUNC_PWRST_OFF,
 	},
 };
 
@@ -84,8 +84,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 
 	local_fiq_disable();
 
-	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
-	pwrdm_set_next_pwrst(core_pd, core_state);
+	pwrdm_set_next_fpwrst(mpu_pd, mpu_state);
+	pwrdm_set_next_fpwrst(core_pd, core_state);
 
 	if (omap_irq_pending() || need_resched())
 		goto return_sleep_time;
@@ -100,7 +100,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 	 * Call idle CPU PM enter notifier chain so that
 	 * VFP context is saved.
 	 */
-	if (mpu_state == PWRDM_POWER_OFF)
+	if (mpu_state == PWRDM_FUNC_PWRST_OFF)
 		cpu_pm_enter();
 
 	/* Execute ARM wfi */
@@ -110,7 +110,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 	 * Call idle CPU PM enter notifier chain to restore
 	 * VFP context.
 	 */
-	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+	if (pwrdm_read_prev_fpwrst(mpu_pd) == PWRDM_FUNC_PWRST_OFF)
 		cpu_pm_exit();
 
 	/* Re-allow idle for C1 */
@@ -159,20 +159,20 @@ static int next_valid_state(struct cpuidle_device *dev,
 			    struct cpuidle_driver *drv, int index)
 {
 	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
-	u32 mpu_deepest_state = PWRDM_POWER_RET;
-	u32 core_deepest_state = PWRDM_POWER_RET;
+	u32 mpu_deepest_state = PWRDM_FUNC_PWRST_CSWR;
+	u32 core_deepest_state = PWRDM_FUNC_PWRST_CSWR;
 	int idx;
 	int next_index = 0; /* C1 is the default value */
 
 	if (enable_off_mode) {
-		mpu_deepest_state = PWRDM_POWER_OFF;
+		mpu_deepest_state = PWRDM_FUNC_PWRST_OFF;
 		/*
 		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
 		 * CORE OFF mode is not supported in a stable form, restrict
 		 * instead the CORE state to RET.
 		 */
 		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
-			core_deepest_state = PWRDM_POWER_OFF;
+			core_deepest_state = PWRDM_FUNC_PWRST_OFF;
 	}
 
 	/* Check if current state is valid */
@@ -218,7 +218,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	 * Use only C1 if CAM is active.
 	 * CAM does not have wakeup capability in OMAP3.
 	 */
-	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
+	if (pwrdm_read_fpwrst(cam_pd) == PWRDM_FUNC_PWRST_ON)
 		new_state_idx = drv->safe_state_index;
 	else
 		new_state_idx = next_valid_state(dev, drv, index);
@@ -234,7 +234,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	/* Program PER state */
 	cx = &omap3_idle_data[new_state_idx];
 	core_next_state = cx->core_state;
-	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
+	per_next_state = per_saved_state = pwrdm_read_next_fpwrst(per_pd);
 	if (new_state_idx == 0) {
 		/* In C1 do not allow PER state lower than CORE state */
 		if (per_next_state < core_next_state)
@@ -244,20 +244,20 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 		 * Prevent PER OFF if CORE is not in RETention or OFF as this
 		 * would disable PER wakeups completely.
 		 */
-		if ((per_next_state == PWRDM_POWER_OFF) &&
-		    (core_next_state > PWRDM_POWER_RET))
-			per_next_state = PWRDM_POWER_RET;
+		if ((per_next_state == PWRDM_FUNC_PWRST_OFF) &&
+		    (core_next_state > PWRDM_FUNC_PWRST_CSWR))
+			per_next_state = PWRDM_FUNC_PWRST_CSWR;
 	}
 
 	/* Are we changing PER target state? */
 	if (per_next_state != per_saved_state)
-		pwrdm_set_next_pwrst(per_pd, per_next_state);
+		pwrdm_set_next_fpwrst(per_pd, per_next_state);
 
 	ret = omap3_enter_idle(dev, drv, new_state_idx);
 
 	/* Restore original PER state if it was modified */
 	if (per_next_state != per_saved_state)
-		pwrdm_set_next_pwrst(per_pd, per_saved_state);
+		pwrdm_set_next_fpwrst(per_pd, per_saved_state);
 
 	return ret;
 }
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index ee05e19..e4af351 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -26,25 +26,21 @@
 /* Machine specific information */
 struct omap4_idle_statedata {
 	u32 cpu_state;
-	u32 mpu_logic_state;
 	u32 mpu_state;
 };
 
 static struct omap4_idle_statedata omap4_idle_data[] = {
 	{
-		.cpu_state = PWRDM_POWER_ON,
-		.mpu_state = PWRDM_POWER_ON,
-		.mpu_logic_state = PWRDM_POWER_RET,
+		.cpu_state = PWRDM_FUNC_PWRST_ON,
+		.mpu_state = PWRDM_FUNC_PWRST_ON,
 	},
 	{
-		.cpu_state = PWRDM_POWER_OFF,
-		.mpu_state = PWRDM_POWER_RET,
-		.mpu_logic_state = PWRDM_POWER_RET,
+		.cpu_state = PWRDM_FUNC_PWRST_OFF,
+		.mpu_state = PWRDM_FUNC_PWRST_CSWR,
 	},
 	{
-		.cpu_state = PWRDM_POWER_OFF,
-		.mpu_state = PWRDM_POWER_RET,
-		.mpu_logic_state = PWRDM_POWER_OFF,
+		.cpu_state = PWRDM_FUNC_PWRST_OFF,
+		.mpu_state = PWRDM_FUNC_PWRST_OSWR,
 	},
 };
 
@@ -91,7 +87,7 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 	 * out of coherency and in OFF mode.
 	 */
 	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
-		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
+		while (pwrdm_read_fpwrst(cpu_pd[1]) != PWRDM_FUNC_PWRST_OFF) {
 			cpu_relax();
 
 			/*
@@ -116,15 +112,13 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 	cpu_pm_enter();
 
 	if (dev->cpu == 0) {
-		pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
-		omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+		pwrdm_set_next_fpwrst(mpu_pd, cx->mpu_state);
 
 		/*
 		 * Call idle CPU cluster PM enter notifier chain
 		 * to save GIC and wakeupgen context.
 		 */
-		if ((cx->mpu_state == PWRDM_POWER_RET) &&
-			(cx->mpu_logic_state == PWRDM_POWER_OFF))
+		if (cx->mpu_state == PWRDM_FUNC_PWRST_OSWR)
 				cpu_cluster_pm_enter();
 	}
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 414083b..be53726 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -58,7 +58,7 @@ void __ref platform_cpu_die(unsigned int cpu)
 		/*
 		 * Enter into low power state
 		 */
-		omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
+		omap4_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
 
 		if (omap_secure_apis_support())
 			boot_cpu = omap_read_auxcoreboot0();
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 637a1bd..f73c0c8 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -86,14 +86,14 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 }
 
 /*
- * Set the CPUx powerdomain's previous power state
+ * Set the CPUx powerdomain's next functional power state
  */
 static inline void set_cpu_next_pwrst(unsigned int cpu_id,
 				unsigned int power_state)
 {
 	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+	pwrdm_set_next_fpwrst(pm_info->pwrdm, power_state);
 }
 
 /*
@@ -103,7 +103,7 @@ static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
 {
 	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
+	return pwrdm_read_prev_fpwrst(pm_info->pwrdm);
 }
 
 /*
@@ -125,14 +125,15 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 	u32 scu_pwr_st;
 
 	switch (cpu_state) {
-	case PWRDM_POWER_RET:
+	case PWRDM_FUNC_PWRST_OSWR:
+	case PWRDM_FUNC_PWRST_CSWR:
 		scu_pwr_st = SCU_PM_DORMANT;
 		break;
-	case PWRDM_POWER_OFF:
+	case PWRDM_FUNC_PWRST_OFF:
 		scu_pwr_st = SCU_PM_POWEROFF;
 		break;
-	case PWRDM_POWER_ON:
-	case PWRDM_POWER_INACTIVE:
+	case PWRDM_FUNC_PWRST_ON:
+	case PWRDM_FUNC_PWRST_INACTIVE:
 	default:
 		scu_pwr_st = SCU_PM_NORMAL;
 		break;
@@ -236,14 +237,15 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 		return -ENXIO;
 
 	switch (power_state) {
-	case PWRDM_POWER_ON:
-	case PWRDM_POWER_INACTIVE:
+	case PWRDM_FUNC_PWRST_ON:
+	case PWRDM_FUNC_PWRST_INACTIVE:
 		save_state = 0;
 		break;
-	case PWRDM_POWER_OFF:
+	case PWRDM_FUNC_PWRST_OFF:
 		save_state = 1;
 		break;
-	case PWRDM_POWER_RET:
+	case PWRDM_FUNC_PWRST_OSWR:
+	case PWRDM_FUNC_PWRST_CSWR:
 	default:
 		/*
 		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
@@ -259,11 +261,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 
 	/*
 	 * Check MPUSS next state and save interrupt controller if needed.
-	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
+	 * In MPUSS OSWR or device OFF, interrupt controller context is lost.
 	 */
 	mpuss_clear_prev_logic_pwrst();
-	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
-		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
+	if (pwrdm_read_next_fpwrst(mpuss_pd) == PWRDM_FUNC_PWRST_OSWR)
 		save_state = 2;
 
 	cpu_clear_prev_logic_pwrst(cpu);
@@ -285,7 +286,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 	 * domain transition
 	 */
 	wakeup_cpu = smp_processor_id();
-	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+	set_cpu_next_pwrst(wakeup_cpu, PWRDM_FUNC_PWRST_ON);
 
 	pwrdm_post_transition(NULL);
 
@@ -304,7 +305,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 	if (omap_rev() == OMAP4430_REV_ES1_0)
 		return -ENXIO;
 
-	if (power_state == PWRDM_POWER_OFF)
+	if (power_state == PWRDM_FUNC_PWRST_OFF)
 		cpu_state = 1;
 
 	clear_cpu_prev_pwrst(cpu);
@@ -319,7 +320,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 	 */
 	omap4_finish_suspend(cpu_state);
 
-	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
+	set_cpu_next_pwrst(cpu, PWRDM_FUNC_PWRST_ON);
 	return 0;
 }
 
@@ -354,7 +355,7 @@ int __init omap4_mpuss_init(void)
 	cpu_clear_prev_logic_pwrst(0);
 
 	/* Initialise CPU0 power domain state to ON */
-	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+	pwrdm_set_next_fpwrst(pm_info->pwrdm, PWRDM_FUNC_PWRST_ON);
 
 	pm_info = &per_cpu(omap4_pm_info, 0x1);
 	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
@@ -371,7 +372,7 @@ int __init omap4_mpuss_init(void)
 	cpu_clear_prev_logic_pwrst(1);
 
 	/* Initialise CPU1 power domain state to ON */
-	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+	pwrdm_set_next_fpwrst(pm_info->pwrdm, PWRDM_FUNC_PWRST_ON);
 
 	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 	if (!mpuss_pd) {
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc..f012bb4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -93,8 +93,7 @@ static int omap2_enter_full_retention(void)
 	 * Set MPU powerdomain's next power state to RETENTION;
 	 * preserve logic state during retention
 	 */
-	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
-	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
+	pwrdm_set_next_fpwrst(mpu_pwrdm, PWRDM_FUNC_PWRST_CSWR);
 
 	/* Workaround to kill USB */
 	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
@@ -248,26 +247,25 @@ static void __init prcm_setup_regs(void)
 	 */
 	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 	for (i = 0; i < num_mem_banks; i++)
-		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
+		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_LOGIC_MEM_PWRST_RET);
 
 	/* Set CORE powerdomain's next power state to RETENTION */
-	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
+	pwrdm_set_next_fpwrst(core_pwrdm, PWRDM_FUNC_PWRST_CSWR);
 
 	/*
 	 * Set MPU powerdomain's next power state to RETENTION;
 	 * preserve logic state during retention
 	 */
-	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
-	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
+	pwrdm_set_next_fpwrst(mpu_pwrdm, PWRDM_FUNC_PWRST_CSWR);
 
 	/* Force-power down DSP, GFX powerdomains */
 
 	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
-	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+	pwrdm_set_next_fpwrst(pwrdm, PWRDM_FUNC_PWRST_OFF);
 	clkdm_sleep(dsp_clkdm);
 
 	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
-	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+	pwrdm_set_next_fpwrst(pwrdm, PWRDM_FUNC_PWRST_OFF);
 	clkdm_sleep(gfx_clkdm);
 
 	/* Enable hardware-supervised idle for all clkdms */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..2049b7f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -111,7 +111,7 @@ static void omap3_core_restore_context(void)
 static void omap3_save_secure_ram_context(void)
 {
 	u32 ret;
-	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+	int mpu_next_state = pwrdm_read_next_fpwrst(mpu_pwrdm);
 
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 		/*
@@ -119,10 +119,10 @@ static void omap3_save_secure_ram_context(void)
 		 * otherwise the WFI executed inside the ROM code
 		 * will hang the system.
 		 */
-		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
+		pwrdm_set_next_fpwrst(mpu_pwrdm, PWRDM_FUNC_PWRST_ON);
 		ret = _omap_save_secure_sram((u32 *)
 				__pa(omap3_secure_ram_storage));
-		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
+		pwrdm_set_next_fpwrst(mpu_pwrdm, mpu_next_state);
 		/* Following is for error tracking, it should not happen */
 		if (ret) {
 			pr_err("save_secure_sram() returns %08x\n", ret);
@@ -241,21 +241,23 @@ void omap_sram_idle(void)
 	/* save_state = 2 => Only L2 lost */
 	/* save_state = 3 => L1, L2 and logic lost */
 	int save_state = 0;
-	int mpu_next_state = PWRDM_POWER_ON;
-	int per_next_state = PWRDM_POWER_ON;
-	int core_next_state = PWRDM_POWER_ON;
+	int mpu_next_state = PWRDM_FUNC_PWRST_ON;
+	int per_next_state = PWRDM_FUNC_PWRST_ON;
+	int core_next_state = PWRDM_FUNC_PWRST_ON;
 	int per_going_off;
 	int core_prev_state;
 	u32 sdrc_pwr = 0;
 
-	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+	mpu_next_state = pwrdm_read_next_fpwrst(mpu_pwrdm);
 	switch (mpu_next_state) {
-	case PWRDM_POWER_ON:
-	case PWRDM_POWER_RET:
+	case PWRDM_FUNC_PWRST_ON:
+	case PWRDM_FUNC_PWRST_INACTIVE:
+	case PWRDM_FUNC_PWRST_CSWR:
 		/* No need to save context */
 		save_state = 0;
 		break;
-	case PWRDM_POWER_OFF:
+	case PWRDM_FUNC_PWRST_OSWR:
+	case PWRDM_FUNC_PWRST_OFF:
 		save_state = 3;
 		break;
 	default:
@@ -265,29 +267,30 @@ void omap_sram_idle(void)
 	}
 
 	/* NEON control */
-	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
-		pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
+	if (pwrdm_read_fpwrst(neon_pwrdm) == PWRDM_FUNC_PWRST_ON)
+		pwrdm_set_next_fpwrst(neon_pwrdm, mpu_next_state);
 
 	/* Enable IO-PAD and IO-CHAIN wakeups */
-	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
-	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
+	per_next_state = pwrdm_read_next_fpwrst(per_pwrdm);
+	core_next_state = pwrdm_read_next_fpwrst(core_pwrdm);
 
-	if (mpu_next_state < PWRDM_POWER_ON) {
+	if (mpu_next_state < PWRDM_FUNC_PWRST_ON) {
 		pwrdm_pre_transition(mpu_pwrdm);
 		pwrdm_pre_transition(neon_pwrdm);
 	}
 
 	/* PER */
-	if (per_next_state < PWRDM_POWER_ON) {
+	if (per_next_state < PWRDM_FUNC_PWRST_ON) {
 		pwrdm_pre_transition(per_pwrdm);
-		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
+		per_going_off = (per_next_state == PWRDM_FUNC_PWRST_OFF) ?
+				1 : 0;
 		omap2_gpio_prepare_for_idle(per_going_off);
 	}
 
 	/* CORE */
-	if (core_next_state < PWRDM_POWER_ON) {
+	if (core_next_state < PWRDM_FUNC_PWRST_ON) {
 		pwrdm_pre_transition(core_pwrdm);
-		if (core_next_state == PWRDM_POWER_OFF) {
+		if (core_next_state == PWRDM_FUNC_PWRST_OFF) {
 			omap3_core_save_context();
 			omap3_cm_save_context();
 		}
@@ -304,7 +307,7 @@ void omap_sram_idle(void)
 	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
-	    core_next_state == PWRDM_POWER_OFF)
+	    core_next_state == PWRDM_FUNC_PWRST_OFF)
 		sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 
 	/*
@@ -323,19 +326,19 @@ void omap_sram_idle(void)
 	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
-	    core_next_state == PWRDM_POWER_OFF)
+	    core_next_state == PWRDM_FUNC_PWRST_OFF)
 		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 
 	/* CORE */
-	if (core_next_state < PWRDM_POWER_ON) {
-		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
-		if (core_prev_state == PWRDM_POWER_OFF) {
+	if (core_next_state < PWRDM_FUNC_PWRST_ON) {
+		core_prev_state = pwrdm_read_prev_fpwrst(core_pwrdm);
+		if (core_prev_state == PWRDM_FUNC_PWRST_OFF) {
 			omap3_core_restore_context();
 			omap3_cm_restore_context();
 			omap3_sram_restore_context();
 			omap2_sms_restore_context();
 		}
-		if (core_next_state == PWRDM_POWER_OFF)
+		if (core_next_state == PWRDM_FUNC_PWRST_OFF)
 			omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 					       OMAP3430_GR_MOD,
 					       OMAP3_PRM_VOLTCTRL_OFFSET);
@@ -344,12 +347,12 @@ void omap_sram_idle(void)
 	omap3_intc_resume_idle();
 
 	/* PER */
-	if (per_next_state < PWRDM_POWER_ON) {
+	if (per_next_state < PWRDM_FUNC_PWRST_ON) {
 		omap2_gpio_resume_after_idle();
 		pwrdm_post_transition(per_pwrdm);
 	}
 
-	if (mpu_next_state < PWRDM_POWER_ON) {
+	if (mpu_next_state < PWRDM_FUNC_PWRST_ON) {
 		pwrdm_post_transition(mpu_pwrdm);
 		pwrdm_post_transition(neon_pwrdm);
 	}
@@ -382,10 +385,10 @@ static int omap3_pm_suspend(void)
 
 	/* Read current next_pwrsts */
 	list_for_each_entry(pwrst, &pwrst_list, node)
-		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+		pwrst->saved_state = pwrdm_read_next_fpwrst(pwrst->pwrdm);
 	/* Set ones wanted by suspend */
 	list_for_each_entry(pwrst, &pwrst_list, node) {
-		if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
+		if (pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->next_state))
 			goto restore;
 		if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 			goto restore;
@@ -398,14 +401,14 @@ static int omap3_pm_suspend(void)
 restore:
 	/* Restore next_pwrsts */
 	list_for_each_entry(pwrst, &pwrst_list, node) {
-		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+		state = pwrdm_read_prev_fpwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
 			pr_info("Powerdomain (%s) didn't enter "
 				"target state %d\n",
 			       pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
-		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+		pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->saved_state);
 	}
 	if (ret)
 		pr_err("Could not enter target state in pm_suspend\n");
@@ -577,21 +580,21 @@ void omap3_pm_off_mode_enable(int enable)
 	u32 state;
 
 	if (enable)
-		state = PWRDM_POWER_OFF;
+		state = PWRDM_FUNC_PWRST_OFF;
 	else
-		state = PWRDM_POWER_RET;
+		state = PWRDM_FUNC_PWRST_CSWR;
 
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 				pwrst->pwrdm == core_pwrdm &&
-				state == PWRDM_POWER_OFF) {
-			pwrst->next_state = PWRDM_POWER_RET;
+				state == PWRDM_FUNC_PWRST_OFF) {
+			pwrst->next_state = PWRDM_FUNC_PWRST_CSWR;
 			pr_warn("%s: Core OFF disabled due to errata i583\n",
 				__func__);
 		} else {
 			pwrst->next_state = state;
 		}
-		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+		pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->next_state);
 	}
 }
 
@@ -630,13 +633,13 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 	if (!pwrst)
 		return -ENOMEM;
 	pwrst->pwrdm = pwrdm;
-	pwrst->next_state = PWRDM_POWER_RET;
+	pwrst->next_state = PWRDM_FUNC_PWRST_CSWR;
 	list_add(&pwrst->node, &pwrst_list);
 
 	if (pwrdm_has_hdwr_sar(pwrdm))
 		pwrdm_enable_hdwr_sar(pwrdm);
 
-	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+	return pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->next_state);
 }
 
 /*
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174..3d31880 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -28,7 +28,6 @@ struct power_state {
 	u32 next_state;
 #ifdef CONFIG_SUSPEND
 	u32 saved_state;
-	u32 saved_logic_state;
 #endif
 	struct list_head node;
 };
@@ -43,16 +42,12 @@ static int omap4_pm_suspend(void)
 	u32 cpu_id = smp_processor_id();
 
 	/* Save current powerdomain state */
-	list_for_each_entry(pwrst, &pwrst_list, node) {
-		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
-		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
-	}
+	list_for_each_entry(pwrst, &pwrst_list, node)
+		pwrst->saved_state = pwrdm_read_next_fpwrst(pwrst->pwrdm);
 
 	/* Set targeted power domain states by suspend */
-	list_for_each_entry(pwrst, &pwrst_list, node) {
-		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
-		pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
-	}
+	list_for_each_entry(pwrst, &pwrst_list, node)
+		pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->next_state);
 
 	/*
 	 * For MPUSS to hit power domain retention(CSWR or OSWR),
@@ -63,19 +58,18 @@ static int omap4_pm_suspend(void)
 	 * domain CSWR is not supported by hardware.
 	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
 	 */
-	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+	omap4_enter_lowpower(cpu_id, PWRDM_FUNC_PWRST_OFF);
 
 	/* Restore next powerdomain state */
 	list_for_each_entry(pwrst, &pwrst_list, node) {
-		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+		state = pwrdm_read_prev_fpwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
 			pr_info("Powerdomain (%s) didn't enter "
 			       "target state %d\n",
 			       pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
-		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
-		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
+		pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->saved_state);
 	}
 	if (ret)
 		pr_crit("Could not enter target state in pm_suspend\n");
@@ -113,10 +107,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 		return -ENOMEM;
 
 	pwrst->pwrdm = pwrdm;
-	pwrst->next_state = PWRDM_POWER_RET;
+	pwrst->next_state = PWRDM_FUNC_PWRST_CSWR;
 	list_add(&pwrst->node, &pwrst_list);
 
-	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+	return pwrdm_set_next_fpwrst(pwrst->pwrdm, pwrst->next_state);
 }
 
 /**
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index a8f7a81..1f9ed2c 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -317,7 +317,7 @@ int pwrdm_complete_init(void)
 		return -EACCES;
 
 	list_for_each_entry(temp_p, &pwrdm_list, node)
-		pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
+		pwrdm_set_next_fpwrst(temp_p, PWRDM_FUNC_PWRST_ON);
 
 	return 0;
 }
-- 
1.7.7.6



From jason77.wang at gmail.com  Wed Aug 15 06:31:45 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Wed, 15 Aug 2012 18:31:45 +0800
Subject: [PATCH v3 0/3] Input: egalax_ts: parse devicetree to get gpio
Message-ID: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>

V3:

Although have got Ack-by from driver author in the V2, i have to send
V3 since the driver is changed due to the change of a property name
in the dts.

As Shawn.guo suggested, i renamed property "irq-gpio" to "wakeup-gpios".
The reason is that, firstly the idiom of gpio naming in DT is *-gpios,
even though most of time, it could be just one gpio, secondly as the pin is
accessed as a gpio only in egalax_wake_up_device for waking up the device.

This time i send the patches both to linux-input and linux-arm, 0001 and
0002 belongs to linux-input, while the 0003 belongs to linux-arm.

V2:

Add return value checking for waking up the controller in the probe
function.

V1:

eeti touch screen controller is an external chip for most platforms,
it connect to CPU via i2c bus, and it has a irq request pin need to be
connected to a gpio of the CPU, this irq request pin also act as a
wake up signal for touch screen controller, we need to get this gpio
number and operate it to wake up the controller, the old way to get
gpio is irq_to_gpio(), this API is dying and most platforms don't support
it, we change it to a more generic way to use devcietree.

Hui Wang (3):
  Input: egalax_ts: get gpio from devicetree node
  Input: add devicetree binding note for egalax_ts
  ARM: dts: imx6q-sabrelite: add eeti egalax touchscreen

 .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++++++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |   16 ++++++++++++++++
 arch/arm/boot/dts/imx6q.dtsi                       |    7 +++++++
 drivers/input/touchscreen/egalax_ts.c              |   19 ++++++++++++++++---
 4 files changed, 58 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt

-- 
1.7.6



From jason77.wang at gmail.com  Wed Aug 15 06:31:46 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Wed, 15 Aug 2012 18:31:46 +0800
Subject: [PATCH v3 1/3] Input: egalax_ts: get gpio from devicetree node
In-Reply-To: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>

The irq_to_gpio() is old, most platforms use GENERIC_GPIO framework
and don't support this API anymore.

The i.MX6q sabrelite platform equips an egalax touchscreen controller,
and this platform already transfered to GENERIC_GPIO framework, to
support this driver, we use a more generic way to get gpio.

Add a return value checking for waking up the controller in the probe
function, this guarantee only a workable device can pass init.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 drivers/input/touchscreen/egalax_ts.c |   19 ++++++++++++++++---
 1 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
index 70524dd..54361c9 100644
--- a/drivers/input/touchscreen/egalax_ts.c
+++ b/drivers/input/touchscreen/egalax_ts.c
@@ -28,6 +28,7 @@
 #include <linux/slab.h>
 #include <linux/bitops.h>
 #include <linux/input/mt.h>
+#include <linux/of_gpio.h>
 
 /*
  * Mouse Mode: some panel may configure the controller to mouse mode,
@@ -122,8 +123,15 @@ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
 /* wake up controller by an falling edge of interrupt gpio.  */
 static int egalax_wake_up_device(struct i2c_client *client)
 {
-	int gpio = irq_to_gpio(client->irq);
-	int ret;
+	struct device_node *np = client->dev.of_node;
+	int gpio, ret;
+
+	if (!np)
+		return -ENODEV;
+
+	gpio = of_get_named_gpio(np, "wakeup-gpios", 0);
+	if (!gpio_is_valid(gpio))
+		return -ENODEV;
 
 	ret = gpio_request(gpio, "egalax_irq");
 	if (ret < 0) {
@@ -181,7 +189,12 @@ static int __devinit egalax_ts_probe(struct i2c_client *client,
 	ts->input_dev = input_dev;
 
 	/* controller may be in sleep, wake it up. */
-	egalax_wake_up_device(client);
+	ret = egalax_wake_up_device(client);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed to wake up the controller\n");
+		error = ret;
+		goto err_free_dev;
+	}
 
 	ret = egalax_firmware_version(client);
 	if (ret < 0) {
-- 
1.7.6



From jason77.wang at gmail.com  Wed Aug 15 06:31:47 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Wed, 15 Aug 2012 18:31:47 +0800
Subject: [PATCH v3 2/3] Input: add devicetree binding note for egalax_ts
In-Reply-To: <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>

The egalax_ts driver needs to get the gpio number of the irq pin,
and use this gpio to wake up the controller. So add a note
for this change.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt

diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
new file mode 100644
index 0000000..df70318
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
@@ -0,0 +1,19 @@
+* EETI eGalax Multiple Touch Controller
+
+Required properties:
+- compatible: must be "eeti,egalax_ts"
+- reg: i2c slave address
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: touch controller interrupt
+- wakeup-gpios: the gpio pin to be used for waking up the controller
+  as well as uased as irq pin
+
+Example:
+
+	egalax_ts at 04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <9 2>;
+		wakeup-gpios = <&gpio1 9 0>;
+	};
-- 
1.7.6



From jason77.wang at gmail.com  Wed Aug 15 06:31:48 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Wed, 15 Aug 2012 18:31:48 +0800
Subject: [PATCH v3 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345026708-14139-4-git-send-email-jason77.wang@gmail.com>

i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
touchscreen controller, add it as an i2c slave device in the dts.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |   16 ++++++++++++++++
 arch/arm/boot/dts/imx6q.dtsi          |    7 +++++++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..4a68e1f 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -54,6 +54,7 @@
 							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
 							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
 							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */
+							   972  0x10		/* MX6Q_PAD_GPIO_9__GPIO_1_9 */
 							   >;
 					};
 				};
@@ -115,6 +116,21 @@
 					VDDIO-supply = <&reg_3p3v>;
 				};
 			};
+
+			i2c at 021a8000 { /* I2C3 */
+				status = "okay";
+				clock-frequency = <100000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c3_1>;
+
+				egalax_ts at 04 {
+					compatible = "eeti,egalax_ts";
+					reg = <0x04>;
+					interrupt-parent = <&gpio1>;
+					interrupts = <9 2>;
+					wakeup-gpios = <&gpio1 9 0>;
+				};
+			};
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..6f833b3 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -552,6 +552,13 @@
 					};
 				};
 
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <1013 0x4001b8b1	/* MX6Q_PAD_GPIO_5__I2C3_SCL */
+							    1037 0x4001b8b1>;	/* MX6Q_PAD_GPIO_16__I2C3_SDA */
+					};
+				};
+
 				serial2 {
 					pinctrl_serial2_1: serial2grp-1 {
 						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
-- 
1.7.6



From artem.bityutskiy at linux.intel.com  Wed Aug 15 06:37:49 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 15 Aug 2012 13:37:49 +0300
Subject: [PATCH 1/2] mtd: lpc32xx_slc: Adjust to pl08x DMA interface
 changes
In-Reply-To: <1342095778-13403-2-git-send-email-stigge@antcom.de>
References: <1342095778-13403-1-git-send-email-stigge@antcom.de>
 <1342095778-13403-2-git-send-email-stigge@antcom.de>
Message-ID: <1345027069.3393.124.camel@sauron.fi.intel.com>

On Thu, 2012-07-12 at 14:22 +0200, Roland Stigge wrote:
> This patch adjusts the LPC32xx SLC NAND driver to the new pl08x DMA interface,
> fixing the compile error resulting from changed pl08x structures.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

This patch breaks compilation:

ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!

Please, send a fix. The defconfig I used is attached.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_LPC32XX=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
CONFIG_CPU_IDLE=y
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_AOUT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=m
CONFIG_MTD_TESTS=m
CONFIG_MTD_REDBOOT_PARTS=m
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=10000
CONFIG_MTD_AFS_PARTS=m
CONFIG_MTD_AR7_PARTS=m
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=m
CONFIG_FTL=m
CONFIG_NFTL=m
CONFIG_NFTL_RW=y
CONFIG_INFTL=m
CONFIG_RFD_FTL=m
CONFIG_SSFDC=m
CONFIG_SM_FTL=m
CONFIG_MTD_OOPS=m
CONFIG_MTD_SWAP=m
CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_ROM=m
CONFIG_MTD_ABSENT=m
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_OF=m
CONFIG_MTD_IMPA7=m
CONFIG_MTD_GPIO_ADDR=m
CONFIG_MTD_PLATRAM=m
CONFIG_MTD_LATCH_ADDR=m
CONFIG_MTD_DATAFLASH=m
CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
CONFIG_MTD_DATAFLASH_OTP=y
CONFIG_MTD_M25P80=m
# CONFIG_M25PXX_USE_FAST_READ is not set
CONFIG_MTD_SST25L=m
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_MTDRAM=m
CONFIG_MTD_BLOCK2MTD=m
CONFIG_MTD_DOC2000=m
CONFIG_MTD_DOC2001=m
CONFIG_MTD_DOC2001PLUS=m
CONFIG_MTD_DOCG3=m
CONFIG_MTD_DOCPROBE_ADVANCED=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND=m
CONFIG_MTD_NAND_MUSEUM_IDS=y
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_DISKONCHIP=m
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
CONFIG_MTD_NAND_DOCG4=m
CONFIG_MTD_NAND_SLC_LPC32XX=m
CONFIG_MTD_NAND_MLC_LPC32XX=m
CONFIG_MTD_NAND_NANDSIM=m
CONFIG_MTD_NAND_PLATFORM=m
CONFIG_MTD_ALAUDA=m
CONFIG_MTD_ONENAND=m
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=m
CONFIG_MTD_ONENAND_OTP=y
CONFIG_MTD_ONENAND_2X_PROGRAM=y
CONFIG_MTD_ONENAND_SIM=m
CONFIG_MTD_LPDDR=m
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
CONFIG_LPC_ENET=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_LPC32XX=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_SEQUENCER_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_LPC32XX=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_LPC32XX=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_STAGING=y
CONFIG_LPC32XX_ADC=y
CONFIG_IIO=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_JFFS2_FS_XATTR=y
# CONFIG_JFFS2_FS_POSIX_ACL is not set
# CONFIG_JFFS2_FS_SECURITY is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_LZO is not set
# CONFIG_UBIFS_FS_ZLIB is not set
CONFIG_LOGFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=y
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From dong.aisheng at linaro.org  Wed Aug 15 06:33:28 2012
From: dong.aisheng at linaro.org (Dong Aisheng)
Date: Wed, 15 Aug 2012 18:33:28 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815092539.GH19681@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
Message-ID: <CAP1dx+zgyvaCYHkFekK1W=J3Vcy-5Xu35wANK5JgtM69GK1xBQ@mail.gmail.com>

On 15 August 2012 17:25, Dong Aisheng <b29396 at freescale.com> wrote:
> On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
>> Hello,
>>
>> On Wed, Aug 15, 2012 at 02:55:27PM +0800, Dong Aisheng wrote:
>> > On Wed, Aug 15, 2012 at 07:44:36AM +0200, Uwe Kleine-K?nig wrote:
>> > > Hello,
>> > >
>> > > (Cc += devicetree-discuss at lists.ozlabs.org)
>> > >
>> > > On Wed, Aug 15, 2012 at 11:59:18AM +0800, Dong Aisheng wrote:
>> > > > On 15 August 2012 03:37, Matt Sealey <matt at genesi-usa.com> wrote:
>> > > > > On Tue, Aug 14, 2012 at 2:20 AM, Dong Aisheng <dong.aisheng at linaro.org> wrote:
>> > > > >> On 13 August 2012 23:12, Matt Sealey <matt at genesi-usa.com> wrote:
>> > > > >>> I have a minor nit; while renumbering the pinctrl definitions is
>> > > > >>> laudable and device trees can match, there are 16 other pin controls
>> > > > >>> below EIM_D16 - this makes the start of the IOMUXC pin definitions
>> > > > >>> actually be the value calculated by (iomuxc_base + 0x300 + (4*16) +
>> > > > >>> (pin_id*4)).
>> > > > >>
>> > > > >> What do you mean of this value calculated?
>> > > > >
>> > > > > Well, it just seems the datasheet has been read from the point of view
>> > > > > of the SW_CTRL settings (pad pullups, drive strength etc.) to define
>> > > > > the enums; every pin setting in order from IOMUXC_BASE + 0x3f0 (sorry
>> > > > > I mistyped) has been entered as an enum into this list. Then a table
>> > > > > has been generated using these enums to supply a pin id. Then this pin
>> > > > > id is not relevant anymore; it actually gets referenced by it's
>> > > > > *offset into the table*.
>> > > > >
>> > > > Not exactly, probably.
>> > > > Basically we follow the mux reigster offset to define pin id, however,
>> > > > there're also some pads may not have mux function but only config
>> > > > which also has a pin id
>> > > > and vice versa.
>> > > > Those pins are not ordered by it's mux regsiter offset.
>> > > >
>> > > > Actually I did not manually search all those pins, instead, i just
>> > > > using the exist ones:
>> > > > arch/arm/plat-mxc/include/mach/iomux-mx51.h
>> > > > Since this exist headfile already covers this case.
>> > > >
>> > > > > In this case, basically the code misses a few pins which have ALT
>> > > > > settings but perhaps not always the ability to change pad control -
>> > > > > EIM_DA5 to 15 are a good example.
>> > > > >
>> > > > As i said, we already defined those pin ids.
>> > > >
>> > > > > Probably better would be to define the binding almost exactly as it
>> > > > > was done in the old method; iomux_v3_cfg_t took into account the three
>> > > > > register offsets possible for the pin (SW_MUX_CTL, SW_PAD_CTL and IPP)
>> > > > > and the three values to be put into those registers.
>> > > > >
>> > > > > This has been reduced down in pinctrl to what I find quite strange,
>> > > > > which is a completely arbitrary pin "id" mapping, which indirectly
>> > > > > references an entry in a table by index which is why pin 1 as a start
>> > > > > looks odd.
>> > > > >
>> > > > Start with pin 1 is a bug which caused by my mistake during the early
>> > > > data conversion.
>> > > >
>> > > > > If the binding is entirely i.MX-specific or even i.MX51-specific then
>> > > > > why not define the pins in the device tree the "old" iomux_v3_cfg_t
>> > > > > way, which is the way they are in the table of imx_pin_regs;
>> > > > >
>> > > > >       IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /*
>> > > > > MX51_PAD_EIM_D16__AUD4_RXFS */
>> > > > >
>> > > > > 0x3f0 is the SW_PAD_CTL, 0x05c is the SW_MUX_CTL, 5 is the ALT mode,
>> > > > > 0x000 is the IPP reg, and 0 the IPP value.
>> > > > >
>> > > > > So fsl,iomux-pins = <0x3f0 0x85 0x05c 5 0 0 ... > (PAD, settings, MUX,
>> > > > > mode/sion, IPP, select - in that order) would be a valid pin
>> > > > > definition and require no table. Sure, the offsets are device specific
>> > > > > but then the arbitrary numbering is too.
>> > > > > This way old iomux controls
>> > > > > can be re-derived for people who use the old method in old kernels, or
>> > > > > use U-Boot with iomux-v3.h taken from Linux (MX6 got ported, I am
>> > > > > porting the Efika to it on MX5 for U-Boot right now). Also that huge
>> > > > > table goes away - it can be built at runtime, along with the
>> > > > > PAD_NAME__ALT_MODE_NAME description.
>> > > > >
>> > > > I can't agree this is better than the exist one now.
>> > > > It's hard to use in device tree.
>> > > > And how would you parse the pin id from this data array?
>> > > I admit I didn't follow completely the calculation suggestion by Matt,
>> > > but I think in general he has a point. This is more or less what I
>> > > thought when I built the imx35 pinctrl driver.
>> > >
>> > > With the current approach (i.e. put the pinfuncs in some order that
>> > > seems sensible today and then referencing them by index according to
>> > > that ordering) you really get into troubles if you have to add a new
>> > > function. You have to add it to the end to not break existing device
>> > > trees and so the ordering is broken.
>> > >
>> > Actually, we do not mean to maintain the ordering in driver.
>> > It just needs to be align with the pin func ids definitions in binding
>> > doc. So the ordering broken in driver is not an issue, it just looks
>> > not so better if we really have to add a new pin function to the end
>> > due to mistake but this does not break anything to work.
>> Well, if you add a function between say current function 11 and 12 all
>> device trees need fixing, i.e. increase all function ids >= 12 by one.
>> You obviously cannot fix out-of-tree users and even fixing the in-tree
>> users is ugly.
>>
> For such case, we should add it to the end since the exist ids are already
> taken. It will not break any user.
>
>> > > Also "11" has no obvious relation to MX35_PAD_COMPARE__SDMA_EXTDMA_2
>> > > other than a match if you grep over the binding docs (or the driver).
>> > > While "0x32c, 0x008, 7, 0x0, 0" is longer and looks more ugly the
>> > > mapping is obvious and so IMHO preferable.
>> > >
>> > Also, don't you think this is hard to use for devicetree?
>> Not harder than the current approach. Obviously macro support would be
>> nice, but this applies to both approaches.
>>
>> > And we need to reference datasheet to fill these values.
>> I'd list the explicit values in the binding docs as the indexes are
>> documented there now. So the difference for a device-tree writer is just
>> the content that is copy-and-pasted.
>>
>> > I just keep using as the old way at best and i remember Sascha also suggested
>> > before that we don't want to lose using the macro way as
>> > MX35_PAD_COMPARE__SDMA_EXTDMA_2 to make easy use.
>> > In the future, we will switch to macro when dt supports.
>> > For the way "0x32c, 0x008, 7, 0x0, 0", it's very unconveniently to use macro.
>> That is just
>>
>>       #define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
>>
>> vs.
>>
>>       #define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0
>>
>> isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
>> different story.)
>>
> Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
> Grant,
> Do you know if dt macro can support it?
>
Sorry, forget to add Grant.
Cc Grant.

Regards
Dong Aisheng

> Now I'm a bit intend to admit that we probably could do like that if it supports.
> The benefit i see is that it could save much code lines in driver while having
> no using experience downgrade.
>
> The left question is that how do we get the pin id from this kind of format data
> (0x32c, 0x008, 7, 0x0, 0), probably one way may be:
> For normal pads and NO_CONFIG pads, we could get it via:
> mux_reg_offset / 4
> for NO_MUX pads but have CONFIG pads, we may get it via:
> mux_reg_offset / 4 + PIN_NO_MUX_ID_BASE + config_reg_offset /4
> That may fix getting pin id issue from dt.
>
> Another known issue is that via this way, that means the pinctrl subsystem
> can only see the using pads, this is a bit not align with the pinctrl
> subsystem design. No sure if Linus would like to see it.
>
> Regards
> Dong Aisheng
>


From jason at lakedaemon.net  Wed Aug 15 07:12:09 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 07:12:09 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
Message-ID: <20120815111209.GB22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 09:36:57AM +0100, Alan M Butler wrote:
> 
> On 15 Aug 2012, at 00:56, Jason Cooper <jason at lakedaemon.net> wrote:
> 
> > On Tue, Aug 14, 2012 at 09:06:16PM +0100, Ownerx35 wrote:
> >> I have created a patch and have tested it myself that create a board
> >> setup file for the Iomega StoreCenter IX2-200, create a dts file and
> >> insert the appropriate lines into the common.h, makefile,
> >> makefile.boot, kconfig and board-ft files.
> > 
> > Awesome!
> > 
> >> But am unsure how to properly submit it should i just post it here? or
> >> is there a specific place i should post?
> > 
> > Take a look at /path/to/linux_src/Documentation/SubmittingPatches .
> > 
> > If you prefer working with git, the two commands I use are format-patch
> > and then send-email.
> > 
> > Assuming the board is ARM based (most likely), then you've found the
> > correct list.
> > 
> > Just post the series here and we'll offer helpful comments ;-)
> > 
> > Also, please check MAINTAINERS for the directories you are changing and
> > include the maintainers in the CC: or TO:.  Most likely, that'll be
> > myself and Andrew Lunn (kirkwood / orion boards).
> > 
> > hth,
> > 
> > Jason.
> 
> Sorry i meant board-dt in the previous message and the name just
> getting used to the mail program on os x aswel. I have run through the
> checkpatch.pl script and it tells me there are no errors but i just
> found out a few minutes ago theres a fix for the 2 sata ports not
> working (on all kirkwood devices as far as i know) so i am going to
> test that now as it envolves modifying a line in the dts file.

Ok.  Please let everyone know in the comment portion of the patch (after
the --- line) that your patch depends on this fix.  I haven't seen the
patch you're referring to yet.  I'll keep my eye out for it.

> Also it is defiantly an arm kirkwood device. My patch also does not
> modify any driver's or anything else just create's the appropriate
> file in the arch/am/boot/dts directory and the board config in the
> arch/arm/mach-kirkwood directory along with adding the lines to the
> appropriate files in that directory. So do i need to inform anyone
> else? the maintainers file is pretty long and i am unsure of what /
> who i am looking for in it.

Nope, sounds like you can just send it to the list, myself, and Andrew
Lunn.  Are you using git to generate the patch?  If not, I highly
recommend it.  I'm not sure about Apple Mail in particular, but most
graphical mail clients tend to mangle patches.

Here's a quick and dirty on what I do with git:

git clone \
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

cd linux

git checkout -b my_new_board v3.6-rc1

hack, hack, hack

mkdir /tmp/patches

git format-patch -o /tmp/patches/ --thread=shallow --cover-letter \
v3.6-rc1..HEAD

# edit /tmp/patches/0000-cover-letter.patch

./scripts/checkpatch.pl /tmp/patches/*.patch
	# ignore errors about patch 0000-cover-letter.patch
	# it's not a patch.

git send-email --to="$MY_EMAIL_ADDR" --smtp-server=$EMAIL_SRV \
--no-chain-reply-to --from="$MY_EMAIL_ADDR" /tmp/patches/*.patch
	# send to yourself first to make sure it looks correct,
	# applies properly from your email client, and is threaded
	# properly

# if it looks good, change the --to and --cc's in the above command to
# send it to me and Andrew, and cc the linux-arm-kernel list.

that's it.  If the list suggests any changes it's a lot easier to make
those changes once you have git set up.  Especially with a series of
patches.

hth,

Jason.


From hvaibhav at ti.com  Wed Aug 15 07:23:25 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 15 Aug 2012 16:53:25 +0530
Subject: [PATCH-V2] arm/dts: AM33XX: Set the default status of module to
 "disabled" state
Message-ID: <1345029805-27987-1-git-send-email-hvaibhav@ti.com>

Ideally in common SoC dtsi file should set all modules
to "disabled" state and it should get enabled in respective
EVM/Board dts file as per usage.

This patch sets default status of all modules to "disabled"
state in am33xx.dtsi file. Currently there are no modules
supported as part of Bone and EVM dts support, so care
to add entry "status = "okay"" while adding support for any
module.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Tony Lindgren <tony at atomide.com>
---
Changes from V1:
	- Fixed indentation issue caused due to extra spaces.

 arch/arm/boot/dts/am335x-bone.dts |    6 ++++++
 arch/arm/boot/dts/am335x-evm.dts  |    6 ++++++
 arch/arm/boot/dts/am33xx.dtsi     |    9 +++++++++
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db..a7906cb 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,10 @@
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
+
+	ocp {
+		uart1: serial at 44E09000 {
+			status = "okay";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9..5dd8a6b 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,10 @@
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
+
+	ocp {
+		uart1: serial at 44E09000 {
+			status = "okay";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c4..5f6c8e3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,36 +102,42 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart2: serial at 48022000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart3: serial at 48024000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart4: serial at 481A6000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart5: serial at 481A8000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		uart6: serial at 481AA000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
+			status = "disabled";
 		};

 		i2c1: i2c at 44E0B000 {
@@ -139,6 +145,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			status = "disabled";
 		};

 		i2c2: i2c at 4802A000 {
@@ -146,6 +153,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			status = "disabled";
 		};

 		i2c3: i2c at 4819C000 {
@@ -153,6 +161,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			status = "disabled";
 		};
 	};
 };
--
1.7.0.4



From josh.coombs at gmail.com  Wed Aug 15 07:55:42 2012
From: josh.coombs at gmail.com (Josh Coombs)
Date: Wed, 15 Aug 2012 07:55:42 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815111209.GB22226@titan.lakedaemon.net>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
Message-ID: <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>

>> Sorry i meant board-dt in the previous message and the name just
>> getting used to the mail program on os x aswel. I have run through the
>> checkpatch.pl script and it tells me there are no errors but i just
>> found out a few minutes ago theres a fix for the 2 sata ports not
>> working (on all kirkwood devices as far as i know) so i am going to
>> test that now as it envolves modifying a line in the dts file.
>
> Ok.  Please let everyone know in the comment portion of the patch (after
> the --- line) that your patch depends on this fix.  I haven't seen the
> patch you're referring to yet.  I'll keep my eye out for it.

What he's referring to is needing to up the coherent_pool size to get
a Kirkwood device with two SATA ports to init completely.  I brought
the topic up on arm-kernel under the subject 'Potential Regression in
3.6-rc1 - Kirkwood SATA' and Aaro Koskinen suggested the root cause
and potential fix of adding coherent_pool=1M to the bootargs.  I
didn't think to cc you in the discussion, sorry about that.  So there
isn't a pending patch yet, just a suggestion of altered bootargs.

Josh Coombs


From jason at lakedaemon.net  Wed Aug 15 08:11:45 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 08:11:45 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
Message-ID: <20120815121145.GC22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 07:55:42AM -0400, Josh Coombs wrote:
> >> Sorry i meant board-dt in the previous message and the name just
> >> getting used to the mail program on os x aswel. I have run through the
> >> checkpatch.pl script and it tells me there are no errors but i just
> >> found out a few minutes ago theres a fix for the 2 sata ports not
> >> working (on all kirkwood devices as far as i know) so i am going to
> >> test that now as it envolves modifying a line in the dts file.
> >
> > Ok.  Please let everyone know in the comment portion of the patch (after
> > the --- line) that your patch depends on this fix.  I haven't seen the
> > patch you're referring to yet.  I'll keep my eye out for it.
> 
> What he's referring to is needing to up the coherent_pool size to get
> a Kirkwood device with two SATA ports to init completely.  I brought
> the topic up on arm-kernel under the subject 'Potential Regression in
> 3.6-rc1 - Kirkwood SATA' and Aaro Koskinen suggested the root cause
> and potential fix of adding coherent_pool=1M to the bootargs.  I
> didn't think to cc you in the discussion, sorry about that.  So there
> isn't a pending patch yet, just a suggestion of altered bootargs.

Yes, I saw that discussion.  Setting coherent_pool=1M was a way of
diagnosing the problem.  It allowed the system to boot, which tells us
where the problem lies.  But it did not fix the problem in the code.
*That's* the patch I was referring to.  Which I haven't seen, yet. ;-)

thx,

Jason.


From jason at lakedaemon.net  Wed Aug 15 08:18:01 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 08:18:01 -0400
Subject: [PATCH] ARM: Dove: allow PCI to be disabled
In-Reply-To: <20120815085709.GI18957@n2100.arm.linux.org.uk>
References: <20120815085709.GI18957@n2100.arm.linux.org.uk>
Message-ID: <20120815121801.GD22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 09:57:09AM +0100, Russell King - ARM Linux wrote:
> Allow PCI support for Dove to be disabled.  Some platforms do not have
> anything connected to the PCIe ports, so requiring PCI support to be
> built into the kernel just wastes space, and presents a lot more config
> options than are necessary.
> 
> However, select USB_ARCH_HAS_EHCI so that we can still have EHCI
> support.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  arch/arm/Kconfig            |    3 ++-
>  arch/arm/mach-dove/Makefile |    3 ++-
>  arch/arm/mach-dove/common.h |    4 ++++
>  3 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 27f5b2c..344d40e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -536,14 +536,15 @@ config ARCH_IXP4XX
>  config ARCH_DOVE
>  	bool "Marvell Dove"
>  	select CPU_V7
> -	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
>  	select GENERIC_CLOCKEVENTS
> +	select MIGHT_HAVE_PCI
>  	select NEED_MACH_IO_H
>  	select PLAT_ORION
>  	select CLKDEV_LOOKUP
>  	select NEED_MACH_MEMORY_H
>  	select COMMON_CLK
> +	select USB_ARCH_HAS_EHCI
>  	help
>  	  Support for the Marvell Dove SoC 88AP510
>  
> diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
> index 7d89269..b5a5773 100644
> --- a/arch/arm/mach-dove/Makefile
> +++ b/arch/arm/mach-dove/Makefile
> @@ -1,4 +1,5 @@
> -obj-y				+= common.o addr-map.o irq.o pcie.o mpp.o clock.o dump_cp15_regs.o
> +obj-y				+= common.o addr-map.o irq.o mpp.o clock.o dump_cp15_regs.o
> +obj-$(CONFIG_PCI)		+= pcie.o
>  
>  obj-$(CONFIG_MACH_DOVE_DB)	+= dove-db-setup.o
>  obj-$(CONFIG_MACH_CM_A510)	+= cm-a510.o
> diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
> index 2ea271d..17404a0 100644
> --- a/arch/arm/mach-dove/common.h
> +++ b/arch/arm/mach-dove/common.h
> @@ -29,7 +29,11 @@ void dove_setup_cpu_mbus(void);
>  void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
>  void dove_hwmon_init(void);
>  void dove_sata_init(struct mv_sata_platform_data *sata_data);
> +#ifdef CONfig_PCI

ummm...   ^^^^^^ is this a typo?  (/me dives into a trench)

>  void dove_pcie_init(int init_port0, int init_port1);
> +#else
> +static inline void dove_pcie_init(int init_port0, int init_port1) { }
> +#endif
>  void dove_ehci0_init(void);
>  void dove_ehci1_init(void);
>  void dove_uart0_init(void);

thx,

Jason.


From bhelgaas at google.com  Wed Aug 15 08:18:04 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 15 Aug 2012 05:18:04 -0700
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
 <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>

On Tue, Aug 14, 2012 at 11:37 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
>> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
>> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
>> >> index a094c97..c886dff 100644
>> >> --- a/arch/arm/boot/dts/tegra20.dtsi
>> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
>> >> @@ -199,6 +199,68 @@
>> >>               #size-cells = <0>;
>> >>       };
>> >>
>> >> +     pcie-controller {
>> >> +             compatible = "nvidia,tegra20-pcie";
>> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
>> >> +                    0x80003800 0x00000200   /* AFI registers */
>> >> +                    0x81000000 0x01000000   /* configuration space */
>> >> +                    0x90000000 0x10000000>; /* extended configuration space */
>> >> +             interrupts = <0 98 0x04   /* controller interrupt */
>> >> +                           0 99 0x04>; /* MSI interrupt */
>> >> +             status = "disabled";
>> >> +
>> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
>> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
>> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
>> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
>> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
>> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
>> >> +
>> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
>> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
>> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
>> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
>> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
>> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
>> >
>> > I've been thinking about this some more. The translations for both the
>> > regular and extended configuration spaces are configured in the top-
>> > level PCIe controller. It is therefore wrong how they are passed to the
>> > PCI host bridges via the ranges property.
>> >
>> > I remember Mitch saying that it should be passed down to the children
>> > because it is partitioned among them, but since the layout is compatible
>> > with ECAM, the partitioning isn't as simple as what's in the tree. In
>> > fact the partitions will be dependent on the number of devices attached
>> > to the host bridges.
>>
>> I don't understand this last bit about the number of devices attached
>> to the host bridges.  Logically, the host bridge has a bus number
>> aperture that you can know up front, even before you know anything
>> about what devices are below it.  On x86, for example, the ACPI _CRS
>> method has something like "[bus 00-7f]" in it, which means that any
>> buses in that range are below this bridge.  That doesn't tell us
>> anything about which buses actually have devices on them, of course;
>> it's just analogous to the secondary and subordinate bus number
>> registers in a P2P bridge.
>
> That's one of the issues I still need to take care of. Currently no bus
> resource is attached to the individual bridges (nor the PCI controller
> for that matter), so the PCI core will assign them dynamically.

So your PCI controller driver knows how to program the controller bus
number aperture?  Sometimes people start by assuming that two host
bridges both have [bus 00-ff] apertures, then they enumerate below the
first and adjust the bus number apertures based on what they found.
For example, if they found buses 00-12 behind the first bridge, they
make the apertures [bus 00-12] for the first bridge and [bus 13-ff]
for the second.  That might be the case, depending on what firmware
set up, but it seems like a dubious way to do it, and of course it
precludes a lot of hot-plug scenarios.

> If this
> range is known at boot time we could assign ECAM ranges based on the bus
> numbers. Standard ECAM ranges, that is. On Tegra this won't work because
> as Stephen mentioned in a previous mail, the bus field is not the top
> field in the ECAM addresses. Basically what you have is this:
>
>         [27:24] upper 4 bits of the register address for extended
>                 configuration space
>         [23:16] bus number
>         [15:11] device number
>         [10: 8] device function
>         [ 8: 0] register
>
> So the ECAM space cannot be partitioned by bus number.

Ah, OK, so definitely not standard PCIe ECAM.

Bjorn


From arnd at arndb.de  Wed Aug 15 08:30:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:30:24 +0000
Subject: [GIT PULL] Ux500 ASIC ID patches
In-Reply-To: <CACRpkdZ1+vjrTQC9-M9icO7p9POg-zcR_gUpkyemF4da3jny2w@mail.gmail.com>
References: <CACRpkdZ1+vjrTQC9-M9icO7p9POg-zcR_gUpkyemF4da3jny2w@mail.gmail.com>
Message-ID: <201208151230.24523.arnd@arndb.de>

On Monday 13 August 2012, Linus Walleij wrote:
> could you please pull the following patch set into ARM SoC as a first
> step for the
> next merge window. This cleans up, updates and structure the use of some ASIC ID
> detection macros so they are understandable and consistent.
> 
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git ux500-core

Pulled, thanks!

I think it would be nice if you could move to using signed tags in
the future, and include the text you want to see in the merge
commit in that tag.

	Arnd


From thierry.reding at avionic-design.de  Wed Aug 15 08:30:22 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 14:30:22 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
 <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
 <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
Message-ID: <20120815123022.GA8678@avionic-0098.adnet.avionic-design.de>

On Wed, Aug 15, 2012 at 05:18:04AM -0700, Bjorn Helgaas wrote:
> On Tue, Aug 14, 2012 at 11:37 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
> >> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
> >> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> >> >> index a094c97..c886dff 100644
> >> >> --- a/arch/arm/boot/dts/tegra20.dtsi
> >> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
> >> >> @@ -199,6 +199,68 @@
> >> >>               #size-cells = <0>;
> >> >>       };
> >> >>
> >> >> +     pcie-controller {
> >> >> +             compatible = "nvidia,tegra20-pcie";
> >> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
> >> >> +                    0x80003800 0x00000200   /* AFI registers */
> >> >> +                    0x81000000 0x01000000   /* configuration space */
> >> >> +                    0x90000000 0x10000000>; /* extended configuration space */
> >> >> +             interrupts = <0 98 0x04   /* controller interrupt */
> >> >> +                           0 99 0x04>; /* MSI interrupt */
> >> >> +             status = "disabled";
> >> >> +
> >> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
> >> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
> >> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
> >> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
> >> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
> >> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
> >> >> +
> >> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
> >> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
> >> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
> >> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
> >> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
> >> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
> >> >
> >> > I've been thinking about this some more. The translations for both the
> >> > regular and extended configuration spaces are configured in the top-
> >> > level PCIe controller. It is therefore wrong how they are passed to the
> >> > PCI host bridges via the ranges property.
> >> >
> >> > I remember Mitch saying that it should be passed down to the children
> >> > because it is partitioned among them, but since the layout is compatible
> >> > with ECAM, the partitioning isn't as simple as what's in the tree. In
> >> > fact the partitions will be dependent on the number of devices attached
> >> > to the host bridges.
> >>
> >> I don't understand this last bit about the number of devices attached
> >> to the host bridges.  Logically, the host bridge has a bus number
> >> aperture that you can know up front, even before you know anything
> >> about what devices are below it.  On x86, for example, the ACPI _CRS
> >> method has something like "[bus 00-7f]" in it, which means that any
> >> buses in that range are below this bridge.  That doesn't tell us
> >> anything about which buses actually have devices on them, of course;
> >> it's just analogous to the secondary and subordinate bus number
> >> registers in a P2P bridge.
> >
> > That's one of the issues I still need to take care of. Currently no bus
> > resource is attached to the individual bridges (nor the PCI controller
> > for that matter), so the PCI core will assign them dynamically.
> 
> So your PCI controller driver knows how to program the controller bus
> number aperture?  Sometimes people start by assuming that two host
> bridges both have [bus 00-ff] apertures, then they enumerate below the
> first and adjust the bus number apertures based on what they found.
> For example, if they found buses 00-12 behind the first bridge, they
> make the apertures [bus 00-12] for the first bridge and [bus 13-ff]
> for the second.  That might be the case, depending on what firmware
> set up, but it seems like a dubious way to do it, and of course it
> precludes a lot of hot-plug scenarios.

No, that's not what I meant. What happens is that no pre-assigned bus
range is specified for either of the host bridges, so that the range
0x00-0xff will be assigned by default in pci_scan_root_bus(). If I
understand correctly, what needs to be done is partition the bus range
between the two bridges (equally?). That would allow hot-plug scenarios
and be more in line with how other architectures do things.

I don't know if the Tegra PCIe controller supports hot-plug, though, so
maybe that wouldn't even be an issue and dynamic assignment would be
okay.

Thierry
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From arnd at arndb.de  Wed Aug 15 08:32:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:32:36 +0000
Subject: [GIT PULL] omap fixes for v3.6-rc1
In-Reply-To: <20120814084314.GH11011@atomide.com>
References: <20120814084314.GH11011@atomide.com>
Message-ID: <201208151232.36587.arnd@arndb.de>

On Tuesday 14 August 2012, Tony Lindgren wrote:
> Here are some omap fixes, these are probably too late for -rc1,
> we're fine getting them in for -rc2 as well.
> 
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-fixes-for-v3.6-rc1
> 

Applied, thanks!

I'll probably send these out in the next few days, whichever -rc that
ends up being.

	Arnd


From markus at oberhumer.com  Wed Aug 15 08:02:43 2012
From: markus at oberhumer.com (Markus F.X.J. Oberhumer)
Date: Wed, 15 Aug 2012 14:02:43 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120814123937.GA14756@sig21.net>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
Message-ID: <502B8FE3.7080501@oberhumer.com>

Hi Johannes,

On 2012-08-14 14:39, Johannes Stezenbach wrote:
> On Tue, Aug 14, 2012 at 01:44:02AM +0200, Markus F.X.J. Oberhumer wrote:
>> On 2012-07-16 20:30, Markus F.X.J. Oberhumer wrote:
>>>
>>> As stated in the README this version is significantly faster (typically more
>>> than 2 times faster!) than the current version, has been thoroughly tested on
>>> x86_64/i386/powerpc platforms and is intended to get included into the
>>> official Linux 3.6 or 3.7 release.
>>>
>>> I encourage all compression users to test and benchmark this new version,
>>> and I also would ask some official LZO maintainer to convert the updated
>>> source files into a GIT commit and possibly push it to Linus or linux-next.
> 
> Sorry for not reporting earlier, but I didn't have time to do real
> benchmarks, just a quick test on ARM926EJ-S using barebox,
> and found in the new version decompression is slower:
> http://lists.infradead.org/pipermail/barebox/2012-July/008268.html

I can only guess, but maybe your ARM cpu does not have an efficient
implementation of {get,put}_unaligned().

Could you please try the following patch and test if you can see
any significant speed difference?

Thanks,
Markus


diff --git a/lib/lzo/lzodefs.h b/lib/lzo/lzodefs.h
index ddc8db5..efc5714 100644
--- a/lib/lzo/lzodefs.h
+++ b/lib/lzo/lzodefs.h
@@ -12,8 +12,15 @@
  */


+#if defined(__arm__)
+#define COPY4(dst, src)        \
+               (dst)[0] = (src)[0]; (dst)[1] = (src)[1]; \
+               (dst)[2] = (src)[2]; (dst)[3] = (src)[3]
+#endif
+#ifndef COPY4
 #define COPY4(dst, src)        \
                put_unaligned(get_unaligned((const u32 *)(src)), (u32 *)(dst))
+#endif
 #if defined(__x86_64__)
 #define COPY8(dst, src)        \
                put_unaligned(get_unaligned((const u64 *)(src)), (u64 *)(dst))


> 
> BTW, do you have userspace code matching the old and new
> lzo versions?  It would be easier to benchmark.
> 
> Unfortunately I cannot claim high confidence in my benchmark results
> due to missing time to do it properly, it would be useful if
> someone else could do some benchmarks on ARM before merging this.
> 
> 
> Johannes 

-- 
Markus Oberhumer, <markus at oberhumer.com>, http://www.oberhumer.com/


From arnd at arndb.de  Wed Aug 15 08:37:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:37:56 +0000
Subject: [GIT PULL] orion/kirkwood fixes for v3.6
In-Reply-To: <20120814234442.GZ22226@titan.lakedaemon.net>
References: <20120814234442.GZ22226@titan.lakedaemon.net>
Message-ID: <201208151237.56639.arnd@arndb.de>

On Tuesday 14 August 2012, Jason Cooper wrote:
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
> 

Pulled, thanks!

As soon as you have a pgp key that is signed by other maintainers,
I think you should start sending signed tags instead of branches,
and include a short description for what is in the branch you are
sending. I've started adding descriptions for every merge I do
and it's easier for me if I don't have to write it myself.

The first patch in your series (ARM: Orion: Set eth packet size
csum offload limit) looks like it should apply to older kernels
as well. In those cases, please add "Cc: stable at vger.kernel.org"
below the Signed-off-by lines (but not in the email submission)
so it can get picked up by Greg for the longterm and stable
releases.

	Arnd


From alanbutty12 at gmail.com  Wed Aug 15 08:43:24 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Wed, 15 Aug 2012 13:43:24 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815121145.GC22226@titan.lakedaemon.net>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
Message-ID: <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>

On 15 August 2012 13:11, Jason Cooper <jason at lakedaemon.net> wrote:
>
> On Wed, Aug 15, 2012 at 07:55:42AM -0400, Josh Coombs wrote:
> > >> Sorry i meant board-dt in the previous message and the name just
> > >> getting used to the mail program on os x aswel. I have run through the
> > >> checkpatch.pl script and it tells me there are no errors but i just
> > >> found out a few minutes ago theres a fix for the 2 sata ports not
> > >> working (on all kirkwood devices as far as i know) so i am going to
> > >> test that now as it envolves modifying a line in the dts file.
> > >
> > > Ok.  Please let everyone know in the comment portion of the patch (after
> > > the --- line) that your patch depends on this fix.  I haven't seen the
> > > patch you're referring to yet.  I'll keep my eye out for it.
> >
> > What he's referring to is needing to up the coherent_pool size to get
> > a Kirkwood device with two SATA ports to init completely.  I brought
> > the topic up on arm-kernel under the subject 'Potential Regression in
> > 3.6-rc1 - Kirkwood SATA' and Aaro Koskinen suggested the root cause
> > and potential fix of adding coherent_pool=1M to the bootargs.  I
> > didn't think to cc you in the discussion, sorry about that.  So there
> > isn't a pending patch yet, just a suggestion of altered bootargs.
>
> Yes, I saw that discussion.  Setting coherent_pool=1M was a way of
> diagnosing the problem.  It allowed the system to boot, which tells us
> where the problem lies.  But it did not fix the problem in the code.
> *That's* the patch I was referring to.  Which I haven't seen, yet. ;-)
>
> thx,
>
> Jason.


I could not get the way to use git figured out so i will send the
patch here though the browser based gmail interface and hope i do not
cause or get in too much trouble. And my patch contains that part of
the altered bootargs so i hope that wont cause a problem either.
Theres a couple of lines at the end that are something dto do with my
attemp at using your earlier instructions.

diff -urN linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
--- linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
1970-01-01 01:00:00.000000000 +0100
+++ linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts    2012-08-15
10:17:35.000000000 +0100
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+    model = "Iomega StorCenter ix2-200";
+    compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+    memory {
+        device_type = "memory";
+        reg = <0x00000000 0x10000000>;
+    };
+
+    chosen {
+        bootargs = "console=ttyS0,115200n8 earlyprintk
root=LABEL=ROOTFS coherent_pool=1M";
+    };
+
+    ocp at f1000000 {
+        i2c at 11000 {
+            status = "okay";
+
+            lm63: lm63 at 4c {
+                compatible = "national,lm63";
+                reg = <0x4c>;
+            };
+        };
+
+        serial at 12000 {
+            clock-frequency = <200000000>;
+            status = "ok";
+        };
+
+        nand at 3000000 {
+            status = "okay";
+
+            partition at 100000 {
+                label = "uImage";
+                reg = <0x100000 0x300000>;
+                read-only;
+            };
+
+            partition at 400000 {
+                label = "uInitrd";
+                reg = <0x540000 0x1000000>;
+            };
+        };
+        sata at 80000 {
+            compatible = "marvell,orion-sata";
+            reg = <0x80000 0x5000>;
+            interrupts = <21>;
+            status = "okay";
+            nr-ports = <2>;
+        };
+
+    };
+    gpio-leds {
+        compatible = "gpio-leds";
+
+        power_led {
+            label = "status:white:power_led";
+            gpios = <&gpio0 16 0>;
+            linux,default-trigger = "default-on";
+        };
+        rebuild_led {
+            label = "status:white:rebuild_led";
+            gpios = <&gpio1 5 0>;
+        };
+        health_led {
+            label = "status:red:health_led";
+            gpios = <&gpio1 6 0>;
+        };
+        backup_led {
+            label = "status:blue:backup_led";
+            gpios = <&gpio0 15 0>;
+        };
+    };
+};
diff -urN linuxorig//arch/arm/mach-kirkwood/board-dt.c
linux//arch/arm/mach-kirkwood/board-dt.c
--- linuxorig//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
12:48:11.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
13:17:47.000000000 +0100
@@ -87,6 +87,9 @@
    if (of_machine_is_compatible("buffalo,lsxl"))
        lsxl_init();

+    if (of_machine_is_compatible("iom,ix2-200"))
+        iomega_ix2_200_init();
+
    of_platform_populate(NULL, kirkwood_dt_match_table,
                 kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@
    "qnap,ts219",
    "seagate,goflexnet",
    "buffalo,lsxl",
+    "iom,ix2-200",
    NULL
 };

diff -urN linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
--- linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
1970-01-01 01:00:00.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c    2012-08-15
10:16:55.000000000 +0100
@@ -0,0 +1,138 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <net/dsa.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+    .phy_addr       = MV643XX_ETH_PHY_NONE,
+    .speed          = SPEED_1000,
+    .duplex         = DUPLEX_FULL,
+};
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
+    .phy_addr    = MV643XX_ETH_PHY_ADDR(11),
+};
+
+/****************************************************************************
+ * GPIO Attached Keys
+ ****************************************************************************/
+
+#define iomega_ix2_200_GPIO_KEY_RESET    12
+#define iomega_ix2_200_GPIO_KEY_POWER    14
+#define iomega_ix2_200_GPIO_KEY_OTB        35
+
+#define iomega_ix2_200_SW_RESET    0x00
+#define iomega_ix2_200_SW_POWER    0x01
+#define iomega_ix2_200_SW_OTB    0x02
+
+static struct gpio_keys_button iomega_ix2_200_buttons[] = {
+    {
+        .type        = EV_SW,
+        .code       = iomega_ix2_200_SW_RESET,
+        .gpio       = iomega_ix2_200_GPIO_KEY_RESET,
+        .desc       = "Reset Button",
+        .active_low     = 1,
+        .debounce_interval = 100,
+    },
+    {
+        .type        = EV_SW,
+        .code       = iomega_ix2_200_SW_POWER,
+        .gpio       = iomega_ix2_200_GPIO_KEY_POWER,
+        .desc       = "Power Button",
+        .active_low     = 1,
+        .debounce_interval = 100,
+    },
+    {
+        .type        = EV_SW,
+        .code       = iomega_ix2_200_SW_OTB,
+        .gpio       = iomega_ix2_200_GPIO_KEY_OTB,
+        .desc       = "OTB Button",
+        .active_low     = 1,
+        .debounce_interval = 100,
+    },
+
+};
+
+static struct gpio_keys_platform_data iomega_ix2_200_button_data = {
+    .buttons    = iomega_ix2_200_buttons,
+    .nbuttons       = ARRAY_SIZE(iomega_ix2_200_buttons),
+};
+
+static struct platform_device iomega_ix2_200_button_device = {
+    .name       = "gpio-keys",
+    .id         = -1,
+    .num_resources  = 0,
+    .dev        = {
+        .platform_data  = &iomega_ix2_200_button_data,
+    },
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+    MPP12_GPIO,                             /* Reset Button */
+    MPP14_GPIO,                             /* Power Button */
+    MPP15_GPIO,                             /* Backup LED (blue) */
+    MPP16_GPIO,                             /* Power LED (white) */
+    MPP35_GPIO,                             /* OTB Button */
+    MPP36_GPIO,                             /* Rebuild LED (white) */
+    MPP37_GPIO,                             /* Health LED (red) */
+    MPP38_GPIO,                             /* SATA LED brightness control 1 */
+    MPP39_GPIO,                             /* SATA LED brightness control 2 */
+    MPP40_GPIO,                             /* Backup LED brightness
control 1 */
+    MPP41_GPIO,                             /* Backup LED brightness
control 2 */
+    MPP42_GPIO,                             /* Power LED brightness
control 1 */
+    MPP43_GPIO,                             /* Power LED brightness
control 2 */
+    MPP44_GPIO,                             /* Health LED brightness
control 1 */
+    MPP45_GPIO,                             /* Health LED brightness
control 2 */
+    MPP46_GPIO,                             /* Rebuild LED brightness
control 1 */
+    MPP47_GPIO,                             /* Rebuild LED brightness
control 2 */
+    0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+    /*
+     * Basic setup. Needs to be called early.
+     */
+    kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+    kirkwood_ehci_init();
+
+    kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
+    kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
+    kirkwood_uart0_init();
+    platform_device_register(&iomega_ix2_200_button_device);
+}
+
+static int __init iomega_ix2_200_pci_init(void)
+{
+    if (of_machine_is_compatible("iom,ix2-200"))
+        kirkwood_pcie_init(KW_PCIE0);
+    return 0;
+}
+subsys_initcall(iomega_ix2_200_pci_init);
+
diff -urN linuxorig//arch/arm/mach-kirkwood/common.h
linux//arch/arm/mach-kirkwood/common.h
--- linuxorig//arch/arm/mach-kirkwood/common.h    2012-08-15
12:48:11.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/common.h    2012-08-15
12:54:07.000000000 +0100
@@ -94,6 +94,12 @@
 static inline void lsxl_init(void) {};
 #endif

+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff -urN linuxorig//arch/arm/mach-kirkwood/Kconfig
linux//arch/arm/mach-kirkwood/Kconfig
--- linuxorig//arch/arm/mach-kirkwood/Kconfig    2012-08-15
12:48:11.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/Kconfig    2012-08-15 12:54:55.000000000 +0100
@@ -195,6 +195,13 @@
      Say 'Y' here if you want your kernel to support the
      HP t5325 Thin Client.

+config MACH_IOMEGA_IX2_200_DT
+    bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+    select ARCH_KIRKWOOD_DT
+    help
+      Say 'Y' here if you want your kernel to support the
+      Iomega StorCenter ix2-200 (Flattened Device Tree).
+
 endmenu

 endif
diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile
linux//arch/arm/mach-kirkwood/Makefile
--- linuxorig//arch/arm/mach-kirkwood/Makefile    2012-08-15
12:48:11.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/Makefile    2012-08-15
12:55:17.000000000 +0100
@@ -28,3 +28,4 @@
 obj-$(CONFIG_MACH_TS219_DT)        += board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)        += board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)        += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile.boot
linux//arch/arm/mach-kirkwood/Makefile.boot
--- linuxorig//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
13:07:03.000000000 +0100
+++ linux//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
12:55:43.000000000 +0100
@@ -11,3 +11,4 @@
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
Binary files linuxorig//.git/index and linux//.git/index differ
diff -urN linuxorig//.git/logs/HEAD linux//.git/logs/HEAD
--- linuxorig//.git/logs/HEAD    2012-08-15 13:07:03.000000000 +0100
+++ linux//.git/logs/HEAD    2012-08-15 12:51:41.000000000 +0100
@@ -1,2 +1,2 @@
 0000000000000000000000000000000000000000
ddf343f635fe4440cad528e12f96f28bd50aa099 ownerx35
<ownerx35 at ownerx35-VirtualBox.(none)> 1345031290 +0100    clone: from
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
-ddf343f635fe4440cad528e12f96f28bd50aa099
0d7614f09c1ebdbaa1599a5aba7593f147bf96ee ownerx35
<ownerx35 at ownerx35-VirtualBox.(none)> 1345032423 +0100    checkout:
moving from master to iomega_ix2_200
+ddf343f635fe4440cad528e12f96f28bd50aa099
0d7614f09c1ebdbaa1599a5aba7593f147bf96ee ownerx35
<ownerx35 at ownerx35-VirtualBox.(none)> 1345031501 +0100    checkout:
moving from master to iomega_ix2_200
diff -urN linuxorig//.git/logs/refs/heads/iomega_ix2_200
linux//.git/logs/refs/heads/iomega_ix2_200
--- linuxorig//.git/logs/refs/heads/iomega_ix2_200    2012-08-15
13:07:03.000000000 +0100
+++ linux//.git/logs/refs/heads/iomega_ix2_200    2012-08-15
12:51:41.000000000 +0100
@@ -1 +1 @@
-0000000000000000000000000000000000000000
0d7614f09c1ebdbaa1599a5aba7593f147bf96ee ownerx35
<ownerx35 at ownerx35-VirtualBox.(none)> 1345032423 +0100    branch:
Created from v3.6-rc1
+0000000000000000000000000000000000000000
0d7614f09c1ebdbaa1599a5aba7593f147bf96ee ownerx35
<ownerx35 at ownerx35-VirtualBox.(none)> 1345031501 +0100    branch:
Created from v3.6-rc1

Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>


From arnd at arndb.de  Wed Aug 15 08:43:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:43:40 +0000
Subject: [GIT PULL] U300 cleanups and sparseirq
In-Reply-To: <CACRpkdb6wB1QVNqn8_sHB8LH0To=aP_8+iocE8JZ2jKC5f_bYg@mail.gmail.com>
References: <CACRpkdb6wB1QVNqn8_sHB8LH0To=aP_8+iocE8JZ2jKC5f_bYg@mail.gmail.com>
Message-ID: <201208151243.40386.arnd@arndb.de>

On Wednesday 15 August 2012, Linus Walleij wrote:
> Hi ARM SoC maintainers,
> 
> could you please pull the following patch set sent out for review the other day
> doing a number of cleanups and a minor improvement to U300, paving the
> way for single zImage and device tree:
> 
> - Deprecate ancient platforms to make the following patches easier to
>   make...
> - Move out one header to platform data and one to the mach-u300 proper
>   to depopulate <mach/*>
> - Consolidate core machine files
> - Convert to sparse IRQs

Pulled into next/soc. Very cool stuff!

	Arnd


From arnd at arndb.de  Wed Aug 15 08:49:41 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:49:41 +0000
Subject: [GIT PULL] U300 cleanups and sparseirq
In-Reply-To: <201208151243.40386.arnd@arndb.de>
References: <CACRpkdb6wB1QVNqn8_sHB8LH0To=aP_8+iocE8JZ2jKC5f_bYg@mail.gmail.com>
 <201208151243.40386.arnd@arndb.de>
Message-ID: <201208151249.42011.arnd@arndb.de>

On Wednesday 15 August 2012, Arnd Bergmann wrote:
> On Wednesday 15 August 2012, Linus Walleij wrote:
> > Hi ARM SoC maintainers,
> > 
> > could you please pull the following patch set sent out for review the other day
> > doing a number of cleanups and a minor improvement to U300, paving the
> > way for single zImage and device tree:
> > 
> > - Deprecate ancient platforms to make the following patches easier to
> >   make...
> > - Move out one header to platform data and one to the mach-u300 proper
> >   to depopulate <mach/*>
> > - Consolidate core machine files
> > - Convert to sparse IRQs
> 
> Pulled into next/soc.

On second thought, I've changed that and put it into next/cleanup instead.

	Arnd


From broonie at opensource.wolfsonmicro.com  Wed Aug 15 08:53:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 15 Aug 2012 13:53:39 +0100
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
Message-ID: <20120815125338.GA13544@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 02:25:18PM +0000, AnilKumar, Chimata wrote:

> AM335x EVM have one dedicated input supply which provide supplies to all
> the PMIC regulators. According to tps65910 "VDD1 regulator" input supply
> is from vcc1 so we have to create a dummy/parent/some node to handle this.
> Example below has the details.

Your device tree should accurately reflect the hardware.

> Similarly we have to add 7 more fixed regulators entries to provide input
> supply to different PMIC regulators.

If you have all these unrelated supplies in the system then your device
tree should accurately reflect that.  However this would be a very
unusual hardware design.  Usually there would be a very small set of
system supply rails, frequently only one.


From shawn.guo at linaro.org  Wed Aug 15 08:53:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 20:53:56 +0800
Subject: [PATCH v3 2/3] Input: add devicetree binding note for egalax_ts
In-Reply-To: <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <20120815125353.GA2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 06:31:47PM +0800, Hui Wang wrote:
> The egalax_ts driver needs to get the gpio number of the irq pin,
> and use this gpio to wake up the controller. So add a note
> for this change.
> 
> Signed-off-by: Hui Wang <jason77.wang at gmail.com>
> ---
>  .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++++++
>  1 files changed, 19 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
> 
> diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
> new file mode 100644
> index 0000000..df70318
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
> @@ -0,0 +1,19 @@
> +* EETI eGalax Multiple Touch Controller
> +
> +Required properties:
> +- compatible: must be "eeti,egalax_ts"

Since we define this in the binding anyway, can we have an corresponding
.of_match_table in the driver?

Regards,
Shawn

> +- reg: i2c slave address
> +- interrupt-parent: the phandle for the interrupt controller
> +- interrupts: touch controller interrupt
> +- wakeup-gpios: the gpio pin to be used for waking up the controller
> +  as well as uased as irq pin
> +
> +Example:
> +
> +	egalax_ts at 04 {
> +		compatible = "eeti,egalax_ts";
> +		reg = <0x04>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <9 2>;
> +		wakeup-gpios = <&gpio1 9 0>;
> +	};
> -- 
> 1.7.6
> 


From arnd at arndb.de  Wed Aug 15 08:57:33 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 12:57:33 +0000
Subject: [PATCH v2 01/31] arm64: Assembly macros and definitions
In-Reply-To: <1344966752-16102-2-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-2-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151257.33405.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> This patch introduces several assembly macros and definitions used in
> the .S files across arch/arm64/ like IRQ disabling/enabling, together
> with asm-offsets.c.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From shawn.guo at linaro.org  Wed Aug 15 09:01:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 21:01:11 +0800
Subject: [PATCH v3 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <1345026708-14139-4-git-send-email-jason77.wang@gmail.com>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <20120815130108.GB2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 06:31:48PM +0800, Hui Wang wrote:
> i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
> touchscreen controller, add it as an i2c slave device in the dts.
> 
> Signed-off-by: Hui Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/boot/dts/imx6q-sabrelite.dts |   16 ++++++++++++++++
>  arch/arm/boot/dts/imx6q.dtsi          |    7 +++++++
>  2 files changed, 23 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index 72f30f3..4a68e1f 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -54,6 +54,7 @@
>  							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
>  							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
>  							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */
> +							   972  0x10		/* MX6Q_PAD_GPIO_9__GPIO_1_9 */
>  							   >;
>  					};
>  				};
> @@ -115,6 +116,21 @@
>  					VDDIO-supply = <&reg_3p3v>;
>  				};
>  			};
> +
> +			i2c at 021a8000 { /* I2C3 */
> +				status = "okay";
> +				clock-frequency = <100000>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_i2c3_1>;
> +
> +				egalax_ts at 04 {
> +					compatible = "eeti,egalax_ts";
> +					reg = <0x04>;
> +					interrupt-parent = <&gpio1>;
> +					interrupts = <9 2>;

So you take this interrupt as falling-edge, while I see IRQF_TRIGGER_LOW
is used in driver with request_threaded_irq call.

Regards,
Shawn

> +					wakeup-gpios = <&gpio1 9 0>;
> +				};
> +			};
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index fd57079..6f833b3 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -552,6 +552,13 @@
>  					};
>  				};
>  
> +				i2c3 {
> +					pinctrl_i2c3_1: i2c3grp-1 {
> +						fsl,pins = <1013 0x4001b8b1	/* MX6Q_PAD_GPIO_5__I2C3_SCL */
> +							    1037 0x4001b8b1>;	/* MX6Q_PAD_GPIO_16__I2C3_SDA */
> +					};
> +				};
> +
>  				serial2 {
>  					pinctrl_serial2_1: serial2grp-1 {
>  						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
> -- 
> 1.7.6
> 


From arnd at arndb.de  Wed Aug 15 09:03:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:03:47 +0000
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151303.47743.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +#ifdef CONFIG_AARCH32_EMULATION
> +#define compat_thumb_mode(regs) \
> +	(((regs)->pstate & COMPAT_PSR_T_BIT))
> +#else
> +#define compat_thumb_mode(regs) (0)
> +#endif

The symbol we use on other platforms is CONFIG_COMPAT. I don't think you
need to have a separate CONFIG_AARCH32_EMULATION

> +void __bad_xchg(volatile void *ptr, int size)
> +{
> +	printk("xchg: bad data size: pc 0x%p, ptr 0x%p, size %d\n",
> +		__builtin_return_address(0), ptr, size);
> +	BUG();
> +}
> +EXPORT_SYMBOL(__bad_xchg);
> +

I think we're better off not defining this function. My guess is that
initially the idea on ARM was that it was meant as a BUILD_BUG_ON
replacement, but the someone added this function. And you copied it.

Microblaze has the same declaration, but (correctly) misses the
definition, which produces a much more helpful link failure than
a run-time BUG(). Using BUILD_BUG_ON would be even better.

	Arnd


From arnd at arndb.de  Wed Aug 15 09:04:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:04:14 +0000
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151304.14585.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> This patch adds SMP initialisation and spinlocks implementation for
> AArch64. The spinlock support uses the new load-acquire/store-release
> instructions to avoid explicit barriers. The architecture also specifies
> that an event is automatically generated when clearing the exclusive
> monitor state to wake up processors in WFE, so there is no need for an
> explicit DSB/SEV instruction sequence. The SEVL instruction is used to
> set the exclusive monitor locally as there is no conditional WFE and a
> branch is more expensive.
> 
> For the SMP booting protocol, see Documentation/arm64/booting.txt.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From gcembed at gmail.com  Wed Aug 15 09:04:32 2012
From: gcembed at gmail.com (=?UTF-8?q?Ga=C3=ABtan=20Carlier?=)
Date: Wed, 15 Aug 2012 15:04:32 +0200
Subject: [PATCH v2] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
Message-ID: <1345035872-11314-1-git-send-email-gcembed@gmail.com>

Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
Warning: The same solution needs to be applied to the boot loader and the
flash programmer.

This is a modified version of patch sent by J?rgen Lambrecht :
[PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block Indicator,
and use for imx27pdk nand support.

Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
---
 arch/arm/plat-mxc/include/mach/mxc_nand.h |    2 ++
 drivers/mtd/nand/mxc_nand.c               |   26 ++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 6bb96ef..7c04437 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -26,6 +26,8 @@ struct mxc_nand_platform_data {
 	unsigned int width;	/* data bus width in bytes */
 	unsigned int hw_ecc:1;	/* 0 if suppress hardware ECC */
 	unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+	unsigned int biswap:1;	/* set to 1 to swap the Bad Block Indicator
+				   NFC v1 workaround */
 	struct mtd_partition *parts;	/* partition table */
 	int nr_parts;			/* size of parts */
 };
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 3f94e1f..7f5847a 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -682,6 +682,26 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 	return 0;
 }
 
+/*
+ * Swap the BI-byte on position 0x7D0 with a data byte at 0x835.
+ * To fix a bug in NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
+ * Warning: The same solution needs to be applied to the boot loader and the
+ * flash programmer.
+ */
+static void imx_bi_swap(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	unsigned short temp1, temp2, new_temp1;
+
+	temp1 = *((volatile unsigned short*)(host->main_area0 + 0x7D0));
+	temp2 = *((volatile unsigned short*)(host->main_area0 + 0x834));
+	new_temp1 = (temp1 & 0xFF00) | (temp2 >> 8);
+	temp2 = (temp2 & 0x00FF) | (temp1 << 8);
+	*((volatile unsigned short*)(host->main_area0 + 0x7D0)) = new_temp1;
+	*((volatile unsigned short*)(host->main_area0 + 0x834)) = temp2;
+}
+
 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = mtd->priv;
@@ -1093,6 +1113,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 
 		host->devtype_data->send_page(mtd, NFC_OUTPUT);
 
+		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
+			imx_bi_swap(mtd);
+
 		memcpy32_fromio(host->data_buf, host->main_area0,
 				mtd->writesize);
 		copy_spare(mtd, true);
@@ -1112,6 +1135,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 	case NAND_CMD_PAGEPROG:
 		memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
 		copy_spare(mtd, false);
+		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
+			imx_bi_swap(mtd);
+
 		host->devtype_data->send_page(mtd, NFC_INPUT);
 		host->devtype_data->send_cmd(host, command, true);
 		mxc_do_addr_cycle(mtd, column, page_addr);
-- 
1.7.7.4



From arnaud.patard at rtp-net.org  Wed Aug 15 09:10:51 2012
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Wed, 15 Aug 2012 15:10:51 +0200
Subject: [GIT PULL] orion/kirkwood fixes for v3.6
In-Reply-To: <201208151237.56639.arnd@arndb.de> (Arnd Bergmann's message of
 "Wed, 15 Aug 2012 12:37:56 +0000")
References: <20120814234442.GZ22226@titan.lakedaemon.net>
 <201208151237.56639.arnd@arndb.de>
Message-ID: <87boicwbac.fsf@lebrac.rtp-net.org>

Arnd Bergmann <arnd at arndb.de> writes:
Hi,

> On Tuesday 14 August 2012, Jason Cooper wrote:
>> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
>> 
>>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
>> 
>> are available in the git repository at:
>>   git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
>> 
>
> Pulled, thanks!
>
> As soon as you have a pgp key that is signed by other maintainers,
> I think you should start sending signed tags instead of branches,
> and include a short description for what is in the branch you are
> sending. I've started adding descriptions for every merge I do
> and it's easier for me if I don't have to write it myself.
>
> The first patch in your series (ARM: Orion: Set eth packet size
> csum offload limit) looks like it should apply to older kernels
> as well. In those cases, please add "Cc: stable at vger.kernel.org"
> below the Signed-off-by lines (but not in the email submission)
> so it can get picked up by Greg for the longterm and stable
> releases.

I've not added stable@ in Cc: because it won't apply on most other
kernels. fwiw, I plan to send a backport for 3.2.

Arnaud


From jason at lakedaemon.net  Wed Aug 15 09:13:17 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 09:13:17 -0400
Subject: [GIT PULL] orion/kirkwood fixes for v3.6
In-Reply-To: <201208151237.56639.arnd@arndb.de>
References: <20120814234442.GZ22226@titan.lakedaemon.net>
 <201208151237.56639.arnd@arndb.de>
Message-ID: <20120815131317.GE22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 12:37:56PM +0000, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Jason Cooper wrote:
> > The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> > 
> >   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> > 
> > are available in the git repository at:
> >   git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
> > 
> 
> Pulled, thanks!
> 
> As soon as you have a pgp key that is signed by other maintainers,
> I think you should start sending signed tags instead of branches,
> and include a short description for what is in the branch you are
> sending. I've started adding descriptions for every merge I do
> and it's easier for me if I don't have to write it myself.

No problem. I have one and we can do the key signing at the mini-summit.

> The first patch in your series (ARM: Orion: Set eth packet size
> csum offload limit) looks like it should apply to older kernels
> as well. In those cases, please add "Cc: stable at vger.kernel.org"
> below the Signed-off-by lines (but not in the email submission)
> so it can get picked up by Greg for the longterm and stable
> releases.

Gah!  I missed that, sorry.  Did you forward it already or would you
like me to handle it?

thx,

Jason.


From arnd at arndb.de  Wed Aug 15 09:20:02 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:20:02 +0000
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151320.02313.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +The AArch64 exception model is made up of a number of exception levels
> +(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
> +counterpart.  EL2 is the hypervisor level and exists only in non-secure
> +mode. EL3 is the highest priority level and exists only in secure mode.

I'm always confused by a description like this. It sounds like you cannot
have a hypervisor if you have code running in secure mode in EL3. What
I instead understand is that you enter non-secure mode by going from
EL3 into EL2.

> +2. Setup the device tree
> +-------------------------
> +
> +Requirement: MANDATORY
> +
> +The device tree blob (dtb) must be no bigger than 2 megabytes in size
> +and placed at a 2-megabyte boundary within the first 512 megabytes from
> +the start of the kernel image. This is to allow the kernel to map the
> +blob using a single section mapping in the initial page tables.

I've seen people put firmware for some peripherals into the device tree,
so that a device driver can grab a blob from there and load it into the
device, rather than calling request_firmware() which would fail if the
OS running on the system does not contain the blob. If such firmware is
too large, you end up violating the 2 MB limit you impose here.

Should we keep that limit and declare those use cases as invalid, or
should we try to make the boot protocol more flexible?

> diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h
> new file mode 100644
> index 0000000..d766493
> --- /dev/null
> +++ b/arch/arm64/include/asm/setup.h
> @@ -0,0 +1,26 @@
> +#ifndef __ASM_SETUP_H
> +#define __ASM_SETUP_H
> +
> +#include <linux/types.h>
> +
> +#define COMMAND_LINE_SIZE 1024
> +
> +#endif

Is this necessary? The asm-generic version of this file allows 512 bytes,
which seems plenty.

> +unsigned int processor_id;
> +EXPORT_SYMBOL(processor_id);
> +
> +unsigned int elf_hwcap __read_mostly;
> +EXPORT_SYMBOL(elf_hwcap);

EXPORT_SYMBOL_GPL?

Neither of these looks like they should be used in drivers.

	Arnd


From arnd at arndb.de  Wed Aug 15 09:30:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:30:01 +0000
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151330.02112.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
>
> +/*
> + * TCR flags.
> + */
> +#define TCR_TxSZ(x)		(((64 - (x)) << 16) | ((64 - (x)) << 0))
> +#define TCR_IRGN_NC		((0 << 8) | (0 << 24))
> +#define TCR_IRGN_WBWA		((1 << 8) | (1 << 24))
> +#define TCR_IRGN_WT		((2 << 8) | (2 << 24))
> +#define TCR_IRGN_WBnWA		((3 << 8) | (3 << 24))
> +#define TCR_IRGN_MASK		((3 << 8) | (3 << 24))
> +#define TCR_ORGN_NC		((0 << 10) | (0 << 26))
> +#define TCR_ORGN_WBWA		((1 << 10) | (1 << 26))
> +#define TCR_ORGN_WT		((2 << 10) | (2 << 26))
> +#define TCR_ORGN_WBnWA		((3 << 10) | (3 << 26))
> +#define TCR_ORGN_MASK		((3 << 10) | (3 << 26))
> +#define TCR_SHARED		((3 << 12) | (3 << 28))
> +#define TCR_TG0_64K		(1 << 14)
> +#define TCR_TG1_64K		(1 << 30)
> +#define TCR_IPS_40BIT		(2 << 32)
> +#define TCR_ASID16		(1 << 36)
> +

As a matter of coding style, I would much prefer tables like this to be
written as

#define TCR_IRGN_MASK		0x0000000003000300
#define TCR_IRGN_WBnWA		0x0000000003000300
#define TCR_IRGN_WT		0x0000000002000200
#define TCR_IRGN_WBWA		0x0000000001000100
#define TCR_IRGN_NC		0x0000000000000000

#define TCR_ORGN_MASK		0x000000000c000c00
#define TCR_ORGN_WBnWA		0x000000000c000c00
#define TCR_ORGN_WT		0x0000000008000800
#define TCR_ORGN_WBWA		0x0000000004000400
#define TCR_ORGN_NC		0x0000000000000000

The advantage of this is that you can visually compare the bitmasks
to a hex dump, and if you are suffering from endian-confused documentation
authors, there is no ambiguity about which end of the word is bit zero.

	Arnd


From arnd at arndb.de  Wed Aug 15 09:35:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:35:47 +0000
Subject: [GIT PULL] orion/kirkwood fixes for v3.6
In-Reply-To: <20120815131317.GE22226@titan.lakedaemon.net>
References: <20120814234442.GZ22226@titan.lakedaemon.net>
 <201208151237.56639.arnd@arndb.de>
 <20120815131317.GE22226@titan.lakedaemon.net>
Message-ID: <201208151335.47964.arnd@arndb.de>

On Wednesday 15 August 2012, Jason Cooper wrote:
> > The first patch in your series (ARM: Orion: Set eth packet size
> > csum offload limit) looks like it should apply to older kernels
> > as well. In those cases, please add "Cc: stable at vger.kernel.org"
> > below the Signed-off-by lines (but not in the email submission)
> > so it can get picked up by Greg for the longterm and stable
> > releases.
> 
> Gah!  I missed that, sorry.  Did you forward it already or would you
> like me to handle it?

I haven't forwarded it yet. I'll just add the tag myself if you
don't mind your patches getting rebased.

	Arnd


From catalin.marinas at arm.com  Wed Aug 15 09:39:23 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 15 Aug 2012 14:39:23 +0100
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <201208151330.02112.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
 <201208151330.02112.arnd@arndb.de>
Message-ID: <20120815133923.GA12596@arm.com>

Hi Arnd,

On Wed, Aug 15, 2012 at 02:30:01PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +/*
> > + * TCR flags.
> > + */
> > +#define TCR_TxSZ(x)		(((64 - (x)) << 16) | ((64 - (x)) << 0))
> > +#define TCR_IRGN_NC		((0 << 8) | (0 << 24))
> > +#define TCR_IRGN_WBWA		((1 << 8) | (1 << 24))
> > +#define TCR_IRGN_WT		((2 << 8) | (2 << 24))
> > +#define TCR_IRGN_WBnWA		((3 << 8) | (3 << 24))
> > +#define TCR_IRGN_MASK		((3 << 8) | (3 << 24))
> > +#define TCR_ORGN_NC		((0 << 10) | (0 << 26))
> > +#define TCR_ORGN_WBWA		((1 << 10) | (1 << 26))
> > +#define TCR_ORGN_WT		((2 << 10) | (2 << 26))
> > +#define TCR_ORGN_WBnWA		((3 << 10) | (3 << 26))
> > +#define TCR_ORGN_MASK		((3 << 10) | (3 << 26))
> > +#define TCR_SHARED		((3 << 12) | (3 << 28))
> > +#define TCR_TG0_64K		(1 << 14)
> > +#define TCR_TG1_64K		(1 << 30)
> > +#define TCR_IPS_40BIT		(2 << 32)
> > +#define TCR_ASID16		(1 << 36)
> > +
> 
> As a matter of coding style, I would much prefer tables like this to be
> written as
> 
> #define TCR_IRGN_MASK		0x0000000003000300
> #define TCR_IRGN_WBnWA		0x0000000003000300
> #define TCR_IRGN_WT		0x0000000002000200
> #define TCR_IRGN_WBWA		0x0000000001000100
> #define TCR_IRGN_NC		0x0000000000000000
> 
> #define TCR_ORGN_MASK		0x000000000c000c00
> #define TCR_ORGN_WBnWA		0x000000000c000c00
> #define TCR_ORGN_WT		0x0000000008000800
> #define TCR_ORGN_WBWA		0x0000000004000400
> #define TCR_ORGN_NC		0x0000000000000000
> 
> The advantage of this is that you can visually compare the bitmasks
> to a hex dump, and if you are suffering from endian-confused documentation
> authors, there is no ambiguity about which end of the word is bit zero.

That depends on the case, in some places it's more readable like this.
In the above case, I find it easier to compare against the documentation
which, for example, has groups of 2 bits at position 8 and 24 or 10 and
26 (for TTBR0 and TTBR1). The meaning of a group of 2 bits is described
separately as 0b00 (NC), 0b01(WBWA) etc. Same goes for the shareability
bits (12 and 28).

So I think at least for code writing it's less error-prone to write the
explicit bit position than a magic long hex.

-- 
Catalin


From arnd at arndb.de  Wed Aug 15 09:45:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:45:08 +0000
Subject: [PATCH v2 05/31] arm64: MMU initialisation
In-Reply-To: <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151345.08961.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> This patch contains the initialisation of the memory blocks, MMU
> attributes and the memory map. Only five memory types are defined:
> Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
> Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
> Cache policies are supported via the memory attributes register
> (MAIR_EL1) and only affect the Normal Cacheable mappings.

It looks like you've managed to eliminate bootmem as I suggested earlier,
very nice!

Acked-by: Arnd Bergmann <arnd at arndb.de>

	Arnd


From arnd at arndb.de  Wed Aug 15 09:47:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:47:00 +0000
Subject: [PATCH v2 06/31] arm64: MMU fault handling and page table
 management
In-Reply-To: <1344966752-16102-7-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-7-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151347.01169.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> +
> +pgd_t *pgd_alloc(struct mm_struct *mm)
> +{
> +	pgd_t *new_pgd;
> +
> +	new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, PGD_ORDER);
> +	if (!new_pgd)
> +		return NULL;
> +
> +	memset(new_pgd, 0, PAGE_SIZE << PGD_ORDER);
> +
> +	return new_pgd;
> +}
> +
> +void pgd_free(struct mm_struct *mm, pgd_t *pgd)
> +{
> +	free_pages((unsigned long)pgd, PGD_ORDER);
> +}
 
According to the documentation, you should only need 8kb for the pgd on
a 64kb page system. Is it required that you use up a full page here?

	Arnd


From arnd at arndb.de  Wed Aug 15 09:53:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:53:01 +0000
Subject: [PATCH v2 07/31] arm64: Process management
In-Reply-To: <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151353.01367.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +#define THREAD_SIZE_ORDER	1
> +#define THREAD_SIZE		8192
> +#define THREAD_START_SP		(THREAD_SIZE - 16)

THREAD_SIZE_ORDER looks wrong for 64kb-page kernels. It also doesn't seem to
be used, so better remove it.

	Arnd



From jason at lakedaemon.net  Wed Aug 15 09:54:27 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 09:54:27 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
Message-ID: <20120815135427.GF22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 01:43:24PM +0100, alan butler wrote:
> On 15 August 2012 13:11, Jason Cooper <jason at lakedaemon.net> wrote:
> > On Wed, Aug 15, 2012 at 07:55:42AM -0400, Josh Coombs wrote:
> > > >> Sorry i meant board-dt in the previous message and the name just
> > > >> getting used to the mail program on os x aswel. I have run through the
> > > >> checkpatch.pl script and it tells me there are no errors but i just
> > > >> found out a few minutes ago theres a fix for the 2 sata ports not
> > > >> working (on all kirkwood devices as far as i know) so i am going to
> > > >> test that now as it envolves modifying a line in the dts file.
> > > >
> > > > Ok.  Please let everyone know in the comment portion of the patch (after
> > > > the --- line) that your patch depends on this fix.  I haven't seen the
> > > > patch you're referring to yet.  I'll keep my eye out for it.
> > >
> > > What he's referring to is needing to up the coherent_pool size to get
> > > a Kirkwood device with two SATA ports to init completely.  I brought
> > > the topic up on arm-kernel under the subject 'Potential Regression in
> > > 3.6-rc1 - Kirkwood SATA' and Aaro Koskinen suggested the root cause
> > > and potential fix of adding coherent_pool=1M to the bootargs.  I
> > > didn't think to cc you in the discussion, sorry about that.  So there
> > > isn't a pending patch yet, just a suggestion of altered bootargs.
> >
> > Yes, I saw that discussion.  Setting coherent_pool=1M was a way of
> > diagnosing the problem.  It allowed the system to boot, which tells us
> > where the problem lies.  But it did not fix the problem in the code.
> > *That's* the patch I was referring to.  Which I haven't seen, yet. ;-)
> 
> I could not get the way to use git figured out so i will send the
> patch here though the browser based gmail interface and hope i do not
> cause or get in too much trouble.

It's doing some linewrapping, but it's fine for review.  When you
resubmit for inclusion, you'll need to get that fixed up.

> And my patch contains that part of
> the altered bootargs so i hope that wont cause a problem either.

Not a problem for review and testing, but I'm going to hold off on
pulling it until we have the core problem fixed.

> diff -urN linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> --- linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> 1970-01-01 01:00:00.000000000 +0100
> +++ linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts    2012-08-15
> 10:17:35.000000000 +0100
> @@ -0,0 +1,77 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +    model = "Iomega StorCenter ix2-200";
> +    compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +    memory {
> +        device_type = "memory";
> +        reg = <0x00000000 0x10000000>;
> +    };
> +
> +    chosen {
> +        bootargs = "console=ttyS0,115200n8 earlyprintk
> root=LABEL=ROOTFS coherent_pool=1M";

watch the linewrap.  Also, please remove the root= declaration and the
coherent_pool=.  Once we get that fixed, your patch won't need it.

> +    };
> +
> +    ocp at f1000000 {
> +        i2c at 11000 {
> +            status = "okay";
> +
> +            lm63: lm63 at 4c {
> +                compatible = "national,lm63";
> +                reg = <0x4c>;
> +            };
> +        };
> +
> +        serial at 12000 {
> +            clock-frequency = <200000000>;
> +            status = "ok";
> +        };
> +
> +        nand at 3000000 {
> +            status = "okay";
> +
> +            partition at 100000 {
> +                label = "uImage";
> +                reg = <0x100000 0x300000>;
> +                read-only;
> +            };
> +
> +            partition at 400000 {
> +                label = "uInitrd";
> +                reg = <0x540000 0x1000000>;
> +            };

is there a partition for u-boot and the u-boot environment?

> +        };
> +        sata at 80000 {
> +            compatible = "marvell,orion-sata";
> +            reg = <0x80000 0x5000>;
> +            interrupts = <21>;
> +            status = "okay";
> +            nr-ports = <2>;
> +        };
> +
> +    };
> +    gpio-leds {
> +        compatible = "gpio-leds";
> +
> +        power_led {
> +            label = "status:white:power_led";
> +            gpios = <&gpio0 16 0>;
> +            linux,default-trigger = "default-on";
> +        };
> +        rebuild_led {
> +            label = "status:white:rebuild_led";
> +            gpios = <&gpio1 5 0>;
> +        };
> +        health_led {
> +            label = "status:red:health_led";
> +            gpios = <&gpio1 6 0>;
> +        };
> +        backup_led {
> +            label = "status:blue:backup_led";
> +            gpios = <&gpio0 15 0>;
> +        };
> +    };
> +};
> diff -urN linuxorig//arch/arm/mach-kirkwood/board-dt.c
> linux//arch/arm/mach-kirkwood/board-dt.c
> --- linuxorig//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
> 12:48:11.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
> 13:17:47.000000000 +0100
> @@ -87,6 +87,9 @@
>     if (of_machine_is_compatible("buffalo,lsxl"))
>         lsxl_init();
> 
> +    if (of_machine_is_compatible("iom,ix2-200"))
> +        iomega_ix2_200_init();
> +
>     of_platform_populate(NULL, kirkwood_dt_match_table,
>                  kirkwood_auxdata_lookup, NULL);
>  }
> @@ -100,6 +103,7 @@
>     "qnap,ts219",
>     "seagate,goflexnet",
>     "buffalo,lsxl",
> +    "iom,ix2-200",

Please double check that this is a leading tab, and not a collection of
spaces.  checkpatch.pl should have coughed on this if it was wrong.
Could also be mail client mangling.

>     NULL
>  };
> 
> diff -urN linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> --- linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> 1970-01-01 01:00:00.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c    2012-08-15
> 10:16:55.000000000 +0100
> @@ -0,0 +1,138 @@
> +/*
> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> + *
> + * Iomega StorCenter ix2-200
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/irq.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/ata_platform.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/ethtool.h>
> +#include <net/dsa.h>
> +#include <linux/gpio.h>
> +#include <linux/leds.h>
> +#include <linux/gpio_keys.h>
> +#include <linux/i2c.h>
> +#include <linux/input.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <mach/kirkwood.h>
> +#include "common.h"
> +#include "mpp.h"
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> +    .phy_addr       = MV643XX_ETH_PHY_NONE,
> +    .speed          = SPEED_1000,
> +    .duplex         = DUPLEX_FULL,
> +};
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
> +    .phy_addr    = MV643XX_ETH_PHY_ADDR(11),
> +};
> +
> +/****************************************************************************
> + * GPIO Attached Keys
> + ****************************************************************************/
> +
> +#define iomega_ix2_200_GPIO_KEY_RESET    12
> +#define iomega_ix2_200_GPIO_KEY_POWER    14
> +#define iomega_ix2_200_GPIO_KEY_OTB        35
> +
> +#define iomega_ix2_200_SW_RESET    0x00
> +#define iomega_ix2_200_SW_POWER    0x01
> +#define iomega_ix2_200_SW_OTB    0x02
> +
> +static struct gpio_keys_button iomega_ix2_200_buttons[] = {
> +    {
> +        .type        = EV_SW,
> +        .code       = iomega_ix2_200_SW_RESET,
> +        .gpio       = iomega_ix2_200_GPIO_KEY_RESET,
> +        .desc       = "Reset Button",
> +        .active_low     = 1,
> +        .debounce_interval = 100,
> +    },
> +    {
> +        .type        = EV_SW,
> +        .code       = iomega_ix2_200_SW_POWER,
> +        .gpio       = iomega_ix2_200_GPIO_KEY_POWER,
> +        .desc       = "Power Button",
> +        .active_low     = 1,
> +        .debounce_interval = 100,
> +    },
> +    {
> +        .type        = EV_SW,
> +        .code       = iomega_ix2_200_SW_OTB,
> +        .gpio       = iomega_ix2_200_GPIO_KEY_OTB,
> +        .desc       = "OTB Button",
> +        .active_low     = 1,
> +        .debounce_interval = 100,
> +    },
> +
> +};
> +
> +static struct gpio_keys_platform_data iomega_ix2_200_button_data = {
> +    .buttons    = iomega_ix2_200_buttons,
> +    .nbuttons       = ARRAY_SIZE(iomega_ix2_200_buttons),
> +};
> +
> +static struct platform_device iomega_ix2_200_button_device = {
> +    .name       = "gpio-keys",
> +    .id         = -1,
> +    .num_resources  = 0,
> +    .dev        = {
> +        .platform_data  = &iomega_ix2_200_button_data,
> +    },
> +};
> +

All of the above (gpio keys) can be removed and described in the DT.
Please look at:

da3fd4c ARM: Kirkwood: Describe iconnect keys in DT.

which is currently at:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
> +    MPP12_GPIO,                             /* Reset Button */
> +    MPP14_GPIO,                             /* Power Button */
> +    MPP15_GPIO,                             /* Backup LED (blue) */
> +    MPP16_GPIO,                             /* Power LED (white) */
> +    MPP35_GPIO,                             /* OTB Button */
> +    MPP36_GPIO,                             /* Rebuild LED (white) */
> +    MPP37_GPIO,                             /* Health LED (red) */
> +    MPP38_GPIO,                             /* SATA LED brightness control 1 */
> +    MPP39_GPIO,                             /* SATA LED brightness control 2 */
> +    MPP40_GPIO,                             /* Backup LED brightness
> control 1 */
> +    MPP41_GPIO,                             /* Backup LED brightness
> control 2 */
> +    MPP42_GPIO,                             /* Power LED brightness
> control 1 */
> +    MPP43_GPIO,                             /* Power LED brightness
> control 2 */
> +    MPP44_GPIO,                             /* Health LED brightness
> control 1 */
> +    MPP45_GPIO,                             /* Health LED brightness
> control 2 */
> +    MPP46_GPIO,                             /* Rebuild LED brightness
> control 1 */
> +    MPP47_GPIO,                             /* Rebuild LED brightness
> control 2 */
> +    0
> +};
> +
> +void __init iomega_ix2_200_init(void)
> +{
> +    /*
> +     * Basic setup. Needs to be called early.
> +     */
> +    kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
> +
> +    kirkwood_ehci_init();
> +
> +    kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
> +    kirkwood_ge01_init(&iomega_ix2_200_ge01_data);


> +    kirkwood_uart0_init();
> +    platform_device_register(&iomega_ix2_200_button_device);

These two lines can be removed, the second after describing the gpio
keys in the DT.  Make sure you have CONFIG_SERIAL_OF_PLATFORM=y in your
config.

> +}
> +
> +static int __init iomega_ix2_200_pci_init(void)
> +{
> +    if (of_machine_is_compatible("iom,ix2-200"))
> +        kirkwood_pcie_init(KW_PCIE0);
> +    return 0;
> +}
> +subsys_initcall(iomega_ix2_200_pci_init);
> +
> diff -urN linuxorig//arch/arm/mach-kirkwood/common.h
> linux//arch/arm/mach-kirkwood/common.h
> --- linuxorig//arch/arm/mach-kirkwood/common.h    2012-08-15
> 12:48:11.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/common.h    2012-08-15
> 12:54:07.000000000 +0100
> @@ -94,6 +94,12 @@
>  static inline void lsxl_init(void) {};
>  #endif
> 
> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
> +void iomega_ix2_200_init(void);
> +#else
> +static inline void iomega_ix2_200_init(void) {};
> +#endif
> +
>  /* early init functions not converted to fdt yet */
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> diff -urN linuxorig//arch/arm/mach-kirkwood/Kconfig
> linux//arch/arm/mach-kirkwood/Kconfig
> --- linuxorig//arch/arm/mach-kirkwood/Kconfig    2012-08-15
> 12:48:11.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/Kconfig    2012-08-15 12:54:55.000000000 +0100
> @@ -195,6 +195,13 @@
>       Say 'Y' here if you want your kernel to support the
>       HP t5325 Thin Client.
> 
> +config MACH_IOMEGA_IX2_200_DT
> +    bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
> +    select ARCH_KIRKWOOD_DT
> +    help
> +      Say 'Y' here if you want your kernel to support the
> +      Iomega StorCenter ix2-200 (Flattened Device Tree).
> +
>  endmenu
> 
>  endif
> diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile
> linux//arch/arm/mach-kirkwood/Makefile
> --- linuxorig//arch/arm/mach-kirkwood/Makefile    2012-08-15
> 12:48:11.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/Makefile    2012-08-15
> 12:55:17.000000000 +0100
> @@ -28,3 +28,4 @@
>  obj-$(CONFIG_MACH_TS219_DT)        += board-ts219.o tsx1x-common.o
>  obj-$(CONFIG_MACH_GOFLEXNET_DT)        += board-goflexnet.o
>  obj-$(CONFIG_MACH_LSXL_DT)        += board-lsxl.o
> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
> diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile.boot
> linux//arch/arm/mach-kirkwood/Makefile.boot
> --- linuxorig//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
> 13:07:03.000000000 +0100
> +++ linux//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
> 12:55:43.000000000 +0100
> @@ -11,3 +11,4 @@
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb

...

> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

This will need to go above the --- line, which you don't have in this
email.

Since you have this patch as a file, do the following:

# after the git checkout command in my previous instructions

patch -Np0 <../my_patch_file
	# you may need 1 instead here, depends on the patch.

git diff HEAD
	# review the output, quit out and fix anything that isn't
	# right. review again with the same command.  Once it looks
	# correct, proceed

git add .

# you'll probably need to do these two if this is a new repo:
	git config --add user.name "Alan M Butler"
	git config --add user.email "alanbutty12 at gmail.com"

git commit -s
	# The first line should be "ARM: Kirkwood: ...".  This will
	# become the subject of the email submission

# now, pickup in my original instructions with 'git format-patch'

hth,

Jason.


From arnd at arndb.de  Wed Aug 15 09:56:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 13:56:05 +0000
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151356.05416.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> diff --git a/arch/arm64/include/asm/procinfo.h b/arch/arm64/include/asm/procinfo.h
> new file mode 100644
> index 0000000..81fece9
> --- /dev/null
> +++ b/arch/arm64/include/asm/procinfo.h
> @@ -0,0 +1,44 @@
> +/*
> + * Based on arch/arm/include/asm/procinfo.h
> + *
> + * Copyright (C) 1996-1999 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_PROCINFO_H
> +#define __ASM_PROCINFO_H
> +
> +#ifdef __KERNEL__
> +
> +/*
> + * Note!  struct processor is always defined if we're
> + * using MULTI_CPU, otherwise this entry is unused,
> + * but still exists.
> + *
> + * NOTE! The following structure is defined by assembly
> + * language, NOT C code.  For more information, check:
> + *  arch/arm/mm/proc-*.S and arch/arm/kernel/head.S
> + */
> +struct proc_info_list {
> +	unsigned int		cpu_val;
> +	unsigned int		cpu_mask;
> +	unsigned long		__cpu_flush;		/* used by head.S */
> +	const char		*cpu_name;
> +};
> +
> +#else	/* __KERNEL__ */
> +#include <asm/elf.h>
> +#warning "Please include asm/elf.h instead"
> +#endif	/* __KERNEL__ */
> +#endif

I think you forgot to remove this file when you removed MULTI_CPU.

	Arnd


From shawn.guo at linaro.org  Wed Aug 15 09:59:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 21:59:50 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815092539.GH19681@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
Message-ID: <20120815135947.GC2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 05:25:40PM +0800, Dong Aisheng wrote:
> On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
> > That is just
> > 
> > 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
> > 
> > vs.
> > 
> > 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0
> > 
> > isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
> > different story.)
> > 
> Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
> Grant,
> Do you know if dt macro can support it?
> 
I have the same doubt there.  Copied Stephen who might have a better
insight on this.

> Now I'm a bit intend to admit that we probably could do like that if it supports.
> The benefit i see is that it could save much code lines in driver while having
> no using experience downgrade.
> 
> The left question is that how do we get the pin id from this kind of format data
> (0x32c, 0x008, 7, 0x0, 0), probably one way may be:
> For normal pads and NO_CONFIG pads, we could get it via:
> mux_reg_offset / 4
> for NO_MUX pads but have CONFIG pads, we may get it via:
> mux_reg_offset / 4 + PIN_NO_MUX_ID_BASE + config_reg_offset /4

In case of NO_MUX, mux_reg_offset is 0, so the formula becomes:

	PIN_NO_MUX_ID_BASE + config_reg_offset / 4

The question comes to how PIN_NO_MUX_ID_BASE gets determined?

> That may fix getting pin id issue from dt.
> 
> Another known issue is that via this way, that means the pinctrl subsystem
> can only see the using pads, this is a bit not align with the pinctrl
> subsystem design. No sure if Linus would like to see it.
> 
I do not quite follow on this.  The "enum imx51_pads" will still be
there, so all the pads will still be visible to the pinctrl system.

-- 
Regards,
Shawn


From broonie at opensource.wolfsonmicro.com  Wed Aug 15 10:01:17 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 15 Aug 2012 15:01:17 +0100
Subject: [PATCH 03/22] ASoC: ab8500: Inform SoC Core that we have our own
 I/O arrangements
In-Reply-To: <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-4-git-send-email-lee.jones@linaro.org>
Message-ID: <20120815140117.GC13544@opensource.wolfsonmicro.com>

On Thu, Aug 09, 2012 at 04:47:29PM +0100, Lee Jones wrote:
> If codec->control_data is not populated SoC Core assumes we want to
> use regmap, which fails catastrophically, as we don't have one:

*Always* submit code against the current code for the subsystem.


From jason at lakedaemon.net  Wed Aug 15 10:02:23 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 10:02:23 -0400
Subject: [GIT PULL V2] orion/kirkwood fixes for v3.6
In-Reply-To: <201208151335.47964.arnd@arndb.de>
References: <20120814234442.GZ22226@titan.lakedaemon.net>
 <201208151237.56639.arnd@arndb.de>
 <20120815131317.GE22226@titan.lakedaemon.net>
 <201208151335.47964.arnd@arndb.de>
Message-ID: <20120815140223.GG22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 01:35:47PM +0000, Arnd Bergmann wrote:
> On Wednesday 15 August 2012, Jason Cooper wrote:
> > > The first patch in your series (ARM: Orion: Set eth packet size
> > > csum offload limit) looks like it should apply to older kernels
> > > as well. In those cases, please add "Cc: stable at vger.kernel.org"
> > > below the Signed-off-by lines (but not in the email submission)
> > > so it can get picked up by Greg for the longterm and stable
> > > releases.
> > 
> > Gah!  I missed that, sorry.  Did you forward it already or would you
> > like me to handle it?
> 
> I haven't forwarded it yet. I'll just add the tag myself if you
> don't mind your patches getting rebased.

I fixed it:

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

Arnaud Patard (3):
      ARM: Orion: Set eth packet size csum offload limit
      ARM: Kirkwood: Fix iconnect leds
      ARM: Kirkwood: fix Makefile.boot

 arch/arm/boot/dts/kirkwood-iconnect.dts   |    6 +++++-
 arch/arm/mach-dove/common.c               |    3 ++-
 arch/arm/mach-kirkwood/Makefile.boot      |    3 ++-
 arch/arm/mach-kirkwood/common.c           |    4 ++--
 arch/arm/mach-mv78xx0/common.c            |    6 ++++--
 arch/arm/mach-orion5x/common.c            |    3 ++-
 arch/arm/plat-orion/common.c              |    8 ++++++--
 arch/arm/plat-orion/include/plat/common.h |    6 ++++--
 include/linux/mv643xx_eth.h               |    2 ++
 9 files changed, 29 insertions(+), 12 deletions(-)


From arnd at arndb.de  Wed Aug 15 10:15:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 14:15:39 +0000
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <1344966752-16102-17-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-17-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151415.39570.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> +
> +void elf_set_personality(int personality)
> +{
> +       switch (personality & PER_MASK) {
> +       case PER_LINUX:
> +               clear_thread_flag(TIF_32BIT);
> +               break;
> +       case PER_LINUX32:
> +               set_thread_flag(TIF_32BIT);
> +               break;
> +       default:
> +               pr_warning("Process %s tried to assume unknown personality %d\n",
> +                          current->comm, personality);
> +               return;
> +       }
> +
> +       current->personality = personality;
> +}
> +EXPORT_SYMBOL(elf_set_personality);

This looks wrong: PER_LINUX/PER_LINUX32 decides over the output of the
uname system call, while TIF_32BIT decides over the instruction set
when returning to user space. You definitely should not set the personality
to the value you pass from the elf loader. Instead, just do

#define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
#defined COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);

I also don't see a reason to export this. You'd have trouble loading
the elf interpreter module from user space without the elf interpreter.

	Arnd


From shawn.guo at linaro.org  Wed Aug 15 10:16:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 22:16:10 +0800
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20120814170300.8f97afcf.akpm@linux-foundation.org>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
Message-ID: <20120815141606.GA2457@S2101-09.ap.freescale.net>

Thanks for looking at the patch, Andrew.

On Tue, Aug 14, 2012 at 05:03:00PM -0700, Andrew Morton wrote:
> On Fri, 13 Jul 2012 15:31:03 +0800
> Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > +static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
> > +{
> > +	unsigned long timeout = jiffies + msecs_to_jiffies(1);
> > +	unsigned long flags;
> > +	u32 lpcr;
> > +
> > +	spin_lock_irqsave(&data->lock, flags);
> > +
> > +	lpcr = readl(data->ioaddr + SNVS_LPCR);
> > +	if (enable)
> > +		lpcr |= SNVS_LPCR_SRTC_ENV;
> > +	else
> > +		lpcr &= ~SNVS_LPCR_SRTC_ENV;
> > +	writel(lpcr, data->ioaddr + SNVS_LPCR);
> > +
> > +	spin_unlock_irqrestore(&data->lock, flags);
> > +
> > +	while (1) {
> > +		lpcr = readl(data->ioaddr + SNVS_LPCR);
> > +
> > +		if (enable) {
> > +			if (lpcr & SNVS_LPCR_SRTC_ENV)
> > +				break;
> > +		} else {
> > +			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
> > +				break;
> > +		}
> > +
> > +		if (time_after(jiffies, timeout))
> > +			return -ETIMEDOUT;
> > +	}
> > +
> > +	return 0;
> > +}
> 
> The timeout code here is fragile.  If acquiring the spinlock takes more
> than a millisecond or if this thread gets interrupted or preempted then
> we could easily execute that loop just a single time, and fail.
> 
So what about moving the timeout initialization to right above the
while(1) loop?

> It would be better to retry a fixed number of times, say 1000?  That
> would take around 1 millisecond, but might be overkill.
> 
How long a 1000 times loop takes really depends on the cpu frequency,
right?

BTW, I have received the notification telling that the patch has been
applied on -mm tree.  So should I just send you an incremental patch
to address the comment?

-- 
Regards,
Shawn


From arnd at arndb.de  Wed Aug 15 10:22:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 14:22:16 +0000
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <1344966752-16102-18-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-18-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151422.16335.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +
> +/* This matches struct stat64 in glibc2.1, hence the absolutely
> + * insane amounts of padding around dev_t's.
> + * Note: The kernel zero's the padded region because glibc might read them
> + * in the hope that the kernel has stretched to using larger sizes.
> + */
> +struct stat64 {
> +	compat_u64	st_dev;
> +	unsigned char   __pad0[4];
> +
> +#define STAT64_HAS_BROKEN_ST_INO	1
> +	compat_ulong_t	__st_ino;
> +	compat_uint_t	st_mode;
> +	compat_uint_t	st_nlink;
> +
> +	compat_ulong_t	st_uid;
> +	compat_ulong_t	st_gid;
> +
> +	compat_u64	st_rdev;
> +	unsigned char   __pad3[4];
> +
> +	compat_s64	st_size;
> +	compat_ulong_t	st_blksize;
> +	compat_u64	st_blocks;	/* Number 512-byte blocks allocated. */
> +
> +	compat_ulong_t	st_atime;
> +	compat_ulong_t	st_atime_nsec;
> +
> +	compat_ulong_t	st_mtime;
> +	compat_ulong_t	st_mtime_nsec;
> +
> +	compat_ulong_t	st_ctime;
> +	compat_ulong_t	st_ctime_nsec;
> +
> +	compat_u64	st_ino;
> +};

The comment above struct stat64 is completely irrelevant here. I would instead
explain why you need your own stat64 in the first place.

> +int kernel_execve(const char *filename,
> +		  const char *const argv[],
> +		  const char *const envp[])
> +{
> +	struct pt_regs regs;
> +	int ret;
> +
> +	memset(&regs, 0, sizeof(struct pt_regs));
> +	ret = do_execve(filename,
> +			(const char __user *const __user *)argv,
> +			(const char __user *const __user *)envp, &regs);
> +	if (ret < 0)
> +		goto out;
> +
> +	/*
> +	 * Save argc to the register structure for userspace.
> +	 */
> +	regs.regs[0] = ret;
> +
> +	/*
> +	 * We were successful.  We won't be returning to our caller, but
> +	 * instead to user space by manipulating the kernel stack.
> +	 */
> +	asm(	"add	x0, %0, %1\n\t"
> +		"mov	x1, %2\n\t"
> +		"mov	x2, %3\n\t"
> +		"bl	memmove\n\t"	/* copy regs to top of stack */
> +		"mov	x27, #0\n\t"	/* not a syscall */
> +		"mov	x28, %0\n\t"	/* thread structure */
> +		"mov	sp, x0\n\t"	/* reposition stack pointer */
> +		"b	ret_to_user"
> +		:
> +		: "r" (current_thread_info()),
> +		  "Ir" (THREAD_START_SP - sizeof(regs)),
> +		  "r" (&regs),
> +		  "Ir" (sizeof(regs))
> +		: "x0", "x1", "x2", "x27", "x28", "x30", "memory");
> +
> + out:
> +	return ret;
> +}
> +EXPORT_SYMBOL(kernel_execve);

Al Viro was recently talking about a generic implementation of execve.
I can't find that now, but I think you should use that.

> +
> +asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
> +			 unsigned long prot, unsigned long flags,
> +			 unsigned long fd, off_t off)
> +{
> +	if (offset_in_page(off) != 0)
> +		return -EINVAL;
> +
> +	return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
> +}
> +
> +/*
> + * Wrappers to pass the pt_regs argument.
> + */
> +#define sys_execve		sys_execve_wrapper
> +#define sys_clone		sys_clone_wrapper
> +#define sys_rt_sigreturn	sys_rt_sigreturn_wrapper
> +#define sys_sigaltstack		sys_sigaltstack_wrapper

I think

#define sys_mmap sys_mmap_pgoff 

would be more appropriate than defining your own sys_mmap function here.
We should probably make that the default in asm-generic/unistd.h and
change the architectures that have their own implementation to override
it.

	Arnd



From festevam at gmail.com  Wed Aug 15 10:26:30 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 15 Aug 2012 11:26:30 -0300
Subject: [PATCH v2 1/2] ARM: mach-imx: Remove board entries in dt_board_compat
Message-ID: <1345040791-3000-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

There is no need for adding board related entries into dt_board_compat.

Leave only the SoC entry.

This way we do not need to patch a C file when adding dt support for a new board.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
--
Changes since v1:
- Rebased against 3.6-rc
---
 arch/arm/mach-imx/imx51-dt.c   |    1 -
 arch/arm/mach-imx/imx53-dt.c   |    4 ----
 arch/arm/mach-imx/mach-imx6q.c |    3 ---
 3 files changed, 8 deletions(-)

diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe..8604165 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -79,7 +79,6 @@ static struct sys_timer imx51_timer = {
 };
 
 static const char *imx51_dt_board_compat[] __initdata = {
-	"fsl,imx51-babbage",
 	"fsl,imx51",
 	NULL
 };
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 1b7a2fc..d193d8f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -105,10 +105,6 @@ static struct sys_timer imx53_timer = {
 };
 
 static const char *imx53_dt_board_compat[] __initdata = {
-	"fsl,imx53-ard",
-	"fsl,imx53-evk",
-	"fsl,imx53-qsb",
-	"fsl,imx53-smd",
 	"fsl,imx53",
 	NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..7a9599f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -218,9 +218,6 @@ static struct sys_timer imx6q_timer = {
 };
 
 static const char *imx6q_dt_compat[] __initdata = {
-	"fsl,imx6q-arm2",
-	"fsl,imx6q-sabrelite",
-	"fsl,imx6q-sabresd",
 	"fsl,imx6q",
 	NULL,
 };
-- 
1.7.9.5



From festevam at gmail.com  Wed Aug 15 10:26:31 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 15 Aug 2012 11:26:31 -0300
Subject: [PATCH v2 2/2] ARM: mach-mxs: Remove board entries in dt_board_compat
In-Reply-To: <1345040791-3000-1-git-send-email-festevam@gmail.com>
References: <1345040791-3000-1-git-send-email-festevam@gmail.com>
Message-ID: <1345040791-3000-2-git-send-email-festevam@gmail.com>

From: fabio <fabio at fabio-Latitude-E6410.(none)>

There is no need for adding board related entries into dt_board_compat.

Leave only the SoC entry.

This way we do not need to patch a C file when adding dt support for a new board.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
--
Changes since v1:
- Rebased against 3.6-rc1
 arch/arm/mach-mxs/mach-mxs.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe8..fb453fd 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -286,19 +286,11 @@ static void __init mxs_machine_init(void)
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-	"fsl,imx23-evk",
-	"fsl,stmp378x_devb"
-	"olimex,imx23-olinuxino",
 	"fsl,imx23",
 	NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
-	"bluegiga,apx4devkit",
-	"crystalfontz,cfa10036",
-	"denx,m28evk",
-	"fsl,imx28-evk",
-	"karo,tx28",
 	"fsl,imx28",
 	NULL,
 };
-- 
1.7.9.5



From festevam at gmail.com  Wed Aug 15 10:29:00 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 15 Aug 2012 11:29:00 -0300
Subject: [PATCH v3 2/2] ARM: mach-mxs: Remove board entries in dt_board_compat
Message-ID: <1345040940-3045-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

There is no need for adding board related entries into dt_board_compat.

Leave only the SoC entry.

This way we do not need to patch a C file when adding dt support for a new board.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
--
Changes since v2:
- Fix From field
Changes since v1:
- Rebased against 3.6-rc1
 arch/arm/mach-mxs/mach-mxs.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe8..fb453fd 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -286,19 +286,11 @@ static void __init mxs_machine_init(void)
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-	"fsl,imx23-evk",
-	"fsl,stmp378x_devb"
-	"olimex,imx23-olinuxino",
 	"fsl,imx23",
 	NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
-	"bluegiga,apx4devkit",
-	"crystalfontz,cfa10036",
-	"denx,m28evk",
-	"fsl,imx28-evk",
-	"karo,tx28",
 	"fsl,imx28",
 	NULL,
 };
-- 
1.7.9.5



From arnd at arndb.de  Wed Aug 15 10:34:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 14:34:04 +0000
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151434.05145.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +#ifdef CONFIG_AARCH32_EMULATION
> +#include <linux/compat.h>
> +
> +#define AARCH32_KERN_SIGRET_CODE_OFFSET	0x500
> +
> +extern const compat_ulong_t aarch32_sigret_code[6];
> +
> +int compat_setup_frame(int usig, struct k_sigaction *ka, sigset_t *set,
> +		       struct pt_regs *regs);
> +int compat_setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
> +			  sigset_t *set, struct pt_regs *regs);
> +
> +void compat_setup_restart_syscall(struct pt_regs *regs);
> +#else
> +
> +static inline int compat_setup_frame(int usid, struct k_sigaction *ka,
> +				     sigset_t *set, struct pt_regs *regs)
> +{
> +	BUG();
> +}

What good is the run-time BUG() here? Nothing should be calling these
when CONFIG_COMPAT is disabled, so I think you should just remove
the #ifdef around the declarations, and the entire #else case.


> +asmlinkage int compat_sys_sched_rr_get_interval(compat_pid_t pid,
> +						struct compat_timespec __user *interval)
> +{
> +	struct timespec t;
> +	int ret;
> +	mm_segment_t old_fs = get_fs();
> +
> +	set_fs(KERNEL_DS);
> +	ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
> +	set_fs(old_fs);
> +	if (put_compat_timespec(&t, interval))
> +		return -EFAULT;
> +	return ret;
> +}
> +
> +asmlinkage int compat_sys_sendfile(int out_fd, int in_fd,
> +				   compat_off_t __user *offset, s32 count)
> +{
> +	mm_segment_t old_fs = get_fs();
> +	int ret;
> +	off_t of;
> +
> +	if (offset && get_user(of, offset))
> +		return -EFAULT;
> +
> +	set_fs(KERNEL_DS);
> +	ret = sys_sendfile(out_fd, in_fd, offset ? (off_t __user *)&of : NULL,
> +			   count);
> +	set_fs(old_fs);
> +
> +	if (offset && put_user(of, offset))
> +		return -EFAULT;
> +	return ret;
> +}

I guess it's time to move these two into common code. They look like they should
be shared across most architectures that have compat support.

> +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> +{
> +	int ret;
> +
> +	if (personality(current->personality) == PER_LINUX32 &&
> +		personality == PER_LINUX)
> +		personality = PER_LINUX32;
> +	ret = sys_personality(personality);
> +	if (ret == PER_LINUX32)
> +		ret = PER_LINUX;
> +	return ret;
> +}

Where did you get this from?

You should not need compat_sys_personality, just call the native function.

	Arnd


From arnd at arndb.de  Wed Aug 15 10:35:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 14:35:30 +0000
Subject: [PATCH v2 22/31] arm64: Floating point and SIMD
In-Reply-To: <1344966752-16102-23-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-23-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151435.30646.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> This patch adds support for FP/ASIMD register bank saving and restoring
> during context switch and FP exception handling to generate SIGFPE.
> There are 32 128-bit registers and the context switching is currently
> done non-lazily. Benchmarks on real hardware are required before
> implementing lazy FP state saving/restoring.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From bhelgaas at google.com  Wed Aug 15 10:36:24 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 15 Aug 2012 07:36:24 -0700
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120815123022.GA8678@avionic-0098.adnet.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
 <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
 <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
 <20120815123022.GA8678@avionic-0098.adnet.avionic-design.de>
Message-ID: <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>

On Wed, Aug 15, 2012 at 5:30 AM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Wed, Aug 15, 2012 at 05:18:04AM -0700, Bjorn Helgaas wrote:
>> On Tue, Aug 14, 2012 at 11:37 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>> > On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
>> >> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
>> >> <thierry.reding at avionic-design.de> wrote:
>> >> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
>> >> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
>> >> >> index a094c97..c886dff 100644
>> >> >> --- a/arch/arm/boot/dts/tegra20.dtsi
>> >> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
>> >> >> @@ -199,6 +199,68 @@
>> >> >>               #size-cells = <0>;
>> >> >>       };
>> >> >>
>> >> >> +     pcie-controller {
>> >> >> +             compatible = "nvidia,tegra20-pcie";
>> >> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
>> >> >> +                    0x80003800 0x00000200   /* AFI registers */
>> >> >> +                    0x81000000 0x01000000   /* configuration space */
>> >> >> +                    0x90000000 0x10000000>; /* extended configuration space */
>> >> >> +             interrupts = <0 98 0x04   /* controller interrupt */
>> >> >> +                           0 99 0x04>; /* MSI interrupt */
>> >> >> +             status = "disabled";
>> >> >> +
>> >> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
>> >> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
>> >> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
>> >> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
>> >> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
>> >> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
>> >> >> +
>> >> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
>> >> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
>> >> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
>> >> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
>> >> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
>> >> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
>> >> >
>> >> > I've been thinking about this some more. The translations for both the
>> >> > regular and extended configuration spaces are configured in the top-
>> >> > level PCIe controller. It is therefore wrong how they are passed to the
>> >> > PCI host bridges via the ranges property.
>> >> >
>> >> > I remember Mitch saying that it should be passed down to the children
>> >> > because it is partitioned among them, but since the layout is compatible
>> >> > with ECAM, the partitioning isn't as simple as what's in the tree. In
>> >> > fact the partitions will be dependent on the number of devices attached
>> >> > to the host bridges.
>> >>
>> >> I don't understand this last bit about the number of devices attached
>> >> to the host bridges.  Logically, the host bridge has a bus number
>> >> aperture that you can know up front, even before you know anything
>> >> about what devices are below it.  On x86, for example, the ACPI _CRS
>> >> method has something like "[bus 00-7f]" in it, which means that any
>> >> buses in that range are below this bridge.  That doesn't tell us
>> >> anything about which buses actually have devices on them, of course;
>> >> it's just analogous to the secondary and subordinate bus number
>> >> registers in a P2P bridge.
>> >
>> > That's one of the issues I still need to take care of. Currently no bus
>> > resource is attached to the individual bridges (nor the PCI controller
>> > for that matter), so the PCI core will assign them dynamically.
>>
>> So your PCI controller driver knows how to program the controller bus
>> number aperture?  Sometimes people start by assuming that two host
>> bridges both have [bus 00-ff] apertures, then they enumerate below the
>> first and adjust the bus number apertures based on what they found.
>> For example, if they found buses 00-12 behind the first bridge, they
>> make the apertures [bus 00-12] for the first bridge and [bus 13-ff]
>> for the second.  That might be the case, depending on what firmware
>> set up, but it seems like a dubious way to do it, and of course it
>> precludes a lot of hot-plug scenarios.
>
> No, that's not what I meant. What happens is that no pre-assigned bus
> range is specified for either of the host bridges, so that the range
> 0x00-0xff will be assigned by default in pci_scan_root_bus().

My concern is about making the kernel's idea of the host bridge bus
number aperture match what the hardware is doing.  I'm pretty sure
that the default [bus 00-ff] range assigned by pci_scan_root_bus()
doesn't actually match the hardware in most cases, at least when we
have multiple host bridges in the same PCI domain.

For example, if you don't supply a bus number range,
pci_scan_root_bus() will assume [bus 00-ff] for both host bridges.
But if you could put an analyzer on each of the root buses and then
read bus 0 config space, will you see that config transaction on
*both* buses?  I doubt it.

You have to know at least the bus number of the root bus up front
before you can even start enumerating it.  The only way to learn that
is by reading registers in the host bridge or by some external
mechanism like ACPI or device tree.  That's the beginning of the bus
number aperture.  The end of the aperture is similar: we can't
reliably determine it by enumerating devices below the host bridge, so
we have to know it up front.  You can enumerate starting with the root
bus number and assigning new subordinate bus numbers as necessary, but
unless you know the host bridge aperture to begin with, you could
inadvertently assign a new bus number that actually belongs to a
different host bridge.

Bjorn


From linus.walleij at linaro.org  Wed Aug 15 10:38:40 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 16:38:40 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>

(Hm maybe I should've read this patch first, well whatever.)

On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:

> This is also include the gpio controller as the IP share both.
> Each soc will have to describe the SoC limitation and pin configuration via
> DT.

This is very good.

> This will allow to do not need to touch the C code when adding new SoC if the
> IP version is supported.

Which is what we want -> less churn.

> +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt

This needs to be CC to devicetree-discuss at lists.ozlabs.org where bindings
are discussed, the people there sometimes make a good job to make sure
the bindings are OS-neutral and stuff (doesn't seem like a problem in this
very case, but anyway).

> +Required properties for iomux controller:
> +- compatible: "atmel,at91rm9200-pinctrl"
> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
> +  configured in this periph mode. All the periph and bank need to be describe.

Can you please be more elaborate on this mux-mask, like what each bit
means and why the bits are arranged like that and what it means on the
AT91 platform.... I was first reading the .dts and was like ?woot? so
I go to the bindings doc and I read this and I'm still like ?woot?..

> +Required properties for pin configuration node:
> +- atmel,pins: 4 integers array, represents a group of pins mux and config

This also need to be detailed so you can just read this and then
look at the numbers in the device tree and, "aha I get it!".

> +  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
> +  The PERIPH 0 means gpio.

So please elaborate a bit on the three first members, so it's easy to read
and understand the device tree. I "sort of" understand it but better
be explicit.

(...)
> +Bits used for CONFIG:
> +PULL_UP(1 << 0): indicate this pin need a pull up.
> +MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.

Hm if we just add multidrive to <linux/pinctrl/pinconf-generic.h> we
could probably get this driver (and bindings) to use the generic
pinconf library in drivers/pinctrl/pinonf-generic.c as the coh901
currently does.

Actually multidrive makes me think that this is just shunting in
several MOSFET driver stages, which we *used* to have in
pinconf-generic, just by documenting that the argument passed
with parameter PIN_CONFIG_DRIVE_PUSH_PULL
would indicate the number of drive stages if != 0.

Like this (old doc):

+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ *     low, this is the most typical case and is typically achieved with two
+ *     active transistors on the output. If the pin can support different
+ *     drive strengths for push/pull, the strength is given in the argument
+ *     as the number of driving stages vs nominal load impedance, so say
+ *     quadruple driving stages (usually 8 transistors rather than two) will
+ *     be configured with the 8 passed as argument.

We're not mandate generic pin config because driver authors told me
repeatedly that their chips are very special (like everyone else, hehe)
but please keep it in mind as it could be hard to change this later.
I'd be happy to put back this piece of doc...

> +2. The pin configuration node intends to work on a specific function should
> +   to be defined under that specific function node.
> +   The function node's name should represent well about what function
> +   this group of pins in this pin configuration node are working on.

I cannot parse this, sorry :-) could you detail...

> +3. The driver can use the function node's name and pin configuration node's
> +   name describe the pin function and group hierarchy.
> +   For example, Linux Iat91 pinctrl driver takes the function node's name
> +   as the function name and pin configuration node's name as group name to
> +   create the map table.
> +4. Each pin configuration node should have a phandle, devices can set pins
> +   configurations by referring to the phandle of that pin configuration node.
> +5. The gpio controller must be describe in the pinctrl simple-bus.

I think I understand this part...

> +pinctrl at fffff400 {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       ranges;
> +       compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +       reg = <0xfffff400 0x600>;
> +
> +       atmel,mux-mask = <
> +             /*    A         B     */
> +              0xffffffff 0xffc00c3b  /* pioA */
> +              0xffffffff 0x7fff3ccf  /* pioB */
> +              0xffffffff 0x007fffff  /* pioC */
> +             >;

I still have a real hard time understanding what is happening here,
but maybe I'll understand as I go on reading the driver.

> +       /* shared pinctrl settings */
> +       dbgu {
> +               pinctrl_dbgu: dbgu-0 {
> +                       atmel,pins =
> +                               <1 14 0x1 0x0   /* PB14 periph A */
> +                                1 15 0x1 0x1>; /* PB15 periph with pullup */

I understand that Pin 14 and 15 in pin bank 1 is connected to some
peripheral numbered 1 and pin 15 is pulled up.

I guess perioheral 1 is identical to debugf uart 0 or something
like that, since the node has this name? ut shouldn't this
peripheral number come from the fact that it's dbgu so there
is somewhere a table cross referencing ... or the device itself
has some node which is separate and has some name like
"pinctrl-periphid" or so?

Just trying to decipher this a bit so I see if I could maintain
it...

Would it be possible to have the periphid as a separate node
entry if it is anyway going to be the same value for all
pins, or is this number also unique per bank or something
like that, so debug uart would be say peripheral ID 5 on another
pin bank? (In that case, keep it like this.)

> +dbgu: serial at fffff200 {
> +       compatible = "atmel,at91sam9260-usart";
> +       reg = <0xfffff200 0x200>;
> +       interrupts = <1 4 7>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_dbgu>;
> +       status = "disabled";
> +};

I really like the looks of this.

(...)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..178a619 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -352,6 +352,7 @@ config ARCH_AT91
>         select CLKDEV_LOOKUP
>         select IRQ_DOMAIN
>         select NEED_MACH_IO_H if PCCARD
> +       select PINCTRL

Richard said something about also selectong the AT91 driver which
seemed lika a good idea.

(There follow some changes moving a lot of IRQ domain stuff etc from
the GPIO driver which is hard to understand, but I guess you're doing
the right thing.)

(...)
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -0,0 +1,1448 @@
> +/*
> + * at91 pinctrl driver based on at91 pinmux core
> + *
> + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
> + * <plagnioj at jcrosoft.com>
> + *
> + * Under GPLv2 only
> + */
> +
> +#define DEBUG

As noted rely on switching on DEBUG_PINCTRL where needed.
It tags on -DDEBUG in the Makefile.

> +#include <asm/mach/irq.h>

Hm, it seems this platform is not using SPARSE_IRQ ...

(...)
> +static struct at91_gpio_chip *gpio_chip[MAX_GPIO_BANKS];

Nitpick should it not be named *gpio_chips[] (plural) since
there are several chips in that array?

> +static int gpio_banks;
> +static unsigned long at91_gpio_caps;

I usually protect this kind of variables with a mutex but it
may be over-cautious.

(...)
> +#define PULL_UP                (0 << 1)
> +#define MULTI_DRIVE    (1 << 1)

So this I would have attempted to use pinconf-generic.[c|h] for
and use PIN_CONFIG_BIAS_PULL_UP and
PIN_CONFIG_DRIVER_PUSH_PULL with a specific
argument for the multidrive.

Beware that you may want to patch pinconf-generic.c
to get the debugfs output you want etc.

But as I said this is optional, just a good idea in general.

(...)
> +struct at91_pmx_pin {
> +       uint32_t bank;
> +       uint32_t pin;
> +       uint32_t mux;
> +       uint32_t pullup;
> +       unsigned long conf;
> +};

Are they all u32 really? I understand that they are u32 in the
devicetree but pullup seems like a candidate for a bool.

Reading below it seems the "mux" member should be some
kind of enum. Doing that an enum and documenting it seems
like it would solve other readability issues.

And this could actually use some kerneldoc too, if possible.

> +/**
> + * struct at91_pin_group - describes an At91 pin group
> + * @name: the name of this specific pin group

@pins_conf is not documented.

> + * @pins: an array of discrete physical pins used in this group, taken
> + *     from the driver-local pin enumeration space
> + * @npins: the number of pins in this group array, i.e. the number of
> + *     elements in .pins so we can iterate over that array
> + */
> +struct at91_pin_group {
> +       const char *name;
> +       struct at91_pmx_pin *pins_conf;
> +       unsigned int *pins;
> +       unsigned npins;
> +};


> +struct at91_pinctrl {
> +       struct device *dev;
> +       struct pinctrl_dev *pctl;
> +
> +       int nbanks;
> +
> +       int nmux;
> +       uint32_t *mux_mask;
> +
> +       struct at91_pmx_func *functions;
> +       int nfunctions;
> +
> +       struct at91_pin_group *groups;
> +       int ngroups;
> +
> +       void (*set_A_periph)(void __iomem *pio, unsigned mask);
> +       void (*set_B_periph)(void __iomem *pio, unsigned mask);
> +};

kerneldoc. Especually the two last functions are mysterious when just
looking at the struct.

(Then follows a block of really nice code...)

(...)
> +static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
> +                  unsigned offset)
> +{
> +       seq_printf(s, "%s", dev_name(pctldev->dev));
> +}

This print should actually output something interesting (if it helps)
maybe you could skip it?

> +static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
> +                       struct device_node *np,
> +                       struct pinctrl_map **map, unsigned *num_maps)

DT parse code, looks nice but would request Stephen to have a look
at it.

(...)
> +       new_map = kmalloc(sizeof(*new_map) * map_num, GFP_KERNEL);

Maybe devm_kzalloc()?

Because:

(...)
> +       if (!parent) {
> +               kfree(new_map);
> +               return -EINVAL;

You could just return here. And:

(...)
> +static void at91_dt_free_map(struct pinctrl_dev *pctldev,
> +                               struct pinctrl_map *map, unsigned num_maps)
> +{
> +       kfree(map);
> +}

Then this wouldn't be needed at all.

(...)
> +static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_IDR);
> +}

I think most people use writel_relaxed() for this purpose (non-timeconsuming
register write) these days. So conside replacing all __raw_* with *_relaxed().

(...)
> +static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
> +{
> +
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
> +                                               pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> +                                               pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
> +                                               pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> +                                               pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_ASR);
> +}
> +
> +static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(mask, pio + PIO_BSR);
> +}
> +
> +static void at91_mux_set_C_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> +}
> +
> +static void at91_mux_set_D_periph(void __iomem *pio, unsigned mask)
> +{
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> +}

I have no clue whatsoever what is going on here, A? B? C? D?
Some small comment or something giving a hint about this grouping
system and how it works would be really nice.

> +static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
> +{
> +       if (pin->mux) {
> +               dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
> +                       pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
> +       } else {
> +               dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
> +                       pin->bank + 'A', pin->pin, pin->conf);
> +       }
> +}

This is nice, and one of the things we try to centralize and standardize in
pinconf-generic. However as I said that would be optional.

(...)

> +static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, unsigned input)
> +{
> +       __raw_writel(mask, pio + PIO_PER);
> +       __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
> +}
> +

The last argument, "input" seems to be a bool.

Also not that this should maybe be named at91_mux_gpio_endisable()
since it is called from the disable() function below.

(...)
> +       for (i = 0; i < npins; i++) {
> +               pin = &pins_conf[i];
> +               at91_pin_dbg(info->dev, pin);
> +               pio = pin_to_controller(info, pin->bank);
> +               mask = pin_to_mask(pin->pin);
> +               at91_mux_disable_interrupt(pio, mask);
> +               switch(pin->mux) {
> +               case 0:
> +                       at91_mux_gpio_enable(pio, mask, 1);
> +                       break;
> +               case 1:
> +                       info->set_A_periph(pio, mask);
> +                       break;
> +               case 2:
> +                       info->set_B_periph(pio, mask);
> +                       break;
> +               case 3:
> +                       at91_mux_set_C_periph(pio, mask);
> +                       break;
> +               case 4:
> +                       at91_mux_set_D_periph(pio, mask);
> +                       break;
> +               }
> +               if (pin->mux)
> +                       at91_mux_gpio_disable(pio, mask);

Looking at this it seems that the pin->mux variable should be an
enum so we get rid of these magic values 0,1,2,3,4. Documenting
these enums with kerneldoc would probably solve a lot of
questionmarks.

(Noted in the struct review above as well.)

(...)
> +static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
> +                          unsigned group)
> +{
> +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> +       const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
> +       const struct at91_pmx_pin *pin;
> +       uint32_t npins = info->groups[group].npins;
> +       int i;
> +       unsigned mask;
> +       void __iomem *pio;
> +
> +       for (i = 0; i < npins; i++) {
> +               pin = &pins_conf[i];
> +               at91_pin_dbg(info->dev, pin);
> +               pio = pin_to_controller(info, pin->bank);
> +               mask = pin_to_mask(pin->pin);
> +               at91_mux_gpio_enable(pio, mask, 1);

Actually calling a function named "*enable" to disable something looks
quite unintuitive. Maybe rename that function to
"at91_mux_gpio_endisable()" or something?

(...)
> +static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
> +                                  struct seq_file *s, unsigned pin_id)
> +{
> +
> +}

Don't you want some nice debug output for each pin here?
Like outputting the pull/drive conf...

> +static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
> +                                        struct seq_file *s, unsigned group)
> +{
> +}

I think this function is optional now, or it should be. So you shouldn't
need to define it.

(...)
> +       pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
> +                               GFP_KERNEL);
> +       grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
> +                               GFP_KERNEL);

Oh managed resources here, use them everywhere.

(...)
> +       at91_pinctrl_desc.name = dev_name(&pdev->dev);
> +       at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
> +       at91_pinctrl_desc.pins = pdesc =
> +               devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
> +
> +       if (!at91_pinctrl_desc.pins)
> +               return -ENOMEM;

Nitpick: checking the local variable pdesc for NULL is shorter.

(...)
> +static char peripheral_function(void __iomem *pio, unsigned mask)
> +{
> +       char    ret = 'X';
> +       u8      select;

This looks like a bool.

> +
> +       if (!pio)
> +               return ret;
> +
> +       if (has_pio3()) {
> +               select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
> +               select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);

Especially if you use it like that...

(...)
> +#ifdef CONFIG_PM
> +static u32 wakeups[MAX_GPIO_BANKS];
> +
> +static int gpio_irq_set_wake(struct irq_data *d, unsigned state)

"state" looks like a bool.

> +{
> +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> +       unsigned        mask = 1 << d->hwirq;
> +       unsigned        bank = at91_gpio->pioc_idx;
> +
> +       if (unlikely(bank >= MAX_GPIO_BANKS))
> +               return -EINVAL;
> +
> +       if (state)
> +               wakeups[bank] |= mask;
> +       else
> +               wakeups[bank] &= ~mask;
> +
> +       irq_set_irq_wake(at91_gpio->pioc_virq, state);
> +
> +       return 0;
> +}

So I can see that this sets or clears bits in a 32-bit word per
bank. But I don't see these words being used for anything at all?

So what's the point of all this?

In  ux500 we have a register bit that enables wakeup on a
certain pin, then it makes all kind of sense to have this,
but what is this stuff, really? It seems the function can be
stripped down to two lines just calling irq_set_irq_wake().

(...)
> +       range = &at91_chip->range;
> +       range->name = chip->label;
> +       range->id = alias_idx;
> +       range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
> +
> +       range->npins = chip->ngpio;
> +       range->gc = chip;

This way of handling ranges looks very smooth, great that this works
for you!

The rest looks very good.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 15 10:40:09 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 15 Aug 2012 16:40:09 +0200
Subject: [GIT PULL] Ux500 ASIC ID patches
In-Reply-To: <201208151230.24523.arnd@arndb.de>
References: <CACRpkdZ1+vjrTQC9-M9icO7p9POg-zcR_gUpkyemF4da3jny2w@mail.gmail.com>
 <201208151230.24523.arnd@arndb.de>
Message-ID: <CACRpkdbFC4h_WHgx_KvJOODKbw7Kgm=GsV-Oh72oSwBAqS3dtw@mail.gmail.com>

On Wed, Aug 15, 2012 at 2:30 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> I think it would be nice if you could move to using signed tags in
> the future, and include the text you want to see in the merge
> commit in that tag.

Sure, I was just being lazy...

Yours,
Linus Walleij


From js at sig21.net  Wed Aug 15 10:45:39 2012
From: js at sig21.net (Johannes Stezenbach)
Date: Wed, 15 Aug 2012 16:45:39 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <502B8FE3.7080501@oberhumer.com>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com>
Message-ID: <20120815144539.GA8300@sig21.net>

Hi Marcus,

On Wed, Aug 15, 2012 at 02:02:43PM +0200, Markus F.X.J. Oberhumer wrote:
> On 2012-08-14 14:39, Johannes Stezenbach wrote:
> > On Tue, Aug 14, 2012 at 01:44:02AM +0200, Markus F.X.J. Oberhumer wrote:
> >> On 2012-07-16 20:30, Markus F.X.J. Oberhumer wrote:
> >>>
> >>> As stated in the README this version is significantly faster (typically more
> >>> than 2 times faster!) than the current version, has been thoroughly tested on
> >>> x86_64/i386/powerpc platforms and is intended to get included into the
> >>> official Linux 3.6 or 3.7 release.
> >>>
> >>> I encourage all compression users to test and benchmark this new version,
> >>> and I also would ask some official LZO maintainer to convert the updated
> >>> source files into a GIT commit and possibly push it to Linus or linux-next.
> > 
> > Sorry for not reporting earlier, but I didn't have time to do real
> > benchmarks, just a quick test on ARM926EJ-S using barebox,
> > and found in the new version decompression is slower:
> > http://lists.infradead.org/pipermail/barebox/2012-July/008268.html
> 
> I can only guess, but maybe your ARM cpu does not have an efficient
> implementation of {get,put}_unaligned().

Yes, ARMv5 cannot do unaligned access.  ARMv6+ could, but
I think the Linux kernel normally traps it for debug,
all ARM seem to use generic {get,put}_unaligned() implementation
which use byte access and shift.

> Could you please try the following patch and test if you can see
> any significant speed difference?

It isn't.  I made the attached quick hack userspace code
using ARM kernel headers and barebox unlzop code.
(new == your new code, old == linux-3.5 git, test == new + your suggested change)
(sorry I had no time to clean it up)

I compressed a Linux Image with lzop (lzop <arch/arm/boot/Image >lzoimage)
and timed uncompression:

# time ./unlzopold <lzoimage >/dev/null
real    0m 0.29s
user    0m 0.19s
sys     0m 0.10s
# time ./unlzopold <lzoimage >/dev/null
real    0m 0.29s
user    0m 0.20s
sys     0m 0.09s
# time ./unlzopnew <lzoimage >/dev/null
real    0m 0.41s
user    0m 0.30s
sys     0m 0.10s
# time ./unlzopnew <lzoimage >/dev/null
real    0m 0.40s
user    0m 0.30s
sys     0m 0.10s
# time ./unlzopnew <lzoimage >/dev/null
real    0m 0.40s
user    0m 0.29s
sys     0m 0.11s
# time ./unlzoptest <lzoimage >/dev/null
real    0m 0.39s
user    0m 0.28s
sys     0m 0.11s
# time ./unlzoptest <lzoimage >/dev/null
real    0m 0.39s
user    0m 0.27s
sys     0m 0.11s
# time ./unlzoptest <lzoimage >/dev/null
real    0m 0.39s
user    0m 0.27s
sys     0m 0.11s

FWIW I also checked the sha1sum to confirm the Image uncompressed OK.


Johannes
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From shawn.guo at linaro.org  Wed Aug 15 10:49:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 22:49:25 +0800
Subject: [PATCH v2 1/2] ARM: mach-imx: Remove board entries in
 dt_board_compat
In-Reply-To: <1345040791-3000-1-git-send-email-festevam@gmail.com>
References: <1345040791-3000-1-git-send-email-festevam@gmail.com>
Message-ID: <20120815144922.GD2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 11:26:30AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> There is no need for adding board related entries into dt_board_compat.
> 
> Leave only the SoC entry.
> 
> This way we do not need to patch a C file when adding dt support for a new board.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

Regards,
Shawn


From arnd at arndb.de  Wed Aug 15 10:49:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 14:49:54 +0000
Subject: [PATCH v2 20/31] arm64: User access library function
In-Reply-To: <1344966752-16102-21-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-21-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151449.54834.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +/*
> + * Single-value transfer routines.  They automatically use the right
> + * size if we just have the right pointer type.  Note that the functions
> + * which read from user space (*get_*) need to take care not to leak
> + * kernel data even if the calling code is buggy and fails to check
> + * the return value.  This means zeroing out the destination variable
> + * or buffer on error.  Normally this is done out of line by the
> + * fixup code, but there are a few places where it intrudes on the
> + * main code path.  When we only write to user space, there is no
> + * problem.
> + */
> +extern long __get_user_1(void *);
> +extern long __get_user_2(void *);
> +extern long __get_user_4(void *);
> +extern long __get_user_8(void *);
> +
> +#define __get_user_x(__r2,__p,__e,__s,__i...)				\
> +	   asm volatile(						\
> +		__asmeq("%0", "x0") __asmeq("%1", "x2")			\
> +		"bl	__get_user_" #__s				\
> +		: "=&r" (__e), "=r" (__r2)				\
> +		: "0" (__p)						\
> +		: __i, "cc")
> +
> +#define get_user(x,p)							\
> +	({								\
> +		register const typeof(*(p)) __user *__p asm("x0") = (p);\
> +		register unsigned long __r2 asm("x2");			\
> +		register long __e asm("x0");				\
> +		switch (sizeof(*(__p))) {				\
> +		case 1:							\
> +			__get_user_x(__r2, __p, __e, 1, "x30");		\
> +			break;						\
> +		case 2:							\
> +			__get_user_x(__r2, __p, __e, 2, "x3", "x30");	\
> +			break;						\
> +		case 4:							\
> +			__get_user_x(__r2, __p, __e, 4, "x30");		\
> +			break;						\
> +		case 8:							\
> +			__get_user_x(__r2, __p, __e, 8, "x30");		\
> +			break;						\
> +		default: __e = __get_user_bad(); break;			\
> +		}							\
> +		x = (typeof(*(p))) __r2;				\
> +		__e;							\
> +	})

It's fairly unusual to have out of line get_user/put_user functions.
What is the reason for this, other than copying from ARM?

> +
> +__get_user_bad:
> +	mov	x2, #0
> +	mov	x0, #-EFAULT
> +	ret
> +ENDPROC(__get_user_bad)

> +__put_user_bad:
> +	mov	x0, #-EFAULT
> +	ret
> +ENDPROC(__put_user_bad)
> +

The purpose of these symbols is to provoke a link error when you
pass the wrong data into get_user/put_user. Actually defining them
completely breaks this logic, so you should remove these!

	Arnd


From linux at arm.linux.org.uk  Wed Aug 15 10:52:10 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 Aug 2012 15:52:10 +0100
Subject: [PATCH] ARM: Dove: allow PCI to be disabled
In-Reply-To: <20120815121801.GD22226@titan.lakedaemon.net>
References: <20120815085709.GI18957@n2100.arm.linux.org.uk>
 <20120815121801.GD22226@titan.lakedaemon.net>
Message-ID: <20120815145210.GA32560@n2100.arm.linux.org.uk>

On Wed, Aug 15, 2012 at 08:18:01AM -0400, Jason Cooper wrote:
> On Wed, Aug 15, 2012 at 09:57:09AM +0100, Russell King - ARM Linux wrote:
> > +#ifdef CONfig_PCI
> 
> ummm...   ^^^^^^ is this a typo?  (/me dives into a trench)

No, it's your imagination playing tricks again. :)  I'll get a new patch
out when I'm in a state that I can redo the git commit without destroying
the current state of my development git tree.

(which may be a while as I'm trying to sort out why ubuntu 12.04 userspace
seems to be a total disaster on the cubox.)


From thierry.reding at avionic-design.de  Wed Aug 15 10:57:08 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 16:57:08 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
 <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
 <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
 <20120815123022.GA8678@avionic-0098.adnet.avionic-design.de>
 <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>
Message-ID: <20120815145708.GA11331@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 07:36:24AM -0700, Bjorn Helgaas wrote:
> On Wed, Aug 15, 2012 at 5:30 AM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Wed, Aug 15, 2012 at 05:18:04AM -0700, Bjorn Helgaas wrote:
> >> On Tue, Aug 14, 2012 at 11:37 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
> >> >> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
> >> >> <thierry.reding at avionic-design.de> wrote:
> >> >> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
> >> >> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> >> >> >> index a094c97..c886dff 100644
> >> >> >> --- a/arch/arm/boot/dts/tegra20.dtsi
> >> >> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
> >> >> >> @@ -199,6 +199,68 @@
> >> >> >>               #size-cells = <0>;
> >> >> >>       };
> >> >> >>
> >> >> >> +     pcie-controller {
> >> >> >> +             compatible = "nvidia,tegra20-pcie";
> >> >> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
> >> >> >> +                    0x80003800 0x00000200   /* AFI registers */
> >> >> >> +                    0x81000000 0x01000000   /* configuration space */
> >> >> >> +                    0x90000000 0x10000000>; /* extended configuration space */
> >> >> >> +             interrupts = <0 98 0x04   /* controller interrupt */
> >> >> >> +                           0 99 0x04>; /* MSI interrupt */
> >> >> >> +             status = "disabled";
> >> >> >> +
> >> >> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
> >> >> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
> >> >> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
> >> >> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
> >> >> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
> >> >> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
> >> >> >> +
> >> >> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
> >> >> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
> >> >> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
> >> >> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
> >> >> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
> >> >> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
> >> >> >
> >> >> > I've been thinking about this some more. The translations for both the
> >> >> > regular and extended configuration spaces are configured in the top-
> >> >> > level PCIe controller. It is therefore wrong how they are passed to the
> >> >> > PCI host bridges via the ranges property.
> >> >> >
> >> >> > I remember Mitch saying that it should be passed down to the children
> >> >> > because it is partitioned among them, but since the layout is compatible
> >> >> > with ECAM, the partitioning isn't as simple as what's in the tree. In
> >> >> > fact the partitions will be dependent on the number of devices attached
> >> >> > to the host bridges.
> >> >>
> >> >> I don't understand this last bit about the number of devices attached
> >> >> to the host bridges.  Logically, the host bridge has a bus number
> >> >> aperture that you can know up front, even before you know anything
> >> >> about what devices are below it.  On x86, for example, the ACPI _CRS
> >> >> method has something like "[bus 00-7f]" in it, which means that any
> >> >> buses in that range are below this bridge.  That doesn't tell us
> >> >> anything about which buses actually have devices on them, of course;
> >> >> it's just analogous to the secondary and subordinate bus number
> >> >> registers in a P2P bridge.
> >> >
> >> > That's one of the issues I still need to take care of. Currently no bus
> >> > resource is attached to the individual bridges (nor the PCI controller
> >> > for that matter), so the PCI core will assign them dynamically.
> >>
> >> So your PCI controller driver knows how to program the controller bus
> >> number aperture?  Sometimes people start by assuming that two host
> >> bridges both have [bus 00-ff] apertures, then they enumerate below the
> >> first and adjust the bus number apertures based on what they found.
> >> For example, if they found buses 00-12 behind the first bridge, they
> >> make the apertures [bus 00-12] for the first bridge and [bus 13-ff]
> >> for the second.  That might be the case, depending on what firmware
> >> set up, but it seems like a dubious way to do it, and of course it
> >> precludes a lot of hot-plug scenarios.
> >
> > No, that's not what I meant. What happens is that no pre-assigned bus
> > range is specified for either of the host bridges, so that the range
> > 0x00-0xff will be assigned by default in pci_scan_root_bus().
> 
> My concern is about making the kernel's idea of the host bridge bus
> number aperture match what the hardware is doing.  I'm pretty sure
> that the default [bus 00-ff] range assigned by pci_scan_root_bus()
> doesn't actually match the hardware in most cases, at least when we
> have multiple host bridges in the same PCI domain.
> 
> For example, if you don't supply a bus number range,
> pci_scan_root_bus() will assume [bus 00-ff] for both host bridges.
> But if you could put an analyzer on each of the root buses and then
> read bus 0 config space, will you see that config transaction on
> *both* buses?  I doubt it.
> 
> You have to know at least the bus number of the root bus up front
> before you can even start enumerating it.  The only way to learn that
> is by reading registers in the host bridge or by some external
> mechanism like ACPI or device tree.  That's the beginning of the bus
> number aperture.  The end of the aperture is similar: we can't
> reliably determine it by enumerating devices below the host bridge, so
> we have to know it up front.  You can enumerate starting with the root
> bus number and assigning new subordinate bus numbers as necessary, but
> unless you know the host bridge aperture to begin with, you could
> inadvertently assign a new bus number that actually belongs to a
> different host bridge.

Yes, that was my understanding as well. So currently I haven't seen any
problems with this because I only use one of the two host bridges. But I
suppose I should add code to initialize the bus number aperture properly
either via platform device resources (for the non-DT case) and the
device tree otherwise.

Thierry
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From shawn.guo at linaro.org  Wed Aug 15 11:00:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 23:00:46 +0800
Subject: [PATCH v3 2/2] ARM: mach-mxs: Remove board entries in
 dt_board_compat
In-Reply-To: <1345040940-3045-1-git-send-email-festevam@gmail.com>
References: <1345040940-3045-1-git-send-email-festevam@gmail.com>
Message-ID: <20120815150043.GE2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 11:29:00AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> There is no need for adding board related entries into dt_board_compat.
> 
> Leave only the SoC entry.
> 
> This way we do not need to patch a C file when adding dt support for a new board.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

Regards,
Shawn


From shawn.guo at linaro.org  Wed Aug 15 11:06:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 23:06:21 +0800
Subject: [PATCH] ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock
 path
In-Reply-To: <1345024816-6368-1-git-send-email-s.trumtrar@pengutronix.de>
References: <1345024816-6368-1-git-send-email-s.trumtrar@pengutronix.de>
Message-ID: <20120815150619.GF2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 12:00:16PM +0200, Steffen Trumtrar wrote:
> From: Philipp Zabel <p.zabel at pengutronix.de>
> 
> The ldb_di[01]_podf is implemented as a clk-divider that
> divides by 1 or 2. In reality, the ldb_di[01]_ipu_div
> dividers divide by either 3.5 or 7. Adding a fixed factor
> of 1/3.5 fixes their children's clock rates.
> 
> This should probably be converted to rate table based dividers,
> once available.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>

Applied this as a fix with stable Cc-ed.  Let me know if this is
inappropriate.

-- 
Regards,
Shawn


From arnd at arndb.de  Wed Aug 15 11:07:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:07:36 +0000
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <1344966752-16102-24-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-24-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151507.36174.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +const struct user_regset_view *task_user_regset_view(struct task_struct *task)
> +{
> +#ifdef CONFIG_AARCH32_EMULATION
> +	if (test_tsk_thread_flag(task, TIF_32BIT))
> +		return &user_aarch32_view;
> +#endif
> +	return &user_aarch64_view;
> +}

Ah, nice. So you support 64 bit debuggers debugging 32 bit processes, right?

From what I can tell, there is no support for 32 bit processes debugging
64 bit ones. Is that something you plan to add in the future, or do you
consider that out of scope? In either case, a comment would be helpful.

> +long arch_ptrace(struct task_struct *child, long request,
> +		 unsigned long addr, unsigned long data)
> +{
> +	int ret;
> +	unsigned long *datap = (unsigned long __user *)data;
> +
> +	switch (request) {
> +		case PTRACE_GET_THREAD_AREA:
> +			ret = put_user(child->thread.tp_value, datap);
> +			break;
> +
> +#ifdef CONFIG_HAVE_HW_BREAKPOINT
> +		case PTRACE_GETHBPREGS:
> +			ret = ptrace_gethbpregs(child, addr, datap);
> +			break;
> +
> +		case PTRACE_SETHBPREGS:
> +			ret = ptrace_sethbpregs(child, addr, datap);
> +			break;
> +#endif
> +
> +		default:
> +			ret = ptrace_request(child, request, addr, data);
> +			break;
> +	}
> +
> +	return ret;
> +}

Is there a reaons why these are not regsets but have their own ptrace
commands? I believe new architectures should generally not add ptrace
commands any more.

	Arnd


From robherring2 at gmail.com  Wed Aug 15 11:07:47 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 15 Aug 2012 10:07:47 -0500
Subject: imx6q restart is broken
In-Reply-To: <20120809092021.GQ18957@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
Message-ID: <502BBB43.5010403@gmail.com>

On 08/09/2012 04:20 AM, Russell King - ARM Linux wrote:
> On Thu, Aug 09, 2012 at 11:18:47AM +0800, Hui Wang wrote:
>> - at the last stage of reset, all non-boot cpus will call  
>> ipi_cpu_stop()->cpu_relax(), the cpu_relax() is defined to smp_mb() for  
>> V6, and smp_mb() is defined to dmb ("mcr p15, 0, %0, c7, c10, 5")
> 
> I suspect having this dmb inside cpu_relax() is flooding the
> interconnects with traffic, which then prevents other CPUs getting
> a look-in (maybe there's no fairness when it comes to dmb's.
> 
> If I'm right, you'll find is that even converting this to the ARMv7
> DMB instruction won't fix the problem.  It does, however, point
> towards a more serious problem - it means that any tight loop using
> dmb is detremental.  I have heard some people mention that even on
> various ARM SMP platforms, they have see quite an amount of
> interaction between the individual CPU cores, and I'm beginning
> to wonder whether this is why.
> 
> I think a useful test would be to only execute the DMB maybe once
> in 50 or 100 loops - the DMB is there to work around a different
> problem with the temporal locality of stores on the local CPU.  So,
> the only requirement is that we issue a DMB at some point while
> spinning waiting for another CPU to respond to our previous writes.

I think I am seeing a similar problem on highbank with a v7 only build.

>From what I've debugged, restart hangs for me on the L2x0 spinlock
during a writel. Changing the writel to writel_relaxed in the restart
hook fixes the problem. This skips barriers in the writel and for the
spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
should not be doing a dmb in my case on a v7 only build.

Rob

> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From arnd at arndb.de  Wed Aug 15 11:08:57 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:08:57 +0000
Subject: [PATCH v2 24/31] arm64: Add support for
 /proc/sys/debug/exception-trace
In-Reply-To: <1344966752-16102-25-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-25-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151508.57474.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> This patch allows setting of the show_unhandled_signals variable via
> /proc/sys/debug/exception-trace. The default value is currently 1
> showing unhandled user faults (undefined instructions, data aborts) and
> invalid signal stack frames.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Aug 15 11:11:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:11:11 +0000
Subject: [PATCH v2 25/31] arm64: Performance counters support
In-Reply-To: <1344966752-16102-26-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-26-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151511.11612.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> From: Will Deacon <will.deacon at arm.com>
> 
> This patch adds support for the AArch64 performance counters.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> ---
>  arch/arm64/include/asm/perf_event.h |   22 +
>  arch/arm64/include/asm/pmu.h        |   82 +++
>  arch/arm64/kernel/perf_event.c      | 1368 +++++++++++++++++++++++++++++++++++
>  tools/perf/perf.h                   |    6 +

Can you explain how AArch64 performance counters differ from the 32
bit ones? Do they work for AArch32 user space under AArch64 kernels?
Is it possible to share parts of the implementation with arch/arm?

	Arnd


From wade_farnsworth at mentor.com  Wed Aug 15 11:14:20 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Wed, 15 Aug 2012 08:14:20 -0700
Subject: [PATCH v2] ARM: support syscall tracing
Message-ID: <502BBCCC.1020006@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
__sys_trace was modified to call trace_sys_enter and
trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
---

This patch is an update of one I posted some months ago.  It has been
rebased to Linus's current master branch.
- v2: Implemented changes suggested by Will:
  - Folded _TIF_SYSCALL_TRACEPOINT into _TIF_SYSCALL_WORK to save an
    instruction in entry-common.S.
  - Moved calls to trace_sys_{enter,exit} to syscall_trace_{enter,exit}.

 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    4 +++-
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |   11 ++++++++++-
 arch/arm/kernel/ptrace.c           |   20 +++++++++++++++-----
 6 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..983e9eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bd..5ded667 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -148,6 +148,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
 #define TIF_SYSCALL_TRACE	8
 #define TIF_SYSCALL_AUDIT	9
+#define TIF_SYSCALL_TRACEPOINT	10
 #define TIF_POLLING_NRFLAG	16
 #define TIF_USING_IWMMXT	17
 #define TIF_MEMDIE		18	/* is terminating due to OOM killer */
@@ -160,12 +161,13 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
 
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0cab47d..a566ec2 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac5..b032c94 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
@@ -415,7 +424,7 @@ local_restart:
 1:
 #endif
 
-	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	tst     r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
 	bne	__sys_trace
 
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f..4e82fc1 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -918,7 +921,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
 	unsigned long ip;
 
-	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
+	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 		return scno;
 
 	current_thread_info()->syscall = scno;
@@ -930,10 +934,12 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 	ip = regs->ARM_ip;
 	regs->ARM_ip = dir;
 
-	if (dir == PTRACE_SYSCALL_EXIT)
-		tracehook_report_syscall_exit(regs, 0);
-	else if (tracehook_report_syscall_entry(regs))
-		current_thread_info()->syscall = -1;
+	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+		if (dir == PTRACE_SYSCALL_EXIT)
+			tracehook_report_syscall_exit(regs, 0);
+		else if (tracehook_report_syscall_entry(regs))
+			current_thread_info()->syscall = -1;
+	}
 
 	regs->ARM_ip = ip;
 	return current_thread_info()->syscall;
@@ -942,6 +948,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_enter(regs, ret);
 	audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
 			    regs->ARM_r2, regs->ARM_r3);
 	return ret;
@@ -950,6 +958,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_exit(regs, ret);
 	audit_syscall_exit(regs);
 	return ret;
 }
-- 
1.7.0.4



From arnd at arndb.de  Wed Aug 15 11:21:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:21:14 +0000
Subject: [PATCH v2 26/31] arm64: Miscellaneous library functions
In-Reply-To: <1344966752-16102-27-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-27-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151521.14663.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> +
> +/*
> + * Use compiler builtins for simple inline operations.
> + */
> +static inline unsigned long __ffs(unsigned long word)
> +{
> +	return __builtin_ffsl(word) - 1;
> +}
> +
> +static inline int ffs(int x)
> +{
> +	return __builtin_ffs(x);
> +}
> +
> +static inline unsigned long __fls(unsigned long word)
> +{
> +	return BITS_PER_LONG - 1 - __builtin_clzl(word);
> +}
> +
> +static inline int fls(int x)
> +{
> +	return x ? sizeof(x) * BITS_PER_BYTE - __builtin_clz(x) : 0;
> +}

These are all great, but I think whether to use them or not should
depend on the compiler version rather than the architecture in
general. Do we know a minimum gcc version that supports all of the
above? Then we could put that code into the generic files.

If that's not possible, we could still make the implementation
available for other architectures by moving it to

asm-generic/bitops/builtin-__ffs.h
asm-generic/bitops/builtin-ffs.h
asm-generic/bitops/builtin-__fls.h
asm-generic/bitops/builtin-fls.h

> --- /dev/null
> +++ b/arch/arm64/lib/bitops.c
> @@ -0,0 +1,25 @@
> +/*
> + * Copyright (C) 2012 ARM Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/spinlock.h>
> +#include <linux/atomic.h>
> +
> +#ifdef CONFIG_SMP
> +arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
> +       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
> +};
> +#endif

What?

I suppose this is a leftover from an earlier version using the
generic bitops, right?

	Arnd


From arnd at arndb.de  Wed Aug 15 11:23:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:23:21 +0000
Subject: [PATCH v2 27/31] arm64: Loadable modules
In-Reply-To: <1344966752-16102-28-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-28-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151523.21447.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> +
> +void *module_alloc(unsigned long size)
> +{
> +       return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
> +                                   GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
> +                                   __builtin_return_address(0));
> +}
> +

What is the reason for using a separate virtual address range for the
modules instead of falling back to the default module_alloc function
that uses vmalloc_exec()?

	Arnd


From jgutierrez at ti.com  Wed Aug 15 11:25:48 2012
From: jgutierrez at ti.com (Juan Gutierrez)
Date: Wed, 15 Aug 2012 10:25:48 -0500
Subject: [PATCH] omap: remoteproc: set bootaddr support
Message-ID: <1345044348-19898-1-git-send-email-jgutierrez@ti.com>

Some remote processors (like Omap4's DSP) need to explicitly
set a boot address from which they start executing code when
taken out of reset.

Support for this has been added to remoteproc code through
a set_bootaddr function in the platform data which, if needed,
must be set according to the backend rproc.

For omap4's dsp we can use the next control funtion:

  .set_bootaddr  = omap_ctrl_write_dsp_boot_addr

Signed-off-by: Juan Gutierrez <jgutierrez at ti.com>
Signed-off-by: Suman Anna <s-anna at ti.com>
---
 arch/arm/plat-omap/include/plat/remoteproc.h |    2 ++
 drivers/remoteproc/omap_remoteproc.c         |    3 +++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
index b10eac8..3c1c644 100644
--- a/arch/arm/plat-omap/include/plat/remoteproc.h
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -30,6 +30,7 @@ struct platform_device;
  * @ops: start/stop rproc handlers
  * @device_enable: omap-specific handler for enabling a device
  * @device_shutdown: omap-specific handler for shutting down a device
+ * @set_bootaddr: omap-specific handler for setting the rproc boot address
  */
 struct omap_rproc_pdata {
 	const char *name;
@@ -40,6 +41,7 @@ struct omap_rproc_pdata {
 	const struct rproc_ops *ops;
 	int (*device_enable) (struct platform_device *pdev);
 	int (*device_shutdown) (struct platform_device *pdev);
+	void(*set_bootaddr)(u32);
 };
 
 #if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
diff --git a/drivers/remoteproc/omap_remoteproc.c b/drivers/remoteproc/omap_remoteproc.c
index a1f7ac1..a0c168c 100644
--- a/drivers/remoteproc/omap_remoteproc.c
+++ b/drivers/remoteproc/omap_remoteproc.c
@@ -116,6 +116,9 @@ static int omap_rproc_start(struct rproc *rproc)
 	struct omap_rproc_pdata *pdata = pdev->dev.platform_data;
 	int ret;
 
+	if (pdata->set_bootaddr)
+		pdata->set_bootaddr(rproc->bootaddr);
+
 	oproc->nb.notifier_call = omap_rproc_mbox_callback;
 
 	/* every omap rproc is assigned a mailbox instance for messaging */
-- 
1.7.1



From shawn.guo at linaro.org  Wed Aug 15 11:31:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 15 Aug 2012 23:31:09 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815135947.GC2258@S2101-09.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
Message-ID: <20120815153107.GG2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 09:59:50PM +0800, Shawn Guo wrote:
> On Wed, Aug 15, 2012 at 05:25:40PM +0800, Dong Aisheng wrote:
> > On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
> > > That is just
> > > 
> > > 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
> > > 
> > > vs.
> > > 
> > > 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0
> > > 
> > > isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
> > > different story.)
> > > 
> > Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
> > Grant,
> > Do you know if dt macro can support it?
> > 
> I have the same doubt there.  Copied Stephen who might have a better
> insight on this.
> 
Rather than betting how DTC will implement macro, we'd better make the
the safest assumption - it will not support that syntax.  But we can
still work our issue, I guess.  Actually, the goal is all about
encoding the data that is currently defined in driver as a big array of
struct imx_pin_reg in device tree.

struct imx_pin_reg {
        u16 pid;
        u16 mux_reg;
        u16 conf_reg;
        u8 mux_mode;
        u16 input_reg;
        u8 input_val;
};

As we will figure out the pid from the mux_reg and conf_reg as below,
it becomes how we encode other fields.  An u64 can just cover them.
That said, the line below in binding doc

  MX35_PAD_COMPARE__SDMA_EXTDMA_2 11

becomes 

  MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x032c000807000000

We should probably have it be mux_reg + mux_mode + conf_reg +
input_reg + input_val or something to have the offset and value coupled.
Anyway, we will still have fsl,pins formatted as <PIN_FUNC_ID CONFIG>,
and only difference is PIN_FUNC_ID becomes an u64 integer.  But it can
save us that big array from the driver.

> > Now I'm a bit intend to admit that we probably could do like that if it supports.
> > The benefit i see is that it could save much code lines in driver while having
> > no using experience downgrade.
> > 
> > The left question is that how do we get the pin id from this kind of format data
> > (0x32c, 0x008, 7, 0x0, 0), probably one way may be:
> > For normal pads and NO_CONFIG pads, we could get it via:
> > mux_reg_offset / 4
> > for NO_MUX pads but have CONFIG pads, we may get it via:
> > mux_reg_offset / 4 + PIN_NO_MUX_ID_BASE + config_reg_offset /4
> 
> In case of NO_MUX, mux_reg_offset is 0, so the formula becomes:
> 
> 	PIN_NO_MUX_ID_BASE + config_reg_offset / 4
> 
> The question comes to how PIN_NO_MUX_ID_BASE gets determined?
> 
So PIN_NO_MUX_ID_BASE will be: the largest mux_reg_offset / 4 + 1, right?

-- 
Regards,
Shawn


From catalin.marinas at arm.com  Wed Aug 15 11:35:39 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 15 Aug 2012 16:35:39 +0100
Subject: [PATCH v2 27/31] arm64: Loadable modules
In-Reply-To: <201208151523.21447.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-28-git-send-email-catalin.marinas@arm.com>
 <201208151523.21447.arnd@arndb.de>
Message-ID: <20120815153538.GA14264@arm.com>

On Wed, Aug 15, 2012 at 04:23:21PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +
> > +void *module_alloc(unsigned long size)
> > +{
> > +       return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
> > +                                   GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
> > +                                   __builtin_return_address(0));
> > +}
> > +
> 
> What is the reason for using a separate virtual address range for the
> modules instead of falling back to the default module_alloc function
> that uses vmalloc_exec()?

Primarily branch relocation, we have a limitation to 128MB branch range.
The alternative would be to always compile the modules with a large
memory model but we may lose some performance and could make the
relocation handling even harder. What we do now is pretty much similar
to static linking but at module load time.

-- 
Catalin


From swarren at wwwdotorg.org  Wed Aug 15 11:39:02 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 09:39:02 -0600
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815135947.GC2258@S2101-09.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
Message-ID: <502BC296.8030108@wwwdotorg.org>

On 08/15/2012 07:59 AM, Shawn Guo wrote:
> On Wed, Aug 15, 2012 at 05:25:40PM +0800, Dong Aisheng wrote:
>> On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
>>> That is just
>>>
>>> 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
>>>
>>> vs.
>>>
>>> 	#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x32c, 0x008, 7, 0x0, 0
>>>
>>> isn't it? (Actually I'd not go for cpp as preprocessor, but that's a
>>> different story.)
>>>
>> Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
>> Grant,
>> Do you know if dt macro can support it?
>>
> I have the same doubt there.  Copied Stephen who might have a better
> insight on this.

You mean like C pre-processor on .dts files? There's currently no
support for anything like that at all, with either syntax above. I
honestly don't know if/when there will be.



From arnd at arndb.de  Wed Aug 15 11:52:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:52:40 +0000
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151552.40484.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> +static void arch_timer_reg_write(int reg, u32 val)
> +{
> +       switch (reg) {
> +       case ARCH_TIMER_REG_CTRL:
> +               asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
> +               break;
> +       case ARCH_TIMER_REG_TVAL:
> +               asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
> +               break;
> +       default:
> +               BUG();
> +       }
> +
> +       isb();
> +}
> +
> +static u32 arch_timer_reg_read(int reg)
> +{
> +       u32 val;
> +
> +       switch (reg) {
> +       case ARCH_TIMER_REG_CTRL:
> +               asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
> +               break;
> +       case ARCH_TIMER_REG_FREQ:
> +               asm volatile("mrs %0,   cntfrq_el0" : "=r" (val));
> +               break;
> +       case ARCH_TIMER_REG_TVAL:
> +               asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
> +               break;
> +       default:
> +               BUG();
> +       }
> +
> +       return val;
> +}

Are the inline assemblies the only things in this driver that are
specific to AArch64?
Are you planning to use the same file for 32 bit ARM as well, e.g.
when running a 32 bit guest kernel on a 64 bit host?

	Arnd


From arnd at arndb.de  Wed Aug 15 11:56:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:56:46 +0000
Subject: [PATCH v2 29/31] arm64: Miscellaneous header files
In-Reply-To: <1344966752-16102-30-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-30-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151556.46426.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
> new file mode 100644
> index 0000000..dc50de7
> --- /dev/null
> +++ b/arch/arm64/include/asm/cmpxchg.h

> +	default:
> +		__bad_cmpxchg(ptr, size);
> +		oldval = 0;
> +	}

I did not see a definition for __bad_cmpxchg but I may have missed that.
Please make sure that none exists, or just use BUILD_BUG_ON().

	Arnd


From arnd at arndb.de  Wed Aug 15 11:57:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 15:57:06 +0000
Subject: [PATCH v2 31/31] arm64: MAINTAINERS update
In-Reply-To: <1344966752-16102-32-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-32-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151557.06246.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> This patch updates the MAINTAINERS file for the AArch64 Linux kernel
> port.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>


Acked-by: Arnd Bergmann <arnd at arndb.de>


From swarren at wwwdotorg.org  Wed Aug 15 12:05:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 10:05:18 -0600
Subject: [PATCH V2 0/6] ARM: tegra: add CPU hotplug support
In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
Message-ID: <502BC8BE.8060800@wwwdotorg.org>

On 08/15/2012 03:22 AM, Joseph Lo wrote:
> This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
> 
> The first 3 patches make the CPU clock and reset control be a module and
> the abstraction APIs for TegraXX SoCs. And clean up some codes for later
> usage. Then add CPU hotplug support for Tegra20 and Tegra30.
> 
> Verified on Seaboard(Tegra20) and Cardhu(Tegra30)
> 
> V2:
> * add one more patch for enable HOTPLUG_CPU [6/6]

The build problem when HOTPLUG_CPU is disabled is still present. The
kernel needs to build with this option disabled.

Enabling HOTPLUG_CPU in defconfig doesn't force everyone to enable that
configuration option; not everyone uses tegra_defconfig, people don't
always update to the latest defconfig, people should be free to disable
functionality they don't need and still get a buildable & working
kernel, etc.

Besides, even if defconfig were a legitimate solution to this problem,
this series still wouldn't work with "git bisect", since the defconfig
patch comes after the patch that causes the build failure.

> * move all the SoC specific CPU shutdown code into platform_cpu_die [4/6]

The reboot problem is indeed solved.

P.S. It'd be nice to include a summary of what changed in each affected
patch, as well as in the cover letter.


From arnd at arndb.de  Wed Aug 15 12:07:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 16:07:55 +0000
Subject: [PATCH v2 30/31] arm64: Build infrastructure
In-Reply-To: <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151607.55669.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:

> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> new file mode 100644
> index 0000000..1ce3d04
> --- /dev/null
> +++ b/arch/arm64/Kconfig
> @@ -0,0 +1,261 @@
> +config ARM64
> +	def_bool y
> +	select OF
> +	select OF_EARLY_FLATTREE
> +	select IRQ_DOMAIN
> +	select HAVE_AOUT
> +	select HAVE_DMA_ATTRS
> +	select HAVE_DMA_API_DEBUG
> +	select HAVE_IDE

Please remove HAVE_AOUT and HAVE_IDE

> +	select HAVE_MEMBLOCK
> +	select RTC_LIB
> +	select SYS_SUPPORTS_APM_EMULATION

APM_EMULATION can probably go too

> +
> +config ARCH_PHYS_ADDR_T_64BIT
> +	def_bool y
> +
> +config HAVE_PWM
> +	bool

HAVE_PWM is going away soon.

> +config AARCH32_EMULATION
> +	bool "Kernel support for 32-bit EL0"
> +	depends on !ARM64_64K_PAGES
> +	select COMPAT_BINFMT_ELF
> +	help
> +	  This option enables support for a 32-bit EL0 running under a 64-bit
> +	  kernel at EL1. AArch32-specific components such as system calls,
> +	  the user helper functions, VFP support and the ptrace interface are
> +	  handled appropriately by the kernel.
> +
> +	  If you want to execute 32-bit userspace applications, say Y.
> +
> +config COMPAT
> +	def_bool y
> +	depends on AARCH32_EMULATION

As mentioned, you can just merge the two into CONFIG_COMPAT.

> +targets := Image Image.gz
> +
> +$(obj)/Image: vmlinux FORCE
> +	$(call if_changed,objcopy)
> +	@echo '  Kernel: $@ is ready'
> +
> +$(obj)/Image.gz: $(obj)/Image FORCE
> +	$(call if_changed,gzip)
> +	@echo '  Kernel: $@ is ready'

Drop the useless output, at least when building with make -s.

> +if [ -x /sbin/loadmap ]; then
> +  /sbin/loadmap
> +else
> +  echo "You have to install it yourself"
> +fi

What is loadmap?

> diff --git a/arch/arm64/configs/generic_defconfig b/arch/arm64/configs/generic_defconfig
> new file mode 100644
> index 0000000..d9aac95
> --- /dev/null
> +++ b/arch/arm64/configs/generic_defconfig

I think it can just be called "defconfig".

> diff --git a/arch/arm64/mm/Kconfig b/arch/arm64/mm/Kconfig
> new file mode 100644
> index 0000000..8e94e52
> --- /dev/null
> +++ b/arch/arm64/mm/Kconfig
> @@ -0,0 +1,5 @@
> +config MMU
> +	def_bool y
> +
> +config CPU_64
> +	def_bool y

This file can be dropped. You can unconditionally enable CONFIG_MMU,
and the CPU_64 symbol is pointless, just use CONFIG_64BIT.

	Arnd


From broonie at opensource.wolfsonmicro.com  Wed Aug 15 12:10:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 15 Aug 2012 17:10:31 +0100
Subject: [PATCH v2 0/4] ASoC machine driver for simple SoC with twl4030
In-Reply-To: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120815161031.GA15365@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 12:07:55PM +0300, Peter Ujfalusi wrote:

> Create new unified ASoC machine driver (with DT support) for boards using simple
> configuration for audio and using the twl4030 codec.
> This driver will replace the following machine drivers (since they are basically
> the same):
> igep0020, omap3beagle, omap3evm and overo.

Applied, thanks.


From arnd at arndb.de  Wed Aug 15 12:13:57 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 16:13:57 +0000
Subject: [PATCH v2 13/31] arm64: Device specific operations
In-Reply-To: <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151613.57400.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> This patch adds several definitions for device communication, including
> I/O accessors and ioremap(). The __raw_* accessors are implemented as
> inline asm to avoid compiler generation of post-indexed accesses (less
> efficient to emulate in a virtualised environment).
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>


Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Aug 15 12:16:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 16:16:00 +0000
Subject: [PATCH v2 14/31] arm64: DMA mapping API
In-Reply-To: <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
Message-ID: <201208151616.01114.arnd@arndb.de>

On Tuesday 14 August 2012, Catalin Marinas wrote:
> +static struct dma_map_ops arm64_swiotlb_dma_ops = {
> +       .alloc = arm64_swiotlb_alloc_coherent,
> +       .free = arm64_swiotlb_free_coherent,
> +       .map_page = arm64_swiotlb_map_page,
> +       .unmap_page = arm64_swiotlb_unmap_page,
> +       .map_sg = arm64_swiotlb_map_sg_attrs,
> +       .unmap_sg = arm64_swiotlb_unmap_sg_attrs,
> +       .sync_single_for_cpu = arm64_swiotlb_sync_single_for_cpu,
> +       .sync_single_for_device = arm64_swiotlb_sync_single_for_device,
> +       .sync_sg_for_cpu = arm64_swiotlb_sync_sg_for_cpu,
> +       .sync_sg_for_device = arm64_swiotlb_sync_sg_for_device,
> +       .dma_supported = swiotlb_dma_supported,
> +       .mapping_error = swiotlb_dma_mapping_error,
> +};
> +
> +void __init swiotlb_init_with_default_size(size_t default_size, int verbose);
> +
> +void __init arm64_swiotlb_init(size_t max_size)
> +{
> +       dma_ops = &arm64_swiotlb_dma_ops;
> +       swiotlb_init_with_default_size(min((size_t)SZ_64M, max_size), 1);
> +}

Why is swiotlb the default? I would expect that most devices can in fact
use the entire 64 bit address space, so you can use a simple linear
implementation for those.

	Arnd


From arnd at arndb.de  Wed Aug 15 12:16:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 16:16:56 +0000
Subject: [PATCH v2 27/31] arm64: Loadable modules
In-Reply-To: <20120815153538.GA14264@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151523.21447.arnd@arndb.de> <20120815153538.GA14264@arm.com>
Message-ID: <201208151616.56932.arnd@arndb.de>

On Wednesday 15 August 2012, Catalin Marinas wrote:
> Primarily branch relocation, we have a limitation to 128MB branch range.
> The alternative would be to always compile the modules with a large
> memory model but we may lose some performance and could make the
> relocation handling even harder. What we do now is pretty much similar
> to static linking but at module load time.

Ok, makes sense.

	Arnd


From arnd at arndb.de  Wed Aug 15 12:19:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 16:19:08 +0000
Subject: [GIT PULL V2] orion/kirkwood fixes for v3.6
In-Reply-To: <20120815140223.GG22226@titan.lakedaemon.net>
References: <20120814234442.GZ22226@titan.lakedaemon.net>
 <201208151335.47964.arnd@arndb.de>
 <20120815140223.GG22226@titan.lakedaemon.net>
Message-ID: <201208151619.09191.arnd@arndb.de>

On Wednesday 15 August 2012, Jason Cooper wrote:
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
> 

Ok, pulled that version now.

Thanks,

	Arnd


From will.deacon at arm.com  Wed Aug 15 12:21:57 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 17:21:57 +0100
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <502BBCCC.1020006@mentor.com>
References: <502BBCCC.1020006@mentor.com>
Message-ID: <20120815162157.GJ29448@mudshark.cambridge.arm.com>

Hi Wade,

On Wed, Aug 15, 2012 at 04:14:20PM +0100, Wade Farnsworth wrote:
> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
> index 3e0fc5f..4e82fc1 100644
> --- a/arch/arm/kernel/ptrace.c
> +++ b/arch/arm/kernel/ptrace.c
> @@ -30,6 +30,9 @@
>  #include <asm/pgtable.h>
>  #include <asm/traps.h>
>  
> +#define CREATE_TRACE_POINTS
> +#include <trace/events/syscalls.h>
> +
>  #define REG_PC	15
>  #define REG_PSR	16
>  /*
> @@ -918,7 +921,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  {
>  	unsigned long ip;
>  
> -	if (!test_thread_flag(TIF_SYSCALL_TRACE))
> +	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
> +	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
>  		return scno;

Can we now remove this hunk?

>  	current_thread_info()->syscall = scno;
> @@ -930,10 +934,12 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  	ip = regs->ARM_ip;
>  	regs->ARM_ip = dir;
>  
> -	if (dir == PTRACE_SYSCALL_EXIT)
> -		tracehook_report_syscall_exit(regs, 0);
> -	else if (tracehook_report_syscall_entry(regs))
> -		current_thread_info()->syscall = -1;
> +	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
> +		if (dir == PTRACE_SYSCALL_EXIT)
> +			tracehook_report_syscall_exit(regs, 0);
> +		else if (tracehook_report_syscall_entry(regs))
> +			current_thread_info()->syscall = -1;
> +	}

and also this one?

Will


From geert at linux-m68k.org  Wed Aug 15 12:34:46 2012
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Wed, 15 Aug 2012 18:34:46 +0200
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <201208151330.02112.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
 <201208151330.02112.arnd@arndb.de>
Message-ID: <CAMuHMdUEKNYFAU4N8KnJ0DPYgW7BRtaaJQSARDJCVjQOU2bFBw@mail.gmail.com>

On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>> +#define TCR_IPS_40BIT                (2 << 32)

By default, constants are int, i.e. 32-bit. So you must write

2ULL << 32

>> +#define TCR_ASID16           (1 << 36)

1ULL

> As a matter of coding style, I would much prefer tables like this to be
> written as
>
> #define TCR_IRGN_MASK           0x0000000003000300

0x0000000003000300ULL, to be safe

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From catalin.marinas at arm.com  Wed Aug 15 12:45:30 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 15 Aug 2012 17:45:30 +0100
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <CAMuHMdUEKNYFAU4N8KnJ0DPYgW7BRtaaJQSARDJCVjQOU2bFBw@mail.gmail.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
 <201208151330.02112.arnd@arndb.de>
 <CAMuHMdUEKNYFAU4N8KnJ0DPYgW7BRtaaJQSARDJCVjQOU2bFBw@mail.gmail.com>
Message-ID: <20120815164529.GB14264@arm.com>

On Wed, Aug 15, 2012 at 05:34:46PM +0100, Geert Uytterhoeven wrote:
> On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> >> +#define TCR_IPS_40BIT                (2 << 32)
> 
> By default, constants are int, i.e. 32-bit. So you must write
> 
> 2ULL << 32
> 
> >> +#define TCR_ASID16           (1 << 36)
> 
> 1ULL

Those higher constants are only used in assembly currently, so no
side-effects. But I agree that I should use something like:

	(_AC(1, UL) << 36)

(UL is sufficient on a 64-bit system)

Thanks.

-- 
Catalin


From anilkumar at ti.com  Wed Aug 15 12:47:02 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Wed, 15 Aug 2012 16:47:02 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <20120815125338.GA13544@opensource.wolfsonmicro.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>

Hi Mark,

On Wed, Aug 15, 2012 at 18:23:39, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 02:25:18PM +0000, AnilKumar, Chimata wrote:
> 
> > AM335x EVM have one dedicated input supply which provide supplies to all
> > the PMIC regulators. According to tps65910 "VDD1 regulator" input supply
> > is from vcc1 so we have to create a dummy/parent/some node to handle this.
> > Example below has the details.
> 
> Your device tree should accurately reflect the hardware.
> 
> > Similarly we have to add 7 more fixed regulators entries to provide input
> > supply to different PMIC regulators.
> 
> If you have all these unrelated supplies in the system then your device
> tree should accurately reflect that.  However this would be a very

In that case I have to add all these fixed regulators.

> unusual hardware design.  Usually there would be a very small set of
> system supply rails, frequently only one.

In case of AM335X-EVM one dedicated supply (5v) feeding to all the input
supplies (vcc1-7 and vccio) of the regulators.

tps65910 PMIC have vcc1-7 and vccio input supplies which are feeding to
all the regulators. (like one - one and one - many).

Tps65910 regulator drivers registration fails if we not providing the
correct input supply with supply name. One option I can see is that
fixed voltage regulators. If we do this then total 21 (8 input supply
fixed regulators and others are out regulators) are present in the system.

If this is the correct approach then I will submit next version of patch.

Thanks
AnilKumar




From matt at genesi-usa.com  Wed Aug 15 12:49:01 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 15 Aug 2012 11:49:01 -0500
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815153107.GG2258@S2101-09.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120815153107.GG2258@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bkNEJbQgwcdZs8PozCgVyOfUE=bDCGkRkKV3VMfbvRMgw@mail.gmail.com>

On Wed, Aug 15, 2012 at 10:31 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 09:59:50PM +0800, Shawn Guo wrote:
>> On Wed, Aug 15, 2012 at 05:25:40PM +0800, Dong Aisheng wrote:
>> > On Wed, Aug 15, 2012 at 03:51:17PM +0800, Uwe Kleine-K?nig wrote:
>> > Hmm, not sure if dt macro may support this kind of syntax but yes if it supports.
>> > Grant,
>> >
>> > Do you know if dt macro can support it?
>>
>> I have the same doubt there.  Copied Stephen who might have a better
>> insight on this.
>>
> Rather than betting how DTC will implement macro, we'd better make the
> the safest assumption - it will not support that syntax.

It won't. DT is defined by properties and those properties have cells.
Properties
that have more than one cell or multiple definitions in them have to have a
#size-cells property to go with it somehow.

I don't see what the problem would be here; you want to define pin properties,
sure, they are intrinsically defined by 3 possible registers and value pairs. In
actual fact if you drill down to this, what happens is you get a pin property
which defines offsets into the unit, and values to stuff into those
registers, so
you could either dictate a size-cell of 6 (3 pairs of reg-value) or 2
(reg, value).
It would be more convenient for a driver to know what those pairs are maybe,
so 6 is better.

> still work our issue, I guess.  Actually, the goal is all about
> encoding the data that is currently defined in driver as a big array of
> struct imx_pin_reg in device tree.

Absolutely!

> struct imx_pin_reg {
>         u16 pid;
>         u16 mux_reg;
>         u16 conf_reg;
>         u8 mux_mode;
>         u16 input_reg;
>         u8 input_val;
> };
>
> As we will figure out the pid from the mux_reg and conf_reg as below,
> it becomes how we encode other fields.  An u64 can just cover them.

Or 3 pairs of values can encode them. Don't needlessly encode data in
the device tree that can just exist in a cell of a property.

> That said, the line below in binding doc
>
>   MX35_PAD_COMPARE__SDMA_EXTDMA_2 11
>
> becomes
>
>   MX35_PAD_COMPARE__SDMA_EXTDMA_2 0x032c000807000000

I can only give a quick example on MX51, MX53 or MX6 since that's my
experience, but essentially.. you're overthinking it.

What it becomes is

iomuxc at 0x73f08000 {
  fsl,iomux-pins = <mux value ctrl value ipp value
/* MX53_PIN_SD4_CMD__SD4_CMD */
                            mux value ctrl value ipp value
       /* etc. */
                            ...>;

You can encode those values *in the driver* as a hash or lookup to get
names for them if you like in the driver.. or build them at runtime
for truly odd combinations or not-usual pin configurations. In any
case, those reg can be "valid" 0 since 0 is IOMUXC_GPR0.. which you do
not want to set. That said, setting IOMUXC_GPR can be useful! Ethernet
may need (on MX6 examples) ENET_CLK_SEL set, IPU may need to select
MIPI gasket or IOMUX. Usually though I would assume that you would
have properties for these though as you do not want to "trash"
bootloader configuration of any clock or mux settings, just update
them (so, fsl,ethernet-clock-sel =1 or fsl,ipu-iomux = <1 0>)

That said, the usual thing is to set them to "-1" explicitly in the
tree and let the DT code sort out what -1 actually means (usually
0xffffffff since by default OF cells are 32-bit, but it's the same
difference if it's a 64-bit device tree binding) since this is totally
invalid. That way a pin with no ctrl or ipp, or ctrl but no ipp or mux
would be

fsl,iomux-pin = <-1 -1 0x05c 0x85 -1 -1
                        ...>;

> We should probably have it be mux_reg + mux_mode + conf_reg +
> input_reg + input_val or something to have the offset and value coupled.
> Anyway, we will still have fsl,pins formatted as <PIN_FUNC_ID CONFIG>,
> and only difference is PIN_FUNC_ID becomes an u64 integer.  But it can
> save us that big array from the driver.

As above. Please do not encode the data. Don't assume you can encode a
64-bit integer either.. that's not in any core binding. What you need
here is a multi-cell property as above. That  way it can be expanded
if MX7 has an extra iomux register set for something else ("enable
awesome mode" or so).

>> The question comes to how PIN_NO_MUX_ID_BASE gets determined?
>>
> So PIN_NO_MUX_ID_BASE will be: the largest mux_reg_offset / 4 + 1, right?

Nope. It should be -1. Do it properly, please. Do not "hack" numbers,
as this can mean the driver has to intimately know the hardware when
it is needless to do so. The driver MAY however  assume that
IOMUXC_BASE_ADDR + 0xffffffff is not really possible - check the
offset generated and if it goes beyond the reg = <start length> range,
it is obviously invalid. Or just check the offset against the length..
walking into unmapped memory invalid is invalid across the board.

One thing though, I don't understand why Dong thinks it would be more
difficult to look up a register number in the docs (PDF search, Dong,
it's easy!) versus looking up the binding number in the binding
document. These pairs are ALREADY encoded in older kernels too in that
64 bit integer. Just split them back out again (there's code in
iomux-v3.h to do this still in the kernel) and you can encode your
device tree. Including headers, macros is unecessary. You may want to
petition Freescale to create a plugin for their IOMUX tool though that
not only spits out the reg/pair values in C source format (this is
very useful, though, since you can paste it into anything that can use
writel() to set up all pins exactly as your board designer dictated),
but also does it in device-tree binding pairs as above. That would
make it a lot easier all round, too.. nobody needs to look up a
binding, the binding is "fsl,iomux-pins defines pairs of offsets and
values inside the IOMUXC unit. These offsets and values are defined in
the manual. <some examples here>"

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From will.deacon at arm.com  Wed Aug 15 12:54:01 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 17:54:01 +0100
Subject: [PATCH 2/3] ARM: mm: avoid taking ASID spinlock on fastpath
In-Reply-To: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
Message-ID: <1345049642-29704-3-git-send-email-will.deacon@arm.com>

When scheduling a new mm, we take a spinlock so that we can:

  1. Safely allocate a new ASID, if required
  2. Update our active_asids field without worrying about parallel
     updates to reserved_asids
  3. Ensure that we flush our local TLB, if required

However, this has the nasty affect of serialising context-switch across
all CPUs in the system. The usual (fast) case is where the next mm has
a valid ASID for the current generation. In such a scenario, we can
avoid taking the lock and instead use atomic64_xchg to update the
active_asids variable for the current CPU. If a rollover occurs on
another CPU (which would take the lock), when copying the active_asids
into the reserved_asids another atomic64_xchg is used to replace each
active_asids with 0. The fast path can then detect this case and fall
back to spinning on the lock.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/context.c |   23 +++++++++++++++--------
 1 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2d1b42d..733774f 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -38,9 +38,9 @@
 #define ASID_FIRST_VERSION	(1ULL << ASID_BITS)
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
-static u64 cpu_last_asid = ASID_FIRST_VERSION;
+static atomic64_t cpu_last_asid = ATOMIC64_INIT(ASID_FIRST_VERSION);
 
-static DEFINE_PER_CPU(u64, active_asids);
+static DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
@@ -112,9 +112,10 @@ static void flush_context(unsigned int cpu)
 	int i;
 
 	/* Update the list of reserved ASIDs. */
-	per_cpu(active_asids, cpu) = 0;
 	for_each_possible_cpu(i)
-		per_cpu(reserved_asids, i) = per_cpu(active_asids, i);
+		per_cpu(reserved_asids, i) =
+			atomic64_xchg(&per_cpu(active_asids, i), 0);
+	per_cpu(reserved_asids, cpu) = 0;
 
 	/* Queue a TLB invalidate and flush the I-cache if necessary. */
 	if (!tlb_ops_need_broadcast())
@@ -144,7 +145,8 @@ static void new_context(struct mm_struct *mm, unsigned int cpu)
 		 * Our current ASID was active during a rollover, we can
 		 * continue to use it and this was just a false alarm.
 		 */
-		asid = (cpu_last_asid & ASID_MASK) | (asid & ~ASID_MASK);
+		asid = (atomic64_read(&cpu_last_asid) & ASID_MASK) | \
+		       (asid & ~ASID_MASK);
 	} else {
 		/*
 		 * Allocate a free ASID. If we can't find one, take a
@@ -152,7 +154,7 @@ static void new_context(struct mm_struct *mm, unsigned int cpu)
 		 * as requiring flushes.
 		 */
 		do {
-			asid = ++cpu_last_asid;
+			asid = atomic64_inc_return(&cpu_last_asid);
 			if ((asid & ~ASID_MASK) == 0)
 				flush_context(cpu);
 		} while (is_reserved_asid(asid, ~ASID_MASK));
@@ -170,6 +172,10 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 	if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
 		__check_kvm_seq(mm);
 
+	if (!((mm->context.id ^ atomic64_read(&cpu_last_asid)) >> ASID_BITS) &&
+	    atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
+		goto switch_mm_fastpath;
+
 	/*
 	 * Required during context switch to avoid speculative page table
 	 * walking with the wrong TTBR.
@@ -178,15 +184,16 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 
 	raw_spin_lock_irqsave(&cpu_asid_lock, flags);
 	/* Check that our ASID belongs to the current generation. */
-	if ((mm->context.id ^ cpu_last_asid) >> ASID_BITS)
+	if ((mm->context.id ^ atomic64_read(&cpu_last_asid)) >> ASID_BITS)
 		new_context(mm, cpu);
 
-	*this_cpu_ptr(&active_asids) = mm->context.id;
+	atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
 	cpumask_set_cpu(cpu, mm_cpumask(mm));
 
 	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
 		local_flush_tlb_all();
 	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
 
+switch_mm_fastpath:
 	cpu_switch_mm(mm->pgd, mm);
 }
-- 
1.7.4.1



From will.deacon at arm.com  Wed Aug 15 12:54:00 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 17:54:00 +0100
Subject: [PATCH 1/3] ARM: mm: remove IPI broadcasting on ASID rollover
In-Reply-To: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
Message-ID: <1345049642-29704-2-git-send-email-will.deacon@arm.com>

ASIDs are allocated to MMU contexts based on a rolling counter. This
means that after 255 allocations we must invalidate all existing ASIDs
via an expensive IPI mechanism to synchronise all of the online CPUs and
ensure that all tasks execute with an ASID from the new generation.

This patch changes the rollover behaviour so that we rely instead on the
hardware broadcasting of the TLB invalidation to avoid the IPI calls.
This works by keeping track of the active ASID on each core, which is
then reserved in the case of a rollover so that currently scheduled
tasks can continue to run. For cores without hardware TLB broadcasting,
we keep track of pending flushes in a cpumask, so cores can flush their
local TLB before scheduling a new mm.

Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/mmu.h         |   11 +--
 arch/arm/include/asm/mmu_context.h |   82 +---------------
 arch/arm/mm/context.c              |  186 +++++++++++++++++-------------------
 3 files changed, 93 insertions(+), 186 deletions(-)

diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 1496565..5b53b53 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -5,18 +5,15 @@
 
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
-	unsigned int id;
-	raw_spinlock_t id_lock;
+	u64 id;
 #endif
 	unsigned int kvm_seq;
 } mm_context_t;
 
 #ifdef CONFIG_CPU_HAS_ASID
-#define ASID(mm)	((mm)->context.id & 255)
-
-/* init_mm.context.id_lock should be initialized. */
-#define INIT_MM_CONTEXT(name)                                                 \
-	.context.id_lock    = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
+#define ASID_BITS	8
+#define ASID_MASK	((~0ULL) << ASID_BITS)
+#define ASID(mm)	((mm)->context.id & ~ASID_MASK)
 #else
 #define ASID(mm)	(0)
 #endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 0306bc6..a64f61c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -24,84 +24,8 @@ void __check_kvm_seq(struct mm_struct *mm);
 
 #ifdef CONFIG_CPU_HAS_ASID
 
-/*
- * On ARMv6, we have the following structure in the Context ID:
- *
- * 31                         7          0
- * +-------------------------+-----------+
- * |      process ID         |   ASID    |
- * +-------------------------+-----------+
- * |              context ID             |
- * +-------------------------------------+
- *
- * The ASID is used to tag entries in the CPU caches and TLBs.
- * The context ID is used by debuggers and trace logic, and
- * should be unique within all running processes.
- */
-#define ASID_BITS		8
-#define ASID_MASK		((~0) << ASID_BITS)
-#define ASID_FIRST_VERSION	(1 << ASID_BITS)
-
-extern unsigned int cpu_last_asid;
-
-void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-void __new_context(struct mm_struct *mm);
-void cpu_set_reserved_ttbr0(void);
-
-static inline void switch_new_context(struct mm_struct *mm)
-{
-	unsigned long flags;
-
-	__new_context(mm);
-
-	local_irq_save(flags);
-	cpu_switch_mm(mm->pgd, mm);
-	local_irq_restore(flags);
-}
-
-static inline void check_and_switch_context(struct mm_struct *mm,
-					    struct task_struct *tsk)
-{
-	if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
-		__check_kvm_seq(mm);
-
-	/*
-	 * Required during context switch to avoid speculative page table
-	 * walking with the wrong TTBR.
-	 */
-	cpu_set_reserved_ttbr0();
-
-	if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
-		/*
-		 * The ASID is from the current generation, just switch to the
-		 * new pgd. This condition is only true for calls from
-		 * context_switch() and interrupts are already disabled.
-		 */
-		cpu_switch_mm(mm->pgd, mm);
-	else if (irqs_disabled())
-		/*
-		 * Defer the new ASID allocation until after the context
-		 * switch critical region since __new_context() cannot be
-		 * called with interrupts disabled (it sends IPIs).
-		 */
-		set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
-	else
-		/*
-		 * That is a direct call to switch_mm() or activate_mm() with
-		 * interrupts enabled and a new context.
-		 */
-		switch_new_context(mm);
-}
-
-#define init_new_context(tsk,mm)	(__init_new_context(tsk,mm),0)
-
-#define finish_arch_post_lock_switch \
-	finish_arch_post_lock_switch
-static inline void finish_arch_post_lock_switch(void)
-{
-	if (test_and_clear_thread_flag(TIF_SWITCH_MM))
-		switch_new_context(current->mm);
-}
+void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
+#define init_new_context(tsk,mm)	({ mm->context.id = 0; })
 
 #else	/* !CONFIG_CPU_HAS_ASID */
 
@@ -143,6 +67,7 @@ static inline void finish_arch_post_lock_switch(void)
 #endif	/* CONFIG_CPU_HAS_ASID */
 
 #define destroy_context(mm)		do { } while(0)
+#define activate_mm(prev,next)		switch_mm(prev, next, NULL)
 
 /*
  * This is called when "tsk" is about to enter lazy TLB mode.
@@ -186,6 +111,5 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 }
 
 #define deactivate_mm(tsk,mm)	do { } while (0)
-#define activate_mm(prev,next)	switch_mm(prev, next, NULL)
 
 #endif
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 119bc52..2d1b42d 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -2,6 +2,9 @@
  *  linux/arch/arm/mm/context.c
  *
  *  Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
+ *  Copyright (C) 2012 ARM Limited
+ *
+ *  Author: Will Deacon <will.deacon at arm.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,14 +17,35 @@
 #include <linux/percpu.h>
 
 #include <asm/mmu_context.h>
+#include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
 
+/*
+ * On ARMv6, we have the following structure in the Context ID:
+ *
+ * 31                         7          0
+ * +-------------------------+-----------+
+ * |      process ID         |   ASID    |
+ * +-------------------------+-----------+
+ * |              context ID             |
+ * +-------------------------------------+
+ *
+ * The ASID is used to tag entries in the CPU caches and TLBs.
+ * The context ID is used by debuggers and trace logic, and
+ * should be unique within all running processes.
+ */
+#define ASID_FIRST_VERSION	(1ULL << ASID_BITS)
+
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
-unsigned int cpu_last_asid = ASID_FIRST_VERSION;
+static u64 cpu_last_asid = ASID_FIRST_VERSION;
+
+static DEFINE_PER_CPU(u64, active_asids);
+static DEFINE_PER_CPU(u64, reserved_asids);
+static cpumask_t tlb_flush_pending;
 
 #ifdef CONFIG_ARM_LPAE
-void cpu_set_reserved_ttbr0(void)
+static void cpu_set_reserved_ttbr0(void)
 {
 	unsigned long ttbl = __pa(swapper_pg_dir);
 	unsigned long ttbh = 0;
@@ -37,7 +61,7 @@ void cpu_set_reserved_ttbr0(void)
 	isb();
 }
 #else
-void cpu_set_reserved_ttbr0(void)
+static void cpu_set_reserved_ttbr0(void)
 {
 	u32 ttb;
 	/* Copy TTBR1 into TTBR0 */
@@ -83,124 +107,86 @@ static int __init contextidr_notifier_init(void)
 arch_initcall(contextidr_notifier_init);
 #endif
 
-/*
- * We fork()ed a process, and we need a new context for the child
- * to run in.
- */
-void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+static void flush_context(unsigned int cpu)
 {
-	mm->context.id = 0;
-	raw_spin_lock_init(&mm->context.id_lock);
-}
+	int i;
 
-static void flush_context(void)
-{
-	cpu_set_reserved_ttbr0();
-	local_flush_tlb_all();
-	if (icache_is_vivt_asid_tagged()) {
+	/* Update the list of reserved ASIDs. */
+	per_cpu(active_asids, cpu) = 0;
+	for_each_possible_cpu(i)
+		per_cpu(reserved_asids, i) = per_cpu(active_asids, i);
+
+	/* Queue a TLB invalidate and flush the I-cache if necessary. */
+	if (!tlb_ops_need_broadcast())
+		cpumask_set_cpu(cpu, &tlb_flush_pending);
+	else
+		cpumask_setall(&tlb_flush_pending);
+
+	if (icache_is_vivt_asid_tagged())
 		__flush_icache_all();
-		dsb();
-	}
 }
 
-#ifdef CONFIG_SMP
+static int is_reserved_asid(u64 asid, u64 mask)
+{
+	int cpu;
+	for_each_possible_cpu(cpu)
+		if ((per_cpu(reserved_asids, cpu) & mask) == (asid & mask))
+			return 1;
+	return 0;
+}
 
-static void set_mm_context(struct mm_struct *mm, unsigned int asid)
+static void new_context(struct mm_struct *mm, unsigned int cpu)
 {
-	unsigned long flags;
+	u64 asid = mm->context.id;
 
-	/*
-	 * Locking needed for multi-threaded applications where the
-	 * same mm->context.id could be set from different CPUs during
-	 * the broadcast. This function is also called via IPI so the
-	 * mm->context.id_lock has to be IRQ-safe.
-	 */
-	raw_spin_lock_irqsave(&mm->context.id_lock, flags);
-	if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
+	if (asid != 0 && is_reserved_asid(asid, ULLONG_MAX)) {
 		/*
-		 * Old version of ASID found. Set the new one and
-		 * reset mm_cpumask(mm).
+		 * Our current ASID was active during a rollover, we can
+		 * continue to use it and this was just a false alarm.
 		 */
-		mm->context.id = asid;
+		asid = (cpu_last_asid & ASID_MASK) | (asid & ~ASID_MASK);
+	} else {
+		/*
+		 * Allocate a free ASID. If we can't find one, take a
+		 * note of the currently active ASIDs and mark the TLBs
+		 * as requiring flushes.
+		 */
+		do {
+			asid = ++cpu_last_asid;
+			if ((asid & ~ASID_MASK) == 0)
+				flush_context(cpu);
+		} while (is_reserved_asid(asid, ~ASID_MASK));
 		cpumask_clear(mm_cpumask(mm));
 	}
-	raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
 
-	/*
-	 * Set the mm_cpumask(mm) bit for the current CPU.
-	 */
-	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+	mm->context.id = asid;
 }
 
-/*
- * Reset the ASID on the current CPU. This function call is broadcast
- * from the CPU handling the ASID rollover and holding cpu_asid_lock.
- */
-static void reset_context(void *info)
+void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 {
-	unsigned int asid;
+	unsigned long flags;
 	unsigned int cpu = smp_processor_id();
-	struct mm_struct *mm = current->active_mm;
-
-	smp_rmb();
-	asid = cpu_last_asid + cpu + 1;
-
-	flush_context();
-	set_mm_context(mm, asid);
-
-	/* set the new ASID */
-	cpu_switch_mm(mm->pgd, mm);
-}
-
-#else
 
-static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
-{
-	mm->context.id = asid;
-	cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
-}
+	if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
+		__check_kvm_seq(mm);
 
-#endif
-
-void __new_context(struct mm_struct *mm)
-{
-	unsigned int asid;
-
-	raw_spin_lock(&cpu_asid_lock);
-#ifdef CONFIG_SMP
 	/*
-	 * Check the ASID again, in case the change was broadcast from
-	 * another CPU before we acquired the lock.
+	 * Required during context switch to avoid speculative page table
+	 * walking with the wrong TTBR.
 	 */
-	if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
-		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
-		raw_spin_unlock(&cpu_asid_lock);
-		return;
-	}
-#endif
-	/*
-	 * At this point, it is guaranteed that the current mm (with
-	 * an old ASID) isn't active on any other CPU since the ASIDs
-	 * are changed simultaneously via IPI.
-	 */
-	asid = ++cpu_last_asid;
-	if (asid == 0)
-		asid = cpu_last_asid = ASID_FIRST_VERSION;
+	cpu_set_reserved_ttbr0();
 
-	/*
-	 * If we've used up all our ASIDs, we need
-	 * to start a new version and flush the TLB.
-	 */
-	if (unlikely((asid & ~ASID_MASK) == 0)) {
-		asid = cpu_last_asid + smp_processor_id() + 1;
-		flush_context();
-#ifdef CONFIG_SMP
-		smp_wmb();
-		smp_call_function(reset_context, NULL, 1);
-#endif
-		cpu_last_asid += NR_CPUS;
-	}
+	raw_spin_lock_irqsave(&cpu_asid_lock, flags);
+	/* Check that our ASID belongs to the current generation. */
+	if ((mm->context.id ^ cpu_last_asid) >> ASID_BITS)
+		new_context(mm, cpu);
 
-	set_mm_context(mm, asid);
-	raw_spin_unlock(&cpu_asid_lock);
+	*this_cpu_ptr(&active_asids) = mm->context.id;
+	cpumask_set_cpu(cpu, mm_cpumask(mm));
+
+	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
+		local_flush_tlb_all();
+	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+
+	cpu_switch_mm(mm->pgd, mm);
 }
-- 
1.7.4.1



From will.deacon at arm.com  Wed Aug 15 12:53:59 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 17:53:59 +0100
Subject: [PATCH 0/3] New algorithm for ASID allocation and rollover
Message-ID: <1345049642-29704-1-git-send-email-will.deacon@arm.com>

Hello,

Following some investigation into preempt-rt Linux, it became apparent
that ASID rollover can happen fairly regularly under certain heavy
scheduling workloads. Each time this happens, we broadcast an interrupt
to the secondary CPUs so that we can reset the global ASID numberspace
without assigning duplicate ASIDs to different tasks or accidentally
assigning different ASIDs to threads of the same process.

This leads to a large number of expensive IPIs between cores:

           CPU0       CPU1
IPI0:          0          0  Timer broadcast interrupts
IPI1:      23165     115888  Rescheduling interrupts
IPI2:          0          0  Function call interrupts
IPI3:       6619       1123  Single function call interrupts <---- IPIs
IPI4:          0          0  CPU stop interrupts

Digging deeper, this also leads to an extremely varied waittime on the
cpu_asid_lock. Granted this is only contended for <1% of the time, but
the waittime varies between 0.5 and 734 us!

After some discussion, it became apparent that tracking the ASIDs
currently active on the cores in the system means that, on rollover, we
can automatically reserve those that are in use without having to stop
the world.

This patch series develops that idea so that:

  - We can support cores without hardware broadcasting of TLB maintenance
    operations without resorting to IPIs.
  - The fastpath (that is, the task already has a valid ASID) remains
    lockless.
  - Assuming that the number of CPUs is less than the number of ASIDs,
    the algorithm scales as they increase (using a bitmap for searching).
  - Generation overflow is not a problem (we use a u64).

With these patches applied, I saw ~2% improvement in hackbench scores on
my dual-core Cortex-A15 board and the interrupt statistics now appear as:

           CPU0       CPU1
IPI0:          0          0  Timer broadcast interrupts
IPI1:      64888      74560  Rescheduling interrupts
IPI2:          0          0  Function call interrupts
IPI3:          1          3  Single function call interrupts <--- Much better!
IPI4:          0          0  CPU stop interrupts

Finally, the waittime on cpu_asid_lock reduced to 0.5 - 4.6 us.

All feedback welcome.

Will


Will Deacon (3):
  ARM: mm: remove IPI broadcasting on ASID rollover
  ARM: mm: avoid taking ASID spinlock on fastpath
  ARM: mm: use bitmap operations when allocating new ASIDs

 arch/arm/include/asm/mmu.h         |   11 +--
 arch/arm/include/asm/mmu_context.h |   82 +--------------
 arch/arm/mm/context.c              |  207 +++++++++++++++++++-----------------
 3 files changed, 115 insertions(+), 185 deletions(-)

-- 
1.7.4.1


From will.deacon at arm.com  Wed Aug 15 12:54:02 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 17:54:02 +0100
Subject: [PATCH 3/3] ARM: mm: use bitmap operations when allocating new ASIDs
In-Reply-To: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
Message-ID: <1345049642-29704-4-git-send-email-will.deacon@arm.com>

When allocating a new ASID, we must take care not to re-assign a
reserved ASID-value to a new mm. This requires us to check each
candidate ASID against those currently reserved by other cores before
assigning a new ASID to the current mm.

This patch improves the ASID allocation algorithm by using a
bitmap-based approach. Rather than iterating over the reserved ASID
array for each candidate ASID, we simply find the first zero bit,
ensuring that those indices corresponding to reserved ASIDs are set
when flushing during a rollover event.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/context.c |   56 +++++++++++++++++++++++++++++++-----------------
 1 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 733774f..1a9e2ab 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -36,9 +36,14 @@
  * should be unique within all running processes.
  */
 #define ASID_FIRST_VERSION	(1ULL << ASID_BITS)
+#define NUM_USER_ASIDS		(ASID_FIRST_VERSION - 1)
+
+#define ASID_TO_IDX(asid)	((asid & ~ASID_MASK) - 1)
+#define IDX_TO_ASID(idx)	((idx + 1) & ~ASID_MASK)
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
-static atomic64_t cpu_last_asid = ATOMIC64_INIT(ASID_FIRST_VERSION);
+static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
+static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
 static DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
@@ -110,12 +115,19 @@ arch_initcall(contextidr_notifier_init);
 static void flush_context(unsigned int cpu)
 {
 	int i;
-
-	/* Update the list of reserved ASIDs. */
-	for_each_possible_cpu(i)
-		per_cpu(reserved_asids, i) =
-			atomic64_xchg(&per_cpu(active_asids, i), 0);
-	per_cpu(reserved_asids, cpu) = 0;
+	u64 asid;
+
+	/* Update the list of reserved ASIDs and the ASID bitmap. */
+	bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
+	for_each_possible_cpu(i) {
+		if (i == cpu) {
+			asid = 0;
+		} else {
+			asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
+			__set_bit(ASID_TO_IDX(asid), asid_map);
+		}
+		per_cpu(reserved_asids, i) = asid;
+	}
 
 	/* Queue a TLB invalidate and flush the I-cache if necessary. */
 	if (!tlb_ops_need_broadcast())
@@ -127,11 +139,11 @@ static void flush_context(unsigned int cpu)
 		__flush_icache_all();
 }
 
-static int is_reserved_asid(u64 asid, u64 mask)
+static int is_reserved_asid(u64 asid)
 {
 	int cpu;
 	for_each_possible_cpu(cpu)
-		if ((per_cpu(reserved_asids, cpu) & mask) == (asid & mask))
+		if (per_cpu(reserved_asids, cpu) == asid)
 			return 1;
 	return 0;
 }
@@ -139,25 +151,29 @@ static int is_reserved_asid(u64 asid, u64 mask)
 static void new_context(struct mm_struct *mm, unsigned int cpu)
 {
 	u64 asid = mm->context.id;
+	u64 generation = atomic64_read(&asid_generation);
 
-	if (asid != 0 && is_reserved_asid(asid, ULLONG_MAX)) {
+	if (asid != 0 && is_reserved_asid(asid)) {
 		/*
 		 * Our current ASID was active during a rollover, we can
 		 * continue to use it and this was just a false alarm.
 		 */
-		asid = (atomic64_read(&cpu_last_asid) & ASID_MASK) | \
-		       (asid & ~ASID_MASK);
+		asid = generation | (asid & ~ASID_MASK);
 	} else {
 		/*
 		 * Allocate a free ASID. If we can't find one, take a
 		 * note of the currently active ASIDs and mark the TLBs
 		 * as requiring flushes.
 		 */
-		do {
-			asid = atomic64_inc_return(&cpu_last_asid);
-			if ((asid & ~ASID_MASK) == 0)
-				flush_context(cpu);
-		} while (is_reserved_asid(asid, ~ASID_MASK));
+		asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+		if (asid == NUM_USER_ASIDS) {
+			generation = atomic64_add_return(ASID_FIRST_VERSION,
+							 &asid_generation);
+			flush_context(cpu);
+			asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+		}
+		__set_bit(asid, asid_map);
+		asid = generation | IDX_TO_ASID(asid);
 		cpumask_clear(mm_cpumask(mm));
 	}
 
@@ -172,8 +188,8 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 	if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
 		__check_kvm_seq(mm);
 
-	if (!((mm->context.id ^ atomic64_read(&cpu_last_asid)) >> ASID_BITS) &&
-	    atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
+	if (!((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
+	    && atomic64_xchg(&per_cpu(active_asids, cpu), mm->context.id))
 		goto switch_mm_fastpath;
 
 	/*
@@ -184,7 +200,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
 
 	raw_spin_lock_irqsave(&cpu_asid_lock, flags);
 	/* Check that our ASID belongs to the current generation. */
-	if ((mm->context.id ^ atomic64_read(&cpu_last_asid)) >> ASID_BITS)
+	if ((mm->context.id ^ atomic64_read(&asid_generation)) >> ASID_BITS)
 		new_context(mm, cpu);
 
 	atomic64_set(&per_cpu(active_asids, cpu), mm->context.id);
-- 
1.7.4.1



From broonie at opensource.wolfsonmicro.com  Wed Aug 15 12:54:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 15 Aug 2012 17:54:32 +0100
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
Message-ID: <20120815165431.GF15365@opensource.wolfsonmicro.com>

On Wed, Aug 15, 2012 at 04:47:02PM +0000, AnilKumar, Chimata wrote:
> On Wed, Aug 15, 2012 at 18:23:39, Mark Brown wrote:

> > If you have all these unrelated supplies in the system then your device
> > tree should accurately reflect that.  However this would be a very

> In that case I have to add all these fixed regulators.

Why?  You then immediately go on to say...

> > unusual hardware design.  Usually there would be a very small set of
> > system supply rails, frequently only one.

> In case of AM335X-EVM one dedicated supply (5v) feeding to all the input
> supplies (vcc1-7 and vccio) of the regulators.

...that they all map onto the same physical supply?


From swarren at wwwdotorg.org  Wed Aug 15 12:58:45 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 10:58:45 -0600
Subject: [PATCH] ARM: dt: tegra: whistler: add regulators
In-Reply-To: <1344017484-29395-1-git-send-email-swarren@wwwdotorg.org>
References: <1344017484-29395-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <502BD545.1010300@wwwdotorg.org>

On 08/03/2012 12:11 PM, Stephen Warren wrote:
> Whistler uses a Maxim 8907 regulator. Instantiate this.
> 
> The voltage settings were derived from the schematic. The only exception
> is the BBAT voltage; the schematic says 1.2v, but the HW can't go that
> low, so use the HW default of 2.4v instead.
> 
> Almost all regulators list all driven supply signal names in their
> regulator-names property. The exception is nvvdd_sv3, which is in turn
> named 12 more different names on the schematic, so these were omitted
> for brevity.

Applied to Tegra's for-3.7/dt branch.



From wade_farnsworth at mentor.com  Wed Aug 15 12:58:44 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Wed, 15 Aug 2012 09:58:44 -0700
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <20120815162157.GJ29448@mudshark.cambridge.arm.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
Message-ID: <502BD544.70903@mentor.com>

Will Deacon wrote:
> Hi Wade,
>
> On Wed, Aug 15, 2012 at 04:14:20PM +0100, Wade Farnsworth wrote:
>> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
>> index 3e0fc5f..4e82fc1 100644
>> --- a/arch/arm/kernel/ptrace.c
>> +++ b/arch/arm/kernel/ptrace.c
>> @@ -30,6 +30,9 @@
>>   #include<asm/pgtable.h>
>>   #include<asm/traps.h>
>>
>> +#define CREATE_TRACE_POINTS
>> +#include<trace/events/syscalls.h>
>> +
>>   #define REG_PC	15
>>   #define REG_PSR	16
>>   /*
>> @@ -918,7 +921,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>>   {
>>   	unsigned long ip;
>>
>> -	if (!test_thread_flag(TIF_SYSCALL_TRACE))
>> +	if (!test_thread_flag(TIF_SYSCALL_TRACE)&&
>> +	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
>>   		return scno;
>
> Can we now remove this hunk?
>
>>   	current_thread_info()->syscall = scno;
>> @@ -930,10 +934,12 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>>   	ip = regs->ARM_ip;
>>   	regs->ARM_ip = dir;
>>
>> -	if (dir == PTRACE_SYSCALL_EXIT)
>> -		tracehook_report_syscall_exit(regs, 0);
>> -	else if (tracehook_report_syscall_entry(regs))
>> -		current_thread_info()->syscall = -1;
>> +	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
>> +		if (dir == PTRACE_SYSCALL_EXIT)
>> +			tracehook_report_syscall_exit(regs, 0);
>> +		else if (tracehook_report_syscall_entry(regs))
>> +			current_thread_info()->syscall = -1;
>> +	}
>
> and also this one?
>

We need to set current_thread_info()->syscall, since it's used in the 
call to syscall_get_nr() in perf_syscall_{enter,exit}.

What about moving the setting of ->syscall to 
syscall_trace_{enter,exit}?  That would preserve ptrace_syscall_trace() 
for the TIF_SYSCALL_TRACE case only, but ensure that the field is set 
the TRACEPOINT case as well.  Thoughts?

Thanks for the feedback!

Wade



From marc.zyngier at arm.com  Wed Aug 15 13:05:55 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 15 Aug 2012 18:05:55 +0100
Subject: [PATCH 0/3] New algorithm for ASID allocation and rollover
In-Reply-To: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
Message-ID: <502BD6F3.9080909@arm.com>

On 15/08/12 17:53, Will Deacon wrote:
> Hello,
> 
> Following some investigation into preempt-rt Linux, it became apparent
> that ASID rollover can happen fairly regularly under certain heavy
> scheduling workloads. Each time this happens, we broadcast an interrupt
> to the secondary CPUs so that we can reset the global ASID numberspace
> without assigning duplicate ASIDs to different tasks or accidentally
> assigning different ASIDs to threads of the same process.
> 
> This leads to a large number of expensive IPIs between cores:
> 
>            CPU0       CPU1
> IPI0:          0          0  Timer broadcast interrupts
> IPI1:      23165     115888  Rescheduling interrupts
> IPI2:          0          0  Function call interrupts
> IPI3:       6619       1123  Single function call interrupts <---- IPIs
> IPI4:          0          0  CPU stop interrupts
> 
> Digging deeper, this also leads to an extremely varied waittime on the
> cpu_asid_lock. Granted this is only contended for <1% of the time, but
> the waittime varies between 0.5 and 734 us!
> 
> After some discussion, it became apparent that tracking the ASIDs
> currently active on the cores in the system means that, on rollover, we
> can automatically reserve those that are in use without having to stop
> the world.
> 
> This patch series develops that idea so that:
> 
>   - We can support cores without hardware broadcasting of TLB maintenance
>     operations without resorting to IPIs.

This particular bit should benefit even more to virtual machines, as it
avoids trapping back to the host to handle a write to the (emulated) GIC
distributor, and the corresponding interrupt injection on the target vcpus.

I'll give it a spin on KVM.

	M.
-- 
Jazz is not dead. It just smells funny...



From santosh.shilimkar at ti.com  Wed Aug 15 13:05:33 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 15 Aug 2012 22:35:33 +0530
Subject: [PATCH v5 0/8] ARM: OMAP2+: PM: introduce the power domains
 functional states
In-Reply-To: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
Message-ID: <CAMQu2gxznhsbK3--nyQmYdHqyGjwpCSa3CJx8aYpF4wwR1qBSg@mail.gmail.com>

Jean,

On Wed, Aug 15, 2012 at 3:32 PM, Jean Pihet <jean.pihet at newoldbits.com> wrote:
>
> Here is a re-spin after some comments and suggestions after review.
>
> Implement the functional states for the power domains:
> - unify the API to use the functional states. pwrdm_set_next_fpwrst
>   now is the function to control the power domains power and logic
>   states,
> - reorganize the powerdomain API in internal and external parts,
>   in powerdomain.h [1]
> - protect the power domain state change by a lock in
>   pwrdm_set_next_fpwrst,
> - introduce the functional states for power domains power states and
>   logic power states, and the conversion functions between the
>   functional and internal states,
> - program the logic power state of power domains from the functional
>   states, in pwrdm_set_next_fpwrst
> - convert the OMAP2/3/4 PM code to use the updated API,
> - provide the power domains statistics by functional states,
> - provide ftrace tracepoints with the functional state,
> - provide error logs in critical code, which makes the development
>   easier.
>
> Note: [1] the physical split of internal and external APIs into
>       different header files is not part of this series, it comes as
>       a separate patch set.
>
>
> Based on mainline kernel 3.6.0-rc1.
>
> Tested on OMAP3 Beagleboard, with suspend and cpuidle in RET and
> OFF modes.
>
I didn't find any mention here about why are we going in this path and not
in the direction proposed in another RFC [1]
I have already given my comments[2] against the introduction of another PD
layer which can be avoided easily as demonstrated by the RFC[1]. The comments
are still applicable for this series too.

We really need to reduce OMAP specific framework overhead and
move towards more generic PM frameworks. For me, this series is
a step back-ward from that direction. Am really sorry for being critical
again but I remain unconvinced about this series and the problem it
is trying to solve.

May be you have valid reasons not to follow the approach in [1] and in
that case, it will be good to clarify that so that some of us get
to know your rationale.

Regards
Santosh
[1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg71732.html
[2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg69081.html


From olof at lixom.net  Wed Aug 15 13:06:13 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 15 Aug 2012 10:06:13 -0700
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <201208151320.02313.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <201208151320.02313.arnd@arndb.de>
Message-ID: <20120815170613.GA2892@quad.lixom.net>

On Wed, Aug 15, 2012 at 01:20:02PM +0000, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +The AArch64 exception model is made up of a number of exception levels
> > +(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
> > +counterpart.  EL2 is the hypervisor level and exists only in non-secure
> > +mode. EL3 is the highest priority level and exists only in secure mode.
> 
> I'm always confused by a description like this. It sounds like you cannot
> have a hypervisor if you have code running in secure mode in EL3. What
> I instead understand is that you enter non-secure mode by going from
> EL3 into EL2.
> 
> > +2. Setup the device tree
> > +-------------------------
> > +
> > +Requirement: MANDATORY
> > +
> > +The device tree blob (dtb) must be no bigger than 2 megabytes in size
> > +and placed at a 2-megabyte boundary within the first 512 megabytes from
> > +the start of the kernel image. This is to allow the kernel to map the
> > +blob using a single section mapping in the initial page tables.
> 
> I've seen people put firmware for some peripherals into the device tree,
> so that a device driver can grab a blob from there and load it into the
> device, rather than calling request_firmware() which would fail if the
> OS running on the system does not contain the blob. If such firmware is
> too large, you end up violating the 2 MB limit you impose here.
> 
> Should we keep that limit and declare those use cases as invalid, or
> should we try to make the boot protocol more flexible?
> 
> > diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h
> > new file mode 100644
> > index 0000000..d766493
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/setup.h
> > @@ -0,0 +1,26 @@
> > +#ifndef __ASM_SETUP_H
> > +#define __ASM_SETUP_H
> > +
> > +#include <linux/types.h>
> > +
> > +#define COMMAND_LINE_SIZE 1024
> > +
> > +#endif
> 
> Is this necessary? The asm-generic version of this file allows 512 bytes,
> which seems plenty.

Chrome OS on my system today uses a 553 character cmdline, in particular
because some of the device mapper arguments are in there (since we boot without
ramdisk). It adds up quickly.

I suggest keeping it common with x86 since those limits are what people
will be used to (2048).


-Olof


From bhelgaas at google.com  Wed Aug 15 13:06:27 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 15 Aug 2012 10:06:27 -0700
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <CAErSpo7v+i8i=mXCs7ZW8DtGTDN_4AEntwYLqGG8FcCzweySFg@mail.gmail.com>

On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> When using deferred driver probing, PCI host controller drivers may
> actually require this function after the init stage.
>
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v3:
> - none
>
> Changes in v2:
> - use __devinit annotations

Your original patch removed __init completely.  Here you change it to
__devinit.  That means we decide whether to discard the function based
on whether CONFIG_HOTPLUG is supported.  But I think your point is not
about hotplug; it's merely that we should be able to scan a PCI bus
after init-time.  We ought to be able to do a late PCI scan even if
hotplug is not supported.

Therefore, I'd be inclined to remove __init completely unless you have
another reason for preferring __devinit.

>  drivers/pci/setup-irq.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
> index eb219a1..f0bcd56 100644
> --- a/drivers/pci/setup-irq.c
> +++ b/drivers/pci/setup-irq.c
> @@ -18,7 +18,7 @@
>  #include <linux/cache.h>
>
>
> -static void __init
> +static void __devinit
>  pdev_fixup_irq(struct pci_dev *dev,
>                u8 (*swizzle)(struct pci_dev *, u8 *),
>                int (*map_irq)(const struct pci_dev *, u8, u8))
> @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev,
>         pcibios_update_irq(dev, irq);
>  }
>
> -void __init
> +void __devinit
>  pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
>                int (*map_irq)(const struct pci_dev *, u8, u8))
>  {
> --
> 1.7.11.2
>


From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:29 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:29 +0200
Subject: [PATCH v3 0/6] ARM: dove: DT support for Marvell Dove
In-Reply-To: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds DT support for Marvell Dove SoC and three boards
equipped with this SoC. The work is based on device tree support for
Marvell Orion based SoCs introduced in 3.6-rc1.

The first three patches move mach-dove closer to Marvell Kirkwood's
setup code by unifying the clock setup routines, adding clock gating
control, and support for Marvell's crypto engine to mach-dove.

Patches 4 and 5 add a generic DT machine descriptor to mach-dove and
corresponding DT descriptors for the SoC and already supported boards.

Finally, the last patch adds a DT descriptor for the SolidRun CuBox,
a plug computer based on Marvell Dove.

This patch set relies on a DT support patch for sdhci-dove that has
been accepted on mmc-next for 3.7 as commit
b2293055c1e1200acbb46523976852d1686fdfa4.

Changes:
v2: removed clk_prepare_enable for tclk and updated subsequent patches
v3: fixed a typo in clk_gate name for pex0
    removed device name macros from clk gate names

Sebastian Hesselbarth (6):
  ARM: dove: unify clock setup
  ARM: dove: add clock gating control
  ARM: dove: add crypto engine
  ARM: dove: add device tree based machine descriptor
  ARM: dove: add device tree descriptors
  ARM: dove: SolidRun CuBox DT

 arch/arm/boot/dts/dove-cm-a510.dts   |   38 +++++++++
 arch/arm/boot/dts/dove-cubox.dts     |   42 +++++++++
 arch/arm/boot/dts/dove-dove-db.dts   |   38 +++++++++
 arch/arm/boot/dts/dove.dtsi          |  143 +++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Kconfig           |    7 ++
 arch/arm/mach-dove/Makefile.boot     |    4 +
 arch/arm/mach-dove/common.c          |  156 +++++++++++++++++++++++++++++++---
 arch/arm/mach-dove/include/mach/pm.h |   54 ++++++++----
 8 files changed, 452 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>

-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:30 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:30 +0200
Subject: [PATCH v3 1/6] ARM: dove: unify clock setup
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch synchronizes the clock setup of dove with other orion-based
platforms.

In dove_find_tclk there was a note about DOVE_SAMPLE_HI/LO register to
detect tclk. While it might be possible to set a different tclk frequency
with reset strapping the Dove datasheets don't tell anything about tclk
frequency here. Therefore, I removed that comment.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c |   19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

v2: remove useless clk_prepare_enable for fixed rate tclk

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 4db5de5..b6f092c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -33,8 +33,6 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -70,12 +68,13 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static void __init dove_clk_init(void)
 {
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-				       get_tclk());
+				       dove_tclk);
 
 	orion_clkdev_init(tclk);
 }
@@ -187,16 +186,16 @@ void __init dove_init_early(void)
 	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
 	return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+	dove_tclk = dove_find_tclk();
 	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-			IRQ_DOVE_BRIDGE, get_tclk());
+			IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -284,8 +283,8 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-	printk(KERN_INFO "Dove 88AP510 SoC, ");
-	printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
 	tauros2_init();
@@ -293,7 +292,7 @@ void __init dove_init(void)
 	dove_setup_cpu_mbus();
 
 	/* Setup root of clk tree */
-	clk_init();
+	dove_clk_init();
 
 	/* internal devices that every board has */
 	dove_rtc_init();
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:32 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:32 +0200
Subject: [PATCH v3 3/6] ARM: dove: add crypto engine
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-4-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a dove specific setup function for the Marvell CESA
crypto engine available on orion based SoCs. Dove setup was just
missing a function to call orion_crypto_init with dove specific
setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 9b2f961..66689ce 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -258,6 +258,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+	orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+			  DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:33 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:33 +0200
Subject: [PATCH v3 4/6] ARM: dove: add device tree based machine descriptor
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-5-git-send-email-sebastian.hesselbarth@gmail.com>

This adds a generic DT_MACHINE for mach-dove. As with other orion based
SoCs there still is some glue code required to make all internal devices
work, i.e. auxdata is provided to pass clocks to corresponding device
drivers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/Kconfig  |    7 +++++
 arch/arm/mach-dove/common.c |   67 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+)

diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c5..00154e7 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
 	  Say 'Y' here if you want your kernel to support the
 	  CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+	bool "Marvell Dove Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 66689ce..810ea15 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,8 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -29,6 +31,7 @@
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
+#include <plat/irq.h>
 #include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -379,3 +382,67 @@ void dove_restart(char mode, const char *cmd)
 	while (1)
 		;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+	OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+	OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+	OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+		       NULL),
+	OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+	OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+	{},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+	.phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+		(dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+	tauros2_init();
+#endif
+	dove_setup_cpu_mbus();
+
+	/* Setup root of clk tree */
+	dove_clk_init();
+
+	/* Internal devices not ported to DT yet */
+	dove_rtc_init();
+	dove_xor0_init();
+	dove_xor1_init();
+
+	dove_ge00_init(&dove_dt_ge00_data);
+	dove_ehci0_init();
+	dove_ehci1_init();
+	dove_pcie_init(1, 1);
+	dove_crypto_init();
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+	"marvell,dove",
+	NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+	.map_io		= dove_map_io,
+	.init_early	= dove_init_early,
+	.init_irq	= orion_dt_init_irq,
+	.timer		= &dove_timer,
+	.init_machine	= dove_dt_init,
+	.restart	= dove_restart,
+	.dt_compat	= dove_dt_board_compat,
+MACHINE_END
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:34 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:34 +0200
Subject: [PATCH v3 5/6] ARM: dove: add device tree descriptors
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-6-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds device tree decriptors for dove SoC and currently
supported boards.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cm-a510.dts |   38 ++++++++++
 arch/arm/boot/dts/dove-dove-db.dts |   38 ++++++++++
 arch/arm/boot/dts/dove.dtsi        |  143 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot   |    3 +
 4 files changed, 222 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts
 create mode 100644 arch/arm/boot/dts/dove-dove-db.dts
 create mode 100644 arch/arm/boot/dts/dove.dtsi

diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 0000000..61a8062
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Compulab CM-A510";
+	compatible = "compulab,cm-a510", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 0000000..e5a920b
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "Marvell DB-MV88AP510-BP Development Board";
+	compatible = "marvell,dove-db", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash ST-M25P32-VMF6P */
+	spi-flash at 0 {
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	  status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 0000000..96fb824
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "marvell,dove";
+	model = "Marvell Armada 88AP510 SoC";
+
+	interrupt-parent = <&intc>;
+
+	intc: interrupt-controller {
+		compatible = "marvell,orion-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xf1020204 0x04>,
+		      <0xf1020214 0x04>;
+	};
+
+	mbus at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0 0xf1000000 0x4000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <7>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart1: serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <8>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart2: serial at 12200 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <9>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		uart3: serial at 12300 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <10>;
+			clock-frequency = <166666667>;
+			status = "disabled";
+		};
+
+		wdt: wdt at 20300 {
+			compatible = "marvell,orion-wdt";
+			reg = <0x20300 0x28>;
+		};
+
+		gpio0: gpio at d0400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0400 0x20>;
+			ngpio = <32>;
+			interrupts = <12>, <13>, <14>, <60>;
+		};
+
+		gpio1: gpio at d0420 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xd0420 0x20>;
+			ngpio = <32>;
+			interrupts = <61>;
+		};
+
+		gpio2: gpio at e8400 {
+			compatible = "marvell,orion-gpio";
+			#gpio-cells = <2>;
+			gpio-controller;
+			reg = <0xe8400 0x0c>;
+			ngpio = <8>;
+		};
+
+		spi0: spi at 10600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			interrupts = <6>;
+			reg = <0x10600 0x28>;
+			status = "disabled";
+		};
+
+		spi1: spi at 14600 {
+			compatible = "marvell,orion-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			interrupts = <5>;
+			reg = <0x14600 0x28>;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 11000 {
+			compatible = "marvell,mv64xxx-i2c";
+			reg = <0x11000 0x20>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11>;
+			clock-frequency = <400000>;
+			timeout-ms = <1000>;
+			status = "disabled";
+		};
+
+		sdio0: sdio at 92000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x92000 0x100>;
+			interrupts = <35>, <37>;
+			status = "disabled";
+		};
+
+		sdio1: sdio at 90000 {
+			compatible = "marvell,dove-sdhci";
+			reg = <0x90000 0x100>;
+			interrupts = <36>, <38>;
+			status = "disabled";
+		};
+
+		sata0: sata at a0000 {
+			compatible = "marvell,orion-sata";
+			reg = <0xa0000 0x2400>;
+			interrupts = <62>;
+			nr-ports = <1>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 760a0ef..94ab6b3 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -1,3 +1,6 @@
    zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:35 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:35 +0200
Subject: [PATCH v3 6/6] ARM: dove: SolidRun CuBox DT
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-7-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds basic support for the SolidRun CuBox to DT based
mach-dove. There are still some issues related to ongoing orion/mvebu
development, e.g. gpio-led will not work as there is no DT pinctrl
for dove yet and we don't have board specific setup code. Nevertheless,
the DT description is already introduced here.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/dove-cubox.dts |   42 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-dove/Makefile.boot |    1 +
 2 files changed, 43 insertions(+)
 create mode 100644 arch/arm/boot/dts/dove-cubox.dts

diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 0000000..0adbd5a
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+	model = "SolidRun CuBox";
+	compatible = "solidrun,cubox", "marvell,dove";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		power {
+			label = "Power";
+			gpios = <&gpio0 18 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+	status = "okay";
+
+	/* spi0.0: 4M Flash Winbond W25Q32BV */
+	spi-flash at 0 {
+		compatible = "st,w25q32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 94ab6b3..cfac9c5 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-dove-db.dtb
 dtb-$(CONFIG_MACH_DOVE_DT) += dove-cm-a510.dtb
+dtb-$(CONFIG_MACH_DOVE_DT) += dove-cubox.dtb
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 15 13:07:31 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 15 Aug 2012 19:07:31 +0200
Subject: [PATCH v3 2/6] ARM: dove: add clock gating control
In-Reply-To: <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344681326-17946-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345050455-32643-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345050455-32643-3-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds clock gates from the clock gating control register
available on dove. All clock gates are hooked up to tclk, except for
gigabit ethernet controller (ge) which is a child of gephy to allow
both enabled/disabled at the same time.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: Rabeeh Khoury <rabeeh at solid-run.com>
Cc: Ian Molton <ian.molton at codethink.co.uk>
Cc: Maen Suleiman <maen at marvell.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-dove/common.c          |   57 +++++++++++++++++++++++++++++++++-
 arch/arm/mach-dove/include/mach/pm.h |   54 +++++++++++++++++++++-----------
 2 files changed, 92 insertions(+), 19 deletions(-)

v2: adapted to removed clk_prepare_enable from patch 1
v3: fixed a typo in clk_gate name for pex0
    removed device name macros from clk gate names

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index b6f092c..9b2f961 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -24,6 +24,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -69,14 +70,68 @@ void __init dove_map_io(void)
  * CLK tree
  ****************************************************************************/
 static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
+static struct clk __init *dove_register_gate(const char *name,
+					     const char *parent, u8 bit_idx)
+{
+	return clk_register_gate(NULL, name, parent, 0,
+				 (void __iomem *)CLOCK_GATING_CONTROL,
+				 bit_idx, 0, &gating_lock);
+}
+
 static void __init dove_clk_init(void)
 {
+	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+	struct clk *xor0, *xor1, *ge, *gephy;
+
 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 				       dove_tclk);
 
-	orion_clkdev_init(tclk);
+	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+	orion_clkdev_add(NULL, "orion_spi.0", tclk);
+	orion_clkdev_add(NULL, "orion_spi.1", tclk);
+	orion_clkdev_add(NULL, "orion_wdt", tclk);
+	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+
+	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+	orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+	orion_clkdev_add("0", "sata_mv.0", sata);
+	orion_clkdev_add("0", "pcie", pex0);
+	orion_clkdev_add("1", "pcie", pex1);
+	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+	orion_clkdev_add(NULL, "orion_nand", nand);
+	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+	orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+	orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+	orion_clkdev_add(NULL, "mv_crypto", crypto);
+	orion_clkdev_add(NULL, "dove-ac97", ac97);
+	orion_clkdev_add(NULL, "dove-pdma", pdma);
+	orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+	orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f94..7bcd0df 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL	(DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK		(1 << 0)
-#define  CLOCK_GATING_USB1_MASK		(1 << 1)
-#define  CLOCK_GATING_GBE_MASK		(1 << 2)
-#define  CLOCK_GATING_SATA_MASK		(1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK	(1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK	(1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK	(1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK	(1 << 9)
-#define  CLOCK_GATING_NAND_MASK		(1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK	(1 << 11)
-#define  CLOCK_GATING_I2S0_MASK		(1 << 12)
-#define  CLOCK_GATING_I2S1_MASK		(1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK	(1 << 15)
-#define  CLOCK_GATING_AC97_MASK		(1 << 21)
-#define  CLOCK_GATING_PDMA_MASK		(1 << 22)
-#define  CLOCK_GATING_XOR0_MASK		(1 << 23)
-#define  CLOCK_GATING_XOR1_MASK		(1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << 30)
+#define  CLOCK_GATING_BIT_USB0		0
+#define  CLOCK_GATING_BIT_USB1		1
+#define  CLOCK_GATING_BIT_GBE		2
+#define  CLOCK_GATING_BIT_SATA		3
+#define  CLOCK_GATING_BIT_PCIE0		4
+#define  CLOCK_GATING_BIT_PCIE1		5
+#define  CLOCK_GATING_BIT_SDIO0		8
+#define  CLOCK_GATING_BIT_SDIO1		9
+#define  CLOCK_GATING_BIT_NAND		10
+#define  CLOCK_GATING_BIT_CAMERA	11
+#define  CLOCK_GATING_BIT_I2S0		12
+#define  CLOCK_GATING_BIT_I2S1		13
+#define  CLOCK_GATING_BIT_CRYPTO	15
+#define  CLOCK_GATING_BIT_AC97		21
+#define  CLOCK_GATING_BIT_PDMA		22
+#define  CLOCK_GATING_BIT_XOR0		23
+#define  CLOCK_GATING_BIT_XOR1		24
+#define  CLOCK_GATING_BIT_GIGA_PHY	30
+#define  CLOCK_GATING_USB0_MASK		(1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK		(1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK		(1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK		(1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK	(1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK	(1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK	(1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK	(1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK		(1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK	(1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK		(1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK		(1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK	(1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK		(1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK		(1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK		(1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK		(1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK	(1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE	(DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK	(DOVE_PMU_VIRT_BASE + 0x54)
-- 
1.7.10.4



From will.deacon at arm.com  Wed Aug 15 13:27:31 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 15 Aug 2012 18:27:31 +0100
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <502BD544.70903@mentor.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
 <502BD544.70903@mentor.com>
Message-ID: <20120815172731.GL29448@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 05:58:44PM +0100, Wade Farnsworth wrote:
> We need to set current_thread_info()->syscall, since it's used in the 
> call to syscall_get_nr() in perf_syscall_{enter,exit}.

Damn. I think that also means we have a bug, given that the SYSCALL_TRACE
code can set this to -1, which gets used as an index into a bitmap by the
looks of it. Considering that we have to pass the syscall number to
trace_sys_enter anyway, it also seems broken.

> What about moving the setting of ->syscall to 
> syscall_trace_{enter,exit}?  That would preserve ptrace_syscall_trace() 
> for the TIF_SYSCALL_TRACE case only, but ensure that the field is set 
> the TRACEPOINT case as well.  Thoughts?

I'd be tempted to set the thing unconditionally before checking the thread
flag at the top of ptrace_syscall_trace. This hangs off the slowpath anyway
and it makes everything a lot more readable.

Will


From catalin.marinas at arm.com  Wed Aug 15 13:37:11 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 15 Aug 2012 18:37:11 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120814230645.GA19607@quad.lixom.net>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <20120814230645.GA19607@quad.lixom.net>
Message-ID: <20120815173711.GC14264@arm.com>

Hi Olof,

On Wed, Aug 15, 2012 at 12:06:45AM +0100, Olof Johansson wrote:
> On Tue, Aug 14, 2012 at 06:52:03PM +0100, Catalin Marinas wrote:
> > +Before jumping into the kernel, the following conditions must be met:
> > +
> > +- Quiesce all DMA capable devices so that memory does not get
> > +  corrupted by bogus network packets or disk data.  This will save
> > +  you many hours of debug.
> > +
> > +- Primary CPU general-purpose register settings
> > +  x0 = physical address of device tree blob (dtb) in system RAM.
> > +
> > +- CPU mode
> > +  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> > +  IRQ and FIQ).
> > +  The CPU must be in either EL2 (RECOMMENDED in order to have access to
> > +  the virtualisation extensions) or non-secure EL1.
> > +
> > +- Caches, MMUs
> > +  The MMU must be off.
> > +  Instruction cache may be on or off.
> > +  Data cache must be off and invalidated.
> > +
> > +- Architected timers
> > +  CNTFRQ must be programmed with the timer frequency.
> > +  If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
> > +  set where available.
> > +
> > +- Coherency
> > +  All CPUs to be booted by the kernel must be part of the same coherency
> > +  domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
> > +  initialisation to enable the receiving of maintenance operations on
> > +  each CPU.
> > +
> > +- System registers
> > +  All writable architected system registers at the exception level where
> > +  the kernel image will be entered must be initialised by software at a
> > +  higher exception level to prevent execution in an UNKNOWN state.
> 
> Given the recent development of ARM platforms, you might want to mandate
> the state of IOMMUs as well (they should probably be off, since there
> should be no active DMA activity). Graphics would be the exception to
> this, since if you want to keep scanning out a splash screen, you'll
> have to keep doing DMA...

We'll enhance this document as we get hardware as it's not clear whether
we can simply mandate it to be off. We may have situations with some
simple IOMMU that is previously set up by the firmware and the kernel
doesn't get access to it. One example is the System MMU from ARM that
supports stage 2 (hypervisor) translations and you just run a guest
kernel without any control of the IOMMU.

> > +- The primary CPU must jump directly to the first instruction of the
> > +  kernel image.  The device tree blob passed by this CPU must contain
> > +  for each CPU node:
> > +
> > +    1. An 'enable-method' property. Currently, the only supported value
> > +       for this field is the string "spin-table".
> > +
> > +    2. A 'cpu-release-addr' property identifying a 64-bit,
> > +       zero-initialised memory location.
> 
> These would be good to have documented in the
> Documentation/devicetree/bindings hierarchy as well.

OK.

> > index 0000000..d766493
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/setup.h
> > @@ -0,0 +1,26 @@
> > +/*
> > + * Based on arch/arm/include/asm/setup.h
> > + *
> > + * Copyright (C) 1997-1999 Russell King
> > + * Copyright (C) 2012 ARM Ltd.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +#ifndef __ASM_SETUP_H
> > +#define __ASM_SETUP_H
> > +
> > +#include <linux/types.h>
> > +
> > +#define COMMAND_LINE_SIZE 1024
> 
> Probably not a huge deal, and other architectures seem to be all over
> the map on this, but you might want to go with a larger value now rather
> than later. 2048 or 4096 perhaps?

It looks like there are many different values, including the asm-generic
one which is 512. I'm happy to follow the x86 example and change it to
2048, it doesn't really matter.

> > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> > new file mode 100644
> > index 0000000..34ccdc0
> > --- /dev/null
> > +++ b/arch/arm64/kernel/head.S
> 
> [...]
> 
> > +/*
> > + * Setup common bits before finally enabling the MMU. Essentially this is just
> > + * loading the page table pointer and vector base registers.
> > + *
> > + * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
> > + * the MMU.
> > + */
> > +__enable_mmu:
> 
> ENTRY()?

__enable_mmu is not used outside this file, so no need for ENTRY().

> > +	ldr	x5, =vectors
> > +	msr	vbar_el1, x5
> > +	msr	ttbr0_el1, x25			// load TTBR0
> > +	msr	ttbr1_el1, x26			// load TTBR1
> > +	isb
> > +	b	__turn_mmu_on
> > +ENDPROC(__enable_mmu)
> 
> ...or just END()? Same for a few of the other functions below.

ENDPROC() gives us ".type @function" in addition to END(). This proved
to be useful in the past for debugging symbols, unwind table (though we
don't have the latter on AArch64).

> > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
> > new file mode 100644
> > index 0000000..f25186f
> > --- /dev/null
> > +++ b/arch/arm64/kernel/setup.c
> 
> [...]
> 
> > +static void __init setup_processor(void)
> > +{
> > +	struct proc_info_list *list;
> > +
> > +	/*
> > +	 * locate processor in the list of supported processor
> > +	 * types.  The linker builds this table for us from the
> > +	 * entries in arch/arm/mm/proc.S
> > +	 */
> 
> Probably from arch/arm64/... somewhere?

Yes, I did a grep and found a few more.

> > +	printk("CPU: %s [%08x] revision %d\n",
> > +	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
> > +
> > +	sprintf(init_utsname()->machine, "aarch64");
> 
> > +	initial_boot_params = devtree;
> > +	dt_root = of_get_flat_dt_root();
> > +
> > +	machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
> > +	if (!machine_name)
> > +		machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
> > +	if (!machine_name)
> > +		machine_name = "<unknown>";
> > +	pr_info("Machine: %s\n", machine_name);
> 
> This property is an array of strings. It would be more valuable to print out
> the entry that was matched for a platform instead of the provided one from the
> device tree.

If we add machine_desc structure back, we could print which machine was
matched. But so far I try to keep the SoC code to a minimum and just do
the probing later in the SoC code (of_find_matching_node). Ideally we
shouldn't have any SoC code and just keep code in drivers but we'll see
how far we can get. We can discuss more details at the KS as I would
like the arm-soc team to get involved here.

Thanks.

-- 
Catalin


From alanbutty12 at gmail.com  Wed Aug 15 14:00:42 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Wed, 15 Aug 2012 19:00:42 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815135427.GF22226@titan.lakedaemon.net>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
Message-ID: <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>

On 15 August 2012 14:54, Jason Cooper <jason at lakedaemon.net> wrote:
> On Wed, Aug 15, 2012 at 01:43:24PM +0100, alan butler wrote:
>> On 15 August 2012 13:11, Jason Cooper <jason at lakedaemon.net> wrote:
>> > On Wed, Aug 15, 2012 at 07:55:42AM -0400, Josh Coombs wrote:
>> > > >> Sorry i meant board-dt in the previous message and the name just
>> > > >> getting used to the mail program on os x aswel. I have run through the
>> > > >> checkpatch.pl script and it tells me there are no errors but i just
>> > > >> found out a few minutes ago theres a fix for the 2 sata ports not
>> > > >> working (on all kirkwood devices as far as i know) so i am going to
>> > > >> test that now as it envolves modifying a line in the dts file.
>> > > >
>> > > > Ok.  Please let everyone know in the comment portion of the patch (after
>> > > > the --- line) that your patch depends on this fix.  I haven't seen the
>> > > > patch you're referring to yet.  I'll keep my eye out for it.
>> > >
>> > > What he's referring to is needing to up the coherent_pool size to get
>> > > a Kirkwood device with two SATA ports to init completely.  I brought
>> > > the topic up on arm-kernel under the subject 'Potential Regression in
>> > > 3.6-rc1 - Kirkwood SATA' and Aaro Koskinen suggested the root cause
>> > > and potential fix of adding coherent_pool=1M to the bootargs.  I
>> > > didn't think to cc you in the discussion, sorry about that.  So there
>> > > isn't a pending patch yet, just a suggestion of altered bootargs.
>> >
>> > Yes, I saw that discussion.  Setting coherent_pool=1M was a way of
>> > diagnosing the problem.  It allowed the system to boot, which tells us
>> > where the problem lies.  But it did not fix the problem in the code.
>> > *That's* the patch I was referring to.  Which I haven't seen, yet. ;-)
>>
>> I could not get the way to use git figured out so i will send the
>> patch here though the browser based gmail interface and hope i do not
>> cause or get in too much trouble.
>
> It's doing some linewrapping, but it's fine for review.  When you
> resubmit for inclusion, you'll need to get that fixed up.
>
>> And my patch contains that part of
>> the altered bootargs so i hope that wont cause a problem either.
>
> Not a problem for review and testing, but I'm going to hold off on
> pulling it until we have the core problem fixed.
>
>> diff -urN linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> --- linuxorig//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> 1970-01-01 01:00:00.000000000 +0100
>> +++ linux//arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts    2012-08-15
>> 10:17:35.000000000 +0100
>> @@ -0,0 +1,77 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +    model = "Iomega StorCenter ix2-200";
>> +    compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>> +
>> +    memory {
>> +        device_type = "memory";
>> +        reg = <0x00000000 0x10000000>;
>> +    };
>> +
>> +    chosen {
>> +        bootargs = "console=ttyS0,115200n8 earlyprintk
>> root=LABEL=ROOTFS coherent_pool=1M";
>
> watch the linewrap.  Also, please remove the root= declaration and the
> coherent_pool=.  Once we get that fixed, your patch won't need it.
>
>> +    };
>> +
>> +    ocp at f1000000 {
>> +        i2c at 11000 {
>> +            status = "okay";
>> +
>> +            lm63: lm63 at 4c {
>> +                compatible = "national,lm63";
>> +                reg = <0x4c>;
>> +            };
>> +        };
>> +
>> +        serial at 12000 {
>> +            clock-frequency = <200000000>;
>> +            status = "ok";
>> +        };
>> +
>> +        nand at 3000000 {
>> +            status = "okay";
>> +
>> +            partition at 100000 {
>> +                label = "uImage";
>> +                reg = <0x100000 0x300000>;
>> +                read-only;
>> +            };
>> +
>> +            partition at 400000 {
>> +                label = "uInitrd";
>> +                reg = <0x540000 0x1000000>;
>> +            };
>
> is there a partition for u-boot and the u-boot environment?
>
>> +        };
>> +        sata at 80000 {
>> +            compatible = "marvell,orion-sata";
>> +            reg = <0x80000 0x5000>;
>> +            interrupts = <21>;
>> +            status = "okay";
>> +            nr-ports = <2>;
>> +        };
>> +
>> +    };
>> +    gpio-leds {
>> +        compatible = "gpio-leds";
>> +
>> +        power_led {
>> +            label = "status:white:power_led";
>> +            gpios = <&gpio0 16 0>;
>> +            linux,default-trigger = "default-on";
>> +        };
>> +        rebuild_led {
>> +            label = "status:white:rebuild_led";
>> +            gpios = <&gpio1 5 0>;
>> +        };
>> +        health_led {
>> +            label = "status:red:health_led";
>> +            gpios = <&gpio1 6 0>;
>> +        };
>> +        backup_led {
>> +            label = "status:blue:backup_led";
>> +            gpios = <&gpio0 15 0>;
>> +        };
>> +    };
>> +};
>> diff -urN linuxorig//arch/arm/mach-kirkwood/board-dt.c
>> linux//arch/arm/mach-kirkwood/board-dt.c
>> --- linuxorig//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
>> 12:48:11.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/board-dt.c    2012-08-15
>> 13:17:47.000000000 +0100
>> @@ -87,6 +87,9 @@
>>     if (of_machine_is_compatible("buffalo,lsxl"))
>>         lsxl_init();
>>
>> +    if (of_machine_is_compatible("iom,ix2-200"))
>> +        iomega_ix2_200_init();
>> +
>>     of_platform_populate(NULL, kirkwood_dt_match_table,
>>                  kirkwood_auxdata_lookup, NULL);
>>  }
>> @@ -100,6 +103,7 @@
>>     "qnap,ts219",
>>     "seagate,goflexnet",
>>     "buffalo,lsxl",
>> +    "iom,ix2-200",
>
> Please double check that this is a leading tab, and not a collection of
> spaces.  checkpatch.pl should have coughed on this if it was wrong.
> Could also be mail client mangling.
>
>>     NULL
>>  };
>>
>> diff -urN linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> --- linuxorig//arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> 1970-01-01 01:00:00.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/board-iomega_ix2_200.c    2012-08-15
>> 10:16:55.000000000 +0100
>> @@ -0,0 +1,138 @@
>> +/*
>> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> + *
>> + * Iomega StorCenter ix2-200
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/irq.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/ata_platform.h>
>> +#include <linux/mv643xx_eth.h>
>> +#include <linux/ethtool.h>
>> +#include <net/dsa.h>
>> +#include <linux/gpio.h>
>> +#include <linux/leds.h>
>> +#include <linux/gpio_keys.h>
>> +#include <linux/i2c.h>
>> +#include <linux/input.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <mach/kirkwood.h>
>> +#include "common.h"
>> +#include "mpp.h"
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
>> +    .phy_addr       = MV643XX_ETH_PHY_NONE,
>> +    .speed          = SPEED_1000,
>> +    .duplex         = DUPLEX_FULL,
>> +};
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
>> +    .phy_addr    = MV643XX_ETH_PHY_ADDR(11),
>> +};
>> +
>> +/****************************************************************************
>> + * GPIO Attached Keys
>> + ****************************************************************************/
>> +
>> +#define iomega_ix2_200_GPIO_KEY_RESET    12
>> +#define iomega_ix2_200_GPIO_KEY_POWER    14
>> +#define iomega_ix2_200_GPIO_KEY_OTB        35
>> +
>> +#define iomega_ix2_200_SW_RESET    0x00
>> +#define iomega_ix2_200_SW_POWER    0x01
>> +#define iomega_ix2_200_SW_OTB    0x02
>> +
>> +static struct gpio_keys_button iomega_ix2_200_buttons[] = {
>> +    {
>> +        .type        = EV_SW,
>> +        .code       = iomega_ix2_200_SW_RESET,
>> +        .gpio       = iomega_ix2_200_GPIO_KEY_RESET,
>> +        .desc       = "Reset Button",
>> +        .active_low     = 1,
>> +        .debounce_interval = 100,
>> +    },
>> +    {
>> +        .type        = EV_SW,
>> +        .code       = iomega_ix2_200_SW_POWER,
>> +        .gpio       = iomega_ix2_200_GPIO_KEY_POWER,
>> +        .desc       = "Power Button",
>> +        .active_low     = 1,
>> +        .debounce_interval = 100,
>> +    },
>> +    {
>> +        .type        = EV_SW,
>> +        .code       = iomega_ix2_200_SW_OTB,
>> +        .gpio       = iomega_ix2_200_GPIO_KEY_OTB,
>> +        .desc       = "OTB Button",
>> +        .active_low     = 1,
>> +        .debounce_interval = 100,
>> +    },
>> +
>> +};
>> +
>> +static struct gpio_keys_platform_data iomega_ix2_200_button_data = {
>> +    .buttons    = iomega_ix2_200_buttons,
>> +    .nbuttons       = ARRAY_SIZE(iomega_ix2_200_buttons),
>> +};
>> +
>> +static struct platform_device iomega_ix2_200_button_device = {
>> +    .name       = "gpio-keys",
>> +    .id         = -1,
>> +    .num_resources  = 0,
>> +    .dev        = {
>> +        .platform_data  = &iomega_ix2_200_button_data,
>> +    },
>> +};
>> +
>
> All of the above (gpio keys) can be removed and described in the DT.
> Please look at:
>
> da3fd4c ARM: Kirkwood: Describe iconnect keys in DT.
>
> which is currently at:
>
> git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
>
>> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
>> +    MPP12_GPIO,                             /* Reset Button */
>> +    MPP14_GPIO,                             /* Power Button */
>> +    MPP15_GPIO,                             /* Backup LED (blue) */
>> +    MPP16_GPIO,                             /* Power LED (white) */
>> +    MPP35_GPIO,                             /* OTB Button */
>> +    MPP36_GPIO,                             /* Rebuild LED (white) */
>> +    MPP37_GPIO,                             /* Health LED (red) */
>> +    MPP38_GPIO,                             /* SATA LED brightness control 1 */
>> +    MPP39_GPIO,                             /* SATA LED brightness control 2 */
>> +    MPP40_GPIO,                             /* Backup LED brightness
>> control 1 */
>> +    MPP41_GPIO,                             /* Backup LED brightness
>> control 2 */
>> +    MPP42_GPIO,                             /* Power LED brightness
>> control 1 */
>> +    MPP43_GPIO,                             /* Power LED brightness
>> control 2 */
>> +    MPP44_GPIO,                             /* Health LED brightness
>> control 1 */
>> +    MPP45_GPIO,                             /* Health LED brightness
>> control 2 */
>> +    MPP46_GPIO,                             /* Rebuild LED brightness
>> control 1 */
>> +    MPP47_GPIO,                             /* Rebuild LED brightness
>> control 2 */
>> +    0
>> +};
>> +
>> +void __init iomega_ix2_200_init(void)
>> +{
>> +    /*
>> +     * Basic setup. Needs to be called early.
>> +     */
>> +    kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
>> +
>> +    kirkwood_ehci_init();
>> +
>> +    kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
>> +    kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
>
>
>> +    kirkwood_uart0_init();
>> +    platform_device_register(&iomega_ix2_200_button_device);
>
> These two lines can be removed, the second after describing the gpio
> keys in the DT.  Make sure you have CONFIG_SERIAL_OF_PLATFORM=y in your
> config.
>
>> +}
>> +
>> +static int __init iomega_ix2_200_pci_init(void)
>> +{
>> +    if (of_machine_is_compatible("iom,ix2-200"))
>> +        kirkwood_pcie_init(KW_PCIE0);
>> +    return 0;
>> +}
>> +subsys_initcall(iomega_ix2_200_pci_init);
>> +
>> diff -urN linuxorig//arch/arm/mach-kirkwood/common.h
>> linux//arch/arm/mach-kirkwood/common.h
>> --- linuxorig//arch/arm/mach-kirkwood/common.h    2012-08-15
>> 12:48:11.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/common.h    2012-08-15
>> 12:54:07.000000000 +0100
>> @@ -94,6 +94,12 @@
>>  static inline void lsxl_init(void) {};
>>  #endif
>>
>> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
>> +void iomega_ix2_200_init(void);
>> +#else
>> +static inline void iomega_ix2_200_init(void) {};
>> +#endif
>> +
>>  /* early init functions not converted to fdt yet */
>>  char *kirkwood_id(void);
>>  void kirkwood_l2_init(void);
>> diff -urN linuxorig//arch/arm/mach-kirkwood/Kconfig
>> linux//arch/arm/mach-kirkwood/Kconfig
>> --- linuxorig//arch/arm/mach-kirkwood/Kconfig    2012-08-15
>> 12:48:11.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/Kconfig    2012-08-15 12:54:55.000000000 +0100
>> @@ -195,6 +195,13 @@
>>       Say 'Y' here if you want your kernel to support the
>>       HP t5325 Thin Client.
>>
>> +config MACH_IOMEGA_IX2_200_DT
>> +    bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
>> +    select ARCH_KIRKWOOD_DT
>> +    help
>> +      Say 'Y' here if you want your kernel to support the
>> +      Iomega StorCenter ix2-200 (Flattened Device Tree).
>> +
>>  endmenu
>>
>>  endif
>> diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile
>> linux//arch/arm/mach-kirkwood/Makefile
>> --- linuxorig//arch/arm/mach-kirkwood/Makefile    2012-08-15
>> 12:48:11.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/Makefile    2012-08-15
>> 12:55:17.000000000 +0100
>> @@ -28,3 +28,4 @@
>>  obj-$(CONFIG_MACH_TS219_DT)        += board-ts219.o tsx1x-common.o
>>  obj-$(CONFIG_MACH_GOFLEXNET_DT)        += board-goflexnet.o
>>  obj-$(CONFIG_MACH_LSXL_DT)        += board-lsxl.o
>> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
>> diff -urN linuxorig//arch/arm/mach-kirkwood/Makefile.boot
>> linux//arch/arm/mach-kirkwood/Makefile.boot
>> --- linuxorig//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
>> 13:07:03.000000000 +0100
>> +++ linux//arch/arm/mach-kirkwood/Makefile.boot    2012-08-15
>> 12:55:43.000000000 +0100
>> @@ -11,3 +11,4 @@
>>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
>> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
>
> ...
>
>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>
> This will need to go above the --- line, which you don't have in this
> email.
>
> Since you have this patch as a file, do the following:
>
> # after the git checkout command in my previous instructions
>
> patch -Np0 <../my_patch_file
>         # you may need 1 instead here, depends on the patch.
>
> git diff HEAD
>         # review the output, quit out and fix anything that isn't
>         # right. review again with the same command.  Once it looks
>         # correct, proceed
>
> git add .
>
> # you'll probably need to do these two if this is a new repo:
>         git config --add user.name "Alan M Butler"
>         git config --add user.email "alanbutty12 at gmail.com"
>
> git commit -s
>         # The first line should be "ARM: Kirkwood: ...".  This will
>         # become the subject of the email submission
>
> # now, pickup in my original instructions with 'git format-patch'
>
> hth,
>
> Jason.

i did what you sujested and all commands worked except for the git
sendmail part so i do not know if I should still be sending you the
patch this way but here it is. i also defined the gpio keys in the dts
file like you said the same as with the iconnect but the kernel keeps
crashing with them defined in the dts is the support actualy there for
the keys? or have i just defined them wrong?

>From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
Message-Id: <cover.1345046444.git.alanbutty12 at gmail.com>
From: Alan M Butler <alanbutty12 at gmail.com>
Date: Wed, 15 Aug 2012 17:00:44 +0100
Subject: [PATCH] *** SUBJECT HERE ***

*** BLURB HERE ***

Alan M Butler (1):
  ARM: Kirkwood: Iomega_IX2_200     Signed-off-by: Alan M Butler
    <alanbutty12 at gmail.com>

 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 210 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

-- 
1.7.5.4
>From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
Message-Id: <f55ed67347f4b10ebbe2adc29d134acaf362279a.1345046444.git.alanbutty12 at gmail.com>
In-Reply-To: <cover.1345046444.git.alanbutty12 at gmail.com>
References: <cover.1345046444.git.alanbutty12 at gmail.com>
From: Alan M Butler <alanbutty12 at gmail.com>
Date: Wed, 15 Aug 2012 16:52:56 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 Signed-off-by: Alan M Butler
 <alanbutty12 at gmail.com>

---
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 210 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 0000000..7863009
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Iomega StorCenter ix2-200";
+	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		i2c at 11000 {
+			status = "okay";
+
+			lm63: lm63 at 4c {
+				compatible = "national,lm63";
+				reg = <0x4c>;
+			};
+		};
+
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at a0000 {
+				label = "env";
+				reg = <0xa0000 0x20000>;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x100000 0x300000>;
+				read-only;
+			};
+
+			partition at 400000 {
+				label = "uInitrd";
+				reg = <0x540000 0x1000000>;
+			};
+		};
+		sata at 80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			label = "status:white:power_led";
+			gpios = <&gpio0 16 0>;
+			linux,default-trigger = "default-on";
+		};
+		rebuild_led {
+			label = "status:white:rebuild_led";
+			gpios = <&gpio1 5 0>;
+		};
+		health_led {
+			label = "status:red:health_led";
+			gpios = <&gpio1 6 0>;
+		};
+		backup_led {
+			label = "status:blue:backup_led";
+			gpios = <&gpio0 15 0>;
+		};
+	};
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		button at 1 {
+			label = "OTB Button";
+			linux,code = <0x00>;
+			gpios = <&gpio1 4 1>;
+			debounce-interval = <100>;
+		};
+		button at 2 {
+			label = "Reset";
+			linux,code = <0x01>;
+			gpios = <&gpio0 12 1>;
+			debounce-interval = <100>;
+		};
+		button at 3 {
+			label = "Power";
+			linux,code = <0x028>;
+			gpios = <&gpio0 14 1>;
+			debounce-interval = <100>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..bee8451 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -195,6 +195,13 @@ config MACH_T5325
 	  Say 'Y' here if you want your kernel to support the
 	  HP t5325 Thin Client.

+config MACH_IOMEGA_IX2_200_DT
+	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Iomega StorCenter ix2-200 (Flattened Device Tree).
+
 endmenu

 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..f5484dc 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot
b/arch/arm/mach-kirkwood/Makefile.boot
index 2a576ab..f8ef771 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c
b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..a932ae9 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();

+	if (of_machine_is_compatible("iom,ix2-200"))
+		iomega_ix2_200_init()
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"iom,ix2-200",
 	NULL
 };

diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 0000000..a6bb98e
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <net/dsa.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+	.phy_addr       = MV643XX_ETH_PHY_NONE,
+	.speed          = SPEED_1000,
+	.duplex         = DUPLEX_FULL,
+};
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+	MPP12_GPIO,			/* Reset Button */
+	MPP14_GPIO,			/* Power Button */
+	MPP15_GPIO,			/* Backup LED (blue) */
+	MPP16_GPIO,			/* Power LED (white) */
+	MPP35_GPIO,			/* OTB Button */
+	MPP36_GPIO,			/* Rebuild LED (white) */
+	MPP37_GPIO,			/* Health LED (red) */
+	MPP38_GPIO,			/* SATA LED brightness control 1 */
+	MPP39_GPIO,			/* SATA LED brightness control 2 */
+	MPP40_GPIO,			/* Backup LED brightness control 1 */
+	MPP41_GPIO,			/* Backup LED brightness control 2 */
+	MPP42_GPIO,			/* Power LED brightness control 1 */
+	MPP43_GPIO,			/* Power LED brightness control 2 */
+	MPP44_GPIO,			/* Health LED brightness control 1 */
+	MPP45_GPIO,			/* Health LED brightness control 2 */
+	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
+	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
+	0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+	kirkwood_ehci_init();
+
+	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
+	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
+}
+
+static int __init iomega_ix2_200_pci_init(void)
+{
+	if (of_machine_is_compatible("iom,ix2-200"))
+		kirkwood_pcie_init(KW_PCIE0);
+	return 0;
+}
+subsys_initcall(iomega_ix2_200_pci_init);
+
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..d5d4064 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif

+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
-- 
1.7.5.4


From olof at lixom.net  Wed Aug 15 15:03:28 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 15 Aug 2012 12:03:28 -0700
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120815173711.GC14264@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <20120814230645.GA19607@quad.lixom.net>
 <20120815173711.GC14264@arm.com>
Message-ID: <20120815190328.GA6714@quad.lixom.net>

Hi,

On Wed, Aug 15, 2012 at 06:37:11PM +0100, Catalin Marinas wrote:
> Hi Olof,
> 
> > Given the recent development of ARM platforms, you might want to mandate
> > the state of IOMMUs as well (they should probably be off, since there
> > should be no active DMA activity). Graphics would be the exception to
> > this, since if you want to keep scanning out a splash screen, you'll
> > have to keep doing DMA...
> 
> We'll enhance this document as we get hardware as it's not clear whether
> we can simply mandate it to be off. We may have situations with some
> simple IOMMU that is previously set up by the firmware and the kernel
> doesn't get access to it. One example is the System MMU from ARM that
> supports stage 2 (hypervisor) translations and you just run a guest
> kernel without any control of the IOMMU.

Ok, fair enough.

> > > +/*
> > > + * Setup common bits before finally enabling the MMU. Essentially this is just
> > > + * loading the page table pointer and vector base registers.
> > > + *
> > > + * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
> > > + * the MMU.
> > > + */
> > > +__enable_mmu:
> > 
> > ENTRY()?
> 
> __enable_mmu is not used outside this file, so no need for ENTRY().
> 
> > > +	ldr	x5, =vectors
> > > +	msr	vbar_el1, x5
> > > +	msr	ttbr0_el1, x25			// load TTBR0
> > > +	msr	ttbr1_el1, x26			// load TTBR1
> > > +	isb
> > > +	b	__turn_mmu_on
> > > +ENDPROC(__enable_mmu)
> > 
> > ...or just END()? Same for a few of the other functions below.
> 
> ENDPROC() gives us ".type @function" in addition to END(). This proved
> to be useful in the past for debugging symbols, unwind table (though we
> don't have the latter on AArch64).

A good as reason as any, sounds good.

> > > +static void __init setup_processor(void)
> > > +{
> > > +	struct proc_info_list *list;
> > > +
> > > +	/*
> > > +	 * locate processor in the list of supported processor
> > > +	 * types.  The linker builds this table for us from the
> > > +	 * entries in arch/arm/mm/proc.S
> > > +	 */
> > 
> > Probably from arch/arm64/... somewhere?
> 
> Yes, I did a grep and found a few more.

Yeah, I pointed out some other stale ARM-derived comments in other patches.

> > > +	printk("CPU: %s [%08x] revision %d\n",
> > > +	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
> > > +
> > > +	sprintf(init_utsname()->machine, "aarch64");
> > 
> > > +	initial_boot_params = devtree;
> > > +	dt_root = of_get_flat_dt_root();
> > > +
> > > +	machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
> > > +	if (!machine_name)
> > > +		machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
> > > +	if (!machine_name)
> > > +		machine_name = "<unknown>";
> > > +	pr_info("Machine: %s\n", machine_name);
> > 
> > This property is an array of strings. It would be more valuable to print out
> > the entry that was matched for a platform instead of the provided one from the
> > device tree.
> 
> If we add machine_desc structure back, we could print which machine was
> matched. But so far I try to keep the SoC code to a minimum and just do
> the probing later in the SoC code (of_find_matching_node). Ideally we
> shouldn't have any SoC code and just keep code in drivers but we'll see
> how far we can get. We can discuss more details at the KS as I would
> like the arm-soc team to get involved here.

Interesting approach, I wonder if it'll scale, in particular if it comes
to needing to do early setup and init. For device-level setup, generic
will probably work just fine. And if it doesn't, things can be changed
later. So it sounds like a good start.

Definitely something we should discuss. I suggest not doing it at KS
though, since only half of the arm-soc team is invited there. So the
ARM mini-summit or hallway around LPC is a better venue.


-Olof



From swarren at wwwdotorg.org  Wed Aug 15 15:04:20 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 13:04:20 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502AE485.8060307@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org> <502AE485.8060307@wwwdotorg.org>
Message-ID: <502BF2B4.9030401@wwwdotorg.org>

On 08/14/2012 05:51 PM, Stephen Warren wrote:
> On 08/14/2012 04:58 PM, Stephen Warren wrote:
...
>> Can't we make the call to pci_bus_add_devices() optional in
>> pci_scan_root_bus() somehow; one of:
> 
> Sigh, that turns out not to work correctly; it solves at least this part
> of the problem when booting using device tree, but when booting using a
> board file, it causes the IRQ number passed to the PCIe device to be
> bogus:-(
> 
> I give up for now.

I think the appropriate workaround for Tegra in 3.6 is to simply make
any drivers for PCIe-based devices be modules instead of built-in, as
Thierry hinted at much earlier in the thread. I've validated that the
Ethernet works just fine on TrimSlice with that change, booting v3.6-rc1
using either board files or device tree.

For 3.7, we should continue the discussion about a real fix; I'll look
into the change Bjorn requested and see if it works, although given that
hacking pci_scan_root_bus as described immediately previously in this
thread caused a regression when booting using a board file, and the fact
that board files are no longer supported on Tegra, I'm not too confident
in the outcome...


From msb at chromium.org  Wed Aug 15 15:16:27 2012
From: msb at chromium.org (Mandeep Singh Baines)
Date: Wed, 15 Aug 2012 12:16:27 -0700
Subject: [PATCH] ARM: SAMSUNG: use spin_lock_irqsave() in clk_set_parent
Message-ID: <1345058187-18843-1-git-send-email-msb@chromium.org>

>From 0cdf3aff, "ARM: SAMSUNG: use spin_lock_irqsave() in
clk_{enable,disable}":

  The clk_enable()and clk_disable() can be used process and ISR either.
  And actually it is used for real product and other platforms use it
  now. So spin_lock_irqsave() should be used instead.

We need to make a similar change in clk_set_parent(). Otherwise,
you can potentially get spinlock recursion:

BUG: spinlock recursion on CPU#0, kinteractive/68
 lock: 807832a8, .magic: dead4ead, .owner: kinteractive/68, .owner_cpu: 0
[<80015f54>] (unwind_backtrace+0x0/0x128) from [<804f2914>] (dump_stack+0x20/0x24)
[<804f2914>] (dump_stack+0x20/0x24) from [<804f57b8>] (spin_dump+0x80/0x94)
[<804f57b8>] (spin_dump+0x80/0x94) from [<804f57f8>] (spin_bug+0x2c/0x30)
[<804f57f8>] (spin_bug+0x2c/0x30) from [<80222730>] (do_raw_spin_lock+0x54/0x150)
[<80222730>] (do_raw_spin_lock+0x54/0x150) from [<804f96ec>] (_raw_spin_lock_irqsave+0x20/0x28)
[<804f96ec>] (_raw_spin_lock_irqsave+0x20/0x28) from [<80022ea4>] (clk_enable+0x3c/0x84)
[<80022ea4>] (clk_enable+0x3c/0x84) from [<8038336c>] (s5p_mfc_clock_on+0x60/0x74)
[<8038336c>] (s5p_mfc_clock_on+0x60/0x74) from [<8038645c>] (s5p_mfc_read_info+0x20/0x38)
[<8038645c>] (s5p_mfc_read_info+0x20/0x38) from [<8037ca3c>] (s5p_mfc_handle_frame+0x2e4/0x4bc)
[<8037ca3c>] (s5p_mfc_handle_frame+0x2e4/0x4bc) from [<8037d420>] (s5p_mfc_irq+0x1ec/0x6cc)
[<8037d420>] (s5p_mfc_irq+0x1ec/0x6cc) from [<8007fc74>] (handle_irq_event_percpu+0x8c/0x244)
[<8007fc74>] (handle_irq_event_percpu+0x8c/0x244) from [<8007fe78>] (handle_irq_event+0x4c/0x6c)
[<8007fe78>] (handle_irq_event+0x4c/0x6c) from [<80082dd8>] (handle_fasteoi_irq+0xe4/0x150)
[<80082dd8>] (handle_fasteoi_irq+0xe4/0x150) from [<8007f424>] (generic_handle_irq+0x3c/0x50)
[<8007f424>] (generic_handle_irq+0x3c/0x50) from [<8000f7c4>] (handle_IRQ+0x88/0xc8)
[<8000f7c4>] (handle_IRQ+0x88/0xc8) from [<80008564>] (gic_handle_irq+0x44/0x68)
[<80008564>] (gic_handle_irq+0x44/0x68) from [<8000e400>] (__irq_svc+0x40/0x60)
Exception stack(0xef3cbe68 to 0xef3cbeb0)
[<8000e400>] (__irq_svc+0x40/0x60) from [<80022cfc>] (clk_set_parent+0x30/0x74)
[<80022cfc>] (clk_set_parent+0x30/0x74) from [<803ac7f8>] (set_apll.isra.0+0x28/0xb0)
[<803ac7f8>] (set_apll.isra.0+0x28/0xb0) from [<803ac8e4>] (exynos5250_set_frequency+0x64/0xb8)
[<803ac8e4>] (exynos5250_set_frequency+0x64/0xb8) from [<803ac280>] (exynos_target+0x1b0/0x220)
[<803ac280>] (exynos_target+0x1b0/0x220) from [<803a4a0c>] (__cpufreq_driver_target+0xb0/0xd4)
[<803a4a0c>] (__cpufreq_driver_target+0xb0/0xd4) from [<803aab80>] (cpufreq_interactive_updown_task+0x214/0x264)
[<803aab80>] (cpufreq_interactive_updown_task+0x214/0x264) from [<80047d04>] (kthread+0x9c/0xa8)
[<80047d04>] (kthread+0x9c/0xa8) from [<8000fa48>] (kernel_thread_exit+0x0/0x8)

Signed-off-by: Mandeep Singh Baines <msb at chromium.org>
Suggested-by: Sunil Mazhavanchery <sunilm at samsung.com>
CC: linux-arm-kernel at lists.infradead.org
CC: linux-samsung-soc at vger.kernel.org
CC: Ben Dooks <ben-linux at fluff.org>
CC: Kukjin Kim <kgene.kim at samsung.com>
CC: Russell King <linux at arm.linux.org.uk>
CC: Minho Ban <mhban at samsung.com>
CC: Jaecheol Lee <jc.lee at samsung.com>
CC: Sunyoung Kang <sy0816.kang at samsung.com>
CC: Kukjin Kim <kgene.kim at samsung.com>
CC: Olof Johansson <olofj at chromium.org>
---
 arch/arm/plat-samsung/clock.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 65c5eca..80eacca 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -173,17 +173,18 @@ struct clk *clk_get_parent(struct clk *clk)
 
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
+	unsigned long flags;
 	int ret = 0;
 
 	if (IS_ERR(clk))
 		return -EINVAL;
 
-	spin_lock(&clocks_lock);
+	spin_lock_irqsave(&clocks_lock, flags);
 
 	if (clk->ops && clk->ops->set_parent)
 		ret = (clk->ops->set_parent)(clk, parent);
 
-	spin_unlock(&clocks_lock);
+	spin_unlock_irqrestore(&clocks_lock, flags);
 
 	return ret;
 }
-- 
1.7.7.3



From swarren at wwwdotorg.org  Wed Aug 15 15:21:30 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 13:21:30 -0600
Subject: [PATCH 5/8] video: vt8500: Add devicetree support for vt8500-fb
 and wm8505-fb
In-Reply-To: <76F764B079F92A4E843589C893D0A022D1DCA8D0@SERVER.prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
 <1344389967-8465-6-git-send-email-linux@prisktech.co.nz>,
 <5022B444.2020501@wwwdotorg.org>
 <76F764B079F92A4E843589C893D0A022D1DCA8D0@SERVER.prisktech.co.nz>
Message-ID: <502BF6BA.9060407@wwwdotorg.org>

On 08/08/2012 01:37 PM, Tony Prisk wrote:
>> On 08/07/2012 07:39 PM, Tony Prisk wrote:
>>> Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
>>> tree bindings.

>>> diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
> 
>>> +     np = of_find_node_by_name(NULL, "display");
>>> +     if (!np) {
>>> +             pr_err("%s: No display description in Device Tree\n", __func__);
>>> +             ret = -EINVAL;
>>> +             goto failed_free_res;
>>> +     }
> 
>> I believe that using hard-coded node names is frowned upon. Better would
>> be to put a phandle into the display controller's node that points at
>> the node representing the display, e.g.:
> 
> Will do.

I don't think this change made it into v2?



From swarren at wwwdotorg.org  Wed Aug 15 15:23:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 13:23:32 -0600
Subject: [PATCHv2 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <502BF734.9000608@wwwdotorg.org>

On 08/08/2012 07:54 PM, Tony Prisk wrote:
> This patchset updates arch-vt8500 to devicetree and removes all the old-style
> code. Support for WM8650 has also been added.

Sorry for taking such a long time to re-review this.

I scanned the series looking for just the changes to the issues I raised
on v1, and I do see almost everything has been fixed up OK, except for
the one issue I just commented on. So, aside from that, this series is
fine by me. I'll defer to others about whether it's necessary to fix the
display node-name-vs.-phandle issue I pointed out, or defer that until
later.


From thierry.reding at avionic-design.de  Wed Aug 15 15:28:14 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 21:28:14 +0200
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <CAErSpo7v+i8i=mXCs7ZW8DtGTDN_4AEntwYLqGG8FcCzweySFg@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7v+i8i=mXCs7ZW8DtGTDN_4AEntwYLqGG8FcCzweySFg@mail.gmail.com>
Message-ID: <20120815192814.GA12870@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 10:06:27AM -0700, Bjorn Helgaas wrote:
> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > When using deferred driver probing, PCI host controller drivers may
> > actually require this function after the init stage.
> >
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v3:
> > - none
> >
> > Changes in v2:
> > - use __devinit annotations
> 
> Your original patch removed __init completely.  Here you change it to
> __devinit.  That means we decide whether to discard the function based
> on whether CONFIG_HOTPLUG is supported.  But I think your point is not
> about hotplug; it's merely that we should be able to scan a PCI bus
> after init-time.  We ought to be able to do a late PCI scan even if
> hotplug is not supported.
> 
> Therefore, I'd be inclined to remove __init completely unless you have
> another reason for preferring __devinit.

I thought __devinit would resolve to nothing if HOTPLUG is defined and
__init otherwise. That seemed more appropriate. However you are right
that it is useful to always have it available, so I'm fine with removing
the annotations altogether. Do you want me to follow up with a patch? Or
can you just take the first version? I'm not sure if it still applies.

Thierry
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From wade_farnsworth at mentor.com  Wed Aug 15 15:35:36 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Wed, 15 Aug 2012 12:35:36 -0700
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <20120815172731.GL29448@mudshark.cambridge.arm.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
 <502BD544.70903@mentor.com>
 <20120815172731.GL29448@mudshark.cambridge.arm.com>
Message-ID: <502BFA08.6010708@mentor.com>

Will Deacon wrote:
> On Wed, Aug 15, 2012 at 05:58:44PM +0100, Wade Farnsworth wrote:
>> We need to set current_thread_info()->syscall, since it's used in the
>> call to syscall_get_nr() in perf_syscall_{enter,exit}.
>
> Damn. I think that also means we have a bug, given that the SYSCALL_TRACE
> code can set this to -1, which gets used as an index into a bitmap by the
> looks of it. Considering that we have to pass the syscall number to
> trace_sys_enter anyway, it also seems broken.
>

I agree.  Looking at the other architectures, it seems the analogous 
function to ptrace_syscall_trace can return -1 under certain 
circumstances, but the original syscall value should be passed onto 
trace_sys_enter and returned from syscall_get_nr().  So, I'm thinking 
that we should modify our behavior accordingly.  What this means for us 
is that we never store -1 in the thread_info syscall field, and then 
pass that into trace_sys_enter instead of the ptrace_syscall_trace 
return value. Do you see any problems with this approach?

>> What about moving the setting of ->syscall to
>> syscall_trace_{enter,exit}?  That would preserve ptrace_syscall_trace()
>> for the TIF_SYSCALL_TRACE case only, but ensure that the field is set
>> the TRACEPOINT case as well.  Thoughts?
>
> I'd be tempted to set the thing unconditionally before checking the thread
> flag at the top of ptrace_syscall_trace. This hangs off the slowpath anyway
> and it makes everything a lot more readable.
>

OK, I'll make that change.

Wade


From thomas.abraham at linaro.org  Wed Aug 15 15:57:32 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:27:32 +0530
Subject: [PATCH v2 0/4] pinctrl: add support for samsung pinctrl driver
Message-ID: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>

Changes since v1:
- Added support for external gpio and wakeup interrupts for Exynos4.

This patch series adds a common pinctrl driver for all Samsung platforms and
enables the pinctrl driver support for Exynos4210 based device tree enabled
platforms. The scope of this driver is limited to only device tree enabled
platforms.

The intention of this driver is to replace the existing gpiolib driver and
provide pinctrl subsystem interface to configure the pins/mux instead
of existing platform callbacks.

Note that, the Samsung pinctrl driver is usable only on device tree enabled
Samsung platforms. Legacy platforms would still continue to use the older
gpiolib driver and hence updates to device drivers to use the pinctrl api
should ensure that support for legacy platforms is maintained.

The first patch adds a new pinctrl driver for Samsung. It provides interfaces
to the pinctrl and gpiolib subsystems. This driver provides a common framework
for all Samsung SoC's to enable the pinctrl and gpiolib support. The driver
accepts the information about pins, groups and functions from the device tree
and the information about gpio banks is supplied using driver data.

The second patch adds the driver data required to operate the pinctrl driver
on Exynos4210 based platforms. It allows includes support for Exynos4210
specific external gpio and wakeup interrupts which are provides to the Samsung
pinctrl driver as extensions.

The third patch modifies the existing gpiolib driver to skip the gpio pin
registrations if pinctrl driver support is found to be enabled. The fourth
patch skips the external wakeup interrupt configuration process in the
Exynos4 platform code if the external wakeup interrupt support is provided
by the pin-control driver.

Thomas Abraham (4):
  pinctrl: add samsung pinctrl and gpiolib driver
  pinctrl: add exynos4210 specific extensions for samsung pinctrl driver
  gpio: exynos4: skip gpiolib registration if pinctrl driver is used
  ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used

.../bindings/pinctrl/samsung-pinctrl.txt           |  176 ++++
 arch/arm/mach-exynos/common.c                      |   26 +
 drivers/gpio/gpio-samsung.c                        |   21 +
 drivers/pinctrl/Kconfig                            |   11 +
 drivers/pinctrl/Makefile                           |    2 +
 drivers/pinctrl/pinctrl-exynos.c                   |  555 +++++++++++++
 drivers/pinctrl/pinctrl-exynos.h                   |  213 +++++
 drivers/pinctrl/pinctrl-samsung.c                  |  873 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h                  |  215 +++++
 9 files changed, 2092 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-exynos.c
 create mode 100644 drivers/pinctrl/pinctrl-exynos.h
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h



From thomas.abraham at linaro.org  Wed Aug 15 15:57:34 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:27:34 +0530
Subject: [PATCH v2 2/4] pinctrl: add exynos4210 specific extensions for samsung
 pinctrl driver
In-Reply-To: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345060656-32201-3-git-send-email-thomas.abraham@linaro.org>

Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 drivers/pinctrl/Kconfig          |    7 +
 drivers/pinctrl/Makefile         |    1 +
 drivers/pinctrl/pinctrl-exynos.c |  555 ++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-exynos.h |  213 +++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-exynos.c
 create mode 100644 drivers/pinctrl/pinctrl-exynos.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 0d2398f..858afa5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -165,6 +165,13 @@ config PINCTRL_SAMSUNG
 	bool "Samsung pinctrl driver"
 	depends on OF
 
+config PINCTRL_EXYNOS4
+	bool "Pinctrl driver data for Exynos4 SoC"
+	depends on ARCH_EXYNOS4 && OF
+	depends on PINCTRL_SAMSUNG
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 7155301..9665411 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
+obj-$(CONFIG_PINCTRL_EXYNOS4)	+= pinctrl-exynos.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
new file mode 100644
index 0000000..f279506
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -0,0 +1,555 @@
+/*
+ * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file contains the Samsung Exynos specific information required by the
+ * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+ * external gpio and wakeup interrupt support.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+
+#include <asm/mach/irq.h>
+
+#include "pinctrl-samsung.h"
+#include "pinctrl-exynos.h"
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+	{ .compatible = "samsung,exynos4210-wakeup-eint", },
+};
+
+static void exynos_gpio_irq_unmask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << edata->pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_gpio_irq_mask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask |= ~(1 << edata->pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_gpio_irq_ack(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
+
+	writel(1 << edata->pin, d->virt_base + reg_pend);
+}
+
+static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct samsung_pin_ctrl *ctrl = d->ctrl;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
+	unsigned int con, trig_type;
+	unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		trig_type = EXYNOS_EINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		trig_type = EXYNOS_EINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		trig_type = EXYNOS_EINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		trig_type = EXYNOS_EINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		trig_type = EXYNOS_EINT_LEVEL_LOW;
+		break;
+	default:
+		pr_err("unsupported external interrupt type\n");
+		return -EINVAL;
+	}
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		__irq_set_handler_locked(irqd->irq, handle_edge_irq);
+	else
+		__irq_set_handler_locked(irqd->irq, handle_level_irq);
+
+	con = readl(d->virt_base + reg_con);
+	con &= ~(EXYNOS_EINT_CON_MASK << shift);
+	con |= trig_type << shift;
+	writel(con, d->virt_base + reg_con);
+	return 0;
+}
+
+/*
+ * irq_chip for gpio interrupts.
+ */
+static struct irq_chip exynos_gpio_irq_chip = {
+	.name		= "exynos_gpio_irq_chip",
+	.irq_unmask	= exynos_gpio_irq_unmask,
+	.irq_mask	= exynos_gpio_irq_mask,
+	.irq_ack		= exynos_gpio_irq_ack,
+	.irq_set_type	= exynos_gpio_irq_set_type,
+};
+
+/*
+ * given a controller-local external gpio interrupt number, prepare the handler
+ * data for it.
+ */
+static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
+				struct samsung_pinctrl_drv_data *d)
+{
+	struct samsung_pin_bank *bank = d->ctrl->pin_banks;
+	struct exynos_geint_data *eint_data;
+	unsigned int nr_banks = d->ctrl->nr_banks, idx;
+	unsigned int irq_base = 0, eint_offset = 0;
+
+	if (hw >= d->ctrl->nr_gint) {
+		dev_err(d->dev, "unsupported ext-gpio interrupt\n");
+		return NULL;
+	}
+
+	for (idx = 0; idx < nr_banks; idx++, bank++) {
+		if (bank->eint_type != EINT_TYPE_GPIO)
+			continue;
+		if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
+			break;
+		irq_base += bank->nr_pins;
+		eint_offset += 4;
+	}
+
+	if (idx == nr_banks) {
+		dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
+		return NULL;
+	}
+
+	eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
+	if (!eint_data) {
+		dev_err(d->dev, "no memory for eint-gpio data\n");
+		return NULL;
+	}
+
+	eint_data->bank	= bank;
+	eint_data->pin = hw - irq_base;
+	eint_data->eint_offset = eint_offset;
+	return eint_data;
+}
+
+static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	struct samsung_pinctrl_drv_data *d = h->host_data;
+	struct exynos_geint_data *eint_data;
+
+	eint_data = exynos_get_eint_data(hw, d);
+	if (!eint_data)
+		return -EINVAL;
+
+	irq_set_handler_data(virq, eint_data);
+	irq_set_chip_data(virq, h->host_data);
+	irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
+					handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
+{
+	struct samsung_pinctrl_drv_data *d = h->host_data;
+	struct exynos_geint_data *eint_data;
+
+	eint_data = irq_get_handler_data(virq);
+	devm_kfree(d->dev, eint_data);
+}
+
+/*
+ * irq domain callbacks for external gpio interrupt controller.
+ */
+static const struct irq_domain_ops exynos_gpio_irqd_ops = {
+	.map	= exynos_gpio_irq_map,
+	.unmap	= exynos_gpio_irq_unmap,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
+{
+	struct samsung_pinctrl_drv_data *d = data;
+	struct samsung_pin_ctrl *ctrl = d->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	unsigned int svc, group, pin, virq;
+
+	svc = readl(d->virt_base + ctrl->svc);
+	group = EXYNOS_SVC_GROUP(svc);
+	pin = svc & EXYNOS_SVC_NUM_MASK;
+
+	if (!group)
+		return IRQ_HANDLED;
+	bank += (group - 1);
+
+	virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
+	if (!virq)
+		return IRQ_NONE;
+	generic_handle_irq(virq);
+	return IRQ_HANDLED;
+}
+
+/*
+ * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
+ * @d: driver data of samsung pinctrl driver.
+ */
+static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
+{
+	struct device *dev = d->dev;
+	unsigned int ret;
+
+	if (!d->irq) {
+		dev_err(dev, "irq number not available\n");
+		return -EINVAL;
+	}
+
+	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
+					0, dev_name(dev), d);
+	if (ret) {
+		dev_err(dev, "irq request failed\n");
+		return -ENXIO;
+	}
+
+	d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
+				&exynos_gpio_irqd_ops, d);
+	if (!d->gpio_irqd) {
+		dev_err(dev, "gpio irq domain allocation failed\n");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
+static void exynos_wkup_irq_unmask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_wkup_irq_mask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_wkup_irq_ack(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long pend = d->ctrl->weint_pend + (bank << 2);
+
+	writel(1 << pin, d->virt_base + pend);
+}
+
+static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
+	unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
+	unsigned long con, trig_type;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		trig_type = EXYNOS_EINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		trig_type = EXYNOS_EINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		trig_type = EXYNOS_EINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		trig_type = EXYNOS_EINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		trig_type = EXYNOS_EINT_LEVEL_LOW;
+		break;
+	default:
+		pr_err("unsupported external interrupt type\n");
+		return -EINVAL;
+	}
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		__irq_set_handler_locked(irqd->irq, handle_edge_irq);
+	else
+		__irq_set_handler_locked(irqd->irq, handle_level_irq);
+
+	con = readl(d->virt_base + reg_con);
+	con &= ~(EXYNOS_EINT_CON_MASK << shift);
+	con |= trig_type << shift;
+	writel(con, d->virt_base + reg_con);
+	return 0;
+}
+
+/*
+ * irq_chip for wakeup interrupts
+ */
+static struct irq_chip exynos_wkup_irq_chip = {
+	.name	= "exynos_wkup_irq_chip",
+	.irq_unmask	= exynos_wkup_irq_unmask,
+	.irq_mask	= exynos_wkup_irq_mask,
+	.irq_ack	= exynos_wkup_irq_ack,
+	.irq_set_type	= exynos_wkup_irq_set_type,
+};
+
+/* interrupt handler for wakeup interrupts 0..15 */
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+	struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
+
+	chained_irq_enter(chip, desc);
+	chip->irq_mask(&desc->irq_data);
+
+	if (chip->irq_ack)
+		chip->irq_ack(&desc->irq_data);
+
+	eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
+	generic_handle_irq(eint_irq);
+	chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(chip, desc);
+}
+
+static void exynos_irq_demux_eint(int irq_base, unsigned long pend,
+					struct irq_domain *domain)
+{
+	unsigned int irq;
+
+	while (pend) {
+		irq = fls(pend) - 1;
+		generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
+		pend &= ~(1 << irq);
+	}
+}
+
+/* interrupt handler for wakeup interrupt 16 */
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+	struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
+	unsigned long pend;
+
+	chained_irq_enter(chip, desc);
+	pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
+	exynos_irq_demux_eint(16, pend, eintd->domain);
+	pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
+	exynos_irq_demux_eint(24, pend, eintd->domain);
+	chained_irq_exit(chip, desc);
+}
+
+static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
+	irq_set_chip_data(virq, h->host_data);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+/*
+ * irq domain callbacks for external wakeup interrupt controller.
+ */
+static const struct irq_domain_ops exynos_wkup_irqd_ops = {
+	.map	= exynos_wkup_irq_map,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+/*
+ * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
+ * @d: driver data of samsung pinctrl driver.
+ */
+static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
+{
+	struct device *dev = d->dev;
+	struct device_node *wkup_np;
+	struct exynos_weint_data *weint_data;
+	int idx, irq;
+
+	wkup_np = of_find_matching_node(dev->of_node, exynos_wkup_irq_ids);
+	if (!wkup_np) {
+		dev_err(dev, "wakeup controller node not found\n");
+		return -ENODEV;
+	}
+
+	d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
+				&exynos_wkup_irqd_ops, d);
+	if (!d->gpio_irqd) {
+		dev_err(dev, "wakeup irq domain allocation failed\n");
+		return -ENXIO;
+	}
+
+	weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
+	if (!weint_data) {
+		dev_err(dev, "could not allocate memory for weint_data\n");
+		return -ENOMEM;
+	}
+
+	irq = irq_of_parse_and_map(wkup_np, 16);
+	if (irq) {
+		weint_data[16].domain = d->wkup_irqd;
+		irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
+		irq_set_handler_data(irq, &weint_data[16]);
+	} else {
+		dev_err(dev, "irq number for EINT16-32 not found\n");
+	}
+
+	for (idx = 0; idx < 16; idx++) {
+		weint_data[idx].domain = d->wkup_irqd;
+		weint_data[idx].irq = idx;
+
+		irq = irq_of_parse_and_map(wkup_np, idx);
+		if (irq) {
+			irq_set_handler_data(irq, &weint_data[idx]);
+			irq_set_chained_handler(irq, exynos_irq_eint0_15);
+		} else {
+			dev_err(dev, "irq number for eint-%x not found\n", idx);
+		}
+	}
+	return 0;
+}
+
+/* pin banks of exynos4210 pin-controller 0 */
+static struct samsung_pin_bank exynos4210_pin_banks0[] = {
+	EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
+	EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
+	EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
+	EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
+	EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
+	EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
+	EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
+	EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
+	EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
+	EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
+	EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
+	EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
+	EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
+	EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
+	EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
+	EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
+};
+
+/* pin banks of exynos4210 pin-controller 1 */
+static struct samsung_pin_bank exynos4210_pin_banks1[] = {
+	EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
+	EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
+	EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
+	EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
+	EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
+	EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
+	EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
+	EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
+	EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
+	EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
+	EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
+	EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
+	EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
+	EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
+	EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
+	EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
+	EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
+	EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
+	EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
+	EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
+};
+
+/* pin banks of exynos4210 pin-controller 2 */
+static struct samsung_pin_bank exynos4210_pin_banks2[] = {
+	EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
+ * three gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 data */
+		.pin_banks	= exynos4210_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks0),
+		.base		= EXYNOS4210_GPIO_A0_START,
+		.nr_pins	= EXYNOS4210_GPIOA_NR_PINS,
+		.nr_gint	= EXYNOS4210_GPIOA_NR_GINT,
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.label		= "exynos4210-gpio-ctrl0",
+	}, {
+		/* pin-controller instance 1 data */
+		.pin_banks	= exynos4210_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks1),
+		.base		= EXYNOS4210_GPIOA_NR_PINS,
+		.nr_pins	= EXYNOS4210_GPIOB_NR_PINS,
+		.nr_gint	= EXYNOS4210_GPIOB_NR_GINT,
+		.nr_wint	= 32,
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,
+		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,
+		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.label		= "exynos4210-gpio-ctrl1",
+	}, {
+		/* pin-controller instance 2 data */
+		.pin_banks	= exynos4210_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks2),
+		.base		= EXYNOS4210_GPIOA_NR_PINS +
+					EXYNOS4210_GPIOB_NR_PINS,
+		.nr_pins	= EXYNOS4210_GPIOC_NR_PINS,
+		.label		= "exynos4210-gpio-ctrl2",
+	},
+};
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
new file mode 100644
index 0000000..e24267f
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -0,0 +1,213 @@
+/*
+ * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * This file contains the Exynos specific definitions for the Samsung
+ * pinctrl/gpiolib interface drivers.
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define EXYNOS_GPIO_START(__gpio)	((__gpio##_START) + (__gpio##_NR))
+
+#define EXYNOS4210_GPIO_A0_NR	(8)
+#define EXYNOS4210_GPIO_A1_NR	(6)
+#define EXYNOS4210_GPIO_B_NR	(8)
+#define EXYNOS4210_GPIO_C0_NR	(5)
+#define EXYNOS4210_GPIO_C1_NR	(5)
+#define EXYNOS4210_GPIO_D0_NR	(4)
+#define EXYNOS4210_GPIO_D1_NR	(4)
+#define EXYNOS4210_GPIO_E0_NR	(5)
+#define EXYNOS4210_GPIO_E1_NR	(8)
+#define EXYNOS4210_GPIO_E2_NR	(6)
+#define EXYNOS4210_GPIO_E3_NR	(8)
+#define EXYNOS4210_GPIO_E4_NR	(8)
+#define EXYNOS4210_GPIO_F0_NR	(8)
+#define EXYNOS4210_GPIO_F1_NR	(8)
+#define EXYNOS4210_GPIO_F2_NR	(8)
+#define EXYNOS4210_GPIO_F3_NR	(6)
+#define EXYNOS4210_GPIO_J0_NR	(8)
+#define EXYNOS4210_GPIO_J1_NR	(5)
+#define EXYNOS4210_GPIO_K0_NR	(7)
+#define EXYNOS4210_GPIO_K1_NR	(7)
+#define EXYNOS4210_GPIO_K2_NR	(7)
+#define EXYNOS4210_GPIO_K3_NR	(7)
+#define EXYNOS4210_GPIO_L0_NR	(8)
+#define EXYNOS4210_GPIO_L1_NR	(3)
+#define EXYNOS4210_GPIO_L2_NR	(8)
+#define EXYNOS4210_GPIO_Y0_NR	(6)
+#define EXYNOS4210_GPIO_Y1_NR	(4)
+#define EXYNOS4210_GPIO_Y2_NR	(6)
+#define EXYNOS4210_GPIO_Y3_NR	(8)
+#define EXYNOS4210_GPIO_Y4_NR	(8)
+#define EXYNOS4210_GPIO_Y5_NR	(8)
+#define EXYNOS4210_GPIO_Y6_NR	(8)
+#define EXYNOS4210_GPIO_X0_NR	(8)
+#define EXYNOS4210_GPIO_X1_NR	(8)
+#define EXYNOS4210_GPIO_X2_NR	(8)
+#define EXYNOS4210_GPIO_X3_NR	(8)
+#define EXYNOS4210_GPIO_Z_NR	(7)
+
+enum exynos4210_gpio_xa_start {
+	EXYNOS4210_GPIO_A0_START	= 0,
+	EXYNOS4210_GPIO_A1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
+	EXYNOS4210_GPIO_B_START		= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
+	EXYNOS4210_GPIO_C0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
+	EXYNOS4210_GPIO_C1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
+	EXYNOS4210_GPIO_D0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
+	EXYNOS4210_GPIO_D1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
+	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
+	EXYNOS4210_GPIO_E1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
+	EXYNOS4210_GPIO_E2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
+	EXYNOS4210_GPIO_E3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
+	EXYNOS4210_GPIO_E4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
+	EXYNOS4210_GPIO_F0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
+	EXYNOS4210_GPIO_F1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
+	EXYNOS4210_GPIO_F2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
+	EXYNOS4210_GPIO_F3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
+};
+
+enum exynos4210_gpio_xb_start {
+	EXYNOS4210_GPIO_J0_START	= 0,
+	EXYNOS4210_GPIO_J1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
+	EXYNOS4210_GPIO_K0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
+	EXYNOS4210_GPIO_K1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
+	EXYNOS4210_GPIO_K2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
+	EXYNOS4210_GPIO_K3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
+	EXYNOS4210_GPIO_L0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
+	EXYNOS4210_GPIO_L1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
+	EXYNOS4210_GPIO_L2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
+	EXYNOS4210_GPIO_Y0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
+	EXYNOS4210_GPIO_Y1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
+	EXYNOS4210_GPIO_Y2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
+	EXYNOS4210_GPIO_Y3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
+	EXYNOS4210_GPIO_Y4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
+	EXYNOS4210_GPIO_Y5_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
+	EXYNOS4210_GPIO_Y6_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
+	EXYNOS4210_GPIO_X0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
+	EXYNOS4210_GPIO_X1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
+	EXYNOS4210_GPIO_X2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
+	EXYNOS4210_GPIO_X3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
+};
+
+enum exynos4210_gpio_xc_start {
+	EXYNOS4210_GPIO_Z_START		= 0,
+};
+
+#define	EXYNOS4210_GPIO_A0_IRQ		EXYNOS4210_GPIO_A0_START
+#define	EXYNOS4210_GPIO_A1_IRQ		EXYNOS4210_GPIO_A1_START
+#define	EXYNOS4210_GPIO_B_IRQ		EXYNOS4210_GPIO_B_START
+#define	EXYNOS4210_GPIO_C0_IRQ		EXYNOS4210_GPIO_C0_START
+#define	EXYNOS4210_GPIO_C1_IRQ		EXYNOS4210_GPIO_C1_START
+#define	EXYNOS4210_GPIO_D0_IRQ		EXYNOS4210_GPIO_D0_START
+#define	EXYNOS4210_GPIO_D1_IRQ		EXYNOS4210_GPIO_D1_START
+#define	EXYNOS4210_GPIO_E0_IRQ		EXYNOS4210_GPIO_E0_START
+#define	EXYNOS4210_GPIO_E1_IRQ		EXYNOS4210_GPIO_E1_START
+#define	EXYNOS4210_GPIO_E2_IRQ		EXYNOS4210_GPIO_E2_START
+#define	EXYNOS4210_GPIO_E3_IRQ		EXYNOS4210_GPIO_E3_START
+#define	EXYNOS4210_GPIO_E4_IRQ		EXYNOS4210_GPIO_E4_START
+#define	EXYNOS4210_GPIO_F0_IRQ		EXYNOS4210_GPIO_F0_START
+#define	EXYNOS4210_GPIO_F1_IRQ		EXYNOS4210_GPIO_F1_START
+#define	EXYNOS4210_GPIO_F2_IRQ		EXYNOS4210_GPIO_F2_START
+#define	EXYNOS4210_GPIO_F3_IRQ		EXYNOS4210_GPIO_F3_START
+#define	EXYNOS4210_GPIO_J0_IRQ		EXYNOS4210_GPIO_J0_START
+#define	EXYNOS4210_GPIO_J1_IRQ		EXYNOS4210_GPIO_J1_START
+#define	EXYNOS4210_GPIO_K0_IRQ		EXYNOS4210_GPIO_K0_START
+#define	EXYNOS4210_GPIO_K1_IRQ		EXYNOS4210_GPIO_K1_START
+#define	EXYNOS4210_GPIO_K2_IRQ		EXYNOS4210_GPIO_K2_START
+#define	EXYNOS4210_GPIO_K3_IRQ		EXYNOS4210_GPIO_K3_START
+#define	EXYNOS4210_GPIO_L0_IRQ		EXYNOS4210_GPIO_L0_START
+#define	EXYNOS4210_GPIO_L1_IRQ		EXYNOS4210_GPIO_L1_START
+#define	EXYNOS4210_GPIO_L2_IRQ		EXYNOS4210_GPIO_L2_START
+#define	EXYNOS4210_GPIO_Z_IRQ		EXYNOS4210_GPIO_Z_START
+
+#define EXYNOS4210_GPIOA_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
+#define EXYNOS4210_GPIOA_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
+#define EXYNOS4210_GPIOB_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
+#define EXYNOS4210_GPIOB_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
+#define EXYNOS4210_GPIOC_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
+
+/* External GPIO and wakeup interrupt related definitions */
+#define EXYNOS_GPIO_ECON_OFFSET		0x700
+#define EXYNOS_GPIO_EMASK_OFFSET	0x900
+#define EXYNOS_GPIO_EPEND_OFFSET	0xA00
+#define EXYNOS_WKUP_ECON_OFFSET		0xE00
+#define EXYNOS_WKUP_EMASK_OFFSET	0xF00
+#define EXYNOS_WKUP_EPEND_OFFSET	0xF40
+#define EXYNOS_SVC_OFFSET		0xB08
+
+/* helpers to access interrupt service register */
+#define EXYNOS_SVC_GROUP_SHIFT		3
+#define EXYNOS_SVC_GROUP_MASK		0x1f
+#define EXYNOS_SVC_NUM_MASK		7
+#define EXYNOS_SVC_GROUP(x)		((x >> EXYNOS_SVC_GROUP_SHIFT) & \
+						EXYNOS_SVC_GROUP_MASK)
+
+/* Exynos specific external interrupt trigger types */
+#define EXYNOS_EINT_LEVEL_LOW		0
+#define EXYNOS_EINT_LEVEL_HIGH		1
+#define EXYNOS_EINT_EDGE_FALLING	2
+#define EXYNOS_EINT_EDGE_RISING		3
+#define EXYNOS_EINT_EDGE_BOTH		4
+#define EXYNOS_EINT_CON_MASK		0xF
+#define EXYNOS_EINT_CON_LEN		4
+
+#define EXYNOS_EINT_MAX_PER_BANK	8
+#define EXYNOS_EINT_NR_WKUP_EINT
+
+#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id)		\
+	{						\
+		.pctl_offset	= reg,			\
+		.pin_base	= (__gpio##_START),	\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.eint_type	= EINT_TYPE_NONE,	\
+		.name		= id			\
+	}
+
+#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id)		\
+	{						\
+		.pctl_offset	= reg,			\
+		.pin_base	= (__gpio##_START),	\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.eint_type	= EINT_TYPE_GPIO,	\
+		.irq_base	= (__gpio##_IRQ),	\
+		.name		= id			\
+	}
+
+/**
+ * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.
+ * @bank: pin bank from which this gpio interrupt originates.
+ * @pin: pin number within the bank.
+ * @eint_offset: offset to be added to the con/pend/mask register bank base.
+ */
+struct exynos_geint_data {
+	struct samsung_pin_bank		*bank;
+	unsigned int			pin;
+	unsigned int			eint_offset;
+};
+
+/**
+ * struct exynos_weint_data: irq specific data for all the wakeup interrupts
+ * generated by the external wakeup interrupt controller.
+ * @domain: irq domain representing the external wakeup interrupts
+ * @irq: interrupt number within the domain.
+ */
+struct exynos_weint_data {
+	struct irq_domain		*domain;
+	unsigned int			irq;
+};
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 15 15:57:33 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:27:33 +0530
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>

Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../bindings/pinctrl/samsung-pinctrl.txt           |  176 ++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-samsung.c                  |  873 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h                  |  215 +++++
 5 files changed, 1269 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
new file mode 100644
index 0000000..c30ee88
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -0,0 +1,176 @@
+Samsung GPIO and Pin Mux/Config controller
+
+Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pads/pins
+and also provides ability to multiplex and configure the output of various
+on-chip controllers onto these pads.
+
+Required Properties:
+- compatible: should be one of the following.
+  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
+  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
+
+- reg: Base address of the pin controller hardware module and length of
+  the address space it occupies.
+
+- interrupts: interrupt specifier for the controller. The format and value of
+  the interrupt specifier depends on the interrupt parent for the controller.
+
+- Pin mux/config groups as child nodes: The pin mux (selecting pin function
+  mode) and pin config (pull up/down, driver strength) settings are represented
+  as child nodes of the pin-controller node. There should be atleast one
+  child node and there is no limit on the count of these child nodes.
+
+  The child node should contain a list of pin(s) on which a particular pin
+  function selection or pin configuration (or both) have to applied. This
+  list of pins is specified using the property name "samsung,pins". There
+  should be atleast one pin specfied for this property and there is no upper
+  limit on the count of pins that can be specified. The pins are specified
+  using pin names which are derived from the hardware manual of the SoC. As
+  an example, the pins in GPA0 bank of the pin controller can be represented
+  as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
+  The format of the pin names should be (as per the hardware manual)
+  "[pin bank name]-[pin number within the bank]".
+
+  The pin function selection that should be applied on the pins listed in the
+  child node is specified using the "samsung,pin-function" property. The value
+  of this property that should be applied to each of the pins listed in the
+  "samsung,pins" property should be picked from the hardware manual of the SoC
+  for the specified pin group. This property is optional in the child node if
+  no specific function selection is desired for the pins listed in the child
+  node. The value of this property is used as-is to program the pin-controller
+  function selector register of the pin-bank.
+
+  The child node can also optionally specify one or more of the pin
+  configuration that should be applied on all the pins listed in the
+  "samsung,pins" property of the child node. The following pin configuration
+  properties are supported.
+
+  - samsung,pin-pud: Pull up/down configuration.
+  - samsung,pin-drv: Drive strength configuration.
+  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
+  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
+
+  The values specified by these config properties should be dervied from the
+  hardware manual and these values are programmed as-is into the pin
+  pull up/down and driver strength register of the pin-controller.
+
+  Note: A child should include atleast a pin function selection property or
+  pin configuration property (one or more) or both.
+
+  The client nodes that require a particular pin function selection and/or
+  pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
+  file.
+
+External GPIO and Wakeup Interrupts:
+
+The controller supports two types of external interrupts over gpio. The first
+is the external gpio interrupt and second is the external wakeup interrupts.
+The difference between the two is that the external wakeup interrupts can be
+used as system wakeup events.
+
+A. External GPIO Interrupts: For supporting external gpio interrupts, the
+   properties should be specified in the pin-controller device node.
+
+- interrupt-controller: identifies the controller node as interrupt-parent.
+- #interrupt-cells: the value of this property should be 2.
+  - First Cell: represents the external gpio interrupt number local to the
+    external gpio interrupt space of the controller.
+  - Second Cell: flags to identify the type of the interrupt
+    - 1 = rising edge triggered
+    - 2 = falling edge triggered
+    - 3 = rising and falling edge triggered
+    - 4 = high level triggered
+    - 8 = low level triggered
+
+B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
+   child node representing the external wakeup interrupt controller should be
+   included in the pin-controller device node. This child node should include
+   the following properties.
+
+   - compatible: identifies the type of the external wakeup interrupt controller
+     The possible values are:
+     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung Exynos4210 SoC.
+   - interrupt-parent: phandle of the interrupt parent to which the external
+     wakeup interrupts are forwarded to.
+   - interrupt-controller: identifies the node as interrupt-parent.
+   - #interrupt-cells: the value of this property should be 2
+     - First Cell: represents the external wakeup interrupt number local to
+       the external wakeup interrupt space of the controller.
+     - Second Cell: flags to identify the type of the interrupt
+       - 1 = rising edge triggered
+       - 2 = falling edge triggered
+       - 3 = rising and falling edge triggered
+       - 4 = high level triggered
+       - 8 = low level triggered
+
+Aliases:
+
+All the pin controller nodes should be represented in the aliases node using
+the following format 'pinctrl{n}' where n is a unique number for the alias.
+
+Example 1:
+
+	pinctrl_0: pinctrl at 11400000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa0-4", "gpa0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_bus: i2c2-bus {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+Example 2:
+
+	pinctrl_1: pinctrl at 11000000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+					<0 32 0>;
+		};
+	};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 73aafd9..0d2398f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -161,6 +161,10 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_SAMSUNG
+	bool "Samsung pinctrl driver"
+	depends on OF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index cda3984..7155301 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
new file mode 100644
index 0000000..e1b81bc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -0,0 +1,873 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This driver implements the Samsung pinctrl driver. It supports setting up of
+ * pinmux and pinconf configurations. The gpiolib interface is also included.
+ * External interrupt (gpio and wakeup) support are not included in this driver
+ * but provides extensions to which platform specific implementation of the gpio
+ * and wakeup interrupts can be hooked to.
+ */
+
+#include "core.h"
+#include "pinctrl-samsung.h"
+
+/* list of all possible config options supported */
+struct pin_config {
+	char		*prop_cfg;
+	unsigned int	cfg_type;
+} pcfgs[] = {
+	{ "samsung,pin-pud", PINCFG_TYPE_PUD },
+	{ "samsung,pin-drv", PINCFG_TYPE_DRV },
+	{ "samsung,pin-pud-pdn", PINCFG_TYPE_CON_PND },
+	{ "samsung,pin-drv-pdn", PINCFG_TYPE_PUD_PND },
+};
+
+/* check if the selector is a valid pin group selector */
+static int samsung_get_group_count(struct pinctrl_dev *pctldev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->nr_groups;
+}
+
+/* return the name of the group selected by the group selector */
+static const char *samsung_get_group_name(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pin_groups[selector].name;
+}
+
+/* return the pin numbers associated with the specified group */
+static int samsung_get_group_pins(struct pinctrl_dev *pctldev,
+		unsigned selector, const unsigned **pins, unsigned *num_pins)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*pins = drvdata->pin_groups[selector].pins;
+	*num_pins = drvdata->pin_groups[selector].num_pins;
+	return 0;
+}
+
+/* create pinctrl_map entries by parsing device tree nodes */
+static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
+			struct device_node *np, struct pinctrl_map **maps,
+			unsigned *nmaps)
+{
+	struct device *dev = pctldev->dev;
+	struct pinctrl_map *map;
+	unsigned long *cfg = NULL;
+	char *gname, *fname;
+	int cfg_cnt = 0, map_cnt = 0, idx = 0;
+
+	/* count the number of config options specfied in the node */
+	for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+		if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
+			cfg_cnt++;
+	}
+
+	/*
+	 * Find out the number of map entries to create. All the config options
+	 * can be accomadated into a single config map entry.
+	 */
+	if (cfg_cnt)
+		map_cnt = 1;
+	if (of_find_property(np, "samsung,pin-function", NULL))
+		map_cnt++;
+	if (!map_cnt) {
+		dev_err(dev, "node %s does not have either config or function "
+				"configurations\n", np->name);
+		return -EINVAL;
+	}
+
+	/* Allocate memory for pin-map entries */
+	map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
+	if (!map) {
+		dev_err(dev, "could not alloc memory for pin-maps\n");
+		return -ENOMEM;
+	}
+	*nmaps = 0;
+
+	/* Allocate memory for pin group name. The pin group name is derived
+	 * from the node name from which these map entries are be created.
+	 */
+	gname = kzalloc(strlen(np->name) + 4, GFP_KERNEL);
+	if (!gname) {
+		dev_err(dev, "failed to alloc memory for group name\n");
+		goto free_map;
+	}
+	sprintf(gname, "%s-grp", np->name);
+
+	/*
+	 * don't have config options? then skip over to creating function
+	 * map entries.
+	 */
+	if (!cfg_cnt)
+		goto skip_cfgs;
+
+	/* Allocate memory for config entries */
+	cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
+	if (!cfg) {
+		dev_err(dev, "failed to alloc memory for configs\n");
+		goto free_gname;
+	}
+
+	/* Prepare a list of config settings */
+	for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+		u32 value;
+		if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
+			cfg[cfg_cnt++] =
+				PINCFG_PACK(pcfgs[idx].cfg_type, value);
+	}
+
+	/* create the config map entry */
+	map[*nmaps].data.configs.group_or_pin = gname;
+	map[*nmaps].data.configs.configs = cfg;
+	map[*nmaps].data.configs.num_configs = cfg_cnt;
+	map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+	*nmaps += 1;
+
+skip_cfgs:
+	/* create the function map entry */
+	if (of_find_property(np, "samsung,pin-function", NULL)) {
+		fname = kzalloc(strlen(np->name) + 4, GFP_KERNEL);
+		if (!fname) {
+			dev_err(dev, "failed to alloc memory for func name\n");
+			goto free_cfg;
+		}
+		sprintf(fname, "%s-mux", np->name);
+
+		map[*nmaps].data.mux.group = gname;
+		map[*nmaps].data.mux.function = fname;
+		map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+		*nmaps += 1;
+	}
+
+	*maps = map;
+	return 0;
+
+free_cfg:
+	kfree(cfg);
+free_gname:
+	kfree(gname);
+free_map:
+	kfree(map);
+	return -ENOMEM;
+}
+
+/* free the memory allocated to hold the pin-map table */
+static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
+			     struct pinctrl_map *map, unsigned num_maps)
+{
+	int idx;
+
+	for (idx = 0; idx < num_maps; idx++) {
+		if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
+			kfree(map[idx].data.mux.function);
+			if (!idx)
+				kfree(map[idx].data.mux.group);
+		} else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
+			kfree(map[idx].data.configs.configs);
+			if (!idx)
+				kfree(map[idx].data.configs.group_or_pin);
+		}
+	};
+
+	kfree(map);
+}
+
+/* list of pinctrl callbacks for the pinctrl core */
+static struct pinctrl_ops samsung_pctrl_ops = {
+	.get_groups_count	= samsung_get_group_count,
+	.get_group_name		= samsung_get_group_name,
+	.get_group_pins		= samsung_get_group_pins,
+	.dt_node_to_map		= samsung_dt_node_to_map,
+	.dt_free_map		= samsung_dt_free_map,
+};
+
+/* check if the selector is a valid pin function selector */
+static int samsung_get_functions_count(struct pinctrl_dev *pctldev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->nr_functions;
+}
+
+/* return the name of the pin function specified */
+static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pmx_functions[selector].name;
+}
+
+/* return the groups associated for the specified function selector */
+static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
+		unsigned selector, const char * const **groups,
+		unsigned * const num_groups)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*groups = drvdata->pmx_functions[selector].groups;
+	*num_groups = drvdata->pmx_functions[selector].num_groups;
+	return 0;
+}
+
+/*
+ * given a pin number that is local to a pin controller, find out the pin bank
+ * and the register base of the pin bank.
+ */
+static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
+			void __iomem **reg, unsigned long *offset,
+			struct samsung_pin_bank **bank)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct samsung_pin_bank *b;
+
+	drvdata = dev_get_drvdata(gc->dev);
+	b = drvdata->ctrl->pin_banks;
+
+	while ((pin >= b->pin_base) &&
+			((b->pin_base + b->nr_pins - 1) < pin))
+		b++;
+
+	*reg = drvdata->virt_base + b->pctl_offset;
+	*offset = pin - b->pin_base;
+	if (bank)
+		*bank = b;
+
+	/* some banks have two config registers in a single bank */
+	if (*offset * b->func_width > BITS_PER_LONG)
+		*reg += 4;
+}
+
+/* enable or disable a pinmux function */
+static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group, bool enable)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pins;
+	unsigned long data, pin_offset, cnt;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	unsigned int mask, shift;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pins = drvdata->pin_groups[group].pins;
+
+	/*
+	 * for each pin in the pin group selected, program the correspoding pin
+	 * pin function number in the config register.
+	 */
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
+		pin_to_reg_bank(drvdata->gc, pins[cnt] - drvdata->ctrl->base,
+				&reg, &pin_offset, &bank);
+		mask = (1 << bank->func_width) - 1;
+		shift = pin_offset * bank->func_width;
+
+		data = readl(reg);
+		data &= ~(mask << shift);
+		if (enable)
+			data |= drvdata->pin_groups[group].func << shift;
+		writel(data, reg);
+	}
+}
+
+/* enable a specified pinmux by writing to registers */
+static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group)
+{
+	samsung_pinmux_setup(pctldev, selector, group, true);
+	return 0;
+}
+
+/* disable a specified pinmux by writing to registers */
+static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
+					unsigned selector, unsigned group)
+{
+	samsung_pinmux_setup(pctldev, selector, group, false);
+}
+
+/*
+ * The calls to gpio_direction_output() and gpio_direction_input()
+ * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
+ * function called from the gpiolib interface).
+ */
+static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+		struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+	unsigned long data, pin_offset;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	unsigned int mask, shift;
+
+	pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank);
+	mask = (1 << bank->func_width) - 1;
+	shift = pin_offset * bank->func_width;
+
+	data = readl(reg);
+	data &= ~(mask << shift);
+	if (!input)
+		data |= FUNC_OUTPUT << shift;
+	writel(data, reg);
+	return 0;
+}
+
+/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
+static struct pinmux_ops samsung_pinmux_ops = {
+	.get_functions_count	= samsung_get_functions_count,
+	.get_function_name	= samsung_pinmux_get_fname,
+	.get_function_groups	= samsung_pinmux_get_groups,
+	.enable			= samsung_pinmux_enable,
+	.disable		= samsung_pinmux_disable,
+	.gpio_set_direction	= samsung_pinmux_gpio_set_direction,
+};
+
+/* configure the pull up/down registers */
+static void samsung_pinconf_set_pud(struct samsung_pinctrl_drv_data *drvdata,
+		struct samsung_pin_bank *bank, void __iomem *reg,
+		unsigned long pin_offset, unsigned long config)
+{
+	unsigned int mask, shift, pud;
+	unsigned long data;
+
+	/* update the pull up/down configuration */
+	mask = (1 << bank->pud_width) - 1;
+	shift = pin_offset * bank->pud_width;
+	pud =  PINCFG_UNPACK_VALUE(config);
+
+	data = readl(reg + PUD_REG);
+	data &= ~(mask << shift);
+	data |= (pud << shift);
+	writel(data, reg + PUD_REG);
+}
+
+/* configure the driver strength registers */
+static void samsung_pinconf_set_drv(struct samsung_pinctrl_drv_data *drvdata,
+		struct samsung_pin_bank *bank, void __iomem *reg,
+		unsigned long pin_offset, unsigned long config)
+{
+	unsigned int mask, shift, drv;
+	unsigned long data;
+
+	/* update the drive strength configuration */
+	mask = (1 << bank->drv_width) - 1;
+	shift = pin_offset * bank->drv_width;
+	drv = PINCFG_UNPACK_VALUE(config);
+
+	data = readl(reg + DRV_REG);
+	data &= ~(mask << shift);
+	data |= (drv << shift);
+	writel(data, reg + DRV_REG);
+}
+
+/* set the pull up/down and driver strength settings for a specified pin */
+static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+					unsigned long config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	unsigned long pin_offset;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg,
+					&pin_offset, &bank);
+
+	switch (PINCFG_UNPACK_TYPE(config)) {
+	case PINCFG_TYPE_PUD:
+		samsung_pinconf_set_pud(drvdata, bank, reg, pin_offset, config);
+		break;
+	case PINCFG_TYPE_DRV:
+		samsung_pinconf_set_drv(drvdata, bank, reg, pin_offset, config);
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * set the pull up/down and driver strength settings for all the pins in a
+ * specified pin group
+ */
+static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
+			unsigned group, unsigned long config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pins;
+	unsigned int cnt;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pins = drvdata->pin_groups[group].pins;
+
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++)
+		samsung_pinconf_set(pctldev, pins[cnt], config);
+
+	return 0;
+}
+
+/* reading pin pull up/down and driver strength settings not implemented */
+static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+					unsigned long *config)
+{
+	return -ENOTSUPP;
+}
+
+/* reading pin pull up/down and driver strength settings not implemented */
+static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
+				unsigned int group, unsigned long *config)
+{
+	return -ENOTSUPP;
+}
+
+/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
+static struct pinconf_ops samsung_pinconf_ops = {
+	.pin_config_get		= samsung_pinconf_get,
+	.pin_config_set		= samsung_pinconf_set,
+	.pin_config_group_get	= samsung_pinconf_group_get,
+	.pin_config_group_set	= samsung_pinconf_group_set,
+};
+
+/* gpiolib gpio_set callback function */
+static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+	void __iomem *reg;
+	unsigned long pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data &= ~(1 << pin_offset);
+	if (value)
+		data |= 1 << pin_offset;
+	writel(data, reg + DAT_REG);
+}
+
+/* gpiolib gpio_get callback function */
+static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+	void __iomem *reg;
+	unsigned long pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data >>= pin_offset;
+	data &= 1;
+	return data;
+}
+
+/*
+ * gpiolib gpio_direction_input callback function. The setting of the pin
+ * mux function as 'gpio input' will be handled by the pinctrl susbsystem
+ * interface.
+ */
+static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+	return pinctrl_gpio_direction_input(gc->base + offset);
+}
+
+/*
+ * gpiolib gpio_direction_output callback function. The setting of the pin
+ * mux function as 'gpio output' will be handled by the pinctrl susbsystem
+ * interface.
+ */
+static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+							int value)
+{
+	samsung_gpio_set(gc, offset, value);
+	return pinctrl_gpio_direction_output(gc->base + offset);
+}
+
+/*
+ * Parse the pin names listed in the 'samsung,pins' property and convert it
+ * into a list of gpio numbers are create a pin group from it.
+ */
+static int __init samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
+			struct device_node *cfg_np, struct pinctrl_desc *pctl,
+			unsigned int **pin_list, unsigned int *npins)
+{
+	struct device *dev = &pdev->dev;
+	struct property *prop;
+	struct pinctrl_pin_desc const *pdesc = pctl->pins;
+	unsigned int idx = 0, cnt;
+	const char *pin_name;
+
+	*npins = of_property_count_strings(cfg_np, "samsung,pins");
+	if (*npins < 0) {
+		dev_err(dev, "invalid pin list in %s node", cfg_np->name);
+		return -EINVAL;
+	}
+
+	*pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
+	if (!*pin_list) {
+		dev_err(dev, "failed to allocate memory for pin list\n");
+		return -ENOMEM;
+	}
+
+	of_property_for_each_string(cfg_np, "samsung,pins", prop, pin_name) {
+		for (cnt = 0; cnt < pctl->npins; cnt++) {
+			if (pdesc[cnt].name) {
+				if (!strcmp(pin_name, pdesc[cnt].name)) {
+					(*pin_list)[idx++] = pdesc[cnt].number;
+					break;
+				}
+			}
+		}
+		if (cnt == pctl->npins) {
+			dev_err(dev, "pin %s not valid in %s node\n",
+					pin_name, cfg_np->name);
+			devm_kfree(dev, *pin_list);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Parse the information about all the available pin groups and pin functions
+ * from device node of the pin-controller. A pin group is formed with all
+ * the pins listed in the "samsung,pins" property.
+ */
+static int __init samsung_pinctrl_parse_dt(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *dev_np = dev->of_node;
+	struct device_node *cfg_np;
+	struct samsung_pin_group *groups, *grp;
+	struct samsung_pmx_func *functions, *func;
+	unsigned *pin_list;
+	unsigned int npins, grp_cnt, func_idx = 0;
+	char *gname, *fname;
+	int ret;
+
+	grp_cnt = of_get_child_count(dev_np);
+	if (!grp_cnt)
+		return -EINVAL;
+
+	groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
+	if (!groups) {
+		dev_err(dev, "failed allocate memory for ping group list\n");
+		return -EINVAL;
+	}
+	grp = groups;
+
+	functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
+	if (!functions) {
+		dev_err(dev, "failed to allocate memory for function list\n");
+		return -EINVAL;
+	}
+	func = functions;
+
+	/*
+	 * Iterate over all the child nodes of the pin controller node
+	 * and create pin groups and pin function lists.
+	 */
+	for_each_child_of_node(dev_np, cfg_np) {
+		if (of_find_property(cfg_np, "interrupt-controller", NULL))
+			continue;
+
+		ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
+					&drvdata->pctl,	&pin_list, &npins);
+		if (ret)
+			return ret;
+
+		/* derive pin group name from the node name */
+		gname = devm_kzalloc(dev, strlen(cfg_np->name) + 4, GFP_KERNEL);
+		if (!gname) {
+			dev_err(dev, "failed to alloc memory for group name\n");
+			return -ENOMEM;
+		}
+		sprintf(gname, "%s-grp", cfg_np->name);
+
+		grp->name = gname;
+		grp->pins = pin_list;
+		grp->num_pins = npins;
+		of_property_read_u32(cfg_np, "samsung,pin-function",
+						&grp->func);
+		grp++;
+
+		if (!of_find_property(cfg_np, "samsung,pin-function", NULL))
+			continue;
+
+		/* derive function name from the node name */
+		fname = devm_kzalloc(dev, strlen(cfg_np->name) + 4, GFP_KERNEL);
+		if (!fname) {
+			dev_err(dev, "failed to alloc memory for func name\n");
+			return -ENOMEM;
+		}
+		sprintf(fname, "%s-mux", cfg_np->name);
+
+		func->name = fname;
+		func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
+		if (!func->groups) {
+			dev_err(dev, "failed to alloc memory for group list "
+					"in pin function");
+			return -ENOMEM;
+		}
+		func->groups[0] = gname;
+		func->num_groups = 1;
+		func++;
+		func_idx++;
+	}
+
+	drvdata->pin_groups = groups;
+	drvdata->nr_groups = grp_cnt;
+	drvdata->pmx_functions = functions;
+	drvdata->nr_functions = func_idx;
+
+	return 0;
+}
+
+/* register the pinctrl interface with the pinctrl subsystem */
+static int __init samsung_pinctrl_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct pinctrl_desc *ctrldesc = &drvdata->pctl;
+	struct pinctrl_pin_desc *pindesc, *pdesc;
+	struct samsung_pin_bank *pin_bank;
+	char *pin_names;
+	int pin, bank, ret;
+
+	ctrldesc->name = "samsung-pinctrl";
+	ctrldesc->owner = THIS_MODULE;
+	ctrldesc->pctlops = &samsung_pctrl_ops;
+	ctrldesc->pmxops = &samsung_pinmux_ops;
+	ctrldesc->confops = &samsung_pinconf_ops;
+
+	pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
+			drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pindesc) {
+		dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
+		return -ENOMEM;
+	}
+	ctrldesc->pins = pindesc;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+
+	/* dynamically populate the pin number and  pin name for pindesc */
+	for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
+		pdesc->number = pin + drvdata->ctrl->base;
+
+	/*
+	 * allocate space for storing the dynamically generated names for all
+	 * the pins which belong to this pin-controller.
+	 */
+	pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
+					drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pin_names) {
+		dev_err(&pdev->dev, "mem alloc for pin names failed\n");
+		return -ENOMEM;
+	}
+
+	/* for each pin, the name of the pin is pin-bank name + pin number */
+	for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) {
+		pin_bank = &drvdata->ctrl->pin_banks[bank];
+		for (pin = 0; pin < pin_bank->nr_pins; pin++) {
+			sprintf(pin_names, "%s-%d", pin_bank->name, pin);
+			pdesc = pindesc + pin_bank->pin_base + pin;
+			pdesc->name = pin_names;
+			pin_names += PIN_NAME_LENGTH;
+		}
+	}
+
+	drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
+	if (!drvdata->pctl_dev) {
+		dev_err(&pdev->dev, "could not register pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	drvdata->grange.name = "samsung-pctrl-gpio-range";
+	drvdata->grange.id = 0;
+	drvdata->grange.base = drvdata->ctrl->base;
+	drvdata->grange.npins = drvdata->ctrl->nr_pins;
+	drvdata->grange.gc = drvdata->gc;
+	pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange);
+
+	ret = samsung_pinctrl_parse_dt(pdev, drvdata);
+	if (ret) {
+		pinctrl_unregister(drvdata->pctl_dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* register the gpiolib interface with the gpiolib subsystem */
+static int __init samsung_gpiolib_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct gpio_chip *gc;
+	int ret;
+
+	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
+	if (!gc) {
+		dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
+		return -ENOMEM;
+	}
+
+	drvdata->gc = gc;
+	gc->base = drvdata->ctrl->base;
+	gc->ngpio = drvdata->ctrl->nr_pins;
+	gc->dev = &pdev->dev;
+	gc->set = samsung_gpio_set;
+	gc->get = samsung_gpio_get;
+	gc->direction_input = samsung_gpio_direction_input;
+	gc->direction_output = samsung_gpio_direction_output;
+	gc->label = drvdata->ctrl->label;
+	gc->owner = THIS_MODULE;
+	ret = gpiochip_add(gc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
+					"code: %d\n", gc->label, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* unregister the gpiolib interface with the gpiolib subsystem */
+static int __init samsung_gpiolib_unregister(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	int ret = gpiochip_remove(drvdata->gc);
+	if (ret) {
+		dev_err(&pdev->dev, "gpio chip remove failed\n");
+		return ret;
+	}
+	return 0;
+}
+
+static const struct of_device_id samsung_pinctrl_dt_match[];
+
+/* retrieve the soc specific data */
+static inline struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
+				struct platform_device *pdev)
+{
+	int id;
+	const struct of_device_id *match;
+	const struct device_node *node = pdev->dev.of_node;
+
+	id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
+	if (id < 0) {
+		dev_err(&pdev->dev, "failed to get alias id\n");
+		return NULL;
+	}
+	match = of_match_node(samsung_pinctrl_dt_match, node);
+	return (struct samsung_pin_ctrl *)match->data + id;
+}
+
+static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct device *dev = &pdev->dev;
+	struct samsung_pin_ctrl *ctrl;
+	struct resource *res;
+	int ret;
+
+	if (!dev->of_node) {
+		dev_err(dev, "device tree node not found\n");
+		return -ENODEV;
+	}
+
+	ctrl = samsung_pinctrl_get_soc_data(pdev);
+	if (!ctrl) {
+		dev_err(&pdev->dev, "driver data not available\n");
+		return -EINVAL;
+	}
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata) {
+		dev_err(dev, "failed to allocate memory for driver's "
+				"private data\n");
+		return -ENOMEM;
+	}
+	drvdata->ctrl = ctrl;
+	drvdata->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "cannot find IO resource\n");
+		return -ENOENT;
+	}
+
+	drvdata->virt_base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!drvdata->virt_base) {
+		dev_err(dev, "ioremap failed\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res)
+		drvdata->irq = res->start;
+
+	ret = samsung_gpiolib_register(pdev, drvdata);
+	if (ret)
+		return ret;
+
+	ret = samsung_pinctrl_register(pdev, drvdata);
+	if (ret) {
+		samsung_gpiolib_unregister(pdev, drvdata);
+		return ret;
+	}
+
+	if (ctrl->eint_gpio_init)
+		ctrl->eint_gpio_init(drvdata);
+	if (ctrl->eint_wkup_init)
+		ctrl->eint_wkup_init(drvdata);
+
+	platform_set_drvdata(pdev, drvdata);
+	return 0;
+}
+
+static const struct of_device_id samsung_pinctrl_dt_match[] = {
+	{ .compatible = "samsung,pinctrl-exynos4210",
+		.data = (void *)exynos4210_pin_ctrl },
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
+
+static struct platform_driver samsung_pinctrl_driver = {
+	.probe		= samsung_pinctrl_probe,
+	.driver = {
+		.name	= "samsung-pinctrl",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(samsung_pinctrl_dt_match),
+	},
+};
+
+static int __init samsung_pinctrl_drv_register(void)
+{
+	return platform_driver_register(&samsung_pinctrl_driver);
+}
+postcore_initcall(samsung_pinctrl_drv_register);
+
+static void __exit samsung_pinctrl_drv_unregister(void)
+{
+	platform_driver_unregister(&samsung_pinctrl_driver);
+}
+module_exit(samsung_pinctrl_drv_unregister);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab at samsung.com>");
+MODULE_DESCRIPTION("Samsung pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
new file mode 100644
index 0000000..a57d7fe
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -0,0 +1,215 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_SAMSUNG_H
+#define __PINCTRL_SAMSUNG_H
+
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+
+/* register offsets within a pin bank */
+#define DAT_REG		0x4
+#define PUD_REG		0x8
+#define DRV_REG		0xC
+
+/* pinmux function number for pin as gpio output line */
+#define FUNC_OUTPUT	0x1
+
+/* Pin configuration types */
+#define PINCFG_TYPE_PUD			0
+#define PINCFG_TYPE_DRV			1
+#define PINCFG_TYPE_CON_PND		2
+#define PINCFG_TYPE_PUD_PND		3
+#define PINCFG_TYPE_MASK		0xFF
+
+/*
+ * pin configuration (pull up/down and drive strength) type and its value are
+ * packed together into a 16-bits. The upper 8-bits represent the configuration
+ * type and the lower 8-bits hold the value of the configuration type.
+ */
+#define PINCFG_VALUE_SHIFT		8
+#define PINCFG_VALUE_MASK		(0xFF << PINCFG_VALUE_SHIFT)
+#define PINCFG_PACK(type, value)	(((value) << PINCFG_VALUE_SHIFT) | type)
+#define PINCFG_UNPACK_TYPE(cfg)		((cfg) & PINCFG_TYPE_MASK)
+#define PINCFG_UNPACK_VALUE(cfg)	(((cfg) & PINCFG_VALUE_MASK) >> \
+						PINCFG_VALUE_SHIFT)
+
+#define EINT_TYPE_NONE	0	/* bank does not support external interrupts */
+#define EINT_TYPE_GPIO	1	/* bank supportes external gpio interrupts */
+
+/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
+#define PIN_NAME_LENGTH	10
+
+#define PIN_GROUP(n, p, f)				\
+	{						\
+		.name		= n,			\
+		.pins		= p,			\
+		.num_pins	= ARRAY_SIZE(p),	\
+		.func		= f			\
+	}
+
+#define PMX_FUNC(n, g)					\
+	{						\
+		.name		= n,			\
+		.groups		= g,			\
+		.num_groups	= ARRAY_SIZE(g),	\
+	}
+
+struct samsung_pinctrl_drv_data;
+
+/**
+ * struct samsung_pin_bank: represent a controller pin-bank.
+ * @reg_offset: starting offset of the pin-bank registers.
+ * @pin_base: starting pin number of the bank.
+ * @nr_pins: number of pins included in this bank.
+ * @func_width: width of the function selector bit field.
+ * @pud_width: width of the pin pull up/down selector bit field.
+ * @drc_width: width of the pin driver strength selector bit field.
+ * @eint_type: type of the external interrupt supported by the bank.
+ * @irq_base: starting controller local irq number of the bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank {
+	unsigned int		pctl_offset;
+	unsigned int		pin_base;
+	unsigned int		nr_pins;
+	unsigned int		func_width;
+	unsigned int		pud_width;
+	unsigned int		drv_width;
+	unsigned int		eint_type;
+	unsigned int		irq_base;
+	char			*name;
+};
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ * @base: starting system wide pin number.
+ * @nr_pins: number of pins supported by the controller.
+ * @nr_gint: number of external gpio interrupts supported.
+ * @nr_wint: number of external wakeup interrupts supported.
+ * @geint_con: offset of the ext-gpio controller registers.
+ * @geint_mask: offset of the ext-gpio interrupt mask registers.
+ * @geint_pend: offset of the ext-gpio interrupt pending registers.
+ * @weint_con: offset of the ext-wakeup controller registers.
+ * @weint_mask: offset of the ext-wakeup interrupt mask registers.
+ * @weint_pend: offset of the ext-wakeup interrupt pending registers.
+ * @svc: offset of the interrupt service register.
+ * @eint_gpio_init: platform specific callback to setup the external gpio
+ *	interrupts for the controller.
+ * @eint_wkup_init: platform specific callback to setup the external wakeup
+ *	interrupts for the controller.
+ * @label: for debug information.
+ */
+struct samsung_pin_ctrl {
+	struct samsung_pin_bank	*pin_banks;
+	unsigned int		nr_banks;
+
+	unsigned int		base;
+	unsigned int		nr_pins;
+	unsigned int		nr_gint;
+	unsigned int		nr_wint;
+
+	unsigned long		geint_con;
+	unsigned long		geint_mask;
+	unsigned long		geint_pend;
+
+	unsigned long		weint_con;
+	unsigned long		weint_mask;
+	unsigned long		weint_pend;
+
+	unsigned long		svc;
+
+	int			(*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
+	int			(*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
+	char			*label;
+};
+
+/**
+ * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
+ * @virt_base: register base address of the controller.
+ * @dev: device instance representing the controller.
+ * @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @ctrl: pin controller instance managed by the driver.
+ * @pctl: pin controller descriptor registered with the pinctrl subsystem.
+ * @pctl_dev: cookie representing pinctrl device instance.
+ * @pin_groups: list of pin groups available to the driver.
+ * @nr_groups: number of such pin groups.
+ * @pmx_functions: list of pin functions available to the driver.
+ * @nr_function: number of such pin functions.
+ * @gc: gpio_chip instance registered with gpiolib.
+ * @grange: linux gpio pin range supported by this controller.
+ */
+struct samsung_pinctrl_drv_data {
+	void __iomem			*virt_base;
+	struct device			*dev;
+	int				irq;
+
+	struct samsung_pin_ctrl		*ctrl;
+	struct pinctrl_desc		pctl;
+	struct pinctrl_dev		*pctl_dev;
+
+	const struct samsung_pin_group	*pin_groups;
+	unsigned int			nr_groups;
+	const struct samsung_pmx_func	*pmx_functions;
+	unsigned int			nr_functions;
+
+	struct irq_domain		*gpio_irqd;
+	struct irq_domain		*wkup_irqd;
+
+	struct gpio_chip		*gc;
+	struct pinctrl_gpio_range	grange;
+};
+
+/**
+ * struct samsung_pin_group: represent group of pins of a pinmux function.
+ * @name: name of the pin group, used to lookup the group.
+ * @pins: the pins included in this group.
+ * @num_pins: number of pins included in this group.
+ * @func: the function number to be programmed when selected.
+ */
+struct samsung_pin_group {
+	const char		*name;
+	const unsigned int	*pins;
+	unsigned int		num_pins;
+	unsigned int		func;
+};
+
+/**
+ * struct samsung_pmx_func: represent a pin function.
+ * @name: name of the pin function, used to lookup the function.
+ * @groups: one or more names of pin groups that provide this function.
+ * @num_groups: number of groups included in @groups.
+ */
+struct samsung_pmx_func {
+	const char		*name;
+	const char		**groups;
+	unsigned		num_groups;
+};
+
+extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
+
+#endif /* __PINCTRL_SAMSUNG_H */
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 15 15:57:35 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:27:35 +0530
Subject: [PATCH v2 3/4] gpio: exynos4: skip gpiolib registration if pinctrl
 driver is used
In-Reply-To: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345060656-32201-4-git-send-email-thomas.abraham@linaro.org>

Pinctrl driver, when enabled, registers all the gpio pins and hence the
registration of gpio pins by this driver can be skipped.

Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 drivers/gpio/gpio-samsung.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 92f7b2b..8e61053 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2734,6 +2734,27 @@ static __init void exynos4_gpiolib_init(void)
 	int group = 0;
 	void __iomem *gpx_base;
 
+#ifdef CONFIG_OF
+		/*
+		 * This gpio driver includes support for device tree support and
+		 * there are platforms using it. In order to maintain
+		 * compatibility with those platforms, and to allow non-dt
+		 * Exynos4210 platforms to use this gpiolib support, a check
+		 * is added to find out if there is a active pin-controller
+		 * driver support available. If it is available, this gpiolib
+		 * support is ignored and the gpiolib support available in
+		 * pin-controller driver is used. This is a temporary check and
+		 * will go away when all of the Exynos4210 platforms have
+		 * switched to using device tree and the pin-ctrl driver.
+		 */
+		struct device_node *pctrl_np;
+		const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+		pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat);
+		if (pctrl_np)
+			if (of_device_is_available(pctrl_np))
+				return -ENODEV;
+#endif
+
 	/* gpio part1 */
 	gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
 	if (gpio_base1 == NULL) {
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 15 15:57:36 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:27:36 +0530
Subject: [PATCH v2 4/4] ARM: EXYNOS: skip wakeup interrupt setup if pinctrl
 driver is used
In-Reply-To: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345060656-32201-5-git-send-email-thomas.abraham@linaro.org>

Pinctrl driver includes support for configuring the external wakeup
interrupts. On exynos platforms that use pinctrl driver, the setup
of wakeup interrupts in the exynos platform code can be skipped.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/common.c |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..ea3a85a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -980,6 +980,32 @@ static int __init exynos_init_irq_eint(void)
 {
 	int irq;
 
+#ifdef CONFIG_OF
+	/*
+	 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
+	 * functionality along with support for external gpio and wakeup
+	 * interrupts. If the samsung pinctrl driver is enabled and includes
+	 * the wakeup interrupt support, then the setting up external wakeup
+	 * interrupts here can be skipped. This check here is temporary to
+	 * allow exynos4 platforms that do not use Samsung pinctrl driver to
+	 * co-exist with platforms that do. When all of the Samsung Exynos4
+	 * platforms switch over to using the pinctrl driver, the wakeup
+	 * interrupt support code here can be completely removed.
+	 */
+	struct device_node *pctrl_np, *wkup_np;
+	const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+	const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
+
+	for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+		if (of_device_is_available(pctrl_np)) {
+			wkup_np = of_find_compatible_node(pctrl_np, NULL,
+							wkup_compat);
+			if (wkup_np)
+				return -ENODEV;
+		}
+	}
+#endif
+
 	if (soc_is_exynos5250())
 		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 	else
-- 
1.6.6.rc2



From bhelgaas at google.com  Wed Aug 15 15:42:39 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 15 Aug 2012 13:42:39 -0600
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <20120815192814.GA12870@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7v+i8i=mXCs7ZW8DtGTDN_4AEntwYLqGG8FcCzweySFg@mail.gmail.com>
 <20120815192814.GA12870@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo6cjOzJegJqXzmk59DChExcbLK1sOhwyAyQL4FZkTN21A@mail.gmail.com>

On Wed, Aug 15, 2012 at 1:28 PM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> On Wed, Aug 15, 2012 at 10:06:27AM -0700, Bjorn Helgaas wrote:
>> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
>> <thierry.reding at avionic-design.de> wrote:
>> > When using deferred driver probing, PCI host controller drivers may
>> > actually require this function after the init stage.
>> >
>> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>> > ---
>> > Changes in v3:
>> > - none
>> >
>> > Changes in v2:
>> > - use __devinit annotations
>>
>> Your original patch removed __init completely.  Here you change it to
>> __devinit.  That means we decide whether to discard the function based
>> on whether CONFIG_HOTPLUG is supported.  But I think your point is not
>> about hotplug; it's merely that we should be able to scan a PCI bus
>> after init-time.  We ought to be able to do a late PCI scan even if
>> hotplug is not supported.
>>
>> Therefore, I'd be inclined to remove __init completely unless you have
>> another reason for preferring __devinit.
>
> I thought __devinit would resolve to nothing if HOTPLUG is defined and
> __init otherwise. That seemed more appropriate. However you are right
> that it is useful to always have it available, so I'm fine with removing
> the annotations altogether. Do you want me to follow up with a patch? Or
> can you just take the first version? I'm not sure if it still applies.

You're right about how __devinit works.  It's just that I don't think
hotplug is actually relevant here.  We're trying to make
pci_fixup_irqs() work after init, whether it's because of hotplug or
simply because the arch scans host bridges after init.

I applied this to my "next" branch.  Thanks!

Bjorn


From catalin.marinas at arm.com  Wed Aug 15 15:53:12 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 15 Aug 2012 20:53:12 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120815190328.GA6714@quad.lixom.net>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <20120814230645.GA19607@quad.lixom.net> <20120815173711.GC14264@arm.com>
 <20120815190328.GA6714@quad.lixom.net>
Message-ID: <CAHkRjk4k0q9TuHqJMLtLy-wxFHN8xQEQERkpf2Qt_48+1Qwwgw@mail.gmail.com>

On 15 August 2012 20:03, Olof Johansson <olof at lixom.net> wrote:
> On Wed, Aug 15, 2012 at 06:37:11PM +0100, Catalin Marinas wrote:
>> If we add machine_desc structure back, we could print which machine was
>> matched. But so far I try to keep the SoC code to a minimum and just do
>> the probing later in the SoC code (of_find_matching_node). Ideally we
>> shouldn't have any SoC code and just keep code in drivers but we'll see
>> how far we can get. We can discuss more details at the KS as I would
>> like the arm-soc team to get involved here.
>
> Interesting approach, I wonder if it'll scale, in particular if it comes
> to needing to do early setup and init. For device-level setup, generic
> will probably work just fine. And if it doesn't, things can be changed
> later. So it sounds like a good start.
>
> Definitely something we should discuss. I suggest not doing it at KS
> though, since only half of the arm-soc team is invited there. So the
> ARM mini-summit or hallway around LPC is a better venue.

I was indeed thinking of the ARM mini-summit or hallway discussions.
The KS has different topics and it wouldn't have been of wide interest
anyway.

-- 
Catalin


From thomas.abraham at linaro.org  Wed Aug 15 16:10:40 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:40:40 +0530
Subject: [PATCH 0/2] Enable pinctrl driver support for Exynos4210 based
 platforms
Message-ID: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>

This patch series enables support for pin controller driver for Exynos4210 SoC
based device tree enabled platforms. The first patch in this series adds the
pin group nodes for each of the three pin controller instances, but it is not
a exhaustive list of all possible pin group nodes. As the coverage of pinctrl
driver is extended device drivers used on Exynos4210 platforms, additional
pin group nodes can be added as required.

Thomas Abraham (2):
  ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
  ARM: EXYNOS: Enable PINCTRL config option for Exynos4 device tree enabled platform

 arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
 arch/arm/mach-exynos/Kconfig              |    1 +
 3 files changed, 495 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi



From thomas.abraham at linaro.org  Wed Aug 15 16:10:42 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:40:42 +0530
Subject: [PATCH 2/2] ARM: EXYNOS: Enable PINCTRL config option for Exynos4
 device tree enabled platform
In-Reply-To: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345061442-32378-3-git-send-email-thomas.abraham@linaro.org>

This enables support for Samsung and Exynos4 pinctrl driver for device
tree enabled Exynos4 platforms.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..ad96c59 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -405,6 +405,7 @@ config MACH_EXYNOS4_DT
 	select USE_OF
 	select ARM_AMBA
 	select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+	select PINCTRL
 	help
 	  Machine support for Samsung Exynos4 machine with device tree enabled.
 	  Select this if a fdt blob is available for the Exynos4 SoC based board.
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 15 16:10:41 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 16 Aug 2012 01:40:41 +0530
Subject: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung Exynos4210
 SoC
In-Reply-To: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>

Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
 2 files changed, 494 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi

diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 0000000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl at 11400000 {
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <0x2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa0-4", "gpa0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_bus: i2c2-bus {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart2_data: uart2-data {
+			samsung,pins = "gpa1-0", "gpa1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart2_fctl: uart2-fctl {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart_audio_a: uart-audio-a {
+			samsung,pins = "gpa1-0", "gpa1-1";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c3_bus: i2c3-bus {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart3_data: uart3-data {
+			samsung,pins = "gpa1-4", "gpa1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart_audio_b: uart-audio-b {
+			samsung,pins = "gpa1-4", "gpa1-5";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi0_bus: spi0-bus {
+			samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c4_bus: i2c4-bus {
+			samsung,pins = "gpb-2", "gpb-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi1_bus: spi1-bus {
+			samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c5_bus: i2c5-bus {
+			samsung,pins = "gpb-6", "gpb-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s1_bus: i2s1-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm1_bus: pcm1-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		ac97_bus: ac97-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s2_bus: i2s2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm2_bus: pcm2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spdif_bus: spdif-bus {
+			samsung,pins = "gpc1-0", "gpc1-1";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c6_bus: i2c6-bus {
+			samsung,pins = "gpc1-3", "gpc1-4";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi2_bus: spi2-bus {
+			samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+			samsung,pin-function = <5>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c7_bus: i2c7-bus {
+			samsung,pins = "gpd0-2", "gpd0-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c0_bus: i2c0-bus {
+			samsung,pins = "gpd1-0", "gpd1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c1_bus: i2c1-bus {
+			samsung,pins = "gpd1-2", "gpd1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl at 11000000 {
+		sd0_clk: sd0-clk {
+			samsung,pins = "gpk0-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_cmd: sd0-cmd {
+			samsung,pins = "gpk0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_cd: sd0-cd {
+			samsung,pins = "gpk0-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus1: sd0-bus-width1 {
+			samsung,pins = "gpk0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus4: sd0-bus-width4 {
+			samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus8: sd0-bus-width8 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_clk: sd4-clk {
+			samsung,pins = "gpk0-0";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_cmd: sd4-cmd {
+			samsung,pins = "gpk0-1";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_cd: sd4-cd {
+			samsung,pins = "gpk0-2";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus1: sd4-bus-width1 {
+			samsung,pins = "gpk0-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus4: sd4-bus-width4 {
+			samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus8: sd4-bus-width8 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <4>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_clk: sd1-clk {
+			samsung,pins = "gpk1-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_cmd: sd1-cmd {
+			samsung,pins = "gpk1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_cd: sd1-cd {
+			samsung,pins = "gpk1-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_bus1: sd1-bus-width1 {
+			samsung,pins = "gpk1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_bus4: sd1-bus-width4 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_clk: sd2-clk {
+			samsung,pins = "gpk2-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_cmd: sd2-cmd {
+			samsung,pins = "gpk2-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_cd: sd2-cd {
+			samsung,pins = "gpk2-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus1: sd2-bus-width1 {
+			samsung,pins = "gpk2-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus4: sd2-bus-width4 {
+			samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus8: sd2-bus-width8 {
+			samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_clk: sd3-clk {
+			samsung,pins = "gpk3-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_cmd: sd3-cmd {
+			samsung,pins = "gpk3-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_cd: sd3-cd {
+			samsung,pins = "gpk3-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_bus1: sd3-bus-width1 {
+			samsung,pins = "gpk3-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_bus4: sd3-bus-width4 {
+			samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint0: ext-int0 {
+			samsung,pins = "gpx0-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint8: ext-int8 {
+			samsung,pins = "gpx1-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint15: ext-int15 {
+			samsung,pins = "gpx1-7";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint16: ext-int16 {
+			samsung,pins = "gpx2-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint31: ext-int31 {
+			samsung,pins = "gpx3-7";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl at 03860000 {
+		i2s0_bus: i2s0-bus {
+			samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+					"gpz-4", "gpz-5", "gpz-6";
+			samsung,pin-function = <0x2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm0_bus: pcm0-bus {
+			samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+					"gpz-4";
+			samsung,pin-function = <0x3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..a4bd0c9 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -20,6 +20,7 @@
 */
 
 /include/ "skeleton.dtsi"
+/include/ "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
@@ -29,6 +30,9 @@
 		spi0 = &spi_0;
 		spi1 = &spi_1;
 		spi2 = &spi_2;
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
 	};
 
 	gic:interrupt-controller at 10490000 {
@@ -50,6 +54,39 @@
 			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 	};
 
+	pinctrl_0: pinctrl at 11400000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	pinctrl_1: pinctrl at 11000000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+					<0 32 0>;
+		};
+	};
+
+	pinctrl_2: pinctrl at 03860000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x03860000 0x1000>;
+	};
+
 	watchdog at 10060000 {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x10060000 0x100>;
-- 
1.6.6.rc2



From thierry.reding at avionic-design.de  Wed Aug 15 16:01:16 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 22:01:16 +0200
Subject: [PATCH v3 01/10] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <CAErSpo6cjOzJegJqXzmk59DChExcbLK1sOhwyAyQL4FZkTN21A@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-2-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7v+i8i=mXCs7ZW8DtGTDN_4AEntwYLqGG8FcCzweySFg@mail.gmail.com>
 <20120815192814.GA12870@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6cjOzJegJqXzmk59DChExcbLK1sOhwyAyQL4FZkTN21A@mail.gmail.com>
Message-ID: <20120815200116.GB12870@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 01:42:39PM -0600, Bjorn Helgaas wrote:
> On Wed, Aug 15, 2012 at 1:28 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Wed, Aug 15, 2012 at 10:06:27AM -0700, Bjorn Helgaas wrote:
> >> On Thu, Jul 26, 2012 at 12:55 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > When using deferred driver probing, PCI host controller drivers may
> >> > actually require this function after the init stage.
> >> >
> >> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> >> > ---
> >> > Changes in v3:
> >> > - none
> >> >
> >> > Changes in v2:
> >> > - use __devinit annotations
> >>
> >> Your original patch removed __init completely.  Here you change it to
> >> __devinit.  That means we decide whether to discard the function based
> >> on whether CONFIG_HOTPLUG is supported.  But I think your point is not
> >> about hotplug; it's merely that we should be able to scan a PCI bus
> >> after init-time.  We ought to be able to do a late PCI scan even if
> >> hotplug is not supported.
> >>
> >> Therefore, I'd be inclined to remove __init completely unless you have
> >> another reason for preferring __devinit.
> >
> > I thought __devinit would resolve to nothing if HOTPLUG is defined and
> > __init otherwise. That seemed more appropriate. However you are right
> > that it is useful to always have it available, so I'm fine with removing
> > the annotations altogether. Do you want me to follow up with a patch? Or
> > can you just take the first version? I'm not sure if it still applies.
> 
> You're right about how __devinit works.  It's just that I don't think
> hotplug is actually relevant here.  We're trying to make
> pci_fixup_irqs() work after init, whether it's because of hotplug or
> simply because the arch scans host bridges after init.
> 
> I applied this to my "next" branch.  Thanks!

Great! Thanks. It's nice to see the patch series shrink. =)

Thierry
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From thierry.reding at avionic-design.de  Wed Aug 15 16:06:55 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 22:06:55 +0200
Subject: [PATCH v3 08/10] of/address: Handle #address-cells > 2 specially
In-Reply-To: <50183DA3.8020308@gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-9-git-send-email-thierry.reding@avionic-design.de>
 <50183DA3.8020308@gmail.com>
Message-ID: <20120815200655.GC12870@avionic-0098.mockup.avionic-design.de>

On Tue, Jul 31, 2012 at 03:18:43PM -0500, Rob Herring wrote:
> On 07/26/2012 02:55 PM, Thierry Reding wrote:
> > When a bus specifies #address-cells > 2, of_bus_default_map() now
> > assumes that the mapping isn't for a physical address but rather an
> > identifier that needs to match exactly.
> > 
> > This is required by bindings that use multiple cells to translate a
> > resource to the parent bus (device index, type, ...).
> > 
> > See here for the discussion:
> > 
> > 	https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-June/016577.html
> > 
> > Originally-by: Arnd Bergmann <arnd at arndb.de>
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> 
> Acked-by: Rob Herring <rob.herring at calxeda.com>

Hi Rob,

Were you going to take this through your DT tree? I'm trying to reduce
the number of patches in this series to make it more manageable and
split it into smaller chunks. There are also a couple of issues that
need to be resolved so I don't know if I can get the whole series into
shape for 3.7.

However if you don't think this patch is useful to be applied by itself
I can also carry it until the complete series is ready.

Thierry
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From thierry.reding at avionic-design.de  Wed Aug 15 16:09:05 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 22:09:05 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502BF2B4.9030401@wwwdotorg.org>
References: <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org> <502AE485.8060307@wwwdotorg.org>
 <502BF2B4.9030401@wwwdotorg.org>
Message-ID: <20120815200905.GD12870@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 01:04:20PM -0600, Stephen Warren wrote:
> On 08/14/2012 05:51 PM, Stephen Warren wrote:
> > On 08/14/2012 04:58 PM, Stephen Warren wrote:
> ...
> >> Can't we make the call to pci_bus_add_devices() optional in
> >> pci_scan_root_bus() somehow; one of:
> > 
> > Sigh, that turns out not to work correctly; it solves at least this part
> > of the problem when booting using device tree, but when booting using a
> > board file, it causes the IRQ number passed to the PCIe device to be
> > bogus:-(
> > 
> > I give up for now.
> 
> I think the appropriate workaround for Tegra in 3.6 is to simply make
> any drivers for PCIe-based devices be modules instead of built-in, as
> Thierry hinted at much earlier in the thread. I've validated that the
> Ethernet works just fine on TrimSlice with that change, booting v3.6-rc1
> using either board files or device tree.

That's certainly the easiest and least error-prone solution.

> For 3.7, we should continue the discussion about a real fix; I'll look
> into the change Bjorn requested and see if it works, although given that
> hacking pci_scan_root_bus as described immediately previously in this
> thread caused a regression when booting using a board file, and the fact
> that board files are no longer supported on Tegra, I'm not too confident
> in the outcome...

I don't understand this last part. If the problem is there when booting
from board files and the board files are removed, doesn't that remove
the problem as well? =)

Thierry
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From swarren at wwwdotorg.org  Wed Aug 15 16:11:10 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 15 Aug 2012 14:11:10 -0600
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <20120815200905.GD12870@avionic-0098.mockup.avionic-design.de>
References: <50201E1D.5060200@wwwdotorg.org>
 <20120813174003.GA2527@avionic-0098.mockup.avionic-design.de>
 <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org> <502AE485.8060307@wwwdotorg.org>
 <502BF2B4.9030401@wwwdotorg.org>
 <20120815200905.GD12870@avionic-0098.mockup.avionic-design.de>
Message-ID: <502C025E.6000009@wwwdotorg.org>

On 08/15/2012 02:09 PM, Thierry Reding wrote:
> On Wed, Aug 15, 2012 at 01:04:20PM -0600, Stephen Warren wrote:
>> On 08/14/2012 05:51 PM, Stephen Warren wrote:
>>> On 08/14/2012 04:58 PM, Stephen Warren wrote:
>> ...
>>>> Can't we make the call to pci_bus_add_devices() optional in 
>>>> pci_scan_root_bus() somehow; one of:
>>> 
>>> Sigh, that turns out not to work correctly; it solves at least
>>> this part of the problem when booting using device tree, but
>>> when booting using a board file, it causes the IRQ number
>>> passed to the PCIe device to be bogus:-(
>>> 
>>> I give up for now.
>> 
>> I think the appropriate workaround for Tegra in 3.6 is to simply
>> make any drivers for PCIe-based devices be modules instead of
>> built-in, as Thierry hinted at much earlier in the thread. I've
>> validated that the Ethernet works just fine on TrimSlice with
>> that change, booting v3.6-rc1 using either board files or device
>> tree.
> 
> That's certainly the easiest and least error-prone solution.
> 
>> For 3.7, we should continue the discussion about a real fix; I'll
>> look into the change Bjorn requested and see if it works,
>> although given that hacking pci_scan_root_bus as described
>> immediately previously in this thread caused a regression when
>> booting using a board file, and the fact that board files are no
>> longer supported on Tegra, I'm not too confident in the
>> outcome...
> 
> I don't understand this last part. If the problem is there when
> booting from board files and the board files are removed, doesn't
> that remove the problem as well? =)

It does for ARM SoCs/CPUs exclusively using device tree, but not all
ARM systems are converting to device tree, so the fact that Tegra has
makes it harder for me not to break anything else.


From rjw at sisk.pl  Wed Aug 15 16:23:17 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 15 Aug 2012 22:23:17 +0200
Subject: [PATCH] cpuidle: Prevent null pointer dereference in
 cpuidle_coupled_cpu_notify
In-Reply-To: <1344945151.2674.56.camel@linaro1.home>
References: <1344945151.2674.56.camel@linaro1.home>
Message-ID: <201208152223.17623.rjw@sisk.pl>

On Tuesday, August 14, 2012, Jon Medhurst (Tixy) wrote:
> When a kernel is built to support multiple hardware types it's possible
> that CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is set but the hardware the
> kernel is run on doesn't support cpuidle and therefore doesn't load a
> driver for it. In this case, when the system is shut down,
> cpuidle_coupled_cpu_notify() gets called with cpuidle_devices set to
> NULL. There are quite possibly other circumstances where this
> situation can also occur and we should check for it.
> 
> Signed-off-by: Jon Medhurst <tixy at linaro.org>

Applied to the linux-next branch of the linux-pm.git tree as v3.6 material.

Thanks,
Rafael


> ---
> 
> Would a better fix be to delay registering the notifier until
> cpuidle_coupled_register_device() is called? Though following through
> with that logic would require unregistering the notifier when cpuidle
> driver is unregistered and it still seems possible that there would
> still be a window of opportunity for things to go wrong.
> 
> 
>  drivers/cpuidle/coupled.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
> index 2c9bf26..c78a5ff 100644
> --- a/drivers/cpuidle/coupled.c
> +++ b/drivers/cpuidle/coupled.c
> @@ -681,7 +681,7 @@ static int cpuidle_coupled_cpu_notify(struct notifier_block *nb,
>  	mutex_lock(&cpuidle_lock);
>  
>  	dev = per_cpu(cpuidle_devices, cpu);
> -	if (!dev->coupled)
> +	if (!dev || !dev->coupled)
>  		goto out;
>  
>  	switch (action & ~CPU_TASKS_FROZEN) {
> 



From jason at lakedaemon.net  Wed Aug 15 16:19:49 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 16:19:49 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
Message-ID: <20120815201949.GI22226@titan.lakedaemon.net>

Alan,

Not too bad for your first go-round with git.  Some comments below.


On Wed, Aug 15, 2012 at 07:00:42PM +0100, alan butler wrote:
...
> i did what you sujested and all commands worked except for the git
> sendmail part so i do not know if I should still be sending you the
> patch this way but here it is. 

Please post the exact command you used and the complete error message it
gave you.

> i also defined the gpio keys in the dts
> file like you said the same as with the iconnect but the kernel keeps
> crashing with them defined in the dts is the support actualy there for
> the keys? or have i just defined them wrong?

Please post the exact error message from the kernel for this as well.

> 
> From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
> Message-Id: <cover.1345046444.git.alanbutty12 at gmail.com>
> From: Alan M Butler <alanbutty12 at gmail.com>
> Date: Wed, 15 Aug 2012 17:00:44 +0100
> Subject: [PATCH] *** SUBJECT HERE ***
> 
> *** BLURB HERE ***

Since this is a single patch, not a series, you can omit --cover-letter.

> Alan M Butler (1):
>   ARM: Kirkwood: Iomega_IX2_200     Signed-off-by: Alan M Butler
>     <alanbutty12 at gmail.com>
> 
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>  arch/arm/mach-kirkwood/Makefile               |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h               |    6 ++
>  7 files changed, 210 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> 
> -- 
> 1.7.5.4
> From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
> Message-Id: <f55ed67347f4b10ebbe2adc29d134acaf362279a.1345046444.git.alanbutty12 at gmail.com>
> In-Reply-To: <cover.1345046444.git.alanbutty12 at gmail.com>
> References: <cover.1345046444.git.alanbutty12 at gmail.com>
> From: Alan M Butler <alanbutty12 at gmail.com>
> Date: Wed, 15 Aug 2012 16:52:56 +0100
> Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 Signed-off-by: Alan M Butler
>  <alanbutty12 at gmail.com>

The 'git commit -s' automatically signs the commit properly.  So, you
shouldn't have to add the Signed-off-by: anywhere once you have git
send-email working.

btw - vvvv these are the '---' I was referring to.

> ---
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>  arch/arm/mach-kirkwood/Makefile               |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h               |    6 ++
>  7 files changed, 210 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> 
> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> new file mode 100644
> index 0000000..7863009
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> @@ -0,0 +1,111 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "Iomega StorCenter ix2-200";
> +	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x10000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	ocp at f1000000 {
> +		i2c at 11000 {
> +			status = "okay";
> +
> +			lm63: lm63 at 4c {
> +				compatible = "national,lm63";
> +				reg = <0x4c>;
> +			};
> +		};
> +
> +		serial at 12000 {
> +			clock-frequency = <200000000>;
> +			status = "ok";
> +		};
> +
> +		nand at 3000000 {
> +			status = "okay";
> +
> +			partition at 0 {
> +				label = "u-boot";
> +				reg = <0x0000000 0x100000>;
> +				read-only;
> +			};
> +
> +			partition at a0000 {
> +				label = "env";
> +				reg = <0xa0000 0x20000>;
> +			};
> +
> +			partition at 100000 {
> +				label = "uImage";
> +				reg = <0x100000 0x300000>;
> +				read-only;
> +			};
> +
> +			partition at 400000 {
> +				label = "uInitrd";
> +				reg = <0x540000 0x1000000>;
> +			};
> +		};
> +		sata at 80000 {
> +			compatible = "marvell,orion-sata";
> +			reg = <0x80000 0x5000>;
> +			interrupts = <21>;
> +			status = "okay";
> +			nr-ports = <2>;
> +		};
> +
> +	};
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		power_led {
> +			label = "status:white:power_led";
> +			gpios = <&gpio0 16 0>;
> +			linux,default-trigger = "default-on";
> +		};
> +		rebuild_led {
> +			label = "status:white:rebuild_led";
> +			gpios = <&gpio1 5 0>;
> +		};
> +		health_led {
> +			label = "status:red:health_led";
> +			gpios = <&gpio1 6 0>;
> +		};
> +		backup_led {
> +			label = "status:blue:backup_led";
> +			gpios = <&gpio0 15 0>;
> +		};
> +	};
> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		button at 1 {
> +			label = "OTB Button";
> +			linux,code = <0x00>;
> +			gpios = <&gpio1 4 1>;
> +			debounce-interval = <100>;
> +		};
> +		button at 2 {
> +			label = "Reset";
> +			linux,code = <0x01>;
> +			gpios = <&gpio0 12 1>;
> +			debounce-interval = <100>;
> +		};
> +		button at 3 {
> +			label = "Power";
> +			linux,code = <0x028>;
> +			gpios = <&gpio0 14 1>;
> +			debounce-interval = <100>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index ca5c15a..bee8451 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -195,6 +195,13 @@ config MACH_T5325
>  	  Say 'Y' here if you want your kernel to support the
>  	  HP t5325 Thin Client.
> 
> +config MACH_IOMEGA_IX2_200_DT
> +	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Iomega StorCenter ix2-200 (Flattened Device Tree).
> +
>  endmenu
> 
>  endif
> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
> index 055c85a..f5484dc 100644
> --- a/arch/arm/mach-kirkwood/Makefile
> +++ b/arch/arm/mach-kirkwood/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
>  obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
>  obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
>  obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot
> b/arch/arm/mach-kirkwood/Makefile.boot
> index 2a576ab..f8ef771 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
> diff --git a/arch/arm/mach-kirkwood/board-dt.c
> b/arch/arm/mach-kirkwood/board-dt.c
> index e4eb450..a932ae9 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>  	if (of_machine_is_compatible("buffalo,lsxl"))
>  		lsxl_init();
> 
> +	if (of_machine_is_compatible("iom,ix2-200"))
> +		iomega_ix2_200_init()
> +
>  	of_platform_populate(NULL, kirkwood_dt_match_table,
>  			     kirkwood_auxdata_lookup, NULL);
>  }
> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>  	"qnap,ts219",
>  	"seagate,goflexnet",
>  	"buffalo,lsxl",
> +	"iom,ix2-200",
>  	NULL
>  };
> 
> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> new file mode 100644
> index 0000000..a6bb98e
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> @@ -0,0 +1,80 @@
> +/*
> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> + *
> + * Iomega StorCenter ix2-200
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/irq.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/ata_platform.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/ethtool.h>
> +#include <net/dsa.h>
> +#include <linux/gpio.h>
> +#include <linux/leds.h>
> +#include <linux/i2c.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <mach/kirkwood.h>
> +#include "common.h"
> +#include "mpp.h"
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> +	.phy_addr       = MV643XX_ETH_PHY_NONE,
> +	.speed          = SPEED_1000,
> +	.duplex         = DUPLEX_FULL,
> +};
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
> +};
> +
> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
> +	MPP12_GPIO,			/* Reset Button */
> +	MPP14_GPIO,			/* Power Button */
> +	MPP15_GPIO,			/* Backup LED (blue) */
> +	MPP16_GPIO,			/* Power LED (white) */
> +	MPP35_GPIO,			/* OTB Button */
> +	MPP36_GPIO,			/* Rebuild LED (white) */
> +	MPP37_GPIO,			/* Health LED (red) */
> +	MPP38_GPIO,			/* SATA LED brightness control 1 */
> +	MPP39_GPIO,			/* SATA LED brightness control 2 */
> +	MPP40_GPIO,			/* Backup LED brightness control 1 */
> +	MPP41_GPIO,			/* Backup LED brightness control 2 */
> +	MPP42_GPIO,			/* Power LED brightness control 1 */
> +	MPP43_GPIO,			/* Power LED brightness control 2 */
> +	MPP44_GPIO,			/* Health LED brightness control 1 */
> +	MPP45_GPIO,			/* Health LED brightness control 2 */
> +	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
> +	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
> +	0
> +};
> +
> +void __init iomega_ix2_200_init(void)
> +{
> +	/*
> +	 * Basic setup. Needs to be called early.
> +	 */
> +	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
> +
> +	kirkwood_ehci_init();
> +
> +	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
> +	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
> +}
> +
> +static int __init iomega_ix2_200_pci_init(void)
> +{
> +	if (of_machine_is_compatible("iom,ix2-200"))
> +		kirkwood_pcie_init(KW_PCIE0);
> +	return 0;
> +}
> +subsys_initcall(iomega_ix2_200_pci_init);
> +
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index 304dd1a..d5d4064 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -94,6 +94,12 @@ void lsxl_init(void);
>  static inline void lsxl_init(void) {};
>  #endif
> 
> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
> +void iomega_ix2_200_init(void);
> +#else
> +static inline void iomega_ix2_200_init(void) {};
> +#endif
> +
>  /* early init functions not converted to fdt yet */
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

Please remove this line ^^^.  It isn't valid C ;-)  See my comment
above.

thx,

Jason.


From thierry.reding at avionic-design.de  Wed Aug 15 16:19:56 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 15 Aug 2012 22:19:56 +0200
Subject: [PATCH v3 00/10] ARM: tegra: Add PCIe device tree support
In-Reply-To: <502C025E.6000009@wwwdotorg.org>
References: <50294BCA.1070807@wwwdotorg.org>
 <CAErSpo7og1XgOSv_mFCQ=hP7pq0j3gXWh2QFL2wBJjz7kcAq=g@mail.gmail.com>
 <502AA96B.2050709@wwwdotorg.org>
 <20120814195834.GA10431@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Bm_Ryx=OK+svjqAwD4N8v0vrheLVdc-N1ijx8i_-N3w@mail.gmail.com>
 <502AD82F.3080702@wwwdotorg.org> <502AE485.8060307@wwwdotorg.org>
 <502BF2B4.9030401@wwwdotorg.org>
 <20120815200905.GD12870@avionic-0098.mockup.avionic-design.de>
 <502C025E.6000009@wwwdotorg.org>
Message-ID: <20120815201956.GG12870@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 02:11:10PM -0600, Stephen Warren wrote:
> On 08/15/2012 02:09 PM, Thierry Reding wrote:
> > On Wed, Aug 15, 2012 at 01:04:20PM -0600, Stephen Warren wrote:
> >> On 08/14/2012 05:51 PM, Stephen Warren wrote:
> >>> On 08/14/2012 04:58 PM, Stephen Warren wrote:
> >> ...
> >>>> Can't we make the call to pci_bus_add_devices() optional in 
> >>>> pci_scan_root_bus() somehow; one of:
> >>> 
> >>> Sigh, that turns out not to work correctly; it solves at least
> >>> this part of the problem when booting using device tree, but
> >>> when booting using a board file, it causes the IRQ number
> >>> passed to the PCIe device to be bogus:-(
> >>> 
> >>> I give up for now.
> >> 
> >> I think the appropriate workaround for Tegra in 3.6 is to simply
> >> make any drivers for PCIe-based devices be modules instead of
> >> built-in, as Thierry hinted at much earlier in the thread. I've
> >> validated that the Ethernet works just fine on TrimSlice with
> >> that change, booting v3.6-rc1 using either board files or device
> >> tree.
> > 
> > That's certainly the easiest and least error-prone solution.
> > 
> >> For 3.7, we should continue the discussion about a real fix; I'll
> >> look into the change Bjorn requested and see if it works,
> >> although given that hacking pci_scan_root_bus as described
> >> immediately previously in this thread caused a regression when
> >> booting using a board file, and the fact that board files are no
> >> longer supported on Tegra, I'm not too confident in the
> >> outcome...
> > 
> > I don't understand this last part. If the problem is there when
> > booting from board files and the board files are removed, doesn't
> > that remove the problem as well? =)
> 
> It does for ARM SoCs/CPUs exclusively using device tree, but not all
> ARM systems are converting to device tree, so the fact that Tegra has
> makes it harder for me not to break anything else.

I think the best road to a real fix would be to implement a custom scan
function for Tegra along the lines of what Bjorn suggested. Ideally,
this implementation should eventually converge to what's done on other
architectures. At that point maybe ARM can completely be converted to
this new generic implementation and the Tegra-specific hook removed.

Thierry
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From wade_farnsworth at mentor.com  Wed Aug 15 16:21:35 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Wed, 15 Aug 2012 13:21:35 -0700
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <502BFA08.6010708@mentor.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
 <502BD544.70903@mentor.com>
 <20120815172731.GL29448@mudshark.cambridge.arm.com>
 <502BFA08.6010708@mentor.com>
Message-ID: <502C04CF.2080409@mentor.com>

Wade Farnsworth wrote:
> Will Deacon wrote:
>> On Wed, Aug 15, 2012 at 05:58:44PM +0100, Wade Farnsworth wrote:
>>> We need to set current_thread_info()->syscall, since it's used in the
>>> call to syscall_get_nr() in perf_syscall_{enter,exit}.
>>
>> Damn. I think that also means we have a bug, given that the SYSCALL_TRACE
>> code can set this to -1, which gets used as an index into a bitmap by the
>> looks of it. Considering that we have to pass the syscall number to
>> trace_sys_enter anyway, it also seems broken.
>>
>
> I agree. Looking at the other architectures, it seems the analogous
> function to ptrace_syscall_trace can return -1 under certain
> circumstances, but the original syscall value should be passed onto
> trace_sys_enter and returned from syscall_get_nr(). So, I'm thinking
> that we should modify our behavior accordingly. What this means for us
> is that we never store -1 in the thread_info syscall field, and then
> pass that into trace_sys_enter instead of the ptrace_syscall_trace
> return value. Do you see any problems with this approach?
>

Hmm, on closer inspection it looks that perf_syscall_enter is broken. 
ftrace_syscall_enter correctly returns if result of a syscall_get_nr is 
negative.  The perf version omits the check for negative values. 
Furthermore, the value of syscall_get_nr() should be -1 if it's not 
called when not in a syscall.  So storing the -1 in the thread_info 
syscall field is not necessarily wrong.  Still, I think the value we 
pass into trace_sys_enter should be the actual syscall number, i.e. the 
value of scno.

>>> What about moving the setting of ->syscall to
>>> syscall_trace_{enter,exit}? That would preserve ptrace_syscall_trace()
>>> for the TIF_SYSCALL_TRACE case only, but ensure that the field is set
>>> the TRACEPOINT case as well. Thoughts?
>>
>> I'd be tempted to set the thing unconditionally before checking the
>> thread
>> flag at the top of ptrace_syscall_trace. This hangs off the slowpath
>> anyway
>> and it makes everything a lot more readable.
>>
>
> OK, I'll make that change.
>
> Wade



From arnd at arndb.de  Wed Aug 15 16:25:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 15 Aug 2012 20:25:25 +0000
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120815145708.GA11331@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>
 <20120815145708.GA11331@avionic-0098.mockup.avionic-design.de>
Message-ID: <201208152025.25252.arnd@arndb.de>

On Wednesday 15 August 2012, Thierry Reding wrote:
> Yes, that was my understanding as well. So currently I haven't seen any
> problems with this because I only use one of the two host bridges. But I
> suppose I should add code to initialize the bus number aperture properly
> either via platform device resources (for the non-DT case) and the
> device tree otherwise.

I think when we last discussed this, the assumption was that each
root port has its own config space range and its own pci domain,
so you don't have to worry about bus apertures because each root port
can then have all 255 bus numbers. Has that turned out to be incorrect
now?

	Arnd


From akpm at linux-foundation.org  Wed Aug 15 16:32:21 2012
From: akpm at linux-foundation.org (Andrew Morton)
Date: Wed, 15 Aug 2012 13:32:21 -0700
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20120815141606.GA2457@S2101-09.ap.freescale.net>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
 <20120815141606.GA2457@S2101-09.ap.freescale.net>
Message-ID: <20120815133221.ca88d4ba.akpm@linux-foundation.org>

On Wed, 15 Aug 2012 22:16:10 +0800
Shawn Guo <shawn.guo at linaro.org> wrote:

> Thanks for looking at the patch, Andrew.
> 
> On Tue, Aug 14, 2012 at 05:03:00PM -0700, Andrew Morton wrote:
> > On Fri, 13 Jul 2012 15:31:03 +0800
> > Shawn Guo <shawn.guo at linaro.org> wrote:
> > 
> > > +static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
> > > +{
> > > +	unsigned long timeout = jiffies + msecs_to_jiffies(1);
> > > +	unsigned long flags;
> > > +	u32 lpcr;
> > > +
> > > +	spin_lock_irqsave(&data->lock, flags);
> > > +
> > > +	lpcr = readl(data->ioaddr + SNVS_LPCR);
> > > +	if (enable)
> > > +		lpcr |= SNVS_LPCR_SRTC_ENV;
> > > +	else
> > > +		lpcr &= ~SNVS_LPCR_SRTC_ENV;
> > > +	writel(lpcr, data->ioaddr + SNVS_LPCR);
> > > +
> > > +	spin_unlock_irqrestore(&data->lock, flags);
> > > +
> > > +	while (1) {
> > > +		lpcr = readl(data->ioaddr + SNVS_LPCR);
> > > +
> > > +		if (enable) {
> > > +			if (lpcr & SNVS_LPCR_SRTC_ENV)
> > > +				break;
> > > +		} else {
> > > +			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
> > > +				break;
> > > +		}
> > > +
> > > +		if (time_after(jiffies, timeout))
> > > +			return -ETIMEDOUT;
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > 
> > The timeout code here is fragile.  If acquiring the spinlock takes more
> > than a millisecond or if this thread gets interrupted or preempted then
> > we could easily execute that loop just a single time, and fail.
> > 
> So what about moving the timeout initialization to right above the
> while(1) loop?

It still has the same problem - a well-timed preemption would cause a
timeout.

> > It would be better to retry a fixed number of times, say 1000?  That
> > would take around 1 millisecond, but might be overkill.
> > 
> How long a 1000 times loop takes really depends on the cpu frequency,
> right?

No, it will depend on the preiod of that readl(), which typically takes
much much longer than a cpu cycle.  It depends a lot on the bus type
but I'd guess that the readl would take 100's of nanoseconds.  Thus we
can use the expected readl duration to control the timeout interval.

> BTW, I have received the notification telling that the patch has been
> applied on -mm tree.  So should I just send you an incremental patch
> to address the comment?

An incremental is nice, as it lets people see what changed.  A full
replacement is OK for me as well - I turn it into an incrememntal so
that I and others can review the change and I fold the two back
together again before sending the patch to someone else (in this case,
Linus).




From bhelgaas at google.com  Wed Aug 15 16:48:15 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 15 Aug 2012 14:48:15 -0600
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <201208152025.25252.arnd@arndb.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>
 <20120815145708.GA11331@avionic-0098.mockup.avionic-design.de>
 <201208152025.25252.arnd@arndb.de>
Message-ID: <CAErSpo7=_zzNCXujq-XJjcb=3wMkUPyUeyQSQ6G59Q-Q6VLd3g@mail.gmail.com>

On Wed, Aug 15, 2012 at 2:25 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 15 August 2012, Thierry Reding wrote:
>> Yes, that was my understanding as well. So currently I haven't seen any
>> problems with this because I only use one of the two host bridges. But I
>> suppose I should add code to initialize the bus number aperture properly
>> either via platform device resources (for the non-DT case) and the
>> device tree otherwise.
>
> I think when we last discussed this, the assumption was that each
> root port has its own config space range and its own pci domain,
> so you don't have to worry about bus apertures because each root port
> can then have all 255 bus numbers. Has that turned out to be incorrect
> now?

If that's the case, there's no problem.  I just want to be explicit
about the host bridge bus number aperture because I'd like to make
pci_scan_root_bus() fail if no aperture is supplied or if the aperture
overlaps with something we've already seen.  I don't know if that
means you want to add a domain and [bus 00-ff] range in device tree,
or if you want to make some device tree rule about every host bridge
being in its own domain, or what.

Bjorn


From alanbutty12 at gmail.com  Wed Aug 15 16:56:29 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Wed, 15 Aug 2012 20:56:29 +0000
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815201949.GI22226@titan.lakedaemon.net>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815201949.GI22226@titan.lakedaemon.net>
Message-ID: <CADhrpJ4kqpxJrBFPD4o=B3ni=ZUX3EdjBW30k9HxazEB75RMPg@mail.gmail.com>

On 15 August 2012 21:19, Jason Cooper <jason at lakedaemon.net> wrote:
> Alan,
>
> Not too bad for your first go-round with git.  Some comments below.
>
>
> On Wed, Aug 15, 2012 at 07:00:42PM +0100, alan butler wrote:
> ...
>> i did what you sujested and all commands worked except for the git
>> sendmail part so i do not know if I should still be sending you the
>> patch this way but here it is.
>
> Please post the exact command you used and the complete error message it
> gave you.
>
>> i also defined the gpio keys in the dts
>> file like you said the same as with the iconnect but the kernel keeps
>> crashing with them defined in the dts is the support actualy there for
>> the keys? or have i just defined them wrong?
>
> Please post the exact error message from the kernel for this as well.
>
>>
>> From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
>> Message-Id: <cover.1345046444.git.alanbutty12 at gmail.com>
>> From: Alan M Butler <alanbutty12 at gmail.com>
>> Date: Wed, 15 Aug 2012 17:00:44 +0100
>> Subject: [PATCH] *** SUBJECT HERE ***
>>
>> *** BLURB HERE ***
>
> Since this is a single patch, not a series, you can omit --cover-letter.
>
>> Alan M Butler (1):
>>   ARM: Kirkwood: Iomega_IX2_200     Signed-off-by: Alan M Butler
>>     <alanbutty12 at gmail.com>
>>
>>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
>>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>>  arch/arm/mach-kirkwood/Makefile               |    1 +
>>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
>>  arch/arm/mach-kirkwood/common.h               |    6 ++
>>  7 files changed, 210 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>
>> --
>> 1.7.5.4
>> From f55ed67347f4b10ebbe2adc29d134acaf362279a Mon Sep 17 00:00:00 2001
>> Message-Id: <f55ed67347f4b10ebbe2adc29d134acaf362279a.1345046444.git.alanbutty12 at gmail.com>
>> In-Reply-To: <cover.1345046444.git.alanbutty12 at gmail.com>
>> References: <cover.1345046444.git.alanbutty12 at gmail.com>
>> From: Alan M Butler <alanbutty12 at gmail.com>
>> Date: Wed, 15 Aug 2012 16:52:56 +0100
>> Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 Signed-off-by: Alan M Butler
>>  <alanbutty12 at gmail.com>
>
> The 'git commit -s' automatically signs the commit properly.  So, you
> shouldn't have to add the Signed-off-by: anywhere once you have git
> send-email working.
>
> btw - vvvv these are the '---' I was referring to.
>
>> ---
>>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  111 +++++++++++++++++++++++++
>>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>>  arch/arm/mach-kirkwood/Makefile               |    1 +
>>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   80 ++++++++++++++++++
>>  arch/arm/mach-kirkwood/common.h               |    6 ++
>>  7 files changed, 210 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>
>> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> new file mode 100644
>> index 0000000..7863009
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> @@ -0,0 +1,111 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +     model = "Iomega StorCenter ix2-200";
>> +     compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>> +
>> +     memory {
>> +             device_type = "memory";
>> +             reg = <0x00000000 0x10000000>;
>> +     };
>> +
>> +     chosen {
>> +             bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +     };
>> +
>> +     ocp at f1000000 {
>> +             i2c at 11000 {
>> +                     status = "okay";
>> +
>> +                     lm63: lm63 at 4c {
>> +                             compatible = "national,lm63";
>> +                             reg = <0x4c>;
>> +                     };
>> +             };
>> +
>> +             serial at 12000 {
>> +                     clock-frequency = <200000000>;
>> +                     status = "ok";
>> +             };
>> +
>> +             nand at 3000000 {
>> +                     status = "okay";
>> +
>> +                     partition at 0 {
>> +                             label = "u-boot";
>> +                             reg = <0x0000000 0x100000>;
>> +                             read-only;
>> +                     };
>> +
>> +                     partition at a0000 {
>> +                             label = "env";
>> +                             reg = <0xa0000 0x20000>;
>> +                     };
>> +
>> +                     partition at 100000 {
>> +                             label = "uImage";
>> +                             reg = <0x100000 0x300000>;
>> +                             read-only;
>> +                     };
>> +
>> +                     partition at 400000 {
>> +                             label = "uInitrd";
>> +                             reg = <0x540000 0x1000000>;
>> +                     };
>> +             };
>> +             sata at 80000 {
>> +                     compatible = "marvell,orion-sata";
>> +                     reg = <0x80000 0x5000>;
>> +                     interrupts = <21>;
>> +                     status = "okay";
>> +                     nr-ports = <2>;
>> +             };
>> +
>> +     };
>> +     gpio-leds {
>> +             compatible = "gpio-leds";
>> +
>> +             power_led {
>> +                     label = "status:white:power_led";
>> +                     gpios = <&gpio0 16 0>;
>> +                     linux,default-trigger = "default-on";
>> +             };
>> +             rebuild_led {
>> +                     label = "status:white:rebuild_led";
>> +                     gpios = <&gpio1 5 0>;
>> +             };
>> +             health_led {
>> +                     label = "status:red:health_led";
>> +                     gpios = <&gpio1 6 0>;
>> +             };
>> +             backup_led {
>> +                     label = "status:blue:backup_led";
>> +                     gpios = <&gpio0 15 0>;
>> +             };
>> +     };
>> +     gpio_keys {
>> +             compatible = "gpio-keys";
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             button at 1 {
>> +                     label = "OTB Button";
>> +                     linux,code = <0x00>;
>> +                     gpios = <&gpio1 4 1>;
>> +                     debounce-interval = <100>;
>> +             };
>> +             button at 2 {
>> +                     label = "Reset";
>> +                     linux,code = <0x01>;
>> +                     gpios = <&gpio0 12 1>;
>> +                     debounce-interval = <100>;
>> +             };
>> +             button at 3 {
>> +                     label = "Power";
>> +                     linux,code = <0x028>;
>> +                     gpios = <&gpio0 14 1>;
>> +                     debounce-interval = <100>;
>> +             };
>> +     };
>> +};
>> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
>> index ca5c15a..bee8451 100644
>> --- a/arch/arm/mach-kirkwood/Kconfig
>> +++ b/arch/arm/mach-kirkwood/Kconfig
>> @@ -195,6 +195,13 @@ config MACH_T5325
>>         Say 'Y' here if you want your kernel to support the
>>         HP t5325 Thin Client.
>>
>> +config MACH_IOMEGA_IX2_200_DT
>> +     bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
>> +     select ARCH_KIRKWOOD_DT
>> +     help
>> +       Say 'Y' here if you want your kernel to support the
>> +       Iomega StorCenter ix2-200 (Flattened Device Tree).
>> +
>>  endmenu
>>
>>  endif
>> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
>> index 055c85a..f5484dc 100644
>> --- a/arch/arm/mach-kirkwood/Makefile
>> +++ b/arch/arm/mach-kirkwood/Makefile
>> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)                += board-ib62x0.o
>>  obj-$(CONFIG_MACH_TS219_DT)          += board-ts219.o tsx1x-common.o
>>  obj-$(CONFIG_MACH_GOFLEXNET_DT)              += board-goflexnet.o
>>  obj-$(CONFIG_MACH_LSXL_DT)           += board-lsxl.o
>> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
>> diff --git a/arch/arm/mach-kirkwood/Makefile.boot
>> b/arch/arm/mach-kirkwood/Makefile.boot
>> index 2a576ab..f8ef771 100644
>> --- a/arch/arm/mach-kirkwood/Makefile.boot
>> +++ b/arch/arm/mach-kirkwood/Makefile.boot
>> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb
>>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
>> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
>> diff --git a/arch/arm/mach-kirkwood/board-dt.c
>> b/arch/arm/mach-kirkwood/board-dt.c
>> index e4eb450..a932ae9 100644
>> --- a/arch/arm/mach-kirkwood/board-dt.c
>> +++ b/arch/arm/mach-kirkwood/board-dt.c
>> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>>       if (of_machine_is_compatible("buffalo,lsxl"))
>>               lsxl_init();
>>
>> +     if (of_machine_is_compatible("iom,ix2-200"))
>> +             iomega_ix2_200_init()
>> +
>>       of_platform_populate(NULL, kirkwood_dt_match_table,
>>                            kirkwood_auxdata_lookup, NULL);
>>  }
>> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>>       "qnap,ts219",
>>       "seagate,goflexnet",
>>       "buffalo,lsxl",
>> +     "iom,ix2-200",
>>       NULL
>>  };
>>
>> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> new file mode 100644
>> index 0000000..a6bb98e
>> --- /dev/null
>> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> @@ -0,0 +1,80 @@
>> +/*
>> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> + *
>> + * Iomega StorCenter ix2-200
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/irq.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/ata_platform.h>
>> +#include <linux/mv643xx_eth.h>
>> +#include <linux/ethtool.h>
>> +#include <net/dsa.h>
>> +#include <linux/gpio.h>
>> +#include <linux/leds.h>
>> +#include <linux/i2c.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <mach/kirkwood.h>
>> +#include "common.h"
>> +#include "mpp.h"
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
>> +     .phy_addr       = MV643XX_ETH_PHY_NONE,
>> +     .speed          = SPEED_1000,
>> +     .duplex         = DUPLEX_FULL,
>> +};
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
>> +     .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
>> +};
>> +
>> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
>> +     MPP12_GPIO,                     /* Reset Button */
>> +     MPP14_GPIO,                     /* Power Button */
>> +     MPP15_GPIO,                     /* Backup LED (blue) */
>> +     MPP16_GPIO,                     /* Power LED (white) */
>> +     MPP35_GPIO,                     /* OTB Button */
>> +     MPP36_GPIO,                     /* Rebuild LED (white) */
>> +     MPP37_GPIO,                     /* Health LED (red) */
>> +     MPP38_GPIO,                     /* SATA LED brightness control 1 */
>> +     MPP39_GPIO,                     /* SATA LED brightness control 2 */
>> +     MPP40_GPIO,                     /* Backup LED brightness control 1 */
>> +     MPP41_GPIO,                     /* Backup LED brightness control 2 */
>> +     MPP42_GPIO,                     /* Power LED brightness control 1 */
>> +     MPP43_GPIO,                     /* Power LED brightness control 2 */
>> +     MPP44_GPIO,                     /* Health LED brightness control 1 */
>> +     MPP45_GPIO,                     /* Health LED brightness control 2 */
>> +     MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
>> +     MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
>> +     0
>> +};
>> +
>> +void __init iomega_ix2_200_init(void)
>> +{
>> +     /*
>> +      * Basic setup. Needs to be called early.
>> +      */
>> +     kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
>> +
>> +     kirkwood_ehci_init();
>> +
>> +     kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
>> +     kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
>> +}
>> +
>> +static int __init iomega_ix2_200_pci_init(void)
>> +{
>> +     if (of_machine_is_compatible("iom,ix2-200"))
>> +             kirkwood_pcie_init(KW_PCIE0);
>> +     return 0;
>> +}
>> +subsys_initcall(iomega_ix2_200_pci_init);
>> +
>> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
>> index 304dd1a..d5d4064 100644
>> --- a/arch/arm/mach-kirkwood/common.h
>> +++ b/arch/arm/mach-kirkwood/common.h
>> @@ -94,6 +94,12 @@ void lsxl_init(void);
>>  static inline void lsxl_init(void) {};
>>  #endif
>>
>> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
>> +void iomega_ix2_200_init(void);
>> +#else
>> +static inline void iomega_ix2_200_init(void) {};
>> +#endif
>> +
>>  /* early init functions not converted to fdt yet */
>>  char *kirkwood_id(void);
>>  void kirkwood_l2_init(void);
>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>
> Please remove this line ^^^.  It isn't valid C ;-)  See my comment
> above.
>
> thx,
>
> Jason.
Thanks yeah first time using git first time trying to create a real
patch for linux (and learning how in the process) and trying to figure
out this device tree stuff.

As far as i can tell from looking at the iconnect button definition's
that part is correct (except for the proper codes to do what the
buttons should actually do) the error i get is:

[    5.976074] Key type dns_resolver registered
[    5.981782] Unable to handle kernel NULL pointer dereference at
virtual address 00000004
[    5.989932] pgd = c0004000
[    5.992649] [00000004] *pgd=00000000
[    5.996247] Internal error: Oops: 805 [#1] ARM
[    6.000707] Modules linked in:
[    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
[    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
[    6.014471] LR is at of_get_named_gpio_flags+0x90/0xb4
[    6.019634] pc : [<c02e3190>]    lr : [<c0191a80>]    psr: 60000013
[    6.019634] sp : cf82feb8  ip : 00000001  fp : cf867400
[    6.031158] r10: cf867408  r9 : 00000028  r8 : 00000000
[    6.036400] r7 : c07ebde0  r6 : c07ebe64  r5 : 00000000  r4 : ceff7600
[    6.042958] r3 : 00000001  r2 : c042e57c  r1 : 00000000  r0 : 00000023
[    6.049516] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    6.056857] Control: 0005397f  Table: 0eff8000  DAC: 00000017
[    6.062629] Process swapper (pid: 1, stack limit = 0xcf82e270)
[    6.068481] Stack: (0xcf82feb8 to 0xcf830000)
[    6.072851] fea0:
    00000000 cefff380
[    6.081071] fec0: cf865b40 c00e88f8 cf84e080 00000000 cf808bac
00000003 cf865b40 00000001
[    6.089286] fee0: cf86743c cf867408 cf86743c c04476cc c04476cc
00000034 c041d318 c03fb208
[    6.097500] ff00: 00000000 c01c7ccc c01c7cb8 c01c6dc4 00000000
cf867408 cf86743c c04476cc
[    6.105713] ff20: 00000000 c01c6f5c c04476cc cf82ff38 c01c6efc
c01c58b4 cf808b8c cf8641b0
[    6.113928] ff40: c04476cc c04476cc ceffe300 c0442d18 00000000
c01c654c c03aa8b2 c03aa8b3
[    6.122141] ff60: c04476cc c0412e40 00000000 c0451300 00000034
c01c7208 00000000 00000007
[    6.130355] ff80: c0412e40 00000000 c0451300 00000034 c03fb208
c0008554 00000007 00000007
[    6.138570] ffa0: 00000000 00000007 c0419614 00000007 c0419618
c04195f8 c0451300 00000034
[    6.146784] ffc0: c041d318 c03fb894 00000007 00000007 c03fb208
00000000 00000000 c03fb77c
[    6.154999] ffe0: c000a004 00000013 00000000 00000000 00000000
c000a004 80040038 08040038
[    6.163226] [<c02e3190>] (gpio_keys_probe+0x110/0x6d4) from
[<c01c7ccc>] (platform_drv_probe+0x14/0x18)
[    6.172676] [<c01c7ccc>] (platform_drv_probe+0x14/0x18) from
[<c01c6dc4>] (driver_probe_device+0xb8/0x1f0)
[    6.182385] [<c01c6dc4>] (driver_probe_device+0xb8/0x1f0) from
[<c01c6f5c>] (__driver_attach+0x60/0x84)
[    6.191827] [<c01c6f5c>] (__driver_attach+0x60/0x84) from
[<c01c58b4>] (bus_for_each_dev+0x4c/0x78)
[    6.200922] [<c01c58b4>] (bus_for_each_dev+0x4c/0x78) from
[<c01c654c>] (bus_add_driver+0xa8/0x21c)
[    6.210017] [<c01c654c>] (bus_add_driver+0xa8/0x21c) from
[<c01c7208>] (driver_register+0x9c/0x138)
[    6.219112] [<c01c7208>] (driver_register+0x9c/0x138) from
[<c0008554>] (do_one_initcall+0x90/0x168)
[    6.228294] [<c0008554>] (do_one_initcall+0x90/0x168) from
[<c03fb894>] (kernel_init+0x118/0x1d8)
[    6.237215] [<c03fb894>] (kernel_init+0x118/0x1d8) from
[<c000a004>] (kernel_thread_exit+0x0/0x8)
[    6.246130] Code: e5945000 ebfaba19 e0255899 e59d3024 (e5850004)
[    6.252273] ---[ end trace 192fd8390b667beb ]---
[    6.256946] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b


and as for the git command i tried and what it tells me this is what i get:

git send-email --to="alanbutty12 at gmail.com" --smtp-server=Gmail
--no-chain-reply-to --from="alanbutty12 at gmail.com"
/tmp/patches/*.patch


error:
git: 'send-email' is not a git command. See 'git --help'.

I am using a ubuntu 11.10 vm to compile and do my patching and such on
if thats in any way useful.


From andrew at lunn.ch  Wed Aug 15 17:15:17 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 15 Aug 2012 23:15:17 +0200
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
Message-ID: <20120815211517.GA15830@lunn.ch>

Hi Alan
...

> i did what you sujested and all commands worked except for the git
> sendmail part so i do not know if I should still be sending you the
> patch this way but here it is. i also defined the gpio keys in the dts
> file like you said the same as with the iconnect but the kernel keeps
> crashing with them defined in the dts is the support actualy there for
> the keys? or have i just defined them wrong?

...

> +		sata at 80000 {
> +			compatible = "marvell,orion-sata";
> +			reg = <0x80000 0x5000>;
> +			interrupts = <21>;
> +			status = "okay";
> +			nr-ports = <2>;
> +		};

You should not need all the values above. All you need is what is
different to the defaults in kirkwood.dtsi. So i _think_ you need:

		sata at 80000 {
			status = "okay";
			nr-ports = <2>;
		};


> +	gpio_keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		button at 1 {
> +			label = "OTB Button";
> +			linux,code = <0x00>;

0x00 seems odd.  

>From <linux/input.h>

#define KEY_RESERVED            0


> +			gpios = <&gpio1 4 1>;
> +			debounce-interval = <100>;
> +		};
> +		button at 2 {
> +			label = "Reset";
> +			linux,code = <0x01>;

0x01 seems odd.
#define KEY_ESC                 1

> +			gpios = <&gpio0 12 1>;
> +			debounce-interval = <100>;
> +		};
> +		button at 3 {
> +			label = "Power";
> +			linux,code = <0x028>;

#define KEY_APOSTROPHE          40

???

	Andrew


From alanbutty12 at gmail.com  Wed Aug 15 17:23:29 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Wed, 15 Aug 2012 22:23:29 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815211517.GA15830@lunn.ch>
References: <3CAEA3DD-9D2C-4052-957D-D09E6EB9B64E@gmail.com>
 <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815211517.GA15830@lunn.ch>
Message-ID: <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>

On 15 August 2012 22:15, Andrew Lunn <andrew at lunn.ch> wrote:
> Hi Alan
> ...
>
>> i did what you sujested and all commands worked except for the git
>> sendmail part so i do not know if I should still be sending you the
>> patch this way but here it is. i also defined the gpio keys in the dts
>> file like you said the same as with the iconnect but the kernel keeps
>> crashing with them defined in the dts is the support actualy there for
>> the keys? or have i just defined them wrong?
>
> ...
>
>> +             sata at 80000 {
>> +                     compatible = "marvell,orion-sata";
>> +                     reg = <0x80000 0x5000>;
>> +                     interrupts = <21>;
>> +                     status = "okay";
>> +                     nr-ports = <2>;
>> +             };
>
> You should not need all the values above. All you need is what is
> different to the defaults in kirkwood.dtsi. So i _think_ you need:
>
>                 sata at 80000 {
>                         status = "okay";
>                         nr-ports = <2>;
>                 };
>
>
>> +     gpio_keys {
>> +             compatible = "gpio-keys";
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             button at 1 {
>> +                     label = "OTB Button";
>> +                     linux,code = <0x00>;
>
> 0x00 seems odd.
>
> From <linux/input.h>
>
> #define KEY_RESERVED            0
>
>
>> +                     gpios = <&gpio1 4 1>;
>> +                     debounce-interval = <100>;
>> +             };
>> +             button at 2 {
>> +                     label = "Reset";
>> +                     linux,code = <0x01>;
>
> 0x01 seems odd.
> #define KEY_ESC                 1
>
>> +                     gpios = <&gpio0 12 1>;
>> +                     debounce-interval = <100>;
>> +             };
>> +             button at 3 {
>> +                     label = "Power";
>> +                     linux,code = <0x028>;
>
> #define KEY_APOSTROPHE          40
>
> ???
>
>         Andrew

ah yeah the last key was a typo and the second key was just what was
in the origional file i was creating the patch from until i can get
the system to properly boot with the buttons defined in the dts file.
(was just kinda using those values as placeholders till i get the
kernel to boot with them then figure out the proper codes)

As for the sata definition that was just an experiment i forgot to
change back (wanted to see if it made any difference).


From linux at arm.linux.org.uk  Wed Aug 15 17:44:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 15 Aug 2012 22:44:12 +0100
Subject: imx6q restart is broken
In-Reply-To: <502BBB43.5010403@gmail.com>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk> <502BBB43.5010403@gmail.com>
Message-ID: <20120815214412.GC32560@n2100.arm.linux.org.uk>

On Wed, Aug 15, 2012 at 10:07:47AM -0500, Rob Herring wrote:
> I think I am seeing a similar problem on highbank with a v7 only build.
> 
> >From what I've debugged, restart hangs for me on the L2x0 spinlock
> during a writel. Changing the writel to writel_relaxed in the restart
> hook fixes the problem. This skips barriers in the writel and for the
> spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
> should not be doing a dmb in my case on a v7 only build.

Well, I had the idea of only doing a dmb() once every N loops, but I don't
think we can sensibly introduce such a change into the mainline kernel.
(How would cpu_relax() know it's being used in a loop?)

Remember that the dmb() is in cpu_relax() as a work-around for the lack
of temporal flushing of pending stores, and is needed to make various bits
of the kernel work.

So at the moment, there is no solution for this - and as I've pointed out
it can be trivially exploited in userspace on the affected CPUs.  So
really a kernel work-around isn't going to sort it.


From alanbutty12 at gmail.com  Wed Aug 15 17:57:27 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Wed, 15 Aug 2012 22:57:27 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815215237.GF15830@lunn.ch>
References: <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
Message-ID: <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>

On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
>> That would be great i just need to recreate the patch with those
>> changes but i was talking with jason cooper i believe and he said to
>> put the buttons for the device in the dts file and im working on that
>> but the kernel panics
>
> Please show us the panic.
>
>        Andrew

i sent it to jason a lil bit earlier but i guess i must of forgotten
to cc the list on the last message or 2 but here is the panic again:

[    5.976074] Key type dns_resolver registered
[    5.981782] Unable to handle kernel NULL pointer dereference at
virtual address 00000004
[    5.989932] pgd = c0004000
[    5.992649] [00000004] *pgd=00000000
[    5.996247] Internal error: Oops: 805 [#1] ARM
[    6.000707] Modules linked in:
[    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
[    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
[    6.014471] LR is at of_get_named_gpio_flags+0x90/0xb4
[    6.019634] pc : [<c02e3190>]    lr : [<c0191a80>]    psr: 60000013
[    6.019634] sp : cf82feb8  ip : 00000001  fp : cf867400
[    6.031158] r10: cf867408  r9 : 00000028  r8 : 00000000
[    6.036400] r7 : c07ebde0  r6 : c07ebe64  r5 : 00000000  r4 : ceff7600
[    6.042958] r3 : 00000001  r2 : c042e57c  r1 : 00000000  r0 : 00000023
[    6.049516] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    6.056857] Control: 0005397f  Table: 0eff8000  DAC: 00000017
[    6.062629] Process swapper (pid: 1, stack limit = 0xcf82e270)
[    6.068481] Stack: (0xcf82feb8 to 0xcf830000)
[    6.072851] fea0:
    00000000 cefff380
[    6.081071] fec0: cf865b40 c00e88f8 cf84e080 00000000 cf808bac
00000003 cf865b40 00000001
[    6.089286] fee0: cf86743c cf867408 cf86743c c04476cc c04476cc
00000034 c041d318 c03fb208
[    6.097500] ff00: 00000000 c01c7ccc c01c7cb8 c01c6dc4 00000000
cf867408 cf86743c c04476cc
[    6.105713] ff20: 00000000 c01c6f5c c04476cc cf82ff38 c01c6efc
c01c58b4 cf808b8c cf8641b0
[    6.113928] ff40: c04476cc c04476cc ceffe300 c0442d18 00000000
c01c654c c03aa8b2 c03aa8b3
[    6.122141] ff60: c04476cc c0412e40 00000000 c0451300 00000034
c01c7208 00000000 00000007
[    6.130355] ff80: c0412e40 00000000 c0451300 00000034 c03fb208
c0008554 00000007 00000007
[    6.138570] ffa0: 00000000 00000007 c0419614 00000007 c0419618
c04195f8 c0451300 00000034
[    6.146784] ffc0: c041d318 c03fb894 00000007 00000007 c03fb208
00000000 00000000 c03fb77c
[    6.154999] ffe0: c000a004 00000013 00000000 00000000 00000000
c000a004 80040038 08040038
[    6.163226] [<c02e3190>] (gpio_keys_probe+0x110/0x6d4) from
[<c01c7ccc>] (platform_drv_probe+0x14/0x18)
[    6.172676] [<c01c7ccc>] (platform_drv_probe+0x14/0x18) from
[<c01c6dc4>] (driver_probe_device+0xb8/0x1f0)
[    6.182385] [<c01c6dc4>] (driver_probe_device+0xb8/0x1f0) from
[<c01c6f5c>] (__driver_attach+0x60/0x84)
[    6.191827] [<c01c6f5c>] (__driver_attach+0x60/0x84) from
[<c01c58b4>] (bus_for_each_dev+0x4c/0x78)
[    6.200922] [<c01c58b4>] (bus_for_each_dev+0x4c/0x78) from
[<c01c654c>] (bus_add_driver+0xa8/0x21c)
[    6.210017] [<c01c654c>] (bus_add_driver+0xa8/0x21c) from
[<c01c7208>] (driver_register+0x9c/0x138)
[    6.219112] [<c01c7208>] (driver_register+0x9c/0x138) from
[<c0008554>] (do_one_initcall+0x90/0x168)
[    6.228294] [<c0008554>] (do_one_initcall+0x90/0x168) from
[<c03fb894>] (kernel_init+0x118/0x1d8)
[    6.237215] [<c03fb894>] (kernel_init+0x118/0x1d8) from
[<c000a004>] (kernel_thread_exit+0x0/0x8)
[    6.246130] Code: e5945000 ebfaba19 e0255899 e59d3024 (e5850004)
[    6.252273] ---[ end trace 192fd8390b667beb ]---
[    6.256946] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b


From mrosenberg at mozilla.com  Wed Aug 15 18:08:29 2012
From: mrosenberg at mozilla.com (Martin Rosenberg)
Date: Wed, 15 Aug 2012 15:08:29 -0700 (PDT)
Subject: Discontiguous memory and cacheflush
In-Reply-To: <20120813160008.GA30302@n2100.arm.linux.org.uk>
Message-ID: <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>



----- Original Message -----
From: "Russell King - ARM Linux" <linux at arm.linux.org.uk>
To: "Jonathan Austin" <jonathan.austin at arm.com>
Cc: "Martin Rosenberg" <mrosenberg at mozilla.com>, "Will Deacon" <will.deacon at arm.com>, linux-arm-kernel at lists.infradead.org
Sent: Monday, August 13, 2012 9:00:08 AM
Subject: Re: Discontiguous memory and cacheflush


> It's intention is to support self-modifying userspace code only and also
> intended to be used over a _short_ range of addresses only - it works by
> flushing each _individual_ cache line over the range of addreses
> requested.
Documenting the current behavior would mostly be acceptable, but it is rather confusing (and took quite some time to track down)

> If it's going to be used for significantly larger areas, then we need to
> think about imposing a limit, upon which we just flush the entire cache
> and be done with it.

I found that there was still a net win making fewer syscalls, even with the overhead of flushing extra cache lines.
In the cases where the range is discontiguous, I usually need to do something silly, like flush 20 individual instructions that are scattered throughout several hundred MB of memory.  I think the fastest method for flushing in this case would be to shave a different call, with a different api, where userspace can provide an array of addresses that need to be flushed, but that sounds like material for a new thread.  Thanks --Marty


From paul at pwsan.com  Wed Aug 15 18:26:42 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 15 Aug 2012 16:26:42 -0600 (MDT)
Subject: [PATCH v2 04/14] ARM: OMAP5: Add minimal support for OMAP5430 SOC
In-Reply-To: <20120709131156.GH1122@atomide.com>
References: <1341566515-22665-1-git-send-email-santosh.shilimkar@ti.com>
 <1341566515-22665-5-git-send-email-santosh.shilimkar@ti.com>
 <4FFA9B61.8030808@ti.com> <20120709131156.GH1122@atomide.com>
Message-ID: <alpine.DEB.2.00.1208151618590.1731@utopia.booyaka.com>

Hi

On Mon, 9 Jul 2012, Tony Lindgren wrote:

> Below (untested) is what could be done in the short term.

That's fine with me.  Do you want to queue it or do you want me to queue 
it?

> Heh these CK_XXXX defines are now running out of the u16 cpu_mask.
> 
> They really should be replaced with SoC specific lists of clocks
> rather than bloating the cpu_mask and repeating it for every clock
> that's compiled in for 800+ times.

Frankly, an extra 1.6KB -- uncompressed -- is pretty low on my list of 
bloat concerns for multi-OMAP kernels.  If it were up to me, I'd just 
change it to a u32 and be done with the problem for the foreseeable 
future.

> I wonder if we could #define CK_OMAP_DUMMY 0 that's always set
> for non-shared clocks if they only get set in some *_data.c
> file in a unique way?
> 
> Paul got any better ideas?

Aside from using u32?  Not really.  As we've discussed in the past, at 
some point we should convert the clock initialization to using some kind 
of per-SoC list.  But it doesn't seem worth spending too much time on that 
while the common clock framework conversion is higher priority.


- Paul


From jason at lakedaemon.net  Wed Aug 15 18:58:16 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 18:58:16 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ4kqpxJrBFPD4o=B3ni=ZUX3EdjBW30k9HxazEB75RMPg@mail.gmail.com>
References: <20120814235653.GA22226@titan.lakedaemon.net>
 <95D5BE56-A79F-4422-B1CE-7AD010A9D70E@gmail.com>
 <20120815111209.GB22226@titan.lakedaemon.net>
 <CAMW5Ufb-8NrWu6vsJ+RezrLEGj-Wfm5Tc+0BK9_2qzn671FrpQ@mail.gmail.com>
 <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815201949.GI22226@titan.lakedaemon.net>
 <CADhrpJ4kqpxJrBFPD4o=B3ni=ZUX3EdjBW30k9HxazEB75RMPg@mail.gmail.com>
Message-ID: <20120815225816.GJ22226@titan.lakedaemon.net>

On Wed, Aug 15, 2012 at 08:56:29PM +0000, alan butler wrote:
...
> >> +     gpio_keys {
> >> +             compatible = "gpio-keys";
> >> +             #address-cells = <1>;
> >> +             #size-cells = <0>;
> >> +             button at 1 {
> >> +                     label = "OTB Button";
> >> +                     linux,code = <0x00>;
> >> +                     gpios = <&gpio1 4 1>;
> >> +                     debounce-interval = <100>;
> >> +             };
> >> +             button at 2 {
> >> +                     label = "Reset";
> >> +                     linux,code = <0x01>;
> >> +                     gpios = <&gpio0 12 1>;
> >> +                     debounce-interval = <100>;
> >> +             };
> >> +             button at 3 {
> >> +                     label = "Power";
> >> +                     linux,code = <0x028>;
> >> +                     gpios = <&gpio0 14 1>;
> >> +                     debounce-interval = <100>;
> >> +             };
> >> +     };
> >> +};
...
> As far as i can tell from looking at the iconnect button definition's
> that part is correct (except for the proper codes to do what the
> buttons should actually do) the error i get is:
> 
> [    5.976074] Key type dns_resolver registered
> [    5.981782] Unable to handle kernel NULL pointer dereference at
> virtual address 00000004
> [    5.989932] pgd = c0004000
> [    5.992649] [00000004] *pgd=00000000
> [    5.996247] Internal error: Oops: 805 [#1] ARM
> [    6.000707] Modules linked in:
> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
> [    6.014471] LR is at of_get_named_gpio_flags+0x90/0xb4
> [    6.019634] pc : [<c02e3190>]    lr : [<c0191a80>]    psr: 60000013
> [    6.019634] sp : cf82feb8  ip : 00000001  fp : cf867400
> [    6.031158] r10: cf867408  r9 : 00000028  r8 : 00000000
> [    6.036400] r7 : c07ebde0  r6 : c07ebe64  r5 : 00000000  r4 : ceff7600
> [    6.042958] r3 : 00000001  r2 : c042e57c  r1 : 00000000  r0 : 00000023
> [    6.049516] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
> Segment kernel
> [    6.056857] Control: 0005397f  Table: 0eff8000  DAC: 00000017
> [    6.062629] Process swapper (pid: 1, stack limit = 0xcf82e270)
> [    6.068481] Stack: (0xcf82feb8 to 0xcf830000)
> [    6.072851] fea0:
>     00000000 cefff380
> [    6.081071] fec0: cf865b40 c00e88f8 cf84e080 00000000 cf808bac
> 00000003 cf865b40 00000001
> [    6.089286] fee0: cf86743c cf867408 cf86743c c04476cc c04476cc
> 00000034 c041d318 c03fb208
> [    6.097500] ff00: 00000000 c01c7ccc c01c7cb8 c01c6dc4 00000000
> cf867408 cf86743c c04476cc
> [    6.105713] ff20: 00000000 c01c6f5c c04476cc cf82ff38 c01c6efc
> c01c58b4 cf808b8c cf8641b0
> [    6.113928] ff40: c04476cc c04476cc ceffe300 c0442d18 00000000
> c01c654c c03aa8b2 c03aa8b3
> [    6.122141] ff60: c04476cc c0412e40 00000000 c0451300 00000034
> c01c7208 00000000 00000007
> [    6.130355] ff80: c0412e40 00000000 c0451300 00000034 c03fb208
> c0008554 00000007 00000007
> [    6.138570] ffa0: 00000000 00000007 c0419614 00000007 c0419618
> c04195f8 c0451300 00000034
> [    6.146784] ffc0: c041d318 c03fb894 00000007 00000007 c03fb208
> 00000000 00000000 c03fb77c
> [    6.154999] ffe0: c000a004 00000013 00000000 00000000 00000000
> c000a004 80040038 08040038
> [    6.163226] [<c02e3190>] (gpio_keys_probe+0x110/0x6d4) from
> [<c01c7ccc>] (platform_drv_probe+0x14/0x18)
> [    6.172676] [<c01c7ccc>] (platform_drv_probe+0x14/0x18) from
> [<c01c6dc4>] (driver_probe_device+0xb8/0x1f0)
> [    6.182385] [<c01c6dc4>] (driver_probe_device+0xb8/0x1f0) from
> [<c01c6f5c>] (__driver_attach+0x60/0x84)
> [    6.191827] [<c01c6f5c>] (__driver_attach+0x60/0x84) from
> [<c01c58b4>] (bus_for_each_dev+0x4c/0x78)
> [    6.200922] [<c01c58b4>] (bus_for_each_dev+0x4c/0x78) from
> [<c01c654c>] (bus_add_driver+0xa8/0x21c)
> [    6.210017] [<c01c654c>] (bus_add_driver+0xa8/0x21c) from
> [<c01c7208>] (driver_register+0x9c/0x138)
> [    6.219112] [<c01c7208>] (driver_register+0x9c/0x138) from
> [<c0008554>] (do_one_initcall+0x90/0x168)
> [    6.228294] [<c0008554>] (do_one_initcall+0x90/0x168) from
> [<c03fb894>] (kernel_init+0x118/0x1d8)
> [    6.237215] [<c03fb894>] (kernel_init+0x118/0x1d8) from
> [<c000a004>] (kernel_thread_exit+0x0/0x8)
> [    6.246130] Code: e5945000 ebfaba19 e0255899 e59d3024 (e5850004)
> [    6.252273] ---[ end trace 192fd8390b667beb ]---
> [    6.256946] Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x0000000b
> 

Take a look at Documentation/devicetree/bindings/gpio/gpio_keys.txt, I
think you need 'linux,input-type = "EV_SW";' for each of the buttons.
Or, the numerical equivalent, <0x05>.

> and as for the git command i tried and what it tells me this is what i get:
> 
> git send-email --to="alanbutty12 at gmail.com" --smtp-server=Gmail
> --no-chain-reply-to --from="alanbutty12 at gmail.com"
> /tmp/patches/*.patch
> 
> 
> error:
> git: 'send-email' is not a git command. See 'git --help'.

sudo apt-get install git-send-email

then, follow the section "Another method, I didn't try it" here:

https://mohammadthalif.wordpress.com/2010/01/02/configuring-git-send-email-to-use-gmail-smtp/

hth,

Jason.


From alanbutty12 at gmail.com  Wed Aug 15 19:12:25 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Thu, 16 Aug 2012 00:12:25 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
References: <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
Message-ID: <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>

On 16 August 2012 00:02, alan butler <alanbutty12 at gmail.com> wrote:
> On 15 August 2012 23:16, Andrew Lunn <andrew at lunn.ch> wrote:
>> On Wed, Aug 15, 2012 at 10:57:27PM +0100, alan butler wrote:
>>> On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
>>> >> That would be great i just need to recreate the patch with those
>>> >> changes but i was talking with jason cooper i believe and he said to
>>> >> put the buttons for the device in the dts file and im working on that
>>> >> but the kernel panics
>>> >
>>> > Please show us the panic.
>>> >
>>> >        Andrew
>>>
>>> i sent it to jason a lil bit earlier but i guess i must of forgotten
>>> to cc the list on the last message or 2 but here is the panic again:
>>>
>>> [    5.976074] Key type dns_resolver registered
>>> [    5.981782] Unable to handle kernel NULL pointer dereference at
>>> virtual address 00000004
>>> [    5.989932] pgd = c0004000
>>> [    5.992649] [00000004] *pgd=00000000
>>> [    5.996247] Internal error: Oops: 805 [#1] ARM
>>> [    6.000707] Modules linked in:
>>> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
>>> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
>>
>> You might want to scatter some printk() in gpio_keys_probe() and see
>> where it panics. It will probably then be clear what is wrong.
>>
>>       Andrew
>
> where do i find the gpio_keys_probe() ?

i found the gpio_keys_probe() and it seems that it is failing in this
piece of code i put a printk() before and after it and it didnt reach
the printk after it:

if (!pdata) {
		pdata = gpio_keys_get_devtree_pdata(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
	}

	ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
			pdata->nbuttons * sizeof(struct gpio_button_data),
			GFP_KERNEL);
	input = input_allocate_device();
	if (!ddata || !input) {
		dev_err(dev, "failed to allocate state\n");
		error = -ENOMEM;
		goto fail1;
	}


From alanbutty12 at gmail.com  Wed Aug 15 19:34:46 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Thu, 16 Aug 2012 00:34:46 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
References: <20120815121145.GC22226@titan.lakedaemon.net>
 <CADhrpJ4-4n15yfttBBFQOdOkKag0gaeqYgB4DFre3aG+R4Vq+Q@mail.gmail.com>
 <20120815135427.GF22226@titan.lakedaemon.net>
 <CADhrpJ5JEGQWAjwu5+=Hy_gFjWLkkrzj9E0dZ-vxMk9x+M5uCA@mail.gmail.com>
 <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
Message-ID: <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>

On 16 August 2012 00:12, alan butler <alanbutty12 at gmail.com> wrote:
> On 16 August 2012 00:02, alan butler <alanbutty12 at gmail.com> wrote:
>> On 15 August 2012 23:16, Andrew Lunn <andrew at lunn.ch> wrote:
>>> On Wed, Aug 15, 2012 at 10:57:27PM +0100, alan butler wrote:
>>>> On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
>>>> >> That would be great i just need to recreate the patch with those
>>>> >> changes but i was talking with jason cooper i believe and he said to
>>>> >> put the buttons for the device in the dts file and im working on that
>>>> >> but the kernel panics
>>>> >
>>>> > Please show us the panic.
>>>> >
>>>> >        Andrew
>>>>
>>>> i sent it to jason a lil bit earlier but i guess i must of forgotten
>>>> to cc the list on the last message or 2 but here is the panic again:
>>>>
>>>> [    5.976074] Key type dns_resolver registered
>>>> [    5.981782] Unable to handle kernel NULL pointer dereference at
>>>> virtual address 00000004
>>>> [    5.989932] pgd = c0004000
>>>> [    5.992649] [00000004] *pgd=00000000
>>>> [    5.996247] Internal error: Oops: 805 [#1] ARM
>>>> [    6.000707] Modules linked in:
>>>> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
>>>> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
>>>
>>> You might want to scatter some printk() in gpio_keys_probe() and see
>>> where it panics. It will probably then be clear what is wrong.
>>>
>>>       Andrew
>>
>> where do i find the gpio_keys_probe() ?
>
> i found the gpio_keys_probe() and it seems that it is failing in this
> piece of code i put a printk() before and after it and it didnt reach
> the printk after it:
>
> if (!pdata) {
>                 pdata = gpio_keys_get_devtree_pdata(dev);
>                 if (IS_ERR(pdata))
>                         return PTR_ERR(pdata);
>         }
>
>         ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
>                         pdata->nbuttons * sizeof(struct gpio_button_data),
>                         GFP_KERNEL);
>         input = input_allocate_device();
>         if (!ddata || !input) {
>                 dev_err(dev, "failed to allocate state\n");
>                 error = -ENOMEM;
>                 goto fail1;
>         }

actualy it seems to not be getting past this piece of code in what i
posted before:

if (!pdata) {
		pdata = gpio_keys_get_devtree_pdata(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
	}


From jason at lakedaemon.net  Wed Aug 15 19:41:59 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 15 Aug 2012 19:41:59 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
References: <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
Message-ID: <20120815234159.GK22226@titan.lakedaemon.net>

On Thu, Aug 16, 2012 at 12:34:46AM +0100, alan butler wrote:
> On 16 August 2012 00:12, alan butler <alanbutty12 at gmail.com> wrote:
> > On 16 August 2012 00:02, alan butler <alanbutty12 at gmail.com> wrote:
> >> On 15 August 2012 23:16, Andrew Lunn <andrew at lunn.ch> wrote:
> >>> On Wed, Aug 15, 2012 at 10:57:27PM +0100, alan butler wrote:
> >>>> On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
> >>>> >> That would be great i just need to recreate the patch with those
> >>>> >> changes but i was talking with jason cooper i believe and he said to
> >>>> >> put the buttons for the device in the dts file and im working on that
> >>>> >> but the kernel panics
> >>>> >
> >>>> > Please show us the panic.
> >>>> >
> >>>> >        Andrew
> >>>>
> >>>> i sent it to jason a lil bit earlier but i guess i must of forgotten
> >>>> to cc the list on the last message or 2 but here is the panic again:
> >>>>
> >>>> [    5.976074] Key type dns_resolver registered
> >>>> [    5.981782] Unable to handle kernel NULL pointer dereference at
> >>>> virtual address 00000004
> >>>> [    5.989932] pgd = c0004000
> >>>> [    5.992649] [00000004] *pgd=00000000
> >>>> [    5.996247] Internal error: Oops: 805 [#1] ARM
> >>>> [    6.000707] Modules linked in:
> >>>> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
> >>>> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
> >>>
> >>> You might want to scatter some printk() in gpio_keys_probe() and see
> >>> where it panics. It will probably then be clear what is wrong.
> >>>
> >>>       Andrew
> >>
> >> where do i find the gpio_keys_probe() ?
> >
> > i found the gpio_keys_probe() and it seems that it is failing in this
> > piece of code i put a printk() before and after it and it didnt reach
> > the printk after it:
> >
> > if (!pdata) {
> >                 pdata = gpio_keys_get_devtree_pdata(dev);
> >                 if (IS_ERR(pdata))
> >                         return PTR_ERR(pdata);
> >         }
> >
> >         ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
> >                         pdata->nbuttons * sizeof(struct gpio_button_data),
> >                         GFP_KERNEL);
> >         input = input_allocate_device();
> >         if (!ddata || !input) {
> >                 dev_err(dev, "failed to allocate state\n");
> >                 error = -ENOMEM;
> >                 goto fail1;
> >         }
> 
> actualy it seems to not be getting past this piece of code in what i
> posted before:
> 
> if (!pdata) {
> 		pdata = gpio_keys_get_devtree_pdata(dev);
> 		if (IS_ERR(pdata))
> 			return PTR_ERR(pdata);
> 	}

That means gpio_keys_get_devtree_pdata() is returning an error.  Have
you tried 'linux,input-type = <0x05>;' ?

thx,

Jason.


From mturquette at linaro.org  Wed Aug 15 19:43:33 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 Aug 2012 16:43:33 -0700
Subject: [PATCH v2 3/4] [RFC] cpufreq: omap: scale regulator from clk notifier
In-Reply-To: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
Message-ID: <1345074214-17531-4-git-send-email-mturquette@linaro.org>

This patch moves direct control of the MPU voltage regulator out of the
cpufreq driver .target callback and instead uses the common dvfs clk
rate-change notifier infrastructure.

Ideally it would be nice to reduce the .target callback for omap's
cpufreq driver to a simple call to clk_set_rate.  For now there is still
some other stuff needed there (jiffies per loop, rounding the rate, etc
etc).

Signed-off-by: Mike Turquette <mturquette at linaro.org>
---
 drivers/cpufreq/omap-cpufreq.c |   85 +++++++++++-----------------------------
 1 file changed, 22 insertions(+), 63 deletions(-)

diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 17fa04d..2f7de30 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -55,7 +55,7 @@ static atomic_t freq_table_users = ATOMIC_INIT(0);
 static struct clk *mpu_clk;
 static char *mpu_clk_name;
 static struct device *mpu_dev;
-static struct regulator *mpu_reg;
+static struct dvfs_info *di;
 
 static int omap_verify_speed(struct cpufreq_policy *policy)
 {
@@ -80,10 +80,9 @@ static int omap_target(struct cpufreq_policy *policy,
 		       unsigned int relation)
 {
 	unsigned int i;
-	int r, ret = 0;
+	int ret = 0;
 	struct cpufreq_freqs freqs;
-	struct opp *opp;
-	unsigned long freq, volt = 0, volt_old = 0, tol = 0;
+	unsigned long freq;
 
 	if (!freq_table) {
 		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
@@ -119,47 +118,11 @@ static int omap_target(struct cpufreq_policy *policy,
 
 	freq = freqs.new * 1000;
 
-	if (mpu_reg) {
-		opp = opp_find_freq_ceil(mpu_dev, &freq);
-		if (IS_ERR(opp)) {
-			dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
-				__func__, freqs.new);
-			return -EINVAL;
-		}
-		volt = opp_get_voltage(opp);
-		tol = volt * OPP_TOLERANCE / 100;
-		volt_old = regulator_get_voltage(mpu_reg);
-	}
-
-	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", 
-		freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
-		freqs.new / 1000, volt ? volt / 1000 : -1);
-
-	/* scaling up?  scale voltage before frequency */
-	if (mpu_reg && (freqs.new > freqs.old)) {
-		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
-		if (r < 0) {
-			dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
-				 __func__);
-			freqs.new = freqs.old;
-			goto done;
-		}
-	}
+	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz --> %u MHz\n",
+			freqs.old / 1000, freqs.new / 1000); 
 
 	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
 
-	/* scaling down?  scale voltage after frequency */
-	if (mpu_reg && (freqs.new < freqs.old)) {
-		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
-		if (r < 0) {
-			dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
-				 __func__);
-			ret = clk_set_rate(mpu_clk, freqs.old * 1000);
-			freqs.new = freqs.old;
-			goto done;
-		}
-	}
-
 	freqs.new = omap_getspeed(policy->cpu);
 #ifdef CONFIG_SMP
 	/*
@@ -187,7 +150,6 @@ static int omap_target(struct cpufreq_policy *policy,
 					freqs.new);
 #endif
 
-done:
 	/* notifiers */
 	for_each_cpu(i, policy->cpus) {
 		freqs.cpu = i;
@@ -207,10 +169,6 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 {
 	int result = 0;
 
-	mpu_clk = clk_get(NULL, mpu_clk_name);
-	if (IS_ERR(mpu_clk))
-		return PTR_ERR(mpu_clk);
-
 	if (policy->cpu >= NR_CPUS) {
 		result = -EINVAL;
 		goto fail_ck;
@@ -286,6 +244,8 @@ static struct cpufreq_driver omap_driver = {
 
 static int __init omap_cpufreq_init(void)
 {
+	struct dvfs_info_init dii;
+
 	if (cpu_is_omap24xx())
 		mpu_clk_name = "virt_prcm_set";
 	else if (cpu_is_omap34xx())
@@ -298,34 +258,33 @@ static int __init omap_cpufreq_init(void)
 		return -EINVAL;
 	}
 
+	mpu_clk = clk_get(NULL, mpu_clk_name);
+	if (IS_ERR(mpu_clk))
+		return PTR_ERR(mpu_clk);
+
 	mpu_dev = omap_device_get_by_hwmod_name("mpu");
 	if (!mpu_dev) {
 		pr_warning("%s: unable to get the mpu device\n", __func__);
-		return -EINVAL;
+		goto out;
 	}
 
-	mpu_reg = regulator_get(mpu_dev, "vcc");
-	if (IS_ERR(mpu_reg)) {
-		pr_warning("%s: unable to get MPU regulator\n", __func__);
-		mpu_reg = NULL;
-	} else {
-		/* 
-		 * Ensure physical regulator is present.
-		 * (e.g. could be dummy regulator.)
-		 */
-		if (regulator_get_voltage(mpu_reg) < 0) {
-			pr_warn("%s: physical regulator not present for MPU\n",
+	dii.dev = mpu_dev;
+	dii.con_id = mpu_clk_name;
+	dii.reg_id = "vcc";
+	dii.tol = OPP_TOLERANCE;
+
+	di = dvfs_clk_notifier_register(&dii);
+	if (IS_ERR(di))
+		pr_warning("%s: failed to register dvfs clk notifier\n",
 				__func__);
-			regulator_put(mpu_reg);
-			mpu_reg = NULL;
-		}
-	}
 
+out:
 	return cpufreq_register_driver(&omap_driver);
 }
 
 static void __exit omap_cpufreq_exit(void)
 {
+	dvfs_clk_notifier_unregister(di);
 	cpufreq_unregister_driver(&omap_driver);
 }
 
-- 
1.7.9.5



From mturquette at linaro.org  Wed Aug 15 19:43:30 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 Aug 2012 16:43:30 -0700
Subject: [PATCH v2 0/4] [RFC] reentrancy in the common clk framework
Message-ID: <1345074214-17531-1-git-send-email-mturquette@linaro.org>

The second version of the reentrancy/dvfs rfc differs from the
original[1] in that the former used per-clk mutexes and this version
uses a global lock to protect access to a per-clk enum.  The enum can be
in one of two states, LOCKED or UNLOCKED.

The second patch in the series introduces a new common clk rate-change
notifier handler which implements typical dynamic voltage and frequency
scaling logic.

The third patch uses the aforementioned common dvfs rate-change notifier
handler.  Instead of implementing the dvfs logic directly (as in [1[)
the driver simply registers a notifier handler using the common dvfs
infrastructure.  Potentially all cpufreq and devfreq users could use
this to implement voltage scaling.

The fourth patch demonstrates how it is possible to call top-level clk
api's reentrantly.  This example code switches parents of a mux clock
and does prepare/disable directly, without using internal functions.  A
more interesting application of this might be to have clk_set_parent
call clk_prepare_enable clk_disable_unprepare directly when reparenting.

There are wide-ranging considerations to the common clk framework in
this series; I know some of you will be in San Diego later this month
and hopefully I'll get some good feedback there as well as on the list.

[1] http://article.gmane.org/gmane.linux.kernel/1327866

Mike Turquette (4):
  clk: new locking scheme for reentrancy
  clk: notifier handler for dynamic voltage scaling
  cpufreq: omap: scale regulator from clk notifier
  omap3+: clk: dpll: call clk_prepare directly

 arch/arm/mach-omap2/dpll3xxx.c |    8 +-
 drivers/clk/Makefile           |    3 +-
 drivers/clk/clk.c              |  354 +++++++++++++++++++++++++++++++++++-----
 drivers/clk/dvfs.c             |  116 +++++++++++++
 drivers/cpufreq/omap-cpufreq.c |   85 +++-------
 include/linux/clk-private.h    |    1 +
 include/linux/clk-provider.h   |    4 +-
 include/linux/clk.h            |   27 ++-
 8 files changed, 488 insertions(+), 110 deletions(-)
 create mode 100644 drivers/clk/dvfs.c

-- 
1.7.9.5



From mturquette at linaro.org  Wed Aug 15 19:43:34 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 Aug 2012 16:43:34 -0700
Subject: [PATCH v2 4/4] [RFC] omap3+: clk: dpll: call clk_prepare directly
In-Reply-To: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
Message-ID: <1345074214-17531-5-git-send-email-mturquette@linaro.org>

In the commit titled "clk: new locking scheme for reentrancy" it became
possible for nested calls to the clock api.  The OMAP3+ DPLL .set_rate
callback has been using the __clk_prepare and __clk_unprepare calls as a
way around this limitation, but these calls are no longer needed with
the aforementioned patch.  Convert the .set_rate callback to use
clk_prepare and clk_unprepare directly.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
---
 arch/arm/mach-omap2/dpll3xxx.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ee18d00..1cc3ec8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -436,9 +436,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (!dd)
 		return -EINVAL;
 
-	__clk_prepare(dd->clk_bypass);
+	clk_prepare(dd->clk_bypass);
 	clk_enable(dd->clk_bypass);
-	__clk_prepare(dd->clk_ref);
+	clk_prepare(dd->clk_ref);
 	clk_enable(dd->clk_ref);
 
 	if (__clk_get_rate(dd->clk_bypass) == rate &&
@@ -483,9 +483,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 		__clk_reparent(hw->clk, new_parent);
 
 	clk_disable(dd->clk_ref);
-	__clk_unprepare(dd->clk_ref);
+	clk_unprepare(dd->clk_ref);
 	clk_disable(dd->clk_bypass);
-	__clk_unprepare(dd->clk_bypass);
+	clk_unprepare(dd->clk_bypass);
 
 	return 0;
 }
-- 
1.7.9.5



From mturquette at linaro.org  Wed Aug 15 19:43:31 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 Aug 2012 16:43:31 -0700
Subject: [PATCH v2 1/4] [RFC] clk: new locking scheme for reentrancy
In-Reply-To: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
Message-ID: <1345074214-17531-2-git-send-email-mturquette@linaro.org>

The global prepare_lock mutex prevents concurrent operations in the clk
api.  This incurs a performance penalty when unrelated clock subtrees
are contending for the lock.

Additionally there are use cases which benefit from reentrancy into the
clk api.  A simple example is reparenting a mux clock with a call to
clk_set_rate.  Patch #4 in this series demonstrates this without the use
of internal helper functions.

A more complex example is performing dynamic frequency and voltage
scaling from clk_set_rate.  Patches #2 and #3 in this series demonstrate
this.

This commit affects users of the global prepare_lock mutex, namely
clk_prepare, clk_unprepare, clk_set_rate and clk_set_parent.

This patch introduces an enum inside of struct clk which tracks whether
the framework has LOCKED or UNLOCKED the clk.

Access to clk->state must be protected by the global prepare_lock mutex.
In the future maybe the global mutex can be dropped and all operations
will only use a global spinlock to protect access to the per-clk enums.
A general outline of the new locking scheme is as follows:

1) hold the global prepare_lock mutex
2) traverse the tree checking to make sure that any clk's needed are
UNLOCKED and not LOCKED
	a) if a clk in the subtree of affected clk's is LOCKED then
	   release the global lock, wait_for_completion and then try
	   again up to a maximum of WAIT_TRIES times
	b) After WAIT_TRIES times return -EBUSY
3) if all clk's are UNLOCKED then mark them as LOCKED
4) release the global prepare_lock mutex
5) do the real work
6) hold the global prepare_lock mutex
7) set all of the clocks previously marked as LOCKED to UNLOCKED
8) release the global prepare_lock mutex and return

The primary down-side to this approach is that the clk api's might
return -EBUSY due to lock contention.  This is only after having tried
several times.  Bailing out like this is necessary to prevent deadlocks.

The enum approach in this version of the patchset does not benefit from
lockdep checking the lock order (but neither did v1).  It is possible
for circular dependencies to pop up for the careless developer and
bailing out after a number of unsuccessful tries is the sanest strategy.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/clk.c            |  354 +++++++++++++++++++++++++++++++++++++-----
 include/linux/clk-private.h  |    1 +
 include/linux/clk-provider.h |    4 +-
 3 files changed, 318 insertions(+), 41 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 51a29d1..92bb516 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -17,6 +17,9 @@
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/completion.h>
+
+#define WAIT_TRIES	5
 
 static DEFINE_SPINLOCK(enable_lock);
 static DEFINE_MUTEX(prepare_lock);
@@ -25,6 +28,8 @@ static HLIST_HEAD(clk_root_list);
 static HLIST_HEAD(clk_orphan_list);
 static LIST_HEAD(clk_notifier_list);
 
+static DECLARE_COMPLETION(clk_completion);
+
 /***        debugfs support        ***/
 
 #ifdef CONFIG_COMMON_CLK_DEBUG
@@ -372,23 +377,51 @@ struct clk *__clk_lookup(const char *name)
 
 /***        clk api        ***/
 
-void __clk_unprepare(struct clk *clk)
+static struct clk *__clk_unprepare_lock(struct clk *clk)
 {
+	struct clk *top;
+
 	if (!clk)
-		return;
+		return ERR_PTR(-ENOENT);
+
+	if (clk->state == LOCKED)
+		return ERR_PTR(-EBUSY);
 
 	if (WARN_ON(clk->prepare_count == 0))
-		return;
+		return ERR_PTR(-EPERM);
 
-	if (--clk->prepare_count > 0)
-		return;
+	if (clk->prepare_count > 1 || clk->flags & CLK_IS_ROOT) {
+		top = clk;
+		clk->state = LOCKED;
+		clk->prepare_count--;
+	} else {
+		top = __clk_unprepare_lock(clk->parent);
+		if (IS_ERR(top))
+			goto out;
 
-	WARN_ON(clk->enable_count > 0);
+		clk->state = LOCKED;
+		clk->prepare_count--;
+	}
 
+out:
+	return top;
+}
+
+void __clk_unprepare(struct clk *clk, struct clk *top)
+{
 	if (clk->ops->unprepare)
 		clk->ops->unprepare(clk->hw);
 
-	__clk_unprepare(clk->parent);
+	if (clk != top)
+		__clk_unprepare(clk->parent, top);
+}
+
+static void __clk_prepare_unlock(struct clk *clk, struct clk *top)
+{
+	clk->state = UNLOCKED;
+
+	if (clk != top)
+		__clk_prepare_unlock(clk->parent, top);
 }
 
 /**
@@ -404,35 +437,94 @@ void __clk_unprepare(struct clk *clk)
  */
 void clk_unprepare(struct clk *clk)
 {
+	struct clk *top = ERR_PTR(-EBUSY);
+	int tries = 0;
+
+	/*
+	 * walk the list of parents checking clk->state along the way.  If all
+	 * clk->state is UNLOCKED then continue.  If a clk->state is LOCKED then
+	 * bail out with -EBUSY.
+	 */
+	while (IS_ERR(top)) {
+		mutex_lock(&prepare_lock);
+		top = __clk_unprepare_lock(clk);
+		mutex_unlock(&prepare_lock);
+
+		if (IS_ERR(top)) {
+			pr_debug("%s: %s failed with %ld on attempt %d\n",
+					__func__, clk->name, PTR_ERR(top),
+					tries);
+			wait_for_completion(&clk_completion);
+			if (WAIT_TRIES == ++tries)
+				break;
+		} else
+			break;
+	}
+
+	if (WAIT_TRIES == tries) {
+		pr_warning("%s: failed to lock clocks; cyclical dependency?\n",
+				__func__);
+		return;
+	}
+
+	/* unprepare the list of clocks from clk to top */
+	__clk_unprepare(clk, top);
+
+	/* set clk->state from LOCKED to UNLOCKED and fire off completion */
 	mutex_lock(&prepare_lock);
-	__clk_unprepare(clk);
+	__clk_prepare_unlock(clk, top);
 	mutex_unlock(&prepare_lock);
+
+	complete(&clk_completion);
 }
 EXPORT_SYMBOL_GPL(clk_unprepare);
 
-int __clk_prepare(struct clk *clk)
+static struct clk *__clk_prepare_lock(struct clk *clk)
 {
-	int ret = 0;
+	struct clk *top;
 
 	if (!clk)
-		return 0;
+		return ERR_PTR(-ENOENT);
+
+	if (clk->state == LOCKED)
+		return ERR_PTR(-EBUSY);
 
-	if (clk->prepare_count == 0) {
-		ret = __clk_prepare(clk->parent);
+	if (clk->prepare_count > 0 || clk->flags & CLK_IS_ROOT) {
+		top = clk;
+		clk->state = LOCKED;
+		clk->prepare_count++;
+	} else {
+		top = __clk_prepare_lock(clk->parent);
+		if (IS_ERR(top))
+			goto out;
+
+		clk->state = LOCKED;
+		clk->prepare_count++;
+	}
+
+out:
+	return top;
+}
+
+int __clk_prepare(struct clk *clk, struct clk *top)
+{
+	int ret = 0;
+
+	if (clk != top) {
+		ret = __clk_prepare(clk->parent, top);
 		if (ret)
 			return ret;
 
 		if (clk->ops->prepare) {
 			ret = clk->ops->prepare(clk->hw);
 			if (ret) {
-				__clk_unprepare(clk->parent);
+				/* this is safe since clk != top */
+				__clk_unprepare(clk->parent, top);
 				return ret;
 			}
 		}
 	}
 
-	clk->prepare_count++;
-
 	return 0;
 }
 
@@ -450,13 +542,42 @@ int __clk_prepare(struct clk *clk)
  */
 int clk_prepare(struct clk *clk)
 {
-	int ret;
+	struct clk *top = ERR_PTR(-EBUSY);
+	int tries = 0;
+
+	while(IS_ERR(top)) {
+		mutex_lock(&prepare_lock);
+		top = __clk_prepare_lock(clk);
+		mutex_unlock(&prepare_lock);
+
+		if (IS_ERR(top)) {
+			pr_debug("%s: %s failed with %ld on attempt %d\n",
+					__func__, clk->name, PTR_ERR(top),
+					tries);
+			wait_for_completion(&clk_completion);
+			if (WAIT_TRIES == ++tries)
+				break;
+		} else
+			break;
+	}
+
+	if (WAIT_TRIES == tries) {
+		pr_err("%s: failed to lock clocks; cyclical dependency?\n",
+				__func__);
+		return -EBUSY;
+	}
 
+	/* unprepare the list of clocks from clk to top */
+	__clk_prepare(clk, top);
+
+	/* set clk->state from LOCKED to UNLOCKED and fire off completion */
 	mutex_lock(&prepare_lock);
-	ret = __clk_prepare(clk);
+	__clk_prepare_unlock(clk, top);
 	mutex_unlock(&prepare_lock);
 
-	return ret;
+	complete(&clk_completion);
+
+	return 0;
 }
 EXPORT_SYMBOL_GPL(clk_prepare);
 
@@ -730,12 +851,12 @@ static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
 	if (clk->notifier_count)
 		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
 
-	if (ret == NOTIFY_BAD)
+	if (ret & NOTIFY_STOP_MASK)
 		goto out;
 
 	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
 		ret = __clk_speculate_rates(child, new_rate);
-		if (ret == NOTIFY_BAD)
+		if (ret & NOTIFY_STOP_MASK)
 			break;
 	}
 
@@ -759,15 +880,89 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 	}
 }
 
+static int clk_test_lock_subtree(struct clk *clk)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	int ret = 0;
+
+	if (clk->state != UNLOCKED)
+		return -EBUSY;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = clk_test_lock_subtree(child);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int clk_test_lock_additional_subtree(struct clk *clk, struct clk *avoid)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	int ret = 0;
+
+	if (clk == avoid)
+		return 0;
+
+	if (clk->state != UNLOCKED)
+		return -EBUSY;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = clk_test_lock_additional_subtree(child, avoid);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void clk_lock_subtree(struct clk *clk)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		clk->state = LOCKED;
+	}
+}
+
+static void clk_lock_additional_subtree(struct clk *clk, struct clk *avoid)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	if (clk == avoid)
+		return;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		clk->state = LOCKED;
+		clk_lock_additional_subtree(child, avoid);
+	}
+}
+
+static void clk_unlock_subtree(struct clk *clk)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		clk->state = UNLOCKED;
+	}
+}
+
 /*
- * calculate the new rates returning the topmost clock that has to be
- * changed.
+ * calculate the new rates returning the topmost clock that has to be changed.
+ * Caller must set clk->state to LOCKED for clk and all of its children
  */
 static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
 	struct clk *top = clk;
 	unsigned long best_parent_rate = 0;
 	unsigned long new_rate;
+	int ret = 0;
 
 	/* sanity */
 	if (IS_ERR_OR_NULL(clk))
@@ -794,6 +989,19 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 	}
 
 	if (!clk->ops->round_rate) {
+		/* set parent and all additional children as LOCKED */
+		mutex_lock(&prepare_lock);
+		ret = clk_test_lock_additional_subtree(clk->parent, clk);
+		if (!ret)
+			clk_lock_additional_subtree(clk->parent, clk);
+		mutex_unlock(&prepare_lock);
+
+		if (ret == -EBUSY) {
+			pr_err("%s: %s: failed with EBUSY\n", __func__, clk->name);
+			/* FIXME the right thing to do? */
+			return NULL;
+		}
+
 		top = clk_calc_new_rates(clk->parent, rate);
 		new_rate = clk->parent->new_rate;
 
@@ -803,6 +1011,18 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 	new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
 
 	if (best_parent_rate != clk->parent->rate) {
+		mutex_lock(&prepare_lock);
+		ret = clk_test_lock_additional_subtree(clk->parent, clk);
+		if (!ret)
+			clk_lock_additional_subtree(clk->parent, clk);
+		mutex_unlock(&prepare_lock);
+
+		if (ret == -EBUSY) {
+			pr_err("%s: %s: failed with EBUSY\n", __func__, clk->name);
+			/* FIXME the right thing to do? */
+			return NULL;
+		}
+
 		top = clk_calc_new_rates(clk->parent, best_parent_rate);
 
 		goto out;
@@ -830,8 +1050,11 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
 
 	if (clk->notifier_count) {
 		ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
-		if (ret == NOTIFY_BAD)
+		if (ret & NOTIFY_STOP_MASK)
 			fail_clk = clk;
+		if (notifier_to_errno(ret) == -EBUSY)
+			WARN(1, "%s: %s: possible cyclical dependency?\n",
+					__func__, clk->name);
 	}
 
 	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
@@ -897,11 +1120,35 @@ static void clk_change_rate(struct clk *clk)
  */
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
-	struct clk *top, *fail_clk;
-	int ret = 0;
+	struct clk *top = clk, *fail_clk;
+	int ret = -EBUSY, i = 0, tries = 0;
+
+	if (!clk)
+		return 0;
 
 	/* prevent racing with updates to the clock topology */
-	mutex_lock(&prepare_lock);
+	while (ret) {
+		mutex_lock(&prepare_lock);
+		ret = clk_test_lock_subtree(clk);
+		if (!ret)
+			clk_lock_subtree(clk);
+		mutex_unlock(&prepare_lock);
+
+		if (ret) {
+			pr_debug("%s: %s failed with %d on attempt %d\n",
+					__func__, clk->name, ret, tries);
+			wait_for_completion(&clk_completion);
+			if (WAIT_TRIES == ++tries)
+				break;
+		} else
+			break;
+	}
+
+	if (i == WAIT_TRIES) {
+		pr_err("%s: failed to lock clocks; cyclical dependency?\n",
+				__func__);
+		return ret;
+	}
 
 	/* bail early if nothing to do */
 	if (rate == clk->rate)
@@ -932,12 +1179,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	/* change the rates */
 	clk_change_rate(top);
 
-	mutex_unlock(&prepare_lock);
-
-	return 0;
 out:
+	mutex_lock(&prepare_lock);
+	clk_unlock_subtree(top);
 	mutex_unlock(&prepare_lock);
 
+	complete(&clk_completion);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(clk_set_rate);
@@ -1095,12 +1343,12 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
 
 	/* migrate prepare and enable */
 	if (clk->prepare_count)
-		__clk_prepare(parent);
+		clk_prepare(parent);
 
 	/* FIXME replace with clk_is_enabled(clk) someday */
 	spin_lock_irqsave(&enable_lock, flags);
 	if (clk->enable_count)
-		__clk_enable(parent);
+		clk_enable(parent);
 	spin_unlock_irqrestore(&enable_lock, flags);
 
 	/* change clock input source */
@@ -1109,11 +1357,11 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
 	/* clean up old prepare and enable */
 	spin_lock_irqsave(&enable_lock, flags);
 	if (clk->enable_count)
-		__clk_disable(old_parent);
+		clk_disable(old_parent);
 	spin_unlock_irqrestore(&enable_lock, flags);
 
 	if (clk->prepare_count)
-		__clk_unprepare(old_parent);
+		clk_unprepare(old_parent);
 
 out:
 	return ret;
@@ -1133,7 +1381,7 @@ out:
  */
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
-	int ret = 0;
+	int ret = 0, i = 0, tries = 0;
 
 	if (!clk || !clk->ops)
 		return -EINVAL;
@@ -1141,19 +1389,42 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 	if (!clk->ops->set_parent)
 		return -ENOSYS;
 
-	/* prevent racing with updates to the clock topology */
-	mutex_lock(&prepare_lock);
-
 	if (clk->parent == parent)
 		goto out;
 
+	/* prevent racing with updates to the clock topology */
+	while (ret) {
+		mutex_lock(&prepare_lock);
+		ret = clk_test_lock_subtree(clk);
+		if (!ret)
+			clk_lock_subtree(clk);
+		mutex_unlock(&prepare_lock);
+
+		if (ret) {
+			pr_debug("%s: %s failed with %d on attempt %d\n",
+					__func__, clk->name, ret, tries);
+			wait_for_completion(&clk_completion);
+			if (WAIT_TRIES == ++tries)
+				break;
+		} else
+			break;
+	}
+
+	if (i == WAIT_TRIES) {
+		pr_err("%s: failed to lock clocks; cyclical dependency?\n",
+				__func__);
+		return ret;
+	}
+
 	/* propagate PRE_RATE_CHANGE notifications */
 	if (clk->notifier_count)
 		ret = __clk_speculate_rates(clk, parent->rate);
 
 	/* abort if a driver objects */
-	if (ret == NOTIFY_STOP)
+	if (ret & NOTIFY_STOP_MASK) {
+		ret = notifier_to_errno(ret);
 		goto out;
+	}
 
 	/* only re-parent if the clock is not in use */
 	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
@@ -1171,6 +1442,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 	__clk_reparent(clk, parent);
 
 out:
+	mutex_lock(&prepare_lock);
+	clk_unlock_subtree(clk);
 	mutex_unlock(&prepare_lock);
 
 	return ret;
@@ -1307,6 +1580,9 @@ int __clk_init(struct device *dev, struct clk *clk)
 	if (clk->ops->init)
 		clk->ops->init(clk->hw);
 
+	/* everything looks good, mark this clock's state as ready */
+	clk->state = UNLOCKED;
+
 	clk_debug_register(clk);
 
 out:
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 9c7f580..751ad6c 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -41,6 +41,7 @@ struct clk {
 	struct hlist_head	children;
 	struct hlist_node	child_node;
 	unsigned int		notifier_count;
+	enum {UNLOCKED, LOCKED}	state;
 #ifdef CONFIG_COMMON_CLK_DEBUG
 	struct dentry		*dentry;
 #endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fa..b3eb074 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -344,8 +344,8 @@ struct clk *__clk_lookup(const char *name);
 /*
  * FIXME clock api without lock protection
  */
-int __clk_prepare(struct clk *clk);
-void __clk_unprepare(struct clk *clk);
+int __clk_prepare(struct clk *clk, struct clk *top);
+void __clk_unprepare(struct clk *clk, struct clk *top);
 void __clk_reparent(struct clk *clk, struct clk *new_parent);
 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
 
-- 
1.7.9.5



From mturquette at linaro.org  Wed Aug 15 19:43:32 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 15 Aug 2012 16:43:32 -0700
Subject: [PATCH v2 2/4] [RFC] clk: notifier handler for dynamic voltage scaling
In-Reply-To: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
Message-ID: <1345074214-17531-3-git-send-email-mturquette@linaro.org>

Dynamic voltage and frequency scaling (dvfs) is a common power saving
technique in many of today's modern processors.  This patch introduces a
common clk rate-change notifier handler which scales voltage
appropriately whenever clk_set_rate is called on an affected clock.

There are three prerequisites to using this feature:

1) the affected clocks must be using the common clk framework
2) voltage must be scaled using the regulator framework
3) clock frequency and regulator voltage values must be paired via the
OPP library

If your platform or device meets these requirements then using the
notifier handler is easy.  A struct device is used as the basis for
performing initial look-ups for clocks via clk_get and regulators via
regulator_get.  This means that notifiers and subscribed on a per-device
basis and multiple devices can have notifiers subscribed to the same
clock.  Put another way, the voltage chosen for a rail during a call to
clk_set_rate is a function of the device, not the clock.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
---
 drivers/clk/Makefile |    3 +-
 drivers/clk/dvfs.c   |  116 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk.h  |   27 +++++++++++-
 3 files changed, 144 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/dvfs.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 02ffdf6..8f1faa0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,7 +1,8 @@
 # common clock types
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
-				   clk-mux.o clk-divider.o clk-fixed-factor.o
+				   clk-mux.o clk-divider.o clk-fixed-factor.o \
+				   dvfs.o
 # SoCs specific
 obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
diff --git a/drivers/clk/dvfs.c b/drivers/clk/dvfs.c
new file mode 100644
index 0000000..9f5d1ba
--- /dev/null
+++ b/drivers/clk/dvfs.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Helper functions for dynamic voltage & frequency transitions using
+ * the OPP library.
+ */
+
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/opp.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+/*
+ * XXX clk, regulator & tolerance should be stored in the OPP table?
+ */
+struct dvfs_info {
+	struct device *dev;
+	struct clk *clk;
+	struct regulator *reg;
+	int tol;
+	/* FIXME struct device_opp *dev_opp */
+	struct notifier_block nb;
+};
+
+#define to_dvfs_info(_nb) container_of(_nb, struct dvfs_info, nb)
+
+static int dvfs_clk_notifier_handler(struct notifier_block *nb,
+		unsigned long flags, void *data)
+{
+	struct clk_notifier_data *cnd = data;
+	struct dvfs_info *di = to_dvfs_info(nb);
+	int ret, volt_new, volt_old;
+	struct opp *opp;
+
+	volt_old = regulator_get_voltage(di->reg);
+	opp = opp_find_freq_floor(di->dev, &cnd->new_rate);
+	volt_new = opp_get_voltage(opp);
+
+	/* scaling up?  scale voltage before frequency */
+	if (flags & PRE_RATE_CHANGE && cnd->new_rate > cnd->old_rate) {
+		dev_dbg(di->dev, "%s: %d mV --> %d mV\n",
+				__func__, volt_old, volt_new);
+
+		ret = regulator_set_voltage_tol(di->reg, volt_new, di->tol);
+
+		if (ret) {
+			dev_warn(di->dev, "%s: unable to scale voltage up.\n",
+				 __func__);
+			return notifier_from_errno(ret);
+		}
+	}
+
+	/* scaling down?  scale voltage after frequency */
+	if (flags & POST_RATE_CHANGE && cnd->new_rate < cnd->old_rate) {
+		dev_dbg(di->dev, "%s: %d mV --> %d mV\n",
+				__func__, volt_old, volt_new);
+
+		ret = regulator_set_voltage_tol(di->reg, volt_new, di->tol);
+
+		if (ret) {
+			dev_warn(di->dev, "%s: unable to scale voltage down.\n",
+				 __func__);
+			return notifier_from_errno(ret);
+		}
+	}
+
+	return NOTIFY_OK;
+}
+
+struct dvfs_info *dvfs_clk_notifier_register(struct dvfs_info_init *dii)
+{
+	struct dvfs_info *di;
+	int ret = 0;
+
+	if (!dii)
+		return ERR_PTR(-EINVAL);
+
+	di = kzalloc(sizeof(struct dvfs_info), GFP_KERNEL);
+	if (!di)
+		return ERR_PTR(-ENOMEM);
+
+	di->dev = dii->dev;
+	di->clk = clk_get(di->dev, dii->con_id);
+	if (IS_ERR(di->clk))
+		return ERR_PTR(-ENOMEM);
+	di->reg = regulator_get(di->dev, dii->reg_id);
+	if (IS_ERR(di->reg))
+		return ERR_PTR(-ENOMEM);
+	di->tol = dii->tol;
+	di->nb.notifier_call = dvfs_clk_notifier_handler;
+
+	ret = clk_notifier_register(di->clk, &di->nb);
+
+	if (ret) {
+		kfree(di);
+		return ERR_PTR(ret);
+	}
+
+	return di;
+}
+EXPORT_SYMBOL_GPL(dvfs_clk_notifier_register);
+
+void dvfs_clk_notifier_unregister(struct dvfs_info *di)
+{
+	clk_notifier_unregister(di->clk, &di->nb);
+	clk_put(di->clk);
+	regulator_put(di->reg);
+	kfree(di);
+}
+EXPORT_SYMBOL_GPL(dvfs_clk_notifier_unregister);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 6587b52..643376b 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -78,9 +78,34 @@ struct clk_notifier_data {
 	unsigned long		new_rate;
 };
 
-int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
+/**
+ * struct dvfs_info_init - data needs to initialize struct dvfs_info
+ * @dev:	device related to this frequency-voltage pair
+ * @con_id:	string name of clock connection
+ * @reg_id:	string name of regulator
+ * @tol:	voltage tolerance for this device
+ *
+ * Provides the data needed to register a common dvfs sequence in a clk
+ * notifier handler.  The clk and regulator lookups are stored in a
+ * private struct and the notifier handler is registered with the clk
+ * framework with a call to dvfs_clk_notifier_register.
+ *
+ * FIXME stuffing @tol here is a hack.  It belongs in the opp table.
+ * Maybe clk & regulator will also live in the opp table some day.
+ */
+struct dvfs_info_init {
+	struct device *dev;
+	const char *con_id;
+	const char *reg_id;
+	int tol;
+};
+
+struct dvfs_info;
 
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
+struct dvfs_info *dvfs_clk_notifier_register(struct dvfs_info_init *dii);
+void dvfs_clk_notifier_unregister(struct dvfs_info *di);
 
 #endif
 
-- 
1.7.9.5



From alanbutty12 at gmail.com  Wed Aug 15 19:52:18 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Thu, 16 Aug 2012 00:52:18 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120815234159.GK22226@titan.lakedaemon.net>
References: <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
 <20120815234159.GK22226@titan.lakedaemon.net>
Message-ID: <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>

On 16 August 2012 00:41, Jason Cooper <jason at lakedaemon.net> wrote:
> On Thu, Aug 16, 2012 at 12:34:46AM +0100, alan butler wrote:
>> On 16 August 2012 00:12, alan butler <alanbutty12 at gmail.com> wrote:
>> > On 16 August 2012 00:02, alan butler <alanbutty12 at gmail.com> wrote:
>> >> On 15 August 2012 23:16, Andrew Lunn <andrew at lunn.ch> wrote:
>> >>> On Wed, Aug 15, 2012 at 10:57:27PM +0100, alan butler wrote:
>> >>>> On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
>> >>>> >> That would be great i just need to recreate the patch with those
>> >>>> >> changes but i was talking with jason cooper i believe and he said to
>> >>>> >> put the buttons for the device in the dts file and im working on that
>> >>>> >> but the kernel panics
>> >>>> >
>> >>>> > Please show us the panic.
>> >>>> >
>> >>>> >        Andrew
>> >>>>
>> >>>> i sent it to jason a lil bit earlier but i guess i must of forgotten
>> >>>> to cc the list on the last message or 2 but here is the panic again:
>> >>>>
>> >>>> [    5.976074] Key type dns_resolver registered
>> >>>> [    5.981782] Unable to handle kernel NULL pointer dereference at
>> >>>> virtual address 00000004
>> >>>> [    5.989932] pgd = c0004000
>> >>>> [    5.992649] [00000004] *pgd=00000000
>> >>>> [    5.996247] Internal error: Oops: 805 [#1] ARM
>> >>>> [    6.000707] Modules linked in:
>> >>>> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
>> >>>> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
>> >>>
>> >>> You might want to scatter some printk() in gpio_keys_probe() and see
>> >>> where it panics. It will probably then be clear what is wrong.
>> >>>
>> >>>       Andrew
>> >>
>> >> where do i find the gpio_keys_probe() ?
>> >
>> > i found the gpio_keys_probe() and it seems that it is failing in this
>> > piece of code i put a printk() before and after it and it didnt reach
>> > the printk after it:
>> >
>> > if (!pdata) {
>> >                 pdata = gpio_keys_get_devtree_pdata(dev);
>> >                 if (IS_ERR(pdata))
>> >                         return PTR_ERR(pdata);
>> >         }
>> >
>> >         ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
>> >                         pdata->nbuttons * sizeof(struct gpio_button_data),
>> >                         GFP_KERNEL);
>> >         input = input_allocate_device();
>> >         if (!ddata || !input) {
>> >                 dev_err(dev, "failed to allocate state\n");
>> >                 error = -ENOMEM;
>> >                 goto fail1;
>> >         }
>>
>> actualy it seems to not be getting past this piece of code in what i
>> posted before:
>>
>> if (!pdata) {
>>               pdata = gpio_keys_get_devtree_pdata(dev);
>>               if (IS_ERR(pdata))
>>                       return PTR_ERR(pdata);
>>       }
>
> That means gpio_keys_get_devtree_pdata() is returning an error.  Have
> you tried 'linux,input-type = <0x05>;' ?
>
> thx,
>
> Jason.

'inux,input-type = <0x05>' instead of 'linux,code = <...>' in the dts?
no i havent tried will give it a try now.


From paul at pwsan.com  Wed Aug 15 20:48:13 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 15 Aug 2012 18:48:13 -0600 (MDT)
Subject: [PATCH v5 0/8] ARM: OMAP2+: PM: introduce the power domains
 functional states
In-Reply-To: <CAMQu2gxznhsbK3--nyQmYdHqyGjwpCSa3CJx8aYpF4wwR1qBSg@mail.gmail.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
 <CAMQu2gxznhsbK3--nyQmYdHqyGjwpCSa3CJx8aYpF4wwR1qBSg@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1208151842380.8833@utopia.booyaka.com>

Hi Santosh,

On Wed, 15 Aug 2012, Shilimkar, Santosh wrote:

> On Wed, Aug 15, 2012 at 3:32 PM, Jean Pihet <jean.pihet at newoldbits.com> wrote:
>
> I didn't find any mention here about why are we going in this path and not
> in the direction proposed in another RFC [1]
> I have already given my comments[2] against the introduction of another PD
> layer which can be avoided easily as demonstrated by the RFC[1]. The comments
> are still applicable for this series too.
> 
> We really need to reduce OMAP specific framework overhead and
> move towards more generic PM frameworks. For me, this series is
> a step back-ward from that direction. Am really sorry for being critical
> again but I remain unconvinced about this series and the problem it
> is trying to solve.
> 
> May be you have valid reasons not to follow the approach in [1] and in
> that case, it will be good to clarify that so that some of us get
> to know your rationale.

I've asked Jean to handle the work of evaluating and/or integrating any 
feedback from you and Rajendra into this series.  Jean, has this latest 
series fully considered those issues?  Or are there still some areas of 
misalignment / lack of clarity?

Anyway.  If there's a problem with this process, it sounds like you, 
Rajendra, Jean, Beno?t and I should schedule some time to talk over the 
same issues that you discussed with me on the phone.  Perhaps next week?


- Paul

From zhangfei.gao at marvell.com  Wed Aug 15 22:23:24 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Thu, 16 Aug 2012 10:23:24 +0800
Subject: [PATCH v4 0/2] dmaengine: add support mmp-pdma
Message-ID: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>

v3-v4
Set DMA_MEM_TO_MEM as default setting for memcpy, Suggested by Russell.
"By default, any channel being asked to do memcpy
should deal with the channel configuration itself and not require it
to be set"

v2->v3 
Use "#dma-channels", instead of "dma-channels", suggested by Arnd

v1->v2
Sync with Arnd and Haojoan, change compatible name to "marvell,pdma-1.0"
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
Use IP name rather than platform name

Also change "marvell,mmp-adma" to "marvell,adma-1.0"

v0->v1
Update dt member and desc according to Arnd's suggestion
Use dma_slave_config.slave_id to transfer drcmr followed Vinod's suggestion

mmp-pdma is added under dmaengine framework.
The final purpose is replacing arch/arm/plat-pxa/dma.c

Test on pxa910 with pxa3xx-nand and dmatest.ko

Zhangfei Gao (2):
  dmaengine: mmp-pdma support
  dmaengine: mmp_tdma: add dt support

 Documentation/devicetree/bindings/dma/mmp-dma.txt |   75 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/mmp_pdma.c                            |  876 +++++++++++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +-
 include/linux/platform_data/mmp_dma.h             |   19 +
 6 files changed, 1009 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h



From zhangfei.gao at marvell.com  Wed Aug 15 22:23:25 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Thu, 16 Aug 2012 10:23:25 +0800
Subject: [PATCH v4 1/2] dmaengine: mmp-pdma support
In-Reply-To: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
References: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1345083806-24588-2-git-send-email-zhangfei.gao@marvell.com>

1. virtual channel vs. physical channel
Virtual channel is managed by dmaengine
Physical channel handling resource, such as irq
Physical channel is alloced dynamically as descending priority,
freed immediately when irq done.
The availble highest priority physically channel will alwayes be alloced

Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel

2. list: running list & pending list
submit: desc list -> pending list
issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
irq: free running list (IDLE)
     check pendlist -> pending list -> running list; free pending list (RUN)

3. irq:
Each list generate one irq, calling callback
One list may contain several desc chain, in such case, make sure only the last desc list generate irq.

4. async
Submit will add desc chain to pending list, which can be multi-called
If multi desc chain is submitted, only the last desc would generate irq -> call back
If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
If RUN, irq will start pending list

5. test
5.1 pxa3xx_nand on pxa910
5.2 insmod dmatest.ko (threads_per_chan=y)
By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   45 ++
 drivers/dma/Kconfig                               |    7 +
 drivers/dma/Makefile                              |    1 +
 drivers/dma/mmp_pdma.c                            |  875 +++++++++++++++++++++
 include/linux/platform_data/mmp_dma.h             |   19 +
 5 files changed, 947 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/mmp-dma.txt
 create mode 100644 drivers/dma/mmp_pdma.c
 create mode 100644 include/linux/platform_data/mmp_dma.h

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
new file mode 100644
index 0000000..cbf40d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -0,0 +1,45 @@
+* MARVELL MMP DMA controller
+
+Marvell Peripheral DMA Controller
+Used platfroms: pxa688, pxa910, pxa3xx, etc
+
+Required properties:
+- compatible: Should be "marvell,pdma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for pdma device
+- #dma-channels: Number of DMA channels supported by the controller.
+
+"marvell,pdma-1.0"
+Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
+
+Examples:
+
+/*
+ * Each channel has specific irq
+ * ICU parse out irq channel from ICU register,
+ * while DMA controller may not able to distinguish the irq channel
+ * Using this method, interrupt-parent is required as demuxer
+ * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
+ * 18~21 is ADMA irq
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+	      interrupt-parent = <&intcmux32>;
+	      #dma-channels = <16>;
+      };
+
+/*
+ * One irq for all channels
+ * Dmaengine driver (DMA controller) distinguish irq channel via
+ * parsing internal register
+ */
+pdma: dma-controller at d4000000 {
+	      compatible = "marvell,pdma-1.0";
+	      reg = <0xd4000000 0x10000>;
+	      interrupts = <47>;
+	      #dma-channels = <16>;
+      };
+
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..f05cb17 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -292,6 +292,13 @@ config DMA_OMAP
 	select DMA_ENGINE
 	select DMA_VIRTUAL_CHANNELS
 
+config MMP_PDMA
+	bool "MMP PDMA support"
+	depends on (ARCH_MMP || ARCH_PXA)
+	select DMA_ENGINE
+	help
+	  Support the MMP PDMA engine for PXA and MMP platfrom.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..6a3f50c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
+obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
new file mode 100644
index 0000000..14da1f4
--- /dev/null
+++ b/drivers/dma/mmp_pdma.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/platform_data/mmp_dma.h>
+#include <linux/dmapool.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+
+#include "dmaengine.h"
+
+#define DCSR		0x0000
+#define DALGN		0x00a0
+#define DINT		0x00f0
+#define DDADR		0x0200
+#define DSADR		0x0204
+#define DTADR		0x0208
+#define DCMD		0x020c
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN	(1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR	(1 << 9)        /* The end of Receive */
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x1f		/* mask for Channel Number (read / write) */
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+#define PDMA_ALIGNMENT		3
+#define PDMA_MAX_DESC_BYTES	0x1000
+
+struct mmp_pdma_desc_hw {
+	u32 ddadr;	/* Points to the next descriptor + flags */
+	u32 dsadr;	/* DSADR value for the current transfer */
+	u32 dtadr;	/* DTADR value for the current transfer */
+	u32 dcmd;	/* DCMD value for the current transfer */
+} __aligned(32);
+
+struct mmp_pdma_desc_sw {
+	struct mmp_pdma_desc_hw desc;
+	struct list_head node;
+	struct list_head tx_list;
+	struct dma_async_tx_descriptor async_tx;
+};
+
+struct mmp_pdma_phy;
+
+struct mmp_pdma_chan {
+	struct device *dev;
+	struct dma_chan chan;
+	struct dma_async_tx_descriptor desc;
+	struct mmp_pdma_phy *phy;
+	enum dma_transfer_direction dir;
+
+	/* channel's basic info */
+	struct tasklet_struct tasklet;
+	u32 dcmd;
+	u32 drcmr;
+	u32 dev_addr;
+
+	/* list for desc */
+	spinlock_t desc_lock;		/* Descriptor list lock */
+	struct list_head chain_pending;	/* Link descriptors queue for pending */
+	struct list_head chain_running;	/* Link descriptors queue for running */
+	bool idle;			/* channel statue machine */
+
+	struct dma_pool *desc_pool;	/* Descriptors pool */
+};
+
+struct mmp_pdma_phy {
+	int idx;
+	void __iomem *base;
+	struct mmp_pdma_chan *vchan;
+};
+
+struct mmp_pdma_device {
+	int				dma_channels;
+	void __iomem			*base;
+	struct device			*dev;
+	struct dma_device		device;
+	struct mmp_pdma_phy		*phy;
+};
+
+#define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx)
+#define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node)
+#define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan)
+#define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device)
+
+static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
+{
+	u32 reg = (phy->idx << 4) + DDADR;
+
+	writel(addr, phy->base + reg);
+}
+
+static void enable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (!phy->vchan)
+		return;
+
+	reg = phy->vchan->drcmr;
+	reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
+	writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
+
+	reg = (phy->idx << 2) + DCSR;
+	writel(readl(phy->base + reg) | DCSR_RUN,
+					phy->base + reg);
+}
+
+static void disable_chan(struct mmp_pdma_phy *phy)
+{
+	u32 reg;
+
+	if (phy) {
+		reg = (phy->idx << 2) + DCSR;
+		writel(readl(phy->base + reg) & ~DCSR_RUN,
+						phy->base + reg);
+	}
+}
+
+static int clear_chan_irq(struct mmp_pdma_phy *phy)
+{
+	u32 dcsr;
+	u32 dint = readl(phy->base + DINT);
+	u32 reg = (phy->idx << 2) + DCSR;
+
+	if (dint & BIT(phy->idx)) {
+		/* clear irq */
+		dcsr = readl(phy->base + reg);
+		writel(dcsr, phy->base + reg);
+		if ((dcsr & DCSR_BUSERR) && (phy->vchan))
+			dev_warn(phy->vchan->dev, "DCSR_BUSERR\n");
+		return 0;
+	}
+	return -EAGAIN;
+}
+
+static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_phy *phy = dev_id;
+
+	if (clear_chan_irq(phy) == 0) {
+		tasklet_schedule(&phy->vchan->tasklet);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id)
+{
+	struct mmp_pdma_device *pdev = dev_id;
+	struct mmp_pdma_phy *phy;
+	u32 dint = readl(pdev->base + DINT);
+	int i, ret;
+	int irq_num = 0;
+
+	while (dint) {
+		i = __ffs(dint);
+		dint &= (dint - 1);
+		phy = &pdev->phy[i];
+		ret = mmp_pdma_chan_handler(irq, phy);
+		if (ret == IRQ_HANDLED)
+			irq_num++;
+	}
+
+	if (irq_num)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+/* lookup free phy channel as descending priority */
+static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan)
+{
+	int prio, i;
+	struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device);
+	struct mmp_pdma_phy *phy;
+
+	/*
+	 * dma channel priorities
+	 * ch 0 - 3,  16 - 19  <--> (0)
+	 * ch 4 - 7,  20 - 23  <--> (1)
+	 * ch 8 - 11, 24 - 27  <--> (2)
+	 * ch 12 - 15, 28 - 31  <--> (3)
+	 */
+	for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) {
+		for (i = 0; i < pdev->dma_channels; i++) {
+			if (prio != ((i & 0xf) >> 2))
+				continue;
+			phy = &pdev->phy[i];
+			if (!phy->vchan) {
+				phy->vchan = pchan;
+				return phy;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+/* desc->tx_list ==> pending list */
+static void append_pending_queue(struct mmp_pdma_chan *chan,
+					struct mmp_pdma_desc_sw *desc)
+{
+	struct mmp_pdma_desc_sw *tail =
+				to_mmp_pdma_desc(chan->chain_pending.prev);
+
+	if (list_empty(&chan->chain_pending))
+		goto out_splice;
+
+	/* one irq per queue, even appended */
+	tail->desc.ddadr = desc->async_tx.phys;
+	tail->desc.dcmd &= ~DCMD_ENDIRQEN;
+
+	/* softly link to pending list */
+out_splice:
+	list_splice_tail_init(&desc->tx_list, &chan->chain_pending);
+}
+
+/**
+ * start_pending_queue - transfer any pending transactions
+ * pending list ==> running list
+ */
+static void start_pending_queue(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+
+	/* still in running, irq will start the pending list */
+	if (!chan->idle) {
+		dev_dbg(chan->dev, "DMA controller still busy\n");
+		return;
+	}
+
+	if (list_empty(&chan->chain_pending)) {
+		/* chance to re-fetch phy channel with higher prio */
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		dev_dbg(chan->dev, "no pending list\n");
+		return;
+	}
+
+	if (!chan->phy) {
+		chan->phy = lookup_phy(chan);
+		if (!chan->phy) {
+			dev_dbg(chan->dev, "no free dma channel\n");
+			return;
+		}
+	}
+
+	/*
+	 * pending -> running
+	 * reintilize pending list
+	 */
+	desc = list_first_entry(&chan->chain_pending,
+				struct mmp_pdma_desc_sw, node);
+	list_splice_tail_init(&chan->chain_pending, &chan->chain_running);
+
+	/*
+	 * Program the descriptor's address into the DMA controller,
+	 * then start the DMA transaction
+	 */
+	set_desc(chan->phy, desc->async_tx.phys);
+	enable_chan(chan->phy);
+	chan->idle = false;
+}
+
+
+/* desc->tx_list ==> pending list */
+static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan);
+	struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx);
+	struct mmp_pdma_desc_sw *child;
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	list_for_each_entry(child, &desc->tx_list, node) {
+		cookie = dma_cookie_assign(&child->async_tx);
+	}
+
+	append_pending_queue(chan, desc);
+
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return cookie;
+}
+
+struct mmp_pdma_desc_sw *mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan)
+{
+	struct mmp_pdma_desc_sw *desc;
+	dma_addr_t pdesc;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
+	if (!desc) {
+		dev_err(chan->dev, "out of memory for link descriptor\n");
+		return NULL;
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	INIT_LIST_HEAD(&desc->tx_list);
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
+	/* each desc has submit */
+	desc->async_tx.tx_submit = mmp_pdma_tx_submit;
+	desc->async_tx.phys = pdesc;
+
+	return desc;
+}
+
+/**
+ * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
+ *
+ * This function will create a dma pool for descriptor allocation.
+ * Request irq only when channel is requested
+ * Return - The number of allocated descriptors.
+ */
+
+static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+
+	if (chan->desc_pool)
+		return 1;
+
+	chan->desc_pool =
+		dma_pool_create(dev_name(&dchan->dev->device), chan->dev,
+				  sizeof(struct mmp_pdma_desc_sw),
+				  __alignof__(struct mmp_pdma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate descriptor pool\n");
+		return -ENOMEM;
+	}
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	chan->idle = true;
+	chan->dev_addr = 0;
+	return 1;
+}
+
+static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan,
+				  struct list_head *list)
+{
+	struct mmp_pdma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void mmp_pdma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+	mmp_pdma_free_desc_list(chan, &chan->chain_running);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+	chan->idle = true;
+	chan->dev_addr = 0;
+	if (chan->phy) {
+		chan->phy->vchan = NULL;
+		chan->phy = NULL;
+	}
+	return;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_memcpy(struct dma_chan *dchan,
+	dma_addr_t dma_dst, dma_addr_t dma_src,
+	size_t len, unsigned long flags)
+{
+	struct mmp_pdma_chan *chan;
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
+	size_t copy = 0;
+
+	if (!dchan)
+		return NULL;
+
+	if (!len)
+		return NULL;
+
+	chan = to_mmp_pdma_chan(dchan);
+
+	if (!chan->dir) {
+		chan->dir = DMA_MEM_TO_MEM;
+		chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR;
+		chan->dcmd |= DCMD_BURST32;
+	}
+
+	do {
+		/* Allocate the link descriptor from DMA pool */
+		new = mmp_pdma_alloc_descriptor(chan);
+		if (!new) {
+			dev_err(chan->dev, "no memory for desc\n");
+			goto fail;
+		}
+
+		copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
+
+		new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
+		new->desc.dsadr = dma_src;
+		new->desc.dtadr = dma_dst;
+
+		if (!first)
+			first = new;
+		else
+			prev->desc.ddadr = new->async_tx.phys;
+
+		new->async_tx.cookie = 0;
+		async_tx_ack(&new->async_tx);
+
+		prev = new;
+		len -= copy;
+
+		if (chan->dir == DMA_MEM_TO_DEV) {
+			dma_src += copy;
+		} else if (chan->dir == DMA_DEV_TO_MEM) {
+			dma_dst += copy;
+		} else if (chan->dir == DMA_MEM_TO_MEM) {
+			dma_src += copy;
+			dma_dst += copy;
+		}
+
+		/* Insert the link descriptor to the LD ring */
+		list_add_tail(&new->node, &first->tx_list);
+	} while (len);
+
+	first->async_tx.flags = flags; /* client is in control of this ack */
+	first->async_tx.cookie = -EBUSY;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *
+mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
+			 unsigned int sg_len, enum dma_transfer_direction dir,
+			 unsigned long flags, void *context)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
+	size_t len, avail;
+	struct scatterlist *sg;
+	dma_addr_t addr;
+	int i;
+
+	if ((sgl == NULL) || (sg_len == 0))
+		return NULL;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		addr = sg_dma_address(sg);
+		avail = sg_dma_len(sgl);
+
+		do {
+			len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
+
+			/* allocate and populate the descriptor */
+			new = mmp_pdma_alloc_descriptor(chan);
+			if (!new) {
+				dev_err(chan->dev, "no memory for desc\n");
+				goto fail;
+			}
+
+			new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
+			if (dir == DMA_MEM_TO_DEV) {
+				new->desc.dsadr = addr;
+				new->desc.dtadr = chan->dev_addr;
+			} else {
+				new->desc.dsadr = chan->dev_addr;
+				new->desc.dtadr = addr;
+			}
+
+			if (!first)
+				first = new;
+			else
+				prev->desc.ddadr = new->async_tx.phys;
+
+			new->async_tx.cookie = 0;
+			async_tx_ack(&new->async_tx);
+			prev = new;
+
+			/* Insert the link descriptor to the LD ring */
+			list_add_tail(&new->node, &first->tx_list);
+
+			/* update metadata */
+			addr += len;
+			avail -= len;
+		} while (avail);
+	}
+
+	first->async_tx.cookie = -EBUSY;
+	first->async_tx.flags = flags;
+
+	/* last desc and fire IRQ */
+	new->desc.ddadr = DDADR_STOP;
+	new->desc.dcmd |= DCMD_ENDIRQEN;
+
+	return &first->async_tx;
+
+fail:
+	if (first)
+		mmp_pdma_free_desc_list(chan, &first->tx_list);
+	return NULL;
+}
+
+static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd,
+		unsigned long arg)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	struct dma_slave_config *cfg = (void *)arg;
+	unsigned long flags;
+	int ret = 0;
+	u32 maxburst = 0, addr = 0;
+	enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+
+	if (!dchan)
+		return -EINVAL;
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		disable_chan(chan->phy);
+		if (chan->phy) {
+			chan->phy->vchan = NULL;
+			chan->phy = NULL;
+		}
+		spin_lock_irqsave(&chan->desc_lock, flags);
+		mmp_pdma_free_desc_list(chan, &chan->chain_pending);
+		mmp_pdma_free_desc_list(chan, &chan->chain_running);
+		spin_unlock_irqrestore(&chan->desc_lock, flags);
+		chan->idle = true;
+		break;
+	case DMA_SLAVE_CONFIG:
+		if (cfg->direction == DMA_DEV_TO_MEM) {
+			chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
+			maxburst = cfg->src_maxburst;
+			width = cfg->src_addr_width;
+			addr = cfg->src_addr;
+		} else if (cfg->direction == DMA_MEM_TO_DEV) {
+			chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
+			maxburst = cfg->dst_maxburst;
+			width = cfg->dst_addr_width;
+			addr = cfg->dst_addr;
+		}
+
+		if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+			chan->dcmd |= DCMD_WIDTH1;
+		else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+			chan->dcmd |= DCMD_WIDTH2;
+		else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
+			chan->dcmd |= DCMD_WIDTH4;
+
+		if (maxburst == 8)
+			chan->dcmd |= DCMD_BURST8;
+		else if (maxburst == 16)
+			chan->dcmd |= DCMD_BURST16;
+		else if (maxburst == 32)
+			chan->dcmd |= DCMD_BURST32;
+
+		if (cfg) {
+			chan->dir = cfg->direction;
+			chan->drcmr = cfg->slave_id;
+		}
+		chan->dev_addr = addr;
+		break;
+	default:
+		return -ENOSYS;
+	}
+
+	return ret;
+}
+
+static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan,
+			dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	enum dma_status ret;
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	ret = dma_cookie_status(dchan, cookie, txstate);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	return ret;
+}
+
+/**
+ * mmp_pdma_issue_pending - Issue the DMA start command
+ * pending list ==> running list
+ */
+static void mmp_pdma_issue_pending(struct dma_chan *dchan)
+{
+	struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+}
+
+/*
+ * dma_do_tasklet
+ * Do call back
+ * Start pending list
+ */
+static void dma_do_tasklet(unsigned long data)
+{
+	struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data;
+	struct mmp_pdma_desc_sw *desc, *_desc;
+	LIST_HEAD(chain_cleanup);
+	unsigned long flags;
+
+	/* submit pending list; callback for each desc; free desc */
+
+	spin_lock_irqsave(&chan->desc_lock, flags);
+
+	/* update the cookie if we have some descriptors to cleanup */
+	if (!list_empty(&chan->chain_running)) {
+		dma_cookie_t cookie;
+
+		desc = to_mmp_pdma_desc(chan->chain_running.prev);
+		cookie = desc->async_tx.cookie;
+		dma_cookie_complete(&desc->async_tx);
+
+		dev_dbg(chan->dev, "completed_cookie=%d\n", cookie);
+	}
+
+	/*
+	 * move the descriptors to a temporary list so we can drop the lock
+	 * during the entire cleanup operation
+	 */
+	list_splice_tail_init(&chan->chain_running, &chain_cleanup);
+
+	/* the hardware is now idle and ready for more */
+	chan->idle = true;
+
+	/* Start any pending transactions automatically */
+	start_pending_queue(chan);
+	spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+	/* Run the callback for each descriptor, in order */
+	list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) {
+		struct dma_async_tx_descriptor *txd = &desc->async_tx;
+
+		/* Remove from the list of transactions */
+		list_del(&desc->node);
+		/* Run the link descriptor callback function */
+		if (txd->callback)
+			txd->callback(txd->callback_param);
+
+		dma_pool_free(chan->desc_pool, desc, txd->phys);
+	}
+}
+
+static int __devexit mmp_pdma_remove(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev = platform_get_drvdata(op);
+
+	dma_async_device_unregister(&pdev->device);
+	return 0;
+}
+
+static int __devinit mmp_pdma_chan_init(struct mmp_pdma_device *pdev,
+							int idx, int irq)
+{
+	struct mmp_pdma_phy *phy  = &pdev->phy[idx];
+	struct mmp_pdma_chan *chan;
+	int ret;
+
+	chan = devm_kzalloc(pdev->dev,
+			sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (chan == NULL)
+		return -ENOMEM;
+
+	phy->idx = idx;
+	phy->base = pdev->base;
+
+	if (irq) {
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
+		if (ret) {
+			dev_err(pdev->dev, "channel request irq fail!\n");
+			return ret;
+		}
+	}
+
+	spin_lock_init(&chan->desc_lock);
+	chan->dev = pdev->dev;
+	chan->chan.device = &pdev->device;
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+	INIT_LIST_HEAD(&chan->chain_pending);
+	INIT_LIST_HEAD(&chan->chain_running);
+
+	/* register virt channel to dma engine */
+	list_add_tail(&chan->chan.device_node,
+			&pdev->device.channels);
+
+	return 0;
+}
+
+static struct of_device_id mmp_pdma_dt_ids[] = {
+	{ .compatible = "marvell,pdma-1.0", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
+
+static int __devinit mmp_pdma_probe(struct platform_device *op)
+{
+	struct mmp_pdma_device *pdev;
+	const struct of_device_id *of_id;
+	struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
+	struct resource *iores;
+	int i, ret, irq = 0;
+	int dma_channels = 0, irq_num = 0;
+
+	pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+	pdev->dev = &op->dev;
+
+	iores = platform_get_resource(op, IORESOURCE_MEM, 0);
+	if (!iores)
+		return -EINVAL;
+
+	pdev->base = devm_request_and_ioremap(pdev->dev, iores);
+	if (!pdev->base)
+		return -EADDRNOTAVAIL;
+
+	of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev);
+	if (of_id)
+		of_property_read_u32(pdev->dev->of_node,
+				"#dma-channels", &dma_channels);
+	else if (pdata && pdata->dma_channels)
+		dma_channels = pdata->dma_channels;
+	else
+		dma_channels = 32;	/* default 32 channel */
+	pdev->dma_channels = dma_channels;
+
+	for (i = 0; i < dma_channels; i++) {
+		if (platform_get_irq(op, i) > 0)
+			irq_num++;
+	}
+
+	pdev->phy = devm_kzalloc(pdev->dev,
+		dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL);
+	if (pdev->phy == NULL)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&pdev->device.channels);
+
+	if (irq_num != dma_channels) {
+		/* all chan share one irq, demux inside */
+		irq = platform_get_irq(op, 0);
+		ret = devm_request_irq(pdev->dev, irq,
+			mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < dma_channels; i++) {
+		irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
+		ret = mmp_pdma_chan_init(pdev, i, irq);
+		if (ret)
+			return ret;
+	}
+
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask);
+	dma_cap_set(DMA_SLAVE, pdev->device.cap_mask);
+	pdev->device.dev = &op->dev;
+	pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources;
+	pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources;
+	pdev->device.device_tx_status = mmp_pdma_tx_status;
+	pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy;
+	pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg;
+	pdev->device.device_issue_pending = mmp_pdma_issue_pending;
+	pdev->device.device_control = mmp_pdma_control;
+	pdev->device.copy_align = PDMA_ALIGNMENT;
+
+	if (pdev->dev->coherent_dma_mask)
+		dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
+	else
+		dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
+
+	ret = dma_async_device_register(&pdev->device);
+	if (ret) {
+		dev_err(pdev->device.dev, "unable to register\n");
+		return ret;
+	}
+
+	dev_info(pdev->device.dev, "initialized\n");
+	return 0;
+}
+
+static const struct platform_device_id mmp_pdma_id_table[] = {
+	{ "mmp-pdma", },
+	{ },
+};
+
+static struct platform_driver mmp_pdma_driver = {
+	.driver		= {
+		.name	= "mmp-pdma",
+		.owner  = THIS_MODULE,
+		.of_match_table = mmp_pdma_dt_ids,
+	},
+	.id_table	= mmp_pdma_id_table,
+	.probe		= mmp_pdma_probe,
+	.remove		= __devexit_p(mmp_pdma_remove),
+};
+
+module_platform_driver(mmp_pdma_driver);
+
+MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver");
+MODULE_AUTHOR("Marvell International Ltd.");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/platform_data/mmp_dma.h b/include/linux/platform_data/mmp_dma.h
new file mode 100644
index 0000000..2a330ec
--- /dev/null
+++ b/include/linux/platform_data/mmp_dma.h
@@ -0,0 +1,19 @@
+/*
+ *  MMP Platform DMA Management
+ *
+ *  Copyright (c) 2011 Marvell Semiconductors Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#ifndef MMP_DMA_H
+#define MMP_DMA_H
+
+struct mmp_dma_platdata {
+	int dma_channels;
+};
+
+#endif /* MMP_DMA_H */
-- 
1.7.1



From zhangfei.gao at marvell.com  Wed Aug 15 22:23:26 2012
From: zhangfei.gao at marvell.com (Zhangfei Gao)
Date: Thu, 16 Aug 2012 10:23:26 +0800
Subject: [PATCH v4 2/2] dmaengine: mmp_tdma: add dt support
In-Reply-To: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
References: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1345083806-24588-3-git-send-email-zhangfei.gao@marvell.com>

Signed-off-by: Zhangfei Gao <zhangfei.gao at marvell.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
 Documentation/devicetree/bindings/dma/mmp-dma.txt |   30 ++++++++++++
 drivers/dma/mmp_tdma.c                            |   51 +++++++++++++--------
 2 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
index cbf40d6..36254c4 100644
--- a/Documentation/devicetree/bindings/dma/mmp-dma.txt
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -43,3 +43,33 @@ pdma: dma-controller at d4000000 {
 	      #dma-channels = <16>;
       };
 
+
+Marvell Two Channel DMA Controller used specifically for audio
+Used platfroms: pxa688, pxa910
+
+Required properties:
+- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+		or one irq for dma device
+
+"marvell,adma-1.0" used on pxa688
+"marvell,pxa910-squ" used on pxa910
+
+Examples:
+
+/* each channel has specific irq */
+adma0: dma-controller at d42a0800 {
+	      compatible = "marvell,adma-1.0";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <18 19>;
+	      interrupt-parent = <&intcmux32>;
+      };
+
+/* One irq for all channels */
+squ: dma-controller at d42a0800 {
+	      compatible = "marvell,pxa910-squ";
+	      reg = <0xd42a0800 0x100>;
+	      interrupts = <46>;
+      };
+
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
index 8a15cf2..b93d73c 100644
--- a/drivers/dma/mmp_tdma.c
+++ b/drivers/dma/mmp_tdma.c
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <mach/regs-icu.h>
 #include <mach/sram.h>
+#include <linux/of_device.h>
 
 #include "dmaengine.h"
 
@@ -127,7 +128,6 @@ struct mmp_tdma_device {
 	void __iomem			*base;
 	struct dma_device		device;
 	struct mmp_tdma_chan		*tdmac[TDMA_CHANNEL_NUM];
-	int				irq;
 };
 
 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
@@ -492,7 +492,7 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 		return -ENOMEM;
 	}
 	if (irq)
-		tdmac->irq = irq + idx;
+		tdmac->irq = irq;
 	tdmac->dev	   = tdev->dev;
 	tdmac->chan.device = &tdev->device;
 	tdmac->idx	   = idx;
@@ -505,34 +505,43 @@ static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
 	/* add the channel to tdma_chan list */
 	list_add_tail(&tdmac->chan.device_node,
 			&tdev->device.channels);
-
 	return 0;
 }
 
+static struct of_device_id mmp_tdma_dt_ids[] = {
+	{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
+	{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
+	{}
+};
+MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
+
 static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 {
-	const struct platform_device_id *id = platform_get_device_id(pdev);
-	enum mmp_tdma_type type = id->driver_data;
+	enum mmp_tdma_type type;
+	const struct of_device_id *of_id;
 	struct mmp_tdma_device *tdev;
 	struct resource *iores;
 	int i, ret;
-	int irq = 0;
+	int irq = 0, irq_num = 0;
 	int chan_num = TDMA_CHANNEL_NUM;
 
+	of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
+	if (of_id)
+		type = (enum mmp_tdma_type) of_id->data;
+	else
+		type = platform_get_device_id(pdev)->driver_data;
+
 	/* always have couple channels */
 	tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
 	if (!tdev)
 		return -ENOMEM;
 
 	tdev->dev = &pdev->dev;
-	iores = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!iores)
-		return -EINVAL;
 
-	if (resource_size(iores) != chan_num)
-		tdev->irq = iores->start;
-	else
-		irq = iores->start;
+	for (i = 0; i < chan_num; i++) {
+		if (platform_get_irq(pdev, i) > 0)
+			irq_num++;
+	}
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iores)
@@ -542,25 +551,26 @@ static int __devinit mmp_tdma_probe(struct platform_device *pdev)
 	if (!tdev->base)
 		return -EADDRNOTAVAIL;
 
-	if (tdev->irq) {
-		ret = devm_request_irq(&pdev->dev, tdev->irq,
+	INIT_LIST_HEAD(&tdev->device.channels);
+
+	if (irq_num != chan_num) {
+		irq = platform_get_irq(pdev, 0);
+		ret = devm_request_irq(&pdev->dev, irq,
 			mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
 		if (ret)
 			return ret;
 	}
 
-	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
-	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
-
-	INIT_LIST_HEAD(&tdev->device.channels);
-
 	/* initialize channel parameters */
 	for (i = 0; i < chan_num; i++) {
+		irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
 		ret = mmp_tdma_chan_init(tdev, i, irq, type);
 		if (ret)
 			return ret;
 	}
 
+	dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
+	dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
 	tdev->device.dev = &pdev->dev;
 	tdev->device.device_alloc_chan_resources =
 					mmp_tdma_alloc_chan_resources;
@@ -595,6 +605,7 @@ static struct platform_driver mmp_tdma_driver = {
 	.driver		= {
 		.name	= "mmp-tdma",
 		.owner  = THIS_MODULE,
+		.of_match_table = mmp_tdma_dt_ids,
 	},
 	.id_table	= mmp_tdma_id_table,
 	.probe		= mmp_tdma_probe,
-- 
1.7.1



From shawn.guo at linaro.org  Wed Aug 15 22:31:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 10:31:11 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120815214412.GC32560@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
Message-ID: <20120816023109.GH2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 10:44:12PM +0100, Russell King - ARM Linux wrote:
> On Wed, Aug 15, 2012 at 10:07:47AM -0500, Rob Herring wrote:
> > I think I am seeing a similar problem on highbank with a v7 only build.
> > 
> > >From what I've debugged, restart hangs for me on the L2x0 spinlock
> > during a writel. Changing the writel to writel_relaxed in the restart
> > hook fixes the problem. This skips barriers in the writel and for the
> > spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
> > should not be doing a dmb in my case on a v7 only build.
> 
> Well, I had the idea of only doing a dmb() once every N loops, but I don't
> think we can sensibly introduce such a change into the mainline kernel.
> (How would cpu_relax() know it's being used in a loop?)
> 
> Remember that the dmb() is in cpu_relax() as a work-around for the lack
> of temporal flushing of pending stores, and is needed to make various bits
> of the kernel work.
> 
The cpu_relax() will do dmb() only #if __LINUX_ARM_ARCH__ == 6 ||
defined(CONFIG_ARM_ERRATA_754327).  Otherwise, it's just a barrier()
call.  I guess Rob's puzzle is since the cpu_relax on the stopped
cores does not do dmb, why a wmb/mb call on the running cpu would hang
it.

One thing I note is that mb() will do a outer_sync() call.  Since the
issue is around L2x0 operation, not sure if they are related ...

> So at the moment, there is no solution for this - and as I've pointed out
> it can be trivially exploited in userspace on the affected CPUs.  So
> really a kernel work-around isn't going to sort it.

So, Sascha, it seems we get another good reason to split
imx_v6_v7_defconfig into imx_v6_defconfig and imx_v7_defconfig?
I have seen Matt Sealey and Hui Wang suggested doing this already.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Wed Aug 15 23:03:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 11:03:13 +0800
Subject: [PATCH] rtc: snvs: change timeout to use a fixed number of loop
In-Reply-To: <Message-ID: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
References: <Message-ID: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345086193-23870-1-git-send-email-shawn.guo@linaro.org>

Andrew Morton <akpm at linux-foundation.org> wrote:

> The timeout code here is fragile.  If acquiring the spinlock takes more
> than a millisecond or if this thread gets interrupted or preempted then
> we could easily execute that loop just a single time, and fail.
>
> It would be better to retry a fixed number of times, say 1000?  That
> would take around 1 millisecond, but might be overkill.

Take Andrew's suggestion to change the timeout code to retry 1000
times.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/rtc/rtc-snvs.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
index 912f116..3c0da33 100644
--- a/drivers/rtc/rtc-snvs.c
+++ b/drivers/rtc/rtc-snvs.c
@@ -83,8 +83,8 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
 
 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 {
-	unsigned long timeout = jiffies + msecs_to_jiffies(1);
 	unsigned long flags;
+	int timeout = 1000;
 	u32 lpcr;
 
 	spin_lock_irqsave(&data->lock, flags);
@@ -98,7 +98,7 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
-	while (1) {
+	while (--timeout) {
 		lpcr = readl(data->ioaddr + SNVS_LPCR);
 
 		if (enable) {
@@ -108,11 +108,11 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
 				break;
 		}
-
-		if (time_after(jiffies, timeout))
-			return -ETIMEDOUT;
 	}
 
+	if (!timeout)
+		return -ETIMEDOUT;
+
 	return 0;
 }
 
-- 
1.7.5.4



From xiechao.mail at gmail.com  Wed Aug 15 23:08:40 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:40 +0800
Subject: [PATCH V3 0/5] clk: mmp: add clock framework for mmp
Message-ID: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

v1->v2:
replace __raw_xxx with xxx_relax
use ioremap to remap the registers. Finaly it will use device tree to
get the physical address.
do not use macro to register clocks, and directly call the functions.

v2->v3:
pxa910 will have APB extension clock, so some peripharals will have
clocks in APB extension base.
change pxa168-pwm to be pxa910-pwm for pxa910. It will fit the current
pwm driver.

Chao Xie (5):
  clk: mmp: add mmp specific clocks
  clk: mmp: add clock definition for pxa168
  clk: mmp: add clock definition for pxa910
  clk: mmp: add clock definition for mmp2
  arm: mmp: make all SOCs use common clock by default

 arch/arm/mach-mmp/Kconfig    |    3 +
 drivers/clk/Makefile         |    3 +
 drivers/clk/mmp/Makefile     |    9 +
 drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++
 drivers/clk/mmp/clk-apmu.c   |   97 ++++++++
 drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++
 drivers/clk/mmp/clk-mmp2.c   |  544 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa168.c |  414 ++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa910.c |  361 ++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h        |   35 +++
 10 files changed, 1771 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk-mmp2.c
 create mode 100644 drivers/clk/mmp/clk-pxa168.c
 create mode 100644 drivers/clk/mmp/clk-pxa910.c
 create mode 100644 drivers/clk/mmp/clk.h



From xiechao.mail at gmail.com  Wed Aug 15 23:08:41 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:41 +0800
Subject: [PATCH V3 1/5] clk: mmp: add mmp specific clocks
In-Reply-To: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345086525-12328-2-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

add mmp specific clocks including apbc cloks, apmu clocks,
and pll2, fraction clocks

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/Makefile       |    3 +
 drivers/clk/mmp/Makefile   |    5 ++
 drivers/clk/mmp/clk-apbc.c |  152 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-apmu.c |   97 ++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-frac.c |  153 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h      |   35 ++++++++++
 6 files changed, 445 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..58590c8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,9 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-$(CONFIG_ARCH_MMP)		+= mmp/
+endif
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
new file mode 100644
index 0000000..b5bc88c
--- /dev/null
+++ b/drivers/clk/mmp/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for mmp specific clk
+#
+
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
new file mode 100644
index 0000000..be3b154
--- /dev/null
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -0,0 +1,152 @@
+/*
+ * mmp APB clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
+#define APBC_RST	(1 << 2)  /* Reset Generation */
+#define APBC_POWER	(1 << 7)  /* Reset Generation */
+
+#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
+struct clk_apbc {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	unsigned int		delay;
+	unsigned int		flags;
+	spinlock_t		*lock;
+};
+
+static int clk_apbc_prepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned int data;
+	unsigned long flags = 0;
+
+	/*
+	 * It may share same register as MUX clock,
+	 * and it will impact FNCLK enable. Spinlock is needed
+	 */
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = __raw_readl(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data |= APBC_POWER;
+	data |= APBC_FNCLK;
+	__raw_writel(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = __raw_readl(apbc->base);
+	data |= APBC_APBCLK;
+	__raw_writel(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
+		if (apbc->lock)
+			spin_lock_irqsave(apbc->lock, flags);
+
+		data = __raw_readl(apbc->base);
+		data &= ~APBC_RST;
+		__raw_writel(data, apbc->base);
+
+		if (apbc->lock)
+			spin_unlock_irqrestore(apbc->lock, flags);
+	}
+
+	return 0;
+}
+
+static void clk_apbc_unprepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = __raw_readl(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data &= ~APBC_POWER;
+	data &= ~APBC_FNCLK;
+	__raw_writel(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(10);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = __raw_readl(apbc->base);
+	data &= ~APBC_APBCLK;
+	__raw_writel(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+}
+
+struct clk_ops clk_apbc_ops = {
+	.prepare = clk_apbc_prepare,
+	.unprepare = clk_apbc_unprepare,
+};
+
+struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
+		void __iomem *base, unsigned int delay,
+		unsigned int apbc_flags, spinlock_t *lock)
+{
+	struct clk_apbc *apbc;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
+	if (!apbc)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apbc_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apbc->base = base;
+	apbc->delay = delay;
+	apbc->flags = apbc_flags;
+	apbc->lock = lock;
+	apbc->hw.init = &init;
+
+	clk = clk_register(NULL, &apbc->hw);
+	if (IS_ERR(clk))
+		kfree(apbc);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
new file mode 100644
index 0000000..4462466
--- /dev/null
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -0,0 +1,97 @@
+/*
+ * mmp AXI peripharal clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
+struct clk_apmu {
+	struct clk_hw   hw;
+	void __iomem    *base;
+	u32		rst_mask;
+	u32		enable_mask;
+	spinlock_t	*lock;
+};
+
+static int clk_apmu_enable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = __raw_readl(apmu->base) | apmu->enable_mask;
+	__raw_writel(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+
+	return 0;
+}
+
+static void clk_apmu_disable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = __raw_readl(apmu->base) & ~apmu->enable_mask;
+	__raw_writel(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+}
+
+struct clk_ops clk_apmu_ops = {
+	.enable = clk_apmu_enable,
+	.disable = clk_apmu_disable,
+};
+
+struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
+		void __iomem *base, u32 enable_mask, spinlock_t *lock)
+{
+	struct clk_apmu *apmu;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
+	if (!apmu)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apmu_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apmu->base = base;
+	apmu->enable_mask = enable_mask;
+	apmu->lock = lock;
+	apmu->hw.init = &init;
+
+	clk = clk_register(NULL, &apmu->hw);
+
+	if (IS_ERR(clk))
+		kfree(apmu);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
new file mode 100644
index 0000000..6d66d55
--- /dev/null
+++ b/drivers/clk/mmp/clk-frac.c
@@ -0,0 +1,153 @@
+/*
+ * mmp factor clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+/*
+ * It is M/N clock
+ *
+ * Fout from synthesizer can be given from two equations:
+ * numerator/denominator = Fin / (Fout * factor)
+ */
+
+#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
+struct clk_factor {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	struct clk_factor_masks	*masks;
+	struct clk_factor_tbl	*ftbl;
+	unsigned int		ftbl_cnt;
+};
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	unsigned long rate = 0, prev_rate;
+	int i;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((*prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i == 0)
+		return rate;
+	else
+		return prev_rate;
+}
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	unsigned int val, num, den;
+
+	val = readl_relaxed(factor->base);
+
+	/* calculate numerator */
+	num = (val >> masks->num_shift) & masks->num_mask;
+
+	/* calculate denominator */
+	den = (val >> masks->den_shift) & masks->num_mask;
+
+	if (!den)
+		return 0;
+
+	return (((parent_rate / 10000)  * den) /
+			(num * factor->masks->factor)) * 10000;
+}
+
+/* Configures new clock rate*/
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
+				unsigned long prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	int i;
+	unsigned long val;
+	unsigned long prev_rate, rate = 0;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i > 0)
+		i--;
+
+	val = __raw_readl(factor->base);
+
+	val &= ~(masks->num_mask << masks->num_shift);
+	val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+
+	val &= ~(masks->den_mask << masks->den_shift);
+	val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+
+	__raw_writel(val, factor->base);
+
+	return 0;
+}
+
+static struct clk_ops clk_factor_ops = {
+	.recalc_rate = clk_factor_recalc_rate,
+	.round_rate = clk_factor_round_rate,
+	.set_rate = clk_factor_set_rate,
+};
+
+struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
+		unsigned long flags, void __iomem *base,
+		struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
+		unsigned int ftbl_cnt)
+{
+	struct clk_factor *factor;
+	struct clk_init_data init;
+	struct clk *clk;
+
+	if (!masks) {
+		pr_err("%s: must pass a clk_factor_mask\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	factor = kzalloc(sizeof(*factor), GFP_KERNEL);
+	if (!factor) {
+		pr_err("%s: could not allocate factor  clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_aux assignments */
+	factor->base = base;
+	factor->masks = masks;
+	factor->ftbl = ftbl;
+	factor->ftbl_cnt = ftbl_cnt;
+	factor->hw.init = &init;
+
+	init.name = name;
+	init.ops = &clk_factor_ops;
+	init.flags = flags;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clk = clk_register(NULL, &factor->hw);
+	if (IS_ERR_OR_NULL(clk))
+		kfree(factor);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
new file mode 100644
index 0000000..ab86dd4
--- /dev/null
+++ b/drivers/clk/mmp/clk.h
@@ -0,0 +1,35 @@
+#ifndef __MACH_MMP_CLK_H
+#define __MACH_MMP_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+#define APBC_NO_BUS_CTRL	BIT(0)
+#define APBC_POWER_CTRL		BIT(1)
+
+struct clk_factor_masks {
+	unsigned int	factor;
+	unsigned int	num_mask;
+	unsigned int	den_mask;
+	unsigned int	num_shift;
+	unsigned int	den_shift;
+};
+
+struct clk_factor_tbl {
+	unsigned int num;
+	unsigned int den;
+};
+
+extern struct clk *mmp_clk_register_pll2(const char *name,
+		const char *parent_name, unsigned long flags);
+extern struct clk *mmp_clk_register_apbc(const char *name,
+		const char *parent_name, void __iomem *base,
+		unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
+extern struct clk *mmp_clk_register_apmu(const char *name,
+		const char *parent_name, void __iomem *base, u32 enable_mask,
+		spinlock_t *lock);
+extern struct clk *mmp_clk_register_factor(const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *base, struct clk_factor_masks *masks,
+		struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+#endif
-- 
1.7.0.4



From xiechao.mail at gmail.com  Wed Aug 15 23:08:42 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:42 +0800
Subject: [PATCH V3 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345086525-12328-3-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa168

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    2 +
 drivers/clk/mmp/clk-pxa168.c |  414 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 416 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa168.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index b5bc88c..a0e69ed 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -3,3 +3,5 @@
 #
 
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+
+obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 0000000..1b04deb
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,414 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x30
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x81c
+#define APBC_SSP1	0x820
+#define APBC_SSP2	0x84c
+#define APBC_SSP3	0x858
+#define APBC_SSP4	0x85c
+#define APBC_TWSI1	0x6c
+#define APBC_UART2	0x70
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+enum {
+	clk32, vctcxo, pll1, pll1_2, pll1_4, pll1_8, pll1_16, pll1_6, pll1_12,
+	pll1_24, pll1_48, pll1_96, pll1_13, pll1_13_1_5, pll1_2_1_5,
+	pll1_3_16, uart_pll, twsi0, twsi1, gpio, kpc, rtc, pwm0, pwm1, pwm2,
+	pwm3, uart0_mux, uart0, uart1_mux, uart1, uart2_mux, uart2,
+	ssp0_mux, ssp0, ssp1_mux, ssp1, ssp2_mux, ssp2, ssp3_mux, ssp3,
+	ssp4_mux, ssp4, dfc, sdh0_mux, sdh0, sdh1_mux, sdh1, usb, sph,
+	disp0_mux, disp0, disp0_hclk, ccic0_mux, ccic0, ccic0_phy_mux,
+	ccic0_phy, ccic0_sphy_div, ccic0_sphy, clk_max
+};
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] =
+	{"pll1_96", "pll1_48", "pll1_24", "pll1_12" };
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa168_clk_init(void)
+{
+	struct clk *clocks[clk_max];
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clocks[clk32] =
+	    clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clocks[clk32], "clk32", NULL);
+
+	clocks[vctcxo] =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(clocks[vctcxo], "vctcxo", NULL);
+
+	clocks[pll1] =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
+	clk_register_clkdev(clocks[pll1], "pll1", NULL);
+
+	clocks[pll1_2] =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_2], "pll1_2", NULL);
+
+	clocks[pll1_4] =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_4], "pll1_4", NULL);
+
+	clocks[pll1_8] =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_8], "pll1_8", NULL);
+
+	clocks[pll1_16] =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_16], "pll1_16", NULL);
+
+	clocks[pll1_6] =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clocks[pll1_6], "pll1_6", NULL);
+
+	clocks[pll1_12] =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_12], "pll1_12", NULL);
+
+	clocks[pll1_24] =
+	    clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_24], "pll1_24", NULL);
+
+	clocks[pll1_48] =
+	    clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_48], "pll1_48", NULL);
+
+	clocks[pll1_96] =
+	    clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_96], "pll1_96", NULL);
+
+	clocks[pll1_13] =
+	    clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clocks[pll1_13], "pll1_13", NULL);
+
+	clocks[pll1_13_1_5] =
+	    clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clocks[pll1_13_1_5], "pll1_13_1_5", NULL);
+
+	clocks[pll1_2_1_5] =
+	    clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clocks[pll1_2_1_5], "pll1_2_1_5", NULL);
+
+	clocks[pll1_3_16] =
+	    clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				      CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clocks[pll1_3_16], "pll1_3_16", NULL);
+
+	clocks[uart_pll] =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(clocks[uart_pll], 14745600);
+	clk_register_clkdev(clocks[uart_pll], "uart_pll", NULL);
+
+	clocks[twsi0] =
+	    mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clocks[twsi0], NULL, "pxa2xx-i2c.0");
+
+	clocks[twsi1] =
+	    mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clocks[twsi1], NULL, "pxa2xx-i2c.1");
+
+	clocks[gpio] =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[gpio], NULL, "pxa-gpio");
+
+	clocks[kpc] =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[kpc], NULL, "pxa27x-keypad");
+
+	clocks[rtc] =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[rtc], NULL, "sa1100-rtc");
+
+	clocks[pwm0] =
+	    mmp_clk_register_apbc("pwm0", "pll1_48", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm0], NULL, "pxa168-pwm.0");
+
+	clocks[pwm1] =
+	    mmp_clk_register_apbc("pwm1", "pll1_48", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm1], NULL, "pxa168-pwm.1");
+
+	clocks[pwm2] =
+	    mmp_clk_register_apbc("pwm2", "pll1_48", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm2], NULL, "pxa168-pwm.2");
+
+	clocks[pwm3] =
+	    mmp_clk_register_apbc("pwm3", "pll1_48", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm3], NULL, "pxa168-pwm.3");
+
+	clocks[uart0_mux] =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart0_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart0_mux], "uart_mux.0", NULL);
+
+	clocks[uart0] =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart0], NULL, "pxa2xx-uart.0");
+
+	clocks[uart1_mux] =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart1_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart1_mux], "uart_mux.1", NULL);
+
+	clocks[uart1] =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart1], NULL, "pxa2xx-uart.1");
+
+	clocks[uart2_mux] =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart2_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart2_mux], "uart_mux.2", NULL);
+
+	clocks[uart2] =
+	    mmp_clk_register_apbc("uart2", "uart2_mux", apbc_base + APBC_UART2,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart2], NULL, "pxa2xx-uart.2");
+
+	clocks[ssp0_mux] =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0_mux], "uart_mux.0", NULL);
+
+	clocks[ssp0] =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0], NULL, "mmp-ssp.0");
+
+	clocks[ssp1_mux] =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1_mux], "ssp_mux.1", NULL);
+
+	clocks[ssp1] =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1], NULL, "mmp-ssp.1");
+
+	clocks[ssp2_mux] =
+	    clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp2_mux], "ssp_mux.2", NULL);
+
+	clocks[ssp2] =
+	    mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp2], NULL, "mmp-ssp.2");
+
+	clocks[ssp3_mux] =
+	    clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp3_mux], "ssp_mux.3", NULL);
+
+	clocks[ssp3] =
+	    mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp3], NULL, "mmp-ssp.3");
+
+	clocks[ssp4_mux] =
+	    clk_register_mux(NULL, "ssp4_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp4_mux], "ssp_mux.4", NULL);
+
+	clocks[ssp4] =
+	    mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp4], NULL, "mmp-ssp.4");
+
+	clocks[dfc] =
+	    mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b,
+				  &clk_lock);
+	clk_register_clkdev(clocks[dfc], NULL, "pxa3xx-nand.0");
+
+	clocks[sdh0_mux] =
+	    clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[sdh0_mux], "sdh0_mux", NULL);
+
+	clocks[sdh0] =
+	    mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh0], NULL, "sdhci-pxa.0");
+
+	clocks[sdh1_mux] =
+	    clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[sdh1_mux], "sdh1_mux", NULL);
+
+	clocks[sdh1] =
+	    mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh1], NULL, "sdhci-pxa.1");
+
+	clocks[usb] =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clocks[usb], "usb_clk", NULL);
+
+	clocks[sph] =
+	    mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 0x12,
+				  &clk_lock);
+	clk_register_clkdev(clocks[sph], "sph_clk", NULL);
+
+	clocks[disp0_mux] =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[disp0_mux], "disp_mux.0", NULL);
+
+	clocks[disp0] =
+	    mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[disp0], "fnclk", "mmp-disp.0");
+
+	clocks[disp0_hclk] =
+	    mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
+				  apmu_base + APMU_DISP0, 0x24, &clk_lock);
+	clk_register_clkdev(clocks[disp0_hclk], "hclk", "mmp-disp.0");
+
+	clocks[ccic0_mux] =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_mux], "ccic_mux.0", NULL);
+
+	clocks[ccic0] =
+	    mmp_clk_register_apmu("ccic0", "ccic0_mux", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[ccic0], "fnclk", "mmp-ccic.0");
+
+	clocks[ccic0_phy_mux] =
+	    clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+			     ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_phy_mux], "ccic_phy_mux.0", NULL);
+
+	clocks[ccic0_phy] =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_phy], "phyclk", "mmp-ccic.0");
+
+	clocks[ccic0_sphy_div] =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy_div], "sphyclk_div", NULL);
+
+	clocks[ccic0_sphy] =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy], "sphyclk", "mmp-ccic.0");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Wed Aug 15 23:08:43 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:43 +0800
Subject: [PATCH V3 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345086525-12328-4-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa910

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    1 +
 drivers/clk/mmp/clk-pxa910.c |  380 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 381 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa910.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index a0e69ed..6160ac2 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -5,3 +5,4 @@
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
+obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
new file mode 100644
index 0000000..6f121e7
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -0,0 +1,380 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x18
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x1c
+#define APBC_SSP1	0x20
+#define APBC_SSP2	0x4c
+#define APBCP_TWSI1	0x28
+#define APBCP_UART2	0x1c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+enum {
+	clk32, vctcxo, pll1, pll1_2, pll1_4, pll1_8, pll1_16, pll1_6, pll1_12,
+	pll1_24, pll1_48, pll1_96, pll1_13, pll1_13_1_5, pll1_2_1_5,
+	pll1_3_16, uart_pll, twsi0, twsi1, gpio, kpc, rtc, pwm0, pwm1, pwm2,
+	pwm3, uart0_mux, uart0, uart1_mux, uart1, uart2_mux, uart2,
+	ssp0_mux, ssp0, ssp1_mux, ssp1, dfc, sdh0_mux, sdh0, sdh1_mux, sdh1,
+	usb, sph, disp0_mux, disp0, ccic0_mux, ccic0, ccic0_phy_mux,
+	ccic0_phy, ccic0_sphy_div, ccic0_sphy, clk_max
+};
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] =
+	{"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa910_clk_init(void)
+{
+	struct clk *clocks[clk_max];
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbcp_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
+	if (apbcp_base == NULL) {
+		pr_err("error to ioremap APBC extension base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clocks[clk32] =
+	    clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clocks[clk32], "clk32", NULL);
+
+	clocks[vctcxo] =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(clocks[vctcxo], "vctcxo", NULL);
+
+	clocks[pll1] =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
+	clk_register_clkdev(clocks[pll1], "pll1", NULL);
+
+	clocks[pll1_2] =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_2], "pll1_2", NULL);
+
+	clocks[pll1_4] =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_4], "pll1_4", NULL);
+
+	clocks[pll1_8] =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_8], "pll1_8", NULL);
+
+	clocks[pll1_16] =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_16], "pll1_16", NULL);
+
+	clocks[pll1_6] =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clocks[pll1_6], "pll1_6", NULL);
+
+	clocks[pll1_12] =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_12], "pll1_12", NULL);
+
+	clocks[pll1_24] =
+	    clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_24], "pll1_24", NULL);
+
+	clocks[pll1_48] =
+	    clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_48], "pll1_48", NULL);
+
+	clocks[pll1_96] =
+	    clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_96], "pll1_96", NULL);
+
+	clocks[pll1_13] =
+	    clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clocks[pll1_13], "pll1_13", NULL);
+
+	clocks[pll1_13_1_5] =
+	    clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clocks[pll1_13_1_5], "pll1_13_1_5", NULL);
+
+	clocks[pll1_2_1_5] =
+	    clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clocks[pll1_2_1_5], "pll1_2_1_5", NULL);
+
+	clocks[pll1_3_16] =
+	    clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				      CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clocks[pll1_3_16], "pll1_3_16", NULL);
+
+	clocks[uart_pll] =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(clocks[uart_pll], 14745600);
+	clk_register_clkdev(clocks[uart_pll], "uart_pll", NULL);
+
+	clocks[twsi0] =
+	    mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clocks[twsi0], NULL, "pxa2xx-i2c.0");
+
+	clocks[twsi1] =
+	    mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				  apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clocks[twsi1], NULL, "pxa2xx-i2c.1");
+
+	clocks[gpio] =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[gpio], NULL, "pxa-gpio");
+
+	clocks[kpc] =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[kpc], NULL, "pxa27x-keypad");
+
+	clocks[rtc] =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[rtc], NULL, "sa1100-rtc");
+
+	clocks[pwm0] =
+	    mmp_clk_register_apbc("pwm0", "pll1_48", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm0], NULL, "pxa910-pwm.0");
+
+	clocks[pwm1] =
+	    mmp_clk_register_apbc("pwm1", "pll1_48", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm1], NULL, "pxa910-pwm.1");
+
+	clocks[pwm2] =
+	    mmp_clk_register_apbc("pwm2", "pll1_48", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm2], NULL, "pxa910-pwm.2");
+
+	clocks[pwm3] =
+	    mmp_clk_register_apbc("pwm3", "pll1_48", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm3], NULL, "pxa910-pwm.3");
+
+	clocks[uart0_mux] =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart0_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart0_mux], "uart_mux.0", NULL);
+
+	clocks[uart0] =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart0], NULL, "pxa2xx-uart.0");
+
+	clocks[uart1_mux] =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart1_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart1_mux], "uart_mux.1", NULL);
+
+	clocks[uart1] =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart1], NULL, "pxa2xx-uart.1");
+
+	clocks[uart2_mux] =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart2_mux], clocks[uart_pll]);
+	clk_register_clkdev(clocks[uart2_mux], "uart_mux.2", NULL);
+
+	clocks[uart2] =
+	    mmp_clk_register_apbc("uart2", "uart2_mux",
+				  apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart2], NULL, "pxa2xx-uart.2");
+
+	clocks[ssp0_mux] =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0_mux], "uart_mux.0", NULL);
+
+	clocks[ssp0] =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0], NULL, "mmp-ssp.0");
+
+	clocks[ssp1_mux] =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1_mux], "ssp_mux.1", NULL);
+
+	clocks[ssp1] =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1], NULL, "mmp-ssp.1");
+
+	clocks[dfc] =
+	    mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b,
+				  &clk_lock);
+	clk_register_clkdev(clocks[dfc], NULL, "pxa3xx-nand.0");
+
+	clocks[sdh0_mux] =
+	    clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[sdh0_mux], "sdh0_mux", NULL);
+
+	clocks[sdh0] =
+	    mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh0], NULL, "sdhci-pxa.0");
+
+	clocks[sdh1_mux] =
+	    clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[sdh1_mux], "sdh1_mux", NULL);
+
+	clocks[sdh1] =
+	    mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh1], NULL, "sdhci-pxa.1");
+
+	clocks[usb] =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clocks[usb], "usb_clk", NULL);
+
+	clocks[sph] =
+	    mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 0x12,
+				  &clk_lock);
+	clk_register_clkdev(clocks[sph], "sph_clk", NULL);
+
+	clocks[disp0_mux] =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[disp0_mux], "disp_mux.0", NULL);
+
+	clocks[disp0] =
+	    mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[disp0], NULL, "mmp-disp.0");
+
+	clocks[ccic0_mux] =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_mux], "ccic_mux.0", NULL);
+
+	clocks[ccic0] =
+	    mmp_clk_register_apmu("ccic0", "ccic0_mux", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[ccic0], "fnclk", "mmp-ccic.0");
+
+	clocks[ccic0_phy_mux] =
+	    clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+			     ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_phy_mux], "ccic_phy_mux.0", NULL);
+
+	clocks[ccic0_phy] =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_phy], "phyclk", "mmp-ccic.0");
+
+	clocks[ccic0_sphy_div] =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy_div], "sphyclk_div", NULL);
+
+	clocks[ccic0_sphy] =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy], "sphyclk", "mmp-ccic.0");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Wed Aug 15 23:08:44 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:44 +0800
Subject: [PATCH V3 4/5] clk: mmp: add clock definition for mmp2
In-Reply-To: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345086525-12328-5-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for mmp2

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile   |    1 +
 drivers/clk/mmp/clk-mmp2.c |  544 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 545 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-mmp2.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 6160ac2..392d780 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
+obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
new file mode 100644
index 0000000..13f30f8
--- /dev/null
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -0,0 +1,544 @@
+/*
+ * mmp clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x0
+#define APBC_TWSI0	0x4
+#define APBC_TWSI1	0x8
+#define APBC_TWSI2	0xc
+#define APBC_TWSI3	0x10
+#define APBC_TWSI4	0x7c
+#define APBC_TWSI5	0x80
+#define APBC_KPC	0x18
+#define APBC_UART0	0x2c
+#define APBC_UART1	0x30
+#define APBC_UART2	0x34
+#define APBC_UART3	0x88
+#define APBC_GPIO	0x38
+#define APBC_PWM0	0x3c
+#define APBC_PWM1	0x40
+#define APBC_PWM2	0x44
+#define APBC_PWM3	0x48
+#define APBC_SSP0	0x50
+#define APBC_SSP1	0x54
+#define APBC_SSP2	0x58
+#define APBC_SSP3	0x5c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_SDH2	0xe8
+#define APMU_SDH3	0xec
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_DISP1	0x110
+#define APMU_CCIC0	0x50
+#define APMU_CCIC1	0xf4
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+enum {
+	clk32, vctcxo, pll1, usb_pll, pll2, pll1_2, pll1_4, pll1_8, pll1_16,
+	pll1_20, pll1_3, pll1_6, pll1_12, pll2_2, pll2_4, pll2_8, pll2_16,
+	pll2_3, pll2_6, pll2_12, vctcxo_2, vctcxo_4, uart_pll, twsi0, twsi1,
+	twsi2, twsi3, twsi4, twsi5, gpio, kpc, rtc, pwm0, pwm1, pwm2, pwm3,
+	uart0_mux, uart0, uart1_mux, uart1, uart2_mux, uart2, uart3_mux,
+	uart3, ssp0_mux, ssp0, ssp1_mux, ssp1, ssp2_mux, ssp2, ssp3_mux,
+	ssp3, sdh_mux, sdh_div, sdh0, sdh1, sdh2, sdh3, usb, disp0_mux,
+	disp0_div, disp0, disp0_sphy_div, disp0_sphy, disp1_mux, disp1_div,
+	disp1, ccic_arbiter, ccic0_mux, ccic0_div, ccic0, ccic0_phy,
+	ccic0_sphy_div, ccic0_sphy, ccic1_mux, ccic1_div, ccic1, ccic1_phy,
+	ccic1_sphy_div, ccic1_sphy, clk_max
+};
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 14634, .den = 2165},	/*14.745MHZ */
+	{.num = 3521, .den = 689},	/*19.23MHZ */
+	{.num = 9679, .den = 5728},	/*58.9824MHZ */
+	{.num = 15850, .den = 9451},	/*59.429MHZ */
+};
+
+static const char *uart_parent[] = {"uart_pll", "vctcxo"};
+static const char *ssp_parent[] =
+	{"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
+
+void __init mmp2_clk_init(void)
+{
+	struct clk *clocks[clk_max];
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clocks[clk32] =
+	    clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clocks[clk32], "clk32", NULL);
+
+	clocks[vctcxo] =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(clocks[vctcxo], "vctcxo", NULL);
+
+	clocks[pll1] =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 800000000);
+	clk_register_clkdev(clocks[pll1], "pll1", NULL);
+
+	clocks[usb_pll] =
+	    clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
+				    480000000);
+	clk_register_clkdev(clocks[usb_pll], "usb_pll", NULL);
+
+	clocks[pll2] =
+	    clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, 960000000);
+	clk_register_clkdev(clocks[pll2], "pll2", NULL);
+
+	clocks[pll1_2] =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_2], "pll1_2", NULL);
+
+	clocks[pll1_4] =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_4], "pll1_4", NULL);
+
+	clocks[pll1_8] =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_8], "pll1_8", NULL);
+
+	clocks[pll1_16] =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_16], "pll1_16", NULL);
+
+	clocks[pll1_20] =
+	    clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 5);
+	clk_register_clkdev(clocks[pll1_20], "pll1_20", NULL);
+
+	clocks[pll1_3] =
+	    clk_register_fixed_factor(NULL, "pll1_3", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clocks[pll1_3], "pll1_3", NULL);
+
+	clocks[pll1_6] =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_6], "pll1_6", NULL);
+
+	clocks[pll1_12] =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll1_12], "pll1_12", NULL);
+
+	clocks[pll2_2] =
+	    clk_register_fixed_factor(NULL, "pll2_2", "pll2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_2], "pll2_2", NULL);
+
+	clocks[pll2_4] =
+	    clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_4], "pll2_4", NULL);
+
+	clocks[pll2_8] =
+	    clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_8], "pll2_8", NULL);
+
+	clocks[pll2_16] =
+	    clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_16], "pll2_16", NULL);
+
+	clocks[pll2_3] =
+	    clk_register_fixed_factor(NULL, "pll2_3", "pll2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clocks[pll2_3], "pll2_3", NULL);
+
+	clocks[pll2_6] =
+	    clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_6], "pll2_6", NULL);
+
+	clocks[pll2_12] =
+	    clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[pll2_12], "pll2_12", NULL);
+
+	clocks[vctcxo_2] =
+	    clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[vctcxo_2], "vctcxo_2", NULL);
+
+	clocks[vctcxo_4] =
+	    clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clocks[vctcxo_4], "vctcxo_4", NULL);
+
+	clocks[uart_pll] =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(clocks[uart_pll], 14745600);
+	clk_register_clkdev(clocks[uart_pll], "uart_pll", NULL);
+
+	clocks[twsi0] =
+	    mmp_clk_register_apbc("twsi0", "vctcxo", apbc_base + APBC_TWSI0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi0], NULL, "pxa2xx-i2c.0");
+
+	clocks[twsi1] =
+	    mmp_clk_register_apbc("twsi1", "vctcxo", apbc_base + APBC_TWSI1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi1], NULL, "pxa2xx-i2c.1");
+
+	clocks[twsi2] =
+	    mmp_clk_register_apbc("twsi2", "vctcxo", apbc_base + APBC_TWSI2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi2], NULL, "pxa2xx-i2c.2");
+
+	clocks[twsi3] =
+	    mmp_clk_register_apbc("twsi3", "vctcxo", apbc_base + APBC_TWSI3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi3], NULL, "pxa2xx-i2c.3");
+
+	clocks[twsi4] =
+	    mmp_clk_register_apbc("twsi4", "vctcxo", apbc_base + APBC_TWSI4, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi4], NULL, "pxa2xx-i2c.4");
+
+	clocks[twsi5] =
+	    mmp_clk_register_apbc("twsi5", "vctcxo", apbc_base + APBC_TWSI5, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[twsi5], NULL, "pxa2xx-i2c.5");
+
+	clocks[gpio] =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[gpio], NULL, "pxa-gpio");
+
+	clocks[kpc] =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[kpc], NULL, "pxa27x-keypad");
+
+	clocks[rtc] =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clocks[rtc], NULL, "mmp-rtc");
+
+	clocks[pwm0] =
+	    mmp_clk_register_apbc("pwm0", "vctcxo", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm0], NULL, "mmp2-pwm.0");
+
+	clocks[pwm1] =
+	    mmp_clk_register_apbc("pwm1", "vctcxo", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm1], NULL, "mmp2-pwm.1");
+
+	clocks[pwm2] =
+	    mmp_clk_register_apbc("pwm2", "vctcxo", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm2], NULL, "mmp2-pwm.2");
+
+	clocks[pwm3] =
+	    mmp_clk_register_apbc("pwm3", "vctcxo", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[pwm3], NULL, "mmp2-pwm.3");
+
+	clocks[uart0_mux] =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart0_mux], clocks[vctcxo]);
+	clk_register_clkdev(clocks[uart0_mux], "uart_mux.0", NULL);
+
+	clocks[uart0] =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart0], NULL, "pxa2xx-uart.0");
+
+	clocks[uart1_mux] =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart1_mux], clocks[vctcxo]);
+	clk_register_clkdev(clocks[uart1_mux], "uart_mux.1", NULL);
+
+	clocks[uart1] =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart1], NULL, "pxa2xx-uart.1");
+
+	clocks[uart2_mux] =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart2_mux], clocks[vctcxo]);
+	clk_register_clkdev(clocks[uart2_mux], "uart_mux.2", NULL);
+
+	clocks[uart2] =
+	    mmp_clk_register_apbc("uart2", "uart2_mux", apbc_base + APBC_UART2,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart2], NULL, "pxa2xx-uart.2");
+
+	clocks[uart3_mux] =
+	    clk_register_mux(NULL, "uart3_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
+	clk_set_parent(clocks[uart3_mux], clocks[vctcxo]);
+	clk_register_clkdev(clocks[uart3_mux], "uart_mux.3", NULL);
+
+	clocks[uart3] =
+	    mmp_clk_register_apbc("uart3", "uart3_mux", apbc_base + APBC_UART3,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clocks[uart3], NULL, "pxa2xx-uart.3");
+
+	clocks[ssp0_mux] =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0_mux], "uart_mux.0", NULL);
+
+	clocks[ssp0] =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp0], NULL, "mmp-ssp.0");
+
+	clocks[ssp1_mux] =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1_mux], "ssp_mux.1", NULL);
+
+	clocks[ssp1] =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp1], NULL, "mmp-ssp.1");
+
+	clocks[ssp2_mux] =
+	    clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp2_mux], "ssp_mux.2", NULL);
+
+	clocks[ssp2] =
+	    mmp_clk_register_apbc("ssp2", "ssp2_mux", apbc_base + APBC_SSP2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp2], NULL, "mmp-ssp.2");
+
+	clocks[ssp3_mux] =
+	    clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clocks[ssp3_mux], "ssp_mux.3", NULL);
+
+	clocks[ssp3] =
+	    mmp_clk_register_apbc("ssp3", "ssp3_mux", apbc_base + APBC_SSP3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clocks[ssp3], NULL, "mmp-ssp.3");
+
+	clocks[sdh_mux] =
+	    clk_register_mux(NULL, "sdh_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
+	clk_register_clkdev(clocks[sdh_mux], "sdh_mux", NULL);
+
+	clocks[sdh_div] =
+	    clk_register_divider(NULL, "sdh_div", "sdh_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, 10,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clocks[sdh_div], "sdh_div", NULL);
+
+	clocks[sdh0] =
+	    mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh0], NULL, "sdhci-pxav3.0");
+
+	clocks[sdh1] =
+	    mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh1], NULL, "sdhci-pxav3.1");
+
+	clocks[sdh2] =
+	    mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh2], NULL, "sdhci-pxav3.2");
+
+	clocks[sdh3] =
+	    mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[sdh3], NULL, "sdhci-pxav3.3");
+
+	clocks[usb] =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clocks[usb], "usb_clk", NULL);
+
+	clocks[disp0_mux] =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clocks[disp0_mux], "disp_mux.0", NULL);
+
+	clocks[disp0_div] =
+	    clk_register_divider(NULL, "disp0_div", "disp0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, 8,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clocks[disp0_div], "disp_div.0", NULL);
+
+	clocks[disp0] =
+	    mmp_clk_register_apmu("disp0", "disp0_div", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[disp0], NULL, "mmp-disp.0");
+
+	clocks[disp0_sphy_div] =
+	    clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
+				 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
+	clk_register_clkdev(clocks[disp0_sphy_div], "disp_sphy_div.0", NULL);
+
+	clocks[disp0_sphy] =
+	    mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
+				  apmu_base + APMU_DISP0, 0x1024, &clk_lock);
+	clk_register_clkdev(clocks[disp0_sphy], "disp_sphy.0", NULL);
+
+	clocks[disp1_mux] =
+	    clk_register_mux(NULL, "disp1_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clocks[disp1_mux], "disp_mux.1", NULL);
+
+	clocks[disp1_div] =
+	    clk_register_divider(NULL, "disp1_div", "disp1_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, 8,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clocks[disp1_div], "disp_div.1", NULL);
+
+	clocks[disp1] =
+	    mmp_clk_register_apmu("disp1", "disp1_div", apmu_base + APMU_DISP1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[disp1], NULL, "mmp-disp.1");
+
+	clocks[ccic_arbiter] =
+	    mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
+				  apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
+	clk_register_clkdev(clocks[ccic_arbiter], "ccic_arbiter", NULL);
+
+	clocks[ccic0_mux] =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_mux], "ccic_mux.0", NULL);
+
+	clocks[ccic0_div] =
+	    clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_div], "ccic_div.0", NULL);
+
+	clocks[ccic0] =
+	    mmp_clk_register_apmu("ccic0", "ccic0_div", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[ccic0], "fnclk", "mmp-ccic.0");
+
+	clocks[ccic0_phy] =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_phy], "phyclk", "mmp-ccic.0");
+
+	clocks[ccic0_sphy_div] =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy_div], "sphyclk_div",
+			    "mmp-ccic.0");
+
+	clocks[ccic0_sphy] =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clocks[ccic0_sphy], "sphyclk", "mmp-ccic.0");
+
+	clocks[ccic1_mux] =
+	    clk_register_mux(NULL, "ccic1_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic1_mux], "ccic_mux.1", NULL);
+
+	clocks[ccic1_div] =
+	    clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clocks[ccic1_div], "ccic_div.1", NULL);
+
+	clocks[ccic1] =
+	    mmp_clk_register_apmu("ccic1", "ccic1_div", apmu_base + APMU_CCIC1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clocks[ccic1], "fnclk", "mmp-ccic.1");
+
+	clocks[ccic1_phy] =
+	    mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
+				  apmu_base + APMU_CCIC1, 0x24, &clk_lock);
+	clk_register_clkdev(clocks[ccic1_phy], "phyclk", "mmp-ccic.1");
+
+	clocks[ccic1_sphy_div] =
+	    clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clocks[ccic1_sphy_div], "sphyclk_div",
+			    "mmp-ccic.1");
+
+	clocks[ccic1_sphy] =
+	    mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
+				  apmu_base + APMU_CCIC1, 0x300, &clk_lock);
+	clk_register_clkdev(clocks[ccic1_sphy], "sphyclk", "mmp-ccic.1");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Wed Aug 15 23:08:45 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 11:08:45 +0800
Subject: [PATCH V3 5/5] arm: mmp: make all SOCs use common clock by default
In-Reply-To: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345086525-12328-6-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Kconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01..d697d07 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
 config CPU_PXA168
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA168
 
 config CPU_PXA910
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA910
 
 config CPU_MMP2
 	bool
 	select CPU_PJ4
+	select COMMON_CLK
 	help
 	  Select code specific to MMP2. MMP2 is ARMv7 compatible.
 
-- 
1.7.0.4



From gururaja.hebbar at ti.com  Wed Aug 15 23:18:48 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Thu, 16 Aug 2012 03:18:48 +0000
Subject: [PATCHv6 14/24] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1344953946-13005-15-git-send-email-shubhrajyoti@ti.com>
References: <1344953946-13005-1-git-send-email-shubhrajyoti@ti.com>
 <1344953946-13005-15-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA5F5B6@DBDE01.ent.ti.com>

On Tue, Aug 14, 2012 at 19:48:56, Datta, Shubhrajyoti wrote:
> From: Felipe Balbi <balbi at ti.com>
> 
> otherwise we could get our IRQ line disabled due
> to many spurious IRQs.

Patch description should be readable by itself. It is not a continuation of
subject line.

> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> ---
>  drivers/i2c/busses/i2c-omap.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 80ebcf5..eb6898b 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -962,7 +962,7 @@ complete:
>  		}
>  	} while (stat);
>  
> -	return count ? IRQ_HANDLED : IRQ_NONE;
> +	return IRQ_HANDLED;
>  }
>  
>  static const struct i2c_algorithm omap_i2c_algo = {
> -- 
> 1.7.5.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


Regards, 
Gururaja


From shawn.guo at linaro.org  Wed Aug 15 23:45:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 11:45:11 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <CAKGA1bkNEJbQgwcdZs8PozCgVyOfUE=bDCGkRkKV3VMfbvRMgw@mail.gmail.com>
References: <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120815153107.GG2258@S2101-09.ap.freescale.net>
 <CAKGA1bkNEJbQgwcdZs8PozCgVyOfUE=bDCGkRkKV3VMfbvRMgw@mail.gmail.com>
Message-ID: <20120816034506.GI2258@S2101-09.ap.freescale.net>

On Wed, Aug 15, 2012 at 11:49:01AM -0500, Matt Sealey wrote:
> > Rather than betting how DTC will implement macro, we'd better make the
> > the safest assumption - it will not support that syntax.
> 
> It won't.

There were a lot of pushing on macro support for DTC.  Though it's
going to be very slow, I guess someday we will have it at least for
those simple and straight-forward syntax.

But right, we shouldn't make any assumption on that.

> DT is defined by properties and those properties have cells.
> Properties
> that have more than one cell or multiple definitions in them have to have a
> #size-cells property to go with it somehow.
> 
> I don't see what the problem would be here; you want to define pin properties,
> sure, they are intrinsically defined by 3 possible registers and value pairs. In
> actual fact if you drill down to this, what happens is you get a pin property
> which defines offsets into the unit, and values to stuff into those
> registers, so
> you could either dictate a size-cell of 6 (3 pairs of reg-value) or 2
> (reg, value).
> It would be more convenient for a driver to know what those pairs are maybe,
> so 6 is better.

<snip>

> iomuxc at 0x73f08000 {
>   fsl,iomux-pins = <mux value ctrl value ipp value
> /* MX53_PIN_SD4_CMD__SD4_CMD */
>                             mux value ctrl value ipp value
>        /* etc. */
>                             ...>;
> 
I do not see problem with this approach either.  But, this is nothing
IMX specific.  Essentially, this becomes a common binding for
configuring a pin with arbitrary number of register/value pairs.

-- 
Regards,
Shawn


From b29396 at freescale.com  Wed Aug 15 23:30:07 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 16 Aug 2012 11:30:07 +0800
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120815135947.GC2258@S2101-09.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
Message-ID: <20120816033006.GA11999@shlinux2.ap.freescale.net>

On Wed, Aug 15, 2012 at 09:59:50PM +0800, Shawn Guo wrote:
...
> > Another known issue is that via this way, that means the pinctrl subsystem
> > can only see the using pads, this is a bit not align with the pinctrl
> > subsystem design. No sure if Linus would like to see it.
> > 
> I do not quite follow on this.  The "enum imx51_pads" will still be
> there, so all the pads will still be visible to the pinctrl system.
> 
Sorry, i did not describe it accurately.
The problem is that those pins are visible to pinctrl subystem, but the pinctrl
subsystem can not manage them all.
Not sure this meet Linus's original design purpose.
Because for the way proposed, all the pin's basic properties like mux_reg, config_reg
are parsed from device tree at runtime.
If a pin is not used in device tree, the driver can not know this pin's
corresponding registers.
Thus, for those unused pins, we can not manage it on mux or config in pinctrl
subsystem and driver.

For example, the pin_config_get/pin_config_set API in
include/linux/pinctrl/consumer.h can not work for such pins.
Then imx_pinconf_dbg_show in current driver may need change since it does not
support show all pins's config value.
It looks like not a big issue currently since i did not see any client driver
using this API.
But i'm not sure if we may have this requirement in the future.
For example, is it possible that pinctrl subsystem may support configure pins
via sysfs dynamically?

Linus, Stephen,
Any comment on it?

If it supports, will imx driver also support config unused pins in devicetree
via sysfs?
Probably it may be rarely used and imx just does not support it.
Then we can get register data from devicetree.

Regards
Dong Aisheng



From thierry.reding at avionic-design.de  Thu Aug 16 00:55:39 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 16 Aug 2012 06:55:39 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <201208152025.25252.arnd@arndb.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo7c4L=Ny=CtZwLB_XWTcN8tVWs_quuE_T+XLEGyhWwHkg@mail.gmail.com>
 <20120815145708.GA11331@avionic-0098.mockup.avionic-design.de>
 <201208152025.25252.arnd@arndb.de>
Message-ID: <20120816045539.GA17067@avionic-0098.mockup.avionic-design.de>

On Wed, Aug 15, 2012 at 08:25:25PM +0000, Arnd Bergmann wrote:
> On Wednesday 15 August 2012, Thierry Reding wrote:
> > Yes, that was my understanding as well. So currently I haven't seen any
> > problems with this because I only use one of the two host bridges. But I
> > suppose I should add code to initialize the bus number aperture properly
> > either via platform device resources (for the non-DT case) and the
> > device tree otherwise.
> 
> I think when we last discussed this, the assumption was that each
> root port has its own config space range and its own pci domain,
> so you don't have to worry about bus apertures because each root port
> can then have all 255 bus numbers. Has that turned out to be incorrect
> now?

At least for the config space this is incorrect. There's a single region
to access the configuration space for all devices below the PCIe
controller. So it is shared by both (Tegra20) or all three (Tegra30)
root ports.

I'm not sure about PCI domains. Do you have any good pointers as to
where I could read up on them? If they need special hardware support,
then I think Tegra doesn't support them either. At least I haven't come
across any mention of domains while going through the, admittedly some-
what sparse on PCIe, Tegra documentation.

Thierry
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From santosh.shilimkar at ti.com  Thu Aug 16 01:50:07 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 16 Aug 2012 11:20:07 +0530
Subject: [PATCH v5 0/8] ARM: OMAP2+: PM: introduce the power domains
 functional states
In-Reply-To: <alpine.DEB.2.00.1208151842380.8833@utopia.booyaka.com>
References: <1345024968-28951-1-git-send-email-j-pihet@ti.com>
 <CAMQu2gxznhsbK3--nyQmYdHqyGjwpCSa3CJx8aYpF4wwR1qBSg@mail.gmail.com>
 <alpine.DEB.2.00.1208151842380.8833@utopia.booyaka.com>
Message-ID: <CAMQu2gyV6gX=KFjMZ1r_BwsJXmgjuLMAWHrrLCYLgKEBRne0Ow@mail.gmail.com>

Paul,

On Thu, Aug 16, 2012 at 6:18 AM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Hi Santosh,
>
> On Wed, 15 Aug 2012, Shilimkar, Santosh wrote:
>
> > On Wed, Aug 15, 2012 at 3:32 PM, Jean Pihet <jean.pihet at newoldbits.com>
> > wrote:
> >
> > I didn't find any mention here about why are we going in this path and
> > not
> > in the direction proposed in another RFC [1]
> > I have already given my comments[2] against the introduction of another
> > PD
> > layer which can be avoided easily as demonstrated by the RFC[1]. The
> > comments
> > are still applicable for this series too.
> >
> > We really need to reduce OMAP specific framework overhead and
> > move towards more generic PM frameworks. For me, this series is
> > a step back-ward from that direction. Am really sorry for being critical
> > again but I remain unconvinced about this series and the problem it
> > is trying to solve.
> >
> > May be you have valid reasons not to follow the approach in [1] and in
> > that case, it will be good to clarify that so that some of us get
> > to know your rationale.
>
> I've asked Jean to handle the work of evaluating and/or integrating any
> feedback from you and Rajendra into this series.  Jean, has this latest
> series fully considered those issues?  Or are there still some areas of
> misalignment / lack of clarity?
>
Thanks for the information. The main objection to this series was to
not add un-necessary glue layer which still remains.

>From our discussion in past on and off list, your main intention for such
a series was -

1. Need a way to support OSWR.
- OSWR by definition is a RET with configurable logic and memory states.
Its a true power state from PD point of view and its not a logical state.
Now since we have agreed to make the OSWR as a static definition
(in all products so far OSWR is used as a static definition with logic
lost, memory retained kind of configuration.)

- The above requirement can be easily fixed by adding the OSWR
as an additional basic power state as demonstrated in RFC.

- There is no need to add another glue layer for above.

2. Locking so that the low level APIs don't race and henec abstracting the
exported API to 1 or 2 and making rest as private functions.

-- Even before this series, except low level PM code, only one
common API was used to set the PD low power state.
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)

-- Once we make OSWR as basic power state, we also avoid usage of
pwrdm_set_logic_retst() API.

-- We implement lock at this API and export only above API +
may be omap_get_pwrdm_state() kind of API based on need.

-- This solves the second requirement too.

Even if we have more requirement, they can be addressed
too without need of another layer.

If you look at the diffstat alone between two approaches, it is
evident how small piece of code is needed to support above.
Am not too much into the lines of code but basic objection we
have is not to add another glue layer.

Thinking bit loud, for the logical layer for power domain
we should move towards common device power domain
APIs and if needed add/enhance them to support OMAP.
   drivers/base/power/domain.c
May be this though is bit premature but the intetion is
to move towards generic linux framework.

> Anyway.  If there's a problem with this process, it sounds like you,
> Rajendra, Jean, Beno?t and I should schedule some time to talk over the
> same issues that you discussed with me on the phone.  Perhaps next week?
>
We can surely do a call if needed. But the comments given so far and the
RFC makes things more or less clear the contention point against the
$subject series.

Regards
Santosh


From grinberg at compulab.co.il  Thu Aug 16 02:21:22 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 16 Aug 2012 09:21:22 +0300
Subject: [PATCH v2 3/4] ARM: OMAP3: Switch to use the unified audio driver
 (omap-twl4030) for selected boards
In-Reply-To: <1344935279-32364-4-git-send-email-peter.ujfalusi@ti.com>
References: <1344935279-32364-1-git-send-email-peter.ujfalusi@ti.com>
 <1344935279-32364-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <502C9162.4020801@compulab.co.il>

On 08/14/12 12:07, Peter Ujfalusi wrote:
> These boards have similar audio setup and they can all use the same driver
> for audio support if it is enabled in the kernel config.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Cc: Igor Grinberg <grinberg at compulab.co.il>
> Acked-by: Tony Lindgren <tony at atomide.com>

Acked-by: Igor Grinberg <grinberg at compulab.co.il>

Thanks Peter!


-- 
Regards,
Igor.


From markus at oberhumer.com  Thu Aug 16 02:27:15 2012
From: markus at oberhumer.com (Markus F.X.J. Oberhumer)
Date: Thu, 16 Aug 2012 08:27:15 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120815144539.GA8300@sig21.net>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net>
Message-ID: <502C92C3.7090701@oberhumer.com>

On 2012-08-15 16:45, Johannes Stezenbach wrote:
> On Wed, Aug 15, 2012 at 02:02:43PM +0200, Markus F.X.J. Oberhumer wrote:
>> On 2012-08-14 14:39, Johannes Stezenbach wrote:
>>> On Tue, Aug 14, 2012 at 01:44:02AM +0200, Markus F.X.J. Oberhumer wrote:
>>>> On 2012-07-16 20:30, Markus F.X.J. Oberhumer wrote:
>>>>>
>>>>> As stated in the README this version is significantly faster (typically more
>>>>> than 2 times faster!) than the current version, has been thoroughly tested on
>>>>> x86_64/i386/powerpc platforms and is intended to get included into the
>>>>> official Linux 3.6 or 3.7 release.
>>>>>
>>>>> I encourage all compression users to test and benchmark this new version,
>>>>> and I also would ask some official LZO maintainer to convert the updated
>>>>> source files into a GIT commit and possibly push it to Linus or linux-next.
>>>
>>> Sorry for not reporting earlier, but I didn't have time to do real
>>> benchmarks, just a quick test on ARM926EJ-S using barebox,
>>> and found in the new version decompression is slower:
>>> http://lists.infradead.org/pipermail/barebox/2012-July/008268.html
>>
>> I can only guess, but maybe your ARM cpu does not have an efficient
>> implementation of {get,put}_unaligned().
> 
> Yes, ARMv5 cannot do unaligned access.  ARMv6+ could, but
> I think the Linux kernel normally traps it for debug,
> all ARM seem to use generic {get,put}_unaligned() implementation
> which use byte access and shift.

Hmm - I could imagine that we're wasting a lot of possible speed gain
by not exploiting that feature on ARMv6+.

>> Could you please try the following patch and test if you can see
>> any significant speed difference?
> 
> It isn't.  I made the attached quick hack userspace code
> using ARM kernel headers and barebox unlzop code.
> (new == your new code, old == linux-3.5 git, test == new + your suggested change)
> (sorry I had no time to clean it up)

My suggested COPY4 replacement probably has a lot of load stalls - maybe some
ARM expert could have a look and suggest a more efficient implementation.

In any case, I still would like to see the new code in linux-next because
of the huge improvements on other modern CPUs.

Cheers,
Markus

> 
> I compressed a Linux Image with lzop (lzop <arch/arm/boot/Image >lzoimage)
> and timed uncompression:
> 
> # time ./unlzopold <lzoimage >/dev/null
> real    0m 0.29s
> user    0m 0.19s
> sys     0m 0.10s
> # time ./unlzopold <lzoimage >/dev/null
> real    0m 0.29s
> user    0m 0.20s
> sys     0m 0.09s
> # time ./unlzopnew <lzoimage >/dev/null
> real    0m 0.41s
> user    0m 0.30s
> sys     0m 0.10s
> # time ./unlzopnew <lzoimage >/dev/null
> real    0m 0.40s
> user    0m 0.30s
> sys     0m 0.10s
> # time ./unlzopnew <lzoimage >/dev/null
> real    0m 0.40s
> user    0m 0.29s
> sys     0m 0.11s
> # time ./unlzoptest <lzoimage >/dev/null
> real    0m 0.39s
> user    0m 0.28s
> sys     0m 0.11s
> # time ./unlzoptest <lzoimage >/dev/null
> real    0m 0.39s
> user    0m 0.27s
> sys     0m 0.11s
> # time ./unlzoptest <lzoimage >/dev/null
> real    0m 0.39s
> user    0m 0.27s
> sys     0m 0.11s
> 
> FWIW I also checked the sha1sum to confirm the Image uncompressed OK.
> 
> 
> Johannes

-- 
Markus Oberhumer, <markus at oberhumer.com>, http://www.oberhumer.com/


From jason77.wang at gmail.com  Thu Aug 16 02:48:00 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 14:48:00 +0800
Subject: [PATCH v3 2/3] Input: add devicetree binding note for egalax_ts
In-Reply-To: <20120815125353.GA2258@S2101-09.ap.freescale.net>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
 <20120815125353.GA2258@S2101-09.ap.freescale.net>
Message-ID: <502C97A0.2010902@gmail.com>

Shawn Guo wrote:
> On Wed, Aug 15, 2012 at 06:31:47PM +0800, Hui Wang wrote:
>   
>> The egalax_ts driver needs to get the gpio number of the irq pin,
>> and use this gpio to wake up the controller. So add a note
>> for this change.
>>
>> Signed-off-by: Hui Wang <jason77.wang at gmail.com>
>> ---
>>  .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++++++
>>  1 files changed, 19 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
>>
>> diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
>> new file mode 100644
>> index 0000000..df70318
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
>> @@ -0,0 +1,19 @@
>> +* EETI eGalax Multiple Touch Controller
>> +
>> +Required properties:
>> +- compatible: must be "eeti,egalax_ts"
>>     
>
> Since we define this in the binding anyway, can we have an corresponding
> .of_match_table in the driver?
>
> Regards,
> Shawn
>
>   
OK, will add it in the driver.

Regards,
Hui.


From jason77.wang at gmail.com  Thu Aug 16 02:53:23 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 14:53:23 +0800
Subject: [PATCH v3 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <20120815130108.GB2258@S2101-09.ap.freescale.net>
References: <1345026708-14139-1-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-2-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-3-git-send-email-jason77.wang@gmail.com>
 <1345026708-14139-4-git-send-email-jason77.wang@gmail.com>
 <20120815130108.GB2258@S2101-09.ap.freescale.net>
Message-ID: <502C98E3.5080306@gmail.com>

Shawn Guo wrote:
> On Wed, Aug 15, 2012 at 06:31:48PM +0800, Hui Wang wrote:
>   
>> i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
>> touchscreen controller, add it as an i2c slave device in the dts.
>>
>> Signed-off-by: Hui Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/boot/dts/imx6q-sabrelite.dts |   16 ++++++++++++++++
>>  arch/arm/boot/dts/imx6q.dtsi          |    7 +++++++
>>  2 files changed, 23 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
>> index 72f30f3..4a68e1f 100644
>> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
>> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
>> @@ -54,6 +54,7 @@
>>  							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
>>  							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
>>  							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */
>> +							   972  0x10		/* MX6Q_PAD_GPIO_9__GPIO_1_9 */
>>  							   >;
>>  					};
>>  				};
>> @@ -115,6 +116,21 @@
>>  					VDDIO-supply = <&reg_3p3v>;
>>  				};
>>  			};
>> +
>> +			i2c at 021a8000 { /* I2C3 */
>> +				status = "okay";
>> +				clock-frequency = <100000>;
>> +				pinctrl-names = "default";
>> +				pinctrl-0 = <&pinctrl_i2c3_1>;
>> +
>> +				egalax_ts at 04 {
>> +					compatible = "eeti,egalax_ts";
>> +					reg = <0x04>;
>> +					interrupt-parent = <&gpio1>;
>> +					interrupts = <9 2>;
>>     
>
> So you take this interrupt as falling-edge, while I see IRQF_TRIGGER_LOW
> is used in driver with request_threaded_irq call.
>
> Regards,
> Shawn
>
>   
Yes, you are right. Should be 8 instead of 2.

Regards,
Hui.


From arnd at arndb.de  Thu Aug 16 03:03:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 07:03:50 +0000
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120816045539.GA17067@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <201208152025.25252.arnd@arndb.de>
 <20120816045539.GA17067@avionic-0098.mockup.avionic-design.de>
Message-ID: <201208160703.50364.arnd@arndb.de>

On Thursday 16 August 2012, Thierry Reding wrote:
> At least for the config space this is incorrect. There's a single region
> to access the configuration space for all devices below the PCIe
> controller. So it is shared by both (Tegra20) or all three (Tegra30)
> root ports.
> 
> I'm not sure about PCI domains. Do you have any good pointers as to
> where I could read up on them? If they need special hardware support,
> then I think Tegra doesn't support them either. At least I haven't come
> across any mention of domains while going through the, admittedly some-
> what sparse on PCIe, Tegra documentation.

I was referring to the same thing here: if you had a separate config
space for each root port, they would by definition be separate PCI
domain. So you don't have them.

	Arnd


From richard.genoud at gmail.com  Thu Aug 16 03:07:25 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 16 Aug 2012 09:07:25 +0200
Subject: [PATCH 00/23] work in progress: SPI controller w/DMA SAM9X5
In-Reply-To: <502A8F5C.6000303@atmel.com>
References: <1344952177-18385-1-git-send-email-richard.genoud@gmail.com>
 <502A6EEC.2010807@atmel.com> <20120814174425.GD8836@game.jcrosoft.org>
 <502A8F5C.6000303@atmel.com>
Message-ID: <CACQ1gAjCXyOtfNd7odv3bJb3JQ7WYrCTS=VaLyOiG8+GtPYpeg@mail.gmail.com>

2012/8/14 Nicolas Ferre <nicolas.ferre at atmel.com>:
>>>>   add at91sam9x5 Kconfig ARCH/SOC link
>>>
>>> Is it fixup for a bug? Jean-Christophe, a though about this one?
>> no the ARCH_xxx is old style can not be used on DT only soc
>>
>> this patch need to be droped
>
> That is what I suspected, thanks J.
Yes, Jean-Christophe is right. This patch needs to be dropped, and
this one should be applied instead:

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 169592a..f45d823 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -76,7 +76,7 @@ config SPI_ATMEL

 config SPI_ATMEL_DMA
 	bool "Atmel SPI DMA support"
-	depends on SPI_ATMEL && (ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5) &&
DMA_ENGINE && EXPERIMENTAL
+	depends on SPI_ATMEL && (SOC_AT91SAM9G45 || SOC_AT91SAM9X5) &&
DMA_ENGINE && EXPERIMENTAL
 	default y
 	help
 	  Say Y here if you want the Atmel SPI driver to use the DMA engine.
Data transfers

Richard.

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From arnd at arndb.de  Thu Aug 16 03:17:03 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 07:17:03 +0000
Subject: [PATCH V3 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <1345086525-12328-4-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
 <1345086525-12328-4-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208160717.03707.arnd@arndb.de>

On Thursday 16 August 2012, Chao Xie wrote:

> +enum {
> +	clk32, vctcxo, pll1, pll1_2, pll1_4, pll1_8, pll1_16, pll1_6, pll1_12,
> +	pll1_24, pll1_48, pll1_96, pll1_13, pll1_13_1_5, pll1_2_1_5,
> +	pll1_3_16, uart_pll, twsi0, twsi1, gpio, kpc, rtc, pwm0, pwm1, pwm2,
> +	pwm3, uart0_mux, uart0, uart1_mux, uart1, uart2_mux, uart2,
> +	ssp0_mux, ssp0, ssp1_mux, ssp1, dfc, sdh0_mux, sdh0, sdh1_mux, sdh1,
> +	usb, sph, disp0_mux, disp0, ccic0_mux, ccic0, ccic0_phy_mux,
> +	ccic0_phy, ccic0_sphy_div, ccic0_sphy, clk_max
> +};

I wonder whether you should just get rid of this enum

> +void __init pxa910_clk_init(void)
> +{
> +	struct clk *clocks[clk_max];

and this array,

> +	clocks[clk32] =
> +	    clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
> +	clk_register_clkdev(clocks[clk32], "clk32", NULL);
> +
> +	clocks[vctcxo] =
> +	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
> +				    26000000);
> +	clk_register_clkdev(clocks[vctcxo], "vctcxo", NULL);

because now that the "obfuscation" macro is gone, it's clear that each index
is used only once here and then passed right into the next function. If you
write it like:

	struct clk *clk;

	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
	clk_register_clkdev(clk, "clk32", NULL);

it becomes much shorter, partly because things start fitting into one
line again. The only exception in this file is 

> +	clocks[uart_pll] =
> +	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
> +				    mpmu_base + MPMU_UART_PLL,
> +				    &uart_factor_masks, uart_factor_tbl,
> +				    ARRAY_SIZE(uart_factor_tbl));
> +	clk_set_rate(clocks[uart_pll], 14745600);
> +	clk_register_clkdev(clocks[uart_pll], "uart_pll", NULL);

with

> +	clocks[uart0_mux] =
> +	    clk_register_mux(NULL, "uart0_mux", uart_parent,
> +			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
> +			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
> +	clk_set_parent(clocks[uart0_mux], clocks[uart_pll]);
> +	clk_register_clkdev(clocks[uart0_mux], "uart_mux.0", NULL);
> +
> +	clocks[uart0] =
> +	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
> +				  10, 0, &clk_lock);
> +	clk_register_clkdev(clocks[uart0], NULL, "pxa2xx-uart.0");

so just add another

	struct clk *clk_uart;

	clk_uart = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
			mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl,
			ARRAY_SIZE(uart_factor_tbl));



	Arnd


From arnd at arndb.de  Thu Aug 16 03:18:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 07:18:01 +0000
Subject: [PATCH V3 1/5] clk: mmp: add mmp specific clocks
In-Reply-To: <1345086525-12328-2-git-send-email-xiechao.mail@gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
 <1345086525-12328-2-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208160718.01769.arnd@arndb.de>

On Thursday 16 August 2012, Chao Xie wrote:
> +static int clk_apbc_prepare(struct clk_hw *hw)
> +{
> +       struct clk_apbc *apbc = to_clk_apbc(hw);
> +       unsigned int data;
> +       unsigned long flags = 0;
> +
> +       /*
> +        * It may share same register as MUX clock,
> +        * and it will impact FNCLK enable. Spinlock is needed
> +        */
> +       if (apbc->lock)
> +               spin_lock_irqsave(apbc->lock, flags);
> +
> +       data = __raw_readl(apbc->base);
> +       if (apbc->flags & APBC_POWER_CTRL)
> +               data |= APBC_POWER;
> +       data |= APBC_FNCLK;
> +       __raw_writel(data, apbc->base);

It seems you have missed a few __raw_readl/__raw_writel that still
want to get changed to readl_relaxed/writel_relaxed.

	Arnd


From xiechao.mail at gmail.com  Thu Aug 16 03:37:42 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Thu, 16 Aug 2012 15:37:42 +0800
Subject: [PATCH V3 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <201208160717.03707.arnd@arndb.de>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
 <1345086525-12328-4-git-send-email-xiechao.mail@gmail.com>
 <201208160717.03707.arnd@arndb.de>
Message-ID: <CADApbej91_Y84sC9R1b0+LgDTzFUH8CveYsDi4wDWOQxkGnnFg@mail.gmail.com>

On Thu, Aug 16, 2012 at 3:17 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 16 August 2012, Chao Xie wrote:
>
>> +enum {
>> +     clk32, vctcxo, pll1, pll1_2, pll1_4, pll1_8, pll1_16, pll1_6, pll1_12,
>> +     pll1_24, pll1_48, pll1_96, pll1_13, pll1_13_1_5, pll1_2_1_5,
>> +     pll1_3_16, uart_pll, twsi0, twsi1, gpio, kpc, rtc, pwm0, pwm1, pwm2,
>> +     pwm3, uart0_mux, uart0, uart1_mux, uart1, uart2_mux, uart2,
>> +     ssp0_mux, ssp0, ssp1_mux, ssp1, dfc, sdh0_mux, sdh0, sdh1_mux, sdh1,
>> +     usb, sph, disp0_mux, disp0, ccic0_mux, ccic0, ccic0_phy_mux,
>> +     ccic0_phy, ccic0_sphy_div, ccic0_sphy, clk_max
>> +};
>
> I wonder whether you should just get rid of this enum
>
>> +void __init pxa910_clk_init(void)
>> +{
>> +     struct clk *clocks[clk_max];
>
> and this array,
>
>> +     clocks[clk32] =
>> +         clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
>> +     clk_register_clkdev(clocks[clk32], "clk32", NULL);
>> +
>> +     clocks[vctcxo] =
>> +         clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
>> +                                 26000000);
>> +     clk_register_clkdev(clocks[vctcxo], "vctcxo", NULL);
>
> because now that the "obfuscation" macro is gone, it's clear that each index
> is used only once here and then passed right into the next function. If you
> write it like:
>
>         struct clk *clk;
>
>         clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
>         clk_register_clkdev(clk, "clk32", NULL);
>
> it becomes much shorter, partly because things start fitting into one
> line again. The only exception in this file is
>
>> +     clocks[uart_pll] =
>> +         mmp_clk_register_factor("uart_pll", "pll1_4", 0,
>> +                                 mpmu_base + MPMU_UART_PLL,
>> +                                 &uart_factor_masks, uart_factor_tbl,
>> +                                 ARRAY_SIZE(uart_factor_tbl));
>> +     clk_set_rate(clocks[uart_pll], 14745600);
>> +     clk_register_clkdev(clocks[uart_pll], "uart_pll", NULL);
>
> with
>
>> +     clocks[uart0_mux] =
>> +         clk_register_mux(NULL, "uart0_mux", uart_parent,
>> +                          ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
>> +                          apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
>> +     clk_set_parent(clocks[uart0_mux], clocks[uart_pll]);
>> +     clk_register_clkdev(clocks[uart0_mux], "uart_mux.0", NULL);
>> +
>> +     clocks[uart0] =
>> +         mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
>> +                               10, 0, &clk_lock);
>> +     clk_register_clkdev(clocks[uart0], NULL, "pxa2xx-uart.0");
>
> so just add another
>
>         struct clk *clk_uart;
>
>         clk_uart = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
>                         mpmu_base + MPMU_UART_PLL, &uart_factor_masks, uart_factor_tbl,
>                         ARRAY_SIZE(uart_factor_tbl));
>
>
>
>         Arnd
i can change remove the clocks array, but even make the sentence
shorter, most of them still can not fit in one line.


From hdk at igel.co.jp  Thu Aug 16 03:42:02 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Thu, 16 Aug 2012 16:42:02 +0900
Subject: [PATCH v2 0/2] Renesas IPMMU driver for sh7372
Message-ID: <1345102924-22045-1-git-send-email-hdk@igel.co.jp>

This is the Renesas IPMMU driver, IOMMU API implementation and IPMMU
device support for sh7372 (AP4EVB and Mackerel).

The IPMMU module supports the MMU function and the PMB function.  The
MMU function provides address translation by pagetable compatible with
ARMv6.  The PMB function provides address translation including
tile-linear translation.  This is implementation of the MMU function.

v2:
- Rebased on v3.6-rc1.
- Make variable names clear.
- Page table size can now be selected by config.

Hideki EIRAKU (2):
  iommu/shmobile: Add iommu driver for Renesas IPMMU modules
  ARM: mach-shmobile: sh7372: Add IPMMU device

 arch/arm/mach-shmobile/Kconfig              |    6 +
 arch/arm/mach-shmobile/Makefile             |    3 +
 arch/arm/mach-shmobile/board-ap4evb.c       |    5 +
 arch/arm/mach-shmobile/board-mackerel.c     |    5 +
 arch/arm/mach-shmobile/include/mach/ipmmu.h |   10 +
 arch/arm/mach-shmobile/ipmmu.c              |  130 ++++++++++
 arch/arm/mach-shmobile/setup-sh7372.c       |   22 ++
 drivers/iommu/Kconfig                       |   35 +++
 drivers/iommu/Makefile                      |    1 +
 drivers/iommu/shmobile-iommu.c              |  342 +++++++++++++++++++++++++++
 10 files changed, 559 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/include/mach/ipmmu.h
 create mode 100644 arch/arm/mach-shmobile/ipmmu.c
 create mode 100644 drivers/iommu/shmobile-iommu.c



From hdk at igel.co.jp  Thu Aug 16 03:42:04 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Thu, 16 Aug 2012 16:42:04 +0900
Subject: [PATCH v2 2/2] ARM: mach-shmobile: sh7372: Add IPMMU device
In-Reply-To: <1345102924-22045-1-git-send-email-hdk@igel.co.jp>
References: <1345102924-22045-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1345102924-22045-3-git-send-email-hdk@igel.co.jp>

This patch adds an IPMMU device and notifies the IPMMU driver which
devices are connected via the IPMMU module.  All devices connected to the main
memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and
SHMOBILE_IOMMU are enabled because physical address cannot be used
while the IPMMU module's MMU function is enabled.

Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
---
 arch/arm/mach-shmobile/board-ap4evb.c   |    5 +++++
 arch/arm/mach-shmobile/board-mackerel.c |    5 +++++
 arch/arm/mach-shmobile/setup-sh7372.c   |   22 ++++++++++++++++++++++
 3 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f172ca8..ce6d796 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,6 +61,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
+#include <mach/ipmmu.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -1448,6 +1449,10 @@ static void __init ap4evb_init(void)
 
 	sh7372_add_standard_devices();
 
+	ipmmu_add_device(&lcdc_device.dev);
+	ipmmu_add_device(&lcdc1_device.dev);
+	ipmmu_add_device(&ceu_device.dev);
+
 	/* HDMI */
 	gpio_request(GPIO_FN_HDMI_HPD, NULL);
 	gpio_request(GPIO_FN_HDMI_CEC, NULL);
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7ea2b31..ac1adb5 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -60,6 +60,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
+#include <mach/ipmmu.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -1621,6 +1622,10 @@ static void __init mackerel_init(void)
 
 	sh7372_add_standard_devices();
 
+	ipmmu_add_device(&lcdc_device.dev);
+	ipmmu_add_device(&hdmi_lcdc_device.dev);
+	ipmmu_add_device(&ceu_device.dev);
+
 	platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
 	rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 838a87b..1106b4f 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -38,6 +38,7 @@
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 #include <mach/common.h>
+#include <mach/ipmmu.h>
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -968,6 +969,23 @@ static struct platform_device spu1_device = {
 	.num_resources	= ARRAY_SIZE(spu1_resources),
 };
 
+/* IPMMUI (an IPMMU module for ICB/LMB) */
+static struct resource ipmmu_resources[] = {
+	[0] = {
+		.name	= "IPMMUI",
+		.start	= 0xfe951000,
+		.end	= 0xfe9510ff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device ipmmu_device = {
+	.name           = "ipmmu",
+	.id             = -1,
+	.resource       = ipmmu_resources,
+	.num_resources  = ARRAY_SIZE(ipmmu_resources),
+};
+
 static struct platform_device *sh7372_early_devices[] __initdata = {
 	&scif0_device,
 	&scif1_device,
@@ -979,6 +997,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
 	&cmt2_device,
 	&tmu00_device,
 	&tmu01_device,
+	&ipmmu_device,
 };
 
 static struct platform_device *sh7372_late_devices[] __initdata = {
@@ -1020,6 +1039,9 @@ void __init sh7372_add_standard_devices(void)
 	platform_add_devices(sh7372_early_devices,
 			    ARRAY_SIZE(sh7372_early_devices));
 
+	ipmmu_add_device(&vpu_device.dev);
+	ipmmu_add_device(&jpu_device.dev);
+
 	platform_add_devices(sh7372_late_devices,
 			    ARRAY_SIZE(sh7372_late_devices));
 
-- 
1.7.0.4



From hdk at igel.co.jp  Thu Aug 16 03:42:03 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Thu, 16 Aug 2012 16:42:03 +0900
Subject: [PATCH v2 1/2] iommu/shmobile: Add iommu driver for Renesas IPMMU
 modules
In-Reply-To: <1345102924-22045-1-git-send-email-hdk@igel.co.jp>
References: <1345102924-22045-1-git-send-email-hdk@igel.co.jp>
Message-ID: <1345102924-22045-2-git-send-email-hdk@igel.co.jp>

This is the Renesas IPMMU driver and IOMMU API implementation.

The IPMMU module supports the MMU function and the PMB function.  The
MMU function provides address translation by pagetable compatible with
ARMv6.  The PMB function provides address translation including
tile-linear translation.  This patch implements the MMU function.

The iommu driver does not register a platform driver directly because:
- the register space of the MMU function and the PMB function
  have a common register (used for settings flush), so they should ideally
  have a way to appropriately share this register.
- the MMU function uses the IOMMU API while the PMB function does not.
- the two functions may be used independently.

Signed-off-by: Hideki EIRAKU <hdk at igel.co.jp>
---
 arch/arm/mach-shmobile/Kconfig              |    6 +
 arch/arm/mach-shmobile/Makefile             |    3 +
 arch/arm/mach-shmobile/include/mach/ipmmu.h |   10 +
 arch/arm/mach-shmobile/ipmmu.c              |  130 ++++++++++
 drivers/iommu/Kconfig                       |   35 +++
 drivers/iommu/Makefile                      |    1 +
 drivers/iommu/shmobile-iommu.c              |  342 +++++++++++++++++++++++++++
 7 files changed, 527 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-shmobile/include/mach/ipmmu.h
 create mode 100644 arch/arm/mach-shmobile/ipmmu.c
 create mode 100644 drivers/iommu/shmobile-iommu.c

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4cacc2d..1add9bd 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -210,6 +210,12 @@ endmenu
 config SH_CLK_CPG
 	bool
 
+config SHMOBILE_IPMMU
+	bool "IPMMU/IPMMUI driver"
+	default n
+	help
+	  This enables build of the IPMMU/IPMMUI driver.
+
 source "drivers/sh/Kconfig"
 
 endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0df5ae6..1e72199 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -60,3 +60,6 @@ obj-$(CONFIG_MACH_KZM9G)	+= board-kzm9g.o
 # Framework support
 obj-$(CONFIG_SMP)		+= $(smp-y)
 obj-$(CONFIG_GENERIC_GPIO)	+= $(pfc-y)
+
+# IPMMU/IPMMUI
+obj-$(CONFIG_SHMOBILE_IPMMU)	+= ipmmu.o
diff --git a/arch/arm/mach-shmobile/include/mach/ipmmu.h b/arch/arm/mach-shmobile/include/mach/ipmmu.h
new file mode 100644
index 0000000..afbd9eb
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/ipmmu.h
@@ -0,0 +1,10 @@
+#ifdef CONFIG_SHMOBILE_IPMMU
+void ipmmu_tlb_flush(void);
+void ipmmu_tlb_set(unsigned long phys, int size, int asid);
+void ipmmu_add_device(struct device *dev);
+int ipmmu_iommu_init(struct device *dev);
+#else
+static inline void ipmmu_add_device(struct device *dev)
+{
+}
+#endif
diff --git a/arch/arm/mach-shmobile/ipmmu.c b/arch/arm/mach-shmobile/ipmmu.c
new file mode 100644
index 0000000..c6a11fb
--- /dev/null
+++ b/arch/arm/mach-shmobile/ipmmu.c
@@ -0,0 +1,130 @@
+/*
+ * IPMMU/IPMMUI
+ * Copyright (C) 2012  Hideki EIRAKU
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <mach/ipmmu.h>
+
+#define IMCTR1 0x000
+#define IMCTR2 0x004
+#define IMASID 0x010
+#define IMTTBR 0x014
+#define IMTTBCR 0x018
+
+#define IMCTR1_TLBEN (1 << 0)
+#define IMCTR1_FLUSH (1 << 1)
+
+static void __iomem *ipmmu_base;
+static int tlb_enabled;
+
+void __attribute__((weak)) ipmmu_add_device(struct device *dev)
+{
+}
+
+void ipmmu_tlb_flush(void)
+{
+	if (!ipmmu_base)
+		return;
+	if (tlb_enabled)
+		iowrite32(IMCTR1_FLUSH | IMCTR1_TLBEN, ipmmu_base + IMCTR1);
+	else
+		iowrite32(IMCTR1_FLUSH, ipmmu_base + IMCTR1);
+}
+
+void ipmmu_tlb_set(unsigned long phys, int size, int asid)
+{
+	if (!ipmmu_base)
+		return;
+	switch (size) {
+	default:
+		tlb_enabled = 0;
+		break;
+	case 0x2000:
+		iowrite32(1, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x1000:
+		iowrite32(2, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x800:
+		iowrite32(3, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x400:
+		iowrite32(4, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x200:
+		iowrite32(5, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x100:
+		iowrite32(6, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	case 0x80:
+		iowrite32(7, ipmmu_base + IMTTBCR);
+		tlb_enabled = 1;
+		break;
+	}
+	iowrite32(phys, ipmmu_base + IMTTBR);
+	iowrite32(asid, ipmmu_base + IMASID);
+}
+
+int __attribute__((weak)) ipmmu_iommu_init(struct device *dev)
+{
+	return 0;
+}
+
+static int __devinit ipmmu_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "cannot get platform resources\n");
+		return -ENOENT;
+	}
+	ipmmu_base = ioremap_nocache(res->start, resource_size(res));
+	if (!ipmmu_base) {
+		dev_err(&pdev->dev, "ioremap_nocache failed\n");
+		return -ENOMEM;
+	}
+	iowrite32(0x0, ipmmu_base + IMCTR1); /* disable TLB */
+	iowrite32(0x0, ipmmu_base + IMCTR2); /* disable PMB */
+	ipmmu_iommu_init(&pdev->dev);
+	return 0;
+}
+
+static struct platform_driver ipmmu_driver = {
+	.probe = ipmmu_probe,
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "ipmmu",
+	},
+};
+
+static int __init ipmmu_init(void)
+{
+	return platform_driver_register(&ipmmu_driver);
+}
+subsys_initcall(ipmmu_init);
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 9f69b56..4d501b3 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -187,4 +187,39 @@ config EXYNOS_IOMMU_DEBUG
 
 	  Say N unless you need kernel log message for IOMMU debugging
 
+config SHMOBILE_IOMMU
+	bool "IOMMU for Renesas IPMMU/IPMMUI"
+	default n
+	depends on SHMOBILE_IPMMU
+	select IOMMU_API
+	select ARM_DMA_USE_IOMMU
+
+choice
+	prompt "IPMMU/IPMMUI 1st level page table size"
+	default SHMOBILE_IOMMU_L1SIZE_8192
+	depends on SHMOBILE_IOMMU
+
+	config SHMOBILE_IOMMU_L1SIZE_8192
+		bool "8192 bytes (2 GiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_4096
+		bool "4096 bytes (1 GiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_2048
+		bool "2048 bytes (512 MiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_1024
+		bool "1024 bytes (256 MiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_512
+		bool "512 bytes (128 MiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_256
+		bool "256 bytes (64 MiB address space)"
+
+	config SHMOBILE_IOMMU_L1SIZE_128
+		bool "128 bytes (32 MiB address space)"
+
+endchoice
+
 endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 14a4d5f..62cf917 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
 obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
 obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
 obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
+obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
diff --git a/drivers/iommu/shmobile-iommu.c b/drivers/iommu/shmobile-iommu.c
new file mode 100644
index 0000000..3a84286
--- /dev/null
+++ b/drivers/iommu/shmobile-iommu.c
@@ -0,0 +1,342 @@
+/*
+ * IOMMU for IPMMU/IPMMUI
+ * Copyright (C) 2012  Hideki EIRAKU
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/dmapool.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/iommu.h>
+#include <linux/dma-mapping.h>
+#include <mach/ipmmu.h>
+#include <asm/dma-iommu.h>
+
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_8192
+#define L1_SIZE 8192
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_4096
+#define L1_SIZE 4096
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_2048
+#define L1_SIZE 2048
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_1024
+#define L1_SIZE 1024
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_512
+#define L1_SIZE 512
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_256
+#define L1_SIZE 256
+#endif
+#ifdef CONFIG_SHMOBILE_IOMMU_L1SIZE_128
+#define L1_SIZE 128
+#endif
+#define L1_LEN (L1_SIZE / 4)
+#define L1_ALIGN L1_SIZE
+#define L2_SIZE 0x400
+#define L2_LEN (L2_SIZE / 4)
+#define L2_ALIGN L2_SIZE
+
+struct shmobile_iommu_priv_pgtable {
+	uint32_t *pgtable;
+	dma_addr_t handle;
+};
+
+struct shmobile_iommu_priv {
+	struct shmobile_iommu_priv_pgtable l1, l2[L1_LEN];
+	spinlock_t map_lock;
+	atomic_t active;
+};
+
+static struct dma_iommu_mapping *iommu_mapping;
+static struct device *ipmmu_devices;
+static struct dma_pool *l1pool, *l2pool;
+static spinlock_t lock;
+static DEFINE_SPINLOCK(lock_add);
+static struct shmobile_iommu_priv *attached;
+static int num_attached_devices;
+
+static int shmobile_iommu_domain_init(struct iommu_domain *domain)
+{
+	struct shmobile_iommu_priv *priv;
+	int i;
+
+	priv = kmalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	priv->l1.pgtable = dma_pool_alloc(l1pool, GFP_KERNEL,
+					  &priv->l1.handle);
+	if (!priv->l1.pgtable) {
+		kfree(priv);
+		return -ENOMEM;
+	}
+	for (i = 0; i < L1_LEN; i++)
+		priv->l2[i].pgtable = NULL;
+	memset(priv->l1.pgtable, 0, L1_SIZE);
+	spin_lock_init(&priv->map_lock);
+	atomic_set(&priv->active, 0);
+	domain->priv = priv;
+	return 0;
+}
+
+static void shmobile_iommu_domain_destroy(struct iommu_domain *domain)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+	int i;
+
+	for (i = 0; i < L1_LEN; i++) {
+		if (priv->l2[i].pgtable)
+			dma_pool_free(l2pool, priv->l2[i].pgtable,
+				      priv->l2[i].handle);
+	}
+	dma_pool_free(l1pool, priv->l1.pgtable, priv->l1.handle);
+	kfree(priv);
+	domain->priv = NULL;
+}
+
+static int shmobile_iommu_attach_device(struct iommu_domain *domain,
+					struct device *dev)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+	int ret = -EBUSY;
+
+	spin_lock(&lock);
+	if (attached != priv) {
+		if (attached)
+			goto err;
+		atomic_set(&priv->active, 1);
+		ipmmu_tlb_set(priv->l1.handle, L1_SIZE, 0);
+		wmb();
+		ipmmu_tlb_flush();
+		attached = priv;
+		num_attached_devices = 0;
+	}
+	num_attached_devices++;
+	ret = 0;
+err:
+	spin_unlock(&lock);
+	return ret;
+}
+
+static void shmobile_iommu_detach_device(struct iommu_domain *domain,
+					 struct device *dev)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+
+	spin_lock(&lock);
+	atomic_set(&priv->active, 0);
+	num_attached_devices--;
+	if (!num_attached_devices) {
+		ipmmu_tlb_set(0, 0, 0);
+		ipmmu_tlb_flush();
+		attached = NULL;
+	}
+	spin_unlock(&lock);
+}
+
+static int
+l2alloc(struct shmobile_iommu_priv *priv, unsigned int l1index)
+{
+	if (!priv->l2[l1index].pgtable) {
+		priv->l2[l1index].pgtable = dma_pool_alloc(l2pool, GFP_KERNEL,
+						&priv->l2[l1index].handle);
+		if (!priv->l2[l1index].pgtable)
+			return -ENOMEM;
+		memset(priv->l2[l1index].pgtable, 0, L2_SIZE);
+	}
+	priv->l1.pgtable[l1index] = priv->l2[l1index].handle | 0x1;
+	return 0;
+}
+
+static int shmobile_iommu_map(struct iommu_domain *domain, unsigned long iova,
+			      phys_addr_t paddr, size_t size, int prot)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+	unsigned int l1index, l2index, i;
+	int ret;
+
+	l1index = iova >> 20;
+	switch (size) {
+	case 0x1000:
+		l2index = (iova >> 12) & 0xff;
+		spin_lock(&priv->map_lock);
+		ret = l2alloc(priv, l1index);
+		if (!ret)
+			priv->l2[l1index].pgtable[l2index] = paddr | 0xff2;
+		spin_unlock(&priv->map_lock);
+		break;
+	case 0x10000:
+		l2index = (iova >> 12) & 0xf0;
+		spin_lock(&priv->map_lock);
+		ret = l2alloc(priv, l1index);
+		if (!ret) {
+			for (i = 0; i < 0x10; i++)
+				priv->l2[l1index].pgtable[l2index + i] =
+					paddr | 0xff1;
+		}
+		spin_unlock(&priv->map_lock);
+		break;
+	case 0x100000:
+		spin_lock(&priv->map_lock);
+		priv->l1.pgtable[l1index] = paddr | 0xc02;
+		spin_unlock(&priv->map_lock);
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	if (!ret && atomic_read(&priv->active)) {
+		wmb();
+		ipmmu_tlb_flush();
+	}
+	return ret;
+}
+
+static size_t shmobile_iommu_unmap(struct iommu_domain *domain,
+				   unsigned long iova, size_t size)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+	unsigned int l1index, l2index, i;
+
+	l1index = iova >> 20;
+	switch (size) {
+	case 0x1000:
+		l2index = (iova >> 12) & 0xff;
+		spin_lock(&priv->map_lock);
+		if (priv->l2[l1index].pgtable)
+			priv->l2[l1index].pgtable[l2index] = 0;
+		spin_unlock(&priv->map_lock);
+		break;
+	case 0x10000:
+		l2index = (iova >> 12) & 0xf0;
+		spin_lock(&priv->map_lock);
+		if (priv->l2[l1index].pgtable) {
+			for (i = 0; i < 0x10; i++)
+				priv->l2[l1index].pgtable[l2index + i] = 0;
+		}
+		spin_unlock(&priv->map_lock);
+		break;
+	case 0x100000:
+		spin_lock(&priv->map_lock);
+		priv->l1.pgtable[l1index] = 0;
+		spin_unlock(&priv->map_lock);
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (atomic_read(&priv->active)) {
+		wmb();
+		ipmmu_tlb_flush();
+	}
+	return size;
+}
+
+static phys_addr_t shmobile_iommu_iova_to_phys(struct iommu_domain *domain,
+					       unsigned long iova)
+{
+	struct shmobile_iommu_priv *priv = domain->priv;
+	uint32_t l1entry = 0, l2entry = 0;
+	unsigned int l1index, l2index;
+
+	l1index = iova >> 20;
+	l2index = (iova >> 12) & 0xff;
+	spin_lock(&priv->map_lock);
+	if (priv->l2[l1index].pgtable)
+		l2entry = priv->l2[l1index].pgtable[l2index];
+	else
+		l1entry = priv->l1.pgtable[l1index];
+	spin_unlock(&priv->map_lock);
+	switch (l2entry & 3) {
+	case 1:
+		return (l2entry & ~0xffff) | (iova & 0xffff);
+	case 2:
+		return (l2entry & ~0xfff) | (iova & 0xfff);
+	default:
+		if ((l1entry & 3) == 2)
+			return (l1entry & ~0xfffff) | (iova & 0xfffff);
+		return 0;
+	}
+}
+
+static struct iommu_ops shmobile_iommu_ops = {
+	.domain_init = shmobile_iommu_domain_init,
+	.domain_destroy = shmobile_iommu_domain_destroy,
+	.attach_dev = shmobile_iommu_attach_device,
+	.detach_dev = shmobile_iommu_detach_device,
+	.map = shmobile_iommu_map,
+	.unmap = shmobile_iommu_unmap,
+	.iova_to_phys = shmobile_iommu_iova_to_phys,
+	.pgsize_bitmap = 0x111000,
+};
+
+static int shmobile_iommu_attach_all_devices(void)
+{
+	struct device *dev;
+	int ret = 0;
+
+	spin_lock(&lock_add);
+	iommu_mapping = arm_iommu_create_mapping(&platform_bus_type, 0x0,
+						 L1_LEN << 20, 0);
+	if (IS_ERR_OR_NULL(iommu_mapping)) {
+		ret = PTR_ERR(iommu_mapping);
+		goto err;
+	}
+	for (dev = ipmmu_devices; dev; dev = dev->archdata.iommu) {
+		if (arm_iommu_attach_device(dev, iommu_mapping))
+			pr_err("arm_iommu_attach_device failed\n");
+	}
+err:
+	spin_unlock(&lock_add);
+	return 0;
+}
+
+void ipmmu_add_device(struct device *dev)
+{
+	spin_lock(&lock_add);
+	dev->archdata.iommu = ipmmu_devices;
+	ipmmu_devices = dev;
+	if (!IS_ERR_OR_NULL(iommu_mapping)) {
+		if (arm_iommu_attach_device(dev, iommu_mapping))
+			pr_err("arm_iommu_attach_device failed\n");
+	}
+	spin_unlock(&lock_add);
+}
+
+int ipmmu_iommu_init(struct device *dev)
+{
+	dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+	l1pool = dma_pool_create("shmobile-iommu-pgtable1", dev,
+				 L1_SIZE, L1_ALIGN, 0);
+	if (!l1pool)
+		goto nomem_pool1;
+	l2pool = dma_pool_create("shmobile-iommu-pgtable2", dev,
+				 L2_SIZE, L2_ALIGN, 0);
+	if (!l2pool)
+		goto nomem_pool2;
+	spin_lock_init(&lock);
+	attached = NULL;
+	bus_set_iommu(&platform_bus_type, &shmobile_iommu_ops);
+	if (shmobile_iommu_attach_all_devices())
+		pr_err("shmobile_iommu_attach_all_devices failed\n");
+	return 0;
+nomem_pool2:
+	dma_pool_destroy(l1pool);
+nomem_pool1:
+	return -ENOMEM;
+}
-- 
1.7.0.4



From thierry.reding at avionic-design.de  Thu Aug 16 03:47:16 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 16 Aug 2012 09:47:16 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <201208160703.50364.arnd@arndb.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <201208152025.25252.arnd@arndb.de>
 <20120816045539.GA17067@avionic-0098.mockup.avionic-design.de>
 <201208160703.50364.arnd@arndb.de>
Message-ID: <20120816074716.GB17917@avionic-0098.mockup.avionic-design.de>

On Thu, Aug 16, 2012 at 07:03:50AM +0000, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Thierry Reding wrote:
> > At least for the config space this is incorrect. There's a single region
> > to access the configuration space for all devices below the PCIe
> > controller. So it is shared by both (Tegra20) or all three (Tegra30)
> > root ports.
> > 
> > I'm not sure about PCI domains. Do you have any good pointers as to
> > where I could read up on them? If they need special hardware support,
> > then I think Tegra doesn't support them either. At least I haven't come
> > across any mention of domains while going through the, admittedly some-
> > what sparse on PCIe, Tegra documentation.
> 
> I was referring to the same thing here: if you had a separate config
> space for each root port, they would by definition be separate PCI
> domain. So you don't have them.

I see, that makes sense. Thanks for explaining.

Thierry
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From haojian.zhuang at gmail.com  Thu Aug 16 03:57:10 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 16 Aug 2012 15:57:10 +0800
Subject: [GIT PULL][for 3.6] pull request from fixes branch in pxa git tree
Message-ID: <CAN1soZw8UC-R0hq4CgsGG20-42z0jYUvbTygF18rn+hhmtJivQ@mail.gmail.com>

Hi Olof & Arnd,

Please help to pull fixes branch from pxa git tree.

Regards
Haojian

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git fixes

for you to fetch changes up to c0db19dabf138741e078f6391fb132821c0d98b5:

  ARM: mmp: fix potential NULL dereference (2012-08-10 22:32:24 +0800)

----------------------------------------------------------------
Yuanhan Liu (1):
      ARM: mmp: fix potential NULL dereference

 arch/arm/mach-mmp/sram.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


From LW at KARO-electronics.de  Thu Aug 16 04:08:04 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Thu, 16 Aug 2012 10:08:04 +0200
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20120815133221.ca88d4ba.akpm@linux-foundation.org>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
 <20120815141606.GA2457@S2101-09.ap.freescale.net>
 <20120815133221.ca88d4ba.akpm@linux-foundation.org>
Message-ID: <20524.43620.36859.792122@ipc1.ka-ro>

Hi,

Andrew Morton writes:
> On Wed, 15 Aug 2012 22:16:10 +0800
> Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > Thanks for looking at the patch, Andrew.
> > 
> > On Tue, Aug 14, 2012 at 05:03:00PM -0700, Andrew Morton wrote:
> > > On Fri, 13 Jul 2012 15:31:03 +0800
> > > Shawn Guo <shawn.guo at linaro.org> wrote:
> > > 
> > > > +static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
> > > > +{
> > > > +	unsigned long timeout = jiffies + msecs_to_jiffies(1);
> > > > +	unsigned long flags;
> > > > +	u32 lpcr;
> > > > +
> > > > +	spin_lock_irqsave(&data->lock, flags);
> > > > +
> > > > +	lpcr = readl(data->ioaddr + SNVS_LPCR);
> > > > +	if (enable)
> > > > +		lpcr |= SNVS_LPCR_SRTC_ENV;
> > > > +	else
> > > > +		lpcr &= ~SNVS_LPCR_SRTC_ENV;
> > > > +	writel(lpcr, data->ioaddr + SNVS_LPCR);
> > > > +
> > > > +	spin_unlock_irqrestore(&data->lock, flags);
> > > > +
> > > > +	while (1) {
> > > > +		lpcr = readl(data->ioaddr + SNVS_LPCR);
> > > > +
> > > > +		if (enable) {
> > > > +			if (lpcr & SNVS_LPCR_SRTC_ENV)
> > > > +				break;
> > > > +		} else {
> > > > +			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
> > > > +				break;
> > > > +		}
> > > > +
> > > > +		if (time_after(jiffies, timeout))
> > > > +			return -ETIMEDOUT;
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +}
> > > 
> > > The timeout code here is fragile.  If acquiring the spinlock takes more
> > > than a millisecond or if this thread gets interrupted or preempted then
> > > we could easily execute that loop just a single time, and fail.
> > > 
> > So what about moving the timeout initialization to right above the
> > while(1) loop?
> 
> It still has the same problem - a well-timed preemption would cause a
> timeout.
> 
> > > It would be better to retry a fixed number of times, say 1000?  That
> > > would take around 1 millisecond, but might be overkill.
> > > 
> > How long a 1000 times loop takes really depends on the cpu frequency,
> > right?
> 
> No, it will depend on the preiod of that readl(), which typically takes
> much much longer than a cpu cycle.  It depends a lot on the bus type
> but I'd guess that the readl would take 100's of nanoseconds.  Thus we
> can use the expected readl duration to control the timeout interval.
> 
Why not read the register once more in case of a timeout, which
would guarantee to have a current view of the register contents no
matter how long the process may have been descheduled before:

[...]
static int snvs_rtc_enable_done(int enable, void __iomem *addr)
{
	u32 lpcr = readl(addr + SNVS_LPCR);

	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
}
[...]
	while (1) {
		if (svns_rtc_enable_done(enable, data->ioaddr))
			break;

		if (time_after(jiffies, timeout)) {
			if (!svns_rtc_enable_done(enable, data->ioaddr))
				return -ETIMEDOUT;
		}
	}


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
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www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From shawn.guo at linaro.org  Thu Aug 16 04:08:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 16:08:44 +0800
Subject: [PATCH 0/2] Move imx6q clock lookup over to device tree
Message-ID: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>

The series adds a generic of_clk_src_onecell_get() function into clock
framework, and then moves imx6q clock lookup over to device tree, so
that any new clock lookup to be added at later time does not need to
patch kerenel.

Shawn Guo (2):
  clk: add of_clk_src_onecell_get() support
  ARM: imx6q: replace clk_register_clkdev with clock DT lookup

 .../devicetree/bindings/clock/imx6q-clock.txt      |  223 +++++++++++++++++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |  261 +++++++++++++++++++-
 arch/arm/mach-imx/clk-imx6q.c                      |   41 +---
 arch/arm/mach-imx/mach-imx6q.c                     |    1 -
 drivers/clk/clk.c                                  |   15 ++
 include/linux/clk-provider.h                       |    1 +
 7 files changed, 493 insertions(+), 50 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt

-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Aug 16 04:08:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 16:08:45 +0800
Subject: [PATCH 1/2] clk: add of_clk_src_onecell_get() support
In-Reply-To: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345104526-14797-2-git-send-email-shawn.guo@linaro.org>

For those SoCs that have hundreds of clock outputs, their clock
DT bindings could reasonably define #clock-cells as 1 and require
the client device specify the index of the clock it consumes in the
cell of its "clocks" phandle.

Add a generic of_clk_src_onecell_get() function for this purpose.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk.c            |   15 +++++++++++++++
 include/linux/clk-provider.h |    1 +
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index efdfd00..06bc0b5 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1582,6 +1582,21 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 }
 EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
 
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
+{
+	const char *clk_name;
+	int idx = clkspec->args[0];
+	int ret;
+
+	ret = of_property_read_string_index(clkspec->np, "clock-output-names",
+					    idx, &clk_name);
+	if (ret < 0)
+		return ERR_PTR(ret);
+
+	return __clk_lookup(clk_name);
+}
+EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
+
 /**
  * of_clk_add_provider() - Register a clock provider for a node
  * @np: Device node pointer associated with clock provider
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fa..2afcadf 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -360,6 +360,7 @@ int of_clk_add_provider(struct device_node *np,
 void of_clk_del_provider(struct device_node *np);
 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 				  void *data);
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 void of_clk_init(const struct of_device_id *matches);
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Aug 16 04:08:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 16 Aug 2012 16:08:46 +0800
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>

It really becomes an issue that every time a device needs to look
up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx6q client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx6q-clock.txt      |  223 +++++++++++++++++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |  261 +++++++++++++++++++-
 arch/arm/mach-imx/clk-imx6q.c                      |   41 +---
 arch/arm/mach-imx/mach-imx6q.c                     |    1 -
 5 files changed, 477 insertions(+), 50 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 0000000..19d8126
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,223 @@
+* Clock bindings for Freescale i.MX6 Quad
+
+Required properties:
+- compatible: Should be "fsl,imx6q-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+- clock-output-names: A list of clock output names that CCM provides.
+  The full list of all valid clock names and IDs is below.
+
+	Name			ID
+	---------------------------
+	dummy			0
+	ckil			1
+	ckih			2
+	osc			3
+	pll2_pfd0_352m		4
+	pll2_pfd1_594m		5
+	pll2_pfd2_396m		6
+	pll3_pfd0_720m		7
+	pll3_pfd1_540m		8
+	pll3_pfd2_508m		9
+	pll3_pfd3_454m		10
+	pll2_198m		11
+	pll3_120m		12
+	pll3_80m		13
+	pll3_60m		14
+	twd			15
+	step			16
+	pll1_sw			17
+	periph_pre		18
+	periph2_pre		19
+	periph_clk2_sel		20
+	periph2_clk2_sel	21
+	axi_sel			22
+	esai_sel		23
+	asrc_sel		24
+	spdif_sel		25
+	gpu2d_axi		26
+	gpu3d_axi		27
+	gpu2d_core_sel		28
+	gpu3d_core_sel		29
+	gpu3d_shader_sel	30
+	ipu1_sel		31
+	ipu2_sel		32
+	ldb_di0_sel		33
+	ldb_di1_sel		34
+	ipu1_di0_pre_sel	35
+	ipu1_di1_pre_sel	36
+	ipu2_di0_pre_sel	37
+	ipu2_di1_pre_sel	38
+	ipu1_di0_sel		39
+	ipu1_di1_sel		40
+	ipu2_di0_sel		41
+	ipu2_di1_sel		42
+	hsi_tx_sel		43
+	pcie_axi_sel		44
+	ssi1_sel		45
+	ssi2_sel		46
+	ssi3_sel		47
+	usdhc1_sel		48
+	usdhc2_sel		49
+	usdhc3_sel		50
+	usdhc4_sel		51
+	enfc_sel		52
+	emi_sel			53
+	emi_slow_sel		54
+	vdo_axi_sel		55
+	vpu_axi_sel		56
+	cko1_sel		57
+	periph			58
+	periph2			59
+	periph_clk2		60
+	periph2_clk2		61
+	ipg			62
+	ipg_per			63
+	esai_pred		64
+	esai_podf		65
+	asrc_pred		66
+	asrc_podf		67
+	spdif_pred		68
+	spdif_podf		69
+	can_root		70
+	ecspi_root		71
+	gpu2d_core_podf		72
+	gpu3d_core_podf		73
+	gpu3d_shader		74
+	ipu1_podf		75
+	ipu2_podf		76
+	ldb_di0_podf		77
+	ldb_di1_podf		78
+	ipu1_di0_pre		79
+	ipu1_di1_pre		80
+	ipu2_di0_pre		81
+	ipu2_di1_pre		82
+	hsi_tx_podf		83
+	ssi1_pred		84
+	ssi1_podf		85
+	ssi2_pred		86
+	ssi2_podf		87
+	ssi3_pred		88
+	ssi3_podf		89
+	uart_serial_podf	90
+	usdhc1_podf		91
+	usdhc2_podf		92
+	usdhc3_podf		93
+	usdhc4_podf		94
+	enfc_pred		95
+	enfc_podf		96
+	emi_podf		97
+	emi_slow_podf		98
+	vpu_axi_podf		99
+	cko1_podf		100
+	axi			101
+	mmdc_ch0_axi_podf	102
+	mmdc_ch1_axi_podf	103
+	arm			104
+	ahb			105
+	apbh_dma		106
+	asrc			107
+	can1_ipg		108
+	can1_serial		109
+	can2_ipg		110
+	can2_serial		111
+	ecspi1			112
+	ecspi2			113
+	ecspi3			114
+	ecspi4			115
+	ecspi5			116
+	enet			117
+	esai			118
+	gpt_ipg			119
+	gpt_ipg_per		120
+	gpu2d_core		121
+	gpu3d_core		122
+	hdmi_iahb		123
+	hdmi_isfr		124
+	i2c1			125
+	i2c2			126
+	i2c3			127
+	iim			128
+	enfc			129
+	ipu1			130
+	ipu1_di0		131
+	ipu1_di1		132
+	ipu2			133
+	ipu2_di0		134
+	ldb_di0			135
+	ldb_di1			136
+	ipu2_di1		137
+	hsi_tx			138
+	mlb			139
+	mmdc_ch0_axi		140
+	mmdc_ch1_axi		141
+	ocram			142
+	openvg_axi		143
+	pcie_axi		144
+	pwm1			145
+	pwm2			146
+	pwm3			147
+	pwm4			148
+	per1_bch		149
+	gpmi_bch_apb		150
+	gpmi_bch		151
+	gpmi_io			152
+	gpmi_apb		153
+	sata			154
+	sdma			155
+	spba			156
+	ssi1			157
+	ssi2			158
+	ssi3			159
+	uart_ipg		160
+	uart_serial		161
+	usboh3			162
+	usdhc1			163
+	usdhc2			164
+	usdhc3			165
+	usdhc4			166
+	vdo_axi			167
+	vpu_axi			168
+	cko1			169
+	pll1_sys		170
+	pll2_bus		171
+	pll3_usb_otg		172
+	pll4_audio		173
+	pll5_video		174
+	pll6_mlb		175
+	pll7_usb_host		176
+	pll8_enet		177
+	ssi1_ipg		178
+	ssi2_ipg		179
+	ssi3_ipg		180
+	rom			181
+	usbphy1			182
+	usbphy2			183
+	ldb_di0_div_3_5		184
+	ldb_di1_div_3_5		185
+
+  The ID will be used by clock consumer in the first cell of "clocks"
+  phandle to specify the desired clock.
+
+Examples:
+
+clks: ccm at 020c4000 {
+	compatible = "fsl,imx6q-ccm";
+	reg = <0x020c4000 0x4000>;
+	interrupts = <0 87 0x04 0 88 0x04>;
+	#clock-cells = <1>;
+	clock-output-names = ...
+			     "uart_ipg",
+			     "uart_serial",
+			     ...;
+};
+
+uart1: serial at 02020000 {
+	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+	reg = <0x02020000 0x4000>;
+	interrupts = <0 26 0x04>;
+	clocks = <&clks 160>, <&clks 161>;
+	clock-names = "ipg", "per";
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..cfdbe53 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -111,6 +111,7 @@
 				codec: sgtl5000 at 0a {
 					compatible = "fsl,sgtl5000";
 					reg = <0x0a>;
+					clocks = <&clks 169>;
 					VDDA-supply = <&reg_2p5v>;
 					VDDIO-supply = <&reg_3p3v>;
 				};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 0052fe7..acff2dc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -93,18 +93,23 @@
 		dma-apbh at 00110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 			reg = <0x00110000 0x2000>;
+			clocks = <&clks 106>;
 		};
 
 		gpmi-nand at 00112000 {
-		       compatible = "fsl,imx6q-gpmi-nand";
-		       #address-cells = <1>;
-		       #size-cells = <1>;
-		       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-		       reg-names = "gpmi-nand", "bch";
-		       interrupts = <0 13 0x04>, <0 15 0x04>;
-		       interrupt-names = "gpmi-dma", "bch";
-		       fsl,gpmi-dma-channel = <0>;
-		       status = "disabled";
+			compatible = "fsl,imx6q-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <0 13 0x04>, <0 15 0x04>;
+			interrupt-names = "gpmi-dma", "bch";
+			clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+				 <&clks 150>, <&clks 149>;
+			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+				      "gpmi_bch_apb", "per1_bch";
+			fsl,gpmi-dma-channel = <0>;
+			status = "disabled";
 		};
 
 		timer at 00a00600 {
@@ -146,6 +151,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02008000 0x4000>;
 					interrupts = <0 31 0x04>;
+					clocks = <&clks 112>, <&clks 112>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -155,6 +162,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x0200c000 0x4000>;
 					interrupts = <0 32 0x04>;
+					clocks = <&clks 113>, <&clks 113>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -164,6 +173,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02010000 0x4000>;
 					interrupts = <0 33 0x04>;
+					clocks = <&clks 114>, <&clks 114>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -173,6 +184,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02014000 0x4000>;
 					interrupts = <0 34 0x04>;
+					clocks = <&clks 115>, <&clks 115>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -182,6 +195,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02018000 0x4000>;
 					interrupts = <0 35 0x04>;
+					clocks = <&clks 116>, <&clks 116>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -189,6 +204,8 @@
 					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 					reg = <0x02020000 0x4000>;
 					interrupts = <0 26 0x04>;
+					clocks = <&clks 160>, <&clks 161>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -201,6 +218,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x02028000 0x4000>;
 					interrupts = <0 46 0x04>;
+					clocks = <&clks 178>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <38 37>;
 					status = "disabled";
@@ -210,6 +228,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x0202c000 0x4000>;
 					interrupts = <0 47 0x04>;
+					clocks = <&clks 179>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <42 41>;
 					status = "disabled";
@@ -219,6 +238,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x02030000 0x4000>;
 					interrupts = <0 48 0x04>;
+					clocks = <&clks 180>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <46 45>;
 					status = "disabled";
@@ -358,6 +378,7 @@
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <0 80 0x04>;
+				clocks = <&clks 0>;
 				status = "disabled";
 			};
 
@@ -365,13 +386,203 @@
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <0 81 0x04>;
+				clocks = <&clks 0>;
 				status = "disabled";
 			};
 
-			ccm at 020c4000 {
+			clks: ccm at 020c4000 {
 				compatible = "fsl,imx6q-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <0 87 0x04 0 88 0x04>;
+				#clock-cells = <1>;
+				clock-output-names =
+					"dummy",		/* 0 */
+					"ckil",			/* 1 */
+					"ckih",			/* 2 */
+					"osc",			/* 3 */
+					"pll2_pfd0_352m",	/* 4 */
+					"pll2_pfd1_594m",	/* 5 */
+					"pll2_pfd2_396m",	/* 6 */
+					"pll3_pfd0_720m",	/* 7 */
+					"pll3_pfd1_540m",	/* 8 */
+					"pll3_pfd2_508m",	/* 9 */
+					"pll3_pfd3_454m",	/* 10 */
+					"pll2_198m",		/* 11 */
+					"pll3_120m",		/* 12 */
+					"pll3_80m",		/* 13 */
+					"pll3_60m",		/* 14 */
+					"twd",			/* 15 */
+					"step",			/* 16 */
+					"pll1_sw",		/* 17 */
+					"periph_pre",		/* 18 */
+					"periph2_pre",		/* 19 */
+					"periph_clk2_sel",	/* 20 */
+					"periph2_clk2_sel",	/* 21 */
+					"axi_sel",		/* 22 */
+					"esai_sel",		/* 23 */
+					"asrc_sel",		/* 24 */
+					"spdif_sel",		/* 25 */
+					"gpu2d_axi",		/* 26 */
+					"gpu3d_axi",		/* 27 */
+					"gpu2d_core_sel",	/* 28 */
+					"gpu3d_core_sel",	/* 29 */
+					"gpu3d_shader_sel",	/* 30 */
+					"ipu1_sel",		/* 31 */
+					"ipu2_sel",		/* 32 */
+					"ldb_di0_sel",		/* 33 */
+					"ldb_di1_sel",		/* 34 */
+					"ipu1_di0_pre_sel",	/* 35 */
+					"ipu1_di1_pre_sel",	/* 36 */
+					"ipu2_di0_pre_sel",	/* 37 */
+					"ipu2_di1_pre_sel",	/* 38 */
+					"ipu1_di0_sel",		/* 39 */
+					"ipu1_di1_sel",		/* 40 */
+					"ipu2_di0_sel",		/* 41 */
+					"ipu2_di1_sel",		/* 42 */
+					"hsi_tx_sel",		/* 43 */
+					"pcie_axi_sel",		/* 44 */
+					"ssi1_sel",		/* 45 */
+					"ssi2_sel",		/* 46 */
+					"ssi3_sel",		/* 47 */
+					"usdhc1_sel",		/* 48 */
+					"usdhc2_sel",		/* 49 */
+					"usdhc3_sel",		/* 50 */
+					"usdhc4_sel",		/* 51 */
+					"enfc_sel",		/* 52 */
+					"emi_sel",		/* 53 */
+					"emi_slow_sel",		/* 54 */
+					"vdo_axi_sel",		/* 55 */
+					"vpu_axi_sel",		/* 56 */
+					"cko1_sel",		/* 57 */
+					"periph",		/* 58 */
+					"periph2",		/* 59 */
+					"periph_clk2",		/* 60 */
+					"periph2_clk2",		/* 61 */
+					"ipg",			/* 62 */
+					"ipg_per",		/* 63 */
+					"esai_pred",		/* 64 */
+					"esai_podf",		/* 65 */
+					"asrc_pred",		/* 66 */
+					"asrc_podf",		/* 67 */
+					"spdif_pred",		/* 68 */
+					"spdif_podf",		/* 69 */
+					"can_root",		/* 70 */
+					"ecspi_root",		/* 71 */
+					"gpu2d_core_podf",	/* 72 */
+					"gpu3d_core_podf",	/* 73 */
+					"gpu3d_shader",		/* 74 */
+					"ipu1_podf",		/* 75 */
+					"ipu2_podf",		/* 76 */
+					"ldb_di0_podf",		/* 77 */
+					"ldb_di1_podf",		/* 78 */
+					"ipu1_di0_pre",		/* 79 */
+					"ipu1_di1_pre",		/* 80 */
+					"ipu2_di0_pre",		/* 81 */
+					"ipu2_di1_pre",		/* 82 */
+					"hsi_tx_podf",		/* 83 */
+					"ssi1_pred",		/* 84 */
+					"ssi1_podf",		/* 85 */
+					"ssi2_pred",		/* 86 */
+					"ssi2_podf",		/* 87 */
+					"ssi3_pred",		/* 88 */
+					"ssi3_podf",		/* 89 */
+					"uart_serial_podf",	/* 90 */
+					"usdhc1_podf",		/* 91 */
+					"usdhc2_podf",		/* 92 */
+					"usdhc3_podf",		/* 93 */
+					"usdhc4_podf",		/* 94 */
+					"enfc_pred",		/* 95 */
+					"enfc_podf",		/* 96 */
+					"emi_podf",		/* 97 */
+					"emi_slow_podf",	/* 98 */
+					"vpu_axi_podf",		/* 99 */
+					"cko1_podf",		/* 100 */
+					"axi",			/* 101 */
+					"mmdc_ch0_axi_podf",	/* 102 */
+					"mmdc_ch1_axi_podf",	/* 103 */
+					"arm",			/* 104 */
+					"ahb",			/* 105 */
+					"apbh_dma",		/* 106 */
+					"asrc",			/* 107 */
+					"can1_ipg",		/* 108 */
+					"can1_serial",		/* 109 */
+					"can2_ipg",		/* 110 */
+					"can2_serial",		/* 111 */
+					"ecspi1",		/* 112 */
+					"ecspi2",		/* 113 */
+					"ecspi3",		/* 114 */
+					"ecspi4",		/* 115 */
+					"ecspi5",		/* 116 */
+					"enet",			/* 117 */
+					"esai",			/* 118 */
+					"gpt_ipg",		/* 119 */
+					"gpt_ipg_per",		/* 120 */
+					"gpu2d_core",		/* 121 */
+					"gpu3d_core",		/* 122 */
+					"hdmi_iahb",		/* 123 */
+					"hdmi_isfr",		/* 124 */
+					"i2c1",			/* 125 */
+					"i2c2",			/* 126 */
+					"i2c3",			/* 127 */
+					"iim",			/* 128 */
+					"enfc",			/* 129 */
+					"ipu1",			/* 130 */
+					"ipu1_di0",		/* 131 */
+					"ipu1_di1",		/* 132 */
+					"ipu2",			/* 133 */
+					"ipu2_di0",		/* 134 */
+					"ldb_di0",		/* 135 */
+					"ldb_di1",		/* 136 */
+					"ipu2_di1",		/* 137 */
+					"hsi_tx",		/* 138 */
+					"mlb",			/* 139 */
+					"mmdc_ch0_axi",		/* 140 */
+					"mmdc_ch1_axi",		/* 141 */
+					"ocram",		/* 142 */
+					"openvg_axi",		/* 143 */
+					"pcie_axi",		/* 144 */
+					"pwm1",			/* 145 */
+					"pwm2",			/* 146 */
+					"pwm3",			/* 147 */
+					"pwm4",			/* 148 */
+					"per1_bch",		/* 149 */
+					"gpmi_bch_apb",		/* 150 */
+					"gpmi_bch",		/* 151 */
+					"gpmi_io",		/* 152 */
+					"gpmi_apb",		/* 153 */
+					"sata",			/* 154 */
+					"sdma",			/* 155 */
+					"spba",			/* 156 */
+					"ssi1",			/* 157 */
+					"ssi2",			/* 158 */
+					"ssi3",			/* 159 */
+					"uart_ipg",		/* 160 */
+					"uart_serial",		/* 161 */
+					"usboh3",		/* 162 */
+					"usdhc1",		/* 163 */
+					"usdhc2",		/* 164 */
+					"usdhc3",		/* 165 */
+					"usdhc4",		/* 166 */
+					"vdo_axi",		/* 167 */
+					"vpu_axi",		/* 168 */
+					"cko1",			/* 169 */
+					"pll1_sys",		/* 170 */
+					"pll2_bus",		/* 171 */
+					"pll3_usb_otg",		/* 172 */
+					"pll4_audio",		/* 173 */
+					"pll5_video",		/* 174 */
+					"pll6_mlb",		/* 175 */
+					"pll7_usb_host",	/* 176 */
+					"pll8_enet",		/* 177 */
+					"ssi1_ipg",		/* 178 */
+					"ssi2_ipg",		/* 179 */
+					"ssi3_ipg",		/* 180 */
+					"rom",			/* 181 */
+					"usbphy1",		/* 182 */
+					"usbphy2",		/* 183 */
+					"ldb_di0_div_3_5",	/* 184 */
+					"ldb_di1_div_3_5",	/* 185 */
+					"end_of_list";
 			};
 
 			anatop at 020c8000 {
@@ -468,12 +679,14 @@
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 0x04>;
+				clocks = <&clks 182>;
 			};
 
 			usbphy2: usbphy at 020ca000 {
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 0x04>;
+				clocks = <&clks 183>;
 			};
 
 			snvs at 020cc000 {
@@ -608,6 +821,9 @@
 				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <0 2 0x04>;
+				clocks = <&clks 155>, <&clks 155>;
+				clock-names = "ipg", "ahb";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
 			};
 		};
 
@@ -631,6 +847,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 0x04>;
+				clocks = <&clks 162>;
 				fsl,usbphy = <&usbphy1>;
 				status = "disabled";
 			};
@@ -639,6 +856,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184200 0x200>;
 				interrupts = <0 40 0x04>;
+				clocks = <&clks 162>;
 				fsl,usbphy = <&usbphy2>;
 				status = "disabled";
 			};
@@ -647,6 +865,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184400 0x200>;
 				interrupts = <0 41 0x04>;
+				clocks = <&clks 162>;
 				status = "disabled";
 			};
 
@@ -654,6 +873,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184600 0x200>;
 				interrupts = <0 42 0x04>;
+				clocks = <&clks 162>;
 				status = "disabled";
 			};
 
@@ -661,6 +881,8 @@
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
 				interrupts = <0 118 0x04 0 119 0x04>;
+				clocks = <&clks 117>, <&clks 117>;
+				clock-names = "ipg", "ahb";
 				status = "disabled";
 			};
 
@@ -673,6 +895,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <0 22 0x04>;
+				clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -680,6 +904,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <0 23 0x04>;
+				clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -687,6 +913,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <0 24 0x04>;
+				clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -694,6 +922,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x0219c000 0x4000>;
 				interrupts = <0 25 0x04>;
+				clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -703,6 +933,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a0000 0x4000>;
 				interrupts = <0 36 0x04>;
+				clocks = <&clks 125>;
 				status = "disabled";
 			};
 
@@ -712,6 +943,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a4000 0x4000>;
 				interrupts = <0 37 0x04>;
+				clocks = <&clks 126>;
 				status = "disabled";
 			};
 
@@ -721,6 +953,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a8000 0x4000>;
 				interrupts = <0 38 0x04>;
+				clocks = <&clks 127>;
 				status = "disabled";
 			};
 
@@ -784,6 +1017,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021e8000 0x4000>;
 				interrupts = <0 27 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -791,6 +1026,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021ec000 0x4000>;
 				interrupts = <0 28 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -798,6 +1035,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f0000 0x4000>;
 				interrupts = <0 29 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -805,6 +1044,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f4000 0x4000>;
 				interrupts = <0 30 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8e46407..433c683 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -387,48 +387,11 @@ int __init mx6q_clocks_init(void)
 			pr_err("i.MX6q clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
 
+	of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
+
 	clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
 	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
 	clk_register_clkdev(clk[twd], NULL, "smp_twd");
-	clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
-	clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
-	clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
-	clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
-	clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
-	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
-	clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
-	clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
-	clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
-	clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
-	clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
-	clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
-	clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
-	clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
-	clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
-	clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
-	clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
-	clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
-	clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
-	clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
-	clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
-	clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
-	clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
 	clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
 	clk_register_clkdev(clk[ahb], "ahb", NULL);
 	clk_register_clkdev(clk[cko1], "cko1", NULL);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 6f9c23b..957f5fe 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -94,7 +94,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
 	clk_set_parent(cko1_sel, ahb);
 	rate = clk_round_rate(cko1, 16000000);
 	clk_set_rate(cko1, rate);
-	clk_register_clkdev(cko1, NULL, "0-000a");
 put_clk:
 	if (!IS_ERR(cko1_sel))
 		clk_put(cko1_sel);
-- 
1.7.5.4



From arnd at arndb.de  Thu Aug 16 04:09:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 08:09:21 +0000
Subject: [PATCH V3 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <CADApbej91_Y84sC9R1b0+LgDTzFUH8CveYsDi4wDWOQxkGnnFg@mail.gmail.com>
References: <1345086525-12328-1-git-send-email-xiechao.mail@gmail.com>
 <201208160717.03707.arnd@arndb.de>
 <CADApbej91_Y84sC9R1b0+LgDTzFUH8CveYsDi4wDWOQxkGnnFg@mail.gmail.com>
Message-ID: <201208160809.21662.arnd@arndb.de>

On Thursday 16 August 2012, Chao Xie wrote:
> >> +     clocks[uart0_mux] =
> >> +         clk_register_mux(NULL, "uart0_mux", uart_parent,
> >> +                          ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
> >> +                          apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);


> i can change remove the clocks array, but even make the sentence
> shorter, most of them still can not fit in one line.

Don't worry too much about the line length or a particular style. This is
all about readability, and the style you use above may conform to some
written style guide, but it's not the most readable one. If you reformat
it to 

	clk = clk_register_mux(NULL, "uart0_mux", uart_parent, ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);

or

	clk = clk_register_mux(NULL, "uart0_mux", uart_parent, ARRAY_SIZE(uart_parent),
		CLK_SET_RATE_PARENT, apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);

or

	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
		 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
		 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);

I still find that more readable.

	Arnd


From arnd at arndb.de  Thu Aug 16 04:10:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 08:10:40 +0000
Subject: [GIT PULL][for 3.6] pull request from fixes branch in pxa git tree
In-Reply-To: <CAN1soZw8UC-R0hq4CgsGG20-42z0jYUvbTygF18rn+hhmtJivQ@mail.gmail.com>
References: <CAN1soZw8UC-R0hq4CgsGG20-42z0jYUvbTygF18rn+hhmtJivQ@mail.gmail.com>
Message-ID: <201208160810.40859.arnd@arndb.de>

On Thursday 16 August 2012, Haojian Zhuang wrote:
> Hi Olof & Arnd,
> 
> Please help to pull fixes branch from pxa git tree.

Pulled, thanks!

	Arnd


From dave.martin at linaro.org  Thu Aug 16 04:27:26 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 16 Aug 2012 09:27:26 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
References: <20120813160008.GA30302@n2100.arm.linux.org.uk>
 <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
Message-ID: <20120816082726.GA2101@linaro.org>

On Wed, Aug 15, 2012 at 03:08:29PM -0700, Martin Rosenberg wrote:
> 
> 
> ----- Original Message -----
> From: "Russell King - ARM Linux" <linux at arm.linux.org.uk>
> To: "Jonathan Austin" <jonathan.austin at arm.com>
> Cc: "Martin Rosenberg" <mrosenberg at mozilla.com>, "Will Deacon" <will.deacon at arm.com>, linux-arm-kernel at lists.infradead.org
> Sent: Monday, August 13, 2012 9:00:08 AM
> Subject: Re: Discontiguous memory and cacheflush
> 
> 
> > It's intention is to support self-modifying userspace code only and also
> > intended to be used over a _short_ range of addresses only - it works by
> > flushing each _individual_ cache line over the range of addreses
> > requested.
> Documenting the current behavior would mostly be acceptable, but it is rather confusing (and took quite some time to track down)
> 
> > If it's going to be used for significantly larger areas, then we need to
> > think about imposing a limit, upon which we just flush the entire cache
> > and be done with it.
> 
> I found that there was still a net win making fewer syscalls, even with the overhead of flushing extra cache lines.
> In the cases where the range is discontiguous, I usually need to do something silly, like flush 20 individual instructions that are scattered throughout several hundred MB of memory.  I think the fastest method for flushing in this case would be to shave a different call, with a different api, where userspace can provide an array of addresses that need to be flushed, but that sounds like material for a new thread.  Thanks --Marty

Could we use the currently must-be-zero flags parameter to add new
functionality to this syscall, or are there legacy uses of that
parameter (or history of userspace not bothering to zero it?)

For example, we could have something like

do_cache_op(struct iovec *iov, int iovcnt, CF_IOVEC)

to flush a discontiguous set of ranges described by an iovec (though we
can of course also describe the ranges in other ways)

Cheers
---Dave


From tony at atomide.com  Thu Aug 16 04:39:24 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 16 Aug 2012 01:39:24 -0700
Subject: [PATCH v2 04/14] ARM: OMAP5: Add minimal support for OMAP5430 SOC
In-Reply-To: <alpine.DEB.2.00.1208151618590.1731@utopia.booyaka.com>
References: <1341566515-22665-1-git-send-email-santosh.shilimkar@ti.com>
 <1341566515-22665-5-git-send-email-santosh.shilimkar@ti.com>
 <4FFA9B61.8030808@ti.com> <20120709131156.GH1122@atomide.com>
 <alpine.DEB.2.00.1208151618590.1731@utopia.booyaka.com>
Message-ID: <20120816083923.GK11011@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120815 15:27]:
> Hi
> 
> On Mon, 9 Jul 2012, Tony Lindgren wrote:
> 
> > Below (untested) is what could be done in the short term.
> 
> That's fine with me.  Do you want to queue it or do you want me to queue 
> it?

Probably best for you to take it along with other related patches.
 
> > Heh these CK_XXXX defines are now running out of the u16 cpu_mask.
> > 
> > They really should be replaced with SoC specific lists of clocks
> > rather than bloating the cpu_mask and repeating it for every clock
> > that's compiled in for 800+ times.
> 
> Frankly, an extra 1.6KB -- uncompressed -- is pretty low on my list of 
> bloat concerns for multi-OMAP kernels.  If it were up to me, I'd just 
> change it to a u32 and be done with the problem for the foreseeable 
> future.

And then we're wasting that 1.6KB..
 
> > I wonder if we could #define CK_OMAP_DUMMY 0 that's always set
> > for non-shared clocks if they only get set in some *_data.c
> > file in a unique way?
> > 
> > Paul got any better ideas?
> 
> Aside from using u32?  Not really.  As we've discussed in the past, at 
> some point we should convert the clock initialization to using some kind 
> of per-SoC list.  But it doesn't seem worth spending too much time on that 
> while the common clock framework conversion is higher priority.

Right, let's do the ifdef else thing then.

Regards,

Tony


From catalin.marinas at arm.com  Thu Aug 16 04:41:36 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 Aug 2012 09:41:36 +0100
Subject: imx6q restart is broken
In-Reply-To: <20120815214412.GC32560@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk> <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
Message-ID: <CAHkRjk4nCVAC=hAGqGX7y0Uo+LT9ObBj7H8z4KbZJbQOAA76RQ@mail.gmail.com>

On 15 August 2012 22:44, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Wed, Aug 15, 2012 at 10:07:47AM -0500, Rob Herring wrote:
>> I think I am seeing a similar problem on highbank with a v7 only build.
>>
>> >From what I've debugged, restart hangs for me on the L2x0 spinlock
>> during a writel. Changing the writel to writel_relaxed in the restart
>> hook fixes the problem. This skips barriers in the writel and for the
>> spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
>> should not be doing a dmb in my case on a v7 only build.
>
> Well, I had the idea of only doing a dmb() once every N loops, but I don't
> think we can sensibly introduce such a change into the mainline kernel.
> (How would cpu_relax() know it's being used in a loop?)

It doesn't really need to know. We can say that every X calls to
cpu_relax() should result in a dmb and we can make the counter
per-cpu. This would ensure the write-buffer draining which was the aim
of this dmb.

-- 
Catalin


From haojian.zhuang at gmail.com  Thu Aug 16 04:44:15 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 16 Aug 2012 16:44:15 +0800
Subject: [GIT PULL][for 3.7] pull request from dt branch in pxa git tree
Message-ID: <CAN1soZwJMbr-9T-7qhh_qfmfjJ+WmTstkhFmZ=yewoJxs+MGqA@mail.gmail.com>

Hi Olof & Arnd,

Please help to merge these patches from dt branch in pxa git tree.

It's the V4 version. The changes are in below.

v4:
1. remove pinctrl patches for pxa.

v3:
1. Revert d03c1990c9681047bf94caa497c41172b3f28351 GPIO: gpio-pxa: fix
devicetree functions
since it's merged into Linus' gpio tree.

v2:
1. Add Linus's Ack in pinctrl driver.
2. Add chao's & haojian's patches for Tauros2 cache.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git dt

for you to fetch changes up to 51931b37fcb17a2f48f726fd21b88e3af770ddc2:

  ARM: mmp: enable tauros2 cache in mmp2 dt (2012-08-16 16:17:10 +0800)

----------------------------------------------------------------
Chao Xie (7):
      ARM: pxa: support CKENC in clk_enable
      gpio: pxa: add chain_eneter and chain_exit for irq handler
      ARM: cache: fix uninitialized ptr in tauros2_init
      ARM: cache: add cputype.h for tauros2
      ARM: cache: add extra feature enable for tauros2
      ARM: mmp&dove: modify tauros2_init call
      ARM: cache: add dt support for tauros2 cache

Daniel Mack (7):
      RTC: add DT bindings to pxa-rtc
      MTD: pxa3xx-nand: add devicetree bindings
      GPIO: gpio-pxa: simplify pxa_gpio_to_irq() and pxa_irq_to_chip()
      ARM: pxa: add devicetree code for irq handling
      ARM: pxa3xx: skip default device initialization when booting via DT
      ARM: pxa3xx: add generic DT machine code
      ARM: pxa: add .dtsi files

Haojian Zhuang (2):
      ARM: mmp: enable tauros2 cache in pxa910
      ARM: mmp: enable tauros2 cache in mmp2 dt

 .../devicetree/bindings/arm/mrvl/tauros2.txt       |   17 +++
 .../devicetree/bindings/mtd/pxa3xx-nand.txt        |   31 +++++
 Documentation/devicetree/bindings/rtc/pxa-rtc.txt  |   14 +++
 arch/arm/boot/dts/mmp2.dtsi                        |    5 +
 arch/arm/boot/dts/pxa27x.dtsi                      |   14 +++
 arch/arm/boot/dts/pxa2xx.dtsi                      |  132 ++++++++++++++++++++
 arch/arm/boot/dts/pxa3xx.dtsi                      |   32 +++++
 arch/arm/boot/dts/pxa910.dtsi                      |    5 +
 arch/arm/include/asm/hardware/cache-tauros2.h      |    5 +-
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-mmp/mmp2.c                           |    2 +-
 arch/arm/mach-mmp/pxa910.c                         |    4 +
 arch/arm/mach-pxa/Kconfig                          |   12 ++
 arch/arm/mach-pxa/Makefile                         |    3 +
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    8 +-
 arch/arm/mach-pxa/irq.c                            |  131 +++++++++++++++----
 arch/arm/mach-pxa/pxa-dt.c                         |   63 ++++++++++
 arch/arm/mach-pxa/pxa3xx.c                         |   21 +++-
 arch/arm/mm/cache-tauros2.c                        |   83 ++++++++----
 drivers/gpio/gpio-pxa.c                            |   77 ++++--------
 drivers/mtd/nand/pxa3xx_nand.c                     |   85 ++++++++++---
 drivers/rtc/rtc-pxa.c                              |   11 ++
 22 files changed, 639 insertions(+), 118 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/pxa-rtc.txt
 create mode 100644 arch/arm/boot/dts/pxa27x.dtsi
 create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi
 create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi
 create mode 100644 arch/arm/mach-pxa/pxa-dt.c


From stigge at antcom.de  Thu Aug 16 04:46:48 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 10:46:48 +0200
Subject: [PATCH 1/2] mtd: lpc32xx_slc: Adjust to pl08x DMA interface
 changes
In-Reply-To: <1345027069.3393.124.camel@sauron.fi.intel.com>
References: <1342095778-13403-1-git-send-email-stigge@antcom.de>
 <1342095778-13403-2-git-send-email-stigge@antcom.de>
 <1345027069.3393.124.camel@sauron.fi.intel.com>
Message-ID: <502CB378.1020708@antcom.de>

Hi,

On 08/15/2012 12:37 PM, Artem Bityutskiy wrote:
> On Thu, 2012-07-12 at 14:22 +0200, Roland Stigge wrote:
>> This patch adjusts the LPC32xx SLC NAND driver to the new pl08x
>> DMA interface, fixing the compile error resulting from changed
>> pl08x structures.
>> 
>> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> This patch breaks compilation:
> 
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko]
> undefined!
> 
> Please, send a fix. The defconfig I used is attached.

Thanks for the note. The issue happens on compiling lpc32xx_slc and
lpc32xx_mlc as a module. Caused by pl08x_filter_id not being exported.
Looking at other dma drivers, they have an EXPORT_SYMBOL() for this,
see also

drivers/dma/coh901318.c
drivers/dma/sirf-dma.c

Will post a respective adjustment for drivers/dma/amba-pl08x.c separately.

Roland


From stigge at antcom.de  Thu Aug 16 04:56:36 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 10:56:36 +0200
Subject: [PATCH] dma: amba-pl08x: Export pl08x_filter_id
Message-ID: <1345107396-27079-1-git-send-email-stigge@antcom.de>

This patch fixes the following when compiling a driver module that uses
amba-pl08x:

ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!
ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_mlc.ko] undefined!

(drivers/mtd/nand/lpc32xx_* are still in l2-mtd.git)

Done as in:

drivers/dma/coh901318.c
drivers/dma/sirf-dma.c

Signed-off-by: Roland Stigge <stigge at antcom.de>

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 6fbeebb..8c2e9b6 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1608,6 +1608,7 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 
 	return false;
 }
+EXPORT_SYMBOL(pl08x_filter_id);
 
 /*
  * Just check that the device is there and active


From arnd at arndb.de  Thu Aug 16 04:59:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 08:59:49 +0000
Subject: [PATCH] dma: amba-pl08x: Export pl08x_filter_id
In-Reply-To: <1345107396-27079-1-git-send-email-stigge@antcom.de>
References: <1345107396-27079-1-git-send-email-stigge@antcom.de>
Message-ID: <201208160859.49317.arnd@arndb.de>

On Thursday 16 August 2012, Roland Stigge wrote:
> This patch fixes the following when compiling a driver module that uses
> amba-pl08x:
> 
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_mlc.ko] undefined!
> 
> (drivers/mtd/nand/lpc32xx_* are still in l2-mtd.git)
> 
> Done as in:
> 
> drivers/dma/coh901318.c
> drivers/dma/sirf-dma.c
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From linux at arm.linux.org.uk  Thu Aug 16 05:00:41 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 Aug 2012 10:00:41 +0100
Subject: [PATCH] dma: amba-pl08x: Export pl08x_filter_id
In-Reply-To: <1345107396-27079-1-git-send-email-stigge@antcom.de>
References: <1345107396-27079-1-git-send-email-stigge@antcom.de>
Message-ID: <20120816090041.GK18957@n2100.arm.linux.org.uk>

On Thu, Aug 16, 2012 at 10:56:36AM +0200, Roland Stigge wrote:
> This patch fixes the following when compiling a driver module that uses
> amba-pl08x:
> 
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_mlc.ko] undefined!
> 
> (drivers/mtd/nand/lpc32xx_* are still in l2-mtd.git)

It is currently intended that this be passed from platform code into
drivers via platform data, so that drivers can decide which DMA engine
they wish to make use of.

See how all the AMBA drivers work in this regard (because they need to
support more than just a single DMA engine implementation.)


From arnd at arndb.de  Thu Aug 16 05:03:29 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 09:03:29 +0000
Subject: [GIT PULL][for 3.7] pull request from dt branch in pxa git tree
In-Reply-To: <CAN1soZwJMbr-9T-7qhh_qfmfjJ+WmTstkhFmZ=yewoJxs+MGqA@mail.gmail.com>
References: <CAN1soZwJMbr-9T-7qhh_qfmfjJ+WmTstkhFmZ=yewoJxs+MGqA@mail.gmail.com>
Message-ID: <201208160903.29386.arnd@arndb.de>

On Thursday 16 August 2012, Haojian Zhuang wrote:
> The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:
> 
>   Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/hzhuang1/linux.git dt

Pulled into next/dt, thanks!

	Arnd


From arnd at arndb.de  Thu Aug 16 05:06:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 09:06:21 +0000
Subject: [PATCH] dma: amba-pl08x: Export pl08x_filter_id
In-Reply-To: <20120816090041.GK18957@n2100.arm.linux.org.uk>
References: <1345107396-27079-1-git-send-email-stigge@antcom.de>
 <20120816090041.GK18957@n2100.arm.linux.org.uk>
Message-ID: <201208160906.21950.arnd@arndb.de>

On Thursday 16 August 2012, Russell King - ARM Linux wrote:
> On Thu, Aug 16, 2012 at 10:56:36AM +0200, Roland Stigge wrote:
> > This patch fixes the following when compiling a driver module that uses
> > amba-pl08x:
> > 
> > ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!
> > ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_mlc.ko] undefined!
> > 
> > (drivers/mtd/nand/lpc32xx_* are still in l2-mtd.git)
> 
> It is currently intended that this be passed from platform code into
> drivers via platform data, so that drivers can decide which DMA engine
> they wish to make use of.
> 
> See how all the AMBA drivers work in this regard (because they need to
> support more than just a single DMA engine implementation.)

Ah, you're right, I forgot about that. I'll take back my Ack then.

	Arnd


From linux at arm.linux.org.uk  Thu Aug 16 05:19:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 Aug 2012 10:19:53 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <20120816082726.GA2101@linaro.org>
References: <20120813160008.GA30302@n2100.arm.linux.org.uk>
 <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
 <20120816082726.GA2101@linaro.org>
Message-ID: <20120816091953.GL18957@n2100.arm.linux.org.uk>

On Thu, Aug 16, 2012 at 09:27:26AM +0100, Dave Martin wrote:
> Could we use the currently must-be-zero flags parameter to add new
> functionality to this syscall, or are there legacy uses of that
> parameter (or history of userspace not bothering to zero it?)
> 
> For example, we could have something like
> 
> do_cache_op(struct iovec *iov, int iovcnt, CF_IOVEC)
> 
> to flush a discontiguous set of ranges described by an iovec (though we
> can of course also describe the ranges in other ways)

Why overload an existing syscall with multiple different argument types
rather than having a new syscall with a sane API?


From josephl at nvidia.com  Thu Aug 16 05:30:11 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:30:11 +0800
Subject: [PATCH V2 0/6] ARM: tegra: add CPU hotplug support
In-Reply-To: <502BC8BE.8060800@wwwdotorg.org>
References: <1345022554-26292-1-git-send-email-josephl@nvidia.com>
 <502BC8BE.8060800@wwwdotorg.org>
Message-ID: <1345109411.29113.76.camel@jlo-ubuntu-64.nvidia.com>

Hi Stephen,

On Thu, 2012-08-16 at 00:05 +0800, Stephen Warren wrote:
> On 08/15/2012 03:22 AM, Joseph Lo wrote:
> > This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
> > 
> > The first 3 patches make the CPU clock and reset control be a module and
> > the abstraction APIs for TegraXX SoCs. And clean up some codes for later
> > usage. Then add CPU hotplug support for Tegra20 and Tegra30.
> > 
> > Verified on Seaboard(Tegra20) and Cardhu(Tegra30)
> > 
> > V2:
> > * add one more patch for enable HOTPLUG_CPU [6/6]
> 
> The build problem when HOTPLUG_CPU is disabled is still present. The
> kernel needs to build with this option disabled.
> 
> Enabling HOTPLUG_CPU in defconfig doesn't force everyone to enable that
> configuration option; not everyone uses tegra_defconfig, people don't
> always update to the latest defconfig, people should be free to disable
> functionality they don't need and still get a buildable & working
> kernel, etc.
> 
Obviously, I didn't get your problem at your first reply. Sorry.

I fixed that and re-checked it again with Tegra20-only, Tegra30-only and
both supported kernel. And checked with "git bisect" as well. It should
be OK now.

Thanks,
Joseph

> Besides, even if defconfig were a legitimate solution to this problem,
> this series still wouldn't work with "git bisect", since the defconfig
> patch comes after the patch that causes the build failure.
> 





From josephl at nvidia.com  Thu Aug 16 05:31:47 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:47 +0800
Subject: [PATCH V3 0/6] ARM: tegra: add CPU hotplug support
Message-ID: <1345109513-21553-1-git-send-email-josephl@nvidia.com>

This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.

The first 3 patches make the CPU clock and reset control be a module and
the abstraction APIs for TegraXX SoCs. And clean up some codes for later
usage. Then add CPU hotplug support for Tegra20 and Tegra30.

Verified on Seaboard(Tegra20) and Cardhu(Tegra30)

V3:
* fix the build error when HOTPLUG_CPU disabled [4/6] [5/6]
V2:
* add one more patch for enable HOTPLUG_CPU [6/6]
* move all the SoC specific CPU shutdown code into platform_cpu_die [4/6]

Joseph Lo (6):
  ARM: tegra: introduce tegra_cpu_car_ops structures
  ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops
  ARM: tegra: clean up the common assembly macros into sleep.h
  ARM: tegra30: add CPU hotplug support
  ARM: tegra20: add CPU hotplug support
  ARM: tegra: defconfig: enable HOTPLUG_CPU

 arch/arm/configs/tegra_defconfig          |    1 +
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/common.c              |    3 +
 arch/arm/mach-tegra/headsmp.S             |    6 +-
 arch/arm/mach-tegra/hotplug.c             |  118 ++++++++---------------------
 arch/arm/mach-tegra/platsmp.c             |   29 +------
 arch/arm/mach-tegra/sleep-t20.S           |   82 ++++++++++++++++++++
 arch/arm/mach-tegra/sleep-t30.S           |  107 ++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.S               |   33 +--------
 arch/arm/mach-tegra/sleep.h               |   85 +++++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 +++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++
 16 files changed, 557 insertions(+), 147 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S
 create mode 100644 arch/arm/mach-tegra/sleep.h
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h



From josephl at nvidia.com  Thu Aug 16 05:31:48 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:48 +0800
Subject: [PATCH V3 1/6] ARM: tegra: introduce tegra_cpu_car_ops structures
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-2-git-send-email-josephl@nvidia.com>

The tegra_cpu_car_ops provide the interface for CPU to control
it's clock gating and reset status. The other drivers should use
this for CPU control. And should not directly access CAR registers
to control CPU.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* no change
V2:
* no change

 arch/arm/mach-tegra/clock.c               |    4 +
 arch/arm/mach-tegra/tegra20_clocks.c      |   70 +++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks_data.c |    2 +
 arch/arm/mach-tegra/tegra30_clocks.c      |   72 ++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra30_clocks_data.c |    3 +
 arch/arm/mach-tegra/tegra_cpu_car.h       |   87 +++++++++++++++++++++++++++++
 6 files changed, 238 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra_cpu_car.h

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 632133f..fd82085 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -31,6 +31,10 @@
 
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 
 /*
  * Locking:
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index b9124af..ee6922b 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -33,6 +33,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
 
 #define RST_DEVICES			0x004
 #define RST_DEVICES_SET			0x300
@@ -152,6 +153,14 @@
 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT	16
 #define PMC_BLINK_TIMER_DATA_OFF_MASK	0xffff
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 
@@ -1534,3 +1543,64 @@ struct clk_ops tegra_cdev_clk_ops = {
 	.disable = tegra20_cdev_clk_disable,
 	.recalc_rate = tegra20_cdev_recalc_rate,
 };
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg & ~CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	barrier();
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+	.wait_for_reset	= tegra20_wait_cpu_in_reset,
+	.put_in_reset	= tegra20_put_cpu_in_reset,
+	.out_of_reset	= tegra20_cpu_out_of_reset,
+	.enable_clock	= tegra20_enable_cpu_clock,
+	.disable_clock	= tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 6516beb..b9cb82b 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "tegra2_emc.h"
 #include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
 
 /* Clock definitions */
 
@@ -1106,4 +1107,5 @@ void __init tegra2_init_clocks(void)
 	}
 
 	init_audio_sync_clock_mux();
+	tegra20_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 3129c2f..7dad44d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -35,6 +35,7 @@
 
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY		100
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR	0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
+#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
+#define CPU_RESET(cpu)	(0x1111ul << (cpu))
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -2221,3 +2232,64 @@ struct clk_ops tegra_cml_clk_ops = {
 struct clk_ops tegra_pciex_clk_ops = {
 	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
+
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(reg_clk_base +
+			    TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
+
+	return;
+}
+
+static void tegra30_put_cpu_in_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+	dmb();
+}
+
+static void tegra30_cpu_out_of_reset(u32 cpu)
+{
+	writel(CPU_RESET(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+	wmb();
+}
+
+static void tegra30_enable_cpu_clock(u32 cpu)
+{
+	unsigned int reg;
+
+	writel(CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	reg = readl(reg_clk_base +
+		    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
+
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
+
+	unsigned int reg;
+
+	reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg | CPU_CLOCK(cpu),
+	       reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+	.wait_for_reset	= tegra30_wait_cpu_in_reset,
+	.put_in_reset	= tegra30_put_cpu_in_reset,
+	.out_of_reset	= tegra30_cpu_out_of_reset,
+	.enable_clock	= tegra30_enable_cpu_clock,
+	.disable_clock	= tegra30_disable_cpu_clock,
+};
+
+void __init tegra30_cpu_car_ops_init(void)
+{
+	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 643a6cc..3d2e553 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -32,6 +32,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
 
 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,		\
 		   _parent_names, _parents, _parent)		\
@@ -1372,4 +1373,6 @@ void __init tegra30_init_clocks(void)
 
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
 		tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+	tegra30_cpu_car_ops_init();
 }
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 0000000..30d063a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *	keep waiting until the CPU in reset state
+ * put_in_reset:
+ *	put the CPU in reset state
+ * out_of_reset:
+ *	release the CPU from reset state
+ * enable_clock:
+ *	CPU clock un-gate
+ * disable_clock:
+ *	CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+	void (*wait_for_reset)(u32 cpu);
+	void (*put_in_reset)(u32 cpu);
+	void (*out_of_reset)(u32 cpu);
+	void (*enable_clock)(u32 cpu);
+	void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+		return;
+
+	tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+		return;
+
+	tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+		return;
+
+	tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+		return;
+
+	tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+	if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+		return;
+
+	tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
-- 
1.7.0.4



From josephl at nvidia.com  Thu Aug 16 05:31:49 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:49 +0800
Subject: [PATCH V3 2/6] ARM: tegra: replace the CPU CAR access code by
 tegra_cpu_car_ops
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-3-git-send-email-josephl@nvidia.com>

Replacing the code that directly access to CAR registers with
tegra_cpu_car_ops. This ops hides CPU CAR access inside and
provides control interface for it.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* no change
V2:
* no change

 arch/arm/mach-tegra/platsmp.c |   29 +++++------------------------
 1 files changed, 5 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208db..96ed171 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
 
 extern void tegra_secondary_startup(void);
 
@@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
 	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu)	(0x1<<(8+cpu))
-#define CPU_RESET(cpu)	(0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
-
 	/* Enable the CPU clock. */
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-	barrier();
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	tegra_enable_cpu_clock(cpu);
 
 	/* Clear flow controller CSR. */
 	flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-	u32 reg;
 	int ret, pwrgateid;
 	unsigned long timeout;
 
@@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
 	}
 
 	/* CPU partition is powered. Enable the CPU clock. */
-	writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+	tegra_enable_cpu_clock(cpu);
 	udelay(10);
 
 	/* Remove I/O clamps. */
@@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * via the flow controller). This will have no effect on first boot
 	 * of the CPU since it should already be in reset.
 	 */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-	dmb();
+	tegra_put_cpu_in_reset(cpu);
 
 	/*
 	 * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		goto done;
 
 	/* Take the CPU out of reset. */
-	writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-	wmb();
+	tegra_cpu_out_of_reset(cpu);
 done:
 	return status;
 }
-- 
1.7.0.4



From josephl at nvidia.com  Thu Aug 16 05:31:50 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:50 +0800
Subject: [PATCH V3 3/6] ARM: tegra: clean up the common assembly macros into
 sleep.h
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-4-git-send-email-josephl@nvidia.com>

There are some common macros for Tegra low-level assembly code. Clean
up them into one header file and move the definitions that will be
re-used into it as well.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* no change
V2:
* no change

 arch/arm/mach-tegra/headsmp.S |    6 +---
 arch/arm/mach-tegra/sleep.S   |   33 +-----------------------
 arch/arm/mach-tegra/sleep.h   |   56 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 37 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep.h

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c..6addc78 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 
 #define APB_MISC_GP_HIDREV	0x804
 #define PMC_SCRATCH41	0x140
 
 #define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
 
-	.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-	.endm
-
         .section ".text.head", "ax"
 	__CPUINIT
 
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156..ea81554 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
+#include "sleep.h"
 
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-					+ IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x14
-	moveq	\rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-	cmp	\rcpu, #0
-	subne	\rd, \rcpu, #1
-	movne	\rd, \rd, lsl #3
-	addne	\rd, \rd, #0x18
-	moveq	\rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-	mrc	p15, 0, \rd, c0, c0, 5
-	and	\rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-	movw	\reg, #:lower16:\val
-	movt	\reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 0000000..d0c7a8b
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x14
+	moveq	\rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x18
+	moveq	\rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+	mrc	p15, 0, \rd, c0, c0, 5
+	and	\rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+	movw	\reg, #:lower16:\val
+	movt	\reg, #:upper16:\val
+.endm
+#endif
+#endif
-- 
1.7.0.4



From josephl at nvidia.com  Thu Aug 16 05:31:51 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:51 +0800
Subject: [PATCH V3 4/6] ARM: tegra30: add CPU hotplug support
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-5-git-send-email-josephl@nvidia.com>

Hotplug function put CPUs in offline or online state at runtime.
When the CPU been put in the offline state, it was been clock and
power gated. Except primary CPU other CPUs can be hotplugged.

Based on the work by:
Scott Williams <scwilliams at nvidia.com>
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* fix the compiling error when HOTPLUG_CPU disabled
V2:
* move the SoC specific CPU shutdown code into platform_cpu_die

 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    2 +
 arch/arm/mach-tegra/hotplug.c   |  110 +++++++++------------------------------
 arch/arm/mach-tegra/sleep-t30.S |  107 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |   25 +++++++++
 5 files changed, 159 insertions(+), 86 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t30.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 060592a..211e279 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f3654f8..0652056 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -147,6 +148,7 @@ void __init tegra30_init_early(void)
 	tegra_init_cache(0x441, 0x551);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra30_hotplug_init();
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9dd..be92d4c 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,91 +1,23 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
 
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
+#include "sleep.h"
+#include "tegra_cpu_car.h"
 
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
-
-		/*if (pen_release == cpu) {*/
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		/*}*/
-
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
+static void (*tegra_hotplug_shutdown)(void);
 
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -99,22 +31,20 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-	int spurious = 0;
+	cpu = cpu_logical_map(cpu);
 
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
+	/* Flush the L1 data cache. */
+	flush_cache_all();
 
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
+	/* Shut down the current CPU. */
+	tegra_hotplug_shutdown();
+
+	/* Clock gate the CPU */
+	tegra_wait_cpu_in_reset(cpu);
+	tegra_disable_cpu_clock(cpu);
 
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+	/* Should never return here. */
+	BUG();
 }
 
 int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,11 @@ int platform_cpu_disable(unsigned int cpu)
 	 */
 	return cpu == 0 ? -EPERM : 0;
 }
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 0000000..777d9ce
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Powergate this CPU */
+	mov	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	bl	tegra30_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+	cpu_id	r3
+	cmp	r3, #0
+	moveq	pc, lr		@ Must never be called for CPU 0
+
+	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
+	cpu_to_csr_reg r1, r3
+	add	r1, r1, r12	@ virtual CSR address for this CPU
+	cpu_to_halt_reg r2, r3
+	add	r2, r2, r12	@ virtual HALT_EVENTS address for this CPU
+
+	/*
+	 * Clear this CPU's "event" and "interrupt" flags and power gate
+	 * it when halting but not before it is in the "WFE" state.
+	 */
+	movw	r12, \
+		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+		FLOW_CTRL_CSR_ENABLE
+	mov	r4, #(1 << 4)
+	orr	r12, r12, r4, lsl r3
+	str	r12, [r1]
+
+	/* Halt this CPU. */
+	mov	r3, #0x400
+delay_1:
+	subs	r3, r3, #1			@ delay as a part of wfe war.
+	bge	delay_1;
+	cpsid	a				@ disable imprecise aborts.
+	ldr	r3, [r1]			@ read CSR
+	str	r3, [r1]			@ clear CSR
+	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+	movne	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
+	str	r3, [r2]
+	ldr	r0, [r2]
+	b	wfe_war
+
+__cpu_reset_again:
+	dsb
+	.align 5
+	wfe					@ CPU should be power gated here
+wfe_war:
+	b	__cpu_reset_again
+
+	/*
+	 * 38 nop's, which fills reset of wfe cache line and
+	 * 4 more cachelines with nop
+	 */
+	.rept 38
+	nop
+	.endr
+	b	.				@ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index d0c7a8b..0f047eb 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -19,6 +19,8 @@
 
 #include <mach/iomap.h>
 
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
 
@@ -52,5 +54,28 @@
 	movw	\reg, #:lower16:\val
 	movt	\reg, #:upper16:\val
 .endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
+	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
+	isb
+	cpu_id	\tmp1
+	mov	\tmp1, \tmp1, lsl #2
+	mov	\tmp2, #0xf
+	mov	\tmp2, \tmp2, lsl \tmp1
+	mov32	\tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+	str	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
+	dsb
+.endm
+#else
+
+#ifdef CONFIG_HOTPLUG_CPU
+void tegra30_hotplug_init(void);
+#else
+static inline void tegra30_hotplug_init(void) {}
+#endif
+
 #endif
 #endif
-- 
1.7.0.4



From josephl at nvidia.com  Thu Aug 16 05:31:52 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:52 +0800
Subject: [PATCH V3 5/6] ARM: tegra20: add CPU hotplug support
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-6-git-send-email-josephl@nvidia.com>

Hotplug function put CPU in offline or online mode at runtime.
When the CPU been put into offline, it was been clock gated. The
offline CPU can be power gated, when the remaining CPU goes into
LP2.

Based on the worked by:
Colin Cross <ccross at android.com>
Gary King <gking at nvidia.com>

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* fix the compiling error when HOTPLUG_CPU disabled
V2:
* no change

 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/common.c    |    1 +
 arch/arm/mach-tegra/hotplug.c   |    8 ++++
 arch/arm/mach-tegra/sleep-t20.S |   82 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/sleep.h     |    4 ++
 5 files changed, 96 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/sleep-t20.S

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 211e279..959a429 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= sleep-t30.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0652056..0560538 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -136,6 +136,7 @@ void __init tegra20_init_early(void)
 	tegra_init_cache(0x331, 0x441);
 	tegra_pmc_init();
 	tegra_powergate_init();
+	tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index be92d4c..d02a354 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -56,6 +56,14 @@ int platform_cpu_disable(unsigned int cpu)
 	return cpu == 0 ? -EPERM : 0;
 }
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+	tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 extern void tegra30_hotplug_shutdown(void);
 void __init tegra30_hotplug_init(void)
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 0000000..a36ae41
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross at android.com>
+ *         Gary King <gking at nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+	/* Turn off SMP coherency */
+	exit_smp r4, r5
+
+	/* Put this CPU down */
+	cpu_id	r0
+	bl	tegra20_cpu_shutdown
+	mov	pc, lr			@ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+	cmp	r0, #0
+	moveq	pc, lr			@ must not be called for CPU 0
+
+	cpu_to_halt_reg r1, r0
+	ldr	r3, =TEGRA_FLOW_CTRL_VIRT
+	mov	r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+	str	r2, [r3, r1]		@ put flow controller in wait event mode
+	ldr	r2, [r3, r1]
+	isb
+	dsb
+	movw	r1, 0x1011
+	mov	r1, r1, lsl r0
+	ldr	r3, =TEGRA_CLK_RESET_VIRT
+	str	r1, [r3, #0x340]	@ put slave CPU in reset
+	isb
+	dsb
+	cpu_id	r3
+	cmp	r3, r0
+	beq	.
+	mov	pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 0f047eb..e25a7cd 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -23,6 +23,8 @@
 					+ IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
 					+ IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+					+ IO_PPSB_VIRT)
 
 #ifdef __ASSEMBLY__
 /* returns the offset of the flow controller halt register for a cpu */
@@ -72,8 +74,10 @@
 #else
 
 #ifdef CONFIG_HOTPLUG_CPU
+void tegra20_hotplug_init(void);
 void tegra30_hotplug_init(void);
 #else
+static inline void tegra20_hotplug_init(void) {}
 static inline void tegra30_hotplug_init(void) {}
 #endif
 
-- 
1.7.0.4



From josephl at nvidia.com  Thu Aug 16 05:31:53 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Thu, 16 Aug 2012 17:31:53 +0800
Subject: [PATCH V3 6/6] ARM: tegra: defconfig: enable HOTPLUG_CPU
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <1345109513-21553-7-git-send-email-josephl@nvidia.com>

Enable HOTPLUG_CPU after the SoC specific code to hotplug a CPU
been merged.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
V3:
* no change
V2:
* init version

 arch/arm/configs/tegra_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 4f078e0..c7f7c7f 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -31,6 +31,7 @@ CONFIG_TEGRA_PCI=y
 CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
+CONFIG_HOTPLUG_CPU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-- 
1.7.0.4



From hvaibhav at ti.com  Thu Aug 16 05:36:44 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 16 Aug 2012 09:36:44 +0000
Subject: [PATCH v2 04/14] ARM: OMAP5: Add minimal support for OMAP5430 SOC
In-Reply-To: <alpine.DEB.2.00.1208151618590.1731@utopia.booyaka.com>
References: <1341566515-22665-1-git-send-email-santosh.shilimkar@ti.com>
 <1341566515-22665-5-git-send-email-santosh.shilimkar@ti.com>
 <4FFA9B61.8030808@ti.com> <20120709131156.GH1122@atomide.com>
 <alpine.DEB.2.00.1208151618590.1731@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA91188@DBDE01.ent.ti.com>

On Thu, Aug 16, 2012 at 03:56:42, Paul Walmsley wrote:
> Hi
> 
> On Mon, 9 Jul 2012, Tony Lindgren wrote:
> 
> > Below (untested) is what could be done in the short term.
> 
> That's fine with me.  Do you want to queue it or do you want me to queue 
> it?
> 
> > Heh these CK_XXXX defines are now running out of the u16 cpu_mask.
> > 
> > They really should be replaced with SoC specific lists of clocks
> > rather than bloating the cpu_mask and repeating it for every clock
> > that's compiled in for 800+ times.
> 
> Frankly, an extra 1.6KB -- uncompressed -- is pretty low on my list of 
> bloat concerns for multi-OMAP kernels.  If it were up to me, I'd just 
> change it to a u32 and be done with the problem for the foreseeable 
> future.
> 
> > I wonder if we could #define CK_OMAP_DUMMY 0 that's always set
> > for non-shared clocks if they only get set in some *_data.c
> > file in a unique way?
> > 
> > Paul got any better ideas?
> 
> Aside from using u32?  Not really.  As we've discussed in the past, at 
> some point we should convert the clock initialization to using some kind 
> of per-SoC list.  But it doesn't seem worth spending too much time on that 
> while the common clock framework conversion is higher priority.
> 
> 

This reminds me for AM33xx clock-tree migration to common-clock framework,
so just wanted to update on this, I have already converted the clock-tree to 
common-clock fw, on top of Rajendra's repository.

Now waiting on Rajendra for his next series...

Thanks,
Vaibhav



From dave.martin at linaro.org  Thu Aug 16 05:43:18 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 16 Aug 2012 10:43:18 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <20120816091953.GL18957@n2100.arm.linux.org.uk>
References: <20120813160008.GA30302@n2100.arm.linux.org.uk>
 <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
 <20120816082726.GA2101@linaro.org>
 <20120816091953.GL18957@n2100.arm.linux.org.uk>
Message-ID: <20120816094318.GB2101@linaro.org>

On Thu, Aug 16, 2012 at 10:19:53AM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 16, 2012 at 09:27:26AM +0100, Dave Martin wrote:
> > Could we use the currently must-be-zero flags parameter to add new
> > functionality to this syscall, or are there legacy uses of that
> > parameter (or history of userspace not bothering to zero it?)
> > 
> > For example, we could have something like
> > 
> > do_cache_op(struct iovec *iov, int iovcnt, CF_IOVEC)
> > 
> > to flush a discontiguous set of ranges described by an iovec (though we
> > can of course also describe the ranges in other ways)
> 
> Why overload an existing syscall with multiple different argument types
> rather than having a new syscall with a sane API?

Sure, if it's OK to add a new system call, that would be a cleaner
approach.

Cheers
---Dave


From will.deacon at arm.com  Thu Aug 16 05:54:31 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 10:54:31 +0100
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <502C04CF.2080409@mentor.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
 <502BD544.70903@mentor.com>
 <20120815172731.GL29448@mudshark.cambridge.arm.com>
 <502BFA08.6010708@mentor.com> <502C04CF.2080409@mentor.com>
Message-ID: <20120816095431.GE31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 09:21:35PM +0100, Wade Farnsworth wrote:
> Wade Farnsworth wrote:
> > Will Deacon wrote:
> >> On Wed, Aug 15, 2012 at 05:58:44PM +0100, Wade Farnsworth wrote:
> >>> We need to set current_thread_info()->syscall, since it's used in the
> >>> call to syscall_get_nr() in perf_syscall_{enter,exit}.
> >>
> >> Damn. I think that also means we have a bug, given that the SYSCALL_TRACE
> >> code can set this to -1, which gets used as an index into a bitmap by the
> >> looks of it. Considering that we have to pass the syscall number to
> >> trace_sys_enter anyway, it also seems broken.
> >>
> >
> > I agree. Looking at the other architectures, it seems the analogous
> > function to ptrace_syscall_trace can return -1 under certain
> > circumstances, but the original syscall value should be passed onto
> > trace_sys_enter and returned from syscall_get_nr(). So, I'm thinking
> > that we should modify our behavior accordingly. What this means for us
> > is that we never store -1 in the thread_info syscall field, and then
> > pass that into trace_sys_enter instead of the ptrace_syscall_trace
> > return value. Do you see any problems with this approach?
> >
> 
> Hmm, on closer inspection it looks that perf_syscall_enter is broken. 
> ftrace_syscall_enter correctly returns if result of a syscall_get_nr is 
> negative.  The perf version omits the check for negative values. 

Yes, that's what I was getting at with the -1 bitmap index. Something like
this should fix it though:


diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index 96fc733..bbff120 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -506,13 +506,13 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)
        int size;
 
        syscall_nr = syscall_get_nr(current, regs);
-       if (!test_bit(syscall_nr, enabled_perf_enter_syscalls))
-               return;
-
        sys_data = syscall_nr_to_meta(syscall_nr);
        if (!sys_data)
                return;
 
+       if (!test_bit(syscall_nr, enabled_perf_enter_syscalls))
+               return;
+
        /* get the size after alignment with the u32 buffer size field */
        size = sizeof(unsigned long) * sys_data->nb_args + sizeof(*rec);
        size = ALIGN(size + sizeof(u32), sizeof(u64));


If you're happy with that, I can post to LKML and see what people say.

Will


From will.deacon at arm.com  Thu Aug 16 06:05:37 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:05:37 +0100
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <201208151303.47743.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-4-git-send-email-catalin.marinas@arm.com>
 <201208151303.47743.arnd@arndb.de>
Message-ID: <20120816100536.GF31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 02:03:47PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +#ifdef CONFIG_AARCH32_EMULATION
> > +#define compat_thumb_mode(regs) \
> > +	(((regs)->pstate & COMPAT_PSR_T_BIT))
> > +#else
> > +#define compat_thumb_mode(regs) (0)
> > +#endif
> 
> The symbol we use on other platforms is CONFIG_COMPAT. I don't think you
> need to have a separate CONFIG_AARCH32_EMULATION

Using COMPAT does preclude the possibility of doing something like the x32
ABI later on though. Some other architectures seem to do something similar
(MIPS32_COMPAT, IA32_EMULATION).

Will


From prabhakar.lad at ti.com  Thu Aug 16 06:13:33 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Thu, 16 Aug 2012 15:43:33 +0530
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions
 for VPIF
In-Reply-To: <502A4464.3020706@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
 <502A4464.3020706@ti.com>
Message-ID: <502CC7CD.80906@ti.com>

Hi Sekhar,

Thanks for the review. My comments are inlined.

On Tuesday 14 August 2012 05:58 PM, Sekhar Nori wrote:
> Hi Prabhakar,
> 
> On 7/24/2012 1:13 PM, Prabhakar Lad wrote:
>> From: Manjunath Hadli <manjunath.hadli at ti.com>
>>
>> Add clock, pin mux definitions and registration function for
>> VPIF capture and display driver on DA850/OMAP-L138 SoC.
>>
>> Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
>> Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
>> Cc: Sekhar Nori <nsekhar at ti.com>
>> ---
>>  arch/arm/mach-davinci/da850.c              |  256 ++++++++++++++++++++++++++++
>>  arch/arm/mach-davinci/include/mach/da8xx.h |   11 ++
>>  arch/arm/mach-davinci/include/mach/mux.h   |   42 +++++
>>  arch/arm/mach-davinci/include/mach/psc.h   |    1 +
>>  4 files changed, 310 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
>> index b44dc84..c864431 100644
>> --- a/arch/arm/mach-davinci/da850.c
>> +++ b/arch/arm/mach-davinci/da850.c
>> @@ -347,6 +347,13 @@ static struct clk spi1_clk = {
>>  	.flags		= DA850_CLK_ASYNC3,
>>  };
>>  
>> +static struct clk vpif_clk = {
>> +	.name		= "vpif",
>> +	.parent		= &pll0_sysclk2,
>> +	.lpsc		= DA850_LPSC1_VPIF,
>> +	.gpsc		= 1,
>> +};
>> +
>>  static struct clk sata_clk = {
>>  	.name		= "sata",
>>  	.parent		= &pll0_sysclk2,
>> @@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = {
>>  	CLK(NULL,		"usb20",	&usb20_clk),
>>  	CLK("spi_davinci.0",	NULL,		&spi0_clk),
>>  	CLK("spi_davinci.1",	NULL,		&spi1_clk),
>> +	CLK(NULL,		"vpif",		&vpif_clk),
> 
> You should dev_id for lookup instead of con_id. Looking at
> drivers/media/video/davinci/vpif.c, there is a single clock that VPIF
> needs, so con_id can actually be passed as NULL.
> 
  Ok I'll use dev_id.

>>  	CLK("ahci",		NULL,		&sata_clk),
>>  	CLK(NULL,		NULL,		NULL),
>>  };
>> @@ -573,6 +581,46 @@ static const struct mux_config da850_pins[] = {
>>  	MUX_CFG(DA850, GPIO6_10,	13,	20,	15,	8,	false)
>>  	MUX_CFG(DA850, GPIO6_13,	13,	8,	15,	8,	false)
>>  	MUX_CFG(DA850, RTC_ALARM,	0,	28,	15,	2,	false)
>> +	/* VPIF Capture */
>> +	MUX_CFG(DA850, VPIF_DIN0,	15,	4,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN1,	15,	0,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN2,	14,	28,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN3,	14,	24,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN4,	14,	20,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN5,	14,	16,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN6,	14,	12,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN7,	14,	8,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN8,	16,	4,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN9,	16,	0,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN10,	15,	28,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN11,	15,	24,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN12,	15,	20,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN13,	15,	16,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN14,	15,	12,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DIN15,	15,	8,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKIN0,	14,	0,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKIN1,	14,	4,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKIN2,	19,	8,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKIN3,	19,	16,	15,	1,	false)
>> +	/* VPIF Display */
>> +	MUX_CFG(DA850, VPIF_DOUT0,	17,	4,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT1,	17,	0,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT2,	16,	28,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT3,	16,	24,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT4,	16,	20,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT5,	16,	16,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT6,	16,	12,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT7,	16,	8,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT8,	18,	4,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT9,	18,	0,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT10,	17,	28,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT11,	17,	24,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT12,	17,	20,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT13,	17,	16,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT14,	17,	12,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_DOUT15,	17,	8,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKO2,	19,	12,	15,	1,	false)
>> +	MUX_CFG(DA850, VPIF_CLKO3,	19,	20,	15,	1,	false)
>>  #endif
>>  };
>>  
>> @@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initdata = {
>>  	-1
>>  };
>>  
>> +const short da850_vpif_capture_pins[] __initdata = {
>> +	DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
>> +	DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
>> +	DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
>> +	DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
>> +	DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
>> +	DA850_VPIF_CLKIN3,
>> +	-1
>> +};
>> +
>> +const short da850_vpif_display_pins[] __initdata = {
>> +	DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
>> +	DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
>> +	DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
>> +	DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
>> +	DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
>> +	DA850_VPIF_CLKO3,
>> +	-1
>> +};
>> +
>>  /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
>>  static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
>>  	[IRQ_DA8XX_COMMTX]		= 7,
>> @@ -1064,6 +1132,194 @@ no_ddrpll_mem:
>>  	return ret;
>>  }
>>  
>> +/* VPIF resource, platform data */
>> +static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
>> +
>> +static struct resource da850_vpif_resource[] = {
>> +	{
>> +		.start	= DA8XX_VPIF_BASE,
>> +		.end	= DA8XX_VPIF_BASE + 0xfff,
>> +		.flags	= IORESOURCE_MEM,
>> +	}
>> +};
>> +
>> +static struct platform_device da850_vpif_dev = {
>> +	.name		= "vpif",
>> +	.id		= -1,
>> +	.dev		= {
>> +			.dma_mask		= &da850_vpif_dma_mask,
>> +			.coherent_dma_mask	= DMA_BIT_MASK(32),
>> +	},
>> +	.resource	= da850_vpif_resource,
>> +	.num_resources	= ARRAY_SIZE(da850_vpif_resource),
>> +};
>> +
>> +static unsigned long vpif_disp_cont_buf_offset;
>> +
>> +static int __init cfg_vpif_disp_cont_buf_offset(char *p)
>> +{
>> +	if (!p)
>> +		return 0;
>> +
>> +	return kstrtoul(p, 10, &vpif_disp_cont_buf_offset);
>> +}
>> +early_param("vpif_disp_cont_buf_offset", cfg_vpif_disp_cont_buf_offset);
>> +
>> +static unsigned long vpif_disp_cont_bufsize;
>> +
>> +static int __init cfg_vpif_disp_cont_bufsize(char *p)
>> +{
>> +	if (!p)
>> +		return 0;
>> +
>> +	return kstrtoul(p, 10, &vpif_disp_cont_bufsize);
>> +}
>> +early_param("vpif_disp_cont_bufsize", cfg_vpif_disp_cont_bufsize);
>> +
>> +static unsigned long vpif_cap_cont_buf_offset;
>> +
>> +static int __init cfg_vpif_cap_cont_buf_offset(char *p)
>> +{
>> +	if (!p)
>> +		return 0;
>> +
>> +	return kstrtoul(p, 10, &vpif_cap_cont_buf_offset);
>> +}
>> +early_param("vpif_cap_cont_buf_offset", cfg_vpif_cap_cont_buf_offset);
>> +
>> +static unsigned long vpif_cap_cont_bufsize;
>> +
>> +static int __init cfg_vpif_cap_cont_bufsize(char *p)
>> +{
>> +	if (!p)
>> +		return 0;
>> +
>> +	return kstrtoul(p, 10, &vpif_cap_cont_bufsize);
>> +}
>> +early_param("vpif_cap_cont_bufsize", cfg_vpif_cap_cont_bufsize);
> 
> 
> All these kernel parameters will need to be documented in
> Documentation/kernel-parameters.txt. I suspect they should rather be
> module parameters?
> 
This was added since dma_declare_coherent() should be done in the
machine file. This was discussed over this thread,
http://linux.omap.com/pipermail/davinci-linux-open-source/2012-May/024165.html.


>> +
>> +static struct platform_device da850_vpif_display_dev = {
>> +	.name		= "vpif_display",
>> +	.id		= -1,
>> +	.dev		= {
>> +		.dma_mask		= &da850_vpif_dma_mask,
>> +		.coherent_dma_mask	= DMA_BIT_MASK(32),
>> +	},
>> +};
>> +
>> +static struct platform_device da850_vpif_capture_dev = {
>> +	.name		= "vpif_capture",
>> +	.id		= -1,
>> +	.dev		= {
>> +		.dma_mask		= &da850_vpif_dma_mask,
>> +		.coherent_dma_mask	= DMA_BIT_MASK(32),
>> +	},
>> +};
>> +
>> +int __init da850_register_vpif(void)
>> +{
>> +	return platform_device_register(&da850_vpif_dev);
>> +}
>> +
>> +int __init da850_register_vpif_display(struct vpif_display_config
>> +						*display_config)
>> +{
>> +	struct resource da850_vpif_display_resource[] = {
>> +		{
>> +			.start = IRQ_DA850_VPIFINT,
>> +			.end   = IRQ_DA850_VPIFINT,
>> +			.flags = IORESOURCE_IRQ,
>> +		},
>> +		{},
>> +	};
>> +	unsigned long phys_end_kernel;
>> +	int ret;
>> +
>> +	if (vpif_disp_cont_bufsize) {
>> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
>> +					(num_physpages << PAGE_SHIFT);
>> +		phys_end_kernel += vpif_disp_cont_buf_offset;
>> +		da850_vpif_display_resource[1].start = phys_end_kernel;
>> +		da850_vpif_display_resource[1].end = phys_end_kernel +
>> +						vpif_disp_cont_bufsize - 1;
>> +		da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
>> +
>> +		if (!request_mem_region(da850_vpif_display_resource[1].start,
>> +				resource_size(&da850_vpif_display_resource[1]),
>> +				da850_vpif_display_dev.name)) {
>> +			pr_err("region already claimed.\n");
>> +			return -EBUSY;
>> +		}
>> +		ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
>> +				phys_end_kernel, phys_end_kernel,
>> +				vpif_disp_cont_bufsize,
>> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
>> +
>> +		if (!ret)
>> +			return -ENOMEM;
>> +	}
>> +	ret = platform_device_add_resources(&da850_vpif_display_dev,
>> +				da850_vpif_display_resource,
>> +				ARRAY_SIZE(da850_vpif_display_resource));
> 
> You are taking memory at the end of RAM and passing it as a IO resource
> to the driver. This is not correct. For contiguous memory needs can you
> look at the recently merged CMA framework (include/linux/dma-contiguous.h)
> 
Ok. But looks like CMA is enabled for CPU_V6/V6K/V7. If CMA is enabled
for ARM926 too than we can use the global CMA itself rather then doing
it for each device, then three will be no need to do the above and all
the kernel parameters can be removed too.

>> +	if (ret)
>> +		return -EINVAL;
>> +
>> +	da850_vpif_display_dev.dev.platform_data = display_config;
>> +	return platform_device_register(&da850_vpif_display_dev);
>> +}
>> +
>> +int __init da850_register_vpif_capture(struct vpif_capture_config
>> +							*capture_config)
>> +{
>> +	static struct resource da850_vpif_capture_resource[] = {
>> +		{
>> +			.start = IRQ_DA850_VPIFINT,
>> +			.end   = IRQ_DA850_VPIFINT,
>> +			.flags = IORESOURCE_IRQ,
>> +		},
>> +		{
>> +			.start = IRQ_DA850_VPIFINT,
>> +			.end   = IRQ_DA850_VPIFINT,
>> +			.flags = IORESOURCE_IRQ,
>> +		},
>> +		{},
>> +	};
>> +	unsigned long phys_end_kernel;
>> +	int ret;
>> +
>> +	if (vpif_cap_cont_bufsize) {
>> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
>> +					(num_physpages << PAGE_SHIFT);
>> +		phys_end_kernel += vpif_cap_cont_buf_offset;
>> +		da850_vpif_capture_resource[2].start = phys_end_kernel;
>> +		da850_vpif_capture_resource[2].end = phys_end_kernel +
>> +						vpif_cap_cont_bufsize - 1;
>> +		da850_vpif_capture_resource[2].flags = IORESOURCE_MEM;
>> +
>> +		if (!request_mem_region(da850_vpif_capture_resource[2].start,
>> +				resource_size(&da850_vpif_capture_resource[2]),
>> +				da850_vpif_capture_dev.name)) {
>> +			pr_err("region already claimed.\n");
>> +			return -EBUSY;
>> +		}
>> +		ret = dma_declare_coherent_memory(&da850_vpif_capture_dev.dev,
>> +				phys_end_kernel, phys_end_kernel,
>> +				vpif_cap_cont_bufsize, DMA_MEMORY_MAP |
>> +				DMA_MEMORY_EXCLUSIVE);
>> +
>> +		if (!ret)
>> +			return -ENOMEM;
>> +	}
>> +	ret = platform_device_add_resources(&da850_vpif_capture_dev,
>> +				da850_vpif_capture_resource,
>> +				ARRAY_SIZE(da850_vpif_capture_resource));
> 
> The capture has the same problems as the display part above.
> 
  ditto

>> +	if (ret)
>> +		return -EINVAL;
>> +
>> +	da850_vpif_capture_dev.dev.platform_data = capture_config;
>> +	return platform_device_register(&da850_vpif_capture_dev);
>> +}
>> +
>>  static struct davinci_soc_info davinci_soc_info_da850 = {
>>  	.io_desc		= da850_io_desc,
>>  	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
>> diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
>> index a2f1f27..0028bd7 100644
>> --- a/arch/arm/mach-davinci/include/mach/da8xx.h
>> +++ b/arch/arm/mach-davinci/include/mach/da8xx.h
>> @@ -16,6 +16,7 @@
>>  #include <linux/platform_device.h>
>>  #include <linux/davinci_emac.h>
>>  #include <linux/spi/spi.h>
>> +#include <linux/videodev2.h>
>>  
>>  #include <mach/serial.h>
>>  #include <mach/edma.h>
>> @@ -26,6 +27,8 @@
>>  #include <mach/pm.h>
>>  #include <mach/spi.h>
>>  
>> +#include <media/davinci/vpif_types.h>
>> +
>>  extern void __iomem *da8xx_syscfg0_base;
>>  extern void __iomem *da8xx_syscfg1_base;
>>  
>> @@ -69,6 +72,7 @@ extern unsigned int da850_max_speed;
>>  #define DA8XX_AEMIF_CS3_BASE	0x62000000
>>  #define DA8XX_AEMIF_CTL_BASE	0x68000000
>>  #define DA8XX_ARM_RAM_BASE	0xffff0000
>> +#define DA8XX_VPIF_BASE		0x01e17000
> 
> These are sorted in increasing order of address. This helps avoid
> duplicates.
> 
 Ok I'll keep them sorted.

Thx,
--Prabhakar

> Thanks,
> Sekhar
> 



From hdk at igel.co.jp  Thu Aug 16 06:13:58 2012
From: hdk at igel.co.jp (Hideki EIRAKU)
Date: Thu, 16 Aug 2012 19:13:58 +0900 (JST)
Subject: [PATCH v3 3/4] media: videobuf2-dma-contig: use
 dma_mmap_coherent if available
In-Reply-To: <012701cd74ac$6a617060$3f245120$%szyprowski@samsung.com>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-4-git-send-email-hdk@igel.co.jp>
 <012701cd74ac$6a617060$3f245120$%szyprowski@samsung.com>
Message-ID: <20120816.191358.127675610.hdk@igel.co.jp>

Hello,

From: Marek Szyprowski <m.szyprowski at samsung.com>
Subject: RE: [PATCH v3 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent if available
Date: Tue, 07 Aug 2012 16:53:25 +0200

> I'm sorry for bringing this issue now, once you have already created v3 of your
> patches, but similar patch has been already proposed some time ago. It is already
> processed together with general videobuf2-dma-contig redesign and dma-buf extensions
> by Tomasz Stanislawski.
> 
> See post http://thread.gmane.org/gmane.comp.video.dri.devel/70402/focus=49461 and
> http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/49438 
> 
> It doesn't use conditional code inside videobuf2 allocator and rely entirely on 
> dma-mapping subsystem to provide a working dma_mmap_coherent/writecombine/attrs() 
> function. When it was posted, it relied on the dma-mapping extensions, which now
> have been finally merged to v3.6-rc1. Now I wonder if there are any architectures, 
> which don't use dma_map_ops based dma-mapping framework, which might use 
> videobuf2-dma-conting module. 

Thank you for telling me about videobuf2-dma-contig and v3.6-rc1.  The
videobuf2-dma-contig patch I sent is now unnecessary.  So I will
remove the patch.  I will remove the patch defining
ARCH_HAS_DMA_MMAP_COHERENT too because the v3.6-rc1 kernel has generic
dma_mmap_coherent() API for every architecture.

I will also remove the Laurent's patch I sent because it was related
to ARCH_HAS_DMA_MMAP_COHERENT.

The remaining patch is sh_mobile_lcdc.  I will remove ifdefs from the
patch and re-post it as a patch v4.

-- 
Hideki EIRAKU <hdk at igel.co.jp>


From will.deacon at arm.com  Thu Aug 16 06:23:00 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:23:00 +0100
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <201208151415.39570.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-17-git-send-email-catalin.marinas@arm.com>
 <201208151415.39570.arnd@arndb.de>
Message-ID: <20120816102300.GG31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 03:15:39PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +
> > +void elf_set_personality(int personality)
> > +{
> > +       switch (personality & PER_MASK) {
> > +       case PER_LINUX:
> > +               clear_thread_flag(TIF_32BIT);
> > +               break;
> > +       case PER_LINUX32:
> > +               set_thread_flag(TIF_32BIT);
> > +               break;
> > +       default:
> > +               pr_warning("Process %s tried to assume unknown personality %d\n",
> > +                          current->comm, personality);
> > +               return;
> > +       }
> > +
> > +       current->personality = personality;
> > +}
> > +EXPORT_SYMBOL(elf_set_personality);
> 
> This looks wrong: PER_LINUX/PER_LINUX32 decides over the output of the
> uname system call, while TIF_32BIT decides over the instruction set
> when returning to user space. You definitely should not set the personality
> to the value you pass from the elf loader. Instead, just do
> 
> #define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
> #defined COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);

In this case, won't uname be incorrect (aarch64l) for aarch32 tasks (which
expect something like armv8l)?

Will


From linux at prisktech.co.nz  Thu Aug 16 06:18:52 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 16 Aug 2012 10:18:52 +0000
Subject: [PATCHv2 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <502BF734.9000608@wwwdotorg.org>
References: <1344477300-25251-1-git-send-email-linux@prisktech.co.nz>,
 <502BF734.9000608@wwwdotorg.org>
Message-ID: <76F764B079F92A4E843589C893D0A022D62814E9@SERVER.prisktech.co.nz>

>>On 08/08/2012 07:54 PM, Tony Prisk wrote:
>> This patchset updates arch-vt8500 to devicetree and removes all the old-style
>> code. Support for WM8650 has also been added.

>Sorry for taking such a long time to re-review this.

>I scanned the series looking for just the changes to the issues I raised
>on v1, and I do see almost everything has been fixed up OK, except for
>the one issue I just commented on. So, aside from that, this series is
>fine by me. I'll defer to others about whether it's necessary to fix the
>display node-name-vs.-phandle issue I pointed out, or defer that until
>later.

Thanks for the review Stephen.

There will be a v3 shortly - I noticed a few other issues that needed to
be corrected as well. I agree with the display-node/phandle comment
and will make sure its included for v3. To be honest, it just slipped my
memory at the time.

Tony Prisk

From will.deacon at arm.com  Thu Aug 16 06:28:09 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:28:09 +0100
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <201208151434.05145.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
Message-ID: <20120816102808.GH31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 03:34:04PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> > +{
> > +	int ret;
> > +
> > +	if (personality(current->personality) == PER_LINUX32 &&
> > +		personality == PER_LINUX)
> > +		personality = PER_LINUX32;
> > +	ret = sys_personality(personality);
> > +	if (ret == PER_LINUX32)
> > +		ret = PER_LINUX;
> > +	return ret;
> > +}
> 
> Where did you get this from?
> 
> You should not need compat_sys_personality, just call the native function.

Hmm, but in that case an aarch32 application doing a personality(PER_LINUX)
syscall will start seeing the wrong uname.

Will


From prabhakar.lad at ti.com  Thu Aug 16 06:31:51 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Thu, 16 Aug 2012 16:01:51 +0530
Subject: [PATCH 2/2] ARM: da850/omap-l138: Add EVM specific code for VPIF
 to work
In-Reply-To: <502A4BFB.9020407@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-3-git-send-email-prabhakar.lad@ti.com>
 <502A4BFB.9020407@ti.com>
Message-ID: <502CCC17.9080208@ti.com>

Hi Sekhar,

Thanks for the review.

On Tuesday 14 August 2012 06:30 PM, Sekhar Nori wrote:
> Hi Prabhakar,
> 
> On 7/24/2012 1:13 PM, Prabhakar Lad wrote:
>> From: Manjunath Hadli <manjunath.hadli at ti.com>
>>
>> Include the expander settings to select VPIF peripheral on
>> UI card and add registration call in EVM init. Also add platform
>> data to configure display and capture devices.
>>
>> Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
>> Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
>> Cc: Sekhar Nori <nsekhar at ti.com>
>> ---
>>  arch/arm/mach-davinci/Kconfig           |    9 ++
>>  arch/arm/mach-davinci/board-da850-evm.c |  195 +++++++++++++++++++++++++++++++
>>  2 files changed, 204 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
>> index 32d837d..19ee4ee 100644
>> --- a/arch/arm/mach-davinci/Kconfig
>> +++ b/arch/arm/mach-davinci/Kconfig
>> @@ -190,6 +190,15 @@ config DA850_UI_RMII
>>  	  NOTE: Please take care while choosing this option, MII PHY will
>>  	  not be functional if RMII mode is selected.
>>  
>> +config DA850_UI_SD_VIDEO_PORT
>> +	bool "Video Port Interface"
>> +	help
>> +	  Say Y if you want to use Video Port Interface (VPIF) on the
>> +	  DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
>> +	  UI daughter card that is supplied with the EVM.
>> +	  NOTE: Please make sure to disable RMII and CLCD options when you
>> +	  select Video Port Interface.
> 
> RMII is in the same choice block as this so it is not possible to have
> RMII enabled along with video port selection. On the CLCD, it will be
> good to register only one of CLCD or video and print a warning if user
> enabled both. davinci_evm_init() in
> arch/arm/mach-davinci/board-dm644x-evm.c has an example of this.
> 
 The CLCD support is not in mainlined yet, if it is the option to enable
the CLCD will also come in the same choice block if  I am not wrong. So
by any means the user can select only one of them.

>> +
>>  endchoice
>>  
>>  config DA850_WL12XX
>> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
>> index 0149fb4..1f5d2c1 100644
>> --- a/arch/arm/mach-davinci/board-da850-evm.c
>> +++ b/arch/arm/mach-davinci/board-da850-evm.c
>> @@ -45,6 +45,8 @@
>>  #include <mach/aemif.h>
>>  #include <mach/spi.h>
>>  
>> +#include <media/tvp514x.h>
>> +
>>  #define DA850_EVM_PHY_ID		"davinci_mdio-0:00"
>>  #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
>>  #define DA850_LCD_BL_PIN		GPIO_TO_PIN(2, 15)
>> @@ -121,6 +123,12 @@ static struct spi_board_info da850evm_spi_info[] = {
>>  	},
>>  };
>>  
>> +#define TVP5147_CH0		"tvp514x-0"
>> +#define TVP5147_CH1		"tvp514x-1"
>> +
>> +#define VPIF_STATUS		0x002c
>> +#define VPIF_STATUS_CLR		0x0030
>> +
>>  #ifdef CONFIG_MTD
>>  static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
>>  {
>> @@ -452,6 +460,15 @@ static void da850_evm_ui_keys_init(unsigned gpio)
>>  	}
>>  }
>>  
>> +#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
>> +static inline void da850_evm_setup_video_port(int video_sel)
>> +{
>> +	gpio_set_value_cansleep(video_sel, 0);
>> +}
>> +#else
>> +static inline void da850_evm_setup_video_port(int video_sel) { }
>> +#endif
>> +
>>  static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
>>  						unsigned ngpio, void *c)
>>  {
>> @@ -497,6 +514,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
>>  
>>  	da850_evm_setup_emac_rmii(sel_a);
>>  
>> +	da850_evm_setup_video_port(sel_c);
>> +
>>  	return 0;
>>  
>>  exp_setup_keys_fail:
>> @@ -1149,6 +1168,151 @@ static __init int da850_evm_init_cpufreq(void)
>>  static __init int da850_evm_init_cpufreq(void) { return 0; }
>>  #endif
>>  
>> +/* Retaining these APIs, since the VPIF drivers do not check NULL handlers */
>> +static int da850_set_vpif_clock(int mux_mode, int hd)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int da850_setup_vpif_input_channel_mode(int mux_mode)
>> +{
>> +	return 0;
>> +}
>> +
>> +int da850_vpif_setup_input_path(int ch, const char *name)
>> +{
>> +	return 0;
>> +}
> 
> Why not enhance the VPIF driver to handle NULL values for these instead?
> 
  Ok can be done.
>> +
>> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
>> +/* VPIF capture configuration */
>> +static struct tvp514x_platform_data tvp5146_pdata = {
>> +	.clk_polarity = 0,
>> +	.hs_polarity = 1,
>> +	.vs_polarity = 1
>> +};
>> +#endif
>> +
>> +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
>> +
>> +static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
>> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
> 
> Why not just continue with the previous #ifdef
> CONFIG_DA850_UI_SD_VIDEO_PORT?
> 
 Ok

>> +	{
>> +		.name	= TVP5147_CH0,
>> +		.board_info = {
>> +			I2C_BOARD_INFO("tvp5146", 0x5d),
>> +			.platform_data = &tvp5146_pdata,
>> +		},
>> +		.input = INPUT_CVBS_VI2B,
>> +		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>> +		.can_route = 1,
>> +		.vpif_if = {
>> +			.if_type = VPIF_IF_BT656,
>> +			.hd_pol = 1,
>> +			.vd_pol = 1,
>> +			.fid_pol = 0,
>> +		},
>> +	},
>> +	{
>> +		.name	= TVP5147_CH1,
>> +		.board_info = {
>> +			I2C_BOARD_INFO("tvp5146", 0x5c),
>> +			.platform_data = &tvp5146_pdata,
>> +		},
>> +		.input = INPUT_SVIDEO_VI2C_VI1C,
>> +		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
>> +		.can_route = 1,
>> +		.vpif_if = {
>> +			.if_type = VPIF_IF_BT656,
>> +			.hd_pol = 1,
>> +			.vd_pol = 1,
>> +			.fid_pol = 0,
>> +		},
>> +	},
>> +#endif
>> +};
>> +
>> +static const struct vpif_input da850_ch0_inputs[] = {
>> +	{
>> +		.input = {
>> +			.index = 0,
>> +			.name = "Composite",
>> +			.type = V4L2_INPUT_TYPE_CAMERA,
>> +			.std = TVP514X_STD_ALL,
>> +		},
>> +		.subdev_name = TVP5147_CH0,
>> +	},
>> +};
>> +
>> +static const struct vpif_input da850_ch1_inputs[] = {
>> +	{
>> +		.input = {
>> +			.index = 0,
>> +			.name = "S-Video",
>> +			.type = V4L2_INPUT_TYPE_CAMERA,
>> +			.std = TVP514X_STD_ALL,
>> +		},
>> +		.subdev_name = TVP5147_CH1,
>> +	},
>> +};
>> +
>> +static struct vpif_capture_config da850_vpif_capture_config = {
>> +	.setup_input_channel_mode = da850_setup_vpif_input_channel_mode,
>> +	.setup_input_path = da850_vpif_setup_input_path,
>> +	.subdev_info = da850_vpif_capture_sdev_info,
>> +	.subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
>> +#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
> 
> Same here.
> 
  Ok
>> +	.chan_config[0] = {
>> +		.inputs = da850_ch0_inputs,
>> +		.input_count = ARRAY_SIZE(da850_ch0_inputs),
>> +	},
>> +	.chan_config[1] = {
>> +		.inputs = da850_ch1_inputs,
>> +		.input_count = ARRAY_SIZE(da850_ch1_inputs),
>> +	},
>> +#endif
>> +	.card_name      = "DA850/OMAP-L138 Video Capture",
>> +};
>> +
>> +/* VPIF display configuration */
>> +static struct vpif_subdev_info da850_vpif_subdev[] = {
>> +	{
>> +		.name	= "adv7343",
>> +		.board_info = {
>> +			I2C_BOARD_INFO("adv7343", 0x2a),
>> +		},
>> +	},
>> +};
>> +
>> +static const char const *vpif_output[] = {
>> +	"Composite",
>> +	"Component",
>> +	"S-Video",
>> +};
>> +
>> +static struct vpif_display_config da850_vpif_display_config = {
>> +	.set_clock	= da850_set_vpif_clock,
>> +	.subdevinfo	= da850_vpif_subdev,
>> +	.subdev_count	= ARRAY_SIZE(da850_vpif_subdev),
>> +	.output		= vpif_output,
>> +	.output_count	= ARRAY_SIZE(vpif_output),
>> +	.card_name	= "DA850/OMAP-L138 Video Display",
>> +};
>> +
>> +#if defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) ||\
>> +		defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY_MODULE)
>> +#define HAS_VPIF_DISPLAY 1
>> +#else
>> +#define HAS_VPIF_DISPLAY 0
>> +#endif
>> +
>> +#if defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) ||\
>> +		defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE_MODULE)
>> +#define HAS_VPIF_CAPTURE 1
>> +#else
>> +#define HAS_VPIF_CAPTURE 0
>> +#endif
>> +
>>  #ifdef CONFIG_DA850_WL12XX
>>  
>>  static void wl12xx_set_power(int index, bool power_on)
>> @@ -1375,6 +1539,37 @@ static __init void da850_evm_init(void)
>>  		pr_warning("da850_evm_init: suspend registration failed: %d\n",
>>  				ret);
>>  
>> +	if (HAS_VPIF_DISPLAY || HAS_VPIF_CAPTURE) {
>> +		ret = da850_register_vpif();
>> +		if (ret)
>> +			pr_warn("da850_evm_init: VPIF setup failed: %d\n",
>> +				   ret);
>> +	}
>> +
>> +	if (HAS_VPIF_CAPTURE) {
>> +		ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
>> +		if (ret)
>> +			pr_warn("da850_evm_init: VPIF capture mux failed:%d\n",
>> +					ret);
>> +
>> +		ret = da850_register_vpif_capture(&da850_vpif_capture_config);
>> +		if (ret)
>> +			pr_warn("da850_evm_init: VPIF capture setup" \
>> +			" failed: %d\n", ret);
> 
> Please don't break print messages.
> 
 Ok.

>> +	}
>> +
>> +	if (HAS_VPIF_DISPLAY) {
>> +		ret = davinci_cfg_reg_list(da850_vpif_display_pins);
>> +		if (ret)
>> +			pr_warn("da850_evm_init : VPIF capture mux failed" \
>> +			": %d\n", ret);
>> +
>> +		ret = da850_register_vpif_display(&da850_vpif_display_config);
>> +		if (ret)
>> +			pr_warn("da850_evm_init: VPIF display setup" \
>> +			" failed: %d\n", ret);
> 
> Same here.
> 
 Ok.

Thx,
--Prabhakar

> Thanks,
> Sekhar
> 



From alanbutty12 at gmail.com  Thu Aug 16 06:36:55 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Thu, 16 Aug 2012 11:36:55 +0100
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ5UF6r2N027nOS6xmJtu21UbDxfzLninCZ7O-A+G3ALgg@mail.gmail.com>
References: <20120815211517.GA15830@lunn.ch>
 <CADhrpJ7+MoKF9qbeh9RBHo3j-m22574pi=cuHfQ9-KeVNX=mzw@mail.gmail.com>
 <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
 <20120815234159.GK22226@titan.lakedaemon.net>
 <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>
 <CADhrpJ5UF6r2N027nOS6xmJtu21UbDxfzLninCZ7O-A+G3ALgg@mail.gmail.com>
Message-ID: <CADhrpJ7geSRc3pow-DQWiA3rZ=f0i2WSws_QuKSDk7uZx1VSRQ@mail.gmail.com>

On 16 August 2012 01:00, alan butler <alanbutty12 at gmail.com> wrote:
> On 16 August 2012 00:52, alan butler <alanbutty12 at gmail.com> wrote:
>> On 16 August 2012 00:41, Jason Cooper <jason at lakedaemon.net> wrote:
>>> On Thu, Aug 16, 2012 at 12:34:46AM +0100, alan butler wrote:
>>>> On 16 August 2012 00:12, alan butler <alanbutty12 at gmail.com> wrote:
>>>> > On 16 August 2012 00:02, alan butler <alanbutty12 at gmail.com> wrote:
>>>> >> On 15 August 2012 23:16, Andrew Lunn <andrew at lunn.ch> wrote:
>>>> >>> On Wed, Aug 15, 2012 at 10:57:27PM +0100, alan butler wrote:
>>>> >>>> On 15 August 2012 22:52, Andrew Lunn <andrew at lunn.ch> wrote:
>>>> >>>> >> That would be great i just need to recreate the patch with those
>>>> >>>> >> changes but i was talking with jason cooper i believe and he said to
>>>> >>>> >> put the buttons for the device in the dts file and im working on that
>>>> >>>> >> but the kernel panics
>>>> >>>> >
>>>> >>>> > Please show us the panic.
>>>> >>>> >
>>>> >>>> >        Andrew
>>>> >>>>
>>>> >>>> i sent it to jason a lil bit earlier but i guess i must of forgotten
>>>> >>>> to cc the list on the last message or 2 but here is the panic again:
>>>> >>>>
>>>> >>>> [    5.976074] Key type dns_resolver registered
>>>> >>>> [    5.981782] Unable to handle kernel NULL pointer dereference at
>>>> >>>> virtual address 00000004
>>>> >>>> [    5.989932] pgd = c0004000
>>>> >>>> [    5.992649] [00000004] *pgd=00000000
>>>> >>>> [    5.996247] Internal error: Oops: 805 [#1] ARM
>>>> >>>> [    6.000707] Modules linked in:
>>>> >>>> [    6.003780] CPU: 0    Not tainted  (3.6.0-rc1-next-20120814 #13)
>>>> >>>> [    6.009822] PC is at gpio_keys_probe+0x110/0x6d4
>>>> >>>
>>>> >>> You might want to scatter some printk() in gpio_keys_probe() and see
>>>> >>> where it panics. It will probably then be clear what is wrong.
>>>> >>>
>>>> >>>       Andrew
>>>> >>
>>>> >> where do i find the gpio_keys_probe() ?
>>>> >
>>>> > i found the gpio_keys_probe() and it seems that it is failing in this
>>>> > piece of code i put a printk() before and after it and it didnt reach
>>>> > the printk after it:
>>>> >
>>>> > if (!pdata) {
>>>> >                 pdata = gpio_keys_get_devtree_pdata(dev);
>>>> >                 if (IS_ERR(pdata))
>>>> >                         return PTR_ERR(pdata);
>>>> >         }
>>>> >
>>>> >         ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
>>>> >                         pdata->nbuttons * sizeof(struct gpio_button_data),
>>>> >                         GFP_KERNEL);
>>>> >         input = input_allocate_device();
>>>> >         if (!ddata || !input) {
>>>> >                 dev_err(dev, "failed to allocate state\n");
>>>> >                 error = -ENOMEM;
>>>> >                 goto fail1;
>>>> >         }
>>>>
>>>> actualy it seems to not be getting past this piece of code in what i
>>>> posted before:
>>>>
>>>> if (!pdata) {
>>>>               pdata = gpio_keys_get_devtree_pdata(dev);
>>>>               if (IS_ERR(pdata))
>>>>                       return PTR_ERR(pdata);
>>>>       }
>>>
>>> That means gpio_keys_get_devtree_pdata() is returning an error.  Have
>>> you tried 'linux,input-type = <0x05>;' ?
>>>
>>> thx,
>>>
>>> Jason.
>>
>> 'inux,input-type = <0x05>' instead of 'linux,code = <...>' in the dts?
>> no i havent tried will give it a try now.
>
> with the buttons setup as follows:
> gpio-keys {
>                 compatible = "gpio-keys";
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>                 iomotb {
>                         label = "OTB Button";
>                         linux,input-type = <133>;
>                         gpios = <&gpio1 3 1>;
>                         debounce-interval = <100>;
>                 };
>                 iomreset {
>                         label = "Reset";
>                         linux,input-type = <0x198>;
>                         gpios = <&gpio0 12 1>;
>                         debounce-interval = <100>;
>                 };
>         };
>
> it errors at the following:
>
> button->gpio = of_get_gpio_flags(pp, 0, &flags);
> button->active_low = flags & OF_GPIO_ACTIVE_LOW;

with the buttons setup like this:

gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		button at 1 {
			label = "Reset Button";
			linux,code = <116>;
			gpios = <&gpio0 12 1>;
		};
		button at 2 {
			label = "Power-on Switch";
			linux,code = <116>;
			gpios = <&gpio0 14 1>;
		};
		button at 3 {
			label = "OTB Switch";
			linux,code = <142>;
			gpios = <&gpio1 3 1>;
		};
	};

the problem seems to be in this comming from this line:

button->gpio = of_get_gpio_flags(pp, 0, &flags);

in the function :

/*
 * Translate OpenFirmware node properties into platform_data
 */
static struct gpio_keys_platform_data * __devinit

of the gpio_keys.c file or whatever that line links to. It does not
know how to deal with some NULL reference as far as i can tell.


From m.szyprowski at samsung.com  Thu Aug 16 06:39:57 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 16 Aug 2012 12:39:57 +0200
Subject: [PATCH v3 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent
 if available
In-Reply-To: <20120816.191358.127675610.hdk@igel.co.jp>
References: <1344246924-32620-1-git-send-email-hdk@igel.co.jp>
 <1344246924-32620-4-git-send-email-hdk@igel.co.jp>
 <012701cd74ac$6a617060$3f245120$%szyprowski@samsung.com>
 <20120816.191358.127675610.hdk@igel.co.jp>
Message-ID: <015b01cd7b9b$8010e2b0$8032a810$%szyprowski@samsung.com>

Hello,

On Thursday, August 16, 2012 12:14 PM Hideki EIRAKU wrote:

> From: Marek Szyprowski <m.szyprowski at samsung.com>
> Subject: RE: [PATCH v3 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent if available
> Date: Tue, 07 Aug 2012 16:53:25 +0200
> 
> > I'm sorry for bringing this issue now, once you have already created v3 of your
> > patches, but similar patch has been already proposed some time ago. It is already
> > processed together with general videobuf2-dma-contig redesign and dma-buf extensions
> > by Tomasz Stanislawski.
> >
> > See post http://thread.gmane.org/gmane.comp.video.dri.devel/70402/focus=49461 and
> > http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/49438
> >
> > It doesn't use conditional code inside videobuf2 allocator and rely entirely on
> > dma-mapping subsystem to provide a working dma_mmap_coherent/writecombine/attrs()
> > function. When it was posted, it relied on the dma-mapping extensions, which now
> > have been finally merged to v3.6-rc1. Now I wonder if there are any architectures,
> > which don't use dma_map_ops based dma-mapping framework, which might use
> > videobuf2-dma-conting module.
> 
> Thank you for telling me about videobuf2-dma-contig and v3.6-rc1.  The
> videobuf2-dma-contig patch I sent is now unnecessary.  So I will
> remove the patch.  I will remove the patch defining
> ARCH_HAS_DMA_MMAP_COHERENT too because the v3.6-rc1 kernel has generic
> dma_mmap_coherent() API for every architecture.

Just to let you know - Tomasz has posted an updated version of the dma-buf/vb2-dma-contig
patches:

http://www.spinics.net/lists/linux-media/msg51768.html

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From will.deacon at arm.com  Thu Aug 16 06:47:48 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:47:48 +0100
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <201208151507.36174.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-24-git-send-email-catalin.marinas@arm.com>
 <201208151507.36174.arnd@arndb.de>
Message-ID: <20120816104748.GI31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 04:07:36PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +const struct user_regset_view *task_user_regset_view(struct task_struct *task)
> > +{
> > +#ifdef CONFIG_AARCH32_EMULATION
> > +	if (test_tsk_thread_flag(task, TIF_32BIT))
> > +		return &user_aarch32_view;
> > +#endif
> > +	return &user_aarch64_view;
> > +}
> 
> Ah, nice. So you support 64 bit debuggers debugging 32 bit processes, right?

That should work if the debugger can deal with it, yes.

> From what I can tell, there is no support for 32 bit processes debugging
> 64 bit ones. Is that something you plan to add in the future, or do you
> consider that out of scope? In either case, a comment would be helpful.

That can't really work because the debugger won't be able to manipulate
child pointers properly without us adding a new ptrace interface (and then,
I still wonder about how feasible it really is). I can add a comment.

> > +long arch_ptrace(struct task_struct *child, long request,
> > +		 unsigned long addr, unsigned long data)
> > +{
> > +	int ret;
> > +	unsigned long *datap = (unsigned long __user *)data;
> > +
> > +	switch (request) {
> > +		case PTRACE_GET_THREAD_AREA:
> > +			ret = put_user(child->thread.tp_value, datap);
> > +			break;
> > +
> > +#ifdef CONFIG_HAVE_HW_BREAKPOINT
> > +		case PTRACE_GETHBPREGS:
> > +			ret = ptrace_gethbpregs(child, addr, datap);
> > +			break;
> > +
> > +		case PTRACE_SETHBPREGS:
> > +			ret = ptrace_sethbpregs(child, addr, datap);
> > +			break;
> > +#endif
> > +
> > +		default:
> > +			ret = ptrace_request(child, request, addr, data);
> > +			break;
> > +	}
> > +
> > +	return ret;
> > +}
> 
> Is there a reaons why these are not regsets but have their own ptrace
> commands? I believe new architectures should generally not add ptrace
> commands any more.

I could probably add some regset wrappers about the hbp accessors (which we
have to keep for the compat ptrace interface). I'll have a think as it might
even make sense to have different regsets for breakpoints and watchpoints.

As for the the tls, is it worth having a regset with only one register?

Will


From jason77.wang at gmail.com  Thu Aug 16 06:47:29 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 18:47:29 +0800
Subject: [PATCH v4 1/3] Input: egalax_ts: get gpio from devicetree node
In-Reply-To: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>

The irq_to_gpio() is old, most platforms use GENERIC_GPIO framework
and don't support this API anymore.

The i.MX6q sabrelite platform equips an egalax touchscreen controller,
and this platform already transfered to GENERIC_GPIO framework, to
support this driver, we use a more generic way to get gpio.

Add a return value checking for waking up the controller in the probe
function, this guarantee only a workable device can pass init.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 drivers/input/touchscreen/egalax_ts.c |   25 ++++++++++++++++++++++---
 1 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/input/touchscreen/egalax_ts.c b/drivers/input/touchscreen/egalax_ts.c
index 70524dd..8516a4e 100644
--- a/drivers/input/touchscreen/egalax_ts.c
+++ b/drivers/input/touchscreen/egalax_ts.c
@@ -28,6 +28,7 @@
 #include <linux/slab.h>
 #include <linux/bitops.h>
 #include <linux/input/mt.h>
+#include <linux/of_gpio.h>
 
 /*
  * Mouse Mode: some panel may configure the controller to mouse mode,
@@ -122,8 +123,15 @@ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
 /* wake up controller by an falling edge of interrupt gpio.  */
 static int egalax_wake_up_device(struct i2c_client *client)
 {
-	int gpio = irq_to_gpio(client->irq);
-	int ret;
+	struct device_node *np = client->dev.of_node;
+	int gpio, ret;
+
+	if (!np)
+		return -ENODEV;
+
+	gpio = of_get_named_gpio(np, "wakeup-gpios", 0);
+	if (!gpio_is_valid(gpio))
+		return -ENODEV;
 
 	ret = gpio_request(gpio, "egalax_irq");
 	if (ret < 0) {
@@ -181,7 +189,12 @@ static int __devinit egalax_ts_probe(struct i2c_client *client,
 	ts->input_dev = input_dev;
 
 	/* controller may be in sleep, wake it up. */
-	egalax_wake_up_device(client);
+	ret = egalax_wake_up_device(client);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed to wake up the controller\n");
+		error = ret;
+		goto err_free_dev;
+	}
 
 	ret = egalax_firmware_version(client);
 	if (ret < 0) {
@@ -274,11 +287,17 @@ static int egalax_ts_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(egalax_ts_pm_ops, egalax_ts_suspend, egalax_ts_resume);
 
+static struct of_device_id egalax_ts_dt_ids[] = {
+	{ .compatible = "eeti,egalax_ts" },
+	{ /* sentinel */ }
+};
+
 static struct i2c_driver egalax_ts_driver = {
 	.driver = {
 		.name	= "egalax_ts",
 		.owner	= THIS_MODULE,
 		.pm	= &egalax_ts_pm_ops,
+		.of_match_table	= egalax_ts_dt_ids,
 	},
 	.id_table	= egalax_ts_id,
 	.probe		= egalax_ts_probe,
-- 
1.7.6



From jason77.wang at gmail.com  Thu Aug 16 06:47:28 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 18:47:28 +0800
Subject: [PATCH v4 0/3] Input: egalax_ts: parse devicetree to get gpio
Message-ID: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>

V4:

add of_match_table in the driver, and change egalax_ts gpio irq type value from
2 to 8 (falling edge to low level) in the dts.

V3:

Although have got Ack-by from driver author in the V2, i have to send
V3 since the driver is changed due to the change of a property name
in the dts.

As Shawn.guo suggested, i renamed property "irq-gpio" to "wakeup-gpios".
The reason is that, firstly the idiom of gpio naming in DT is *-gpios,
even though most of time, it could be just one gpio, secondly as the pin is
accessed as a gpio only in egalax_wake_up_device for waking up the device.

This time i send the patches both to linux-input and linux-arm, 0001 and
0002 belongs to linux-input, while the 0003 belongs to linux-arm.

V2:

Add return value checking for waking up the controller in the probe
function.

V1:

eeti touch screen controller is an external chip for most platforms,
it connect to CPU via i2c bus, and it has a irq request pin need to be
connected to a gpio of the CPU, this irq request pin also act as a
wake up signal for touch screen controller, we need to get this gpio
number and operate it to wake up the controller, the old way to get
gpio is irq_to_gpio(), this API is dying and most platforms don't support
it, we change it to a more generic way to use devcietree.

Hui Wang (3):
  Input: egalax_ts: get gpio from devicetree node
  Input: add devicetree binding note for egalax_ts
  ARM: dts: imx6q-sabrelite: add eeti egalax touchscreen

 .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |   16 ++++++++++++
 arch/arm/boot/dts/imx6q.dtsi                       |    7 +++++
 drivers/input/touchscreen/egalax_ts.c              |   25 +++++++++++++++++--
 4 files changed, 64 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt

-- 
1.7.6



From jason77.wang at gmail.com  Thu Aug 16 06:47:30 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 18:47:30 +0800
Subject: [PATCH v4 2/3] Input: add devicetree binding note for egalax_ts
In-Reply-To: <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>

The egalax_ts driver needs to get the gpio number of the irq pin,
and use this gpio to wake up the controller. So add a note
for this change.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 .../bindings/input/touchscreen/egalax-ts.txt       |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt

diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
new file mode 100644
index 0000000..df70318
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
@@ -0,0 +1,19 @@
+* EETI eGalax Multiple Touch Controller
+
+Required properties:
+- compatible: must be "eeti,egalax_ts"
+- reg: i2c slave address
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: touch controller interrupt
+- wakeup-gpios: the gpio pin to be used for waking up the controller
+  as well as uased as irq pin
+
+Example:
+
+	egalax_ts at 04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <9 2>;
+		wakeup-gpios = <&gpio1 9 0>;
+	};
-- 
1.7.6



From jason77.wang at gmail.com  Thu Aug 16 06:47:31 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 16 Aug 2012 18:47:31 +0800
Subject: [PATCH v4 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1345114051-3052-4-git-send-email-jason77.wang@gmail.com>

i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
touchscreen controller, add it as an i2c slave device in the dts.

Signed-off-by: Hui Wang <jason77.wang at gmail.com>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |   16 ++++++++++++++++
 arch/arm/boot/dts/imx6q.dtsi          |    7 +++++++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..337ec74 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -54,6 +54,7 @@
 							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
 							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
 							   953  0x80000000	/* MX6Q_PAD_GPIO_0__CCM_CLKO */
+							   972  0x10		/* MX6Q_PAD_GPIO_9__GPIO_1_9 */
 							   >;
 					};
 				};
@@ -115,6 +116,21 @@
 					VDDIO-supply = <&reg_3p3v>;
 				};
 			};
+
+			i2c at 021a8000 { /* I2C3 */
+				status = "okay";
+				clock-frequency = <100000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_i2c3_1>;
+
+				egalax_ts at 04 {
+					compatible = "eeti,egalax_ts";
+					reg = <0x04>;
+					interrupt-parent = <&gpio1>;
+					interrupts = <9 8>;
+					wakeup-gpios = <&gpio1 9 0>;
+				};
+			};
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..6f833b3 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -552,6 +552,13 @@
 					};
 				};
 
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <1013 0x4001b8b1	/* MX6Q_PAD_GPIO_5__I2C3_SCL */
+							    1037 0x4001b8b1>;	/* MX6Q_PAD_GPIO_16__I2C3_SDA */
+					};
+				};
+
 				serial2 {
 					pinctrl_serial2_1: serial2grp-1 {
 						fsl,pins = <183 0x1b0b1		/* MX6Q_PAD_EIM_D26__UART2_TXD */
-- 
1.7.6



From will.deacon at arm.com  Thu Aug 16 06:51:34 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:51:34 +0100
Subject: [PATCH v2 25/31] arm64: Performance counters support
In-Reply-To: <201208151511.11612.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-26-git-send-email-catalin.marinas@arm.com>
 <201208151511.11612.arnd@arndb.de>
Message-ID: <20120816105134.GJ31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 04:11:11PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > From: Will Deacon <will.deacon at arm.com>
> > 
> > This patch adds support for the AArch64 performance counters.
> > 
> > Signed-off-by: Will Deacon <will.deacon at arm.com>
> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> > ---
> >  arch/arm64/include/asm/perf_event.h |   22 +
> >  arch/arm64/include/asm/pmu.h        |   82 +++
> >  arch/arm64/kernel/perf_event.c      | 1368 +++++++++++++++++++++++++++++++++++
> >  tools/perf/perf.h                   |    6 +
> 
> Can you explain how AArch64 performance counters differ from the 32
> bit ones? Do they work for AArch32 user space under AArch64 kernels?
> Is it possible to share parts of the implementation with arch/arm?

Perf should work for compat tasks, yes. I'd like to share some of the code
with arch/arm/ and I've started reworking the arch/arm/ stuff to accomodate
this better:

  git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git perf/updates

I'm not sure how well it will fit in drivers/ but I'm certainly willing to
give it a try.

Will


From will.deacon at arm.com  Thu Aug 16 06:57:09 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 11:57:09 +0100
Subject: [PATCH v2 26/31] arm64: Miscellaneous library functions
In-Reply-To: <201208151521.14663.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-27-git-send-email-catalin.marinas@arm.com>
 <201208151521.14663.arnd@arndb.de>
Message-ID: <20120816105709.GK31784@mudshark.cambridge.arm.com>

On Wed, Aug 15, 2012 at 04:21:14PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +
> > +/*
> > + * Use compiler builtins for simple inline operations.
> > + */
> > +static inline unsigned long __ffs(unsigned long word)
> > +{
> > +	return __builtin_ffsl(word) - 1;
> > +}
> > +
> > +static inline int ffs(int x)
> > +{
> > +	return __builtin_ffs(x);
> > +}
> > +
> > +static inline unsigned long __fls(unsigned long word)
> > +{
> > +	return BITS_PER_LONG - 1 - __builtin_clzl(word);
> > +}
> > +
> > +static inline int fls(int x)
> > +{
> > +	return x ? sizeof(x) * BITS_PER_BYTE - __builtin_clz(x) : 0;
> > +}
> 
> These are all great, but I think whether to use them or not should
> depend on the compiler version rather than the architecture in
> general. Do we know a minimum gcc version that supports all of the
> above? Then we could put that code into the generic files.

I imagine that the version of GCC that supports these builtins varies for
each architecture. For aarch64, the compile will always support these
builtins and these particular ones are guaranteed to be inlined.

> If that's not possible, we could still make the implementation
> available for other architectures by moving it to
> 
> asm-generic/bitops/builtin-__ffs.h
> asm-generic/bitops/builtin-ffs.h
> asm-generic/bitops/builtin-__fls.h
> asm-generic/bitops/builtin-fls.h

Yeah, that might be an idea. The architecture can then decide to use them if
it knows they are available and usable.

> > --- /dev/null
> > +++ b/arch/arm64/lib/bitops.c
> > @@ -0,0 +1,25 @@
> > +/*
> > + * Copyright (C) 2012 ARM Limited
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/atomic.h>
> > +
> > +#ifdef CONFIG_SMP
> > +arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
> > +       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
> > +};
> > +#endif
> 
> What?
> 
> I suppose this is a leftover from an earlier version using the
> generic bitops, right?

We currently use the generic atomic bitops (asm-generic/bitops/atomic.h)
which contains:

#  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))

so we have to provide a definition for the array. We have additional patches
containing optimised assembly implementations of the atomic bitops which we
will push later, once we've got some hardware to benchmark with.

Will


From jtzhou at marvell.com  Thu Aug 16 07:59:08 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Thu, 16 Aug 2012 19:59:08 +0800
Subject: [PATCH 1/3] rtc: avoid cpuid checking in pxa-rtc
Message-ID: <1345118348-10255-1-git-send-email-jtzhou@marvell.com>

From: Haojian Zhuang <haojian.zhuang at marvell.com>

pxa-rtc is widely used in pxa27x/pxa3xx/pxa93x/pxa95x. Checking cpuid in
pxa-rtc driver is unnecessary since we assign on-chip device in soc files.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/rtc/rtc-pxa.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8f..a2c3534 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -433,10 +433,7 @@ static struct platform_driver pxa_rtc_driver = {
 
 static int __init pxa_rtc_init(void)
 {
-	if (cpu_is_pxa27x() || cpu_is_pxa3xx())
-		return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
-
-	return -ENODEV;
+	return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
 }
 
 static void __exit pxa_rtc_exit(void)
-- 
1.7.0.4



From jtzhou at marvell.com  Thu Aug 16 07:59:28 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Thu, 16 Aug 2012 19:59:28 +0800
Subject: [PATCH 2/3] rtc: use __devinit instead on pxa-rtc
Message-ID: <1345118368-10409-1-git-send-email-jtzhou@marvell.com>

From: Haojian Zhuang <haojian.zhuang at marvell.com>

Avoid to use __init/__exit on probe()/remove(). Use __devinit/__devexit
instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/rtc/rtc-pxa.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index a2c3534..3a060d2 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -308,7 +308,7 @@ static const struct rtc_class_ops pxa_rtc_ops = {
 	.proc = pxa_rtc_proc,
 };
 
-static int __init pxa_rtc_probe(struct platform_device *pdev)
+static int __devinit pxa_rtc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct pxa_rtc *pxa_rtc;
@@ -381,7 +381,7 @@ err_map:
 	return ret;
 }
 
-static int __exit pxa_rtc_remove(struct platform_device *pdev)
+static int __devexit pxa_rtc_remove(struct platform_device *pdev)
 {
 	struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
 
@@ -422,7 +422,8 @@ static const struct dev_pm_ops pxa_rtc_pm_ops = {
 #endif
 
 static struct platform_driver pxa_rtc_driver = {
-	.remove		= __exit_p(pxa_rtc_remove),
+	.probe		= pxa_rtc_probe,
+	.remove		= __devexit_p(pxa_rtc_remove),
 	.driver		= {
 		.name	= "pxa-rtc",
 #ifdef CONFIG_PM
@@ -433,7 +434,7 @@ static struct platform_driver pxa_rtc_driver = {
 
 static int __init pxa_rtc_init(void)
 {
-	return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
+	return platform_driver_register(&pxa_rtc_driver);
 }
 
 static void __exit pxa_rtc_exit(void)
-- 
1.7.0.4



From jtzhou at marvell.com  Thu Aug 16 07:59:51 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Thu, 16 Aug 2012 19:59:51 +0800
Subject: [PATCH 3/3] rtc: pxa: convert to use module_platform_driver()
Message-ID: <1345118391-10577-1-git-send-email-jtzhou@marvell.com>

Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
---
 drivers/rtc/rtc-pxa.c |   13 +------------
 1 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 3a060d2..b2a1c7f 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -432,18 +432,7 @@ static struct platform_driver pxa_rtc_driver = {
 	},
 };
 
-static int __init pxa_rtc_init(void)
-{
-	return platform_driver_register(&pxa_rtc_driver);
-}
-
-static void __exit pxa_rtc_exit(void)
-{
-	platform_driver_unregister(&pxa_rtc_driver);
-}
-
-module_init(pxa_rtc_init);
-module_exit(pxa_rtc_exit);
+module_platform_driver(pxa_rtc_driver);
 
 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik at free.fr>");
 MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
-- 
1.7.0.4



From peter.ujfalusi at ti.com  Thu Aug 16 08:13:12 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 15:13:12 +0300
Subject: [PATCH v2 0/3] MFD/GPIO: Add twl6040 GPO driver
Message-ID: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v1:
- Removed the ti,use-gpo property from DT bindings
- Register the GPO driver if we booted with DT blob or in legacy if the pdata
  for the GPO driver is present
- DT binding Documentation update

The Documentation update has reference to the twl6040.dtsi file which will be
created to hold the common/static properties for the twl6040.
To avoid cross tree merge issues later I have only included the Documentation
update to this series and I will send the actual .dtsi/.dts changes via
linux-omap. If this is not a problem.

The dependencies for this series are in mainline and I think this series can
go via GPIO if Samuel agrees with the changes.

Intro mail from v1:

The following series adds support for the GPO (General Purpose Output) on the
twl6040/41 audio chip.
The series has been tested on SDP4430, compile tested for x86_64 and x86_32 bit
to be sure it does not introduce build breakage.

Regards,
Peter
---
Peter Ujfalusi (3):
  mfd: twl6040: Fix GPO mask
  mfd: twl6040: Add twl6040-gpio child
  gpio: Add basic support for TWL6040 GPOs

 Documentation/devicetree/bindings/mfd/twl6040.txt |    9 +-
 drivers/gpio/Kconfig                              |    7 +
 drivers/gpio/Makefile                             |    1 +
 drivers/gpio/gpio-twl6040.c                       |  137 +++++++++++++++++++++
 drivers/mfd/twl6040-core.c                        |   15 +++
 include/linux/mfd/twl6040.h                       |   11 ++-
 6 files changed, 175 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpio/gpio-twl6040.c

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 08:13:13 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 15:13:13 +0300
Subject: [PATCH v2 1/3] mfd: twl6040: Fix GPO mask
In-Reply-To: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345119195-7490-2-git-send-email-peter.ujfalusi@ti.com>

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 include/linux/mfd/twl6040.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index eaad49f..269b706 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -143,7 +143,7 @@
 
 #define TWL6040_GPO1			0x01
 #define TWL6040_GPO2			0x02
-#define TWL6040_GPO3			0x03
+#define TWL6040_GPO3			0x04
 
 /* ACCCTL (0x2D) fields */
 
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 08:13:15 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 15:13:15 +0300
Subject: [PATCH v2 3/3] gpio: Add basic support for TWL6040 GPOs
In-Reply-To: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345119195-7490-4-git-send-email-peter.ujfalusi@ti.com>

TWL6040 provides GPO lines to be used for controlling external devices.The number
of lines different between versions: twl6040 have 3 GPO while TWL6041 have 1.

Signed-off-by: Sergio Aguirre <saaguirre at ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/Kconfig        |    7 ++
 drivers/gpio/Makefile       |    1 +
 drivers/gpio/gpio-twl6040.c |  137 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 145 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpio/gpio-twl6040.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..f74633e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -402,6 +402,13 @@ config GPIO_TWL4030
 	  Say yes here to access the GPIO signals of various multi-function
 	  power management chips from Texas Instruments.
 
+config GPIO_TWL6040
+	tristate "TWL6040 GPO"
+	depends on TWL6040_CORE
+	help
+	  Say yes here to access the GPO signals of twl6040
+	  audio chip from Texas Instruments.
+
 config GPIO_WM831X
 	tristate "WM831x GPIOs"
 	depends on MFD_WM831X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..f857b46 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_GPIO_TPS6586X)	+= gpio-tps6586x.o
 obj-$(CONFIG_GPIO_TPS65910)	+= gpio-tps65910.o
 obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
+obj-$(CONFIG_GPIO_TWL6040)	+= gpio-twl6040.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o
diff --git a/drivers/gpio/gpio-twl6040.c b/drivers/gpio/gpio-twl6040.c
new file mode 100644
index 0000000..dd58e8b
--- /dev/null
+++ b/drivers/gpio/gpio-twl6040.c
@@ -0,0 +1,137 @@
+/*
+ * Access to GPOs on TWL6040 chip
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Authors:
+ *	Sergio Aguirre <saaguirre at ti.com>
+ *	Peter Ujfalusi <peter.ujfalusi at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kthread.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+
+#include <linux/mfd/twl6040.h>
+
+static struct gpio_chip twl6040gpo_chip;
+
+static int twl6040gpo_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct twl6040 *twl6040 = dev_get_drvdata(chip->dev->parent);
+	int ret = 0;
+
+	ret = twl6040_reg_read(twl6040, TWL6040_REG_GPOCTL);
+	if (ret < 0)
+		return ret;
+
+	return (ret >> offset) & 1;
+}
+
+static int twl6040gpo_direction_out(struct gpio_chip *chip, unsigned offset,
+				    int value)
+{
+	/* This only drives GPOs, and can't change direction */
+	return 0;
+}
+
+static void twl6040gpo_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	struct twl6040 *twl6040 = dev_get_drvdata(chip->dev->parent);
+	int ret;
+	u8 gpoctl;
+
+	ret = twl6040_reg_read(twl6040, TWL6040_REG_GPOCTL);
+	if (ret < 0)
+		return;
+
+	if (value)
+		gpoctl = ret | (1 << offset);
+	else
+		gpoctl = ret & ~(1 << offset);
+
+	twl6040_reg_write(twl6040, TWL6040_REG_GPOCTL, gpoctl);
+}
+
+static struct gpio_chip twl6040gpo_chip = {
+	.label			= "twl6040",
+	.owner			= THIS_MODULE,
+	.get			= twl6040gpo_get,
+	.direction_output	= twl6040gpo_direction_out,
+	.set			= twl6040gpo_set,
+	.can_sleep		= 1,
+};
+
+/*----------------------------------------------------------------------*/
+
+static int __devinit gpo_twl6040_probe(struct platform_device *pdev)
+{
+	struct twl6040_gpo_data *pdata = pdev->dev.platform_data;
+	struct device *twl6040_core_dev = pdev->dev.parent;
+	struct twl6040 *twl6040 = dev_get_drvdata(twl6040_core_dev);
+	int ret;
+
+	if (pdata)
+		twl6040gpo_chip.base = pdata->gpio_base;
+	else
+		twl6040gpo_chip.base = -1;
+
+	if (twl6040_get_revid(twl6040) < TWL6041_REV_ES2_0)
+		twl6040gpo_chip.ngpio = 3; /* twl6040 have 3 GPO */
+	else
+		twl6040gpo_chip.ngpio = 1; /* twl6041 have 1 GPO */
+
+	twl6040gpo_chip.dev = &pdev->dev;
+#ifdef CONFIG_OF_GPIO
+	twl6040gpo_chip.of_node = twl6040_core_dev->of_node;
+#endif
+
+	ret = gpiochip_add(&twl6040gpo_chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
+		twl6040gpo_chip.ngpio = 0;
+	}
+
+	return ret;
+}
+
+static int __devexit gpo_twl6040_remove(struct platform_device *pdev)
+{
+	return gpiochip_remove(&twl6040gpo_chip);
+}
+
+/* Note:  this hardware lives inside an I2C-based multi-function device. */
+MODULE_ALIAS("platform:twl6040-gpo");
+
+static struct platform_driver gpo_twl6040_driver = {
+	.driver = {
+		.name	= "twl6040-gpo",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= gpo_twl6040_probe,
+	.remove		= gpo_twl6040_remove,
+};
+
+module_platform_driver(gpo_twl6040_driver);
+
+MODULE_AUTHOR("Texas Instruments, Inc.");
+MODULE_DESCRIPTION("GPO interface for TWL6040");
+MODULE_LICENSE("GPL");
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 08:13:14 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 15:13:14 +0300
Subject: [PATCH v2 2/3] mfd: twl6040: Add twl6040-gpio child
In-Reply-To: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345119195-7490-3-git-send-email-peter.ujfalusi@ti.com>

Add needed platform data structure and code to be able to load
the GPO child of twl6040.
Update the devicetree binding documentation at the same time.

Signed-off-by: Sergio Aguirre <saaguirre at ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 Documentation/devicetree/bindings/mfd/twl6040.txt |    9 ++++++---
 drivers/mfd/twl6040-core.c                        |   15 +++++++++++++++
 include/linux/mfd/twl6040.h                       |    9 ++++++++-
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt
index c855240..0f5dd70 100644
--- a/Documentation/devicetree/bindings/mfd/twl6040.txt
+++ b/Documentation/devicetree/bindings/mfd/twl6040.txt
@@ -1,7 +1,7 @@
 Texas Instruments TWL6040 family
 
-The TWL6040s are 8-channel high quality low-power audio codecs providing audio
-and vibra functionality on OMAP4+ platforms.
+The TWL6040s are 8-channel high quality low-power audio codecs providing audio,
+vibra and GPO functionality on OMAP4+ platforms.
 They are connected ot the host processor via i2c for commands, McPDM for audio
 data and commands.
 
@@ -10,6 +10,8 @@ Required properties:
 - reg: must be 0x4b for i2c address
 - interrupts: twl6040 has one interrupt line connecteded to the main SoC
 - interrupt-parent: The parent interrupt controller
+- gpio-controller:
+- #gpio-cells = <1>: twl6040 provides GPO lines.
 - twl6040,audpwron-gpio: Power on GPIO line for the twl6040
 
 - vio-supply: Regulator for the twl6040 VIO supply
@@ -37,7 +39,6 @@ Example:
 &i2c1 {
 	twl6040: twl at 4b {
 		compatible = "ti,twl6040";
-		reg = <0x4b>;
 
 		interrupts = <0 119 4>;
 		interrupt-parent = <&gic>;
@@ -60,3 +61,5 @@ Example:
 		};
 	};
 };
+
+/include/ "twl6040.dtsi"
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
index b0fad0f..413df8e 100644
--- a/drivers/mfd/twl6040-core.c
+++ b/drivers/mfd/twl6040-core.c
@@ -631,6 +631,21 @@ static int __devinit twl6040_probe(struct i2c_client *client,
 		children++;
 	}
 
+	/*
+	 * Enable the GPO driver in the following cases:
+	 * DT booted kernel or legacy boot with valid gpo platform_data
+	 */
+	if (!pdata || (pdata && pdata->gpo)) {
+		cell = &twl6040->cells[children];
+		cell->name = "twl6040-gpo";
+
+		if (pdata) {
+			cell->platform_data = pdata->gpo;
+			cell->pdata_size = sizeof(*pdata->gpo);
+		}
+		children++;
+	}
+
 	ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
 			      NULL, 0);
 	if (ret)
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 269b706..8991532 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -158,7 +158,7 @@
 #define TWL6040_VIBROCDET		0x20
 #define TWL6040_TSHUTDET                0x40
 
-#define TWL6040_CELLS			2
+#define TWL6040_CELLS			3
 
 #define TWL6040_REV_ES1_0		0x00
 #define TWL6040_REV_ES1_1		0x01 /* Rev ES1.1 and ES1.2 */
@@ -176,6 +176,8 @@
 #define TWL6040_SYSCLK_SEL_LPPLL	0
 #define TWL6040_SYSCLK_SEL_HPPLL	1
 
+#define TWL6040_GPO_MAX	3
+
 struct twl6040_codec_data {
 	u16 hs_left_step;
 	u16 hs_right_step;
@@ -192,12 +194,17 @@ struct twl6040_vibra_data {
 	int vddvibr_uV;			/* VDDVIBR volt, set 0 for fixed reg */
 };
 
+struct twl6040_gpo_data {
+	int gpio_base;
+};
+
 struct twl6040_platform_data {
 	int audpwron_gpio;	/* audio power-on gpio */
 	unsigned int irq_base;
 
 	struct twl6040_codec_data *codec;
 	struct twl6040_vibra_data *vibra;
+	struct twl6040_gpo_data *gpo;
 };
 
 struct regmap;
-- 
1.7.8.6



From thierry.reding at avionic-design.de  Thu Aug 16 08:15:13 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 16 Aug 2012 14:15:13 +0200
Subject: [PATCH v3 10/10] ARM: tegra: pcie: Add device tree support
In-Reply-To: <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-11-git-send-email-thierry.reding@avionic-design.de>
 <20120814201215.GA10542@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6Awbx9-DWM3V02HUg7Xv4tWAhcLO7UKuT_0uXbpZ+nKw@mail.gmail.com>
 <20120815063718.GA15665@avionic-0098.mockup.avionic-design.de>
 <CAErSpo7Y9ADYHwZMjQjDwd7m8jtwgcxsE-NE_K5X_Z+PuV=C4w@mail.gmail.com>
Message-ID: <20120816121513.GA10175@avionic-0098.adnet.avionic-design.de>

On Wed, Aug 15, 2012 at 05:18:04AM -0700, Bjorn Helgaas wrote:
> On Tue, Aug 14, 2012 at 11:37 PM, Thierry Reding
> <thierry.reding at avionic-design.de> wrote:
> > On Tue, Aug 14, 2012 at 04:50:26PM -0700, Bjorn Helgaas wrote:
> >> On Tue, Aug 14, 2012 at 1:12 PM, Thierry Reding
> >> <thierry.reding at avionic-design.de> wrote:
> >> > On Thu, Jul 26, 2012 at 09:55:12PM +0200, Thierry Reding wrote:
> >> >> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> >> >> index a094c97..c886dff 100644
> >> >> --- a/arch/arm/boot/dts/tegra20.dtsi
> >> >> +++ b/arch/arm/boot/dts/tegra20.dtsi
> >> >> @@ -199,6 +199,68 @@
> >> >>               #size-cells = <0>;
> >> >>       };
> >> >>
> >> >> +     pcie-controller {
> >> >> +             compatible = "nvidia,tegra20-pcie";
> >> >> +             reg = <0x80003000 0x00000800   /* PADS registers */
> >> >> +                    0x80003800 0x00000200   /* AFI registers */
> >> >> +                    0x81000000 0x01000000   /* configuration space */
> >> >> +                    0x90000000 0x10000000>; /* extended configuration space */
> >> >> +             interrupts = <0 98 0x04   /* controller interrupt */
> >> >> +                           0 99 0x04>; /* MSI interrupt */
> >> >> +             status = "disabled";
> >> >> +
> >> >> +             ranges = <0 0 0  0x80000000 0x00001000   /* root port 0 */
> >> >> +                       0 1 0  0x81000000 0x00800000   /* port 0 config space */
> >> >> +                       0 2 0  0x90000000 0x08000000   /* port 0 ext config space */
> >> >> +                       0 3 0  0x82000000 0x00010000   /* port 0 downstream I/O */
> >> >> +                       0 4 0  0xa0000000 0x08000000   /* port 0 non-prefetchable memory */
> >> >> +                       0 5 0  0xb0000000 0x08000000   /* port 0 prefetchable memory */
> >> >> +
> >> >> +                       1 0 0  0x80001000 0x00001000   /* root port 1 */
> >> >> +                       1 1 0  0x81800000 0x00800000   /* port 1 config space */
> >> >> +                       1 2 0  0x98000000 0x08000000   /* port 1 ext config space */
> >> >> +                       1 3 0  0x82010000 0x00010000   /* port 1 downstream I/O */
> >> >> +                       1 4 0  0xa8000000 0x08000000   /* port 1 non-prefetchable memory */
> >> >> +                       1 5 0  0xb8000000 0x08000000>; /* port 1 prefetchable memory */
> >> >
> >> > I've been thinking about this some more. The translations for both the
> >> > regular and extended configuration spaces are configured in the top-
> >> > level PCIe controller. It is therefore wrong how they are passed to the
> >> > PCI host bridges via the ranges property.
> >> >
> >> > I remember Mitch saying that it should be passed down to the children
> >> > because it is partitioned among them, but since the layout is compatible
> >> > with ECAM, the partitioning isn't as simple as what's in the tree. In
> >> > fact the partitions will be dependent on the number of devices attached
> >> > to the host bridges.
> >>
> >> I don't understand this last bit about the number of devices attached
> >> to the host bridges.  Logically, the host bridge has a bus number
> >> aperture that you can know up front, even before you know anything
> >> about what devices are below it.  On x86, for example, the ACPI _CRS
> >> method has something like "[bus 00-7f]" in it, which means that any
> >> buses in that range are below this bridge.  That doesn't tell us
> >> anything about which buses actually have devices on them, of course;
> >> it's just analogous to the secondary and subordinate bus number
> >> registers in a P2P bridge.
> >
> > That's one of the issues I still need to take care of. Currently no bus
> > resource is attached to the individual bridges (nor the PCI controller
> > for that matter), so the PCI core will assign them dynamically.
> 
> So your PCI controller driver knows how to program the controller bus
> number aperture?  Sometimes people start by assuming that two host
> bridges both have [bus 00-ff] apertures, then they enumerate below the
> first and adjust the bus number apertures based on what they found.
> For example, if they found buses 00-12 behind the first bridge, they
> make the apertures [bus 00-12] for the first bridge and [bus 13-ff]
> for the second.  That might be the case, depending on what firmware
> set up, but it seems like a dubious way to do it, and of course it
> precludes a lot of hot-plug scenarios.
> 
> > If this
> > range is known at boot time we could assign ECAM ranges based on the bus
> > numbers. Standard ECAM ranges, that is. On Tegra this won't work because
> > as Stephen mentioned in a previous mail, the bus field is not the top
> > field in the ECAM addresses. Basically what you have is this:
> >
> >         [27:24] upper 4 bits of the register address for extended
> >                 configuration space
> >         [23:16] bus number
> >         [15:11] device number
> >         [10: 8] device function
> >         [ 8: 0] register
> >
> > So the ECAM space cannot be partitioned by bus number.
> 
> Ah, OK, so definitely not standard PCIe ECAM.

I had an idea about how we could maybe implement a generic ECAM
mechanism that provides for this kind of mapping as well. Basically,
every mechanism that can be covered by such an implementation would in
one way or another specify the above five fields, so how about designing
it in a way that the driver could define the fields that encode the
information, so for Tegra, something along these lines:

	struct pci_ecam_map pci_ecam_tegra = {
		.register = {  0,  7 },
		.extended = { 24, 27 },
		.function = {  8, 10 },
		.device   = { 11, 15 },
		.bus      = { 16, 23 },
	}

For standard ECAM, something like this:

	struct pci_ecam_map pci_ecam_standard = {
		.register = {  0,  7 },
		.extended = {  8, 11 },
		.function = { 12, 14 },
		.device   = { 15, 19 },
		.bus      = { 20, 27 },
	};

Thierry
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From linus.walleij at linaro.org  Thu Aug 16 08:15:17 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:15:17 +0200
Subject: [PATCH 0/6] Integrator devicetree support
Message-ID: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>

This is a patch set for devicetree on the Integrator/AP and
Integrator/CP I've been cooking. I did some stepwise development
in recent kernels moving to sparse IRQs, per-system clock
source then common clk. Now we can do single zImage and
also devicetree on this platform, so this is a first patch
set.

In case you're wondering why, take down your Torvalds
autobiography and read the title. It was also a bit of
learning exercise, plus it's fun to run devicetree on this
ARMv4 system.

This patch set moves all the non-DT platform code into
#ifndef CONFIG_OF sections for clarity. The plan is to
delete them after deprecation.

Remaining roadblocks to deleting non-DT code altogether.

- Uncertain about how to do the fpga-irq DT binding so
  please review closely.

- The Integrator/AP ARM core tiles have add-on logic modules
  called Integrator/IM-PD1 with a load of PrimeCells and
  stuff. These spawn off a special bus called "lm" in
  arch/arm/mach-integrator/lm.c, and the core module support
  is in impd1.c. It'd probably be pretty easy to create
  device tree bindings for these, but I have no such module
  and no clue on where to get one. Is anyone actually using
  it? Russell?

- The special PCI adapter in the Integrator has to be DT:ed,
  but AFAICT there is still a problem with how to represent
  these things in DT. Any hints/examples, Arnd, Rob?
  arch/arm/mach-integrator/pci_v3.c

Yours,
Linus Walleij

Linus Walleij (6):
  ARM: integrator: call common init function from machine
  ARM: integrator: check PL010 device name rather than base address
  ARM: plat-versatile: add DT support to FPGA IRQ controller
  ARM: integrator: initial device tree support
  ARM: integrator: convert AMBA devices to device tree
  ARM: integrator: convert platform devices to Device Tree

 Documentation/devicetree/bindings/arm/arm-boards   |  12 +
 .../devicetree/bindings/arm/versatile-fpga-irq.txt |  35 +++
 arch/arm/boot/dts/integratorap.dts                 |  78 ++++++
 arch/arm/boot/dts/integratorcp.dts                 | 122 +++++++++
 arch/arm/mach-integrator/common.h                  |   3 +
 arch/arm/mach-integrator/core.c                    |  14 +-
 arch/arm/mach-integrator/integrator_ap.c           | 214 ++++++++++-----
 arch/arm/mach-integrator/integrator_cp.c           | 296 +++++++++++++--------
 arch/arm/plat-versatile/fpga-irq.c                 |  41 +++
 arch/arm/plat-versatile/include/plat/fpga-irq.h    |   2 +
 10 files changed, 640 insertions(+), 177 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
 create mode 100644 arch/arm/boot/dts/integratorap.dts
 create mode 100644 arch/arm/boot/dts/integratorcp.dts

-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:15:39 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:15:39 +0200
Subject: [PATCH 1/6] ARM: integrator: call common init function from machine
Message-ID: <1345119339-22638-1-git-send-email-linus.walleij@linaro.org>

There is currently a common integrator_init() function set up
to be called from an arch_initcall(). The problem is that it is
using machine_is_integrator() which is not working with device
tree, let's call this from respective machine initilization
function and add a parameter to tell whether it's the
Integrator/AP or Integrator/CP instead.

There are still machine_is*() calls in the Integrator
machines directory, but this one needs to be fixed lest we
don't even get a UART console on the Integrator/AP after a
Device Tree boot.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-integrator/common.h        | 1 +
 arch/arm/mach-integrator/core.c          | 6 ++----
 arch/arm/mach-integrator/integrator_ap.c | 2 ++
 arch/arm/mach-integrator/integrator_cp.c | 1 +
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 899561d..c4338e2 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,4 @@
 void integrator_init_early(void);
+int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 3fa6c51..5ba4bc8 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -61,7 +61,7 @@ static struct amba_device *amba_devs[] __initdata = {
 	&kmi1_device,
 };
 
-static int __init integrator_init(void)
+int __init integrator_init(bool is_cp)
 {
 	int i;
 
@@ -70,7 +70,7 @@ static int __init integrator_init(void)
 	 * hard-code them. The Integator/CP and forward have proper cell IDs.
 	 * Else we leave them undefined to the bus driver can autoprobe them.
 	 */
-	if (machine_is_integrator()) {
+	if (!is_cp) {
 		rtc_device.periphid	= 0x00041030;
 		uart0_device.periphid	= 0x00041010;
 		uart1_device.periphid	= 0x00041010;
@@ -86,8 +86,6 @@ static int __init integrator_init(void)
 	return 0;
 }
 
-arch_initcall(integrator_init);
-
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
  * bits in the following SC_CTRLS register bits:
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3b22675..ff966d8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -312,6 +312,8 @@ static void __init ap_init(void)
 
 		lm_device_register(lmdev);
 	}
+
+	integrator_init(false);
 }
 
 /*
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 82d5c83..2b40bc1 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -366,6 +366,7 @@ static void __init intcp_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
+	integrator_init(true);
 }
 
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:15:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:15:49 +0200
Subject: [PATCH 2/6] ARM: integrator: check PL010 device name rather than base
 address
Message-ID: <1345119349-22670-1-git-send-email-linus.walleij@linaro.org>

In the PL010 UART callback a comparison against the base address is
done to figure out which UART is doing the callback. This does not
play well with device tree, so let's check the dev_name() of the
device instead.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-integrator/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 5ba4bc8..67ea181 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -100,7 +100,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
 {
 	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 
-	if (dev == &uart0_device) {
+	if (!strcmp(dev_name(&dev->dev), "uart0")) {
 		rts_mask = 1 << 4;
 		dtr_mask = 1 << 5;
 	} else {
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:15:57 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:15:57 +0200
Subject: [PATCH 3/6] ARM: plat-versatile: add DT support to FPGA IRQ controller
Message-ID: <1345119357-22702-1-git-send-email-linus.walleij@linaro.org>

This adds Device Tree probing support to the Versatile FPGA
IRQ controller.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 .../devicetree/bindings/arm/versatile-fpga-irq.txt | 35 ++++++++++++++++++
 arch/arm/plat-versatile/fpga-irq.c                 | 41 ++++++++++++++++++++++
 arch/arm/plat-versatile/include/plat/fpga-irq.h    |  2 ++
 3 files changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt

diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
new file mode 100644
index 0000000..d20242a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
@@ -0,0 +1,35 @@
+* ARM Versatile FPGA interrupt controller
+
+One or more FPGA IRQ controllers can be synthesized in an ARM reference board
+such as the Integrator or Versatile family. The output of these different
+controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
+instance can handle up to 32 interrupts.
+
+Required properties:
+- compatible: "arm,versatile-fpga-irq"
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
+  as the FPGA IRQ controller has no configuration options for interrupt
+  sources.  The cell is a u32 and defines the interrupt number.
+- reg: The register bank for the FPGA interrupt controller.
+- irq-start: the u32 hardware IRQ number of the first interrupt handled by
+  this FPGA IRQ instance - since there may be many FPGA IRQ controller
+  instances, each will have its unique hardware offset number.
+- clear-mask: a u32 number representing the mask written to clear all IRQs
+  on the controller at boot for example.
+- valid-mask: a u32 number representing a bit mask determining which of
+  the interrupts are valid. Unconnected/unused lines are set to 0, and
+  the system till not make it possible for devices to request these
+  interrupts.
+
+Example:
+
+pic: pic at 14000000 {
+        compatible = "arm,versatile-fpga-irq";
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        reg = <0x14000000 0x100>;
+        irq-start = <1>;
+        clear-mask = <0xffffffff>;
+        valid-mask = <0x003fffff>;
+};
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 6e70d03..379ff53 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -5,6 +5,8 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -14,6 +16,13 @@
 #define IRQ_RAW_STATUS		0x04
 #define IRQ_ENABLE_SET		0x08
 #define IRQ_ENABLE_CLEAR	0x0c
+#define INT_SOFT_SET		0x10
+#define INT_SOFT_CLEAR		0x14
+#define FIQ_STATUS		0x20
+#define FIQ_RAW_STATUS		0x24
+#define FIQ_ENABLE		0x28
+#define FIQ_ENABLE_SET		0x28
+#define FIQ_ENABLE_CLEAR	0x2C
 
 /**
  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
@@ -156,3 +165,35 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
 
 	fpga_irq_id++;
 }
+
+#ifdef CONFIG_OF
+int __init fpga_irq_of_init(struct device_node *node,
+			    struct device_node *parent)
+{
+	void __iomem *base;
+	u32 irq_start;
+	u32 clear_mask;
+	u32 valid_mask;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	base = of_iomap(node, 0);
+	WARN(!base, "unable to map fpga irq registers\n");
+
+	if (of_property_read_u32(node, "irq-start", &irq_start))
+		irq_start = 0;
+
+	if (of_property_read_u32(node, "clear-mask", &clear_mask))
+		clear_mask = 0;
+
+	if (of_property_read_u32(node, "valid-mask", &valid_mask))
+		valid_mask = 0;
+
+	writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+	writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+	fpga_irq_init(base, node->name, irq_start, -1, valid_mask, node);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 91bcfb6..1fac965 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -7,5 +7,7 @@ struct pt_regs;
 void fpga_handle_irq(struct pt_regs *regs);
 void fpga_irq_init(void __iomem *, const char *, int, int, u32,
 		struct device_node *node);
+int fpga_irq_of_init(struct device_node *node,
+		     struct device_node *parent);
 
 #endif
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:16:04 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:16:04 +0200
Subject: [PATCH 4/6] ARM: integrator: initial device tree support
Message-ID: <1345119364-22742-1-git-send-email-linus.walleij@linaro.org>

This is initial device tree support for the ARM Integrator family,
we create a very basic device tree, #ifdef out the non-DT machines
when compiling for device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 Documentation/devicetree/bindings/arm/arm-boards |  12 +++
 arch/arm/boot/dts/integratorap.dts               |  26 ++++++
 arch/arm/boot/dts/integratorcp.dts               |  46 ++++++++++
 arch/arm/mach-integrator/integrator_ap.c         |  77 ++++++++++++----
 arch/arm/mach-integrator/integrator_cp.c         | 112 ++++++++++++++++-------
 5 files changed, 221 insertions(+), 52 deletions(-)
 create mode 100644 arch/arm/boot/dts/integratorap.dts
 create mode 100644 arch/arm/boot/dts/integratorcp.dts

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 91f2614..670e80e 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -1,3 +1,15 @@
+ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
+-----------------------------------------------------------------------------
+ARM's oldest Linux-supported platform with connectors for different core
+tiles of ARMv4, ARMv5 and ARMv6 type.
+
+Required properties (in root node):
+	compatible = "arm,integrator-ap";  /* Application Platform */
+	compatible = "arm,integrator-cp";  /* Compact Platform */
+
+FPGA type interrupt controllers, see the fpga-irq binding doc.
+
+
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
 ARM's development hardware platform with connectors for customizable
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 0000000..a40d1ec0
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,26 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "ARM Integrator/AP";
+	compatible = "arm,integrator-ap";
+	ranges;
+
+	chosen {
+		bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+	};
+
+	pic: pic at 14000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x14000000 0x100>;
+		irq-start = <1>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x003fffff>;
+	};
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 0000000..b6ca10f
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,46 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "ARM Integrator/CP";
+	compatible = "arm,integrator-cp";
+	ranges;
+
+	chosen {
+		bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+	};
+
+	pic: pic at 14000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x14000000 0x100>;
+		irq-start = <1>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x1fc003ff>;
+	};
+
+	cic: cic at 10000040 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x10000040 0x100>;
+		irq-start = <32>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x00000007>;
+	};
+
+	sic: sic at ca000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0xca000000 0x100>;
+		irq-start = <35>;
+		clear-mask = <0x00000fff>;
+		valid-mask = <0x00000fff>;
+	};
+};
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index ff966d8..58b0a58 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -34,6 +34,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -161,23 +162,6 @@ static void __init ap_map_io(void)
 	vga_base = PCI_MEMORY_VADDR;
 }
 
-#define INTEGRATOR_SC_VALID_INT	0x003fffff
-
-static void __init ap_init_irq(void)
-{
-	/* Disable all interrupts initially. */
-	/* Do the core module ones */
-	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-	/* do the header card stuff next */
-	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-		-1, INTEGRATOR_SC_VALID_INT, NULL);
-	integrator_clk_init(false);
-}
-
 #ifdef CONFIG_PM
 static unsigned long ic_irq_enable;
 
@@ -473,6 +457,63 @@ static struct sys_timer ap_timer = {
 	.init		= ap_init_timer,
 };
 
+#ifdef CONFIG_OF
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init ap_init_irq_of(void)
+{
+	/* disable core module IRQs */
+	writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(false);
+}
+
+static const char * ap_dt_board_compat[] = {
+	"arm,integrator-ap",
+	NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= ap_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
+	.init_early	= ap_init_early,
+	.init_irq	= ap_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &ap_timer,
+	.init_machine	= ap_init,
+	.restart	= integrator_restart,
+	.dt_compat      = ap_dt_board_compat,
+MACHINE_END
+
+#else
+
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+
+#define INTEGRATOR_SC_VALID_INT	0x003fffff
+
+static void __init ap_init_irq(void)
+{
+	/* Disable all interrupts initially. */
+	/* Do the core module ones */
+	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+
+	/* do the header card stuff next */
+	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+		-1, INTEGRATOR_SC_VALID_INT, NULL);
+	integrator_clk_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
@@ -486,3 +527,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	.init_machine	= ap_init,
 	.restart	= integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 2b40bc1..0f6dc99 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,6 +23,7 @@
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -53,10 +54,6 @@
 
 #define INTCP_PA_CLCD_BASE		0xc0000000
 
-#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
-
 #define INTCP_ETH_SIZE			0x10
 
 #define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
@@ -143,37 +140,6 @@ static void __init intcp_map_io(void)
 	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
 
-static void __init intcp_init_irq(void)
-{
-	u32 pic_mask, cic_mask, sic_mask;
-
-	/* These masks are for the HW IRQ registers */
-	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-	pic_mask |= (~((~0u) << (29 - 22))) << 22;
-	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-
-	/*
-	 * Disable all interrupt sources
-	 */
-	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-
-	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-		      -1, pic_mask, NULL);
-
-	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-		      -1, cic_mask, NULL);
-
-	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-		      IRQ_CP_CPPLDINT, sic_mask, NULL);
-	integrator_clk_init(true);
-}
-
 /*
  * Flash handling.
  */
@@ -387,6 +353,80 @@ static struct sys_timer cp_timer = {
 	.init		= intcp_timer_init,
 };
 
+#ifdef CONFIG_OF
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init intcp_init_irq_of(void)
+{
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(true);
+}
+
+static const char * intcp_dt_board_compat[] = {
+	"arm,integrator-cp",
+	NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= intcp_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
+	.init_early	= intcp_init_early,
+	.init_irq	= intcp_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &cp_timer,
+	.init_machine	= intcp_init,
+	.restart	= integrator_restart,
+	.dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+
+#else
+
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+
+#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
+
+static void __init intcp_init_irq(void)
+{
+	u32 pic_mask, cic_mask, sic_mask;
+
+	/* These masks are for the HW IRQ registers */
+	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+	pic_mask |= (~((~0u) << (29 - 22))) << 22;
+	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+
+	/*
+	 * Disable all interrupt sources
+	 */
+	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+
+	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+		      -1, pic_mask, NULL);
+
+	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+		      -1, cic_mask, NULL);
+
+	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+		      IRQ_CP_CPPLDINT, sic_mask, NULL);
+
+	integrator_clk_init(true);
+}
+
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
@@ -400,3 +440,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 	.init_machine	= intcp_init,
 	.restart	= integrator_restart,
 MACHINE_END
+
+#endif
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:16:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:16:13 +0200
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
Message-ID: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>

This converts the AMBA (PrimeCell) devices on the Integrator/AP
and Integrator/CP over to probing from the Device Tree if the
kernel is compiled for Device Tree support.

We continue to #ifdef out all non-DT code and vice versa on
respective boot type to get a clean cut.

We need to add a bunch of auxdata (compare to the Versatile)
to handle bus names and callbacks alike.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/integratorap.dts       |  47 +++++++++++++
 arch/arm/boot/dts/integratorcp.dts       |  64 ++++++++++++++++++
 arch/arm/mach-integrator/common.h        |   2 +
 arch/arm/mach-integrator/core.c          |   8 ++-
 arch/arm/mach-integrator/integrator_ap.c | 109 ++++++++++++++++++++++---------
 arch/arm/mach-integrator/integrator_cp.c |  97 +++++++++++++++++----------
 6 files changed, 261 insertions(+), 66 deletions(-)

diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index a40d1ec0..303d001 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -23,4 +23,51 @@
 		clear-mask = <0xffffffff>;
 		valid-mask = <0x003fffff>;
 	};
+
+	fpga {
+		compatible = "arm,amba-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rtc: rtc at 15000000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x15000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <8>;
+			arm,primecell-periphid = <0x00041030>;
+		};
+
+		uart0: uart at 16000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x16000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <1>;
+			arm,primecell-periphid = <0x00041010>;
+		};
+
+		uart1: uart at 17000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x17000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <2>;
+			arm,primecell-periphid = <0x00041010>;
+		};
+
+		kmi0: kmi at 18000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x18000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <3>;
+			arm,primecell-periphid = <0x00041050>;
+		};
+
+		kmi1: kmi at 19000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x19000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <4>;
+			arm,primecell-periphid = <0x00041050>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index b6ca10f..517d420 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -43,4 +43,68 @@
 		clear-mask = <0x00000fff>;
 		valid-mask = <0x00000fff>;
 	};
+
+	fpga {
+		compatible = "arm,amba-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rtc: rtc at 15000000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x15000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <8>;
+		};
+
+		uart0: uart at 16000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x16000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <1>;
+		};
+
+		uart1: uart at 17000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x17000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <2>;
+		};
+
+		kmi0: kmi at 18000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x18000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <3>;
+		};
+
+		kmi1: kmi at 19000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x19000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <4>;
+		};
+
+		mmci: mmc at 1C000000 {
+			compatible = "arm,pl180", "arm,primecell";
+			reg = <0x1C000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <23 24>;
+			max-frequency = <515633>;
+		};
+
+		aaci: aaci at 1D000000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x1D000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <25>;
+		};
+
+		clcd: clcd at c0000000 {
+			compatible = "arm,pl110", "arm,primecell";
+			reg = <0xC0000000 0x1000>;
+			interrupt-parent = <&pic>;
+			interrupts = <22>;
+		};
+	};
 };
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index c4338e2..c3ff21b 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,5 @@
+#include <linux/amba/serial.h>
+extern struct amba_pl010_data integrator_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 67ea181..42890c8 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -33,7 +33,9 @@
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
 
-static struct amba_pl010_data integrator_uart_data;
+#include "common.h"
+
+#ifndef CONFIG_OF
 
 #define INTEGRATOR_RTC_IRQ	{ IRQ_RTCINT }
 #define INTEGRATOR_UART0_IRQ	{ IRQ_UARTINT0 }
@@ -86,6 +88,8 @@ int __init integrator_init(bool is_cp)
 	return 0;
 }
 
+#endif
+
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
  * bits in the following SC_CTRLS register bits:
@@ -122,7 +126,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
 	__raw_writel(ctrlc, SC_CTRLC);
 }
 
-static struct amba_pl010_data integrator_uart_data = {
+struct amba_pl010_data integrator_uart_data = {
 	.set_mctrl = integrator_uart_set_mctrl,
 };
 
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 58b0a58..ff20173 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -35,6 +35,7 @@
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -270,36 +271,6 @@ static struct platform_device cfi_flash_device = {
 	.resource	= &cfi_flash_resource,
 };
 
-static void __init ap_init(void)
-{
-	unsigned long sc_dec;
-	int i;
-
-	platform_device_register(&cfi_flash_device);
-
-	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-	for (i = 0; i < 4; i++) {
-		struct lm_device *lmdev;
-
-		if ((sc_dec & (16 << i)) == 0)
-			continue;
-
-		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-		if (!lmdev)
-			continue;
-
-		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-		lmdev->resource.flags = IORESOURCE_MEM;
-		lmdev->irq = IRQ_AP_EXPINT0 + i;
-		lmdev->id = i;
-
-		lm_device_register(lmdev);
-	}
-
-	integrator_init(false);
-}
-
 /*
  * Where is the timer (VA)?
  */
@@ -472,6 +443,52 @@ static void __init ap_init_irq_of(void)
 	integrator_clk_init(false);
 }
 
+/* For the Device Tree, add in the UART callbacks as AUXDATA */
+static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+		"rtc", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+		"uart0", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+		"uart1", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+		"kmi0", NULL),
+	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+		"kmi1", NULL),
+	{ /* sentinel */ },
+};
+
+static void __init ap_init_of(void)
+{
+	unsigned long sc_dec;
+	int i;
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			ap_auxdata_lookup, NULL);
+
+	platform_device_register(&cfi_flash_device);
+
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_AP_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+}
+
 static const char * ap_dt_board_compat[] = {
 	"arm,integrator-ap",
 	NULL,
@@ -485,7 +502,7 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 	.init_irq	= ap_init_irq_of,
 	.handle_irq	= fpga_handle_irq,
 	.timer		= &ap_timer,
-	.init_machine	= ap_init,
+	.init_machine	= ap_init_of,
 	.restart	= integrator_restart,
 	.dt_compat      = ap_dt_board_compat,
 MACHINE_END
@@ -514,6 +531,36 @@ static void __init ap_init_irq(void)
 	integrator_clk_init(false);
 }
 
+static void __init ap_init(void)
+{
+	unsigned long sc_dec;
+	int i;
+
+	platform_device_register(&cfi_flash_device);
+
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_AP_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+
+	integrator_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 0f6dc99..c341174 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -24,6 +24,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
+#include <linux/of_platform.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -244,16 +245,6 @@ static struct mmci_platform_data mmc_data = {
 	.gpio_cd	= -1,
 };
 
-#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }
-
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-	INTEGRATOR_CP_AACI_IRQS, NULL);
-
-
 /*
  * CLCD support
  */
@@ -304,15 +295,6 @@ static struct clcd_board clcd_data = {
 	.remove		= versatile_clcd_remove_dma,
 };
 
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-	{ IRQ_CP_CLCDCINT }, &clcd_data);
-
-static struct amba_device *amba_devs[] __initdata = {
-	&mmc_device,
-	&aaci_device,
-	&clcd_device,
-};
-
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 
 static void __init intcp_init_early(void)
@@ -322,19 +304,6 @@ static void __init intcp_init_early(void)
 #endif
 }
 
-static void __init intcp_init(void)
-{
-	int i;
-
-	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
-
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-	integrator_init(true);
-}
-
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
@@ -366,6 +335,37 @@ static void __init intcp_init_irq_of(void)
 	integrator_clk_init(true);
 }
 
+/*
+ * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
+ * and enforce the bus names since these are used for clock lookups.
+ */
+static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+		"rtc", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+		"uart0", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+		"uart1", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+		"kmi0", NULL),
+	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+		"kmi1", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
+		"mmci", &mmc_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
+		"aaci", &mmc_data),
+	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
+		"clcd", &clcd_data),
+	{ /* sentinel */ },
+};
+
+static void __init intcp_init_of(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			intcp_auxdata_lookup, NULL);
+	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+}
+
 static const char * intcp_dt_board_compat[] = {
 	"arm,integrator-cp",
 	NULL,
@@ -379,7 +379,7 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 	.init_irq	= intcp_init_irq_of,
 	.handle_irq	= fpga_handle_irq,
 	.timer		= &cp_timer,
-	.init_machine	= intcp_init,
+	.init_machine	= intcp_init_of,
 	.restart	= integrator_restart,
 	.dt_compat      = intcp_dt_board_compat,
 MACHINE_END
@@ -427,6 +427,37 @@ static void __init intcp_init_irq(void)
 	integrator_clk_init(true);
 }
 
+#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }
+
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
+	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
+	INTEGRATOR_CP_AACI_IRQS, NULL);
+
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
+	{ IRQ_CP_CLCDCINT }, &clcd_data);
+
+static struct amba_device *amba_devs[] __initdata = {
+	&mmc_device,
+	&aaci_device,
+	&clcd_device,
+};
+
+static void __init intcp_init(void)
+{
+	int i;
+
+	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+
+	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+		struct amba_device *d = amba_devs[i];
+		amba_device_register(d, &iomem_resource);
+	}
+	integrator_init(true);
+}
+
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
-- 
1.7.11.2



From linus.walleij at linaro.org  Thu Aug 16 08:16:20 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:16:20 +0200
Subject: [PATCH 6/6] ARM: integrator: convert platform devices to Device Tree
Message-ID: <1345119380-22806-1-git-send-email-linus.walleij@linaro.org>

This moves the physmap flash and SMSC91x ethernet devices
over to the device tree, moving the static board code down
into the #ifndef CONFIG_OF section.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/integratorap.dts       |  5 ++
 arch/arm/boot/dts/integratorcp.dts       | 12 +++++
 arch/arm/mach-integrator/integrator_ap.c | 36 ++++++-------
 arch/arm/mach-integrator/integrator_cp.c | 92 ++++++++++++++++----------------
 4 files changed, 82 insertions(+), 63 deletions(-)

diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 303d001..9c3288f 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -24,6 +24,11 @@
 		valid-mask = <0x003fffff>;
 	};
 
+	flash: flash at 24000000 {
+		compatible = "cfi-flash";
+		reg = <0x24000000 0x02000000>;
+	};
+
 	fpga {
 		compatible = "arm,amba-bus", "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 517d420..9cdc34e 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -44,6 +44,18 @@
 		valid-mask = <0x00000fff>;
 	};
 
+	flash: flash at 24000000 {
+		compatible = "cfi-flash";
+		reg = <0x24000000 0x02000000>;
+	};
+
+	ethernet: ethernet at c8000000 {
+		compatible = "smsc,lan91c111";
+		reg = <0xc8000000 0x10>;
+		interrupt-parent = <&pic>;
+		interrupts = <27>;
+	};
+
 	fpga {
 		compatible = "arm,amba-bus", "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index ff20173..c6122a2 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -255,22 +255,6 @@ static struct physmap_flash_data ap_flash_data = {
 	.set_vpp	= ap_flash_set_vpp,
 };
 
-static struct resource cfi_flash_resource = {
-	.start		= INTEGRATOR_FLASH_BASE,
-	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device cfi_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &ap_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &cfi_flash_resource,
-};
-
 /*
  * Where is the timer (VA)?
  */
@@ -455,6 +439,8 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 		"kmi0", NULL),
 	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 		"kmi1", NULL),
+	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
+		"physmap-flash", &ap_flash_data),
 	{ /* sentinel */ },
 };
 
@@ -466,8 +452,6 @@ static void __init ap_init_of(void)
 	of_platform_populate(NULL, of_default_bus_match_table,
 			ap_auxdata_lookup, NULL);
 
-	platform_device_register(&cfi_flash_device);
-
 	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 	for (i = 0; i < 4; i++) {
 		struct lm_device *lmdev;
@@ -514,6 +498,22 @@ MACHINE_END
  * for eventual deletion.
  */
 
+static struct resource cfi_flash_resource = {
+	.start		= INTEGRATOR_FLASH_BASE,
+	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device cfi_flash_device = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &ap_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &cfi_flash_resource,
+};
+
 #define INTEGRATOR_SC_VALID_INT	0x003fffff
 
 static void __init ap_init_irq(void)
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index c341174..b04ccf2 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -51,12 +51,9 @@
 #include "common.h"
 
 #define INTCP_PA_FLASH_BASE		0x24000000
-#define INTCP_FLASH_SIZE		SZ_32M
 
 #define INTCP_PA_CLCD_BASE		0xc0000000
 
-#define INTCP_ETH_SIZE			0x10
-
 #define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG			0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
@@ -183,47 +180,6 @@ static struct physmap_flash_data intcp_flash_data = {
 	.set_vpp	= intcp_flash_set_vpp,
 };
 
-static struct resource intcp_flash_resource = {
-	.start		= INTCP_PA_FLASH_BASE,
-	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device intcp_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &intcp_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &intcp_flash_resource,
-};
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= INTEGRATOR_CP_ETH_BASE,
-		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_CP_ETHINT,
-		.end	= IRQ_CP_ETHINT,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *intcp_devs[] __initdata = {
-	&intcp_flash_device,
-	&smc91x_device,
-};
-
 /*
  * It seems that the card insertion interrupt remains active after
  * we've acknowledged it.  We therefore ignore the interrupt, and
@@ -356,6 +312,8 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 		"aaci", &mmc_data),
 	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 		"clcd", &clcd_data),
+	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
+		"physmap-flash", &intcp_flash_data),
 	{ /* sentinel */ },
 };
 
@@ -363,7 +321,6 @@ static void __init intcp_init_of(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table,
 			intcp_auxdata_lookup, NULL);
-	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 }
 
 static const char * intcp_dt_board_compat[] = {
@@ -391,6 +348,51 @@ MACHINE_END
  * for eventual deletion.
  */
 
+#define INTCP_FLASH_SIZE		SZ_32M
+
+static struct resource intcp_flash_resource = {
+	.start		= INTCP_PA_FLASH_BASE,
+	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device intcp_flash_device = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &intcp_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &intcp_flash_resource,
+};
+
+#define INTCP_ETH_SIZE			0x10
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	= INTEGRATOR_CP_ETH_BASE,
+		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_CP_ETHINT,
+		.end	= IRQ_CP_ETHINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *intcp_devs[] __initdata = {
+	&intcp_flash_device,
+	&smc91x_device,
+};
+
 #define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
 #define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
 #define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
-- 
1.7.11.2



From plagnioj at jcrosoft.com  Thu Aug 16 08:18:52 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 16 Aug 2012 14:18:52 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
Message-ID: <20120816121852.GA7439@game.jcrosoft.org>

On 16:38 Wed 15 Aug     , Linus Walleij wrote:
> (Hm maybe I should've read this patch first, well whatever.)
> 
> On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> 
> > This is also include the gpio controller as the IP share both.
> > Each soc will have to describe the SoC limitation and pin configuration via
> > DT.
> 
> This is very good.
> 
> > This will allow to do not need to touch the C code when adding new SoC if the
> > IP version is supported.
> 
> Which is what we want -> less churn.
> 
> > +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
> 
> This needs to be CC to devicetree-discuss at lists.ozlabs.org where bindings
> are discussed, the people there sometimes make a good job to make sure
> the bindings are OS-neutral and stuff (doesn't seem like a problem in this
> very case, but anyway).
> 
> > +Required properties for iomux controller:
> > +- compatible: "atmel,at91rm9200-pinctrl"
> > +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
> > +  configured in this periph mode. All the periph and bank need to be describe.
> 
> Can you please be more elaborate on this mux-mask, like what each bit
> means and why the bits are arranged like that and what it means on the
> AT91 platform.... I was first reading the .dts and was like ?woot? so
> I go to the bindings doc and I read this and I'm still like ?woot?..
> 
> > +Required properties for pin configuration node:
> > +- atmel,pins: 4 integers array, represents a group of pins mux and config
> 
> This also need to be detailed so you can just read this and then
> look at the numbers in the device tree and, "aha I get it!".
> 
> > +  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
> > +  The PERIPH 0 means gpio.
> 
> So please elaborate a bit on the three first members, so it's easy to read
> and understand the device tree. I "sort of" understand it but better
> be explicit.
> 
> (...)
> > +Bits used for CONFIG:
> > +PULL_UP(1 << 0): indicate this pin need a pull up.
> > +MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.
> 
> Hm if we just add multidrive to <linux/pinctrl/pinconf-generic.h> we
> could probably get this driver (and bindings) to use the generic
> pinconf library in drivers/pinctrl/pinonf-generic.c as the coh901
> currently does.
> 
> Actually multidrive makes me think that this is just shunting in
> several MOSFET driver stages, which we *used* to have in
> pinconf-generic, just by documenting that the argument passed
> with parameter PIN_CONFIG_DRIVE_PUSH_PULL
> would indicate the number of drive stages if != 0.
> 
> Like this (old doc):
> 
> + * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
> + *     low, this is the most typical case and is typically achieved with two
> + *     active transistors on the output. If the pin can support different
> + *     drive strengths for push/pull, the strength is given in the argument
> + *     as the number of driving stages vs nominal load impedance, so say
> + *     quadruple driving stages (usually 8 transistors rather than two) will
> + *     be configured with the 8 passed as argument.
> 
> We're not mandate generic pin config because driver authors told me
> repeatedly that their chips are very special (like everyone else, hehe)
> but please keep it in mind as it could be hard to change this later.
> I'd be happy to put back this piece of doc...
> 
> > +2. The pin configuration node intends to work on a specific function should
> > +   to be defined under that specific function node.
> > +   The function node's name should represent well about what function
> > +   this group of pins in this pin configuration node are working on.
> 
> I cannot parse this, sorry :-) could you detail...
> 
> > +3. The driver can use the function node's name and pin configuration node's
> > +   name describe the pin function and group hierarchy.
> > +   For example, Linux Iat91 pinctrl driver takes the function node's name
> > +   as the function name and pin configuration node's name as group name to
> > +   create the map table.
> > +4. Each pin configuration node should have a phandle, devices can set pins
> > +   configurations by referring to the phandle of that pin configuration node.
> > +5. The gpio controller must be describe in the pinctrl simple-bus.
> 
> I think I understand this part...
> 
> > +pinctrl at fffff400 {
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +       ranges;
> > +       compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> > +       reg = <0xfffff400 0x600>;
> > +
> > +       atmel,mux-mask = <
> > +             /*    A         B     */
> > +              0xffffffff 0xffc00c3b  /* pioA */
> > +              0xffffffff 0x7fff3ccf  /* pioB */
> > +              0xffffffff 0x007fffff  /* pioC */
> > +             >;
> 
> I still have a real hard time understanding what is happening here,
> but maybe I'll understand as I go on reading the driver.
> 
> > +       /* shared pinctrl settings */
> > +       dbgu {
> > +               pinctrl_dbgu: dbgu-0 {
> > +                       atmel,pins =
> > +                               <1 14 0x1 0x0   /* PB14 periph A */
> > +                                1 15 0x1 0x1>; /* PB15 periph with pullup */
> 
> I understand that Pin 14 and 15 in pin bank 1 is connected to some
> peripheral numbered 1 and pin 15 is pulled up.
> 
> I guess perioheral 1 is identical to debugf uart 0 or something
> like that, since the node has this name? ut shouldn't this
> peripheral number come from the fact that it's dbgu so there
> is somewhere a table cross referencing ... or the device itself
> has some node which is separate and has some name like
> "pinctrl-periphid" or so?
> 
> Just trying to decipher this a bit so I see if I could maintain
> it...
> 
> Would it be possible to have the periphid as a separate node
> entry if it is anyway going to be the same value for all
> pins, or is this number also unique per bank or something
> like that, so debug uart would be say peripheral ID 5 on another
> pin bank? (In that case, keep it like this.)
the pin can be anywhere on the different bank and configured in different mux
(periph) so can not do as you suggest
> 
> > +dbgu: serial at fffff200 {
> > +       compatible = "atmel,at91sam9260-usart";
> > +       reg = <0xfffff200 0x200>;
> > +       interrupts = <1 4 7>;
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&pinctrl_dbgu>;
> > +       status = "disabled";
> > +};
> 
> I really like the looks of this.
> 
> (...)
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index e91c7cd..178a619 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -352,6 +352,7 @@ config ARCH_AT91
> >         select CLKDEV_LOOKUP
> >         select IRQ_DOMAIN
> >         select NEED_MACH_IO_H if PCCARD
> > +       select PINCTRL
> 
> Richard said something about also selectong the AT91 driver which
> seemed lika a good idea.
as I reply Richard we need to force the at91 driver only when DT enabled
> 
> (There follow some changes moving a lot of IRQ domain stuff etc from
> the GPIO driver which is hard to understand, but I guess you're doing
> the right thing.)
> 
> (...)
> > --- /dev/null
> > +++ b/drivers/pinctrl/pinctrl-at91.c
> > @@ -0,0 +1,1448 @@
> > +/*
> > + * at91 pinctrl driver based on at91 pinmux core
> > + *
> > + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
> > + * <plagnioj at jcrosoft.com>
> > + *
> > + * Under GPLv2 only
> > + */
> > +
> > +#define DEBUG
> 
> As noted rely on switching on DEBUG_PINCTRL where needed.
> It tags on -DDEBUG in the Makefile.
> 
> > +#include <asm/mach/irq.h>
> 
> Hm, it seems this platform is not using SPARSE_IRQ ...
it does

see chained_irq_enter/chained_irq_exit
> 
> (...)
> > +static struct at91_gpio_chip *gpio_chip[MAX_GPIO_BANKS];
> 
> Nitpick should it not be named *gpio_chips[] (plural) since
> there are several chips in that array?
ok
> 
> > +static int gpio_banks;
> > +static unsigned long at91_gpio_caps;
> 
> I usually protect this kind of variables with a mutex but it
> may be over-cautious.
> 
> (...)
> > +#define PULL_UP                (0 << 1)
> > +#define MULTI_DRIVE    (1 << 1)
> 
> So this I would have attempted to use pinconf-generic.[c|h] for
> and use PIN_CONFIG_BIAS_PULL_UP and
> PIN_CONFIG_DRIVER_PUSH_PULL with a specific
> argument for the multidrive.
> 
> Beware that you may want to patch pinconf-generic.c
> to get the debugfs output you want etc.
> 
> But as I said this is optional, just a good idea in general.
I'll take a look
> 
> (...)
> > +struct at91_pmx_pin {
> > +       uint32_t bank;
> > +       uint32_t pin;
> > +       uint32_t mux;
> > +       uint32_t pullup;
> > +       unsigned long conf;
> > +};
> 
> Are they all u32 really? I understand that they are u32 in the
> devicetree but pullup seems like a candidate for a bool.
> 
> Reading below it seems the "mux" member should be some
> kind of enum. Doing that an enum and documenting it seems
> like it would solve other readability issues.
> 
> And this could actually use some kerneldoc too, if possible.
ok
> 
> > +/**
> > + * struct at91_pin_group - describes an At91 pin group
> > + * @name: the name of this specific pin group
> 
> @pins_conf is not documented.
> 
> > + * @pins: an array of discrete physical pins used in this group, taken
> > + *     from the driver-local pin enumeration space
> > + * @npins: the number of pins in this group array, i.e. the number of
> > + *     elements in .pins so we can iterate over that array
> > + */
> > +struct at91_pin_group {
> > +       const char *name;
> > +       struct at91_pmx_pin *pins_conf;
> > +       unsigned int *pins;
> > +       unsigned npins;
> > +};
> 
> 
> > +struct at91_pinctrl {
> > +       struct device *dev;
> > +       struct pinctrl_dev *pctl;
> > +
> > +       int nbanks;
> > +
> > +       int nmux;
> > +       uint32_t *mux_mask;
> > +
> > +       struct at91_pmx_func *functions;
> > +       int nfunctions;
> > +
> > +       struct at91_pin_group *groups;
> > +       int ngroups;
> > +
> > +       void (*set_A_periph)(void __iomem *pio, unsigned mask);
> > +       void (*set_B_periph)(void __iomem *pio, unsigned mask);
> > +};
> 
> kerneldoc. Especually the two last functions are mysterious when just
> looking at the struct.
> 
> (Then follows a block of really nice code...)
> 
> (...)
> > +static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
> > +                  unsigned offset)
> > +{
> > +       seq_printf(s, "%s", dev_name(pctldev->dev));
> > +}
> 
> This print should actually output something interesting (if it helps)
> maybe you could skip it?
I've plan at a second step
> 
> > +static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
> > +                       struct device_node *np,
> > +                       struct pinctrl_map **map, unsigned *num_maps)
> 
> DT parse code, looks nice but would request Stephen to have a look
> at it.
> 
> (...)
> > +       new_map = kmalloc(sizeof(*new_map) * map_num, GFP_KERNEL);
> 
> Maybe devm_kzalloc()?
> 
> Because:
> 
> (...)
> > +       if (!parent) {
> > +               kfree(new_map);
> > +               return -EINVAL;
> 
> You could just return here. And:
> 
> (...)
> > +static void at91_dt_free_map(struct pinctrl_dev *pctldev,
> > +                               struct pinctrl_map *map, unsigned num_maps)
> > +{
> > +       kfree(map);
> > +}
> 
> Then this wouldn't be needed at all.
> 
> (...)
> > +static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(mask, pio + PIO_IDR);
> > +}
> 
> I think most people use writel_relaxed() for this purpose (non-timeconsuming
> register write) these days. So conside replacing all __raw_* with *_relaxed().
I known this one I've in mind to do it as second patch
> 
> (...)
> > +static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
> > +{
> > +
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
> > +                                               pio + PIO_ABCDSR1);
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> > +                                               pio + PIO_ABCDSR2);
> > +}
> > +
> > +static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
> > +                                               pio + PIO_ABCDSR1);
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
> > +                                               pio + PIO_ABCDSR2);
> > +}
> > +
> > +static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(mask, pio + PIO_ASR);
> > +}
> > +
> > +static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(mask, pio + PIO_BSR);
> > +}
> > +
> > +static void at91_mux_set_C_periph(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> > +}
> > +
> > +static void at91_mux_set_D_periph(void __iomem *pio, unsigned mask)
> > +{
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
> > +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
> > +}
> 
> I have no clue whatsoever what is going on here, A? B? C? D?
> Some small comment or something giving a hint about this grouping
> system and how it works would be really nice.
periph (mux)
> 
> > +static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
> > +{
> > +       if (pin->mux) {
> > +               dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
> > +                       pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
> > +       } else {
> > +               dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
> > +                       pin->bank + 'A', pin->pin, pin->conf);
> > +       }
> > +}
> 
> This is nice, and one of the things we try to centralize and standardize in
> pinconf-generic. However as I said that would be optional.
> 
> (...)
> 
> > +static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, unsigned input)
> > +{
> > +       __raw_writel(mask, pio + PIO_PER);
> > +       __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER));
> > +}
> > +
> 
> The last argument, "input" seems to be a bool.
> 
> Also not that this should maybe be named at91_mux_gpio_endisable()
> since it is called from the disable() function below.
ok
> 
> (...)
> > +       for (i = 0; i < npins; i++) {
> > +               pin = &pins_conf[i];
> > +               at91_pin_dbg(info->dev, pin);
> > +               pio = pin_to_controller(info, pin->bank);
> > +               mask = pin_to_mask(pin->pin);
> > +               at91_mux_disable_interrupt(pio, mask);
> > +               switch(pin->mux) {
> > +               case 0:
> > +                       at91_mux_gpio_enable(pio, mask, 1);
> > +                       break;
> > +               case 1:
> > +                       info->set_A_periph(pio, mask);
> > +                       break;
> > +               case 2:
> > +                       info->set_B_periph(pio, mask);
> > +                       break;
> > +               case 3:
> > +                       at91_mux_set_C_periph(pio, mask);
> > +                       break;
> > +               case 4:
> > +                       at91_mux_set_D_periph(pio, mask);
> > +                       break;
> > +               }
> > +               if (pin->mux)
> > +                       at91_mux_gpio_disable(pio, mask);
> 
> Looking at this it seems that the pin->mux variable should be an
> enum so we get rid of these magic values 0,1,2,3,4. Documenting
> these enums with kerneldoc would probably solve a lot of
> questionmarks.
> 
> (Noted in the struct review above as well.)
ok
> 
> (...)
> > +static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
> > +                          unsigned group)
> > +{
> > +       struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
> > +       const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
> > +       const struct at91_pmx_pin *pin;
> > +       uint32_t npins = info->groups[group].npins;
> > +       int i;
> > +       unsigned mask;
> > +       void __iomem *pio;
> > +
> > +       for (i = 0; i < npins; i++) {
> > +               pin = &pins_conf[i];
> > +               at91_pin_dbg(info->dev, pin);
> > +               pio = pin_to_controller(info, pin->bank);
> > +               mask = pin_to_mask(pin->pin);
> > +               at91_mux_gpio_enable(pio, mask, 1);
> 
> Actually calling a function named "*enable" to disable something looks
> quite unintuitive. Maybe rename that function to
> "at91_mux_gpio_endisable()" or something?
> 
> (...)
...
> > +{
> > +       struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
> > +       unsigned        mask = 1 << d->hwirq;
> > +       unsigned        bank = at91_gpio->pioc_idx;
> > +
> > +       if (unlikely(bank >= MAX_GPIO_BANKS))
> > +               return -EINVAL;
> > +
> > +       if (state)
> > +               wakeups[bank] |= mask;
> > +       else
> > +               wakeups[bank] &= ~mask;
> > +
> > +       irq_set_irq_wake(at91_gpio->pioc_virq, state);
> > +
> > +       return 0;
> > +}
> 
> So I can see that this sets or clears bits in a 32-bit word per
> bank. But I don't see these words being used for anything at all?
> 
> So what's the point of all this?
> 
> In  ux500 we have a register bit that enables wakeup on a
> certain pin, then it makes all kind of sense to have this,
> but what is this stuff, really? It seems the function can be
> stripped down to two lines just calling irq_set_irq_wake().
> 
will take a look on this
> (...)
> > +       range = &at91_chip->range;
> > +       range->name = chip->label;
> > +       range->id = alias_idx;
> > +       range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
> > +
> > +       range->npins = chip->ngpio;
> > +       range->gc = chip;
> 
> This way of handling ranges looks very smooth, great that this works
> for you!

should work for everyone with pinctrl that combine both

Best Regards,
J.


From anilkumar at ti.com  Thu Aug 16 08:20:06 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Thu, 16 Aug 2012 17:50:06 +0530
Subject: [PATCH 0/4] Add device tree data for AM33XX devices
Message-ID: <1345119610-5247-1-git-send-email-anilkumar@ti.com>

Add pinctrl and d_can device tree data to AM33XX family of devices.
First two patches add support for pinctrl DT data and rest adds
dcan DT data.

Reason behind combining these patches is to apply cleanly on
linux-omap devel-dt tree because these are sequential patches.

These patches were tested on AM335x-Bone and AM335x-EVM apply
on linux-omap:devel-dt tree with this patch
http://lkml.org/lkml/2012/8/15/106

AnilKumar Ch (4):
  arm/dts: AM33XX: Add basic pinctrl device tree data
  arm/dts: AM33XX: Configure pinmuxs for user leds control on Bone
  arm/dts: AM33XX: Configure pinmuxs for D_CAN1 on AM335x-EVM
  arm/dts: AM33XX: Add D_CAN device tree data

 arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
 arch/arm/boot/dts/am335x-evm.dts  |   16 ++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi     |   27 +++++++++++++++++++++++++++
 3 files changed, 57 insertions(+)

-- 
1.7.9.5



From anilkumar at ti.com  Thu Aug 16 08:20:09 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Thu, 16 Aug 2012 17:50:09 +0530
Subject: [PATCH v3 3/4] arm/dts: AM33XX: Configure pinmuxs for D_CAN1 on
 AM335x-EVM
In-Reply-To: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345119610-5247-4-git-send-email-anilkumar@ti.com>

Add D_CAN1 pinctrl node to am3358_pinmux master node to export
D_CAN functionality on AM335x EVM according to pinctrl-single
driver.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
Changes from v2:
	- Incorporated Vaibhav H's comments on v2
	  * Added dcan0 instances to am33xx.dtsi file

Changes from v1:
	- These two patches separated from c_can DT support
	  patch series.

 arch/arm/boot/dts/am335x-evm.dts |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 5dd8a6b..a64c30a 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -18,6 +18,18 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
+	am3358_pinmux: pinmux at 44E10800 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&d_can1_pins>;
+
+		d_can1_pins: pinmux_d_can_pins {
+			pinctrl-single,pins = <
+				0x168 0x2	/* uart0_ctsn.d_can1_tx, OUTPUT | MODE2 */
+				0x16C 0x32	/* uart0_rtsn.d_can1_rx, INPUT_PULLUP | MODE2 */
+			>;
+		};
+	};
+
 	ocp {
 		uart1: serial at 44E09000 {
 			status = "okay";
-- 
1.7.9.5



From anilkumar at ti.com  Thu Aug 16 08:20:08 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Thu, 16 Aug 2012 17:50:08 +0530
Subject: [PATCH v4 2/4] arm/dts: AM33XX: Configure pinmuxs for user leds
 control on Bone
In-Reply-To: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345119610-5247-3-git-send-email-anilkumar@ti.com>

Adds GPIO pinctrl nodes to am3358_pinmux master node to control
user leds (USR0, USR1, USR2 and USR3) present on BeagleBone.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a7906cb..58f5042 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -18,6 +18,20 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
+	am3358_pinmux: pinmux at 44E10800 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&userled_pins>;
+
+		userled_pins: pinmux_userled_pins {
+			pinctrl-single,pins = <
+				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+				0x5C 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+			>;
+		};
+	};
+
 	ocp {
 		uart1: serial at 44E09000 {
 			status = "okay";
-- 
1.7.9.5



From anilkumar at ti.com  Thu Aug 16 08:20:10 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Thu, 16 Aug 2012 17:50:10 +0530
Subject: [PATCH v3 4/4] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345119610-5247-5-git-send-email-anilkumar@ti.com>

Add Bosch D_CAN controller device tree data to AM33XX dtsi
file by adding d_can device nodes with all the necessary
parameters.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts |    4 ++++
 arch/arm/boot/dts/am33xx.dtsi    |   18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index a64c30a..1e1fc15 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -34,5 +34,9 @@
 		uart1: serial at 44E09000 {
 			status = "okay";
 		};
+
+		dcan1: d_can at 481D0000 {
+			status = "okay";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dfe9c559..d965137 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -177,5 +177,23 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		dcan0: d_can at 481CC000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			reg = <0x481CC000 0x2000>;
+			interrupts = <52>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		dcan1: d_can at 481D0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			reg = <0x481D0000 0x2000>;
+			interrupts = <55>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.7.9.5



From anilkumar at ti.com  Thu Aug 16 08:20:07 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Thu, 16 Aug 2012 17:50:07 +0530
Subject: [PATCH v4 1/4] arm/dts: AM33XX: Add basic pinctrl device tree data
In-Reply-To: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345119610-5247-2-git-send-email-anilkumar@ti.com>

Adds basic pinctrl device tree data for AM33XX family of devices.
This patch is based on the pinctrl-single driver.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
Changes from v3:
	- Updated the reg length based on latest AM335x TRM.

Changes from v2:
	- user led pinmux comments updated according to Tony's
	  comment.

Changes from v1:
	- Rebased the patches based on latest pinctrl-single driver

 arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dde76f7..dfe9c559 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -40,6 +40,15 @@
 		};
 	};
 
+	am3358_pinmux: pinmux at 44E10800 {
+		compatible = "pinctrl-single";
+		reg = <0x44E10800 0x0238>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7F>;
+	};
+
 	/*
 	 * XXX: Use a flat representation of the AM33XX interconnect.
 	 * The real AM33XX interconnect network is quite complex.Since
-- 
1.7.9.5



From arnd at arndb.de  Thu Aug 16 07:54:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 11:54:10 +0000
Subject: [PATCH v2 03/31] arm64: Exception handling
In-Reply-To: <20120816100536.GF31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151303.47743.arnd@arndb.de>
 <20120816100536.GF31784@mudshark.cambridge.arm.com>
Message-ID: <201208161154.10891.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> On Wed, Aug 15, 2012 at 02:03:47PM +0100, Arnd Bergmann wrote:
> > On Tuesday 14 August 2012, Catalin Marinas wrote:
> > 
> > > +#ifdef CONFIG_AARCH32_EMULATION
> > > +#define compat_thumb_mode(regs) \
> > > +   (((regs)->pstate & COMPAT_PSR_T_BIT))
> > > +#else
> > > +#define compat_thumb_mode(regs) (0)
> > > +#endif
> > 
> > The symbol we use on other platforms is CONFIG_COMPAT. I don't think you
> > need to have a separate CONFIG_AARCH32_EMULATION
> 
> Using COMPAT does preclude the possibility of doing something like the x32
> ABI later on though. Some other architectures seem to do something similar
> (MIPS32_COMPAT, IA32_EMULATION).

Ok, fair enough.

	Arnd



From arnd at arndb.de  Thu Aug 16 08:37:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 12:37:53 +0000
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <20120816102300.GG31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151415.39570.arnd@arndb.de>
 <20120816102300.GG31784@mudshark.cambridge.arm.com>
Message-ID: <201208161237.53594.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> > This looks wrong: PER_LINUX/PER_LINUX32 decides over the output of the
> > uname system call, while TIF_32BIT decides over the instruction set
> > when returning to user space. You definitely should not set the personality
> > to the value you pass from the elf loader. Instead, just do
> > 
> > #define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
> > #defined COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
> 
> In this case, won't uname be incorrect (aarch64l) for aarch32 tasks (which
> expect something like armv8l)?

No, the uname output is meant to tell you about the system, not the
instruction set that you are using (you already know that in compiled
code).

The main use case is to fool stuff like autoconf into assuming your
architecture is the other one, e.g. when building a 32 bit package
on using a 64 bit /bin/bash to run ./configure or vice versa.

	Arnd


From arnd at arndb.de  Thu Aug 16 08:39:31 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 12:39:31 +0000
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <20120816102808.GH31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
 <20120816102808.GH31784@mudshark.cambridge.arm.com>
Message-ID: <201208161239.31409.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> 
> On Wed, Aug 15, 2012 at 03:34:04PM +0100, Arnd Bergmann wrote:
> > On Tuesday 14 August 2012, Catalin Marinas wrote:
> > > +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> > > +{
> > > +   int ret;
> > > +
> > > +   if (personality(current->personality) == PER_LINUX32 &&
> > > +           personality == PER_LINUX)
> > > +           personality = PER_LINUX32;
> > > +   ret = sys_personality(personality);
> > > +   if (ret == PER_LINUX32)
> > > +           ret = PER_LINUX;
> > > +   return ret;
> > > +}
> > 
> > Where did you get this from?
> > 
> > You should not need compat_sys_personality, just call the native function.
> 
> Hmm, but in that case an aarch32 application doing a personality(PER_LINUX)
> syscall will start seeing the wrong uname.

Not the wrong uname, just the default one, which is correct.

	Arnd


From plagnioj at jcrosoft.com  Thu Aug 16 08:40:02 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 16 Aug 2012 14:40:02 +0200
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
References: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <20120816124002.GB7439@game.jcrosoft.org>

On 14:16 Thu 16 Aug     , Linus Walleij wrote:
> This converts the AMBA (PrimeCell) devices on the Integrator/AP
> and Integrator/CP over to probing from the Device Tree if the
> kernel is compiled for Device Tree support.
> 
> We continue to #ifdef out all non-DT code and vice versa on
> respective boot type to get a clean cut.
> 
> We need to add a bunch of auxdata (compare to the Versatile)
> to handle bus names and callbacks alike.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/integratorap.dts       |  47 +++++++++++++
>  arch/arm/boot/dts/integratorcp.dts       |  64 ++++++++++++++++++
>  arch/arm/mach-integrator/common.h        |   2 +
>  arch/arm/mach-integrator/core.c          |   8 ++-
>  arch/arm/mach-integrator/integrator_ap.c | 109 ++++++++++++++++++++++---------
>  arch/arm/mach-integrator/integrator_cp.c |  97 +++++++++++++++++----------
>  6 files changed, 261 insertions(+), 66 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
> index a40d1ec0..303d001 100644
> --- a/arch/arm/boot/dts/integratorap.dts
> +++ b/arch/arm/boot/dts/integratorap.dts
> @@ -23,4 +23,51 @@
>  		clear-mask = <0xffffffff>;
>  		valid-mask = <0x003fffff>;
>  	};
> +
> +	fpga {
> +		compatible = "arm,amba-bus", "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		rtc: rtc at 15000000 {
> +			compatible = "arm,pl031", "arm,primecell";
> +			reg = <0x15000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <8>;
> +			arm,primecell-periphid = <0x00041030>;
> +		};
> +
> +		uart0: uart at 16000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x16000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <1>;
> +			arm,primecell-periphid = <0x00041010>;
> +		};
> +
> +		uart1: uart at 17000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x17000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <2>;
> +			arm,primecell-periphid = <0x00041010>;
> +		};
> +
> +		kmi0: kmi at 18000000 {
> +			compatible = "arm,pl050", "arm,primecell";
> +			reg = <0x18000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <3>;
> +			arm,primecell-periphid = <0x00041050>;
> +		};
> +
> +		kmi1: kmi at 19000000 {
> +			compatible = "arm,pl050", "arm,primecell";
> +			reg = <0x19000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <4>;
> +			arm,primecell-periphid = <0x00041050>;
> +		};
> +	};
>  };
> diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
> index b6ca10f..517d420 100644
> --- a/arch/arm/boot/dts/integratorcp.dts
> +++ b/arch/arm/boot/dts/integratorcp.dts
> @@ -43,4 +43,68 @@
>  		clear-mask = <0x00000fff>;
>  		valid-mask = <0x00000fff>;
>  	};
> +
> +	fpga {
> +		compatible = "arm,amba-bus", "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		rtc: rtc at 15000000 {
> +			compatible = "arm,pl031", "arm,primecell";
> +			reg = <0x15000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <8>;
> +		};
> +
> +		uart0: uart at 16000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x16000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <1>;
> +		};
> +
> +		uart1: uart at 17000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x17000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <2>;
> +		};
> +
> +		kmi0: kmi at 18000000 {
> +			compatible = "arm,pl050", "arm,primecell";
> +			reg = <0x18000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <3>;
> +		};
> +
> +		kmi1: kmi at 19000000 {
> +			compatible = "arm,pl050", "arm,primecell";
> +			reg = <0x19000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <4>;
> +		};
> +
> +		mmci: mmc at 1C000000 {
> +			compatible = "arm,pl180", "arm,primecell";
> +			reg = <0x1C000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <23 24>;
> +			max-frequency = <515633>;
> +		};
> +
> +		aaci: aaci at 1D000000 {
> +			compatible = "arm,pl041", "arm,primecell";
> +			reg = <0x1D000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <25>;
> +		};
> +
> +		clcd: clcd at c0000000 {
> +			compatible = "arm,pl110", "arm,primecell";
> +			reg = <0xC0000000 0x1000>;
> +			interrupt-parent = <&pic>;
> +			interrupts = <22>;
> +		};
> +	};
>  };
> diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
> index c4338e2..c3ff21b 100644
> --- a/arch/arm/mach-integrator/common.h
> +++ b/arch/arm/mach-integrator/common.h
> @@ -1,3 +1,5 @@
> +#include <linux/amba/serial.h>
> +extern struct amba_pl010_data integrator_uart_data;
>  void integrator_init_early(void);
>  int integrator_init(bool is_cp);
>  void integrator_reserve(void);
> diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
> index 67ea181..42890c8 100644
> --- a/arch/arm/mach-integrator/core.c
> +++ b/arch/arm/mach-integrator/core.c
> @@ -33,7 +33,9 @@
>  #include <asm/mach/time.h>
>  #include <asm/pgtable.h>
>  
> -static struct amba_pl010_data integrator_uart_data;
> +#include "common.h"
> +
> +#ifndef CONFIG_OF
>  
>  #define INTEGRATOR_RTC_IRQ	{ IRQ_RTCINT }
>  #define INTEGRATOR_UART0_IRQ	{ IRQ_UARTINT0 }
> @@ -86,6 +88,8 @@ int __init integrator_init(bool is_cp)
>  	return 0;
>  }
>  
> +#endif
> +
>  /*
>   * On the Integrator platform, the port RTS and DTR are provided by
>   * bits in the following SC_CTRLS register bits:
> @@ -122,7 +126,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
>  	__raw_writel(ctrlc, SC_CTRLC);
>  }
>  
> -static struct amba_pl010_data integrator_uart_data = {
> +struct amba_pl010_data integrator_uart_data = {
>  	.set_mctrl = integrator_uart_set_mctrl,
>  };
>  
> diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
> index 58b0a58..ff20173 100644
> --- a/arch/arm/mach-integrator/integrator_ap.c
> +++ b/arch/arm/mach-integrator/integrator_ap.c
> @@ -35,6 +35,7 @@
>  #include <linux/clk.h>
>  #include <linux/platform_data/clk-integrator.h>
>  #include <linux/of_irq.h>
> +#include <linux/of_platform.h>
>  #include <video/vga.h>
>  
>  #include <mach/hardware.h>
> @@ -270,36 +271,6 @@ static struct platform_device cfi_flash_device = {
>  	.resource	= &cfi_flash_resource,
>  };
>  
> -static void __init ap_init(void)
> -{
> -	unsigned long sc_dec;
> -	int i;
> -
> -	platform_device_register(&cfi_flash_device);
> -
> -	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
> -	for (i = 0; i < 4; i++) {
> -		struct lm_device *lmdev;
> -
> -		if ((sc_dec & (16 << i)) == 0)
> -			continue;
> -
> -		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
> -		if (!lmdev)
> -			continue;
> -
> -		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
> -		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
> -		lmdev->resource.flags = IORESOURCE_MEM;
> -		lmdev->irq = IRQ_AP_EXPINT0 + i;
> -		lmdev->id = i;
> -
> -		lm_device_register(lmdev);
> -	}
> -
> -	integrator_init(false);
> -}
> -
>  /*
>   * Where is the timer (VA)?
>   */
> @@ -472,6 +443,52 @@ static void __init ap_init_irq_of(void)
>  	integrator_clk_init(false);
>  }
>  
> +/* For the Device Tree, add in the UART callbacks as AUXDATA */
> +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
> +	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
> +		"rtc", NULL),
> +	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
> +		"uart0", &integrator_uart_data),
> +	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
> +		"uart1", &integrator_uart_data),
> +	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
> +		"kmi0", NULL),
> +	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
> +		"kmi1", NULL),
> +	{ /* sentinel */ },
why that?

Best Regards,
J.


From linus.walleij at linaro.org  Thu Aug 16 08:40:06 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:40:06 +0200
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
Message-ID: <CACRpkdYJngvG92BJ_jMyx5KZcr2WmMwGtat6=wKsq+RLk3ECgA@mail.gmail.com>

On Tue, Aug 14, 2012 at 7:52 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:

> From: Marc Zyngier <marc.zyngier at arm.com>
(...)
> +static void __init arch_timer_calibrate(void)

I think you wrot in the last review thread that this should be renamed
"arch_timer_get_freq()".

> +{
> +       if (arch_timer_rate == 0) {
> +               arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
> +               arch_timer_rate = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
> +
> +               /* Check the timer frequency. */
> +               if (arch_timer_rate == 0)
> +                       panic("Architected timer frequency is set to zero.\n"
> +                             "You must set this in your .dts file\n");

This comment about the .dts file is completely out-of-place.
The error message should be about the register containing 0, right?

Also, at this very point in the code, I think you should convert that panic()
to pr_err() and insert:

#include <linux/clk.h>

struct clk *clk;

clk = clk_get_sys("arm_generic_timer", NULL);
if (IS_ERR(clk))
               panic("Not even a clk to get freq off! Giving up.\n");
err = clk_prepare_enable(clk);
if (err) {
           pr_err("smp_twd: clock failed to prepare: %d\n", err);
           clk_put(clk);
           panic("Not even a clk to get freq off! Giving up.\n");
}
arch_timer_rate = clk_get_rate(clk);

Possibly the clk should even be able to override the register value,
then it's the other way around.

> +       }
> +
> +       /* Cache the sched_clock multiplier to save a divide in the hot path. */
> +
> +       sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
> +
> +       pr_info("Architected local timer running at %u.%02uMHz.\n",
> +                arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);

This multiplier and print should be moved below the call site since
the DT frequency
overrides it and then you get no print which is sad, and incorrect
sched_clock_mult
which is a bug.

> +}

(...)
> +       /* Try to determine the frequency from the device tree or CNTFRQ */
> +       if (!of_property_read_u32(np, "clock-frequency", &freq))
> +               arch_timer_rate = freq;
> +       arch_timer_calibrate();

rename arch_timer_get_freq()

And move that print here.

Yours,
Linus Walleij


From jason at lakedaemon.net  Thu Aug 16 08:43:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 08:43:44 -0400
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>
References: <20120815213221.GE15830@lunn.ch>
 <CADhrpJ4eAUdDaLF8OXvjRf6oA6ya0na-SHYs43eoNwdoEJETpA@mail.gmail.com>
 <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
 <20120815234159.GK22226@titan.lakedaemon.net>
 <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>
Message-ID: <20120816124344.GM22226@titan.lakedaemon.net>

On Thu, Aug 16, 2012 at 12:52:18AM +0100, alan butler wrote:
> On 16 August 2012 00:41, Jason Cooper <jason at lakedaemon.net> wrote:
...
> > That means gpio_keys_get_devtree_pdata() is returning an error.  Have
> > you tried 'linux,input-type = <0x05>;' ?
> 
> 'inux,input-type = <0x05>' instead of 'linux,code = <...>' in the dts?
> no i havent tried will give it a try now.

no, use both.  Look at the original gpio code you had.  It specified
both the type and the code in the struct.  gpio_keys.txt says when
input-type isn't specified it defaults to EV_KEY, whereas your code set
it to EV_SW (0x05 in include/linux/inputh:181).

hth,

Jason.


From arnd at arndb.de  Thu Aug 16 08:49:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 12:49:34 +0000
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <20120816104748.GI31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151507.36174.arnd@arndb.de>
 <20120816104748.GI31784@mudshark.cambridge.arm.com>
Message-ID: <201208161249.35008.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> On Wed, Aug 15, 2012 at 04:07:36PM +0100, Arnd Bergmann wrote:
> > On Tuesday 14 August 2012, Catalin Marinas wrote:

> > From what I can tell, there is no support for 32 bit processes debugging
> > 64 bit ones. Is that something you plan to add in the future, or do you
> > consider that out of scope? In either case, a comment would be helpful.
> 
> That can't really work because the debugger won't be able to manipulate
> child pointers properly without us adding a new ptrace interface (and then,
> I still wonder about how feasible it really is). I can add a comment.

You can already have a 32 bit gdb that is able to do remote debugging of
64 bit processes using a gdb server process. I guess it wouldn't be
too strange to have a ptrace extension to allow the native case as well.
I agree it's not a high priority.

> > > +long arch_ptrace(struct task_struct *child, long request,
> > > +		 unsigned long addr, unsigned long data)
> > > +{
> > > +	int ret;
> > > +	unsigned long *datap = (unsigned long __user *)data;
> > > +
> > > +	switch (request) {
> > > +		case PTRACE_GET_THREAD_AREA:
> > > +			ret = put_user(child->thread.tp_value, datap);
> > > +			break;
> > > +
> > > +#ifdef CONFIG_HAVE_HW_BREAKPOINT
> > > +		case PTRACE_GETHBPREGS:
> > > +			ret = ptrace_gethbpregs(child, addr, datap);
> > > +			break;
> > > +
> > > +		case PTRACE_SETHBPREGS:
> > > +			ret = ptrace_sethbpregs(child, addr, datap);
> > > +			break;
> > > +#endif
> > > +
> > > +		default:
> > > +			ret = ptrace_request(child, request, addr, data);
> > > +			break;
> > > +	}
> > > +
> > > +	return ret;
> > > +}
> > 
> > Is there a reaons why these are not regsets but have their own ptrace
> > commands? I believe new architectures should generally not add ptrace
> > commands any more.
> 
> I could probably add some regset wrappers about the hbp accessors (which we
> have to keep for the compat ptrace interface). I'll have a think as it might
> even make sense to have different regsets for breakpoints and watchpoints.
> 
> As for the the tls, is it worth having a regset with only one register?

Better ask the gdb folks. I'm adding Uli to Cc, maybe he has some insight.

	Arnd


From catalin.marinas at arm.com  Thu Aug 16 08:53:24 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 Aug 2012 13:53:24 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <201208151320.02313.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <201208151320.02313.arnd@arndb.de>
Message-ID: <20120816125324.GB30876@arm.com>

On Wed, Aug 15, 2012 at 02:20:02PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +The AArch64 exception model is made up of a number of exception levels
> > +(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
> > +counterpart.  EL2 is the hypervisor level and exists only in non-secure
> > +mode. EL3 is the highest priority level and exists only in secure mode.
> 
> I'm always confused by a description like this. It sounds like you cannot
> have a hypervisor if you have code running in secure mode in EL3. What
> I instead understand is that you enter non-secure mode by going from
> EL3 into EL2.

>From EL3 you can drop to either EL2 (non-secure) or EL1 (secure or
non-secure), it's the highest privilege level. But we don't support the
kernel entering at EL3, the SoC firmware runs in this mode. I'll try to
make it clearer.

> > +2. Setup the device tree
> > +-------------------------
> > +
> > +Requirement: MANDATORY
> > +
> > +The device tree blob (dtb) must be no bigger than 2 megabytes in size
> > +and placed at a 2-megabyte boundary within the first 512 megabytes from
> > +the start of the kernel image. This is to allow the kernel to map the
> > +blob using a single section mapping in the initial page tables.
> 
> I've seen people put firmware for some peripherals into the device tree,
> so that a device driver can grab a blob from there and load it into the
> device, rather than calling request_firmware() which would fail if the
> OS running on the system does not contain the blob. If such firmware is
> too large, you end up violating the 2 MB limit you impose here.
> 
> Should we keep that limit and declare those use cases as invalid, or
> should we try to make the boot protocol more flexible?

I would be ok to allowing larger range here but we currently don't get
the information about the size of the dtb early enough to know how much
to map. We could make some other arbitrary choice if needed like being
in the first 16MB of RAM and we map this range.

-- 
Catalin


From linus.walleij at linaro.org  Thu Aug 16 08:56:10 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 16 Aug 2012 14:56:10 +0200
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdaDi8KMk0tyWuEHGnLWhZ4ufnNY4cUm-+q9kKryBztzkw@mail.gmail.com>

On Mon, Aug 6, 2012 at 6:32 PM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> This converts the ARM RealView machine over to using the common
> clock. The approach is similar to the one used for the Integrator,
> and we're reusing the ICST wrapper code.

Mike have you had time to look at this? I got Pawel's ACK in the thread.

Yours,
Linus Walleij


From arnd at arndb.de  Thu Aug 16 09:00:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:00:32 +0000
Subject: [PATCH v2 26/31] arm64: Miscellaneous library functions
In-Reply-To: <20120816105709.GK31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151521.14663.arnd@arndb.de>
 <20120816105709.GK31784@mudshark.cambridge.arm.com>
Message-ID: <201208161300.32830.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> > > +
> > > +#include <linux/kernel.h>
> > > +#include <linux/spinlock.h>
> > > +#include <linux/atomic.h>
> > > +
> > > +#ifdef CONFIG_SMP
> > > +arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
> > > +       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
> > > +};
> > > +#endif
> > 
> > What?
> > 
> > I suppose this is a leftover from an earlier version using the
> > generic bitops, right?
> 
> We currently use the generic atomic bitops (asm-generic/bitops/atomic.h)
> which contains:
> 
> #  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
> 
> so we have to provide a definition for the array. We have additional patches
> containing optimised assembly implementations of the atomic bitops which we
> will push later, once we've got some hardware to benchmark with.
> 

Ah, I was confusing this with the asm/atomic.h stuff, for which you already
provide an optimized version.

The generic atomic bitops are really horrible in performance and I would
expect that there is just one obvious way to implement bitops using ldaxr/stlxr,
so I recommend just doing that even if you have no hardware for benchmarking.

The s390 version should be fairly easy to adapt.

	Arnd


From stigge at antcom.de  Thu Aug 16 09:13:48 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 15:13:48 +0200
Subject: [PATCH] dma: amba-pl08x: Export pl08x_filter_id
In-Reply-To: <20120816090041.GK18957@n2100.arm.linux.org.uk>
References: <1345107396-27079-1-git-send-email-stigge@antcom.de>
 <20120816090041.GK18957@n2100.arm.linux.org.uk>
Message-ID: <502CF20C.20801@antcom.de>

On 08/16/2012 11:00 AM, Russell King - ARM Linux wrote:
> On Thu, Aug 16, 2012 at 10:56:36AM +0200, Roland Stigge wrote:
>> This patch fixes the following when compiling a driver module that uses
>> amba-pl08x:
>>
>> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko] undefined!
>> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_mlc.ko] undefined!
>>
>> (drivers/mtd/nand/lpc32xx_* are still in l2-mtd.git)
> 
> It is currently intended that this be passed from platform code into
> drivers via platform data, so that drivers can decide which DMA engine
> they wish to make use of.
> 
> See how all the AMBA drivers work in this regard (because they need to
> support more than just a single DMA engine implementation.)

Thanks for the note!

I'll post respective changes to the MTD SLC and MLC drivers of LPC32xx
(for the MTD subsystem) and the adjustment I'll do in mach-lpc32xx (my
lpc32xx tree for arm-soc).


From stigge at antcom.de  Thu Aug 16 09:15:35 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 15:15:35 +0200
Subject: [PATCH] mtd: lpc32xx_mlc: Make driver independent of AMBA DMA engine
 driver
In-Reply-To: <1345122935-22115-1-git-send-email-stigge@antcom.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
Message-ID: <1345122935-22115-3-git-send-email-stigge@antcom.de>

This patch makes the MLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/mtd/nand/lpc32xx_mlc.c  |   13 +++++++++++--
 include/linux/mtd/lpc32xx_mlc.h |   20 ++++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_mlc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_mlc.c
@@ -37,7 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_mtd.h>
 #include <linux/of_gpio.h>
-#include <linux/amba/pl08x.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
@@ -171,6 +171,7 @@ static struct nand_bbt_descr lpc32xx_nan
 
 struct lpc32xx_nand_host {
 	struct nand_chip	nand_chip;
+	struct lpc32xx_mlc_platform_data *pdata;
 	struct clk		*clk;
 	struct mtd_info		mtd;
 	void __iomem		*io_base;
@@ -581,9 +582,15 @@ static int lpc32xx_dma_setup(struct lpc3
 	struct mtd_info *mtd = &host->mtd;
 	dma_cap_mask_t mask;
 
+	if (!host->pdata || !host->pdata->dma_filter) {
+		dev_err(mtd->dev.parent, "no DMA platform data\n");
+		return -ENOENT;
+	}
+
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
-	host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-mlc");
+	host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
+					     "nand-mlc");
 	if (!host->dma_chan) {
 		dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 		return -EBUSY;
@@ -703,6 +710,8 @@ static int __devinit lpc32xx_nand_probe(
 	}
 	lpc32xx_wp_disable(host);
 
+	host->pdata = pdev->dev.platform_data;
+
 	nand_chip->priv = host;		/* link the private data structures */
 	mtd->priv = nand_chip;
 	mtd->owner = THIS_MODULE;
--- /dev/null
+++ linux-2.6/include/linux/mtd/lpc32xx_mlc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC MLC NAND controller
+ *
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_MLC_H
+#define __LINUX_MTD_LPC32XX_MLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_mlc_platform_data {
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_MLC_H */


From stigge at antcom.de  Thu Aug 16 09:15:34 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 15:15:34 +0200
Subject: [PATCH] mtd: lpc32xx_slc: Make driver independent of AMBA DMA engine
 driver
In-Reply-To: <1345122935-22115-1-git-send-email-stigge@antcom.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
Message-ID: <1345122935-22115-2-git-send-email-stigge@antcom.de>

This patch makes the SLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/mtd/nand/lpc32xx_slc.c  |   13 +++++++++++--
 include/linux/mtd/lpc32xx_slc.h |   20 ++++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_slc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_slc.c
@@ -37,7 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_mtd.h>
 #include <linux/of_gpio.h>
-#include <linux/amba/pl08x.h>
+#include <linux/mtd/lpc32xx_slc.h>
 
 #define LPC32XX_MODNAME		"lpc32xx-nand"
 
@@ -199,6 +199,7 @@ struct lpc32xx_nand_cfg_slc {
 
 struct lpc32xx_nand_host {
 	struct nand_chip	nand_chip;
+	struct lpc32xx_slc_platform_data *pdata;
 	struct clk		*clk;
 	struct mtd_info		mtd;
 	void __iomem		*io_base;
@@ -714,9 +715,15 @@ static int lpc32xx_nand_dma_setup(struct
 	struct mtd_info *mtd = &host->mtd;
 	dma_cap_mask_t mask;
 
+	if (!host->pdata || !host->pdata->dma_filter) {
+		dev_err(mtd->dev.parent, "no DMA platform data\n");
+		return -ENOENT;
+	}
+
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
-	host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-slc");
+	host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
+					     "nand-slc");
 	if (!host->dma_chan) {
 		dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 		return -EBUSY;
@@ -814,6 +821,8 @@ static int __devinit lpc32xx_nand_probe(
 	}
 	lpc32xx_wp_disable(host);
 
+	host->pdata = pdev->dev.platform_data;
+
 	mtd = &host->mtd;
 	chip = &host->nand_chip;
 	chip->priv = host;
--- /dev/null
+++ linux-2.6/include/linux/mtd/lpc32xx_slc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC SLC NAND controller
+ *
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_SLC_H
+#define __LINUX_MTD_LPC32XX_SLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_slc_platform_data {
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_SLC_H */


From stigge at antcom.de  Thu Aug 16 09:15:33 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 15:15:33 +0200
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform data
Message-ID: <1345122935-22115-1-git-send-email-stigge@antcom.de>

The SLC and MLC NAND drivers now need their dma_filter callbacks via platform
data to make them independent of single DMA engine drivers.

(This also helps fixing build errors of the SLC and MLC drivers when building
as modules because direct access to AMBA dma filter functions isn't available
via export.)

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.6-rc1

 arch/arm/mach-lpc32xx/phy3250.c |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -223,6 +225,14 @@ static struct mmci_platform_data lpc32xx
 	 * gather, and the MMCI driver doesn't do it this way */
 };
 
+static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
+	.dma_filter = pl08x_filter_id,
+};
+
+static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
+	.dma_filter = pl08x_filter_id,
+};
+
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
 	OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
@@ -230,6 +240,10 @@ static const struct of_dev_auxdata lpc32
 	OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
 	OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
 		       &lpc32xx_mmci_data),
+	OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
+		       &lpc32xx_slc_data),
+	OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
+		       &lpc32xx_mlc_data),
 	{ }
 };
 


From anilkumar at ti.com  Thu Aug 16 09:22:27 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Thu, 16 Aug 2012 13:22:27 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <20120815165431.GF15365@opensource.wolfsonmicro.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>

Mark,

On Wed, Aug 15, 2012 at 22:24:32, Mark Brown wrote:
> On Wed, Aug 15, 2012 at 04:47:02PM +0000, AnilKumar, Chimata wrote:
> > On Wed, Aug 15, 2012 at 18:23:39, Mark Brown wrote:
> 
> > > If you have all these unrelated supplies in the system then your device
> > > tree should accurately reflect that.  However this would be a very
> 
> > In that case I have to add all these fixed regulators.
> 
> Why?  You then immediately go on to say...

Because all the nodes/regulators should be provided/registered otherwise
"regulator_dev_lookup" returns NULL if there are no regulator matches with
the supply_name.

I have gone through this thread
http://patchwork.ozlabs.org/patch/166682/

But problem here is single input supply battery/main is not sufficient.

pmic->desc[i].supply_name = info->vin_name;
with this assignment regulator core searches for exact supply name vcc1 or
vcc2 etc if there are no matches then it will not register any regulators. 

> 
> > > unusual hardware design.  Usually there would be a very small set of
> > > system supply rails, frequently only one.
> 
> > In case of AM335X-EVM one dedicated supply (5v) feeding to all the input
> > supplies (vcc1-7 and vccio) of the regulators.
> 
> ...that they all map onto the same physical supply?
> 

Yes single physical supply, if we want to add single fixed regulator node
to feed all the regulators then driver have to modify to support this.
Similar to revert of "regulator: tps65910: add support for input supply"
Patch.

Thanks
AnilKumar


From anilkumar at ti.com  Thu Aug 16 09:25:23 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Thu, 16 Aug 2012 13:25:23 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com> 
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA13D5D@DBDE01.ent.ti.com>

Mark,

Small correction

On Thu, Aug 16, 2012 at 18:52:25, AnilKumar, Chimata wrote:
> Mark,
> 
> On Wed, Aug 15, 2012 at 22:24:32, Mark Brown wrote:
> > On Wed, Aug 15, 2012 at 04:47:02PM +0000, AnilKumar, Chimata wrote:
> > > On Wed, Aug 15, 2012 at 18:23:39, Mark Brown wrote:
> > 
> > > > If you have all these unrelated supplies in the system then your device
> > > > tree should accurately reflect that.  However this would be a very
> > 
> > > In that case I have to add all these fixed regulators.
> > 
> > Why?  You then immediately go on to say...
> 
> Because all the nodes/regulators should be provided/registered otherwise
> "regulator_dev_lookup" returns NULL if there are no regulator matches with
> the supply_name.
> 
> I have gone through this thread
> http://patchwork.ozlabs.org/patch/166682/
> 
> But problem here is single input supply battery/main is not sufficient.
> 
> pmic->desc[i].supply_name = info->vin_name;
> with this assignment regulator core searches for exact supply name vcc1 or
> vcc2 etc if there are no matches then it will not register any regulators. 
> 
> > 
> > > > unusual hardware design.  Usually there would be a very small set of
> > > > system supply rails, frequently only one.
> > 
> > > In case of AM335X-EVM one dedicated supply (5v) feeding to all the input
> > > supplies (vcc1-7 and vccio) of the regulators.
> > 
> > ...that they all map onto the same physical supply?
> > 
> 
> Yes single physical supply, if we want to add single fixed regulator node
> to feed all the regulators then driver have to modify to support this.
> Similar to revert of "regulator: tps65910: add support for input supply"
                       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Copy/paste error

Similar to revert of this patch "regulator: tps65910: set input_supply on
desc unconditionally"

Thanks
AnilKumar



From jason at lakedaemon.net  Thu Aug 16 09:28:39 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 09:28:39 -0400
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120816132839.GO22226@titan.lakedaemon.net>

On Mon, Aug 06, 2012 at 11:42:16AM +0200, Thomas Petazzoni wrote:
> Andrew, Jason, Gr?gory,
> 
> Here is a small patch set that introduces basic support for address
> decoding on Armada 370 and Armada XP. The aim of this basic support is
> essentially to be able to configure a window to remap the BootROM,
> which is needed to startup the secondary CPUs for the SMP support.
> 
> As we had discussed already, the address decoding configuration is not
> described in the Device Tree, it is for now hardcoded on a per-SoC
> basis. We might later discuss how to extend this to the Device Tree.
> 
> This patch set has five patches:
> 
>  (*) First patch reworks the addr-map code to use void __iomem * where
>      appropriate instead of u32, as per the suggestion of Arnd
>      Bergmann.
> 
>  (*) Second patch introducing PLAT_ORION_LEGACY, which allows the
>      Marvell 370/XP platforms to be part of PLAT_ORION, and therefore
>      re-use the existing address decoding code.
> 
>  (*) Third patch making a small change to an address decoding
>      structure so that we can define at runtime the virtual address of
>      the configuration registers. This is needed as on Armada 370/XP
>      the address decoding "controller" is declared in the Device Tree.
> 
>  (*) Fourth patch adding the 370/XP address decoding code itself. For
>      now, it only maps the BootROM on Armada XP.
> 
>  (*) Fifth path adding the necessary DT code to instantiate the
>      address decoding "controller".
> 
> Changes since v2:
>  * Remove one more useless (void __iomem *) cast in the Armada 370/XP
>    addr-map.c file, as noticed by Arnd Bergmann.
> 
> Changes since v1:
>  * Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
>  * Add Acked-by on patches 2->5 from Gr?gory Cl?ment

Whole series applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

thx,

Jason.


From jason at lakedaemon.net  Thu Aug 16 09:35:21 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 09:35:21 -0400
Subject: [PATCH v2 1/2] ARM: kirkwood: DT board setup for Seagate
 FreeAgent Dockstar
In-Reply-To: <20120814232256.GX22226@titan.lakedaemon.net>
References: <20120814193613.GS22226@titan.lakedaemon.net>
 <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20120814232256.GX22226@titan.lakedaemon.net>
Message-ID: <20120816133521.GP22226@titan.lakedaemon.net>

On Tue, Aug 14, 2012 at 07:22:56PM -0400, Jason Cooper wrote:
> On Tue, Aug 14, 2012 at 10:43:41PM +0200, Sebastian Hesselbarth wrote:
> > This add a DT compatible board specific setup for the Seagate
> > FreeAgent Dockstar.
> > 
> > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> > ---
> > Cc: Jason Cooper <jason at lakedaemon.net>
> > Cc: Andrew Lunn <andrew at lunn.ch>
> > Cc: Russell King <linux at arm.linux.org.uk>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: linux-kernel at vger.kernel.org
> > 
> > v2: rebased on git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
> 
> patches [1/2] and [2/2] of this series applied to:
> 
>   git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
> 
> patch [2/2] depends upon:
> 
>   bda63c1 ARM: Kirkwood: fix Makefile.boot
> 
> which should be in an upcoming v3.6-rc

Oops, building with both legacy and DT support for the Dockstar yields
the following error:

arch/arm/mach-kirkwood/dockstar-setup.c:81:20: error: static declaration
of 'dockstar_init' follows non-static declaration
arch/arm/mach-kirkwood/common.h:86:6: note: previous declaration of
'dockstar_init' was here
make[1]: *** [arch/arm/mach-kirkwood/dockstar-setup.o] Error 1
make: *** [arch/arm/mach-kirkwood] Error 2

As a quick fix I renamed your dockstar_init() to dockstar_dt_init()
across your patch.  This compiles clean.  Unfortunately, I can't send
this fix up as a separate patch (a bisect may land in between it and
yours).

Unless I hear otherwise from you in the next day or so, I'm going to
collapse the fix into your patch and push it that way.

thx,

Jason.


From peter.ujfalusi at ti.com  Thu Aug 16 09:40:59 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:40:59 +0300
Subject: [PATCH v3 0/9] ARM/ASoC: OMAP McBSP device tree support
Message-ID: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v2:
- Replaced the IS_ERR_OR_NULL() with IS_ERR()

Changes since v1:
- ICLK workaround for the sidetone module has been kept for legacy mode.

Intro mail from v2:

in order to be able to add DT support for the McBSP driver which is used on all
OMAP platforms (OMAP1/2/3/4/5) I needed to make some cleanups to the stack:
- Removing callbacks used by the driver for
 - clock re-parenting (code moved to sound driver)
 - FSR/CLKR mux configuration (from now on it need to be done at board level)
   This mux is board specific and depends on the wiring.
- Replaced the cpu_is_omap* checks with future proof check.
- The FIFO was not enabled on OMAP2430 SoC

It has been tested on BeagleBoard (with legacy and DT boot).

The series changes McBSP related files mostly. It would be great if the whole
series could go via audio tree (if the patches are OK and it is fine by Tony).

For DT booted kernel on OMAP3 proper ICLK woraround need to be implemented. At
the moment I don't see this as a stopper since we can not properly boot OMAP3
devices (especially rx51 which is using the ST). Other OMAP revisions does not
have ST block so the missing workaround is not going to hurt them.
I'm working on a solution which can replace the current workaround with a
generic implementation to support DT and non DT booted kernels.

Regards,
Peter
---
Peter Ujfalusi (9):
  ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code to ASoC driver
  ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
  ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR signal source
  ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR signal muxing
  ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux configuration code
  ASoC: omap-mcbsp: Remove unused defines
  ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the code
  ARM: OMAP2+: McBSP: Do not create legacy devices when booting with DT
    data
  ASoC: omap-mcbsp: Add device tree bindings

 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 +++++++
 arch/arm/mach-omap2/board-am3517evm.c              |   13 ++
 arch/arm/mach-omap2/mcbsp.c                        |  126 +------------------
 arch/arm/plat-omap/include/plat/mcbsp.h            |    2 -
 sound/soc/omap/am3517evm.c                         |   20 +---
 sound/soc/omap/mcbsp.c                             |   54 ++++-----
 sound/soc/omap/mcbsp.h                             |    3 -
 sound/soc/omap/omap-mcbsp.c                        |  106 +++++++++++-----
 sound/soc/omap/omap-mcbsp.h                        |   20 ---
 9 files changed, 162 insertions(+), 227 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:00 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:00 +0300
Subject: [PATCH v3 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting code
 to ASoC driver
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-2-git-send-email-peter.ujfalusi@ti.com>

Move the McBSP CLKS re-parenting code to ASoC driver from
arch/arm/mach-omap2.
The call fort the re-parenting has been already limited to OMAP2+ SoC in
the ASoC driver. There is no longer need to have callback function for it.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   40 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ++++++++++++++++++++----
 3 files changed, 26 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 577cb77..ebc801e 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -101,45 +101,6 @@ static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
 	return 0;
 }
 
-/* McBSP CLKS source switching function */
-static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
-				   const char *src)
-{
-	struct clk *fck_src;
-	char *fck_src_name;
-	int r;
-
-	if (!strcmp(src, "clks_ext"))
-		fck_src_name = "pad_fck";
-	else if (!strcmp(src, "clks_fclk"))
-		fck_src_name = "prcm_fck";
-	else
-		return -EINVAL;
-
-	fck_src = clk_get(dev, fck_src_name);
-	if (IS_ERR_OR_NULL(fck_src)) {
-		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
-		       fck_src_name);
-		return -EINVAL;
-	}
-
-	pm_runtime_put_sync(dev);
-
-	r = clk_set_parent(clk, fck_src);
-	if (IS_ERR_VALUE(r)) {
-		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
-		       "clks", fck_src_name);
-		clk_put(fck_src);
-		return -EINVAL;
-	}
-
-	pm_runtime_get_sync(dev);
-
-	clk_put(fck_src);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -181,7 +142,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->reg_size = 4;
 		pdata->has_ccr = true;
 	}
-	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
 
 	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
 	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 1881412..0a7d5ca 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
 	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index d33c48b..935ccf6 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <plat/mcbsp.h>
 
@@ -726,19 +727,39 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 {
+	struct clk *fck_src;
 	const char *src;
+	int r;
 
 	if (fck_src_id == MCBSP_CLKS_PAD_SRC)
-		src = "clks_ext";
+		src = "pad_fck";
 	else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
-		src = "clks_fclk";
+		src = "prcm_fck";
 	else
 		return -EINVAL;
 
-	if (mcbsp->pdata->set_clk_src)
-		return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
-	else
+	fck_src = clk_get(mcbsp->dev, src);
+	if (IS_ERR(fck_src)) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
 		return -EINVAL;
+	}
+
+	pm_runtime_put_sync(mcbsp->dev);
+
+	r = clk_set_parent(mcbsp->fclk, fck_src);
+	if (r) {
+		dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
+			src);
+		clk_put(fck_src);
+		return r;
+	}
+
+	pm_runtime_get_sync(mcbsp->dev);
+
+	clk_put(fck_src);
+
+	return 0;
+
 }
 
 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:03 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:03 +0300
Subject: [PATCH v3 4/9] ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR
 signal muxing
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-5-git-send-email-peter.ujfalusi@ti.com>

The muxing is done at board level, no need to do it in the ASoC machine
driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/am3517evm.c |   20 ++------------------
 1 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/sound/soc/omap/am3517evm.c b/sound/soc/omap/am3517evm.c
index 009533a..a997988 100644
--- a/sound/soc/omap/am3517evm.c
+++ b/sound/soc/omap/am3517evm.c
@@ -47,26 +47,10 @@ static int am3517evm_hw_params(struct snd_pcm_substream *substream,
 	/* Set the codec system clock for DAC and ADC */
 	ret = snd_soc_dai_set_sysclk(codec_dai, 0,
 			CODEC_CLOCK, SND_SOC_CLOCK_IN);
-	if (ret < 0) {
+	if (ret < 0)
 		printk(KERN_ERR "can't set codec system clock\n");
-		return ret;
-	}
-
-	ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_CLKR_SRC_CLKX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_CLKR_SRC_CLKX\n");
-		return ret;
-	}
 
-	snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_FSR_SRC_FSX, 0,
-				SND_SOC_CLOCK_IN);
-	if (ret < 0) {
-		printk(KERN_ERR "can't set CPU system clock OMAP_MCBSP_FSR_SRC_FSX\n");
-		return ret;
-	}
-
-	return 0;
+	return ret;
 }
 
 static struct snd_soc_ops am3517evm_ops = {
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:02 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:02 +0300
Subject: [PATCH v3 3/9] ARM: OMAP: board-am3517evm: Configure McBSP1 CLKR/FSR
 signal source
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-4-git-send-email-peter.ujfalusi@ti.com>

am3517evm board uses McBSP1 for audio with 4pin configuration.
The CLKR/FSR signals need to be connected to CLKX/FSX pin of the SoC in
this case.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/board-am3517evm.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f6010..592812a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -264,6 +264,16 @@ static __init void am3517_evm_musb_init(void)
 	usb_musb_init(&musb_board_data);
 }
 
+static __init void am3517_evm_mcbsp1_init(void)
+{
+	u32 devconf0;
+
+	/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
+	devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
+	omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
+}
+
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -373,6 +383,9 @@ static void __init am3517_evm_init(void)
 	/* MUSB */
 	am3517_evm_musb_init();
 
+	/* McBSP1 */
+	am3517_evm_mcbsp1_init();
+
 	/* MMC init function */
 	omap_hsmmc_init(mmc);
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:05 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:05 +0300
Subject: [PATCH v3 6/9] ASoC: omap-mcbsp: Remove unused defines
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-7-git-send-email-peter.ujfalusi@ti.com>

NUM_LINKS is no longer in use by the code.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/omap-mcbsp.h |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index baebcee..ba8386a 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -39,22 +39,6 @@ enum omap_mcbsp_div {
 	OMAP_MCBSP_CLKGDV,		/* Sample rate generator divider */
 };
 
-#if defined(CONFIG_SOC_OMAP2420)
-#define NUM_LINKS	2
-#endif
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-#undef  NUM_LINKS
-#define NUM_LINKS	3
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-#undef  NUM_LINKS
-#define NUM_LINKS	4
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430)
-#undef  NUM_LINKS
-#define NUM_LINKS	5
-#endif
-
 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd);
 
 #endif
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:04 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:04 +0300
Subject: [PATCH v3 5/9] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux
 configuration code
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>

Remove the feature to configure the CLKR/FSR mux on McBSP port with 6pin
configuration.
When moving to devicetree these callback can no longer be used in a clean
way anymore.
If a board require to change the 6pin port to work in 4pin setup it needs
to set up the mux in the board file.
For OMAP2/3:
u32 devconf0;

/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);

For OMAP4:
u32 mcbsp_pad;

/* McBSP4 CLKR/FSR signal to be connected to CLKX/FSX pin */
mcbsp_pad = omap4_ctrl_pad_readl(OMAP2_CONTROL_DEVCONF0);
mcbsp_pad |=  ((1 << 31) | (1 << 30));
omap4_ctrl_pad_writel(mcbsp_pad, OMAP2_CONTROL_DEVCONF0);

In case when the kernel is booted with DT blob the pinctrl-single will be
provided as soon as it is enabled on the platform.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c             |   77 -------------------------------
 arch/arm/plat-omap/include/plat/mcbsp.h |    1 -
 sound/soc/omap/mcbsp.c                  |   31 ------------
 sound/soc/omap/mcbsp.h                  |    3 -
 sound/soc/omap/omap-mcbsp.c             |   32 +------------
 sound/soc/omap/omap-mcbsp.h             |    4 --
 6 files changed, 3 insertions(+), 145 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 6e046e1..660e00b 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,8 +25,6 @@
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
-#include "control.h"
-
 /*
  * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
  * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,73 +32,6 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP2_MCBSP1_CLKR_MASK;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP2_MCBSP1_CLKR_MASK;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP2_MCBSP1_FSR_MASK;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP2_MCBSP1_FSR_MASK;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-
-	return 0;
-}
-
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
-				   const char *src)
-{
-	u32 v;
-
-	/*
-	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
-	 * mux) is used */
-	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	if (!strcmp(signal, "clkr")) {
-		if (!strcmp(src, "clkr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else if (!strcmp(src, "clkx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
-		else
-			return -EINVAL;
-	} else if (!strcmp(signal, "fsr")) {
-		if (!strcmp(src, "fsr"))
-			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else if (!strcmp(src, "fsx"))
-			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
-		else
-			return -EINVAL;
-	} else {
-		return -EINVAL;
-	}
-
-	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
-	return 0;
-}
-
 static int omap3_enable_st_clock(unsigned int id, bool enable)
 {
 	unsigned int w;
@@ -143,14 +74,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->has_ccr = true;
 	}
 
-	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
-	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
-
-	/* On OMAP4 the McBSP4 port has 6 pin configuration */
-	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
-		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
-
 	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
 		/* The FIFO has 128 locations */
 		pdata->buffer_size = 0x80;
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 0a7d5ca..c78d90b 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
 	bool has_wakeup; /* Wakeup capability */
 	bool has_ccr; /* Transceiver has configuration control registers */
 	int (*enable_st_clock)(unsigned int, bool);
-	int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
 /**
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index 935ccf6..bc06175 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -762,37 +762,6 @@ int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 
 }
 
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
-{
-	const char *signal, *src;
-
-	if (!mcbsp->pdata->mux_signal)
-		return -EINVAL;
-
-	switch (mux) {
-	case CLKR_SRC_CLKR:
-		signal = "clkr";
-		src = "clkr";
-		break;
-	case CLKR_SRC_CLKX:
-		signal = "clkr";
-		src = "clkx";
-		break;
-	case FSR_SRC_FSR:
-		signal = "fsr";
-		src = "fsr";
-		break;
-	case FSR_SRC_FSX:
-		signal = "fsr";
-		src = "fsx";
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
-}
-
 #define max_thres(m)			(mcbsp->pdata->buffer_size)
 #define valid_threshold(m, val)		((val) <= max_thres(m))
 #define THRESHOLD_PROP_BUILDER(prop)					\
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index 262a615..49a6725 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -334,9 +334,6 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
 /* McBSP functional clock source changing function */
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
 
-/* McBSP signal muxing API */
-int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux);
-
 /* Sidetone specific API */
 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain);
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 1046083..5061594 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -516,21 +516,9 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 			return -EBUSY;
 	}
 
-	if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
-	    clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
-		mcbsp->in_freq = freq;
-		regs->srgr2	&= ~CLKSM;
-		regs->pcr0	&= ~SCLKME;
-	} else if (cpu_class_is_omap1()) {
-		/*
-		 * McBSP CLKR/FSR signal muxing functions are only available on
-		 * OMAP2 or newer versions
-		 */
-		return -EINVAL;
-	}
+	mcbsp->in_freq = freq;
+	regs->srgr2 &= ~CLKSM;
+	regs->pcr0 &= ~SCLKME;
 
 	switch (clk_id) {
 	case OMAP_MCBSP_SYSCLK_CLK:
@@ -558,20 +546,6 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 		regs->pcr0	|= SCLKME;
 		break;
-
-
-	case OMAP_MCBSP_CLKR_SRC_CLKR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
-		break;
-	case OMAP_MCBSP_CLKR_SRC_CLKX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSR:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
-		break;
-	case OMAP_MCBSP_FSR_SRC_FSX:
-		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
-		break;
 	default:
 		err = -ENODEV;
 	}
diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
index f877b16..baebcee 100644
--- a/sound/soc/omap/omap-mcbsp.h
+++ b/sound/soc/omap/omap-mcbsp.h
@@ -32,10 +32,6 @@ enum omap_mcbsp_clksrg_clk {
 	OMAP_MCBSP_SYSCLK_CLK,		/* Internal ICLK */
 	OMAP_MCBSP_SYSCLK_CLKX_EXT,	/* External CLKX pin */
 	OMAP_MCBSP_SYSCLK_CLKR_EXT,	/* External CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKR,	/* CLKR from CLKR pin */
-	OMAP_MCBSP_CLKR_SRC_CLKX,	/* CLKR from CLKX pin */
-	OMAP_MCBSP_FSR_SRC_FSR,		/* FSR from FSR pin */
-	OMAP_MCBSP_FSR_SRC_FSX,		/* FSR from FSX pin */
 };
 
 /* McBSP dividers */
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:06 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:06 +0300
Subject: [PATCH v3 7/9] ASoC: omap-mcbsp: Remove cpu_is_omap* checks from the
 code
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-8-git-send-email-peter.ujfalusi@ti.com>

We can use the has_ccr flag to replace the cpu_is_omap* checks.
This provides future proof implementation and we do not need to update the
code if new OMAP revision starts to use the McBSP driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/omap-mcbsp.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 5061594..b9770ee 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -398,12 +398,14 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	/* Generic McBSP register settings */
 	regs->spcr2	|= XINTM(3) | FREE;
 	regs->spcr1	|= RINTM(3);
-	/* RFIG and XFIG are not defined in 34xx */
-	if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
+	/* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
+	if (!mcbsp->pdata->has_ccr) {
 		regs->rcr2	|= RFIG;
 		regs->xcr2	|= XFIG;
 	}
-	if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
+
+	/* Configure XCCR/RCCR only for revisions which have ccr registers */
+	if (mcbsp->pdata->has_ccr) {
 		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 	}
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:07 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:07 +0300
Subject: [PATCH v3 8/9] ARM: OMAP2+: McBSP: Do not create legacy devices when
 booting with DT data
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-9-git-send-email-peter.ujfalusi@ti.com>

Only create the devices in a legacy way if we do not have the DT data.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/mcbsp.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 660e00b..d57a357 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -113,7 +114,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 
 static int __init omap2_mcbsp_init(void)
 {
-	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+	if (!of_have_populated_dt())
+		omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
 	return 0;
 }
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:08 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:08 +0300
Subject: [PATCH v3 9/9] ASoC: omap-mcbsp: Add device tree bindings
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-10-git-send-email-peter.ujfalusi@ti.com>

Device tree support for McBSP modules on OMAP2+ SoC.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 .../devicetree/bindings/sound/omap-mcbsp.txt       |   45 +++++++++++++
 sound/soc/omap/omap-mcbsp.c                        |   66 +++++++++++++++++++-
 2 files changed, 110 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/omap-mcbsp.txt

diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
new file mode 100644
index 0000000..447cb13
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -0,0 +1,45 @@
+* Texas Instruments OMAP2+ McBSP module
+
+Required properties:
+- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
+	      "ti,omap2430-mcbsp" for McBSP on OMAP2430
+	      "ti,omap3-mcbsp" for McBSP on OMAP3
+	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
+- reg: Register location and size, for OMAP4+ as an array:
+       <MPU access base address, size>,
+       <L3 interconnect address, size>;
+- interrupts: Interrupt numbers for the McBSP port, as an array in case the
+	      McBSP IP have more interrupt lines:
+	<OCP compliant irq>,
+	<TX irq>,
+	<RX irq>;
+- interrupt-parent: The parent interrupt controller
+- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
+- ti,hwmods: Name of the hwmod associated to the McBSP port
+
+Sidetone support for OMAP3 McBSP2 and 3 ports:
+- sidetone { }: Within this section the following parameters are required:
+- reg: Register location and size for the ST block
+- interrupts: The interrupt number for the ST block
+- interrupt-parent: The parent interrupt controller for the ST block
+
+Example:
+
+mcbsp2: mcbsp at 49022000 {
+	compatible = "ti,omap3-mcbsp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0x49022000 0xff>;
+	interrupts = <0 17 0x4>, /* OCP compliant interrup */
+		     <0 62 0x4>, /* TX interrup */
+		     <0 63 0x4>; /* RX interrup */
+	interrupt-parent = <&intc>;
+	ti,buffer-size = <1280>;
+	ti,hwmods = "mcbsp2";
+
+	sidetone {
+		reg = <0x49028000 0xff>;
+		interrupts = <0 4 0x4>;
+		interrupt-parent = <&intc>;
+	};
+};
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index b9770ee..2e1750e 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -26,6 +26,8 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -737,13 +739,74 @@ int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 }
 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 
+static struct omap_mcbsp_platform_data omap2420_pdata = {
+	.reg_step = 4,
+	.reg_size = 2,
+};
+
+static struct omap_mcbsp_platform_data omap2430_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+};
+
+static struct omap_mcbsp_platform_data omap3_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static struct omap_mcbsp_platform_data omap4_pdata = {
+	.reg_step = 4,
+	.reg_size = 4,
+	.has_ccr = true,
+	.has_wakeup = true,
+};
+
+static const struct of_device_id omap_mcbsp_of_match[] = {
+	{
+		.compatible = "ti,omap2420-mcbsp",
+		.data = &omap2420_pdata,
+	},
+	{
+		.compatible = "ti,omap2430-mcbsp",
+		.data = &omap2430_pdata,
+	},
+	{
+		.compatible = "ti,omap3-mcbsp",
+		.data = &omap3_pdata,
+	},
+	{
+		.compatible = "ti,omap4-mcbsp",
+		.data = &omap4_pdata,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
+
 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 {
 	struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 	struct omap_mcbsp *mcbsp;
+	const struct of_device_id *match;
 	int ret;
 
-	if (!pdata) {
+	match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
+	if (match) {
+		struct device_node *node = pdev->dev.of_node;
+		int buffer_size;
+
+		pdata = devm_kzalloc(&pdev->dev,
+				     sizeof(struct omap_mcbsp_platform_data),
+				     GFP_KERNEL);
+		if (!pdata)
+			return -ENOMEM;
+
+		memcpy(pdata, match->data, sizeof(*pdata));
+		if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
+			pdata->buffer_size = buffer_size;
+	} else if (!pdata) {
 		dev_err(&pdev->dev, "missing platform data.\n");
 		return -EINVAL;
 	}
@@ -785,6 +848,7 @@ static struct platform_driver asoc_mcbsp_driver = {
 	.driver = {
 			.name = "omap-mcbsp",
 			.owner = THIS_MODULE,
+			.of_match_table = omap_mcbsp_of_match,
 	},
 
 	.probe = asoc_mcbsp_probe,
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 16 09:41:01 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 16 Aug 2012 16:41:01 +0300
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>

On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
the FIFO for the audio stack.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index ebc801e..6e046e1 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -151,7 +151,10 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
 		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
 
-	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
+		/* The FIFO has 128 locations */
+		pdata->buffer_size = 0x80;
+	} else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
 		if (id == 2)
 			/* The FIFO has 1024 + 256 locations */
 			pdata->buffer_size = 0x500;
-- 
1.7.8.6



From sebastian.hesselbarth at gmail.com  Thu Aug 16 09:45:00 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 16 Aug 2012 15:45:00 +0200
Subject: [PATCH v2 1/2] ARM: kirkwood: DT board setup for Seagate
 FreeAgent Dockstar
In-Reply-To: <20120816133521.GP22226@titan.lakedaemon.net>
References: <20120814193613.GS22226@titan.lakedaemon.net>
 <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20120814232256.GX22226@titan.lakedaemon.net>
 <20120816133521.GP22226@titan.lakedaemon.net>
Message-ID: <CABJ1b_Q0TuhoUvM_hGVecLWnPn9pWf_UvUPyyUscK1yf8g7Q-g@mail.gmail.com>

On 8/16/12, Jason Cooper <jason at lakedaemon.net> wrote:
> Unless I hear otherwise from you in the next day or so, I'm going to
> collapse the fix into your patch and push it that way.

Jason,

please feel free to fix the patch. I am behind corporate firewall ATM
and cannot update the patch quickly.

Sebastian


From arnd at arndb.de  Thu Aug 16 09:44:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:44:55 +0000
Subject: [PATCH 0/6] Integrator devicetree support
In-Reply-To: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
References: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <201208161344.55723.arnd@arndb.de>

On Thursday 16 August 2012, Linus Walleij wrote:
> This patch set moves all the non-DT platform code into
> #ifndef CONFIG_OF sections for clarity. The plan is to
> delete them after deprecation.

I'm fine with your playing around with this in any way you
like, but I think in general we should have a new CONFIG_ATAG
symbol, so you can build a kernel that supports booting
both with and without DT for the same platform, depending
on what the boot loader supports.

Then you can enclose all the non-DT sections in #ifdef
CONFIG_ATAG and we can remove them at some later stage.

> - The special PCI adapter in the Integrator has to be DT:ed,
>   but AFAICT there is still a problem with how to represent
>   these things in DT. Any hints/examples, Arnd, Rob?
>   arch/arm/mach-integrator/pci_v3.c

PCI bindings are a bit tricky but they are well-defined,
see www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf

The main thing to understand is the use of 3-cell address
spaces and the interrupt map. Each PCI host must have

         #interrupt-cells = <1>;
         #size-cells = <2>;
         #address-cells = <3>;

The "ranges" property is used to transform the PCI
address space into the host address space.

The first cell identifies the device and address space
using a bit-masked notation. The important part to
know here is 

0x00000000 config space
0x01000000 I/O space
0x02000000 memory space
0x03000000 64 bit memory space
0x42000000 memory space, prefetchable
0x43000000 64 bit memory space, prefetchable

Each entry in the ranges property consists of 3 cells
for the PCI address start, one cell for a 32 bit parent
but start address where this is mapped, and two cells for
the size.
For your bus, the ranges then would be defined as 

ranges = <0x00000000 0x00000000 0x00000000 /* configuration space: */
	  0x61000000 0x00000000 0x00100000 /* 16 MB at 61000000    */
	  0x01000000 0x00000000 0x00000000 /* I/O space:	   */
	  0x60000000 0x00000000 0x00010000 /* 64KB at 0x60000000   */
	  0x02000000 0x00000000 0x40000000 /* non-prefetchable mem */
	  0x40000000 0x00000000 0x10000000 /* identity-mapped      */
	  0x42000000 0x00000000 0x50000000 /* prefetchable mem     */
	  0x50000000 0x00000000 0x10000000> /* identity-mapped     */

I'm not quite sure if I understood the comments about LB_BASE0 etc
correctly, so it might actually be different.

You also need an interrupt-map, which maps the slots to the
connected irq lines in a board-specific way:

interrupt-map = <
	/* IDSEL 9 */
	0x4800 0 0 1 &pic 14 /* INT A on slot 9 is irq 14 */
	0x4800 0 0 2 &pic 15 /* INT B on slot 9 is irq 15 */
	0x4800 0 0 3 &pic 16 /* INT C on slot 9 is irq 16 */
	0x4800 0 0 4 &pic 17 /* INT D on slot 9 is irq 17 */

	/* IDSEL 10 */
	0x5000 0 0 1 &pic 15 /* INT A on slot 10 is irq 15 */
	0x5000 0 0 2 &pic 16 /* INT B on slot 10 is irq 16 */
	0x5000 0 0 3 &pic 17 /* INT C on slot 10 is irq 17 */
	0x5000 0 0 4 &pic 14 /* INT D on slot 10 is irq 18 */

	/* IDSEL 11 */
	0x5800 0 0 1 &pic 16 /* INT A on slot 11 is irq 16 */
	0x5800 0 0 2 &pic 17 /* INT B on slot 11 is irq 17 */
	0x5800 0 0 3 &pic 14 /* INT C on slot 11 is irq 18 */
	0x5800 0 0 4 &pic 15 /* INT D on slot 11 is irq 14 */

	/* IDSEL 12 */
	0x6000 0 0 1 &pic 17 /* INT A on slot 12 is irq 17 */
	0x6000 0 0 2 &pic 14 /* INT B on slot 12 is irq 14 */
	0x6000 0 0 3 &pic 15 /* INT C on slot 12 is irq 15 */
	0x6000 0 0 4 &pic 16 /* INT D on slot 12 is irq 16 */
	>;

	Arnd


From arnd at arndb.de  Thu Aug 16 09:45:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:45:46 +0000
Subject: [PATCH 1/6] ARM: integrator: call common init function from
 machine
In-Reply-To: <1345119339-22638-1-git-send-email-linus.walleij@linaro.org>
References: <1345119339-22638-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <201208161345.46346.arnd@arndb.de>

On Thursday 16 August 2012, Linus Walleij wrote:
> There is currently a common integrator_init() function set up
> to be called from an arch_initcall(). The problem is that it is
> using machine_is_integrator() which is not working with device
> tree, let's call this from respective machine initilization
> function and add a parameter to tell whether it's the
> Integrator/AP or Integrator/CP instead.
> 
> There are still machine_is*() calls in the Integrator
> machines directory, but this one needs to be fixed lest we
> don't even get a UART console on the Integrator/AP after a
> Device Tree boot.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From jason at lakedaemon.net  Thu Aug 16 09:47:49 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 09:47:49 -0400
Subject: [PATCH v2 1/2] ARM: kirkwood: DT board setup for Seagate
 FreeAgent Dockstar
In-Reply-To: <CABJ1b_Q0TuhoUvM_hGVecLWnPn9pWf_UvUPyyUscK1yf8g7Q-g@mail.gmail.com>
References: <20120814193613.GS22226@titan.lakedaemon.net>
 <1344977022-29037-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <20120814232256.GX22226@titan.lakedaemon.net>
 <20120816133521.GP22226@titan.lakedaemon.net>
 <CABJ1b_Q0TuhoUvM_hGVecLWnPn9pWf_UvUPyyUscK1yf8g7Q-g@mail.gmail.com>
Message-ID: <20120816134749.GR22226@titan.lakedaemon.net>

On Thu, Aug 16, 2012 at 03:45:00PM +0200, Sebastian Hesselbarth wrote:
> On 8/16/12, Jason Cooper <jason at lakedaemon.net> wrote:
> > Unless I hear otherwise from you in the next day or so, I'm going to
> > collapse the fix into your patch and push it that way.
> 
> please feel free to fix the patch. I am behind corporate firewall ATM
> and cannot update the patch quickly.

Done.

thx,

Jason.


From arnd at arndb.de  Thu Aug 16 09:50:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:50:48 +0000
Subject: [PATCH 3/6] ARM: plat-versatile: add DT support to FPGA IRQ
 controller
In-Reply-To: <1345119357-22702-1-git-send-email-linus.walleij@linaro.org>
References: <1345119357-22702-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <201208161350.49063.arnd@arndb.de>

On Thursday 16 August 2012, Linus Walleij wrote:
> +- irq-start: the u32 hardware IRQ number of the first interrupt handled by
> +  this FPGA IRQ instance - since there may be many FPGA IRQ controller
> +  instances, each will have its unique hardware offset number.

The irq-start value is a Linux specific invention, the hardware doesn't
know anything about these. As long as you depend on specific IRQ numbers
to get assigned, I would use something like auxdata to find the
start number. When all devices get their IRQ numbers from the device
tree, you can move to linear IRQ domains instead of legacy, and let
the irq domain code pick the numbers.

	Arnd


From jon-hunter at ti.com  Thu Aug 16 09:56:06 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 16 Aug 2012 08:56:06 -0500
Subject: [PATCH 1/9] ARM: PMU: Add runtime PM Support
In-Reply-To: <20120813104006.GA20537@mudshark.cambridge.arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-2-git-send-email-will.deacon@arm.com>
 <CACVXFVMg5Acx4_KGT5jn1JgO3JsXAjZzU8virR=B3+pBrT4o_A@mail.gmail.com>
 <20120813104006.GA20537@mudshark.cambridge.arm.com>
Message-ID: <502CFBF6.7050404@ti.com>


On 08/13/2012 05:40 AM, Will Deacon wrote:
> On Sat, Aug 11, 2012 at 04:09:51PM +0100, Ming Lei wrote:
>> On Sat, Aug 11, 2012 at 1:36 AM, Will Deacon <will.deacon at arm.com> wrote:
>>> +       pm_runtime_put_sync(&pmu_device->dev);
>>
>> One question, each pmu is just inside one cpu core and should be
>> suspended individually, but looks the above don't support it, do it?
> 
> I'll let Jon elaborate, but I'm not sure that suspending the individual PMUs
> makes much sense if one of them is being used (other than taking the whole
> CPU offline). Given that tasks can migrate and perf-events can be across
> multiple CPUs, it makes it a lot easier to treat them as a single entity. It
> also allows us to implement mutual exclusion using the same hooks and to
> manage any common IP (e.g. CTI) at the same time, without having to keep
> track of things like the last man standing.
> 
> So, unless Jon has some ideas here, it's not something that I consider to be
> a real problem.

So from an OMAP3/4 perspective (which is the only device so far using
these runtime PM callbacks that I know of), it does not add any value to
suspend each PMU individually. For OMAP3/4, if one or more PMU is active
then we need to power up additional power domains and we need to keep
them powered until all PMUs are no longer in use.

For OMAP5 (which I have started testing) does not need other power
domains apart from the CPU power domain. So this could make more sense,
but I have not tried this yet. For now I think it is ok to keep as is
and then we can always change later to optimise for newer devices or
architectures if we think that they would benefit from this.

Cheers
Jon


From arnd at arndb.de  Thu Aug 16 09:56:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:56:38 +0000
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
References: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <201208161356.38997.arnd@arndb.de>

On Thursday 16 August 2012, Linus Walleij wrote:
> +       fpga {
> +               compatible = "arm,amba-bus", "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               rtc: rtc at 15000000 {
> +                       compatible = "arm,pl031", "arm,primecell";
> +                       reg = <0x15000000 0x1000>;
> +                       interrupt-parent = <&pic>;
> +                       interrupts = <8>;
> +                       arm,primecell-periphid = <0x00041030>;
> +               };
> +
> +               uart0: uart at 16000000 {
> +                       compatible = "arm,pl011", "arm,primecell";
> +                       reg = <0x16000000 0x1000>;
> +                       interrupt-parent = <&pic>;
> +                       interrupts = <1>;
> +                       arm,primecell-periphid = <0x00041010>;
> +               };
> +
> +               uart1: uart at 17000000 {
> +                       compatible = "arm,pl011", "arm,primecell";
> +                       reg = <0x17000000 0x1000>;
> +                       interrupt-parent = <&pic>;
> +                       interrupts = <2>;
> +                       arm,primecell-periphid = <0x00041010>;
> +               };

When all devices set the same interrupt-parent, you can just as well
move that property to the fpga node.

	Arnd


From arnd at arndb.de  Thu Aug 16 09:59:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 16 Aug 2012 13:59:21 +0000
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <1345122935-22115-1-git-send-email-stigge@antcom.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
Message-ID: <201208161359.21276.arnd@arndb.de>

On Thursday 16 August 2012, Roland Stigge wrote:
> The SLC and MLC NAND drivers now need their dma_filter callbacks via platform
> data to make them independent of single DMA engine drivers.
> 
> (This also helps fixing build errors of the SLC and MLC drivers when building
> as modules because direct access to AMBA dma filter functions isn't available
> via export.)
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Yes, this looks right.

Acked-by: Arnd Bergmann <arnd at arndb.de>

Once we have proper DT bindings for the DMA channels, we can hopefully
get rid of the auxdata again.

	Arnd


From jon-hunter at ti.com  Thu Aug 16 09:59:47 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 16 Aug 2012 08:59:47 -0500
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-5-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
Message-ID: <502CFCD3.9010603@ti.com>


On 08/10/2012 12:36 PM, Will Deacon wrote:
> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
> 
> The arm_pmu_type enumeration was initially introduced to identify
> different PMU types in the system, the usual one being that on the CPU
> (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
> the introduction of devicetree bindings for the CPU PMU, the enumeration
> is no longer required.
> 
> This patch removes the enumeration and updates the various CPU PMU
> platform devices so that they no longer pass an .id field referring
> to identify the PMU type.

Acked-by: Jon Hunter <jon-hunter at ti.com>

Cheers
Jon


From broonie at opensource.wolfsonmicro.com  Thu Aug 16 10:00:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 16 Aug 2012 15:00:56 +0100
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>
Message-ID: <20120816140056.GK15365@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 01:22:27PM +0000, AnilKumar, Chimata wrote:

> But problem here is single input supply battery/main is not sufficient.

What makes you say this?

> pmic->desc[i].supply_name = info->vin_name;
> with this assignment regulator core searches for exact supply name vcc1 or
> vcc2 etc if there are no matches then it will not register any regulators. 

Why does this mean you need multiple regulators?  A single regulator can
of course supply multiple devices.


From shubhrajyoti at ti.com  Thu Aug 16 10:03:45 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:45 +0530
Subject: [PATCHv7 14/24] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-15-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

Always return IRQ_HANDLED otherwise we could get our IRQ line disabled due
to many spurious IRQs.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Trivial changes to commitlogs]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 80ebcf5..eb6898b 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -962,7 +962,7 @@ complete:
 		}
 	} while (stat);
 
-	return count ? IRQ_HANDLED : IRQ_NONE;
+	return IRQ_HANDLED;
 }
 
 static const struct i2c_algorithm omap_i2c_algo = {
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:41 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:41 +0530
Subject: [PATCHv7 10/24] i2c: omap: ack IRQ in parts
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-11-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

According to flow diagrams on OMAP TRMs,
we should ACK the IRQ as they happen.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Ack the stat OMAP_I2C_STAT_AL in case of arbitration lost]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   28 ++++++++++++++++------------
 1 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8b80799..0adbfb1 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -850,21 +850,19 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		}
 
 complete:
-		/*
-		 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
-		 * acked after the data operation is complete.
-		 * Ref: TRM SWPU114Q Figure 18-31
-		 */
-		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
-				~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
-
-		if (stat & OMAP_I2C_STAT_NACK)
+		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
+		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
 		/*
@@ -941,12 +939,18 @@ complete:
 
 		if (stat & OMAP_I2C_STAT_ROVR) {
 			dev_err(dev->dev, "Receive overrun\n");
-			dev->cmd_err |= OMAP_I2C_STAT_ROVR;
+			err |= OMAP_I2C_STAT_ROVR;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
-			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
+			err |= OMAP_I2C_STAT_XUDF;
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 	} while (stat);
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:49 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:49 +0530
Subject: [PATCHv7 18/24] i2c: omap: remove redundant status read
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-19-git-send-email-shubhrajyoti@ti.com>

Remove the redundant read of the status register.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dfdcc2b..2dd2301 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -946,7 +946,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 				num_bytes = dev->buf_len;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
-			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
 				goto out;
 
@@ -962,7 +961,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 				num_bytes = dev->threshold;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
-			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
 				goto out;
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:50 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:50 +0530
Subject: [PATCHv7 19/24] i2c: omap: always return IRQ_HANDLED
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-20-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

even if our clocks are disabled, we still
handled the IRQ, so we should return IRQ_HANDLED.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2dd2301..f5eafb7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -862,7 +862,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	int err = 0, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
-		return IRQ_NONE;
+		return IRQ_HANDLED;
 
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:43 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:43 +0530
Subject: [PATCHv7 12/24] i2c: omap: bus: add a receiver flag
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-13-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that way we can ignore TX IRQs while in receiver
mode and ignore RX IRQs while in transmitter mode.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Remove unnecessary braces]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e9907b5..fa54d41 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -199,6 +199,7 @@ struct omap_i2c_dev {
 						 */
 	u8			rev;
 	unsigned		b_hw:1;		/* bad h/w fixes */
+	unsigned		receiver:1;	/* true when we're in receiver mode */
 	u16			iestate;	/* Saved interrupt register */
 	u16			pscstate;
 	u16			scllstate;
@@ -492,6 +493,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 
 	INIT_COMPLETION(dev->cmd_complete);
 	dev->cmd_err = 0;
+	dev->receiver = !!(msg->flags & I2C_M_RD);
 
 	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 
@@ -837,6 +839,12 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 		stat &= bits;
 
+		/* If we're in receiver mode, ignore XDR/XRDY */
+		if (dev->receiver)
+			stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
+		else
+			stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
+
 		if (!stat) {
 			/* my work here is done */
 			return IRQ_HANDLED;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:31 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:31 +0530
Subject: [PATCHv7 00/24] I2C big cleanup
Message-ID: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>

Changes since v1:
       - removed tabification on patch 6/17
       - removed dev_err() which was introduced on patch 09/17
Changes since v2:
        - do not set full fifo depth in the RDR interrupt.
        - some changelog updates.
        - rebase to the Wolfram's tree.
Changes since v3:
        - Remove a redundant read of status register
        - Read the dev->buf_len variable instead of the register
        as the information of the remaining bytes is there.
Changes since v4:
        - Ack the arbitration lost.
        - Rebase to the i2c-embedded/for-next branch.
Changes since v5:
        - Rebase to latest mainline
        - Added some more cleanup patches so as have a consolidated series.
Changes since v6:
        - Fix comments on setting the pdev to NULL.
        - Trivial changelog update

Tested on omap4sdp and 3430sdp.

The following changes since commit 3bf671af14d591ede9251acb0085e8017f3705e7:

  Merge branch 'fixes-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds (2012-08-13 09:59:04 +0300)

are available in the git repository at:

  git://gitorious.org/linus-tree/linus-tree.git for_3.6/i2c/big_cleanup



Felipe Balbi (22):
  i2c: omap: switch to devm_* API
  i2c: omap: simplify num_bytes handling
  i2c: omap: decrease indentation level on data handling
  i2c: omap: add blank lines
  i2c: omap: simplify omap_i2c_ack_stat()
  i2c: omap: split out [XR]DR and [XR]RDY
  i2c: omap: improve i462 errata handling
  i2c: omap: re-factor receive/transmit data loop
  i2c: omap: switch over to do {} while loop
  i2c: omap: ack IRQ in parts
  i2c: omap: switch to platform_get_irq()
  i2c: omap: bus: add a receiver flag
  i2c: omap: simplify errata check
  i2c: omap: always return IRQ_HANDLED
  i2c: omap: simplify IRQ exit path
  i2c: omap: resize fifos before each message
  i2c: omap: get rid of the "complete" label
  i2c: omap: always return IRQ_HANDLED
  i2c: omap: switch to threaded IRQ support
  i2c: omap: remove unnecessary pm_runtime_suspended check
  i2c: omap: switch over to autosuspend API
  i2c: omap: sanitize exit path

Shubhrajyoti D (2):
  i2c: omap: remove redundant status read
  i2c: omap: Prevent NULL pointer dereference in remove

 drivers/i2c/busses/i2c-omap.c |  446 +++++++++++++++++++++++++----------------
 1 files changed, 271 insertions(+), 175 deletions(-)

-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:37 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:37 +0530
Subject: [PATCHv7 06/24] i2c: omap: split out [XR]DR and [XR]RDY
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-7-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

While they do pretty much the same thing, there
are a few peculiarities. Specially WRT erratas,
it's best to split those out and re-factor the
read/write loop to another function which both
cases call.

This last part will be done on another patch.

While at that, also avoid an unncessary register
read since dev->fifo_len will always contain the
correct amount of data to be transferred.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |  126 ++++++++++++++++++++++++++++++-----------
 1 files changed, 92 insertions(+), 34 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8009095..139602f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -801,36 +801,62 @@ complete:
 			return IRQ_HANDLED;
 		}
 
-		if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
+		if (stat & OMAP_I2C_STAT_RDR) {
 			u8 num_bytes = 1;
 
+			if (dev->fifo_size)
+				num_bytes = dev->buf_len;
+
+			while (num_bytes--) {
+				if (!dev->buf_len) {
+					dev_err(dev->dev,
+							"RDR IRQ while no data"
+							" requested\n");
+					break;
+				}
+
+				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+				*dev->buf++ = w;
+				dev->buf_len--;
+
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						*dev->buf++ = w >> 8;
+						dev->buf_len--;
+					}
+				}
+			}
+
 			if (dev->errata & I2C_OMAP_ERRATA_I207)
 				i2c_omap_errata_i207(dev, stat);
 
-			if (dev->fifo_size) {
-				if (stat & OMAP_I2C_STAT_RRDY)
-					num_bytes = dev->fifo_size;
-				else    /* read RXSTAT on RDR interrupt */
-					num_bytes = (omap_i2c_read_reg(dev,
-							OMAP_I2C_BUFSTAT_REG)
-							>> 8) & 0x3F;
-			}
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
+			continue;
+		}
+
+		if (stat & OMAP_I2C_STAT_RRDY) {
+			u8 num_bytes = 1;
+
+			if (dev->fifo_size)
+				num_bytes = dev->fifo_size;
+
 			while (num_bytes--) {
 				if (!dev->buf_len) {
-					if (stat & OMAP_I2C_STAT_RRDY)
-						dev_err(dev->dev,
+					dev_err(dev->dev,
 							"RRDY IRQ while no data"
-								" requested\n");
-					if (stat & OMAP_I2C_STAT_RDR)
-						dev_err(dev->dev,
-							"RDR IRQ while no data"
-								" requested\n");
+							" requested\n");
 					break;
 				}
 
 				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 				*dev->buf++ = w;
 				dev->buf_len--;
+
 				/*
 				 * Data reg in 2430, omap3 and
 				 * omap4 is 8 bit wide
@@ -843,36 +869,68 @@ complete:
 					}
 				}
 			}
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
-						OMAP_I2C_STAT_RDR));
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 			continue;
 		}
 
-		if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
+		if (stat & OMAP_I2C_STAT_XDR) {
 			u8 num_bytes = 1;
-			if (dev->fifo_size) {
-				if (stat & OMAP_I2C_STAT_XRDY)
-					num_bytes = dev->fifo_size;
-				else    /* read TXSTAT on XDR interrupt */
-					num_bytes = omap_i2c_read_reg(dev,
-							OMAP_I2C_BUFSTAT_REG)
-							& 0x3F;
+
+			if (dev->fifo_size)
+				num_bytes = dev->buf_len;
+
+			while (num_bytes--) {
+				if (!dev->buf_len) {
+					dev_err(dev->dev,
+							"XDR IRQ while no "
+							"data to send\n");
+					break;
+				}
+
+				w = *dev->buf++;
+				dev->buf_len--;
+
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						w |= *dev->buf++ << 8;
+						dev->buf_len--;
+					}
+				}
+
+				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
+				    errata_omap3_i462(dev, &stat, &err))
+					goto complete;
+
+				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
+			continue;
+		}
+
+		if (stat & OMAP_I2C_STAT_XRDY) {
+			u8 num_bytes = 1;
+
+			if (dev->fifo_size)
+				num_bytes = dev->fifo_size;
+
 			while (num_bytes--) {
 				if (!dev->buf_len) {
-					if (stat & OMAP_I2C_STAT_XRDY)
-						dev_err(dev->dev,
+					dev_err(dev->dev,
 							"XRDY IRQ while no "
 							"data to send\n");
-					if (stat & OMAP_I2C_STAT_XDR)
-						dev_err(dev->dev,
-							"XDR IRQ while no "
-							"data to send\n");
 					break;
 				}
 
 				w = *dev->buf++;
 				dev->buf_len--;
+
 				/*
 				 * Data reg in 2430, omap3 and
 				 * omap4 is 8 bit wide
@@ -891,8 +949,8 @@ complete:
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
-						OMAP_I2C_STAT_XDR));
+
+			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
 		}
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:46 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:46 +0530
Subject: [PATCHv7 15/24] i2c: omap: simplify IRQ exit path
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-16-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

instead of having multiple return points, use
a goto statement to make that clearer.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   20 ++++++++------------
 1 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index eb6898b..b0b1705 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -853,24 +853,21 @@ omap_i2c_isr(int this_irq, void *dev_id)
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 complete:
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		/*
@@ -883,8 +880,7 @@ complete:
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 						OMAP_I2C_STAT_ARDY));
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_RDR) {
@@ -949,19 +945,19 @@ complete:
 			dev_err(dev->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
-			omap_i2c_complete_cmd(dev, err);
-			return IRQ_HANDLED;
+			goto out;
 		}
 	} while (stat);
 
+out:
+	omap_i2c_complete_cmd(dev, err);
 	return IRQ_HANDLED;
 }
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:32 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:32 +0530
Subject: [PATCHv7 01/24] i2c: omap: switch to devm_* API
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-2-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that helps deleting some boiler plate code
and lets driver-core manage our resources
for us.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   41 ++++++++++++-----------------------------
 1 files changed, 12 insertions(+), 29 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 6849635..6449383 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -943,7 +943,7 @@ omap_i2c_probe(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev;
 	struct i2c_adapter	*adap;
-	struct resource		*mem, *irq, *ioarea;
+	struct resource		*mem, *irq;
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
@@ -962,17 +962,16 @@ omap_i2c_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	ioarea = request_mem_region(mem->start, resource_size(mem),
-			pdev->name);
-	if (!ioarea) {
-		dev_err(&pdev->dev, "I2C region already claimed\n");
-		return -EBUSY;
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&pdev->dev, "Menory allocation failed\n");
+		return -ENOMEM;
 	}
 
-	dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
-	if (!dev) {
-		r = -ENOMEM;
-		goto err_release_region;
+	dev->base = devm_request_and_ioremap(&pdev->dev, mem);
+	if (!dev->base) {
+		dev_err(&pdev->dev, "I2C region already claimed\n");
+		return -ENOMEM;
 	}
 
 	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
@@ -995,11 +994,6 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	dev->dev = &pdev->dev;
 	dev->irq = irq->start;
-	dev->base = ioremap(mem->start, resource_size(mem));
-	if (!dev->base) {
-		r = -ENOMEM;
-		goto err_free_mem;
-	}
 
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
@@ -1057,7 +1051,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
 								   omap_i2c_isr;
-	r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev);
+	r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
+			     pdev->name, dev);
 
 	if (r) {
 		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
@@ -1081,7 +1076,7 @@ omap_i2c_probe(struct platform_device *pdev)
 	r = i2c_add_numbered_adapter(adap);
 	if (r) {
 		dev_err(dev->dev, "failure adding adapter\n");
-		goto err_free_irq;
+		goto err_unuse_clocks;
 	}
 
 	of_i2c_register_devices(adap);
@@ -1090,18 +1085,12 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	return 0;
 
-err_free_irq:
-	free_irq(dev->irq, dev);
 err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(dev->dev);
-	iounmap(dev->base);
 	pm_runtime_disable(&pdev->dev);
 err_free_mem:
 	platform_set_drvdata(pdev, NULL);
-	kfree(dev);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
 
 	return r;
 }
@@ -1109,12 +1098,10 @@ err_release_region:
 static int __devexit omap_i2c_remove(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
-	struct resource		*mem;
 	int ret;
 
 	platform_set_drvdata(pdev, NULL);
 
-	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (IS_ERR_VALUE(ret))
@@ -1123,10 +1110,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
-	iounmap(dev->base);
-	kfree(dev);
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
 	return 0;
 }
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:42 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:42 +0530
Subject: [PATCHv7 11/24] i2c: omap: switch to platform_get_irq()
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-12-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

that's a nice helper from drivers core which
will give us the exact IRQ number, instead
of a pointer to an IRQ resource.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0adbfb1..e9907b5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -993,11 +993,12 @@ omap_i2c_probe(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev;
 	struct i2c_adapter	*adap;
-	struct resource		*mem, *irq;
+	struct resource		*mem;
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
 	irq_handler_t isr;
+	int irq;
 	int r;
 
 	/* NOTE: driver uses the static register mapping */
@@ -1006,10 +1007,11 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "no mem resource?\n");
 		return -ENODEV;
 	}
-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!irq) {
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
 		dev_err(&pdev->dev, "no irq resource?\n");
-		return -ENODEV;
+		return irq;
 	}
 
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
@@ -1043,7 +1045,7 @@ omap_i2c_probe(struct platform_device *pdev)
 	}
 
 	dev->dev = &pdev->dev;
-	dev->irq = irq->start;
+	dev->irq = irq;
 
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:33 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:33 +0530
Subject: [PATCHv7 02/24] i2c: omap: simplify num_bytes handling
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-3-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

trivial patch, no functional changes

If the fifo is disabled or fifo_size is 0 the num_bytes
is set to 1. Else it is set to fifo_size or in case of a
draining interrupt the remaining bytes in the buff stat.
So the zero check is redundant and can be safely optimised.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 6449383..9b003a3 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -812,8 +812,7 @@ complete:
 							OMAP_I2C_BUFSTAT_REG)
 							>> 8) & 0x3F;
 			}
-			while (num_bytes) {
-				num_bytes--;
+			while (num_bytes--) {
 				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 				if (dev->buf_len) {
 					*dev->buf++ = w;
@@ -855,8 +854,7 @@ complete:
 							OMAP_I2C_BUFSTAT_REG)
 							& 0x3F;
 			}
-			while (num_bytes) {
-				num_bytes--;
+			while (num_bytes--) {
 				w = 0;
 				if (dev->buf_len) {
 					w = *dev->buf++;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:38 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:38 +0530
Subject: [PATCHv7 07/24] i2c: omap: improve i462 errata handling
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-8-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

Make it not depend on ISR's local variables
in order to make it easier to re-factor the
transmit data loop.
Also since we are waiting for XUDF(Transmitter underflow) just before
writing data lets not flag the underflow.
This is anyways going to go once we write
the data.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   43 ++++++++++++++++++++++++++++------------
 1 files changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 139602f..0067875 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -725,27 +725,30 @@ omap_i2c_omap1_isr(int this_irq, void *dev_id)
  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
  * them from the memory to the I2C interface.
  */
-static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err)
+static int errata_omap3_i462(struct omap_i2c_dev *dev)
 {
 	unsigned long timeout = 10000;
+	u16 stat;
 
-	while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
-		if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
+	do {
+		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		if (stat & OMAP_I2C_STAT_XUDF)
+			break;
+
+		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
-			return -ETIMEDOUT;
+			return -EIO;
 		}
 
 		cpu_relax();
-		*stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-	}
+	} while (--timeout);
 
 	if (!timeout) {
 		dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 		return 0;
 	}
 
-	*err |= OMAP_I2C_STAT_XUDF;
 	return 0;
 }
 
@@ -903,9 +906,16 @@ complete:
 					}
 				}
 
-				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
-				    errata_omap3_i462(dev, &stat, &err))
-					goto complete;
+				if (dev->errata & I2C_OMAP_ERRATA_I462) {
+					int ret;
+
+					ret = errata_omap3_i462(dev);
+					stat = omap_i2c_read_reg(dev,
+							OMAP_I2C_STAT_REG);
+
+					if (ret < 0)
+						goto complete;
+				}
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
@@ -943,9 +953,16 @@ complete:
 					}
 				}
 
-				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
-				    errata_omap3_i462(dev, &stat, &err))
-					goto complete;
+				if (dev->errata & I2C_OMAP_ERRATA_I462) {
+					int ret;
+
+					ret = errata_omap3_i462(dev);
+					stat = omap_i2c_read_reg(dev,
+							OMAP_I2C_STAT_REG);
+
+					if (ret < 0)
+						goto complete;
+				}
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:54 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:54 +0530
Subject: [PATCHv7 23/24] i2c: omap: sanitize exit path
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-24-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

move the goto out label one line down, so that
it can be used when stat is read as zero. All
other exits, can be done with a break statement.

While at that, also break out as soon as we
complete draining IRQ, since at that time
we know we transferred everything there was
to be transferred.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index d81189a..3df6f92 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -901,27 +901,26 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
-			spin_unlock_irqrestore(&dev->lock, flags);
-			return IRQ_HANDLED;
+			goto out;
 		}
 
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_AL) {
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
-			goto out;
+			break;
 		}
 
 		/*
@@ -934,7 +933,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 						OMAP_I2C_STAT_XRDY |
 						OMAP_I2C_STAT_XDR |
 						OMAP_I2C_STAT_ARDY));
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RDR) {
@@ -949,7 +948,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 				i2c_omap_errata_i207(dev, stat);
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_RRDY) {
@@ -972,10 +971,10 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
-			continue;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XRDY) {
@@ -987,7 +986,7 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			if (ret < 0)
-				goto out;
+				break;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
@@ -997,19 +996,20 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 			dev_err(dev->dev, "Receive overrun\n");
 			err |= OMAP_I2C_STAT_ROVR;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
-			goto out;
+			break;
 		}
 
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			err |= OMAP_I2C_STAT_XUDF;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
-			goto out;
+			break;
 		}
 	} while (stat);
 
-out:
 	omap_i2c_complete_cmd(dev, err);
+
+out:
 	spin_unlock_irqrestore(&dev->lock, flags);
 
 	return IRQ_HANDLED;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:34 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:34 +0530
Subject: [PATCHv7 03/24] i2c: omap: decrease indentation level on data handling
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-4-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

The patch intends to decrease the indentation level on the
data handling
by using the fact that else of if (dev->buf_len) is same as
if (!dev->buf_len)

if (dev->buf_len) {
	aaa;
} else {
	bbb;
	break;
}

to

if (!dev->buf_len) {
        bbb;
        break;
}
aaa;

Hence no functional changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   63 ++++++++++++++++++++---------------------
 1 files changed, 31 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 9b003a3..81ef0a7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -813,22 +813,7 @@ complete:
 							>> 8) & 0x3F;
 			}
 			while (num_bytes--) {
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				if (dev->buf_len) {
-					*dev->buf++ = w;
-					dev->buf_len--;
-					/*
-					 * Data reg in 2430, omap3 and
-					 * omap4 is 8 bit wide
-					 */
-					if (dev->flags &
-						 OMAP_I2C_FLAG_16BIT_DATA_REG) {
-						if (dev->buf_len) {
-							*dev->buf++ = w >> 8;
-							dev->buf_len--;
-						}
-					}
-				} else {
+				if (!dev->buf_len) {
 					if (stat & OMAP_I2C_STAT_RRDY)
 						dev_err(dev->dev,
 							"RRDY IRQ while no data"
@@ -839,6 +824,21 @@ complete:
 								" requested\n");
 					break;
 				}
+
+				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+				*dev->buf++ = w;
+				dev->buf_len--;
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						*dev->buf++ = w >> 8;
+						dev->buf_len--;
+					}
+				}
 			}
 			omap_i2c_ack_stat(dev,
 				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
@@ -855,22 +855,7 @@ complete:
 							& 0x3F;
 			}
 			while (num_bytes--) {
-				w = 0;
-				if (dev->buf_len) {
-					w = *dev->buf++;
-					dev->buf_len--;
-					/*
-					 * Data reg in 2430, omap3 and
-					 * omap4 is 8 bit wide
-					 */
-					if (dev->flags &
-						 OMAP_I2C_FLAG_16BIT_DATA_REG) {
-						if (dev->buf_len) {
-							w |= *dev->buf++ << 8;
-							dev->buf_len--;
-						}
-					}
-				} else {
+				if (!dev->buf_len) {
 					if (stat & OMAP_I2C_STAT_XRDY)
 						dev_err(dev->dev,
 							"XRDY IRQ while no "
@@ -882,6 +867,20 @@ complete:
 					break;
 				}
 
+				w = *dev->buf++;
+				dev->buf_len--;
+				/*
+				 * Data reg in 2430, omap3 and
+				 * omap4 is 8 bit wide
+				 */
+				if (dev->flags &
+						OMAP_I2C_FLAG_16BIT_DATA_REG) {
+					if (dev->buf_len) {
+						w |= *dev->buf++ << 8;
+						dev->buf_len--;
+					}
+				}
+
 				if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
 				    errata_omap3_i462(dev, &stat, &err))
 					goto complete;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:39 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:39 +0530
Subject: [PATCHv7 08/24] i2c: omap: re-factor receive/transmit data loop
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-9-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

re-factor the common parts to a separate function,
so that code is easier to read and understand.

No functional changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |  204 ++++++++++++++++------------------------
 1 files changed, 82 insertions(+), 122 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0067875..d4b6f7d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -752,12 +752,81 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev)
 	return 0;
 }
 
+static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
+		bool is_rdr)
+{
+	u16		w;
+
+	while (num_bytes--) {
+		if (!dev->buf_len) {
+			dev_err(dev->dev, "%s without data",
+					is_rdr ? "RDR" : "RRDY");
+			break;
+		}
+
+		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
+		*dev->buf++ = w;
+		dev->buf_len--;
+
+		/*
+		 * Data reg in 2430, omap3 and
+		 * omap4 is 8 bit wide
+		 */
+		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+			if (dev->buf_len) {
+				*dev->buf++ = w >> 8;
+				dev->buf_len--;
+			}
+		}
+	}
+}
+
+static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
+		bool is_xdr)
+{
+	u16		w;
+
+	while (num_bytes--) {
+		if (!dev->buf_len) {
+			dev_err(dev->dev, "%s without data",
+					is_xdr ? "XDR" : "XRDY");
+			break;
+		}
+
+		w = *dev->buf++;
+		dev->buf_len--;
+
+		/*
+		 * Data reg in 2430, omap3 and
+		 * omap4 is 8 bit wide
+		 */
+		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
+			if (dev->buf_len) {
+				w |= *dev->buf++ << 8;
+				dev->buf_len--;
+			}
+		}
+
+		if (dev->errata & I2C_OMAP_ERRATA_I462) {
+			int ret;
+
+			ret = errata_omap3_i462(dev);
+			if (ret < 0)
+				return ret;
+		}
+
+		omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+	}
+
+	return 0;
+}
+
 static irqreturn_t
 omap_i2c_isr(int this_irq, void *dev_id)
 {
 	struct omap_i2c_dev *dev = dev_id;
 	u16 bits;
-	u16 stat, w;
+	u16 stat;
 	int err, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
@@ -810,30 +879,7 @@ complete:
 			if (dev->fifo_size)
 				num_bytes = dev->buf_len;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"RDR IRQ while no data"
-							" requested\n");
-					break;
-				}
-
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				*dev->buf++ = w;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						*dev->buf++ = w >> 8;
-						dev->buf_len--;
-					}
-				}
-			}
+			omap_i2c_receive_data(dev, num_bytes, true);
 
 			if (dev->errata & I2C_OMAP_ERRATA_I207)
 				i2c_omap_errata_i207(dev, stat);
@@ -848,77 +894,22 @@ complete:
 			if (dev->fifo_size)
 				num_bytes = dev->fifo_size;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"RRDY IRQ while no data"
-							" requested\n");
-					break;
-				}
-
-				w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-				*dev->buf++ = w;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						*dev->buf++ = w >> 8;
-						dev->buf_len--;
-					}
-				}
-			}
-
+			omap_i2c_receive_data(dev, num_bytes, false);
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 			continue;
 		}
 
 		if (stat & OMAP_I2C_STAT_XDR) {
 			u8 num_bytes = 1;
+			int ret;
 
 			if (dev->fifo_size)
 				num_bytes = dev->buf_len;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"XDR IRQ while no "
-							"data to send\n");
-					break;
-				}
-
-				w = *dev->buf++;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						w |= *dev->buf++ << 8;
-						dev->buf_len--;
-					}
-				}
-
-				if (dev->errata & I2C_OMAP_ERRATA_I462) {
-					int ret;
-
-					ret = errata_omap3_i462(dev);
-					stat = omap_i2c_read_reg(dev,
-							OMAP_I2C_STAT_REG);
-
-					if (ret < 0)
-						goto complete;
-				}
-
-				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
-			}
+			ret = omap_i2c_transmit_data(dev, num_bytes, true);
+			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+			if (ret < 0)
+				goto complete;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
 			continue;
@@ -926,46 +917,15 @@ complete:
 
 		if (stat & OMAP_I2C_STAT_XRDY) {
 			u8 num_bytes = 1;
+			int ret;
 
 			if (dev->fifo_size)
 				num_bytes = dev->fifo_size;
 
-			while (num_bytes--) {
-				if (!dev->buf_len) {
-					dev_err(dev->dev,
-							"XRDY IRQ while no "
-							"data to send\n");
-					break;
-				}
-
-				w = *dev->buf++;
-				dev->buf_len--;
-
-				/*
-				 * Data reg in 2430, omap3 and
-				 * omap4 is 8 bit wide
-				 */
-				if (dev->flags &
-						OMAP_I2C_FLAG_16BIT_DATA_REG) {
-					if (dev->buf_len) {
-						w |= *dev->buf++ << 8;
-						dev->buf_len--;
-					}
-				}
-
-				if (dev->errata & I2C_OMAP_ERRATA_I462) {
-					int ret;
-
-					ret = errata_omap3_i462(dev);
-					stat = omap_i2c_read_reg(dev,
-							OMAP_I2C_STAT_REG);
-
-					if (ret < 0)
-						goto complete;
-				}
-
-				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
-			}
+			ret = omap_i2c_transmit_data(dev, num_bytes, false);
+			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+			if (ret < 0)
+				goto complete;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:36 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:36 +0530
Subject: [PATCHv7 05/24] i2c: omap: simplify omap_i2c_ack_stat()
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-6-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

stat & BIT(1) is the same as BIT(1), so let's
simplify things a bit by removing "stat &" from
all omap_i2c_ack_stat() calls.

Code snippet (extremely simplified):

if (stat & NACK) {
        ...
        omap_i2c_ack_stat(dev, stat & NACK);
}

if (stat & RDR) {
        ...
        omap_i2c_ack_stat(dev, stat & RDR);
}

and so on. The tricky place is only WRT errata handling, for example:

if (*stat & (NACK | AL)) {
        omap_i2c_ack_stat(dev, *stat & (XRDY | XDR));
        ...
}

but in this case, the errata says we must clear XRDY and XDR if that
errata triggers, so if they just got enabled or not, it doesn't matter.

Another tricky place is RDR | RRDY (likewise for XDR | XRDY):

if (stat & (RDR | RRDY)) {
        ...
        omap_i2c_ack_stat(dev, stat & (RDR | RRDY));
}

again here there will be no issues because those IRQs never fire
simultaneously and one will only after after we have handled the
previous, that's because the same FIFO is used anyway and we won't shift
data into FIFO until we tell the IP "hey, I'm done with the FIFO, you
can shift more data"

Signed-off-by: Felipe Balbi <balbi at ti.com>
Reviewed-by : Santosh Shilimkar <santosh.shilimkar at ti.com>
[Added the explaination from the discurssion to the commit logs]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   19 ++++++++++---------
 1 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dbc5a3c..8009095 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -731,7 +731,7 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err)
 
 	while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 		if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
 			return -ETIMEDOUT;
 		}
@@ -792,10 +792,11 @@ complete:
 		 */
 		if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 					OMAP_I2C_STAT_AL)) {
-			omap_i2c_ack_stat(dev, stat &
-				(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
-				OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
-				OMAP_I2C_STAT_ARDY));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
+						OMAP_I2C_STAT_RDR |
+						OMAP_I2C_STAT_XRDY |
+						OMAP_I2C_STAT_XDR |
+						OMAP_I2C_STAT_ARDY));
 			omap_i2c_complete_cmd(dev, err);
 			return IRQ_HANDLED;
 		}
@@ -842,8 +843,8 @@ complete:
 					}
 				}
 			}
-			omap_i2c_ack_stat(dev,
-				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
+						OMAP_I2C_STAT_RDR));
 			continue;
 		}
 
@@ -890,8 +891,8 @@ complete:
 
 				omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 			}
-			omap_i2c_ack_stat(dev,
-				stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
+			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
+						OMAP_I2C_STAT_XDR));
 			continue;
 		}
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:53 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:53 +0530
Subject: [PATCHv7 22/24] i2c: omap: switch over to autosuspend API
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-23-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

this helps us reduce unnecessary pm transitions
in case we have another i2c message starting soon.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2d5db56..d81189a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -55,6 +55,9 @@
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
 
+/* timeout for pm runtime autosuspend */
+#define OMAP_I2C_PM_TIMEOUT		1000	/* ms */
+
 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
 enum {
 	OMAP_I2C_REV_REG = 0,
@@ -645,7 +648,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	omap_i2c_wait_for_bb(dev);
 out:
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 	return r;
 }
 
@@ -1113,6 +1117,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
+	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
+	pm_runtime_use_autosuspend(dev->dev);
+
 	r = pm_runtime_get_sync(dev->dev);
 	if (IS_ERR_VALUE(r))
 		goto err_free_mem;
@@ -1190,7 +1197,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
-	pm_runtime_put(dev->dev);
+	pm_runtime_mark_last_busy(dev->dev);
+	pm_runtime_put_autosuspend(dev->dev);
 
 	return 0;
 
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:48 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:48 +0530
Subject: [PATCHv7 17/24] i2c: omap: get rid of the "complete" label
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-18-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

we can ack stat and complete the command from
the errata handling itself.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dfbf667..dfdcc2b 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -775,6 +775,17 @@ static int errata_omap3_i462(struct omap_i2c_dev *dev)
 		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 							OMAP_I2C_STAT_XDR));
+			if (stat & OMAP_I2C_STAT_NACK) {
+				dev->cmd_err |= OMAP_I2C_STAT_NACK;
+				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			}
+
+			if (stat & OMAP_I2C_STAT_AL) {
+				dev_err(dev->dev, "Arbitration lost\n");
+				dev->cmd_err |= OMAP_I2C_STAT_AL;
+				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
+			}
+
 			return -EIO;
 		}
 
@@ -875,7 +886,6 @@ omap_i2c_isr(int this_irq, void *dev_id)
 			goto out;
 		}
 
-complete:
 		if (stat & OMAP_I2C_STAT_NACK) {
 			err |= OMAP_I2C_STAT_NACK;
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
@@ -938,7 +948,7 @@ complete:
 			ret = omap_i2c_transmit_data(dev, num_bytes, true);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
-				goto complete;
+				goto out;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
 			continue;
@@ -954,7 +964,7 @@ complete:
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 			if (ret < 0)
-				goto complete;
+				goto out;
 
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 			continue;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:51 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:51 +0530
Subject: [PATCHv7 20/24] i2c: omap: switch to threaded IRQ support
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-21-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

for OMAP2, we can easily switch over to threaded
IRQs on the I2C driver. This will allow us to
spend less time in hardirq context.

Signed-off-by: Felipe Balbi <balbi at ti.com>
[Trivial formating changes]
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   43 +++++++++++++++++++++++++++++++++++-----
 1 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f5eafb7..39e5d36 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -176,6 +176,7 @@ enum {
 #define I2C_OMAP_ERRATA_I462		(1 << 1)
 
 struct omap_i2c_dev {
+	spinlock_t		lock;		/* IRQ synchronization */
 	struct device		*dev;
 	void __iomem		*base;		/* virtual */
 	int			irq;
@@ -854,9 +855,30 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 }
 
 static irqreturn_t
-omap_i2c_isr(int this_irq, void *dev_id)
+omap_i2c_isr(int irq, void *dev_id)
 {
 	struct omap_i2c_dev *dev = dev_id;
+	irqreturn_t ret = IRQ_HANDLED;
+	u16 mask;
+	u16 stat;
+
+	spin_lock(&dev->lock);
+	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+
+	if (stat & mask)
+		ret = IRQ_WAKE_THREAD;
+
+	spin_unlock(&dev->lock);
+
+	return ret;
+}
+
+static irqreturn_t
+omap_i2c_isr_thread(int this_irq, void *dev_id)
+{
+	struct omap_i2c_dev *dev = dev_id;
+	unsigned long flags;
 	u16 bits;
 	u16 stat;
 	int err = 0, count = 0;
@@ -864,6 +886,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	if (pm_runtime_suspended(dev->dev))
 		return IRQ_HANDLED;
 
+	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
@@ -877,6 +900,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 		if (!stat) {
 			/* my work here is done */
+			spin_unlock_irqrestore(&dev->lock, flags);
 			return IRQ_HANDLED;
 		}
 
@@ -985,6 +1009,8 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
 out:
 	omap_i2c_complete_cmd(dev, err);
+	spin_unlock_irqrestore(&dev->lock, flags);
+
 	return IRQ_HANDLED;
 }
 
@@ -1028,7 +1054,6 @@ omap_i2c_probe(struct platform_device *pdev)
 	struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
-	irq_handler_t isr;
 	int irq;
 	int r;
 
@@ -1078,6 +1103,8 @@ omap_i2c_probe(struct platform_device *pdev)
 	dev->dev = &pdev->dev;
 	dev->irq = irq;
 
+	spin_lock_init(&dev->lock);
+
 	platform_set_drvdata(pdev, dev);
 	init_completion(&dev->cmd_complete);
 
@@ -1130,10 +1157,14 @@ omap_i2c_probe(struct platform_device *pdev)
 	/* reset ASAP, clearing any IRQs */
 	omap_i2c_init(dev);
 
-	isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
-								   omap_i2c_isr;
-	r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
-			     pdev->name, dev);
+	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
+		r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
+				IRQF_NO_SUSPEND, pdev->name, dev);
+	else
+		r = devm_request_threaded_irq(&pdev->dev, dev->irq,
+				omap_i2c_isr, omap_i2c_isr_thread,
+				IRQF_NO_SUSPEND | IRQF_ONESHOT,
+				pdev->name, dev);
 
 	if (r) {
 		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:40 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:40 +0530
Subject: [PATCHv7 09/24] i2c: omap: switch over to do {} while loop
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-10-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

this will make sure that we execute at least once.
No functional changes otherwise.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index d4b6f7d..8b80799 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -827,20 +827,28 @@ omap_i2c_isr(int this_irq, void *dev_id)
 	struct omap_i2c_dev *dev = dev_id;
 	u16 bits;
 	u16 stat;
-	int err, count = 0;
+	int err = 0, count = 0;
 
 	if (pm_runtime_suspended(dev->dev))
 		return IRQ_NONE;
 
-	bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-	while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
+	do {
+		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
+		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+		stat &= bits;
+
+		if (!stat) {
+			/* my work here is done */
+			return IRQ_HANDLED;
+		}
+
 		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 		if (count++ == 100) {
 			dev_warn(dev->dev, "Too much work in one IRQ\n");
-			break;
+			omap_i2c_complete_cmd(dev, err);
+			return IRQ_HANDLED;
 		}
 
-		err = 0;
 complete:
 		/*
 		 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
@@ -940,7 +948,7 @@ complete:
 			dev_err(dev->dev, "Transmit underflow\n");
 			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 		}
-	}
+	} while (stat);
 
 	return count ? IRQ_HANDLED : IRQ_NONE;
 }
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:35 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:35 +0530
Subject: [PATCHv7 04/24] i2c: omap: add blank lines
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-5-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

trivial patch to aid readability. No functional
changes.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 81ef0a7..dbc5a3c 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -786,6 +786,7 @@ complete:
 			dev_err(dev->dev, "Arbitration lost\n");
 			err |= OMAP_I2C_STAT_AL;
 		}
+
 		/*
 		 * ProDB0017052: Clear ARDY bit twice
 		 */
@@ -798,6 +799,7 @@ complete:
 			omap_i2c_complete_cmd(dev, err);
 			return IRQ_HANDLED;
 		}
+
 		if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 			u8 num_bytes = 1;
 
@@ -844,6 +846,7 @@ complete:
 				stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 			continue;
 		}
+
 		if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 			u8 num_bytes = 1;
 			if (dev->fifo_size) {
@@ -891,10 +894,12 @@ complete:
 				stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 			continue;
 		}
+
 		if (stat & OMAP_I2C_STAT_ROVR) {
 			dev_err(dev->dev, "Receive overrun\n");
 			dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 		}
+
 		if (stat & OMAP_I2C_STAT_XUDF) {
 			dev_err(dev->dev, "Transmit underflow\n");
 			dev->cmd_err |= OMAP_I2C_STAT_XUDF;
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:52 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:52 +0530
Subject: [PATCHv7 21/24] i2c: omap: remove unnecessary pm_runtime_suspended
 check
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-22-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

before starting any messages we call pm_runtime_get_sync()
which will make sure that by the time we program a transfer
and our IRQ handler gets called, we're not suspended
anymore.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 39e5d36..2d5db56 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -883,9 +883,6 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
 	u16 stat;
 	int err = 0, count = 0;
 
-	if (pm_runtime_suspended(dev->dev))
-		return IRQ_HANDLED;
-
 	spin_lock_irqsave(&dev->lock, flags);
 	do {
 		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:44 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:44 +0530
Subject: [PATCHv7 13/24] i2c: omap: simplify errata check
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-14-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

omap_i2c_dev is allocated with kzalloc(),
so we need not initialize b_hw to zero.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index fa54d41..80ebcf5 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1095,9 +1095,7 @@ omap_i2c_probe(struct platform_device *pdev)
 
 		dev->fifo_size = (dev->fifo_size / 2);
 
-		if (dev->rev >= OMAP_I2C_REV_ON_3630_4430)
-			dev->b_hw = 0; /* Disable hardware fixes */
-		else
+		if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
 			dev->b_hw = 1; /* Enable hardware fixes */
 
 		/* calculate wakeup latency constraint for MPU */
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:55 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:55 +0530
Subject: [PATCHv7 24/24] i2c: omap: Prevent NULL pointer dereference in remove
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-25-git-send-email-shubhrajyoti@ti.com>

Prevent the NULL pointer access of pdev. The platform_device is anyways
deleted so remove  platform_set_drvdata(pdev, NULL);.

[  654.961761] Unable to handle kernel NULL pointer dereference at virtual address 00000070
[  654.970611] pgd = df254000
[  654.973480] [00000070] *pgd=9f1da831, *pte=00000000, *ppte=00000000
[  654.980163] Internal error: Oops: 17 [#1] SMP ARM
[  654.985076] Modules linked in:
[  654.988281] CPU: 1    Not tainted  (3.6.0-rc1-00031-ge547de1-dirty #339)
[  654.995330] PC is at omap_i2c_runtime_resume+0x8/0x148
[  655.000732] LR is at omap_i2c_runtime_resume+0x8/0x148

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 3df6f92..9aefd36 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1207,8 +1207,6 @@ err_unuse_clocks:
 	pm_runtime_put(dev->dev);
 	pm_runtime_disable(&pdev->dev);
 err_free_mem:
-	platform_set_drvdata(pdev, NULL);
-
 	return r;
 }
 
@@ -1217,8 +1215,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
 	int ret;
 
-	platform_set_drvdata(pdev, NULL);
-
 	i2c_del_adapter(&dev->adapter);
 	ret = pm_runtime_get_sync(&pdev->dev);
 	if (IS_ERR_VALUE(ret))
-- 
1.7.5.4



From shubhrajyoti at ti.com  Thu Aug 16 10:03:47 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 16 Aug 2012 19:33:47 +0530
Subject: [PATCHv7 16/24] i2c: omap: resize fifos before each message
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1345125835-15524-17-git-send-email-shubhrajyoti@ti.com>

From: Felipe Balbi <balbi at ti.com>

This patch will try to avoid the usage of
draining feature by reconfiguring the FIFO
the start condition of each message based
on the message's size.

By doing that, we will be better utilizing
the FIFO when doing big transfers.

While at that also drop the now unneeded
check for dev->buf_len as we always know
the amount of data to be transmitted.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   83 +++++++++++++++++++++++++----------------
 1 files changed, 51 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index b0b1705..dfbf667 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -193,6 +193,7 @@ struct omap_i2c_dev {
 	u8			*regs;
 	size_t			buf_len;
 	struct i2c_adapter	adapter;
+	u8			threshold;
 	u8			fifo_size;	/* use as flag and value
 						 * fifo_size==0 implies no fifo
 						 * if set, should be trsh+1
@@ -418,13 +419,6 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 
-	if (dev->fifo_size) {
-		/* Note: setup required fifo size - 1. RTRSH and XTRSH */
-		buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
-			(dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
-		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
-	}
-
 	/* Take the I2C module out of reset: */
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 
@@ -462,6 +456,45 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 	return 0;
 }
 
+static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
+{
+	u16		buf;
+
+	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
+		return;
+
+	/*
+	 * Set up notification threshold based on message size. We're doing
+	 * this to try and avoid draining feature as much as possible. Whenever
+	 * we have big messages to transfer (bigger than our total fifo size)
+	 * then we might use draining feature to transfer the remaining bytes.
+	 */
+
+	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
+
+	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
+
+	if (is_rx) {
+		/* Clear RX Threshold */
+		buf &= ~(0x3f << 8);
+		buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
+	} else {
+		/* Clear TX Threshold */
+		buf &= ~0x3f;
+		buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
+	}
+
+	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
+
+	if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
+		dev->b_hw = 1; /* Enable hardware fixes */
+
+	/* calculate wakeup latency constraint for MPU */
+	if (dev->set_mpu_wkup_lat != NULL)
+		dev->latency = (1000000 * dev->threshold) /
+			(1000 * dev->speed / 8);
+}
+
 /*
  * Low level master read/write transaction.
  */
@@ -478,6 +511,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 	if (msg->len == 0)
 		return -EINVAL;
 
+	dev->receiver = !!(msg->flags & I2C_M_RD);
+	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
+
 	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 
 	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
@@ -493,7 +529,6 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 
 	INIT_COMPLETION(dev->cmd_complete);
 	dev->cmd_err = 0;
-	dev->receiver = !!(msg->flags & I2C_M_RD);
 
 	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 
@@ -760,12 +795,6 @@ static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
 	u16		w;
 
 	while (num_bytes--) {
-		if (!dev->buf_len) {
-			dev_err(dev->dev, "%s without data",
-					is_rdr ? "RDR" : "RRDY");
-			break;
-		}
-
 		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 		*dev->buf++ = w;
 		dev->buf_len--;
@@ -775,10 +804,8 @@ static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
 		 * omap4 is 8 bit wide
 		 */
 		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			if (dev->buf_len) {
-				*dev->buf++ = w >> 8;
-				dev->buf_len--;
-			}
+			*dev->buf++ = w >> 8;
+			dev->buf_len--;
 		}
 	}
 }
@@ -789,12 +816,6 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 	u16		w;
 
 	while (num_bytes--) {
-		if (!dev->buf_len) {
-			dev_err(dev->dev, "%s without data",
-					is_xdr ? "XDR" : "XRDY");
-			break;
-		}
-
 		w = *dev->buf++;
 		dev->buf_len--;
 
@@ -803,10 +824,8 @@ static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 		 * omap4 is 8 bit wide
 		 */
 		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
-			if (dev->buf_len) {
-				w |= *dev->buf++ << 8;
-				dev->buf_len--;
-			}
+			w |= *dev->buf++ << 8;
+			dev->buf_len--;
 		}
 
 		if (dev->errata & I2C_OMAP_ERRATA_I462) {
@@ -901,8 +920,8 @@ complete:
 		if (stat & OMAP_I2C_STAT_RRDY) {
 			u8 num_bytes = 1;
 
-			if (dev->fifo_size)
-				num_bytes = dev->fifo_size;
+			if (dev->threshold)
+				num_bytes = dev->threshold;
 
 			omap_i2c_receive_data(dev, num_bytes, false);
 			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
@@ -929,8 +948,8 @@ complete:
 			u8 num_bytes = 1;
 			int ret;
 
-			if (dev->fifo_size)
-				num_bytes = dev->fifo_size;
+			if (dev->threshold)
+				num_bytes = dev->threshold;
 
 			ret = omap_i2c_transmit_data(dev, num_bytes, false);
 			stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-- 
1.7.5.4



From catalin.marinas at arm.com  Thu Aug 16 10:11:53 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 16 Aug 2012 15:11:53 +0100
Subject: [PATCH v2 26/31] arm64: Miscellaneous library functions
In-Reply-To: <201208161300.32830.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151521.14663.arnd@arndb.de>
 <20120816105709.GK31784@mudshark.cambridge.arm.com>
 <201208161300.32830.arnd@arndb.de>
Message-ID: <20120816141153.GC30876@arm.com>

On Thu, Aug 16, 2012 at 02:00:32PM +0100, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Will Deacon wrote:
> > > > +
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/spinlock.h>
> > > > +#include <linux/atomic.h>
> > > > +
> > > > +#ifdef CONFIG_SMP
> > > > +arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
> > > > +       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
> > > > +};
> > > > +#endif
> > > 
> > > What?
> > > 
> > > I suppose this is a leftover from an earlier version using the
> > > generic bitops, right?
> > 
> > We currently use the generic atomic bitops (asm-generic/bitops/atomic.h)
> > which contains:
> > 
> > #  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
> > 
> > so we have to provide a definition for the array. We have additional patches
> > containing optimised assembly implementations of the atomic bitops which we
> > will push later, once we've got some hardware to benchmark with.
> > 
> 
> Ah, I was confusing this with the asm/atomic.h stuff, for which you already
> provide an optimized version.
> 
> The generic atomic bitops are really horrible in performance and I would
> expect that there is just one obvious way to implement bitops using ldaxr/stlxr,
> so I recommend just doing that even if you have no hardware for benchmarking.

As Will said, we have the code already but I dropped it from the initial
set patches to be reviewed to keep them simpler. They will be added
later.

-- 
Catalin


From w.sang at pengutronix.de  Thu Aug 16 10:15:38 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 16 Aug 2012 16:15:38 +0200
Subject: [PATCHv7 00/24] I2C big cleanup
In-Reply-To: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
References: <1345125835-15524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <20120816141538.GA13740@pengutronix.de>

On Thu, Aug 16, 2012 at 07:33:31PM +0530, Shubhrajyoti D wrote:
> Changes since v1:
>        - removed tabification on patch 6/17
>        - removed dev_err() which was introduced on patch 09/17
> Changes since v2:
>         - do not set full fifo depth in the RDR interrupt.
>         - some changelog updates.
>         - rebase to the Wolfram's tree.
> Changes since v3:
>         - Remove a redundant read of status register
>         - Read the dev->buf_len variable instead of the register
>         as the information of the remaining bytes is there.
> Changes since v4:
>         - Ack the arbitration lost.
>         - Rebase to the i2c-embedded/for-next branch.
> Changes since v5:
>         - Rebase to latest mainline
>         - Added some more cleanup patches so as have a consolidated series.
> Changes since v6:
>         - Fix comments on setting the pdev to NULL.
>         - Trivial changelog update
> 
> Tested on omap4sdp and 3430sdp.
> 
> The following changes since commit 3bf671af14d591ede9251acb0085e8017f3705e7:
> 
>   Merge branch 'fixes-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds (2012-08-13 09:59:04 +0300)
> 
> are available in the git repository at:
> 
>   git://gitorious.org/linus-tree/linus-tree.git for_3.6/i2c/big_cleanup

A GIT tree, thanks for that!

Since the series is quite huge, I'd appreciate it if you could wait for
reviews a little bit (a few days) and collect the issues raised there
before resending. I know "release early & often", yet the traffic causes
some overhead here :)

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From jason at lakedaemon.net  Thu Aug 16 10:20:05 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 10:20:05 -0400
Subject: dreamplug spi partitions
In-Reply-To: <1344498477.11783.38.camel@dagon.hellion.org.uk>
References: <1344498477.11783.38.camel@dagon.hellion.org.uk>
Message-ID: <20120816142005.GS22226@titan.lakedaemon.net>

On Thu, Aug 09, 2012 at 08:47:57AM +0100, Ian Campbell wrote:
> Hi all,
> 
> I've been using "fw_printenv" and "fw_setenv" from the u-boot-tools
> package on my DreamPlug which work fine with this /etc/fw_env.config:
>         # Configuration file for fw_(printenv/saveenv) utility.
>         # Up to two entries are valid, in this case the redundant
>         # environment sector is assumed present.
>         # MTD device name       Device offset   Env. size       Flash sector size
>         /dev/mtd1               0x00000000      0x00001000      0x00001000
>         
> This corresponds roughly, but not exactly, with:
>         # cat /proc/mtd 
>         dev:    size   erasesize  name
>         mtd0: 00080000 00001000 "u-boot"
>         mtd1: 00010000 00001000 "u-boot env"
>         mtd2: 00010000 00001000 "dtb"
> 
> But notice how "Env. size" and mtd1's size don't match -- if I use
> 0x10000 in fw_env.cfg then the tools don't work (checksums don't match).

I've always seen the u-boot environment set to 4k.  The kernel
partitions came out of my head.  When I added support for the dreamplug
to u-boot, I found out there was a bug in the factory supplied u-boot
which only allowed it to see the first 1MB of the 2MB flash.  Also, the
factory supplied kernel didn't even have support for the flash.

So, I fixed u-boot, and figured the extra 1MB was too small for a
kernel, wasn't used by anybody else, and imho, the factory location of
the environment didn't leave much room for new u-boots.

I decided to move the environment and make a place for the dtb.  As I
didn't want to constrain either one, I split the extra space between the
two.

Was that the best decision?  Well, no one yelled at me and I was new to
the whole process, so that's how it went down.

As it is right now, if you configure your own u-boot to have, say
0x10000 bytes for the environment, you don't need to change your kernel
to support it.  Just set the size and write it.

I'm open to suggestions and patches...

hth,

Jason.


From stigge at antcom.de  Thu Aug 16 10:26:53 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 16 Aug 2012 16:26:53 +0200
Subject: [PATCH 1/2] mtd: lpc32xx_slc: Adjust to pl08x DMA interface
 changes
In-Reply-To: <1345027069.3393.124.camel@sauron.fi.intel.com>
References: <1342095778-13403-1-git-send-email-stigge@antcom.de>
 <1342095778-13403-2-git-send-email-stigge@antcom.de>
 <1345027069.3393.124.camel@sauron.fi.intel.com>
Message-ID: <502D032D.1000301@antcom.de>

Hi,

On 08/15/2012 12:37 PM, Artem Bityutskiy wrote:
> On Thu, 2012-07-12 at 14:22 +0200, Roland Stigge wrote:
>> This patch adjusts the LPC32xx SLC NAND driver to the new pl08x
>> DMA interface, fixing the compile error resulting from changed
>> pl08x structures.
>> 
>> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> This patch breaks compilation:
> 
> ERROR: "pl08x_filter_id" [drivers/mtd/nand/lpc32xx_slc.ko]
> undefined!
> 
> Please, send a fix. The defconfig I used is attached.

Please see my just posted patches:

mtd: lpc32xx_slc: Make driver independent of AMBA DMA engine driver
mtd: lpc32xx_mlc: Make driver independent of AMBA DMA engine driver

This also fixes the above problem by getting rid of the reference to
pl08x_filter_id.

Thanks,

Roland


From wade_farnsworth at mentor.com  Thu Aug 16 10:33:45 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Thu, 16 Aug 2012 07:33:45 -0700
Subject: [PATCH v2] ARM: support syscall tracing
In-Reply-To: <20120816095431.GE31784@mudshark.cambridge.arm.com>
References: <502BBCCC.1020006@mentor.com>
 <20120815162157.GJ29448@mudshark.cambridge.arm.com>
 <502BD544.70903@mentor.com>
 <20120815172731.GL29448@mudshark.cambridge.arm.com>
 <502BFA08.6010708@mentor.com> <502C04CF.2080409@mentor.com>
 <20120816095431.GE31784@mudshark.cambridge.arm.com>
Message-ID: <502D04C9.2050501@mentor.com>

Will Deacon wrote:
> On Wed, Aug 15, 2012 at 09:21:35PM +0100, Wade Farnsworth wrote:
>> Wade Farnsworth wrote:
>>> Will Deacon wrote:
>>>> On Wed, Aug 15, 2012 at 05:58:44PM +0100, Wade Farnsworth wrote:
>>>>> We need to set current_thread_info()->syscall, since it's used in the
>>>>> call to syscall_get_nr() in perf_syscall_{enter,exit}.
>>>>
>>>> Damn. I think that also means we have a bug, given that the SYSCALL_TRACE
>>>> code can set this to -1, which gets used as an index into a bitmap by the
>>>> looks of it. Considering that we have to pass the syscall number to
>>>> trace_sys_enter anyway, it also seems broken.
>>>>
>>>
>>> I agree. Looking at the other architectures, it seems the analogous
>>> function to ptrace_syscall_trace can return -1 under certain
>>> circumstances, but the original syscall value should be passed onto
>>> trace_sys_enter and returned from syscall_get_nr(). So, I'm thinking
>>> that we should modify our behavior accordingly. What this means for us
>>> is that we never store -1 in the thread_info syscall field, and then
>>> pass that into trace_sys_enter instead of the ptrace_syscall_trace
>>> return value. Do you see any problems with this approach?
>>>
>>
>> Hmm, on closer inspection it looks that perf_syscall_enter is broken.
>> ftrace_syscall_enter correctly returns if result of a syscall_get_nr is
>> negative.  The perf version omits the check for negative values.
>
> Yes, that's what I was getting at with the -1 bitmap index. Something like
> this should fix it though:
>
>
> diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
> index 96fc733..bbff120 100644
> --- a/kernel/trace/trace_syscalls.c
> +++ b/kernel/trace/trace_syscalls.c
> @@ -506,13 +506,13 @@ static void perf_syscall_enter(void *ignore, struct pt_regs *regs, long id)
>          int size;
>
>          syscall_nr = syscall_get_nr(current, regs);
> -       if (!test_bit(syscall_nr, enabled_perf_enter_syscalls))
> -               return;
> -
>          sys_data = syscall_nr_to_meta(syscall_nr);
>          if (!sys_data)
>                  return;
>
> +       if (!test_bit(syscall_nr, enabled_perf_enter_syscalls))
> +               return;
> +
>          /* get the size after alignment with the u32 buffer size field */
>          size = sizeof(unsigned long) * sys_data->nb_args + sizeof(*rec);
>          size = ALIGN(size + sizeof(u32), sizeof(u64));
>
>
> If you're happy with that, I can post to LKML and see what people say.
>
> Will

I think you have to make a corresponding change in perf_syscall_exit, 
but yes, this looks right to me.

Thanks,

Wade


From jon-hunter at ti.com  Thu Aug 16 11:04:14 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 16 Aug 2012 10:04:14 -0500
Subject: [RFC RESEND 1/4] arm/dts: OMAP: Add timer nodes
In-Reply-To: <502B67DD.6050904@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-2-git-send-email-jon-hunter@ti.com>
 <5000D647.4090200@gmail.com> <500439A8.1050705@ti.com>
 <500D6CAB.4030504@ti.com> <502B67DD.6050904@ti.com>
Message-ID: <502D0BEE.3010609@ti.com>

Hi Vaibhav,

On 08/15/2012 04:11 AM, Vaibhav Hiremath wrote:
> 
> 
> On 7/23/2012 8:54 PM, Jon Hunter wrote:
>> Hi Rob,
>>
>> On 07/16/2012 10:56 AM, Jon Hunter wrote:
>>> Hi Rob,
>>>
>>> On 07/13/2012 09:15 PM, Rob Herring wrote:
>>>> On 07/13/2012 05:26 PM, Jon Hunter wrote:
>>>>> Add the 12 GP timers nodes present in OMAP3.
>>>>> Add the 11 GP timers nodes present in OMAP4.
>>>>>
>>>>> Add documentation for timer properties specific to OMAP.
>>>>>
>>>>> For each timer an alias is being added. The purpose for doing this is because
>>>>> the OMAP dmtimer driver uses an ID to distinguish between the different timer
>>>>> instances. For example, a timer can be requested by its ID. By adding an alias
>>>>> for each timer we can then use the function of_alias_get_id() to extract the
>>>>> ID for each timer from the alias name. The same method is used for the TTY
>>>>> serial devices. If it is preferred that such an alias is not added and there
>>>>> is a better way to pass an ID from device-tree let me know.
>>>>
>>>> I'm not sure this is really a good use of aliases. UARTs use aliases
>>>> because it is important that the UART number to tty number is known and
>>>> fixed. IIUC, as an example you are picking timer1 because it has
>>>> properties X, Y and Z. If so, then you should describe those h/w
>>>> properties within the timer nodes so you can pick which timer to use
>>>> based on it's h/w properties.
>>>
>>> Thanks for the feedback. What you suggest could definitely work for most
>>> timers. The only item that I would need to resolve here is the handling
>>> of system timers (ie. those used for clockevents and clocksource). These
>>> system timers (for OMAP) are reserved during early boot based upon the
>>> timer ID today and so this is before the actual main timer driver has
>>> been probed and all the attributes of the timers has been read for
>>> device-tree.
>>>
>>> One thought would be to move the reservation of the system timers out of
>>> the kernel and into device-tree itself. Then we query device tree on
>>> start-up to see which we should use. I am wondering if this could be a
>>> better use of alias? For example, say I want to use timer1 as my
>>> clockevent timer and so I could have an alias of ...
>>>
>>> alias {
>>> 	clockevent_timer = &timer1;
>>> }
>>>
>>> However, I am not sure if this is even correct, because there does not
>>> appear to be an API to search the aliases by name and return the
>>> phandle, just of_alias_get_id(). Alternatively, I could add another
>>> property called "ti,timer-clockevent" that is populated for the timer
>>> used as the clockevent timer.
>>
>> Do you have any inputs on the above? Does it make sense to reserve timer
>> resources for kernel system timers in device-tree?
>>
> 
> Hey Jon,
> 
> Did we get conclude on this? I haven't got anything further on this
> thread, this may block baseport support for the new devices in omap2
> family, like AM33xx and OMAP5.

Sorry I have been out of the office. However, no update on this so far.
I need to check with Tony if he has any preference for handling this. I
will follow-up with him and keep you posted.

Cheers
Jon


From js at sig21.net  Thu Aug 16 11:06:47 2012
From: js at sig21.net (Johannes Stezenbach)
Date: Thu, 16 Aug 2012 17:06:47 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <502C92C3.7090701@oberhumer.com>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com>
Message-ID: <20120816150647.GA22010@sig21.net>

On Thu, Aug 16, 2012 at 08:27:15AM +0200, Markus F.X.J. Oberhumer wrote:
> On 2012-08-15 16:45, Johannes Stezenbach wrote:
> > 
> > I made the attached quick hack userspace code
> > using ARM kernel headers and barebox unlzop code.
> > (new == your new code, old == linux-3.5 git, test == new + your suggested change)
> > (sorry I had no time to clean it up)
> 
> My suggested COPY4 replacement probably has a lot of load stalls - maybe some
> ARM expert could have a look and suggest a more efficient implementation.
> 
> In any case, I still would like to see the new code in linux-next because
> of the huge improvements on other modern CPUs.

Well, ~2x speedup on x86 is certainly a good achievement, but there
are more ARM based devices than there are PCs, and I guess many
embedded devices use lzo compressed kernels and file systems
while I'm not convinced many PCs rely on lzo in the kernel.

I know everyone's either busy or on vacation, but it would
be so cool if someone could test on a more modern ARM core,
with the userspace test code I posted it should be easy to do.


Johannes


From imp at bsdimp.com  Thu Aug 16 11:15:18 2012
From: imp at bsdimp.com (Warner Losh)
Date: Thu, 16 Aug 2012 09:15:18 -0600
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <20120816121852.GA7439@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <20120816121852.GA7439@game.jcrosoft.org>
Message-ID: <2ABEF8B7-7F9C-4A5F-8303-0196970CA300@bsdimp.com>


On Aug 16, 2012, at 6:18 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 16:38 Wed 15 Aug     , Linus Walleij wrote:
>>> +static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
>>> +                                               pio + PIO_ABCDSR1);
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
>>> +                                               pio + PIO_ABCDSR2);
>>> +}
>>> +
>>> +static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
>>> +                                               pio + PIO_ABCDSR1);
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
>>> +                                               pio + PIO_ABCDSR2);
>>> +}
>>> +
>>> +static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +       __raw_writel(mask, pio + PIO_ASR);
>>> +}
>>> +
>>> +static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +       __raw_writel(mask, pio + PIO_BSR);
>>> +}
>>> +
>>> +static void at91_mux_set_C_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
>>> +}
>>> +
>>> +static void at91_mux_set_D_periph(void __iomem *pio, unsigned mask)
>>> +{
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
>>> +       __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
>>> +}
>> 
>> I have no clue whatsoever what is going on here, A? B? C? D?
>> Some small comment or something giving a hint about this grouping
>> system and how it works would be really nice.
> periph (mux)
>> 

You should read it in the context that's there.  'A_periph', 'B_periph', etc.  These functions select what device is connected to a given pin.  These are designated A, B, C, or D in the data sheets.  The overloading of PIO names with letters and Peripheral names with letters is mildly confusion in the Atmel datasheets, but is something one quickly gets used to.  Adding a one line comment wouldn't hurt here.  Maybe '/* Select proper peripheral for pin mux. */'

No comments on the rest of the patch, since I've only seen the replies to the original and can't find it any of the archives.  From what was quoted, however, this looks like a giant leap forward.  DT in 3.5 looked to be very limited, and this is one of the last pieces needed to avoid any board specific files in the general case.  I'm glad to see it coming along.

Warner

From tklauser at distanz.ch  Thu Aug 16 11:09:39 2012
From: tklauser at distanz.ch (Tobias Klauser)
Date: Thu, 16 Aug 2012 17:09:39 +0200
Subject: [PATCH v2 07/31] arm64: Process management
In-Reply-To: <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120816150939.GH7141@distanz.ch>

On 2012-08-14 at 19:52:08 +0200, Catalin Marinas <catalin.marinas at arm.com> wrote:
> +void cpu_idle(void)
> +{
> +	local_fiq_enable();
> +
> +	/* endless idle loop with no priority at all */
> +	while (1) {
> +		tick_nohz_idle_enter();
> +		rcu_idle_enter();
> +		while (!need_resched()) {
> +			/*
> +			 * We need to disable interrupts here to ensure
> +			 * we don't miss a wakeup call.
> +			 */
> +			local_irq_disable();
> +			if (!need_resched()) {
> +				stop_critical_timings();
> +				pm_idle();
> +				start_critical_timings();
> +				/*
> +				 * pm_idle functions should always return
> +				 * with IRQs enabled.
> +				 */
> +				WARN_ON(irqs_disabled());
> +			} else {
> +				local_irq_enable();
> +			}
> +		}
> +		rcu_idle_exit();
> +		tick_nohz_idle_exit();
> +		preempt_enable_no_resched();
> +		schedule();
> +		preempt_disable();

You could use schedule_preempt_disabled() instead of the above 3 calls.
See http://lkml.kernel.org/n/tip-24swm5zut3h9c4a6s46x8rws at git.kernel.org

Cheers
Tobias


From swarren at wwwdotorg.org  Thu Aug 16 11:18:20 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 Aug 2012 09:18:20 -0600
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <20120815064902.GB15665@avionic-0098.mockup.avionic-design.de>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
 <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Efy-Dt67rktzNiYfZfOTSu=pmYtyGd3tR-zZQ3jDGtA@mail.gmail.com>
 <20120815064902.GB15665@avionic-0098.mockup.avionic-design.de>
Message-ID: <502D0F3C.4010308@wwwdotorg.org>

On 08/15/2012 12:49 AM, Thierry Reding wrote:
...
> Stephen: Could you try to find out whether the regular
> configuration space translation can just be omitted if we already
> set up the one for the extended configuration space? In
> tegra_pcie_setup_translations(), BAR 0 is setup for regular
> configuration space (which requires a 16 MiB region), while BAR 1
> is setup for the extended configuration space (requiring a full 256
> MiB region). However, if I understand correctly, each of the
> registers that can be accessed via the BAR 0 translation can also
> be accessed via the BAR 1 translation. That seems like we're 
> wasting the 16 MiB set aside for the BAR 0 mapping.

I have confirmed that in theory, the EXTCFG space can indeed be used
to access any register, making the regular config space redundant.
However, using the HW this way has apparently received less validation.


From richard.genoud at gmail.com  Thu Aug 16 11:19:11 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 16 Aug 2012 17:19:11 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>
Message-ID: <CACQ1gAhWdwrXEkicy4ij=rukzS-v98bZRr433Qq5M_Dan5JAog@mail.gmail.com>

2012/8/15 Linus Walleij <linus.walleij at linaro.org>:
> On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
>
>> Cc: Linus Walleij <linus.walleij at linaro.org>
>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> (...)
>> +                               nand {
>> +                                       pinctrl_nand: nand-0 {
>> +                                               atmel,pins =
>> +                                                       <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
>> +                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
>> +                                       };
>> +                               };
>
> Again magic hex I don't understand so skipping this patch -> Nicolas.

Maybe it will be more readable if we use something like :
atmel,pull-up;
atmel,multidrive;
atmel,mux="GPIO"
atmel,mux="A"
...
just my 2 cents...


Richard.


From jgarzik at pobox.com  Thu Aug 16 11:21:49 2012
From: jgarzik at pobox.com (Jeff Garzik)
Date: Thu, 16 Aug 2012 11:21:49 -0400
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <502C92C3.7090701@oberhumer.com>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net> <502C92C3.7090701@oberhumer.com>
Message-ID: <502D100D.2030609@pobox.com>

On 08/16/2012 02:27 AM, Markus F.X.J. Oberhumer wrote:
> On 2012-08-15 16:45, Johannes Stezenbach wrote:
>> On Wed, Aug 15, 2012 at 02:02:43PM +0200, Markus F.X.J. Oberhumer wrote:
>>> On 2012-08-14 14:39, Johannes Stezenbach wrote:
>>>> On Tue, Aug 14, 2012 at 01:44:02AM +0200, Markus F.X.J. Oberhumer wrote:
>>>>> On 2012-07-16 20:30, Markus F.X.J. Oberhumer wrote:
>>>>>>
>>>>>> As stated in the README this version is significantly faster (typically more
>>>>>> than 2 times faster!) than the current version, has been thoroughly tested on
>>>>>> x86_64/i386/powerpc platforms and is intended to get included into the
>>>>>> official Linux 3.6 or 3.7 release.
>>>>>>
>>>>>> I encourage all compression users to test and benchmark this new version,
>>>>>> and I also would ask some official LZO maintainer to convert the updated
>>>>>> source files into a GIT commit and possibly push it to Linus or linux-next.
>>>>
>>>> Sorry for not reporting earlier, but I didn't have time to do real
>>>> benchmarks, just a quick test on ARM926EJ-S using barebox,
>>>> and found in the new version decompression is slower:
>>>> http://lists.infradead.org/pipermail/barebox/2012-July/008268.html
>>>
>>> I can only guess, but maybe your ARM cpu does not have an efficient
>>> implementation of {get,put}_unaligned().
>>
>> Yes, ARMv5 cannot do unaligned access.  ARMv6+ could, but
>> I think the Linux kernel normally traps it for debug,
>> all ARM seem to use generic {get,put}_unaligned() implementation
>> which use byte access and shift.
>
> Hmm - I could imagine that we're wasting a lot of possible speed gain
> by not exploiting that feature on ARMv6+.

Or you could just realize that unaligned accesses are slow in the best 
case, and are simply not supported on some processors.

If you think a little bit, I bet you could come up with a solution that 
operates at cacheline-aligned granularity, something that would be _even 
faster_ than simply fixing the code to do aligned accesses.

	Jeff






From Stefano.Stabellini at eu.citrix.com  Thu Aug 16 11:33:47 2012
From: Stefano.Stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:33:47 +0100
Subject: [PATCH v3 00/23] Introduce Xen support on ARM
Message-ID: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>

Hi all,
this patch series implements Xen support for ARMv7 with virtualization
extensions.  It allows a Linux guest to boot as dom0 and
as domU on Xen on ARM. PV console, disk and network frontends and
backends are all working correctly.

It has been tested on a Versatile Express Cortex A15 emulator, using the
latest Xen ARM developement branch
(git://xenbits.xen.org/people/ianc/xen-unstable.git arm-for-4.3) plus
the "ARM hypercall ABI: 64 bit ready" patch series
(http://marc.info/?l=xen-devel&m=134426267205408), and a simple ad-hoc
tool to build guest domains (marc.info/?l=xen-devel&m=134089788016546).

The patch marked with [HACK] shouldn't be applied and is part of the
series only because it is needed to create domUs.

I am also attaching to this email the dts'es that I am currently using
for dom0 and domU: vexpress-v2p-ca15-tc1.dts (that includes
vexpress-v2m-rs1-rtsm.dtsi) is the dts used for dom0 and it is passed to
Linux by Xen, while vexpress-virt.dts is the dts used for other domUs
and it is appended in binary form to the guest kernel image. I am not
sure where they are supposed to live yet, so I am just attaching them
here so that people can actually try out this series if they want to.

Comments are very welcome!


Changes in v3:
- move patches that have been picked up by Konrad at the end of the
  series;
- improve comments;
- add a doc to describe the Xen Device Tree format;
- do not use xen_ulong_t for multicalls and apic_physbase;
- add a patch at the end of the series to use the new __HVC macro;
- add missing pvclock-abi.h include to ia64 header files;
- do not use an anonymous union in struct xen_add_to_physmap.


Changes in v2:
- fix up many comments and commit messages;
- remove the early_printk patches: rely on the emulated serial for now;
- remove the xen_guest_init patch: without any PV early_printk, we don't
  need any early call to xen_guest_init, we can rely on core_initcall
  alone;
- define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
  at the moment is unused;
- use ldm instead of pop in the hypercall wrappers;
- return -ENOSYS rather than -1 from the unimplemented grant_table
  functions;
- remove the pvclock ifdef in the Xen headers;
- remove include linux/types.h from xen/interface/xen.h;
- replace pr_info with pr_debug in xen_guest_init;
- add a new patch to introduce xen_ulong_t and use it top replace all
  the occurences of unsigned long in the public Xen interface;
- explicitely size all the pointers to 64 bit on ARM, so that the
  hypercall ABI is "64 bit ready";
- clean up xenbus_init;
- make pci.o depend on CONFIG_PCI and acpi.o depend on CONFIG_ACPI;
- mark Xen guest support on ARM as EXPERIMENTAL;
- introduce GRANT_TABLE_PHYSADDR;
- remove unneeded initialization of boot_max_nr_grant_frames;
- add a new patch to clear IRQ_NOAUTOEN and IRQ_NOREQUEST in events.c;
- return -EINVAL from xen_remap_domain_mfn_range if
  auto_translated_physmap;
- retain binary compatibility in xen_add_to_physmap: use a union to
  introduce foreign_domid.


Ian Campbell (1):
      [HACK] xen/arm: implement xen_remap_domain_mfn_range

Stefano Stabellini (24):
      arm: initial Xen support
      xen/arm: hypercalls
      xen/arm: page.h definitions
      xen/arm: sync_bitops
      xen/arm: empty implementation of grant_table arch specific functions
      docs: Xen ARM DT bindings
      xen/arm: Xen detection and shared_info page mapping
      xen/arm: Introduce xen_pfn_t for pfn and mfn types
      xen/arm: Introduce xen_ulong_t for unsigned long
      xen/arm: compile and run xenbus
      xen: do not compile manage, balloon, pci, acpi and cpu_hotplug on ARM
      xen/arm: introduce CONFIG_XEN on ARM
      xen/arm: get privilege status
      xen/arm: initialize grant_table on ARM
      xen/arm: receive Xen events on ARM
      xen: clear IRQ_NOAUTOEN and IRQ_NOREQUEST
      xen/arm: implement alloc/free_xenballooned_pages with alloc_pages/kfree
      xen: allow privcmd for HVM guests
      xen/arm: compile blkfront and blkback
      xen/arm: compile netback
      arm/v2m: initialize arch_timers even if v2m_timer is not present
      xen/arm: use the __HVC macro
      xen: missing includes
      xen: update xen_add_to_physmap interface

 Documentation/devicetree/bindings/arm/xen.txt |   22 +++
 arch/arm/Kconfig                              |   10 +
 arch/arm/Makefile                             |    1 +
 arch/arm/include/asm/hypervisor.h             |    6 +
 arch/arm/include/asm/sync_bitops.h            |   27 +++
 arch/arm/include/asm/xen/events.h             |   18 ++
 arch/arm/include/asm/xen/hypercall.h          |   69 +++++++
 arch/arm/include/asm/xen/hypervisor.h         |   19 ++
 arch/arm/include/asm/xen/interface.h          |   73 ++++++++
 arch/arm/include/asm/xen/page.h               |   82 ++++++++
 arch/arm/mach-vexpress/v2m.c                  |   11 +-
 arch/arm/xen/Makefile                         |    1 +
 arch/arm/xen/enlighten.c                      |  245 +++++++++++++++++++++++++
 arch/arm/xen/grant-table.c                    |   53 ++++++
 arch/arm/xen/hypercall.S                      |  102 ++++++++++
 arch/ia64/include/asm/xen/interface.h         |    8 +-
 arch/x86/include/asm/xen/interface.h          |    8 +
 arch/x86/xen/enlighten.c                      |    1 +
 arch/x86/xen/irq.c                            |    1 +
 arch/x86/xen/mmu.c                            |    3 +
 arch/x86/xen/xen-ops.h                        |    1 -
 drivers/block/xen-blkback/blkback.c           |    1 +
 drivers/net/xen-netback/netback.c             |    1 +
 drivers/net/xen-netfront.c                    |    1 +
 drivers/tty/hvc/hvc_xen.c                     |    2 +
 drivers/xen/Makefile                          |   11 +-
 drivers/xen/events.c                          |   18 ++-
 drivers/xen/grant-table.c                     |    1 +
 drivers/xen/privcmd.c                         |   20 +-
 drivers/xen/xenbus/xenbus_comms.c             |    2 +-
 drivers/xen/xenbus/xenbus_probe.c             |   62 +++++--
 drivers/xen/xenbus/xenbus_probe_frontend.c    |    1 +
 drivers/xen/xenbus/xenbus_xs.c                |    1 +
 drivers/xen/xenfs/super.c                     |    7 +
 include/xen/events.h                          |    2 +
 include/xen/interface/features.h              |    3 +
 include/xen/interface/grant_table.h           |    4 +-
 include/xen/interface/io/protocols.h          |    3 +
 include/xen/interface/memory.h                |   32 ++-
 include/xen/interface/physdev.h               |    2 +-
 include/xen/interface/platform.h              |    4 +-
 include/xen/interface/version.h               |    2 +-
 include/xen/interface/xen.h                   |    7 +-
 include/xen/privcmd.h                         |    3 +-
 include/xen/xen.h                             |    2 +-
 45 files changed, 885 insertions(+), 68 deletions(-)


A branch based on 3.5-rc7 is available here (the __HVC patch is missing
from this branch because it depends on "ARM: opcodes: Facilitate custom
opcode injection" http://marc.info/?l=linux-arm-kernel&m=134442896128124):

git://xenbits.xen.org/people/sstabellini/linux-pvhvm.git 3.5-rc7-arm-3

Cheers,

Stefano
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * ARM Envelope Model v7A (single CPU).
 */

/dts-v1/;

/include/ "skeleton.dtsi"

/ {
	model = "V2P-AEMv7A";
	compatible = "arm,vexpress,v2p-aem,v7a", "arm,vexpress,v2p-aem", "arm,vexpress";
	interrupt-parent = <&gic>;

        chosen {
                bootargs = "earlyprintk debug loglevel=9 console=hvc0 root=/dev/xvda init=/sbin/init";
        };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu at 0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x08000000>;
	};

	gic: interrupt-controller at 2c001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c002000 0x100>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	hypervisor {
		compatible = "xen,xen", "xen,xen-4.2";
		reg = <0xb0000000 0x20000>;
		interrupts = <1 15 0xf08>;
	};

	motherboard {
		arm,v2m-memory-map = "rs1";
		ranges = <0 0 0x08000000 0x04000000>,
			 <1 0 0x14000000 0x04000000>,
			 <2 0 0x18000000 0x04000000>,
			 <3 0 0x1c000000 0x04000000>,
			 <4 0 0x0c000000 0x04000000>,
			 <5 0 0x10000000 0x04000000>;

		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};
};

/* /include/ "vexpress-v2m-rs1-rtsm.dtsi" */
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * original variant (vexpress-v2m.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m.dtsi!
 */

/ {
	aliases {
		arm,v2m_timer = &v2m_timer01;
	};

	motherboard {
		compatible = "simple-bus";
		arm,v2m-memory-map = "rs1";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;

		flash at 0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <4 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		psram at 1,00000000 {
			compatible = "arm,vexpress-psram", "mtd-ram";
			reg = <1 0x00000000 0x02000000>;
			bank-width = <4>;
		};

		vram at 2,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <2 0x00000000 0x00800000>;
		};

		ethernet at 2,02000000 {
			compatible = "smsc,lan91c111";
 			reg = <2 0x02000000 0x10000>;
 			interrupts = <15>;
		};

		usb at 2,03000000 {
			compatible = "nxp,usb-isp1761";
			reg = <2 0x03000000 0x20000>;
			interrupts = <16>;
			port1-otg;
		};

		iofpga at 3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			sysreg at 010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
			};

			sysctl at 020000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
			};

			/* PCI-E I2C bus */
			v2m_i2c_pcie: i2c at 030000 {
				compatible = "arm,versatile-i2c";
				reg = <0x030000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				pcie-switch at 60 {
					compatible = "idt,89hpes32h8";
					reg = <0x60>;
				};
			};

			aaci at 040000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x040000 0x1000>;
				interrupts = <11>;
			};

			mmci at 050000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x050000 0x1000>;
				interrupts = <9 10>;
			};

			kmi at 060000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x060000 0x1000>;
				interrupts = <12>;
			};

			kmi at 070000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x070000 0x1000>;
				interrupts = <13>;
			};

			v2m_serial0: uart at 090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
			};

			v2m_serial1: uart at 0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
			};

			v2m_serial2: uart at 0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
			};

			v2m_serial3: uart at 0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
			};

			wdt at 0f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0>;
			};

			v2m_timer01: timer at 110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <2>;
			};

			v2m_timer23: timer at 120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
			};

			/* DVI I2C bus */
			v2m_i2c_dvi: i2c at 160000 {
				compatible = "arm,versatile-i2c";
				reg = <0x160000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				dvi-transmitter at 39 {
					compatible = "sil,sii9022-tpi", "sil,sii9022";
					reg = <0x39>;
				};

				dvi-transmitter at 60 {
					compatible = "sil,sii9022-cpi", "sil,sii9022";
					reg = <0x60>;
				};
			};

			rtc at 170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <4>;
			};

			compact-flash at 1a0000 {
				compatible = "arm,vexpress-cf", "ata-generic";
				reg = <0x1a0000 0x100
				       0x1a0100 0xf00>;
				reg-shift = <2>;
			};

			clcd at 1f0000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f0000 0x1000>;
				interrupts = <14>;
			};
		};
	};
};
-------------- next part --------------
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 (version with Test Chip 1)
 * Cortex-A15 MPCore (V2P-CA15)
 *
 * HBI-0237A
 */

/dts-v1/;

/ {
	model = "V2P-CA15";
	arm,hbi = <0x237>;
	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
                 bootargs = "dom0_mem=128M";
                 xen,dom0-bootargs = "earlyprintk console=ttyAMA1 root=/dev/mmcblk0 debug rw";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu at 0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	gic: interrupt-controller at 2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c002000 0x1000>,
		      <0x2c004000 0x2000>,
		      <0x2c006000 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
	};
	
	hypervisor {
		compatible = "xen,xen", "xen,xen-4.2";
		reg = <0xb0000000 0x20000>;
		interrupts = <1 15 0xf08>;
	};

	motherboard {
		ranges = <0 0 0x08000000 0x04000000>,
			 <1 0 0x14000000 0x04000000>,
			 <2 0 0x18000000 0x04000000>,
			 <3 0 0x1c000000 0x04000000>,
			 <4 0 0x0c000000 0x04000000>,
			 <5 0 0x10000000 0x04000000>;

		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0  0 4>,
				<0 0  1 &gic 0  1 4>,
				<0 0  2 &gic 0  2 4>,
				<0 0  3 &gic 0  3 4>,
				<0 0  4 &gic 0  4 4>,
				<0 0  5 &gic 0  5 4>,
				<0 0  6 &gic 0  6 4>,
				<0 0  7 &gic 0  7 4>,
				<0 0  8 &gic 0  8 4>,
				<0 0  9 &gic 0  9 4>,
				<0 0 10 &gic 0 10 4>,
				<0 0 11 &gic 0 11 4>,
				<0 0 12 &gic 0 12 4>,
				<0 0 13 &gic 0 13 4>,
				<0 0 14 &gic 0 14 4>,
				<0 0 15 &gic 0 15 4>,
				<0 0 16 &gic 0 16 4>,
				<0 0 17 &gic 0 17 4>,
				<0 0 18 &gic 0 18 4>,
				<0 0 19 &gic 0 19 4>,
				<0 0 20 &gic 0 20 4>,
				<0 0 21 &gic 0 21 4>,
				<0 0 22 &gic 0 22 4>,
				<0 0 23 &gic 0 23 4>,
				<0 0 24 &gic 0 24 4>,
				<0 0 25 &gic 0 25 4>,
				<0 0 26 &gic 0 26 4>,
				<0 0 27 &gic 0 27 4>,
				<0 0 28 &gic 0 28 4>,
				<0 0 29 &gic 0 29 4>,
				<0 0 30 &gic 0 30 4>,
				<0 0 31 &gic 0 31 4>,
				<0 0 32 &gic 0 32 4>,
				<0 0 33 &gic 0 33 4>,
				<0 0 34 &gic 0 34 4>,
				<0 0 35 &gic 0 35 4>,
				<0 0 36 &gic 0 36 4>,
				<0 0 37 &gic 0 37 4>,
				<0 0 38 &gic 0 38 4>,
				<0 0 39 &gic 0 39 4>,
				<0 0 40 &gic 0 40 4>,
				<0 0 41 &gic 0 41 4>,
				<0 0 42 &gic 0 42 4>;
	};
};

/include/ "vexpress-v2m-rs1.dtsi"

From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:55 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:55 +0100
Subject: [PATCH v3 03/25] xen/arm: page.h definitions
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-3-git-send-email-stefano.stabellini@eu.citrix.com>

ARM Xen guests always use paging in hardware, like PV on HVM guests in
the X86 world.

Changes in v3:

- improve comments.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/include/asm/xen/page.h |   82 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/page.h

diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
new file mode 100644
index 0000000..1742023
--- /dev/null
+++ b/arch/arm/include/asm/xen/page.h
@@ -0,0 +1,82 @@
+#ifndef _ASM_ARM_XEN_PAGE_H
+#define _ASM_ARM_XEN_PAGE_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include <linux/pfn.h>
+#include <linux/types.h>
+
+#include <xen/interface/grant_table.h>
+
+#define pfn_to_mfn(pfn)			(pfn)
+#define phys_to_machine_mapping_valid	(1)
+#define mfn_to_pfn(mfn)			(mfn)
+#define mfn_to_virt(m)			(__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+#define pte_mfn	    pte_pfn
+#define mfn_pte	    pfn_pte
+
+/* Xen machine address */
+typedef struct xmaddr {
+	phys_addr_t maddr;
+} xmaddr_t;
+
+/* Xen pseudo-physical address */
+typedef struct xpaddr {
+	phys_addr_t paddr;
+} xpaddr_t;
+
+#define XMADDR(x)	((xmaddr_t) { .maddr = (x) })
+#define XPADDR(x)	((xpaddr_t) { .paddr = (x) })
+
+static inline xmaddr_t phys_to_machine(xpaddr_t phys)
+{
+	unsigned offset = phys.paddr & ~PAGE_MASK;
+	return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+}
+
+static inline xpaddr_t machine_to_phys(xmaddr_t machine)
+{
+	unsigned offset = machine.maddr & ~PAGE_MASK;
+	return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+}
+/* VIRT <-> MACHINE conversion */
+#define virt_to_machine(v)	(phys_to_machine(XPADDR(__pa(v))))
+#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
+#define virt_to_mfn(v)		(pfn_to_mfn(virt_to_pfn(v)))
+#define mfn_to_virt(m)		(__va(mfn_to_pfn(m) << PAGE_SHIFT))
+
+static inline xmaddr_t arbitrary_virt_to_machine(void *vaddr)
+{
+	/* TODO: assuming it is mapped in the kernel 1:1 */
+	return virt_to_machine(vaddr);
+}
+
+/* TODO: this shouldn't be here but it is because the frontend drivers
+ * are using it (its rolled in headers) even though we won't hit the code path.
+ * So for right now just punt with this.
+ */
+static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
+{
+	BUG();
+	return NULL;
+}
+
+static inline int m2p_add_override(unsigned long mfn, struct page *page,
+		struct gnttab_map_grant_ref *kmap_op)
+{
+	return 0;
+}
+
+static inline int m2p_remove_override(struct page *page, bool clear_pte)
+{
+	return 0;
+}
+
+static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
+{
+	BUG();
+	return false;
+}
+#endif /* _ASM_ARM_XEN_PAGE_H */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:56 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:56 +0100
Subject: [PATCH v3 04/25] xen/arm: sync_bitops
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-4-git-send-email-stefano.stabellini@eu.citrix.com>

sync_bitops functions are equivalent to the SMP implementation of the
original functions, independently from CONFIG_SMP being defined.

We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
under Xen you might be communicating with a completely external entity
who might be on another CPU (e.g. two uniprocessor guests communicating
via event channels and grant tables). So we need a variant of the bit
ops which are SMP safe even on a UP kernel.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/include/asm/sync_bitops.h |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/sync_bitops.h

diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
new file mode 100644
index 0000000..63479ee
--- /dev/null
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/system.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)		_set_bit(nr, p)
+#define sync_clear_bit(nr, p)		_clear_bit(nr, p)
+#define sync_change_bit(nr, p)		_change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)	_test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p)	_test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p)	_test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)		test_bit(nr, addr)
+#define sync_cmpxchg			cmpxchg
+
+
+#endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:57 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:57 +0100
Subject: [PATCH v3 05/25] xen/arm: empty implementation of grant_table arch
 specific functions
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-5-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- return -ENOSYS rather than -1.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/xen/Makefile      |    2 +-
 arch/arm/xen/grant-table.c |   53 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/xen/grant-table.c

diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
index b9d6acc..4384103 100644
--- a/arch/arm/xen/Makefile
+++ b/arch/arm/xen/Makefile
@@ -1 +1 @@
-obj-y		:= enlighten.o hypercall.o
+obj-y		:= enlighten.o hypercall.o grant-table.o
diff --git a/arch/arm/xen/grant-table.c b/arch/arm/xen/grant-table.c
new file mode 100644
index 0000000..dbd1330
--- /dev/null
+++ b/arch/arm/xen/grant-table.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+ * grant_table.c
+ * ARM specific part
+ *
+ * Granting foreign access to our memory reservation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <xen/interface/xen.h>
+#include <xen/page.h>
+#include <xen/grant_table.h>
+
+int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
+			   unsigned long max_nr_gframes,
+			   void **__shared)
+{
+	return -ENOSYS;
+}
+
+void arch_gnttab_unmap(void *shared, unsigned long nr_gframes)
+{
+	return;
+}
+
+int arch_gnttab_map_status(uint64_t *frames, unsigned long nr_gframes,
+			   unsigned long max_nr_gframes,
+			   grant_status_t **__shared)
+{
+	return -ENOSYS;
+}
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:53 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:53 +0100
Subject: [PATCH v3 01/25] arm: initial Xen support
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-1-git-send-email-stefano.stabellini@eu.citrix.com>

- Basic hypervisor.h and interface.h definitions.
- Skeleton enlighten.c, set xen_start_info to an empty struct.
- Make xen_initial_domain dependent on the SIF_PRIVILIGED_BIT.

The new code only compiles when CONFIG_XEN is set, that is going to be
added to arch/arm/Kconfig in patch #11 "xen/arm: introduce CONFIG_XEN on
ARM".

Changes in v3:

- improve comments.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/Makefile                     |    1 +
 arch/arm/include/asm/hypervisor.h     |    6 +++
 arch/arm/include/asm/xen/hypervisor.h |   19 ++++++++++
 arch/arm/include/asm/xen/interface.h  |   65 +++++++++++++++++++++++++++++++++
 arch/arm/xen/Makefile                 |    1 +
 arch/arm/xen/enlighten.c              |   35 ++++++++++++++++++
 include/xen/xen.h                     |    2 +-
 7 files changed, 128 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/hypervisor.h
 create mode 100644 arch/arm/include/asm/xen/hypervisor.h
 create mode 100644 arch/arm/include/asm/xen/interface.h
 create mode 100644 arch/arm/xen/Makefile
 create mode 100644 arch/arm/xen/enlighten.c

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00..70aaa82 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -246,6 +246,7 @@ endif
 core-$(CONFIG_FPE_NWFPE)	+= arch/arm/nwfpe/
 core-$(CONFIG_FPE_FASTFPE)	+= $(FASTFPE_OBJ)
 core-$(CONFIG_VFP)		+= arch/arm/vfp/
+core-$(CONFIG_XEN)		+= arch/arm/xen/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
diff --git a/arch/arm/include/asm/hypervisor.h b/arch/arm/include/asm/hypervisor.h
new file mode 100644
index 0000000..b90d9e5
--- /dev/null
+++ b/arch/arm/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_HYPERVISOR_H
+#define _ASM_ARM_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h
new file mode 100644
index 0000000..d7ab99a
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypervisor.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_XEN_HYPERVISOR_H
+#define _ASM_ARM_XEN_HYPERVISOR_H
+
+extern struct shared_info *HYPERVISOR_shared_info;
+extern struct start_info *xen_start_info;
+
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+	PARAVIRT_LAZY_NONE,
+	PARAVIRT_LAZY_MMU,
+	PARAVIRT_LAZY_CPU,
+};
+
+static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
+{
+	return PARAVIRT_LAZY_NONE;
+}
+
+#endif /* _ASM_ARM_XEN_HYPERVISOR_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
new file mode 100644
index 0000000..9e0ec5a
--- /dev/null
+++ b/arch/arm/include/asm/xen/interface.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * Guest OS interface to ARM Xen.
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ */
+
+#ifndef _ASM_ARM_XEN_INTERFACE_H
+#define _ASM_ARM_XEN_INTERFACE_H
+
+#include <linux/types.h>
+
+#define __DEFINE_GUEST_HANDLE(name, type) \
+	typedef type * __guest_handle_ ## name
+
+#define DEFINE_GUEST_HANDLE_STRUCT(name) \
+	__DEFINE_GUEST_HANDLE(name, struct name)
+#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
+#define GUEST_HANDLE(name)        __guest_handle_ ## name
+
+#define set_xen_guest_handle(hnd, val)			\
+	do {						\
+		if (sizeof(hnd) == 8)			\
+			*(uint64_t *)&(hnd) = 0;	\
+		(hnd) = val;				\
+	} while (0)
+
+#ifndef __ASSEMBLY__
+/* Guest handles for primitive C types. */
+__DEFINE_GUEST_HANDLE(uchar, unsigned char);
+__DEFINE_GUEST_HANDLE(uint,  unsigned int);
+__DEFINE_GUEST_HANDLE(ulong, unsigned long);
+DEFINE_GUEST_HANDLE(char);
+DEFINE_GUEST_HANDLE(int);
+DEFINE_GUEST_HANDLE(long);
+DEFINE_GUEST_HANDLE(void);
+DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
+
+/* Maximum number of virtual CPUs in multi-processor guests. */
+#define MAX_VIRT_CPUS 1
+
+struct arch_vcpu_info { };
+struct arch_shared_info { };
+
+/* TODO: Move pvclock definitions some place arch independent */
+struct pvclock_vcpu_time_info {
+	u32   version;
+	u32   pad0;
+	u64   tsc_timestamp;
+	u64   system_time;
+	u32   tsc_to_system_mul;
+	s8    tsc_shift;
+	u8    flags;
+	u8    pad[2];
+} __attribute__((__packed__)); /* 32 bytes */
+
+/* It is OK to have a 12 bytes struct with no padding because it is packed */
+struct pvclock_wall_clock {
+	u32   version;
+	u32   sec;
+	u32   nsec;
+} __attribute__((__packed__));
+#endif
+
+#endif /* _ASM_ARM_XEN_INTERFACE_H */
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
new file mode 100644
index 0000000..0bad594
--- /dev/null
+++ b/arch/arm/xen/Makefile
@@ -0,0 +1 @@
+obj-y		:= enlighten.o
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
new file mode 100644
index 0000000..c535540
--- /dev/null
+++ b/arch/arm/xen/enlighten.c
@@ -0,0 +1,35 @@
+#include <xen/xen.h>
+#include <xen/interface/xen.h>
+#include <xen/interface/memory.h>
+#include <xen/platform_pci.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include <linux/module.h>
+
+struct start_info _xen_start_info;
+struct start_info *xen_start_info = &_xen_start_info;
+EXPORT_SYMBOL_GPL(xen_start_info);
+
+enum xen_domain_type xen_domain_type = XEN_NATIVE;
+EXPORT_SYMBOL_GPL(xen_domain_type);
+
+struct shared_info xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+
+DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
+
+/* TODO: to be removed */
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
+int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+
+int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
+			       unsigned long addr,
+			       unsigned long mfn, int nr,
+			       pgprot_t prot, unsigned domid)
+{
+	return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
diff --git a/include/xen/xen.h b/include/xen/xen.h
index a164024..2c0d3a5 100644
--- a/include/xen/xen.h
+++ b/include/xen/xen.h
@@ -23,7 +23,7 @@ extern enum xen_domain_type xen_domain_type;
 #include <xen/interface/xen.h>
 #include <asm/xen/hypervisor.h>
 
-#define xen_initial_domain()	(xen_pv_domain() && \
+#define xen_initial_domain()	(xen_domain() && \
 				 xen_start_info->flags & SIF_INITDOMAIN)
 #else  /* !CONFIG_XEN_DOM0 */
 #define xen_initial_domain()	(0)
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:59 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:59 +0100
Subject: [PATCH v3 07/25] xen/arm: Xen detection and shared_info page mapping
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-7-git-send-email-stefano.stabellini@eu.citrix.com>

Check for a node in the device tree compatible with "xen,xen", if it is
present set xen_domain_type to XEN_HVM_DOMAIN and continue
initialization.

Map the real shared info page using XENMEM_add_to_physmap with
XENMAPSPACE_shared_info.

Changes in v3:

- use the "xen,xen" notation rather than "arm,xen";
- add an additional check on the presence of the Xen version.

Changes in v2:

- replace pr_info with pr_debug.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   61 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index c535540..78ea1f7 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -5,6 +5,9 @@
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 struct start_info _xen_start_info;
 struct start_info *xen_start_info = &_xen_start_info;
@@ -33,3 +36,61 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 	return -ENOSYS;
 }
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
+
+/*
+ * see Documentation/devicetree/bindings/arm/xen.txt for the
+ * documentation of the Xen Device Tree format.
+ */
+static int __init xen_guest_init(void)
+{
+	struct xen_add_to_physmap xatp;
+	static struct shared_info *shared_info_page = 0;
+	struct device_node *node;
+	int len;
+	const char *s = NULL;
+	const char *version = NULL;
+	const char *xen_prefix = "xen,xen-";
+
+	node = of_find_compatible_node(NULL, NULL, "xen,xen");
+	if (!node) {
+		pr_debug("No Xen support\n");
+		return 0;
+	}
+	s = of_get_property(node, "compatible", &len);
+	if (strlen(s) + strlen(xen_prefix) + 1  < len &&
+			!strncmp(xen_prefix, s + strlen(s) + 1, strlen(xen_prefix)))
+		version = s + strlen(s) + strlen(xen_prefix) + 1;
+	if (version == NULL) {
+		pr_debug("Xen version not found\n");
+		return 0;
+	}
+	xen_domain_type = XEN_HVM_DOMAIN;
+
+	if (!shared_info_page)
+		shared_info_page = (struct shared_info *)
+			get_zeroed_page(GFP_KERNEL);
+	if (!shared_info_page) {
+		pr_err("not enough memory\n");
+		return -ENOMEM;
+	}
+	xatp.domid = DOMID_SELF;
+	xatp.idx = 0;
+	xatp.space = XENMAPSPACE_shared_info;
+	xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+	if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+		BUG();
+
+	HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+	/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+	 * page, we use it in the event channel upcall and in some pvclock
+	 * related functions. We don't need the vcpu_info placement
+	 * optimizations because we don't use any pv_mmu or pv_irq op on
+	 * HVM.
+	 * The shared info contains exactly 1 CPU (the boot CPU). The guest
+	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
+	 * for secondary CPUs as they are brought up. */
+	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+	return 0;
+}
+core_initcall(xen_guest_init);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:58 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:58 +0100
Subject: [PATCH v3 06/25] docs: Xen ARM DT bindings
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-6-git-send-email-stefano.stabellini@eu.citrix.com>

Add a doc to describe the Xen ARM device tree bindings

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: devicetree-discuss at lists.ozlabs.org
CC: David Vrabel <david.vrabel at citrix.com>
---
 Documentation/devicetree/bindings/arm/xen.txt |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/xen.txt

diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt
new file mode 100644
index 0000000..ec6d884
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/xen.txt
@@ -0,0 +1,22 @@
+* Xen hypervisor device tree bindings
+
+Xen ARM virtual platforms shall have the following properties:
+
+- compatible:
+	compatible = "xen,xen", "xen,xen-<version>";
+  where <version> is the version of the Xen ABI of the platform.
+
+- reg: specifies the base physical address and size of a region in
+  memory where the grant table should be mapped to, using an
+  HYPERVISOR_memory_op hypercall. 
+
+- interrupts: the interrupt used by Xen to inject event notifications.
+
+
+Example:
+
+hypervisor {
+	compatible = "xen,xen", "xen,xen-4.3";
+	reg = <0xb0000000 0x20000>;
+	interrupts = <1 15 0xf08>;
+};
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:35:54 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:35:54 +0100
Subject: [PATCH v3 02/25] xen/arm: hypercalls
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-2-git-send-email-stefano.stabellini@eu.citrix.com>

Use r12 to pass the hypercall number to the hypervisor.

We need a register to pass the hypercall number because we might not
know it at compile time and HVC only takes an immediate argument.

Among the available registers r12 seems to be the best choice because it
is defined as "intra-procedure call scratch register".

Use the ISS to pass an hypervisor specific tag.


Changes in v2:
- define an HYPERCALL macro for 5 arguments hypercall wrappers, even if
at the moment is unused;
- use ldm instead of pop;
- fix up comments.


Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/hypercall.h |   50 ++++++++++++++++
 arch/arm/xen/Makefile                |    2 +-
 arch/arm/xen/hypercall.S             |  106 ++++++++++++++++++++++++++++++++++
 3 files changed, 157 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/hypercall.h
 create mode 100644 arch/arm/xen/hypercall.S

diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
new file mode 100644
index 0000000..4ac0624
--- /dev/null
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+ * hypercall.h
+ *
+ * Linux-specific hypervisor handling.
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef _ASM_ARM_XEN_HYPERCALL_H
+#define _ASM_ARM_XEN_HYPERCALL_H
+
+#include <xen/interface/xen.h>
+
+long privcmd_call(unsigned call, unsigned long a1,
+		unsigned long a2, unsigned long a3,
+		unsigned long a4, unsigned long a5);
+int HYPERVISOR_xen_version(int cmd, void *arg);
+int HYPERVISOR_console_io(int cmd, int count, char *str);
+int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count);
+int HYPERVISOR_sched_op(int cmd, void *arg);
+int HYPERVISOR_event_channel_op(int cmd, void *arg);
+unsigned long HYPERVISOR_hvm_op(int op, void *arg);
+int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
+int HYPERVISOR_physdev_op(int cmd, void *arg);
+
+#endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile
index 0bad594..b9d6acc 100644
--- a/arch/arm/xen/Makefile
+++ b/arch/arm/xen/Makefile
@@ -1 +1 @@
-obj-y		:= enlighten.o
+obj-y		:= enlighten.o hypercall.o
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
new file mode 100644
index 0000000..074f5ed
--- /dev/null
+++ b/arch/arm/xen/hypercall.S
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini at eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the ARM
+ * procedure calling convention: the first paramter is passed in r0, the
+ * second in r1, the third in r2 and the fourth in r3. Considering that
+ * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * in r4, differently from the procedure calling convention of using the
+ * stack for that case.
+ *
+ * The hypercall number is passed in r12.
+ *
+ * The return value is in r0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+/* HVC 0xEA1 */
+#ifdef CONFIG_THUMB2_KERNEL
+#define xen_hvc .word 0xf7e08ea1
+#else
+#define xen_hvc .word 0xe140ea71
+#endif
+
+#define HYPERCALL_SIMPLE(hypercall)		\
+ENTRY(HYPERVISOR_##hypercall)			\
+	mov r12, #__HYPERVISOR_##hypercall;	\
+	xen_hvc;							\
+	mov pc, lr;							\
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+
+#define HYPERCALL5(hypercall)			\
+ENTRY(HYPERVISOR_##hypercall)			\
+	stmdb sp!, {r4}						\
+	ldr r4, [sp, #4]					\
+	mov r12, #__HYPERVISOR_##hypercall;	\
+	xen_hvc								\
+	ldm sp!, {r4}						\
+	mov pc, lr							\
+ENDPROC(HYPERVISOR_##hypercall)
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+
+ENTRY(privcmd_call)
+	stmdb sp!, {r4}
+	mov r12, r0
+	mov r0, r1
+	mov r1, r2
+	mov r2, r3
+	ldr r3, [sp, #8]
+	ldr r4, [sp, #4]
+	xen_hvc
+	ldm sp!, {r4}
+	mov pc, lr
+ENDPROC(privcmd_call);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:01 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:01 +0100
Subject: [PATCH v3 09/25] xen/arm: Introduce xen_ulong_t for unsigned long
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-9-git-send-email-stefano.stabellini@eu.citrix.com>

All the original Xen headers have xen_ulong_t as unsigned long type, however
when they have been imported in Linux, xen_ulong_t has been replaced with
unsigned long. That might work for x86 and ia64 but it does not for arm.
Bring back xen_ulong_t and let each architecture define xen_ulong_t as they
see fit.

Also explicitly size pointers (__DEFINE_GUEST_HANDLE) to 64 bit.


Changes in v3:

- remove the incorrect changes to multicall_entry;
- remove the change to apic_physbase.


Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/interface.h  |    8 ++++++--
 arch/ia64/include/asm/xen/interface.h |    1 +
 arch/x86/include/asm/xen/interface.h  |    1 +
 include/xen/interface/memory.h        |   12 ++++++------
 include/xen/interface/physdev.h       |    2 +-
 include/xen/interface/version.h       |    2 +-
 6 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index 74c72b5..ae05e56 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -9,8 +9,11 @@
 
 #include <linux/types.h>
 
+#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
+
 #define __DEFINE_GUEST_HANDLE(name, type) \
-	typedef type * __guest_handle_ ## name
+	typedef struct { union { type *p; uint64_aligned_t q; }; }  \
+        __guest_handle_ ## name
 
 #define DEFINE_GUEST_HANDLE_STRUCT(name) \
 	__DEFINE_GUEST_HANDLE(name, struct name)
@@ -21,13 +24,14 @@
 	do {						\
 		if (sizeof(hnd) == 8)			\
 			*(uint64_t *)&(hnd) = 0;	\
-		(hnd) = val;				\
+		(hnd).p = val;				\
 	} while (0)
 
 #ifndef __ASSEMBLY__
 /* Explicitly size integers that represent pfns in the interface with
  * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
 typedef uint64_t xen_pfn_t;
+typedef uint64_t xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 686464e..7c83445 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -71,6 +71,7 @@
  * with Xen so that we could have one ABI that works for 32 and 64 bit
  * guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index 2289075..25cc8df 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -51,6 +51,7 @@
  * with Xen so that on ARM we can have one ABI that works for 32 and 64
  * bit guests. */
 typedef unsigned long xen_pfn_t;
+typedef unsigned long xen_ulong_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index abbbff0..b5c3098 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -34,7 +34,7 @@ struct xen_memory_reservation {
     GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /* Number of extents, and size/alignment of each (2^extent_order pages). */
-    unsigned long  nr_extents;
+    xen_ulong_t  nr_extents;
     unsigned int   extent_order;
 
     /*
@@ -92,7 +92,7 @@ struct xen_memory_exchange {
      *     command will be non-zero.
      *  5. THIS FIELD MUST BE INITIALISED TO ZERO BY THE CALLER!
      */
-    unsigned long nr_exchanged;
+    xen_ulong_t nr_exchanged;
 };
 
 DEFINE_GUEST_HANDLE_STRUCT(xen_memory_exchange);
@@ -148,8 +148,8 @@ DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list);
  */
 #define XENMEM_machphys_mapping     12
 struct xen_machphys_mapping {
-    unsigned long v_start, v_end; /* Start and end virtual addresses.   */
-    unsigned long max_mfn;        /* Maximum MFN that can be looked up. */
+    xen_ulong_t v_start, v_end; /* Start and end virtual addresses.   */
+    xen_ulong_t max_mfn;        /* Maximum MFN that can be looked up. */
 };
 DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mapping_t);
 
@@ -169,7 +169,7 @@ struct xen_add_to_physmap {
     unsigned int space;
 
     /* Index into source mapping space. */
-    unsigned long idx;
+    xen_ulong_t idx;
 
     /* GPFN where the source mapping page should appear. */
     xen_pfn_t gpfn;
@@ -186,7 +186,7 @@ struct xen_translate_gpfn_list {
     domid_t domid;
 
     /* Length of list. */
-    unsigned long nr_gpfns;
+    xen_ulong_t nr_gpfns;
 
     /* List of GPFNs to translate. */
     GUEST_HANDLE(ulong) gpfn_list;
diff --git a/include/xen/interface/physdev.h b/include/xen/interface/physdev.h
index 9ce788d..f616514 100644
--- a/include/xen/interface/physdev.h
+++ b/include/xen/interface/physdev.h
@@ -56,7 +56,7 @@ struct physdev_eoi {
 #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
 struct physdev_pirq_eoi_gmfn {
     /* IN */
-    unsigned long gmfn;
+    xen_ulong_t gmfn;
 };
 
 /*
diff --git a/include/xen/interface/version.h b/include/xen/interface/version.h
index e8b6519..30280c9 100644
--- a/include/xen/interface/version.h
+++ b/include/xen/interface/version.h
@@ -45,7 +45,7 @@ struct xen_changeset_info {
 
 #define XENVER_platform_parameters 5
 struct xen_platform_parameters {
-    unsigned long virt_start;
+    xen_ulong_t virt_start;
 };
 
 #define XENVER_get_features 6
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:02 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:02 +0100
Subject: [PATCH v3 10/25] xen/arm: compile and run xenbus
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-10-git-send-email-stefano.stabellini@eu.citrix.com>

bind_evtchn_to_irqhandler can legitimately return 0 (irq 0): it is not
an error.

If Linux is running as an HVM domain and is running as Dom0, use
xenstored_local_init to initialize the xenstore page and event channel.

Changes in v2:

- refactor xenbus_init.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 drivers/xen/xenbus/xenbus_comms.c |    2 +-
 drivers/xen/xenbus/xenbus_probe.c |   62 +++++++++++++++++++++++++-----------
 drivers/xen/xenbus/xenbus_xs.c    |    1 +
 3 files changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
index 52fe7ad..c5aa55c 100644
--- a/drivers/xen/xenbus/xenbus_comms.c
+++ b/drivers/xen/xenbus/xenbus_comms.c
@@ -224,7 +224,7 @@ int xb_init_comms(void)
 		int err;
 		err = bind_evtchn_to_irqhandler(xen_store_evtchn, wake_waiting,
 						0, "xenbus", &xb_waitq);
-		if (err <= 0) {
+		if (err < 0) {
 			printk(KERN_ERR "XENBUS request irq failed %i\n", err);
 			return err;
 		}
diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
index b793723..a67ccc0 100644
--- a/drivers/xen/xenbus/xenbus_probe.c
+++ b/drivers/xen/xenbus/xenbus_probe.c
@@ -719,37 +719,61 @@ static int __init xenstored_local_init(void)
 	return err;
 }
 
+enum xenstore_init {
+	UNKNOWN,
+	PV,
+	HVM,
+	LOCAL,
+};
 static int __init xenbus_init(void)
 {
 	int err = 0;
+	enum xenstore_init usage = UNKNOWN;
+	uint64_t v = 0;
 
 	if (!xen_domain())
 		return -ENODEV;
 
 	xenbus_ring_ops_init();
 
-	if (xen_hvm_domain()) {
-		uint64_t v = 0;
-		err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
-		if (err)
-			goto out_error;
-		xen_store_evtchn = (int)v;
-		err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
-		if (err)
-			goto out_error;
-		xen_store_mfn = (unsigned long)v;
-		xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
-	} else {
-		xen_store_evtchn = xen_start_info->store_evtchn;
-		xen_store_mfn = xen_start_info->store_mfn;
-		if (xen_store_evtchn)
-			xenstored_ready = 1;
-		else {
+	if (xen_pv_domain())
+		usage = PV;
+	if (xen_hvm_domain())
+		usage = HVM;
+	if (xen_hvm_domain() && xen_initial_domain())
+		usage = LOCAL;
+	if (xen_pv_domain() && !xen_start_info->store_evtchn)
+		usage = LOCAL;
+	if (xen_pv_domain() && xen_start_info->store_evtchn)
+		xenstored_ready = 1;
+
+	switch (usage) {
+		case LOCAL:
 			err = xenstored_local_init();
 			if (err)
 				goto out_error;
-		}
-		xen_store_interface = mfn_to_virt(xen_store_mfn);
+			xen_store_interface = mfn_to_virt(xen_store_mfn);
+			break;
+		case PV:
+			xen_store_evtchn = xen_start_info->store_evtchn;
+			xen_store_mfn = xen_start_info->store_mfn;
+			xen_store_interface = mfn_to_virt(xen_store_mfn);
+			break;
+		case HVM:
+			err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
+			if (err)
+				goto out_error;
+			xen_store_evtchn = (int)v;
+			err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
+			if (err)
+				goto out_error;
+			xen_store_mfn = (unsigned long)v;
+			xen_store_interface =
+				ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
+			break;
+		default:
+			pr_warn("Xenstore state unknown\n");
+			break;
 	}
 
 	/* Initialize the interface to xenstore. */
diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
index d1c217b..f7feb3d 100644
--- a/drivers/xen/xenbus/xenbus_xs.c
+++ b/drivers/xen/xenbus/xenbus_xs.c
@@ -44,6 +44,7 @@
 #include <linux/rwsem.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <asm/xen/hypervisor.h>
 #include <xen/xenbus.h>
 #include <xen/xen.h>
 #include "xenbus_comms.h"
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:00 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:00 +0100
Subject: [PATCH v3 08/25] xen/arm: Introduce xen_pfn_t for pfn and mfn types
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-8-git-send-email-stefano.stabellini@eu.citrix.com>

All the original Xen headers have xen_pfn_t as mfn and pfn type, however
when they have been imported in Linux, xen_pfn_t has been replaced with
unsigned long. That might work for x86 and ia64 but it does not for arm.
Bring back xen_pfn_t and let each architecture define xen_pfn_t as they
see fit.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/include/asm/xen/interface.h  |    4 ++++
 arch/ia64/include/asm/xen/interface.h |    5 ++++-
 arch/x86/include/asm/xen/interface.h  |    5 +++++
 include/xen/interface/grant_table.h   |    4 ++--
 include/xen/interface/memory.h        |    6 +++---
 include/xen/interface/platform.h      |    4 ++--
 include/xen/interface/xen.h           |    6 +++---
 include/xen/privcmd.h                 |    2 --
 8 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index 9e0ec5a..74c72b5 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -25,6 +25,9 @@
 	} while (0)
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the interface with
+ * Xen so that we can have one ABI that works for 32 and 64 bit guests. */
+typedef uint64_t xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
@@ -35,6 +38,7 @@ DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
 
 /* Maximum number of virtual CPUs in multi-processor guests. */
 #define MAX_VIRT_CPUS 1
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 09d5f7f..686464e 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -67,6 +67,10 @@
 #define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the public interface
+ * with Xen so that we could have one ABI that works for 32 and 64 bit
+ * guests. */
+typedef unsigned long xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint, unsigned int);
@@ -79,7 +83,6 @@ DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
 
-typedef unsigned long xen_pfn_t;
 DEFINE_GUEST_HANDLE(xen_pfn_t);
 #define PRI_xen_pfn	"lx"
 #endif
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index cbf0c9d..2289075 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -47,6 +47,10 @@
 #endif
 
 #ifndef __ASSEMBLY__
+/* Explicitly size integers that represent pfns in the public interface
+ * with Xen so that on ARM we can have one ABI that works for 32 and 64
+ * bit guests. */
+typedef unsigned long xen_pfn_t;
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
@@ -57,6 +61,7 @@ DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
 DEFINE_GUEST_HANDLE(uint32_t);
+DEFINE_GUEST_HANDLE(xen_pfn_t);
 #endif
 
 #ifndef HYPERVISOR_VIRT_START
diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h
index a17d844..7da811b 100644
--- a/include/xen/interface/grant_table.h
+++ b/include/xen/interface/grant_table.h
@@ -338,7 +338,7 @@ DEFINE_GUEST_HANDLE_STRUCT(gnttab_dump_table);
 #define GNTTABOP_transfer                4
 struct gnttab_transfer {
     /* IN parameters. */
-    unsigned long mfn;
+    xen_pfn_t mfn;
     domid_t       domid;
     grant_ref_t   ref;
     /* OUT parameters. */
@@ -375,7 +375,7 @@ struct gnttab_copy {
 	struct {
 		union {
 			grant_ref_t ref;
-			unsigned long   gmfn;
+			xen_pfn_t   gmfn;
 		} u;
 		domid_t  domid;
 		uint16_t offset;
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index eac3ce1..abbbff0 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -31,7 +31,7 @@ struct xen_memory_reservation {
      *   OUT: GMFN bases of extents that were allocated
      *   (NB. This command also updates the mach_to_phys translation table)
      */
-    GUEST_HANDLE(ulong) extent_start;
+    GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /* Number of extents, and size/alignment of each (2^extent_order pages). */
     unsigned long  nr_extents;
@@ -130,7 +130,7 @@ struct xen_machphys_mfn_list {
      * any large discontiguities in the machine address space, 2MB gaps in
      * the machphys table will be represented by an MFN base of zero.
      */
-    GUEST_HANDLE(ulong) extent_start;
+    GUEST_HANDLE(xen_pfn_t) extent_start;
 
     /*
      * Number of extents written to the above array. This will be smaller
@@ -172,7 +172,7 @@ struct xen_add_to_physmap {
     unsigned long idx;
 
     /* GPFN where the source mapping page should appear. */
-    unsigned long gpfn;
+    xen_pfn_t gpfn;
 };
 DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap);
 
diff --git a/include/xen/interface/platform.h b/include/xen/interface/platform.h
index 486653f..0bea470 100644
--- a/include/xen/interface/platform.h
+++ b/include/xen/interface/platform.h
@@ -54,7 +54,7 @@ DEFINE_GUEST_HANDLE_STRUCT(xenpf_settime_t);
 #define XENPF_add_memtype         31
 struct xenpf_add_memtype {
 	/* IN variables. */
-	unsigned long mfn;
+	xen_pfn_t mfn;
 	uint64_t nr_mfns;
 	uint32_t type;
 	/* OUT variables. */
@@ -84,7 +84,7 @@ struct xenpf_read_memtype {
 	/* IN variables. */
 	uint32_t reg;
 	/* OUT variables. */
-	unsigned long mfn;
+	xen_pfn_t mfn;
 	uint64_t nr_mfns;
 	uint32_t type;
 };
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index a890804..f6b8965 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -189,7 +189,7 @@ struct mmuext_op {
 	unsigned int cmd;
 	union {
 		/* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR */
-		unsigned long mfn;
+		xen_pfn_t mfn;
 		/* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
 		unsigned long linear_addr;
 	} arg1;
@@ -429,11 +429,11 @@ struct start_info {
 	unsigned long nr_pages;     /* Total pages allocated to this domain.  */
 	unsigned long shared_info;  /* MACHINE address of shared info struct. */
 	uint32_t flags;             /* SIF_xxx flags.                         */
-	unsigned long store_mfn;    /* MACHINE page number of shared page.    */
+	xen_pfn_t store_mfn;        /* MACHINE page number of shared page.    */
 	uint32_t store_evtchn;      /* Event channel for store communication. */
 	union {
 		struct {
-			unsigned long mfn;  /* MACHINE page number of console page.   */
+			xen_pfn_t mfn;      /* MACHINE page number of console page.   */
 			uint32_t  evtchn;   /* Event channel for console page.        */
 		} domU;
 		struct {
diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
index 17857fb..59f1bd8 100644
--- a/include/xen/privcmd.h
+++ b/include/xen/privcmd.h
@@ -36,8 +36,6 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
-typedef unsigned long xen_pfn_t;
-
 struct privcmd_hypercall {
 	__u64 op;
 	__u64 arg[5];
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:03 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:03 +0100
Subject: [PATCH v3 11/25] xen: do not compile manage, balloon, pci,
 acpi and cpu_hotplug on ARM
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-11-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- make pci.o depend on CONFIG_PCI and acpi.o depend on CONFIG_ACPI.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 drivers/xen/Makefile |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index fc34886..bee02b2 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -1,11 +1,17 @@
-obj-y	+= grant-table.o features.o events.o manage.o balloon.o
+ifneq ($(CONFIG_ARM),y)
+obj-y	+= manage.o balloon.o
+obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
+endif
+obj-y	+= grant-table.o features.o events.o
 obj-y	+= xenbus/
 
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_features.o			:= $(nostackp)
 
+obj-$(CONFIG_XEN_DOM0)			+= $(dom0-y)
+dom0-$(CONFIG_PCI) := pci.o
+dom0-$(CONFIG_ACPI) := acpi.o
 obj-$(CONFIG_BLOCK)			+= biomerge.o
-obj-$(CONFIG_HOTPLUG_CPU)		+= cpu_hotplug.o
 obj-$(CONFIG_XEN_XENCOMM)		+= xencomm.o
 obj-$(CONFIG_XEN_BALLOON)		+= xen-balloon.o
 obj-$(CONFIG_XEN_SELFBALLOONING)	+= xen-selfballoon.o
@@ -17,7 +23,6 @@ obj-$(CONFIG_XEN_SYS_HYPERVISOR)	+= sys-hypervisor.o
 obj-$(CONFIG_XEN_PVHVM)			+= platform-pci.o
 obj-$(CONFIG_XEN_TMEM)			+= tmem.o
 obj-$(CONFIG_SWIOTLB_XEN)		+= swiotlb-xen.o
-obj-$(CONFIG_XEN_DOM0)			+= pci.o acpi.o
 obj-$(CONFIG_XEN_PCIDEV_BACKEND)	+= xen-pciback/
 obj-$(CONFIG_XEN_PRIVCMD)		+= xen-privcmd.o
 obj-$(CONFIG_XEN_ACPI_PROCESSOR)	+= xen-acpi-processor.o
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:17 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:17 +0100
Subject: [PATCH v3 25/25] [HACK] xen/arm: implement xen_remap_domain_mfn_range
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-25-git-send-email-stefano.stabellini@eu.citrix.com>

From: Ian Campbell <Ian.Campbell at citrix.com>

Do not apply!

This is a simple, hacky implementation of xen_remap_domain_mfn_range,
using XENMAPSPACE_gmfn_foreign.

It should use same interface as hybrid x86.


Changes in v2:

- retain binary compatibility in xen_add_to_physmap: use a union.

Changes in v3:

- do not use an anonymous union.


Signed-off-by: Ian Campbell <Ian.Campbell at citrix.com>
Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c       |   79 +++++++++++++++++++++++++++++++++++++++-
 drivers/xen/privcmd.c          |   16 +++++----
 drivers/xen/xenfs/super.c      |    7 ++++
 include/xen/interface/memory.h |   15 ++++++--
 4 files changed, 105 insertions(+), 12 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 3348d90..4616412 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -16,6 +16,10 @@
 #include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+
+#include <asm/pgtable.h>
 
 struct start_info _xen_start_info;
 struct start_info *xen_start_info = &_xen_start_info;
@@ -38,12 +42,85 @@ EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 
 static __read_mostly int xen_events_irq = -1;
 
+#define FOREIGN_MAP_BUFFER 0x90000000UL
+#define FOREIGN_MAP_BUFFER_SIZE 0x10000000UL
+struct resource foreign_map_resource = {
+	.start = FOREIGN_MAP_BUFFER,
+	.end = FOREIGN_MAP_BUFFER + FOREIGN_MAP_BUFFER_SIZE,
+	.name = "Xen foreign map buffer",
+	.flags = 0,
+};
+
+static unsigned long foreign_map_buffer_pfn = FOREIGN_MAP_BUFFER >> PAGE_SHIFT;
+
+struct remap_data {
+	struct mm_struct *mm;
+	unsigned long mfn;
+	pgprot_t prot;
+};
+
+static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
+				 unsigned long addr, void *data)
+{
+	struct remap_data *rmd = data;
+	pte_t pte = pfn_pte(rmd->mfn, rmd->prot);
+
+	if (rmd->mfn < 0x90010)
+		pr_crit("%s: ptep %p addr %#lx => %#x / %#lx\n",
+		       __func__, ptep, addr, pte_val(pte), rmd->mfn);
+
+	set_pte_at(rmd->mm, addr, ptep, pte);
+
+	rmd->mfn++;
+	return 0;
+}
+
 int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 			       unsigned long addr,
 			       unsigned long mfn, int nr,
 			       pgprot_t prot, unsigned domid)
 {
-	return -ENOSYS;
+	int i, rc = 0;
+	struct remap_data rmd = {
+		.mm = vma->vm_mm,
+		.prot = prot,
+	};
+	struct xen_add_to_physmap xatp = {
+		.domid = DOMID_SELF,
+		.space = XENMAPSPACE_gmfn_foreign,
+
+		.u.foreign_domid = domid,
+	};
+
+	if (foreign_map_buffer_pfn + nr > ((FOREIGN_MAP_BUFFER +
+					FOREIGN_MAP_BUFFER_SIZE)>>PAGE_SHIFT)) {
+		pr_crit("RAM out of foreign map buffers...\n");
+		return -EBUSY;
+	}
+
+	for (i = 0; i < nr; i++) {
+		xatp.idx = mfn + i;
+		xatp.gpfn = foreign_map_buffer_pfn + i;
+		rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
+		if (rc != 0) {
+			pr_crit("foreign map add_to_physmap failed, err=%d\n", rc);
+			goto out;
+		}
+	}
+
+	rmd.mfn = foreign_map_buffer_pfn;
+	rc = apply_to_page_range(vma->vm_mm,
+				 addr,
+				 (unsigned long)nr << PAGE_SHIFT,
+				 remap_area_mfn_pte_fn, &rmd);
+	if (rc != 0) {
+		pr_crit("apply_to_page_range failed rc=%d\n", rc);
+		goto out;
+	}
+
+	foreign_map_buffer_pfn += nr;
+out:
+	return rc;
 }
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
 
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 85226cb..3e15c22 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -20,6 +20,8 @@
 #include <linux/pagemap.h>
 #include <linux/seq_file.h>
 #include <linux/miscdevice.h>
+#include <linux/resource.h>
+#include <linux/ioport.h>
 
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
@@ -196,9 +198,6 @@ static long privcmd_ioctl_mmap(void __user *udata)
 	LIST_HEAD(pagelist);
 	struct mmap_mfn_state state;
 
-	if (!xen_initial_domain())
-		return -EPERM;
-
 	if (copy_from_user(&mmapcmd, udata, sizeof(mmapcmd)))
 		return -EFAULT;
 
@@ -286,9 +285,6 @@ static long privcmd_ioctl_mmap_batch(void __user *udata)
 	LIST_HEAD(pagelist);
 	struct mmap_batch_state state;
 
-	if (!xen_initial_domain())
-		return -EPERM;
-
 	if (copy_from_user(&m, udata, sizeof(m)))
 		return -EFAULT;
 
@@ -365,6 +361,11 @@ static long privcmd_ioctl(struct file *file,
 	return ret;
 }
 
+static void privcmd_close(struct vm_area_struct *vma)
+{
+	/* TODO: unmap VMA */
+}
+
 static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 {
 	printk(KERN_DEBUG "privcmd_fault: vma=%p %lx-%lx, pgoff=%lx, uv=%p\n",
@@ -375,7 +376,8 @@ static int privcmd_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 }
 
 static struct vm_operations_struct privcmd_vm_ops = {
-	.fault = privcmd_fault
+	.fault = privcmd_fault,
+	.close = privcmd_close,
 };
 
 static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
diff --git a/drivers/xen/xenfs/super.c b/drivers/xen/xenfs/super.c
index a84b53c..edbe22f 100644
--- a/drivers/xen/xenfs/super.c
+++ b/drivers/xen/xenfs/super.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/magic.h>
+#include <linux/ioport.h>
 
 #include <xen/xen.h>
 
@@ -80,6 +81,8 @@ static const struct file_operations capabilities_file_ops = {
 	.llseek = default_llseek,
 };
 
+extern struct resource foreign_map_resource;
+
 static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
 {
 	static struct tree_descr xenfs_files[] = {
@@ -100,6 +103,10 @@ static int xenfs_fill_super(struct super_block *sb, void *data, int silent)
 				  &xsd_kva_file_ops, NULL, S_IRUSR|S_IWUSR);
 		xenfs_create_file(sb, sb->s_root, "xsd_port",
 				  &xsd_port_file_ops, NULL, S_IRUSR|S_IWUSR);
+		rc = request_resource(&iomem_resource, &foreign_map_resource);
+		if (rc < 0)
+			pr_crit("failed to register foreign map resource\n");
+		rc = 0; /* ignore */
 	}
 
 	return rc;
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index b66d04c..99c5052 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -163,12 +163,19 @@ struct xen_add_to_physmap {
     /* Which domain to change the mapping for. */
     domid_t domid;
 
-    /* Number of pages to go through for gmfn_range */
-    uint16_t    size;
+    union {
+        /* Number of pages to go through for gmfn_range */
+        uint16_t    size;
+        /* IFF gmfn_foreign */
+        domid_t foreign_domid;
+    } u;
 
     /* Source mapping space. */
-#define XENMAPSPACE_shared_info 0 /* shared info page */
-#define XENMAPSPACE_grant_table 1 /* grant table page */
+#define XENMAPSPACE_shared_info  0 /* shared info page */
+#define XENMAPSPACE_grant_table  1 /* grant table page */
+#define XENMAPSPACE_gmfn         2 /* GMFN */
+#define XENMAPSPACE_gmfn_range   3 /* GMFN range */
+#define XENMAPSPACE_gmfn_foreign 4 /* GMFN from another guest */
     unsigned int space;
 
     /* Index into source mapping space. */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:12 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:12 +0100
Subject: [PATCH v3 20/25] xen/arm: compile netback
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-20-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/include/asm/xen/hypercall.h |   19 +++++++++++++++++++
 drivers/net/xen-netback/netback.c    |    1 +
 drivers/net/xen-netfront.c           |    1 +
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
index 4ac0624..8a82325 100644
--- a/arch/arm/include/asm/xen/hypercall.h
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -47,4 +47,23 @@ unsigned long HYPERVISOR_hvm_op(int op, void *arg);
 int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
 int HYPERVISOR_physdev_op(int cmd, void *arg);
 
+static inline void
+MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
+			unsigned int new_val, unsigned long flags)
+{
+	BUG();
+}
+
+static inline void
+MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
+		 int count, int *success_count, domid_t domid)
+{
+	BUG();
+}
+
+static inline int
+HYPERVISOR_multicall(void *call_list, int nr_calls)
+{
+	BUG();
+}
 #endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index f4a6fca..ab4f81c 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -40,6 +40,7 @@
 
 #include <net/tcp.h>
 
+#include <xen/xen.h>
 #include <xen/events.h>
 #include <xen/interface/memory.h>
 
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 3089990..bf4ba2b 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -43,6 +43,7 @@
 #include <linux/slab.h>
 #include <net/ip.h>
 
+#include <asm/xen/page.h>
 #include <xen/xen.h>
 #include <xen/xenbus.h>
 #include <xen/events.h>
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:15 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:15 +0100
Subject: [PATCH v3 23/25] xen: missing includes
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-23-git-send-email-stefano.stabellini@eu.citrix.com>

Note: this patch should be already in Konrad's tree, it is here just for
convenience.

Changes in v3:
- add missing pvclock-abi.h include to ia64 header files.

Changes in v2:
- remove pvclock hack;
- remove include linux/types.h from xen/interface/xen.h.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/ia64/include/asm/xen/interface.h      |    2 ++
 arch/x86/include/asm/xen/interface.h       |    2 ++
 drivers/tty/hvc/hvc_xen.c                  |    2 ++
 drivers/xen/grant-table.c                  |    1 +
 drivers/xen/xenbus/xenbus_probe_frontend.c |    1 +
 include/xen/interface/xen.h                |    1 -
 include/xen/privcmd.h                      |    1 +
 7 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index 7c83445..e88c5de 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -269,6 +269,8 @@ typedef struct xen_callback xen_callback_t;
 
 #endif /* !__ASSEMBLY__ */
 
+#include <asm/pvclock-abi.h>
+
 /* Size of the shared_info area (this is not related to page size).  */
 #define XSI_SHIFT			14
 #define XSI_SIZE			(1 << XSI_SHIFT)
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index 25cc8df..28fc621 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -127,6 +127,8 @@ struct arch_shared_info {
 #include "interface_64.h"
 #endif
 
+#include <asm/pvclock-abi.h>
+
 #ifndef __ASSEMBLY__
 /*
  * The following is all CPU context. Note that the fpu_ctxt block is filled
diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c
index 944eaeb..dc07f56 100644
--- a/drivers/tty/hvc/hvc_xen.c
+++ b/drivers/tty/hvc/hvc_xen.c
@@ -21,6 +21,7 @@
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/list.h>
@@ -35,6 +36,7 @@
 #include <xen/page.h>
 #include <xen/events.h>
 #include <xen/interface/io/console.h>
+#include <xen/interface/sched.h>
 #include <xen/hvc-console.h>
 #include <xen/xenbus.h>
 
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
index 0bfc1ef..1d0d95e 100644
--- a/drivers/xen/grant-table.c
+++ b/drivers/xen/grant-table.c
@@ -47,6 +47,7 @@
 #include <xen/interface/memory.h>
 #include <xen/hvc-console.h>
 #include <asm/xen/hypercall.h>
+#include <asm/xen/interface.h>
 
 #include <asm/pgtable.h>
 #include <asm/sync_bitops.h>
diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
index a31b54d..3159a37 100644
--- a/drivers/xen/xenbus/xenbus_probe_frontend.c
+++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
@@ -21,6 +21,7 @@
 #include <xen/xenbus.h>
 #include <xen/events.h>
 #include <xen/page.h>
+#include <xen/xen.h>
 
 #include <xen/platform_pci.h>
 
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index f6b8965..42834a3 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -10,7 +10,6 @@
 #define __XEN_PUBLIC_XEN_H__
 
 #include <asm/xen/interface.h>
-#include <asm/pvclock-abi.h>
 
 /*
  * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
diff --git a/include/xen/privcmd.h b/include/xen/privcmd.h
index 59f1bd8..45c1aa1 100644
--- a/include/xen/privcmd.h
+++ b/include/xen/privcmd.h
@@ -35,6 +35,7 @@
 
 #include <linux/types.h>
 #include <linux/compiler.h>
+#include <xen/interface/xen.h>
 
 struct privcmd_hypercall {
 	__u64 op;
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:16 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:16 +0100
Subject: [PATCH v3 24/25] xen: update xen_add_to_physmap interface
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-24-git-send-email-stefano.stabellini@eu.citrix.com>

Update struct xen_add_to_physmap to be in sync with Xen's version of the
structure.
The size field was introduced by:

changeset:   24164:707d27fe03e7
user:        Jean Guyader <jean.guyader at eu.citrix.com>
date:        Fri Nov 18 13:42:08 2011 +0000
summary:     mm: New XENMEM space, XENMAPSPACE_gmfn_range

According to the comment:

"This new field .size is located in the 16 bits padding between .domid
and .space in struct xen_add_to_physmap to stay compatible with older
versions."

Note: this patch should be already in Konrad's tree, it is here just for
convenience.

Changes in v2:

- remove erroneous comment in the commit message.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 include/xen/interface/memory.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index b5c3098..b66d04c 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -163,6 +163,9 @@ struct xen_add_to_physmap {
     /* Which domain to change the mapping for. */
     domid_t domid;
 
+    /* Number of pages to go through for gmfn_range */
+    uint16_t    size;
+
     /* Source mapping space. */
 #define XENMAPSPACE_shared_info 0 /* shared info page */
 #define XENMAPSPACE_grant_table 1 /* grant table page */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:08 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:08 +0100
Subject: [PATCH v3 16/25] xen: clear IRQ_NOAUTOEN and IRQ_NOREQUEST
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-16-git-send-email-stefano.stabellini@eu.citrix.com>

Reset the IRQ_NOAUTOEN and IRQ_NOREQUEST flags that are enabled by
default on ARM. If IRQ_NOAUTOEN is set, __setup_irq doesn't call
irq_startup, that is responsible for calling irq_unmask at startup time.
As a result event channels remain masked.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 drivers/xen/events.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index c3516d3..9b506b2 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -839,6 +839,7 @@ int bind_evtchn_to_irq(unsigned int evtchn)
 		struct irq_info *info = info_for_irq(irq);
 		WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
 	}
+	irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
 
 out:
 	mutex_unlock(&irq_mapping_update_lock);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:06 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:06 +0100
Subject: [PATCH v3 14/25] xen/arm: initialize grant_table on ARM
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-14-git-send-email-stefano.stabellini@eu.citrix.com>

Initialize the grant table mapping at the address specified at index 0
in the DT under the /xen node.
After the grant table is initialized, call xenbus_probe (if not dom0).

Changes in v2:

- introduce GRANT_TABLE_PHYSADDR;
- remove unneeded initialization of boot_max_nr_grant_frames.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/xen/enlighten.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index e529662..2e65e8d 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,8 +1,12 @@
 #include <xen/xen.h>
+#include <xen/grant_table.h>
+#include <xen/hvm.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/memory.h>
+#include <xen/interface/hvm/params.h>
 #include <xen/features.h>
 #include <xen/platform_pci.h>
+#include <xen/xenbus.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include <linux/module.h>
@@ -42,6 +46,7 @@ EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
  * see Documentation/devicetree/bindings/arm/xen.txt for the
  * documentation of the Xen Device Tree format.
  */
+#define GRANT_TABLE_PHYSADDR 0
 static int __init xen_guest_init(void)
 {
 	struct xen_add_to_physmap xatp;
@@ -51,6 +56,7 @@ static int __init xen_guest_init(void)
 	const char *s = NULL;
 	const char *version = NULL;
 	const char *xen_prefix = "xen,xen-";
+	struct resource res;
 
 	node = of_find_compatible_node(NULL, NULL, "xen,xen");
 	if (!node) {
@@ -65,6 +71,9 @@ static int __init xen_guest_init(void)
 		pr_debug("Xen version not found\n");
 		return 0;
 	}
+	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
+		return 0;
+	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
 	xen_domain_type = XEN_HVM_DOMAIN;
 
 	xen_setup_features();
@@ -98,6 +107,11 @@ static int __init xen_guest_init(void)
 	 * is required to use VCPUOP_register_vcpu_info to place vcpu info
 	 * for secondary CPUs as they are brought up. */
 	per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
+
+	gnttab_init();
+	if (!xen_initial_domain())
+		xenbus_probe(NULL);
+
 	return 0;
 }
 core_initcall(xen_guest_init);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:09 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:09 +0100
Subject: [PATCH v3 17/25] xen/arm: implement alloc/free_xenballooned_pages
 with alloc_pages/kfree
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-17-git-send-email-stefano.stabellini@eu.citrix.com>

Only until we get the balloon driver to work.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/xen/enlighten.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 14af29d..3348d90 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -148,3 +148,21 @@ static int __init xen_init_events(void)
 	return 0;
 }
 postcore_initcall(xen_init_events);
+
+/* XXX: only until balloon is properly working */
+int alloc_xenballooned_pages(int nr_pages, struct page **pages, bool highmem)
+{
+	*pages = alloc_pages(highmem ? GFP_HIGHUSER : GFP_KERNEL,
+			get_order(nr_pages));
+	if (*pages == NULL)
+		return -ENOMEM;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(alloc_xenballooned_pages);
+
+void free_xenballooned_pages(int nr_pages, struct page **pages)
+{
+	kfree(*pages);
+	*pages = NULL;
+}
+EXPORT_SYMBOL_GPL(free_xenballooned_pages);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:14 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:14 +0100
Subject: [PATCH v3 22/25] xen/arm: use the __HVC macro
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-22-git-send-email-stefano.stabellini@eu.citrix.com>

Note: This patch depends on Dave Martin's patch series "ARM: opcodes:
Facilitate custom opcode injection".

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/xen/hypercall.S |   14 +++++---------
 1 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
index 074f5ed..71f7239 100644
--- a/arch/arm/xen/hypercall.S
+++ b/arch/arm/xen/hypercall.S
@@ -48,20 +48,16 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/opcodes-virt.h>
 #include <xen/interface/xen.h>
 
 
-/* HVC 0xEA1 */
-#ifdef CONFIG_THUMB2_KERNEL
-#define xen_hvc .word 0xf7e08ea1
-#else
-#define xen_hvc .word 0xe140ea71
-#endif
+#define XEN_IMM 0xEA1
 
 #define HYPERCALL_SIMPLE(hypercall)		\
 ENTRY(HYPERVISOR_##hypercall)			\
 	mov r12, #__HYPERVISOR_##hypercall;	\
-	xen_hvc;							\
+	__HVC(XEN_IMM);						\
 	mov pc, lr;							\
 ENDPROC(HYPERVISOR_##hypercall)
 
@@ -76,7 +72,7 @@ ENTRY(HYPERVISOR_##hypercall)			\
 	stmdb sp!, {r4}						\
 	ldr r4, [sp, #4]					\
 	mov r12, #__HYPERVISOR_##hypercall;	\
-	xen_hvc								\
+	__HVC(XEN_IMM);						\
 	ldm sp!, {r4}						\
 	mov pc, lr							\
 ENDPROC(HYPERVISOR_##hypercall)
@@ -100,7 +96,7 @@ ENTRY(privcmd_call)
 	mov r2, r3
 	ldr r3, [sp, #8]
 	ldr r4, [sp, #4]
-	xen_hvc
+	__HVC(XEN_IMM)
 	ldm sp!, {r4}
 	mov pc, lr
 ENDPROC(privcmd_call);
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:10 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:10 +0100
Subject: [PATCH v3 18/25] xen: allow privcmd for HVM guests
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-18-git-send-email-stefano.stabellini@eu.citrix.com>

This patch removes the "return -ENOSYS" for auto_translated_physmap
guests from privcmd_mmap, thus it allows ARM guests to issue privcmd
mmap calls. However privcmd mmap calls are still going to fail for HVM
and hybrid guests on x86 because the xen_remap_domain_mfn_range
implementation is currently PV only.

Changes in v2:

- better commit message;
- return -EINVAL from xen_remap_domain_mfn_range if
  auto_translated_physmap.


Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/x86/xen/mmu.c    |    3 +++
 drivers/xen/privcmd.c |    4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 3a73785..885a223 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -2310,6 +2310,9 @@ int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 	unsigned long range;
 	int err = 0;
 
+	if (xen_feature(XENFEAT_auto_translated_physmap))
+		return -EINVAL;
+
 	prot = __pgprot(pgprot_val(prot) | _PAGE_IOMAP);
 
 	BUG_ON(!((vma->vm_flags & (VM_PFNMAP | VM_RESERVED | VM_IO)) ==
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index ccee0f1..85226cb 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -380,10 +380,6 @@ static struct vm_operations_struct privcmd_vm_ops = {
 
 static int privcmd_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	/* Unsupported for auto-translate guests. */
-	if (xen_feature(XENFEAT_auto_translated_physmap))
-		return -ENOSYS;
-
 	/* DONTCOPY is essential for Xen because copy_page_range doesn't know
 	 * how to recreate these mappings */
 	vma->vm_flags |= VM_RESERVED | VM_IO | VM_DONTCOPY | VM_PFNMAP;
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:11 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:11 +0100
Subject: [PATCH v3 19/25] xen/arm: compile blkfront and blkback
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-19-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 drivers/block/xen-blkback/blkback.c  |    1 +
 include/xen/interface/io/protocols.h |    3 +++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
index 73f196c..63dd5b9 100644
--- a/drivers/block/xen-blkback/blkback.c
+++ b/drivers/block/xen-blkback/blkback.c
@@ -42,6 +42,7 @@
 
 #include <xen/events.h>
 #include <xen/page.h>
+#include <xen/xen.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
 #include "common.h"
diff --git a/include/xen/interface/io/protocols.h b/include/xen/interface/io/protocols.h
index 01fc8ae..0eafaf2 100644
--- a/include/xen/interface/io/protocols.h
+++ b/include/xen/interface/io/protocols.h
@@ -5,6 +5,7 @@
 #define XEN_IO_PROTO_ABI_X86_64     "x86_64-abi"
 #define XEN_IO_PROTO_ABI_IA64       "ia64-abi"
 #define XEN_IO_PROTO_ABI_POWERPC64  "powerpc64-abi"
+#define XEN_IO_PROTO_ABI_ARM        "arm-abi"
 
 #if defined(__i386__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_X86_32
@@ -14,6 +15,8 @@
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_IA64
 #elif defined(__powerpc64__)
 # define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_POWERPC64
+#elif defined(__arm__)
+# define XEN_IO_PROTO_ABI_NATIVE XEN_IO_PROTO_ABI_ARM
 #else
 # error arch fixup needed here
 #endif
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:13 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:13 +0100
Subject: [PATCH v3 21/25] arm/v2m: initialize arch_timers even if v2m_timer is
 not present
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-21-git-send-email-stefano.stabellini@eu.citrix.com>

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
CC: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-vexpress/v2m.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26ad..dee1451 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -637,16 +637,17 @@ static void __init v2m_dt_timer_init(void)
 	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
 	v2m_sysctl_init(of_iomap(node, 0));
 
-	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
-	if (WARN_ON(err))
-		return;
-	node = of_find_node_by_path(path);
-	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
 	if (arch_timer_of_register() != 0)
 		twd_local_timer_of_register();
 
 	if (arch_timer_sched_clock_init() != 0)
 		versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
 }
 
 static struct sys_timer v2m_dt_timer = {
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:07 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:07 +0100
Subject: [PATCH v3 15/25] xen/arm: receive Xen events on ARM
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-15-git-send-email-stefano.stabellini@eu.citrix.com>

Compile events.c on ARM.
Parse, map and enable the IRQ to get event notifications from the device
tree (node "/xen").

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
---
 arch/arm/include/asm/xen/events.h |   18 ++++++++++++++++++
 arch/arm/xen/enlighten.c          |   33 +++++++++++++++++++++++++++++++++
 arch/x86/xen/enlighten.c          |    1 +
 arch/x86/xen/irq.c                |    1 +
 arch/x86/xen/xen-ops.h            |    1 -
 drivers/xen/events.c              |   17 ++++++++++++++---
 include/xen/events.h              |    2 ++
 7 files changed, 69 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/include/asm/xen/events.h

diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h
new file mode 100644
index 0000000..94b4e90
--- /dev/null
+++ b/arch/arm/include/asm/xen/events.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_XEN_EVENTS_H
+#define _ASM_ARM_XEN_EVENTS_H
+
+#include <asm/ptrace.h>
+
+enum ipi_vector {
+	XEN_PLACEHOLDER_VECTOR,
+
+	/* Xen IPIs go here */
+	XEN_NR_IPIS,
+};
+
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+	return raw_irqs_disabled_flags(regs->ARM_cpsr);
+}
+
+#endif /* _ASM_ARM_XEN_EVENTS_H */
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 2e65e8d..14af29d 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,4 +1,5 @@
 #include <xen/xen.h>
+#include <xen/events.h>
 #include <xen/grant_table.h>
 #include <xen/hvm.h>
 #include <xen/interface/xen.h>
@@ -9,6 +10,8 @@
 #include <xen/xenbus.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
@@ -33,6 +36,8 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
 int xen_platform_pci_unplug = XEN_UNPLUG_ALL;
 EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
 
+static __read_mostly int xen_events_irq = -1;
+
 int xen_remap_domain_mfn_range(struct vm_area_struct *vma,
 			       unsigned long addr,
 			       unsigned long mfn, int nr,
@@ -74,6 +79,9 @@ static int __init xen_guest_init(void)
 	if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
 		return 0;
 	xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
+	xen_events_irq = irq_of_parse_and_map(node, 0);
+	pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
+			version, xen_events_irq, xen_hvm_resume_frames);
 	xen_domain_type = XEN_HVM_DOMAIN;
 
 	xen_setup_features();
@@ -115,3 +123,28 @@ static int __init xen_guest_init(void)
 	return 0;
 }
 core_initcall(xen_guest_init);
+
+static irqreturn_t xen_arm_callback(int irq, void *arg)
+{
+	xen_hvm_evtchn_do_upcall();
+	return IRQ_HANDLED;
+}
+
+static int __init xen_init_events(void)
+{
+	if (!xen_domain() || xen_events_irq < 0)
+		return -ENODEV;
+
+	xen_init_IRQ();
+
+	if (request_percpu_irq(xen_events_irq, xen_arm_callback,
+			"events", xen_vcpu)) {
+		pr_err("Error requesting IRQ %d\n", xen_events_irq);
+		return -EINVAL;
+	}
+
+	enable_percpu_irq(xen_events_irq, 0);
+
+	return 0;
+}
+postcore_initcall(xen_init_events);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index ff962d4..9f8b0ef 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -33,6 +33,7 @@
 #include <linux/memblock.h>
 
 #include <xen/xen.h>
+#include <xen/events.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 1573376..01a4dc0 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -5,6 +5,7 @@
 #include <xen/interface/xen.h>
 #include <xen/interface/sched.h>
 #include <xen/interface/vcpu.h>
+#include <xen/events.h>
 
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 202d4c1..2368295 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -35,7 +35,6 @@ void xen_set_pat(u64);
 
 char * __init xen_memory_setup(void);
 void __init xen_arch_setup(void);
-void __init xen_init_IRQ(void);
 void xen_enable_sysenter(void);
 void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 7da65d3..c3516d3 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -31,14 +31,16 @@
 #include <linux/irqnr.h>
 #include <linux/pci.h>
 
+#ifdef CONFIG_X86
 #include <asm/desc.h>
 #include <asm/ptrace.h>
 #include <asm/irq.h>
 #include <asm/idle.h>
 #include <asm/io_apic.h>
-#include <asm/sync_bitops.h>
 #include <asm/xen/page.h>
 #include <asm/xen/pci.h>
+#endif
+#include <asm/sync_bitops.h>
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
 
@@ -50,6 +52,9 @@
 #include <xen/interface/event_channel.h>
 #include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/hvm/params.h>
+#include <xen/interface/physdev.h>
+#include <xen/interface/sched.h>
+#include <asm/hw_irq.h>
 
 /*
  * This lock protects updates to the following mapping and reference-count
@@ -1377,7 +1382,9 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
 {
 	struct pt_regs *old_regs = set_irq_regs(regs);
 
+#ifdef CONFIG_X86
 	exit_idle();
+#endif
 	irq_enter();
 
 	__xen_evtchn_do_upcall();
@@ -1786,9 +1793,9 @@ void xen_callback_vector(void)
 void xen_callback_vector(void) {}
 #endif
 
-void __init xen_init_IRQ(void)
+void xen_init_IRQ(void)
 {
-	int i, rc;
+	int i;
 
 	evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
 				    GFP_KERNEL);
@@ -1804,6 +1811,7 @@ void __init xen_init_IRQ(void)
 
 	pirq_needs_eoi = pirq_needs_eoi_flag;
 
+#ifdef CONFIG_X86
 	if (xen_hvm_domain()) {
 		xen_callback_vector();
 		native_init_IRQ();
@@ -1811,6 +1819,7 @@ void __init xen_init_IRQ(void)
 		 * __acpi_register_gsi can point at the right function */
 		pci_xen_hvm_init();
 	} else {
+		int rc;
 		struct physdev_pirq_eoi_gmfn eoi_gmfn;
 
 		irq_ctx_init(smp_processor_id());
@@ -1826,4 +1835,6 @@ void __init xen_init_IRQ(void)
 		} else
 			pirq_needs_eoi = pirq_check_eoi_map;
 	}
+#endif
 }
+EXPORT_SYMBOL_GPL(xen_init_IRQ);
diff --git a/include/xen/events.h b/include/xen/events.h
index 04399b2..c6bfe01 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -109,4 +109,6 @@ int xen_irq_from_gsi(unsigned gsi);
 /* Determine whether to ignore this IRQ if it is passed to a guest. */
 int xen_test_irq_shared(int irq);
 
+/* initialize Xen IRQ subsystem */
+void xen_init_IRQ(void);
 #endif	/* _XEN_EVENTS_H */
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:04 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:04 +0100
Subject: [PATCH v3 12/25] xen/arm: introduce CONFIG_XEN on ARM
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-12-git-send-email-stefano.stabellini@eu.citrix.com>

Changes in v2:

- mark Xen guest support on ARM as EXPERIMENTAL.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/Kconfig |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c..f14664b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1855,6 +1855,16 @@ config DEPRECATED_PARAM_STRUCT
 	  This was deprecated in 2001 and announced to live on for 5 years.
 	  Some old boot loaders still use this way.
 
+config XEN_DOM0
+	def_bool y
+
+config XEN
+	bool "Xen guest support on ARM (EXPERIMENTAL)"
+	depends on EXPERIMENTAL && ARM && OF
+	select XEN_DOM0
+	help
+	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
+
 endmenu
 
 menu "Boot options"
-- 
1.7.2.5



From stefano.stabellini at eu.citrix.com  Thu Aug 16 11:36:05 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 16 Aug 2012 16:36:05 +0100
Subject: [PATCH v3 13/25] xen/arm: get privilege status
In-Reply-To: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
Message-ID: <1345131377-14713-13-git-send-email-stefano.stabellini@eu.citrix.com>

Use Xen features to figure out if we are privileged.

XENFEAT_dom0 was introduced by 23735 in xen-unstable.hg.

Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
---
 arch/arm/xen/enlighten.c         |    7 +++++++
 include/xen/interface/features.h |    3 +++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 78ea1f7..e529662 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -1,6 +1,7 @@
 #include <xen/xen.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/memory.h>
+#include <xen/features.h>
 #include <xen/platform_pci.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/xen/hypercall.h>
@@ -66,6 +67,12 @@ static int __init xen_guest_init(void)
 	}
 	xen_domain_type = XEN_HVM_DOMAIN;
 
+	xen_setup_features();
+	if (xen_feature(XENFEAT_dom0))
+		xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
+	else
+		xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
+
 	if (!shared_info_page)
 		shared_info_page = (struct shared_info *)
 			get_zeroed_page(GFP_KERNEL);
diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h
index b6ca39a..131a6cc 100644
--- a/include/xen/interface/features.h
+++ b/include/xen/interface/features.h
@@ -50,6 +50,9 @@
 /* x86: pirq can be used by HVM guests */
 #define XENFEAT_hvm_pirqs           10
 
+/* operation as Dom0 is supported */
+#define XENFEAT_dom0                      11
+
 #define XENFEAT_NR_SUBMAPS 1
 
 #endif /* __XEN_PUBLIC_FEATURES_H__ */
-- 
1.7.2.5



From andi at firstfloor.org  Thu Aug 16 12:20:52 2012
From: andi at firstfloor.org (Andi Kleen)
Date: Thu, 16 Aug 2012 18:20:52 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <502D100D.2030609@pobox.com>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net> <502C92C3.7090701@oberhumer.com>
 <502D100D.2030609@pobox.com>
Message-ID: <20120816162051.GK11413@one.firstfloor.org>

> If you think a little bit, I bet you could come up with a solution that 
> operates at cacheline-aligned granularity, something that would be _even 
> faster_ than simply fixing the code to do aligned accesses.

Cache aligned compression is unlikely to compress anything at all.
Compression algorithms are usually by definition unaligned.

-Andi


From ian.molton at codethink.co.uk  Thu Aug 16 12:30:22 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Thu, 16 Aug 2012 17:30:22 +0100
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <5028D040.60604@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <201208091143.32972.arnd@arndb.de> <5023D577.8090001@codethink.co.uk>
 <201208101049.57586.arnd@arndb.de> <5028D040.60604@codethink.co.uk>
Message-ID: <502D201E.9030304@codethink.co.uk>

Ping :)

Can we get some consensus on the right approach here? I'm loathe to code
this if its going to be rejected.

I'd prefer the driver to be properly split so we dont have the MDIO
driver mapping the ethernet drivers address spaces, but if thats not
going to be merged, I'm not feeling like doing the work for nothing.

If the driver is to use the overlapping-address mapped-by-the-mdio
scheme, then so be it, but I could do with knowing.

Another point against the latter scheme is that the MDIO driver could
sensibly be used (the block is identical) on the ArmadaXP, which has 4
ethernet blocks rather than two, yet grouped in two pairs with a
discontiguous address range.

I'd like to get this moved along as soon as possible though.

-Ian


From jgarzik at pobox.com  Thu Aug 16 12:48:49 2012
From: jgarzik at pobox.com (Jeff Garzik)
Date: Thu, 16 Aug 2012 12:48:49 -0400
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120816162051.GK11413@one.firstfloor.org>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net> <502C92C3.7090701@oberhumer.com>
 <502D100D.2030609@pobox.com> <20120816162051.GK11413@one.firstfloor.org>
Message-ID: <502D2471.407@pobox.com>

On 08/16/2012 12:20 PM, Andi Kleen wrote:
>> If you think a little bit, I bet you could come up with a solution that
>> operates at cacheline-aligned granularity, something that would be _even
>> faster_ than simply fixing the code to do aligned accesses.
>
> Cache aligned compression is unlikely to compress anything at all.
> Compression algorithms are usually by definition unaligned.

Sure it's a bitstream, but that does not imply the impossibility of 
reading data in in an word-aligned manner.

Maybe cache-aligned is ambitious, because of resultant code bloat, but 
machine-int-aligned is doable and reasonable.

	Jeff






From jon-hunter at ti.com  Thu Aug 16 12:57:42 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 16 Aug 2012 11:57:42 -0500
Subject: [RFC RESEND 2/4] ARM: OMAP3: Dynamically disable secure timer
 nodes for secure devices
In-Reply-To: <502B6838.9080907@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
 <502B6838.9080907@ti.com>
Message-ID: <502D2686.4090107@ti.com>


On 08/15/2012 04:13 AM, Vaibhav Hiremath wrote:
> 
> 
> On 7/14/2012 3:56 AM, Jon Hunter wrote:
>> OMAP3 devices may or may not have security features enabled. Security enabled
>> devices are known as high-secure (HS) and devices without security are known as
>> general purpose (GP).
>>
>> For OMAP3 devices there are 12 general purpose timers available. On secure
>> devices the 12th timer is reserved for secure usage and so cannot be used by
>> the kernel, where as for a GP device it is available. We can detect the OMAP
>> device type, secure or GP, at runtime via an on-chip register. Today, when not
>> using DT, we do not register the 12th timer as a linux device if the device is
>> secure.
>>
>> When using device tree, device tree is going to register all the timer devices
>> it finds in the device tree blob. To prevent device tree from registering 12th
>> timer on a secure OMAP3 device we can add a status property to the timer
>> binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
>> device has a property "ti,timer-secure" to indicate that it will not be
>> available on a secure device and so for secure OMAP3 devices, we search for
>> timers with this property and then disable them. Using the prom_add_property()
>> function to dynamically add a property was a recommended approach suggested by
>> Rob Herring [1].
>>
>> I have tested this on an OMAP3 GP device and faking it to pretend to be a
>> secure device to ensure that any timers marked with "ti,timer-secure" are not
>> registered on boot. I have also made sure that all timers are registered as
>> expected on a GP device by default.
>>
>> [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
>>
>> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
>> ---
>>  arch/arm/mach-omap2/board-generic.c |    1 +
>>  arch/arm/mach-omap2/common.h        |    1 +
>>  arch/arm/mach-omap2/timer.c         |   36 +++++++++++++++++++++++++++++++++++
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
>> index 6f93a20..20124d7 100644
>> --- a/arch/arm/mach-omap2/board-generic.c
>> +++ b/arch/arm/mach-omap2/board-generic.c
>> @@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>>  static void __init omap_generic_init(void)
>>  {
>>  	omap_sdrc_init(NULL, NULL);
>> +	omap_dmtimer_init();
>>  
>>  	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
>>  }
>> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
>> index 1f65b18..d6a4875 100644
>> --- a/arch/arm/mach-omap2/common.h
>> +++ b/arch/arm/mach-omap2/common.h
>> @@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>>  				      struct omap_sdrc_params *sdrc_cs1);
>>  struct omap2_hsmmc_info;
>>  extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
>> +extern void omap_dmtimer_init(void);
>>  
>>  #endif /* __ASSEMBLER__ */
>>  #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>> index 13d20c8..e3b9931 100644
>> --- a/arch/arm/mach-omap2/timer.c
>> +++ b/arch/arm/mach-omap2/timer.c
>> @@ -36,6 +36,7 @@
>>  #include <linux/clocksource.h>
>>  #include <linux/clockchips.h>
>>  #include <linux/slab.h>
>> +#include <linux/of.h>
>>  
>>  #include <asm/mach/time.h>
>>  #include <plat/dmtimer.h>
>> @@ -482,6 +483,41 @@ static int __init omap2_dm_timer_init(void)
>>  }
>>  arch_initcall(omap2_dm_timer_init);
>>  
>> +static struct property timer_disabled = {
>> +	.name = "status",
>> +	.length = sizeof("disabled"),
>> +	.value = "disabled",
>> +};
>> +
>> +static struct of_device_id omap3_timer_match[] __initdata = {
>> +	{ .compatible = "ti,omap3-timer", },
>> +	{ }
>> +};
>> +
>> +/**
>> + * omap_dmtimer_init - initialisation function when device tree is used
>> + *
>> + * For secure OMAP3 devices, timers with device type "timer-secure" cannot
>> + * be used by the kernel as they are reserved. Therefore, to prevent the
>> + * kernel registering these devices remove them dynamically from the device
>> + * tree on boot.
>> + */
>> +void __init omap_dmtimer_init(void)
>> +{
>> +	struct device_node *np;
>> +
>> +	if (!cpu_is_omap34xx())
>> +		return;
>> +
> 
> Sorry for responding so late, but why only omap34xx check here?
> Isn't this applicable to all omap & non-omap devices?

It is only applicable to omap3 devices as far as omap is concerned.

By non-omap, you are referring to the AMxxx stuff?

Do AMxxx devices even support security (ie. secure boot and have secure
peripherals)? If not then this will work for AMxxx devices too.

Let me know if the changelog is not clear why this is needed for an
omap3 device.

Jon




From matt at genesi-usa.com  Thu Aug 16 13:21:25 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 16 Aug 2012 12:21:25 -0500
Subject: imx6q restart is broken
In-Reply-To: <20120816023109.GH2258@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk> <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
 <20120816023109.GH2258@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bn1NxMU2Y7O4xQs25yDdBkkcdw+0sdzB3PYvB7vX7+z=A@mail.gmail.com>

On Wed, Aug 15, 2012 at 9:31 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 10:44:12PM +0100, Russell King - ARM Linux wrote:
>> On Wed, Aug 15, 2012 at 10:07:47AM -0500, Rob Herring wrote:
>> > I think I am seeing a similar problem on highbank with a v7 only build.
>> >
>> > >From what I've debugged, restart hangs for me on the L2x0 spinlock
>> > during a writel. Changing the writel to writel_relaxed in the restart
>> > hook fixes the problem. This skips barriers in the writel and for the
>> > spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
>> > should not be doing a dmb in my case on a v7 only build.
>>
>> Well, I had the idea of only doing a dmb() once every N loops, but I don't
>> think we can sensibly introduce such a change into the mainline kernel.
>> (How would cpu_relax() know it's being used in a loop?)
>>
>> Remember that the dmb() is in cpu_relax() as a work-around for the lack
>> of temporal flushing of pending stores, and is needed to make various bits
>> of the kernel work.
>>
> The cpu_relax() will do dmb() only #if __LINUX_ARM_ARCH__ == 6 ||
> defined(CONFIG_ARM_ERRATA_754327).  Otherwise, it's just a barrier()
> call.  I guess Rob's puzzle is since the cpu_relax on the stopped
> cores does not do dmb, why a wmb/mb call on the running cpu would hang
> it.
>
> One thing I note is that mb() will do a outer_sync() call.  Since the
> issue is around L2x0 operation, not sure if they are related ...
>
>> So at the moment, there is no solution for this - and as I've pointed out
>> it can be trivially exploited in userspace on the affected CPUs.  So
>> really a kernel work-around isn't going to sort it.
>
> So, Sascha, it seems we get another good reason to split
> imx_v6_v7_defconfig into imx_v6_defconfig and imx_v7_defconfig?
> I have seen Matt Sealey and Hui Wang suggested doing this already.

Only because Hui suggested it. I figured it would be better from the
standpoint of allowing
proper compiler-generated or more
efficient/architecture-revision-specific code to be
generated. It was mostly because I also have a side nit about
individual erratum being enabled,
in that by default in imx_v6_v7_defconfig they aren't; that's not nice
and it's true of other ARM
platforms too (Tegra notwithstanding). It's unlikely you'd want to run
your chip without these fixes
enabled, but in any kernel built from imx_v6_v7_defconfig it's likely
MX51, MX53 aren't going to
run particularly reliably.

There are a couple options to make it more likely to run with a
working configuration, namely
turning every single one on regardless, or alternatively every mach
defined (SOC_IMX51,
SOC_OMAP or so) or so depends on the errata necessary for correct
operation (just as
ARCH_TEGRA_2x_SOC does right now) so you can still whittle down the number of
compiled-in errata to the CPUs and cache controllers needed to boot
that particular kernel
on the particular boards you chose.

The vast majority are only done on cores that need it, but this
particular one, and a couple
others I noticed, will be enabled in the future on "v7-pure"
multi-platform configs if you just enable
Tegra support with the above solution (since it's not v6, but it is
affected by erratum 754327).

Is there any way to fix cpu_relax(), smp_mb() or whatever to
specifically fix that particular core
or particular A9 revision at runtime rather than having it be
compile-time if we're doing it every few loops,
per-cpu like Catalin suggested? I assume it's not dangerous to do so
(and would mean we don't
run into it on the systems it's not booted on, rather than running
into it by virtue of compiling it in).

I'm not suggesting it fixes the dmb issue Russell described
(especially the userspace part),
but it would mean the kernel won't be issuing them itself under any
circumstance when it
doesn't need to.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From swarren at wwwdotorg.org  Thu Aug 16 13:22:04 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 Aug 2012 11:22:04 -0600
Subject: [PATCH V3 0/6] ARM: tegra: add CPU hotplug support
In-Reply-To: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
References: <1345109513-21553-1-git-send-email-josephl@nvidia.com>
Message-ID: <502D2C3C.9090506@wwwdotorg.org>

On 08/16/2012 03:31 AM, Joseph Lo wrote:
> This patch set adds CPU hotplug support for Tegra20 and Tegra30 SoCs.
> 
> The first 3 patches make the CPU clock and reset control be a module and
> the abstraction APIs for TegraXX SoCs. And clean up some codes for later
> usage. Then add CPU hotplug support for Tegra20 and Tegra30.
> 
> Verified on Seaboard(Tegra20) and Cardhu(Tegra30)

Thanks, I applied patches 1-5 to for-3.7/cpu-hotplug, and squashed patch
6 into the patch in for-3.7/defconfig.


From js at sig21.net  Thu Aug 16 13:22:51 2012
From: js at sig21.net (Johannes Stezenbach)
Date: Thu, 16 Aug 2012 19:22:51 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <502D2471.407@pobox.com>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com> <502D100D.2030609@pobox.com>
 <20120816162051.GK11413@one.firstfloor.org>
 <502D2471.407@pobox.com>
Message-ID: <20120816172251.GA25640@sig21.net>

On Thu, Aug 16, 2012 at 12:48:49PM -0400, Jeff Garzik wrote:
> On 08/16/2012 12:20 PM, Andi Kleen wrote:
> >>If you think a little bit, I bet you could come up with a solution that
> >>operates at cacheline-aligned granularity, something that would be _even
> >>faster_ than simply fixing the code to do aligned accesses.
> >
> >Cache aligned compression is unlikely to compress anything at all.
> >Compression algorithms are usually by definition unaligned.
> 
> Sure it's a bitstream, but that does not imply the impossibility of
> reading data in in an word-aligned manner.
> 
> Maybe cache-aligned is ambitious, because of resultant code bloat,
> but machine-int-aligned is doable and reasonable.

Well, I for one would be content if the old and new lzo versions
could be merged based on CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS.

(Assuming that the slowdown on ARM is due to unaligned access,
since the old version also uses get/put_unaligned, is the new
version actually using more unaligned accesses?)


Johannes


From rm at romanrm.ru  Thu Aug 16 13:25:49 2012
From: rm at romanrm.ru (Roman Mamedov)
Date: Thu, 16 Aug 2012 23:25:49 +0600
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120816150647.GA22010@sig21.net>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com> <20120816150647.GA22010@sig21.net>
Message-ID: <20120816232549.4d14a6aa@natsu>

On Thu, 16 Aug 2012 17:06:47 +0200
Johannes Stezenbach <js at sig21.net> wrote:

> Well, ~2x speedup on x86 is certainly a good achievement, but there
> are more ARM based devices than there are PCs, and I guess many
> embedded devices use lzo compressed kernels and file systems
> while I'm not convinced many PCs rely on lzo in the kernel.

Keep in mind that a major user of LZO is the BTRFS filesystem, and I believe it
is used much more often on larger machines than on ARM, in fact it had problems
operating on ARM at all, until quite recently.

> I know everyone's either busy or on vacation, but it would
> be so cool if someone could test on a more modern ARM core,
> with the userspace test code I posted it should be easy to do.

I have locked the Allwinner A10 CPU in my Mele A2000 to 60 MHz using cpufreq-set,
and ran your test. rnd.lzo is a 9 MB file from /dev/urandom compressed with lzo.
There doesn't seem to be a significant difference between all three variants.

# time for i in {1..20}; do old/unlzop < rnd.lzo >/dev/null ; done

real	0m11.353s
user	0m3.060s
sys	0m8.170s
# time for i in {1..20}; do new/unlzop < rnd.lzo >/dev/null ; done

real	0m11.416s
user	0m3.030s
sys	0m8.200s
# time for i in {1..20}; do test/unlzop < rnd.lzo >/dev/null ; done

real	0m11.310s
user	0m3.100s
sys	0m8.150s

-- 
With respect,
Roman

~~~~~~~~~~~~~~~~~~~~~~~~~~~
"Stallman had a printer,
with code he could not see.
So he began to tinker,
and set the software free."
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From will.deacon at arm.com  Thu Aug 16 13:37:07 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 16 Aug 2012 18:37:07 +0100
Subject: [PATCH] ARM: mm: only flush both pmd entries for classic MMU
Message-ID: <1345138627-8140-1-git-send-email-will.deacon@arm.com>

LPAE does not use two pmd entries for a pte, so the additional tlb
flushing is not required.

Cc: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/tlb.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 314d466..7dce8a6 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -199,6 +199,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 {
 	pgtable_page_dtor(pte);
 
+#ifdef CONFIG_ARM_LPAE
+	tlb_add_flush(tlb, addr)
+#else
 	/*
 	 * With the classic ARM MMU, a pte page has two corresponding pmd
 	 * entries, each covering 1MB.
@@ -206,6 +209,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 	addr &= PMD_MASK;
 	tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
 	tlb_add_flush(tlb, addr + SZ_1M);
+#endif
 
 	tlb_remove_page(tlb, pte);
 }
-- 
1.7.4.1



From plagnioj at jcrosoft.com  Thu Aug 16 13:38:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 16 Aug 2012 19:38:44 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <CACQ1gAhWdwrXEkicy4ij=rukzS-v98bZRr433Qq5M_Dan5JAog@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>
 <CACQ1gAhWdwrXEkicy4ij=rukzS-v98bZRr433Qq5M_Dan5JAog@mail.gmail.com>
Message-ID: <20120816173844.GC7439@game.jcrosoft.org>

On 17:19 Thu 16 Aug     , Richard Genoud wrote:
> 2012/8/15 Linus Walleij <linus.walleij at linaro.org>:
> > On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
> > <plagnioj at jcrosoft.com> wrote:
> >
> >> Cc: Linus Walleij <linus.walleij at linaro.org>
> >> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > (...)
> >> +                               nand {
> >> +                                       pinctrl_nand: nand-0 {
> >> +                                               atmel,pins =
> >> +                                                       <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
> >> +                                                        2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
> >> +                                       };
> >> +                               };
> >
> > Again magic hex I don't understand so skipping this patch -> Nicolas.
> 
> Maybe it will be more readable if we use something like :
> atmel,pull-up;
> atmel,multidrive;
> atmel,mux="GPIO"
> atmel,mux="A"
> ...
> just my 2 cents...
no too much data and too much node as you will need a node per pin which we
tyr to avoid

Best Regards,
J.


From matt at genesi-usa.com  Thu Aug 16 13:39:09 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 16 Aug 2012 12:39:09 -0500
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120816034506.GI2258@S2101-09.ap.freescale.net>
References: <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120815153107.GG2258@S2101-09.ap.freescale.net>
 <CAKGA1bkNEJbQgwcdZs8PozCgVyOfUE=bDCGkRkKV3VMfbvRMgw@mail.gmail.com>
 <20120816034506.GI2258@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bncgxP9WX=1K4wOC6ixyjwqLg4-FkUFTOaGgkW5+OOciw@mail.gmail.com>

On Wed, Aug 15, 2012 at 10:45 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 11:49:01AM -0500, Matt Sealey wrote:
>> > Rather than betting how DTC will implement macro, we'd better make the
>> > the safest assumption - it will not support that syntax.
>>
>> It won't.
>
> There were a lot of pushing on macro support for DTC.  Though it's
> going to be very slow, I guess someday we will have it at least for
> those simple and straight-forward syntax.
>
> But right, we shouldn't make any assumption on that.

I'm not sure you'd want a "programmable" device tree that expanded itself out
using macros. Just imagine what one tiny mistake in syntax could do - stop a
board from booting, for example.

You never ran into this on real OF, you never needed it, why would precompiled
DTs need it?

>> iomuxc at 0x73f08000 {
>>   fsl,iomux-pins = <mux value ctrl value ipp value
>> /* MX53_PIN_SD4_CMD__SD4_CMD */
>>                             mux value ctrl value ipp value
>>        /* etc. */
>>                             ...>;
>
> I do not see problem with this approach either.  But, this is nothing
> IMX specific.  Essentially, this becomes a common binding for
> configuring a pin with arbitrary number of register/value pairs.

And indeed, I don't see how this could possibly be a bad thing when
multiple boards can share such a binding and ease device tree
generation by making it a task of "cross reference the manual" or
"read the automated tool output and copy it to the device tree". So
the name changes to something non-fsl-specific or something and all
the boards that support it this way can enable it this way, job done,
common binding for multiple systems?

Side nit: how do you propose in the device tree to enable certain bits
in certain IOMUXC registers on MX6 or so?

The current solution where pinctrl holds IOMUXC to ransom (it ioremaps
the register set until _remove) is fine for now, but what if I want to
change my ENET_CLK_CTL or MIPI_IPU1_MUX or USB_OTG_ID or OCRAM
pipeline control bits in IOMUXC_GPRn for correct board operation? Is
this a bootloader responsibility or device tree? It seems odd to make
pad mux and control a device tree job, but internal path or unit setup
a bootloader job.

If we're doing this to configure the correct internal paths in the
SoC, the "correct" place might be in the ethernet@ node, or ipu-csi@
node as they define the operation and paths of these units, but they
would be better served to be defined at the pinctrl level and not at
the unit, since pinctrl "owns" IOMUXC. But having iomuxc at foo contain a
lot of very strange internal path definitions seems too odd and
cluttered.

In this case, pinctrl-imx implementation is too generic in claiming
this entire unit for the purpose. Probably what needs to be done is
fsl,imx6q-iomuxc gets claimed by an MFD which allows setting these
feature bits, and pinctrl simply depends on it to implement a pinctrl@
node underneath it (like regulators are done now).

As for requiring drivers to fetch and use pinctrl data without
possibility of dummies to allow it to "fail gracefully", I would say
pinctrl in i.MX drivers at least should not be a requirement - by all
means, search for the pin definitions, instruct pinctrl to perform
these operations, but if it does not find a compatible property..
carry on regardless, maybe with a warning that you MUST have trusted
your bootloader. Or define a linux,pinctrl-already-done property (this
would be useful for MX51 uart1 which is muxed to ALT0 by default, so
pinctrl needn't bother doing anything - it was always there and always
correctly configured from mask rom time up to Linux anyway..) and as
such we can omit the warning and just carry on regardless.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From andi at firstfloor.org  Thu Aug 16 13:52:34 2012
From: andi at firstfloor.org (Andi Kleen)
Date: Thu, 16 Aug 2012 19:52:34 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120816232549.4d14a6aa@natsu>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net> <502C92C3.7090701@oberhumer.com>
 <20120816150647.GA22010@sig21.net> <20120816232549.4d14a6aa@natsu>
Message-ID: <20120816175234.GL11413@one.firstfloor.org>

> I have locked the Allwinner A10 CPU in my Mele A2000 to 60 MHz using cpufreq-set,
> and ran your test. rnd.lzo is a 9 MB file from /dev/urandom compressed with lzo.
> There doesn't seem to be a significant difference between all three variants.

I found that in compression benchmarks it depends a lot on the data
compressed.

urandom (which should be essentially incompressible) will be handled
by different code paths in the compressor than other more compressible data.
It becomes a complicated memcpy then.

But then there are IO benchmarks which also only do zeroes, which
also gives an unrealistic picture.

Usually it's best to use some corpus with different data types, from very
compressible to less so; and look at the aggregate.

For my snappy work I usually had at least large executables (medium) and some
pdfs (already compressed; low) and then uncompressed source code tars (high
compression)

-Andi


From geert at linux-m68k.org  Thu Aug 16 14:18:57 2012
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Thu, 16 Aug 2012 20:18:57 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120816175234.GL11413@one.firstfloor.org>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com> <20120816150647.GA22010@sig21.net>
 <20120816232549.4d14a6aa@natsu>
 <20120816175234.GL11413@one.firstfloor.org>
Message-ID: <CAMuHMdWK_Y=QwkgQD6K8tFBLaO04Fy0yVAzEpb2OYW6Ec0hGoA@mail.gmail.com>

On Thu, Aug 16, 2012 at 7:52 PM, Andi Kleen <andi at firstfloor.org> wrote:
>> I have locked the Allwinner A10 CPU in my Mele A2000 to 60 MHz using cpufreq-set,
>> and ran your test. rnd.lzo is a 9 MB file from /dev/urandom compressed with lzo.
>> There doesn't seem to be a significant difference between all three variants.
>
> I found that in compression benchmarks it depends a lot on the data
> compressed.
>
> urandom (which should be essentially incompressible) will be handled
> by different code paths in the compressor than other more compressible data.
> It becomes a complicated memcpy then.

In addition, locking the CPU to 60 MHz may improve the memory access penalty,
as a cache miss may cost much less cycles.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From thierry.reding at avionic-design.de  Thu Aug 16 14:27:03 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 16 Aug 2012 20:27:03 +0200
Subject: [PATCH v3 05/10] resource: add PCI configuration space support
In-Reply-To: <502D0F3C.4010308@wwwdotorg.org>
References: <1343332512-28762-1-git-send-email-thierry.reding@avionic-design.de>
 <1343332512-28762-6-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo4qg45brVRwEbw3=R04VsbnvUowSMWcT+M6VoAxbf3Cqg@mail.gmail.com>
 <20120814055542.GB16181@avionic-0098.mockup.avionic-design.de>
 <CAErSpo6LYpkC5wop53S1r1z3ov4+w4soqrQARzbbouVs1trzUg@mail.gmail.com>
 <20120814180142.GA9430@avionic-0098.mockup.avionic-design.de>
 <CAErSpo4Efy-Dt67rktzNiYfZfOTSu=pmYtyGd3tR-zZQ3jDGtA@mail.gmail.com>
 <20120815064902.GB15665@avionic-0098.mockup.avionic-design.de>
 <502D0F3C.4010308@wwwdotorg.org>
Message-ID: <20120816182703.GA31005@avionic-0098.mockup.avionic-design.de>

On Thu, Aug 16, 2012 at 09:18:20AM -0600, Stephen Warren wrote:
> On 08/15/2012 12:49 AM, Thierry Reding wrote:
> ...
> > Stephen: Could you try to find out whether the regular
> > configuration space translation can just be omitted if we already
> > set up the one for the extended configuration space? In
> > tegra_pcie_setup_translations(), BAR 0 is setup for regular
> > configuration space (which requires a 16 MiB region), while BAR 1
> > is setup for the extended configuration space (requiring a full 256
> > MiB region). However, if I understand correctly, each of the
> > registers that can be accessed via the BAR 0 translation can also
> > be accessed via the BAR 1 translation. That seems like we're 
> > wasting the 16 MiB set aside for the BAR 0 mapping.
> 
> I have confirmed that in theory, the EXTCFG space can indeed be used
> to access any register, making the regular config space redundant.
> However, using the HW this way has apparently received less validation.

Okay. I wasn't expecting anything else really. I'll give this a try next
time I get my hands on some Tegra hardware. If that works maybe we
should make up for the missing validation by testing this more
thoroughly.

Thierry
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From jason at lakedaemon.net  Thu Aug 16 14:37:08 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 16 Aug 2012 14:37:08 -0400
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120816132839.GO22226@titan.lakedaemon.net>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
Message-ID: <20120816183708.GT22226@titan.lakedaemon.net>

On Thu, Aug 16, 2012 at 09:28:39AM -0400, Jason Cooper wrote:
> On Mon, Aug 06, 2012 at 11:42:16AM +0200, Thomas Petazzoni wrote:
> > Andrew, Jason, Gr?gory,
> > 
> > Here is a small patch set that introduces basic support for address
> > decoding on Armada 370 and Armada XP. The aim of this basic support is
> > essentially to be able to configure a window to remap the BootROM,
> > which is needed to startup the secondary CPUs for the SMP support.
> > 
> > As we had discussed already, the address decoding configuration is not
> > described in the Device Tree, it is for now hardcoded on a per-SoC
> > basis. We might later discuss how to extend this to the Device Tree.
> > 
> > This patch set has five patches:
> > 
> >  (*) First patch reworks the addr-map code to use void __iomem * where
> >      appropriate instead of u32, as per the suggestion of Arnd
> >      Bergmann.
> > 
> >  (*) Second patch introducing PLAT_ORION_LEGACY, which allows the
> >      Marvell 370/XP platforms to be part of PLAT_ORION, and therefore
> >      re-use the existing address decoding code.
> > 
> >  (*) Third patch making a small change to an address decoding
> >      structure so that we can define at runtime the virtual address of
> >      the configuration registers. This is needed as on Armada 370/XP
> >      the address decoding "controller" is declared in the Device Tree.
> > 
> >  (*) Fourth patch adding the 370/XP address decoding code itself. For
> >      now, it only maps the BootROM on Armada XP.
> > 
> >  (*) Fifth path adding the necessary DT code to instantiate the
> >      address decoding "controller".
> > 
> > Changes since v2:
> >  * Remove one more useless (void __iomem *) cast in the Armada 370/XP
> >    addr-map.c file, as noticed by Arnd Bergmann.
> > 
> > Changes since v1:
> >  * Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
> >  * Add Acked-by on patches 2->5 from Gr?gory Cl?ment
> 
> Whole series applied to:
> 
> git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7

I'm getting the following build error with orion_nand enabled:

  CC      drivers/mtd/nand/orion_nand.o
drivers/mtd/nand/orion_nand.c:24:27: fatal error: mach/hardware.h: No
such file or directory
compilation terminated.

I don't have time to look at it right now, hopefully I can look at it
tomorrow or this weekend.

thx,

Jason.


From gregkh at linuxfoundation.org  Thu Aug 16 14:45:02 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 16 Aug 2012 11:45:02 -0700
Subject: [PATCH v4 4/4] memory: emif: add device tree support to emif
 driver
In-Reply-To: <CAMQu2gyBQ-iJCLCtPziX8eRm6_eXZfAoDDO0DusKCBQYpaR8jQ@mail.gmail.com>
References: <CAMQu2gz6jdcR4hQPPbmyO8vrkdmppHeCkZmV3_9w27LOzKrUuA@mail.gmail.com>
 <20120630042356.GC1816@kroah.com>
 <CAMQu2gy0MmP4JLW4P1FreJqMMEBYSTjkLHJb8WX=aXLA6hxtZg@mail.gmail.com>
 <CAMQu2gxZ-tWJXAOeh20NsF1uyvs9fqwYtggFv=d7-qX+WFumRQ@mail.gmail.com>
 <CAMQu2gw_ZB7gVyL95B-h27B1fQh0d-YB3weaWRN6DNaGtSypDw@mail.gmail.com>
 <20120717163602.GA7167@kroah.com>
 <CAMQu2gw2Zt3E8byD=_nUXya-xU=gOA71arbbSh7gzxQhet0Vtg@mail.gmail.com>
 <20120717175832.GA20806@kroah.com>
 <CAMQu2gy5dkzoUDy0eFXAKqA-GkBvmmBdQwkfHUaySuKGqF9MKw@mail.gmail.com>
 <CAMQu2gyBQ-iJCLCtPziX8eRm6_eXZfAoDDO0DusKCBQYpaR8jQ@mail.gmail.com>
Message-ID: <20120816184502.GA20400@kroah.com>

On Mon, Aug 13, 2012 at 10:57:06AM +0530, Shilimkar, Santosh wrote:
> Greg,
> 
> On Wed, Jul 18, 2012 at 12:14 PM, Shilimkar, Santosh
> <santosh.shilimkar at ti.com> wrote:
> > On Tue, Jul 17, 2012 at 11:28 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> >> On Tue, Jul 17, 2012 at 10:37:45PM +0530, Shilimkar, Santosh wrote:
> >>> On Tue, Jul 17, 2012 at 10:06 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> >>> > On Mon, Jul 09, 2012 at 07:02:36PM +0530, Shilimkar, Santosh wrote:
> >>> >> Greg,
> >>> >>
> >
> > [..]
> >
> >>> >From 74688a87fd490909e9122bf757c0096480e9fc11 Mon Sep 17 00:00:00 2001
> >>> From: Aneesh V <aneesh at ti.com>
> >>> Date: Mon, 30 Jan 2012 20:06:30 +0530
> >>> Subject: [PATCH 4/4] memory: emif: add device tree support to emif driver
> >>>
> >>> Device tree support for the EMIF driver. LPDDR2 generic timings
> >>> extraction from device is managed using couple of helper
> >>> functions which can be used by other memory controller
> >>> drivers.
> >>>
> >>> Reviewed-by: Benoit Cousson <b-cousson at ti.com>
> >>> Reviewed-by: Grant Likely <grant.likely at secretlab.ca>
> >>> Tested-by: Lokesh Vutla <lokeshvutla at ti.com>
> >>> Signed-off-by: Aneesh V <aneesh at ti.com>
> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >>> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> >>> ---
> >>>  drivers/memory/Makefile    |    1 +
> >>>  drivers/memory/emif.c      |  182 +++++++++++++++++++++++++++++++++++++++++++-
> >>>  drivers/memory/of_memory.c |  153 +++++++++++++++++++++++++++++++++++++
> >>>  drivers/memory/of_memory.h |   36 +++++++++
> >>>  4 files changed, 371 insertions(+), 1 deletion(-)
> >>>  create mode 100644 drivers/memory/of_memory.c
> >>>  create mode 100644 drivers/memory/of_memory.h
> >>>
> >>> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> >>> index 42b3ce9..cd8486b 100644
> >>> --- a/drivers/memory/Makefile
> >>> +++ b/drivers/memory/Makefile
> >>> @@ -2,6 +2,7 @@
> >>>  # Makefile for memory devices
> >>>  #
> >>>
> >>> +obj-$(CONFIG_OF)             += of_memory.o
> >>>  obj-$(CONFIG_TI_EMIF)                += emif.o
> >>>  obj-$(CONFIG_TEGRA20_MC)     += tegra20-mc.o
> >>>  obj-$(CONFIG_TEGRA30_MC)     += tegra30-mc.o
> >>> diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
> >>> index 33a4396..06b4eb7 100644
> >>> --- a/drivers/memory/emif.c
> >>> +++ b/drivers/memory/emif.c
> >>> @@ -18,6 +18,7 @@
> >>>  #include <linux/platform_device.h>
> >>>  #include <linux/interrupt.h>
> >>>  #include <linux/slab.h>
> >>> +#include <linux/of.h>
> >>>  #include <linux/debugfs.h>
> >>>  #include <linux/seq_file.h>
> >>>  #include <linux/module.h>
> >>> @@ -25,6 +26,7 @@
> >>>  #include <linux/spinlock.h>
> >>>  #include <memory/jedec_ddr.h>
> >>>  #include "emif.h"
> >>> +#include "of_memory.h"
> >>>
> >>>  /**
> >>>   * struct emif_data - Per device static data for driver's use
> >>> @@ -49,6 +51,7 @@
> >>>   *                           frequency in effect at the moment)
> >>>   * @plat_data:                       Pointer to saved platform data.
> >>>   * @debugfs_root:            dentry to the root folder for EMIF in debugfs
> >>> + * @np_ddr:                  Pointer to ddr device tree node
> >>>   */
> >>>  struct emif_data {
> >>>       u8                              duplicate;
> >>> @@ -63,6 +66,7 @@ struct emif_data {
> >>>       struct emif_regs                *curr_regs;
> >>>       struct emif_platform_data       *plat_data;
> >>>       struct dentry                   *debugfs_root;
> >>> +     struct device_node              *np_ddr;
> >>>  };
> >>>
> >>>  static struct emif_data *emif1;
> >>> @@ -1148,6 +1152,168 @@ static int is_custom_config_valid(struct
> >>> emif_custom_configs *cust_cfgs,
> >>>       return valid;
> >>>  }
> >>>
> >>> +#if defined(CONFIG_OF)
> >>> +static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
> >>> +             struct emif_data *emif)
> >>
> >> Why can't all of this code be in the of_memory.c file?
> >>
> > Primarily because the parameters are very much specific to EMIF
> > memory controller and won't be of much use for other memory controllers.
> >
> > Currently the information extracted from DT with these function is like:
> > - EMIF controller IP version : EMIF_4D or EMIF_4D5
> > - Which analog phy is integrated : EMIF_ATTILAPHY or EMIF_ATTILAPHY
> > - IP hardware interface: EMIF Low latency port or sys port interface.
> > - EMIF connections - Whether EMIF1 only, EMIF2 only or EMIF1 & EMIF2
> > - Memory connections to EMIF - Same type and size memories or asymmetric
> > - Chip select usage per controller: Whether CS0, CS1, CS0 & CS1
> > - ZQ calibration - Per chip select or enable EMIF dual calibration feature.
> > - Enable/disable EMIF Low power mode and temperature alerts.
> > - EMIF low power mode configuration:
> >       - Clock stop, self refresh, Deep power down.
> >       - Low power time out values for performance and power mode.
> >       - DDR frequency threshold to switch between power and
> > performance settings.
> > - EMIF temperature polling cycle configuration.
> >
> > As you can see these are very specific to the EMIF memory controller and hence
> > I didn't move them to of_memory.c
> >
> Do you have any more comment on this patch? If not, I can go ahead and
> post the refreshed version of the patch.

Please always do, I have no idea what this patch even contained anymore,
it was a few hundred patches ago that I've reviewed and I have no
recollection of it...

thanks,

greg k-h


From matt at genesi-usa.com  Thu Aug 16 14:51:54 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 16 Aug 2012 13:51:54 -0500
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120816033006.GA11999@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120816033006.GA11999@shlinux2.ap.freescale.net>
Message-ID: <CAKGA1bkDL=-NCvSNSb8t4LA6wjfDTi-L042ix6n-nEZpap5szQ@mail.gmail.com>

On Wed, Aug 15, 2012 at 10:30 PM, Dong Aisheng <b29396 at freescale.com> wrote:
> On Wed, Aug 15, 2012 at 09:59:50PM +0800, Shawn Guo wrote:
> ...
>> > Another known issue is that via this way, that means the pinctrl subsystem
>> > can only see the using pads, this is a bit not align with the pinctrl
>> > subsystem design. No sure if Linus would like to see it.
>> >
>> I do not quite follow on this.  The "enum imx51_pads" will still be
>> there, so all the pads will still be visible to the pinctrl system.
>
> Sorry, i did not describe it accurately.
> The problem is that those pins are visible to pinctrl subystem, but the pinctrl
> subsystem can not manage them all.

Why not? It only needs to "manage" the ones the DT defines or the ones
you specify.

The rest of the data is there as a convenience for debug and naming of
pins, a cross-reference that could be compiled out for non-debug
kernels since there's not a lot of point wasting 64kb or possibly more
of memory on naming every pin on the chip statically. The name of the
pad is in pin_desc and can be marked dynamic (a small function at
get_pin_desc can work out the string and vsprintf the correct string,
and put_pin_desc can free it again). The name of the groups/configs
etc. is also dynamic, no?

> Because for the way proposed, all the pin's basic properties like mux_reg, config_reg
> are parsed from device tree at runtime.

The ones you want to perform anyway.

> If a pin is not used in device tree, the driver can not know this pin's
> corresponding registers.

It would. I'm not saying get rid of the table, just remove the
redundancy - if you don't reference pins by "arbitrary id" anymore,
why include an arbitrary id?

At the moment you've got a redundant list of enums to define offsets
into an array which is.. an array anyway. You can always work out the
position in the array from it's address and the structure size
(offsetof or some clever math).

If you're not referencing the pin by index into the array anyway which
is bad behavior, the other data serves as cross-reference - the
register offsets defined are unique to the pin in question. So the
enums go away, and the first element of imx_pin_reg goes away. The
rest is just debug data.

The static pinctrl_pin_desc array can go away as well. As it stands
it's a waste of memory - MX6Q_PAD_ in every string cannot be merged by
the compiler, that's 329 multiplied 9 bytes you're compiling into the
kernel redundantly. The name can be referenced - I'm gonna use
MX6Q_PAD_SD4_CMD__SD4_CMD as an example here to reduce confusion.

> Then imx_pinconf_dbg_show in current driver may need change since it does not
> support show all pins's config value.

You will need the huge static array to cross-reference the pins
canonical name and generated configuration, sure, I don't want to
remove it, just.. not use array index to reference it from the device
tree.

If you imagine building a string like "MX6Q_PAD_" "SD4_CMD" "__"
"SD4_CMD" - this is defined by the SoC in use and the DT binding, the
default pad name from the docs, a couple underscores to match the old
iomux-v3 definition which we are still clinging on to (and should
since this is what's used in U-Boot right now) and the ALT mode from
the MUX_MODE bits.

The enum id can be replaced with a pin name string pointer "SD4_CMD"
which is static per pin. The imx_pin_reg struct would become

struct imx_pin_reg {
   const char *pad_name;
   u32 mux_reg;
   u32 ctl_reg;
   u32 ipp_reg;
   const char *mux_modes;
   u32 nmodes;
};

This can be used to build strings for debug. You're not using much
more space than the existing model, and the array contains strings
defining the last part of the debug string representing the alt mode -
saving a little bit of memory besides. And of course, it's not needed
to actually perform the muxing since that's just adding register
offsets to bases and writel() a value direct from the DT (although,
imx_pin_reg could be used to verify that the 3 pairs correspond to
each other...)

And you'd need strings to define the CTL settings like HYS, ODE, PKE,
PUE settings from the registers and give them human readable names as
per the device tree binding, as they were set, but this is not in the
imx_pin_regs array (or maybe it is, someone should put all the default
pad settings in there?).

Build the string like you want and you reproduce the naming in the
comments. Some other debug data needs to be exposed to define the bits
in the register as above, which isn't done right now. As such the
debug currently isn't so useful - it only describes the pad itself,
the MUX_MODE in an i.MX IOMUXC and the rest of the information is lost
since it does not take into account the pad control itself. This is
lucky as it's less work for now.

> If it supports, will imx driver also support config unused pins in devicetree
> via sysfs?

Setting up the stuff from the device tree wouldn't involve the
imx_pin_reg array so you could compile the whole thing out if you
didn't want the space usage or the chattiness of debug logs.

> Probably it may be rarely used and imx just does not support it.
> Then we can get register data from devicetree.

-- 
Matt


From matt at genesi-usa.com  Thu Aug 16 14:56:39 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 16 Aug 2012 13:56:39 -0500
Subject: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung
 Exynos4210 SoC
In-Reply-To: <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
 <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAKGA1b=nXbTU70tFWWwvKoA6N4bMjG9R-vs2egppzQbwgkxAVw@mail.gmail.com>

Re: samsung,pin-function samsung,pin-pud samsung,pin-drv - why can't
these be one property, why take the space to define them individually
instead of in an array of 3 values under one property name?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Wed, Aug 15, 2012 at 3:10 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> Add pinctrl driver nodes for the three instances of pin controllers
> in Samsung Exynos4210 SoC and add the pin group nodes available in the
> each of those three instances.
>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
>  2 files changed, 494 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
>
> diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
> new file mode 100644
> index 0000000..b12cf27
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
> @@ -0,0 +1,457 @@
> +/*
> + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2011-2012 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
> + * tree nodes are listed in this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/ {
> +       pinctrl at 11400000 {
> +               uart0_data: uart0-data {
> +                       samsung,pins = "gpa0-0", "gpa0-1";
> +                       samsung,pin-function = <0x2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart0_fctl: uart0-fctl {
> +                       samsung,pins = "gpa0-2", "gpa0-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart1_data: uart1-data {
> +                       samsung,pins = "gpa0-4", "gpa0-5";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart1_fctl: uart1-fctl {
> +                       samsung,pins = "gpa0-6", "gpa0-7";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c2_bus: i2c2-bus {
> +                       samsung,pins = "gpa0-6", "gpa0-7";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart2_data: uart2-data {
> +                       samsung,pins = "gpa1-0", "gpa1-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart2_fctl: uart2-fctl {
> +                       samsung,pins = "gpa1-2", "gpa1-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart_audio_a: uart-audio-a {
> +                       samsung,pins = "gpa1-0", "gpa1-1";
> +                       samsung,pin-function = <4>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c3_bus: i2c3-bus {
> +                       samsung,pins = "gpa1-2", "gpa1-3";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart3_data: uart3-data {
> +                       samsung,pins = "gpa1-4", "gpa1-5";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               uart_audio_b: uart-audio-b {
> +                       samsung,pins = "gpa1-4", "gpa1-5";
> +                       samsung,pin-function = <4>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               spi0_bus: spi0-bus {
> +                       samsung,pins = "gpb-0", "gpb-2", "gpb-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c4_bus: i2c4-bus {
> +                       samsung,pins = "gpb-2", "gpb-3";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               spi1_bus: spi1-bus {
> +                       samsung,pins = "gpb-4", "gpb-6", "gpb-7";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c5_bus: i2c5-bus {
> +                       samsung,pins = "gpb-6", "gpb-7";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2s1_bus: i2s1-bus {
> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
> +                                       "gpc0-4";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               pcm1_bus: pcm1-bus {
> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
> +                                       "gpc0-4";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               ac97_bus: ac97-bus {
> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
> +                                       "gpc0-4";
> +                       samsung,pin-function = <4>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2s2_bus: i2s2-bus {
> +                       samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
> +                                       "gpc1-4";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               pcm2_bus: pcm2-bus {
> +                       samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
> +                                       "gpc1-4";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               spdif_bus: spdif-bus {
> +                       samsung,pins = "gpc1-0", "gpc1-1";
> +                       samsung,pin-function = <4>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c6_bus: i2c6-bus {
> +                       samsung,pins = "gpc1-3", "gpc1-4";
> +                       samsung,pin-function = <4>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               spi2_bus: spi2-bus {
> +                       samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
> +                       samsung,pin-function = <5>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c7_bus: i2c7-bus {
> +                       samsung,pins = "gpd0-2", "gpd0-3";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c0_bus: i2c0-bus {
> +                       samsung,pins = "gpd1-0", "gpd1-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               i2c1_bus: i2c1-bus {
> +                       samsung,pins = "gpd1-2", "gpd1-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +       };
> +
> +       pinctrl at 11000000 {
> +               sd0_clk: sd0-clk {
> +                       samsung,pins = "gpk0-0";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd0_cmd: sd0-cmd {
> +                       samsung,pins = "gpk0-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd0_cd: sd0-cd {
> +                       samsung,pins = "gpk0-2";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd0_bus1: sd0-bus-width1 {
> +                       samsung,pins = "gpk0-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd0_bus4: sd0-bus-width4 {
> +                       samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd0_bus8: sd0-bus-width8 {
> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_clk: sd4-clk {
> +                       samsung,pins = "gpk0-0";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_cmd: sd4-cmd {
> +                       samsung,pins = "gpk0-1";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_cd: sd4-cd {
> +                       samsung,pins = "gpk0-2";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_bus1: sd4-bus-width1 {
> +                       samsung,pins = "gpk0-3";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_bus4: sd4-bus-width4 {
> +                       samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd4_bus8: sd4-bus-width8 {
> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <4>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd1_clk: sd1-clk {
> +                       samsung,pins = "gpk1-0";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd1_cmd: sd1-cmd {
> +                       samsung,pins = "gpk1-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd1_cd: sd1-cd {
> +                       samsung,pins = "gpk1-2";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd1_bus1: sd1-bus-width1 {
> +                       samsung,pins = "gpk1-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd1_bus4: sd1-bus-width4 {
> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_clk: sd2-clk {
> +                       samsung,pins = "gpk2-0";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_cmd: sd2-cmd {
> +                       samsung,pins = "gpk2-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_cd: sd2-cd {
> +                       samsung,pins = "gpk2-2";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_bus1: sd2-bus-width1 {
> +                       samsung,pins = "gpk2-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_bus4: sd2-bus-width4 {
> +                       samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd2_bus8: sd2-bus-width8 {
> +                       samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
> +                       samsung,pin-function = <3>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd3_clk: sd3-clk {
> +                       samsung,pins = "gpk3-0";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd3_cmd: sd3-cmd {
> +                       samsung,pins = "gpk3-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd3_cd: sd3-cd {
> +                       samsung,pins = "gpk3-2";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd3_bus1: sd3-bus-width1 {
> +                       samsung,pins = "gpk3-3";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               sd3_bus4: sd3-bus-width4 {
> +                       samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <3>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               eint0: ext-int0 {
> +                       samsung,pins = "gpx0-0";
> +                       samsung,pin-function = <0xf>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               eint8: ext-int8 {
> +                       samsung,pins = "gpx1-0";
> +                       samsung,pin-function = <0xf>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               eint15: ext-int15 {
> +                       samsung,pins = "gpx1-7";
> +                       samsung,pin-function = <0xf>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               eint16: ext-int16 {
> +                       samsung,pins = "gpx2-0";
> +                       samsung,pin-function = <0xf>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               eint31: ext-int31 {
> +                       samsung,pins = "gpx3-7";
> +                       samsung,pin-function = <0xf>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +       };
> +
> +       pinctrl at 03860000 {
> +               i2s0_bus: i2s0-bus {
> +                       samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
> +                                       "gpz-4", "gpz-5", "gpz-6";
> +                       samsung,pin-function = <0x2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +
> +               pcm0_bus: pcm0-bus {
> +                       samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
> +                                       "gpz-4";
> +                       samsung,pin-function = <0x3>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };
> +       };
> +};
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 02891fe..a4bd0c9 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -20,6 +20,7 @@
>  */
>
>  /include/ "skeleton.dtsi"
> +/include/ "exynos4210-pinctrl.dtsi"
>
>  / {
>         compatible = "samsung,exynos4210";
> @@ -29,6 +30,9 @@
>                 spi0 = &spi_0;
>                 spi1 = &spi_1;
>                 spi2 = &spi_2;
> +               pinctrl0 = &pinctrl_0;
> +               pinctrl1 = &pinctrl_1;
> +               pinctrl2 = &pinctrl_2;
>         };
>
>         gic:interrupt-controller at 10490000 {
> @@ -50,6 +54,39 @@
>                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
>         };
>
> +       pinctrl_0: pinctrl at 11400000 {
> +               compatible = "samsung,pinctrl-exynos4210";
> +               reg = <0x11400000 0x1000>;
> +               interrupts = <0 47 0>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +       };
> +
> +       pinctrl_1: pinctrl at 11000000 {
> +               compatible = "samsung,pinctrl-exynos4210";
> +               reg = <0x11000000 0x1000>;
> +               interrupts = <0 46 0>;
> +               interrupt-controller;
> +               #interrupt-cells = <2>;
> +
> +               wakup_eint: wakeup-interrupt-controller {
> +                       compatible = "samsung,exynos4210-wakeup-eint";
> +                       interrupt-parent = <&gic>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +                       interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> +                                       <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> +                                       <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> +                                       <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
> +                                       <0 32 0>;
> +               };
> +       };
> +
> +       pinctrl_2: pinctrl at 03860000 {
> +               compatible = "samsung,pinctrl-exynos4210";
> +               reg = <0x03860000 0x1000>;
> +       };
> +
>         watchdog at 10060000 {
>                 compatible = "samsung,s3c2410-wdt";
>                 reg = <0x10060000 0x100>;
> --
> 1.6.6.rc2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From nico at fluxnic.net  Thu Aug 16 14:59:43 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 16 Aug 2012 14:59:43 -0400 (EDT)
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
Message-ID: <alpine.LFD.2.02.1208161438110.1541@xanadu.home>

On Tue, 14 Aug 2012, Catalin Marinas wrote:

> The patch adds the kernel booting and the initial setup code.
> Documentation/arm64/booting.txt describes the booting protocol on the
> AArch64 Linux kernel. This is subject to change following the work on
> boot standardisation, ACPI.
> 
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

A few minor comments below, otherwise...

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  Documentation/arm64/booting.txt |  141 +++++++++++
>  arch/arm64/include/asm/setup.h  |   26 ++
>  arch/arm64/kernel/head.S        |  521 +++++++++++++++++++++++++++++++++++++++
>  arch/arm64/kernel/setup.c       |  357 +++++++++++++++++++++++++++
>  4 files changed, 1045 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/arm64/booting.txt
>  create mode 100644 arch/arm64/include/asm/setup.h
>  create mode 100644 arch/arm64/kernel/head.S
>  create mode 100644 arch/arm64/kernel/setup.c
> 
> diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt
> new file mode 100644
> index 0000000..3197820
> --- /dev/null
> +++ b/Documentation/arm64/booting.txt
> @@ -0,0 +1,141 @@
> +			Booting AArch64 Linux
> +			=====================
> +
> +Author: Will Deacon <will.deacon at arm.com>
> +Date  : 25 April 2012
> +
> +This document is based on the ARM booting document by Russell King and
> +is relevant to all public releases of the AArch64 Linux kernel.
> +
> +The AArch64 exception model is made up of a number of exception levels
> +(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
> +counterpart.  EL2 is the hypervisor level and exists only in non-secure
> +mode. EL3 is the highest priority level and exists only in secure mode.
> +
> +For the purposes of this document, we will use the term `boot loader'
> +simply to define all software that executes on the CPU(s) before control
> +is passed to the Linux kernel.  This may include secure monitor and
> +hypervisor code, or it may just be a handful of instructions for
> +preparing a minimal boot environment.
> +
> +Essentially, the boot loader should provide (as a minimum) the
> +following:
> +
> +1. Setup and initialise the RAM
> +2. Setup the device tree
> +3. Decompress the kernel image
> +4. Call the kernel image
> +
> +
> +1. Setup and initialise RAM
> +---------------------------
> +
> +Requirement: MANDATORY
> +
> +The boot loader is expected to find and initialise all RAM that the
> +kernel will use for volatile data storage in the system.  It performs
> +this in a machine dependent manner.  (It may use internal algorithms
> +to automatically locate and size all RAM, or it may use knowledge of
> +the RAM in the machine, or any other method the boot loader designer
> +sees fit.)
> +
> +
> +2. Setup the device tree
> +-------------------------
> +
> +Requirement: MANDATORY
> +
> +The device tree blob (dtb) must be no bigger than 2 megabytes in size
> +and placed at a 2-megabyte boundary within the first 512 megabytes from
> +the start of the kernel image. This is to allow the kernel to map the
> +blob using a single section mapping in the initial page tables.

It might be a good idea to specify the minimum information that should 
be contained in the DTB.  Memory size is certainly one such item.

> +3. Decompress the kernel image
> +------------------------------
> +
> +Requirement: OPTIONAL
> +
> +The AArch64 kernel does not provide a decompressor and therefore
> +requires gzip decompression to be performed by the boot loader if the
> +default Image.gz target is used.  For bootloaders that do not implement
> +this requirement, the larger Image target is available instead.

Some people will want to use bzip2 or whatever other decompressor du 
jour.  Maybe this shouldn't be gzip specific, or just presented as a 
possible option?

> +4. Call the kernel image
> +------------------------
> +
> +Requirement: MANDATORY
> +
> +The decompressed kernel image contains a 32-byte header as follows:
> +
> +  u32 magic	= 0x14000008;	/* branch to stext, little-endian */
> +  u32 res0	= 0;		/* reserved */
> +  u64 text_offset;		/* Image load offset */
> +  u64 res1	= 0;		/* reserved */
> +  u64 res2	= 0;		/* reserved */
> +
> +The image must be placed at the specified offset (currently 0x80000)
> +from the start of the system RAM and called there. The start of the
> +system RAM must be aligned to 2MB.
> +
> +Before jumping into the kernel, the following conditions must be met:
> +
> +- Quiesce all DMA capable devices so that memory does not get
> +  corrupted by bogus network packets or disk data.  This will save
> +  you many hours of debug.
> +
> +- Primary CPU general-purpose register settings
> +  x0 = physical address of device tree blob (dtb) in system RAM.

I think you should mandate that some additional registers be explicitly 
initialized to 0 for possible future usage (and also mentioned in the 
corresponding code comment).  We have that issue on ARM32 where it is 
unclear if r2 contains a valid ATAG/DTB address or not as its content 
was not defined before.

[...]


Nicolas


From u.kleine-koenig at pengutronix.de  Thu Aug 16 16:29:32 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 16 Aug 2012 22:29:32 +0200
Subject: [PATCH v6 0/3] Updated Cortex-M3 series
In-Reply-To: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343988614-5508-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120816202932.GY2232@pengutronix.de>

Hello Russell,

On Fri, Aug 03, 2012 at 12:10:11PM +0200, Uwe Kleine-K?nig wrote:
> the only changes compared to v5 (sent starting with Message-id:
> 1341512035-8173-1-git-send-email-u.kleine-koenig at pengutronix.de)
> are that several debug pr_infos were dropped that I missed to remove
> before. Thanks to Will Deacon for pointing out that problem.
> Furthermore I rebased (trivially) to v3.5.
Any feedback from your side? It would be great to get this in for 3.7
with some time in next before.

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From rjw at sisk.pl  Thu Aug 16 17:05:54 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 16 Aug 2012 23:05:54 +0200
Subject: [PATCH v3 2/3] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <1344577046-14847-3-git-send-email-shawn.guo@linaro.org>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
 <1344577046-14847-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <201208162305.55114.rjw@sisk.pl>

On Friday, August 10, 2012, Shawn Guo wrote:
> With a lot of devices booting from device tree nowadays, it requires
> that OPP table can be initialized from device tree.  The patch adds
> a helper function of_init_opp_table together with a binding doc for
> that purpose.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

I need an ACK from whoever maintains the DT bindings for that.

Thanks,
Rafael


> ---
>  Documentation/devicetree/bindings/power/opp.txt |   25 ++++++++++++
>  drivers/base/power/opp.c                        |   47 +++++++++++++++++++++++
>  include/linux/opp.h                             |    8 ++++
>  3 files changed, 80 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/power/opp.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt
> new file mode 100644
> index 0000000..74499e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/opp.txt
> @@ -0,0 +1,25 @@
> +* Generic OPP Interface
> +
> +SoCs have a standard set of tuples consisting of frequency and
> +voltage pairs that the device will support per voltage domain. These
> +are called Operating Performance Points or OPPs.
> +
> +Properties:
> +- operating-points: An array of 2-tuples items, and each item consists
> +  of frequency and voltage like <freq-kHz vol-uV>.
> +	freq: clock frequency in kHz
> +	vol: voltage in microvolt
> +
> +Examples:
> +
> +cpu at 0 {
> +	compatible = "arm,cortex-a9";
> +	reg = <0>;
> +	next-level-cache = <&L2>;
> +	operating-points = <
> +		/* kHz    uV */
> +		792000  1100000
> +		396000  950000
> +		198000  850000
> +	>;
> +};
> diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
> index ac993ea..d946864 100644
> --- a/drivers/base/power/opp.c
> +++ b/drivers/base/power/opp.c
> @@ -22,6 +22,7 @@
>  #include <linux/rculist.h>
>  #include <linux/rcupdate.h>
>  #include <linux/opp.h>
> +#include <linux/of.h>
>  
>  /*
>   * Internal data structure organization with the OPP layer library is as
> @@ -674,3 +675,49 @@ struct srcu_notifier_head *opp_get_notifier(struct device *dev)
>  
>  	return &dev_opp->head;
>  }
> +
> +#ifdef CONFIG_OF
> +/**
> + * of_init_opp_table() - Initialize opp table from device tree
> + * @dev:	device pointer used to lookup device OPPs.
> + *
> + * Register the initial OPP table with the OPP library for given device.
> + */
> +int of_init_opp_table(struct device *dev)
> +{
> +	const struct property *prop;
> +	const __be32 *val;
> +	int nr;
> +
> +	prop = of_find_property(dev->of_node, "operating-points", NULL);
> +	if (!prop)
> +		return -ENODEV;
> +	if (!prop->value)
> +		return -ENODATA;
> +
> +	/*
> +	 * Each OPP is a set of tuples consisting of frequency and
> +	 * voltage like <freq-kHz vol-uV>.
> +	 */
> +	nr = prop->length / sizeof(u32);
> +	if (nr % 2) {
> +		dev_err(dev, "%s: Invalid OPP list\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	val = prop->value;
> +	while (nr) {
> +		unsigned long freq = be32_to_cpup(val++) * 1000;
> +		unsigned long volt = be32_to_cpup(val++);
> +
> +		if (opp_add(dev, freq, volt)) {
> +			dev_warn(dev, "%s: Failed to add OPP %ld\n",
> +				 __func__, freq);
> +			continue;
> +		}
> +		nr -= 2;
> +	}
> +
> +	return 0;
> +}
> +#endif
> diff --git a/include/linux/opp.h b/include/linux/opp.h
> index 2a4e5fa..214e0eb 100644
> --- a/include/linux/opp.h
> +++ b/include/linux/opp.h
> @@ -48,6 +48,14 @@ int opp_disable(struct device *dev, unsigned long freq);
>  
>  struct srcu_notifier_head *opp_get_notifier(struct device *dev);
>  
> +#ifdef CONFIG_OF
> +int of_init_opp_table(struct device *dev);
> +#else
> +static inline int of_init_opp_table(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +#endif /* CONFIG_OF */
>  #else
>  static inline unsigned long opp_get_voltage(struct opp *opp)
>  {
> 



From swarren at wwwdotorg.org  Thu Aug 16 17:12:10 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 16 Aug 2012 15:12:10 -0600
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120816033006.GA11999@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120816033006.GA11999@shlinux2.ap.freescale.net>
Message-ID: <502D622A.1030104@wwwdotorg.org>

On 08/15/2012 09:30 PM, Dong Aisheng wrote:
> On Wed, Aug 15, 2012 at 09:59:50PM +0800, Shawn Guo wrote:
> ...
>>> Another known issue is that via this way, that means the pinctrl subsystem
>>> can only see the using pads, this is a bit not align with the pinctrl
>>> subsystem design. No sure if Linus would like to see it.
>>>
>> I do not quite follow on this.  The "enum imx51_pads" will still be
>> there, so all the pads will still be visible to the pinctrl system.
>>
> Sorry, i did not describe it accurately.
> The problem is that those pins are visible to pinctrl subystem, but the pinctrl
> subsystem can not manage them all.
> Not sure this meet Linus's original design purpose.
> Because for the way proposed, all the pin's basic properties like mux_reg, config_reg
> are parsed from device tree at runtime.
> If a pin is not used in device tree, the driver can not know this pin's
> corresponding registers.
> Thus, for those unused pins, we can not manage it on mux or config in pinctrl
> subsystem and driver.
> 
> For example, the pin_config_get/pin_config_set API in
> include/linux/pinctrl/consumer.h can not work for such pins.

Hmmm. Given we support all pin mux/config options from the mapping
table, I'd question whether that API should even exist any more...

> Then imx_pinconf_dbg_show in current driver may need change since it does not
> support show all pins's config value.

The pinctrl core assumes that the pin numbering space could be sparse.
For example, see that pinconf.c:pinconf_pins_show() "continues" the loop
if pin_desc_get() fails for a particular pin number. So just based on
what I've read in this one email, I think this is fine.

> It looks like not a big issue currently since i did not see any client driver
> using this API.
> But i'm not sure if we may have this requirement in the future.
> For example, is it possible that pinctrl subsystem may support configure pins
> via sysfs dynamically?

I can't comment on sysfs specifically, but I believe it would be
generally true that a pin that isn't know to the pinctrl subsystem can't
be manipulated in any way.


From mporter at ti.com  Thu Aug 16 17:44:28 2012
From: mporter at ti.com (Matt Porter)
Date: Thu, 16 Aug 2012 17:44:28 -0400
Subject: [PATCH 0/3] DaVinci DMA engine conversion
Message-ID: <1345153471-22757-1-git-send-email-mporter@ti.com>

This series begins the conversion of the DaVinci private
EDMA API implementation to a DMA engine driver and
converts two of the three in-kernel users of the private
EDMA API to DMA engine.

The approach taken is similar to the recent OMAP DMA
Engine conversion. The EDMA DMA Engine driver is a
wrapper around the existing private EDMA implementation
and registers the platform device within the driver.
This allows the conversion series to stand alone with
just the drivers and no changes to platform code. It
also allows peripheral drivers to continue to use the
private EDMA implementation until they are converted.

The EDMA DMA Engine driver supports slave transfers only
at this time. It is planned to add cyclic transfers in
support of audio peripherals.

There are three users of the private EDMA API in the
kernel now: davinci_mmc, spi-davinci, and davinci-mcasp.
This series provides DMA Engine conversions for the
davinci_mmc and spi-davinci drivers which use the
supported slave transfers.

This series has been tested on an AM18x EVM and
performance is comparable with the private EDMA
API implementations. I do not have a Wifi module
for the AM18x EVM to test the MMC1 instance which
has DMA channels on the second EDMA channel controller
instance. Testing is needed on all DaVinci platforms
including DM355/365, DM644x/6x, DA830/OMAP-L137/AM17x,
and DA850/OMAP-L138/AM18x.

After this series, the current plan is to complete
the mcasp driver conversion which includes adding
cyclic dma support. This will then enable the
removal and refactoring of the private EDMA API
functionality into the EDMA DMA Engine driver.
Since EDMA is also used on the AM33xx family of
parts in mach-omap2/, the plan is to enable this
driver on that platform as well.

Matt Porter (3):
  dmaengine: add TI EDMA DMA engine driver
  mmc: davinci_mmc: convert to DMA engine API
  spi: spi-davinci: convert to DMA engine API

 drivers/dma/Kconfig            |    9 +
 drivers/dma/Makefile           |    1 +
 drivers/dma/edma.c             |  729 ++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/davinci_mmc.c |  271 +++++----------
 drivers/spi/spi-davinci.c      |  292 +++++++---------
 include/linux/edma.h           |   29 ++
 6 files changed, 980 insertions(+), 351 deletions(-)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

-- 
1.7.9.5



From mporter at ti.com  Thu Aug 16 17:44:31 2012
From: mporter at ti.com (Matt Porter)
Date: Thu, 16 Aug 2012 17:44:31 -0400
Subject: [PATCH 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345153471-22757-1-git-send-email-mporter@ti.com>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
Message-ID: <1345153471-22757-4-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/spi/spi-davinci.c |  292 ++++++++++++++++++++-------------------------
 1 file changed, 130 insertions(+), 162 deletions(-)

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 9b2901f..c1ec52d 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -25,13 +25,14 @@
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
 #include <mach/spi.h>
-#include <mach/edma.h>
 
 #define SPI_NO_RESOURCE		((resource_size_t)-1)
 
@@ -113,14 +114,6 @@
 #define SPIDEF		0x4c
 #define SPIFMT0		0x50
 
-/* We have 2 DMA channels per CS, one for RX and one for TX */
-struct davinci_spi_dma {
-	int			tx_channel;
-	int			rx_channel;
-	int			dummy_param_slot;
-	enum dma_event_q	eventq;
-};
-
 /* SPI Controller driver's private data. */
 struct davinci_spi {
 	struct spi_bitbang	bitbang;
@@ -134,11 +127,14 @@ struct davinci_spi {
 
 	const void		*tx;
 	void			*rx;
-#define SPI_TMP_BUFSZ	(SMP_CACHE_BYTES + 1)
-	u8			rx_tmp_buf[SPI_TMP_BUFSZ];
 	int			rcount;
 	int			wcount;
-	struct davinci_spi_dma	dma;
+
+	struct dma_chan		*dma_rx;
+	struct dma_chan		*dma_tx;
+	int			dma_rx_chnum;
+	int			dma_tx_chnum;
+
 	struct davinci_spi_platform_data *pdata;
 
 	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
@@ -496,21 +492,23 @@ out:
 	return errors;
 }
 
-static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
+static void davinci_spi_dma_rx_callback(void *data)
 {
-	struct davinci_spi *dspi = data;
-	struct davinci_spi_dma *dma = &dspi->dma;
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
 
-	edma_stop(lch);
+	dspi->rcount = 0;
 
-	if (status == DMA_COMPLETE) {
-		if (lch == dma->rx_channel)
-			dspi->rcount = 0;
-		if (lch == dma->tx_channel)
-			dspi->wcount = 0;
-	}
+	if (!dspi->wcount && !dspi->rcount)
+		complete(&dspi->done);
+}
 
-	if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
+static void davinci_spi_dma_tx_callback(void *data)
+{
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
+
+	dspi->wcount = 0;
+
+	if (!dspi->wcount && !dspi->rcount)
 		complete(&dspi->done);
 }
 
@@ -526,20 +524,20 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
 	struct davinci_spi *dspi;
-	int data_type, ret;
+	int data_type, ret = -ENOMEM;
 	u32 tx_data, spidat1;
 	u32 errors = 0;
 	struct davinci_spi_config *spicfg;
 	struct davinci_spi_platform_data *pdata;
 	unsigned uninitialized_var(rx_buf_count);
-	struct device *sdev;
+	void *dummy_buf = NULL;
+	struct scatterlist sg_rx, sg_tx;
 
 	dspi = spi_master_get_devdata(spi->master);
 	pdata = dspi->pdata;
 	spicfg = (struct davinci_spi_config *)spi->controller_data;
 	if (!spicfg)
 		spicfg = &davinci_spi_default_cfg;
-	sdev = dspi->bitbang.master->dev.parent;
 
 	/* convert len to words based on bits_per_word */
 	data_type = dspi->bytes_per_word[spi->chip_select];
@@ -567,112 +565,83 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 		spidat1 |= tx_data & 0xFFFF;
 		iowrite32(spidat1, dspi->base + SPIDAT1);
 	} else {
-		struct davinci_spi_dma *dma;
-		unsigned long tx_reg, rx_reg;
-		struct edmacc_param param;
-		void *rx_buf;
-		int b, c;
-
-		dma = &dspi->dma;
-
-		tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
-		rx_reg = (unsigned long)dspi->pbase + SPIBUF;
-
-		/*
-		 * Transmit DMA setup
-		 *
-		 * If there is transmit data, map the transmit buffer, set it
-		 * as the source of data and set the source B index to data
-		 * size. If there is no transmit data, set the transmit register
-		 * as the source of data, and set the source B index to zero.
-		 *
-		 * The destination is always the transmit register itself. And
-		 * the destination never increments.
-		 */
-
-		if (t->tx_buf) {
-			t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
-						t->len, DMA_TO_DEVICE);
-			if (dma_mapping_error(&spi->dev, t->tx_dma)) {
-				dev_dbg(sdev, "Unable to DMA map %d bytes"
-						"TX buffer\n", t->len);
-				return -ENOMEM;
-			}
-		}
-
-		/*
-		 * If number of words is greater than 65535, then we need
-		 * to configure a 3 dimension transfer.  Use the BCNTRLD
-		 * feature to allow for transfers that aren't even multiples
-		 * of 65535 (or any other possible b size) by first transferring
-		 * the remainder amount then grabbing the next N blocks of
-		 * 65535 words.
-		 */
-
-		c = dspi->wcount / (SZ_64K - 1);	/* N 65535 Blocks */
-		b = dspi->wcount - c * (SZ_64K - 1);	/* Remainder */
-		if (b)
-			c++;
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
+			.src_addr_width = data_type,
+			.src_maxburst = 1,
+		};
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
+			.dst_addr_width = data_type,
+			.dst_maxburst = 1,
+		};
+		struct dma_async_tx_descriptor *rxdesc;
+		struct dma_async_tx_descriptor *txdesc;
+		void *buf;
+
+		dummy_buf = kzalloc(t->len, GFP_KERNEL);
+		if (!dummy_buf)
+			goto err_alloc_dummy_buf;
+
+		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
+		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
+
+		sg_init_table(&sg_rx, 1);
+		if (!t->rx_buf)
+			buf = dummy_buf;
 		else
-			b = SZ_64K - 1;
-
-		param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
-		param.src = t->tx_buf ? t->tx_dma : tx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = tx_reg;
-		param.src_dst_bidx = t->tx_buf ? data_type : 0;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = t->tx_buf ? data_type : 0;
-		param.ccnt = c;
-		edma_write_slot(dma->tx_channel, &param);
-		edma_link(dma->tx_channel, dma->dummy_param_slot);
-
-		/*
-		 * Receive DMA setup
-		 *
-		 * If there is receive buffer, use it to receive data. If there
-		 * is none provided, use a temporary receive buffer. Set the
-		 * destination B index to 0 so effectively only one byte is used
-		 * in the temporary buffer (address does not increment).
-		 *
-		 * The source of receive data is the receive data register. The
-		 * source address never increments.
-		 */
-
-		if (t->rx_buf) {
-			rx_buf = t->rx_buf;
-			rx_buf_count = t->len;
-		} else {
-			rx_buf = dspi->rx_tmp_buf;
-			rx_buf_count = sizeof(dspi->rx_tmp_buf);
+			buf = t->rx_buf;
+		t->rx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->rx_dma) {
+			ret = -EFAULT;
+			goto err_rx_map;
 		}
+		sg_dma_address(&sg_rx) = t->rx_dma;
+		sg_dma_len(&sg_rx) = t->len;
 
-		t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
-							DMA_FROM_DEVICE);
-		if (dma_mapping_error(&spi->dev, t->rx_dma)) {
-			dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
-								rx_buf_count);
-			if (t->tx_buf)
-				dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-			return -ENOMEM;
+		sg_init_table(&sg_tx, 1);
+		if (!t->tx_buf)
+			buf = dummy_buf;
+		else
+			buf = (void *)t->tx_buf;
+		t->tx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->tx_dma) {
+			ret = -EFAULT;
+			goto err_tx_map;
 		}
-
-		param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
-		param.src = rx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = t->rx_dma;
-		param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16;
-		param.ccnt = c;
-		edma_write_slot(dma->rx_channel, &param);
+		sg_dma_address(&sg_tx) = t->tx_dma;
+		sg_dma_len(&sg_tx) = t->len;
+
+		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
+				&sg_rx, 1, DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!rxdesc)
+			goto err_desc;
+
+		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
+				&sg_tx, 1, DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!txdesc)
+			goto err_desc;
+
+		rxdesc->callback = davinci_spi_dma_rx_callback;
+		rxdesc->callback_param = (void *)dspi;
+		txdesc->callback = davinci_spi_dma_tx_callback;
+		txdesc->callback_param = (void *)dspi;
 
 		if (pdata->cshold_bug)
 			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
 
-		edma_start(dma->rx_channel);
-		edma_start(dma->tx_channel);
+		dmaengine_submit(rxdesc);
+		dmaengine_submit(txdesc);
+
+		dma_async_issue_pending(dspi->dma_rx);
+		dma_async_issue_pending(dspi->dma_tx);
+
 		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
 	}
 
@@ -690,15 +659,13 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 
 	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
 	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
-
-		if (t->tx_buf)
-			dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-
-		dma_unmap_single(&spi->dev, t->rx_dma, rx_buf_count,
-							DMA_FROM_DEVICE);
-
 		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
+
+		dma_unmap_single(&spi->dev, t->rx_dma,
+				t->len, DMA_FROM_DEVICE);
+		dma_unmap_single(&spi->dev, t->tx_dma,
+				t->len, DMA_TO_DEVICE);
+		kfree(dummy_buf);
 	}
 
 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
@@ -716,11 +683,20 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 	}
 
 	if (dspi->rcount != 0 || dspi->wcount != 0) {
-		dev_err(sdev, "SPI data transfer error\n");
+		dev_err(&spi->dev, "SPI data transfer error\n");
 		return -EIO;
 	}
 
 	return t->len;
+
+err_desc:
+	dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
+err_tx_map:
+	dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
+err_rx_map:
+	kfree(dummy_buf);
+err_alloc_dummy_buf:
+	return ret;
 }
 
 /**
@@ -751,39 +727,33 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *data)
 
 static int davinci_spi_request_dma(struct davinci_spi *dspi)
 {
+	dma_cap_mask_t mask;
+	struct device *sdev = dspi->bitbang.master->dev.parent;
 	int r;
-	struct davinci_spi_dma *dma = &dspi->dma;
 
-	r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI RX\n");
-		r = -EAGAIN;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_rx_chnum);
+	if (!dspi->dma_rx) {
+		dev_err(sdev, "request RX DMA channel failed\n");
+		r = -ENODEV;
 		goto rx_dma_failed;
 	}
 
-	r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI TX\n");
-		r = -EAGAIN;
+	dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_tx_chnum);
+	if (!dspi->dma_tx) {
+		dev_err(sdev, "request TX DMA channel failed\n");
+		r = -ENODEV;
 		goto tx_dma_failed;
 	}
 
-	r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
-	if (r < 0) {
-		pr_err("Unable to request SPI TX DMA param slot\n");
-		r = -EAGAIN;
-		goto param_failed;
-	}
-	dma->dummy_param_slot = r;
-	edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
-
 	return 0;
-param_failed:
-	edma_free_channel(dma->tx_channel);
+
 tx_dma_failed:
-	edma_free_channel(dma->rx_channel);
+	dma_release_channel(dspi->dma_rx);
 rx_dma_failed:
 	return r;
 }
@@ -898,9 +868,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
 	if (dma_rx_chan != SPI_NO_RESOURCE &&
 	    dma_tx_chan != SPI_NO_RESOURCE) {
-		dspi->dma.rx_channel = dma_rx_chan;
-		dspi->dma.tx_channel = dma_tx_chan;
-		dspi->dma.eventq = pdata->dma_event_q;
+		dspi->dma_rx_chnum = dma_rx_chan;
+		dspi->dma_tx_chnum = dma_tx_chan;
 
 		ret = davinci_spi_request_dma(dspi);
 		if (ret)
@@ -955,9 +924,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	return ret;
 
 free_dma:
-	edma_free_channel(dspi->dma.tx_channel);
-	edma_free_channel(dspi->dma.rx_channel);
-	edma_free_slot(dspi->dma.dummy_param_slot);
+	dma_release_channel(dspi->dma_rx);
+	dma_release_channel(dspi->dma_tx);
 free_clk:
 	clk_disable(dspi->clk);
 	clk_put(dspi->clk);
-- 
1.7.9.5



From mporter at ti.com  Thu Aug 16 17:44:29 2012
From: mporter at ti.com (Matt Porter)
Date: Thu, 16 Aug 2012 17:44:29 -0400
Subject: [PATCH 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345153471-22757-1-git-send-email-mporter@ti.com>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
Message-ID: <1345153471-22757-2-git-send-email-mporter@ti.com>

Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/dma/Kconfig  |    9 +
 drivers/dma/Makefile |    1 +
 drivers/dma/edma.c   |  729 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/edma.h |   29 ++
 4 files changed, 768 insertions(+)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..d9f17d4 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,15 @@ config SIRF_DMA
 	help
 	  Enable support for the CSR SiRFprimaII DMA engine.
 
+config TI_EDMA
+	tristate "TI EDMA support"
+	depends on ARCH_DAVINCI
+	select DMA_ENGINE
+	default y
+	help
+	  Enable support for the TI EDMA controller. This DMA
+	  engine is found on TI DaVinci and AM33xx parts.
+
 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 0000000..ba4de75
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,729 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <mach/edma.h>
+
+#include "dmaengine.h"
+
+#define EDMA_MAX_CHANNELS	64
+#define EDMA_DESCRIPTORS	16
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG		16
+#define EDMA_MAX_SLOTS		MAX_NR_SG
+
+struct edma_desc {
+	struct dma_async_tx_descriptor	txd;
+	struct list_head		node;
+
+	struct edmacc_param		pset[EDMA_MAX_SLOTS];
+	int				pset_nr;
+	int				absync;
+};
+
+struct edma_cc;
+
+struct edma_chan {
+	struct dma_chan			chan;
+	struct list_head		free;
+	struct list_head		prepared;
+	struct list_head		queued;
+	struct list_head		active;
+	struct list_head		completed;
+	struct tasklet_struct		work;
+
+	struct edma_cc			*ecc;
+	int				ch_num;
+	bool				alloced;
+	int				slot[EDMA_MAX_SLOTS];
+
+	dma_addr_t			addr;
+	int				addr_width;
+	int				maxburst;
+
+	/* Lock for this structure */
+	spinlock_t			lock;
+};
+
+/* EDMA channel controller */
+struct edma_cc {
+	struct dma_device		dma_slave;
+	struct edma_chan		slave_chans[EDMA_MAX_CHANNELS];
+	int				num_slave_chans;
+	int				dummy_slot[2];
+};
+
+/* Convert struct dma_chan to struct edma_chan */
+static inline
+struct edma_chan *to_edma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct edma_chan, chan);
+}
+
+/* Dispatch a queued descriptor to the controller (caller holds lock) */
+static void edma_execute(struct edma_chan *echan)
+{
+	struct edma_desc *edesc = NULL;
+	int i;
+
+	/* Move the first queued descriptor to active list */
+	edesc = list_first_entry(&echan->queued, struct edma_desc,
+		node);
+	list_move_tail(&edesc->node, &echan->active);
+
+	/* Write descriptor PaRAM set(s) */
+	for (i = 0; i < edesc->pset_nr; i++) {
+		edma_write_slot(echan->slot[i], &edesc->pset[i]);
+		dev_dbg(echan->chan.device->dev,
+			"\n pset[%d]:\n"
+			"  chnum\t%d\n"
+			"  slot\t%d\n"
+			"  opt\t%08x\n"
+			"  src\t%08x\n"
+			"  dst\t%08x\n"
+			"  abcnt\t%08x\n"
+			"  ccnt\t%08x\n"
+			"  bidx\t%08x\n"
+			"  cidx\t%08x\n"
+			"  lkrld\t%08x\n",
+			i, echan->ch_num, echan->slot[i],
+			edesc->pset[i].opt,
+			edesc->pset[i].src,
+			edesc->pset[i].dst,
+			edesc->pset[i].a_b_cnt,
+			edesc->pset[i].ccnt,
+			edesc->pset[i].src_dst_bidx,
+			edesc->pset[i].src_dst_cidx,
+			edesc->pset[i].link_bcntrld);
+		/* Link to the previous slot if not the last set */
+		if (i != (edesc->pset_nr - 1))
+			edma_link(echan->slot[i], echan->slot[i+1]);
+		/* Final pset links to the dummy pset */
+		else
+			edma_link(echan->slot[i],
+				echan->ecc->dummy_slot[
+				EDMA_CTLR(echan->ch_num)]);
+	}
+
+	edma_start(echan->ch_num);
+}
+
+/* Process completed descriptors */
+static void edma_process_completed(struct edma_chan *echan)
+{
+	struct edma_desc *edesc;
+	struct dma_async_tx_descriptor *txd;
+	unsigned long flags;
+	LIST_HEAD(list);
+
+	/* Get all completed descriptors */
+	if (!list_empty(&echan->completed)) {
+		spin_lock_irqsave(&echan->lock, flags);
+		list_splice_tail_init(&echan->completed, &list);
+		spin_unlock_irqrestore(&echan->lock, flags);
+
+		/* Execute callbacks and run dependencies */
+		list_for_each_entry(edesc, &list, node) {
+			txd = &edesc->txd;
+
+			dma_cookie_complete(txd);
+
+			if (txd->callback)
+				txd->callback(txd->callback_param);
+
+			dma_run_dependencies(txd);
+		}
+
+		/* Free descriptors */
+		spin_lock_irqsave(&echan->lock, flags);
+		list_splice_tail_init(&list, &echan->free);
+		spin_unlock_irqrestore(&echan->lock, flags);
+	}
+}
+
+/* EDMA tasklet */
+static void edma_work(unsigned long data)
+{
+	struct edma_chan *echan = (void *)data;
+
+	edma_process_completed(echan);
+}
+
+/* Queue descriptor for processing */
+static dma_cookie_t edma_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+	struct edma_chan *echan = to_edma_chan(txd->chan);
+	struct edma_desc *edesc;
+	dma_cookie_t cookie;
+	unsigned long flags;
+
+	edesc = container_of(txd, struct edma_desc, txd);
+
+	spin_lock_irqsave(&echan->lock, flags);
+
+	/* Assign a cookie and queue it */
+	cookie = dma_cookie_assign(&edesc->txd);
+	list_move_tail(&edesc->node, &echan->queued);
+
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	return cookie;
+}
+
+static int edma_slave_config(struct edma_chan *echan,
+	struct dma_slave_config *config)
+{
+	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+		return -EINVAL;
+
+	if (config->direction == DMA_MEM_TO_DEV) {
+		if (config->dst_addr)
+			echan->addr = config->dst_addr;
+		if (config->dst_addr_width)
+			echan->addr_width = config->dst_addr_width;
+		if (config->dst_maxburst)
+			echan->maxburst = config->dst_maxburst;
+	} else if (config->direction == DMA_DEV_TO_MEM) {
+		if (config->src_addr)
+			echan->addr = config->src_addr;
+		if (config->src_addr_width)
+			echan->addr_width = config->src_addr_width;
+		if (config->src_maxburst)
+			echan->maxburst = config->src_maxburst;
+	}
+
+	return 0;
+}
+
+static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			unsigned long arg)
+{
+	int ret = 0;
+	struct dma_slave_config *config;
+	struct edma_chan *echan = to_edma_chan(chan);
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		edma_stop(echan->ch_num);
+		break;
+	case DMA_SLAVE_CONFIG:
+		config = (struct dma_slave_config *)arg;
+		ret = edma_slave_config(echan, config);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	return ret;
+}
+
+static struct dma_async_tx_descriptor *edma_prep_slave_sg(
+	struct dma_chan *chan, struct scatterlist *sgl,
+	unsigned int sg_len, enum dma_transfer_direction direction,
+	unsigned long dma_flags, void *context)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = echan->chan.device->dev;
+	struct edma_desc *edesc = NULL;
+	struct scatterlist *sg;
+	unsigned long flags;
+	int i;
+	int acnt, bcnt, ccnt, src, dst, cidx;
+	int src_bidx, dst_bidx, src_cidx, dst_cidx;
+
+	if (unlikely(!echan || !sgl || !sg_len))
+		return NULL;
+
+	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
+		dev_err(dev, "Undefined slave buswidth\n");
+		return NULL;
+	}
+
+	if (sg_len > MAX_NR_SG) {
+		dev_err(dev, "Exceeded max SG segments %d > %d\n",
+			sg_len, MAX_NR_SG);
+		return NULL;
+	}
+
+	spin_lock_irqsave(&echan->lock, flags);
+	/* Get free descriptor */
+	if (!list_empty(&echan->free)) {
+		edesc = list_first_entry(&echan->free,
+				struct edma_desc, node);
+		list_del_init(&edesc->node);
+	}
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	if (!edesc) {
+		dev_dbg(dev, "Out of descriptors for channel %d",
+			echan->ch_num);
+		/* Try to free completed descriptors */
+		edma_process_completed(echan);
+		return NULL;
+	}
+
+	edesc->pset_nr = sg_len;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		/* Allocate a PaRAM slot, if needed */
+		if (echan->slot[i] < 0) {
+			echan->slot[i] =
+				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
+						EDMA_SLOT_ANY);
+			if (echan->slot[i] < 0) {
+				dev_err(dev, "Failed to allocate slot\n");
+				return NULL;
+			}
+		}
+
+		acnt = echan->addr_width;
+
+		/*
+		 * If the maxburst is equal to the fifo width, use
+		 * A-synced transfers. This allows for large contiguous
+		 * buffer transfers using only one PaRAM set.
+		 */
+		if (echan->maxburst == 1) {
+			edesc->absync = false;
+			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
+			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
+			if (bcnt)
+				ccnt++;
+			else
+				bcnt = SZ_64K - 1;
+			cidx = acnt;
+		/*
+		 * If maxburst is greater than the fifo address_width,
+		 * use AB-synced transfers where A count is the fifo
+		 * address_width and B count is the maxburst. In this
+		 * case, we are limited to transfers of C count frames
+		 * of (address_width * maxburst) where C count is limited
+		 * to SZ_64K-1. This places an upper bound on the length
+		 * of an SG segment that can be handled.
+		 */
+		} else {
+			edesc->absync = true;
+			bcnt = echan->maxburst;
+			ccnt = sg_dma_len(sg) / (acnt * bcnt);
+			if (ccnt > (SZ_64K - 1)) {
+				dev_err(dev, "Exceeded max SG segment size\n");
+				return NULL;
+			}
+			cidx = acnt * bcnt;
+		}
+
+		if (direction == DMA_MEM_TO_DEV) {
+			src = sg_dma_address(sg);
+			dst = echan->addr;
+			src_bidx = acnt;
+			src_cidx = cidx;
+			dst_bidx = 0;
+			dst_cidx = 0;
+		} else {
+			src = echan->addr;
+			dst = sg_dma_address(sg);
+			src_bidx = 0;
+			src_cidx = 0;
+			dst_bidx = acnt;
+			dst_cidx = cidx;
+		}
+
+		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
+		/* Configure A or AB synchronized transfers */
+		if (edesc->absync)
+			edesc->pset[i].opt |= SYNCDIM;
+		/* If this is the last set, enable completion interrupt flag */
+		if (i == sg_len - 1)
+			edesc->pset[i].opt |= TCINTEN;
+
+		edesc->pset[i].src = src;
+		edesc->pset[i].dst = dst;
+
+		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
+		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
+
+		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
+		edesc->pset[i].ccnt = ccnt;
+		edesc->pset[i].link_bcntrld = 0xffffffff;
+
+	}
+	edesc->txd.flags = dma_flags;
+
+	/* Place descriptor in prepared list */
+	spin_lock_irqsave(&echan->lock, flags);
+	list_add_tail(&edesc->node, &echan->prepared);
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	return &edesc->txd;
+}
+
+static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
+{
+	struct edma_chan *echan = to_edma_chan((struct dma_chan *)data);
+	struct device *dev = echan->chan.device->dev;
+	struct edma_desc *edesc = NULL;
+
+	/* Stop the channel */
+	edma_stop(echan->ch_num);
+
+	switch (ch_status) {
+	case DMA_COMPLETE:
+		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
+
+		spin_lock(&echan->lock);
+
+		/* Grab the first active descriptor */
+		edesc = list_first_entry(&echan->active, struct edma_desc,
+			node);
+
+		/* Mark the descriptor completed */
+		list_move_tail(&edesc->node, &echan->completed);
+
+		/* Execute queued descriptors */
+		if (!list_empty(&echan->queued)) {
+			dev_dbg(dev, "descriptor queued on channel %d\n",
+				ch_num);
+			edma_execute(echan);
+		}
+
+		spin_unlock(&echan->lock);
+
+		/* Schedule work */
+		tasklet_schedule(&echan->work);
+
+		break;
+	case DMA_CC_ERROR:
+		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Alloc channel resources */
+static int edma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = echan->chan.device->dev;
+	struct edma_desc *edesc;
+	int ret;
+	int a_ch_num;
+	LIST_HEAD(descs);
+	int i;
+	unsigned long flags;
+
+	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
+					chan, EVENTQ_DEFAULT);
+
+	if (a_ch_num < 0) {
+		ret = -ENODEV;
+		goto err_no_chan;
+	}
+
+	if (a_ch_num != echan->ch_num) {
+		dev_err(dev, "failed to allocate requested channel %d\n",
+			echan->ch_num);
+		ret = -ENODEV;
+		goto err_wrong_chan;
+	}
+
+	dma_cookie_init(&echan->chan);
+	echan->alloced = true;
+	echan->slot[0] = echan->ch_num;
+
+	/* Alloc descriptors for this channel */
+	for (i = 0; i < EDMA_DESCRIPTORS; i++) {
+		edesc = kzalloc(sizeof(*edesc), GFP_KERNEL);
+		if (!edesc) {
+			dev_notice(dev,
+				"allocated only %u descriptors\n", i);
+			break;
+		}
+
+		dma_async_tx_descriptor_init(&edesc->txd, chan);
+		edesc->txd.flags = DMA_CTRL_ACK;
+		edesc->txd.tx_submit = edma_tx_submit;
+
+		list_add_tail(&edesc->node, &descs);
+	}
+
+	/* Return error only if no descriptors were allocated */
+	if (i == 0) {
+		ret = -ENOMEM;
+		goto err_alloc_desc;
+	}
+
+	spin_lock_irqsave(&echan->lock, flags);
+
+	list_splice_tail_init(&descs, &echan->free);
+
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	return 0;
+
+err_alloc_desc:
+err_wrong_chan:
+	edma_free_channel(a_ch_num);
+err_no_chan:
+	return ret;
+}
+
+/* Free channel resources */
+static void edma_free_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct edma_desc *edesc, *tmp;
+	unsigned long flags;
+	LIST_HEAD(descs);
+	int i;
+
+	/* Terminate transfers */
+	edma_stop(echan->ch_num);
+
+	spin_lock_irqsave(&echan->lock, flags);
+
+	/* Channel must be idle */
+	BUG_ON(!list_empty(&echan->prepared));
+	BUG_ON(!list_empty(&echan->queued));
+	BUG_ON(!list_empty(&echan->active));
+	BUG_ON(!list_empty(&echan->completed));
+
+	list_splice_tail_init(&echan->free, &descs);
+
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	/* Free descriptors */
+	list_for_each_entry_safe(edesc, tmp, &descs, node)
+		kfree(edesc);
+
+	/* Free EDMA PaRAM slots */
+	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
+		if (echan->slot[i] >= 0) {
+			edma_free_slot(echan->slot[i]);
+			echan->slot[i] = -1;
+		}
+	}
+
+	/* Free EDMA channel */
+	if (echan->alloced) {
+		edma_free_channel(echan->ch_num);
+		echan->alloced = false;
+	}
+}
+
+/* Send pending descriptor to hardware */
+static void edma_issue_pending(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&echan->lock, flags);
+
+	if (list_empty(&echan->active) && !list_empty(&echan->queued))
+		edma_execute(echan);
+
+	spin_unlock_irqrestore(&echan->lock, flags);
+}
+
+/* Check request completion status */
+static enum dma_status edma_tx_status(struct dma_chan *chan,
+				      dma_cookie_t cookie,
+				      struct dma_tx_state *txstate)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	unsigned long flags;
+	enum dma_status ret;
+
+	spin_lock_irqsave(&echan->lock, flags);
+	ret = dma_cookie_status(chan, cookie, txstate);
+	spin_unlock_irqrestore(&echan->lock, flags);
+
+	return ret;
+}
+
+static void __init edma_chan_init(struct edma_cc *ecc,
+				  struct dma_device *dma,
+				  struct edma_chan *echans)
+{
+	int i, j;
+	int chcnt = 0;
+
+	INIT_LIST_HEAD(&dma->channels);
+
+	for (i = 0; i < EDMA_MAX_CHANNELS; i++) {
+		struct edma_chan *echan = &echans[chcnt];
+		echan->ch_num = i;
+		echan->ecc = ecc;
+		echan->chan.device = dma;
+		for (j = 0; j < EDMA_MAX_SLOTS; j++)
+			echan->slot[j] = -1;
+
+		spin_lock_init(&echan->lock);
+
+		INIT_LIST_HEAD(&echan->free);
+		INIT_LIST_HEAD(&echan->prepared);
+		INIT_LIST_HEAD(&echan->queued);
+		INIT_LIST_HEAD(&echan->active);
+		INIT_LIST_HEAD(&echan->completed);
+
+		tasklet_init(&echan->work, edma_work, (unsigned long)echan);
+
+		list_add_tail(&echan->chan.device_node, &dma->channels);
+
+		chcnt++;
+	}
+}
+
+static void edma_ops_init(struct edma_cc *ecc, struct dma_device *dma,
+			  struct device *dev)
+{
+	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
+		dma->device_prep_slave_sg = edma_prep_slave_sg;
+
+	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
+	dma->device_free_chan_resources = edma_free_chan_resources;
+	dma->device_issue_pending = edma_issue_pending;
+	dma->device_tx_status = edma_tx_status;
+	dma->device_control = edma_control;
+	dma->dev = dev;
+}
+
+static int __devinit edma_probe(struct platform_device *pdev)
+{
+	struct edma_cc *ecc;
+	int ret;
+
+	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
+	if (!ecc) {
+		dev_err(&pdev->dev, "Can't allocate controller\n");
+		ret = -ENOMEM;
+		goto err_alloc_ecc;
+	}
+
+	ecc->dummy_slot[0] = edma_alloc_slot(0, EDMA_SLOT_ANY);
+	if (ecc->dummy_slot[0] < 0) {
+		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
+		ret = -EIO;
+		goto err_alloc_slot0;
+	}
+
+	ecc->dummy_slot[1] = edma_alloc_slot(1, EDMA_SLOT_ANY);
+	if (ecc->dummy_slot[1] < 0) {
+		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
+		ret = -EIO;
+		goto err_alloc_slot1;
+	}
+
+	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
+
+	dma_cap_zero(ecc->dma_slave.cap_mask);
+	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
+
+	edma_ops_init(ecc, &ecc->dma_slave, &pdev->dev);
+
+	ret = dma_async_device_register(&ecc->dma_slave);
+	if (ret)
+		goto err_reg1;
+
+	platform_set_drvdata(pdev, ecc);
+
+	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
+
+	return 0;
+
+err_reg1:
+	edma_free_slot(ecc->dummy_slot[1]);
+err_alloc_slot1:
+	edma_free_slot(ecc->dummy_slot[0]);
+err_alloc_slot0:
+	devm_kfree(&pdev->dev, ecc);
+err_alloc_ecc:
+	return ret;
+}
+
+static int __devexit edma_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct edma_cc *ecc = dev_get_drvdata(dev);
+
+	dma_async_device_unregister(&ecc->dma_slave);
+	edma_free_slot(ecc->dummy_slot[0]);
+	edma_free_slot(ecc->dummy_slot[1]);
+	devm_kfree(dev, ecc);
+
+	return 0;
+}
+
+static struct platform_driver edma_driver = {
+	.probe		= edma_probe,
+	.remove		= __devexit_p(edma_remove),
+	.driver = {
+		.name = "edma-dma-engine",
+		.owner = THIS_MODULE,
+	},
+};
+
+bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	if (chan->device->dev->driver == &edma_driver.driver) {
+		struct edma_chan *echan = to_edma_chan(chan);
+		unsigned ch_req = *(unsigned *)param;
+		return ch_req == echan->ch_num;
+	}
+	return false;
+}
+EXPORT_SYMBOL(edma_filter_fn);
+
+static struct platform_device *pdev;
+
+static const struct platform_device_info edma_dev_info = {
+	.name = "edma-dma-engine",
+	.id = -1,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
+static int edma_init(void)
+{
+	int ret = platform_driver_register(&edma_driver);
+
+	if (ret == 0) {
+		pdev = platform_device_register_full(&edma_dev_info);
+		if (IS_ERR(pdev)) {
+			platform_driver_unregister(&edma_driver);
+			ret = PTR_ERR(pdev);
+		}
+	}
+	return ret;
+}
+subsys_initcall(edma_init);
+
+static void __exit edma_exit(void)
+{
+	platform_device_unregister(pdev);
+	platform_driver_unregister(&edma_driver);
+}
+module_exit(edma_exit);
+
+MODULE_AUTHOR("Matt Porter <mporter at ti.com>");
+MODULE_DESCRIPTION("TI EDMA DMA engine driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/edma.h b/include/linux/edma.h
new file mode 100644
index 0000000..a1307e7
--- /dev/null
+++ b/include/linux/edma.h
@@ -0,0 +1,29 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_EDMA_H
+#define __LINUX_EDMA_H
+
+struct dma_chan;
+
+#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
+bool edma_filter_fn(struct dma_chan *, void *);
+#else
+static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	return false;
+}
+#endif
+
+#endif
-- 
1.7.9.5



From mporter at ti.com  Thu Aug 16 17:44:30 2012
From: mporter at ti.com (Matt Porter)
Date: Thu, 16 Aug 2012 17:44:30 -0400
Subject: [PATCH 2/3] mmc: davinci_mmc: convert to DMA engine API
In-Reply-To: <1345153471-22757-1-git-send-email-mporter@ti.com>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
Message-ID: <1345153471-22757-3-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/mmc/host/davinci_mmc.c |  271 ++++++++++++----------------------------
 1 file changed, 82 insertions(+), 189 deletions(-)

diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 7cf6c62..c5e1eeb 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -30,11 +30,12 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/mmc/mmc.h>
 
 #include <mach/mmc.h>
-#include <mach/edma.h>
 
 /*
  * Register Definitions
@@ -200,21 +201,13 @@ struct mmc_davinci_host {
 	u32 bytes_left;
 
 	u32 rxdma, txdma;
+	struct dma_chan *dma_tx;
+	struct dma_chan *dma_rx;
 	bool use_dma;
 	bool do_dma;
 	bool sdio_int;
 	bool active_request;
 
-	/* Scatterlist DMA uses one or more parameter RAM entries:
-	 * the main one (associated with rxdma or txdma) plus zero or
-	 * more links.  The entries for a given transfer differ only
-	 * by memory buffer (address, length) and link field.
-	 */
-	struct edmacc_param	tx_template;
-	struct edmacc_param	rx_template;
-	unsigned		n_link;
-	u32			links[MAX_NR_SG - 1];
-
 	/* For PIO we walk scatterlists one segment at a time. */
 	unsigned int		sg_len;
 	struct scatterlist *sg;
@@ -410,153 +403,74 @@ static void mmc_davinci_start_command(struct mmc_davinci_host *host,
 
 static void davinci_abort_dma(struct mmc_davinci_host *host)
 {
-	int sync_dev;
+	struct dma_chan *sync_dev;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
-		sync_dev = host->rxdma;
+		sync_dev = host->dma_rx;
 	else
-		sync_dev = host->txdma;
-
-	edma_stop(sync_dev);
-	edma_clean_channel(sync_dev);
-}
-
-static void
-mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
-
-static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
-{
-	if (DMA_COMPLETE != ch_status) {
-		struct mmc_davinci_host *host = data;
-
-		/* Currently means:  DMA Event Missed, or "null" transfer
-		 * request was seen.  In the future, TC errors (like bad
-		 * addresses) might be presented too.
-		 */
-		dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
-			(host->data->flags & MMC_DATA_WRITE)
-				? "write" : "read");
-		host->data->error = -EIO;
-		mmc_davinci_xfer_done(host, host->data);
-	}
-}
-
-/* Set up tx or rx template, to be modified and updated later */
-static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
-		bool tx, struct edmacc_param *template)
-{
-	unsigned	sync_dev;
-	const u16	acnt = 4;
-	const u16	bcnt = rw_threshold >> 2;
-	const u16	ccnt = 0;
-	u32		src_port = 0;
-	u32		dst_port = 0;
-	s16		src_bidx, dst_bidx;
-	s16		src_cidx, dst_cidx;
-
-	/*
-	 * A-B Sync transfer:  each DMA request is for one "frame" of
-	 * rw_threshold bytes, broken into "acnt"-size chunks repeated
-	 * "bcnt" times.  Each segment needs "ccnt" such frames; since
-	 * we tell the block layer our mmc->max_seg_size limit, we can
-	 * trust (later) that it's within bounds.
-	 *
-	 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
-	 * EDMA will optimize memory operations to use larger bursts.
-	 */
-	if (tx) {
-		sync_dev = host->txdma;
-
-		/* src_prt, ccnt, and link to be set up later */
-		src_bidx = acnt;
-		src_cidx = acnt * bcnt;
-
-		dst_port = host->mem_res->start + DAVINCI_MMCDXR;
-		dst_bidx = 0;
-		dst_cidx = 0;
-	} else {
-		sync_dev = host->rxdma;
-
-		src_port = host->mem_res->start + DAVINCI_MMCDRR;
-		src_bidx = 0;
-		src_cidx = 0;
-
-		/* dst_prt, ccnt, and link to be set up later */
-		dst_bidx = acnt;
-		dst_cidx = acnt * bcnt;
-	}
-
-	/*
-	 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
-	 * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
-	 * parameter is ignored.
-	 */
-	edma_set_src(sync_dev, src_port, INCR, W8BIT);
-	edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
+		sync_dev = host->dma_tx;
 
-	edma_set_src_index(sync_dev, src_bidx, src_cidx);
-	edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
-
-	edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
-
-	edma_read_slot(sync_dev, template);
-
-	/* don't bother with irqs or chaining */
-	template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
+	dmaengine_terminate_all(sync_dev);
 }
 
-static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
+static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
 		struct mmc_data *data)
 {
-	struct edmacc_param	*template;
-	int			channel, slot;
-	unsigned		link;
-	struct scatterlist	*sg;
-	unsigned		sg_len;
-	unsigned		bytes_left = host->bytes_left;
-	const unsigned		shift = ffs(rw_threshold) - 1;
+	struct dma_chan *chan;
+	struct dma_async_tx_descriptor *desc;
+	int ret = 0;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
-		template = &host->tx_template;
-		channel = host->txdma;
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
+			.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.dst_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_tx;
+		dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_tx,
+				data->sg,
+				host->sg_len,
+				DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA TX descriptor");
+			ret = -1;
+			goto out;
+		}
 	} else {
-		template = &host->rx_template;
-		channel = host->rxdma;
-	}
-
-	/* We know sg_len and ccnt will never be out of range because
-	 * we told the mmc layer which in turn tells the block layer
-	 * to ensure that it only hands us one scatterlist segment
-	 * per EDMA PARAM entry.  Update the PARAM
-	 * entries needed for each segment of this scatterlist.
-	 */
-	for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
-			sg_len-- != 0 && bytes_left;
-			sg = sg_next(sg), slot = host->links[link++]) {
-		u32		buf = sg_dma_address(sg);
-		unsigned	count = sg_dma_len(sg);
-
-		template->link_bcntrld = sg_len
-				? (EDMA_CHAN_SLOT(host->links[link]) << 5)
-				: 0xffff;
-
-		if (count > bytes_left)
-			count = bytes_left;
-		bytes_left -= count;
-
-		if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
-			template->src = buf;
-		else
-			template->dst = buf;
-		template->ccnt = count >> shift;
-
-		edma_write_slot(slot, template);
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = host->mem_res->start + DAVINCI_MMCDRR,
+			.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.src_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_rx;
+		dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_rx,
+				data->sg,
+				host->sg_len,
+				DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA RX descriptor");
+			ret = -1;
+			goto out;
+		}
 	}
 
-	if (host->version == MMC_CTLR_VERSION_2)
-		edma_clear_event(channel);
+	dmaengine_submit(desc);
+	dma_async_issue_pending(chan);
 
-	edma_start(channel);
+out:
+	return ret;
 }
 
 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
@@ -564,6 +478,7 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 {
 	int i;
 	int mask = rw_threshold - 1;
+	int ret = 0;
 
 	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 				((data->flags & MMC_DATA_WRITE)
@@ -583,70 +498,48 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 	}
 
 	host->do_dma = 1;
-	mmc_davinci_send_dma_request(host, data);
+	ret = mmc_davinci_send_dma_request(host, data);
 
-	return 0;
+	return ret;
 }
 
 static void __init_or_module
 davinci_release_dma_channels(struct mmc_davinci_host *host)
 {
-	unsigned	i;
-
 	if (!host->use_dma)
 		return;
 
-	for (i = 0; i < host->n_link; i++)
-		edma_free_slot(host->links[i]);
-
-	edma_free_channel(host->txdma);
-	edma_free_channel(host->rxdma);
+	dma_release_channel(host->dma_tx);
+	dma_release_channel(host->dma_rx);
 }
 
 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
 {
-	u32 link_size;
-	int r, i;
-
-	/* Acquire master DMA write channel */
-	r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"tx", r);
-		return r;
-	}
-	mmc_davinci_dma_setup(host, true, &host->tx_template);
-
-	/* Acquire master DMA read channel */
-	r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"rx", r);
-		goto free_master_write;
+	int r;
+	dma_cap_mask_t mask;
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	host->dma_tx =
+		dma_request_channel(mask, edma_filter_fn, &host->txdma);
+	if (!host->dma_tx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
+		return -ENODEV;
 	}
-	mmc_davinci_dma_setup(host, false, &host->rx_template);
 
-	/* Allocate parameter RAM slots, which will later be bound to a
-	 * channel as needed to handle a scatterlist.
-	 */
-	link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
-	for (i = 0; i < link_size; i++) {
-		r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
-		if (r < 0) {
-			dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
-				r);
-			break;
-		}
-		host->links[i] = r;
+	host->dma_rx =
+		dma_request_channel(mask, edma_filter_fn, &host->rxdma);
+	if (!host->dma_rx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
+		r = -ENODEV;
+		goto free_master_write;
 	}
-	host->n_link = i;
 
 	return 0;
 
 free_master_write:
-	edma_free_channel(host->txdma);
+	dma_release_channel(host->dma_tx);
 
 	return r;
 }
@@ -1359,7 +1252,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 	 * Each hw_seg uses one EDMA parameter RAM slot, always one
 	 * channel and then usually some linked slots.
 	 */
-	mmc->max_segs		= 1 + host->n_link;
+	mmc->max_segs		= MAX_NR_SG;
 
 	/* EDMA limit per hw segment (one or two MBytes) */
 	mmc->max_seg_size	= MAX_CCNT * rw_threshold;
-- 
1.7.9.5



From andrew at lunn.ch  Thu Aug 16 18:10:00 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 17 Aug 2012 00:10:00 +0200
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <CADhrpJ7geSRc3pow-DQWiA3rZ=f0i2WSws_QuKSDk7uZx1VSRQ@mail.gmail.com>
References: <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
 <20120815234159.GK22226@titan.lakedaemon.net>
 <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>
 <CADhrpJ5UF6r2N027nOS6xmJtu21UbDxfzLninCZ7O-A+G3ALgg@mail.gmail.com>
 <CADhrpJ7geSRc3pow-DQWiA3rZ=f0i2WSws_QuKSDk7uZx1VSRQ@mail.gmail.com>
Message-ID: <20120816221000.GG18145@lunn.ch>

> the problem seems to be in this comming from this line:
> 
> button->gpio = of_get_gpio_flags(pp, 0, &flags);
> 
> in the function :
> 
> /*
>  * Translate OpenFirmware node properties into platform_data
>  */
> static struct gpio_keys_platform_data * __devinit
> 
> of the gpio_keys.c file or whatever that line links to. It does not
> know how to deal with some NULL reference as far as i can tell.

Do you mean this piece of code:

       while ((pp = of_get_next_child(node, pp))) {
                enum of_gpio_flags flags;

                if (!of_find_property(pp, "gpios", NULL)) {
                        pdata->nbuttons--;
                        dev_warn(dev, "Found button without gpios\n");
                        continue;
                }
                buttons[i].gpio = of_get_gpio_flags(pp, 0, &flags);

This would fit with:

[    5.981782] Unable to handle kernel NULL pointer dereference at
virtual address 00000004
  
since gpio is at offset 4 in buttons. What is the value of i when it
oppses? What is buttons[i]?

	Andrew


From andi at firstfloor.org  Thu Aug 16 18:17:58 2012
From: andi at firstfloor.org (Andi Kleen)
Date: Fri, 17 Aug 2012 00:17:58 +0200
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <CAPkEcwgv6f5B+Mrw7kzrHcZ5JZ+Yr0o=bLdoFqCB-e4CLiVx5A@mail.gmail.com>
References: <50299142.2030504@oberhumer.com>
 <20120814123937.GA14756@sig21.net> <502B8FE3.7080501@oberhumer.com>
 <20120815144539.GA8300@sig21.net> <502C92C3.7090701@oberhumer.com>
 <20120816150647.GA22010@sig21.net> <20120816232549.4d14a6aa@natsu>
 <20120816175234.GL11413@one.firstfloor.org>
 <CAMuHMdWK_Y=QwkgQD6K8tFBLaO04Fy0yVAzEpb2OYW6Ec0hGoA@mail.gmail.com>
 <CAPkEcwgv6f5B+Mrw7kzrHcZ5JZ+Yr0o=bLdoFqCB-e4CLiVx5A@mail.gmail.com>
Message-ID: <20120816221758.GM11413@one.firstfloor.org>

On Thu, Aug 16, 2012 at 11:55:06AM -0700, james northrup wrote:
> looks like ARM results are inconclusive from a lot of folks without
> bandwidth to do a write-up, what about just plain STAGING status for ARM so
> the android tweakers can beat on it for a while?

Staging only really works for new drivers, not for updating existing
library functions like this.

I suppose you could keep both and have the architecture select with a
CONFIG.

-Andi


From linux at arm.linux.org.uk  Thu Aug 16 18:29:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 Aug 2012 23:29:12 +0100
Subject: [PATCH 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345153471-22757-2-git-send-email-mporter@ti.com>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
 <1345153471-22757-2-git-send-email-mporter@ti.com>
Message-ID: <20120816222912.GA15883@n2100.arm.linux.org.uk>

On Thu, Aug 16, 2012 at 05:44:29PM -0400, Matt Porter wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.

Have you looked at the virt-dma support?  That should allow you to
avoid some common errors, like forgetting that stuff submitted but
not issued should not be started even if the channel is currently
running.


From linux at arm.linux.org.uk  Thu Aug 16 18:34:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 16 Aug 2012 23:34:46 +0100
Subject: imx6q restart is broken
In-Reply-To: <20120816023109.GH2258@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk> <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
 <20120816023109.GH2258@S2101-09.ap.freescale.net>
Message-ID: <20120816223446.GB15883@n2100.arm.linux.org.uk>

On Thu, Aug 16, 2012 at 10:31:11AM +0800, Shawn Guo wrote:
> On Wed, Aug 15, 2012 at 10:44:12PM +0100, Russell King - ARM Linux wrote:
> > On Wed, Aug 15, 2012 at 10:07:47AM -0500, Rob Herring wrote:
> > > I think I am seeing a similar problem on highbank with a v7 only build.
> > > 
> > > >From what I've debugged, restart hangs for me on the L2x0 spinlock
> > > during a writel. Changing the writel to writel_relaxed in the restart
> > > hook fixes the problem. This skips barriers in the writel and for the
> > > spinlock. However, I'm still puzzled as cpu_relax on the secondary cores
> > > should not be doing a dmb in my case on a v7 only build.
> > 
> > Well, I had the idea of only doing a dmb() once every N loops, but I don't
> > think we can sensibly introduce such a change into the mainline kernel.
> > (How would cpu_relax() know it's being used in a loop?)
> > 
> > Remember that the dmb() is in cpu_relax() as a work-around for the lack
> > of temporal flushing of pending stores, and is needed to make various bits
> > of the kernel work.
> > 
> The cpu_relax() will do dmb() only #if __LINUX_ARM_ARCH__ == 6 ||
> defined(CONFIG_ARM_ERRATA_754327).  Otherwise, it's just a barrier()
> call.  I guess Rob's puzzle is since the cpu_relax on the stopped
> cores does not do dmb, why a wmb/mb call on the running cpu would hang
> it.
> 
> One thing I note is that mb() will do a outer_sync() call.  Since the
> issue is around L2x0 operation, not sure if they are related ...

This doesn't get around the problem that userspace can still effectively
issue a DoS against the system by just running a dmb in a tight loop.
Or maybe this would have a much more dramatic effect:

	while (1) {
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
		asm("dmb");
	}

and make that 3 seconds to get a ps listing turn into something much
longer?

> > So at the moment, there is no solution for this - and as I've pointed out
> > it can be trivially exploited in userspace on the affected CPUs.  So
> > really a kernel work-around isn't going to sort it.
> 
> So, Sascha, it seems we get another good reason to split
> imx_v6_v7_defconfig into imx_v6_defconfig and imx_v7_defconfig?
> I have seen Matt Sealey and Hui Wang suggested doing this already.

The last thing we need are more defconfigs.

I think what needs to happen here (while we wait) is someone _with_ the
problem needs to experiment, and find out how many nops are needed for
the DMB not to have much effect in cpu_relax().  If it turns out we just
need to put one nop in, then that's not _too_ bad.


From festevam at gmail.com  Thu Aug 16 20:03:11 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 16 Aug 2012 21:03:11 -0300
Subject: PATCH Add support for the Iomega IX2-200 Device Tree
In-Reply-To: <20120816221000.GG18145@lunn.ch>
References: <20120815215237.GF15830@lunn.ch>
 <CADhrpJ7ANwD4asN4-D9OeicGA_V5-9DZoV9G6dDFZ9taN7AZsg@mail.gmail.com>
 <20120815221613.GH15830@lunn.ch>
 <CADhrpJ66ncpT74ATyvJDXTuJC-zrmh8vQ99RPg0t=XuQ_2RcVA@mail.gmail.com>
 <CADhrpJ4sH9krkrWSoFjCg5jrkompgFY=G8iiXo0xy8_iCKeKxA@mail.gmail.com>
 <CADhrpJ7=5QbivftpcuVdhmcKxp3rjiuKQ4Lrf3NckBwL6YNmPQ@mail.gmail.com>
 <20120815234159.GK22226@titan.lakedaemon.net>
 <CADhrpJ4EMCuvuynF9x+q-PkNPRBaCD_G_YWbcYVj0UrGRQk5dg@mail.gmail.com>
 <CADhrpJ5UF6r2N027nOS6xmJtu21UbDxfzLninCZ7O-A+G3ALgg@mail.gmail.com>
 <CADhrpJ7geSRc3pow-DQWiA3rZ=f0i2WSws_QuKSDk7uZx1VSRQ@mail.gmail.com>
 <20120816221000.GG18145@lunn.ch>
Message-ID: <CAOMZO5A-Oc2PKwqwoE55OF-OMOqOh3AOOY=5N0KtkHkXfdeFOw@mail.gmail.com>

On Thu, Aug 16, 2012 at 7:10 PM, Andrew Lunn <andrew at lunn.ch> wrote:

>
> This would fit with:
>
> [    5.981782] Unable to handle kernel NULL pointer dereference at
> virtual address 00000004

Can you check if this patch fixes your issue?
https://patchwork.kernel.org/patch/1270731/

Regards,

Fabio Estevam


From shawn.guo at linaro.org  Thu Aug 16 20:31:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 08:31:27 +0800
Subject: [PATCH v4 1/3] Input: egalax_ts: get gpio from devicetree node
In-Reply-To: <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20120817003125.GA24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 06:47:29PM +0800, Hui Wang wrote:
> The irq_to_gpio() is old, most platforms use GENERIC_GPIO framework
> and don't support this API anymore.
> 
> The i.MX6q sabrelite platform equips an egalax touchscreen controller,
> and this platform already transfered to GENERIC_GPIO framework, to
> support this driver, we use a more generic way to get gpio.
> 
> Add a return value checking for waking up the controller in the probe
> function, this guarantee only a workable device can pass init.
> 
> Signed-off-by: Hui Wang <jason77.wang at gmail.com>

Reviewed-by: Shawn Guo <shawn.guo at linaro.org>


From shawn.guo at linaro.org  Thu Aug 16 20:32:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 08:32:11 +0800
Subject: [PATCH v4 2/3] Input: add devicetree binding note for egalax_ts
In-Reply-To: <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <20120817003209.GB24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 06:47:30PM +0800, Hui Wang wrote:
> The egalax_ts driver needs to get the gpio number of the irq pin,
> and use this gpio to wake up the controller. So add a note
> for this change.
> 
> Signed-off-by: Hui Wang <jason77.wang at gmail.com>

Reviewed-by: Shawn Guo <shawn.guo at linaro.org>


From shawn.guo at linaro.org  Thu Aug 16 20:33:31 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 08:33:31 +0800
Subject: [PATCH v4 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <1345114051-3052-4-git-send-email-jason77.wang@gmail.com>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <20120817003329.GC24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 06:47:31PM +0800, Hui Wang wrote:
> i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
> touchscreen controller, add it as an i2c slave device in the dts.
> 
> Signed-off-by: Hui Wang <jason77.wang at gmail.com>

Looks good.  Will apply it after the driver part gets accepted.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Aug 16 20:52:12 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 08:52:12 +0800
Subject: [PATCH v3 2/3] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <201208162305.55114.rjw@sisk.pl>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
 <1344577046-14847-3-git-send-email-shawn.guo@linaro.org>
 <201208162305.55114.rjw@sisk.pl>
Message-ID: <20120817005210.GD24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 11:05:54PM +0200, Rafael J. Wysocki wrote:
> On Friday, August 10, 2012, Shawn Guo wrote:
> > With a lot of devices booting from device tree nowadays, it requires
> > that OPP table can be initialized from device tree.  The patch adds
> > a helper function of_init_opp_table together with a binding doc for
> > that purpose.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> 
> I need an ACK from whoever maintains the DT bindings for that.
> 
Rob, please?

-- 
Regards,
Shawn


From jason77.wang at gmail.com  Thu Aug 16 21:20:59 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Fri, 17 Aug 2012 09:20:59 +0800
Subject: [PATCH v4 3/3] ARM: dts: imx6q-sabrelite: add eeti egalax
In-Reply-To: <20120817003329.GC24242@S2101-09.ap.freescale.net>
References: <1345114051-3052-1-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-2-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-3-git-send-email-jason77.wang@gmail.com>
 <1345114051-3052-4-git-send-email-jason77.wang@gmail.com>
 <20120817003329.GC24242@S2101-09.ap.freescale.net>
Message-ID: <502D9C7B.6070203@gmail.com>

Shawn Guo wrote:
> On Thu, Aug 16, 2012 at 06:47:31PM +0800, Hui Wang wrote:
>   
>> i.MX6Q sabrelite board uses i2c3 to connect an eeti egalax
>> touchscreen controller, add it as an i2c slave device in the dts.
>>
>> Signed-off-by: Hui Wang <jason77.wang at gmail.com>
>>     
>
> Looks good.  Will apply it after the driver part gets accepted.
>
>   
Got it, thanks.

Regards,
Hui.



From mitch.harder at sabayonlinux.org  Thu Aug 16 21:23:06 2012
From: mitch.harder at sabayonlinux.org (Mitch Harder)
Date: Thu, 16 Aug 2012 20:23:06 -0500
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <20120816221758.GM11413@one.firstfloor.org>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com> <20120816150647.GA22010@sig21.net>
 <20120816232549.4d14a6aa@natsu>
 <20120816175234.GL11413@one.firstfloor.org>
 <CAMuHMdWK_Y=QwkgQD6K8tFBLaO04Fy0yVAzEpb2OYW6Ec0hGoA@mail.gmail.com>
 <CAPkEcwgv6f5B+Mrw7kzrHcZ5JZ+Yr0o=bLdoFqCB-e4CLiVx5A@mail.gmail.com>
 <20120816221758.GM11413@one.firstfloor.org>
Message-ID: <CAKcLGm97zq7kx43cMyDwythin+R01E4zrtzrjAKkJjQL0iy+mg@mail.gmail.com>

On Thu, Aug 16, 2012 at 5:17 PM, Andi Kleen <andi at firstfloor.org> wrote:
> On Thu, Aug 16, 2012 at 11:55:06AM -0700, james northrup wrote:
>> looks like ARM results are inconclusive from a lot of folks without
>> bandwidth to do a write-up, what about just plain STAGING status for ARM so
>> the android tweakers can beat on it for a while?
>
> Staging only really works for new drivers, not for updating existing
> library functions like this.
>
> I suppose you could keep both and have the architecture select with a
> CONFIG.
>

I've been doing some rough benchmarking with the updated LZO in btrfs.

My tests primarily consist of timing some typical copying, git
manipulating, and running rsync using a set of kernel git sources.
Git sources are typically about 50% pack files which won't compress
very well, with the remainder being mostly highly compressible source
files.

Of course, any underlying speed improvement attributable only to LZO
is not shown by test like this. But I thought it would be interesting
to see the impact in some typical real-world btrfs operations.

I was seeing between 3-9% improvement in speed with the new LZO.

Copying several directories of git sources showed the most
improvement, ~9%.  Typical git operations, such as a git checkout or
git status where only showing 3-5% improvement, which is close to the
noise level of my tests.  Running multiple rsync processes showed a 5%
improvement.

With only 10 trials (5 with each LZO), I can't say I would
statistically hang my hat on these numbers.

Given all the other stuff that is going on in my rough benchmarks, a
3-9% improvement from a single change is probably pretty good.


From robherring2 at gmail.com  Thu Aug 16 21:53:05 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 16 Aug 2012 20:53:05 -0500
Subject: [PATCH v3 2/3] PM / OPP: Initialize OPP table from device tree
In-Reply-To: <20120817005210.GD24242@S2101-09.ap.freescale.net>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
 <1344577046-14847-3-git-send-email-shawn.guo@linaro.org>
 <201208162305.55114.rjw@sisk.pl>
 <20120817005210.GD24242@S2101-09.ap.freescale.net>
Message-ID: <502DA401.7040408@gmail.com>

On 08/16/2012 07:52 PM, Shawn Guo wrote:
> On Thu, Aug 16, 2012 at 11:05:54PM +0200, Rafael J. Wysocki wrote:
>> On Friday, August 10, 2012, Shawn Guo wrote:
>>> With a lot of devices booting from device tree nowadays, it requires
>>> that OPP table can be initialized from device tree.  The patch adds
>>> a helper function of_init_opp_table together with a binding doc for
>>> that purpose.
>>>
>>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>>
>> I need an ACK from whoever maintains the DT bindings for that.
>>
> Rob, please?

Acked-by: Rob Herring <rob.herring at calxeda.com>


From linux at roeck-us.net  Thu Aug 16 23:14:25 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Thu, 16 Aug 2012 20:14:25 -0700
Subject: [PATCH] spi/s3c64xx: Drop extra calls to spi_master_get in
 suspend/remove functions
Message-ID: <1345173265-1721-1-git-send-email-linux@roeck-us.net>

Suspend and resume functions call spi_master_get() without matching
spi_master_put(). The extra references are unnecessary and cause subsequent
module unload attempts to fail. Drop the calls.

Signed-off-by: Guenter Roeck <linux at roeck-us.net>
---
 drivers/spi/spi-s3c64xx.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 646a765..d7a87df 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1409,7 +1409,7 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int s3c64xx_spi_suspend(struct device *dev)
 {
-	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
+	struct spi_master *master = dev_get_drvdata(dev);
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 
 	spi_master_suspend(master);
@@ -1428,7 +1428,7 @@ static int s3c64xx_spi_suspend(struct device *dev)
 
 static int s3c64xx_spi_resume(struct device *dev)
 {
-	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
+	struct spi_master *master = dev_get_drvdata(dev);
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 
@@ -1452,7 +1452,7 @@ static int s3c64xx_spi_resume(struct device *dev)
 #ifdef CONFIG_PM_RUNTIME
 static int s3c64xx_spi_runtime_suspend(struct device *dev)
 {
-	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
+	struct spi_master *master = dev_get_drvdata(dev);
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 
 	clk_disable(sdd->clk);
@@ -1463,7 +1463,7 @@ static int s3c64xx_spi_runtime_suspend(struct device *dev)
 
 static int s3c64xx_spi_runtime_resume(struct device *dev)
 {
-	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
+	struct spi_master *master = dev_get_drvdata(dev);
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 
 	clk_enable(sdd->src_clk);
-- 
1.7.9.7



From linux at roeck-us.net  Thu Aug 16 23:28:19 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Thu, 16 Aug 2012 20:28:19 -0700
Subject: [PATCH] spi/s3c64xx: Drop extra calls to spi_master_get in
 suspend/remove functions
In-Reply-To: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
References: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
Message-ID: <20120817032819.GA6656@roeck-us.net>

Sigh.

s/remove/resume/ in headline.

Guenter

On Thu, Aug 16, 2012 at 08:14:25PM -0700, Guenter Roeck wrote:
> Suspend and resume functions call spi_master_get() without matching
> spi_master_put(). The extra references are unnecessary and cause subsequent
> module unload attempts to fail. Drop the calls.
> 
> Signed-off-by: Guenter Roeck <linux at roeck-us.net>
> ---
>  drivers/spi/spi-s3c64xx.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 646a765..d7a87df 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1409,7 +1409,7 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
>  #ifdef CONFIG_PM
>  static int s3c64xx_spi_suspend(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
>  
>  	spi_master_suspend(master);
> @@ -1428,7 +1428,7 @@ static int s3c64xx_spi_suspend(struct device *dev)
>  
>  static int s3c64xx_spi_resume(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
>  	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
>  
> @@ -1452,7 +1452,7 @@ static int s3c64xx_spi_resume(struct device *dev)
>  #ifdef CONFIG_PM_RUNTIME
>  static int s3c64xx_spi_runtime_suspend(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
>  
>  	clk_disable(sdd->clk);
> @@ -1463,7 +1463,7 @@ static int s3c64xx_spi_runtime_suspend(struct device *dev)
>  
>  static int s3c64xx_spi_runtime_resume(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
>  
>  	clk_enable(sdd->src_clk);
> -- 
> 1.7.9.7
> 
> 


From nico at fluxnic.net  Thu Aug 16 23:43:01 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 16 Aug 2012 23:43:01 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
Message-ID: <alpine.LFD.2.02.1208161906390.1541@xanadu.home>

On Tue, 14 Aug 2012, Will Deacon wrote:

> Data aborts taken to hyp mode do not provide a valid instruction
> syndrome field in the HSR if the faulting instruction is a memory
> access using a writeback addressing mode.
> 
> For hypervisors emulating MMIO accesses to virtual peripherals, taking
> such an exception requires disassembling the faulting instruction in
> order to determine the behaviour of the access. Since this requires
> manually walking the two stages of translation, the world must be
> stopped to prevent races against page aging in the guest, where the
> first-stage translation is invalidated after the hypervisor has
> translated to an IPA and the physical page is reused for something else.
> 
> This patch avoids taking this heavy performance penalty when running
> Linux as a guest by ensuring that our I/O accessors do not make use of
> writeback addressing modes.

How often does this happen?  I don't really see writeback as a common 
pattern for IO access.

What does happen quite a lot, though, is pre-indexed addressing.  For 
example, let's take this code which is fairly typical of driver code:

#define HW_REG1		0x10
#define HW_REG2		0x14
#define HW_REG3		0x18
#define HW_REG4		0x30

int hw_init(void __iomem *ioaddr)
{
	writel(0, ioaddr + HW_REG1)
	writel(-1, ioaddr + HW_REG2);
	writel(readl(ioaddr + HW_REG3) | 0xff, ioaddr + HW_REG4);
	return 0;
}

Right now this produces this:

hw_init:
        mov     r3, r0
        mvn     r2, #0
        mov     r0, #0
        str     r0, [r3, #16]
        str     r2, [r3, #20]
        ldr     r2, [r3, #24]
        orr     r2, r2, #255
        str     r2, [r3, #48]
        bx      lr

With your patch applied this becomes:

hw_init:
        add     r2, r0, #16
        mov     r3, #0
        str r3, [r2]
        mvn     r3, #0
        add     r2, r0, #20
        str r3, [r2]
        add     r3, r0, #24
        ldr r3, [r3]
        orr     r3, r3, #255
        add     r0, r0, #48
        str r3, [r0]
        mov     r0, #0
        bx      lr

This basically made every IO access into two instructions instead of 
only one, as well as increasing register pressure.

So, is the performance claim something that you've actually measured 
with a real system, or was it only theoretical?


Nicolas


From shawn.guo at linaro.org  Thu Aug 16 23:48:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 11:48:56 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120816223446.GB15883@n2100.arm.linux.org.uk>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
 <20120816023109.GH2258@S2101-09.ap.freescale.net>
 <20120816223446.GB15883@n2100.arm.linux.org.uk>
Message-ID: <20120817034854.GE24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 11:34:46PM +0100, Russell King - ARM Linux wrote:
> This doesn't get around the problem that userspace can still effectively
> issue a DoS against the system by just running a dmb in a tight loop.
> Or maybe this would have a much more dramatic effect:
> 
> 	while (1) {
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 		asm("dmb");
> 	}
> 
> and make that 3 seconds to get a ps listing turn into something much
> longer?
> 
>From my testing, no, it does not get the thing even worse.

> I think what needs to happen here (while we wait) is someone _with_ the
> problem needs to experiment, and find out how many nops are needed for
> the DMB not to have much effect in cpu_relax().  If it turns out we just
> need to put one nop in, then that's not _too_ bad.

At least, I need to have 5 nops to get rid of the issue, something like
below.

Regards,
Shawn

--8<---

diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 99afa74..3e1b099 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
 unsigned long get_wchan(struct task_struct *p);

 #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
-#define cpu_relax()                    smp_mb()
+#define cpu_relax()    do {                                            \
+                               asm("nop");                             \
+                               asm("nop");                             \
+                               asm("nop");                             \
+                               asm("nop");                             \
+                               asm("nop");                             \
+                               smp_mb();                               \
+                       } while (0)
 #else
 #define cpu_relax()                    barrier()
 #endif



From shawn.guo at linaro.org  Fri Aug 17 01:11:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 13:11:56 +0800
Subject: [PATCH] ARM: imx6q: remove imx_src_prepare_restart() call
Message-ID: <1345180316-9209-1-git-send-email-shawn.guo@linaro.org>

Currently, imx_src_prepare_restart which is called by imx6q_restart
assumes that cpu0 must be the running cpu, so it disables all secondary
cpus.  However this is not the case, the restart routine could possibly
running on cpu1 or any other secondary cores.  In that case, disabling
the cpu that runs restart routine will hang up system.

Also it turns out that everything that is done by imx_src_prepare_restart
is not really necessary, because the watchdog reset will have those
registers reset properly.  So let's remove the imx_src_prepare_restart
call completely.

Cc: <stable at vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-imx6q.c          |    2 --
 arch/arm/mach-imx/src.c                 |   13 -------------
 arch/arm/plat-mxc/include/mach/common.h |    1 -
 3 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..d9b0614 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -48,8 +48,6 @@ void imx6q_restart(char mode, const char *cmd)
 	if (!wdog_base)
 		goto soft;
 
-	imx_src_prepare_restart();
-
 	/* enable wdog */
 	writew_relaxed(1 << 2, wdog_base);
 	/* write twice to ensure the request will not get ignored */
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index e15f155..900b3c1 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -43,19 +43,6 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
 		       src_base + SRC_GPR1 + cpu * 8);
 }
 
-void imx_src_prepare_restart(void)
-{
-	u32 val;
-
-	/* clear enable bits of secondary cores */
-	val = readl_relaxed(src_base + SRC_SCR);
-	val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
-	writel_relaxed(val, src_base + SRC_SCR);
-
-	/* clear persistent entry register of primary core */
-	writel_relaxed(0, src_base + SRC_GPR1);
-}
-
 void __init imx_src_init(void)
 {
 	struct device_node *np;
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e97..e94073f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -133,7 +133,6 @@ static inline void imx_smp_prepare(void) {}
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
-extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
-- 
1.7.5.4



From thomas.abraham at linaro.org  Fri Aug 17 01:20:24 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 17 Aug 2012 10:50:24 +0530
Subject: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung
 Exynos4210 SoC
In-Reply-To: <CAKGA1b=nXbTU70tFWWwvKoA6N4bMjG9R-vs2egppzQbwgkxAVw@mail.gmail.com>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
 <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>
 <CAKGA1b=nXbTU70tFWWwvKoA6N4bMjG9R-vs2egppzQbwgkxAVw@mail.gmail.com>
Message-ID: <CAJuYYwTG=GgricAJRHiSQBn6ZAOy+sucFCdDX3QhgfSQFwuKaw@mail.gmail.com>

On 17 August 2012 00:26, Matt Sealey <matt at genesi-usa.com> wrote:
> Re: samsung,pin-function samsung,pin-pud samsung,pin-drv - why can't
> these be one property, why take the space to define them individually
> instead of in an array of 3 values under one property name?

Samsung pinctrl driver was written to be usable on all of the Samsung
application processors starting from 24xx series to the latest
Exynos5.

The gpio/pinmux/pinconfig controllers on these SoC have varying
capabilities. Some of the banks in s3c24xx series support mux function
but do not support pull up/down (pud) or driver strength (drv).
s3c64xx soc's have banks that support pin mux and 'pud' but do not
support 'drv'. And there are banks that do not support mux function
but support 'pud' and 'drv'. Further, a given SoC can have multiple
combinations of different bank types.

In addition to this, there are two more properties for mux and pud
values in power down mode in some of the samsung SoC's.

To keep the bindings common across all the possible Samsung SoC's, the
mux, pud and drv properties were split so that the parsing code in the
Samsung pinctrl driver remains generic for all the possible
combinations of pin banks and SoC's.

Thanks,
Thomas.


>
> --
> Matt Sealey <matt at genesi-usa.com>
> Product Development Analyst, Genesi USA, Inc.
>
>
> On Wed, Aug 15, 2012 at 3:10 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>> Add pinctrl driver nodes for the three instances of pin controllers
>> in Samsung Exynos4210 SoC and add the pin group nodes available in the
>> each of those three instances.
>>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>>  arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
>>  2 files changed, 494 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
>>
>> diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
>> new file mode 100644
>> index 0000000..b12cf27
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
>> @@ -0,0 +1,457 @@
>> +/*
>> + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
>> + *
>> + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
>> + *             http://www.samsung.com
>> + * Copyright (c) 2011-2012 Linaro Ltd.
>> + *             www.linaro.org
>> + *
>> + * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
>> + * tree nodes are listed in this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/ {
>> +       pinctrl at 11400000 {
>> +               uart0_data: uart0-data {
>> +                       samsung,pins = "gpa0-0", "gpa0-1";
>> +                       samsung,pin-function = <0x2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart0_fctl: uart0-fctl {
>> +                       samsung,pins = "gpa0-2", "gpa0-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart1_data: uart1-data {
>> +                       samsung,pins = "gpa0-4", "gpa0-5";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart1_fctl: uart1-fctl {
>> +                       samsung,pins = "gpa0-6", "gpa0-7";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c2_bus: i2c2-bus {
>> +                       samsung,pins = "gpa0-6", "gpa0-7";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart2_data: uart2-data {
>> +                       samsung,pins = "gpa1-0", "gpa1-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart2_fctl: uart2-fctl {
>> +                       samsung,pins = "gpa1-2", "gpa1-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart_audio_a: uart-audio-a {
>> +                       samsung,pins = "gpa1-0", "gpa1-1";
>> +                       samsung,pin-function = <4>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c3_bus: i2c3-bus {
>> +                       samsung,pins = "gpa1-2", "gpa1-3";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart3_data: uart3-data {
>> +                       samsung,pins = "gpa1-4", "gpa1-5";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               uart_audio_b: uart-audio-b {
>> +                       samsung,pins = "gpa1-4", "gpa1-5";
>> +                       samsung,pin-function = <4>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               spi0_bus: spi0-bus {
>> +                       samsung,pins = "gpb-0", "gpb-2", "gpb-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c4_bus: i2c4-bus {
>> +                       samsung,pins = "gpb-2", "gpb-3";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               spi1_bus: spi1-bus {
>> +                       samsung,pins = "gpb-4", "gpb-6", "gpb-7";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c5_bus: i2c5-bus {
>> +                       samsung,pins = "gpb-6", "gpb-7";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2s1_bus: i2s1-bus {
>> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
>> +                                       "gpc0-4";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               pcm1_bus: pcm1-bus {
>> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
>> +                                       "gpc0-4";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               ac97_bus: ac97-bus {
>> +                       samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
>> +                                       "gpc0-4";
>> +                       samsung,pin-function = <4>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2s2_bus: i2s2-bus {
>> +                       samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
>> +                                       "gpc1-4";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               pcm2_bus: pcm2-bus {
>> +                       samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
>> +                                       "gpc1-4";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               spdif_bus: spdif-bus {
>> +                       samsung,pins = "gpc1-0", "gpc1-1";
>> +                       samsung,pin-function = <4>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c6_bus: i2c6-bus {
>> +                       samsung,pins = "gpc1-3", "gpc1-4";
>> +                       samsung,pin-function = <4>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               spi2_bus: spi2-bus {
>> +                       samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
>> +                       samsung,pin-function = <5>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c7_bus: i2c7-bus {
>> +                       samsung,pins = "gpd0-2", "gpd0-3";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c0_bus: i2c0-bus {
>> +                       samsung,pins = "gpd1-0", "gpd1-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               i2c1_bus: i2c1-bus {
>> +                       samsung,pins = "gpd1-2", "gpd1-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +       };
>> +
>> +       pinctrl at 11000000 {
>> +               sd0_clk: sd0-clk {
>> +                       samsung,pins = "gpk0-0";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd0_cmd: sd0-cmd {
>> +                       samsung,pins = "gpk0-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd0_cd: sd0-cd {
>> +                       samsung,pins = "gpk0-2";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd0_bus1: sd0-bus-width1 {
>> +                       samsung,pins = "gpk0-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd0_bus4: sd0-bus-width4 {
>> +                       samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd0_bus8: sd0-bus-width8 {
>> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_clk: sd4-clk {
>> +                       samsung,pins = "gpk0-0";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_cmd: sd4-cmd {
>> +                       samsung,pins = "gpk0-1";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_cd: sd4-cd {
>> +                       samsung,pins = "gpk0-2";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_bus1: sd4-bus-width1 {
>> +                       samsung,pins = "gpk0-3";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_bus4: sd4-bus-width4 {
>> +                       samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd4_bus8: sd4-bus-width8 {
>> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <4>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd1_clk: sd1-clk {
>> +                       samsung,pins = "gpk1-0";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd1_cmd: sd1-cmd {
>> +                       samsung,pins = "gpk1-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd1_cd: sd1-cd {
>> +                       samsung,pins = "gpk1-2";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd1_bus1: sd1-bus-width1 {
>> +                       samsung,pins = "gpk1-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd1_bus4: sd1-bus-width4 {
>> +                       samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_clk: sd2-clk {
>> +                       samsung,pins = "gpk2-0";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_cmd: sd2-cmd {
>> +                       samsung,pins = "gpk2-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_cd: sd2-cd {
>> +                       samsung,pins = "gpk2-2";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_bus1: sd2-bus-width1 {
>> +                       samsung,pins = "gpk2-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_bus4: sd2-bus-width4 {
>> +                       samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd2_bus8: sd2-bus-width8 {
>> +                       samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
>> +                       samsung,pin-function = <3>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd3_clk: sd3-clk {
>> +                       samsung,pins = "gpk3-0";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd3_cmd: sd3-cmd {
>> +                       samsung,pins = "gpk3-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd3_cd: sd3-cd {
>> +                       samsung,pins = "gpk3-2";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd3_bus1: sd3-bus-width1 {
>> +                       samsung,pins = "gpk3-3";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               sd3_bus4: sd3-bus-width4 {
>> +                       samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <3>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               eint0: ext-int0 {
>> +                       samsung,pins = "gpx0-0";
>> +                       samsung,pin-function = <0xf>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               eint8: ext-int8 {
>> +                       samsung,pins = "gpx1-0";
>> +                       samsung,pin-function = <0xf>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               eint15: ext-int15 {
>> +                       samsung,pins = "gpx1-7";
>> +                       samsung,pin-function = <0xf>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               eint16: ext-int16 {
>> +                       samsung,pins = "gpx2-0";
>> +                       samsung,pin-function = <0xf>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               eint31: ext-int31 {
>> +                       samsung,pins = "gpx3-7";
>> +                       samsung,pin-function = <0xf>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +       };
>> +
>> +       pinctrl at 03860000 {
>> +               i2s0_bus: i2s0-bus {
>> +                       samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
>> +                                       "gpz-4", "gpz-5", "gpz-6";
>> +                       samsung,pin-function = <0x2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +
>> +               pcm0_bus: pcm0-bus {
>> +                       samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
>> +                                       "gpz-4";
>> +                       samsung,pin-function = <0x3>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>> +       };
>> +};
>> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
>> index 02891fe..a4bd0c9 100644
>> --- a/arch/arm/boot/dts/exynos4210.dtsi
>> +++ b/arch/arm/boot/dts/exynos4210.dtsi
>> @@ -20,6 +20,7 @@
>>  */
>>
>>  /include/ "skeleton.dtsi"
>> +/include/ "exynos4210-pinctrl.dtsi"
>>
>>  / {
>>         compatible = "samsung,exynos4210";
>> @@ -29,6 +30,9 @@
>>                 spi0 = &spi_0;
>>                 spi1 = &spi_1;
>>                 spi2 = &spi_2;
>> +               pinctrl0 = &pinctrl_0;
>> +               pinctrl1 = &pinctrl_1;
>> +               pinctrl2 = &pinctrl_2;
>>         };
>>
>>         gic:interrupt-controller at 10490000 {
>> @@ -50,6 +54,39 @@
>>                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
>>         };
>>
>> +       pinctrl_0: pinctrl at 11400000 {
>> +               compatible = "samsung,pinctrl-exynos4210";
>> +               reg = <0x11400000 0x1000>;
>> +               interrupts = <0 47 0>;
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +       };
>> +
>> +       pinctrl_1: pinctrl at 11000000 {
>> +               compatible = "samsung,pinctrl-exynos4210";
>> +               reg = <0x11000000 0x1000>;
>> +               interrupts = <0 46 0>;
>> +               interrupt-controller;
>> +               #interrupt-cells = <2>;
>> +
>> +               wakup_eint: wakeup-interrupt-controller {
>> +                       compatible = "samsung,exynos4210-wakeup-eint";
>> +                       interrupt-parent = <&gic>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <2>;
>> +                       interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
>> +                                       <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
>> +                                       <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
>> +                                       <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
>> +                                       <0 32 0>;
>> +               };
>> +       };
>> +
>> +       pinctrl_2: pinctrl at 03860000 {
>> +               compatible = "samsung,pinctrl-exynos4210";
>> +               reg = <0x03860000 0x1000>;
>> +       };
>> +
>>         watchdog at 10060000 {
>>                 compatible = "samsung,s3c2410-wdt";
>>                 reg = <0x10060000 0x100>;
>> --
>> 1.6.6.rc2
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From hvaibhav at ti.com  Fri Aug 17 01:32:53 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 Aug 2012 05:32:53 +0000
Subject: [RFC RESEND 2/4] ARM: OMAP3: Dynamically disable secure timer
 nodes for secure devices
In-Reply-To: <502D2686.4090107@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
 <502B6838.9080907@ti.com> <502D2686.4090107@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA91D63@DBDE01.ent.ti.com>

On Thu, Aug 16, 2012 at 22:27:42, Hunter, Jon wrote:
> 
> On 08/15/2012 04:13 AM, Vaibhav Hiremath wrote:
> > 
> > 
> > On 7/14/2012 3:56 AM, Jon Hunter wrote:
> >> OMAP3 devices may or may not have security features enabled. Security enabled
> >> devices are known as high-secure (HS) and devices without security are known as
> >> general purpose (GP).
> >>
> >> For OMAP3 devices there are 12 general purpose timers available. On secure
> >> devices the 12th timer is reserved for secure usage and so cannot be used by
> >> the kernel, where as for a GP device it is available. We can detect the OMAP
> >> device type, secure or GP, at runtime via an on-chip register. Today, when not
> >> using DT, we do not register the 12th timer as a linux device if the device is
> >> secure.
> >>
> >> When using device tree, device tree is going to register all the timer devices
> >> it finds in the device tree blob. To prevent device tree from registering 12th
> >> timer on a secure OMAP3 device we can add a status property to the timer
> >> binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
> >> device has a property "ti,timer-secure" to indicate that it will not be
> >> available on a secure device and so for secure OMAP3 devices, we search for
> >> timers with this property and then disable them. Using the prom_add_property()
> >> function to dynamically add a property was a recommended approach suggested by
> >> Rob Herring [1].
> >>
> >> I have tested this on an OMAP3 GP device and faking it to pretend to be a
> >> secure device to ensure that any timers marked with "ti,timer-secure" are not
> >> registered on boot. I have also made sure that all timers are registered as
> >> expected on a GP device by default.
> >>
> >> [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
> >>
> >> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> >> ---
> >>  arch/arm/mach-omap2/board-generic.c |    1 +
> >>  arch/arm/mach-omap2/common.h        |    1 +
> >>  arch/arm/mach-omap2/timer.c         |   36 +++++++++++++++++++++++++++++++++++
> >>  3 files changed, 38 insertions(+)
> >>
> >> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> >> index 6f93a20..20124d7 100644
> >> --- a/arch/arm/mach-omap2/board-generic.c
> >> +++ b/arch/arm/mach-omap2/board-generic.c
> >> @@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
> >>  static void __init omap_generic_init(void)
> >>  {
> >>  	omap_sdrc_init(NULL, NULL);
> >> +	omap_dmtimer_init();
> >>  
> >>  	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
> >>  }
> >> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> >> index 1f65b18..d6a4875 100644
> >> --- a/arch/arm/mach-omap2/common.h
> >> +++ b/arch/arm/mach-omap2/common.h
> >> @@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> >>  				      struct omap_sdrc_params *sdrc_cs1);
> >>  struct omap2_hsmmc_info;
> >>  extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
> >> +extern void omap_dmtimer_init(void);
> >>  
> >>  #endif /* __ASSEMBLER__ */
> >>  #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
> >> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> >> index 13d20c8..e3b9931 100644
> >> --- a/arch/arm/mach-omap2/timer.c
> >> +++ b/arch/arm/mach-omap2/timer.c
> >> @@ -36,6 +36,7 @@
> >>  #include <linux/clocksource.h>
> >>  #include <linux/clockchips.h>
> >>  #include <linux/slab.h>
> >> +#include <linux/of.h>
> >>  
> >>  #include <asm/mach/time.h>
> >>  #include <plat/dmtimer.h>
> >> @@ -482,6 +483,41 @@ static int __init omap2_dm_timer_init(void)
> >>  }
> >>  arch_initcall(omap2_dm_timer_init);
> >>  
> >> +static struct property timer_disabled = {
> >> +	.name = "status",
> >> +	.length = sizeof("disabled"),
> >> +	.value = "disabled",
> >> +};
> >> +
> >> +static struct of_device_id omap3_timer_match[] __initdata = {
> >> +	{ .compatible = "ti,omap3-timer", },
> >> +	{ }
> >> +};
> >> +
> >> +/**
> >> + * omap_dmtimer_init - initialisation function when device tree is used
> >> + *
> >> + * For secure OMAP3 devices, timers with device type "timer-secure" cannot
> >> + * be used by the kernel as they are reserved. Therefore, to prevent the
> >> + * kernel registering these devices remove them dynamically from the device
> >> + * tree on boot.
> >> + */
> >> +void __init omap_dmtimer_init(void)
> >> +{
> >> +	struct device_node *np;
> >> +
> >> +	if (!cpu_is_omap34xx())
> >> +		return;
> >> +
> > 
> > Sorry for responding so late, but why only omap34xx check here?
> > Isn't this applicable to all omap & non-omap devices?
> 
> It is only applicable to omap3 devices as far as omap is concerned.
> 
> By non-omap, you are referring to the AMxxx stuff?
> 
> Do AMxxx devices even support security (ie. secure boot and have secure
> peripherals)? If not then this will work for AMxxx devices too.
> 

Yes it does. 

AM33xx has 8 timers and Timer-0 is a secure timer. As in case of OMAP3, we 
do not even register timer-0 to kernel.


> Let me know if the changelog is not clear why this is needed for an
> omap3 device.
> 

The changelog description is clear, but it is not only restricted to OMAP3.

Thanks,
Vaibhav



From xiechao.mail at gmail.com  Fri Aug 17 02:02:05 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:05 +0800
Subject: [PATCH v4 0/5] clk: mmp: add clock framework for mmp
Message-ID: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

v1->v2:
replace __raw_xxx with xxx_relax
use ioremap to remap the registers. Finaly it will use device tree to
get the physical address.
do not use macro to register clocks, and directly call the functions.

v2->v3:
pxa910 will have APB extension clock, so some peripharals will have
clocks in APB extension base.
change pxa168-pwm to be pxa910-pwm for pxa910. It will fit the current
pwm driver.

v3->v4:
remove addtional clock name definition
replace left __raw_xxx

Chao Xie (5):
  clk: mmp: add mmp specific clocks
  clk: mmp: add clock definition for pxa168
  clk: mmp: add clock definition for pxa910
  clk: mmp: add clock definition for mmp2
  arm: mmp: make all SOCs use common clock by default

 arch/arm/mach-mmp/Kconfig    |    3 +
 drivers/clk/Makefile         |    3 +
 drivers/clk/mmp/Makefile     |    9 +
 drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++
 drivers/clk/mmp/clk-apmu.c   |   97 ++++++++
 drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++
 drivers/clk/mmp/clk-mmp2.c   |  527 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa168.c |  402 ++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa910.c |  369 +++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h        |   35 +++
 10 files changed, 1750 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk-mmp2.c
 create mode 100644 drivers/clk/mmp/clk-pxa168.c
 create mode 100644 drivers/clk/mmp/clk-pxa910.c
 create mode 100644 drivers/clk/mmp/clk.h



From xiechao.mail at gmail.com  Fri Aug 17 02:02:06 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:06 +0800
Subject: [PATCH V4 1/5] clk: mmp: add mmp specific clocks
In-Reply-To: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345183330-20244-2-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

add mmp specific clocks including apbc cloks, apmu clocks,
and pll2, fraction clocks

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/Makefile       |    3 +
 drivers/clk/mmp/Makefile   |    5 ++
 drivers/clk/mmp/clk-apbc.c |  152 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-apmu.c |   97 ++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-frac.c |  153 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h      |   35 ++++++++++
 6 files changed, 445 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..58590c8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,9 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-$(CONFIG_ARCH_MMP)		+= mmp/
+endif
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
new file mode 100644
index 0000000..b5bc88c
--- /dev/null
+++ b/drivers/clk/mmp/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for mmp specific clk
+#
+
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
new file mode 100644
index 0000000..d14120e
--- /dev/null
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -0,0 +1,152 @@
+/*
+ * mmp APB clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
+#define APBC_RST	(1 << 2)  /* Reset Generation */
+#define APBC_POWER	(1 << 7)  /* Reset Generation */
+
+#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
+struct clk_apbc {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	unsigned int		delay;
+	unsigned int		flags;
+	spinlock_t		*lock;
+};
+
+static int clk_apbc_prepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned int data;
+	unsigned long flags = 0;
+
+	/*
+	 * It may share same register as MUX clock,
+	 * and it will impact FNCLK enable. Spinlock is needed
+	 */
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data |= APBC_POWER;
+	data |= APBC_FNCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	data |= APBC_APBCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
+		if (apbc->lock)
+			spin_lock_irqsave(apbc->lock, flags);
+
+		data = readl_relaxed(apbc->base);
+		data &= ~APBC_RST;
+		writel_relaxed(data, apbc->base);
+
+		if (apbc->lock)
+			spin_unlock_irqrestore(apbc->lock, flags);
+	}
+
+	return 0;
+}
+
+static void clk_apbc_unprepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data &= ~APBC_POWER;
+	data &= ~APBC_FNCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(10);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	data &= ~APBC_APBCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+}
+
+struct clk_ops clk_apbc_ops = {
+	.prepare = clk_apbc_prepare,
+	.unprepare = clk_apbc_unprepare,
+};
+
+struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
+		void __iomem *base, unsigned int delay,
+		unsigned int apbc_flags, spinlock_t *lock)
+{
+	struct clk_apbc *apbc;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
+	if (!apbc)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apbc_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apbc->base = base;
+	apbc->delay = delay;
+	apbc->flags = apbc_flags;
+	apbc->lock = lock;
+	apbc->hw.init = &init;
+
+	clk = clk_register(NULL, &apbc->hw);
+	if (IS_ERR(clk))
+		kfree(apbc);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
new file mode 100644
index 0000000..abe182b
--- /dev/null
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -0,0 +1,97 @@
+/*
+ * mmp AXI peripharal clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
+struct clk_apmu {
+	struct clk_hw   hw;
+	void __iomem    *base;
+	u32		rst_mask;
+	u32		enable_mask;
+	spinlock_t	*lock;
+};
+
+static int clk_apmu_enable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = readl_relaxed(apmu->base) | apmu->enable_mask;
+	writel_relaxed(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+
+	return 0;
+}
+
+static void clk_apmu_disable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
+	writel_relaxed(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+}
+
+struct clk_ops clk_apmu_ops = {
+	.enable = clk_apmu_enable,
+	.disable = clk_apmu_disable,
+};
+
+struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
+		void __iomem *base, u32 enable_mask, spinlock_t *lock)
+{
+	struct clk_apmu *apmu;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
+	if (!apmu)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apmu_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apmu->base = base;
+	apmu->enable_mask = enable_mask;
+	apmu->lock = lock;
+	apmu->hw.init = &init;
+
+	clk = clk_register(NULL, &apmu->hw);
+
+	if (IS_ERR(clk))
+		kfree(apmu);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
new file mode 100644
index 0000000..80c1dd1
--- /dev/null
+++ b/drivers/clk/mmp/clk-frac.c
@@ -0,0 +1,153 @@
+/*
+ * mmp factor clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+/*
+ * It is M/N clock
+ *
+ * Fout from synthesizer can be given from two equations:
+ * numerator/denominator = Fin / (Fout * factor)
+ */
+
+#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
+struct clk_factor {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	struct clk_factor_masks	*masks;
+	struct clk_factor_tbl	*ftbl;
+	unsigned int		ftbl_cnt;
+};
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	unsigned long rate = 0, prev_rate;
+	int i;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((*prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i == 0)
+		return rate;
+	else
+		return prev_rate;
+}
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	unsigned int val, num, den;
+
+	val = readl_relaxed(factor->base);
+
+	/* calculate numerator */
+	num = (val >> masks->num_shift) & masks->num_mask;
+
+	/* calculate denominator */
+	den = (val >> masks->den_shift) & masks->num_mask;
+
+	if (!den)
+		return 0;
+
+	return (((parent_rate / 10000)  * den) /
+			(num * factor->masks->factor)) * 10000;
+}
+
+/* Configures new clock rate*/
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
+				unsigned long prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	int i;
+	unsigned long val;
+	unsigned long prev_rate, rate = 0;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i > 0)
+		i--;
+
+	val = readl_relaxed(factor->base);
+
+	val &= ~(masks->num_mask << masks->num_shift);
+	val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+
+	val &= ~(masks->den_mask << masks->den_shift);
+	val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+
+	writel_relaxed(val, factor->base);
+
+	return 0;
+}
+
+static struct clk_ops clk_factor_ops = {
+	.recalc_rate = clk_factor_recalc_rate,
+	.round_rate = clk_factor_round_rate,
+	.set_rate = clk_factor_set_rate,
+};
+
+struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
+		unsigned long flags, void __iomem *base,
+		struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
+		unsigned int ftbl_cnt)
+{
+	struct clk_factor *factor;
+	struct clk_init_data init;
+	struct clk *clk;
+
+	if (!masks) {
+		pr_err("%s: must pass a clk_factor_mask\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	factor = kzalloc(sizeof(*factor), GFP_KERNEL);
+	if (!factor) {
+		pr_err("%s: could not allocate factor  clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_aux assignments */
+	factor->base = base;
+	factor->masks = masks;
+	factor->ftbl = ftbl;
+	factor->ftbl_cnt = ftbl_cnt;
+	factor->hw.init = &init;
+
+	init.name = name;
+	init.ops = &clk_factor_ops;
+	init.flags = flags;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clk = clk_register(NULL, &factor->hw);
+	if (IS_ERR_OR_NULL(clk))
+		kfree(factor);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
new file mode 100644
index 0000000..ab86dd4
--- /dev/null
+++ b/drivers/clk/mmp/clk.h
@@ -0,0 +1,35 @@
+#ifndef __MACH_MMP_CLK_H
+#define __MACH_MMP_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+#define APBC_NO_BUS_CTRL	BIT(0)
+#define APBC_POWER_CTRL		BIT(1)
+
+struct clk_factor_masks {
+	unsigned int	factor;
+	unsigned int	num_mask;
+	unsigned int	den_mask;
+	unsigned int	num_shift;
+	unsigned int	den_shift;
+};
+
+struct clk_factor_tbl {
+	unsigned int num;
+	unsigned int den;
+};
+
+extern struct clk *mmp_clk_register_pll2(const char *name,
+		const char *parent_name, unsigned long flags);
+extern struct clk *mmp_clk_register_apbc(const char *name,
+		const char *parent_name, void __iomem *base,
+		unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
+extern struct clk *mmp_clk_register_apmu(const char *name,
+		const char *parent_name, void __iomem *base, u32 enable_mask,
+		spinlock_t *lock);
+extern struct clk *mmp_clk_register_factor(const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *base, struct clk_factor_masks *masks,
+		struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+#endif
-- 
1.7.0.4



From xiechao.mail at gmail.com  Fri Aug 17 02:02:07 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:07 +0800
Subject: [PATCH V4 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345183330-20244-3-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa168

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    2 +
 drivers/clk/mmp/clk-pxa168.c |  402 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 404 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa168.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index b5bc88c..a0e69ed 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -3,3 +3,5 @@
 #
 
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+
+obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 0000000..21ac6cc
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,402 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x30
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x81c
+#define APBC_SSP1	0x820
+#define APBC_SSP2	0x84c
+#define APBC_SSP3	0x858
+#define APBC_SSP4	0x85c
+#define APBC_TWSI1	0x6c
+#define APBC_UART2	0x70
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa168_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *uart_pll;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(clk, "vctcxo", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_24", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_48", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_96", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clk, "pll1_13", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				      CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+	uart_pll =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(uart_pll, 14745600);
+	clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk =
+	    mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+	clk =
+	    mmp_clk_register_apbc("pwm0", "pll1_48", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
+
+	clk =
+	    mmp_clk_register_apbc("pwm1", "pll1_48", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
+
+	clk =
+	    mmp_clk_register_apbc("pwm2", "pll1_48", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
+
+	clk =
+	    mmp_clk_register_apbc("pwm3", "pll1_48", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
+
+	clk =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart2", "uart2_mux", apbc_base + APBC_UART2,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk =
+	    clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+	clk =
+	    clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+	clk =
+	    clk_register_mux(NULL, "ssp4_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.4", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.4");
+
+	clk =
+	    mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+	clk =
+	    clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+	clk =
+	    clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+	clk =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 0x12,
+				  &clk_lock);
+	clk_register_clkdev(clk, "sph_clk", NULL);
+
+	clk =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
+
+	clk =
+	    mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
+				  apmu_base + APMU_DISP0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "hclk", "mmp-disp.0");
+
+	clk =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0", "ccic0_mux", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+			     ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Fri Aug 17 02:02:08 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:08 +0800
Subject: [PATCH V4 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345183330-20244-4-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa910

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    1 +
 drivers/clk/mmp/clk-pxa910.c |  369 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 370 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa910.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index a0e69ed..6160ac2 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -5,3 +5,4 @@
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
+obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
new file mode 100644
index 0000000..a6a0911
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -0,0 +1,369 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x18
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x1c
+#define APBC_SSP1	0x20
+#define APBC_SSP2	0x4c
+#define APBCP_TWSI1	0x28
+#define APBCP_UART2	0x1c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa910_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *uart_pll;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbcp_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
+	if (apbcp_base == NULL) {
+		pr_err("error to ioremap APBC extension base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(clk, "vctcxo", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_24", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_48", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_96", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clk, "pll1_13", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				      CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				      CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+	uart_pll =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(uart_pll, 14745600);
+	clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				  apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk =
+	    mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				  apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+	clk =
+	    mmp_clk_register_apbc("pwm0", "pll1_48", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
+
+	clk =
+	    mmp_clk_register_apbc("pwm1", "pll1_48", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
+
+	clk =
+	    mmp_clk_register_apbc("pwm2", "pll1_48", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
+
+	clk =
+	    mmp_clk_register_apbc("pwm3", "pll1_48", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
+
+	clk =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart2", "uart2_mux",
+				  apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk =
+	    mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 0x19b,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+	clk =
+	    clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+	clk =
+	    clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+	clk =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 0x12,
+				  &clk_lock);
+	clk_register_clkdev(clk, "sph_clk", NULL);
+
+	clk =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("disp0", "disp0_mux", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+	clk =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0", "ccic0_mux", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+			     ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Fri Aug 17 02:02:09 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:09 +0800
Subject: [PATCH V4 4/5] clk: mmp: add clock definition for mmp2
In-Reply-To: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345183330-20244-5-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for mmp2

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile   |    1 +
 drivers/clk/mmp/clk-mmp2.c |  527 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 528 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-mmp2.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 6160ac2..392d780 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
+obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
new file mode 100644
index 0000000..3dfb7d5
--- /dev/null
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -0,0 +1,527 @@
+/*
+ * mmp clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x0
+#define APBC_TWSI0	0x4
+#define APBC_TWSI1	0x8
+#define APBC_TWSI2	0xc
+#define APBC_TWSI3	0x10
+#define APBC_TWSI4	0x7c
+#define APBC_TWSI5	0x80
+#define APBC_KPC	0x18
+#define APBC_UART0	0x2c
+#define APBC_UART1	0x30
+#define APBC_UART2	0x34
+#define APBC_UART3	0x88
+#define APBC_GPIO	0x38
+#define APBC_PWM0	0x3c
+#define APBC_PWM1	0x40
+#define APBC_PWM2	0x44
+#define APBC_PWM3	0x48
+#define APBC_SSP0	0x50
+#define APBC_SSP1	0x54
+#define APBC_SSP2	0x58
+#define APBC_SSP3	0x5c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_SDH2	0xe8
+#define APMU_SDH3	0xec
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_DISP1	0x110
+#define APMU_CCIC0	0x50
+#define APMU_CCIC1	0xf4
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 14634, .den = 2165},	/*14.745MHZ */
+	{.num = 3521, .den = 689},	/*19.23MHZ */
+	{.num = 9679, .den = 5728},	/*58.9824MHZ */
+	{.num = 15850, .den = 9451},	/*59.429MHZ */
+};
+
+static const char *uart_parent[] = {"uart_pll", "vctcxo"};
+static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
+
+void __init mmp2_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *vctcxo;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	vctcxo =
+	    clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				    26000000);
+	clk_register_clkdev(vctcxo, "vctcxo", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 800000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
+				    480000000);
+	clk_register_clkdev(clk, "usb_pll", NULL);
+
+	clk =
+	    clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, 960000000);
+	clk_register_clkdev(clk, "pll2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
+				      CLK_SET_RATE_PARENT, 1, 5);
+	clk_register_clkdev(clk, "pll1_20", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_3", "pll1",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_3", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_2", "pll2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_4", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_8", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_16", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_3", "pll2",
+				      CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll2_3", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_6", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_12", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "vctcxo_2", NULL);
+
+	clk =
+	    clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
+				      CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "vctcxo_4", NULL);
+
+	clk =
+	    mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				    mpmu_base + MPMU_UART_PLL,
+				    &uart_factor_masks, uart_factor_tbl,
+				    ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(clk, 14745600);
+	clk_register_clkdev(clk, "uart_pll", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("twsi0", "vctcxo", apbc_base + APBC_TWSI0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk =
+	    mmp_clk_register_apbc("twsi1", "vctcxo", apbc_base + APBC_TWSI1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk =
+	    mmp_clk_register_apbc("twsi2", "vctcxo", apbc_base + APBC_TWSI2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
+
+	clk =
+	    mmp_clk_register_apbc("twsi3", "vctcxo", apbc_base + APBC_TWSI3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
+
+	clk =
+	    mmp_clk_register_apbc("twsi4", "vctcxo", apbc_base + APBC_TWSI4, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
+
+	clk =
+	    mmp_clk_register_apbc("twsi5", "vctcxo", apbc_base + APBC_TWSI5, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
+
+	clk =
+	    mmp_clk_register_apbc("gpio", "vctcxo", apbc_base + APBC_GPIO, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk =
+	    mmp_clk_register_apbc("kpc", "clk32", apbc_base + APBC_KPC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk =
+	    mmp_clk_register_apbc("rtc", "clk32", apbc_base + APBC_RTC, 10, 0,
+				  &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-rtc");
+
+	clk =
+	    mmp_clk_register_apbc("pwm0", "vctcxo", apbc_base + APBC_PWM0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
+
+	clk =
+	    mmp_clk_register_apbc("pwm1", "vctcxo", apbc_base + APBC_PWM1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
+
+	clk =
+	    mmp_clk_register_apbc("pwm2", "vctcxo", apbc_base + APBC_PWM2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
+
+	clk =
+	    mmp_clk_register_apbc("pwm3", "vctcxo", apbc_base + APBC_PWM3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
+
+	clk =
+	    clk_register_mux(NULL, "uart0_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart0", "uart0_mux", apbc_base + APBC_UART0,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk =
+	    clk_register_mux(NULL, "uart1_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart1", "uart1_mux", apbc_base + APBC_UART1,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk =
+	    clk_register_mux(NULL, "uart2_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart2", "uart2_mux", apbc_base + APBC_UART2,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk =
+	    clk_register_mux(NULL, "uart3_mux", uart_parent,
+			     ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.3", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("uart3", "uart3_mux", apbc_base + APBC_UART3,
+				  10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
+
+	clk =
+	    clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk =
+	    clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk =
+	    clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp2", "ssp2_mux", apbc_base + APBC_SSP2, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+	clk =
+	    clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+			     ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			     apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+	clk =
+	    mmp_clk_register_apbc("ssp3", "ssp3_mux", apbc_base + APBC_SSP3, 10,
+				  0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+	clk =
+	    clk_register_mux(NULL, "sdh_mux", sdh_parent,
+			     ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh_mux", NULL);
+
+	clk =
+	    clk_register_divider(NULL, "sdh_div", "sdh_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, 10,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "sdh_div", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
+
+	clk =
+	    mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
+
+	clk =
+	    mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
+
+	clk =
+	    mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
+
+	clk =
+	    mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 0x9,
+				  &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk =
+	    clk_register_mux(NULL, "disp0_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk =
+	    clk_register_divider(NULL, "disp0_div", "disp0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, 8,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "disp_div.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("disp0", "disp0_div", apmu_base + APMU_DISP0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+	clk =
+	    clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
+				 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
+				  apmu_base + APMU_DISP0, 0x1024, &clk_lock);
+	clk_register_clkdev(clk, "disp_sphy.0", NULL);
+
+	clk =
+	    clk_register_mux(NULL, "disp1_mux", disp_parent,
+			     ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.1", NULL);
+
+	clk =
+	    clk_register_divider(NULL, "disp1_div", "disp1_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, 8,
+				 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "disp_div.1", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("disp1", "disp1_div", apmu_base + APMU_DISP1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.1");
+
+	clk =
+	    mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
+				  apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
+	clk_register_clkdev(clk, "ccic_arbiter", NULL);
+
+	clk =
+	    clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk =
+	    clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "ccic_div.0", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic0", "ccic0_div", apmu_base + APMU_CCIC0,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
+				  apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
+
+	clk =
+	    mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				  apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+
+	clk =
+	    clk_register_mux(NULL, "ccic1_mux", ccic_parent,
+			     ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			     apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.1", NULL);
+
+	clk =
+	    clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "ccic_div.1", NULL);
+
+	clk =
+	    mmp_clk_register_apmu("ccic1", "ccic1_div", apmu_base + APMU_CCIC1,
+				  0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
+
+	clk =
+	    mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
+				  apmu_base + APMU_CCIC1, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
+
+	clk =
+	    clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
+				 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				 10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
+
+	clk =
+	    mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
+				  apmu_base + APMU_CCIC1, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
+
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Fri Aug 17 02:02:10 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 14:02:10 +0800
Subject: [PATCH V4 5/5] arm: mmp: make all SOCs use common clock by default
In-Reply-To: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345183330-20244-6-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Kconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01..d697d07 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
 config CPU_PXA168
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA168
 
 config CPU_PXA910
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA910
 
 config CPU_MMP2
 	bool
 	select CPU_PJ4
+	select COMMON_CLK
 	help
 	  Select code specific to MMP2. MMP2 is ARMv7 compatible.
 
-- 
1.7.0.4



From shawn.guo at linaro.org  Fri Aug 17 02:14:42 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 17 Aug 2012 14:14:42 +0800
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20524.43620.36859.792122@ipc1.ka-ro>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
 <20120815141606.GA2457@S2101-09.ap.freescale.net>
 <20120815133221.ca88d4ba.akpm@linux-foundation.org>
 <20524.43620.36859.792122@ipc1.ka-ro>
Message-ID: <20120817061439.GF24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 10:08:04AM +0200, Lothar Wa?mann wrote:
> Why not read the register once more in case of a timeout, which
> would guarantee to have a current view of the register contents no
> matter how long the process may have been descheduled before:
> 
> [...]
> static int snvs_rtc_enable_done(int enable, void __iomem *addr)
> {
> 	u32 lpcr = readl(addr + SNVS_LPCR);
> 
> 	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
> }
> [...]
> 	while (1) {
> 		if (svns_rtc_enable_done(enable, data->ioaddr))
> 			break;
> 
> 		if (time_after(jiffies, timeout)) {
> 			if (!svns_rtc_enable_done(enable, data->ioaddr))
> 				return -ETIMEDOUT;
> 		}
> 	}
> 
I'm fine with this solution.  Can you send a formal patch for this?
Then we will have two incremental patches (I already sent the fixed
times loop one) for Andrew to choose one.

-- 
Regards,
Shawn


From josephl at nvidia.com  Fri Aug 17 02:51:21 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 17 Aug 2012 14:51:21 +0800
Subject: [PATCH] ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20
 and Tegra30
Message-ID: <1345186281-3859-1-git-send-email-josephl@nvidia.com>

Currently the tegra20 and tegra30 share the same symbol for
tegra_clk_32k_ops. This will cause a compile error when building
a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and
modify tegra30_clk_32k_ops for tegra30.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/tegra20_clocks.c      |   10 ++++++++++
 arch/arm/mach-tegra/tegra30_clocks.c      |    2 +-
 arch/arm/mach-tegra/tegra30_clocks.h      |    2 +-
 arch/arm/mach-tegra/tegra30_clocks_data.c |    2 +-
 4 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index b073396..ee6922b 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -240,6 +240,16 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
 	return divider_u16 - 1;
 }
 
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+	.recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+
 /* clk_m functions */
 static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
 			unsigned long prate)
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index b2d0864..7dad44d 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -489,7 +489,7 @@ static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
 	return to_clk_tegra(hw)->fixed_rate;
 }
 
-struct clk_ops tegra_clk_32k_ops = {
+struct clk_ops tegra30_clk_32k_ops = {
 	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index aeb4e96..b08b8d9 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -17,7 +17,7 @@
 #ifndef __MACH_TEGRA30_CLOCK_H
 #define __MACH_TEGRA30_CLOCK_H
 
-extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra30_clk_32k_ops;
 extern struct clk_ops tegra30_clk_m_ops;
 extern struct clk_ops tegra_clk_m_div_ops;
 extern struct clk_ops tegra_pll_ref_ops;
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index dad1b2f..2271ac1 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -58,7 +58,7 @@ static struct clk_tegra tegra_clk_32k_hw = {
 static struct clk tegra_clk_32k = {
 	.name = "clk_32k",
 	.hw = &tegra_clk_32k_hw.hw,
-	.ops = &tegra_clk_32k_ops,
+	.ops = &tegra30_clk_32k_ops,
 	.flags = CLK_IS_ROOT,
 };
 
-- 
1.7.0.4



From richard.genoud at gmail.com  Fri Aug 17 02:53:01 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 08:53:01 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <20120816173844.GC7439@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>
 <CACQ1gAhWdwrXEkicy4ij=rukzS-v98bZRr433Qq5M_Dan5JAog@mail.gmail.com>
 <20120816173844.GC7439@game.jcrosoft.org>
Message-ID: <CACQ1gAgqXOJiiocOEMBZiaBchXDhvxqfA7RkiEvCCsv000LQNw@mail.gmail.com>

2012/8/16 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> Maybe it will be more readable if we use something like :
>> atmel,pull-up;
>> atmel,multidrive;
>> atmel,mux="GPIO"
>> atmel,mux="A"
>> ...
>> just my 2 cents...
> no too much data and too much node as you will need a node per pin which we
> tyr to avoid

One one hand we've got a DTS quite concise but unreadable, and on the
other hand, something understandable but huge.
( and it's not specific to your patch Jean-Christophe, on imx6q.dtsi,
it looks worse )
I'm just trying to make sure that having a DTS like that :
nand {
	pinctrl_nand: nand-0 {
		atmel,pins =
			<2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
			2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
	};
};
is better than :
nand {
	pinctrl_nand: nand-0 {
		nand_rdy { atmel,bank = "C"; atmel,pin = <13>; atmel,mux = "GPIO";
atmel,pull-up; };
		nand_ena { atmel,bank = "C"; atmel,pin = <14>; atmel,mux = "GPIO";
atmel,pull-up; };
	};
};
It's what you did in 1st place on linux-at91 git, and I kinda liked it.
But yeah, it's more verbose, and some lines will go beyond 80 columns,
but that's already the case.

Best regards,

Richard.

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From josephl at nvidia.com  Fri Aug 17 02:54:10 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 17 Aug 2012 14:54:10 +0800
Subject: [PATCH] ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops
 name
Message-ID: <1345186450-4517-1-git-send-email-josephl@nvidia.com>

It should use tegra30_audio_sync_clk_ops for tegra30. It will cause
the tegra30 use the wrong audio_sync_clk_ops when build a kernel with
a tegra20 and tegra30 both supported kernel. And building error when
a tegra30-only kernel.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 arch/arm/mach-tegra/tegra30_clocks.h      |    2 +-
 arch/arm/mach-tegra/tegra30_clocks_data.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index b08b8d9..f2f88fe 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -28,7 +28,7 @@ extern struct clk_ops tegra30_plle_ops;
 extern struct clk_ops tegra_cml_clk_ops;
 extern struct clk_ops tegra_pciex_clk_ops;
 extern struct clk_ops tegra_sync_source_ops;
-extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
 extern struct clk_ops tegra30_clk_double_ops;
 extern struct clk_ops tegra_clk_out_ops;
 extern struct clk_ops tegra30_super_ops;
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 2271ac1..3d2e553 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -521,7 +521,7 @@ static const char *mux_audio_sync_clk[] = {
 	};							\
 	static struct clk tegra_##_name = {			\
 		.name = #_name,					\
-		.ops = &tegra_audio_sync_clk_ops,		\
+		.ops = &tegra30_audio_sync_clk_ops,		\
 		.hw = &tegra_##_name##_hw.hw,			\
 		.parent_names = mux_audio_sync_clk,		\
 		.parents = tegra_sync_source_list,		\
-- 
1.7.0.4



From josephl at nvidia.com  Fri Aug 17 03:04:31 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 17 Aug 2012 15:04:31 +0800
Subject: [PATCH] mmc: tegra: convert to device tree support only
Message-ID: <1345187071-6619-1-git-send-email-josephl@nvidia.com>

When compiling a kernel that supports only Tegra30 and not Tegra20,
the SDHCI driver will fail to compile since the of_match_device() failure
fallback code unconditinally references soc_data_tegra20, which is only
compiled in when Tegra20 support is enabled.

In Kernel 3.7, both Tegra20 and Tegra30 will only support booting using
device tree, Hence, there is never a need to fall back to using
soc_data_tegra20 if of_mach_device() fails. Instead, make this case an
error. This removes the reference to soc_data_tegra20, and hence solves
the compile failure.

Signed-off-by: Joseph Lo <josephl at nvidia.com>
---
 drivers/mmc/host/sdhci-tegra.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0810ccc..436186c 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -257,10 +257,9 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 	int rc;
 
 	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
-	if (match)
-		soc_data = match->data;
-	else
-		soc_data = &soc_data_tegra20;
+	if (!match)
+		return -EINVAL;
+	soc_data = match->data;
 
 	host = sdhci_pltfm_init(pdev, soc_data->pdata);
 	if (IS_ERR(host))
-- 
1.7.0.4



From arnd at arndb.de  Fri Aug 17 03:06:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 07:06:07 +0000
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <201208161249.35008.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120816104748.GI31784@mudshark.cambridge.arm.com>
 <201208161249.35008.arnd@arndb.de>
Message-ID: <201208170706.07821.arnd@arndb.de>

On Thursday 16 August 2012, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Will Deacon wrote:
> > On Wed, Aug 15, 2012 at 04:07:36PM +0100, Arnd Bergmann wrote:
> > > On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > > From what I can tell, there is no support for 32 bit processes debugging
> > > 64 bit ones. Is that something you plan to add in the future, or do you
> > > consider that out of scope? In either case, a comment would be helpful.
> > 
> > That can't really work because the debugger won't be able to manipulate
> > child pointers properly without us adding a new ptrace interface (and then,
> > I still wonder about how feasible it really is). I can add a comment.
> 
> You can already have a 32 bit gdb that is able to do remote debugging of
> 64 bit processes using a gdb server process. I guess it wouldn't be
> too strange to have a ptrace extension to allow the native case as well.
> I agree it's not a high priority.
> 
> > > > +long arch_ptrace(struct task_struct *child, long request,
> > > > +		 unsigned long addr, unsigned long data)
> > > > +{
> > > > +	int ret;
> > > > +	unsigned long *datap = (unsigned long __user *)data;
> > > > +
> > > > +	switch (request) {
> > > > +		case PTRACE_GET_THREAD_AREA:
> > > > +			ret = put_user(child->thread.tp_value, datap);
> > > > +			break;
> > > > +
> > > > +#ifdef CONFIG_HAVE_HW_BREAKPOINT
> > > > +		case PTRACE_GETHBPREGS:
> > > > +			ret = ptrace_gethbpregs(child, addr, datap);
> > > > +			break;
> > > > +
> > > > +		case PTRACE_SETHBPREGS:
> > > > +			ret = ptrace_sethbpregs(child, addr, datap);
> > > > +			break;
> > > > +#endif
> > > > +
> > > > +		default:
> > > > +			ret = ptrace_request(child, request, addr, data);
> > > > +			break;
> > > > +	}
> > > > +
> > > > +	return ret;
> > > > +}
> > > 
> > > Is there a reaons why these are not regsets but have their own ptrace
> > > commands? I believe new architectures should generally not add ptrace
> > > commands any more.
> > 
> > I could probably add some regset wrappers about the hbp accessors (which we
> > have to keep for the compat ptrace interface). I'll have a think as it might
> > even make sense to have different regsets for breakpoints and watchpoints.
> > 
> > As for the the tls, is it worth having a regset with only one register?
> 
> Better ask the gdb folks. I'm adding Uli to Cc, maybe he has some insight.

Sorry for the dumb question, but why do you even need PTRACE_GET_THREAD_AREA
for 64 bit tasks? I thought the thread pointer is a GPR, or is this just
for compat tasks?

	Arnd


From gcembed at gmail.com  Fri Aug 17 03:07:57 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Fri, 17 Aug 2012 09:07:57 +0200
Subject: i.MX27 SLCDC driver
Message-ID: <502DEDCD.9050303@gmail.com>

Hello,
I would like to write the driver for SmartLCD controller of i.MX27. This 
kind of interface needs a LCD with an embedded graphic controller 
partially controlled by GPIO. I want to link it with an OLED DD12832.

How have I to write this driver : One driver for SLCDC and one driver 
for DD12832 ? How to link them together ?

Maybe use similar philosophy than soc-camera ?

I have written a driver for kernel 2.6.22 but SLCDC and DD12832 are in 
the same driver.

Thank you for your help.
Ga?tan Carlier

ps : I attach my previous driver for a better overview (this is a 
working draft for test purpose)
-------------- next part --------------
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From tony at atomide.com  Fri Aug 17 03:49:34 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 00:49:34 -0700
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
Message-ID: <20120817074934.GL11011@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > Hi,
> > 
> > * Paul Walmsley <paul at pwsan.com> [120726 13:07]:
> > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > > 
> > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > The rest of the IP block named in the file don't use periods -- which
> > > > is also the style used by the rest of the OMAP SoCs.  Is there
> > > > some reason that these have periods in their names?
> > > 
> > > I've changed those to match the rest of the names, and queued the 
> > > following for 3.7.
> > > 
> > > Thanks again for all the hard work you all put into this.  I realize that 
> > > with all the upstream changes, this was probably a little painful for you. 
> > > But from my perspective you've been a pleasure to work with through the 
> > > process.
> > 
> > As am33xx and omap5 are DT only, we should start moving towards getting
> > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > data from .dtsi files instead.
> > 
> 
> It may not be so straight, given the fact that hwmod layer 
> requires these resources, as hwmod is responsible to configure SYSCONF 
> register of the device (happens very early at core_init level).
> 
> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> core_init call, which will take DT resources and initialize accordingly.

That's for the device reset/idle? We should not do that in hwmod code
except in late_initcall for unclaimed devices as discussed earlier. We
discussed setting up the reset function in the device specific headers
so both device and hwmod code can call them as needed.
 
> Another dependency we will have is on system timers, Jon has already done 
> some initial work on this, but I believe we did not concluded on the it.
> I will re-start the thread again, since in any case DT support in timer is 
> required.

Right.. The timers are a pain right now as they need to be initialized
early. Everything else can and should be initialized at the device probe
time, or from a late_initcall for the unclaimed devices.
 
> > Alternatively we could get rid of the names and match the module based on
> > pa_start and pa_end.
> > 
> 
> Just FYI, from resource perspective, I have changed omap_device layer for DT 
> resources only (still need hwmod resources as explained above) and patch 
> looks something like (and it works) -

Cool yeah few more dependencies remain still.

Regards,

Tony


From tony at atomide.com  Fri Aug 17 03:52:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 00:52:41 -0700
Subject: [PATCH v2 3/3] ARM: OMAP: omap_device: idle devices with no
 driver bound
In-Reply-To: <alpine.DEB.2.00.1208101658130.29149@utopia.booyaka.com>
References: <1344623953-26434-1-git-send-email-khilman@ti.com>
 <1344623953-26434-4-git-send-email-khilman@ti.com>
 <alpine.DEB.2.00.1208101658130.29149@utopia.booyaka.com>
Message-ID: <20120817075240.GM11011@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120810 15:59]:
> On Fri, 10 Aug 2012, Kevin Hilman wrote:
> 
> > Under some circumstances, drivers may leave an omap_device enabled due
> > to driver programming errors, or due to a failure in the drivers
> > probe method.
> > 
> > Using the recently added omap_device driver_status field, we can
> > detect conditions where an omap_device is enabled but has no driver
> > bound and then ensure that the device is properly idled until it can
> > be probed again.
> > 
> > The goal of this feature is not only to detect and warn on these error
> > conditions, but also to ensure that devices are properly put in
> > low-power states so they do not prevent SoC-wide low-power states.
> > 
> > Cc: Paul Walmsley <paul at pwsan.com>
> > Signed-off-by: Kevin Hilman <khilman at ti.com>
> 
> Here's the queued version of this one.

Nice to see this happening :)

Tony


From jason77.wang at gmail.com  Fri Aug 17 04:11:32 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Fri, 17 Aug 2012 16:11:32 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120817034854.GE24242@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk> <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
 <20120816023109.GH2258@S2101-09.ap.freescale.net>
 <20120816223446.GB15883@n2100.arm.linux.org.uk>
 <20120817034854.GE24242@S2101-09.ap.freescale.net>
Message-ID: <502DFCB4.9050502@gmail.com>

Shawn Guo wrote:
> On Thu, Aug 16, 2012 at 11:34:46PM +0100, Russell King - ARM Linux wrote:
>   
>> This doesn't get around the problem that userspace can still effectively
>> issue a DoS against the system by just running a dmb in a tight loop.
>> Or maybe this would have a much more dramatic effect:
>>
>> 	while (1) {
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 		asm("dmb");
>> 	}
>>
>> and make that 3 seconds to get a ps listing turn into something much
>> longer?
>>
>>     
> >From my testing, no, it does not get the thing even worse.
>
>   
>> I think what needs to happen here (while we wait) is someone _with_ the
>> problem needs to experiment, and find out how many nops are needed for
>> the DMB not to have much effect in cpu_relax().  If it turns out we just
>> need to put one nop in, then that's not _too_ bad.
>>     
>
> At least, I need to have 5 nops to get rid of the issue, something like
> below.
>
> Regards,
> Shawn
>
> --8<---
>
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index 99afa74..3e1b099 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
>  unsigned long get_wchan(struct task_struct *p);
>
>  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> -#define cpu_relax()                    smp_mb()
> +#define cpu_relax()    do {                                            \
> +                               asm("nop");                             \
> +                               asm("nop");                             \
> +                               asm("nop");                             \
> +                               asm("nop");                             \
> +                               asm("nop");                             \
> +                               smp_mb();                               \
> +                       } while (0)
>  #else
>  #define cpu_relax()                    barrier()
>  #endif
>
>
>   
In my test, if the number of nops is equal or more than 4, the reset can 
work fine.

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 0511238..3ad4258 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -22,7 +22,11 @@
: : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5\n" \
+ "nop\n" \
+ "nop\n" \
+ "nop\n" \
+ "nop\n" \
: : "r" (0) : "memory")






From hvaibhav at ti.com  Fri Aug 17 04:22:15 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 Aug 2012 08:22:15 +0000
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <20120817074934.GL11011@atomide.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>

On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> > On Tue, Aug 14, 2012 at 13:59:12, Tony Lindgren wrote:
> > > Hi,
> > > 
> > > * Paul Walmsley <paul at pwsan.com> [120726 13:07]:
> > > > On Wed, 25 Jul 2012, Paul Walmsley wrote:
> > > > 
> > > > > These IP blocks and the ECAP IP blocks have periods in their names.
> > > > > The rest of the IP block named in the file don't use periods -- which
> > > > > is also the style used by the rest of the OMAP SoCs.  Is there
> > > > > some reason that these have periods in their names?
> > > > 
> > > > I've changed those to match the rest of the names, and queued the 
> > > > following for 3.7.
> > > > 
> > > > Thanks again for all the hard work you all put into this.  I realize that 
> > > > with all the upstream changes, this was probably a little painful for you. 
> > > > But from my perspective you've been a pleasure to work with through the 
> > > > process.
> > > 
> > > As am33xx and omap5 are DT only, we should start moving towards getting
> > > rid of grep -E "irq|pa_start|pa_end|dma" in this patch and get the standard
> > > data from .dtsi files instead.
> > > 
> > 
> > It may not be so straight, given the fact that hwmod layer 
> > requires these resources, as hwmod is responsible to configure SYSCONF 
> > register of the device (happens very early at core_init level).
> > 
> > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> > core_init call, which will take DT resources and initialize accordingly.
> 
> That's for the device reset/idle? We should not do that in hwmod code
> except in late_initcall for unclaimed devices as discussed earlier. We
> discussed setting up the reset function in the device specific headers
> so both device and hwmod code can call them as needed.
>  

Tony,

May be I didn't understand your above statement, can you please elaborate 
more on "device specific header file"?


Just to highlight, its not only during late_initcall, the _enable and _idle 
functions are getting executed as part of every runtime_pm_get\put_sync from 
the driver.

Are you saying as part of late_initcall, we should initialize " _mpu_rt_va" 
of "struct omap_hwmod"???

Also, as far unclaimed resources is concerned, somewhere you should have 
base addr of the device maintained, right? Currently, hwmod is maintaining 
this data and the execution goes something like,

Core_initcall()
	-> _setup()
		-> _setup_reset()
		-> _idle()


Another biggest worry is, if I play here, it may break existing omap3/4 
Functionality, especially may impact from PM perspective. So I believe, we 
need to have something which adds/cleans-up things in stages.
May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
now??

Any thoughts??

Thanks,
Vaibhav



> > Another dependency we will have is on system timers, Jon has already done 
> > some initial work on this, but I believe we did not concluded on the it.
> > I will re-start the thread again, since in any case DT support in timer is 
> > required.
> 
> Right.. The timers are a pain right now as they need to be initialized
> early. Everything else can and should be initialized at the device probe
> time, or from a late_initcall for the unclaimed devices.
>  
> > > Alternatively we could get rid of the names and match the module based on
> > > pa_start and pa_end.
> > > 
> > 
> > Just FYI, from resource perspective, I have changed omap_device layer for DT 
> > resources only (still need hwmod resources as explained above) and patch 
> > looks something like (and it works) -
> 
> Cool yeah few more dependencies remain still.
> 

> Regards,
> 
> Tony
> 



From voice.shen at atmel.com  Fri Aug 17 04:23:56 2012
From: voice.shen at atmel.com (Bo Shen)
Date: Fri, 17 Aug 2012 16:23:56 +0800
Subject: [PATCH] arm: dts: remove partial parameter in at91sam9g25ek.dts
Message-ID: <1345191836-16523-1-git-send-email-voice.shen@atmel.com>

Remove the partial parameter in at91sam9g25ek.dts file

Signed-off-by: Bo Shen <voice.shen at atmel.com>
---
 arch/arm/boot/dts/at91sam9g25ek.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7829a4d..96514c1 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -15,7 +15,7 @@
 	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
 	chosen {
-		bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+		bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
 	};
 
 	ahb {
-- 
1.7.10



From tony at atomide.com  Fri Aug 17 04:40:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 01:40:47 -0700
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
Message-ID: <20120817084047.GN11011@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> > > 
> > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> > > core_init call, which will take DT resources and initialize accordingly.
> > 
> > That's for the device reset/idle? We should not do that in hwmod code
> > except in late_initcall for unclaimed devices as discussed earlier. We
> > discussed setting up the reset function in the device specific headers
> > so both device and hwmod code can call them as needed.
> 
> May be I didn't understand your above statement, can you please elaborate 
> more on "device specific header file"?

We should have the device drivers idle and reset the devices. But also
hwmod may need to do that for the unclaimed devices for PM to work. 
As the driver may not be even compiled in, the driver specific reset and
idle functions should be static inline functions in the device specific
header file so hwmod code can still call those.
 
> Just to highlight, its not only during late_initcall, the _enable and _idle 
> functions are getting executed as part of every runtime_pm_get\put_sync from 
> the driver.

Right, so no need to initialize those until at driver probe time.
 
> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va" 
> of "struct omap_hwmod"???

I guess either at driver probe for the claimed devices, or at late_initcall
for the unclaimeded devices.

> Also, as far unclaimed resources is concerned, somewhere you should have 
> base addr of the device maintained, right? Currently, hwmod is maintaining 
> this data and the execution goes something like,
> 
> Core_initcall()
> 	-> _setup()
> 		-> _setup_reset()
> 		-> _idle()

For the DT only case also the unclaimed devices can from DT with
status = "disabled". 
 
> Another biggest worry is, if I play here, it may break existing omap3/4 
> Functionality, especially may impact from PM perspective. So I believe, we 
> need to have something which adds/cleans-up things in stages.

It seems that we need three stages: Something early for the timers only,
initialize most things during driver probe, then late_initcall for the
unclaimed devices.

> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
> now??

Sorry I don't follow this part, care to explain a little more?

Regards,

Tony


From santosh.shilimkar at ti.com  Fri Aug 17 04:50:36 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 17 Aug 2012 14:20:36 +0530
Subject: [PATCH v4 4/4] memory: emif: add device tree support to emif
 driver
In-Reply-To: <20120816184502.GA20400@kroah.com>
References: <CAMQu2gz6jdcR4hQPPbmyO8vrkdmppHeCkZmV3_9w27LOzKrUuA@mail.gmail.com>
 <20120630042356.GC1816@kroah.com>
 <CAMQu2gy0MmP4JLW4P1FreJqMMEBYSTjkLHJb8WX=aXLA6hxtZg@mail.gmail.com>
 <CAMQu2gxZ-tWJXAOeh20NsF1uyvs9fqwYtggFv=d7-qX+WFumRQ@mail.gmail.com>
 <CAMQu2gw_ZB7gVyL95B-h27B1fQh0d-YB3weaWRN6DNaGtSypDw@mail.gmail.com>
 <20120717163602.GA7167@kroah.com>
 <CAMQu2gw2Zt3E8byD=_nUXya-xU=gOA71arbbSh7gzxQhet0Vtg@mail.gmail.com>
 <20120717175832.GA20806@kroah.com>
 <CAMQu2gy5dkzoUDy0eFXAKqA-GkBvmmBdQwkfHUaySuKGqF9MKw@mail.gmail.com>
 <CAMQu2gyBQ-iJCLCtPziX8eRm6_eXZfAoDDO0DusKCBQYpaR8jQ@mail.gmail.com>
 <20120816184502.GA20400@kroah.com>
Message-ID: <CAMQu2gwofS1H9yxEt6NMoJoRoNKsc302TxbyGHihuBQBrHCn6g@mail.gmail.com>

On Fri, Aug 17, 2012 at 12:15 AM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Mon, Aug 13, 2012 at 10:57:06AM +0530, Shilimkar, Santosh wrote:
>> Greg,
>>
>> On Wed, Jul 18, 2012 at 12:14 PM, Shilimkar, Santosh
>> <santosh.shilimkar at ti.com> wrote:
>> > On Tue, Jul 17, 2012 at 11:28 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
>> >> On Tue, Jul 17, 2012 at 10:37:45PM +0530, Shilimkar, Santosh wrote:
>> >>> On Tue, Jul 17, 2012 at 10:06 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
>> >>> > On Mon, Jul 09, 2012 at 07:02:36PM +0530, Shilimkar, Santosh wrote:
>> >>> >> Greg,
>> >>> >>
>> >
>> > [..]
>> >
>> >>> >From 74688a87fd490909e9122bf757c0096480e9fc11 Mon Sep 17 00:00:00 2001
>> >>> From: Aneesh V <aneesh at ti.com>
>> >>> Date: Mon, 30 Jan 2012 20:06:30 +0530
>> >>> Subject: [PATCH 4/4] memory: emif: add device tree support to emif driver
>> >>>
>> >>> Device tree support for the EMIF driver. LPDDR2 generic timings
>> >>> extraction from device is managed using couple of helper
>> >>> functions which can be used by other memory controller
>> >>> drivers.
>> >>>
>> >>> Reviewed-by: Benoit Cousson <b-cousson at ti.com>
>> >>> Reviewed-by: Grant Likely <grant.likely at secretlab.ca>
>> >>> Tested-by: Lokesh Vutla <lokeshvutla at ti.com>
>> >>> Signed-off-by: Aneesh V <aneesh at ti.com>
>> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> >>> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
>> >>> ---
>> >>>  drivers/memory/Makefile    |    1 +
>> >>>  drivers/memory/emif.c      |  182 +++++++++++++++++++++++++++++++++++++++++++-
>> >>>  drivers/memory/of_memory.c |  153 +++++++++++++++++++++++++++++++++++++
>> >>>  drivers/memory/of_memory.h |   36 +++++++++
>> >>>  4 files changed, 371 insertions(+), 1 deletion(-)
>> >>>  create mode 100644 drivers/memory/of_memory.c
>> >>>  create mode 100644 drivers/memory/of_memory.h
>> >>>
>> >>> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
>> >>> index 42b3ce9..cd8486b 100644
>> >>> --- a/drivers/memory/Makefile
>> >>> +++ b/drivers/memory/Makefile
>> >>> @@ -2,6 +2,7 @@
>> >>>  # Makefile for memory devices
>> >>>  #
>> >>>
>> >>> +obj-$(CONFIG_OF)             += of_memory.o
>> >>>  obj-$(CONFIG_TI_EMIF)                += emif.o
>> >>>  obj-$(CONFIG_TEGRA20_MC)     += tegra20-mc.o
>> >>>  obj-$(CONFIG_TEGRA30_MC)     += tegra30-mc.o
>> >>> diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
>> >>> index 33a4396..06b4eb7 100644
>> >>> --- a/drivers/memory/emif.c
>> >>> +++ b/drivers/memory/emif.c
>> >>> @@ -18,6 +18,7 @@
>> >>>  #include <linux/platform_device.h>
>> >>>  #include <linux/interrupt.h>
>> >>>  #include <linux/slab.h>
>> >>> +#include <linux/of.h>
>> >>>  #include <linux/debugfs.h>
>> >>>  #include <linux/seq_file.h>
>> >>>  #include <linux/module.h>
>> >>> @@ -25,6 +26,7 @@
>> >>>  #include <linux/spinlock.h>
>> >>>  #include <memory/jedec_ddr.h>
>> >>>  #include "emif.h"
>> >>> +#include "of_memory.h"
>> >>>
>> >>>  /**
>> >>>   * struct emif_data - Per device static data for driver's use
>> >>> @@ -49,6 +51,7 @@
>> >>>   *                           frequency in effect at the moment)
>> >>>   * @plat_data:                       Pointer to saved platform data.
>> >>>   * @debugfs_root:            dentry to the root folder for EMIF in debugfs
>> >>> + * @np_ddr:                  Pointer to ddr device tree node
>> >>>   */
>> >>>  struct emif_data {
>> >>>       u8                              duplicate;
>> >>> @@ -63,6 +66,7 @@ struct emif_data {
>> >>>       struct emif_regs                *curr_regs;
>> >>>       struct emif_platform_data       *plat_data;
>> >>>       struct dentry                   *debugfs_root;
>> >>> +     struct device_node              *np_ddr;
>> >>>  };
>> >>>
>> >>>  static struct emif_data *emif1;
>> >>> @@ -1148,6 +1152,168 @@ static int is_custom_config_valid(struct
>> >>> emif_custom_configs *cust_cfgs,
>> >>>       return valid;
>> >>>  }
>> >>>
>> >>> +#if defined(CONFIG_OF)
>> >>> +static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
>> >>> +             struct emif_data *emif)
>> >>
>> >> Why can't all of this code be in the of_memory.c file?
>> >>
>> > Primarily because the parameters are very much specific to EMIF
>> > memory controller and won't be of much use for other memory controllers.
>> >
>> > Currently the information extracted from DT with these function is like:
>> > - EMIF controller IP version : EMIF_4D or EMIF_4D5
>> > - Which analog phy is integrated : EMIF_ATTILAPHY or EMIF_ATTILAPHY
>> > - IP hardware interface: EMIF Low latency port or sys port interface.
>> > - EMIF connections - Whether EMIF1 only, EMIF2 only or EMIF1 & EMIF2
>> > - Memory connections to EMIF - Same type and size memories or asymmetric
>> > - Chip select usage per controller: Whether CS0, CS1, CS0 & CS1
>> > - ZQ calibration - Per chip select or enable EMIF dual calibration feature.
>> > - Enable/disable EMIF Low power mode and temperature alerts.
>> > - EMIF low power mode configuration:
>> >       - Clock stop, self refresh, Deep power down.
>> >       - Low power time out values for performance and power mode.
>> >       - DDR frequency threshold to switch between power and
>> > performance settings.
>> > - EMIF temperature polling cycle configuration.
>> >
>> > As you can see these are very specific to the EMIF memory controller and hence
>> > I didn't move them to of_memory.c
>> >
>> Do you have any more comment on this patch? If not, I can go ahead and
>> post the refreshed version of the patch.
>
> Please always do, I have no idea what this patch even contained anymore,
> it was a few hundred patches ago that I've reviewed and I have no
> recollection of it...
>
Done. Posted the refresh version [1]. Thanks for review.

Regards
Santosh

[1] https://patchwork.kernel.org/patch/1337871/


From tony at atomide.com  Fri Aug 17 04:56:15 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 01:56:15 -0700
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817085615.GO11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 11:00]:
> +3. Decompress the kernel image
> +------------------------------
> +
> +Requirement: OPTIONAL
> +
> +The AArch64 kernel does not provide a decompressor and therefore
> +requires gzip decompression to be performed by the boot loader if the
> +default Image.gz target is used.  For bootloaders that do not implement
> +this requirement, the larger Image target is available instead.

Maybe add something here about why AArch64 does not provide a
decompressor? That's something everybody will wonder while reading
this part.

> +- Caches, MMUs
> +  The MMU must be off.
> +  Instruction cache may be on or off.
> +  Data cache must be off and invalidated.

External caches must be configured by bootloader but set to disabled
state?

Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 05:04:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:04:52 -0700
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817090451.GP11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 10:57]:
> The virtual memory layout is described in
> Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> the 4KB and 64KB translation table configurations. The SECTION_SIZE is
> 2MB with 4KB page and 512MB with 64KB page configuration.
> 
> PHYS_OFFSET is calculated at run-time and stored in a variable (no
> run-time code patching at this stage).

Care to clarify this part a bit? Is the memory standardized somehow
now and not needed? Or do we still need to add that for various SoCs
later on?

Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 05:19:08 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:19:08 -0700
Subject: [PATCH v2 13/31] arm64: Device specific operations
In-Reply-To: <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-14-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817091908.GQ11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 11:05]:
> --- /dev/null
> +++ b/arch/arm64/mm/ioremap.c
> +
> +void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot)
> +{
> +	return __ioremap_caller(phys_addr, size, prot,
> +				__builtin_return_address(0));
> +}
> +EXPORT_SYMBOL(__ioremap);

>From SoC point of view, we're probably going to need __ioremap_exec()
here too for programming clocks during runtime in SRAM etc. But that
can be added later as needed.

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 05:21:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:21:33 -0700
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817092133.GR11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 11:05]:
> This patch adds SMP initialisation and spinlocks implementation for
> AArch64. The spinlock support uses the new load-acquire/store-release
> instructions to avoid explicit barriers. The architecture also specifies
> that an event is automatically generated when clearing the exclusive
> monitor state to wake up processors in WFE, so there is no need for an
> explicit DSB/SEV instruction sequence. The SEVL instruction is used to
> set the exclusive monitor locally as there is no conditional WFE and a
> branch is more expensive.

Do we always have SMP hardware on arm64? Or are we going to need to
again add smp_on_up support later on?

Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From catalin.marinas at arm.com  Fri Aug 17 05:21:06 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 10:21:06 +0100
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <20120817090451.GP11011@atomide.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
 <20120817090451.GP11011@atomide.com>
Message-ID: <20120817092106.GA24389@arm.com>

On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
> * Catalin Marinas <catalin.marinas at arm.com> [120814 10:57]:
> > The virtual memory layout is described in
> > Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> > the 4KB and 64KB translation table configurations. The SECTION_SIZE is
> > 2MB with 4KB page and 512MB with 64KB page configuration.
> > 
> > PHYS_OFFSET is calculated at run-time and stored in a variable (no
> > run-time code patching at this stage).
> 
> Care to clarify this part a bit? Is the memory standardized somehow
> now and not needed? Or do we still need to add that for various SoCs
> later on?

The memory is not standardised but we have FDT to fully specify it. The
PHYS_OFFSET does not need to be defined, it is automatically detected at
boo-time based on the kernel load address and stored in a variable to be
used later.

> Other than that:
> 
> Acked-by: Tony Lindgren <tony at atomide.com>

Thanks.

-- 
Catalin


From tony at atomide.com  Fri Aug 17 05:29:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:29:06 -0700
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817092904.GS11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 11:00]:
> From: Marc Zyngier <marc.zyngier at arm.com>
> 
> This patch adds support for the ARM generic timers with A64 instructions
> for accessing the timer registers. It uses the physical counter as the
> clock source and the virtual counter as sched_clock.
> 
> The timer frequency can be specified via DT or read from the CNTFRQ_EL0
> register. The physical counter is also accessible from user space
> allowing fast gettimeofday() implementation.

Can we always assume we can boot the kernel with ARM generic timers
and interrupts?

If so, maybe that should be mentioned in the booting requirements doc as
that means we can delay SoC specific initialization quite a bit and boot
with generic kernel to the initramfs ;)

Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 05:32:13 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:32:13 -0700
Subject: [PATCH v2 30/31] arm64: Build infrastructure
In-Reply-To: <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817093213.GT11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 11:00]:
> --- /dev/null
> +++ b/arch/arm64/Kconfig
> @@ -0,0 +1,261 @@
> +config ARM64
> +	def_bool y
> +	select OF
> +	select OF_EARLY_FLATTREE
> +	select IRQ_DOMAIN
> +	select HAVE_AOUT
> +	select HAVE_DMA_ATTRS
> +	select HAVE_DMA_API_DEBUG
> +	select HAVE_IDE
> +	select HAVE_MEMBLOCK
> +	select RTC_LIB
> +	select SYS_SUPPORTS_APM_EMULATION
> +	select HAVE_GENERIC_DMA_COHERENT
> +	select GENERIC_IOMAP
> +	select HAVE_IRQ_WORK
> +	select HAVE_PERF_EVENTS
> +	select HAVE_ARCH_TRACEHOOK
> +	select PERF_USE_VMALLOC
> +	select HAVE_HW_BREAKPOINT if PERF_EVENTS
> +	select HAVE_GENERIC_HARDIRQS
> +	select GENERIC_HARDIRQS_NO_DEPRECATED
> +	select HAVE_SPARSE_IRQ
> +	select SPARSE_IRQ
> +	select GENERIC_IRQ_SHOW
> +	select GENERIC_SMP_IDLE_THREAD
> +	select NO_BOOTMEM
> +	help
> +	  ARM 64-bit (AArch64) Linux support.

Anything we should select here for ARM generic timers and
interrupts assuming we can always expect to boot using those?

Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From catalin.marinas at arm.com  Fri Aug 17 05:32:50 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 10:32:50 +0100
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <20120817092133.GR11011@atomide.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
 <20120817092133.GR11011@atomide.com>
Message-ID: <20120817093250.GB24389@arm.com>

On Fri, Aug 17, 2012 at 10:21:33AM +0100, Tony Lindgren wrote:
> * Catalin Marinas <catalin.marinas at arm.com> [120814 11:05]:
> > This patch adds SMP initialisation and spinlocks implementation for
> > AArch64. The spinlock support uses the new load-acquire/store-release
> > instructions to avoid explicit barriers. The architecture also specifies
> > that an event is automatically generated when clearing the exclusive
> > monitor state to wake up processors in WFE, so there is no need for an
> > explicit DSB/SEV instruction sequence. The SEVL instruction is used to
> > set the exclusive monitor locally as there is no conditional WFE and a
> > branch is more expensive.
> 
> Do we always have SMP hardware on arm64? Or are we going to need to
> again add smp_on_up support later on?

There isn't anything in the architecture specs that mandates multiple
cores but given the current trend it's very likely that we'll always
have MP.

An improvement in AArch64 is that we can use the SMP cache/TLB ops (the
inner shareable variants) even on a UP system so there is no need for
run-time code patching for correct execution.

-- 
Catalin


From tony at atomide.com  Fri Aug 17 05:36:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:36:59 -0700
Subject: [PATCH v2 00/31] AArch64 Linux kernel port
In-Reply-To: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120817093659.GU11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120814 10:54]:
> This is the 2nd version of the set of patches implementing Linux kernel
> support for the 64-bit ARM architecture (AArch64). Thanks to all who
> provided feedback on the previous version.

I've looked at these patches mostly from supporting SoCs point of view
and made few minor comments. It's nice to see that at least so far I did
not spot mutually exlusive #ifdef else stuff that's been causing major issues
supporting multiple SoCs with the current ARMs :) So all these patches,
feel free to add:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 05:38:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:38:22 -0700
Subject: [PATCH v2 04/31] arm64: MMU definitions
In-Reply-To: <20120817092106.GA24389@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-5-git-send-email-catalin.marinas@arm.com>
 <20120817090451.GP11011@atomide.com>
 <20120817092106.GA24389@arm.com>
Message-ID: <20120817093822.GV11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120817 02:21]:
> On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote:
> > * Catalin Marinas <catalin.marinas at arm.com> [120814 10:57]:
> > > The virtual memory layout is described in
> > > Documentation/arm64/memory.txt. This patch adds the MMU definitions for
> > > the 4KB and 64KB translation table configurations. The SECTION_SIZE is
> > > 2MB with 4KB page and 512MB with 64KB page configuration.
> > > 
> > > PHYS_OFFSET is calculated at run-time and stored in a variable (no
> > > run-time code patching at this stage).
> > 
> > Care to clarify this part a bit? Is the memory standardized somehow
> > now and not needed? Or do we still need to add that for various SoCs
> > later on?
> 
> The memory is not standardised but we have FDT to fully specify it. The
> PHYS_OFFSET does not need to be defined, it is automatically detected at
> boo-time based on the kernel load address and stored in a variable to be
> used later.

OK nice thanks.

Tony


From tony at atomide.com  Fri Aug 17 05:39:12 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:39:12 -0700
Subject: [PATCH v2 15/31] arm64: SMP support
In-Reply-To: <20120817093250.GB24389@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-16-git-send-email-catalin.marinas@arm.com>
 <20120817092133.GR11011@atomide.com>
 <20120817093250.GB24389@arm.com>
Message-ID: <20120817093912.GW11011@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [120817 02:33]:
> On Fri, Aug 17, 2012 at 10:21:33AM +0100, Tony Lindgren wrote:
> > * Catalin Marinas <catalin.marinas at arm.com> [120814 11:05]:
> > > This patch adds SMP initialisation and spinlocks implementation for
> > > AArch64. The spinlock support uses the new load-acquire/store-release
> > > instructions to avoid explicit barriers. The architecture also specifies
> > > that an event is automatically generated when clearing the exclusive
> > > monitor state to wake up processors in WFE, so there is no need for an
> > > explicit DSB/SEV instruction sequence. The SEVL instruction is used to
> > > set the exclusive monitor locally as there is no conditional WFE and a
> > > branch is more expensive.
> > 
> > Do we always have SMP hardware on arm64? Or are we going to need to
> > again add smp_on_up support later on?
> 
> There isn't anything in the architecture specs that mandates multiple
> cores but given the current trend it's very likely that we'll always
> have MP.
> 
> An improvement in AArch64 is that we can use the SMP cache/TLB ops (the
> inner shareable variants) even on a UP system so there is no need for
> run-time code patching for correct execution.

That's good to hear!

Tony


From santosh.shilimkar at ti.com  Fri Aug 17 05:41:10 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 Aug 2012 15:11:10 +0530
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
Message-ID: <502E11B6.4020104@ti.com>

On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> The patch adds the kernel booting and the initial setup code.
> Documentation/arm64/booting.txt describes the booting protocol on the
> AArch64 Linux kernel. This is subject to change following the work on
> boot standardisation, ACPI.
>
> Signed-off-by: Will Deacon<will.deacon at arm.com>
> Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
> ---
>   Documentation/arm64/booting.txt |  141 +++++++++++
>   arch/arm64/include/asm/setup.h  |   26 ++
>   arch/arm64/kernel/head.S        |  521 +++++++++++++++++++++++++++++++++++++++
>   arch/arm64/kernel/setup.c       |  357 +++++++++++++++++++++++++++
>   4 files changed, 1045 insertions(+), 0 deletions(-)
>   create mode 100644 Documentation/arm64/booting.txt
>   create mode 100644 arch/arm64/include/asm/setup.h
>   create mode 100644 arch/arm64/kernel/head.S
>   create mode 100644 arch/arm64/kernel/setup.c
>
> diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt
> new file mode 100644
> index 0000000..3197820
> --- /dev/null
> +++ b/Documentation/arm64/booting.txt

[...]

> +
> +The boot loader is expected to enter the kernel on each CPU in the
> +following manner:
> +
> +- The primary CPU must jump directly to the first instruction of the
> +  kernel image.  The device tree blob passed by this CPU must contain
> +  for each CPU node:
> +
> +    1. An 'enable-method' property. Currently, the only supported value
> +       for this field is the string "spin-table".
> +
> +    2. A 'cpu-release-addr' property identifying a 64-bit,
> +       zero-initialised memory location.
> +
> +  It is expected that the bootloader will generate these device tree
> +  properties and insert them into the blob prior to kernel entry.
> +
> +- Any secondary CPUs must spin outside of the kernel in a reserved area
> +  of memory (communicated to the kernel by a /memreserve/ region in the
> +  device tree) polling their cpu-release-addr location, which must be
> +  contained in the reserved region.  A wfe instruction may be inserted
> +  to reduce the overhead of the busy-loop and a sev will be issued by
> +  the primary CPU.  When a read of the location pointed to by the
> +  cpu-release-addr returns a non-zero value, the CPU must jump directly
> +  to this value.

So you expect all the secondary CPUs to be in wakeup state and probably
looping in WFE for a signal from kernel to boot. There is one issue
with this requirement though. For large CPU system, you need to reset
all the CPUs and hit this waiting loop. This will lead to large inrush
current need at bootup which may be not be supported. To avoid this
issue, secondary CPUs are kept in OFF state and then they are woken
up from kernel one by one whenever they need to be brought into the
system. This requirement should be considered.


> diff --git a/arch/arm64/include/asm/setup.h b/arch/arm64/include/asm/setup.h
> new file mode 100644
> index 0000000..d766493
> --- /dev/null
> +++ b/arch/arm64/include/asm/setup.h
> @@ -0,0 +1,26 @@
> +/*
> + * Based on arch/arm/include/asm/setup.h
> + *
> + * Copyright (C) 1997-1999 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_SETUP_H
> +#define __ASM_SETUP_H
> +
> +#include<linux/types.h>
> +
> +#define COMMAND_LINE_SIZE 1024
> +
> +#endif
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> new file mode 100644
> index 0000000..34ccdc0
> --- /dev/null
> +++ b/arch/arm64/kernel/head.S
> @@ -0,0 +1,521 @@
> +/*
> + * Low-level CPU initialisation
> + * Based on arch/arm/kernel/head.S
> + *
> + * Copyright (C) 1994-2002 Russell King
> + * Copyright (C) 2003-2012 ARM Ltd.
> + * Authors:	Catalin Marinas<catalin.marinas at arm.com>
> + *		Will Deacon<will.deacon at arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +

[..]

> +
> +	/*
> +	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
> +	 */
> +	b	stext				// branch to kernel start, magic
> +	.long	0				// reserved
> +	.quad	TEXT_OFFSET			// Image load offset from start of RAM
> +	.quad	0				// reserved
> +	.quad	0				// reserved
> +

Minor nit. Avoid C++ commenting style "//"  here and rest of the patch.

Regards
santosh



From catalin.marinas at arm.com  Fri Aug 17 05:46:02 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 10:46:02 +0100
Subject: [PATCH v2 30/31] arm64: Build infrastructure
In-Reply-To: <20120817093213.GT11011@atomide.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-31-git-send-email-catalin.marinas@arm.com>
 <20120817093213.GT11011@atomide.com>
Message-ID: <20120817094602.GC24389@arm.com>

On Fri, Aug 17, 2012 at 10:32:13AM +0100, Tony Lindgren wrote:
> * Catalin Marinas <catalin.marinas at arm.com> [120814 11:00]:
> > --- /dev/null
> > +++ b/arch/arm64/Kconfig
> > @@ -0,0 +1,261 @@
> > +config ARM64
> > +	def_bool y
> > +	select OF
> > +	select OF_EARLY_FLATTREE
> > +	select IRQ_DOMAIN
> > +	select HAVE_AOUT
> > +	select HAVE_DMA_ATTRS
> > +	select HAVE_DMA_API_DEBUG
> > +	select HAVE_IDE
> > +	select HAVE_MEMBLOCK
> > +	select RTC_LIB
> > +	select SYS_SUPPORTS_APM_EMULATION
> > +	select HAVE_GENERIC_DMA_COHERENT
> > +	select GENERIC_IOMAP
> > +	select HAVE_IRQ_WORK
> > +	select HAVE_PERF_EVENTS
> > +	select HAVE_ARCH_TRACEHOOK
> > +	select PERF_USE_VMALLOC
> > +	select HAVE_HW_BREAKPOINT if PERF_EVENTS
> > +	select HAVE_GENERIC_HARDIRQS
> > +	select GENERIC_HARDIRQS_NO_DEPRECATED
> > +	select HAVE_SPARSE_IRQ
> > +	select SPARSE_IRQ
> > +	select GENERIC_IRQ_SHOW
> > +	select GENERIC_SMP_IDLE_THREAD
> > +	select NO_BOOTMEM
> > +	help
> > +	  ARM 64-bit (AArch64) Linux support.
> 
> Anything we should select here for ARM generic timers and
> interrupts assuming we can always expect to boot using those?

There is an entry in drivers/clocksource/Kconfig:

config CLKSRC_ARM_GENERIC
	def_bool y if ARM64

I will have something similar for the GIC but the model does not
currently support GICv3 to be able to test. I'll publish a branch with
example SoC code (for the model) and that adds GIC support into
drivers/irqchip/ with the address information from FDT. The per-CPU GIC
initialisation is done via a CPU notifier to decouple this from the SoC
code (I think even on 32-bit ARM it could be done in the same way,
gic_secondary_init() always takes 0 as argument.

-- 
Catalin


From richard.genoud at gmail.com  Fri Aug 17 05:47:23 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 11:47:23 +0200
Subject: [PATCH] BUG: clk_find() misses some clocks
Message-ID: <1345196843-23059-1-git-send-email-richard.genoud@gmail.com>

if a clock is declared like that:
CLKDEV_CON_DEV_ID("pioA", "fffff400.gpio", &pioAB_clk)
(so, dev_id AND con_id are defined)
and the driver looks for a dev_id (but no specific con_id) like that:
clock = clk_get(&pdev->dev, NULL);

The clock won't be found:

if (dev_id)
	best_possible += 2; /* dev_id != NULL */
if (con_id)
	best_possible += 1; /* con_id == NULL */
/* => so best possible == 2 */

list_for_each_entry(p, &clocks, node) {
	match = 0;
/*
 * checking p->dev_id = "fffff400.gpio" and p->con_id = "pioA"
 * against dev_id = "fffff400.gpio" and con_id = NULL
 */
	if (p->dev_id) { /* ok, p->dev_id exists */
	 /* and, we are lucky, there's a match ! \o/ */
		if (!dev_id || strcmp(p->dev_id, dev_id))
			continue;
		match += 2;
	}
/* so we have match == 2 */

	if (p->con_id) {
		/* p->con_id is not null */
		if (!con_id || strcmp(p->con_id, con_id))
		/*
		 * too bad !! con_id is null !
		 * even if we have best_possible == match
		 * our clock won't be selected
		 */
			continue;
		match += 1;
	}

	if (match > best_found) {
		cl = p;
		if (match != best_possible)
			best_found = match;
		else
			break;
	}
}

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/clk/clkdev.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index d423c9b..e28b120 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -114,13 +114,13 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 
 	list_for_each_entry(p, &clocks, node) {
 		match = 0;
-		if (p->dev_id) {
-			if (!dev_id || strcmp(p->dev_id, dev_id))
+		if (p->dev_id && dev_id) {
+			if (strcmp(p->dev_id, dev_id))
 				continue;
 			match += 2;
 		}
-		if (p->con_id) {
-			if (!con_id || strcmp(p->con_id, con_id))
+		if (p->con_id && con_id) {
+			if (strcmp(p->con_id, con_id))
 				continue;
 			match += 1;
 		}
-- 
1.7.2.5



From hvaibhav at ti.com  Fri Aug 17 05:51:00 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 Aug 2012 09:51:00 +0000
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <20120817084047.GN11011@atomide.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
 <20120817084047.GN11011@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>

On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
> > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> > > > 
> > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> > > > core_init call, which will take DT resources and initialize accordingly.
> > > 
> > > That's for the device reset/idle? We should not do that in hwmod code
> > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > discussed setting up the reset function in the device specific headers
> > > so both device and hwmod code can call them as needed.
> > 
> > May be I didn't understand your above statement, can you please elaborate 
> > more on "device specific header file"?
> 
> We should have the device drivers idle and reset the devices. But also
> hwmod may need to do that for the unclaimed devices for PM to work. 
> As the driver may not be even compiled in, the driver specific reset and
> idle functions should be static inline functions in the device specific
> header file so hwmod code can still call those.
>  

How about mapping the address of the devices?

Some more thoughts on the similar line on unclaimed devices -
As par of late_initcall(), traverse all the DTB nodes and for each node with 
"state = disabled", we can do something like,

Late_initcall()
	-> Traverse DTB nodes and check for "state = disabled"
		-> Read the "ti,hwmod" entry and get offsets like, sys_config 
		   and reset.
		-> Map the base address
		-> Enable the module/clock
		-> Reset the device
		-> Write to sysc register offset
		-> Disable the module/clock



> > Just to highlight, its not only during late_initcall, the _enable and _idle 
> > functions are getting executed as part of every runtime_pm_get\put_sync from 
> > the driver.
> 
> Right, so no need to initialize those until at driver probe time.
>  

Agreed.

> > Are you saying as part of late_initcall, we should initialize " _mpu_rt_va" 
> > of "struct omap_hwmod"???
> 
> I guess either at driver probe for the claimed devices, or at late_initcall
> for the unclaimeded devices.
> 
> > Also, as far unclaimed resources is concerned, somewhere you should have 
> > base addr of the device maintained, right? Currently, hwmod is maintaining 
> > this data and the execution goes something like,
> > 
> > Core_initcall()
> > 	-> _setup()
> > 		-> _setup_reset()
> > 		-> _idle()
> 
> For the DT only case also the unclaimed devices can from DT with
> status = "disabled". 
>  
> > Another biggest worry is, if I play here, it may break existing omap3/4 
> > Functionality, especially may impact from PM perspective. So I believe, we 
> > need to have something which adds/cleans-up things in stages.
> 
> It seems that we need three stages: Something early for the timers only,
> initialize most things during driver probe, then late_initcall for the
> unclaimed devices.
> 

Most likely yes, or it may even get into more stages.

At the current stage, I really think it would be really nice and beneficial 
for driver developers from the community if they get Linux Boot from 
linux-next/master branch. I have seen lot of community folks are struggling 
with it and they are blocked because we do not have booting kernel on 
BeagleBone.
They always end up patching kernel with HWMOD patch and submit the driver 
patches. So request to consider this cleanup as sequential patch on top of 
original HWMOD patch?


> > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
> > now??
> 
> Sorry I don't follow this part, care to explain a little more?
> 

As per current implementation, we are using HWMOD information to fill the 
platform_device->resources. Even if you pass "reg" and "interrupt" property 
from DT, omap_device layer overwrites it with HWMOD data information.

So what I am trying to propose here is, avoid this overwrite and resources 
(address and interrupt) should strictly gets used from DT blob. Since AM33xx 
and OMAP5 devices are the new devices and supports DT boot only, we can 
implement it easily for them.

Only issue her is, DMA resources, I was going through some of the old email 
archives today, submitted by Benoit and later Jon, but I am still not sure 
how to pass dma_channel to driver as a resource.

Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -

omap_device_alloc ()
{
	...

	res_count = omap_device_count_resources(od);
	if (res_count > pdev->num_resources) {
		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
	      if (!res)
      		goto oda_exit3;

		if (pdev->num_resources && pdev->resource) {
			omap_device_fill_dma_resources(od, res);
			memcpy(&res[pdev->num_resources], pdev->resource,
				sizeof(struct resource) * pdev->num_resources);
			} else {
				omap_device_fill_resources(od, res);
			}
	
		ret = platform_device_add_resources(pdev, res, res_count);
		kfree(res);
	}

	...
}

Thanks,
Vaibhav


From alanbutty12 at gmail.com  Fri Aug 17 05:56:13 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 10:56:13 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch v2
Message-ID: <cover.1345196553.git.alanbutty12@gmail.com>

Fixed some typo's and renamed the leds.
The patch should follow in the next email.
sorry bout subject of the email still getting used to to git and sendmail

Alan M Butler (1):
  ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch v2    
    Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

-- 
1.7.5.4



From alanbutty12 at gmail.com  Fri Aug 17 05:56:14 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 10:56:14 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch v2
 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <cover.1345196553.git.alanbutty12@gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
Message-ID: <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>

---
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 0000000..821a76b
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Iomega StorCenter ix2-200";
+	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk coherent_pool=1M";
+	};
+
+	ocp at f1000000 {
+		i2c at 11000 {
+			status = "okay";
+
+			lm63: lm63 at 4c {
+				compatible = "national,lm63";
+				reg = <0x4c>;
+			};
+		};
+
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at a0000 {
+				label = "env";
+				reg = <0xa0000 0x20000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x100000 0x300000>;
+			};
+
+			partition at 400000 {
+				label = "uInitrd";
+				reg = <0x540000 0x1000000>;
+			};
+		};
+		sata at 80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			label = "status:white:power_led";
+			gpios = <&gpio0 16 0>;
+			linux,default-trigger = "default-on";
+		};
+		health_led1 {
+			label = "status:red:health_led";
+			gpios = <&gpio1 5 0>;
+		};
+		health_led2 {
+			label = "status:white:health_led";
+			gpios = <&gpio1 4 0>;
+		};
+		backup_led {
+			label = "status:blue:backup_led";
+			gpios = <&gpio0 15 0>;
+		};
+	};
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		Power {
+			label = "Power Button";
+			linux,code = <116>;
+			gpios = <&gpio0 14 1>;
+		};
+		Reset {
+			label = "Reset Button";
+			linux,code = <0x198>;
+			gpios = <&gpio0 12 1>;
+		};
+		OTB {
+			label = "OTB Button";
+			linux,code = <133>;
+			gpios = <&gpio1 3 1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..bee8451 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -195,6 +195,13 @@ config MACH_T5325
 	  Say 'Y' here if you want your kernel to support the
 	  HP t5325 Thin Client.
 
+config MACH_IOMEGA_IX2_200_DT
+	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Iomega StorCenter ix2-200 (Flattened Device Tree).
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..f5484dc 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 2a576ab..f8ef771 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..9b3ec17 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
+	if (of_machine_is_compatible("iom,ix2-200"))
+		iomega_ix2_200_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"iom,ix2-200",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 0000000..0c78752
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <net/dsa.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+	.phy_addr       = MV643XX_ETH_PHY_NONE,
+	.speed          = SPEED_1000,
+	.duplex         = DUPLEX_FULL,
+};
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+	MPP12_GPIO,			/* Reset Button */
+	MPP14_GPIO,			/* Power Button */
+	MPP15_GPIO,			/* Backup LED (blue) */
+	MPP16_GPIO,			/* Power LED (white) */
+	MPP35_GPIO,			/* OTB Button */
+	MPP36_GPIO,			/* Rebuild LED (white) */
+	MPP37_GPIO,			/* Health LED (red) */
+	MPP38_GPIO,			/* SATA LED brightness control 1 */
+	MPP39_GPIO,			/* SATA LED brightness control 2 */
+	MPP40_GPIO,			/* Backup LED brightness control 1 */
+	MPP41_GPIO,			/* Backup LED brightness control 2 */
+	MPP42_GPIO,			/* Power LED brightness control 1 */
+	MPP43_GPIO,			/* Power LED brightness control 2 */
+	MPP44_GPIO,			/* Health LED brightness control 1 */
+	MPP45_GPIO,			/* Health LED brightness control 2 */
+	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
+	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
+	0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+	kirkwood_ehci_init();
+
+	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
+	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
+}
+static int __init iomega_ix2_200_pci_init(void)
+{
+	if (of_machine_is_compatible("iom,ix2-200"))
+		kirkwood_pcie_init(KW_PCIE0);
+	return 0;
+}
+subsys_initcall(iomega_ix2_200_pci_init);
+
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..d5d4064 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Fri Aug 17 05:57:20 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 Aug 2012 15:27:20 +0530
Subject: [PATCH v2 09/31] arm64: Cache maintenance routines
In-Reply-To: <1344966752-16102-10-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-10-git-send-email-catalin.marinas@arm.com>
Message-ID: <502E1580.70702@ti.com>

On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> The patch adds functionality required for cache maintenance. The AArch64
> architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may
> have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations
> are automatically broadcast in hardware between CPUs.
>
> Signed-off-by: Will Deacon<will.deacon at arm.com>
> Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
> ---
>   arch/arm64/include/asm/cache.h      |   32 ++++
>   arch/arm64/include/asm/cacheflush.h |  209 ++++++++++++++++++++++++++
>   arch/arm64/include/asm/cachetype.h  |   48 ++++++
>   arch/arm64/mm/cache.S               |  279 +++++++++++++++++++++++++++++++++++
>   arch/arm64/mm/flush.c               |  132 +++++++++++++++++
>   5 files changed, 700 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm64/include/asm/cache.h
>   create mode 100644 arch/arm64/include/asm/cacheflush.h
>   create mode 100644 arch/arm64/include/asm/cachetype.h
>   create mode 100644 arch/arm64/mm/cache.S
>   create mode 100644 arch/arm64/mm/flush.c
>
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> new file mode 100644
> index 0000000..390308a
> --- /dev/null
> +++ b/arch/arm64/include/asm/cache.h
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_CACHE_H
> +#define __ASM_CACHE_H
> +
> +#define L1_CACHE_SHIFT		6
> +#define L1_CACHE_BYTES		(1<<  L1_CACHE_SHIFT)
> +
> +/*
> + * Memory returned by kmalloc() may be used for DMA, so we must make
> + * sure that all such allocations are cache aligned. Otherwise,
> + * unrelated code may cause parts of the buffer to be read into the
> + * cache before the transfer is done, causing old data to be seen by
> + * the CPU.
> + */
> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
> +#define ARCH_SLAB_MINALIGN	8
> +
> +#endif
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> new file mode 100644
> index 0000000..93b5590
> --- /dev/null
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -0,0 +1,209 @@
> +/*
> + * Based on arch/arm/include/asm/cacheflush.h
> + *
> + * Copyright (C) 1999-2002 Russell King.
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_CACHEFLUSH_H
> +#define __ASM_CACHEFLUSH_H
> +
> +#include<linux/mm.h>
> +
> +/*
> + * This flag is used to indicate that the page pointed to by a pte is clean
> + * and does not require cleaning before returning it to the user.
> + */
> +#define PG_dcache_clean PG_arch_1
> +
> +/*
> + *	MM Cache Management
> + *	===================
> + *
> + *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
> + *	implement these methods.
> + *
> + *	Start addresses are inclusive and end addresses are exclusive;
> + *	start addresses should be rounded down, end addresses up.
> + *
> + *	See Documentation/cachetlb.txt for more information.
> + *	Please note that the implementation of these, and the required
> + *	effects are cache-type (VIVT/VIPT/PIPT) specific.
> + *
> + *	flush_cache_kern_all()
> + *
> + *		Unconditionally clean and invalidate the entire cache.
> + *
> + *	flush_cache_user_mm(mm)
> + *
> + *		Clean and invalidate all user space cache entries
> + *		before a change of page tables.
> + *
> + *	flush_cache_user_range(start, end, flags)
> + *
> + *		Clean and invalidate a range of cache entries in the
> + *		specified address space before a change of page tables.
> + *		- start - user start address (inclusive, page aligned)
> + *		- end   - user end address   (exclusive, page aligned)
> + *		- flags - vma->vm_flags field
> + *
> + *	coherent_kern_range(start, end)
> + *
> + *		Ensure coherency between the Icache and the Dcache in the
> + *		region described by start, end.  If you have non-snooping
> + *		Harvard caches, you need to implement this function.
> + *		- start  - virtual start address
> + *		- end    - virtual end address
> + *
> + *	coherent_user_range(start, end)
> + *
> + *		Ensure coherency between the Icache and the Dcache in the
> + *		region described by start, end.  If you have non-snooping
> + *		Harvard caches, you need to implement this function.
> + *		- start  - virtual start address
> + *		- end    - virtual end address
> + *
> + *	flush_kern_dcache_area(kaddr, size)
> + *
> + *		Ensure that the data held in page is written back.
> + *		- kaddr  - page address
> + *		- size   - region size
> + *
> + *	DMA Cache Coherency
> + *	===================
> + *
> + *	dma_flush_range(start, end)
> + *
> + *		Clean and invalidate the specified virtual address range.
> + *		- start  - virtual start address
> + *		- end    - virtual end address
> + */
> +extern void __cpuc_flush_kern_all(void);
> +extern void __cpuc_flush_user_all(void);
> +extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
> +extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
> +extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
> +extern void __cpuc_flush_dcache_area(void *, size_t);
> +
> +/*
> + * These are private to the dma-mapping API.  Do not use directly.
> + * Their sole purpose is to ensure that data held in the cache
> + * is visible to DMA, or data written by DMA to system memory is
> + * visible to the CPU.
> + */
> +extern void dmac_map_area(const void *, size_t, int);
> +extern void dmac_unmap_area(const void *, size_t, int);
> +extern void dmac_flush_range(const void *, const void *);
> +
> +/*
> + * Copy user data from/to a page which is mapped into a different
> + * processes address space.  Really, we want to allow our "user
> + * space" model to handle this.
> + */
> +extern void copy_to_user_page(struct vm_area_struct *, struct page *,
> +	unsigned long, void *, const void *, unsigned long);
> +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
> +	do {							\
> +		memcpy(dst, src, len);				\
> +	} while (0)
> +
> +/*
> + * Convert calls to our calling convention.
> + */
> +#define flush_cache_all()		__cpuc_flush_kern_all()
> +extern void flush_cache_mm(struct mm_struct *mm);
> +extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
> +extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
> +
> +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
> +
> +/*
> + * flush_cache_user_range is used when we want to ensure that the
> + * Harvard caches are synchronised for the user space address range.
> + * This is used for the ARM private sys_cacheflush system call.
> + */
> +#define flush_cache_user_range(start, end) \
> +	__cpuc_coherent_user_range((start)&  PAGE_MASK, PAGE_ALIGN(end))
> +
> +/*
> + * Perform necessary cache operations to ensure that data previously
> + * stored within this range of addresses can be executed by the CPU.
> + */
> +#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)
> +
> +/*
> + * flush_dcache_page is used when the kernel has written to the page
> + * cache page at virtual address page->virtual.
> + *
> + * If this page isn't mapped (ie, page_mapping == NULL), or it might
> + * have userspace mappings, then we _must_ always clean + invalidate
> + * the dcache entries associated with the kernel mapping.
> + *
> + * Otherwise we can defer the operation, and clean the cache when we are
> + * about to change to user space.  This is the same method as used on SPARC64.
> + * See update_mmu_cache for the user space part.
> + */
> +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
> +extern void flush_dcache_page(struct page *);
> +
> +static inline void __flush_icache_all(void)
> +{
> +	asm("ic	ialluis");
> +}
> +
> +#define ARCH_HAS_FLUSH_ANON_PAGE
> +static inline void flush_anon_page(struct vm_area_struct *vma,
> +			 struct page *page, unsigned long vmaddr)
> +{
> +	extern void __flush_anon_page(struct vm_area_struct *vma,
> +				struct page *, unsigned long);
> +	if (PageAnon(page))
> +		__flush_anon_page(vma, page, vmaddr);
> +}
> +
> +#define flush_dcache_mmap_lock(mapping) \
> +	spin_lock_irq(&(mapping)->tree_lock)
> +#define flush_dcache_mmap_unlock(mapping) \
> +	spin_unlock_irq(&(mapping)->tree_lock)
> +
> +#define flush_icache_user_range(vma,page,addr,len) \
> +	flush_dcache_page(page)
> +
> +/*
> + * We don't appear to need to do anything here.  In fact, if we did, we'd
> + * duplicate cache flushing elsewhere performed by flush_dcache_page().
> + */
> +#define flush_icache_page(vma,page)	do { } while (0)
> +
> +/*
> + * flush_cache_vmap() is used when creating mappings (eg, via vmap,
> + * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
> + * caches, since the direct-mappings of these pages may contain cached
> + * data, we need to do a full cache flush to ensure that writebacks
> + * don't corrupt data placed into these pages via the new mappings.
> + */
> +static inline void flush_cache_vmap(unsigned long start, unsigned long end)
> +{
> +	/*
> +	 * set_pte_at() called from vmap_pte_range() does not
> +	 * have a DSB after cleaning the cache line.
> +	 */
> +	dsb();
> +}
> +
> +static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
> +{
> +}
> +
> +#endif
> diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h
> new file mode 100644
> index 0000000..85f5f51
> --- /dev/null
> +++ b/arch/arm64/include/asm/cachetype.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_CACHETYPE_H
> +#define __ASM_CACHETYPE_H
> +
> +#include<asm/cputype.h>
> +
> +#define CTR_L1IP_SHIFT		14
> +#define CTR_L1IP_MASK		3
> +
> +#define ICACHE_POLICY_RESERVED	0
> +#define ICACHE_POLICY_AIVIVT	1
> +#define ICACHE_POLICY_VIPT	2
> +#define ICACHE_POLICY_PIPT	3
> +
> +static inline u32 icache_policy(void)
> +{
> +	return (read_cpuid_cachetype()>>  CTR_L1IP_SHIFT)&  CTR_L1IP_MASK;
> +}
> +
> +/*
> + * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
> + * permitted in the I-cache.
> + */
> +static inline int icache_is_aliasing(void)
> +{
> +	return icache_policy() != ICACHE_POLICY_PIPT;
> +}
> +
> +static inline int icache_is_aivivt(void)
> +{
> +	return icache_policy() == ICACHE_POLICY_AIVIVT;
> +}
> +
> +#endif	/* __ASM_CACHETYPE_H */
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> new file mode 100644
> index 0000000..f4efa04
> --- /dev/null
> +++ b/arch/arm64/mm/cache.S
> @@ -0,0 +1,279 @@
> +/*
> + * Cache maintenance
> + *
> + * Copyright (C) 2001 Deep Blue Solutions Ltd.
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +
> +#include<linux/linkage.h>
> +#include<linux/init.h>
> +#include<asm/assembler.h>
> +
> +#include "proc-macros.S"
> +
> +/*
> + *	__cpuc_flush_dcache_all()
> + *
> + *	Flush the whole D-cache.
> + *
> + *	Corrupted registers: x0-x7, x9-x11
> + */
> +ENTRY(__cpuc_flush_dcache_all)
> +	dsb	sy				// ensure ordering with previous memory accesses
> +	mrs	x0, clidr_el1			// read clidr
> +	and	x3, x0, #0x7000000		// extract loc from clidr
> +	lsr	x3, x3, #23			// left align loc bit field
> +	cbz	x3, finished			// if loc is 0, then no need to clean
> +	mov	x10, #0				// start clean at cache level 0
> +loop1:
> +	add	x2, x10, x10, lsr #1		// work out 3x current cache level
> +	lsr	x1, x0, x2			// extract cache type bits from clidr
> +	and	x1, x1, #7			// mask of the bits for current cache only
> +	cmp	x1, #2				// see what cache we have at this level
> +	b.lt	skip				// skip if no cache, or just i-cache
> +	save_and_disable_irqs x9		// make CSSELR and CCSIDR access atomic
> +	msr	csselr_el1, x10			// select current cache level in csselr
> +	isb					// isb to sych the new cssr&csidr
> +	mrs	x1, ccsidr_el1			// read the new ccsidr
> +	restore_irqs x9
> +	and	x2, x1, #7			// extract the length of the cache lines
> +	add	x2, x2, #4			// add 4 (line length offset)
> +	mov	x4, #0x3ff
> +	and	x4, x4, x1, lsr #3		// find maximum number on the way size
> +	clz	x5, x4				// find bit position of way size increment
> +	mov	x7, #0x7fff
> +	and	x7, x7, x1, lsr #13		// extract max number of the index size
> +loop2:
> +	mov	x9, x4				// create working copy of max way size
> +loop3:
> +	lsl	x6, x9, x5
> +	orr	x11, x10, x6			// factor way and cache number into x11
> +	lsl	x6, x7, x2
> +	orr	x11, x11, x6			// factor index number into x11
> +	dc	cisw, x11			// clean&  invalidate by set/way
> +	subs	x9, x9, #1			// decrement the way
> +	b.ge	loop3
> +	subs	x7, x7, #1			// decrement the index
> +	b.ge	loop2
> +skip:
> +	add	x10, x10, #2			// increment cache number
> +	cmp	x3, x10
> +	b.gt	loop1
> +finished:
> +	mov	x10, #0				// swith back to cache level 0
> +	msr	csselr_el1, x10			// select current cache level in csselr
> +	dsb	sy
> +	isb
> +	ret
> +ENDPROC(__cpuc_flush_dcache_all)
> +
>
We have discussed the need of cache maintenance by
level kind of API for ARMv7 (A15).

Shouldn't we add such API for arm64 as well ?

Regards
Santosh



From linux at arm.linux.org.uk  Fri Aug 17 05:58:37 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 Aug 2012 10:58:37 +0100
Subject: [PATCH] BUG: clk_find() misses some clocks
In-Reply-To: <1345196843-23059-1-git-send-email-richard.genoud@gmail.com>
References: <1345196843-23059-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120817095837.GM18957@n2100.arm.linux.org.uk>

Please read the comments on the function:

 * Find the correct struct clk for the device and connection ID.
 * We do slightly fuzzy matching here:
 *  An entry with a NULL ID is assumed to be a wildcard.
 *  If an entry has a device ID, it must match
 *  If an entry has a connection ID, it must match
 * Then we take the most specific entry - with the following
 * order of precedence: dev+con > dev only > con only.

On Fri, Aug 17, 2012 at 11:47:23AM +0200, Richard Genoud wrote:
> if a clock is declared like that:
> CLKDEV_CON_DEV_ID("pioA", "fffff400.gpio", &pioAB_clk)

So you've declared it with a connection ID.  Therefore, as the comment
above says, "it must match" what the driver is asking for.

It's not a bug, this is done intentionally so that mismatches do not
occur.


From tony at atomide.com  Fri Aug 17 05:58:51 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 02:58:51 -0700
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
 <20120817084047.GN11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
Message-ID: <20120817095851.GX11011@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120817 02:51]:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
> > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> > > > > 
> > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> > > > > core_init call, which will take DT resources and initialize accordingly.
> > > > 
> > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > discussed setting up the reset function in the device specific headers
> > > > so both device and hwmod code can call them as needed.
> > > 
> > > May be I didn't understand your above statement, can you please elaborate 
> > > more on "device specific header file"?
> > 
> > We should have the device drivers idle and reset the devices. But also
> > hwmod may need to do that for the unclaimed devices for PM to work. 
> > As the driver may not be even compiled in, the driver specific reset and
> > idle functions should be static inline functions in the device specific
> > header file so hwmod code can still call those.
> >  
> 
> How about mapping the address of the devices?

That should be done based on the iorange coming from DT during the driver
probe. The range in hwmod can be populated at that point too if needed.
 
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with 
> "state = disabled", we can do something like,
> 
> Late_initcall()
> 	-> Traverse DTB nodes and check for "state = disabled"
> 		-> Read the "ti,hwmod" entry and get offsets like, sys_config 
> 		   and reset.
> 		-> Map the base address
> 		-> Enable the module/clock
> 		-> Reset the device
> 		-> Write to sysc register offset
> 		-> Disable the module/clock
> 
> 
> 
> > > Just to highlight, its not only during late_initcall, the _enable and _idle 
> > > functions are getting executed as part of every runtime_pm_get\put_sync from 
> > > the driver.

Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
calls for the unclaimed devicdes.

> At the current stage, I really think it would be really nice and beneficial 
> for driver developers from the community if they get Linux Boot from 
> linux-next/master branch. I have seen lot of community folks are struggling 
> with it and they are blocked because we do not have booting kernel on 
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver 
> patches. So request to consider this cleanup as sequential patch on top of 
> original HWMOD patch?

Yes I'm fine merging the data as is, just trying to figure out how to sort
out the issues for future. 
 
> > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
> > > now??
> > 
> > Sorry I don't follow this part, care to explain a little more?
> > 
> 
> As per current implementation, we are using HWMOD information to fill the 
> platform_device->resources. Even if you pass "reg" and "interrupt" property 
> from DT, omap_device layer overwrites it with HWMOD data information.
> 
> So what I am trying to propose here is, avoid this overwrite and resources 
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx 
> and OMAP5 devices are the new devices and supports DT boot only, we can 
> implement it easily for them.

Yes I agree. And then we should also drop the data from hwmod when it's no
longer needed.
 
> Only issue her is, DMA resources, I was going through some of the old email 
> archives today, submitted by Benoit and later Jon, but I am still not sure 
> how to pass dma_channel to driver as a resource.

Hmm I thought that got merged already? Anyways, the iorange and interrupts
are standard resources that should exist in every device entry in .dts files.

Regards,

Tony 


From artem.bityutskiy at linux.intel.com  Fri Aug 17 06:09:31 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Fri, 17 Aug 2012 13:09:31 +0300
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <1345122935-22115-1-git-send-email-stigge@antcom.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
Message-ID: <1345198171.27859.39.camel@sauron.fi.intel.com>

On Thu, 2012-08-16 at 15:15 +0200, Roland Stigge wrote:
> The SLC and MLC NAND drivers now need their dma_filter callbacks via platform
> data to make them independent of single DMA engine drivers.
> 
> (This also helps fixing build errors of the SLC and MLC drivers when building
> as modules because direct access to AMBA dma filter functions isn't available
> via export.)
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Pushed the 3 patches to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From catalin.marinas at arm.com  Fri Aug 17 06:05:33 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 11:05:33 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <502E11B6.4020104@ti.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <502E11B6.4020104@ti.com>
Message-ID: <20120817100533.GE24389@arm.com>

On Fri, Aug 17, 2012 at 10:41:10AM +0100, Santosh Shilimkar wrote:
> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> > +The boot loader is expected to enter the kernel on each CPU in the
> > +following manner:
> > +
> > +- The primary CPU must jump directly to the first instruction of the
> > +  kernel image.  The device tree blob passed by this CPU must contain
> > +  for each CPU node:
> > +
> > +    1. An 'enable-method' property. Currently, the only supported value
> > +       for this field is the string "spin-table".
> > +
> > +    2. A 'cpu-release-addr' property identifying a 64-bit,
> > +       zero-initialised memory location.
> > +
> > +  It is expected that the bootloader will generate these device tree
> > +  properties and insert them into the blob prior to kernel entry.
> > +
> > +- Any secondary CPUs must spin outside of the kernel in a reserved area
> > +  of memory (communicated to the kernel by a /memreserve/ region in the
> > +  device tree) polling their cpu-release-addr location, which must be
> > +  contained in the reserved region.  A wfe instruction may be inserted
> > +  to reduce the overhead of the busy-loop and a sev will be issued by
> > +  the primary CPU.  When a read of the location pointed to by the
> > +  cpu-release-addr returns a non-zero value, the CPU must jump directly
> > +  to this value.
> 
> So you expect all the secondary CPUs to be in wakeup state and probably
> looping in WFE for a signal from kernel to boot. There is one issue
> with this requirement though. For large CPU system, you need to reset
> all the CPUs and hit this waiting loop. This will lead to large inrush
> current need at bootup which may be not be supported. To avoid this
> issue, secondary CPUs are kept in OFF state and then they are woken
> up from kernel one by one whenever they need to be brought into the
> system. This requirement should be considered.

I agree, this part will be extended. That's one method that we currently
support and suitable to the model.

The better method is the SMC standardisation that Charles Garcia-Tobin
has written (to be made available soon) and was presented at the last
Linaro Connect in HK. Given that the CPU power is usually controlled by
the secure side, we'll ask for an SMC to be issued for waking up
secondary CPUs, so it's up to the secure firmware to write the correct
hardware registers.

> > --- /dev/null
> > +++ b/arch/arm64/kernel/head.S
> [..]
> > +	/*
> > +	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
> > +	 */
> > +	b	stext				// branch to kernel start, magic
> > +	.long	0				// reserved
> > +	.quad	TEXT_OFFSET			// Image load offset from start of RAM
> > +	.quad	0				// reserved
> > +	.quad	0				// reserved
> > +
> 
> Minor nit. Avoid C++ commenting style "//"  here and rest of the patch.

That's not C++ comment style, it's the *official* assembly comment style
for AArch64 ('@' is no longer supported).

-- 
Catalin


From santosh.shilimkar at ti.com  Fri Aug 17 06:06:11 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 Aug 2012 15:36:11 +0530
Subject: [PATCH v2 05/31] arm64: MMU initialisation
In-Reply-To: <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
Message-ID: <502E1793.9080605@ti.com>

On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> This patch contains the initialisation of the memory blocks, MMU
> attributes and the memory map. Only five memory types are defined:
> Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
> Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
> Cache policies are supported via the memory attributes register
> (MAIR_EL1) and only affect the Normal Cacheable mappings.
>
> This patch also adds the SPARSEMEM_VMEMMAP initialisation.
>
> Signed-off-by: Will Deacon<will.deacon at arm.com>
> Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
> ---

Whats the difference between Device nGnRE and Device GRE ?
Sorry, I haven't gone through the specs yet and hence the
question.

>   arch/arm64/include/asm/memblock.h |   21 ++
>   arch/arm64/mm/init.c              |  416 +++++++++++++++++++++++++++++++++++++
>   arch/arm64/mm/mmu.c               |  395 +++++++++++++++++++++++++++++++++++
>   3 files changed, 832 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm64/include/asm/memblock.h
>   create mode 100644 arch/arm64/mm/init.c
>   create mode 100644 arch/arm64/mm/mmu.c
>
> diff --git a/arch/arm64/include/asm/memblock.h b/arch/arm64/include/asm/memblock.h
> new file mode 100644
> index 0000000..6afeed2
> --- /dev/null
> +++ b/arch/arm64/include/asm/memblock.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +#ifndef __ASM_MEMBLOCK_H
> +#define __ASM_MEMBLOCK_H
> +
> +extern void arm64_memblock_init(void);
> +
> +#endif
> diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
> new file mode 100644
> index 0000000..c87583d
> --- /dev/null
> +++ b/arch/arm64/mm/init.c
> @@ -0,0 +1,416 @@
> +/*
> + * Based on arch/arm/mm/init.c
> + *
> + * Copyright (C) 1995-2005 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +
> +#include<linux/kernel.h>
> +#include<linux/export.h>
> +#include<linux/errno.h>
> +#include<linux/swap.h>
> +#include<linux/init.h>
> +#include<linux/bootmem.h>
> +#include<linux/mman.h>
> +#include<linux/nodemask.h>
> +#include<linux/initrd.h>
> +#include<linux/gfp.h>
> +#include<linux/memblock.h>
> +#include<linux/sort.h>
> +#include<linux/of_fdt.h>
> +
> +#include<asm/prom.h>
> +#include<asm/sections.h>
> +#include<asm/setup.h>
> +#include<asm/sizes.h>
> +#include<asm/tlb.h>
> +
> +#include "mm.h"
> +
> +static unsigned long phys_initrd_start __initdata = 0;
> +static unsigned long phys_initrd_size __initdata = 0;
> +
> +phys_addr_t memstart_addr __read_mostly = 0;
> +
> +void __init early_init_dt_setup_initrd_arch(unsigned long start,
> +					    unsigned long end)
> +{
> +	phys_initrd_start = start;
> +	phys_initrd_size = end - start;
> +}
> +
> +static int __init early_initrd(char *p)
> +{
> +	unsigned long start, size;
> +	char *endp;
> +
> +	start = memparse(p,&endp);
> +	if (*endp == ',') {
> +		size = memparse(endp + 1, NULL);
> +
> +		phys_initrd_start = start;
> +		phys_initrd_size = size;
> +	}
> +	return 0;
> +}
> +early_param("initrd", early_initrd);
> +
> +#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024)>>  PAGE_SHIFT)
> +
> +static void __init zone_sizes_init(unsigned long min, unsigned long max)
> +{
> +	unsigned long zone_size[MAX_NR_ZONES];
> +	unsigned long max_dma32 = min;
> +
> +	memset(zone_size, 0, sizeof(zone_size));
> +
> +	zone_size[0] = max - min;
> +#ifdef CONFIG_ZONE_DMA32
> +	/* 4GB maximum for 32-bit only capable devices */
> +	max_dma32 = min(max, MAX_DMA32_PFN);
> +	zone_size[ZONE_DMA32] = max_dma32 - min;
> +#endif
Do you see need of supporting DMA32 on arm64 SOCs ?

[..]

> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> new file mode 100644
> index 0000000..d2dd438
> --- /dev/null
> +++ b/arch/arm64/mm/mmu.c
> @@ -0,0 +1,395 @@
> +/*
> + * Based on arch/arm/mm/mmu.c
> + *
> + * Copyright (C) 1995-2005 Russell King
> + * Copyright (C) 2012 ARM Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see<http://www.gnu.org/licenses/>.
> + */
> +
> +#include<linux/export.h>
> +#include<linux/kernel.h>
> +#include<linux/errno.h>
> +#include<linux/init.h>
> +#include<linux/mman.h>
> +#include<linux/nodemask.h>
> +#include<linux/memblock.h>
> +#include<linux/fs.h>
> +
> +#include<asm/cputype.h>
> +#include<asm/sections.h>
> +#include<asm/setup.h>
> +#include<asm/sizes.h>
> +#include<asm/tlb.h>
> +#include<asm/mmu_context.h>
> +
> +#include "mm.h"
> +
> +/*
> + * Empty_zero_page is a special page that is used for zero-initialized data
> + * and COW.
> + */
> +struct page *empty_zero_page;
> +EXPORT_SYMBOL(empty_zero_page);
> +
> +pgprot_t pgprot_default;
> +EXPORT_SYMBOL(pgprot_default);
> +
> +static pmdval_t prot_sect_kernel;
> +
> +struct cachepolicy {
> +	const char	policy[16];
> +	u64		mair;
> +	u64		tcr;
> +};
> +
> +static struct cachepolicy cache_policies[] __initdata = {
> +	{
> +		.policy		= "uncached",
> +		.mair		= 0x44,			/* inner, outer non-cacheable */
> +		.tcr		= TCR_IRGN_NC | TCR_ORGN_NC,
> +	}, {
> +		.policy		= "writethrough",
> +		.mair		= 0xaa,			/* inner, outer write-through, read-allocate */
> +		.tcr		= TCR_IRGN_WT | TCR_ORGN_WT,
Is WT supported on arm64?
On the recent ARMv7 processors, I think WT wasn't supported.

Regards
Santosh


From catalin.marinas at arm.com  Fri Aug 17 06:07:29 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 11:07:29 +0100
Subject: [PATCH v2 09/31] arm64: Cache maintenance routines
In-Reply-To: <502E1580.70702@ti.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-10-git-send-email-catalin.marinas@arm.com>
 <502E1580.70702@ti.com>
Message-ID: <20120817100729.GF24389@arm.com>

On Fri, Aug 17, 2012 at 10:57:20AM +0100, Santosh Shilimkar wrote:
> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> > +ENTRY(__cpuc_flush_dcache_all)
>
> We have discussed the need of cache maintenance by
> level kind of API for ARMv7 (A15).
> 
> Shouldn't we add such API for arm64 as well ?

Yes, at some point we'll probably add but we'll discuss it again when
actually needed. I wouldn't define new API now that's not used by any
AArch64 code.

-- 
Catalin


From hvaibhav at ti.com  Fri Aug 17 06:09:05 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 17 Aug 2012 10:09:05 +0000
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <20120817095851.GX11011@atomide.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
 <20120817084047.GN11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
 <20120817095851.GX11011@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA922AA@DBDE01.ent.ti.com>

On Fri, Aug 17, 2012 at 15:28:51, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 02:51]:
> > On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
> > > * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
> > > > On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
> > > > > * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
> > > > > > 
> > > > > > Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
> > > > > > core_init call, which will take DT resources and initialize accordingly.
> > > > > 
> > > > > That's for the device reset/idle? We should not do that in hwmod code
> > > > > except in late_initcall for unclaimed devices as discussed earlier. We
> > > > > discussed setting up the reset function in the device specific headers
> > > > > so both device and hwmod code can call them as needed.
> > > > 
> > > > May be I didn't understand your above statement, can you please elaborate 
> > > > more on "device specific header file"?
> > > 
> > > We should have the device drivers idle and reset the devices. But also
> > > hwmod may need to do that for the unclaimed devices for PM to work. 
> > > As the driver may not be even compiled in, the driver specific reset and
> > > idle functions should be static inline functions in the device specific
> > > header file so hwmod code can still call those.
> > >  
> > 
> > How about mapping the address of the devices?
> 
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>  

There will not be any driver probe for unclaimed devices, right? 

> > Some more thoughts on the similar line on unclaimed devices -
> > As par of late_initcall(), traverse all the DTB nodes and for each node with 
> > "state = disabled", we can do something like,
> > 
> > Late_initcall()
> > 	-> Traverse DTB nodes and check for "state = disabled"
> > 		-> Read the "ti,hwmod" entry and get offsets like, sys_config 
> > 		   and reset.
> > 		-> Map the base address
> > 		-> Enable the module/clock
> > 		-> Reset the device
> > 		-> Write to sysc register offset
> > 		-> Disable the module/clock
> > 
> > 
> > 
> > > > Just to highlight, its not only during late_initcall, the _enable and _idle 
> > > > functions are getting executed as part of every runtime_pm_get\put_sync from 
> > > > the driver.
> 
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
> 

I think you mixed two responses here, this was not part of my last response.
Just only read above code execution steps, I think they still make sense and 
we may end up doing something similar.

> > At the current stage, I really think it would be really nice and beneficial 
> > for driver developers from the community if they get Linux Boot from 
> > linux-next/master branch. I have seen lot of community folks are struggling 
> > with it and they are blocked because we do not have booting kernel on 
> > BeagleBone.
> > They always end up patching kernel with HWMOD patch and submit the driver 
> > patches. So request to consider this cleanup as sequential patch on top of 
> > original HWMOD patch?
> 
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future. 
>  

Thanks a lot Tony.
Paul, Care to add it in your next pull request.

> > > > May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
> > > > now??
> > > 
> > > Sorry I don't follow this part, care to explain a little more?
> > > 
> > 
> > As per current implementation, we are using HWMOD information to fill the 
> > platform_device->resources. Even if you pass "reg" and "interrupt" property 
> > from DT, omap_device layer overwrites it with HWMOD data information.
> > 
> > So what I am trying to propose here is, avoid this overwrite and resources 
> > (address and interrupt) should strictly gets used from DT blob. Since AM33xx 
> > and OMAP5 devices are the new devices and supports DT boot only, we can 
> > implement it easily for them.
> 
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>  

Exactly, I will submit RFC for this.

> > Only issue her is, DMA resources, I was going through some of the old email 
> > archives today, submitted by Benoit and later Jon, but I am still not sure 
> > how to pass dma_channel to driver as a resource.
> 
> Hmm I thought that got merged already? 

No, atleast didn't find in 3.6-rc1.

> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.
> 

Agreed, I am submitting patch for this as well.

Thanks,
Vaibhav


From santosh.shilimkar at ti.com  Fri Aug 17 06:10:12 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 17 Aug 2012 15:40:12 +0530
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120817100533.GE24389@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <502E11B6.4020104@ti.com> <20120817100533.GE24389@arm.com>
Message-ID: <CAMQu2gzz0j+SnxCY0u3H__H4U-Lor_xV-eyiMBSohCMngbkD2w@mail.gmail.com>

On Fri, Aug 17, 2012 at 3:35 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
>
> On Fri, Aug 17, 2012 at 10:41:10AM +0100, Santosh Shilimkar wrote:
> > On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> > > +The boot loader is expected to enter the kernel on each CPU in the
> > > +following manner:
> > > +
> > > +- The primary CPU must jump directly to the first instruction of the
> > > +  kernel image.  The device tree blob passed by this CPU must contain
> > > +  for each CPU node:
> > > +
> > > +    1. An 'enable-method' property. Currently, the only supported
> > > value
> > > +       for this field is the string "spin-table".
> > > +
> > > +    2. A 'cpu-release-addr' property identifying a 64-bit,
> > > +       zero-initialised memory location.
> > > +
> > > +  It is expected that the bootloader will generate these device tree
> > > +  properties and insert them into the blob prior to kernel entry.
> > > +
> > > +- Any secondary CPUs must spin outside of the kernel in a reserved
> > > area
> > > +  of memory (communicated to the kernel by a /memreserve/ region in
> > > the
> > > +  device tree) polling their cpu-release-addr location, which must be
> > > +  contained in the reserved region.  A wfe instruction may be
> > > inserted
> > > +  to reduce the overhead of the busy-loop and a sev will be issued by
> > > +  the primary CPU.  When a read of the location pointed to by the
> > > +  cpu-release-addr returns a non-zero value, the CPU must jump
> > > directly
> > > +  to this value.
> >
> > So you expect all the secondary CPUs to be in wakeup state and probably
> > looping in WFE for a signal from kernel to boot. There is one issue
> > with this requirement though. For large CPU system, you need to reset
> > all the CPUs and hit this waiting loop. This will lead to large inrush
> > current need at bootup which may be not be supported. To avoid this
> > issue, secondary CPUs are kept in OFF state and then they are woken
> > up from kernel one by one whenever they need to be brought into the
> > system. This requirement should be considered.
>
> I agree, this part will be extended. That's one method that we currently
> support and suitable to the model.
>
> The better method is the SMC standardisation that Charles Garcia-Tobin
> has written (to be made available soon) and was presented at the last
> Linaro Connect in HK. Given that the CPU power is usually controlled by
> the secure side, we'll ask for an SMC to be issued for waking up
> secondary CPUs, so it's up to the secure firmware to write the correct
> hardware registers.
>
Thanks for the information. SMC standardization would indeed help
to overcome some of these. Will wait for that information before
next set of questions.

> > > --- /dev/null
> > > +++ b/arch/arm64/kernel/head.S
> > [..]
> > > +   /*
> > > +    * DO NOT MODIFY. Image header expected by Linux boot-loaders.
> > > +    */
> > > +   b       stext                           // branch to kernel start,
> > > magic
> > > +   .long   0                               // reserved
> > > +   .quad   TEXT_OFFSET                     // Image load offset from
> > > start of RAM
> > > +   .quad   0                               // reserved
> > > +   .quad   0                               // reserved
> > > +
> >
> > Minor nit. Avoid C++ commenting style "//"  here and rest of the patch.
>
> That's not C++ comment style, it's the *official* assembly comment style
> for AArch64 ('@' is no longer supported).
>
Ok. Thanks for clarifying.

Regards
Santosh


From santosh.shilimkar at ti.com  Fri Aug 17 06:12:07 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 17 Aug 2012 15:42:07 +0530
Subject: [PATCH v2 09/31] arm64: Cache maintenance routines
In-Reply-To: <20120817100729.GF24389@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-10-git-send-email-catalin.marinas@arm.com>
 <502E1580.70702@ti.com> <20120817100729.GF24389@arm.com>
Message-ID: <CAMQu2gz1A5VCTFS_7vzBhnaLhbEKUOhpH-KfFbrE6YhaLDDxXA@mail.gmail.com>

On Fri, Aug 17, 2012 at 3:37 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Fri, Aug 17, 2012 at 10:57:20AM +0100, Santosh Shilimkar wrote:
>> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
>> > +ENTRY(__cpuc_flush_dcache_all)
>>
>> We have discussed the need of cache maintenance by
>> level kind of API for ARMv7 (A15).
>>
>> Shouldn't we add such API for arm64 as well ?
>
> Yes, at some point we'll probably add but we'll discuss it again when
> actually needed. I wouldn't define new API now that's not used by any
> AArch64 code.
>
The patches are already on the list for ARMv7 and just waiting to merge
two approaches.
I agree once it is getting merged for ARMv7 and ARMv8 port can be
updated.

Regards
Santosh


From catalin.marinas at arm.com  Fri Aug 17 06:15:00 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 11:15:00 +0100
Subject: [PATCH v2 05/31] arm64: MMU initialisation
In-Reply-To: <502E1793.9080605@ti.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
 <502E1793.9080605@ti.com>
Message-ID: <20120817101500.GG24389@arm.com>

On Fri, Aug 17, 2012 at 11:06:11AM +0100, Santosh Shilimkar wrote:
> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> > This patch contains the initialisation of the memory blocks, MMU
> > attributes and the memory map. Only five memory types are defined:
> > Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
> > Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
> > Cache policies are supported via the memory attributes register
> > (MAIR_EL1) and only affect the Normal Cacheable mappings.
> >
> > This patch also adds the SPARSEMEM_VMEMMAP initialisation.
> >
> > Signed-off-by: Will Deacon<will.deacon at arm.com>
> > Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
> > ---
> 
> Whats the difference between Device nGnRE and Device GRE ?
> Sorry, I haven't gone through the specs yet and hence the
> question.

G - gathering (multiple reads/writes into one)
R - reordering (reads/writes)
E - early acknowledgement (the write may have not hit the device before
    the instruction returns).

The 'n' in front just negates the meaning.

So the Device memory as we know it on ARMv7 is equivalent to nGnRE. The
Strongly Ordered is nGnRnE. GRE is pretty much like Normal Non-cacheable
memory but with Device mapping, so there are restrictions on unaligned
accesses.

> > +#ifdef CONFIG_ZONE_DMA32
> > +	/* 4GB maximum for 32-bit only capable devices */
> > +	max_dma32 = min(max, MAX_DMA32_PFN);
> > +	zone_size[ZONE_DMA32] = max_dma32 - min;
> > +#endif
> 
> Do you see need of supporting DMA32 on arm64 SOCs ?

I've got some questions from partners but those devices may just be
hidden behind an iommu. For now I left it in.

> > +static struct cachepolicy cache_policies[] __initdata = {
> > +	{
> > +		.policy		= "uncached",
> > +		.mair		= 0x44,			/* inner, outer non-cacheable */
> > +		.tcr		= TCR_IRGN_NC | TCR_ORGN_NC,
> > +	}, {
> > +		.policy		= "writethrough",
> > +		.mair		= 0xaa,			/* inner, outer write-through, read-allocate */
> > +		.tcr		= TCR_IRGN_WT | TCR_ORGN_WT,
> 
> Is WT supported on arm64?
> On the recent ARMv7 processors, I think WT wasn't supported.

All of WB, WA, WT are just architectural hints. A CPU implementation may
or may not ignore them but with Linux we try to follow the architecture
rather than specific implementations.

-- 
Catalin


From broonie at opensource.wolfsonmicro.com  Fri Aug 17 06:18:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 11:18:39 +0100
Subject: [PATCH v3 0/9] ARM/ASoC: OMAP McBSP device tree support
In-Reply-To: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817101838.GB30548@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:40:59PM +0300, Peter Ujfalusi wrote:

> in order to be able to add DT support for the McBSP driver which is used on all
> OMAP platforms (OMAP1/2/3/4/5) I needed to make some cleanups to the stack:

Tony, are you OK with these changes going via ASoC?


From santosh.shilimkar at ti.com  Fri Aug 17 06:21:17 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 17 Aug 2012 15:51:17 +0530
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
Message-ID: <502E1B1D.2030609@ti.com>

On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
> From: Marc Zyngier<marc.zyngier at arm.com>
>
> This patch adds support for the ARM generic timers with A64 instructions
> for accessing the timer registers. It uses the physical counter as the
> clock source and the virtual counter as sched_clock.
>
> The timer frequency can be specified via DT or read from the CNTFRQ_EL0
> register. The physical counter is also accessible from user space
> allowing fast gettimeofday() implementation.
>
> Signed-off-by: Marc Zyngier<marc.zyngier at arm.com>
> Signed-off-by: Will Deacon<will.deacon at arm.com>
> Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
> ---

[..]

> diff --git a/drivers/clocksource/arm_generic.c b/drivers/clocksource/arm_generic.c
> new file mode 100644
> index 0000000..05c898c
> --- /dev/null
> +++ b/drivers/clocksource/arm_generic.c

[..]

> +
> +static void __cpuinit arch_timer_setup(struct clock_event_device *clk)
> +{
> +	/* Let's make sure the timer is off before doing anything else */
> +	arch_timer_stop();
> +
> +	clk->features = CLOCK_EVT_FEAT_ONESHOT;
Are these CPU timers wakeup capable or we need the wakeup capable
broadcast timer for low power wakeups ?
In that case C3STOP would be needed here.

Regards
santosh


From richard.genoud at gmail.com  Fri Aug 17 06:23:06 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 12:23:06 +0200
Subject: [PATCH] BUG: clk_find() misses some clocks
In-Reply-To: <20120817095837.GM18957@n2100.arm.linux.org.uk>
References: <1345196843-23059-1-git-send-email-richard.genoud@gmail.com>
 <20120817095837.GM18957@n2100.arm.linux.org.uk>
Message-ID: <CACQ1gAh3YcMBXp7BFoR68+rdDM1PEe4fenNG77s=SP05RditEA@mail.gmail.com>

2012/8/17 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> Please read the comments on the function:
>
>  * Find the correct struct clk for the device and connection ID.
>  * We do slightly fuzzy matching here:
>  *  An entry with a NULL ID is assumed to be a wildcard.
>  *  If an entry has a device ID, it must match
>  *  If an entry has a connection ID, it must match
>  * Then we take the most specific entry - with the following
>  * order of precedence: dev+con > dev only > con only.
>
> On Fri, Aug 17, 2012 at 11:47:23AM +0200, Richard Genoud wrote:
>> if a clock is declared like that:
>> CLKDEV_CON_DEV_ID("pioA", "fffff400.gpio", &pioAB_clk)
>
> So you've declared it with a connection ID.  Therefore, as the comment
> above says, "it must match" what the driver is asking for.
>
> It's not a bug, this is done intentionally so that mismatches do not
> occur.
Ok, so I have to declare it like that :
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk)

Got it !
Thanks.

Richard.

-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From santosh.shilimkar at ti.com  Fri Aug 17 06:25:25 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 17 Aug 2012 15:55:25 +0530
Subject: [PATCH v2 05/31] arm64: MMU initialisation
In-Reply-To: <20120817101500.GG24389@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-6-git-send-email-catalin.marinas@arm.com>
 <502E1793.9080605@ti.com> <20120817101500.GG24389@arm.com>
Message-ID: <CAMQu2gxpmCZqAqZ1KCXoxg3vXQLqdFRv+nQ2vt0FeDzpGvNc7A@mail.gmail.com>

On Fri, Aug 17, 2012 at 3:45 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Fri, Aug 17, 2012 at 11:06:11AM +0100, Santosh Shilimkar wrote:
>> On Tuesday 14 August 2012 11:22 PM, Catalin Marinas wrote:
>> > This patch contains the initialisation of the memory blocks, MMU
>> > attributes and the memory map. Only five memory types are defined:
>> > Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
>> > Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
>> > Cache policies are supported via the memory attributes register
>> > (MAIR_EL1) and only affect the Normal Cacheable mappings.
>> >
>> > This patch also adds the SPARSEMEM_VMEMMAP initialisation.
>> >
>> > Signed-off-by: Will Deacon<will.deacon at arm.com>
>> > Signed-off-by: Catalin Marinas<catalin.marinas at arm.com>
>> > ---
>>
>> Whats the difference between Device nGnRE and Device GRE ?
>> Sorry, I haven't gone through the specs yet and hence the
>> question.
>
> G - gathering (multiple reads/writes into one)
> R - reordering (reads/writes)
> E - early acknowledgement (the write may have not hit the device before
>     the instruction returns).
>
> The 'n' in front just negates the meaning.
>
> So the Device memory as we know it on ARMv7 is equivalent to nGnRE. The
> Strongly Ordered is nGnRnE. GRE is pretty much like Normal Non-cacheable
> memory but with Device mapping, so there are restrictions on unaligned
> accesses.
>
Thanks for explaining it so clearly.

>> > +#ifdef CONFIG_ZONE_DMA32
>> > +   /* 4GB maximum for 32-bit only capable devices */
>> > +   max_dma32 = min(max, MAX_DMA32_PFN);
>> > +   zone_size[ZONE_DMA32] = max_dma32 - min;
>> > +#endif
>>
>> Do you see need of supporting DMA32 on arm64 SOCs ?
>
> I've got some questions from partners but those devices may just be
> hidden behind an iommu. For now I left it in.
>
ok.

>> > +static struct cachepolicy cache_policies[] __initdata = {
>> > +   {
>> > +           .policy         = "uncached",
>> > +           .mair           = 0x44,                 /* inner, outer non-cacheable */
>> > +           .tcr            = TCR_IRGN_NC | TCR_ORGN_NC,
>> > +   }, {
>> > +           .policy         = "writethrough",
>> > +           .mair           = 0xaa,                 /* inner, outer write-through, read-allocate */
>> > +           .tcr            = TCR_IRGN_WT | TCR_ORGN_WT,
>>
>> Is WT supported on arm64?
>> On the recent ARMv7 processors, I think WT wasn't supported.
>
> All of WB, WA, WT are just architectural hints. A CPU implementation may
> or may not ignore them but with Linux we try to follow the architecture
> rather than specific implementations.
>
Agree.

Regards
Santosh


From stigge at antcom.de  Fri Aug 17 06:52:41 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 17 Aug 2012 12:52:41 +0200
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <1345198171.27859.39.camel@sauron.fi.intel.com>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
 <1345198171.27859.39.camel@sauron.fi.intel.com>
Message-ID: <502E2279.1030604@antcom.de>

On 08/17/2012 12:09 PM, Artem Bityutskiy wrote:
> On Thu, 2012-08-16 at 15:15 +0200, Roland Stigge wrote:
>> The SLC and MLC NAND drivers now need their dma_filter callbacks
>> via platform data to make them independent of single DMA engine
>> drivers.
>> 
>> (This also helps fixing build errors of the SLC and MLC drivers
>> when building as modules because direct access to AMBA dma filter
>> functions isn't available via export.)
>> 
>> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> Pushed the 3 patches to l2-mtd.git, thanks!

To later avoid collisions on subsystem merge, can you please leave the
patch with arch/arm/mach-lpc32xx/phy3250.c for arm-soc.git? (I will
provide a pull request for Arnd and Olof, as usual.)

Thanks,

Roland


From artem.bityutskiy at linux.intel.com  Fri Aug 17 07:01:51 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Fri, 17 Aug 2012 14:01:51 +0300
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <502E2279.1030604@antcom.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
 <1345198171.27859.39.camel@sauron.fi.intel.com>
 <502E2279.1030604@antcom.de>
Message-ID: <1345201311.27859.51.camel@sauron.fi.intel.com>

On Fri, 2012-08-17 at 12:52 +0200, Roland Stigge wrote:
> On 08/17/2012 12:09 PM, Artem Bityutskiy wrote:
> > On Thu, 2012-08-16 at 15:15 +0200, Roland Stigge wrote:
> >> The SLC and MLC NAND drivers now need their dma_filter callbacks
> >> via platform data to make them independent of single DMA engine
> >> drivers.
> >> 
> >> (This also helps fixing build errors of the SLC and MLC drivers
> >> when building as modules because direct access to AMBA dma filter
> >> functions isn't available via export.)
> >> 
> >> Signed-off-by: Roland Stigge <stigge at antcom.de>
> > 
> > Pushed the 3 patches to l2-mtd.git, thanks!
> 
> To later avoid collisions on subsystem merge, can you please leave the
> patch with arch/arm/mach-lpc32xx/phy3250.c for arm-soc.git? (I will
> provide a pull request for Arnd and Olof, as usual.)

Only if Arnd insists. Otherwise I'd prefer to resolve collisions (they
cannot be hard with this patch) than pulling the soc tree to the mtd
tree.

-- 
Best Regards,
Artem Bityutskiy
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From r.sricharan at ti.com  Fri Aug 17 07:02:22 2012
From: r.sricharan at ti.com (R, Sricharan)
Date: Fri, 17 Aug 2012 16:32:22 +0530
Subject: [PATCH v2 1/1] ARM: LPAE: Fix mapping in alloc_init_pte for
 unaligned addresses.
In-Reply-To: <1344238885-13683-1-git-send-email-r.sricharan@ti.com>
References: <1344238885-13683-1-git-send-email-r.sricharan@ti.com>
Message-ID: <CAJ7qFSeoyVGie__3mJ8=edeEf7Jh7TQY8vcWgGdOtWVXa8TU0Q@mail.gmail.com>

Hi,

> With LPAE, When either the start address or end address
> or physical address to be mapped is unaligned,
> alloc_init_section creates page granularity mappings.
> alloc_init_section calls alloc_init_pte which populates
> one pmd entry and sets up the ptes. But if the size is
> greater than what can be mapped by one pmd entry,
> then the rest remains unmapped.
>
> The issue becomes visible when LPAE is enabled, where we have
> the 3 levels with seperate pgd and pmd's.
> When a static mapping for 3MB is requested, only 2MB is mapped
> and the remaining 1MB is unmapped. Fixing this here, by looping
> in to map the entire unaligned address range.
>
> Boot tested on OMAP5 evm with both LPAE enabled/disabled
> and verified that static mappings with unaligned addresses
> are properly mapped.
>
> Signed-off-by: R Sricharan <r.sricharan at ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> ---
> [V2] Moved the loop to alloc_init_pte as per Russell's
>      feedback and changed the subject accordingly.
>      Using PMD_XXX instead of SECTION_XXX to avoid
>      different loop increments with/without LPAE.
>
>  arch/arm/mm/mmu.c |   22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index cf4528d..0ed8808 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -585,11 +585,25 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
>                                   unsigned long end, unsigned long pfn,
>                                   const struct mem_type *type)
>  {
> -       pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
> +       unsigned long next;
> +       pte_t *pte;
> +       phys_addr_t phys;
> +
>         do {
> -               set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
> -               pfn++;
> -       } while (pte++, addr += PAGE_SIZE, addr != end);
> +               if ((end-addr) & PMD_MASK)
> +                       next = (addr + PMD_SIZE) & PMD_MASK;
> +               else
> +                       next = end;
> +
> +               pte = early_pte_alloc(pmd, addr, type->prot_l1);
> +               do {
> +                       set_pte_ext(pte, pfn_pte(pfn,
> +                                       __pgprot(type->prot_pte)), 0);
> +                       pfn++;
> +               } while (pte++, addr += PAGE_SIZE, addr != next);
> +
> +               phys += next - addr;
> +       } while (pmd++, addr = next, addr != end);
>  }
>
  ping..

Thanks,
 Sricharan


From r.sricharan at ti.com  Fri Aug 17 07:03:07 2012
From: r.sricharan at ti.com (R, Sricharan)
Date: Fri, 17 Aug 2012 16:33:07 +0530
Subject: [RFC PATCH] ARM: LPAE: Fix alloc_init_section to flush all the
 pmd entries.
In-Reply-To: <1344249230-29835-1-git-send-email-r.sricharan@ti.com>
References: <1344249230-29835-1-git-send-email-r.sricharan@ti.com>
Message-ID: <CAJ7qFSfdZmzH=u9DV4MYeFyee5ntB2gOC1GOSDqNzMBYh0puoA@mail.gmail.com>

Hi,
On Mon, Aug 6, 2012 at 4:03 PM, R Sricharan <r.sricharan at ti.com> wrote:
> flush_pmd_entry flushes one cache line by MVA. This is
> called by alloc_init_section to flush the mapped pmd
> entries. But this is called outside the loop and when
> LPAE is enabled the number of pmd entries to be
> flushed can be across multiple cache lines. So call
> this inside the loop so that all the mapped entries are
> flushed.
>
> This is going to result in additional cache line
> flushes. There might be other better way to handle
> this.
>
> Signed-off-by: R Sricharan <r.sricharan at ti.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
>  arch/arm/mm/mmu.c |    4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 0ed8808..02af3fe 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -619,7 +619,6 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
>          * up one logical pointer to an L2 table.
>          */
>         if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
> -               pmd_t *p = pmd;
>
>  #ifndef CONFIG_ARM_LPAE
>                 if (addr & SECTION_SIZE)
> @@ -629,9 +628,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
>                 do {
>                         *pmd = __pmd(phys | type->prot_sect);
>                         phys += SECTION_SIZE;
> +                       flush_pmd_entry(pmd);
>                 } while (pmd++, addr += SECTION_SIZE, addr != end);
> -
> -               flush_pmd_entry(p);
>         } else {
>                 /*
>                  * No need to loop; pte's aren't interested in the
  Ping...

Thanks,
 Sricharan


From dedekind1 at gmail.com  Fri Aug 17 07:10:35 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 17 Aug 2012 14:10:35 +0300
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <1345201311.27859.51.camel@sauron.fi.intel.com>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
 <1345198171.27859.39.camel@sauron.fi.intel.com>
 <502E2279.1030604@antcom.de>
 <1345201311.27859.51.camel@sauron.fi.intel.com>
Message-ID: <1345201835.27859.52.camel@sauron.fi.intel.com>

On Fri, 2012-08-17 at 14:01 +0300, Artem Bityutskiy wrote:
> > To later avoid collisions on subsystem merge, can you please leave the
> > patch with arch/arm/mach-lpc32xx/phy3250.c for arm-soc.git? (I will
> > provide a pull request for Arnd and Olof, as usual.)
> 
> Only if Arnd insists. Otherwise I'd prefer to resolve collisions (they
> cannot be hard with this patch) than pulling the soc tree to the mtd
> tree.

Actually the mtd patches do not compile-depend on it, sorry, I am
dropping it from the MTD tree. Thanks!

-- 
Best Regards,
Artem Bityutskiy
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From arnd at arndb.de  Fri Aug 17 07:20:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 11:20:40 +0000
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <alpine.LFD.2.02.1208161438110.1541@xanadu.home>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <alpine.LFD.2.02.1208161438110.1541@xanadu.home>
Message-ID: <201208171120.40740.arnd@arndb.de>

On Thursday 16 August 2012, Nicolas Pitre wrote:
> > +3. Decompress the kernel image
> > +------------------------------
> > +
> > +Requirement: OPTIONAL
> > +
> > +The AArch64 kernel does not provide a decompressor and therefore
> > +requires gzip decompression to be performed by the boot loader if the
> > +default Image.gz target is used.  For bootloaders that do not implement
> > +this requirement, the larger Image target is available instead.
> 
> Some people will want to use bzip2 or whatever other decompressor du 
> jour.  Maybe this shouldn't be gzip specific, or just presented as a 
> possible option?

Good point. Whether this should be part of this document depends on
what assumptions we make about the boot loader getting the image
in the first place.

In the strict sense, we are documenting the interface between the boot
loader and the kernel here, which already specifies that  the kernel
must be uncompressed by the time we enter it. If the boot loader wants
to add its own encryption or compression methods, or its own headers
in front of the binary, the boot protocol isn't really impacted.

That said, I think it's a good idea to also specify what kind of
format we want to be used, e.g. a stripped ELF Image compressed
with one of gzip/bzip2/lzo/xz and with no other headers added,
on a vfat/ext4/btrfs formatted file system. There are probably a
lot of other things one might want to specify if we go down this
route. Or we could refer to the UEFI spec and mandate that the
same format that UEFI uses should be used here independent of
what boot loader is used. I think we can still allow other ways to
get to the image for deeply embedded systems, e.g. linking the
kernel into the boot loader as a blob on tightly constrained
systems. For that case, we'd only specify the interface between
boot loader and kernel as described above.

	Arnd


From arnd at arndb.de  Fri Aug 17 07:24:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 11:24:39 +0000
Subject: [PATCH V4 1/5] clk: mmp: add mmp specific clocks
In-Reply-To: <1345183330-20244-2-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
 <1345183330-20244-2-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208171124.39201.arnd@arndb.de>

On Friday 17 August 2012, Chao Xie wrote:
> 
> From: Chao Xie <chao.xie at marvell.com>
> 
> add mmp specific clocks including apbc cloks, apmu clocks,
> and pll2, fraction clocks
> 
> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From dedekind1 at gmail.com  Fri Aug 17 07:29:44 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 17 Aug 2012 14:29:44 +0300
Subject: [PATCH 1/1 v2] MTD: atmel nand: fix gpio missing request
In-Reply-To: <1342081868-5995-1-git-send-email-plagnioj@jcrosoft.com>
References: <1342071036-15905-1-git-send-email-plagnioj@jcrosoft.com>
 <1342081868-5995-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1345202984.27859.54.camel@sauron.fi.intel.com>

On Thu, 2012-07-12 at 10:31 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> without this the gpio will not be muxed as a gpio by the current custom pinmux
> or later by the pinctrl
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From arnd at arndb.de  Fri Aug 17 07:25:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 11:25:36 +0000
Subject: [PATCH V4 5/5] arm: mmp: make all SOCs use common clock by default
In-Reply-To: <1345183330-20244-6-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
 <1345183330-20244-6-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208171125.36990.arnd@arndb.de>

On Friday 17 August 2012, Chao Xie wrote:
> From: Chao Xie <chao.xie at marvell.com>
> 
> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
> ---
>  arch/arm/mach-mmp/Kconfig |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 

Acked-by: Arnd Bergmann <arnd at arndb.de>


From b-cousson at ti.com  Fri Aug 17 07:33:01 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 17 Aug 2012 13:33:01 +0200
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <20120817095851.GX11011@atomide.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
 <20120817084047.GN11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
 <20120817095851.GX11011@atomide.com>
Message-ID: <502E2BED.3030705@ti.com>

Hi Guys,

On 08/17/2012 11:58 AM, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 02:51]:
>> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>>> * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
>>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>>> * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
>>>>>>
>>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
>>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>>
>>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>>> discussed setting up the reset function in the device specific headers
>>>>> so both device and hwmod code can call them as needed.
>>>>
>>>> May be I didn't understand your above statement, can you please elaborate 
>>>> more on "device specific header file"?
>>>
>>> We should have the device drivers idle and reset the devices. But also
>>> hwmod may need to do that for the unclaimed devices for PM to work. 
>>> As the driver may not be even compiled in, the driver specific reset and
>>> idle functions should be static inline functions in the device specific
>>> header file so hwmod code can still call those.
>>>  
>>
>> How about mapping the address of the devices?
> 
> That should be done based on the iorange coming from DT during the driver
> probe. The range in hwmod can be populated at that point too if needed.
>  
>> Some more thoughts on the similar line on unclaimed devices -
>> As par of late_initcall(), traverse all the DTB nodes and for each node with 
>> "state = disabled", we can do something like,
>>
>> Late_initcall()
>> 	-> Traverse DTB nodes and check for "state = disabled"
>> 		-> Read the "ti,hwmod" entry and get offsets like, sys_config 
>> 		   and reset.
>> 		-> Map the base address
>> 		-> Enable the module/clock
>> 		-> Reset the device
>> 		-> Write to sysc register offset
>> 		-> Disable the module/clock
>>
>>
>>
>>>> Just to highlight, its not only during late_initcall, the _enable and _idle 
>>>> functions are getting executed as part of every runtime_pm_get\put_sync from 
>>>> the driver.
> 
> Heh, but the unclaimed devices do not have a driver :) So there's no runtime_pm
> calls for the unclaimed devicdes.
> 
>> At the current stage, I really think it would be really nice and beneficial 
>> for driver developers from the community if they get Linux Boot from 
>> linux-next/master branch. I have seen lot of community folks are struggling 
>> with it and they are blocked because we do not have booting kernel on 
>> BeagleBone.
>> They always end up patching kernel with HWMOD patch and submit the driver 
>> patches. So request to consider this cleanup as sequential patch on top of 
>> original HWMOD patch?
> 
> Yes I'm fine merging the data as is, just trying to figure out how to sort
> out the issues for future. 
>  
>>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
>>>> now??
>>>
>>> Sorry I don't follow this part, care to explain a little more?
>>>
>>
>> As per current implementation, we are using HWMOD information to fill the 
>> platform_device->resources. Even if you pass "reg" and "interrupt" property 
>> from DT, omap_device layer overwrites it with HWMOD data information.
>>
>> So what I am trying to propose here is, avoid this overwrite and resources 
>> (address and interrupt) should strictly gets used from DT blob. Since AM33xx 
>> and OMAP5 devices are the new devices and supports DT boot only, we can 
>> implement it easily for them.
> 
> Yes I agree. And then we should also drop the data from hwmod when it's no
> longer needed.
>  
>> Only issue her is, DMA resources, I was going through some of the old email 
>> archives today, submitted by Benoit and later Jon, but I am still not sure 
>> how to pass dma_channel to driver as a resource.
> 
> Hmm I thought that got merged already?

No, it is still under discussion. I don't even know why they are still
arguing, but there are still a lot of discussion on that thread.

> Anyways, the iorange and interrupts
> are standard resources that should exist in every device entry in .dts files.

Yeah, I wanted to avoid that to make things simpler. As soon as we have
the DMA we can switch easily to DT resource.

My other concern is that so far we still have to duplicate the io space
address with the way the hwmod is initializing the syscofig today.

So it will require some change in that part to make an effective use of
DT. So point is that if we start using that mechanism for DT boot, we
will still have to keep the legacy one for non DT boot.
Nothing is impossible, but that's still a lot of work before having
something useful.

The idea was to stop iterating the hwmods early and init the hwmod only
during device probe or late_initcall for the one that will not probe.

Again, easy with DT, less straighforward for non-DT boot.

Regards,
Benoit




From arnd at arndb.de  Fri Aug 17 07:34:31 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 11:34:31 +0000
Subject: [PATCH V4 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <1345183330-20244-3-git-send-email-xiechao.mail@gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
 <1345183330-20244-3-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208171134.32195.arnd@arndb.de>

On Friday 17 August 2012, Chao Xie wrote:
> +void __init pxa168_clk_init(void)
> +{
> +       struct clk *clk;
> +       struct clk *uart_pll;
> +       void __iomem *mpmu_base;
> +       void __iomem *apmu_base;
> +       void __iomem *apbc_base;
> +
> +       mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
> +       if (mpmu_base == NULL) {
> +               pr_err("error to ioremap MPMU base\n");
> +               return;
> +       }
> +
> +       apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
> +       if (apmu_base == NULL) {
> +               pr_err("error to ioremap APMU base\n");
> +               return;
> +       }
> +
> +       apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
> +       if (apbc_base == NULL) {
> +               pr_err("error to ioremap APBC base\n");
> +               return;
> +       }

I hadn't noticed this before, but you are hardcoded physical address locations
in the driver, which is not so good since we're trying to move all those
locations to device tree. Maybe someone else has an idea to do this better.

> +       clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
> +       clk_register_clkdev(clk, "clk32", NULL);
> +
> +       clk =
> +           clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
> +                                   26000000);
> +       clk_register_clkdev(clk, "vctcxo", NULL);
> +
> +       clk =
> +           clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
> +       clk_register_clkdev(clk, "pll1", NULL);

Ok, so you've managed to remove the array, good!

I'm still not overly happy with the style of newline after "=", that is
very unusual, and only saves you two characters per line. I'd say just move
them each into one line as you did in the first one here. It's less important
to align the arguments to the opening braces if you are trying to stay in the
80 character limit. Another option would be to rename the variable to just
'c' instead of 'clk' ;-)

	Arnd


	Arnd


From linux at arm.linux.org.uk  Fri Aug 17 07:34:42 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 Aug 2012 12:34:42 +0100
Subject: [PATCH] BUG: clk_find() misses some clocks
In-Reply-To: <CACQ1gAh3YcMBXp7BFoR68+rdDM1PEe4fenNG77s=SP05RditEA@mail.gmail.com>
References: <1345196843-23059-1-git-send-email-richard.genoud@gmail.com>
 <20120817095837.GM18957@n2100.arm.linux.org.uk>
 <CACQ1gAh3YcMBXp7BFoR68+rdDM1PEe4fenNG77s=SP05RditEA@mail.gmail.com>
Message-ID: <20120817113442.GN18957@n2100.arm.linux.org.uk>

On Fri, Aug 17, 2012 at 12:23:06PM +0200, Richard Genoud wrote:
> Ok, so I have to declare it like that :
> CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk)

Yes, because the wildcarding is in the clkdev tables, not in the driver.
If you think about what's going on, that's the way it has to be.  Remember
that it's the _device_ that defines what the connection name is (there's
the hint: it's the connection name on the device itself) and it isn't a
global clock name.

So, for example, if set of devices used in multiple different SoCs have a
clock input called "apbclk" and on some SoCs this clock is uncontrollable,
but on others it can be individually controlled, we can cater for this:

- the SoC where this clock is uncontrollable can create a dummy clock with
  a connection ID of "apbclk" and a NULL device name, which will match
  against any device asking for an "apbclk".
- the SoC where the clock is individually controllable would list the
  individual "apbclk" entries in the clkdev table, and clkdev will return
  the appropriate one.

In mixed environments, this also works, because we return the "best match"
from clkdev.

Same goes for devices where they have an "iclk" and an "fclk" (iow, two
clocks) - the connection ID can be wildcarded in the clkdev tables so that
the same clock can be returned for the same device where the driver asks
for the clocks individually - if that's what the SoC support desires.

It makes no sense for a driver to ask for "any clock on this device"
because drivers always want the clock for a particular purpose.  Hence
why NULL arguments to clk_get() don't act as wildcards.


From arnd at arndb.de  Fri Aug 17 07:40:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 11:40:50 +0000
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <1345201835.27859.52.camel@sauron.fi.intel.com>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
 <1345201311.27859.51.camel@sauron.fi.intel.com>
 <1345201835.27859.52.camel@sauron.fi.intel.com>
Message-ID: <201208171140.50388.arnd@arndb.de>

On Friday 17 August 2012, Artem Bityutskiy wrote:
>   Show Details
>   On Fri, 2012-08-17 at 14:01 +0300, Artem Bityutskiy wrote:
> > > To later avoid collisions on subsystem merge, can you please leave the
> > > patch with arch/arm/mach-lpc32xx/phy3250.c for arm-soc.git? (I will
> > > provide a pull request for Arnd and Olof, as usual.)
> > 
> > Only if Arnd insists. Otherwise I'd prefer to resolve collisions (they
> > cannot be hard with this patch) than pulling the soc tree to the mtd
> > tree.
> 
> Actually the mtd patches do not compile-depend on it, sorry, I am
> dropping it from the MTD tree. Thanks!

For reference, I'm fine with either outcome, I don't mind seeing an
occasional collision with subsystem trees, as they tend to be trivial
to resolve.

If you split a series to go through multiple git trees, you have to
ensure that both halves are actually regression free by themselves,
which typically ends up being much harder than fixing a small merge
conflict.

	Arnd


From b-cousson at ti.com  Fri Aug 17 07:43:11 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 17 Aug 2012 13:43:11 +0200
Subject: [PATCH-V3] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
References: <1343214422-28718-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207251438210.23542@utopia.booyaka.com>
 <alpine.DEB.2.00.1207261359500.14468@utopia.booyaka.com>
 <20120814082911.GG11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA8F4CD@DBDE01.ent.ti.com>
 <20120817074934.GL11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA92062@DBDE01.ent.ti.com>
 <20120817084047.GN11011@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9220D@DBDE01.ent.ti.com>
Message-ID: <502E2E4F.9040301@ti.com>

Hi Vaibhav,

On 08/17/2012 11:51 AM, Hiremath, Vaibhav wrote:
> On Fri, Aug 17, 2012 at 14:10:47, Tony Lindgren wrote:
>> * Hiremath, Vaibhav <hvaibhav at ti.com> [120817 01:22]:
>>> On Fri, Aug 17, 2012 at 13:19:34, Tony Lindgren wrote:
>>>> * Hiremath, Vaibhav <hvaibhav at ti.com> [120815 02:11]:
>>>>>
>>>>> Somehow we have to have some mechanism to initialize " _mpu_rt_va" before 
>>>>> core_init call, which will take DT resources and initialize accordingly.
>>>>
>>>> That's for the device reset/idle? We should not do that in hwmod code
>>>> except in late_initcall for unclaimed devices as discussed earlier. We
>>>> discussed setting up the reset function in the device specific headers
>>>> so both device and hwmod code can call them as needed.
>>>
>>> May be I didn't understand your above statement, can you please elaborate 
>>> more on "device specific header file"?
>>
>> We should have the device drivers idle and reset the devices. But also
>> hwmod may need to do that for the unclaimed devices for PM to work. 
>> As the driver may not be even compiled in, the driver specific reset and
>> idle functions should be static inline functions in the device specific
>> header file so hwmod code can still call those.
>>  
> 
> How about mapping the address of the devices?
> 
> Some more thoughts on the similar line on unclaimed devices -
> As par of late_initcall(), traverse all the DTB nodes and for each node with 
> "state = disabled", we can do something like,

Yes, in fact we should duplicate the same mechanism that will be used to
init a regular device during probe.

> Late_initcall()
> 	-> Traverse DTB nodes and check for "state = disabled"
> 		-> Read the "ti,hwmod" entry and get offsets like, sys_config 
> 		   and reset.
> 		-> Map the base address
> 		-> Enable the module/clock
> 		-> Reset the device
> 		-> Write to sysc register offset
> 		-> Disable the module/clock
> 
> 
> 
>>> Just to highlight, its not only during late_initcall, the _enable and _idle 
>>> functions are getting executed as part of every runtime_pm_get\put_sync from 
>>> the driver.
>>
>> Right, so no need to initialize those until at driver probe time.
>>  
> 
> Agreed.
> 
>>> Are you saying as part of late_initcall, we should initialize " _mpu_rt_va" 
>>> of "struct omap_hwmod"???
>>
>> I guess either at driver probe for the claimed devices, or at late_initcall
>> for the unclaimeded devices.
>>
>>> Also, as far unclaimed resources is concerned, somewhere you should have 
>>> base addr of the device maintained, right? Currently, hwmod is maintaining 
>>> this data and the execution goes something like,
>>>
>>> Core_initcall()
>>> 	-> _setup()
>>> 		-> _setup_reset()
>>> 		-> _idle()
>>
>> For the DT only case also the unclaimed devices can from DT with
>> status = "disabled". 
>>  
>>> Another biggest worry is, if I play here, it may break existing omap3/4 
>>> Functionality, especially may impact from PM perspective. So I believe, we 
>>> need to have something which adds/cleans-up things in stages.
>>
>> It seems that we need three stages: Something early for the timers only,
>> initialize most things during driver probe, then late_initcall for the
>> unclaimed devices.
>>
> 
> Most likely yes, or it may even get into more stages.
> 
> At the current stage, I really think it would be really nice and beneficial 
> for driver developers from the community if they get Linux Boot from 
> linux-next/master branch. I have seen lot of community folks are struggling 
> with it and they are blocked because we do not have booting kernel on 
> BeagleBone.
> They always end up patching kernel with HWMOD patch and submit the driver 
> patches. So request to consider this cleanup as sequential patch on top of 
> original HWMOD patch?
> 
> 
>>> May be get rid of resource overwriting for AM33xx and OMAP5 alone as of 
>>> now??
>>
>> Sorry I don't follow this part, care to explain a little more?
>>
> 
> As per current implementation, we are using HWMOD information to fill the 
> platform_device->resources. Even if you pass "reg" and "interrupt" property 
> from DT, omap_device layer overwrites it with HWMOD data information.
> 
> So what I am trying to propose here is, avoid this overwrite and resources 
> (address and interrupt) should strictly gets used from DT blob. Since AM33xx 
> and OMAP5 devices are the new devices and supports DT boot only, we can 
> implement it easily for them.

Well, the point is that that mechanism is still common to OMAP2+
devices, so the tricky part is that a legacy mode will still be needed.

> Only issue her is, DMA resources, I was going through some of the old email 
> archives today, submitted by Benoit and later Jon, but I am still not sure 
> how to pass dma_channel to driver as a resource.

There is no way currently :-(.

> Below logic works for me, I have tested it on both BeagleBone and AM37xEVM -
> 
> omap_device_alloc ()
> {
> 	...
> 
> 	res_count = omap_device_count_resources(od);
> 	if (res_count > pdev->num_resources) {
> 		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
> 	      if (!res)
>       		goto oda_exit3;
> 
> 		if (pdev->num_resources && pdev->resource) {
> 			omap_device_fill_dma_resources(od, res);
> 			memcpy(&res[pdev->num_resources], pdev->resource,
> 				sizeof(struct resource) * pdev->num_resources);
> 			} else {
> 				omap_device_fill_resources(od, res);
> 			}
> 	
> 		ret = platform_device_add_resources(pdev, res, res_count);
> 		kfree(res);
> 	}
> 
> 	...
> }

Yeah, or we can potentially define a custom ti DMA binding for the time
being. In fact Tegra and Exynios are currently using some custom DMA
binding. I wanted to avoid that with a generic binding RFC, but as
already said, that series is not progressing really fast whereas our
need for SDMA/EDMA is pretty simple. Well at least for SDMA.

Anyway, your approach is the proper one to me and something we've been
discussing for a while with Tony. I've just never had the time to
progress on that. I'll be more than happy to support you on OMAP4+
devices to validate that code if you can work on it.

Thanks,
Benoit



From stigge at antcom.de  Fri Aug 17 07:45:31 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 17 Aug 2012 13:45:31 +0200
Subject: [PATCH] ARM: LPC32xx: Provide DMA filter callbacks via platform
 data
In-Reply-To: <201208171140.50388.arnd@arndb.de>
References: <1345122935-22115-1-git-send-email-stigge@antcom.de>
 <1345201311.27859.51.camel@sauron.fi.intel.com>
 <1345201835.27859.52.camel@sauron.fi.intel.com>
 <201208171140.50388.arnd@arndb.de>
Message-ID: <502E2EDB.2050200@antcom.de>

On 08/17/2012 01:40 PM, Arnd Bergmann wrote:
>> Actually the mtd patches do not compile-depend on it, sorry, I am
>> dropping it from the MTD tree. Thanks!
> 
> For reference, I'm fine with either outcome, I don't mind seeing an
> occasional collision with subsystem trees, as they tend to be trivial
> to resolve.
> 
> If you split a series to go through multiple git trees, you have to
> ensure that both halves are actually regression free by themselves,

Of course. But in this very case, they are. So I'd prefer pushing them
via different trees because I have other patches for mach-lpc32xx in the
queue and would like to minimize work for you. :-)

Roland


From xiechao.mail at gmail.com  Fri Aug 17 08:03:26 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 17 Aug 2012 20:03:26 +0800
Subject: [PATCH V4 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <201208171134.32195.arnd@arndb.de>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
 <1345183330-20244-3-git-send-email-xiechao.mail@gmail.com>
 <201208171134.32195.arnd@arndb.de>
Message-ID: <CADApbejwG5F5pEicWSAb0308npupfHkE0fqTweec9ve2ZzkREw@mail.gmail.com>

On Fri, Aug 17, 2012 at 7:34 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 17 August 2012, Chao Xie wrote:
>> +void __init pxa168_clk_init(void)
>> +{
>> +       struct clk *clk;
>> +       struct clk *uart_pll;
>> +       void __iomem *mpmu_base;
>> +       void __iomem *apmu_base;
>> +       void __iomem *apbc_base;
>> +
>> +       mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
>> +       if (mpmu_base == NULL) {
>> +               pr_err("error to ioremap MPMU base\n");
>> +               return;
>> +       }
>> +
>> +       apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
>> +       if (apmu_base == NULL) {
>> +               pr_err("error to ioremap APMU base\n");
>> +               return;
>> +       }
>> +
>> +       apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
>> +       if (apbc_base == NULL) {
>> +               pr_err("error to ioremap APBC base\n");
>> +               return;
>> +       }
>
> I hadn't noticed this before, but you are hardcoded physical address locations
> in the driver, which is not so good since we're trying to move all those
> locations to device tree. Maybe someone else has an idea to do this better.
>
>> +       clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
>> +       clk_register_clkdev(clk, "clk32", NULL);
>> +
>> +       clk =
>> +           clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
>> +                                   26000000);
>> +       clk_register_clkdev(clk, "vctcxo", NULL);
>> +
>> +       clk =
>> +           clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, 624000000);
>> +       clk_register_clkdev(clk, "pll1", NULL);
>
> Ok, so you've managed to remove the array, good!
>
> I'm still not overly happy with the style of newline after "=", that is
> very unusual, and only saves you two characters per line. I'd say just move
> them each into one line as you did in the first one here. It's less important
> to align the arguments to the opening braces if you are trying to stay in the
> 80 character limit. Another option would be to rename the variable to just
> 'c' instead of 'clk' ;-)
>
>         Arnd
>
>
>         Arnd
hi
The clock tree is formatted into a table, and i used perl to generate
the code based on the table. In order to make the indent clearly, i
used the scripts/Lindent to automatically format the .c file.
I have tried to searched the parameter for indent, but i do not find
that anything can remove the the style of newline after "=", so in
order to not format the file line by line, i just accept the results
of indent.
Do you have any idea about it?


From arnd at arndb.de  Fri Aug 17 08:13:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 12:13:08 +0000
Subject: [PATCH v3 0/7] mv643xx.c: Add basic device tree support.
In-Reply-To: <5028D040.60604@codethink.co.uk>
References: <1344350092-24050-1-git-send-email-ian.molton@codethink.co.uk>
 <201208101049.57586.arnd@arndb.de> <5028D040.60604@codethink.co.uk>
Message-ID: <201208171213.09160.arnd@arndb.de>

On Monday 13 August 2012, Ian Molton wrote:
> On 10/08/12 11:49, Arnd Bergmann wrote:
> > On Thursday 09 August 2012, Ian Molton wrote:
> >>>  The driver
> >>> already knows all those offsets and they are always the same
> >>> for all variants of mv643xx, right?
> >> Yes, but its not clean. And no amount of refactoring is
> >> really going to make a nice driver that also fits the ancient
> >> (and badly thought out) OF bindings.
> > In what way is it badly though out, or not clean? The use of
> > underscores in the properties, and the way that the sram
> > is configured is problematic, I agree. But The way that
> > the three ports are addressed and how the PHY is found
> > seems quite clever.
> 
> It forces one to load the MDIO driver first, because it maps ALL the
> registers for both itself and all the ports, and the MDIO driver has no
> way of knowing how many ethernet blocks are present (I have a device
> here with two, and another with four). Thats anywhere from 1 to 12
> ports, split across 1 to 4 address ranges, and theres a big gap in the
> address range between controllers 0,1 and 2,3. *ALL* the devices on the
> board are sharing ethernet block 0's MDIO bus. By pure luck it happens
> to work, because the blocks 2,3 have an alias of the MDIO registers from
> blocks 0,1.
> 
> Having the MDIO driver map the ethernet drivers memory is a terrible
> solution, IMO. Ethernet drivers should map their own memory, and that
> introduces the n-ports-per-block problem, because their address ranges
> overlap.
> 
> I think the best solution is to make each ethernet block register 3 ports.
> 
> the PPC code can simply generate different fixups so that instead of
> creating 3 devices, it creates one, with three ports.

Ok.

> Can we get some consensus on the right approach here? I'm loathe to code
> this if its going to be rejected.
> 
> I'd prefer the driver to be properly split so we dont have the MDIO
> driver mapping the ethernet drivers address spaces, but if thats not
> going to be merged, I'm not feeling like doing the work for nothing.
> 
> If the driver is to use the overlapping-address mapped-by-the-mdio
> scheme, then so be it, but I could do with knowing.
> 
> Another point against the latter scheme is that the MDIO driver could
> sensibly be used (the block is identical) on the ArmadaXP, which has 4
> ethernet blocks rather than two, yet grouped in two pairs with a
> discontiguous address range.
> 
> I'd like to get this moved along as soon as possible though.

I don't object to any device driver changes, but I do want to make
sure that the bindings are sensible and can coexist with the
ones that have been used for the past 5 years.

Maybe you can move the binding for the ethernet parts out of the
marvell.txt file into the place you want to use for the new
bindings and then extend it to cover both the old and the new style.

	Arnd


From jon-hunter at ti.com  Fri Aug 17 08:24:09 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Fri, 17 Aug 2012 07:24:09 -0500
Subject: [RFC RESEND 2/4] ARM: OMAP3: Dynamically disable secure timer
 nodes for secure devices
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA91D63@DBDE01.ent.ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
 <502B6838.9080907@ti.com> <502D2686.4090107@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA91D63@DBDE01.ent.ti.com>
Message-ID: <502E37E9.3060201@ti.com>


On 08/17/2012 12:32 AM, Hiremath, Vaibhav wrote:
> On Thu, Aug 16, 2012 at 22:27:42, Hunter, Jon wrote:
>>
>> On 08/15/2012 04:13 AM, Vaibhav Hiremath wrote:
>>>
>>>
>>> On 7/14/2012 3:56 AM, Jon Hunter wrote:
>>>> OMAP3 devices may or may not have security features enabled. Security enabled
>>>> devices are known as high-secure (HS) and devices without security are known as
>>>> general purpose (GP).
>>>>
>>>> For OMAP3 devices there are 12 general purpose timers available. On secure
>>>> devices the 12th timer is reserved for secure usage and so cannot be used by
>>>> the kernel, where as for a GP device it is available. We can detect the OMAP
>>>> device type, secure or GP, at runtime via an on-chip register. Today, when not
>>>> using DT, we do not register the 12th timer as a linux device if the device is
>>>> secure.
>>>>
>>>> When using device tree, device tree is going to register all the timer devices
>>>> it finds in the device tree blob. To prevent device tree from registering 12th
>>>> timer on a secure OMAP3 device we can add a status property to the timer
>>>> binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
>>>> device has a property "ti,timer-secure" to indicate that it will not be
>>>> available on a secure device and so for secure OMAP3 devices, we search for
>>>> timers with this property and then disable them. Using the prom_add_property()
>>>> function to dynamically add a property was a recommended approach suggested by
>>>> Rob Herring [1].
>>>>
>>>> I have tested this on an OMAP3 GP device and faking it to pretend to be a
>>>> secure device to ensure that any timers marked with "ti,timer-secure" are not
>>>> registered on boot. I have also made sure that all timers are registered as
>>>> expected on a GP device by default.
>>>>
>>>> [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
>>>>
>>>> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
>>>> ---
>>>>  arch/arm/mach-omap2/board-generic.c |    1 +
>>>>  arch/arm/mach-omap2/common.h        |    1 +
>>>>  arch/arm/mach-omap2/timer.c         |   36 +++++++++++++++++++++++++++++++++++
>>>>  3 files changed, 38 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
>>>> index 6f93a20..20124d7 100644
>>>> --- a/arch/arm/mach-omap2/board-generic.c
>>>> +++ b/arch/arm/mach-omap2/board-generic.c
>>>> @@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
>>>>  static void __init omap_generic_init(void)
>>>>  {
>>>>  	omap_sdrc_init(NULL, NULL);
>>>> +	omap_dmtimer_init();
>>>>  
>>>>  	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
>>>>  }
>>>> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
>>>> index 1f65b18..d6a4875 100644
>>>> --- a/arch/arm/mach-omap2/common.h
>>>> +++ b/arch/arm/mach-omap2/common.h
>>>> @@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
>>>>  				      struct omap_sdrc_params *sdrc_cs1);
>>>>  struct omap2_hsmmc_info;
>>>>  extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
>>>> +extern void omap_dmtimer_init(void);
>>>>  
>>>>  #endif /* __ASSEMBLER__ */
>>>>  #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
>>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>>>> index 13d20c8..e3b9931 100644
>>>> --- a/arch/arm/mach-omap2/timer.c
>>>> +++ b/arch/arm/mach-omap2/timer.c
>>>> @@ -36,6 +36,7 @@
>>>>  #include <linux/clocksource.h>
>>>>  #include <linux/clockchips.h>
>>>>  #include <linux/slab.h>
>>>> +#include <linux/of.h>
>>>>  
>>>>  #include <asm/mach/time.h>
>>>>  #include <plat/dmtimer.h>
>>>> @@ -482,6 +483,41 @@ static int __init omap2_dm_timer_init(void)
>>>>  }
>>>>  arch_initcall(omap2_dm_timer_init);
>>>>  
>>>> +static struct property timer_disabled = {
>>>> +	.name = "status",
>>>> +	.length = sizeof("disabled"),
>>>> +	.value = "disabled",
>>>> +};
>>>> +
>>>> +static struct of_device_id omap3_timer_match[] __initdata = {
>>>> +	{ .compatible = "ti,omap3-timer", },
>>>> +	{ }
>>>> +};
>>>> +
>>>> +/**
>>>> + * omap_dmtimer_init - initialisation function when device tree is used
>>>> + *
>>>> + * For secure OMAP3 devices, timers with device type "timer-secure" cannot
>>>> + * be used by the kernel as they are reserved. Therefore, to prevent the
>>>> + * kernel registering these devices remove them dynamically from the device
>>>> + * tree on boot.
>>>> + */
>>>> +void __init omap_dmtimer_init(void)
>>>> +{
>>>> +	struct device_node *np;
>>>> +
>>>> +	if (!cpu_is_omap34xx())
>>>> +		return;
>>>> +
>>>
>>> Sorry for responding so late, but why only omap34xx check here?
>>> Isn't this applicable to all omap & non-omap devices?
>>
>> It is only applicable to omap3 devices as far as omap is concerned.
>>
>> By non-omap, you are referring to the AMxxx stuff?
>>
>> Do AMxxx devices even support security (ie. secure boot and have secure
>> peripherals)? If not then this will work for AMxxx devices too.
>>
> 
> Yes it does. 
> 
> AM33xx has 8 timers and Timer-0 is a secure timer. As in case of OMAP3, we 
> do not even register timer-0 to kernel.

Ok, however, please note that the omap3 timer 12 is a special case,
because on a non-secure device it is available for general purpose use
and only reserved for secure use on a secure device.

For omap4/5 timer 12 is always a secure timer and so we never register
it for any device (secure or non-secure) by using the "ti,timer-secure"
property in DT.

So, for AM33xx, is timer0 always reserved for secure used on non-secure
and secure devices? If so, then timer0 just needs to add the
"ti,timer-secure" property in device-tree file and it will not be
registered and no change is needed in the above code.

>> Let me know if the changelog is not clear why this is needed for an
>> omap3 device.
>>
> 
> The changelog description is clear, but it is not only restricted to OMAP3.

Not exactly, per the above it depends on whether the timer is always
secure for all device types or not.

Cheers
Jon


From m.szyprowski at samsung.com  Fri Aug 17 08:46:50 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 17 Aug 2012 14:46:50 +0200
Subject: Potential Regression in 3.6-rc1 - Kirkwood SATA
In-Reply-To: <20120815002536.GC747@harshnoise.musicnaut.iki.fi>
References: <CAMW5UfZ_kVz_b4_98zPdY2RFjTMN9H2OzjYcRQrCTgA1xqdmPw@mail.gmail.com>
 <20120815002536.GC747@harshnoise.musicnaut.iki.fi>
Message-ID: <023801cd7c76$617b0610$24711230$%szyprowski@samsung.com>

Hi Aaro,

On Wednesday, August 15, 2012 2:26 AM Aaro Koskinen wrote:

> On Tue, Aug 14, 2012 at 07:59:00PM -0400, Josh Coombs wrote:
> > I finally got a chance to test 3.6-rc1 after having my GoFlex Net
> > support patch accepted for the 3.6 release train.  Included in 3.6-rc1
> > was an update for Kirkwoods switching SATA to DT which was not part of
> > my original testing.  It seems something with this change has
> > partially broken the GoFlex and a couple other Kirkwood based devices.
> >
> > The key factor is the number of SATA ports defined in the dts:
> >
> > 		sata at 80000 {
> > 			status = "okay";
> > 			nr-ports = <2>;
> > 		};
> >
> > If set at the correct number for my device, 2, my GFN does not
> > complete kernel init, hanging here:
> >
> > <SNIP>
> > [   15.287832] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
> > [   15.296545] jffs2: version 2.2. (NAND) ?C 2001-2006 Red Hat, Inc.
> > [   15.303202] msgmni has been set to 240
> > [   15.308503] Block layer SCSI generic (bsg) driver version 0.4 loaded (major )
> > [   15.316021] io scheduler noop registered
> > [   15.320149] io scheduler deadline registered
> > [   15.324558] io scheduler cfq registered (default)
> > [   15.329462] mv_xor_shared mv_xor_shared.0: Marvell shared XOR driver
> > [   15.335962] mv_xor_shared mv_xor_shared.1: Marvell shared XOR driver
> > [   15.376751] mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
> > [   15.416736] mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )
> > [   15.456735] mv_xor mv_xor.2: Marvell XOR: ( xor cpy )
> > [   15.496734] mv_xor mv_xor.3: Marvell XOR: ( xor fill cpy )
> > [   15.506309] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> > [   15.509111] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
> > [   15.509141] console [ttyS0] enabled, bootconsole disabled
> > [   15.518967] brd: module loaded
> > [   15.524991] loop: module loaded
> > [   15.528584] sata_mv sata_mv.0: cannot get optional clkdev
> > [   15.534180] sata_mv sata_mv.0: slots 32 ports 2
> >
> > If you set nr-ports to 1 the unit boots cleanly, save for only
> > detecting one functional SATA port.  Another user has confirmed this
> > behavior on an Iomega IX2-200.
> 
> Try booting with "coherent_pool=1M" (or bigger) kernel parameter. I think
> with the recent DMA mapping changes, the default 256 KB coherent pool may
> be too small, mv_xor and sata_mv together needs more. (I'm not sure how
> it actually worked before commit e9da6e9905e639b0f842a244bc770b48ad0523e9,
> but it seems this is the cuase).
> 
> It should be noted that dma_pool_alloc() uses GFP_ATOMIC always, and if
> drivers exhaust the coherent pool already during the boot that function
> just keeps looping forever. Users only see boot hanging with no clue
> what to do. I would say it's quite a poor error handling...

Thanks for the report, I will improve error handling and add a possibility for
setting the default pool size by platform/board setup code. I'm sorry for a late
response.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From alanbutty12 at gmail.com  Fri Aug 17 08:47:06 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Fri, 17 Aug 2012 13:47:06 +0100
Subject: Issues with all kernels after 3.3.7
Message-ID: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>

I have been trying all kernels after 3.3.7 (except for the 3.5 series)
on my ix2-200
and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
and now even on 3.6 rc1
and the next dated today 17 august that when i use git for example:

git clone git://git.videolan.org/x264

my system just crash's / hangs and even through the serial port i get
no response.
This also happens when i try to access a web interface for example the
serviio java webui.

The second issue i have noticed is that my raid 0 array hangs / pauses
when being mounted
at system startup. (for approximatly 30 seconds maybe more maybe less
im not certain).
But again on the 3.3.7 kernel there was no issue and no hang.

If i return to 3.3.7 everything works fine with no other modifications
to the os or kernels.
I am using debian wheezy at the moment but also tried debian squeeze
so it does not
seem to be related to the specific linux version just the kernel.


From tony at atomide.com  Fri Aug 17 09:06:20 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:06:20 -0700
Subject: [PATCH v3 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock
 parenting code to ASoC driver
In-Reply-To: <1345124468-8876-2-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-2-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130619.GY11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> Move the McBSP CLKS re-parenting code to ASoC driver from
> arch/arm/mach-omap2.
> The call fort the re-parenting has been already limited to OMAP2+ SoC in
> the ASoC driver. There is no longer need to have callback function for it.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 09:07:24 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:07:24 -0700
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130723.GZ11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
> the FIFO for the audio stack.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
> ---
>  arch/arm/mach-omap2/mcbsp.c |    5 ++++-
>  1 files changed, 4 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
> index ebc801e..6e046e1 100644
> --- a/arch/arm/mach-omap2/mcbsp.c
> +++ b/arch/arm/mach-omap2/mcbsp.c
> @@ -151,7 +151,10 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
>  	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
>  		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
>  
> -	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
> +	if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
> +		/* The FIFO has 128 locations */
> +		pdata->buffer_size = 0x80;
> +	} else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
>  		if (id == 2)
>  			/* The FIFO has 1024 + 256 locations */
>  			pdata->buffer_size = 0x500;

Is this the case also for 2420? I thought some only had a FIFO at
one port?

Tony


From tony at atomide.com  Fri Aug 17 09:07:45 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:07:45 -0700
Subject: [PATCH v3 3/9] ARM: OMAP: board-am3517evm: Configure McBSP1
 CLKR/FSR signal source
In-Reply-To: <1345124468-8876-4-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130744.GA11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> am3517evm board uses McBSP1 for audio with 4pin configuration.
> The CLKR/FSR signals need to be connected to CLKX/FSX pin of the SoC in
> this case.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 09:08:02 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:08:02 -0700
Subject: [PATCH v3 4/9] ASoC: am3517evm: Do not configure McBSP1
 CLKR/FSR signal muxing
In-Reply-To: <1345124468-8876-5-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-5-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130802.GB11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> The muxing is done at board level, no need to do it in the ASoC machine
> driver.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 09:08:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:08:33 -0700
Subject: [PATCH v3 5/9] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux
 configuration code
In-Reply-To: <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130833.GC11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> Remove the feature to configure the CLKR/FSR mux on McBSP port with 6pin
> configuration.
> When moving to devicetree these callback can no longer be used in a clean
> way anymore.
> If a board require to change the 6pin port to work in 4pin setup it needs
> to set up the mux in the board file.
> For OMAP2/3:
> u32 devconf0;
> 
> /* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
> devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
> devconf0 |=  OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
> omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
> 
> For OMAP4:
> u32 mcbsp_pad;
> 
> /* McBSP4 CLKR/FSR signal to be connected to CLKX/FSX pin */
> mcbsp_pad = omap4_ctrl_pad_readl(OMAP2_CONTROL_DEVCONF0);
> mcbsp_pad |=  ((1 << 31) | (1 << 30));
> omap4_ctrl_pad_writel(mcbsp_pad, OMAP2_CONTROL_DEVCONF0);
> 
> In case when the kernel is booted with DT blob the pinctrl-single will be
> provided as soon as it is enabled on the platform.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 09:09:04 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:09:04 -0700
Subject: [PATCH v3 8/9] ARM: OMAP2+: McBSP: Do not create legacy
 devices when booting with DT data
In-Reply-To: <1345124468-8876-9-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-9-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120817130904.GD11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> Only create the devices in a legacy way if we do not have the DT data.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 17 09:10:24 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:10:24 -0700
Subject: [PATCH v3 0/9] ARM/ASoC: OMAP McBSP device tree support
In-Reply-To: <20120817101838.GB30548@opensource.wolfsonmicro.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <20120817101838.GB30548@opensource.wolfsonmicro.com>
Message-ID: <20120817131023.GE11011@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120817 03:18]:
> On Thu, Aug 16, 2012 at 04:40:59PM +0300, Peter Ujfalusi wrote:
> 
> > in order to be able to add DT support for the McBSP driver which is used on all
> > OMAP platforms (OMAP1/2/3/4/5) I needed to make some cleanups to the stack:
> 
> Tony, are you OK with these changes going via ASoC?

Yes, had one 2420 related question about the FIFO, other than that
I've acked the omap related patches.

Tony


From tony at atomide.com  Fri Aug 17 09:13:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 06:13:59 -0700
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <CAMQu2gzz0j+SnxCY0u3H__H4U-Lor_xV-eyiMBSohCMngbkD2w@mail.gmail.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <502E11B6.4020104@ti.com> <20120817100533.GE24389@arm.com>
 <CAMQu2gzz0j+SnxCY0u3H__H4U-Lor_xV-eyiMBSohCMngbkD2w@mail.gmail.com>
Message-ID: <20120817131358.GF11011@atomide.com>

* Shilimkar, Santosh <santosh.shilimkar at ti.com> [120817 03:11]:
> On Fri, Aug 17, 2012 at 3:35 PM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> >
> > On Fri, Aug 17, 2012 at 10:41:10AM +0100, Santosh Shilimkar wrote:
> > >
> > > So you expect all the secondary CPUs to be in wakeup state and probably
> > > looping in WFE for a signal from kernel to boot. There is one issue
> > > with this requirement though. For large CPU system, you need to reset
> > > all the CPUs and hit this waiting loop. This will lead to large inrush
> > > current need at bootup which may be not be supported. To avoid this
> > > issue, secondary CPUs are kept in OFF state and then they are woken
> > > up from kernel one by one whenever they need to be brought into the
> > > system. This requirement should be considered.
> >
> > I agree, this part will be extended. That's one method that we currently
> > support and suitable to the model.
> >
> > The better method is the SMC standardisation that Charles Garcia-Tobin
> > has written (to be made available soon) and was presented at the last
> > Linaro Connect in HK. Given that the CPU power is usually controlled by
> > the secure side, we'll ask for an SMC to be issued for waking up
> > secondary CPUs, so it's up to the secure firmware to write the correct
> > hardware registers.
> >
> Thanks for the information. SMC standardization would indeed help
> to overcome some of these. Will wait for that information before
> next set of questions.

Yes please. If the SMC is not standardized for most calls at least,
we'll end up with a horrible mess of SoC specific calls like we
currently have. Related to that, the virtualization calls should be
also standardized so we don't end up with multiple different hypervisors
with different calls.

Regards,

Tony


From jarkko.nikula at bitmer.com  Fri Aug 17 09:14:36 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Fri, 17 Aug 2012 16:14:36 +0300
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <20120817130723.GZ11011@atomide.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120817130723.GZ11011@atomide.com>
Message-ID: <502E43BC.30708@bitmer.com>

On 08/17/2012 04:07 PM, Tony Lindgren wrote:
> * Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
>> On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
>> the FIFO for the audio stack.
> Is this the case also for 2420? I thought some only had a FIFO at
> one port?
> 
IRCC (I don't have specs), nope. Only 2430 (as noted by Peter) and
onwards have FIFO.

But that's true that FIFO sizes differ between the ports. E.g. only
ports 2 and 3 have 1024+128 deep FIFOs in OMAP3.

-- 
Jarkko


From thomas.petazzoni at free-electrons.com  Fri Aug 17 09:21:56 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 17 Aug 2012 15:21:56 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120816183708.GT22226@titan.lakedaemon.net>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
Message-ID: <20120817152156.4d91ba16@skate>

Hello,

Le Thu, 16 Aug 2012 14:37:08 -0400,
Jason Cooper <jason at lakedaemon.net> a ?crit :

> > Whole series applied to:
> > 
> > git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
> 
> I'm getting the following build error with orion_nand enabled:
> 
>   CC      drivers/mtd/nand/orion_nand.o
> drivers/mtd/nand/orion_nand.c:24:27: fatal error: mach/hardware.h: No
> such file or directory
> compilation terminated.
> 
> I don't have time to look at it right now, hopefully I can look at it
> tomorrow or this weekend.

I have just built your boards-for-v3.7 for Kirkwood (which includes the
orion_nand driver) and it builds just fine.

Are you perhaps trying to enable the orion_nand driver for a mach-mvebu
platform (Armada 370 or XP)? If it's the case, then yes, this build
breakage is expected: we haven't enabled any of the I/O for now, so we
don't have hardware.h yet. This is not something that is broken due to
the address decoding changes.

If however my guess was wrong, could you send me the failing .config so
that I can reproduce and investigate?

Thanks!

Thomas Petazzoni
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From sr at denx.de  Fri Aug 17 09:22:32 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 17 Aug 2012 15:22:32 +0200
Subject: [PATCH v2] mtd: physmap_of: Add "no-unaligned-direct-access" DT
 property
Message-ID: <1345209752-22938-1-git-send-email-sr@denx.de>

On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
problems with JFFS2 usage, as the local bus (LPB) doesn't support
unaligned accesses as implemented in the JFFS2 code via memcpy().
By defining "no-unaligned-direct-access", the flash will not be
exposed directly to the MTD users (e.g. JFFS2) any more.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Stephan Gatzka <Stephan.Gatzka at hbm.com>
Cc: Anatolij Gustschin <agust at denx.de>
Cc: Albrecht Dress <albrecht.dress at arcor.de>
Cc: Artem Bityutskiy <dedekind1 at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
---
v2:
- Changed "map-indirect" to "no-unaligned-direct-access" because of
  David's comments.

 Documentation/devicetree/bindings/mtd/mtd-physmap.txt |  7 +++++++
 drivers/mtd/maps/physmap_of.c                         | 14 ++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index a63c2bd7..94de19b 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -16,6 +16,13 @@ file systems on embedded devices.
  - #address-cells, #size-cells : Must be present if the device has
    sub-nodes representing partitions (see below).  In this case
    both #address-cells and #size-cells must be equal to 1.
+ - no-unaligned-direct-access: boolean to disable the default direct
+   mapping of the flash.
+   On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
+   problems with JFFS2 usage, as the local bus (LPB) doesn't support
+   unaligned accesses as implemented in the JFFS2 code via memcpy().
+   By defining "no-unaligned-direct-access", the flash will not be
+   exposed directly to the MTD users (e.g. JFFS2) any more.
 
 For JEDEC compatible devices, the following additional properties
 are defined:
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
index 2e6fb68..6f19aca 100644
--- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -169,6 +169,7 @@ static int __devinit of_flash_probe(struct platform_device *dev)
 	struct mtd_info **mtd_list = NULL;
 	resource_size_t res_size;
 	struct mtd_part_parser_data ppdata;
+	bool map_indirect;
 
 	match = of_match_device(of_flash_match, &dev->dev);
 	if (!match)
@@ -192,6 +193,8 @@ static int __devinit of_flash_probe(struct platform_device *dev)
 	}
 	count /= reg_tuple_size;
 
+	map_indirect = of_property_read_bool(dp, "no-unaligned-direct-access");
+
 	err = -ENOMEM;
 	info = kzalloc(sizeof(struct of_flash) +
 		       sizeof(struct of_flash_list) * count, GFP_KERNEL);
@@ -247,6 +250,17 @@ static int __devinit of_flash_probe(struct platform_device *dev)
 
 		simple_map_init(&info->list[i].map);
 
+		/*
+		 * On some platforms (e.g. MPC5200) a direct 1:1 mapping
+		 * may cause problems with JFFS2 usage, as the local bus (LPB)
+		 * doesn't support unaligned accesses as implemented in the
+		 * JFFS2 code via memcpy(). By setting NO_XIP, the
+		 * flash will not be exposed directly to the MTD users
+		 * (e.g. JFFS2) any more.
+		 */
+		if (map_indirect)
+			info->list[i].map.phys = NO_XIP;
+
 		if (probe_type) {
 			info->list[i].mtd = do_map_probe(probe_type,
 							 &info->list[i].map);
-- 
1.7.11.2



From u.kleine-koenig at pengutronix.de  Fri Aug 17 09:26:29 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 17 Aug 2012 15:26:29 +0200
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
Message-ID: <20120817132629.GA2232@pengutronix.de>

On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
> on my ix2-200
> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
> and now even on 3.6 rc1
> and the next dated today 17 august that when i use git for example:
> 
> git clone git://git.videolan.org/x264
> 
> my system just crash's / hangs and even through the serial port i get
> no response.
> This also happens when i try to access a web interface for example the
> serviio java webui.
> 
> The second issue i have noticed is that my raid 0 array hangs / pauses
> when being mounted
> at system startup. (for approximatly 30 seconds maybe more maybe less
> im not certain).
> But again on the 3.3.7 kernel there was no issue and no hang.
> 
> If i return to 3.3.7 everything works fine with no other modifications
> to the os or kernels.
> I am using debian wheezy at the moment but also tried debian squeeze
> so it does not
> seem to be related to the specific linux version just the kernel.
Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
be the obvious range to test.

You can also try to enable the various debugging options like

	CONFIG_DETECT_HUNG_TASK
	CONFIG_PROVE_LOCKING
	CONFIG_DEBUG_ATOMIC_SLEEP
	CONFIG_MAGIC_SYSRQ

or try https://lkml.org/lkml/2012/5/26/83.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From catalin.marinas at arm.com  Fri Aug 17 09:45:15 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 14:45:15 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <201208171120.40740.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <alpine.LFD.2.02.1208161438110.1541@xanadu.home>
 <201208171120.40740.arnd@arndb.de>
Message-ID: <20120817134515.GH24389@arm.com>

On Fri, Aug 17, 2012 at 12:20:40PM +0100, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Nicolas Pitre wrote:
> > > +3. Decompress the kernel image
> > > +------------------------------
> > > +
> > > +Requirement: OPTIONAL
> > > +
> > > +The AArch64 kernel does not provide a decompressor and therefore
> > > +requires gzip decompression to be performed by the boot loader if the
> > > +default Image.gz target is used.  For bootloaders that do not implement
> > > +this requirement, the larger Image target is available instead.
> > 
> > Some people will want to use bzip2 or whatever other decompressor du 
> > jour.  Maybe this shouldn't be gzip specific, or just presented as a 
> > possible option?
> 
> Good point. Whether this should be part of this document depends on
> what assumptions we make about the boot loader getting the image
> in the first place.

It ended up here because there is a Makefile target, Image.gz, though I
haven't used it at all. I'll expand the text so that it is not
restricted to gzip.

> In the strict sense, we are documenting the interface between the boot
> loader and the kernel here, which already specifies that  the kernel
> must be uncompressed by the time we enter it. If the boot loader wants
> to add its own encryption or compression methods, or its own headers
> in front of the binary, the boot protocol isn't really impacted.

Yes.

> That said, I think it's a good idea to also specify what kind of
> format we want to be used, e.g. a stripped ELF Image compressed
> with one of gzip/bzip2/lzo/xz and with no other headers added,
> on a vfat/ext4/btrfs formatted file system. There are probably a
> lot of other things one might want to specify if we go down this
> route. Or we could refer to the UEFI spec and mandate that the
> same format that UEFI uses should be used here independent of
> what boot loader is used. I think we can still allow other ways to
> get to the image for deeply embedded systems, e.g. linking the
> kernel into the boot loader as a blob on tightly constrained
> systems. For that case, we'd only specify the interface between
> boot loader and kernel as described above.

At least the latter case is used on the model. For the other cases, it's
quite early to clearly specify what is needed as we don't currently have
a boot-loader other than UEFI. We may expect GRUB as well.

-- 
Catalin


From catalin.marinas at arm.com  Fri Aug 17 09:48:57 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 14:48:57 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120817131358.GF11011@atomide.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <502E11B6.4020104@ti.com> <20120817100533.GE24389@arm.com>
 <CAMQu2gzz0j+SnxCY0u3H__H4U-Lor_xV-eyiMBSohCMngbkD2w@mail.gmail.com>
 <20120817131358.GF11011@atomide.com>
Message-ID: <20120817134857.GI24389@arm.com>

On Fri, Aug 17, 2012 at 02:13:59PM +0100, Tony Lindgren wrote:
> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120817 03:11]:
> > On Fri, Aug 17, 2012 at 3:35 PM, Catalin Marinas
> > <catalin.marinas at arm.com> wrote:
> > >
> > > On Fri, Aug 17, 2012 at 10:41:10AM +0100, Santosh Shilimkar wrote:
> > > >
> > > > So you expect all the secondary CPUs to be in wakeup state and probably
> > > > looping in WFE for a signal from kernel to boot. There is one issue
> > > > with this requirement though. For large CPU system, you need to reset
> > > > all the CPUs and hit this waiting loop. This will lead to large inrush
> > > > current need at bootup which may be not be supported. To avoid this
> > > > issue, secondary CPUs are kept in OFF state and then they are woken
> > > > up from kernel one by one whenever they need to be brought into the
> > > > system. This requirement should be considered.
> > >
> > > I agree, this part will be extended. That's one method that we currently
> > > support and suitable to the model.
> > >
> > > The better method is the SMC standardisation that Charles Garcia-Tobin
> > > has written (to be made available soon) and was presented at the last
> > > Linaro Connect in HK. Given that the CPU power is usually controlled by
> > > the secure side, we'll ask for an SMC to be issued for waking up
> > > secondary CPUs, so it's up to the secure firmware to write the correct
> > > hardware registers.
> > >
> > Thanks for the information. SMC standardization would indeed help
> > to overcome some of these. Will wait for that information before
> > next set of questions.
> 
> Yes please. If the SMC is not standardized for most calls at least,
> we'll end up with a horrible mess of SoC specific calls like we
> currently have. Related to that, the virtualization calls should be
> also standardized so we don't end up with multiple different hypervisors
> with different calls.

For hypervisor, there are two kinds of API - one meant for power
management that is pretty much the same as the SMC and another specific
to the hypervisor solution (KVM, Xen etc.). The latter is specific to
the host kernel that's running as we start it at EL2 but it's not
standardised. It would be good indeed and there are other advantages
like self-virtualisation but it needs the KVM and Xen guys to come to a
common definition.

-- 
Catalin


From alanbutty12 at gmail.com  Fri Aug 17 10:01:43 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 14:01:43 +0000
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <20120817132629.GA2232@pengutronix.de>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <20120817132629.GA2232@pengutronix.de>
Message-ID: <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>

On 17 August 2012 13:26, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
>> on my ix2-200
>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
>> and now even on 3.6 rc1
>> and the next dated today 17 august that when i use git for example:
>>
>> git clone git://git.videolan.org/x264
>>
>> my system just crash's / hangs and even through the serial port i get
>> no response.
>> This also happens when i try to access a web interface for example the
>> serviio java webui.
>>
>> The second issue i have noticed is that my raid 0 array hangs / pauses
>> when being mounted
>> at system startup. (for approximatly 30 seconds maybe more maybe less
>> im not certain).
>> But again on the 3.3.7 kernel there was no issue and no hang.
>>
>> If i return to 3.3.7 everything works fine with no other modifications
>> to the os or kernels.
>> I am using debian wheezy at the moment but also tried debian squeeze
>> so it does not
>> seem to be related to the specific linux version just the kernel.
> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
> be the obvious range to test.
>
> You can also try to enable the various debugging options like
>
>         CONFIG_DETECT_HUNG_TASK
>         CONFIG_PROVE_LOCKING
>         CONFIG_DEBUG_ATOMIC_SLEEP
>         CONFIG_MAGIC_SYSRQ
>
> or try https://lkml.org/lkml/2012/5/26/83.
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

i enabled the options you said there and i see alot of the following
popping up while connected through serial:

 BUG: sleeping function called from invalid context at
include/linux/freezer.h:46
[  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180, name:
console-kit-dae
[  126.904566] no locks held by console-kit-dae/2180.
[  126.909378] irq event stamp: 27643
[  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
_raw_spin_unlock_irqrestore+0x3c/0x5c
[  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
ret_fast_syscall+0xc/0x38
[  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
irq_exit+0x54/0xb8
[  126.936890] softirqs last disabled at (25558): [<c001bc20>]
irq_exit+0x54/0xb8
[  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
[<c000b414>] (do_signal+0x84/0x5c0)
[  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from [<c000be0c>]
(do_notify_resume+0x18/0x60)
[  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
[<c0009120>] (work_pending+0x24/0x28)

there seems to be alot more of them when i have serviio upnp server running.


From peter.ujfalusi at ti.com  Fri Aug 17 10:03:23 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri, 17 Aug 2012 17:03:23 +0300
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <502E43BC.30708@bitmer.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120817130723.GZ11011@atomide.com> <502E43BC.30708@bitmer.com>
Message-ID: <502E4F2B.6060403@ti.com>

On 08/17/2012 04:14 PM, Jarkko Nikula wrote:
> On 08/17/2012 04:07 PM, Tony Lindgren wrote:
>> * Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
>>> On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
>>> the FIFO for the audio stack.
>> Is this the case also for 2420? I thought some only had a FIFO at
>> one port?
>>
> IRCC (I don't have specs), nope. Only 2430 (as noted by Peter) and
> onwards have FIFO.
> 
> But that's true that FIFO sizes differ between the ports. E.g. only
> ports 2 and 3 have 1024+128 deep FIFOs in OMAP3.
> 

OMAP2420 McBSP does not have FIFO (the IP is closer to OMAP1 McBSP).
OMAP2430, OMAP4, OMAP5 has 128 word long FIFO on all McBSP ports.
On OMAP3: McBSP2 have 1024+256 (1280) word FIFO the rest of the ports have 128
long FIFO.


-- 
P?ter


From jon-hunter at ti.com  Fri Aug 17 10:08:51 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Fri, 17 Aug 2012 09:08:51 -0500
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-5-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
Message-ID: <502E5073.6000901@ti.com>

Hi Will, Tony,

On 08/10/2012 12:36 PM, Will Deacon wrote:
> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
> 
> The arm_pmu_type enumeration was initially introduced to identify
> different PMU types in the system, the usual one being that on the CPU
> (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
> the introduction of devicetree bindings for the CPU PMU, the enumeration
> is no longer required.
> 
> This patch removes the enumeration and updates the various CPU PMU
> platform devices so that they no longer pass an .id field referring
> to identify the PMU type.

[snip]

> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
> index c00c689..02b9478 100644
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -23,7 +23,6 @@
>  #include <mach/irqs.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/map.h>
> -#include <asm/pmu.h>
>  
>  #include "iomap.h"
>  #include <plat/board.h>
> @@ -448,7 +447,7 @@ static struct resource omap3_pmu_resource = {
>  
>  static struct platform_device omap_pmu_device = {
>  	.name		= "arm-pmu",
> -	.id		= ARM_PMU_DEVICE_CPU,
> +	.id		= -1,
>  	.num_resources	= 1,
>  };

I know that I have already ack-ed the change and it is fine with me,
however, I see a potential merge conflict here with my patch [1]
(assuming that these all go into v3.7) where I am moving the above
structure.

For testing I have rebased my series on top of this series and it is
working well so far on OMAP4460.

I am hoping to get the next version of my series for omap out next week.
However, before I did I wanted to ask how we should handle the above
change. Should I submit my series as rebased on top of this?

Thanks
Jon

[1]
https://github.com/jonhunter/linux/commit/6a07e3aa21f956bea7858704c224b7f50d25e1c0


From richard.genoud at gmail.com  Fri Aug 17 10:35:16 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:16 +0200
Subject: [PATCH 0/8] UBI: add max_beb_per1024 parameter / ioctl
Message-ID: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>

Artem,
This patch serie introduce, step by step the kernel module parameter
max_beb_per1024, then the ioctl and finally drop the kernel config option
CONFIG_MTD_UBI_BEB_LIMIT.

It's based on top of linux-ubi/master (and I added your patch on
sam9_l9260_defconfig).
BTW, I let the BEB value at 30 in sam9_l9260_defconfig, you can set it at 25 if
you want (as it's the value from the datasheet).

Best Regards

Richard.

Artem Bityutskiy (1):
  arm: sam9_l9260_defconfig: adjust UBI bad eraseblocks limit

Richard Genoud (7):
  UBI: separate bad_peb_limit in a function
  UBI: introduce MTD_PARAM_MAX_COUNT
  UBI: prepare for max_beb_per1024 module parameter addition
  UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
  UBI: replace MTD_UBI_BEB_LIMIT with module parameter
  UBI: add ioctl for max_beb_per1024
  UBI: drop CONFIG_MTD_UBI_BEB_LIMIT

 arch/arm/configs/sam9_l9260_defconfig |    1 -
 drivers/mtd/ubi/Kconfig               |   26 -------
 drivers/mtd/ubi/build.c               |  116 +++++++++++++++++++++-----------
 drivers/mtd/ubi/cdev.c                |    3 +-
 drivers/mtd/ubi/ubi.h                 |    6 ++-
 include/mtd/ubi-user.h                |   19 +++++-
 6 files changed, 101 insertions(+), 70 deletions(-)

-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:20 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:20 +0200
Subject: [PATCH 4/8] UBI: prepare for max_beb_per1024 module parameter addition
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-5-git-send-email-richard.genoud@gmail.com>

This patch prepare the way for the addition of max_beb_per1024 module
parameter.
There's no functional change.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/build.c |   14 ++++++++------
 drivers/mtd/ubi/cdev.c  |    3 ++-
 drivers/mtd/ubi/ubi.h   |    3 ++-
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 1f45f51..58fe53d 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -602,6 +602,7 @@ static int get_bad_peb_limit(const struct ubi_device *ubi, int max_beb_per1024)
 /**
  * io_init - initialize I/O sub-system for a given UBI device.
  * @ubi: UBI device description object
+ * @max_beb_per1024: maximum expected number of bad PEB per 1024 PEB
  *
  * If @ubi->vid_hdr_offset or @ubi->leb_start is zero, default offsets are
  * assumed:
@@ -614,10 +615,8 @@ static int get_bad_peb_limit(const struct ubi_device *ubi, int max_beb_per1024)
  * This function returns zero in case of success and a negative error code in
  * case of failure.
  */
-static int io_init(struct ubi_device *ubi)
+static int io_init(struct ubi_device *ubi, int max_beb_per1024)
 {
-	const int max_beb_per1024 = CONFIG_MTD_UBI_BEB_LIMIT;
-
 	if (ubi->mtd->numeraseregions != 0) {
 		/*
 		 * Some flashes have several erase regions. Different regions
@@ -839,6 +838,7 @@ static int autoresize(struct ubi_device *ubi, int vol_id)
  * @mtd: MTD device description object
  * @ubi_num: number to assign to the new UBI device
  * @vid_hdr_offset: VID header offset
+ * @max_beb_per1024: maximum number of expected bad blocks per 1024 eraseblocks
  *
  * This function attaches MTD device @mtd_dev to UBI and assign @ubi_num number
  * to the newly created UBI device, unless @ubi_num is %UBI_DEV_NUM_AUTO, in
@@ -849,7 +849,8 @@ static int autoresize(struct ubi_device *ubi, int vol_id)
  * Note, the invocations of this function has to be serialized by the
  * @ubi_devices_mutex.
  */
-int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset)
+int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
+		       int vid_hdr_offset, int max_beb_per1024)
 {
 	struct ubi_device *ubi;
 	int i, err, ref = 0;
@@ -922,7 +923,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset)
 	dbg_msg("sizeof(struct ubi_ainf_peb) %zu", sizeof(struct ubi_ainf_peb));
 	dbg_msg("sizeof(struct ubi_wl_entry) %zu", sizeof(struct ubi_wl_entry));
 
-	err = io_init(ubi);
+	err = io_init(ubi, max_beb_per1024);
 	if (err)
 		goto out_free;
 
@@ -1211,7 +1212,8 @@ static int __init ubi_init(void)
 
 		mutex_lock(&ubi_devices_mutex);
 		err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO,
-					 p->vid_hdr_offs);
+					 p->vid_hdr_offs,
+					 CONFIG_MTD_UBI_BEB_LIMIT);
 		mutex_unlock(&ubi_devices_mutex);
 		if (err < 0) {
 			ubi_err("cannot attach mtd%d", mtd->index);
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index fb55678..619f914 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -1010,7 +1010,8 @@ static long ctrl_cdev_ioctl(struct file *file, unsigned int cmd,
 		 * 'ubi_attach_mtd_dev()'.
 		 */
 		mutex_lock(&ubi_devices_mutex);
-		err = ubi_attach_mtd_dev(mtd, req.ubi_num, req.vid_hdr_offset);
+		err = ubi_attach_mtd_dev(mtd, req.ubi_num, req.vid_hdr_offset,
+					 CONFIG_MTD_UBI_BEB_LIMIT);
 		mutex_unlock(&ubi_devices_mutex);
 		if (err < 0)
 			put_mtd_device(mtd);
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index c94612e..2a2475b 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -693,7 +693,8 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum,
 			 struct ubi_vid_hdr *vid_hdr);
 
 /* build.c */
-int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset);
+int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
+		       int vid_hdr_offset, int max_beb_per1024);
 int ubi_detach_mtd_dev(int ubi_num, int anyway);
 struct ubi_device *ubi_get_device(int ubi_num);
 void ubi_put_device(struct ubi_device *ubi);
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:22 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:22 +0200
Subject: [PATCH 6/8] UBI: replace MTD_UBI_BEB_LIMIT with module parameter
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-7-git-send-email-richard.genoud@gmail.com>

This patch provides the possibility to adjust the "maximum expected number of
bad blocks per 1024 blocks" (max_beb_per1024) for each mtd device.

The majority of NAND devices have their max_beb_per1024 equal to 20, but
sometimes it's more.
Now, we can adjust that via a kernel parameter:
ubi.mtd=<name|num|path>[,<vid_hdr_offs>[,max_beb_per1024]]

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/Kconfig |    2 ++
 drivers/mtd/ubi/build.c |   38 ++++++++++++++++++++++++--------------
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index f326877..8b67bac 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -51,6 +51,8 @@ config MTD_UBI_BEB_LIMIT
 	  MTD partitions of the same size, UBI will reserve 40 eraseblocks when
 	  attaching a partition.
 
+	  This option can be overridden by the kernel parameter ubi.mtd.
+
 	  Leave the default value if unsure.
 
 config MTD_UBI_GLUEBI
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index ec7311f..cc05022 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -47,7 +47,7 @@
 #define MTD_PARAM_LEN_MAX 64
 
 /* Maximum number of comma-separated items in ht 'mtd=' parameter */
-#define MTD_PARAM_MAX_COUNT 2
+#define MTD_PARAM_MAX_COUNT 3
 
 #ifdef CONFIG_MTD_UBI_MODULE
 #define ubi_is_module() 1
@@ -60,10 +60,12 @@
  * @name: MTD character device node path, MTD device name, or MTD device number
  *        string
  * @vid_hdr_offs: VID header offset
+ * @max_beb_per1024: maximum expected number of bad blocks per 1024 erase blocks
  */
 struct mtd_dev_param {
 	char name[MTD_PARAM_LEN_MAX];
 	int vid_hdr_offs;
+	int max_beb_per1024;
 };
 
 /* Numbers of elements set in the @mtd_dev_param array */
@@ -1222,8 +1224,7 @@ static int __init ubi_init(void)
 
 		mutex_lock(&ubi_devices_mutex);
 		err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO,
-					 p->vid_hdr_offs,
-					 CONFIG_MTD_UBI_BEB_LIMIT);
+					 p->vid_hdr_offs, p->max_beb_per1024);
 		mutex_unlock(&ubi_devices_mutex);
 		if (err < 0) {
 			ubi_err("cannot attach mtd%d", mtd->index);
@@ -1343,6 +1344,7 @@ static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp)
 	char buf[MTD_PARAM_LEN_MAX];
 	char *pbuf = &buf[0];
 	char *tokens[MTD_PARAM_MAX_COUNT];
+	int err;
 
 	if (!val)
 		return -EINVAL;
@@ -1390,23 +1392,31 @@ static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp)
 	if (p->vid_hdr_offs < 0)
 		return p->vid_hdr_offs;
 
+	if (tokens[2]) {
+		err = kstrtoint(tokens[2], 10, &p->max_beb_per1024);
+		if (err) {
+			pr_err("UBI error: bad value for max_beb_per1024 parameter: %s",
+			       tokens[2]);
+			return -EINVAL;
+		}
+	}
+
 	mtd_devs += 1;
 	return 0;
 }
 
 module_param_call(mtd, ubi_mtd_param_parse, NULL, NULL, 000);
-MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: "
-		      "mtd=<name|num|path>[,<vid_hdr_offs>].\n"
+MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: mtd=<name|num|path>[,<vid_hdr_offs>[,max_beb_per1024]].\n"
 		      "Multiple \"mtd\" parameters may be specified.\n"
-		      "MTD devices may be specified by their number, name, or "
-		      "path to the MTD character device node.\n"
-		      "Optional \"vid_hdr_offs\" parameter specifies UBI VID "
-		      "header position to be used by UBI.\n"
-		      "Example 1: mtd=/dev/mtd0 - attach MTD device "
-		      "/dev/mtd0.\n"
-		      "Example 2: mtd=content,1984 mtd=4 - attach MTD device "
-		      "with name \"content\" using VID header offset 1984, and "
-		      "MTD device number 4 with default VID header offset.");
+		      "MTD devices may be specified by their number, name, or path to the MTD character device node.\n"
+		      "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0 or not set)\n"
+		      "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value ("
+		      __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0 or not set)\n"
+		      "\n"
+		      "Example 1: mtd=/dev/mtd0 - attach MTD device /dev/mtd0.\n"
+		      "Example 2: mtd=content,1984 mtd=4 - attach MTD device with name \"content\" using VID header offset 1984, and MTD device number 4 with default VID header offset.\n"
+		      "Example 3: mtd=/dev/mtd1,0,25 - attach MTD device /dev/mtd1 using default VID header offset and reserve 25*nand_size_in_blocks/1024 erase blocks for bad block handling.\n"
+		      "\t(e.g. if the NAND *chipset* has 4096 PEB, 100 will be reserved for this UBI device).");
 
 MODULE_VERSION(__stringify(UBI_VERSION));
 MODULE_DESCRIPTION("UBI - Unsorted Block Images");
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:18 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:18 +0200
Subject: [PATCH 2/8] UBI: separate bad_peb_limit in a function
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-3-git-send-email-richard.genoud@gmail.com>

No functional changes here, just to prepare for next patch.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/build.c |   57 ++++++++++++++++++++++++++++-------------------
 1 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 738772c..82d11e1 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -565,6 +565,37 @@ void ubi_free_internal_volumes(struct ubi_device *ubi)
 	}
 }
 
+static int get_bad_peb_limit(const struct ubi_device *ubi, int max_beb_per1024)
+{
+	int limit, device_pebs;
+	uint64_t device_size;
+
+	/*
+	 * We don't want a division by 0, and having max_beb_per1024 == 0 is ok
+	 */
+	if (!max_beb_per1024)
+		return 0;
+
+	/*
+	 * Here we are using size of the entire flash chip and
+	 * not just the MTD partition size because the maximum
+	 * number of bad eraseblocks is a percentage of the
+	 * whole device and bad eraseblocks are not fairly
+	 * distributed over the flash chip. So the worst case
+	 * is that all the bad eraseblocks of the chip are in
+	 * the MTD partition we are attaching (ubi->mtd).
+	 */
+	device_size = mtd_get_device_size(ubi->mtd);
+	device_pebs = mtd_div_by_eb(device_size, ubi->mtd);
+	limit = mult_frac(device_pebs, max_beb_per1024, 1024);
+
+	/* Round it up */
+	if (mult_frac(limit, 1024, max_beb_per1024) < device_pebs)
+		limit += 1;
+
+	return limit;
+}
+
 /**
  * io_init - initialize I/O sub-system for a given UBI device.
  * @ubi: UBI device description object
@@ -582,6 +613,8 @@ void ubi_free_internal_volumes(struct ubi_device *ubi)
  */
 static int io_init(struct ubi_device *ubi)
 {
+	const int max_beb_per1024 = CONFIG_MTD_UBI_BEB_LIMIT;
+
 	if (ubi->mtd->numeraseregions != 0) {
 		/*
 		 * Some flashes have several erase regions. Different regions
@@ -610,29 +643,7 @@ static int io_init(struct ubi_device *ubi)
 
 	if (mtd_can_have_bb(ubi->mtd)) {
 		ubi->bad_allowed = 1;
-		if (CONFIG_MTD_UBI_BEB_LIMIT > 0) {
-			int per1024 = CONFIG_MTD_UBI_BEB_LIMIT;
-			int limit, device_pebs;
-			uint64_t device_size;
-
-			/*
-			 * Here we are using size of the entire flash chip and
-			 * not just the MTD partition size because the maximum
-			 * number of bad eraseblocks is a percentage of the
-			 * whole device and bad eraseblocks are not fairly
-			 * distributed over the flash chip. So the worst case
-			 * is that all the bad eraseblocks of the chip are in
-			 * the MTD partition we are attaching (ubi->mtd).
-			 */
-			device_size = mtd_get_device_size(ubi->mtd);
-			device_pebs = mtd_div_by_eb(device_size, ubi->mtd);
-			limit = mult_frac(device_pebs, per1024, 1024);
-
-			/* Round it up */
-			if (mult_frac(limit, 1024, per1024) < device_pebs)
-				limit += 1;
-			ubi->bad_peb_limit = limit;
-		}
+		ubi->bad_peb_limit = get_bad_peb_limit(ubi, max_beb_per1024);
 	}
 
 	if (ubi->mtd->type == MTD_NORFLASH) {
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:23 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:23 +0200
Subject: [PATCH 7/8] UBI: add ioctl for max_beb_per1024
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-8-git-send-email-richard.genoud@gmail.com>

This patch provides the possibility to adjust the "maximum expected number of
bad blocks per 1024 blocks" (max_beb_per1024) for each mtd device from
UBI_IOCATT ioctl.

The majority of NAND devices have their max_beb_per1024 equal to 20, but
sometimes it's more.
We already could adjust that via a kernel parameter, now we can also use
UBI_IOCATT ioctl:
struct ubi_attach_req {
	__s32 ubi_num;
	__s32 mtd_num;
	__s32 vid_hdr_offset;
	__u8 max_beb_per1024;
	__s8 padding[11];
};

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/Kconfig |    3 ++-
 drivers/mtd/ubi/cdev.c  |    2 +-
 include/mtd/ubi-user.h  |   19 ++++++++++++++++++-
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 8b67bac..56531a7 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -51,7 +51,8 @@ config MTD_UBI_BEB_LIMIT
 	  MTD partitions of the same size, UBI will reserve 40 eraseblocks when
 	  attaching a partition.
 
-	  This option can be overridden by the kernel parameter ubi.mtd.
+	  This option can be overridden by the kernel parameter ubi.mtd and the
+	  ioctl UBI_IOCATT.
 
 	  Leave the default value if unsure.
 
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index 619f914..7885dc0 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -1011,7 +1011,7 @@ static long ctrl_cdev_ioctl(struct file *file, unsigned int cmd,
 		 */
 		mutex_lock(&ubi_devices_mutex);
 		err = ubi_attach_mtd_dev(mtd, req.ubi_num, req.vid_hdr_offset,
-					 CONFIG_MTD_UBI_BEB_LIMIT);
+					 req.max_beb_per1024);
 		mutex_unlock(&ubi_devices_mutex);
 		if (err < 0)
 			put_mtd_device(mtd);
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
index 8787349..8168d9b 100644
--- a/include/mtd/ubi-user.h
+++ b/include/mtd/ubi-user.h
@@ -222,6 +222,7 @@ enum {
  * @ubi_num: UBI device number to create
  * @mtd_num: MTD device number to attach
  * @vid_hdr_offset: VID header offset (use defaults if %0)
+ * @max_beb_per1024: Maximum expected bad eraseblocks per 1024 eraseblocks
  * @padding: reserved for future, not used, has to be zeroed
  *
  * This data structure is used to specify MTD device UBI has to attach and the
@@ -245,12 +246,28 @@ enum {
  * be 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
  * aligned, which is OK, as UBI is clever enough to realize this is 4th
  * sub-page of the first page and add needed padding.
+ *
+ * The @max_beb_per1024 is the maximum bad eraseblocks UBI expects on the ubi
+ * device per 1024 eraseblocks.
+ * This value is often given in an other form in the NAND datasheet (min NVB
+ * i.e. minimal number of valid blocks). The maximum expected bad eraseblocks
+ * per 1024 is then:
+ *   1024 * (1 - MinNVB / MaxNVB)
+ * Which gives 20 for most NAND devices.
+ * This limit is used in order to derive amount of eraseblock UBI reserves for
+ * handling new bad blocks.
+ * If the device has more bad eraseblocks than this limit, UBI does not reserve
+ * any physical eraseblocks for new bad eraseblocks, but attempts to use
+ * available eraseblocks (if any).
+ * The accepted range is 0-255. If 0 is given, the default kernel config value
+ * CONFIG_MTD_UBI_BEB_LIMIT will be used for compatibility.
  */
 struct ubi_attach_req {
 	__s32 ubi_num;
 	__s32 mtd_num;
 	__s32 vid_hdr_offset;
-	__s8 padding[12];
+	__u8 max_beb_per1024;
+	__s8 padding[11];
 };
 
 /**
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:19 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:19 +0200
Subject: [PATCH 3/8] UBI: introduce MTD_PARAM_MAX_COUNT
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-4-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/build.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 82d11e1..1f45f51 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -46,6 +46,9 @@
 /* Maximum length of the 'mtd=' parameter */
 #define MTD_PARAM_LEN_MAX 64
 
+/* Maximum number of comma-separated items in ht 'mtd=' parameter */
+#define MTD_PARAM_MAX_COUNT 2
+
 #ifdef CONFIG_MTD_UBI_MODULE
 #define ubi_is_module() 1
 #else
@@ -1327,7 +1330,7 @@ static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp)
 	struct mtd_dev_param *p;
 	char buf[MTD_PARAM_LEN_MAX];
 	char *pbuf = &buf[0];
-	char *tokens[2] = {NULL, NULL};
+	char *tokens[MTD_PARAM_MAX_COUNT];
 
 	if (!val)
 		return -EINVAL;
@@ -1357,7 +1360,7 @@ static int __init ubi_mtd_param_parse(const char *val, struct kernel_param *kp)
 	if (buf[len - 1] == '\n')
 		buf[len - 1] = '\0';
 
-	for (i = 0; i < 2; i++)
+	for (i = 0; i < MTD_PARAM_MAX_COUNT; i++)
 		tokens[i] = strsep(&pbuf, ",");
 
 	if (pbuf) {
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:17 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:17 +0200
Subject: [PATCH 1/8] arm: sam9_l9260_defconfig: adjust UBI bad eraseblocks
 limit
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

UBI has changed the MTD_UBI_BEB_LIMIT semantics. It used to be a percent of
total amount of eraseblock in the partition, and now it is the maximum
amount of bad eraseblocks on the entire devise per 1024 eraseblocks. So not
only the units changed, but also the meaning. But anyway, old 3% roughly
correspond to new 30, so change the defconfig correspondingly.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 arch/arm/configs/sam9_l9260_defconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index da276f9..d11fea5 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=3
+CONFIG_MTD_UBI_BEB_LIMIT=30
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:21 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:21 +0200
Subject: [PATCH 5/8] UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>

max_beb_per1024 shouldn't be negative, and a 0 value will be treated as
the default value.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/ubi/build.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 58fe53d..ec7311f 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -855,6 +855,16 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	struct ubi_device *ubi;
 	int i, err, ref = 0;
 
+	if (max_beb_per1024 < 0)
+		return -EINVAL;
+
+	/*
+	 * A value of 0 is forced to the default value to keep the same
+	 * behavior between ubiattach command and module parameter
+	 */
+	if (!max_beb_per1024)
+		max_beb_per1024 = CONFIG_MTD_UBI_BEB_LIMIT;
+
 	/*
 	 * Check if we already have the same MTD device attached.
 	 *
-- 
1.7.2.5



From richard.genoud at gmail.com  Fri Aug 17 10:35:24 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 16:35:24 +0200
Subject: [PATCH 8/8] UBI: drop CONFIG_MTD_UBI_BEB_LIMIT
In-Reply-To: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345214124-5478-9-git-send-email-richard.genoud@gmail.com>

This option can be set by a kernel parameter and an ioctl, so we may not
need the kernel config option any more.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/configs/sam9_l9260_defconfig |    1 -
 drivers/mtd/ubi/Kconfig               |   29 -----------------------------
 drivers/mtd/ubi/build.c               |    4 ++--
 drivers/mtd/ubi/ubi.h                 |    3 +++
 include/mtd/ubi-user.h                |    2 +-
 5 files changed, 6 insertions(+), 33 deletions(-)

diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index d11fea5..47dd71a 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -39,7 +39,6 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=30
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 56531a7..7a57cc0 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -27,35 +27,6 @@ config MTD_UBI_WL_THRESHOLD
 	  life-cycle less than 10000, the threshold should be lessened (e.g.,
 	  to 128 or 256, although it does not have to be power of 2).
 
-config MTD_UBI_BEB_LIMIT
-	int "Maximum expected bad eraseblock count per 1024 eraseblocks"
-	default 20
-	range 2 256
-	help
-	  This option specifies the maximum bad physical eraseblocks UBI
-	  expects on the MTD device (per 1024 eraseblocks). If the underlying
-	  flash does not admit of bad eraseblocks (e.g. NOR flash), this value
-	  is ignored.
-
-	  NAND datasheets often specify the minimum and maximum NVM (Number of
-	  Valid Blocks) for the flashes' endurance lifetime. The maximum
-	  expected bad eraseblocks per 1024 eraseblocks then can be calculated
-	  as "1024 * (1 - MinNVB / MaxNVB)", which gives 20 for most NANDs
-	  (MaxNVB is basically the total count of eraseblocks on the chip).
-
-	  To put it differently, if this value is 20, UBI will try to reserve
-	  about 1.9% of physical eraseblocks for bad blocks handling. And that
-	  will be 1.9% of eraseblocks on the entire NAND chip, not just the MTD
-	  partition UBI attaches. This means that if you have, say, a NAND
-	  flash chip admits maximum 40 bad eraseblocks, and it is split on two
-	  MTD partitions of the same size, UBI will reserve 40 eraseblocks when
-	  attaching a partition.
-
-	  This option can be overridden by the kernel parameter ubi.mtd and the
-	  ioctl UBI_IOCATT.
-
-	  Leave the default value if unsure.
-
 config MTD_UBI_GLUEBI
 	tristate "MTD devices emulation driver (gluebi)"
 	help
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index cc05022..d940a12 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -865,7 +865,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	 * behavior between ubiattach command and module parameter
 	 */
 	if (!max_beb_per1024)
-		max_beb_per1024 = CONFIG_MTD_UBI_BEB_LIMIT;
+		max_beb_per1024 = MTD_UBI_DEFAULT_BEB_LIMIT;
 
 	/*
 	 * Check if we already have the same MTD device attached.
@@ -1411,7 +1411,7 @@ MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: mtd=<name|num|pa
 		      "MTD devices may be specified by their number, name, or path to the MTD character device node.\n"
 		      "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0 or not set)\n"
 		      "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value ("
-		      __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0 or not set)\n"
+		      __stringify(MTD_UBI_DEFAULT_BEB_LIMIT) ") if 0 or not set)\n"
 		      "\n"
 		      "Example 1: mtd=/dev/mtd0 - attach MTD device /dev/mtd0.\n"
 		      "Example 2: mtd=content,1984 mtd=4 - attach MTD device with name \"content\" using VID header offset 1984, and MTD device number 4 with default VID header offset.\n"
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index 2a2475b..2148f35 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -50,6 +50,9 @@
 /* UBI name used for character devices, sysfs, etc */
 #define UBI_NAME_STR "ubi"
 
+/* Default number of maximum expected bad blocks per 1024 eraseblocks */
+#define MTD_UBI_DEFAULT_BEB_LIMIT 20
+
 /* Normal UBI messages */
 #define ubi_msg(fmt, ...) printk(KERN_NOTICE "UBI: " fmt "\n", ##__VA_ARGS__)
 /* UBI warning messages */
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
index 8168d9b..0b25f4c 100644
--- a/include/mtd/ubi-user.h
+++ b/include/mtd/ubi-user.h
@@ -260,7 +260,7 @@ enum {
  * any physical eraseblocks for new bad eraseblocks, but attempts to use
  * available eraseblocks (if any).
  * The accepted range is 0-255. If 0 is given, the default kernel config value
- * CONFIG_MTD_UBI_BEB_LIMIT will be used for compatibility.
+ * MTD_UBI_DEFAULT_BEB_LIMIT will be used for compatibility.
  */
 struct ubi_attach_req {
 	__s32 ubi_num;
-- 
1.7.2.5



From arnd at arndb.de  Fri Aug 17 10:46:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 17 Aug 2012 14:46:23 +0000
Subject: [PATCH V4 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <CADApbejwG5F5pEicWSAb0308npupfHkE0fqTweec9ve2ZzkREw@mail.gmail.com>
References: <1345183330-20244-1-git-send-email-xiechao.mail@gmail.com>
 <201208171134.32195.arnd@arndb.de>
 <CADApbejwG5F5pEicWSAb0308npupfHkE0fqTweec9ve2ZzkREw@mail.gmail.com>
Message-ID: <201208171446.23851.arnd@arndb.de>

On Friday 17 August 2012, Chao Xie wrote:
> The clock tree is formatted into a table, and i used perl to generate
> the code based on the table. In order to make the indent clearly, i
> used the scripts/Lindent to automatically format the .c file.
> I have tried to searched the parameter for indent, but i do not find
> that anything can remove the the style of newline after "=", so in
> order to not format the file line by line, i just accept the results
> of indent.
> Do you have any idea about it?

No easy solution. I don't normally trust lindent. Especially if you want
to bend the rules slightly, it's often better to manually edit the
output of lindent.

	Arnd


From nsekhar at ti.com  Fri Aug 17 10:59:12 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 17 Aug 2012 20:29:12 +0530
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions
 for VPIF
In-Reply-To: <502CC7CD.80906@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
 <502A4464.3020706@ti.com> <502CC7CD.80906@ti.com>
Message-ID: <502E5C40.803@ti.com>

Hi Prabhakar,

On 8/16/2012 3:43 PM, Prabhakar Lad wrote:
> On Tuesday 14 August 2012 05:58 PM, Sekhar Nori wrote:

[...]

>>> +int __init da850_register_vpif_display(struct vpif_display_config
>>> +						*display_config)
>>> +{
>>> +	struct resource da850_vpif_display_resource[] = {
>>> +		{
>>> +			.start = IRQ_DA850_VPIFINT,
>>> +			.end   = IRQ_DA850_VPIFINT,
>>> +			.flags = IORESOURCE_IRQ,
>>> +		},
>>> +		{},
>>> +	};
>>> +	unsigned long phys_end_kernel;
>>> +	int ret;
>>> +
>>> +	if (vpif_disp_cont_bufsize) {
>>> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
>>> +					(num_physpages << PAGE_SHIFT);
>>> +		phys_end_kernel += vpif_disp_cont_buf_offset;
>>> +		da850_vpif_display_resource[1].start = phys_end_kernel;
>>> +		da850_vpif_display_resource[1].end = phys_end_kernel +
>>> +						vpif_disp_cont_bufsize - 1;
>>> +		da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
>>> +
>>> +		if (!request_mem_region(da850_vpif_display_resource[1].start,
>>> +				resource_size(&da850_vpif_display_resource[1]),
>>> +				da850_vpif_display_dev.name)) {
>>> +			pr_err("region already claimed.\n");
>>> +			return -EBUSY;
>>> +		}
>>> +		ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
>>> +				phys_end_kernel, phys_end_kernel,
>>> +				vpif_disp_cont_bufsize,
>>> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
>>> +
>>> +		if (!ret)
>>> +			return -ENOMEM;
>>> +	}
>>> +	ret = platform_device_add_resources(&da850_vpif_display_dev,
>>> +				da850_vpif_display_resource,
>>> +				ARRAY_SIZE(da850_vpif_display_resource));
>>
>> You are taking memory at the end of RAM and passing it as a IO resource
>> to the driver. This is not correct. For contiguous memory needs can you
>> look at the recently merged CMA framework (include/linux/dma-contiguous.h)
>>
> Ok. But looks like CMA is enabled for CPU_V6/V6K/V7. If CMA is enabled
> for ARM926 too than we can use the global CMA itself rather then doing
> it for each device, then three will be no need to do the above and all
> the kernel parameters can be removed too.

I hadn't followed the CMA development closely so I am not sure of the
reasons behind restricting it to v6+. The patch that added this doesn't
really talk about why it should be restricted to v6+. I am copying Marek
here to see if he can quickly clarify, but may be you can even start a
new thread asking about this.

Thanks,
Sekhar


From jon-hunter at ti.com  Fri Aug 17 11:02:34 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Fri, 17 Aug 2012 10:02:34 -0500
Subject: gpmc generic retime function (subject was RE: [PATCH v5 3/3]
 ARM: OMAP2+: onenand: prepare for gpmc driver migration)
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9B150D@DBDE01.ent.ti.com>
References: <C8443D0743D26F4388EA172BF4E2A7A93E9A35E1@DBDE01.ent.ti.com>
 <20120705105535.GB1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A39DF@DBDE01.ent.ti.com>
 <20120706120533.GU1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A622E@DBDE01.ent.ti.com>
 <20120710094538.GT1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A64D0@DBDE01.ent.ti.com>
 <20120710131734.GV1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A669D@DBDE01.ent.ti.com>
 <4FFC6330.1040409@ti.com> <20120711064724.GA1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9B150D@DBDE01.ent.ti.com>
Message-ID: <502E5D0A.2030109@ti.com>

Hi Afzal,

Sorry for the delay, I have been out of the office.

On 08/06/2012 08:38 AM, Mohammed, Afzal wrote:
> Hi Tony, Jon,
> 
> On Wed, Jul 11, 2012 at 12:17:25, Tony Lindgren wrote:
>> * Jon Hunter <jon-hunter at ti.com> [120710 10:20]:
> 
>>> The DT node should simply have the information required by the retime
>>> function or gpmc timings themselves if available. In the case of OneNAND
> 
>>> These can be stored in the DT and then translated to gpmc timings at
>>> runtime. DT should only store static timing or clock information known
> 
>> Yup. And the format of the timing data in DT should be standardized so
>> the only differences for each connected peripheral is the retime function.
> 
> If we are able to achieve a generic retime function applicable to all
> peripherals then we don't need wrapper layer for retime handling or two
> linux devices and drivers (one the existing and the other to handle retime)
> to represent a single physical gpmc peripheral device (for DT conversion).
> Then handling core frequency scaling and DT conversion would be easier.
> We were trying to create such a retime function that would be generic so
> as to handle different types of gpmc peripherals.

Sounds like a much better approach!

> And we have been able to create such a function. Below is an implementation
> that has been made for handling asynchronous timings. It has been tested for
> OneNAND & SMSC on OMAP3EVM (rev G & C) with [1-4]. OneNAND was tested using
> [5] (OMAP3EVM OneNAND works in async mode) & SMSC using [6] (mainline does
> not have a timing calculation for smsc911x)

Are you able to verify that the timing calculated by this function are
identical? May be some more details on exactly how you tested this would
be good.

> It was difficult to squeeze tusb6010 timing calculation into generic timing
> calculation, hence a boolean "tusb" has been used. This is what I could
> achieve based on existing retime for tusb6010 and for lack of tusb6010
> timing specifications.
> 
> ----8<-----------------------------------------------------------------------
> 
> /* Device timings in picoseconds */
> struct gpmc_device_timings {
>         u32     cs_setup;       /* CS setup time */
>         u32     adv_setup;      /* ADV setup time */
>         u32     adv_rd_off;     /* ADV read off time */
>         u32     adv_add_hold;   /* address hold time */
>         u32     oe_setup;       /* OE setup time */
>         u32     adv_access;     /* access time from ADV assertion */
>         u32     rd_access;      /* read access time */
>         u32     oe_access;      /* access time from OE assertion */
>         u32     cs_access;      /* access time from CS asertion */
>         u32     rd_cycle;       /* read cycle time */
>         u32     cs_highz;       /* CS deassertion to high Z */
>         u32     oe_highz;       /* OE deassertion to high Z */
>         u32     adv_wr_off;     /* ADV write off time */
>         u32     we_setup;       /* WE setup time */
>         u32     wr_pulse;       /* write assertion time */
>         u32     wr_data_setup;  /* data setup time from write assertion */
>         u32     wr_high;        /* write deassertion time */
>         u32     we_highz;       /* WE deassertion to high Z */
>         u32     wr_cycle;       /* write cycle time */
> 
>         bool    mux;            /* address & data muxed */
>         bool    tusb;           /* peripheral is tusb6010 */

Do you think that there is any value in making the tusb member a "u32
dev_type" and then set it too GPMC_DEVICE_TUSB then this could be used
for other devices in the future too if needed?

> };
> 
> struct gpmc_timings gpmc_calc_timings(struct gpmc_device_timings *dev_t)
> {
>         struct gpmc_timings gpmc_t;
>         bool mux = dev_t->mux;
>         bool tusb = dev_t->tusb;
>         u32 temp;
> 
>         memset(&gpmc_t, 0, sizeof(gpmc_t));
> 
>         /* cs_on */
>         gpmc_t.cs_on = gpmc_round_ns_to_ticks(dev_t->cs_setup / 1000);
> 
>         /* adv_on */
>         temp = dev_t->adv_setup;
>         if (tusb)
>                 temp = max_t(u32,
>                         (gpmc_t.cs_on + gpmc_ticks_to_ns(1)) * 1000, temp);
>         gpmc_t.adv_on = gpmc_round_ns_to_ticks(temp / 1000);

Would it be possible to create a sub-function called
gpmc_calc_timings_tusb() and put all these "if (tusb)" statements in
there? Or maybe a generic function called gpmc_calc_timings_prepare().

For the above case could have ...

void gpmc_calc_timings_prepare(struct gpmc_device_timings *dev_t)
{
	if (dev_t->tusb) {
		dev_t->adv_on = max_t(u32,
		(gpmc_t.cs_on + gpmc_ticks_to_ns(1)) * 1000,
		dev_t->adv_setup);
		...
	} else {
		dev_t->adv_on = dev_t->adv_setup;
		...
	}
}

And then in the gpmc_calc_timings() you would just have ...

         gpmc_t.adv_on = gpmc_round_ns_to_ticks(dev_t->adv_on / 1000);

>         /* adv_rd_off */
>         temp = dev_t->adv_rd_off;
>         if (tusb)
>                 temp = max_t(u32,
>                         (gpmc_t.adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
>         gpmc_t.adv_rd_off = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         /* oe_on */
>         if (mux)
>                 temp = gpmc_t.adv_rd_off * 1000 + dev_t->adv_add_hold;
>         else
>                 temp = dev_t->oe_setup;
>         if (tusb)
>                 temp = max_t(u32,
>                         (gpmc_t.adv_rd_off + gpmc_ticks_to_ns(1)) * 1000, temp);
>         gpmc_t.oe_on = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         /* access */
>         temp = max_t(u32, dev_t->rd_access,
>                                 gpmc_t.oe_on * 1000 + dev_t->oe_access);
>         temp = max_t(u32, temp,
>                                 gpmc_t.cs_on * 1000 + dev_t->cs_access);
>         temp = max_t(u32, temp,
>                                 gpmc_t.adv_on * 1000 + dev_t->adv_access);
>         if (tusb) {
>                 temp = max_t(u32, temp,
>                                 (gpmc_t.oe_on + gpmc_ticks_to_ns(1)) * 1000);
>                 temp = max_t(u32, temp, gpmc_t.oe_on * 1000 + 300);
>         }
>         gpmc_t.access = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         gpmc_t.oe_off = gpmc_t.access + gpmc_ticks_to_ns(1);
>         gpmc_t.cs_rd_off = gpmc_t.oe_off;
> 
>         /* rd_cycle */
>         temp = max_t(u32, dev_t->rd_cycle,
>                         gpmc_t.cs_rd_off * 1000 + dev_t->cs_highz);
>         temp = max_t(u32, temp,
>                         gpmc_t.oe_off * 1000 + dev_t->oe_highz);
>         if (tusb) {
>                 temp = max_t(u32, temp,
>                         (gpmc_t.cs_rd_off + gpmc_ticks_to_ns(1)) * 1000);
>                 temp = max_t(u32, temp, gpmc_t.cs_rd_off * 1000 + 7000);
>         }
>         gpmc_t.rd_cycle = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         /* adv_wr_off */
>         temp = dev_t->adv_wr_off;
>         if (tusb)
>                 temp = max_t(u32,
>                         (gpmc_t.adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
>         gpmc_t.adv_wr_off = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         /* we_on */
>         if (mux)
>                 temp = gpmc_t.adv_wr_off * 1000 + dev_t->adv_add_hold;
>         else
>                 temp = dev_t->we_setup;
>         if (tusb)
>                 temp = max_t(u32,
>                         (gpmc_t.adv_wr_off + gpmc_ticks_to_ns(1)) * 1000, temp);
>         gpmc_t.we_on = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         gpmc_t.wr_data_mux_bus = gpmc_t.we_on;
> 
>         /* we_off */
>         temp = max_t(u32, gpmc_t.we_on * 1000 + dev_t->wr_pulse,
>                         gpmc_t.we_on * 1000 + dev_t->wr_data_setup);
>         if (tusb) {
>                 temp = max_t(u32, temp,
>                                 (gpmc_t.we_on + gpmc_ticks_to_ns(1)) * 1000);
>                 temp = max_t(u32, temp, gpmc_t.we_on * 1000 + 300);
>         }
>         gpmc_t.we_off = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         gpmc_t.cs_wr_off = gpmc_round_ns_to_ticks((gpmc_t.we_off * 1000 +
>                                 dev_t->wr_high) / 1000);
> 
>         /* wr_cycle */
>         temp = max_t(u32, dev_t->wr_cycle,
>                         gpmc_t.cs_wr_off * 1000 + dev_t->cs_highz);
>         temp = max_t(u32, temp,
>                         gpmc_t.we_off * 1000 + dev_t->we_highz);
>         if (tusb) {
>                 temp = max_t(u32, temp,
>                         (gpmc_t.cs_wr_off + gpmc_ticks_to_ns(1)) * 1000);
>                 temp = max_t(u32, temp, gpmc_t.cs_wr_off * 1000 + 7000);
>         }
>         gpmc_t.wr_cycle = gpmc_round_ns_to_ticks(temp / 1000);
> 
>         return gpmc_t;
> }
> 
>>> From a high-level I think that the goal should be ...
>>>
>>> gpmc_probe
>>> 	--> request CS
>>> 	--> calls retime function to calculate gpmc timing (optional)
>>> 	--> configures CS
>>> 	--> registers peripheral device
>>
>> Yes with few additions.. Connected peripheral probe requests CS from
>> gpmc with the optional retime function pointer passed as a parameter.
>> After gpmc code has determined the CS is available, it calls the optional
>> retime function before returning back to the connected peripheral probe.
>>
>> So how about the following with a bit more details:
>>
>> gpmc_probe
>> 	--> just sets up gpmc resources then idles itself
>>
>> connected peripheral probe
>> 	--> calls gpmc_cs_request() with gpmc timings from DT and an
>> 	    optional retime function as a parameter
>> 	--> gpmc_cs_request() allocates the CS
>> 	--> gpmc_cs_request() calls the optional retime function and
>> 	    if not specified, just sets the DT timings and disables
>> 	    L3 DFS
>> 	--> gpmc_cs_request() returns to connected peripheral probe
> 
> Once we are able to use the generic retime function as mentioned above,
> instead of requiring additional driver for each peripheral that has
> retime and its effect on complicating DT conversion,  we can have the
> gpmc driver organization similar to the one that was posted
> earlier[4].
> 
> With DT, we can pass peripheral timings that has been generalized as in 
> gpmc_device_timings structure. In addition to timings, we would need
> to have fields for specifying whether multiplexed or not ("mux" in
> struct gpmc_device_timings), asynchronous or synchronous.
> 
> With the generic retime function, driver could do as follows,
> 
> gpmc_probe
>   -> setup_device
>     -> setup_cs
>       ->setup_cs_config_timing
> 		if (gpmc_timings)
> 			gpmc_cs_set_timings(gpmc_t);
> 		else if (gpmc_device_timings) {
> 			gpmc_t = gpmc_calc_timings();
> 			gpmc_cs_set_timings(cs, &gpmc_t);
> 		}
> 

I will let Tony comment on how he would like the above to work.

> In the above, addition to already posted driver series [4] would
> be the "else if" portions.
> 
> For core DFS, we could register a notifier that would invoke,
> 	gpmc_t = gpmc_calc_timings(); /* defined above */
> 	gpmc_cs_set-timings(cs, &gpmc_t);
> enabling us to have the gpmc timings adjusted.
> 
> 
> Please let me know your comments on the above. Currently I am working
> on achieving generalized timing for synchronous operations too so
> that gpmc timings can be calculated at runtime using a single generic
> retime function for all kinds of operations like mux, sync/async etc.

Great!

Cheers
Jon


From linus.walleij at linaro.org  Fri Aug 17 11:02:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 17 Aug 2012 17:02:32 +0200
Subject: [PATCH 1/1 v4] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <20120808131158.GD8227@gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120808131158.GD8227@gmail.com>
Message-ID: <CACRpkdb+6S5yYvVjrr2f+wubE43dzD3i=OVfWtM_U+HW_XZX1A@mail.gmail.com>

On Wed, Aug 8, 2012 at 3:11 PM, Lee Jones <lee.jones at linaro.org> wrote:

> From: Lee Jones <lee.jones at linaro.org>
> Date: Tue, 7 Aug 2012 12:27:24 +0100
> Subject: [PATCH 1/1 v4] i2c/nomadik: Add default configuration into the Nomadik I2C driver

Wolfram are you taking this v4 patch into the i2c tree for the -rc:s?

Right now this is causing boot regressions so we need it badly...

Yours,
Linus Walleij


From m.szyprowski at samsung.com  Fri Aug 17 11:09:38 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 17 Aug 2012 17:09:38 +0200
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions for
 VPIF
In-Reply-To: <502E5C40.803@ti.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
 <502A4464.3020706@ti.com> <502CC7CD.80906@ti.com> <502E5C40.803@ti.com>
Message-ID: <024a01cd7c8a$541efb20$fc5cf160$%szyprowski@samsung.com>

Hello,

On Friday, August 17, 2012 4:59 PM Sekhar Nori wrote:

> On 8/16/2012 3:43 PM, Prabhakar Lad wrote:
> > On Tuesday 14 August 2012 05:58 PM, Sekhar Nori wrote:
> 
> [...]
> 
> >>> +int __init da850_register_vpif_display(struct vpif_display_config
> >>> +						*display_config)
> >>> +{
> >>> +	struct resource da850_vpif_display_resource[] = {
> >>> +		{
> >>> +			.start = IRQ_DA850_VPIFINT,
> >>> +			.end   = IRQ_DA850_VPIFINT,
> >>> +			.flags = IORESOURCE_IRQ,
> >>> +		},
> >>> +		{},
> >>> +	};
> >>> +	unsigned long phys_end_kernel;
> >>> +	int ret;
> >>> +
> >>> +	if (vpif_disp_cont_bufsize) {
> >>> +		phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
> >>> +					(num_physpages << PAGE_SHIFT);
> >>> +		phys_end_kernel += vpif_disp_cont_buf_offset;
> >>> +		da850_vpif_display_resource[1].start = phys_end_kernel;
> >>> +		da850_vpif_display_resource[1].end = phys_end_kernel +
> >>> +						vpif_disp_cont_bufsize - 1;
> >>> +		da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
> >>> +
> >>> +		if (!request_mem_region(da850_vpif_display_resource[1].start,
> >>> +				resource_size(&da850_vpif_display_resource[1]),
> >>> +				da850_vpif_display_dev.name)) {
> >>> +			pr_err("region already claimed.\n");
> >>> +			return -EBUSY;
> >>> +		}
> >>> +		ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
> >>> +				phys_end_kernel, phys_end_kernel,
> >>> +				vpif_disp_cont_bufsize,
> >>> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> >>> +
> >>> +		if (!ret)
> >>> +			return -ENOMEM;
> >>> +	}
> >>> +	ret = platform_device_add_resources(&da850_vpif_display_dev,
> >>> +				da850_vpif_display_resource,
> >>> +				ARRAY_SIZE(da850_vpif_display_resource));
> >>
> >> You are taking memory at the end of RAM and passing it as a IO resource
> >> to the driver. This is not correct. For contiguous memory needs can you
> >> look at the recently merged CMA framework (include/linux/dma-contiguous.h)
> >>
> > Ok. But looks like CMA is enabled for CPU_V6/V6K/V7. If CMA is enabled
> > for ARM926 too than we can use the global CMA itself rather then doing
> > it for each device, then three will be no need to do the above and all
> > the kernel parameters can be removed too.
> 
> I hadn't followed the CMA development closely so I am not sure of the
> reasons behind restricting it to v6+. The patch that added this doesn't
> really talk about why it should be restricted to v6+. I am copying Marek
> here to see if he can quickly clarify, but may be you can even start a
> new thread asking about this.

Frankly, this is a leftover from some earlier suggestions that CMA should solve the
aliasing of coherent mappings, which might be a problem on v6+. If it works correctly
on pre-v6, then this dependency should be removed. Feel free to submit a patch and 
I will take it to my fixes branch.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From gcembed at gmail.com  Fri Aug 17 11:16:03 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Fri, 17 Aug 2012 17:16:03 +0200
Subject: mx27_3ds : Sound doesn't work anymore on linux-next
Message-ID: <502E6033.4010805@gmail.com>

Hi,
It is several days that I tried to make sound work on mx27_3ds platform 
from linux-next (daily cloned/pulled) but each time I try start start 
aplay or alsamixer, the process freeze and CTRL+C has not effect. I can 
open another SSH session and execute other commands but alsa commands 
always freeze.
The sound card is correctly installer at boot :

imx_mc13783 imx_mc13783.0:  mc13783-hifi <-> imx-ssi.0 mapping ok
ALSA device list:
   #0: imx_mc13783

I only apply the patch "[PATCH 1/2] ARM: mx27pdk: Add audio support". I 
attach my config file.

I try to apply patch on a previous commit when I told that this patch 
was working but it didn't succeed the is still freezing.
I try to make it working on another mx27-based platform but same 
problem. I try to update Alsa from version 1.0.23 to 1.0.25 but same 
behaviour.
What is wrong ?

Regards,
Ga?tan Carlier.
-------------- next part --------------
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.6.0-rc2 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_HAVE_IRQ_WORK=y
CONFIG_IRQ_WORK=y

#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_FHANDLE is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y

#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_SPARSE_IRQ=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

#
# RCU Subsystem
#
CONFIG_TINY_PREEMPT_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_RCU_BOOST is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
# CONFIG_CGROUP_DEBUG is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CPUSETS is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_RESOURCE_COUNTERS is not set
# CONFIG_CGROUP_PERF is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_BLK_CGROUP is not set
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_NAMESPACES is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EXPERT=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_PROFILING=y
CONFIG_OPROFILE=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_UNINLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_UNLOCK is not set
# CONFIG_INLINE_READ_UNLOCK_BH is not set
# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_UNLOCK is not set
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
CONFIG_FREEZER=y

#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CNS3XXX is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_PRIMA2 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
CONFIG_ARCH_MXC=y
# CONFIG_ARCH_MXS is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_PICOXCELL is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_VT8500 is not set
# CONFIG_ARCH_ZYNQ is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
CONFIG_IMX_HAVE_PLATFORM_FEC=y
CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA=y
CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
CONFIG_IMX_HAVE_PLATFORM_IMX_FB=y
CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA=y
CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
CONFIG_IMX_HAVE_PLATFORM_MXC_MMC=y
CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y

#
# Freescale MXC Implementations
#
CONFIG_ARCH_IMX_V4_V5=y
# CONFIG_ARCH_IMX_V6_V7 is not set
CONFIG_MACH_MX27=y
CONFIG_SOC_IMX27=y

#
# MX1 platforms:
#
# CONFIG_ARCH_MX1ADS is not set
# CONFIG_MACH_SCB9328 is not set
# CONFIG_MACH_APF9328 is not set

#
# MX21 platforms:
#
# CONFIG_MACH_MX21ADS is not set

#
# MX25 platforms:
#
# CONFIG_MACH_MX25_3DS is not set
# CONFIG_MACH_EUKREA_CPUIMX25SD is not set

#
# MX27 platforms:
#
# CONFIG_MACH_MX27ADS is not set
# CONFIG_MACH_PCM038 is not set
# CONFIG_MACH_CPUIMX27 is not set
CONFIG_MACH_MX27_3DS=y
# CONFIG_MACH_IMX27_VISSTRIM_M10 is not set
# CONFIG_MACH_IMX27LITE is not set
# CONFIG_MACH_PCA100 is not set
# CONFIG_MACH_MXT_TD60 is not set
# CONFIG_MACH_IMX27IPCAM is not set
CONFIG_MACH_IMX27_DT=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_AVIC=y
CONFIG_MXC_DEBUG_BOARD=y
CONFIG_IMX_HAVE_IOMUX_V1=y

#
# Processor Type
#
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5TJ=y
CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_USE_DOMAINS=y

#
# Processor Features
#
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_ARM_NR_BANKS=8
CONFIG_MULTI_IRQ_HANDLER=y

#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_ARCH_NR_GPIO=0
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
# CONFIG_HIGHMEM is not set
CONFIG_HW_PERF_EVENTS=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_COMPACTION is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CLEANCACHE is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_DEPRECATED_PARAM_STRUCT is not set

#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y

#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
# CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_PM_SLEEP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_APM_EMULATION is not set
CONFIG_PM_CLK=y
CONFIG_CPU_PM=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
# CONFIG_XFRM_USER is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_NETPRIO_CGROUP is not set
CONFIG_BQL=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_RFKILL_REGULATOR is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
# CONFIG_DMA_SHARED_BUFFER is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
CONFIG_DTC=y
CONFIG_OF=y

#
# Device Tree and Open Firmware support
#
# CONFIG_PROC_DEVICETREE is not set
# CONFIG_OF_SELFTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_DEVICE=y
CONFIG_OF_I2C=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set

#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
# CONFIG_BLK_DEV_RBD is not set

#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_ATMEL_PWM is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_BMP085_I2C is not set
# CONFIG_BMP085_SPI is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set

#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_BLK_DEV_SD is not set
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_TARGET_CORE is not set
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
CONFIG_MII=y
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set

#
# CAIF transport drivers
#
CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_CALXEDA_XGMAC is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_DM9000 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_FARADAY is not set
CONFIG_NET_VENDOR_FREESCALE=y
CONFIG_FEC=y
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
CONFIG_SMSC_PHY=y
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_WLAN is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_IMX is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVKMEM=y

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_EM is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_OF_PLATFORM is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_TTY_PRINTK is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_IMX=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_IMX=y
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PXA2XX_PCI is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_HSI is not set

#
# PPS support
#
# CONFIG_PPS is not set

#
# PPS generators support
#

#
# PTP clock support
#

#
# Enable Device Drivers -> PPS to see the PTP clock options.
#
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_OF_GPIO=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers:
#
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_EM is not set
CONFIG_GPIO_MXC=y

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
# CONFIG_GPIO_ADP5588 is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_74X164 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_POWER_AVS is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
CONFIG_SENSORS_MC13783_ADC=y
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_CORE is not set
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_IMX2_WDT is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
CONFIG_MFD_MC13783=y
CONFIG_MFD_MC13XXX=y
CONFIG_MFD_MC13XXX_SPI=y
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_PALMAS is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_MC13XXX_CORE=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_RC_SUPPORT is not set
# CONFIG_MEDIA_CONTROLLER is not set
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_COMMON=y

#
# Media drivers
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEOBUF_GEN=y
CONFIG_V4L2_MEM2MEM_DEV=y
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set

#
# Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
# CONFIG_VIDEO_MSP3400 is not set
# CONFIG_VIDEO_CS5345 is not set
# CONFIG_VIDEO_CS53L32A is not set
# CONFIG_VIDEO_TLV320AIC23B is not set
# CONFIG_VIDEO_WM8775 is not set
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_SAA7110 is not set
# CONFIG_VIDEO_SAA711X is not set
# CONFIG_VIDEO_SAA7191 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
# CONFIG_VIDEO_CX25840 is not set

#
# MPEG video encoders
#
# CONFIG_VIDEO_CX2341X is not set

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set

#
# Camera sensor devices
#
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_VS6624 is not set
# CONFIG_VIDEO_MT9V011 is not set
# CONFIG_VIDEO_TCM825X is not set
# CONFIG_VIDEO_SR030PC30 is not set

#
# Flash devices
#

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set

#
# Miscelaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_VIVI is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_TIMBERDALE is not set
CONFIG_SOC_CAMERA=y
# CONFIG_SOC_CAMERA_IMX074 is not set
# CONFIG_SOC_CAMERA_MT9M001 is not set
# CONFIG_SOC_CAMERA_MT9M111 is not set
# CONFIG_SOC_CAMERA_MT9T031 is not set
# CONFIG_SOC_CAMERA_MT9T112 is not set
# CONFIG_SOC_CAMERA_MT9V022 is not set
# CONFIG_SOC_CAMERA_RJ54N1 is not set
# CONFIG_SOC_CAMERA_TW9910 is not set
# CONFIG_SOC_CAMERA_PLATFORM is not set
CONFIG_SOC_CAMERA_OV2640=y
# CONFIG_SOC_CAMERA_OV5642 is not set
# CONFIG_SOC_CAMERA_OV6650 is not set
# CONFIG_SOC_CAMERA_OV772X is not set
# CONFIG_SOC_CAMERA_OV9640 is not set
# CONFIG_SOC_CAMERA_OV9740 is not set
# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
# CONFIG_VIDEO_SH_MOBILE_CEU is not set
CONFIG_VIDEO_MX2_HOSTSUPPORT=y
CONFIG_VIDEO_MX2=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
# CONFIG_VIDEO_CODA is not set
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
CONFIG_VIDEO_MX2_EMMAPRP=y

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_WMT_GE_ROPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_IMX is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_TMIO is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_AUO_K190X is not set
# CONFIG_EXYNOS_VIDEO is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_S6E63M0 is not set
# CONFIG_LCD_LD9040 is not set
# CONFIG_LCD_AMS369FG06 is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LP855X is not set

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
# CONFIG_FONT_8x16 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_JACK=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
# CONFIG_SND_HRTIMER is not set
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
# CONFIG_SND_PCM_XRUN_DEBUG is not set
# CONFIG_SND_RAWMIDI_SEQ is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_ALOOP is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_DMAENGINE_PCM=y
# CONFIG_SND_DESIGNWARE_I2S is not set
CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_IMX_SSI=y
CONFIG_SND_SOC_IMX_PCM=y
CONFIG_SND_SOC_IMX_PCM_DMA=y
CONFIG_SND_SOC_IMX_AUDMUX=y
# CONFIG_SND_SOC_IMX_SGTL5000 is not set
CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
CONFIG_SND_SOC_MC13783=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_SOUND_PRIME is not set

#
# HID support
#
# CONFIG_HID is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_USB_ARCH_HAS_XHCI is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
# CONFIG_DW_DMAC is not set
# CONFIG_MX3_IPU is not set
# CONFIG_TIMB_DMA is not set
# CONFIG_IMX_SDMA is not set
CONFIG_IMX_DMA=y
CONFIG_DMA_ENGINE=y

#
# DMA Clients
#
# CONFIG_NET_DMA is not set
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set

#
# Virtio drivers
#
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_STAGING is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_DEBUG=y

#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_MMIO=y
# CONFIG_IOMMU_SUPPORT is not set

#
# Remoteproc drivers (EXPERIMENTAL)
#

#
# Rpmsg drivers (EXPERIMENTAL)
#
# CONFIG_VIRT_DRIVERS is not set
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_PWM is not set

#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_SWAP is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
CONFIG_NLS_ISO8859_15=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set

#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_PREEMPT=y
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_PROVE_RCU_DELAY is not set
# CONFIG_SPARSE_RCU_POINTER is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_RING_BUFFER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_PROBE_EVENTS is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_STRICT_DEVMEM is not set
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_LL is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_MANAGER2 is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set

#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set

#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_ZLIB is not set
CONFIG_CRYPTO_LZO=y

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
CONFIG_CRYPTO_HW=y
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
# CONFIG_CRC_CCITT is not set
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
# CONFIG_XZ_DEC_BCJ is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set

From gcembed at gmail.com  Fri Aug 17 11:28:41 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Fri, 17 Aug 2012 17:28:41 +0200
Subject: mx27_3ds : Sound doesn't work anymore on linux-next
In-Reply-To: <502E6033.4010805@gmail.com>
References: <502E6033.4010805@gmail.com>
Message-ID: <502E6329.60308@gmail.com>

Just some more informations, process enter in D+ state and this is so 
impossible to kill them.
On 08/17/2012 05:16 PM, Ga?tan Carlier wrote:
> Hi,
> It is several days that I tried to make sound work on mx27_3ds platform
> from linux-next (daily cloned/pulled) but each time I try start start
> aplay or alsamixer, the process freeze and CTRL+C has not effect. I can
> open another SSH session and execute other commands but alsa commands
> always freeze.
> The sound card is correctly installer at boot :
>
> imx_mc13783 imx_mc13783.0:  mc13783-hifi <-> imx-ssi.0 mapping ok
> ALSA device list:
>    #0: imx_mc13783
>
> I only apply the patch "[PATCH 1/2] ARM: mx27pdk: Add audio support". I
> attach my config file.
>
> I try to apply patch on a previous commit when I told that this patch
> was working but it didn't succeed the is still freezing.
> I try to make it working on another mx27-based platform but same
> problem. I try to update Alsa from version 1.0.23 to 1.0.25 but same
> behaviour.
> What is wrong ?
>
> Regards,
> Ga?tan Carlier.

Regards,
Ga?tan.



From richard.genoud at gmail.com  Fri Aug 17 11:39:32 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Fri, 17 Aug 2012 17:39:32 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <CACRpkdY2HjwOBy7P8mZ81f8bYU4V2=taXzqv03q9NWqbfMVQ4A@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdY2HjwOBy7P8mZ81f8bYU4V2=taXzqv03q9NWqbfMVQ4A@mail.gmail.com>
Message-ID: <CACQ1gAjy7kT9emFGYQY5m1=kS3S5SPS4F5yMCV2ZzMxbhPcFGQ@mail.gmail.com>

Jean-Christophe, it seems that you forgot those clocks:

Regards,
Richard.


    sam9x5: add clocks for pinctrl

    Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 arch/arm/mach-at91/at91sam9x5.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..55b52ef 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,6 +231,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
+
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.2.5


From dedekind1 at gmail.com  Fri Aug 17 11:52:58 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 17 Aug 2012 18:52:58 +0300
Subject: [PATCH v2 1/3] mtd: nand: Include IMX6 in the list of supported
 SoCs
In-Reply-To: <1343215100-24005-1-git-send-email-festevam@gmail.com>
References: <1343215100-24005-1-git-send-email-festevam@gmail.com>
Message-ID: <1345218778.1003.13.camel@sauron.fi.intel.com>

On Wed, 2012-07-25 at 08:18 -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Include IMX6 in the list of supported SoCs.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com> 

Pushed this one to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From prabhakar.csengg at gmail.com  Fri Aug 17 11:50:01 2012
From: prabhakar.csengg at gmail.com (Prabhakar Lad)
Date: Fri, 17 Aug 2012 21:20:01 +0530
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions for
 VPIF
In-Reply-To: <024a01cd7c8a$541efb20$fc5cf160$%szyprowski@samsung.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
 <502A4464.3020706@ti.com>
 <502CC7CD.80906@ti.com> <502E5C40.803@ti.com>
 <024a01cd7c8a$541efb20$fc5cf160$%szyprowski@samsung.com>
Message-ID: <CA+V-a8vcFhkF-dEOtBpx=v8P5DC+4qjsG8xxCeDRxkYTQTSStg@mail.gmail.com>

Hi Marek,

On Fri, Aug 17, 2012 at 8:39 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Friday, August 17, 2012 4:59 PM Sekhar Nori wrote:
>
>> On 8/16/2012 3:43 PM, Prabhakar Lad wrote:
>> > On Tuesday 14 August 2012 05:58 PM, Sekhar Nori wrote:
>>
>> [...]
>>
>> >>> +int __init da850_register_vpif_display(struct vpif_display_config
>> >>> +                                         *display_config)
>> >>> +{
>> >>> + struct resource da850_vpif_display_resource[] = {
>> >>> +         {
>> >>> +                 .start = IRQ_DA850_VPIFINT,
>> >>> +                 .end   = IRQ_DA850_VPIFINT,
>> >>> +                 .flags = IORESOURCE_IRQ,
>> >>> +         },
>> >>> +         {},
>> >>> + };
>> >>> + unsigned long phys_end_kernel;
>> >>> + int ret;
>> >>> +
>> >>> + if (vpif_disp_cont_bufsize) {
>> >>> +         phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
>> >>> +                                 (num_physpages << PAGE_SHIFT);
>> >>> +         phys_end_kernel += vpif_disp_cont_buf_offset;
>> >>> +         da850_vpif_display_resource[1].start = phys_end_kernel;
>> >>> +         da850_vpif_display_resource[1].end = phys_end_kernel +
>> >>> +                                         vpif_disp_cont_bufsize - 1;
>> >>> +         da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
>> >>> +
>> >>> +         if (!request_mem_region(da850_vpif_display_resource[1].start,
>> >>> +                         resource_size(&da850_vpif_display_resource[1]),
>> >>> +                         da850_vpif_display_dev.name)) {
>> >>> +                 pr_err("region already claimed.\n");
>> >>> +                 return -EBUSY;
>> >>> +         }
>> >>> +         ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
>> >>> +                         phys_end_kernel, phys_end_kernel,
>> >>> +                         vpif_disp_cont_bufsize,
>> >>> +                         DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
>> >>> +
>> >>> +         if (!ret)
>> >>> +                 return -ENOMEM;
>> >>> + }
>> >>> + ret = platform_device_add_resources(&da850_vpif_display_dev,
>> >>> +                         da850_vpif_display_resource,
>> >>> +                         ARRAY_SIZE(da850_vpif_display_resource));
>> >>
>> >> You are taking memory at the end of RAM and passing it as a IO resource
>> >> to the driver. This is not correct. For contiguous memory needs can you
>> >> look at the recently merged CMA framework (include/linux/dma-contiguous.h)
>> >>
>> > Ok. But looks like CMA is enabled for CPU_V6/V6K/V7. If CMA is enabled
>> > for ARM926 too than we can use the global CMA itself rather then doing
>> > it for each device, then three will be no need to do the above and all
>> > the kernel parameters can be removed too.
>>
>> I hadn't followed the CMA development closely so I am not sure of the
>> reasons behind restricting it to v6+. The patch that added this doesn't
>> really talk about why it should be restricted to v6+. I am copying Marek
>> here to see if he can quickly clarify, but may be you can even start a
>> new thread asking about this.
>
> Frankly, this is a leftover from some earlier suggestions that CMA should solve the
> aliasing of coherent mappings, which might be a problem on v6+. If it works correctly
> on pre-v6, then this dependency should be removed. Feel free to submit a patch and
> I will take it to my fixes branch.
>

I have created a patch for enabling CMA on CPU32_v5 [1], and also
tested it works.
Soon posting this patch.

[1] http://git.linuxtv.org/mhadli/v4l-dvb-davinci_devices.git/commitdiff/e940a1b9262bde96eec4b18971a6307f24262667?hp=2f30ae4ee373fe4c69ab1606373538dcc99ed283

Thanks and Regards,
--Prabhakar Lad

> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jonathan.austin at arm.com  Fri Aug 17 11:53:44 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 17 Aug 2012 16:53:44 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
References: <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
Message-ID: <502E6908.4070408@arm.com>

On 15/08/12 23:08, Martin Rosenberg wrote:

>> It's intention is to support self-modifying userspace code only and
>> also intended to be used over a _short_ range of addresses only -
>> it works by flushing each _individual_ cache line over the range of
>> addreses requested.
> Documenting the current behavior would mostly be acceptable, but it
> is rather confusing (and took quite some time to track down)
> 
>> If it's going to be used for significantly larger areas, then we
>> need to think about imposing a limit, upon which we just flush the
>> entire cache and be done with it.
> 
> I found that there was still a net win making fewer syscalls, even
> with the overhead of flushing extra cache lines. In the cases where
> the range is discontiguous, 


Was this net win on platforms other than ARM? Was it still evident after
working around the truncation/multiple vma issue that occurs?

I'm curious as to whether some (even most?) of your performance
improvement could be coming from the range truncation. Perhaps the
performance is better because you're actually doing less flushing, and
not governed by the syscall overhead?

Consider an extreme version of the case you describe below: lets say
instruction 1/20 was in the first vma and 19/20 are in subsequent vmas.
In the un-coalesced case you are going to flush several pages covering
the addresses of all 20 instructions, but in your coalesced case I think
only one page that contains the first instruction[1] will get
flushed...(which, as you know, means you've got a bug!)

> I usually need to do something silly,
> like flush 20 individual instructions that are scattered throughout
> several hundred MB of memory. I think the fastest method for
> flushing in this case would be to shave a different call, with a
> different api, where userspace can provide an array of addresses that
> need to be flushed, but that sounds like material for a new thread.
> Thanks --Marty

A better understanding of the details of your case would be a good
starting point for a discussion. For example it might be nice to know
how significant the syscall overhead is compared to the time to flush
ranges you're interested in...

Also, as Russell says, there'll be a point at which flushing the whole
cache is better than flushing a load of odd chunks here and there...

Jonny

[1] Had you noticed that our implementation flushes a minimum of 1-page?

(cacheflush.h:257)
#define flush_cache_user_range(start,end) \
        __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))

Does that have a bearing on what you're doing?





From catalin.marinas at arm.com  Fri Aug 17 12:07:29 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 17:07:29 +0100
Subject: [PATCH v2 06/31] arm64: MMU fault handling and page table
 management
In-Reply-To: <201208151347.01169.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-7-git-send-email-catalin.marinas@arm.com>
 <201208151347.01169.arnd@arndb.de>
Message-ID: <20120817160729.GJ24389@arm.com>

On Wed, Aug 15, 2012 at 02:47:00PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +pgd_t *pgd_alloc(struct mm_struct *mm)
> > +{
> > +	pgd_t *new_pgd;
> > +
> > +	new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, PGD_ORDER);
> > +	if (!new_pgd)
> > +		return NULL;
> > +
> > +	memset(new_pgd, 0, PAGE_SIZE << PGD_ORDER);
> > +
> > +	return new_pgd;
> > +}
> > +
> > +void pgd_free(struct mm_struct *mm, pgd_t *pgd)
> > +{
> > +	free_pages((unsigned long)pgd, PGD_ORDER);
> > +}
>  
> According to the documentation, you should only need 8kb for the pgd on
> a 64kb page system. Is it required that you use up a full page here?

Not with the current virtual memory layout with 39-bit address space for
kernel. With 64K pages we can increase the address space to 42-bit while
still using 2-level page table, in which case a full page is used.

But for now I'll keep the same virtual memory layout and add a check on
(PTRS_PER_PGD * sizeof(pgd_t)), the compiler will choose the right path.

-- 
Catalin


From catalin.marinas at arm.com  Fri Aug 17 12:15:28 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 17 Aug 2012 17:15:28 +0100
Subject: [PATCH v2 07/31] arm64: Process management
In-Reply-To: <201208151353.01367.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-8-git-send-email-catalin.marinas@arm.com>
 <201208151353.01367.arnd@arndb.de>
Message-ID: <20120817161528.GK24389@arm.com>

On Wed, Aug 15, 2012 at 02:53:01PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +#define THREAD_SIZE_ORDER	1
> > +#define THREAD_SIZE		8192
> > +#define THREAD_START_SP		(THREAD_SIZE - 16)
> 
> THREAD_SIZE_ORDER looks wrong for 64kb-page kernels. It also doesn't seem to
> be used, so better remove it.

It's used in kernel/fork.c if THREAD_SIZE >= PAGE_SIZE. I'll define it
conditionally.

-- 
Catalin


From jonathan.austin at arm.com  Fri Aug 17 13:03:00 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri, 17 Aug 2012 18:03:00 +0100
Subject: [PATCH] arm: mm: Fix vmalloc overlap check for !HIGHMEM
Message-ID: <1345222980-16965-1-git-send-email-jonathan.austin@arm.com>

With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
partially overlap the vmalloc region. The test for partial overlap checks
__va(bank->start + bank->size) > vmalloc_min. This is not appropriate if
there is a non-linear translation between virtual and physical addresses,
as bank->start + bank->size is actually in the bank following the one being
interrogated.

In most cases, even when using SPARSEMEM, this is not problematic as the
subsequent bank will start at a higher va than the one in question. However
if the physical to virtual address conversion is not monotonic increasing,
the incorrect test could result in a bank not being truncated when it
should be.

This patch ensures we perform the va-pa conversion on memory from the
bank we are interested in, not the following one.

Reported-by: ????????? (Steve) <zhanzhenbo at gmail.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---

This is modified based on Russell's feedback in the original
discussion (Why the region area don't decrease 1 in function
sanity_check_meminfo?)

 arch/arm/mm/mmu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d045..dbd9ff6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -961,8 +961,8 @@ void __init sanity_check_meminfo(void)
 		 * Check whether this memory bank would partially overlap
 		 * the vmalloc area.
 		 */
-		if (__va(bank->start + bank->size) > vmalloc_min ||
-		    __va(bank->start + bank->size) < __va(bank->start)) {
+		if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
+		    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
 			unsigned long newsize = vmalloc_min - __va(bank->start);
 			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
 			       "to -%.8llx (vmalloc region overlap).\n",
-- 
1.7.1




From alanbutty12 at gmail.com  Fri Aug 17 13:30:27 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 17:30:27 +0000
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <20120817132629.GA2232@pengutronix.de>
 <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>
Message-ID: <CADhrpJ6352dHG5ieN5fxvAno2HLq-5fVfCmU-HP9nEz_SaA4ew@mail.gmail.com>

On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
> On 17 August 2012 13:26, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
>> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>>> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
>>> on my ix2-200
>>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
>>> and now even on 3.6 rc1
>>> and the next dated today 17 august that when i use git for example:
>>>
>>> git clone git://git.videolan.org/x264
>>>
>>> my system just crash's / hangs and even through the serial port i get
>>> no response.
>>> This also happens when i try to access a web interface for example the
>>> serviio java webui.
>>>
>>> The second issue i have noticed is that my raid 0 array hangs / pauses
>>> when being mounted
>>> at system startup. (for approximatly 30 seconds maybe more maybe less
>>> im not certain).
>>> But again on the 3.3.7 kernel there was no issue and no hang.
>>>
>>> If i return to 3.3.7 everything works fine with no other modifications
>>> to the os or kernels.
>>> I am using debian wheezy at the moment but also tried debian squeeze
>>> so it does not
>>> seem to be related to the specific linux version just the kernel.
>> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
>> be the obvious range to test.
>>
>> You can also try to enable the various debugging options like
>>
>>         CONFIG_DETECT_HUNG_TASK
>>         CONFIG_PROVE_LOCKING
>>         CONFIG_DEBUG_ATOMIC_SLEEP
>>         CONFIG_MAGIC_SYSRQ
>>
>> or try https://lkml.org/lkml/2012/5/26/83.
>>
>> Best regards
>> Uwe
>>
>> --
>> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
>> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>
> i enabled the options you said there and i see alot of the following
> popping up while connected through serial:
>
>  BUG: sleeping function called from invalid context at
> include/linux/freezer.h:46
> [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180, name:
> console-kit-dae
> [  126.904566] no locks held by console-kit-dae/2180.
> [  126.909378] irq event stamp: 27643
> [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
> _raw_spin_unlock_irqrestore+0x3c/0x5c
> [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
> ret_fast_syscall+0xc/0x38
> [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
> irq_exit+0x54/0xb8
> [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
> irq_exit+0x54/0xb8
> [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
> [<c000b414>] (do_signal+0x84/0x5c0)
> [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from [<c000be0c>]
> (do_notify_resume+0x18/0x60)
> [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
> [<c0009120>] (work_pending+0x24/0x28)
>
> there seems to be alot more of them when i have serviio upnp server running.

After a little testing with those config options enabled that you
sujested iv found that the problem with git first appears in the 3.4.1
kernel.
For example:
in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264' successfully.

>From 3.4.1 kernel on  I can not use 'git clone
git://git.videolan.org/x264' the system hangs / crashes with no output
at all.

the other issue the hang / stall while mounting my etx4 raid 0 is
actualy much more recent than i remembered i have tested each kernel
from 3.4.0 all the way to 3.4.9 with the config options enabled as
sujested before and the stall first starts in kernel 3.4.8 and the
following bug keeps popping up repeatedly until the raid is mounted
and then anytime a disk is accessed it seems. I was certain it had
been popping up before 3.4.8.

The following is one of what pops up:

 BUG: sleeping function called from invalid context at
include/linux/freezer.h:46
in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
no locks held by minissdpd/2166.
 irq event stamp: 2081
hardirqs last  enabled at (2080): [<c02f8dc8>] _raw_spin_unlock_irq+0x24/0x4c
hardirqs last disabled at (2081): [<c00090cc>] ret_fast_syscall+0xc/0x38
softirqs last  enabled at (0): [<c0016b38>] copy_process+0x3f8/0xfe8
softirqs last disabled at (0): [<  (null)>]   (null)
[<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
(do_signal+0x84/0x554)
[<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
(do_notify_resume+0x18/0x60)
[<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
(work_pending+0x24/0x28)


From u.kleine-koenig at pengutronix.de  Fri Aug 17 13:46:32 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 17 Aug 2012 19:46:32 +0200
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ6352dHG5ieN5fxvAno2HLq-5fVfCmU-HP9nEz_SaA4ew@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <20120817132629.GA2232@pengutronix.de>
 <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>
 <CADhrpJ6352dHG5ieN5fxvAno2HLq-5fVfCmU-HP9nEz_SaA4ew@mail.gmail.com>
Message-ID: <20120817174632.GD2232@pengutronix.de>

Hello,

On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
> > On 17 August 2012 13:26, Uwe Kleine-K?nig
> > <u.kleine-koenig at pengutronix.de> wrote:
> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
> >>> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
> >>> on my ix2-200
> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
> >>> and now even on 3.6 rc1
> >>> and the next dated today 17 august that when i use git for example:
> >>>
> >>> git clone git://git.videolan.org/x264
> >>>
> >>> my system just crash's / hangs and even through the serial port i get
> >>> no response.
> >>> This also happens when i try to access a web interface for example the
> >>> serviio java webui.
> >>>
> >>> The second issue i have noticed is that my raid 0 array hangs / pauses
> >>> when being mounted
> >>> at system startup. (for approximatly 30 seconds maybe more maybe less
> >>> im not certain).
> >>> But again on the 3.3.7 kernel there was no issue and no hang.
> >>>
> >>> If i return to 3.3.7 everything works fine with no other modifications
> >>> to the os or kernels.
> >>> I am using debian wheezy at the moment but also tried debian squeeze
> >>> so it does not
> >>> seem to be related to the specific linux version just the kernel.
> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
> >> be the obvious range to test.
> >>
> >> You can also try to enable the various debugging options like
> >>
> >>         CONFIG_DETECT_HUNG_TASK
> >>         CONFIG_PROVE_LOCKING
> >>         CONFIG_DEBUG_ATOMIC_SLEEP
> >>         CONFIG_MAGIC_SYSRQ
> >>
> >> or try https://lkml.org/lkml/2012/5/26/83.
> >>
> >> Best regards
> >> Uwe
> >>
> >> --
> >> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
> >> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> >
> > i enabled the options you said there and i see alot of the following
> > popping up while connected through serial:
> >
> >  BUG: sleeping function called from invalid context at
> > include/linux/freezer.h:46
> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180, name:
> > console-kit-dae
> > [  126.904566] no locks held by console-kit-dae/2180.
> > [  126.909378] irq event stamp: 27643
> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
> > _raw_spin_unlock_irqrestore+0x3c/0x5c
> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
> > ret_fast_syscall+0xc/0x38
> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
> > irq_exit+0x54/0xb8
> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
> > irq_exit+0x54/0xb8
> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
> > [<c000b414>] (do_signal+0x84/0x5c0)
> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from [<c000be0c>]
> > (do_notify_resume+0x18/0x60)
> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
> > [<c0009120>] (work_pending+0x24/0x28)
> >
> > there seems to be alot more of them when i have serviio upnp server running.
> 
> After a little testing with those config options enabled that you
> sujested iv found that the problem with git first appears in the 3.4.1
> kernel.
> For example:
> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264' successfully.
> 
> From 3.4.1 kernel on  I can not use 'git clone
> git://git.videolan.org/x264' the system hangs / crashes with no output
> at all.
> 
> the other issue the hang / stall while mounting my etx4 raid 0 is
> actualy much more recent than i remembered i have tested each kernel
> from 3.4.0 all the way to 3.4.9 with the config options enabled as
> sujested before and the stall first starts in kernel 3.4.8 and the
> following bug keeps popping up repeatedly until the raid is mounted
> and then anytime a disk is accessed it seems. I was certain it had
> been popping up before 3.4.8.
> 
> The following is one of what pops up:
> 
>  BUG: sleeping function called from invalid context at
> include/linux/freezer.h:46
> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
> no locks held by minissdpd/2166.
>  irq event stamp: 2081
> hardirqs last  enabled at (2080): [<c02f8dc8>] _raw_spin_unlock_irq+0x24/0x4c
> hardirqs last disabled at (2081): [<c00090cc>] ret_fast_syscall+0xc/0x38
> softirqs last  enabled at (0): [<c0016b38>] copy_process+0x3f8/0xfe8
> softirqs last disabled at (0): [<  (null)>]   (null)
> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
> (do_signal+0x84/0x554)
> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
> (do_notify_resume+0x18/0x60)
> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
> (work_pending+0x24/0x28)
I think this is an unrelated issue that I think is fixed in later
kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
Can you try a bisection, i.e.

	git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
	cd linus
	git remote add -f stable git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
	git bisect v3.4.1 v3.4

and test if the kernel that is checked out then results in a freeze.
Depending on the test result either do:

	git bisect good # i.e. problem doesn't occur

or

	git bisect bad # problem is reproducible

Repeat that until git points out the first bad commit and report that.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From alanbutty12 at gmail.com  Fri Aug 17 14:12:19 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 18:12:19 +0000
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ7YOapZU7zeAHQz8XfYhsJ0LL_OZ35bk0+4GJAKxG4ocw@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <20120817132629.GA2232@pengutronix.de>
 <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>
 <CADhrpJ6352dHG5ieN5fxvAno2HLq-5fVfCmU-HP9nEz_SaA4ew@mail.gmail.com>
 <20120817174632.GD2232@pengutronix.de>
 <CADhrpJ7YOapZU7zeAHQz8XfYhsJ0LL_OZ35bk0+4GJAKxG4ocw@mail.gmail.com>
Message-ID: <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>

From: Alan M Butler <alanbutty12 at gmail.com>
Date: 17 August 2012 18:09
Subject: Re: Issues with all kernels after 3.3.7
To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>


On 17 August 2012 17:46, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:
> Hello,
>
> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
>> >>> on my ix2-200
>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
>> >>> and now even on 3.6 rc1
>> >>> and the next dated today 17 august that when i use git for example:
>> >>>
>> >>> git clone git://git.videolan.org/x264
>> >>>
>> >>> my system just crash's / hangs and even through the serial port i get
>> >>> no response.
>> >>> This also happens when i try to access a web interface for example the
>> >>> serviio java webui.
>> >>>
>> >>> The second issue i have noticed is that my raid 0 array hangs / pauses
>> >>> when being mounted
>> >>> at system startup. (for approximatly 30 seconds maybe more maybe less
>> >>> im not certain).
>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>> >>>
>> >>> If i return to 3.3.7 everything works fine with no other modifications
>> >>> to the os or kernels.
>> >>> I am using debian wheezy at the moment but also tried debian squeeze
>> >>> so it does not
>> >>> seem to be related to the specific linux version just the kernel.
>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
>> >> be the obvious range to test.
>> >>
>> >> You can also try to enable the various debugging options like
>> >>
>> >>         CONFIG_DETECT_HUNG_TASK
>> >>         CONFIG_PROVE_LOCKING
>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>> >>         CONFIG_MAGIC_SYSRQ
>> >>
>> >> or try https://lkml.org/lkml/2012/5/26/83.
>> >>
>> >> Best regards
>> >> Uwe
>> >>
>> >> --
>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
>> >> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>> >
>> > i enabled the options you said there and i see alot of the following
>> > popping up while connected through serial:
>> >
>> >  BUG: sleeping function called from invalid context at
>> > include/linux/freezer.h:46
>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180, name:
>> > console-kit-dae
>> > [  126.904566] no locks held by console-kit-dae/2180.
>> > [  126.909378] irq event stamp: 27643
>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>> > ret_fast_syscall+0xc/0x38
>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>> > irq_exit+0x54/0xb8
>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>> > irq_exit+0x54/0xb8
>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>> > [<c000b414>] (do_signal+0x84/0x5c0)
>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from [<c000be0c>]
>> > (do_notify_resume+0x18/0x60)
>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>> > [<c0009120>] (work_pending+0x24/0x28)
>> >
>> > there seems to be alot more of them when i have serviio upnp server running.
>>
>> After a little testing with those config options enabled that you
>> sujested iv found that the problem with git first appears in the 3.4.1
>> kernel.
>> For example:
>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264' successfully.
>>
>> From 3.4.1 kernel on  I can not use 'git clone
>> git://git.videolan.org/x264' the system hangs / crashes with no output
>> at all.
>>
>> the other issue the hang / stall while mounting my etx4 raid 0 is
>> actualy much more recent than i remembered i have tested each kernel
>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>> sujested before and the stall first starts in kernel 3.4.8 and the
>> following bug keeps popping up repeatedly until the raid is mounted
>> and then anytime a disk is accessed it seems. I was certain it had
>> been popping up before 3.4.8.
>>
>> The following is one of what pops up:
>>
>>  BUG: sleeping function called from invalid context at
>> include/linux/freezer.h:46
>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>> no locks held by minissdpd/2166.
>>  irq event stamp: 2081
>> hardirqs last  enabled at (2080): [<c02f8dc8>] _raw_spin_unlock_irq+0x24/0x4c
>> hardirqs last disabled at (2081): [<c00090cc>] ret_fast_syscall+0xc/0x38
>> softirqs last  enabled at (0): [<c0016b38>] copy_process+0x3f8/0xfe8
>> softirqs last disabled at (0): [<  (null)>]   (null)
>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>> (do_signal+0x84/0x554)
>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>> (do_notify_resume+0x18/0x60)
>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>> (work_pending+0x24/0x28)
> I think this is an unrelated issue that I think is fixed in later
> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
> Can you try a bisection, i.e.
>
>         git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>         cd linus
>         git remote add -f stable git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
>         git bisect v3.4.1 v3.4
>
> and test if the kernel that is checked out then results in a freeze.
> Depending on the test result either do:
>
>         git bisect good # i.e. problem doesn't occur
>
> or
>
>         git bisect bad # problem is reproducible
>
> Repeat that until git points out the first bad commit and report that.
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

I dont think it has as i have recently been building the latest 3.6 rc
kernels while creating a patch for my nas and i had the same issue's
on them. Thats what prompted me to actualy come to the mailing list
with it. I have tried the 3.6-rc1 and the latest linux-next dated 17th
of august.


From nsekhar at ti.com  Fri Aug 17 14:13:44 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 17 Aug 2012 23:43:44 +0530
Subject: [PATCH 1/5] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <502E89D8.2090304@ti.com>

Hi Gururaja,

On 8/14/2012 6:12 PM, Hebbar, Gururaja wrote:
> Davinci McASP header & driver are shared by few OMAP platforms (like
> TI81xx, AM335x). Splitting asp header into Davinci platform specific
> header and Audio specific header helps to share them across platforms.
> 
> Audio specific defines is moved to to common
> <linux/platform_data/davinci_asp.h> so that the header can be
> accessed by all related platforms.
> 
> While here, correct the header usage (remove multiple header
> re-definitions and unused headers) and remove platform names from
> structures comments and enum
> 
> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> Acked-by: Vaibhav Bedia <vaibhav.bedia at ti.com>

This patch looks good to me. See a minor nit below.

Acked-by: Sekhar Nori <nsekhar at ti.com>

> diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
> new file mode 100644
> index 0000000..8fd5238
> --- /dev/null
> +++ b/arch/arm/mach-davinci/asp.h
> @@ -0,0 +1,49 @@
> +/*
> + * TI DaVinci Audio definitions
> + */
> +#ifndef __ASM_ARCH_DAVINCI_ASP_H
> +#define __ASM_ARCH_DAVINCI_ASP_H
> +
> +/* Bases of dm644x and dm355 register banks */
> +#define DAVINCI_ASP0_BASE	0x01E02000
> +#define DAVINCI_ASP1_BASE	0x01E04000
> +
> +/* Bases of dm365 register banks */
> +#define DAVINCI_DM365_ASP0_BASE	0x01D02000
> +
> +/* Bases of dm646x register banks */
> +#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
> +#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800

Can you remove usage of tabs after 'define'. I understand this is coming
from existing code.

Thanks,
Sekhar


From nico at fluxnic.net  Fri Aug 17 14:21:24 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 17 Aug 2012 14:21:24 -0400 (EDT)
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <201208171120.40740.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <alpine.LFD.2.02.1208161438110.1541@xanadu.home>
 <201208171120.40740.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208171407540.1541@xanadu.home>

On Fri, 17 Aug 2012, Arnd Bergmann wrote:

> On Thursday 16 August 2012, Nicolas Pitre wrote:
> > Some people will want to use bzip2 or whatever other decompressor du 
> > jour.  Maybe this shouldn't be gzip specific, or just presented as a 
> > possible option?
> 
> Good point. Whether this should be part of this document depends on
> what assumptions we make about the boot loader getting the image
> in the first place.
> 
> In the strict sense, we are documenting the interface between the boot
> loader and the kernel here, which already specifies that  the kernel
> must be uncompressed by the time we enter it. If the boot loader wants
> to add its own encryption or compression methods, or its own headers
> in front of the binary, the boot protocol isn't really impacted.

Right.  And someone else will insist on wrapping the kernel into a boot 
loader specific image format e.g. u-Boot.  If all those variations could 
be kept out of the kernel build that would be a good thing.

That means the kernel should be wrapped/compressed/scrambled at 
installation time, not at build time.  This way the kernel image remains 
universal and flexibility in its installation is possible.

> That said, I think it's a good idea to also specify what kind of 
> format we want to be used, e.g. a stripped ELF Image compressed with 
> one of gzip/bzip2/lzo/xz and with no other headers added, on a 
> vfat/ext4/btrfs formatted file system. There are probably a lot of 
> other things one might want to specify if we go down this route. Or we 
> could refer to the UEFI spec and mandate that the same format that 
> UEFI uses should be used here independent of what boot loader is used. 
> I think we can still allow other ways to get to the image for deeply 
> embedded systems, e.g. linking the kernel into the boot loader as a 
> blob on tightly constrained systems. For that case, we'd only specify 
> the interface between boot loader and kernel as described above.

I don't think we'll have to concern ourselves with tightly constrained 
systems that much on ARM64.


Nicolas


From swarren at wwwdotorg.org  Fri Aug 17 15:01:31 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 Aug 2012 13:01:31 -0600
Subject: [PATCH] mmc: tegra: convert to device tree support only
In-Reply-To: <1345187071-6619-1-git-send-email-josephl@nvidia.com>
References: <1345187071-6619-1-git-send-email-josephl@nvidia.com>
Message-ID: <502E950B.2010205@wwwdotorg.org>

On 08/17/2012 01:04 AM, Joseph Lo wrote:
> When compiling a kernel that supports only Tegra30 and not Tegra20,
> the SDHCI driver will fail to compile since the of_match_device() failure
> fallback code unconditinally references soc_data_tegra20, which is only
> compiled in when Tegra20 support is enabled.
> 
> In Kernel 3.7, both Tegra20 and Tegra30 will only support booting using
> device tree, Hence, there is never a need to fall back to using
> soc_data_tegra20 if of_mach_device() fails. Instead, make this case an
> error. This removes the reference to soc_data_tegra20, and hence solves
> the compile failure.

Tested-by: Stephen Warren <swarren at wwwdotorg.org>

(built and tested both Tegra20-only and Tegr30-only kernels with this
applied on top of next-20120816).


From w.sang at pengutronix.de  Fri Aug 17 15:05:37 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Fri, 17 Aug 2012 21:05:37 +0200
Subject: [PATCH 1/1 v4] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <CACRpkdb+6S5yYvVjrr2f+wubE43dzD3i=OVfWtM_U+HW_XZX1A@mail.gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120808131158.GD8227@gmail.com>
 <CACRpkdb+6S5yYvVjrr2f+wubE43dzD3i=OVfWtM_U+HW_XZX1A@mail.gmail.com>
Message-ID: <20120817190537.GA32339@pengutronix.de>

On Fri, Aug 17, 2012 at 05:02:32PM +0200, Linus Walleij wrote:
> On Wed, Aug 8, 2012 at 3:11 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > From: Lee Jones <lee.jones at linaro.org>
> > Date: Tue, 7 Aug 2012 12:27:24 +0100
> > Subject: [PATCH 1/1 v4] i2c/nomadik: Add default configuration into the Nomadik I2C driver
> 
> Wolfram are you taking this v4 patch into the i2c tree for the -rc:s?
> 
> Right now this is causing boot regressions so we need it badly...

I am collecting patches for rc3 this weekend.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From festevam at gmail.com  Fri Aug 17 15:08:47 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 17 Aug 2012 16:08:47 -0300
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120810210647.GG1451@pengutronix.de>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
Message-ID: <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>

On Fri, Aug 10, 2012 at 6:06 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:

> One clock is for the bus which must be turned on. The other is for the
> bitclock which we currently can ignore since we only support clock slave
> mode.
> On an i.MX5 ssi[123]_ipg_gate must be turned on by the ssi driver. From
> a quick look to the clock code it looks correct.

I tested audio playback on a mx51evk board last week using linux-next
and it worked fine (it has a sgtl5000).

I don't have any hardware with ac97 to try it.

Also, for the playback to work you need to install the SDMA firmware.

Regards,

Fabio Estevam


From swarren at wwwdotorg.org  Fri Aug 17 15:26:41 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 Aug 2012 13:26:41 -0600
Subject: [PATCH] ARM: tegra: clocks: separate tegra_clk_32k_ops from
 Tegra20 and Tegra30
In-Reply-To: <1345186281-3859-1-git-send-email-josephl@nvidia.com>
References: <1345186281-3859-1-git-send-email-josephl@nvidia.com>
Message-ID: <502E9AF1.2000701@wwwdotorg.org>

On 08/17/2012 12:51 AM, Joseph Lo wrote:
> Currently the tegra20 and tegra30 share the same symbol for
> tegra_clk_32k_ops. This will cause a compile error when building
> a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and
> modify tegra30_clk_32k_ops for tegra30.
> 
> Signed-off-by: Joseph Lo <josephl at nvidia.com>

Thanks, applied to Tegra's for-3.7/common-clk branch.



From swarren at wwwdotorg.org  Fri Aug 17 15:26:51 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 17 Aug 2012 13:26:51 -0600
Subject: [PATCH] ARM: tegra30: clocks: fix the wrong
 tegra_audio_sync_clk_ops name
In-Reply-To: <1345186450-4517-1-git-send-email-josephl@nvidia.com>
References: <1345186450-4517-1-git-send-email-josephl@nvidia.com>
Message-ID: <502E9AFB.3090205@wwwdotorg.org>

On 08/17/2012 12:54 AM, Joseph Lo wrote:
> It should use tegra30_audio_sync_clk_ops for tegra30. It will cause
> the tegra30 use the wrong audio_sync_clk_ops when build a kernel with
> a tegra20 and tegra30 both supported kernel. And building error when
> a tegra30-only kernel.

Thanks, applied to Tegra's for-3.7/common-clk branch.



From alanbutty12 at gmail.com  Fri Aug 17 15:37:08 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 20:37:08 +0100
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <20120817132629.GA2232@pengutronix.de>
 <CADhrpJ63XMer2zQ+wBQxGGLYwfU8hJ=ejDTwYktFtmE6OY+dPw@mail.gmail.com>
 <CADhrpJ6352dHG5ieN5fxvAno2HLq-5fVfCmU-HP9nEz_SaA4ew@mail.gmail.com>
 <20120817174632.GD2232@pengutronix.de>
 <CADhrpJ7YOapZU7zeAHQz8XfYhsJ0LL_OZ35bk0+4GJAKxG4ocw@mail.gmail.com>
 <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>
Message-ID: <CADhrpJ7=XooXLcU5_V9wkZAgwCJaLdUL4bfPUWbo-J_eVqovHQ@mail.gmail.com>

On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
> From: Alan M Butler <alanbutty12 at gmail.com>
> Date: 17 August 2012 18:09
> Subject: Re: Issues with all kernels after 3.3.7
> To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>
>
> On 17 August 2012 17:46, Uwe Kleine-K?nig
> <u.kleine-koenig at pengutronix.de> wrote:
>> Hello,
>>
>> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
>>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>>> > <u.kleine-koenig at pengutronix.de> wrote:
>>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5 series)
>>> >>> on my ix2-200
>>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4 =>3.4.7
>>> >>> and now even on 3.6 rc1
>>> >>> and the next dated today 17 august that when i use git for example:
>>> >>>
>>> >>> git clone git://git.videolan.org/x264
>>> >>>
>>> >>> my system just crash's / hangs and even through the serial port i get
>>> >>> no response.
>>> >>> This also happens when i try to access a web interface for example the
>>> >>> serviio java webui.
>>> >>>
>>> >>> The second issue i have noticed is that my raid 0 array hangs / pauses
>>> >>> when being mounted
>>> >>> at system startup. (for approximatly 30 seconds maybe more maybe less
>>> >>> im not certain).
>>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>>> >>>
>>> >>> If i return to 3.3.7 everything works fine with no other modifications
>>> >>> to the os or kernels.
>>> >>> I am using debian wheezy at the moment but also tried debian squeeze
>>> >>> so it does not
>>> >>> seem to be related to the specific linux version just the kernel.
>>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8 seems to
>>> >> be the obvious range to test.
>>> >>
>>> >> You can also try to enable the various debugging options like
>>> >>
>>> >>         CONFIG_DETECT_HUNG_TASK
>>> >>         CONFIG_PROVE_LOCKING
>>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>>> >>         CONFIG_MAGIC_SYSRQ
>>> >>
>>> >> or try https://lkml.org/lkml/2012/5/26/83.
>>> >>
>>> >> Best regards
>>> >> Uwe
>>> >>
>>> >> --
>>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
>>> >> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>>> >
>>> > i enabled the options you said there and i see alot of the following
>>> > popping up while connected through serial:
>>> >
>>> >  BUG: sleeping function called from invalid context at
>>> > include/linux/freezer.h:46
>>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180, name:
>>> > console-kit-dae
>>> > [  126.904566] no locks held by console-kit-dae/2180.
>>> > [  126.909378] irq event stamp: 27643
>>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>>> > ret_fast_syscall+0xc/0x38
>>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>>> > irq_exit+0x54/0xb8
>>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>>> > irq_exit+0x54/0xb8
>>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>>> > [<c000b414>] (do_signal+0x84/0x5c0)
>>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from [<c000be0c>]
>>> > (do_notify_resume+0x18/0x60)
>>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>>> > [<c0009120>] (work_pending+0x24/0x28)
>>> >
>>> > there seems to be alot more of them when i have serviio upnp server running.
>>>
>>> After a little testing with those config options enabled that you
>>> sujested iv found that the problem with git first appears in the 3.4.1
>>> kernel.
>>> For example:
>>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264' successfully.
>>>
>>> From 3.4.1 kernel on  I can not use 'git clone
>>> git://git.videolan.org/x264' the system hangs / crashes with no output
>>> at all.
>>>
>>> the other issue the hang / stall while mounting my etx4 raid 0 is
>>> actualy much more recent than i remembered i have tested each kernel
>>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>>> sujested before and the stall first starts in kernel 3.4.8 and the
>>> following bug keeps popping up repeatedly until the raid is mounted
>>> and then anytime a disk is accessed it seems. I was certain it had
>>> been popping up before 3.4.8.
>>>
>>> The following is one of what pops up:
>>>
>>>  BUG: sleeping function called from invalid context at
>>> include/linux/freezer.h:46
>>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>>> no locks held by minissdpd/2166.
>>>  irq event stamp: 2081
>>> hardirqs last  enabled at (2080): [<c02f8dc8>] _raw_spin_unlock_irq+0x24/0x4c
>>> hardirqs last disabled at (2081): [<c00090cc>] ret_fast_syscall+0xc/0x38
>>> softirqs last  enabled at (0): [<c0016b38>] copy_process+0x3f8/0xfe8
>>> softirqs last disabled at (0): [<  (null)>]   (null)
>>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>>> (do_signal+0x84/0x554)
>>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>>> (do_notify_resume+0x18/0x60)
>>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>>> (work_pending+0x24/0x28)
>> I think this is an unrelated issue that I think is fixed in later
>> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
>> Can you try a bisection, i.e.
>>
>>         git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>>         cd linus
>>         git remote add -f stable git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
>>         git bisect v3.4.1 v3.4
>>
>> and test if the kernel that is checked out then results in a freeze.
>> Depending on the test result either do:
>>
>>         git bisect good # i.e. problem doesn't occur
>>
>> or
>>
>>         git bisect bad # problem is reproducible
>>
>> Repeat that until git points out the first bad commit and report that.
>>
>> Best regards
>> Uwe
>>
>> --
>> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
>> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>
> I dont think it has as i have recently been building the latest 3.6 rc
> kernels while creating a patch for my nas and i had the same issue's
> on them. Thats what prompted me to actualy come to the mailing list
> with it. I have tried the 3.6-rc1 and the latest linux-next dated 17th
> of august.

Im not sure if this is the right commit as i dont know what way it
works but basically the very first commit caused the issue of me not
being able to use git and when i typed the git bisect bad it said
this:

ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad

Bisecting: 21 revisions left to test after this (roughly 5 steps)
[774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
during timeout


From tomasz.figa at gmail.com  Fri Aug 17 16:08:44 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 Aug 2012 22:08:44 +0200
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ7=XooXLcU5_V9wkZAgwCJaLdUL4bfPUWbo-J_eVqovHQ@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>
 <CADhrpJ7=XooXLcU5_V9wkZAgwCJaLdUL4bfPUWbo-J_eVqovHQ@mail.gmail.com>
Message-ID: <4345020.aIxQDhhJn6@flatron>

Hi Alan,

On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
> > From: Alan M Butler <alanbutty12 at gmail.com>
> > Date: 17 August 2012 18:09
> > Subject: Re: Issues with all kernels after 3.3.7
> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > 
> > 
> > On 17 August 2012 17:46, Uwe Kleine-K?nig
> > 
> > <u.kleine-koenig at pengutronix.de> wrote:
> >> Hello,
> >> 
> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
> >>> > 
> >>> > <u.kleine-koenig at pengutronix.de> wrote:
> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
> >>> >>> series)
> >>> >>> on my ix2-200
> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
> >>> >>> =>3.4.7
> >>> >>> and now even on 3.6 rc1
> >>> >>> and the next dated today 17 august that when i use git for
> >>> >>> example:
> >>> >>> 
> >>> >>> git clone git://git.videolan.org/x264
> >>> >>> 
> >>> >>> my system just crash's / hangs and even through the serial port i
> >>> >>> get
> >>> >>> no response.
> >>> >>> This also happens when i try to access a web interface for
> >>> >>> example the
> >>> >>> serviio java webui.
> >>> >>> 
> >>> >>> The second issue i have noticed is that my raid 0 array hangs /
> >>> >>> pauses
> >>> >>> when being mounted
> >>> >>> at system startup. (for approximatly 30 seconds maybe more maybe
> >>> >>> less
> >>> >>> im not certain).
> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
> >>> >>> 
> >>> >>> If i return to 3.3.7 everything works fine with no other
> >>> >>> modifications
> >>> >>> to the os or kernels.
> >>> >>> I am using debian wheezy at the moment but also tried debian
> >>> >>> squeeze
> >>> >>> so it does not
> >>> >>> seem to be related to the specific linux version just the kernel.
> >>> >> 
> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
> >>> >> seems to
> >>> >> be the obvious range to test.
> >>> >> 
> >>> >> You can also try to enable the various debugging options like
> >>> >> 
> >>> >>         CONFIG_DETECT_HUNG_TASK
> >>> >>         CONFIG_PROVE_LOCKING
> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
> >>> >>         CONFIG_MAGIC_SYSRQ
> >>> >> 
> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
> >>> >> 
> >>> >> Best regards
> >>> >> Uwe
> >>> >> 
> >>> >> --
> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig     
> >>> >>       | Industrial Linux Solutions                 |
> >>> >> http://www.pengutronix.de/  |>>> > 
> >>> > i enabled the options you said there and i see alot of the
> >>> > following
> >>> > 
> >>> > popping up while connected through serial:
> >>> >  BUG: sleeping function called from invalid context at
> >>> > 
> >>> > include/linux/freezer.h:46
> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
> >>> > name:
> >>> > console-kit-dae
> >>> > [  126.904566] no locks held by console-kit-dae/2180.
> >>> > [  126.909378] irq event stamp: 27643
> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
> >>> > ret_fast_syscall+0xc/0x38
> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
> >>> > irq_exit+0x54/0xb8
> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
> >>> > irq_exit+0x54/0xb8
> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
> >>> > [<c000be0c>]
> >>> > (do_notify_resume+0x18/0x60)
> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
> >>> > [<c0009120>] (work_pending+0x24/0x28)
> >>> > 
> >>> > there seems to be alot more of them when i have serviio upnp server
> >>> > running.>>> 
> >>> After a little testing with those config options enabled that you
> >>> sujested iv found that the problem with git first appears in the
> >>> 3.4.1
> >>> kernel.
> >>> For example:
> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
> >>> successfully.
> >>> 
> >>> From 3.4.1 kernel on  I can not use 'git clone
> >>> git://git.videolan.org/x264' the system hangs / crashes with no
> >>> output
> >>> at all.
> >>> 
> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
> >>> actualy much more recent than i remembered i have tested each kernel
> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
> >>> sujested before and the stall first starts in kernel 3.4.8 and the
> >>> following bug keeps popping up repeatedly until the raid is mounted
> >>> and then anytime a disk is accessed it seems. I was certain it had
> >>> been popping up before 3.4.8.
> >>> 
> >>> The following is one of what pops up:
> >>>  BUG: sleeping function called from invalid context at
> >>> 
> >>> include/linux/freezer.h:46
> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
> >>> no locks held by minissdpd/2166.
> >>> 
> >>>  irq event stamp: 2081
> >>> 
> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled at
> >>> (0): [<  (null)>]   (null)
> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
> >>> (do_signal+0x84/0x554)
> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
> >>> (do_notify_resume+0x18/0x60)
> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
> >>> (work_pending+0x24/0x28)
> >> 
> >> I think this is an unrelated issue that I think is fixed in later
> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
> >> Can you try a bisection, i.e.
> >> 
> >>         git clone
> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.
> >>         git cd linus
> >>         git remote add -f stable
> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-st
> >>         able.git git bisect v3.4.1 v3.4
> >> 
> >> and test if the kernel that is checked out then results in a freeze.
> >> 
> >> Depending on the test result either do:
> >>         git bisect good # i.e. problem doesn't occur
> >> 
> >> or
> >> 
> >>         git bisect bad # problem is reproducible
> >> 
> >> Repeat that until git points out the first bad commit and report that.
> >> 
> >> Best regards
> >> Uwe
> >> 
> >> --
> >> Pengutronix e.K.                           | Uwe Kleine-K?nig         
> >>   | Industrial Linux Solutions                 |
> >> http://www.pengutronix.de/  |> 
> > I dont think it has as i have recently been building the latest 3.6 rc
> > kernels while creating a patch for my nas and i had the same issue's
> > on them. Thats what prompted me to actualy come to the mailing list
> > with it. I have tried the 3.6-rc1 and the latest linux-next dated 17th
> > of august.
> 
> Im not sure if this is the right commit as i dont know what way it
> works but basically the very first commit caused the issue of me not
> being able to use git and when i typed the git bisect bad it said
> this:
> 
> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
> 
> Bisecting: 21 revisions left to test after this (roughly 5 steps)
> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
> during timeout

After calling git bisect bad it checks out files from a revision between 
the one currently checked and the one marked as good (imagine binary 
search).

You have to compile and test resulting kernels and tell git whether they're 
good or bad until it tells you that it found the problematic commit.

Best regards,
Tomasz Figa

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From alanbutty12 at gmail.com  Fri Aug 17 16:19:08 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 21:19:08 +0100
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>
 <CADhrpJ7=XooXLcU5_V9wkZAgwCJaLdUL4bfPUWbo-J_eVqovHQ@mail.gmail.com>
 <4345020.aIxQDhhJn6@flatron>
 <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
Message-ID: <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>

On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Hi Alan,
>
> On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
>> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> > From: Alan M Butler <alanbutty12 at gmail.com>
>> > Date: 17 August 2012 18:09
>> > Subject: Re: Issues with all kernels after 3.3.7
>> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>> >
>> >
>> > On 17 August 2012 17:46, Uwe Kleine-K?nig
>> >
>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >> Hello,
>> >>
>> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>> >>> >
>> >>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
>> >>> >>> series)
>> >>> >>> on my ix2-200
>> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
>> >>> >>> =>3.4.7
>> >>> >>> and now even on 3.6 rc1
>> >>> >>> and the next dated today 17 august that when i use git for
>> >>> >>> example:
>> >>> >>>
>> >>> >>> git clone git://git.videolan.org/x264
>> >>> >>>
>> >>> >>> my system just crash's / hangs and even through the serial port i
>> >>> >>> get
>> >>> >>> no response.
>> >>> >>> This also happens when i try to access a web interface for
>> >>> >>> example the
>> >>> >>> serviio java webui.
>> >>> >>>
>> >>> >>> The second issue i have noticed is that my raid 0 array hangs /
>> >>> >>> pauses
>> >>> >>> when being mounted
>> >>> >>> at system startup. (for approximatly 30 seconds maybe more maybe
>> >>> >>> less
>> >>> >>> im not certain).
>> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>> >>> >>>
>> >>> >>> If i return to 3.3.7 everything works fine with no other
>> >>> >>> modifications
>> >>> >>> to the os or kernels.
>> >>> >>> I am using debian wheezy at the moment but also tried debian
>> >>> >>> squeeze
>> >>> >>> so it does not
>> >>> >>> seem to be related to the specific linux version just the kernel.
>> >>> >>
>> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
>> >>> >> seems to
>> >>> >> be the obvious range to test.
>> >>> >>
>> >>> >> You can also try to enable the various debugging options like
>> >>> >>
>> >>> >>         CONFIG_DETECT_HUNG_TASK
>> >>> >>         CONFIG_PROVE_LOCKING
>> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>> >>> >>         CONFIG_MAGIC_SYSRQ
>> >>> >>
>> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
>> >>> >>
>> >>> >> Best regards
>> >>> >> Uwe
>> >>> >>
>> >>> >> --
>> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >>> >>       | Industrial Linux Solutions                 |
>> >>> >> http://www.pengutronix.de/  |>>> >
>> >>> > i enabled the options you said there and i see alot of the
>> >>> > following
>> >>> >
>> >>> > popping up while connected through serial:
>> >>> >  BUG: sleeping function called from invalid context at
>> >>> >
>> >>> > include/linux/freezer.h:46
>> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
>> >>> > name:
>> >>> > console-kit-dae
>> >>> > [  126.904566] no locks held by console-kit-dae/2180.
>> >>> > [  126.909378] irq event stamp: 27643
>> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>> >>> > ret_fast_syscall+0xc/0x38
>> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>> >>> > irq_exit+0x54/0xb8
>> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>> >>> > irq_exit+0x54/0xb8
>> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
>> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
>> >>> > [<c000be0c>]
>> >>> > (do_notify_resume+0x18/0x60)
>> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>> >>> > [<c0009120>] (work_pending+0x24/0x28)
>> >>> >
>> >>> > there seems to be alot more of them when i have serviio upnp server
>> >>> > running.>>>
>> >>> After a little testing with those config options enabled that you
>> >>> sujested iv found that the problem with git first appears in the
>> >>> 3.4.1
>> >>> kernel.
>> >>> For example:
>> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
>> >>> successfully.
>> >>>
>> >>> From 3.4.1 kernel on  I can not use 'git clone
>> >>> git://git.videolan.org/x264' the system hangs / crashes with no
>> >>> output
>> >>> at all.
>> >>>
>> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
>> >>> actualy much more recent than i remembered i have tested each kernel
>> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>> >>> sujested before and the stall first starts in kernel 3.4.8 and the
>> >>> following bug keeps popping up repeatedly until the raid is mounted
>> >>> and then anytime a disk is accessed it seems. I was certain it had
>> >>> been popping up before 3.4.8.
>> >>>
>> >>> The following is one of what pops up:
>> >>>  BUG: sleeping function called from invalid context at
>> >>>
>> >>> include/linux/freezer.h:46
>> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>> >>> no locks held by minissdpd/2166.
>> >>>
>> >>>  irq event stamp: 2081
>> >>>
>> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
>> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
>> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
>> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled at
>> >>> (0): [<  (null)>]   (null)
>> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>> >>> (do_signal+0x84/0x554)
>> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>> >>> (do_notify_resume+0x18/0x60)
>> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>> >>> (work_pending+0x24/0x28)
>> >>
>> >> I think this is an unrelated issue that I think is fixed in later
>> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
>> >> Can you try a bisection, i.e.
>> >>
>> >>         git clone
>> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.
>> >>         git cd linus
>> >>         git remote add -f stable
>> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-st
>> >>         able.git git bisect v3.4.1 v3.4
>> >>
>> >> and test if the kernel that is checked out then results in a freeze.
>> >>
>> >> Depending on the test result either do:
>> >>         git bisect good # i.e. problem doesn't occur
>> >>
>> >> or
>> >>
>> >>         git bisect bad # problem is reproducible
>> >>
>> >> Repeat that until git points out the first bad commit and report that.
>> >>
>> >> Best regards
>> >> Uwe
>> >>
>> >> --
>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >>   | Industrial Linux Solutions                 |
>> >> http://www.pengutronix.de/  |>
>> > I dont think it has as i have recently been building the latest 3.6 rc
>> > kernels while creating a patch for my nas and i had the same issue's
>> > on them. Thats what prompted me to actualy come to the mailing list
>> > with it. I have tried the 3.6-rc1 and the latest linux-next dated 17th
>> > of august.
>>
>> Im not sure if this is the right commit as i dont know what way it
>> works but basically the very first commit caused the issue of me not
>> being able to use git and when i typed the git bisect bad it said
>> this:
>>
>> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
>>
>> Bisecting: 21 revisions left to test after this (roughly 5 steps)
>> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
>> during timeout
>
> After calling git bisect bad it checks out files from a revision between
> the one currently checked and the one marked as good (imagine binary
> search).
>
> You have to compile and test resulting kernels and tell git whether they're
> good or bad until it tells you that it found the problematic commit.
>
> Best regards,
> Tomasz Figa
>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

It said something about doing it 5 more times or such. and if im
understanding what your saying basicaly i have to build it 5 more
times then it will tell me the commit that was actualy bad so the one
i said there is not the problematic one?


From tomasz.figa at gmail.com  Fri Aug 17 16:23:25 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 17 Aug 2012 22:23:25 +0200
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
 <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>
Message-ID: <2094430.QvfuTg7dJ7@flatron>

On Friday 17 of August 2012 21:19:08 Alan M Butler wrote:
> On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> > Hi Alan,
> > 
> > On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
> >> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
> >> > From: Alan M Butler <alanbutty12 at gmail.com>
> >> > Date: 17 August 2012 18:09
> >> > Subject: Re: Issues with all kernels after 3.3.7
> >> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> >> > 
> >> > 
> >> > On 17 August 2012 17:46, Uwe Kleine-K?nig
> >> > 
> >> > <u.kleine-koenig at pengutronix.de> wrote:
> >> >> Hello,
> >> >> 
> >> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
> >> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> 
wrote:
> >> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
> >> >>> > 
> >> >>> > <u.kleine-koenig at pengutronix.de> wrote:
> >> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
> >> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
> >> >>> >>> series)
> >> >>> >>> on my ix2-200
> >> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
> >> >>> >>> =>3.4.7
> >> >>> >>> and now even on 3.6 rc1
> >> >>> >>> and the next dated today 17 august that when i use git for
> >> >>> >>> example:
> >> >>> >>> 
> >> >>> >>> git clone git://git.videolan.org/x264
> >> >>> >>> 
> >> >>> >>> my system just crash's / hangs and even through the serial
> >> >>> >>> port i
> >> >>> >>> get
> >> >>> >>> no response.
> >> >>> >>> This also happens when i try to access a web interface for
> >> >>> >>> example the
> >> >>> >>> serviio java webui.
> >> >>> >>> 
> >> >>> >>> The second issue i have noticed is that my raid 0 array hangs
> >> >>> >>> /
> >> >>> >>> pauses
> >> >>> >>> when being mounted
> >> >>> >>> at system startup. (for approximatly 30 seconds maybe more
> >> >>> >>> maybe
> >> >>> >>> less
> >> >>> >>> im not certain).
> >> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
> >> >>> >>> 
> >> >>> >>> If i return to 3.3.7 everything works fine with no other
> >> >>> >>> modifications
> >> >>> >>> to the os or kernels.
> >> >>> >>> I am using debian wheezy at the moment but also tried debian
> >> >>> >>> squeeze
> >> >>> >>> so it does not
> >> >>> >>> seem to be related to the specific linux version just the
> >> >>> >>> kernel.
> >> >>> >> 
> >> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
> >> >>> >> seems to
> >> >>> >> be the obvious range to test.
> >> >>> >> 
> >> >>> >> You can also try to enable the various debugging options like
> >> >>> >> 
> >> >>> >>         CONFIG_DETECT_HUNG_TASK
> >> >>> >>         CONFIG_PROVE_LOCKING
> >> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
> >> >>> >>         CONFIG_MAGIC_SYSRQ
> >> >>> >> 
> >> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
> >> >>> >> 
> >> >>> >> Best regards
> >> >>> >> Uwe
> >> >>> >> 
> >> >>> >> --
> >> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
> >> >>> >> 
> >> >>> >>       | Industrial Linux Solutions                 |
> >> >>> >> 
> >> >>> >> http://www.pengutronix.de/  |>>> >
> >> >>> > 
> >> >>> > i enabled the options you said there and i see alot of the
> >> >>> > following
> >> >>> > 
> >> >>> > popping up while connected through serial:
> >> >>> >  BUG: sleeping function called from invalid context at
> >> >>> > 
> >> >>> > include/linux/freezer.h:46
> >> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
> >> >>> > name:
> >> >>> > console-kit-dae
> >> >>> > [  126.904566] no locks held by console-kit-dae/2180.
> >> >>> > [  126.909378] irq event stamp: 27643
> >> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
> >> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
> >> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
> >> >>> > ret_fast_syscall+0xc/0x38
> >> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
> >> >>> > irq_exit+0x54/0xb8
> >> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
> >> >>> > irq_exit+0x54/0xb8
> >> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
> >> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
> >> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
> >> >>> > [<c000be0c>]
> >> >>> > (do_notify_resume+0x18/0x60)
> >> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
> >> >>> > [<c0009120>] (work_pending+0x24/0x28)
> >> >>> > 
> >> >>> > there seems to be alot more of them when i have serviio upnp
> >> >>> > server
> >> >>> > running.>>>
> >> >>> 
> >> >>> After a little testing with those config options enabled that you
> >> >>> sujested iv found that the problem with git first appears in the
> >> >>> 3.4.1
> >> >>> kernel.
> >> >>> For example:
> >> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
> >> >>> successfully.
> >> >>> 
> >> >>> From 3.4.1 kernel on  I can not use 'git clone
> >> >>> git://git.videolan.org/x264' the system hangs / crashes with no
> >> >>> output
> >> >>> at all.
> >> >>> 
> >> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
> >> >>> actualy much more recent than i remembered i have tested each
> >> >>> kernel
> >> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
> >> >>> sujested before and the stall first starts in kernel 3.4.8 and the
> >> >>> following bug keeps popping up repeatedly until the raid is
> >> >>> mounted
> >> >>> and then anytime a disk is accessed it seems. I was certain it had
> >> >>> been popping up before 3.4.8.
> >> >>> 
> >> >>> The following is one of what pops up:
> >> >>>  BUG: sleeping function called from invalid context at
> >> >>> 
> >> >>> include/linux/freezer.h:46
> >> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
> >> >>> no locks held by minissdpd/2166.
> >> >>> 
> >> >>>  irq event stamp: 2081
> >> >>> 
> >> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
> >> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
> >> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
> >> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled
> >> >>> at
> >> >>> (0): [<  (null)>]   (null)
> >> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
> >> >>> (do_signal+0x84/0x554)
> >> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
> >> >>> (do_notify_resume+0x18/0x60)
> >> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
> >> >>> (work_pending+0x24/0x28)
> >> >> 
> >> >> I think this is an unrelated issue that I think is fixed in later
> >> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further
> >> >> testing.
> >> >> Can you try a bisection, i.e.
> >> >> 
> >> >>         git clone
> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linu
> >> >>         x.
> >> >>         git cd linus
> >> >>         git remote add -f stable
> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-
> >> >>         st
> >> >>         able.git git bisect v3.4.1 v3.4
> >> >> 
> >> >> and test if the kernel that is checked out then results in a
> >> >> freeze.
> >> >> 
> >> >> Depending on the test result either do:
> >> >>         git bisect good # i.e. problem doesn't occur
> >> >> 
> >> >> or
> >> >> 
> >> >>         git bisect bad # problem is reproducible
> >> >> 
> >> >> Repeat that until git points out the first bad commit and report
> >> >> that.
> >> >> 
> >> >> Best regards
> >> >> Uwe
> >> >> 
> >> >> --
> >> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
> >> >> 
> >> >>   | Industrial Linux Solutions                 |
> >> >> 
> >> >> http://www.pengutronix.de/  |>
> >> > 
> >> > I dont think it has as i have recently been building the latest 3.6
> >> > rc
> >> > kernels while creating a patch for my nas and i had the same issue's
> >> > on them. Thats what prompted me to actualy come to the mailing list
> >> > with it. I have tried the 3.6-rc1 and the latest linux-next dated
> >> > 17th
> >> > of august.
> >> 
> >> Im not sure if this is the right commit as i dont know what way it
> >> works but basically the very first commit caused the issue of me not
> >> being able to use git and when i typed the git bisect bad it said
> >> this:
> >> 
> >> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
> >> 
> >> Bisecting: 21 revisions left to test after this (roughly 5 steps)
> >> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
> >> during timeout
> > 
> > After calling git bisect bad it checks out files from a revision
> > between
> > the one currently checked and the one marked as good (imagine binary
> > search).
> > 
> > You have to compile and test resulting kernels and tell git whether
> > they're good or bad until it tells you that it found the problematic
> > commit.
> > 
> > Best regards,
> > Tomasz Figa
> > 
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> It said something about doing it 5 more times or such. and if im
> understanding what your saying basicaly i have to build it 5 more
> times then it will tell me the commit that was actualy bad so the one
> i said there is not the problematic one?
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Yes, that's it.

P.S. Next time please reply to the mailing list, not to individual posters. 
I have forwarded your message to the list this time.

Best regards,
Tomasz Figa



From linux at arm.linux.org.uk  Fri Aug 17 17:03:49 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 17 Aug 2012 22:03:49 +0100
Subject: Discontiguous memory and cacheflush
In-Reply-To: <502E6908.4070408@arm.com>
References: <1822556972.575011.1345068509111.JavaMail.root@mozilla.com>
 <502E6908.4070408@arm.com>
Message-ID: <20120817210349.GO18957@n2100.arm.linux.org.uk>

On Fri, Aug 17, 2012 at 04:53:44PM +0100, Jonathan Austin wrote:
> (cacheflush.h:257)
> #define flush_cache_user_range(start,end) \
>         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
> 
> Does that have a bearing on what you're doing?

I'm going to do some digging over the weekend, and work out why that
was added.  I don't think it used to be the case that it flushed an
entire page.


From alanbutty12 at gmail.com  Fri Aug 17 17:04:37 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 22:04:37 +0100
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <2094430.QvfuTg7dJ7@flatron>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
 <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>
 <2094430.QvfuTg7dJ7@flatron>
Message-ID: <CADhrpJ4=VdsEat7TWYTWx=HGUKqQNAcnV5zK5aQAzFvcN89pqw@mail.gmail.com>

On 17 August 2012 21:23, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> On Friday 17 of August 2012 21:19:08 Alan M Butler wrote:
>> On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> > Hi Alan,
>> >
>> > On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
>> >> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> >> > From: Alan M Butler <alanbutty12 at gmail.com>
>> >> > Date: 17 August 2012 18:09
>> >> > Subject: Re: Issues with all kernels after 3.3.7
>> >> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>> >> >
>> >> >
>> >> > On 17 August 2012 17:46, Uwe Kleine-K?nig
>> >> >
>> >> > <u.kleine-koenig at pengutronix.de> wrote:
>> >> >> Hello,
>> >> >>
>> >> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>> >> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com>
> wrote:
>> >> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>> >> >>> >
>> >> >>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> >> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
>> >> >>> >>> series)
>> >> >>> >>> on my ix2-200
>> >> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
>> >> >>> >>> =>3.4.7
>> >> >>> >>> and now even on 3.6 rc1
>> >> >>> >>> and the next dated today 17 august that when i use git for
>> >> >>> >>> example:
>> >> >>> >>>
>> >> >>> >>> git clone git://git.videolan.org/x264
>> >> >>> >>>
>> >> >>> >>> my system just crash's / hangs and even through the serial
>> >> >>> >>> port i
>> >> >>> >>> get
>> >> >>> >>> no response.
>> >> >>> >>> This also happens when i try to access a web interface for
>> >> >>> >>> example the
>> >> >>> >>> serviio java webui.
>> >> >>> >>>
>> >> >>> >>> The second issue i have noticed is that my raid 0 array hangs
>> >> >>> >>> /
>> >> >>> >>> pauses
>> >> >>> >>> when being mounted
>> >> >>> >>> at system startup. (for approximatly 30 seconds maybe more
>> >> >>> >>> maybe
>> >> >>> >>> less
>> >> >>> >>> im not certain).
>> >> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>> >> >>> >>>
>> >> >>> >>> If i return to 3.3.7 everything works fine with no other
>> >> >>> >>> modifications
>> >> >>> >>> to the os or kernels.
>> >> >>> >>> I am using debian wheezy at the moment but also tried debian
>> >> >>> >>> squeeze
>> >> >>> >>> so it does not
>> >> >>> >>> seem to be related to the specific linux version just the
>> >> >>> >>> kernel.
>> >> >>> >>
>> >> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
>> >> >>> >> seems to
>> >> >>> >> be the obvious range to test.
>> >> >>> >>
>> >> >>> >> You can also try to enable the various debugging options like
>> >> >>> >>
>> >> >>> >>         CONFIG_DETECT_HUNG_TASK
>> >> >>> >>         CONFIG_PROVE_LOCKING
>> >> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>> >> >>> >>         CONFIG_MAGIC_SYSRQ
>> >> >>> >>
>> >> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
>> >> >>> >>
>> >> >>> >> Best regards
>> >> >>> >> Uwe
>> >> >>> >>
>> >> >>> >> --
>> >> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >> >>> >>
>> >> >>> >>       | Industrial Linux Solutions                 |
>> >> >>> >>
>> >> >>> >> http://www.pengutronix.de/  |>>> >
>> >> >>> >
>> >> >>> > i enabled the options you said there and i see alot of the
>> >> >>> > following
>> >> >>> >
>> >> >>> > popping up while connected through serial:
>> >> >>> >  BUG: sleeping function called from invalid context at
>> >> >>> >
>> >> >>> > include/linux/freezer.h:46
>> >> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
>> >> >>> > name:
>> >> >>> > console-kit-dae
>> >> >>> > [  126.904566] no locks held by console-kit-dae/2180.
>> >> >>> > [  126.909378] irq event stamp: 27643
>> >> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>> >> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>> >> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>> >> >>> > ret_fast_syscall+0xc/0x38
>> >> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>> >> >>> > irq_exit+0x54/0xb8
>> >> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>> >> >>> > irq_exit+0x54/0xb8
>> >> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>> >> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
>> >> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
>> >> >>> > [<c000be0c>]
>> >> >>> > (do_notify_resume+0x18/0x60)
>> >> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>> >> >>> > [<c0009120>] (work_pending+0x24/0x28)
>> >> >>> >
>> >> >>> > there seems to be alot more of them when i have serviio upnp
>> >> >>> > server
>> >> >>> > running.>>>
>> >> >>>
>> >> >>> After a little testing with those config options enabled that you
>> >> >>> sujested iv found that the problem with git first appears in the
>> >> >>> 3.4.1
>> >> >>> kernel.
>> >> >>> For example:
>> >> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
>> >> >>> successfully.
>> >> >>>
>> >> >>> From 3.4.1 kernel on  I can not use 'git clone
>> >> >>> git://git.videolan.org/x264' the system hangs / crashes with no
>> >> >>> output
>> >> >>> at all.
>> >> >>>
>> >> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
>> >> >>> actualy much more recent than i remembered i have tested each
>> >> >>> kernel
>> >> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>> >> >>> sujested before and the stall first starts in kernel 3.4.8 and the
>> >> >>> following bug keeps popping up repeatedly until the raid is
>> >> >>> mounted
>> >> >>> and then anytime a disk is accessed it seems. I was certain it had
>> >> >>> been popping up before 3.4.8.
>> >> >>>
>> >> >>> The following is one of what pops up:
>> >> >>>  BUG: sleeping function called from invalid context at
>> >> >>>
>> >> >>> include/linux/freezer.h:46
>> >> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>> >> >>> no locks held by minissdpd/2166.
>> >> >>>
>> >> >>>  irq event stamp: 2081
>> >> >>>
>> >> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
>> >> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
>> >> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
>> >> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled
>> >> >>> at
>> >> >>> (0): [<  (null)>]   (null)
>> >> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>> >> >>> (do_signal+0x84/0x554)
>> >> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>> >> >>> (do_notify_resume+0x18/0x60)
>> >> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>> >> >>> (work_pending+0x24/0x28)
>> >> >>
>> >> >> I think this is an unrelated issue that I think is fixed in later
>> >> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further
>> >> >> testing.
>> >> >> Can you try a bisection, i.e.
>> >> >>
>> >> >>         git clone
>> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linu
>> >> >>         x.
>> >> >>         git cd linus
>> >> >>         git remote add -f stable
>> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-
>> >> >>         st
>> >> >>         able.git git bisect v3.4.1 v3.4
>> >> >>
>> >> >> and test if the kernel that is checked out then results in a
>> >> >> freeze.
>> >> >>
>> >> >> Depending on the test result either do:
>> >> >>         git bisect good # i.e. problem doesn't occur
>> >> >>
>> >> >> or
>> >> >>
>> >> >>         git bisect bad # problem is reproducible
>> >> >>
>> >> >> Repeat that until git points out the first bad commit and report
>> >> >> that.
>> >> >>
>> >> >> Best regards
>> >> >> Uwe
>> >> >>
>> >> >> --
>> >> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >> >>
>> >> >>   | Industrial Linux Solutions                 |
>> >> >>
>> >> >> http://www.pengutronix.de/  |>
>> >> >
>> >> > I dont think it has as i have recently been building the latest 3.6
>> >> > rc
>> >> > kernels while creating a patch for my nas and i had the same issue's
>> >> > on them. Thats what prompted me to actualy come to the mailing list
>> >> > with it. I have tried the 3.6-rc1 and the latest linux-next dated
>> >> > 17th
>> >> > of august.
>> >>
>> >> Im not sure if this is the right commit as i dont know what way it
>> >> works but basically the very first commit caused the issue of me not
>> >> being able to use git and when i typed the git bisect bad it said
>> >> this:
>> >>
>> >> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
>> >>
>> >> Bisecting: 21 revisions left to test after this (roughly 5 steps)
>> >> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
>> >> during timeout
>> >
>> > After calling git bisect bad it checks out files from a revision
>> > between
>> > the one currently checked and the one marked as good (imagine binary
>> > search).
>> >
>> > You have to compile and test resulting kernels and tell git whether
>> > they're good or bad until it tells you that it found the problematic
>> > commit.
>> >
>> > Best regards,
>> > Tomasz Figa
>> >
>> >> _______________________________________________
>> >> linux-arm-kernel mailing list
>> >> linux-arm-kernel at lists.infradead.org
>> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>> It said something about doing it 5 more times or such. and if im
>> understanding what your saying basicaly i have to build it 5 more
>> times then it will tell me the commit that was actualy bad so the one
>> i said there is not the problematic one?
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Yes, that's it.
>
> P.S. Next time please reply to the mailing list, not to individual posters.
> I have forwarded your message to the list this time.
>
> Best regards,
> Tomasz Figa
>

this is odd i went back to the 3.4 kernel (which was working) from my
earlier testing and which i can wrote to the nand on the device now
has the same issue with the git clone? I tried the command just to
make sure the kernel was working and nothing the nas just stopped like
usual and after 3 rebuild of the kernel its still the same run the
command and freeze.


From broonie at opensource.wolfsonmicro.com  Fri Aug 17 17:55:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 22:55:39 +0100
Subject: [PATCH 00/10 V3] MXS SPI driver
In-Reply-To: <1344007575-11448-1-git-send-email-marex@denx.de>
References: <1344007575-11448-1-git-send-email-marex@denx.de>
Message-ID: <20120817215538.GD18871@opensource.wolfsonmicro.com>

On Fri, Aug 03, 2012 at 05:26:05PM +0200, Marek Vasut wrote:
> This patchset adds SPI master support for Freescale i.MX233/i.MX28.
> This is rebased on top of next-20120713. Please consider applying,
> bugs shall now be squashed during the previous two review rounds.

I applied all these except patch 10 (the pinctrl data) which Shawn
wasn't happy with and which seems like it'd make sense to merge via the
arch tree anyway since it's likely to avoid merge conflicts.
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From alanbutty12 at gmail.com  Fri Aug 17 18:19:07 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 23:19:07 +0100
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CADhrpJ4=VdsEat7TWYTWx=HGUKqQNAcnV5zK5aQAzFvcN89pqw@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
 <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>
 <2094430.QvfuTg7dJ7@flatron>
 <CADhrpJ4=VdsEat7TWYTWx=HGUKqQNAcnV5zK5aQAzFvcN89pqw@mail.gmail.com>
Message-ID: <CADhrpJ44UJOj+tXk++FPsano7=fghv31hiwstK9bSkti2+aGWA@mail.gmail.com>

On 17 August 2012 22:04, Alan M Butler <alanbutty12 at gmail.com> wrote:
> On 17 August 2012 21:23, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> On Friday 17 of August 2012 21:19:08 Alan M Butler wrote:
>>> On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>>> > Hi Alan,
>>> >
>>> > On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
>>> >> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
>>> >> > From: Alan M Butler <alanbutty12 at gmail.com>
>>> >> > Date: 17 August 2012 18:09
>>> >> > Subject: Re: Issues with all kernels after 3.3.7
>>> >> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>>> >> >
>>> >> >
>>> >> > On 17 August 2012 17:46, Uwe Kleine-K?nig
>>> >> >
>>> >> > <u.kleine-koenig at pengutronix.de> wrote:
>>> >> >> Hello,
>>> >> >>
>>> >> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>>> >> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com>
>> wrote:
>>> >> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>>> >> >>> >
>>> >> >>> > <u.kleine-koenig at pengutronix.de> wrote:
>>> >> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>>> >> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
>>> >> >>> >>> series)
>>> >> >>> >>> on my ix2-200
>>> >> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
>>> >> >>> >>> =>3.4.7
>>> >> >>> >>> and now even on 3.6 rc1
>>> >> >>> >>> and the next dated today 17 august that when i use git for
>>> >> >>> >>> example:
>>> >> >>> >>>
>>> >> >>> >>> git clone git://git.videolan.org/x264
>>> >> >>> >>>
>>> >> >>> >>> my system just crash's / hangs and even through the serial
>>> >> >>> >>> port i
>>> >> >>> >>> get
>>> >> >>> >>> no response.
>>> >> >>> >>> This also happens when i try to access a web interface for
>>> >> >>> >>> example the
>>> >> >>> >>> serviio java webui.
>>> >> >>> >>>
>>> >> >>> >>> The second issue i have noticed is that my raid 0 array hangs
>>> >> >>> >>> /
>>> >> >>> >>> pauses
>>> >> >>> >>> when being mounted
>>> >> >>> >>> at system startup. (for approximatly 30 seconds maybe more
>>> >> >>> >>> maybe
>>> >> >>> >>> less
>>> >> >>> >>> im not certain).
>>> >> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>>> >> >>> >>>
>>> >> >>> >>> If i return to 3.3.7 everything works fine with no other
>>> >> >>> >>> modifications
>>> >> >>> >>> to the os or kernels.
>>> >> >>> >>> I am using debian wheezy at the moment but also tried debian
>>> >> >>> >>> squeeze
>>> >> >>> >>> so it does not
>>> >> >>> >>> seem to be related to the specific linux version just the
>>> >> >>> >>> kernel.
>>> >> >>> >>
>>> >> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
>>> >> >>> >> seems to
>>> >> >>> >> be the obvious range to test.
>>> >> >>> >>
>>> >> >>> >> You can also try to enable the various debugging options like
>>> >> >>> >>
>>> >> >>> >>         CONFIG_DETECT_HUNG_TASK
>>> >> >>> >>         CONFIG_PROVE_LOCKING
>>> >> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>>> >> >>> >>         CONFIG_MAGIC_SYSRQ
>>> >> >>> >>
>>> >> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
>>> >> >>> >>
>>> >> >>> >> Best regards
>>> >> >>> >> Uwe
>>> >> >>> >>
>>> >> >>> >> --
>>> >> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>>> >> >>> >>
>>> >> >>> >>       | Industrial Linux Solutions                 |
>>> >> >>> >>
>>> >> >>> >> http://www.pengutronix.de/  |>>> >
>>> >> >>> >
>>> >> >>> > i enabled the options you said there and i see alot of the
>>> >> >>> > following
>>> >> >>> >
>>> >> >>> > popping up while connected through serial:
>>> >> >>> >  BUG: sleeping function called from invalid context at
>>> >> >>> >
>>> >> >>> > include/linux/freezer.h:46
>>> >> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
>>> >> >>> > name:
>>> >> >>> > console-kit-dae
>>> >> >>> > [  126.904566] no locks held by console-kit-dae/2180.
>>> >> >>> > [  126.909378] irq event stamp: 27643
>>> >> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>>> >> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>>> >> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>>> >> >>> > ret_fast_syscall+0xc/0x38
>>> >> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>>> >> >>> > irq_exit+0x54/0xb8
>>> >> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>>> >> >>> > irq_exit+0x54/0xb8
>>> >> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>>> >> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
>>> >> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
>>> >> >>> > [<c000be0c>]
>>> >> >>> > (do_notify_resume+0x18/0x60)
>>> >> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>>> >> >>> > [<c0009120>] (work_pending+0x24/0x28)
>>> >> >>> >
>>> >> >>> > there seems to be alot more of them when i have serviio upnp
>>> >> >>> > server
>>> >> >>> > running.>>>
>>> >> >>>
>>> >> >>> After a little testing with those config options enabled that you
>>> >> >>> sujested iv found that the problem with git first appears in the
>>> >> >>> 3.4.1
>>> >> >>> kernel.
>>> >> >>> For example:
>>> >> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
>>> >> >>> successfully.
>>> >> >>>
>>> >> >>> From 3.4.1 kernel on  I can not use 'git clone
>>> >> >>> git://git.videolan.org/x264' the system hangs / crashes with no
>>> >> >>> output
>>> >> >>> at all.
>>> >> >>>
>>> >> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
>>> >> >>> actualy much more recent than i remembered i have tested each
>>> >> >>> kernel
>>> >> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>>> >> >>> sujested before and the stall first starts in kernel 3.4.8 and the
>>> >> >>> following bug keeps popping up repeatedly until the raid is
>>> >> >>> mounted
>>> >> >>> and then anytime a disk is accessed it seems. I was certain it had
>>> >> >>> been popping up before 3.4.8.
>>> >> >>>
>>> >> >>> The following is one of what pops up:
>>> >> >>>  BUG: sleeping function called from invalid context at
>>> >> >>>
>>> >> >>> include/linux/freezer.h:46
>>> >> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>>> >> >>> no locks held by minissdpd/2166.
>>> >> >>>
>>> >> >>>  irq event stamp: 2081
>>> >> >>>
>>> >> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
>>> >> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
>>> >> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
>>> >> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled
>>> >> >>> at
>>> >> >>> (0): [<  (null)>]   (null)
>>> >> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>>> >> >>> (do_signal+0x84/0x554)
>>> >> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>>> >> >>> (do_notify_resume+0x18/0x60)
>>> >> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>>> >> >>> (work_pending+0x24/0x28)
>>> >> >>
>>> >> >> I think this is an unrelated issue that I think is fixed in later
>>> >> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further
>>> >> >> testing.
>>> >> >> Can you try a bisection, i.e.
>>> >> >>
>>> >> >>         git clone
>>> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linu
>>> >> >>         x.
>>> >> >>         git cd linus
>>> >> >>         git remote add -f stable
>>> >> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-
>>> >> >>         st
>>> >> >>         able.git git bisect v3.4.1 v3.4
>>> >> >>
>>> >> >> and test if the kernel that is checked out then results in a
>>> >> >> freeze.
>>> >> >>
>>> >> >> Depending on the test result either do:
>>> >> >>         git bisect good # i.e. problem doesn't occur
>>> >> >>
>>> >> >> or
>>> >> >>
>>> >> >>         git bisect bad # problem is reproducible
>>> >> >>
>>> >> >> Repeat that until git points out the first bad commit and report
>>> >> >> that.
>>> >> >>
>>> >> >> Best regards
>>> >> >> Uwe
>>> >> >>
>>> >> >> --
>>> >> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>>> >> >>
>>> >> >>   | Industrial Linux Solutions                 |
>>> >> >>
>>> >> >> http://www.pengutronix.de/  |>
>>> >> >
>>> >> > I dont think it has as i have recently been building the latest 3.6
>>> >> > rc
>>> >> > kernels while creating a patch for my nas and i had the same issue's
>>> >> > on them. Thats what prompted me to actualy come to the mailing list
>>> >> > with it. I have tried the 3.6-rc1 and the latest linux-next dated
>>> >> > 17th
>>> >> > of august.
>>> >>
>>> >> Im not sure if this is the right commit as i dont know what way it
>>> >> works but basically the very first commit caused the issue of me not
>>> >> being able to use git and when i typed the git bisect bad it said
>>> >> this:
>>> >>
>>> >> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
>>> >>
>>> >> Bisecting: 21 revisions left to test after this (roughly 5 steps)
>>> >> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
>>> >> during timeout
>>> >
>>> > After calling git bisect bad it checks out files from a revision
>>> > between
>>> > the one currently checked and the one marked as good (imagine binary
>>> > search).
>>> >
>>> > You have to compile and test resulting kernels and tell git whether
>>> > they're good or bad until it tells you that it found the problematic
>>> > commit.
>>> >
>>> > Best regards,
>>> > Tomasz Figa
>>> >
>>> >> _______________________________________________
>>> >> linux-arm-kernel mailing list
>>> >> linux-arm-kernel at lists.infradead.org
>>> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>> It said something about doing it 5 more times or such. and if im
>>> understanding what your saying basicaly i have to build it 5 more
>>> times then it will tell me the commit that was actualy bad so the one
>>> i said there is not the problematic one?
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>> Yes, that's it.
>>
>> P.S. Next time please reply to the mailing list, not to individual posters.
>> I have forwarded your message to the list this time.
>>
>> Best regards,
>> Tomasz Figa
>>
>
> this is odd i went back to the 3.4 kernel (which was working) from my
> earlier testing and which i can wrote to the nand on the device now
> has the same issue with the git clone? I tried the command just to
> make sure the kernel was working and nothing the nas just stopped like
> usual and after 3 rebuild of the kernel its still the same run the
> command and freeze.

I think it seems that there is something bigger than the kernel
causing the git problem
i just decided out of curiosity to recompile a fresh 3.3.7 kernel
which has been working
perfectly and now git clone hangs the nas after being issued so
perhaps its the compiler
or OS that im compileing the kernels on perhaps something has gone wrong there.

incase anyone wants to know im using ubuntu 11.10 in a virtual box vm. with
the codesourcery arm toolchain dated 2012-03.


From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:27:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:27:38 +0100
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
Message-ID: <20120817222738.GH18871@opensource.wolfsonmicro.com>

On Fri, Aug 17, 2012 at 04:08:47PM -0300, Fabio Estevam wrote:

> Also, for the playback to work you need to install the SDMA firmware.

This is deadlocking during boot, I'm getting nowhere near trying
playback.
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From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:31:24 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:31:24 +0100
Subject: [PATCH 3/5] ASoC: Davinci: pcm: Add device tree bindings
In-Reply-To: <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120817223122.GA21445@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 06:12:03PM +0530, Hebbar, Gururaja wrote:
> Device tree support for Davinci/OMAP2+ pcm driver.

This looks like it's a device which maps a shared DMA controller in the
SoC core into ASoC rather than actual hardware.  Such devices are
usually instantiated automatically from the DAI rather than being
represented in the device tree since they are a Linux internal thing
really - the Tegra and Freescale drivers provide examples of how this
sort of thing can be done.
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From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:33:58 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:33:58 +0100
Subject: [PATCH 1/5] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120817223358.GI18871@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 06:12:01PM +0530, Hebbar, Gururaja wrote:
> Davinci McASP header & driver are shared by few OMAP platforms (like
> TI81xx, AM335x). Splitting asp header into Davinci platform specific
> header and Audio specific header helps to share them across platforms.

This doesn't apply against v3.6-rc2, I suspect there's overlapping
changes in arch/arm.  I was just going to apply it on a separate branch
to allow cross-tree merge if there's overlap with architecture work.
Can you please check and resend?
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From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:41:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:41:32 +0100
Subject: [PATCH 2/5] ASoC: Davinci: McASP: add device tree support for
 McASP
In-Reply-To: <1344948125-5649-3-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-3-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120817224131.GJ18871@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 06:12:02PM +0530, Hebbar, Gururaja wrote:

> +- op-mode : I2S/DIT ops mode.

This would normally be part of the machine binding since it needs to be
applied to both ends of the link.  When adding it could you come up with
a generic binding for this in terms of the current ASoC DAI paremeters
please?  That way we'll be able to have other machine drivers be
consistent with this one.

> +- tdm-slots : Slots for TDM operation.

This would normally also be a machine driver thing though it's less
normal to need to configure this on both ends.
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From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:43:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:43:28 +0100
Subject: [PATCH 4/5] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1344948125-5649-5-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-5-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120817224327.GK18871@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 06:12:04PM +0530, Hebbar, Gururaja wrote:

> +- ti,codec-clock : The Codec Clock from the board

I think this is the clock rate?  Please specify it more specifically.

> +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> +"<evm ops required, evm_ops or evm_spdif_ops>";

Please be more specific as to what these actually do - consider the user
who is reading the bindings with a view to implementing them for their
board, or writing drivers for another OS.
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From broonie at opensource.wolfsonmicro.com  Fri Aug 17 18:45:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 17 Aug 2012 23:45:13 +0100
Subject: [PATCH 5/5] ASoC: tlv320aic3x: Add device tree bindings
In-Reply-To: <1344948125-5649-6-git-send-email-gururaja.hebbar@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-6-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120817224512.GL18871@opensource.wolfsonmicro.com>

On Tue, Aug 14, 2012 at 06:12:05PM +0530, Hebbar, Gururaja wrote:

> +- gpio-reset - <int> -  gpio pin number used for codec reset

This should be a standard DT GPIO reference by phandle like:

	gpio = <&gpio1 16 0>;

There's quite a few examples in tree.

Otherwise this looks good.
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From festevam at gmail.com  Fri Aug 17 19:35:49 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 17 Aug 2012 20:35:49 -0300
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120817222738.GH18871@opensource.wolfsonmicro.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
Message-ID: <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>

On Fri, Aug 17, 2012 at 7:27 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Fri, Aug 17, 2012 at 04:08:47PM -0300, Fabio Estevam wrote:
>
>> Also, for the playback to work you need to install the SDMA firmware.
>
> This is deadlocking during boot, I'm getting nowhere near trying
> playback.

Are you running a dt or non-dt kernel? In case of a dt kernel, can you
share the dts file?


From alanbutty12 at gmail.com  Fri Aug 17 20:10:44 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Sat, 18 Aug 2012 00:10:44 +0000
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <CA+Ln22HB_=r0FbSR9Z8Y0mkuBmTW8_MHsD_B=_+h=9W2BkMR7Q@mail.gmail.com>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>
 <CADhrpJ6LsBXvJiOkOhHNibvazHY0ymREoZ4c2ztQR-RCKD50Mg@mail.gmail.com>
 <2094430.QvfuTg7dJ7@flatron>
 <CADhrpJ4=VdsEat7TWYTWx=HGUKqQNAcnV5zK5aQAzFvcN89pqw@mail.gmail.com>
 <CADhrpJ44UJOj+tXk++FPsano7=fghv31hiwstK9bSkti2+aGWA@mail.gmail.com>
 <CA+Ln22HB_=r0FbSR9Z8Y0mkuBmTW8_MHsD_B=_+h=9W2BkMR7Q@mail.gmail.com>
Message-ID: <CADhrpJ6bFYxga99x76H9YO8L+WwfUUdMZBBx2VubbuWFgZEqxQ@mail.gmail.com>

On 17 August 2012 23:57, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Your last two replies were again addressed just to me, not the mailing list.
> Please resend them correctly.
>
> 18 sie 2012 00:22, "Alan M Butler" <alanbutty12 at gmail.com> napisa?(a):
>
>> On 17 August 2012 22:04, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> > On 17 August 2012 21:23, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> >> On Friday 17 of August 2012 21:19:08 Alan M Butler wrote:
>> >>> On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
>> >>> > Hi Alan,
>> >>> >
>> >>> > On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
>> >>> >> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com>
>> >>> >> wrote:
>> >>> >> > From: Alan M Butler <alanbutty12 at gmail.com>
>> >>> >> > Date: 17 August 2012 18:09
>> >>> >> > Subject: Re: Issues with all kernels after 3.3.7
>> >>> >> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>> >>> >> >
>> >>> >> >
>> >>> >> > On 17 August 2012 17:46, Uwe Kleine-K?nig
>> >>> >> >
>> >>> >> > <u.kleine-koenig at pengutronix.de> wrote:
>> >>> >> >> Hello,
>> >>> >> >>
>> >>> >> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>> >>> >> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com>
>> >> wrote:
>> >>> >> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>> >>> >> >>> >
>> >>> >> >>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >>> >> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> >>> >> >>> >>> I have been trying all kernels after 3.3.7 (except for the
>> >>> >> >>> >>> 3.5
>> >>> >> >>> >>> series)
>> >>> >> >>> >>> on my ix2-200
>> >>> >> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2,
>> >>> >> >>> >>> 3.4.4
>> >>> >> >>> >>> =>3.4.7
>> >>> >> >>> >>> and now even on 3.6 rc1
>> >>> >> >>> >>> and the next dated today 17 august that when i use git for
>> >>> >> >>> >>> example:
>> >>> >> >>> >>>
>> >>> >> >>> >>> git clone git://git.videolan.org/x264
>> >>> >> >>> >>>
>> >>> >> >>> >>> my system just crash's / hangs and even through the serial
>> >>> >> >>> >>> port i
>> >>> >> >>> >>> get
>> >>> >> >>> >>> no response.
>> >>> >> >>> >>> This also happens when i try to access a web interface for
>> >>> >> >>> >>> example the
>> >>> >> >>> >>> serviio java webui.
>> >>> >> >>> >>>
>> >>> >> >>> >>> The second issue i have noticed is that my raid 0 array
>> >>> >> >>> >>> hangs
>> >>> >> >>> >>> /
>> >>> >> >>> >>> pauses
>> >>> >> >>> >>> when being mounted
>> >>> >> >>> >>> at system startup. (for approximatly 30 seconds maybe more
>> >>> >> >>> >>> maybe
>> >>> >> >>> >>> less
>> >>> >> >>> >>> im not certain).
>> >>> >> >>> >>> But again on the 3.3.7 kernel there was no issue and no
>> >>> >> >>> >>> hang.
>> >>> >> >>> >>>
>> >>> >> >>> >>> If i return to 3.3.7 everything works fine with no other
>> >>> >> >>> >>> modifications
>> >>> >> >>> >>> to the os or kernels.
>> >>> >> >>> >>> I am using debian wheezy at the moment but also tried
>> >>> >> >>> >>> debian
>> >>> >> >>> >>> squeeze
>> >>> >> >>> >>> so it does not
>> >>> >> >>> >>> seem to be related to the specific linux version just the
>> >>> >> >>> >>> kernel.
>> >>> >> >>> >>
>> >>> >> >>> >> Can you bisect your problem? Doing that between 3.3.7 and
>> >>> >> >>> >> 3.3.8
>> >>> >> >>> >> seems to
>> >>> >> >>> >> be the obvious range to test.
>> >>> >> >>> >>
>> >>> >> >>> >> You can also try to enable the various debugging options
>> >>> >> >>> >> like
>> >>> >> >>> >>
>> >>> >> >>> >>         CONFIG_DETECT_HUNG_TASK
>> >>> >> >>> >>         CONFIG_PROVE_LOCKING
>> >>> >> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>> >>> >> >>> >>         CONFIG_MAGIC_SYSRQ
>> >>> >> >>> >>
>> >>> >> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
>> >>> >> >>> >>
>> >>> >> >>> >> Best regards
>> >>> >> >>> >> Uwe
>> >>> >> >>> >>
>> >>> >> >>> >> --
>> >>> >> >>> >> Pengutronix e.K.                           | Uwe
>> >>> >> >>> >> Kleine-K?nig
>> >>> >> >>> >>
>> >>> >> >>> >>       | Industrial Linux Solutions                 |
>> >>> >> >>> >>
>> >>> >> >>> >> http://www.pengutronix.de/  |>>> >
>> >>> >> >>> >
>> >>> >> >>> > i enabled the options you said there and i see alot of the
>> >>> >> >>> > following
>> >>> >> >>> >
>> >>> >> >>> > popping up while connected through serial:
>> >>> >> >>> >  BUG: sleeping function called from invalid context at
>> >>> >> >>> >
>> >>> >> >>> > include/linux/freezer.h:46
>> >>> >> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid:
>> >>> >> >>> > 2180,
>> >>> >> >>> > name:
>> >>> >> >>> > console-kit-dae
>> >>> >> >>> > [  126.904566] no locks held by console-kit-dae/2180.
>> >>> >> >>> > [  126.909378] irq event stamp: 27643
>> >>> >> >>> > [  126.912797] hardirqs last  enabled at (27642):
>> >>> >> >>> > [<c03781ac>]
>> >>> >> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>> >>> >> >>> > [  126.921735] hardirqs last disabled at (27643):
>> >>> >> >>> > [<c00090cc>]
>> >>> >> >>> > ret_fast_syscall+0xc/0x38
>> >>> >> >>> > [  126.929618] softirqs last  enabled at (25565):
>> >>> >> >>> > [<c001bc20>]
>> >>> >> >>> > irq_exit+0x54/0xb8
>> >>> >> >>> > [  126.936890] softirqs last disabled at (25558):
>> >>> >> >>> > [<c001bc20>]
>> >>> >> >>> > irq_exit+0x54/0xb8
>> >>> >> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>> >>> >> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
>> >>> >> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
>> >>> >> >>> > [<c000be0c>]
>> >>> >> >>> > (do_notify_resume+0x18/0x60)
>> >>> >> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>> >>> >> >>> > [<c0009120>] (work_pending+0x24/0x28)
>> >>> >> >>> >
>> >>> >> >>> > there seems to be alot more of them when i have serviio upnp
>> >>> >> >>> > server
>> >>> >> >>> > running.>>>
>> >>> >> >>>
>> >>> >> >>> After a little testing with those config options enabled that
>> >>> >> >>> you
>> >>> >> >>> sujested iv found that the problem with git first appears in
>> >>> >> >>> the
>> >>> >> >>> 3.4.1
>> >>> >> >>> kernel.
>> >>> >> >>> For example:
>> >>> >> >>> in 3.4.0 kernel i can use 'git clone
>> >>> >> >>> git://git.videolan.org/x264'
>> >>> >> >>> successfully.
>> >>> >> >>>
>> >>> >> >>> From 3.4.1 kernel on  I can not use 'git clone
>> >>> >> >>> git://git.videolan.org/x264' the system hangs / crashes with no
>> >>> >> >>> output
>> >>> >> >>> at all.
>> >>> >> >>>
>> >>> >> >>> the other issue the hang / stall while mounting my etx4 raid 0
>> >>> >> >>> is
>> >>> >> >>> actualy much more recent than i remembered i have tested each
>> >>> >> >>> kernel
>> >>> >> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled
>> >>> >> >>> as
>> >>> >> >>> sujested before and the stall first starts in kernel 3.4.8 and
>> >>> >> >>> the
>> >>> >> >>> following bug keeps popping up repeatedly until the raid is
>> >>> >> >>> mounted
>> >>> >> >>> and then anytime a disk is accessed it seems. I was certain it
>> >>> >> >>> had
>> >>> >> >>> been popping up before 3.4.8.
>> >>> >> >>>
>> >>> >> >>> The following is one of what pops up:
>> >>> >> >>>  BUG: sleeping function called from invalid context at
>> >>> >> >>>
>> >>> >> >>> include/linux/freezer.h:46
>> >>> >> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name:
>> >>> >> >>> minissdpd
>> >>> >> >>> no locks held by minissdpd/2166.
>> >>> >> >>>
>> >>> >> >>>  irq event stamp: 2081
>> >>> >> >>>
>> >>> >> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
>> >>> >> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at
>> >>> >> >>> (2081):
>> >>> >> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled
>> >>> >> >>> at
>> >>> >> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last
>> >>> >> >>> disabled
>> >>> >> >>> at
>> >>> >> >>> (0): [<  (null)>]   (null)
>> >>> >> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>> >>> >> >>> (do_signal+0x84/0x554)
>> >>> >> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>> >>> >> >>> (do_notify_resume+0x18/0x60)
>> >>> >> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>> >>> >> >>> (work_pending+0x24/0x28)
>> >>> >> >>
>> >>> >> >> I think this is an unrelated issue that I think is fixed in
>> >>> >> >> later
>> >>> >> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further
>> >>> >> >> testing.
>> >>> >> >> Can you try a bisection, i.e.
>> >>> >> >>
>> >>> >> >>         git clone
>> >>> >> >>
>> >>> >> >> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linu
>> >>> >> >>         x.
>> >>> >> >>         git cd linus
>> >>> >> >>         git remote add -f stable
>> >>> >> >>
>> >>> >> >> git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-
>> >>> >> >>         st
>> >>> >> >>         able.git git bisect v3.4.1 v3.4
>> >>> >> >>
>> >>> >> >> and test if the kernel that is checked out then results in a
>> >>> >> >> freeze.
>> >>> >> >>
>> >>> >> >> Depending on the test result either do:
>> >>> >> >>         git bisect good # i.e. problem doesn't occur
>> >>> >> >>
>> >>> >> >> or
>> >>> >> >>
>> >>> >> >>         git bisect bad # problem is reproducible
>> >>> >> >>
>> >>> >> >> Repeat that until git points out the first bad commit and report
>> >>> >> >> that.
>> >>> >> >>
>> >>> >> >> Best regards
>> >>> >> >> Uwe
>> >>> >> >>
>> >>> >> >> --
>> >>> >> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >>> >> >>
>> >>> >> >>   | Industrial Linux Solutions                 |
>> >>> >> >>
>> >>> >> >> http://www.pengutronix.de/  |>
>> >>> >> >
>> >>> >> > I dont think it has as i have recently been building the latest
>> >>> >> > 3.6
>> >>> >> > rc
>> >>> >> > kernels while creating a patch for my nas and i had the same
>> >>> >> > issue's
>> >>> >> > on them. Thats what prompted me to actualy come to the mailing
>> >>> >> > list
>> >>> >> > with it. I have tried the 3.6-rc1 and the latest linux-next dated
>> >>> >> > 17th
>> >>> >> > of august.
>> >>> >>
>> >>> >> Im not sure if this is the right commit as i dont know what way it
>> >>> >> works but basically the very first commit caused the issue of me
>> >>> >> not
>> >>> >> being able to use git and when i typed the git bisect bad it said
>> >>> >> this:
>> >>> >>
>> >>> >> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
>> >>> >>
>> >>> >> Bisecting: 21 revisions left to test after this (roughly 5 steps)
>> >>> >> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
>> >>> >> during timeout
>> >>> >
>> >>> > After calling git bisect bad it checks out files from a revision
>> >>> > between
>> >>> > the one currently checked and the one marked as good (imagine binary
>> >>> > search).
>> >>> >
>> >>> > You have to compile and test resulting kernels and tell git whether
>> >>> > they're good or bad until it tells you that it found the problematic
>> >>> > commit.
>> >>> >
>> >>> > Best regards,
>> >>> > Tomasz Figa
>> >>> >
>> >>> >> _______________________________________________
>> >>> >> linux-arm-kernel mailing list
>> >>> >> linux-arm-kernel at lists.infradead.org
>> >>> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >>>
>> >>> It said something about doing it 5 more times or such. and if im
>> >>> understanding what your saying basicaly i have to build it 5 more
>> >>> times then it will tell me the commit that was actualy bad so the one
>> >>> i said there is not the problematic one?
>> >>>
>> >>> _______________________________________________
>> >>> linux-arm-kernel mailing list
>> >>> linux-arm-kernel at lists.infradead.org
>> >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >>
>> >> Yes, that's it.
>> >>
>> >> P.S. Next time please reply to the mailing list, not to individual
>> >> posters.
>> >> I have forwarded your message to the list this time.
>> >>
>> >> Best regards,
>> >> Tomasz Figa
>> >>
>> >
this is odd i went back to the 3.4 kernel (which was working) from my
earlier testing and which i can wrote to the nand on the device now
has the same issue with the git clone? I tried the command just to
make sure the kernel was working and nothing the nas just stopped like
usual and after 3 rebuild of the kernel its still the same run the
command and freeze.

I think it seems that there is something bigger than the kernel
causing the git problem
i just decided out of curiosity to recompile a fresh 3.3.7 kernel
which has been working perfectly and now git clone hangs the nas after
being issued so
perhaps its the compiler or OS that im compileing the kernels on
perhaps something has gone wrong there.
incase anyone wants to know im using ubuntu 11.10 in a virtual box
vm.with the codesourcery arm toolchain dated 2012-03.

and im sorry Tomasz but the last 2 messages arrording to mt gmail
anyway were sent to the mailing list and not to you so i do not know
how they went to you.


From tony at atomide.com  Sat Aug 18 02:08:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 17 Aug 2012 23:08:10 -0700
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <502E4F2B.6060403@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120817130723.GZ11011@atomide.com> <502E43BC.30708@bitmer.com>
 <502E4F2B.6060403@ti.com>
Message-ID: <20120818060810.GH11011@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120817 07:03]:
> On 08/17/2012 04:14 PM, Jarkko Nikula wrote:
> > On 08/17/2012 04:07 PM, Tony Lindgren wrote:
> >> * Peter Ujfalusi <peter.ujfalusi at ti.com> [120816 06:41]:
> >>> On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
> >>> the FIFO for the audio stack.
> >> Is this the case also for 2420? I thought some only had a FIFO at
> >> one port?
> >>
> > IRCC (I don't have specs), nope. Only 2430 (as noted by Peter) and
> > onwards have FIFO.
> > 
> > But that's true that FIFO sizes differ between the ports. E.g. only
> > ports 2 and 3 have 1024+128 deep FIFOs in OMAP3.
> > 
> 
> OMAP2420 McBSP does not have FIFO (the IP is closer to OMAP1 McBSP).
> OMAP2430, OMAP4, OMAP5 has 128 word long FIFO on all McBSP ports.
> On OMAP3: McBSP2 have 1024+256 (1280) word FIFO the rest of the ports have 128
> long FIFO.

Thanks, is this patch still correct so it does not try to enable FIFO
for 2420?

Regards,

Tony


From chf.fritz at googlemail.com  Sat Aug 18 02:31:28 2012
From: chf.fritz at googlemail.com (Christoph Fritz)
Date: Sat, 18 Aug 2012 08:31:28 +0200
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
 <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>
Message-ID: <1345271488.3694.1.camel@lovely>

On Fri, 2012-08-17 at 20:35 -0300, Fabio Estevam wrote:
> On Fri, Aug 17, 2012 at 7:27 PM, Mark Brown
> <broonie at opensource.wolfsonmicro.com> wrote:
> > On Fri, Aug 17, 2012 at 04:08:47PM -0300, Fabio Estevam wrote:
> >
> >> Also, for the playback to work you need to install the SDMA firmware.
> >
> > This is deadlocking during boot, I'm getting nowhere near trying
> > playback.
> 
> Are you running a dt or non-dt kernel? In case of a dt kernel, can you
> share the dts file?

I suppose Mark means an i.MX35 not an i.MX51.



From LW at KARO-electronics.de  Sat Aug 18 02:43:04 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Sat, 18 Aug 2012 08:43:04 +0200
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20120817061439.GF24242@S2101-09.ap.freescale.net>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
 <20120815141606.GA2457@S2101-09.ap.freescale.net>
 <20120815133221.ca88d4ba.akpm@linux-foundation.org>
 <20524.43620.36859.792122@ipc1.ka-ro>
 <20120817061439.GF24242@S2101-09.ap.freescale.net>
Message-ID: <20527.14712.202172.863404@ipc1.ka-ro>

Hi,

Shawn Guo writes:
> On Thu, Aug 16, 2012 at 10:08:04AM +0200, Lothar Wa?mann wrote:
> > Why not read the register once more in case of a timeout, which
> > would guarantee to have a current view of the register contents no
> > matter how long the process may have been descheduled before:
> > 
> > [...]
> > static int snvs_rtc_enable_done(int enable, void __iomem *addr)
> > {
> > 	u32 lpcr = readl(addr + SNVS_LPCR);
> > 
> > 	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
> > }
> > [...]
> > 	while (1) {
> > 		if (svns_rtc_enable_done(enable, data->ioaddr))
> > 			break;
> > 
> > 		if (time_after(jiffies, timeout)) {
> > 			if (!svns_rtc_enable_done(enable, data->ioaddr))
> > 				return -ETIMEDOUT;
> > 		}
> > 	}
> > 
> I'm fine with this solution.  Can you send a formal patch for this?
> Then we will have two incremental patches (I already sent the fixed
> times loop one) for Andrew to choose one.
> 
What should I base this patch on?


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From shawn.guo at linaro.org  Sat Aug 18 03:03:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 18 Aug 2012 15:03:54 +0800
Subject: [rtc-linux] [PATCH v3] rtc: snvs: add Freescale rtc-snvs driver
In-Reply-To: <20527.14712.202172.863404@ipc1.ka-ro>
References: <1342164663-31351-1-git-send-email-shawn.guo@linaro.org>
 <20120814170300.8f97afcf.akpm@linux-foundation.org>
 <20120815141606.GA2457@S2101-09.ap.freescale.net>
 <20120815133221.ca88d4ba.akpm@linux-foundation.org>
 <20524.43620.36859.792122@ipc1.ka-ro>
 <20120817061439.GF24242@S2101-09.ap.freescale.net>
 <20527.14712.202172.863404@ipc1.ka-ro>
Message-ID: <20120818070352.GG24242@S2101-09.ap.freescale.net>

On Sat, Aug 18, 2012 at 08:43:04AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> Shawn Guo writes:
> > On Thu, Aug 16, 2012 at 10:08:04AM +0200, Lothar Wa?mann wrote:
> > > Why not read the register once more in case of a timeout, which
> > > would guarantee to have a current view of the register contents no
> > > matter how long the process may have been descheduled before:
> > > 
> > > [...]
> > > static int snvs_rtc_enable_done(int enable, void __iomem *addr)
> > > {
> > > 	u32 lpcr = readl(addr + SNVS_LPCR);
> > > 
> > > 	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
> > > }
> > > [...]
> > > 	while (1) {
> > > 		if (svns_rtc_enable_done(enable, data->ioaddr))
> > > 			break;
> > > 
> > > 		if (time_after(jiffies, timeout)) {
> > > 			if (!svns_rtc_enable_done(enable, data->ioaddr))
> > > 				return -ETIMEDOUT;
> > > 		}
> > > 	}
> > > 
> > I'm fine with this solution.  Can you send a formal patch for this?
> > Then we will have two incremental patches (I already sent the fixed
> > times loop one) for Andrew to choose one.
> > 
> What should I base this patch on?
> 
v3.6-rc1 with "[PATCH v3] rtc: snvs: add Freescale rtc-snvs driver"
applied.

-- 
Regards,
Shawn


From u.kleine-koenig at pengutronix.de  Sat Aug 18 03:42:16 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sat, 18 Aug 2012 09:42:16 +0200
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120817222738.GH18871@opensource.wolfsonmicro.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
Message-ID: <20120818074216.GG2232@pengutronix.de>

On Fri, Aug 17, 2012 at 11:27:38PM +0100, Mark Brown wrote:
> On Fri, Aug 17, 2012 at 04:08:47PM -0300, Fabio Estevam wrote:
> 
> > Also, for the playback to work you need to install the SDMA firmware.
> 
> This is deadlocking during boot, I'm getting nowhere near trying
> playback.
You're on i.MX35, right. I had to add

	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");

to arch/arm/mach-imx/clk-imx35.c to be able to access the codec.
(Obviously this is a hack, and to do it better, you'd need to change

	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");

to use ssi1_gate and fix the ssi-driver to be aware that there are two
clocks to handle.)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From w.sang at pengutronix.de  Sat Aug 18 04:01:10 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sat, 18 Aug 2012 10:01:10 +0200
Subject: [PATCH 1/1 v4] i2c: Add default configuration into the Nomadik
 I2C driver.
In-Reply-To: <20120808131158.GD8227@gmail.com>
References: <1344266253-14050-1-git-send-email-lee.jones@linaro.org>
 <20120808131158.GD8227@gmail.com>
Message-ID: <20120818080110.GC24639@pengutronix.de>

On Wed, Aug 08, 2012 at 02:11:59PM +0100, Lee Jones wrote:
> From: Lee Jones <lee.jones at linaro.org>
> Date: Tue, 7 Aug 2012 12:27:24 +0100
> Subject: [PATCH 1/1 v4] i2c/nomadik: Add default configuration into the Nomadik I2C driver

Actually, unlike Linus said, I prefer "i2c: nomadik:"; minor nit,
though.

> 
> At this moment in time there is only one known configuration for the
> Nomadik I2C driver. By not holding that configuration in the driver
> adds some unnecessary overhead in platform code. The configuration
> as already been removed from platform code, this patch checks for any

  ^^ has ( I fixed it )

> over-riding configurations. If there aren't any, the default is used.
> 
> Cc: linux-i2c at vger.kernel.org
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Applied to -current, thanks! I added a note from Linus that it is needed
because of boot regressions. That is also useful in commit messages.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From shawn.guo at linaro.org  Sat Aug 18 04:09:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 18 Aug 2012 16:09:25 +0800
Subject: [PATCH] ARM: imx6: spin the cpu until hardware takes it down
Message-ID: <1345277365-30192-1-git-send-email-shawn.guo@linaro.org>

Though commit 602bf40 (ARM: imx6: exit coherency when shutting down
a cpu) improves the stability of imx6q cpu hotplug a lot, there are
still hangs seen with a more stressful hotplug testing.

It's expected that once imx_enable_cpu(cpu, false) is called, the cpu
will be taken down by hardware immediately, and the code after that
will not get any chance to execute.  However, this is not always the
case from the testing.  The cpu could possibly be alive for a few
cycles before hardware actually takes it down.  So rather than letting
cpu execute some code that could cause a hang in these cycles, let's
make the cpu spin there and wait for hardware to take it down.

Cc: <stable at vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/hotplug.c |   23 +++--------------------
 1 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 20ed2d5..f8f7437 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(void)
 	  : "cc");
 }
 
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(
-		"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C), "Ir" (0x40)
-	  : "cc");
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
@@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu)
 {
 	cpu_enter_lowpower();
 	imx_enable_cpu(cpu, false);
-	cpu_do_idle();
-	cpu_leave_lowpower();
 
-	/* We should never return from idle */
-	panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+	/* spin here until hardware takes it down */
+	while (1)
+		;
 }
 
 int platform_cpu_disable(unsigned int cpu)
-- 
1.7.5.4



From LW at KARO-electronics.de  Sat Aug 18 04:10:08 2012
From: LW at KARO-electronics.de (=?UTF-8?q?Lothar=20Wa=C3=9Fmann?=)
Date: Sat, 18 Aug 2012 10:10:08 +0200
Subject: [PATCH] rtc: snvs: improve timeout handling in snvs_rtc_enable()
Message-ID: <1345277408-30044-1-git-send-email-LW@KARO-electronics.de>

If snvs_rtc_enable() happens to be descheduled for a period longer
than the timout period, a timeout may be indicated even if the RTC
status has changed meanwhile. Force a status read at the end of the
timeout period to prevent bogus timeout errors.


Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
---
 drivers/rtc/rtc-snvs.c |   22 +++++++++++++---------
 1 files changed, 13 insertions(+), 9 deletions(-)

 Compile tested only due to lack of HW.

diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
index 912f116..dc921b2 100644
--- a/drivers/rtc/rtc-snvs.c
+++ b/drivers/rtc/rtc-snvs.c
@@ -81,6 +81,13 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
 	}
 }
 
+static int snvs_rtc_enable_done(int enable, void __iomem *addr)
+{
+	u32 lpcr = readl(addr + SNVS_LPCR);
+
+	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
+}
+
 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 {
 	unsigned long timeout = jiffies + msecs_to_jiffies(1);
@@ -99,18 +106,15 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 	spin_unlock_irqrestore(&data->lock, flags);
 
 	while (1) {
-		lpcr = readl(data->ioaddr + SNVS_LPCR);
+		if (snvs_rtc_enable_done(enable, data->ioaddr))
+			break;
 
-		if (enable) {
-			if (lpcr & SNVS_LPCR_SRTC_ENV)
-				break;
-		} else {
-			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
+		if (time_after(jiffies, timeout)) {
+			if (snvs_rtc_enable_done(enable, data->ioaddr))
 				break;
+			else
+				return -ETIMEDOUT;
 		}
-
-		if (time_after(jiffies, timeout))
-			return -ETIMEDOUT;
 	}
 
 	return 0;
-- 
1.7.2.5



From w.sang at pengutronix.de  Sat Aug 18 04:13:00 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sat, 18 Aug 2012 10:13:00 +0200
Subject: [PATCH] I2C: OMAP: xfer: fix runtime PM get/put balance on error
In-Reply-To: <87wr1b35qb.fsf@ti.com>
References: <1340761532-27231-1-git-send-email-khilman@ti.com>
 <87wr1b35qb.fsf@ti.com>
Message-ID: <20120818081300.GE24639@pengutronix.de>

On Mon, Aug 06, 2012 at 05:28:44PM -0700, Kevin Hilman wrote:
> Hi Wolfram,
> 
> Kevin Hilman <khilman at ti.com> writes:
> 
> > In omap_i2c_xfer(), ensure pm_runtime_put() is called, even on
> > failure.
> >
> > Without this, after a failed xfer, the runtime PM usecount will have
> > been incremented, but not decremented causing the usecount to never
> > reach zero after a failure.  This keeps the device always runtime PM
> > enabled which keeps the enclosing power domain active, and prevents
> > full-chip retention/off from happening during idle.
> >
> > Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
> > Signed-off-by: Kevin Hilman <khilman at ti.com>
> > ---
> > This patch applies to current i2c-embedded/for-next branch
> 
> This one is needed for v3.6.  Can you queue this up as a fix for
> v3.6-rc?

Done, applied to -current, thanks!

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From w.sang at pengutronix.de  Sat Aug 18 04:41:54 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sat, 18 Aug 2012 10:41:54 +0200
Subject: [PATCH v7] ARM: davinci: i2c: add OF support
In-Reply-To: <502127A4.2040505@denx.de>
References: <1343632872-25896-1-git-send-email-hs@denx.de>
 <502127A4.2040505@denx.de>
Message-ID: <20120818084154.GF24639@pengutronix.de>

On Tue, Aug 07, 2012 at 04:35:16PM +0200, Heiko Schocher wrote:
> Hello,
> 
> On 30.07.2012 09:21, Heiko Schocher wrote:
> >add of support for the davinci i2c driver.
> >
> >Signed-off-by: Heiko Schocher<hs at denx.de>
> >Signed-off-by: Sekhar Nori<nsekhar at ti.com>
> >Cc: davinci-linux-open-source at linux.davincidsp.com
> >Cc: linux-arm-kernel at lists.infradead.org
> >Cc: devicetree-discuss at lists.ozlabs.org
> >Cc: linux-i2c at vger.kernel.org
> >Cc: Ben Dooks<ben-linux at fluff.org>
> >Cc: Wolfram Sang<w.sang at pengutronix.de>
> >Cc: Grant Likely<grant.likely at secretlab.ca>
> >Cc: Sekhar Nori<nsekhar at ti.com>
> >Cc: Wolfgang Denk<wd at denx.de>
> >Cc: Sylwester Nawrocki<s.nawrocki at samsung.com>
> >
> >---
> 
> ping ... any comments?

Applied to -next with indentation fixes to the binding description.
Thanks!

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From dirk.behme at gmail.com  Sat Aug 18 05:58:33 2012
From: dirk.behme at gmail.com (Dirk Behme)
Date: Sat, 18 Aug 2012 11:58:33 +0200
Subject: [PATCH] mtd: mxc_nand: Fix compiler warnings
In-Reply-To: <20120805083926.GL2626@pengutronix.de>
References: <1343466310-14584-1-git-send-email-dirk.behme@gmail.com>
 <20120730073454.GI1528@pengutronix.de> <501D4405.6030900@googlemail.com>
 <20120805083926.GL2626@pengutronix.de>
Message-ID: <502F6749.4020705@gmail.com>

On 05.08.2012 10:39, Uwe Kleine-K?nig wrote:
> On Sat, Aug 04, 2012 at 05:47:17PM +0200, Dirk Behme wrote:
>> On 30.07.2012 09:34, Uwe Kleine-K?nig wrote:
>>> Hello,
>>>
>>> On Sat, Jul 28, 2012 at 11:05:10AM +0200, Dirk Behme wrote:
>>>> From: Dirk Behme<dirk.behme at googlemail.com>
>>>>
>>>> Fix the compiler warnings
>>>>
>>>> drivers/mtd/nand/mxc_nand.c:1267: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1270: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1273: warning: initialization discards qualifiers from pointer target type
>>>> drivers/mtd/nand/mxc_nand.c:1276: warning: initialization discards qualifiers from pointer target type
>>> These should be gone in next already.
>>
>> Hmm, which next?
>>
>> I tried linux-next [1] from today (next-20120803, 55fa9961f) and still get
> next-20120725 contained 98d7bbb9929bcc14e11ac8a55245a4f2dc174e17, don't
> konw why it isn't included in the newer next snapshorts.

It seems to be in -next again:

http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=commit;h=98d7bbb9929bcc14e11ac8a55245a4f2dc174e17

I'm not so familiar with -next: Do we have any chance to get that 
commit into 3.6-rcX to get this warning fixed for the final 3.6?

Best regards

Dirk



From keguang.zhang at gmail.com  Sat Aug 18 06:55:01 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Sat, 18 Aug 2012 18:55:01 +0800
Subject: [PATCH] clk: add Loongson1B clock support
Message-ID: <1345287301-18165-1-git-send-email-keguang.zhang@gmail.com>

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
---
 drivers/clk/Makefile   |    1 +
 drivers/clk/clk-ls1x.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 0000000..0aadf9d
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <asm/mach-loongson1/loongson1.h>
+
+#include <loongson1.h>
+
+#define OSC	33
+
+static DEFINE_SPINLOCK(_lock);
+
+int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+	return 0;
+}
+
+void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 pll, rate;
+
+	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+	rate = ((12 + (pll & 0x3f)) * 1000000) +
+		((((pll >> 8) & 0x3ff) * 1000000) >> 10);
+	rate *= OSC;
+	rate >>= 1;
+
+	return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+	.enable = ls1x_pll_clk_enable,
+	.disable = ls1x_pll_clk_disable,
+	.recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+	 const char *name, const char *parent_name, unsigned long flags)
+{
+	struct clk_hw *hw;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the divider */
+	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+	if (!hw) {
+		pr_err("%s: could not allocate clk_hw\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ls1x_pll_clk_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+	hw->init = &init;
+
+	/* register the clock */
+	clk = clk_register(dev, hw);
+
+	if (IS_ERR(clk))
+		kfree(hw);
+
+	return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+	struct clk *clk;
+
+	clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+	clk_prepare_enable(clk);
+
+	clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+			DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "cpu", NULL);
+
+	clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+			DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "ddr", NULL);
+	clk_register_clkdev(clk, "stmmaceth", NULL);
+
+	clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+			DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "dc", NULL);
+	clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Sat Aug 18 07:43:02 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sat, 18 Aug 2012 13:43:02 +0200
Subject: [PATCH] mtd: mxc_nand: Fix compiler warnings
In-Reply-To: <502F6749.4020705@gmail.com>
References: <1343466310-14584-1-git-send-email-dirk.behme@gmail.com>
 <20120730073454.GI1528@pengutronix.de>
 <501D4405.6030900@googlemail.com>
 <20120805083926.GL2626@pengutronix.de> <502F6749.4020705@gmail.com>
Message-ID: <20120818114302.GH2232@pengutronix.de>

Hi Dirk,

On Sat, Aug 18, 2012 at 11:58:33AM +0200, Dirk Behme wrote:
> On 05.08.2012 10:39, Uwe Kleine-K?nig wrote:
> >On Sat, Aug 04, 2012 at 05:47:17PM +0200, Dirk Behme wrote:
> >>On 30.07.2012 09:34, Uwe Kleine-K?nig wrote:
> >>>Hello,
> >>>
> >>>On Sat, Jul 28, 2012 at 11:05:10AM +0200, Dirk Behme wrote:
> >>>>From: Dirk Behme<dirk.behme at googlemail.com>
> >>>>
> >>>>Fix the compiler warnings
> >>>>
> >>>>drivers/mtd/nand/mxc_nand.c:1267: warning: initialization discards qualifiers from pointer target type
> >>>>drivers/mtd/nand/mxc_nand.c:1270: warning: initialization discards qualifiers from pointer target type
> >>>>drivers/mtd/nand/mxc_nand.c:1273: warning: initialization discards qualifiers from pointer target type
> >>>>drivers/mtd/nand/mxc_nand.c:1276: warning: initialization discards qualifiers from pointer target type
> >>>These should be gone in next already.
> >>
> >>Hmm, which next?
> >>
> >>I tried linux-next [1] from today (next-20120803, 55fa9961f) and still get
> >next-20120725 contained 98d7bbb9929bcc14e11ac8a55245a4f2dc174e17, don't
> >konw why it isn't included in the newer next snapshorts.
> 
> It seems to be in -next again:
> 
> http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=commit;h=98d7bbb9929bcc14e11ac8a55245a4f2dc174e17
> 
> I'm not so familiar with -next: Do we have any chance to get that
> commit into 3.6-rcX to get this warning fixed for the final 3.6?
Arnd sent a pull request that Linus T. seems to have ignored so far.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From marek.belisko at gmail.com  Sat Aug 18 07:43:58 2012
From: marek.belisko at gmail.com (Belisko Marek)
Date: Sat, 18 Aug 2012 13:43:58 +0200
Subject: [PATCH] clk: add Loongson1B clock support
In-Reply-To: <1345287301-18165-1-git-send-email-keguang.zhang@gmail.com>
References: <1345287301-18165-1-git-send-email-keguang.zhang@gmail.com>
Message-ID: <CAAfyv36-wwvSFJGXN9bmDy8pdDOT_h0b7sy78+7f4kCW57AxuA@mail.gmail.com>

On Sat, Aug 18, 2012 at 12:55 PM, Kelvin Cheung <keguang.zhang at gmail.com> wrote:
> This adds clock support to Loongson1B SoC using the common clock
> infrastructure.
>
> Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
> ---
>  drivers/clk/Makefile   |    1 +
>  drivers/clk/clk-ls1x.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 109 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/clk-ls1x.c
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 5869ea3..018ec57 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)    += socfpga/
>  obj-$(CONFIG_PLAT_SPEAR)       += spear/
>  obj-$(CONFIG_ARCH_U300)                += clk-u300.o
>  obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
> +obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
>
>  # Chip specific
>  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
> new file mode 100644
> index 0000000..0aadf9d
> --- /dev/null
> +++ b/drivers/clk/clk-ls1x.c
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <asm/mach-loongson1/loongson1.h>
> +
> +#include <loongson1.h>
> +
> +#define OSC    33
> +
> +static DEFINE_SPINLOCK(_lock);
> +
> +int ls1x_pll_clk_enable(struct clk_hw *hw)
^^^^static
> +{
> +       return 0;
> +}
> +
> +void ls1x_pll_clk_disable(struct clk_hw *hw)
^^^^ also static
> +{
> +}
> +
> +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
> +                                            unsigned long parent_rate)
> +{
> +       u32 pll, rate;
> +
> +       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
> +       rate = ((12 + (pll & 0x3f)) * 1000000) +
> +               ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
> +       rate *= OSC;
> +       rate >>= 1;
> +
> +       return rate;
> +}
> +
> +static const struct clk_ops ls1x_pll_clk_ops = {
> +       .enable = ls1x_pll_clk_enable,
> +       .disable = ls1x_pll_clk_disable,
> +       .recalc_rate = ls1x_pll_recalc_rate,
> +};
> +
> +static struct clk * __init clk_register_pll(struct device *dev,
> +        const char *name, const char *parent_name, unsigned long flags)
> +{
> +       struct clk_hw *hw;
> +       struct clk *clk;
> +       struct clk_init_data init;
> +
> +       /* allocate the divider */
> +       hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
> +       if (!hw) {
> +               pr_err("%s: could not allocate clk_hw\n", __func__);
> +               return ERR_PTR(-ENOMEM);
> +       }
> +
> +       init.name = name;
> +       init.ops = &ls1x_pll_clk_ops;
> +       init.flags = flags | CLK_IS_BASIC;
> +       init.parent_names = (parent_name ? &parent_name : NULL);
> +       init.num_parents = (parent_name ? 1 : 0);
> +       hw->init = &init;
> +
> +       /* register the clock */
> +       clk = clk_register(dev, hw);
> +
> +       if (IS_ERR(clk))
> +               kfree(hw);
> +
> +       return clk;
> +}
> +
> +void __init ls1x_clk_init(void)
> +{
> +       struct clk *clk;
> +
> +       clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
> +       clk_prepare_enable(clk);
> +
> +       clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
> +                       DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "cpu", NULL);
> +
> +       clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
> +                       DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "ddr", NULL);
> +       clk_register_clkdev(clk, "stmmaceth", NULL);
> +
> +       clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
> +                       DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "dc", NULL);
> +       clk_register_clkdev(clk, "serial8250", NULL);
> +}
> --
> 1.7.1
>
> --
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> Please read the FAQ at  http://www.tux.org/lkml/

cheers,

marek

-- 
as simple and primitive as possible
-------------------------------------------------
Marek Belisko - OPEN-NANDRA
Freelance Developer

Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
twitter: #opennandra
web: http://open-nandra.com


From keguang.zhang at gmail.com  Sat Aug 18 08:08:26 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Sat, 18 Aug 2012 20:08:26 +0800
Subject: [PATCH v2] clk: add Loongson1B clock support
Message-ID: <1345291706-26211-1-git-send-email-keguang.zhang@gmail.com>

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
---
 drivers/clk/Makefile   |    1 +
 drivers/clk/clk-ls1x.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 0000000..ff12fc0
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <asm/mach-loongson1/loongson1.h>
+
+#include <loongson1.h>
+
+#define OSC	33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 pll, rate;
+
+	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+	rate = ((12 + (pll & 0x3f)) * 1000000) +
+		((((pll >> 8) & 0x3ff) * 1000000) >> 10);
+	rate *= OSC;
+	rate >>= 1;
+
+	return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+	.enable = ls1x_pll_clk_enable,
+	.disable = ls1x_pll_clk_disable,
+	.recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+	 const char *name, const char *parent_name, unsigned long flags)
+{
+	struct clk_hw *hw;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the divider */
+	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+	if (!hw) {
+		pr_err("%s: could not allocate clk_hw\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ls1x_pll_clk_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+	hw->init = &init;
+
+	/* register the clock */
+	clk = clk_register(dev, hw);
+
+	if (IS_ERR(clk))
+		kfree(hw);
+
+	return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+	struct clk *clk;
+
+	clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+	clk_prepare_enable(clk);
+
+	clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+			DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "cpu", NULL);
+
+	clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+			DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "ddr", NULL);
+	clk_register_clkdev(clk, "stmmaceth", NULL);
+
+	clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+			DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "dc", NULL);
+	clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1



From shawn.guo at linaro.org  Sat Aug 18 08:46:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 18 Aug 2012 20:46:54 +0800
Subject: [PATCH] rtc: snvs: improve timeout handling in snvs_rtc_enable()
In-Reply-To: <1345277408-30044-1-git-send-email-LW@KARO-electronics.de>
References: <1345277408-30044-1-git-send-email-LW@KARO-electronics.de>
Message-ID: <20120818124652.GH24242@S2101-09.ap.freescale.net>

On Sat, Aug 18, 2012 at 10:10:08AM +0200, Lothar Wa?mann wrote:
> If snvs_rtc_enable() happens to be descheduled for a period longer
> than the timout period, a timeout may be indicated even if the RTC
> status has changed meanwhile. Force a status read at the end of the
> timeout period to prevent bogus timeout errors.
> 
> 
> Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
> ---
>  drivers/rtc/rtc-snvs.c |   22 +++++++++++++---------
>  1 files changed, 13 insertions(+), 9 deletions(-)
> 
>  Compile tested only due to lack of HW.

Tested-by: Shawn Guo <shawn.guo at linaro.org>

A small nitpick below.

> 
> diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
> index 912f116..dc921b2 100644
> --- a/drivers/rtc/rtc-snvs.c
> +++ b/drivers/rtc/rtc-snvs.c
> @@ -81,6 +81,13 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
>  	}
>  }
>  
> +static int snvs_rtc_enable_done(int enable, void __iomem *addr)

Can we rename parameter "addr" to "ioaddr" and put it before "enable",
also change "enable" to bool?

Regards,
Shawn

> +{
> +	u32 lpcr = readl(addr + SNVS_LPCR);
> +
> +	return !!enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
> +}
> +
>  static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
>  {
>  	unsigned long timeout = jiffies + msecs_to_jiffies(1);
> @@ -99,18 +106,15 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
>  	spin_unlock_irqrestore(&data->lock, flags);
>  
>  	while (1) {
> -		lpcr = readl(data->ioaddr + SNVS_LPCR);
> +		if (snvs_rtc_enable_done(enable, data->ioaddr))
> +			break;
>  
> -		if (enable) {
> -			if (lpcr & SNVS_LPCR_SRTC_ENV)
> -				break;
> -		} else {
> -			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
> +		if (time_after(jiffies, timeout)) {
> +			if (snvs_rtc_enable_done(enable, data->ioaddr))
>  				break;
> +			else
> +				return -ETIMEDOUT;
>  		}
> -
> -		if (time_after(jiffies, timeout))
> -			return -ETIMEDOUT;
>  	}
>  
>  	return 0;
> -- 
> 1.7.2.5
> 


From LW at KARO-electronics.de  Sat Aug 18 09:14:04 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Sat, 18 Aug 2012 15:14:04 +0200
Subject: [PATCH] rtc: snvs: improve timeout handling in snvs_rtc_enable()
In-Reply-To: <20120818124652.GH24242@S2101-09.ap.freescale.net>
References: <1345277408-30044-1-git-send-email-LW@KARO-electronics.de>
 <20120818124652.GH24242@S2101-09.ap.freescale.net>
Message-ID: <20527.38172.621130.368019@ipc1.ka-ro>

Shawn Guo writes:
> On Sat, Aug 18, 2012 at 10:10:08AM +0200, Lothar Wa?mann wrote:
> > If snvs_rtc_enable() happens to be descheduled for a period longer
> > than the timout period, a timeout may be indicated even if the RTC
> > status has changed meanwhile. Force a status read at the end of the
> > timeout period to prevent bogus timeout errors.
> > 
> > 
> > Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
> > ---
> >  drivers/rtc/rtc-snvs.c |   22 +++++++++++++---------
> >  1 files changed, 13 insertions(+), 9 deletions(-)
> > 
> >  Compile tested only due to lack of HW.
> 
> Tested-by: Shawn Guo <shawn.guo at linaro.org>
> 
> A small nitpick below.
> 
> > 
> > diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
> > index 912f116..dc921b2 100644
> > --- a/drivers/rtc/rtc-snvs.c
> > +++ b/drivers/rtc/rtc-snvs.c
> > @@ -81,6 +81,13 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
> >  	}
> >  }
> >  
> > +static int snvs_rtc_enable_done(int enable, void __iomem *addr)
> 
> Can we rename parameter "addr" to "ioaddr" and put it before "enable",
> also change "enable" to bool?
> 
OK. The resulting assembler code of the patch below is identical to
the previous version of this patch.


Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
Tested-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/rtc/rtc-snvs.c |   22 +++++++++++++---------
 1 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
index 912f116..a757cb9 100644
--- a/drivers/rtc/rtc-snvs.c
+++ b/drivers/rtc/rtc-snvs.c
@@ -81,6 +81,13 @@ static void rtc_write_sync_lp(void __iomem *ioaddr)
 	}
 }
 
+static int snvs_rtc_enable_done(void __iomem *ioaddr, bool enable)
+{
+	u32 lpcr = readl(ioaddr + SNVS_LPCR);
+
+	return enable ^ !(lpcr & SNVS_LPCR_SRTC_ENV);
+}
+
 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 {
 	unsigned long timeout = jiffies + msecs_to_jiffies(1);
@@ -99,18 +106,15 @@ static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
 	spin_unlock_irqrestore(&data->lock, flags);
 
 	while (1) {
-		lpcr = readl(data->ioaddr + SNVS_LPCR);
+		if (snvs_rtc_enable_done(data->ioaddr, enable))
+			break;
 
-		if (enable) {
-			if (lpcr & SNVS_LPCR_SRTC_ENV)
-				break;
-		} else {
-			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
+		if (time_after(jiffies, timeout)) {
+			if (snvs_rtc_enable_done(data->ioaddr, enable))
 				break;
+			else
+				return -ETIMEDOUT;
 		}
-
-		if (time_after(jiffies, timeout))
-			return -ETIMEDOUT;
 	}
 
 	return 0;
-- 
1.7.2.5


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From festevam at gmail.com  Sat Aug 18 10:53:35 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sat, 18 Aug 2012 11:53:35 -0300
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120818074216.GG2232@pengutronix.de>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
 <20120818074216.GG2232@pengutronix.de>
Message-ID: <CAOMZO5BirGnUqmvprk-PKDfJ-PX9GYkLeULHRKETUsedbi2F2A@mail.gmail.com>

On Sat, Aug 18, 2012 at 4:42 AM, Uwe Kleine-K?nig
<u.kleine-koenig at pengutronix.de> wrote:

> You're on i.MX35, right. I had to add
>
>         clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");

Ah, ok. This is the same we have on arch/arm/mach-imx/clk-imx31.c ,

and mx31 audio playback is functional in next, so it looks like this
will fix Mark's issue on mx35.

Uwe, would you like to send this patch for clk-imx35.c ?

Regards,

Fabio Estevam


From linux at arm.linux.org.uk  Sat Aug 18 10:58:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 18 Aug 2012 15:58:56 +0100
Subject: [BUG] Deferred probing in driver model is racy, resulting in lost
 probes
Message-ID: <20120818145856.GP18957@n2100.arm.linux.org.uk>

Okay, so EPROBE_DEFER seems to work when I build everything into the
kernel, but when I build a pile of ASoC drivers as modules, it fails
every time I've tried booting the platform so far.

This is a v3.5 based kernel, with preempt enabled.

Okay, what I have is a bunch of devices already pre-registered in the
system:

	kirkwood-spdif-audio.1 (requiring module snd_soc_kirkwood_spdif)
	kirkwood-i2s.1 (requiring module snd_soc_kirkwood_i2s)
	kirkwood-pcm-audio.1 (requiring module snd_soc_kirkwood)
	spdif-dit (requiring module snd_soc_spdif)

and the modules were loaded in this order:

Module                  Size  Used by
snd_soc_spdif           1020  0		(spdif-dit driver)
dove                   24577  1		(dove-drm driver)
snd_soc_kirkwood_i2s     5209  0	(kirkwood-i2s driver)
snd_soc_kirkwood        3629  0		(kirkwood-pcm-audio driver)
snd_soc_kirkwood_spdif     1449  0	(kirkwood-spdif-audio driver)

snd_soc_kirkwood_spdif will return -EPROBE_DEFER if it can't find the
devices registered into ASoC by the other three modules (referred to as
the CPU DAI, and Codec DAI).

What I see in the debugging is this (I've added some to increase the
debuggability):

bus: 'platform': add driver kirkwood-spdif-audio
bus: 'platform': driver_probe_device: matched device kirkwood-spdif-audio.1 with driver kirkwood-spdif-audio
bus: 'platform': really_probe: probing driver kirkwood-spdif-audio with device kirkwood-spdif-audio.1
kirkwood-spdif-audio kirkwood-spdif-audio.1: CPU DAI kirkwood-i2s.1 not registered
bus: 'platform': add driver kirkwood-pcm-audio
bus: 'platform': add driver kirkwood-i2s
kirkwood-spdif-audio kirkwood-spdif-audio.1: failed to register card
bus: 'platform': add driver dove-drm
platform kirkwood-spdif-audio.1: Driver kirkwood-spdif-audio requests probe deferral
platform kirkwood-spdif-audio.1: Added to deferred list
bus: 'platform': driver_probe_device: matched device kirkwood-pcm-audio.1 with driver kirkwood-pcm-audio
bus: 'platform': really_probe: probing driver kirkwood-pcm-audio with device kirkwood-pcm-audio.1
driver: 'kirkwood-pcm-audio.1': driver_bound: bound to device 'kirkwood-pcm-audio'
bus: 'platform': really_probe: bound device kirkwood-pcm-audio.1 to driver kirkwood-pcm-audio
platform kirkwood-spdif-audio.1: Retrying from deferred list
bus: device_attach 'kirkwood-spdif-audio.1' unbound
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'dove-temp'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'galcore'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'alarmtimer'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'mv_xor_shared'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'mv_xor'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'serial8250'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'sata_mv'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'orion_spi'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'mv643xx_eth'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'mv643xx_eth_port'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'ap510-vmeta'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'orion-ehci'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'rtc-mv'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'mv64xxx_i2c'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'gpio-rc-recv'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'sdhci-pxav2'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'sdhci-dove'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'leds-gpio'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'snd-soc-dummy'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'soc-audio'
bus: __device_attach 'kirkwood-spdif-audio.1' probing with 'kirkwood-pcm-audio'

What you notice here is that the kirkwood-spdif-audio driver has gone
missing - it hasn't been unloaded, and it still appears in sysfs, and
it can still be cleanly unloaded and reloaded.

bus: 'platform': driver_probe_device: matched device kirkwood-i2s.1 with driver kirkwood-i2s
bus: 'platform': really_probe: probing driver kirkwood-i2s with device kirkwood-i2s.1
kirkwood-i2s kirkwood-i2s.1: found external clock
driver: 'kirkwood-i2s.1': driver_bound: bound to device 'kirkwood-i2s'
bus: 'platform': really_probe: bound device kirkwood-i2s.1 to driver kirkwood-i2s
bus: 'platform': driver_probe_device: matched device dove-drm with driver dove-drm
bus: 'platform': really_probe: probing driver dove-drm with device dove-drm
bus: 'platform': add driver spdif-dit
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] No driver support for vblank timestamp query.
fb0: dove-drmfb frame buffer device
drm: registered panic notifier
[drm] Initialized dove-drm 1.0.0 20120730 on minor 0
driver: 'dove-drm': driver_bound: bound to device 'dove-drm'
bus: 'platform': really_probe: bound device dove-drm to driver dove-drm
bus: 'platform': driver_probe_device: matched device spdif-dit with driver spdif-dit
bus: 'platform': really_probe: probing driver spdif-dit with device spdif-dit
driver: 'spdif-dit': driver_bound: bound to device 'spdif-dit'
bus: 'platform': really_probe: bound device spdif-dit to driver spdif-dit

I suspect what is going on is that we have a race condition between the
device being added to the deferred list vs other drivers successfully
probing and running the deferred list, and the driver with the deferred
device being added to the driver list.

This allows the deferred list to be run *before* the driver is placed
onto the bus driver list, which means when we try to re-probe deferred
devices, we find no matching driver to probe the device with.  This
then results in the device being dropped off the deferred probe list
(as the only way it stays on that list is if a driver is probed _and_
it returns -EPROBE_DEFER.)

I do not know all the details of the locking in this area, so I'm not
going to try to come up with a patch... but as this stands, it's
unworkable.  I have not yet had the system come up once with these
drivers as modules and had it work without having to manually remove
and re-add the Kirkwood SPDIF driver.


From peter.ujfalusi at ti.com  Sat Aug 18 11:58:10 2012
From: peter.ujfalusi at ti.com (Ujfalusi, Peter)
Date: Sat, 18 Aug 2012 17:58:10 +0200
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <20120818060810.GH11011@atomide.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120817130723.GZ11011@atomide.com> <502E43BC.30708@bitmer.com>
 <502E4F2B.6060403@ti.com> <20120818060810.GH11011@atomide.com>
Message-ID: <CAPo=G1w5N5GVra7TK=En9xnaFmNNP1Zb7g2tZSjg8CO8wewOwA@mail.gmail.com>

Hi Tony,

On Sat, Aug 18, 2012 at 8:08 AM, Tony Lindgren <tony at atomide.com> wrote:
> Thanks, is this patch still correct so it does not try to enable FIFO
> for 2420?

Yes it only enables the FIFO for 2430, 2420 is not affected.

-- 
P?ter


From festevam at gmail.com  Sat Aug 18 12:23:45 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sat, 18 Aug 2012 13:23:45 -0300
Subject: [PATCH 01/11] ARM: defconfig: Remove CONFIG_MISC_DEVICES
Message-ID: <1345307035-3545-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

commit 7c5763 (drivers:misc: Remove MISC_DEVICES config option) removed 
CONFIG_MISC_DEVICES option, so remove the occurrences from the config files 
as well.

Cc: <linux-arm-kernel at lists.infradead.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/acs5k_tiny_defconfig     |    1 -
 arch/arm/configs/ap4evb_defconfig         |    1 -
 arch/arm/configs/at91sam9261_defconfig    |    1 -
 arch/arm/configs/at91sam9263_defconfig    |    1 -
 arch/arm/configs/at91sam9g45_defconfig    |    1 -
 arch/arm/configs/bcmring_defconfig        |    1 -
 arch/arm/configs/cam60_defconfig          |    1 -
 arch/arm/configs/cm_x2xx_defconfig        |    1 -
 arch/arm/configs/cns3420vb_defconfig      |    1 -
 arch/arm/configs/colibri_pxa300_defconfig |    1 -
 arch/arm/configs/cpu9260_defconfig        |    1 -
 arch/arm/configs/cpu9g20_defconfig        |    1 -
 arch/arm/configs/em_x270_defconfig        |    1 -
 arch/arm/configs/ezx_defconfig            |    1 -
 arch/arm/configs/g3evm_defconfig          |    1 -
 arch/arm/configs/g4evm_defconfig          |    1 -
 arch/arm/configs/h3600_defconfig          |    1 -
 arch/arm/configs/imote2_defconfig         |    1 -
 arch/arm/configs/kirkwood_defconfig       |    1 -
 arch/arm/configs/magician_defconfig       |    1 -
 arch/arm/configs/mmp2_defconfig           |    1 -
 arch/arm/configs/nuc910_defconfig         |    1 -
 arch/arm/configs/nuc950_defconfig         |    1 -
 arch/arm/configs/nuc960_defconfig         |    1 -
 arch/arm/configs/palmz72_defconfig        |    1 -
 arch/arm/configs/pcm027_defconfig         |    1 -
 arch/arm/configs/pxa168_defconfig         |    1 -
 arch/arm/configs/pxa3xx_defconfig         |    1 -
 arch/arm/configs/pxa910_defconfig         |    1 -
 arch/arm/configs/qil-a9260_defconfig      |    1 -
 arch/arm/configs/s5p64x0_defconfig        |    1 -
 arch/arm/configs/s5pv210_defconfig        |    1 -
 arch/arm/configs/sam9_l9260_defconfig     |    1 -
 arch/arm/configs/stamp9g20_defconfig      |    1 -
 arch/arm/configs/tct_hammer_defconfig     |    1 -
 arch/arm/configs/usb-a9260_defconfig      |    1 -
 arch/arm/configs/vexpress_defconfig       |    1 -
 arch/arm/configs/xcep_defconfig           |    1 -
 38 files changed, 38 deletions(-)

diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig
index 2a27a14..ae52a07 100644
--- a/arch/arm/configs/acs5k_tiny_defconfig
+++ b/arch/arm/configs/acs5k_tiny_defconfig
@@ -40,7 +40,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_ARM_KS8695_ETHER=y
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
index 2eef85e..ba3455d 100644
--- a/arch/arm/configs/ap4evb_defconfig
+++ b/arch/arm/configs/ap4evb_defconfig
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index 1e8712e..c2005df 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -51,7 +51,6 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index d2050ca..b89306e 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -66,7 +66,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 606d48f..a3cb69e 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -65,7 +65,6 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
index 9e6a8fe..e67e755 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -47,7 +47,6 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_BCM_UMI=y
 CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
index cedc92e..04a4edf 100644
--- a/arch/arm/configs/cam60_defconfig
+++ b/arch/arm/configs/cam60_defconfig
@@ -53,7 +53,6 @@ CONFIG_MTD_NAND_VERIFY_WRITE=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_TGT=y
 CONFIG_BLK_DEV_SD=y
diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
index a93ff8d..a443065 100644
--- a/arch/arm/configs/cm_x2xx_defconfig
+++ b/arch/arm/configs/cm_x2xx_defconfig
@@ -69,7 +69,6 @@ CONFIG_MTD_NAND_CM_X270=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=m
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index 313627a..366e834 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -38,7 +38,6 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=20000
-# CONFIG_MISC_DEVICES is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
index b985334..76c4866 100644
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ b/arch/arm/configs/colibri_pxa300_defconfig
@@ -17,7 +17,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
index 921480c..4a50e2a 100644
--- a/arch/arm/configs/cpu9260_defconfig
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -40,7 +40,6 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
index ea116cb..10d5991 100644
--- a/arch/arm/configs/cpu9g20_defconfig
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -40,7 +40,6 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
index 60a21e0..1f409cd 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/em_x270_defconfig
@@ -63,7 +63,6 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index d95763d..90f8ba4 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -190,7 +190,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 # CONFIG_NETDEV_1000 is not set
diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig
index 4a336ab..52d9235 100644
--- a/arch/arm/configs/g3evm_defconfig
+++ b/arch/arm/configs/g3evm_defconfig
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig
index 21c6d03..2f20f40 100644
--- a/arch/arm/configs/g4evm_defconfig
+++ b/arch/arm/configs/g4evm_defconfig
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index 317960f..ea97960 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -41,7 +41,6 @@ CONFIG_MTD_SA1100=y
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECS=y
 CONFIG_NETDEVICES=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index fd996bb..84195c8 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -170,7 +170,6 @@ CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 # CONFIG_NETDEV_1000 is not set
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af5..87df04a 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -69,7 +69,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index a691ef4..1790e2b 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -67,7 +67,6 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a58452..7da3dab 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -34,7 +34,6 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_GENERIC=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig
index 10180cf..c1cd29f 100644
--- a/arch/arm/configs/nuc910_defconfig
+++ b/arch/arm/configs/nuc910_defconfig
@@ -25,7 +25,6 @@ CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig
index 27aa873..923254b 100644
--- a/arch/arm/configs/nuc950_defconfig
+++ b/arch/arm/configs/nuc950_defconfig
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig
index 56fd7ad..14dc661 100644
--- a/arch/arm/configs/nuc960_defconfig
+++ b/arch/arm/configs/nuc960_defconfig
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
index 4baa83c..3d7a8dd 100644
--- a/arch/arm/configs/palmz72_defconfig
+++ b/arch/arm/configs/palmz72_defconfig
@@ -34,7 +34,6 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
index 2f136c3..fa85865 100644
--- a/arch/arm/configs/pcm027_defconfig
+++ b/arch/arm/configs/pcm027_defconfig
@@ -47,7 +47,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
index 74d7e01..bbb9843 100644
--- a/arch/arm/configs/pxa168_defconfig
+++ b/arch/arm/configs/pxa168_defconfig
@@ -30,7 +30,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 1677a06..62f5e46 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -44,7 +44,6 @@ CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e..985fb89 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -30,7 +30,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index 42d5db1..ed1de4f 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -51,7 +51,6 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
index ad6b61b..5a3d76f 100644
--- a/arch/arm/configs/s5p64x0_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -20,7 +20,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index fa98990..ecc7f44 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -25,7 +25,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index da276f9..78355b1 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -44,7 +44,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_RAID_ATTRS=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
index 52f1488..0d32d73 100644
--- a/arch/arm/configs/stamp9g20_defconfig
+++ b/arch/arm/configs/stamp9g20_defconfig
@@ -51,7 +51,6 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 71277a1..0aaf23f 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -36,7 +36,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=10240
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
index a1501e1..e2a124d 100644
--- a/arch/arm/configs/usb-a9260_defconfig
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -50,7 +50,6 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f2de51f..a1c0541 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -55,7 +55,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MISC_DEVICES=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig
index 721832f..d718e51 100644
--- a/arch/arm/configs/xcep_defconfig
+++ b/arch/arm/configs/xcep_defconfig
@@ -50,7 +50,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_MTD_PXA2XX=y
-# CONFIG_MISC_DEVICES is not set
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 # CONFIG_NETDEV_1000 is not set
-- 
1.7.9.5



From arnd at arndb.de  Sat Aug 18 14:08:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 18 Aug 2012 18:08:21 +0000
Subject: [PATCH 01/11] ARM: defconfig: Remove CONFIG_MISC_DEVICES
In-Reply-To: <1345307035-3545-1-git-send-email-festevam@gmail.com>
References: <1345307035-3545-1-git-send-email-festevam@gmail.com>
Message-ID: <201208181808.21484.arnd@arndb.de>

On Saturday 18 August 2012, Fabio Estevam wrote:
> 
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> commit 7c5763 (drivers:misc: Remove MISC_DEVICES config option) removed 
> CONFIG_MISC_DEVICES option, so remove the occurrences from the config files 
> as well.
> 
> Cc: <linux-arm-kernel at lists.infradead.org>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Sat Aug 18 17:14:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 18 Aug 2012 21:14:34 +0000
Subject: [PATCH 02/14] at91: regroup gpio and pinctrl under a simple-bus
In-Reply-To: <1344603731-32667-2-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <201208182114.35063.arnd@arndb.de>

On Friday 10 August 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> -                       pioA: gpio at fffff400 {
> -                               compatible = "atmel,at91rm9200-gpio";
> -                               reg = <0xfffff400 0x100>;
> -                               interrupts = <2 4 1>;
> -                               #gpio-cells = <2>;
> -                               gpio-controller;
> -                               interrupt-controller;
> -                       };
> +                       pinctrl at fffff400 {
> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges;
> +                               compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
> +                               reg = <0xfffff400 0x600>;
> +
> +                               pioA: gpio at fffff400 {
> +                                       compatible = "atmel,at91rm9200-gpio";
> +                                       reg = <0xfffff400 0x200>;
> +                                       interrupts = <2 4 1>;
> +                                       #gpio-cells = <2>;
> +                                       gpio-controller;
> +                                       interrupt-controller;
> +                               };

Hmm, If the node declares itself to be an interrupt-controller, it should
normally have an #interrupt-cells property as well.

Also, I think you should not list the same registers in both the parent
and the children. It's probably better to remove the registers in the
parent node and just refer to the children from the pinctrl driver.
Since the pinctrl device is not really a bus in the sense that devices
connected to it see the same address space, you could have the
registers translated like 

	ranges = <0xfffff400 0 0x600>;


	Arnd


From arnd at arndb.de  Sat Aug 18 17:18:45 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 18 Aug 2012 21:18:45 +0000
Subject: [PATCH 03/14] arm: at91: at91sam9x5: fix gpio number per bank
In-Reply-To: <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <201208182118.45349.arnd@arndb.de>

On Friday 10 August 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> @@ -9,6 +9,10 @@ Required properties:
>    unused).
>  - gpio-controller: Marks the device node as a GPIO controller.
>  
> +optional properties:
> +- gpio-nb: Number of gpio if absent 32.
> +
> +
>  Example:
>         pioA: gpio at fffff200 {
>                 compatible = "atmel,at91rm9200-gpio";
> @@ -16,5 +20,6 @@ Example:
>                 interrupts = <2 4>;
>                 #gpio-cells = <2>;
>                 gpio-controller;
> +               gpio-nb = <19>;

What does "nb" stand for?

The marvell-gpio binding uses "ngpio" for the number, so that would
already be established. Otherwise, I think "#gpio-lines" would be
more in line with other things we count in the bindings.

	Arnd


From linus.walleij at linaro.org  Sat Aug 18 18:42:12 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 19 Aug 2012 00:42:12 +0200
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <20120816124002.GB7439@game.jcrosoft.org>
References: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
 <20120816124002.GB7439@game.jcrosoft.org>
Message-ID: <CACRpkdZDMxk30YTkrumRveR3OuWptSpzNevrAvC2FxYShOZp-A@mail.gmail.com>

On Thu, Aug 16, 2012 at 2:40 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> On 14:16 Thu 16 Aug     , Linus Walleij wrote:
>> +/* For the Device Tree, add in the UART callbacks as AUXDATA */
>> +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
>> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
>> +             "rtc", NULL),
>> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
>> +             "uart0", &integrator_uart_data),
>> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
>> +             "uart1", &integrator_uart_data),
>> +     OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
>> +             "kmi0", NULL),
>> +     OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
>> +             "kmi1", NULL),
>> +     { /* sentinel */ },

> why that?

Based on similar code by Grant in arch/arm/mach-versatile/core.c
also ending with a {}. Also at other places ... I though this terminated
the list iteration, is it not needed anymore?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Sat Aug 18 19:06:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sun, 19 Aug 2012 01:06:50 +0200
Subject: [PATCH 0/6] Integrator devicetree support
In-Reply-To: <201208161344.55723.arnd@arndb.de>
References: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
 <201208161344.55723.arnd@arndb.de>
Message-ID: <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>

On Thu, Aug 16, 2012 at 3:44 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 16 August 2012, Linus Walleij wrote:
>> This patch set moves all the non-DT platform code into
>> #ifndef CONFIG_OF sections for clarity. The plan is to
>> delete them after deprecation.
>
> I'm fine with your playing around with this in any way you
> like, but I think in general we should have a new CONFIG_ATAG
> symbol, so you can build a kernel that supports booting
> both with and without DT for the same platform, depending
> on what the boot loader supports.
>
> Then you can enclose all the non-DT sections in #ifdef
> CONFIG_ATAG and we can remove them at some later stage.

Since we already have CONFIG_USE_OF I think
CONFIG_USE_ATAGS is more apropriate, but I get the
idea. So it begins like this:

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..0764ef7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1907,6 +1907,12 @@ endmenu

 menu "Boot options"

+config USE_ATAGS
+       bool "ATAGS support"
+       default y
+       help
+         Include support for ATAGS-based machine descriptions.
+
 config USE_OF
        bool "Flattened Device Tree support"
        select OF
@@ -2110,6 +2116,7 @@ config KEXEC

 config ATAGS_PROC
        bool "Export atags in procfs"
+       depends on USE_ATAGS
        depends on KEXEC
        default y
        help

But then we hit #ifdeffing and compiling out a lot of dangerous stuff
in arch/arm/kernel and then I get the creeps. I can try, but I think
this is typical Nico territory for example...

Yours,
Linus Walleij


From marcos21xx at gmail.com  Sat Aug 18 21:22:23 2012
From: marcos21xx at gmail.com (Marcos Silva Cunha)
Date: Sat, 18 Aug 2012 18:22:23 -0700 (PDT)
Subject: [PATCH 0/8] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
References: <1344389967-8465-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <f807b970-dbc1-4c58-8647-42d5291b096b@googlegroups.com>

These patches can be used directly on kernel.org's main tarballs? Or just 
on gitorious/vt8500 ?

On Tuesday, 7 August 2012 22:39:18 UTC-3, Tony Prisk wrote:
>
> This patchset updates arch-vt8500 to devicetree and removes all the 
> old-style 
> code. Support for WM8650 has also been added. 
>
> Example dts/dtsi files are given for the three currently supported models. 
>
> Major changes: 
>
> GPIO code has been converted to a platform_device and rewritten as WM8505 
> support was broken. Add support for WM8650 gpio controller. 
>
> UHCI support was missing. Added this as a generic non-pci uhci controller 
> as 
> it doesn't require anything special. Should be usable by any system that 
> doesn't 
> have special requirements to get the UHCI controller working. 
>
> Framebuffer code patched to support WM8650. The bindings for this are of 
> concern 
> but there doesn't seem to be a formalized binding yet. This patch is based 
> off 
> Sascha Hauer's current patch on the dri-devel mailing list and should be 
> easily 
> patched out when its finalized. 
>
> Patchset based on Arnd's arm-soc/for-next branch. 
>
>
> Could I get this reviewed, hopefully for inclusion into v3.7. 
>
> Regards 
> Tony Prisk 
>
>
> Tony Prisk (8): 
>   arm: vt8500: Add device tree files for VIA/Wondermedia SoC's 
>   rtc: vt8500: Add devicetree support for vt8500-rtc 
>   serial: vt8500: Add devicetree support for vt8500-serial 
>   usb: vt8500: Add devicetree support for vt8500-ehci and -uhci. 
>   video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb 
>   arm: vt8500: Update arch-vt8500 to devicetree support. 
>   arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices 
>   ARM: vt8500: gpio: Devicetree support for arch-vt8500 
>
>  Documentation/devicetree/bindings/arm/vt8500.txt   |   15 + 
>  .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 + 
>  .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 + 
>  .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 + 
>  .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 ++ 
>  .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 + 
>  .../bindings/tty/serial/via,vt8500-uart.txt        |   15 + 
>  .../devicetree/bindings/usb/platform-uhci.txt      |   15 + 
>  .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 + 
>  .../devicetree/bindings/vendor-prefixes.txt        |    2 + 
>  .../devicetree/bindings/video/via,vt8500-fb.txt    |   46 +++ 
>  .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 + 
>  .../devicetree/bindings/video/wm,wm8505-fb.txt     |   20 ++ 
>  arch/arm/Kconfig                                   |    2 + 
>  arch/arm/boot/dts/vt8500.dtsi                      |   99 ++++++ 
>  arch/arm/boot/dts/vt8500_ref.dts                   |   31 ++ 
>  arch/arm/boot/dts/wm8505.dtsi                      |  125 ++++++++ 
>  arch/arm/boot/dts/wm8505_ref.dts                   |   31 ++ 
>  arch/arm/boot/dts/wm8650.dtsi                      |   95 ++++++ 
>  arch/arm/boot/dts/wm8650_ref.dts                   |   31 ++ 
>  arch/arm/mach-vt8500/Kconfig                       |   72 +---- 
>  arch/arm/mach-vt8500/Makefile                      |    9 +- 
>  arch/arm/mach-vt8500/bv07.c                        |   80 ----- 
>  arch/arm/mach-vt8500/common.h                      |   25 ++ 
>  arch/arm/mach-vt8500/devices-vt8500.c              |   91 ------ 
>  arch/arm/mach-vt8500/devices-wm8505.c              |   99 ------ 
>  arch/arm/mach-vt8500/devices.c                     |  270 
> ----------------- 
>  arch/arm/mach-vt8500/devices.h                     |   88 ------ 
>  arch/arm/mach-vt8500/gpio.c                        |  240 --------------- 
>  arch/arm/mach-vt8500/include/mach/restart.h        |    4 +- 
>  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h    |   88 ------ 
>  arch/arm/mach-vt8500/include/mach/vt8500_regs.h    |   79 ----- 
>  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h    |  115 ------- 
>  arch/arm/mach-vt8500/include/mach/wm8505_regs.h    |   78 ----- 
>  arch/arm/mach-vt8500/irq.c                         |  160 +++++----- 
>  arch/arm/mach-vt8500/restart.c                     |   54 ---- 
>  arch/arm/mach-vt8500/timer.c                       |   56 +++- 
>  arch/arm/mach-vt8500/vt8500.c                      |  192 ++++++++++++ 
>  arch/arm/mach-vt8500/wm8505_7in.c                  |   79 ----- 
>  drivers/gpio/Kconfig                               |    6 + 
>  drivers/gpio/Makefile                              |    1 + 
>  drivers/gpio/gpio-vt8500.c                         |  318 
> ++++++++++++++++++++ 
>  drivers/rtc/rtc-vt8500.c                           |    7 + 
>  drivers/tty/serial/vt8500_serial.c                 |    7 + 
>  drivers/usb/host/Kconfig                           |    4 +- 
>  drivers/usb/host/ehci-vt8500.c                     |   24 +- 
>  drivers/usb/host/uhci-hcd.c                        |    5 + 
>  drivers/usb/host/uhci-platform.c                   |  166 ++++++++++ 
>  drivers/video/Kconfig                              |    6 +- 
>  drivers/video/vt8500lcdfb.c                        |   77 ++++- 
>  drivers/video/wm8505fb.c                           |   95 +++++- 
>  drivers/video/wmt_ge_rops.c                        |    7 + 
>  52 files changed, 1674 insertions(+), 1566 deletions(-) 
>  create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt 
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/usb/platform-uhci.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/video/via,vt8500-fb.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt 
>  create mode 100644 
> Documentation/devicetree/bindings/video/wm,wm8505-fb.txt 
>  create mode 100644 arch/arm/boot/dts/vt8500.dtsi 
>  create mode 100644 arch/arm/boot/dts/vt8500_ref.dts 
>  create mode 100644 arch/arm/boot/dts/wm8505.dtsi 
>  create mode 100644 arch/arm/boot/dts/wm8505_ref.dts 
>  create mode 100644 arch/arm/boot/dts/wm8650.dtsi 
>  create mode 100644 arch/arm/boot/dts/wm8650_ref.dts 
>  delete mode 100644 arch/arm/mach-vt8500/bv07.c 
>  create mode 100644 arch/arm/mach-vt8500/common.h 
>  delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c 
>  delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c 
>  delete mode 100644 arch/arm/mach-vt8500/devices.c 
>  delete mode 100644 arch/arm/mach-vt8500/devices.h 
>  delete mode 100644 arch/arm/mach-vt8500/gpio.c 
>  delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h 
>  delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h 
>  delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h 
>  delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h 
>  delete mode 100644 arch/arm/mach-vt8500/restart.c 
>  create mode 100644 arch/arm/mach-vt8500/vt8500.c 
>  delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c 
>  create mode 100644 drivers/gpio/gpio-vt8500.c 
>  create mode 100644 drivers/usb/host/uhci-platform.c 
>
> -- 
> 1.7.9.5 
>
>
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From jason at lakedaemon.net  Sat Aug 18 22:06:08 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 18 Aug 2012 22:06:08 -0400
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support
 Patch v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
Message-ID: <20120819020607.GZ22226@titan.lakedaemon.net>

You're so close!

Your subject line should be "[PATCH] ARM: Kirkwood: Iomega ix2-200 DT
support"

Also, please add a short description of the device and a link to iomega
page describing it to the commit message (should start on the third line
of the commit message, above the Signed-off-by:).

On Fri, Aug 17, 2012 at 10:56:14AM +0100, Alan M Butler wrote:

VVVVVVV--- This is where the signed-off-by goes, not at the end.

> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
> 
> ---
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>  arch/arm/mach-kirkwood/Makefile               |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h               |    6 ++
>  7 files changed, 203 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> 
> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> new file mode 100644
> index 0000000..821a76b
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> @@ -0,0 +1,105 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "Iomega StorCenter ix2-200";
> +	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x10000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk coherent_pool=1M";

Please remove 'coherent_pool=1M' that's a diagnosis tool, we still need
to get to the bottom of what that fixed.

> +	};
> +
> +	ocp at f1000000 {
> +		i2c at 11000 {
> +			status = "okay";
> +
> +			lm63: lm63 at 4c {
> +				compatible = "national,lm63";
> +				reg = <0x4c>;
> +			};
> +		};
> +
> +		serial at 12000 {
> +			clock-frequency = <200000000>;
> +			status = "ok";
> +		};
> +
> +		nand at 3000000 {
> +			status = "okay";
> +
> +			partition at 0 {
> +				label = "u-boot";
> +				reg = <0x0000000 0x100000>;
> +				read-only;
> +			};
> +
> +			partition at a0000 {
> +				label = "env";
> +				reg = <0xa0000 0x20000>;
> +				read-only;
> +			};
> +
> +			partition at 100000 {
> +				label = "uImage";
> +				reg = <0x100000 0x300000>;
> +			};
> +
> +			partition at 400000 {
> +				label = "uInitrd";
> +				reg = <0x540000 0x1000000>;
> +			};
> +		};
> +		sata at 80000 {
> +			status = "okay";
> +			nr-ports = <2>;
> +		};
> +
> +	};
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		power_led {
> +			label = "status:white:power_led";
> +			gpios = <&gpio0 16 0>;
> +			linux,default-trigger = "default-on";
> +		};
> +		health_led1 {
> +			label = "status:red:health_led";
> +			gpios = <&gpio1 5 0>;
> +		};
> +		health_led2 {
> +			label = "status:white:health_led";
> +			gpios = <&gpio1 4 0>;
> +		};
> +		backup_led {
> +			label = "status:blue:backup_led";
> +			gpios = <&gpio0 15 0>;
> +		};
> +	};
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		Power {
> +			label = "Power Button";
> +			linux,code = <116>;
> +			gpios = <&gpio0 14 1>;
> +		};
> +		Reset {
> +			label = "Reset Button";
> +			linux,code = <0x198>;
> +			gpios = <&gpio0 12 1>;
> +		};
> +		OTB {
> +			label = "OTB Button";
> +			linux,code = <133>;
> +			gpios = <&gpio1 3 1>;
> +		};
> +	};

Did Fabio's patch fix gpio-keys?  If so, please list that as a
dependency below the '---', ie 3 lines below the Signed-off-by:.
Include the link he supplied with that comment.

> +};
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index ca5c15a..bee8451 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -195,6 +195,13 @@ config MACH_T5325
>  	  Say 'Y' here if you want your kernel to support the
>  	  HP t5325 Thin Client.
>  
> +config MACH_IOMEGA_IX2_200_DT
> +	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Iomega StorCenter ix2-200 (Flattened Device Tree).
> +
>  endmenu
>  
>  endif
> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
> index 055c85a..f5484dc 100644
> --- a/arch/arm/mach-kirkwood/Makefile
> +++ b/arch/arm/mach-kirkwood/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
>  obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
>  obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
>  obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index 2a576ab..f8ef771 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index e4eb450..9b3ec17 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>  	if (of_machine_is_compatible("buffalo,lsxl"))
>  		lsxl_init();
>  
> +	if (of_machine_is_compatible("iom,ix2-200"))
> +		iomega_ix2_200_init();
> +
>  	of_platform_populate(NULL, kirkwood_dt_match_table,
>  			     kirkwood_auxdata_lookup, NULL);
>  }
> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>  	"qnap,ts219",
>  	"seagate,goflexnet",
>  	"buffalo,lsxl",
> +	"iom,ix2-200",
>  	NULL
>  };
>  
> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> new file mode 100644
> index 0000000..0c78752
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> @@ -0,0 +1,79 @@
> +/*
> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> + *
> + * Iomega StorCenter ix2-200
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/irq.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/ata_platform.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/ethtool.h>
> +#include <net/dsa.h>
> +#include <linux/gpio.h>
> +#include <linux/leds.h>
> +#include <linux/i2c.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <mach/kirkwood.h>
> +#include "common.h"
> +#include "mpp.h"
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> +	.phy_addr       = MV643XX_ETH_PHY_NONE,
> +	.speed          = SPEED_1000,
> +	.duplex         = DUPLEX_FULL,
> +};
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
> +};
> +
> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
> +	MPP12_GPIO,			/* Reset Button */
> +	MPP14_GPIO,			/* Power Button */
> +	MPP15_GPIO,			/* Backup LED (blue) */
> +	MPP16_GPIO,			/* Power LED (white) */
> +	MPP35_GPIO,			/* OTB Button */
> +	MPP36_GPIO,			/* Rebuild LED (white) */
> +	MPP37_GPIO,			/* Health LED (red) */
> +	MPP38_GPIO,			/* SATA LED brightness control 1 */
> +	MPP39_GPIO,			/* SATA LED brightness control 2 */
> +	MPP40_GPIO,			/* Backup LED brightness control 1 */
> +	MPP41_GPIO,			/* Backup LED brightness control 2 */
> +	MPP42_GPIO,			/* Power LED brightness control 1 */
> +	MPP43_GPIO,			/* Power LED brightness control 2 */
> +	MPP44_GPIO,			/* Health LED brightness control 1 */
> +	MPP45_GPIO,			/* Health LED brightness control 2 */
> +	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
> +	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
> +	0
> +};
> +
> +void __init iomega_ix2_200_init(void)
> +{
> +	/*
> +	 * Basic setup. Needs to be called early.
> +	 */
> +	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
> +
> +	kirkwood_ehci_init();
> +
> +	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
> +	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
> +}
> +static int __init iomega_ix2_200_pci_init(void)
> +{
> +	if (of_machine_is_compatible("iom,ix2-200"))
> +		kirkwood_pcie_init(KW_PCIE0);
> +	return 0;
> +}
> +subsys_initcall(iomega_ix2_200_pci_init);
> +
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index 304dd1a..d5d4064 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -94,6 +94,12 @@ void lsxl_init(void);
>  static inline void lsxl_init(void) {};
>  #endif
>  
> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
> +void iomega_ix2_200_init(void);
> +#else
> +static inline void iomega_ix2_200_init(void) {};
> +#endif
> +
>  /* early init functions not converted to fdt yet */
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

This is the wrong place for the Signed-off-by:, please see my comments,
above.  If anyone tries to apply this patch it will fail because git or
patch will think the sob is a line of context.  There won't be a match,
so it will fail.

hth,

Jason.


From jason at lakedaemon.net  Sat Aug 18 21:23:03 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 18 Aug 2012 21:23:03 -0400
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120817152156.4d91ba16@skate>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
 <20120817152156.4d91ba16@skate>
Message-ID: <20120819012303.GX22226@titan.lakedaemon.net>

On Fri, Aug 17, 2012 at 03:21:56PM +0200, Thomas Petazzoni wrote:
> Le Thu, 16 Aug 2012 14:37:08 -0400,
> Jason Cooper <jason at lakedaemon.net> a ?crit :
> 
> > > Whole series applied to:
> > > 
> > > git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
> > 
> > I'm getting the following build error with orion_nand enabled:
> > 
> >   CC      drivers/mtd/nand/orion_nand.o
> > drivers/mtd/nand/orion_nand.c:24:27: fatal error: mach/hardware.h: No
> > such file or directory
> > compilation terminated.
> 
> Are you perhaps trying to enable the orion_nand driver for a mach-mvebu
> platform (Armada 370 or XP)? If it's the case, then yes, this build
> breakage is expected: we haven't enabled any of the I/O for now, so we
> don't have hardware.h yet. This is not something that is broken due to
> the address decoding changes.

Ok, I've added Arnd and Olof to the CC.  The above is exactly what I
did.

Arnd, how extensive is the 'make randconfig' testing in next?  Is this
something that needs to be fixed before we push?  I found it by a fluke,
but the right randconfig would light it up as well.

thx,

Jason.


From shmulik.ladkani at gmail.com  Sun Aug 19 03:20:43 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 19 Aug 2012 10:20:43 +0300
Subject: [PATCH 2/8] UBI: separate bad_peb_limit in a function
In-Reply-To: <1345214124-5478-3-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-3-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120819102043.421db2aa@pixies.home.jungo.com>

On Fri, 17 Aug 2012 16:35:18 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
> No functional changes here, just to prepare for next patch.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Reviewed-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>


From alanbutty12 at gmail.com  Sun Aug 19 04:45:28 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Sun, 19 Aug 2012 09:45:28 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <20120819020607.GZ22226@titan.lakedaemon.net>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
Message-ID: <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>

On 19 August 2012 03:06, Jason Cooper <jason at lakedaemon.net> wrote:
> You're so close!
>
> Your subject line should be "[PATCH] ARM: Kirkwood: Iomega ix2-200 DT
> support"
>
> Also, please add a short description of the device and a link to iomega
> page describing it to the commit message (should start on the third line
> of the commit message, above the Signed-off-by:).
>
> On Fri, Aug 17, 2012 at 10:56:14AM +0100, Alan M Butler wrote:
>
> VVVVVVV--- This is where the signed-off-by goes, not at the end.
>
>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>>
>> ---
>>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
>>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>>  arch/arm/mach-kirkwood/Makefile               |    1 +
>>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
>>  arch/arm/mach-kirkwood/common.h               |    6 ++
>>  7 files changed, 203 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>
>> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> new file mode 100644
>> index 0000000..821a76b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>> @@ -0,0 +1,105 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +     model = "Iomega StorCenter ix2-200";
>> +     compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>> +
>> +     memory {
>> +             device_type = "memory";
>> +             reg = <0x00000000 0x10000000>;
>> +     };
>> +
>> +     chosen {
>> +             bootargs = "console=ttyS0,115200n8 earlyprintk coherent_pool=1M";
>
> Please remove 'coherent_pool=1M' that's a diagnosis tool, we still need
> to get to the bottom of what that fixed.
>
>> +     };
>> +
>> +     ocp at f1000000 {
>> +             i2c at 11000 {
>> +                     status = "okay";
>> +
>> +                     lm63: lm63 at 4c {
>> +                             compatible = "national,lm63";
>> +                             reg = <0x4c>;
>> +                     };
>> +             };
>> +
>> +             serial at 12000 {
>> +                     clock-frequency = <200000000>;
>> +                     status = "ok";
>> +             };
>> +
>> +             nand at 3000000 {
>> +                     status = "okay";
>> +
>> +                     partition at 0 {
>> +                             label = "u-boot";
>> +                             reg = <0x0000000 0x100000>;
>> +                             read-only;
>> +                     };
>> +
>> +                     partition at a0000 {
>> +                             label = "env";
>> +                             reg = <0xa0000 0x20000>;
>> +                             read-only;
>> +                     };
>> +
>> +                     partition at 100000 {
>> +                             label = "uImage";
>> +                             reg = <0x100000 0x300000>;
>> +                     };
>> +
>> +                     partition at 400000 {
>> +                             label = "uInitrd";
>> +                             reg = <0x540000 0x1000000>;
>> +                     };
>> +             };
>> +             sata at 80000 {
>> +                     status = "okay";
>> +                     nr-ports = <2>;
>> +             };
>> +
>> +     };
>> +     gpio-leds {
>> +             compatible = "gpio-leds";
>> +
>> +             power_led {
>> +                     label = "status:white:power_led";
>> +                     gpios = <&gpio0 16 0>;
>> +                     linux,default-trigger = "default-on";
>> +             };
>> +             health_led1 {
>> +                     label = "status:red:health_led";
>> +                     gpios = <&gpio1 5 0>;
>> +             };
>> +             health_led2 {
>> +                     label = "status:white:health_led";
>> +                     gpios = <&gpio1 4 0>;
>> +             };
>> +             backup_led {
>> +                     label = "status:blue:backup_led";
>> +                     gpios = <&gpio0 15 0>;
>> +             };
>> +     };
>> +     gpio-keys {
>> +             compatible = "gpio-keys";
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             Power {
>> +                     label = "Power Button";
>> +                     linux,code = <116>;
>> +                     gpios = <&gpio0 14 1>;
>> +             };
>> +             Reset {
>> +                     label = "Reset Button";
>> +                     linux,code = <0x198>;
>> +                     gpios = <&gpio0 12 1>;
>> +             };
>> +             OTB {
>> +                     label = "OTB Button";
>> +                     linux,code = <133>;
>> +                     gpios = <&gpio1 3 1>;
>> +             };
>> +     };
>
> Did Fabio's patch fix gpio-keys?  If so, please list that as a
> dependency below the '---', ie 3 lines below the Signed-off-by:.
> Include the link he supplied with that comment.
>
>> +};
>> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
>> index ca5c15a..bee8451 100644
>> --- a/arch/arm/mach-kirkwood/Kconfig
>> +++ b/arch/arm/mach-kirkwood/Kconfig
>> @@ -195,6 +195,13 @@ config MACH_T5325
>>         Say 'Y' here if you want your kernel to support the
>>         HP t5325 Thin Client.
>>
>> +config MACH_IOMEGA_IX2_200_DT
>> +     bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
>> +     select ARCH_KIRKWOOD_DT
>> +     help
>> +       Say 'Y' here if you want your kernel to support the
>> +       Iomega StorCenter ix2-200 (Flattened Device Tree).
>> +
>>  endmenu
>>
>>  endif
>> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
>> index 055c85a..f5484dc 100644
>> --- a/arch/arm/mach-kirkwood/Makefile
>> +++ b/arch/arm/mach-kirkwood/Makefile
>> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)                += board-ib62x0.o
>>  obj-$(CONFIG_MACH_TS219_DT)          += board-ts219.o tsx1x-common.o
>>  obj-$(CONFIG_MACH_GOFLEXNET_DT)              += board-goflexnet.o
>>  obj-$(CONFIG_MACH_LSXL_DT)           += board-lsxl.o
>> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
>> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
>> index 2a576ab..f8ef771 100644
>> --- a/arch/arm/mach-kirkwood/Makefile.boot
>> +++ b/arch/arm/mach-kirkwood/Makefile.boot
>> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb
>>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
>> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
>> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
>> index e4eb450..9b3ec17 100644
>> --- a/arch/arm/mach-kirkwood/board-dt.c
>> +++ b/arch/arm/mach-kirkwood/board-dt.c
>> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>>       if (of_machine_is_compatible("buffalo,lsxl"))
>>               lsxl_init();
>>
>> +     if (of_machine_is_compatible("iom,ix2-200"))
>> +             iomega_ix2_200_init();
>> +
>>       of_platform_populate(NULL, kirkwood_dt_match_table,
>>                            kirkwood_auxdata_lookup, NULL);
>>  }
>> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>>       "qnap,ts219",
>>       "seagate,goflexnet",
>>       "buffalo,lsxl",
>> +     "iom,ix2-200",
>>       NULL
>>  };
>>
>> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> new file mode 100644
>> index 0000000..0c78752
>> --- /dev/null
>> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> @@ -0,0 +1,79 @@
>> +/*
>> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> + *
>> + * Iomega StorCenter ix2-200
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/irq.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/ata_platform.h>
>> +#include <linux/mv643xx_eth.h>
>> +#include <linux/ethtool.h>
>> +#include <net/dsa.h>
>> +#include <linux/gpio.h>
>> +#include <linux/leds.h>
>> +#include <linux/i2c.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <mach/kirkwood.h>
>> +#include "common.h"
>> +#include "mpp.h"
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
>> +     .phy_addr       = MV643XX_ETH_PHY_NONE,
>> +     .speed          = SPEED_1000,
>> +     .duplex         = DUPLEX_FULL,
>> +};
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
>> +     .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
>> +};
>> +
>> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
>> +     MPP12_GPIO,                     /* Reset Button */
>> +     MPP14_GPIO,                     /* Power Button */
>> +     MPP15_GPIO,                     /* Backup LED (blue) */
>> +     MPP16_GPIO,                     /* Power LED (white) */
>> +     MPP35_GPIO,                     /* OTB Button */
>> +     MPP36_GPIO,                     /* Rebuild LED (white) */
>> +     MPP37_GPIO,                     /* Health LED (red) */
>> +     MPP38_GPIO,                     /* SATA LED brightness control 1 */
>> +     MPP39_GPIO,                     /* SATA LED brightness control 2 */
>> +     MPP40_GPIO,                     /* Backup LED brightness control 1 */
>> +     MPP41_GPIO,                     /* Backup LED brightness control 2 */
>> +     MPP42_GPIO,                     /* Power LED brightness control 1 */
>> +     MPP43_GPIO,                     /* Power LED brightness control 2 */
>> +     MPP44_GPIO,                     /* Health LED brightness control 1 */
>> +     MPP45_GPIO,                     /* Health LED brightness control 2 */
>> +     MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
>> +     MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
>> +     0
>> +};
>> +
>> +void __init iomega_ix2_200_init(void)
>> +{
>> +     /*
>> +      * Basic setup. Needs to be called early.
>> +      */
>> +     kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
>> +
>> +     kirkwood_ehci_init();
>> +
>> +     kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
>> +     kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
>> +}
>> +static int __init iomega_ix2_200_pci_init(void)
>> +{
>> +     if (of_machine_is_compatible("iom,ix2-200"))
>> +             kirkwood_pcie_init(KW_PCIE0);
>> +     return 0;
>> +}
>> +subsys_initcall(iomega_ix2_200_pci_init);
>> +
>> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
>> index 304dd1a..d5d4064 100644
>> --- a/arch/arm/mach-kirkwood/common.h
>> +++ b/arch/arm/mach-kirkwood/common.h
>> @@ -94,6 +94,12 @@ void lsxl_init(void);
>>  static inline void lsxl_init(void) {};
>>  #endif
>>
>> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
>> +void iomega_ix2_200_init(void);
>> +#else
>> +static inline void iomega_ix2_200_init(void) {};
>> +#endif
>> +
>>  /* early init functions not converted to fdt yet */
>>  char *kirkwood_id(void);
>>  void kirkwood_l2_init(void);
>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>
> This is the wrong place for the Signed-off-by:, please see my comments,
> above.  If anyone tries to apply this patch it will fail because git or
> patch will think the sob is a line of context.  There won't be a match,
> so it will fail.
>
> hth,
>
> Jason.

yeah 2 seconds after i sent the patch i noticed i forgot to remove the
coherent_pool line and i think i sent a v3 with it removed but i will
need to do a v4 and fix what you told me here. and i think i told
fabio that it did not fix the keys however it did allow the kernel to
boot with no panics but the keys still did not work so there is still
something small thats missing or broken in his gpio file i think.

But the patch as is works on 3.6-rc1 with the buttons and leds. If i
get a chance i will try with his patch again later today. Should i
remake the patch on 3.6-rc2 so to be sure it applies cleanly?

Thanks.

p.s Do i send the updated patch directly to you and andrew or to the
list and just cc you both? Still getting used to this mailing list and
submitting a patch thing.


From Julia.Lawall at lip6.fr  Sun Aug 19 04:44:30 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 19 Aug 2012 10:44:30 +0200
Subject: [PATCH 14/14] drivers/spi/spi-s3c24xx.c: fix error return code
In-Reply-To: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Initialize return variable before exiting on an error path.

A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)

// <smpl>
(
if at p1 (\(ret < 0\|ret != 0\))
 { ... return ret; }
|
ret at p1 = 0
)
... when != ret = e1
    when != &ret
*if(...)
{
  ... when != ret = e2
      when forall
 return ret;
}

// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
Perhaps -EINVAL is not the right value in this case.

 drivers/spi/spi-s3c24xx.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 8ee7d79..a2a080b 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -611,6 +611,7 @@ static int __devinit s3c24xx_spi_probe(struct platform_device *pdev)
 	if (!pdata->set_cs) {
 		if (pdata->pin_cs < 0) {
 			dev_err(&pdev->dev, "No chipselect pin\n");
+			err = -EINVAL;
 			goto err_register;
 		}
 



From shmulik.ladkani at gmail.com  Sun Aug 19 05:01:17 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 19 Aug 2012 12:01:17 +0300
Subject: [PATCH 4/8] UBI: prepare for max_beb_per1024 module parameter
 addition
In-Reply-To: <1345214124-5478-5-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-5-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120819120117.0d47ec6c@pixies.home.jungo.com>

On Fri, 17 Aug 2012 16:35:20 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
> This patch prepare the way for the addition of max_beb_per1024 module
> parameter.
> There's no functional change.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Reviewed-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>


From shmulik.ladkani at gmail.com  Sun Aug 19 05:08:04 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 19 Aug 2012 12:08:04 +0300
Subject: [PATCH 5/8] UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
In-Reply-To: <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120819120804.15c33931@pixies.home.jungo.com>

Hi Richard,

On Fri, 17 Aug 2012 16:35:21 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
> +	/*
> +	 * A value of 0 is forced to the default value to keep the same
> +	 * behavior between ubiattach command and module parameter
> +	 */

Minor thing.

Since the module parameter is not yet introduced (only in a later
patch), and since last part of sentence isn't that important, I would
simply state:

+	 * Use the default if max_beb_per1024 isn't provided.

or alike.

Regards,
Shmulik


From shmulik.ladkani at gmail.com  Sun Aug 19 05:26:34 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 19 Aug 2012 12:26:34 +0300
Subject: [PATCH 6/8] UBI: replace MTD_UBI_BEB_LIMIT with module parameter
In-Reply-To: <1345214124-5478-7-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-7-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120819122634.252f1ea5@pixies.home.jungo.com>

Hi Richard,

On Fri, 17 Aug 2012 16:35:22 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
> +		      "MTD devices may be specified by their number, name, or path to the MTD character device node.\n"
> +		      "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0 or not set)\n"
> +		      "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value ("
> +		      __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0 or not set)\n"

Looks like "mtd=/dev/mtd1,,25" is invalid, although we state "default
value if 0 or not set".

Also, lines are exceeding 80 chars, not sure this is more readable than
if they were broken.

Regards,
Shmulik


From stigge at antcom.de  Sun Aug 19 07:04:29 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 19 Aug 2012 13:04:29 +0200
Subject: [PATCH] USB: isp1301: Remove unused static array and define
Message-ID: <1345374269-5471-1-git-send-email-stigge@antcom.de>

This patch removes an unused statically defined array and an associated #define.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
Applies to v3.6-rc2

 drivers/usb/phy/isp1301.c |    6 ------
 1 file changed, 6 deletions(-)

--- linux-2.6.orig/drivers/usb/phy/isp1301.c
+++ linux-2.6/drivers/usb/phy/isp1301.c
@@ -15,12 +15,6 @@
 
 #define DRV_NAME		"isp1301"
 
-#define ISP1301_I2C_ADDR	0x2C
-
-static const unsigned short normal_i2c[] = {
-	ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END
-};
-
 static const struct i2c_device_id isp1301_id[] = {
 	{ "isp1301", 0 },
 	{ }


From shawn.guo at linaro.org  Sun Aug 19 10:05:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 19 Aug 2012 22:05:25 +0800
Subject: [PATCH 3/4] clk: mxs: replace imx28 clk_register_clkdev with clock DT
 lookup
In-Reply-To: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345385125-15262-1-git-send-email-shawn.guo@linaro.org>

It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx28 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx28-clock.txt      |  100 ++++++++++++++++++
 arch/arm/boot/dts/imx28.dtsi                       |  100 ++++++++++++++++++-
 drivers/clk/mxs/clk-imx28.c                        |  109 +------------------
 3 files changed, 204 insertions(+), 105 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx28-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
new file mode 100644
index 0000000..85b72e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -0,0 +1,100 @@
+* Clock bindings for Freescale i.MX28
+
+Required properties:
+- compatible: Should be "fsl,imx28-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clock-output-names: A list of clock output names that i.MX28 CLKCTRL
+  provides.  The full list of all valid clock names and IDs is below.
+
+	Name		ID
+	------------------
+	ref_xtal	0
+	pll0		1
+	pll1		2
+	pll2		3
+	ref_cpu		4
+	ref_emi		5
+	ref_io0		6
+	ref_io1		7
+	ref_pix		8
+	ref_hsadc	9
+	ref_gpmi	10
+	saif0_sel	11
+	saif1_sel	12
+	gpmi_sel	13
+	ssp0_sel	14
+	ssp1_sel	15
+	ssp2_sel	16
+	ssp3_sel	17
+	emi_sel		18
+	etm_sel		19
+	lcdif_sel	20
+	cpu		21
+	ptp_sel		22
+	cpu_pll		23
+	cpu_xtal	24
+	hbus		25
+	xbus		26
+	ssp0_div	27
+	ssp1_div	28
+	ssp2_div	29
+	ssp3_div	30
+	gpmi_div	31
+	emi_pll		32
+	emi_xtal	33
+	lcdif_div	34
+	etm_div		35
+	ptp		36
+	saif0_div	37
+	saif1_div	38
+	clk32k_div	39
+	rtc		40
+	lradc		41
+	spdif_div	42
+	clk32k		43
+	pwm		44
+	uart		45
+	ssp0		46
+	ssp1		47
+	ssp2		48
+	ssp3		49
+	gpmi		50
+	spdif		51
+	emi		52
+	saif0		53
+	saif1		54
+	lcdif		55
+	etm		56
+	fec		57
+	can0		58
+	can1		59
+	usb0		60
+	usb1		61
+	usb0_pwr	62
+	usb1_pwr	63
+	enet_out	64
+
+  The ID will be used by clock consumer in the first cell of "clocks"
+  phandle to specify the desired clock.
+
+Examples:
+
+clks: clkctrl at 80040000 {
+	compatible = "fsl,imx28-clkctrl";
+	reg = <0x80040000 0x2000>;
+	#clock-cells = <1>;
+	clock-output-names =
+		...
+		"uart",		/* 45 */
+		...
+		"end_of_list";
+};
+
+auart0: serial at 8006a000 {
+	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+	reg = <0x8006a000 0x2000>;
+	interrupts = <112 70 71>;
+	clocks = <&clks 45>;
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e2240da..2e3ec2e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -65,6 +65,7 @@
 			dma-apbh at 80004000 {
 				compatible = "fsl,imx28-dma-apbh";
 				reg = <0x80004000 0x2000>;
+				clocks = <&clks 25>;
 			};
 
 			perfmon at 80006000 {
@@ -81,6 +82,7 @@
 				reg-names = "gpmi-nand", "bch";
 				interrupts = <88>, <41>;
 				interrupt-names = "gpmi-dma", "bch";
+				clocks = <&clks 50>;
 				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -88,6 +90,7 @@
 			ssp0: ssp at 80010000 {
 				reg = <0x80010000 0x2000>;
 				interrupts = <96 82>;
+				clocks = <&clks 46>;
 				fsl,ssp-dma-channel = <0>;
 				status = "disabled";
 			};
@@ -95,6 +98,7 @@
 			ssp1: ssp at 80012000 {
 				reg = <0x80012000 0x2000>;
 				interrupts = <97 83>;
+				clocks = <&clks 47>;
 				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
@@ -102,6 +106,7 @@
 			ssp2: ssp at 80014000 {
 				reg = <0x80014000 0x2000>;
 				interrupts = <98 84>;
+				clocks = <&clks 48>;
 				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
@@ -109,6 +114,7 @@
 			ssp3: ssp at 80016000 {
 				reg = <0x80016000 0x2000>;
 				interrupts = <99 85>;
+				clocks = <&clks 49>;
 				fsl,ssp-dma-channel = <3>;
 				status = "disabled";
 			};
@@ -523,6 +529,7 @@
 			dma-apbx at 80024000 {
 				compatible = "fsl,imx28-dma-apbx";
 				reg = <0x80024000 0x2000>;
+				clocks = <&clks 26>;
 			};
 
 			dcp at 80028000 {
@@ -551,6 +558,7 @@
 				compatible = "fsl,imx28-lcdif";
 				reg = <0x80030000 0x2000>;
 				interrupts = <38 86>;
+				clocks = <&clks 55>;
 				status = "disabled";
 			};
 
@@ -558,6 +566,7 @@
 				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
 				reg = <0x80032000 0x2000>;
 				interrupts = <8>;
+				clocks = <&clks 58>;
 				status = "disabled";
 			};
 
@@ -565,6 +574,7 @@
 				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
 				reg = <0x80034000 0x2000>;
 				interrupts = <9>;
+				clocks = <&clks 59>;
 				status = "disabled";
 			};
 
@@ -611,15 +621,84 @@
 			reg = <0x80040000 0x40000>;
 			ranges;
 
-			clkctl at 80040000 {
+			clks: clkctrl at 80040000 {
+				compatible = "fsl,imx28-clkctrl";
 				reg = <0x80040000 0x2000>;
-				status = "disabled";
+				#clock-cells = <1>;
+				clock-output-names =
+					"ref_xtal",	/* 0 */
+					"pll0",		/* 1 */
+					"pll1",		/* 2 */
+					"pll2",		/* 3 */
+					"ref_cpu",	/* 4 */
+					"ref_emi",	/* 5 */
+					"ref_io0",	/* 6 */
+					"ref_io1",	/* 7 */
+					"ref_pix",	/* 8 */
+					"ref_hsadc",	/* 9 */
+					"ref_gpmi",	/* 10 */
+					"saif0_sel",	/* 11 */
+					"saif1_sel",	/* 12 */
+					"gpmi_sel",	/* 13 */
+					"ssp0_sel",	/* 14 */
+					"ssp1_sel",	/* 15 */
+					"ssp2_sel",	/* 16 */
+					"ssp3_sel",	/* 17 */
+					"emi_sel",	/* 18 */
+					"etm_sel",	/* 19 */
+					"lcdif_sel",	/* 20 */
+					"cpu",		/* 21 */
+					"ptp_sel",	/* 22 */
+					"cpu_pll",	/* 23 */
+					"cpu_xtal",	/* 24 */
+					"hbus",		/* 25 */
+					"xbus",		/* 26 */
+					"ssp0_div",	/* 27 */
+					"ssp1_div",	/* 28 */
+					"ssp2_div",	/* 29 */
+					"ssp3_div",	/* 30 */
+					"gpmi_div",	/* 31 */
+					"emi_pll",	/* 32 */
+					"emi_xtal",	/* 33 */
+					"lcdif_div",	/* 34 */
+					"etm_div",	/* 35 */
+					"ptp",		/* 36 */
+					"saif0_div",	/* 37 */
+					"saif1_div",	/* 38 */
+					"clk32k_div",	/* 39 */
+					"rtc",		/* 40 */
+					"lradc",	/* 41 */
+					"spdif_div",	/* 42 */
+					"clk32k",	/* 43 */
+					"pwm",		/* 44 */
+					"uart",		/* 45 */
+					"ssp0",		/* 46 */
+					"ssp1",		/* 47 */
+					"ssp2",		/* 48 */
+					"ssp3",		/* 49 */
+					"gpmi",		/* 50 */
+					"spdif",	/* 51 */
+					"emi",		/* 52 */
+					"saif0",	/* 53 */
+					"saif1",	/* 54 */
+					"lcdif",	/* 55 */
+					"etm",		/* 56 */
+					"fec",		/* 57 */
+					"can0",		/* 58 */
+					"can1",		/* 59 */
+					"usb0",		/* 60 */
+					"usb1",		/* 61 */
+					"usb0_pwr",	/* 62 */
+					"usb1_pwr",	/* 63 */
+					"enet_out",	/* 64 */
+					"end_of_list";
 			};
 
 			saif0: saif at 80042000 {
 				compatible = "fsl,imx28-saif";
 				reg = <0x80042000 0x2000>;
 				interrupts = <59 80>;
+				clocks = <&clks 53>;
 				fsl,saif-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -633,6 +712,7 @@
 				compatible = "fsl,imx28-saif";
 				reg = <0x80046000 0x2000>;
 				interrupts = <58 81>;
+				clocks = <&clks 54>;
 				fsl,saif-dma-channel = <5>;
 				status = "disabled";
 			};
@@ -680,6 +760,7 @@
 			pwm: pwm at 80064000 {
 				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
 				reg = <0x80064000 0x2000>;
+				clocks = <&clks 44>;
 				#pwm-cells = <2>;
 				fsl,pwm-number = <8>;
 				status = "disabled";
@@ -694,6 +775,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006a000 0x2000>;
 				interrupts = <112 70 71>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -701,6 +783,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006c000 0x2000>;
 				interrupts = <113 72 73>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -708,6 +791,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006e000 0x2000>;
 				interrupts = <114 74 75>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -715,6 +799,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x80070000 0x2000>;
 				interrupts = <115 76 77>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -722,6 +807,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x80072000 0x2000>;
 				interrupts = <116 78 79>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -729,18 +815,22 @@
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x80074000 0x1000>;
 				interrupts = <47>;
+				clocks = <&clks 45>, <&clks 26>;
+				clock-names = "uart", "apb_pclk";
 				status = "disabled";
 			};
 
 			usbphy0: usbphy at 8007c000 {
 				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
 				reg = <0x8007c000 0x2000>;
+				clocks = <&clks 62>;
 				status = "disabled";
 			};
 
 			usbphy1: usbphy at 8007e000 {
 				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
 				reg = <0x8007e000 0x2000>;
+				clocks = <&clks 63>;
 				status = "disabled";
 			};
 		};
@@ -757,6 +847,7 @@
 			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
 			reg = <0x80080000 0x10000>;
 			interrupts = <93>;
+			clocks = <&clks 60>;
 			fsl,usbphy = <&usbphy0>;
 			status = "disabled";
 		};
@@ -765,6 +856,7 @@
 			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
 			reg = <0x80090000 0x10000>;
 			interrupts = <92>;
+			clocks = <&clks 61>;
 			fsl,usbphy = <&usbphy1>;
 			status = "disabled";
 		};
@@ -778,6 +870,8 @@
 			compatible = "fsl,imx28-fec";
 			reg = <0x800f0000 0x4000>;
 			interrupts = <101>;
+			clocks = <&clks 57>, <&clks 57>;
+			clock-names = "ipg", "ahb";
 			status = "disabled";
 		};
 
@@ -785,6 +879,8 @@
 			compatible = "fsl,imx28-fec";
 			reg = <0x800f4000 0x4000>;
 			interrupts = <102>;
+			clocks = <&clks 57>, <&clks 57>;
+			clock-names = "ipg", "ahb";
 			status = "disabled";
 		};
 
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67..3f62e23 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx28.h>
 #include "clk.h"
@@ -120,90 +121,6 @@ static void __init clk_misc_init(void)
 	writel_relaxed(val, FRAC0);
 }
 
-static struct clk_lookup uart_lookups[] = {
-	{ .dev_id = "duart", },
-	{ .dev_id = "mxs-auart.0", },
-	{ .dev_id = "mxs-auart.1", },
-	{ .dev_id = "mxs-auart.2", },
-	{ .dev_id = "mxs-auart.3", },
-	{ .dev_id = "mxs-auart.4", },
-	{ .dev_id = "8006a000.serial", },
-	{ .dev_id = "8006c000.serial", },
-	{ .dev_id = "8006e000.serial", },
-	{ .dev_id = "80070000.serial", },
-	{ .dev_id = "80072000.serial", },
-	{ .dev_id = "80074000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-	{ .dev_id = "imx28-dma-apbh", },
-	{ .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-	{ .dev_id = "duart", .con_id = "apb_pclk"},
-	{ .dev_id = "80074000.serial", .con_id = "apb_pclk"},
-	{ .dev_id = "imx28-dma-apbx", },
-	{ .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp0_lookups[] = {
-	{ .dev_id = "imx28-mmc.0", },
-	{ .dev_id = "80010000.ssp", },
-};
-
-static struct clk_lookup ssp1_lookups[] = {
-	{ .dev_id = "imx28-mmc.1", },
-	{ .dev_id = "80012000.ssp", },
-};
-
-static struct clk_lookup ssp2_lookups[] = {
-	{ .dev_id = "imx28-mmc.2", },
-	{ .dev_id = "80014000.ssp", },
-};
-
-static struct clk_lookup ssp3_lookups[] = {
-	{ .dev_id = "imx28-mmc.3", },
-	{ .dev_id = "80016000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-	{ .dev_id = "imx28-fb", },
-	{ .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-	{ .dev_id = "imx28-gpmi-nand", },
-	{ .dev_id = "8000c000.gpmi-nand", },
-};
-
-static struct clk_lookup fec_lookups[] = {
-	{ .dev_id = "imx28-fec.0", },
-	{ .dev_id = "imx28-fec.1", },
-	{ .dev_id = "800f0000.ethernet", },
-	{ .dev_id = "800f4000.ethernet", },
-};
-
-static struct clk_lookup can0_lookups[] = {
-	{ .dev_id = "flexcan.0", },
-	{ .dev_id = "80032000.can", },
-};
-
-static struct clk_lookup can1_lookups[] = {
-	{ .dev_id = "flexcan.1", },
-	{ .dev_id = "80034000.can", },
-};
-
-static struct clk_lookup saif0_lookups[] = {
-	{ .dev_id = "mxs-saif.0", },
-	{ .dev_id = "80042000.saif", },
-};
-
-static struct clk_lookup saif1_lookups[] = {
-	{ .dev_id = "mxs-saif.1", },
-	{ .dev_id = "80046000.saif", },
-};
-
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
@@ -235,6 +152,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
 
 int __init mx28_clocks_init(void)
 {
+	struct device_node *np;
 	int i;
 
 	clk_misc_init();
@@ -312,27 +230,12 @@ int __init mx28_clocks_init(void)
 			return PTR_ERR(clks[i]);
 		}
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
+	if (np)
+		of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
+
 	clk_register_clkdev(clks[clk32k], NULL, "timrot");
 	clk_register_clkdev(clks[enet_out], NULL, "enet_out");
-	clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-	clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-	clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-	clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-	clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
-	clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
-	clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
-	clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
-	clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-	clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
-	clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
-	clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
-	clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
-	clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
-	clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
-	clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
-	clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
-	clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
-	clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
-- 
1.7.5.4



From arnd at arndb.de  Sun Aug 19 10:05:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 19 Aug 2012 14:05:24 +0000
Subject: [PATCH 0/6] Integrator devicetree support
In-Reply-To: <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>
References: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
 <201208161344.55723.arnd@arndb.de>
 <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>
Message-ID: <201208191405.25048.arnd@arndb.de>

On Saturday 18 August 2012, Linus Walleij wrote:
> Since we already have CONFIG_USE_OF I think
> CONFIG_USE_ATAGS is more apropriate, but I get the
> idea.

There is both CONFIG_USE_OF and CONFIG_OF. The former is what
a platform selects and it turns on a few other options as well,
while the latter is the one that you typically check in #ifdef.

We might need both of them for ATAG as well, but I think if
we have just one, CONFIG_ATAGS or CONFIG_ATAG would be nicer
because it's slightly shorter.

> So it begins like this:
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..0764ef7 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1907,6 +1907,12 @@ endmenu
> 
>  menu "Boot options"
> 
> +config USE_ATAGS
> +       bool "ATAGS support"
> +       default y
> +       help
> +         Include support for ATAGS-based machine descriptions.
> +
>  config USE_OF
>         bool "Flattened Device Tree support"
>         select OF
> @@ -2110,6 +2116,7 @@ config KEXEC
> 
>  config ATAGS_PROC
>         bool "Export atags in procfs"
> +       depends on USE_ATAGS
>         depends on KEXEC
>         default y
>         help
> 
> But then we hit #ifdeffing and compiling out a lot of dangerous stuff
> in arch/arm/kernel and then I get the creeps. I can try, but I think
> this is typical Nico territory for example...

We don't have to enclose every single usage of ATAGS with this, but
I think it's helpful in platforms that you want to migrate away
from ATAG to DT-only. I think we should also use this method in
mach-ux500, for instance.

Putting MACHINE_START and DT_MACHINE_START inside of CONFIG_ATAG
and CONFIG_OF respectively would help ensure that we don't
accidentally build support for a board that cannot work.

	Arnd


From shawn.guo at linaro.org  Sun Aug 19 10:05:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 19 Aug 2012 22:05:55 +0800
Subject: [PATCH 4/4] clk: mxs: replace imx23 clk_register_clkdev with clock DT
 lookup
In-Reply-To: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345385155-15301-1-git-send-email-shawn.guo@linaro.org>

It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx23 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx23-clock.txt      |   77 ++++++++++++++++++++
 arch/arm/boot/dts/imx23.dtsi                       |   60 +++++++++++++++-
 drivers/clk/mxs/clk-imx23.c                        |   51 ++------------
 3 files changed, 141 insertions(+), 47 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx23-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 0000000..d8e89b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,77 @@
+* Clock bindings for Freescale i.MX23
+
+Required properties:
+- compatible: Should be "fsl,imx23-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clock-output-names: A list of clock output names that i.MX23 CLKCTRL
+  provides.  The full list of all valid clock names and IDs is below.
+
+	Name		ID
+	------------------
+	ref_xtal	0
+	pll		1
+	ref_cpu		2
+	ref_emi		3
+	ref_pix		4
+	ref_io		5
+	saif_sel	6
+	lcdif_sel	7
+	gpmi_sel	8
+	ssp_sel		9
+	emi_sel		10
+	cpu		11
+	etm_sel		12
+	cpu_pll		13
+	cpu_xtal	14
+	hbus		15
+	xbus		16
+	lcdif_div	17
+	ssp_div		18
+	gpmi_div	19
+	emi_pll		20
+	emi_xtal	21
+	etm_div		22
+	saif_div	23
+	clk32k_div	24
+	rtc		25
+	adc		26
+	spdif_div	27
+	clk32k		28
+	dri		29
+	pwm		30
+	filt		31
+	uart		32
+	ssp		33
+	gpmi		34
+	spdif		35
+	emi		36
+	saif		37
+	lcdif		38
+	etm		39
+	usb		40
+	usb_pwr		41
+
+  The ID will be used by clock consumer in the first cell of "clocks"
+  phandle to specify the desired clock.
+
+Examples:
+
+clks: clkctrl at 80040000 {
+	compatible = "fsl,imx23-clkctrl";
+	reg = <0x80040000 0x2000>;
+	#clock-cells = <1>;
+	clock-output-names =
+		...
+		"uart",		/* 32 */
+		...
+		"end_of_list";
+};
+
+auart0: serial at 8006c000 {
+	compatible = "fsl,imx23-auart";
+	reg = <0x8006c000 0x2000>;
+	interrupts = <24 25 23>;
+	clocks = <&clks 32>;
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 9700872..b7b2963 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
 			dma-apbh at 80004000 {
 				compatible = "fsl,imx23-dma-apbh";
 				reg = <0x80004000 0x2000>;
+				clocks = <&clks 15>;
 			};
 
 			ecc at 80008000 {
@@ -67,6 +68,7 @@
 				reg-names = "gpmi-nand", "bch";
 				interrupts = <13>, <56>;
 				interrupt-names = "gpmi-dma", "bch";
+				clocks = <&clks 34>;
 				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -74,6 +76,7 @@
 			ssp0: ssp at 80010000 {
 				reg = <0x80010000 0x2000>;
 				interrupts = <15 14>;
+				clocks = <&clks 33>;
 				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
@@ -291,6 +294,7 @@
 			dma-apbx at 80024000 {
 				compatible = "fsl,imx23-dma-apbx";
 				reg = <0x80024000 0x2000>;
+				clocks = <&clks 16>;
 			};
 
 			dcp at 80028000 {
@@ -317,12 +321,14 @@
 				compatible = "fsl,imx23-lcdif";
 				reg = <0x80030000 2000>;
 				interrupts = <46 45>;
+				clocks = <&clks 38>;
 				status = "disabled";
 			};
 
 			ssp1: ssp at 80034000 {
 				reg = <0x80034000 0x2000>;
 				interrupts = <2 20>;
+				clocks = <&clks 33>;
 				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
@@ -340,9 +346,54 @@
 			reg = <0x80040000 0x40000>;
 			ranges;
 
-			clkctl at 80040000 {
+			clks: clkctrl at 80040000 {
+				compatible = "fsl,imx23-clkctrl";
 				reg = <0x80040000 0x2000>;
-				status = "disabled";
+				#clock-cells = <1>;
+				clock-output-names =
+					"ref_xtal",	/* 0 */
+					"pll",		/* 1 */
+					"ref_cpu",	/* 2 */
+					"ref_emi",	/* 3 */
+					"ref_pix",	/* 4 */
+					"ref_io",	/* 5 */
+					"saif_sel",	/* 6 */
+					"lcdif_sel",	/* 7 */
+					"gpmi_sel",	/* 8 */
+					"ssp_sel",	/* 9 */
+					"emi_sel",	/* 10 */
+					"cpu",		/* 11 */
+					"etm_sel",	/* 12 */
+					"cpu_pll",	/* 13 */
+					"cpu_xtal",	/* 14 */
+					"hbus",		/* 15 */
+					"xbus",		/* 16 */
+					"lcdif_div",	/* 17 */
+					"ssp_div",	/* 18 */
+					"gpmi_div",	/* 19 */
+					"emi_pll",	/* 20 */
+					"emi_xtal",	/* 21 */
+					"etm_div",	/* 22 */
+					"saif_div",	/* 23 */
+					"clk32k_div",	/* 24 */
+					"rtc",		/* 25 */
+					"adc",		/* 26 */
+					"spdif_div",	/* 27 */
+					"clk32k",	/* 28 */
+					"dri",		/* 29 */
+					"pwm",		/* 30 */
+					"filt",		/* 31 */
+					"uart",		/* 32 */
+					"ssp",		/* 33 */
+					"gpmi",		/* 34 */
+					"spdif",	/* 35 */
+					"emi",		/* 36 */
+					"saif",		/* 37 */
+					"lcdif",	/* 38 */
+					"etm",		/* 39 */
+					"usb",		/* 40 */
+					"usb_pwr",	/* 41 */
+					"end_of_list";
 			};
 
 			saif0: saif at 80042000 {
@@ -394,6 +445,7 @@
 			pwm: pwm at 80064000 {
 				compatible = "fsl,imx23-pwm";
 				reg = <0x80064000 0x2000>;
+				clocks = <&clks 30>;
 				#pwm-cells = <2>;
 				fsl,pwm-number = <5>;
 				status = "disabled";
@@ -408,6 +460,7 @@
 				compatible = "fsl,imx23-auart";
 				reg = <0x8006c000 0x2000>;
 				interrupts = <24 25 23>;
+				clocks = <&clks 32>;
 				status = "disabled";
 			};
 
@@ -415,6 +468,7 @@
 				compatible = "fsl,imx23-auart";
 				reg = <0x8006e000 0x2000>;
 				interrupts = <59 60 58>;
+				clocks = <&clks 32>;
 				status = "disabled";
 			};
 
@@ -422,6 +476,8 @@
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x80070000 0x2000>;
 				interrupts = <0>;
+				clocks = <&clks 32>, <&clks 16>;
+				clock-names = "uart", "apb_pclk";
 				status = "disabled";
 			};
 
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0..d1c7cdb 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx23.h>
 #include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
 	__mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
 }
 
-static struct clk_lookup uart_lookups[] = {
-	{ .dev_id = "duart", },
-	{ .dev_id = "mxs-auart.0", },
-	{ .dev_id = "mxs-auart.1", },
-	{ .dev_id = "8006c000.serial", },
-	{ .dev_id = "8006e000.serial", },
-	{ .dev_id = "80070000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-	{ .dev_id = "imx23-dma-apbh", },
-	{ .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-	{ .dev_id = "duart", .con_id = "apb_pclk"},
-	{ .dev_id = "80070000.serial", .con_id = "apb_pclk"},
-	{ .dev_id = "imx23-dma-apbx", },
-	{ .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp_lookups[] = {
-	{ .dev_id = "imx23-mmc.0", },
-	{ .dev_id = "imx23-mmc.1", },
-	{ .dev_id = "80010000.ssp", },
-	{ .dev_id = "80034000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-	{ .dev_id = "imx23-fb", },
-	{ .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-	{ .dev_id = "imx23-gpmi-nand", },
-	{ .dev_id = "8000c000.gpmi-nand", },
-};
-
 static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
@@ -134,6 +97,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
 
 int __init mx23_clocks_init(void)
 {
+	struct device_node *np;
 	int i;
 
 	clk_misc_init();
@@ -188,14 +152,11 @@ int __init mx23_clocks_init(void)
 			return PTR_ERR(clks[i]);
 		}
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
+	if (np)
+		of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
+
 	clk_register_clkdev(clks[clk32k], NULL, "timrot");
-	clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-	clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-	clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-	clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-	clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
-	clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-	clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
-- 
1.7.5.4



From festevam at gmail.com  Sun Aug 19 10:09:05 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 19 Aug 2012 11:09:05 -0300
Subject: [PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration
Message-ID: <1345385346-25412-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/clk-imx35.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb..f7910df 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -230,10 +230,8 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.1");
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
-- 
1.7.9.5



From festevam at gmail.com  Sun Aug 19 10:09:06 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 19 Aug 2012 11:09:06 -0300
Subject: [PATCH 2/2] ARM: clk-imx25: Fix SSI clock registration
In-Reply-To: <1345385346-25412-1-git-send-email-festevam@gmail.com>
References: <1345385346-25412-1-git-send-email-festevam@gmail.com>
Message-ID: <1345385346-25412-2-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/clk-imx25.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index fdd8cc8..5ff9534 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
 	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-- 
1.7.9.5



From arnd at arndb.de  Sun Aug 19 10:16:03 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 19 Aug 2012 14:16:03 +0000
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120819012303.GX22226@titan.lakedaemon.net>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120817152156.4d91ba16@skate> <20120819012303.GX22226@titan.lakedaemon.net>
Message-ID: <201208191416.03873.arnd@arndb.de>

On Sunday 19 August 2012, Jason Cooper wrote:
> On Fri, Aug 17, 2012 at 03:21:56PM +0200, Thomas Petazzoni wrote:
> > Le Thu, 16 Aug 2012 14:37:08 -0400,
> > Jason Cooper <jason at lakedaemon.net> a ?crit :
> > 
> > > > Whole series applied to:
> > > > 
> > > > git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
> > > 
> > > I'm getting the following build error with orion_nand enabled:
> > > 
> > >   CC      drivers/mtd/nand/orion_nand.o
> > > drivers/mtd/nand/orion_nand.c:24:27: fatal error: mach/hardware.h: No
> > > such file or directory
> > > compilation terminated.
> > 
> > Are you perhaps trying to enable the orion_nand driver for a mach-mvebu
> > platform (Armada 370 or XP)? If it's the case, then yes, this build
> > breakage is expected: we haven't enabled any of the I/O for now, so we
> > don't have hardware.h yet. This is not something that is broken due to
> > the address decoding changes.
> 
> Ok, I've added Arnd and Olof to the CC.  The above is exactly what I
> did.
> 
> Arnd, how extensive is the 'make randconfig' testing in next?  Is this
> something that needs to be fixed before we push?  I found it by a fluke,
> but the right randconfig would light it up as well.

If there is a bug you know about, you should fix it. In the above
example, I would guess that you should not actually need to include
mach/hardware.h, so the fix should be simple. In general, we should
eliminate mach/hardware.h where we can and put register locations
into resource, and offsets into the drivers themselves.

	Arnd


From arnd at arndb.de  Sun Aug 19 11:21:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 19 Aug 2012 15:21:37 +0000
Subject: [PATCH 0/3] New algorithm for ASID allocation and rollover
In-Reply-To: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
Message-ID: <201208191521.37460.arnd@arndb.de>

On Wednesday 15 August 2012, Will Deacon wrote:
> After some discussion, it became apparent that tracking the ASIDs
> currently active on the cores in the system means that, on rollover, we
> can automatically reserve those that are in use without having to stop
> the world.

Just a question for my general understanding of how this is done: How do
you know if an ASID is active or not? Do you broadcast flush an address
space completely when the struct mm goes away, or do you keep track of
which CPUs had TLBs in an ASIC when it went away and then flush that ASID
when you reuse it on that CPU?

	Arnd


From shawn.guo at linaro.org  Sun Aug 19 11:26:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 19 Aug 2012 23:26:58 +0800
Subject: imx6q restart is broken
In-Reply-To: <20120817034854.GE24242@S2101-09.ap.freescale.net>
References: <20120808101817.GA14718@S2101-09.ap.freescale.net>
 <50224547.9020000@de.bosch.com> <50232C17.9000700@gmail.com>
 <20120809092021.GQ18957@n2100.arm.linux.org.uk>
 <502BBB43.5010403@gmail.com>
 <20120815214412.GC32560@n2100.arm.linux.org.uk>
 <20120816023109.GH2258@S2101-09.ap.freescale.net>
 <20120816223446.GB15883@n2100.arm.linux.org.uk>
 <20120817034854.GE24242@S2101-09.ap.freescale.net>
Message-ID: <20120819152656.GI24242@S2101-09.ap.freescale.net>

On Fri, Aug 17, 2012 at 11:48:56AM +0800, Shawn Guo wrote:
> > I think what needs to happen here (while we wait) is someone _with_ the
> > problem needs to experiment, and find out how many nops are needed for
> > the DMB not to have much effect in cpu_relax().  If it turns out we just
> > need to put one nop in, then that's not _too_ bad.
> 
> At least, I need to have 5 nops to get rid of the issue, something like
> below.
> 
Russell,

What's your take on this then?

-- 
Regards,
Shawn


From nico at fluxnic.net  Sun Aug 19 11:42:15 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Sun, 19 Aug 2012 11:42:15 -0400 (EDT)
Subject: [PATCH] arm: mm: Fix vmalloc overlap check for !HIGHMEM
In-Reply-To: <1345222980-16965-1-git-send-email-jonathan.austin@arm.com>
References: <1345222980-16965-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <alpine.LFD.2.02.1208191141470.1754@xanadu.home>

On Fri, 17 Aug 2012, Jonathan Austin wrote:

> With !HIGHMEM, sanity_check_meminfo checks for banks that completely or
> partially overlap the vmalloc region. The test for partial overlap checks
> __va(bank->start + bank->size) > vmalloc_min. This is not appropriate if
> there is a non-linear translation between virtual and physical addresses,
> as bank->start + bank->size is actually in the bank following the one being
> interrogated.
> 
> In most cases, even when using SPARSEMEM, this is not problematic as the
> subsequent bank will start at a higher va than the one in question. However
> if the physical to virtual address conversion is not monotonic increasing,
> the incorrect test could result in a bank not being truncated when it
> should be.
> 
> This patch ensures we perform the va-pa conversion on memory from the
> bank we are interested in, not the following one.
> 
> Reported-by: ????????? (Steve) <zhanzhenbo at gmail.com>
> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
> 
> This is modified based on Russell's feedback in the original
> discussion (Why the region area don't decrease 1 in function
> sanity_check_meminfo?)
> 
>  arch/arm/mm/mmu.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 4c2d045..dbd9ff6 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -961,8 +961,8 @@ void __init sanity_check_meminfo(void)
>  		 * Check whether this memory bank would partially overlap
>  		 * the vmalloc area.
>  		 */
> -		if (__va(bank->start + bank->size) > vmalloc_min ||
> -		    __va(bank->start + bank->size) < __va(bank->start)) {
> +		if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
> +		    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
>  			unsigned long newsize = vmalloc_min - __va(bank->start);
>  			printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
>  			       "to -%.8llx (vmalloc region overlap).\n",
> -- 
> 1.7.1
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

From nicolas.pitre at linaro.org  Sun Aug 19 11:52:32 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Sun, 19 Aug 2012 11:52:32 -0400 (EDT)
Subject: [PATCH 0/6] Integrator devicetree support
In-Reply-To: <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>
References: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
 <201208161344.55723.arnd@arndb.de>
 <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208191148520.1754@xanadu.home>

On Sun, 19 Aug 2012, Linus Walleij wrote:

> But then we hit #ifdeffing and compiling out a lot of dangerous stuff
> in arch/arm/kernel and then I get the creeps. I can try, but I think
> this is typical Nico territory for example...

I did post a patch moving all the ATAG stuff to a separate source file a 
while ago, exactly for that purpose.  I should try to dig it out and 
refresh it.


Nicolas


From festevam at gmail.com  Sun Aug 19 13:05:59 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 19 Aug 2012 14:05:59 -0300
Subject: [PATCH v2 2/2] ARM: clk-imx25: Fix SSI clock registration
Message-ID: <1345395959-26978-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Use imx-ssi.1 for ssi2_ipg

 arch/arm/mach-imx/clk-imx25.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index fdd8cc8..5ff9534 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
 	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
 	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
-- 
1.7.9.5



From alanbutty12 at gmail.com  Sun Aug 19 14:03:15 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Sun, 19 Aug 2012 19:03:15 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
Message-ID: <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>

On 19 August 2012 09:45, Alan M Butler <alanbutty12 at gmail.com> wrote:
> On 19 August 2012 03:06, Jason Cooper <jason at lakedaemon.net> wrote:
>> You're so close!
>>
>> Your subject line should be "[PATCH] ARM: Kirkwood: Iomega ix2-200 DT
>> support"
>>
>> Also, please add a short description of the device and a link to iomega
>> page describing it to the commit message (should start on the third line
>> of the commit message, above the Signed-off-by:).
>>
>> On Fri, Aug 17, 2012 at 10:56:14AM +0100, Alan M Butler wrote:
>>
>> VVVVVVV--- This is where the signed-off-by goes, not at the end.
>>
>>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>>>
>>> ---
>>>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
>>>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>>>  arch/arm/mach-kirkwood/Makefile               |    1 +
>>>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>>>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>>>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
>>>  arch/arm/mach-kirkwood/common.h               |    6 ++
>>>  7 files changed, 203 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>>
>>> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>> new file mode 100644
>>> index 0000000..821a76b
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>>> @@ -0,0 +1,105 @@
>>> +/dts-v1/;
>>> +
>>> +/include/ "kirkwood.dtsi"
>>> +
>>> +/ {
>>> +     model = "Iomega StorCenter ix2-200";
>>> +     compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>>> +
>>> +     memory {
>>> +             device_type = "memory";
>>> +             reg = <0x00000000 0x10000000>;
>>> +     };
>>> +
>>> +     chosen {
>>> +             bootargs = "console=ttyS0,115200n8 earlyprintk coherent_pool=1M";
>>
>> Please remove 'coherent_pool=1M' that's a diagnosis tool, we still need
>> to get to the bottom of what that fixed.
>>
>>> +     };
>>> +
>>> +     ocp at f1000000 {
>>> +             i2c at 11000 {
>>> +                     status = "okay";
>>> +
>>> +                     lm63: lm63 at 4c {
>>> +                             compatible = "national,lm63";
>>> +                             reg = <0x4c>;
>>> +                     };
>>> +             };
>>> +
>>> +             serial at 12000 {
>>> +                     clock-frequency = <200000000>;
>>> +                     status = "ok";
>>> +             };
>>> +
>>> +             nand at 3000000 {
>>> +                     status = "okay";
>>> +
>>> +                     partition at 0 {
>>> +                             label = "u-boot";
>>> +                             reg = <0x0000000 0x100000>;
>>> +                             read-only;
>>> +                     };
>>> +
>>> +                     partition at a0000 {
>>> +                             label = "env";
>>> +                             reg = <0xa0000 0x20000>;
>>> +                             read-only;
>>> +                     };
>>> +
>>> +                     partition at 100000 {
>>> +                             label = "uImage";
>>> +                             reg = <0x100000 0x300000>;
>>> +                     };
>>> +
>>> +                     partition at 400000 {
>>> +                             label = "uInitrd";
>>> +                             reg = <0x540000 0x1000000>;
>>> +                     };
>>> +             };
>>> +             sata at 80000 {
>>> +                     status = "okay";
>>> +                     nr-ports = <2>;
>>> +             };
>>> +
>>> +     };
>>> +     gpio-leds {
>>> +             compatible = "gpio-leds";
>>> +
>>> +             power_led {
>>> +                     label = "status:white:power_led";
>>> +                     gpios = <&gpio0 16 0>;
>>> +                     linux,default-trigger = "default-on";
>>> +             };
>>> +             health_led1 {
>>> +                     label = "status:red:health_led";
>>> +                     gpios = <&gpio1 5 0>;
>>> +             };
>>> +             health_led2 {
>>> +                     label = "status:white:health_led";
>>> +                     gpios = <&gpio1 4 0>;
>>> +             };
>>> +             backup_led {
>>> +                     label = "status:blue:backup_led";
>>> +                     gpios = <&gpio0 15 0>;
>>> +             };
>>> +     };
>>> +     gpio-keys {
>>> +             compatible = "gpio-keys";
>>> +             #address-cells = <1>;
>>> +             #size-cells = <0>;
>>> +             Power {
>>> +                     label = "Power Button";
>>> +                     linux,code = <116>;
>>> +                     gpios = <&gpio0 14 1>;
>>> +             };
>>> +             Reset {
>>> +                     label = "Reset Button";
>>> +                     linux,code = <0x198>;
>>> +                     gpios = <&gpio0 12 1>;
>>> +             };
>>> +             OTB {
>>> +                     label = "OTB Button";
>>> +                     linux,code = <133>;
>>> +                     gpios = <&gpio1 3 1>;
>>> +             };
>>> +     };
>>
>> Did Fabio's patch fix gpio-keys?  If so, please list that as a
>> dependency below the '---', ie 3 lines below the Signed-off-by:.
>> Include the link he supplied with that comment.
>>
>>> +};
>>> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
>>> index ca5c15a..bee8451 100644
>>> --- a/arch/arm/mach-kirkwood/Kconfig
>>> +++ b/arch/arm/mach-kirkwood/Kconfig
>>> @@ -195,6 +195,13 @@ config MACH_T5325
>>>         Say 'Y' here if you want your kernel to support the
>>>         HP t5325 Thin Client.
>>>
>>> +config MACH_IOMEGA_IX2_200_DT
>>> +     bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
>>> +     select ARCH_KIRKWOOD_DT
>>> +     help
>>> +       Say 'Y' here if you want your kernel to support the
>>> +       Iomega StorCenter ix2-200 (Flattened Device Tree).
>>> +
>>>  endmenu
>>>
>>>  endif
>>> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
>>> index 055c85a..f5484dc 100644
>>> --- a/arch/arm/mach-kirkwood/Makefile
>>> +++ b/arch/arm/mach-kirkwood/Makefile
>>> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)                += board-ib62x0.o
>>>  obj-$(CONFIG_MACH_TS219_DT)          += board-ts219.o tsx1x-common.o
>>>  obj-$(CONFIG_MACH_GOFLEXNET_DT)              += board-goflexnet.o
>>>  obj-$(CONFIG_MACH_LSXL_DT)           += board-lsxl.o
>>> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
>>> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
>>> index 2a576ab..f8ef771 100644
>>> --- a/arch/arm/mach-kirkwood/Makefile.boot
>>> +++ b/arch/arm/mach-kirkwood/Makefile.boot
>>> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb
>>>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>>>  dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
>>> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
>>> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
>>> index e4eb450..9b3ec17 100644
>>> --- a/arch/arm/mach-kirkwood/board-dt.c
>>> +++ b/arch/arm/mach-kirkwood/board-dt.c
>>> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>>>       if (of_machine_is_compatible("buffalo,lsxl"))
>>>               lsxl_init();
>>>
>>> +     if (of_machine_is_compatible("iom,ix2-200"))
>>> +             iomega_ix2_200_init();
>>> +
>>>       of_platform_populate(NULL, kirkwood_dt_match_table,
>>>                            kirkwood_auxdata_lookup, NULL);
>>>  }
>>> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>>>       "qnap,ts219",
>>>       "seagate,goflexnet",
>>>       "buffalo,lsxl",
>>> +     "iom,ix2-200",
>>>       NULL
>>>  };
>>>
>>> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>> new file mode 100644
>>> index 0000000..0c78752
>>> --- /dev/null
>>> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>> @@ -0,0 +1,79 @@
>>> +/*
>>> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>>> + *
>>> + * Iomega StorCenter ix2-200
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> + * License version 2.  This program is licensed "as is" without any
>>> + * warranty of any kind, whether express or implied.
>>> + */
>>> +
>>> +#include <linux/kernel.h>
>>> +#include <linux/init.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/irq.h>
>>> +#include <linux/mtd/partitions.h>
>>> +#include <linux/ata_platform.h>
>>> +#include <linux/mv643xx_eth.h>
>>> +#include <linux/ethtool.h>
>>> +#include <net/dsa.h>
>>> +#include <linux/gpio.h>
>>> +#include <linux/leds.h>
>>> +#include <linux/i2c.h>
>>> +#include <asm/mach-types.h>
>>> +#include <asm/mach/arch.h>
>>> +#include <mach/kirkwood.h>
>>> +#include "common.h"
>>> +#include "mpp.h"
>>> +
>>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
>>> +     .phy_addr       = MV643XX_ETH_PHY_NONE,
>>> +     .speed          = SPEED_1000,
>>> +     .duplex         = DUPLEX_FULL,
>>> +};
>>> +
>>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
>>> +     .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
>>> +};
>>> +
>>> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
>>> +     MPP12_GPIO,                     /* Reset Button */
>>> +     MPP14_GPIO,                     /* Power Button */
>>> +     MPP15_GPIO,                     /* Backup LED (blue) */
>>> +     MPP16_GPIO,                     /* Power LED (white) */
>>> +     MPP35_GPIO,                     /* OTB Button */
>>> +     MPP36_GPIO,                     /* Rebuild LED (white) */
>>> +     MPP37_GPIO,                     /* Health LED (red) */
>>> +     MPP38_GPIO,                     /* SATA LED brightness control 1 */
>>> +     MPP39_GPIO,                     /* SATA LED brightness control 2 */
>>> +     MPP40_GPIO,                     /* Backup LED brightness control 1 */
>>> +     MPP41_GPIO,                     /* Backup LED brightness control 2 */
>>> +     MPP42_GPIO,                     /* Power LED brightness control 1 */
>>> +     MPP43_GPIO,                     /* Power LED brightness control 2 */
>>> +     MPP44_GPIO,                     /* Health LED brightness control 1 */
>>> +     MPP45_GPIO,                     /* Health LED brightness control 2 */
>>> +     MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
>>> +     MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
>>> +     0
>>> +};
>>> +
>>> +void __init iomega_ix2_200_init(void)
>>> +{
>>> +     /*
>>> +      * Basic setup. Needs to be called early.
>>> +      */
>>> +     kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
>>> +
>>> +     kirkwood_ehci_init();
>>> +
>>> +     kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
>>> +     kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
>>> +}
>>> +static int __init iomega_ix2_200_pci_init(void)
>>> +{
>>> +     if (of_machine_is_compatible("iom,ix2-200"))
>>> +             kirkwood_pcie_init(KW_PCIE0);
>>> +     return 0;
>>> +}
>>> +subsys_initcall(iomega_ix2_200_pci_init);
>>> +
>>> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
>>> index 304dd1a..d5d4064 100644
>>> --- a/arch/arm/mach-kirkwood/common.h
>>> +++ b/arch/arm/mach-kirkwood/common.h
>>> @@ -94,6 +94,12 @@ void lsxl_init(void);
>>>  static inline void lsxl_init(void) {};
>>>  #endif
>>>
>>> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
>>> +void iomega_ix2_200_init(void);
>>> +#else
>>> +static inline void iomega_ix2_200_init(void) {};
>>> +#endif
>>> +
>>>  /* early init functions not converted to fdt yet */
>>>  char *kirkwood_id(void);
>>>  void kirkwood_l2_init(void);
>>> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
>>
>> This is the wrong place for the Signed-off-by:, please see my comments,
>> above.  If anyone tries to apply this patch it will fail because git or
>> patch will think the sob is a line of context.  There won't be a match,
>> so it will fail.
>>
>> hth,
>>
>> Jason.
>
> yeah 2 seconds after i sent the patch i noticed i forgot to remove the
> coherent_pool line and i think i sent a v3 with it removed but i will
> need to do a v4 and fix what you told me here. and i think i told
> fabio that it did not fix the keys however it did allow the kernel to
> boot with no panics but the keys still did not work so there is still
> something small thats missing or broken in his gpio file i think.
>
> But the patch as is works on 3.6-rc1 with the buttons and leds. If i
> get a chance i will try with his patch again later today. Should i
> remake the patch on 3.6-rc2 so to be sure it applies cleanly?
>
> Thanks.
>
> p.s Do i send the updated patch directly to you and andrew or to the
> list and just cc you both? Still getting used to this mailing list and
> submitting a patch thing.

i just thaught i should let fabio and jason know that i just tried
kernel 3.6-rc2 and the buttons work i tried to apply the patch that
fabio sent me before but it didnt apply so i tried the kernel anyway
and the buttons do work.


From dedekind1 at gmail.com  Sun Aug 19 15:19:18 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 19 Aug 2012 22:19:18 +0300
Subject: [PATCH 2/8] UBI: separate bad_peb_limit in a function
In-Reply-To: <1345214124-5478-3-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-3-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345403958.1930.5.camel@kyv>

On Fri, 2012-08-17 at 16:35 +0200, Richard Genoud wrote:
> No functional changes here, just to prepare for next patch.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Pushed this one to linux-ubi, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From dedekind1 at gmail.com  Sun Aug 19 15:21:19 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 19 Aug 2012 22:21:19 +0300
Subject: [PATCH 1/8] arm: sam9_l9260_defconfig: adjust UBI bad
 eraseblocks limit
In-Reply-To: <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345404079.1930.7.camel@kyv>

On Fri, 2012-08-17 at 16:35 +0200, Richard Genoud wrote:
> diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
> index da276f9..d11fea5 100644
> --- a/arch/arm/configs/sam9_l9260_defconfig
> +++ b/arch/arm/configs/sam9_l9260_defconfig
> @@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y
>  CONFIG_MTD_NAND_ATMEL=y
>  CONFIG_MTD_NAND_PLATFORM=y
>  CONFIG_MTD_UBI=y
> -CONFIG_MTD_UBI_BEB_LIMIT=3
> +CONFIG_MTD_UBI_BEB_LIMIT=30

I'll just remove this from from the defconfig and make it use the
default, which is more sensible for this device, as your research
showed.

-- 
Best Regards,
Artem Bityutskiy
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From dedekind1 at gmail.com  Sun Aug 19 15:29:33 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 19 Aug 2012 22:29:33 +0300
Subject: [PATCH 1/8] arm: sam9_l9260_defconfig: adjust UBI bad
 eraseblocks limit
In-Reply-To: <1345404079.1930.7.camel@kyv>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>
 <1345404079.1930.7.camel@kyv>
Message-ID: <1345404573.1930.9.camel@kyv>

On Sun, 2012-08-19 at 22:21 +0300, Artem Bityutskiy wrote:
> I'll just remove this from from the defconfig and make it use the
> default, which is more sensible for this device, as your research
> showed.

Actually, pushed this patch to l2-mtd.git:


From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date: Sun, 19 Aug 2012 22:22:23 +0300
Subject: [PATCH] arm: sam9_l9260_defconfig: correct CONFIG_MTD_UBI_BEB_LIMIT

UBI has changed the MTD_UBI_BEB_LIMIT semantics. It used to be a percent of
total amount of eraseblock in the partition, and now it is the maximum
amount of bad eraseblocks on the entire devise per 1024 eraseblocks. So not
only the units changed, but also the meaning.

Richard Genoud <richard.genoud at gmail.com> says:

"I found the board:
https://www.olimex.com/dev/sam9-L9260.html
and the nand datasheet:
http://www.rockbox.org/wiki/pub/Main/LyrePrototype/K9xxG08UXM.pdf
page 11, we can see that the max_bad_bebper1024 is 25 (100 for 4096)"

Thus, use "25" for sam9.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 arch/arm/configs/sam9_l9260_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index da276f9..b4384af 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -39,7 +39,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=3
+CONFIG_MTD_UBI_BEB_LIMIT=25
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
-- 
1.7.11.2

-- 
Best Regards,
Artem Bityutskiy
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From dedekind1 at gmail.com  Sun Aug 19 15:32:06 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 19 Aug 2012 22:32:06 +0300
Subject: [PATCH 3/8] UBI: introduce MTD_PARAM_MAX_COUNT
In-Reply-To: <1345214124-5478-4-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-4-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345404726.1930.10.camel@kyv>

On Fri, 2012-08-17 at 16:35 +0200, Richard Genoud wrote:
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
> ---
>  drivers/mtd/ubi/build.c |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
> index 82d11e1..1f45f51 100644
> --- a/drivers/mtd/ubi/build.c
> +++ b/drivers/mtd/ubi/build.c
> @@ -46,6 +46,9 @@
>  /* Maximum length of the 'mtd=' parameter */
>  #define MTD_PARAM_LEN_MAX 64
>  
> +/* Maximum number of comma-separated items in ht 'mtd=' parameter */
> +#define MTD_PARAM_MAX_COUNT 2

Fixed the spelling of "the" and pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From dedekind1 at gmail.com  Sun Aug 19 15:32:19 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 19 Aug 2012 22:32:19 +0300
Subject: [PATCH 3/8] UBI: introduce MTD_PARAM_MAX_COUNT
In-Reply-To: <1345214124-5478-4-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-4-git-send-email-richard.genoud@gmail.com>
Message-ID: <1345404739.1930.11.camel@kyv>

On Fri, 2012-08-17 at 16:35 +0200, Richard Genoud wrote:
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
> ---
>  drivers/mtd/ubi/build.c |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
> index 82d11e1..1f45f51 100644
> --- a/drivers/mtd/ubi/build.c
> +++ b/drivers/mtd/ubi/build.c
> @@ -46,6 +46,9 @@
>  /* Maximum length of the 'mtd=' parameter */
>  #define MTD_PARAM_LEN_MAX 64
>  
> +/* Maximum number of comma-separated items in ht 'mtd=' parameter */
> +#define MTD_PARAM_MAX_COUNT 2

Fixed the spelling of "the" and pushed to linux-ubi.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From notasas at gmail.com  Sun Aug 19 19:18:12 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Mon, 20 Aug 2012 02:18:12 +0300
Subject: ARM hugetlb support?
Message-ID: <CANOLnOPLLQ=Cy5rvf5J7R96whrvLKO4HW9nVn4rQXqXCTVgCPA@mail.gmail.com>

Hello,

We are developing an application that's drawing various geometry on
1024x1024 framebuffer (lines, triangles, etc) and is running on
Cortex-A8 CPU. It seems this kind of application is suffering badly
from TLB misses, as A8 only has 32 entry TLB cache.

I've found that hugetlb support patches have been posted some months
ago [1]. I've been testing them with very good results [2]. Are there
still plans to further develop them and eventually merge them?


[1] http://marc.info/?l=linux-arm-kernel&m=132912620601308&w=2
[2] Cycle measurements of rendering full scene (using cycle counter in
A8), x1000 cycles:

       normal hugetlb improvement
scene1 28507  21351   34%
scene2 11710  10138   16%
scene3 17178  13631   26%
scene4 4372   3810    15%
scene5 3525   3255    8%

-- 
Gra?vydas


From festevam at gmail.com  Sun Aug 19 22:31:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 19 Aug 2012 23:31:55 -0300
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
Message-ID: <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>

On Sun, Aug 19, 2012 at 3:03 PM, Alan M Butler <alanbutty12 at gmail.com> wrote:
> i just thaught i should let fabio and jason know that i just tried
> kernel 3.6-rc2 and the buttons work i tried to apply the patch that
> fabio sent me before but it didnt apply so i tried the kernel anyway
> and the buttons do work.

The patch I sent applies against linux-next.

If you try linux-next you will probably get the kernel crash.


From xiechao.mail at gmail.com  Sun Aug 19 22:55:10 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:10 +0800
Subject: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
Message-ID: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

v1->v2:
replace __raw_xxx with xxx_relax
use ioremap to remap the registers. Finaly it will use device tree to
get the physical address.
do not use macro to register clocks, and directly call the functions.

v2->v3:
pxa910 will have APB extension clock, so some peripharals will have
clocks in APB extension base.
change pxa168-pwm to be pxa910-pwm for pxa910. It will fit the current
pwm driver.

v3->v4:
remove addtional clock name definition
replace left __raw_xxx

v4->v5:
change the format of the file

Chao Xie (5):
  clk: mmp: add mmp specific clocks
  clk: mmp: add clock definition for pxa168
  clk: mmp: add clock definition for pxa910
  clk: mmp: add clock definition for mmp2
  arm: mmp: make all SOCs use common clock by default

 arch/arm/mach-mmp/Kconfig    |    3 +
 drivers/clk/Makefile         |    3 +
 drivers/clk/mmp/Makefile     |    9 +
 drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++++
 drivers/clk/mmp/clk-apmu.c   |   97 +++++++++
 drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++++
 drivers/clk/mmp/clk-mmp2.c   |  449 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa168.c |  346 ++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-pxa910.c |  320 ++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h        |   35 ++++
 10 files changed, 1567 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk-mmp2.c
 create mode 100644 drivers/clk/mmp/clk-pxa168.c
 create mode 100644 drivers/clk/mmp/clk-pxa910.c
 create mode 100644 drivers/clk/mmp/clk.h



From xiechao.mail at gmail.com  Sun Aug 19 22:55:11 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:11 +0800
Subject: [PATCH V5 1/5] clk: mmp: add mmp specific clocks
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345431315-8037-2-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

add mmp specific clocks including apbc cloks, apmu clocks,
and pll2, fraction clocks

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/Makefile       |    3 +
 drivers/clk/mmp/Makefile   |    5 ++
 drivers/clk/mmp/clk-apbc.c |  152 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-apmu.c |   97 ++++++++++++++++++++++++++++
 drivers/clk/mmp/clk-frac.c |  153 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/mmp/clk.h      |   35 ++++++++++
 6 files changed, 445 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/Makefile
 create mode 100644 drivers/clk/mmp/clk-apbc.c
 create mode 100644 drivers/clk/mmp/clk-apmu.c
 create mode 100644 drivers/clk/mmp/clk-frac.c
 create mode 100644 drivers/clk/mmp/clk.h

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..58590c8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,9 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-$(CONFIG_ARCH_MMP)		+= mmp/
+endif
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
new file mode 100644
index 0000000..b5bc88c
--- /dev/null
+++ b/drivers/clk/mmp/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for mmp specific clk
+#
+
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
new file mode 100644
index 0000000..d14120e
--- /dev/null
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -0,0 +1,152 @@
+/*
+ * mmp APB clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
+#define APBC_RST	(1 << 2)  /* Reset Generation */
+#define APBC_POWER	(1 << 7)  /* Reset Generation */
+
+#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
+struct clk_apbc {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	unsigned int		delay;
+	unsigned int		flags;
+	spinlock_t		*lock;
+};
+
+static int clk_apbc_prepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned int data;
+	unsigned long flags = 0;
+
+	/*
+	 * It may share same register as MUX clock,
+	 * and it will impact FNCLK enable. Spinlock is needed
+	 */
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data |= APBC_POWER;
+	data |= APBC_FNCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	data |= APBC_APBCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(apbc->delay);
+
+	if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
+		if (apbc->lock)
+			spin_lock_irqsave(apbc->lock, flags);
+
+		data = readl_relaxed(apbc->base);
+		data &= ~APBC_RST;
+		writel_relaxed(data, apbc->base);
+
+		if (apbc->lock)
+			spin_unlock_irqrestore(apbc->lock, flags);
+	}
+
+	return 0;
+}
+
+static void clk_apbc_unprepare(struct clk_hw *hw)
+{
+	struct clk_apbc *apbc = to_clk_apbc(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	if (apbc->flags & APBC_POWER_CTRL)
+		data &= ~APBC_POWER;
+	data &= ~APBC_FNCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+
+	udelay(10);
+
+	if (apbc->lock)
+		spin_lock_irqsave(apbc->lock, flags);
+
+	data = readl_relaxed(apbc->base);
+	data &= ~APBC_APBCLK;
+	writel_relaxed(data, apbc->base);
+
+	if (apbc->lock)
+		spin_unlock_irqrestore(apbc->lock, flags);
+}
+
+struct clk_ops clk_apbc_ops = {
+	.prepare = clk_apbc_prepare,
+	.unprepare = clk_apbc_unprepare,
+};
+
+struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
+		void __iomem *base, unsigned int delay,
+		unsigned int apbc_flags, spinlock_t *lock)
+{
+	struct clk_apbc *apbc;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
+	if (!apbc)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apbc_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apbc->base = base;
+	apbc->delay = delay;
+	apbc->flags = apbc_flags;
+	apbc->lock = lock;
+	apbc->hw.init = &init;
+
+	clk = clk_register(NULL, &apbc->hw);
+	if (IS_ERR(clk))
+		kfree(apbc);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
new file mode 100644
index 0000000..abe182b
--- /dev/null
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -0,0 +1,97 @@
+/*
+ * mmp AXI peripharal clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
+struct clk_apmu {
+	struct clk_hw   hw;
+	void __iomem    *base;
+	u32		rst_mask;
+	u32		enable_mask;
+	spinlock_t	*lock;
+};
+
+static int clk_apmu_enable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = readl_relaxed(apmu->base) | apmu->enable_mask;
+	writel_relaxed(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+
+	return 0;
+}
+
+static void clk_apmu_disable(struct clk_hw *hw)
+{
+	struct clk_apmu *apmu = to_clk_apmu(hw);
+	unsigned long data;
+	unsigned long flags = 0;
+
+	if (apmu->lock)
+		spin_lock_irqsave(apmu->lock, flags);
+
+	data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
+	writel_relaxed(data, apmu->base);
+
+	if (apmu->lock)
+		spin_unlock_irqrestore(apmu->lock, flags);
+}
+
+struct clk_ops clk_apmu_ops = {
+	.enable = clk_apmu_enable,
+	.disable = clk_apmu_disable,
+};
+
+struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
+		void __iomem *base, u32 enable_mask, spinlock_t *lock)
+{
+	struct clk_apmu *apmu;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
+	if (!apmu)
+		return NULL;
+
+	init.name = name;
+	init.ops = &clk_apmu_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+
+	apmu->base = base;
+	apmu->enable_mask = enable_mask;
+	apmu->lock = lock;
+	apmu->hw.init = &init;
+
+	clk = clk_register(NULL, &apmu->hw);
+
+	if (IS_ERR(clk))
+		kfree(apmu);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
new file mode 100644
index 0000000..80c1dd1
--- /dev/null
+++ b/drivers/clk/mmp/clk-frac.c
@@ -0,0 +1,153 @@
+/*
+ * mmp factor clock operation source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include "clk.h"
+/*
+ * It is M/N clock
+ *
+ * Fout from synthesizer can be given from two equations:
+ * numerator/denominator = Fin / (Fout * factor)
+ */
+
+#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
+struct clk_factor {
+	struct clk_hw		hw;
+	void __iomem		*base;
+	struct clk_factor_masks	*masks;
+	struct clk_factor_tbl	*ftbl;
+	unsigned int		ftbl_cnt;
+};
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
+		unsigned long *prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	unsigned long rate = 0, prev_rate;
+	int i;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((*prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i == 0)
+		return rate;
+	else
+		return prev_rate;
+}
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	unsigned int val, num, den;
+
+	val = readl_relaxed(factor->base);
+
+	/* calculate numerator */
+	num = (val >> masks->num_shift) & masks->num_mask;
+
+	/* calculate denominator */
+	den = (val >> masks->den_shift) & masks->num_mask;
+
+	if (!den)
+		return 0;
+
+	return (((parent_rate / 10000)  * den) /
+			(num * factor->masks->factor)) * 10000;
+}
+
+/* Configures new clock rate*/
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
+				unsigned long prate)
+{
+	struct clk_factor *factor = to_clk_factor(hw);
+	struct clk_factor_masks *masks = factor->masks;
+	int i;
+	unsigned long val;
+	unsigned long prev_rate, rate = 0;
+
+	for (i = 0; i < factor->ftbl_cnt; i++) {
+		prev_rate = rate;
+		rate = (((prate / 10000) * factor->ftbl[i].num) /
+			(factor->ftbl[i].den * factor->masks->factor)) * 10000;
+		if (rate > drate)
+			break;
+	}
+	if (i > 0)
+		i--;
+
+	val = readl_relaxed(factor->base);
+
+	val &= ~(masks->num_mask << masks->num_shift);
+	val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
+
+	val &= ~(masks->den_mask << masks->den_shift);
+	val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
+
+	writel_relaxed(val, factor->base);
+
+	return 0;
+}
+
+static struct clk_ops clk_factor_ops = {
+	.recalc_rate = clk_factor_recalc_rate,
+	.round_rate = clk_factor_round_rate,
+	.set_rate = clk_factor_set_rate,
+};
+
+struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
+		unsigned long flags, void __iomem *base,
+		struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
+		unsigned int ftbl_cnt)
+{
+	struct clk_factor *factor;
+	struct clk_init_data init;
+	struct clk *clk;
+
+	if (!masks) {
+		pr_err("%s: must pass a clk_factor_mask\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	factor = kzalloc(sizeof(*factor), GFP_KERNEL);
+	if (!factor) {
+		pr_err("%s: could not allocate factor  clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_aux assignments */
+	factor->base = base;
+	factor->masks = masks;
+	factor->ftbl = ftbl;
+	factor->ftbl_cnt = ftbl_cnt;
+	factor->hw.init = &init;
+
+	init.name = name;
+	init.ops = &clk_factor_ops;
+	init.flags = flags;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clk = clk_register(NULL, &factor->hw);
+	if (IS_ERR_OR_NULL(clk))
+		kfree(factor);
+
+	return clk;
+}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
new file mode 100644
index 0000000..ab86dd4
--- /dev/null
+++ b/drivers/clk/mmp/clk.h
@@ -0,0 +1,35 @@
+#ifndef __MACH_MMP_CLK_H
+#define __MACH_MMP_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
+#define APBC_NO_BUS_CTRL	BIT(0)
+#define APBC_POWER_CTRL		BIT(1)
+
+struct clk_factor_masks {
+	unsigned int	factor;
+	unsigned int	num_mask;
+	unsigned int	den_mask;
+	unsigned int	num_shift;
+	unsigned int	den_shift;
+};
+
+struct clk_factor_tbl {
+	unsigned int num;
+	unsigned int den;
+};
+
+extern struct clk *mmp_clk_register_pll2(const char *name,
+		const char *parent_name, unsigned long flags);
+extern struct clk *mmp_clk_register_apbc(const char *name,
+		const char *parent_name, void __iomem *base,
+		unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
+extern struct clk *mmp_clk_register_apmu(const char *name,
+		const char *parent_name, void __iomem *base, u32 enable_mask,
+		spinlock_t *lock);
+extern struct clk *mmp_clk_register_factor(const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *base, struct clk_factor_masks *masks,
+		struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+#endif
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 19 22:55:12 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:12 +0800
Subject: [PATCH V5 2/5] clk: mmp: add clock definition for pxa168
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345431315-8037-3-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa168

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    2 +
 drivers/clk/mmp/clk-pxa168.c |  346 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 348 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa168.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index b5bc88c..a0e69ed 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -3,3 +3,5 @@
 #
 
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
+
+obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 0000000..e8d036c
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,346 @@
+/*
+ * pxa168 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x30
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x81c
+#define APBC_SSP1	0x820
+#define APBC_SSP2	0x84c
+#define APBC_SSP3	0x858
+#define APBC_SSP4	0x85c
+#define APBC_TWSI1	0x6c
+#define APBC_UART2	0x70
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa168_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *uart_pll;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				26000000);
+	clk_register_clkdev(clk, "vctcxo", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+				624000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_24", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_48", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_96", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clk, "pll1_13", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+	uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				mpmu_base + MPMU_UART_PLL,
+				&uart_factor_masks, uart_factor_tbl,
+				ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(uart_pll, 14745600);
+	clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+	clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk = mmp_clk_register_apbc("gpio", "vctcxo",
+				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk = mmp_clk_register_apbc("kpc", "clk32",
+				apbc_base + APBC_KPC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk = mmp_clk_register_apbc("rtc", "clk32",
+				apbc_base + APBC_RTC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+	clk = mmp_clk_register_apbc("pwm0", "pll1_48",
+				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
+
+	clk = mmp_clk_register_apbc("pwm1", "pll1_48",
+				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
+
+	clk = mmp_clk_register_apbc("pwm2", "pll1_48",
+				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
+
+	clk = mmp_clk_register_apbc("pwm3", "pll1_48",
+				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
+
+	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+				apbc_base + APBC_UART0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+				apbc_base + APBC_UART1,	10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+				apbc_base + APBC_UART2,	10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
+				10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
+				10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+	clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
+				10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+	clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
+				10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+	clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.4", NULL);
+
+	clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
+				10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.4");
+
+	clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
+				0x19b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+	clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+	clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
+				0x9, &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
+				0x12, &clk_lock);
+	clk_register_clkdev(clk, "sph_clk", NULL);
+
+	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("disp0", "disp0_mux",
+				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
+
+	clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
+				apmu_base + APMU_DISP0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "hclk", "mmp-disp.0");
+
+	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
+				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+				ARRAY_SIZE(ccic_phy_parent),
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				7, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 19 22:55:13 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:13 +0800
Subject: [PATCH V5 3/5] clk: mmp: add clock definition for pxa910
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345431315-8037-4-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for pxa910

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile     |    1 +
 drivers/clk/mmp/clk-pxa910.c |  320 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 321 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa910.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index a0e69ed..6160ac2 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -5,3 +5,4 @@
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
+obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
new file mode 100644
index 0000000..7048c31
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -0,0 +1,320 @@
+/*
+ * pxa910 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x28
+#define APBC_TWSI0	0x2c
+#define APBC_KPC	0x18
+#define APBC_UART0	0x0
+#define APBC_UART1	0x4
+#define APBC_GPIO	0x8
+#define APBC_PWM0	0xc
+#define APBC_PWM1	0x10
+#define APBC_PWM2	0x14
+#define APBC_PWM3	0x18
+#define APBC_SSP0	0x1c
+#define APBC_SSP1	0x20
+#define APBC_SSP2	0x4c
+#define APBCP_TWSI1	0x28
+#define APBCP_UART2	0x1c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_CCIC0	0x50
+#define APMU_DFC	0x60
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 8125, .den = 1536},	/*14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa910_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *uart_pll;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbcp_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
+	if (apbcp_base == NULL) {
+		pr_err("error to ioremap APBC extension base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				26000000);
+	clk_register_clkdev(clk, "vctcxo", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+				624000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
+				CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_24", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_48", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_96", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
+				CLK_SET_RATE_PARENT, 1, 13);
+	clk_register_clkdev(clk, "pll1_13", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
+				CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_13_1_5", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
+				CLK_SET_RATE_PARENT, 2, 3);
+	clk_register_clkdev(clk, "pll1_2_1_5", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
+				CLK_SET_RATE_PARENT, 3, 16);
+	clk_register_clkdev(clk, "pll1_3_16", NULL);
+
+	uart_pll =  mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				mpmu_base + MPMU_UART_PLL,
+				&uart_factor_masks, uart_factor_tbl,
+				ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(uart_pll, 14745600);
+	clk_register_clkdev(uart_pll, "uart_pll", NULL);
+
+	clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
+				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
+				apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk = mmp_clk_register_apbc("gpio", "vctcxo",
+				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk = mmp_clk_register_apbc("kpc", "clk32",
+				apbc_base + APBC_KPC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk = mmp_clk_register_apbc("rtc", "clk32",
+				apbc_base + APBC_RTC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sa1100-rtc");
+
+	clk = mmp_clk_register_apbc("pwm0", "pll1_48",
+				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
+
+	clk = mmp_clk_register_apbc("pwm1", "pll1_48",
+				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
+
+	clk = mmp_clk_register_apbc("pwm2", "pll1_48",
+				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
+
+	clk = mmp_clk_register_apbc("pwm3", "pll1_48",
+				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
+
+	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+				apbc_base + APBC_UART0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+				apbc_base + APBC_UART1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, uart_pll);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+				apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
+				apbc_base + APBC_SSP0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
+				apbc_base + APBC_SSP1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk = mmp_clk_register_apmu("dfc", "pll1_4",
+				apmu_base + APMU_DFC, 0x19b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
+
+	clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
+				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh0_mux", NULL);
+
+	clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
+				apmu_base + APMU_SDH0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
+
+	clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
+				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh1_mux", NULL);
+
+	clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
+				apmu_base + APMU_SDH1, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
+
+	clk = mmp_clk_register_apmu("usb", "usb_pll",
+				apmu_base + APMU_USB, 0x9, &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk = mmp_clk_register_apmu("sph", "usb_pll",
+				apmu_base + APMU_USB, 0x12, &clk_lock);
+	clk_register_clkdev(clk, "sph_clk", NULL);
+
+	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("disp0", "disp0_mux",
+				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
+				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
+				ARRAY_SIZE(ccic_phy_parent),
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				7, 1, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
+				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 19 22:55:14 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:14 +0800
Subject: [PATCH V5 4/5] clk: mmp: add clock definition for mmp2
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345431315-8037-5-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Initialize the clocks for mmp2

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 drivers/clk/mmp/Makefile   |    1 +
 drivers/clk/mmp/clk-mmp2.c |  449 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 450 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-mmp2.c

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 6160ac2..392d780 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o
 
 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
+obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
new file mode 100644
index 0000000..6d77a9b
--- /dev/null
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -0,0 +1,449 @@
+/*
+ * mmp2 clock framework source file
+ *
+ * Copyright (C) 2012 Marvell
+ * Chao Xie <xiechao.mail at gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	0x0
+#define APBC_TWSI0	0x4
+#define APBC_TWSI1	0x8
+#define APBC_TWSI2	0xc
+#define APBC_TWSI3	0x10
+#define APBC_TWSI4	0x7c
+#define APBC_TWSI5	0x80
+#define APBC_KPC	0x18
+#define APBC_UART0	0x2c
+#define APBC_UART1	0x30
+#define APBC_UART2	0x34
+#define APBC_UART3	0x88
+#define APBC_GPIO	0x38
+#define APBC_PWM0	0x3c
+#define APBC_PWM1	0x40
+#define APBC_PWM2	0x44
+#define APBC_PWM3	0x48
+#define APBC_SSP0	0x50
+#define APBC_SSP1	0x54
+#define APBC_SSP2	0x58
+#define APBC_SSP3	0x5c
+#define APMU_SDH0	0x54
+#define APMU_SDH1	0x58
+#define APMU_SDH2	0xe8
+#define APMU_SDH3	0xec
+#define APMU_USB	0x5c
+#define APMU_DISP0	0x4c
+#define APMU_DISP1	0x110
+#define APMU_CCIC0	0x50
+#define APMU_CCIC1	0xf4
+#define MPMU_UART_PLL	0x14
+
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct clk_factor_masks uart_factor_masks = {
+	.factor = 2,
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl uart_factor_tbl[] = {
+	{.num = 14634, .den = 2165},	/*14.745MHZ */
+	{.num = 3521, .den = 689},	/*19.23MHZ */
+	{.num = 9679, .den = 5728},	/*58.9824MHZ */
+	{.num = 15850, .den = 9451},	/*59.429MHZ */
+};
+
+static const char *uart_parent[] = {"uart_pll", "vctcxo"};
+static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
+static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
+static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
+
+void __init mmp2_clk_init(void)
+{
+	struct clk *clk;
+	struct clk *vctcxo;
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+
+	mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
+	if (mpmu_base == NULL) {
+		pr_err("error to ioremap MPMU base\n");
+		return;
+	}
+
+	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
+	if (apmu_base == NULL) {
+		pr_err("error to ioremap APMU base\n");
+		return;
+	}
+
+	apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
+	if (apbc_base == NULL) {
+		pr_err("error to ioremap APBC base\n");
+		return;
+	}
+
+	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
+	clk_register_clkdev(clk, "clk32", NULL);
+
+	vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
+				26000000);
+	clk_register_clkdev(vctcxo, "vctcxo", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
+				800000000);
+	clk_register_clkdev(clk, "pll1", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
+				480000000);
+	clk_register_clkdev(clk, "usb_pll", NULL);
+
+	clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
+				960000000);
+	clk_register_clkdev(clk, "pll2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_4", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_8", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_16", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
+				CLK_SET_RATE_PARENT, 1, 5);
+	clk_register_clkdev(clk, "pll1_20", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
+				CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll1_3", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_6", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll1_12", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_4", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_8", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_16", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
+				CLK_SET_RATE_PARENT, 1, 3);
+	clk_register_clkdev(clk, "pll2_3", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_6", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "pll2_12", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "vctcxo_2", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
+				CLK_SET_RATE_PARENT, 1, 2);
+	clk_register_clkdev(clk, "vctcxo_4", NULL);
+
+	clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				mpmu_base + MPMU_UART_PLL,
+				&uart_factor_masks, uart_factor_tbl,
+				ARRAY_SIZE(uart_factor_tbl));
+	clk_set_rate(clk, 14745600);
+	clk_register_clkdev(clk, "uart_pll", NULL);
+
+	clk = mmp_clk_register_apbc("twsi0", "vctcxo",
+				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
+
+	clk = mmp_clk_register_apbc("twsi1", "vctcxo",
+				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
+
+	clk = mmp_clk_register_apbc("twsi2", "vctcxo",
+				apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
+
+	clk = mmp_clk_register_apbc("twsi3", "vctcxo",
+				apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
+
+	clk = mmp_clk_register_apbc("twsi4", "vctcxo",
+				apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
+
+	clk = mmp_clk_register_apbc("twsi5", "vctcxo",
+				apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
+
+	clk = mmp_clk_register_apbc("gpio", "vctcxo",
+				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa-gpio");
+
+	clk = mmp_clk_register_apbc("kpc", "clk32",
+				apbc_base + APBC_KPC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
+
+	clk = mmp_clk_register_apbc("rtc", "clk32",
+				apbc_base + APBC_RTC, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-rtc");
+
+	clk = mmp_clk_register_apbc("pwm0", "vctcxo",
+				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
+
+	clk = mmp_clk_register_apbc("pwm1", "vctcxo",
+				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
+
+	clk = mmp_clk_register_apbc("pwm2", "vctcxo",
+				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
+
+	clk = mmp_clk_register_apbc("pwm3", "vctcxo",
+				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
+
+	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
+				apbc_base + APBC_UART0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
+
+	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
+				apbc_base + APBC_UART1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
+
+	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.2", NULL);
+
+	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
+				apbc_base + APBC_UART2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
+
+	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
+				ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
+	clk_set_parent(clk, vctcxo);
+	clk_register_clkdev(clk, "uart_mux.3", NULL);
+
+	clk = mmp_clk_register_apbc("uart3", "uart3_mux",
+				apbc_base + APBC_UART3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
+
+	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "uart_mux.0", NULL);
+
+	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
+				apbc_base + APBC_SSP0, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
+
+	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.1", NULL);
+
+	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
+				apbc_base + APBC_SSP1, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
+
+	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.2", NULL);
+
+	clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
+				apbc_base + APBC_SSP2, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
+
+	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
+				ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
+	clk_register_clkdev(clk, "ssp_mux.3", NULL);
+
+	clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
+				apbc_base + APBC_SSP3, 10, 0, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
+
+	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
+				ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "sdh_mux", NULL);
+
+	clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
+				10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "sdh_div", NULL);
+
+	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
+
+	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
+
+	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
+
+	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
+				0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
+
+	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
+				0x9, &clk_lock);
+	clk_register_clkdev(clk, "usb_clk", NULL);
+
+	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
+				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.0", NULL);
+
+	clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
+				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "disp_div.0", NULL);
+
+	clk = mmp_clk_register_apmu("disp0", "disp0_div",
+				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.0");
+
+	clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
+				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
+
+	clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
+				apmu_base + APMU_DISP0, 0x1024, &clk_lock);
+	clk_register_clkdev(clk, "disp_sphy.0", NULL);
+
+	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
+				ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "disp_mux.1", NULL);
+
+	clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
+				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "disp_div.1", NULL);
+
+	clk = mmp_clk_register_apmu("disp1", "disp1_div",
+				apmu_base + APMU_DISP1, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, NULL, "mmp-disp.1");
+
+	clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
+				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
+	clk_register_clkdev(clk, "ccic_arbiter", NULL);
+
+	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
+				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.0", NULL);
+
+	clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "ccic_div.0", NULL);
+
+	clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
+				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
+
+	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
+				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
+
+	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
+				10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
+
+	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
+				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
+
+	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
+				ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
+	clk_register_clkdev(clk, "ccic_mux.1", NULL);
+
+	clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
+	clk_register_clkdev(clk, "ccic_div.1", NULL);
+
+	clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
+				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
+	clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
+
+	clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
+				apmu_base + APMU_CCIC1, 0x24, &clk_lock);
+	clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
+
+	clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
+				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
+				10, 5, 0, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
+
+	clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
+				apmu_base + APMU_CCIC1, 0x300, &clk_lock);
+	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
+}
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 19 22:55:15 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 20 Aug 2012 10:55:15 +0800
Subject: [PATCH V5 5/5] arm: mmp: make all SOCs use common clock by default
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1345431315-8037-6-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Kconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01..d697d07 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -108,18 +108,21 @@ endmenu
 config CPU_PXA168
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA168
 
 config CPU_PXA910
 	bool
 	select CPU_MOHAWK
+	select COMMON_CLK
 	help
 	  Select code specific to PXA910
 
 config CPU_MMP2
 	bool
 	select CPU_PJ4
+	select COMMON_CLK
 	help
 	  Select code specific to MMP2. MMP2 is ARMv7 compatible.
 
-- 
1.7.0.4



From arnd at arndb.de  Mon Aug 20 01:39:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 05:39:17 +0000
Subject: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <201208200539.17878.arnd@arndb.de>

On Monday 20 August 2012, Chao Xie wrote:
> 
> From: Chao Xie <chao.xie at marvell.com>
> 
> v1->v2:
> replace __raw_xxx with xxx_relax
> use ioremap to remap the registers. Finaly it will use device tree to
> get the physical address.
> do not use macro to register clocks, and directly call the functions.
> 
> v2->v3:
> pxa910 will have APB extension clock, so some peripharals will have
> clocks in APB extension base.
> change pxa168-pwm to be pxa910-pwm for pxa910. It will fit the current
> pwm driver.
> 
> v3->v4:
> remove addtional clock name definition
> replace left __raw_xxx
> 
> v4->v5:
> change the format of the file
> 

Reviewed-by: Arnd Bergmann <arnd at arndb.de>

	Arnd


From haojian.zhuang at gmail.com  Mon Aug 20 01:49:37 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 20 Aug 2012 13:49:37 +0800
Subject: [PATCH 1/3] ARM: pxa: append the definition of CKENC
Message-ID: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com>

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb4..f4d48d2 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
 #define AICSR		__REG(0x41340008)	/* Application Subsystem Interrupt Control/Status Register */
 #define CKENA		__REG(0x4134000C)	/* A Clock Enable Register */
 #define CKENB		__REG(0x41340010)	/* B Clock Enable Register */
+#define CKENC		__REG(0x41340024)	/* C Clock Enable Register */
 #define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */
 
 #define ACCR_XPDIS		(1 << 31)	/* Core PLL Output Disable */
-- 
1.7.9.5



From haojian.zhuang at gmail.com  Mon Aug 20 01:49:38 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 20 Aug 2012 13:49:38 +0800
Subject: [PATCH 2/3] mtd: nand: append missing parameter and value
In-Reply-To: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com>
References: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1345441779-22632-2-git-send-email-haojian.zhuang@gmail.com>

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9c08691..616993a 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1035,7 +1035,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
 	struct pxa3xx_nand_host *host;
-	struct nand_chip *chip;
+	struct nand_chip *chip = NULL;
 	struct mtd_info *mtd;
 	struct resource *r;
 	int ret, irq, cs;
@@ -1245,7 +1245,7 @@ static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
 	return 0;
 }
 #else
-static inline int pxa3xx_nand_probe_dt(struct platform_device *)
+static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
 {
 	return 0;
 }
-- 
1.7.9.5



From haojian.zhuang at gmail.com  Mon Aug 20 01:49:39 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 20 Aug 2012 13:49:39 +0800
Subject: [PATCH 3/3] ARM: pxa: fix build issue while CONFIG_OF is disabled
In-Reply-To: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com>
References: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <1345441779-22632-3-git-send-email-haojian.zhuang@gmail.com>

arch/arm/mach-pxa/built-in.o: In function `pxa3xx_dt_init_irq':
saar.c:(.init.text+0x604): undefined reference to `pxa_dt_irq_init'

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 arch/arm/mach-pxa/pxa3xx.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 4a9d04a..ff9c957 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -402,11 +402,13 @@ void __init pxa3xx_init_irq(void)
 	pxa_init_irq(56, pxa3xx_set_wake);
 }
 
+#ifdef CONFIG_OF
 void __init pxa3xx_dt_init_irq(void)
 {
 	__pxa3xx_init_irq();
 	pxa_dt_irq_init(pxa3xx_set_wake);
 }
+#endif	/* CONFIG_OF */
 
 static struct map_desc pxa3xx_io_desc[] __initdata = {
 	{	/* Mem Ctl */
-- 
1.7.9.5



From haojian.zhuang at gmail.com  Mon Aug 20 01:55:23 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 20 Aug 2012 13:55:23 +0800
Subject: [GIT PULL][for 3.7] pull request for pxa/dt branch in arm-soc from
 arch-pxa git tree
Message-ID: <CAN1soZwqoOvk3f7jzQUbza3PH2houwE4ERFJFn480F9yzBqm_w@mail.gmail.com>

Hi Arnd & Olof,

Please help to merge these three patches into pxa/dt branch. Since
they're depend
on existing patch on pxa/dt branch, I didn't do rebase on v3.6-rc2.

Regards
Haojian

The following changes since commit 51931b37fcb17a2f48f726fd21b88e3af770ddc2:

  ARM: mmp: enable tauros2 cache in mmp2 dt (2012-08-16 16:17:10 +0800)

are available in the git repository at:

  git://github.com/hzhuang1/linux.git dt

for you to fetch changes up to e6c509c8ef85155bf504254399d758384a3b2e38:

  ARM: pxa: fix build issue while CONFIG_OF is disabled (2012-08-20
13:52:05 +0800)

----------------------------------------------------------------
Haojian Zhuang (3):
      ARM: pxa: append the definition of CKENC
      mtd: nand: append missing parameter and value
      ARM: pxa: fix build issue while CONFIG_OF is disabled

 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |    1 +
 arch/arm/mach-pxa/pxa3xx.c                   |    2 ++
 drivers/mtd/nand/pxa3xx_nand.c               |    4 ++--
 3 files changed, 5 insertions(+), 2 deletions(-)


From arnd at arndb.de  Mon Aug 20 02:04:18 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 06:04:18 +0000
Subject: [GIT PULL][for 3.7] pull request for pxa/dt branch in arm-soc
 from arch-pxa git tree
In-Reply-To: <CAN1soZwqoOvk3f7jzQUbza3PH2houwE4ERFJFn480F9yzBqm_w@mail.gmail.com>
References: <CAN1soZwqoOvk3f7jzQUbza3PH2houwE4ERFJFn480F9yzBqm_w@mail.gmail.com>
Message-ID: <201208200604.19142.arnd@arndb.de>

On Monday 20 August 2012, Haojian Zhuang wrote:
> Hi Arnd & Olof,
> 
> Please help to merge these three patches into pxa/dt branch. Since
> they're depend
> on existing patch on pxa/dt branch, I didn't do rebase on v3.6-rc2.

Ok, pulled into next/dt branch.

	Arnd


From m.szyprowski at samsung.com  Mon Aug 20 02:16:12 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 08:16:12 +0200
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous Memory
 Allocator
Message-ID: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>

Contiguous Memory Allocator requires only paging and MMU enabled not
particular CPU architectures, so there is no need for strict dependency
on CPU type. This enables to use CMA on some older ARM v5 systems which
also might need large contiguous blocks for the multimedia processing hw
modules.

Reported-by: Prabhakar Lad <prabhakar.csengg at gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..6ef75e2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -6,7 +6,7 @@ config ARM
 	select HAVE_DMA_API_DEBUG
 	select HAVE_IDE if PCI || ISA || PCMCIA
 	select HAVE_DMA_ATTRS
-	select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
+	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_MEMBLOCK
 	select RTC_LIB
 	select SYS_SUPPORTS_APM_EMULATION
-- 
1.7.1.569.g6f426



From anilkumar at ti.com  Mon Aug 20 02:27:01 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Mon, 20 Aug 2012 06:27:01 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <20120816140056.GK15365@opensource.wolfsonmicro.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>
 <20120816140056.GK15365@opensource.wolfsonmicro.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA19A81@DBDE01.ent.ti.com>

Hi Mark,

On Thu, Aug 16, 2012 at 19:30:56, Mark Brown wrote:
> On Thu, Aug 16, 2012 at 01:22:27PM +0000, AnilKumar, Chimata wrote:
> 
> > But problem here is single input supply battery/main is not sufficient.
> 
> What makes you say this?
> 
> > pmic->desc[i].supply_name = info->vin_name;
> > with this assignment regulator core searches for exact supply name vcc1 or
> > vcc2 etc if there are no matches then it will not register any regulators. 
> 
> Why does this mean you need multiple regulators?  A single regulator can
> of course supply multiple devices.

I got your point but tps65910 driver is failing if we add single fixed
regulator. Solution is driver needs to change or add multiple fixed
regulators.

Let's take this example

ocp {
        vcc5v_supply: fixedregulator at 0 {
                compatible = "regulator-fixed";
                regulator-name = "vcc5v";
                regulator-boot-on;
        };
};

/include/ "tps65910.dtsi"

&tps {
        regulators {
                vcc1-supply = <&vcc5v_supply>;
                vcc2-supply = <&vcc5v_supply>;
                vcc3-supply = <&vcc5v_supply>;
                vcc4-supply = <&vcc5v_supply>;
                vcc5-supply = <&vcc5v_supply>;
                vcc6-supply = <&vcc5v_supply>;
                vcc7-supply = <&vcc5v_supply>;
                vccio-supply = <&vcc5v_supply>;

                vrtc_reg: regulator at 0 { /* vrtc input is vcc7 */
                        regulator-always-on;
                };

                ... 
                ...
        };
};

These changes are added to am335x-evm.dts file after this change I
am seeing below error.

vrtc:
tps65910 0-002d: Failed to find supply vcc7
tps65910 0-002d: failed to register tps65910-pmic regulator

To get rid of this error we have to change the driver like this

if (info->vin_name) {
         snprintf(in_supply, 32, "%s-supply", info->vin_name);
         if (of_find_property(np, in_supply, 0))
                  pmic_plat_data->input_supply[idx] = info->vin_name;
}

And

pmic->desc[i].supply_name = pmic_plat_data->input_supply[i];

Regards
AnilKumar


From richard.genoud at gmail.com  Mon Aug 20 02:31:39 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 20 Aug 2012 08:31:39 +0200
Subject: [PATCH 5/8] UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
In-Reply-To: <20120819120804.15c33931@pixies.home.jungo.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>
 <20120819120804.15c33931@pixies.home.jungo.com>
Message-ID: <CACQ1gAgLirwiwiUOoL7ig7R_RpB8xDr2-g2gVOEUZNvAHB60pQ@mail.gmail.com>

Hi Shmulik,

2012/8/19 Shmulik Ladkani <shmulik.ladkani at gmail.com>:
> Hi Richard,
>
> On Fri, 17 Aug 2012 16:35:21 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
>> +     /*
>> +      * A value of 0 is forced to the default value to keep the same
>> +      * behavior between ubiattach command and module parameter
>> +      */
>
> Minor thing.
>
> Since the module parameter is not yet introduced (only in a later
> patch), and since last part of sentence isn't that important, I would
> simply state:
>
> +        * Use the default if max_beb_per1024 isn't provided.
>
That's right, I'll correct that in next version.
Thanks !


From Barry.Song at csr.com  Mon Aug 20 02:42:37 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 14:42:37 +0800
Subject: [PATCH v4 2/2] clk: prima2: move from arch/arm/mach to drivers/clk
In-Reply-To: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>
References: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345444957-16039-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Signed-off-by: Barry Song <Baohua.Song at csr.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
 -v4: rename to clk-prima2 as we will have clk-marco or others

 arch/arm/mach-prima2/Makefile                      |    1 -
 drivers/clk/Makefile                               |    1 +
 .../clock.c => drivers/clk/clk-prima2.c            |    0
 3 files changed, 1 insertions(+), 1 deletions(-)
 rename arch/arm/mach-prima2/clock.c => drivers/clk/clk-prima2.c (100%)

diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd160..841847d 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,6 +1,5 @@
 obj-y := timer.o
 obj-y += irq.o
-obj-y += clock.o
 obj-y += rstc.o
 obj-y += prima2.o
 obj-y += rtciobrg.o
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..d4c7253 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_ARCH_PRIMA2)	+= clk-prima2.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/arch/arm/mach-prima2/clock.c b/drivers/clk/clk-prima2.c
similarity index 100%
rename from arch/arm/mach-prima2/clock.c
rename to drivers/clk/clk-prima2.c
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Mon Aug 20 02:42:36 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 14:42:36 +0800
Subject: [PATCH v4 1/2] ARM: PRIMA2: convert to common clk and finish full clk
 tree
Message-ID: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>

From: Binghua Duan <Binghua.Duan at csr.com>

Commit 02c981c07bc95ac1e only implements a little part of primaII clk tree
due to common clk framework was not ready at that time.
This patch converts the old driver to common clk and finish the full clk
tree.

Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v4: fix a typo

 arch/arm/Kconfig              |    2 +-
 arch/arm/mach-prima2/clock.c  | 1189 ++++++++++++++++++++++++++++++++---------
 arch/arm/mach-prima2/prima2.c |    1 -
 arch/arm/mach-prima2/timer.c  |    8 +-
 4 files changed, 933 insertions(+), 267 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..fb60148 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -413,7 +413,7 @@ config ARCH_PRIMA2
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
+	select COMMON_CLK
 	select GENERIC_IRQ_CHIP
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
index aebad7e..517874f 100644
--- a/arch/arm/mach-prima2/clock.c
+++ b/arch/arm/mach-prima2/clock.c
@@ -8,16 +8,12 @@
 
 #include <linux/module.h>
 #include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
 #include <linux/io.h>
-#include <linux/clkdev.h>
 #include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/of_address.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
+#include <linux/syscore_ops.h>
 
 #define SIRFSOC_CLKC_CLK_EN0    0x0000
 #define SIRFSOC_CLKC_CLK_EN1    0x0004
@@ -29,7 +25,7 @@
 #define SIRFSOC_CLKC_DSP_CFG    0x0028
 #define SIRFSOC_CLKC_GFX_CFG    0x002c
 #define SIRFSOC_CLKC_MM_CFG     0x0030
-#define SIRFSOC_LKC_LCD_CFG     0x0034
+#define SIRFSOC_CLKC_LCD_CFG     0x0034
 #define SIRFSOC_CLKC_MMC_CFG    0x0038
 #define SIRFSOC_CLKC_PLL1_CFG0  0x0040
 #define SIRFSOC_CLKC_PLL2_CFG0  0x0044
@@ -40,68 +36,82 @@
 #define SIRFSOC_CLKC_PLL1_CFG2  0x0058
 #define SIRFSOC_CLKC_PLL2_CFG2  0x005c
 #define SIRFSOC_CLKC_PLL3_CFG2  0x0060
+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
+#define SIRFSOC_USBPHY_PLL_POWERDOWN  BIT(1)
+#define SIRFSOC_USBPHY_PLL_BYPASS     BIT(2)
+#define SIRFSOC_USBPHY_PLL_LOCK       BIT(3)
 
-#define SIRFSOC_CLOCK_VA_BASE		SIRFSOC_VA(0x005000)
+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
 
 #define KHZ     1000
 #define MHZ     (KHZ * KHZ)
 
-struct clk_ops {
-	unsigned long (*get_rate)(struct clk *clk);
-	long (*round_rate)(struct clk *clk, unsigned long rate);
-	int (*set_rate)(struct clk *clk, unsigned long rate);
-	int (*enable)(struct clk *clk);
-	int (*disable)(struct clk *clk);
-	struct clk *(*get_parent)(struct clk *clk);
-	int (*set_parent)(struct clk *clk, struct clk *parent);
+/*
+ * SiRFprimaII clock controller
+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
+ * - 3 standard configurable plls: pll1, pll2 & pll3
+ * - 2 exclusive plls: usb phy pll and sata phy pll
+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
+ *     display and sdphy.
+ *     Each clock domain can select its own clock source from five clock sources,
+ *     X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
+ *     clock of the group clock.
+ *     - dsp domain: gps, mf
+ *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
+ *     - sys domain: security
+ */
+
+struct clk_pll {
+	struct clk_hw hw;
+	unsigned short regofs;  /* register offset */
 };
 
-struct clk {
-	struct clk *parent;     /* parent clk */
-	unsigned long rate;     /* clock rate in Hz */
-	signed char usage;      /* clock enable count */
+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
+
+struct clk_dmn {
+	struct clk_hw hw;
 	signed char enable_bit; /* enable bit: 0 ~ 63 */
 	unsigned short regofs;  /* register offset */
-	struct clk_ops *ops;    /* clock operation */
 };
 
-static DEFINE_SPINLOCK(clocks_lock);
+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
+
+struct clk_std {
+	struct clk_hw hw;
+	signed char enable_bit; /* enable bit: 0 ~ 63 */
+};
+
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw);
+static int std_clk_enable(struct clk_hw *hw);
+static void std_clk_disable(struct clk_hw *hw);
 
 static inline unsigned long clkc_readl(unsigned reg)
 {
-	return readl(SIRFSOC_CLOCK_VA_BASE + reg);
+	return readl(sirfsoc_clk_vbase + reg);
 }
 
 static inline void clkc_writel(u32 val, unsigned reg)
 {
-	writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
+	writel(val, sirfsoc_clk_vbase + reg);
 }
 
 /*
- * osc_rtc - real time oscillator - 32.768KHz
- * osc_sys - high speed oscillator - 26MHz
- */
-
-static struct clk clk_rtc = {
-	.rate = 32768,
-};
-
-static struct clk clk_osc = {
-	.rate = 26 * MHZ,
-};
-
-/*
  * std pll
  */
-static unsigned long std_pll_get_rate(struct clk *clk)
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
 {
-	unsigned long fin = clk_get_rate(clk->parent);
+	unsigned long fin = parent_rate;
+	struct clk_pll *clk = to_pllclk(hw);
 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
 		SIRFSOC_CLKC_PLL1_CFG0;
 
 	if (clkc_readl(regcfg2) & BIT(2)) {
 		/* pll bypass mode */
-		clk->rate = fin;
+		return fin;
 	} else {
 		/* fout = fin * nf / nr / od */
 		u32 cfg0 = clkc_readl(clk->regofs);
@@ -109,14 +119,41 @@ static unsigned long std_pll_get_rate(struct clk *clk)
 		u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
 		u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
 		WARN_ON(fin % MHZ);
-		clk->rate = fin / MHZ * nf / nr / od * MHZ;
+		return fin / MHZ * nf / nr / od * MHZ;
 	}
+}
+
+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin, nf, nr, od;
+
+	/*
+	 * fout = fin * nf / (nr * od);
+	 * set od = 1, nr = fin/MHz, so fout = nf * MHz
+	 */
+	rate = rate - rate % MHZ;
+
+	nf = rate / MHZ;
+	if (nf > BIT(13))
+		nf = BIT(13);
+	if (nf < 1)
+		nf = 1;
 
-	return clk->rate;
+	fin = *parent_rate;
+
+	nr = fin / MHZ;
+	if (nr > BIT(6))
+		nr = BIT(6);
+	od = 1;
+
+	return fin * nf / (nr * od);
 }
 
-static int std_pll_set_rate(struct clk *clk, unsigned long rate)
+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
 {
+	struct clk_pll *clk = to_pllclk(hw);
 	unsigned long fin, nf, nr, od, reg;
 
 	/*
@@ -128,7 +165,7 @@ static int std_pll_set_rate(struct clk *clk, unsigned long rate)
 	if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
 		return -EINVAL;
 
-	fin = clk_get_rate(clk->parent);
+	fin = parent_rate;
 	BUG_ON(fin < MHZ);
 
 	nr = fin / MHZ;
@@ -146,76 +183,163 @@ static int std_pll_set_rate(struct clk *clk, unsigned long rate)
 	while (!(clkc_readl(reg) & BIT(6)))
 		cpu_relax();
 
-	clk->rate = 0; /* set to zero will force recalculation */
 	return 0;
 }
 
 static struct clk_ops std_pll_ops = {
-	.get_rate = std_pll_get_rate,
-	.set_rate = std_pll_set_rate,
+	.recalc_rate = pll_clk_recalc_rate,
+	.round_rate = pll_clk_round_rate,
+	.set_rate = pll_clk_set_rate,
 };
 
-static struct clk clk_pll1 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
+static const char *pll_clk_parents[] = {
+	"osc",
+};
+
+static struct clk_init_data clk_pll1_init = {
+	.name = "pll1",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
 };
 
-static struct clk clk_pll2 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
+static struct clk_init_data clk_pll2_init = {
+	.name = "pll2",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
 };
 
-static struct clk clk_pll3 = {
-	.parent = &clk_osc,
-	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
+static struct clk_init_data clk_pll3_init = {
+	.name = "pll3",
 	.ops = &std_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_pll clk_pll1 = {
+	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
+	.hw = {
+		.init = &clk_pll1_init,
+	},
+};
+
+static struct clk_pll clk_pll2 = {
+	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
+	.hw = {
+		.init = &clk_pll2_init,
+	},
+};
+
+static struct clk_pll clk_pll3 = {
+	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
+	.hw = {
+		.init = &clk_pll3_init,
+	},
 };
 
 /*
- * clock domains - cpu, mem, sys/io
+ * usb uses specified pll
  */
 
-static struct clk clk_mem;
+static int usb_pll_clk_enable(struct clk_hw *hw)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
+			SIRFSOC_USBPHY_PLL_LOCK))
+		cpu_relax();
+
+	return 0;
+}
+
+static void usb_pll_clk_disable(struct clk_hw *clk)
+{
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+	writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+}
 
-static struct clk *dmn_get_parent(struct clk *clk)
+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
-	struct clk *clks[] = {
-		&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-	};
+	u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+	return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
+}
+
+static struct clk_ops usb_pll_ops = {
+	.enable = usb_pll_clk_enable,
+	.disable = usb_pll_clk_disable,
+	.recalc_rate = usb_pll_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_usb_pll_init = {
+	.name = "usb_pll",
+	.ops = &usb_pll_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw usb_pll_clk_hw = {
+	.init = &clk_usb_pll_init,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io, dsp, gfx
+ */
+
+static const char *dmn_clk_parents[] = {
+	"rtc",
+	"osc",
+	"pll1",
+	"pll2",
+	"pll3",
+};
+
+static u8 dmn_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_dmn *clk = to_dmnclk(hw);
 	u32 cfg = clkc_readl(clk->regofs);
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return 4;
+
 	WARN_ON((cfg & (BIT(3) - 1)) > 4);
-	return clks[cfg & (BIT(3) - 1)];
+
+	return cfg & (BIT(3) - 1);
 }
 
-static int dmn_set_parent(struct clk *clk, struct clk *parent)
+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
 {
-	const struct clk *clks[] = {
-		&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
-	};
+	struct clk_dmn *clk = to_dmnclk(hw);
 	u32 cfg = clkc_readl(clk->regofs);
-	int i;
-	for (i = 0; i < ARRAY_SIZE(clks); i++) {
-		if (clks[i] == parent) {
-			cfg &= ~(BIT(3) - 1);
-			clkc_writel(cfg | i, clk->regofs);
-			/* BIT(3) - switching status: 1 - busy, 0 - done */
-			while (clkc_readl(clk->regofs) & BIT(3))
-				cpu_relax();
-			return 0;
-		}
-	}
-	return -EINVAL;
+
+	/* parent of io domain can only be pll3 */
+	if (strcmp(hw->init->name, "io") == 0)
+		return -EINVAL;
+
+	cfg &= ~(BIT(3) - 1);
+	clkc_writel(cfg | parent, clk->regofs);
+	/* BIT(3) - switching status: 1 - busy, 0 - done */
+	while (clkc_readl(clk->regofs) & BIT(3))
+		cpu_relax();
+
+	return 0;
 }
 
-static unsigned long dmn_get_rate(struct clk *clk)
+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
+
 {
-	unsigned long fin = clk_get_rate(clk->parent);
+	unsigned long fin = parent_rate;
+	struct clk_dmn *clk = to_dmnclk(hw);
+
 	u32 cfg = clkc_readl(clk->regofs);
+
 	if (cfg & BIT(24)) {
 		/* fcd bypass mode */
-		clk->rate = fin;
+		return fin;
 	} else {
 		/*
 		 * wait count: bit[19:16], hold count: bit[23:20]
@@ -223,19 +347,40 @@ static unsigned long dmn_get_rate(struct clk *clk)
 		u32 wait = (cfg >> 16) & (BIT(4) - 1);
 		u32 hold = (cfg >> 20) & (BIT(4) - 1);
 
-		clk->rate = fin / (wait + hold + 2);
+		return fin / (wait + hold + 2);
 	}
+}
+
+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long *parent_rate)
+{
+	unsigned long fin;
+	unsigned ratio, wait, hold;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+	fin = *parent_rate;
+	ratio = fin / rate;
+
+	if (ratio < 2)
+		ratio = 2;
+	if (ratio > BIT(bits + 1))
+		ratio = BIT(bits + 1);
 
-	return clk->rate;
+	wait = (ratio >> 1) - 1;
+	hold = ratio - wait - 2;
+
+	return fin / (wait + hold + 2);
 }
 
-static int dmn_set_rate(struct clk *clk, unsigned long rate)
+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+	unsigned long parent_rate)
 {
+	struct clk_dmn *clk = to_dmnclk(hw);
 	unsigned long fin;
 	unsigned ratio, wait, hold, reg;
-	unsigned bits = (clk == &clk_mem) ? 3 : 4;
+	unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
 
-	fin = clk_get_rate(clk->parent);
+	fin = parent_rate;
 	ratio = fin / rate;
 
 	if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
@@ -255,256 +400,772 @@ static int dmn_set_rate(struct clk *clk, unsigned long rate)
 	while (clkc_readl(clk->regofs) & BIT(25))
 		cpu_relax();
 
-	clk->rate = 0; /* set to zero will force recalculation */
-
 	return 0;
 }
 
-/*
- * cpu clock has no FCD register in Prima2, can only change pll
- */
-static int cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret1, ret2;
-	struct clk *cur_parent, *tmp_parent;
+static struct clk_ops msi_ops = {
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
+};
 
-	cur_parent = dmn_get_parent(clk);
-	BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
+static struct clk_init_data clk_mem_init = {
+	.name = "mem",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	/* switch to tmp pll before setting parent clock's rate */
-	tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
-	ret1 = dmn_set_parent(clk, tmp_parent);
-	BUG_ON(ret1);
+static struct clk_dmn clk_mem = {
+	.regofs = SIRFSOC_CLKC_MEM_CFG,
+	.hw = {
+		.init = &clk_mem_init,
+	},
+};
 
-	ret2 = clk_set_rate(cur_parent, rate);
+static struct clk_init_data clk_sys_init = {
+	.name = "sys",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_GATE,
+};
 
-	ret1 = dmn_set_parent(clk, cur_parent);
+static struct clk_dmn clk_sys = {
+	.regofs = SIRFSOC_CLKC_SYS_CFG,
+	.hw = {
+		.init = &clk_sys_init,
+	},
+};
 
-	clk->rate = 0; /* set to zero will force recalculation */
+static struct clk_init_data clk_io_init = {
+	.name = "io",
+	.ops = &msi_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	return ret2 ? ret2 : ret1;
-}
+static struct clk_dmn clk_io = {
+	.regofs = SIRFSOC_CLKC_IO_CFG,
+	.hw = {
+		.init = &clk_io_init,
+	},
+};
 
 static struct clk_ops cpu_ops = {
-	.get_parent = dmn_get_parent,
-	.set_parent = dmn_set_parent,
-	.set_rate = cpu_set_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
 };
 
-static struct clk clk_cpu = {
-	.parent = &clk_pll1,
-	.regofs = SIRFSOC_CLKC_CPU_CFG,
+static struct clk_init_data clk_cpu_init = {
+	.name = "cpu",
 	.ops = &cpu_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+	.flags = CLK_SET_RATE_PARENT,
 };
 
+static struct clk_dmn clk_cpu = {
+	.regofs = SIRFSOC_CLKC_CPU_CFG,
+	.hw = {
+		.init = &clk_cpu_init,
+	},
+};
 
-static struct clk_ops msi_ops = {
-	.set_rate = dmn_set_rate,
-	.get_rate = dmn_get_rate,
-	.set_parent = dmn_set_parent,
-	.get_parent = dmn_get_parent,
+static struct clk_ops dmn_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+	.set_rate = dmn_clk_set_rate,
+	.round_rate = dmn_clk_round_rate,
+	.recalc_rate = dmn_clk_recalc_rate,
+	.set_parent = dmn_clk_set_parent,
+	.get_parent = dmn_clk_get_parent,
 };
 
-static struct clk clk_mem = {
-	.parent = &clk_pll2,
-	.regofs = SIRFSOC_CLKC_MEM_CFG,
-	.ops = &msi_ops,
+/* dsp, gfx, mm, lcd and vpp domain */
+
+static struct clk_init_data clk_dsp_init = {
+	.name = "dsp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
 };
 
-static struct clk clk_sys = {
-	.parent = &clk_pll3,
-	.regofs = SIRFSOC_CLKC_SYS_CFG,
-	.ops = &msi_ops,
+static struct clk_dmn clk_dsp = {
+	.regofs = SIRFSOC_CLKC_DSP_CFG,
+	.enable_bit = 0,
+	.hw = {
+		.init = &clk_dsp_init,
+	},
 };
 
-static struct clk clk_io = {
-	.parent = &clk_pll3,
-	.regofs = SIRFSOC_CLKC_IO_CFG,
-	.ops = &msi_ops,
+static struct clk_init_data clk_gfx_init = {
+	.name = "gfx",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
 };
 
-/*
- * on-chip clock sets
- */
-static struct clk_lookup onchip_clks[] = {
-	{
-		.dev_id = "rtc",
-		.clk = &clk_rtc,
-	}, {
-		.dev_id = "osc",
-		.clk = &clk_osc,
-	}, {
-		.dev_id = "pll1",
-		.clk = &clk_pll1,
-	}, {
-		.dev_id = "pll2",
-		.clk = &clk_pll2,
-	}, {
-		.dev_id = "pll3",
-		.clk = &clk_pll3,
-	}, {
-		.dev_id = "cpu",
-		.clk = &clk_cpu,
-	}, {
-		.dev_id = "mem",
-		.clk = &clk_mem,
-	}, {
-		.dev_id = "sys",
-		.clk = &clk_sys,
-	}, {
-		.dev_id = "io",
-		.clk = &clk_io,
-	},
-};
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
+static struct clk_dmn clk_gfx = {
+	.regofs = SIRFSOC_CLKC_GFX_CFG,
+	.enable_bit = 8,
+	.hw = {
+		.init = &clk_gfx_init,
+	},
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+static struct clk_init_data clk_mm_init = {
+	.name = "mm",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->parent)
-		clk_enable(clk->parent);
+static struct clk_dmn clk_mm = {
+	.regofs = SIRFSOC_CLKC_MM_CFG,
+	.enable_bit = 9,
+	.hw = {
+		.init = &clk_mm_init,
+	},
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (!clk->usage++ && clk->ops && clk->ops->enable)
-		clk->ops->enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
+static struct clk_init_data clk_lcd_init = {
+	.name = "lcd",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
+static struct clk_dmn clk_lcd = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 10,
+	.hw = {
+		.init = &clk_lcd_init,
+	},
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return;
+static struct clk_init_data clk_vpp_init = {
+	.name = "vpp",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	WARN_ON(!clk->usage);
+static struct clk_dmn clk_vpp = {
+	.regofs = SIRFSOC_CLKC_LCD_CFG,
+	.enable_bit = 11,
+	.hw = {
+		.init = &clk_vpp_init,
+	},
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (--clk->usage == 0 && clk->ops && clk->ops->disable)
-		clk->ops->disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
+static struct clk_init_data clk_mmc01_init = {
+	.name = "mmc01",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->parent)
-		clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
+static struct clk_dmn clk_mmc01 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 59,
+	.hw = {
+		.init = &clk_mmc01_init,
+	},
+};
 
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return 0;
+static struct clk_init_data clk_mmc23_init = {
+	.name = "mmc23",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	if (clk->rate)
-		return clk->rate;
+static struct clk_dmn clk_mmc23 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 60,
+	.hw = {
+		.init = &clk_mmc23_init,
+	},
+};
 
-	if (clk->ops && clk->ops->get_rate)
-		return clk->ops->get_rate(clk);
+static struct clk_init_data clk_mmc45_init = {
+	.name = "mmc45",
+	.ops = &dmn_ops,
+	.parent_names = dmn_clk_parents,
+	.num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
 
-	return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
+static struct clk_dmn clk_mmc45 = {
+	.regofs = SIRFSOC_CLKC_MMC_CFG,
+	.enable_bit = 61,
+	.hw = {
+		.init = &clk_mmc45_init,
+	},
+};
 
-long clk_round_rate(struct clk *clk, unsigned long rate)
+/*
+ * peripheral controllers in io domain
+ */
+
+static int std_clk_is_enabled(struct clk_hw *hw)
 {
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return 0;
+	u32 reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (clk->ops && clk->ops->round_rate)
-		return clk->ops->round_rate(clk, rate);
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	return 0;
+	return !!(clkc_readl(reg) & BIT(bit));
 }
-EXPORT_SYMBOL(clk_round_rate);
 
-int clk_set_rate(struct clk *clk, unsigned long rate)
+static int std_clk_enable(struct clk_hw *hw)
 {
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (!clk->ops || !clk->ops->set_rate)
-		return -EINVAL;
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	return clk->ops->set_rate(clk, rate);
+	val = clkc_readl(reg) | BIT(bit);
+	clkc_writel(val, reg);
+	return 0;
 }
-EXPORT_SYMBOL(clk_set_rate);
 
-int clk_set_parent(struct clk *clk, struct clk *parent)
+static void std_clk_disable(struct clk_hw *hw)
 {
-	int ret;
-	unsigned long flags;
+	u32 val, reg;
+	int bit;
+	struct clk_std *clk = to_stdclk(hw);
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return -EINVAL;
+	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
 
-	if (!clk->ops || !clk->ops->set_parent)
-		return -EINVAL;
+	bit = clk->enable_bit % 32;
+	reg = clk->enable_bit / 32;
+	reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	ret = clk->ops->set_parent(clk, parent);
-	if (!ret) {
-		parent->usage += clk->usage;
-		clk->parent->usage -= clk->usage;
-		BUG_ON(clk->parent->usage < 0);
-		clk->parent = parent;
-	}
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return ret;
+	val = clkc_readl(reg) & ~BIT(bit);
+	clkc_writel(val, reg);
 }
-EXPORT_SYMBOL(clk_set_parent);
 
-struct clk *clk_get_parent(struct clk *clk)
-{
-	unsigned long flags;
+static const char *std_clk_io_parents[] = {
+	"io",
+};
 
-	if (unlikely(IS_ERR_OR_NULL(clk)))
-		return NULL;
+static struct clk_ops ios_ops = {
+	.is_enabled = std_clk_is_enabled,
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+};
 
-	if (!clk->ops || !clk->ops->get_parent)
-		return clk->parent;
+static struct clk_init_data clk_dmac0_init = {
+	.name = "dmac0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
 
-	spin_lock_irqsave(&clocks_lock, flags);
-	clk->parent = clk->ops->get_parent(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
+static struct clk_std clk_dmac0 = {
+	.enable_bit = 32,
+	.hw = {
+		.init = &clk_dmac0_init,
+	},
+};
 
-static void __init sirfsoc_clk_init(void)
-{
-	clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
-}
+static struct clk_init_data clk_dmac1_init = {
+	.name = "dmac1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac1 = {
+	.enable_bit = 33,
+	.hw = {
+		.init = &clk_dmac1_init,
+	},
+};
+
+static struct clk_init_data clk_nand_init = {
+	.name = "nand",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_nand = {
+	.enable_bit = 34,
+	.hw = {
+		.init = &clk_nand_init,
+	},
+};
+
+static struct clk_init_data clk_audio_init = {
+	.name = "audio",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_audio = {
+	.enable_bit = 35,
+	.hw = {
+		.init = &clk_audio_init,
+	},
+};
+
+static struct clk_init_data clk_uart0_init = {
+	.name = "uart0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart0 = {
+	.enable_bit = 36,
+	.hw = {
+		.init = &clk_uart0_init,
+	},
+};
+
+static struct clk_init_data clk_uart1_init = {
+	.name = "uart1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart1 = {
+	.enable_bit = 37,
+	.hw = {
+		.init = &clk_uart1_init,
+	},
+};
+
+static struct clk_init_data clk_uart2_init = {
+	.name = "uart2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart2 = {
+	.enable_bit = 38,
+	.hw = {
+		.init = &clk_uart2_init,
+	},
+};
+
+static struct clk_init_data clk_usp0_init = {
+	.name = "usp0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp0 = {
+	.enable_bit = 39,
+	.hw = {
+		.init = &clk_usp0_init,
+	},
+};
+
+static struct clk_init_data clk_usp1_init = {
+	.name = "usp1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp1 = {
+	.enable_bit = 40,
+	.hw = {
+		.init = &clk_usp1_init,
+	},
+};
+
+static struct clk_init_data clk_usp2_init = {
+	.name = "usp2",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp2 = {
+	.enable_bit = 41,
+	.hw = {
+		.init = &clk_usp2_init,
+	},
+};
+
+static struct clk_init_data clk_vip_init = {
+	.name = "vip",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_vip = {
+	.enable_bit = 42,
+	.hw = {
+		.init = &clk_vip_init,
+	},
+};
+
+static struct clk_init_data clk_spi0_init = {
+	.name = "spi0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi0 = {
+	.enable_bit = 43,
+	.hw = {
+		.init = &clk_spi0_init,
+	},
+};
+
+static struct clk_init_data clk_spi1_init = {
+	.name = "spi1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi1 = {
+	.enable_bit = 44,
+	.hw = {
+		.init = &clk_spi1_init,
+	},
+};
+
+static struct clk_init_data clk_tsc_init = {
+	.name = "tsc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_tsc = {
+	.enable_bit = 45,
+	.hw = {
+		.init = &clk_tsc_init,
+	},
+};
+
+static struct clk_init_data clk_i2c0_init = {
+	.name = "i2c0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c0 = {
+	.enable_bit = 46,
+	.hw = {
+		.init = &clk_i2c0_init,
+	},
+};
+
+static struct clk_init_data clk_i2c1_init = {
+	.name = "i2c1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c1 = {
+	.enable_bit = 47,
+	.hw = {
+		.init = &clk_i2c1_init,
+	},
+};
+
+static struct clk_init_data clk_pwmc_init = {
+	.name = "pwmc",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pwmc = {
+	.enable_bit = 48,
+	.hw = {
+		.init = &clk_pwmc_init,
+	},
+};
+
+static struct clk_init_data clk_efuse_init = {
+	.name = "efuse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_efuse = {
+	.enable_bit = 49,
+	.hw = {
+		.init = &clk_efuse_init,
+	},
+};
+
+static struct clk_init_data clk_pulse_init = {
+	.name = "pulse",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pulse = {
+	.enable_bit = 50,
+	.hw = {
+		.init = &clk_pulse_init,
+	},
+};
+
+static const char *std_clk_dsp_parents[] = {
+	"dsp",
+};
+
+static struct clk_init_data clk_gps_init = {
+	.name = "gps",
+	.ops = &ios_ops,
+	.parent_names = std_clk_dsp_parents,
+	.num_parents = ARRAY_SIZE(std_clk_dsp_parents),
+};
+
+static struct clk_std clk_gps = {
+	.enable_bit = 1,
+	.hw = {
+		.init = &clk_gps_init,
+	},
+};
+
+static struct clk_init_data clk_mf_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_io_parents,
+	.num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_mf = {
+	.enable_bit = 2,
+	.hw = {
+		.init = &clk_mf_init,
+	},
+};
+
+static const char *std_clk_sys_parents[] = {
+	"sys",
+};
+
+static struct clk_init_data clk_security_init = {
+	.name = "mf",
+	.ops = &ios_ops,
+	.parent_names = std_clk_sys_parents,
+	.num_parents = ARRAY_SIZE(std_clk_sys_parents),
+};
+
+static struct clk_std clk_security = {
+	.enable_bit = 19,
+	.hw = {
+		.init = &clk_security_init,
+	},
+};
+
+static const char *std_clk_usb_parents[] = {
+	"usb_pll",
+};
+
+static struct clk_init_data clk_usb0_init = {
+	.name = "usb0",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb0 = {
+	.enable_bit = 16,
+	.hw = {
+		.init = &clk_usb0_init,
+	},
+};
+
+static struct clk_init_data clk_usb1_init = {
+	.name = "usb1",
+	.ops = &ios_ops,
+	.parent_names = std_clk_usb_parents,
+	.num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb1 = {
+	.enable_bit = 17,
+	.hw = {
+		.init = &clk_usb1_init,
+	},
+};
 
 static struct of_device_id clkc_ids[] = {
 	{ .compatible = "sirf,prima2-clkc" },
 	{},
 };
 
+static struct of_device_id rsc_ids[] = {
+	{ .compatible = "sirf,prima2-rsc" },
+	{},
+};
+
 void __init sirfsoc_of_clk_init(void)
 {
+	struct clk *clk;
 	struct device_node *np;
-	struct resource res;
-	struct map_desc sirfsoc_clkc_iodesc = {
-		.virtual = SIRFSOC_CLOCK_VA_BASE,
-		.type    = MT_DEVICE,
-	};
 
 	np = of_find_matching_node(NULL, clkc_ids);
 	if (!np)
 		panic("unable to find compatible clkc node in dtb\n");
 
-	if (of_address_to_resource(np, 0, &res))
-		panic("unable to find clkc range in dtb");
+	sirfsoc_clk_vbase = of_iomap(np, 0);
+	if (!sirfsoc_clk_vbase)
+		panic("unable to map clkc registers\n");
+
 	of_node_put(np);
 
-	sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
-	sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
+	np = of_find_matching_node(NULL, rsc_ids);
+	if (!np)
+		panic("unable to find compatible rsc node in dtb\n");
+
+	sirfsoc_rsc_vbase = of_iomap(np, 0);
+	if (!sirfsoc_rsc_vbase)
+		panic("unable to map rsc registers\n");
+
+	of_node_put(np);
 
-	iotable_init(&sirfsoc_clkc_iodesc, 1);
 
-	sirfsoc_clk_init();
+	/* These are always available (RTC and 26MHz OSC)*/
+	clk = clk_register_fixed_rate(NULL, "rtc", NULL,
+		CLK_IS_ROOT, 32768);
+	BUG_ON(!clk);
+	clk = clk_register_fixed_rate(NULL, "osc", NULL,
+		CLK_IS_ROOT, 26000000);
+	BUG_ON(!clk);
+
+	clk = clk_register(NULL, &clk_pll1.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll2.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_pll3.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mem.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_sys.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_security.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b8030000.security");
+	clk = clk_register(NULL, &clk_dsp.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_gps.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a8010000.gps");
+	clk = clk_register(NULL, &clk_mf.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_io.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "io");
+	clk = clk_register(NULL, &clk_cpu.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "cpu");
+	clk = clk_register(NULL, &clk_uart0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0050000.uart");
+	clk = clk_register(NULL, &clk_uart1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0060000.uart");
+	clk = clk_register(NULL, &clk_uart2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0070000.uart");
+	clk = clk_register(NULL, &clk_tsc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0110000.tsc");
+	clk = clk_register(NULL, &clk_i2c0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.i2c");
+	clk = clk_register(NULL, &clk_i2c1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.i2c");
+	clk = clk_register(NULL, &clk_spi0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00d0000.spi");
+	clk = clk_register(NULL, &clk_spi1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0170000.spi");
+	clk = clk_register(NULL, &clk_pwmc.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0130000.pwm");
+	clk = clk_register(NULL, &clk_efuse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0140000.efusesys");
+	clk = clk_register(NULL, &clk_pulse.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0150000.pulsec");
+	clk = clk_register(NULL, &clk_dmac0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
+	clk = clk_register(NULL, &clk_dmac1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
+	clk = clk_register(NULL, &clk_nand.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0030000.nand");
+	clk = clk_register(NULL, &clk_audio.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0040000.audio");
+	clk = clk_register(NULL, &clk_usp0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0080000.usp");
+	clk = clk_register(NULL, &clk_usp1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b0090000.usp");
+	clk = clk_register(NULL, &clk_usp2.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00a0000.usp");
+	clk = clk_register(NULL, &clk_vip.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00c0000.vip");
+	clk = clk_register(NULL, &clk_gfx.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "98000000.graphics");
+	clk = clk_register(NULL, &clk_mm.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "a0000000.multimedia");
+	clk = clk_register(NULL, &clk_lcd.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90010000.display");
+	clk = clk_register(NULL, &clk_vpp.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "90020000.vpp");
+	clk = clk_register(NULL, &clk_mmc01.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc23.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_mmc45.hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &usb_pll_clk_hw);
+	BUG_ON(!clk);
+	clk = clk_register(NULL, &clk_usb0.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00e0000.usb");
+	clk = clk_register(NULL, &clk_usb1.hw);
+	BUG_ON(!clk);
+	clk_register_clkdev(clk, NULL, "b00f0000.usb");
 }
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index 8f0429d..e9a17ae 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -38,7 +38,6 @@ static const char *prima2cb_dt_match[] __initdata = {
 MACHINE_START(PRIMA2_EVB, "prima2cb")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.atag_offset	= 0x100,
-	.init_early     = sirfsoc_of_clk_init,
 	.map_io         = sirfsoc_map_lluart,
 	.init_irq	= sirfsoc_of_irq_init,
 	.timer		= &sirfsoc_timer,
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107..d95bf25 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
 #include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+
 #define SIRFSOC_TIMER_COUNTER_LO	0x0000
 #define SIRFSOC_TIMER_COUNTER_HI	0x0004
 #define SIRFSOC_TIMER_MATCH_0		0x0008
@@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
 static void __init sirfsoc_timer_init(void)
 {
 	unsigned long rate;
+	struct clk *clk;
+
+	/* initialize clocking early, we want to set the OS timer */
+	sirfsoc_of_clk_init();
 
 	/* timer's input clock is io clock */
-	struct clk *clk = clk_get_sys("io", NULL);
+	clk = clk_get_sys("io", NULL);
 
 	BUG_ON(IS_ERR(clk));
 
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From tony at atomide.com  Mon Aug 20 02:57:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Sun, 19 Aug 2012 23:57:41 -0700
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <CAPo=G1w5N5GVra7TK=En9xnaFmNNP1Zb7g2tZSjg8CO8wewOwA@mail.gmail.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120817130723.GZ11011@atomide.com> <502E43BC.30708@bitmer.com>
 <502E4F2B.6060403@ti.com> <20120818060810.GH11011@atomide.com>
 <CAPo=G1w5N5GVra7TK=En9xnaFmNNP1Zb7g2tZSjg8CO8wewOwA@mail.gmail.com>
Message-ID: <20120820065740.GK11011@atomide.com>

* Ujfalusi, Peter <peter.ujfalusi at ti.com> [120818 08:58]:
> Hi Tony,
> 
> On Sat, Aug 18, 2012 at 8:08 AM, Tony Lindgren <tony at atomide.com> wrote:
> > Thanks, is this patch still correct so it does not try to enable FIFO
> > for 2420?
> 
> Yes it only enables the FIFO for 2430, 2420 is not affected.

OK thanks for the clarification.

Tony


From arnd at arndb.de  Mon Aug 20 03:02:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 07:02:35 +0000
Subject: [GIT PULL] arm-soc: bug fixes for v3.6-rc3
Message-ID: <201208200702.35629.arnd@arndb.de>

Hi Linus,

Please pull the latest fixes from the arm-soc tree. Since most patches
came in after I sent out the previous pull request but before -rc2, the
branch is based on the last commit you pulled from me, in case you are
wondering.

	Arnd

The following changes since commit de9234306bb28fe6c8c3bb908e3f9956f5276a02:

  ARM: davinci: remove broken ntosd2_init_i2c (2012-08-10 13:14:36 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus

for you to fetch changes up to 8a211d362cc94df2bb42323ab13d258650529bec:

  Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes (2012-08-16 10:10:15 +0200)

----------------------------------------------------------------

arm-soc: bug fixes for v3.6-rc3

The bug fixes this time are mostly for the TI omap platforms, but there
are also a couple for the various Marvell platforms.

----------------------------------------------------------------
Afzal Mohammed (1):
      arm/dts: Fix am33xx wdt node

Arnaud Patard (3):
      ARM: Orion: Set eth packet size csum offload limit
      ARM: Kirkwood: Fix iconnect leds
      ARM: Kirkwood: fix Makefile.boot

Arnd Bergmann (4):
      ARM: mv78xx0: fix win_cfg_base prototype
      Merge tag 'omap-fixes-for-v3.6-rc1' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge branch 'fixes-for-v3.6' of git://git.infradead.org/users/jcooper/linux into fixes
      Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes

Domenico Andreoli (1):
      OMAP: remove unused parameter arch_id from uncompress.h

Igor Grinberg (1):
      Revert "ARM: OMAP3530evm: set pendown_state and debounce time for ads7846"

Jan Luebbe (1):
      omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX are selected

Javier Martinez Canillas (1):
      ARM: OMAP3: igep0020: set GPIO mode for mux mcspi1_cs2 pin

Jon Hunter (1):
      ARM: OMAP2+: Fix dmtimer set source clock failure

Kevin Hilman (2):
      ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled
      Revert "ARM: OMAP3: PM: call pre/post transition per powerdomain"

Michael Jones (1):
      omap2: mux: remove comment for nonexistent member

Rajendra Nayak (3):
      arm/dts: Mark vcxio, v2v1 and v1v8 regulators as always on
      cpufreq: OMAP: Handle missing frequency table on SMP systems
      ARM: OMAP4: Register the OPP table only for 4430 device

Santosh Shilimkar (2):
      OMAP2+: Fix random config build break with !ARM_CPU_SUSPEND
      ARM: OMAP4: sleep: Save the complete used register stack frame

Timo Kokkonen (1):
      ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*()

Tony Lindgren (2):
      Merge branch 'for_3.6/fixes/ads7846-2' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes
      Merge branch 'for_3.6/fixes/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes

Vaibhav Hiremath (1):
      ARM: OMAP2+: cpu: Add am33xx device under cpu_class_is_omap2

Yuanhan Liu (1):
      ARM: mmp: fix potential NULL dereference

 arch/arm/boot/dts/am33xx.dtsi                |    5 +++++
 arch/arm/boot/dts/kirkwood-iconnect.dts      |    6 +++++-
 arch/arm/boot/dts/twl6030.dtsi               |    3 +++
 arch/arm/mach-dove/common.c                  |    3 ++-
 arch/arm/mach-kirkwood/Makefile.boot         |    3 ++-
 arch/arm/mach-kirkwood/common.c              |    4 ++--
 arch/arm/mach-mmp/sram.c                     |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c             |    2 +-
 arch/arm/mach-mv78xx0/common.c               |    6 ++++--
 arch/arm/mach-omap2/Kconfig                  |    1 +
 arch/arm/mach-omap2/board-igep0020.c         |    2 ++
 arch/arm/mach-omap2/board-omap3evm.c         |    1 +
 arch/arm/mach-omap2/common-board-devices.c   |   11 -----------
 arch/arm/mach-omap2/common-board-devices.h   |    1 -
 arch/arm/mach-omap2/mux.h                    |    1 -
 arch/arm/mach-omap2/opp4xxx_data.c           |    2 +-
 arch/arm/mach-omap2/pm34xx.c                 |   19 ++++---------------
 arch/arm/mach-omap2/sleep44xx.S              |    8 ++++++--
 arch/arm/mach-omap2/twl-common.c             |    1 +
 arch/arm/mach-orion5x/common.c               |    3 ++-
 arch/arm/plat-omap/dmtimer.c                 |    6 +++---
 arch/arm/plat-omap/include/plat/cpu.h        |    3 ++-
 arch/arm/plat-omap/include/plat/multi.h      |    9 +++++++++
 arch/arm/plat-omap/include/plat/uncompress.h |    4 +---
 arch/arm/plat-orion/common.c                 |    8 ++++++--
 arch/arm/plat-orion/include/plat/common.h    |    6 ++++--
 drivers/cpufreq/omap-cpufreq.c               |    4 +++-
 include/linux/mv643xx_eth.h                  |    2 ++
 28 files changed, 73 insertions(+), 53 deletions(-)


From m.szyprowski at samsung.com  Mon Aug 20 03:13:16 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 09:13:16 +0200
Subject: [PATCH 1/2] ARM: da850/omap-l138: Add SoC related definitions for
 VPIF
In-Reply-To: <CA+V-a8vcFhkF-dEOtBpx=v8P5DC+4qjsG8xxCeDRxkYTQTSStg@mail.gmail.com>
References: <1343115786-15801-1-git-send-email-prabhakar.lad@ti.com>
 <1343115786-15801-2-git-send-email-prabhakar.lad@ti.com>
 <502A4464.3020706@ti.com> <502CC7CD.80906@ti.com> <502E5C40.803@ti.com>
 <024a01cd7c8a$541efb20$fc5cf160$%szyprowski@samsung.com>
 <CA+V-a8vcFhkF-dEOtBpx=v8P5DC+4qjsG8xxCeDRxkYTQTSStg@mail.gmail.com>
Message-ID: <02f201cd7ea3$479e2d10$d6da8730$%szyprowski@samsung.com>

Hi Prabhakar,

On Friday, August 17, 2012 5:50 PM Prabhakar Lad wrote:
 
> On Fri, Aug 17, 2012 at 8:39 PM, Marek Szyprowski
> <m.szyprowski at samsung.com> wrote:
> > Hello,
> >
> > On Friday, August 17, 2012 4:59 PM Sekhar Nori wrote:
> >
> >> On 8/16/2012 3:43 PM, Prabhakar Lad wrote:
> >> > On Tuesday 14 August 2012 05:58 PM, Sekhar Nori wrote:
> >>
> >> [...]
> >>
> >> >>> +int __init da850_register_vpif_display(struct vpif_display_config
> >> >>> +                                         *display_config)
> >> >>> +{
> >> >>> + struct resource da850_vpif_display_resource[] = {
> >> >>> +         {
> >> >>> +                 .start = IRQ_DA850_VPIFINT,
> >> >>> +                 .end   = IRQ_DA850_VPIFINT,
> >> >>> +                 .flags = IORESOURCE_IRQ,
> >> >>> +         },
> >> >>> +         {},
> >> >>> + };
> >> >>> + unsigned long phys_end_kernel;
> >> >>> + int ret;
> >> >>> +
> >> >>> + if (vpif_disp_cont_bufsize) {
> >> >>> +         phys_end_kernel = virt_to_phys((void *)PAGE_OFFSET) +
> >> >>> +                                 (num_physpages << PAGE_SHIFT);
> >> >>> +         phys_end_kernel += vpif_disp_cont_buf_offset;
> >> >>> +         da850_vpif_display_resource[1].start = phys_end_kernel;
> >> >>> +         da850_vpif_display_resource[1].end = phys_end_kernel +
> >> >>> +                                         vpif_disp_cont_bufsize - 1;
> >> >>> +         da850_vpif_display_resource[1].flags = IORESOURCE_MEM;
> >> >>> +
> >> >>> +         if (!request_mem_region(da850_vpif_display_resource[1].start,
> >> >>> +                         resource_size(&da850_vpif_display_resource[1]),
> >> >>> +                         da850_vpif_display_dev.name)) {
> >> >>> +                 pr_err("region already claimed.\n");
> >> >>> +                 return -EBUSY;
> >> >>> +         }
> >> >>> +         ret = dma_declare_coherent_memory(&da850_vpif_display_dev.dev,
> >> >>> +                         phys_end_kernel, phys_end_kernel,
> >> >>> +                         vpif_disp_cont_bufsize,
> >> >>> +                         DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> >> >>> +
> >> >>> +         if (!ret)
> >> >>> +                 return -ENOMEM;
> >> >>> + }
> >> >>> + ret = platform_device_add_resources(&da850_vpif_display_dev,
> >> >>> +                         da850_vpif_display_resource,
> >> >>> +                         ARRAY_SIZE(da850_vpif_display_resource));
> >> >>
> >> >> You are taking memory at the end of RAM and passing it as a IO resource
> >> >> to the driver. This is not correct. For contiguous memory needs can you
> >> >> look at the recently merged CMA framework (include/linux/dma-contiguous.h)
> >> >>
> >> > Ok. But looks like CMA is enabled for CPU_V6/V6K/V7. If CMA is enabled
> >> > for ARM926 too than we can use the global CMA itself rather then doing
> >> > it for each device, then three will be no need to do the above and all
> >> > the kernel parameters can be removed too.
> >>
> >> I hadn't followed the CMA development closely so I am not sure of the
> >> reasons behind restricting it to v6+. The patch that added this doesn't
> >> really talk about why it should be restricted to v6+. I am copying Marek
> >> here to see if he can quickly clarify, but may be you can even start a
> >> new thread asking about this.
> >
> > Frankly, this is a leftover from some earlier suggestions that CMA should solve the
> > aliasing of coherent mappings, which might be a problem on v6+. If it works correctly
> > on pre-v6, then this dependency should be removed. Feel free to submit a patch and
> > I will take it to my fixes branch.
> >
> 
> I have created a patch for enabling CMA on CPU32_v5 [1], and also
> tested it works.
> Soon posting this patch.
> 
> [1] http://git.linuxtv.org/mhadli/v4l-dvb-
> davinci_devices.git/commitdiff/e940a1b9262bde96eec4b18971a6307f24262667?hp=2f30ae4ee373fe4c69a
> b1606373538dcc99ed283

I've taken a look at this issue and realized that the dependency on enabled MMU is much
better idea instead of listing possible CPU versions, so I've posted a new patch:

http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002374.html

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From richard.genoud at gmail.com  Mon Aug 20 03:38:31 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 20 Aug 2012 09:38:31 +0200
Subject: [PATCH 6/8] UBI: replace MTD_UBI_BEB_LIMIT with module parameter
In-Reply-To: <20120819122634.252f1ea5@pixies.home.jungo.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-7-git-send-email-richard.genoud@gmail.com>
 <20120819122634.252f1ea5@pixies.home.jungo.com>
Message-ID: <CACQ1gAgUdXj9KKtgjf=Lx0Kz2v18Xgz4RjiRQnKHMsf3m3THJw@mail.gmail.com>

2012/8/19 Shmulik Ladkani <shmulik.ladkani at gmail.com>:
> Hi Richard,
>
> On Fri, 17 Aug 2012 16:35:22 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
>> +                   "MTD devices may be specified by their number, name, or path to the MTD character device node.\n"
>> +                   "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0 or not set)\n"
>> +                   "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value ("
>> +                   __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0 or not set)\n"
>
> Looks like "mtd=/dev/mtd1,,25" is invalid, although we state "default
> value if 0 or not set".
I'm going to check that.
>
> Also, lines are exceeding 80 chars, not sure this is more readable than
> if they were broken.
Actually, I didn't split those lines to make checkpatch happy.
Checkpatch.pl doesn't like split strings because they are hard to grep.
So there's an exception on the 80 column rule for strings.

>
> Regards,
> Shmulik



-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From u.kleine-koenig at pengutronix.de  Mon Aug 20 03:52:05 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Mon, 20 Aug 2012 09:52:05 +0200
Subject: [PATCH RFC] ARM: busy loop at the end of machine_power_off
Message-ID: <1345449125-23212-1-git-send-email-u.kleine-koenig@pengutronix.de>

When machine_power_off returns the kernel panics with

	Attempted to kill init!

. So let machine_power_off busy loop as machine_halt does, too.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
This is triggered when issuing

	poweroff

only if the machine sets the pm_power_off callback because the reboot
system call does

        if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
		cmd = LINUX_REBOOT_CMD_HALT;

So it might even be safe to call pm_power_off unconditionally in
machine_power_off.

Best regards
Uwe

 arch/arm/kernel/process.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 693b744..eda0846 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -256,6 +256,8 @@ void machine_power_off(void)
 	machine_shutdown();
 	if (pm_power_off)
 		pm_power_off();
+	local_irq_disable();
+	while (1);
 }
 
 void machine_restart(char *cmd)
-- 
1.7.10.4



From plagnioj at jcrosoft.com  Mon Aug 20 03:56:12 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 09:56:12 +0200
Subject: [PATCH 1/8] arm: sam9_l9260_defconfig: adjust UBI bad
 eraseblocks limit
In-Reply-To: <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-2-git-send-email-richard.genoud@gmail.com>
Message-ID: <20120820075612.GD7439@game.jcrosoft.org>

On 16:35 Fri 17 Aug     , Richard Genoud wrote:
> From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> 
> UBI has changed the MTD_UBI_BEB_LIMIT semantics. It used to be a percent of
> total amount of eraseblock in the partition, and now it is the maximum
> amount of bad eraseblocks on the entire devise per 1024 eraseblocks. So not
> only the units changed, but also the meaning. But anyway, old 3% roughly
> correspond to new 30, so change the defconfig correspondingly.
> 
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
simply drop this defconfig

Best Regards,
J.


From plagnioj at jcrosoft.com  Mon Aug 20 03:58:32 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 09:58:32 +0200
Subject: [PATCH 13/14] arm: at91: dt: at91sam9 add nand pinctrl support
In-Reply-To: <CACQ1gAgqXOJiiocOEMBZiaBchXDhvxqfA7RkiEvCCsv000LQNw@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-13-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZXjFE7UsRneskNqnN7DFERHxgAt-FCXtL2A52xKgEA=w@mail.gmail.com>
 <CACQ1gAhWdwrXEkicy4ij=rukzS-v98bZRr433Qq5M_Dan5JAog@mail.gmail.com>
 <20120816173844.GC7439@game.jcrosoft.org>
 <CACQ1gAgqXOJiiocOEMBZiaBchXDhvxqfA7RkiEvCCsv000LQNw@mail.gmail.com>
Message-ID: <20120820075832.GE7439@game.jcrosoft.org>

On 08:53 Fri 17 Aug     , Richard Genoud wrote:
> 2012/8/16 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> >> Maybe it will be more readable if we use something like :
> >> atmel,pull-up;
> >> atmel,multidrive;
> >> atmel,mux="GPIO"
> >> atmel,mux="A"
> >> ...
> >> just my 2 cents...
> > no too much data and too much node as you will need a node per pin which we
> > tyr to avoid
> 
> One one hand we've got a DTS quite concise but unreadable, and on the
> other hand, something understandable but huge.
> ( and it's not specific to your patch Jean-Christophe, on imx6q.dtsi,
> it looks worse )
> I'm just trying to make sure that having a DTS like that :
> nand {
> 	pinctrl_nand: nand-0 {
> 		atmel,pins =
> 			<2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
> 			2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
> 	};
> };
> is better than :
> nand {
> 	pinctrl_nand: nand-0 {
> 		nand_rdy { atmel,bank = "C"; atmel,pin = <13>; atmel,mux = "GPIO";
> atmel,pull-up; };
> 		nand_ena { atmel,bank = "C"; atmel,pin = <14>; atmel,mux = "GPIO";
> atmel,pull-up; };
> 	};
> };
> It's what you did in 1st place on linux-at91 git, and I kinda liked it.
> But yeah, it's more verbose, and some lines will go beyond 80 columns,
> but that's already the case.
but as I explain you the DT must not have 1000s of not which we will have if
we do this. that's why I drop it

and soon we will have macro in DT so this will be more readable

Best Regards,
J.


From plagnioj at jcrosoft.com  Mon Aug 20 04:02:10 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 10:02:10 +0200
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <CACRpkdZDMxk30YTkrumRveR3OuWptSpzNevrAvC2FxYShOZp-A@mail.gmail.com>
References: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
 <20120816124002.GB7439@game.jcrosoft.org>
 <CACRpkdZDMxk30YTkrumRveR3OuWptSpzNevrAvC2FxYShOZp-A@mail.gmail.com>
Message-ID: <20120820080210.GF7439@game.jcrosoft.org>

On 00:42 Sun 19 Aug     , Linus Walleij wrote:
> On Thu, Aug 16, 2012 at 2:40 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> > On 14:16 Thu 16 Aug     , Linus Walleij wrote:
> >> +/* For the Device Tree, add in the UART callbacks as AUXDATA */
> >> +static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
> >> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
> >> +             "rtc", NULL),
> >> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
> >> +             "uart0", &integrator_uart_data),
> >> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
> >> +             "uart1", &integrator_uart_data),
> >> +     OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
> >> +             "kmi0", NULL),
> >> +     OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
> >> +             "kmi1", NULL),
> >> +     { /* sentinel */ },
> 
> > why that?
> 
> Based on similar code by Grant in arch/arm/mach-versatile/core.c
> also ending with a {}. Also at other places ... I though this terminated
> the list iteration, is it not needed anymore?
no I mean why
> >> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
> >> +             "rtc", NULL),
> >> +     OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
> >> +             "kmi0", NULL),
> >> +     OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
> >> +             "kmi1", NULL),

no platform data why do you use the AUXDATA?

as the OF_DEV_AUXDATA is deprecated now

Bset Regards,
J.


From plagnioj at jcrosoft.com  Mon Aug 20 04:02:58 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 10:02:58 +0200
Subject: [PATCH 03/14] arm: at91: at91sam9x5: fix gpio number per bank
In-Reply-To: <201208182118.45349.arnd@arndb.de>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-3-git-send-email-plagnioj@jcrosoft.com>
 <201208182118.45349.arnd@arndb.de>
Message-ID: <20120820080258.GG7439@game.jcrosoft.org>

On 21:18 Sat 18 Aug     , Arnd Bergmann wrote:
> On Friday 10 August 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> > +++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> > @@ -9,6 +9,10 @@ Required properties:
> >    unused).
> >  - gpio-controller: Marks the device node as a GPIO controller.
> >  
> > +optional properties:
> > +- gpio-nb: Number of gpio if absent 32.
> > +
> > +
> >  Example:
> >         pioA: gpio at fffff200 {
> >                 compatible = "atmel,at91rm9200-gpio";
> > @@ -16,5 +20,6 @@ Example:
> >                 interrupts = <2 4>;
> >                 #gpio-cells = <2>;
> >                 gpio-controller;
> > +               gpio-nb = <19>;
> 
> What does "nb" stand for?
> 
> The marvell-gpio binding uses "ngpio" for the number, so that would
> already be established. Otherwise, I think "#gpio-lines" would be
> more in line with other things we count in the bindings.
ngpio I dont like
#gpio-lines ok

Best Regards,
J.


From lee.jones at linaro.org  Mon Aug 20 04:06:34 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 09:06:34 +0100
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
 <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>
Message-ID: <20120820080632.GD8450@gmail.com>

On Tue, Aug 14, 2012 at 01:13:49PM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > We've done this before and it worked well last time. Here we're
> > duplicating a complex registration function to ease the process
> > of enabling it for Device Tree. As there are quite a few steps
> > taken during the registration process, it makes sense to break
> > them up into more manageable chunks. This patch will aid us.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> I understand you have used this approach before so:
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Does this comment take back your previous one:

NOTE: it seems this patch set contains some churn. First you
add in the forked device init, put in a big chunk of code and
then in the *same* patch set delete it again. It's not like
we're dying to see all the development history... can this
be squashed down a bit?

... hence leave the patch-set as it is?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From javier.martin at vista-silicon.com  Mon Aug 20 04:08:39 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Mon, 20 Aug 2012 10:08:39 +0200
Subject: [PATCH] media: mx2_camera: Remove MX2_CAMERA_SWAP16 and
 MX2_CAMERA_PACK_DIR_MSB flags.
In-Reply-To: <Pine.LNX.4.64.1207301718510.28003@axis700.grange>
References: <1342083809-19921-1-git-send-email-javier.martin@vista-silicon.com>
 <Pine.LNX.4.64.1207201330240.27906@axis700.grange>
 <CACKLOr2sKVWCk3we_cP5MvnR6-WsaFwA9AC=fgp3iLm8B6mfEA@mail.gmail.com>
 <Pine.LNX.4.64.1207301718510.28003@axis700.grange>
Message-ID: <CACKLOr3OmRUACO8QaJnYA6E=YZMCrrOq1pAXb1wTv4Udg+u8bQ@mail.gmail.com>

Hi,

On 30 July 2012 17:33, Guennadi Liakhovetski <g.liakhovetski at gmx.de> wrote:
> Hi Javier
>
> On Mon, 30 Jul 2012, javier Martin wrote:
>
>> Hi,
>> thank you for yor ACKs.
>>
>> On 20 July 2012 13:31, Guennadi Liakhovetski <g.liakhovetski at gmx.de> wrote:
>> > On Thu, 12 Jul 2012, Javier Martin wrote:
>> >
>> >> These flags are not used any longer and can be safely removed
>> >> since the following patch:
>> >> http://www.spinics.net/lists/linux-media/msg50165.html
>> >>
>> >> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
>> >
>> > For the ARM tree:
>> >
>> > Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
>>
>> forgive my ignorance on the matter. Could you please point me to the
>> git repository this patch should be merged?
>
> Sorry, my "for the ARM tree" comment was probably not clear enough. This
> patch should certainly go via the ARM (SoC) tree, since it only touches
> arch/arm. So, the maintainer (Sascha - added to CC), that will be
> forwarding this patch to Linus can thereby add my "acked-by" to this
> patch, if he feels like it.
>

Sascha, do you have any comments on this one? I can't find it in
arm-soc, did you already merge it?

Regards.

-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From lee.jones at linaro.org  Mon Aug 20 04:09:46 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 09:09:46 +0100
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
 <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
Message-ID: <20120820080945.GE8450@gmail.com>

On Tue, Aug 14, 2012 at 10:51:02AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > In the initial submission of the MSP driver msp1 and msp3's associated
> > pinctrl mechanism was passed back to platform code using a plat_init()
> > call-back routine, but it has no place in platform code. The MSP driver
> > should set this up for the appropriate ports. Instead we use a use_pinctrl
> > identifier which is passed from platform_data/Device Tree which indicates
> > which ports should use pinctrl.
> >
> > CC: alsa-devel at alsa-project.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This is very good because it rids platform code and makes the driver
> self-contained without strange platform data hooks.
> 
> Now details...
> 
> > +/* MSP1/3 Tx/Rx usage protection */
> > +static DEFINE_SPINLOCK(msp_rxtx_lock);
> > +
> > +/* Pin modes */
> > +struct pinctrl *pinctrl_p;
> > +struct pinctrl_state *pinctrl_def;
> > +struct pinctrl_state *pinctrl_sleep;
> > +
> > +/* Reference Count */
> > +int pinctrl_rxtx_ref;
> 
> 
> But wait. These are just local statics. Surelty you can put these into
> struct ux500_msp instead? Here it looks like these will be used for
> all ports, so MSP2 will enable the pins requested by MSP1 etc
> completely broken. So put it into the struct ux500_msp state
> container from ux500_msp_i2s.h where it belongs.

This was intentional, as in the previous implementation only MSP1 and
MSP3 (which share pins) were enabled for pinctrl. I will move them into
struct ux500_msp instead though, no problem

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Mon Aug 20 04:12:31 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 10:12:31 +0200
Subject: [PATCH 00/11] pinctrl: mvebu: pinctrl driver
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdZn73M_5rciZhpTTidMpwfMSZqb+wZnY5FkgztK2YBFiQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
> SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
> The SoC specific stubs use the pinctrl-mvebu core driver that handles
> pinctrl API and register accesses for common pinctrl registers.

Nice! I'll now go in and review it.

Please add Stephen Warren <swarren at wwwdotorg.org> on CC for
subsequent iterations.

Yours,
Linus Walleij


From dedekind1 at gmail.com  Mon Aug 20 04:25:28 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 20 Aug 2012 11:25:28 +0300
Subject: [PATCH 5/8] UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
In-Reply-To: <CACQ1gAgLirwiwiUOoL7ig7R_RpB8xDr2-g2gVOEUZNvAHB60pQ@mail.gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>
 <20120819120804.15c33931@pixies.home.jungo.com>
 <CACQ1gAgLirwiwiUOoL7ig7R_RpB8xDr2-g2gVOEUZNvAHB60pQ@mail.gmail.com>
Message-ID: <1345451128.2848.14.camel@sauron.fi.intel.com>

On Mon, 2012-08-20 at 08:31 +0200, Richard Genoud wrote:
> That's right, I'll correct that in next version.
> Thanks !

I've amended this patch, added Shmulik's reviewed-by and pushed to
linux-ubi.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From Barry.Song at csr.com  Mon Aug 20 04:19:47 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 16:19:47 +0800
Subject: [PATCH 3/3] ARM: SIRF: make sirf irqchip driver selectable since new
 SoCs will have GIC
In-Reply-To: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345450787-17246-4-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

New MARCO and POLO SoC uses GIC, so make irq.c selectable and select
it for PRIMAII

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/mach-sirf/Kconfig  |    4 ++++
 arch/arm/mach-sirf/Makefile |    2 +-
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-sirf/Kconfig b/arch/arm/mach-sirf/Kconfig
index 811e782..fea4bd9 100644
--- a/arch/arm/mach-sirf/Kconfig
+++ b/arch/arm/mach-sirf/Kconfig
@@ -8,9 +8,13 @@ config ARCH_PRIMA2
 	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 	select CPU_V7
 	select ZONE_DMA
+	select SIRF_IRQ
 	help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
 endchoice
 
+config SIRF_IRQ
+	bool
+
 endif
diff --git a/arch/arm/mach-sirf/Makefile b/arch/arm/mach-sirf/Makefile
index 852af49..3103fdf 100644
--- a/arch/arm/mach-sirf/Makefile
+++ b/arch/arm/mach-sirf/Makefile
@@ -1,8 +1,8 @@
 obj-y := timer.o
-obj-y += irq.o
 obj-y += rstc.o
 obj-y += board-generic.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Mon Aug 20 04:19:45 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 16:19:45 +0800
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to generic
 board
In-Reply-To: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345450787-17246-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

we will have SiRFMarco and SiRFPolo, all of them will be in the
generic board.

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/mach-prima2/Makefile                      |    2 +-
 arch/arm/mach-prima2/{prima2.c => board-generic.c} |   10 ++++++----
 2 files changed, 7 insertions(+), 5 deletions(-)
 rename arch/arm/mach-prima2/{prima2.c => board-generic.c} (81%)

diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 841847d..852af49 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,7 +1,7 @@
 obj-y := timer.o
 obj-y += irq.o
 obj-y += rstc.o
-obj-y += prima2.o
+obj-y += board-generic.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/board-generic.c
similarity index 81%
rename from arch/arm/mach-prima2/prima2.c
rename to arch/arm/mach-prima2/board-generic.c
index e9a17ae..f06b887 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/board-generic.c
@@ -30,12 +30,13 @@ void __init sirfsoc_init_late(void)
 	sirfsoc_pm_init();
 }
 
-static const char *prima2cb_dt_match[] __initdata = {
-       "sirf,prima2-cb",
+#ifdef CONFIG_ARCH_PRIMA2
+static const char *prima2_dt_match[] __initdata = {
+       "sirf,prima2",
        NULL
 };
 
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.atag_offset	= 0x100,
 	.map_io         = sirfsoc_map_lluart,
@@ -44,6 +45,7 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
-	.dt_compat      = prima2cb_dt_match,
+	.dt_compat      = prima2_dt_match,
 	.restart	= sirfsoc_restart,
 MACHINE_END
+#endif
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Mon Aug 20 04:19:44 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 16:19:44 +0800
Subject: [PATCH 0/3] ARM: PRIMA2: some patches prepared to support new SiRF
 SoCs
Message-ID: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

we will support SiRFmarco and SiRFpolo SMP SoCs, this series is making
mach-prima2 common for all of them.

Barry Song (3):
  ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
  ARM: PRIMA2: make mach-prima2 common for all SiRF series SoC
  ARM: SIRF: make sirf irqchip driver selectable since new SoCs will
    have GIC

 arch/arm/Kconfig                                   |   10 +++++-----
 arch/arm/Makefile                                  |    2 +-
 arch/arm/mach-sirf/Kconfig                         |   20 ++++++++++++++++++++
 arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    4 ++--
 arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
 .../prima2.c => mach-sirf/board-generic.c}         |   10 ++++++----
 arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
 .../include/mach/clkdev.h                          |    0
 .../include/mach/debug-macro.S                     |    0
 .../include/mach/entry-macro.S                     |    0
 .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
 .../include/mach/hardware.h                        |    0
 .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
 .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0
 .../include/mach/timex.h                           |    0
 .../{mach-prima2 => mach-sirf}/include/mach/uart.h |    0
 .../include/mach/uncompress.h                      |    0
 arch/arm/{mach-prima2 => mach-sirf}/irq.c          |    0
 arch/arm/{mach-prima2 => mach-sirf}/l2x0.c         |    0
 arch/arm/{mach-prima2 => mach-sirf}/lluart.c       |    0
 arch/arm/{mach-prima2 => mach-sirf}/pm.c           |    0
 arch/arm/{mach-prima2 => mach-sirf}/pm.h           |    0
 arch/arm/{mach-prima2 => mach-sirf}/rstc.c         |    0
 arch/arm/{mach-prima2 => mach-sirf}/rtciobrg.c     |    0
 arch/arm/{mach-prima2 => mach-sirf}/sleep.S        |    0
 arch/arm/{mach-prima2 => mach-sirf}/timer.c        |    0
 26 files changed, 34 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/mach-sirf/Kconfig
 rename arch/arm/{mach-prima2 => mach-sirf}/Makefile (73%)
 rename arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot (100%)
 rename arch/arm/{mach-prima2/prima2.c => mach-sirf/board-generic.c} (81%)
 rename arch/arm/{mach-prima2 => mach-sirf}/common.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/clkdev.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/debug-macro.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/entry-macro.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/gpio.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/hardware.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/irqs.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/map.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/timex.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/uart.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/uncompress.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/irq.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/l2x0.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/lluart.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/pm.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/pm.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/rstc.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/rtciobrg.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/sleep.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/timer.c (100%)



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From richard.genoud at gmail.com  Mon Aug 20 04:21:17 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 20 Aug 2012 10:21:17 +0200
Subject: [PATCH 6/8] UBI: replace MTD_UBI_BEB_LIMIT with module parameter
In-Reply-To: <CACQ1gAgUdXj9KKtgjf=Lx0Kz2v18Xgz4RjiRQnKHMsf3m3THJw@mail.gmail.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-7-git-send-email-richard.genoud@gmail.com>
 <20120819122634.252f1ea5@pixies.home.jungo.com>
 <CACQ1gAgUdXj9KKtgjf=Lx0Kz2v18Xgz4RjiRQnKHMsf3m3THJw@mail.gmail.com>
Message-ID: <CACQ1gAjqL3DS8e+Ya2xAKOBVuRjjyLPYU7xa74vTOKhyypHL2Q@mail.gmail.com>

2012/8/20 Richard Genoud <richard.genoud at gmail.com>:
> 2012/8/19 Shmulik Ladkani <shmulik.ladkani at gmail.com>:
>> Hi Richard,
>>
>> On Fri, 17 Aug 2012 16:35:22 +0200 Richard Genoud <richard.genoud at gmail.com> wrote:
>>> +                   "MTD devices may be specified by their number, name, or path to the MTD character device node.\n"
>>> +                   "Optional \"vid_hdr_offs\" parameter specifies UBI VID header position to be used by UBI. (default value if 0 or not set)\n"
>>> +                   "Optional \"max_beb_per1024\" parameter specifies the maximum expected bad eraseblock per 1024 eraseblocks. (default value ("
>>> +                   __stringify(CONFIG_MTD_UBI_BEB_LIMIT) ") if 0 or not set)\n"
>>
>> Looks like "mtd=/dev/mtd1,,25" is invalid, although we state "default
>> value if 0 or not set".
> I'm going to check that.
I made a patch to accept empty string value.
I'll send it with the rest of the patch serie.

Regards,
Richard.


From Barry.Song at csr.com  Mon Aug 20 04:19:46 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 20 Aug 2012 16:19:46 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF series
 SoC
In-Reply-To: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345450787-17246-3-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

We will have SiRF Marco and Polo, so rename the dir to mach-sirf
and add Kconfig menu

Signed-off-by: Baohua Song <Baohua.Song at csr.com>
---
 arch/arm/Kconfig                                   |   10 +++++-----
 arch/arm/Makefile                                  |    2 +-
 arch/arm/mach-sirf/Kconfig                         |   16 ++++++++++++++++
 arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    0
 arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
 .../arm/{mach-prima2 => mach-sirf}/board-generic.c |    0
 arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
 .../include/mach/clkdev.h                          |    0
 .../include/mach/debug-macro.S                     |    0
 .../include/mach/entry-macro.S                     |    0
 .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
 .../include/mach/hardware.h                        |    0
 .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
 .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0
 .../include/mach/timex.h                           |    0
 .../{mach-prima2 => mach-sirf}/include/mach/uart.h |    0
 .../include/mach/uncompress.h                      |    0
 arch/arm/{mach-prima2 => mach-sirf}/irq.c          |    0
 arch/arm/{mach-prima2 => mach-sirf}/l2x0.c         |    0
 arch/arm/{mach-prima2 => mach-sirf}/lluart.c       |    0
 arch/arm/{mach-prima2 => mach-sirf}/pm.c           |    0
 arch/arm/{mach-prima2 => mach-sirf}/pm.h           |    0
 arch/arm/{mach-prima2 => mach-sirf}/rstc.c         |    0
 arch/arm/{mach-prima2 => mach-sirf}/rtciobrg.c     |    0
 arch/arm/{mach-prima2 => mach-sirf}/sleep.S        |    0
 arch/arm/{mach-prima2 => mach-sirf}/timer.c        |    0
 26 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-sirf/Kconfig
 rename arch/arm/{mach-prima2 => mach-sirf}/Makefile (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/board-generic.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/common.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/clkdev.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/debug-macro.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/entry-macro.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/gpio.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/hardware.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/irqs.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/map.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/timex.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/uart.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/include/mach/uncompress.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/irq.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/l2x0.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/lluart.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/pm.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/pm.h (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/rstc.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/rtciobrg.c (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/sleep.S (100%)
 rename arch/arm/{mach-prima2 => mach-sirf}/timer.c (100%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fb60148..21cc08a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -407,9 +407,8 @@ config ARCH_GEMINI
 	help
 	  Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_PRIMA2
-	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-	select CPU_V7
+config ARCH_SIRF
+	bool "CSR SiRF"
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
@@ -419,9 +418,8 @@ config ARCH_PRIMA2
 	select PINCTRL
 	select PINCTRL_SIRF
 	select USE_OF
-	select ZONE_DMA
 	help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
+	  Support for CSR SiRFprimaII/Marco/Polo platforms
 
 config ARCH_EBSA110
 	bool "EBSA-110"
@@ -1118,6 +1116,8 @@ source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
+source "arch/arm/mach-sirf/Kconfig"
+
 source "arch/arm/mach-tegra/Kconfig"
 
 source "arch/arm/mach-u300/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..cc8da8e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -168,7 +168,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
 machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
 machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
-machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
+machine-$(CONFIG_ARCH_SIRF)		:= sirf
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
 machine-$(CONFIG_ARCH_RPC)		:= rpc
diff --git a/arch/arm/mach-sirf/Kconfig b/arch/arm/mach-sirf/Kconfig
new file mode 100644
index 0000000..811e782
--- /dev/null
+++ b/arch/arm/mach-sirf/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_SIRF
+
+choice
+	prompt "Qualcomm SiRF SoC Type"
+	default ARCH_PRIMA2
+
+config ARCH_PRIMA2
+	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+	select CPU_V7
+	select ZONE_DMA
+	help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-sirf/Makefile
similarity index 100%
rename from arch/arm/mach-prima2/Makefile
rename to arch/arm/mach-sirf/Makefile
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-sirf/Makefile.boot
similarity index 100%
rename from arch/arm/mach-prima2/Makefile.boot
rename to arch/arm/mach-sirf/Makefile.boot
diff --git a/arch/arm/mach-prima2/board-generic.c b/arch/arm/mach-sirf/board-generic.c
similarity index 100%
rename from arch/arm/mach-prima2/board-generic.c
rename to arch/arm/mach-sirf/board-generic.c
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-sirf/common.h
similarity index 100%
rename from arch/arm/mach-prima2/common.h
rename to arch/arm/mach-sirf/common.h
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-sirf/include/mach/clkdev.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/clkdev.h
rename to arch/arm/mach-sirf/include/mach/clkdev.h
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-sirf/include/mach/debug-macro.S
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/debug-macro.S
rename to arch/arm/mach-sirf/include/mach/debug-macro.S
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-sirf/include/mach/entry-macro.S
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/entry-macro.S
rename to arch/arm/mach-sirf/include/mach/entry-macro.S
diff --git a/arch/arm/mach-prima2/include/mach/gpio.h b/arch/arm/mach-sirf/include/mach/gpio.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/gpio.h
rename to arch/arm/mach-sirf/include/mach/gpio.h
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-sirf/include/mach/hardware.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/hardware.h
rename to arch/arm/mach-sirf/include/mach/hardware.h
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-sirf/include/mach/irqs.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/irqs.h
rename to arch/arm/mach-sirf/include/mach/irqs.h
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-sirf/include/mach/map.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/map.h
rename to arch/arm/mach-sirf/include/mach/map.h
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-sirf/include/mach/timex.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/timex.h
rename to arch/arm/mach-sirf/include/mach/timex.h
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-sirf/include/mach/uart.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/uart.h
rename to arch/arm/mach-sirf/include/mach/uart.h
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-sirf/include/mach/uncompress.h
similarity index 100%
rename from arch/arm/mach-prima2/include/mach/uncompress.h
rename to arch/arm/mach-sirf/include/mach/uncompress.h
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-sirf/irq.c
similarity index 100%
rename from arch/arm/mach-prima2/irq.c
rename to arch/arm/mach-sirf/irq.c
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-sirf/l2x0.c
similarity index 100%
rename from arch/arm/mach-prima2/l2x0.c
rename to arch/arm/mach-sirf/l2x0.c
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-sirf/lluart.c
similarity index 100%
rename from arch/arm/mach-prima2/lluart.c
rename to arch/arm/mach-sirf/lluart.c
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-sirf/pm.c
similarity index 100%
rename from arch/arm/mach-prima2/pm.c
rename to arch/arm/mach-sirf/pm.c
diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-sirf/pm.h
similarity index 100%
rename from arch/arm/mach-prima2/pm.h
rename to arch/arm/mach-sirf/pm.h
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-sirf/rstc.c
similarity index 100%
rename from arch/arm/mach-prima2/rstc.c
rename to arch/arm/mach-sirf/rstc.c
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-sirf/rtciobrg.c
similarity index 100%
rename from arch/arm/mach-prima2/rtciobrg.c
rename to arch/arm/mach-sirf/rtciobrg.c
diff --git a/arch/arm/mach-prima2/sleep.S b/arch/arm/mach-sirf/sleep.S
similarity index 100%
rename from arch/arm/mach-prima2/sleep.S
rename to arch/arm/mach-sirf/sleep.S
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-sirf/timer.c
similarity index 100%
rename from arch/arm/mach-prima2/timer.c
rename to arch/arm/mach-sirf/timer.c
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
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From u.kleine-koenig at pengutronix.de  Mon Aug 20 04:24:23 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 20 Aug 2012 10:24:23 +0200
Subject: restart callback not supposed to sleep?
Message-ID: <20120820082423.GJ2232@pengutronix.de>

Hello,

while triggering a reboot via sysrq on an ARM machine I saw a "BUG:
sleeping function called from invalid context" message (details below).
The reason is that the sysrq handler is calling the restart hook in irq
context. So what should be done about that? The obvious possiblities
are:

 a) ignore the problem as it won't result in problems (and maybe somehow
    silence the warnign); or
 b) make the restart hook atomic; or
 c) assert sysrq not calling the hook in atomic mode

What do you think?

Best regards
Uwe

[  357.957733] SysRq : Resetting
[  357.960772] BUG: sleeping function called from invalid context at kernel/mutex.c:269
[  357.973053] in_atomic(): 1, irqs_disabled(): 0, pid: 0, name: swapper
[  357.979508] 2 locks held by swapper/0:
[  357.983268]  #0:  (&port_lock_key){-.-...}, at: [<801df9ec>] imx_rxint+0x24/0x2a4
[  357.990887]  #1:  (sysrq_key_table_lock){-.....}, at: [<801cda7c>] __handle_sysrq+0x1c/0x188
[  357.999442] Backtrace: 
[  358.001962] [<80010e9c>] (dump_backtrace+0x0/0x10c) from [<80365da0>] (dump_stack+0x18/0x1c)
[  358.010415]  r6:0000166c r5:804dbc00 r4:804ce000 r3:60000113
[  358.016200] [<80365d88>] (dump_stack+0x0/0x1c) from [<80040f70>] (__might_sleep+0xe0/0x11c)
[  358.024590] [<80040e90>] (__might_sleep+0x0/0x11c) from [<80369d8c>] (mutex_lock_nested+0x2c/0x2d0)
[  358.033649]  r6:804e90dc r5:80425b9c r4:804fb224
[  358.038372] [<80369d60>] (mutex_lock_nested+0x0/0x2d0) from [<8028ffdc>] (clk_get_sys+0x24/0x110)
[  358.047290] [<8028ffb8>] (clk_get_sys+0x0/0x110) from [<800188c8>] (mxc_restart+0x18/0xb8)
[  358.055588] [<800188b0>] (mxc_restart+0x0/0xb8) from [<8000ed70>] (machine_restart+0x24/0x60)
[  358.064126]  r5:804e4d70 r4:804dab3c
[  358.067863] [<8000ed4c>] (machine_restart+0x0/0x60) from [<8002d554>] (emergency_restart+0x1c/0x20)
[  358.076961]  r5:00000062 r4:804dab3c
[  358.080615] [<8002d538>] (emergency_restart+0x0/0x20) from [<801cd93c>] (sysrq_handle_reboot+0x1c/0x20)
[  358.090073] [<801cd920>] (sysrq_handle_reboot+0x0/0x20) from [<801cdb6c>] (__handle_sysrq+0x10c/0x188)
[  358.099441] [<801cda60>] (__handle_sysrq+0x0/0x188) from [<801cde00>] (handle_sysrq+0x30/0x38)
[  358.108115] [<801cddd0>] (handle_sysrq+0x0/0x38) from [<801dfba8>] (imx_rxint+0x1e0/0x2a4)
[  358.116440] [<801df9c8>] (imx_rxint+0x0/0x2a4) from [<801e0b0c>] (imx_int+0xa0/0xb8)
[  358.124224] [<801e0a6c>] (imx_int+0x0/0xb8) from [<80063f44>] (handle_irq_event_percpu+0x54/0x1bc)
[  358.133226]  r6:00000000 r5:87808e90 r4:870e9000 r3:801e0a6c
[  358.139026] [<80063ef0>] (handle_irq_event_percpu+0x0/0x1bc) from [<800640f0>] (handle_irq_event+0x44/0x64)
[  358.148834] [<800640ac>] (handle_irq_event+0x0/0x64) from [<80066414>] (handle_level_irq+0x94/0xf0)
[  358.157923]  r6:00000000 r5:87808e90 r4:87808e40 r3:00020000
[  358.163698] [<80066380>] (handle_level_irq+0x0/0xf0) from [<800637a8>] (generic_handle_irq+0x28/0x38)
[  358.172961]  r5:0000003d r4:0000003d
[  358.176635] [<80063780>] (generic_handle_irq+0x0/0x38) from [<8000e92c>] (handle_IRQ+0x38/0x8c)
[  358.185347]  r4:804e4da4 r3:000000b4
[  358.189023] [<8000e8f4>] (handle_IRQ+0x0/0x8c) from [<800084c4>] (avic_handle_irq+0x3c/0x5c)
[  358.197502]  r6:0000ffff r5:804cff18 r4:80502e58 r3:00000010
[  358.203272] [<80008488>] (avic_handle_irq+0x0/0x5c) from [<8000dd24>] (__irq_svc+0x44/0x58)
[  358.211670] Exception stack(0x804cff18 to 0x804cff60)
[  358.216769] ff00:                                                       00000001 00000001
[  358.224977] ff20: 00000000 804d8600 804ce000 80502a68 804d98d0 804ce000 80004008 4117b363
[  358.233211] ff40: 804c1cec 804cff6c 804cff30 804cff60 800530e0 8000eaac 20000013 ffffffff
[  358.241430]  r6:ffffffff r5:20000013 r4:8000eaac r3:804d8600
[  358.247229] [<8000ea84>] (default_idle+0x0/0x40) from [<8000ec88>] (cpu_idle+0x64/0xd0)
[  358.255281] [<8000ec24>] (cpu_idle+0x0/0xd0) from [<803605a8>] (rest_init+0xc4/0xec)
[  358.263069]  r7:00000002 r6:00000001 r5:804dc534 r4:804ce000
[  358.268876] [<803604e4>] (rest_init+0x0/0xec) from [<804a27d0>] (start_kernel+0x2ac/0x2fc)
[  358.277184]  r7:80b4e620 r6:804c31bc r5:805029c0 r4:804d6140
[  358.282954] [<804a2524>] (start_kernel+0x0/0x2fc) from [<80008040>] (0x80008040)
[  358.290400] BUG: scheduling while atomic: swapper/0/0x40010004
[  358.296277] 2 locks held by swapper/0:
[  358.300038]  #0:  (&port_lock_key){-.-...}, at: [<801df9ec>] imx_rxint+0x24/0x2a4
[  358.307669]  #1:  (sysrq_key_table_lock){-.....}, at: [<801cda7c>] __handle_sysrq+0x1c/0x188
[  358.316253] Modules linked in:
[  358.319337] Backtrace: 
[  358.321837] [<80010e9c>] (dump_backtrace+0x0/0x10c) from [<80365da0>] (dump_stack+0x18/0x1c)
[  358.330320]  r6:804d8600 r5:80425b9c r4:804d8600 r3:20000113
[  358.336121] [<80365d88>] (dump_stack+0x0/0x1c) from [<803664cc>] (__schedule_bug+0x64/0x78)
[  358.344505] [<80366468>] (__schedule_bug+0x0/0x78) from [<8036acf8>] (__schedule+0x3fc/0x464)
[  358.353072]  r4:804ce000 r3:00000000
[  358.356752] [<8036a8fc>] (__schedule+0x0/0x464) from [<8004153c>] (__cond_resched+0x28/0x38)
[  358.365225] [<80041514>] (__cond_resched+0x0/0x38) from [<8036adf4>] (_cond_resched+0x38/0x48)
[  358.373880]  r4:804fb224 r3:00010003
[  358.377553] [<8036adbc>] (_cond_resched+0x0/0x48) from [<80369d90>] (mutex_lock_nested+0x30/0x2d0)
[  358.386580] [<80369d60>] (mutex_lock_nested+0x0/0x2d0) from [<8028ffdc>] (clk_get_sys+0x24/0x110)
[  358.395492] [<8028ffb8>] (clk_get_sys+0x0/0x110) from [<800188c8>] (mxc_restart+0x18/0xb8)
[  358.403824] [<800188b0>] (mxc_restart+0x0/0xb8) from [<8000ed70>] (machine_restart+0x24/0x60)
[  358.412393]  r5:804e4d70 r4:804dab3c
[  358.416046] [<8000ed4c>] (machine_restart+0x0/0x60) from [<8002d554>] (emergency_restart+0x1c/0x20)
[  358.425135]  r5:00000062 r4:804dab3c
[  358.428810] [<8002d538>] (emergency_restart+0x0/0x20) from [<801cd93c>] (sysrq_handle_reboot+0x1c/0x20)
[  358.438265] [<801cd920>] (sysrq_handle_reboot+0x0/0x20) from [<801cdb6c>] (__handle_sysrq+0x10c/0x188)
[  358.447631] [<801cda60>] (__handle_sysrq+0x0/0x188) from [<801cde00>] (handle_sysrq+0x30/0x38)
[  358.456308] [<801cddd0>] (handle_sysrq+0x0/0x38) from [<801dfba8>] (imx_rxint+0x1e0/0x2a4)
[  358.464604] [<801df9c8>] (imx_rxint+0x0/0x2a4) from [<801e0b0c>] (imx_int+0xa0/0xb8)
[  358.472410] [<801e0a6c>] (imx_int+0x0/0xb8) from [<80063f44>] (handle_irq_event_percpu+0x54/0x1bc)
[  358.481411]  r6:00000000 r5:87808e90 r4:870e9000 r3:801e0a6c
[  358.487210] [<80063ef0>] (handle_irq_event_percpu+0x0/0x1bc) from [<800640f0>] (handle_irq_event+0x44/0x64)
[  358.497013] [<800640ac>] (handle_irq_event+0x0/0x64) from [<80066414>] (handle_level_irq+0x94/0xf0)
[  358.506072]  r6:00000000 r5:87808e90 r4:87808e40 r3:00020000
[  358.511877] [<80066380>] (handle_level_irq+0x0/0xf0) from [<800637a8>] (generic_handle_irq+0x28/0x38)
[  358.521139]  r5:0000003d r4:0000003d
[  358.524787] [<80063780>] (generic_handle_irq+0x0/0x38) from [<8000e92c>] (handle_IRQ+0x38/0x8c)
[  358.533529]  r4:804e4da4 r3:000000b4
[  358.537199] [<8000e8f4>] (handle_IRQ+0x0/0x8c) from [<800084c4>] (avic_handle_irq+0x3c/0x5c)
[  358.545650]  r6:0000ffff r5:804cff18 r4:80502e58 r3:00000010
[  358.551450] [<80008488>] (avic_handle_irq+0x0/0x5c) from [<8000dd24>] (__irq_svc+0x44/0x58)
[  358.559847] Exception stack(0x804cff18 to 0x804cff60)
[  358.564918] ff00:                                                       00000001 00000001
[  358.573156] ff20: 00000000 804d8600 804ce000 80502a68 804d98d0 804ce000 80004008 4117b363
[  358.581391] ff40: 804c1cec 804cff6c 804cff30 804cff60 800530e0 8000eaac 20000013 ffffffff
[  358.589609]  r6:ffffffff r5:20000013 r4:8000eaac r3:804d8600
[  358.595383] [<8000ea84>] (default_idle+0x0/0x40) from [<8000ec88>] (cpu_idle+0x64/0xd0)
[  358.603455] [<8000ec24>] (cpu_idle+0x0/0xd0) from [<803605a8>] (rest_init+0xc4/0xec)
[  358.611241]  r7:00000002 r6:00000001 r5:804dc534 r4:804ce000
[  358.617041] [<803604e4>] (rest_init+0x0/0xec) from [<804a27d0>] (start_kernel+0x2ac/0x2fc)
[  358.625319]  r7:80b4e620 r6:804c31bc r5:805029c0 r4:804d6140
[  358.631118] [<804a2524>] (start_kernel+0x0/0x2fc) from [<80008040>] (0x80008040)
[  358.686854] ------------[ cut here ]------------
[  358.691551] WARNING: at kernel/mutex.c:198 mutex_lock_nested+0x290/0x2d0()
[  358.703020] Modules linked in:
[  358.706145] Backtrace: 
[  358.708665] [<80010e9c>] (dump_backtrace+0x0/0x10c) from [<80365da0>] (dump_stack+0x18/0x1c)
[  358.717153]  r6:000000c6 r5:80369ff0 r4:00000000 r3:00000000
[  358.722925] [<80365d88>] (dump_stack+0x0/0x1c) from [<8001b4d0>] (warn_slowpath_common+0x54/0x6c)
[  358.731860] [<8001b47c>] (warn_slowpath_common+0x0/0x6c) from [<8001b50c>] (warn_slowpath_null+0x24/0x2c)
[  358.741469]  r8:00000000 r7:804d8600 r6:804ce000 r5:8050401c r4:804fb224 r3:00000009
[  358.749478] [<8001b4e8>] (warn_slowpath_null+0x0/0x2c) from [<80369ff0>] (mutex_lock_nested+0x290/0x2d0)
[  358.759032] [<80369d60>] (mutex_lock_nested+0x0/0x2d0) from [<8028ffdc>] (clk_get_sys+0x24/0x110)
[  358.767984] [<8028ffb8>] (clk_get_sys+0x0/0x110) from [<800188c8>] (mxc_restart+0x18/0xb8)
[  358.776318] [<800188b0>] (mxc_restart+0x0/0xb8) from [<8000ed70>] (machine_restart+0x24/0x60)
[  358.784858]  r5:804e4d70 r4:804dab3c
[  358.788547] [<8000ed4c>] (machine_restart+0x0/0x60) from [<8002d554>] (emergency_restart+0x1c/0x20)
[  358.797637]  r5:00000062 r4:804dab3c
[  358.801294] [<8002d538>] (emergency_restart+0x0/0x20) from [<801cd93c>] (sysrq_handle_reboot+0x1c/0x20)
[  358.810750] [<801cd920>] (sysrq_handle_reboot+0x0/0x20) from [<801cdb6c>] (__handle_sysrq+0x10c/0x188)
[  358.820115] [<801cda60>] (__handle_sysrq+0x0/0x188) from [<801cde00>] (handle_sysrq+0x30/0x38)
[  358.828795] [<801cddd0>] (handle_sysrq+0x0/0x38) from [<801dfba8>] (imx_rxint+0x1e0/0x2a4)
[  358.837123] [<801df9c8>] (imx_rxint+0x0/0x2a4) from [<801e0b0c>] (imx_int+0xa0/0xb8)
[  358.844909] [<801e0a6c>] (imx_int+0x0/0xb8) from [<80063f44>] (handle_irq_event_percpu+0x54/0x1bc)
[  358.853909]  r6:00000000 r5:87808e90 r4:870e9000 r3:801e0a6c
[  358.859708] [<80063ef0>] (handle_irq_event_percpu+0x0/0x1bc) from [<800640f0>] (handle_irq_event+0x44/0x64)
[  358.869513] [<800640ac>] (handle_irq_event+0x0/0x64) from [<80066414>] (handle_level_irq+0x94/0xf0)
[  358.878602]  r6:00000000 r5:87808e90 r4:87808e40 r3:00020000
[  358.884374] [<80066380>] (handle_level_irq+0x0/0xf0) from [<800637a8>] (generic_handle_irq+0x28/0x38)
[  358.893635]  r5:0000003d r4:0000003d
[  358.897307] [<80063780>] (generic_handle_irq+0x0/0x38) from [<8000e92c>] (handle_IRQ+0x38/0x8c)
[  358.906020]  r4:804e4da4 r3:000000b4
[  358.909693] [<8000e8f4>] (handle_IRQ+0x0/0x8c) from [<800084c4>] (avic_handle_irq+0x3c/0x5c)
[  358.918173]  r6:0000ffff r5:804cff18 r4:80502e58 r3:00000010
[  358.923941] [<80008488>] (avic_handle_irq+0x0/0x5c) from [<8000dd24>] (__irq_svc+0x44/0x58)
[  358.932339] Exception stack(0x804cff18 to 0x804cff60)
[  358.937439] ff00:                                                       00000001 00000001
[  358.945645] ff20: 00000000 804d8600 804ce000 80502a68 804d98d0 804ce000 80004008 4117b363
[  358.953878] ff40: 804c1cec 804cff6c 804cff30 804cff60 800530e0 8000eaac 20000013 ffffffff
[  358.962095]  r6:ffffffff r5:20000013 r4:8000eaac r3:804d8600
[  358.967894] [<8000ea84>] (default_idle+0x0/0x40) from [<8000ec88>] (cpu_idle+0x64/0xd0)
[  358.975943] [<8000ec24>] (cpu_idle+0x0/0xd0) from [<803605a8>] (rest_init+0xc4/0xec)
[  358.983728]  r7:00000002 r6:00000001 r5:804dc534 r4:804ce000
[  358.989531] [<803604e4>] (rest_init+0x0/0xec) from [<804a27d0>] (start_kernel+0x2ac/0x2fc)
[  358.997838]  r7:80b4e620 r6:804c31bc r5:805029c0 r4:804d6140
[  359.003606] [<804a2524>] (start_kernel+0x0/0x2fc) from [<80008040>] (0x80008040)
[  359.011047] ---[ end trace 1ad357144973f17c ]---
[  359.015715] BUG: sleeping function called from invalid context at kernel/mutex.c:269
[  359.028025] in_atomic(): 1, irqs_disabled(): 0, pid: 0, name: swapper
[  359.034479] INFO: lockdep is turned off.
[  359.038440] Backtrace: 
[  359.040946] [<80010e9c>] (dump_backtrace+0x0/0x10c) from [<80365da0>] (dump_stack+0x18/0x1c)
[  359.049430]  r6:000016d5 r5:804dbc00 r4:804ce000 r3:60000013
[  359.055216] [<80365d88>] (dump_stack+0x0/0x1c) from [<80040f70>] (__might_sleep+0xe0/0x11c)
[  359.063635] [<80040e90>] (__might_sleep+0x0/0x11c) from [<80369d8c>] (mutex_lock_nested+0x2c/0x2d0)
[  359.072726]  r6:804e90dc r5:8780db40 r4:804fb274
[  359.077470] [<80369d60>] (mutex_lock_nested+0x0/0x2d0) from [<80291478>] (clk_prepare+0x20/0x40)
[  359.086333] [<80291458>] (clk_prepare+0x0/0x40) from [<800188d8>] (mxc_restart+0x28/0xb8)
[  359.094526]  r5:804e4d70 r4:8780db40
[  359.098207] [<800188b0>] (mxc_restart+0x0/0xb8) from [<8000ed70>] (machine_restart+0x24/0x60)
[  359.106776]  r5:804e4d70 r4:804dab3c
[  359.110427] [<8000ed4c>] (machine_restart+0x0/0x60) from [<8002d554>] (emergency_restart+0x1c/0x20)
[  359.119517]  r5:00000062 r4:804dab3c
[  359.123166] [<8002d538>] (emergency_restart+0x0/0x20) from [<801cd93c>] (sysrq_handle_reboot+0x1c/0x20)
[  359.132621] [<801cd920>] (sysrq_handle_reboot+0x0/0x20) from [<801cdb6c>] (__handle_sysrq+0x10c/0x188)
[  359.141988] [<801cda60>] (__handle_sysrq+0x0/0x188) from [<801cde00>] (handle_sysrq+0x30/0x38)
[  359.150664] [<801cddd0>] (handle_sysrq+0x0/0x38) from [<801dfba8>] (imx_rxint+0x1e0/0x2a4)
[  359.158987] [<801df9c8>] (imx_rxint+0x0/0x2a4) from [<801e0b0c>] (imx_int+0xa0/0xb8)
[  359.166794] [<801e0a6c>] (imx_int+0x0/0xb8) from [<80063f44>] (handle_irq_event_percpu+0x54/0x1bc)
[  359.175767]  r6:00000000 r5:87808e90 r4:870e9000 r3:801e0a6c
[  359.181569] [<80063ef0>] (handle_irq_event_percpu+0x0/0x1bc) from [<800640f0>] (handle_irq_event+0x44/0x64)
[  359.191374] [<800640ac>] (handle_irq_event+0x0/0x64) from [<80066414>] (handle_level_irq+0x94/0xf0)
[  359.200461]  r6:00000000 r5:87808e90 r4:87808e40 r3:00020000
[  359.206260] [<80066380>] (handle_level_irq+0x0/0xf0) from [<800637a8>] (generic_handle_irq+0x28/0x38)
[  359.215494]  r5:0000003d r4:0000003d
[  359.219168] [<80063780>] (generic_handle_irq+0x0/0x38) from [<8000e92c>] (handle_IRQ+0x38/0x8c)
[  359.227911]  r4:804e4da4 r3:000000b4
[  359.231555] [<8000e8f4>] (handle_IRQ+0x0/0x8c) from [<800084c4>] (avic_handle_irq+0x3c/0x5c)
[  359.240035]  r6:0000ffff r5:804cff18 r4:80502e58 r3:00000010
[  359.245803] [<80008488>] (avic_handle_irq+0x0/0x5c) from [<8000dd24>] (__irq_svc+0x44/0x58)
[  359.254198] Exception stack(0x804cff18 to 0x804cff60)
[  359.259296] ff00:                                                       00000001 00000001
[  359.267530] ff20: 00000000 804d8600 804ce000 80502a68 804d98d0 804ce000 80004008 4117b363
[  359.275736] ff40: 804c1cec 804cff6c 804cff30 804cff60 800530e0 8000eaac 20000013 ffffffff
[  359.283951]  r6:ffffffff r5:20000013 r4:8000eaac r3:804d8600
[  359.289748] [<8000ea84>] (default_idle+0x0/0x40) from [<8000ec88>] (cpu_idle+0x64/0xd0)
[  359.297818] [<8000ec24>] (cpu_idle+0x0/0xd0) from [<803605a8>] (rest_init+0xc4/0xec)
[  359.305576]  r7:00000002 r6:00000001 r5:804dc534 r4:804ce000
[  359.311380] [<803604e4>] (rest_init+0x0/0xec) from [<804a27d0>] (start_kernel+0x2ac/0x2fc)
[  359.319688]  r7:80b4e620 r6:804c31bc r5:805029c0 r4:804d6140
[  359.325454] [<804a2524>] (start_kernel+0x0/0x2fc) from [<80008040>] (0x80008040)
[  359.332899] BUG: scheduling while atomic: swapper/0/0x40010004
[  359.338769] INFO: lockdep is turned off.
[  359.342703] Modules linked in:
[  359.345783] Backtrace: 
[  359.348312] [<80010e9c>] (dump_backtrace+0x0/0x10c) from [<80365da0>] (dump_stack+0x18/0x1c)
[  359.356797]  r6:804d8600 r5:8780db40 r4:804d8600 r3:60000013
[  359.362567] [<80365d88>] (dump_stack+0x0/0x1c) from [<803664cc>] (__schedule_bug+0x64/0x78)
[  359.370980] [<80366468>] (__schedule_bug+0x0/0x78) from [<8036acf8>] (__schedule+0x3fc/0x464)
[  359.379546]  r4:804ce000 r3:00000000
[  359.383201] [<8036a8fc>] (__schedule+0x0/0x464) from [<8004153c>] (__cond_resched+0x28/0x38)
[  359.391708] [<80041514>] (__cond_resched+0x0/0x38) from [<8036adf4>] (_cond_resched+0x38/0x48)
[  359.400365]  r4:804fb274 r3:00010003
[  359.404012] [<8036adbc>] (_cond_resched+0x0/0x48) from [<80369d90>] (mutex_lock_nested+0x30/0x2d0)
[  359.413041] [<80369d60>] (mutex_lock_nested+0x0/0x2d0) from [<80291478>] (clk_prepare+0x20/0x40)
[  359.421896] [<80291458>] (clk_prepare+0x0/0x40) from [<800188d8>] (mxc_restart+0x28/0xb8)
[  359.430116]  r5:804e4d70 r4:8780db40
[  359.433767] [<800188b0>] (mxc_restart+0x0/0xb8) from [<8000ed70>] (machine_restart+0x24/0x60)
[  359.442336]  r5:804e4d70 r4:804dab3c
[  359.445986] [<8000ed4c>] (machine_restart+0x0/0x60) from [<8002d554>] (emergency_restart+0x1c/0x20)
[  359.455074]  r5:00000062 r4:804dab3c
[  359.458748] [<8002d538>] (emergency_restart+0x0/0x20) from [<801cd93c>] (sysrq_handle_reboot+0x1c/0x20)
[  359.468202] [<801cd920>] (sysrq_handle_reboot+0x0/0x20) from [<801cdb6c>] (__handle_sysrq+0x10c/0x188)
[  359.477569] [<801cda60>] (__handle_sysrq+0x0/0x188) from [<801cde00>] (handle_sysrq+0x30/0x38)
[  359.486242] [<801cddd0>] (handle_sysrq+0x0/0x38) from [<801dfba8>] (imx_rxint+0x1e0/0x2a4)
[  359.494538] [<801df9c8>] (imx_rxint+0x0/0x2a4) from [<801e0b0c>] (imx_int+0xa0/0xb8)
[  359.502344] [<801e0a6c>] (imx_int+0x0/0xb8) from [<80063f44>] (handle_irq_event_percpu+0x54/0x1bc)
[  359.511344]  r6:00000000 r5:87808e90 r4:870e9000 r3:801e0a6c
[  359.517140] [<80063ef0>] (handle_irq_event_percpu+0x0/0x1bc) from [<800640f0>] (handle_irq_event+0x44/0x64)
[  359.526943] [<800640ac>] (handle_irq_event+0x0/0x64) from [<80066414>] (handle_level_irq+0x94/0xf0)
[  359.536002]  r6:00000000 r5:87808e90 r4:87808e40 r3:00020000
[  359.541803] [<80066380>] (handle_level_irq+0x0/0xf0) from [<800637a8>] (generic_handle_irq+0x28/0x38)
[  359.551064]  r5:0000003d r4:0000003d
[  359.554713] [<80063780>] (generic_handle_irq+0x0/0x38) from [<8000e92c>] (handle_IRQ+0x38/0x8c)
[  359.563453]  r4:804e4da4 r3:000000b4
[  359.567121] [<8000e8f4>] (handle_IRQ+0x0/0x8c) from [<800084c4>] (avic_handle_irq+0x3c/0x5c)
[  359.575572]  r6:0000ffff r5:804cff18 r4:80502e58 r3:00000010
[  359.581372] [<80008488>] (avic_handle_irq+0x0/0x5c) from [<8000dd24>] (__irq_svc+0x44/0x58)
[  359.589768] Exception stack(0x804cff18 to 0x804cff60)
[  359.594839] ff00:                                                       00000001 00000001
[  359.603073] ff20: 00000000 804d8600 804ce000 80502a68 804d98d0 804ce000 80004008 4117b363
[  359.611307] ff40: 804c1cec 804cff6c 804cff30 804cff60 800530e0 8000eaac 20000013 ffffffff
[  359.619524]  r6:ffffffff r5:20000013 r4:8000eaac r3:804d8600
[  359.625296] [<8000ea84>] (default_idle+0x0/0x40) from [<8000ec88>] (cpu_idle+0x64/0xd0)
[  359.633366] [<8000ec24>] (cpu_idle+0x0/0xd0) from [<803605a8>] (rest_init+0xc4/0xec)
[  359.641152]  r7:00000002 r6:00000001 r5:804dc534 r4:804ce000
[  359.646950] [<803604e4>] (rest_init+0x0/0xec) from [<804a27d0>] (start_kernel+0x2ac/0x2fc)
[  359.655227]  r7:80b4e620 r6:804c31bc r5:805029c0 r4:804d6140
[  359.661024] [<804a2524>] (start_kernel+0x0/0x2fc) from [<80008040>] (0x80008040)


-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From dedekind1 at gmail.com  Mon Aug 20 04:29:48 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 20 Aug 2012 11:29:48 +0300
Subject: [PATCH 5/8] UBI: check max_beb_per1024 value in ubi_attach_mtd_dev
In-Reply-To: <1345451128.2848.14.camel@sauron.fi.intel.com>
References: <1345214124-5478-1-git-send-email-richard.genoud@gmail.com>
 <1345214124-5478-6-git-send-email-richard.genoud@gmail.com>
 <20120819120804.15c33931@pixies.home.jungo.com>
 <CACQ1gAgLirwiwiUOoL7ig7R_RpB8xDr2-g2gVOEUZNvAHB60pQ@mail.gmail.com>
 <1345451128.2848.14.camel@sauron.fi.intel.com>
Message-ID: <1345451388.2848.16.camel@sauron.fi.intel.com>

On Mon, 2012-08-20 at 11:25 +0300, Artem Bityutskiy wrote:
> On Mon, 2012-08-20 at 08:31 +0200, Richard Genoud wrote:
> > That's right, I'll correct that in next version.
> > Thanks !
> 
> I've amended this patch, added Shmulik's reviewed-by and pushed to
> linux-ubi.git, thanks!

Sorry, actually I've dropped it - it does not compile :-) Please, send
bisectable patch-sets. Anyway, I expect you to re-send patches 5-8.

P.S. I am not sure we need to CC arm mailing list and lkml - I think we
spam them unnecessarily and the MTD list is enough.

-- 
Best Regards,
Artem Bityutskiy
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From herbert at gondor.apana.org.au  Mon Aug 20 04:32:47 2012
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Mon, 20 Aug 2012 16:32:47 +0800
Subject: [PATCH 11/11] pm/drivers: fix use of SIMPLE_DEV_PM_OPS
In-Reply-To: <201208081726.21878.arnd@arndb.de>
References: <1344437248-20560-1-git-send-email-arnd@arndb.de>
 <201208081622.29777.arnd@arndb.de> <s5hwr19fi6h.wl%tiwai@suse.de>
 <201208081726.21878.arnd@arndb.de>
Message-ID: <20120820083247.GF22951@gondor.apana.org.au>

On Wed, Aug 08, 2012 at 05:26:21PM +0000, Arnd Bergmann wrote:
> 
> Ok. this leaves the omap-rng driver, and my patch comes down to the below.
> Thanks!

Patch applied.  Thanks Arnd.
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From lee.jones at linaro.org  Mon Aug 20 04:36:43 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 09:36:43 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
Message-ID: <20120820083640.GH8450@gmail.com>

On Tue, Aug 14, 2012 at 12:44:37PM +0200, Linus Walleij wrote:
> On Tue, Aug 14, 2012 at 11:42 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Tuesday 14 August 2012, Linus Walleij wrote:
> >> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> >>
> >> > +int db8500_irq_get_virq(int irq);
> >>
> >> And I'm sceptic about this business. Why isn't this physical-to virtual
> >> mapping business confined to the core MFD driver? But enlighten me.
> >
> > Traditionally, an MFD would add an offset to the local IRQ number
> > to put the VIRQ into the IRQ resource, but this doesn't work when
> > you have domains other than legacy.
> 
> Yes but I think I saw this other patch set from Lee, hitting
> irqdomain, OF and MFD to actually fix this ... or did I get
> it wrong?

No, you're not wrong.

Historically (in my patches) xb8500_irq_get_virq() was used by drivers
to obtain a VIRQ when not using Device Tree. Now the MFD core handles
conversion there is little requirement for it. In fact there are no
more users for db8500_irq_get_virq() and only one user for 
ab8500_irq_get_virq() and that's itself. I guess we can rid them and
call irq_get_mapping() directly instead.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From alanbutty12 at gmail.com  Mon Aug 20 04:41:20 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 09:41:20 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
Message-ID: <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>

On 20 August 2012 03:31, Fabio Estevam <festevam at gmail.com> wrote:
> On Sun, Aug 19, 2012 at 3:03 PM, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> i just thaught i should let fabio and jason know that i just tried
>> kernel 3.6-rc2 and the buttons work i tried to apply the patch that
>> fabio sent me before but it didnt apply so i tried the kernel anyway
>> and the buttons do work.
>
> The patch I sent applies against linux-next.
>
> If you try linux-next you will probably get the kernel crash.

Oh yeah i did send you the eroor before i did try the patch on linux
next dated the 17th and the kernel did not crash but i got an error so
i will re-send you the error i got again incase you have lost it or
anything.

> orion_gpio_is_valid: invalid GPIO 0
> orion_gpio_is_valid: invalid GPIO 0
> gpio-keys gpio-keys.2: \x013INFO: %s in %pS age=%lu cpu=%u pid=%d
> Failed to request GPIO 0, error -22
> gpio-keys: probe of gpio-keys.2 failed with error -22

Thats what i got on that linux-next. but the 3.6-rc2 works fine. the
gpio settings are the exact same in the rc2 that i tried in the linux
next so it might be something in the way the dts file is read in the
new code?

should the gpio-keys be named button at 1 and so on as i see that in the
other kirkwood dts files where i have mine named power, otb, reset?


From burman.yan at gmail.com  Sun Aug 19 15:58:16 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Sun, 19 Aug 2012 22:58:16 +0300
Subject: [PATCH v2] ARM: ep93xx: Use HW MAC filter in ethernet driver
Message-ID: <1345406296.20237.4.camel@localhost>

ARM: ep93xx: Use HW MAC filter in ethernet driver
Use HW MAC filtering for broadcasts and multicasts.
Do not always work in promiscuous mode.
Partially based on kernel 2.6.20.4 driver from cirrus logic.
Tested on 9302 and 9315 based boards.

Changes from v1:
* Some minor style fixes
* Use CRC32 code instead of duplicating code
* Fixed multicast reception (tested with omping)

Signed-off-by: Yan Burman <burman.yan at gmail.com>

diff --git a/drivers/net/ethernet/cirrus/Kconfig b/drivers/net/ethernet/cirrus/Kconfig
index 8388e36..b7b154f 100644
--- a/drivers/net/ethernet/cirrus/Kconfig
+++ b/drivers/net/ethernet/cirrus/Kconfig
@@ -46,6 +46,7 @@ config EP93XX_ETH
 	depends on ARM && ARCH_EP93XX
 	select NET_CORE
 	select MII
+	select CRC32
 	help
 	  This is a driver for the ethernet hardware included in EP93xx CPUs.
 	  Say Y if you are building a kernel for EP93xx based devices.
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..27299ce 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/crc32.h>
 
 #include <mach/hardware.h>
 
@@ -37,8 +38,32 @@
 #define MAX_PKT_SIZE		2044
 #define PKT_BUF_SIZE		2048
 
+#define HASH_TBL_ENTRIES	8
+
 #define REG_RXCTL		0x0000
-#define  REG_RXCTL_DEFAULT	0x00073800
+#define  REG_RXCTL_PauseA  (1 << 20)
+#define  REG_RXCTL_RxFCE1  (1 << 19)
+#define  REG_RXCTL_RxFCE0  (1 << 18)
+#define  REG_RXCTL_BCRC    (1 << 17)
+#define  REG_RXCTL_SRxON   (1 << 16)
+#define  REG_RXCTL_RCRCA   (1 << 13)
+#define  REG_RXCTL_RA      (1 << 12)
+#define  REG_RXCTL_PA      (1 << 11)
+#define  REG_RXCTL_BA      (1 << 10)
+#define  REG_RXCTL_MA      (1 << 9)
+#define  REG_RXCTL_IAHA    (1 << 8)
+#define  REG_RXCTL_IA3     (1 << 3)
+#define  REG_RXCTL_IA2     (1 << 2)
+#define  REG_RXCTL_IA1     (1 << 1)
+#define  REG_RXCTL_IA0     (1 << 0)
+#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
+				REG_RXCTL_RA | \
+				REG_RXCTL_RCRCA | \
+				REG_RXCTL_SRxON | \
+				REG_RXCTL_BCRC | \
+				REG_RXCTL_RxFCE0 | \
+				REG_RXCTL_IA0)
+
 #define REG_TXCTL		0x0004
 #define  REG_TXCTL_ENABLE	0x00000001
 #define REG_MIICMD		0x0010
@@ -57,6 +82,12 @@
 #define  REG_INTSTS_RX		0x00000004
 #define REG_INTSTSC		0x002c
 #define REG_AFP			0x004c
+#define  REG_AFP_IA0		0
+#define  REG_AFP_IA1		1
+#define  REG_AFP_IA2		2
+#define  REG_AFP_IA3		3
+#define  REG_AFP_DTxP		6
+#define  REG_AFP_HASH		7
 #define REG_INDAD0		0x0050
 #define REG_INDAD1		0x0051
 #define REG_INDAD2		0x0052
@@ -386,6 +417,51 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 }
 
+static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *buf)
+{
+	struct netdev_hw_addr *ha;
+	u32 crc;
+
+	netdev_for_each_mc_addr(ha, dev) {
+		crc = ether_crc_le(ETH_ALEN, ha->addr);
+		buf[crc >> 29] |= (1 << ((crc >> 26) & 7));
+	}
+}
+
+static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *buf)
+{
+	u32 rxctl;
+	unsigned int i, len;
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	switch (afp) {
+	case REG_AFP_IA0:
+	case REG_AFP_IA1:
+	case REG_AFP_IA2:
+	case REG_AFP_IA3:
+	case REG_AFP_DTxP:
+		len = ETH_ALEN;
+		break;
+
+	case REG_AFP_HASH:
+		len = HASH_TBL_ENTRIES;
+		break;
+
+	default:
+		pr_crit("invalid afp value: %d\n", afp);
+		return -1;
+	}
+
+	rxctl = rdl(ep, REG_RXCTL);
+	wrl(ep, REG_RXCTL, ~REG_RXCTL_SRxON & rxctl);
+	wrl(ep, REG_AFP, afp);
+	for (i = 0; i < len; i++)
+		wrb(ep, REG_INDAD0 + i, buf[i]);
+	wrl(ep, REG_RXCTL, rxctl);
+
+	return 0;
+}
+
 static void ep93xx_tx_complete(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -615,13 +691,7 @@ static int ep93xx_start_hw(struct net_device *dev)
 	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
 	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
 
-	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
-	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
-	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
-	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
-	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
-	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
-	wrl(ep, REG_AFP, 0);
+	ep93xx_ind_addr_write(dev, REG_AFP_IA0, dev->dev_addr);
 
 	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
 
@@ -647,6 +717,32 @@ static void ep93xx_stop_hw(struct net_device *dev)
 		pr_crit("hw failed to reset\n");
 }
 
+static void ep93xx_set_multicast_list(struct net_device *dev)
+{
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	if (dev->flags & IFF_PROMISC) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
+	} else if (dev->flags & IFF_ALLMULTI) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
+		ep93xx_ind_addr_write(dev, REG_AFP_HASH,
+			      "\xff\xff\xff\xff\xff\xff\xff\xff");
+	} else if (!netdev_mc_empty(dev)) {
+		u8 tblMulti[HASH_TBL_ENTRIES + 1];
+
+		memset(tblMulti, 0, sizeof(tblMulti));
+
+		ep93xx_set_mcast_tbl(dev, tblMulti);
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
+		ep93xx_ind_addr_write(dev, REG_AFP_HASH, tblMulti);
+	} else {
+		wrl(ep, REG_RXCTL,
+			~(REG_RXCTL_PA | REG_RXCTL_MA) & rdl(ep, REG_RXCTL));
+	}
+}
+
 static int ep93xx_open(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -754,6 +850,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_change_mtu		= eth_change_mtu,
 	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
 };
 
 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)




From burman.yan at gmail.com  Sun Aug 19 16:00:44 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Sun, 19 Aug 2012 23:00:44 +0300
Subject: [PATCH v2] ARM: ep93xx: clockevent support
Message-ID: <1345406444.20237.7.camel@localhost>

ARM: ep93xx: clockevent support
I have ported to 3.6-rc2 and slightly modified a previous patch for clockevent support for the ep93xx.
The porting mainly consists of sched_clock support + CLKSRC_MMIO usage.
Tested on 9302 based board.

Changes from v1:
* Number of cosmetic style fixes
* Use CLKSRC_MMIO

From: Ahmed Ammar <aammar <at> edge-techno.com>
Signed-off-by: Yan Burman <burman.yan at gmail.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..b1d0b11 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -451,7 +451,8 @@ config ARCH_EP93XX
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_USES_GETTIMEOFFSET
+	select GENERIC_CLOCKEVENTS
+	select CLKSRC_MMIO
 	select NEED_MACH_MEMORY_H
 	help
 	  This enables support for the Cirrus EP93xx series of CPUs.
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4afe52a..f59a849 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -30,6 +30,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/mtd/physmap.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -43,6 +45,7 @@
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 
 #include <asm/hardware/vic.h>
 
@@ -114,63 +117,114 @@ void __init ep93xx_map_io(void)
 #define EP93XX_TIMER4_CLOCK		983040
 
 #define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
-#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
-
-static unsigned int last_jiffy_time;
 
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
+	struct clock_event_device *evt = dev_id;
+
 	/* Writing any value clears the timer interrupt */
 	__raw_writel(1, EP93XX_TIMER1_CLEAR);
-
-	/* Recover lost jiffies */
-	while ((signed long)
-		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
-						>= TIMER4_TICKS_PER_JIFFY) {
-		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
-		timer_tick();
-	}
+	evt->event_handler(evt);
 
 	return IRQ_HANDLED;
 }
 
+static int ep93xx_set_next_event(unsigned long evt,
+				struct clock_event_device *unused)
+{
+	u32 tmode = __raw_readl(EP93XX_TIMER1_CONTROL);
+
+	/* stop timer */
+	__raw_writel(tmode & ~EP93XX_TIMER123_CONTROL_ENABLE,
+			EP93XX_TIMER1_CONTROL);
+	/* program timer */
+	__raw_writel(evt, EP93XX_TIMER1_LOAD);
+	/* start timer */
+	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+			EP93XX_TIMER1_CONTROL);
+
+	return 0;
+}
+
+static void ep93xx_set_mode(enum clock_event_mode mode,
+			    struct clock_event_device *evt)
+{
+	u32 tmode = EP93XX_TIMER123_CONTROL_CLKSEL;
+
+	/* Disable timer */
+	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		/* Set timer period  */
+		__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
+		tmode |= EP93XX_TIMER123_CONTROL_MODE;
+		/* fall through */
+
+	case CLOCK_EVT_MODE_ONESHOT:
+		tmode |= EP93XX_TIMER123_CONTROL_ENABLE;
+		__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+		break;
+
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+}
+
+static struct clock_event_device ep93xx_clockevent = {
+	.name		= "ep93xx-timer1",
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.shift		= 32,
+	.set_mode	= ep93xx_set_mode,
+	.set_next_event	= ep93xx_set_next_event,
+};
+
 static struct irqaction ep93xx_timer_irq = {
 	.name		= "ep93xx timer",
 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= ep93xx_timer_interrupt,
+	.dev_id		= &ep93xx_clockevent,
 };
 
-static void __init ep93xx_timer_init(void)
+static void __init ep93xx_clockevent_init(void)
 {
-	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
-		    EP93XX_TIMER123_CONTROL_CLKSEL;
+	struct clock_event_device *evt = &ep93xx_clockevent;
 
-	/* Enable periodic HZ timer.  */
-	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
-	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
-	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
-			EP93XX_TIMER1_CONTROL);
-
-	/* Enable lost jiffy timer.  */
-	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
-			EP93XX_TIMER4_VALUE_HIGH);
+	evt->mult = div_sc(EP93XX_TIMER123_CLOCK, NSEC_PER_SEC, evt->shift);
+	evt->max_delta_ns = clockevent_delta2ns(0xfffffffe, evt);
+	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
+	evt->cpumask = cpumask_of(0);
 
 	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
+
+	clockevents_register_device(evt);
 }
 
-static unsigned long ep93xx_gettimeoffset(void)
+static void __init ep93xx_clocksource_init(void)
 {
-	int offset;
+	/* Reset time-stamp counter */
+	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, EP93XX_TIMER4_VALUE_HIGH);
+
+	clocksource_mmio_init(EP93XX_TIMER4_VALUE_LOW, "ep93xx-timer4",
+		CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
+}
 
-	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
+static u32 notrace ep93xx_sched_clock(void)
+{
+	return __raw_readl(EP93XX_TIMER4_VALUE_LOW);
+}
 
-	/* Calculate (1000000 / 983040) * offset.  */
-	return offset + (53 * offset / 3072);
+static void __init ep93xx_timer_init(void)
+{
+	ep93xx_clocksource_init();
+	ep93xx_clockevent_init();
+	setup_sched_clock(ep93xx_sched_clock, 32, CLOCK_TICK_RATE);
 }
 
 struct sys_timer ep93xx_timer = {
 	.init		= ep93xx_timer_init,
-	.offset		= ep93xx_gettimeoffset,
 };
 
 




From linux at arm.linux.org.uk  Mon Aug 20 04:57:20 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 Aug 2012 09:57:20 +0100
Subject: restart callback not supposed to sleep?
In-Reply-To: <20120820082423.GJ2232@pengutronix.de>
References: <20120820082423.GJ2232@pengutronix.de>
Message-ID: <20120820085720.GQ18957@n2100.arm.linux.org.uk>

On Mon, Aug 20, 2012 at 10:24:23AM +0200, Uwe Kleine-K?nig wrote:
> while triggering a reboot via sysrq on an ARM machine I saw a "BUG:
> sleeping function called from invalid context" message (details below).
> The reason is that the sysrq handler is calling the restart hook in irq
> context.

Correct - it's been the case for years that the restart hook is called
from atomic contexts (it's not only sysrq, but also softdog as well which
does this, as well as any system panic with panic timeout/panic-on-oops
enabled.)

You need to fix your platform restart hook.


From LW at KARO-electronics.de  Mon Aug 20 04:57:34 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Mon, 20 Aug 2012 10:57:34 +0200
Subject: restart callback not supposed to sleep?
In-Reply-To: <20120820082423.GJ2232@pengutronix.de>
References: <20120820082423.GJ2232@pengutronix.de>
Message-ID: <20529.64510.403690.325993@ipc1.ka-ro>

Hi,

Uwe Kleine-K?nig writes:
> Hello,
> 
> while triggering a reboot via sysrq on an ARM machine I saw a "BUG:
> sleeping function called from invalid context" message (details below).
> The reason is that the sysrq handler is calling the restart hook in irq
> context. So what should be done about that? The obvious possiblities
> are:
> 
>  a) ignore the problem as it won't result in problems (and maybe somehow
>     silence the warnign); or
>  b) make the restart hook atomic; or
>  c) assert sysrq not calling the hook in atomic mode
> 
> What do you think?
> 
This has been discussed earlier (with your participation) with 'a)'
being the conclusion.
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-December/033877.html


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From will.deacon at arm.com  Mon Aug 20 05:01:38 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 10:01:38 +0100
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <502E5073.6000901@ti.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
 <502E5073.6000901@ti.com>
Message-ID: <20120820090138.GA25864@mudshark.cambridge.arm.com>

On Fri, Aug 17, 2012 at 03:08:51PM +0100, Jon Hunter wrote:
> Hi Will, Tony,

Hi Jon [adding Arnd],

> On 08/10/2012 12:36 PM, Will Deacon wrote:
> > diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
> > index c00c689..02b9478 100644
> > --- a/arch/arm/mach-omap2/devices.c
> > +++ b/arch/arm/mach-omap2/devices.c
> > @@ -23,7 +23,6 @@
> >  #include <mach/irqs.h>
> >  #include <asm/mach-types.h>
> >  #include <asm/mach/map.h>
> > -#include <asm/pmu.h>
> >  
> >  #include "iomap.h"
> >  #include <plat/board.h>
> > @@ -448,7 +447,7 @@ static struct resource omap3_pmu_resource = {
> >  
> >  static struct platform_device omap_pmu_device = {
> >  	.name		= "arm-pmu",
> > -	.id		= ARM_PMU_DEVICE_CPU,
> > +	.id		= -1,
> >  	.num_resources	= 1,
> >  };
> 
> I know that I have already ack-ed the change and it is fine with me,
> however, I see a potential merge conflict here with my patch [1]
> (assuming that these all go into v3.7) where I am moving the above
> structure.

Are your patches queued anywhere other than your tree? If not, then I could
ask Arnd to pull the perf changes into their own branch in arm-soc and you
could rebase onto that.

> For testing I have rebased my series on top of this series and it is
> working well so far on OMAP4460.

Great, thanks. Can I add your tested-by to the patches please?

Will


From linux at arm.linux.org.uk  Mon Aug 20 05:05:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 Aug 2012 10:05:46 +0100
Subject: restart callback not supposed to sleep?
In-Reply-To: <20529.64510.403690.325993@ipc1.ka-ro>
References: <20120820082423.GJ2232@pengutronix.de>
 <20529.64510.403690.325993@ipc1.ka-ro>
Message-ID: <20120820090546.GR18957@n2100.arm.linux.org.uk>

On Mon, Aug 20, 2012 at 10:57:34AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> Uwe Kleine-K?nig writes:
> > Hello,
> > 
> > while triggering a reboot via sysrq on an ARM machine I saw a "BUG:
> > sleeping function called from invalid context" message (details below).
> > The reason is that the sysrq handler is calling the restart hook in irq
> > context. So what should be done about that? The obvious possiblities
> > are:
> > 
> >  a) ignore the problem as it won't result in problems (and maybe somehow
> >     silence the warnign); or
> >  b) make the restart hook atomic; or
> >  c) assert sysrq not calling the hook in atomic mode
> > 
> > What do you think?
> > 
> This has been discussed earlier (with your participation) with 'a)'
> being the conclusion.
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-December/033877.html

Except if you look at the backtrace, it seems that it fails to restart.
There are two attempts there at making it restart so the first could
not have succeeded.


From will.deacon at arm.com  Mon Aug 20 05:07:54 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 10:07:54 +0100
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <201208170706.07821.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120816104748.GI31784@mudshark.cambridge.arm.com>
 <201208161249.35008.arnd@arndb.de>
 <201208170706.07821.arnd@arndb.de>
Message-ID: <20120820090754.GB25864@mudshark.cambridge.arm.com>

On Fri, Aug 17, 2012 at 08:06:07AM +0100, Arnd Bergmann wrote:
> Sorry for the dumb question, but why do you even need PTRACE_GET_THREAD_AREA
> for 64 bit tasks? I thought the thread pointer is a GPR, or is this just
> for compat tasks?

The TLS is stored in a co-processor register which is read-only for
userspace. However, it's banked, so accessing the TLS of your child (the guy
you're ptracing) requires a system call.

Will


From linus.walleij at linaro.org  Mon Aug 20 05:09:51 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 11:09:51 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Thanks for dealing with this, much appreaciated!

Are you taking this patch series through some Marvell tree or do you want
me to carry it in the pinctrl tree?

(...)
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
> @@ -0,0 +1,46 @@
> +* Marvell SoC pinctrl core driver for mpp
> +
> +The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
> +(mpp) to a specific function. For each SoC family there is a SoC specific
> +driver using this core driver.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +A Marvell SoC pin configuration node is a node of a group of pins which can
> +be used for a specific device or function. Each node requires one or more
> +mpp pins or group of pins and a mpp function common to all pins.
> +
> +Required properties for pinctrl driver:
> +- compatible: "marvell,<soc>-pinctrl"
> +  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
> +
> +Required properties for pin configuration node:
> +- marvell,pins: string array of mpp pins or group of pins to be muxed.
> +- marvell,function: string representing to function to mux to for all
> +    marvell,pins given in this pin configuration node. The function has to be
> +    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
> +    valid pin/pin group names and available function names for each SoC.
> +
> +Examples:
> +
> +uart1: serial at 12100 {
> +       compatible = "ns16550a";
> +       reg = <0x12100 0x100>;
> +       reg-shift = <2>;
> +       interrupts = <7>;
> +       clock-frequency = <166666667>;

It's got nothing to do with this patch, but getting a clock frequency
out of the DT instead of getting it from the clk_get_rate(clk) and
the clock tree seems absurd... (But maybe this platform does not
even have a clk implementation?)

> +
> +       pinctrl-0 = <&pmx_uart1_sw>;
> +};
> +
> +pinctrl: pinctrl at d0200 {
> +       compatible = "marvell,dove-pinctrl";
> +       reg = <0xd0200 0x20>;
> +
> +       pmx_uart1_sw: pmx-uart1-sw {
> +               marvell,pins = "mpp_uart1";
> +               marvell,function = "uart1";
> +       };
> +};

This looks very good.

(...)
> +#include <linux/pinctrl/consumer.h>

Why are you including this header?
(There are valid reasons, state them in a comment,
e.g. /* to access pinctrl_gpio* in GPIO portions */)

> +struct mvebu_pinctrl_function {
> +       unsigned fid;
> +       const char *name;
> +       const char *setting;
> +       const char **groups;
> +       unsigned num_groups;
> +};
> +
> +struct mvebu_pinctrl_group {
> +       const char *name;
> +       struct mvebu_mpp_ctrl *ctrl;
> +       struct mvebu_mpp_ctrl_setting *settings;
> +       unsigned num_settings;
> +       unsigned gid;
> +       unsigned *pins;
> +       unsigned npins;
> +};
> +
> +struct mvebu_pinctrl {
> +       struct device *dev;
> +       struct pinctrl_dev *pctldev;
> +       struct pinctrl_desc desc;
> +       void __iomem *base;
> +       struct mvebu_pinctrl_group *groups;
> +       unsigned num_groups;
> +       struct mvebu_pinctrl_function *functions;
> +       unsigned num_functions;
> +       unsigned variant;
> +};

There is some other "variant" field elsewhere that is
a u8, is this correct? In this and the other case, should
this "variant" rather be an enum?

> +struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
> +       struct mvebu_pinctrl *pctl, unsigned pid)
> +{
> +       unsigned n;
> +       for (n = 0; n < pctl->num_groups; n++) {
> +               if (pid >= pctl->groups[n].pins[0] &&
> +                   pid < pctl->groups[n].pins[0] +
> +                       pctl->groups[n].npins)
> +                       return &pctl->groups[n];
> +       }
> +       return NULL;
> +}
> +
> +struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
> +       struct mvebu_pinctrl *pctl, const char *name)
> +{
> +       unsigned n;
> +       for (n = 0; n < pctl->num_groups; n++) {
> +               if (strcmp(name, pctl->groups[n].name) == 0)
> +                       return &pctl->groups[n];
> +       }
> +       return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
> +       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
> +       unsigned long config)
> +{
> +       unsigned n;
> +       for (n = 0; n < grp->num_settings; n++) {
> +               if (config == grp->settings[n].val) {
> +                       if (!pctl->variant || (pctl->variant &
> +                                              grp->settings[n].variant))
> +                               return &grp->settings[n];
> +               }
> +       }
> +       return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
> +       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
> +       const char *name)
> +{
> +       unsigned n;
> +       for (n = 0; n < grp->num_settings; n++) {
> +               if (strcmp(name, grp->settings[n].name) == 0) {
> +                       if (!pctl->variant || (pctl->variant &
> +                                              grp->settings[n].variant))
> +                               return &grp->settings[n];
> +               }
> +       }
> +       return NULL;
> +}
> +
> +struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
> +       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
> +{
> +       unsigned n;
> +       for (n = 0; n < grp->num_settings; n++) {
> +               if (grp->settings[n].flags &
> +                       (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
> +                       if (!pctl->variant || (pctl->variant &
> +                                               grp->settings[n].variant))
> +                               return &grp->settings[n];
> +               }
> +       }
> +       return NULL;
> +}
> +
> +struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
> +       struct mvebu_pinctrl *pctl, const char *name)
> +{
> +       unsigned n;
> +       for (n = 0; n < pctl->num_functions; n++) {
> +               if (strcmp(name, pctl->functions[n].name) == 0)
> +                       return &pctl->functions[n];
> +       }
> +       return NULL;
> +}
> +
> +static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
> +                               struct mvebu_pinctrl_group *grp,
> +                               unsigned long *config)
> +{
> +       unsigned pin = grp->gid;
> +       unsigned off = (pin / 8) * 4;
> +       unsigned shift = (pin % 8) * 4;

Some magic numbers here. Either use relevant #define:s or
put an inline comment that explains what is going on.

> +
> +       *config = readl(pctl->base + off);
> +       *config >>= shift;
> +       *config &= 0xf;

Here too...

> +
> +       return 0;
> +}
> +
> +static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
> +                               struct mvebu_pinctrl_group *grp,
> +                               unsigned long config)
> +{
> +       unsigned pin = grp->gid;
> +       unsigned off = (pin / 8) * 4;
> +       unsigned shift = (pin % 8) * 4;
> +       unsigned long reg;
> +
> +       reg = readl(pctl->base + off);
> +       reg &= ~(0xf << shift);
> +       reg |= (config << shift);
> +       writel(reg, pctl->base + off);
> +
> +       return 0;
> +}

Same comment as previous function.

(...)
> +static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
> +                               struct pinctrl_map *map, unsigned num_maps)
> +{
> +       kfree(map);
> +}

Is it possible to use devm_* managed devm_kzalloc() for this map
so you don't need to free it explicitly?

(Maybe not, just checking.)

The rest of this file is looking so good that I find nothing to comment on.

(...)
> diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
(...)
> +/*

Kerneldoc begins with /** have you really tested to generate
kerneldoc?

> + * struct mvebu_mpp_ctrl - describe a mpp control
> + * @name: name of the control group
> + * @pid: first pin id handled by this control
> + * @npins: number of pins controlled by this control
> + * @mpp_get: (optional) special function to get mpp setting
> + * @mpp_set: (optional) special function to set mpp setting
> + * @mpp_gpio_req: (optional) special function to request gpio
> + * @mpp_gpio_dir: (optional) special function to set gpio direction
> + *
> + * if optional mpp_get/_set functions are set these
> + * are used to get/set a specific mode. Otherwise it is
> + * assumed that the mpp control is based on 4-bit groups
> + * in subsequent registers.
> + *
> + * mpp_gpio_req/_dir functions can be used to allow pin settings
> + * with varying gpio pins.
> + */
> +struct mvebu_mpp_ctrl {
> +       const char *name;
> +       u8 pid;
> +       u8 npins;

So, there will never be > 256 pins on a Marvell platform?

Just checking...

> +       unsigned *pins;
> +       int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
> +       int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
> +       int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
> +       int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
> +};
> +
> +/*

/**

> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
> + * @val: ctrl setting value

It is not obvious to me what this means, it it possible to elaborate
on how this member is defined and used?

> + * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
> + * @subname: (optional) additional ctrl setting name, e.g. rts, cts
> + * @variant: (optional) variant identifier mask

This thing again, there are lots of "variants" around here.
Is it a candidate for an enum?

> + * @flags: (private) flags to store gpi/gpo/gpio capabilities

Write something about the two available flags and what they
mean maybe?

> + *
> + * ctrl setting name will be used to switch to this setting in
> + * DT description, e.g. marvell,function = "uart2". subname
> + * is only for debugging purposes.
> + * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
> + * parsed during initialization.
> + */
> +struct mvebu_mpp_ctrl_setting {
> +       u8 val;
> +       const char *name;
> +       const char *subname;
> +       u8 variant;

enum?

> +       u8 flags;
> +#define  MVEBU_SETTING_GPO     (1 << 0)
> +#define  MVEBU_SETTING_GPI     (1 << 1)

So these are the possible flags I suspect. (Looking good.)

> +};
> +
> +/*
> + * struct mvebu_mpp_mode - link ctrl and settings
> + * @pid: first pin id handled by this mode
> + * @settings: list of settings available for this mode
> + */
> +struct mvebu_mpp_mode {
> +       u8 pid;
> +       struct mvebu_mpp_ctrl_setting *settings;
> +};
> +
> +/*
> + * struct mvebu_pinctrl_soc_info -
> + *       SoC specific info passed to pinctrl-mvebu
> + * @variant: variant mask of soc_info
> + * @controls: list of available mvebu_mpp_ctrls
> + * @ncontrols: number of available mvebu_mpp_ctrls
> + * @modes: list of available mvebu_mpp_modes
> + * @nmodes: number of available mvebu_mpp_modes
> + * @gpioranges: list of pinctrl_gpio_ranges
> + * @ngpioranges: number of available pinctrl_gpio_ranges
> + */
> +struct mvebu_pinctrl_soc_info {
> +       u8 variant;

Why is this an u8 rather than an enum?

> +       struct mvebu_mpp_ctrl *controls;
> +       int ncontrols;
> +       struct mvebu_mpp_mode *modes;
> +       int nmodes;
> +       struct pinctrl_gpio_range *gpioranges;
> +       int ngpioranges;
> +};

(...)
> +#if defined(CONFIG_DEBUG_FS)
> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
> +       _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
> +#else
> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
> +       _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
> +#endif

This looks a bit kludgy. Is the purpose to save memory
if debugfs is not used?

This looks good overall.

Yours,
Linus Walleij


From u.kleine-koenig at pengutronix.de  Mon Aug 20 05:21:45 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 20 Aug 2012 11:21:45 +0200
Subject: restart callback not supposed to sleep?
In-Reply-To: <20120820090546.GR18957@n2100.arm.linux.org.uk>
References: <20120820082423.GJ2232@pengutronix.de>
 <20529.64510.403690.325993@ipc1.ka-ro>
 <20120820090546.GR18957@n2100.arm.linux.org.uk>
Message-ID: <20120820092145.GM2232@pengutronix.de>

On Mon, Aug 20, 2012 at 10:05:46AM +0100, Russell King - ARM Linux wrote:
> On Mon, Aug 20, 2012 at 10:57:34AM +0200, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Uwe Kleine-K?nig writes:
> > > Hello,
> > > 
> > > while triggering a reboot via sysrq on an ARM machine I saw a "BUG:
> > > sleeping function called from invalid context" message (details below).
> > > The reason is that the sysrq handler is calling the restart hook in irq
> > > context. So what should be done about that? The obvious possiblities
> > > are:
> > > 
> > >  a) ignore the problem as it won't result in problems (and maybe somehow
> > >     silence the warnign); or
> > >  b) make the restart hook atomic; or
> > >  c) assert sysrq not calling the hook in atomic mode
> > > 
> > > What do you think?
> > > 
> > This has been discussed earlier (with your participation) with 'a)'
> > being the conclusion.
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-December/033877.html
> 
> Except if you look at the backtrace, it seems that it fails to restart.
> There are two attempts there at making it restart so the first could
> not have succeeded.
Just for the log: The restart works ok.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From will.deacon at arm.com  Mon Aug 20 05:27:44 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 10:27:44 +0100
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <20120820090754.GB25864@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120816104748.GI31784@mudshark.cambridge.arm.com>
 <201208161249.35008.arnd@arndb.de>
 <201208170706.07821.arnd@arndb.de>
 <20120820090754.GB25864@mudshark.cambridge.arm.com>
Message-ID: <20120820092744.GD25864@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 10:07:54AM +0100, Will Deacon wrote:
> On Fri, Aug 17, 2012 at 08:06:07AM +0100, Arnd Bergmann wrote:
> > Sorry for the dumb question, but why do you even need PTRACE_GET_THREAD_AREA
> > for 64 bit tasks? I thought the thread pointer is a GPR, or is this just
> > for compat tasks?
> 
> The TLS is stored in a co-processor register which is read-only for
> userspace.

I should elaborate: the register is RW for AArch64 tasks, RO for aarch32
tasks (although that doesn't affect the need for the ptrace request).

Will


From lee.jones at linaro.org  Mon Aug 20 05:36:40 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 10:36:40 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
Message-ID: <20120820093638.GK8450@gmail.com>

On Tue, Aug 14, 2012 at 10:29:14AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > +static struct irq_domain *db8500_irq_domain;
> 
> So this is a good idea.

Did you mean this, or did you mean that it's _not_ a good idea?

If the latter is true, where would you prefer to see it?

> > +int db8500_irq_get_virq(int irq);
> 
> And I'm sceptic about this business. Why isn't this physical-to virtual
> mapping business confined to the core MFD driver? But enlighten me.
> 
> Yours,
> Linus Walleij

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linux at arm.linux.org.uk  Mon Aug 20 05:44:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 20 Aug 2012 10:44:55 +0100
Subject: restart callback not supposed to sleep?
In-Reply-To: <20120820092145.GM2232@pengutronix.de>
References: <20120820082423.GJ2232@pengutronix.de>
 <20529.64510.403690.325993@ipc1.ka-ro>
 <20120820090546.GR18957@n2100.arm.linux.org.uk>
 <20120820092145.GM2232@pengutronix.de>
Message-ID: <20120820094455.GS18957@n2100.arm.linux.org.uk>

On Mon, Aug 20, 2012 at 11:21:45AM +0200, Uwe Kleine-K?nig wrote:
> Just for the log: The restart works ok.

Restart with a command or restart with sysrq ?


From sebastian.hesselbarth at gmail.com  Mon Aug 20 05:46:14 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 Aug 2012 11:46:14 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
Message-ID: <CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>

On 8/20/12, Linus Walleij <linus.walleij at linaro.org> wrote:
> Are you taking this patch series through some Marvell tree or do you want
> me to carry it in the pinctrl tree?

Hi Linus,

I think it would be better to take it through the Marvell tree of Jason
Cooper. It is only for Marvell SoCs anyway.

>> +uart1: serial at 12100 {
>> +       compatible = "ns16550a";
>> +       reg = <0x12100 0x100>;
>> +       reg-shift = <2>;
>> +       interrupts = <7>;
>> +       clock-frequency = <166666667>;
>
> It's got nothing to do with this patch, but getting a clock frequency
> out of the DT instead of getting it from the clk_get_rate(clk) and
> the clock tree seems absurd... (But maybe this platform does not
> even have a clk implementation?)

It's of_serial's implementation. I patched that once for getting
frequency out of "clocks" property but then I got busy with
porting mach-dove and pinctrl.. Marvell SoCs do have a clk
implementation and as soon as of_serial can handle "clocks"
property it will be used for sure. I can remove "clock-frequency"
from the example anyway as it is not really part of pinctrl
binding documentation.

> (...)
>> +#include <linux/pinctrl/consumer.h>
>
> Why are you including this header?
> (There are valid reasons, state them in a comment,
> e.g. /* to access pinctrl_gpio* in GPIO portions */)

I guess it was a left-over from my experiments with
default pinmux configuration until you pointed me to
the correct way of having the pinctrl itself hog muxes.

I'll remove that include.

>> +struct mvebu_pinctrl {
>> +       struct device *dev;
>> +       struct pinctrl_dev *pctldev;
>> +       struct pinctrl_desc desc;
>> +       void __iomem *base;
>> +       struct mvebu_pinctrl_group *groups;
>> +       unsigned num_groups;
>> +       struct mvebu_pinctrl_function *functions;
>> +       unsigned num_functions;
>> +       unsigned variant;
>> +};
>
> There is some other "variant" field elsewhere that is
> a u8, is this correct? In this and the other case, should
> this "variant" rather be an enum?

I'll review the variant types but inside pinctrl-mvebu variant
is used as a bit mask to distinguish different variants. Anyway,
they should always be the same size.

>> +static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
>> +                               struct mvebu_pinctrl_group *grp,
>> +                               unsigned long *config)
>> +{
>> +       unsigned pin = grp->gid;
>> +       unsigned off = (pin / 8) * 4;
>> +       unsigned shift = (pin % 8) * 4;
>
> Some magic numbers here. Either use relevant #define:s or
> put an inline comment that explains what is going on.

Ok.

>> +static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
>> +                               struct pinctrl_map *map, unsigned
>> num_maps)
>> +{
>> +       kfree(map);
>> +}
>
> Is it possible to use devm_* managed devm_kzalloc() for this map
> so you don't need to free it explicitly?
>
> (Maybe not, just checking.)

Hmm, I guess not as I thought I've read not to use devm_kfree when
you allocate _and_ free stuff on runtime without removing the device
itself, right?

>> diff --git a/drivers/pinctrl/pinctrl-mvebu.h
>> b/drivers/pinctrl/pinctrl-mvebu.h
> (...)
>> +/*
>
> Kerneldoc begins with /** have you really tested to generate
> kerneldoc?

Nope, I wasn't even aware of that, sorry. I just copied it over
from some other pinctrl include. I'll check for compatibility with
kerneldoc.

>> +struct mvebu_mpp_ctrl {
>> +       const char *name;
>> +       u8 pid;
>> +       u8 npins;
>
> So, there will never be > 256 pins on a Marvell platform?

Well, with all current platforms we are well below 100. I guess
256 max (muxable) pins will be enough.

>> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
>> + * @val: ctrl setting value
>
> It is not obvious to me what this means, it it possible to elaborate
> on how this member is defined and used?

Well, I see if I can clarify the description but wrt the datasheet it
_should_ be quite obvious.

>> + * @variant: (optional) variant identifier mask
>
> This thing again, there are lots of "variants" around here.
> Is it a candidate for an enum?

As it is a mask, I don't think enum fits here.

>> + * @flags: (private) flags to store gpi/gpo/gpio capabilities
>
> Write something about the two available flags and what they
> mean maybe?

Ok.

>> +#define  MVEBU_SETTING_GPO     (1 << 0)
>> +#define  MVEBU_SETTING_GPI     (1 << 1)
>
> So these are the possible flags I suspect. (Looking good.)

Yes, some mpp pins on Marvell SoCs are out-only, while
normally they are in-out. I haven't seen in-only yet but better
to have the flags ready if someone stumbles upon one.

>> +#if defined(CONFIG_DEBUG_FS)
>> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
>> +       _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
>> +#else
>> +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
>> +       _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
>> +#endif
>
> This looks a bit kludgy. Is the purpose to save memory
> if debugfs is not used?

Yes, that was the intention. Subnames are not used by pinctrl at all,
other for debugfs files. Although, there are some pins that have two different
settings for the same device name, e.g. sata(prsnt) and sata(act), I don't
think it is a good idea to use the subname but have sata(prsnt) and sata-1(act)
instead. Otherwise, you'll always have to look up the specific function for
each pin. OTOH, I could check for "sata" and take the subname into account
when it is given in marvell,function. But it will not help reducing the required
pinmux descriptions in DT because you still have to distinguish both and
there are only 2 out of ~50 groups that have them for Dove.

> This looks good overall.

Thanks!
In some internal review with Andrew I also added a spinlock to
mvebu_pinconf_get/_set that will protect all calls to generic and specific
_get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
with the devm_ counterpart and removed the explicit clk_put.

Sebastian


From u.kleine-koenig at pengutronix.de  Mon Aug 20 05:47:57 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 20 Aug 2012 11:47:57 +0200
Subject: restart callback not supposed to sleep?
In-Reply-To: <20120820094455.GS18957@n2100.arm.linux.org.uk>
References: <20120820082423.GJ2232@pengutronix.de>
 <20529.64510.403690.325993@ipc1.ka-ro>
 <20120820090546.GR18957@n2100.arm.linux.org.uk>
 <20120820092145.GM2232@pengutronix.de>
 <20120820094455.GS18957@n2100.arm.linux.org.uk>
Message-ID: <20120820094757.GP2232@pengutronix.de>

Hello,

On Mon, Aug 20, 2012 at 10:44:55AM +0100, Russell King - ARM Linux wrote:
> On Mon, Aug 20, 2012 at 11:21:45AM +0200, Uwe Kleine-K?nig wrote:
> > Just for the log: The restart works ok.
> 
> Restart with a command or restart with sysrq ?
using sysrq. I get all these messages, but in the end the machine
restarts.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From keguang.zhang at gmail.com  Mon Aug 20 06:05:35 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Mon, 20 Aug 2012 18:05:35 +0800
Subject: [PATCH v3] clk: add Loongson1B clock support
Message-ID: <1345457135-12737-1-git-send-email-keguang.zhang@gmail.com>

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
---
 drivers/clk/Makefile   |    1 +
 drivers/clk/clk-ls1x.c |  111 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 0000000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <loongson1.h>
+
+#define OSC	33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 pll, rate;
+
+	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+	rate = ((12 + (pll & 0x3f)) * 1000000) +
+		((((pll >> 8) & 0x3ff) * 1000000) >> 10);
+	rate *= OSC;
+	rate >>= 1;
+
+	return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+	.enable = ls1x_pll_clk_enable,
+	.disable = ls1x_pll_clk_disable,
+	.recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+	 const char *name, const char *parent_name, unsigned long flags)
+{
+	struct clk_hw *hw;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the divider */
+	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+	if (!hw) {
+		pr_err("%s: could not allocate clk_hw\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ls1x_pll_clk_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+	hw->init = &init;
+
+	/* register the clock */
+	clk = clk_register(dev, hw);
+
+	if (IS_ERR(clk))
+		kfree(hw);
+
+	return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+	struct clk *clk;
+
+	clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+	clk_prepare_enable(clk);
+
+	clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+			DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "cpu", NULL);
+
+	clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+			DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "dc", NULL);
+
+	clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+			DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "ahb", NULL);
+	clk_register_clkdev(clk, "stmmaceth", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "apb", NULL);
+	clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1



From javier.martin at vista-silicon.com  Mon Aug 20 06:13:01 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 20 Aug 2012 12:13:01 +0200
Subject: [PATCH v3] Visstrim SM10: Use mo_version to decide board video mode.
Message-ID: <1345457581-13837-1-git-send-email-javier.martin@vista-silicon.com>

If the mother board version number is odd, emmaprp() for
format conversion + UVC camera will be used.

Otherwise mx2_camera and m2m-deinterlacer will be registered.

For both cases Coda video codec is registered.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
This patch should go through the media-tree because it depends on the following
patches that have already made through it:

 [PATCH v2 3/3] Visstrim M10: Add support for Coda. 
 [PATCH 2/2] i.MX27: Visstrim_M10: Add support for deinterlacing driver. 

For this reason I've added Mauro to CC and I will need Sascha's ACK.

Changes since v2:
- Remove redundant 'return' pointed out by Baruch.
---
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   52 ++++++++++++++++++++++++---
 1 file changed, 47 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 176533e..1d6830f 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -49,6 +49,10 @@
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
 
+#define VERSION_MASK		0x7
+#define MOTHERBOARD_SHIFT	4
+#define EXPBOARD_SHIFT		0
+
 #define MOTHERBOARD_BIT2	(GPIO_PORTD + 31)
 #define MOTHERBOARD_BIT1	(GPIO_PORTD + 30)
 #define MOTHERBOARD_BIT0	(GPIO_PORTD + 29)
@@ -205,7 +209,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
 static phys_addr_t mx2_camera_base __initdata;
 #define MX2_CAMERA_BUF_SIZE SZ_8M
 
-static void __init visstrim_camera_init(void)
+static void __init visstrim_analog_camera_init(void)
 {
 	struct platform_device *pdev;
 	int dma;
@@ -442,6 +446,27 @@ static void __init visstrim_deinterlace_init(void)
 		return;
 }
 
+/* Emma-PrP for format conversion */
+static void __init visstrim_emmaprp_init(void)
+{
+	struct platform_device *pdev;
+	int dma;
+
+	pdev = imx27_add_mx2_emmaprp();
+	if (IS_ERR(pdev))
+		return;
+
+	/*
+	 * Use the same memory area as the analog camera since both
+	 * devices are, by nature, exclusive.
+	 */
+	dma = dma_declare_coherent_memory(&pdev->dev,
+				mx2_camera_base, mx2_camera_base,
+				MX2_CAMERA_BUF_SIZE,
+				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+	if (!(dma & DMA_MEMORY_MAP))
+		pr_err("Failed to declare memory for emmaprp\n");
+}
 
 static void __init visstrim_m10_revision(void)
 {
@@ -467,13 +492,14 @@ static void __init visstrim_m10_revision(void)
 	mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
 
 	system_rev = 0x27000;
-	system_rev |= (mo_version << 4);
-	system_rev |= exp_version;
+	system_rev |= (mo_version << MOTHERBOARD_SHIFT);
+	system_rev |= (exp_version << EXPBOARD_SHIFT);
 }
 
 static void __init visstrim_m10_board_init(void)
 {
 	int ret;
+	int mo_version;
 
 	imx27_soc_init();
 	visstrim_m10_revision();
@@ -505,8 +531,24 @@ static void __init visstrim_m10_board_init(void)
 	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
 				      &iclink_tvp5150, sizeof(iclink_tvp5150));
 	gpio_led_register_device(0, &visstrim_m10_led_data);
-	visstrim_deinterlace_init();
-	visstrim_camera_init();
+
+	/* Use mother board version to decide what video devices we shall use */
+	mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
+	if (mo_version & 0x1) {
+		visstrim_emmaprp_init();
+
+		/*
+		 * Despite not being used, tvp5150 must be
+		 * powered on to avoid I2C problems. To minimize
+		 * power consupmtion keep reset enabled.
+		 */
+		gpio_set_value(TVP5150_PWDN, 1);
+		ndelay(1);
+		gpio_set_value(TVP5150_RSTN, 0);
+	} else {
+		visstrim_deinterlace_init();
+		visstrim_analog_camera_init();
+	}
 	visstrim_coda_init();
 }
 
-- 
1.7.9.5



From b-cousson at ti.com  Mon Aug 20 06:21:56 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 20 Aug 2012 12:21:56 +0200
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <CALLhW=7yJTq_cfB=KGY5VT8fNO1u_hrY118ysihFuQA+gVFRuQ@mail.gmail.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
 <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>
 <501B609F.9030403@ti.com>
 <CALLhW=7yJTq_cfB=KGY5VT8fNO1u_hrY118ysihFuQA+gVFRuQ@mail.gmail.com>
Message-ID: <50320FC4.2020100@ti.com>

Hi Omar,

On 08/03/2012 05:52 PM, Omar Ramirez Luna wrote:
> On 3 August 2012 00:24, Vaibhav Hiremath <hvaibhav at ti.com> wrote:
>> On 8/3/2012 3:50 AM, Omar Ramirez Luna wrote:
>>> So in _enable:
>>>
>>>         _enable_clocks(oh);
>>>         if (soc_ops.enable_module)
>>>                 soc_ops.enable_module(oh);
>>>
>>> The enable_module part seems redundant to me, since the module should
>>> be already enabled by the first call to _enable_clocks.
>>
>> Yes they do same thing, I believe the plan is to get rid of all clock
>> leaf-nodes in the near future, and let hwmod handle module
>> enable/disable part.
> 
> If this is the case then an enable_module call is needed in my patch
> for when these changes are made. The original works fine but only
> because currently clock framework does what enable_module is doing.

Yes, that's the case, but I plan to remove most of the leaf clocks ASAP,
so we cannot rely on that.

> Please let me know if you want me to resend with this change.

Yes, could you please repost with that change?

It will be good as well that you remove the leaf clock and use the
parent clock of current leaf as the main_clock. In that case it will
ensure that this is the hwmod fmwk that does enable the modulemode and
not the clock fmwk.

Regards,
Benoit



From m.szyprowski at samsung.com  Mon Aug 20 06:47:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 12:47:25 +0200
Subject: [PATCH 0/3] Add code for setting coherent pool size
Message-ID: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>

Hi!

Aaro Koskinen and Josh Coombs reported that commit e9da6e9905e639 ("ARM:
dma-mapping: remove custom consistent dma region") introduced a
regresion. It turned out that the default 256KiB for atomic coherent
pool might not be enough. After that patch, some Kirkwood systems run
out of atomic coherent memory and fail without any meanfull message.

This patch series is an attempt to fix those issues by adding function
for setting coherent pool size from platform initialization code and
increasing the size of the pool for Kirkwood systems.

Best regards
Marek Szyprowski
Samsung Poland R&D Center

Patch summary:

Marek Szyprowski (3):
  ARM: DMA-Mapping: add function for setting coherent pool size from
    platform code
  ARM: DMA-Mapping: print warning when atomic coherent allocation fails
  ARM: Kirkwood: increase atomic coherent pool size

 arch/arm/include/asm/dma-mapping.h |    7 +++++++
 arch/arm/mach-kirkwood/common.c    |    7 +++++++
 arch/arm/mm/dma-mapping.c          |   22 +++++++++++++++++++++-
 3 files changed, 35 insertions(+), 1 deletions(-)

-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Mon Aug 20 06:47:26 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 12:47:26 +0200
Subject: [PATCH 1/3] ARM: DMA-Mapping: add function for setting coherent pool
 size from platform code
In-Reply-To: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1345459648-24263-2-git-send-email-m.szyprowski@samsung.com>

Some platforms might require to increase atomic coherent pool to make
sure that their device will be able to allocate all their buffers from
atomic context. This function can be also used to decrease atomic
coherent pool size if coherent allocations are not used for the given
sub-platform.

Suggested-by: Josh Coombs <josh.coombs at gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/include/asm/dma-mapping.h |    7 +++++++
 arch/arm/mm/dma-mapping.c          |   19 ++++++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 2ae842d..a53940d 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -203,6 +203,13 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
 }
 
 /*
+ * This can be called during early boot to increase the size of the atomic
+ * coherent DMA pool above the default value of 256KiB. It must be called 
+ * before postcore_initcall.
+ */
+extern void __init init_dma_coherent_pool_size(unsigned long size);
+
+/*
  * This can be called during boot to increase the size of the consistent
  * DMA region above it's default value of 2MB. It must be called before the
  * memory allocator is initialised, i.e. before any core_initcall.
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4e7d118..d1cc9c1 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -267,6 +267,8 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
 	vunmap(cpu_addr);
 }
 
+#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_256K
+
 struct dma_pool {
 	size_t size;
 	spinlock_t lock;
@@ -277,7 +279,7 @@ struct dma_pool {
 };
 
 static struct dma_pool atomic_pool = {
-	.size = SZ_256K,
+	.size = DEFAULT_DMA_COHERENT_POOL_SIZE,
 };
 
 static int __init early_coherent_pool(char *p)
@@ -287,6 +289,21 @@ static int __init early_coherent_pool(char *p)
 }
 early_param("coherent_pool", early_coherent_pool);
 
+void __init init_dma_coherent_pool_size(unsigned long size)
+{
+	/*
+	 * Catch any attempt to set the pool size too late.
+	 */
+	BUG_ON(atomic_pool.vaddr);
+
+	/*
+	 * Set architecture specific coherent pool size only if
+	 * it has not been changed by kernel command line parameter.
+	 */
+	if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
+		atomic_pool.size = size;
+}
+
 /*
  * Initialise the coherent pool for atomic allocations.
  */
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Mon Aug 20 06:47:28 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 12:47:28 +0200
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>

The default 256 KiB coherent pool may be too small for some of the Kirkwood
devices, so increase it to make sure that devices will be able to allocate
their buffers with GFP_ATOMIC flag.

Suggested-by: Josh Coombs <josh.coombs at gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-kirkwood/common.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c4b64ad..d748f50 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -517,6 +517,13 @@ void __init kirkwood_wdt_init(void)
 void __init kirkwood_init_early(void)
 {
 	orion_time_set_base(TIMER_VIRT_BASE);
+
+	/*
+	 * Some Kirkwood devices allocate their coherent buffers from atomic
+	 * context. Increase size of atomic coherent pool to make sure such
+	 * the allocations won't fail.
+	 */
+	init_dma_coherent_pool_size(SZ_1M);
 }
 
 int kirkwood_tclk;
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Mon Aug 20 06:47:27 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 12:47:27 +0200
Subject: [PATCH 2/3] ARM: DMA-Mapping: print warning when atomic coherent
 allocation fails
In-Reply-To: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>

Print a loud warning when system runs out of memory from atomic coherent
pool to let users notice the potential problem.

Reported-by: Aaro Koskinen <aaro.koskinen at iki.fi>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mm/dma-mapping.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index d1cc9c1..25963ea 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -461,6 +461,9 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 		bitmap_set(pool->bitmap, pageno, count);
 		ptr = pool->vaddr + PAGE_SIZE * pageno;
 		*ret_page = pool->page + pageno;
+	} else {
+		pr_err("Atomic coherent pool too small!\n"
+		       "Please increase it with coherent_pool= kernel parameter!\n");
 	}
 	spin_unlock_irqrestore(&pool->lock, flags);
 
-- 
1.7.1.569.g6f426



From lee.jones at linaro.org  Mon Aug 20 06:49:49 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 11:49:49 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
Message-ID: <20120820104944.GM8450@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Fri, 3 Aug 2012 15:45:50 +0100
Subject: [PATCH 1/1] mfd: Provide the PRCMU with its own IRQ domain

The PRCMU has its own USB, Thermal, GPIO, Modem, HSI and RTC drivers,
amongst other things. This patch allows those subordinate devices to
use it as an interrupt controller as and when they are DT enabled.

CC: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/db8500-prcmu.c |   48 ++++++++++++++++++++++++++++++++------------
 1 file changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 7040a00..de09113 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -270,6 +270,8 @@ static struct {
 	struct prcmu_fw_version version;
 } fw_info;
 
+static struct irq_domain *db8500_irq_domain;
+
 /*
  * This vector maps irq numbers to the bits in the bit field used in
  * communication with the PRCMU firmware.
@@ -2583,7 +2585,7 @@ static void prcmu_irq_mask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2597,7 +2599,7 @@ static void prcmu_irq_unmask(struct irq_data *d)
 
 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
 
-	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
 
 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
 
@@ -2637,9 +2639,37 @@ static char *fw_project_name(u8 project)
 	}
 }
 
+static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
+				irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(virq, &prcmu_irq_chip,
+				handle_simple_irq);
+	set_irq_flags(virq, IRQF_VALID);
+
+	return 0;
+}
+
+static struct irq_domain_ops db8500_irq_ops = {
+        .map    = db8500_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+static int db8500_irq_init(struct device_node *np)
+{
+	db8500_irq_domain = irq_domain_add_legacy(
+		np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE,
+		0, &db8500_irq_ops, NULL);
+
+	if (!db8500_irq_domain) {
+		pr_err("Failed to create irqdomain\n");
+		return -ENOSYS;
+	}
+
+	return 0;
+}
+
 void __init db8500_prcmu_early_init(void)
 {
-	unsigned int i;
 	if (cpu_is_u8500v2()) {
 		void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
 
@@ -2683,16 +2713,6 @@ void __init db8500_prcmu_early_init(void)
 	init_completion(&mb5_transfer.work);
 
 	INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
-
-	/* Initalize irqs. */
-	for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
-		unsigned int irq;
-
-		irq = IRQ_PRCMU_BASE + i;
-		irq_set_chip_and_handler(irq, &prcmu_irq_chip,
-					 handle_simple_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
 }
 
 static void __init init_prcm_registers(void)
@@ -2999,6 +3019,8 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
 		goto no_irq_return;
 	}
 
+	db8500_irq_init(np);
+
 	for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
 		if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
 			db8500_prcmu_devs[i].platform_data = ab8500_platdata;
-- 
1.7.9.5


From pavel at ucw.cz  Mon Aug 20 06:53:08 2012
From: pavel at ucw.cz (Pavel Machek)
Date: Mon, 20 Aug 2012 12:53:08 +0200
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
Message-ID: <20120820105308.GA906@elf.ucw.cz>

Hi!

> This patch adds support for 32-bit applications. The vectors page is a
> binary blob mapped into the application user space at 0xffff0000 (the
> AArch64 toolchain does not support compilation of AArch32 code). Full
> compatibility with ARMv7 user space is supported. The use of deprecated
> ARMv7 functionality (SWP, CP15 barriers) has been disabled by default on
> AArch64 kernels and unaligned LDM/STM is not supported.
> 
> Please note that only the ARM 32-bit EABI is supported, so no OABI
> compatibility.

> +struct compat_statfs {
> +	int		f_type;
> +	int		f_bsize;
> +	int		f_blocks;
> +	int		f_bfree;
> +	int		f_bavail;
> +	int		f_files;
> +	int		f_ffree;
> +	compat_fsid_t	f_fsid;
> +	int		f_namelen;	/* SunOS ignores this field. */

I'm sure it does. But is it good comment?

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From lee.jones at linaro.org  Mon Aug 20 06:53:36 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 11:53:36 +0100
Subject: [PATCH] mfd: ab8500: Make ab8500_irq_get_virq() static
Message-ID: <1345460017-404-1-git-send-email-lee.jones@linaro.org>

MFD core now takes care of  HWIRQ <-> VIRQ mapping, so the helper
ab8500_irq_get_virq() is no longer used by ab8500 subordinate devices
to obtain a Linux wide Virtual IRQ. The AB8500 IRQ controller still
uses it internally though, so we'll just hide it from the rest of the
world by making it static instead.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mfd/ab8500-core.c         |   33 ++++++++++++++++-----------------
 include/linux/mfd/abx500/ab8500.h |    2 --
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 71a7757..020c1a8 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -472,6 +472,22 @@ static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
 	return IRQ_HANDLED;
 }
 
+/**
+ * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
+ *
+ * @ab8500: ab8500_irq controller to operate on.
+ * @irq: index of the interrupt requested in the chip IRQs
+ *
+ * Useful for drivers to request their own IRQs.
+ */
+static int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
+{
+	if (!ab8500)
+		return -EINVAL;
+
+	return irq_create_mapping(ab8500->domain, irq);
+}
+
 static irqreturn_t ab8500_irq(int irq, void *dev)
 {
 	struct ab8500 *ab8500 = dev;
@@ -512,23 +528,6 @@ static irqreturn_t ab8500_irq(int irq, void *dev)
 	return IRQ_HANDLED;
 }
 
-/**
- * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
- *
- * @ab8500: ab8500_irq controller to operate on.
- * @irq: index of the interrupt requested in the chip IRQs
- *
- * Useful for drivers to request their own IRQs.
- */
-int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
-{
-	if (!ab8500)
-		return -EINVAL;
-
-	return irq_create_mapping(ab8500->domain, irq);
-}
-EXPORT_SYMBOL_GPL(ab8500_irq_get_virq);
-
 static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
 				irq_hw_number_t hwirq)
 {
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 3764cb6..1491044 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -341,6 +341,4 @@ static inline int is_ab8500_2p0(struct ab8500 *ab)
 	return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
 }
 
-int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq);
-
 #endif /* MFD_AB8500_H */
-- 
1.7.9.5



From alanbutty12 at gmail.com  Mon Aug 20 07:16:31 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 12:16:31 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 DT support Signed-off-by: Alan
 M Butler <alanbutty12@gmail.com>
In-Reply-To: <cover.1345459608.git.alanbutty12@gmail.com>
References: <cover.1345459608.git.alanbutty12@gmail.com>
Message-ID: <1d07faa52b5ca4453c7eaa7c9decb01af92ee648.1345459608.git.alanbutty12@gmail.com>

Patch version 4.
Add support for the Iomega ix2-200.
Led's and buttons working as of kernel 3.6-rc2
Product page:
http://go.iomega.com/en/products/network-storage-desktop/storcenter-network-storage-solution/network-hard-drive-ix2-200-cloud/?partner=4735#tech_specsItem_tab

Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

---
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   79 +++++++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 203 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 0000000..865aeec
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Iomega StorCenter ix2-200";
+	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		i2c at 11000 {
+			status = "okay";
+
+			lm63: lm63 at 4c {
+				compatible = "national,lm63";
+				reg = <0x4c>;
+			};
+		};
+
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at a0000 {
+				label = "env";
+				reg = <0xa0000 0x20000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x100000 0x300000>;
+			};
+
+			partition at 400000 {
+				label = "uInitrd";
+				reg = <0x540000 0x1000000>;
+			};
+		};
+		sata at 80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			label = "status:white:power_led";
+			gpios = <&gpio0 16 0>;
+			linux,default-trigger = "default-on";
+		};
+		health_led1 {
+			label = "status:red:health_led";
+			gpios = <&gpio1 5 0>;
+		};
+		health_led2 {
+			label = "status:white:health_led";
+			gpios = <&gpio1 4 0>;
+		};
+		backup_led {
+			label = "status:blue:backup_led";
+			gpios = <&gpio0 15 0>;
+		};
+	};
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		Power {
+			label = "Power Button";
+			linux,code = <116>;
+			gpios = <&gpio0 14 1>;
+		};
+		Reset {
+			label = "Reset Button";
+			linux,code = <0x198>;
+			gpios = <&gpio0 12 1>;
+		};
+		OTB {
+			label = "OTB Button";
+			linux,code = <133>;
+			gpios = <&gpio1 3 1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..bee8451 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -195,6 +195,13 @@ config MACH_T5325
 	  Say 'Y' here if you want your kernel to support the
 	  HP t5325 Thin Client.
 
+config MACH_IOMEGA_IX2_200_DT
+	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Iomega StorCenter ix2-200 (Flattened Device Tree).
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..f5484dc 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a571755..59b719d 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..9b3ec17 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
+	if (of_machine_is_compatible("iom,ix2-200"))
+		iomega_ix2_200_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"iom,ix2-200",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 0000000..0c78752
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <net/dsa.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+	.phy_addr       = MV643XX_ETH_PHY_NONE,
+	.speed          = SPEED_1000,
+	.duplex         = DUPLEX_FULL,
+};
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(11),
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+	MPP12_GPIO,			/* Reset Button */
+	MPP14_GPIO,			/* Power Button */
+	MPP15_GPIO,			/* Backup LED (blue) */
+	MPP16_GPIO,			/* Power LED (white) */
+	MPP35_GPIO,			/* OTB Button */
+	MPP36_GPIO,			/* Rebuild LED (white) */
+	MPP37_GPIO,			/* Health LED (red) */
+	MPP38_GPIO,			/* SATA LED brightness control 1 */
+	MPP39_GPIO,			/* SATA LED brightness control 2 */
+	MPP40_GPIO,			/* Backup LED brightness control 1 */
+	MPP41_GPIO,			/* Backup LED brightness control 2 */
+	MPP42_GPIO,			/* Power LED brightness control 1 */
+	MPP43_GPIO,			/* Power LED brightness control 2 */
+	MPP44_GPIO,			/* Health LED brightness control 1 */
+	MPP45_GPIO,			/* Health LED brightness control 2 */
+	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
+	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
+	0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+	kirkwood_ehci_init();
+
+	kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
+	kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
+}
+static int __init iomega_ix2_200_pci_init(void)
+{
+	if (of_machine_is_compatible("iom,ix2-200"))
+		kirkwood_pcie_init(KW_PCIE0);
+	return 0;
+}
+subsys_initcall(iomega_ix2_200_pci_init);
+
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..d5d4064 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.9.5



From sourav.poddar at ti.com  Mon Aug 20 07:19:36 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Mon, 20 Aug 2012 16:49:36 +0530
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>
References: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>

Hi All,

On Tue, Aug 14, 2012 at 4:45 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
> Add keypad data node in omap4 device tree file.
> Also fill the device tree binding parameters
> with the required value in "omap4-sdp" dts file.
>
> Tested on omap4430 sdp.
>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
> v6->v7
> Add key name as a comment.
>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>  2 files changed, 75 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> index 72216e9..8e200f4 100644
> --- a/arch/arm/boot/dts/omap4-sdp.dts
> +++ b/arch/arm/boot/dts/omap4-sdp.dts
> @@ -113,6 +113,76 @@
>                         "DMic", "Digital Mic",
>                         "Digital Mic", "Digital Mic1 Bias";
>         };
> +
> +       keypad {
> +               keypad,num-rows = <8>;
> +               keypad,num-columns = <8>;
> +               linux,keymap = < 0x00000012 /* KEY_E */
> +                       0x00010013 /* KEY_R */
> +                       0x00020014 /* KEY_T */
> +                       0x00030066 /* KEY_HOME */
> +                       0x0004003f /* KEY_F5 */
> +                       0x000500f0 /* KEY_UNKNOWN */
> +                       0x00060017 /* KEY_I */
> +                       0x0007002a /* KEY_LEFTSHIFT */
> +                       0x01000020 /* KEY_D*/
> +                       0x01010021 /* KEY_F */
> +                       0x01020022 /* KEY_G */
> +                       0x010300e7 /* KEY_SEND */
> +                       0x01040040 /* KEY_F6 */
> +                       0x010500f0 /* KEY_UNKNOWN */
> +                       0x01060025 /* KEY_K */
> +                       0x0107001c /* KEY_ENTER */
> +                       0x0200002d /* KEY_X */
> +                       0x0201002e /* KEY_C */
> +                       0x0202002f /* KEY_V */
> +                       0x0203006b /* KEY_END */
> +                       0x02040041 /* KEY_F7 */
> +                       0x020500f0 /* KEY_UNKNOWN */
> +                       0x02060034 /* KEY_DOT */
> +                       0x0207003a /* KEY_CAPSLOCK */
> +                       0x0300002c /* KEY_Z */
> +                       0x0301004e /* KEY_KPLUS */
> +                       0x03020030 /* KEY_B */
> +                       0x0303003b /* KEY_F1 */
> +                       0x03040042 /* KEY_F8 */
> +                       0x030500f0 /* KEY_UNKNOWN */
> +                       0x03060018 /* KEY_O */
> +                       0x03070039 /* KEY_SPACE */
> +                       0x04000011 /* KEY_W */
> +                       0x04010015 /* KEY_Y */
> +                       0x04020016 /* KEY_U */
> +                       0x0403003c /* KEY_F2 */
> +                       0x04040073 /* KEY_VOLUMEUP */
> +                       0x040500f0 /* KEY_UNKNOWN */
> +                       0x04060026 /* KEY_L */
> +                       0x04070069 /* KEY_LEFT */
> +                       0x0500001f /* KEY_S */
> +                       0x05010023 /* KEY_H */
> +                       0x05020024 /* KEY_J */
> +                       0x0503003d /* KEY_F3 */
> +                       0x05040043 /* KEY_F9 */
> +                       0x05050072 /* KEY_VOLUMEDOWN */
> +                       0x05060032 /* KEY_M */
> +                       0x0507006a /* KEY_RIGHT */
> +                       0x06000010 /* KEY_Q */
> +                       0x0601001e /* KEY_A */
> +                       0x06020031 /* KEY_N */
> +                       0x0603009e /* KEY_BACK */
> +                       0x0604000e /* KEY_BACKSPACE */
> +                       0x060500f0 /* KEY_UNKNOWN */
> +                       0x06060019 /* KEY_P */
> +                       0x06070067 /* KEY_UP */
> +                       0x07000094 /* KEY_PROG1 */
> +                       0x07010095 /* KEY_PROG2 */
> +                       0x070200ca /* KEY_PROG3 */
> +                       0x070300cb /* KEY_PROG4 */
> +                       0x0704003e /* KEY_F4 */
> +                       0x070500f0 /* KEY_UNKNOWN */
> +                       0x07060160 /* KEY_OK */
> +                       0x0707006c >; /* KEY_DOWN */
> +               linux,input-no-autorepeat;
> +       };
>  };
>
>  &i2c1 {
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 04cbbcb..e78a1f1 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -296,4 +296,9 @@
>                         ti,hwmods = "dmic";
>                 };
>         };
> +
> +       keypad {
> +               compatible = "ti,omap4-keypad";
> +               ti,hwmods = "kbd";
> +       };
>  };
> --
> 1.7.1
>
Any more comments on this?

~Sourav


From prabhakar.lad at ti.com  Mon Aug 20 07:29:57 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Mon, 20 Aug 2012 16:59:57 +0530
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous
 Memory Allocator
In-Reply-To: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
References: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <50321FB5.90507@ti.com>

Hi Marek,

Thanks for the patch.

On Monday 20 August 2012 11:46 AM, Marek Szyprowski wrote:
> Contiguous Memory Allocator requires only paging and MMU enabled not
> particular CPU architectures, so there is no need for strict dependency
> on CPU type. This enables to use CMA on some older ARM v5 systems which
> also might need large contiguous blocks for the multimedia processing hw
> modules.
> 
> Reported-by: Prabhakar Lad <prabhakar.csengg at gmail.com>

  Reported-by: Prabhakar Lad <prabhakar.lad at ti.com>
  Tested-by: Prabhakar Lad <prabhakar.lad at ti.com>

Thx,
--Prabhakar

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> ---
>  arch/arm/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..6ef75e2 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -6,7 +6,7 @@ config ARM
>  	select HAVE_DMA_API_DEBUG
>  	select HAVE_IDE if PCI || ISA || PCMCIA
>  	select HAVE_DMA_ATTRS
> -	select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
> +	select HAVE_DMA_CONTIGUOUS if MMU
>  	select HAVE_MEMBLOCK
>  	select RTC_LIB
>  	select SYS_SUPPORTS_APM_EMULATION
> 



From lee.jones at linaro.org  Mon Aug 20 07:34:31 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 12:34:31 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <s5h628lu0q9.wl%tiwai@suse.de>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de>
Message-ID: <20120820113427.GN8450@gmail.com>

From: Lee Jones <lee.jones at linaro.org>
Date: Fri, 27 Jul 2012 08:50:05 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree

We continue to allow the AB8500 CODEC to be registered via the AB8500
Multi Functional Device API, only this time we extract its configuration
from the Device Tree binary.

CC: alsa-devel at alsa-project.org
Acked-by: Ola Lilja <ola.o.lilja at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/mfd/abx500/ab8500-codec.h |    6 ++-
 sound/soc/codecs/ab8500-codec.c         |   81 +++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/include/linux/mfd/abx500/ab8500-codec.h b/include/linux/mfd/abx500/ab8500-codec.h
index dc65292..d707941 100644
--- a/include/linux/mfd/abx500/ab8500-codec.h
+++ b/include/linux/mfd/abx500/ab8500-codec.h
@@ -23,7 +23,8 @@ enum amic_type {
 /* Mic-biases */
 enum amic_micbias {
 	AMIC_MICBIAS_VAMIC1,
-	AMIC_MICBIAS_VAMIC2
+	AMIC_MICBIAS_VAMIC2,
+	AMIC_MICBIAS_UNKNOWN
 };
 
 /* Bias-voltage */
@@ -31,7 +32,8 @@ enum ear_cm_voltage {
 	EAR_CMV_0_95V,
 	EAR_CMV_1_10V,
 	EAR_CMV_1_27V,
-	EAR_CMV_1_58V
+	EAR_CMV_1_58V,
+	EAR_CMV_UNKNOWN
 };
 
 /* Analog microphone settings */
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 23b4018..99dffcf 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -34,6 +34,7 @@
 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 #include <linux/mfd/abx500/ab8500-codec.h>
 #include <linux/regulator/consumer.h>
+#include <linux/of.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -2394,9 +2395,65 @@ struct snd_soc_dai_driver ab8500_codec_dai[] = {
 	}
 };
 
+static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
+				struct ab8500_codec_platform_data *codec)
+{
+	u32 value;
+
+	if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
+		codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
+
+	if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
+		codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
+
+	/* Has a non-standard Vamic been requested? */
+	if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
+	else
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
+
+	if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
+		switch (value) {
+		case 950 :
+			codec->ear_cmv = EAR_CMV_0_95V;
+			break;
+		case 1100 :
+			codec->ear_cmv = EAR_CMV_1_10V;
+			break;
+		case 1270 :
+			codec->ear_cmv = EAR_CMV_1_27V;
+			break;
+		case 1580 :
+			codec->ear_cmv = EAR_CMV_1_58V;
+			break;
+		default :
+			codec->ear_cmv = EAR_CMV_UNKNOWN;
+			dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
+		}
+	} else {
+		dev_warn(dev, "No earpiece voltage found in DT - using default\n");
+		codec->ear_cmv = EAR_CMV_0_95V;
+	}
+}
+
 static int ab8500_codec_probe(struct snd_soc_codec *codec)
 {
 	struct device *dev = codec->dev;
+	struct device_node *np = dev->of_node;
 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
 	struct ab8500_platform_data *pdata;
 	struct filter_control *fc;
@@ -2407,6 +2464,30 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
 	/* Setup AB8500 according to board-settings */
 	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
 
+	if (np) {
+		if (!pdata)
+			pdata = devm_kzalloc(dev,
+					sizeof(struct ab8500_platform_data),
+					GFP_KERNEL);
+
+		if (pdata && !pdata->codec)
+			pdata->codec
+				= devm_kzalloc(dev,
+					sizeof(struct ab8500_codec_platform_data),
+					GFP_KERNEL);
+
+		if (!(pdata && pdata->codec))
+			return -ENOMEM;
+
+		ab8500_codec_of_probe(dev, np, pdata->codec);
+
+	} else {
+		if (!(pdata && pdata->codec)) {
+			dev_err(dev, "No codec platform data or DT found\n");
+			return -EINVAL;
+		}
+	}
+
 	/* Inform SoC Core that we have our own I/O arrangements. */
 	codec->control_data = (void *)true;
 
-- 
1.7.9.5


From balbi at ti.com  Mon Aug 20 07:34:49 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 20 Aug 2012 14:34:49 +0300
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>
References: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>
Message-ID: <20120820113448.GO17455@arwen.pp.htv.fi>

On Mon, Aug 20, 2012 at 04:49:36PM +0530, Poddar, Sourav wrote:
> Hi All,
> 
> On Tue, Aug 14, 2012 at 4:45 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
> > Add keypad data node in omap4 device tree file.
> > Also fill the device tree binding parameters
> > with the required value in "omap4-sdp" dts file.
> >
> > Tested on omap4430 sdp.
> >
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Rob Herring <rob.herring at calxeda.com>
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > Cc: Felipe Balbi <balbi at ti.com>

to me it looks good. you've even added comments on each key for easy
human parsing.

Acked-by: Felipe Balbi <balbi at ti.com>

> > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> > ---
> > v6->v7
> > Add key name as a comment.
> >  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/omap4.dtsi    |    5 +++
> >  2 files changed, 75 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
> > index 72216e9..8e200f4 100644
> > --- a/arch/arm/boot/dts/omap4-sdp.dts
> > +++ b/arch/arm/boot/dts/omap4-sdp.dts
> > @@ -113,6 +113,76 @@
> >                         "DMic", "Digital Mic",
> >                         "Digital Mic", "Digital Mic1 Bias";
> >         };
> > +
> > +       keypad {
> > +               keypad,num-rows = <8>;
> > +               keypad,num-columns = <8>;
> > +               linux,keymap = < 0x00000012 /* KEY_E */
> > +                       0x00010013 /* KEY_R */
> > +                       0x00020014 /* KEY_T */
> > +                       0x00030066 /* KEY_HOME */
> > +                       0x0004003f /* KEY_F5 */
> > +                       0x000500f0 /* KEY_UNKNOWN */
> > +                       0x00060017 /* KEY_I */
> > +                       0x0007002a /* KEY_LEFTSHIFT */
> > +                       0x01000020 /* KEY_D*/
> > +                       0x01010021 /* KEY_F */
> > +                       0x01020022 /* KEY_G */
> > +                       0x010300e7 /* KEY_SEND */
> > +                       0x01040040 /* KEY_F6 */
> > +                       0x010500f0 /* KEY_UNKNOWN */
> > +                       0x01060025 /* KEY_K */
> > +                       0x0107001c /* KEY_ENTER */
> > +                       0x0200002d /* KEY_X */
> > +                       0x0201002e /* KEY_C */
> > +                       0x0202002f /* KEY_V */
> > +                       0x0203006b /* KEY_END */
> > +                       0x02040041 /* KEY_F7 */
> > +                       0x020500f0 /* KEY_UNKNOWN */
> > +                       0x02060034 /* KEY_DOT */
> > +                       0x0207003a /* KEY_CAPSLOCK */
> > +                       0x0300002c /* KEY_Z */
> > +                       0x0301004e /* KEY_KPLUS */
> > +                       0x03020030 /* KEY_B */
> > +                       0x0303003b /* KEY_F1 */
> > +                       0x03040042 /* KEY_F8 */
> > +                       0x030500f0 /* KEY_UNKNOWN */
> > +                       0x03060018 /* KEY_O */
> > +                       0x03070039 /* KEY_SPACE */
> > +                       0x04000011 /* KEY_W */
> > +                       0x04010015 /* KEY_Y */
> > +                       0x04020016 /* KEY_U */
> > +                       0x0403003c /* KEY_F2 */
> > +                       0x04040073 /* KEY_VOLUMEUP */
> > +                       0x040500f0 /* KEY_UNKNOWN */
> > +                       0x04060026 /* KEY_L */
> > +                       0x04070069 /* KEY_LEFT */
> > +                       0x0500001f /* KEY_S */
> > +                       0x05010023 /* KEY_H */
> > +                       0x05020024 /* KEY_J */
> > +                       0x0503003d /* KEY_F3 */
> > +                       0x05040043 /* KEY_F9 */
> > +                       0x05050072 /* KEY_VOLUMEDOWN */
> > +                       0x05060032 /* KEY_M */
> > +                       0x0507006a /* KEY_RIGHT */
> > +                       0x06000010 /* KEY_Q */
> > +                       0x0601001e /* KEY_A */
> > +                       0x06020031 /* KEY_N */
> > +                       0x0603009e /* KEY_BACK */
> > +                       0x0604000e /* KEY_BACKSPACE */
> > +                       0x060500f0 /* KEY_UNKNOWN */
> > +                       0x06060019 /* KEY_P */
> > +                       0x06070067 /* KEY_UP */
> > +                       0x07000094 /* KEY_PROG1 */
> > +                       0x07010095 /* KEY_PROG2 */
> > +                       0x070200ca /* KEY_PROG3 */
> > +                       0x070300cb /* KEY_PROG4 */
> > +                       0x0704003e /* KEY_F4 */
> > +                       0x070500f0 /* KEY_UNKNOWN */
> > +                       0x07060160 /* KEY_OK */
> > +                       0x0707006c >; /* KEY_DOWN */
> > +               linux,input-no-autorepeat;
> > +       };
> >  };
> >
> >  &i2c1 {
> > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > index 04cbbcb..e78a1f1 100644
> > --- a/arch/arm/boot/dts/omap4.dtsi
> > +++ b/arch/arm/boot/dts/omap4.dtsi
> > @@ -296,4 +296,9 @@
> >                         ti,hwmods = "dmic";
> >                 };
> >         };
> > +
> > +       keypad {
> > +               compatible = "ti,omap4-keypad";
> > +               ti,hwmods = "kbd";
> > +       };
> >  };
> > --
> > 1.7.1
> >
> Any more comments on this?
> 
> ~Sourav

-- 
balbi
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From andrew at lunn.ch  Mon Aug 20 07:43:20 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 Aug 2012 13:43:20 +0200
Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 DT support Signed-off-by:
 Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <1d07faa52b5ca4453c7eaa7c9decb01af92ee648.1345459608.git.alanbutty12@gmail.com>
References: <cover.1345459608.git.alanbutty12@gmail.com>
 <1d07faa52b5ca4453c7eaa7c9decb01af92ee648.1345459608.git.alanbutty12@gmail.com>
Message-ID: <20120820114320.GB26837@lunn.ch>

Hi Alan

Overall this is looking good.

Just a few minor comments below.

> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> new file mode 100644
> index 0000000..0c78752
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> @@ -0,0 +1,79 @@
> +/*
> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> + *
> + * Iomega StorCenter ix2-200
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/irq.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/ata_platform.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/ethtool.h>
> +#include <net/dsa.h>
> +#include <linux/gpio.h>
> +#include <linux/leds.h>
> +#include <linux/i2c.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <mach/kirkwood.h>
> +#include "common.h"
> +#include "mpp.h"

It would be good to remove all the unneeded include files.

> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> +	.phy_addr       = MV643XX_ETH_PHY_NONE,
> +	.speed          = SPEED_1000,
> +	.duplex         = DUPLEX_FULL,
> +};

It is somewhat unusual to have this configuration, 1000 full. Is this
a hardware limitation? Or is the port connected to an internal switch?
Maybe add a comment why its hard coded.

      Andrew



From b-cousson at ti.com  Mon Aug 20 07:53:34 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 20 Aug 2012 13:53:34 +0200
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>
References: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>
Message-ID: <5032253E.9000106@ti.com>

Hi Sourav,

On 08/20/2012 01:19 PM, Poddar, Sourav wrote:
> Hi All,
> 
> On Tue, Aug 14, 2012 at 4:45 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>> Add keypad data node in omap4 device tree file.
>> Also fill the device tree binding parameters
>> with the required value in "omap4-sdp" dts file.
>>
>> Tested on omap4430 sdp.
>>
>> Cc: Tony Lindgren <tony at atomide.com>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>> v6->v7
>> Add key name as a comment.
>>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>>  2 files changed, 75 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
>> index 72216e9..8e200f4 100644
>> --- a/arch/arm/boot/dts/omap4-sdp.dts
>> +++ b/arch/arm/boot/dts/omap4-sdp.dts
>> @@ -113,6 +113,76 @@
>>                         "DMic", "Digital Mic",
>>                         "Digital Mic", "Digital Mic1 Bias";
>>         };
>> +
>> +       keypad {
>> +               keypad,num-rows = <8>;
>> +               keypad,num-columns = <8>;
>> +               linux,keymap = < 0x00000012 /* KEY_E */
>> +                       0x00010013 /* KEY_R */
>> +                       0x00020014 /* KEY_T */
>> +                       0x00030066 /* KEY_HOME */
>> +                       0x0004003f /* KEY_F5 */
>> +                       0x000500f0 /* KEY_UNKNOWN */
>> +                       0x00060017 /* KEY_I */
>> +                       0x0007002a /* KEY_LEFTSHIFT */
>> +                       0x01000020 /* KEY_D*/
>> +                       0x01010021 /* KEY_F */
>> +                       0x01020022 /* KEY_G */
>> +                       0x010300e7 /* KEY_SEND */
>> +                       0x01040040 /* KEY_F6 */
>> +                       0x010500f0 /* KEY_UNKNOWN */
>> +                       0x01060025 /* KEY_K */
>> +                       0x0107001c /* KEY_ENTER */
>> +                       0x0200002d /* KEY_X */
>> +                       0x0201002e /* KEY_C */
>> +                       0x0202002f /* KEY_V */
>> +                       0x0203006b /* KEY_END */
>> +                       0x02040041 /* KEY_F7 */
>> +                       0x020500f0 /* KEY_UNKNOWN */
>> +                       0x02060034 /* KEY_DOT */
>> +                       0x0207003a /* KEY_CAPSLOCK */
>> +                       0x0300002c /* KEY_Z */
>> +                       0x0301004e /* KEY_KPLUS */
>> +                       0x03020030 /* KEY_B */
>> +                       0x0303003b /* KEY_F1 */
>> +                       0x03040042 /* KEY_F8 */
>> +                       0x030500f0 /* KEY_UNKNOWN */
>> +                       0x03060018 /* KEY_O */
>> +                       0x03070039 /* KEY_SPACE */
>> +                       0x04000011 /* KEY_W */
>> +                       0x04010015 /* KEY_Y */
>> +                       0x04020016 /* KEY_U */
>> +                       0x0403003c /* KEY_F2 */
>> +                       0x04040073 /* KEY_VOLUMEUP */
>> +                       0x040500f0 /* KEY_UNKNOWN */
>> +                       0x04060026 /* KEY_L */
>> +                       0x04070069 /* KEY_LEFT */
>> +                       0x0500001f /* KEY_S */
>> +                       0x05010023 /* KEY_H */
>> +                       0x05020024 /* KEY_J */
>> +                       0x0503003d /* KEY_F3 */
>> +                       0x05040043 /* KEY_F9 */
>> +                       0x05050072 /* KEY_VOLUMEDOWN */
>> +                       0x05060032 /* KEY_M */
>> +                       0x0507006a /* KEY_RIGHT */
>> +                       0x06000010 /* KEY_Q */
>> +                       0x0601001e /* KEY_A */
>> +                       0x06020031 /* KEY_N */
>> +                       0x0603009e /* KEY_BACK */
>> +                       0x0604000e /* KEY_BACKSPACE */
>> +                       0x060500f0 /* KEY_UNKNOWN */
>> +                       0x06060019 /* KEY_P */
>> +                       0x06070067 /* KEY_UP */
>> +                       0x07000094 /* KEY_PROG1 */
>> +                       0x07010095 /* KEY_PROG2 */
>> +                       0x070200ca /* KEY_PROG3 */
>> +                       0x070300cb /* KEY_PROG4 */
>> +                       0x0704003e /* KEY_F4 */
>> +                       0x070500f0 /* KEY_UNKNOWN */
>> +                       0x07060160 /* KEY_OK */
>> +                       0x0707006c >; /* KEY_DOWN */
>> +               linux,input-no-autorepeat;
>> +       };
>>  };
>>
>>  &i2c1 {
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 04cbbcb..e78a1f1 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -296,4 +296,9 @@
>>                         ti,hwmods = "dmic";
>>                 };
>>         };
>> +
>> +       keypad {
>> +               compatible = "ti,omap4-keypad";
>> +               ti,hwmods = "kbd";
>> +       };
>>  };
>> --
>> 1.7.1
>>
> Any more comments on this?

That's perfect.

I'll take it and send it with other DT patches to Tony.

Regards,
Benoit



From sourav.poddar at ti.com  Mon Aug 20 07:56:53 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Mon, 20 Aug 2012 17:26:53 +0530
Subject: [PATCHv7] arm/dts: omap4-sdp: Add keypad data
In-Reply-To: <5032253E.9000106@ti.com>
References: <1344942937-4685-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57n1jA5_7EOLcsB=u5X4wX6hPVXoZ2HLrnpEKS3kLZ=OQ@mail.gmail.com>
 <5032253E.9000106@ti.com>
Message-ID: <CAKdam55faoLjstiGjsLq8LOgnc=DfL=moBENT-Y7SN3ZGxx_Mw@mail.gmail.com>

On Mon, Aug 20, 2012 at 5:23 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Sourav,
>
> On 08/20/2012 01:19 PM, Poddar, Sourav wrote:
>> Hi All,
>>
>> On Tue, Aug 14, 2012 at 4:45 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>>> Add keypad data node in omap4 device tree file.
>>> Also fill the device tree binding parameters
>>> with the required value in "omap4-sdp" dts file.
>>>
>>> Tested on omap4430 sdp.
>>>
>>> Cc: Tony Lindgren <tony at atomide.com>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> Cc: Felipe Balbi <balbi at ti.com>
>>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>>> ---
>>> v6->v7
>>> Add key name as a comment.
>>>  arch/arm/boot/dts/omap4-sdp.dts |   70 +++++++++++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/omap4.dtsi    |    5 +++
>>>  2 files changed, 75 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
>>> index 72216e9..8e200f4 100644
>>> --- a/arch/arm/boot/dts/omap4-sdp.dts
>>> +++ b/arch/arm/boot/dts/omap4-sdp.dts
>>> @@ -113,6 +113,76 @@
>>>                         "DMic", "Digital Mic",
>>>                         "Digital Mic", "Digital Mic1 Bias";
>>>         };
>>> +
>>> +       keypad {
>>> +               keypad,num-rows = <8>;
>>> +               keypad,num-columns = <8>;
>>> +               linux,keymap = < 0x00000012 /* KEY_E */
>>> +                       0x00010013 /* KEY_R */
>>> +                       0x00020014 /* KEY_T */
>>> +                       0x00030066 /* KEY_HOME */
>>> +                       0x0004003f /* KEY_F5 */
>>> +                       0x000500f0 /* KEY_UNKNOWN */
>>> +                       0x00060017 /* KEY_I */
>>> +                       0x0007002a /* KEY_LEFTSHIFT */
>>> +                       0x01000020 /* KEY_D*/
>>> +                       0x01010021 /* KEY_F */
>>> +                       0x01020022 /* KEY_G */
>>> +                       0x010300e7 /* KEY_SEND */
>>> +                       0x01040040 /* KEY_F6 */
>>> +                       0x010500f0 /* KEY_UNKNOWN */
>>> +                       0x01060025 /* KEY_K */
>>> +                       0x0107001c /* KEY_ENTER */
>>> +                       0x0200002d /* KEY_X */
>>> +                       0x0201002e /* KEY_C */
>>> +                       0x0202002f /* KEY_V */
>>> +                       0x0203006b /* KEY_END */
>>> +                       0x02040041 /* KEY_F7 */
>>> +                       0x020500f0 /* KEY_UNKNOWN */
>>> +                       0x02060034 /* KEY_DOT */
>>> +                       0x0207003a /* KEY_CAPSLOCK */
>>> +                       0x0300002c /* KEY_Z */
>>> +                       0x0301004e /* KEY_KPLUS */
>>> +                       0x03020030 /* KEY_B */
>>> +                       0x0303003b /* KEY_F1 */
>>> +                       0x03040042 /* KEY_F8 */
>>> +                       0x030500f0 /* KEY_UNKNOWN */
>>> +                       0x03060018 /* KEY_O */
>>> +                       0x03070039 /* KEY_SPACE */
>>> +                       0x04000011 /* KEY_W */
>>> +                       0x04010015 /* KEY_Y */
>>> +                       0x04020016 /* KEY_U */
>>> +                       0x0403003c /* KEY_F2 */
>>> +                       0x04040073 /* KEY_VOLUMEUP */
>>> +                       0x040500f0 /* KEY_UNKNOWN */
>>> +                       0x04060026 /* KEY_L */
>>> +                       0x04070069 /* KEY_LEFT */
>>> +                       0x0500001f /* KEY_S */
>>> +                       0x05010023 /* KEY_H */
>>> +                       0x05020024 /* KEY_J */
>>> +                       0x0503003d /* KEY_F3 */
>>> +                       0x05040043 /* KEY_F9 */
>>> +                       0x05050072 /* KEY_VOLUMEDOWN */
>>> +                       0x05060032 /* KEY_M */
>>> +                       0x0507006a /* KEY_RIGHT */
>>> +                       0x06000010 /* KEY_Q */
>>> +                       0x0601001e /* KEY_A */
>>> +                       0x06020031 /* KEY_N */
>>> +                       0x0603009e /* KEY_BACK */
>>> +                       0x0604000e /* KEY_BACKSPACE */
>>> +                       0x060500f0 /* KEY_UNKNOWN */
>>> +                       0x06060019 /* KEY_P */
>>> +                       0x06070067 /* KEY_UP */
>>> +                       0x07000094 /* KEY_PROG1 */
>>> +                       0x07010095 /* KEY_PROG2 */
>>> +                       0x070200ca /* KEY_PROG3 */
>>> +                       0x070300cb /* KEY_PROG4 */
>>> +                       0x0704003e /* KEY_F4 */
>>> +                       0x070500f0 /* KEY_UNKNOWN */
>>> +                       0x07060160 /* KEY_OK */
>>> +                       0x0707006c >; /* KEY_DOWN */
>>> +               linux,input-no-autorepeat;
>>> +       };
>>>  };
>>>
>>>  &i2c1 {
>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>> index 04cbbcb..e78a1f1 100644
>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>> @@ -296,4 +296,9 @@
>>>                         ti,hwmods = "dmic";
>>>                 };
>>>         };
>>> +
>>> +       keypad {
>>> +               compatible = "ti,omap4-keypad";
>>> +               ti,hwmods = "kbd";
>>> +       };
>>>  };
>>> --
>>> 1.7.1
>>>
>> Any more comments on this?
>
> That's perfect.
>
> I'll take it and send it with other DT patches to Tony.
>
Thanks Benoit !!
> Regards,
> Benoit
>


From lee.jones at linaro.org  Mon Aug 20 07:59:25 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 12:59:25 +0100
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
 <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
Message-ID: <20120820115914.GP8450@gmail.com>

On Tue, Aug 14, 2012 at 10:51:02AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > In the initial submission of the MSP driver msp1 and msp3's associated
> > pinctrl mechanism was passed back to platform code using a plat_init()
> > call-back routine, but it has no place in platform code. The MSP driver
> > should set this up for the appropriate ports. Instead we use a use_pinctrl
> > identifier which is passed from platform_data/Device Tree which indicates
> > which ports should use pinctrl.
> >
> > CC: alsa-devel at alsa-project.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This is very good because it rids platform code and makes the driver
> self-contained without strange platform data hooks.
> 
> Now details...
> 
> > +/* MSP1/3 Tx/Rx usage protection */
> > +static DEFINE_SPINLOCK(msp_rxtx_lock);
> > +
> > +/* Pin modes */
> > +struct pinctrl *pinctrl_p;
> > +struct pinctrl_state *pinctrl_def;
> > +struct pinctrl_state *pinctrl_sleep;
> > +
> > +/* Reference Count */
> > +int pinctrl_rxtx_ref;
> 
> 
> But wait. These are just local statics. Surelty you can put these into
> struct ux500_msp instead? Here it looks like these will be used for
> all ports, so MSP2 will enable the pins requested by MSP1 etc
> completely broken. So put it into the struct ux500_msp state
> container from ux500_msp_i2s.h where it belongs.
> 
> Refer to drivers/tty/serial/amba-pl011.c when in trouble. This
> one is a good pinctrl example.

How do you see the MSP1 and MSP3 usage protection working if I hide it
all away in MSP specific structs?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From sourav.poddar at ti.com  Mon Aug 20 08:10:29 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Mon, 20 Aug 2012 17:40:29 +0530
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>

Hi All,

On Tue, Aug 14, 2012 at 9:54 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
> The following patch series add i2c support for omap5.
> As well as enable I2C based devices like pressure and temperature
> through device tree. Also add onchip keypad dts data.
>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> Sourav Poddar (4):
>   arm/dts: omap5-evm: Add I2C support
>   arm/dts: omap5-evm: Add tmp102 sensor support
>   arm/dts: omap5-evm: Add keypad data
>   arm/dts: omap5-evm: Add bmp085 sensor support
>
> v2->v3
> - Rebased on 3.6-rc1
> - Add comments for tmp102 and bmp085
>  arch/arm/boot/dts/omap5-evm.dts |   32 +++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 72 insertions(+), 0 deletions(-)
>
Any comment on this series?

~Sourav


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 08:10:55 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 13:10:55 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820083640.GH8450@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
Message-ID: <20120820121055.GA26991@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 09:36:43AM +0100, Lee Jones wrote:
> On Tue, Aug 14, 2012 at 12:44:37PM +0200, Linus Walleij wrote:

> > Yes but I think I saw this other patch set from Lee, hitting
> > irqdomain, OF and MFD to actually fix this ... or did I get
> > it wrong?

> No, you're not wrong.

> Historically (in my patches) xb8500_irq_get_virq() was used by drivers
> to obtain a VIRQ when not using Device Tree. Now the MFD core handles
> conversion there is little requirement for it. In fact there are no
> more users for db8500_irq_get_virq() and only one user for 
> ab8500_irq_get_virq() and that's itself. I guess we can rid them and
> call irq_get_mapping() directly instead.

Oh dear.  Unfortunately whoever added this support to the MFD core did
so in such a manner that it's only supported for device tree systems
and only for devices which express the MFD cells as device tree nodes
which means that most devices can't it - db8500 has got a reasonably
unusual combination there.
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From b-cousson at ti.com  Mon Aug 20 08:13:41 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 20 Aug 2012 14:13:41 +0200
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
Message-ID: <503229F5.4030405@ti.com>

On 08/20/2012 02:10 PM, Poddar, Sourav wrote:
> Hi All,
> 
> On Tue, Aug 14, 2012 at 9:54 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>> The following patch series add i2c support for omap5.
>> As well as enable I2C based devices like pressure and temperature
>> through device tree. Also add onchip keypad dts data.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>
>> Sourav Poddar (4):
>>   arm/dts: omap5-evm: Add I2C support
>>   arm/dts: omap5-evm: Add tmp102 sensor support
>>   arm/dts: omap5-evm: Add keypad data
>>   arm/dts: omap5-evm: Add bmp085 sensor support
>>
>> v2->v3
>> - Rebased on 3.6-rc1
>> - Add comments for tmp102 and bmp085
>>  arch/arm/boot/dts/omap5-evm.dts |   32 +++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 72 insertions(+), 0 deletions(-)
>>
> Any comment on this series?

Didn't we mentioned updating the trivial-devices.txt in the
documentation to list these devices?

Otherwise it it fine. You can add the documentation and I'll take these
patches as well along with the others.

Regards,
Benoit


From festevam at gmail.com  Mon Aug 20 08:17:35 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 20 Aug 2012 09:17:35 -0300
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
 <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
Message-ID: <CAOMZO5BoWyGzB3p11yE9NXAXq319oi0bnbFuwxvahCqGDOZKrw@mail.gmail.com>

On 8/20/12, Alan M Butler <alanbutty12 at gmail.com> wrote:

>> orion_gpio_is_valid: invalid GPIO 0
>> orion_gpio_is_valid: invalid GPIO 0
>> gpio-keys gpio-keys.2: \x013INFO: %s in %pS age=%lu cpu=%u pid=%d
>> Failed to request GPIO 0, error -22
>> gpio-keys: probe of gpio-keys.2 failed with error -22

This looks like a different issue.

Regards,

Fabio Estevam


From sourav.poddar at ti.com  Mon Aug 20 08:17:59 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Mon, 20 Aug 2012 17:47:59 +0530
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <503229F5.4030405@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
 <503229F5.4030405@ti.com>
Message-ID: <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>

Hi Benoit,

On Mon, Aug 20, 2012 at 5:43 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> On 08/20/2012 02:10 PM, Poddar, Sourav wrote:
>> Hi All,
>>
>> On Tue, Aug 14, 2012 at 9:54 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>>> The following patch series add i2c support for omap5.
>>> As well as enable I2C based devices like pressure and temperature
>>> through device tree. Also add onchip keypad dts data.
>>>
>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>> Cc: Felipe Balbi <balbi at ti.com>
>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>>
>>> Sourav Poddar (4):
>>>   arm/dts: omap5-evm: Add I2C support
>>>   arm/dts: omap5-evm: Add tmp102 sensor support
>>>   arm/dts: omap5-evm: Add keypad data
>>>   arm/dts: omap5-evm: Add bmp085 sensor support
>>>
>>> v2->v3
>>> - Rebased on 3.6-rc1
>>> - Add comments for tmp102 and bmp085
>>>  arch/arm/boot/dts/omap5-evm.dts |   32 +++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>>>  2 files changed, 72 insertions(+), 0 deletions(-)
>>>
>> Any comment on this series?
>
> Didn't we mentioned updating the trivial-devices.txt in the
> documentation to list these devices?
>
I had posted a patch for updating the Documentation, though I created
a seperate
hwmon/tmp102.txt file. There is a comment to add it to trivial devices. So,
I will post a single patch doing so.

> Otherwise it it fine. You can add the documentation and I'll take these
> patches as well along with the others.
>
> Regards,
> Benoit


From b-cousson at ti.com  Mon Aug 20 08:19:52 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 20 Aug 2012 14:19:52 +0200
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
 <503229F5.4030405@ti.com>
 <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>
Message-ID: <50322B68.8060906@ti.com>

On 08/20/2012 02:17 PM, Poddar, Sourav wrote:
> Hi Benoit,
> 
> On Mon, Aug 20, 2012 at 5:43 PM, Benoit Cousson <b-cousson at ti.com> wrote:
>> On 08/20/2012 02:10 PM, Poddar, Sourav wrote:
>>> Hi All,
>>>
>>> On Tue, Aug 14, 2012 at 9:54 PM, Sourav Poddar <sourav.poddar at ti.com> wrote:
>>>> The following patch series add i2c support for omap5.
>>>> As well as enable I2C based devices like pressure and temperature
>>>> through device tree. Also add onchip keypad dts data.
>>>>
>>>> Cc: Benoit Cousson <b-cousson at ti.com>
>>>> Cc: Felipe Balbi <balbi at ti.com>
>>>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>>>
>>>> Sourav Poddar (4):
>>>>   arm/dts: omap5-evm: Add I2C support
>>>>   arm/dts: omap5-evm: Add tmp102 sensor support
>>>>   arm/dts: omap5-evm: Add keypad data
>>>>   arm/dts: omap5-evm: Add bmp085 sensor support
>>>>
>>>> v2->v3
>>>> - Rebased on 3.6-rc1
>>>> - Add comments for tmp102 and bmp085
>>>>  arch/arm/boot/dts/omap5-evm.dts |   32 +++++++++++++++++++++++++++++++
>>>>  arch/arm/boot/dts/omap5.dtsi    |   40 +++++++++++++++++++++++++++++++++++++++
>>>>  2 files changed, 72 insertions(+), 0 deletions(-)
>>>>
>>> Any comment on this series?
>>
>> Didn't we mentioned updating the trivial-devices.txt in the
>> documentation to list these devices?
>>
> I had posted a patch for updating the Documentation, though I created
> a seperate
> hwmon/tmp102.txt file. There is a comment to add it to trivial devices. So,
> I will post a single patch doing so.

Cool, I'll take it on top of this one then.

Thanks,
Benoit



From fabio.estevam at freescale.com  Mon Aug 20 08:39:22 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 20 Aug 2012 09:39:22 -0300
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
Message-ID: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>

SSI block has two types of clock:

ipg: bus clock, the clock needed for accessing registers.
per: peripheral clock, the clock needed for generating the bit rate.

Currently SSI driver only supports slave mode and only need to handle
the ipg clock, because the peripheral clock comes from the master codec.

Only register the ipg clock and do not register the peripheral clock for ssi.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
Changes since v1:
- Use ssi2_gate for imx-ssi.1

 arch/arm/mach-imx/clk-imx35.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb..f7910df 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -230,10 +230,8 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
-	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
-	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
-	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
-- 
1.7.9.5




From will.deacon at arm.com  Mon Aug 20 08:41:10 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 13:41:10 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
Message-ID: <20120820124109.GK25864@mudshark.cambridge.arm.com>

Hi Nicolas,

[apologies in advance for the long reply]

On Fri, Aug 17, 2012 at 04:43:01AM +0100, Nicolas Pitre wrote:
> On Tue, 14 Aug 2012, Will Deacon wrote:
> 
> > Data aborts taken to hyp mode do not provide a valid instruction
> > syndrome field in the HSR if the faulting instruction is a memory
> > access using a writeback addressing mode.
> > 
> > For hypervisors emulating MMIO accesses to virtual peripherals, taking
> > such an exception requires disassembling the faulting instruction in
> > order to determine the behaviour of the access. Since this requires
> > manually walking the two stages of translation, the world must be
> > stopped to prevent races against page aging in the guest, where the
> > first-stage translation is invalidated after the hypervisor has
> > translated to an IPA and the physical page is reused for something else.
> > 
> > This patch avoids taking this heavy performance penalty when running
> > Linux as a guest by ensuring that our I/O accessors do not make use of
> > writeback addressing modes.
> 
> How often does this happen?  I don't really see writeback as a common 
> pattern for IO access.

Building a Thumb-2 kernel with GCC:

gcc version 4.6.3 20120201 (prerelease) (crosstool-NG
linaro-1.13.1-2012.02-20120222 - Linaro GCC 2012.02)

Translates the following code from amba_device_add:

		for (pid = 0, i = 0; i < 4; i++)
			pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) <<
				(i * 8);
		for (cid = 0, i = 0; i < 4; i++)
			cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
				(i * 8);

into:

c0177bec:       f853 2b04       ldr.w   r2, [r3], #4	<---
c0177bf0:       f3bf 8f4f       dsb     sy
c0177bf4:       b2d2            uxtb    r2, r2
c0177bf6:       40a2            lsls    r2, r4
c0177bf8:       3408            adds    r4, #8
c0177bfa:       2c20            cmp     r4, #32
c0177bfc:       ea45 0502       orr.w   r5, r5, r2
c0177c00:       d1f4            bne.n   c0177bec <amba_device_add+0x94>
c0177c02:       f1a8 0810       sub.w   r8, r8, #16
c0177c06:       2300            movs    r3, #0
c0177c08:       44c8            add     r8, r9
c0177c0a:       461c            mov     r4, r3
c0177c0c:       f858 2b04       ldr.w   r2, [r8], #4	<---
c0177c10:       f3bf 8f4f       dsb     sy
c0177c14:       b2d2            uxtb    r2, r2
c0177c16:       409a            lsls    r2, r3
c0177c18:       3308            adds    r3, #8
c0177c1a:       2b20            cmp     r3, #32
c0177c1c:       ea44 0402       orr.w   r4, r4, r2
c0177c20:       d1f4            bne.n   c0177c0c <amba_device_add+0xb4>

so this is happening with recent toolchains and current kernel sources.

> What does happen quite a lot, though, is pre-indexed addressing.  For 
> example, let's take this code which is fairly typical of driver code:
> 
> #define HW_REG1		0x10
> #define HW_REG2		0x14
> #define HW_REG3		0x18
> #define HW_REG4		0x30
> 
> int hw_init(void __iomem *ioaddr)
> {
> 	writel(0, ioaddr + HW_REG1)
> 	writel(-1, ioaddr + HW_REG2);
> 	writel(readl(ioaddr + HW_REG3) | 0xff, ioaddr + HW_REG4);
> 	return 0;
> }
> 
> Right now this produces this:
> 
> hw_init:
>         mov     r3, r0
>         mvn     r2, #0
>         mov     r0, #0
>         str     r0, [r3, #16]
>         str     r2, [r3, #20]
>         ldr     r2, [r3, #24]
>         orr     r2, r2, #255
>         str     r2, [r3, #48]
>         bx      lr

Well, that's not quite true for CONFIG_ARM_DMA_MEM_BUFFERABLE=y. The dsb and
compiler barrier ends up creating this monster for that code:

00000280 <hw_init>:
 280:   4603            mov     r3, r0
 282:   f3bf 8f4f       dsb     sy
 286:   2000            movs    r0, #0
 288:   6118            str     r0, [r3, #16]
 28a:   f3bf 8f4f       dsb     sy
 28e:   f04f 32ff       mov.w   r2, #4294967295
 292:   615a            str     r2, [r3, #20]
 294:   f3bf 8f4f       dsb     sy
 298:   699a            ldr     r2, [r3, #24]
 29a:   f3bf 8f4f       dsb     sy
 29e:   f042 02ff       orr.w   r2, r2, #255    ; 0xff
 2a2:   631a            str     r2, [r3, #48]   ; 0x30
 2a4:   4770            bx      lr
 2a6:   bf00            nop

whilst the addressing modes are still nice, the dsb is going to be the
performance limitation here. That said, we could try the "Qo" constraints,
which I seem to remember don't generate writebacks. I'll have a play.

> So, is the performance claim something that you've actually measured 
> with a real system, or was it only theoretical?

The difference is down to the work done by the hypvervisor: an MMIO access
will trap to hyp mode, where the HSR describes the instruction (access size,
load/store, Rt, signed etc). For the case of a writeback instruction, this
information is not provided by the hardware. Instead, the hypervisor has to
disassemble the faulting instruction and work out what it's doing at which
address prior to emulation.

Even if that cost was acceptable, the problem then gets worse. Imagine that
a guest MMIO access faults into the hypervisor, where the emulation code
tries to decode the instruction because the fault information is incomplete.
To do this, it must obtain the *physical* address of the faulting text page
so that it can load the instruction. This happens via the ATS12NSOP{R,W}
registers, which return a PA for the faulting VA (i.e. both stages of
translation).

Now, let's say the hypervisor has got hold of a PA but hasn't yet loaded the
instruction. Meanwhile, another virtual CPU running the same guest decides
(due to page aging or whatnot) to reclaim the text page containing the
faulting instruction. It writes a faulting pte and does a TLB invalidation,
however this is too late for the hypervisor, who has already translated its
address. Furthermore, let's say that the guest then reuses the same physical
page for something like a network buffer. The hypervisor goes ahead and grabs
what it thinks is the faulting instruction from memory but in fact gets a
load of random network data!

To deal with this, the hypervisor will likely have to stop the virtual world
when emulating any MMIO accesses that report incomplete fault information to
avoid racing with a TLB invalidation from another virtual CPU. That will
certainly be more expensive than an additional instruction on each access.
To answer your question: I haven't measured it (largely because KVM can't
pull apart Thumb-2 instructions yet).

I believe that the KVM guys were planning to print a diagnostic prior to
emulation/world-stop if the fault information is incomplete, complaining that
the guest is using writeback addressing modes for I/O.

Cheers,

Will


From alanbutty12 at gmail.com  Mon Aug 20 08:44:56 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 13:44:56 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CAOMZO5BbdT2CXHh4NEt8bPZ4C7Mg=Yd9C9E7J2H_JsGJ=88fqQ@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
 <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
 <CAOMZO5BoWyGzB3p11yE9NXAXq319oi0bnbFuwxvahCqGDOZKrw@mail.gmail.com>
 <CADhrpJ487cN23gRkws1Grp+SEmrKO2JdDT0r-DVeCZm-XqdP=A@mail.gmail.com>
 <CAOMZO5BbdT2CXHh4NEt8bPZ4C7Mg=Yd9C9E7J2H_JsGJ=88fqQ@mail.gmail.com>
Message-ID: <CADhrpJ7Fq0FktNN-54++39=SN_GrkX7gpse+2QfD7ioQw+_cEA@mail.gmail.com>

On 20 August 2012 13:36, Fabio Estevam <festevam at gmail.com> wrote:
> On Mon, Aug 20, 2012 at 9:30 AM, Alan M Butler <alanbutty12 at gmail.com> wrote:
>
>> im not sure but i only get that after applying the patch you sent me
>> on the linux next from the 17th.
>> i will try building a new linux-next later today and will send you what happens.
>
> Please do not drop the list from Cc.
>
>> would it be because i named the buttons power, reset and otb? instead
>> of button at 1 and so on like the other kirkwood devices?
>
> I am not familiar with kirkwood device, sorry.

sorry i forgot to cc the list.

But as far as i can tell with the buttons the only difference between
my device and the other's like the iconnect is that they named the
buttons button at 1 and i named mine Power, Reset and OTB. Is it possible
the capital letters are causing the problem?


From will.deacon at arm.com  Mon Aug 20 08:51:16 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 13:51:16 +0100
Subject: [PATCH 0/3] New algorithm for ASID allocation and rollover
In-Reply-To: <201208191521.37460.arnd@arndb.de>
References: <1345049642-29704-1-git-send-email-will.deacon@arm.com>
 <201208191521.37460.arnd@arndb.de>
Message-ID: <20120820125116.GM25864@mudshark.cambridge.arm.com>

Hi Arnd,

Thanks for the interest!

On Sun, Aug 19, 2012 at 04:21:37PM +0100, Arnd Bergmann wrote:
> On Wednesday 15 August 2012, Will Deacon wrote:
> > After some discussion, it became apparent that tracking the ASIDs
> > currently active on the cores in the system means that, on rollover, we
> > can automatically reserve those that are in use without having to stop
> > the world.
> 
> Just a question for my general understanding of how this is done: How do
> you know if an ASID is active or not? Do you broadcast flush an address
> space completely when the struct mm goes away, or do you keep track of
> which CPUs had TLBs in an ASIC when it went away and then flush that ASID
> when you reuse it on that CPU?

Ok, I'll address these in turn:

1. We know if an ASID is active or not by updating the per-cpu active_asids
   variable when switching mm.

2. Flushing (TLB invalidation) only happens when all ASIDs are dirty. So
   when a struct mm is freed, its ASID remains `dirty' in the asid_map.
   Eventually, no more ASIDs can be allocated, so the flushing takes place
   then. All v7 CPUs broadcast this operation in hardware. At this point, we
   mark all the active ASIDs as dirty to prevent them being re-allocated to
   different tasks.

I did play with per-ASID TLB-flushing depending on ASID pressure but I
couldn't find any benchmarks that showed an improvement.

Cheers,

Will


From robherring2 at gmail.com  Mon Aug 20 08:51:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 20 Aug 2012 07:51:44 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <503232E0.3000007@gmail.com>

On 08/16/2012 03:08 AM, Shawn Guo wrote:
> It really becomes an issue that every time a device needs to look
> up (clk_get) a clock we have to patch kernel clock file to call
> clk_register_clkdev for that clock.
> 
> Since clock DT support which is meant to resolve clock lookup in device
> tree is in place, the patch moves imx6q client devices' clock lookup
> over to device tree, so that any new lookup to be added at later time
> can just get done in DT instead of kernel.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Looks good. For both patches:

Reviewed-by: Rob Herring <rob.herring at calxeda.com>

> ---
>  .../devicetree/bindings/clock/imx6q-clock.txt      |  223 +++++++++++++++++
>  arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
>  arch/arm/boot/dts/imx6q.dtsi                       |  261 +++++++++++++++++++-
>  arch/arm/mach-imx/clk-imx6q.c                      |   41 +---
>  arch/arm/mach-imx/mach-imx6q.c                     |    1 -
>  5 files changed, 477 insertions(+), 50 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> new file mode 100644
> index 0000000..19d8126
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
> @@ -0,0 +1,223 @@
> +* Clock bindings for Freescale i.MX6 Quad
> +
> +Required properties:
> +- compatible: Should be "fsl,imx6q-ccm"
> +- reg: Address and length of the register set
> +- interrupts: Should contain CCM interrupt
> +- #clock-cells: Should be <1>
> +- clock-output-names: A list of clock output names that CCM provides.
> +  The full list of all valid clock names and IDs is below.
> +
> +	Name			ID
> +	---------------------------
> +	dummy			0
> +	ckil			1
> +	ckih			2
> +	osc			3
> +	pll2_pfd0_352m		4
> +	pll2_pfd1_594m		5
> +	pll2_pfd2_396m		6
> +	pll3_pfd0_720m		7
> +	pll3_pfd1_540m		8
> +	pll3_pfd2_508m		9
> +	pll3_pfd3_454m		10
> +	pll2_198m		11
> +	pll3_120m		12
> +	pll3_80m		13
> +	pll3_60m		14
> +	twd			15
> +	step			16
> +	pll1_sw			17
> +	periph_pre		18
> +	periph2_pre		19
> +	periph_clk2_sel		20
> +	periph2_clk2_sel	21
> +	axi_sel			22
> +	esai_sel		23
> +	asrc_sel		24
> +	spdif_sel		25
> +	gpu2d_axi		26
> +	gpu3d_axi		27
> +	gpu2d_core_sel		28
> +	gpu3d_core_sel		29
> +	gpu3d_shader_sel	30
> +	ipu1_sel		31
> +	ipu2_sel		32
> +	ldb_di0_sel		33
> +	ldb_di1_sel		34
> +	ipu1_di0_pre_sel	35
> +	ipu1_di1_pre_sel	36
> +	ipu2_di0_pre_sel	37
> +	ipu2_di1_pre_sel	38
> +	ipu1_di0_sel		39
> +	ipu1_di1_sel		40
> +	ipu2_di0_sel		41
> +	ipu2_di1_sel		42
> +	hsi_tx_sel		43
> +	pcie_axi_sel		44
> +	ssi1_sel		45
> +	ssi2_sel		46
> +	ssi3_sel		47
> +	usdhc1_sel		48
> +	usdhc2_sel		49
> +	usdhc3_sel		50
> +	usdhc4_sel		51
> +	enfc_sel		52
> +	emi_sel			53
> +	emi_slow_sel		54
> +	vdo_axi_sel		55
> +	vpu_axi_sel		56
> +	cko1_sel		57
> +	periph			58
> +	periph2			59
> +	periph_clk2		60
> +	periph2_clk2		61
> +	ipg			62
> +	ipg_per			63
> +	esai_pred		64
> +	esai_podf		65
> +	asrc_pred		66
> +	asrc_podf		67
> +	spdif_pred		68
> +	spdif_podf		69
> +	can_root		70
> +	ecspi_root		71
> +	gpu2d_core_podf		72
> +	gpu3d_core_podf		73
> +	gpu3d_shader		74
> +	ipu1_podf		75
> +	ipu2_podf		76
> +	ldb_di0_podf		77
> +	ldb_di1_podf		78
> +	ipu1_di0_pre		79
> +	ipu1_di1_pre		80
> +	ipu2_di0_pre		81
> +	ipu2_di1_pre		82
> +	hsi_tx_podf		83
> +	ssi1_pred		84
> +	ssi1_podf		85
> +	ssi2_pred		86
> +	ssi2_podf		87
> +	ssi3_pred		88
> +	ssi3_podf		89
> +	uart_serial_podf	90
> +	usdhc1_podf		91
> +	usdhc2_podf		92
> +	usdhc3_podf		93
> +	usdhc4_podf		94
> +	enfc_pred		95
> +	enfc_podf		96
> +	emi_podf		97
> +	emi_slow_podf		98
> +	vpu_axi_podf		99
> +	cko1_podf		100
> +	axi			101
> +	mmdc_ch0_axi_podf	102
> +	mmdc_ch1_axi_podf	103
> +	arm			104
> +	ahb			105
> +	apbh_dma		106
> +	asrc			107
> +	can1_ipg		108
> +	can1_serial		109
> +	can2_ipg		110
> +	can2_serial		111
> +	ecspi1			112
> +	ecspi2			113
> +	ecspi3			114
> +	ecspi4			115
> +	ecspi5			116
> +	enet			117
> +	esai			118
> +	gpt_ipg			119
> +	gpt_ipg_per		120
> +	gpu2d_core		121
> +	gpu3d_core		122
> +	hdmi_iahb		123
> +	hdmi_isfr		124
> +	i2c1			125
> +	i2c2			126
> +	i2c3			127
> +	iim			128
> +	enfc			129
> +	ipu1			130
> +	ipu1_di0		131
> +	ipu1_di1		132
> +	ipu2			133
> +	ipu2_di0		134
> +	ldb_di0			135
> +	ldb_di1			136
> +	ipu2_di1		137
> +	hsi_tx			138
> +	mlb			139
> +	mmdc_ch0_axi		140
> +	mmdc_ch1_axi		141
> +	ocram			142
> +	openvg_axi		143
> +	pcie_axi		144
> +	pwm1			145
> +	pwm2			146
> +	pwm3			147
> +	pwm4			148
> +	per1_bch		149
> +	gpmi_bch_apb		150
> +	gpmi_bch		151
> +	gpmi_io			152
> +	gpmi_apb		153
> +	sata			154
> +	sdma			155
> +	spba			156
> +	ssi1			157
> +	ssi2			158
> +	ssi3			159
> +	uart_ipg		160
> +	uart_serial		161
> +	usboh3			162
> +	usdhc1			163
> +	usdhc2			164
> +	usdhc3			165
> +	usdhc4			166
> +	vdo_axi			167
> +	vpu_axi			168
> +	cko1			169
> +	pll1_sys		170
> +	pll2_bus		171
> +	pll3_usb_otg		172
> +	pll4_audio		173
> +	pll5_video		174
> +	pll6_mlb		175
> +	pll7_usb_host		176
> +	pll8_enet		177
> +	ssi1_ipg		178
> +	ssi2_ipg		179
> +	ssi3_ipg		180
> +	rom			181
> +	usbphy1			182
> +	usbphy2			183
> +	ldb_di0_div_3_5		184
> +	ldb_di1_div_3_5		185
> +
> +  The ID will be used by clock consumer in the first cell of "clocks"
> +  phandle to specify the desired clock.
> +
> +Examples:
> +
> +clks: ccm at 020c4000 {
> +	compatible = "fsl,imx6q-ccm";
> +	reg = <0x020c4000 0x4000>;
> +	interrupts = <0 87 0x04 0 88 0x04>;
> +	#clock-cells = <1>;
> +	clock-output-names = ...
> +			     "uart_ipg",
> +			     "uart_serial",
> +			     ...;
> +};
> +
> +uart1: serial at 02020000 {
> +	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
> +	reg = <0x02020000 0x4000>;
> +	interrupts = <0 26 0x04>;
> +	clocks = <&clks 160>, <&clks 161>;
> +	clock-names = "ipg", "per";
> +	status = "disabled";
> +};
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index 72f30f3..cfdbe53 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -111,6 +111,7 @@
>  				codec: sgtl5000 at 0a {
>  					compatible = "fsl,sgtl5000";
>  					reg = <0x0a>;
> +					clocks = <&clks 169>;
>  					VDDA-supply = <&reg_2p5v>;
>  					VDDIO-supply = <&reg_3p3v>;
>  				};
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 0052fe7..acff2dc 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -93,18 +93,23 @@
>  		dma-apbh at 00110000 {
>  			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
>  			reg = <0x00110000 0x2000>;
> +			clocks = <&clks 106>;
>  		};
>  
>  		gpmi-nand at 00112000 {
> -		       compatible = "fsl,imx6q-gpmi-nand";
> -		       #address-cells = <1>;
> -		       #size-cells = <1>;
> -		       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
> -		       reg-names = "gpmi-nand", "bch";
> -		       interrupts = <0 13 0x04>, <0 15 0x04>;
> -		       interrupt-names = "gpmi-dma", "bch";
> -		       fsl,gpmi-dma-channel = <0>;
> -		       status = "disabled";
> +			compatible = "fsl,imx6q-gpmi-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
> +			reg-names = "gpmi-nand", "bch";
> +			interrupts = <0 13 0x04>, <0 15 0x04>;
> +			interrupt-names = "gpmi-dma", "bch";
> +			clocks = <&clks 152>, <&clks 153>, <&clks 151>,
> +				 <&clks 150>, <&clks 149>;
> +			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
> +				      "gpmi_bch_apb", "per1_bch";
> +			fsl,gpmi-dma-channel = <0>;
> +			status = "disabled";
>  		};
>  
>  		timer at 00a00600 {
> @@ -146,6 +151,8 @@
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>  					reg = <0x02008000 0x4000>;
>  					interrupts = <0 31 0x04>;
> +					clocks = <&clks 112>, <&clks 112>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -155,6 +162,8 @@
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>  					reg = <0x0200c000 0x4000>;
>  					interrupts = <0 32 0x04>;
> +					clocks = <&clks 113>, <&clks 113>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -164,6 +173,8 @@
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>  					reg = <0x02010000 0x4000>;
>  					interrupts = <0 33 0x04>;
> +					clocks = <&clks 114>, <&clks 114>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -173,6 +184,8 @@
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>  					reg = <0x02014000 0x4000>;
>  					interrupts = <0 34 0x04>;
> +					clocks = <&clks 115>, <&clks 115>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -182,6 +195,8 @@
>  					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>  					reg = <0x02018000 0x4000>;
>  					interrupts = <0 35 0x04>;
> +					clocks = <&clks 116>, <&clks 116>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -189,6 +204,8 @@
>  					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  					reg = <0x02020000 0x4000>;
>  					interrupts = <0 26 0x04>;
> +					clocks = <&clks 160>, <&clks 161>;
> +					clock-names = "ipg", "per";
>  					status = "disabled";
>  				};
>  
> @@ -201,6 +218,7 @@
>  					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>  					reg = <0x02028000 0x4000>;
>  					interrupts = <0 46 0x04>;
> +					clocks = <&clks 178>;
>  					fsl,fifo-depth = <15>;
>  					fsl,ssi-dma-events = <38 37>;
>  					status = "disabled";
> @@ -210,6 +228,7 @@
>  					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>  					reg = <0x0202c000 0x4000>;
>  					interrupts = <0 47 0x04>;
> +					clocks = <&clks 179>;
>  					fsl,fifo-depth = <15>;
>  					fsl,ssi-dma-events = <42 41>;
>  					status = "disabled";
> @@ -219,6 +238,7 @@
>  					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>  					reg = <0x02030000 0x4000>;
>  					interrupts = <0 48 0x04>;
> +					clocks = <&clks 180>;
>  					fsl,fifo-depth = <15>;
>  					fsl,ssi-dma-events = <46 45>;
>  					status = "disabled";
> @@ -358,6 +378,7 @@
>  				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>  				reg = <0x020bc000 0x4000>;
>  				interrupts = <0 80 0x04>;
> +				clocks = <&clks 0>;
>  				status = "disabled";
>  			};
>  
> @@ -365,13 +386,203 @@
>  				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>  				reg = <0x020c0000 0x4000>;
>  				interrupts = <0 81 0x04>;
> +				clocks = <&clks 0>;
>  				status = "disabled";
>  			};
>  
> -			ccm at 020c4000 {
> +			clks: ccm at 020c4000 {
>  				compatible = "fsl,imx6q-ccm";
>  				reg = <0x020c4000 0x4000>;
>  				interrupts = <0 87 0x04 0 88 0x04>;
> +				#clock-cells = <1>;
> +				clock-output-names =
> +					"dummy",		/* 0 */
> +					"ckil",			/* 1 */
> +					"ckih",			/* 2 */
> +					"osc",			/* 3 */
> +					"pll2_pfd0_352m",	/* 4 */
> +					"pll2_pfd1_594m",	/* 5 */
> +					"pll2_pfd2_396m",	/* 6 */
> +					"pll3_pfd0_720m",	/* 7 */
> +					"pll3_pfd1_540m",	/* 8 */
> +					"pll3_pfd2_508m",	/* 9 */
> +					"pll3_pfd3_454m",	/* 10 */
> +					"pll2_198m",		/* 11 */
> +					"pll3_120m",		/* 12 */
> +					"pll3_80m",		/* 13 */
> +					"pll3_60m",		/* 14 */
> +					"twd",			/* 15 */
> +					"step",			/* 16 */
> +					"pll1_sw",		/* 17 */
> +					"periph_pre",		/* 18 */
> +					"periph2_pre",		/* 19 */
> +					"periph_clk2_sel",	/* 20 */
> +					"periph2_clk2_sel",	/* 21 */
> +					"axi_sel",		/* 22 */
> +					"esai_sel",		/* 23 */
> +					"asrc_sel",		/* 24 */
> +					"spdif_sel",		/* 25 */
> +					"gpu2d_axi",		/* 26 */
> +					"gpu3d_axi",		/* 27 */
> +					"gpu2d_core_sel",	/* 28 */
> +					"gpu3d_core_sel",	/* 29 */
> +					"gpu3d_shader_sel",	/* 30 */
> +					"ipu1_sel",		/* 31 */
> +					"ipu2_sel",		/* 32 */
> +					"ldb_di0_sel",		/* 33 */
> +					"ldb_di1_sel",		/* 34 */
> +					"ipu1_di0_pre_sel",	/* 35 */
> +					"ipu1_di1_pre_sel",	/* 36 */
> +					"ipu2_di0_pre_sel",	/* 37 */
> +					"ipu2_di1_pre_sel",	/* 38 */
> +					"ipu1_di0_sel",		/* 39 */
> +					"ipu1_di1_sel",		/* 40 */
> +					"ipu2_di0_sel",		/* 41 */
> +					"ipu2_di1_sel",		/* 42 */
> +					"hsi_tx_sel",		/* 43 */
> +					"pcie_axi_sel",		/* 44 */
> +					"ssi1_sel",		/* 45 */
> +					"ssi2_sel",		/* 46 */
> +					"ssi3_sel",		/* 47 */
> +					"usdhc1_sel",		/* 48 */
> +					"usdhc2_sel",		/* 49 */
> +					"usdhc3_sel",		/* 50 */
> +					"usdhc4_sel",		/* 51 */
> +					"enfc_sel",		/* 52 */
> +					"emi_sel",		/* 53 */
> +					"emi_slow_sel",		/* 54 */
> +					"vdo_axi_sel",		/* 55 */
> +					"vpu_axi_sel",		/* 56 */
> +					"cko1_sel",		/* 57 */
> +					"periph",		/* 58 */
> +					"periph2",		/* 59 */
> +					"periph_clk2",		/* 60 */
> +					"periph2_clk2",		/* 61 */
> +					"ipg",			/* 62 */
> +					"ipg_per",		/* 63 */
> +					"esai_pred",		/* 64 */
> +					"esai_podf",		/* 65 */
> +					"asrc_pred",		/* 66 */
> +					"asrc_podf",		/* 67 */
> +					"spdif_pred",		/* 68 */
> +					"spdif_podf",		/* 69 */
> +					"can_root",		/* 70 */
> +					"ecspi_root",		/* 71 */
> +					"gpu2d_core_podf",	/* 72 */
> +					"gpu3d_core_podf",	/* 73 */
> +					"gpu3d_shader",		/* 74 */
> +					"ipu1_podf",		/* 75 */
> +					"ipu2_podf",		/* 76 */
> +					"ldb_di0_podf",		/* 77 */
> +					"ldb_di1_podf",		/* 78 */
> +					"ipu1_di0_pre",		/* 79 */
> +					"ipu1_di1_pre",		/* 80 */
> +					"ipu2_di0_pre",		/* 81 */
> +					"ipu2_di1_pre",		/* 82 */
> +					"hsi_tx_podf",		/* 83 */
> +					"ssi1_pred",		/* 84 */
> +					"ssi1_podf",		/* 85 */
> +					"ssi2_pred",		/* 86 */
> +					"ssi2_podf",		/* 87 */
> +					"ssi3_pred",		/* 88 */
> +					"ssi3_podf",		/* 89 */
> +					"uart_serial_podf",	/* 90 */
> +					"usdhc1_podf",		/* 91 */
> +					"usdhc2_podf",		/* 92 */
> +					"usdhc3_podf",		/* 93 */
> +					"usdhc4_podf",		/* 94 */
> +					"enfc_pred",		/* 95 */
> +					"enfc_podf",		/* 96 */
> +					"emi_podf",		/* 97 */
> +					"emi_slow_podf",	/* 98 */
> +					"vpu_axi_podf",		/* 99 */
> +					"cko1_podf",		/* 100 */
> +					"axi",			/* 101 */
> +					"mmdc_ch0_axi_podf",	/* 102 */
> +					"mmdc_ch1_axi_podf",	/* 103 */
> +					"arm",			/* 104 */
> +					"ahb",			/* 105 */
> +					"apbh_dma",		/* 106 */
> +					"asrc",			/* 107 */
> +					"can1_ipg",		/* 108 */
> +					"can1_serial",		/* 109 */
> +					"can2_ipg",		/* 110 */
> +					"can2_serial",		/* 111 */
> +					"ecspi1",		/* 112 */
> +					"ecspi2",		/* 113 */
> +					"ecspi3",		/* 114 */
> +					"ecspi4",		/* 115 */
> +					"ecspi5",		/* 116 */
> +					"enet",			/* 117 */
> +					"esai",			/* 118 */
> +					"gpt_ipg",		/* 119 */
> +					"gpt_ipg_per",		/* 120 */
> +					"gpu2d_core",		/* 121 */
> +					"gpu3d_core",		/* 122 */
> +					"hdmi_iahb",		/* 123 */
> +					"hdmi_isfr",		/* 124 */
> +					"i2c1",			/* 125 */
> +					"i2c2",			/* 126 */
> +					"i2c3",			/* 127 */
> +					"iim",			/* 128 */
> +					"enfc",			/* 129 */
> +					"ipu1",			/* 130 */
> +					"ipu1_di0",		/* 131 */
> +					"ipu1_di1",		/* 132 */
> +					"ipu2",			/* 133 */
> +					"ipu2_di0",		/* 134 */
> +					"ldb_di0",		/* 135 */
> +					"ldb_di1",		/* 136 */
> +					"ipu2_di1",		/* 137 */
> +					"hsi_tx",		/* 138 */
> +					"mlb",			/* 139 */
> +					"mmdc_ch0_axi",		/* 140 */
> +					"mmdc_ch1_axi",		/* 141 */
> +					"ocram",		/* 142 */
> +					"openvg_axi",		/* 143 */
> +					"pcie_axi",		/* 144 */
> +					"pwm1",			/* 145 */
> +					"pwm2",			/* 146 */
> +					"pwm3",			/* 147 */
> +					"pwm4",			/* 148 */
> +					"per1_bch",		/* 149 */
> +					"gpmi_bch_apb",		/* 150 */
> +					"gpmi_bch",		/* 151 */
> +					"gpmi_io",		/* 152 */
> +					"gpmi_apb",		/* 153 */
> +					"sata",			/* 154 */
> +					"sdma",			/* 155 */
> +					"spba",			/* 156 */
> +					"ssi1",			/* 157 */
> +					"ssi2",			/* 158 */
> +					"ssi3",			/* 159 */
> +					"uart_ipg",		/* 160 */
> +					"uart_serial",		/* 161 */
> +					"usboh3",		/* 162 */
> +					"usdhc1",		/* 163 */
> +					"usdhc2",		/* 164 */
> +					"usdhc3",		/* 165 */
> +					"usdhc4",		/* 166 */
> +					"vdo_axi",		/* 167 */
> +					"vpu_axi",		/* 168 */
> +					"cko1",			/* 169 */
> +					"pll1_sys",		/* 170 */
> +					"pll2_bus",		/* 171 */
> +					"pll3_usb_otg",		/* 172 */
> +					"pll4_audio",		/* 173 */
> +					"pll5_video",		/* 174 */
> +					"pll6_mlb",		/* 175 */
> +					"pll7_usb_host",	/* 176 */
> +					"pll8_enet",		/* 177 */
> +					"ssi1_ipg",		/* 178 */
> +					"ssi2_ipg",		/* 179 */
> +					"ssi3_ipg",		/* 180 */
> +					"rom",			/* 181 */
> +					"usbphy1",		/* 182 */
> +					"usbphy2",		/* 183 */
> +					"ldb_di0_div_3_5",	/* 184 */
> +					"ldb_di1_div_3_5",	/* 185 */
> +					"end_of_list";
>  			};
>  
>  			anatop at 020c8000 {
> @@ -468,12 +679,14 @@
>  				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>  				reg = <0x020c9000 0x1000>;
>  				interrupts = <0 44 0x04>;
> +				clocks = <&clks 182>;
>  			};
>  
>  			usbphy2: usbphy at 020ca000 {
>  				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>  				reg = <0x020ca000 0x1000>;
>  				interrupts = <0 45 0x04>;
> +				clocks = <&clks 183>;
>  			};
>  
>  			snvs at 020cc000 {
> @@ -608,6 +821,9 @@
>  				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
>  				reg = <0x020ec000 0x4000>;
>  				interrupts = <0 2 0x04>;
> +				clocks = <&clks 155>, <&clks 155>;
> +				clock-names = "ipg", "ahb";
> +				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
>  			};
>  		};
>  
> @@ -631,6 +847,7 @@
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184000 0x200>;
>  				interrupts = <0 43 0x04>;
> +				clocks = <&clks 162>;
>  				fsl,usbphy = <&usbphy1>;
>  				status = "disabled";
>  			};
> @@ -639,6 +856,7 @@
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184200 0x200>;
>  				interrupts = <0 40 0x04>;
> +				clocks = <&clks 162>;
>  				fsl,usbphy = <&usbphy2>;
>  				status = "disabled";
>  			};
> @@ -647,6 +865,7 @@
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184400 0x200>;
>  				interrupts = <0 41 0x04>;
> +				clocks = <&clks 162>;
>  				status = "disabled";
>  			};
>  
> @@ -654,6 +873,7 @@
>  				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>  				reg = <0x02184600 0x200>;
>  				interrupts = <0 42 0x04>;
> +				clocks = <&clks 162>;
>  				status = "disabled";
>  			};
>  
> @@ -661,6 +881,8 @@
>  				compatible = "fsl,imx6q-fec";
>  				reg = <0x02188000 0x4000>;
>  				interrupts = <0 118 0x04 0 119 0x04>;
> +				clocks = <&clks 117>, <&clks 117>;
> +				clock-names = "ipg", "ahb";
>  				status = "disabled";
>  			};
>  
> @@ -673,6 +895,8 @@
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02190000 0x4000>;
>  				interrupts = <0 22 0x04>;
> +				clocks = <&clks 163>, <&clks 163>, <&clks 163>;
> +				clock-names = "ipg", "ahb", "per";
>  				status = "disabled";
>  			};
>  
> @@ -680,6 +904,8 @@
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02194000 0x4000>;
>  				interrupts = <0 23 0x04>;
> +				clocks = <&clks 164>, <&clks 164>, <&clks 164>;
> +				clock-names = "ipg", "ahb", "per";
>  				status = "disabled";
>  			};
>  
> @@ -687,6 +913,8 @@
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x02198000 0x4000>;
>  				interrupts = <0 24 0x04>;
> +				clocks = <&clks 165>, <&clks 165>, <&clks 165>;
> +				clock-names = "ipg", "ahb", "per";
>  				status = "disabled";
>  			};
>  
> @@ -694,6 +922,8 @@
>  				compatible = "fsl,imx6q-usdhc";
>  				reg = <0x0219c000 0x4000>;
>  				interrupts = <0 25 0x04>;
> +				clocks = <&clks 166>, <&clks 166>, <&clks 166>;
> +				clock-names = "ipg", "ahb", "per";
>  				status = "disabled";
>  			};
>  
> @@ -703,6 +933,7 @@
>  				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>  				reg = <0x021a0000 0x4000>;
>  				interrupts = <0 36 0x04>;
> +				clocks = <&clks 125>;
>  				status = "disabled";
>  			};
>  
> @@ -712,6 +943,7 @@
>  				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>  				reg = <0x021a4000 0x4000>;
>  				interrupts = <0 37 0x04>;
> +				clocks = <&clks 126>;
>  				status = "disabled";
>  			};
>  
> @@ -721,6 +953,7 @@
>  				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>  				reg = <0x021a8000 0x4000>;
>  				interrupts = <0 38 0x04>;
> +				clocks = <&clks 127>;
>  				status = "disabled";
>  			};
>  
> @@ -784,6 +1017,8 @@
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021e8000 0x4000>;
>  				interrupts = <0 27 0x04>;
> +				clocks = <&clks 160>, <&clks 161>;
> +				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
>  
> @@ -791,6 +1026,8 @@
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021ec000 0x4000>;
>  				interrupts = <0 28 0x04>;
> +				clocks = <&clks 160>, <&clks 161>;
> +				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
>  
> @@ -798,6 +1035,8 @@
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021f0000 0x4000>;
>  				interrupts = <0 29 0x04>;
> +				clocks = <&clks 160>, <&clks 161>;
> +				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
>  
> @@ -805,6 +1044,8 @@
>  				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>  				reg = <0x021f4000 0x4000>;
>  				interrupts = <0 30 0x04>;
> +				clocks = <&clks 160>, <&clks 161>;
> +				clock-names = "ipg", "per";
>  				status = "disabled";
>  			};
>  		};
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 8e46407..433c683 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -387,48 +387,11 @@ int __init mx6q_clocks_init(void)
>  			pr_err("i.MX6q clk %d: register failed with %ld\n",
>  				i, PTR_ERR(clk[i]));
>  
> +	of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
> +
>  	clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
>  	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
>  	clk_register_clkdev(clk[twd], NULL, "smp_twd");
> -	clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
> -	clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
> -	clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
> -	clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
> -	clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
> -	clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
> -	clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
> -	clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
> -	clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
> -	clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
> -	clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
> -	clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
> -	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
> -	clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
> -	clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
> -	clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
> -	clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
> -	clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
> -	clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
> -	clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
> -	clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
> -	clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
> -	clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
> -	clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
> -	clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
> -	clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
> -	clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
> -	clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
> -	clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
> -	clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
> -	clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
> -	clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
> -	clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
> -	clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
> -	clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
> -	clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
> -	clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
> -	clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
> -	clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
>  	clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
>  	clk_register_clkdev(clk[ahb], "ahb", NULL);
>  	clk_register_clkdev(clk[cko1], "cko1", NULL);
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 6f9c23b..957f5fe 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -94,7 +94,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
>  	clk_set_parent(cko1_sel, ahb);
>  	rate = clk_round_rate(cko1, 16000000);
>  	clk_set_rate(cko1, rate);
> -	clk_register_clkdev(cko1, NULL, "0-000a");
>  put_clk:
>  	if (!IS_ERR(cko1_sel))
>  		clk_put(cko1_sel);
> 



From thomas.petazzoni at free-electrons.com  Mon Aug 20 08:51:48 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 Aug 2012 14:51:48 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
 <CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>
Message-ID: <20120820145148.47a69ba4@skate>

Hello,

Le Mon, 20 Aug 2012 11:46:14 +0200,
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :

> >> +uart1: serial at 12100 {
> >> +       compatible = "ns16550a";
> >> +       reg = <0x12100 0x100>;
> >> +       reg-shift = <2>;
> >> +       interrupts = <7>;
> >> +       clock-frequency = <166666667>;
> >
> > It's got nothing to do with this patch, but getting a clock frequency
> > out of the DT instead of getting it from the clk_get_rate(clk) and
> > the clock tree seems absurd... (But maybe this platform does not
> > even have a clk implementation?)
> 
> It's of_serial's implementation. I patched that once for getting
> frequency out of "clocks" property but then I got busy with
> porting mach-dove and pinctrl.. Marvell SoCs do have a clk
> implementation and as soon as of_serial can handle "clocks"
> property it will be used for sure. I can remove "clock-frequency"
> from the example anyway as it is not really part of pinctrl
> binding documentation.

We are also working on using the clk framework for the 370/XP support
(my colleague Gr?gory in Cc has started working on this last week), and
we also want to be able to get the serial clock-frequency from the clk
framework instead of an explicit value in the DT node. But that's a
separate topic :)

> > Is it possible to use devm_* managed devm_kzalloc() for this map
> > so you don't need to free it explicitly?
> >
> > (Maybe not, just checking.)
> 
> Hmm, I guess not as I thought I've read not to use devm_kfree when
> you allocate _and_ free stuff on runtime without removing the device
> itself, right?

It is also my understanding that devm_*() functions should be used to
allocate things that should persist until the device is removed. But I
might be wrong here.

> >> +struct mvebu_mpp_ctrl {
> >> +       const char *name;
> >> +       u8 pid;
> >> +       u8 npins;
> >
> > So, there will never be > 256 pins on a Marvell platform?
> 
> Well, with all current platforms we are well below 100. I guess
> 256 max (muxable) pins will be enough.

Agreed, and this structure is completely internal to the kernel, so we
can easily change it in the future if needed.

> >> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
> >> + * @val: ctrl setting value
> >
> > It is not obvious to me what this means, it it possible to elaborate
> > on how this member is defined and used?
> 
> Well, I see if I can clarify the description but wrt the datasheet it
> _should_ be quite obvious.

I think the setting/function/group/control terminology would benefit
from an explanation, as it isn't very easy to figure out what all these
words mean in the context of the pinctrl-mvebu driver.

> In some internal review with Andrew I also added a spinlock to
> mvebu_pinconf_get/_set that will protect all calls to generic and specific
> _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
> with the devm_ counterpart and removed the explicit clk_put.

Yes, I had seen this discussion, but I am not sure it is needed: it
seems the pinctrl core calls all the pinconf_set/pinconf_get methods
with the pinctrl_mutex held. When I wrote an initial pinctrl driver for
370/XP I had the same question as Andrew and my conclusion was that the
locking done by the pinctrl subsystem core was sufficient.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Mon Aug 20 08:55:32 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 13:55:32 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820121055.GA26991@opensource.wolfsonmicro.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
Message-ID: <20120820125531.GA20242@gmail.com>

On Mon, Aug 20, 2012 at 01:10:55PM +0100, Mark Brown wrote:
> On Mon, Aug 20, 2012 at 09:36:43AM +0100, Lee Jones wrote:
> > On Tue, Aug 14, 2012 at 12:44:37PM +0200, Linus Walleij wrote:
> 
> > > Yes but I think I saw this other patch set from Lee, hitting
> > > irqdomain, OF and MFD to actually fix this ... or did I get
> > > it wrong?
> 
> > No, you're not wrong.
> 
> > Historically (in my patches) xb8500_irq_get_virq() was used by drivers
> > to obtain a VIRQ when not using Device Tree. Now the MFD core handles
> > conversion there is little requirement for it. In fact there are no
> > more users for db8500_irq_get_virq() and only one user for 
> > ab8500_irq_get_virq() and that's itself. I guess we can rid them and
> > call irq_get_mapping() directly instead.
> 
> Oh dear.  Unfortunately whoever added this support to the MFD core did
> so in such a manner that it's only supported for device tree systems
> and only for devices which express the MFD cells as device tree nodes
> which means that most devices can't it - db8500 has got a reasonably
> unusual combination there.

Right, that was the initial intention. It would be a trivial semantic
change if drivers without DT support wished to use the functionality
though. However, the only examples I found of a non-DT enabled driver
that could make good use of it in order to strip out some cruft would
be the Arizona and one of the Samsung drivers, and they each have
their own hand-rolled methods of hwirq -> virq conversion now, so any
change to support them would result in multiple invocations of
irq_create_mapping which would likely cause breakage.
 
-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From alanbutty12 at gmail.com  Mon Aug 20 08:55:39 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 13:55:39 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 DT support Signed-off-by:
 Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <20120820114320.GB26837@lunn.ch>
References: <cover.1345459608.git.alanbutty12@gmail.com>
 <1d07faa52b5ca4453c7eaa7c9decb01af92ee648.1345459608.git.alanbutty12@gmail.com>
 <20120820114320.GB26837@lunn.ch>
Message-ID: <CADhrpJ6oH3W9XevfFo52-cxu0zoZ2tmxZuANje01igXeawJP4w@mail.gmail.com>

On 20 August 2012 12:43, Andrew Lunn <andrew at lunn.ch> wrote:
> Hi Alan
>
> Overall this is looking good.
>
> Just a few minor comments below.
>
>> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> new file mode 100644
>> index 0000000..0c78752
>> --- /dev/null
>> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> @@ -0,0 +1,79 @@
>> +/*
>> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
>> + *
>> + * Iomega StorCenter ix2-200
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/irq.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/ata_platform.h>
>> +#include <linux/mv643xx_eth.h>
>> +#include <linux/ethtool.h>
>> +#include <net/dsa.h>
>> +#include <linux/gpio.h>
>> +#include <linux/leds.h>
>> +#include <linux/i2c.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <mach/kirkwood.h>
>> +#include "common.h"
>> +#include "mpp.h"
>
> It would be good to remove all the unneeded include files.
>
>> +
>> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
>> +     .phy_addr       = MV643XX_ETH_PHY_NONE,
>> +     .speed          = SPEED_1000,
>> +     .duplex         = DUPLEX_FULL,
>> +};
>
> It is somewhat unusual to have this configuration, 1000 full. Is this
> a hardware limitation? Or is the port connected to an internal switch?
> Maybe add a comment why its hard coded.
>
>       Andrew
>

the only 2 includes i can think of that might be able to be removed are:

#include <linux/ethtool.h>
#include <net/dsa.h>

As they do not appear in the iconnect or the goflexnet which i have
been using as my guide to makeing the dts file.
But i am not sure about the include files its probably best to leave
them the way they are maybe?.

As for the network that was setup that way in the origional modified
config file and in uboot on the device it states 2 network devices
egiga0 and egiga1 i believe it refers to them by but the device only
has only 1 phisical network interface (egiga1) so i think there must
be some kind of switch inside.


From jon-hunter at ti.com  Mon Aug 20 09:05:20 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Mon, 20 Aug 2012 08:05:20 -0500
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <20120820090138.GA25864@mudshark.cambridge.arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
 <502E5073.6000901@ti.com> <20120820090138.GA25864@mudshark.cambridge.arm.com>
Message-ID: <50323610.5020200@ti.com>


On 08/20/2012 04:01 AM, Will Deacon wrote:
> On Fri, Aug 17, 2012 at 03:08:51PM +0100, Jon Hunter wrote:
>> Hi Will, Tony,
> 
> Hi Jon [adding Arnd],
> 
>> On 08/10/2012 12:36 PM, Will Deacon wrote:
>>> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
>>> index c00c689..02b9478 100644
>>> --- a/arch/arm/mach-omap2/devices.c
>>> +++ b/arch/arm/mach-omap2/devices.c
>>> @@ -23,7 +23,6 @@
>>>  #include <mach/irqs.h>
>>>  #include <asm/mach-types.h>
>>>  #include <asm/mach/map.h>
>>> -#include <asm/pmu.h>
>>>  
>>>  #include "iomap.h"
>>>  #include <plat/board.h>
>>> @@ -448,7 +447,7 @@ static struct resource omap3_pmu_resource = {
>>>  
>>>  static struct platform_device omap_pmu_device = {
>>>  	.name		= "arm-pmu",
>>> -	.id		= ARM_PMU_DEVICE_CPU,
>>> +	.id		= -1,
>>>  	.num_resources	= 1,
>>>  };
>>
>> I know that I have already ack-ed the change and it is fine with me,
>> however, I see a potential merge conflict here with my patch [1]
>> (assuming that these all go into v3.7) where I am moving the above
>> structure.
> 
> Are your patches queued anywhere other than your tree? If not, then I could
> ask Arnd to pull the perf changes into their own branch in arm-soc and you
> could rebase onto that.

No just my tree for now, so that would work for me.

>> For testing I have rebased my series on top of this series and it is
>> working well so far on OMAP4460.
> 
> Great, thanks. Can I add your tested-by to the patches please?

Yes, you can add my tested-by. I will also test on omap3 and omap4430 too.

Cheers
Jon


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 09:18:46 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 14:18:46 +0100
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
 <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>
Message-ID: <20120820131845.GD26991@opensource.wolfsonmicro.com>

On Fri, Aug 17, 2012 at 08:35:49PM -0300, Fabio Estevam wrote:

> Are you running a dt or non-dt kernel? In case of a dt kernel, can you
> share the dts file?

Non-DT.
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From festevam at gmail.com  Mon Aug 20 09:24:24 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 20 Aug 2012 10:24:24 -0300
Subject: [alsa-devel] Lockups reading from i.MX51 SSI registers
In-Reply-To: <20120820131845.GD26991@opensource.wolfsonmicro.com>
References: <20120810195005.GP24328@opensource.wolfsonmicro.com>
 <20120810195638.GF1451@pengutronix.de>
 <20120810201456.GL25520@pengutronix.de>
 <20120810210647.GG1451@pengutronix.de>
 <CAOMZO5DAs=jm-08tWdfdLG_nm=gdi-Q_RReiUKGM_RCgB82dwA@mail.gmail.com>
 <20120817222738.GH18871@opensource.wolfsonmicro.com>
 <CAOMZO5BgeW_z-zf3Auw6RCJg1o5L=DqWdVeF+0Xb_W=6hZJMnQ@mail.gmail.com>
 <20120820131845.GD26991@opensource.wolfsonmicro.com>
Message-ID: <CAOMZO5D0HnhLAwo0Ee+McciU7ZKOTJeBxoNU+vXFEwi9K7V96w@mail.gmail.com>

On 8/20/12, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
> On Fri, Aug 17, 2012 at 08:35:49PM -0300, Fabio Estevam wrote:
>
>> Are you running a dt or non-dt kernel? In case of a dt kernel, can you
>> share the dts file?
>
> Non-DT.

Please try this patch:
http://www.spinics.net/lists/arm-kernel/msg190040.html

Regards,

Fabio Estevam


From andrew at lunn.ch  Mon Aug 20 09:25:00 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 20 Aug 2012 15:25:00 +0200
Subject: [PATCH] ARM: Kirkwood: Iomega_IX2_200 DT support Signed-off-by:
 Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ6oH3W9XevfFo52-cxu0zoZ2tmxZuANje01igXeawJP4w@mail.gmail.com>
References: <cover.1345459608.git.alanbutty12@gmail.com>
 <1d07faa52b5ca4453c7eaa7c9decb01af92ee648.1345459608.git.alanbutty12@gmail.com>
 <20120820114320.GB26837@lunn.ch>
 <CADhrpJ6oH3W9XevfFo52-cxu0zoZ2tmxZuANje01igXeawJP4w@mail.gmail.com>
Message-ID: <20120820132500.GC26837@lunn.ch>

> >> +#include <linux/kernel.h>
> >> +#include <linux/init.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/irq.h>
> >> +#include <linux/mtd/partitions.h>
> >> +#include <linux/ata_platform.h>
> >> +#include <linux/mv643xx_eth.h>
> >> +#include <linux/ethtool.h>
> >> +#include <net/dsa.h>
> >> +#include <linux/gpio.h>
> >> +#include <linux/leds.h>
> >> +#include <linux/i2c.h>
> >> +#include <asm/mach-types.h>
> >> +#include <asm/mach/arch.h>
> >> +#include <mach/kirkwood.h>
> >> +#include "common.h"
> >> +#include "mpp.h"
> >
> > It would be good to remove all the unneeded include files.
> >
> >> +
> >> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> >> +     .phy_addr       = MV643XX_ETH_PHY_NONE,
> >> +     .speed          = SPEED_1000,
> >> +     .duplex         = DUPLEX_FULL,
> >> +};
> >
> > It is somewhat unusual to have this configuration, 1000 full. Is this
> > a hardware limitation? Or is the port connected to an internal switch?
> > Maybe add a comment why its hard coded.
> >
> >       Andrew
> >
> 
> the only 2 includes i can think of that might be able to be removed are:
> 
> #include <linux/ethtool.h>
> #include <net/dsa.h>

I think you can remove a lot more. I _think_ you can remove all these:

#include <linux/irq.h>
#include <linux/mtd/partitions.h>
#include <linux/ata_platform.h>
#include <net/dsa.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/i2c.h>

and maybe:

#include <asm/mach-types.h>
#include <asm/mach/arch.h>


Try it and see.

> As for the network that was setup that way in the origional modified
> config file and in uboot on the device it states 2 network devices
> egiga0 and egiga1 i believe it refers to them by but the device only
> has only 1 phisical network interface (egiga1) so i think there must
> be some kind of switch inside.

You should only instantiate the one that is usable, comes outside of
the box. I would delete the other.

	Andrew


From nico at fluxnic.net  Mon Aug 20 09:29:31 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 20 Aug 2012 09:29:31 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120820124109.GK25864@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208200902120.1754@xanadu.home>

On Mon, 20 Aug 2012, Will Deacon wrote:

> Hi Nicolas,
> 
> [apologies in advance for the long reply]
> 
> On Fri, Aug 17, 2012 at 04:43:01AM +0100, Nicolas Pitre wrote:
> > On Tue, 14 Aug 2012, Will Deacon wrote:
> > 
> > > Data aborts taken to hyp mode do not provide a valid instruction
> > > syndrome field in the HSR if the faulting instruction is a memory
> > > access using a writeback addressing mode.
> > > 
> > > For hypervisors emulating MMIO accesses to virtual peripherals, taking
> > > such an exception requires disassembling the faulting instruction in
> > > order to determine the behaviour of the access. Since this requires
> > > manually walking the two stages of translation, the world must be
> > > stopped to prevent races against page aging in the guest, where the
> > > first-stage translation is invalidated after the hypervisor has
> > > translated to an IPA and the physical page is reused for something else.
> > > 
> > > This patch avoids taking this heavy performance penalty when running
> > > Linux as a guest by ensuring that our I/O accessors do not make use of
> > > writeback addressing modes.
> > 
> > How often does this happen?  I don't really see writeback as a common 
> > pattern for IO access.
> 
> Building a Thumb-2 kernel with GCC:
> 
> gcc version 4.6.3 20120201 (prerelease) (crosstool-NG
> linaro-1.13.1-2012.02-20120222 - Linaro GCC 2012.02)
> 
> Translates the following code from amba_device_add:
> 
> 		for (pid = 0, i = 0; i < 4; i++)
> 			pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) <<
> 				(i * 8);
> 		for (cid = 0, i = 0; i < 4; i++)
> 			cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
> 				(i * 8);
> 
> into:
[...]

OK, I can see how the compiler will fold the loop increment into the IO 
access instruction.  But my point is: is this common?  And when this 
happens, is this a critical path?

> > What does happen quite a lot, though, is pre-indexed addressing.  For 
> > example, let's take this code which is fairly typical of driver code:
> > 
> > #define HW_REG1		0x10
> > #define HW_REG2		0x14
> > #define HW_REG3		0x18
> > #define HW_REG4		0x30
> > 
> > int hw_init(void __iomem *ioaddr)
> > {
> > 	writel(0, ioaddr + HW_REG1)
> > 	writel(-1, ioaddr + HW_REG2);
> > 	writel(readl(ioaddr + HW_REG3) | 0xff, ioaddr + HW_REG4);
> > 	return 0;
> > }
> > 
> > Right now this produces this:
> > 
> > hw_init:
> >         mov     r3, r0
> >         mvn     r2, #0
> >         mov     r0, #0
> >         str     r0, [r3, #16]
> >         str     r2, [r3, #20]
> >         ldr     r2, [r3, #24]
> >         orr     r2, r2, #255
> >         str     r2, [r3, #48]
> >         bx      lr
> 
> Well, that's not quite true for CONFIG_ARM_DMA_MEM_BUFFERABLE=y.

True.  I turned those readl() into their raw counterparts to generate 
the assembly but didn't update the example code in my mailer.

> whilst the addressing modes are still nice, the dsb is going to be the
> performance limitation here. That said, we could try the "Qo" constraints,
> which I seem to remember don't generate writebacks. I'll have a play.

OK.  That would be excellent.

> > So, is the performance claim something that you've actually measured 
> > with a real system, or was it only theoretical?
> 
> The difference is down to the work done by the hypvervisor: an MMIO access
> will trap to hyp mode, where the HSR describes the instruction (access size,
> load/store, Rt, signed etc). For the case of a writeback instruction, this
> information is not provided by the hardware. Instead, the hypervisor has to
> disassemble the faulting instruction and work out what it's doing at which
> address prior to emulation.
> 
> Even if that cost was acceptable, the problem then gets worse. Imagine that
> a guest MMIO access faults into the hypervisor, where the emulation code
> tries to decode the instruction because the fault information is incomplete.
> To do this, it must obtain the *physical* address of the faulting text page
> so that it can load the instruction. This happens via the ATS12NSOP{R,W}
> registers, which return a PA for the faulting VA (i.e. both stages of
> translation).
> 
> Now, let's say the hypervisor has got hold of a PA but hasn't yet loaded the
> instruction. Meanwhile, another virtual CPU running the same guest decides
> (due to page aging or whatnot) to reclaim the text page containing the
> faulting instruction. It writes a faulting pte and does a TLB invalidation,
> however this is too late for the hypervisor, who has already translated its
> address. Furthermore, let's say that the guest then reuses the same physical
> page for something like a network buffer. The hypervisor goes ahead and grabs
> what it thinks is the faulting instruction from memory but in fact gets a
> load of random network data!
> 
> To deal with this, the hypervisor will likely have to stop the virtual world
> when emulating any MMIO accesses that report incomplete fault information to
> avoid racing with a TLB invalidation from another virtual CPU. That will
> certainly be more expensive than an additional instruction on each access.

I totally agree with you here.

However, for completeness and above all for security reasons, the 
hypervisor will _ahve_ to support that case anyway.

So it is now a matter of compromise between performance and code size.  
If the pathological case you brought up above is the exception and not 
the rule then I think that we can live with the performance impact in 
that case and keep the optimal pre-indexed addressing for the common 
cases.


Nicolas


From linus.walleij at linaro.org  Mon Aug 20 09:43:11 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 15:43:11 +0200
Subject: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver
In-Reply-To: <1344689809-6223-3-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-3-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkda9BL5+NiDOsMKG0kv2coBsw=Er=ZccXnNkgeftV9hPhQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

(...)
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>
>  config PINCTRL_MVEBU
>         bool "Marvell SoC pin controller drivers"
> -       depends on ARCH_MVEBU
> +       depends on ARCH_MVEBU || ARCH_DOVE

Hmmmm.

Shouldn't this thing rather be:

depends on PLAT_ORION

else you end up lining up all Marvell machines here...

>         select PINMUX
>         select PINCONF
>         help
> @@ -155,6 +155,13 @@ config PINCTRL_MVEBU
>           This is only the driver core and additionally needs a SoC specific
>           driver.
>
> +config PINCTRL_DOVE
> +       bool "Support for Marvell Dove SoCs"
> +       depends on PINCTRL_MVEBU

Shouldn't this rather be:

depends on ARCH_DOVE
select PINCTRL_MVEBU

since you call down into the mvebu driver, it definatley needs
to select that.

(...)
> diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c

> +#define  DOVE_AU0_AC97_SEL             (1 << 16)

It is way cleaner to say:

#include <linux/bitops.h>

#define  DOVE_AU0_AC97_SEL             BIT(16)

(...)
> +static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> +                                unsigned long *config)
> +{
> +       unsigned off = (ctrl->pid / 8) * 4;
> +       unsigned shift = (ctrl->pid % 8) * 4;
> +       unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
> +       unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
> +
> +       if (pmu & (1 << ctrl->pid))
> +               *config = 0x10;
> +       else
> +               *config = (mpp >> shift) & 0xf;
> +       return 0;
> +}

Same comments about the magic numbers as in the review of the first
patch.

> +static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> +                                unsigned long config)
> +{
> +       unsigned off = (ctrl->pid / 8) * 4;
> +       unsigned shift = (ctrl->pid % 8) * 4;
> +       unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
> +       unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
> +
> +       if (config == 0x10)
> +               writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
> +       else {
> +               writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
> +               mpp &= ~(0xf << shift);
> +               mpp |= config << shift;
> +               writel(mpp, DOVE_MPP_VIRT_BASE + off);
> +       }
> +       return 0;
> +}

Dito.

> +static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> +                             unsigned long *config)
> +{
> +       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> +       unsigned long mask;
> +
> +       if (ctrl->pid == 24)
> +               mask = DOVE_CAM_GPIO_SEL;
> +       else if (ctrl->pid == 40)
> +               mask = DOVE_SD0_GPIO_SEL;
> +       else if (ctrl->pid == 46)
> +               mask = DOVE_SD1_GPIO_SEL;
> +       else if (ctrl->pid == 58)
> +               mask = DOVE_SPI_GPIO_SEL;
> +       else if (ctrl->pid == 62)
> +               mask = DOVE_UART1_GPIO_SEL;
> +       else
> +               return -EINVAL;

Magic numbers, atleast provide a comment on what is so special about
these pins, and can you use a switch() statement instead?

(...)
> +static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> +                             unsigned long config)
> +{
> +       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> +       unsigned long mask;
> +
> +       if (ctrl->pid == 24)
> +               mask = DOVE_CAM_GPIO_SEL;
> +       else if (ctrl->pid == 40)
> +               mask = DOVE_SD0_GPIO_SEL;
> +       else if (ctrl->pid == 46)
> +               mask = DOVE_SD1_GPIO_SEL;
> +       else if (ctrl->pid == 58)
> +               mask = DOVE_SPI_GPIO_SEL;
> +       else if (ctrl->pid == 62)
> +               mask = DOVE_UART1_GPIO_SEL;
> +       else
> +               return -EINVAL;

Dito.

(...)
> +static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
> +                               unsigned long *config)
> +{
> +       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> +       unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
> +       unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> +       unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
> +
> +       *config = 0;
> +       if (mpp4 & DOVE_AU1_GPIO_SEL)
> +               *config |= 0x8;
> +       if (sspc1 & DOVE_SSP_ON_AU1)
> +               *config |= 0x4;
> +       if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
> +               *config |= 0x2;
> +       if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
> +               *config |= 0x1;

More magic, but the flags make it clear what the set
bits are all about, so OK.

But I would have:
#include <linux/bitops.h>

*config |= BIT(0);

etc.

> +       /* SSP/TWSI only if I2S1 not set*/
> +       if ((*config & 0x8) == 0)
> +               *config &= ~(0x4 | 0x1);
> +       /* TWSI only if SPDIFO not set*/
> +       if ((*config & 0x2) == 0)
> +               *config &= ~(0x1);
> +       return 0;

And that applies to these.

> +static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
> +                               unsigned long config)
> +{
> +       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
> +       unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
> +       unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
> +       unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
> +
> +       if (config & 0x1)
> +               gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
> +       if (config & 0x2)
> +               gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
> +       if (config & 0x4)
> +               sspc1 |= DOVE_SSP_ON_AU1;
> +       if (config & 0x8)
> +               mpp4 |= DOVE_AU1_GPIO_SEL;

Dito.

> +static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
> +{
> +       unsigned long config;
> +
> +       dove_audio1_ctrl_get(ctrl, &config);
> +
> +       switch (config) {
> +       /* mode 0x00 i2s1/spdifo : no gpio */
> +       /* mode 0x0c ssp/spdifo  : no gpio */
> +       /* mode 0x0f ssp/twsi    : no gpio */
> +       case 0x00:
> +       case 0x0c:
> +       case 0x0f:
> +               return -ENOTSUPP;

Nice with the comments (also before the function),
now I understand what's happening, this is pretty OK,
I would have put the comments on the same
line as the magic number but whatever.

However you could just delete these lines and let them
fall through to -ENOTSUPP at the bottom.

> +
> +       /* mode 0x02 i2s1 : gpio[56:57] */
> +       /* mode 0x0e ssp  : gpio[56:57] */
> +       case 0x02:
> +       case 0x0e:
> +               if (pid >= 56)
> +                       return 0;
> +
> +       /* mode 0x08 spdifo : gpio[52:55] */
> +       /* mode 0x0b twsi   : gpio[52:55] */
> +       case 0x08:
> +       case 0x0b:
> +               if (pid <= 55)
> +                       return 0;
> +
> +       /* mode 0x0a/gpio : all gpio */
> +       case 0x0a:
> +               return 0;
> +       }
> +
> +       return -ENOTSUPP;
> +}

> +/* mpp[52:57] has gpio pins capable of in and out */
> +static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
> +                               bool input)
> +{
> +       return 0;
> +}

So should this not return a -ENOTSUPP for
pin < 52 || pin > 57?

(...)
> +static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
> +{
> +       const struct of_device_id *match =
> +               of_match_device(dove_pinctrl_of_match, &pdev->dev);
> +       int ret;
> +
> +       if (match)
> +               pdev->dev.platform_data = match->data;
> +
> +       /*
> +        * General MPP Configuration Register is part of pdma registers.
> +        * grab clk to make sure it is clocked.
> +        */
> +       pdma_clk = clk_get_sys("dove-pdma", NULL);

First there is something really weird with the name of this
clock. Atleast call the variable holding the clk something
apropriate like just "clk".

Second why are you fetching a sys clock instead of using the clkdev
device binding in the clock tree so you could say:

clk = clk_get(&pdev->dev, NULL);

> +       clk_prepare_enable(pdma_clk);

Good!

> +       ret = mvebu_pinctrl_probe(pdev);
> +       if (!ret)
> +               return 0;
> +
> +       clk_disable_unprepare(pdma_clk);
> +       clk_put(pdma_clk);
> +       return ret;
> +}
> +
> +static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
> +{
> +       int ret;
> +
> +       ret = mvebu_pinctrl_remove(pdev);
> +       if (!IS_ERR(pdma_clk)) {
> +               clk_disable_unprepare(pdma_clk);
> +               clk_put(pdma_clk);
> +       }

You don't need this (!IS_ERR()) clause, look in yout probe function:
you bail out if the clock is not found.

The rest looks good... atleast now, but I'm low on coffee FTM.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 09:49:01 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 15:49:01 +0200
Subject: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdbG4jkFcVP_6AmAZzciffQCamKXw7PcFnTdccyq7AMa8A@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
> plus DT binding documentation. This driver will use the mvebu pinctrl
> driver core.

Thanks for working on Kirkwood. Love this platform.

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index cd3d827..361f513 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
>         select GENERIC_CLOCKEVENTS
>         select NEED_MACH_IO_H
>         select PLAT_ORION
> +       select PINCTRL

select PINCTRL_KIRKWOOD too I think.
Then it's just automatic.

> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index e2427eb..1f84090 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>
>  config PINCTRL_MVEBU
>         bool "Marvell SoC pin controller drivers"
> -       depends on ARCH_MVEBU || ARCH_DOVE
> +       depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD

As stated elsewhere I think this should be
depends on PLAT_ORION

> +config PINCTRL_KIRKWOOD
> +       bool "Support for Marvell Kirkwood SoCs"
> +       depends on PINCTRL_MVEBU

depends on ARCH_KIRKWOOD
select PINCTRL_MVEBU

(...)
> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
> +
> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
> +       { .compatible = "marvell,88f6180-pinctrl",
> +                                         .data = (void *)VARIANT_MV88F6180 },
> +       { .compatible = "marvell,88f6190-pinctrl",
> +                                         .data = (void *)VARIANT_MV88F6190 },
> +       { .compatible = "marvell,88f6192-pinctrl",
> +                                         .data = (void *)VARIANT_MV88F6192 },
> +       { .compatible = "marvell,88f6281-pinctrl",
> +                                         .data = (void *)VARIANT_MV88F6281 },
> +       { .compatible = "marvell,88f6282-pinctrl",
> +                                         .data = (void *)VARIANT_MV88F6282 },
> +       { }
> +};

I'm thinking this variant should maybe be an enum... unless it is
strongly established somewhere in Orion/Marvell stuff.

> +static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
> +       const struct of_device_id *match =
> +               of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
> +
> +       if (match) {
> +               soc->variant = (unsigned)match->data & 0xff;
> +               switch (soc->variant) {
> +               case VARIANT_MV88F6180:
> +                       soc->controls = mv88f6180_mpp_controls;
> +                       soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
> +                       soc->modes = mv88f6xxx_mpp_modes;
> +                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> +                       soc->gpioranges = mv88f6180_gpio_ranges;
> +                       soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
> +                       break;
> +               case VARIANT_MV88F6190:
> +               case VARIANT_MV88F6192:
> +                       soc->controls = mv88f619x_mpp_controls;
> +                       soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
> +                       soc->modes = mv88f6xxx_mpp_modes;
> +                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> +                       soc->gpioranges = mv88f619x_gpio_ranges;
> +                       soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
> +                       break;
> +               case VARIANT_MV88F6281:
> +               case VARIANT_MV88F6282:
> +                       soc->controls = mv88f628x_mpp_controls;
> +                       soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
> +                       soc->modes = mv88f6xxx_mpp_modes;
> +                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
> +                       soc->gpioranges = mv88f628x_gpio_ranges;
> +                       soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
> +                       break;
> +               }
> +               pdev->dev.platform_data = soc;
> +       }
> +       return mvebu_pinctrl_probe(pdev);
> +}

This is looking real good, clean & nice.

No further comments on this driver.

Yours,
Linus Walleij


From prabhakar.lad at ti.com  Mon Aug 20 10:08:49 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Mon, 20 Aug 2012 19:38:49 +0530
Subject: [PATCH v2 0/2] ARM: davinci: da850/omap-l138: add support for VPIF
 driver
Message-ID: <1345471731-31678-1-git-send-email-prabhakar.lad@ti.com>

This patch series adds support for VPIF
capture and display driver on da850/omap-l138.
Enables SD capture and display.

This patch series is dependent on the following patch:
https://patchwork.kernel.org/patch/1332311/

Changes for v2:
1: Avoid breaking of print messages.
2: Removed the handlers which just returned zero (which did nothing).
3: Clubbed the code where ever possible for DA850_UI_SD_VIDEO_PORT
   config option.
4: Removed the dma_declare_coherent_memory() calls and used 
   global CMA.
5: Added the base address in increasing order.

Manjunath Hadli (2):
  ARM: da850/omap-l138: Add SoC related definitions for VPIF
  ARM: da850/omap-l138: Add EVM specific code for VPIF to work

 arch/arm/mach-davinci/Kconfig              |    9 ++
 arch/arm/mach-davinci/board-da850-evm.c    |  178 ++++++++++++++++++++++++++++
 arch/arm/mach-davinci/da850.c              |  162 +++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/da8xx.h |   11 ++
 arch/arm/mach-davinci/include/mach/mux.h   |   42 +++++++
 arch/arm/mach-davinci/include/mach/psc.h   |    1 +
 6 files changed, 403 insertions(+), 0 deletions(-)



From prabhakar.lad at ti.com  Mon Aug 20 10:08:50 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Mon, 20 Aug 2012 19:38:50 +0530
Subject: [PATCH v2 1/2] ARM: da850/omap-l138: Add SoC related definitions for
 VPIF
In-Reply-To: <1345471731-31678-1-git-send-email-prabhakar.lad@ti.com>
References: <1345471731-31678-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1345471731-31678-2-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

Add clock, pin mux definitions and registration function for
VPIF capture and display driver on DA850/OMAP-L138 SoC.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
Cc: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/da850.c              |  162 ++++++++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/da8xx.h |   11 ++
 arch/arm/mach-davinci/include/mach/mux.h   |   42 +++++++
 arch/arm/mach-davinci/include/mach/psc.h   |    1 +
 4 files changed, 216 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc84..76e434a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -347,6 +347,13 @@ static struct clk spi1_clk = {
 	.flags		= DA850_CLK_ASYNC3,
 };
 
+static struct clk vpif_clk = {
+	.name		= "vpif",
+	.parent		= &pll0_sysclk2,
+	.lpsc		= DA850_LPSC1_VPIF,
+	.gpsc		= 1,
+};
+
 static struct clk sata_clk = {
 	.name		= "sata",
 	.parent		= &pll0_sysclk2,
@@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = {
 	CLK(NULL,		"usb20",	&usb20_clk),
 	CLK("spi_davinci.0",	NULL,		&spi0_clk),
 	CLK("spi_davinci.1",	NULL,		&spi1_clk),
+	CLK("vpif",		NULL,		&vpif_clk),
 	CLK("ahci",		NULL,		&sata_clk),
 	CLK(NULL,		NULL,		NULL),
 };
@@ -573,6 +581,46 @@ static const struct mux_config da850_pins[] = {
 	MUX_CFG(DA850, GPIO6_10,	13,	20,	15,	8,	false)
 	MUX_CFG(DA850, GPIO6_13,	13,	8,	15,	8,	false)
 	MUX_CFG(DA850, RTC_ALARM,	0,	28,	15,	2,	false)
+	/* VPIF Capture */
+	MUX_CFG(DA850, VPIF_DIN0,	15,	4,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN1,	15,	0,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN2,	14,	28,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN3,	14,	24,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN4,	14,	20,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN5,	14,	16,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN6,	14,	12,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN7,	14,	8,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN8,	16,	4,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN9,	16,	0,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN10,	15,	28,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN11,	15,	24,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN12,	15,	20,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN13,	15,	16,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN14,	15,	12,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DIN15,	15,	8,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKIN0,	14,	0,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKIN1,	14,	4,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKIN2,	19,	8,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKIN3,	19,	16,	15,	1,	false)
+	/* VPIF Display */
+	MUX_CFG(DA850, VPIF_DOUT0,	17,	4,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT1,	17,	0,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT2,	16,	28,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT3,	16,	24,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT4,	16,	20,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT5,	16,	16,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT6,	16,	12,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT7,	16,	8,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT8,	18,	4,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT9,	18,	0,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT10,	17,	28,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT11,	17,	24,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT12,	17,	20,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT13,	17,	16,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT14,	17,	12,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_DOUT15,	17,	8,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKO2,	19,	12,	15,	1,	false)
+	MUX_CFG(DA850, VPIF_CLKO3,	19,	20,	15,	1,	false)
 #endif
 };
 
@@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initdata = {
 	-1
 };
 
+const short da850_vpif_capture_pins[] __initdata = {
+	DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
+	DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
+	DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
+	DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
+	DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
+	DA850_VPIF_CLKIN3,
+	-1
+};
+
+const short da850_vpif_display_pins[] __initdata = {
+	DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
+	DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
+	DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
+	DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
+	DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
+	DA850_VPIF_CLKO3,
+	-1
+};
+
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_COMMTX]		= 7,
@@ -1064,6 +1132,100 @@ no_ddrpll_mem:
 	return ret;
 }
 
+/* VPIF resource, platform data */
+static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource da850_vpif_resource[] = {
+	{
+		.start = DA8XX_VPIF_BASE,
+		.end   = DA8XX_VPIF_BASE + 0xfff,
+		.flags = IORESOURCE_MEM,
+	}
+};
+
+static struct platform_device da850_vpif_dev = {
+	.name		= "vpif",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &da850_vpif_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+	.resource	= da850_vpif_resource,
+	.num_resources	= ARRAY_SIZE(da850_vpif_resource),
+};
+
+static struct platform_device da850_vpif_display_dev = {
+	.name		= "vpif_display",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &da850_vpif_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+static struct platform_device da850_vpif_capture_dev = {
+	.name		= "vpif_capture",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &da850_vpif_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+int __init da850_register_vpif(void)
+{
+	return platform_device_register(&da850_vpif_dev);
+}
+
+int __init da850_register_vpif_display(struct vpif_display_config
+						*display_config)
+{
+	struct resource da850_vpif_display_resource[] = {
+		{
+			.start = IRQ_DA850_VPIFINT,
+			.end   = IRQ_DA850_VPIFINT,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+	int ret;
+
+	ret = platform_device_add_resources(&da850_vpif_display_dev,
+				da850_vpif_display_resource,
+				ARRAY_SIZE(da850_vpif_display_resource));
+	if (ret)
+		return -EINVAL;
+
+	da850_vpif_display_dev.dev.platform_data = display_config;
+	return platform_device_register(&da850_vpif_display_dev);
+}
+
+int __init da850_register_vpif_capture(struct vpif_capture_config
+							*capture_config)
+{
+	static struct resource da850_vpif_capture_resource[] = {
+		{
+			.start = IRQ_DA850_VPIFINT,
+			.end   = IRQ_DA850_VPIFINT,
+			.flags = IORESOURCE_IRQ,
+		},
+		{
+			.start = IRQ_DA850_VPIFINT,
+			.end   = IRQ_DA850_VPIFINT,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+	int ret;
+
+	ret = platform_device_add_resources(&da850_vpif_capture_dev,
+				da850_vpif_capture_resource,
+				ARRAY_SIZE(da850_vpif_capture_resource));
+	if (ret)
+		return -EINVAL;
+
+	da850_vpif_capture_dev.dev.platform_data = capture_config;
+	return platform_device_register(&da850_vpif_capture_dev);
+}
+
 static struct davinci_soc_info davinci_soc_info_da850 = {
 	.io_desc		= da850_io_desc,
 	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f27..8eecbce 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
+#include <linux/videodev2.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
@@ -26,6 +27,8 @@
 #include <mach/pm.h>
 #include <mach/spi.h>
 
+#include <media/davinci/vpif_types.h>
+
 extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
 
@@ -63,6 +66,7 @@ extern unsigned int da850_max_speed;
 #define DA8XX_PLL0_BASE		0x01c11000
 #define DA8XX_TIMER64P0_BASE	0x01c20000
 #define DA8XX_TIMER64P1_BASE	0x01c21000
+#define DA8XX_VPIF_BASE		0x01e17000
 #define DA8XX_GPIO_BASE		0x01e26000
 #define DA8XX_PSC1_BASE		0x01e27000
 #define DA8XX_AEMIF_CS2_BASE	0x60000000
@@ -92,6 +96,11 @@ int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
 int __init da850_register_sata(unsigned long refclkpn);
+int __init da850_register_vpif(void);
+int __init da850_register_vpif_display
+			(struct vpif_display_config *display_config);
+int __init da850_register_vpif_capture
+			(struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
 
 extern struct platform_device da8xx_serial_device;
@@ -126,6 +135,8 @@ extern const short da830_ecap1_pins[];
 extern const short da830_ecap2_pins[];
 extern const short da830_eqep0_pins[];
 extern const short da830_eqep1_pins[];
+extern const short da850_vpif_capture_pins[];
+extern const short da850_vpif_display_pins[];
 
 extern const short da850_i2c0_pins[];
 extern const short da850_i2c1_pins[];
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index a7e92fc..9e95b8a 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -928,6 +928,48 @@ enum davinci_da850_index {
 	DA850_GPIO6_10,
 	DA850_GPIO6_13,
 	DA850_RTC_ALARM,
+
+	/* VPIF Capture */
+	DA850_VPIF_DIN0,
+	DA850_VPIF_DIN1,
+	DA850_VPIF_DIN2,
+	DA850_VPIF_DIN3,
+	DA850_VPIF_DIN4,
+	DA850_VPIF_DIN5,
+	DA850_VPIF_DIN6,
+	DA850_VPIF_DIN7,
+	DA850_VPIF_DIN8,
+	DA850_VPIF_DIN9,
+	DA850_VPIF_DIN10,
+	DA850_VPIF_DIN11,
+	DA850_VPIF_DIN12,
+	DA850_VPIF_DIN13,
+	DA850_VPIF_DIN14,
+	DA850_VPIF_DIN15,
+	DA850_VPIF_CLKIN0,
+	DA850_VPIF_CLKIN1,
+	DA850_VPIF_CLKIN2,
+	DA850_VPIF_CLKIN3,
+
+	/* VPIF Display */
+	DA850_VPIF_DOUT0,
+	DA850_VPIF_DOUT1,
+	DA850_VPIF_DOUT2,
+	DA850_VPIF_DOUT3,
+	DA850_VPIF_DOUT4,
+	DA850_VPIF_DOUT5,
+	DA850_VPIF_DOUT6,
+	DA850_VPIF_DOUT7,
+	DA850_VPIF_DOUT8,
+	DA850_VPIF_DOUT9,
+	DA850_VPIF_DOUT10,
+	DA850_VPIF_DOUT11,
+	DA850_VPIF_DOUT12,
+	DA850_VPIF_DOUT13,
+	DA850_VPIF_DOUT14,
+	DA850_VPIF_DOUT15,
+	DA850_VPIF_CLKO2,
+	DA850_VPIF_CLKO3,
 };
 
 enum davinci_tnetv107x_index {
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 405318e..40a0027 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -166,6 +166,7 @@
 #define DA830_LPSC1_McASP1		8
 #define DA850_LPSC1_SATA		8
 #define DA830_LPSC1_McASP2		9
+#define DA850_LPSC1_VPIF		9
 #define DA8XX_LPSC1_SPI1		10
 #define DA8XX_LPSC1_I2C			11
 #define DA8XX_LPSC1_UART1		12
-- 
1.7.0.4



From richard.genoud at gmail.com  Mon Aug 20 10:09:45 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 20 Aug 2012 16:09:45 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <CACQ1gAjJ2HL1b9hi3RKGWWs_kW_hELAFYQ=fnHGj5nymjWdiWw@mail.gmail.com>

Hi Jean-Christophe,

2012/8/10 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 477cf9d..bbd2f8e 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -310,12 +310,6 @@ static void __init at91sam9x5_map_io(void)
>         at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
>  }
>
> -void __init at91sam9x5_initialize(void)
> -{
> -       /* Register GPIO subsystem (using DT) */
> -       at91_gpio_init(NULL, 0);
> -}
> -
>  /* --------------------------------------------------------------------
>   *  Interrupt initialization
>   * -------------------------------------------------------------------- */
> @@ -323,5 +317,4 @@ void __init at91sam9x5_initialize(void)
>  struct at91_init_soc __initdata at91sam9x5_soc = {
>         .map_io = at91sam9x5_map_io,
>         .register_clocks = at91sam9x5_register_clocks,
> -       .init = at91sam9x5_initialize,
>  };
That's why my board wasn't booting anymore after your patchset.
if .init is NULL, then in arch/arm/mach-at91/soc.h :
static inline int at91_soc_is_enabled(void)
{
	return at91_boot_soc.init != NULL;
}
is false, and in arch/arm/mach-at91/setup.c:
void __init at91_map_io(void)
{
...
	if (!at91_soc_is_enabled())
		panic("AT91: Soc not enabled");
...
}

Regars,
Richard.


From prabhakar.lad at ti.com  Mon Aug 20 10:08:51 2012
From: prabhakar.lad at ti.com (Prabhakar Lad)
Date: Mon, 20 Aug 2012 19:38:51 +0530
Subject: [PATCH v2 2/2] ARM: da850/omap-l138: Add EVM specific code for VPIF
 to work
In-Reply-To: <1345471731-31678-1-git-send-email-prabhakar.lad@ti.com>
References: <1345471731-31678-1-git-send-email-prabhakar.lad@ti.com>
Message-ID: <1345471731-31678-3-git-send-email-prabhakar.lad@ti.com>

From: Manjunath Hadli <manjunath.hadli at ti.com>

Include the expander settings to select VPIF peripheral on
UI card and add registration call in EVM init. Also add platform
data to configure display and capture devices.

Signed-off-by: Manjunath Hadli <manjunath.hadli at ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad at ti.com>
Cc: Sekhar Nori <nsekhar at ti.com>
---
 arch/arm/mach-davinci/Kconfig           |    9 ++
 arch/arm/mach-davinci/board-da850-evm.c |  178 +++++++++++++++++++++++++++++++
 2 files changed, 187 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index ab99c3c..436b47c 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -186,6 +186,15 @@ config DA850_UI_RMII
 	  NOTE: Please take care while choosing this option, MII PHY will
 	  not be functional if RMII mode is selected.
 
+config DA850_UI_SD_VIDEO_PORT
+	bool "Video Port Interface"
+	help
+	  Say Y if you want to use Video Port Interface (VPIF) on the
+	  DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
+	  UI daughter card that is supplied with the EVM.
+	  NOTE: Please make sure to disable RMII and CLCD options when you
+	  select Video Port Interface.
+
 endchoice
 
 config DA850_WL12XX
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0149fb4..cdbbced 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -45,6 +45,8 @@
 #include <mach/aemif.h>
 #include <mach/spi.h>
 
+#include <media/tvp514x.h>
+
 #define DA850_EVM_PHY_ID		"davinci_mdio-0:00"
 #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
 #define DA850_LCD_BL_PIN		GPIO_TO_PIN(2, 15)
@@ -121,6 +123,12 @@ static struct spi_board_info da850evm_spi_info[] = {
 	},
 };
 
+#define TVP5147_CH0		"tvp514x-0"
+#define TVP5147_CH1		"tvp514x-1"
+
+#define VPIF_STATUS		0x002c
+#define VPIF_STATUS_CLR		0x0030
+
 #ifdef CONFIG_MTD
 static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
 {
@@ -452,6 +460,15 @@ static void da850_evm_ui_keys_init(unsigned gpio)
 	}
 }
 
+#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
+static inline void da850_evm_setup_video_port(int video_sel)
+{
+	gpio_set_value_cansleep(video_sel, 0);
+}
+#else
+static inline void da850_evm_setup_video_port(int video_sel) { }
+#endif
+
 static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
 						unsigned ngpio, void *c)
 {
@@ -497,6 +514,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
 
 	da850_evm_setup_emac_rmii(sel_a);
 
+	da850_evm_setup_video_port(sel_c);
+
 	return 0;
 
 exp_setup_keys_fail:
@@ -1149,6 +1168,133 @@ static __init int da850_evm_init_cpufreq(void)
 static __init int da850_evm_init_cpufreq(void) { return 0; }
 #endif
 
+#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
+
+/* VPIF capture configuration */
+static struct tvp514x_platform_data tvp5146_pdata = {
+	.clk_polarity = 0,
+	.hs_polarity = 1,
+	.vs_polarity = 1
+};
+
+#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
+
+static const struct vpif_input da850_ch0_inputs[] = {
+	{
+		.input = {
+			.index = 0,
+			.name = "Composite",
+			.type = V4L2_INPUT_TYPE_CAMERA,
+			.std = TVP514X_STD_ALL,
+		},
+		.subdev_name = TVP5147_CH0,
+	},
+};
+
+static const struct vpif_input da850_ch1_inputs[] = {
+	{
+		.input = {
+			.index = 0,
+			.name = "S-Video",
+			.type = V4L2_INPUT_TYPE_CAMERA,
+			.std = TVP514X_STD_ALL,
+		},
+		.subdev_name = TVP5147_CH1,
+	},
+};
+#endif
+
+static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
+#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
+	{
+		.name	= TVP5147_CH0,
+		.board_info = {
+			I2C_BOARD_INFO("tvp5146", 0x5d),
+			.platform_data = &tvp5146_pdata,
+		},
+		.input = INPUT_CVBS_VI2B,
+		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+		.can_route = 1,
+		.vpif_if = {
+			.if_type = VPIF_IF_BT656,
+			.hd_pol = 1,
+			.vd_pol = 1,
+			.fid_pol = 0,
+		},
+	},
+	{
+		.name	= TVP5147_CH1,
+		.board_info = {
+			I2C_BOARD_INFO("tvp5146", 0x5c),
+			.platform_data = &tvp5146_pdata,
+		},
+		.input = INPUT_SVIDEO_VI2C_VI1C,
+		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+		.can_route = 1,
+		.vpif_if = {
+			.if_type = VPIF_IF_BT656,
+			.hd_pol = 1,
+			.vd_pol = 1,
+			.fid_pol = 0,
+		},
+	},
+#endif
+};
+
+static struct vpif_capture_config da850_vpif_capture_config = {
+	.subdev_info = da850_vpif_capture_sdev_info,
+	.subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
+#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
+	.chan_config[0] = {
+		.inputs = da850_ch0_inputs,
+		.input_count = ARRAY_SIZE(da850_ch0_inputs),
+	},
+	.chan_config[1] = {
+		.inputs = da850_ch1_inputs,
+		.input_count = ARRAY_SIZE(da850_ch1_inputs),
+	},
+#endif
+	.card_name      = "DA850/OMAP-L138 Video Capture",
+};
+
+/* VPIF display configuration */
+static struct vpif_subdev_info da850_vpif_subdev[] = {
+	{
+		.name	= "adv7343",
+		.board_info = {
+			I2C_BOARD_INFO("adv7343", 0x2a),
+		},
+	},
+};
+
+static const char const *vpif_output[] = {
+	"Composite",
+	"Component",
+	"S-Video",
+};
+
+static struct vpif_display_config da850_vpif_display_config = {
+	.subdevinfo	= da850_vpif_subdev,
+	.subdev_count	= ARRAY_SIZE(da850_vpif_subdev),
+	.output		= vpif_output,
+	.output_count	= ARRAY_SIZE(vpif_output),
+	.card_name	= "DA850/OMAP-L138 Video Display",
+};
+
+#if defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY) ||\
+		defined(CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY_MODULE)
+#define HAS_VPIF_DISPLAY 1
+#else
+#define HAS_VPIF_DISPLAY 0
+#endif
+
+#if defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE) ||\
+		defined(CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE_MODULE)
+#define HAS_VPIF_CAPTURE 1
+#else
+#define HAS_VPIF_CAPTURE 0
+#endif
+
 #ifdef CONFIG_DA850_WL12XX
 
 static void wl12xx_set_power(int index, bool power_on)
@@ -1375,6 +1521,38 @@ static __init void da850_evm_init(void)
 		pr_warning("da850_evm_init: suspend registration failed: %d\n",
 				ret);
 
+	if (HAS_VPIF_DISPLAY || HAS_VPIF_CAPTURE) {
+		ret = da850_register_vpif();
+		if (ret)
+			pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
+	}
+
+	if (HAS_VPIF_CAPTURE) {
+		ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
+		if (ret)
+			pr_warn(
+			"da850_evm_init: VPIF capture mux setup failed: %d\n",
+			ret);
+
+		ret = da850_register_vpif_capture(&da850_vpif_capture_config);
+		if (ret)
+			pr_warn(
+			"da850_evm_init: VPIF capture setup failed: %d\n", ret);
+	}
+
+	if (HAS_VPIF_DISPLAY) {
+		ret = davinci_cfg_reg_list(da850_vpif_display_pins);
+		if (ret)
+			pr_warn(
+			"da850_evm_init: VPIF display mux setup failed: %d\n",
+			ret);
+
+		ret = da850_register_vpif_display(&da850_vpif_display_config);
+		if (ret)
+			pr_warn(
+			"da850_evm_init: VPIF display setup failed: %d\n", ret);
+	}
+
 	ret = da8xx_register_spi(1, da850evm_spi_info,
 				 ARRAY_SIZE(da850evm_spi_info));
 	if (ret)
-- 
1.7.0.4



From linus.walleij at linaro.org  Mon Aug 20 10:11:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:11:35 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdZvjLx4+2CpgOemwWVfyFjFbRe-pzZbwAjExqHhQqBOjA@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
(...)
> +config PINCTRL_MVEBU
> +       bool "Marvell SoC pin controller drivers"
> +       depends on ARCH_MVEBU

So altering earlier statements I suspect this should be simply:

depends on PLAT_ORION

Yours,
Linus Walleij


From m.szyprowski at samsung.com  Mon Aug 20 10:16:12 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 20 Aug 2012 16:16:12 +0200
Subject: [PATCH 0/4] Per device coherent DMA map ops
In-Reply-To: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
Message-ID: <000601cd7ede$5d2ef390$178cdab0$%szyprowski@samsung.com>

Hello,

On Tuesday, August 14, 2012 5:49 AM Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> This is series adds coherent DMA map operations which can be set per device.
> Expanding on the first RFC[1], this version adds iommu ops and implements
> support on highbank platform.
> 
> arch_is_coherent is never defined true since removing ixp2xxx, so we can
> remove it altogether.
> 
> Rob
> 
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/113921.html
> 
> Rob Herring (4):
>   ARM: add coherent dma ops
>   ARM: add coherent iommu dma ops
>   ARM: kill off arch_is_coherent
>   ARM: highbank: add coherent DMA setup
> 
>  .../devicetree/bindings/ata/ahci-platform.txt      |    3 +
>  .../devicetree/bindings/dma/arm-pl330.txt          |    3 +
>  .../devicetree/bindings/net/calxeda-xgmac.txt      |    3 +
>  arch/arm/boot/dts/highbank.dts                     |    1 +
>  arch/arm/include/asm/barrier.h                     |    7 +-
>  arch/arm/include/asm/dma-mapping.h                 |    1 +
>  arch/arm/include/asm/memory.h                      |    8 -
>  arch/arm/mach-highbank/highbank.c                  |   52 ++++
>  arch/arm/mm/dma-mapping.c                          |  254 ++++++++++++++++----
>  arch/arm/mm/mmu.c                                  |   17 +-
>  10 files changed, 271 insertions(+), 78 deletions(-)

I like those patches and I would like to take it to my dma-mapping-next tree, but I wonder 
how to handle merging of the last patch. Arnd, Olof - could You tell me how to do it? I assume
that it should be somehow merged by arm-soc tree, so it depends on the earlier patches.
Would it be enough if I take them to the topic branch? Then I can continue works on 
dma-mapping subsystem by merging that topic branch to my dma-mapping-next and you will
also take it as a dependency for highbank patches. Am I right?

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From mporter at ti.com  Mon Aug 20 10:17:21 2012
From: mporter at ti.com (Matt Porter)
Date: Mon, 20 Aug 2012 10:17:21 -0400
Subject: [PATCH 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <20120816222912.GA15883@n2100.arm.linux.org.uk>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
 <1345153471-22757-2-git-send-email-mporter@ti.com>
 <20120816222912.GA15883@n2100.arm.linux.org.uk>
Message-ID: <20120820141721.GA31897@beef>

On Thu, Aug 16, 2012 at 11:29:12PM +0100, Russell King wrote:
> On Thu, Aug 16, 2012 at 05:44:29PM -0400, Matt Porter wrote:
> > Add a DMA engine driver for the TI EDMA controller. This driver
> > is implemented as a wrapper around the existing DaVinci private
> > DMA implementation. This approach allows for incremental conversion
> > of each peripheral driver to the DMA engine API. The EDMA driver
> > supports slave transfers but does not yet support cyclic transfers.
> 
> Have you looked at the virt-dma support?  That should allow you to
> avoid some common errors, like forgetting that stuff submitted but
> not issued should not be started even if the channel is currently
> running.

I had previously skimmed it a bit and wrote it off as a helper for
certain types of controllers. On your suggestion, I looked into it
in detail and it does look to be a nice improvement on handling those
types of errors...some of which I noticed were not being handled
properly in my v1 version. I did a quick and dirty conversion of the
EDMA driver to use virt-dma now and it also results in simplified
handling of the descriptors and about a 10% code reduction. I'll do
some clean up on this virt-dma-enabled version and post v2.

One thing to note is that although I'm borrowing a lot from how you
did the omap-dma.c driver, the EDMA implementation of issue_pending()
cannot schedule a tasklet to send the descriptor to the hardware. The
client drivers have to be sure that dma_async_issue_pending() results
in the PaRAM set been written to the h/w before the driver specific
DMA reqs are enabled. Enabling the DMA req before the PaRAM set is
programmed results in an event error condition on this h/w. Ideally
there would be a dma_status state to reflect that a descriptor has
actually been written to the h/w so that client drivers can safely
enable dma reqs where this is a requirement.

Thanks,
Matt


From linus.walleij at linaro.org  Mon Aug 20 10:18:15 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:18:15 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
 <CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>
Message-ID: <CACRpkdaozBQPe1PkjaKrnqYZ=tpX1mv1iS-rCrJaSFAsQqzgnA@mail.gmail.com>

On Mon, Aug 20, 2012 at 11:46 AM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:
> On 8/20/12, Linus Walleij <linus.walleij at linaro.org> wrote:

>> Are you taking this patch series through some Marvell tree or do you want
>> me to carry it in the pinctrl tree?
>
> I think it would be better to take it through the Marvell tree of Jason
> Cooper. It is only for Marvell SoCs anyway.

OK.

>> There is some other "variant" field elsewhere that is
>> a u8, is this correct? In this and the other case, should
>> this "variant" rather be an enum?
>
> I'll review the variant types but inside pinctrl-mvebu variant
> is used as a bit mask to distinguish different variants. Anyway,
> they should always be the same size.

Aha bitmask, seems you can only have 8 different variants of
the Marvell's then?

>> Is it possible to use devm_* managed devm_kzalloc() for this map
>> so you don't need to free it explicitly?
>>
>> (Maybe not, just checking.)
>
> Hmm, I guess not as I thought I've read not to use devm_kfree when
> you allocate _and_ free stuff on runtime without removing the device
> itself, right?

You're right.

>> So, there will never be > 256 pins on a Marvell platform?
>
> Well, with all current platforms we are well below 100. I guess
> 256 max (muxable) pins will be enough.

OK.

>>> + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
>>> + * @val: ctrl setting value
>>
>> It is not obvious to me what this means, it it possible to elaborate
>> on how this member is defined and used?
>
> Well, I see if I can clarify the description but wrt the datasheet it
> _should_ be quite obvious.

I mainly worry about being able to read the code and figure out
what's going on, if the datasheet is vital then pls include some
link to it or so in the header of the file (but preferrably the code
should speak for itself).

>>> + * @variant: (optional) variant identifier mask
>>
>> This thing again, there are lots of "variants" around here.
>> Is it a candidate for an enum?
>
> As it is a mask, I don't think enum fits here.

OK. No big deal anyway.

> In some internal review with Andrew I also added a spinlock to
> mvebu_pinconf_get/_set that will protect all calls to generic and specific
> _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove
> with the devm_ counterpart and removed the explicit clk_put.

I had some separate comments on that clk thing...
Anyway, looking forward to v2, this is progressing quickly
I think.

Yours,
Linus Walleij


From shawn.guo at linaro.org  Mon Aug 20 10:19:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:54 +0800
Subject: [PATCH 0/6] Enable SPARSE_IRQ for mach-mxs
Message-ID: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>

The series adopts irq_domain support for mxs icoll and gpio drivers,
enables SPARSE_IRQ, and remove mach/irqs.h for mach-mxs.

As the series depends on mxs/dt branch, I plan to have it go via arm-soc
tree with Linus' ack on the first patch.

Shawn Guo (6):
  gpio/mxs: adopt irq_domain support for mxs gpio driver
  ARM: mxs: retrieve timer irq from device tree
  ARM: mxs: select MULTI_IRQ_HANDLER
  ARM: mxs: adopt irq_domain support for icoll driver
  ARM: mxs: select SPARSE_IRQ
  ARM: mxs: remove mach/irqs.h

 arch/arm/Kconfig                             |    2 +
 arch/arm/boot/dts/imx23.dtsi                 |    5 +-
 arch/arm/boot/dts/imx28.dtsi                 |    5 +-
 arch/arm/mach-mxs/icoll.c                    |   63 ++++++++++++++++++++++----
 arch/arm/mach-mxs/include/mach/common.h      |    3 +-
 arch/arm/mach-mxs/include/mach/entry-macro.S |   35 --------------
 arch/arm/mach-mxs/include/mach/irqs.h        |   32 -------------
 arch/arm/mach-mxs/mach-mxs.c                 |   39 ++--------------
 arch/arm/mach-mxs/timer.c                    |   13 +++++-
 drivers/clk/mxs/clk-imx23.c                  |    2 +-
 drivers/clk/mxs/clk-imx28.c                  |    2 +-
 drivers/gpio/gpio-mxs.c                      |   48 ++++++++++++-------
 12 files changed, 112 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-mxs/include/mach/irqs.h

-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:19:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:55 +0800
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>

Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
driver adopt irqdomain support, so that we can have the mapping
between gpio and irq number available without using virtual_irq_start
and MXS_GPIO_IRQ_START.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-mxs/mach-mxs.c |   12 ----------
 drivers/gpio/gpio-mxs.c      |   48 ++++++++++++++++++++++++++---------------
 2 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 3b0d9c6..9f8406e 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -149,20 +149,8 @@ static int __init mxs_icoll_add_irq_domain(struct device_node *np,
 	return 0;
 }
 
-static int __init mxs_gpio_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	static int gpio_irq_base = MXS_GPIO_IRQ_START;
-
-	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-	gpio_irq_base += 32;
-
-	return 0;
-}
-
 static const struct of_device_id mxs_irq_match[] __initconst = {
 	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
-	{ .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 39e4956..796fb13 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -52,8 +53,6 @@
 #define GPIO_INT_LEV_MASK	(1 << 0)
 #define GPIO_INT_POL_MASK	(1 << 1)
 
-#define irq_to_gpio(irq)	((irq) - MXS_GPIO_IRQ_START)
-
 enum mxs_gpio_id {
 	IMX23_GPIO,
 	IMX28_GPIO,
@@ -63,7 +62,7 @@ struct mxs_gpio_port {
 	void __iomem *base;
 	int id;
 	int irq;
-	int virtual_irq_start;
+	struct irq_domain *domain;
 	struct bgpio_chip bgc;
 	enum mxs_gpio_id devid;
 };
@@ -82,8 +81,7 @@ static inline int is_imx28_gpio(struct mxs_gpio_port *port)
 
 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
-	u32 gpio = irq_to_gpio(d->irq);
-	u32 pin_mask = 1 << (gpio & 31);
+	u32 pin_mask = 1 << d->hwirq;
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 	struct mxs_gpio_port *port = gc->private;
 	void __iomem *pin_addr;
@@ -120,7 +118,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 	else
 		writel(pin_mask, pin_addr + MXS_CLR);
 
-	writel(1 << (gpio & 0x1f),
+	writel(pin_mask,
 	       port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 
 	return 0;
@@ -131,7 +129,6 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
 	u32 irq_stat;
 	struct mxs_gpio_port *port = irq_get_handler_data(irq);
-	u32 gpio_irq_no_base = port->virtual_irq_start;
 
 	desc->irq_data.chip->irq_ack(&desc->irq_data);
 
@@ -140,7 +137,7 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 
 	while (irq_stat != 0) {
 		int irqoffset = fls(irq_stat) - 1;
-		generic_handle_irq(gpio_irq_no_base + irqoffset);
+		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 		irq_stat &= ~(1 << irqoffset);
 	}
 }
@@ -167,12 +164,12 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 	return 0;
 }
 
-static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
+static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 {
 	struct irq_chip_generic *gc;
 	struct irq_chip_type *ct;
 
-	gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
+	gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
 				    port->base, handle_level_irq);
 	gc->private = port;
 
@@ -194,7 +191,7 @@ static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 	struct mxs_gpio_port *port =
 		container_of(bgc, struct mxs_gpio_port, bgc);
 
-	return port->virtual_irq_start + offset;
+	return irq_find_mapping(port->domain, offset);
 }
 
 static struct platform_device_id mxs_gpio_ids[] = {
@@ -226,6 +223,7 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 	static void __iomem *base;
 	struct mxs_gpio_port *port;
 	struct resource *iores = NULL;
+	int irq_base;
 	int err;
 
 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
@@ -241,7 +239,6 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 		port->id = pdev->id;
 		port->devid = pdev->id_entry->driver_data;
 	}
-	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 
 	port->irq = platform_get_irq(pdev, 0);
 	if (port->irq < 0)
@@ -275,8 +272,19 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 	/* clear address has to be used to clear IRQSTAT bits */
 	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 
+	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+	if (irq_base < 0)
+		return irq_base;
+
+	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
+					     &irq_domain_simple_ops, NULL);
+	if (!port->domain) {
+		err = -ENODEV;
+		goto out_irqdesc_free;
+	}
+
 	/* gpio-mxs can be a generic irq chip */
-	mxs_gpio_init_gc(port);
+	mxs_gpio_init_gc(port, irq_base);
 
 	/* setup one handler for each entry */
 	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
@@ -287,18 +295,22 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 			 port->base + PINCTRL_DOUT(port), NULL,
 			 port->base + PINCTRL_DOE(port), NULL, 0);
 	if (err)
-		return err;
+		goto out_irqdesc_free;
 
 	port->bgc.gc.to_irq = mxs_gpio_to_irq;
 	port->bgc.gc.base = port->id * 32;
 
 	err = gpiochip_add(&port->bgc.gc);
-	if (err) {
-		bgpio_remove(&port->bgc);
-		return err;
-	}
+	if (err)
+		goto out_bgpio_remove;
 
 	return 0;
+
+out_bgpio_remove:
+	bgpio_remove(&port->bgc);
+out_irqdesc_free:
+	irq_free_descs(irq_base, 32);
+	return err;
 }
 
 static struct platform_driver mxs_gpio_driver = {
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:19:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:56 +0800
Subject: [PATCH 2/6] ARM: mxs: retrieve timer irq from device tree
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-3-git-send-email-shawn.guo@linaro.org>

Rather than using the static timer irq definition, we should retrieve
timer irq from device tree for better.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx23.dtsi            |    3 ++-
 arch/arm/boot/dts/imx28.dtsi            |    3 ++-
 arch/arm/mach-mxs/include/mach/common.h |    2 +-
 arch/arm/mach-mxs/timer.c               |   13 ++++++++++++-
 drivers/clk/mxs/clk-imx23.c             |    2 +-
 drivers/clk/mxs/clk-imx28.c             |    2 +-
 6 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 9700872..2672dcf 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -400,8 +400,9 @@
 			};
 
 			timrot at 80068000 {
+				compatible = "fsl,imx23-timrot", "fsl,timrot";
 				reg = <0x80068000 0x2000>;
-				status = "disabled";
+				interrupts = <28 29 30 31>;
 			};
 
 			auart0: serial at 8006c000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e2240da..f8b145a 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -686,8 +686,9 @@
 			};
 
 			timrot at 80068000 {
+				compatible = "fsl,imx28-timrot", "fsl,timrot";
 				reg = <0x80068000 0x2000>;
-				status = "disabled";
+				interrupts = <48 49 50 51>;
 			};
 
 			auart0: serial at 8006a000 {
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 4dec795..6798be5 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,7 +13,7 @@
 
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(int);
+extern void mxs_timer_init(void);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 02d36de..7c37926 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -25,6 +25,8 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 #include <mach/mxs.h>
@@ -244,9 +246,17 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
 	return 0;
 }
 
-void __init mxs_timer_init(int irq)
+void __init mxs_timer_init(void)
 {
+	struct device_node *np;
 	struct clk *timer_clk;
+	int irq;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
+	if (!np) {
+		pr_err("%s: failed find timrot node\n", __func__);
+		return;
+	}
 
 	timer_clk = clk_get_sys("timrot", NULL);
 	if (IS_ERR(timer_clk)) {
@@ -295,5 +305,6 @@ void __init mxs_timer_init(int irq)
 	mxs_clockevent_init(timer_clk);
 
 	/* Make irqs happen */
+	irq = irq_of_parse_and_map(np, 0);
 	setup_irq(irq, &mxs_timer_irq);
 }
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0..e0dc3f8 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -200,7 +200,7 @@ int __init mx23_clocks_init(void)
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
 
-	mxs_timer_init(MX23_INT_TIMER0);
+	mxs_timer_init();
 
 	return 0;
 }
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67..9df864d 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -337,7 +337,7 @@ int __init mx28_clocks_init(void)
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
 
-	mxs_timer_init(MX28_INT_TIMER0);
+	mxs_timer_init();
 
 	return 0;
 }
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:19:57 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:57 +0800
Subject: [PATCH 3/6] ARM: mxs: select MULTI_IRQ_HANDLER
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-4-git-send-email-shawn.guo@linaro.org>

As part of multi-platform effort, let's enable MULTI_IRQ_HANDLER for
mach-mxs and remove entry-macro.S.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/Kconfig                             |    1 +
 arch/arm/mach-mxs/icoll.c                    |   18 ++++++++++++-
 arch/arm/mach-mxs/include/mach/common.h      |    1 +
 arch/arm/mach-mxs/include/mach/entry-macro.S |   35 --------------------------
 arch/arm/mach-mxs/mach-mxs.c                 |    2 +
 5 files changed, 21 insertions(+), 36 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/include/mach/entry-macro.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..7207086 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -489,6 +489,7 @@ config ARCH_MXS
 	select CLKSRC_MMIO
 	select COMMON_CLK
 	select HAVE_CLK_PREPARE
+	select MULTI_IRQ_HANDLER
 	select PINCTRL
 	select USE_OF
 	help
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 23ca9d0..a11b618 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -20,13 +20,14 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-
+#include <asm/exception.h>
 #include <mach/mxs.h>
 #include <mach/common.h>
 
 #define HW_ICOLL_VECTOR				0x0000
 #define HW_ICOLL_LEVELACK			0x0010
 #define HW_ICOLL_CTRL				0x0020
+#define HW_ICOLL_STAT_OFFSET			0x0070
 #define HW_ICOLL_INTERRUPTn_SET(n)		(0x0124 + (n) * 0x10)
 #define HW_ICOLL_INTERRUPTn_CLR(n)		(0x0128 + (n) * 0x10)
 #define BM_ICOLL_INTERRUPTn_ENABLE		0x00000004
@@ -63,6 +64,21 @@ static struct irq_chip mxs_icoll_chip = {
 	.irq_unmask = icoll_unmask_irq,
 };
 
+asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
+{
+	u32 irqnr;
+
+	do {
+		irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+		if (irqnr != 0x7f) {
+			__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 void __init icoll_init_irq(void)
 {
 	int i;
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 6798be5..be5a9c9 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -24,5 +24,6 @@ extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
 
 extern void icoll_init_irq(void);
+extern void icoll_handle_irq(struct pt_regs *);
 
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
deleted file mode 100644
index 0c14259..0000000
--- a/arch/arm/mach-mxs/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Low-level IRQ helper macros for Freescale MXS-based
- *
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <mach/mxs.h>
-
-#define MXS_ICOLL_VBASE		MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
-#define HW_ICOLL_STAT_OFFSET	0x70
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	ldr	\irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
-	cmp	\irqnr, #0x7F
-	strne	\irqnr, [\base]
-	moveqs	\irqnr, #0
-	.endm
-
-	.macro  get_irqnr_preamble, base, tmp
-	ldr	\base, =MXS_ICOLL_VBASE
-	.endm
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 9f8406e..d238eb0 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -413,6 +413,7 @@ static const char *imx28_dt_compat[] __initdata = {
 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
 	.map_io		= mx23_map_io,
 	.init_irq	= mxs_dt_init_irq,
+	.handle_irq	= icoll_handle_irq,
 	.timer		= &imx23_timer,
 	.init_machine	= mxs_machine_init,
 	.dt_compat	= imx23_dt_compat,
@@ -422,6 +423,7 @@ MACHINE_END
 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
 	.map_io		= mx28_map_io,
 	.init_irq	= mxs_dt_init_irq,
+	.handle_irq	= icoll_handle_irq,
 	.timer		= &imx28_timer,
 	.init_machine	= mxs_machine_init,
 	.dt_compat	= imx28_dt_compat,
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:19:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:58 +0800
Subject: [PATCH 4/6] ARM: mxs: adopt irq_domain support for icoll driver
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-5-git-send-email-shawn.guo@linaro.org>

Remove irq_domain_add_legacy call from mach-mxs.c and have icoll adopt
irq_domain support in the driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx23.dtsi |    2 +-
 arch/arm/boot/dts/imx28.dtsi |    2 +-
 arch/arm/mach-mxs/icoll.c    |   45 ++++++++++++++++++++++++++++++++++-------
 arch/arm/mach-mxs/mach-mxs.c |   25 +---------------------
 4 files changed, 41 insertions(+), 33 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 2672dcf..8de4eb2 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -43,7 +43,7 @@
 			ranges;
 
 			icoll: interrupt-controller at 80000000 {
-				compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
+				compatible = "fsl,imx23-icoll", "fsl,icoll";
 				interrupt-controller;
 				#interrupt-cells = <1>;
 				reg = <0x80000000 0x2000>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index f8b145a..bed5c48 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -50,7 +50,7 @@
 			ranges;
 
 			icoll: interrupt-controller at 80000000 {
-				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+				compatible = "fsl,imx28-icoll", "fsl,icoll";
 				interrupt-controller;
 				#interrupt-cells = <1>;
 				reg = <0x80000000 0x2000>;
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index a11b618..8fb23af 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -19,7 +19,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 #include <asm/exception.h>
 #include <mach/mxs.h>
 #include <mach/common.h>
@@ -33,7 +36,10 @@
 #define BM_ICOLL_INTERRUPTn_ENABLE		0x00000004
 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0	0x1
 
+#define ICOLL_NUM_IRQS		128
+
 static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+static struct irq_domain *icoll_domain;
 
 static void icoll_ack_irq(struct irq_data *d)
 {
@@ -49,13 +55,13 @@ static void icoll_ack_irq(struct irq_data *d)
 static void icoll_mask_irq(struct irq_data *d)
 {
 	__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-			icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->irq));
+			icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
 }
 
 static void icoll_unmask_irq(struct irq_data *d)
 {
 	__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-			icoll_base + HW_ICOLL_INTERRUPTn_SET(d->irq));
+			icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
 }
 
 static struct irq_chip mxs_icoll_chip = {
@@ -72,6 +78,7 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 		irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
 		if (irqnr != 0x7f) {
 			__raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+			irqnr = irq_find_mapping(icoll_domain, irqnr);
 			handle_IRQ(irqnr, regs);
 			continue;
 		}
@@ -79,18 +86,40 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 	} while (1);
 }
 
-void __init icoll_init_irq(void)
+static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
+				irq_hw_number_t hw)
 {
-	int i;
+	irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
+
+	return 0;
+}
 
+static struct irq_domain_ops icoll_irq_domain_ops = {
+	.map = icoll_irq_domain_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+void __init icoll_of_init(struct device_node *np,
+			  struct device_node *interrupt_parent)
+{
 	/*
 	 * Interrupt Collector reset, which initializes the priority
 	 * for each irq to level 0.
 	 */
 	mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
 
-	for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
-		irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
+	icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
+					     &icoll_irq_domain_ops, NULL);
+	WARN_ON(!icoll_domain);
+}
+
+static const struct of_device_id icoll_of_match[] __initconst = {
+	{.compatible = "fsl,icoll", .data = icoll_of_init},
+	{ /* sentinel */ }
+};
+
+void __init icoll_init_irq(void)
+{
+	of_irq_init(icoll_of_match);
 }
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index d238eb0..a1fb04d 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -17,10 +17,8 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
@@ -141,25 +139,6 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
 	{ /* sentinel */ }
 };
 
-static int __init mxs_icoll_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-
-	return 0;
-}
-
-static const struct of_device_id mxs_irq_match[] __initconst = {
-	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
-	{ /* sentinel */ }
-};
-
-static void __init mxs_dt_init_irq(void)
-{
-	icoll_init_irq();
-	of_irq_init(mxs_irq_match);
-}
-
 static void __init imx23_timer_init(void)
 {
 	mx23_clocks_init();
@@ -412,7 +391,7 @@ static const char *imx28_dt_compat[] __initdata = {
 
 DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
 	.map_io		= mx23_map_io,
-	.init_irq	= mxs_dt_init_irq,
+	.init_irq	= icoll_init_irq,
 	.handle_irq	= icoll_handle_irq,
 	.timer		= &imx23_timer,
 	.init_machine	= mxs_machine_init,
@@ -422,7 +401,7 @@ MACHINE_END
 
 DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
 	.map_io		= mx28_map_io,
-	.init_irq	= mxs_dt_init_irq,
+	.init_irq	= icoll_init_irq,
 	.handle_irq	= icoll_handle_irq,
 	.timer		= &imx28_timer,
 	.init_machine	= mxs_machine_init,
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:19:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:19:59 +0800
Subject: [PATCH 5/6] ARM: mxs: select SPARSE_IRQ
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-6-git-send-email-shawn.guo@linaro.org>

With icoll and gpio interrupt controllers adopt irqdomain support and
all interrupt nubmers are retrieved from device tree, it's save to
select SPARSE_IRQ for mxs now.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7207086..58bffb3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -491,6 +491,7 @@ config ARCH_MXS
 	select HAVE_CLK_PREPARE
 	select MULTI_IRQ_HANDLER
 	select PINCTRL
+	select SPARSE_IRQ
 	select USE_OF
 	help
 	  Support for Freescale MXS-based family of processors
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:20:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:20:00 +0800
Subject: [PATCH 6/6] ARM: mxs: remove mach/irqs.h
In-Reply-To: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345472400-31262-7-git-send-email-shawn.guo@linaro.org>

With SPARSE_IRQ adopted for mach-mxs, header mach/irqs.h is needed
nowhere now, so remove it.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-mxs/include/mach/irqs.h |   32 --------------------------------
 1 files changed, 0 insertions(+), 32 deletions(-)
 delete mode 100644 arch/arm/mach-mxs/include/mach/irqs.h

diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
deleted file mode 100644
index f771039..0000000
--- a/arch/arm/mach-mxs/include/mach/irqs.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_IRQS_H__
-#define __MACH_MXS_IRQS_H__
-
-#define MXS_INTERNAL_IRQS	128
-
-#define MXS_GPIO_IRQ_START	MXS_INTERNAL_IRQS
-
-/* the maximum for MXS-based */
-#define MXS_GPIO_IRQS		(32 * 5)
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase MXS_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXS_BOARD_IRQ_START	(MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
-#define MXS_BOARD_IRQS		16
-
-#define NR_IRQS			(MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
-
-#endif /* __MACH_MXS_IRQS_H__ */
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Aug 20 10:24:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:24:24 +0800
Subject: [PATCH 5/6] ARM: mxs: select SPARSE_IRQ
In-Reply-To: <1345472400-31262-6-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-6-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120820142422.GK24242@S2101-09.ap.freescale.net>

On Mon, Aug 20, 2012 at 10:19:59PM +0800, Shawn Guo wrote:
> With icoll and gpio interrupt controllers adopt irqdomain support and
> all interrupt nubmers are retrieved from device tree, it's save to

s/save/safe

> select SPARSE_IRQ for mxs now.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>


From linus.walleij at linaro.org  Mon Aug 20 10:25:05 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:25:05 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> This pinctrl driver is not a full-blown pinctrl driver from scratch:
> it relies on the common pinctrl-mvebu driver, which is used for all
> Marvell EBU SoCs.

Good!

> +config PINCTRL_ARMADA_370
> +       bool "Support for Marvell Armada 370 SoCs"
> +       depends on PINCTRL_MVEBU
> +       depends on MACH_ARMADA_370_XP

select PINCTRL_MVEBU simply?

And then have the Armada Kconfig

select PINCTRL
select PINCTRL_ARMADA_370

This machine doesn't seem to depend in the MVEBU driver, I guess it's
the same ARCH as something else, oh well. Still suspect the
MVEBU driver should depend on PLAT_ORION until proven
wrong.

(...)
> +static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
> +{
> +       struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
> +
> +       soc->variant = 0;

Shouldn't this be a #defined thing or something. "variant 0" doesn't
tell me much.

No further comments, looking good.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:26:24 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:26:24 +0200
Subject: [PATCH 05/11] pinctrl: mvebu: add pinctrl driver for Armada XP
In-Reply-To: <1344689809-6223-6-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-6-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdaP10PBREYO4OLvzCeKQLctup6+Upty4GWRzRZwsa+ReA@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> This pinctrl driver is not a full-blown pinctrl driver from scratch:
> it relies on the common pinctrl-mvebu driver, which is used for all
> Marvell EBU SoCs.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Same comments as on the previous driver, no further comments,
and looking good.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:27:05 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:27:05 +0200
Subject: [PATCH 06/11] ARM: mvebu: add pinctrl device in DT for Armada
 370/XP SoCs
In-Reply-To: <1344689809-6223-7-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-7-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdaWKf2se6PE7SMoOoqbTCLaMBMgjKbJa5tpQzr-RTSmJg@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> The Armada 370 and XP SoCs have configurable muxing for a certain
> number of their pins, controlled through a pinctrl driver.
>
> The 'compatible' property is defined in the SoC-specific .dtsi files,
> since the compatible string identifies the number of pins and other
> SoC-specific properties.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:27:41 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:27:41 +0200
Subject: [PATCH 07/11] ARM: mvebu: Add pinctrl support to Armada XP SoCs
In-Reply-To: <1344689809-6223-8-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-8-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdbNpeBLy-JmUz-YjFYVZfAw3mavUAWigLKyXU=iQ_wMSQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada XP SoCs.
>
> Until now, the device tree representation considered the Armada XP as
> a single SoC. But in fact, there are three different SoCs in the
> Armada XP families, with different number of CPU cores, different
> number of Ethernet interfaces... and different number of muxable pins
> or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
> the three SoCs of the Armada XP family. The current armada-xp-db.dts
> evaluation board uses the MV78460 variant of the SoC.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:28:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:28:00 +0200
Subject: [PATCH 08/11] ARM: mvebu: Add pinctrl support to Armada 370 SoC
In-Reply-To: <1344689809-6223-9-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-9-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkda_tac95mYmw9y6dW-0TS4P5Fknji11E39_TUPjp0Tw2w@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada 370 SoC.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:28:17 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:28:17 +0200
Subject: [PATCH 09/11] ARM: mvebu: adjust Armada XP evaluation board DTS
In-Reply-To: <1344689809-6223-10-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-10-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdb5+FuFU3pqkZosiTuhp=6Yr5rqcTng072+KDkUh=J5ag@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> The Armada XP evaluation board is based on the MV78460 Armava XP
> SoC. Now that we have separate .dtsi files for the three different
> SoCs of the Armada XP family, use the appropriate one as include for
> the Armada XP evaluation board .dts file.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From alanbutty12 at gmail.com  Mon Aug 20 10:29:07 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 15:29:07 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega ix2-200 DT support Signed-off-by: Alan
 M Butler <alanbutty12@gmail.com>
In-Reply-To: <cover.1345472556.git.alanbutty12@gmail.com>
References: <cover.1345472556.git.alanbutty12@gmail.com>
Message-ID: <2b8d12ce68911cc12c96dcdd60c3345b72d25780.1345472556.git.alanbutty12@gmail.com>

Patch version 5.
Add support for the Iomega ix2-200.
Led's and buttons working as of kernel 3.6-rc2

the 3 lines in the network interface do seem to be required as
removing either causes the network card to not be able to reach
the network (at least on my device).

Product page:
http://go.iomega.com/en/products/network-storage-desktop/storcenter-network-storage-solution/network-hard-drive-ix2-200-cloud/?partner=4735#tech_specsItem_tab

Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

---
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/Kconfig                |    7 ++
 arch/arm/mach-kirkwood/Makefile               |    1 +
 arch/arm/mach-kirkwood/Makefile.boot          |    1 +
 arch/arm/mach-kirkwood/board-dt.c             |    4 +
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   57 ++++++++++++++
 arch/arm/mach-kirkwood/common.h               |    6 ++
 7 files changed, 181 insertions(+)
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c

diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 0000000..865aeec
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Iomega StorCenter ix2-200";
+	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		i2c at 11000 {
+			status = "okay";
+
+			lm63: lm63 at 4c {
+				compatible = "national,lm63";
+				reg = <0x4c>;
+			};
+		};
+
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at a0000 {
+				label = "env";
+				reg = <0xa0000 0x20000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x100000 0x300000>;
+			};
+
+			partition at 400000 {
+				label = "uInitrd";
+				reg = <0x540000 0x1000000>;
+			};
+		};
+		sata at 80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			label = "status:white:power_led";
+			gpios = <&gpio0 16 0>;
+			linux,default-trigger = "default-on";
+		};
+		health_led1 {
+			label = "status:red:health_led";
+			gpios = <&gpio1 5 0>;
+		};
+		health_led2 {
+			label = "status:white:health_led";
+			gpios = <&gpio1 4 0>;
+		};
+		backup_led {
+			label = "status:blue:backup_led";
+			gpios = <&gpio0 15 0>;
+		};
+	};
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		Power {
+			label = "Power Button";
+			linux,code = <116>;
+			gpios = <&gpio0 14 1>;
+		};
+		Reset {
+			label = "Reset Button";
+			linux,code = <0x198>;
+			gpios = <&gpio0 12 1>;
+		};
+		OTB {
+			label = "OTB Button";
+			linux,code = <133>;
+			gpios = <&gpio1 3 1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..bee8451 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -195,6 +195,13 @@ config MACH_T5325
 	  Say 'Y' here if you want your kernel to support the
 	  HP t5325 Thin Client.
 
+config MACH_IOMEGA_IX2_200_DT
+	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Iomega StorCenter ix2-200 (Flattened Device Tree).
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..f5484dc 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a571755..59b719d 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..9b3ec17 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
+	if (of_machine_is_compatible("iom,ix2-200"))
+		iomega_ix2_200_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"iom,ix2-200",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 0000000..158fb97
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+	.phy_addr       = MV643XX_ETH_PHY_NONE,
+	.speed          = SPEED_1000,
+	.duplex         = DUPLEX_FULL,
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+	MPP12_GPIO,			/* Reset Button */
+	MPP14_GPIO,			/* Power Button */
+	MPP15_GPIO,			/* Backup LED (blue) */
+	MPP16_GPIO,			/* Power LED (white) */
+	MPP35_GPIO,			/* OTB Button */
+	MPP36_GPIO,			/* Rebuild LED (white) */
+	MPP37_GPIO,			/* Health LED (red) */
+	MPP38_GPIO,			/* SATA LED brightness control 1 */
+	MPP39_GPIO,			/* SATA LED brightness control 2 */
+	MPP40_GPIO,			/* Backup LED brightness control 1 */
+	MPP41_GPIO,			/* Backup LED brightness control 2 */
+	MPP42_GPIO,			/* Power LED brightness control 1 */
+	MPP43_GPIO,			/* Power LED brightness control 2 */
+	MPP44_GPIO,			/* Health LED brightness control 1 */
+	MPP45_GPIO,			/* Health LED brightness control 2 */
+	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
+	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
+	0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+	kirkwood_ehci_init();
+
+	kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..d5d4064 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.9.5



From linus.walleij at linaro.org  Mon Aug 20 10:29:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:29:55 +0200
Subject: [PATCH 10/11] arm: mvebu: enable PINCTRL usage
In-Reply-To: <1344689809-6223-11-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-11-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkda+X5-GtsMJ07TA7UBbbk1W+pJzTtQjQJ8VPD9z_5UoDQ@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
>
> Now that we have a proper pinctrl driver for Marvell EBU platforms,
> enable PINCTRL support in ARCH_MVEBU.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

(...)
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 361f513..95317a9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -573,6 +573,7 @@ config ARCH_MVEBU
>         select GENERIC_IRQ_CHIP
>         select IRQ_DOMAIN
>         select COMMON_CLK
> +       select PINCTRL
>         help
>           Support for the Marvell SoC Family with device tree support

So this symbol collects all the DT-migrated platforms?

Probably OK but want to figure out if the PLAT_NOMADIK symbol
is applicable.

Yours,
Linus Walleij


From shawn.guo at linaro.org  Mon Aug 20 10:30:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 22:30:44 +0800
Subject: [PATCH 1/2] clk: add of_clk_src_onecell_get() support
In-Reply-To: <1345104526-14797-2-git-send-email-shawn.guo@linaro.org>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120820143042.GL24242@S2101-09.ap.freescale.net>

On Thu, Aug 16, 2012 at 04:08:45PM +0800, Shawn Guo wrote:
> For those SoCs that have hundreds of clock outputs, their clock
> DT bindings could reasonably define #clock-cells as 1 and require
> the client device specify the index of the clock it consumes in the
> cell of its "clocks" phandle.
> 
> Add a generic of_clk_src_onecell_get() function for this purpose.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/clk/clk.c            |   15 +++++++++++++++
>  include/linux/clk-provider.h |    1 +
>  2 files changed, 16 insertions(+), 0 deletions(-)
> 
Mike,

Can you please apply this patch on clk tree if it looks good to you?
I plan to ask arm-soc people pull in clk tree as dependency and then
have the other 3 patches in the series to go via arm-soc tree.

Regards,
Shawn


From linus.walleij at linaro.org  Mon Aug 20 10:31:25 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:31:25 +0200
Subject: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig
In-Reply-To: <1344689809-6223-12-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-12-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <CACRpkdaF3OuBLC7odWyH5C_EJT9uFq1rYQMh6=kr8PQjvA68sA@mail.gmail.com>

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
<sebastian.hesselbarth at gmail.com> wrote:

> diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
> index 2e86b31..cb07e64 100644
> --- a/arch/arm/configs/mvebu_defconfig
> +++ b/arch/arm/configs/mvebu_defconfig
> @@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>  CONFIG_SERIAL_8250=y
>  CONFIG_SERIAL_8250_CONSOLE=y
>  CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_PINCTRL_ARMADA_370=y
> +CONFIG_PINCTRL_ARMADA_XP=y

If the system is not even booting without pinctrl you should
(IMHO) select these from the machine's Kconfig entry insteaf.

If they boot fine without I'm fine with this ... the arch maintainer
gets to choose anyway.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:32:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:32:13 +0200
Subject: [PATCH 2/5] Documentation: add description of DT binding for the
 gpio-mvebu driver
In-Reply-To: <1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <CACRpkdaimkvGbgj2u3o=tqpdgjFgxHZxpLswQdvAi6cTWm4kAw@mail.gmail.com>

On Sat, Aug 11, 2012 at 3:31 PM, Thomas Petazzoni
<thomas.petazzoni at free-electrons.com> wrote:

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 20 10:34:11 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 20 Aug 2012 16:34:11 +0200
Subject: [PATCH 12/22] ARM: ux500: Add AB8500 CODEC node to DB8500 Device
 Tree
In-Reply-To: <1344527268-5964-13-git-send-email-lee.jones@linaro.org>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-13-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZU3NKmrM+MboJrk7nsmENc2B=acfsRobU0F-Zk1kGZcg@mail.gmail.com>

On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Ensure correct probing and pass though important configuration
> options to the AB8500 CODEC driver when DT is enabled
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

FWIW:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

But I think Ola and Marks ACKS are more important on this one.

Yours,
Linus Walleij


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 10:36:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 15:36:53 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <20120820113427.GN8450@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de> <20120820113427.GN8450@gmail.com>
Message-ID: <20120820143653.GE26991@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 12:34:31PM +0100, Lee Jones wrote:
> From: Lee Jones <lee.jones at linaro.org>
> Date: Fri, 27 Jul 2012 08:50:05 +0100
> Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
> 
> We continue to allow the AB8500 CODEC to be registered via the AB8500
> Multi Functional Device API, only this time we extract its configuration
> from the Device Tree binary.

Please resend this series with all the acks you've got rather than
mixing incremental updates in like this.  Please also send patches in
the format documented in SubmittingPatches.
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From wade_farnsworth at mentor.com  Mon Aug 20 10:38:37 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 20 Aug 2012 07:38:37 -0700
Subject: [PATCH v3] ARM: support syscall tracing
Message-ID: <50324BED.9000500@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
syscall_trace_{enter,exit} were modified to call trace_sys_{enter,exit}
as appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
---
This patch is an update of one I posted some months ago.  It has been
rebased to Linus's current master branch.
- v2: Implemented changes suggested by Will:
  - Folded _TIF_SYSCALL_TRACEPOINT into _TIF_SYSCALL_WORK to save an
    instruction in entry-common.S.
  - Moved calls to trace_sys_{enter,exit} to syscall_trace_{enter,exit}
- v3:
  - Set current_thread_info()->syscall before checking TIF_SYSCALL_TRACE.
  - Pass the original syscall number into trace_sys_{enter,exit}, not
    the return value from ptrace_syscall_trace().
 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    4 +++-
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |   11 ++++++++++-
 arch/arm/kernel/ptrace.c           |   11 +++++++++--
 6 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..983e9eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bd..5ded667 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -148,6 +148,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
 #define TIF_SYSCALL_TRACE	8
 #define TIF_SYSCALL_AUDIT	9
+#define TIF_SYSCALL_TRACEPOINT	10
 #define TIF_POLLING_NRFLAG	16
 #define TIF_USING_IWMMXT	17
 #define TIF_MEMDIE		18	/* is terminating due to OOM killer */
@@ -160,12 +161,13 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
 
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0cab47d..a566ec2 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac5..b032c94 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
@@ -415,7 +424,7 @@ local_restart:
 1:
 #endif
 
-	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	tst     r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
 	bne	__sys_trace
 
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f..4974cdf 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
 	unsigned long ip;
 
+	current_thread_info()->syscall = scno;
+
 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
 		return scno;
 
-	current_thread_info()->syscall = scno;
-
 	/*
 	 * IP is used to denote syscall entry/exit:
 	 * IP = 0 -> entry, =1 -> exit
@@ -942,6 +945,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_enter(regs, scno);
 	audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
 			    regs->ARM_r2, regs->ARM_r3);
 	return ret;
@@ -950,6 +955,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_exit(regs, scno);
 	audit_syscall_exit(regs);
 	return ret;
 }
-- 
1.7.0.4



From sebastian.hesselbarth at gmail.com  Mon Aug 20 10:43:00 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarh)
Date: Mon, 20 Aug 2012 16:43:00 +0200
Subject: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver
In-Reply-To: <CACRpkda9BL5+NiDOsMKG0kv2coBsw=Er=ZccXnNkgeftV9hPhQ@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>	<1344689809-6223-3-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda9BL5+NiDOsMKG0kv2coBsw=Er=ZccXnNkgeftV9hPhQ@mail.gmail.com>
Message-ID: <50324CF4.7060304@gmail.com>

On 08/20/2012 03:43 PM, Linus Walleij wrote:
>>   config PINCTRL_MVEBU
>>          bool "Marvell SoC pin controller drivers"
>> -       depends on ARCH_MVEBU
>> +       depends on ARCH_MVEBU || ARCH_DOVE
>
> Hmmmm.
>
> Shouldn't this thing rather be:
> depends on PLAT_ORION
> else you end up lining up all Marvell machines here...
 > (...)
 >> +config PINCTRL_DOVE
 >> +       bool "Support for Marvell Dove SoCs"
 >> +       depends on PINCTRL_MVEBU
 >
 > Shouldn't this rather be:
 >
 > depends on ARCH_DOVE
 > select PINCTRL_MVEBU
 >
 > since you call down into the mvebu driver, it definatley needs
 > to select that.

Yes, this is a bit difficult but PLAT_ORION is basically all existing
Marvell SoCs of the Orion family. Armada 370/XP are two new SoCs
_and_ the approach to combine all into one mach-mvebu. The pinctrl
driver will only be made available to mach-mvebu as I am already close
to have at least mach-dove ported over.

After the review of Andrew, I already changed the Kconfig to have the 
structure you are proposing.

>> +#define  DOVE_AU0_AC97_SEL             (1<<  16)
>
> It is way cleaner to say:
> #include<linux/bitops.h>
> #define  DOVE_AU0_AC97_SEL             BIT(16)

Ok.

> Same comments about the magic numbers as in the review of the first
> patch.

I just agree with all of these comments and will work them in.

>> +       if (ctrl->pid == 24)
>> +               mask = DOVE_CAM_GPIO_SEL;
>> +       else if (ctrl->pid == 40)
>> +               mask = DOVE_SD0_GPIO_SEL;
>> +       else if (ctrl->pid == 46)
>> +               mask = DOVE_SD1_GPIO_SEL;
>> +       else if (ctrl->pid == 58)
>> +               mask = DOVE_SPI_GPIO_SEL;
>> +       else if (ctrl->pid == 62)
>> +               mask = DOVE_UART1_GPIO_SEL;
>> +       else
>> +               return -EINVAL;
>
> Magic numbers, atleast provide a comment on what is so special about
> these pins, and can you use a switch() statement instead?

Sure.

>> +static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
>> +{
>> +       unsigned long config;
>> +
>> +       dove_audio1_ctrl_get(ctrl,&config);
>> +
>> +       switch (config) {
>> +       /* mode 0x00 i2s1/spdifo : no gpio */
>> +       /* mode 0x0c ssp/spdifo  : no gpio */
>> +       /* mode 0x0f ssp/twsi    : no gpio */
>> +       case 0x00:
>> +       case 0x0c:
>> +       case 0x0f:
>> +               return -ENOTSUPP;
>
> Nice with the comments (also before the function),
> now I understand what's happening, this is pretty OK,
> I would have put the comments on the same
> line as the magic number but whatever.
>
> However you could just delete these lines and let them
> fall through to -ENOTSUPP at the bottom.

Ok.

>> +/* mpp[52:57] has gpio pins capable of in and out */
>> +static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
>> +                               bool input)
>> +{
>> +       return 0;
>> +}
>
> So should this not return a -ENOTSUPP for
> pin<  52 || pin>  57?

Well, as pinctrl-mvebu and pinctrl core are already checking for pin
ranges, I think it's ok not to do it here again. But I don't have a
strong opinion about that.

>> +       /*
>> +        * General MPP Configuration Register is part of pdma registers.
>> +        * grab clk to make sure it is clocked.
>> +        */
>> +       pdma_clk = clk_get_sys("dove-pdma", NULL);
>
> First there is something really weird with the name of this
> clock. Atleast call the variable holding the clk something
> apropriate like just "clk".
>
> Second why are you fetching a sys clock instead of using the clkdev
> device binding in the clock tree so you could say:
>
> clk = clk_get(&pdev->dev, NULL);

pdma is the name of the clock gating control bit used in DS, IIRC it
stands for Peripheral DMA. Moreover, as I already mentioned it is now
using devm_clk_get. I think the time the pinctrl-dove driver patch was
posted there was no clock binding in 3.6.

>> +static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
>> +{
>> +       int ret;
>> +
>> +       ret = mvebu_pinctrl_remove(pdev);
>> +       if (!IS_ERR(pdma_clk)) {
>> +               clk_disable_unprepare(pdma_clk);
>> +               clk_put(pdma_clk);
>> +       }
>
> You don't need this (!IS_ERR()) clause, look in yout probe function:
> you bail out if the clock is not found.

Agree.

Sebastian


From ludovic.desroches at atmel.com  Mon Aug 20 10:44:00 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Mon, 20 Aug 2012 16:44:00 +0200
Subject: [PATCH] ARM: at91: automatically select DT support for sam9x5 and
 sam9n12
Message-ID: <1345473840-22141-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

at91sam9x5 and at91sam9n12 only have device tree support so we can
select device tree support when selecting these chips.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8050b1..db94ec6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -88,6 +88,7 @@ config SOC_AT91SAM9X5
 	select HAVE_AT91_DBGU0
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
+	select MACH_AT91SAM_DT
 	help
 	  Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
 	  This means that your SAM9 name finishes with a '5' (except if it is
@@ -100,6 +101,7 @@ config SOC_AT91SAM9N12
 	select SOC_AT91SAM9
 	select HAVE_AT91_DBGU0
 	select HAVE_FB_ATMEL
+	select MACH_AT91SAM_DT
 	help
 	  Select this if you are using Atmel's AT91SAM9N12 SoC.
 
-- 
1.7.11.3



From anton.vorontsov at linaro.org  Mon Aug 20 10:44:49 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:44:49 -0700
Subject: [PATCH v4 0/12] KGDB/KDB FIQ (NMI) debugger
Message-ID: <20120820144449.GA32560@lizard>

Hi all,

In v4:

- Implemented kgdb_nmi serial driver, it provides 'nmi_console' KDB
  command. With the driver we can use our debugger port as a normal
  console, except that we can always get back to the debugger using the
  magic sequence.  Note that I still somewhat reluctant to introduce
  software-raised interrupts, as they're arch-specific and not always
  possible.  So today the driver uses a tasklet, it should be pretty
  cheap: we're checking for the input on timer interrupts, but we don't
  cause needless wakeups. The pro of this is that it works everywhere
  (but arches still have an option to optimize things, of course);

- Two new patches added to propagate init_poll() callbacks from tty
  to uart drivers. As a side-effect, a long-standing bug fixed in
  amba-pl1011 driver;

- Dropped patch 'Get rid of .LCcralign local label';

- Some more fixes in SVC return path. Now it seems rock-solid;

- The patches were rebased on the latest Linus' tree, and as usual can
  be found in the following repo:

	git://git.infradead.org/users/cbou/linux-nmi-kdb.git master


Boilerplate:

These patches introduce KGDB FIQ debugger support. The idea (and some
code, of course) comes from Google's FIQ debugger[2]. There are some
differences (mostly implementation details, feature-wise they're almost
equivalent, or can be made equivalent, if desired).

The FIQ debugger is a facility that can be used to debug situations when
the kernel stuck in uninterruptable sections, e.g. the kernel infinitely
loops or deadlocked in an interrupt or with interrupts disabled. On some
development boards there is even a special NMI button, which is very
useful for debugging weird kernel hangs.

And FIQ is basically an NMI, it has a higher priority than IRQs, and
upon IRQ exception FIQs are not disabled. It is still possible to
disable FIQs (as well as some "NMIs" on other architectures), but via
special means.

So, here FIQs and NMIs are synonyms, but in the code I use NMI term for
arch-independent code, and FIQs for ARM code.

A few years ago KDB wasn't yet ready for production, or even not
well-known, so originally Google implemented its own FIQ debugger that
included its own shell, ring-buffer, commands, dumping, backtracing
logic and whatnot. This is very much like PowerPC's xmon
(arch/powerpc/xmon), except that xmon was there for a decade, so it even
predates KDB.

Anyway, nowadays KGDB/KDB is the cross-platform debugger, and the only
feature that was missing is NMI handling. This is now fixed for ARM.

There are a few differences comparing to the original (Google's) FIQ
debugger:

- Doing stuff in FIQ context is dangerous, as there we are not allowed
  to cause aborts or faults. In the original FIQ debugger there was a
  "signal" software-induced interrupt, upon exit from FIQ it would fire,
  and we would continue to execute "dangerous" commands from there.

  In KGDB/KDB we don't use signal interrupts. We can do easier: set up a
  breakpoint, continue, and you'll trap into KGDB again in a safe
  context.

  It works for most cases, but I can imagine cases when you can't set up
  a breakpoint. For these cases we'd better introduce a KDB command
  "exit_nmi", that will rise the SW IRQ, after which we're allowed to do
  anything.

- KGDB/KDB FIQ debugger shell is synchronous. In Google's version you
  could have a dedicated shell always running in the FIQ context, so
  when you type something on a serial line, you won't actually cause any
  debugging actions, FIQ would save the characters in its own buffer and
  continue execution normally. But when you hit return key after the
  command, then the command is executed.

  In KGDB/KDB FIQ debugger it is different. Once you enter KGDB, the
  kernel will stop until you instruct it to continue.

  This might look as a drastic change, but it is not. There is actually
  no difference whether you have sync or async shell, or at least I
  couldn't find any use-case where this would matter at all. Anyways, it
  is still possible to do async shell in KDB, just don't see any need
  for this.

- Original FIQ debugger used a custom FIQ vector handling code, w/ a lot
  of logic in it. In this approach I'm using the fact that FIQs are
  basically IRQs, except that we there are a bit more registers banked,
  and we can actually trap from the IRQ context.

  But this all does not prevent us from using a simple jump-table based
  approach as used in the generic ARM entry code. So, here I just reuse
  the generic approach.

Note that I test the code on a modelled ARM machine (QEMU Versatile), so
there might be some issues on a real HW, but it works in QEMU tho. :-)

Assuming you have QEMU >= 1.1.0, you can easily play with the code using
ARM/versatile defconfig and command like this:

  qemu-system-arm -nographic -machine versatilepb -kernel
  linux/arch/arm/boot/zImage -append "console=ttyAMA0 kgdboc=ttyAMA0
  kgdb_fiq.enable=1"

Thanks,

--
 arch/arm/Kconfig                    |  19 ++
 arch/arm/common/vic.c               |  28 +++
 arch/arm/include/asm/hardware/vic.h |   2 +
 arch/arm/include/asm/kgdb.h         |   8 +
 arch/arm/kernel/Makefile            |   1 +
 arch/arm/kernel/entry-armv.S        | 167 +----------------
 arch/arm/kernel/entry-header.S      | 170 ++++++++++++++++++
 arch/arm/kernel/kgdb_fiq.c          |  99 ++++++++++
 arch/arm/kernel/kgdb_fiq_entry.S    |  87 +++++++++
 arch/arm/mach-versatile/Makefile    |   1 +
 arch/arm/mach-versatile/kgdb_fiq.c  |  31 ++++
 drivers/tty/serial/Kconfig          |  19 ++
 drivers/tty/serial/Makefile         |   1 +
 drivers/tty/serial/amba-pl011.c     |  60 +++++--
 drivers/tty/serial/kgdb_nmi.c       | 348 ++++++++++++++++++++++++++++++++++++
 drivers/tty/serial/kgdboc.c         |  16 ++
 drivers/tty/serial/serial_core.c    |  30 ++++
 include/linux/kdb.h                 |  29 +--
 include/linux/kgdb.h                |  34 ++++
 include/linux/serial_core.h         |   2 +
 include/linux/tty_driver.h          |   1 +
 kernel/debug/debug_core.c           |  36 +++-
 kernel/debug/kdb/kdb_main.c         |  29 +++
 23 files changed, 1024 insertions(+), 194 deletions(-)

In v3:

- Per Colin Cross suggestion, added a way to release a debug console for
  normal use.  This is done via 'disable_nmi' command (in the original
  FIQ debugger it was 'console' command). For this I added a new
  callback in the tty ops, and serial drivers have to provide a way to
  clear its interrupts. The patch 'tty/serial/kgdboc: Add and wire up
  clear_irqs callback' explains the concept in details.
- Made the debug entry prompt more shell-like;
- A new knocking mode '-1'. It disables the feature altogether, and thus
  makes it possible to hook KDB entry to a dedicated button.
- The code was rebased on 'v3.5 + kdb kiosk'[1] patches;

In v2:

- Per Colin Cross' suggestion, we should not enter the debugger on any
  received byte (this might be a problem when there's a noise on the
  serial line). So there is now an additional patch that implements
  "knocking" to the KDB (either via $3#33 command or return key, this is
  configurable);
- Reworked {enable,select}_fiq/is_fiq callbacks, now multi-mach kernels
  should not be a problem;
- For versatile machines there are run-time checks for proper UART port
  (kernel will scream aloud if out of range port is specified);
- Added some __init annotations;
- Since not every architecture defines FIQ_START, we can't just blindly
  select CONFIG_FIQ symbol. So ARCH_MIGHT_HAVE_FIQ introduced;
- Add !THUMB2_KERNEL dependency for KGDB_FIQ, we don't support Thumb2
  kernels;
- New patch that is used to get rid of LCcralign label in alignment_trap
  macro.

[1] https://lkml.org/lkml/2012/7/26/260
[2]
Original Google's FIQ debugger, fiq_* files:
http://android.git.linaro.org/gitweb?p=kernel/common.git;a=tree;f=arch/arm/common;hb=refs/heads/android-3.4
And board support as an example of using it:
http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=commitdiff;h=461cb80c16e4e266ab6207a00767b59212148086


From will.deacon at arm.com  Mon Aug 20 10:49:28 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 15:49:28 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
Message-ID: <20120820144927.GP25864@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 02:29:31PM +0100, Nicolas Pitre wrote:
> On Mon, 20 Aug 2012, Will Deacon wrote:
> > Translates the following code from amba_device_add:
> > 
> > 		for (pid = 0, i = 0; i < 4; i++)
> > 			pid |= (readl(tmp + size - 0x20 + 4 * i) & 255) <<
> > 				(i * 8);
> > 		for (cid = 0, i = 0; i < 4; i++)
> > 			cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) <<
> > 				(i * 8);
> > 
> > into:
> [...]
> 
> OK, I can see how the compiler will fold the loop increment into the IO 
> access instruction.  But my point is: is this common?  And when this 
> happens, is this a critical path?

Sure, this case isn't such a big deal (basically just boot-time probing) but
GCC could still generate this stuff in a driver, where it could end up being
an I/O bottleneck for a guest OS.

> > whilst the addressing modes are still nice, the dsb is going to be the
> > performance limitation here. That said, we could try the "Qo" constraints,
> > which I seem to remember don't generate writebacks. I'll have a play.
> 
> OK.  That would be excellent.

Looks like we have a winner (diff against the original patch below). I now
see:

00000340 <hw_init>:
 340:   e1a03000        mov     r3, r0
 344:   e3a00000        mov     r0, #0
 348:   e5830010        str     r0, [r3, #16]
 34c:   e3e02000        mvn     r2, #0
 350:   e5832014        str     r2, [r3, #20]
 354:   e5932018        ldr     r2, [r3, #24]
 358:   e38220ff        orr     r2, r2, #255    ; 0xff
 35c:   e5832030        str     r2, [r3, #48]   ; 0x30
 360:   e12fff1e        bx      lr

with the new code, which is basically the same as the old code but the mvn and
a str have switched places. The same difference occurs when targetting Thumb2.

> > To deal with this, the hypervisor will likely have to stop the virtual world
> > when emulating any MMIO accesses that report incomplete fault information to
> > avoid racing with a TLB invalidation from another virtual CPU. That will
> > certainly be more expensive than an additional instruction on each access.
> 
> I totally agree with you here.
> 
> However, for completeness and above all for security reasons, the 
> hypervisor will _ahve_ to support that case anyway.

Support it, yes, but perhaps not efficiently.

> So it is now a matter of compromise between performance and code size.  
> If the pathological case you brought up above is the exception and not 
> the rule then I think that we can live with the performance impact in 
> that case and keep the optimal pre-indexed addressing for the common 
> cases.

It looks like the new code does exactly what we want, so I think we could
actually have the best of both worlds: pre-index addressing and no
writeback.

Will

--- >8

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index b54d687..bbc94c2 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -63,38 +63,50 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  */
 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 {
-       asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
+       asm volatile("strh %1, %0"
+                    : "=Qo" (*(volatile u16 __force *)addr)
+                    : "r" (val));
 }
 
 static inline u16 __raw_readw(const volatile void __iomem *addr)
 {
        u16 val;
-       asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
+       asm volatile("ldrh %0, %1"
+                    : "=r" (val)
+                    : "Qo" (*(const volatile u16 __force *)addr));
        return val;
 }
 #endif
 
 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 {
-       asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr));
+       asm volatile("strb %1, %0"
+                    : "=Qo" (*(volatile u8 __force *)addr)
+                    : "r" (val));
 }
 
 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 {
-       asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
+       asm volatile("str %1, %0"
+                    : "=Qo" (*(volatile u32 __force *)addr)
+                    : "r" (val));
 }
 
 static inline u8 __raw_readb(const volatile void __iomem *addr)
 {
        u8 val;
-       asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr));
+       asm volatile("ldrb %0, %1"
+                    : "=r" (val)
+                    : "Qo" (*(const volatile u8 __force *)addr));
        return val;
 }
 
 static inline u32 __raw_readl(const volatile void __iomem *addr)
 {
        u32 val;
-       asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
+       asm volatile("ldr %0, %1"
+                    : "=r" (val)
+                    : "Qo" (*(const volatile u32 __force *)addr));
        return val;
 }


From b-cousson at ti.com  Mon Aug 20 10:49:40 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Mon, 20 Aug 2012 16:49:40 +0200
Subject: [PATCH 1/3] ARM: OMAP: hwmod: partially un-reset hwmods might
 not be properly enabled
In-Reply-To: <1342466485-1050-2-git-send-email-omar.luna@linaro.org>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-2-git-send-email-omar.luna@linaro.org>
Message-ID: <50324E84.6080407@ti.com>

Hi Omar,

On 07/16/2012 09:21 PM, Omar Ramirez Luna wrote:
> Some IP blocks might not be using/controlling more than one
> reset line, this check loosens the restriction to fully use
> hwmod framework for those drivers.
> 
> E.g.: ipu has reset lines: mmu_cache, cpu0 and cpu1.
> - cpu1 might not be used and hence (with previous check)
>   won't be fully enabled by hwmod code.

You mean that you might have some case where you need to enable the
mmu_cache and cpu0 and thus deassert only the mmu/cpu0 while keeping the
cpu1 under reset?

So the any_hardreset is indeed not appropriate in that case.

In fact, since the hardreset cannot be handled at all by the hwmod fmwk,
I'm even wondering if we should take care of checking the state at all.
But as Paul stated, if was done due to the lack of understanding about
the diver usage, so maybe things will become clearer once we will have
that code available.

So I guess that checking for all the lines for the hardreset state is
anyway already a first step toward a good understanding of the reset
need for the remote processors.

The patch looks fine to me considering that we do not have a lot of
information about the usage :-(

Maybe you could add more information in the changelog to explain the way
you are going to use the reset API.

Regards,
Benoit


> While at it, prevent _omap4_module_disable if all the hardreset
> lines on an IP block are not under reset.


> 
> Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |   37 ++++++++++++++++++++++---------------
>  1 files changed, 22 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 3215dad..091c199 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -1558,25 +1558,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
>  }
>  
>  /**
> - * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
> + * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
>   * @oh: struct omap_hwmod *
>   *
> - * If any hardreset line associated with @oh is asserted, then return true.
> - * Otherwise, if @oh has no hardreset lines associated with it, or if
> - * no hardreset lines associated with @oh are asserted, then return false.
> + * If all hardreset lines associated with @oh are asserted, then return true.
> + * Otherwise, if part of @oh is out hardreset or if no hardreset lines
> + * associated with @oh are asserted, then return false.
>   * This function is used to avoid executing some parts of the IP block
> - * enable/disable sequence if a hardreset line is set.
> + * enable/disable sequence if its hardreset line is set.
>   */
> -static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
> +static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
>  {
> -	int i;
> +	int i, rst_cnt = 0;
>  
>  	if (oh->rst_lines_cnt == 0)
>  		return false;
>  
>  	for (i = 0; i < oh->rst_lines_cnt; i++)
>  		if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
> -			return true;
> +			rst_cnt++;
> +
> +	if (oh->rst_lines_cnt == rst_cnt)
> +		return true;
>  
>  	return false;
>  }
> @@ -1595,6 +1598,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
>  	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
>  		return -EINVAL;
>  
> +	/*
> +	 * Since integration code might still be doing something, only
> +	 * disable if all lines are under hardreset.
> +	 */
> +	if (!_are_all_hardreset_lines_asserted(oh))
> +		return 0;
> +
>  	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
>  
>  	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
> @@ -1602,9 +1612,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
>  				    oh->clkdm->clkdm_offs,
>  				    oh->prcm.omap4.clkctrl_offs);
>  
> -	if (_are_any_hardreset_lines_asserted(oh))
> -		return 0;
> -
>  	v = _omap4_wait_target_disable(oh);
>  	if (v)
>  		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
> @@ -1830,7 +1837,7 @@ static int _enable(struct omap_hwmod *oh)
>  	}
>  
>  	/*
> -	 * If an IP block contains HW reset lines and any of them are
> +	 * If an IP block contains HW reset lines and all of them are
>  	 * asserted, we let integration code associated with that
>  	 * block handle the enable.  We've received very little
>  	 * information on what those driver authors need, and until
> @@ -1838,7 +1845,7 @@ static int _enable(struct omap_hwmod *oh)
>  	 * posted to the public lists, this is probably the best we
>  	 * can do.
>  	 */
> -	if (_are_any_hardreset_lines_asserted(oh))
> +	if (_are_all_hardreset_lines_asserted(oh))
>  		return 0;
>  
>  	/* Mux pins for device runtime if populated */
> @@ -1918,7 +1925,7 @@ static int _idle(struct omap_hwmod *oh)
>  		return -EINVAL;
>  	}
>  
> -	if (_are_any_hardreset_lines_asserted(oh))
> +	if (_are_all_hardreset_lines_asserted(oh))
>  		return 0;
>  
>  	if (oh->class->sysc)
> @@ -2006,7 +2013,7 @@ static int _shutdown(struct omap_hwmod *oh)
>  		return -EINVAL;
>  	}
>  
> -	if (_are_any_hardreset_lines_asserted(oh))
> +	if (_are_all_hardreset_lines_asserted(oh))
>  		return 0;
>  
>  	pr_debug("omap_hwmod: %s: disabling\n", oh->name);
> 



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:20 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:20 -0700
Subject: [PATCH 02/12] kdb: Implement disable_nmi command
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-2-git-send-email-anton.vorontsov@linaro.org>

This command disables NMI-entry. If NMI source has been previously shared
with a serial console ("debug port"), this effectively releases the port
from KDB exclusive use, and makes the console available for normal use.

Of course, NMI can be reenabled, enable_nmi modparam is used for that:

	echo 1 > /sys/module/kdb/parameters/enable_nmi

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 kernel/debug/kdb/kdb_main.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c
index 31df170..9fadff1 100644
--- a/kernel/debug/kdb/kdb_main.c
+++ b/kernel/debug/kdb/kdb_main.c
@@ -21,6 +21,7 @@
 #include <linux/smp.h>
 #include <linux/utsname.h>
 #include <linux/vmalloc.h>
+#include <linux/atomic.h>
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/init.h>
@@ -2107,6 +2108,32 @@ static int kdb_dmesg(int argc, const char **argv)
 	return 0;
 }
 #endif /* CONFIG_PRINTK */
+
+/* Make sure we balance enable/disable calls, must disable first. */
+static atomic_t kdb_nmi_disabled;
+
+static int kdb_disable_nmi(int argc, const char *argv[])
+{
+	if (atomic_read(&kdb_nmi_disabled))
+		return 0;
+	atomic_set(&kdb_nmi_disabled, 1);
+	kgdb_enable_nmi(0);
+	return 0;
+}
+
+static int kdb_param_enable_nmi(const char *val, const struct kernel_param *kp)
+{
+	if (!atomic_add_unless(&kdb_nmi_disabled, -1, 0))
+		return -EINVAL;
+	kgdb_enable_nmi(1);
+	return 0;
+}
+
+static const struct kernel_param_ops kdb_param_ops_enable_nmi = {
+	.set = kdb_param_enable_nmi,
+};
+module_param_cb(enable_nmi, &kdb_param_ops_enable_nmi, NULL, 0600);
+
 /*
  * kdb_cpu - This function implements the 'cpu' command.
  *	cpu	[<cpunum>]
@@ -2851,6 +2878,8 @@ static void __init kdb_inittab(void)
 	kdb_register_repeat("dmesg", kdb_dmesg, "[lines]",
 	  "Display syslog buffer", 0, KDB_REPEAT_NONE);
 #endif
+	kdb_register_repeat("disable_nmi", kdb_disable_nmi, "",
+	  "Disable NMI entry to KDB", 0, KDB_REPEAT_NONE);
 	kdb_register_repeat("defcmd", kdb_defcmd, "name \"usage\" \"help\"",
 	  "Define a set of commands, down to endefcmd", 0, KDB_REPEAT_NONE);
 	kdb_register_repeat("kill", kdb_kill, "<-signal> <pid>",
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:19 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:19 -0700
Subject: [PATCH 01/12] kernel/debug: Mask KGDB NMI upon entry
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-1-git-send-email-anton.vorontsov@linaro.org>

The new arch callback should manage NMIs that usually cause KGDB to
enter. That is, not all NMIs should be enabled/disabled, but only
those that issue kgdb_handle_exception().

We must mask it as serial-line interrupt can be used as an NMI, so
if the original KGDB-entry cause was say a breakpoint, then every
input to KDB console will cause KGDB to reenter, which we don't want.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 include/linux/kgdb.h      | 23 +++++++++++++++++++++++
 kernel/debug/debug_core.c | 36 +++++++++++++++++++++++++++++++++---
 2 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h
index c4d2fc1..3b111a6 100644
--- a/include/linux/kgdb.h
+++ b/include/linux/kgdb.h
@@ -221,6 +221,29 @@ extern int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt);
  */
 extern void kgdb_arch_late(void);
 
+/**
+ *	kgdb_arch_enable_nmi - Enable or disable KGDB-entry NMI
+ *	@on: Flag to either enable or disable an NMI
+ *
+ *	This is an architecture-specific "back-end" for kgdb_enable_nmi(). The
+ *	call does not count disable/enable requests, do not use it directly.
+ */
+extern void kgdb_arch_enable_nmi(bool on);
+
+/**
+ *	kgdb_enable_nmi - Enable or disable KGDB-entry NMI
+ *	@on: Flag to either enable or disable an NMI
+ *
+ *	This function manages NMIs that usually cause KGDB to enter. That is,
+ *	not all NMIs should be enabled or disabled, but only those that issue
+ *	kgdb_handle_exception().
+ *
+ *	The call counts disable requests, and thus allows to nest disables.
+ *	But trying to enable already enabled NMI is an error. The call returns
+ *	1 if NMI has been actually enabled after the call, and a value <= 0 if
+ *	it is still disabled.
+ */
+extern int kgdb_enable_nmi(bool on);
 
 /**
  * struct kgdb_arch - Describe architecture specific values.
diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c
index 0557f24..b621d1e 100644
--- a/kernel/debug/debug_core.c
+++ b/kernel/debug/debug_core.c
@@ -214,6 +214,30 @@ int __weak kgdb_skipexception(int exception, struct pt_regs *regs)
 	return 0;
 }
 
+void __weak kgdb_arch_enable_nmi(bool on)
+{
+}
+
+int kgdb_enable_nmi(bool on)
+{
+	static atomic_t cnt;
+	int ret;
+
+	ret = atomic_add_return(on ? 1 : -1, &cnt);
+	if (ret > 1 && on) {
+		/*
+		 * There should be only one instance that calls this function
+		 * in "enable, disable" order. All other users must call
+		 * disable first, then enable. If not, something is wrong.
+		 */
+		WARN_ON(1);
+		return 1;
+	}
+
+	kgdb_arch_enable_nmi(ret > 0);
+	return ret;
+}
+
 /*
  * Some architectures need cache flushes when we set/clear a
  * breakpoint:
@@ -672,6 +696,9 @@ kgdb_handle_exception(int evector, int signo, int ecode, struct pt_regs *regs)
 {
 	struct kgdb_state kgdb_var;
 	struct kgdb_state *ks = &kgdb_var;
+	int ret = 0;
+
+	kgdb_enable_nmi(0);
 
 	ks->cpu			= raw_smp_processor_id();
 	ks->ex_vector		= evector;
@@ -681,11 +708,14 @@ kgdb_handle_exception(int evector, int signo, int ecode, struct pt_regs *regs)
 	ks->linux_regs		= regs;
 
 	if (kgdb_reenter_check(ks))
-		return 0; /* Ouch, double exception ! */
+		goto out; /* Ouch, double exception ! */
 	if (kgdb_info[ks->cpu].enter_kgdb != 0)
-		return 0;
+		goto out;
 
-	return kgdb_cpu_enter(ks, regs, DCPU_WANT_MASTER);
+	ret = kgdb_cpu_enter(ks, regs, DCPU_WANT_MASTER);
+out:
+	kgdb_enable_nmi(1);
+	return ret;
 }
 
 int kgdb_nmicallback(int cpu, void *regs)
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:21 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:21 -0700
Subject: [PATCH 03/12] kdb: Turn KGDB_KDB=n stubs into static inlines
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-3-git-send-email-anton.vorontsov@linaro.org>

This makes the stubs actually usable, since e.g. 'foo = kdb_register();'
leads to build errors in !KGDB_KDB case. Plus, with static inlines we
do type checking.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 include/linux/kdb.h | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/include/linux/kdb.h b/include/linux/kdb.h
index 42d9e86..7f6fe6e 100644
--- a/include/linux/kdb.h
+++ b/include/linux/kdb.h
@@ -13,6 +13,14 @@
  * Copyright (C) 2009 Jason Wessel <jason.wessel at windriver.com>
  */
 
+typedef enum {
+	KDB_REPEAT_NONE = 0,	/* Do not repeat this command */
+	KDB_REPEAT_NO_ARGS,	/* Repeat the command without arguments */
+	KDB_REPEAT_WITH_ARGS,	/* Repeat the command including its arguments */
+} kdb_repeat_t;
+
+typedef int (*kdb_func_t)(int, const char **);
+
 #ifdef	CONFIG_KGDB_KDB
 #include <linux/init.h>
 #include <linux/sched.h>
@@ -32,14 +40,6 @@ extern atomic_t kdb_event;
 
 #define KDB_MAXARGS    16 /* Maximum number of arguments to a function  */
 
-typedef enum {
-	KDB_REPEAT_NONE = 0,	/* Do not repeat this command */
-	KDB_REPEAT_NO_ARGS,	/* Repeat the command without arguments */
-	KDB_REPEAT_WITH_ARGS,	/* Repeat the command including its arguments */
-} kdb_repeat_t;
-
-typedef int (*kdb_func_t)(int, const char **);
-
 /* KDB return codes from a command or internal kdb function */
 #define KDB_NOTFOUND	(-1)
 #define KDB_ARGCOUNT	(-2)
@@ -149,11 +149,14 @@ extern int kdb_register_repeat(char *, kdb_func_t, char *, char *,
 			       short, kdb_repeat_t);
 extern int kdb_unregister(char *);
 #else /* ! CONFIG_KGDB_KDB */
-#define kdb_printf(...)
-#define kdb_init(x)
-#define kdb_register(...)
-#define kdb_register_repeat(...)
-#define kdb_uregister(x)
+static inline __printf(1, 2) int kdb_printf(const char *fmt, ...) { return 0; }
+static inline void kdb_init(int level) {}
+static inline int kdb_register(char *cmd, kdb_func_t func, char *usage,
+			       char *help, short minlen) { return 0; }
+static inline int kdb_register_repeat(char *cmd, kdb_func_t func, char *usage,
+				      char *help, short minlen,
+				      kdb_repeat_t repeat) { return 0; }
+static inline int kdb_unregister(char *cmd) { return 0; }
 #endif	/* CONFIG_KGDB_KDB */
 enum {
 	KDB_NOT_INITIALIZED,
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:22 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:22 -0700
Subject: [PATCH 04/12] tty/serial/core: Introduce poll_init callback
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-4-git-send-email-anton.vorontsov@linaro.org>

It was noticed that polling drivers (like KGDB) are not able to use
serial ports if the ports were not previously initialized via console.
I.e.  when booting with console=ttyAMA0 kgdboc=ttyAMA0, everything works
fine, but with console=ttyFOO kgdboc=ttyAMA0, the kgdboc doesn't work.

This is because we don't initialize the hardware. Calling ->startup() is
not an option, because drivers request interrupts there, and drivers
fail to handle situations when tty isn't opened with interrupts enabled.

So, we have to implement a new callback (actually, tty_ops already have
a similar callback), which does everything needed to initialize just the
hardware.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/tty/serial/serial_core.c | 15 +++++++++++++++
 include/linux/serial_core.h      |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index a21dc8e..cba8443 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2108,11 +2108,13 @@ static int uart_poll_init(struct tty_driver *driver, int line, char *options)
 {
 	struct uart_driver *drv = driver->driver_state;
 	struct uart_state *state = drv->state + line;
+	struct tty_port *tport;
 	struct uart_port *port;
 	int baud = 9600;
 	int bits = 8;
 	int parity = 'n';
 	int flow = 'n';
+	int ret;
 
 	if (!state || !state->uart_port)
 		return -1;
@@ -2121,6 +2123,19 @@ static int uart_poll_init(struct tty_driver *driver, int line, char *options)
 	if (!(port->ops->poll_get_char && port->ops->poll_put_char))
 		return -1;
 
+	tport = &state->port;
+	if (!(tport->flags & ASYNC_INITIALIZED) && port->ops->poll_init) {
+		mutex_lock(&tport->mutex);
+		ret = port->ops->poll_init(port);
+		/*
+		 * We don't set ASYNCB_INITIALIZED as we only initialized the
+		 * hw, e.g. state->xmit is still uninitialized.
+		 */
+		mutex_unlock(&tport->mutex);
+		if (ret)
+			return ret;
+	}
+
 	if (options) {
 		uart_parse_options(options, &baud, &parity, &bits, &flow);
 		return uart_set_options(port, NULL, baud, parity, bits, flow);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 0253c20..3642710 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -274,6 +274,7 @@ struct uart_ops {
 	int		(*verify_port)(struct uart_port *, struct serial_struct *);
 	int		(*ioctl)(struct uart_port *, unsigned int, unsigned long);
 #ifdef CONFIG_CONSOLE_POLL
+	int		(*poll_init)(struct uart_port *);
 	void	(*poll_put_char)(struct uart_port *, unsigned char);
 	int		(*poll_get_char)(struct uart_port *);
 #endif
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:23 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:23 -0700
Subject: [PATCH 05/12] tty/serial/amba-pl011: Implement poll_init callback
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-5-git-send-email-anton.vorontsov@linaro.org>

The callback is used to initialize the hardware, nothing else should be
done, i.e. we should not request interrupts (but we can and do unmask
some of them, as they might be useful for NMI entry).

As a side-effect, the patch also fixes a division by zero[1] when booting
with kgdboc options specified (e.g. kgdboc=ttyAMA0,115200n8). The issue
happens because serial core calls set_termios callback, but the driver
doesn't know clock frequency, and thus cannot calculate proper baud rate
values.

[1]
WARNING: at drivers/tty/serial/serial_core.c:400 uart_get_baud_rate+0xe8/0x14c()
Modules linked in:
[<c0018e50>] (unwind_backtrace+0x0/0xf0) from [<c0020ae8>] (warn_slowpath_common+0x4c/0x64)
[<c0020ae8>] (warn_slowpath_common+0x4c/0x64) from [<c0020b1c>] (warn_slowpath_null+0x1c/0x24)
[<c0020b1c>] (warn_slowpath_null+0x1c/0x24) from [<c0185ed8>] (uart_get_baud_rate+0xe8/0x14c)
[<c0185ed8>] (uart_get_baud_rate+0xe8/0x14c) from [<c0187078>] (pl011_set_termios+0x48/0x278)
[<c0187078>] (pl011_set_termios+0x48/0x278) from [<c01850b0>] (uart_set_options+0xe8/0x114)
[<c01850b0>] (uart_set_options+0xe8/0x114) from [<c0185de4>] (uart_poll_init+0xd4/0xe0)
[<c0185de4>] (uart_poll_init+0xd4/0xe0) from [<c016da8c>] (tty_find_polling_driver+0x100/0x17c)
[<c016da8c>] (tty_find_polling_driver+0x100/0x17c) from [<c0188538>] (configure_kgdboc+0xc8/0x1b8)
[<c0188538>] (configure_kgdboc+0xc8/0x1b8) from [<c00088a4>] (do_one_initcall+0x30/0x168)
[<c00088a4>] (do_one_initcall+0x30/0x168) from [<c033784c>] (do_basic_setup+0x94/0xc8)
[<c033784c>] (do_basic_setup+0x94/0xc8) from [<c03378e0>] (kernel_init+0x60/0xf4)
[<c03378e0>] (kernel_init+0x60/0xf4) from [<c00144a0>] (kernel_thread_exit+0x0/0x8)
---[ end trace 7d41c9186f342c40 ]---
Division by zero in kernel.
[<c0018e50>] (unwind_backtrace+0x0/0xf0) from [<c014546c>] (Ldiv0+0x8/0x10)
[<c014546c>] (Ldiv0+0x8/0x10) from [<c0187098>] (pl011_set_termios+0x68/0x278)
[<c0187098>] (pl011_set_termios+0x68/0x278) from [<c01850b0>] (uart_set_options+0xe8/0x114)
[<c01850b0>] (uart_set_options+0xe8/0x114) from [<c0185de4>] (uart_poll_init+0xd4/0xe0)
[<c0185de4>] (uart_poll_init+0xd4/0xe0) from [<c016da8c>] (tty_find_polling_driver+0x100/0x17c)
[<c016da8c>] (tty_find_polling_driver+0x100/0x17c) from [<c0188538>] (configure_kgdboc+0xc8/0x1b8)
[<c0188538>] (configure_kgdboc+0xc8/0x1b8) from [<c00088a4>] (do_one_initcall+0x30/0x168)
[<c00088a4>] (do_one_initcall+0x30/0x168) from [<c033784c>] (do_basic_setup+0x94/0xc8)
[<c033784c>] (do_basic_setup+0x94/0xc8) from [<c03378e0>] (kernel_init+0x60/0xf4)
[<c03378e0>] (kernel_init+0x60/0xf4) from [<c00144a0>] (kernel_thread_exit+0x0/0x8)
Division by zero in kernel.
[<c0018e50>] (unwind_backtrace+0x0/0xf0) from [<c014546c>] (Ldiv0+0x8/0x10)
[<c014546c>] (Ldiv0+0x8/0x10) from [<c0183a98>] (uart_update_timeout+0x4c/0x5c)
[<c0183a98>] (uart_update_timeout+0x4c/0x5c) from [<c01870f8>] (pl011_set_termios+0xc8/0x278)
[<c01870f8>] (pl011_set_termios+0xc8/0x278) from [<c01850b0>] (uart_set_options+0xe8/0x114)
[<c01850b0>] (uart_set_options+0xe8/0x114) from [<c0185de4>] (uart_poll_init+0xd4/0xe0)
[<c0185de4>] (uart_poll_init+0xd4/0xe0) from [<c016da8c>] (tty_find_polling_driver+0x100/0x17c)
[<c016da8c>] (tty_find_polling_driver+0x100/0x17c) from [<c0188538>] (configure_kgdboc+0xc8/0x1b8)
[<c0188538>] (configure_kgdboc+0xc8/0x1b8) from [<c00088a4>] (do_one_initcall+0x30/0x168)
[<c00088a4>] (do_one_initcall+0x30/0x168) from [<c033784c>] (do_basic_setup+0x94/0xc8)
[<c033784c>] (do_basic_setup+0x94/0xc8) from [<c03378e0>] (kernel_init+0x60/0xf4)
[<c03378e0>] (kernel_init+0x60/0xf4) from [<c00144a0>] (kernel_thread_exit+0x0/0x8)

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/tty/serial/amba-pl011.c | 47 ++++++++++++++++++++++++++++++-----------
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d3553b5..90f2302 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1310,10 +1310,9 @@ static void pl010_put_poll_char(struct uart_port *port,
 
 #endif /* CONFIG_CONSOLE_POLL */
 
-static int pl011_startup(struct uart_port *port)
+static int pl011_hwinit(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
-	unsigned int cr;
 	int retval;
 
 	/* Optionaly enable pins to be muxed in and configured */
@@ -1342,6 +1341,39 @@ static int pl011_startup(struct uart_port *port)
 	       UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
 
 	/*
+	 * Save interrupts enable mask, and enable RX interrupts in case if
+	 * the interrupt is used for NMI entry.
+	 */
+	uap->im = readw(uap->port.membase + UART011_IMSC);
+	writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
+
+	if (uap->port.dev->platform_data) {
+		struct amba_pl011_data *plat;
+
+		plat = uap->port.dev->platform_data;
+		if (plat->init)
+			plat->init();
+	}
+	return 0;
+clk_unprep:
+	clk_unprepare(uap->clk);
+out:
+	return retval;
+}
+
+static int pl011_startup(struct uart_port *port)
+{
+	struct uart_amba_port *uap = (struct uart_amba_port *)port;
+	unsigned int cr;
+	int retval;
+
+	retval = pl011_hwinit(port);
+	if (retval)
+		goto clk_dis;
+
+	writew(uap->im, uap->port.membase + UART011_IMSC);
+
+	/*
 	 * Allocate the IRQ
 	 */
 	retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
@@ -1400,21 +1432,11 @@ static int pl011_startup(struct uart_port *port)
 	writew(uap->im, uap->port.membase + UART011_IMSC);
 	spin_unlock_irq(&uap->port.lock);
 
-	if (uap->port.dev->platform_data) {
-		struct amba_pl011_data *plat;
-
-		plat = uap->port.dev->platform_data;
-		if (plat->init)
-			plat->init();
-	}
-
 	return 0;
 
  clk_dis:
 	clk_disable(uap->clk);
- clk_unprep:
 	clk_unprepare(uap->clk);
- out:
 	return retval;
 }
 
@@ -1696,6 +1718,7 @@ static struct uart_ops amba_pl011_pops = {
 	.config_port	= pl010_config_port,
 	.verify_port	= pl010_verify_port,
 #ifdef CONFIG_CONSOLE_POLL
+	.poll_init	= pl011_hwinit,
 	.poll_get_char = pl010_get_poll_char,
 	.poll_put_char = pl010_put_poll_char,
 #endif
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:24 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:24 -0700
Subject: [PATCH 06/12] tty/serial/kgdboc: Add and wire up clear_irqs callback
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-6-git-send-email-anton.vorontsov@linaro.org>

This patch implements a new callback: clear_irqs. It is used for the
cases when KDB-entry (e.g. NMI) and KDB IO (e.g. serial port) shares
the same interrupt. To get the idea, let's take some real example (ARM
machine): we have a serial port which interrupt is routed to an NMI,
and the interrupt is used to enter KDB. Once there is some activity on
the serial port, the CPU receives NMI exception, and we fall into KDB
shell. So, it is our "debug console", and it is able to interrupt (and
thus debug) even IRQ handlers themselves.

When used that way, the interrupt never reaches serial driver's IRQ
handler routine, which means that serial driver will not silence the
interrupt. NMIs behaviour are quite arch-specific, and we can't assume
that we can use them as ordinary IRQs, e.g. on some arches (like ARM)
we can't handle data aborts, the behaviour is undefined then. So we
can't just handle execution to serial driver's IRQ handler from the
NMI context once we're done with KDB (plus this would defeat the
debugger's purpose: we want the NMI handler be as simple as possible,
so it will have less chances to hang).

So, given that have to deal with it somehow, we have two options:

1. Implement something that clears the interrupt;
2. Implement a whole new concept of grabbing tty for exclusive KDB use,
   plus implement mask/unmask callbacks, i.e.:
   - Since consoles might use ttys w/o opending them, we would have
     to make kdb respect CON_ENABLED flag (maybe a good idea to do it
     anyway);
   - Add 'bool exclusive' argument to tty_find_polling_driver(), if set
     to 1, the function will refuse to return an already tty; and will
     use the flag in tty_reopen() to not allow multiple users (there are
     already checks for pty masters, which are "open once" ttys);
   - Once we got the tty exclusively, we would need to call some new
     uart->mask_all_but_rx_interrupts call before we want to use the
     port for NMI/KDB, and unmask_all_but_rx_interrupts after we're
     done with it.

The second option is obviously more complex, needlessly so, and less
generic. So I went with the first one: we just consume all the interrupts.
The tty becomes silently unusable for the rest of the world when we use
it with KDB; but once we reroute the serial IRQ source back from NMI to
an ordinary IRQ (in KDB this can be done with 'disable_nmi' command), it
will behave as normal.

p.s. Since the callback is so far used only by polling user, we place
it under the appropriate #ifdef.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/tty/serial/kgdboc.c      | 10 ++++++++++
 drivers/tty/serial/serial_core.c | 15 +++++++++++++++
 include/linux/kgdb.h             |  1 +
 include/linux/serial_core.h      |  1 +
 include/linux/tty_driver.h       |  1 +
 5 files changed, 28 insertions(+)

diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c
index 2b42a01..0aa08c8 100644
--- a/drivers/tty/serial/kgdboc.c
+++ b/drivers/tty/serial/kgdboc.c
@@ -227,6 +227,15 @@ static int kgdboc_get_char(void)
 						kgdb_tty_line);
 }
 
+static void kgdboc_clear_irqs(void)
+{
+	if (!kgdb_tty_driver)
+		return;
+	if (kgdb_tty_driver->ops->clear_irqs)
+		kgdb_tty_driver->ops->clear_irqs(kgdb_tty_driver,
+						 kgdb_tty_line);
+}
+
 static void kgdboc_put_char(u8 chr)
 {
 	if (!kgdb_tty_driver)
@@ -298,6 +307,7 @@ static struct kgdb_io kgdboc_io_ops = {
 	.name			= "kgdboc",
 	.read_char		= kgdboc_get_char,
 	.write_char		= kgdboc_put_char,
+	.clear_irqs		= kgdboc_clear_irqs,
 	.pre_exception		= kgdboc_pre_exp_handler,
 	.post_exception		= kgdboc_post_exp_handler,
 };
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index cba8443..908d108 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2169,6 +2169,20 @@ static void uart_poll_put_char(struct tty_driver *driver, int line, char ch)
 	port = state->uart_port;
 	port->ops->poll_put_char(port, ch);
 }
+
+static void uart_clear_irqs(struct tty_driver *driver, int line)
+{
+	struct uart_driver *drv = driver->driver_state;
+	struct uart_state *state = drv->state + line;
+	struct uart_port *port;
+
+	if (!state || !state->uart_port)
+		return;
+
+	port = state->uart_port;
+	if (port->ops->clear_irqs)
+		port->ops->clear_irqs(port);
+}
 #endif
 
 static const struct tty_operations uart_ops = {
@@ -2201,6 +2215,7 @@ static const struct tty_operations uart_ops = {
 	.poll_init	= uart_poll_init,
 	.poll_get_char	= uart_poll_get_char,
 	.poll_put_char	= uart_poll_put_char,
+	.clear_irqs	= uart_clear_irqs,
 #endif
 };
 
diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h
index 3b111a6..1fd1cf0 100644
--- a/include/linux/kgdb.h
+++ b/include/linux/kgdb.h
@@ -295,6 +295,7 @@ struct kgdb_io {
 	const char		*name;
 	int			(*read_char) (void);
 	void			(*write_char) (u8);
+	void			(*clear_irqs) (void);
 	void			(*flush) (void);
 	int			(*init) (void);
 	void			(*pre_exception) (void);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 3642710..114b3f3 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -277,6 +277,7 @@ struct uart_ops {
 	int		(*poll_init)(struct uart_port *);
 	void	(*poll_put_char)(struct uart_port *, unsigned char);
 	int		(*poll_get_char)(struct uart_port *);
+	void	(*clear_irqs)(struct uart_port *);
 #endif
 };
 
diff --git a/include/linux/tty_driver.h b/include/linux/tty_driver.h
index 6e6dbb7..94b14cd 100644
--- a/include/linux/tty_driver.h
+++ b/include/linux/tty_driver.h
@@ -287,6 +287,7 @@ struct tty_operations {
 	int (*poll_init)(struct tty_driver *driver, int line, char *options);
 	int (*poll_get_char)(struct tty_driver *driver, int line);
 	void (*poll_put_char)(struct tty_driver *driver, int line, char ch);
+	void (*clear_irqs)(struct tty_driver *driver, int line);
 #endif
 	const struct file_operations *proc_fops;
 };
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:25 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:25 -0700
Subject: [PATCH 07/12] tty/serial/amba-pl011: Implement clear_irqs callback
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-7-git-send-email-anton.vorontsov@linaro.org>

It's all pretty straightforward, except for TXIM interrupt. The interrupt
has meaning "ready to transmit", so it's almost always raised, and the
only way to silence it is to mask it. But that's OK, ops->start_tx will
unmask it.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/tty/serial/amba-pl011.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 90f2302..cf9278c 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1308,6 +1308,18 @@ static void pl010_put_poll_char(struct uart_port *port,
 	writew(ch, uap->port.membase + UART01x_DR);
 }
 
+static void pl010_clear_irqs(struct uart_port *port)
+{
+	struct uart_amba_port *uap = (struct uart_amba_port *)port;
+	unsigned char __iomem *regs = uap->port.membase;
+
+	writew(readw(regs + UART011_MIS), regs + UART011_ICR);
+	/*
+	 * There is no way to clear TXIM, this is "ready to transmit IRQ", so
+	 * we simply mask it. ops->start_tx will unmask it.
+	 */
+	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
+}
 #endif /* CONFIG_CONSOLE_POLL */
 
 static int pl011_hwinit(struct uart_port *port)
@@ -1721,6 +1733,7 @@ static struct uart_ops amba_pl011_pops = {
 	.poll_init	= pl011_hwinit,
 	.poll_get_char = pl010_get_poll_char,
 	.poll_put_char = pl010_put_poll_char,
+	.clear_irqs    = pl010_clear_irqs,
 #endif
 };
 
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:26 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:26 -0700
Subject: =?UTF-8?q?=5BPATCH=2008/12=5D=20tty/serial=3A=20Add=20kgdb=5Fnmi=20driver?=
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-8-git-send-email-anton.vorontsov@linaro.org>

This special driver makes it possible to temporary use NMI debugger port
as a normal console by issuing 'nmi_console' command (assuming that the
port is attached to KGDB).

Unlike KDB's disable_nmi command, with this driver you are always able
to go back to the debugger using KGDB escape sequence ($3#33).  This is
because this console driver processes the input in NMI context, and thus
is able to intercept the magic sequence.

Note that since the console interprets input and uses polling
communication methods, for things like PPP it is still better to fully
detach debugger port from the KGDB NMI (i.e. disable_nmi), and use raw
console.

Usually, to enter the debugger one have to type the magic sequence, so
initially the kernel will print the following prompt on the NMI debugger
console:

	Type $3#33 to enter the debugger>

For convenience, there is a kgdb_fiq.knock kernel command line option,
when set to 0, this turns the special command to just a return key
press, so the kernel will be printing this:

	Hit <return> to enter the debugger>

This is more convenient for long debugging sessions, although it makes
nmi_console feature somewhat useless.

And for the cases when NMI connected to a dedicated button, the knocking
can be disabled altogether by setting kgdb_fiq.knock to -1.

Suggested-by: Colin Cross <ccross at android.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 drivers/tty/serial/Kconfig    |  19 +++
 drivers/tty/serial/Makefile   |   1 +
 drivers/tty/serial/kgdb_nmi.c | 348 ++++++++++++++++++++++++++++++++++++++++++
 drivers/tty/serial/kgdboc.c   |   6 +
 include/linux/kgdb.h          |  10 ++
 5 files changed, 384 insertions(+)
 create mode 100644 drivers/tty/serial/kgdb_nmi.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 4720b4b..32d6d3f 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -141,6 +141,25 @@ config SERIAL_ATMEL_TTYAT
 
 	  Say Y if you have an external 8250/16C550 UART.  If unsure, say N.
 
+config SERIAL_KGDB_NMI
+	bool "Serial console over KGDB NMI debugger port"
+	depends on KGDB_SERIAL_CONSOLE
+	help
+	  This special driver allows you to temporary use NMI debugger port
+	  as a normal console (assuming that the port is attached to KGDB).
+
+	  Unlike KDB's disable_nmi command, with this driver you are always
+	  able to go back to the debugger using KGDB escape sequence ($3#33).
+	  This is because this console driver processes the input in NMI
+	  context, and thus is able to intercept the magic sequence.
+
+	  Note that since the console interprets input and uses polling
+	  communication methods, for things like PPP you still must fully
+	  detach debugger port from the KGDB NMI (i.e. disable_nmi), and
+	  use raw console.
+
+	  If unsure, say N.
+
 config SERIAL_KS8695
 	bool "Micrel KS8695 (Centaur) serial port support"
 	depends on ARCH_KS8695
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 7257c5d..7a61d52 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SERIAL_MSM_HS) += msm_serial_hs.o
 obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
 obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
 obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
+obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o
 obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
 obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
 obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
diff --git a/drivers/tty/serial/kgdb_nmi.c b/drivers/tty/serial/kgdb_nmi.c
new file mode 100644
index 0000000..e1cd1be
--- /dev/null
+++ b/drivers/tty/serial/kgdb_nmi.c
@@ -0,0 +1,348 @@
+/*
+ * KGDB NMI serial console
+ *
+ * Copyright 2010 Google, Inc.
+ *		  Arve Hj?nnev?g <arve at android.com>
+ *		  Colin Cross <ccross at android.com>
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/compiler.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/atomic.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/interrupt.h>
+#include <linux/hrtimer.h>
+#include <linux/tick.h>
+#include <linux/kfifo.h>
+#include <linux/kgdb.h>
+#include <linux/kdb.h>
+
+static int kgdb_nmi_knock = 1;
+module_param_named(knock, kgdb_nmi_knock, int, 0600);
+MODULE_PARM_DESC(knock, "if set to 1 (default), the special '$3#33' command "
+			"must be used to enter the debugger; when set to 0, "
+			"hitting return key is enough to enter the debugger; "
+			"when set to -1, the debugger is entered immediately "
+			"upon NMI");
+
+static bool kgdb_nmi_tty_enabled;
+
+static void kgdb_nmi_console_write(struct console *co, const char *s, uint c)
+{
+	int i;
+
+	if (!kgdb_nmi_tty_enabled || atomic_read(&kgdb_active) >= 0)
+		return;
+
+	for (i = 0; i < c; i++)
+		dbg_io_ops->write_char(s[i]);
+}
+
+static struct tty_driver *kgdb_nmi_tty_driver;
+
+static struct tty_driver *kgdb_nmi_console_device(struct console *co, int *idx)
+{
+	*idx = co->index;
+	return kgdb_nmi_tty_driver;
+}
+
+static struct console kgdb_nmi_console = {
+	.name	= "ttyNMI",
+	.write	= kgdb_nmi_console_write,
+	.device	= kgdb_nmi_console_device,
+	.flags	= CON_PRINTBUFFER | CON_ANYTIME | CON_ENABLED,
+	.index	= -1,
+};
+
+/*
+ * This is usually the maximum rate on debug ports. We make fifo large enough
+ * to make copy-pasting to the terminal usable.
+ */
+#define KGDB_NMI_BAUD		115200
+#define KGDB_NMI_FIFO_SIZE	roundup_pow_of_two(KGDB_NMI_BAUD / 8 / HZ)
+
+struct kgdb_nmi_tty_priv {
+	int opened;
+	struct tty_struct *tty;
+	struct tasklet_struct tlet;
+	STRUCT_KFIFO(char, KGDB_NMI_FIFO_SIZE) fifo;
+};
+
+/*
+ * Our debugging console is polled in a tasklet, so we'll check for input
+ * every tick. In HZ-less mode, we should program the next tick.  We have
+ * to use the lowlevel stuff as no locks should be grabbed.
+ */
+#ifdef CONFIG_HIGH_RES_TIMERS
+static void kgdb_tty_poke(void)
+{
+	tick_program_event(ktime_get(), 0);
+}
+#else
+static inline void kgdb_tty_poke(void) {}
+#endif
+
+static struct tty_struct *kgdb_nmi_tty;
+
+static void kgdb_tty_recv(int ch)
+{
+	struct kgdb_nmi_tty_priv *priv;
+	char c = ch;
+
+	if (!kgdb_nmi_tty || ch < 0)
+		return;
+
+	priv = kgdb_nmi_tty->driver_data;
+	kfifo_in(&priv->fifo, &c, 1);
+	kgdb_tty_poke();
+}
+
+static int kgdb_nmi_poll_one_knock(void)
+{
+	static int n;
+	int c = -1;
+	char magic[] = "$3#33";
+	size_t m = strlen(magic);
+	bool printch = 0;
+
+	c = dbg_io_ops->read_char();
+	if (c == NO_POLL_CHAR)
+		return c;
+
+	if (!kgdb_nmi_knock && (c == '\r' || c == '\n')) {
+		return 1;
+	} else if (c == magic[n]) {
+		n = (n + 1) % m;
+		if (!n)
+			return 1;
+		printch = 1;
+	} else {
+		n = 0;
+	}
+
+	if (kgdb_nmi_tty_enabled) {
+		kgdb_tty_recv(c);
+		return 0;
+	}
+
+	if (printch) {
+		kdb_printf("%c", c);
+		return 0;
+	}
+
+	kdb_printf("\r%s %s to enter the debugger> %*s",
+		   kgdb_nmi_knock ? "Type" : "Hit",
+		   kgdb_nmi_knock ? magic  : "<return>", m, "");
+	memset(magic, '\b', m);
+	kdb_printf("%s", magic);
+	return 0;
+}
+
+/**
+ * kgdb_nmi_poll_knock - Check if it is time to enter the debugger
+ *
+ * "Serial ports are often noisy, especially when muxed over another port (we
+ * often use serial over the headset connector). Noise on the async command
+ * line just causes characters that are ignored, on a command line that blocked
+ * execution noise would be catastrophic." -- Colin Cross
+ *
+ * So, this function implements KGDB/KDB knocking on the serial line: we won't
+ * enter the debugger until we receive a known magic phrase (which is actually
+ * "$3#33", known as "escape to KDB" command. There is also a relaxed variant
+ * of knocking, i.e. just pressing the return key is enough to enter the
+ * debugger. And if knocking is disabled, the function always returns 1.
+ */
+bool kgdb_nmi_poll_knock(void)
+{
+	if (kgdb_nmi_knock < 0)
+		return 1;
+
+	dbg_io_ops->clear_irqs();
+
+	while (1) {
+		int ret;
+
+		ret = kgdb_nmi_poll_one_knock();
+		if (ret == NO_POLL_CHAR)
+			return 0;
+		else if (ret == 1)
+			break;
+	}
+	return 1;
+}
+
+static void kgdb_nmi_tty_receiver(unsigned long data)
+{
+	struct kgdb_nmi_tty_priv *priv = (void *)data;
+	char ch;
+
+	tasklet_schedule(&priv->tlet);
+
+	if (likely(!kgdb_nmi_tty_enabled || !kfifo_len(&priv->fifo)))
+		return;
+
+	while (kfifo_out(&priv->fifo, &ch, 1))
+		tty_insert_flip_char(priv->tty, ch, TTY_NORMAL);
+	tty_flip_buffer_push(priv->tty);
+}
+
+static DEFINE_MUTEX(kgdb_nmi_tty_mutex);
+
+static int kgdb_nmi_tty_open(struct tty_struct *tty, struct file *file)
+{
+	struct kgdb_nmi_tty_priv *priv;
+	int ret = 0;
+
+	mutex_lock(&kgdb_nmi_tty_mutex);
+
+	priv = tty->driver_data;
+	if (priv)
+		goto out;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	kgdb_nmi_tty = tty;
+	priv->tty = tty;
+	INIT_KFIFO(priv->fifo);
+	tty->driver_data = priv;
+
+	/*
+	 * The tasklet is cheap, it does not cause wakeups when reschedules
+	 * itself, instead it waits for the next tick.
+	 */
+	tasklet_init(&priv->tlet, kgdb_nmi_tty_receiver, (unsigned long)priv);
+	tasklet_schedule(&priv->tlet);
+out:
+	priv->opened++;
+err:
+	mutex_unlock(&kgdb_nmi_tty_mutex);
+	return ret;
+}
+
+static void kgdb_nmi_tty_close(struct tty_struct *tty, struct file *file)
+{
+	struct kgdb_nmi_tty_priv *priv;
+
+	mutex_lock(&kgdb_nmi_tty_mutex);
+
+	priv = tty->driver_data;
+	if (--priv->opened)
+		goto out;
+
+	tasklet_kill(&priv->tlet);
+	kgdb_nmi_tty = NULL;
+	kfree(priv);
+out:
+	mutex_unlock(&kgdb_nmi_tty_mutex);
+}
+
+static int kgdb_nmi_tty_write_room(struct tty_struct *tty)
+{
+	/* Actually, we can handle any amount as we use polled writes. */
+	return 2048;
+}
+
+static int kgdb_nmi_tty_write(struct tty_struct *tty, const unchar *buf, int c)
+{
+	int i;
+
+	for (i = 0; i < c; i++)
+		dbg_io_ops->write_char(buf[i]);
+	return c;
+}
+
+static const struct tty_operations kgdb_nmi_tty_ops = {
+	.open		= kgdb_nmi_tty_open,
+	.close		= kgdb_nmi_tty_close,
+	.write_room	= kgdb_nmi_tty_write_room,
+	.write		= kgdb_nmi_tty_write,
+};
+
+static int kgdb_nmi_enable_console(int argc, const char *argv[])
+{
+	kgdb_nmi_tty_enabled = !(argc == 1 && !strcmp(argv[1], "off"));
+	return 0;
+}
+
+int kgdb_register_nmi_console(void)
+{
+	int ret;
+
+	kgdb_nmi_tty_driver = alloc_tty_driver(1);
+	if (!kgdb_nmi_tty_driver) {
+		pr_err("%s: cannot allocate tty\n", __func__);
+		return -ENOMEM;
+	}
+	kgdb_nmi_tty_driver->driver_name	= "ttyNMI";
+	kgdb_nmi_tty_driver->name		= "ttyNMI";
+	kgdb_nmi_tty_driver->type		= TTY_DRIVER_TYPE_SERIAL;
+	kgdb_nmi_tty_driver->subtype		= SERIAL_TYPE_NORMAL;
+	kgdb_nmi_tty_driver->flags		= TTY_DRIVER_REAL_RAW |
+						  TTY_DRIVER_DYNAMIC_DEV;
+	kgdb_nmi_tty_driver->init_termios	= tty_std_termios;
+	tty_termios_encode_baud_rate(&kgdb_nmi_tty_driver->init_termios,
+				     KGDB_NMI_BAUD, KGDB_NMI_BAUD);
+	tty_set_operations(kgdb_nmi_tty_driver, &kgdb_nmi_tty_ops);
+
+	ret = tty_register_driver(kgdb_nmi_tty_driver);
+	if (ret) {
+		pr_err("%s: unable to register tty: %d\n", __func__, ret);
+		goto err_tty_reg;
+	}
+
+	ret = kdb_register("nmi_console", kgdb_nmi_enable_console, "[off]",
+			   "switch to Linux NMI console", 0);
+	if (ret) {
+		pr_err("%s: unable to register kdb command: %d\n",
+		       __func__, ret);
+		goto err_kdb_reg;
+	}
+
+	register_console(&kgdb_nmi_console);
+	kgdb_enable_nmi(1);
+
+	return 0;
+err_kdb_reg:
+	tty_unregister_driver(kgdb_nmi_tty_driver);
+err_tty_reg:
+	put_tty_driver(kgdb_nmi_tty_driver);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(kgdb_register_nmi_console);
+
+int kgdb_unregister_nmi_console(void)
+{
+	int ret;
+
+	kgdb_enable_nmi(0);
+
+	ret = tty_unregister_driver(kgdb_nmi_tty_driver);
+	if (ret)
+		return ret;
+	put_tty_driver(kgdb_nmi_tty_driver);
+
+	ret = unregister_console(&kgdb_nmi_console);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(kgdb_unregister_nmi_console);
diff --git a/drivers/tty/serial/kgdboc.c b/drivers/tty/serial/kgdboc.c
index 0aa08c8..bb69803 100644
--- a/drivers/tty/serial/kgdboc.c
+++ b/drivers/tty/serial/kgdboc.c
@@ -145,6 +145,8 @@ __setup("kgdboc=", kgdboc_option_setup);
 
 static void cleanup_kgdboc(void)
 {
+	if (kgdb_unregister_nmi_console())
+		return;
 	kgdboc_unregister_kbd();
 	if (configured == 1)
 		kgdb_unregister_io_module(&kgdboc_io_ops);
@@ -198,6 +200,10 @@ do_register:
 	if (err)
 		goto noconfig;
 
+	err = kgdb_register_nmi_console();
+	if (err)
+		goto noconfig;
+
 	configured = 1;
 
 	return 0;
diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h
index 1fd1cf0..fb7c55c 100644
--- a/include/linux/kgdb.h
+++ b/include/linux/kgdb.h
@@ -245,6 +245,16 @@ extern void kgdb_arch_enable_nmi(bool on);
  */
 extern int kgdb_enable_nmi(bool on);
 
+#ifdef CONFIG_SERIAL_KGDB_NMI
+extern int kgdb_register_nmi_console(void);
+extern int kgdb_unregister_nmi_console(void);
+extern bool kgdb_nmi_poll_knock(void);
+#else
+static inline int kgdb_register_nmi_console(void) { return 0; }
+static inline int kgdb_unregister_nmi_console(void) { return 0; }
+static inline bool kgdb_nmi_poll_knock(void) { return 1; }
+#endif
+
 /**
  * struct kgdb_arch - Describe architecture specific values.
  * @gdb_bpt_instr: The instruction to trigger a breakpoint.
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:27 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:27 -0700
Subject: [PATCH 09/12] ARM: Move some macros from entry-armv to entry-header
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-9-git-send-email-anton.vorontsov@linaro.org>

Just move the macros into header file as we would want to use them for
KGDB FIQ entry code.

The following macros were moved:

 - svc_entry
 - usr_entry
 - kuser_cmpxchg_check
 - vector_stub

To make kuser_cmpxchg_check actually work across different files, we
also have to make kuser_cmpxchg64_fixup global.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/kernel/entry-armv.S   | 167 +---------------------------------------
 arch/arm/kernel/entry-header.S | 170 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 171 insertions(+), 166 deletions(-)

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098..0f15368 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -136,57 +136,6 @@ common_invalid:
 	b	bad_mode
 ENDPROC(__und_invalid)
 
-/*
- * SVC mode handlers
- */
-
-#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
-#define SPFIX(code...) code
-#else
-#define SPFIX(code...)
-#endif
-
-	.macro	svc_entry, stack_hole=0
- UNWIND(.fnstart		)
- UNWIND(.save {r0 - pc}		)
-	sub	sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
-#ifdef CONFIG_THUMB2_KERNEL
- SPFIX(	str	r0, [sp]	)	@ temporarily saved
- SPFIX(	mov	r0, sp		)
- SPFIX(	tst	r0, #4		)	@ test original stack alignment
- SPFIX(	ldr	r0, [sp]	)	@ restored
-#else
- SPFIX(	tst	sp, #4		)
-#endif
- SPFIX(	subeq	sp, sp, #4	)
-	stmia	sp, {r1 - r12}
-
-	ldmia	r0, {r3 - r5}
-	add	r7, sp, #S_SP - 4	@ here for interlock avoidance
-	mov	r6, #-1			@  ""  ""      ""       ""
-	add	r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
- SPFIX(	addeq	r2, r2, #4	)
-	str	r3, [sp, #-4]!		@ save the "real" r0 copied
-					@ from the exception stack
-
-	mov	r3, lr
-
-	@
-	@ We are now ready to fill in the remaining blanks on the stack:
-	@
-	@  r2 - sp_svc
-	@  r3 - lr_svc
-	@  r4 - lr_<exception>, already fixed up for correct return/restart
-	@  r5 - spsr_<exception>
-	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
-	@
-	stmia	r7, {r2 - r6}
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-	bl	trace_hardirqs_off
-#endif
-	.endm
-
 	.align	5
 __dabt_svc:
 	svc_entry
@@ -348,71 +297,8 @@ ENDPROC(__pabt_svc)
 
 /*
  * User mode handlers
- *
- * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
  */
 
-#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
-#error "sizeof(struct pt_regs) must be a multiple of 8"
-#endif
-
-	.macro	usr_entry
- UNWIND(.fnstart	)
- UNWIND(.cantunwind	)	@ don't unwind the user space
-	sub	sp, sp, #S_FRAME_SIZE
- ARM(	stmib	sp, {r1 - r12}	)
- THUMB(	stmia	sp, {r0 - r12}	)
-
-	ldmia	r0, {r3 - r5}
-	add	r0, sp, #S_PC		@ here for interlock avoidance
-	mov	r6, #-1			@  ""  ""     ""        ""
-
-	str	r3, [sp]		@ save the "real" r0 copied
-					@ from the exception stack
-
-	@
-	@ We are now ready to fill in the remaining blanks on the stack:
-	@
-	@  r4 - lr_<exception>, already fixed up for correct return/restart
-	@  r5 - spsr_<exception>
-	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
-	@
-	@ Also, separately save sp_usr and lr_usr
-	@
-	stmia	r0, {r4 - r6}
- ARM(	stmdb	r0, {sp, lr}^			)
- THUMB(	store_user_sp_lr r0, r1, S_SP - S_PC	)
-
-	@
-	@ Enable the alignment trap while in kernel mode
-	@
-	alignment_trap r0
-
-	@
-	@ Clear FP to mark the first stack frame
-	@
-	zero_fp
-
-#ifdef CONFIG_IRQSOFF_TRACER
-	bl	trace_hardirqs_off
-#endif
-	.endm
-
-	.macro	kuser_cmpxchg_check
-#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
-#ifndef CONFIG_MMU
-#warning "NPTL on non MMU needs fixing"
-#else
-	@ Make sure our user space atomic helper is restarted
-	@ if it was interrupted in a critical region.  Here we
-	@ perform a quick test inline since it should be false
-	@ 99.9999% of the time.  The rest is done out of line.
-	cmp	r4, #TASK_SIZE
-	blhs	kuser_cmpxchg64_fixup
-#endif
-#endif
-	.endm
-
 	.align	5
 __dabt_usr:
 	usr_entry
@@ -846,6 +732,7 @@ __kuser_cmpxchg64:				@ 0xffff0f60
 	ldmfd	sp!, {r4, r5, r6, pc}
 
 	.text
+	.global kuser_cmpxchg64_fixup
 kuser_cmpxchg64_fixup:
 	@ Called from kuser_cmpxchg_fixup.
 	@ r4 = address of interrupted insn (must be preserved).
@@ -976,58 +863,6 @@ __kuser_helper_end:
 
  THUMB(	.thumb	)
 
-/*
- * Vector stubs.
- *
- * This code is copied to 0xffff0200 so we can use branches in the
- * vectors, rather than ldr's.  Note that this code must not
- * exceed 0x300 bytes.
- *
- * Common stub entry macro:
- *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
- *
- * SP points to a minimal amount of processor-private memory, the address
- * of which is copied into r0 for the mode specific abort handler.
- */
-	.macro	vector_stub, name, mode, correction=0
-	.align	5
-
-vector_\name:
-	.if \correction
-	sub	lr, lr, #\correction
-	.endif
-
-	@
-	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
-	@ (parent CPSR)
-	@
-	stmia	sp, {r0, lr}		@ save r0, lr
-	mrs	lr, spsr
-	str	lr, [sp, #8]		@ save spsr
-
-	@
-	@ Prepare for SVC32 mode.  IRQs remain disabled.
-	@
-	mrs	r0, cpsr
-	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
-	msr	spsr_cxsf, r0
-
-	@
-	@ the branch table must immediately follow this code
-	@
-	and	lr, lr, #0x0f
- THUMB(	adr	r0, 1f			)
- THUMB(	ldr	lr, [r0, lr, lsl #2]	)
-	mov	r0, sp
- ARM(	ldr	lr, [pc, lr, lsl #2]	)
-	movs	pc, lr			@ branch to handler in SVC mode
-ENDPROC(vector_\name)
-
-	.align	2
-	@ handler addresses follow this label
-1:
-	.endm
-
 	.globl	__stubs_start
 __stubs_start:
 /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531e..c3c09ac 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -73,6 +73,109 @@
 	msr	cpsr_c, \rtemp			@ switch back to the SVC mode
 	.endm
 
+/*
+ * Vector stubs.
+ *
+ * This code is copied to 0xffff0200 so we can use branches in the
+ * vectors, rather than ldr's.  Note that this code must not
+ * exceed 0x300 bytes.
+ *
+ * Common stub entry macro:
+ *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
+ *
+ * SP points to a minimal amount of processor-private memory, the address
+ * of which is copied into r0 for the mode specific abort handler.
+ */
+	.macro	vector_stub, name, mode, correction=0
+	.align	5
+
+vector_\name:
+	.if \correction
+	sub	lr, lr, #\correction
+	.endif
+
+	@
+	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
+	@ (parent CPSR)
+	@
+	stmia	sp, {r0, lr}		@ save r0, lr
+	mrs	lr, spsr
+	str	lr, [sp, #8]		@ save spsr
+
+	@
+	@ Prepare for SVC32 mode.  IRQs remain disabled.
+	@
+	mrs	r0, cpsr
+	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
+	msr	spsr_cxsf, r0
+
+	@
+	@ the branch table must immediately follow this code
+	@
+	and	lr, lr, #0x0f
+ THUMB(	adr	r0, 1f			)
+ THUMB(	ldr	lr, [r0, lr, lsl #2]	)
+	mov	r0, sp
+ ARM(	ldr	lr, [pc, lr, lsl #2]	)
+	movs	pc, lr			@ branch to handler in SVC mode
+ENDPROC(vector_\name)
+
+	.align	2
+	@ handler addresses follow this label
+1:
+	.endm
+
+/*
+ * SVC mode handlers
+ */
+
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
+#define SPFIX(code...) code
+#else
+#define SPFIX(code...)
+#endif
+
+	.macro	svc_entry, stack_hole=0
+ UNWIND(.fnstart		)
+ UNWIND(.save {r0 - pc}		)
+	sub	sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+#ifdef CONFIG_THUMB2_KERNEL
+ SPFIX(	str	r0, [sp]	)	@ temporarily saved
+ SPFIX(	mov	r0, sp		)
+ SPFIX(	tst	r0, #4		)	@ test original stack alignment
+ SPFIX(	ldr	r0, [sp]	)	@ restored
+#else
+ SPFIX(	tst	sp, #4		)
+#endif
+ SPFIX(	subeq	sp, sp, #4	)
+	stmia	sp, {r1 - r12}
+
+	ldmia	r0, {r3 - r5}
+	add	r7, sp, #S_SP - 4	@ here for interlock avoidance
+	mov	r6, #-1			@  ""  ""      ""       ""
+	add	r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+ SPFIX(	addeq	r2, r2, #4	)
+	str	r3, [sp, #-4]!		@ save the "real" r0 copied
+					@ from the exception stack
+
+	mov	r3, lr
+
+	@
+	@ We are now ready to fill in the remaining blanks on the stack:
+	@
+	@  r2 - sp_svc
+	@  r3 - lr_svc
+	@  r4 - lr_<exception>, already fixed up for correct return/restart
+	@  r5 - spsr_<exception>
+	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
+	@
+	stmia	r7, {r2 - r6}
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+	bl	trace_hardirqs_off
+#endif
+	.endm
+
 #ifndef CONFIG_THUMB2_KERNEL
 	.macro	svc_exit, rpsr
 	msr	spsr_cxsf, \rpsr
@@ -164,6 +267,73 @@
 #endif	/* !CONFIG_THUMB2_KERNEL */
 
 /*
+ * User mode handlers
+ *
+ * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
+ */
+
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
+#error "sizeof(struct pt_regs) must be a multiple of 8"
+#endif
+
+	.macro	usr_entry
+ UNWIND(.fnstart	)
+ UNWIND(.cantunwind	)	@ don't unwind the user space
+	sub	sp, sp, #S_FRAME_SIZE
+ ARM(	stmib	sp, {r1 - r12}	)
+ THUMB(	stmia	sp, {r0 - r12}	)
+
+	ldmia	r0, {r3 - r5}
+	add	r0, sp, #S_PC		@ here for interlock avoidance
+	mov	r6, #-1			@  ""  ""     ""        ""
+
+	str	r3, [sp]		@ save the "real" r0 copied
+					@ from the exception stack
+
+	@
+	@ We are now ready to fill in the remaining blanks on the stack:
+	@
+	@  r4 - lr_<exception>, already fixed up for correct return/restart
+	@  r5 - spsr_<exception>
+	@  r6 - orig_r0 (see pt_regs definition in ptrace.h)
+	@
+	@ Also, separately save sp_usr and lr_usr
+	@
+	stmia	r0, {r4 - r6}
+ ARM(	stmdb	r0, {sp, lr}^			)
+ THUMB(	store_user_sp_lr r0, r1, S_SP - S_PC	)
+
+	@
+	@ Enable the alignment trap while in kernel mode
+	@
+	alignment_trap r0
+
+	@
+	@ Clear FP to mark the first stack frame
+	@
+	zero_fp
+
+#ifdef CONFIG_IRQSOFF_TRACER
+	bl	trace_hardirqs_off
+#endif
+	.endm
+
+	.macro	kuser_cmpxchg_check
+#if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
+#ifndef CONFIG_MMU
+#warning "NPTL on non MMU needs fixing"
+#else
+	@ Make sure our user space atomic helper is restarted
+	@ if it was interrupted in a critical region.  Here we
+	@ perform a quick test inline since it should be false
+	@ 99.9999% of the time.  The rest is done out of line.
+	cmp	r4, #TASK_SIZE
+	blhs	kuser_cmpxchg64_fixup
+#endif
+#endif
+	.endm
+
+/*
  * These are the registers used in the syscall handler, and allow us to
  * have in theory up to 7 arguments to a function - r0 to r6.
  *
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:28 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:28 -0700
Subject: =?UTF-8?q?=5BPATCH=2010/12=5D=20ARM=3A=20Add=20KGDB/KDB=20FIQ=20debugger=20generic=20code?=
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-10-git-send-email-anton.vorontsov@linaro.org>

The FIQ debugger may be used to debug situations when the kernel stuck
in uninterruptable sections, e.g. the kernel infinitely loops or
deadlocked in an interrupt or with interrupts disabled.

By default KGDB FIQ is disabled in runtime, but can be enabled with
kgdb_fiq.enable=1 kernel command line option.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/Kconfig                 | 18 ++++++++
 arch/arm/include/asm/kgdb.h      |  8 ++++
 arch/arm/kernel/Makefile         |  1 +
 arch/arm/kernel/kgdb_fiq.c       | 99 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/kgdb_fiq_entry.S | 87 +++++++++++++++++++++++++++++++++++
 5 files changed, 213 insertions(+)
 create mode 100644 arch/arm/kernel/kgdb_fiq.c
 create mode 100644 arch/arm/kernel/kgdb_fiq_entry.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..c978c74 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -171,6 +171,24 @@ config GENERIC_ISA_DMA
 config FIQ
 	bool
 
+config ARCH_MIGHT_HAVE_KGDB_FIQ
+	bool
+
+config KGDB_FIQ
+	bool "KGDB/KDB FIQ debugger"
+	depends on KGDB_KDB && ARCH_MIGHT_HAVE_KGDB_FIQ && !THUMB2_KERNEL
+	select FIQ
+	help
+	  The FIQ debugger may be used to debug situations when the
+	  kernel stuck in uninterruptable sections, e.g. the kernel
+	  infinitely loops or deadlocked in an interrupt or with
+	  interrupts disabled.
+
+	  By default KGDB FIQ is disabled in runtime, but can be
+	  enabled with kgdb_fiq.enable=1 kernel command line option.
+
+	  If unsure, say N.
+
 config NEED_RET_TO_USER
 	bool
 
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 48066ce..807e547 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -11,6 +11,8 @@
 #define __ARM_KGDB_H__
 
 #include <linux/ptrace.h>
+#include <linux/linkage.h>
+#include <asm/exception.h>
 
 /*
  * GDB assumes that we're a user process being debugged, so
@@ -47,6 +49,12 @@ static inline void arch_kgdb_breakpoint(void)
 extern void kgdb_handle_bus_error(void);
 extern int kgdb_fault_expected;
 
+extern char kgdb_fiq_handler;
+extern char kgdb_fiq_handler_end;
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs);
+extern int __init kgdb_register_fiq(unsigned int mach_kgdb_fiq,
+		     void (*mach_kgdb_enable_fiq)(unsigned int irq, bool on),
+		     bool (*mach_is_kgdb_fiq)(unsigned int irq));
 #endif /* !__ASSEMBLY__ */
 
 /*
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..5aa079b 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_ATAGS_PROC)	+= atags.o
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
+obj-$(CONFIG_KGDB_FIQ)		+= kgdb_fiq_entry.o kgdb_fiq.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
 obj-$(CONFIG_OF)		+= devtree.o
diff --git a/arch/arm/kernel/kgdb_fiq.c b/arch/arm/kernel/kgdb_fiq.c
new file mode 100644
index 0000000..8443af1
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq.c
@@ -0,0 +1,99 @@
+/*
+ * KGDB FIQ
+ *
+ * Copyright 2010 Google, Inc.
+ *		  Arve Hj?nnev?g <arve at android.com>
+ *		  Colin Cross <ccross at android.com>
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/hardirq.h>
+#include <linux/kdb.h>
+#include <linux/kgdb.h>
+#include <asm/fiq.h>
+#include <asm/exception.h>
+
+static int kgdb_fiq_enabled;
+module_param_named(enable, kgdb_fiq_enabled, int, 0600);
+MODULE_PARM_DESC(enable, "set to 1 to enable FIQ KGDB");
+
+static unsigned int kgdb_fiq;
+static bool (*is_kgdb_fiq)(unsigned int irq);
+
+asmlinkage void __exception_irq_entry kgdb_fiq_do_handle(struct pt_regs *regs)
+{
+	if (!is_kgdb_fiq(kgdb_fiq))
+		return;
+	if (!kgdb_nmi_poll_knock())
+		return;
+
+	nmi_enter();
+	kgdb_handle_exception(1, 0, 0, regs);
+	nmi_exit();
+}
+
+static struct fiq_handler kgdb_fiq_desc = {
+	.name = "kgdb",
+};
+
+static long kgdb_fiq_setup_stack(void *info)
+{
+	struct pt_regs regs;
+
+	regs.ARM_sp = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER) +
+			THREAD_START_SP;
+	WARN_ON(!regs.ARM_sp);
+
+	set_fiq_regs(&regs);
+	return 0;
+}
+
+static void (*kgdb_enable_fiq)(unsigned int irq, bool on);
+
+void kgdb_arch_enable_nmi(bool on)
+{
+	if (!kgdb_enable_fiq)
+		return;
+	kgdb_enable_fiq(kgdb_fiq, on);
+}
+
+int __init kgdb_register_fiq(unsigned int mach_kgdb_fiq,
+		void (*mach_kgdb_enable_fiq)(unsigned int irq, bool on),
+		bool (*mach_is_kgdb_fiq)(unsigned int irq))
+{
+	int err;
+	int cpu;
+
+	if (!kgdb_fiq_enabled)
+		return -ENODEV;
+	if (kgdb_fiq)
+		return -EBUSY;
+
+	kgdb_fiq = mach_kgdb_fiq;
+	kgdb_enable_fiq = mach_kgdb_enable_fiq;
+	is_kgdb_fiq = mach_is_kgdb_fiq;
+
+	err = claim_fiq(&kgdb_fiq_desc);
+	if (err) {
+		pr_warn("%s: unable to claim fiq", __func__);
+		return err;
+	}
+
+	for_each_possible_cpu(cpu)
+		work_on_cpu(cpu, kgdb_fiq_setup_stack, NULL);
+
+	set_fiq_handler(&kgdb_fiq_handler,
+			&kgdb_fiq_handler_end - &kgdb_fiq_handler);
+
+	return 0;
+}
diff --git a/arch/arm/kernel/kgdb_fiq_entry.S b/arch/arm/kernel/kgdb_fiq_entry.S
new file mode 100644
index 0000000..d6becca
--- /dev/null
+++ b/arch/arm/kernel/kgdb_fiq_entry.S
@@ -0,0 +1,87 @@
+/*
+ * KGDB FIQ entry
+ *
+ * Copyright 1996,1997,1998 Russell King.
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/unwind.h>
+#include "entry-header.S"
+
+	.text
+
+@ This is needed for usr_entry/alignment_trap
+.LCcralign:
+	.long	cr_alignment
+.LCdohandle:
+	.long	kgdb_fiq_do_handle
+
+	.macro	fiq_handler
+	ldr	r1, =.LCdohandle
+	mov	r0, sp
+	adr	lr, BSYM(9997f)
+	ldr	pc, [r1]
+9997:
+	.endm
+
+	.align	5
+__fiq_svc:
+	svc_entry
+	fiq_handler
+	mov	r0, sp
+	ldmib	r0, {r1 - r14}
+	msr	cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	add	r8, r0, #S_PC
+	ldr	r9, [r0, #S_PSR]
+	msr	spsr_cxsf, r9
+	ldr	r0, [r0, #S_R0]
+	ldmia	r8, {pc}^
+
+ UNWIND(.fnend		)
+ENDPROC(__fiq_svc)
+	.ltorg
+
+	.align	5
+__fiq_usr:
+	usr_entry
+	kuser_cmpxchg_check
+	fiq_handler
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user_from_irq
+ UNWIND(.fnend		)
+ENDPROC(__fiq_usr)
+	.ltorg
+
+	.global kgdb_fiq_handler
+kgdb_fiq_handler:
+
+	vector_stub	fiq, FIQ_MODE, 4
+
+	.long	__fiq_usr			@  0  (USR_26 / USR_32)
+	.long	__fiq_svc			@  1  (FIQ_26 / FIQ_32)
+	.long	__fiq_svc			@  2  (IRQ_26 / IRQ_32)
+	.long	__fiq_svc			@  3  (SVC_26 / SVC_32)
+	.long	__fiq_svc			@  4
+	.long	__fiq_svc			@  5
+	.long	__fiq_svc			@  6
+	.long	__fiq_svc			@  7
+	.long	__fiq_svc			@  8
+	.long	__fiq_svc			@  9
+	.long	__fiq_svc			@  a
+	.long	__fiq_svc			@  b
+	.long	__fiq_svc			@  c
+	.long	__fiq_svc			@  d
+	.long	__fiq_svc			@  e
+	.long	__fiq_svc			@  f
+
+	.global kgdb_fiq_handler_end
+kgdb_fiq_handler_end:
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:29 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:29 -0700
Subject: [PATCH 11/12] ARM: VIC: Add a couple of low-level FIQ management
 helpers
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-11-git-send-email-anton.vorontsov@linaro.org>

Just a couple of calls to manage VIC FIQ routing. We'll use them for
KGDB FIQ support on ARM Versatile machines.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/common/vic.c               | 28 ++++++++++++++++++++++++++++
 arch/arm/include/asm/hardware/vic.h |  2 ++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index e0d5388..df2fc82 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -66,6 +66,34 @@ static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 
 static int vic_id;
 
+static void __iomem *vic_base(struct irq_data *d)
+{
+	return (void __iomem *)irq_data_get_irq_chip_data(d);
+}
+
+void vic_fiq_select(unsigned int irq, bool on)
+{
+	void __iomem *base = vic_base(&irq_to_desc(irq)->irq_data);
+	void __iomem *sel = base + VIC_INT_SELECT;
+	u32 msk = 1 << irq;
+	u32 val;
+
+	pr_debug("rerouting VIC vector %d to %s\n", irq, on ? "FIQ" : "IRQ");
+
+	val = readl(sel);
+	val &= ~msk;
+	if (on)
+		val |= msk;
+	writel(val, sel);
+}
+
+bool vic_is_fiq_rised(unsigned int irq)
+{
+	void __iomem *base = vic_base(&irq_to_desc(irq)->irq_data);
+
+	return readl(base + VIC_FIQ_STATUS) & (1 << irq);
+}
+
 /**
  * vic_init2 - common initialisation code
  * @base: Base of the VIC.
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index e14af1a..2728975 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -52,6 +52,8 @@ void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
 int vic_of_init(struct device_node *node, struct device_node *parent);
 void vic_handle_irq(struct pt_regs *regs);
+void vic_fiq_select(unsigned int irq, bool on);
+bool vic_is_fiq_rised(unsigned int irq);
 
 #endif /* __ASSEMBLY__ */
 #endif
-- 
1.7.11.5



From anton.vorontsov at linaro.org  Mon Aug 20 10:47:30 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 07:47:30 -0700
Subject: [PATCH 12/12] ARM: versatile: Make able to use UART ports for KGDB
 FIQ debugger
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <1345474050-8339-12-git-send-email-anton.vorontsov@linaro.org>

If enabled, kernel will able to enter KGDB upon serial line activity on
UART ports.

Note that even with this patch and CONFIG_KGDB_FIQ is enabled, you still
need to pass kgdb_fiq.enable=1 kernel command line option, otherwise UART
will behave in a normal way.

By default UART0 is used, but this can be changed via kgdb_fiq.uart_num
kernel command line option.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/Kconfig                   |  1 +
 arch/arm/mach-versatile/Makefile   |  1 +
 arch/arm/mach-versatile/kgdb_fiq.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 33 insertions(+)
 create mode 100644 arch/arm/mach-versatile/kgdb_fiq.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c978c74..689b716 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,6 +330,7 @@ config ARCH_VERSATILE
 	select ICST
 	select GENERIC_CLOCKEVENTS
 	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARCH_MIGHT_HAVE_KGDB_FIQ
 	select NEED_MACH_IO_H if PCI
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLOCK
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 81fa3fe..bfd761f 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_ARCH_VERSATILE_PB)		+= versatile_pb.o
 obj-$(CONFIG_MACH_VERSATILE_AB)		+= versatile_ab.o
 obj-$(CONFIG_MACH_VERSATILE_DT)		+= versatile_dt.o
 obj-$(CONFIG_PCI)			+= pci.o
+obj-$(CONFIG_KGDB_FIQ)			+= kgdb_fiq.o
diff --git a/arch/arm/mach-versatile/kgdb_fiq.c b/arch/arm/mach-versatile/kgdb_fiq.c
new file mode 100644
index 0000000..3cdf71d
--- /dev/null
+++ b/arch/arm/mach-versatile/kgdb_fiq.c
@@ -0,0 +1,31 @@
+/*
+ * KGDB FIQ board support
+ *
+ * Copyright 2012 Linaro Ltd.
+ *		  Anton Vorontsov <anton.vorontsov at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kgdb.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <asm/hardware/vic.h>
+
+static int kgdb_fiq;
+module_param_named(uart_num, kgdb_fiq, int, 0600);
+MODULE_PARM_DESC(uart_num, "UART<number> port to use for KGDB FIQ");
+
+static int __init kgdb_fiq_init(void)
+{
+	WARN_ON(kgdb_fiq > INT_UARTINT2 - INT_UARTINT0);
+
+	return kgdb_register_fiq(INT_UARTINT0 + kgdb_fiq,
+				 vic_fiq_select,
+				 vic_is_fiq_rised);
+}
+console_initcall(kgdb_fiq_init);
-- 
1.7.11.5



From sebastian.hesselbarth at gmail.com  Mon Aug 20 10:51:20 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 Aug 2012 16:51:20 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CACRpkdaozBQPe1PkjaKrnqYZ=tpX1mv1iS-rCrJaSFAsQqzgnA@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>	<1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>	<CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>	<CABJ1b_TCF=Jfb0uuoh-M87n6faezj4OqZ4S_nJLA0yKga2-ioQ@mail.gmail.com>
 <CACRpkdaozBQPe1PkjaKrnqYZ=tpX1mv1iS-rCrJaSFAsQqzgnA@mail.gmail.com>
Message-ID: <50324EE8.9010206@gmail.com>

On 08/20/2012 04:18 PM, Linus Walleij wrote:
>> I'll review the variant types but inside pinctrl-mvebu variant
>> is used as a bit mask to distinguish different variants. Anyway,
>> they should always be the same size.
>
> Aha bitmask, seems you can only have 8 different variants of
> the Marvell's then?

Only 8 different variants of one SoC! Currently, there are 5 for
Kirkwood, none for Dove. I think there are two more Kirkwood's that
never appeared in public, but it is still < 8.

>> Well, I see if I can clarify the description but wrt the datasheet it
>> _should_ be quite obvious.
>
> I mainly worry about being able to read the code and figure out
> what's going on, if the datasheet is vital then pls include some
> link to it or so in the header of the file (but preferrably the code
> should speak for itself).

Ok, I clarify whats meant by mvebu_*_ctrl/ctrl_setting/mode. I am not
that happy with that names either, but honestly pinctrl core already
took all names that I'd have chosen. Therefore, I chose some that do
not interfere with pinctrl core as the meaning is different.

Sebastian


From robherring2 at gmail.com  Mon Aug 20 10:54:18 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 20 Aug 2012 09:54:18 -0500
Subject: [PATCH 0/4] Per device coherent DMA map ops
In-Reply-To: <000601cd7ede$5d2ef390$178cdab0$%szyprowski@samsung.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
 <000601cd7ede$5d2ef390$178cdab0$%szyprowski@samsung.com>
Message-ID: <50324F9A.5000608@gmail.com>



On 08/20/2012 09:16 AM, Marek Szyprowski wrote:
> Hello,
> 
> On Tuesday, August 14, 2012 5:49 AM Rob Herring wrote:
> 
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> This is series adds coherent DMA map operations which can be set per device.
>> Expanding on the first RFC[1], this version adds iommu ops and implements
>> support on highbank platform.
>>
>> arch_is_coherent is never defined true since removing ixp2xxx, so we can
>> remove it altogether.
>>
>> Rob
>>
>> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/113921.html
>>
>> Rob Herring (4):
>>   ARM: add coherent dma ops
>>   ARM: add coherent iommu dma ops
>>   ARM: kill off arch_is_coherent
>>   ARM: highbank: add coherent DMA setup
>>
>>  .../devicetree/bindings/ata/ahci-platform.txt      |    3 +
>>  .../devicetree/bindings/dma/arm-pl330.txt          |    3 +
>>  .../devicetree/bindings/net/calxeda-xgmac.txt      |    3 +
>>  arch/arm/boot/dts/highbank.dts                     |    1 +
>>  arch/arm/include/asm/barrier.h                     |    7 +-
>>  arch/arm/include/asm/dma-mapping.h                 |    1 +
>>  arch/arm/include/asm/memory.h                      |    8 -
>>  arch/arm/mach-highbank/highbank.c                  |   52 ++++
>>  arch/arm/mm/dma-mapping.c                          |  254 ++++++++++++++++----
>>  arch/arm/mm/mmu.c                                  |   17 +-
>>  10 files changed, 271 insertions(+), 78 deletions(-)
> 
> I like those patches and I would like to take it to my dma-mapping-next tree, but I wonder 
> how to handle merging of the last patch. Arnd, Olof - could You tell me how to do it? I assume
> that it should be somehow merged by arm-soc tree, so it depends on the earlier patches.
> Would it be enough if I take them to the topic branch? Then I can continue works on 
> dma-mapping subsystem by merging that topic branch to my dma-mapping-next and you will
> also take it as a dependency for highbank patches. Am I right?
> 

I'm fine with it all going in thru your tree. Seems a bit silly to deal
with tracking the dependencies all for 1 patch. The only possible
conflict I see is with the dts file and some other SATA related changes
which will go in via the ata tree. But the merge is trivial and the
conflict will be there either with your tree or arm-soc.

Rob


From sebastian.hesselbarth at gmail.com  Mon Aug 20 10:54:27 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 Aug 2012 16:54:27 +0200
Subject: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig
In-Reply-To: <CACRpkdaF3OuBLC7odWyH5C_EJT9uFq1rYQMh6=kr8PQjvA68sA@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>	<1344689809-6223-12-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdaF3OuBLC7odWyH5C_EJT9uFq1rYQMh6=kr8PQjvA68sA@mail.gmail.com>
Message-ID: <50324FA3.9030005@gmail.com>

On 08/20/2012 04:31 PM, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <sebastian.hesselbarth at gmail.com>  wrote:
>> +CONFIG_PINCTRL_ARMADA_370=y
>> +CONFIG_PINCTRL_ARMADA_XP=y
>
> If the system is not even booting without pinctrl you should
> (IMHO) select these from the machine's Kconfig entry insteaf.

I don't have a strong opinion on this but I think most systems
will boot just fine without pinctrl. The basic stuff is set up
by u-boot. Anyway, I think we should enable pinctrl for each soc
by default.

Sebastian


From matt at genesi-usa.com  Mon Aug 20 10:54:48 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 20 Aug 2012 09:54:48 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <503232E0.3000007@gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
Message-ID: <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>

Yet another arbitrary array...

I'm not sure why you would move the registration lookup into the DT
and use an arbitrarily ordered array again. Sure, you're looking it up
entirely within the device tree here, but a better solution would be
to not name clocks twice, and structure your clock definition
properly.

What's wrong with;

ccm at 020c4000 {
   ...
   my_clock: clock at 0 {
       name = "my_clock_name";
   }
}

uart at nnnnnnnn {
   ...
   clocks = <&my_clock>;
}

?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Mon, Aug 20, 2012 at 7:51 AM, Rob Herring <robherring2 at gmail.com> wrote:
> On 08/16/2012 03:08 AM, Shawn Guo wrote:
>> It really becomes an issue that every time a device needs to look
>> up (clk_get) a clock we have to patch kernel clock file to call
>> clk_register_clkdev for that clock.
>>
>> Since clock DT support which is meant to resolve clock lookup in device
>> tree is in place, the patch moves imx6q client devices' clock lookup
>> over to device tree, so that any new lookup to be added at later time
>> can just get done in DT instead of kernel.
>>
>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>
> Looks good. For both patches:
>
> Reviewed-by: Rob Herring <rob.herring at calxeda.com>
>
>> ---
>>  .../devicetree/bindings/clock/imx6q-clock.txt      |  223 +++++++++++++++++
>>  arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
>>  arch/arm/boot/dts/imx6q.dtsi                       |  261 +++++++++++++++++++-
>>  arch/arm/mach-imx/clk-imx6q.c                      |   41 +---
>>  arch/arm/mach-imx/mach-imx6q.c                     |    1 -
>>  5 files changed, 477 insertions(+), 50 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
>> new file mode 100644
>> index 0000000..19d8126
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
>> @@ -0,0 +1,223 @@
>> +* Clock bindings for Freescale i.MX6 Quad
>> +
>> +Required properties:
>> +- compatible: Should be "fsl,imx6q-ccm"
>> +- reg: Address and length of the register set
>> +- interrupts: Should contain CCM interrupt
>> +- #clock-cells: Should be <1>
>> +- clock-output-names: A list of clock output names that CCM provides.
>> +  The full list of all valid clock names and IDs is below.
>> +
>> +     Name                    ID
>> +     ---------------------------
>> +     dummy                   0
>> +     ckil                    1
>> +     ckih                    2
>> +     osc                     3
>> +     pll2_pfd0_352m          4
>> +     pll2_pfd1_594m          5
>> +     pll2_pfd2_396m          6
>> +     pll3_pfd0_720m          7
>> +     pll3_pfd1_540m          8
>> +     pll3_pfd2_508m          9
>> +     pll3_pfd3_454m          10
>> +     pll2_198m               11
>> +     pll3_120m               12
>> +     pll3_80m                13
>> +     pll3_60m                14
>> +     twd                     15
>> +     step                    16
>> +     pll1_sw                 17
>> +     periph_pre              18
>> +     periph2_pre             19
>> +     periph_clk2_sel         20
>> +     periph2_clk2_sel        21
>> +     axi_sel                 22
>> +     esai_sel                23
>> +     asrc_sel                24
>> +     spdif_sel               25
>> +     gpu2d_axi               26
>> +     gpu3d_axi               27
>> +     gpu2d_core_sel          28
>> +     gpu3d_core_sel          29
>> +     gpu3d_shader_sel        30
>> +     ipu1_sel                31
>> +     ipu2_sel                32
>> +     ldb_di0_sel             33
>> +     ldb_di1_sel             34
>> +     ipu1_di0_pre_sel        35
>> +     ipu1_di1_pre_sel        36
>> +     ipu2_di0_pre_sel        37
>> +     ipu2_di1_pre_sel        38
>> +     ipu1_di0_sel            39
>> +     ipu1_di1_sel            40
>> +     ipu2_di0_sel            41
>> +     ipu2_di1_sel            42
>> +     hsi_tx_sel              43
>> +     pcie_axi_sel            44
>> +     ssi1_sel                45
>> +     ssi2_sel                46
>> +     ssi3_sel                47
>> +     usdhc1_sel              48
>> +     usdhc2_sel              49
>> +     usdhc3_sel              50
>> +     usdhc4_sel              51
>> +     enfc_sel                52
>> +     emi_sel                 53
>> +     emi_slow_sel            54
>> +     vdo_axi_sel             55
>> +     vpu_axi_sel             56
>> +     cko1_sel                57
>> +     periph                  58
>> +     periph2                 59
>> +     periph_clk2             60
>> +     periph2_clk2            61
>> +     ipg                     62
>> +     ipg_per                 63
>> +     esai_pred               64
>> +     esai_podf               65
>> +     asrc_pred               66
>> +     asrc_podf               67
>> +     spdif_pred              68
>> +     spdif_podf              69
>> +     can_root                70
>> +     ecspi_root              71
>> +     gpu2d_core_podf         72
>> +     gpu3d_core_podf         73
>> +     gpu3d_shader            74
>> +     ipu1_podf               75
>> +     ipu2_podf               76
>> +     ldb_di0_podf            77
>> +     ldb_di1_podf            78
>> +     ipu1_di0_pre            79
>> +     ipu1_di1_pre            80
>> +     ipu2_di0_pre            81
>> +     ipu2_di1_pre            82
>> +     hsi_tx_podf             83
>> +     ssi1_pred               84
>> +     ssi1_podf               85
>> +     ssi2_pred               86
>> +     ssi2_podf               87
>> +     ssi3_pred               88
>> +     ssi3_podf               89
>> +     uart_serial_podf        90
>> +     usdhc1_podf             91
>> +     usdhc2_podf             92
>> +     usdhc3_podf             93
>> +     usdhc4_podf             94
>> +     enfc_pred               95
>> +     enfc_podf               96
>> +     emi_podf                97
>> +     emi_slow_podf           98
>> +     vpu_axi_podf            99
>> +     cko1_podf               100
>> +     axi                     101
>> +     mmdc_ch0_axi_podf       102
>> +     mmdc_ch1_axi_podf       103
>> +     arm                     104
>> +     ahb                     105
>> +     apbh_dma                106
>> +     asrc                    107
>> +     can1_ipg                108
>> +     can1_serial             109
>> +     can2_ipg                110
>> +     can2_serial             111
>> +     ecspi1                  112
>> +     ecspi2                  113
>> +     ecspi3                  114
>> +     ecspi4                  115
>> +     ecspi5                  116
>> +     enet                    117
>> +     esai                    118
>> +     gpt_ipg                 119
>> +     gpt_ipg_per             120
>> +     gpu2d_core              121
>> +     gpu3d_core              122
>> +     hdmi_iahb               123
>> +     hdmi_isfr               124
>> +     i2c1                    125
>> +     i2c2                    126
>> +     i2c3                    127
>> +     iim                     128
>> +     enfc                    129
>> +     ipu1                    130
>> +     ipu1_di0                131
>> +     ipu1_di1                132
>> +     ipu2                    133
>> +     ipu2_di0                134
>> +     ldb_di0                 135
>> +     ldb_di1                 136
>> +     ipu2_di1                137
>> +     hsi_tx                  138
>> +     mlb                     139
>> +     mmdc_ch0_axi            140
>> +     mmdc_ch1_axi            141
>> +     ocram                   142
>> +     openvg_axi              143
>> +     pcie_axi                144
>> +     pwm1                    145
>> +     pwm2                    146
>> +     pwm3                    147
>> +     pwm4                    148
>> +     per1_bch                149
>> +     gpmi_bch_apb            150
>> +     gpmi_bch                151
>> +     gpmi_io                 152
>> +     gpmi_apb                153
>> +     sata                    154
>> +     sdma                    155
>> +     spba                    156
>> +     ssi1                    157
>> +     ssi2                    158
>> +     ssi3                    159
>> +     uart_ipg                160
>> +     uart_serial             161
>> +     usboh3                  162
>> +     usdhc1                  163
>> +     usdhc2                  164
>> +     usdhc3                  165
>> +     usdhc4                  166
>> +     vdo_axi                 167
>> +     vpu_axi                 168
>> +     cko1                    169
>> +     pll1_sys                170
>> +     pll2_bus                171
>> +     pll3_usb_otg            172
>> +     pll4_audio              173
>> +     pll5_video              174
>> +     pll6_mlb                175
>> +     pll7_usb_host           176
>> +     pll8_enet               177
>> +     ssi1_ipg                178
>> +     ssi2_ipg                179
>> +     ssi3_ipg                180
>> +     rom                     181
>> +     usbphy1                 182
>> +     usbphy2                 183
>> +     ldb_di0_div_3_5         184
>> +     ldb_di1_div_3_5         185
>> +
>> +  The ID will be used by clock consumer in the first cell of "clocks"
>> +  phandle to specify the desired clock.
>> +
>> +Examples:
>> +
>> +clks: ccm at 020c4000 {
>> +     compatible = "fsl,imx6q-ccm";
>> +     reg = <0x020c4000 0x4000>;
>> +     interrupts = <0 87 0x04 0 88 0x04>;
>> +     #clock-cells = <1>;
>> +     clock-output-names = ...
>> +                          "uart_ipg",
>> +                          "uart_serial",
>> +                          ...;
>> +};
>> +
>> +uart1: serial at 02020000 {
>> +     compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>> +     reg = <0x02020000 0x4000>;
>> +     interrupts = <0 26 0x04>;
>> +     clocks = <&clks 160>, <&clks 161>;
>> +     clock-names = "ipg", "per";
>> +     status = "disabled";
>> +};
>> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
>> index 72f30f3..cfdbe53 100644
>> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
>> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
>> @@ -111,6 +111,7 @@
>>                               codec: sgtl5000 at 0a {
>>                                       compatible = "fsl,sgtl5000";
>>                                       reg = <0x0a>;
>> +                                     clocks = <&clks 169>;
>>                                       VDDA-supply = <&reg_2p5v>;
>>                                       VDDIO-supply = <&reg_3p3v>;
>>                               };
>> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
>> index 0052fe7..acff2dc 100644
>> --- a/arch/arm/boot/dts/imx6q.dtsi
>> +++ b/arch/arm/boot/dts/imx6q.dtsi
>> @@ -93,18 +93,23 @@
>>               dma-apbh at 00110000 {
>>                       compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
>>                       reg = <0x00110000 0x2000>;
>> +                     clocks = <&clks 106>;
>>               };
>>
>>               gpmi-nand at 00112000 {
>> -                    compatible = "fsl,imx6q-gpmi-nand";
>> -                    #address-cells = <1>;
>> -                    #size-cells = <1>;
>> -                    reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
>> -                    reg-names = "gpmi-nand", "bch";
>> -                    interrupts = <0 13 0x04>, <0 15 0x04>;
>> -                    interrupt-names = "gpmi-dma", "bch";
>> -                    fsl,gpmi-dma-channel = <0>;
>> -                    status = "disabled";
>> +                     compatible = "fsl,imx6q-gpmi-nand";
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
>> +                     reg-names = "gpmi-nand", "bch";
>> +                     interrupts = <0 13 0x04>, <0 15 0x04>;
>> +                     interrupt-names = "gpmi-dma", "bch";
>> +                     clocks = <&clks 152>, <&clks 153>, <&clks 151>,
>> +                              <&clks 150>, <&clks 149>;
>> +                     clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
>> +                                   "gpmi_bch_apb", "per1_bch";
>> +                     fsl,gpmi-dma-channel = <0>;
>> +                     status = "disabled";
>>               };
>>
>>               timer at 00a00600 {
>> @@ -146,6 +151,8 @@
>>                                       compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>>                                       reg = <0x02008000 0x4000>;
>>                                       interrupts = <0 31 0x04>;
>> +                                     clocks = <&clks 112>, <&clks 112>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -155,6 +162,8 @@
>>                                       compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>>                                       reg = <0x0200c000 0x4000>;
>>                                       interrupts = <0 32 0x04>;
>> +                                     clocks = <&clks 113>, <&clks 113>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -164,6 +173,8 @@
>>                                       compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>>                                       reg = <0x02010000 0x4000>;
>>                                       interrupts = <0 33 0x04>;
>> +                                     clocks = <&clks 114>, <&clks 114>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -173,6 +184,8 @@
>>                                       compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>>                                       reg = <0x02014000 0x4000>;
>>                                       interrupts = <0 34 0x04>;
>> +                                     clocks = <&clks 115>, <&clks 115>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -182,6 +195,8 @@
>>                                       compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
>>                                       reg = <0x02018000 0x4000>;
>>                                       interrupts = <0 35 0x04>;
>> +                                     clocks = <&clks 116>, <&clks 116>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -189,6 +204,8 @@
>>                                       compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>>                                       reg = <0x02020000 0x4000>;
>>                                       interrupts = <0 26 0x04>;
>> +                                     clocks = <&clks 160>, <&clks 161>;
>> +                                     clock-names = "ipg", "per";
>>                                       status = "disabled";
>>                               };
>>
>> @@ -201,6 +218,7 @@
>>                                       compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>>                                       reg = <0x02028000 0x4000>;
>>                                       interrupts = <0 46 0x04>;
>> +                                     clocks = <&clks 178>;
>>                                       fsl,fifo-depth = <15>;
>>                                       fsl,ssi-dma-events = <38 37>;
>>                                       status = "disabled";
>> @@ -210,6 +228,7 @@
>>                                       compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>>                                       reg = <0x0202c000 0x4000>;
>>                                       interrupts = <0 47 0x04>;
>> +                                     clocks = <&clks 179>;
>>                                       fsl,fifo-depth = <15>;
>>                                       fsl,ssi-dma-events = <42 41>;
>>                                       status = "disabled";
>> @@ -219,6 +238,7 @@
>>                                       compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
>>                                       reg = <0x02030000 0x4000>;
>>                                       interrupts = <0 48 0x04>;
>> +                                     clocks = <&clks 180>;
>>                                       fsl,fifo-depth = <15>;
>>                                       fsl,ssi-dma-events = <46 45>;
>>                                       status = "disabled";
>> @@ -358,6 +378,7 @@
>>                               compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>>                               reg = <0x020bc000 0x4000>;
>>                               interrupts = <0 80 0x04>;
>> +                             clocks = <&clks 0>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -365,13 +386,203 @@
>>                               compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
>>                               reg = <0x020c0000 0x4000>;
>>                               interrupts = <0 81 0x04>;
>> +                             clocks = <&clks 0>;
>>                               status = "disabled";
>>                       };
>>
>> -                     ccm at 020c4000 {
>> +                     clks: ccm at 020c4000 {
>>                               compatible = "fsl,imx6q-ccm";
>>                               reg = <0x020c4000 0x4000>;
>>                               interrupts = <0 87 0x04 0 88 0x04>;
>> +                             #clock-cells = <1>;
>> +                             clock-output-names =
>> +                                     "dummy",                /* 0 */
>> +                                     "ckil",                 /* 1 */
>> +                                     "ckih",                 /* 2 */
>> +                                     "osc",                  /* 3 */
>> +                                     "pll2_pfd0_352m",       /* 4 */
>> +                                     "pll2_pfd1_594m",       /* 5 */
>> +                                     "pll2_pfd2_396m",       /* 6 */
>> +                                     "pll3_pfd0_720m",       /* 7 */
>> +                                     "pll3_pfd1_540m",       /* 8 */
>> +                                     "pll3_pfd2_508m",       /* 9 */
>> +                                     "pll3_pfd3_454m",       /* 10 */
>> +                                     "pll2_198m",            /* 11 */
>> +                                     "pll3_120m",            /* 12 */
>> +                                     "pll3_80m",             /* 13 */
>> +                                     "pll3_60m",             /* 14 */
>> +                                     "twd",                  /* 15 */
>> +                                     "step",                 /* 16 */
>> +                                     "pll1_sw",              /* 17 */
>> +                                     "periph_pre",           /* 18 */
>> +                                     "periph2_pre",          /* 19 */
>> +                                     "periph_clk2_sel",      /* 20 */
>> +                                     "periph2_clk2_sel",     /* 21 */
>> +                                     "axi_sel",              /* 22 */
>> +                                     "esai_sel",             /* 23 */
>> +                                     "asrc_sel",             /* 24 */
>> +                                     "spdif_sel",            /* 25 */
>> +                                     "gpu2d_axi",            /* 26 */
>> +                                     "gpu3d_axi",            /* 27 */
>> +                                     "gpu2d_core_sel",       /* 28 */
>> +                                     "gpu3d_core_sel",       /* 29 */
>> +                                     "gpu3d_shader_sel",     /* 30 */
>> +                                     "ipu1_sel",             /* 31 */
>> +                                     "ipu2_sel",             /* 32 */
>> +                                     "ldb_di0_sel",          /* 33 */
>> +                                     "ldb_di1_sel",          /* 34 */
>> +                                     "ipu1_di0_pre_sel",     /* 35 */
>> +                                     "ipu1_di1_pre_sel",     /* 36 */
>> +                                     "ipu2_di0_pre_sel",     /* 37 */
>> +                                     "ipu2_di1_pre_sel",     /* 38 */
>> +                                     "ipu1_di0_sel",         /* 39 */
>> +                                     "ipu1_di1_sel",         /* 40 */
>> +                                     "ipu2_di0_sel",         /* 41 */
>> +                                     "ipu2_di1_sel",         /* 42 */
>> +                                     "hsi_tx_sel",           /* 43 */
>> +                                     "pcie_axi_sel",         /* 44 */
>> +                                     "ssi1_sel",             /* 45 */
>> +                                     "ssi2_sel",             /* 46 */
>> +                                     "ssi3_sel",             /* 47 */
>> +                                     "usdhc1_sel",           /* 48 */
>> +                                     "usdhc2_sel",           /* 49 */
>> +                                     "usdhc3_sel",           /* 50 */
>> +                                     "usdhc4_sel",           /* 51 */
>> +                                     "enfc_sel",             /* 52 */
>> +                                     "emi_sel",              /* 53 */
>> +                                     "emi_slow_sel",         /* 54 */
>> +                                     "vdo_axi_sel",          /* 55 */
>> +                                     "vpu_axi_sel",          /* 56 */
>> +                                     "cko1_sel",             /* 57 */
>> +                                     "periph",               /* 58 */
>> +                                     "periph2",              /* 59 */
>> +                                     "periph_clk2",          /* 60 */
>> +                                     "periph2_clk2",         /* 61 */
>> +                                     "ipg",                  /* 62 */
>> +                                     "ipg_per",              /* 63 */
>> +                                     "esai_pred",            /* 64 */
>> +                                     "esai_podf",            /* 65 */
>> +                                     "asrc_pred",            /* 66 */
>> +                                     "asrc_podf",            /* 67 */
>> +                                     "spdif_pred",           /* 68 */
>> +                                     "spdif_podf",           /* 69 */
>> +                                     "can_root",             /* 70 */
>> +                                     "ecspi_root",           /* 71 */
>> +                                     "gpu2d_core_podf",      /* 72 */
>> +                                     "gpu3d_core_podf",      /* 73 */
>> +                                     "gpu3d_shader",         /* 74 */
>> +                                     "ipu1_podf",            /* 75 */
>> +                                     "ipu2_podf",            /* 76 */
>> +                                     "ldb_di0_podf",         /* 77 */
>> +                                     "ldb_di1_podf",         /* 78 */
>> +                                     "ipu1_di0_pre",         /* 79 */
>> +                                     "ipu1_di1_pre",         /* 80 */
>> +                                     "ipu2_di0_pre",         /* 81 */
>> +                                     "ipu2_di1_pre",         /* 82 */
>> +                                     "hsi_tx_podf",          /* 83 */
>> +                                     "ssi1_pred",            /* 84 */
>> +                                     "ssi1_podf",            /* 85 */
>> +                                     "ssi2_pred",            /* 86 */
>> +                                     "ssi2_podf",            /* 87 */
>> +                                     "ssi3_pred",            /* 88 */
>> +                                     "ssi3_podf",            /* 89 */
>> +                                     "uart_serial_podf",     /* 90 */
>> +                                     "usdhc1_podf",          /* 91 */
>> +                                     "usdhc2_podf",          /* 92 */
>> +                                     "usdhc3_podf",          /* 93 */
>> +                                     "usdhc4_podf",          /* 94 */
>> +                                     "enfc_pred",            /* 95 */
>> +                                     "enfc_podf",            /* 96 */
>> +                                     "emi_podf",             /* 97 */
>> +                                     "emi_slow_podf",        /* 98 */
>> +                                     "vpu_axi_podf",         /* 99 */
>> +                                     "cko1_podf",            /* 100 */
>> +                                     "axi",                  /* 101 */
>> +                                     "mmdc_ch0_axi_podf",    /* 102 */
>> +                                     "mmdc_ch1_axi_podf",    /* 103 */
>> +                                     "arm",                  /* 104 */
>> +                                     "ahb",                  /* 105 */
>> +                                     "apbh_dma",             /* 106 */
>> +                                     "asrc",                 /* 107 */
>> +                                     "can1_ipg",             /* 108 */
>> +                                     "can1_serial",          /* 109 */
>> +                                     "can2_ipg",             /* 110 */
>> +                                     "can2_serial",          /* 111 */
>> +                                     "ecspi1",               /* 112 */
>> +                                     "ecspi2",               /* 113 */
>> +                                     "ecspi3",               /* 114 */
>> +                                     "ecspi4",               /* 115 */
>> +                                     "ecspi5",               /* 116 */
>> +                                     "enet",                 /* 117 */
>> +                                     "esai",                 /* 118 */
>> +                                     "gpt_ipg",              /* 119 */
>> +                                     "gpt_ipg_per",          /* 120 */
>> +                                     "gpu2d_core",           /* 121 */
>> +                                     "gpu3d_core",           /* 122 */
>> +                                     "hdmi_iahb",            /* 123 */
>> +                                     "hdmi_isfr",            /* 124 */
>> +                                     "i2c1",                 /* 125 */
>> +                                     "i2c2",                 /* 126 */
>> +                                     "i2c3",                 /* 127 */
>> +                                     "iim",                  /* 128 */
>> +                                     "enfc",                 /* 129 */
>> +                                     "ipu1",                 /* 130 */
>> +                                     "ipu1_di0",             /* 131 */
>> +                                     "ipu1_di1",             /* 132 */
>> +                                     "ipu2",                 /* 133 */
>> +                                     "ipu2_di0",             /* 134 */
>> +                                     "ldb_di0",              /* 135 */
>> +                                     "ldb_di1",              /* 136 */
>> +                                     "ipu2_di1",             /* 137 */
>> +                                     "hsi_tx",               /* 138 */
>> +                                     "mlb",                  /* 139 */
>> +                                     "mmdc_ch0_axi",         /* 140 */
>> +                                     "mmdc_ch1_axi",         /* 141 */
>> +                                     "ocram",                /* 142 */
>> +                                     "openvg_axi",           /* 143 */
>> +                                     "pcie_axi",             /* 144 */
>> +                                     "pwm1",                 /* 145 */
>> +                                     "pwm2",                 /* 146 */
>> +                                     "pwm3",                 /* 147 */
>> +                                     "pwm4",                 /* 148 */
>> +                                     "per1_bch",             /* 149 */
>> +                                     "gpmi_bch_apb",         /* 150 */
>> +                                     "gpmi_bch",             /* 151 */
>> +                                     "gpmi_io",              /* 152 */
>> +                                     "gpmi_apb",             /* 153 */
>> +                                     "sata",                 /* 154 */
>> +                                     "sdma",                 /* 155 */
>> +                                     "spba",                 /* 156 */
>> +                                     "ssi1",                 /* 157 */
>> +                                     "ssi2",                 /* 158 */
>> +                                     "ssi3",                 /* 159 */
>> +                                     "uart_ipg",             /* 160 */
>> +                                     "uart_serial",          /* 161 */
>> +                                     "usboh3",               /* 162 */
>> +                                     "usdhc1",               /* 163 */
>> +                                     "usdhc2",               /* 164 */
>> +                                     "usdhc3",               /* 165 */
>> +                                     "usdhc4",               /* 166 */
>> +                                     "vdo_axi",              /* 167 */
>> +                                     "vpu_axi",              /* 168 */
>> +                                     "cko1",                 /* 169 */
>> +                                     "pll1_sys",             /* 170 */
>> +                                     "pll2_bus",             /* 171 */
>> +                                     "pll3_usb_otg",         /* 172 */
>> +                                     "pll4_audio",           /* 173 */
>> +                                     "pll5_video",           /* 174 */
>> +                                     "pll6_mlb",             /* 175 */
>> +                                     "pll7_usb_host",        /* 176 */
>> +                                     "pll8_enet",            /* 177 */
>> +                                     "ssi1_ipg",             /* 178 */
>> +                                     "ssi2_ipg",             /* 179 */
>> +                                     "ssi3_ipg",             /* 180 */
>> +                                     "rom",                  /* 181 */
>> +                                     "usbphy1",              /* 182 */
>> +                                     "usbphy2",              /* 183 */
>> +                                     "ldb_di0_div_3_5",      /* 184 */
>> +                                     "ldb_di1_div_3_5",      /* 185 */
>> +                                     "end_of_list";
>>                       };
>>
>>                       anatop at 020c8000 {
>> @@ -468,12 +679,14 @@
>>                               compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>>                               reg = <0x020c9000 0x1000>;
>>                               interrupts = <0 44 0x04>;
>> +                             clocks = <&clks 182>;
>>                       };
>>
>>                       usbphy2: usbphy at 020ca000 {
>>                               compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
>>                               reg = <0x020ca000 0x1000>;
>>                               interrupts = <0 45 0x04>;
>> +                             clocks = <&clks 183>;
>>                       };
>>
>>                       snvs at 020cc000 {
>> @@ -608,6 +821,9 @@
>>                               compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
>>                               reg = <0x020ec000 0x4000>;
>>                               interrupts = <0 2 0x04>;
>> +                             clocks = <&clks 155>, <&clks 155>;
>> +                             clock-names = "ipg", "ahb";
>> +                             fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
>>                       };
>>               };
>>
>> @@ -631,6 +847,7 @@
>>                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>>                               reg = <0x02184000 0x200>;
>>                               interrupts = <0 43 0x04>;
>> +                             clocks = <&clks 162>;
>>                               fsl,usbphy = <&usbphy1>;
>>                               status = "disabled";
>>                       };
>> @@ -639,6 +856,7 @@
>>                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>>                               reg = <0x02184200 0x200>;
>>                               interrupts = <0 40 0x04>;
>> +                             clocks = <&clks 162>;
>>                               fsl,usbphy = <&usbphy2>;
>>                               status = "disabled";
>>                       };
>> @@ -647,6 +865,7 @@
>>                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>>                               reg = <0x02184400 0x200>;
>>                               interrupts = <0 41 0x04>;
>> +                             clocks = <&clks 162>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -654,6 +873,7 @@
>>                               compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>>                               reg = <0x02184600 0x200>;
>>                               interrupts = <0 42 0x04>;
>> +                             clocks = <&clks 162>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -661,6 +881,8 @@
>>                               compatible = "fsl,imx6q-fec";
>>                               reg = <0x02188000 0x4000>;
>>                               interrupts = <0 118 0x04 0 119 0x04>;
>> +                             clocks = <&clks 117>, <&clks 117>;
>> +                             clock-names = "ipg", "ahb";
>>                               status = "disabled";
>>                       };
>>
>> @@ -673,6 +895,8 @@
>>                               compatible = "fsl,imx6q-usdhc";
>>                               reg = <0x02190000 0x4000>;
>>                               interrupts = <0 22 0x04>;
>> +                             clocks = <&clks 163>, <&clks 163>, <&clks 163>;
>> +                             clock-names = "ipg", "ahb", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -680,6 +904,8 @@
>>                               compatible = "fsl,imx6q-usdhc";
>>                               reg = <0x02194000 0x4000>;
>>                               interrupts = <0 23 0x04>;
>> +                             clocks = <&clks 164>, <&clks 164>, <&clks 164>;
>> +                             clock-names = "ipg", "ahb", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -687,6 +913,8 @@
>>                               compatible = "fsl,imx6q-usdhc";
>>                               reg = <0x02198000 0x4000>;
>>                               interrupts = <0 24 0x04>;
>> +                             clocks = <&clks 165>, <&clks 165>, <&clks 165>;
>> +                             clock-names = "ipg", "ahb", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -694,6 +922,8 @@
>>                               compatible = "fsl,imx6q-usdhc";
>>                               reg = <0x0219c000 0x4000>;
>>                               interrupts = <0 25 0x04>;
>> +                             clocks = <&clks 166>, <&clks 166>, <&clks 166>;
>> +                             clock-names = "ipg", "ahb", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -703,6 +933,7 @@
>>                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>>                               reg = <0x021a0000 0x4000>;
>>                               interrupts = <0 36 0x04>;
>> +                             clocks = <&clks 125>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -712,6 +943,7 @@
>>                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>>                               reg = <0x021a4000 0x4000>;
>>                               interrupts = <0 37 0x04>;
>> +                             clocks = <&clks 126>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -721,6 +953,7 @@
>>                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
>>                               reg = <0x021a8000 0x4000>;
>>                               interrupts = <0 38 0x04>;
>> +                             clocks = <&clks 127>;
>>                               status = "disabled";
>>                       };
>>
>> @@ -784,6 +1017,8 @@
>>                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>>                               reg = <0x021e8000 0x4000>;
>>                               interrupts = <0 27 0x04>;
>> +                             clocks = <&clks 160>, <&clks 161>;
>> +                             clock-names = "ipg", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -791,6 +1026,8 @@
>>                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>>                               reg = <0x021ec000 0x4000>;
>>                               interrupts = <0 28 0x04>;
>> +                             clocks = <&clks 160>, <&clks 161>;
>> +                             clock-names = "ipg", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -798,6 +1035,8 @@
>>                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>>                               reg = <0x021f0000 0x4000>;
>>                               interrupts = <0 29 0x04>;
>> +                             clocks = <&clks 160>, <&clks 161>;
>> +                             clock-names = "ipg", "per";
>>                               status = "disabled";
>>                       };
>>
>> @@ -805,6 +1044,8 @@
>>                               compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
>>                               reg = <0x021f4000 0x4000>;
>>                               interrupts = <0 30 0x04>;
>> +                             clocks = <&clks 160>, <&clks 161>;
>> +                             clock-names = "ipg", "per";
>>                               status = "disabled";
>>                       };
>>               };
>> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
>> index 8e46407..433c683 100644
>> --- a/arch/arm/mach-imx/clk-imx6q.c
>> +++ b/arch/arm/mach-imx/clk-imx6q.c
>> @@ -387,48 +387,11 @@ int __init mx6q_clocks_init(void)
>>                       pr_err("i.MX6q clk %d: register failed with %ld\n",
>>                               i, PTR_ERR(clk[i]));
>>
>> +     of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
>> +
>>       clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
>>       clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
>>       clk_register_clkdev(clk[twd], NULL, "smp_twd");
>> -     clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
>> -     clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
>> -     clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
>> -     clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
>> -     clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
>> -     clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
>> -     clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
>> -     clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
>> -     clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
>> -     clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
>> -     clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
>> -     clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
>> -     clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
>> -     clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
>> -     clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
>> -     clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
>> -     clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
>> -     clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
>> -     clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
>> -     clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
>> -     clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
>> -     clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
>> -     clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
>> -     clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
>> -     clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
>> -     clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
>> -     clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
>> -     clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
>> -     clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
>> -     clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
>> -     clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
>> -     clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
>> -     clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
>> -     clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
>> -     clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
>> -     clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
>> -     clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
>> -     clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
>> -     clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
>>       clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
>>       clk_register_clkdev(clk[ahb], "ahb", NULL);
>>       clk_register_clkdev(clk[cko1], "cko1", NULL);
>> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
>> index 6f9c23b..957f5fe 100644
>> --- a/arch/arm/mach-imx/mach-imx6q.c
>> +++ b/arch/arm/mach-imx/mach-imx6q.c
>> @@ -94,7 +94,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
>>       clk_set_parent(cko1_sel, ahb);
>>       rate = clk_round_rate(cko1, 16000000);
>>       clk_set_rate(cko1, rate);
>> -     clk_register_clkdev(cko1, NULL, "0-000a");
>>  put_clk:
>>       if (!IS_ERR(cko1_sel))
>>               clk_put(cko1_sel);
>>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From plagnioj at jcrosoft.com  Mon Aug 20 11:03:35 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 17:03:35 +0200
Subject: [PATCH] ARM: at91: automatically select DT support for sam9x5
 and sam9n12
In-Reply-To: <1345473840-22141-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345473840-22141-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120820150335.GH7439@game.jcrosoft.org>

On 16:44 Mon 20 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> at91sam9x5 and at91sam9n12 only have device tree support so we can
> select device tree support when selecting these chips.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/mach-at91/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index c8050b1..db94ec6 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -88,6 +88,7 @@ config SOC_AT91SAM9X5
>  	select HAVE_AT91_DBGU0
>  	select HAVE_FB_ATMEL
>  	select HAVE_NET_MACB
> +	select MACH_AT91SAM_DT
>  	help
>  	  Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
>  	  This means that your SAM9 name finishes with a '5' (except if it is
> @@ -100,6 +101,7 @@ config SOC_AT91SAM9N12
>  	select SOC_AT91SAM9
>  	select HAVE_AT91_DBGU0
>  	select HAVE_FB_ATMEL
> +	select MACH_AT91SAM_DT
as we are goig to have more and more soc put it as default in the
MACH_AT91SAM_DT if the DT is enabled

Best Regards,
J.


From plagnioj at jcrosoft.com  Mon Aug 20 11:11:46 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 17:11:46 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <CACQ1gAjJ2HL1b9hi3RKGWWs_kW_hELAFYQ=fnHGj5nymjWdiWw@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjJ2HL1b9hi3RKGWWs_kW_hELAFYQ=fnHGj5nymjWdiWw@mail.gmail.com>
Message-ID: <20120820151146.GA7456@game.jcrosoft.org>

On 16:09 Mon 20 Aug     , Richard Genoud wrote:
> Hi Jean-Christophe,
> 
> 2012/8/10 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
> > diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> > index 477cf9d..bbd2f8e 100644
> > --- a/arch/arm/mach-at91/at91sam9x5.c
> > +++ b/arch/arm/mach-at91/at91sam9x5.c
> > @@ -310,12 +310,6 @@ static void __init at91sam9x5_map_io(void)
> >         at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
> >  }
> >
> > -void __init at91sam9x5_initialize(void)
> > -{
> > -       /* Register GPIO subsystem (using DT) */
> > -       at91_gpio_init(NULL, 0);
> > -}
> > -
> >  /* --------------------------------------------------------------------
> >   *  Interrupt initialization
> >   * -------------------------------------------------------------------- */
> > @@ -323,5 +317,4 @@ void __init at91sam9x5_initialize(void)
> >  struct at91_init_soc __initdata at91sam9x5_soc = {
> >         .map_io = at91sam9x5_map_io,
> >         .register_clocks = at91sam9x5_register_clocks,
> > -       .init = at91sam9x5_initialize,
> >  };
> That's why my board wasn't booting anymore after your patchset.
> if .init is NULL, then in arch/arm/mach-at91/soc.h :
> static inline int at91_soc_is_enabled(void)
the it have the patch that drop this

Best Regards,
J.


From shawn.guo at linaro.org  Mon Aug 20 11:16:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 20 Aug 2012 23:16:11 +0800
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
Message-ID: <20120820151609.GN24242@S2101-09.ap.freescale.net>

On Mon, Aug 20, 2012 at 09:54:48AM -0500, Matt Sealey wrote:
> Yet another arbitrary array...
> 
> I'm not sure why you would move the registration lookup into the DT

Because I do not want to patch kernel every time I need a new lookup.
Furthermore, looking at function imx53_qsb_init in imx53-dt.c, you
will find that lookup for sgtl5000 is really board specific and should
go to device tree.

> and use an arbitrarily ordered array again. Sure, you're looking it up
> entirely within the device tree here, but a better solution would be
> to not name clocks twice, and structure your clock definition
> properly.
> 
> What's wrong with;
> 
> ccm at 020c4000 {
>    ...
>    my_clock: clock at 0 {
>        name = "my_clock_name";
>    }
> }
> 
> uart at nnnnnnnn {
>    ...
>    clocks = <&my_clock>;
> }
> 
> ?
> 
It turns a property into 185 nodes, which will just bloat the device
tree.  This issue has been discussed for a plenty of times.

-- 
Regards,
Shawn


From matt at genesi-usa.com  Mon Aug 20 11:21:46 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 20 Aug 2012 10:21:46 -0500
Subject: i.MX27 SLCDC driver
In-Reply-To: <502DEDCD.9050303@gmail.com>
References: <502DEDCD.9050303@gmail.com>
Message-ID: <CAKGA1bmuUxiHbkF0n+bOx81EBQujuhu+piDsfHSVo2LejoPmcw@mail.gmail.com>

On Fri, Aug 17, 2012 at 2:07 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
> Hello,
> I would like to write the driver for SmartLCD controller of i.MX27. This
> kind of interface needs a LCD with an embedded graphic controller partially
> controlled by GPIO. I want to link it with an OLED DD12832.
>
> How have I to write this driver : One driver for SLCDC and one driver for
> DD12832 ? How to link them together ?
>
> Maybe use similar philosophy than soc-camera ?

Please use DRM if you can. That way your SLCDC controller is a "crtc"
and your OLED panel is a combination "encoder" and "connector". The
DRM subsystem isn't by far the best solution since it is designed
around PCI-class graphics cards and the split is intended for those
and not for more tightly-knit LCDC+display combinations, but it does
split things the way you're thinking and with a little extra code it
will do exactly what you want if a little less efficient than your
attached driver.

I was sure Sascha had a driver for this already;
http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commit;h=c333f47fa185edfd1c9d889fc8af040dd557b02c
- it should not be too hard to add your panel and the specific gpio
control as an encoder/connector. Maybe with a user this can actually
go upstream.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From ludovic.desroches at atmel.com  Mon Aug 20 11:40:26 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Mon, 20 Aug 2012 17:40:26 +0200
Subject: [PATCH v2] ARM: at91: select DT support by default
Message-ID: <1345477226-23483-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Since at91sam9x5, at91sam9n12 and future SOCs only have device tree
support, select it by default.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8050b1..5aee940 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -502,6 +502,7 @@ comment "Generic Board Type"
 
 config MACH_AT91SAM_DT
 	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
+	default y
 	select USE_OF
 	help
 	  Select this if you want to experiment device-tree with
-- 
1.7.11.3



From swarren at wwwdotorg.org  Mon Aug 20 11:41:23 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 Aug 2012 09:41:23 -0600
Subject: [PATCH] ARM: tegra: remove duplicate select USE_OF
Message-ID: <1345477283-26000-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

ARCH_TEGRA (arch/arm/Kconfig) now selects USE_OF, so there's not need
for ARCH_TEGRA_3x_SOC to do so too.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/Kconfig |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d3e73ec..b3226f8 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -34,7 +34,6 @@ config ARCH_TEGRA_3x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
-	select USE_OF
 	select ARM_ERRATA_743622
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_754322
-- 
1.7.0.4



From richard.genoud at gmail.com  Mon Aug 20 11:43:50 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 20 Aug 2012 17:43:50 +0200
Subject: [PATCH 06/14] arm: at91: dt: at91sam9 add pinctrl support
In-Reply-To: <20120820151146.GA7456@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-6-git-send-email-plagnioj@jcrosoft.com>
 <CACQ1gAjJ2HL1b9hi3RKGWWs_kW_hELAFYQ=fnHGj5nymjWdiWw@mail.gmail.com>
 <20120820151146.GA7456@game.jcrosoft.org>
Message-ID: <CACQ1gAjT9zSUdNxiS7wxm1YKo44e8zN_mtLwmSuCV9EMAxCXLg@mail.gmail.com>

2012/8/20 Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>:
>> if .init is NULL, then in arch/arm/mach-at91/soc.h :
>> static inline int at91_soc_is_enabled(void)
> the it have the patch that drop this

and who/where is "it" ?

Richard.


From catalin.marinas at arm.com  Mon Aug 20 11:57:40 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 Aug 2012 16:57:40 +0100
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <20120815001043.GD19607@quad.lixom.net>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
 <20120815001043.GD19607@quad.lixom.net>
Message-ID: <20120820155740.GA912@arm.com>

On Wed, Aug 15, 2012 at 01:10:43AM +0100, Olof Johansson wrote:
> On Tue, Aug 14, 2012 at 06:52:09PM +0100, Catalin Marinas wrote:
> 
> > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> > new file mode 100644
> > index 0000000..ef54125
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/cputype.h
> > @@ -0,0 +1,49 @@
> > +#define ID_MIDR_EL1		"midr_el1"
> > +#define ID_CTR_EL0		"ctr_el0"
> > +
> > +#define ID_AA64PFR0_EL1		"id_aa64pfr0_el1"
> > +#define ID_AA64DFR0_EL1		"id_aa64dfr0_el1"
> > +#define ID_AA64AFR0_EL1		"id_aa64afr0_el1"
> > +#define ID_AA64ISAR0_EL1	"id_aa64isar0_el1"
> > +#define ID_AA64MMFR0_EL1	"id_aa64mmfr0_el1"
> > +
> > +#define read_cpuid(reg) ({						\
> > +	u64 __val;							\
> > +	asm("mrs	%0, " reg : "=r" (__val));			\
> > +	__val;								\
> > +})
> > +
> > +/*
> > + * The CPU ID never changes at run time, so we might as well tell the
> > + * compiler that it's constant.  Use this function to read the CPU ID
> > + * rather than directly reading processor_id or read_cpuid() directly.
> > + */
> > +static inline u32 __attribute_const__ read_cpuid_id(void)
> > +{
> > +	return read_cpuid(ID_MIDR_EL1);
> > +}
> > +
> > +static inline u32 __attribute_const__ read_cpuid_cachetype(void)
> > +{
> > +	return read_cpuid(ID_CTR_EL0);
> > +}
> 
> Is this perhaps a carry-over from arch/arm? Abstracting out read_cpuid()
> doesn't seem to buy anything here, just opencode the one-line assembly
> in each.

It doesn't buy much but it's more readable to use read_cpuid() in places
like hw_breakpoint.c than open coding the assembly.

I could get rid of the ID_* macros and just pass the register name
direcly to read_cpuid().

> Might as well cleanup the naming a little too while you're at it, i.e.
> read_cpu_id() and read_cpu_cachetype().

These were defined for convenience, a bit less typing. But they have the
intended name.

> > --- /dev/null
> > +++ b/arch/arm64/mm/proc-syms.c
...
> > +EXPORT_SYMBOL(__cpuc_flush_kern_all);
> > +EXPORT_SYMBOL(__cpuc_flush_user_all);
> > +EXPORT_SYMBOL(__cpuc_flush_user_range);
> > +EXPORT_SYMBOL(__cpuc_coherent_kern_range);
> > +EXPORT_SYMBOL(__cpuc_flush_dcache_area);
> 
> See comment on other email about putting function pointers in a struct
> instead.

There is no need to support multiple CPU architectures with different
implementations, so allowing these functions to be called without
indirection is better.

> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > new file mode 100644
> > index 0000000..453f517
> > --- /dev/null
> > +++ b/arch/arm64/mm/proc.S
> > @@ -0,0 +1,193 @@
> > +	.section ".proc.info.init", #alloc, #execinstr
> > +
> > +	.type	__v8_proc_info, #object
> > +__v8_proc_info:
> > +	.long	0x000f0000			// Required ID value
> > +	.long	0x000f0000			// Mask for ID
> > +	b	__cpu_setup
> > +	nop
> > +	.quad	cpu_name
> > +	.long	0
> > +	.size	__v8_proc_info, . - __v8_proc_info
> 
> I know this is a carry-over from arch/arm, but how about moving this
> to more of a C construct similar to arch/powerpc/kernel/cputable.c
> instead? It's considerably easier to read that way, and it's convenient
> to have the definitions all in one place, making it easier to share some
> of the functions, etc.

I can do this, it would be indeed cleaner.

-- 
Catalin


From catalin.marinas at arm.com  Mon Aug 20 12:00:54 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 20 Aug 2012 17:00:54 +0100
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <201208151356.05416.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-9-git-send-email-catalin.marinas@arm.com>
 <201208151356.05416.arnd@arndb.de>
Message-ID: <20120820160053.GB912@arm.com>

On Wed, Aug 15, 2012 at 02:56:05PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/procinfo.h
...
> > +struct proc_info_list {
> > +	unsigned int		cpu_val;
> > +	unsigned int		cpu_mask;
> > +	unsigned long		__cpu_flush;		/* used by head.S */
> > +	const char		*cpu_name;
> > +};
> > +
> > +#else	/* __KERNEL__ */
> > +#include <asm/elf.h>
> > +#warning "Please include asm/elf.h instead"
> > +#endif	/* __KERNEL__ */
> > +#endif
> 
> I think you forgot to remove this file when you removed MULTI_CPU.

proc_info_list() structure is still used just for the CPU name and setup
function (e.g. we need to apply errata workaround on a certain CPU). But
as Olof suggested, I better move all this to a cputable.c file.

-- 
Catalin


From will.deacon at arm.com  Mon Aug 20 12:09:01 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 17:09:01 +0100
Subject: [PATCH] ARM: perf: update event period in response to
 PERF_EVENT_IOC_PERIOD
Message-ID: <1345478941-32483-1-git-send-email-will.deacon@arm.com>

The PERF_EVENT_IOC_PERIOD ioctl command can be used to change the
sample period of a running perf_event. Consequently, when calculating
the next event period, the new period will only be considered after the
previous one has overflowed.

This patch changes the calculation of the remaining event ticks so that
they are offset if the period has changed.

Reported-by: Andreas Sandberg <andreas.sandberg at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/perf_event.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b8..29a6939 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -148,6 +148,10 @@ armpmu_event_set_period(struct perf_event *event,
 	s64 period = hwc->sample_period;
 	int ret = 0;
 
+	/* The period may have been changed by PERF_EVENT_IOC_PERIOD */
+	if (unlikely(period != hwc->last_period))
+		left = period - (hwc->last_period - left);
+
 	if (unlikely(left <= -period)) {
 		left = period;
 		local64_set(&hwc->period_left, left);
-- 
1.7.4.1



From gcembed at gmail.com  Mon Aug 20 12:21:16 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Mon, 20 Aug 2012 18:21:16 +0200
Subject: i.MX27 SLCDC driver
In-Reply-To: <CAKGA1bmuUxiHbkF0n+bOx81EBQujuhu+piDsfHSVo2LejoPmcw@mail.gmail.com>
References: <502DEDCD.9050303@gmail.com>
 <CAKGA1bmuUxiHbkF0n+bOx81EBQujuhu+piDsfHSVo2LejoPmcw@mail.gmail.com>
Message-ID: <503263FC.8040901@gmail.com>

Hello
On 08/20/2012 05:21 PM, Matt Sealey wrote:
> On Fri, Aug 17, 2012 at 2:07 AM, Ga?tan Carlier <gcembed at gmail.com> wrote:
>> Hello,
>> I would like to write the driver for SmartLCD controller of i.MX27. This
>> kind of interface needs a LCD with an embedded graphic controller partially
>> controlled by GPIO. I want to link it with an OLED DD12832.
>>
>> How have I to write this driver : One driver for SLCDC and one driver for
>> DD12832 ? How to link them together ?
>>
>> Maybe use similar philosophy than soc-camera ?
>
> Please use DRM if you can. That way your SLCDC controller is a "crtc"
> and your OLED panel is a combination "encoder" and "connector". The
> DRM subsystem isn't by far the best solution since it is designed
> around PCI-class graphics cards and the split is intended for those
> and not for more tightly-knit LCDC+display combinations, but it does
> split things the way you're thinking and with a little extra code it
> will do exactly what you want if a little less efficient than your
> attached driver.
>
> I was sure Sascha had a driver for this already;
> http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commit;h=c333f47fa185edfd1c9d889fc8af040dd557b02c
> - it should not be too hard to add your panel and the specific gpio
> control as an encoder/connector. Maybe with a user this can actually
> go upstream.
>
Thanks a lot for your advises. I will study this code.
Regards,
Ga?tan Carlier.


From plagnioj at jcrosoft.com  Mon Aug 20 12:26:51 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 20 Aug 2012 18:26:51 +0200
Subject: [PATCH v2] ARM: at91: select DT support by default
In-Reply-To: <1345477226-23483-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345477226-23483-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120820162651.GB7456@game.jcrosoft.org>

On 17:40 Mon 20 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Since at91sam9x5, at91sam9n12 and future SOCs only have device tree
> support, select it by default.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/mach-at91/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index c8050b1..5aee940 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -502,6 +502,7 @@ comment "Generic Board Type"
>  
>  config MACH_AT91SAM_DT
>  	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
> +	default y
>  	select USE_OF
no you can not force the USE_OF

force the machine by default if USE_OF ok otherwise no
to this you need to select the USE_OF as SoC level

Best Regards,
J.


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 12:29:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 17:29:23 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820125531.GA20242@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
Message-ID: <20120820162923.GF26991@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 01:55:32PM +0100, Lee Jones wrote:

> Right, that was the initial intention. It would be a trivial semantic
> change if drivers without DT support wished to use the functionality
> though. However, the only examples I found of a non-DT enabled driver
> that could make good use of it in order to strip out some cruft would
> be the Arizona and one of the Samsung drivers, and they each have

All of the regmap devices could use this.

> their own hand-rolled methods of hwirq -> virq conversion now, so any
> change to support them would result in multiple invocations of
> irq_create_mapping which would likely cause breakage.

Multiple calls to irq_create_mapping() are totally fine.
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From ludovic.desroches at atmel.com  Mon Aug 20 12:40:39 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 20 Aug 2012 18:40:39 +0200
Subject: [PATCH v2] ARM: at91: select DT support by default
In-Reply-To: <20120820162651.GB7456@game.jcrosoft.org>
References: <1345477226-23483-1-git-send-email-ludovic.desroches@atmel.com>
 <20120820162651.GB7456@game.jcrosoft.org>
Message-ID: <50326887.5050400@atmel.com>

Le 08/20/2012 06:26 PM, Jean-Christophe PLAGNIOL-VILLARD a ?crit :
> On 17:40 Mon 20 Aug     , ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Since at91sam9x5, at91sam9n12 and future SOCs only have device tree
>> support, select it by default.
>>
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> ---
>>   arch/arm/mach-at91/Kconfig | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index c8050b1..5aee940 100644
>> --- a/arch/arm/mach-at91/Kconfig
>> +++ b/arch/arm/mach-at91/Kconfig
>> @@ -502,6 +502,7 @@ comment "Generic Board Type"
>>
>>   config MACH_AT91SAM_DT
>>   	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
>> +	default y
>>   	select USE_OF
> no you can not force the USE_OF
>
> force the machine by default if USE_OF ok otherwise no
> to this you need to select the USE_OF as SoC level

Sorry, it seems I have badly understood your first answer and I don't 
understand the second one too.

So what did you mean by "as we are goig to have more and more soc put it 
as default in the MACH_AT91SAM_DT if the DT is enabled"?

>
> Best Regards,
> J.
>
>

Regards

Ludovic



From stigge at antcom.de  Mon Aug 20 12:47:58 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 20 Aug 2012 18:47:58 +0200
Subject: [PATCH RESEND 1/2] i2c: pnx: Fix bit definitions
In-Reply-To: <083DF309106F364B939360100EC290F823A0354A3D@eu1rdcrdc1wx030.exi.nxp.com>
References: <1344411752-23469-1-git-send-email-stigge@antcom.de>
 <20120818095108.GB24812@pengutronix.de> <5030A81E.5090508@antcom.de>
 <083DF309106F364B939360100EC290F823A0354A3D@eu1rdcrdc1wx030.exi.nxp.com>
Message-ID: <50326A3E.9070607@antcom.de>

On 08/20/2012 06:26 PM, Kevin Wells wrote:
>>>> This patch for i2c-pnx affects PNX4008 and LPC32xx (and LPC31xx,
>>>> not yet in mainline). Can you please test and double-check the
>>>> manuals of PNX4008 and LPC31xx? I only found this via the manual
>>>> of LPC32xx but assume it's the same for the others, also.
>>>>
>>>> Thanks in advance!
>>>
>>> Kevin, since the other manuals seem to be not easily available, can
>>> you please check?
>>
>> Yes, would be great if someone at NXP could confirm that PNX actually
>> uses the same IP core for the I2C controller as LPCs do (which is
>> currently assumed by Linux anyway).
> 
> I've never had my hands on a PNX4008 chip at NXP, but I do believe they
> are the same IP. That specific I2C IP was used in a number of NXP/Phillips
> chips besides the PNX4008/LPC32xx. I don't think there are any PNX4008's in
> the wild, and even working in NXP, I can't find any non-marketing reference
> material for that part (including the user manual).

Considering this, it might be a good idea to remove support for PNX4008
(arch/arm/mach-pnx4008/) altogether. It's hard to maintain support for
hardware which isn't available, even at NXP. It would also simplify
maintenance of mach-lpc32xx because the overlap currently makes me
always wonder if the respective changes still work with mach-pnx4008.

Any opposition?

Roland


PS: I just wonder how mach-pnx4008 came into the kernel at all...


From sebastian.hesselbarth at gmail.com  Mon Aug 20 12:48:32 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 Aug 2012 18:48:32 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
Message-ID: <50326A60.1070007@gmail.com>

On 08/20/2012 04:25 PM, Linus Walleij wrote:
>> +config PINCTRL_ARMADA_370
>> +       bool "Support for Marvell Armada 370 SoCs"
>> +       depends on PINCTRL_MVEBU
>> +       depends on MACH_ARMADA_370_XP
>
> select PINCTRL_MVEBU simply?
>
> And then have the Armada Kconfig
>
> select PINCTRL
> select PINCTRL_ARMADA_370

Linus, Thomas, Gregory,

this is really difficult here ;) I thought I could just add PINCTRL_DOVE
to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.

If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
you work it out if you ever have two distinct MACHs? Or it could remain
selectable in pinctrl/Kconfig but that will then be different with the
other stubs.

Sebastian


From lee.jones at linaro.org  Mon Aug 20 12:49:50 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Mon, 20 Aug 2012 17:49:50 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820162923.GF26991@opensource.wolfsonmicro.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
Message-ID: <20120820164949.GB22749@gmail.com>

On Mon, Aug 20, 2012 at 05:29:23PM +0100, Mark Brown wrote:
> On Mon, Aug 20, 2012 at 01:55:32PM +0100, Lee Jones wrote:
> 
> > Right, that was the initial intention. It would be a trivial semantic
> > change if drivers without DT support wished to use the functionality
> > though. However, the only examples I found of a non-DT enabled driver
> > that could make good use of it in order to strip out some cruft would
> > be the Arizona and one of the Samsung drivers, and they each have
> 
> All of the regmap devices could use this.

Only if they have linear domains and don't support DT.

If they don't have linear domains there's no point, if they support DT
then they can use it as it is.

> > their own hand-rolled methods of hwirq -> virq conversion now, so any
> > change to support them would result in multiple invocations of
> > irq_create_mapping which would likely cause breakage.
> 
> Multiple calls to irq_create_mapping() are totally fine.

Sorry, perhaps I wasn't clear.

<mfd_parent_device>_probe()
|
+-> mfd_add_device()
    |
    +-> res->start = res->end = irq_create_mapping(res->start); // Now a VIRQ


<mfd_child_device>_probe()
|
+-> <mfd_parent_device>_irq_get_virq(res->start) // Ahhh, double VIRQ conversion

To stop being DT dependent we'd need to remove all hand-rolled stuff 
that these drivers are currently using, or else they will be attempting
to convert and already converted VIRQ value. 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Mon Aug 20 12:54:05 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 17:54:05 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
Message-ID: <20120820165405.GU25864@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 05:09:06PM +0100, Nicolas Pitre wrote:
> On Mon, 20 Aug 2012, Will Deacon wrote:
> > diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> > index b54d687..bbc94c2 100644
> > --- a/arch/arm/include/asm/io.h
> > +++ b/arch/arm/include/asm/io.h
> > @@ -63,38 +63,50 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
> >   */
> >  static inline void __raw_writew(u16 val, volatile void __iomem *addr)
> >  {
> > -       asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
> > +       asm volatile("strh %1, %0"
> > +                    : "=Qo" (*(volatile u16 __force *)addr)
> > +                    : "r" (val));
> >  }
> >  
> >  static inline u16 __raw_readw(const volatile void __iomem *addr)
> >  {
> >         u16 val;
> > -       asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
> > +       asm volatile("ldrh %0, %1"
> > +                    : "=r" (val)
> > +                    : "Qo" (*(const volatile u16 __force *)addr));
> >         return val;
> >  }
> 
> Semantically, I think the qualifier on the Qo constraint should be + as 
> in "+Qo" listed in the input operand list in both cases since we may not 
> assume anything about the memory location when it is referring to IO 
> registers.  It is not because you write to it that previous writes can 
> be optimized away, and it is not because you read from it that the 
> accessed memory location will remain the same after the read.  Granted, 
> the volatile should take care of that, but it doesn't hurt to be 
> explicit.

Hmm, ok. I too would hope that the volatile keyword would sort that out but,
since the '+' doesn't seem to change the generated code, I can add that. It
does, however, mean we have to cast away the `const' in the read accessors
which makes the code even uglier.

> Reviewed-by: Nicolas Pitre <nico at linaro.org>

Cheers Nicolas, I'll post the patch independently with your tag.

Will


From nico at fluxnic.net  Mon Aug 20 12:09:06 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 20 Aug 2012 12:09:06 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120820144927.GP25864@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208201150010.1754@xanadu.home>

On Mon, 20 Aug 2012, Will Deacon wrote:
> On Mon, Aug 20, 2012 at 02:29:31PM +0100, Nicolas Pitre wrote:
> > On Mon, 20 Aug 2012, Will Deacon wrote:
> > > That said, we could try the "Qo" constraints, which I seem to 
> > > remember don't generate writebacks. I'll have a play.
> > 
> > OK.  That would be excellent.
> 
> Looks like we have a winner (diff against the original patch below). I now
> see:
> 
> 00000340 <hw_init>:
>  340:   e1a03000        mov     r3, r0
>  344:   e3a00000        mov     r0, #0
>  348:   e5830010        str     r0, [r3, #16]
>  34c:   e3e02000        mvn     r2, #0
>  350:   e5832014        str     r2, [r3, #20]
>  354:   e5932018        ldr     r2, [r3, #24]
>  358:   e38220ff        orr     r2, r2, #255    ; 0xff
>  35c:   e5832030        str     r2, [r3, #48]   ; 0x30
>  360:   e12fff1e        bx      lr
> 
> with the new code, which is basically the same as the old code but the mvn and
> a str have switched places. The same difference occurs when targetting Thumb2.

OK.  Of course the compiler cannot have the same cost evaluation when 
instructions are hidden inside an asm statement which might change the 
instruction scheduling slightly.  But I don't think that matters much 
for IO accesses.

> --- >8
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index b54d687..bbc94c2 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -63,38 +63,50 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
>   */
>  static inline void __raw_writew(u16 val, volatile void __iomem *addr)
>  {
> -       asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
> +       asm volatile("strh %1, %0"
> +                    : "=Qo" (*(volatile u16 __force *)addr)
> +                    : "r" (val));
>  }
>  
>  static inline u16 __raw_readw(const volatile void __iomem *addr)
>  {
>         u16 val;
> -       asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
> +       asm volatile("ldrh %0, %1"
> +                    : "=r" (val)
> +                    : "Qo" (*(const volatile u16 __force *)addr));
>         return val;
>  }

Semantically, I think the qualifier on the Qo constraint should be + as 
in "+Qo" listed in the input operand list in both cases since we may not 
assume anything about the memory location when it is referring to IO 
registers.  It is not because you write to it that previous writes can 
be optimized away, and it is not because you read from it that the 
accessed memory location will remain the same after the read.  Granted, 
the volatile should take care of that, but it doesn't hurt to be 
explicit.

If you fix that then you can add...

Reviewed-by: Nicolas Pitre <nico at linaro.org>


Nicolas


From swarren at wwwdotorg.org  Mon Aug 20 13:15:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 Aug 2012 11:15:55 -0600
Subject: [PATCH] ARM: tegra: remove duplicate select USE_OF
In-Reply-To: <1345477283-26000-1-git-send-email-swarren@wwwdotorg.org>
References: <1345477283-26000-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <503270CB.4090700@wwwdotorg.org>

On 08/20/2012 09:41 AM, Stephen Warren wrote:
> ARCH_TEGRA (arch/arm/Kconfig) now selects USE_OF, so there's not need
> for ARCH_TEGRA_3x_SOC to do so too.

Applied to Tegra's for-3.7/fixes branch.


From swarren at wwwdotorg.org  Mon Aug 20 13:17:59 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 20 Aug 2012 11:17:59 -0600
Subject: [PATCH 3/3] ARM: tegra: remove board (but not DT) support for
 Harmony
In-Reply-To: <1344288734-24131-3-git-send-email-swarren@wwwdotorg.org>
References: <1344288734-24131-1-git-send-email-swarren@wwwdotorg.org>
 <1344288734-24131-3-git-send-email-swarren@wwwdotorg.org>
Message-ID: <50327147.6060406@wwwdotorg.org>

On 08/06/2012 03:32 PM, Stephen Warren wrote:
> Harmony can be booted using device tree with equal functionality as when
> booted using a board file. Remove as much of the board file as is
> possible, since it's no longer needed.
> 
> Two special-cases are still left in board-dt-tegra20.c, since the Tegra
> PCIe driver doesn't support device tree yet, and the Harmony .dts file
> doesn't yet describe regulators which are needed for PCIe. This logic is
> now enabled unconditionally rather than via CONFIG_MACH_HARMONY. While
> this is more code than other boards, it's still unlikely to be much of a
> problem, and both regulators and PCIe should be supported via device tree
> in the near future, allowing the remaining code to be removed.

Applied to Tegra's for-3.7/board-removal branch.



From matt at genesi-usa.com  Mon Aug 20 13:22:56 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 20 Aug 2012 12:22:56 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <20120820151609.GN24242@S2101-09.ap.freescale.net>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
Message-ID: <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>

On Mon, Aug 20, 2012 at 10:16 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Mon, Aug 20, 2012 at 09:54:48AM -0500, Matt Sealey wrote:
>> Yet another arbitrary array...
>>
>> I'm not sure why you would move the registration lookup into the DT
>
> Because I do not want to patch kernel every time I need a new lookup.
> Furthermore, looking at function imx53_qsb_init in imx53-dt.c, you
> will find that lookup for sgtl5000 is really board specific and should
> go to device tree.
>
>> and use an arbitrarily ordered array again. Sure, you're looking it up
>> entirely within the device tree here, but a better solution would be
>> to not name clocks twice, and structure your clock definition
>> properly.
>>
>> What's wrong with;
>>
>> ccm at 020c4000 {
>>    ...
>>    my_clock: clock at 0 {
>>        name = "my_clock_name";
>>    }
>> }
>>
>> uart at nnnnnnnn {
>>    ...
>>    clocks = <&my_clock>;
>> }
>>
>> ?
>>
> It turns a property into 185 nodes, which will just bloat the device
> tree.  This issue has been discussed for a plenty of times.

It's not bloat just because it is by its very definition "a big list", is it?

How do you explain duplicating the clock names in the array AND in the
device node as NOT being bloated?

You're going to have to define these clocks as a tree with parents and
leaf nodes anyway in the clock subsystem. Why not define these in the
device tree in total and reference them by handle when you build the
entire clock tree from the ground up? Or will it just be all the
clocks defined in Linux, but the lookups (which is what I see here)
moved into the DT? Why not form the lookups as part of the definition
of the clock tree?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From will.deacon at arm.com  Mon Aug 20 13:26:00 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 18:26:00 +0100
Subject: [PATCH v3] ARM: support syscall tracing
In-Reply-To: <50324BED.9000500@mentor.com>
References: <50324BED.9000500@mentor.com>
Message-ID: <20120820172559.GW25864@mudshark.cambridge.arm.com>

Hi Wade,

On Mon, Aug 20, 2012 at 03:38:37PM +0100, Wade Farnsworth wrote:
> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> index 978eac5..b032c94 100644
> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
>  	.equ NR_syscalls,0
>  #define CALL(x) .equ NR_syscalls,NR_syscalls+1
>  #include "calls.S"
> +
> +/*
> + * Ensure that the system call table is equal to __NR_syscalls,
> + * which is the value the rest of the system sees
> + */
> +.ifne NR_syscalls - __NR_syscalls
> +.error "__NR_syscalls is not equal to the size of the syscall table"
> +.endif
> +
>  #undef CALL
>  #define CALL(x) .long x
>  
> @@ -415,7 +424,7 @@ local_restart:
>  1:
>  #endif
>  
> -	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
> +	tst     r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?

This is just a whitespace change, so I think you can drop it.

> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
> index 3e0fc5f..4974cdf 100644
> --- a/arch/arm/kernel/ptrace.c
> +++ b/arch/arm/kernel/ptrace.c
> @@ -30,6 +30,9 @@
>  #include <asm/pgtable.h>
>  #include <asm/traps.h>
>  
> +#define CREATE_TRACE_POINTS
> +#include <trace/events/syscalls.h>
> +
>  #define REG_PC	15
>  #define REG_PSR	16
>  /*
> @@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  {
>  	unsigned long ip;
>  
> +	current_thread_info()->syscall = scno;
> +
>  	if (!test_thread_flag(TIF_SYSCALL_TRACE))
>  		return scno;
>  
> -	current_thread_info()->syscall = scno;
> -
>  	/*
>  	 * IP is used to denote syscall entry/exit:
>  	 * IP = 0 -> entry, =1 -> exit
> @@ -942,6 +945,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>  asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
>  {
>  	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
> +	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
> +		trace_sys_enter(regs, scno);
>  	audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
>  			    regs->ARM_r2, regs->ARM_r3);
>  	return ret;
> @@ -950,6 +955,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
>  asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
>  {
>  	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
> +	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
> +		trace_sys_exit(regs, scno);

I think that trace_sys_{enter,exit} should take ret rather than scno. A
debugger could change the syscall number if TIF_SYSCALL_TRACE is set and
that new number should be the one that we use.

The style, however, is much better and I think the code is fairly clear now
so we just need to wait for my fix to the core code to get merged (it got
picked up by Steve Rostedt) and I think we can use ret directly. It might be
worth dropping the local variable and using scno for everything, so that
it's obvious where the syscall number is stored.

Will


From thomas.petazzoni at free-electrons.com  Mon Aug 20 13:36:22 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 Aug 2012 19:36:22 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <50326A60.1070007@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
 <50326A60.1070007@gmail.com>
Message-ID: <20120820193622.4e539451@skate>

Le Mon, 20 Aug 2012 18:48:32 +0200,
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :

> this is really difficult here ;) I thought I could just add PINCTRL_DOVE
> to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
> But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
> 
> If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
> you work it out if you ever have two distinct MACHs? Or it could remain
> selectable in pinctrl/Kconfig but that will then be different with the
> other stubs.

In order to keep the consistency with other SoC families, maybe we can
split the 370 and XP options in two separate MACH_ARMADA_370 and
MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
converted to DT+mach-mvebu, we should have:

 *) arch/arm/Kconfig defines MACH_MVEBU

 *) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
    MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X

Then, an user is free to build a single kernel image that supports all,
or a selection of the supported Marvell EBU SoCs.

Would that be ok with you?

If that's fine with you, then I would prefer if we keep the single
MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches
does not depend on something else. We would do the small Kconfig option
refactoring as a follow-up set of patches. Thoughts?

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From alanbutty12 at gmail.com  Mon Aug 20 13:37:32 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 18:37:32 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ7Fq0FktNN-54++39=SN_GrkX7gpse+2QfD7ioQw+_cEA@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
 <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
 <CAOMZO5BoWyGzB3p11yE9NXAXq319oi0bnbFuwxvahCqGDOZKrw@mail.gmail.com>
 <CADhrpJ487cN23gRkws1Grp+SEmrKO2JdDT0r-DVeCZm-XqdP=A@mail.gmail.com>
 <CAOMZO5BbdT2CXHh4NEt8bPZ4C7Mg=Yd9C9E7J2H_JsGJ=88fqQ@mail.gmail.com>
 <CADhrpJ7Fq0FktNN-54++39=SN_GrkX7gpse+2QfD7ioQw+_cEA@mail.gmail.com>
Message-ID: <CADhrpJ56iWZnBKf6Knoqbm6iucrXMb7ESDtB8WSyWbCxO6A4rg@mail.gmail.com>

On 20 August 2012 13:44, Alan M Butler <alanbutty12 at gmail.com> wrote:
> On 20 August 2012 13:36, Fabio Estevam <festevam at gmail.com> wrote:
>> On Mon, Aug 20, 2012 at 9:30 AM, Alan M Butler <alanbutty12 at gmail.com> wrote:
>>
>>> im not sure but i only get that after applying the patch you sent me
>>> on the linux next from the 17th.
>>> i will try building a new linux-next later today and will send you what happens.
>>
>> Please do not drop the list from Cc.
>>
>>> would it be because i named the buttons power, reset and otb? instead
>>> of button at 1 and so on like the other kirkwood devices?
>>
>> I am not familiar with kirkwood device, sorry.
>
> sorry i forgot to cc the list.
>
> But as far as i can tell with the buttons the only difference between
> my device and the other's like the iconnect is that they named the
> buttons button at 1 and i named mine Power, Reset and OTB. Is it possible
> the capital letters are causing the problem?

i just tried your patch again with the latest linux-next dated 20th of
august with that patch you gave me and i am still getting the errors
on the gpio-keys this is the error:

[    4.838988] orion_gpio_is_valid: invalid GPIO 0
[    4.838999] orion_gpio_is_valid: invalid GPIO 0
[    4.839015] gpio-keys gpio-keys.2: Failed to request GPIO 0, error -22
[    4.845617] gpio-keys: probe of gpio-keys.2 failed with error -22

and this is how the keys are assigned in the dts file:

               Power {
                       label = "Power Button";
                       linux,code = <116>;
                       gpios = <&gpio0 14 1>;
               };
               Reset {
                       label = "Reset Button";
                       linux,code = <0x198>;
                       gpios = <&gpio0 12 1>;
               };
               OTB {
                       label = "OTB Button";
                       linux,code = <133>;
                       gpios = <&gpio1 3 1>;
               };

I hope this helps you figure out the problem.


From thomas.petazzoni at free-electrons.com  Mon Aug 20 13:37:34 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 Aug 2012 19:37:34 +0200
Subject: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig
In-Reply-To: <50324FA3.9030005@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-12-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdaF3OuBLC7odWyH5C_EJT9uFq1rYQMh6=kr8PQjvA68sA@mail.gmail.com>
 <50324FA3.9030005@gmail.com>
Message-ID: <20120820193734.4fcdbb1a@skate>

Le Mon, 20 Aug 2012 16:54:27 +0200,
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :

> On 08/20/2012 04:31 PM, Linus Walleij wrote:
> > On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> > <sebastian.hesselbarth at gmail.com>  wrote:
> >> +CONFIG_PINCTRL_ARMADA_370=y
> >> +CONFIG_PINCTRL_ARMADA_XP=y
> >
> > If the system is not even booting without pinctrl you should
> > (IMHO) select these from the machine's Kconfig entry insteaf.
> 
> I don't have a strong opinion on this but I think most systems
> will boot just fine without pinctrl. The basic stuff is set up
> by u-boot. Anyway, I think we should enable pinctrl for each soc
> by default.

Yes, the system boots fine without the pinctrl support. So I don't
think that MACH_ARMADA_370_XP should forcefully select the pinctrl
code, but it's nice to have the default defconfig for this platform
select the pinctrl support.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 13:51:55 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 18:51:55 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820164949.GB22749@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
Message-ID: <20120820175155.GH26991@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 05:49:50PM +0100, Lee Jones wrote:
> On Mon, Aug 20, 2012 at 05:29:23PM +0100, Mark Brown wrote:

> > All of the regmap devices could use this.

> Only if they have linear domains and don't support DT.

Neither of those restrictions really apply...

> If they don't have linear domains there's no point, if they support DT
> then they can use it as it is.

All this stuff just works for any IRQ domain type, there's no
requirement for a particular one.  It's not urgently exciting for legacy
domains but it's not harmful either and pushes all the handling of this
stuff out of the MFD core and into the irqdomain code which is
definitely an abstraction win.

As far as DT goes supporting DT isn't enough, the current code will only
work on systems that actively use DT and do so using a particular style
of binding.  Since the majority of Linux architectures don't support DT
at all and it's not universally deployed on those that do this means
that generic drivers can't rely on it, and even drivers that use DT
might not be using the binding pattern which the framework code now
uses.

Indeed now that I think about the above isn't this going to be actively
harmful for generic drivers if they use this pattern for their bindings?
On DT systems the framework will unconditionally do the mapping but on
others no mapping will be done.  The function drivers don't know if the
mapping has been performed or not.

Unless I'm missing something here we need to fix this before the merge
window...

> To stop being DT dependent we'd need to remove all hand-rolled stuff 
> that these drivers are currently using, or else they will be attempting
> to convert and already converted VIRQ value. 

Well, yes - using framework code would be the goal here...
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From sebastian.hesselbarth at gmail.com  Mon Aug 20 14:01:51 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 20 Aug 2012 20:01:51 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <20120820193622.4e539451@skate>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
 <50326A60.1070007@gmail.com> <20120820193622.4e539451@skate>
Message-ID: <50327B8F.3050503@gmail.com>

On 08/20/2012 07:36 PM, Thomas Petazzoni wrote:
> In order to keep the consistency with other SoC families, maybe we can
> split the 370 and XP options in two separate MACH_ARMADA_370 and
> MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
> converted to DT+mach-mvebu, we should have:
>
>   *) arch/arm/Kconfig defines MACH_MVEBU
>
>   *) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
>      MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
>
> Then, an user is free to build a single kernel image that supports all,
> or a selection of the supported Marvell EBU SoCs.
>
> Would that be ok with you?

Yes!

> If that's fine with you, then I would prefer if we keep the single
> MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches
> does not depend on something else. We would do the small Kconfig option
> refactoring as a follow-up set of patches. Thoughts?

Despite any objections, I will remove all arch/arm/*/Kconfig patches
from pinctrl patch set.

Sebastian


From nico at fluxnic.net  Mon Aug 20 14:04:01 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 20 Aug 2012 14:04:01 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120820165405.GU25864@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
 <20120820165405.GU25864@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208201356130.1754@xanadu.home>

On Mon, 20 Aug 2012, Will Deacon wrote:

> On Mon, Aug 20, 2012 at 05:09:06PM +0100, Nicolas Pitre wrote:
> > On Mon, 20 Aug 2012, Will Deacon wrote:
> > > diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> > > index b54d687..bbc94c2 100644
> > > --- a/arch/arm/include/asm/io.h
> > > +++ b/arch/arm/include/asm/io.h
> > > @@ -63,38 +63,50 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
> > >   */
> > >  static inline void __raw_writew(u16 val, volatile void __iomem *addr)
> > >  {
> > > -       asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr));
> > > +       asm volatile("strh %1, %0"
> > > +                    : "=Qo" (*(volatile u16 __force *)addr)
> > > +                    : "r" (val));
> > >  }
> > >  
> > >  static inline u16 __raw_readw(const volatile void __iomem *addr)
> > >  {
> > >         u16 val;
> > > -       asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr));
> > > +       asm volatile("ldrh %0, %1"
> > > +                    : "=r" (val)
> > > +                    : "Qo" (*(const volatile u16 __force *)addr));
> > >         return val;
> > >  }
> > 
> > Semantically, I think the qualifier on the Qo constraint should be + as 
> > in "+Qo" listed in the input operand list in both cases since we may not 
> > assume anything about the memory location when it is referring to IO 
> > registers.  It is not because you write to it that previous writes can 
> > be optimized away, and it is not because you read from it that the 
> > accessed memory location will remain the same after the read.  Granted, 
> > the volatile should take care of that, but it doesn't hurt to be 
> > explicit.
> 
> Hmm, ok. I too would hope that the volatile keyword would sort that out but,
> since the '+' doesn't seem to change the generated code, I can add that. It
> does, however, mean we have to cast away the `const' in the read accessors
> which makes the code even uglier.

Nah... the const is wrong.  The way you wrote it means that addr may 
change but the pointed data is constant.  This is obviously wrong since 
we expect the pointed location to change even from a read.


Nicolas


From will.deacon at arm.com  Mon Aug 20 14:10:08 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 20 Aug 2012 19:10:08 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <alpine.LFD.2.02.1208201356130.1754@xanadu.home>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
 <20120820165405.GU25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201356130.1754@xanadu.home>
Message-ID: <20120820181007.GX25864@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 07:04:01PM +0100, Nicolas Pitre wrote:
> On Mon, 20 Aug 2012, Will Deacon wrote:
> > 
> > Hmm, ok. I too would hope that the volatile keyword would sort that out but,
> > since the '+' doesn't seem to change the generated code, I can add that. It
> > does, however, mean we have to cast away the `const' in the read accessors
> > which makes the code even uglier.
> 
> Nah... the const is wrong.  The way you wrote it means that addr may 
> change but the pointed data is constant.  This is obviously wrong since 
> we expect the pointed location to change even from a read.

That's the prototype for the read accessors though -- a bunch of other
architectures define them that way (including asm-generic), so I wonder what
the reasoning behind that was?

Will


From r.schwebel at pengutronix.de  Mon Aug 20 14:15:31 2012
From: r.schwebel at pengutronix.de (Robert Schwebel)
Date: Mon, 20 Aug 2012 20:15:31 +0200
Subject: [PATCH] media: mx2_camera: Remove MX2_CAMERA_SWAP16 and
 MX2_CAMERA_PACK_DIR_MSB flags.
In-Reply-To: <CACKLOr3OmRUACO8QaJnYA6E=YZMCrrOq1pAXb1wTv4Udg+u8bQ@mail.gmail.com>
References: <1342083809-19921-1-git-send-email-javier.martin@vista-silicon.com>
 <Pine.LNX.4.64.1207201330240.27906@axis700.grange>
 <CACKLOr2sKVWCk3we_cP5MvnR6-WsaFwA9AC=fgp3iLm8B6mfEA@mail.gmail.com>
 <Pine.LNX.4.64.1207301718510.28003@axis700.grange>
 <CACKLOr3OmRUACO8QaJnYA6E=YZMCrrOq1pAXb1wTv4Udg+u8bQ@mail.gmail.com>
Message-ID: <20120820181531.GL31821@pengutronix.de>

On Mon, Aug 20, 2012 at 10:08:39AM +0200, javier Martin wrote:
> Sascha, do you have any comments on this one? I can't find it in
> arm-soc, did you already merge it?

Sascha is not in the office this week.

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.petazzoni at free-electrons.com  Mon Aug 20 13:16:55 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 Aug 2012 19:16:55 +0200
Subject: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver
In-Reply-To: <CACRpkda9BL5+NiDOsMKG0kv2coBsw=Er=ZccXnNkgeftV9hPhQ@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-3-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda9BL5+NiDOsMKG0kv2coBsw=Er=ZccXnNkgeftV9hPhQ@mail.gmail.com>
Message-ID: <20120820191655.5e2f2dba@skate>

Le Mon, 20 Aug 2012 15:43:11 +0200,
Linus Walleij <linus.walleij at linaro.org> a ?crit :

> >  config PINCTRL_MVEBU
> >         bool "Marvell SoC pin controller drivers"
> > -       depends on ARCH_MVEBU
> > +       depends on ARCH_MVEBU || ARCH_DOVE
> 
> Hmmmm.
> 
> Shouldn't this thing rather be:
> 
> depends on PLAT_ORION
> 
> else you end up lining up all Marvell machines here...

When we started working on this, ARCH_MVEBU was not a PLAT_ORION
platform, because PLAT_ORION includes its own custom pinmux code, gpio
code, etc, and what we're trying to achieve with Sebastian is to clean
all this. Ultimately, our goal is to have all Orion, Kirkwood, Dove,
Discovery and Armada 370/XP supported in mach-mvebu, and therefore
plat-orion would most likely disappear.

In the mean time, a patch got accepted that separates PLAT_ORION for
PLAT_ORION_LEGACY, and therefore MACH_MVEBU now selects PLAT_ORION to
access things that are still useful (address decoding code) while all
other platforms select PLAT_ORION_LEGACY to get the old pinmux code,
old gpio code, etc. All this is very much a work in progress.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From nico at fluxnic.net  Mon Aug 20 14:45:20 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 20 Aug 2012 14:45:20 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120820181007.GX25864@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
 <20120820165405.GU25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201356130.1754@xanadu.home>
 <20120820181007.GX25864@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208201443070.1754@xanadu.home>

On Mon, 20 Aug 2012, Will Deacon wrote:

> On Mon, Aug 20, 2012 at 07:04:01PM +0100, Nicolas Pitre wrote:
> > On Mon, 20 Aug 2012, Will Deacon wrote:
> > > 
> > > Hmm, ok. I too would hope that the volatile keyword would sort that out but,
> > > since the '+' doesn't seem to change the generated code, I can add that. It
> > > does, however, mean we have to cast away the `const' in the read accessors
> > > which makes the code even uglier.
> > 
> > Nah... the const is wrong.  The way you wrote it means that addr may 
> > change but the pointed data is constant.  This is obviously wrong since 
> > we expect the pointed location to change even from a read.
> 
> That's the prototype for the read accessors though -- a bunch of other
> architectures define them that way (including asm-generic), so I wonder what
> the reasoning behind that was?

I'm still asserting that they're wrong.


Nicolas


From thomas.petazzoni at free-electrons.com  Mon Aug 20 14:51:59 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Mon, 20 Aug 2012 20:51:59 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <50327B8F.3050503@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
 <50326A60.1070007@gmail.com> <20120820193622.4e539451@skate>
 <50327B8F.3050503@gmail.com>
Message-ID: <20120820205159.63001848@skate>

Le Mon, 20 Aug 2012 20:01:51 +0200,
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :

> > If that's fine with you, then I would prefer if we keep the single
> > MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of
> > patches does not depend on something else. We would do the small
> > Kconfig option refactoring as a follow-up set of patches. Thoughts?
> 
> Despite any objections, I will remove all arch/arm/*/Kconfig patches
> from pinctrl patch set.

Ok, fine with me, but we'll have to send separate patches for those,
then.

Thanks!

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From festevam at gmail.com  Mon Aug 20 14:53:33 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 20 Aug 2012 15:53:33 -0300
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CADhrpJ56iWZnBKf6Knoqbm6iucrXMb7ESDtB8WSyWbCxO6A4rg@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
 <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
 <CAOMZO5BoWyGzB3p11yE9NXAXq319oi0bnbFuwxvahCqGDOZKrw@mail.gmail.com>
 <CADhrpJ487cN23gRkws1Grp+SEmrKO2JdDT0r-DVeCZm-XqdP=A@mail.gmail.com>
 <CAOMZO5BbdT2CXHh4NEt8bPZ4C7Mg=Yd9C9E7J2H_JsGJ=88fqQ@mail.gmail.com>
 <CADhrpJ7Fq0FktNN-54++39=SN_GrkX7gpse+2QfD7ioQw+_cEA@mail.gmail.com>
 <CADhrpJ56iWZnBKf6Knoqbm6iucrXMb7ESDtB8WSyWbCxO6A4rg@mail.gmail.com>
Message-ID: <CAOMZO5ApRi6uF1ByNzudSM9VaRNhWy4Pa1AJ-G976NezReG3WA@mail.gmail.com>

Hi Alan,

On Mon, Aug 20, 2012 at 2:37 PM, Alan M Butler <alanbutty12 at gmail.com> wrote:

> i just tried your patch again with the latest linux-next dated 20th of
> august with that patch you gave me and i am still getting the errors
> on the gpio-keys this is the error:
>
> [    4.838988] orion_gpio_is_valid: invalid GPIO 0
> [    4.838999] orion_gpio_is_valid: invalid GPIO 0
> [    4.839015] gpio-keys gpio-keys.2: Failed to request GPIO 0, error -22
> [    4.845617] gpio-keys: probe of gpio-keys.2 failed with error -22

Ok, I am able to reproduce your issue on a mx53qsb as well.

I haven't seen the issue previously because I was registering only one
key on my mx51-babbage. The failure happens on the subsequent key
registrations.

I fixed it with the attached patch, which just sent it to the linux-input list.

Can you please test it?

Regards,

Fabio Estevam
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From arnd at arndb.de  Mon Aug 20 15:49:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 19:49:05 +0000
Subject: [PATCH RESEND 1/2] i2c: pnx: Fix bit definitions
In-Reply-To: <50326A3E.9070607@antcom.de>
References: <1344411752-23469-1-git-send-email-stigge@antcom.de>
 <083DF309106F364B939360100EC290F823A0354A3D@eu1rdcrdc1wx030.exi.nxp.com>
 <50326A3E.9070607@antcom.de>
Message-ID: <201208201949.06530.arnd@arndb.de>

On Monday 20 August 2012, Roland Stigge wrote:
> On 08/20/2012 06:26 PM, Kevin Wells wrote:
> > I've never had my hands on a PNX4008 chip at NXP, but I do believe they
> > are the same IP. That specific I2C IP was used in a number of NXP/Phillips
> > chips besides the PNX4008/LPC32xx. I don't think there are any PNX4008's in
> > the wild, and even working in NXP, I can't find any non-marketing reference
> > material for that part (including the user manual).
> 
> Considering this, it might be a good idea to remove support for PNX4008
> (arch/arm/mach-pnx4008/) altogether. It's hard to maintain support for
> hardware which isn't available, even at NXP. It would also simplify
> maintenance of mach-lpc32xx because the overlap currently makes me
> always wonder if the respective changes still work with mach-pnx4008.
> 
> Any opposition?
> 
> 
> PS: I just wonder how mach-pnx4008 came into the kernel at all...

According to the git logs, Vitaly Wool originally added support for the
platform in 2006 when working at MontaVista, and that year was also the
last time he or anyone else from that company contributed anything in
that directory. Russell was the only other person to make substantial
contributions to it, but they all seem to be cross-platform changes.

In the platform code, there is only a single board number reserved,
with the name of the SoC: MACHINE_START(PNX4008, "Philips PNX4008").
This indicates that whoever was actually using the code did not have
their board code upstream and relied on out-of-tree patches for the
platform.

From all I can tell, the PNX4008 family probably went to ST-Ericsson,
not to NXP in the various acquisitions and mergers that happened
around NXP. This explains why Kevin has no documentation or hardware
for it. On the ST-Ericsson web site, I could find some information
about the PNX4908, presumably a follow-on chip, but not about PNX4008,
so I guess the company also considers the product line dead.

Finally, the chips seems to be targetted at mobile phones and was
introduced seven years ago, which is multiple generations of
products in that market, so probably people stopped caring about
them long ago, unlike embedded chips from the same era for other
markets.

I'd say let's wait for Vitaly to reply on this matter, if he doesn't
care about the code, we can kill it off in 3.7 or 3.8.

	Arnd


From mathieu.poirier at linaro.org  Mon Aug 20 15:50:55 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Mon, 20 Aug 2012 13:50:55 -0600
Subject: [PATCH] drivers/watchdog: Adding PRCMU based WD for ux500 processors
Message-ID: <1345492255-28900-1-git-send-email-mathieu.poirier@linaro.org>

From: "Mathieu J. Poirier" <mathieu.poirier at linaro.org>

This patch is a partial re-write of the driver developed by
Jonas Aaberg and brings it up to the new watchdog interface
now the standard in the mainline kernel.

Cc: Jonas Aaberg <jonas.aberg at stericsson.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
---
 drivers/watchdog/Kconfig      |   10 +++
 drivers/watchdog/Makefile     |    1 +
 drivers/watchdog/ux500_wdt.c  |  168 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/ux500_wdt.h |   19 +++++
 4 files changed, 198 insertions(+), 0 deletions(-)
 create mode 100644 drivers/watchdog/ux500_wdt.c
 create mode 100644 include/linux/mfd/ux500_wdt.h

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 53d7571..5e5f2e5 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -352,6 +352,16 @@ config IMX2_WDT
 	  To compile this driver as a module, choose M here: the
 	  module will be called imx2_wdt.
 
+config UX500_WATCHDOG
+	bool "ST-Ericsson Ux500 watchdog"
+	depends on UX500_SOC_DB8500
+	default y
+	help
+	  Say Y here to include Watchdog timer support for the
+	  watchdog existing in the prcmu of ST-Ericsson Ux500 series platforms.
+	  This watchdog is used to reset the system and thus cannot be
+	  compiled as a module.
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 572b39b..bec0ef8 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
 obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
 obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
+obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/ux500_wdt.c b/drivers/watchdog/ux500_wdt.c
new file mode 100644
index 0000000..7b8cfe27
--- /dev/null
+++ b/drivers/watchdog/ux500_wdt.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Mathieu Poirier <mathieu.poirier at linaro.org> for ST-Ericsson
+ * Author: Jonas Aaberg <jonas.aberg at stericsson.com> for ST-Ericsson
+ *
+ * Heavily based upon geodewdt.c
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/ux500_wdt.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <mach/id.h>
+
+#define WATCHDOG_TIMEOUT 600 /* 10 minutes */
+#define WATCHDOG_MIN	0
+#define WATCHDOG_MAX	268435 /* 28 bit resolution in ms == 268435.455 s */
+
+static int timeout = WATCHDOG_TIMEOUT;
+module_param(timeout, int, 0);
+MODULE_PARM_DESC(timeout,
+	"Watchdog timeout in seconds. default="
+				__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout,
+	"Watchdog cannot be stopped once started (default="
+				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+static bool wdt_en;
+static bool wdt_auto_off;
+
+static int ux500_wdt_start(struct watchdog_device *wdd)
+{
+	wdt_en = true;
+	return db8500_prcmu_enable_a9wdog(0);
+}
+
+static int ux500_wdt_stop(struct watchdog_device *wdd)
+{
+	return  db8500_prcmu_disable_a9wdog(0);
+}
+
+static int ux500_wdt_keepalive(struct watchdog_device *wdd)
+{
+	return db8500_prcmu_kick_a9wdog(0);
+}
+
+static int ux500_wdt_set_timeout(struct watchdog_device *wdd,
+						unsigned int timeout)
+{
+	ux500_wdt_stop(wdd);
+	db8500_prcmu_load_a9wdog(0, timeout);
+	ux500_wdt_start(wdd);
+
+	return 0;
+}
+
+static const struct watchdog_info ux500_wdt_info = {
+	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
+	.identity = "Ux500 WDT",
+	.firmware_version = 1,
+};
+
+static struct watchdog_ops ux500_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = ux500_wdt_start,
+	.stop  = ux500_wdt_stop,
+	.ping  = ux500_wdt_keepalive,
+	.set_timeout = ux500_wdt_set_timeout,
+
+};
+
+static struct watchdog_device ux500_wdt = {
+	.info = &ux500_wdt_info,
+	.ops = &ux500_wdt_ops,
+	.min_timeout = WATCHDOG_MIN,
+	.max_timeout = WATCHDOG_MAX,
+};
+
+static int __init ux500_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+
+	watchdog_set_nowayout(&ux500_wdt, nowayout);
+
+	/* auto off on sleep */
+	db8500_prcmu_config_a9wdog(1, wdt_auto_off);
+
+	/* set HW initial value */
+	db8500_prcmu_load_a9wdog(0, timeout * 1000);
+
+	err = watchdog_register_device(&ux500_wdt);
+	if (err)
+		return err;
+
+	dev_info(&pdev->dev, "initialized\n");
+
+	return 0;
+}
+
+static int __exit ux500_wdt_remove(struct platform_device *dev)
+{
+	watchdog_unregister_device(&ux500_wdt);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ux500_wdt_suspend(struct platform_device *pdev,
+			     pm_message_t state)
+{
+	if (wdt_en && !wdt_auto_off) {
+		ux500_wdt_stop(&ux500_wdt);
+		db8500_prcmu_config_a9wdog(1, true);
+
+		db8500_prcmu_load_a9wdog(0, timeout * 1000);
+		ux500_wdt_start(&ux500_wdt);
+	}
+	return 0;
+}
+
+static int ux500_wdt_resume(struct platform_device *pdev)
+{
+	if (wdt_en && !wdt_auto_off) {
+		ux500_wdt_stop(&ux500_wdt);
+		db8500_prcmu_config_a9wdog(1, true);
+
+		db8500_prcmu_load_a9wdog(0, timeout * 1000);
+		ux500_wdt_start(&ux500_wdt);
+	}
+	return 0;
+}
+
+#else
+#define ux500_wdt_suspend NULL
+#define ux500_wdt_resume NULL
+#endif
+static struct platform_driver ux500_wdt_driver = {
+	.remove		= __exit_p(ux500_wdt_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ux500_wdt",
+	},
+	.suspend	= ux500_wdt_suspend,
+	.resume		= ux500_wdt_resume,
+};
+
+static int __init ux500_wdt_init(void)
+{
+	return platform_driver_probe(&ux500_wdt_driver, ux500_wdt_probe);
+}
+module_init(ux500_wdt_init);
+
+MODULE_AUTHOR("Jonas Aaberg <jonas.aberg at stericsson.com>");
+MODULE_DESCRIPTION("Ux500 Watchdog Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/include/linux/mfd/ux500_wdt.h b/include/linux/mfd/ux500_wdt.h
new file mode 100644
index 0000000..bfb91f1
--- /dev/null
+++ b/include/linux/mfd/ux500_wdt.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) ST Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * STE Ux500 PRCMU API
+ */
+#ifndef __UX500_WDT_H
+#define __UX500_WDT_H
+
+/**
+ * struct ux500_wdt_data
+ */
+struct ux500_wdt_data {
+	int timeout;
+	int nowayout;
+};
+
+#endif /* __UX500_WDT_H */
-- 
1.7.5.4



From baruch at tkos.co.il  Mon Aug 20 16:00:17 2012
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 20 Aug 2012 23:00:17 +0300
Subject: [PATCH] drivers/watchdog: Adding PRCMU based WD for ux500
 processors
In-Reply-To: <1345492255-28900-1-git-send-email-mathieu.poirier@linaro.org>
References: <1345492255-28900-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120820200017.GE3829@tarshish>

Hi Mathieu,

On Mon, Aug 20, 2012 at 01:50:55PM -0600, mathieu.poirier at linaro.org wrote:
> From: "Mathieu J. Poirier" <mathieu.poirier at linaro.org>
> 
> This patch is a partial re-write of the driver developed by
> Jonas Aaberg and brings it up to the new watchdog interface
> now the standard in the mainline kernel.
> 
> Cc: Jonas Aaberg <jonas.aberg at stericsson.com>
> Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>

[snip]

> +/**
> + * struct ux500_wdt_data
> + */
> +struct ux500_wdt_data {
> +	int timeout;
> +	int nowayout;
> +};

This struct doesn't seem to be used anywhere.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From arnd at arndb.de  Mon Aug 20 16:01:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:01:23 +0000
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous
 Memory Allocator
In-Reply-To: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
References: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <201208202001.23443.arnd@arndb.de>

On Monday 20 August 2012, Marek Szyprowski wrote:
> Contiguous Memory Allocator requires only paging and MMU enabled not
> particular CPU architectures, so there is no need for strict dependency
> on CPU type. This enables to use CMA on some older ARM v5 systems which
> also might need large contiguous blocks for the multimedia processing hw
> modules.
> 
> Reported-by: Prabhakar Lad <prabhakar.csengg at gmail.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>

The patch looks simple, but I want a better explanation for it.
When we went through all possible cases, we decided that:

* ARMv6+ need CMA to avoid the double mapping problem.
* ARMv4/v5 cannot generally use CMA because it doesn't work
  together with DMABOUNCE. I don't remember if it was the
  only problem, but I definitely remember this was intentional.
* We want a common kernel for all ARMv6+ eventually, and a
  separate kernel for all ARMv4/v5 ones.

If the reasoning has changed, please try to explain the full
situation. On a related topic, what happened to the idea that
ARMv6+ is broken without CMA? I noticed that it's optional
now.

	Arnd


From arnd at arndb.de  Mon Aug 20 16:06:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:06:24 +0000
Subject: [PATCH 0/4] Per device coherent DMA map ops
In-Reply-To: <50324F9A.5000608@gmail.com>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
 <000601cd7ede$5d2ef390$178cdab0$%szyprowski@samsung.com>
 <50324F9A.5000608@gmail.com>
Message-ID: <201208202006.24851.arnd@arndb.de>

On Monday 20 August 2012, Rob Herring wrote:
> > 
> > I like those patches and I would like to take it to my dma-mapping-next tree, but I wonder 
> > how to handle merging of the last patch. Arnd, Olof - could You tell me how to do it? I assume
> > that it should be somehow merged by arm-soc tree, so it depends on the earlier patches.
> > Would it be enough if I take them to the topic branch? Then I can continue works on 
> > dma-mapping subsystem by merging that topic branch to my dma-mapping-next and you will
> > also take it as a dependency for highbank patches. Am I right?
> > 
> 
> I'm fine with it all going in thru your tree. Seems a bit silly to deal
> with tracking the dependencies all for 1 patch. The only possible
> conflict I see is with the dts file and some other SATA related changes
> which will go in via the ata tree. But the merge is trivial and the
> conflict will be there either with your tree or arm-soc.

Right. I see no problem having this patch go through the dma-mapping tree.

	Arnd


From broonie at opensource.wolfsonmicro.com  Mon Aug 20 16:07:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 20 Aug 2012 21:07:15 +0100
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA19A81@DBDE01.ent.ti.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>
 <20120816140056.GK15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA19A81@DBDE01.ent.ti.com>
Message-ID: <20120820200715.GT26991@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 06:27:01AM +0000, AnilKumar, Chimata wrote:
> On Thu, Aug 16, 2012 at 19:30:56, Mark Brown wrote:

> > Why does this mean you need multiple regulators?  A single regulator can
> > of course supply multiple devices.

> I got your point but tps65910 driver is failing if we add single fixed
> regulator. Solution is driver needs to change or add multiple fixed
> regulators.

No, really.  One regulator can supply many things, not being a.

> vrtc:
> tps65910 0-002d: Failed to find supply vcc7
> tps65910 0-002d: failed to register tps65910-pmic regulator

So you've specified a whole bunch of supplies and this one individual
supply is not matching (and it's not the first...).  You should
investigate what's gone wrong there rather than bodging around the
problem.  I can't immediately say anything much based on the information
you've given.
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From arnd at arndb.de  Mon Aug 20 16:10:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:10:59 +0000
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <20120820092744.GD25864@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120820090754.GB25864@mudshark.cambridge.arm.com>
 <20120820092744.GD25864@mudshark.cambridge.arm.com>
Message-ID: <201208202010.59985.arnd@arndb.de>

On Monday 20 August 2012, Will Deacon wrote:
> On Mon, Aug 20, 2012 at 10:07:54AM +0100, Will Deacon wrote:
> > On Fri, Aug 17, 2012 at 08:06:07AM +0100, Arnd Bergmann wrote:
> > > Sorry for the dumb question, but why do you even need PTRACE_GET_THREAD_AREA
> > > for 64 bit tasks? I thought the thread pointer is a GPR, or is this just
> > > for compat tasks?
> > 
> > The TLS is stored in a co-processor register which is read-only for
> > userspace.
> 
> I should elaborate: the register is RW for AArch64 tasks, RO for aarch32
> tasks (although that doesn't affect the need for the ptrace request).

So can't you just /add/ that register to the GPR regset?

	Arnd


From alanbutty12 at gmail.com  Mon Aug 20 16:24:02 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Mon, 20 Aug 2012 21:24:02 +0100
Subject: [PATCH] ARM: Kirkwood: Iomega IX2-200 Device Tree Support Patch
 v2 Signed-off-by: Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <CAOMZO5ApRi6uF1ByNzudSM9VaRNhWy4Pa1AJ-G976NezReG3WA@mail.gmail.com>
References: <cover.1345196553.git.alanbutty12@gmail.com>
 <05c3c186d3675cde472bcc3a01198b6726c48a3c.1345196553.git.alanbutty12@gmail.com>
 <20120819020607.GZ22226@titan.lakedaemon.net>
 <CADhrpJ5WX-ZR3vxwe92Rg4R9a1+79Vf-QxKdJhyaC87o8HJYrw@mail.gmail.com>
 <CADhrpJ6HmUd86zx6Az0bx9JiiYp6kMmTis6ARMWBrNqoK8aKng@mail.gmail.com>
 <CAOMZO5AZZwQS8rkvrG3Nd7KAhgh3+PcfkdoKiqRW95eaUyTghg@mail.gmail.com>
 <CADhrpJ7ZE=L25V8sKyQAT02iDuyCRwyCAjw4ukopek1i0TRqNw@mail.gmail.com>
 <CAOMZO5BoWyGzB3p11yE9NXAXq319oi0bnbFuwxvahCqGDOZKrw@mail.gmail.com>
 <CADhrpJ487cN23gRkws1Grp+SEmrKO2JdDT0r-DVeCZm-XqdP=A@mail.gmail.com>
 <CAOMZO5BbdT2CXHh4NEt8bPZ4C7Mg=Yd9C9E7J2H_JsGJ=88fqQ@mail.gmail.com>
 <CADhrpJ7Fq0FktNN-54++39=SN_GrkX7gpse+2QfD7ioQw+_cEA@mail.gmail.com>
 <CADhrpJ56iWZnBKf6Knoqbm6iucrXMb7ESDtB8WSyWbCxO6A4rg@mail.gmail.com>
 <CAOMZO5ApRi6uF1ByNzudSM9VaRNhWy4Pa1AJ-G976NezReG3WA@mail.gmail.com>
Message-ID: <CADhrpJ7ivG4EN80Q5_5Qi0RyGqrrtJOuHF2b5tDVBLrRedqfug@mail.gmail.com>

On 20 August 2012 19:53, Fabio Estevam <festevam at gmail.com> wrote:
> Hi Alan,
>
> On Mon, Aug 20, 2012 at 2:37 PM, Alan M Butler <alanbutty12 at gmail.com> wrote:
>
>> i just tried your patch again with the latest linux-next dated 20th of
>> august with that patch you gave me and i am still getting the errors
>> on the gpio-keys this is the error:
>>
>> [    4.838988] orion_gpio_is_valid: invalid GPIO 0
>> [    4.838999] orion_gpio_is_valid: invalid GPIO 0
>> [    4.839015] gpio-keys gpio-keys.2: Failed to request GPIO 0, error -22
>> [    4.845617] gpio-keys: probe of gpio-keys.2 failed with error -22
>
> Ok, I am able to reproduce your issue on a mx53qsb as well.
>
> I haven't seen the issue previously because I was registering only one
> key on my mx51-babbage. The failure happens on the subsequent key
> registrations.
>
> I fixed it with the attached patch, which just sent it to the linux-input list.
>
> Can you please test it?
>
> Regards,
>
> Fabio Estevam

I can confirm fabio that the patch you sent did fix the problem with
the buttons
on the linux-next dated 20th of august.


From mathieu.poirier at linaro.org  Mon Aug 20 16:30:24 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Mon, 20 Aug 2012 14:30:24 -0600
Subject: [PATCH v2] drivers/watchdog: Adding PRCMU based WD for ux500
 processors
Message-ID: <1345494624-7557-1-git-send-email-mathieu.poirier@linaro.org>

From: "Mathieu J. Poirier" <mathieu.poirier at linaro.org>

This patch is a partial re-write of the driver developed by
Jonas Aaberg and brings it up to the new watchdog interface
now the standard in the mainline kernel.

Cc: Jonas Aaberg <jonas.aberg at stericsson.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
---
 drivers/watchdog/Kconfig      |   10 +++
 drivers/watchdog/Makefile     |    1 +
 drivers/watchdog/ux500_wdt.c  |  174 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/ux500_wdt.h |   19 +++++
 4 files changed, 204 insertions(+), 0 deletions(-)
 create mode 100644 drivers/watchdog/ux500_wdt.c
 create mode 100644 include/linux/mfd/ux500_wdt.h

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 53d7571..5e5f2e5 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -352,6 +352,16 @@ config IMX2_WDT
 	  To compile this driver as a module, choose M here: the
 	  module will be called imx2_wdt.
 
+config UX500_WATCHDOG
+	bool "ST-Ericsson Ux500 watchdog"
+	depends on UX500_SOC_DB8500
+	default y
+	help
+	  Say Y here to include Watchdog timer support for the
+	  watchdog existing in the prcmu of ST-Ericsson Ux500 series platforms.
+	  This watchdog is used to reset the system and thus cannot be
+	  compiled as a module.
+
 # AVR32 Architecture
 
 config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 572b39b..bec0ef8 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
 obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
 obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
+obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/ux500_wdt.c b/drivers/watchdog/ux500_wdt.c
new file mode 100644
index 0000000..0eb7ae3
--- /dev/null
+++ b/drivers/watchdog/ux500_wdt.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Mathieu Poirier <mathieu.poirier at linaro.org> for ST-Ericsson
+ * Author: Jonas Aaberg <jonas.aberg at stericsson.com> for ST-Ericsson
+ *
+ * Heavily based upon geodewdt.c
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/ux500_wdt.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <mach/id.h>
+
+#define WATCHDOG_TIMEOUT 600 /* 10 minutes */
+#define WATCHDOG_MIN	0
+#define WATCHDOG_MAX	268435 /* 28 bit resolution in ms == 268435.455 s */
+
+static int timeout = WATCHDOG_TIMEOUT;
+module_param(timeout, int, 0);
+MODULE_PARM_DESC(timeout,
+	"Watchdog timeout in seconds. default="
+				__MODULE_STRING(WATCHDOG_TIMEOUT) ".");
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout,
+	"Watchdog cannot be stopped once started (default="
+				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+static bool wdt_en;
+static bool wdt_auto_off;
+
+static int ux500_wdt_start(struct watchdog_device *wdd)
+{
+	wdt_en = true;
+	return db8500_prcmu_enable_a9wdog(0);
+}
+
+static int ux500_wdt_stop(struct watchdog_device *wdd)
+{
+	return  db8500_prcmu_disable_a9wdog(0);
+}
+
+static int ux500_wdt_keepalive(struct watchdog_device *wdd)
+{
+	return db8500_prcmu_kick_a9wdog(0);
+}
+
+static int ux500_wdt_set_timeout(struct watchdog_device *wdd,
+						unsigned int timeout)
+{
+	ux500_wdt_stop(wdd);
+	db8500_prcmu_load_a9wdog(0, timeout);
+	ux500_wdt_start(wdd);
+
+	return 0;
+}
+
+static const struct watchdog_info ux500_wdt_info = {
+	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
+	.identity = "Ux500 WDT",
+	.firmware_version = 1,
+};
+
+static struct watchdog_ops ux500_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = ux500_wdt_start,
+	.stop  = ux500_wdt_stop,
+	.ping  = ux500_wdt_keepalive,
+	.set_timeout = ux500_wdt_set_timeout,
+
+};
+
+static struct watchdog_device ux500_wdt = {
+	.info = &ux500_wdt_info,
+	.ops = &ux500_wdt_ops,
+	.min_timeout = WATCHDOG_MIN,
+	.max_timeout = WATCHDOG_MAX,
+};
+
+static int __init ux500_wdt_probe(struct platform_device *pdev)
+{
+	int err;
+	struct ux500_wdt_data *pdata = pdev->dev.platform_data;
+
+	if (pdata) {
+		timeout = pdata->timeout;
+		nowayout = pdata->nowayout;
+	}
+
+	watchdog_set_nowayout(&ux500_wdt, nowayout);
+
+	/* auto off on sleep */
+	db8500_prcmu_config_a9wdog(1, wdt_auto_off);
+
+	/* set HW initial value */
+	db8500_prcmu_load_a9wdog(0, timeout * 1000);
+
+	err = watchdog_register_device(&ux500_wdt);
+	if (err)
+		return err;
+
+	dev_info(&pdev->dev, "initialized\n");
+
+	return 0;
+}
+
+static int __exit ux500_wdt_remove(struct platform_device *dev)
+{
+	watchdog_unregister_device(&ux500_wdt);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ux500_wdt_suspend(struct platform_device *pdev,
+			     pm_message_t state)
+{
+	if (wdt_en && !wdt_auto_off) {
+		ux500_wdt_stop(&ux500_wdt);
+		db8500_prcmu_config_a9wdog(1, true);
+
+		db8500_prcmu_load_a9wdog(0, timeout * 1000);
+		ux500_wdt_start(&ux500_wdt);
+	}
+	return 0;
+}
+
+static int ux500_wdt_resume(struct platform_device *pdev)
+{
+	if (wdt_en && !wdt_auto_off) {
+		ux500_wdt_stop(&ux500_wdt);
+		db8500_prcmu_config_a9wdog(1, true);
+
+		db8500_prcmu_load_a9wdog(0, timeout * 1000);
+		ux500_wdt_start(&ux500_wdt);
+	}
+	return 0;
+}
+
+#else
+#define ux500_wdt_suspend NULL
+#define ux500_wdt_resume NULL
+#endif
+static struct platform_driver ux500_wdt_driver = {
+	.remove		= __exit_p(ux500_wdt_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ux500_wdt",
+	},
+	.suspend	= ux500_wdt_suspend,
+	.resume		= ux500_wdt_resume,
+};
+
+static int __init ux500_wdt_init(void)
+{
+	return platform_driver_probe(&ux500_wdt_driver, ux500_wdt_probe);
+}
+module_init(ux500_wdt_init);
+
+MODULE_AUTHOR("Jonas Aaberg <jonas.aberg at stericsson.com>");
+MODULE_DESCRIPTION("Ux500 Watchdog Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/include/linux/mfd/ux500_wdt.h b/include/linux/mfd/ux500_wdt.h
new file mode 100644
index 0000000..bfb91f1
--- /dev/null
+++ b/include/linux/mfd/ux500_wdt.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) ST Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * STE Ux500 PRCMU API
+ */
+#ifndef __UX500_WDT_H
+#define __UX500_WDT_H
+
+/**
+ * struct ux500_wdt_data
+ */
+struct ux500_wdt_data {
+	int timeout;
+	int nowayout;
+};
+
+#endif /* __UX500_WDT_H */
-- 
1.7.5.4



From arnd at arndb.de  Mon Aug 20 16:34:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:34:54 +0000
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <20120820105308.GA906@elf.ucw.cz>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
 <20120820105308.GA906@elf.ucw.cz>
Message-ID: <201208202034.55135.arnd@arndb.de>

On Monday 20 August 2012, Pavel Machek wrote:
> > This patch adds support for 32-bit applications. The vectors page is a
> > binary blob mapped into the application user space at 0xffff0000 (the
> > AArch64 toolchain does not support compilation of AArch32 code). Full
> > compatibility with ARMv7 user space is supported. The use of deprecated
> > ARMv7 functionality (SWP, CP15 barriers) has been disabled by default on
> > AArch64 kernels and unaligned LDM/STM is not supported.
> > 
> > Please note that only the ARM 32-bit EABI is supported, so no OABI
> > compatibility.
> 
> > +struct compat_statfs {
> > +     int             f_type;
> > +     int             f_bsize;
> > +     int             f_blocks;
> > +     int             f_bfree;
> > +     int             f_bavail;
> > +     int             f_files;
> > +     int             f_ffree;
> > +     compat_fsid_t   f_fsid;
> > +     int             f_namelen;      /* SunOS ignores this field. */
> 
> I'm sure it does. But is it good comment?

Good catch. It seems that some of the other compat platforms (x86,
sparc, powerpc) have the same thing. I guess the real solution would
be to introduce an asm-generic/compat.h file that contains a bunch
of those definitions, like

#ifndef compat_timespec
struct compat_timespec {
        compat_time_t   tv_sec;
        s32             tv_nsec;
};
#endif

#ifndef compat_timeval
struct compat_timeval {
        compat_time_t   tv_sec;
        s32             tv_usec;
};
#endif

#ifndef compat_sysctl
struct compat_sysctl {
        unsigned int    name;
        int             nlen;
        unsigned int    oldval;
        unsigned int    oldlenp;
        unsigned int    newval;
        unsigned int    newlen;
        unsigned int    __unused[4];
};
#endif

For the most part, arch/tile should have useful defaults, though not in the
case of struct statfs, because its 32 bit version does not have a statfs syscall
(it only has statfs64).

	Arnd


From wade_farnsworth at mentor.com  Mon Aug 20 16:35:52 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 20 Aug 2012 13:35:52 -0700
Subject: [PATCH v4] ARM: support syscall tracing
Message-ID: <50329FA8.1010701@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
__sys_trace was modified to call trace_sys_enter and
trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
---
This patch is an update of one I posted some months ago.  It has been
rebased to Linus's current master branch.
- v2: Implemented changes suggested by Will:
  - Folded _TIF_SYSCALL_TRACEPOINT into _TIF_SYSCALL_WORK to save an
    instruction in entry-common.S.
  - Moved calls to trace_sys_{enter,exit} to syscall_trace_{enter,exit}
- v3:
  - Set current_thread_info()->syscall before checking TIF_SYSCALL_TRACE.
  - Pass the original syscall number into trace_sys_{enter,exit}, not
    the return value from ptrace_syscall_trace().
- v4: More changes based on Will's feedback:
  - Reverted to passing the return value from ptrace_syscall_trace() into
    trace_sys_{enter,exit}.
  - Removed inadvertent whitespace change.
 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    4 +++-
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |    9 +++++++++
 arch/arm/kernel/ptrace.c           |   11 +++++++++--
 6 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..983e9eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index af7b0bd..5ded667 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -148,6 +148,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
 #define TIF_SYSCALL_TRACE	8
 #define TIF_SYSCALL_AUDIT	9
+#define TIF_SYSCALL_TRACEPOINT	10
 #define TIF_POLLING_NRFLAG	16
 #define TIF_USING_IWMMXT	17
 #define TIF_MEMDIE		18	/* is terminating due to OOM killer */
@@ -160,12 +161,13 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
 
 /* Checks for any syscall work in entry-common.S */
-#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
 
 /*
  * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0cab47d..a566ec2 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 978eac5..f459870 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f..c382d3c 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/pgtable.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 {
 	unsigned long ip;
 
+	current_thread_info()->syscall = scno;
+
 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
 		return scno;
 
-	current_thread_info()->syscall = scno;
-
 	/*
 	 * IP is used to denote syscall entry/exit:
 	 * IP = 0 -> entry, =1 -> exit
@@ -942,6 +945,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_enter(regs, ret);
 	audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
 			    regs->ARM_r2, regs->ARM_r3);
 	return ret;
@@ -950,6 +955,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
 	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+		trace_sys_exit(regs, ret);
 	audit_syscall_exit(regs);
 	return ret;
 }
-- 
1.7.0.4



From wade_farnsworth at mentor.com  Mon Aug 20 16:45:10 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 20 Aug 2012 13:45:10 -0700
Subject: [PATCH v3] ARM: support syscall tracing
In-Reply-To: <20120820172559.GW25864@mudshark.cambridge.arm.com>
References: <50324BED.9000500@mentor.com>
 <20120820172559.GW25864@mudshark.cambridge.arm.com>
Message-ID: <5032A1D6.6010605@mentor.com>

Will Deacon wrote:
> Hi Wade,
>
> On Mon, Aug 20, 2012 at 03:38:37PM +0100, Wade Farnsworth wrote:
>> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
>> index 978eac5..b032c94 100644
>> --- a/arch/arm/kernel/entry-common.S
>> +++ b/arch/arm/kernel/entry-common.S
>> @@ -94,6 +94,15 @@ ENDPROC(ret_from_fork)
>>   	.equ NR_syscalls,0
>>   #define CALL(x) .equ NR_syscalls,NR_syscalls+1
>>   #include "calls.S"
>> +
>> +/*
>> + * Ensure that the system call table is equal to __NR_syscalls,
>> + * which is the value the rest of the system sees
>> + */
>> +.ifne NR_syscalls - __NR_syscalls
>> +.error "__NR_syscalls is not equal to the size of the syscall table"
>> +.endif
>> +
>>   #undef CALL
>>   #define CALL(x) .long x
>>
>> @@ -415,7 +424,7 @@ local_restart:
>>   1:
>>   #endif
>>
>> -	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
>> +	tst     r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
>
> This is just a whitespace change, so I think you can drop it.
>
>> diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
>> index 3e0fc5f..4974cdf 100644
>> --- a/arch/arm/kernel/ptrace.c
>> +++ b/arch/arm/kernel/ptrace.c
>> @@ -30,6 +30,9 @@
>>   #include<asm/pgtable.h>
>>   #include<asm/traps.h>
>>
>> +#define CREATE_TRACE_POINTS
>> +#include<trace/events/syscalls.h>
>> +
>>   #define REG_PC	15
>>   #define REG_PSR	16
>>   /*
>> @@ -918,11 +921,11 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>>   {
>>   	unsigned long ip;
>>
>> +	current_thread_info()->syscall = scno;
>> +
>>   	if (!test_thread_flag(TIF_SYSCALL_TRACE))
>>   		return scno;
>>
>> -	current_thread_info()->syscall = scno;
>> -
>>   	/*
>>   	 * IP is used to denote syscall entry/exit:
>>   	 * IP = 0 ->  entry, =1 ->  exit
>> @@ -942,6 +945,8 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
>>   asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
>>   {
>>   	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
>> +	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
>> +		trace_sys_enter(regs, scno);
>>   	audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
>>   			    regs->ARM_r2, regs->ARM_r3);
>>   	return ret;
>> @@ -950,6 +955,8 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
>>   asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
>>   {
>>   	int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
>> +	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
>> +		trace_sys_exit(regs, scno);
>
> I think that trace_sys_{enter,exit} should take ret rather than scno. A
> debugger could change the syscall number if TIF_SYSCALL_TRACE is set and
> that new number should be the one that we use.
>
> The style, however, is much better and I think the code is fairly clear now
> so we just need to wait for my fix to the core code to get merged (it got
> picked up by Steve Rostedt) and I think we can use ret directly. It might be
> worth dropping the local variable and using scno for everything, so that
> it's obvious where the syscall number is stored.
>

I agree that your patch needs to get merged before mine gets picked up 
so that we don't introduce a new bug.  I've sent v4 with the changes you 
suggest.  Would you like me to modify syscall_trace_* to remove the 
local variable in this patch as well?  It seems to me that such a rework 
is better handled separately, but let me know if you think otherwise.

Thanks for the reviews!

Wade


From arnd at arndb.de  Mon Aug 20 16:47:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:47:07 +0000
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <20120820155740.GA912@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120815001043.GD19607@quad.lixom.net> <20120820155740.GA912@arm.com>
Message-ID: <201208202047.07991.arnd@arndb.de>

On Monday 20 August 2012, Catalin Marinas wrote:
> > > --- /dev/null
> > > +++ b/arch/arm64/mm/proc-syms.c
> ...
> > > +EXPORT_SYMBOL(__cpuc_flush_kern_all);
> > > +EXPORT_SYMBOL(__cpuc_flush_user_all);
> > > +EXPORT_SYMBOL(__cpuc_flush_user_range);
> > > +EXPORT_SYMBOL(__cpuc_coherent_kern_range);
> > > +EXPORT_SYMBOL(__cpuc_flush_dcache_area);
> > 
> > See comment on other email about putting function pointers in a struct
> > instead.
> 
> There is no need to support multiple CPU architectures with different
> implementations, so allowing these functions to be called without
> indirection is better.

What is the __cpuc prefix about then? Could you just drop it?

	Arnd


From swetland at google.com  Mon Aug 20 16:51:33 2012
From: swetland at google.com (Brian Swetland)
Date: Mon, 20 Aug 2012 13:51:33 -0700
Subject: [PATCH v4 0/12] KGDB/KDB FIQ (NMI) debugger
In-Reply-To: <20120820144449.GA32560@lizard>
References: <20120820144449.GA32560@lizard>
Message-ID: <CANqkERCzQdViRjhtz19wbSWEEnxYjpDcuUZNP9jNHYrtANwp-g@mail.gmail.com>

On Mon, Aug 20, 2012 at 7:44 AM, Anton Vorontsov
<anton.vorontsov at linaro.org> wrote:
>
> - KGDB/KDB FIQ debugger shell is synchronous. In Google's version you
>   could have a dedicated shell always running in the FIQ context, so
>   when you type something on a serial line, you won't actually cause any
>   debugging actions, FIQ would save the characters in its own buffer and
>   continue execution normally. But when you hit return key after the
>   command, then the command is executed.
>
>   In KGDB/KDB FIQ debugger it is different. Once you enter KGDB, the
>   kernel will stop until you instruct it to continue.
>
>   This might look as a drastic change, but it is not. There is actually
>   no difference whether you have sync or async shell, or at least I
>   couldn't find any use-case where this would matter at all. Anyways, it
>   is still possible to do async shell in KDB, just don't see any need
>   for this.

The main reason we did this asynchronously was that it's entirely possible
to get the occasional random character on the debug serial port (which is
often multiplexed with the audio path on the headphone jack), and having
the device freeze mysteriously when this happens is problematic.

Since the FIQ debugger is incredibly useful for diagnosing "my device is
stuck" type problems, we tend to leave it enabled on large numbers of
devices during internal testing, so that if somebody runs into a problem
an engineer can plug in a serial debug cable and take a look.  It's
important that the presence of the debug feature doesn't lead to instability,
and thus we don't want a single random character to stop the normal
operation ofthe device.

Brian


From arnd at arndb.de  Mon Aug 20 16:56:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 20:56:28 +0000
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <1345450787-17246-2-git-send-email-Barry.Song@csr.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-2-git-send-email-Barry.Song@csr.com>
Message-ID: <201208202056.28361.arnd@arndb.de>

On Monday 20 August 2012, Barry Song wrote:
> From: Barry Song <Baohua.Song at csr.com>
> 
> we will have SiRFMarco and SiRFPolo, all of them will be in the
> generic board.
> 
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  arch/arm/mach-prima2/Makefile                      |    2 +-
>  arch/arm/mach-prima2/{prima2.c => board-generic.c} |   10 ++++++----
>  2 files changed, 7 insertions(+), 5 deletions(-)
>  rename arch/arm/mach-prima2/{prima2.c => board-generic.c} (81%)

I would prefer not to have a board-* file in there, because it's not
specific to a board. If you want to get rid of the prima2 name in it,
you can call it common.c.

> diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/board-generic.c
> similarity index 81%
> rename from arch/arm/mach-prima2/prima2.c
> rename to arch/arm/mach-prima2/board-generic.c
> index e9a17ae..f06b887 100644
> --- a/arch/arm/mach-prima2/prima2.c
> +++ b/arch/arm/mach-prima2/board-generic.c
> @@ -30,12 +30,13 @@ void __init sirfsoc_init_late(void)
>  	sirfsoc_pm_init();
>  }
>  
> -static const char *prima2cb_dt_match[] __initdata = {
> -       "sirf,prima2-cb",
> +#ifdef CONFIG_ARCH_PRIMA2
> +static const char *prima2_dt_match[] __initdata = {
> +       "sirf,prima2",
>         NULL
>  };
>  
> -MACHINE_START(PRIMA2_EVB, "prima2cb")
> +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
>  	/* Maintainer: Barry Song <baohua.song at csr.com> */
>  	.atag_offset	= 0x100,
>  	.map_io         = sirfsoc_map_lluart,
> @@ -44,6 +45,7 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
>  	.dma_zone_size	= SZ_256M,
>  	.init_machine	= sirfsoc_mach_init,
>  	.init_late	= sirfsoc_init_late,
> -	.dt_compat      = prima2cb_dt_match,
> +	.dt_compat      = prima2_dt_match,
>  	.restart	= sirfsoc_restart,
>  MACHINE_END
> +#endif

I suppose this never really worked before then?

	Arnd


From arnd at arndb.de  Mon Aug 20 17:06:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 20 Aug 2012 21:06:42 +0000
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <1345450787-17246-3-git-send-email-Barry.Song@csr.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-3-git-send-email-Barry.Song@csr.com>
Message-ID: <201208202106.43206.arnd@arndb.de>

On Monday 20 August 2012, Barry Song wrote:
> From: Barry Song <Baohua.Song at csr.com>
> 
> We will have SiRF Marco and Polo, so rename the dir to mach-sirf
> and add Kconfig menu
> 
> Signed-off-by: Baohua Song <Baohua.Song at csr.com>
> ---
>  arch/arm/Kconfig                                   |   10 +++++-----
>  arch/arm/Makefile                                  |    2 +-
>  arch/arm/mach-sirf/Kconfig                         |   16 ++++++++++++++++
>  arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    0
>  arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
>  .../arm/{mach-prima2 => mach-sirf}/board-generic.c |    0
>  arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
>  .../include/mach/clkdev.h                          |    0
>  .../include/mach/debug-macro.S                     |    0
>  .../include/mach/entry-macro.S                     |    0
>  .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
>  .../include/mach/hardware.h                        |    0
>  .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
>  .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0

I'm not sure if we should rename all of these right now. I've been thinking
about moving all of recent and simple ARMv7 based platforms (socfpga, zynq,
prima2, ...) into a single directory, where they would basically end up
being one file per platform. We should discuss this at the ARM mini summit,
and I can let you know the outcome of it. I don't object on the rename in
principle, but it might end up causing extra churn.

> +if ARCH_SIRF
> +
> +choice
> +       prompt "Qualcomm SiRF SoC Type"
> +       default ARCH_PRIMA2

I'm curious about this: I did read that Samsung acquired CSR, and
you list the chips as Qualcomm. What's the story here?

> +config ARCH_PRIMA2
> +       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
> +       select CPU_V7
> +       select ZONE_DMA
> +       help
> +          Support for CSR SiRFSoC ARM Cortex A9 Platform
> +
> +endchoice

Is this still needed? When you add other SoC type here, would you
build kernels that are for just one of them in practice?  If they
are completely generic anyway, you can skip the submenu.

	Arnd


From anton.vorontsov at linaro.org  Mon Aug 20 17:24:51 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Mon, 20 Aug 2012 14:24:51 -0700
Subject: [PATCH v4 0/12] KGDB/KDB FIQ (NMI) debugger
In-Reply-To: <CANqkERCzQdViRjhtz19wbSWEEnxYjpDcuUZNP9jNHYrtANwp-g@mail.gmail.com>
References: <20120820144449.GA32560@lizard>
 <CANqkERCzQdViRjhtz19wbSWEEnxYjpDcuUZNP9jNHYrtANwp-g@mail.gmail.com>
Message-ID: <20120820212451.GA15823@lizard>

Hi Brian,

On Mon, Aug 20, 2012 at 01:51:33PM -0700, Brian Swetland wrote:
> > - KGDB/KDB FIQ debugger shell is synchronous. In Google's version you
> >   could have a dedicated shell always running in the FIQ context,
[...]
> The main reason we did this asynchronously was that it's entirely possible
> to get the occasional random character on the debug serial port (which is
> often multiplexed with the audio path on the headphone jack), and having
> the device freeze mysteriously when this happens is problematic.
> 
> Since the FIQ debugger is incredibly useful for diagnosing "my device is
> stuck" type problems, we tend to leave it enabled on large numbers of
> devices during internal testing, so that if somebody runs into a problem
> an engineer can plug in a serial debug cable and take a look.  It's
> important that the presence of the debug feature doesn't lead to instability,
> and thus we don't want a single random character to stop the normal
> operation ofthe device.

Yup, and that's why in my approach I implemented a tiny async "shell" on
to of KDB, the shell accepts just one command "$3#33" -- GDB-protocol
escape sequence:

/**
 * kgdb_nmi_poll_knock - Check if it is time to enter the debugger
 *
 * "Serial ports are often noisy, especially when muxed over another port (we
 * often use serial over the headset connector). Noise on the async command
 * line just causes characters that are ignored, on a command line that blocked
 * execution noise would be catastrophic." -- Colin Cross
 *
 * So, this function implements KGDB/KDB knocking on the serial line: we won't
 * enter the debugger until we receive a known magic phrase (which is actually
 * "$3#33", known as "escape to KDB" command.
 ...

I.e. the kernel will print this prompt on the NMI debugger console:

        Type $3#33 to enter the debugger>

And this command will be processed asynchronously.

Thanks!

Anton.


From rmallon at gmail.com  Mon Aug 20 19:01:07 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 21 Aug 2012 09:01:07 +1000
Subject: [PATCH v2] ARM: ep93xx: Use HW MAC filter in ethernet driver
In-Reply-To: <1345406296.20237.4.camel@localhost>
References: <1345406296.20237.4.camel@localhost>
Message-ID: <5032C1B3.4030809@gmail.com>

On 20/08/12 05:58, Yan Burman wrote:
> ARM: ep93xx: Use HW MAC filter in ethernet driver
> Use HW MAC filtering for broadcasts and multicasts.
> Do not always work in promiscuous mode.
> Partially based on kernel 2.6.20.4 driver from cirrus logic.
> Tested on 9302 and 9315 based boards.
> 
> Changes from v1:
> * Some minor style fixes
> * Use CRC32 code instead of duplicating code
> * Fixed multicast reception (tested with omping)
> 
> Signed-off-by: Yan Burman <burman.yan at gmail.com>

Hi Yan,

Some very minor comments below. Otherwise looks fine. Repost with the
changes and I'll get this into my tree.

Thanks,
~Ryan

> 
> diff --git a/drivers/net/ethernet/cirrus/Kconfig b/drivers/net/ethernet/cirrus/Kconfig
> index 8388e36..b7b154f 100644
> --- a/drivers/net/ethernet/cirrus/Kconfig
> +++ b/drivers/net/ethernet/cirrus/Kconfig
> @@ -46,6 +46,7 @@ config EP93XX_ETH
>  	depends on ARM && ARCH_EP93XX
>  	select NET_CORE
>  	select MII
> +	select CRC32
>  	help
>  	  This is a driver for the ethernet hardware included in EP93xx CPUs.
>  	  Say Y if you are building a kernel for EP93xx based devices.
> diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> index 78c5521..27299ce 100644
> --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
> +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> @@ -25,6 +25,7 @@
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> +#include <linux/crc32.h>
>  
>  #include <mach/hardware.h>
>  
> @@ -37,8 +38,32 @@
>  #define MAX_PKT_SIZE		2044
>  #define PKT_BUF_SIZE		2048
>  
> +#define HASH_TBL_ENTRIES	8
> +
>  #define REG_RXCTL		0x0000
> -#define  REG_RXCTL_DEFAULT	0x00073800
> +#define  REG_RXCTL_PauseA  (1 << 20)

Please use capitals only for register #defines.

> +#define  REG_RXCTL_RxFCE1  (1 << 19)
> +#define  REG_RXCTL_RxFCE0  (1 << 18)
> +#define  REG_RXCTL_BCRC    (1 << 17)
> +#define  REG_RXCTL_SRxON   (1 << 16)
> +#define  REG_RXCTL_RCRCA   (1 << 13)
> +#define  REG_RXCTL_RA      (1 << 12)
> +#define  REG_RXCTL_PA      (1 << 11)
> +#define  REG_RXCTL_BA      (1 << 10)
> +#define  REG_RXCTL_MA      (1 << 9)
> +#define  REG_RXCTL_IAHA    (1 << 8)
> +#define  REG_RXCTL_IA3     (1 << 3)
> +#define  REG_RXCTL_IA2     (1 << 2)
> +#define  REG_RXCTL_IA1     (1 << 1)
> +#define  REG_RXCTL_IA0     (1 << 0)
> +#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
> +				REG_RXCTL_RA | \
> +				REG_RXCTL_RCRCA | \
> +				REG_RXCTL_SRxON | \
> +				REG_RXCTL_BCRC | \
> +				REG_RXCTL_RxFCE0 | \
> +				REG_RXCTL_IA0)
> +
>  #define REG_TXCTL		0x0004
>  #define  REG_TXCTL_ENABLE	0x00000001
>  #define REG_MIICMD		0x0010
> @@ -57,6 +82,12 @@
>  #define  REG_INTSTS_RX		0x00000004
>  #define REG_INTSTSC		0x002c
>  #define REG_AFP			0x004c
> +#define  REG_AFP_IA0		0
> +#define  REG_AFP_IA1		1
> +#define  REG_AFP_IA2		2
> +#define  REG_AFP_IA3		3
> +#define  REG_AFP_DTxP		6
> +#define  REG_AFP_HASH		7
>  #define REG_INDAD0		0x0050
>  #define REG_INDAD1		0x0051
>  #define REG_INDAD2		0x0052
> @@ -386,6 +417,51 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
>  	return NETDEV_TX_OK;
>  }
>  
> +static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *buf)
> +{
> +	struct netdev_hw_addr *ha;
> +	u32 crc;
> +
> +	netdev_for_each_mc_addr(ha, dev) {
> +		crc = ether_crc_le(ETH_ALEN, ha->addr);
> +		buf[crc >> 29] |= (1 << ((crc >> 26) & 7));
> +	}
> +}
> +
> +static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *buf)
> +{
> +	u32 rxctl;
> +	unsigned int i, len;
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	switch (afp) {
> +	case REG_AFP_IA0:
> +	case REG_AFP_IA1:
> +	case REG_AFP_IA2:
> +	case REG_AFP_IA3:
> +	case REG_AFP_DTxP:
> +		len = ETH_ALEN;
> +		break;
> +
> +	case REG_AFP_HASH:
> +		len = HASH_TBL_ENTRIES;
> +		break;
> +
> +	default:
> +		pr_crit("invalid afp value: %d\n", afp);
> +		return -1;

errno code please. Also, the return value of this function is never
checked by its callers. Should it be?

> +	}
> +
> +	rxctl = rdl(ep, REG_RXCTL);
> +	wrl(ep, REG_RXCTL, ~REG_RXCTL_SRxON & rxctl);

Nitpick - I think maybe it is more readable the other way round?

	wrl(ep, REG_RXCTL, rxctl & ~REG_RXCTL_SRXON);

> +	wrl(ep, REG_AFP, afp);
> +	for (i = 0; i < len; i++)
> +		wrb(ep, REG_INDAD0 + i, buf[i]);
> +	wrl(ep, REG_RXCTL, rxctl);
> +
> +	return 0;
> +}
> +
>  static void ep93xx_tx_complete(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -615,13 +691,7 @@ static int ep93xx_start_hw(struct net_device *dev)
>  	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
>  	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
>  
> -	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
> -	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
> -	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
> -	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
> -	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
> -	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
> -	wrl(ep, REG_AFP, 0);
> +	ep93xx_ind_addr_write(dev, REG_AFP_IA0, dev->dev_addr);
>  
>  	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
>  
> @@ -647,6 +717,32 @@ static void ep93xx_stop_hw(struct net_device *dev)
>  		pr_crit("hw failed to reset\n");
>  }
>  
> +static void ep93xx_set_multicast_list(struct net_device *dev)
> +{
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	if (dev->flags & IFF_PROMISC) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
> +	} else if (dev->flags & IFF_ALLMULTI) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
> +		ep93xx_ind_addr_write(dev, REG_AFP_HASH,
> +			      "\xff\xff\xff\xff\xff\xff\xff\xff");
> +	} else if (!netdev_mc_empty(dev)) {
> +		u8 tblMulti[HASH_TBL_ENTRIES + 1];
> +
> +		memset(tblMulti, 0, sizeof(tblMulti));

Nitpick - this can be written as:

	u8 tbl_multi[HASH_TBL_ENTRIES + 1] = {0};

Use underscores in variable names, no camel-case please.

> +
> +		ep93xx_set_mcast_tbl(dev, tblMulti);
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(~REG_RXCTL_PA & rdl(ep, REG_RXCTL)));
> +		ep93xx_ind_addr_write(dev, REG_AFP_HASH, tblMulti);
> +	} else {
> +		wrl(ep, REG_RXCTL,
> +			~(REG_RXCTL_PA | REG_RXCTL_MA) & rdl(ep, REG_RXCTL));
> +	}
> +}
> +
>  static int ep93xx_open(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -754,6 +850,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
>  	.ndo_validate_addr	= eth_validate_addr,
>  	.ndo_change_mtu		= eth_change_mtu,
>  	.ndo_set_mac_address	= eth_mac_addr,
> +	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
>  };
>  
>  static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
> 
> 



From aaro.koskinen at iki.fi  Mon Aug 20 19:01:05 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 21 Aug 2012 02:01:05 +0300
Subject: [PATCH 2/3] ARM: DMA-Mapping: print warning when atomic
 coherent allocation fails
In-Reply-To: <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120820230058.GA755@harshnoise.musicnaut.iki.fi>

Hi,

On Mon, Aug 20, 2012 at 12:47:27PM +0200, Marek Szyprowski wrote:
> @@ -461,6 +461,9 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
>  		bitmap_set(pool->bitmap, pageno, count);
>  		ptr = pool->vaddr + PAGE_SIZE * pageno;
>  		*ret_page = pool->page + pageno;
> +	} else {
> +		pr_err("Atomic coherent pool too small!\n"
> +		       "Please increase it with coherent_pool= kernel parameter!\n");

This should be rate limited, perhaps even printed only once.

A.


From aaro.koskinen at iki.fi  Mon Aug 20 19:14:19 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 21 Aug 2012 02:14:19 +0300
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120820231419.GB755@harshnoise.musicnaut.iki.fi>

On Mon, Aug 20, 2012 at 12:47:28PM +0200, Marek Szyprowski wrote:
> The default 256 KiB coherent pool may be too small for some of the Kirkwood
> devices, so increase it to make sure that devices will be able to allocate
> their buffers with GFP_ATOMIC flag.
[...]
> +	/*
> +	 * Some Kirkwood devices allocate their coherent buffers from atomic
> +	 * context. Increase size of atomic coherent pool to make sure such
> +	 * the allocations won't fail.
> +	 */
> +	init_dma_coherent_pool_size(SZ_1M);

Not sure if it's a valid use case, but what if some user wants to drop
e.g. SATA driver and and free up some memory. Would a smaller coherent
pool kernel parameter override this code in that case?

A.


From omar.luna at linaro.org  Mon Aug 20 21:13:47 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Mon, 20 Aug 2012 20:13:47 -0500
Subject: [PATCH 1/3] ARM: OMAP: hwmod: partially un-reset hwmods might not
 be properly enabled
In-Reply-To: <50324E84.6080407@ti.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-2-git-send-email-omar.luna@linaro.org>
 <50324E84.6080407@ti.com>
Message-ID: <CALLhW=44R0H-3k5qU=Uckf9UjzP2=xLFYXJt8Nce7VoKFpX_dQ@mail.gmail.com>

Hi Benoit,

On 20 August 2012 09:49, Benoit Cousson <b-cousson at ti.com> wrote:
> On 07/16/2012 09:21 PM, Omar Ramirez Luna wrote:
>> Some IP blocks might not be using/controlling more than one
>> reset line, this check loosens the restriction to fully use
>> hwmod framework for those drivers.
>>
>> E.g.: ipu has reset lines: mmu_cache, cpu0 and cpu1.
>> - cpu1 might not be used and hence (with previous check)
>>   won't be fully enabled by hwmod code.
>
> You mean that you might have some case where you need to enable the
> mmu_cache and cpu0 and thus deassert only the mmu/cpu0 while keeping the
> cpu1 under reset?
>
> So the any_hardreset is indeed not appropriate in that case.
>
> In fact, since the hardreset cannot be handled at all by the hwmod fmwk,
> I'm even wondering if we should take care of checking the state at all.
> But as Paul stated, if was done due to the lack of understanding about
> the diver usage, so maybe things will become clearer once we will have
> that code available.
>
> So I guess that checking for all the lines for the hardreset state is
> anyway already a first step toward a good understanding of the reset
> need for the remote processors.
>
> The patch looks fine to me considering that we do not have a lot of
> information about the usage :-(
>
> Maybe you could add more information in the changelog to explain the way
> you are going to use the reset API.

I'll add an updated description with more information.

Thanks for the comments,

Omar


From omar.luna at linaro.org  Mon Aug 20 21:15:16 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Mon, 20 Aug 2012 20:15:16 -0500
Subject: [PATCH 2/3] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <50320FC4.2020100@ti.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-3-git-send-email-omar.luna@linaro.org>
 <alpine.DEB.2.00.1208020150240.4177@utopia.booyaka.com>
 <CALLhW=6-b+kjfG-u3+uXiD64UwoNEdufjJKu0Mx-sGWp6n9csg@mail.gmail.com>
 <501B609F.9030403@ti.com>
 <CALLhW=7yJTq_cfB=KGY5VT8fNO1u_hrY118ysihFuQA+gVFRuQ@mail.gmail.com>
 <50320FC4.2020100@ti.com>
Message-ID: <CALLhW=6DNiH4pimWVB3o3uoCp2sC6gqub4_DqE+MB1Chjri8sw@mail.gmail.com>

Hi Benoit,

On 20 August 2012 05:21, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Omar,
>
> On 08/03/2012 05:52 PM, Omar Ramirez Luna wrote:
>> On 3 August 2012 00:24, Vaibhav Hiremath <hvaibhav at ti.com> wrote:
>>> On 8/3/2012 3:50 AM, Omar Ramirez Luna wrote:
>>>> So in _enable:
>>>>
>>>>         _enable_clocks(oh);
>>>>         if (soc_ops.enable_module)
>>>>                 soc_ops.enable_module(oh);
>>>>
>>>> The enable_module part seems redundant to me, since the module should
>>>> be already enabled by the first call to _enable_clocks.
>>>
>>> Yes they do same thing, I believe the plan is to get rid of all clock
>>> leaf-nodes in the near future, and let hwmod handle module
>>> enable/disable part.
>>
>> If this is the case then an enable_module call is needed in my patch
>> for when these changes are made. The original works fine but only
>> because currently clock framework does what enable_module is doing.
>
> Yes, that's the case, but I plan to remove most of the leaf clocks ASAP,
> so we cannot rely on that.
>
>> Please let me know if you want me to resend with this change.
>
> Yes, could you please repost with that change?

Not a problem.

> It will be good as well that you remove the leaf clock and use the
> parent clock of current leaf as the main_clock. In that case it will
> ensure that this is the hwmod fmwk that does enable the modulemode and
> not the clock fmwk.

Ok, let me try that.

Thanks for the comments,

Omar


From festevam at gmail.com  Mon Aug 20 21:43:15 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 20 Aug 2012 22:43:15 -0300
Subject: [PATCH] ARM: olinuxino: Add gpio-led support
Message-ID: <1345513396-12320-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Olinuxino has a LED connected to MX23_PAD_SSP1_DETECT__GPIO_2_1 pin.

Since mmc0_4bit_pins_a defines MX23_PAD_SSP1_DETECT as SSP function, create
a new mmc0_4bit_pins_b.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx23-olinuxino.dts |   28 +++++++++++++++++++++++++++-
 arch/arm/boot/dts/imx23.dtsi          |   15 +++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index a286873..dece3fe 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -27,10 +27,25 @@
 			ssp0: ssp at 80010000 {
 				compatible = "fsl,imx23-mmc";
 				pinctrl-names = "default";
-				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+				pinctrl-0 = <&mmc0_4bit_pins_b &mmc0_pins_fixup>;
 				bus-width = <4>;
 				status = "okay";
 			};
+
+			pinctrl at 80018000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&hog_pins_a>;
+
+				hog_pins_a: hog-gpios at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+			};
 		};
 
 		apbx at 80040000 {
@@ -47,4 +62,15 @@
 			};
 		};
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		user {
+			label = "green";
+			gpios = <&gpio2 1 0>;
+			linux,default-trigger = "default-on";
+			default-state = "on";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 9700872..a8b423a 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -202,6 +202,21 @@
 					fsl,pull-up = <1>;
 				};
 
+				mmc0_4bit_pins_b: mmc0-4bit_b at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
+						0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
+						0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
+						0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
+						0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
+						0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
 				mmc0_8bit_pins_a: mmc0-8bit at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
-- 
1.7.9.5



From 21cnbao at gmail.com  Mon Aug 20 21:49:04 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 09:49:04 +0800
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <201208202056.28361.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-2-git-send-email-Barry.Song@csr.com>
 <201208202056.28361.arnd@arndb.de>
Message-ID: <CAGsJ_4wR1dU05QutVeKHephDmSpSKOki1+AGZVV95hf3ABePDA@mail.gmail.com>

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Monday 20 August 2012, Barry Song wrote:
>> From: Barry Song <Baohua.Song at csr.com>
>>
>> we will have SiRFMarco and SiRFPolo, all of them will be in the
>> generic board.
>>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> ---
>>  arch/arm/mach-prima2/Makefile                      |    2 +-
>>  arch/arm/mach-prima2/{prima2.c => board-generic.c} |   10 ++++++----
>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>  rename arch/arm/mach-prima2/{prima2.c => board-generic.c} (81%)
>
> I would prefer not to have a board-* file in there, because it's not
> specific to a board. If you want to get rid of the prima2 name in it,
> you can call it common.c.

that is fine to me. i rename to board-generic.c just because omap and
some others did like that.
and i'll add marco and polo DT_MACHINE_START to this file too.

>
>> diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/board-generic.c
>> similarity index 81%
>> rename from arch/arm/mach-prima2/prima2.c
>> rename to arch/arm/mach-prima2/board-generic.c
>> index e9a17ae..f06b887 100644
>> --- a/arch/arm/mach-prima2/prima2.c
>> +++ b/arch/arm/mach-prima2/board-generic.c
>> @@ -30,12 +30,13 @@ void __init sirfsoc_init_late(void)
>>       sirfsoc_pm_init();
>>  }
>>
>> -static const char *prima2cb_dt_match[] __initdata = {
>> -       "sirf,prima2-cb",
>> +#ifdef CONFIG_ARCH_PRIMA2
>> +static const char *prima2_dt_match[] __initdata = {
>> +       "sirf,prima2",
>>         NULL
>>  };
>>
>> -MACHINE_START(PRIMA2_EVB, "prima2cb")
>> +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
>>       /* Maintainer: Barry Song <baohua.song at csr.com> */
>>       .atag_offset    = 0x100,
>>       .map_io         = sirfsoc_map_lluart,
>> @@ -44,6 +45,7 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
>>       .dma_zone_size  = SZ_256M,
>>       .init_machine   = sirfsoc_mach_init,
>>       .init_late      = sirfsoc_init_late,
>> -     .dt_compat      = prima2cb_dt_match,
>> +     .dt_compat      = prima2_dt_match,
>>       .restart        = sirfsoc_restart,
>>  MACHINE_END
>> +#endif
>
> I suppose this never really worked before then?

i am not sure what you mean, but this does work and i tested and found
prima2 can boot normally.

>
>         Arnd

-barry


From bill4carson at gmail.com  Mon Aug 20 21:55:17 2012
From: bill4carson at gmail.com (bill4carson)
Date: Tue, 21 Aug 2012 09:55:17 +0800
Subject: ARM hugetlb support?
In-Reply-To: <CANOLnOPLLQ=Cy5rvf5J7R96whrvLKO4HW9nVn4rQXqXCTVgCPA@mail.gmail.com>
References: <CANOLnOPLLQ=Cy5rvf5J7R96whrvLKO4HW9nVn4rQXqXCTVgCPA@mail.gmail.com>
Message-ID: <5032EA85.9030404@gmail.com>



On 2012?08?20? 07:18, Grazvydas Ignotas wrote:
> Hello,
>
> We are developing an application that's drawing various geometry on
> 1024x1024 framebuffer (lines, triangles, etc) and is running on
> Cortex-A8 CPU. It seems this kind of application is suffering badly
> from TLB misses, as A8 only has 32 entry TLB cache.
>
> I've found that hugetlb support patches have been posted some months
> ago [1]. I've been testing them with very good results [2]. Are there
> still plans to further develop them and eventually merge them?
>
Hi, Grazvydas

I'm glad you got performance boost with my hugetlb patch!

It's a pity this patch series probably will not be developed.
I really don't have much time to continue with the development,
especially provide statistics how arm huge tlb could be tunned
well to produce better performance, that's based on much testing
and also application specific.

Anyway, query and discussion are always welcome.

>
> [1] http://marc.info/?l=linux-arm-kernel&m=132912620601308&w=2
> [2] Cycle measurements of rendering full scene (using cycle counter in
> A8), x1000 cycles:
>
>         normal hugetlb improvement
> scene1 28507  21351   34%
> scene2 11710  10138   16%
> scene3 17178  13631   26%
> scene4 4372   3810    15%
> scene5 3525   3255    8%
>

-- 
Love each day!

--bill


From 21cnbao at gmail.com  Mon Aug 20 21:56:02 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 09:56:02 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <201208202106.43206.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-3-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
Message-ID: <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Monday 20 August 2012, Barry Song wrote:
>> From: Barry Song <Baohua.Song at csr.com>
>>
>> We will have SiRF Marco and Polo, so rename the dir to mach-sirf
>> and add Kconfig menu
>>
>> Signed-off-by: Baohua Song <Baohua.Song at csr.com>
>> ---
>>  arch/arm/Kconfig                                   |   10 +++++-----
>>  arch/arm/Makefile                                  |    2 +-
>>  arch/arm/mach-sirf/Kconfig                         |   16 ++++++++++++++++
>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    0
>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
>>  .../arm/{mach-prima2 => mach-sirf}/board-generic.c |    0
>>  arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
>>  .../include/mach/clkdev.h                          |    0
>>  .../include/mach/debug-macro.S                     |    0
>>  .../include/mach/entry-macro.S                     |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
>>  .../include/mach/hardware.h                        |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0
>
> I'm not sure if we should rename all of these right now. I've been thinking
> about moving all of recent and simple ARMv7 based platforms (socfpga, zynq,
> prima2, ...) into a single directory, where they would basically end up
> being one file per platform. We should discuss this at the ARM mini summit,
> and I can let you know the outcome of it. I don't object on the rename in
> principle, but it might end up causing extra churn.

ok. i will follow the output of  ARM mini summit.

>
>> +if ARCH_SIRF
>> +
>> +choice
>> +       prompt "Qualcomm SiRF SoC Type"
>> +       default ARCH_PRIMA2
>
> I'm curious about this: I did read that Samsung acquired CSR, and
> you list the chips as Qualcomm. What's the story here?

sorry. this is typo.
prompt "Qualcomm SiRF SoC Type"
->
prompt "CSR SiRF SoC Type"

>
>> +config ARCH_PRIMA2
>> +       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
>> +       select CPU_V7
>> +       select ZONE_DMA
>> +       help
>> +          Support for CSR SiRFSoC ARM Cortex A9 Platform
>> +
>> +endchoice
>
> Is this still needed? When you add other SoC type here, would you
> build kernels that are for just one of them in practice?  If they
> are completely generic anyway, you can skip the submenu.
>

for the moment, that is needed just because the DEBUG UART base
address is difficult for different SoC. debug-macro.S is very early,
it depends on the SIRFSOC_UART1_PA_BASE.

 /* UART-1: used as serial debug port */
 #ifdef CONFIG_ARCH_PRIMA2
#define SIRFSOC_UART1_PA_BASE          0xb0060000
 #elif defined(CONFIG_ARCH_MARCO)
#define SIRFSOC_UART1_PA_BASE          0xcc060000
#endif
otherwise, PRIMA2 and MARCO can co-exist.

i think i can find some ways to set the rp dynamically according to chip type.
         .macro  addruart, rp, rv, tmp
         ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
         ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
         .endm


>         Arnd
>

-barry


From 21cnbao at gmail.com  Mon Aug 20 22:06:50 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 10:06:50 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <201208202106.43206.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-3-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
Message-ID: <CAGsJ_4yWzdzJMrCqWWozKBrkSJ7O5thpP+mYTTEsN8+AuO03wA@mail.gmail.com>

Hi Arnd,

more comments.

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Monday 20 August 2012, Barry Song wrote:
>> From: Barry Song <Baohua.Song at csr.com>
>>
>> We will have SiRF Marco and Polo, so rename the dir to mach-sirf
>> and add Kconfig menu
>>
>> Signed-off-by: Baohua Song <Baohua.Song at csr.com>
>> ---
>>  arch/arm/Kconfig                                   |   10 +++++-----
>>  arch/arm/Makefile                                  |    2 +-
>>  arch/arm/mach-sirf/Kconfig                         |   16 ++++++++++++++++
>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    0
>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
>>  .../arm/{mach-prima2 => mach-sirf}/board-generic.c |    0
>>  arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
>>  .../include/mach/clkdev.h                          |    0
>>  .../include/mach/debug-macro.S                     |    0
>>  .../include/mach/entry-macro.S                     |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
>>  .../include/mach/hardware.h                        |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
>>  .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0
>
> I'm not sure if we should rename all of these right now. I've been thinking
> about moving all of recent and simple ARMv7 based platforms (socfpga, zynq,
> prima2, ...) into a single directory, where they would basically end up
> being one file per platform. We should discuss this at the ARM mini summit,
> and I can let you know the outcome of it. I don't object on the rename in
> principle, but it might end up causing extra churn.

we will have other SoCs which are more complex than primaII. i am not
sure whether you can merge all of them into a single dir together with
zynq or other platforms.
i am debugging the patches of MARCO and will send them soon. this
series is just preparing for delivering MARCO patches.

>
>> +if ARCH_SIRF
>> +
>> +choice
>> +       prompt "Qualcomm SiRF SoC Type"
>> +       default ARCH_PRIMA2
>
> I'm curious about this: I did read that Samsung acquired CSR, and
> you list the chips as Qualcomm. What's the story here?

BTW, i just want to clarify Samsung  acquired the mobile business of
CSR, not including our primaII or other SoCs.

>
>> +config ARCH_PRIMA2
>> +       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
>> +       select CPU_V7
>> +       select ZONE_DMA
>> +       help
>> +          Support for CSR SiRFSoC ARM Cortex A9 Platform
>> +
>> +endchoice
>
> Is this still needed? When you add other SoC type here, would you
> build kernels that are for just one of them in practice?  If they
> are completely generic anyway, you can skip the submenu.
>
>         Arnd
>

-barry


From andrew at lunn.ch  Tue Aug 21 01:10:01 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 21 Aug 2012 07:10:01 +0200
Subject: [PATCH] ARM: Kirkwood: Iomega ix2-200 DT support Signed-off-by:
 Alan M Butler <alanbutty12@gmail.com>
In-Reply-To: <2b8d12ce68911cc12c96dcdd60c3345b72d25780.1345472556.git.alanbutty12@gmail.com>
References: <cover.1345472556.git.alanbutty12@gmail.com>
 <2b8d12ce68911cc12c96dcdd60c3345b72d25780.1345472556.git.alanbutty12@gmail.com>
Message-ID: <20120821051001.GB30810@lunn.ch>

On Mon, Aug 20, 2012 at 03:29:07PM +0100, Alan M Butler wrote:
> Patch version 5.
> Add support for the Iomega ix2-200.
> Led's and buttons working as of kernel 3.6-rc2
> 
> the 3 lines in the network interface do seem to be required as
> removing either causes the network card to not be able to reach
> the network (at least on my device).
> 
> Product page:
> http://go.iomega.com/en/products/network-storage-desktop/storcenter-network-storage-solution/network-hard-drive-ix2-200-cloud/?partner=4735#tech_specsItem_tab
> 
> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>
> 
> ---
>  arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts |  105 +++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/Kconfig                |    7 ++
>  arch/arm/mach-kirkwood/Makefile               |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot          |    1 +
>  arch/arm/mach-kirkwood/board-dt.c             |    4 +
>  arch/arm/mach-kirkwood/board-iomega_ix2_200.c |   57 ++++++++++++++
>  arch/arm/mach-kirkwood/common.h               |    6 ++
>  7 files changed, 181 insertions(+)
>  create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> 
> diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> new file mode 100644
> index 0000000..865aeec
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
> @@ -0,0 +1,105 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "Iomega StorCenter ix2-200";
> +	compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x10000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	ocp at f1000000 {
> +		i2c at 11000 {
> +			status = "okay";
> +
> +			lm63: lm63 at 4c {
> +				compatible = "national,lm63";
> +				reg = <0x4c>;
> +			};
> +		};
> +
> +		serial at 12000 {
> +			clock-frequency = <200000000>;
> +			status = "ok";
> +		};
> +
> +		nand at 3000000 {
> +			status = "okay";
> +
> +			partition at 0 {
> +				label = "u-boot";
> +				reg = <0x0000000 0x100000>;
> +				read-only;
> +			};
> +
> +			partition at a0000 {
> +				label = "env";
> +				reg = <0xa0000 0x20000>;
> +				read-only;
> +			};
> +
> +			partition at 100000 {
> +				label = "uImage";
> +				reg = <0x100000 0x300000>;
> +			};
> +
> +			partition at 400000 {
> +				label = "uInitrd";
> +				reg = <0x540000 0x1000000>;
> +			};
> +		};
> +		sata at 80000 {
> +			status = "okay";
> +			nr-ports = <2>;
> +		};
> +
> +	};
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		power_led {
> +			label = "status:white:power_led";
> +			gpios = <&gpio0 16 0>;
> +			linux,default-trigger = "default-on";
> +		};
> +		health_led1 {
> +			label = "status:red:health_led";
> +			gpios = <&gpio1 5 0>;
> +		};
> +		health_led2 {
> +			label = "status:white:health_led";
> +			gpios = <&gpio1 4 0>;
> +		};
> +		backup_led {
> +			label = "status:blue:backup_led";
> +			gpios = <&gpio0 15 0>;
> +		};
> +	};
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		Power {
> +			label = "Power Button";
> +			linux,code = <116>;
> +			gpios = <&gpio0 14 1>;
> +		};
> +		Reset {
> +			label = "Reset Button";
> +			linux,code = <0x198>;
> +			gpios = <&gpio0 12 1>;
> +		};
> +		OTB {
> +			label = "OTB Button";
> +			linux,code = <133>;
> +			gpios = <&gpio1 3 1>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index ca5c15a..bee8451 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -195,6 +195,13 @@ config MACH_T5325
>  	  Say 'Y' here if you want your kernel to support the
>  	  HP t5325 Thin Client.
>  
> +config MACH_IOMEGA_IX2_200_DT
> +	bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Iomega StorCenter ix2-200 (Flattened Device Tree).
> +
>  endmenu
>  
>  endif
> diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
> index 055c85a..f5484dc 100644
> --- a/arch/arm/mach-kirkwood/Makefile
> +++ b/arch/arm/mach-kirkwood/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
>  obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
>  obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
>  obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
> +obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)	+= board-iomega_ix2_200.o
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index a571755..59b719d 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
>  dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
>  dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
>  dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
> +dtb-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += kirkwood-iomega_ix2_200.dtb
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index e4eb450..9b3ec17 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
>  	if (of_machine_is_compatible("buffalo,lsxl"))
>  		lsxl_init();
>  
> +	if (of_machine_is_compatible("iom,ix2-200"))
> +		iomega_ix2_200_init();
> +
>  	of_platform_populate(NULL, kirkwood_dt_match_table,
>  			     kirkwood_auxdata_lookup, NULL);
>  }
> @@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
>  	"qnap,ts219",
>  	"seagate,goflexnet",
>  	"buffalo,lsxl",
> +	"iom,ix2-200",
>  	NULL
>  };
>  
> diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> new file mode 100644
> index 0000000..158fb97
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> @@ -0,0 +1,57 @@
> +/*
> + * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
> + *
> + * Iomega StorCenter ix2-200
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/ethtool.h>
> +#include <mach/kirkwood.h>
> +#include "common.h"
> +#include "mpp.h"
> +
> +static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
> +	.phy_addr       = MV643XX_ETH_PHY_NONE,
> +	.speed          = SPEED_1000,
> +	.duplex         = DUPLEX_FULL,
> +};
> +
> +static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
> +	MPP12_GPIO,			/* Reset Button */
> +	MPP14_GPIO,			/* Power Button */
> +	MPP15_GPIO,			/* Backup LED (blue) */
> +	MPP16_GPIO,			/* Power LED (white) */
> +	MPP35_GPIO,			/* OTB Button */
> +	MPP36_GPIO,			/* Rebuild LED (white) */
> +	MPP37_GPIO,			/* Health LED (red) */
> +	MPP38_GPIO,			/* SATA LED brightness control 1 */
> +	MPP39_GPIO,			/* SATA LED brightness control 2 */
> +	MPP40_GPIO,			/* Backup LED brightness control 1 */
> +	MPP41_GPIO,			/* Backup LED brightness control 2 */
> +	MPP42_GPIO,			/* Power LED brightness control 1 */
> +	MPP43_GPIO,			/* Power LED brightness control 2 */
> +	MPP44_GPIO,			/* Health LED brightness control 1 */
> +	MPP45_GPIO,			/* Health LED brightness control 2 */
> +	MPP46_GPIO,			/* Rebuild LED brightness control 1 */
> +	MPP47_GPIO,			/* Rebuild LED brightness control 2 */
> +	0
> +};
> +
> +void __init iomega_ix2_200_init(void)
> +{
> +	/*
> +	 * Basic setup. Needs to be called early.
> +	 */
> +	kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
> +
> +	kirkwood_ehci_init();
> +
> +	kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
> +}
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index 304dd1a..d5d4064 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -94,6 +94,12 @@ void lsxl_init(void);
>  static inline void lsxl_init(void) {};
>  #endif
>  
> +#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
> +void iomega_ix2_200_init(void);
> +#else
> +static inline void iomega_ix2_200_init(void) {};
> +#endif
> +
>  /* early init functions not converted to fdt yet */
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> -- 
> 1.7.9.5
> 

Acked-by: Andrew Lunn <andrew at lunn.ch>

	  Andrew


From linus.walleij at linaro.org  Tue Aug 21 02:16:13 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 08:16:13 +0200
Subject: [GIT PULL] ux500 fixes
Message-ID: <CACRpkdZeTb35naqs7UXo127syN7iPgsHUokRE7B=ER8iJRNhmw@mail.gmail.com>

Hi Arnd, Olof,

here are two audio fixes from Lee Jones for ux500 for the -rc series.
Using a signed tag now!

Please pull them in,
Linus Walleij

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-fixes-v3.6-rc2

for you to fetch changes up to 46a8b9837da20206c6daca11949485fab7b6e875:

  ARM: ux500: Ensure probing of Audio devices when Device Tree is
enabled (2012-08-17 11:21:30 +0200)

----------------------------------------------------------------
Here are two audio fixes for the ux500 found by Lee Jones.

----------------------------------------------------------------
Lee Jones (2):
      ARM: ux500: Fix merge error, no matching driver name for 'snd_soc_u8500'
      ARM: ux500: Ensure probing of Audio devices when Device Tree is enabled

 arch/arm/mach-ux500/board-mop500-msp.c | 10 +++++-----
 arch/arm/mach-ux500/board-mop500.c     |  4 ++++
 2 files changed, 9 insertions(+), 5 deletions(-)


From gregory.clement at free-electrons.com  Tue Aug 21 03:12:41 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 21 Aug 2012 09:12:41 +0200
Subject: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <20120820193622.4e539451@skate>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-5-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdYNZar7865-T12J37h3AWA9-8R1R5tymuOhaB0b3ddEAA@mail.gmail.com>
 <50326A60.1070007@gmail.com> <20120820193622.4e539451@skate>
Message-ID: <503334E9.508@free-electrons.com>

On 08/20/2012 07:36 PM, Thomas Petazzoni wrote:
> Le Mon, 20 Aug 2012 18:48:32 +0200,
> Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :
> 
>> this is really difficult here ;) I thought I could just add PINCTRL_DOVE
>> to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso.
>> But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
>>
>> If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and
>> you work it out if you ever have two distinct MACHs? Or it could remain
>> selectable in pinctrl/Kconfig but that will then be different with the
>> other stubs.
> 
> In order to keep the consistency with other SoC families, maybe we can
> split the 370 and XP options in two separate MACH_ARMADA_370 and
> MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are
> converted to DT+mach-mvebu, we should have:
> 
>  *) arch/arm/Kconfig defines MACH_MVEBU
> 
>  *) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
>     MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
> 
> Then, an user is free to build a single kernel image that supports all,
> or a selection of the supported Marvell EBU SoCs.

I agree with Thomas

> 
> Thomas
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Tue Aug 21 03:29:48 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Tue, 21 Aug 2012 09:29:48 +0200
Subject: [RFC] Add support for Aurora L2 Cache Controller
In-Reply-To: <CAHkRjk4qPPktXsqnRaZLG0Z=VMH_Qf6xRdQBPMvxC20m6noc+A@mail.gmail.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
 <CAHkRjk4qPPktXsqnRaZLG0Z=VMH_Qf6xRdQBPMvxC20m6noc+A@mail.gmail.com>
Message-ID: <503338EC.4070303@free-electrons.com>

On 08/08/2012 05:16 PM, Catalin Marinas wrote:> On 8 August 2012 16:05, Gregory CLEMENT
> <gregory.clement at free-electrons.com> wrote:
>> - two flavors of the controller 'outer cache' and 'system cache' (the
>>   last one meaning maintenance operations on L1 are broadcasted to the
>>   L2 and L2 performs the same operation).
>
> BTW, is the DSB also transparently handled by the L2 in 'system cache' mode?
>

The information I have is that from the point view of the software
there is no need to take any extra actions when using this kind of
command, everything is handle by the hardware. So I guess that the
answer to your question should be yes.

---
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From m.szyprowski at samsung.com  Tue Aug 21 03:31:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 09:31:25 +0200
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <20120820231419.GB755@harshnoise.musicnaut.iki.fi>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
 <20120820231419.GB755@harshnoise.musicnaut.iki.fi>
Message-ID: <000301cd7f6e$fc925130$f5b6f390$%szyprowski@samsung.com>

Hello,

On Tuesday, August 21, 2012 1:14 AM Aaro Koskinen wrote:

> On Mon, Aug 20, 2012 at 12:47:28PM +0200, Marek Szyprowski wrote:
> > The default 256 KiB coherent pool may be too small for some of the Kirkwood
> > devices, so increase it to make sure that devices will be able to allocate
> > their buffers with GFP_ATOMIC flag.
> [...]
> > +	/*
> > +	 * Some Kirkwood devices allocate their coherent buffers from atomic
> > +	 * context. Increase size of atomic coherent pool to make sure such
> > +	 * the allocations won't fail.
> > +	 */
> > +	init_dma_coherent_pool_size(SZ_1M);
> 
> Not sure if it's a valid use case, but what if some user wants to drop
> e.g. SATA driver and and free up some memory. Would a smaller coherent
> pool kernel parameter override this code in that case?

Kernel command line parameter always overrides the value set by platform code
(or the default 256KiB).

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From arnd at arndb.de  Tue Aug 21 03:53:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 07:53:12 +0000
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <CAGsJ_4wR1dU05QutVeKHephDmSpSKOki1+AGZVV95hf3ABePDA@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208202056.28361.arnd@arndb.de>
 <CAGsJ_4wR1dU05QutVeKHephDmSpSKOki1+AGZVV95hf3ABePDA@mail.gmail.com>
Message-ID: <201208210753.12718.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> > On Monday 20 August 2012, Barry Song wrote:
> >
> > I would prefer not to have a board-* file in there, because it's not
> > specific to a board. If you want to get rid of the prima2 name in it,
> > you can call it common.c.
> 
> that is fine to me. i rename to board-generic.c just because omap and
> some others did like that.
> and i'll add marco and polo DT_MACHINE_START to this file too.

Ok. For the older platforms that have a lot of non-DT board files, it makes
sense to have a separate board-generic.c file.

> >> diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/board-generic.c
> >> similarity index 81%
> >> rename from arch/arm/mach-prima2/prima2.c
> >> rename to arch/arm/mach-prima2/board-generic.c
> >> index e9a17ae..f06b887 100644
> >> --- a/arch/arm/mach-prima2/prima2.c
> >> +++ b/arch/arm/mach-prima2/board-generic.c
> >> @@ -30,12 +30,13 @@ void __init sirfsoc_init_late(void)
> >>       sirfsoc_pm_init();
> >>  }
> >>
> >> -static const char *prima2cb_dt_match[] __initdata = {
> >> -       "sirf,prima2-cb",
> >> +#ifdef CONFIG_ARCH_PRIMA2
> >> +static const char *prima2_dt_match[] __initdata = {
> >> +       "sirf,prima2",
> >>         NULL
> >>  };
> >>
> >> -MACHINE_START(PRIMA2_EVB, "prima2cb")
> >> +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
> >>       /* Maintainer: Barry Song <baohua.song at csr.com> */
> >>       .atag_offset    = 0x100,
> >>       .map_io         = sirfsoc_map_lluart,
> >> @@ -44,6 +45,7 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
> >>       .dma_zone_size  = SZ_256M,
> >>       .init_machine   = sirfsoc_mach_init,
> >>       .init_late      = sirfsoc_init_late,
> >> -     .dt_compat      = prima2cb_dt_match,
> >> +     .dt_compat      = prima2_dt_match,
> >>       .restart        = sirfsoc_restart,
> >>  MACHINE_END
> >> +#endif
> >
> > I suppose this never really worked before then?
> 
> i am not sure what you mean, but this does work and i tested and found
> prima2 can boot normally.

I mean the old version, not the new one. If you use MACHINE_START,
you cannot access the device tree data from the boot loader, which
means that none of the device drivers find their devices.

I also just noticed that you ahve both the .atag_offset and the .dt_compat
field set here, which is a bit strange as the dt_compat field was previously
unused. Now, the .atag_offset field is unused, so you should remove that.

	Arnd


From arnd at arndb.de  Tue Aug 21 03:55:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 07:55:26 +0000
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4yWzdzJMrCqWWozKBrkSJ7O5thpP+mYTTEsN8+AuO03wA@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
 <CAGsJ_4yWzdzJMrCqWWozKBrkSJ7O5thpP+mYTTEsN8+AuO03wA@mail.gmail.com>
Message-ID: <201208210755.26253.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> >
> >> +if ARCH_SIRF
> >> +
> >> +choice
> >> +       prompt "Qualcomm SiRF SoC Type"
> >> +       default ARCH_PRIMA2
> >
> > I'm curious about this: I did read that Samsung acquired CSR, and
> > you list the chips as Qualcomm. What's the story here?
> 
> BTW, i just want to clarify Samsung  acquired the mobile business of
> CSR, not including our primaII or other SoCs.

Ah, I had not realized that. Thanks for the clarification.

	Arnd


From arnd at arndb.de  Tue Aug 21 03:57:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 07:57:32 +0000
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
 <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
Message-ID: <201208210757.32852.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> for the moment, that is needed just because the DEBUG UART base
> address is difficult for different SoC. debug-macro.S is very early,
> it depends on the SIRFSOC_UART1_PA_BASE.
> 
>  /* UART-1: used as serial debug port */
>  #ifdef CONFIG_ARCH_PRIMA2
> #define SIRFSOC_UART1_PA_BASE          0xb0060000
>  #elif defined(CONFIG_ARCH_MARCO)
> #define SIRFSOC_UART1_PA_BASE          0xcc060000
> #endif
> otherwise, PRIMA2 and MARCO can co-exist.

Ok, I see.

> i think i can find some ways to set the rp dynamically according to chip type.
>          .macro  addruart, rp, rv, tmp
>          ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
>          ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
>          .endm

The most common way to do this is to have multiple entries in
arch/arm/Kconfig.debug in the "Kernel low-level debugging port"
menu. For production kernels, you would just leave out DEBUG_LL
while for debugging you have to pick one UART.

	Arnd


From 21cnbao at gmail.com  Tue Aug 21 04:26:31 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 16:26:31 +0800
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <201208210753.12718.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208202056.28361.arnd@arndb.de>
 <CAGsJ_4wR1dU05QutVeKHephDmSpSKOki1+AGZVV95hf3ABePDA@mail.gmail.com>
 <201208210753.12718.arnd@arndb.de>
Message-ID: <CAGsJ_4x+sm9=bg1Riyeb6JF0sSC-n=ZBAy6ibx_Styu5rM9yYA@mail.gmail.com>

Hi Arnd,
Thanks.

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Tuesday 21 August 2012, Barry Song wrote:
>> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
>> > On Monday 20 August 2012, Barry Song wrote:
>> >
>> > I would prefer not to have a board-* file in there, because it's not
>> > specific to a board. If you want to get rid of the prima2 name in it,
>> > you can call it common.c.
>>
>> that is fine to me. i rename to board-generic.c just because omap and
>> some others did like that.
>> and i'll add marco and polo DT_MACHINE_START to this file too.
>
> Ok. For the older platforms that have a lot of non-DT board files, it makes
> sense to have a separate board-generic.c file.

ok. then renaming to common.c is better for this full-DT platform.

>
>> >> diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/board-generic.c
>> >> similarity index 81%
>> >> rename from arch/arm/mach-prima2/prima2.c
>> >> rename to arch/arm/mach-prima2/board-generic.c
>> >> index e9a17ae..f06b887 100644
>> >> --- a/arch/arm/mach-prima2/prima2.c
>> >> +++ b/arch/arm/mach-prima2/board-generic.c
>> >> @@ -30,12 +30,13 @@ void __init sirfsoc_init_late(void)
>> >>       sirfsoc_pm_init();
>> >>  }
>> >>
>> >> -static const char *prima2cb_dt_match[] __initdata = {
>> >> -       "sirf,prima2-cb",
>> >> +#ifdef CONFIG_ARCH_PRIMA2
>> >> +static const char *prima2_dt_match[] __initdata = {
>> >> +       "sirf,prima2",
>> >>         NULL
>> >>  };
>> >>
>> >> -MACHINE_START(PRIMA2_EVB, "prima2cb")
>> >> +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
>> >>       /* Maintainer: Barry Song <baohua.song at csr.com> */
>> >>       .atag_offset    = 0x100,
>> >>       .map_io         = sirfsoc_map_lluart,
>> >> @@ -44,6 +45,7 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
>> >>       .dma_zone_size  = SZ_256M,
>> >>       .init_machine   = sirfsoc_mach_init,
>> >>       .init_late      = sirfsoc_init_late,
>> >> -     .dt_compat      = prima2cb_dt_match,
>> >> +     .dt_compat      = prima2_dt_match,
>> >>       .restart        = sirfsoc_restart,
>> >>  MACHINE_END
>> >> +#endif
>> >
>> > I suppose this never really worked before then?
>>
>> i am not sure what you mean, but this does work and i tested and found
>> prima2 can boot normally.
>
> I mean the old version, not the new one. If you use MACHINE_START,
> you cannot access the device tree data from the boot loader, which
> means that none of the device drivers find their devices.

sorry i didn't get you.

DT is read to 0x3608000 by bootloader, and bootm has param "bootm
0x02008000 - 0x3608000" as:

bootcmd=mmc read 0 0x3608000 0x3780 0x80;mmc read 0 0x02008000 0x1800
0x1800;fdt addr 0x3608000;
fdt resize;bootm 0x02008000 - 0x3608000

kernel has been always able to read DT data from bootloader.

>
> I also just noticed that you ahve both the .atag_offset and the .dt_compat
> field set here, which is a bit strange as the dt_compat field was previously
> unused. Now, the .atag_offset field is unused, so you should remove that.
>

i'll remove .atag_offset field then.

>         Arnd

-barry


From will.deacon at arm.com  Tue Aug 21 04:27:35 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 Aug 2012 09:27:35 +0100
Subject: [PATCH v3] ARM: support syscall tracing
In-Reply-To: <5032A1D6.6010605@mentor.com>
References: <50324BED.9000500@mentor.com>
 <20120820172559.GW25864@mudshark.cambridge.arm.com>
 <5032A1D6.6010605@mentor.com>
Message-ID: <20120821082734.GA28660@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 09:45:10PM +0100, Wade Farnsworth wrote:
> Will Deacon wrote:
> >
> > I think that trace_sys_{enter,exit} should take ret rather than scno. A
> > debugger could change the syscall number if TIF_SYSCALL_TRACE is set and
> > that new number should be the one that we use.
> >
> > The style, however, is much better and I think the code is fairly clear now
> > so we just need to wait for my fix to the core code to get merged (it got
> > picked up by Steve Rostedt) and I think we can use ret directly. It might be
> > worth dropping the local variable and using scno for everything, so that
> > it's obvious where the syscall number is stored.
> >
> 
> I agree that your patch needs to get merged before mine gets picked up 
> so that we don't introduce a new bug.  I've sent v4 with the changes you 
> suggest.  Would you like me to modify syscall_trace_* to remove the 
> local variable in this patch as well?  It seems to me that such a rework 
> is better handled separately, but let me know if you think otherwise.

Don't worry about the scno rework -- I'll do that as a separate patch
because I think that the audit calls need updating to use the return value
from ptrace_syscall_trace too (otherwise you could use a debugger to execute
syscalls that you shouldn't be allowed to make).

So, if it's ok with you, I'll take this into my tree and then send it to
Russell along with the scno change once the core fix has been merged into
mainline.

Cheers,

Will

--- >8

diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e0fc5f..90396a6 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -941,15 +941,15 @@ static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
 
 asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
 {
-       int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+       scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
        audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
                            regs->ARM_r2, regs->ARM_r3);
-       return ret;
+       return scno;
 }
 
 asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
 {
-       int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+       scno = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
        audit_syscall_exit(regs);
-       return ret;
+       return scno;
 }



From arnd at arndb.de  Tue Aug 21 04:44:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 08:44:05 +0000
Subject: [PATCH 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <CAGsJ_4x+sm9=bg1Riyeb6JF0sSC-n=ZBAy6ibx_Styu5rM9yYA@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210753.12718.arnd@arndb.de>
 <CAGsJ_4x+sm9=bg1Riyeb6JF0sSC-n=ZBAy6ibx_Styu5rM9yYA@mail.gmail.com>
Message-ID: <201208210844.05153.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> > I mean the old version, not the new one. If you use MACHINE_START,
> > you cannot access the device tree data from the boot loader, which
> > means that none of the device drivers find their devices.
> 
> sorry i didn't get you.
> 
> DT is read to 0x3608000 by bootloader, and bootm has param "bootm
> 0x02008000 - 0x3608000" as:
> 
> bootcmd=mmc read 0 0x3608000 0x3780 0x80;mmc read 0 0x02008000 0x1800
> 0x1800;fdt addr 0x3608000;
> fdt resize;bootm 0x02008000 - 0x3608000
> 
> kernel has been always able to read DT data from bootloader.

Ah, right. I had to read the initialition code again, my incorrect
assumption was that we could not use a machine_desc that is
declared with MACHINE_START() together with a flattened device tree.

	Arnd


From lee.jones at linaro.org  Tue Aug 21 04:56:19 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 09:56:19 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120820175155.GH26991@opensource.wolfsonmicro.com>
References: <1344527635-6163-6-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
Message-ID: <20120821085618.GA26899@gmail.com>

> > If they don't have linear domains there's no point, if they support DT
> > then they can use it as it is.
> 
> All this stuff just works for any IRQ domain type, there's no
> requirement for a particular one.  It's not urgently exciting for legacy
> domains but it's not harmful either and pushes all the handling of this
> stuff out of the MFD core and into the irqdomain code which is
> definitely an abstraction win.

Wherever we do this from to be able to obtain the IRQ domain pointer, 
which is where I'm currently struggling. Our options are:

- Call into a helper function based in the IRQ controller from each 
child device. In turn the IRQ controller will be responsible for creating
the mapping necessary to obtain a virq. Using this method the child
device doesn't need to know if we're using an IRQ domain or not, or
whether we're using Device Tree or not. The drawback is that each child
device will be required to call the helper function prior to requesting
an IRQ. 

- If we're only talking MFD here, we can handle this stuff in the MFD
core, but we need more information. The IRQ domain subsystem only allows
domain look-up via a Device Tree node, so we need to get our hands on
the domain another way in the case of non-DT enabled devices. Either we
add another parameter to mfd_add_device(irq_domain, ...), or we
standardise the 'irq_domain' variable name and use:
        irq_domain = container_of(parent, struct irq_domain, irq_domain);

- I know that you have interest in pushing the functionality into the
IRQ domain subsystem, but I'm struggling to see how. It's calling into
the IRQ domain where we're seeing issues in the first place, specifically
irq_create_mapping(). How about if we passed 'irq_domain' as a parameter
when requesting the IRQ? That way we can pass the correct IRQ without
worry of conversion. If 'irq_domain' is !NULL the IRQ management subsystem
can do the necessary conversions. If 'irq_domain' is NULL it continues to
use the requested IRQ as a virq.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Tue Aug 21 05:02:13 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 Aug 2012 10:02:13 +0100
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <alpine.LFD.2.02.1208201443070.1754@xanadu.home>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
 <20120820165405.GU25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201356130.1754@xanadu.home>
 <20120820181007.GX25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201443070.1754@xanadu.home>
Message-ID: <20120821090213.GE28660@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 07:45:20PM +0100, Nicolas Pitre wrote:
> On Mon, 20 Aug 2012, Will Deacon wrote:
> > On Mon, Aug 20, 2012 at 07:04:01PM +0100, Nicolas Pitre wrote:
> > > Nah... the const is wrong.  The way you wrote it means that addr may 
> > > change but the pointed data is constant.  This is obviously wrong since 
> > > we expect the pointed location to change even from a read.
> > 
> > That's the prototype for the read accessors though -- a bunch of other
> > architectures define them that way (including asm-generic), so I wonder what
> > the reasoning behind that was?
> 
> I'm still asserting that they're wrong.

I did a bit of digging around and `const volatile void *' is apparently used
because a function with such a parameter type can be passed any old pointer
without warnings. Torvalds says something about them here:

  http://readlist.com/lists/vger.kernel.org/linux-kernel/14/72300.html

Personally, I too think that the const is misleading and who on Earth would
be passing in pointers to const for an I/O region? However, it's an argument
I'd rather avoid so, for the sake of consistency, I'll cast away the const in
the asm block.

Cheers,

Will


From will.deacon at arm.com  Tue Aug 21 04:58:19 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 Aug 2012 09:58:19 +0100
Subject: [PATCH v2 23/31] arm64: Debugging support
In-Reply-To: <201208202010.59985.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120820090754.GB25864@mudshark.cambridge.arm.com>
 <20120820092744.GD25864@mudshark.cambridge.arm.com>
 <201208202010.59985.arnd@arndb.de>
Message-ID: <20120821085819.GD28660@mudshark.cambridge.arm.com>

On Mon, Aug 20, 2012 at 09:10:59PM +0100, Arnd Bergmann wrote:
> On Monday 20 August 2012, Will Deacon wrote:
> > On Mon, Aug 20, 2012 at 10:07:54AM +0100, Will Deacon wrote:
> > > On Fri, Aug 17, 2012 at 08:06:07AM +0100, Arnd Bergmann wrote:
> > > > Sorry for the dumb question, but why do you even need PTRACE_GET_THREAD_AREA
> > > > for 64 bit tasks? I thought the thread pointer is a GPR, or is this just
> > > > for compat tasks?
> > > 
> > > The TLS is stored in a co-processor register which is read-only for
> > > userspace.
> > 
> > I should elaborate: the register is RW for AArch64 tasks, RO for aarch32
> > tasks (although that doesn't affect the need for the ptrace request).
> 
> So can't you just /add/ that register to the GPR regset?

We *could*, but it doesn't feel right to me. The TLS register:

	- Can only be manipulated by msr/mrs instructions
	- Is not part of the PCS
	- Is not accessed explicitly by user applications
	- Can not be written via ptrace

so I think it sticks out like a sore thumb if we bundle it up with the GPRs.

Will


From 21cnbao at gmail.com  Tue Aug 21 05:16:02 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 17:16:02 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <201208210757.32852.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
 <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
 <201208210757.32852.arnd@arndb.de>
Message-ID: <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>

Hi Arnd,

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Tuesday 21 August 2012, Barry Song wrote:
>> for the moment, that is needed just because the DEBUG UART base
>> address is difficult for different SoC. debug-macro.S is very early,
>> it depends on the SIRFSOC_UART1_PA_BASE.
>>
>>  /* UART-1: used as serial debug port */
>>  #ifdef CONFIG_ARCH_PRIMA2
>> #define SIRFSOC_UART1_PA_BASE          0xb0060000
>>  #elif defined(CONFIG_ARCH_MARCO)
>> #define SIRFSOC_UART1_PA_BASE          0xcc060000
>> #endif
>> otherwise, PRIMA2 and MARCO can co-exist.
>
> Ok, I see.
>
>> i think i can find some ways to set the rp dynamically according to chip type.
>>          .macro  addruart, rp, rv, tmp
>>          ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
>>          ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
>>          .endm
>
> The most common way to do this is to have multiple entries in
> arch/arm/Kconfig.debug in the "Kernel low-level debugging port"
> menu. For production kernels, you would just leave out DEBUG_LL
> while for debugging you have to pick one UART.

then i add these to Kconfig.debug as it is a common way

        config DEBUG_PRIMA2_UART1
                bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
                depends on ARCH_PRIMA2
                help
                  Say Y here if you want the debug print routines to direct
                  their output to UART1 serial port on SiRFprimaII devices.

        config DEBUG_MARCO_UART1
                bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
                depends on ARCH_MARCO
                help
                  Say Y here if you want the debug print routines to direct
                  their output to UART1 serial port on SiRFmarco devices.

and these in mach-prima2/include/mach/uart.h

  #ifdef CONFIG_DEBUG_PRIMA2_UART1
  #define SIRFSOC_UART1_PA_BASE          0xb0060000
  #elif defined(CONFIG_DEBUG_MARCO_UART1)
  #define SIRFSOC_UART1_PA_BASE          0xcc060000
  #endif

the above codes seem still ugly ?

>
>         Arnd

-barry


From balbi at ti.com  Tue Aug 21 05:15:42 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:42 +0300
Subject: [RFC/PATCH 00/13] OMAP UART patches
Message-ID: <1345540555-24359-1-git-send-email-balbi@ti.com>

Hi guys,

here's a series of cleanup patches to the OMAP serial
driver. A later series could be made re-implementing
DMA using the DMA Engine API. Note that for RX DMA
we could be using RX Timeout IRQ as a hint that we better
use PIO instead ;-)

All patches were tested on my pandaboard, but I'd really
like to receive Tested-by on other platforms.

After this goes in, I'll probably try to get UART wakeup
working again and only after that look at DMA.

cheers

Felipe Balbi (13):
  serial: omap: define and use to_uart_omap_port()
  serial: omap: always return IRQ_HANDLED
  serial: omap: define helpers for pdata function pointers
  serial: omap: don't access the platform_device
  serial: omap: drop DMA support
  serial: add OMAP-specific defines
  serial: omap: simplify IRQ handling
  serial: omap: refactor receive_chars() into rdi/rlsi handlers
  serial: omap: move THRE check to transmit_chars()
  serial: omap: stick to put_autosuspend
  serial: omap: set dev->drvdata before enabling pm_runtime
  serial: omap: drop unnecessary check from remove
  serial: omap: make sure to suspend device before remove

 arch/arm/mach-omap2/serial.c                  |  15 +-
 arch/arm/plat-omap/include/plat/omap-serial.h |  12 +-
 drivers/tty/serial/omap-serial.c              | 707 +++++++++-----------------
 include/linux/serial_reg.h                    |   4 +
 4 files changed, 250 insertions(+), 488 deletions(-)

-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:43 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:43 +0300
Subject: [RFC/PATCH 01/13] serial: omap: define and use to_uart_omap_port()
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-2-git-send-email-balbi@ti.com>

current code only works because struct uart_port
is the first member on the uart_omap_port structure.

If, for whatever reason, someone puts another
member as the first of the structure, that cast
won't work anymore. In order to be safe, let's use
a container_of() which, for now, gets optimized into
a cast anyway.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h |  2 ++
 drivers/tty/serial/omap-serial.c              | 36 +++++++++++++--------------
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725..f3b35d9 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -137,4 +137,6 @@ struct uart_omap_port {
 	struct work_struct	qos_work;
 };
 
+#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
+
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d3cda0c..5c0d0bc 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -141,7 +141,7 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 
 static void serial_omap_enable_ms(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
@@ -153,7 +153,7 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 
 	if (up->use_dma &&
@@ -186,7 +186,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	if (up->use_dma)
@@ -307,7 +307,7 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 
 static void serial_omap_start_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
@@ -449,7 +449,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 
 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
@@ -464,7 +464,7 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 
 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 	unsigned int ret = 0;
 
@@ -487,7 +487,7 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char mcr = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
@@ -511,7 +511,7 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
@@ -528,7 +528,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 
 static int serial_omap_startup(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	int retval;
 
@@ -606,7 +606,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 static void serial_omap_shutdown(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
@@ -721,7 +721,7 @@ static void
 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 			struct ktermios *old)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char cval = 0;
 	unsigned char efr = 0;
 	unsigned long flags = 0;
@@ -932,7 +932,7 @@ static void
 serial_omap_pm(struct uart_port *port, unsigned int state,
 	       unsigned int oldstate)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char efr;
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
@@ -971,7 +971,7 @@ static int serial_omap_request_port(struct uart_port *port)
 
 static void serial_omap_config_port(struct uart_port *port, int flags)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 							up->port.line);
@@ -989,7 +989,7 @@ serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 static const char *
 serial_omap_type(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 	return up->name;
@@ -1032,7 +1032,7 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
 
 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	wait_for_xmitr(up);
@@ -1042,7 +1042,7 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 
 static int serial_omap_poll_get_char(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
 	pm_runtime_get_sync(&up->pdev->dev);
@@ -1065,7 +1065,7 @@ static struct uart_driver serial_omap_reg;
 
 static void serial_omap_console_putchar(struct uart_port *port, int ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
@@ -1341,7 +1341,7 @@ static void serial_omap_continue_tx(struct uart_omap_port *up)
 
 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)data;
+	struct uart_omap_port *up = data;
 	struct circ_buf *xmit = &up->port.state->xmit;
 
 	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:44 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:44 +0300
Subject: [RFC/PATCH 02/13] serial: omap: always return IRQ_HANDLED
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-3-git-send-email-balbi@ti.com>

Even if we enter our IRQ handler just to notice
that the our device didn't generate the IRQ,
that still means "handling" and IRQ, so let's
return IRQ_HANDLED.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 5c0d0bc..b4b95fc 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -417,7 +417,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	if (iir & UART_IIR_NO_INT) {
 		pm_runtime_mark_last_busy(&up->pdev->dev);
 		pm_runtime_put_autosuspend(&up->pdev->dev);
-		return IRQ_NONE;
+		return IRQ_HANDLED;
 	}
 
 	spin_lock_irqsave(&up->port.lock, flags);
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:45 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:45 +0300
Subject: [RFC/PATCH 03/13] serial: omap: define helpers for pdata function
 pointers
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-4-git-send-email-balbi@ti.com>

this patch is in preparation to a few other changes
which will align on the prototype for function
pointers passed through pdata.

It also helps cleaning up the driver a little by
agregating checks for pdata in a single location.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 66 ++++++++++++++++++++++++++++------------
 1 file changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index b4b95fc..c3e6fa0 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -101,6 +101,40 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 	serial_out(up, UART_FCR, 0);
 }
 
+static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (!pdata->get_context_loss_count)
+		return 0;
+
+	return pdata->get_context_loss_count(&up->pdev->dev);
+}
+
+static void serial_omap_set_forceidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_forceidle)
+		pdata->set_forceidle(up->pdev);
+}
+
+static void serial_omap_set_noidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_noidle)
+		pdata->set_noidle(up->pdev);
+}
+
+static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->enable_wakeup)
+		pdata->enable_wakeup(up->pdev, enable);
+}
+
 /*
  * serial_omap_get_divisor - calculate divisor value
  * @port: uart port info
@@ -177,8 +211,8 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata && pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+	if (!up->use_dma && pdata)
+		serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(&up->pdev->dev);
 	pm_runtime_put_autosuspend(&up->pdev->dev);
@@ -308,7 +342,6 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
 	int ret = 0;
@@ -316,8 +349,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	if (!up->use_dma) {
 		pm_runtime_get_sync(&up->pdev->dev);
 		serial_omap_enable_ier_thri(up);
-		if (pdata && pdata->set_noidle)
-			pdata->set_noidle(up->pdev);
+		serial_omap_set_noidle(up);
 		pm_runtime_mark_last_busy(&up->pdev->dev);
 		pm_runtime_put_autosuspend(&up->pdev->dev);
 		return;
@@ -1648,28 +1680,26 @@ static int serial_omap_runtime_suspend(struct device *dev)
 	if (!up)
 		return -EINVAL;
 
-	if (!pdata || !pdata->enable_wakeup)
+	if (!pdata)
 		return 0;
 
-	if (pdata->get_context_loss_count)
-		up->context_loss_cnt = pdata->get_context_loss_count(dev);
+	up->context_loss_cnt = serial_omap_get_context_loss_count(up);
 
 	if (device_may_wakeup(dev)) {
 		if (!up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, true);
+			serial_omap_enable_wakeup(up, true);
 			up->wakeups_enabled = true;
 		}
 	} else {
 		if (up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, false);
+			serial_omap_enable_wakeup(up, false);
 			up->wakeups_enabled = false;
 		}
 	}
 
 	/* Errata i291 */
-	if (up->use_dma && pdata->set_forceidle &&
-			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		pdata->set_forceidle(up->pdev);
+	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
+		serial_omap_set_forceidle(up);
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
@@ -1683,17 +1713,15 @@ static int serial_omap_runtime_resume(struct device *dev)
 	struct omap_uart_port_info *pdata = dev->platform_data;
 
 	if (up && pdata) {
-		if (pdata->get_context_loss_count) {
-			u32 loss_cnt = pdata->get_context_loss_count(dev);
+			u32 loss_cnt = serial_omap_get_context_loss_count(up);
 
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
-		}
 
 		/* Errata i291 */
-		if (up->use_dma && pdata->set_noidle &&
-				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-			pdata->set_noidle(up->pdev);
+		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
+				up->use_dma)
+			serial_omap_set_noidle(up);
 
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:48 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:48 +0300
Subject: [RFC/PATCH 06/13] serial: add OMAP-specific defines
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-7-git-send-email-balbi@ti.com>

OMAP has some extra Interrupt types which can
be really useful for SW. Let's define them
so we can later use those in OMAP's serial driver.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 include/linux/serial_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 8ce70d7..5ed325e 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -40,6 +40,10 @@
 
 #define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
 
+#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
+
 #define UART_FCR	2	/* Out: FIFO Control Register */
 #define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
 #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:49 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:49 +0300
Subject: [RFC/PATCH 07/13] serial: omap: simplify IRQ handling
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-8-git-send-email-balbi@ti.com>

quite a few changes here, though they are
pretty obvious. In summary we're making sure
to detect which interrupt type we need to
handle before calling the underlying interrupt
handling procedure.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 47 ++++++++++++++++++++++++++++++----------
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 4d74a9b..1ca08b8 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -350,32 +350,55 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
 	unsigned int iir, lsr;
+	unsigned int type;
 	unsigned long flags;
 
+	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
-	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return IRQ_HANDLED;
-	}
+again:
+	if (iir & UART_IIR_NO_INT)
+		goto out;
 
-	spin_lock_irqsave(&up->port.lock, flags);
 	lsr = serial_in(up, UART_LSR);
-	if (iir & UART_IIR_RLSI) {
+
+	/* extract IRQ type from IIR register */
+	type = iir & 0x3e;
+
+	switch (type) {
+	case UART_IIR_MSI:
+		check_modem_status(up);
+		break;
+	case UART_IIR_THRI:
+		if (lsr & UART_LSR_THRE)
+			transmit_chars(up);
+		break;
+	case UART_IIR_RDI:
 		if (lsr & UART_LSR_DR)
 			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RLSI:
+		if (lsr & UART_LSR_BRK_ERROR_BITS)
+			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RX_TIMEOUT:
+		receive_chars(up, &lsr);
+		break;
+	case UART_IIR_CTS_RTS_DSR:
+		iir = serial_in(up, UART_IIR);
+		goto again;
+	case UART_IIR_XOFF:
+		/* FALLTHROUGH */
+	default:
+		break;
 	}
 
-	check_modem_status(up);
-	if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
-		transmit_chars(up);
-
+out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-
 	up->port_activity = jiffies;
+
 	return IRQ_HANDLED;
 }
 
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:46 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:46 +0300
Subject: [RFC/PATCH 04/13] serial: omap: don't access the platform_device
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-5-git-send-email-balbi@ti.com>

The driver doesn't need to know about its platform_device.

Everything the driver needs can be done through the
struct device pointer. In case we need to use the
OMAP-specific PM function pointers, those can make
sure to find the device's platform_device pointer
so they can find the struct omap_device through
pdev->archdata field.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/mach-omap2/serial.c                  |  15 ++--
 arch/arm/plat-omap/include/plat/omap-serial.h |  10 +--
 drivers/tty/serial/omap-serial.c              | 124 +++++++++++++-------------
 3 files changed, 76 insertions(+), 73 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c7..8f07841 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
 };
 
 #ifdef CONFIG_PM
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	if (!od)
@@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
  * in Smartidle Mode When Configured for DMA Operations.
  * WA: configure uart in force idle mode.
  */
-static void omap_uart_set_noidle(struct platform_device *pdev)
+static void omap_uart_set_noidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
 
-static void omap_uart_set_smartidle(struct platform_device *pdev)
+static void omap_uart_set_smartidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 	u8 idlemode;
 
@@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev)
 }
 
 #else
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct platform_device *pdev) {}
-static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+static void omap_uart_set_noidle(struct device *dev) {}
+static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index f3b35d9..743ac80 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,7 +18,7 @@
 #define __OMAP_SERIAL_H__
 
 #include <linux/serial_core.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
 #include <linux/pm_qos.h>
 
 #include <plat/mux.h>
@@ -71,9 +71,9 @@ struct omap_uart_port_info {
 	unsigned int		dma_rx_poll_rate;
 
 	int (*get_context_loss_count)(struct device *);
-	void (*set_forceidle)(struct platform_device *);
-	void (*set_noidle)(struct platform_device *);
-	void (*enable_wakeup)(struct platform_device *, bool);
+	void (*set_forceidle)(struct device *);
+	void (*set_noidle)(struct device *);
+	void (*enable_wakeup)(struct device *, bool);
 };
 
 struct uart_omap_dma {
@@ -105,7 +105,7 @@ struct uart_omap_dma {
 struct uart_omap_port {
 	struct uart_port	port;
 	struct uart_omap_dma	uart_dma;
-	struct platform_device	*pdev;
+	struct device		*dev;
 
 	unsigned char		ier;
 	unsigned char		lcr;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index c3e6fa0..fb81366 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -103,36 +103,36 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 
 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (!pdata->get_context_loss_count)
 		return 0;
 
-	return pdata->get_context_loss_count(&up->pdev->dev);
+	return pdata->get_context_loss_count(up->dev);
 }
 
 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+		pdata->set_forceidle(up->dev);
 }
 
 static void serial_omap_set_noidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_noidle)
-		pdata->set_noidle(up->pdev);
+		pdata->set_noidle(up->dev);
 }
 
 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->enable_wakeup)
-		pdata->enable_wakeup(up->pdev, enable);
+		pdata->enable_wakeup(up->dev, enable);
 }
 
 /*
@@ -168,8 +168,8 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 		omap_free_dma(up->uart_dma.rx_dma_channel);
 		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
 		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 }
 
@@ -179,16 +179,16 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (up->use_dma &&
 		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
@@ -201,11 +201,11 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		omap_stop_dma(up->uart_dma.tx_dma_channel);
 		omap_free_dma(up->uart_dma.tx_dma_channel);
 		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
 		up->ier &= ~UART_IER_THRI;
 		serial_out(up, UART_IER, up->ier);
@@ -214,22 +214,22 @@ static void serial_omap_stop_tx(struct uart_port *port)
 	if (!up->use_dma && pdata)
 		serial_omap_set_forceidle(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->use_dma)
 		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static inline void receive_chars(struct uart_omap_port *up,
@@ -347,11 +347,11 @@ static void serial_omap_start_tx(struct uart_port *port)
 	int ret = 0;
 
 	if (!up->use_dma) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		serial_omap_enable_ier_thri(up);
 		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return;
 	}
 
@@ -361,7 +361,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	xmit = &up->port.state->xmit;
 
 	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
 				"UART Tx DMA",
 				(void *)uart_tx_dma_callback, up,
@@ -444,11 +444,11 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	unsigned int iir, lsr;
 	unsigned long flags;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
 	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return IRQ_HANDLED;
 	}
 
@@ -472,8 +472,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 		transmit_chars(up);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	up->port_activity = jiffies;
 	return IRQ_HANDLED;
@@ -485,12 +485,12 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return ret;
 }
 
@@ -500,9 +500,9 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 	unsigned int status;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -534,11 +534,11 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	if (mctrl & TIOCM_LOOP)
 		mcr |= UART_MCR_LOOP;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -547,7 +547,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 	if (break_state == -1)
 		up->lcr |= UART_LCR_SBC;
@@ -555,7 +555,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -574,7 +574,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Clear the FIFO buffers and disable them.
 	 * (they will be reenabled in set_termios())
@@ -630,8 +630,8 @@ static int serial_omap_startup(struct uart_port *port)
 	/* Enable module level wake up */
 	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
 	return 0;
 }
@@ -643,7 +643,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Disable interrupts from this port
 	 */
@@ -678,7 +678,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 		up->uart_dma.rx_buf = NULL;
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -807,7 +807,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	 * Ok, we're now changing the port state. Do it with
 	 * interrupts disabled.
 	 */
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 
 	/*
@@ -956,7 +956,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -969,7 +969,7 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 	efr = serial_in(up, UART_EFR);
 	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
@@ -980,14 +980,14 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 	serial_out(up, UART_EFR, efr);
 	serial_out(up, UART_LCR, 0);
 
-	if (!device_may_wakeup(&up->pdev->dev)) {
+	if (!device_may_wakeup(up->dev)) {
 		if (!state)
-			pm_runtime_forbid(&up->pdev->dev);
+			pm_runtime_forbid(up->dev);
 		else
-			pm_runtime_allow(&up->pdev->dev);
+			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -1066,10 +1066,10 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -1077,13 +1077,13 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = serial_in(up, UART_LSR);
 	if (!(status & UART_LSR_DR))
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return status;
 }
 
@@ -1112,7 +1112,7 @@ serial_omap_console_write(struct console *co, const char *s,
 	unsigned int ier;
 	int locked = 1;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 
 	local_irq_save(flags);
 	if (up->port.sysrq)
@@ -1146,8 +1146,8 @@ serial_omap_console_write(struct console *co, const char *s,
 	if (up->msr_saved_flags)
 		check_modem_status(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	if (locked)
 		spin_unlock(&up->port.lock);
 	local_irq_restore(flags);
@@ -1309,7 +1309,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
 	int ret = 0;
 
 	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
 				"UART Rx DMA",
 				(void *)uart_rx_dma_callback, up,
@@ -1421,7 +1421,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 		break;
 	default:
-		dev_warn(&up->pdev->dev,
+		dev_warn(up->dev,
 			"Unknown %s revision, defaulting to highest\n",
 			up->name);
 		/* highest possible revision */
@@ -1502,7 +1502,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (!up)
 		return -ENOMEM;
 
-	up->pdev = pdev;
+	up->dev = &pdev->dev;
 	up->port.dev = &pdev->dev;
 	up->port.type = PORT_OMAP;
 	up->port.iotype = UPIO_MEM;
@@ -1599,7 +1599,7 @@ static int serial_omap_remove(struct platform_device *dev)
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
 	if (up) {
-		pm_runtime_disable(&up->pdev->dev);
+		pm_runtime_disable(up->dev);
 		uart_remove_one_port(&serial_omap_reg, &up->port);
 		pm_qos_remove_request(&up->pm_qos_request);
 	}
@@ -1634,7 +1634,7 @@ static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
 		timeout--;
 		if (!timeout) {
 			/* Should *never* happen. we warn and carry on */
-			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
+			dev_crit(up->dev, "Errata i202: timedout %x\n",
 						serial_in(up, UART_LSR));
 			break;
 		}
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:47 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:47 +0300
Subject: [RFC/PATCH 05/13] serial: omap: drop DMA support
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-6-git-send-email-balbi@ti.com>

The current support is known to be broken and
a later patch will come re-adding it using
dma engine API.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 330 ++-------------------------------------
 1 file changed, 12 insertions(+), 318 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index fb81366..4d74a9b 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -33,14 +33,12 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/io.h>
-#include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/serial_core.h>
 #include <linux/irq.h>
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 
-#include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/omap-serial.h>
 
@@ -74,9 +72,6 @@
 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 
 /* Forward declaration of functions */
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
-static void serial_omap_rxdma_poll(unsigned long uart_no);
-static int serial_omap_start_rxdma(struct uart_omap_port *up);
 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 
 static struct workqueue_struct *serial_omap_uart_wq;
@@ -160,19 +155,6 @@ serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 	return port->uartclk/(baud * divisor);
 }
 
-static void serial_omap_stop_rxdma(struct uart_omap_port *up)
-{
-	if (up->uart_dma.rx_dma_used) {
-		del_timer(&up->uart_dma.rx_timer);
-		omap_stop_dma(up->uart_dma.rx_dma_channel);
-		omap_free_dma(up->uart_dma.rx_dma_channel);
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
-}
-
 static void serial_omap_enable_ms(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
@@ -188,22 +170,6 @@ static void serial_omap_enable_ms(struct uart_port *port)
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->dev->platform_data;
-
-	if (up->use_dma &&
-		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
-		/*
-		 * Check if dma is still active. If yes do nothing,
-		 * return. Else stop dma
-		 */
-		if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
-			return;
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		omap_free_dma(up->uart_dma.tx_dma_channel);
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
 
 	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
@@ -211,8 +177,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata)
-		serial_omap_set_forceidle(up);
+	serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
@@ -223,8 +188,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(up->dev);
-	if (up->use_dma)
-		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
@@ -342,67 +305,12 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct circ_buf *xmit;
-	unsigned int start;
-	int ret = 0;
-
-	if (!up->use_dma) {
-		pm_runtime_get_sync(up->dev);
-		serial_omap_enable_ier_thri(up);
-		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return;
-	}
-
-	if (up->uart_dma.tx_dma_used)
-		return;
-
-	xmit = &up->port.state->xmit;
-
-	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
-				"UART Tx DMA",
-				(void *)uart_tx_dma_callback, up,
-				&(up->uart_dma.tx_dma_channel));
 
-		if (ret < 0) {
-			serial_omap_enable_ier_thri(up);
-			return;
-		}
-	}
-	spin_lock(&(up->uart_dma.tx_lock));
-	up->uart_dma.tx_dma_used = true;
-	spin_unlock(&(up->uart_dma.tx_lock));
-
-	start = up->uart_dma.tx_buf_dma_phys +
-				(xmit->tail & (UART_XMIT_SIZE - 1));
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys +
-			UART_XMIT_SIZE) - start;
-
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
+	pm_runtime_get_sync(up->dev);
+	serial_omap_enable_ier_thri(up);
+	serial_omap_set_noidle(up);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static unsigned int check_modem_status(struct uart_omap_port *up)
@@ -455,16 +363,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	spin_lock_irqsave(&up->port.lock, flags);
 	lsr = serial_in(up, UART_LSR);
 	if (iir & UART_IIR_RLSI) {
-		if (!up->use_dma) {
-			if (lsr & UART_LSR_DR)
-				receive_chars(up, &lsr);
-		} else {
-			up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-			if ((serial_omap_start_rxdma(up) != 0) &&
-					(lsr & UART_LSR_DR))
-				receive_chars(up, &lsr);
-		}
+		if (lsr & UART_LSR_DR)
+			receive_chars(up, &lsr);
 	}
 
 	check_modem_status(up);
@@ -605,20 +505,6 @@ static int serial_omap_startup(struct uart_port *port)
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
 	up->msr_saved_flags = 0;
-	if (up->use_dma) {
-		free_page((unsigned long)up->port.state->xmit.buf);
-		up->port.state->xmit.buf = dma_alloc_coherent(NULL,
-			UART_XMIT_SIZE,
-			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
-			0);
-		init_timer(&(up->uart_dma.rx_timer));
-		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
-		up->uart_dma.rx_timer.data = up->port.line;
-		/* Currently the buffer size is 4KB. Can increase it */
-		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
-			up->uart_dma.rx_buf_size,
-			(dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
-	}
 	/*
 	 * Finally, enable interrupts. Note: Modem status interrupts
 	 * are set via set_termios(), which will be occurring imminently
@@ -666,17 +552,6 @@ static void serial_omap_shutdown(struct uart_port *port)
 	 */
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
-	if (up->use_dma) {
-		dma_free_coherent(up->port.dev,
-			UART_XMIT_SIZE,	up->port.state->xmit.buf,
-			up->uart_dma.tx_buf_dma_phys);
-		up->port.state->xmit.buf = NULL;
-		serial_omap_stop_rx(port);
-		dma_free_coherent(up->port.dev,
-			up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
-			up->uart_dma.rx_buf_dma_phys);
-		up->uart_dma.rx_buf = NULL;
-	}
 
 	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
@@ -800,8 +675,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 			UART_FCR_ENABLE_FIFO;
-	if (up->use_dma)
-		up->fcr |= UART_FCR_DMA_SELECT;
 
 	/*
 	 * Ok, we're now changing the port state. Do it with
@@ -877,14 +750,9 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 
-	if (up->use_dma) {
-		serial_out(up, UART_TI752_TLR, 0);
-		up->scr |= UART_FCR_TRIGGER_4;
-	} else {
-		/* Set receive FIFO threshold to 1 byte */
-		up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
-		up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
-	}
+	/* Set receive FIFO threshold to 1 byte */
+	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
+	up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
 
 	serial_out(up, UART_FCR, up->fcr);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
@@ -1253,149 +1121,6 @@ static int serial_omap_resume(struct device *dev)
 }
 #endif
 
-static void serial_omap_rxdma_poll(unsigned long uart_no)
-{
-	struct uart_omap_port *up = ui[uart_no];
-	unsigned int curr_dma_pos, curr_transmitted_size;
-	int ret = 0;
-
-	curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
-	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
-			     (curr_dma_pos == 0)) {
-		if (jiffies_to_msecs(jiffies - up->port_activity) <
-						up->uart_dma.rx_timeout) {
-			mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-		} else {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-		return;
-	}
-
-	curr_transmitted_size = curr_dma_pos -
-					up->uart_dma.prev_rx_dma_pos;
-	up->port.icount.rx += curr_transmitted_size;
-	tty_insert_flip_string(up->port.state->port.tty,
-			up->uart_dma.rx_buf +
-			(up->uart_dma.prev_rx_dma_pos -
-			up->uart_dma.rx_buf_dma_phys),
-			curr_transmitted_size);
-	tty_flip_buffer_push(up->port.state->port.tty);
-	up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
-	if (up->uart_dma.rx_buf_size +
-			up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
-		ret = serial_omap_start_rxdma(up);
-		if (ret < 0) {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-	} else  {
-		mod_timer(&up->uart_dma.rx_timer, jiffies +
-			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	}
-	up->port_activity = jiffies;
-}
-
-static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	return;
-}
-
-static int serial_omap_start_rxdma(struct uart_omap_port *up)
-{
-	int ret = 0;
-
-	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
-				"UART Rx DMA",
-				(void *)uart_rx_dma_callback, up,
-				&(up->uart_dma.rx_dma_channel));
-		if (ret < 0)
-			return ret;
-
-		omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-		omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC,
-				up->uart_dma.rx_buf_dma_phys, 0, 0);
-		omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.rx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_rx, 0);
-	}
-	up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.rx_dma_channel);
-	mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	up->uart_dma.rx_dma_used = true;
-	return ret;
-}
-
-static void serial_omap_continue_tx(struct uart_omap_port *up)
-{
-	struct circ_buf *xmit = &up->port.state->xmit;
-	unsigned int start = up->uart_dma.tx_buf_dma_phys
-			+ (xmit->tail & (UART_XMIT_SIZE - 1));
-
-	if (uart_circ_empty(xmit))
-		return;
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
-}
-
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	struct uart_omap_port *up = data;
-	struct circ_buf *xmit = &up->port.state->xmit;
-
-	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-			(UART_XMIT_SIZE - 1);
-	up->port.icount.tx += up->uart_dma.tx_buf_size;
-
-	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-		uart_write_wakeup(&up->port);
-
-	if (uart_circ_empty(xmit)) {
-		spin_lock(&(up->uart_dma.tx_lock));
-		serial_omap_stop_tx(&up->port);
-		up->uart_dma.tx_dma_used = false;
-		spin_unlock(&(up->uart_dma.tx_lock));
-	} else {
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		serial_omap_continue_tx(up);
-	}
-	up->port_activity = jiffies;
-	return;
-}
-
 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 {
 	u32 mvr, scheme;
@@ -1465,7 +1190,7 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 static int serial_omap_probe(struct platform_device *pdev)
 {
 	struct uart_omap_port	*up;
-	struct resource		*mem, *irq, *dma_tx, *dma_rx;
+	struct resource		*mem, *irq;
 	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
 	int ret = -ENOSPC;
 
@@ -1490,14 +1215,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-	if (!dma_rx)
-		return -ENXIO;
-
-	dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-	if (!dma_tx)
-		return -ENXIO;
-
 	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
 	if (!up)
 		return -ENOMEM;
@@ -1541,20 +1258,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		dev_warn(&pdev->dev, "No clock speed specified: using default:"
 						"%d\n", DEFAULT_CLK_SPEED);
 	}
-	up->uart_dma.uart_base = mem->start;
-
-	if (omap_up_info->dma_enabled) {
-		up->uart_dma.uart_dma_tx = dma_tx->start;
-		up->uart_dma.uart_dma_rx = dma_rx->start;
-		up->use_dma = 1;
-		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
-		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
-		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
-		spin_lock_init(&(up->uart_dma.tx_lock));
-		spin_lock_init(&(up->uart_dma.rx_lock));
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-	}
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
@@ -1697,10 +1400,6 @@ static int serial_omap_runtime_suspend(struct device *dev)
 		}
 	}
 
-	/* Errata i291 */
-	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		serial_omap_set_forceidle(up);
-
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
 
@@ -1718,11 +1417,6 @@ static int serial_omap_runtime_resume(struct device *dev)
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
 
-		/* Errata i291 */
-		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
-				up->use_dma)
-			serial_omap_set_noidle(up);
-
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
 	}
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:50 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:50 +0300
Subject: [RFC/PATCH 08/13] serial: omap: refactor receive_chars() into
 rdi/rlsi handlers
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-9-git-send-email-balbi@ti.com>

receive_chars() was getting too big and too difficult
to follow. By splitting it into separate RDI and RSLI
handlers, we have smaller functions which are easy
to understand and only touch the pieces which they need
to touch.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 203 +++++++++++++++++++--------------------
 1 file changed, 100 insertions(+), 103 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 1ca08b8..74a4f0a 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,74 +195,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static inline void receive_chars(struct uart_omap_port *up,
-		unsigned int *status)
-{
-	struct tty_struct *tty = up->port.state->port.tty;
-	unsigned int flag, lsr = *status;
-	unsigned char ch = 0;
-	int max_count = 256;
-
-	do {
-		if (likely(lsr & UART_LSR_DR))
-			ch = serial_in(up, UART_RX);
-		flag = TTY_NORMAL;
-		up->port.icount.rx++;
-
-		if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
-			/*
-			 * For statistics only
-			 */
-			if (lsr & UART_LSR_BI) {
-				lsr &= ~(UART_LSR_FE | UART_LSR_PE);
-				up->port.icount.brk++;
-				/*
-				 * We do the SysRQ and SAK checking
-				 * here because otherwise the break
-				 * may get masked by ignore_status_mask
-				 * or read_status_mask.
-				 */
-				if (uart_handle_break(&up->port))
-					goto ignore_char;
-			} else if (lsr & UART_LSR_PE) {
-				up->port.icount.parity++;
-			} else if (lsr & UART_LSR_FE) {
-				up->port.icount.frame++;
-			}
-
-			if (lsr & UART_LSR_OE)
-				up->port.icount.overrun++;
-
-			/*
-			 * Mask off conditions which should be ignored.
-			 */
-			lsr &= up->port.read_status_mask;
-
-#ifdef CONFIG_SERIAL_OMAP_CONSOLE
-			if (up->port.line == up->port.cons->index) {
-				/* Recover the break flag from console xmit */
-				lsr |= up->lsr_break_flag;
-			}
-#endif
-			if (lsr & UART_LSR_BI)
-				flag = TTY_BREAK;
-			else if (lsr & UART_LSR_PE)
-				flag = TTY_PARITY;
-			else if (lsr & UART_LSR_FE)
-				flag = TTY_FRAME;
-		}
-
-		if (uart_handle_sysrq_char(&up->port, ch))
-			goto ignore_char;
-		uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
-ignore_char:
-		lsr = serial_in(up, UART_LSR);
-	} while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
-	spin_unlock(&up->port.lock);
-	tty_flip_buffer_push(tty);
-	spin_lock(&up->port.lock);
-}
-
 static void transmit_chars(struct uart_omap_port *up)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
@@ -341,6 +273,68 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 	return status;
 }
 
+static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned int flag;
+
+	up->port.icount.rx++;
+	flag = TTY_NORMAL;
+
+	if (lsr & UART_LSR_BI) {
+		flag = TTY_BREAK;
+		lsr &= ~(UART_LSR_FE | UART_LSR_PE);
+		up->port.icount.brk++;
+		/*
+		 * We do the SysRQ and SAK checking
+		 * here because otherwise the break
+		 * may get masked by ignore_status_mask
+		 * or read_status_mask.
+		 */
+		if (uart_handle_break(&up->port))
+			return;
+
+	}
+
+	if (lsr & UART_LSR_PE) {
+		flag = TTY_PARITY;
+		up->port.icount.parity++;
+	}
+
+	if (lsr & UART_LSR_FE) {
+		flag = TTY_FRAME;
+		up->port.icount.frame++;
+	}
+
+	if (lsr & UART_LSR_OE)
+		up->port.icount.overrun++;
+
+#ifdef CONFIG_SERIAL_OMAP_CONSOLE
+	if (up->port.line == up->port.cons->index) {
+		/* Recover the break flag from console xmit */
+		lsr |= up->lsr_break_flag;
+	}
+#endif
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
+}
+
+static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned char ch = 0;
+	unsigned int flag;
+
+	if (!(lsr & UART_LSR_DR))
+		return;
+
+	ch = serial_in(up, UART_RX);
+	flag = TTY_NORMAL;
+	up->port.icount.rx++;
+
+	if (uart_handle_sysrq_char(&up->port, ch))
+		return;
+
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
+}
+
 /**
  * serial_omap_irq() - This handles the interrupt from one port
  * @irq: uart port irq number
@@ -349,52 +343,55 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
+	struct tty_struct *tty = up->port.state->port.tty;
 	unsigned int iir, lsr;
 	unsigned int type;
 	unsigned long flags;
+	int max_count = 256;
 
 	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
-	iir = serial_in(up, UART_IIR);
-again:
-	if (iir & UART_IIR_NO_INT)
-		goto out;
 
-	lsr = serial_in(up, UART_LSR);
+	do {
+		iir = serial_in(up, UART_IIR);
+		if (iir & UART_IIR_NO_INT)
+			break;
 
-	/* extract IRQ type from IIR register */
-	type = iir & 0x3e;
+		lsr = serial_in(up, UART_LSR);
 
-	switch (type) {
-	case UART_IIR_MSI:
-		check_modem_status(up);
-		break;
-	case UART_IIR_THRI:
-		if (lsr & UART_LSR_THRE)
-			transmit_chars(up);
-		break;
-	case UART_IIR_RDI:
-		if (lsr & UART_LSR_DR)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RLSI:
-		if (lsr & UART_LSR_BRK_ERROR_BITS)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RX_TIMEOUT:
-		receive_chars(up, &lsr);
-		break;
-	case UART_IIR_CTS_RTS_DSR:
-		iir = serial_in(up, UART_IIR);
-		goto again;
-	case UART_IIR_XOFF:
-		/* FALLTHROUGH */
-	default:
-		break;
-	}
+		/* extract IRQ type from IIR register */
+		type = iir & 0x3e;
+
+		switch (type) {
+		case UART_IIR_MSI:
+			check_modem_status(up);
+			break;
+		case UART_IIR_THRI:
+			if (lsr & UART_LSR_THRE)
+				transmit_chars(up);
+			break;
+		case UART_IIR_RX_TIMEOUT:
+			/* FALLTHROUGH */
+		case UART_IIR_RDI:
+			serial_omap_rdi(up, lsr);
+			break;
+		case UART_IIR_RLSI:
+			serial_omap_rlsi(up, lsr);
+			break;
+		case UART_IIR_CTS_RTS_DSR:
+			/* simply try again */
+			break;
+		case UART_IIR_XOFF:
+			/* FALLTHROUGH */
+		default:
+			break;
+		}
+	} while (!(iir & UART_IIR_NO_INT) && max_count--);
 
-out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
+
+	tty_flip_buffer_push(tty);
+
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:51 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:51 +0300
Subject: [RFC/PATCH 09/13] serial: omap: move THRE check to transmit_chars()
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-10-git-send-email-balbi@ti.com>

since all other IRQ types now do all necessary
checks inside their handlers, transmit_chars()
was the only one left expecting serial_omap_irq()
to check THRE for it. We can move THRE check to
transmit_chars() in order to make serial_omap_irq()
more uniform.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 74a4f0a..6ea24c5 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,11 +195,14 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static void transmit_chars(struct uart_omap_port *up)
+static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
 	int count;
 
+	if (!(lsr & UART_LSR_THRE))
+		return;
+
 	if (up->port.x_char) {
 		serial_out(up, UART_TX, up->port.x_char);
 		up->port.icount.tx++;
@@ -367,8 +370,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 			check_modem_status(up);
 			break;
 		case UART_IIR_THRI:
-			if (lsr & UART_LSR_THRE)
-				transmit_chars(up);
+			transmit_chars(up, lsr);
 			break;
 		case UART_IIR_RX_TIMEOUT:
 			/* FALLTHROUGH */
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:52 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:52 +0300
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-11-git-send-email-balbi@ti.com>

Everytime we're done using our TTY, we want
the pm timer to be reinitilized. By sticking
to pm_runtime_pm_autosuspend() we make sure
that this will always be the case.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6ea24c5..458d77c 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
 	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
@@ -412,7 +413,8 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return ret;
 }
 
@@ -424,7 +426,8 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -460,7 +463,8 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -477,7 +481,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -575,7 +580,8 @@ static void serial_omap_shutdown(struct uart_port *port)
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -846,7 +852,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -877,7 +884,8 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -959,7 +967,8 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -973,7 +982,8 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return status;
 }
 
@@ -1305,7 +1315,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (ret != 0)
 		goto err_add_port;
 
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	platform_set_drvdata(pdev, up);
 	return 0;
 
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:53 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:53 +0300
Subject: [RFC/PATCH 11/13] serial: omap: set dev->drvdata before enabling
 pm_runtime
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-12-git-send-email-balbi@ti.com>

by the time we call our first pm_runtme_get_sync()
after enable pm_runtime, our resume method might
be called. To avoid problems, we must make sure
that our dev->drvdata is set correctly before
our resume method gets called.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 458d77c..ba9cdf1 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1298,6 +1298,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
 
+	platform_set_drvdata(pdev, up);
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
 			omap_up_info->autosuspend_timeout);
@@ -1317,7 +1318,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-	platform_set_drvdata(pdev, up);
 	return 0;
 
 err_add_port:
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 05:15:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:54 +0300
Subject: [RFC/PATCH 12/13] serial: omap: drop unnecessary check from remove
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-13-git-send-email-balbi@ti.com>

if platform_get_drvdata() returns NULL, that's
quite a nasty bug on the driver which we want to
catch ASAP. Otherwise, that check is hugely
unneeded.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index ba9cdf1..25d2055 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1334,13 +1334,10 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
-	if (up) {
-		pm_runtime_disable(up->dev);
-		uart_remove_one_port(&serial_omap_reg, &up->port);
-		pm_qos_remove_request(&up->pm_qos_request);
-	}
+	pm_runtime_disable(up->dev);
+	uart_remove_one_port(&serial_omap_reg, &up->port);
+	pm_qos_remove_request(&up->pm_qos_request);
 
-	platform_set_drvdata(dev, NULL);
 	return 0;
 }
 
-- 
1.7.12.rc3



From arnd at arndb.de  Tue Aug 21 05:20:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 09:20:52 +0000
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210757.32852.arnd@arndb.de>
 <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
Message-ID: <201208210920.52816.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> then i add these to Kconfig.debug as it is a common way
> 
>         config DEBUG_PRIMA2_UART1
>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
>                 depends on ARCH_PRIMA2
>                 help
>                   Say Y here if you want the debug print routines to direct
>                   their output to UART1 serial port on SiRFprimaII devices.
> 
>         config DEBUG_MARCO_UART1
>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
>                 depends on ARCH_MARCO
>                 help
>                   Say Y here if you want the debug print routines to direct
>                   their output to UART1 serial port on SiRFmarco devices.
> 
> and these in mach-prima2/include/mach/uart.h
> 
>   #ifdef CONFIG_DEBUG_PRIMA2_UART1
>   #define SIRFSOC_UART1_PA_BASE          0xb0060000
>   #elif defined(CONFIG_DEBUG_MARCO_UART1)
>   #define SIRFSOC_UART1_PA_BASE          0xcc060000
>   #endif
> 
> the above codes seem still ugly ?
> 

No, that's fine, about as a good as it gets with today's kernel
capabilities. Just fix the description to have the correct
SoC name instead of "DaVinci DA8XX" ;-)

	Arnd


From balbi at ti.com  Tue Aug 21 05:15:55 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 12:15:55 +0300
Subject: [RFC/PATCH 13/13] serial: omap: make sure to suspend device before
 remove
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345540555-24359-14-git-send-email-balbi@ti.com>

before removing the driver, let's make sure
to force device into a suspended state in order
to conserve power.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 25d2055..f849ab9 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1334,6 +1334,7 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
+	pm_runtime_put_sync(up->dev);
 	pm_runtime_disable(up->dev);
 	uart_remove_one_port(&serial_omap_reg, &up->port);
 	pm_qos_remove_request(&up->pm_qos_request);
-- 
1.7.12.rc3



From lee.jones at linaro.org  Tue Aug 21 05:23:29 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 10:23:29 +0100
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
Message-ID: <20120821092328.GC26899@gmail.com>

On Tue, Aug 14, 2012 at 10:31:08AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > There was a plan to place ab8500_irq_get_virq() calls in each AB8500
> > child device prior to requesting an IRQ, but as we're no longer using
> > Device Tree to collect our IRQ numbers, it's actually better to allow
> > the core to do this during device registration time. So the IRQ number
> > we pull from its resource has already been converted to a virtual IRQ.
> >
> > CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
> > CC: linux-input at vger.kernel.org
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This is looking good, I guess you need all patches to go in at the
> same time so Dmitry's ACK is required.

Yep, just waiting for that now.
 
> FWIW:
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> BTW: this makes me suspect that the public ab8500_irq_get_virq()
> interface can be *deleted* and the function made static in the
> AB8500 driver, right?

Right. Already taken care of.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From 21cnbao at gmail.com  Tue Aug 21 05:29:54 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 17:29:54 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <1345450787-17246-3-git-send-email-Barry.Song@csr.com>
 <201208202106.43206.arnd@arndb.de>
 <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
Message-ID: <CAGsJ_4zBEgexWBWsKCe2UtfP1m7BSMO9dq8thi3oQVYsq22v+A@mail.gmail.com>

2012/8/21 Barry Song <21cnbao at gmail.com>:
> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
>> On Monday 20 August 2012, Barry Song wrote:
>>> From: Barry Song <Baohua.Song at csr.com>
>>>
>>> We will have SiRF Marco and Polo, so rename the dir to mach-sirf
>>> and add Kconfig menu
>>>
>>> Signed-off-by: Baohua Song <Baohua.Song at csr.com>
>>> ---
>>>  arch/arm/Kconfig                                   |   10 +++++-----
>>>  arch/arm/Makefile                                  |    2 +-
>>>  arch/arm/mach-sirf/Kconfig                         |   16 ++++++++++++++++
>>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile       |    0
>>>  arch/arm/{mach-prima2 => mach-sirf}/Makefile.boot  |    0
>>>  .../arm/{mach-prima2 => mach-sirf}/board-generic.c |    0
>>>  arch/arm/{mach-prima2 => mach-sirf}/common.h       |    0
>>>  .../include/mach/clkdev.h                          |    0
>>>  .../include/mach/debug-macro.S                     |    0
>>>  .../include/mach/entry-macro.S                     |    0
>>>  .../{mach-prima2 => mach-sirf}/include/mach/gpio.h |    0
>>>  .../include/mach/hardware.h                        |    0
>>>  .../{mach-prima2 => mach-sirf}/include/mach/irqs.h |    0
>>>  .../{mach-prima2 => mach-sirf}/include/mach/map.h  |    0
>>
>> I'm not sure if we should rename all of these right now. I've been thinking
>> about moving all of recent and simple ARMv7 based platforms (socfpga, zynq,
>> prima2, ...) into a single directory, where they would basically end up
>> being one file per platform. We should discuss this at the ARM mini summit,
>> and I can let you know the outcome of it. I don't object on the rename in
>> principle, but it might end up causing extra churn.
>
> ok. i will follow the output of  ARM mini summit.

i would think merging several SoCs into a dir still needs much time.
if the whole rename is too aggresive for the moment, how about keeping
the mach-prima2 temporarily, but this prima2 dir will also include the
coming Marco stuff?

-barry


From 21cnbao at gmail.com  Tue Aug 21 05:44:02 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 21 Aug 2012 17:44:02 +0800
Subject: [PATCH v4 1/2] ARM: PRIMA2: convert to common clk and finish full
 clk tree
In-Reply-To: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>
References: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>
Message-ID: <CAGsJ_4xAoa_w9BYKvtFS7=TdgXY6QReb7ja9QUWn=njbEq98vg@mail.gmail.com>

Hi Mike,

can you pls merge these two patches as our discussion at:

http://comments.gmane.org/gmane.linux.ports.arm.kernel/178760

our following many patches depend on these two.

-barry

2012/8/20 Barry Song <Barry.Song at csr.com>:
> From: Binghua Duan <Binghua.Duan at csr.com>
>
> Commit 02c981c07bc95ac1e only implements a little part of primaII clk tree
> due to common clk framework was not ready at that time.
> This patch converts the old driver to common clk and finish the full clk
> tree.
>
> Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  -v4: fix a typo


From santosh.shilimkar at ti.com  Tue Aug 21 05:44:19 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 21 Aug 2012 15:14:19 +0530
Subject: [RFC/PATCH 05/13] serial: omap: drop DMA support
In-Reply-To: <1345540555-24359-6-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-6-git-send-email-balbi@ti.com>
Message-ID: <CAMQu2gw93ES=u9J1FfWK_CKkgUq8V487+tmKtQ34p8O7VJ6aHA@mail.gmail.com>

On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> The current support is known to be broken and
> a later patch will come re-adding it using
> dma engine API.
>
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
Thanks Felipe !!
One less driver now towards OMAP DMA
engine conversion.

FWIW,
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From thomas.petazzoni at free-electrons.com  Tue Aug 21 05:46:30 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 Aug 2012 11:46:30 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120819012303.GX22226@titan.lakedaemon.net>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
 <20120817152156.4d91ba16@skate>
 <20120819012303.GX22226@titan.lakedaemon.net>
Message-ID: <20120821114630.545fb771@skate>

Le Sat, 18 Aug 2012 21:23:03 -0400,
Jason Cooper <jason at lakedaemon.net> a ?crit :

> On Fri, Aug 17, 2012 at 03:21:56PM +0200, Thomas Petazzoni wrote:
> > Le Thu, 16 Aug 2012 14:37:08 -0400,
> > Jason Cooper <jason at lakedaemon.net> a ?crit :
> > 
> > > > Whole series applied to:
> > > > 
> > > > git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7
> > > 
> > > I'm getting the following build error with orion_nand enabled:
> > > 
> > >   CC      drivers/mtd/nand/orion_nand.o
> > > drivers/mtd/nand/orion_nand.c:24:27: fatal error: mach/hardware.h: No
> > > such file or directory
> > > compilation terminated.
> > 
> > Are you perhaps trying to enable the orion_nand driver for a mach-mvebu
> > platform (Armada 370 or XP)? If it's the case, then yes, this build
> > breakage is expected: we haven't enabled any of the I/O for now, so we
> > don't have hardware.h yet. This is not something that is broken due to
> > the address decoding changes.
> 
> Ok, I've added Arnd and Olof to the CC.  The above is exactly what I
> did.
> 
> Arnd, how extensive is the 'make randconfig' testing in next?  Is this
> something that needs to be fixed before we push?  I found it by a fluke,
> but the right randconfig would light it up as well.

Well, this build failure is not caused by the address decoding changes
themselves. So the breakage you're seeing with that particular
configuration already exists. We would like to get these address
decoding changes merged so that we can make progress on the SMP support.

In parallel to that, we will start enabling the different I/O: network
interfaces, SATA, XOR engines, USB, etc. During this work, we'll
progressively make all these drivers compatible with mach-mvebu and
Armada 370/XP, and therefore fix the build issues like the one you're
seeing.

Or maybe, you want me to change the "depends on PLAT_ORION" of the
Orion NAND driver to "depends on PLAT_ORION_LEGACY" so that this driver
cannot be selected for now with mach-mvebu? As part of the PLAT_ORION
-> PLAT_ORION_LEGACY conversion, it would make sense. Of course, I
would do it for the other drivers as well (crypto, dma, etc.).

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From broonie at opensource.wolfsonmicro.com  Tue Aug 21 05:50:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 10:50:27 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821085618.GA26899@gmail.com>
References: <CACRpkdZ7bMBytyDppV2sB1d1sUbDpPRqAQVOq8k4UOYdmg+Mkw@mail.gmail.com>
 <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
Message-ID: <20120821095026.GU26991@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 09:56:19AM +0100, Lee Jones wrote:

> Wherever we do this from to be able to obtain the IRQ domain pointer, 
> which is where I'm currently struggling. Our options are:

> - If we're only talking MFD here, we can handle this stuff in the MFD
> core, but we need more information. The IRQ domain subsystem only allows
> domain look-up via a Device Tree node, so we need to get our hands on

What makes you say this?  This is just a convenience for finding a
domain, irqdomains are *completely* indepentant of device tree.

> the domain another way in the case of non-DT enabled devices. Either we
> add another parameter to mfd_add_device(irq_domain, ...), or we
> standardise the 'irq_domain' variable name and use:
>         irq_domain = container_of(parent, struct irq_domain, irq_domain);

Passing the domain into mfd seems like the obvious solution here - it's
exactly what we currently do for legacy stuff (where we pass in the irq
base), ideally what we'd end up with over time is that we could just
remove the irq_base parameter entirely as everything would in time be
moved over to using irqdomains.

> - I know that you have interest in pushing the functionality into the
> IRQ domain subsystem, but I'm struggling to see how. It's calling into
> the IRQ domain where we're seeing issues in the first place, specifically
> irq_create_mapping(). How about if we passed 'irq_domain' as a parameter
> when requesting the IRQ? That way we can pass the correct IRQ without
> worry of conversion. If 'irq_domain' is !NULL the IRQ management subsystem
> can do the necessary conversions. If 'irq_domain' is NULL it continues to
> use the requested IRQ as a virq.

This is totally orthogonal to doing the mapping in the MFD subsystem
which is the issue here.
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From catalin.marinas at arm.com  Tue Aug 21 05:50:51 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 10:50:51 +0100
Subject: [PATCH v2 08/31] arm64: CPU support
In-Reply-To: <201208202047.07991.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <20120815001043.GD19607@quad.lixom.net>
 <20120820155740.GA912@arm.com> <201208202047.07991.arnd@arndb.de>
Message-ID: <20120821095051.GA12708@arm.com>

On Mon, Aug 20, 2012 at 09:47:07PM +0100, Arnd Bergmann wrote:
> On Monday 20 August 2012, Catalin Marinas wrote:
> > > > --- /dev/null
> > > > +++ b/arch/arm64/mm/proc-syms.c
> > ...
> > > > +EXPORT_SYMBOL(__cpuc_flush_kern_all);
> > > > +EXPORT_SYMBOL(__cpuc_flush_user_all);
> > > > +EXPORT_SYMBOL(__cpuc_flush_user_range);
> > > > +EXPORT_SYMBOL(__cpuc_coherent_kern_range);
> > > > +EXPORT_SYMBOL(__cpuc_flush_dcache_area);
> > > 
> > > See comment on other email about putting function pointers in a struct
> > > instead.
> > 
> > There is no need to support multiple CPU architectures with different
> > implementations, so allowing these functions to be called without
> > indirection is better.
> 
> What is the __cpuc prefix about then? Could you just drop it?

It can be dropped indeed.

-- 
Catalin


From notasas at gmail.com  Tue Aug 21 05:57:40 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Tue, 21 Aug 2012 12:57:40 +0300
Subject: ARM hugetlb support?
In-Reply-To: <20120820082514.GF27631@e103986-lin>
References: <20120820082514.GF27631@e103986-lin>
Message-ID: <CANOLnOMaV_urZvRL5NF++3UpOQSa_RwL1jfOTdGkn7fN+yZ28Q@mail.gmail.com>

On Mon, Aug 20, 2012 at 11:25 AM, Steve Capper <steve.capper at arm.com> wrote:
> n Mon, Aug 20, 2012 at 00:18:12AM +0100, Grazvydas Ignotas wrote:
>> Hello,
> Hello Grazvydas,
>
>> I've found that hugetlb support patches have been posted some months
>> ago [1]. I've been testing them with very good results [2]. Are there
>> still plans to further develop them and eventually merge them?
>>
>
> We are currently working on HugeTLB and Transparent HugePage support for both
> LPAE and non-LPAE memory descriptors. The non-LPAE HugeTLB patches are based
> on Bill's.
>
> I hope to get some patches out to the list soon.

Sounds promising. If you CC me when sending those patches, I can test
them on CortexA8 with my application.
BTW as you probably know know, Catalin seems to have hugetlb branch for LPAE:
http://git.kernel.org/?p=linux/kernel/git/cmarinas/linux-arm-arch.git;a=shortlog;h=refs/heads/hugetlb


-- 
Gra?vydas


From arnd at arndb.de  Tue Aug 21 06:11:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 10:11:40 +0000
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120821090213.GE28660@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208201443070.1754@xanadu.home>
 <20120821090213.GE28660@mudshark.cambridge.arm.com>
Message-ID: <201208211011.41093.arnd@arndb.de>

On Tuesday 21 August 2012, Will Deacon wrote:
> On Mon, Aug 20, 2012 at 07:45:20PM +0100, Nicolas Pitre wrote:
> > On Mon, 20 Aug 2012, Will Deacon wrote:
> > > On Mon, Aug 20, 2012 at 07:04:01PM +0100, Nicolas Pitre wrote:
> > > > Nah... the const is wrong.  The way you wrote it means that addr may 
> > > > change but the pointed data is constant.  This is obviously wrong since 
> > > > we expect the pointed location to change even from a read.
> > > 
> > > That's the prototype for the read accessors though -- a bunch of other
> > > architectures define them that way (including asm-generic), so I wonder what
> > > the reasoning behind that was?
> > 
> > I'm still asserting that they're wrong.
> 
> I did a bit of digging around and `const volatile void *' is apparently used
> because a function with such a parameter type can be passed any old pointer
> without warnings. Torvalds says something about them here:
> 
>   http://readlist.com/lists/vger.kernel.org/linux-kernel/14/72300.html
> 
> Personally, I too think that the const is misleading and who on Earth would
> be passing in pointers to const for an I/O region? However, it's an argument
> I'd rather avoid so, for the sake of consistency, I'll cast away the const in
> the asm block.
> 

You could have a read-only register area, and I would regard it as sensible
to mark a pointer to it as "const", although there should not be any
optimizations based on that.

There is no need to cast away the constness of the pointer when passing
it into the inline assembly, as the "asm volatile" already implies that
gcc cannot remove the contents.

On a related topic, thank you very much for introducing the inline
assemblies here, as they finally solve a lingering problem that has
hit us in the past [1] and that could happen again in other drivers.

	Arnd

[1] http://old.nabble.com/ARM-unaligned-MMIO-access-with-attribute%28%28packed%29%29-td30827280.html


From m.szyprowski at samsung.com  Tue Aug 21 06:14:51 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 12:14:51 +0200
Subject: [PATCH 2/3] ARM: DMA-Mapping: print warning when atomic coherent
 allocation fails
In-Reply-To: <20120820230058.GA755@harshnoise.musicnaut.iki.fi>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>
 <20120820230058.GA755@harshnoise.musicnaut.iki.fi>
Message-ID: <000d01cd7f85$d091b3c0$71b51b40$%szyprowski@samsung.com>

Hello,

On Tuesday, August 21, 2012 1:01 AM Aaro Koskinen wrote:

> On Mon, Aug 20, 2012 at 12:47:27PM +0200, Marek Szyprowski wrote:
> > @@ -461,6 +461,9 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
> >  		bitmap_set(pool->bitmap, pageno, count);
> >  		ptr = pool->vaddr + PAGE_SIZE * pageno;
> >  		*ret_page = pool->page + pageno;
> > +	} else {
> > +		pr_err("Atomic coherent pool too small!\n"
> > +		       "Please increase it with coherent_pool= kernel parameter!\n");
> 
> This should be rate limited, perhaps even printed only once.

Ok, I will change it to pr_err_once().

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From arnd at arndb.de  Tue Aug 21 06:16:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 10:16:22 +0000
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4zBEgexWBWsKCe2UtfP1m7BSMO9dq8thi3oQVYsq22v+A@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <CAGsJ_4ynJjm6WuA6NGZdOgj80Xc=ZxKcRatQuEacVW=EXuxh=w@mail.gmail.com>
 <CAGsJ_4zBEgexWBWsKCe2UtfP1m7BSMO9dq8thi3oQVYsq22v+A@mail.gmail.com>
Message-ID: <201208211016.22511.arnd@arndb.de>

On Tuesday 21 August 2012, Barry Song wrote:
> i would think merging several SoCs into a dir still needs much time.
> if the whole rename is too aggresive for the moment, how about keeping
> the mach-prima2 temporarily, but this prima2 dir will also include the
> coming Marco stuff?
> 

Yes, that is what I meant. Sorry if I wasn't clear on that. Please send
the marco patches adding the code in the mach-prima2 directory.


	Arnd


From balbi at ti.com  Tue Aug 21 06:20:46 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:20:46 +0300
Subject: [RFC/PATCH 05/13] serial: omap: drop DMA support
In-Reply-To: <CAMQu2gw93ES=u9J1FfWK_CKkgUq8V487+tmKtQ34p8O7VJ6aHA@mail.gmail.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-6-git-send-email-balbi@ti.com>
 <CAMQu2gw93ES=u9J1FfWK_CKkgUq8V487+tmKtQ34p8O7VJ6aHA@mail.gmail.com>
Message-ID: <20120821102045.GL10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 03:14:19PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> > The current support is known to be broken and
> > a later patch will come re-adding it using
> > dma engine API.
> >
> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> > ---
> Thanks Felipe !!

no problem.

> One less driver now towards OMAP DMA
> engine conversion.

indeed :-) I'll take a closer look into rx timeout IRQ, but it looks
like we can use it to kick dma only for "big" transfers... need to play
with it for a while first, though.

> FWIW,
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

is this Ack for this patch only or the entire series ??

-- 
balbi
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From pavel at ucw.cz  Tue Aug 21 06:28:11 2012
From: pavel at ucw.cz (Pavel Machek)
Date: Tue, 21 Aug 2012 12:28:11 +0200
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <201208202034.55135.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
 <20120820105308.GA906@elf.ucw.cz>
 <201208202034.55135.arnd@arndb.de>
Message-ID: <20120821102811.GA22126@elf.ucw.cz>

On Mon 2012-08-20 20:34:54, Arnd Bergmann wrote:
> On Monday 20 August 2012, Pavel Machek wrote:
> > > This patch adds support for 32-bit applications. The vectors page is a
> > > binary blob mapped into the application user space at 0xffff0000 (the
> > > AArch64 toolchain does not support compilation of AArch32 code). Full
> > > compatibility with ARMv7 user space is supported. The use of deprecated
> > > ARMv7 functionality (SWP, CP15 barriers) has been disabled by default on
> > > AArch64 kernels and unaligned LDM/STM is not supported.
> > > 
> > > Please note that only the ARM 32-bit EABI is supported, so no OABI
> > > compatibility.
> > 
> > > +struct compat_statfs {
> > > +     int             f_type;
> > > +     int             f_bsize;
> > > +     int             f_blocks;
> > > +     int             f_bfree;
> > > +     int             f_bavail;
> > > +     int             f_files;
> > > +     int             f_ffree;
> > > +     compat_fsid_t   f_fsid;
> > > +     int             f_namelen;      /* SunOS ignores this field. */
> > 
> > I'm sure it does. But is it good comment?
> 
> Good catch. It seems that some of the other compat platforms (x86,
> sparc, powerpc) have the same thing. I guess the real solution would
> be to introduce an asm-generic/compat.h file that contains a bunch
> of those definitions, like
> 
> #ifndef compat_timespec
> struct compat_timespec {
>         compat_time_t   tv_sec;
>         s32             tv_nsec;
> };
> #endif
> 
> #ifndef compat_timeval
> struct compat_timeval {
>         compat_time_t   tv_sec;
>         s32             tv_usec;
> };
> #endif

Yes, I guess that would be very good.
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From matthew.leach at arm.com  Tue Aug 21 06:18:22 2012
From: matthew.leach at arm.com (Matthew Leach)
Date: Tue, 21 Aug 2012 11:18:22 +0100
Subject: [PATCH] serial: pl011: honour serial aliases in device tree
Message-ID: <1345544302-12406-1-git-send-email-matthew.leach@arm.com>

If the order of UART nodes is changed in the device tree, then tty dev
devices are attached to different serial ports causing the console to
be directed to a different physical serial port. The "serial" aliases
in the device tree should prevent this.

This patch ensures that the UART driver creates tty devices that
honour these aliases if a device tree is present.

Signed-off-by: Matthew Leach <matthew.leach at arm.com>
---
 drivers/tty/serial/amba-pl011.c |   39 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index c17923e..5919599 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,7 @@
 #include <linux/scatterlist.h>
 #include <linux/delay.h>
 #include <linux/types.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
 
 #include <asm/io.h>
@@ -1869,6 +1870,42 @@ static struct uart_driver amba_reg = {
 	.cons			= AMBA_CONSOLE,
 };
 
+#ifdef CONFIG_OF
+static int pl011_probe_dt_alias(int index, struct device *dev)
+{
+	struct device_node *np;
+	static bool seen_dev_with_alias = false;
+	static bool seen_dev_without_alias = false;
+	int ret = index;
+
+	np = dev->of_node;
+	if (!np)
+		return ret;
+
+	ret = of_alias_get_id(np, "serial");
+	if (IS_ERR_VALUE(ret)) {
+		seen_dev_without_alias = true;
+		ret = index;
+	} else {
+		seen_dev_with_alias = true;
+		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
+			dev_warn(dev, "requested serial port %d  not available.\n", ret);
+			ret = index;
+		}
+	}
+
+	if (seen_dev_with_alias && seen_dev_without_alias)
+		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
+
+	return ret;
+}
+#else
+static int pl011_probe_dt_alias(int index, struct device *dev)
+{
+	return index;
+}
+#endif
+
 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 {
 	struct uart_amba_port *uap;
@@ -1891,6 +1928,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto out;
 	}
 
+	i = pl011_probe_dt_alias(i, &dev->dev);
+
 	base = ioremap(dev->res.start, resource_size(&dev->res));
 	if (!base) {
 		ret = -ENOMEM;
-- 
1.7.0.4



From balbi at ti.com  Tue Aug 21 06:29:59 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:29:59 +0300
Subject: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree
In-Reply-To: <CAMQu2gy46sVEBH0hvaXrwOLMfcKH+fwyExFmwzAPzxQKoYwhhA@mail.gmail.com>
References: <1344855623-14879-1-git-send-email-santosh.shilimkar@ti.com>
 <1344855623-14879-5-git-send-email-santosh.shilimkar@ti.com>
 <503240EF.4050805@ti.com>
 <CAMQu2gxgSasF4mmEFiZq-gsZfQwYn07DKyVGBVPWqjYkTSTu6g@mail.gmail.com>
 <CAMQu2gyL4-j9QSKMpNi5QQFsLqex8Q=bW9uNQtsewXVyrTumOQ@mail.gmail.com>
 <20120821102455.GM10347@arwen.pp.htv.fi>
 <CAMQu2gy46sVEBH0hvaXrwOLMfcKH+fwyExFmwzAPzxQKoYwhhA@mail.gmail.com>
Message-ID: <20120821102958.GN10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:02:38PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 3:54 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
> >> On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
> >> <santosh.shilimkar at ti.com> wrote:
> >> > On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> >> >> Hi Santosh,
> >> >>
> >> >> On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
> >> >>> This provides PL310 Level 2 Cache Controller Device Tree
> >> >>> support for OMAP4 based devices.
> >> >>>
> >> >>> Cc: Benoit Cousson <b-cousson at ti.com>
> >> >>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >> >>> ---
> >> >>>  arch/arm/boot/dts/omap4.dtsi       |    7 +++++++
> >> >>>  arch/arm/mach-omap2/omap4-common.c |    6 +++++-
> >> >>>  2 files changed, 12 insertions(+), 1 deletion(-)
> >> >>>
> >> >>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> >> >>> index 6717c71..cf1efb6 100644
> >> >>> --- a/arch/arm/boot/dts/omap4.dtsi
> >> >>> +++ b/arch/arm/boot/dts/omap4.dtsi
> >> >>> @@ -36,6 +36,13 @@
> >> >>>               };
> >> >>>       };
> >> >>>
> >> >>
> >> >>> +     L2: l2-cache-controller {
> >> >>
> >> >> The reg offset is missing: l2-cache-controller at 48242000
> >> >>
> >> >>> +             compatible = "arm,pl310-cache";
> >> >>> +             reg = <0x48242000 0x1000>;
> >> >>> +             cache-unified;
> >> >>> +             cache-level = <2>;
> >> >>> +     };
> >> >>> +
> >> >>
> >> >> In theory, the L2 cache should be referenced from the CPUs.
> >> >>
> >> > Agree.
> >> >
> >> I have added the reference for the L2 controller in CPUs.
> >> Other information like L1 cache size etc can be added in cpu
> >> DT node with another patch.
> >>
> >> Updated patch below. Have also updated git branch
> >> accordingly.
> >>
> >> Regards
> >> Santosh
> >>
> >> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
> >> From: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >> Date: Wed, 4 Jul 2012 17:57:34 +0530
> >> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree
> >>
> >> This provides PL310 Level 2 Cache Controller Device Tree
> >> support for OMAP4 based devices.
> >>
> >> Cc: Benoit Cousson <b-cousson at ti.com>
> >> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >
> > nice work :-)
> >
> > FWIW this looks good to me:
> >
> > Acked-by: Felipe Balbi <balbi at ti.com>
> >
> Thanks.
> 
> > just one thing, will a similar patch for omap3 be sent ?
> >
> OMAP3 has an integrated L2 cache controller so there
> won't any additional DT node for L2.
> 
> OMAP3 CPU DT node can be updated with l1/l2 cache
> size etc related information though.

fair enough, thanks for the info.

-- 
balbi
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From santosh.shilimkar at ti.com  Tue Aug 21 06:35:22 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 21 Aug 2012 16:05:22 +0530
Subject: [RFC/PATCH 05/13] serial: omap: drop DMA support
In-Reply-To: <20120821102045.GL10347@arwen.pp.htv.fi>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-6-git-send-email-balbi@ti.com>
 <CAMQu2gw93ES=u9J1FfWK_CKkgUq8V487+tmKtQ34p8O7VJ6aHA@mail.gmail.com>
 <20120821102045.GL10347@arwen.pp.htv.fi>
Message-ID: <CAMQu2gyGVhB63rn+G6B3nFLki5ib40C_2o2Bh1mBd8sw8wT_Ng@mail.gmail.com>

On Tue, Aug 21, 2012 at 3:50 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Tue, Aug 21, 2012 at 03:14:19PM +0530, Shilimkar, Santosh wrote:
>> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
>> > The current support is known to be broken and
>> > a later patch will come re-adding it using
>> > dma engine API.
>> >
>> > Signed-off-by: Felipe Balbi <balbi at ti.com>
>> > ---
>> Thanks Felipe !!
>
> no problem.
>
>> One less driver now towards OMAP DMA
>> engine conversion.
>
> indeed :-) I'll take a closer look into rx timeout IRQ, but it looks
> like we can use it to kick dma only for "big" transfers... need to play
> with it for a while first, though.
>
Yep. The RX path with DMA is bit of difficult part to manage for
UART.

>> FWIW,
>> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> is this Ack for this patch only or the entire series ??
>
Two more patches to review and then I will do it for
full series on top of the cover-letter :-)

Regards
Santosh


From sebastian.hesselbarth at gmail.com  Tue Aug 21 06:37:24 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 Aug 2012 12:37:24 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120821114630.545fb771@skate>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
 <20120817152156.4d91ba16@skate>
 <20120819012303.GX22226@titan.lakedaemon.net>
 <20120821114630.545fb771@skate>
Message-ID: <CABJ1b_RVaSjsneDCvejSMot0ZHDr1dmeroVRDUNMF2y83UGXNA@mail.gmail.com>

On 8/21/12, Thomas Petazzoni <thomas.petazzoni at free-electrons.com> wrote:
> Or maybe, you want me to change the "depends on PLAT_ORION" of the
> Orion NAND driver to "depends on PLAT_ORION_LEGACY" so that this driver
> cannot be selected for now with mach-mvebu? As part of the PLAT_ORION
> -> PLAT_ORION_LEGACY conversion, it would make sense. Of course, I
> would do it for the other drivers as well (crypto, dma, etc.).

Thomas,

I have reworked addr-map to allow for both Armada 370/XP and Orion SoCs
merging into mach-mvebu. Instead of reusing PLAT_ORION this is totally
independent but reusing as much code as possible. I can send it hopefully
today if I get it cleaned up. I also have irq-mvebu, irq-orion, and time-mvebu
patches that merge code. With that patches booting Dove into mach-mvebu
works until DMA kicks in because XOR hasn't event touched for DT support
and is still missing.

Armada 370/XP should still work as they do with current patches in for-3.7
with little changes in DT. But that of course must be tested by you.

Sebastian


From balbi at ti.com  Tue Aug 21 06:34:39 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:34:39 +0300
Subject: [RFC/PATCH 05/13] serial: omap: drop DMA support
In-Reply-To: <CAMQu2gyGVhB63rn+G6B3nFLki5ib40C_2o2Bh1mBd8sw8wT_Ng@mail.gmail.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-6-git-send-email-balbi@ti.com>
 <CAMQu2gw93ES=u9J1FfWK_CKkgUq8V487+tmKtQ34p8O7VJ6aHA@mail.gmail.com>
 <20120821102045.GL10347@arwen.pp.htv.fi>
 <CAMQu2gyGVhB63rn+G6B3nFLki5ib40C_2o2Bh1mBd8sw8wT_Ng@mail.gmail.com>
Message-ID: <20120821103438.GQ10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:05:22PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 3:50 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Tue, Aug 21, 2012 at 03:14:19PM +0530, Shilimkar, Santosh wrote:
> >> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> >> > The current support is known to be broken and
> >> > a later patch will come re-adding it using
> >> > dma engine API.
> >> >
> >> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> >> > ---
> >> Thanks Felipe !!
> >
> > no problem.
> >
> >> One less driver now towards OMAP DMA
> >> engine conversion.
> >
> > indeed :-) I'll take a closer look into rx timeout IRQ, but it looks
> > like we can use it to kick dma only for "big" transfers... need to play
> > with it for a while first, though.
> >
> Yep. The RX path with DMA is bit of difficult part to manage for
> UART.
> 
> >> FWIW,
> >> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >
> > is this Ack for this patch only or the entire series ??
> >
> Two more patches to review and then I will do it for
> full series on top of the cover-letter :-)

cool, thanks

-- 
balbi
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From afzal at ti.com  Tue Aug 21 06:41:56 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:11:56 +0530
Subject: [PATCH v6 00/10] OMAP-GPMC: generic time calc, prepare for driver
Message-ID: <cover.1345524670.git.afzal@ti.com>

Hi,

This series provides a generic gpmc timing calculation routine. There
were three peripherals (OneNAND, tusb6010, smc91x) using custom timing
calculations, they are migrated to use the generic timing calculation.

Such a generic routine would help create a driver out of gpmc platform
code, which would be peripheral agnostic and thus lead to DT finally.
Input to generic timing calculation routine would be gpmc peripheral
timings, output - translated timings that gpmc can understand. Later,
to DT'ify, gpmc peripheral timings could be passed through DT. Input
timings that has been used here are selected such that it represents
those that are present in peripheral timing datasheets.

Proposed generic routine has been tested on OneNAND (async) on
OMAP3EVM rev C (as mainline does not have the OneNAND support for this,
local patch were used to test). For other cases of custom timing
calculation (tusb6010, smc91x non-muxed, OneNAND sync), generic timing
calculation routine was verified by simulating on OMAP3EVM. Codebase
for such a testing is available
@ git://gitorious.org/x0148406-public/linux-kernel.git gpmc-prep-v6-verify

Regarding "we_on" for onenand async, it was found that even for muxed
address/data, it need not be greater than "adv_wr_off", but rather
could be derived from write setup time for peripheral from start of
access, hence would more be in line with peripheral timings. With
"we_on" calculated this way, it was working fine. If it is required in
some cases to have "we_on" same as "wr_data_mux_bus" (i.e. greater
than "adv_wr_off") other than for IP's not having "wr_data_mux_bus",
another variable could be added to indicate it, but such a
requirement is not expected though.

It has been observed that "adv_rd_off" & "adv_wr_off" are currently
calculated by adding an offset over "oe_on" & "we_on" respectively
in the case of smc91x. But peripheral datasheet does not specify
so and so "adv_rd(wr)_off" has been derived (to be specific, made
ignorant of "oe_on" & "we_on") observing datasheet rather than adding
an offset. Hence this generic routine is expected to work for smc91x
(91C96 RX51 board). This was verified on smsc911x (9220 on OMAP3EVM)
- a similar ethernet controller.

Also this series contains, patches 1-3 of v5 in addition to
minor cleanups that were low hanging fruits came across upon
implementing generic timing routine. One such is credited to
Jon Hunter, relevant patch is 1/2 of his series
@ http://marc.info/?l=linux-omap&m=134090910321284&w=2

This series has been tested on OMAP3EVM. As mentioned above, generic
timing could be tested on OneNAND hardware working in async mode.
Also generic timing calculation for other cases was validated by
comparing output values of existing custom timing calculation routine
& the new generic one, these conditions were simulated on OMAP3EVM


This series is available
	@ git://gitorious.org/x0148406-public/linux-kernel.git gpmc-prep-v6

and is made on top of
	http://marc.info/?l=linux-omap&m=134554192102899&w=2

which is based over 3.6-rc1.

Regards
Afzal

v6:
	1. Generic timing calculation, move existing users of custom
	 calculation to use the new generic one
	2. Set OneNAND part to async mode before gpmc configuration
	3. Move extra delay time user handling to proper patch
	 (3/10 -> 2/10)
	4. Modify nand init for OMAP3EVM too as support got added
v5:
	Use flags for sync_read/write, hv, vhf
v4:
	Reorganize OneNAND set_sync/async functions in a better way
v3:
	1. Refactor OneNAND set_sync/async functions to separate out
	 timing and configurations
	2. Handle bool type timings too
	3. Swap patches 2 & 3 due to dependency of OneNAND change on
	 newly added bool type timings
v2:
	1. Make use of timing api for setting clock activation time,
	 and remove direct writing to register for clock activation.
	2. Move ensuring that async mode in OneNAND has been setup from
	 set_sync to setup function, improve commit message

Afzal Mohammed (9):
  ARM: OMAP2+: nand: unify init functions
  ARM: OMAP2+: gpmc: handle additional timings
  ARM: OMAP2+: onenand: refactor for clarity
  ARM: OMAP2+: gpmc: find features by ip rev check
  ARM: OMAP2+: gpmc: remove cs# in sync clk div calc
  ARM: OMAP2+: gpmc: generic timing calculation
  ARM: OMAP2+: onenand: generic timing calculation
  ARM: OMAP2+: smc91x: generic timing calculation
  ARM: OMAP2+: tusb6010: generic timing calculation

Jon Hunter (1):
  ARM: OMAP2+: GPMC: Remove unused OneNAND get_freq() platform function

 arch/arm/mach-omap2/board-devkit8000.c     |    8 +-
 arch/arm/mach-omap2/board-flash.c          |   45 ++--
 arch/arm/mach-omap2/board-flash.h          |    6 +-
 arch/arm/mach-omap2/board-igep0020.c       |    2 +-
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    8 +-
 arch/arm/mach-omap2/board-omap3evm.c       |    8 +-
 arch/arm/mach-omap2/board-omap3touchbook.c |    8 +-
 arch/arm/mach-omap2/board-overo.c          |    7 +-
 arch/arm/mach-omap2/board-zoom.c           |    5 +-
 arch/arm/mach-omap2/common-board-devices.c |   46 ----
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 arch/arm/mach-omap2/gpmc-onenand.c         |  334 +++++++++++---------------
 arch/arm/mach-omap2/gpmc-smc91x.c          |   43 ++--
 arch/arm/mach-omap2/gpmc.c                 |  363 +++++++++++++++++++++++++++-
 arch/arm/mach-omap2/usb-tusb6010.c         |  180 ++++-----------
 arch/arm/plat-omap/include/plat/gpmc.h     |   82 ++++++-
 arch/arm/plat-omap/include/plat/onenand.h  |    8 -
 18 files changed, 707 insertions(+), 451 deletions(-)



From santosh.shilimkar at ti.com  Tue Aug 21 06:42:11 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 21 Aug 2012 16:12:11 +0530
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <1345540555-24359-11-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-11-git-send-email-balbi@ti.com>
Message-ID: <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>

On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> Everytime we're done using our TTY, we want
> the pm timer to be reinitilized. By sticking
> to pm_runtime_pm_autosuspend() we make sure
> that this will always be the case.
>
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
>  drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
>  1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> index 6ea24c5..458d77c 100644
> --- a/drivers/tty/serial/omap-serial.c
> +++ b/drivers/tty/serial/omap-serial.c
> @@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
>         pm_runtime_get_sync(up->dev);
>         up->ier |= UART_IER_MSI;
>         serial_out(up, UART_IER, up->ier);
> -       pm_runtime_put(up->dev);
> +       pm_runtime_mark_last_busy(up->dev);
> +       pm_runtime_put_autosuspend(up->dev);
>  }
>
Can you please expand the change-log a bit ?
Didn't follow the time re-init part completely.

Regards
Santosh


From santosh.shilimkar at ti.com  Tue Aug 21 06:43:59 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 21 Aug 2012 16:13:59 +0530
Subject: [RFC/PATCH 00/13] OMAP UART patches
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <CAMQu2gxJqpJG0LbhbJ-YKOEpR=2_ogu2SpdUtvafn2kBXWudyg@mail.gmail.com>

On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi guys,
>
> here's a series of cleanup patches to the OMAP serial
> driver. A later series could be made re-implementing
> DMA using the DMA Engine API. Note that for RX DMA
> we could be using RX Timeout IRQ as a hint that we better
> use PIO instead ;-)
>
> All patches were tested on my pandaboard, but I'd really
> like to receive Tested-by on other platforms.
>
> After this goes in, I'll probably try to get UART wakeup
> working again and only after that look at DMA.
>
> cheers
>
> Felipe Balbi (13):
>   serial: omap: define and use to_uart_omap_port()
>   serial: omap: always return IRQ_HANDLED
>   serial: omap: define helpers for pdata function pointers
>   serial: omap: don't access the platform_device
>   serial: omap: drop DMA support
>   serial: add OMAP-specific defines
>   serial: omap: simplify IRQ handling
>   serial: omap: refactor receive_chars() into rdi/rlsi handlers
>   serial: omap: move THRE check to transmit_chars()
>   serial: omap: stick to put_autosuspend
>   serial: omap: set dev->drvdata before enabling pm_runtime
>   serial: omap: drop unnecessary check from remove
>   serial: omap: make sure to suspend device before remove
>
Apart from that one question on last patch, rest of the clean-up
is really good. Nice work.

FWIW,
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From afzal at ti.com  Tue Aug 21 06:45:13 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:13 +0530
Subject: [PATCH v6 02/10] ARM: OMAP2+: gpmc: handle additional timings
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <87c048380a105b8d2f9527faa77ae008933483f1.1345524670.git.afzal@ti.com>

Configure busturnaround, cycle2cycledelay, waitmonitoringtime,
clkactivationtime in gpmc_cs_set_timings(). This is done so
that boards can configure these parameters of gpmc in Kernel
instead of relying on bootloader. Also configure bool type
timings like extradelay.

This needed change to the existing users that were configuring
clk activation time and extra delay by directly writing to
registers. Thanks to Tony for making me aware of users of clk
activation and being kind enough to test the modified one.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---

v6:	Move extra delay time user handling to present one from 3/10
v3:	Handle bool type timings too
v2:	Make use of timing api for setting clock activation time,
	 and remove direct writing to register for clock activation.

 arch/arm/mach-omap2/gpmc-onenand.c     |   28 ++++---------------
 arch/arm/mach-omap2/gpmc.c             |   45 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/usb-tusb6010.c     |    3 +-
 arch/arm/plat-omap/include/plat/gpmc.h |   19 +++++++++++++
 4 files changed, 72 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 71d7c07..977b71d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -284,27 +284,10 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 					sync_read, sync_write, hf, vhf);
 
 	if (div == 1) {
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
-		reg |= (1 << 7);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
-		reg |= (1 << 7);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
-		reg |= (1 << 7);
-		reg |= (1 << 23);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
-	} else {
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
-		reg &= ~(1 << 7);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
-		reg &= ~(1 << 7);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
-		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
-		reg &= ~(1 << 7);
-		reg &= ~(1 << 23);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
+		t.bool_timings.cs_extra_delay = true;
+		t.bool_timings.adv_extra_delay = true;
+		t.bool_timings.oe_extra_delay = true;
+		t.bool_timings.we_extra_delay = true;
 	}
 
 	/* Set synchronous read timings */
@@ -329,6 +312,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
 		     ticks_cez);
 
+	t.clk_activation = fclk_offset_ns;
+
 	/* Write */
 	if (sync_write) {
 		t.adv_wr_off = t.adv_rd_off;
@@ -362,7 +347,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 			  (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-			  GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
 			  GPMC_CONFIG1_PAGE_LEN(2) |
 			  (cpu_is_omap34xx() ? 0 :
 				(GPMC_CONFIG1_WAIT_READ_MON |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 39c30d9..070fac5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -64,6 +64,13 @@
 #define GPMC_ECC_CTRL_ECCREG8		0x008
 #define GPMC_ECC_CTRL_ECCREG9		0x009
 
+#define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)
+#define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)
+#define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)
+#define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)
+#define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)
+#define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)
+
 #define GPMC_CS0_OFFSET		0x60
 #define GPMC_CS_SIZE		0x30
 
@@ -220,6 +227,36 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 	return ticks * gpmc_get_fclk_period() / 1000;
 }
 
+static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
+{
+	u32 l;
+
+	l = gpmc_cs_read_reg(cs, reg);
+	if (value)
+		l |= mask;
+	else
+		l &= ~mask;
+	gpmc_cs_write_reg(cs, reg, l);
+}
+
+static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
+{
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
+		GPMC_CONFIG1_TIME_PARA_GRAN, p->time_para_granularity);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
+		GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
+		GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
+		GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
+		GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
+		GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, p->cycle2cyclesamecsen);
+	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
+		GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, p->cycle2cyclediffcsen);
+}
+
 #ifdef DEBUG
 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 			       int time, const char *name)
@@ -313,6 +350,12 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
+	GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
+	GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
+
+	GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
+	GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
+
 	if (cpu_is_omap34xx()) {
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
@@ -332,6 +375,8 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 	}
 
+	gpmc_cs_bool_timings(cs, &t->bool_timings);
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 805bea6..7a85ebe 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -174,6 +174,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
 	tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */;
 	t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
 
+	t.clk_activation = gpmc_ticks_to_ns(1);
+
 	return gpmc_cs_set_timings(sync_cs, &t);
 }
 
@@ -283,7 +285,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
 			| GPMC_CONFIG1_READTYPE_SYNC
 			| GPMC_CONFIG1_WRITEMULTIPLE_SUPP
 			| GPMC_CONFIG1_WRITETYPE_SYNC
-			| GPMC_CONFIG1_CLKACTIVATIONTIME(1)
 			| GPMC_CONFIG1_PAGE_LEN(2)
 			| GPMC_CONFIG1_WAIT_READ_MON
 			| GPMC_CONFIG1_WAIT_WRITE_MON
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 2e6e259..b7c9ea6 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -96,6 +96,17 @@ enum omap_ecc {
 	OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
 };
 
+/* bool type time settings */
+struct gpmc_bool_timings {
+	bool cycle2cyclediffcsen;
+	bool cycle2cyclesamecsen;
+	bool we_extra_delay;
+	bool oe_extra_delay;
+	bool adv_extra_delay;
+	bool cs_extra_delay;
+	bool time_para_granularity;
+};
+
 /*
  * Note that all values in this struct are in nanoseconds except sync_clk
  * (which is in picoseconds), while the register values are in gpmc_fck cycles.
@@ -128,9 +139,17 @@ struct gpmc_timings {
 	u16 rd_cycle;		/* Total read cycle time */
 	u16 wr_cycle;		/* Total write cycle time */
 
+	u16 bus_turnaround;
+	u16 cycle2cycle_delay;
+
+	u16 wait_monitoring;
+	u16 clk_activation;
+
 	/* The following are only on OMAP3430 */
 	u16 wr_access;		/* WRACCESSTIME */
 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
+
+	struct gpmc_bool_timings bool_timings;
 };
 
 struct gpmc_nand_regs {
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:07 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:07 +0530
Subject: [PATCH v6 01/10] ARM: OMAP2+: nand: unify init functions
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <8e0958354be60d026e7e03bd179509fcbe70957b.1345524670.git.afzal@ti.com>

Helper function for updating nand platform data has been
added the capability to take timing structure arguement.
Usage of omap_nand_flash_init() has been replaced by modifed
one, omap_nand_flash_init was doing things similar to
board_nand_init except that NAND CS# were being acquired
based on bootloader setting. As CS# is hardwired for a given
board, acquiring gpmc CS# has been removed, and updated with
the value on board.

NAND CS# used in beagle board & omap3evm was found to be CS0.
Thomas Weber <thomas.weber.linux at googlemail.com> reported
that value of devkit8000 to be CS0. Overo board was found
to be using CS0 based on u-boot, while google grep says
omap3touchbook too has CS0.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
Reviewed-by: Jon Hunter <jon-hunter at ti.com>
---

v6:	Modify nand init for OMAP3EVM too as support got added

 arch/arm/mach-omap2/board-devkit8000.c     |    8 ++++-
 arch/arm/mach-omap2/board-flash.c          |   45 ++++++++++++++-------------
 arch/arm/mach-omap2/board-flash.h          |    6 ++-
 arch/arm/mach-omap2/board-igep0020.c       |    2 +-
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    8 ++++-
 arch/arm/mach-omap2/board-omap3evm.c       |    8 ++++-
 arch/arm/mach-omap2/board-omap3touchbook.c |    8 ++++-
 arch/arm/mach-omap2/board-overo.c          |    7 +++-
 arch/arm/mach-omap2/board-zoom.c           |    5 ++-
 arch/arm/mach-omap2/common-board-devices.c |   46 ----------------------------
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 12 files changed, 62 insertions(+), 86 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1c..6ee429a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -59,8 +59,11 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define	NAND_CS			0
+
 #define OMAP_DM9000_GPIO_IRQ	25
 #define OMAP3_DEVKIT_TS_GPIO	27
 
@@ -628,8 +631,9 @@ static void __init devkit8000_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
-			     ARRAY_SIZE(devkit8000_nand_partitions));
+	board_nand_init(devkit8000_nand_partitions,
+		ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 53c39d2..47fb903 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -103,41 +103,41 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 /* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings[1] = {
+	{
+		.sync_clk = 0,
 
-	.sync_clk = 0,
+		.cs_on = 0,
+		.cs_rd_off = 36,
+		.cs_wr_off = 36,
 
-	.cs_on = 0,
-	.cs_rd_off = 36,
-	.cs_wr_off = 36,
+		.adv_on = 6,
+		.adv_rd_off = 24,
+		.adv_wr_off = 36,
 
-	.adv_on = 6,
-	.adv_rd_off = 24,
-	.adv_wr_off = 36,
+		.we_off = 30,
+		.oe_off = 48,
 
-	.we_off = 30,
-	.oe_off = 48,
+		.access = 54,
+		.rd_cycle = 72,
+		.wr_cycle = 72,
 
-	.access = 54,
-	.rd_cycle = 72,
-	.wr_cycle = 72,
-
-	.wr_access = 30,
-	.wr_data_mux_bus = 0,
+		.wr_access = 30,
+		.wr_data_mux_bus = 0,
+	},
 };
 
-static struct omap_nand_platform_data board_nand_data = {
-	.gpmc_t		= &nand_timings,
-};
+static struct omap_nand_platform_data board_nand_data;
 
 void
-__init board_nand_init(struct mtd_partition *nand_parts,
-			u8 nr_parts, u8 cs, int nand_type)
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+				int nand_type, struct gpmc_timings *gpmc_t)
 {
 	board_nand_data.cs		= cs;
 	board_nand_data.parts		= nand_parts;
 	board_nand_data.nr_parts	= nr_parts;
 	board_nand_data.devsize		= nand_type;
+	board_nand_data.gpmc_t		= gpmc_t;
 
 	board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
 	board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
@@ -238,5 +238,6 @@ void __init board_flash_init(struct flash_partitions partition_info[],
 		pr_err("NAND: Unable to find configuration in GPMC\n");
 	else
 		board_nand_init(partition_info[2].parts,
-			partition_info[2].nr_parts, nandcs, nand_type);
+			partition_info[2].nr_parts, nandcs,
+			nand_type, nand_default_timings);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index c44b70d..a3aa5fc 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -40,12 +40,14 @@ static inline void board_flash_init(struct flash_partitions part[],
 #if defined(CONFIG_MTD_NAND_OMAP2) || \
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type);
+		u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
+extern struct gpmc_timings nand_default_timings[];
 #else
 static inline void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type)
+		u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
 {
 }
+#define	nand_default_timings	NULL
 #endif
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 2821448..b7401f7 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -175,7 +175,7 @@ static void __init igep_flash_init(void)
 		pr_info("IGEP: initializing NAND memory device\n");
 		board_nand_init(igep_flash_partitions,
 				ARRAY_SIZE(igep_flash_partitions),
-				0, NAND_BUSWIDTH_16);
+				0, NAND_BUSWIDTH_16, nand_default_timings);
 	} else if (mux == IGEP_SYSBOOT_ONENAND) {
 		pr_info("IGEP: initializing OneNAND memory device\n");
 		board_onenand_init(igep_flash_partitions,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ef9e829..5d8fa99 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -427,8 +427,8 @@ static void __init omap_ldp_init(void)
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
 	usb_musb_init(NULL);
-	board_nand_init(ldp_nand_partitions,
-		ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+	board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
+				ZOOM_NAND_CS, 0, nand_default_timings);
 
 	omap_hsmmc_init(mmc);
 	ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc7..940ab49 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -51,8 +51,11 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define	NAND_CS	0
+
 /*
  * OMAP3 Beagle revision
  * Run time detection of Beagle revision is done by reading GPIO.
@@ -517,8 +520,9 @@ static void __init omap3_beagle_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
-			     ARRAY_SIZE(omap3beagle_nand_partitions));
+	board_nand_init(omap3beagle_nand_partitions,
+		ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure msecure is mux'd to be able to set the RTC. */
 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0d362e9..833c42c 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -57,6 +57,9 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+
+#define	NAND_CS			0
 
 #define OMAP3_EVM_TS_GPIO	175
 #define OMAP3_EVM_EHCI_VBUS	22
@@ -730,8 +733,9 @@ static void __init omap3_evm_init(void)
 	}
 	usb_musb_init(&musb_board_data);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
-			     ARRAY_SIZE(omap3evm_nand_partitions));
+	board_nand_init(omap3evm_nand_partitions,
+		ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
+		NAND_BUSWIDTH_16, NULL);
 
 	omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
 	omap3evm_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 485d14d..75e07f6 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -52,6 +52,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #include <asm/setup.h>
@@ -61,6 +62,8 @@
 #define TB_BL_PWM_TIMER		9
 #define TB_KILL_POWER_GPIO	168
 
+#define	NAND_CS			0
+
 static unsigned long touchbook_revision;
 
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
@@ -370,8 +373,9 @@ static void __init omap3_touchbook_init(void)
 	omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
-			     ARRAY_SIZE(omap3touchbook_nand_partitions));
+	board_nand_init(omap3touchbook_nand_partitions,
+		ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d..56d5b9e 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -57,8 +57,11 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
+#define	NAND_CS			0
+
 #define OVERO_GPIO_BT_XGATE	15
 #define OVERO_GPIO_W2W_NRESET	16
 #define OVERO_GPIO_PENDOWN	114
@@ -500,8 +503,8 @@ static void __init overo_init(void)
 	omap_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
-	omap_nand_flash_init(0, overo_nand_partitions,
-			     ARRAY_SIZE(overo_nand_partitions));
+	board_nand_init(overo_nand_partitions,
+		ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
 	overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4e7e561..a04dd85 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -114,8 +114,9 @@ static void __init omap_zoom_init(void)
 		usbhs_init(&usbhs_bdata);
 	}
 
-	board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
-						ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+	board_nand_init(zoom_nand_partitions,
+			ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+			NAND_BUSWIDTH_16, nand_default_timings);
 	zoom_debugboard_init();
 	zoom_peripherals_init();
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index c187586..3aef3a9 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -95,49 +95,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 {
 }
 #endif
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-	u8 cs = 0;
-	u8 nandcs = GPMC_CS_NUM + 1;
-
-	/* find out the chip-select on which NAND exists */
-	while (cs < GPMC_CS_NUM) {
-		u32 ret = 0;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		if ((ret & 0xC00) == 0x800) {
-			printk(KERN_INFO "Found NAND on CS%d\n", cs);
-			if (nandcs > GPMC_CS_NUM)
-				nandcs = cs;
-		}
-		cs++;
-	}
-
-	if (nandcs > GPMC_CS_NUM) {
-		printk(KERN_INFO "NAND: Unable to find configuration "
-				 "in GPMC\n ");
-		return;
-	}
-
-	if (nandcs < GPMC_CS_NUM) {
-		nand_data.cs = nandcs;
-		nand_data.parts = parts;
-		nand_data.nr_parts = nr_parts;
-		nand_data.devsize = options;
-
-		printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-		if (gpmc_nand_init(&nand_data) < 0)
-			printk(KERN_ERR "Unable to register NAND device\n");
-	}
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-}
-#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a42..72bb41b 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 		       struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
 
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:19 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:19 +0530
Subject: [PATCH v6 03/10] ARM: OMAP2+: onenand: refactor for clarity
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <932f692496f484143705e272e19ae3a18c18521f.1345524670.git.afzal@ti.com>

Refactor set_async_mode & set_sync_mode functions to
separate out timing calculation & actual configuration
(GPMC & OneNAND side).

Thanks to Jon for his suggestions.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
Reviewed-by: Jon Hunter <jon-hunter at ti.com>
---

v6:
	1. Set OneNAND part to async mode before gpmc configuration
	2. Move extra delay time user handling away from this patch
	 (3/10 -> 2/10)
v5:	Use flags for sync_read/write, hv, vhf
v4:	Reorganize OneNAND set_sync/async functions in a better way
v3:	Refactor OneNAND set_sync/async functions to separate out
	 timing and configurations
v2:	Move ensuring that async mode in OneNAND has been setup from
	 set_sync to setup function, improve commit message

 arch/arm/mach-omap2/gpmc-onenand.c |  174 ++++++++++++++++++++++-------------
 1 files changed, 109 insertions(+), 65 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 977b71d..bbae674 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/err.h>
 
 #include <asm/mach/flash.h>
 
@@ -25,6 +26,14 @@
 
 #define	ONENAND_IO_SIZE	SZ_128K
 
+#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
+#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
+#define	ONENAND_FLAG_HF		(1 << 2)
+#define	ONENAND_FLAG_VHF	(1 << 3)
+
+static unsigned onenand_flags;
+static unsigned latency;
+
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 
 static struct resource gpmc_onenand_resource = {
@@ -38,11 +47,9 @@ static struct platform_device gpmc_onenand_device = {
 	.resource	= &gpmc_onenand_resource,
 };
 
-static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 {
 	struct gpmc_timings t;
-	u32 reg;
-	int err;
 
 	const int t_cer = 15;
 	const int t_avdp = 12;
@@ -55,11 +62,6 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 	const int t_wpl = 40;
 	const int t_wph = 30;
 
-	/* Ensure sync read and sync write are disabled */
-	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
-	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-
 	memset(&t, 0, sizeof(t));
 	t.sync_clk = 0;
 	t.cs_on = 0;
@@ -86,25 +88,30 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 	t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
 	t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
 
+	return t;
+}
+
+static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
+{
 	/* Configure GPMC for asynchronous read */
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 			  GPMC_CONFIG1_DEVICESIZE_16 |
 			  GPMC_CONFIG1_MUXADDDATA);
 
-	err = gpmc_cs_set_timings(cs, &t);
-	if (err)
-		return err;
+	return gpmc_cs_set_timings(cs, t);
+}
+
+static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
+{
+	u32 reg;
 
 	/* Ensure sync read and sync write are disabled */
 	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
 	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
 	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
-
-	return 0;
 }
 
-static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-				int sync_read, int sync_write, int hf, int vhf)
+static void set_onenand_cfg(void __iomem *onenand_base)
 {
 	u32 reg;
 
@@ -112,19 +119,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
 		ONENAND_SYS_CFG1_BL_16;
-	if (sync_read)
+	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
 		reg |= ONENAND_SYS_CFG1_SYNC_READ;
 	else
 		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
-	if (sync_write)
+	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
 		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 	else
 		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
-	if (hf)
+	if (onenand_flags & ONENAND_FLAG_HF)
 		reg |= ONENAND_SYS_CFG1_HF;
 	else
 		reg &= ~ONENAND_SYS_CFG1_HF;
-	if (vhf)
+	if (onenand_flags & ONENAND_FLAG_VHF)
 		reg |= ONENAND_SYS_CFG1_VHF;
 	else
 		reg &= ~ONENAND_SYS_CFG1_VHF;
@@ -172,9 +179,9 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
 	return freq;
 }
 
-static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
-					void __iomem *onenand_base,
-					int *freq_ptr)
+static struct gpmc_timings
+omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
+						int freq, bool clk_dep)
 {
 	struct gpmc_timings t;
 	const int t_cer  = 15;
@@ -184,29 +191,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	const int t_wpl  = 40;
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-	int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
-	int err, ticks_cez;
-	int cs = cfg->cs, freq = *freq_ptr;
-	u32 reg;
-	bool clk_dep = false;
-
-	if (cfg->flags & ONENAND_SYNC_READ) {
-		sync_read = 1;
-	} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
-		sync_read = 1;
-		sync_write = 1;
-	} else
-		return omap2_onenand_set_async_mode(cs, onenand_base);
+	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns;
+	int ticks_cez;
+	int cs = cfg->cs;
 
-	if (!freq) {
-		/* Very first call freq is not known */
-		err = omap2_onenand_set_async_mode(cs, onenand_base);
-		if (err)
-			return err;
-		freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
-		first_time = 1;
-	}
+	if (cfg->flags & ONENAND_SYNC_READ)
+		onenand_flags = ONENAND_FLAG_SYNCREAD;
+	else if (cfg->flags & ONENAND_SYNC_READWRITE)
+		onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
 	switch (freq) {
 	case 104:
@@ -244,19 +236,23 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		t_ach   = 9;
 		t_aavdh = 7;
 		t_rdyo  = 15;
-		sync_write = 0;
+		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
 		break;
 	}
 
 	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
 	gpmc_clk_ns = gpmc_ticks_to_ns(div);
 	if (gpmc_clk_ns < 15) /* >66Mhz */
-		hf = 1;
+		onenand_flags |= ONENAND_FLAG_HF;
+	else
+		onenand_flags &= ~ONENAND_FLAG_HF;
 	if (gpmc_clk_ns < 12) /* >83Mhz */
-		vhf = 1;
-	if (vhf)
+		onenand_flags |= ONENAND_FLAG_VHF;
+	else
+		onenand_flags &= ~ONENAND_FLAG_VHF;
+	if (onenand_flags & ONENAND_FLAG_VHF)
 		latency = 8;
-	else if (hf)
+	else if (onenand_flags & ONENAND_FLAG_HF)
 		latency = 6;
 	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
 		latency = 3;
@@ -279,9 +275,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		}
 	}
 
-	if (first_time)
-		set_onenand_cfg(onenand_base, latency,
-					sync_read, sync_write, hf, vhf);
+	/* Set synchronous read timings */
+	memset(&t, 0, sizeof(t));
 
 	if (div == 1) {
 		t.bool_timings.cs_extra_delay = true;
@@ -290,8 +285,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		t.bool_timings.we_extra_delay = true;
 	}
 
-	/* Set synchronous read timings */
-	memset(&t, 0, sizeof(t));
 	t.sync_clk = min_gpmc_clk_period;
 	t.cs_on = 0;
 	t.adv_on = 0;
@@ -315,7 +308,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	t.clk_activation = fclk_offset_ns;
 
 	/* Write */
-	if (sync_write) {
+	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
 		t.adv_wr_off = t.adv_rd_off;
 		t.we_on  = 0;
 		t.we_off = t.cs_rd_off;
@@ -340,6 +333,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		}
 	}
 
+	return t;
+}
+
+static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
+{
+	unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
+	unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
+
 	/* Configure GPMC for synchronous read */
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 			  GPMC_CONFIG1_WRAPBURST_SUPP |
@@ -355,11 +356,47 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 			  GPMC_CONFIG1_DEVICETYPE_NOR |
 			  GPMC_CONFIG1_MUXADDDATA);
 
-	err = gpmc_cs_set_timings(cs, &t);
-	if (err)
-		return err;
+	return gpmc_cs_set_timings(cs, t);
+}
+
+static int omap2_onenand_setup_async(void __iomem *onenand_base)
+{
+	struct gpmc_timings t;
+	int ret;
+
+	omap2_onenand_set_async_mode(onenand_base);
+
+	t = omap2_onenand_calc_async_timings();
+
+	ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	omap2_onenand_set_async_mode(onenand_base);
+
+	return 0;
+}
+
+static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
+{
+	int ret, freq = *freq_ptr;
+	struct gpmc_timings t;
+	bool clk_dep = false;
+
+	if (!freq) {
+		/* Very first call freq is not known */
+		freq = omap2_onenand_get_freq(gpmc_onenand_data,
+						onenand_base, &clk_dep);
+		set_onenand_cfg(onenand_base);
+	}
+
+	t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq, clk_dep);
 
-	set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+	ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	set_onenand_cfg(onenand_base);
 
 	*freq_ptr = freq;
 
@@ -369,15 +406,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
 	struct device *dev = &gpmc_onenand_device.dev;
+	unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
+	int ret;
 
-	/* Set sync timings in GPMC */
-	if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-			freq_ptr) < 0) {
-		dev_err(dev, "Unable to set synchronous mode\n");
-		return -EINVAL;
+	ret = omap2_onenand_setup_async(onenand_base);
+	if (ret) {
+		dev_err(dev, "unable to set to async mode\n");
+		return ret;
 	}
 
-	return 0;
+	if (!(gpmc_onenand_data->flags & l))
+		return 0;
+
+	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
+	if (ret)
+		dev_err(dev, "unable to set to sync mode\n");
+	return ret;
 }
 
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:25 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:25 +0530
Subject: [PATCH v6 04/10] ARM: OMAP2+: GPMC: Remove unused OneNAND get_freq()
 platform function
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <17842e012f55065653a29e9361625d03567ac4f6.1345524670.git.afzal@ti.com>

From: Jon Hunter <jon-hunter at ti.com>

A platform function pointer for getting the frequency of a OneNAND device
was added so that a platform could specify a custom function for returning
the frequency and not just rely on the OneNAND version to determine the
frequency. However, this platform function pointer is not currently being
used and I am not sure if it ever has.

OneNAND devices are not so common these days and as far as I know not being
used with new devices. Therefore, it is most likely that this get_freq()
function pointer will not be used and so remove it.

Given that the get_freq() function pointer is not used, neither is the
clk_dep variable and so all references to it can also be removed.

Signed-off-by: Jon Hunter <jon-hunter at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-onenand.c        |   39 +++-------------------------
 arch/arm/plat-omap/include/plat/onenand.h |    8 ------
 2 files changed, 5 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index bbae674..8a301f3 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -139,21 +139,10 @@ static void set_onenand_cfg(void __iomem *onenand_base)
 }
 
 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
-				  void __iomem *onenand_base, bool *clk_dep)
+				  void __iomem *onenand_base)
 {
 	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
-	int freq = 0;
-
-	if (cfg->get_freq) {
-		struct onenand_freq_info fi;
-
-		fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
-		fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
-		fi.ver_id = ver;
-		freq = cfg->get_freq(&fi, clk_dep);
-		if (freq)
-			return freq;
-	}
+	int freq;
 
 	switch ((ver >> 4) & 0xf) {
 	case 0:
@@ -181,7 +170,7 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
 
 static struct gpmc_timings
 omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-						int freq, bool clk_dep)
+						int freq)
 {
 	struct gpmc_timings t;
 	const int t_cer  = 15;
@@ -259,22 +248,6 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
 	else
 		latency = 4;
 
-	if (clk_dep) {
-		if (gpmc_clk_ns < 12) { /* >83Mhz */
-			t_ces   = 3;
-			t_avds  = 4;
-		} else if (gpmc_clk_ns < 15) { /* >66Mhz */
-			t_ces   = 5;
-			t_avds  = 4;
-		} else if (gpmc_clk_ns < 25) { /* >40Mhz */
-			t_ces   = 6;
-			t_avds  = 5;
-		} else {
-			t_ces   = 7;
-			t_avds  = 7;
-		}
-	}
-
 	/* Set synchronous read timings */
 	memset(&t, 0, sizeof(t));
 
@@ -381,16 +354,14 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
 {
 	int ret, freq = *freq_ptr;
 	struct gpmc_timings t;
-	bool clk_dep = false;
 
 	if (!freq) {
 		/* Very first call freq is not known */
-		freq = omap2_onenand_get_freq(gpmc_onenand_data,
-						onenand_base, &clk_dep);
+		freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
 		set_onenand_cfg(onenand_base);
 	}
 
-	t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq, clk_dep);
+	t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
 
 	ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
 	if (IS_ERR_VALUE(ret))
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 2858667..21bb0ff 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,20 +15,12 @@
 #define ONENAND_SYNC_READ	(1 << 0)
 #define ONENAND_SYNC_READWRITE	(1 << 1)
 
-struct onenand_freq_info {
-	u16			maf_id;
-	u16			dev_id;
-	u16			ver_id;
-};
-
 struct omap_onenand_platform_data {
 	int			cs;
 	int			gpio_irq;
 	struct mtd_partition	*parts;
 	int			nr_parts;
 	int			(*onenand_setup)(void __iomem *, int *freq_ptr);
-	int		(*get_freq)(const struct onenand_freq_info *freq_info,
-				    bool *clk_dep);
 	int			dma_channel;
 	u8			flags;
 	u8			regulator_can_sleep;
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:33 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:33 +0530
Subject: [PATCH v6 05/10] ARM: OMAP2+: gpmc: find features by ip rev check
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <0b211272d0d6f9281df7db400cb2d6a968b31222.1345524670.git.afzal@ti.com>

Newer IP's have wr_access and wr_data_mux_bus fields. Use
IP revision values to determine availability of these
fields and hence decide on whether to configure them.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 070fac5..68123d0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -85,6 +85,11 @@
 #define ENABLE_PREFETCH		(0x1 << 7)
 #define DMA_MPU_MODE		2
 
+#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)
+
+#define	GPMC_HAS_WR_ACCESS		0x1
+#define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
+
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
 #define	GPMC_NR_IRQ		2
@@ -131,6 +136,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
 
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
@@ -356,10 +362,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
 	GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
 
-	if (cpu_is_omap34xx()) {
+	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-	}
 
 	/* caller is expected to have initialized CONFIG1 to cover
 	 * at least sync vs async
@@ -922,6 +928,8 @@ static int __init gpmc_init(void)
 	clk_enable(gpmc_l3_clk);
 
 	l = gpmc_read_reg(GPMC_REVISION);
+	if (GPMC_REVISION_MAJOR(l) > 0x4)
+		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
 	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 	/* Set smart idle mode and automatic L3 clock gating */
 	l = gpmc_read_reg(GPMC_SYSCONFIG);
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 21 06:45:36 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 21 Aug 2012 16:15:36 +0530
Subject: [PATCH 0/4] Add mfd driver for smsc-ece1099 chip
Message-ID: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>

Add a smsc-ece1099 mfd driver which will work as 
keypad scan device or a gpio expander device.

Patch 1 creates the parent mfd driver.
Patch 2 add keypad support. Patch 3 adds dts
support for keypad in omap5 dts file.
Patch 4 add gpio expansion driver for chip (RFC).

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>

G, Manjunath Kondaiah (1):
  Input: keypad: Add smsc ece1099 keypad driver

Sourav Poddar (3):
  mfd: smsc: Add support for smsc gpio io/keypad driver
  arm/dts: omap5-evm: Add keypad support
  gpio: smscece: Add support for gpio IO expander feature

 Documentation/smsc_ece1099.txt               |   56 ++++
 arch/arm/boot/dts/omap5-evm.dts              |   95 +++++++
 drivers/gpio/Kconfig                         |    7 +
 drivers/gpio/Makefile                        |    1 +
 drivers/gpio/gpio-smscece.c                  |  373 ++++++++++++++++++++++++++
 drivers/input/keyboard/Kconfig               |   11 +
 drivers/input/keyboard/Makefile              |    1 +
 drivers/input/keyboard/smsc-ece1099-keypad.c |  308 +++++++++++++++++++++
 drivers/mfd/Kconfig                          |   10 +
 drivers/mfd/Makefile                         |    1 +
 drivers/mfd/smsc-ece1099.c                   |  139 ++++++++++
 include/linux/mfd/smsc.h                     |   89 ++++++
 12 files changed, 1091 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/smsc_ece1099.txt
 create mode 100644 drivers/gpio/gpio-smscece.c
 create mode 100644 drivers/input/keyboard/smsc-ece1099-keypad.c
 create mode 100644 drivers/mfd/smsc-ece1099.c
 create mode 100644 include/linux/mfd/smsc.h



From afzal at ti.com  Tue Aug 21 06:45:40 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:40 +0530
Subject: [PATCH v6 06/10] ARM: OMAP2+: gpmc: remove cs# in sync clk div calc
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <3cc7885c2ae9055763ba72cae0735b065dae403e.1345524670.git.afzal@ti.com>

Divider value for a certain sync clk is determined solely
based on gpmc fclk. CS# does not have any role here, thus
remove presence of CS# in clock divider calculation API.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-onenand.c     |    3 +--
 arch/arm/mach-omap2/gpmc.c             |    4 ++--
 arch/arm/plat-omap/include/plat/gpmc.h |    2 +-
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 8a301f3..e139e3f 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -182,7 +182,6 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns;
 	int ticks_cez;
-	int cs = cfg->cs;
 
 	if (cfg->flags & ONENAND_SYNC_READ)
 		onenand_flags = ONENAND_FLAG_SYNCREAD;
@@ -229,7 +228,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
 		break;
 	}
 
-	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
+	div = gpmc_calc_divider(min_gpmc_clk_period);
 	gpmc_clk_ns = gpmc_ticks_to_ns(div);
 	if (gpmc_clk_ns < 15) /* >66Mhz */
 		onenand_flags |= ONENAND_FLAG_HF;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 68123d0..d005b3a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -313,7 +313,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 		return -1
 #endif
 
-int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+int gpmc_calc_divider(unsigned int sync_clk)
 {
 	int div;
 	u32 l;
@@ -333,7 +333,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 	int div;
 	u32 l;
 
-	div = gpmc_cs_calc_divider(cs, t->sync_clk);
+	div = gpmc_calc_divider(t->sync_clk);
 	if (div < 0)
 		return -1;
 
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index b7c9ea6..1cafbfd 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -179,7 +179,7 @@ extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
 extern u32 gpmc_cs_read_reg(int cs, int idx);
-extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
+extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 21 06:45:39 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 21 Aug 2012 16:15:39 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad support
In-Reply-To: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1345545940-2232-4-git-send-email-sourav.poddar@ti.com>

Add keypad data node in omap5-evm.

Based on I2C support patch for omap5, which has been
already posted as a different series.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Tested on omap5430 sdp with 3.5 custom kernel.

Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/boot/dts/omap5-evm.dts |   95 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39a..6473983 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -18,3 +18,98 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 };
+
+&i2c5 {
+	clock-frequency = <400000>;
+
+	smsc at 38 {
+		compatible = "smsc";
+		reg = <0x38>;
+		clock = <0x13>;
+		keypad {
+			compatible = "smsc,keypad";
+			interrupt-parent = <&gpio5>;
+			interrupts = <23>; /* gpio line 151 */
+			keypad,num-rows = <8>;
+			keypad,num-columns = <16>;
+			linux,keymap = < 0x20041 /*KEY_F7*/
+					0x30001 /*KEY_ESC*/
+					0x4003e /*KEY_F4*/
+					0x50022 /*KEY_G*/
+					0x70023 /*KEY_H*/
+					0x9009a /*KEY_CYCLEWINDOWS*/
+					0xc000e /*KEY_BACKSPACE*/
+					0xd0057 /*KEY_F11*/
+					0xe009f /*KEY_FORWARD*/
+					0xf006e /*KEY_INSERT*/
+					0x1020036 /*KEY_RIGHTSHIFT*/
+					0x1030011 /*KEY_W*/
+					0x1040010 /*KEY_Q*/
+					0x1050012 /*KEY_E*/
+					0x1070013 /*KEY_R*/
+					0x1080016 /*KEY_U*/
+					0x10c0017 /*KEY_I*/
+					0x10d0067 /*KEY_UP*/
+					0x10e0018 /*KEY_O*/
+					0x10f0019 /*KEY_LEFT*/
+					0x2020003 /*KEY_2*/
+					0x2040004 /*KEY_1*/
+					0x2050005 /*KEY_3*/
+					0x2070008 /*KEY_4*/
+					0x2080009 /*KEY_7*/
+					0x20b0064 /*KEY_8*/
+					0x20c006c /*KEY_RIGHTALT*/
+					0x20d000a /*KEY_DOWN*/
+					0x20e0001 /*KEY_0*/
+					0x20f006a /*KEY_RIGHT*/
+					0x3010061 /*KEY_RIGHTCTRL*/
+					0x302001f /*KEY_S*/
+					0x303001e /*KEY_A*/
+					0x3040020 /*KEY_D*/
+					0x3050021 /*KEY_F*/
+					0x3070024 /*KEY_J*/
+					0x3080025 /*KEY_K*/
+					0x30c001c /*KEY_ENTER*/
+					0x30d0026 /*KEY_L*/
+					0x30e0027 /*KEY_SEMICOLON*/
+					0x400002a /*KEY_LEFTSHIFT*/
+					0x402002d /*KEY_X*/
+					0x403002c /*KEY_Z*/
+					0x404002e /*KEY_C*/
+					0x405002f /*KEY_V/
+					0x4070032 /*KEY_M*/
+					0x4080033 /*KEY_COMMA*/
+					0x40c0039 /*KEY_SPACE*/
+					0x40d0033 /*KEY_DOT*/
+					0x40e0035 /*KEY_SLASH*/
+					0x40f006b /*KEY_END*/
+					0x501001d /*KEY_LEFTCTRL*/
+					0x5020040 /*KEY_F6*/
+					0x503000f /*KEY_TAB*/
+					0x504003d /*KEY_F3*/
+					0x5050014 /*KEY_T*/
+					0x5070015 /*KEY_Y*/
+					0x508001a /*KEY_LEFTBRACE*/
+					0x50d0044 /*KEY_F10*/
+					0x50e001b /*KEY_RIGHTBRACE*/
+					0x50f0066 /*KEY_HOME*/
+					0x602003f /*KEY_F5*/
+					0x604003c /*KEY_F2*/
+					0x6050006 /*KEY_5*/
+					0x60601d0 /*KEY_FN*/
+					0x6070007 /*KEY_6*/
+					0x60a008b /*KEY_MENU*/
+					0x60c002b /*KEY_BACKSLASH*/
+					0x60d0043 /*KEY_F9*/
+					0x7020042 /*KEY_F8*/
+					0x703003a /*KEY_CAPSLOCK*/
+					0x704003b /*KEY_F1*/
+					0x7050030 /*KEY_B*/
+					0x7070031 /*KEY_N*/
+					0x70b0038 /*KEY_LEFTALT*/
+					0x70d0058 /*KEY_F12*/
+					0x70f006f >; /*KEY_DELETE*/
+			linux,input-no-autorepeat;
+		};
+	};
+};
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 21 06:45:38 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 21 Aug 2012 16:15:38 +0530
Subject: [PATCH 2/4] Input: keypad: Add smsc ece1099 keypad driver
In-Reply-To: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>

From: G, Manjunath Kondaiah <manjugk at ti.com>

SMSC ECE1099 is a keyboard scan or GPIO expansion device.The device
supports a keypad scan matrix of 23*8.This driver uses this
device as a keypad driver.

Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/input/keyboard/Kconfig               |   11 +
 drivers/input/keyboard/Makefile              |    1 +
 drivers/input/keyboard/smsc-ece1099-keypad.c |  308 ++++++++++++++++++++++++++
 3 files changed, 320 insertions(+), 0 deletions(-)
 create mode 100644 drivers/input/keyboard/smsc-ece1099-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index c50fa75..2a2d374 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -593,6 +593,17 @@ config KEYBOARD_TWL4030
 	  To compile this driver as a module, choose M here: the
 	  module will be called twl4030_keypad.
 
+config KEYBOARD_SMSC
+       tristate "SMSC ECE1099 keypad support"
+       depends on I2C=y
+       help
+         Say Y here if your board use the smsc keypad controller
+         for omap5 defconfig. It's safe to say enable this
+         even on boards that don't use the keypad controller.
+
+         To compile this driver as a module, choose M here: the
+         module will be called smsc-ece1099-keypad.
+
 config KEYBOARD_XTKBD
 	tristate "XT keyboard"
 	select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 44e7600..0f2aa26 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -52,5 +52,6 @@ obj-$(CONFIG_KEYBOARD_TC3589X)		+= tc3589x-keypad.o
 obj-$(CONFIG_KEYBOARD_TEGRA)		+= tegra-kbc.o
 obj-$(CONFIG_KEYBOARD_TNETV107X)	+= tnetv107x-keypad.o
 obj-$(CONFIG_KEYBOARD_TWL4030)		+= twl4030_keypad.o
+obj-$(CONFIG_KEYBOARD_SMSC)            += smsc-ece1099-keypad.o
 obj-$(CONFIG_KEYBOARD_XTKBD)		+= xtkbd.o
 obj-$(CONFIG_KEYBOARD_W90P910)		+= w90p910_keypad.o
diff --git a/drivers/input/keyboard/smsc-ece1099-keypad.c b/drivers/input/keyboard/smsc-ece1099-keypad.c
new file mode 100644
index 0000000..8a77878
--- /dev/null
+++ b/drivers/input/keyboard/smsc-ece1099-keypad.c
@@ -0,0 +1,308 @@
+/*
+ * SMSC_ECE1099 Keypad driver
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/delay.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/smsc.h>
+#include <linux/of_gpio.h>
+#include <linux/of.h>
+
+#define KEYPRESS_TIME          200
+
+struct smsc_keypad {
+	struct smsc *smsc;
+	struct matrix_keymap_data *keymap_data;
+	unsigned int last_key_state[16];
+	unsigned int last_col;
+	unsigned int last_key_ms[16];
+	unsigned short *keymap;
+	struct i2c_client *client;
+	struct input_dev *input;
+	int rows, cols;
+	int row_shift;
+	bool no_autorepeat;
+	unsigned        irq;
+	struct device *dev;
+};
+
+static void smsc_kp_scan(struct smsc_keypad *kp)
+{
+	struct input_dev *input = kp->input;
+	int i, j;
+	int row, col;
+	int temp, code;
+	unsigned int new_state[16];
+	unsigned int bits_changed;
+	int this_ms;
+
+	smsc_write(kp->dev, SMSC_KP_INT_MASK, 0x00);
+	smsc_write(kp->dev, SMSC_KP_INT_STAT, 0xFF);
+
+	/* Scan for row and column */
+	for (i = 0; i < kp->cols; i++) {
+		smsc_write(kp->dev, SMSC_KP_OUT, SMSC_KSO_EVAL + i);
+		/* Read Row Status */
+		smsc_read(kp->dev, SMSC_KP_IN, &temp);
+		if (temp == 0xFF)
+			continue;
+
+		col = i;
+		for (j = 0; j < kp->rows; j++) {
+			if ((temp & 0x01) != 0x00) {
+				temp = temp >> 1;
+				continue;
+			}
+
+			row = j;
+			new_state[col] =  (1 << row);
+			bits_changed = kp->last_key_state[col] ^ new_state[col];
+			this_ms = jiffies_to_msecs(jiffies);
+			if (bits_changed != 0 || (!bits_changed &&
+					((this_ms - kp->last_key_ms[col]) >= KEYPRESS_TIME))) {
+				code = MATRIX_SCAN_CODE(row, col, kp->row_shift);
+				input_event(input, EV_MSC, MSC_SCAN, code);
+				input_report_key(input, kp->keymap[code], 1);
+				input_report_key(input, kp->keymap[code], 0);
+				kp->last_key_state[col] = new_state[col];
+				if (kp->last_col != col)
+					kp->last_key_state[kp->last_col] = 0;
+				kp->last_key_ms[col] = this_ms;
+			}
+			temp = temp >> 1;
+		}
+	}
+	input_sync(input);
+
+	smsc_write(kp->dev, SMSC_KP_INT_MASK, 0xFF);
+
+	/* Set up Low Power Mode (Wake-up) (0xFB) */
+	smsc_write(kp->dev, SMSC_WKUP_CTRL, SMSC_KP_SET_LOW_PWR);
+
+	/*Enable Keypad Scan (generate interrupt on key press) (0x40)*/
+	smsc_write(kp->dev, SMSC_KP_OUT, SMSC_KSO_ALL_LOW);
+}
+
+static irqreturn_t do_kp_irq(int irq, void *_kp)
+{
+	struct smsc_keypad *kp = _kp;
+	int int_status;
+
+	smsc_read(kp->dev, SMSC_KP_INT_STAT, &int_status);
+	if (int_status)
+		smsc_kp_scan(kp);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_OF
+static int __devinit smsc_keypad_parse_dt(struct device *dev,
+				struct smsc_keypad *kp)
+{
+	struct device_node *np = dev->of_node;
+
+	if (!np) {
+		dev_err(dev, "missing DT data");
+		return -EINVAL;
+	}
+
+	of_property_read_u32(np, "keypad,num-rows", &kp->rows);
+	of_property_read_u32(np, "keypad,num-columns", &kp->cols);
+	if (!kp->rows || !kp->cols) {
+		dev_err(dev, "number of keypad rows/columns not specified\n");
+		return -EINVAL;
+	}
+
+	if (of_get_property(np, "linux,input-no-autorepeat", NULL))
+		kp->no_autorepeat = true;
+
+	return 0;
+}
+#else
+static inline int smsc_keypad_parse_dt(struct device *dev,
+				struct smsc_keypad *kp)
+{
+	return -ENOSYS;
+}
+#endif
+
+static int __devinit
+smsc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
+	struct input_dev *input;
+	struct smsc_keypad *kp;
+	int ret = 0, error;
+	int col, i, max_keys, row_shift;
+	int irq;
+	int addr_start, addr;
+
+	kp = devm_kzalloc(dev, sizeof(*kp), GFP_KERNEL);
+
+	input = input_allocate_device();
+	if (!kp || !input) {
+		error = -ENOMEM;
+		goto err1;
+	}
+
+	error = smsc_keypad_parse_dt(&pdev->dev, kp);
+	if (error)
+		return error;
+
+	/* Get the debug Device */
+	kp->input = input;
+	kp->smsc = smsc;
+	kp->irq = platform_get_irq(pdev, 0);
+	kp->dev = dev;
+
+	for (col = 0; col < 16; col++) {
+		kp->last_key_state[col] = 0;
+		kp->last_key_ms[col] = 0;
+	}
+
+	/* setup input device */
+	 __set_bit(EV_KEY, input->evbit);
+
+	/* Enable auto repeat feature of Linux input subsystem */
+	if (!(kp->no_autorepeat))
+		__set_bit(EV_REP, input->evbit);
+
+	input_set_capability(input, EV_MSC, MSC_SCAN);
+	input->name             = "SMSC Keypad";
+	input->phys             = "smsc_keypad/input0";
+	input->dev.parent       = &pdev->dev;
+	input->id.bustype       = BUS_HOST;
+	input->id.vendor        = 0x0001;
+	input->id.product       = 0x0001;
+	input->id.version       = 0x0003;
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(kp->dev,
+			"Unable to register twl4030 keypad device\n");
+		goto err1;
+	}
+
+	/* Mask all GPIO interrupts (0x37-0x3B) */
+	for (addr = 0x37; addr < 0x3B; addr++)
+		smsc_write(dev, addr, 0);
+
+	/* Set all outputs high (0x05-0x09) */
+	for (addr = 0x05; addr < 0x09; addr++)
+		smsc_write(dev, addr, 0xff);
+
+	/* Clear all GPIO interrupts (0x32-0x36) */
+	for (addr = 0x32; addr < 0x36; addr++)
+		smsc_write(dev, addr, 0xff);
+
+	addr_start = 0x12;
+	for (i = 0; i <= kp->rows; i++) {
+		addr = 0x12 + i;
+		smsc_write(dev, addr, SMSC_KP_KSI);
+	}
+
+	addr_start =  0x1A;
+	for (i = 0; i <= kp->cols; i++) {
+		addr = 0x1A + i;
+		smsc_write(dev, addr, SMSC_KP_KSO);
+	}
+
+	addr = SMSC_KP_INT_STAT;
+	smsc_write(dev, addr, SMSC_KP_SET_HIGH);
+
+	addr = SMSC_WKUP_CTRL;
+	smsc_write(dev, addr, SMSC_KP_SET_LOW_PWR);
+
+	addr = SMSC_KP_OUT;
+	smsc_write(dev, addr, SMSC_KSO_ALL_LOW);
+
+	row_shift = get_count_order(kp->cols);
+	max_keys = kp->rows << row_shift;
+
+	kp->row_shift = row_shift;
+	kp->keymap = kzalloc(max_keys * sizeof(kp->keymap[0]),
+					GFP_KERNEL);
+	if (!kp->keymap) {
+		dev_err(&pdev->dev, "Not enough memory for keymap\n");
+		error = -ENOMEM;
+	}
+
+	matrix_keypad_build_keymap(NULL, NULL, kp->rows,
+			kp->cols, kp->keymap, input);
+
+	/*
+	* This ISR will always execute in kernel thread context because of
+	* the need to access the SMSC over the I2C bus.
+	*/
+	ret = devm_request_threaded_irq(dev, kp->irq, NULL, do_kp_irq,
+			IRQF_TRIGGER_FALLING | IRQF_ONESHOT, pdev->name, kp);
+	if (ret) {
+		dev_dbg(&pdev->dev, "request_irq failed for irq no=%d\n",
+			irq);
+		goto err2;
+	}
+
+	/* Enable smsc keypad interrupts */
+	ret = smsc_write(dev, SMSC_KP_INT_MASK, 0xff);
+	if (ret < 0)
+		goto err2;
+
+	return 0;
+
+err2:
+	input_unregister_device(input);
+	free_irq(kp->irq, NULL);
+err1:
+	input_free_device(input);
+	return ret;
+}
+
+static int smsc_remove(struct platform_device *pdev)
+{
+	struct smsc_keypad *kp = platform_get_drvdata(pdev);
+	free_irq(kp->irq, kp);
+	input_unregister_device(kp->input);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id smsc_keypad_dt_match[] = {
+	{ .compatible = "smsc,keypad" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, smsc_keypad_dt_match);
+#endif
+
+static struct platform_driver smsc_driver = {
+	.driver = {
+		.name	= "smsc-keypad",
+		.of_match_table = of_match_ptr(smsc_keypad_dt_match),
+		.owner  = THIS_MODULE,
+	},
+	.probe		= smsc_probe,
+	.remove		= smsc_remove,
+};
+
+module_platform_driver(smsc_driver);
+
+MODULE_AUTHOR("G Kondaiah Manjunath <manjugk at ti.com>");
+MODULE_DESCRIPTION("SMSC ECE1099 Keypad driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 21 06:45:40 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 21 Aug 2012 16:15:40 +0530
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>

smsc can be used as an gpio io expander device also. So adding
support for configuring smsc pins as a gpio.

Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/gpio/Kconfig        |    7 +
 drivers/gpio/Makefile       |    1 +
 drivers/gpio/gpio-smscece.c |  373 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 381 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpio/gpio-smscece.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..e883929 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -444,6 +444,13 @@ config GPIO_ADP5588_IRQ
 	  Say yes here to enable the adp5588 to be used as an interrupt
 	  controller. It requires the driver to be built in the kernel.
 
+config GPIO_SMSCECE
+	tristate "SMSCECE 1099 I2C GPIO expander"
+	depends on I2C
+	help
+	  This option enables support for 18 GPIOs found
+	  on SMSC ECE 1099 GPIO Expanders.
+
 comment "PCI GPIO expanders:"
 
 config GPIO_CS5535
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..7c803c5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_74X164)	+= gpio-74x164.o
 obj-$(CONFIG_GPIO_AB8500)	+= gpio-ab8500.o
 obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
+obj-$(CONFIG_GPIO_SMSCECE)      += gpio-smscece.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
 obj-$(CONFIG_GPIO_BT8XX)	+= gpio-bt8xx.o
diff --git a/drivers/gpio/gpio-smscece.c b/drivers/gpio/gpio-smscece.c
new file mode 100644
index 0000000..0cb0959
--- /dev/null
+++ b/drivers/gpio/gpio-smscece.c
@@ -0,0 +1,373 @@
+/*
+ * GPIO Chip driver for smsc
+ * SMSC I/O Expander and QWERTY Keypad Controller
+ *
+ * Copyright 2012 Texas Instruments Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/mfd/smsc.h>
+#include <linux/err.h>
+
+struct smsc_gpio {
+	struct device *dev;
+	struct smsc *smsc;
+	struct gpio_chip gpio_chip;
+	struct mutex lock;	/* protect cached dir, dat_out */
+	/* protect serialized access to the interrupt controller bus */
+	struct mutex irq_lock;
+	unsigned gpio_start;
+	int type;
+	int flags;
+	int irq;
+	int irq_base;
+	unsigned int gpio_base;
+	unsigned int dat_out[5];
+	unsigned int dir[5];
+	unsigned int int_lvl[5];
+	unsigned int int_en[5];
+	unsigned int irq_mask[5];
+	unsigned int irq_stat[5];
+};
+
+static int smsc_gpio_get_value(struct gpio_chip *chip, unsigned off)
+{
+	struct smsc_gpio *sg =
+		container_of(chip, struct smsc_gpio, gpio_chip);
+	unsigned int get;
+	return !!(smsc_read(sg->dev,
+		(SMSC_GPIO_DATA_IN_START + SMSC_BANK(off)) & SMSC_BIT(off),
+					&get));
+}
+
+static void smsc_gpio_set_value(struct gpio_chip *chip,
+			unsigned off, int val)
+{
+	unsigned bank, bit;
+	struct smsc_gpio *sg =
+		container_of(chip, struct smsc_gpio, gpio_chip);
+
+	bank = SMSC_BANK(off);
+	bit = SMSC_BIT(off);
+
+	mutex_lock(&sg->lock);
+	if (val)
+		sg->dat_out[bank] |= bit;
+	else
+		sg->dat_out[bank] &= ~bit;
+
+	smsc_write(sg->dev, SMSC_GPIO_DATA_OUT_START + bank,
+			   sg->dat_out[bank]);
+	mutex_unlock(&sg->lock);
+}
+
+static int smsc_gpio_direction_input(struct gpio_chip *chip, unsigned off)
+{
+	unsigned int reg;
+	struct smsc_gpio *sg =
+	    container_of(chip, struct smsc_gpio, gpio_chip);
+	int reg_dir;
+
+	mutex_lock(&sg->lock);
+	reg_dir = SMSC_CFG_START + off;
+	smsc_read(sg->dev, reg_dir, &reg);
+	reg |= SMSC_GPIO_INPUT_LOW;
+	mutex_unlock(&sg->lock);
+
+	return smsc_write(sg->dev, reg_dir, reg);
+}
+
+static int smsc_gpio_direction_output(struct gpio_chip *chip,
+					 unsigned off, int val)
+{
+	unsigned int reg;
+	struct smsc_gpio *sg =
+	    container_of(chip, struct smsc_gpio, gpio_chip);
+	int reg_dir;
+
+	mutex_lock(&sg->lock);
+	reg_dir = SMSC_CFG_START + off;
+	smsc_read(sg->dev, reg_dir, &reg);
+	reg |= SMSC_GPIO_OUTPUT_PP;
+	mutex_unlock(&sg->lock);
+
+	return smsc_write(sg->dev, reg_dir, reg);
+}
+
+static int smsc_gpio_to_irq(struct gpio_chip *chip, unsigned off)
+{
+	struct smsc_gpio *sg =
+		container_of(chip, struct smsc_gpio, gpio_chip);
+	return sg->irq_base + off;
+}
+
+static void smsc_irq_bus_lock(struct irq_data *d)
+{
+	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
+
+	mutex_lock(&sg->irq_lock);
+}
+
+static void smsc_irq_bus_sync_unlock(struct irq_data *d)
+{
+	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
+	int i;
+
+	for (i = 0; i < SMSC_BANK(SMSC_MAXGPIO); i++)
+		if (sg->int_en[i] ^ sg->irq_mask[i]) {
+			sg->int_en[i] = sg->irq_mask[i];
+			smsc_write(sg->dev, SMSC_GPIO_INT_MASK_START + i,
+					   sg->int_en[i]);
+		}
+
+	mutex_unlock(&sg->irq_lock);
+}
+
+static void smsc_irq_mask(struct irq_data *d)
+{
+	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
+	unsigned gpio = d->irq - sg->irq_base;
+
+	sg->irq_mask[SMSC_BANK(gpio)] &= ~SMSC_BIT(gpio);
+}
+
+static void smsc_irq_unmask(struct irq_data *d)
+{
+	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
+	unsigned gpio = d->irq - sg->irq_base;
+
+	sg->irq_mask[SMSC_BANK(gpio)] |= SMSC_BIT(gpio);
+}
+
+static int smsc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
+	uint16_t gpio = d->irq - sg->irq_base;
+	unsigned bank, bit;
+
+	if ((type & IRQ_TYPE_EDGE_BOTH)) {
+		dev_err(sg->dev, "irq %d: unsupported type %d\n",
+			d->irq, type);
+		return -EINVAL;
+	}
+
+	bank = SMSC_BANK(gpio);
+	bit = SMSC_BIT(gpio);
+
+	if (type & IRQ_TYPE_LEVEL_HIGH)
+		sg->int_lvl[bank] |= bit;
+	else if (type & IRQ_TYPE_LEVEL_LOW)
+		sg->int_lvl[bank] &= ~bit;
+	else
+		return -EINVAL;
+
+	smsc_gpio_direction_input(&sg->gpio_chip, gpio);
+	smsc_write(sg->dev, SMSC_CFG_START + gpio,
+			sg->int_lvl[bank]);
+
+	return 0;
+}
+
+static struct irq_chip smsc_irq_chip = {
+	.name			= "smsc",
+	.irq_mask		= smsc_irq_mask,
+	.irq_unmask		= smsc_irq_unmask,
+	.irq_bus_lock		= smsc_irq_bus_lock,
+	.irq_bus_sync_unlock	= smsc_irq_bus_sync_unlock,
+	.irq_set_type		= smsc_irq_set_type,
+};
+
+static int smsc_gpio_read_intstat(struct smsc_gpio *sg,
+				unsigned int *buf, int i)
+{
+	int ret = smsc_read(sg->dev,
+			SMSC_GPIO_INT_STAT_START + i, buf);
+
+	if (ret < 0)
+		dev_err(sg->dev, "Read INT_STAT Error\n");
+
+	return ret;
+}
+
+static irqreturn_t smsc_irq_handler(int irq, void *devid)
+{
+	struct smsc_gpio *sg = devid;
+	unsigned int status, bank, pending;
+	int ret;
+	smsc_read(sg->dev, GRP_INT_STAT, &status);
+
+	if (!(status & SMSC_GPI_INT))
+		goto out;
+
+	for (bank = 0; bank <= SMSC_BANK(SMSC_MAXGPIO);
+		bank++) {
+		pending = sg->irq_stat[bank] & sg->irq_mask[bank];
+		ret = smsc_gpio_read_intstat(sg,
+				&sg->irq_stat[bank], bank);
+		if (ret < 0)
+			memset(&sg->irq_stat[bank], 0,
+				ARRAY_SIZE(sg->irq_stat));
+
+		while (pending) {
+			unsigned long   bit = __ffs(pending);
+			unsigned int    irq;
+
+			pending &= ~BIT(bit);
+			irq = bit + sg->irq_base;
+			handle_nested_irq(irq);
+		}
+	}
+
+out:
+	smsc_write(sg->dev, GRP_INT_STAT, status); /* Status is W1C */
+
+	return IRQ_HANDLED;
+}
+
+static int smsc_irq_setup(struct smsc_gpio *sg)
+{
+	unsigned gpio;
+	int ret;
+
+	mutex_init(&sg->irq_lock);
+
+	for (gpio = 0; gpio < sg->gpio_chip.ngpio; gpio++) {
+		int irq = gpio + sg->irq_base;
+		irq_set_chip_data(irq, sg);
+		irq_set_chip_and_handler(irq, &smsc_irq_chip,
+				handle_level_irq);
+		irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+		set_irq_flags(irq, IRQF_VALID);
+#else
+		irq_set_noprobe(irq);
+#endif
+	}
+
+	ret = request_threaded_irq(sg->irq, NULL,
+			smsc_irq_handler, sg->flags,
+			"smsc_gpio", sg);
+	if (ret) {
+		dev_err(sg->dev, "failed to request irq %d\n",
+			sg->irq);
+	}
+
+	sg->gpio_chip.to_irq = smsc_gpio_to_irq;
+
+	return 0;
+}
+
+static int __devinit smsc_gpio_probe(struct platform_device *pdev)
+{
+	struct smsc_gpio *sg;
+	struct gpio_chip *gc;
+	struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
+	int ret, i, temp;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	int irq_base;
+
+	sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
+	if (sg == NULL) {
+		dev_err(&pdev->dev, "failed to alloc memory\n");
+		return -ENOMEM;
+	}
+
+	sg->irq = platform_get_irq(pdev, 0);
+	if (np) {
+		of_property_read_u32(np, "gpio,base", &temp);
+		of_property_read_u32(np, "flags", &sg->flags);
+	}
+
+	gc = &sg->gpio_chip;
+	gc->direction_input = smsc_gpio_direction_input;
+	gc->direction_output = smsc_gpio_direction_output;
+	gc->get = smsc_gpio_get_value;
+	gc->set = smsc_gpio_set_value;
+	gc->can_sleep = 1;
+
+	gc->base = temp;
+	gc->ngpio = SMSC_MAXGPIO;
+	gc->owner = THIS_MODULE;
+
+	sg->smsc = smsc;
+	sg->dev = dev;
+	mutex_init(&sg->lock);
+
+	for (i = 0; i <= SMSC_BANK(SMSC_MAXGPIO); i++)
+		smsc_read(sg->dev, SMSC_GPIO_DATA_OUT_START + i,
+					&sg->dat_out[i]);
+
+	for (i = 0; i < SMSC_MAXGPIO; i++)
+		smsc_read(sg->dev, SMSC_CFG_START + i, &sg->dir[i]);
+
+	irq_base = irq_alloc_descs(-1, 0, sg->gpio_chip.ngpio, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		dev_err(sg->dev, "Fail to allocate IRQ descs\n");
+		return irq_base;
+	}
+	sg->irq_base = irq_base;
+
+	irq_domain_add_legacy(pdev->dev.of_node, sg->gpio_chip.ngpio,
+		sg->irq_base, 0, &irq_domain_simple_ops, NULL);
+
+	ret = smsc_irq_setup(sg);
+	if (ret)
+		goto err;
+
+	ret = gpiochip_add(&sg->gpio_chip);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	kfree(sg);
+
+	return ret;
+}
+
+static int __devexit smsc_gpio_remove(struct platform_device *pdev)
+{
+	struct smsc_gpio *sg = dev_get_drvdata(&pdev->dev);
+	int ret;
+
+	ret = gpiochip_remove(&sg->gpio_chip);
+	if (ret) {
+		dev_err(&pdev->dev, "gpiochip_remove failed %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id smsc_gpio_dt_match[] = {
+	{ .compatible = "smsc,gpio" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, smsc_gpio_dt_match);
+
+static struct platform_driver smsc_gpio_driver = {
+	.driver = {
+		   .name = "smsc_gpio",
+		   .of_match_table = of_match_ptr(smsc_gpio_dt_match),
+		   },
+	.probe = smsc_gpio_probe,
+	.remove = __devexit_p(smsc_gpio_remove),
+};
+
+module_platform_driver(smsc_gpio_driver);
+
+MODULE_AUTHOR("Sourav Poddar <sourav.poddar at ti.com>");
+MODULE_DESCRIPTION("GPIO SMSC Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From sourav.poddar at ti.com  Tue Aug 21 06:45:37 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Tue, 21 Aug 2012 16:15:37 +0530
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>

smsc ece1099 is a keyboard scan or gpio expansion device.
The patch create keypad and gpio expander child for this
multi function smsc driver.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 Documentation/smsc_ece1099.txt |   56 ++++++++++++++++
 drivers/mfd/Kconfig            |   10 +++
 drivers/mfd/Makefile           |    1 +
 drivers/mfd/smsc-ece1099.c     |  139 ++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/smsc.h       |   89 +++++++++++++++++++++++++
 5 files changed, 295 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/smsc_ece1099.txt
 create mode 100644 drivers/mfd/smsc-ece1099.c
 create mode 100644 include/linux/mfd/smsc.h

diff --git a/Documentation/smsc_ece1099.txt b/Documentation/smsc_ece1099.txt
new file mode 100644
index 0000000..6b492e8
--- /dev/null
+++ b/Documentation/smsc_ece1099.txt
@@ -0,0 +1,56 @@
+What is smsc-ece1099?
+----------------------
+
+The ECE1099 is a 40-Pin 3.3V Keyboard Scan Expansion
+or GPIO Expansion device. The device supports a keyboard
+scan matrix of 23x8. The device is connected to a Master
+via the SMSC BC-Link interface or via the SMBus.
+Keypad scan Input(KSI) and Keypad Scan Output(KSO) signals
+are multiplexed with GPIOs.
+
+Interrupt generation
+--------------------
+
+Interrupts can be generated by an edge detection on a GPIO
+pin or an edge detection on one of the bus interface pins.
+Interrupts can also be detected on the keyboard scan interface.
+The bus interrupt pin (BC_INT# or SMBUS_INT#) is asserted if
+any bit in one of the Interrupt Status registers is 1 and
+the corresponding Interrupt Mask bit is also 1.
+
+In order for software to determine which device is the source
+of an interrupt, it should first read the Group Interrupt Status Register
+to determine which Status register group is a source for the interrupt.
+Software should read both the Status register and the associated Mask register,
+then AND the two values together. Bits that are 1 in the result of the AND
+are active interrupts. Software clears an interrupt by writing a 1 to the
+corresponding bit in the Status register.
+
+Communication Protocol
+----------------------
+
+- SMbus slave Interface
+	The host processor communicates with the ECE1099 device
+	through a series of read/write registers via the SMBus
+	interface. SMBus is a serial communication protocol between
+	a computer host and its peripheral devices. The SMBus data
+	rate is 10KHz minimum to 400 KHz maximum
+
+- Slave Bus Interface
+	The ECE1099 device SMBus implementation is a subset of the
+	SMBus interface to the host. The device is a slave-only SMBus device.
+	The implementation in the device is a subset of SMBus since it
+	only supports four protocols.
+
+	The Write Byte, Read Byte, Send Byte, and Receive Byte protocols are the
+	only valid SMBus protocols for the device.
+
+- BC-LinkTM Interface
+	The BC-Link is a proprietary bus that allows communication
+	between a Master device and a Companion device. The Master
+	device uses this serial bus to read and write registers
+	located on the Companion device. The bus comprises three signals,
+	BC_CLK, BC_DAT and BC_INT#. The Master device always provides the
+	clock, BC_CLK, and the Companion device is the source for an
+	independent asynchronous interrupt signal, BC_INT#. The ECE1099
+	supports BC-Link speeds up to 24MHz.
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d1facef..3b81c17 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -385,6 +385,16 @@ config MFD_T7L66XB
 	help
 	  Support for Toshiba Mobile IO Controller T7L66XB
 
+config MFD_SMSC
+       bool "Support for the SMSC ECE1099 series chips"
+       depends on I2C=y && MFD_CORE && REGMAP_I2C
+       help
+        If you say yes here you get support for the
+        ece1099 chips from SMSC.
+
+        To compile this driver as a module, choose M here: the
+        module will be called smsc.
+
 config MFD_TC6387XB
 	bool "Support Toshiba TC6387XB"
 	depends on ARM && HAVE_CLK
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..f587d91 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_EZX_PCAP)		+= ezx-pcap.o
 obj-$(CONFIG_MCP)		+= mcp-core.o
 obj-$(CONFIG_MCP_SA11X0)	+= mcp-sa11x0.o
 obj-$(CONFIG_MCP_UCB1200)	+= ucb1x00-core.o
+obj-$(CONFIG_MFD_SMSC)        += smsc.o
 obj-$(CONFIG_MCP_UCB1200_TS)	+= ucb1x00-ts.o
 
 ifeq ($(CONFIG_SA1100_ASSABET),y)
diff --git a/drivers/mfd/smsc-ece1099.c b/drivers/mfd/smsc-ece1099.c
new file mode 100644
index 0000000..6ba06b8
--- /dev/null
+++ b/drivers/mfd/smsc-ece1099.c
@@ -0,0 +1,139 @@
+/*
+ * TI SMSC MFD Driver
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Sourav Poddar <sourav.poddar at ti.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  GPL v2.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/workqueue.h>
+#include <linux/irq.h>
+#include <linux/regmap.h>
+#include <linux/err.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/smsc.h>
+#include <linux/of_platform.h>
+
+struct smsc {
+	struct device *dev;
+	struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS];
+	struct regmap *regmap;
+	int clk;
+	/* Stored chip id */
+	int id;
+};
+
+int smsc_read(struct device *child, unsigned int reg,
+	unsigned int *dest)
+{
+	struct smsc     *smsc = dev_get_drvdata(child->parent);
+
+	return regmap_read(smsc->regmap, reg, dest);
+}
+EXPORT_SYMBOL_GPL(smsc_read);
+
+int smsc_write(struct device *child, unsigned int reg,
+	unsigned int value)
+{
+	struct smsc     *smsc = dev_get_drvdata(child->parent);
+
+	return regmap_write(smsc->regmap, reg, value);
+}
+EXPORT_SYMBOL_GPL(smsc_write);
+
+static struct regmap_config smsc_regmap_config = {
+		.reg_bits = 8,
+		.val_bits = 8,
+		.cache_type = REGCACHE_COMPRESSED,
+};
+
+static const struct of_device_id of_smsc_match[] = {
+	{ .compatible = "smsc,ece1099", },
+	{ },
+};
+
+static int smsc_i2c_probe(struct i2c_client *i2c,
+			const struct i2c_device_id *id)
+{
+	struct device_node              *node = i2c->dev.of_node;
+	struct smsc *smsc;
+	int ret = 0;
+
+	smsc = devm_kzalloc(&i2c->dev, sizeof(struct smsc),
+				GFP_KERNEL);
+
+	smsc->regmap = devm_regmap_init_i2c(i2c, &smsc_regmap_config);
+	if (IS_ERR(smsc->regmap)) {
+		ret = PTR_ERR(smsc->regmap);
+		goto err;
+	}
+
+	i2c_set_clientdata(i2c, smsc);
+	smsc->dev = &i2c->dev;
+
+	of_property_read_u32(node, "clock", &smsc->clk);
+
+	regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
+	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+	regmap_read(smsc->regmap, SMSC_DEV_REV, &ret);
+	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+	regmap_read(smsc->regmap, SMSC_VEN_ID_L, &ret);
+	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+	regmap_read(smsc->regmap, SMSC_VEN_ID_H, &ret);
+	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+	ret = regmap_write(smsc->regmap, SMSC_CLK_CTRL, smsc->clk);
+	if (ret)
+		goto err;
+
+	if (node)
+		ret = of_platform_populate(node, NULL, NULL, &i2c->dev);
+
+	return ret;
+
+err:
+	kfree(smsc);
+	return ret;
+}
+
+static int smsc_i2c_remove(struct i2c_client *i2c)
+{
+	return 0;
+}
+
+static const struct i2c_device_id smsc_i2c_id[] = {
+	{ "smsc", 0},
+	{},
+};
+MODULE_DEVICE_TABLE(i2c, smsc_i2c_id);
+
+static struct i2c_driver smsc_i2c_driver = {
+	.driver = {
+		   .name = "smsc",
+		   .of_match_table = of_smsc_match,
+		   .owner = THIS_MODULE,
+	},
+	.probe = smsc_i2c_probe,
+	.remove = smsc_i2c_remove,
+	.id_table = smsc_i2c_id,
+};
+
+module_i2c_driver(smsc_i2c_driver);
+
+MODULE_AUTHOR("Sourav Poddar <sourav.poddar at ti.com>");
+MODULE_DESCRIPTION("SMSC chip multi-function driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/smsc.h b/include/linux/mfd/smsc.h
new file mode 100644
index 0000000..0b048c6
--- /dev/null
+++ b/include/linux/mfd/smsc.h
@@ -0,0 +1,89 @@
+/*
+ * SMSC ECE1099
+ *
+ * Copyright 2012 Texas Instruments Inc.
+ *
+ * Author: Sourav Poddar <sourav.poddar at ti.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_SMSC_H
+#define __LINUX_MFD_SMSC_H
+
+#include <linux/regmap.h>
+
+#define SMSC_ID_ECE1099			1
+#define SMSC_NUM_CLIENTS		2
+
+#define SMSC_BASE_ADDR			0x38
+#define OMAP_GPIO_SMSC_IRQ		151
+
+#define SMSC_MAXGPIO         32
+#define SMSC_BANK(offs)      ((offs) >> 3)
+#define SMSC_BIT(offs)       (1u << ((offs) & 0x7))
+
+struct smsc_gpio;
+struct smsc_keypad;
+
+int smsc_read(struct device *child, unsigned int reg,
+	unsigned int *dest);
+int smsc_write(struct device *child, unsigned int reg,
+	unsigned int value);
+
+/* Registers for SMSC */
+#define SMSC_RESET						0xF5
+#define SMSC_GRP_INT						0xF9
+#define SMSC_CLK_CTRL						0xFA
+#define SMSC_WKUP_CTRL						0xFB
+#define SMSC_DEV_ID						0xFC
+#define SMSC_DEV_REV						0xFD
+#define SMSC_VEN_ID_L						0xFE
+#define SMSC_VEN_ID_H						0xFF
+
+/* CLK VALUE */
+#define SMSC_CLK_VALUE						0x13
+
+/* Registers for function GPIO INPUT */
+#define SMSC_GPIO_DATA_IN_START					0x00
+
+/* Registers for function GPIO OUPUT */
+#define SMSC_GPIO_DATA_OUT_START                                       0x05
+
+/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/
+#define SMSC_GPIO_INPUT_LOW					0x01
+#define SMSC_GPIO_INPUT_RISING					0x09
+#define SMSC_GPIO_INPUT_FALLING					0x11
+#define SMSC_GPIO_INPUT_BOTH_EDGE				0x19
+#define SMSC_GPIO_OUTPUT_PP					0x21
+#define SMSC_GPIO_OUTPUT_OP					0x31
+
+#define GRP_INT_STAT						0xf9
+#define	SMSC_GPI_INT						0x0f
+#define SMSC_CFG_START						0x0A
+
+/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/
+#define SMSC_GPIO_INT_STAT_START                                  0x32
+
+/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/
+#define SMSC_GPIO_INT_MASK_START                               0x37
+
+/* Registers for SMSC function KEYPAD*/
+#define SMSC_KP_OUT						0x40
+#define SMSC_KP_IN						0x41
+#define SMSC_KP_INT_STAT					0x42
+#define SMSC_KP_INT_MASK					0x43
+
+/* Definitions for keypad */
+#define SMSC_KP_KSO           0x70
+#define SMSC_KP_KSI           0x51
+#define SMSC_KSO_ALL_LOW        0x20
+#define SMSC_KP_SET_LOW_PWR        0x0B
+#define SMSC_KP_SET_HIGH           0xFF
+#define SMSC_KSO_EVAL           0x00
+
+#endif /*  __LINUX_MFD_SMSC_H */
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:53 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:53 +0530
Subject: [PATCH v6 08/10] ARM: OMAP2+: onenand: generic timing calculation
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <998aae9cb10d5eb1574dde792954b1cb08c425b6.1345524670.git.afzal@ti.com>

Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-onenand.c |  124 ++++++++++++------------------------
 1 files changed, 41 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index e139e3f..700f9a6 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -49,6 +49,7 @@ static struct platform_device gpmc_onenand_device = {
 
 static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 {
+	struct gpmc_device_timings dev_t;
 	struct gpmc_timings t;
 
 	const int t_cer = 15;
@@ -58,35 +59,22 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 	const int t_aa = 76;
 	const int t_oe = 20;
 	const int t_cez = 20; /* max of t_cez, t_oez */
-	const int t_ds = 30;
 	const int t_wpl = 40;
 	const int t_wph = 30;
 
-	memset(&t, 0, sizeof(t));
-	t.sync_clk = 0;
-	t.cs_on = 0;
-	t.adv_on = 0;
-
-	/* Read */
-	t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
-	t.oe_on  = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
-	t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
-	t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
-	t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
-	t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
-	t.cs_rd_off = t.oe_off;
-	t.rd_cycle  = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
-
-	/* Write */
-	t.adv_wr_off = t.adv_rd_off;
-	t.we_on  = t.oe_on;
-	if (cpu_is_omap34xx()) {
-		t.wr_data_mux_bus = t.we_on;
-		t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
-	}
-	t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
-	t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
-	t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
+	memset(&dev_t, 0, sizeof(dev_t));
+
+	dev_t.mux = true;
+	dev_t.t_avdp_r = dev_t.t_avdp_w = max_t(int, t_avdp, t_cer) * 1000;
+	dev_t.t_aavdh = t_aavdh * 1000;
+	dev_t.t_aa = t_aa * 1000;
+	dev_t.t_ce = t_ce * 1000;
+	dev_t.t_oe = t_oe * 1000;
+	dev_t.t_cez_r = dev_t.t_cez_w = t_cez * 1000;
+	dev_t.t_wpl = t_wpl * 1000;
+	dev_t.t_wph = t_wph * 1000;
+
+	gpmc_calc_timings(&t, &dev_t);
 
 	return t;
 }
@@ -172,16 +160,15 @@ static struct gpmc_timings
 omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
 						int freq)
 {
+	struct gpmc_device_timings dev_t;
 	struct gpmc_timings t;
 	const int t_cer  = 15;
 	const int t_avdp = 12;
 	const int t_cez  = 20; /* max of t_cez, t_oez */
-	const int t_ds   = 30;
 	const int t_wpl  = 40;
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns;
-	int ticks_cez;
+	int div, gpmc_clk_ns;
 
 	if (cfg->flags & ONENAND_SYNC_READ)
 		onenand_flags = ONENAND_FLAG_SYNCREAD;
@@ -248,62 +235,33 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
 		latency = 4;
 
 	/* Set synchronous read timings */
-	memset(&t, 0, sizeof(t));
+	memset(&dev_t, 0, sizeof(dev_t));
 
-	if (div == 1) {
-		t.bool_timings.cs_extra_delay = true;
-		t.bool_timings.adv_extra_delay = true;
-		t.bool_timings.oe_extra_delay = true;
-		t.bool_timings.we_extra_delay = true;
-	}
-
-	t.sync_clk = min_gpmc_clk_period;
-	t.cs_on = 0;
-	t.adv_on = 0;
-	fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
-	fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
-	t.page_burst_access = gpmc_clk_ns;
-
-	/* Read */
-	t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
-	t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
-	/* Force at least 1 clk between AVD High to OE Low */
-	if (t.oe_on <= t.adv_rd_off)
-		t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
-	t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
-	t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
-	t.cs_rd_off = t.oe_off;
-	ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
-	t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
-		     ticks_cez);
-
-	t.clk_activation = fclk_offset_ns;
-
-	/* Write */
-	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-		t.adv_wr_off = t.adv_rd_off;
-		t.we_on  = 0;
-		t.we_off = t.cs_rd_off;
-		t.cs_wr_off = t.cs_rd_off;
-		t.wr_cycle  = t.rd_cycle;
-		if (cpu_is_omap34xx()) {
-			t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
-					gpmc_ps_to_ticks(min_gpmc_clk_period +
-					t_rdyo * 1000));
-			t.wr_access = t.access;
-		}
-	} else {
-		t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
-							t_avdp, t_cer));
-		t.we_on  = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
-		t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
-		t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
-		t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
-		if (cpu_is_omap34xx()) {
-			t.wr_data_mux_bus = t.we_on;
-			t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
-		}
+	dev_t.mux = true;
+	dev_t.sync_read = true;
+	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
+		dev_t.sync_write = true;
+	else {
+		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
+		dev_t.t_wpl = t_wpl * 1000;
+		dev_t.t_wph = t_wph * 1000;
+		dev_t.t_aavdh = t_aavdh * 1000;
 	}
+	dev_t.ce_xdelay = true;
+	dev_t.avd_xdelay = true;
+	dev_t.oe_xdelay = true;
+	dev_t.we_xdelay = true;
+	dev_t.clk = dev_t.t_bacc = min_gpmc_clk_period;
+	dev_t.t_ces = t_ces * 1000;
+	dev_t.t_avds = t_avds * 1000;
+	dev_t.t_avdh = t_avdh * 1000;
+	dev_t.t_ach = t_ach * 1000;
+	dev_t.cyc_iaa = (latency + 1);
+	dev_t.t_cez_r = dev_t.t_cez_w = t_cez * 1000;
+	dev_t.cyc_aavdh_oe = 1;
+	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
+
+	gpmc_calc_timings(&t, &dev_t);
 
 	return t;
 }
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:45:47 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:15:47 +0530
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>

Presently there are three peripherals that gets it timing
by runtime calculation. Those peripherals can work with
frequency scaling that affects gpmc clock. But timing
calculation for them are in different ways.

Here a generic runtime calculation method is proposed. Input
to this function were selected so that they represent timing
variables that are present in peripheral datasheets. Motive
behind this was to achieve DT bindings for the inputs as is.
Even though a few of the tusb6010 timings could not be made
directly related to timings normally found on peripherals,
expressions used were translated to those that could be
justified.

There are possibilities of improving the calculations, like
calculating timing for read & write operations in a more
similar way. Expressions derived here were tested for async
onenand on omap3evm (as vanilla Kernel does not have omap3evm
onenand support, local patch was used). Other peripherals,
tusb6010, smc91x calculations were validated by simulating
on omap3evm.

Regarding "we_on" for onenand async, it was found that even
for muxed address/data, it need not be greater than
"adv_wr_off", but rather could be derived from write setup
time for peripheral from start of access time, hence would
more be in line with peripheral timings. With this method
it was working fine. If it is required in some cases to
have "we_on" same as "wr_data_mux_bus" (i.e. greater than
"adv_wr_off"), another variable could be added to indicate
it. But such a requirement is not expected though.

Whole of this exercise is being done to achieve driver and
DT conversion. If timings could not be calculated in a
peripheral agnostic way, either gpmc driver would have to
be peripheral gnostic or a wrapper arrangement over gpmc
driver would be required.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc.c             |  302 ++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/gpmc.h |   61 +++++++
 2 files changed, 363 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d005b3a..d8e5b08 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -233,6 +233,18 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 	return ticks * gpmc_get_fclk_period() / 1000;
 }
 
+unsigned int gpmc_ticks_to_ps(unsigned int ticks)
+{
+	return ticks * gpmc_get_fclk_period();
+}
+
+unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
+{
+	unsigned long ticks = gpmc_ps_to_ticks(time_ps);
+
+	return ticks * gpmc_get_fclk_period();
+}
+
 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 {
 	u32 l;
@@ -884,6 +896,296 @@ static void __init gpmc_mem_init(void)
 	}
 }
 
+static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
+{
+	u32 temp;
+	int div;
+
+	div = gpmc_calc_divider(sync_clk);
+	temp = gpmc_ps_to_ticks(time_ps);
+	temp = (temp + div - 1) / div;
+	return gpmc_ticks_to_ps(temp * div);
+}
+
+/* can the cycles be avoided ? */
+static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
+				struct gpmc_device_timings *dev_t)
+{
+	bool mux = dev_t->mux;
+	u32 temp;
+
+	/* adv_rd_off */
+	temp = dev_t->t_avdp_r;
+	/* mux check required ? */
+	if (mux) {
+		/* t_avdp not to be required for sync, only added for tusb this
+		 * indirectly necessitates requirement of t_avdp_r & t_avdp_w
+		 * instead of having a single t_avdp
+		 */
+		temp = max_t(u32, temp,	gpmc_t->clk_activation * 1000 +
+							dev_t->t_avdh);
+		temp = max_t(u32,
+			(gpmc_t->adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
+	}
+	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* oe_on */
+	temp = dev_t->t_oeasu; /* remove this ? */
+	if (mux) {
+		temp = max_t(u32, temp,
+			gpmc_t->clk_activation * 1000 + dev_t->t_ach);
+		temp = max_t(u32, temp, (gpmc_t->adv_rd_off +
+				gpmc_ticks_to_ns(dev_t->cyc_aavdh_oe)) * 1000);
+	}
+	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* access */
+	/* any scope for improvement ?, by combining oe_on & clk_activation,
+	 * need to check whether access = clk_activation + round to sync clk ?
+	 */
+	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);
+	temp += gpmc_t->clk_activation * 1000;
+	if (dev_t->cyc_oe)
+		temp = max_t(u32, temp, (gpmc_t->oe_on +
+				gpmc_ticks_to_ns(dev_t->cyc_oe)) * 1000);
+	gpmc_t->access = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ns(1);
+	gpmc_t->cs_rd_off = gpmc_t->oe_off;
+
+	/* rd_cycle */
+	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
+	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
+							gpmc_t->access * 1000;
+	/* barter t_ce_rdyz with t_cez_r ? */
+	if (dev_t->t_ce_rdyz)
+		temp = max_t(u32, temp,
+				gpmc_t->cs_rd_off * 1000 + dev_t->t_ce_rdyz);
+	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	return 0;
+}
+
+static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
+				struct gpmc_device_timings *dev_t)
+{
+	bool mux = dev_t->mux;
+	u32 temp;
+
+	/* adv_wr_off */
+	temp = dev_t->t_avdp_w;
+	if (mux) {
+		temp = max_t(u32, temp,
+			gpmc_t->clk_activation * 1000 + dev_t->t_avdh);
+		temp = max_t(u32,
+			(gpmc_t->adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
+	}
+	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* wr_data_mux_bus */
+	temp = max_t(u32, dev_t->t_weasu,
+			gpmc_t->clk_activation * 1000 + dev_t->t_rdyo);
+	/* shouldn't mux be kept as a whole for wr_data_mux_bus ?,
+	 * and in that case remember to handle we_on properly
+	 */
+	if (mux) {
+		temp = max_t(u32, temp,
+			gpmc_t->adv_wr_off * 1000 + dev_t->t_aavdh);
+		temp = max_t(u32, temp, (gpmc_t->adv_wr_off +
+				gpmc_ticks_to_ns(dev_t->cyc_aavdh_we)) * 1000);
+	}
+	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* we_on */
+	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
+		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu) / 1000;
+	else
+		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
+
+	/* wr_access */
+	/* gpmc_capability check reqd ? , even if not, will not harm */
+	gpmc_t->wr_access = gpmc_t->access;
+
+	/* we_off */
+	temp = gpmc_t->we_on * 1000 + dev_t->t_wpl;
+	temp = max_t(u32, temp,
+			(gpmc_t->wr_access + gpmc_ticks_to_ns(1)) * 1000);
+	temp = max_t(u32, temp,
+		(gpmc_t->we_on + gpmc_ticks_to_ns(dev_t->cyc_wpl)) * 1000);
+	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off * 1000 +
+							dev_t->t_wph) / 1000;
+
+	/* wr_cycle */
+	temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
+	temp += gpmc_t->wr_access * 1000;
+	/* barter t_ce_rdyz with t_cez_w ? */
+	if (dev_t->t_ce_rdyz)
+		temp = max_t(u32, temp,
+				 gpmc_t->cs_wr_off * 1000 + dev_t->t_ce_rdyz);
+	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	return 0;
+}
+
+static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
+				struct gpmc_device_timings *dev_t)
+{
+	bool mux = dev_t->mux;
+	u32 temp;
+
+	/* adv_rd_off */
+	temp = dev_t->t_avdp_r;
+	if (mux)
+		temp = max_t(u32,
+			(gpmc_t->adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
+	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* oe_on */
+	temp = dev_t->t_oeasu;
+	if (mux)
+		temp = max_t(u32, temp,
+			gpmc_t->adv_rd_off * 1000 + dev_t->t_aavdh);
+	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* access */
+	temp = max_t(u32, dev_t->t_iaa, /* remove t_iaa in async ? */
+				gpmc_t->oe_on * 1000 + dev_t->t_oe);
+	temp = max_t(u32, temp,
+				gpmc_t->cs_on * 1000 + dev_t->t_ce);
+	temp = max_t(u32, temp,
+				gpmc_t->adv_on * 1000 + dev_t->t_aa);
+	gpmc_t->access = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ns(1);
+	gpmc_t->cs_rd_off = gpmc_t->oe_off;
+
+	/* rd_cycle */
+	temp = max_t(u32, dev_t->t_rd_cycle,
+			gpmc_t->cs_rd_off * 1000 + dev_t->t_cez_r);
+	temp = max_t(u32, temp,
+			gpmc_t->oe_off * 1000 + dev_t->t_oez);
+	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	return 0;
+}
+
+static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
+				struct gpmc_device_timings *dev_t)
+{
+	bool mux = dev_t->mux;
+	u32 temp;
+
+	/* adv_wr_off */
+	temp = dev_t->t_avdp_w;
+	if (mux)
+		temp = max_t(u32,
+			(gpmc_t->adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
+	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* wr_data_mux_bus */
+	temp = dev_t->t_weasu;
+	if (mux) {
+		temp = max_t(u32, temp,
+			gpmc_t->adv_wr_off * 1000 + dev_t->t_aavdh);
+		temp = max_t(u32, temp, (gpmc_t->adv_wr_off +
+				gpmc_ticks_to_ns(dev_t->cyc_aavdh_we)) * 1000);
+	}
+	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	/* we_on */
+	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
+		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu) / 1000;
+	else
+		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
+
+	/* we_off */
+	temp = gpmc_t->we_on * 1000 + dev_t->t_wpl;
+	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks((gpmc_t->we_off * 1000 +
+				dev_t->t_wph)) / 1000;
+
+	/* wr_cycle */
+	temp = max_t(u32, dev_t->t_wr_cycle,
+				gpmc_t->cs_wr_off * 1000 + dev_t->t_cez_w);
+	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	return 0;
+}
+
+static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
+			struct gpmc_device_timings *dev_t)
+{
+	u32 temp;
+
+	gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
+						gpmc_get_fclk_period();
+
+	gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
+					dev_t->t_bacc,
+					gpmc_t->sync_clk) / 1000;
+
+	temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
+	gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp) / 1000;
+
+	if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
+		return 0;
+
+	if (dev_t->ce_xdelay)
+		gpmc_t->bool_timings.cs_extra_delay = true;
+	if (dev_t->avd_xdelay)
+		gpmc_t->bool_timings.adv_extra_delay = true;
+	if (dev_t->oe_xdelay)
+		gpmc_t->bool_timings.oe_extra_delay = true;
+	if (dev_t->we_xdelay)
+		gpmc_t->bool_timings.we_extra_delay = true;
+
+	return 0;
+}
+
+static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
+			struct gpmc_device_timings *dev_t)
+{
+	u32 temp;
+
+	/* cs_on */
+	gpmc_t->cs_on = gpmc_round_ns_to_ticks(dev_t->t_ceasu / 1000);
+
+	/* adv_on */
+	temp = dev_t->t_avdasu;
+	if (dev_t->t_ce_avd)
+		temp = max_t(u32, temp,
+				gpmc_t->cs_on * 1000 + dev_t->t_ce_avd);
+	gpmc_t->adv_on = gpmc_round_ns_to_ticks(temp / 1000);
+
+	if (dev_t->sync_write || dev_t->sync_read)
+		gpmc_calc_sync_common_timings(gpmc_t, dev_t);
+
+	return 0;
+}
+
+int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
+			struct gpmc_device_timings *dev_t)
+{
+	memset(gpmc_t, 0, sizeof(*gpmc_t));
+
+	gpmc_calc_common_timings(gpmc_t, dev_t);
+
+	if (dev_t->sync_read)
+		gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+	else
+		gpmc_calc_async_read_timings(gpmc_t, dev_t);
+
+	if (dev_t->sync_write)
+		gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+	else
+		gpmc_calc_async_write_timings(gpmc_t, dev_t);
+
+	return 0;
+}
+
 static int __init gpmc_init(void)
 {
 	u32 l;
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 1cafbfd..e59a932 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -152,6 +152,67 @@ struct gpmc_timings {
 	struct gpmc_bool_timings bool_timings;
 };
 
+/* Device timings in picoseconds */
+struct gpmc_device_timings {
+	u32     t_ceasu;	/* address setup to CS valid */
+	u32     t_avdasu;	/* address setup to ADV valid */
+	/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
+	 * of tusb using these timings even for sync whilst
+	 * ideally for adv_rd/(wr)_off it should have considered
+	 * t_avdh instead. This indirectly necessitates r/w
+	 * variations of t_avdp as it is possible to have one
+	 * sync & other async
+	 */
+	u32	t_avdp_r;	/* ADV low time (what about t_cer ?) */
+	u32	t_avdp_w;
+	u32	t_aavdh;	/* address hold time */
+	u32     t_oeasu;	/* address setup to OE valid */
+	u32     t_aa;		/* access time from ADV assertion */
+	u32     t_iaa;		/* initial access time */
+	u32     t_oe;		/* access time from OE assertion */
+	u32     t_ce;		/* access time from CS asertion */
+	u32     t_rd_cycle;	/* read cycle time */
+	u32     t_cez_r;	/* read CS deassertion to high Z */
+	u32     t_cez_w;	/* write CS deassertion to high Z */
+	u32     t_oez;		/* OE deassertion to high Z */
+	u32     t_weasu;	/* address setup to WE valid */
+	u32     t_wpl;		/* write assertion time */
+	u32     t_wph;		/* write deassertion time */
+	u32     t_wr_cycle;	/* write cycle time */
+
+	u32	clk;
+	u32	t_bacc;		/* burst access valid clock to output delay */
+	u32	t_ces;		/* CS setup time to clk */
+	u32	t_avds;		/* ADV setup time to clk */
+	u32	t_avdh;		/* ADV hold time from clk */
+	u32     t_ach;		/* address hold time from clk */
+	u32	t_rdyo;		/* clk to ready valid */
+
+	u32	t_ce_rdyz;	/* XXX: description ?, or use t_cez instead */
+	u32	t_ce_avd;	/* CS on to ADV on delay */
+
+	/* XXX: check the possibility of combining
+	 * cyc_aavhd_oe & cyc_aavdh_we
+	 */
+	u8	cyc_aavdh_oe;
+	u8	cyc_aavdh_we;
+	u8	cyc_oe;
+	u8	cyc_wpl;
+	u32     cyc_iaa;
+
+	bool	mux;		/* address & data muxed */
+	bool	sync_write;	/* synchronous write */
+	bool	sync_read;	/* synchronous read */
+
+	bool	ce_xdelay;
+	bool	avd_xdelay;
+	bool	oe_xdelay;
+	bool	we_xdelay;
+};
+
+extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
+				struct gpmc_device_timings *dev_t);
+
 struct gpmc_nand_regs {
 	void __iomem	*gpmc_status;
 	void __iomem	*gpmc_nand_command;
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:46:00 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:16:00 +0530
Subject: [PATCH v6 09/10] ARM: OMAP2+: smc91x: generic timing calculation
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <3a90c0a44f09b51fb0cbb4c0d15db4743eb36bc5.1345524670.git.afzal@ti.com>

Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-smc91x.c |   43 ++++++++++++++----------------------
 1 files changed, 17 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index ba10c24..43900f9 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -57,6 +57,7 @@ static struct platform_device gpmc_smc91x_device = {
 static int smc91c96_gpmc_retime(void)
 {
 	struct gpmc_timings t;
+	struct gpmc_device_timings dev_t;
 	const int t3 = 10;	/* Figure 12.2 read and 12.4 write */
 	const int t4_r = 20;	/* Figure 12.2 read */
 	const int t4_w = 5;	/* Figure 12.4 write */
@@ -67,32 +68,6 @@ static int smc91c96_gpmc_retime(void)
 	const int t20 = 185;	/* Figure 12.2 read and 12.4 write */
 	u32 l;
 
-	memset(&t, 0, sizeof(t));
-
-	/* Read timings */
-	t.cs_on = 0;
-	t.adv_on = t.cs_on;
-	t.oe_on = t.adv_on + t3;
-	t.access = t.oe_on + t5;
-	t.oe_off = t.access;
-	t.adv_rd_off = t.oe_off + max(t4_r, t6);
-	t.cs_rd_off = t.oe_off;
-	t.rd_cycle = t20 - t.oe_on;
-
-	/* Write timings */
-	t.we_on = t.adv_on + t3;
-
-	if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
-		t.wr_data_mux_bus = t.we_on;
-		t.we_off = t.wr_data_mux_bus + t7;
-	} else
-		t.we_off = t.we_on + t7;
-	if (cpu_is_omap34xx())
-		t.wr_access = t.we_off;
-	t.adv_wr_off = t.we_off + max(t4_w, t8);
-	t.cs_wr_off = t.we_off + t4_w;
-	t.wr_cycle = t20 - t.we_on;
-
 	l = GPMC_CONFIG1_DEVICESIZE_16;
 	if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
 		l |= GPMC_CONFIG1_MUXADDDATA;
@@ -114,6 +89,22 @@ static int smc91c96_gpmc_retime(void)
 	if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
 		return 0;
 
+	memset(&dev_t, 0, sizeof(dev_t));
+
+	dev_t.t_oeasu = t3 * 1000;
+	dev_t.t_oe = t5 * 1000;
+	dev_t.t_cez_r = t4_r * 1000;
+	dev_t.t_oez = t6 * 1000;
+	dev_t.t_rd_cycle = (t20 - t3) * 1000;
+
+	dev_t.t_weasu = t3 * 1000;
+	dev_t.t_wpl = t7 * 1000;
+	dev_t.t_wph = t8 * 1000;
+	dev_t.t_cez_w = t4_w * 1000;
+	dev_t.t_wr_cycle = (t20 - t3) * 1000;
+
+	gpmc_calc_timings(&t, &dev_t);
+
 	return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
 
-- 
1.7.1



From afzal at ti.com  Tue Aug 21 06:46:07 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 21 Aug 2012 16:16:07 +0530
Subject: [PATCH v6 10/10] ARM: OMAP2+: tusb6010: generic timing calculation
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <bc000ac53bb1b3ae1a951bbcf372caf6336d2a19.1345524670.git.afzal@ti.com>

Generic gpmc timing calculation helper is available now, use
it instead of custom timing calculation.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/usb-tusb6010.c |  181 +++++++++---------------------------
 1 files changed, 43 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 7a85ebe..cce1f06 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -26,182 +26,87 @@ static u8		async_cs, sync_cs;
 static unsigned		refclk_psec;
 
 
-/* t2_ps, when quantized to fclk units, must happen no earlier than
- * the clock after after t1_NS.
- *
- * Return a possibly updated value of t2_ps, converted to nsec.
- */
-static unsigned
-next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps)
-{
-	unsigned	t1_ps = t1_NS * 1000;
-	unsigned	t1_f, t2_f;
-
-	if ((t1_ps + fclk_ps) < t2_ps)
-		return t2_ps / 1000;
-
-	t1_f = (t1_ps + fclk_ps - 1) / fclk_ps;
-	t2_f = (t2_ps + fclk_ps - 1) / fclk_ps;
-
-	if (t1_f >= t2_f)
-		t2_f = t1_f + 1;
-
-	return (t2_f * fclk_ps) / 1000;
-}
-
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
-static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps)
+static int tusb_set_async_mode(unsigned sysclk_ps)
 {
+	struct gpmc_device_timings dev_t;
 	struct gpmc_timings	t;
 	unsigned		t_acsnh_advnh = sysclk_ps + 3000;
-	unsigned		tmp;
-
-	memset(&t, 0, sizeof(t));
-
-	/* CS_ON = t_acsnh_acsnl */
-	t.cs_on = 8;
-	/* ADV_ON = t_acsnh_advnh - t_advn */
-	t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps);
-
-	/*
-	 * READ ... from omap2420 TRM fig 12-13
-	 */
-
-	/* ADV_RD_OFF = t_acsnh_advnh */
-	t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps);
-
-	/* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */
-	t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps);
-
-	/* ACCESS = counters continue only after nRDY */
-	tmp = t.oe_on * 1000 + 300;
-	t.access = next_clk(t.oe_on, tmp, fclk_ps);
-
-	/* OE_OFF = after data gets sampled */
-	tmp = t.access * 1000;
-	t.oe_off = next_clk(t.access, tmp, fclk_ps);
-
-	t.cs_rd_off = t.oe_off;
-
-	tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */;
-	t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
-
-	/*
-	 * WRITE ... from omap2420 TRM fig 12-15
-	 */
 
-	/* ADV_WR_OFF = t_acsnh_advnh */
-	t.adv_wr_off = t.adv_rd_off;
+	memset(&dev_t, 0, sizeof(dev_t));
 
-	/* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */
-	t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps);
+	dev_t.mux = true;
 
-	/* WE_OFF = after data gets sampled */
-	tmp = t.we_on * 1000 + 300;
-	t.we_off = next_clk(t.we_on, tmp, fclk_ps);
+	dev_t.t_ceasu = 8 * 1000;
+	dev_t.t_avdasu = t_acsnh_advnh - 7000;
+	dev_t.t_ce_avd = 1000;
+	dev_t.t_avdp_r = t_acsnh_advnh;
+	dev_t.t_oeasu = t_acsnh_advnh + 1000;
+	dev_t.t_oe = 300;
+	dev_t.t_cez_r = dev_t.t_cez_w = 7000;
+	dev_t.t_avdp_w = t_acsnh_advnh;
+	dev_t.t_weasu = t_acsnh_advnh + 1000;
+	dev_t.t_wpl = 300;
+	dev_t.cyc_aavdh_we = 1;
 
-	t.cs_wr_off = t.we_off;
-
-	tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */;
-	t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
+	gpmc_calc_timings(&t, &dev_t);
 
 	return gpmc_cs_set_timings(async_cs, &t);
 }
 
-static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
+static int tusb_set_sync_mode(unsigned sysclk_ps)
 {
+	struct gpmc_device_timings dev_t;
 	struct gpmc_timings	t;
 	unsigned		t_scsnh_advnh = sysclk_ps + 3000;
-	unsigned		tmp;
-
-	memset(&t, 0, sizeof(t));
-	t.cs_on = 8;
-
-	/* ADV_ON = t_acsnh_advnh - t_advn */
-	t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
-
-	/* GPMC_CLK rate = fclk rate / div */
-	t.sync_clk = 11100 /* 11.1 nsec */;
-	tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
-	if (tmp > 4)
-		return -ERANGE;
-	if (tmp == 0)
-		tmp = 1;
-	t.page_burst_access = (fclk_ps * tmp) / 1000;
-
-	/*
-	 * READ ... based on omap2420 TRM fig 12-19, 12-20
-	 */
-
-	/* ADV_RD_OFF = t_scsnh_advnh */
-	t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps);
-
-	/* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */
-	tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps);
-	t.oe_on = next_clk(t.adv_on, tmp, fclk_ps);
-
-	/* ACCESS = number of clock cycles after t_adv_eon */
-	tmp = (t.oe_on * 1000) + (5 * fclk_ps);
-	t.access = next_clk(t.oe_on, tmp, fclk_ps);
-
-	/* OE_OFF = after data gets sampled */
-	tmp = (t.access * 1000) + (1 * fclk_ps);
-	t.oe_off = next_clk(t.access, tmp, fclk_ps);
 
-	t.cs_rd_off = t.oe_off;
-
-	tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */;
-	t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps);
-
-	/*
-	 * WRITE ... based on omap2420 TRM fig 12-21
-	 */
-
-	/* ADV_WR_OFF = t_scsnh_advnh */
-	t.adv_wr_off = t.adv_rd_off;
-
-	/* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */
-	tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps);
-	t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps);
-
-	/* WE_OFF = number of clock cycles after t_adv_wen */
-	tmp = (t.we_on * 1000) + (6 * fclk_ps);
-	t.we_off = next_clk(t.we_on, tmp, fclk_ps);
-
-	t.cs_wr_off = t.we_off;
-
-	tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */;
-	t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps);
-
-	t.clk_activation = gpmc_ticks_to_ns(1);
+	memset(&dev_t, 0, sizeof(dev_t));
+
+	dev_t.mux = true;
+	dev_t.sync_read = true;
+	dev_t.sync_write = true;
+
+	dev_t.clk = 11100;
+	dev_t.t_bacc = 1000;
+	dev_t.t_ces = 1000;
+	dev_t.t_ceasu = 8 * 1000;
+	dev_t.t_avdasu = t_scsnh_advnh - 7000;
+	dev_t.t_ce_avd = 1000;
+	dev_t.t_avdp_r = t_scsnh_advnh;
+	dev_t.cyc_aavdh_oe = 3;
+	dev_t.cyc_oe = 5;
+	dev_t.t_ce_rdyz = 7000;
+	dev_t.t_avdp_w = t_scsnh_advnh;
+	dev_t.cyc_aavdh_we = 3;
+	dev_t.cyc_wpl = 6;
+	dev_t.t_ce_rdyz = 7000;
+
+	gpmc_calc_timings(&t, &dev_t);
 
 	return gpmc_cs_set_timings(sync_cs, &t);
 }
 
-extern unsigned long gpmc_get_fclk_period(void);
-
 /* tusb driver calls this when it changes the chip's clocking */
 int tusb6010_platform_retime(unsigned is_refclk)
 {
 	static const char	error[] =
 		KERN_ERR "tusb6010 %s retime error %d\n";
 
-	unsigned	fclk_ps = gpmc_get_fclk_period();
 	unsigned	sysclk_ps;
 	int		status;
 
-	if (!refclk_psec || fclk_ps == 0)
+	if (!refclk_psec)
 		return -ENODEV;
 
 	sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
 
-	status = tusb_set_async_mode(sysclk_ps, fclk_ps);
+	status = tusb_set_async_mode(sysclk_ps);
 	if (status < 0) {
 		printk(error, "async", status);
 		goto done;
 	}
-	status = tusb_set_sync_mode(sysclk_ps, fclk_ps);
+	status = tusb_set_sync_mode(sysclk_ps);
 	if (status < 0)
 		printk(error, "sync", status);
 done:
-- 
1.7.1



From balbi at ti.com  Tue Aug 21 06:45:49 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:45:49 +0300
Subject: [PATCH 2/4] Input: keypad: Add smsc ece1099 keypad driver
In-Reply-To: <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120821104549.GT10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:15:38PM +0530, Sourav Poddar wrote:
> From: G, Manjunath Kondaiah <manjugk at ti.com>
> 
> SMSC ECE1099 is a keyboard scan or GPIO expansion device.The device
> supports a keypad scan matrix of 23*8.This driver uses this
> device as a keypad driver.
> 
> Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>

looks good. If you just fix my comment on free_irq() below, you can add:

Acked-by: Felipe Balbi <balbi at ti.com>

> +static int __devinit
> +smsc_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
> +	struct input_dev *input;
> +	struct smsc_keypad *kp;
> +	int ret = 0, error;
> +	int col, i, max_keys, row_shift;
> +	int irq;
> +	int addr_start, addr;
> +
> +	kp = devm_kzalloc(dev, sizeof(*kp), GFP_KERNEL);
> +
> +	input = input_allocate_device();
> +	if (!kp || !input) {
> +		error = -ENOMEM;
> +		goto err1;
> +	}
> +
> +	error = smsc_keypad_parse_dt(&pdev->dev, kp);
> +	if (error)
> +		return error;
> +
> +	/* Get the debug Device */
> +	kp->input = input;
> +	kp->smsc = smsc;
> +	kp->irq = platform_get_irq(pdev, 0);
> +	kp->dev = dev;
> +
> +	for (col = 0; col < 16; col++) {
> +		kp->last_key_state[col] = 0;
> +		kp->last_key_ms[col] = 0;
> +	}
> +
> +	/* setup input device */
> +	 __set_bit(EV_KEY, input->evbit);
> +
> +	/* Enable auto repeat feature of Linux input subsystem */
> +	if (!(kp->no_autorepeat))
> +		__set_bit(EV_REP, input->evbit);
> +
> +	input_set_capability(input, EV_MSC, MSC_SCAN);
> +	input->name             = "SMSC Keypad";
> +	input->phys             = "smsc_keypad/input0";
> +	input->dev.parent       = &pdev->dev;
> +	input->id.bustype       = BUS_HOST;
> +	input->id.vendor        = 0x0001;
> +	input->id.product       = 0x0001;
> +	input->id.version       = 0x0003;
> +
> +	error = input_register_device(input);
> +	if (error) {
> +		dev_err(kp->dev,
> +			"Unable to register twl4030 keypad device\n");
> +		goto err1;
> +	}
> +
> +	/* Mask all GPIO interrupts (0x37-0x3B) */
> +	for (addr = 0x37; addr < 0x3B; addr++)
> +		smsc_write(dev, addr, 0);
> +
> +	/* Set all outputs high (0x05-0x09) */
> +	for (addr = 0x05; addr < 0x09; addr++)
> +		smsc_write(dev, addr, 0xff);
> +
> +	/* Clear all GPIO interrupts (0x32-0x36) */
> +	for (addr = 0x32; addr < 0x36; addr++)
> +		smsc_write(dev, addr, 0xff);
> +
> +	addr_start = 0x12;
> +	for (i = 0; i <= kp->rows; i++) {
> +		addr = 0x12 + i;
> +		smsc_write(dev, addr, SMSC_KP_KSI);
> +	}
> +
> +	addr_start =  0x1A;
> +	for (i = 0; i <= kp->cols; i++) {
> +		addr = 0x1A + i;
> +		smsc_write(dev, addr, SMSC_KP_KSO);
> +	}
> +
> +	addr = SMSC_KP_INT_STAT;
> +	smsc_write(dev, addr, SMSC_KP_SET_HIGH);
> +
> +	addr = SMSC_WKUP_CTRL;
> +	smsc_write(dev, addr, SMSC_KP_SET_LOW_PWR);
> +
> +	addr = SMSC_KP_OUT;
> +	smsc_write(dev, addr, SMSC_KSO_ALL_LOW);
> +
> +	row_shift = get_count_order(kp->cols);
> +	max_keys = kp->rows << row_shift;
> +
> +	kp->row_shift = row_shift;
> +	kp->keymap = kzalloc(max_keys * sizeof(kp->keymap[0]),
> +					GFP_KERNEL);
> +	if (!kp->keymap) {
> +		dev_err(&pdev->dev, "Not enough memory for keymap\n");
> +		error = -ENOMEM;
> +	}
> +
> +	matrix_keypad_build_keymap(NULL, NULL, kp->rows,
> +			kp->cols, kp->keymap, input);
> +
> +	/*
> +	* This ISR will always execute in kernel thread context because of
> +	* the need to access the SMSC over the I2C bus.
> +	*/
> +	ret = devm_request_threaded_irq(dev, kp->irq, NULL, do_kp_irq,
> +			IRQF_TRIGGER_FALLING | IRQF_ONESHOT, pdev->name, kp);
> +	if (ret) {
> +		dev_dbg(&pdev->dev, "request_irq failed for irq no=%d\n",
> +			irq);
> +		goto err2;
> +	}
> +
> +	/* Enable smsc keypad interrupts */
> +	ret = smsc_write(dev, SMSC_KP_INT_MASK, 0xff);
> +	if (ret < 0)
> +		goto err2;
> +
> +	return 0;
> +
> +err2:
> +	input_unregister_device(input);
> +	free_irq(kp->irq, NULL);

you're using devm_request_threaded_irq, this is unnecessary

> +err1:
> +	input_free_device(input);
> +	return ret;
> +}
> +
> +static int smsc_remove(struct platform_device *pdev)
> +{
> +	struct smsc_keypad *kp = platform_get_drvdata(pdev);
> +	free_irq(kp->irq, kp);

ditto.


-- 
balbi
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From balbi at ti.com  Tue Aug 21 06:46:48 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:46:48 +0300
Subject: [PATCH 2/4] Input: keypad: Add smsc ece1099 keypad driver
In-Reply-To: <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120821104647.GU10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 04:15:38PM +0530, Sourav Poddar wrote:
> +static struct platform_driver smsc_driver = {
> +	.driver = {
> +		.name	= "smsc-keypad",
> +		.of_match_table = of_match_ptr(smsc_keypad_dt_match),
> +		.owner  = THIS_MODULE,
> +	},
> +	.probe		= smsc_probe,
> +	.remove		= smsc_remove,

one extra comment which I forgot. You probably should put your remove on
__devexit and add __devexit_p(smsc_remove) here.

-- 
balbi
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From balbi at ti.com  Tue Aug 21 06:47:45 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:47:45 +0300
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad support
In-Reply-To: <1345545940-2232-4-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-4-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120821104744.GV10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:15:39PM +0530, Sourav Poddar wrote:
> Add keypad data node in omap5-evm.
> 
> Based on I2C support patch for omap5, which has been
> already posted as a different series.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Tested on omap5430 sdp with 3.5 custom kernel.
> 
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>

after fixing my only comment below, you can add my:

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/boot/dts/omap5-evm.dts |   95 +++++++++++++++++++++++++++++++++++++++
>  1 files changed, 95 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
> index 200c39a..6473983 100644
> --- a/arch/arm/boot/dts/omap5-evm.dts
> +++ b/arch/arm/boot/dts/omap5-evm.dts
> @@ -18,3 +18,98 @@
>  		reg = <0x80000000 0x40000000>; /* 1 GB */
>  	};
>  };
> +
> +&i2c5 {
> +	clock-frequency = <400000>;
> +
> +	smsc at 38 {
> +		compatible = "smsc";
> +		reg = <0x38>;
> +		clock = <0x13>;
> +		keypad {
> +			compatible = "smsc,keypad";
> +			interrupt-parent = <&gpio5>;
> +			interrupts = <23>; /* gpio line 151 */
> +			keypad,num-rows = <8>;
> +			keypad,num-columns = <16>;
> +			linux,keymap = < 0x20041 /*KEY_F7*/

please add spaces around /* and */ so it's easier to read. Ditto to all
others.

-- 
balbi
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From lee.jones at linaro.org  Tue Aug 21 06:54:14 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 11:54:14 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821095026.GU26991@opensource.wolfsonmicro.com>
References: <201208140942.54773.arnd@arndb.de>
 <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
Message-ID: <20120821105413.GD26899@gmail.com>

On Tue, Aug 21, 2012 at 10:50:27AM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 09:56:19AM +0100, Lee Jones wrote:
> 
> > Wherever we do this from to be able to obtain the IRQ domain pointer, 
> > which is where I'm currently struggling. Our options are:
> 
> > - If we're only talking MFD here, we can handle this stuff in the MFD
> > core, but we need more information. The IRQ domain subsystem only allows
> > domain look-up via a Device Tree node, so we need to get our hands on
> 
> What makes you say this?  This is just a convenience for finding a
> domain, irqdomains are *completely* indepentant of device tree.

How can you say that? I think you mean _can_ be independent of DT. If
that's what you mean then yes, that's true. All I'm saying is we need
another way to get hold of the domain, because the only way to obtain
it without having direct access is via a device node.
 
> > the domain another way in the case of non-DT enabled devices. Either we
> > add another parameter to mfd_add_device(irq_domain, ...), or we
> > standardise the 'irq_domain' variable name and use:
> >         irq_domain = container_of(parent, struct irq_domain, irq_domain);
> 
> Passing the domain into mfd seems like the obvious solution here - it's
> exactly what we currently do for legacy stuff (where we pass in the irq
> base), ideally what we'd end up with over time is that we could just
> remove the irq_base parameter entirely as everything would in time be
> moved over to using irqdomains.

Right. That's fine (and easy) then. You threw me when you said you wanted
it handled higher-up in the framework, as I didn't see how we could do 
this in the irqdomain itself.
 
> > - I know that you have interest in pushing the functionality into the
> > IRQ domain subsystem, but I'm struggling to see how. It's calling into
> > the IRQ domain where we're seeing issues in the first place, specifically
> > irq_create_mapping(). How about if we passed 'irq_domain' as a parameter
> > when requesting the IRQ? That way we can pass the correct IRQ without
> > worry of conversion. If 'irq_domain' is !NULL the IRQ management subsystem
> > can do the necessary conversions. If 'irq_domain' is NULL it continues to
> > use the requested IRQ as a virq.
> 
> This is totally orthogonal to doing the mapping in the MFD subsystem
> which is the issue here.

Again, I only mentioned this because you said you wanted it to be handled
by the irqdomain.

I'll code up the second suggestion now.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From anilkumar at ti.com  Tue Aug 21 06:57:20 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 21 Aug 2012 10:57:20 +0000
Subject: [PATCH v2 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <20120820200715.GT26991@opensource.wolfsonmicro.com>
References: <1343110735-10640-1-git-send-email-anilkumar@ti.com>
 <1343110735-10640-4-git-send-email-anilkumar@ti.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA1293E@DBDE01.ent.ti.com>
 <20120815125338.GA13544@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13118@DBDE01.ent.ti.com>
 <20120815165431.GF15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA13D18@DBDE01.ent.ti.com>
 <20120816140056.GK15365@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA19A81@DBDE01.ent.ti.com>
 <20120820200715.GT26991@opensource.wolfsonmicro.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA1AC7D@DBDE01.ent.ti.com>

Hi Mark,

On Tue, Aug 21, 2012 at 01:37:15, Mark Brown wrote:
> On Mon, Aug 20, 2012 at 06:27:01AM +0000, AnilKumar, Chimata wrote:
> > On Thu, Aug 16, 2012 at 19:30:56, Mark Brown wrote:
> 
> > > Why does this mean you need multiple regulators?  A single regulator can
> > > of course supply multiple devices.
> 
> > I got your point but tps65910 driver is failing if we add single fixed
> > regulator. Solution is driver needs to change or add multiple fixed
> > regulators.
> 
> No, really.  One regulator can supply many things, not being a.
> 
> > vrtc:
> > tps65910 0-002d: Failed to find supply vcc7
> > tps65910 0-002d: failed to register tps65910-pmic regulator
> 
> So you've specified a whole bunch of supplies and this one individual
> supply is not matching (and it's not the first...).  You should
> investigate what's gone wrong there rather than bodging around the
> problem.  I can't immediately say anything much based on the information
> you've given.
> 

Sorry for the noise in this issue, I found the root cause. I
was defining the supply names like this which is wrong.

&tps {
        regulators {
                vcc1-supply = <&vcc5v_supply>;
                vcc2-supply = <&vcc5v_supply>;
                vcc3-supply = <&vcc5v_supply>;
                vcc4-supply = <&vcc5v_supply>;
                vcc5-supply = <&vcc5v_supply>;
                vcc6-supply = <&vcc5v_supply>;
                vcc7-supply = <&vcc5v_supply>;
                vccio-supply = <&vcc5v_supply>;

                vrtc_reg: regulator at 0 { /* vrtc input is vcc7 */
                        regulator-always-on;
                };

                ... 
                ...
        };
};

This was suppose to be

&tps {
        vcc1-supply = <&vcc5v_supply>;
        vcc2-supply = <&vcc5v_supply>;
        vcc3-supply = <&vcc5v_supply>;
        vcc4-supply = <&vcc5v_supply>;
        vcc5-supply = <&vcc5v_supply>;
        vcc6-supply = <&vcc5v_supply>;
        vcc7-supply = <&vcc5v_supply>;
        vccio-supply = <&vcc5v_supply>;

        regulators {

                vrtc_reg: regulator at 0 { /* vrtc input is vcc7 */
                        regulator-always-on;
                };

                ... 
                ...
        };
};

Thanks for your continuous feedback.

Thanks
AnilKumar


From balbi at ti.com  Tue Aug 21 06:53:34 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:53:34 +0300
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120821105333.GW10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 04:15:40PM +0530, Sourav Poddar wrote:
> smsc can be used as an gpio io expander device also. So adding
> support for configuring smsc pins as a gpio.
> 
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  drivers/gpio/Kconfig        |    7 +
>  drivers/gpio/Makefile       |    1 +
>  drivers/gpio/gpio-smscece.c |  373 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 381 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/gpio/gpio-smscece.c
> 
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index b16c8a7..e883929 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -444,6 +444,13 @@ config GPIO_ADP5588_IRQ
>  	  Say yes here to enable the adp5588 to be used as an interrupt
>  	  controller. It requires the driver to be built in the kernel.
>  
> +config GPIO_SMSCECE
> +	tristate "SMSCECE 1099 I2C GPIO expander"
> +	depends on I2C
> +	help
> +	  This option enables support for 18 GPIOs found
> +	  on SMSC ECE 1099 GPIO Expanders.
> +
>  comment "PCI GPIO expanders:"
>  
>  config GPIO_CS5535
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 153cace..7c803c5 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_74X164)	+= gpio-74x164.o
>  obj-$(CONFIG_GPIO_AB8500)	+= gpio-ab8500.o
>  obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
>  obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
> +obj-$(CONFIG_GPIO_SMSCECE)      += gpio-smscece.o
>  obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
>  obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
>  obj-$(CONFIG_GPIO_BT8XX)	+= gpio-bt8xx.o
> diff --git a/drivers/gpio/gpio-smscece.c b/drivers/gpio/gpio-smscece.c
> new file mode 100644
> index 0000000..0cb0959
> --- /dev/null
> +++ b/drivers/gpio/gpio-smscece.c
> @@ -0,0 +1,373 @@
> +/*
> + * GPIO Chip driver for smsc
> + * SMSC I/O Expander and QWERTY Keypad Controller
> + *
> + * Copyright 2012 Texas Instruments Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/slab.h>
> +#include <linux/init.h>
> +#include <linux/i2c.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irq.h>
> +#include <linux/mfd/smsc.h>
> +#include <linux/err.h>
> +
> +struct smsc_gpio {
> +	struct device *dev;
> +	struct smsc *smsc;
> +	struct gpio_chip gpio_chip;
> +	struct mutex lock;	/* protect cached dir, dat_out */
> +	/* protect serialized access to the interrupt controller bus */
> +	struct mutex irq_lock;
> +	unsigned gpio_start;
> +	int type;
> +	int flags;
> +	int irq;
> +	int irq_base;
> +	unsigned int gpio_base;
> +	unsigned int dat_out[5];
> +	unsigned int dir[5];
> +	unsigned int int_lvl[5];
> +	unsigned int int_en[5];
> +	unsigned int irq_mask[5];
> +	unsigned int irq_stat[5];
> +};
> +
> +static int smsc_gpio_get_value(struct gpio_chip *chip, unsigned off)
> +{
> +	struct smsc_gpio *sg =
> +		container_of(chip, struct smsc_gpio, gpio_chip);
> +	unsigned int get;
> +	return !!(smsc_read(sg->dev,
> +		(SMSC_GPIO_DATA_IN_START + SMSC_BANK(off)) & SMSC_BIT(off),
> +					&get));
> +}
> +
> +static void smsc_gpio_set_value(struct gpio_chip *chip,
> +			unsigned off, int val)
> +{
> +	unsigned bank, bit;
> +	struct smsc_gpio *sg =
> +		container_of(chip, struct smsc_gpio, gpio_chip);
> +
> +	bank = SMSC_BANK(off);
> +	bit = SMSC_BIT(off);
> +
> +	mutex_lock(&sg->lock);
> +	if (val)
> +		sg->dat_out[bank] |= bit;
> +	else
> +		sg->dat_out[bank] &= ~bit;
> +
> +	smsc_write(sg->dev, SMSC_GPIO_DATA_OUT_START + bank,
> +			   sg->dat_out[bank]);
> +	mutex_unlock(&sg->lock);
> +}
> +
> +static int smsc_gpio_direction_input(struct gpio_chip *chip, unsigned off)
> +{
> +	unsigned int reg;
> +	struct smsc_gpio *sg =
> +	    container_of(chip, struct smsc_gpio, gpio_chip);
> +	int reg_dir;
> +
> +	mutex_lock(&sg->lock);
> +	reg_dir = SMSC_CFG_START + off;
> +	smsc_read(sg->dev, reg_dir, &reg);
> +	reg |= SMSC_GPIO_INPUT_LOW;
> +	mutex_unlock(&sg->lock);
> +
> +	return smsc_write(sg->dev, reg_dir, reg);
> +}
> +
> +static int smsc_gpio_direction_output(struct gpio_chip *chip,
> +					 unsigned off, int val)
> +{
> +	unsigned int reg;
> +	struct smsc_gpio *sg =
> +	    container_of(chip, struct smsc_gpio, gpio_chip);
> +	int reg_dir;
> +
> +	mutex_lock(&sg->lock);
> +	reg_dir = SMSC_CFG_START + off;
> +	smsc_read(sg->dev, reg_dir, &reg);
> +	reg |= SMSC_GPIO_OUTPUT_PP;
> +	mutex_unlock(&sg->lock);
> +
> +	return smsc_write(sg->dev, reg_dir, reg);
> +}
> +
> +static int smsc_gpio_to_irq(struct gpio_chip *chip, unsigned off)
> +{
> +	struct smsc_gpio *sg =
> +		container_of(chip, struct smsc_gpio, gpio_chip);
> +	return sg->irq_base + off;
> +}
> +
> +static void smsc_irq_bus_lock(struct irq_data *d)
> +{
> +	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
> +
> +	mutex_lock(&sg->irq_lock);
> +}
> +
> +static void smsc_irq_bus_sync_unlock(struct irq_data *d)
> +{
> +	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
> +	int i;
> +
> +	for (i = 0; i < SMSC_BANK(SMSC_MAXGPIO); i++)
> +		if (sg->int_en[i] ^ sg->irq_mask[i]) {
> +			sg->int_en[i] = sg->irq_mask[i];
> +			smsc_write(sg->dev, SMSC_GPIO_INT_MASK_START + i,
> +					   sg->int_en[i]);
> +		}
> +
> +	mutex_unlock(&sg->irq_lock);
> +}
> +
> +static void smsc_irq_mask(struct irq_data *d)
> +{
> +	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
> +	unsigned gpio = d->irq - sg->irq_base;
> +
> +	sg->irq_mask[SMSC_BANK(gpio)] &= ~SMSC_BIT(gpio);
> +}
> +
> +static void smsc_irq_unmask(struct irq_data *d)
> +{
> +	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
> +	unsigned gpio = d->irq - sg->irq_base;
> +
> +	sg->irq_mask[SMSC_BANK(gpio)] |= SMSC_BIT(gpio);
> +}
> +
> +static int smsc_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
> +	uint16_t gpio = d->irq - sg->irq_base;
> +	unsigned bank, bit;
> +
> +	if ((type & IRQ_TYPE_EDGE_BOTH)) {
> +		dev_err(sg->dev, "irq %d: unsupported type %d\n",
> +			d->irq, type);
> +		return -EINVAL;
> +	}
> +
> +	bank = SMSC_BANK(gpio);
> +	bit = SMSC_BIT(gpio);
> +
> +	if (type & IRQ_TYPE_LEVEL_HIGH)
> +		sg->int_lvl[bank] |= bit;
> +	else if (type & IRQ_TYPE_LEVEL_LOW)
> +		sg->int_lvl[bank] &= ~bit;
> +	else
> +		return -EINVAL;

this looks wrong. You could have a user who wants to trigger on both
HIGH and LOW levels, no ?

> +	smsc_gpio_direction_input(&sg->gpio_chip, gpio);
> +	smsc_write(sg->dev, SMSC_CFG_START + gpio,
> +			sg->int_lvl[bank]);
> +
> +	return 0;
> +}
> +
> +static struct irq_chip smsc_irq_chip = {
> +	.name			= "smsc",
> +	.irq_mask		= smsc_irq_mask,
> +	.irq_unmask		= smsc_irq_unmask,
> +	.irq_bus_lock		= smsc_irq_bus_lock,
> +	.irq_bus_sync_unlock	= smsc_irq_bus_sync_unlock,
> +	.irq_set_type		= smsc_irq_set_type,
> +};
> +
> +static int smsc_gpio_read_intstat(struct smsc_gpio *sg,
> +				unsigned int *buf, int i)
> +{
> +	int ret = smsc_read(sg->dev,
> +			SMSC_GPIO_INT_STAT_START + i, buf);
> +
> +	if (ret < 0)
> +		dev_err(sg->dev, "Read INT_STAT Error\n");
> +
> +	return ret;
> +}
> +
> +static irqreturn_t smsc_irq_handler(int irq, void *devid)
> +{
> +	struct smsc_gpio *sg = devid;
> +	unsigned int status, bank, pending;
> +	int ret;
> +	smsc_read(sg->dev, GRP_INT_STAT, &status);
> +
> +	if (!(status & SMSC_GPI_INT))
> +		goto out;
> +
> +	for (bank = 0; bank <= SMSC_BANK(SMSC_MAXGPIO);
> +		bank++) {
> +		pending = sg->irq_stat[bank] & sg->irq_mask[bank];
> +		ret = smsc_gpio_read_intstat(sg,
> +				&sg->irq_stat[bank], bank);
> +		if (ret < 0)
> +			memset(&sg->irq_stat[bank], 0,
> +				ARRAY_SIZE(sg->irq_stat));
> +
> +		while (pending) {
> +			unsigned long   bit = __ffs(pending);
> +			unsigned int    irq;
> +
> +			pending &= ~BIT(bit);
> +			irq = bit + sg->irq_base;
> +			handle_nested_irq(irq);
> +		}
> +	}
> +
> +out:
> +	smsc_write(sg->dev, GRP_INT_STAT, status); /* Status is W1C */
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int smsc_irq_setup(struct smsc_gpio *sg)
> +{
> +	unsigned gpio;
> +	int ret;
> +
> +	mutex_init(&sg->irq_lock);
> +
> +	for (gpio = 0; gpio < sg->gpio_chip.ngpio; gpio++) {
> +		int irq = gpio + sg->irq_base;
> +		irq_set_chip_data(irq, sg);
> +		irq_set_chip_and_handler(irq, &smsc_irq_chip,
> +				handle_level_irq);
> +		irq_set_nested_thread(irq, 1);
> +#ifdef CONFIG_ARM
> +		set_irq_flags(irq, IRQF_VALID);
> +#else
> +		irq_set_noprobe(irq);
> +#endif
> +	}
> +
> +	ret = request_threaded_irq(sg->irq, NULL,
> +			smsc_irq_handler, sg->flags,
> +			"smsc_gpio", sg);

would be nice to stick to devm_request_threaded_irq() like on the other
patch.

> +	if (ret) {
> +		dev_err(sg->dev, "failed to request irq %d\n",
> +			sg->irq);
> +	}
> +
> +	sg->gpio_chip.to_irq = smsc_gpio_to_irq;
> +
> +	return 0;
> +}
> +
> +static int __devinit smsc_gpio_probe(struct platform_device *pdev)
> +{
> +	struct smsc_gpio *sg;
> +	struct gpio_chip *gc;
> +	struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
> +	int ret, i, temp;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	int irq_base;
> +
> +	sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
> +	if (sg == NULL) {
> +		dev_err(&pdev->dev, "failed to alloc memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	sg->irq = platform_get_irq(pdev, 0);
> +	if (np) {
> +		of_property_read_u32(np, "gpio,base", &temp);
> +		of_property_read_u32(np, "flags", &sg->flags);
> +	}
> +
> +	gc = &sg->gpio_chip;
> +	gc->direction_input = smsc_gpio_direction_input;
> +	gc->direction_output = smsc_gpio_direction_output;
> +	gc->get = smsc_gpio_get_value;
> +	gc->set = smsc_gpio_set_value;
> +	gc->can_sleep = 1;
> +
> +	gc->base = temp;
> +	gc->ngpio = SMSC_MAXGPIO;
> +	gc->owner = THIS_MODULE;
> +
> +	sg->smsc = smsc;
> +	sg->dev = dev;
> +	mutex_init(&sg->lock);
> +
> +	for (i = 0; i <= SMSC_BANK(SMSC_MAXGPIO); i++)
> +		smsc_read(sg->dev, SMSC_GPIO_DATA_OUT_START + i,
> +					&sg->dat_out[i]);
> +
> +	for (i = 0; i < SMSC_MAXGPIO; i++)
> +		smsc_read(sg->dev, SMSC_CFG_START + i, &sg->dir[i]);
> +
> +	irq_base = irq_alloc_descs(-1, 0, sg->gpio_chip.ngpio, 0);
> +	if (IS_ERR_VALUE(irq_base)) {
> +		dev_err(sg->dev, "Fail to allocate IRQ descs\n");
> +		return irq_base;
> +	}
> +	sg->irq_base = irq_base;
> +
> +	irq_domain_add_legacy(pdev->dev.of_node, sg->gpio_chip.ngpio,
> +		sg->irq_base, 0, &irq_domain_simple_ops, NULL);
> +
> +	ret = smsc_irq_setup(sg);
> +	if (ret)
> +		goto err;
> +
> +	ret = gpiochip_add(&sg->gpio_chip);
> +	if (ret)
> +		goto err;
> +
> +	return 0;
> +
> +err:
> +	kfree(sg);

using devm_kzalloc(), not needed to free.

> +
> +	return ret;
> +}
> +
> +static int __devexit smsc_gpio_remove(struct platform_device *pdev)
> +{
> +	struct smsc_gpio *sg = dev_get_drvdata(&pdev->dev);
> +	int ret;
> +
> +	ret = gpiochip_remove(&sg->gpio_chip);
> +	if (ret) {
> +		dev_err(&pdev->dev, "gpiochip_remove failed %d\n", ret);
> +		return ret;
> +	}

this will leak the irq (please move to devm_request_threaded_irq).

It's also leaking irq_descs and irq_domain, you need to free those
resources by calling irq_domain_remove and irq_free_descs.

-- 
balbi
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From balbi at ti.com  Tue Aug 21 06:57:03 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 13:57:03 +0300
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-11-git-send-email-balbi@ti.com>
 <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>
Message-ID: <20120821105702.GX10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:12:11PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> > Everytime we're done using our TTY, we want
> > the pm timer to be reinitilized. By sticking
> > to pm_runtime_pm_autosuspend() we make sure
> > that this will always be the case.
> >
> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> > ---
> >  drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
> >  1 file changed, 22 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> > index 6ea24c5..458d77c 100644
> > --- a/drivers/tty/serial/omap-serial.c
> > +++ b/drivers/tty/serial/omap-serial.c
> > @@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
> >         pm_runtime_get_sync(up->dev);
> >         up->ier |= UART_IER_MSI;
> >         serial_out(up, UART_IER, up->ier);
> > -       pm_runtime_put(up->dev);
> > +       pm_runtime_mark_last_busy(up->dev);
> > +       pm_runtime_put_autosuspend(up->dev);
> >  }
> >
> Can you please expand the change-log a bit ?
> Didn't follow the time re-init part completely.

It's really just a micro-optimization. The thing is:

if I call pm_runtime_put(), I will not reinitialize the pm timer to
whatever timeout value I used. This means that pm_runtime_put() could
actually execute right away (if timer was about to expire when I called
pm_runtime_put()). While this wouldn't cause any issues, it's better to
reinitialize the timer and make sure if there's another
read/write/set_termios/whatever coming right after this, UART is still
powered up.

I mean, it's really just trying to avoid context save & restore when
UART is still under heavy usage.

Does it make sense ?

-- 
balbi
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 07:03:29 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 12:03:29 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821105413.GD26899@gmail.com>
References: <CACRpkdYbOBEPNbCdfi+=gupdqS8_7t7MpOgXs7VCVTs8Y3j_mQ@mail.gmail.com>
 <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
Message-ID: <20120821110329.GA7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 11:54:14AM +0100, Lee Jones wrote:
> On Tue, Aug 21, 2012 at 10:50:27AM +0100, Mark Brown wrote:

> > What makes you say this?  This is just a convenience for finding a
> > domain, irqdomains are *completely* indepentant of device tree.

> How can you say that? I think you mean _can_ be independent of DT. If
> that's what you mean then yes, that's true. All I'm saying is we need

No, I really mean what I'm saying.  Device tree builds on irqdomains,
not the other way around.

> another way to get hold of the domain, because the only way to obtain
> it without having direct access is via a device node.

This doesn't actually hold.

> > > - I know that you have interest in pushing the functionality into the
> > > IRQ domain subsystem, but I'm struggling to see how. It's calling into
> > > the IRQ domain where we're seeing issues in the first place, specifically
> > > irq_create_mapping(). How about if we passed 'irq_domain' as a parameter
> > > when requesting the IRQ? That way we can pass the correct IRQ without
> > > worry of conversion. If 'irq_domain' is !NULL the IRQ management subsystem
> > > can do the necessary conversions. If 'irq_domain' is NULL it continues to
> > > use the requested IRQ as a virq.

> > This is totally orthogonal to doing the mapping in the MFD subsystem
> > which is the issue here.

> Again, I only mentioned this because you said you wanted it to be handled
> by the irqdomain.

The *mapping* should be being handled in irqdomain.

> I'll code up the second suggestion now.

I've already done this.
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From santosh.shilimkar at ti.com  Tue Aug 21 07:05:26 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 21 Aug 2012 16:35:26 +0530
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <20120821105702.GX10347@arwen.pp.htv.fi>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-11-git-send-email-balbi@ti.com>
 <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>
 <20120821105702.GX10347@arwen.pp.htv.fi>
Message-ID: <CAMQu2gzJ2YksrJKPLNZ9pBoBoSih2Up=isca=X9Wsd5MsnNrTQ@mail.gmail.com>

On Tue, Aug 21, 2012 at 4:27 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Tue, Aug 21, 2012 at 04:12:11PM +0530, Shilimkar, Santosh wrote:
>> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
>> > Everytime we're done using our TTY, we want
>> > the pm timer to be reinitilized. By sticking
>> > to pm_runtime_pm_autosuspend() we make sure
>> > that this will always be the case.
>> >
>> > Signed-off-by: Felipe Balbi <balbi at ti.com>
>> > ---
>> >  drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
>> >  1 file changed, 22 insertions(+), 11 deletions(-)
>> >
>> > diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
>> > index 6ea24c5..458d77c 100644
>> > --- a/drivers/tty/serial/omap-serial.c
>> > +++ b/drivers/tty/serial/omap-serial.c
>> > @@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
>> >         pm_runtime_get_sync(up->dev);
>> >         up->ier |= UART_IER_MSI;
>> >         serial_out(up, UART_IER, up->ier);
>> > -       pm_runtime_put(up->dev);
>> > +       pm_runtime_mark_last_busy(up->dev);
>> > +       pm_runtime_put_autosuspend(up->dev);
>> >  }
>> >
>> Can you please expand the change-log a bit ?
>> Didn't follow the time re-init part completely.
>
> It's really just a micro-optimization. The thing is:
>
> if I call pm_runtime_put(), I will not reinitialize the pm timer to
> whatever timeout value I used. This means that pm_runtime_put() could
> actually execute right away (if timer was about to expire when I called
> pm_runtime_put()). While this wouldn't cause any issues, it's better to
> reinitialize the timer and make sure if there's another
> read/write/set_termios/whatever coming right after this, UART is still
> powered up.
>
> I mean, it's really just trying to avoid context save & restore when
> UART is still under heavy usage.
>
> Does it make sense ?

It does. Would be good to add the above description in the change-log.
Thanks for clarification.

Regars
Santosh


From balbi at ti.com  Tue Aug 21 07:02:46 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 14:02:46 +0300
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <CAMQu2gzJ2YksrJKPLNZ9pBoBoSih2Up=isca=X9Wsd5MsnNrTQ@mail.gmail.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-11-git-send-email-balbi@ti.com>
 <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>
 <20120821105702.GX10347@arwen.pp.htv.fi>
 <CAMQu2gzJ2YksrJKPLNZ9pBoBoSih2Up=isca=X9Wsd5MsnNrTQ@mail.gmail.com>
Message-ID: <20120821110245.GY10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 04:35:26PM +0530, Shilimkar, Santosh wrote:
> On Tue, Aug 21, 2012 at 4:27 PM, Felipe Balbi <balbi at ti.com> wrote:
> > On Tue, Aug 21, 2012 at 04:12:11PM +0530, Shilimkar, Santosh wrote:
> >> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> >> > Everytime we're done using our TTY, we want
> >> > the pm timer to be reinitilized. By sticking
> >> > to pm_runtime_pm_autosuspend() we make sure
> >> > that this will always be the case.
> >> >
> >> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> >> > ---
> >> >  drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
> >> >  1 file changed, 22 insertions(+), 11 deletions(-)
> >> >
> >> > diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> >> > index 6ea24c5..458d77c 100644
> >> > --- a/drivers/tty/serial/omap-serial.c
> >> > +++ b/drivers/tty/serial/omap-serial.c
> >> > @@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
> >> >         pm_runtime_get_sync(up->dev);
> >> >         up->ier |= UART_IER_MSI;
> >> >         serial_out(up, UART_IER, up->ier);
> >> > -       pm_runtime_put(up->dev);
> >> > +       pm_runtime_mark_last_busy(up->dev);
> >> > +       pm_runtime_put_autosuspend(up->dev);
> >> >  }
> >> >
> >> Can you please expand the change-log a bit ?
> >> Didn't follow the time re-init part completely.
> >
> > It's really just a micro-optimization. The thing is:
> >
> > if I call pm_runtime_put(), I will not reinitialize the pm timer to
> > whatever timeout value I used. This means that pm_runtime_put() could
> > actually execute right away (if timer was about to expire when I called
> > pm_runtime_put()). While this wouldn't cause any issues, it's better to
> > reinitialize the timer and make sure if there's another
> > read/write/set_termios/whatever coming right after this, UART is still
> > powered up.
> >
> > I mean, it's really just trying to avoid context save & restore when
> > UART is still under heavy usage.
> >
> > Does it make sense ?
> 
> It does. Would be good to add the above description in the change-log.
> Thanks for clarification.

will do, cheers

-- 
balbi
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From balbi at ti.com  Tue Aug 21 07:09:52 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 14:09:52 +0300
Subject: [RFC/PATCH 10/13] serial: omap: stick to put_autosuspend
In-Reply-To: <20120821110245.GY10347@arwen.pp.htv.fi>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-11-git-send-email-balbi@ti.com>
 <CAMQu2gzm4z8DbCiz4hOS2nKa2HzNofmp=SPORYEu2Z_H3+JN9Q@mail.gmail.com>
 <20120821105702.GX10347@arwen.pp.htv.fi>
 <CAMQu2gzJ2YksrJKPLNZ9pBoBoSih2Up=isca=X9Wsd5MsnNrTQ@mail.gmail.com>
 <20120821110245.GY10347@arwen.pp.htv.fi>
Message-ID: <20120821110951.GZ10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 02:02:46PM +0300, Felipe Balbi wrote:
> On Tue, Aug 21, 2012 at 04:35:26PM +0530, Shilimkar, Santosh wrote:
> > On Tue, Aug 21, 2012 at 4:27 PM, Felipe Balbi <balbi at ti.com> wrote:
> > > On Tue, Aug 21, 2012 at 04:12:11PM +0530, Shilimkar, Santosh wrote:
> > >> On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi <balbi at ti.com> wrote:
> > >> > Everytime we're done using our TTY, we want
> > >> > the pm timer to be reinitilized. By sticking
> > >> > to pm_runtime_pm_autosuspend() we make sure
> > >> > that this will always be the case.
> > >> >
> > >> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> > >> > ---
> > >> >  drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
> > >> >  1 file changed, 22 insertions(+), 11 deletions(-)
> > >> >
> > >> > diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> > >> > index 6ea24c5..458d77c 100644
> > >> > --- a/drivers/tty/serial/omap-serial.c
> > >> > +++ b/drivers/tty/serial/omap-serial.c
> > >> > @@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
> > >> >         pm_runtime_get_sync(up->dev);
> > >> >         up->ier |= UART_IER_MSI;
> > >> >         serial_out(up, UART_IER, up->ier);
> > >> > -       pm_runtime_put(up->dev);
> > >> > +       pm_runtime_mark_last_busy(up->dev);
> > >> > +       pm_runtime_put_autosuspend(up->dev);
> > >> >  }
> > >> >
> > >> Can you please expand the change-log a bit ?
> > >> Didn't follow the time re-init part completely.
> > >
> > > It's really just a micro-optimization. The thing is:
> > >
> > > if I call pm_runtime_put(), I will not reinitialize the pm timer to
> > > whatever timeout value I used. This means that pm_runtime_put() could
> > > actually execute right away (if timer was about to expire when I called
> > > pm_runtime_put()). While this wouldn't cause any issues, it's better to
> > > reinitialize the timer and make sure if there's another
> > > read/write/set_termios/whatever coming right after this, UART is still
> > > powered up.
> > >
> > > I mean, it's really just trying to avoid context save & restore when
> > > UART is still under heavy usage.
> > >
> > > Does it make sense ?
> > 
> > It does. Would be good to add the above description in the change-log.
> > Thanks for clarification.
> 
> will do, cheers

I have updated my branch like below. Will wait for any other comments
before sending another version.

commit 8ff7ab777d2bf8619328ddd43ddf2f8660dd011f
Author: Felipe Balbi <balbi at ti.com>
Date:   Tue Aug 21 11:45:47 2012 +0300

    serial: omap: stick to put_autosuspend
    
    Everytime we're done using our TTY, we want
    the pm timer to be reinitilized. By sticking
    to pm_runtime_pm_autosuspend() we make sure
    that this will always be the case.
    
    The idea behind this patch is to make sure we
    will always reinitialize the pm timer so that
    we don't fall into a situation where pm_runtime_put()
    expires right away (if timer was already about to
    expire when we made the call to pm_runtime_put()).
    
    While suspending right away wouldn't cause any
    issues, reinitializing the pm timer can help us
    avoiding unnecessary context save & restore
    operations (which are somewhat expensive) if there's
    another read/write/set_termios request coming right
    after. IOW, we are trying to make sure UART is still
    powered up while it's still under heavy usage.
    
    Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
    Signed-off-by: Felipe Balbi <balbi at ti.com>

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6ea24c5..458d77c 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
 	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
@@ -412,7 +413,8 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return ret;
 }
 
@@ -424,7 +426,8 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -460,7 +463,8 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -477,7 +481,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -575,7 +580,8 @@ static void serial_omap_shutdown(struct uart_port *port)
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -846,7 +852,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -877,7 +884,8 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -959,7 +967,8 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -973,7 +982,8 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return status;
 }
 
@@ -1305,7 +1315,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (ret != 0)
 		goto err_add_port;
 
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	platform_set_drvdata(pdev, up);
 	return 0;
 

let me know if your Ack is still valid.

-- 
balbi
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From afzal at ti.com  Tue Aug 21 07:14:07 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 21 Aug 2012 11:14:07 +0000
Subject: gpmc generic retime function (subject was RE: [PATCH v5 3/3]
 ARM: OMAP2+: onenand: prepare for gpmc driver migration)
In-Reply-To: <502E5D0A.2030109@ti.com>
References: <C8443D0743D26F4388EA172BF4E2A7A93E9A35E1@DBDE01.ent.ti.com>
 <20120705105535.GB1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A39DF@DBDE01.ent.ti.com>
 <20120706120533.GU1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A622E@DBDE01.ent.ti.com>
 <20120710094538.GT1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A64D0@DBDE01.ent.ti.com>
 <20120710131734.GV1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9A669D@DBDE01.ent.ti.com>
 <4FFC6330.1040409@ti.com> <20120711064724.GA1122@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9B150D@DBDE01.ent.ti.com>
 <502E5D0A.2030109@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9B854C@DBDE01.ent.ti.com>

Hi Jon,

On Fri, Aug 17, 2012 at 20:32:34, Hunter, Jon wrote:

> > And we have been able to create such a function. Below is an implementation
> > that has been made for handling asynchronous timings. It has been tested for
> > OneNAND & SMSC on OMAP3EVM (rev G & C) with [1-4]. OneNAND was tested using
> > [5] (OMAP3EVM OneNAND works in async mode) & SMSC using [6] (mainline does
> > not have a timing calculation for smsc911x)
> 
> Are you able to verify that the timing calculated by this function are
> identical? May be some more details on exactly how you tested this would
> be good.

Yes, it was verified.

A new driver preparation series has been posted,
	http://marc.info/?l=linux-omap&m=134554573104116&w=2
that includes generic timing calculation method.

The new series mentions how timing values were validated. There are a
couple of timing parameters that would vary as mentioned in the above
mentioned mail, but these I don't expect to create problems as this is 
more inline with gpmc peripheral timings. And both of the these has
been verified that it would not create problem with peripheral
functionality. One was tested directly (we_on related for OneNAND) and
other indirectly (adv_rd(wr)_off on SMSC 9220 for SMSC 91C96).

Reason for doing so was that quirks required to handle these specific
cases could be avoided, otherwise new peripheral timing data would be
required and it would be difficult to achieve DT bindings (when DT
happens) for these kind of fixup timings.

But if this causes any problems (which I don't expect), then we will
have to fallback to the quirks that I wanted to avoid.

> Do you think that there is any value in making the tusb member a "u32
> dev_type" and then set it too GPMC_DEVICE_TUSB then this could be used
> for other devices in the future too if needed?

> Would it be possible to create a sub-function called
> gpmc_calc_timings_tusb() and put all these "if (tusb)" statements in
> there? Or maybe a generic function called gpmc_calc_timings_prepare().

Usage of a "tusb" check was something that I really wanted to avoid as
that was making generic timing calculation function peripheral Gnostic.
With the newly posted series, "tusb" field has been removed.

Regards
Afzal


From anilkumar at ti.com  Tue Aug 21 07:17:28 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 21 Aug 2012 16:47:28 +0530
Subject: [PATCH v3 2/4] arm/dts: regulator: Add tps65217 device tree data
In-Reply-To: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345547850-29761-3-git-send-email-anilkumar@ti.com>

Add device tree data for tps65217 regulator by adding all tps65217
regulator nodes. Regulator is initialized based on compatiable
name provided in tps65217 DT file.

All tps65910 PMIC regulator device tree nodes are placed in a
seperate device tree include file (tps65217.dtsi). This patch
was tested on AM335x-Bone.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/tps65217.dtsi |   56 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/boot/dts/tps65217.dtsi

diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 0000000..a632724
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+	compatible = "ti,tps65217";
+
+	regulators {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dcdc1_reg: regulator at 0 {
+			reg = <0>;
+			regulator-compatible = "dcdc1";
+		};
+
+		dcdc2_reg: regulator at 1 {
+			reg = <1>;
+			regulator-compatible = "dcdc2";
+		};
+
+		dcdc3_reg: regulator at 2 {
+			reg = <2>;
+			regulator-compatible = "dcdc3";
+		};
+
+		ldo1_reg: regulator at 3 {
+			reg = <3>;
+			regulator-compatible = "ldo1";
+		};
+
+		ldo2_reg: regulator at 4 {
+			reg = <4>;
+			regulator-compatible = "ldo2";
+		};
+
+		ldo3_reg: regulator at 5 {
+			reg = <5>;
+			regulator-compatible = "ldo3";
+		};
+
+		ldo4_reg: regulator at 6 {
+			reg = <6>;
+			regulator-compatible = "ldo4";
+		};
+	};
+};
-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 21 07:17:26 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 21 Aug 2012 16:47:26 +0530
Subject: [PATCH v3 0/4] Add AM33XX regulators device tree data
Message-ID: <1345547850-29761-1-git-send-email-anilkumar@ti.com>

This patch series add AM33XX regulators (tps65910/tps65217) device
tree data to am335x-evm and am335x-bone dts files. These patches
are based on Tony L "devel-dt" tree with these patches
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg73843.html
and these patches has been tested on AM335x EVM and Bone devices.

Changes from v2:
	- Added remaining regulator nodes with always on flag.
	  With out this flag regulator core calls for disable
	  regulators after init, which make device hang.
	- Modified tps65910 DTS entires with respect to tps65910
	  input supply.

Changes from v1:
	- Incorporated all Mark Brown's review comments on v1 by
	  * moving all the regulator constraints to corresponding
	    DTS file
	  * Regulator constraints are added according to board.
	- regulator name is added.

AnilKumar Ch (4):
  arm/dts: regulator: Add tps65910 device tree data
  arm/dts: regulator: Add tps65217 device tree data
  arm/dts: Add tps65910 regulator DT data to am335x-evm.dts
  arm/dts: Add tps65217 regulator DT data to am335x-bone.dts

 arch/arm/boot/dts/am335x-bone.dts |   54 +++++++++++++++++++++
 arch/arm/boot/dts/am335x-evm.dts  |   94 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tps65217.dtsi   |   56 ++++++++++++++++++++++
 arch/arm/boot/dts/tps65910.dtsi   |   86 +++++++++++++++++++++++++++++++++
 4 files changed, 290 insertions(+)
 create mode 100644 arch/arm/boot/dts/tps65217.dtsi
 create mode 100644 arch/arm/boot/dts/tps65910.dtsi

-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 21 07:17:27 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 21 Aug 2012 16:47:27 +0530
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345547850-29761-2-git-send-email-anilkumar@ti.com>

Add device tree data for tps65910 regulator by adding all tps65910
regulator nodes. Regulator is initialized based on compatiable
name provided in tps65910 DT file.

All tps65910 PMIC regulator device tree nodes are placed in a
seperate device tree include file (tps65910.dtsi). This patch
was tested on AM335x-EVM.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/tps65910.dtsi |   86 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 arch/arm/boot/dts/tps65910.dtsi

diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 0000000..92693a8
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+	compatible = "ti,tps65910";
+
+	regulators {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vrtc_reg: regulator at 0 {
+			reg = <0>;
+			regulator-compatible = "vrtc";
+		};
+
+		vio_reg: regulator at 1 {
+			reg = <1>;
+			regulator-compatible = "vio";
+		};
+
+		vdd1_reg: regulator at 2 {
+			reg = <2>;
+			regulator-compatible = "vdd1";
+		};
+
+		vdd2_reg: regulator at 3 {
+			reg = <3>;
+			regulator-compatible = "vdd2";
+		};
+
+		vdd3_reg: regulator at 4 {
+			reg = <4>;
+			regulator-compatible = "vdd3";
+		};
+
+		vdig1_reg: regulator at 5 {
+			reg = <5>;
+			regulator-compatible = "vdig1";
+		};
+
+		vdig2_reg: regulator at 6 {
+			reg = <6>;
+			regulator-compatible = "vdig2";
+		};
+
+		vpll_reg: regulator at 7 {
+			reg = <7>;
+			regulator-compatible = "vpll";
+		};
+
+		vdac_reg: regulator at 8 {
+			reg = <8>;
+			regulator-compatible = "vdac";
+		};
+
+		vaux1_reg: regulator at 9 {
+			reg = <9>;
+			regulator-compatible = "vaux1";
+		};
+
+		vaux2_reg: regulator at 10 {
+			reg = <10>;
+			regulator-compatible = "vaux2";
+		};
+
+		vaux33_reg: regulator at 11 {
+			reg = <11>;
+			regulator-compatible = "vaux33";
+		};
+
+		vmmc_reg: regulator at 12 {
+			reg = <12>;
+			regulator-compatible = "vmmc";
+		};
+	};
+};
-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 21 07:17:30 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 21 Aug 2012 16:47:30 +0530
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345547850-29761-5-git-send-email-anilkumar@ti.com>

Add tps65217 regulator device tree data to AM335x-Bone by adding
regulator consumers with tightened constraints and regulator-name.
TPS65217 regulator handle can be obtained by using this regulator
name.

This patch also add I2C node with I2C frequency and tps65217 PMIC
I2C slave address.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |   54 +++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 58f5042..f1c2772 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -36,5 +36,59 @@
 		uart1: serial at 44E09000 {
 			status = "okay";
 		};
+
+		i2c1: i2c at 44E0B000 {
+			status = "okay";
+			clock-frequency = <400000>;
+
+			tps: tps at 24 {
+				reg = <0x24>;
+			};
+
+		};
+	};
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+	regulators {
+		dcdc1_reg: regulator at 0 {
+			regulator-always-on;
+		};
+
+		dcdc2_reg: regulator at 1 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1325000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3_reg: regulator at 2 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo1_reg: regulator at 3 {
+			regulator-always-on;
+		};
+
+		ldo2_reg: regulator at 4 {
+			regulator-always-on;
+		};
+
+		ldo3_reg: regulator at 5 {
+			regulator-always-on;
+		};
+
+		ldo4_reg: regulator at 6 {
+			regulator-always-on;
+		};
 	};
 };
-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 21 07:17:29 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 21 Aug 2012 16:47:29 +0530
Subject: [PATCH v3 3/4] arm/dts: Add tps65910 regulator DT data to
 am335x-evm.dts
In-Reply-To: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
Message-ID: <1345547850-29761-4-git-send-email-anilkumar@ti.com>

Add tps65910 regulator device tree data to AM335x-EVM by adding
regulator consumers with tightened constraints and regulator-name.
TPS65910 regulator handle can be obtained by using this regulator
name.

This patch also add I2C node with I2C frequency and tps65910 PMIC
I2C slave address.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts |   94 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 1e1fc15..f9c28a5 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -38,5 +38,99 @@
 		dcan1: d_can at 481D0000 {
 			status = "okay";
 		};
+
+		i2c1: i2c at 44E0B000 {
+			status = "okay";
+			clock-frequency = <400000>;
+
+			tps: tps at 2D {
+				reg = <0x2D>;
+			};
+		};
+	};
+
+	vbat: fixedregulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator at 0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator at 1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator at 2 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1312500>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator at 3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator at 4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator at 5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator at 6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator at 7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator at 8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator at 9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator at 10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator at 11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator at 12 {
+			regulator-always-on;
+		};
 	};
 };
-- 
1.7.9.5



From sourav.poddar at ti.com  Tue Aug 21 07:20:50 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 21 Aug 2012 16:50:50 +0530
Subject: [PATCH 3/4] arm/dts: omap5-evm: Add keypad support
In-Reply-To: <20120821104744.GV10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-4-git-send-email-sourav.poddar@ti.com>
 <20120821104744.GV10347@arwen.pp.htv.fi>
Message-ID: <CAKdam54=+vn7YepPoDVkKaXm+0cxGNZ=w4v-eYbW4VtmWxmYBQ@mail.gmail.com>

Hi,

On Tue, Aug 21, 2012 at 4:17 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Tue, Aug 21, 2012 at 04:15:39PM +0530, Sourav Poddar wrote:
>> Add keypad data node in omap5-evm.
>>
>> Based on I2C support patch for omap5, which has been
>> already posted as a different series.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Tested on omap5430 sdp with 3.5 custom kernel.
>>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>
> after fixing my only comment below, you can add my:
>
> Acked-by: Felipe Balbi <balbi at ti.com>
>
>> ---
>>  arch/arm/boot/dts/omap5-evm.dts |   95 +++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 95 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
>> index 200c39a..6473983 100644
>> --- a/arch/arm/boot/dts/omap5-evm.dts
>> +++ b/arch/arm/boot/dts/omap5-evm.dts
>> @@ -18,3 +18,98 @@
>>               reg = <0x80000000 0x40000000>; /* 1 GB */
>>       };
>>  };
>> +
>> +&i2c5 {
>> +     clock-frequency = <400000>;
>> +
>> +     smsc at 38 {
>> +             compatible = "smsc";
>> +             reg = <0x38>;
>> +             clock = <0x13>;
>> +             keypad {
>> +                     compatible = "smsc,keypad";
>> +                     interrupt-parent = <&gpio5>;
>> +                     interrupts = <23>; /* gpio line 151 */
>> +                     keypad,num-rows = <8>;
>> +                     keypad,num-columns = <16>;
>> +                     linux,keymap = < 0x20041 /*KEY_F7*/
>
> please add spaces around /* and */ so it's easier to read. Ditto to all
> others.
>
Yes, will add spaces in the new version.
> --
> balbi


From hdoyu at nvidia.com  Tue Aug 21 07:22:35 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 21 Aug 2012 14:22:35 +0300
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com>
References: <1343636899-19508-1-git-send-email-m.szyprowski@samsung.com>
 <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120821142235.97984abc9ad98d01015a3338@nvidia.com>

Hi,

On Mon, 30 Jul 2012 10:28:19 +0200
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> This patch changes dma-mapping subsystem to use generic vmalloc areas
> for all consistent dma allocations. This increases the total size limit
> of the consistent allocations and removes platform hacks and a lot of
> duplicated code.
> 
> Atomic allocations are served from special pool preallocated on boot,
> because vmalloc areas cannot be reliably created in atomic context.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Reviewed-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  Documentation/kernel-parameters.txt |    2 +-
>  arch/arm/include/asm/dma-mapping.h  |    2 +-
>  arch/arm/mm/dma-mapping.c           |  486 ++++++++++++-----------------------
>  arch/arm/mm/mm.h                    |    3 +
>  include/linux/vmalloc.h             |    1 +
>  mm/vmalloc.c                        |   10 +-
>  6 files changed, 181 insertions(+), 323 deletions(-)
> 
...
> @@ -1117,61 +984,32 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
>   * Create a CPU mapping for a specified pages
>   */
>  static void *
> -__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
> +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
> +                   const void *caller)
>  {
> -       struct arm_vmregion *c;
> -       size_t align;
> -       size_t count = size >> PAGE_SHIFT;
> -       int bit;
> +       unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
> +       struct vm_struct *area;
> +       unsigned long p;
> 
> -       if (!consistent_pte[0]) {
> -               pr_err("%s: not initialised\n", __func__);
> -               dump_stack();
> +       area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
> +                                 caller);
> +       if (!area)

This patch replaced the custom "consistent_pte" with
get_vm_area_caller()", which breaks the compatibility with the
existing driver. This causes the following kernel oops(*1). That
driver has called dma_pool_alloc() to allocate memory from the
interrupt context, and it hits BUG_ON(in_interrpt()) in
"get_vm_area_caller()"(*2). Regardless of the badness of allocation
from interrupt handler in the driver, I have the following question.

The following "__get_vm_area_node()" can take gfp_mask, it means that
this function is expected to be called from atomic context, but why
it's _NOT_ allowed _ONLY_ from interrupt context?

According to the following definitions, "in_interrupt()" is in "in_atomic()".

#define in_interrupt()	(preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK | NMI_MASK))
#define in_atomic()	((preempt_count() & ~PREEMPT_ACTIVE) != 0)

Does anyone know why BUG_ON(in_interrupt()) is set in __get_vm_area_node(*3)?

*2:
  static struct vm_struct *__get_vm_area_node(unsigned long size,
                  unsigned long align, unsigned long flags, unsigned long start,
                  unsigned long end, int node, gfp_t gfp_mask, const void *caller)
  {
          struct vmap_area *va;
          struct vm_struct *area;

          BUG_ON(in_interrupt());
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^*3:
*1:
[    8.321343] ------------[ cut here ]------------
[    8.325971] kernel BUG at /home/hdoyu/mydroid-k340-cardhu/kernel/mm/vmalloc.c:1322!
[    8.333615] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[    8.339436] Modules linked in:
[    8.342496] CPU: 0    Tainted: G        W     (3.4.6-00067-g5d485f7 #67)
[    8.349192] PC is at __get_vm_area_node.isra.29+0x164/0x16c
[    8.354758] LR is at get_vm_area_caller+0x4c/0x54
[    8.359454] pc : [<c011297c>]    lr : [<c011318c>]    psr: 20000193
[    8.359458] sp : c09edca0  ip : c09ec000  fp : ae278000
[    8.370922] r10: f0000000  r9 : c011aa54  r8 : c0a26cb8
[    8.376136] r7 : 00000001  r6 : 000000d0  r5 : 20000008  r4 : c09edca0
[    8.382651] r3 : 00010000  r2 : 20000008  r1 : 00000001  r0 : 00001000
[    8.389166] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    8.396549] Control: 10c5387d  Table: ad98c04a  DAC: 00000015
....
[    9.169162] dfa0: 412fc099 c09ec000 00000000 c000fdd8 c06df1e4 c0a1b080 00000000 00000000
[    9.177329] dfc0: c0a235cc 8000406a 00000000 c0986818 ffffffff ffffffff c0986404 00000000
[    9.185497] dfe0: 00000000 c09bb070 10c5387d c0a19c58 c09bb064 80008044 00000000 00000000
[    9.193673] [<c011297c>] (__get_vm_area_node.isra.29+0x164/0x16c) from [<c011318c>] (get_vm_area_caller+0x4c/0x54)
[    9.204022] [<c011318c>] (get_vm_area_caller+0x4c/0x54) from [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc)
[    9.214276] [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc) from [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8)
[    9.224795] [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8) from [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8)
[    9.235309] [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8) from [<c011ab60>] (dma_pool_alloc+0x80/0x170)
[    9.245304] [<c011ab60>] (dma_pool_alloc+0x80/0x170) from [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c)
[    9.254344] [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c) from [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8)
[    9.263467] [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8) from [<c03cc140>] (tegra_ep_queue+0x154/0x33c)
[    9.272592] [<c03cc140>] (tegra_ep_queue+0x154/0x33c) from [<c03dd5b4>] (composite_setup+0x364/0x6d4)
[    9.281804] [<c03dd5b4>] (composite_setup+0x364/0x6d4) from [<c03dd9dc>] (android_setup+0xb8/0x14c)
[    9.290843] [<c03dd9dc>] (android_setup+0xb8/0x14c) from [<c03cd144>] (setup_received_irq+0xbc/0x270)
[    9.300053] [<c03cd144>] (setup_received_irq+0xbc/0x270) from [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4)
[    9.309353] [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4) from [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0)
[    9.319087] [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0) from [<c00b59b4>] (handle_irq_event+0x44/0x64)
[    9.328907] [<c00b59b4>] (handle_irq_event+0x44/0x64) from [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c)
[    9.338294] [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c) from [<c00b4f14>] (generic_handle_irq+0x34/0x48)
[    9.347858] [<c00b4f14>] (generic_handle_irq+0x34/0x48) from [<c000f6f4>] (handle_IRQ+0x54/0xb4)
[    9.356637] [<c000f6f4>] (handle_IRQ+0x54/0xb4) from [<c00084b0>] (gic_handle_irq+0x2c/0x60)
[    9.365068] [<c00084b0>] (gic_handle_irq+0x2c/0x60) from [<c000e900>] (__irq_svc+0x40/0x70)
[    9.373405] Exception stack(0xc09edf10 to 0xc09edf58)
[    9.378447] df00:                                     00000000 000f4240 00000003 00000000
[    9.386615] df20: 00000000 e55bbc00 ef66f3ca 00000001 00000000 412fc099 c0abb9c8 00000000
[    9.394781] df40: 3b9ac9ff c09edf58 c027a9bc c0042880 20000113 ffffffff
[    9.401396] [<c000e900>] (__irq_svc+0x40/0x70) from [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78)
[    9.410272] [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78) from [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4)
[    9.419922] [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4) from [<c000fdd8>] (cpu_idle+0xd8/0x134)
[    9.428612] [<c000fdd8>] (cpu_idle+0xd8/0x134) from [<c0986818>] (start_kernel+0x27c/0x2cc)
[    9.436952] Code: e1a00004 e3a04000 eb002265 eaffffe0 (e7f001f2)
[    9.443038] ---[ end trace 1b75b31a2719ed24 ]---
[    9.447645] Kernel panic - not syncing: Fatal exception in interrupt


From linus.walleij at linaro.org  Tue Aug 21 07:25:18 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 13:25:18 +0200
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>

On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
> SoC's.

Thanks for doing this Thomas, great work!

> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

I don't understand the rules around bindings very well, I would
suggest you include
devicetree-discuss at lists.ozlabs.org on the mails, besides you know
this stuff way
better than me anyway :-)

> +  The child node can also optionally specify one or more of the pin
> +  configuration that should be applied on all the pins listed in the
> +  "samsung,pins" property of the child node. The following pin configuration
> +  properties are supported.
> +
> +  - samsung,pin-pud: Pull up/down configuration.
> +  - samsung,pin-drv: Drive strength configuration.
> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.

This looks a bit scary, as it seems to be orthogonal to the pin config
interface. I.e. this will be programmed "behind the back" of the
pin config system. However as long as the pin config implementation
reads back these things from the registers it will work, too.

In the U300 and Ux500 I explicitly use pin config hogs to set up
the pin configuration, and when we enter a state such as
"default" the mux setting and config settings are set from the
framework separately.

See for example:
arch/arm/mach-ux500/board-mop500-pins.c

This example is using platform data but it should be trivial to do with
device tree.

I think the Tegra also works this way. Can you elaborate on
why you need this static setup from the device tree instead
of using default states?

I also think this looks like it could use generic pin config to stash
the configs, just expand the stuff in <linux/pinctrl/pinconf-generic.h>

(...)
> +Example 1:

The examples seem to only pertain to the pin controller per se, maybe you
could include a DT entry for a uart or something showing how the
uart device binds to a certain pinctrl setting.

> +       pinctrl_0: pinctrl at 11400000 {
> +               compatible = "samsung,pinctrl-exynos4210";
> +               reg = <0x11400000 0x1000>;
> +               interrupts = <0 47 0>;
> +
> +               uart0_data: uart0-data {
> +                       samsung,pins = "gpa0-0", "gpa0-1";
> +                       samsung,pin-function = <2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };

This setup needs to be associated with a certain state, it's possible to
do in the code or directly in the device tree.

I.e. these settings for pin-pud and pin-drv needs to belong to a
certain pin config state, typically the state named "default"

> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig

> +config PINCTRL_SAMSUNG
> +       bool "Samsung pinctrl driver"
> +       depends on OF

I don't understand how this can even compile. Do you need:

select PINMUX
select PINCONF

to get the framework files you need to compile?

Or are you selecting thes in some platform Kconfig or so?
In that case please move them here.

> +/* list of all possible config options supported */
> +struct pin_config {
> +       char            *prop_cfg;
> +       unsigned int    cfg_type;
> +} pcfgs[] = {
> +       { "samsung,pin-pud", PINCFG_TYPE_PUD },
> +       { "samsung,pin-drv", PINCFG_TYPE_DRV },
> +       { "samsung,pin-pud-pdn", PINCFG_TYPE_CON_PND },
> +       { "samsung,pin-drv-pdn", PINCFG_TYPE_PUD_PND },
> +};

Hmmmmm it looks very much like this controller could make use of
the generic pinconf library, but it's not mandatory so just a suggestion.

(...)
> +/* create pinctrl_map entries by parsing device tree nodes */
> +static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
> +                       struct device_node *np, struct pinctrl_map **maps,
> +                       unsigned *nmaps)
> +{
(...)
> +       /* Allocate memory for pin group name. The pin group name is derived
> +        * from the node name from which these map entries are be created.
> +        */
> +       gname = kzalloc(strlen(np->name) + 4, GFP_KERNEL);

Why +4? I would have suspected +1 for the null terminator...

> +       if (!gname) {
> +               dev_err(dev, "failed to alloc memory for group name\n");
> +               goto free_map;
> +       }
> +       sprintf(gname, "%s-grp", np->name);

The rest of the pinmux implementation looks nice!

(...)
> +/* set the pull up/down and driver strength settings for a specified pin */
> +static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
> +                                       unsigned long config)
> +{
> +       struct samsung_pinctrl_drv_data *drvdata;
> +       unsigned long pin_offset;
> +       struct samsung_pin_bank *bank;
> +       void __iomem *reg;
> +
> +       drvdata = pinctrl_dev_get_drvdata(pctldev);
> +       pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg,
> +                                       &pin_offset, &bank);
> +
> +       switch (PINCFG_UNPACK_TYPE(config)) {
> +       case PINCFG_TYPE_PUD:
> +               samsung_pinconf_set_pud(drvdata, bank, reg, pin_offset, config);
> +               break;
> +       case PINCFG_TYPE_DRV:
> +               samsung_pinconf_set_drv(drvdata, bank, reg, pin_offset, config);
> +               break;


Hm there are two more types defined in the device tree:

+  - samsung,pin-pud: Pull up/down configuration.
+  - samsung,pin-drv: Drive strength configuration.
+  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
+  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.

I think you should define these as well, especially if you use the
states to program these things instead of the hack that I'm quite
sceptical about...

> +/* reading pin pull up/down and driver strength settings not implemented */

OK why not? It seems very simple and straight-forward.
Just read the same registers and switch() then return...

(...)

The gpiolib part looks really good, so no comments on that.

(...)
> +               /* derive function name from the node name */
> +               fname = devm_kzalloc(dev, strlen(cfg_np->name) + 4, GFP_KERNEL);

This +4 again...

(...)
> +       drvdata->grange.name = "samsung-pctrl-gpio-range";
> +       drvdata->grange.id = 0;
> +       drvdata->grange.base = drvdata->ctrl->base;
> +       drvdata->grange.npins = drvdata->ctrl->nr_pins;
> +       drvdata->grange.gc = drvdata->gc;
> +       pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange);

Grant didn't like custom ranges at all IIRC and wanted a generic
way of handling this. But doing so requires turning the range registration
API:s upside down and let the GPIO controller register the ranges.

If noone else is coding that, I guess we might have to live with
this kind of custom hacks. (No, I don't have time to fix it, sadly.)

(...)
> +static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
(...)
> +       if (ctrl->eint_gpio_init)
> +               ctrl->eint_gpio_init(drvdata);
> +       if (ctrl->eint_wkup_init)
> +               ctrl->eint_wkup_init(drvdata);

So this stuff I'm doing in the default states instead.

(...)
> +++ b/drivers/pinctrl/pinctrl-samsung.h
(...)
> +#ifndef __PINCTRL_SAMSUNG_H
> +#define __PINCTRL_SAMSUNG_H
> +
> +#include <linux/module.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/consumer.h>
> +#include <linux/pinctrl/machine.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>

Usually I prefer to have as many as possible of these in the .c file, but this
works too, and I haven't seen any rationale about it. Especially since this is
a local include I can live with it...


> +/**
> + * struct samsung_pin_bank: represent a controller pin-bank.
> + * @reg_offset: starting offset of the pin-bank registers.
> + * @pin_base: starting pin number of the bank.
> + * @nr_pins: number of pins included in this bank.
> + * @func_width: width of the function selector bit field.
> + * @pud_width: width of the pin pull up/down selector bit field.
> + * @drc_width: width of the pin driver strength selector bit field.
> + * @eint_type: type of the external interrupt supported by the bank.
> + * @irq_base: starting controller local irq number of the bank.
> + * @name: name to be prefixed for each pin in this pin bank.
> + */
> +struct samsung_pin_bank {
> +       unsigned int            pctl_offset;

Isn't this a u32?

> +       unsigned int            pin_base;
> +       unsigned int            nr_pins;
> +       unsigned int            func_width;
> +       unsigned int            pud_width;
> +       unsigned int            drv_width;

Are these "widths" really unsigned (32/64) bits?
Isn't u8 enough?

> +       unsigned int            eint_type;

Shouldn't this be some kund of enum if it denotes a type?

> +       unsigned int            irq_base;

u32?

> +       char                    *name;
> +};
> +
> +/**
> + * struct samsung_pin_ctrl: represent a pin controller.
> + * @pin_banks: list of pin banks included in this controller.
> + * @nr_banks: number of pin banks.
> + * @base: starting system wide pin number.
> + * @nr_pins: number of pins supported by the controller.
> + * @nr_gint: number of external gpio interrupts supported.
> + * @nr_wint: number of external wakeup interrupts supported.
> + * @geint_con: offset of the ext-gpio controller registers.

If it's an offset why not name it geint_con_offset?

> + * @geint_mask: offset of the ext-gpio interrupt mask registers.
> + * @geint_pend: offset of the ext-gpio interrupt pending registers.
> + * @weint_con: offset of the ext-wakeup controller registers.
> + * @weint_mask: offset of the ext-wakeup interrupt mask registers.
> + * @weint_pend: offset of the ext-wakeup interrupt pending registers.

Dito.

> + * @svc: offset of the interrupt service register.
> + * @eint_gpio_init: platform specific callback to setup the external gpio
> + *     interrupts for the controller.
> + * @eint_wkup_init: platform specific callback to setup the external wakeup
> + *     interrupts for the controller.
> + * @label: for debug information.

Could you add some free text here explaining the hardware just a little
bit? What is a external GPIO? what is an external wakeup? etc.

> + */
> +struct samsung_pin_ctrl {
> +       struct samsung_pin_bank *pin_banks;
> +       unsigned int            nr_banks;
> +
> +       unsigned int            base;

u32?

> +       unsigned int            nr_pins;
> +       unsigned int            nr_gint;
> +       unsigned int            nr_wint;
> +
> +       unsigned long           geint_con;
> +       unsigned long           geint_mask;
> +       unsigned long           geint_pend;

All three u32?

> +       unsigned long           weint_con;

u32?

> +       unsigned long           weint_mask;
> +       unsigned long           weint_pend;

u32?

> +       unsigned long           svc;

u32?

> +
> +       int                     (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
> +       int                     (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);

I guess you need to set up these using auxdata?

> +       char                    *label;
> +};
> +
> +/**
> + * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
> + * @virt_base: register base address of the controller.
> + * @dev: device instance representing the controller.
> + * @irq: interrpt number used by the controller to notify gpio interrupts.
> + * @ctrl: pin controller instance managed by the driver.
> + * @pctl: pin controller descriptor registered with the pinctrl subsystem.

Maybe name this pctl_desc then?

> + * @pctl_dev: cookie representing pinctrl device instance.
> + * @pin_groups: list of pin groups available to the driver.
> + * @nr_groups: number of such pin groups.
> + * @pmx_functions: list of pin functions available to the driver.
> + * @nr_function: number of such pin functions.
> + * @gc: gpio_chip instance registered with gpiolib.
> + * @grange: linux gpio pin range supported by this controller.
> + */
> +struct samsung_pinctrl_drv_data {
> +       void __iomem                    *virt_base;
> +       struct device                   *dev;
> +       int                             irq;
> +
> +       struct samsung_pin_ctrl         *ctrl;
> +       struct pinctrl_desc             pctl;
> +       struct pinctrl_dev              *pctl_dev;
> +
> +       const struct samsung_pin_group  *pin_groups;
> +       unsigned int                    nr_groups;
> +       const struct samsung_pmx_func   *pmx_functions;
> +       unsigned int                    nr_functions;
> +
> +       struct irq_domain               *gpio_irqd;
> +       struct irq_domain               *wkup_irqd;
> +
> +       struct gpio_chip                *gc;
> +       struct pinctrl_gpio_range       grange;
> +};

This is looking really good.

No further comments! (Atleast not this time, since it's a big
driver I have probably missed something...)

Linus Walleij


From sourav.poddar at ti.com  Tue Aug 21 07:30:44 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 21 Aug 2012 17:00:44 +0530
Subject: [PATCH 2/4] Input: keypad: Add smsc ece1099 keypad driver
In-Reply-To: <20120821104549.GT10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
 <20120821104549.GT10347@arwen.pp.htv.fi>
Message-ID: <CAKdam57c=yc2AtG8R_ioMcxQhNj39i+f4PDuJM5wruWOSn5FYw@mail.gmail.com>

Hi,

On Tue, Aug 21, 2012 at 4:15 PM, Felipe Balbi <balbi at ti.com> wrote:
> On Tue, Aug 21, 2012 at 04:15:38PM +0530, Sourav Poddar wrote:
>> From: G, Manjunath Kondaiah <manjugk at ti.com>
>>
>> SMSC ECE1099 is a keyboard scan or GPIO expansion device.The device
>> supports a keypad scan matrix of 23*8.This driver uses this
>> device as a keypad driver.
>>
>> Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>
> looks good. If you just fix my comment on free_irq() below, you can add:
>
> Acked-by: Felipe Balbi <balbi at ti.com>
>
>> +static int __devinit
>> +smsc_probe(struct platform_device *pdev)
>> +{
>> +     struct device *dev = &pdev->dev;
>> +     struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
>> +     struct input_dev *input;
>> +     struct smsc_keypad *kp;
>> +     int ret = 0, error;
>> +     int col, i, max_keys, row_shift;
>> +     int irq;
>> +     int addr_start, addr;
>> +
>> +     kp = devm_kzalloc(dev, sizeof(*kp), GFP_KERNEL);
>> +
>> +     input = input_allocate_device();
>> +     if (!kp || !input) {
>> +             error = -ENOMEM;
>> +             goto err1;
>> +     }
>> +
>> +     error = smsc_keypad_parse_dt(&pdev->dev, kp);
>> +     if (error)
>> +             return error;
>> +
>> +     /* Get the debug Device */
>> +     kp->input = input;
>> +     kp->smsc = smsc;
>> +     kp->irq = platform_get_irq(pdev, 0);
>> +     kp->dev = dev;
>> +
>> +     for (col = 0; col < 16; col++) {
>> +             kp->last_key_state[col] = 0;
>> +             kp->last_key_ms[col] = 0;
>> +     }
>> +
>> +     /* setup input device */
>> +      __set_bit(EV_KEY, input->evbit);
>> +
>> +     /* Enable auto repeat feature of Linux input subsystem */
>> +     if (!(kp->no_autorepeat))
>> +             __set_bit(EV_REP, input->evbit);
>> +
>> +     input_set_capability(input, EV_MSC, MSC_SCAN);
>> +     input->name             = "SMSC Keypad";
>> +     input->phys             = "smsc_keypad/input0";
>> +     input->dev.parent       = &pdev->dev;
>> +     input->id.bustype       = BUS_HOST;
>> +     input->id.vendor        = 0x0001;
>> +     input->id.product       = 0x0001;
>> +     input->id.version       = 0x0003;
>> +
>> +     error = input_register_device(input);
>> +     if (error) {
>> +             dev_err(kp->dev,
>> +                     "Unable to register twl4030 keypad device\n");
>> +             goto err1;
>> +     }
>> +
>> +     /* Mask all GPIO interrupts (0x37-0x3B) */
>> +     for (addr = 0x37; addr < 0x3B; addr++)
>> +             smsc_write(dev, addr, 0);
>> +
>> +     /* Set all outputs high (0x05-0x09) */
>> +     for (addr = 0x05; addr < 0x09; addr++)
>> +             smsc_write(dev, addr, 0xff);
>> +
>> +     /* Clear all GPIO interrupts (0x32-0x36) */
>> +     for (addr = 0x32; addr < 0x36; addr++)
>> +             smsc_write(dev, addr, 0xff);
>> +
>> +     addr_start = 0x12;
>> +     for (i = 0; i <= kp->rows; i++) {
>> +             addr = 0x12 + i;
>> +             smsc_write(dev, addr, SMSC_KP_KSI);
>> +     }
>> +
>> +     addr_start =  0x1A;
>> +     for (i = 0; i <= kp->cols; i++) {
>> +             addr = 0x1A + i;
>> +             smsc_write(dev, addr, SMSC_KP_KSO);
>> +     }
>> +
>> +     addr = SMSC_KP_INT_STAT;
>> +     smsc_write(dev, addr, SMSC_KP_SET_HIGH);
>> +
>> +     addr = SMSC_WKUP_CTRL;
>> +     smsc_write(dev, addr, SMSC_KP_SET_LOW_PWR);
>> +
>> +     addr = SMSC_KP_OUT;
>> +     smsc_write(dev, addr, SMSC_KSO_ALL_LOW);
>> +
>> +     row_shift = get_count_order(kp->cols);
>> +     max_keys = kp->rows << row_shift;
>> +
>> +     kp->row_shift = row_shift;
>> +     kp->keymap = kzalloc(max_keys * sizeof(kp->keymap[0]),
>> +                                     GFP_KERNEL);
>> +     if (!kp->keymap) {
>> +             dev_err(&pdev->dev, "Not enough memory for keymap\n");
>> +             error = -ENOMEM;
>> +     }
>> +
>> +     matrix_keypad_build_keymap(NULL, NULL, kp->rows,
>> +                     kp->cols, kp->keymap, input);
>> +
>> +     /*
>> +     * This ISR will always execute in kernel thread context because of
>> +     * the need to access the SMSC over the I2C bus.
>> +     */
>> +     ret = devm_request_threaded_irq(dev, kp->irq, NULL, do_kp_irq,
>> +                     IRQF_TRIGGER_FALLING | IRQF_ONESHOT, pdev->name, kp);
>> +     if (ret) {
>> +             dev_dbg(&pdev->dev, "request_irq failed for irq no=%d\n",
>> +                     irq);
>> +             goto err2;
>> +     }
>> +
>> +     /* Enable smsc keypad interrupts */
>> +     ret = smsc_write(dev, SMSC_KP_INT_MASK, 0xff);
>> +     if (ret < 0)
>> +             goto err2;
>> +
>> +     return 0;
>> +
>> +err2:
>> +     input_unregister_device(input);
>> +     free_irq(kp->irq, NULL);
>
> you're using devm_request_threaded_irq, this is unnecessary
>
True. Will remove "free_irq"  from the code.
>> +err1:
>> +     input_free_device(input);
>> +     return ret;
>> +}
>> +
>> +static int smsc_remove(struct platform_device *pdev)
>> +{
>> +     struct smsc_keypad *kp = platform_get_drvdata(pdev);
>> +     free_irq(kp->irq, kp);
>
> ditto.
>
>
> --
> balbi


From sourav.poddar at ti.com  Tue Aug 21 07:31:47 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 21 Aug 2012 17:01:47 +0530
Subject: [PATCH 2/4] Input: keypad: Add smsc ece1099 keypad driver
In-Reply-To: <20120821104647.GU10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-3-git-send-email-sourav.poddar@ti.com>
 <20120821104647.GU10347@arwen.pp.htv.fi>
Message-ID: <CAKdam57p_K-ui1x+u-n07PQ8aweZocDsXoFTtdk_6CAVsC+xOg@mail.gmail.com>

Hi,

On Tue, Aug 21, 2012 at 4:16 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Tue, Aug 21, 2012 at 04:15:38PM +0530, Sourav Poddar wrote:
>> +static struct platform_driver smsc_driver = {
>> +     .driver = {
>> +             .name   = "smsc-keypad",
>> +             .of_match_table = of_match_ptr(smsc_keypad_dt_match),
>> +             .owner  = THIS_MODULE,
>> +     },
>> +     .probe          = smsc_probe,
>> +     .remove         = smsc_remove,
>
> one extra comment which I forgot. You probably should put your remove on
> __devexit and add __devexit_p(smsc_remove) here.
>
yes, Will do it.
> --
> balbi


From alan at linux.intel.com  Tue Aug 21 07:50:05 2012
From: alan at linux.intel.com (Alan Cox)
Date: Tue, 21 Aug 2012 12:50:05 +0100
Subject: [RFC/PATCH 02/13] serial: omap: always return IRQ_HANDLED
In-Reply-To: <1345540555-24359-3-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-3-git-send-email-balbi@ti.com>
Message-ID: <20120821125005.235926e0@bob.linux.org.uk>

On Tue, 21 Aug 2012 12:15:44 +0300
Felipe Balbi <balbi at ti.com> wrote:

> Even if we enter our IRQ handler just to notice
> that the our device didn't generate the IRQ,
> that still means "handling" and IRQ, so let's
> return IRQ_HANDLED.

That looks wrong - you'll defeat the stuck IRQ protection. If we didn't
cause the IRQ then we are IRQ_NONE ?



From grinberg at compulab.co.il  Tue Aug 21 07:37:00 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 21 Aug 2012 14:37:00 +0300
Subject: [PATCH v6 01/10] ARM: OMAP2+: nand: unify init functions
In-Reply-To: <8e0958354be60d026e7e03bd179509fcbe70957b.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <8e0958354be60d026e7e03bd179509fcbe70957b.1345524670.git.afzal@ti.com>
Message-ID: <503372DC.20504@compulab.co.il>

Hi Afzal,

Thanks for the patches!

On 08/21/12 13:45, Afzal Mohammed wrote:
> Helper function for updating nand platform data has been
> added the capability to take timing structure arguement.
> Usage of omap_nand_flash_init() has been replaced by modifed
> one, omap_nand_flash_init was doing things similar to
> board_nand_init except that NAND CS# were being acquired
> based on bootloader setting. As CS# is hardwired for a given
> board, acquiring gpmc CS# has been removed, and updated with
> the value on board.
> 
> NAND CS# used in beagle board & omap3evm was found to be CS0.
> Thomas Weber <thomas.weber.linux at googlemail.com> reported
> that value of devkit8000 to be CS0. Overo board was found
> to be using CS0 based on u-boot, while google grep says
> omap3touchbook too has CS0.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> Reviewed-by: Jon Hunter <jon-hunter at ti.com>

Acked-by: Igor Grinberg <grinberg at compulab.co.il>


-- 
Regards,
Igor.


From sourav.poddar at ti.com  Tue Aug 21 07:47:37 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 21 Aug 2012 17:17:37 +0530
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <20120821105333.GW10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
 <20120821105333.GW10347@arwen.pp.htv.fi>
Message-ID: <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>

Hi,

On Tue, Aug 21, 2012 at 4:23 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Tue, Aug 21, 2012 at 04:15:40PM +0530, Sourav Poddar wrote:
>> smsc can be used as an gpio io expander device also. So adding
>> support for configuring smsc pins as a gpio.
>>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Felipe Balbi <balbi at ti.com>
>> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>> ---
>>  drivers/gpio/Kconfig        |    7 +
>>  drivers/gpio/Makefile       |    1 +
>>  drivers/gpio/gpio-smscece.c |  373 +++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 381 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/gpio/gpio-smscece.c
>>
>> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
>> index b16c8a7..e883929 100644
>> --- a/drivers/gpio/Kconfig
>> +++ b/drivers/gpio/Kconfig
>> @@ -444,6 +444,13 @@ config GPIO_ADP5588_IRQ
>>         Say yes here to enable the adp5588 to be used as an interrupt
>>         controller. It requires the driver to be built in the kernel.
>>
>> +config GPIO_SMSCECE
>> +     tristate "SMSCECE 1099 I2C GPIO expander"
>> +     depends on I2C
>> +     help
>> +       This option enables support for 18 GPIOs found
>> +       on SMSC ECE 1099 GPIO Expanders.
>> +
>>  comment "PCI GPIO expanders:"
>>
>>  config GPIO_CS5535
>> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
>> index 153cace..7c803c5 100644
>> --- a/drivers/gpio/Makefile
>> +++ b/drivers/gpio/Makefile
>> @@ -12,6 +12,7 @@ obj-$(CONFIG_GPIO_74X164)   += gpio-74x164.o
>>  obj-$(CONFIG_GPIO_AB8500)    += gpio-ab8500.o
>>  obj-$(CONFIG_GPIO_ADP5520)   += gpio-adp5520.o
>>  obj-$(CONFIG_GPIO_ADP5588)   += gpio-adp5588.o
>> +obj-$(CONFIG_GPIO_SMSCECE)      += gpio-smscece.o
>>  obj-$(CONFIG_GPIO_AMD8111)   += gpio-amd8111.o
>>  obj-$(CONFIG_GPIO_ARIZONA)   += gpio-arizona.o
>>  obj-$(CONFIG_GPIO_BT8XX)     += gpio-bt8xx.o
>> diff --git a/drivers/gpio/gpio-smscece.c b/drivers/gpio/gpio-smscece.c
>> new file mode 100644
>> index 0000000..0cb0959
>> --- /dev/null
>> +++ b/drivers/gpio/gpio-smscece.c
>> @@ -0,0 +1,373 @@
>> +/*
>> + * GPIO Chip driver for smsc
>> + * SMSC I/O Expander and QWERTY Keypad Controller
>> + *
>> + * Copyright 2012 Texas Instruments Inc.
>> + *
>> + * Licensed under the GPL-2 or later.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/kernel.h>
>> +#include <linux/slab.h>
>> +#include <linux/init.h>
>> +#include <linux/i2c.h>
>> +#include <linux/gpio.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/irq.h>
>> +#include <linux/mfd/smsc.h>
>> +#include <linux/err.h>
>> +
>> +struct smsc_gpio {
>> +     struct device *dev;
>> +     struct smsc *smsc;
>> +     struct gpio_chip gpio_chip;
>> +     struct mutex lock;      /* protect cached dir, dat_out */
>> +     /* protect serialized access to the interrupt controller bus */
>> +     struct mutex irq_lock;
>> +     unsigned gpio_start;
>> +     int type;
>> +     int flags;
>> +     int irq;
>> +     int irq_base;
>> +     unsigned int gpio_base;
>> +     unsigned int dat_out[5];
>> +     unsigned int dir[5];
>> +     unsigned int int_lvl[5];
>> +     unsigned int int_en[5];
>> +     unsigned int irq_mask[5];
>> +     unsigned int irq_stat[5];
>> +};
>> +
>> +static int smsc_gpio_get_value(struct gpio_chip *chip, unsigned off)
>> +{
>> +     struct smsc_gpio *sg =
>> +             container_of(chip, struct smsc_gpio, gpio_chip);
>> +     unsigned int get;
>> +     return !!(smsc_read(sg->dev,
>> +             (SMSC_GPIO_DATA_IN_START + SMSC_BANK(off)) & SMSC_BIT(off),
>> +                                     &get));
>> +}
>> +
>> +static void smsc_gpio_set_value(struct gpio_chip *chip,
>> +                     unsigned off, int val)
>> +{
>> +     unsigned bank, bit;
>> +     struct smsc_gpio *sg =
>> +             container_of(chip, struct smsc_gpio, gpio_chip);
>> +
>> +     bank = SMSC_BANK(off);
>> +     bit = SMSC_BIT(off);
>> +
>> +     mutex_lock(&sg->lock);
>> +     if (val)
>> +             sg->dat_out[bank] |= bit;
>> +     else
>> +             sg->dat_out[bank] &= ~bit;
>> +
>> +     smsc_write(sg->dev, SMSC_GPIO_DATA_OUT_START + bank,
>> +                        sg->dat_out[bank]);
>> +     mutex_unlock(&sg->lock);
>> +}
>> +
>> +static int smsc_gpio_direction_input(struct gpio_chip *chip, unsigned off)
>> +{
>> +     unsigned int reg;
>> +     struct smsc_gpio *sg =
>> +         container_of(chip, struct smsc_gpio, gpio_chip);
>> +     int reg_dir;
>> +
>> +     mutex_lock(&sg->lock);
>> +     reg_dir = SMSC_CFG_START + off;
>> +     smsc_read(sg->dev, reg_dir, &reg);
>> +     reg |= SMSC_GPIO_INPUT_LOW;
>> +     mutex_unlock(&sg->lock);
>> +
>> +     return smsc_write(sg->dev, reg_dir, reg);
>> +}
>> +
>> +static int smsc_gpio_direction_output(struct gpio_chip *chip,
>> +                                      unsigned off, int val)
>> +{
>> +     unsigned int reg;
>> +     struct smsc_gpio *sg =
>> +         container_of(chip, struct smsc_gpio, gpio_chip);
>> +     int reg_dir;
>> +
>> +     mutex_lock(&sg->lock);
>> +     reg_dir = SMSC_CFG_START + off;
>> +     smsc_read(sg->dev, reg_dir, &reg);
>> +     reg |= SMSC_GPIO_OUTPUT_PP;
>> +     mutex_unlock(&sg->lock);
>> +
>> +     return smsc_write(sg->dev, reg_dir, reg);
>> +}
>> +
>> +static int smsc_gpio_to_irq(struct gpio_chip *chip, unsigned off)
>> +{
>> +     struct smsc_gpio *sg =
>> +             container_of(chip, struct smsc_gpio, gpio_chip);
>> +     return sg->irq_base + off;
>> +}
>> +
>> +static void smsc_irq_bus_lock(struct irq_data *d)
>> +{
>> +     struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
>> +
>> +     mutex_lock(&sg->irq_lock);
>> +}
>> +
>> +static void smsc_irq_bus_sync_unlock(struct irq_data *d)
>> +{
>> +     struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
>> +     int i;
>> +
>> +     for (i = 0; i < SMSC_BANK(SMSC_MAXGPIO); i++)
>> +             if (sg->int_en[i] ^ sg->irq_mask[i]) {
>> +                     sg->int_en[i] = sg->irq_mask[i];
>> +                     smsc_write(sg->dev, SMSC_GPIO_INT_MASK_START + i,
>> +                                        sg->int_en[i]);
>> +             }
>> +
>> +     mutex_unlock(&sg->irq_lock);
>> +}
>> +
>> +static void smsc_irq_mask(struct irq_data *d)
>> +{
>> +     struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
>> +     unsigned gpio = d->irq - sg->irq_base;
>> +
>> +     sg->irq_mask[SMSC_BANK(gpio)] &= ~SMSC_BIT(gpio);
>> +}
>> +
>> +static void smsc_irq_unmask(struct irq_data *d)
>> +{
>> +     struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
>> +     unsigned gpio = d->irq - sg->irq_base;
>> +
>> +     sg->irq_mask[SMSC_BANK(gpio)] |= SMSC_BIT(gpio);
>> +}
>> +
>> +static int smsc_irq_set_type(struct irq_data *d, unsigned int type)
>> +{
>> +     struct smsc_gpio *sg = irq_data_get_irq_chip_data(d);
>> +     uint16_t gpio = d->irq - sg->irq_base;
>> +     unsigned bank, bit;
>> +
>> +     if ((type & IRQ_TYPE_EDGE_BOTH)) {
>> +             dev_err(sg->dev, "irq %d: unsupported type %d\n",
>> +                     d->irq, type);
>> +             return -EINVAL;
>> +     }
>> +
>> +     bank = SMSC_BANK(gpio);
>> +     bit = SMSC_BIT(gpio);
>> +
>> +     if (type & IRQ_TYPE_LEVEL_HIGH)
>> +             sg->int_lvl[bank] |= bit;
>> +     else if (type & IRQ_TYPE_LEVEL_LOW)
>> +             sg->int_lvl[bank] &= ~bit;
>> +     else
>> +             return -EINVAL;
>
> this looks wrong. You could have a user who wants to trigger on both
> HIGH and LOW levels, no ?
>
Yes, I think there can be a scenario where gpio_keys are attached
to this driver and signals a "key press" at low and "key release" at
high. ?
 Will figure out a way to add support to check for case where
both High and low levels are used.
>> +     smsc_gpio_direction_input(&sg->gpio_chip, gpio);
>> +     smsc_write(sg->dev, SMSC_CFG_START + gpio,
>> +                     sg->int_lvl[bank]);
>> +
>> +     return 0;
>> +}
>> +
>> +static struct irq_chip smsc_irq_chip = {
>> +     .name                   = "smsc",
>> +     .irq_mask               = smsc_irq_mask,
>> +     .irq_unmask             = smsc_irq_unmask,
>> +     .irq_bus_lock           = smsc_irq_bus_lock,
>> +     .irq_bus_sync_unlock    = smsc_irq_bus_sync_unlock,
>> +     .irq_set_type           = smsc_irq_set_type,
>> +};
>> +
>> +static int smsc_gpio_read_intstat(struct smsc_gpio *sg,
>> +                             unsigned int *buf, int i)
>> +{
>> +     int ret = smsc_read(sg->dev,
>> +                     SMSC_GPIO_INT_STAT_START + i, buf);
>> +
>> +     if (ret < 0)
>> +             dev_err(sg->dev, "Read INT_STAT Error\n");
>> +
>> +     return ret;
>> +}
>> +
>> +static irqreturn_t smsc_irq_handler(int irq, void *devid)
>> +{
>> +     struct smsc_gpio *sg = devid;
>> +     unsigned int status, bank, pending;
>> +     int ret;
>> +     smsc_read(sg->dev, GRP_INT_STAT, &status);
>> +
>> +     if (!(status & SMSC_GPI_INT))
>> +             goto out;
>> +
>> +     for (bank = 0; bank <= SMSC_BANK(SMSC_MAXGPIO);
>> +             bank++) {
>> +             pending = sg->irq_stat[bank] & sg->irq_mask[bank];
>> +             ret = smsc_gpio_read_intstat(sg,
>> +                             &sg->irq_stat[bank], bank);
>> +             if (ret < 0)
>> +                     memset(&sg->irq_stat[bank], 0,
>> +                             ARRAY_SIZE(sg->irq_stat));
>> +
>> +             while (pending) {
>> +                     unsigned long   bit = __ffs(pending);
>> +                     unsigned int    irq;
>> +
>> +                     pending &= ~BIT(bit);
>> +                     irq = bit + sg->irq_base;
>> +                     handle_nested_irq(irq);
>> +             }
>> +     }
>> +
>> +out:
>> +     smsc_write(sg->dev, GRP_INT_STAT, status); /* Status is W1C */
>> +
>> +     return IRQ_HANDLED;
>> +}
>> +
>> +static int smsc_irq_setup(struct smsc_gpio *sg)
>> +{
>> +     unsigned gpio;
>> +     int ret;
>> +
>> +     mutex_init(&sg->irq_lock);
>> +
>> +     for (gpio = 0; gpio < sg->gpio_chip.ngpio; gpio++) {
>> +             int irq = gpio + sg->irq_base;
>> +             irq_set_chip_data(irq, sg);
>> +             irq_set_chip_and_handler(irq, &smsc_irq_chip,
>> +                             handle_level_irq);
>> +             irq_set_nested_thread(irq, 1);
>> +#ifdef CONFIG_ARM
>> +             set_irq_flags(irq, IRQF_VALID);
>> +#else
>> +             irq_set_noprobe(irq);
>> +#endif
>> +     }
>> +
>> +     ret = request_threaded_irq(sg->irq, NULL,
>> +                     smsc_irq_handler, sg->flags,
>> +                     "smsc_gpio", sg);
>
> would be nice to stick to devm_request_threaded_irq() like on the other
> patch.
>
Yes, will change.
>> +     if (ret) {
>> +             dev_err(sg->dev, "failed to request irq %d\n",
>> +                     sg->irq);
>> +     }
>> +
>> +     sg->gpio_chip.to_irq = smsc_gpio_to_irq;
>> +
>> +     return 0;
>> +}
>> +
>> +static int __devinit smsc_gpio_probe(struct platform_device *pdev)
>> +{
>> +     struct smsc_gpio *sg;
>> +     struct gpio_chip *gc;
>> +     struct smsc *smsc = dev_get_drvdata(pdev->dev.parent);
>> +     int ret, i, temp;
>> +     struct device *dev = &pdev->dev;
>> +     struct device_node *np = dev->of_node;
>> +     int irq_base;
>> +
>> +     sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
>> +     if (sg == NULL) {
>> +             dev_err(&pdev->dev, "failed to alloc memory\n");
>> +             return -ENOMEM;
>> +     }
>> +
>> +     sg->irq = platform_get_irq(pdev, 0);
>> +     if (np) {
>> +             of_property_read_u32(np, "gpio,base", &temp);
>> +             of_property_read_u32(np, "flags", &sg->flags);
>> +     }
>> +
>> +     gc = &sg->gpio_chip;
>> +     gc->direction_input = smsc_gpio_direction_input;
>> +     gc->direction_output = smsc_gpio_direction_output;
>> +     gc->get = smsc_gpio_get_value;
>> +     gc->set = smsc_gpio_set_value;
>> +     gc->can_sleep = 1;
>> +
>> +     gc->base = temp;
>> +     gc->ngpio = SMSC_MAXGPIO;
>> +     gc->owner = THIS_MODULE;
>> +
>> +     sg->smsc = smsc;
>> +     sg->dev = dev;
>> +     mutex_init(&sg->lock);
>> +
>> +     for (i = 0; i <= SMSC_BANK(SMSC_MAXGPIO); i++)
>> +             smsc_read(sg->dev, SMSC_GPIO_DATA_OUT_START + i,
>> +                                     &sg->dat_out[i]);
>> +
>> +     for (i = 0; i < SMSC_MAXGPIO; i++)
>> +             smsc_read(sg->dev, SMSC_CFG_START + i, &sg->dir[i]);
>> +
>> +     irq_base = irq_alloc_descs(-1, 0, sg->gpio_chip.ngpio, 0);
>> +     if (IS_ERR_VALUE(irq_base)) {
>> +             dev_err(sg->dev, "Fail to allocate IRQ descs\n");
>> +             return irq_base;
>> +     }
>> +     sg->irq_base = irq_base;
>> +
>> +     irq_domain_add_legacy(pdev->dev.of_node, sg->gpio_chip.ngpio,
>> +             sg->irq_base, 0, &irq_domain_simple_ops, NULL);
>> +
>> +     ret = smsc_irq_setup(sg);
>> +     if (ret)
>> +             goto err;
>> +
>> +     ret = gpiochip_add(&sg->gpio_chip);
>> +     if (ret)
>> +             goto err;
>> +
>> +     return 0;
>> +
>> +err:
>> +     kfree(sg);
>
> using devm_kzalloc(), not needed to free.
>
True, will change.
>> +
>> +     return ret;
>> +}
>> +
>> +static int __devexit smsc_gpio_remove(struct platform_device *pdev)
>> +{
>> +     struct smsc_gpio *sg = dev_get_drvdata(&pdev->dev);
>> +     int ret;
>> +
>> +     ret = gpiochip_remove(&sg->gpio_chip);
>> +     if (ret) {
>> +             dev_err(&pdev->dev, "gpiochip_remove failed %d\n", ret);
>> +             return ret;
>> +     }
>
> this will leak the irq (please move to devm_request_threaded_irq).
>
> It's also leaking irq_descs and irq_domain, you need to free those
> resources by calling irq_domain_remove and irq_free_descs.
>
Ok. will add the above apis in the next version.
> --
> balbi


From thomas.petazzoni at free-electrons.com  Tue Aug 21 07:50:45 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 21 Aug 2012 13:50:45 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <CABJ1b_RVaSjsneDCvejSMot0ZHDr1dmeroVRDUNMF2y83UGXNA@mail.gmail.com>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
 <20120817152156.4d91ba16@skate>
 <20120819012303.GX22226@titan.lakedaemon.net>
 <20120821114630.545fb771@skate>
 <CABJ1b_RVaSjsneDCvejSMot0ZHDr1dmeroVRDUNMF2y83UGXNA@mail.gmail.com>
Message-ID: <20120821135045.58e2a633@skate>

Le Tue, 21 Aug 2012 12:37:24 +0200,
Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com> a ?crit :

> I have reworked addr-map to allow for both Armada 370/XP and Orion SoCs
> merging into mach-mvebu. Instead of reusing PLAT_ORION this is totally
> independent but reusing as much code as possible. I can send it hopefully
> today if I get it cleaned up. I also have irq-mvebu, irq-orion, and time-mvebu
> patches that merge code. With that patches booting Dove into mach-mvebu
> works until DMA kicks in because XOR hasn't event touched for DT support
> and is still missing.
> 
> Armada 370/XP should still work as they do with current patches in for-3.7
> with little changes in DT. But that of course must be tested by you.

Ok, I will look at your code, but the purpose of
PLAT_ORION/PLAT_ORION_LEGACY was not only to re-use the addr-map code,
but also to allow drivers to access the header files containing their
platform_data structure and other stuff (i.e, all the header files from
arch/arm/plat-orion/include/). How do you handle this problem if
MACH_MVEBU is not a PLAT_ORION platform?

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Tue Aug 21 07:51:24 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 12:51:24 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <20120820143653.GE26991@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de> <20120820113427.GN8450@gmail.com>
 <20120820143653.GE26991@opensource.wolfsonmicro.com>
Message-ID: <20120821115123.GE26899@gmail.com>

On Mon, Aug 20, 2012 at 03:36:53PM +0100, Mark Brown wrote:
> On Mon, Aug 20, 2012 at 12:34:31PM +0100, Lee Jones wrote:
> > From: Lee Jones <lee.jones at linaro.org>
> > Date: Fri, 27 Jul 2012 08:50:05 +0100
> > Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
> > 
> > We continue to allow the AB8500 CODEC to be registered via the AB8500
> > Multi Functional Device API, only this time we extract its configuration
> > from the Device Tree binary.
> 
> Please resend this series with all the acks you've got rather than
> mixing incremental updates in like this.

I'm waiting until I have a few more Acks before I resend the entire
patch-set again. Actually it's you and one other that I'm waiting for
to review (and Ack as necessary) the ones requested by Linus, then 
resend with the corrections.

> Please also send patches in
> the format documented in SubmittingPatches.

That's a big document, most of which I guess I'm adhering to. Care to
be a little more specific?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From balbi at ti.com  Tue Aug 21 07:54:27 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 14:54:27 +0300
Subject: [RFC/PATCH 02/13] serial: omap: always return IRQ_HANDLED
In-Reply-To: <20120821125005.235926e0@bob.linux.org.uk>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345540555-24359-3-git-send-email-balbi@ti.com>
 <20120821125005.235926e0@bob.linux.org.uk>
Message-ID: <20120821115426.GC10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 12:50:05PM +0100, Alan Cox wrote:
> On Tue, 21 Aug 2012 12:15:44 +0300
> Felipe Balbi <balbi at ti.com> wrote:
> 
> > Even if we enter our IRQ handler just to notice
> > that the our device didn't generate the IRQ,
> > that still means "handling" and IRQ, so let's
> > return IRQ_HANDLED.
> 
> That looks wrong - you'll defeat the stuck IRQ protection. If we didn't
> cause the IRQ then we are IRQ_NONE ?

that's true. I'll drop this patch from the list. My bad.

-- 
balbi
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From linus.walleij at linaro.org  Tue Aug 21 08:02:18 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:02:18 +0200
Subject: [PATCH v2 2/4] pinctrl: add exynos4210 specific extensions for
 samsung pinctrl driver
In-Reply-To: <1345060656-32201-3-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdYiJOkHrjZ22_0onRHc0ApmBLj+tXPa4SrPo2h0d=fJHA@mail.gmail.com>

On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> Add information about the Exynos4210 pin banks and driver data which is
> used by the Samsung pinctrl driver. In addition to this, the support for
> external gpio and wakeup interrupt support is included and hooked up with
> the Samsung pinctrl driver.

OK...

> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> +config PINCTRL_EXYNOS4
> +       bool "Pinctrl driver data for Exynos4 SoC"
> +       depends on ARCH_EXYNOS4 && OF

Since you depend on PINCTRL_SAMSUNG which depends
on OF you don't need to depend on OF here.

> +       depends on PINCTRL_SAMSUNG
> +       select PINMUX
> +       select PINCONF

So as noted in the main driver, let PINCTRL_SAMSUNG
select PINMUX and PINCONF and you need only select
PINCTRL_SAMSUNG here.

> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
(...)
> +#include <linux/interrupt.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irq.h>
> +#include <linux/of_irq.h>

Do you need these includes? Didn't you put them
all in "pinctrl-samsung.h"?

Overall this looks good and straight-forward, but I cannot figure
out how the samsung_pinctrl_soc_data is passed to the main
driver, it seems to be through some DT node but I cannot figure
this out. Can you explain this?

Yours,
Linus Walleij


From lee.jones at linaro.org  Tue Aug 21 08:02:46 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 13:02:46 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821110329.GA7995@opensource.wolfsonmicro.com>
References: <20120820083640.GH8450@gmail.com>
 <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
Message-ID: <20120821120243.GF26899@gmail.com>

On Tue, Aug 21, 2012 at 12:03:29PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 11:54:14AM +0100, Lee Jones wrote:
> > On Tue, Aug 21, 2012 at 10:50:27AM +0100, Mark Brown wrote:
> 
> > > What makes you say this?  This is just a convenience for finding a
> > > domain, irqdomains are *completely* indepentant of device tree.
> 
> > How can you say that? I think you mean _can_ be independent of DT. If
> > that's what you mean then yes, that's true. All I'm saying is we need
> 
> No, I really mean what I'm saying.  Device tree builds on irqdomains,
> not the other way around.

This is just semantics.
 
> > another way to get hold of the domain, because the only way to obtain
> > it without having direct access is via a device node.
> 
> This doesn't actually hold.

Okay, besides irq_find_host(struct device_node *np), how else can you fetch
a domain from the irqdomain?

> > > > - I know that you have interest in pushing the functionality into the
> > > > IRQ domain subsystem, but I'm struggling to see how. It's calling into
> > > > the IRQ domain where we're seeing issues in the first place, specifically
> > > > irq_create_mapping(). How about if we passed 'irq_domain' as a parameter
> > > > when requesting the IRQ? That way we can pass the correct IRQ without
> > > > worry of conversion. If 'irq_domain' is !NULL the IRQ management subsystem
> > > > can do the necessary conversions. If 'irq_domain' is NULL it continues to
> > > > use the requested IRQ as a virq.
> 
> > > This is totally orthogonal to doing the mapping in the MFD subsystem
> > > which is the issue here.
> 
> > Again, I only mentioned this because you said you wanted it to be handled
> > by the irqdomain.
> 
> The *mapping* should be being handled in irqdomain.
> 
> > I'll code up the second suggestion now.
> 
> I've already done this.

What have you done already? 

Why make suggestions if you're just going to do the work yourself?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linus.walleij at linaro.org  Tue Aug 21 08:04:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:04:23 +0200
Subject: [PATCH v2 4/4] ARM: EXYNOS: skip wakeup interrupt setup if
 pinctrl driver is used
In-Reply-To: <1345060656-32201-5-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-5-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdaxSZZQwefN3FNvv3ctXFHqaLZoAZ5f8CVu7Tx9n6-v1Q@mail.gmail.com>

On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> Pinctrl driver includes support for configuring the external wakeup
> interrupts. On exynos platforms that use pinctrl driver, the setup
> of wakeup interrupts in the exynos platform code can be skipped.
>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>

> +#ifdef CONFIG_OF

Don't you actually want to use:

#fidef CONFIG_PINCTRL_SAMSUNG

here? CONFIG_OF is a bit vague.

Yours,
Linus Walleij


From balbi at ti.com  Tue Aug 21 08:00:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:00:54 +0300
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
 <20120821105333.GW10347@arwen.pp.htv.fi>
 <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>
Message-ID: <20120821120052.GD10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 05:17:37PM +0530, Poddar, Sourav wrote:
> >> +     if (type & IRQ_TYPE_LEVEL_HIGH)
> >> +             sg->int_lvl[bank] |= bit;
> >> +     else if (type & IRQ_TYPE_LEVEL_LOW)
> >> +             sg->int_lvl[bank] &= ~bit;
> >> +     else
> >> +             return -EINVAL;
> >
> > this looks wrong. You could have a user who wants to trigger on both
> > HIGH and LOW levels, no ?
> >
> Yes, I think there can be a scenario where gpio_keys are attached
> to this driver and signals a "key press" at low and "key release" at
> high. ?
>  Will figure out a way to add support to check for case where
> both High and low levels are used.

could probably be done on a separate patch, maybe... Just now I saw that
HIGH and LOW levels use the same bit.

-- 
balbi
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From linus.walleij at linaro.org  Tue Aug 21 08:05:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:05:22 +0200
Subject: [PATCH v2 3/4] gpio: exynos4: skip gpiolib registration if
 pinctrl driver is used
In-Reply-To: <1345060656-32201-4-git-send-email-thomas.abraham@linaro.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdYc-iMgKBNfRmxUFftK78G77qQ8h_Rr5td1-95NGo7wZg@mail.gmail.com>

On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> Pinctrl driver, when enabled, registers all the gpio pins and hence the
> registration of gpio pins by this driver can be skipped.
>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>

> +#ifdef CONFIG_OF

Wouldn't it be better to use
#ifdef CONFIG_PINCTRL_SAMSUNG?

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Tue Aug 21 08:12:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 21 Aug 2012 13:12:56 +0100
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous
 Memory Allocator
In-Reply-To: <201208202001.23443.arnd@arndb.de>
References: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
 <201208202001.23443.arnd@arndb.de>
Message-ID: <20120821121256.GT18957@n2100.arm.linux.org.uk>

On Mon, Aug 20, 2012 at 08:01:23PM +0000, Arnd Bergmann wrote:
> The patch looks simple, but I want a better explanation for it.
> When we went through all possible cases, we decided that:
> 
> * ARMv6+ need CMA to avoid the double mapping problem.
> * ARMv4/v5 cannot generally use CMA because it doesn't work
>   together with DMABOUNCE. I don't remember if it was the
>   only problem, but I definitely remember this was intentional.
> * We want a common kernel for all ARMv6+ eventually, and a
>   separate kernel for all ARMv4/v5 ones.
> 
> If the reasoning has changed, please try to explain the full
> situation.

Indeed.

> On a related topic, what happened to the idea that
> ARMv6+ is broken without CMA? I noticed that it's optional
> now.

With Marek's patch, it's always selected for MMU-based builds (it can't
be disabled).  Before the patch, it was always selected for V6 and later
CPUs.

And the description doesn't make sense:

"Contiguous Memory Allocator requires only paging and MMU enabled not
particular CPU architectures,"

what does "only paging and MMU enabled" mean?  Are you trying to say that
CMA only requires a kernel with MMU support?


From hdoyu at nvidia.com  Tue Aug 21 08:15:21 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 21 Aug 2012 14:15:21 +0200
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <20120821142235.97984abc9ad98d01015a3338@nvidia.com>
References: <1343636899-19508-1-git-send-email-m.szyprowski@samsung.com><1343636899-19508-3-git-send-email-m.szyprowski@samsung.com><20120821142235.97984abc9ad98d01015a3338@nvidia.com>
Message-ID: <20120821.151521.702882672715065253.hdoyu@nvidia.com>

Hiroshi Doyu <hdoyu at nvidia.com> wrote @ Tue, 21 Aug 2012 13:22:35 +0200:

> Hi,
> 
> On Mon, 30 Jul 2012 10:28:19 +0200
> Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> 
> > This patch changes dma-mapping subsystem to use generic vmalloc areas
> > for all consistent dma allocations. This increases the total size limit
> > of the consistent allocations and removes platform hacks and a lot of
> > duplicated code.
> > 
> > Atomic allocations are served from special pool preallocated on boot,
> > because vmalloc areas cannot be reliably created in atomic context.
> > 
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Reviewed-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  Documentation/kernel-parameters.txt |    2 +-
> >  arch/arm/include/asm/dma-mapping.h  |    2 +-
> >  arch/arm/mm/dma-mapping.c           |  486 ++++++++++++-----------------------
> >  arch/arm/mm/mm.h                    |    3 +
> >  include/linux/vmalloc.h             |    1 +
> >  mm/vmalloc.c                        |   10 +-
> >  6 files changed, 181 insertions(+), 323 deletions(-)
> > 
> ...
> > @@ -1117,61 +984,32 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
> >   * Create a CPU mapping for a specified pages
> >   */
> >  static void *
> > -__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
> > +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
> > +                   const void *caller)
> >  {
> > -       struct arm_vmregion *c;
> > -       size_t align;
> > -       size_t count = size >> PAGE_SHIFT;
> > -       int bit;
> > +       unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
> > +       struct vm_struct *area;
> > +       unsigned long p;
> > 
> > -       if (!consistent_pte[0]) {
> > -               pr_err("%s: not initialised\n", __func__);
> > -               dump_stack();
> > +       area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
> > +                                 caller);
> > +       if (!area)
> 
> This patch replaced the custom "consistent_pte" with
> get_vm_area_caller()", which breaks the compatibility with the
> existing driver. This causes the following kernel oops(*1). That
> driver has called dma_pool_alloc() to allocate memory from the
> interrupt context, and it hits BUG_ON(in_interrpt()) in
> "get_vm_area_caller()"(*2). Regardless of the badness of allocation
> from interrupt handler in the driver, I have the following question.
> 
> The following "__get_vm_area_node()" can take gfp_mask, it means that
> this function is expected to be called from atomic context, but why
> it's _NOT_ allowed _ONLY_ from interrupt context?
> 
> According to the following definitions, "in_interrupt()" is in "in_atomic()".
> 
> #define in_interrupt()	(preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK | NMI_MASK))
> #define in_atomic()	((preempt_count() & ~PREEMPT_ACTIVE) != 0)
> 
> Does anyone know why BUG_ON(in_interrupt()) is set in __get_vm_area_node(*3)?

For arm_dma_alloc(), it allocates from the pool if GFP_ATOMIC, but for
arm_iommu_alloc_attrs() doesn't have pre-allocate pool at all, and it
always call "get_vm_area_caller()". That's why it hits BUG(). But
still I don't understand why it's not BUG_ON(in_atomic) as Russell
already pointed out(*1).

*1: http://article.gmane.org/gmane.linux.kernel.mm/76708


From balbi at ti.com  Tue Aug 21 08:15:58 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:15:58 +0300
Subject: [PATCH v2 00/13] OMAP Serial patches
In-Reply-To: <1345540555-24359-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-1-git-send-email-balbi@ti.com>

Hi guys,

here's a series of cleanup patches to the OMAP serial
driver. A later series could be made re-implementing
DMA using the DMA Engine API. Note that for RX DMA
we could be using RX Timeout IRQ as a hint that we better
use PIO instead ;-)

All patches were tested on my pandaboard, but I'd really
like to receive Tested-by on other platforms.

After this goes in, I'll probably try to get UART wakeup
working again and only after that look at DMA.

Changes since v1:

	. improved commit log on patch 9/13 (formerly 10/13)
	. removed patch 2/13
	. added a new patch switching from spin_lock_irqsave() to spin_lock and
		spin_unlock_irqrestore to spin_unlock

Retested with my pandaboard, UART continues to work:

 # grep -i uart /proc/interrupts
 106:        124          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        189          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        255          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        321          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        387          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        453          0       GIC  OMAP UART2
 #  grep -i uart /proc/interrupts
 106:        519          0       GIC  OMAP UART2

cheers

ps: if anyone knows a better test for UART, let me know.

for convenience of anyone testing, patches are available on my git tree [1] on
branch uart

[1] git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart

Felipe Balbi (13):
  serial: omap: define and use to_uart_omap_port()
  serial: omap: define helpers for pdata function pointers
  serial: omap: don't access the platform_device
  serial: omap: drop DMA support
  serial: add OMAP-specific defines
  serial: omap: simplify IRQ handling
  serial: omap: refactor receive_chars() into rdi/rlsi handlers
  serial: omap: move THRE check to transmit_chars()
  serial: omap: stick to put_autosuspend
  serial: omap: set dev->drvdata before enabling pm_runtime
  serial: omap: drop unnecessary check from remove
  serial: omap: make sure to suspend device before remove
  serial: omap: don't save IRQ flags on hardirq

 arch/arm/mach-omap2/serial.c                  |  15 +-
 arch/arm/plat-omap/include/plat/omap-serial.h |  12 +-
 drivers/tty/serial/omap-serial.c              | 713 +++++++++-----------------
 include/linux/serial_reg.h                    |   4 +
 4 files changed, 254 insertions(+), 490 deletions(-)

-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:15:59 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:15:59 +0300
Subject: [PATCH v2 01/13] serial: omap: define and use to_uart_omap_port()
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-2-git-send-email-balbi@ti.com>

current code only works because struct uart_port
is the first member on the uart_omap_port structure.

If, for whatever reason, someone puts another
member as the first of the structure, that cast
won't work anymore. In order to be safe, let's use
a container_of() which, for now, gets optimized into
a cast anyway.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h |  2 ++
 drivers/tty/serial/omap-serial.c              | 36 +++++++++++++--------------
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725..f3b35d9 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -137,4 +137,6 @@ struct uart_omap_port {
 	struct work_struct	qos_work;
 };
 
+#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
+
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d3cda0c..5c0d0bc 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -141,7 +141,7 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 
 static void serial_omap_enable_ms(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
@@ -153,7 +153,7 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 
 	if (up->use_dma &&
@@ -186,7 +186,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	if (up->use_dma)
@@ -307,7 +307,7 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 
 static void serial_omap_start_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
@@ -449,7 +449,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 
 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
@@ -464,7 +464,7 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 
 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 	unsigned int ret = 0;
 
@@ -487,7 +487,7 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char mcr = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
@@ -511,7 +511,7 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
@@ -528,7 +528,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 
 static int serial_omap_startup(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	int retval;
 
@@ -606,7 +606,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 static void serial_omap_shutdown(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
@@ -721,7 +721,7 @@ static void
 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 			struct ktermios *old)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char cval = 0;
 	unsigned char efr = 0;
 	unsigned long flags = 0;
@@ -932,7 +932,7 @@ static void
 serial_omap_pm(struct uart_port *port, unsigned int state,
 	       unsigned int oldstate)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char efr;
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
@@ -971,7 +971,7 @@ static int serial_omap_request_port(struct uart_port *port)
 
 static void serial_omap_config_port(struct uart_port *port, int flags)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 							up->port.line);
@@ -989,7 +989,7 @@ serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 static const char *
 serial_omap_type(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 	return up->name;
@@ -1032,7 +1032,7 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
 
 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	wait_for_xmitr(up);
@@ -1042,7 +1042,7 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 
 static int serial_omap_poll_get_char(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
 	pm_runtime_get_sync(&up->pdev->dev);
@@ -1065,7 +1065,7 @@ static struct uart_driver serial_omap_reg;
 
 static void serial_omap_console_putchar(struct uart_port *port, int ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
@@ -1341,7 +1341,7 @@ static void serial_omap_continue_tx(struct uart_omap_port *up)
 
 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)data;
+	struct uart_omap_port *up = data;
 	struct circ_buf *xmit = &up->port.state->xmit;
 
 	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:00 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:00 +0300
Subject: [PATCH v2 02/13] serial: omap: define helpers for pdata function
 pointers
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-3-git-send-email-balbi@ti.com>

this patch is in preparation to a few other changes
which will align on the prototype for function
pointers passed through pdata.

It also helps cleaning up the driver a little by
agregating checks for pdata in a single location.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 66 ++++++++++++++++++++++++++++------------
 1 file changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 5c0d0bc..6814a26 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -101,6 +101,40 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 	serial_out(up, UART_FCR, 0);
 }
 
+static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (!pdata->get_context_loss_count)
+		return 0;
+
+	return pdata->get_context_loss_count(&up->pdev->dev);
+}
+
+static void serial_omap_set_forceidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_forceidle)
+		pdata->set_forceidle(up->pdev);
+}
+
+static void serial_omap_set_noidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_noidle)
+		pdata->set_noidle(up->pdev);
+}
+
+static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->enable_wakeup)
+		pdata->enable_wakeup(up->pdev, enable);
+}
+
 /*
  * serial_omap_get_divisor - calculate divisor value
  * @port: uart port info
@@ -177,8 +211,8 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata && pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+	if (!up->use_dma && pdata)
+		serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(&up->pdev->dev);
 	pm_runtime_put_autosuspend(&up->pdev->dev);
@@ -308,7 +342,6 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
 	int ret = 0;
@@ -316,8 +349,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	if (!up->use_dma) {
 		pm_runtime_get_sync(&up->pdev->dev);
 		serial_omap_enable_ier_thri(up);
-		if (pdata && pdata->set_noidle)
-			pdata->set_noidle(up->pdev);
+		serial_omap_set_noidle(up);
 		pm_runtime_mark_last_busy(&up->pdev->dev);
 		pm_runtime_put_autosuspend(&up->pdev->dev);
 		return;
@@ -1648,28 +1680,26 @@ static int serial_omap_runtime_suspend(struct device *dev)
 	if (!up)
 		return -EINVAL;
 
-	if (!pdata || !pdata->enable_wakeup)
+	if (!pdata)
 		return 0;
 
-	if (pdata->get_context_loss_count)
-		up->context_loss_cnt = pdata->get_context_loss_count(dev);
+	up->context_loss_cnt = serial_omap_get_context_loss_count(up);
 
 	if (device_may_wakeup(dev)) {
 		if (!up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, true);
+			serial_omap_enable_wakeup(up, true);
 			up->wakeups_enabled = true;
 		}
 	} else {
 		if (up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, false);
+			serial_omap_enable_wakeup(up, false);
 			up->wakeups_enabled = false;
 		}
 	}
 
 	/* Errata i291 */
-	if (up->use_dma && pdata->set_forceidle &&
-			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		pdata->set_forceidle(up->pdev);
+	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
+		serial_omap_set_forceidle(up);
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
@@ -1683,17 +1713,15 @@ static int serial_omap_runtime_resume(struct device *dev)
 	struct omap_uart_port_info *pdata = dev->platform_data;
 
 	if (up && pdata) {
-		if (pdata->get_context_loss_count) {
-			u32 loss_cnt = pdata->get_context_loss_count(dev);
+			u32 loss_cnt = serial_omap_get_context_loss_count(up);
 
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
-		}
 
 		/* Errata i291 */
-		if (up->use_dma && pdata->set_noidle &&
-				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-			pdata->set_noidle(up->pdev);
+		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
+				up->use_dma)
+			serial_omap_set_noidle(up);
 
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:01 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:01 +0300
Subject: [PATCH v2 03/13] serial: omap: don't access the platform_device
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-4-git-send-email-balbi@ti.com>

The driver doesn't need to know about its platform_device.

Everything the driver needs can be done through the
struct device pointer. In case we need to use the
OMAP-specific PM function pointers, those can make
sure to find the device's platform_device pointer
so they can find the struct omap_device through
pdev->archdata field.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/mach-omap2/serial.c                  |  15 ++--
 arch/arm/plat-omap/include/plat/omap-serial.h |  10 +--
 drivers/tty/serial/omap-serial.c              | 124 +++++++++++++-------------
 3 files changed, 76 insertions(+), 73 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c7..8f07841 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
 };
 
 #ifdef CONFIG_PM
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	if (!od)
@@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
  * in Smartidle Mode When Configured for DMA Operations.
  * WA: configure uart in force idle mode.
  */
-static void omap_uart_set_noidle(struct platform_device *pdev)
+static void omap_uart_set_noidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
 
-static void omap_uart_set_smartidle(struct platform_device *pdev)
+static void omap_uart_set_smartidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 	u8 idlemode;
 
@@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev)
 }
 
 #else
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct platform_device *pdev) {}
-static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+static void omap_uart_set_noidle(struct device *dev) {}
+static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index f3b35d9..743ac80 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,7 +18,7 @@
 #define __OMAP_SERIAL_H__
 
 #include <linux/serial_core.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
 #include <linux/pm_qos.h>
 
 #include <plat/mux.h>
@@ -71,9 +71,9 @@ struct omap_uart_port_info {
 	unsigned int		dma_rx_poll_rate;
 
 	int (*get_context_loss_count)(struct device *);
-	void (*set_forceidle)(struct platform_device *);
-	void (*set_noidle)(struct platform_device *);
-	void (*enable_wakeup)(struct platform_device *, bool);
+	void (*set_forceidle)(struct device *);
+	void (*set_noidle)(struct device *);
+	void (*enable_wakeup)(struct device *, bool);
 };
 
 struct uart_omap_dma {
@@ -105,7 +105,7 @@ struct uart_omap_dma {
 struct uart_omap_port {
 	struct uart_port	port;
 	struct uart_omap_dma	uart_dma;
-	struct platform_device	*pdev;
+	struct device		*dev;
 
 	unsigned char		ier;
 	unsigned char		lcr;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6814a26..6ab3582 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -103,36 +103,36 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 
 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (!pdata->get_context_loss_count)
 		return 0;
 
-	return pdata->get_context_loss_count(&up->pdev->dev);
+	return pdata->get_context_loss_count(up->dev);
 }
 
 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+		pdata->set_forceidle(up->dev);
 }
 
 static void serial_omap_set_noidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_noidle)
-		pdata->set_noidle(up->pdev);
+		pdata->set_noidle(up->dev);
 }
 
 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->enable_wakeup)
-		pdata->enable_wakeup(up->pdev, enable);
+		pdata->enable_wakeup(up->dev, enable);
 }
 
 /*
@@ -168,8 +168,8 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 		omap_free_dma(up->uart_dma.rx_dma_channel);
 		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
 		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 }
 
@@ -179,16 +179,16 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (up->use_dma &&
 		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
@@ -201,11 +201,11 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		omap_stop_dma(up->uart_dma.tx_dma_channel);
 		omap_free_dma(up->uart_dma.tx_dma_channel);
 		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
 		up->ier &= ~UART_IER_THRI;
 		serial_out(up, UART_IER, up->ier);
@@ -214,22 +214,22 @@ static void serial_omap_stop_tx(struct uart_port *port)
 	if (!up->use_dma && pdata)
 		serial_omap_set_forceidle(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->use_dma)
 		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static inline void receive_chars(struct uart_omap_port *up,
@@ -347,11 +347,11 @@ static void serial_omap_start_tx(struct uart_port *port)
 	int ret = 0;
 
 	if (!up->use_dma) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		serial_omap_enable_ier_thri(up);
 		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return;
 	}
 
@@ -361,7 +361,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	xmit = &up->port.state->xmit;
 
 	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
 				"UART Tx DMA",
 				(void *)uart_tx_dma_callback, up,
@@ -444,11 +444,11 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	unsigned int iir, lsr;
 	unsigned long flags;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
 	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return IRQ_NONE;
 	}
 
@@ -472,8 +472,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 		transmit_chars(up);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	up->port_activity = jiffies;
 	return IRQ_HANDLED;
@@ -485,12 +485,12 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return ret;
 }
 
@@ -500,9 +500,9 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 	unsigned int status;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -534,11 +534,11 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	if (mctrl & TIOCM_LOOP)
 		mcr |= UART_MCR_LOOP;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -547,7 +547,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 	if (break_state == -1)
 		up->lcr |= UART_LCR_SBC;
@@ -555,7 +555,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -574,7 +574,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Clear the FIFO buffers and disable them.
 	 * (they will be reenabled in set_termios())
@@ -630,8 +630,8 @@ static int serial_omap_startup(struct uart_port *port)
 	/* Enable module level wake up */
 	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
 	return 0;
 }
@@ -643,7 +643,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Disable interrupts from this port
 	 */
@@ -678,7 +678,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 		up->uart_dma.rx_buf = NULL;
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -807,7 +807,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	 * Ok, we're now changing the port state. Do it with
 	 * interrupts disabled.
 	 */
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 
 	/*
@@ -956,7 +956,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -969,7 +969,7 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 	efr = serial_in(up, UART_EFR);
 	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
@@ -980,14 +980,14 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 	serial_out(up, UART_EFR, efr);
 	serial_out(up, UART_LCR, 0);
 
-	if (!device_may_wakeup(&up->pdev->dev)) {
+	if (!device_may_wakeup(up->dev)) {
 		if (!state)
-			pm_runtime_forbid(&up->pdev->dev);
+			pm_runtime_forbid(up->dev);
 		else
-			pm_runtime_allow(&up->pdev->dev);
+			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -1066,10 +1066,10 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -1077,13 +1077,13 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = serial_in(up, UART_LSR);
 	if (!(status & UART_LSR_DR))
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return status;
 }
 
@@ -1112,7 +1112,7 @@ serial_omap_console_write(struct console *co, const char *s,
 	unsigned int ier;
 	int locked = 1;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 
 	local_irq_save(flags);
 	if (up->port.sysrq)
@@ -1146,8 +1146,8 @@ serial_omap_console_write(struct console *co, const char *s,
 	if (up->msr_saved_flags)
 		check_modem_status(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	if (locked)
 		spin_unlock(&up->port.lock);
 	local_irq_restore(flags);
@@ -1309,7 +1309,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
 	int ret = 0;
 
 	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
 				"UART Rx DMA",
 				(void *)uart_rx_dma_callback, up,
@@ -1421,7 +1421,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 		break;
 	default:
-		dev_warn(&up->pdev->dev,
+		dev_warn(up->dev,
 			"Unknown %s revision, defaulting to highest\n",
 			up->name);
 		/* highest possible revision */
@@ -1502,7 +1502,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (!up)
 		return -ENOMEM;
 
-	up->pdev = pdev;
+	up->dev = &pdev->dev;
 	up->port.dev = &pdev->dev;
 	up->port.type = PORT_OMAP;
 	up->port.iotype = UPIO_MEM;
@@ -1599,7 +1599,7 @@ static int serial_omap_remove(struct platform_device *dev)
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
 	if (up) {
-		pm_runtime_disable(&up->pdev->dev);
+		pm_runtime_disable(up->dev);
 		uart_remove_one_port(&serial_omap_reg, &up->port);
 		pm_qos_remove_request(&up->pm_qos_request);
 	}
@@ -1634,7 +1634,7 @@ static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
 		timeout--;
 		if (!timeout) {
 			/* Should *never* happen. we warn and carry on */
-			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
+			dev_crit(up->dev, "Errata i202: timedout %x\n",
 						serial_in(up, UART_LSR));
 			break;
 		}
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:04 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:04 +0300
Subject: [PATCH v2 06/13] serial: omap: simplify IRQ handling
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-7-git-send-email-balbi@ti.com>

quite a few changes here, though they are
pretty obvious. In summary we're making sure
to detect which interrupt type we need to
handle before calling the underlying interrupt
handling procedure.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 48 +++++++++++++++++++++++++++++++---------
 1 file changed, 37 insertions(+), 11 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 16808b6..2d3e64e 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -350,33 +350,59 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
 	unsigned int iir, lsr;
+	unsigned int type;
 	unsigned long flags;
+	irqreturn_t ret = IRQ_HANDLED;
 
+	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
+again:
 	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return IRQ_NONE;
+		ret = IRQ_NONE;
+		goto out;
 	}
 
-	spin_lock_irqsave(&up->port.lock, flags);
 	lsr = serial_in(up, UART_LSR);
-	if (iir & UART_IIR_RLSI) {
+
+	/* extract IRQ type from IIR register */
+	type = iir & 0x3e;
+
+	switch (type) {
+	case UART_IIR_MSI:
+		check_modem_status(up);
+		break;
+	case UART_IIR_THRI:
+		if (lsr & UART_LSR_THRE)
+			transmit_chars(up);
+		break;
+	case UART_IIR_RDI:
 		if (lsr & UART_LSR_DR)
 			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RLSI:
+		if (lsr & UART_LSR_BRK_ERROR_BITS)
+			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RX_TIMEOUT:
+		receive_chars(up, &lsr);
+		break;
+	case UART_IIR_CTS_RTS_DSR:
+		iir = serial_in(up, UART_IIR);
+		goto again;
+	case UART_IIR_XOFF:
+		/* FALLTHROUGH */
+	default:
+		break;
 	}
 
-	check_modem_status(up);
-	if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
-		transmit_chars(up);
-
+out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-
 	up->port_activity = jiffies;
-	return IRQ_HANDLED;
+
+	return ret;
 }
 
 static unsigned int serial_omap_tx_empty(struct uart_port *port)
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:03 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:03 +0300
Subject: [PATCH v2 05/13] serial: add OMAP-specific defines
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-6-git-send-email-balbi@ti.com>

OMAP has some extra Interrupt types which can
be really useful for SW. Let's define them
so we can later use those in OMAP's serial driver.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 include/linux/serial_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 8ce70d7..5ed325e 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -40,6 +40,10 @@
 
 #define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
 
+#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
+
 #define UART_FCR	2	/* Out: FIFO Control Register */
 #define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
 #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-- 
1.7.12.rc3



From sourav.poddar at ti.com  Tue Aug 21 08:20:28 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Tue, 21 Aug 2012 17:50:28 +0530
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <20120821120052.GD10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
 <20120821105333.GW10347@arwen.pp.htv.fi>
 <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>
 <20120821120052.GD10347@arwen.pp.htv.fi>
Message-ID: <CAKdam55SqXiCGv766yxoY1GdDjxNCYNaDdNZPaeLTAXc+3+c6g@mail.gmail.com>

Hi,

On Tue, Aug 21, 2012 at 5:30 PM, Felipe Balbi <balbi at ti.com> wrote:
> Hi,
>
> On Tue, Aug 21, 2012 at 05:17:37PM +0530, Poddar, Sourav wrote:
>> >> +     if (type & IRQ_TYPE_LEVEL_HIGH)
>> >> +             sg->int_lvl[bank] |= bit;
>> >> +     else if (type & IRQ_TYPE_LEVEL_LOW)
>> >> +             sg->int_lvl[bank] &= ~bit;
>> >> +     else
>> >> +             return -EINVAL;
>> >
>> > this looks wrong. You could have a user who wants to trigger on both
>> > HIGH and LOW levels, no ?
>> >
>> Yes, I think there can be a scenario where gpio_keys are attached
>> to this driver and signals a "key press" at low and "key release" at
>> high. ?
>>  Will figure out a way to add support to check for case where
>> both High and low levels are used.
>
> could probably be done on a separate patch, maybe... Just now I saw that
> HIGH and LOW levels use the same bit.
>
If I am understanding correctly, if they both uses the same bit we cannot
use both for a particular user. ?
> --
> balbi


From balbi at ti.com  Tue Aug 21 08:16:02 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:02 +0300
Subject: [PATCH v2 04/13] serial: omap: drop DMA support
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-5-git-send-email-balbi@ti.com>

The current support is known to be broken and
a later patch will come re-adding it using
dma engine API.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 330 ++-------------------------------------
 1 file changed, 12 insertions(+), 318 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6ab3582..16808b6 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -33,14 +33,12 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/io.h>
-#include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/serial_core.h>
 #include <linux/irq.h>
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 
-#include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/omap-serial.h>
 
@@ -74,9 +72,6 @@
 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 
 /* Forward declaration of functions */
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
-static void serial_omap_rxdma_poll(unsigned long uart_no);
-static int serial_omap_start_rxdma(struct uart_omap_port *up);
 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 
 static struct workqueue_struct *serial_omap_uart_wq;
@@ -160,19 +155,6 @@ serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 	return port->uartclk/(baud * divisor);
 }
 
-static void serial_omap_stop_rxdma(struct uart_omap_port *up)
-{
-	if (up->uart_dma.rx_dma_used) {
-		del_timer(&up->uart_dma.rx_timer);
-		omap_stop_dma(up->uart_dma.rx_dma_channel);
-		omap_free_dma(up->uart_dma.rx_dma_channel);
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
-}
-
 static void serial_omap_enable_ms(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
@@ -188,22 +170,6 @@ static void serial_omap_enable_ms(struct uart_port *port)
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->dev->platform_data;
-
-	if (up->use_dma &&
-		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
-		/*
-		 * Check if dma is still active. If yes do nothing,
-		 * return. Else stop dma
-		 */
-		if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
-			return;
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		omap_free_dma(up->uart_dma.tx_dma_channel);
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
 
 	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
@@ -211,8 +177,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata)
-		serial_omap_set_forceidle(up);
+	serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
@@ -223,8 +188,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(up->dev);
-	if (up->use_dma)
-		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
@@ -342,67 +305,12 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct circ_buf *xmit;
-	unsigned int start;
-	int ret = 0;
-
-	if (!up->use_dma) {
-		pm_runtime_get_sync(up->dev);
-		serial_omap_enable_ier_thri(up);
-		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return;
-	}
-
-	if (up->uart_dma.tx_dma_used)
-		return;
-
-	xmit = &up->port.state->xmit;
-
-	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
-				"UART Tx DMA",
-				(void *)uart_tx_dma_callback, up,
-				&(up->uart_dma.tx_dma_channel));
 
-		if (ret < 0) {
-			serial_omap_enable_ier_thri(up);
-			return;
-		}
-	}
-	spin_lock(&(up->uart_dma.tx_lock));
-	up->uart_dma.tx_dma_used = true;
-	spin_unlock(&(up->uart_dma.tx_lock));
-
-	start = up->uart_dma.tx_buf_dma_phys +
-				(xmit->tail & (UART_XMIT_SIZE - 1));
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys +
-			UART_XMIT_SIZE) - start;
-
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
+	pm_runtime_get_sync(up->dev);
+	serial_omap_enable_ier_thri(up);
+	serial_omap_set_noidle(up);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static unsigned int check_modem_status(struct uart_omap_port *up)
@@ -455,16 +363,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	spin_lock_irqsave(&up->port.lock, flags);
 	lsr = serial_in(up, UART_LSR);
 	if (iir & UART_IIR_RLSI) {
-		if (!up->use_dma) {
-			if (lsr & UART_LSR_DR)
-				receive_chars(up, &lsr);
-		} else {
-			up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-			if ((serial_omap_start_rxdma(up) != 0) &&
-					(lsr & UART_LSR_DR))
-				receive_chars(up, &lsr);
-		}
+		if (lsr & UART_LSR_DR)
+			receive_chars(up, &lsr);
 	}
 
 	check_modem_status(up);
@@ -605,20 +505,6 @@ static int serial_omap_startup(struct uart_port *port)
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
 	up->msr_saved_flags = 0;
-	if (up->use_dma) {
-		free_page((unsigned long)up->port.state->xmit.buf);
-		up->port.state->xmit.buf = dma_alloc_coherent(NULL,
-			UART_XMIT_SIZE,
-			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
-			0);
-		init_timer(&(up->uart_dma.rx_timer));
-		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
-		up->uart_dma.rx_timer.data = up->port.line;
-		/* Currently the buffer size is 4KB. Can increase it */
-		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
-			up->uart_dma.rx_buf_size,
-			(dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
-	}
 	/*
 	 * Finally, enable interrupts. Note: Modem status interrupts
 	 * are set via set_termios(), which will be occurring imminently
@@ -666,17 +552,6 @@ static void serial_omap_shutdown(struct uart_port *port)
 	 */
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
-	if (up->use_dma) {
-		dma_free_coherent(up->port.dev,
-			UART_XMIT_SIZE,	up->port.state->xmit.buf,
-			up->uart_dma.tx_buf_dma_phys);
-		up->port.state->xmit.buf = NULL;
-		serial_omap_stop_rx(port);
-		dma_free_coherent(up->port.dev,
-			up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
-			up->uart_dma.rx_buf_dma_phys);
-		up->uart_dma.rx_buf = NULL;
-	}
 
 	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
@@ -800,8 +675,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 			UART_FCR_ENABLE_FIFO;
-	if (up->use_dma)
-		up->fcr |= UART_FCR_DMA_SELECT;
 
 	/*
 	 * Ok, we're now changing the port state. Do it with
@@ -877,14 +750,9 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 
-	if (up->use_dma) {
-		serial_out(up, UART_TI752_TLR, 0);
-		up->scr |= UART_FCR_TRIGGER_4;
-	} else {
-		/* Set receive FIFO threshold to 1 byte */
-		up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
-		up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
-	}
+	/* Set receive FIFO threshold to 1 byte */
+	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
+	up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
 
 	serial_out(up, UART_FCR, up->fcr);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
@@ -1253,149 +1121,6 @@ static int serial_omap_resume(struct device *dev)
 }
 #endif
 
-static void serial_omap_rxdma_poll(unsigned long uart_no)
-{
-	struct uart_omap_port *up = ui[uart_no];
-	unsigned int curr_dma_pos, curr_transmitted_size;
-	int ret = 0;
-
-	curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
-	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
-			     (curr_dma_pos == 0)) {
-		if (jiffies_to_msecs(jiffies - up->port_activity) <
-						up->uart_dma.rx_timeout) {
-			mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-		} else {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-		return;
-	}
-
-	curr_transmitted_size = curr_dma_pos -
-					up->uart_dma.prev_rx_dma_pos;
-	up->port.icount.rx += curr_transmitted_size;
-	tty_insert_flip_string(up->port.state->port.tty,
-			up->uart_dma.rx_buf +
-			(up->uart_dma.prev_rx_dma_pos -
-			up->uart_dma.rx_buf_dma_phys),
-			curr_transmitted_size);
-	tty_flip_buffer_push(up->port.state->port.tty);
-	up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
-	if (up->uart_dma.rx_buf_size +
-			up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
-		ret = serial_omap_start_rxdma(up);
-		if (ret < 0) {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-	} else  {
-		mod_timer(&up->uart_dma.rx_timer, jiffies +
-			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	}
-	up->port_activity = jiffies;
-}
-
-static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	return;
-}
-
-static int serial_omap_start_rxdma(struct uart_omap_port *up)
-{
-	int ret = 0;
-
-	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
-				"UART Rx DMA",
-				(void *)uart_rx_dma_callback, up,
-				&(up->uart_dma.rx_dma_channel));
-		if (ret < 0)
-			return ret;
-
-		omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-		omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC,
-				up->uart_dma.rx_buf_dma_phys, 0, 0);
-		omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.rx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_rx, 0);
-	}
-	up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.rx_dma_channel);
-	mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	up->uart_dma.rx_dma_used = true;
-	return ret;
-}
-
-static void serial_omap_continue_tx(struct uart_omap_port *up)
-{
-	struct circ_buf *xmit = &up->port.state->xmit;
-	unsigned int start = up->uart_dma.tx_buf_dma_phys
-			+ (xmit->tail & (UART_XMIT_SIZE - 1));
-
-	if (uart_circ_empty(xmit))
-		return;
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
-}
-
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	struct uart_omap_port *up = data;
-	struct circ_buf *xmit = &up->port.state->xmit;
-
-	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-			(UART_XMIT_SIZE - 1);
-	up->port.icount.tx += up->uart_dma.tx_buf_size;
-
-	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-		uart_write_wakeup(&up->port);
-
-	if (uart_circ_empty(xmit)) {
-		spin_lock(&(up->uart_dma.tx_lock));
-		serial_omap_stop_tx(&up->port);
-		up->uart_dma.tx_dma_used = false;
-		spin_unlock(&(up->uart_dma.tx_lock));
-	} else {
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		serial_omap_continue_tx(up);
-	}
-	up->port_activity = jiffies;
-	return;
-}
-
 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 {
 	u32 mvr, scheme;
@@ -1465,7 +1190,7 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 static int serial_omap_probe(struct platform_device *pdev)
 {
 	struct uart_omap_port	*up;
-	struct resource		*mem, *irq, *dma_tx, *dma_rx;
+	struct resource		*mem, *irq;
 	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
 	int ret = -ENOSPC;
 
@@ -1490,14 +1215,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-	if (!dma_rx)
-		return -ENXIO;
-
-	dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-	if (!dma_tx)
-		return -ENXIO;
-
 	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
 	if (!up)
 		return -ENOMEM;
@@ -1541,20 +1258,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		dev_warn(&pdev->dev, "No clock speed specified: using default:"
 						"%d\n", DEFAULT_CLK_SPEED);
 	}
-	up->uart_dma.uart_base = mem->start;
-
-	if (omap_up_info->dma_enabled) {
-		up->uart_dma.uart_dma_tx = dma_tx->start;
-		up->uart_dma.uart_dma_rx = dma_rx->start;
-		up->use_dma = 1;
-		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
-		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
-		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
-		spin_lock_init(&(up->uart_dma.tx_lock));
-		spin_lock_init(&(up->uart_dma.rx_lock));
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-	}
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
@@ -1697,10 +1400,6 @@ static int serial_omap_runtime_suspend(struct device *dev)
 		}
 	}
 
-	/* Errata i291 */
-	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		serial_omap_set_forceidle(up);
-
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
 
@@ -1718,11 +1417,6 @@ static int serial_omap_runtime_resume(struct device *dev)
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
 
-		/* Errata i291 */
-		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
-				up->use_dma)
-			serial_omap_set_noidle(up);
-
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
 	}
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:05 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:05 +0300
Subject: [PATCH v2 07/13] serial: omap: refactor receive_chars() into rdi/rlsi
 handlers
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-8-git-send-email-balbi@ti.com>

receive_chars() was getting too big and too difficult
to follow. By splitting it into separate RDI and RSLI
handlers, we have smaller functions which are easy
to understand and only touch the pieces which they need
to touch.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 207 +++++++++++++++++++--------------------
 1 file changed, 102 insertions(+), 105 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 2d3e64e..fe9852b 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,74 +195,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static inline void receive_chars(struct uart_omap_port *up,
-		unsigned int *status)
-{
-	struct tty_struct *tty = up->port.state->port.tty;
-	unsigned int flag, lsr = *status;
-	unsigned char ch = 0;
-	int max_count = 256;
-
-	do {
-		if (likely(lsr & UART_LSR_DR))
-			ch = serial_in(up, UART_RX);
-		flag = TTY_NORMAL;
-		up->port.icount.rx++;
-
-		if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
-			/*
-			 * For statistics only
-			 */
-			if (lsr & UART_LSR_BI) {
-				lsr &= ~(UART_LSR_FE | UART_LSR_PE);
-				up->port.icount.brk++;
-				/*
-				 * We do the SysRQ and SAK checking
-				 * here because otherwise the break
-				 * may get masked by ignore_status_mask
-				 * or read_status_mask.
-				 */
-				if (uart_handle_break(&up->port))
-					goto ignore_char;
-			} else if (lsr & UART_LSR_PE) {
-				up->port.icount.parity++;
-			} else if (lsr & UART_LSR_FE) {
-				up->port.icount.frame++;
-			}
-
-			if (lsr & UART_LSR_OE)
-				up->port.icount.overrun++;
-
-			/*
-			 * Mask off conditions which should be ignored.
-			 */
-			lsr &= up->port.read_status_mask;
-
-#ifdef CONFIG_SERIAL_OMAP_CONSOLE
-			if (up->port.line == up->port.cons->index) {
-				/* Recover the break flag from console xmit */
-				lsr |= up->lsr_break_flag;
-			}
-#endif
-			if (lsr & UART_LSR_BI)
-				flag = TTY_BREAK;
-			else if (lsr & UART_LSR_PE)
-				flag = TTY_PARITY;
-			else if (lsr & UART_LSR_FE)
-				flag = TTY_FRAME;
-		}
-
-		if (uart_handle_sysrq_char(&up->port, ch))
-			goto ignore_char;
-		uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
-ignore_char:
-		lsr = serial_in(up, UART_LSR);
-	} while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
-	spin_unlock(&up->port.lock);
-	tty_flip_buffer_push(tty);
-	spin_lock(&up->port.lock);
-}
-
 static void transmit_chars(struct uart_omap_port *up)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
@@ -341,6 +273,68 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 	return status;
 }
 
+static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned int flag;
+
+	up->port.icount.rx++;
+	flag = TTY_NORMAL;
+
+	if (lsr & UART_LSR_BI) {
+		flag = TTY_BREAK;
+		lsr &= ~(UART_LSR_FE | UART_LSR_PE);
+		up->port.icount.brk++;
+		/*
+		 * We do the SysRQ and SAK checking
+		 * here because otherwise the break
+		 * may get masked by ignore_status_mask
+		 * or read_status_mask.
+		 */
+		if (uart_handle_break(&up->port))
+			return;
+
+	}
+
+	if (lsr & UART_LSR_PE) {
+		flag = TTY_PARITY;
+		up->port.icount.parity++;
+	}
+
+	if (lsr & UART_LSR_FE) {
+		flag = TTY_FRAME;
+		up->port.icount.frame++;
+	}
+
+	if (lsr & UART_LSR_OE)
+		up->port.icount.overrun++;
+
+#ifdef CONFIG_SERIAL_OMAP_CONSOLE
+	if (up->port.line == up->port.cons->index) {
+		/* Recover the break flag from console xmit */
+		lsr |= up->lsr_break_flag;
+	}
+#endif
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
+}
+
+static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned char ch = 0;
+	unsigned int flag;
+
+	if (!(lsr & UART_LSR_DR))
+		return;
+
+	ch = serial_in(up, UART_RX);
+	flag = TTY_NORMAL;
+	up->port.icount.rx++;
+
+	if (uart_handle_sysrq_char(&up->port, ch))
+		return;
+
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
+}
+
 /**
  * serial_omap_irq() - This handles the interrupt from one port
  * @irq: uart port irq number
@@ -349,55 +343,58 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
+	struct tty_struct *tty = up->port.state->port.tty;
 	unsigned int iir, lsr;
 	unsigned int type;
 	unsigned long flags;
 	irqreturn_t ret = IRQ_HANDLED;
+	int max_count = 256;
 
 	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
-	iir = serial_in(up, UART_IIR);
-again:
-	if (iir & UART_IIR_NO_INT) {
-		ret = IRQ_NONE;
-		goto out;
-	}
 
-	lsr = serial_in(up, UART_LSR);
+	do {
+		iir = serial_in(up, UART_IIR);
+		if (iir & UART_IIR_NO_INT) {
+			ret = IRQ_NONE;
+			break;
+		}
 
-	/* extract IRQ type from IIR register */
-	type = iir & 0x3e;
+		lsr = serial_in(up, UART_LSR);
 
-	switch (type) {
-	case UART_IIR_MSI:
-		check_modem_status(up);
-		break;
-	case UART_IIR_THRI:
-		if (lsr & UART_LSR_THRE)
-			transmit_chars(up);
-		break;
-	case UART_IIR_RDI:
-		if (lsr & UART_LSR_DR)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RLSI:
-		if (lsr & UART_LSR_BRK_ERROR_BITS)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RX_TIMEOUT:
-		receive_chars(up, &lsr);
-		break;
-	case UART_IIR_CTS_RTS_DSR:
-		iir = serial_in(up, UART_IIR);
-		goto again;
-	case UART_IIR_XOFF:
-		/* FALLTHROUGH */
-	default:
-		break;
-	}
+		/* extract IRQ type from IIR register */
+		type = iir & 0x3e;
+
+		switch (type) {
+		case UART_IIR_MSI:
+			check_modem_status(up);
+			break;
+		case UART_IIR_THRI:
+			if (lsr & UART_LSR_THRE)
+				transmit_chars(up);
+			break;
+		case UART_IIR_RX_TIMEOUT:
+			/* FALLTHROUGH */
+		case UART_IIR_RDI:
+			serial_omap_rdi(up, lsr);
+			break;
+		case UART_IIR_RLSI:
+			serial_omap_rlsi(up, lsr);
+			break;
+		case UART_IIR_CTS_RTS_DSR:
+			/* simply try again */
+			break;
+		case UART_IIR_XOFF:
+			/* FALLTHROUGH */
+		default:
+			break;
+		}
+	} while (!(iir & UART_IIR_NO_INT) && max_count--);
 
-out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
+
+	tty_flip_buffer_push(tty);
+
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:06 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:06 +0300
Subject: [PATCH v2 08/13] serial: omap: move THRE check to transmit_chars()
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-9-git-send-email-balbi@ti.com>

since all other IRQ types now do all necessary
checks inside their handlers, transmit_chars()
was the only one left expecting serial_omap_irq()
to check THRE for it. We can move THRE check to
transmit_chars() in order to make serial_omap_irq()
more uniform.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index fe9852b..bb63dc9 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,11 +195,14 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static void transmit_chars(struct uart_omap_port *up)
+static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
 	int count;
 
+	if (!(lsr & UART_LSR_THRE))
+		return;
+
 	if (up->port.x_char) {
 		serial_out(up, UART_TX, up->port.x_char);
 		up->port.icount.tx++;
@@ -370,8 +373,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 			check_modem_status(up);
 			break;
 		case UART_IIR_THRI:
-			if (lsr & UART_LSR_THRE)
-				transmit_chars(up);
+			transmit_chars(up, lsr);
 			break;
 		case UART_IIR_RX_TIMEOUT:
 			/* FALLTHROUGH */
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:07 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:07 +0300
Subject: [PATCH v2 09/13] serial: omap: stick to put_autosuspend
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-10-git-send-email-balbi@ti.com>

Everytime we're done using our TTY, we want
the pm timer to be reinitilized. By sticking
to pm_runtime_pm_autosuspend() we make sure
that this will always be the case.

The idea behind this patch is to make sure we
will always reinitialize the pm timer so that
we don't fall into a situation where pm_runtime_put()
expires right away (if timer was already about to
expire when we made the call to pm_runtime_put()).

While suspending right away wouldn't cause any
issues, reinitializing the pm timer can help us
avoiding unnecessary context save & restore
operations (which are somewhat expensive) if there's
another read/write/set_termios request coming right
after. IOW, we are trying to make sure UART is still
powered up while it's still under heavy usage.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index bb63dc9..c272ecc 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
 	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
@@ -415,7 +416,8 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return ret;
 }
 
@@ -427,7 +429,8 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -463,7 +466,8 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -480,7 +484,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -578,7 +583,8 @@ static void serial_omap_shutdown(struct uart_port *port)
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -849,7 +855,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -880,7 +887,8 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -962,7 +970,8 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -976,7 +985,8 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return status;
 }
 
@@ -1308,7 +1318,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (ret != 0)
 		goto err_add_port;
 
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	platform_set_drvdata(pdev, up);
 	return 0;
 
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:08 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:08 +0300
Subject: [PATCH v2 10/13] serial: omap: set dev->drvdata before enabling
 pm_runtime
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-11-git-send-email-balbi@ti.com>

by the time we call our first pm_runtme_get_sync()
after enable pm_runtime, our resume method might
be called. To avoid problems, we must make sure
that our dev->drvdata is set correctly before
our resume method gets called.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index c272ecc..1aaba77 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1301,6 +1301,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
 
+	platform_set_drvdata(pdev, up);
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
 			omap_up_info->autosuspend_timeout);
@@ -1320,7 +1321,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-	platform_set_drvdata(pdev, up);
 	return 0;
 
 err_add_port:
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:09 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:09 +0300
Subject: [PATCH v2 11/13] serial: omap: drop unnecessary check from remove
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-12-git-send-email-balbi@ti.com>

if platform_get_drvdata() returns NULL, that's
quite a nasty bug on the driver which we want to
catch ASAP. Otherwise, that check is hugely
unneeded.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 1aaba77..2e1a33a 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1337,13 +1337,10 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
-	if (up) {
-		pm_runtime_disable(up->dev);
-		uart_remove_one_port(&serial_omap_reg, &up->port);
-		pm_qos_remove_request(&up->pm_qos_request);
-	}
+	pm_runtime_disable(up->dev);
+	uart_remove_one_port(&serial_omap_reg, &up->port);
+	pm_qos_remove_request(&up->pm_qos_request);
 
-	platform_set_drvdata(dev, NULL);
 	return 0;
 }
 
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:10 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:10 +0300
Subject: [PATCH v2 12/13] serial: omap: make sure to suspend device before
 remove
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-13-git-send-email-balbi@ti.com>

before removing the driver, let's make sure
to force device into a suspended state in order
to conserve power.

Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 2e1a33a..b79c4fa 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1337,6 +1337,7 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
+	pm_runtime_put_sync(up->dev);
 	pm_runtime_disable(up->dev);
 	uart_remove_one_port(&serial_omap_reg, &up->port);
 	pm_qos_remove_request(&up->pm_qos_request);
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:16:11 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:16:11 +0300
Subject: [PATCH v2 13/13] serial: omap: don't save IRQ flags on hardirq
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <1345551371-18862-14-git-send-email-balbi@ti.com>

When we're running our hardirq handler, there's
not need to disable IRQs with spin_lock_irqsave()
because IRQs are already disabled. It also makes
no difference if we save or not IRQ flags.

Switch over to simple spin_lock/spin_unlock and
drop the "flags" variable.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index b79c4fa..a79658d 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -350,11 +350,10 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	struct tty_struct *tty = up->port.state->port.tty;
 	unsigned int iir, lsr;
 	unsigned int type;
-	unsigned long flags;
 	irqreturn_t ret = IRQ_HANDLED;
 	int max_count = 256;
 
-	spin_lock_irqsave(&up->port.lock, flags);
+	spin_lock(&up->port.lock);
 	pm_runtime_get_sync(up->dev);
 
 	do {
@@ -394,7 +393,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 		}
 	} while (!(iir & UART_IIR_NO_INT) && max_count--);
 
-	spin_unlock_irqrestore(&up->port.lock, flags);
+	spin_unlock(&up->port.lock);
 
 	tty_flip_buffer_push(tty);
 
-- 
1.7.12.rc3



From balbi at ti.com  Tue Aug 21 08:22:18 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:22:18 +0300
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO expander
 feature
In-Reply-To: <CAKdam55SqXiCGv766yxoY1GdDjxNCYNaDdNZPaeLTAXc+3+c6g@mail.gmail.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
 <20120821105333.GW10347@arwen.pp.htv.fi>
 <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>
 <20120821120052.GD10347@arwen.pp.htv.fi>
 <CAKdam55SqXiCGv766yxoY1GdDjxNCYNaDdNZPaeLTAXc+3+c6g@mail.gmail.com>
Message-ID: <20120821122217.GF10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 05:50:28PM +0530, Poddar, Sourav wrote:
> Hi,
> 
> On Tue, Aug 21, 2012 at 5:30 PM, Felipe Balbi <balbi at ti.com> wrote:
> > Hi,
> >
> > On Tue, Aug 21, 2012 at 05:17:37PM +0530, Poddar, Sourav wrote:
> >> >> +     if (type & IRQ_TYPE_LEVEL_HIGH)
> >> >> +             sg->int_lvl[bank] |= bit;
> >> >> +     else if (type & IRQ_TYPE_LEVEL_LOW)
> >> >> +             sg->int_lvl[bank] &= ~bit;
> >> >> +     else
> >> >> +             return -EINVAL;
> >> >
> >> > this looks wrong. You could have a user who wants to trigger on both
> >> > HIGH and LOW levels, no ?
> >> >
> >> Yes, I think there can be a scenario where gpio_keys are attached
> >> to this driver and signals a "key press" at low and "key release" at
> >> high. ?
> >>  Will figure out a way to add support to check for case where
> >> both High and low levels are used.
> >
> > could probably be done on a separate patch, maybe... Just now I saw that
> > HIGH and LOW levels use the same bit.
> >
> If I am understanding correctly, if they both uses the same bit we cannot
> use both for a particular user. ?

we can, it's just a bit more complex. If a user request both LOW and
HIGH, then you start with HIGH, once it triggers, before calling the
nested IRQ handler, you need to change it LOW. When low triggers, before
calling the nested IRQ handler, you need to change it to HIGH again. And
so on. I'm just not sure if that's valid on linux IRQ subsystem.

Anyone ?

-- 
balbi
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From linux at arm.linux.org.uk  Tue Aug 21 08:27:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 21 Aug 2012 13:27:53 +0100
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
Message-ID: <20120821122753.GU18957@n2100.arm.linux.org.uk>

On Mon, Aug 20, 2012 at 12:22:56PM -0500, Matt Sealey wrote:
> You're going to have to define these clocks as a tree with parents and
> leaf nodes anyway in the clock subsystem. Why not define these in the
> device tree in total and reference them by handle when you build the
> entire clock tree from the ground up? Or will it just be all the
> clocks defined in Linux, but the lookups (which is what I see here)
> moved into the DT? Why not form the lookups as part of the definition
> of the clock tree?

Well, IMHO the DT conversion of the clk lookup stuff has been done
completely wrong.

What should have been done is rather than invent a totally new bloody
lookup interface that drivers have to use instead of clk_get(), is to
embed the OF lookup _inside_ clk_get().

What you do is this:

1. Have property names in the device node like:

	clock_<connection-id> = <&provider-node output>

   In the case of a NULL connection id:

	clock = <&provider-node output>

   Remember that the connection ID is _supposed_ to be something that
   is described by the hardware (like - for the AACI primecell, the
   clock which runs the functional side is called "AACICLK" by the TRM,
   and for the MMCI primecell, it's "MMCICLK" - even though these two
   clocks may be fed by the same source in an implementation.)

2. clkdev's lookup is then modified to look at the struct device, and
   check for a DT node.  If there is a DT node, it formats a property
   string:

	if (dev->of_node) {
		char *propname, *clk_prop = NULL;
		struct property *p;

		if (conn_id) {
			clk_prop = kasprintf("clock_%s", conn_id);
			propname = clk_prop;
		} else {
			propname = "clock";
		}

		p = of_find_property(dev->of_node, propname, NULL);
		if (clk_prop)
			kfree(clk_prop);

		if (p) {
			clk = clk_get_from_of_property(p);
			if (clk)
				return clk;
		}

		/* Fallthrough to clkdev table lookup */
	}

So now, you're not dealing with inventing a whole load of names for clocks
on a platform, instead what you're doing is describing _where_ the clock
comes from in the system for a particular device by device node and index
into it - just like we do for interrupts.

This means there's no need for huge tables and such like of clock names.

I did mention this idea long ago but got ignored.


From linus.walleij at linaro.org  Tue Aug 21 08:31:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:31:43 +0200
Subject: [PATCH 2/2] ARM: EXYNOS: Enable PINCTRL config option for Exynos4
 device tree enabled platform
In-Reply-To: <1345061442-32378-3-git-send-email-thomas.abraham@linaro.org>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
 <1345061442-32378-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkda9BiGejU+Qs=1CqKgLxLGumcM4QZOb_og-aAAmKr-0VQ@mail.gmail.com>

On Wed, Aug 15, 2012 at 10:10 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> This enables support for Samsung and Exynos4 pinctrl driver for device
> tree enabled Exynos4 platforms.
>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/mach-exynos/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index b5b4c8c..ad96c59 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -405,6 +405,7 @@ config MACH_EXYNOS4_DT
>         select USE_OF
>         select ARM_AMBA
>         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
> +       select PINCTRL

I don't think this works, since PINCTRL_SAMSUNG is not default "y"
(nor should it be).

For the platforms I converted I had to select both the subsystem and
the indivudual driver, as is already done for some GPIO controllers
for example:

select PINCTRL
select PINCTRL_SAMSUNG

Yours,
Linus Walleij


From nico at fluxnic.net  Tue Aug 21 08:33:19 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 21 Aug 2012 08:33:19 -0400 (EDT)
Subject: [PATCH] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <20120821090213.GE28660@mudshark.cambridge.arm.com>
References: <1344956366-32574-1-git-send-email-will.deacon@arm.com>
 <alpine.LFD.2.02.1208161906390.1541@xanadu.home>
 <20120820124109.GK25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208200902120.1754@xanadu.home>
 <20120820144927.GP25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201150010.1754@xanadu.home>
 <20120820165405.GU25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201356130.1754@xanadu.home>
 <20120820181007.GX25864@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1208201443070.1754@xanadu.home>
 <20120821090213.GE28660@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1208210832210.1754@xanadu.home>

On Tue, 21 Aug 2012, Will Deacon wrote:

> On Mon, Aug 20, 2012 at 07:45:20PM +0100, Nicolas Pitre wrote:
> > On Mon, 20 Aug 2012, Will Deacon wrote:
> > > On Mon, Aug 20, 2012 at 07:04:01PM +0100, Nicolas Pitre wrote:
> > > > Nah... the const is wrong.  The way you wrote it means that addr may 
> > > > change but the pointed data is constant.  This is obviously wrong since 
> > > > we expect the pointed location to change even from a read.
> > > 
> > > That's the prototype for the read accessors though -- a bunch of other
> > > architectures define them that way (including asm-generic), so I wonder what
> > > the reasoning behind that was?
> > 
> > I'm still asserting that they're wrong.
> 
> I did a bit of digging around and `const volatile void *' is apparently used
> because a function with such a parameter type can be passed any old pointer
> without warnings. Torvalds says something about them here:
> 
>   http://readlist.com/lists/vger.kernel.org/linux-kernel/14/72300.html
> 
> Personally, I too think that the const is misleading and who on Earth would
> be passing in pointers to const for an I/O region? However, it's an argument
> I'd rather avoid so, for the sake of consistency, I'll cast away the const in
> the asm block.

OK.  Either that or your previous patch should do then.


Nicolas


From linux at arm.linux.org.uk  Tue Aug 21 08:34:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 21 Aug 2012 13:34:51 +0100
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <20120821142235.97984abc9ad98d01015a3338@nvidia.com>
References: <1343636899-19508-1-git-send-email-m.szyprowski@samsung.com>
 <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com>
 <20120821142235.97984abc9ad98d01015a3338@nvidia.com>
Message-ID: <20120821123451.GV18957@n2100.arm.linux.org.uk>

On Tue, Aug 21, 2012 at 02:22:35PM +0300, Hiroshi Doyu wrote:
> The following "__get_vm_area_node()" can take gfp_mask, it means that
> this function is expected to be called from atomic context, but why
> it's _NOT_ allowed _ONLY_ from interrupt context?

One reason is it takes read/write locks without using the IRQ safe
versions for starters (vmap_area_lock and vmlist_lock).  I don't see
any other reasons in that bit of code though.


From burman.yan at gmail.com  Tue Aug 21 07:36:07 2012
From: burman.yan at gmail.com (Yan Burman)
Date: Tue, 21 Aug 2012 14:36:07 +0300
Subject: [PATCH v3] ARM: ep93xx: Use HW MAC filter in ethernet driver
Message-ID: <1345548967.4262.2.camel@localhost>

ARM: ep93xx: Use HW MAC filter in ethernet driver
Use HW MAC filtering for broadcasts and multicasts.
Do not always work in promiscuous mode.
Partially based on kernel 2.6.20.4 driver from cirrus logic.
Tested on 9302 and 9315 based boards.

Changes from v2:
* Some more minor style changes

Changes from v1:
* Some minor style fixes
* Use CRC32 code instead of duplicating code
* Fixed multicast reception (tested with omping)

Signed-off-by: Yan Burman <burman.yan at gmail.com>

diff --git a/drivers/net/ethernet/cirrus/Kconfig b/drivers/net/ethernet/cirrus/Kconfig
index 8388e36..b7b154f 100644
--- a/drivers/net/ethernet/cirrus/Kconfig
+++ b/drivers/net/ethernet/cirrus/Kconfig
@@ -46,6 +46,7 @@ config EP93XX_ETH
 	depends on ARM && ARCH_EP93XX
 	select NET_CORE
 	select MII
+	select CRC32
 	help
 	  This is a driver for the ethernet hardware included in EP93xx CPUs.
 	  Say Y if you are building a kernel for EP93xx based devices.
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..a92a033 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/crc32.h>
 
 #include <mach/hardware.h>
 
@@ -37,8 +38,32 @@
 #define MAX_PKT_SIZE		2044
 #define PKT_BUF_SIZE		2048
 
+#define HASH_TBL_ENTRIES	8
+
 #define REG_RXCTL		0x0000
-#define  REG_RXCTL_DEFAULT	0x00073800
+#define  REG_RXCTL_PAUSEA  (1 << 20)
+#define  REG_RXCTL_RXFCE1  (1 << 19)
+#define  REG_RXCTL_RXFCE0  (1 << 18)
+#define  REG_RXCTL_BCRC    (1 << 17)
+#define  REG_RXCTL_SRXON   (1 << 16)
+#define  REG_RXCTL_RCRCA   (1 << 13)
+#define  REG_RXCTL_RA      (1 << 12)
+#define  REG_RXCTL_PA      (1 << 11)
+#define  REG_RXCTL_BA      (1 << 10)
+#define  REG_RXCTL_MA      (1 << 9)
+#define  REG_RXCTL_IAHA    (1 << 8)
+#define  REG_RXCTL_IA3     (1 << 3)
+#define  REG_RXCTL_IA2     (1 << 2)
+#define  REG_RXCTL_IA1     (1 << 1)
+#define  REG_RXCTL_IA0     (1 << 0)
+#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
+				REG_RXCTL_RA | \
+				REG_RXCTL_RCRCA | \
+				REG_RXCTL_SRXON | \
+				REG_RXCTL_BCRC | \
+				REG_RXCTL_RXFCE0 | \
+				REG_RXCTL_IA0)
+
 #define REG_TXCTL		0x0004
 #define  REG_TXCTL_ENABLE	0x00000001
 #define REG_MIICMD		0x0010
@@ -57,6 +82,12 @@
 #define  REG_INTSTS_RX		0x00000004
 #define REG_INTSTSC		0x002c
 #define REG_AFP			0x004c
+#define  REG_AFP_IA0		0
+#define  REG_AFP_IA1		1
+#define  REG_AFP_IA2		2
+#define  REG_AFP_IA3		3
+#define  REG_AFP_DTxP		6
+#define  REG_AFP_HASH		7
 #define REG_INDAD0		0x0050
 #define REG_INDAD1		0x0051
 #define REG_INDAD2		0x0052
@@ -386,6 +417,51 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 }
 
+static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *buf)
+{
+	struct netdev_hw_addr *ha;
+	u32 crc;
+
+	netdev_for_each_mc_addr(ha, dev) {
+		crc = ether_crc_le(ETH_ALEN, ha->addr);
+		buf[crc >> 29] |= (1 << ((crc >> 26) & 7));
+	}
+}
+
+static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *buf)
+{
+	u32 rxctl;
+	unsigned int i, len;
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	switch (afp) {
+	case REG_AFP_IA0:
+	case REG_AFP_IA1:
+	case REG_AFP_IA2:
+	case REG_AFP_IA3:
+	case REG_AFP_DTxP:
+		len = ETH_ALEN;
+		break;
+
+	case REG_AFP_HASH:
+		len = HASH_TBL_ENTRIES;
+		break;
+
+	default:
+		pr_crit("invalid afp value: %d\n", afp);
+		return -EINVAL;
+	}
+
+	rxctl = rdl(ep, REG_RXCTL);
+	wrl(ep, REG_RXCTL, rxctl & ~REG_RXCTL_SRXON);
+	wrl(ep, REG_AFP, afp);
+	for (i = 0; i < len; i++)
+		wrb(ep, REG_INDAD0 + i, buf[i]);
+	wrl(ep, REG_RXCTL, rxctl);
+
+	return 0;
+}
+
 static void ep93xx_tx_complete(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -615,13 +691,7 @@ static int ep93xx_start_hw(struct net_device *dev)
 	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
 	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
 
-	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
-	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
-	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
-	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
-	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
-	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
-	wrl(ep, REG_AFP, 0);
+	ep93xx_ind_addr_write(dev, REG_AFP_IA0, dev->dev_addr);
 
 	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
 
@@ -647,6 +717,30 @@ static void ep93xx_stop_hw(struct net_device *dev)
 		pr_crit("hw failed to reset\n");
 }
 
+static void ep93xx_set_multicast_list(struct net_device *dev)
+{
+	struct ep93xx_priv *ep = netdev_priv(dev);
+
+	if (dev->flags & IFF_PROMISC) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
+	} else if (dev->flags & IFF_ALLMULTI) {
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(rdl(ep, REG_RXCTL) & ~REG_RXCTL_PA));
+		ep93xx_ind_addr_write(dev, REG_AFP_HASH,
+			      "\xff\xff\xff\xff\xff\xff\xff\xff");
+	} else if (!netdev_mc_empty(dev)) {
+		u8 tbl_multi[HASH_TBL_ENTRIES + 1] = {0};
+
+		ep93xx_set_mcast_tbl(dev, tbl_multi);
+		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
+			(rdl(ep, REG_RXCTL) & ~REG_RXCTL_PA));
+		ep93xx_ind_addr_write(dev, REG_AFP_HASH, tbl_multi);
+	} else {
+		wrl(ep, REG_RXCTL,
+			rdl(ep, REG_RXCTL) & ~(REG_RXCTL_PA | REG_RXCTL_MA));
+	}
+}
+
 static int ep93xx_open(struct net_device *dev)
 {
 	struct ep93xx_priv *ep = netdev_priv(dev);
@@ -754,6 +848,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_change_mtu		= eth_change_mtu,
 	.ndo_set_mac_address	= eth_mac_addr,
+	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
 };
 
 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)




From broonie at opensource.wolfsonmicro.com  Tue Aug 21 08:39:51 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 13:39:51 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <20120821115123.GE26899@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de> <20120820113427.GN8450@gmail.com>
 <20120820143653.GE26991@opensource.wolfsonmicro.com>
 <20120821115123.GE26899@gmail.com>
Message-ID: <20120821123951.GC7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 12:51:24PM +0100, Lee Jones wrote:
> On Mon, Aug 20, 2012 at 03:36:53PM +0100, Mark Brown wrote:

> > > From: Lee Jones <lee.jones at linaro.org>
> > > Date: Fri, 27 Jul 2012 08:50:05 +0100

> > Please resend this series with all the acks you've got rather than
> > mixing incremental updates in like this.

> I'm waiting until I have a few more Acks before I resend the entire
> patch-set again. Actually it's you and one other that I'm waiting for
> to review (and Ack as necessary) the ones requested by Linus, then 
> resend with the corrections.

Well, I'm the person who's going to apply the patches so I'm unlikely
to ack them...  I was waiting for arch/arm review before I looked at
them due to the number of resends.

> > Please also send patches in
> > the format documented in SubmittingPatches.

> That's a big document, most of which I guess I'm adhering to. Care to
> be a little more specific?

The bit I quoted is the main example, you're including random mail
headers in the body of the mail.
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 08:41:46 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 13:41:46 +0100
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120821124146.GA21557@sirena.org.uk>

On Tue, Aug 21, 2012 at 04:15:37PM +0530, Sourav Poddar wrote:

> +config MFD_SMSC
> +       bool "Support for the SMSC ECE1099 series chips"
> +       depends on I2C=y && MFD_CORE && REGMAP_I2C

This needs to select REGMAP_I2C not depend on it.  REGMAP_I2C will only
be enabled by being selected.

> +int smsc_read(struct device *child, unsigned int reg,
> +	unsigned int *dest)
> +{
> +	struct smsc     *smsc = dev_get_drvdata(child->parent);
> +
> +	return regmap_read(smsc->regmap, reg, dest);
> +}
> +EXPORT_SYMBOL_GPL(smsc_read);

I'd suggest making these static inlines in the header given that they're
so trivial.

> +static struct regmap_config smsc_regmap_config = {
> +		.reg_bits = 8,
> +		.val_bits = 8,
> +		.cache_type = REGCACHE_COMPRESSED,
> +};

Indentation is weird here.  For the cache we should have at least
.max_register defined and given the functionality there must surely be
some volatile registers (I'm surprised this works at all as it is, the
cache should break things).

> +	of_property_read_u32(node, "clock", &smsc->clk);
> +

This is all unconditional, there should be a dependency on this in
Kconfig.

> +	regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
> +	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);

I'd make these log messages dev_info() or something.

> +err:
> +	kfree(smsc);

Use devm_kzalloc() for this.

> +static const struct i2c_device_id smsc_i2c_id[] = {
> +	{ "smsc", 0},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(i2c, smsc_i2c_id);

This should probably list the part name rather than "smsc" - that seems
far too generic a name to use, obviously smsc produce more than one
part!


From sebastian.hesselbarth at gmail.com  Tue Aug 21 08:45:23 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 21 Aug 2012 14:45:23 +0200
Subject: [v3] Add basic address decoding support for Marvell 370/XP
In-Reply-To: <20120821135045.58e2a633@skate>
References: <1344246141-23931-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120816132839.GO22226@titan.lakedaemon.net>
 <20120816183708.GT22226@titan.lakedaemon.net>
 <20120817152156.4d91ba16@skate>
 <20120819012303.GX22226@titan.lakedaemon.net>
 <20120821114630.545fb771@skate>
 <CABJ1b_RVaSjsneDCvejSMot0ZHDr1dmeroVRDUNMF2y83UGXNA@mail.gmail.com>
 <20120821135045.58e2a633@skate>
Message-ID: <CABJ1b_Tg-O6HOnrLynJv33oFYAaqSKJ+XmvwW7TzY47Q4+MhDQ@mail.gmail.com>

On 8/21/12, Thomas Petazzoni <thomas.petazzoni at free-electrons.com> wrote:
> Ok, I will look at your code, but the purpose of
> PLAT_ORION/PLAT_ORION_LEGACY was not only to re-use the addr-map code,
> but also to allow drivers to access the header files containing their
> platform_data structure and other stuff (i.e, all the header files from
> arch/arm/plat-orion/include/). How do you handle this problem if
> MACH_MVEBU is not a PLAT_ORION platform?

Hmm, ok I wasn't aware of that. But I have a bad feeling about joining
PLAT_ORION into MACH_MVEBU if you want to have ORION replaced
by MVEBU in the future. Maybe it is better here to put all you need into
mach-mvebu/include/mach/legacy.h that can be easily abandoned when
everything is ported to something more general.

I know it is code duplication but it is only for the purpose of removing
PLAT_ORION later on.

Sebastian


From balbi at ti.com  Tue Aug 21 08:42:45 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 15:42:45 +0300
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821124146.GA21557@sirena.org.uk>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
Message-ID: <20120821124243.GG10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 01:41:46PM +0100, Mark Brown wrote:
> > +	regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
> > +	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
> 
> I'd make these log messages dev_info() or something.

dev_info() ? It'lll just make boot noisier for no good reason. Which
user wants to see this during boot up ? That's a debugging feature for
develop IMHO.

-- 
balbi
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From linus.walleij at linaro.org  Tue Aug 21 08:46:59 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:46:59 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <20120816033006.GA11999@shlinux2.ap.freescale.net>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120816033006.GA11999@shlinux2.ap.freescale.net>
Message-ID: <CACRpkdaKUt2UFrcRH41dFMxTVcN-Z2yqPKnc1r_O56+tcaiL5w@mail.gmail.com>

On Thu, Aug 16, 2012 at 5:30 AM, Dong Aisheng <b29396 at freescale.com> wrote:

> The problem is that those pins are visible to pinctrl subystem, but the pinctrl
> subsystem can not manage them all.
> Not sure this meet Linus's original design purpose.

The U300 driver has *lots* of pins it cannot manage. I have no strong
opinions on this, often if there are lots of pins and say some ranges
here and there are controllable, you may want to register them all
(with names) just so that you can get something intuitive out of the
pin numbers.

But the descriptors are actually sparse, so you don't have to have
a consecutive pin range and can actually just register the pins you
want with the names you want. It's your pick...

> But i'm not sure if we may have this requirement in the future.
> For example, is it possible that pinctrl subsystem may support configure pins
> via sysfs dynamically?

Not sysfs. For GPIO this ended up in a bad place.
Maybe /dev/pinctrl0, /dev/pinctrl1

But I don't think we want to expose individual pin configs to
userspace. Maybe pinctrl states. Dunno, has to be designed,
and surely pins can be totally numb and unconfigurable as well....

> If it supports, will imx driver also support config unused pins in devicetree
> via sysfs?

DT *or* /dev/foo I guess.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Aug 21 08:52:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:52:43 +0200
Subject: [PATCH] pinctrl: imx5: start numbering pad from 0
In-Reply-To: <502D622A.1030104@wwwdotorg.org>
References: <1344869278-27334-1-git-send-email-shawn.guo@linaro.org>
 <CAKGA1b=DqyZvSre3C4YQ3GM6RuFtFsGWDkF784iKggrNzwiKpg@mail.gmail.com>
 <CAP1dx+zQvBurT9oCmfJ0dGHHV3rbgdy+0Yh_hoPL9jQB8QNxKw@mail.gmail.com>
 <CAKGA1bmHqyDGyvZjEcQ+RO1jHiZNZKNu3BGkyUXzYfwVaySYEQ@mail.gmail.com>
 <CAP1dx+x0_j_f3Pj+9+YHcwoTqjGLXouf7t+SoCCMVGKJNOHCPw@mail.gmail.com>
 <20120815054436.GK2232@pengutronix.de>
 <20120815065526.GG19681@shlinux2.ap.freescale.net>
 <20120815075117.GL2232@pengutronix.de>
 <20120815092539.GH19681@shlinux2.ap.freescale.net>
 <20120815135947.GC2258@S2101-09.ap.freescale.net>
 <20120816033006.GA11999@shlinux2.ap.freescale.net>
 <502D622A.1030104@wwwdotorg.org>
Message-ID: <CACRpkdZghkK8eCVdzEm2bQizVq=U-Zg90i43vD9YMkS+2WxVNA@mail.gmail.com>

On Thu, Aug 16, 2012 at 11:12 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/15/2012 09:30 PM, Dong Aisheng wrote:

>> For example, the pin_config_get/pin_config_set API in
>> include/linux/pinctrl/consumer.h can not work for such pins.
>
> Hmmm. Given we support all pin mux/config options from the mapping
> table, I'd question whether that API should even exist any more...

If there are no in-kernel users we can delete it. But I can surely see
things like PCI lab boards etc wanting to have full control over pins
from userspace, just like they can hammer GPIO's on/off today
from userspace (i.e. embedded SoCs is not the only use case)
so I wouldn't rule it out. I think this use case is quite real for
automatic control, robotics, factory lines... those guys do use GPIO
sysfs like that already today.

>> It looks like not a big issue currently since i did not see any client driver
>> using this API.
>> But i'm not sure if we may have this requirement in the future.
>> For example, is it possible that pinctrl subsystem may support configure pins
>> via sysfs dynamically?
>
> I can't comment on sysfs specifically, but I believe it would be
> generally true that a pin that isn't know to the pinctrl subsystem can't
> be manipulated in any way.

sysfs over my dead body ... but exposing pin names to userspace is
another thing, and might be interesting, in case we want to just
sort of list all pins on the system from some command line tool or
HW-info control panel. But that requires designing the userspace
device interface first, so no need to haste.

Yours,
Linus Walleij


From rob.herring at calxeda.com  Tue Aug 21 08:53:55 2012
From: rob.herring at calxeda.com (Rob Herring)
Date: Tue, 21 Aug 2012 07:53:55 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
Message-ID: <503384E3.4030705@calxeda.com>



On 08/20/2012 12:22 PM, Matt Sealey wrote:
> On Mon, Aug 20, 2012 at 10:16 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> On Mon, Aug 20, 2012 at 09:54:48AM -0500, Matt Sealey wrote:
>>> Yet another arbitrary array...
>>>
>>> I'm not sure why you would move the registration lookup into the DT
>>
>> Because I do not want to patch kernel every time I need a new lookup.
>> Furthermore, looking at function imx53_qsb_init in imx53-dt.c, you
>> will find that lookup for sgtl5000 is really board specific and should
>> go to device tree.
>>
>>> and use an arbitrarily ordered array again. Sure, you're looking it up
>>> entirely within the device tree here, but a better solution would be
>>> to not name clocks twice, and structure your clock definition
>>> properly.
>>>
>>> What's wrong with;
>>>
>>> ccm at 020c4000 {
>>>    ...
>>>    my_clock: clock at 0 {
>>>        name = "my_clock_name";
>>>    }
>>> }
>>>
>>> uart at nnnnnnnn {
>>>    ...
>>>    clocks = <&my_clock>;
>>> }
>>>
>>> ?
>>>
>> It turns a property into 185 nodes, which will just bloat the device
>> tree.  This issue has been discussed for a plenty of times.
> 
> It's not bloat just because it is by its very definition "a big list", is it?
> 
> How do you explain duplicating the clock names in the array AND in the
> device node as NOT being bloated?

Read the clock binding doc. Names are optional and the 2 names are not
the same. One is the name of the output on the CCM and one is the name
on input to the module.

While generally optional, Shawn has chosen to require at least the
output names. In the case of defining a signal clock controller node
with lots of outputs, that is the right choice.

Rob

> 
> You're going to have to define these clocks as a tree with parents and
> leaf nodes anyway in the clock subsystem. Why not define these in the
> device tree in total and reference them by handle when you build the
> entire clock tree from the ground up? Or will it just be all the
> clocks defined in Linux, but the lookups (which is what I see here)
> moved into the DT? Why not form the lookups as part of the definition
> of the clock tree?
> 


From linus.walleij at linaro.org  Tue Aug 21 08:54:16 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 14:54:16 +0200
Subject: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung
 Exynos4210 SoC
In-Reply-To: <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
 <1345061442-32378-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdbuqtPKMTEziPfMYfSssjWxPeMEP7=wJD4WtEHNppcOZA@mail.gmail.com>

On Wed, Aug 15, 2012 at 10:10 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> +       pinctrl at 11400000 {
> +               uart0_data: uart0-data {
> +                       samsung,pins = "gpa0-0", "gpa0-1";
> +                       samsung,pin-function = <0x2>;
> +                       samsung,pin-pud = <0>;
> +                       samsung,pin-drv = <0>;
> +               };

Apart from the pin-pud and pin-drv stuff this patch looks fine. These two
things I want to discuss in the other mail thread (controller core) first.

Yours,
Linus Walleij


From lee.jones at linaro.org  Tue Aug 21 08:58:12 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 21 Aug 2012 13:58:12 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <20120821123951.GC7995@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de> <20120820113427.GN8450@gmail.com>
 <20120820143653.GE26991@opensource.wolfsonmicro.com>
 <20120821115123.GE26899@gmail.com>
 <20120821123951.GC7995@opensource.wolfsonmicro.com>
Message-ID: <20120821125811.GA931@gmail.com>

On Tue, Aug 21, 2012 at 01:39:51PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 12:51:24PM +0100, Lee Jones wrote:
> > On Mon, Aug 20, 2012 at 03:36:53PM +0100, Mark Brown wrote:
> 
> > > > From: Lee Jones <lee.jones at linaro.org>
> > > > Date: Fri, 27 Jul 2012 08:50:05 +0100
> 
> > > Please resend this series with all the acks you've got rather than
> > > mixing incremental updates in like this.
> 
> > I'm waiting until I have a few more Acks before I resend the entire
> > patch-set again. Actually it's you and one other that I'm waiting for
> > to review (and Ack as necessary) the ones requested by Linus, then 
> > resend with the corrections.
> 
> Well, I'm the person who's going to apply the patches so I'm unlikely
> to ack them...  I was waiting for arch/arm review before I looked at

I have all of Linus' Acks. The only ones missing are yours and Ola's,
but I think Ola is on vacation still, so he's asked Roger to do it.
I don't know if you saw, but Linus has placed lots of Acked-by's which
are dependent on your say-so, hence why I was waiting for your response.

> them due to the number of resends.

Bingo, thus why I was dubious about resending the entire patch-set too
prematurely.

> > > Please also send patches in
> > > the format documented in SubmittingPatches.
> 
> > That's a big document, most of which I guess I'm adhering to. Care to
> > be a little more specific?
> 
> The bit I quoted is the main example, you're including random mail
> headers in the body of the mail.

They're not mail headers per-say, they're `git format-patch` headers.
I thought this was acceptable for single patches, hence why I've done
it lots of times and had no complaints (until now).

If there are some changes required in a single patch, I usually fix
it up, create a patch with `git format-patch` and send it as a reply
to either the original patch in the series or the mail containing the
suggestion. If this is wrong please educate me as I thought this was
acceptable, as I thought it would be less pain than sending the
entire patch-set again for just one change?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From hdoyu at nvidia.com  Tue Aug 21 08:59:45 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 21 Aug 2012 14:59:45 +0200
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <20120821123451.GV18957@n2100.arm.linux.org.uk>
References: <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com><20120821142235.97984abc9ad98d01015a3338@nvidia.com><20120821123451.GV18957@n2100.arm.linux.org.uk>
Message-ID: <20120821.155945.1711711797763144039.hdoyu@nvidia.com>

Russell King - ARM Linux <linux at arm.linux.org.uk> wrote @ Tue, 21 Aug 2012 14:34:51 +0200:

> On Tue, Aug 21, 2012 at 02:22:35PM +0300, Hiroshi Doyu wrote:
> > The following "__get_vm_area_node()" can take gfp_mask, it means that
> > this function is expected to be called from atomic context, but why
> > it's _NOT_ allowed _ONLY_ from interrupt context?
> 
> One reason is it takes read/write locks without using the IRQ safe
> versions for starters (vmap_area_lock and vmlist_lock).  I don't see
> any other reasons in that bit of code though.

IIRC, if *_{irqsave,irqrestore} versions were introduced to protect
from IRQ context, could we remove this BUG_ON(in_interrupt()) in
__get_vm_area_node() at least? Or is it not encouraged from
performance POV?

It seems that the solution to allow IOMMU'able device driver to
allocate from ISR are:
(1) To provide the pre-allocate area like arm_dma_alloc() does,
or
(2) __get_vm_area_node() can be called from ISR.


From catalin.marinas at arm.com  Tue Aug 21 08:59:48 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 13:59:48 +0100
Subject: [PATCH v2 14/31] arm64: DMA mapping API
In-Reply-To: <201208151616.01114.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
 <201208151616.01114.arnd@arndb.de>
Message-ID: <20120821125948.GC12708@arm.com>

On Wed, Aug 15, 2012 at 05:16:00PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> > +static struct dma_map_ops arm64_swiotlb_dma_ops = {
> > +       .alloc = arm64_swiotlb_alloc_coherent,
> > +       .free = arm64_swiotlb_free_coherent,
> > +       .map_page = arm64_swiotlb_map_page,
> > +       .unmap_page = arm64_swiotlb_unmap_page,
> > +       .map_sg = arm64_swiotlb_map_sg_attrs,
> > +       .unmap_sg = arm64_swiotlb_unmap_sg_attrs,
> > +       .sync_single_for_cpu = arm64_swiotlb_sync_single_for_cpu,
> > +       .sync_single_for_device = arm64_swiotlb_sync_single_for_device,
> > +       .sync_sg_for_cpu = arm64_swiotlb_sync_sg_for_cpu,
> > +       .sync_sg_for_device = arm64_swiotlb_sync_sg_for_device,
> > +       .dma_supported = swiotlb_dma_supported,
> > +       .mapping_error = swiotlb_dma_mapping_error,
> > +};
> > +
> > +void __init swiotlb_init_with_default_size(size_t default_size, int verbose);
> > +
> > +void __init arm64_swiotlb_init(size_t max_size)
> > +{
> > +       dma_ops = &arm64_swiotlb_dma_ops;
> > +       swiotlb_init_with_default_size(min((size_t)SZ_64M, max_size), 1);
> > +}
> 
> Why is swiotlb the default? I would expect that most devices can in fact
> use the entire 64 bit address space, so you can use a simple linear
> implementation for those.

That was my worry, devices not capable of accessing the full 64-bit
address space. We can hope that those SoCs would have an IOMMU but I
can't tell for sure at this stage.

The default implementation could be simpler. I can even drop it
altogether from the initial patchset given that no SoC makes use of it
yet.

-- 
Catalin


From linus.walleij at linaro.org  Tue Aug 21 09:01:40 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 21 Aug 2012 15:01:40 +0200
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkda2hc2eZaFqRfAPEG7KfLd3mFFdWze=V45=w84nRPqijA@mail.gmail.com>

On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
> driver adopt irqdomain support, so that we can have the mapping
> between gpio and irq number available without using virtual_irq_start
> and MXS_GPIO_IRQ_START.

Seems like a good thing to do, but with Grant and Rob being better at
irqdomain than me I'd prefer one of them to have a look at this too.

> +       irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
> +       if (irq_base < 0)
> +               return irq_base;
> +
> +       port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
> +                                            &irq_domain_simple_ops, NULL);

For example I want to understand if it'd be possible to use a
linear domain here.

Yours,
Linus Walleij


From balbi at ti.com  Tue Aug 21 09:01:36 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 16:01:36 +0300
Subject: [PATCH v2 00/13] OMAP Serial patches
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <20120821130134.GH10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 03:15:58PM +0300, Felipe Balbi wrote:
> Hi guys,
> 
> here's a series of cleanup patches to the OMAP serial
> driver. A later series could be made re-implementing
> DMA using the DMA Engine API. Note that for RX DMA
> we could be using RX Timeout IRQ as a hint that we better
> use PIO instead ;-)
> 
> All patches were tested on my pandaboard, but I'd really
> like to receive Tested-by on other platforms.
> 
> After this goes in, I'll probably try to get UART wakeup
> working again and only after that look at DMA.
> 
> Changes since v1:
> 
> 	. improved commit log on patch 9/13 (formerly 10/13)
> 	. removed patch 2/13
> 	. added a new patch switching from spin_lock_irqsave() to spin_lock and
> 		spin_unlock_irqrestore to spin_unlock
> 
> Retested with my pandaboard, UART continues to work:
> 
>  # grep -i uart /proc/interrupts
>  106:        124          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        189          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        255          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        321          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        387          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        453          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        519          0       GIC  OMAP UART2
> 
> cheers
> 
> ps: if anyone knows a better test for UART, let me know.
> 
> for convenience of anyone testing, patches are available on my git tree [1] on
> branch uart
> 
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart

I have added one extra patch to this series:

From 6921efdb13dda7af216b331bb35535d4b53f004a Mon Sep 17 00:00:00 2001
From: Felipe Balbi <balbi at ti.com>
Date: Tue, 21 Aug 2012 15:48:35 +0300
Subject: [PATCH] serial: omap: drop pm_runtime_irq_safe() usage

pm_runtime_irq_safe() will essentially do an
unbalanced pm_runtime_get_sync() on our parent
device, which might cause problems when trying
to suspend.

In order to prevent that we drop pm_runtime_irq_safe
usage in exchange for a little performance hit
when we enter our IRQ handler while still suspended.

If that happens, what we will do is set the irq_pending
flag, do an asynchronous pm_runtime_get() call and
return IRQ_HANDLED. When our runtime_resume() callback
is executed, we check for that flag, and run our
IRQ handler so that we receive/transmit the pending
characters.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---

One extra patch to OMAP UART driver. This seems to be working
pretty well even after echo mem > /sys/power/state. I can
see that I can even wake my pandaboard up by sending a character
through serial:

 #  echo mem > /sys/power/state
 [ 1335.679260] PM: Syncing filesystems ... done.
 [ 1335.684387] Freezing user space processes ... (elapsed 0.00 seconds) done.
 [ 1335.691741] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
 [ 1335.720886] Suspending console(s) (use no_console_suspend to debug)
 
 [ 1335.734405] PM: suspend of devices complete after 5.492 msecs
 [ 1335.735534] PM: late suspend of devices complete after 1.128 msecs
 [ 1335.737518] PM: noirq suspend of devices complete after 1.952 msecs
 [ 1335.737518] Disabling non-boot CPUs ...
 [ 1335.738525] CPU1: shutdown
 [ 1338.543762] Successfully put all powerdomains to target state
 [ 1338.543853] Enabling non-boot CPUs ...
 [ 1338.545654] CPU1: Booted secondary processor
 [ 1338.546020] CPU1 is up
 [ 1338.547027] PM: noirq resume of devices complete after 0.976 msecs
 [ 1338.548400] PM: early resume of devices complete after 0.762 msecs
 [ 1339.827087] PM: resume of devices complete after 1278.686 msecs
 [ 1339.890960] Restarting tasks ... done.
 # # grep -i uart /proc/interrupts
 106:       3385          0       GIC  OMAP UART2
 # echo mem > /sys/power/state
 [ 1358.015624] PM: Syncing filesystems ... done.
 [ 1358.020812] Freezing user space processes ... (elapsed 0.00 seconds) done.
 [ 1358.028167] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
 [ 1358.055084] Suspending console(s) (use no_console_suspend to debug)
 
 [ 1358.068847] PM: suspend of devices complete after 5.633 msecs
 [ 1358.070007] PM: late suspend of devices complete after 1.126 msecs
 [ 1358.072051] PM: noirq suspend of devices complete after 2.040 msecs
 [ 1358.072051] Disabling non-boot CPUs ...
 [ 1358.073211] CPU1: shutdown
 [ 1359.104156] Successfully put all powerdomains to target state
 [ 1359.104278] Enabling non-boot CPUs ...
 [ 1359.106079] CPU1: Booted secondary processor
 [ 1359.106475] CPU1 is up
 [ 1359.107482] PM: noirq resume of devices complete after 1.004 msecs
 [ 1359.108886] PM: early resume of devices complete after 0.761 msecs
 [ 1360.414794] PM: resume of devices complete after 1305.836 msecs
 [ 1360.478668] Restarting tasks ... done.
 # # grep -i uart /proc/interrupts
 106:       3511          0       GIC  OMAP UART2

 arch/arm/plat-omap/include/plat/omap-serial.h |  1 +
 drivers/tty/serial/omap-serial.c              | 16 +++++++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 743ac80..52328ca 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -130,6 +130,7 @@ struct uart_omap_port {
 	u32			context_loss_cnt;
 	u32			errata;
 	u8			wakeups_enabled;
+	unsigned int		irq_pending:1;
 
 	struct pm_qos_request	pm_qos_request;
 	u32			latency;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index a79658d..7e237f3 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -353,9 +353,13 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	irqreturn_t ret = IRQ_HANDLED;
 	int max_count = 256;
 
-	spin_lock(&up->port.lock);
-	pm_runtime_get_sync(up->dev);
+	if (pm_runtime_suspended(up->dev)) {
+		up->irq_pending = true;
+		pm_runtime_get(up->dev);
+		return IRQ_HANDLED;
+	}
 
+	spin_lock(&up->port.lock);
 	do {
 		iir = serial_in(up, UART_IIR);
 		if (iir & UART_IIR_NO_INT) {
@@ -400,6 +404,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
+	up->irq_pending = false;
 
 	return ret;
 }
@@ -1305,7 +1310,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
 			omap_up_info->autosuspend_timeout);
 
-	pm_runtime_irq_safe(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
 
@@ -1416,6 +1420,9 @@ static int serial_omap_runtime_suspend(struct device *dev)
 	if (!up)
 		return -EINVAL;
 
+	if (up->irq_pending)
+		return -EBUSY;
+
 	if (!pdata)
 		return 0;
 
@@ -1452,6 +1459,9 @@ static int serial_omap_runtime_resume(struct device *dev)
 
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
+
+		if (up->irq_pending)
+			serial_omap_irq(up->port.irq, up);
 	}
 
 	return 0;
-- 
1.7.12.rc3


-- 
balbi
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From catalin.marinas at arm.com  Tue Aug 21 09:05:39 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 14:05:39 +0100
Subject: [PATCH v2 14/31] arm64: DMA mapping API
In-Reply-To: <20120815004006.GG19607@quad.lixom.net>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-15-git-send-email-catalin.marinas@arm.com>
 <20120815004006.GG19607@quad.lixom.net>
Message-ID: <20120821130539.GD12708@arm.com>

On Wed, Aug 15, 2012 at 01:40:06AM +0100, Olof Johansson wrote:
> On Tue, Aug 14, 2012 at 06:52:15PM +0100, Catalin Marinas wrote:
> > +static inline struct dma_map_ops *get_dma_ops(struct device *dev)
> > +{
> > +	if (unlikely(!dev) || !dev->archdata.dma_ops)
> > +		return dma_ops;
> > +	else
> > +		return dev->archdata.dma_ops;
> > +}
> 
> Does it make sense to add the concept of a global dma ops on arm64,
> instead of requiring the dma ops pointer per device similar to how
> some other platforms do it (including powerpc)? For devices that lack
> archdata.dma_ops, dma_supported() should return 0 (and the other ops
> should return error).

If the device doesn't have archdata.dma_ops we return the default
implementation which is currently based on swiotlb. Do you mean that
this shouldn't be the case and just let the device always set
archdata.dma_ops?

-- 
Catalin


From rob.herring at calxeda.com  Tue Aug 21 09:11:57 2012
From: rob.herring at calxeda.com (Rob Herring)
Date: Tue, 21 Aug 2012 08:11:57 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <20120821122753.GU18957@n2100.arm.linux.org.uk>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <20120821122753.GU18957@n2100.arm.linux.org.uk>
Message-ID: <5033891D.90509@calxeda.com>

On 08/21/2012 07:27 AM, Russell King - ARM Linux wrote:
> On Mon, Aug 20, 2012 at 12:22:56PM -0500, Matt Sealey wrote:
>> You're going to have to define these clocks as a tree with parents and
>> leaf nodes anyway in the clock subsystem. Why not define these in the
>> device tree in total and reference them by handle when you build the
>> entire clock tree from the ground up? Or will it just be all the
>> clocks defined in Linux, but the lookups (which is what I see here)
>> moved into the DT? Why not form the lookups as part of the definition
>> of the clock tree?
> 
> Well, IMHO the DT conversion of the clk lookup stuff has been done
> completely wrong.
> 
> What should have been done is rather than invent a totally new bloody
> lookup interface that drivers have to use instead of clk_get(), is to
> embed the OF lookup _inside_ clk_get().

That is exactly what was done. Drivers only use clk_get. Only if you
don't have a struct device, then you can use of_clk_get.

Internally, you still need a conversion of clk provider node and cell to
a struct clk. It is up to each clk provider how to do this. The lookup
done here by Shawn is using the struct clk name and using the existing
clk framework lookup.

> What you do is this:
> 
> 1. Have property names in the device node like:
> 
> 	clock_<connection-id> = <&provider-node output>

The connection id is defined by the position in the list and
supplemented with "clock-names" property.

> 
>    In the case of a NULL connection id:
> 
> 	clock = <&provider-node output>
> 
>    Remember that the connection ID is _supposed_ to be something that
>    is described by the hardware (like - for the AACI primecell, the
>    clock which runs the functional side is called "AACICLK" by the TRM,
>    and for the MMCI primecell, it's "MMCICLK" - even though these two
>    clocks may be fed by the same source in an implementation.)
> 
> 2. clkdev's lookup is then modified to look at the struct device, and
>    check for a DT node.  If there is a DT node, it formats a property
>    string:
> 
> 	if (dev->of_node) {
> 		char *propname, *clk_prop = NULL;
> 		struct property *p;
> 
> 		if (conn_id) {
> 			clk_prop = kasprintf("clock_%s", conn_id);
> 			propname = clk_prop;
> 		} else {
> 			propname = "clock";
> 		}
> 
> 		p = of_find_property(dev->of_node, propname, NULL);
> 		if (clk_prop)
> 			kfree(clk_prop);
> 
> 		if (p) {
> 			clk = clk_get_from_of_property(p);
> 			if (clk)
> 				return clk;
> 		}
> 
> 		/* Fallthrough to clkdev table lookup */
> 	}
> 
> So now, you're not dealing with inventing a whole load of names for clocks
> on a platform, instead what you're doing is describing _where_ the clock
> comes from in the system for a particular device by device node and index
> into it - just like we do for interrupts.

That is what we're doing. The names are optional for DT, but happen to
be required for struct clk now. If we don't put something in DT, then
the clock names will have to be something generic like ccm-1..ccm-185.

Rob

> 
> This means there's no need for huge tables and such like of clock names.
> 
> I did mention this idea long ago but got ignored.
> 


From robherring2 at gmail.com  Tue Aug 21 09:16:37 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 21 Aug 2012 08:16:37 -0500
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <CACRpkda2hc2eZaFqRfAPEG7KfLd3mFFdWze=V45=w84nRPqijA@mail.gmail.com>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
 <CACRpkda2hc2eZaFqRfAPEG7KfLd3mFFdWze=V45=w84nRPqijA@mail.gmail.com>
Message-ID: <50338A35.9070803@gmail.com>

On 08/21/2012 08:01 AM, Linus Walleij wrote:
> On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
>> Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
>> driver adopt irqdomain support, so that we can have the mapping
>> between gpio and irq number available without using virtual_irq_start
>> and MXS_GPIO_IRQ_START.
> 
> Seems like a good thing to do, but with Grant and Rob being better at
> irqdomain than me I'd prefer one of them to have a look at this too.
> 
>> +       irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
>> +       if (irq_base < 0)
>> +               return irq_base;
>> +
>> +       port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
>> +                                            &irq_domain_simple_ops, NULL);
> 
> For example I want to understand if it'd be possible to use a
> linear domain here.

Unfortunately, not if you care about your irq base and need sequential
irq numbers which is the case for non-DT.

Rob

> 
> Yours,
> Linus Walleij
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From broonie at opensource.wolfsonmicro.com  Tue Aug 21 09:22:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 14:22:22 +0100
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821124243.GG10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
Message-ID: <20120821132222.GF7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 03:42:45PM +0300, Felipe Balbi wrote:
> On Tue, Aug 21, 2012 at 01:41:46PM +0100, Mark Brown wrote:
> > > +	regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
> > > +	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);

> > I'd make these log messages dev_info() or something.

> dev_info() ? It'lll just make boot noisier for no good reason. Which
> user wants to see this during boot up ? That's a debugging feature for
> develop IMHO.

Most of the registers appeared to be chip revision information which is
most definitely useful to tell people about, though possibly with neater
formatting ("why is this batch of boards failing...  oh, right").  If
they're fixed device IDs then the driver should instead be verifying
that the registers contain the expected values and bombing out if they
don't.  Either way dev_dbg() isn't too helpful.
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From robherring2 at gmail.com  Tue Aug 21 09:26:15 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 21 Aug 2012 08:26:15 -0500
Subject: [PATCH] serial: pl011: honour serial aliases in device tree
In-Reply-To: <1345544302-12406-1-git-send-email-matthew.leach@arm.com>
References: <1345544302-12406-1-git-send-email-matthew.leach@arm.com>
Message-ID: <50338C77.4060700@gmail.com>

On 08/21/2012 05:18 AM, Matthew Leach wrote:
> If the order of UART nodes is changed in the device tree, then tty dev
> devices are attached to different serial ports causing the console to
> be directed to a different physical serial port. The "serial" aliases
> in the device tree should prevent this.
> 
> This patch ensures that the UART driver creates tty devices that
> honour these aliases if a device tree is present.
> 
> Signed-off-by: Matthew Leach <matthew.leach at arm.com>

One comment/question below, but otherwise:

Acked-by: Rob Herring <rob.herring at calxeda.com>

> ---
>  drivers/tty/serial/amba-pl011.c |   39 +++++++++++++++++++++++++++++++++++++++
>  1 files changed, 39 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index c17923e..5919599 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -52,6 +52,7 @@
>  #include <linux/scatterlist.h>
>  #include <linux/delay.h>
>  #include <linux/types.h>
> +#include <linux/of_device.h>
>  #include <linux/pinctrl/consumer.h>
>  
>  #include <asm/io.h>
> @@ -1869,6 +1870,42 @@ static struct uart_driver amba_reg = {
>  	.cons			= AMBA_CONSOLE,
>  };
>  
> +#ifdef CONFIG_OF

Now that we have IS_ENABLED, perhaps we want to put this inside the
function instead?

if (!IS_ENABLED(CONFIG_OF))
	return index;


> +static int pl011_probe_dt_alias(int index, struct device *dev)
> +{
> +	struct device_node *np;
> +	static bool seen_dev_with_alias = false;
> +	static bool seen_dev_without_alias = false;
> +	int ret = index;
> +
> +	np = dev->of_node;
> +	if (!np)
> +		return ret;
> +
> +	ret = of_alias_get_id(np, "serial");
> +	if (IS_ERR_VALUE(ret)) {
> +		seen_dev_without_alias = true;
> +		ret = index;
> +	} else {
> +		seen_dev_with_alias = true;
> +		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
> +			dev_warn(dev, "requested serial port %d  not available.\n", ret);
> +			ret = index;
> +		}
> +	}
> +
> +	if (seen_dev_with_alias && seen_dev_without_alias)
> +		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
> +
> +	return ret;
> +}
> +#else
> +static int pl011_probe_dt_alias(int index, struct device *dev)
> +{
> +	return index;
> +}
> +#endif
> +
>  static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
>  {
>  	struct uart_amba_port *uap;
> @@ -1891,6 +1928,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
>  		goto out;
>  	}
>  
> +	i = pl011_probe_dt_alias(i, &dev->dev);
> +
>  	base = ioremap(dev->res.start, resource_size(&dev->res));
>  	if (!base) {
>  		ret = -ENOMEM;
> 



From balbi at ti.com  Tue Aug 21 09:27:44 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 16:27:44 +0300
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821132222.GF7995@opensource.wolfsonmicro.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
Message-ID: <20120821132741.GI10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 02:22:22PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 03:42:45PM +0300, Felipe Balbi wrote:
> > On Tue, Aug 21, 2012 at 01:41:46PM +0100, Mark Brown wrote:
> > > > +	regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
> > > > +	dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
> 
> > > I'd make these log messages dev_info() or something.
> 
> > dev_info() ? It'lll just make boot noisier for no good reason. Which
> > user wants to see this during boot up ? That's a debugging feature for
> > develop IMHO.
> 
> Most of the registers appeared to be chip revision information which is
> most definitely useful to tell people about, though possibly with neater
> formatting ("why is this batch of boards failing...  oh, right").  If
> they're fixed device IDs then the driver should instead be verifying
> that the registers contain the expected values and bombing out if they
> don't.  Either way dev_dbg() isn't too helpful.

I still beg to differ. Even if it fails, dmesg will still contain the
message (provided you have it enabled). I really don't think we want
this to print to console on every boot.

If you're still testing your new batch of boards, you're not just a
simple user and you will have debugging enabled anyway. dev_info() will
be visible to anyone who's got a console running. Not sure how useful
that would be to my neighbor.

-- 
balbi
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 09:40:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 14:40:13 +0100
Subject: [PATCH 1/1] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <20120821125811.GA931@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-9-git-send-email-lee.jones@linaro.org>
 <s5h628lu0q9.wl%tiwai@suse.de> <20120820113427.GN8450@gmail.com>
 <20120820143653.GE26991@opensource.wolfsonmicro.com>
 <20120821115123.GE26899@gmail.com>
 <20120821123951.GC7995@opensource.wolfsonmicro.com>
 <20120821125811.GA931@gmail.com>
Message-ID: <20120821134013.GG7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 01:58:12PM +0100, Lee Jones wrote:
> On Tue, Aug 21, 2012 at 01:39:51PM +0100, Mark Brown wrote:

> > The bit I quoted is the main example, you're including random mail
> > headers in the body of the mail.

> They're not mail headers per-say, they're `git format-patch` headers.
> I thought this was acceptable for single patches, hence why I've done
> it lots of times and had no complaints (until now).

> If there are some changes required in a single patch, I usually fix
> it up, create a patch with `git format-patch` and send it as a reply
> to either the original patch in the series or the mail containing the
> suggestion. If this is wrong please educate me as I thought this was

If you're going to do this send the patch properly in the same way
patches are normally sent.  Take a step back and think about this for a
minute - why would it be a good idea to send these incremental patches
in a different format which requires the person applying the patch to
hand edit things to strip out the noise?

> acceptable, as I thought it would be less pain than sending the
> entire patch-set again for just one change?

It makes it harder to work out which versions of things to apply and
causes issues for tools when doing things like applying from a mailbox.
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 09:49:37 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 14:49:37 +0100
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821132741.GI10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
 <20120821132741.GI10347@arwen.pp.htv.fi>
Message-ID: <20120821134936.GH7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 04:27:44PM +0300, Felipe Balbi wrote:

> I still beg to differ. Even if it fails, dmesg will still contain the
> message (provided you have it enabled). I really don't think we want
> this to print to console on every boot.

Only if it's enabled which is the trick...

> If you're still testing your new batch of boards, you're not just a
> simple user and you will have debugging enabled anyway. dev_info() will
> be visible to anyone who's got a console running. Not sure how useful
> that would be to my neighbor.

Also think about hobbyists and so on, and ideally at some point the
people using distros.  We shouldn't be requiring kernel rebuilds for
this sort of diagnostic information.  I guess sysfs is another option
but frankly the overhead on boot just doesn't seem meaningful in the
context of the overall kernel boot style - I'd really expect people who
are bothered by this sort of output would be raising the minimum log
level appearing on the console.
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From will.deacon at arm.com  Tue Aug 21 09:50:59 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 Aug 2012 14:50:59 +0100
Subject: [PATCH v2] ARM: io: avoid writeback addressing modes for __raw_
 accessors
Message-ID: <1345557059-6922-1-git-send-email-will.deacon@arm.com>

Data aborts taken to hyp mode do not provide a valid instruction
syndrome field in the HSR if the faulting instruction is a memory
access using a writeback addressing mode.

For hypervisors emulating MMIO accesses to virtual peripherals, taking
such an exception requires disassembling the faulting instruction in
order to determine the behaviour of the access. Since this requires
manually walking the two stages of translation, the world must be
stopped to prevent races against page aging in the guest, where the
first-stage translation is invalidated after the hypervisor has
translated to an IPA and the physical page is reused for something else.

This patch avoids taking this heavy performance penalty when running
Linux as a guest by ensuring that our I/O accessors do not make use of
writeback addressing modes.

Cc: Marc Zyngier <marc.zyngier at arm.com>
Reviewed-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

Changes since v1:
	- Use "Qo" to allow for pre-indexing addressing modes

 arch/arm/include/asm/io.h |   67 +++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 61 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669..09c4628 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v)))
-#define __raw_writew(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
-#define __raw_writel(v,a)	((void)(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v)))
+#if __LINUX_ARM_ARCH__ < 6
+/*
+ * Half-word accesses are problematic with RiscPC due to limitations of
+ * the bus. Rather than special-case the machine, just let the compiler
+ * generate the access for CPUs prior to ARMv6.
+ */
+#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
+#else
+/*
+ * When running under a hypervisor, we want to avoid I/O accesses with
+ * writeback addressing modes as these incur a significant performance
+ * overhead (the address generation must be emulated in software).
+ */
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+	asm volatile("strh %1, %0"
+		     : "+Qo" (*(volatile u16 __force *)addr)
+		     : "r" (val));
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 val;
+	asm volatile("ldrh %1, %0"
+		     : "+Qo" (*(volatile u16 __force *)addr),
+		       "=r" (val));
+	return val;
+}
+#endif
 
-#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
-#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
-#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+	asm volatile("strb %1, %0"
+		     : "+Qo" (*(volatile u8 __force *)addr)
+		     : "r" (val));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+	asm volatile("str %1, %0"
+		     : "+Qo" (*(volatile u32 __force *)addr)
+		     : "r" (val));
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 val;
+	asm volatile("ldrb %1, %0"
+		     : "+Qo" (*(volatile u8 __force *)addr),
+		       "=r" (val));
+	return val;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 val;
+	asm volatile("ldr %1, %0"
+		     : "+Qo" (*(volatile u32 __force *)addr),
+		       "=r" (val));
+	return val;
+}
 
 /*
  * Architecture ioremap implementation.
-- 
1.7.4.1



From balbi at ti.com  Tue Aug 21 09:52:41 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 16:52:41 +0300
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821134936.GH7995@opensource.wolfsonmicro.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
 <20120821132741.GI10347@arwen.pp.htv.fi>
 <20120821134936.GH7995@opensource.wolfsonmicro.com>
Message-ID: <20120821135240.GJ10347@arwen.pp.htv.fi>

On Tue, Aug 21, 2012 at 02:49:37PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 04:27:44PM +0300, Felipe Balbi wrote:
> 
> > I still beg to differ. Even if it fails, dmesg will still contain the
> > message (provided you have it enabled). I really don't think we want
> > this to print to console on every boot.
> 
> Only if it's enabled which is the trick...
> 
> > If you're still testing your new batch of boards, you're not just a
> > simple user and you will have debugging enabled anyway. dev_info() will
> > be visible to anyone who's got a console running. Not sure how useful
> > that would be to my neighbor.
> 
> Also think about hobbyists and so on, and ideally at some point the
> people using distros.  We shouldn't be requiring kernel rebuilds for
> this sort of diagnostic information.  I guess sysfs is another option

but we don't. We have dynamic printk for that, right ?

> but frankly the overhead on boot just doesn't seem meaningful in the
> context of the overall kernel boot style - I'd really expect people who
> are bothered by this sort of output would be raising the minimum log
> level appearing on the console.

Well, if you consider a single driver then surely it doesn't make a
difference. But when you add many drivers, each with its own dev_info()
output, it can delay bootup rather significantly, actually.

Fair enough, we have "quiet", but I'm not sure that's enough argument to
allow any simple driver to start poluting dmesg with whatever random
messages.

my 2 cents

-- 
balbi
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 09:57:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 14:57:38 +0100
Subject: [PATCH v3 0/4] Add AM33XX regulators device tree data
In-Reply-To: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
Message-ID: <20120821135738.GJ7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 04:47:26PM +0530, AnilKumar Ch wrote:
> This patch series add AM33XX regulators (tps65910/tps65217) device
> tree data to am335x-evm and am335x-bone dts files. These patches
> are based on Tony L "devel-dt" tree with these patches
> http://www.mail-archive.com/linux-omap at vger.kernel.org/msg73843.html
> and these patches has been tested on AM335x EVM and Bone devices.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 10:08:03 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 15:08:03 +0100
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821135240.GJ10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
 <20120821132741.GI10347@arwen.pp.htv.fi>
 <20120821134936.GH7995@opensource.wolfsonmicro.com>
 <20120821135240.GJ10347@arwen.pp.htv.fi>
Message-ID: <20120821140803.GK7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 04:52:41PM +0300, Felipe Balbi wrote:

> Fair enough, we have "quiet", but I'm not sure that's enough argument to
> allow any simple driver to start poluting dmesg with whatever random
> messages.

I think if the driver is just logging to say "I'm running" that's noise
and I do push back on that routinely myself; if the driver is providing
information it's discovered from the running system then that seems much
more useful and we should have a sensible way of getting that out in a
place where users are likely to find.
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From balbi at ti.com  Tue Aug 21 10:09:24 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 17:09:24 +0300
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821140803.GK7995@opensource.wolfsonmicro.com>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
 <20120821132741.GI10347@arwen.pp.htv.fi>
 <20120821134936.GH7995@opensource.wolfsonmicro.com>
 <20120821135240.GJ10347@arwen.pp.htv.fi>
 <20120821140803.GK7995@opensource.wolfsonmicro.com>
Message-ID: <20120821140923.GL10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 03:08:03PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 04:52:41PM +0300, Felipe Balbi wrote:
> 
> > Fair enough, we have "quiet", but I'm not sure that's enough argument to
> > allow any simple driver to start poluting dmesg with whatever random
> > messages.
> 
> I think if the driver is just logging to say "I'm running" that's noise
> and I do push back on that routinely myself; if the driver is providing
> information it's discovered from the running system then that seems much
> more useful and we should have a sensible way of getting that out in a
> place where users are likely to find.

fair enough. But look at the messages which that driver is printing:

+       regmap_read(smsc->regmap, SMSC_DEV_ID, &ret);
+       dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+       regmap_read(smsc->regmap, SMSC_DEV_REV, &ret);
+       dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+       regmap_read(smsc->regmap, SMSC_VEN_ID_L, &ret);
+       dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);
+
+       regmap_read(smsc->regmap, SMSC_VEN_ID_H, &ret);
+       dev_dbg(&i2c->dev, "SMSC Device ID: %d\n", ret);

You can't possibly understand what that'll print. First of all, VEN_ID_H
and VEN_ID_L should be ORed together. Second, the user will see the same
message four times in a row, with different values, but see that driver
claims that all four values refer to the device id. What this should do,
is at least combine all four messages into a single one of the format:

dev_(dbg|info)(&i2c->dev, "SMSCxxx devid: %02x rev: %02x venid: %02x\n",
	devid, rev, (venid_h << 8) | venid_l);

or something similar.

-- 
balbi
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From broonie at opensource.wolfsonmicro.com  Tue Aug 21 10:13:37 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 15:13:37 +0100
Subject: [2/3][PATCH][v2] TDM Framework
In-Reply-To: <20120801123738.GA28291@kroah.com>
References: <1343397940-12975-1-git-send-email-sandeep@freescale.com>
 <20120727152542.GB1613@electric-eye.fr.zoreil.com>
 <3F1D9DCAAB49B94D88DBE05911FA4E6E511121@039-SN1MPN1-006.039d.mgd.msft.net>
 <20120730160146.GB28703@kroah.com>
 <3F1D9DCAAB49B94D88DBE05911FA4E6E515F98@039-SN1MPN1-001.039d.mgd.msft.net>
 <20120801123738.GA28291@kroah.com>
Message-ID: <20120821141336.GD21557@sirena.org.uk>

On Wed, Aug 01, 2012 at 05:37:38AM -0700, Greg KH wrote:
> On Wed, Aug 01, 2012 at 12:13:19PM +0000, Singh Sandeep-B37400 wrote:

> > But running a complete voice stack itself is beyond the scope of Freescale.
> > So vendors integrate their solutions with FSL solution.

> And sorry, I was thinking you had kernel drivers that attached to this
> framework, not userspace programs.  Actually, what is the user/kernel
> interface for this framework, I seem to have missed that entirely.  You
> will have to document that quite well, and run it by the linux-api
> mailing list.

This does also sound like we ought to be playing nicer with ALSA rather
than just providing a binary only pipe...


From broonie at opensource.wolfsonmicro.com  Tue Aug 21 10:20:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 15:20:08 +0100
Subject: [PATCH 1/4] mfd: smsc: Add support for smsc gpio io/keypad driver
In-Reply-To: <20120821140923.GL10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-2-git-send-email-sourav.poddar@ti.com>
 <20120821124146.GA21557@sirena.org.uk>
 <20120821124243.GG10347@arwen.pp.htv.fi>
 <20120821132222.GF7995@opensource.wolfsonmicro.com>
 <20120821132741.GI10347@arwen.pp.htv.fi>
 <20120821134936.GH7995@opensource.wolfsonmicro.com>
 <20120821135240.GJ10347@arwen.pp.htv.fi>
 <20120821140803.GK7995@opensource.wolfsonmicro.com>
 <20120821140923.GL10347@arwen.pp.htv.fi>
Message-ID: <20120821142007.GP7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 05:09:24PM +0300, Felipe Balbi wrote:

> You can't possibly understand what that'll print. First of all, VEN_ID_H
> and VEN_ID_L should be ORed together. Second, the user will see the same
> message four times in a row, with different values, but see that driver
> claims that all four values refer to the device id. What this should do,
> is at least combine all four messages into a single one of the format:

> dev_(dbg|info)(&i2c->dev, "SMSCxxx devid: %02x rev: %02x venid: %02x\n",
> 	devid, rev, (venid_h << 8) | venid_l);

> or something similar.

Yes, I agree that the formatting here should also be improved - as I
said in one of my earlier mails if any of these things are fixed things
that should never change the driver should instead verify the value
rather than log it.
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From mnalajal at codeaurora.org  Tue Aug 21 10:28:06 2012
From: mnalajal at codeaurora.org (Murali Nalajala)
Date: Tue, 21 Aug 2012 19:58:06 +0530
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
Message-ID: <50339AF6.1060601@codeaurora.org>

Hi All,
I am doing a below call in my driver to get the virtual address 
equivalent to physical address 0x0.

pdata->v_addr = ioremap(pdata->p_addr, PAGE_SIZE); /* pdata->p_addr=0 */

Above call returns me a valid virtual address i.e: 0xfa200000. After 
that when i try to access the address i am getting a kernel panic like 
below.

[   59.498141] Unable to handle kernel paging request at virtual address 
fa200000
[   59.498141] pgd = d4f80000
[   59.498141] [fa200000] *pgd=00000000
[   59.498141] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
[   59.498141] Modules linked in:
[   59.498141] CPU: 0    Tainted: G        W 
(3.4.0-g3b5f728-00009-g638207a #13)
[   59.498141] PC is at msm_pm_config_rst_vector_before_pc+0x8/0x30
[   59.498141] LR is at msm_pm_boot_config_before_pc+0x18/0x20
[   59.498141] pc : [<c0078f84>]    lr : [<c007903c>]    psr: a0000093
[   59.498141] sp : c0837ef0  ip : cfe00000  fp : 0000000d
[   59.498141] r10: da7efc17  r9 : 225c4278  r8 : 00000006
[   59.498141] r7 : 0003c000  r6 : c085c824  r5 : 00000001  r4 : fa101000
[   59.498141] r3 : fa200000  r2 : c095080c  r1 : 002250fc  r0 : 00000000
[   59.498141] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM 
Segment kernel
[   59.498141] Control: 10c5387d  Table: 25180059  DAC: 00000015
[   59.498141] [<c0078f84>] 
(msm_pm_config_rst_vector_before_pc+0x8/0x30) from [<c007903c>] 
(msm_pm_boot_config_before_pc+0x18/0x20)
[   59.498141] [<c007903c>] (msm_pm_boot_config_before_pc+0x18/0x20) 
from [<c007a55c>] (msm_pm_power_collapse+0x410/0xb04)
[   59.498141] [<c007a55c>] (msm_pm_power_collapse+0x410/0xb04) from 
[<c007b17c>] (arch_idle+0x294/0x3e0)
[   59.498141] [<c007b17c>] (arch_idle+0x294/0x3e0) from [<c000eed8>] 
(default_idle+0x18/0x2c)
[   59.498141] [<c000eed8>] (default_idle+0x18/0x2c) from [<c000f254>] 
(cpu_idle+0x90/0xe4)
[   59.498141] [<c000f254>] (cpu_idle+0x90/0xe4) from [<c057231c>] 
(rest_init+0x88/0xa0)
[   59.498141] [<c057231c>] (rest_init+0x88/0xa0) from [<c07ff890>] 
(start_kernel+0x3a8/0x40c)
[   59.498141] Code: c0704256 e12fff1e e59f2020 e5923000 (e5930000)


I am observing the crash on 3.4 but not on the 3.0 kernel.I check the 
"arch/arch/mm/ioremap.c" code changes between 3.0 and 3.4. I came across 
few changes that are uploaded by "Nicolas Pitre" and few fixes made by 
RMK and Pawel Moll.

I don't see a crash after i commented out the below code in 
__arm_ioremap_pfn_caller().


read_lock()
---
loop
---
read_unlock()


Here i am pasting a few extra logs that i have added into "ioremap.c" & 
"mmu.c" file.

[    0.000000] memory pool 3 (start 2a300000 size 3800000) initialized
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] vm_area_add_early: called with addr=fa100000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa101000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa000000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa102000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa103000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa010000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa900000 size=0xd00000
[    0.000000] vm_area_add_early: called with addr=fa400000 size=0x100000
[    0.000000] vm_area_add_early: called with addr=fa701000 size=0x1000
[    0.000000] vm_area_add_early: called with addr=fa300000 size=0x100000
[    0.000000] vm_area_add_early: called with addr=fa200000 size=0x100000
[    0.000000] vm_area_add_early: called with addr=fa500000 size=0x100000
[    0.000000] vm_area_add_early: called with addr=fa800000 size=0x100000
...
...
...
[ 0.161784] ioremap: pfn=0x0 phys=0x0 offset=0x0 size=0x1000
[ 0.161813] ioremap: area da0fbdc0: phys_addr=0xc0100000 pfn=0xc0100 
size=0x1000
[ 0.161838] ioremap: area da0fbe20: phys_addr=0xa8600000 pfn=0xa8600 
size=0x1000
[ 0.161861] ioremap: area da0fbd80: phys_addr=0xc0000000 pfn=0xc0000 
size=0x1000
[ 0.161886] ioremap: area da0fbda0: phys_addr=0xc0100000 pfn=0xc0100 
size=0x1000
[ 0.161909] ioremap: area da0fbde0: phys_addr=0xa9200000 pfn=0xa9200 
size=0x1000
[ 0.161933] ioremap: area da0fbe00: phys_addr=0xa9300000 pfn=0xa9300 
size=0x1000
[ 0.161956] ioremap: area da0fbd40: phys_addr=0x0 pfn=0x0 size=0x100000
[ 0.161979] ioremap: found: addr fa200000 => 0xfa200000 => 0xfa200000
[ 0.161999] *** reset_vector = 0xfa200000


Can someone know me what is wrong in ioremap call?
Why i am not seeing a crash after i commented out the loop above?


Thanks,
Murali N

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From ludovic.desroches at atmel.com  Tue Aug 21 10:29:00 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:29:00 +0200
Subject: [RFC PATCH 0/5] fixes and DT support based on Nikolaus TWI driver
Message-ID: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Hi Nikolaus,

First of all, thanks for the work you have done on i2c-at91 driver and sorry
to have been so long to answer you.

This set of patches is based on:
http://article.gmane.org/gmane.linux.kernel/1285193/match=patch+v10+0+4+at91+replace+broken+twi+driver+i2c+c

On my side, I don't see any issue with this new driver. I am not an I2C guru
but it works with all the I2C devices I have and your patches have already
been reviewed and tested. I'll continue to test it with other I2C devices and
on several chips.

So the goal of this set of patches is to get feedback on the fix I added, on
the DT support and to resurect your set of patches.

Regards

Ludovic

Ludovic Desroches (5):
  i2c: at91: add new fixes for some TWI ip versions
  i2c: at91: add dt support to i2c-at91
  ARM: at91: add clocks for i2c DT entries
  ARM: dts: add twi nodes for atmel SOCs
  ARM: dts: add twi nodes for atmel boards

 .../devicetree/bindings/i2c/atmel-i2c.txt          | 29 +++++++++
 arch/arm/boot/dts/at91sam9260.dtsi                 | 23 +++----
 arch/arm/boot/dts/at91sam9263.dtsi                 | 23 +++----
 arch/arm/boot/dts/at91sam9263ek.dts                | 20 +++---
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi        | 28 ++++-----
 arch/arm/boot/dts/at91sam9g25ek.dts                | 12 ++++
 arch/arm/boot/dts/at91sam9g45.dtsi                 | 33 ++++++----
 arch/arm/boot/dts/at91sam9m10g45ek.dts             | 14 +++++
 arch/arm/boot/dts/at91sam9n12.dtsi                 | 33 ++++++----
 arch/arm/boot/dts/at91sam9n12ek.dts                |  8 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  | 69 +++++++++------------
 arch/arm/mach-at91/at91rm9200_devices.c            |  9 ---
 arch/arm/mach-at91/at91sam9260.c                   |  1 +
 arch/arm/mach-at91/at91sam9263.c                   |  1 +
 arch/arm/mach-at91/at91sam9g45.c                   |  2 +
 arch/arm/mach-at91/at91sam9n12.c                   |  2 +
 arch/arm/mach-at91/at91sam9x5.c                    |  3 +
 drivers/i2c/busses/i2c-at91.c                      | 71 ++++++++++++++++------
 18 files changed, 239 insertions(+), 142 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/i2c/atmel-i2c.txt

-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 21 10:29:01 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:29:01 +0200
Subject: [PATCH 1/5] i2c: at91: add new fixes for some TWI ip versions
In-Reply-To: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

The at91sam9261 TWI ip version requires also some fixes. The id_entry
field from the platform device structure has been replaced by the use
of cpu_is_xxx function to determine when to use these fixes.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91rm9200_devices.c |  9 -------
 drivers/i2c/busses/i2c-at91.c           | 42 +++++++++++++++++++--------------
 2 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 2b9b493..e6b7d05 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -494,18 +494,9 @@ static struct resource twi_resources[] = {
 	},
 };
 
-static const struct platform_device_id twi_id = {
-	/*
-	 * driver_data is "1" for hardware with ckdiv upper limit == 5
-	 * (AT91RM9200 erratum 22), "0" for twi modules without this bug
-	 */
-	.driver_data	= 1,
-};
-
 static struct platform_device at91rm9200_twi_device = {
 	.name		= "at91_i2c",
 	.id		= -1,
-	.id_entry	= &twi_id,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
 };
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index b1cb780..4599522 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -27,6 +27,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
+#include <mach/cpu.h>
+
 #define TWI_CLK_HZ		100000			/* max 400 Kbits/s */
 #define AT91_I2C_TIMEOUT	msecs_to_jiffies(100)	/* transfer timeout */
 
@@ -72,7 +74,6 @@ struct at91_twi_dev {
 	int			irq;
 	unsigned		transfer_status;
 	struct i2c_adapter	adapter;
-	bool			is_rm9200;
 	unsigned		twi_cwgr_reg;
 };
 
@@ -111,20 +112,28 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-	const int offset = dev->is_rm9200 ? 3 : 4;
-	const int div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
-						 2 * twi_clk) - offset);
-	int ckdiv = fls(div >> 8);
-	int cdiv = div >> ckdiv;
-
-	if (dev->is_rm9200 && (ckdiv > 5)) {
-		dev_warn(dev->dev, "AT91RM9200 erratum 22: using ckdiv = 5.\n");
-		ckdiv = 5;
-		cdiv = 255;
-	} else if (ckdiv > 7) {
-		dev_warn(dev->dev, "%d exceeds 3 bits for ckdiv, limiting.\n",
-			 ckdiv);
-		ckdiv = 7;
+	int offset, div, max_ckdiv, ckdiv, cdiv;
+
+	if (cpu_is_at91rm9200()) {
+		offset = 3;
+		max_ckdiv = 5;
+	} else if (cpu_is_at91sam9261()) {
+		offset = 4;
+		max_ckdiv = 5;
+	} else {
+		offset = 4;
+		max_ckdiv = 7;
+	}
+
+	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
+				       2 * twi_clk) - offset);
+	ckdiv = fls(div >> 8);
+	cdiv = div >> ckdiv;
+
+	if (ckdiv > max_ckdiv) {
+		dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
+			 ckdiv, max_ckdiv);
+		ckdiv = max_ckdiv;
 		cdiv = 255;
 	}
 
@@ -331,9 +340,6 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 		goto err_release_region;
 	}
 
-	if (pdev->id_entry && pdev->id_entry->driver_data == 1)
-		dev->is_rm9200 = 1;
-
 	init_completion(&dev->cmd_complete);
 
 	dev->dev = &pdev->dev;
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 21 10:29:02 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:29:02 +0200
Subject: [PATCH 2/5] i2c: at91: add dt support to i2c-at91
In-Reply-To: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559345-13988-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 .../devicetree/bindings/i2c/atmel-i2c.txt          | 29 +++++++++++++
 drivers/i2c/busses/i2c-at91.c                      | 49 +++++++++++++++++-----
 2 files changed, 68 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/i2c/atmel-i2c.txt

diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
new file mode 100644
index 0000000..9e46289
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
@@ -0,0 +1,29 @@
+I2C for Atmel platforms
+
+Required properties :
+- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c" or
+     "atmel,at91sam9g20-i2c"
+- reg: physical base address of the controller and length of memory mapped
+     region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- Child nodes conforming to i2c bus binding
+
+Examples :
+
+i2c0: i2c at fff84000 {
+	compatible = "atmel,at91sam9g20-i2c";
+	reg = <0xfff84000 0x100>;
+	interrupts = <12 4>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	24c512 at 50 {
+		compatible = "24c512";
+		reg = <0x50>;
+		pagesize = <128>;
+	}
+}
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 4599522..1c86b24 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -24,6 +24,9 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_i2c.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -112,17 +115,27 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
  */
 static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
-	int offset, div, max_ckdiv, ckdiv, cdiv;
-
-	if (cpu_is_at91rm9200()) {
-		offset = 3;
-		max_ckdiv = 5;
-	} else if (cpu_is_at91sam9261()) {
-		offset = 4;
-		max_ckdiv = 5;
+	int offset = 4, max_ckdiv = 7;
+	int div, ckdiv, cdiv;
+
+	if (dev->dev->of_node) {
+		if (of_device_is_compatible(dev->dev->of_node,
+					    "atmel,at91rm9200-i2c")) {
+			offset = 3;
+			max_ckdiv = 5;
+		} else if (of_device_is_compatible(dev->dev->of_node,
+						   "atmel,at91sam9261-i2c")) {
+			offset = 4;
+			max_ckdiv = 5;
+		}
 	} else {
-		offset = 4;
-		max_ckdiv = 7;
+		if (cpu_is_at91rm9200()) {
+			offset = 3;
+			max_ckdiv = 5;
+		} else if (cpu_is_at91sam9261()) {
+			offset = 4;
+			max_ckdiv = 5;
+		}
 	}
 
 	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
@@ -379,6 +392,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 	dev->adapter.dev.parent = dev->dev;
 	dev->adapter.nr = pdev->id;
 	dev->adapter.timeout = AT91_I2C_TIMEOUT;
+	dev->adapter.dev.of_node = pdev->dev.of_node;
 
 	rc = i2c_add_numbered_adapter(&dev->adapter);
 	if (rc) {
@@ -387,6 +401,8 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 		goto err_free_irq;
 	}
 
+	of_i2c_register_devices(&dev->adapter);
+
 	dev_info(dev->dev, "AT91 i2c bus driver.\n");
 	return 0;
 
@@ -454,12 +470,25 @@ static const struct dev_pm_ops at91_twi_pm = {
 #define at91_twi_pm_ops NULL
 #endif
 
+#ifdef CONFIG_OF
+static const struct of_device_id at91_twi_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-i2c", },
+	{ .compatible = "atmel,at91sam9260-i2c", },
+	{ .compatible = "atmel,at91sam9261-i2c", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, at91_twi_dt_ids);
+#else
+#define at91_twi_dt_ids NULL
+#endif
+
 static struct platform_driver at91_twi_driver = {
 	.probe		= at91_twi_probe,
 	.remove		= __devexit_p(at91_twi_remove),
 	.driver		= {
 		.name	= "at91_i2c",
 		.owner	= THIS_MODULE,
+		.of_match_table = at91_twi_dt_ids,
 		.pm	= at91_twi_pm_ops,
 	},
 };
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 21 10:29:03 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:29:03 +0200
Subject: [PATCH 3/5] ARM: at91: add clocks for i2c DT entries
In-Reply-To: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559345-13988-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9260.c | 1 +
 arch/arm/mach-at91/at91sam9263.c | 1 +
 arch/arm/mach-at91/at91sam9g45.c | 2 ++
 arch/arm/mach-at91/at91sam9n12.c | 2 ++
 arch/arm/mach-at91/at91sam9x5.c  | 3 +++
 5 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 2e56321..f3fdca7 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -227,6 +227,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 71305fa..15458ad 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -210,6 +210,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 2944fc7..dcc4e3c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -244,6 +244,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..732d3d3 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1b144b4..744ffc2 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,6 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 21 10:29:04 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:29:04 +0200
Subject: [PATCH 4/5] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559345-13988-5-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Add twi nodes for atmel SOCs and remove i2c-gpio ones.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9263.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9g45.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9n12.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9x5.dtsi  | 69 +++++++++++++++++---------------------
 5 files changed, 90 insertions(+), 91 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index f449efc..0ab7a3c 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -28,6 +28,7 @@
 		gpio2 = &pioC;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -198,6 +199,15 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fffac000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfffac000 0x100>;
+				interrupts = <11 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
@@ -257,17 +267,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 23 0 /* sda */
-			 &pioA 24 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 0209913..efb86dd 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -24,6 +24,7 @@
 		gpio3 = &pioD;
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -179,6 +180,15 @@
 				interrupts = <24 4>;
 				status = "disabled";
 			};
+
+			i2c0: i2c at fff88000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -204,17 +214,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 7dbccaf..8dd3ff8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -29,6 +29,8 @@
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -200,6 +202,24 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fff84000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff84000 0x100>;
+				interrupts = <12 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at fff88000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffb0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffb0000 0x100>;
@@ -268,17 +288,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 20 0 /* sda */
-			 &pioA 21 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index cb84de7..8a1969d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -26,6 +26,8 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -178,6 +180,24 @@
 				atmel,use-dma-tx;
 				status = "disabled";
 			};
+
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -205,17 +225,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 6b3ef43..ec56eaf 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -27,6 +27,9 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
 	};
 	cpus {
 		cpu at 0 {
@@ -191,6 +194,33 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at f8018000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8018000 0x100>;
+				interrupts = <11 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at f804c000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf804c000 0x100>;
@@ -259,43 +289,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 1 {
-		compatible = "i2c-gpio";
-		gpios = <&pioC 0 0 /* sda */
-			 &pioC 1 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 2 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
-- 
1.7.11.3



From wade_farnsworth at mentor.com  Tue Aug 21 10:29:52 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Tue, 21 Aug 2012 07:29:52 -0700
Subject: [PATCH v3] ARM: support syscall tracing
In-Reply-To: <20120821082734.GA28660@mudshark.cambridge.arm.com>
References: <50324BED.9000500@mentor.com>
 <20120820172559.GW25864@mudshark.cambridge.arm.com>
 <5032A1D6.6010605@mentor.com>
 <20120821082734.GA28660@mudshark.cambridge.arm.com>
Message-ID: <50339B60.7030909@mentor.com>

Will Deacon wrote:
> On Mon, Aug 20, 2012 at 09:45:10PM +0100, Wade Farnsworth wrote:
>> Will Deacon wrote:
>>>
>>> I think that trace_sys_{enter,exit} should take ret rather than scno. A
>>> debugger could change the syscall number if TIF_SYSCALL_TRACE is set and
>>> that new number should be the one that we use.
>>>
>>> The style, however, is much better and I think the code is fairly clear now
>>> so we just need to wait for my fix to the core code to get merged (it got
>>> picked up by Steve Rostedt) and I think we can use ret directly. It might be
>>> worth dropping the local variable and using scno for everything, so that
>>> it's obvious where the syscall number is stored.
>>>
>>
>> I agree that your patch needs to get merged before mine gets picked up
>> so that we don't introduce a new bug.  I've sent v4 with the changes you
>> suggest.  Would you like me to modify syscall_trace_* to remove the
>> local variable in this patch as well?  It seems to me that such a rework
>> is better handled separately, but let me know if you think otherwise.
>
> Don't worry about the scno rework -- I'll do that as a separate patch
> because I think that the audit calls need updating to use the return value
> from ptrace_syscall_trace too (otherwise you could use a debugger to execute
> syscalls that you shouldn't be allowed to make).
>
> So, if it's ok with you, I'll take this into my tree and then send it to
> Russell along with the scno change once the core fix has been merged into
> mainline.

Sounds great.  Thanks, Will!

Wade




From ludovic.desroches at atmel.com  Tue Aug 21 10:30:49 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:30:49 +0200
Subject: [PATCH 4/5] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <1345559345-13988-5-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-5-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559449-14034-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Add twi nodes for atmel SOCs and remove i2c-gpio ones.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9263.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9g45.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9n12.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9x5.dtsi  | 69 +++++++++++++++++---------------------
 5 files changed, 90 insertions(+), 91 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index f449efc..0ab7a3c 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -28,6 +28,7 @@
 		gpio2 = &pioC;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -198,6 +199,15 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fffac000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfffac000 0x100>;
+				interrupts = <11 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
@@ -257,17 +267,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 23 0 /* sda */
-			 &pioA 24 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 0209913..efb86dd 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -24,6 +24,7 @@
 		gpio3 = &pioD;
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -179,6 +180,15 @@
 				interrupts = <24 4>;
 				status = "disabled";
 			};
+
+			i2c0: i2c at fff88000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -204,17 +214,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 7dbccaf..8dd3ff8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -29,6 +29,8 @@
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -200,6 +202,24 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fff84000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff84000 0x100>;
+				interrupts = <12 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at fff88000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffb0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffb0000 0x100>;
@@ -268,17 +288,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 20 0 /* sda */
-			 &pioA 21 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index cb84de7..8a1969d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -26,6 +26,8 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -178,6 +180,24 @@
 				atmel,use-dma-tx;
 				status = "disabled";
 			};
+
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -205,17 +225,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 6b3ef43..ec56eaf 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -27,6 +27,9 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
 	};
 	cpus {
 		cpu at 0 {
@@ -191,6 +194,33 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at f8018000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xf8018000 0x100>;
+				interrupts = <11 4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at f804c000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf804c000 0x100>;
@@ -259,43 +289,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 1 {
-		compatible = "i2c-gpio";
-		gpios = <&pioC 0 0 /* sda */
-			 &pioC 1 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 2 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Tue Aug 21 10:32:00 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Tue, 21 Aug 2012 16:32:00 +0200
Subject: [PATCH 5/5] ARM: dts: add twi nodes for atmel boards
In-Reply-To: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1345559520-14074-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Use the atmel twi instead of gpio for i2c stuff.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9263ek.dts         | 20 ++++++++++----------
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 28 ++++++++++++++--------------
 arch/arm/boot/dts/at91sam9g25ek.dts         | 12 ++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      | 14 ++++++++++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |  8 ++++++++
 5 files changed, 58 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b..772ab75 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -50,6 +50,16 @@
 				atmel,vbus-gpio = <&pioA 25 0>;
 				status = "okay";
 			};
+
+			i2c0: i2c at fff88000 {
+				status = "okay";
+
+				24c512 at 50 {
+					compatible = "24c512";
+					reg = <0x50>;
+					pagesize = <128>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -143,14 +153,4 @@
 			gpio-key,wakeup;
 		};
 	};
-
-	i2c at 0 {
-		status = "okay";
-
-		24c512 at 50 {
-			compatible = "24c512";
-			reg = <0x50>;
-			pagesize = <128>;
-		};
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index b06c0db..712106b 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -51,6 +51,20 @@
 				atmel,vbus-gpio = <&pioC 5 0>;
 				status = "okay";
 			};
+
+			i2c0: i2c at fffac000 {
+				status = "okay";
+
+				24c512 at 50 {
+					compatible = "24c512";
+					reg = <0x50>;
+				};
+
+				wm8731 at 1b {
+					compatible = "wm8731";
+					reg = <0x1b>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -106,20 +120,6 @@
 		};
 	};
 
-	i2c at 0 {
-		status = "okay";
-
-		24c512 at 50 {
-			compatible = "24c512";
-			reg = <0x50>;
-		};
-
-		wm8731 at 1b {
-			compatible = "wm8731";
-			reg = <0x1b>;
-		};
-	};
-
 	gpio_keys {
 		compatible = "gpio-keys";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7829a4d..3b0adbc 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,18 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			i2c0: i2c at f8010000 {
+				status = "okay";
+			};
+
+			i2c1: i2c at f8014000 {
+				status = "okay";
+			};
+
+			i2c2: i2c at f8018000 {
+				status = "okay";
+			};
 		};
 
 		usb0: ohci at 00600000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd..4f94f23 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -46,6 +46,20 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			i2c0: i2c at fff84000 {
+				status = "okay";
+
+				24c512 at 50 {
+					compatible = "24c512";
+					reg = <0x50>;
+					pagesize = <128>;
+				};
+			};
+			
+			i2c1: i2c at fff88000 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index f4e43e3..912b2c2 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -37,6 +37,14 @@
 			dbgu: serial at fffff200 {
 				status = "okay";
 			};
+
+			i2c0: i2c at f8010000 {
+				status = "okay";
+			};
+
+			i2c1: i2c at f8014000 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.11.3



From peter.ujfalusi at ti.com  Tue Aug 21 10:33:56 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 21 Aug 2012 17:33:56 +0300
Subject: [PATCH] ASoC: omap-mcbsp: Device tree binding documentation update
Message-ID: <1345559636-23370-1-git-send-email-peter.ujfalusi@ti.com>

To reflect the final devicetree node structure of McBSPs.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---

Hello,

the initial OMAP McBSP DT structure was not able to describe the IP (and it's
versions) correctly.
The main issue was the sidetone block of McBSP2/3 on OMAP3.
With this change in the DT description the OS can get the needed information
about the IP.

The sidetone is still not supported when the Linux kernel is booted with DT
since we still depend on hwmod to fill the resources.

This patch depend on the McBSP DT support series going via audio tree.

Regards,
Peter

 .../devicetree/bindings/sound/omap-mcbsp.txt       |   28 +++++++------------
 1 files changed, 10 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
index 447cb13..17cce44 100644
--- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -8,38 +8,30 @@ Required properties:
 - reg: Register location and size, for OMAP4+ as an array:
        <MPU access base address, size>,
        <L3 interconnect address, size>;
+- reg-names: Array of strings associated with the address space
 - interrupts: Interrupt numbers for the McBSP port, as an array in case the
 	      McBSP IP have more interrupt lines:
 	<OCP compliant irq>,
 	<TX irq>,
 	<RX irq>;
+- interrupt-names: Array of strings associated with the interrupt numbers
 - interrupt-parent: The parent interrupt controller
 - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
 - ti,hwmods: Name of the hwmod associated to the McBSP port
 
-Sidetone support for OMAP3 McBSP2 and 3 ports:
-- sidetone { }: Within this section the following parameters are required:
-- reg: Register location and size for the ST block
-- interrupts: The interrupt number for the ST block
-- interrupt-parent: The parent interrupt controller for the ST block
-
 Example:
 
 mcbsp2: mcbsp at 49022000 {
 	compatible = "ti,omap3-mcbsp";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	reg = <0x49022000 0xff>;
-	interrupts = <0 17 0x4>, /* OCP compliant interrup */
-		     <0 62 0x4>, /* TX interrup */
-		     <0 63 0x4>; /* RX interrup */
+	reg = <0x49022000 0xff>,
+	      <0x49028000 0xff>;
+	reg-names = "mpu", "sidetone";
+	interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+		     <0 62 0x4>, /* TX interrupt */
+		     <0 63 0x4>, /* RX interrupt */
+		     <0 4 0x4>;  /* Sidetone */
+	interrupt-names = "common", "tx", "rx", "sidetone";
 	interrupt-parent = <&intc>;
 	ti,buffer-size = <1280>;
 	ti,hwmods = "mcbsp2";
-
-	sidetone {
-		reg = <0x49028000 0xff>;
-		interrupts = <0 4 0x4>;
-		interrupt-parent = <&intc>;
-	};
 };
-- 
1.7.8.6



From m.szyprowski at samsung.com  Tue Aug 21 10:46:54 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 16:46:54 +0200
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous
 Memory Allocator
In-Reply-To: <201208202001.23443.arnd@arndb.de>
References: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
 <201208202001.23443.arnd@arndb.de>
Message-ID: <00c001cd7fab$d145f350$73d1d9f0$%szyprowski@samsung.com>

Hello,

On Monday, August 20, 2012 10:01 PM Arnd Bergmann wrote:

> On Monday 20 August 2012, Marek Szyprowski wrote:
> > Contiguous Memory Allocator requires only paging and MMU enabled not
> > particular CPU architectures, so there is no need for strict dependency
> > on CPU type. This enables to use CMA on some older ARM v5 systems which
> > also might need large contiguous blocks for the multimedia processing hw
> > modules.
> >
> > Reported-by: Prabhakar Lad <prabhakar.csengg at gmail.com>
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> 
> The patch looks simple, but I want a better explanation for it.
> When we went through all possible cases, we decided that:
> 
> * ARMv6+ need CMA to avoid the double mapping problem.

Right. CMA can be used to avoid double mapping issues, but we also should keep in
mind that right now no one observed any issues with the real hw, so this discussion
is still a bit hypothetical.

> * ARMv4/v5 cannot generally use CMA because it doesn't work
>   together with DMABOUNCE. I don't remember if it was the
>   only problem, but I definitely remember this was intentional.

DMABOUNCE is used only by a few machines. I also tested and see no reason why it 
might cause problems with such machines. I've used DMABOUNCE code to test atomic 
allocations many times and found no problems. The only issue I might suspect is 
a very limited DMA zone. CMA needs 4Mib alignment of the contiguous area base and
size to meet requirements of the memory management core (mainly for migration and
page isolation purposes), so it might not fit into some small DMA zones.

> * We want a common kernel for all ARMv6+ eventually, and a
>   separate kernel for all ARMv4/v5 ones.

I see no problem here, if required why may have even a separate dma_map_ops for
CMA and use it only for selected devices.

> 
> If the reasoning has changed, please try to explain the full
> situation. On a related topic, what happened to the idea that
> ARMv6+ is broken without CMA? I noticed that it's optional
> now.

Right. I removed unconditional dependency on CMA on Russell's request. CMA is
still experimental and there are still some known issues with it, which we are 
investigating. It doesn't make sense to make the whole architecture depending
on the experimental stuff. The old method of allocating and managing coherent
buffers was stable and worked well enough for the drivers and platforms already
present in the mainline kernel, so if one want to use stable stuff I see no 
reason to disable it.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From m.szyprowski at samsung.com  Tue Aug 21 10:47:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 16:47:25 +0200
Subject: [PATCH] ARM: relax conditions required for enabling Contiguous
 Memory Allocator
In-Reply-To: <20120821121256.GT18957@n2100.arm.linux.org.uk>
References: <1345443372-3824-1-git-send-email-m.szyprowski@samsung.com>
 <201208202001.23443.arnd@arndb.de>
 <20120821121256.GT18957@n2100.arm.linux.org.uk>
Message-ID: <00c101cd7fab$e341fc20$a9c5f460$%szyprowski@samsung.com>

Hello,

On Tuesday, August 21, 2012 2:13 PM Russell King - ARM Linux wrote:

> On Mon, Aug 20, 2012 at 08:01:23PM +0000, Arnd Bergmann wrote:
> > The patch looks simple, but I want a better explanation for it.
> > When we went through all possible cases, we decided that:
> >
> > * ARMv6+ need CMA to avoid the double mapping problem.
> > * ARMv4/v5 cannot generally use CMA because it doesn't work
> >   together with DMABOUNCE. I don't remember if it was the
> >   only problem, but I definitely remember this was intentional.
> > * We want a common kernel for all ARMv6+ eventually, and a
> >   separate kernel for all ARMv4/v5 ones.
> >
> > If the reasoning has changed, please try to explain the full
> > situation.
> 
> Indeed.
> 
> > On a related topic, what happened to the idea that
> > ARMv6+ is broken without CMA? I noticed that it's optional
> > now.
> 
> With Marek's patch, it's always selected for MMU-based builds (it can't
> be disabled).  Before the patch, it was always selected for V6 and later
> CPUs.

My patch only alters dependences of HAVE_DMA_CONTIGUOUS symbol, by changing
them from CPU_V6+ to MMU. It doesn't change or select CMA for any of the 
systems - this is done by the CONFIG_CMA symbol from drivers/base/KConfig 
which depends on HAVE_DMA_CONTIGUOUS. It is up to user to enable it or not.

> And the description doesn't make sense:
> 
> "Contiguous Memory Allocator requires only paging and MMU enabled not
> particular CPU architectures,"
> 
> what does "only paging and MMU enabled" mean?  Are you trying to say that
> CMA only requires a kernel with MMU support?

On ARM architecture CMA can be enabled on any system which has MMU support, 
MMU is required for page migration. The integration layer in dma-mapping is 
generic enough to work on any ARM architecture.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From m.szyprowski at samsung.com  Tue Aug 21 10:48:58 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 16:48:58 +0200
Subject: [PATCH 0/4] Per device coherent DMA map ops
In-Reply-To: <201208202006.24851.arnd@arndb.de>
References: <1344916147-13546-1-git-send-email-robherring2@gmail.com>
 <000601cd7ede$5d2ef390$178cdab0$%szyprowski@samsung.com>
 <50324F9A.5000608@gmail.com> <201208202006.24851.arnd@arndb.de>
Message-ID: <00c201cd7fac$1abf75b0$503e6110$%szyprowski@samsung.com>

Hello,

On Monday, August 20, 2012 10:06 PM Arnd Bergmann wrote:

> On Monday 20 August 2012, Rob Herring wrote:
> > >
> > > I like those patches and I would like to take it to my dma-mapping-next tree, but I wonder
> > > how to handle merging of the last patch. Arnd, Olof - could You tell me how to do it? I
> assume
> > > that it should be somehow merged by arm-soc tree, so it depends on the earlier patches.
> > > Would it be enough if I take them to the topic branch? Then I can continue works on
> > > dma-mapping subsystem by merging that topic branch to my dma-mapping-next and you will
> > > also take it as a dependency for highbank patches. Am I right?
> > >
> >
> > I'm fine with it all going in thru your tree. Seems a bit silly to deal
> > with tracking the dependencies all for 1 patch. The only possible
> > conflict I see is with the dts file and some other SATA related changes
> > which will go in via the ata tree. But the merge is trivial and the
> > conflict will be there either with your tree or arm-soc.
> 
> Right. I see no problem having this patch go through the dma-mapping tree.

Ok, I've took them to my dma-mapping-next tree and I will handle pushing them to Linus.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From broonie at opensource.wolfsonmicro.com  Tue Aug 21 10:50:09 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 15:50:09 +0100
Subject: [RFC/PATCH 4/4] gpio: smscece: Add support for gpio IO
 expander feature
In-Reply-To: <20120821122217.GF10347@arwen.pp.htv.fi>
References: <1345545940-2232-1-git-send-email-sourav.poddar@ti.com>
 <1345545940-2232-5-git-send-email-sourav.poddar@ti.com>
 <20120821105333.GW10347@arwen.pp.htv.fi>
 <CAKdam56DiFpnoQwrHe1tjQWLMy5vP9ynstNj_n=OyMxkJJAUOA@mail.gmail.com>
 <20120821120052.GD10347@arwen.pp.htv.fi>
 <CAKdam55SqXiCGv766yxoY1GdDjxNCYNaDdNZPaeLTAXc+3+c6g@mail.gmail.com>
 <20120821122217.GF10347@arwen.pp.htv.fi>
Message-ID: <20120821145009.GE21557@sirena.org.uk>

On Tue, Aug 21, 2012 at 03:22:18PM +0300, Felipe Balbi wrote:
> On Tue, Aug 21, 2012 at 05:50:28PM +0530, Poddar, Sourav wrote:

> > If I am understanding correctly, if they both uses the same bit we cannot
> > use both for a particular user. ?

> we can, it's just a bit more complex. If a user request both LOW and
> HIGH, then you start with HIGH, once it triggers, before calling the
> nested IRQ handler, you need to change it LOW. When low triggers, before
> calling the nested IRQ handler, you need to change it to HIGH again. And
> so on. I'm just not sure if that's valid on linux IRQ subsystem.

The given example was for keypress - usually a system would use edge
triggered interrupts in combination with reading the GPIO state rather
than level triggered interrupts.


From m.szyprowski at samsung.com  Tue Aug 21 11:01:08 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 21 Aug 2012 17:01:08 +0200
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <20120821.151521.702882672715065253.hdoyu@nvidia.com>
References: <1343636899-19508-1-git-send-email-m.szyprowski@samsung.com>
 <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com>
 <20120821142235.97984abc9ad98d01015a3338@nvidia.com>
 <20120821.151521.702882672715065253.hdoyu@nvidia.com>
Message-ID: <00c301cd7fad$cfc7f3f0$6f57dbd0$%szyprowski@samsung.com>

Hi Hiroshi,

On Tuesday, August 21, 2012 2:15 PM Hiroshi Doyu wrote:

> Hiroshi Doyu <hdoyu at nvidia.com> wrote @ Tue, 21 Aug 2012 13:22:35 +0200:
> 
> > Hi,
> >
> > On Mon, 30 Jul 2012 10:28:19 +0200
> > Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> >
> > > This patch changes dma-mapping subsystem to use generic vmalloc areas
> > > for all consistent dma allocations. This increases the total size limit
> > > of the consistent allocations and removes platform hacks and a lot of
> > > duplicated code.
> > >
> > > Atomic allocations are served from special pool preallocated on boot,
> > > because vmalloc areas cannot be reliably created in atomic context.
> > >
> > > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > > Reviewed-by: Kyungmin Park <kyungmin.park at samsung.com>
> > > ---
> > >  Documentation/kernel-parameters.txt |    2 +-
> > >  arch/arm/include/asm/dma-mapping.h  |    2 +-
> > >  arch/arm/mm/dma-mapping.c           |  486 ++++++++++++-----------------------
> > >  arch/arm/mm/mm.h                    |    3 +
> > >  include/linux/vmalloc.h             |    1 +
> > >  mm/vmalloc.c                        |   10 +-
> > >  6 files changed, 181 insertions(+), 323 deletions(-)
> > >
> > ...
> > > @@ -1117,61 +984,32 @@ static int __iommu_free_buffer(struct device *dev, struct page
> **pages, size_t s
> > >   * Create a CPU mapping for a specified pages
> > >   */
> > >  static void *
> > > -__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
> > > +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
> > > +                   const void *caller)
> > >  {
> > > -       struct arm_vmregion *c;
> > > -       size_t align;
> > > -       size_t count = size >> PAGE_SHIFT;
> > > -       int bit;
> > > +       unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
> > > +       struct vm_struct *area;
> > > +       unsigned long p;
> > >
> > > -       if (!consistent_pte[0]) {
> > > -               pr_err("%s: not initialised\n", __func__);
> > > -               dump_stack();
> > > +       area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
> > > +                                 caller);
> > > +       if (!area)
> >
> > This patch replaced the custom "consistent_pte" with
> > get_vm_area_caller()", which breaks the compatibility with the
> > existing driver. This causes the following kernel oops(*1). That
> > driver has called dma_pool_alloc() to allocate memory from the
> > interrupt context, and it hits BUG_ON(in_interrpt()) in
> > "get_vm_area_caller()"(*2). Regardless of the badness of allocation
> > from interrupt handler in the driver, I have the following question.
> >
> > The following "__get_vm_area_node()" can take gfp_mask, it means that
> > this function is expected to be called from atomic context, but why
> > it's _NOT_ allowed _ONLY_ from interrupt context?
> >
> > According to the following definitions, "in_interrupt()" is in "in_atomic()".
> >
> > #define in_interrupt()	(preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK | NMI_MASK))
> > #define in_atomic()	((preempt_count() & ~PREEMPT_ACTIVE) != 0)
> >
> > Does anyone know why BUG_ON(in_interrupt()) is set in __get_vm_area_node(*3)?
> 
> For arm_dma_alloc(), it allocates from the pool if GFP_ATOMIC, but for
> arm_iommu_alloc_attrs() doesn't have pre-allocate pool at all, and it
> always call "get_vm_area_caller()". That's why it hits BUG(). But
> still I don't understand why it's not BUG_ON(in_atomic) as Russell
> already pointed out(*1).
> 
> *1: http://article.gmane.org/gmane.linux.kernel.mm/76708

Ok, now I see the problem. I will try to find out a solution for your issue.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From balbi at ti.com  Tue Aug 21 11:07:04 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 21 Aug 2012 18:07:04 +0300
Subject: [PATCH v2 00/13] OMAP Serial patches
In-Reply-To: <20120821130134.GH10347@arwen.pp.htv.fi>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
 <20120821130134.GH10347@arwen.pp.htv.fi>
Message-ID: <20120821150702.GN10347@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 04:01:36PM +0300, Felipe Balbi wrote:
> Hi,
> 
> On Tue, Aug 21, 2012 at 03:15:58PM +0300, Felipe Balbi wrote:
> > Hi guys,
> > 
> > here's a series of cleanup patches to the OMAP serial
> > driver. A later series could be made re-implementing
> > DMA using the DMA Engine API. Note that for RX DMA
> > we could be using RX Timeout IRQ as a hint that we better
> > use PIO instead ;-)
> > 
> > All patches were tested on my pandaboard, but I'd really
> > like to receive Tested-by on other platforms.
> > 
> > After this goes in, I'll probably try to get UART wakeup
> > working again and only after that look at DMA.
> > 
> > Changes since v1:
> > 
> > 	. improved commit log on patch 9/13 (formerly 10/13)
> > 	. removed patch 2/13
> > 	. added a new patch switching from spin_lock_irqsave() to spin_lock and
> > 		spin_unlock_irqrestore to spin_unlock
> > 
> > Retested with my pandaboard, UART continues to work:
> > 
> >  # grep -i uart /proc/interrupts
> >  106:        124          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        189          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        255          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        321          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        387          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        453          0       GIC  OMAP UART2
> >  #  grep -i uart /proc/interrupts
> >  106:        519          0       GIC  OMAP UART2
> > 
> > cheers
> > 
> > ps: if anyone knows a better test for UART, let me know.
> > 
> > for convenience of anyone testing, patches are available on my git tree [1] on
> > branch uart
> > 
> > [1] git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart
> 
> I have added one extra patch to this series:
> 
> From 6921efdb13dda7af216b331bb35535d4b53f004a Mon Sep 17 00:00:00 2001
> From: Felipe Balbi <balbi at ti.com>
> Date: Tue, 21 Aug 2012 15:48:35 +0300
> Subject: [PATCH] serial: omap: drop pm_runtime_irq_safe() usage
> 
> pm_runtime_irq_safe() will essentially do an
> unbalanced pm_runtime_get_sync() on our parent
> device, which might cause problems when trying
> to suspend.
> 
> In order to prevent that we drop pm_runtime_irq_safe
> usage in exchange for a little performance hit
> when we enter our IRQ handler while still suspended.
> 
> If that happens, what we will do is set the irq_pending
> flag, do an asynchronous pm_runtime_get() call and
> return IRQ_HANDLED. When our runtime_resume() callback
> is executed, we check for that flag, and run our
> IRQ handler so that we receive/transmit the pending
> characters.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
> 
> One extra patch to OMAP UART driver. This seems to be working
> pretty well even after echo mem > /sys/power/state. I can
> see that I can even wake my pandaboard up by sending a character
> through serial:
> 
>  #  echo mem > /sys/power/state
>  [ 1335.679260] PM: Syncing filesystems ... done.
>  [ 1335.684387] Freezing user space processes ... (elapsed 0.00 seconds) done.
>  [ 1335.691741] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
>  [ 1335.720886] Suspending console(s) (use no_console_suspend to debug)
>  
>  [ 1335.734405] PM: suspend of devices complete after 5.492 msecs
>  [ 1335.735534] PM: late suspend of devices complete after 1.128 msecs
>  [ 1335.737518] PM: noirq suspend of devices complete after 1.952 msecs
>  [ 1335.737518] Disabling non-boot CPUs ...
>  [ 1335.738525] CPU1: shutdown
>  [ 1338.543762] Successfully put all powerdomains to target state
>  [ 1338.543853] Enabling non-boot CPUs ...
>  [ 1338.545654] CPU1: Booted secondary processor
>  [ 1338.546020] CPU1 is up
>  [ 1338.547027] PM: noirq resume of devices complete after 0.976 msecs
>  [ 1338.548400] PM: early resume of devices complete after 0.762 msecs
>  [ 1339.827087] PM: resume of devices complete after 1278.686 msecs
>  [ 1339.890960] Restarting tasks ... done.
>  # # grep -i uart /proc/interrupts
>  106:       3385          0       GIC  OMAP UART2
>  # echo mem > /sys/power/state
>  [ 1358.015624] PM: Syncing filesystems ... done.
>  [ 1358.020812] Freezing user space processes ... (elapsed 0.00 seconds) done.
>  [ 1358.028167] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
>  [ 1358.055084] Suspending console(s) (use no_console_suspend to debug)
>  
>  [ 1358.068847] PM: suspend of devices complete after 5.633 msecs
>  [ 1358.070007] PM: late suspend of devices complete after 1.126 msecs
>  [ 1358.072051] PM: noirq suspend of devices complete after 2.040 msecs
>  [ 1358.072051] Disabling non-boot CPUs ...
>  [ 1358.073211] CPU1: shutdown
>  [ 1359.104156] Successfully put all powerdomains to target state
>  [ 1359.104278] Enabling non-boot CPUs ...
>  [ 1359.106079] CPU1: Booted secondary processor
>  [ 1359.106475] CPU1 is up
>  [ 1359.107482] PM: noirq resume of devices complete after 1.004 msecs
>  [ 1359.108886] PM: early resume of devices complete after 0.761 msecs
>  [ 1360.414794] PM: resume of devices complete after 1305.836 msecs
>  [ 1360.478668] Restarting tasks ... done.
>  # # grep -i uart /proc/interrupts
>  106:       3511          0       GIC  OMAP UART2
> 
>  arch/arm/plat-omap/include/plat/omap-serial.h |  1 +
>  drivers/tty/serial/omap-serial.c              | 16 +++++++++++++---
>  2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
> index 743ac80..52328ca 100644
> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
> @@ -130,6 +130,7 @@ struct uart_omap_port {
>  	u32			context_loss_cnt;
>  	u32			errata;
>  	u8			wakeups_enabled;
> +	unsigned int		irq_pending:1;
>  
>  	struct pm_qos_request	pm_qos_request;
>  	u32			latency;
> diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> index a79658d..7e237f3 100644
> --- a/drivers/tty/serial/omap-serial.c
> +++ b/drivers/tty/serial/omap-serial.c
> @@ -353,9 +353,13 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
>  	irqreturn_t ret = IRQ_HANDLED;
>  	int max_count = 256;
>  
> -	spin_lock(&up->port.lock);
> -	pm_runtime_get_sync(up->dev);
> +	if (pm_runtime_suspended(up->dev)) {
> +		up->irq_pending = true;
> +		pm_runtime_get(up->dev);
> +		return IRQ_HANDLED;
> +	}
>  
> +	spin_lock(&up->port.lock);
>  	do {
>  		iir = serial_in(up, UART_IIR);
>  		if (iir & UART_IIR_NO_INT) {
> @@ -400,6 +404,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
>  	pm_runtime_mark_last_busy(up->dev);
>  	pm_runtime_put_autosuspend(up->dev);
>  	up->port_activity = jiffies;
> +	up->irq_pending = false;
>  
>  	return ret;
>  }
> @@ -1305,7 +1310,6 @@ static int serial_omap_probe(struct platform_device *pdev)
>  	pm_runtime_set_autosuspend_delay(&pdev->dev,
>  			omap_up_info->autosuspend_timeout);
>  
> -	pm_runtime_irq_safe(&pdev->dev);
>  	pm_runtime_enable(&pdev->dev);
>  	pm_runtime_get_sync(&pdev->dev);
>  
> @@ -1416,6 +1420,9 @@ static int serial_omap_runtime_suspend(struct device *dev)
>  	if (!up)
>  		return -EINVAL;
>  
> +	if (up->irq_pending)
> +		return -EBUSY;
> +
>  	if (!pdata)
>  		return 0;
>  
> @@ -1452,6 +1459,9 @@ static int serial_omap_runtime_resume(struct device *dev)
>  
>  		up->latency = up->calc_latency;
>  		schedule_work(&up->qos_work);
> +
> +		if (up->irq_pending)
> +			serial_omap_irq(up->port.irq, up);
>  	}
>  
>  	return 0;

let's not apply this extra patch. It actually caused a regression which
was pretty difficult to trigger. I have now dropped it from my series.
Sorry for the noise.

-- 
balbi
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From gcembed at gmail.com  Tue Aug 21 11:14:47 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Tue, 21 Aug 2012 17:14:47 +0200
Subject: mx27_3ds : Sound doesn't work anymore on linux-next
In-Reply-To: <502E6329.60308@gmail.com>
References: <502E6033.4010805@gmail.com> <502E6329.60308@gmail.com>
Message-ID: <5033A5E7.2030701@gmail.com>

Hi,
On 08/17/2012 05:28 PM, Ga?tan Carlier wrote:
> Just some more informations, process enter in D+ state and this is so
> impossible to kill them.
> On 08/17/2012 05:16 PM, Ga?tan Carlier wrote:
>> Hi,
>> It is several days that I tried to make sound work on mx27_3ds platform
>> from linux-next (daily cloned/pulled) but each time I try start start
>> aplay or alsamixer, the process freeze and CTRL+C has not effect. I can
>> open another SSH session and execute other commands but alsa commands
>> always freeze.
>> The sound card is correctly installer at boot :
>>
>> imx_mc13783 imx_mc13783.0:  mc13783-hifi <-> imx-ssi.0 mapping ok
>> ALSA device list:
>>    #0: imx_mc13783
>>
>> I only apply the patch "[PATCH 1/2] ARM: mx27pdk: Add audio support". I
>> attach my config file.
>>
>> I try to apply patch on a previous commit when I told that this patch
>> was working but it didn't succeed the is still freezing.
>> I try to make it working on another mx27-based platform but same
>> problem. I try to update Alsa from version 1.0.23 to 1.0.25 but same
>> behaviour.
>> What is wrong ?
>>
>> Regards,
>> Ga?tan Carlier.
>
> Regards,
> Ga?tan.
>
I have more informations about the problem : freeze only occurs when I 
disable MMC device support (CONFIG_MMC_MXC=n).
I don't know why these two drivers affect each other (except that CSPI 
for MC13783 and SDHC use the same PERDIV1 clock).
So I enable it back and try put a "return 0" in mxcmmc.c (only for debug 
purpose) as following :

### This makes alsamixer working
@@ -913,10 +913,11 @@ static int mxcmci_probe(struct platform_device *pdev)
  		goto out_iounmap;
  	}

  	clk_prepare_enable(host->clk_per);
  	clk_prepare_enable(host->clk_ipg);
+return 0;

  	mxcmci_softreset(host);

  	host->rev_no = readw(host->base + MMC_REG_REV_NO);
  	if (host->rev_no != 0x400) {

### This makes alsamixer freezing
@@ -898,10 +898,11 @@ static int mxcmci_probe(struct platform_device *pdev)
  	else
  		host->default_irq_mask = 0;

  	host->res = r;
  	host->irq = irq;
+return 0;

  	host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  	if (IS_ERR(host->clk_ipg)) {
  		ret = PTR_ERR(host->clk_ipg);
  		goto out_iounmap;


So I supposed that there is a problem in clock definition but I don't 
now how to solve it. I try to replace in clk-imx27.c
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
by
clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "imx-ssi.0");

and in imx-ssi.c in imx_ssi_probe(), replaced
ssi->clk = devm_clk_get(&pdev->dev, "ipg");
by
ssi->clk = devm_clk_get(&pdev->dev, "ipg");

This has no effect. I don't fully know how clock mechanism for imx27 
works so I am not able to solve this problem and send a patch.
Regards,
Ga?tan Carlier.



From arnd at arndb.de  Tue Aug 21 11:38:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:38:12 +0000
Subject: [PATCH v2] ARM: io: avoid writeback addressing modes for __raw_
 accessors
In-Reply-To: <1345557059-6922-1-git-send-email-will.deacon@arm.com>
References: <1345557059-6922-1-git-send-email-will.deacon@arm.com>
Message-ID: <201208211538.13113.arnd@arndb.de>

On Tuesday 21 August 2012, Will Deacon wrote:
> 
> Data aborts taken to hyp mode do not provide a valid instruction
> syndrome field in the HSR if the faulting instruction is a memory
> access using a writeback addressing mode.
> 
> For hypervisors emulating MMIO accesses to virtual peripherals, taking
> such an exception requires disassembling the faulting instruction in
> order to determine the behaviour of the access. Since this requires
> manually walking the two stages of translation, the world must be
> stopped to prevent races against page aging in the guest, where the
> first-stage translation is invalidated after the hypervisor has
> translated to an IPA and the physical page is reused for something else.
> 
> This patch avoids taking this heavy performance penalty when running
> Linux as a guest by ensuring that our I/O accessors do not make use of
> writeback addressing modes.
> 
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Reviewed-by: Nicolas Pitre <nico at linaro.org>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From matthew.leach at arm.com  Tue Aug 21 11:48:14 2012
From: matthew.leach at arm.com (Matthew Leach)
Date: Tue, 21 Aug 2012 16:48:14 +0100
Subject: [PATCH v2] serial: pl011: honour serial aliases in device tree
Message-ID: <1345564094-16565-1-git-send-email-matthew.leach@arm.com>

If the order of UART nodes is changed in the device tree, then tty dev
devices are attached to different serial ports causing the console to
be directed to a different physical serial port. The "serial" aliases
in the device tree should prevent this.

This patch ensures that the UART driver creates tty devices that
honour these aliases if a device tree is present.

Acked-by: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Matthew Leach <matthew.leach at arm.com>
---
v2: use IS_ENABLED instead of ifdefs

 drivers/tty/serial/amba-pl011.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d3553b5..33c90f6 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,8 @@
 #include <linux/scatterlist.h>
 #include <linux/delay.h>
 #include <linux/types.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/sizes.h>
 
@@ -1869,6 +1871,38 @@ static struct uart_driver amba_reg = {
 	.cons			= AMBA_CONSOLE,
 };
 
+static int pl011_probe_dt_alias(int index, struct device *dev)
+{
+	struct device_node *np;
+	static bool seen_dev_with_alias = false;
+	static bool seen_dev_without_alias = false;
+	int ret = index;
+
+	if (!IS_ENABLED(CONFIG_OF))
+		return index;
+
+	np = dev->of_node;
+	if (!np)
+		return ret;
+
+	ret = of_alias_get_id(np, "serial");
+	if (IS_ERR_VALUE(ret)) {
+		seen_dev_without_alias = true;
+		ret = index;
+	} else {
+		seen_dev_with_alias = true;
+		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
+			dev_warn(dev, "requested serial port %d  not available.\n", ret);
+			ret = index;
+		}
+	}
+
+	if (seen_dev_with_alias && seen_dev_without_alias)
+		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
+
+	return ret;
+}
+
 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 {
 	struct uart_amba_port *uap;
@@ -1891,6 +1925,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto out;
 	}
 
+	i = pl011_probe_dt_alias(i, &dev->dev);
+
 	base = ioremap(dev->res.start, resource_size(&dev->res));
 	if (!base) {
 		ret = -ENOMEM;
-- 
1.7.0.4



From swarren at wwwdotorg.org  Tue Aug 21 11:48:21 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 Aug 2012 09:48:21 -0600
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <1345547850-29761-2-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
Message-ID: <5033ADC5.4030002@wwwdotorg.org>

On 08/21/2012 05:17 AM, AnilKumar Ch wrote:
> Add device tree data for tps65910 regulator by adding all tps65910
> regulator nodes. Regulator is initialized based on compatiable
> name provided in tps65910 DT file.
> 
> All tps65910 PMIC regulator device tree nodes are placed in a
> seperate device tree include file (tps65910.dtsi). This patch
> was tested on AM335x-EVM.

This .dtsi file adds a node for every single regulator within the
TPS65910, which in turn means that of_regulator_match() will find a node
for every regulator, and in turn every regulator will be registered. On
some boards, not all of those regulators will be used, and hence we
don't want all of them to be registered.

If we backport the /delete-node/ feature I implemented, perhaps we could
solve that; see:

http://comments.gmane.org/gmane.linux.drivers.devicetree/19170

> diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi

I wonder if there shouldn't be some better common location for .dtsi
files that are ancilliary chips, rather than ARM-specific?

> +&tps {
> +	compatible = "ti,tps65910";

Perhaps this file should expect some more unique label than just "tps".
Many boards have many power-related chips, all with model names that
start with "tps"; I foresee conflict here.

If dtc allowed /include/ inside a node rather than just at the
top-level, that might solve this. Or, #defines to the board .dts could
define the label name, and the .dtsi reference that label name.


From nicolas.ferre at atmel.com  Tue Aug 21 12:04:22 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 Aug 2012 18:04:22 +0200
Subject: [PATCH 1/5] i2c: at91: add new fixes for some TWI ip versions
In-Reply-To: <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5033B186.5010601@atmel.com>

On 08/21/2012 04:29 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> The at91sam9261 TWI ip version requires also some fixes. The id_entry
> field from the platform device structure has been replaced by the use
> of cpu_is_xxx function to determine when to use these fixes.

No, for this one. The current tendency is to remove the use of
cpu_is_xxx() functions.

So yes, you will have to keep the use of struct platform_device_id in
this driver and extend it with the device tree information.

> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
>  arch/arm/mach-at91/at91rm9200_devices.c |  9 -------
>  drivers/i2c/busses/i2c-at91.c           | 42 +++++++++++++++++++--------------
>  2 files changed, 24 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
> index 2b9b493..e6b7d05 100644
> --- a/arch/arm/mach-at91/at91rm9200_devices.c
> +++ b/arch/arm/mach-at91/at91rm9200_devices.c
> @@ -494,18 +494,9 @@ static struct resource twi_resources[] = {
>  	},
>  };
>  
> -static const struct platform_device_id twi_id = {
> -	/*
> -	 * driver_data is "1" for hardware with ckdiv upper limit == 5
> -	 * (AT91RM9200 erratum 22), "0" for twi modules without this bug
> -	 */
> -	.driver_data	= 1,
> -};
> -
>  static struct platform_device at91rm9200_twi_device = {
>  	.name		= "at91_i2c",
>  	.id		= -1,
> -	.id_entry	= &twi_id,
>  	.resource	= twi_resources,
>  	.num_resources	= ARRAY_SIZE(twi_resources),
>  };
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index b1cb780..4599522 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -27,6 +27,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
>  
> +#include <mach/cpu.h>
> +
>  #define TWI_CLK_HZ		100000			/* max 400 Kbits/s */
>  #define AT91_I2C_TIMEOUT	msecs_to_jiffies(100)	/* transfer timeout */
>  
> @@ -72,7 +74,6 @@ struct at91_twi_dev {
>  	int			irq;
>  	unsigned		transfer_status;
>  	struct i2c_adapter	adapter;
> -	bool			is_rm9200;
>  	unsigned		twi_cwgr_reg;
>  };
>  
> @@ -111,20 +112,28 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
>   */
>  static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
>  {
> -	const int offset = dev->is_rm9200 ? 3 : 4;
> -	const int div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> -						 2 * twi_clk) - offset);
> -	int ckdiv = fls(div >> 8);
> -	int cdiv = div >> ckdiv;
> -
> -	if (dev->is_rm9200 && (ckdiv > 5)) {
> -		dev_warn(dev->dev, "AT91RM9200 erratum 22: using ckdiv = 5.\n");
> -		ckdiv = 5;
> -		cdiv = 255;
> -	} else if (ckdiv > 7) {
> -		dev_warn(dev->dev, "%d exceeds 3 bits for ckdiv, limiting.\n",
> -			 ckdiv);
> -		ckdiv = 7;
> +	int offset, div, max_ckdiv, ckdiv, cdiv;
> +
> +	if (cpu_is_at91rm9200()) {
> +		offset = 3;
> +		max_ckdiv = 5;
> +	} else if (cpu_is_at91sam9261()) {
> +		offset = 4;
> +		max_ckdiv = 5;
> +	} else {
> +		offset = 4;
> +		max_ckdiv = 7;
> +	}
> +
> +	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> +				       2 * twi_clk) - offset);
> +	ckdiv = fls(div >> 8);
> +	cdiv = div >> ckdiv;
> +
> +	if (ckdiv > max_ckdiv) {
> +		dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
> +			 ckdiv, max_ckdiv);
> +		ckdiv = max_ckdiv;
>  		cdiv = 255;
>  	}
>  
> @@ -331,9 +340,6 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
>  		goto err_release_region;
>  	}
>  
> -	if (pdev->id_entry && pdev->id_entry->driver_data == 1)
> -		dev->is_rm9200 = 1;
> -
>  	init_completion(&dev->cmd_complete);
>  
>  	dev->dev = &pdev->dev;
> 


-- 
Nicolas Ferre


From catalin.marinas at arm.com  Tue Aug 21 12:06:53 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 17:06:53 +0100
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <201208161237.53594.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151415.39570.arnd@arndb.de>
 <20120816102300.GG31784@mudshark.cambridge.arm.com>
 <201208161237.53594.arnd@arndb.de>
Message-ID: <20120821160653.GH12708@arm.com>

On Thu, Aug 16, 2012 at 01:37:53PM +0100, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Will Deacon wrote:
> > > This looks wrong: PER_LINUX/PER_LINUX32 decides over the output of the
> > > uname system call, while TIF_32BIT decides over the instruction set
> > > when returning to user space. You definitely should not set the personality
> > > to the value you pass from the elf loader. Instead, just do
> > > 
> > > #define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
> > > #defined COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
> > 
> > In this case, won't uname be incorrect (aarch64l) for aarch32 tasks (which
> > expect something like armv8l)?
> 
> No, the uname output is meant to tell you about the system, not the
> instruction set that you are using (you already know that in compiled
> code).

OK, so we assumed that compat tasks should get a uname as close as
possible to a 32-bit system, i.e. armv8l, for full compatibility. This
would allow us to run something like 32-bit Debian on an AArch64 kernel
without worrying about any scripts failing.

But I can see on x86 that it always reports x86_64 even if the task is
x86_32.

-- 
Catalin


From nicolas.ferre at atmel.com  Tue Aug 21 12:08:02 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 Aug 2012 18:08:02 +0200
Subject: [PATCH 2/5] i2c: at91: add dt support to i2c-at91
In-Reply-To: <1345559345-13988-3-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-3-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5033B262.2020900@atmel.com>

On 08/21/2012 04:29 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
>  .../devicetree/bindings/i2c/atmel-i2c.txt          | 29 +++++++++++++
>  drivers/i2c/busses/i2c-at91.c                      | 49 +++++++++++++++++-----
>  2 files changed, 68 insertions(+), 10 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/i2c/atmel-i2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
> new file mode 100644
> index 0000000..9e46289
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
> @@ -0,0 +1,29 @@
> +I2C for Atmel platforms
> +
> +Required properties :
> +- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c" or
> +     "atmel,at91sam9g20-i2c"
> +- reg: physical base address of the controller and length of memory mapped
> +     region.
> +- interrupts: interrupt number to the cpu.
> +- #address-cells = <1>;
> +- #size-cells = <0>;
> +
> +Optional properties:
> +- Child nodes conforming to i2c bus binding
> +
> +Examples :
> +
> +i2c0: i2c at fff84000 {
> +	compatible = "atmel,at91sam9g20-i2c";
> +	reg = <0xfff84000 0x100>;
> +	interrupts = <12 4>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	24c512 at 50 {
> +		compatible = "24c512";
> +		reg = <0x50>;
> +		pagesize = <128>;
> +	}
> +}
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index 4599522..1c86b24 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -24,6 +24,9 @@
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_i2c.h>
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
>  
> @@ -112,17 +115,27 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
>   */
>  static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
>  {
> -	int offset, div, max_ckdiv, ckdiv, cdiv;
> -
> -	if (cpu_is_at91rm9200()) {
> -		offset = 3;
> -		max_ckdiv = 5;
> -	} else if (cpu_is_at91sam9261()) {
> -		offset = 4;
> -		max_ckdiv = 5;
> +	int offset = 4, max_ckdiv = 7;
> +	int div, ckdiv, cdiv;
> +
> +	if (dev->dev->of_node) {
> +		if (of_device_is_compatible(dev->dev->of_node,
> +					    "atmel,at91rm9200-i2c")) {
> +			offset = 3;
> +			max_ckdiv = 5;
> +		} else if (of_device_is_compatible(dev->dev->of_node,
> +						   "atmel,at91sam9261-i2c")) {
> +			offset = 4;
> +			max_ckdiv = 5;
> +		}
>  	} else {
> -		offset = 4;
> -		max_ckdiv = 7;
> +		if (cpu_is_at91rm9200()) {
> +			offset = 3;
> +			max_ckdiv = 5;
> +		} else if (cpu_is_at91sam9261()) {

H?h? ;-) here also, you will have to review this part...

> +			offset = 4;
> +			max_ckdiv = 5;
> +		}
>  	}
>  
>  	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> @@ -379,6 +392,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
>  	dev->adapter.dev.parent = dev->dev;
>  	dev->adapter.nr = pdev->id;
>  	dev->adapter.timeout = AT91_I2C_TIMEOUT;
> +	dev->adapter.dev.of_node = pdev->dev.of_node;
>  
>  	rc = i2c_add_numbered_adapter(&dev->adapter);
>  	if (rc) {
> @@ -387,6 +401,8 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
>  		goto err_free_irq;
>  	}
>  
> +	of_i2c_register_devices(&dev->adapter);
> +
>  	dev_info(dev->dev, "AT91 i2c bus driver.\n");
>  	return 0;
>  
> @@ -454,12 +470,25 @@ static const struct dev_pm_ops at91_twi_pm = {
>  #define at91_twi_pm_ops NULL
>  #endif
>  
> +#ifdef CONFIG_OF
> +static const struct of_device_id at91_twi_dt_ids[] = {
> +	{ .compatible = "atmel,at91rm9200-i2c", },
> +	{ .compatible = "atmel,at91sam9260-i2c", },
> +	{ .compatible = "atmel,at91sam9261-i2c", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, at91_twi_dt_ids);
> +#else
> +#define at91_twi_dt_ids NULL
> +#endif
> +
>  static struct platform_driver at91_twi_driver = {
>  	.probe		= at91_twi_probe,
>  	.remove		= __devexit_p(at91_twi_remove),
>  	.driver		= {
>  		.name	= "at91_i2c",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = at91_twi_dt_ids,
>  		.pm	= at91_twi_pm_ops,
>  	},
>  };
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Tue Aug 21 12:08:39 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 Aug 2012 18:08:39 +0200
Subject: [PATCH 3/5] ARM: at91: add clocks for i2c DT entries
In-Reply-To: <1345559345-13988-4-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-4-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5033B287.8080008@atmel.com>

On 08/21/2012 04:29 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/mach-at91/at91sam9260.c | 1 +
>  arch/arm/mach-at91/at91sam9263.c | 1 +
>  arch/arm/mach-at91/at91sam9g45.c | 2 ++
>  arch/arm/mach-at91/at91sam9n12.c | 2 ++
>  arch/arm/mach-at91/at91sam9x5.c  | 3 +++
>  5 files changed, 9 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 2e56321..f3fdca7 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -227,6 +227,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
>  	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
>  	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
>  	/* fake hclk clock */
>  	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
>  	CLKDEV_CON_ID("pioA", &pioA_clk),
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 71305fa..15458ad 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -210,6 +210,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
>  	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
>  	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
>  };
>  
>  static struct clk_lookup usart_clocks_lookups[] = {
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 2944fc7..dcc4e3c 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -244,6 +244,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
>  	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
>  	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
>  	/* fake hclk clock */
>  	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
>  	CLKDEV_CON_ID("pioA", &pioA_clk),
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index 0849466..732d3d3 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
>  	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
>  	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
>  	CLKDEV_CON_ID("pioA", &pioAB_clk),
>  	CLKDEV_CON_ID("pioB", &pioAB_clk),
>  	CLKDEV_CON_ID("pioC", &pioCD_clk),
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 1b144b4..744ffc2 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -231,6 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
>  	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
>  	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
>  	CLKDEV_CON_ID("pioA", &pioAB_clk),
>  	CLKDEV_CON_ID("pioB", &pioAB_clk),
>  	CLKDEV_CON_ID("pioC", &pioCD_clk),
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Tue Aug 21 12:10:56 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 Aug 2012 18:10:56 +0200
Subject: [PATCH 4/5] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <1345559345-13988-5-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-5-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5033B310.2020904@atmel.com>

On 08/21/2012 04:29 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Add twi nodes for atmel SOCs and remove i2c-gpio ones.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Yes, we will move to it once people test it a little bit...

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/boot/dts/at91sam9260.dtsi | 23 ++++++-------
>  arch/arm/boot/dts/at91sam9263.dtsi | 23 ++++++-------
>  arch/arm/boot/dts/at91sam9g45.dtsi | 33 +++++++++++-------
>  arch/arm/boot/dts/at91sam9n12.dtsi | 33 +++++++++++-------
>  arch/arm/boot/dts/at91sam9x5.dtsi  | 69 +++++++++++++++++---------------------
>  5 files changed, 90 insertions(+), 91 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> index f449efc..0ab7a3c 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -28,6 +28,7 @@
>  		gpio2 = &pioC;
>  		tcb0 = &tcb0;
>  		tcb1 = &tcb1;
> +		i2c0 = &i2c0;
>  	};
>  	cpus {
>  		cpu at 0 {
> @@ -198,6 +199,15 @@
>  				status = "disabled";
>  			};
>  
> +			i2c0: i2c at fffac000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xfffac000 0x100>;
> +				interrupts = <11 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
>  			adc0: adc at fffe0000 {
>  				compatible = "atmel,at91sam9260-adc";
>  				reg = <0xfffe0000 0x100>;
> @@ -257,17 +267,4 @@
>  			status = "disabled";
>  		};
>  	};
> -
> -	i2c at 0 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioA 23 0 /* sda */
> -			 &pioA 24 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
>  };
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> index 0209913..efb86dd 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -24,6 +24,7 @@
>  		gpio3 = &pioD;
>  		gpio4 = &pioE;
>  		tcb0 = &tcb0;
> +		i2c0 = &i2c0;
>  	};
>  	cpus {
>  		cpu at 0 {
> @@ -179,6 +180,15 @@
>  				interrupts = <24 4>;
>  				status = "disabled";
>  			};
> +
> +			i2c0: i2c at fff88000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xfff88000 0x100>;
> +				interrupts = <13 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> @@ -204,17 +214,4 @@
>  			status = "disabled";
>  		};
>  	};
> -
> -	i2c at 0 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioB 4 0 /* sda */
> -			 &pioB 5 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
>  };
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index 7dbccaf..8dd3ff8 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -29,6 +29,8 @@
>  		gpio4 = &pioE;
>  		tcb0 = &tcb0;
>  		tcb1 = &tcb1;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
>  	};
>  	cpus {
>  		cpu at 0 {
> @@ -200,6 +202,24 @@
>  				status = "disabled";
>  			};
>  
> +			i2c0: i2c at fff84000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xfff84000 0x100>;
> +				interrupts = <12 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c at fff88000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xfff88000 0x100>;
> +				interrupts = <13 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
>  			adc0: adc at fffb0000 {
>  				compatible = "atmel,at91sam9260-adc";
>  				reg = <0xfffb0000 0x100>;
> @@ -268,17 +288,4 @@
>  			status = "disabled";
>  		};
>  	};
> -
> -	i2c at 0 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioA 20 0 /* sda */
> -			 &pioA 21 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
>  };
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index cb84de7..8a1969d 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -26,6 +26,8 @@
>  		gpio3 = &pioD;
>  		tcb0 = &tcb0;
>  		tcb1 = &tcb1;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
>  	};
>  	cpus {
>  		cpu at 0 {
> @@ -178,6 +180,24 @@
>  				atmel,use-dma-tx;
>  				status = "disabled";
>  			};
> +
> +			i2c0: i2c at f8010000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xf8010000 0x100>;
> +				interrupts = <9 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c at f8014000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xf8014000 0x100>;
> +				interrupts = <10 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> @@ -205,17 +225,4 @@
>  			status = "disabled";
>  		};
>  	};
> -
> -	i2c at 0 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioA 30 0 /* sda */
> -			 &pioA 31 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
>  };
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 6b3ef43..ec56eaf 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -27,6 +27,9 @@
>  		gpio3 = &pioD;
>  		tcb0 = &tcb0;
>  		tcb1 = &tcb1;
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
>  	};
>  	cpus {
>  		cpu at 0 {
> @@ -191,6 +194,33 @@
>  				status = "disabled";
>  			};
>  
> +			i2c0: i2c at f8010000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xf8010000 0x100>;
> +				interrupts = <9 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c at f8014000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xf8014000 0x100>;
> +				interrupts = <10 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c at f8018000 {
> +				compatible = "atmel,at91sam9260-i2c";
> +				reg = <0xf8018000 0x100>;
> +				interrupts = <11 4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
>  			adc0: adc at f804c000 {
>  				compatible = "atmel,at91sam9260-adc";
>  				reg = <0xf804c000 0x100>;
> @@ -259,43 +289,4 @@
>  			status = "disabled";
>  		};
>  	};
> -
> -	i2c at 0 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioA 30 0 /* sda */
> -			 &pioA 31 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
> -
> -	i2c at 1 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioC 0 0 /* sda */
> -			 &pioC 1 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
> -
> -	i2c at 2 {
> -		compatible = "i2c-gpio";
> -		gpios = <&pioB 4 0 /* sda */
> -			 &pioB 5 0 /* scl */
> -			>;
> -		i2c-gpio,sda-open-drain;
> -		i2c-gpio,scl-open-drain;
> -		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
>  };
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Tue Aug 21 12:13:31 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 21 Aug 2012 18:13:31 +0200
Subject: [PATCH 5/5] ARM: dts: add twi nodes for atmel boards
In-Reply-To: <1345559520-14074-1-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559520-14074-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5033B3AB.8060507@atmel.com>

On 08/21/2012 04:32 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Use the atmel twi instead of gpio for i2c stuff.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Seems good. Maybe we will have to test wm8731 a little bit more.

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/boot/dts/at91sam9263ek.dts         | 20 ++++++++++----------
>  arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 28 ++++++++++++++--------------
>  arch/arm/boot/dts/at91sam9g25ek.dts         | 12 ++++++++++++
>  arch/arm/boot/dts/at91sam9m10g45ek.dts      | 14 ++++++++++++++
>  arch/arm/boot/dts/at91sam9n12ek.dts         |  8 ++++++++
>  5 files changed, 58 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
> index f86ac4b..772ab75 100644
> --- a/arch/arm/boot/dts/at91sam9263ek.dts
> +++ b/arch/arm/boot/dts/at91sam9263ek.dts
> @@ -50,6 +50,16 @@
>  				atmel,vbus-gpio = <&pioA 25 0>;
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at fff88000 {
> +				status = "okay";
> +
> +				24c512 at 50 {
> +					compatible = "24c512";
> +					reg = <0x50>;
> +					pagesize = <128>;
> +				};
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> @@ -143,14 +153,4 @@
>  			gpio-key,wakeup;
>  		};
>  	};
> -
> -	i2c at 0 {
> -		status = "okay";
> -
> -		24c512 at 50 {
> -			compatible = "24c512";
> -			reg = <0x50>;
> -			pagesize = <128>;
> -		};
> -	};
>  };
> diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
> index b06c0db..712106b 100644
> --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
> @@ -51,6 +51,20 @@
>  				atmel,vbus-gpio = <&pioC 5 0>;
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at fffac000 {
> +				status = "okay";
> +
> +				24c512 at 50 {
> +					compatible = "24c512";
> +					reg = <0x50>;
> +				};
> +
> +				wm8731 at 1b {
> +					compatible = "wm8731";
> +					reg = <0x1b>;
> +				};
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> @@ -106,20 +120,6 @@
>  		};
>  	};
>  
> -	i2c at 0 {
> -		status = "okay";
> -
> -		24c512 at 50 {
> -			compatible = "24c512";
> -			reg = <0x50>;
> -		};
> -
> -		wm8731 at 1b {
> -			compatible = "wm8731";
> -			reg = <0x1b>;
> -		};
> -	};
> -
>  	gpio_keys {
>  		compatible = "gpio-keys";
>  		#address-cells = <1>;
> diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
> index 7829a4d..3b0adbc 100644
> --- a/arch/arm/boot/dts/at91sam9g25ek.dts
> +++ b/arch/arm/boot/dts/at91sam9g25ek.dts
> @@ -32,6 +32,18 @@
>  				phy-mode = "rmii";
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at f8010000 {
> +				status = "okay";
> +			};
> +
> +			i2c1: i2c at f8014000 {
> +				status = "okay";
> +			};
> +
> +			i2c2: i2c at f8018000 {
> +				status = "okay";
> +			};
>  		};
>  
>  		usb0: ohci at 00600000 {
> diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> index a3633bd..4f94f23 100644
> --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
> +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> @@ -46,6 +46,20 @@
>  				phy-mode = "rmii";
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at fff84000 {
> +				status = "okay";
> +
> +				24c512 at 50 {
> +					compatible = "24c512";
> +					reg = <0x50>;
> +					pagesize = <128>;
> +				};
> +			};
> +			
> +			i2c1: i2c at fff88000 {
> +				status = "okay";
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
> index f4e43e3..912b2c2 100644
> --- a/arch/arm/boot/dts/at91sam9n12ek.dts
> +++ b/arch/arm/boot/dts/at91sam9n12ek.dts
> @@ -37,6 +37,14 @@
>  			dbgu: serial at fffff200 {
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at f8010000 {
> +				status = "okay";
> +			};
> +
> +			i2c1: i2c at f8014000 {
> +				status = "okay";
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {
> 


-- 
Nicolas Ferre


From ijc at hellion.org.uk  Tue Aug 21 12:28:25 2012
From: ijc at hellion.org.uk (Ian Campbell)
Date: Tue, 21 Aug 2012 17:28:25 +0100
Subject: dreamplug spi partitions
In-Reply-To: <20120816142005.GS22226@titan.lakedaemon.net>
References: <1344498477.11783.38.camel@dagon.hellion.org.uk>
 <20120816142005.GS22226@titan.lakedaemon.net>
Message-ID: <1345566505.6821.115.camel@zakaz.uk.xensource.com>

On Thu, 2012-08-16 at 10:20 -0400, Jason Cooper wrote:
> On Thu, Aug 09, 2012 at 08:47:57AM +0100, Ian Campbell wrote:
> > Hi all,
> > 
> > I've been using "fw_printenv" and "fw_setenv" from the u-boot-tools
> > package on my DreamPlug which work fine with this /etc/fw_env.config:
> >         # Configuration file for fw_(printenv/saveenv) utility.
> >         # Up to two entries are valid, in this case the redundant
> >         # environment sector is assumed present.
> >         # MTD device name       Device offset   Env. size       Flash sector size
> >         /dev/mtd1               0x00000000      0x00001000      0x00001000
> >         
> > This corresponds roughly, but not exactly, with:
> >         # cat /proc/mtd 
> >         dev:    size   erasesize  name
> >         mtd0: 00080000 00001000 "u-boot"
> >         mtd1: 00010000 00001000 "u-boot env"
> >         mtd2: 00010000 00001000 "dtb"
> > 
> > But notice how "Env. size" and mtd1's size don't match -- if I use
> > 0x10000 in fw_env.cfg then the tools don't work (checksums don't match).
> 
> I've always seen the u-boot environment set to 4k.

Right, so it seems like that is the right size for the kernel to report
then?

>   The kernel
> partitions came out of my head.  When I added support for the dreamplug
> to u-boot, I found out there was a bug in the factory supplied u-boot
> which only allowed it to see the first 1MB of the 2MB flash.  Also, the
> factory supplied kernel didn't even have support for the flash.
> 
> So, I fixed u-boot, and figured the extra 1MB was too small for a
> kernel, wasn't used by anybody else, and imho, the factory location of
> the environment didn't leave much room for new u-boots.
> 
> I decided to move the environment and make a place for the dtb.  As I
> didn't want to constrain either one, I split the extra space between the
> two.
> 
> Was that the best decision?  Well, no one yelled at me and I was new to
> the whole process, so that's how it went down.

;-)

I'm not saying the partitioning scheme is wrong or trying to criticize,
I just noticed that upstream u-boot and the kernel are inconsistent.

I haven't looked at the factory u-boot, I wouldn't be too torn up if it
matched neither of the other two though.

> As it is right now, if you configure your own u-boot to have, say
> 0x10000 bytes for the environment, you don't need to change your kernel
> to support it.  Just set the size and write it.
> 
> I'm open to suggestions and patches...

I think upstream u-boot and the kernel should match, but I'm not really
sure which one should be changed to match the other.

At this point I suppose it is generally easier for people to change
their kernel so that should be the one to change?

Ian.
-- 
Ian Campbell
Current Noise: Crowbar - Counting Daze

* gb notes that fdisk thinks his cdrom can store one terabyte
		-- Seen on #Linux



From broonie at opensource.wolfsonmicro.com  Tue Aug 21 12:38:05 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 17:38:05 +0100
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <5033ADC5.4030002@wwwdotorg.org>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
 <5033ADC5.4030002@wwwdotorg.org>
Message-ID: <20120821163805.GW7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 09:48:21AM -0600, Stephen Warren wrote:

> This .dtsi file adds a node for every single regulator within the
> TPS65910, which in turn means that of_regulator_match() will find a node
> for every regulator, and in turn every regulator will be registered. On
> some boards, not all of those regulators will be used, and hence we
> don't want all of them to be registered.

This isn't the general view for the regualtor API - we generally want
all regulators to be registered in order to allow us to see what's going
on with things even if we've not figured them out from software.

> If dtc allowed /include/ inside a node rather than just at the
> top-level, that might solve this. Or, #defines to the board .dts could
> define the label name, and the .dtsi reference that label name.

I do constantly wish that more of the people churning out DT stuff would
look at the tooling around it :/
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From dmitry.torokhov at gmail.com  Tue Aug 21 12:42:44 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Tue, 21 Aug 2012 09:42:44 -0700
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120821092328.GC26899@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
Message-ID: <20120821164244.GA4672@core.coreip.homeip.net>

On Tue, Aug 21, 2012 at 10:23:29AM +0100, Lee Jones wrote:
> On Tue, Aug 14, 2012 at 10:31:08AM +0200, Linus Walleij wrote:
> > On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> > 
> > > There was a plan to place ab8500_irq_get_virq() calls in each AB8500
> > > child device prior to requesting an IRQ, but as we're no longer using
> > > Device Tree to collect our IRQ numbers, it's actually better to allow
> > > the core to do this during device registration time. So the IRQ number
> > > we pull from its resource has already been converted to a virtual IRQ.
> > >
> > > CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
> > > CC: linux-input at vger.kernel.org
> > > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > 
> > This is looking good, I guess you need all patches to go in at the
> > same time so Dmitry's ACK is required.
> 
> Yep, just waiting for that now.

Sorry for the delay. Yes, this shoudl be fine, but since it is
essentially a revert of the original patch it should be pushed in as
such.

Thanks.

-- 
Dmitry


From shc_work at mail.ru  Tue Aug 21 12:59:33 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 21 Aug 2012 20:59:33 +0400
Subject: [PATCH 2/4] ARM: clps711x: Fix register definitions
In-Reply-To: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
References: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
Message-ID: <1345568375-28516-2-git-send-email-shc_work@mail.ru>

This patch contain some fixes:
- Fixes the address of register PORTE.
- Corrects name for DAIDR0 register.
- Removes unused definition for SYNCIO_CFGLEN.
- Fixes definition SYNCIO_FRMLEN.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/include/mach/clps711x.h |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 1dd806f..c82e21c 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -31,8 +31,8 @@
 #define PBDDR		(0x0041)
 #define PCDDR		(0x0042)
 #define PDDDR		(0x0043)
-#define PEDR		(0x0080)
-#define PEDDR		(0x00c0)
+#define PEDR		(0x0083)
+#define PEDDR		(0x00c3)
 #define SYSCON1		(0x0100)
 #define SYSFLG1		(0x0140)
 #define MEMCFG1		(0x0180)
@@ -77,7 +77,7 @@
 #define KBDEOI		(0x1700)
 
 #define DAIR		(0x2000)
-#define DAIR0		(0x2040)
+#define DAIDR0		(0x2040)
 #define DAIDR1		(0x2080)
 #define DAIDR2		(0x20c0)
 #define DAISR		(0x2100)
@@ -191,8 +191,7 @@
 #define UBRLCR_WRDLEN8		(3 << 17)
 #define UBRLCR_WRDLEN_MASK	(3 << 17)
 
-#define SYNCIO_FRMLEN(x)	(((x) & 0x3f) << 7)
-#define SYNCIO_CFGLEN(x)	((x) & 0x7f)
+#define SYNCIO_FRMLEN(x)	(((x) & 0x1f) << 8)
 #define SYNCIO_SMCKEN		(1 << 13)
 #define SYNCIO_TXFRMEN		(1 << 14)
 
-- 
1.7.8.6



From shc_work at mail.ru  Tue Aug 21 12:59:32 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 21 Aug 2012 20:59:32 +0400
Subject: [PATCH 1/4] ARM: clps711x: Remove board support for CEIVA
Message-ID: <1345568375-28516-1-git-send-email-shc_work@mail.ru>

The current kernel does not fit in the CEIVA ROM. Also, some functional
has already been removed due migrate from 2.6 to 3.0, and it seems that
no one uses this platform. So, remove support for this board and modules
specific only to this board.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/Kconfig                 |    6 -
 arch/arm/mach-clps711x/Makefile                |    1 -
 arch/arm/mach-clps711x/ceiva.c                 |   64 --
 arch/arm/mach-clps711x/include/mach/hardware.h |   48 --
 arch/arm/tools/mach-types                      |    1 -
 drivers/video/Kconfig                          |   12 -
 drivers/video/Makefile                         |    1 -
 drivers/video/epson1355fb.c                    |  749 ------------------------
 include/video/epson1355.h                      |   64 --
 9 files changed, 0 insertions(+), 946 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/ceiva.c
 delete mode 100644 drivers/video/epson1355fb.c
 delete mode 100644 include/video/epson1355.h

diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index ea036d6..e613536 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -16,12 +16,6 @@ config ARCH_CDB89712
 	  The board includes 2 serial ports, Ethernet, IRDA, and expansion
 	  headers.  It comes with 16 MB SDRAM and 8 MB flash ROM.
 
-config ARCH_CEIVA
-	bool "CEIVA"
-	help
-	  Say Y here if you intend to run this kernel on the Ceiva/Polaroid
-	  PhotoMax Digital Picture Frame.
-
 config ARCH_CLEP7312
 	bool "CLEP7312"
 	help
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f2f0256..aed9eb6 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -9,7 +9,6 @@ obj-m			:=
 obj-n			:=
 obj-			:=
 
-obj-$(CONFIG_ARCH_CEIVA) += ceiva.o
 obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o
 obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
deleted file mode 100644
index a70147e..0000000
--- a/arch/arm/mach-clps711x/ceiva.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/arch-ceiva.c
- *
- *  Copyright (C) 2002, Rob Scott <rscott at mtrob.fdns.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <linux/kernel.h>
-
-#include <mach/hardware.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/sizes.h>
-
-#include <asm/mach/map.h>
-
-#include "common.h"
-
-static struct map_desc ceiva_io_desc[] __initdata = {
- 	/* SED1355 controlled video RAM & registers */
- 	{
-		.virtual	= CEIVA_VIRT_SED1355,
-		.pfn		= __phys_to_pfn(CEIVA_PHYS_SED1355),
-		.length		= SZ_2M,
-		.type		= MT_DEVICE
-	}
-};
-
-
-static void __init ceiva_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(ceiva_io_desc, ARRAY_SIZE(ceiva_io_desc));
-}
-
-
-MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
-	/* Maintainer: Rob Scott */
-	.atag_offset	= 0x100,
-	.map_io		= ceiva_map_io,
-	.init_irq	= clps711x_init_irq,
-	.timer		= &clps711x_timer,
-	.restart	= clps711x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 13a64fc..8497775 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -116,7 +116,6 @@
 
 #endif /* CONFIG_ARCH_EDB7211 */
 
-
 /*
  * Relevant bits in port D, which controls power to the various parts of
  * the LCD on the EDB7211.
@@ -125,51 +124,4 @@
 #define EDB_PD2_LCDEN		(1<<2)
 #define EDB_PD3_LCDBL		(1<<3)
 
-
-#if defined (CONFIG_ARCH_CEIVA)
-
-/*
- * The two flash banks are wired to chip selects 0 and 1. This is the mapping
- * for them.
- *
- * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
- * in jumpered boot mode.
- */
-#define CEIVA_PHYS_FLASH1	CS0_PHYS_BASE	/* physical */
-#define CEIVA_PHYS_FLASH2	CS1_PHYS_BASE	/* physical */
-
-#define CEIVA_VIRT_FLASH1	(0xfa000000)	/* virtual */
-#define CEIVA_VIRT_FLASH2	(0xfb000000)	/* virtual */
-
-#define CEIVA_FLASH_SIZE        0x100000
-#define CEIVA_FLASH_WIDTH       2
-
-/*
- * SED1355 LCD controller
- */
-#define CEIVA_PHYS_SED1355	CS2_PHYS_BASE
-#define CEIVA_VIRT_SED1355	(0xfc000000)
-
-/*
- * Relevant bits in port D, which controls power to the various parts of
- * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
- */
-
-// Reset line to SED1355 (must be high to operate)
-#define CEIVA_PD1_LCDRST	(1<<1)
-// LCD panel enable (set to one, to enable LCD)
-#define CEIVA_PD4_LCDEN		(1<<4)
-// Backlight (set to one, to turn on backlight
-#define CEIVA_PD5_LCDBL		(1<<5)
-
-/*
- * Relevant bits in port B, which report the status of the buttons.
- */
-
-// White button
-#define CEIVA_PB4_WHT_BTN	(1<<4)
-// Black button
-#define CEIVA_PB0_BLK_BTN	(1<<0)
-#endif // #if defined (CONFIG_ARCH_CEIVA)
-
 #endif
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56..ae87c5e 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -66,7 +66,6 @@ iq80321			ARCH_IQ80321		IQ80321			169
 ks8695			ARCH_KS8695		KS8695			180
 karo			ARCH_KARO		KARO			190
 smdk2410		ARCH_SMDK2410		SMDK2410		193
-ceiva			ARCH_CEIVA		CEIVA			200
 voiceblue		MACH_VOICEBLUE		VOICEBLUE		218
 h5400			ARCH_H5400		H5400			220
 omap_innovator		MACH_OMAP_INNOVATOR	OMAP_INNOVATOR		234
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..8c17adb 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -979,18 +979,6 @@ config FB_PVR2
 	  (<file:drivers/video/pvr2fb.c>). Please see the file
 	  <file:Documentation/fb/pvr2fb.txt>.
 
-config FB_EPSON1355
-	bool "Epson 1355 framebuffer support"
-	depends on (FB = y) && ARCH_CEIVA
-	select FB_CFB_FILLRECT
-	select FB_CFB_COPYAREA
-	select FB_CFB_IMAGEBLIT
-	help
-	  Build in support for the SED1355 Epson Research Embedded RAMDAC
-	  LCD/CRT Controller (since redesignated as the S1D13505) as a
-	  framebuffer.  Product specs at
-	  <http://vdc.epson.com/>.
-
 config FB_S1D13XXX
 	tristate "Epson S1D13XXX framebuffer support"
 	depends on FB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ee8dafb..1940359 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -94,7 +94,6 @@ obj-$(CONFIG_FB_G364)             += g364fb.o
 obj-$(CONFIG_FB_EP93XX)		  += ep93xx-fb.o
 obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
 obj-$(CONFIG_FB_HIT)              += hitfb.o
-obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
 obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
 obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
 obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c
deleted file mode 100644
index 68b9b51..0000000
--- a/drivers/video/epson1355fb.c
+++ /dev/null
@@ -1,749 +0,0 @@
-/*
- * linux/drivers/video/epson1355fb.c -- Epson S1D13505 frame buffer for 2.5.
- *
- * Epson Research S1D13505 Embedded RAMDAC LCD/CRT Controller
- *   (previously known as SED1355)
- *
- * Cf. http://vdc.epson.com/
- *
- *
- * Copyright (C) Hewlett-Packard Company.  All rights reserved.
- *
- * Written by Christopher Hoover <ch at hpl.hp.com>
- *
- * Adapted from:
- *
- *  linux/drivers/video/skeletonfb.c
- *  Modified to new api Jan 2001 by James Simmons (jsimmons at infradead.org)
- *  Created 28 Dec 1997 by Geert Uytterhoeven
- *
- *  linux/drivers/video/epson1355fb.c (2.4 driver)
- *  Copyright (C) 2000 Philipp Rumpf <prumpf at tux.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- *
- *
- * Noteworthy Issues
- * -----------------
- *
- * This driver is complicated by the fact that this is a 16-bit chip
- * and, on at least one platform (ceiva), we can only do 16-bit reads
- * and writes to the framebuffer.  We hide this from user space
- * except in the case of mmap().
- *
- *
- * To Do
- * -----
- *
- * - Test 8-bit pseudocolor mode
- * - Allow setting bpp, virtual resolution
- * - Implement horizontal panning
- * - (maybe) Implement hardware cursor
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <linux/uaccess.h>
-
-#include <video/epson1355.h>
-
-struct epson1355_par {
-	unsigned long reg_addr;
-	u32 pseudo_palette[16];
-};
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_ARM)
-
-# ifdef CONFIG_ARCH_CEIVA
-#  include <mach/hardware.h>
-#  define EPSON1355FB_BASE_PHYS	(CEIVA_PHYS_SED1355)
-# endif
-
-static inline u8 epson1355_read_reg(struct epson1355_par *par, int index)
-{
-	return __raw_readb(par->reg_addr + index);
-}
-
-static inline void epson1355_write_reg(struct epson1355_par *par, u8 data, int index)
-{
-	__raw_writeb(data, par->reg_addr + index);
-}
-
-#else
-# error "no architecture-specific epson1355_{read,write}_reg"
-#endif
-
-#ifndef EPSON1355FB_BASE_PHYS
-# error  "EPSON1355FB_BASE_PHYS is not defined"
-#endif
-
-#define EPSON1355FB_REGS_OFS	(0)
-#define EPSON1355FB_REGS_PHYS	(EPSON1355FB_BASE_PHYS + EPSON1355FB_REGS_OFS)
-#define EPSON1355FB_REGS_LEN	(64)
-
-#define EPSON1355FB_FB_OFS	(0x00200000)
-#define EPSON1355FB_FB_PHYS	(EPSON1355FB_BASE_PHYS + EPSON1355FB_FB_OFS)
-#define EPSON1355FB_FB_LEN	(2 * 1024 * 1024)
-
-/* ------------------------------------------------------------------------- */
-
-static inline u16 epson1355_read_reg16(struct epson1355_par *par, int index)
-{
-	u8 lo = epson1355_read_reg(par, index);
-	u8 hi = epson1355_read_reg(par, index + 1);
-
-	return (hi << 8) | lo;
-}
-
-static inline void epson1355_write_reg16(struct epson1355_par *par, u16 data, int index)
-{
-	u8 lo = data & 0xff;
-	u8 hi = (data >> 8) & 0xff;
-
-	epson1355_write_reg(par, lo, index);
-	epson1355_write_reg(par, hi, index + 1);
-}
-
-static inline u32 epson1355_read_reg20(struct epson1355_par *par, int index)
-{
-	u8 b0 = epson1355_read_reg(par, index);
-	u8 b1 = epson1355_read_reg(par, index + 1);
-	u8 b2 = epson1355_read_reg(par, index + 2);
-
-	return (b2 & 0x0f) << 16 | (b1 << 8) | b0;
-}
-
-static inline void epson1355_write_reg20(struct epson1355_par *par, u32 data, int index)
-{
-	u8 b0 = data & 0xff;
-	u8 b1 = (data >> 8) & 0xff;
-	u8 b2 = (data >> 16) & 0x0f;
-
-	epson1355_write_reg(par, b0, index);
-	epson1355_write_reg(par, b1, index + 1);
-	epson1355_write_reg(par, b2, index + 2);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void set_lut(struct epson1355_par *par, u8 index, u8 r, u8 g, u8 b)
-{
-	epson1355_write_reg(par, index, REG_LUT_ADDR);
-	epson1355_write_reg(par, r, REG_LUT_DATA);
-	epson1355_write_reg(par, g, REG_LUT_DATA);
-	epson1355_write_reg(par, b, REG_LUT_DATA);
-}
-
-
-/**
- *  	epson1355fb_setcolreg - sets a color register.
- *      @regno: Which register in the CLUT we are programming
- *      @red: The red value which can be up to 16 bits wide
- *	@green: The green value which can be up to 16 bits wide
- *	@blue:  The blue value which can be up to 16 bits wide.
- *	@transp: If supported the alpha value which can be up to 16 bits wide.
- *      @info: frame buffer info structure
- *
- *	Returns negative errno on error, or zero on success.
- */
-static int epson1355fb_setcolreg(unsigned regno, unsigned r, unsigned g,
-				 unsigned b, unsigned transp,
-				 struct fb_info *info)
-{
-	struct epson1355_par *par = info->par;
-
-	if (info->var.grayscale)
-		r = g = b = (19595 * r + 38470 * g + 7471 * b) >> 16;
-
-	switch (info->fix.visual) {
-	case FB_VISUAL_TRUECOLOR:
-		if (regno >= 16)
-			return -EINVAL;
-
-		((u32 *) info->pseudo_palette)[regno] =
-		    (r & 0xf800) | (g & 0xfc00) >> 5 | (b & 0xf800) >> 11;
-
-		break;
-	case FB_VISUAL_PSEUDOCOLOR:
-		if (regno >= 256)
-			return -EINVAL;
-
-		set_lut(par, regno, r >> 8, g >> 8, b >> 8);
-
-		break;
-	default:
-		return -ENOSYS;
-	}
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/**
- *      epson1355fb_pan_display - Pans the display.
- *      @var: frame buffer variable screen structure
- *      @info: frame buffer structure that represents a single frame buffer
- *
- *	Pan (or wrap, depending on the `vmode' field) the display using the
- *  	`xoffset' and `yoffset' fields of the `var' structure.
- *  	If the values don't fit, return -EINVAL.
- *
- *      Returns negative errno on error, or zero on success.
- */
-static int epson1355fb_pan_display(struct fb_var_screeninfo *var,
-				   struct fb_info *info)
-{
-	struct epson1355_par *par = info->par;
-	u32 start;
-
-	if (var->xoffset != 0)	/* not yet ... */
-		return -EINVAL;
-
-	if (var->yoffset + info->var.yres > info->var.yres_virtual)
-		return -EINVAL;
-
-	start = (info->fix.line_length >> 1) * var->yoffset;
-
-	epson1355_write_reg20(par, start, REG_SCRN1_DISP_START_ADDR0);
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void lcd_enable(struct epson1355_par *par, int enable)
-{
-	u8 mode = epson1355_read_reg(par, REG_DISPLAY_MODE);
-
-	if (enable)
-		mode |= 1;
-	else
-		mode &= ~1;
-
-	epson1355_write_reg(par, mode, REG_DISPLAY_MODE);
-}
-
-#if defined(CONFIG_ARCH_CEIVA)
-static void backlight_enable(int enable)
-{
-	/* ### this should be protected by a spinlock ... */
-	u8 pddr = clps_readb(PDDR);
-	if (enable)
-		pddr |= (1 << 5);
-	else
-		pddr &= ~(1 << 5);
-	clps_writeb(pddr, PDDR);
-}
-#else
-static void backlight_enable(int enable)
-{
-}
-#endif
-
-
-/**
- *      epson1355fb_blank - blanks the display.
- *      @blank_mode: the blank mode we want.
- *      @info: frame buffer structure that represents a single frame buffer
- *
- *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
- *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
- *      video mode which doesn't support it. Implements VESA suspend
- *      and powerdown modes on hardware that supports disabling hsync/vsync:
- *      blank_mode == 2: suspend vsync
- *      blank_mode == 3: suspend hsync
- *      blank_mode == 4: powerdown
- *
- *      Returns negative errno on error, or zero on success.
- *
- */
-static int epson1355fb_blank(int blank_mode, struct fb_info *info)
-{
-	struct epson1355_par *par = info->par;
-
-	switch (blank_mode) {
-	case FB_BLANK_UNBLANK:
-	case FB_BLANK_NORMAL:
-		lcd_enable(par, 1);
-		backlight_enable(1);
-		break;
-	case FB_BLANK_VSYNC_SUSPEND:
-	case FB_BLANK_HSYNC_SUSPEND:
-		backlight_enable(0);
-		break;
-	case FB_BLANK_POWERDOWN:
-		backlight_enable(0);
-		lcd_enable(par, 0);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* let fbcon do a soft blank for us */
-	return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * We can't use the cfb generic routines, as we have to limit
- * ourselves to 16-bit or 8-bit loads and stores to this 16-bit
- * chip.
- */
-
-static inline void epson1355fb_fb_writel(unsigned long v, unsigned long *a)
-{
-	u16 *p = (u16 *) a;
-	u16 l = v & 0xffff;
-	u16 h = v >> 16;
-
-	fb_writew(l, p);
-	fb_writew(h, p + 1);
-}
-
-static inline unsigned long epson1355fb_fb_readl(const unsigned long *a)
-{
-	const u16 *p = (u16 *) a;
-	u16 l = fb_readw(p);
-	u16 h = fb_readw(p + 1);
-
-	return (h << 16) | l;
-}
-
-#define FB_READL epson1355fb_fb_readl
-#define FB_WRITEL epson1355fb_fb_writel
-
-/* ------------------------------------------------------------------------- */
-
-static inline unsigned long copy_from_user16(void *to, const void *from,
-					     unsigned long n)
-{
-	u16 *dst = (u16 *) to;
-	u16 *src = (u16 *) from;
-
-	if (!access_ok(VERIFY_READ, from, n))
-		return n;
-
-	while (n > 1) {
-		u16 v;
-		if (__get_user(v, src))
-			return n;
-
-		fb_writew(v, dst);
-
-		src++, dst++;
-		n -= 2;
-	}
-
-	if (n) {
-		u8 v;
-
-		if (__get_user(v, ((u8 *) src)))
-			return n;
-
-		fb_writeb(v, dst);
-	}
-	return 0;
-}
-
-static inline unsigned long copy_to_user16(void *to, const void *from,
-					   unsigned long n)
-{
-	u16 *dst = (u16 *) to;
-	u16 *src = (u16 *) from;
-
-	if (!access_ok(VERIFY_WRITE, to, n))
-		return n;
-
-	while (n > 1) {
-		u16 v = fb_readw(src);
-
-		if (__put_user(v, dst))
-			return n;
-
-		src++, dst++;
-		n -= 2;
-	}
-
-	if (n) {
-		u8 v = fb_readb(src);
-
-		if (__put_user(v, ((u8 *) dst)))
-			return n;
-	}
-	return 0;
-}
-
-
-static ssize_t
-epson1355fb_read(struct fb_info *info, char *buf, size_t count, loff_t * ppos)
-{
-	unsigned long p = *ppos;
-
-	if (p >= info->fix.smem_len)
-		return 0;
-	if (count >= info->fix.smem_len)
-		count = info->fix.smem_len;
-	if (count + p > info->fix.smem_len)
-		count = info->fix.smem_len - p;
-
-	if (count) {
-		char *base_addr;
-
-		base_addr = info->screen_base;
-		count -= copy_to_user16(buf, base_addr + p, count);
-		if (!count)
-			return -EFAULT;
-		*ppos += count;
-	}
-	return count;
-}
-
-static ssize_t
-epson1355fb_write(struct fb_info *info, const char *buf,
-		  size_t count, loff_t * ppos)
-{
-	unsigned long p = *ppos;
-	int err;
-
-	/* from fbmem.c except for our own copy_*_user */
-	if (p > info->fix.smem_len)
-		return -ENOSPC;
-	if (count >= info->fix.smem_len)
-		count = info->fix.smem_len;
-	err = 0;
-	if (count + p > info->fix.smem_len) {
-		count = info->fix.smem_len - p;
-		err = -ENOSPC;
-	}
-
-	if (count) {
-		char *base_addr;
-
-		base_addr = info->screen_base;
-		count -= copy_from_user16(base_addr + p, buf, count);
-		*ppos += count;
-		err = -EFAULT;
-	}
-	if (count)
-		return count;
-	return err;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static struct fb_ops epson1355fb_fbops = {
-	.owner 		= THIS_MODULE,
-	.fb_setcolreg 	= epson1355fb_setcolreg,
-	.fb_pan_display = epson1355fb_pan_display,
-	.fb_blank 	= epson1355fb_blank,
-	.fb_fillrect 	= cfb_fillrect,
-	.fb_copyarea 	= cfb_copyarea,
-	.fb_imageblit 	= cfb_imageblit,
-	.fb_read 	= epson1355fb_read,
-	.fb_write 	= epson1355fb_write,
-};
-
-/* ------------------------------------------------------------------------- */
-
-static __init unsigned int get_fb_size(struct fb_info *info)
-{
-	unsigned int size = 2 * 1024 * 1024;
-	char *p = info->screen_base;
-
-	/* the 512k framebuffer is aliased at start + 0x80000 * n */
-	fb_writeb(1, p);
-	fb_writeb(0, p + 0x80000);
-	if (!fb_readb(p))
-		size = 512 * 1024;
-
-	fb_writeb(0, p);
-
-	return size;
-}
-
-static int epson1355_width_tab[2][4] __devinitdata =
-    { {4, 8, 16, -1}, {9, 12, 16, -1} };
-static int epson1355_bpp_tab[8] __devinitdata = { 1, 2, 4, 8, 15, 16 };
-
-static void __devinit fetch_hw_state(struct fb_info *info, struct epson1355_par *par)
-{
-	struct fb_var_screeninfo *var = &info->var;
-	struct fb_fix_screeninfo *fix = &info->fix;
-	u8 panel, display;
-	u16 offset;
-	u32 xres, yres;
-	u32 xres_virtual, yres_virtual;
-	int bpp, lcd_bpp;
-	int is_color, is_dual, is_tft;
-	int lcd_enabled, crt_enabled;
-
-	fix->type = FB_TYPE_PACKED_PIXELS;
-
-	display = epson1355_read_reg(par, REG_DISPLAY_MODE);
-	bpp = epson1355_bpp_tab[(display >> 2) & 7];
-
-	switch (bpp) {
-	case 8:
-		fix->visual = FB_VISUAL_PSEUDOCOLOR;
-		var->bits_per_pixel = 8;
-		var->red.offset = var->green.offset = var->blue.offset = 0;
-		var->red.length = var->green.length = var->blue.length = 8;
-		break;
-	case 16:
-		/* 5-6-5 RGB */
-		fix->visual = FB_VISUAL_TRUECOLOR;
-		var->bits_per_pixel = 16;
-		var->red.offset = 11;
-		var->red.length = 5;
-		var->green.offset = 5;
-		var->green.length = 6;
-		var->blue.offset = 0;
-		var->blue.length = 5;
-		break;
-	default:
-		BUG();
-	}
-	fb_alloc_cmap(&(info->cmap), 256, 0);
-
-	panel = epson1355_read_reg(par, REG_PANEL_TYPE);
-	is_color = (panel & 0x04) != 0;
-	is_dual = (panel & 0x02) != 0;
-	is_tft = (panel & 0x01) != 0;
-	crt_enabled = (display & 0x02) != 0;
-	lcd_enabled = (display & 0x01) != 0;
-	lcd_bpp = epson1355_width_tab[is_tft][(panel >> 4) & 3];
-
-	xres = (epson1355_read_reg(par, REG_HORZ_DISP_WIDTH) + 1) * 8;
-	yres = (epson1355_read_reg16(par, REG_VERT_DISP_HEIGHT0) + 1) *
-	    ((is_dual && !crt_enabled) ? 2 : 1);
-	offset = epson1355_read_reg16(par, REG_MEM_ADDR_OFFSET0) & 0x7ff;
-	xres_virtual = offset * 16 / bpp;
-	yres_virtual = fix->smem_len / (offset * 2);
-
-	var->xres = xres;
-	var->yres = yres;
-	var->xres_virtual = xres_virtual;
-	var->yres_virtual = yres_virtual;
-	var->xoffset = var->yoffset = 0;
-
-	fix->line_length = offset * 2;
-
-	fix->xpanstep = 0;	/* no pan yet */
-	fix->ypanstep = 1;
-	fix->ywrapstep = 0;
-	fix->accel = FB_ACCEL_NONE;
-
-	var->grayscale = !is_color;
-
-#ifdef DEBUG
-	printk(KERN_INFO
-	       "epson1355fb: xres=%d, yres=%d, "
-	       "is_color=%d, is_dual=%d, is_tft=%d\n",
-	       xres, yres, is_color, is_dual, is_tft);
-	printk(KERN_INFO
-	       "epson1355fb: bpp=%d, lcd_bpp=%d, "
-	       "crt_enabled=%d, lcd_enabled=%d\n",
-	       bpp, lcd_bpp, crt_enabled, lcd_enabled);
-#endif
-}
-
-
-static void clearfb16(struct fb_info *info)
-{
-	u16 *dst = (u16 *) info->screen_base;
-	unsigned long n = info->fix.smem_len;
-
-	while (n > 1) {
-		fb_writew(0, dst);
-		dst++, n -= 2;
-	}
-
-	if (n)
-		fb_writeb(0, dst);
-}
-
-static int epson1355fb_remove(struct platform_device *dev)
-{
-	struct fb_info *info = platform_get_drvdata(dev);
-	struct epson1355_par *par = info->par;
-
-	backlight_enable(0);
-	if (par) {
-		lcd_enable(par, 0);
-		if (par && par->reg_addr)
-			iounmap((void *) par->reg_addr);
-	}
-
-	if (info) {
-		fb_dealloc_cmap(&info->cmap);
-		if (info->screen_base)
-			iounmap(info->screen_base);
-		framebuffer_release(info);
-	}
-	release_mem_region(EPSON1355FB_FB_PHYS, EPSON1355FB_FB_LEN);
-	release_mem_region(EPSON1355FB_REGS_PHYS, EPSON1355FB_REGS_LEN);
-	return 0;
-}
-
-static int __devinit epson1355fb_probe(struct platform_device *dev)
-{
-	struct epson1355_par *default_par;
-	struct fb_info *info;
-	u8 revision;
-	int rc = 0;
-
-	if (!request_mem_region(EPSON1355FB_REGS_PHYS, EPSON1355FB_REGS_LEN, "S1D13505 registers")) {
-		printk(KERN_ERR "epson1355fb: unable to reserve "
-		       "registers at 0x%0x\n", EPSON1355FB_REGS_PHYS);
-		rc = -EBUSY;
-		goto bail;
-	}
-
-	if (!request_mem_region(EPSON1355FB_FB_PHYS, EPSON1355FB_FB_LEN,
-				"S1D13505 framebuffer")) {
-		printk(KERN_ERR "epson1355fb: unable to reserve "
-		       "framebuffer at 0x%0x\n", EPSON1355FB_FB_PHYS);
-		rc = -EBUSY;
-		goto bail;
-	}
-
-	info = framebuffer_alloc(sizeof(struct epson1355_par), &dev->dev);
-	if (!info) {
-		rc = -ENOMEM;
-		goto bail;
-	}
-
-	default_par = info->par;
-	default_par->reg_addr = (unsigned long) ioremap(EPSON1355FB_REGS_PHYS, EPSON1355FB_REGS_LEN);
-	if (!default_par->reg_addr) {
-		printk(KERN_ERR "epson1355fb: unable to map registers\n");
-		rc = -ENOMEM;
-		goto bail;
-	}
-	info->pseudo_palette = default_par->pseudo_palette;
-
-	info->screen_base = ioremap(EPSON1355FB_FB_PHYS, EPSON1355FB_FB_LEN);
-	if (!info->screen_base) {
-		printk(KERN_ERR "epson1355fb: unable to map framebuffer\n");
-		rc = -ENOMEM;
-		goto bail;
-	}
-
-	revision = epson1355_read_reg(default_par, REG_REVISION_CODE);
-	if ((revision >> 2) != 3) {
-		printk(KERN_INFO "epson1355fb: epson1355 not found\n");
-		rc = -ENODEV;
-		goto bail;
-	}
-
-	info->fix.mmio_start = EPSON1355FB_REGS_PHYS;
-	info->fix.mmio_len = EPSON1355FB_REGS_LEN;
-	info->fix.smem_start = EPSON1355FB_FB_PHYS;
-	info->fix.smem_len = get_fb_size(info);
-
-	printk(KERN_INFO "epson1355fb: regs mapped at 0x%lx, fb %d KiB mapped at 0x%p\n",
-	       default_par->reg_addr, info->fix.smem_len / 1024, info->screen_base);
-
-	strcpy(info->fix.id, "S1D13505");
-	info->par = default_par;
-	info->fbops = &epson1355fb_fbops;
-	info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
-
-	/* we expect the boot loader to have initialized the chip
-	   with appropriate parameters from which we can determinte
-	   the flavor of lcd panel attached */
-	fetch_hw_state(info, default_par);
-
-	/* turn this puppy on ... */
-	clearfb16(info);
-	backlight_enable(1);
-	lcd_enable(default_par, 1);
-
-	if (register_framebuffer(info) < 0) {
-		rc = -EINVAL;
-		goto bail;
-	}
-	/*
-	 * Our driver data.
-	 */
-	platform_set_drvdata(dev, info);
-
-	printk(KERN_INFO "fb%d: %s frame buffer device\n",
-	       info->node, info->fix.id);
-
-	return 0;
-
-      bail:
-	epson1355fb_remove(dev);
-	return rc;
-}
-
-static struct platform_driver epson1355fb_driver = {
-	.probe	= epson1355fb_probe,
-	.remove	= epson1355fb_remove,
-	.driver	= {
-		.name	= "epson1355fb",
-	},
-};
-
-static struct platform_device *epson1355fb_device;
-
-int __init epson1355fb_init(void)
-{
-	int ret = 0;
-
-	if (fb_get_options("epson1355fb", NULL))
-		return -ENODEV;
-
-	ret = platform_driver_register(&epson1355fb_driver);
-
-	if (!ret) {
-		epson1355fb_device = platform_device_alloc("epson1355fb", 0);
-
-		if (epson1355fb_device)
-			ret = platform_device_add(epson1355fb_device);
-		else
-			ret = -ENOMEM;
-
-		if (ret) {
-			platform_device_put(epson1355fb_device);
-			platform_driver_unregister(&epson1355fb_driver);
-		}
-	}
-
-	return ret;
-}
-
-module_init(epson1355fb_init);
-	
-#ifdef MODULE
-static void __exit epson1355fb_exit(void)
-{
-	platform_device_unregister(epson1355fb_device);
-	platform_driver_unregister(&epson1355fb_driver);
-}
-
-/* ------------------------------------------------------------------------- */
-
-module_exit(epson1355fb_exit);
-#endif
-
-MODULE_AUTHOR("Christopher Hoover <ch at hpl.hp.com>");
-MODULE_DESCRIPTION("Framebuffer driver for Epson S1D13505");
-MODULE_LICENSE("GPL");
diff --git a/include/video/epson1355.h b/include/video/epson1355.h
deleted file mode 100644
index 9759f29..0000000
--- a/include/video/epson1355.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * include/video/epson13xx.h -- Epson 13xx frame buffer
- *
- * Copyright (C) Hewlett-Packard Company.  All rights reserved.
- *
- * Written by Christopher Hoover <ch at hpl.hp.com>
- *
- */
-
-#ifndef _EPSON13XX_H_
-#define _EPSON13XX_H_
-
-#define REG_REVISION_CODE              0x00
-#define REG_MEMORY_CONFIG              0x01
-#define REG_PANEL_TYPE                 0x02
-#define REG_MOD_RATE                   0x03
-#define REG_HORZ_DISP_WIDTH            0x04
-#define REG_HORZ_NONDISP_PERIOD        0x05
-#define REG_HRTC_START_POSITION        0x06
-#define REG_HRTC_PULSE_WIDTH           0x07
-#define REG_VERT_DISP_HEIGHT0          0x08
-#define REG_VERT_DISP_HEIGHT1          0x09
-#define REG_VERT_NONDISP_PERIOD        0x0A
-#define REG_VRTC_START_POSITION        0x0B
-#define REG_VRTC_PULSE_WIDTH           0x0C
-#define REG_DISPLAY_MODE               0x0D
-#define REG_SCRN1_LINE_COMPARE0        0x0E
-#define REG_SCRN1_LINE_COMPARE1        0x0F
-#define REG_SCRN1_DISP_START_ADDR0     0x10
-#define REG_SCRN1_DISP_START_ADDR1     0x11
-#define REG_SCRN1_DISP_START_ADDR2     0x12
-#define REG_SCRN2_DISP_START_ADDR0     0x13
-#define REG_SCRN2_DISP_START_ADDR1     0x14
-#define REG_SCRN2_DISP_START_ADDR2     0x15
-#define REG_MEM_ADDR_OFFSET0           0x16
-#define REG_MEM_ADDR_OFFSET1           0x17
-#define REG_PIXEL_PANNING              0x18
-#define REG_CLOCK_CONFIG               0x19
-#define REG_POWER_SAVE_CONFIG          0x1A
-#define REG_MISC                       0x1B
-#define REG_MD_CONFIG_READBACK0        0x1C
-#define REG_MD_CONFIG_READBACK1        0x1D
-#define REG_GPIO_CONFIG0               0x1E
-#define REG_GPIO_CONFIG1               0x1F
-#define REG_GPIO_CONTROL0              0x20
-#define REG_GPIO_CONTROL1              0x21
-#define REG_PERF_ENHANCEMENT0          0x22
-#define REG_PERF_ENHANCEMENT1          0x23
-#define REG_LUT_ADDR                   0x24
-#define REG_RESERVED_1                 0x25
-#define REG_LUT_DATA                   0x26
-#define REG_INK_CURSOR_CONTROL         0x27
-#define REG_CURSOR_X_POSITION0         0x28
-#define REG_CURSOR_X_POSITION1         0x29
-#define REG_CURSOR_Y_POSITION0         0x2A
-#define REG_CURSOR_Y_POSITION1         0x2B
-#define REG_INK_CURSOR_COLOR0_0        0x2C
-#define REG_INK_CURSOR_COLOR0_1        0x2D
-#define REG_INK_CURSOR_COLOR1_0        0x2E
-#define REG_INK_CURSOR_COLOR1_1        0x2F
-#define REG_INK_CURSOR_START_ADDR      0x30
-#define REG_ALTERNATE_FRM              0x31
-
-#endif
-- 
1.7.8.6



From shc_work at mail.ru  Tue Aug 21 12:59:34 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 21 Aug 2012 20:59:34 +0400
Subject: [PATCH 3/4] ARM: clps711x: Fix lowlevel debug-macro
In-Reply-To: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
References: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
Message-ID: <1345568375-28516-3-git-send-email-shc_work@mail.ru>

CTS signal can not be used for the port and tied to any logic state.
In this case we have an infinite loop waiting for the signal. For fix
this problem, checking CTS removed, waiting for the signal "busy" was
postponed after the byte write to the port.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/mach-clps711x/include/mach/debug-macro.S |    8 +-------
 1 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 118b3d9..cb3684f 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -28,17 +28,11 @@
 		.endm
 
 		.macro	waituart,rd,rx
-1001:		ldr	\rd, [\rx, #0x0140]	@ SYSFLGx
-		tst	\rd, #1 << 11		@ UBUSYx
-		bne	1001b
 		.endm
 
 		.macro	busyuart,rd,rx
-		tst	\rx, #0x1000		@ UART2 does not have CTS here
-		bne	1002f
 1001:		ldr	\rd, [\rx, #0x0140]	@ SYSFLGx
-		tst	\rd, #1 << 8		@ CTS
+		tst	\rd, #1 << 11		@ UBUSYx
 		bne	1001b
-1002:
 		.endm
 
-- 
1.7.8.6



From shc_work at mail.ru  Tue Aug 21 12:59:35 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 21 Aug 2012 20:59:35 +0400
Subject: [PATCH 4/4] ARM: clps711x: Added simple clock framework
In-Reply-To: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
References: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
Message-ID: <1345568375-28516-4-git-send-email-shc_work@mail.ru>

Modern CPUs from CLPS711X-line can operate at frequencies other than 73 MHz.
This patch adds simple clock framework for handling all possible CPU rates.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/Kconfig                            |    2 +
 arch/arm/mach-clps711x/common.c             |   89 ++++++++++++++++++++++-----
 arch/arm/mach-clps711x/include/mach/timex.h |   23 +-------
 3 files changed, 76 insertions(+), 38 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..2b23202 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -384,6 +384,8 @@ config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 	select CPU_ARM720T
 	select ARCH_USES_GETTIMEOFFSET
+	select COMMON_CLK
+	select CLKDEV_LOOKUP
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Cirrus Logic 711x/721x/731x based boards.
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293b..5f25ea3 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,24 +19,25 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/kernel.h>
-#include <linux/mm.h>
+#include <linux/io.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/sched.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 
 #include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
+#include <mach/hardware.h>
+
+static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
+		  *clk_tint, *clk_spi;
+static unsigned long latch;
+
 /*
  * This maps the generic CLPS711x registers
  */
@@ -166,8 +167,8 @@ void __init clps711x_init_irq(void)
 static unsigned long clps711x_gettimeoffset(void)
 {
 	unsigned long hwticks;
-	hwticks = LATCH - (clps_readl(TC2D) & 0xffff);	/* since last underflow */
-	return (hwticks * (tick_nsec / 1000)) / LATCH;
+	hwticks = latch - (clps_readl(TC2D) & 0xffff);
+	return (hwticks * (tick_nsec / 1000)) / latch;
 }
 
 /*
@@ -185,15 +186,71 @@ static struct irqaction clps711x_timer_irq = {
 	.handler	= p720t_timer_interrupt,
 };
 
+static void add_fixed_clk(struct clk *clk, const char *name, int rate)
+{
+	clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+	clk_register_clkdev(clk, name, NULL);
+}
+
 static void __init clps711x_timer_init(void)
 {
-	unsigned int syscon;
+	int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
+	u32 tmp;
+
+	osc = 3686400;
+	ext = 13000000;
+
+	tmp = clps_readl(PLLR) >> 24;
+	if (tmp)
+		pll = (osc * tmp) / 2;
+	else
+		pll = 73728000; /* Default value */
+
+	tmp = clps_readl(SYSFLG2);
+	if (tmp & SYSFLG2_CKMODE) {
+		cpu = ext;
+		bus = cpu;
+		spi = 135400;
+	} else {
+		cpu = pll;
+		if (cpu >= 36864000)
+			bus = cpu / 2;
+		else
+			bus = 36864000 / 2;
+		spi = cpu / 576;
+	}
+
+	uart = bus / 10;
+
+	if (tmp & SYSFLG2_CKMODE) {
+		tmp = clps_readl(SYSCON2);
+		if (tmp & SYSCON2_OSTB)
+			timh = ext / 26;
+		else
+			timh = 541440;
+	} else
+		timh = cpu / 144;
+
+	timl = timh / 256;
+
+	/* All clocks are fixed */
+	add_fixed_clk(clk_pll, "pll", pll);
+	add_fixed_clk(clk_bus, "bus", bus);
+	add_fixed_clk(clk_uart, "uart", uart);
+	add_fixed_clk(clk_timerl, "timer_lf", timl);
+	add_fixed_clk(clk_timerh, "timer_hf", timh);
+	add_fixed_clk(clk_tint, "tint", 64);
+	add_fixed_clk(clk_spi, "spi", spi);
+
+	pr_info("CPU frequency set at %i Hz.\n", cpu);
+
+	latch = (timh + HZ / 2) / HZ;
 
-	syscon = clps_readl(SYSCON1);
-	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
-	clps_writel(syscon, SYSCON1);
+	tmp = clps_readl(SYSCON1);
+	tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+	clps_writel(tmp, SYSCON1);
 
-	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+	clps_writel(latch - 1, TC2D);
 
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h
index ac8823c..de6fd19 100644
--- a/arch/arm/mach-clps711x/include/mach/timex.h
+++ b/arch/arm/mach-clps711x/include/mach/timex.h
@@ -1,23 +1,2 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/timex.h
- *
- *  Prospector 720T architecture timex specifications
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
+/* Bogus value */
 #define CLOCK_TICK_RATE 512000
-- 
1.7.8.6



From broonie at opensource.wolfsonmicro.com  Tue Aug 21 12:52:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 17:52:07 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821120243.GF26899@gmail.com>
References: <20120820121055.GA26991@opensource.wolfsonmicro.com>
 <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
 <20120821120243.GF26899@gmail.com>
Message-ID: <20120821165207.GX7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 01:02:46PM +0100, Lee Jones wrote:
> On Tue, Aug 21, 2012 at 12:03:29PM +0100, Mark Brown wrote:

> > > another way to get hold of the domain, because the only way to obtain
> > > it without having direct access is via a device node.

> > This doesn't actually hold.

> Okay, besides irq_find_host(struct device_node *np), how else can you fetch
> a domain from the irqdomain?

I'm not sure I can parse the above, sorry - I'm not sure I can
distinguish "domain" and "irqdomain".

> What have you done already? 

Implemented a patch for this which I've now tested a bit and will
probably post in the next hour or so.

> Why make suggestions if you're just going to do the work yourself?

I made the suggestion then later on realised that this was actively
going to break things I care about so I actually need it fixing.
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From lauraa at codeaurora.org  Tue Aug 21 13:23:52 2012
From: lauraa at codeaurora.org (Laura Abbott)
Date: Tue, 21 Aug 2012 10:23:52 -0700
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <50339AF6.1060601@codeaurora.org>
References: <50339AF6.1060601@codeaurora.org>
Message-ID: <5033C428.2050607@codeaurora.org>

On 8/21/2012 7:28 AM, Murali Nalajala wrote:
> Hi All,
> I am doing a below call in my driver to get the virtual address
> equivalent to physical address 0x0.
>
> pdata->v_addr = ioremap(pdata->p_addr, PAGE_SIZE); /* pdata->p_addr=0 */
>
> Above call returns me a valid virtual address i.e: 0xfa200000. After
> that when i try to access the address i am getting a kernel panic like
> below.

<snip>

> [ 0.161784] ioremap: pfn=0x0 phys=0x0 offset=0x0 size=0x1000
> [ 0.161813] ioremap: area da0fbdc0: phys_addr=0xc0100000 pfn=0xc0100
> size=0x1000
> [ 0.161838] ioremap: area da0fbe20: phys_addr=0xa8600000 pfn=0xa8600
> size=0x1000
> [ 0.161861] ioremap: area da0fbd80: phys_addr=0xc0000000 pfn=0xc0000
> size=0x1000
> [ 0.161886] ioremap: area da0fbda0: phys_addr=0xc0100000 pfn=0xc0100
> size=0x1000
> [ 0.161909] ioremap: area da0fbde0: phys_addr=0xa9200000 pfn=0xa9200
> size=0x1000
> [ 0.161933] ioremap: area da0fbe00: phys_addr=0xa9300000 pfn=0xa9300
> size=0x1000
> [ 0.161956] ioremap: area da0fbd40: phys_addr=0x0 pfn=0x0 size=0x100000
> [ 0.161979] ioremap: found: addr fa200000 => 0xfa200000 => 0xfa200000
> [ 0.161999] *** reset_vector = 0xfa200000
>
>
> Can someone know me what is wrong in ioremap call?
> Why i am not seeing a crash after i commented out the loop above?
>

Looks like you are hitting the empty section gap:

0xfa200000-0xfa300000 1048576 pmd_empty_section_gap+0x0/0x3c ioremap

pmd_empty_section_gap ends up with vm->phys_addr = 0x0 because it was 
never set. This section isn't actually mapped so when searching for the 
range in the static io map it finds this address and returns it but it 
isn't actually a valid address to return. Perhaps ioremap should not 
bother trying to re-use the static iomap if the address is zero and let 
pmd_empty_section_gap use 0x0 as a dummy value?



diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -228,7 +228,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned 
long pfn,
          */
         read_lock(&vmlist_lock);
         for (area = vmlist; area; area = area->next) {
-               if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
+               if (!size || !pfn || (sizeof(phys_addr_t) == 4 &&
+                   pfn >= 0x100000))
                         break;
                 if (!(area->flags & VM_ARM_STATIC_MAPPING))
                         continue;



>
> Thanks,
> Murali N
>

Thanks,
Laura

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From omar.luna at linaro.org  Tue Aug 21 13:48:16 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Tue, 21 Aug 2012 12:48:16 -0500
Subject: [PATCH 1/3] ARM: OMAP: hwmod: partially un-reset hwmods might not
 be properly enabled
In-Reply-To: <50324E84.6080407@ti.com>
References: <1342466485-1050-1-git-send-email-omar.luna@linaro.org>
 <1342466485-1050-2-git-send-email-omar.luna@linaro.org>
 <50324E84.6080407@ti.com>
Message-ID: <CALLhW=50Ro5T=u7KTObT6g7eF=835Ywj9sQ+z8kZ_+5U7U7fJA@mail.gmail.com>

On 20 August 2012 09:49, Benoit Cousson <b-cousson at ti.com> wrote:
> On 07/16/2012 09:21 PM, Omar Ramirez Luna wrote:
>> Some IP blocks might not be using/controlling more than one
>> reset line, this check loosens the restriction to fully use
>> hwmod framework for those drivers.
>>
>> E.g.: ipu has reset lines: mmu_cache, cpu0 and cpu1.
>> - cpu1 might not be used and hence (with previous check)
>>   won't be fully enabled by hwmod code.
>
> You mean that you might have some case where you need to enable the
> mmu_cache and cpu0 and thus deassert only the mmu/cpu0 while keeping the
> cpu1 under reset?

Looks like I didn't reply to this question.

Yes, initially cpu1 might not be used and kept under reset. Or even
the mmu can be taken out of reset and configured, and cpu0 after it,
creating a small window where one is taken out and the other is under
reset.

> So the any_hardreset is indeed not appropriate in that case.
>
> In fact, since the hardreset cannot be handled at all by the hwmod fmwk,
> I'm even wondering if we should take care of checking the state at all.
> But as Paul stated, if was done due to the lack of understanding about
> the diver usage, so maybe things will become clearer once we will have
> that code available.

I still think it can, in fact all the code I'm using comes from the
hwmod fmwk. _deassert_reset is almost the same as _enable, I left it
this way to avoid reintroducing the issues that caused reset code to
be stripped out from _enable path.

Regards,

Omar


From catalin.marinas at arm.com  Tue Aug 21 13:51:22 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 18:51:22 +0100
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <201208151422.16335.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-18-git-send-email-catalin.marinas@arm.com>
 <201208151422.16335.arnd@arndb.de>
Message-ID: <20120821175122.GI12708@arm.com>

On Wed, Aug 15, 2012 at 03:22:16PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +
> > +/* This matches struct stat64 in glibc2.1, hence the absolutely
> > + * insane amounts of padding around dev_t's.
> > + * Note: The kernel zero's the padded region because glibc might read them
> > + * in the hope that the kernel has stretched to using larger sizes.
> > + */
> > +struct stat64 {
> > +	compat_u64	st_dev;
> > +	unsigned char   __pad0[4];
> 
> The comment above struct stat64 is completely irrelevant here. I would instead
> explain why you need your own stat64 in the first place.

OK, I added a comment. It's only needed for compat.

> > +int kernel_execve(const char *filename,
> > +		  const char *const argv[],
> > +		  const char *const envp[])
> 
> Al Viro was recently talking about a generic implementation of execve.
> I can't find that now, but I think you should use that.

I've seen these but I'm waiting for the generic sys_execve and
kernel_execve to get into mainline before switch arch/arm64 to them.

> > +asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
> > +			 unsigned long prot, unsigned long flags,
> > +			 unsigned long fd, off_t off)
> > +{
> > +	if (offset_in_page(off) != 0)
> > +		return -EINVAL;
> > +
> > +	return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
> > +}
> 
> I think
> 
> #define sys_mmap sys_mmap_pgoff 

There are slightly different semantics with the last argument of
sys_mmap() which takes a byte offset. The sys_mmap_pgoff() function
takes the offset shifted by PAGE_SHIFT (which is the same as sys_mmap2).

Looking at the other architectures, it makes sense to use a generic
sys_mmap() implementation similar to the one above (or the ia-64, seems
to be the most complete).

-- 
Catalin


From swarren at wwwdotorg.org  Tue Aug 21 14:05:15 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 Aug 2012 12:05:15 -0600
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <20120821163805.GW7995@opensource.wolfsonmicro.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
 <5033ADC5.4030002@wwwdotorg.org>
 <20120821163805.GW7995@opensource.wolfsonmicro.com>
Message-ID: <5033CDDB.808@wwwdotorg.org>

On 08/21/2012 10:38 AM, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 09:48:21AM -0600, Stephen Warren wrote:
> 
>> This .dtsi file adds a node for every single regulator within
>> the TPS65910, which in turn means that of_regulator_match() will
>> find a node for every regulator, and in turn every regulator will
>> be registered. On some boards, not all of those regulators will
>> be used, and hence we don't want all of them to be registered.
> 
> This isn't the general view for the regualtor API - we generally
> want all regulators to be registered in order to allow us to see
> what's going on with things even if we've not figured them out from
> software.

Oh, I said the above specifically because when I added the LDO
configuration for the regulators that weren't used to the Tegra .dts
files, you told me to remove it, based on the comment I put in there
that they weren't used on the board.


From broonie at opensource.wolfsonmicro.com  Tue Aug 21 14:08:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 21 Aug 2012 19:08:47 +0100
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <5033CDDB.808@wwwdotorg.org>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
 <5033ADC5.4030002@wwwdotorg.org>
 <20120821163805.GW7995@opensource.wolfsonmicro.com>
 <5033CDDB.808@wwwdotorg.org>
Message-ID: <20120821180847.GC7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 12:05:15PM -0600, Stephen Warren wrote:
> On 08/21/2012 10:38 AM, Mark Brown wrote:

> > This isn't the general view for the regualtor API - we generally
> > want all regulators to be registered in order to allow us to see
> > what's going on with things even if we've not figured them out from
> > software.

> Oh, I said the above specifically because when I added the LDO
> configuration for the regulators that weren't used to the Tegra .dts
> files, you told me to remove it, based on the comment I put in there
> that they weren't used on the board.

The board shouldn't have to define the regulators, the regulator driver
really ought to be able to figure out that they're there by itself if
there's no configuration based purely on knowing which chip is there.
From that point of view it's OK for the chip .dtsi to have them (though
ideally the driver wouldn't *need* that either) which was what was
happening here.
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From geert at linux-m68k.org  Tue Aug 21 14:17:19 2012
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Tue, 21 Aug 2012 20:17:19 +0200
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <20120821160653.GH12708@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151415.39570.arnd@arndb.de>
 <20120816102300.GG31784@mudshark.cambridge.arm.com>
 <201208161237.53594.arnd@arndb.de> <20120821160653.GH12708@arm.com>
Message-ID: <CAMuHMdVEX0egzFETMJ=LA_PB+7Qc=Ph-7uxofVr__wOE-0cvLQ@mail.gmail.com>

On Tue, Aug 21, 2012 at 6:06 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> But I can see on x86 that it always reports x86_64 even if the task is
> x86_32.

Really?

$ uname -m
x86_64
$ linux32 uname -m
i686
$

On Ubuntu 2.6.32-42-generic

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds


From mporter at ti.com  Tue Aug 21 14:20:04 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 21 Aug 2012 14:20:04 -0400
Subject: [PATCH 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345153471-22757-2-git-send-email-mporter@ti.com>
References: <1345153471-22757-1-git-send-email-mporter@ti.com>
 <1345153471-22757-2-git-send-email-mporter@ti.com>
Message-ID: <20120821182004.GA32420@beef>

On Thu, Aug 16, 2012 at 05:44:29PM -0400, Matt Porter wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.

I got my hands on a AM18x WL12xx module so I could test MMC1 and this
exposed some bugs in the driver's handling of the second EDMA controller
case. DA850/OMAP-L138/AM1x have this second EDMA controller. I've
addressed this in v2 which will be posted shortly.

I'm expecting to receive a DM646x EVM RSN so I can cover testing that
part as well.

-Matt


From catalin.marinas at arm.com  Tue Aug 21 14:27:31 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 19:27:31 +0100
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <CAMuHMdVEX0egzFETMJ=LA_PB+7Qc=Ph-7uxofVr__wOE-0cvLQ@mail.gmail.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151415.39570.arnd@arndb.de>
 <20120816102300.GG31784@mudshark.cambridge.arm.com>
 <201208161237.53594.arnd@arndb.de> <20120821160653.GH12708@arm.com>
 <CAMuHMdVEX0egzFETMJ=LA_PB+7Qc=Ph-7uxofVr__wOE-0cvLQ@mail.gmail.com>
Message-ID: <20120821182731.GJ12708@arm.com>

On Tue, Aug 21, 2012 at 07:17:19PM +0100, Geert Uytterhoeven wrote:
> On Tue, Aug 21, 2012 at 6:06 PM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> > But I can see on x86 that it always reports x86_64 even if the task is
> > x86_32.
> 
> Really?
> 
> $ uname -m
> x86_64
> $ linux32 uname -m
> i686
> $

Well, you set the personality explicitly with linux32. What I tested was
with an x86_32 uname called directly (without linux32) and even though
the ELF was a 32-bit one, it was reporting x86_64. In this AArch64
patch, a compat task was automatically setting the linux32 personality
(which x86 does not do).

Arnd's point is that the ELF file should not affect the personality and
hence the uname value. This should only be done by an explicit call to
sys_personality().

-- 
Catalin


From mporter at ti.com  Tue Aug 21 14:43:06 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 21 Aug 2012 14:43:06 -0400
Subject: [PATCH v2 0/3] DaVinci DMA engine conversion
Message-ID: <1345574589-24757-1-git-send-email-mporter@ti.com>

Changes since v1:
	- Add virt-dma support. Better error checks
	  and simplified descriptor handling.
	- Fix support for multiple EDMA controllers
	  Tested on AM18x EVM with WL12xx on MMC1

This series begins the conversion of the DaVinci private
EDMA API implementation to a DMA engine driver and
converts two of the three in-kernel users of the private
EDMA API to DMA engine.

The approach taken is similar to the recent OMAP DMA
Engine conversion. The EDMA DMA Engine driver is a
wrapper around the existing private EDMA implementation
and registers the platform device within the driver.
This allows the conversion series to stand alone with
just the drivers and no changes to platform code. It
also allows peripheral drivers to continue to use the
private EDMA implementation until they are converted.

The EDMA DMA Engine driver supports slave transfers only
at this time. It is planned to add cyclic transfers in
support of audio peripherals.

There are three users of the private EDMA API in the
kernel now: davinci_mmc, spi-davinci, and davinci-mcasp.
This series provides DMA Engine conversions for the
davinci_mmc and spi-davinci drivers which use the
supported slave transfers.

This series has been tested on an AM18x EVM and
performance is comparable with the private EDMA
API implementations. Both MMC0 and MMC1 are tested
which handles the DA850/OMAP-L138/AM18x specific
case where MMC1 has DMA channels on a second EDMA
channel controller. Testing is needed on all DaVinci
platforms including DM355/365, DM644x/6x,
DA830/OMAP-L137/AM17x, and DA850/OMAP-L138/AM18x.

In order to ease the testing burden, I've pushed a
branch for each series release to my github tree
at https://github.com/ohporter/linux. The current
branch is edma-dmaengine-v2.

After this series, the current plan is to complete
the mcasp driver conversion which includes adding
cyclic dma support. This will then enable the
removal and refactoring of the private EDMA API
functionality into the EDMA DMA Engine driver.
Since EDMA is also used on the AM33xx family of
parts in mach-omap2/, the plan is to enable this
driver on that platform as well.

Matt Porter (3):
  dmaengine: add TI EDMA DMA engine driver
  mmc: davinci_mmc: convert to DMA engine API
  spi: spi-davinci: convert to DMA engine API

 drivers/dma/Kconfig            |   10 +
 drivers/dma/Makefile           |    1 +
 drivers/dma/edma.c             |  684 ++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/davinci_mmc.c |  271 +++++-----------
 drivers/spi/spi-davinci.c      |  292 ++++++++---------
 include/linux/edma.h           |   29 ++
 6 files changed, 936 insertions(+), 351 deletions(-)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

-- 
1.7.9.5



From mporter at ti.com  Tue Aug 21 14:43:08 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 21 Aug 2012 14:43:08 -0400
Subject: [PATCH v2 2/3] mmc: davinci_mmc: convert to DMA engine API
In-Reply-To: <1345574589-24757-1-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
Message-ID: <1345574589-24757-3-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/mmc/host/davinci_mmc.c |  271 ++++++++++++----------------------------
 1 file changed, 82 insertions(+), 189 deletions(-)

diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 7cf6c62..c5e1eeb 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -30,11 +30,12 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/mmc/mmc.h>
 
 #include <mach/mmc.h>
-#include <mach/edma.h>
 
 /*
  * Register Definitions
@@ -200,21 +201,13 @@ struct mmc_davinci_host {
 	u32 bytes_left;
 
 	u32 rxdma, txdma;
+	struct dma_chan *dma_tx;
+	struct dma_chan *dma_rx;
 	bool use_dma;
 	bool do_dma;
 	bool sdio_int;
 	bool active_request;
 
-	/* Scatterlist DMA uses one or more parameter RAM entries:
-	 * the main one (associated with rxdma or txdma) plus zero or
-	 * more links.  The entries for a given transfer differ only
-	 * by memory buffer (address, length) and link field.
-	 */
-	struct edmacc_param	tx_template;
-	struct edmacc_param	rx_template;
-	unsigned		n_link;
-	u32			links[MAX_NR_SG - 1];
-
 	/* For PIO we walk scatterlists one segment at a time. */
 	unsigned int		sg_len;
 	struct scatterlist *sg;
@@ -410,153 +403,74 @@ static void mmc_davinci_start_command(struct mmc_davinci_host *host,
 
 static void davinci_abort_dma(struct mmc_davinci_host *host)
 {
-	int sync_dev;
+	struct dma_chan *sync_dev;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
-		sync_dev = host->rxdma;
+		sync_dev = host->dma_rx;
 	else
-		sync_dev = host->txdma;
-
-	edma_stop(sync_dev);
-	edma_clean_channel(sync_dev);
-}
-
-static void
-mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
-
-static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
-{
-	if (DMA_COMPLETE != ch_status) {
-		struct mmc_davinci_host *host = data;
-
-		/* Currently means:  DMA Event Missed, or "null" transfer
-		 * request was seen.  In the future, TC errors (like bad
-		 * addresses) might be presented too.
-		 */
-		dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
-			(host->data->flags & MMC_DATA_WRITE)
-				? "write" : "read");
-		host->data->error = -EIO;
-		mmc_davinci_xfer_done(host, host->data);
-	}
-}
-
-/* Set up tx or rx template, to be modified and updated later */
-static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
-		bool tx, struct edmacc_param *template)
-{
-	unsigned	sync_dev;
-	const u16	acnt = 4;
-	const u16	bcnt = rw_threshold >> 2;
-	const u16	ccnt = 0;
-	u32		src_port = 0;
-	u32		dst_port = 0;
-	s16		src_bidx, dst_bidx;
-	s16		src_cidx, dst_cidx;
-
-	/*
-	 * A-B Sync transfer:  each DMA request is for one "frame" of
-	 * rw_threshold bytes, broken into "acnt"-size chunks repeated
-	 * "bcnt" times.  Each segment needs "ccnt" such frames; since
-	 * we tell the block layer our mmc->max_seg_size limit, we can
-	 * trust (later) that it's within bounds.
-	 *
-	 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
-	 * EDMA will optimize memory operations to use larger bursts.
-	 */
-	if (tx) {
-		sync_dev = host->txdma;
-
-		/* src_prt, ccnt, and link to be set up later */
-		src_bidx = acnt;
-		src_cidx = acnt * bcnt;
-
-		dst_port = host->mem_res->start + DAVINCI_MMCDXR;
-		dst_bidx = 0;
-		dst_cidx = 0;
-	} else {
-		sync_dev = host->rxdma;
-
-		src_port = host->mem_res->start + DAVINCI_MMCDRR;
-		src_bidx = 0;
-		src_cidx = 0;
-
-		/* dst_prt, ccnt, and link to be set up later */
-		dst_bidx = acnt;
-		dst_cidx = acnt * bcnt;
-	}
-
-	/*
-	 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
-	 * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
-	 * parameter is ignored.
-	 */
-	edma_set_src(sync_dev, src_port, INCR, W8BIT);
-	edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
+		sync_dev = host->dma_tx;
 
-	edma_set_src_index(sync_dev, src_bidx, src_cidx);
-	edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
-
-	edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
-
-	edma_read_slot(sync_dev, template);
-
-	/* don't bother with irqs or chaining */
-	template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
+	dmaengine_terminate_all(sync_dev);
 }
 
-static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
+static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
 		struct mmc_data *data)
 {
-	struct edmacc_param	*template;
-	int			channel, slot;
-	unsigned		link;
-	struct scatterlist	*sg;
-	unsigned		sg_len;
-	unsigned		bytes_left = host->bytes_left;
-	const unsigned		shift = ffs(rw_threshold) - 1;
+	struct dma_chan *chan;
+	struct dma_async_tx_descriptor *desc;
+	int ret = 0;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
-		template = &host->tx_template;
-		channel = host->txdma;
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
+			.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.dst_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_tx;
+		dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_tx,
+				data->sg,
+				host->sg_len,
+				DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA TX descriptor");
+			ret = -1;
+			goto out;
+		}
 	} else {
-		template = &host->rx_template;
-		channel = host->rxdma;
-	}
-
-	/* We know sg_len and ccnt will never be out of range because
-	 * we told the mmc layer which in turn tells the block layer
-	 * to ensure that it only hands us one scatterlist segment
-	 * per EDMA PARAM entry.  Update the PARAM
-	 * entries needed for each segment of this scatterlist.
-	 */
-	for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
-			sg_len-- != 0 && bytes_left;
-			sg = sg_next(sg), slot = host->links[link++]) {
-		u32		buf = sg_dma_address(sg);
-		unsigned	count = sg_dma_len(sg);
-
-		template->link_bcntrld = sg_len
-				? (EDMA_CHAN_SLOT(host->links[link]) << 5)
-				: 0xffff;
-
-		if (count > bytes_left)
-			count = bytes_left;
-		bytes_left -= count;
-
-		if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
-			template->src = buf;
-		else
-			template->dst = buf;
-		template->ccnt = count >> shift;
-
-		edma_write_slot(slot, template);
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = host->mem_res->start + DAVINCI_MMCDRR,
+			.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.src_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_rx;
+		dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_rx,
+				data->sg,
+				host->sg_len,
+				DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA RX descriptor");
+			ret = -1;
+			goto out;
+		}
 	}
 
-	if (host->version == MMC_CTLR_VERSION_2)
-		edma_clear_event(channel);
+	dmaengine_submit(desc);
+	dma_async_issue_pending(chan);
 
-	edma_start(channel);
+out:
+	return ret;
 }
 
 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
@@ -564,6 +478,7 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 {
 	int i;
 	int mask = rw_threshold - 1;
+	int ret = 0;
 
 	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 				((data->flags & MMC_DATA_WRITE)
@@ -583,70 +498,48 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 	}
 
 	host->do_dma = 1;
-	mmc_davinci_send_dma_request(host, data);
+	ret = mmc_davinci_send_dma_request(host, data);
 
-	return 0;
+	return ret;
 }
 
 static void __init_or_module
 davinci_release_dma_channels(struct mmc_davinci_host *host)
 {
-	unsigned	i;
-
 	if (!host->use_dma)
 		return;
 
-	for (i = 0; i < host->n_link; i++)
-		edma_free_slot(host->links[i]);
-
-	edma_free_channel(host->txdma);
-	edma_free_channel(host->rxdma);
+	dma_release_channel(host->dma_tx);
+	dma_release_channel(host->dma_rx);
 }
 
 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
 {
-	u32 link_size;
-	int r, i;
-
-	/* Acquire master DMA write channel */
-	r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"tx", r);
-		return r;
-	}
-	mmc_davinci_dma_setup(host, true, &host->tx_template);
-
-	/* Acquire master DMA read channel */
-	r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"rx", r);
-		goto free_master_write;
+	int r;
+	dma_cap_mask_t mask;
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	host->dma_tx =
+		dma_request_channel(mask, edma_filter_fn, &host->txdma);
+	if (!host->dma_tx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
+		return -ENODEV;
 	}
-	mmc_davinci_dma_setup(host, false, &host->rx_template);
 
-	/* Allocate parameter RAM slots, which will later be bound to a
-	 * channel as needed to handle a scatterlist.
-	 */
-	link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
-	for (i = 0; i < link_size; i++) {
-		r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
-		if (r < 0) {
-			dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
-				r);
-			break;
-		}
-		host->links[i] = r;
+	host->dma_rx =
+		dma_request_channel(mask, edma_filter_fn, &host->rxdma);
+	if (!host->dma_rx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
+		r = -ENODEV;
+		goto free_master_write;
 	}
-	host->n_link = i;
 
 	return 0;
 
 free_master_write:
-	edma_free_channel(host->txdma);
+	dma_release_channel(host->dma_tx);
 
 	return r;
 }
@@ -1359,7 +1252,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 	 * Each hw_seg uses one EDMA parameter RAM slot, always one
 	 * channel and then usually some linked slots.
 	 */
-	mmc->max_segs		= 1 + host->n_link;
+	mmc->max_segs		= MAX_NR_SG;
 
 	/* EDMA limit per hw segment (one or two MBytes) */
 	mmc->max_seg_size	= MAX_CCNT * rw_threshold;
-- 
1.7.9.5



From mporter at ti.com  Tue Aug 21 14:43:09 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 21 Aug 2012 14:43:09 -0400
Subject: [PATCH v2 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345574589-24757-1-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
Message-ID: <1345574589-24757-4-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/spi/spi-davinci.c |  292 ++++++++++++++++++++-------------------------
 1 file changed, 130 insertions(+), 162 deletions(-)

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 9b2901f..c1ec52d 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -25,13 +25,14 @@
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
 #include <mach/spi.h>
-#include <mach/edma.h>
 
 #define SPI_NO_RESOURCE		((resource_size_t)-1)
 
@@ -113,14 +114,6 @@
 #define SPIDEF		0x4c
 #define SPIFMT0		0x50
 
-/* We have 2 DMA channels per CS, one for RX and one for TX */
-struct davinci_spi_dma {
-	int			tx_channel;
-	int			rx_channel;
-	int			dummy_param_slot;
-	enum dma_event_q	eventq;
-};
-
 /* SPI Controller driver's private data. */
 struct davinci_spi {
 	struct spi_bitbang	bitbang;
@@ -134,11 +127,14 @@ struct davinci_spi {
 
 	const void		*tx;
 	void			*rx;
-#define SPI_TMP_BUFSZ	(SMP_CACHE_BYTES + 1)
-	u8			rx_tmp_buf[SPI_TMP_BUFSZ];
 	int			rcount;
 	int			wcount;
-	struct davinci_spi_dma	dma;
+
+	struct dma_chan		*dma_rx;
+	struct dma_chan		*dma_tx;
+	int			dma_rx_chnum;
+	int			dma_tx_chnum;
+
 	struct davinci_spi_platform_data *pdata;
 
 	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
@@ -496,21 +492,23 @@ out:
 	return errors;
 }
 
-static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
+static void davinci_spi_dma_rx_callback(void *data)
 {
-	struct davinci_spi *dspi = data;
-	struct davinci_spi_dma *dma = &dspi->dma;
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
 
-	edma_stop(lch);
+	dspi->rcount = 0;
 
-	if (status == DMA_COMPLETE) {
-		if (lch == dma->rx_channel)
-			dspi->rcount = 0;
-		if (lch == dma->tx_channel)
-			dspi->wcount = 0;
-	}
+	if (!dspi->wcount && !dspi->rcount)
+		complete(&dspi->done);
+}
 
-	if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
+static void davinci_spi_dma_tx_callback(void *data)
+{
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
+
+	dspi->wcount = 0;
+
+	if (!dspi->wcount && !dspi->rcount)
 		complete(&dspi->done);
 }
 
@@ -526,20 +524,20 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
 	struct davinci_spi *dspi;
-	int data_type, ret;
+	int data_type, ret = -ENOMEM;
 	u32 tx_data, spidat1;
 	u32 errors = 0;
 	struct davinci_spi_config *spicfg;
 	struct davinci_spi_platform_data *pdata;
 	unsigned uninitialized_var(rx_buf_count);
-	struct device *sdev;
+	void *dummy_buf = NULL;
+	struct scatterlist sg_rx, sg_tx;
 
 	dspi = spi_master_get_devdata(spi->master);
 	pdata = dspi->pdata;
 	spicfg = (struct davinci_spi_config *)spi->controller_data;
 	if (!spicfg)
 		spicfg = &davinci_spi_default_cfg;
-	sdev = dspi->bitbang.master->dev.parent;
 
 	/* convert len to words based on bits_per_word */
 	data_type = dspi->bytes_per_word[spi->chip_select];
@@ -567,112 +565,83 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 		spidat1 |= tx_data & 0xFFFF;
 		iowrite32(spidat1, dspi->base + SPIDAT1);
 	} else {
-		struct davinci_spi_dma *dma;
-		unsigned long tx_reg, rx_reg;
-		struct edmacc_param param;
-		void *rx_buf;
-		int b, c;
-
-		dma = &dspi->dma;
-
-		tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
-		rx_reg = (unsigned long)dspi->pbase + SPIBUF;
-
-		/*
-		 * Transmit DMA setup
-		 *
-		 * If there is transmit data, map the transmit buffer, set it
-		 * as the source of data and set the source B index to data
-		 * size. If there is no transmit data, set the transmit register
-		 * as the source of data, and set the source B index to zero.
-		 *
-		 * The destination is always the transmit register itself. And
-		 * the destination never increments.
-		 */
-
-		if (t->tx_buf) {
-			t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
-						t->len, DMA_TO_DEVICE);
-			if (dma_mapping_error(&spi->dev, t->tx_dma)) {
-				dev_dbg(sdev, "Unable to DMA map %d bytes"
-						"TX buffer\n", t->len);
-				return -ENOMEM;
-			}
-		}
-
-		/*
-		 * If number of words is greater than 65535, then we need
-		 * to configure a 3 dimension transfer.  Use the BCNTRLD
-		 * feature to allow for transfers that aren't even multiples
-		 * of 65535 (or any other possible b size) by first transferring
-		 * the remainder amount then grabbing the next N blocks of
-		 * 65535 words.
-		 */
-
-		c = dspi->wcount / (SZ_64K - 1);	/* N 65535 Blocks */
-		b = dspi->wcount - c * (SZ_64K - 1);	/* Remainder */
-		if (b)
-			c++;
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
+			.src_addr_width = data_type,
+			.src_maxburst = 1,
+		};
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
+			.dst_addr_width = data_type,
+			.dst_maxburst = 1,
+		};
+		struct dma_async_tx_descriptor *rxdesc;
+		struct dma_async_tx_descriptor *txdesc;
+		void *buf;
+
+		dummy_buf = kzalloc(t->len, GFP_KERNEL);
+		if (!dummy_buf)
+			goto err_alloc_dummy_buf;
+
+		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
+		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
+
+		sg_init_table(&sg_rx, 1);
+		if (!t->rx_buf)
+			buf = dummy_buf;
 		else
-			b = SZ_64K - 1;
-
-		param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
-		param.src = t->tx_buf ? t->tx_dma : tx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = tx_reg;
-		param.src_dst_bidx = t->tx_buf ? data_type : 0;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = t->tx_buf ? data_type : 0;
-		param.ccnt = c;
-		edma_write_slot(dma->tx_channel, &param);
-		edma_link(dma->tx_channel, dma->dummy_param_slot);
-
-		/*
-		 * Receive DMA setup
-		 *
-		 * If there is receive buffer, use it to receive data. If there
-		 * is none provided, use a temporary receive buffer. Set the
-		 * destination B index to 0 so effectively only one byte is used
-		 * in the temporary buffer (address does not increment).
-		 *
-		 * The source of receive data is the receive data register. The
-		 * source address never increments.
-		 */
-
-		if (t->rx_buf) {
-			rx_buf = t->rx_buf;
-			rx_buf_count = t->len;
-		} else {
-			rx_buf = dspi->rx_tmp_buf;
-			rx_buf_count = sizeof(dspi->rx_tmp_buf);
+			buf = t->rx_buf;
+		t->rx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->rx_dma) {
+			ret = -EFAULT;
+			goto err_rx_map;
 		}
+		sg_dma_address(&sg_rx) = t->rx_dma;
+		sg_dma_len(&sg_rx) = t->len;
 
-		t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
-							DMA_FROM_DEVICE);
-		if (dma_mapping_error(&spi->dev, t->rx_dma)) {
-			dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
-								rx_buf_count);
-			if (t->tx_buf)
-				dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-			return -ENOMEM;
+		sg_init_table(&sg_tx, 1);
+		if (!t->tx_buf)
+			buf = dummy_buf;
+		else
+			buf = (void *)t->tx_buf;
+		t->tx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->tx_dma) {
+			ret = -EFAULT;
+			goto err_tx_map;
 		}
-
-		param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
-		param.src = rx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = t->rx_dma;
-		param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16;
-		param.ccnt = c;
-		edma_write_slot(dma->rx_channel, &param);
+		sg_dma_address(&sg_tx) = t->tx_dma;
+		sg_dma_len(&sg_tx) = t->len;
+
+		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
+				&sg_rx, 1, DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!rxdesc)
+			goto err_desc;
+
+		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
+				&sg_tx, 1, DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!txdesc)
+			goto err_desc;
+
+		rxdesc->callback = davinci_spi_dma_rx_callback;
+		rxdesc->callback_param = (void *)dspi;
+		txdesc->callback = davinci_spi_dma_tx_callback;
+		txdesc->callback_param = (void *)dspi;
 
 		if (pdata->cshold_bug)
 			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
 
-		edma_start(dma->rx_channel);
-		edma_start(dma->tx_channel);
+		dmaengine_submit(rxdesc);
+		dmaengine_submit(txdesc);
+
+		dma_async_issue_pending(dspi->dma_rx);
+		dma_async_issue_pending(dspi->dma_tx);
+
 		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
 	}
 
@@ -690,15 +659,13 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 
 	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
 	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
-
-		if (t->tx_buf)
-			dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-
-		dma_unmap_single(&spi->dev, t->rx_dma, rx_buf_count,
-							DMA_FROM_DEVICE);
-
 		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
+
+		dma_unmap_single(&spi->dev, t->rx_dma,
+				t->len, DMA_FROM_DEVICE);
+		dma_unmap_single(&spi->dev, t->tx_dma,
+				t->len, DMA_TO_DEVICE);
+		kfree(dummy_buf);
 	}
 
 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
@@ -716,11 +683,20 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 	}
 
 	if (dspi->rcount != 0 || dspi->wcount != 0) {
-		dev_err(sdev, "SPI data transfer error\n");
+		dev_err(&spi->dev, "SPI data transfer error\n");
 		return -EIO;
 	}
 
 	return t->len;
+
+err_desc:
+	dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
+err_tx_map:
+	dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
+err_rx_map:
+	kfree(dummy_buf);
+err_alloc_dummy_buf:
+	return ret;
 }
 
 /**
@@ -751,39 +727,33 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *data)
 
 static int davinci_spi_request_dma(struct davinci_spi *dspi)
 {
+	dma_cap_mask_t mask;
+	struct device *sdev = dspi->bitbang.master->dev.parent;
 	int r;
-	struct davinci_spi_dma *dma = &dspi->dma;
 
-	r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI RX\n");
-		r = -EAGAIN;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_rx_chnum);
+	if (!dspi->dma_rx) {
+		dev_err(sdev, "request RX DMA channel failed\n");
+		r = -ENODEV;
 		goto rx_dma_failed;
 	}
 
-	r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI TX\n");
-		r = -EAGAIN;
+	dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_tx_chnum);
+	if (!dspi->dma_tx) {
+		dev_err(sdev, "request TX DMA channel failed\n");
+		r = -ENODEV;
 		goto tx_dma_failed;
 	}
 
-	r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
-	if (r < 0) {
-		pr_err("Unable to request SPI TX DMA param slot\n");
-		r = -EAGAIN;
-		goto param_failed;
-	}
-	dma->dummy_param_slot = r;
-	edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
-
 	return 0;
-param_failed:
-	edma_free_channel(dma->tx_channel);
+
 tx_dma_failed:
-	edma_free_channel(dma->rx_channel);
+	dma_release_channel(dspi->dma_rx);
 rx_dma_failed:
 	return r;
 }
@@ -898,9 +868,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
 	if (dma_rx_chan != SPI_NO_RESOURCE &&
 	    dma_tx_chan != SPI_NO_RESOURCE) {
-		dspi->dma.rx_channel = dma_rx_chan;
-		dspi->dma.tx_channel = dma_tx_chan;
-		dspi->dma.eventq = pdata->dma_event_q;
+		dspi->dma_rx_chnum = dma_rx_chan;
+		dspi->dma_tx_chnum = dma_tx_chan;
 
 		ret = davinci_spi_request_dma(dspi);
 		if (ret)
@@ -955,9 +924,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	return ret;
 
 free_dma:
-	edma_free_channel(dspi->dma.tx_channel);
-	edma_free_channel(dspi->dma.rx_channel);
-	edma_free_slot(dspi->dma.dummy_param_slot);
+	dma_release_channel(dspi->dma_rx);
+	dma_release_channel(dspi->dma_tx);
 free_clk:
 	clk_disable(dspi->clk);
 	clk_put(dspi->clk);
-- 
1.7.9.5



From mporter at ti.com  Tue Aug 21 14:43:07 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 21 Aug 2012 14:43:07 -0400
Subject: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345574589-24757-1-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
Message-ID: <1345574589-24757-2-git-send-email-mporter@ti.com>

Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/dma/Kconfig  |   10 +
 drivers/dma/Makefile |    1 +
 drivers/dma/edma.c   |  684 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/edma.h |   29 +++
 4 files changed, 724 insertions(+)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..5064e85 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,16 @@ config SIRF_DMA
 	help
 	  Enable support for the CSR SiRFprimaII DMA engine.
 
+config TI_EDMA
+	tristate "TI EDMA support"
+	depends on ARCH_DAVINCI
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	default y
+	help
+	  Enable support for the TI EDMA controller. This DMA
+	  engine is found on TI DaVinci and AM33xx parts.
+
 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 0000000..bf15f81
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,684 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <mach/edma.h>
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/*
+ * This will go away when the private EDMA API is folded
+ * into this driver and the platform device(s) are
+ * instantiated in the arch code. We can only get away
+ * with this simplification because DA8XX may not be built
+ * in the same kernel image with other DaVinci parts. This
+ * avoids having to sprinkle dmaengine driver platform devices
+ * and data throughout all the existing board files.
+ */
+#ifdef CONFIG_ARCH_DAVINCI_DA8XX
+#define EDMA_CTLRS	2
+#define EDMA_CHANS	32
+#else
+#define EDMA_CTLRS	1
+#define EDMA_CHANS	64
+#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
+
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG		16
+#define EDMA_MAX_SLOTS		MAX_NR_SG
+#define EDMA_DESCRIPTORS	16
+
+struct edma_desc {
+	struct virt_dma_desc		vdesc;
+	struct list_head		node;
+
+	int				absync;
+	int				pset_nr;
+	struct edmacc_param		pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+	struct virt_dma_chan		vchan;
+	struct list_head		node;
+	struct edma_desc		*edesc;
+	struct edma_cc			*ecc;
+	int				ch_num;
+	bool				alloced;
+	int				slot[EDMA_MAX_SLOTS];
+
+	dma_addr_t			addr;
+	int				addr_width;
+	int				maxburst;
+};
+
+struct edma_cc {
+	int				ctlr;
+	struct dma_device		dma_slave;
+	struct edma_chan		slave_chans[EDMA_CHANS];
+	int				num_slave_chans;
+	int				dummy_slot;
+};
+
+static inline struct edma_cc *to_edma_cc(struct dma_device *d)
+{
+	return container_of(d, struct edma_cc, dma_slave);
+}
+
+static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct edma_chan, vchan.chan);
+}
+
+static inline struct edma_desc
+*to_edma_desc(struct dma_async_tx_descriptor *tx)
+{
+	return container_of(tx, struct edma_desc, vdesc.tx);
+}
+
+static void edma_desc_free(struct virt_dma_desc *vdesc)
+{
+	kfree(container_of(vdesc, struct edma_desc, vdesc));
+}
+
+/* Dispatch a queued descriptor to the controller (caller holds lock) */
+static void edma_execute(struct edma_chan *echan)
+{
+	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
+	struct edma_desc *edesc;
+	int i;
+
+	if (!vdesc) {
+		echan->edesc = NULL;
+		return;
+	}
+
+	list_del(&vdesc->node);
+
+	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
+
+	/* Write descriptor PaRAM set(s) */
+	for (i = 0; i < edesc->pset_nr; i++) {
+		edma_write_slot(echan->slot[i], &edesc->pset[i]);
+		dev_dbg(echan->vchan.chan.device->dev,
+			"\n pset[%d]:\n"
+			"  chnum\t%d\n"
+			"  slot\t%d\n"
+			"  opt\t%08x\n"
+			"  src\t%08x\n"
+			"  dst\t%08x\n"
+			"  abcnt\t%08x\n"
+			"  ccnt\t%08x\n"
+			"  bidx\t%08x\n"
+			"  cidx\t%08x\n"
+			"  lkrld\t%08x\n",
+			i, echan->ch_num, echan->slot[i],
+			edesc->pset[i].opt,
+			edesc->pset[i].src,
+			edesc->pset[i].dst,
+			edesc->pset[i].a_b_cnt,
+			edesc->pset[i].ccnt,
+			edesc->pset[i].src_dst_bidx,
+			edesc->pset[i].src_dst_cidx,
+			edesc->pset[i].link_bcntrld);
+		/* Link to the previous slot if not the last set */
+		if (i != (edesc->pset_nr - 1))
+			edma_link(echan->slot[i], echan->slot[i+1]);
+		/* Final pset links to the dummy pset */
+		else
+			edma_link(echan->slot[i], echan->ecc->dummy_slot);
+	}
+
+	edma_start(echan->ch_num);
+}
+
+static int edma_terminate_all(struct edma_chan *echan)
+{
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+
+	/*
+	 * Stop DMA activity: we assume the callback will not be called
+	 * after edma_dma() returns (even if it does, it will see
+	 * echan->edesc is NULL and exit.)
+	 */
+	if (echan->edesc) {
+		echan->edesc = NULL;
+		edma_stop(echan->ch_num);
+	}
+
+	vchan_get_all_descriptors(&echan->vchan, &head);
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+	vchan_dma_desc_free_list(&echan->vchan, &head);
+
+	return 0;
+}
+
+
+static int edma_slave_config(struct edma_chan *echan,
+	struct dma_slave_config *config)
+{
+	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+		return -EINVAL;
+
+	if (config->direction == DMA_MEM_TO_DEV) {
+		if (config->dst_addr)
+			echan->addr = config->dst_addr;
+		if (config->dst_addr_width)
+			echan->addr_width = config->dst_addr_width;
+		if (config->dst_maxburst)
+			echan->maxburst = config->dst_maxburst;
+	} else if (config->direction == DMA_DEV_TO_MEM) {
+		if (config->src_addr)
+			echan->addr = config->src_addr;
+		if (config->src_addr_width)
+			echan->addr_width = config->src_addr_width;
+		if (config->src_maxburst)
+			echan->maxburst = config->src_maxburst;
+	}
+
+	return 0;
+}
+
+static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			unsigned long arg)
+{
+	int ret = 0;
+	struct dma_slave_config *config;
+	struct edma_chan *echan = to_edma_chan(chan);
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		edma_terminate_all(echan);
+		break;
+	case DMA_SLAVE_CONFIG:
+		config = (struct dma_slave_config *)arg;
+		ret = edma_slave_config(echan, config);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	return ret;
+}
+
+static struct dma_async_tx_descriptor *edma_prep_slave_sg(
+	struct dma_chan *chan, struct scatterlist *sgl,
+	unsigned int sg_len, enum dma_transfer_direction direction,
+	unsigned long tx_flags, void *context)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = echan->vchan.chan.device->dev;
+	struct edma_desc *edesc;
+	struct scatterlist *sg;
+	int i;
+	int acnt, bcnt, ccnt, src, dst, cidx;
+	int src_bidx, dst_bidx, src_cidx, dst_cidx;
+
+	if (unlikely(!echan || !sgl || !sg_len))
+		return NULL;
+
+	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
+		dev_err(dev, "Undefined slave buswidth\n");
+		return NULL;
+	}
+
+	if (sg_len > MAX_NR_SG) {
+		dev_err(dev, "Exceeded max SG segments %d > %d\n",
+			sg_len, MAX_NR_SG);
+		return NULL;
+	}
+
+	edesc = kzalloc(sizeof(*edesc) + sg_len *
+		sizeof(edesc->pset[0]), GFP_ATOMIC);
+	if (!edesc) {
+		dev_dbg(dev, "Failed to allocate a descriptor\n");
+		return NULL;
+	}
+
+	edesc->pset_nr = sg_len;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		/* Allocate a PaRAM slot, if needed */
+		if (echan->slot[i] < 0) {
+			echan->slot[i] =
+				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
+						EDMA_SLOT_ANY);
+			if (echan->slot[i] < 0) {
+				dev_err(dev, "Failed to allocate slot\n");
+				return NULL;
+			}
+		}
+
+		acnt = echan->addr_width;
+
+		/*
+		 * If the maxburst is equal to the fifo width, use
+		 * A-synced transfers. This allows for large contiguous
+		 * buffer transfers using only one PaRAM set.
+		 */
+		if (echan->maxburst == 1) {
+			edesc->absync = false;
+			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
+			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
+			if (bcnt)
+				ccnt++;
+			else
+				bcnt = SZ_64K - 1;
+			cidx = acnt;
+		/*
+		 * If maxburst is greater than the fifo address_width,
+		 * use AB-synced transfers where A count is the fifo
+		 * address_width and B count is the maxburst. In this
+		 * case, we are limited to transfers of C count frames
+		 * of (address_width * maxburst) where C count is limited
+		 * to SZ_64K-1. This places an upper bound on the length
+		 * of an SG segment that can be handled.
+		 */
+		} else {
+			edesc->absync = true;
+			bcnt = echan->maxburst;
+			ccnt = sg_dma_len(sg) / (acnt * bcnt);
+			if (ccnt > (SZ_64K - 1)) {
+				dev_err(dev, "Exceeded max SG segment size\n");
+				return NULL;
+			}
+			cidx = acnt * bcnt;
+		}
+
+		if (direction == DMA_MEM_TO_DEV) {
+			src = sg_dma_address(sg);
+			dst = echan->addr;
+			src_bidx = acnt;
+			src_cidx = cidx;
+			dst_bidx = 0;
+			dst_cidx = 0;
+		} else {
+			src = echan->addr;
+			dst = sg_dma_address(sg);
+			src_bidx = 0;
+			src_cidx = 0;
+			dst_bidx = acnt;
+			dst_cidx = cidx;
+		}
+
+		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
+		/* Configure A or AB synchronized transfers */
+		if (edesc->absync)
+			edesc->pset[i].opt |= SYNCDIM;
+		/* If this is the last set, enable completion interrupt flag */
+		if (i == sg_len - 1)
+			edesc->pset[i].opt |= TCINTEN;
+
+		edesc->pset[i].src = src;
+		edesc->pset[i].dst = dst;
+
+		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
+		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
+
+		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
+		edesc->pset[i].ccnt = ccnt;
+		edesc->pset[i].link_bcntrld = 0xffffffff;
+
+	}
+
+	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
+}
+
+static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
+{
+	struct edma_chan *echan = data;
+	struct device *dev = echan->vchan.chan.device->dev;
+	struct edma_desc *edesc;
+	unsigned long flags;
+
+	/* Stop the channel */
+	edma_stop(echan->ch_num);
+
+	switch (ch_status) {
+	case DMA_COMPLETE:
+		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
+
+		spin_lock_irqsave(&echan->vchan.lock, flags);
+
+		edesc = echan->edesc;
+		if (edesc) {
+			edma_execute(echan);
+			vchan_cookie_complete(&edesc->vdesc);
+		}
+
+		spin_unlock_irqrestore(&echan->vchan.lock, flags);
+
+		break;
+	case DMA_CC_ERROR:
+		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Alloc channel resources */
+static int edma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = echan->vchan.chan.device->dev;
+	int ret;
+	int a_ch_num;
+	LIST_HEAD(descs);
+
+	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
+					chan, EVENTQ_DEFAULT);
+
+	if (a_ch_num < 0) {
+		ret = -ENODEV;
+		goto err_no_chan;
+	}
+
+	if (a_ch_num != echan->ch_num) {
+		dev_err(dev, "failed to allocate requested channel %u:%u\n",
+			EDMA_CTLR(echan->ch_num),
+			EDMA_CHAN_SLOT(echan->ch_num));
+		ret = -ENODEV;
+		goto err_wrong_chan;
+	}
+
+	echan->alloced = true;
+	echan->slot[0] = echan->ch_num;
+
+	dev_info(dev, "allocated channel for %u:%u\n",
+		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
+
+	return 0;
+
+err_wrong_chan:
+	edma_free_channel(a_ch_num);
+err_no_chan:
+	return ret;
+}
+
+/* Free channel resources */
+static void edma_free_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = echan->vchan.chan.device->dev;
+	int i;
+
+	/* Terminate transfers */
+	edma_stop(echan->ch_num);
+
+	vchan_free_chan_resources(&echan->vchan);
+
+	/* Free EDMA PaRAM slots */
+	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
+		if (echan->slot[i] >= 0) {
+			edma_free_slot(echan->slot[i]);
+			echan->slot[i] = -1;
+		}
+	}
+
+	/* Free EDMA channel */
+	if (echan->alloced) {
+		edma_free_channel(echan->ch_num);
+		echan->alloced = false;
+	}
+
+	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
+}
+
+/* Send pending descriptor to hardware */
+static void edma_issue_pending(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
+		edma_execute(echan);
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+}
+
+static size_t edma_desc_size(struct edma_desc *edesc)
+{
+	int i;
+	size_t size;
+
+	if (edesc->absync)
+		for (size = i = 0; i < edesc->pset_nr; i++)
+			size += (edesc->pset[i].a_b_cnt & 0xffff) *
+				(edesc->pset[i].a_b_cnt >> 16) *
+				 edesc->pset[i].ccnt;
+	else
+		size = (edesc->pset[0].a_b_cnt & 0xffff) *
+			(edesc->pset[0].a_b_cnt >> 16) +
+			(edesc->pset[0].a_b_cnt & 0xffff) *
+			(SZ_64K - 1) * edesc->pset[0].ccnt;
+
+	return size;
+}
+
+/* Check request completion status */
+static enum dma_status edma_tx_status(struct dma_chan *chan,
+				      dma_cookie_t cookie,
+				      struct dma_tx_state *txstate)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct virt_dma_desc *vdesc;
+	enum dma_status ret;
+	unsigned long flags;
+
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret == DMA_SUCCESS || !txstate)
+		return ret;
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+	vdesc = vchan_find_desc(&echan->vchan, cookie);
+	if (vdesc) {
+		txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
+	} else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
+		struct edma_desc *edesc = echan->edesc;
+		txstate->residue = edma_desc_size(edesc);
+	} else {
+		txstate->residue = 0;
+	}
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+
+	return ret;
+}
+
+static void __init edma_chan_init(struct edma_cc *ecc,
+				  struct dma_device *dma,
+				  struct edma_chan *echans)
+{
+	int i, j;
+	int chcnt = 0;
+
+	for (i = 0; i < EDMA_CHANS; i++) {
+		struct edma_chan *echan = &echans[chcnt];
+		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
+		echan->ecc = ecc;
+		echan->vchan.desc_free = edma_desc_free;
+
+		vchan_init(&echan->vchan, dma);
+
+		INIT_LIST_HEAD(&echan->node);
+		for (j = 0; j < EDMA_MAX_SLOTS; j++)
+			echan->slot[j] = -1;
+
+		chcnt++;
+	}
+}
+
+static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
+			  struct device *dev)
+{
+	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
+		dma->device_prep_slave_sg = edma_prep_slave_sg;
+
+	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
+	dma->device_free_chan_resources = edma_free_chan_resources;
+	dma->device_issue_pending = edma_issue_pending;
+	dma->device_tx_status = edma_tx_status;
+	dma->device_control = edma_control;
+	dma->dev = dev;
+
+	INIT_LIST_HEAD(&dma->channels);
+}
+
+static int __devinit edma_probe(struct platform_device *pdev)
+{
+	struct edma_cc *ecc;
+	int ret;
+
+	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
+	if (!ecc) {
+		dev_err(&pdev->dev, "Can't allocate controller\n");
+		ret = -ENOMEM;
+		goto err_alloc_ecc;
+	}
+
+	ecc->ctlr = pdev->id;
+	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
+	if (ecc->dummy_slot < 0) {
+		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
+		ret = -EIO;
+		goto err_alloc_slot;
+	}
+
+	dma_cap_zero(ecc->dma_slave.cap_mask);
+	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
+
+	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
+
+	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
+
+	ret = dma_async_device_register(&ecc->dma_slave);
+	if (ret)
+		goto err_reg1;
+
+	platform_set_drvdata(pdev, ecc);
+
+	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
+
+	return 0;
+
+err_reg1:
+	edma_free_slot(ecc->dummy_slot);
+err_alloc_slot:
+	devm_kfree(&pdev->dev, ecc);
+err_alloc_ecc:
+	return ret;
+}
+
+static int __devexit edma_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct edma_cc *ecc = dev_get_drvdata(dev);
+
+	dma_async_device_unregister(&ecc->dma_slave);
+	edma_free_slot(ecc->dummy_slot);
+	devm_kfree(dev, ecc);
+
+	return 0;
+}
+
+static struct platform_driver edma_driver = {
+	.probe		= edma_probe,
+	.remove		= __devexit_p(edma_remove),
+	.driver = {
+		.name = "edma-dma-engine",
+		.owner = THIS_MODULE,
+	},
+};
+
+bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	if (chan->device->dev->driver == &edma_driver.driver) {
+		struct edma_chan *echan = to_edma_chan(chan);
+		unsigned ch_req = *(unsigned *)param;
+		return ch_req == echan->ch_num;
+	}
+	return false;
+}
+EXPORT_SYMBOL(edma_filter_fn);
+
+static struct platform_device *pdev0, *pdev1;
+
+static const struct platform_device_info edma_dev_info0 = {
+	.name = "edma-dma-engine",
+	.id = 0,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
+static const struct platform_device_info edma_dev_info1 = {
+	.name = "edma-dma-engine",
+	.id = 1,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
+static int edma_init(void)
+{
+	int ret = platform_driver_register(&edma_driver);
+
+	if (ret == 0) {
+		pdev0 = platform_device_register_full(&edma_dev_info0);
+		if (IS_ERR(pdev0)) {
+			platform_driver_unregister(&edma_driver);
+			ret = PTR_ERR(pdev0);
+			goto out;
+		}
+	}
+
+	if (EDMA_CTLRS == 2) {
+		pdev1 = platform_device_register_full(&edma_dev_info1);
+		if (IS_ERR(pdev1)) {
+			platform_driver_unregister(&edma_driver);
+			platform_device_unregister(pdev0);
+			ret = PTR_ERR(pdev1);
+		}
+	}
+
+out:
+	return ret;
+}
+subsys_initcall(edma_init);
+
+static void __exit edma_exit(void)
+{
+	platform_device_unregister(pdev0);
+	if (pdev1)
+		platform_device_unregister(pdev1);
+	platform_driver_unregister(&edma_driver);
+}
+module_exit(edma_exit);
+
+MODULE_AUTHOR("Matt Porter <mporter at ti.com>");
+MODULE_DESCRIPTION("TI EDMA DMA engine driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/edma.h b/include/linux/edma.h
new file mode 100644
index 0000000..a1307e7
--- /dev/null
+++ b/include/linux/edma.h
@@ -0,0 +1,29 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_EDMA_H
+#define __LINUX_EDMA_H
+
+struct dma_chan;
+
+#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
+bool edma_filter_fn(struct dma_chan *, void *);
+#else
+static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	return false;
+}
+#endif
+
+#endif
-- 
1.7.9.5



From vapier at gentoo.org  Tue Aug 21 14:53:16 2012
From: vapier at gentoo.org (Mike Frysinger)
Date: Tue, 21 Aug 2012 14:53:16 -0400
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <20120821182731.GJ12708@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <CAMuHMdVEX0egzFETMJ=LA_PB+7Qc=Ph-7uxofVr__wOE-0cvLQ@mail.gmail.com>
 <20120821182731.GJ12708@arm.com>
Message-ID: <201208211453.18583.vapier@gentoo.org>

On Tuesday 21 August 2012 14:27:31 Catalin Marinas wrote:
> On Tue, Aug 21, 2012 at 07:17:19PM +0100, Geert Uytterhoeven wrote:
> > On Tue, Aug 21, 2012 at 6:06 PM, Catalin Marinas wrote:
> > > But I can see on x86 that it always reports x86_64 even if the task is
> > > x86_32.
> > 
> > Really?
> > 
> > $ uname -m
> > x86_64
> > $ linux32 uname -m
> > i686
> > $
> 
> Well, you set the personality explicitly with linux32. What I tested was
> with an x86_32 uname called directly (without linux32) and even though
> the ELF was a 32-bit one, it was reporting x86_64. In this AArch64
> patch, a compat task was automatically setting the linux32 personality
> (which x86 does not do).

i don't think any arch does this.

$ uname -m
ppc64
$ linux32 uname -m
ppc

$ uname -m
sparc64
$ linux32 uname -m
sparc

$ uname -m
x86_64
$ linux32 uname -m
i686

$ uname -m
s390x
$ linux32 uname -m
s390

> Arnd's point is that the ELF file should not affect the personality and
> hence the uname value. This should only be done by an explicit call to
> sys_personality().

correct.  if someone really wants to launch their whole userland with the 
adjusted personality, they could always boot the kernel with:
	init=/usr/bin/linux32 /sbin/init
but the kernel shouldn't be doing this automatically.
-mike
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From cov at codeaurora.org  Tue Aug 21 15:20:18 2012
From: cov at codeaurora.org (Christopher Covington)
Date: Tue, 21 Aug 2012 15:20:18 -0400
Subject: [PATCH v2 28/31] arm64: Generic timers support
In-Reply-To: <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-29-git-send-email-catalin.marinas@arm.com>
Message-ID: <5033DF72.70609@codeaurora.org>

On 08/14/2012 01:52 PM, Catalin Marinas wrote:
> From: Marc Zyngier <marc.zyngier at arm.com>
> 
> This patch adds support for the ARM generic timers with A64 instructions
> for accessing the timer registers. It uses the physical counter as the
> clock source and the virtual counter as sched_clock.
> 
> The timer frequency can be specified via DT or read from the CNTFRQ_EL0
> register. The physical counter is also accessible from user space
> allowing fast gettimeofday() implementation.

[...]

> +++ b/drivers/clocksource/arm_generic.c

[...]

> +static void arch_timer_reg_write(int reg, u32 val)
> +{
> +	switch (reg) {
> +	case ARCH_TIMER_REG_CTRL:
> +		asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
> +		break;
> +	case ARCH_TIMER_REG_TVAL:
> +		asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
> +		break;
> +	default:
> +		BUG();
> +	}
> +
> +	isb();
> +}

Doesn't architecture-specific assembly need to go in the arch directory rather
than the drivers directory?

Christopher

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum


From arnd at arndb.de  Tue Aug 21 15:50:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 19:50:06 +0000
Subject: [PATCH 1/4] ARM: clps711x: Remove board support for CEIVA
In-Reply-To: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
References: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
Message-ID: <201208211950.07166.arnd@arndb.de>

On Tuesday 21 August 2012, Alexander Shiyan wrote:
> The current kernel does not fit in the CEIVA ROM. Also, some functional
> has already been removed due migrate from 2.6 to 3.0, and it seems that
> no one uses this platform. So, remove support for this board and modules
> specific only to this board.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

I got curious about this machine and found some ten year old emails
and a howto from Colin Cross about this machine. Since he's still
actively working on ARM Linux, maybe he has some final words to say
about this platform before it gets removed.

Otherwise, no objections.

	Arnd

>  arch/arm/mach-clps711x/Kconfig                 |    6 -
>  arch/arm/mach-clps711x/Makefile                |    1 -
>  arch/arm/mach-clps711x/ceiva.c                 |   64 --
>  arch/arm/mach-clps711x/include/mach/hardware.h |   48 --
>  arch/arm/tools/mach-types                      |    1 -
>  drivers/video/Kconfig                          |   12 -
>  drivers/video/Makefile                         |    1 -
>  drivers/video/epson1355fb.c                    |  749 ------------------------
>  include/video/epson1355.h                      |   64 --
>  9 files changed, 0 insertions(+), 946 deletions(-)
>  delete mode 100644 arch/arm/mach-clps711x/ceiva.c
>  delete mode 100644 drivers/video/epson1355fb.c
>  delete mode 100644 include/video/epson1355.h



From arnd at arndb.de  Tue Aug 21 16:14:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 20:14:01 +0000
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <20120821175122.GI12708@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151422.16335.arnd@arndb.de> <20120821175122.GI12708@arm.com>
Message-ID: <201208212014.01837.arnd@arndb.de>

On Tuesday 21 August 2012, Catalin Marinas wrote:
> > > +asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
> > > +                    unsigned long prot, unsigned long flags,
> > > +                    unsigned long fd, off_t off)
> > > +{
> > > +   if (offset_in_page(off) != 0)
> > > +           return -EINVAL;
> > > +
> > > +   return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
> > > +}
> > 
> > I think
> > 
> > #define sys_mmap sys_mmap_pgoff 
> 
> There are slightly different semantics with the last argument of
> sys_mmap() which takes a byte offset. The sys_mmap_pgoff() function
> takes the offset shifted by PAGE_SHIFT (which is the same as sys_mmap2).
> 
> Looking at the other architectures, it makes sense to use a generic
> sys_mmap() implementation similar to the one above (or the ia-64, seems
> to be the most complete).
> 

Why that? The generic sys_mmap_pgoff was specifically added so new architectures
could just use that instead of having their own wrappers, see f8b72560.

	Arnd


From arnd at arndb.de  Tue Aug 21 16:17:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 20:17:07 +0000
Subject: [PATCH v2 16/31] arm64: ELF definitions
In-Reply-To: <20120821160653.GH12708@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208161237.53594.arnd@arndb.de> <20120821160653.GH12708@arm.com>
Message-ID: <201208212017.08110.arnd@arndb.de>

On Tuesday 21 August 2012, Catalin Marinas wrote:
> On Thu, Aug 16, 2012 at 01:37:53PM +0100, Arnd Bergmann wrote:
> > On Thursday 16 August 2012, Will Deacon wrote:
> > > > This looks wrong: PER_LINUX/PER_LINUX32 decides over the output of the
> > > > uname system call, while TIF_32BIT decides over the instruction set
> > > > when returning to user space. You definitely should not set the personality
> > > > to the value you pass from the elf loader. Instead, just do
> > > > 
> > > > #define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
> > > > #defined COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
> > > 
> > > In this case, won't uname be incorrect (aarch64l) for aarch32 tasks (which
> > > expect something like armv8l)?
> > 
> > No, the uname output is meant to tell you about the system, not the
> > instruction set that you are using (you already know that in compiled
> > code).
> 
> OK, so we assumed that compat tasks should get a uname as close as
> possible to a 32-bit system, i.e. armv8l, for full compatibility. This
> would allow us to run something like 32-bit Debian on an AArch64 kernel
> without worrying about any scripts failing.

You can still do that, just boot with init="/sbin/setarch armv7 /sbin/init".

> But I can see on x86 that it always reports x86_64 even if the task is
> x86_32.

Not just x86, the same behavior is used on powerpc, s390, mips, sparc and
parisc. Not sure about tile though.

	Arnd


From ccross at android.com  Tue Aug 21 16:31:58 2012
From: ccross at android.com (Colin Cross)
Date: Tue, 21 Aug 2012 13:31:58 -0700
Subject: [PATCH 1/4] ARM: clps711x: Remove board support for CEIVA
In-Reply-To: <201208211950.07166.arnd@arndb.de>
References: <1345568375-28516-1-git-send-email-shc_work@mail.ru>
 <201208211950.07166.arnd@arndb.de>
Message-ID: <CAMbhsRReOzQogzESWjKu5o=0Ep3UqcEP1zdzO8dbHfM4AofhYQ@mail.gmail.com>

On Tue, Aug 21, 2012 at 12:50 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 21 August 2012, Alexander Shiyan wrote:
>> The current kernel does not fit in the CEIVA ROM. Also, some functional
>> has already been removed due migrate from 2.6 to 3.0, and it seems that
>> no one uses this platform. So, remove support for this board and modules
>> specific only to this board.
>>
>> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
>
> I got curious about this machine and found some ten year old emails
> and a howto from Colin Cross about this machine. Since he's still
> actively working on ARM Linux, maybe he has some final words to say
> about this platform before it gets removed.
>
> Otherwise, no objections.

That was my first embedded linux hobby project, and I haven't touched
it in ten years, although I probably have one in a box somewhere.  I
have no objection to removing it.


From will.deacon at arm.com  Tue Aug 21 16:42:04 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 21 Aug 2012 21:42:04 +0100
Subject: [PATCH v2] serial: pl011: honour serial aliases in device tree
In-Reply-To: <1345564094-16565-1-git-send-email-matthew.leach@arm.com>
References: <1345564094-16565-1-git-send-email-matthew.leach@arm.com>
Message-ID: <20120821204204.GA8316@mudshark.cambridge.arm.com>

Hi Matthew,

On Tue, Aug 21, 2012 at 04:48:14PM +0100, Matthew Leach wrote:
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index d3553b5..33c90f6 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -52,6 +52,8 @@
>  #include <linux/scatterlist.h>
>  #include <linux/delay.h>
>  #include <linux/types.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/pinctrl/consumer.h>
>  #include <linux/sizes.h>
>  
> @@ -1869,6 +1871,38 @@ static struct uart_driver amba_reg = {
>  	.cons			= AMBA_CONSOLE,
>  };
>  
> +static int pl011_probe_dt_alias(int index, struct device *dev)
> +{
> +	struct device_node *np;
> +	static bool seen_dev_with_alias = false;
> +	static bool seen_dev_without_alias = false;
> +	int ret = index;
> +
> +	if (!IS_ENABLED(CONFIG_OF))
> +		return index;

May as well return ret here for consistency. With that:

Reviewed-by: Will Deacon <will.deacon at arm.com>

I guess this goes via Greg's tree rather than the ARM one?

Will


From linux at prisktech.co.nz  Tue Aug 21 16:47:32 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:32 +1200
Subject: [PATCHv3 3/9] serial: vt8500: Add devicetree support for vt8500-serial
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-4-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/tty/serial/vt8500_serial.c |   37 ++++++++++++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006f..72e32db 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -76,6 +77,8 @@
 #define RX_FIFO_INTS	(RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
 #define TX_FIFO_INTS	(TXFAE | TXFE | TXUDR)
 
+#define VT8500_MAX_PORTS	6
+
 struct vt8500_port {
 	struct uart_port	uart;
 	char			name[16];
@@ -83,6 +86,13 @@ struct vt8500_port {
 	unsigned int		ier;
 };
 
+/*
+ * we use this variable to keep track of which ports
+ * have been allocated as we can't use pdev->id in
+ * devicetree
+ */
+static unsigned long vt8500_ports_in_use;
+
 static inline void vt8500_write(struct uart_port *port, unsigned int val,
 			     unsigned int off)
 {
@@ -431,7 +441,7 @@ static int vt8500_verify_port(struct uart_port *port,
 	return 0;
 }
 
-static struct vt8500_port *vt8500_uart_ports[4];
+static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
 static struct uart_driver vt8500_uart_driver;
 
 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
@@ -549,6 +559,7 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 	struct vt8500_port *vt8500_port;
 	struct resource *mmres, *irqres;
 	int ret;
+	int port;
 
 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -559,13 +570,25 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 	if (!vt8500_port)
 		return -ENOMEM;
 
+	/* calculate the port id */
+	port = find_first_zero_bit(&vt8500_ports_in_use,
+				sizeof(vt8500_ports_in_use));
+	if (port > VT8500_MAX_PORTS)
+		return -ENODEV;
+
+	/* reserve the port id */
+	if (test_and_set_bit(port, &vt8500_ports_in_use)) {
+		/* port already in use - shouldn't really happen */
+		return -EBUSY;
+	}
+
 	vt8500_port->uart.type = PORT_VT8500;
 	vt8500_port->uart.iotype = UPIO_MEM;
 	vt8500_port->uart.mapbase = mmres->start;
 	vt8500_port->uart.irq = irqres->start;
 	vt8500_port->uart.fifosize = 16;
 	vt8500_port->uart.ops = &vt8500_uart_pops;
-	vt8500_port->uart.line = pdev->id;
+	vt8500_port->uart.line = port;
 	vt8500_port->uart.dev = &pdev->dev;
 	vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	vt8500_port->uart.uartclk = 24000000;
@@ -579,7 +602,7 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 		goto err;
 	}
 
-	vt8500_uart_ports[pdev->id] = vt8500_port;
+	vt8500_uart_ports[port] = vt8500_port;
 
 	uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
 
@@ -603,12 +626,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-uart", },
+	{}
+};
+
 static struct platform_driver vt8500_platform_driver = {
 	.probe  = vt8500_serial_probe,
 	.remove = __devexit_p(vt8500_serial_remove),
 	.driver = {
 		.name = "vt8500_serial",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -642,4 +671,4 @@ module_exit(vt8500_serial_exit);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("Driver for vt8500 serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:33 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:33 +1200
Subject: [PATCHv3 4/9] usb: vt8500: Add devicetree support for vt8500-ehci and
 -uhci.
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-5-git-send-email-linux@prisktech.co.nz>

Add devicetree support for vt8500-ehci.
Convert vt8500-uhci to a generic non-pci platform-uhci with
device tree support.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/usb/host/Kconfig         |    4 +-
 drivers/usb/host/ehci-vt8500.c   |   25 ++++--
 drivers/usb/host/uhci-hcd.c      |    5 ++
 drivers/usb/host/uhci-platform.c |  169 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 195 insertions(+), 8 deletions(-)
 create mode 100644 drivers/usb/host/uhci-platform.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index dcfaaa9..d7a6b10 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -450,7 +450,7 @@ config USB_OHCI_LITTLE_ENDIAN
 
 config USB_UHCI_HCD
 	tristate "UHCI HCD (most Intel and VIA) support"
-	depends on USB && (PCI || SPARC_LEON)
+	depends on USB && (PCI || SPARC_LEON || ARCH_VT8500)
 	---help---
 	  The Universal Host Controller Interface is a standard by Intel for
 	  accessing the USB hardware in the PC (which is also called the USB
@@ -468,7 +468,7 @@ config USB_UHCI_HCD
 config USB_UHCI_SUPPORT_NON_PCI_HC
 	bool
 	depends on USB_UHCI_HCD
-	default y if SPARC_LEON
+	default y if (SPARC_LEON  || ARCH_VT8500)
 
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c
index c1eda73..0e1637b 100644
--- a/drivers/usb/host/ehci-vt8500.c
+++ b/drivers/usb/host/ehci-vt8500.c
@@ -16,6 +16,7 @@
  *
  */
 
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
@@ -84,20 +85,23 @@ static const struct hc_driver vt8500_ehci_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static u64 wmt_ehci_dma_mask = DMA_BIT_MASK(32);
+
 static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
+	int irq;
 	int ret;
 
 	if (usb_disabled())
 		return -ENODEV;
 
-	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
-		pr_debug("resource[1] is not IORESOURCE_IRQ");
-		return -ENOMEM;
-	}
+	/* devicetree created devices don't specify a dma mask */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &wmt_ehci_dma_mask;
+
 	hcd = usb_create_hcd(&vt8500_ehci_hc_driver, &pdev->dev, "VT8500");
 	if (!hcd)
 		return -ENOMEM;
@@ -134,8 +138,9 @@ static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 
 	ehci_reset(ehci);
 
-	ret = usb_add_hcd(hcd, pdev->resource[1].start,
-			  IRQF_SHARED);
+	irq = platform_get_irq(pdev, 0);
+
+	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret == 0) {
 		platform_set_drvdata(pdev, hcd);
 		return ret;
@@ -162,6 +167,11 @@ static int vt8500_ehci_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id vt8500_ehci_ids[] = {
+	{ .compatible = "via,vt8500-ehci", },
+	{}
+};
+
 static struct platform_driver vt8500_ehci_driver = {
 	.probe		= vt8500_ehci_drv_probe,
 	.remove		= vt8500_ehci_drv_remove,
@@ -169,7 +179,10 @@ static struct platform_driver vt8500_ehci_driver = {
 	.driver = {
 		.name	= "vt8500-ehci",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(vt8500_ehci_ids),
 	}
 };
 
 MODULE_ALIAS("platform:vt8500-ehci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index e4db350..5da5c99 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -846,6 +846,11 @@ static const char hcd_name[] = "uhci_hcd";
 #define PLATFORM_DRIVER		uhci_grlib_driver
 #endif
 
+#ifdef CONFIG_ARCH_VT8500
+#include "uhci-platform.c"
+#define PLATFORM_DRIVER		uhci_platform_driver
+#endif
+
 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
 #error "missing bus glue for uhci-hcd"
 #endif
diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
new file mode 100644
index 0000000..35ca094
--- /dev/null
+++ b/drivers/usb/host/uhci-platform.c
@@ -0,0 +1,169 @@
+/*
+ * Generic UHCI HCD (Host Controller Driver) for Platform Devices
+ *
+ * Copyright (c) 2011 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This file is based on uhci-grlib.c
+ * (C) Copyright 2004-2007 Alan Stern, stern at rowland.harvard.edu
+ */
+
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static int uhci_platform_init(struct usb_hcd *hcd)
+{
+	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+	uhci->rh_numports = uhci_count_ports(hcd);
+
+	/* Set up pointers to to generic functions */
+	uhci->reset_hc = uhci_generic_reset_hc;
+	uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc;
+
+	/* No special actions need to be taken for the functions below */
+	uhci->configure_hc = NULL;
+	uhci->resume_detect_interrupts_are_broken = NULL;
+	uhci->global_suspend_mode_is_broken = NULL;
+
+	/* Reset if the controller isn't already safely quiescent. */
+	check_and_reset_hc(uhci);
+	return 0;
+}
+
+static const struct hc_driver uhci_platform_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "Generic UHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct uhci_hcd),
+
+	/* Generic hardware linkage */
+	.irq =                  uhci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/* Basic lifecycle operations */
+	.reset =                uhci_platform_init,
+	.start =                uhci_start,
+#ifdef CONFIG_PM
+	.pci_suspend =          NULL,
+	.pci_resume =           NULL,
+	.bus_suspend =          uhci_rh_suspend,
+	.bus_resume =           uhci_rh_resume,
+#endif
+	.stop =                 uhci_stop,
+
+	.urb_enqueue =          uhci_urb_enqueue,
+	.urb_dequeue =          uhci_urb_dequeue,
+
+	.endpoint_disable =     uhci_hcd_endpoint_disable,
+	.get_frame_number =     uhci_hcd_get_frame_number,
+
+	.hub_status_data =      uhci_hub_status_data,
+	.hub_control =          uhci_hub_control,
+};
+
+static u64 platform_uhci_dma_mask = DMA_BIT_MASK(32);
+
+static int __devinit uhci_hcd_platform_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd;
+	struct uhci_hcd *uhci;
+	struct resource *res;
+	int ret;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &platform_uhci_dma_mask;
+
+	hcd = usb_create_hcd(&uhci_platform_hc_driver, &pdev->dev,
+				pdev->name);
+	if (!hcd)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		pr_err("%s: request_mem_region failed\n", __func__);
+		ret = -EBUSY;
+		goto err_rmr;
+	}
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		pr_err("%s: ioremap failed\n", __func__);
+		ret = -ENOMEM;
+		goto err_irq;
+	}
+	uhci = hcd_to_uhci(hcd);
+
+	uhci->regs = hcd->regs;
+
+	ret = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED |
+								IRQF_SHARED);
+	if (ret)
+		goto err_uhci;
+
+	return 0;
+
+err_uhci:
+	iounmap(hcd->regs);
+err_irq:
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+	usb_put_hcd(hcd);
+
+	return ret;
+}
+
+static int uhci_hcd_platform_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more.  This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel.  Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_hcd_platform_shutdown(struct platform_device *op)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+	uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+static const struct of_device_id platform_uhci_ids[] = {
+	{ .compatible = "platform-uhci", },
+	{}
+};
+
+static struct platform_driver uhci_platform_driver = {
+	.probe          = uhci_hcd_platform_probe,
+	.remove         = uhci_hcd_platform_remove,
+	.shutdown       = uhci_hcd_platform_shutdown,
+	.driver = {
+		.name = "platform-uhci",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(platform_uhci_ids),
+	},
+};
+
+MODULE_ALIAS("platform:platform-uhci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, platform_uhci_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:31 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:31 +1200
Subject: [PATCHv3 2/9] rtc: vt8500: Add devicetree support for vt8500-rtc
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-3-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/rtc/rtc-vt8500.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-vt8500.c b/drivers/rtc/rtc-vt8500.c
index 9e94fb1..07bf193 100644
--- a/drivers/rtc/rtc-vt8500.c
+++ b/drivers/rtc/rtc-vt8500.c
@@ -23,6 +23,7 @@
 #include <linux/bcd.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 /*
  * Register definitions
@@ -302,12 +303,18 @@ static int __devexit vt8500_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-rtc", },
+	{}
+};
+
 static struct platform_driver vt8500_rtc_driver = {
 	.probe		= vt8500_rtc_probe,
 	.remove		= __devexit_p(vt8500_rtc_remove),
 	.driver		= {
 		.name	= "vt8500-rtc",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -315,5 +322,5 @@ module_platform_driver(vt8500_rtc_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:vt8500-rtc");
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:30 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:30 +1200
Subject: [PATCHv3 1/9] arm: vt8500: Add device tree files for VIA/Wondermedia
 SoC's
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-2-git-send-email-linux@prisktech.co.nz>

Add device tree files for VT8500, WM8505 and WM8650 SoC's and
reference boards.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/boot/dts/vt8500-bv07.dts |   31 +++++++++
 arch/arm/boot/dts/vt8500.dtsi     |  100 +++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8505-ref.dts  |   31 +++++++++
 arch/arm/boot/dts/wm8505.dtsi     |  126 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8650-mid.dts  |   31 +++++++++
 arch/arm/boot/dts/wm8650.dtsi     |  138 +++++++++++++++++++++++++++++++++++++
 6 files changed, 457 insertions(+)
 create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505-ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650-mid.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi

diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 0000000..339a664
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,31 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+	model = "Benign BV07 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 0000000..78571d5
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,100 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "via,vt8500";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc>;
+
+		intc: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "via,vt8500-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d800e400 {
+			compatible = "via,vt8500-fb";
+			reg = <0xd800e400 0x400>;
+			interrupts = <12>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 0000000..fcd9836
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+	model = "Wondermedia WM8505 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <32>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 0000000..64a3d7f
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,126 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8505";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8505-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007100 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007100 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007300 {
+			compatible = "platform-uhci";
+			reg = <0xd8007300 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+		};
+
+		uart at d8370000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8370000 0x1040>;
+			interrupts = <31>;
+		};
+
+		uart at d8380000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8380000 0x1040>;
+			interrupts = <30>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 0000000..d37dbf0
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+	model = "Wondermedia WM8650-MID Tablet";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 0000000..e4ca840
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,138 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8650";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8650-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ref25: ref25M {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <25000000>;
+				};
+
+				plla: plla {
+					#clock-cells = <0>;
+					compatible = "wm,wm8650-pll-clock";
+					clocks = <&ref25>;
+					reg = <0x200>;
+				};
+
+				pllb: pllb {
+					#clock-cells = <0>;
+					compatible = "wm,wm8650-pll-clock";
+					clocks = <&ref25>;
+					reg = <0x204>;
+				};
+
+				arm: arm {
+					#clock-cells = <0>;
+					compatible = "via,vt8500-device-clock";
+					clocks = <&plla>;
+					divisor-reg = <0x300>;
+				};
+
+				sdhc: sdhc {
+					#clock-cells = <0>;
+					compatible = "via,vt8500-device-clock";
+					clocks = <&pllb>;
+					divisor-reg = <0x328>;
+					divisor-mask = <0x3f>;
+					enable-reg = <0x254>;
+					enable-bit = <18>;
+				};
+			};
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:29 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:29 +1200
Subject: [PATCHv3 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
Message-ID: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>

This patchset updates arch-vt8500 to devicetree and removes all the old-style
code. Support for WM8650 has also been added.

Example dts/dtsi files are given for the three currently supported models.

Major changes:

GPIO code has been converted to a platform_device and rewritten as WM8505
support was broken. Add support for WM8650 gpio controller.

UHCI support was missing. Added this as a generic non-pci uhci controller as
it doesn't require anything special. Should be usable by any system that doesn't
have special requirements to get the UHCI controller working.

Framebuffer code patched to support WM8650. The bindings for this are of concern
but there doesn't seem to be a formalized binding yet. This patch is based off
Sascha Hauer's current patch on the dri-devel mailing list and should be easily
patched out when its finalized.

Patchset based on Arnd's arm-soc/for-next branch.


Could I get this reviewed, hopefully for inclusion into v3.7.

Regards
Tony Prisk

Changes
v2:
Cleanup style/formatting errors
Removed erroneous commit message about GPIO not being converted to devicetree
Corrected arch-vt8500/irq.c header to correct filename
Changed GPIO driver to use module_platform_driver()
Renamed vt8500_gpio_bank_regs -> vt8500_gpio_bank_regoffsets
Changed vt8500_gpio_bank_regoffset fields to unsigned int
Changed bit-setting code to use BIT() macro
Removed of_find_compatible() and use pdev->dev.of_node in _probe()
Removed regoff field and related code - leftover from old design
Added kerneldoc regarding struct vt8500_gpio_bank_regoffsets fields
Update MODULE_LICENSE on all platform devices to "GPL v2" to match their headers
Renamed dts board files to clarify product names

v3:
Corrected serial driver issue after porting to device tree. pdev->id no longer
valid.
Corrected irq.c to properly initialize slaved interrupt controller.
Updated framebuffer drivers to use phandles for display node.
Corrected dts definitions for updated framebuffer driver.
EHCI/UHCI patch (Patch 4/9) already in -next via usb-next tree.

Included common clock frame support.
Added initialization code to arch/arm/mach-vt8500/vt8500.c for clocks.
Updated wm8650.dtsi to include basic clocks.


Tony Prisk (9):
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  rtc: vt8500: Add devicetree support for vt8500-rtc
  serial: vt8500: Add devicetree support for vt8500-serial
  usb: vt8500: Add devicetree support for vt8500-ehci and -uhci.
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  arm: vt8500: gpio: Devicetree support for arch-vt8500
  arm: vt8500: clk: Add Common Clock Framework support

 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 +
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +
 Documentation/devicetree/bindings/clock/vt8500.txt |   72 +++
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 +
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 +
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   48 ++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 +
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   22 +
 arch/arm/Kconfig                                   |    5 +
 arch/arm/boot/dts/vt8500-bv07.dts                  |   31 ++
 arch/arm/boot/dts/vt8500.dtsi                      |  100 ++++
 arch/arm/boot/dts/wm8505-ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8505.dtsi                      |  126 +++++
 arch/arm/boot/dts/wm8650-mid.dts                   |   31 ++
 arch/arm/boot/dts/wm8650.dtsi                      |  138 ++++++
 arch/arm/mach-vt8500/Kconfig                       |   72 +--
 arch/arm/mach-vt8500/Makefile                      |    9 +-
 arch/arm/mach-vt8500/bv07.c                        |   80 ----
 arch/arm/mach-vt8500/common.h                      |   28 ++
 arch/arm/mach-vt8500/devices-vt8500.c              |   91 ----
 arch/arm/mach-vt8500/devices-wm8505.c              |   99 ----
 arch/arm/mach-vt8500/devices.c                     |  270 -----------
 arch/arm/mach-vt8500/devices.h                     |   88 ----
 arch/arm/mach-vt8500/gpio.c                        |  240 ----------
 arch/arm/mach-vt8500/include/mach/restart.h        |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h    |   88 ----
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h    |   79 ----
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h    |  115 -----
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h    |   78 ---
 arch/arm/mach-vt8500/irq.c                         |  209 +++++----
 arch/arm/mach-vt8500/restart.c                     |   54 ---
 arch/arm/mach-vt8500/timer.c                       |   67 ++-
 arch/arm/mach-vt8500/vt8500.c                      |  196 ++++++++
 arch/arm/mach-vt8500/wm8505_7in.c                  |   79 ----
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-vt8500.c                           |  496 ++++++++++++++++++++
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-vt8500.c                         |  313 ++++++++++++
 drivers/rtc/rtc-vt8500.c                           |    9 +-
 drivers/tty/serial/vt8500_serial.c                 |   37 +-
 drivers/usb/host/Kconfig                           |    4 +-
 drivers/usb/host/ehci-vt8500.c                     |   25 +-
 drivers/usb/host/uhci-hcd.c                        |    5 +
 drivers/usb/host/uhci-platform.c                   |  169 +++++++
 drivers/video/Kconfig                              |    6 +-
 drivers/video/vt8500lcdfb.c                        |   79 +++-
 drivers/video/wm8505fb.c                           |   97 +++-
 drivers/video/wmt_ge_rops.c                        |    9 +-
 55 files changed, 2384 insertions(+), 1581 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
 create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505-ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650-mid.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c
 create mode 100644 drivers/clk/clk-vt8500.c
 create mode 100644 drivers/gpio/gpio-vt8500.c
 create mode 100644 drivers/usb/host/uhci-platform.c

-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:37 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:37 +1200
Subject: [PATCHv3 8/9] arm: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-9-git-send-email-linux@prisktech.co.nz>

Converted the existing arch-vt8500 gpio to a platform_device.
Added support for WM8505 and WM8650 GPIO controllers.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/gpio/Kconfig       |    6 +
 drivers/gpio/Makefile      |    1 +
 drivers/gpio/gpio-vt8500.c |  313 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 320 insertions(+)
 create mode 100644 drivers/gpio/gpio-vt8500.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 542f0c0..3c8897a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,12 @@ config GPIO_STA2X11
 	  Say yes here to support the STA2x11/ConneXt GPIO device.
 	  The GPIO module has 128 GPIO pins with alternate functions.
 
+config GPIO_VT8500
+	bool "VIA/Wondermedia SoC GPIO Support"
+	depends on ARCH_VT8500
+	help
+	  Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
 config GPIO_XILINX
 	bool "Xilinx GPIO support"
 	depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0f55662..2c014b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500)	+= gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)	+= gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
new file mode 100644
index 0000000..19b12d9
--- /dev/null
+++ b/drivers/gpio/gpio-vt8500.c
@@ -0,0 +1,313 @@
+/* linux/arch/arm/mach-vt8500/gpio.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ * Based on gpio.c:
+ * - Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+
+/*
+	We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
+	by one set of registers (although not all may be valid).
+
+	Because different SoC's have different register offsets, we pass the
+	register offsets as data in vt8500_gpio_dt_ids[].
+
+	A value of NO_REG is used to indicate that this register is not
+	supported. Only used for ->en at the moment.
+*/
+
+#define NO_REG	0xFFFF
+
+/*
+ * struct vt8500_gpio_bank_regoffsets
+ * @en: offset to enable register of the bank
+ * @dir: offset to direction register of the bank
+ * @data_out: offset to the data out register of the bank
+ * @data_in: offset to the data in register of the bank
+ * @ngpio: highest valid pin in this bank
+ */
+
+struct vt8500_gpio_bank_regoffsets {
+	unsigned int	en;
+	unsigned int	dir;
+	unsigned int	data_out;
+	unsigned int	data_in;
+	unsigned char	ngpio;
+};
+
+struct vt8500_gpio_data {
+	unsigned int				num_banks;
+	struct vt8500_gpio_bank_regoffsets	banks[];
+};
+
+#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)		\
+{								\
+	.en = __en,						\
+	.dir = __dir,						\
+	.data_out = __out,					\
+	.data_in = __in,					\
+	.ngpio = __ngpio,					\
+}
+
+static struct vt8500_gpio_data vt8500_data = {
+	.num_banks	= 7,
+	.banks	= {
+		VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
+		VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
+		VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
+		VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
+		VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
+		VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
+		VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
+	},
+};
+
+static struct vt8500_gpio_data wm8505_data = {
+	.num_banks	= 10,
+	.banks	= {
+		VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
+		VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
+		VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
+		VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
+		VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
+		VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
+		VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
+		VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
+		VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
+		VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+	},
+};
+
+/*
+ * No information about which bits are valid so we just make
+ * them all available until its figured out.
+ */
+static struct vt8500_gpio_data wm8650_data = {
+	.num_banks	= 9,
+	.banks	= {
+		VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
+		VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
+		VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
+		VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
+		VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
+		VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
+		VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
+		VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
+		VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+	},
+};
+
+struct vt8500_gpio_chip {
+	struct gpio_chip		chip;
+
+	const struct vt8500_gpio_bank_regoffsets *regs;
+	void __iomem	*base;
+};
+
+
+#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
+
+static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	unsigned val;
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return 0;
+
+	val = readl(vt8500_chip->base + vt8500_chip->regs->en);
+	val |= BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en);
+
+	return 0;
+}
+
+static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+	unsigned val;
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return;
+
+	val = readl(vt8500_chip->base + vt8500_chip->regs->en);
+	val &= ~BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->en);
+}
+
+static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir);
+	val &= ~BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	return 0;
+}
+
+static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->dir);
+	val |= BIT(offset);
+	writel(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	if (value) {
+		val = readl(vt8500_chip->base + vt8500_chip->regs->data_out);
+		val |= BIT(offset);
+		writel(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+	}
+	return 0;
+}
+
+static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	return (readl(vt8500_chip->base + vt8500_chip->regs->data_in) >>
+								offset) & 1;
+}
+
+static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	unsigned val = readl(vt8500_chip->base + vt8500_chip->regs->data_out);
+	if (value)
+		val |= BIT(offset);
+	else
+		val &= ~BIT(offset);
+
+	writel(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+}
+
+static int vt8500_of_xlate(struct gpio_chip *gc,
+			    const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	/* bank if specificed in gpiospec->args[0] */
+	if (flags)
+		*flags = gpiospec->args[2];
+
+	return gpiospec->args[1];
+}
+
+static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
+				const struct vt8500_gpio_data *data)
+{
+	struct vt8500_gpio_chip *vtchip;
+	struct gpio_chip *chip;
+	int i;
+	int pin_cnt = 0;
+
+	vtchip = devm_kzalloc(&pdev->dev,
+			sizeof(struct vt8500_gpio_chip) * data->num_banks,
+			GFP_KERNEL);
+	if (!vtchip) {
+		pr_err("%s: failed to allocate chip memory\n", __func__);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < data->num_banks; i++) {
+		vtchip[i].base = base;
+		vtchip[i].regs = &data->banks[i];
+
+		chip = &vtchip[i].chip;
+
+		chip->of_xlate = vt8500_of_xlate;
+		chip->of_gpio_n_cells = 3;
+		chip->of_node = pdev->dev.of_node;
+
+		chip->request = vt8500_gpio_request;
+		chip->free = vt8500_gpio_free;
+		chip->direction_input = vt8500_gpio_direction_input;
+		chip->direction_output = vt8500_gpio_direction_output;
+		chip->get = vt8500_gpio_get_value;
+		chip->set = vt8500_gpio_set_value;
+		chip->can_sleep = 0;
+		chip->base = pin_cnt;
+		chip->ngpio = data->banks[i].ngpio;
+
+		pin_cnt += data->banks[i].ngpio;
+
+		gpiochip_add(chip);
+	}
+	return 0;
+}
+
+static struct of_device_id vt8500_gpio_dt_ids[] = {
+	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
+	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
+	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
+	{ /* Sentinel */ },
+};
+
+static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
+{
+	void __iomem *gpio_base;
+	struct device_node *np;
+	const struct of_device_id *of_id =
+				of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -ENODEV;
+	}
+
+	np = pdev->dev.of_node;
+	if (!np) {
+		dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
+		return -EFAULT;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(&pdev->dev, "Unable to map GPIO registers\n");
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+	return 0;
+}
+
+static struct platform_driver vt8500_gpio_driver = {
+	.probe		= vt8500_gpio_probe,
+	.driver		= {
+		.name	= "vt8500-gpio",
+		.owner	= THIS_MODULE,
+		.of_match_table = vt8500_gpio_dt_ids,
+	},
+};
+
+module_platform_driver(vt8500_gpio_driver);
+
+MODULE_DESCRIPTION("VT8500 GPIO Driver");
+MODULE_AUTHOR("Tony Prisk <linux at prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:34 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:34 +1200
Subject: [PATCHv3 5/9] video: vt8500: Add devicetree support for vt8500-fb and
 wm8505-fb
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-6-git-send-email-linux@prisktech.co.nz>

Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
tree bindings.
Small change in wm8505-fb.c to support WM8650 framebuffer color
format.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/Kconfig       |    6 +--
 drivers/video/vt8500lcdfb.c |   79 ++++++++++++++++++++++++++++++-----
 drivers/video/wm8505fb.c    |   97 ++++++++++++++++++++++++++++++++++++-------
 drivers/video/wmt_ge_rops.c |    9 +++-
 4 files changed, 161 insertions(+), 30 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..b66d951 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1788,7 +1788,7 @@ config FB_AU1200
 
 config FB_VT8500
 	bool "VT8500 LCD Driver"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
@@ -1797,11 +1797,11 @@ config FB_VT8500
 
 config FB_WM8505
 	bool "WM8505 frame buffer support"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
-	  This is the framebuffer driver for WonderMedia WM8505
+	  This is the framebuffer driver for WonderMedia WM8505/WM8650
 	  integrated LCD controller.
 
 source "drivers/video/geode/Kconfig"
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6e..758e359 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -35,6 +35,13 @@
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
 
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
+#endif
+
+
 #define to_vt8500lcd_info(__info) container_of(__info, \
 						struct vt8500lcd_info, fb)
 
@@ -270,15 +277,21 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 {
 	struct vt8500lcd_info *fbi;
 	struct resource *res;
-	struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
 	void *addr;
 	int irq, ret;
 
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
+
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+			+ sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -333,9 +346,45 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
+	np = of_parse_phandle(pdev->dev.of_node, "via,display", 0);
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.fix.smem_start	= fb_mem_phys;
+	fbi->fb.fix.smem_len	= fb_mem_len;
+	fbi->fb.screen_base	= fb_mem_virt;
 
 	fbi->palette_size	= PAGE_ALIGN(512);
 	fbi->palette_cpu	= dma_alloc_coherent(&pdev->dev,
@@ -370,10 +419,11 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_irq;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
 
 	ret = vt8500lcd_set_par(&fbi->fb);
 	if (ret) {
@@ -448,12 +498,18 @@ static int __devexit vt8500lcd_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id via_dt_ids[] = {
+	{ .compatible = "via,vt8500-fb", },
+	{}
+};
+
 static struct platform_driver vt8500lcd_driver = {
 	.probe		= vt8500lcd_probe,
 	.remove		= __devexit_p(vt8500lcd_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "vt8500-lcd",
+		.of_match_table = of_match_ptr(via_dt_ids),
 	},
 };
 
@@ -461,4 +517,5 @@ module_platform_driver(vt8500lcd_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, via_dt_ids);
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd..d4448b0 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/wait.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
 
 #include <mach/vt8500fb.h>
 
@@ -59,8 +62,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
 
-	/* Set in-memory picture format to RGB 32bpp */
-	writel(0x1c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
+	/*
+	 * Set in-memory picture format to RGB
+	 * 0x31C sets the correct color mode (RGB565) for WM8650
+	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
+	 */
+	writel(0x31c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
 	writel(1,		       fbi->regbase + WMT_GOVR_COLORSPACE1);
 
 	/* Virtual buffer size */
@@ -127,6 +134,18 @@ static int wm8505fb_set_par(struct fb_info *info)
 		info->var.blue.msb_right = 0;
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		info->fix.line_length = info->var.xres_virtual << 2;
+	} else if (info->var.bits_per_pixel == 16) {
+		info->var.red.offset = 11;
+		info->var.red.length = 5;
+		info->var.red.msb_right = 0;
+		info->var.green.offset = 5;
+		info->var.green.length = 6;
+		info->var.green.msb_right = 0;
+		info->var.blue.offset = 0;
+		info->var.blue.length = 5;
+		info->var.blue.msb_right = 0;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		info->fix.line_length = info->var.xres_virtual << 1;
 	}
 
 	wm8505fb_set_timing(info);
@@ -246,16 +265,20 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 	struct wm8505fb_info	*fbi;
 	struct resource		*res;
 	void			*addr;
-	struct vt8500fb_platform_data *pdata;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
 
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
+			sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -305,21 +328,58 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+	np = of_parse_phandle(pdev->dev.of_node, "via,display", 0);
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
 
 	fbi->fb.var.nonstd		= 0;
 	fbi->fb.var.activate		= FB_ACTIVATE_NOW;
 
 	fbi->fb.var.height		= -1;
 	fbi->fb.var.width		= -1;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
-	fbi->fb.screen_size	= pdata->video_mem_len;
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
+
+	fbi->fb.fix.smem_start		= fb_mem_phys;
+	fbi->fb.fix.smem_len		= fb_mem_len;
+	fbi->fb.screen_base		= fb_mem_virt;
+	fbi->fb.screen_size		= fb_mem_len;
 
 	if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
 		dev_err(&pdev->dev, "Failed to allocate color map\n");
@@ -395,12 +455,18 @@ static int __devexit wm8505fb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,wm8505-fb", },
+	{}
+};
+
 static struct platform_driver wm8505fb_driver = {
 	.probe		= wm8505fb_probe,
 	.remove		= __devexit_p(wm8505fb_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -408,4 +474,5 @@ module_platform_driver(wm8505fb_driver);
 
 MODULE_AUTHOR("Ed Spiridonov <edo.rus at gmail.com>");
 MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 55be386..ba025b4 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -158,12 +158,18 @@ static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,prizm-ge-rops", },
+	{ /* sentinel */ }
+};
+
 static struct platform_driver wmt_ge_rops_driver = {
 	.probe		= wmt_ge_rops_probe,
 	.remove		= __devexit_p(wmt_ge_rops_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "wmt_ge_rops",
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -172,4 +178,5 @@ module_platform_driver(wmt_ge_rops_driver);
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com");
 MODULE_DESCRIPTION("Accelerators for raster operations using "
 		   "WonderMedia Graphics Engine");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:38 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:38 +1200
Subject: [PATCHv3 9/9] arm: vt8500: clk: Add Common Clock Framework support
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-10-git-send-email-linux@prisktech.co.nz>

This patch adds common clock framework support for arch-vt8500.
Support for PLL and device clocks on VT8500, WM8505 and WM8650
are included.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/clk/Makefile     |    1 +
 drivers/clk/clk-vt8500.c |  496 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 497 insertions(+)
 create mode 100644 drivers/clk/clk-vt8500.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..42fb173 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
new file mode 100644
index 0000000..524c479
--- /dev/null
+++ b/drivers/clk/clk-vt8500.c
@@ -0,0 +1,496 @@
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+/* All clocks share the same lock as none can be changed concurrently */
+static DEFINE_SPINLOCK(_lock);
+
+struct clk_device {
+	struct clk_hw	hw;
+	void __iomem	*div_reg;
+	unsigned int	div_mask;
+	void __iomem	*en_reg;
+	int		en_bit;
+	spinlock_t	*lock;
+};
+
+/*
+ * Add new PLL_TYPE_x definitions here as required. Use the first known model
+ * to support the new type as the name.
+ * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
+ * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
+ */
+
+#define PLL_TYPE_VT8500		0
+#define PLL_TYPE_WM8650		1
+
+struct clk_pll {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	spinlock_t	*lock;
+	int		type;
+};
+
+static void __iomem *pmc_base;
+
+#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
+
+
+#define VT8500_PMC_BUSY_MASK		0x18
+
+static void vt8500_pmc_wait_busy(void)
+{
+	while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
+		cpu_relax();
+}
+
+static void vt8500_dclk_endisable(struct clk_hw *hw, int enable)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 en_val;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	en_val = readl(cdev->en_reg);
+
+	if (enable)
+		en_val |= BIT(cdev->en_bit);
+	else
+		en_val &= ~BIT(cdev->en_bit);
+
+	writel(en_val, cdev->en_reg);
+
+	spin_unlock_irqrestore(cdev->lock, flags);
+}
+
+static int vt8500_dclk_enable(struct clk_hw *hw)
+{
+	vt8500_dclk_endisable(hw, 1);
+	return 0;
+}
+
+static void vt8500_dclk_disable(struct clk_hw *hw)
+{
+	vt8500_dclk_endisable(hw, 0);
+}
+
+static int vt8500_dclk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
+
+	return en_val ? 1 : 0;
+}
+
+static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 div = readl(cdev->div_reg) & cdev->div_mask;
+
+	/* Special case for SDMMC devices */
+	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
+		div = 64 * (div & 0x1f);
+
+	/* div == 0 is actually the highest divisor */
+	if (div == 0)
+		div = (cdev->div_mask + 1);
+
+	return parent_rate / div;
+}
+
+static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	u32 divisor = rate / *prate;
+
+	return *prate / divisor;
+}
+
+static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 divisor = rate / parent_rate;
+	unsigned long flags = 0;
+
+	if (divisor == cdev->div_mask + 1)
+		divisor = 0;
+
+	if (divisor > cdev->div_mask) {
+		pr_err("%s: invalid divisor for clock\n", __func__);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	vt8500_pmc_wait_busy();
+	writel(divisor, cdev->div_reg);
+	vt8500_pmc_wait_busy();
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	return 0;
+}
+
+
+static const struct clk_ops vt8500_gated_clk_ops = {
+	.enable = vt8500_dclk_enable,
+	.disable = vt8500_dclk_disable,
+	.is_enabled = vt8500_dclk_is_enabled,
+};
+
+static const struct clk_ops vt8500_divisor_clk_ops = {
+	.round_rate = vt8500_dclk_round_rate,
+	.set_rate = vt8500_dclk_set_rate,
+	.recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+static const struct clk_ops vt8500_gated_divisor_clk_ops = {
+	.enable = vt8500_dclk_enable,
+	.disable = vt8500_dclk_disable,
+	.is_enabled = vt8500_dclk_is_enabled,
+	.round_rate = vt8500_dclk_round_rate,
+	.set_rate = vt8500_dclk_set_rate,
+	.recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+#define CLK_INIT_GATED			BIT(0)
+#define CLK_INIT_DIVISOR		BIT(1)
+#define CLK_INIT_GATED_DIVISOR		(CLK_INIT_DIVISOR | CLK_INIT_GATED)
+
+static __init void vtwm_device_clk_init(struct device_node *node)
+{
+	u32 en_reg, div_reg;
+	struct clk *clk;
+	struct clk_device *dev_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+	int clk_init_flags = 0;
+
+	dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
+	if (WARN_ON(!dev_clk))
+		return;
+
+	dev_clk->lock = &_lock;
+
+	rc = of_property_read_u32(node, "enable-reg", &en_reg);
+	if (!rc) {
+		dev_clk->en_reg = pmc_base + en_reg;
+		rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
+		if (rc) {
+			pr_err("%s: enable-bit property required for gated clock\n",
+								__func__);
+			return;
+		}
+		clk_init_flags |= CLK_INIT_GATED;
+	}
+
+	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
+	if (!rc) {
+		dev_clk->div_reg = pmc_base + div_reg;
+		/*
+		 * use 0x1f as the default mask since it covers
+		 * almost all the clocks and reduces dts properties
+		 */
+		dev_clk->div_mask = 0x1f;
+
+		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
+		clk_init_flags |= CLK_INIT_DIVISOR;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	switch (clk_init_flags) {
+	case CLK_INIT_GATED:
+		init.ops = &vt8500_gated_clk_ops;
+		break;
+	case CLK_INIT_DIVISOR:
+		init.ops = &vt8500_divisor_clk_ops;
+		break;
+	case CLK_INIT_GATED_DIVISOR:
+		init.ops = &vt8500_gated_divisor_clk_ops;
+		break;
+	default:
+		pr_err("%s: Invalid clock description in device tree\n",
+								__func__);
+		kfree(dev_clk);
+		return;
+	}
+
+	init.name = clk_name;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	dev_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &dev_clk->hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(dev_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* PLL clock related functions */
+
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Helper macros for PLL_VT8500 */
+#define VT8500_PLL_MUL(x)	((x & 0x1F) << 1)
+#define VT8500_PLL_DIV(x)	((x & 0x100) ? 1 : 2)
+
+#define VT8500_BITS_TO_FREQ(r, m, d)					\
+				((r / d) * m)
+
+#define VT8500_BITS_TO_VAL(m, d)					\
+				((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
+
+/* Helper macros for PLL_WM8650 */
+#define WM8650_PLL_MUL(x)	(x & 0x3FF)
+#define WM8650_PLL_DIV(x)	(((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
+
+#define WM8650_BITS_TO_FREQ(r, m, d1, d2)				\
+				(r * m / (d1 * (1 << d2)))
+
+#define WM8650_BITS_TO_VAL(m, d1, d2)					\
+				((d2 << 13) | (d1 << 10) | (m & 0x3FF))
+
+
+static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *prediv)
+{
+	unsigned long tclk;
+
+	/* sanity check */
+	if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
+		pr_err("%s: requested rate out of range\n", __func__);
+		*multiplier = 0;
+		*prediv = 1;
+		return;
+	}
+	if (rate <= parent_rate * 31)
+		/* use the prediv to double the resolution */
+		*prediv = 2;
+	else
+		*prediv = 1;
+
+	*multiplier = rate / (parent_rate / *prediv);
+	tclk = (parent_rate / *prediv) * *multiplier;
+
+	if (tclk != rate)
+		pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
+								rate, tclk);
+}
+
+static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+{
+	u32 mul, div1, div2;
+	u32 best_mul, best_div1, best_div2;
+	unsigned long tclk, rate_err, best_err;
+
+	best_err = (unsigned long)-1;
+
+	/* Find the closest match (lower or equal to requested) */
+	for (div1 = 5; div1 >= 3; div1--)
+		for (div2 = 3; div2 >= 0; div2--)
+			for (mul = 3; mul <= 1023; mul++) {
+				tclk = parent_rate * mul / (div1 * (1 << div2));
+				if (tclk > rate)
+					continue;
+				/* error will always be +ve */
+				rate_err = rate - tclk;
+				if (rate_err == 0) {
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
+					return;
+				}
+
+				if (rate_err < best_err) {
+					best_err = rate_err;
+					best_mul = mul;
+					best_div1 = div1;
+					best_div2 = div2;
+				}
+			}
+
+	/* if we got here, it wasn't an exact match */
+	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
+							rate - best_err);
+	*multiplier = mul;
+	*divisor1 = div1;
+	*divisor2 = div2;
+}
+
+static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mul, div1, div2;
+	u32 pll_val;
+	unsigned long flags = 0;
+
+	/* sanity check */
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
+		pll_val = VT8500_BITS_TO_VAL(mul, div1);
+		break;
+	case PLL_TYPE_WM8650:
+		wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
+		pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
+		break;
+	default:
+		pr_err("%s: invalid pll type\n", __func__);
+		return 0;
+	}
+
+	spin_lock_irqsave(pll->lock, flags);
+
+	vt8500_pmc_wait_busy();
+	writel(pll_val, pll->reg);
+	vt8500_pmc_wait_busy();
+
+	spin_unlock_irqrestore(pll->lock, flags);
+
+	return 0;
+}
+
+static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mul, div1, div2;
+	long round_rate;
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		vt8500_find_pll_bits(rate, *prate, &mul, &div1);
+		round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
+		break;
+	case PLL_TYPE_WM8650:
+		wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
+		round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
+		break;
+	default:
+		round_rate = 0;
+	}
+
+	return round_rate;
+}
+
+static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 pll_val = readl(pll->reg);
+	unsigned long pll_freq;
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
+		pll_freq /= VT8500_PLL_DIV(pll_val);
+		break;
+	case PLL_TYPE_WM8650:
+		pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
+		pll_freq /= WM8650_PLL_DIV(pll_val);
+		break;
+	default:
+		pll_freq = 0;
+	}
+
+	return pll_freq;
+}
+
+const struct clk_ops vtwm_pll_ops = {
+	.round_rate = vtwm_pll_round_rate,
+	.set_rate = vtwm_pll_set_rate,
+	.recalc_rate = vtwm_pll_recalc_rate,
+};
+
+static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
+{
+	u32 reg;
+	struct clk *clk;
+	struct clk_pll *pll_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	rc = of_property_read_u32(node, "reg", &reg);
+	if (WARN_ON(rc))
+		return;
+
+	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+	if (WARN_ON(!pll_clk))
+		return;
+
+	pll_clk->reg = pmc_base + reg;
+	pll_clk->lock = &_lock;
+	pll_clk->type = pll_type;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = &vtwm_pll_ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	pll_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &pll_clk->hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(pll_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* Wrappers for initialization functions */
+
+static void __init vt8500_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
+}
+
+static void __init wm8650_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
+}
+
+static const __initconst struct of_device_id clk_match[] = {
+	{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{ .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
+	{ .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
+	{ .compatible = "via,vt8500-device-clock",
+					.data = vtwm_device_clk_init, },
+	{ /* sentinel */ }
+};
+
+void __init vtwm_clk_init(void __iomem *base)
+{
+	if (!base)
+		return;
+
+	pmc_base = base;
+
+	of_clk_init(clk_match);
+}
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:36 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:36 +1200
Subject: [PATCHv3 7/9] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-8-git-send-email-linux@prisktech.co.nz>

Bindings for gpio, interrupt controller, power management controller,
timer, realtime clock, serial uart, ehci and uhci controllers and
framebuffer controllers used on the arch-vt8500 platform.

Framebuffer binding also specifies a 'display' node which is required
for determining the lcd panel data.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 ++++
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +++++
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 ++++
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 ++++
 Documentation/devicetree/bindings/clock/vt8500.txt |   72 ++++++++++++++++++++
 .../devicetree/bindings/gpio/gpio_vt8500.txt       |   24 +++++++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 ++++
 .../bindings/tty/serial/via,vt8500-uart.txt        |   15 ++++
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 ++++
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 ++++
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   48 +++++++++++++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 ++++
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   22 ++++++
 14 files changed, 300 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt

diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
new file mode 100644
index 0000000..1b3b187
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the VIA VT8500 SoC shall have the following properties:
+Required root node property:
+compatible = "via,vt8500";
+
+Boards with the Wondermedia WM8505 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8505";
+
+Boards with the Wondermedia WM8650 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8650";
+
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
new file mode 100644
index 0000000..0a4ce10
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
@@ -0,0 +1,16 @@
+VIA/Wondermedia VT8500 Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-intc"
+- reg : Should contain 1 register ranges(address and length)
+- #interrupt-cells : should be <1>
+
+Example:
+
+	intc: interrupt-controller at d8140000 {
+		compatible = "via,vt8500-intc";
+		interrupt-controller;
+		reg = <0xd8140000 0x10000>;
+		#interrupt-cells = <1>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
new file mode 100644
index 0000000..521b9c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia VT8500 Power Management Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-pmc"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	pmc at d8130000 {
+		compatible = "via,vt8500-pmc";
+		reg = <0xd8130000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
new file mode 100644
index 0000000..901c73f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+	timer at d8130100 {
+		compatible = "via,vt8500-timer";
+		reg = <0xd8130100 0x28>;
+		interrupts = <36>;
+	};
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
new file mode 100644
index 0000000..a880c70
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -0,0 +1,72 @@
+Device Tree Clock bindings for arch-vt8500
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
+	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
+	"via,vt8500-device-clock" - for a VT/WM device clock
+
+Required properties for PLL clocks:
+- reg : shall be the control register offset from PMC base for the pll clock.
+- clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Required properties for device clocks:
+- clocks : shall be the input parent clock phandle for the clock. This should
+	be a pll output.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+
+Device Clocks
+
+Device clocks are required to have one or both of the following sets of
+properties:
+
+
+Gated device clocks:
+
+Required properties:
+- enable-reg : shall be the register offset from PMC base for the enable
+	register.
+- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
+
+
+Divisor device clocks:
+
+Required property:
+- divisor-reg : shall be the register offset from PMC base for the divisor
+	register.
+Optional property:
+- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
+	if not specified.
+
+
+For example:
+
+ref25: ref25M {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+plla: plla {
+	#clock-cells = <0>;
+	compatible = "wm,wm8650-pll-clock";
+	clocks = <&ref25>;
+	reg = <0x200>;
+};
+
+sdhc: sdhc {
+	#clock-cells = <0>;
+	compatible = "via,vt8500-device-clock";
+	clocks = <&pllb>;
+	divisor-reg = <0x328>;
+	divisor-mask = <0x3f>;
+	enable-reg = <0x254>;
+	enable-bit = <18>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
new file mode 100644
index 0000000..1a122bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+	or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+	1) bank
+	2) pin number
+	3) flags
+
+Example:
+
+	gpio: gpio-controller at d8110000 {
+		compatible = "via,vt8500-gpio";
+		gpio-controller;
+		reg = <0xd8110000 0x10000>;
+		#gpio-cells = <3>;
+	};
+
+	vibrate {
+		gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+	};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 0000000..3c0484c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+	rtc at d8100000 {
+		compatible = "via,vt8500-rtc";
+		reg = <0xd8100000 0x10000>;
+		interrupts = <48>;
+	};
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
new file mode 100644
index 0000000..3222502
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 UART Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-uart"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UART interrupt
+
+Example:
+
+	uart at d8210000 {
+		compatible = "via,vt8500-uart";
+		reg = <0xd8210000 0x1040>;
+		interrupts = <47>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
new file mode 100644
index 0000000..a4fb071
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/platform-uhci.txt
@@ -0,0 +1,15 @@
+Generic Platform UHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "platform-uhci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UHCI controller interrupt
+
+Example:
+
+	uhci at d8007b00 {
+		compatible = "platform-uhci";
+		reg = <0xd8007b00 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
new file mode 100644
index 0000000..17b3ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 EHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-ehci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : ehci controller interrupt
+
+Example:
+
+	ehci at d8007900 {
+		compatible = "via,vt8500-ehci";
+		reg = <0xd8007900 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af..5c63da2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -47,5 +47,7 @@ sirf	SiRF Technology, Inc.
 st	STMicroelectronics
 stericsson	ST-Ericsson
 ti	Texas Instruments
+via	VIA Technologies, Inc.
 wlf	Wolfson Microelectronics
+wm	Wondermedia Technologies, Inc.
 xlnx	Xilinx
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
new file mode 100644
index 0000000..98ad14c
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
@@ -0,0 +1,48 @@
+VIA VT8500 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-fb"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : framebuffer controller interrupt
+- via,display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts.
+
+Example:
+
+	fb at d800e400 {
+		compatible = "via,vt8500-fb";
+		reg = <0xd800e400 0x400>;
+		interrupts = <12>;
+		via,display = <&display>;
+	};
+
+VIA VT8500 Display
+-----------------------------------------------------
+Required properties:
+- xres : lcd panel horizontal resolution
+- yres : lcd panel vertical resolution
+- left-margin,
+- right-margin,
+- hsync-len: lcd panel horizontal timings in pixels
+- upper-margin,
+- lower-margin,
+- vsync-len: lcd panel verticals timings in pixels
+- bpp: lcd panel bit-depth.
+	<16> for RGB565, <32> for RGB888
+
+Example:
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
new file mode 100644
index 0000000..a850fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia Graphics Engine Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,prizm-ge-rops"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	ge_rops at d8050400 {
+		compatible = "wm,prizm-ge-rops";
+		reg = <0xd8050400 0x100>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
new file mode 100644
index 0000000..64f016a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -0,0 +1,22 @@
+Wondermedia WM8505 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,wm8505-fb"
+- reg : Should contain 1 register ranges(address and length)
+- via,display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts. See definition in
+	Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+
+
+Example:
+
+	fb at d8050800 {
+		compatible = "wm,wm8505-fb";
+		reg = <0xd8050800 0x200>;
+		via,display = <&display>;
+	};
+
-- 
1.7.9.5



From linux at prisktech.co.nz  Tue Aug 21 16:47:35 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 08:47:35 +1200
Subject: [PATCHv3 6/9] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345582058-2291-7-git-send-email-linux@prisktech.co.nz>

Merged existing board files to a single dt-capable file.
Converted irq and timer code to devicetree.
Removed existing device files that are no longer required with
devicetree support.
All existing platform devices are converted to devicetree nodes
except PWM.

Removed restart.c and moved code into vt8500.c to remove
duplicate PMC code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/Kconfig                                |    5 +
 arch/arm/mach-vt8500/Kconfig                    |   72 +-----
 arch/arm/mach-vt8500/Makefile                   |    9 +-
 arch/arm/mach-vt8500/bv07.c                     |   80 -------
 arch/arm/mach-vt8500/common.h                   |   28 +++
 arch/arm/mach-vt8500/devices-vt8500.c           |   91 --------
 arch/arm/mach-vt8500/devices-wm8505.c           |   99 ---------
 arch/arm/mach-vt8500/devices.c                  |  270 -----------------------
 arch/arm/mach-vt8500/devices.h                  |   88 --------
 arch/arm/mach-vt8500/gpio.c                     |  240 --------------------
 arch/arm/mach-vt8500/include/mach/restart.h     |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h |   88 --------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h |   79 -------
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h |  115 ----------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h |   78 -------
 arch/arm/mach-vt8500/irq.c                      |  209 +++++++++++-------
 arch/arm/mach-vt8500/restart.c                  |   54 -----
 arch/arm/mach-vt8500/timer.c                    |   67 ++++--
 arch/arm/mach-vt8500/vt8500.c                   |  196 ++++++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c               |   79 -------
 20 files changed, 413 insertions(+), 1538 deletions(-)
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6774c80..ea8ec75 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -996,6 +996,10 @@ config ARCH_VT8500
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_PWM
+	select USE_OF
+	select COMMON_CLK
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
 	help
 	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1613,6 +1617,7 @@ config ARCH_NR_GPIO
 	default 355 if ARCH_U8500
 	default 264 if MACH_H4700
 	default 512 if SOC_OMAP5
+	default 288 if ARCH_VT8500
 	default 0
 	help
 	  Maximum number of GPIOs in the system.
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2c20a34..44f9f9d 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,73 +1,15 @@
 if ARCH_VT8500
 
-config VTWM_VERSION_VT8500
+config VTWM_VERSION_WMT_DT
 	bool
 
-config VTWM_VERSION_WM8505
-	bool
-
-config MACH_BV07
-	bool "Benign BV07-8500 Mini Netbook"
-	depends on ARCH_VT8500
-	select VTWM_VERSION_VT8500
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-	bool "WM8505 7-inch generic netbook"
+config MACH_WMT_DT
+	bool "VIA/Wondermedia SoC based boards (Device Tree Support)"
 	depends on ARCH_VT8500
-	select VTWM_VERSION_WM8505
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-	bool "7-inch with 800x480 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	default y
-	help
-	  These are found in most of the netbooks in generic cases, as
-	  well as in Eken M001 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x480' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_800X600
-	bool "8-inch with 800x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M003 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X576
-	bool "10-inch with 1024x576 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
+	select VTWM_VERSION_WMT_DT
 	help
-	  These are found in CherryPal netbooks and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x576' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X600
-	bool "10-inch with 1024x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M006 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
+	  Add support for netbooks, tablets and other devices based on
+	  the reference board design as produced by VIA/WonderMedia, using
+	  VT8500/WM8505/WM8650 System-on-Chip.
 
 endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 54e6997..1966183 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,9 +1,4 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_VTWM_VERSION_WMT_DT) += irq.o timer.o
+obj-$(CONFIG_MACH_WMT_DT) += vt8500.o
 
 obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2..0000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_lcdc,
-	&vt8500_device_ehci,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-	wmt_setup_restart();
-	vt8500_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= vt8500_reserve_mem,
-	.map_io		= vt8500_map_io,
-	.init_irq	= vt8500_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
new file mode 100644
index 0000000..2b24196
--- /dev/null
+++ b/arch/arm/mach-vt8500/common.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/mach-vt8500/dt_common.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
+
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+				struct device_node *parent);
+
+/* defined in drivers/clk/clk-vt8500.c */
+void __init vtwm_clk_init(void __iomem *pmc_base);
+
+#endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519ae..0000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-	tmp[1] = wmt_irq_res(IRQ_LCDC);
-	wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = VT8500_IC_BASE;
-	wmt_gpio_base = VT8500_GPIO_BASE;
-	wmt_pmc_base = VT8500_PMC_BASE;
-	wmt_i8042_base = VT8500_PS2_BASE;
-
-	wmt_nr_irqs = VT8500_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e..0000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-	wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART4);
-	wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART5);
-	wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = WM8505_IC_BASE;
-	wmt_sic_base = WM8505_SIC_BASE;
-	wmt_gpio_base = WM8505_GPIO_BASE;
-	wmt_pmc_base = WM8505_PMC_BASE;
-	wmt_i8042_base = WM8505_PS2_BASE;
-
-	wmt_nr_irqs = WM8505_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 1fcdc36..0000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-	.name           = "vt8500-lcd",
-	.id             = 0,
-	.dev		= {
-		.dma_mask	= &fb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-	.name           = "wm8505-fb",
-	.id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 480 * 2,
-	.mode		= {
-		.name		= "800x480",
-		.xres		= 800,
-		.yres		= 480,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "800x600",
-		.xres		= 800,
-		.yres		= 600,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 576 * 2,
-	.mode		= {
-		.name		= "1024x576",
-		.xres		= 1024,
-		.yres		= 576,
-		.left_margin	= 40,
-		.right_margin	= 24,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 96,
-		.vsync_len	= 2,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "1024x600",
-		.xres		= 1024,
-		.yres		= 600,
-		.left_margin	= 66,
-		.right_margin	= 2,
-		.upper_margin	= 19,
-		.lower_margin	= 1,
-		.hsync_len	= 23,
-		.vsync_len	= 8,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(panels); i++) {
-		if (strcmp(panels[i].mode.name, str) == 0) {
-			current_panel_idx = i;
-			break;
-		}
-	}
-	return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-				  unsigned long align) {
-	p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-			(p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-					(8 / p->bpp) + 1));
-	p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-							  align);
-	p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-	.name		= "vt8500_serial",
-	.id		= 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-	.name		= "vt8500_serial",
-	.id		= 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-	.name		= "vt8500_serial",
-	.id		= 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-	.name		= "vt8500_serial",
-	.id		= 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-	.name		= "vt8500_serial",
-	.id		= 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-	.name		= "vt8500_serial",
-	.id		= 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-	.name		= "vt8500-ehci",
-	.id		= 0,
-	.dev		= {
-		.dma_mask	= &ehci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_ge_rops = {
-	.name		= "wmt_ge_rops",
-	.id		= -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-	.name		= "vt8500-pwm",
-	.id		= 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-	.pwm_id		= 0,
-	.max_brightness	= 128,
-	.dft_brightness = 70,
-	.pwm_period_ns	= 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-	.name		= "pwm-backlight",
-	.id		= 0,
-	.dev		= {
-		.platform_data = &vt8500_pwmbl_data,
-	},
-};
-
-struct platform_device vt8500_device_rtc = {
-	.name		= "vt8500-rtc",
-	.id		= 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-	/* SoC MMIO registers */
-	[0] = {
-		.virtual	= 0xf8000000,
-		.pfn		= __phys_to_pfn(0xd8000000),
-		.length		= 0x00390000, /* max of all chip variants */
-		.type		= MT_DEVICE
-	},
-	/* PCI I/O space, numbers tied to those in <mach/io.h> */
-	[1] = {
-		.virtual	= 0xf0000000,
-		.pfn		= __phys_to_pfn(0xc0000000),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE
-	},
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-	panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-	preallocate_fb(&panels[current_panel_idx], SZ_4M);
-	vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-	panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-	preallocate_fb(&panels[current_panel_idx], 32);
-	vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e1..0000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_MEM,
-		.start = start,
-		.end = start + size - 1,
-	};
-
-	return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_IRQ,
-		.start = irq,
-		.end = irq,
-	};
-
-	return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-			       const struct resource *res, unsigned int num)
-{
-	if (unlikely(platform_device_add_resources(pdev, res, num)))
-		pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec..0000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS	0x0
-#define DIRECTION_REGS	0x20
-#define OUTVALUE_REGS	0x40
-#define INVALUE_REGS	0x60
-
-#define EXT_REGOFF	0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-	struct gpio_chip	chip;
-	unsigned int		shift;
-	unsigned int		regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-				     unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-				   unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-		val |= (1 << vt8500_chip->shift << offset);
-		writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-	}
-	return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-	return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-		>> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-	if (value)
-		val |= (1 << vt8500_chip->shift << offset);
-	else
-		val &= ~(1 << vt8500_chip->shift << offset);
-
-	writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)		\
-{									\
-	.chip = {							\
-		.label			= __name,			\
-		.request		= vt8500_muxed_gpio_request,	\
-		.free			= vt8500_muxed_gpio_free,	\
-		.direction_input  = vt8500_muxed_gpio_direction_input,	\
-		.direction_output = vt8500_muxed_gpio_direction_output,	\
-		.get			= vt8500_muxed_gpio_get_value,	\
-		.set			= vt8500_muxed_gpio_set_value,	\
-		.can_sleep		= 0,				\
-		.base			= __base,			\
-		.ngpio			= __num,			\
-	},								\
-	.shift		= __shift,					\
-	.regoff		= __off,					\
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-	VT8500_GPIO_BANK("uart0",	0,	0x0,	8,	4),
-	VT8500_GPIO_BANK("uart1",	4,	0x0,	12,	4),
-	VT8500_GPIO_BANK("spi0",	8,	0x0,	16,	4),
-	VT8500_GPIO_BANK("spi1",	12,	0x0,	20,	4),
-	VT8500_GPIO_BANK("spi2",	16,	0x0,	24,	4),
-	VT8500_GPIO_BANK("pwmout",	24,	0x0,	28,	2),
-
-	VT8500_GPIO_BANK("sdmmc",	0,	0x4,	30,	11),
-	VT8500_GPIO_BANK("ms",		16,	0x4,	41,	7),
-	VT8500_GPIO_BANK("i2c0",	24,	0x4,	48,	2),
-	VT8500_GPIO_BANK("i2c1",	26,	0x4,	50,	2),
-
-	VT8500_GPIO_BANK("mii",		0,	0x8,	52,	20),
-	VT8500_GPIO_BANK("see",		20,	0x8,	72,	4),
-	VT8500_GPIO_BANK("ide",		24,	0x8,	76,	7),
-
-	VT8500_GPIO_BANK("ccir",	0,	0xc,	83,	19),
-
-	VT8500_GPIO_BANK("ts",		8,	0x10,	102,	11),
-
-	VT8500_GPIO_BANK("lcd",		0,	0x14,	113,	23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val &= ~(1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-	return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val |= (1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-		val |= (1 << offset);
-		writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-	}
-	return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-	if (value)
-		val |= (1 << offset);
-	else
-		val &= ~(1 << offset);
-
-	writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	if (offset > 7)
-		return -EINVAL;
-
-	return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-	.label			= "extgpio",
-	.direction_input	= vt8500_gpio_direction_input,
-	.direction_output	= vt8500_gpio_direction_output,
-	.get			= vt8500_gpio_get_value,
-	.set			= vt8500_gpio_set_value,
-	.to_irq			= vt8500_gpio_to_irq,
-	.can_sleep		= 0,
-	.base			= 0,
-	.ngpio			= 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-	regbase = ioremap(wmt_gpio_base, SZ_64K);
-	if (!regbase) {
-		printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-		return;
-	}
-
-	gpiochip_add(&vt8500_external_gpios);
-
-	for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-		gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b78..7389795 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee91..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC	0	/* JPEG Encoder */
-#define IRQ_JPEGDEC	1	/* JPEG Decoder */
-				/* Reserved */
-#define IRQ_PATA	3	/* PATA Controller */
-				/* Reserved */
-#define IRQ_DMA		5	/* DMA Controller */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_GE		8	/* Graphic Engine */
-#define IRQ_GOV		9	/* Graphic Overlay Engine */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-#define IRQ_MPEGTS	11	/* Transport Stream Interface */
-#define IRQ_LCDC	12	/* LCD Controller */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_CIPHER	16	/* Cipher */
-#define IRQ_VPP		17	/* Video Post-Processor */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-				/* Reserved */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_LCDDF	27	/* LCD Data Formatter */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_MS		30	/* MemoryStick Controller */
-#define IRQ_MS_DMA	31	/* MemoryStick Controller DMA */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_I2S		34	/* I2S */
-#define IRQ_PCM		35	/* PCM */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_VPU		40	/* Video Processing Unit */
-#define IRQ_VID		41	/* Video Digital Input Interface */
-#define IRQ_AC97	42	/* AC97 Interface */
-#define IRQ_EHCI	43	/* USB */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_PS2MOUSE	45	/* PS/2 Mouse */
-#define IRQ_PS2KBD	46	/* PS/2 Keyboard */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_ADC		51	/* ADC */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_DMA0	56	/* DMA Channel 0 */
-#define IRQ_DMA1	57	/* DMA Channel 1 */
-#define IRQ_DMA2	58	/* DMA Channel 2 */
-#define IRQ_DMA3	59	/* DMA Channel 3 */
-#define IRQ_DMA4	60	/* DMA Channel 4 */
-#define IRQ_DMA5	61	/* DMA Channel 5 */
-#define IRQ_DMA6	62	/* DMA Channel 6 */
-#define IRQ_DMA7	63	/* DMA Channel 7 */
-
-#define VT8500_NR_IRQS		64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ec..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define VT8500_DDR_BASE		0xd8000000	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define VT8500_DMA_BASE		0xd8001000	/* 1k	DMA Controller */
-#define VT8500_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define VT8500_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define VT8500_USB_BASE		0xd8007800	/* 2k	USB OTG */
-# define VT8500_EHCI_BASE	0xd8007900	/*	EHCI */
-# define VT8500_UHCI_BASE	0xd8007b01	/*	UHCI */
-#define VT8500_PATA_BASE	0xd8008000	/* 512	PATA */
-#define VT8500_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define VT8500_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define VT8500_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define VT8500_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define VT8500_MS_BASE		0xd800b000	/* 1k	MS/MSPRO Controller */
-#define VT8500_LCDC_BASE	0xd800e400	/* 1k	LCD Controller */
-#define VT8500_VPU_BASE		0xd8050000	/* 256	VPU */
-#define VT8500_GOV_BASE		0xd8050300	/* 256	GOV */
-#define VT8500_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE	0xd8050900	/* 256	LCD Formatter */
-#define VT8500_VID_BASE		0xd8050a00	/* 256	VID */
-#define VT8500_VPP_BASE		0xd8050b00	/* 256	VPP */
-#define VT8500_TSBK_BASE	0xd80f4000	/* 4k	TSBK */
-#define VT8500_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define VT8500_JPEGENC_BASE	0xd80ff000	/* 4k	JPEG Encoder */
-#define VT8500_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define VT8500_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define VT8500_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define VT8500_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define VT8500_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define VT8500_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define VT8500_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define VT8500_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define VT8500_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define VT8500_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define VT8500_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define VT8500_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define VT8500_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define VT8500_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define VT8500_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define VT8500_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define VT8500_PCM_BASE		0xd82d0000	/* 64k	PCM */
-#define VT8500_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define VT8500_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define VT8500_ADC_BASE		0xd8340000	/* 64k	ADC */
-
-#define VT8500_REGS_END_PHYS	0xd834ffff	/* End of MMIO registers */
-#define VT8500_REGS_LENGTH	(VT8500_REGS_END_PHYS \
-				- VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI	0	/* UHC FS (UHCI?) */
-#define IRQ_EHCI	1	/* UHC HS */
-#define IRQ_UDCDMA	2	/* UDC DMA */
-				/* Reserved */
-#define IRQ_PS2MOUSE	4	/* PS/2 Mouse */
-#define IRQ_UDC		5	/* UDC */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_KEYPAD	8	/* Keypad */
-#define IRQ_DMA		9	/* DMA Controller */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-				/* Reserved */
-				/* Reserved */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_APB		16	/* APB Bridge */
-#define IRQ_DMA0	17	/* DMA Channel 0 */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-#define IRQ_PS2KBD	23	/* PS/2 Keyboard */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_DMA1	27	/* DMA Channel 1 */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_UART5	30	/* UART 5 */
-#define IRQ_UART4	31	/* UART 4 */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_DMA2	34	/* DMA Channel 2 */
-#define IRQ_I2S		35	/* I2S */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_DMA3	40	/* DMA Channel 3 */
-#define IRQ_DMA4	41	/* DMA Channel 4 */
-#define IRQ_AC97	42	/* AC97 Interface */
-				/* Reserved */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_DMA5	45	/* DMA Channel 5 */
-#define IRQ_DMA6	46	/* DMA Channel 6 */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_DMA7	51	/* DMA Channel 7 */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_SIC0	56	/* SIC IRQ0 */
-#define IRQ_SIC1	57	/* SIC IRQ1 */
-#define IRQ_SIC2	58	/* SIC IRQ2 */
-#define IRQ_SIC3	59	/* SIC IRQ3 */
-#define IRQ_SIC4	60	/* SIC IRQ4 */
-#define IRQ_SIC5	61	/* SIC IRQ5 */
-#define IRQ_SIC6	62	/* SIC IRQ6 */
-#define IRQ_SIC7	63	/* SIC IRQ7 */
-				/* Reserved */
-#define IRQ_JPEGDEC	65	/* JPEG Decoder */
-#define IRQ_SAE		66	/* SAE (?) */
-				/* Reserved */
-#define IRQ_VPU		79	/* Video Processing Unit */
-#define IRQ_VPP		80	/* Video Post-Processor */
-#define IRQ_VID		81	/* Video Digital Input Interface */
-#define IRQ_SPU		82	/* SPU (?) */
-#define IRQ_PIP		83	/* PIP Error */
-#define IRQ_GE		84	/* Graphic Engine */
-#define IRQ_GOV		85	/* Graphic Overlay Engine */
-#define IRQ_DVO		86	/* Digital Video Output */
-				/* Reserved */
-#define IRQ_DMA8	92	/* DMA Channel 8 */
-#define IRQ_DMA9	93	/* DMA Channel 9 */
-#define IRQ_DMA10	94	/* DMA Channel 10 */
-#define IRQ_DMA11	95	/* DMA Channel 11 */
-#define IRQ_DMA12	96	/* DMA Channel 12 */
-#define IRQ_DMA13	97	/* DMA Channel 13 */
-#define IRQ_DMA14	98	/* DMA Channel 14 */
-#define IRQ_DMA15	99	/* DMA Channel 15 */
-				/* Reserved */
-#define IRQ_GOVW	111	/* GOVW (?) */
-#define IRQ_GOVRSDSCD	112	/* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF	113	/* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD	114	/* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF	115	/* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS		116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df15509..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define WM8505_DDR_BASE		0xd8000400	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define WM8505_DMA_BASE		0xd8001800	/* 1k	DMA Controller */
-#define WM8505_VDMA_BASE	0xd8001c00	/* 1k	VDMA */
-#define WM8505_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define WM8505_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define WM8505_USB_BASE		0xd8007000	/* 2k	USB 2.0 Host */
-# define WM8505_EHCI_BASE	0xd8007100	/*	EHCI */
-# define WM8505_UHCI_BASE	0xd8007301	/*	UHCI */
-#define WM8505_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define WM8505_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define WM8505_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define WM8505_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define WM8505_VPU_BASE		0xd8050000	/* 256	VPU */
-#define WM8505_GOV_BASE		0xd8050300	/* 256	GOV */
-#define WM8505_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE	0xd8050800	/* 512	GOVR (frambuffer) */
-#define WM8505_VID_BASE		0xd8050a00	/* 256	VID */
-#define WM8505_SCL_BASE		0xd8050d00	/* 256	SCL */
-#define WM8505_VPP_BASE		0xd8050f00	/* 256	VPP */
-#define WM8505_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define WM8505_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define WM8505_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define WM8505_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define WM8505_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define WM8505_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define WM8505_SIC_BASE		0xd8150000	/* 64k	Secondary IC */
-#define WM8505_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define WM8505_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define WM8505_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define WM8505_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define WM8505_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define WM8505_KEYPAD_BASE	0xd8260000	/* 64k	Keypad control */
-#define WM8505_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define WM8505_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define WM8505_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define WM8505_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define WM8505_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define WM8505_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define WM8505_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define WM8505_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define WM8505_UART4_BASE	0xd8370000	/* 64k	UART 4 */
-#define WM8505_UART5_BASE	0xd8380000	/* 64k	UART 5 */
-
-#define WM8505_REGS_END_PHYS	0xd838ffff	/* End of MMIO registers */
-#define WM8505_REGS_LENGTH	(WM8505_REGS_END_PHYS \
-				- WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de04..f8f9ab9 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
  *  arch/arm/mach-vt8500/irq.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,81 +19,102 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR		0x40		/* Destination control
-						register, 64*u8 */
-#define VT8500_INT_ENABLE	(1 << 3)
-#define VT8500_TRIGGER_HIGH	(0 << 4)
-#define VT8500_TRIGGER_RISING	(1 << 4)
-#define VT8500_TRIGGER_FALLING	(2 << 4)
+#define VT8500_ICPC_IRQ		0x20
+#define VT8500_ICPC_FIQ		0x24
+#define VT8500_ICDC		0x40		/* Destination Control 64*u32 */
+#define VT8500_ICIS		0x80		/* Interrupt status, 16*u32 */
+
+/* ICPC */
+#define ICPC_MASK		0x3F
+#define ICPC_ROTATE		BIT(6)
+
+/* IC_DCTR */
+#define ICDC_IRQ		0x00
+#define ICDC_FIQ		0x01
+#define ICDC_DSS0		0x02
+#define ICDC_DSS1		0x03
+#define ICDC_DSS2		0x04
+#define ICDC_DSS3		0x05
+#define ICDC_DSS4		0x06
+#define ICDC_DSS5		0x07
+
+#define VT8500_INT_DISABLE	0
+#define VT8500_INT_ENABLE	BIT(3)
+
+#define VT8500_TRIGGER_HIGH	0
+#define VT8500_TRIGGER_RISING	BIT(5)
+#define VT8500_TRIGGER_FALLING	BIT(6)
 #define VT8500_EDGE		( VT8500_TRIGGER_RISING \
 				| VT8500_TRIGGER_FALLING)
-#define VT8500_IC_STATUS	0x80		/* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt;
+
+struct vt8500_irq_priv {
+	void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 edge;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
 	if (edge) {
-		void __iomem *stat_reg = base + VT8500_IC_STATUS
-						+ (irq < 32 ? 0 : 4);
+		void __iomem *stat_reg = base + VT8500_ICIS
+						+ (d->hwirq < 32 ? 0 : 4);
 		unsigned status = readl(stat_reg);
 
-		status |= (1 << (irq & 0x1f));
+		status |= (1 << (d->hwirq & 0x1f));
 		writel(status, stat_reg);
 	} else {
-		u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+		u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
 
 		dctr &= ~VT8500_INT_ENABLE;
-		writeb(dctr, base + VT8500_IC_DCTR + irq);
+		writeb(dctr, base + VT8500_ICDC + d->hwirq);
 	}
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_ICDC + d->hwirq);
 	dctr |= VT8500_INT_ENABLE;
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_ICDC + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
-	unsigned orig_irq = irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_ICDC + d->hwirq);
 	dctr &= ~VT8500_EDGE;
 
 	switch (flow_type) {
@@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 		return -EINVAL;
 	case IRQF_TRIGGER_HIGH:
 		dctr |= VT8500_TRIGGER_HIGH;
-		__irq_set_handler_locked(orig_irq, handle_level_irq);
+		__irq_set_handler_locked(d->irq, handle_level_irq);
 		break;
 	case IRQF_TRIGGER_FALLING:
 		dctr |= VT8500_TRIGGER_FALLING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	case IRQF_TRIGGER_RISING:
 		dctr |= VT8500_TRIGGER_RISING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	}
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_ICDC + d->hwirq);
 
 	return 0;
 }
@@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = {
 	.irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
 	unsigned int i;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+	/* Enable rotating priority for IRQ */
+	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
+	writel(0x00, base + VT8500_ICPC_FIQ);
 
-	if (ic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
+	for (i = 0; i < 64; i++) {
+		/* Disable all interrupts and route them to IRQ */
+		writeb(VT8500_INT_DISABLE | ICDC_IRQ,
+						base + VT8500_ICDC + i);
+	}
+}
 
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
 
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+	.map = vt8500_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-	unsigned int i;
+	struct irq_domain *vt8500_irq_domain;
+	struct vt8500_irq_priv *priv;
+	int irq, i;
+	struct device_node *np = node;
+
+	priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+	priv->base = of_iomap(np, 0);
+
+	vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+				&vt8500_irq_domain_ops, priv);
+	if (!vt8500_irq_domain)
+		pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+
+	irq_set_default_host(vt8500_irq_domain);
+
+	vt8500_init_irq_hw(priv->base);
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-	sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-	if (ic_regbase && sic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
-		writel((1 << 6), sic_regbase + 0x20);
-		writel(0, sic_regbase + 0x24);
-
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			if (i < 64)
-				writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-			else
-				writeb(0x00, sic_regbase + VT8500_IC_DCTR
-								+ i - 64);
-
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
+	pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+						(u32)(priv->base), irq_cnt);
+
+	/* check if this is a slaved controller */
+	if (of_irq_count(np) != 0) {
+		/* check that we have the correct number of interrupts */
+		if (of_irq_count(np) != 8) {
+			pr_err("%s: Incorrect IRQ map for slave controller\n",
+					__func__);
+			return -EINVAL;
 		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
+
+		for (i = 0; i < 8; i++) {
+			irq = irq_of_parse_and_map(np, i);
+			enable_irq(irq);
+		}
+
+		pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
 	}
+
+	irq_cnt += 64;
+
+	return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a..0000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE		0xD8130000
-#define WMT_PRIZM_PMSR_REG	0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-	struct device_node *np;
-
-	/*
-	 * Check if Power Mgmt Controller node is present in device tree. If no
-	 * device tree node, use the legacy PMSR value (valid for all current
-	 * SoCs).
-	 */
-	np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-	if (np) {
-		pmc_base = of_iomap(np, 0);
-
-		if (!pmc_base)
-			pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-		of_node_put(np);
-	} else {
-		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-		if (!pmc_base) {
-			pr_err("%s:ioremap(rstc) failed\n", __func__);
-			return;
-		}
-	}
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-	if (pmc_base)
-		writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c5..050e183 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET	0x0100
+#define VT8500_TIMER_HZ		3000000
 #define TIMER_MATCH_VAL		0x0000
 #define TIMER_COUNT_VAL		0x0010
 #define TIMER_STATUS_VAL	0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
 #define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
 #define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */
-#define VT8500_TIMER_HZ		3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
 	return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
 	.name           = "vt8500_timer",
 	.rating         = 200,
 	.read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
 	}
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
 	.name           = "vt8500_timer",
 	.features       = CLOCK_EVT_FEAT_ONESHOT,
 	.rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
 	.name    = "vt8500_timer",
 	.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = vt8500_timer_interrupt,
 	.dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+	{ .compatible = "via,vt8500-timer" },
+	{ }
+};
+
+void __init vt8500_timer_init(void)
 {
-	regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-	if (!regbase)
-		printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+	struct device_node *np;
+	int timer_irq;
+
+	np = of_find_matching_node(NULL, vt8500_timer_ids);
+	if (!np) {
+		pr_err("%s: Timer description missing from Device Tree\n",
+								__func__);
+		return;
+	}
+	regbase = of_iomap(np, 0);
+	if (!regbase) {
+		pr_err("%s: Missing iobase description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
+	timer_irq = irq_of_parse_and_map(np, 0);
+	if (!timer_irq) {
+		pr_err("%s: Missing irq description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
 
 	writel(1, regbase + TIMER_CTRL_VAL);
 	writel(0xf, regbase + TIMER_STATUS_VAL);
 	writel(~0, regbase + TIMER_MATCH_VAL);
 
 	if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-		printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
-					clocksource.name);
+		pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
+					__func__, clocksource.name);
 
 	clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
 
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
 	clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
 	clockevent.cpumask = cpumask_of(0);
 
-	if (setup_irq(wmt_timer_irq, &irq))
-		printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
-					clockevent.name);
+	if (setup_irq(timer_irq, &irq))
+		pr_err("%s: setup_irq failed for %s\n", __func__,
+							clockevent.name);
 	clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-	.init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 0000000..4494993
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,196 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE	0xD8110000
+#define LEGACY_PMC_BASE		0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG	0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG		0x12
+#define VT8500_PMSR_REG		0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+	if (pmc_base)
+		writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+	/* SoC MMIO registers */
+	[0] = {
+		.virtual	= 0xf8000000,
+		.pfn		= __phys_to_pfn(0xd8000000),
+		.length		= 0x00390000, /* max of all chip variants */
+		.type		= MT_DEVICE
+	},
+};
+
+void __init vt8500_map_io(void)
+{
+	iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+	local_irq_disable();
+	writew(5, pmc_base + VT8500_HCR_REG);
+	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+	struct device_node *np, *fb;
+	void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+	fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+				gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+#ifdef CONFIG_FB_WM8505
+	fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np)
+			np = of_find_compatible_node(NULL, NULL,
+							"wm,wm8650-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+				0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+	np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+	if (np) {
+		pmc_base = of_iomap(np, 0);
+
+		if (!pmc_base)
+			pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+		of_node_put(np);
+	} else {
+		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+		if (!pmc_base)
+			pr_err("%s:ioremap(power_off) failed\n", __func__);
+	}
+	if (pmc_base)
+		pm_power_off = &vt8500_power_off;
+	else
+		pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+	vtwm_clk_init(pmc_base);
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+	{ .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+	{ /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+	of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+	.init = vt8500_timer_init,
+};
+
+static const char * const vt8500_dt_compat[] = {
+	"via,vt8500",
+	"wm,wm8650",
+	"wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+	.dt_compat	= vt8500_dt_compat,
+	.map_io		= vt8500_map_io,
+	.init_irq	= vt8500_init_irq,
+	.timer		= &vt8500_timer,
+	.init_machine	= vt8500_init,
+	.restart	= vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886..0000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_ehci,
-	&vt8500_device_wm8505_fb,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-	wmt_setup_restart();
-	wm8505_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= wm8505_reserve_mem,
-	.map_io		= wm8505_map_io,
-	.init_irq	= wm8505_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= wm8505_7in_init,
-MACHINE_END
-- 
1.7.9.5



From swarren at wwwdotorg.org  Tue Aug 21 17:38:40 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 21 Aug 2012 15:38:40 -0600
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
Message-ID: <5033FFE0.5070209@wwwdotorg.org>

On 08/21/2012 05:25 AM, Linus Walleij wrote:
> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
> 
>> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
>> SoC's.
...
>> +  The child node can also optionally specify one or more of the pin
>> +  configuration that should be applied on all the pins listed in the
>> +  "samsung,pins" property of the child node. The following pin configuration
>> +  properties are supported.
>> +
>> +  - samsung,pin-pud: Pull up/down configuration.
>> +  - samsung,pin-drv: Drive strength configuration.
>> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
>> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
> 
> This looks a bit scary, as it seems to be orthogonal to the pin config
> interface. I.e. this will be programmed "behind the back" of the
> pin config system. However as long as the pin config implementation
> reads back these things from the registers it will work, too.
> 
> In the U300 and Ux500 I explicitly use pin config hogs to set up
> the pin configuration, and when we enter a state such as
> "default" the mux setting and config settings are set from the
> framework separately.

I know that some HW has a separate set of registers (or fields) for the
"awake" and "sleep" configuration, and the HW switches between the two
automatically when sleeping. I have no idea if the Samsung SoCs do this,
but I think if this were the case, it'd be quite legitimate to define
both these HW states as separate sets of properties within a single
pinctrl SW state. So, that might be the explanation here?



From catalin.marinas at arm.com  Tue Aug 21 18:01:45 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 21 Aug 2012 23:01:45 +0100
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <201208212014.01837.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151422.16335.arnd@arndb.de> <20120821175122.GI12708@arm.com>
 <201208212014.01837.arnd@arndb.de>
Message-ID: <20120821220145.GA27934@arm.com>

On Tue, Aug 21, 2012 at 09:14:01PM +0100, Arnd Bergmann wrote:
> On Tuesday 21 August 2012, Catalin Marinas wrote:
> > > > +asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
> > > > +                    unsigned long prot, unsigned long flags,
> > > > +                    unsigned long fd, off_t off)
> > > > +{
> > > > +   if (offset_in_page(off) != 0)
> > > > +           return -EINVAL;
> > > > +
> > > > +   return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
> > > > +}
> > > 
> > > I think
> > > 
> > > #define sys_mmap sys_mmap_pgoff 
> > 
> > There are slightly different semantics with the last argument of
> > sys_mmap() which takes a byte offset. The sys_mmap_pgoff() function
> > takes the offset shifted by PAGE_SHIFT (which is the same as sys_mmap2).
> > 
> > Looking at the other architectures, it makes sense to use a generic
> > sys_mmap() implementation similar to the one above (or the ia-64, seems
> > to be the most complete).
> 
> Why that? The generic sys_mmap_pgoff was specifically added so new architectures
> could just use that instead of having their own wrappers, see f8b72560.

As I understand, sys_mmap_pgoff can be used instead of sys_mmap2 on new
32-bit architectures. But on 64-bit architectures we don't have
sys_mmap2, only sys_mmap with the difference that the last argument is
the offset in bytes (and multiple of PAGE_SIZE) rather than in pages. So
unless we change the meaning of this last argument for sys_mmap, we
cannot just define it to sys_mmap_pgoff.

Since the other 64-bit architectures seem to have a sys_mmap wrapper
that does this:

	sys_mmap_pgoff(..., off >> PAGE_SHIFT);

I think AArch64 should also use the same sys_mmap convention. We can
make this wrapper generic.

-- 
Catalin


From linus.walleij at linaro.org  Tue Aug 21 18:04:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 00:04:23 +0200
Subject: [PATCH v2] serial: pl011: honour serial aliases in device tree
In-Reply-To: <1345564094-16565-1-git-send-email-matthew.leach@arm.com>
References: <1345564094-16565-1-git-send-email-matthew.leach@arm.com>
Message-ID: <CACRpkdbh-PhFKU54FCti-7RwQLJ8Q0d9_XLPEk5vNemjDOa-wQ@mail.gmail.com>

On Tue, Aug 21, 2012 at 5:48 PM, Matthew Leach <matthew.leach at arm.com> wrote:

> If the order of UART nodes is changed in the device tree, then tty dev
> devices are attached to different serial ports causing the console to
> be directed to a different physical serial port. The "serial" aliases
> in the device tree should prevent this.
>
> This patch ensures that the UART driver creates tty devices that
> honour these aliases if a device tree is present.
>
> Acked-by: Rob Herring <rob.herring at calxeda.com>
> Signed-off-by: Matthew Leach <matthew.leach at arm.com>
> ---
> v2: use IS_ENABLED instead of ifdefs

Looks good to me.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From alan at lxorguk.ukuu.org.uk  Tue Aug 21 18:12:55 2012
From: alan at lxorguk.ukuu.org.uk (Alan Cox)
Date: Tue, 21 Aug 2012 23:12:55 +0100
Subject: [PATCHv3 3/9] serial: vt8500: Add devicetree support for
 vt8500-serial
In-Reply-To: <1345582058-2291-4-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-4-git-send-email-linux@prisktech.co.nz>
Message-ID: <20120821231255.71a7515a@pyramind.ukuu.org.uk>

On Wed, 22 Aug 2012 08:47:32 +1200
Tony Prisk <linux at prisktech.co.nz> wrote:

> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
> ---
>  drivers/tty/serial/vt8500_serial.c |   37 ++++++++++++++++++++++++++++++++----
>  1 file changed, 33 insertions(+), 4 deletions(-)

Can we have a comment attached to a change this size. In particular one
describing why it gone from 4 to 6 ports, and why the port id twiddling.

Is there a reason you can't use the device tree port id ?

What are the regression risks for existing users expecting the pdev->id
binding ?


From jon-hunter at ti.com  Tue Aug 21 22:08:39 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 21 Aug 2012 21:08:39 -0500
Subject: [PATCH v6 05/10] ARM: OMAP2+: gpmc: find features by ip rev check
In-Reply-To: <0b211272d0d6f9281df7db400cb2d6a968b31222.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <0b211272d0d6f9281df7db400cb2d6a968b31222.1345524670.git.afzal@ti.com>
Message-ID: <50343F27.4060101@ti.com>


On 08/21/2012 05:45 AM, Afzal Mohammed wrote:
> Newer IP's have wr_access and wr_data_mux_bus fields. Use
> IP revision values to determine availability of these
> fields and hence decide on whether to configure them.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  arch/arm/mach-omap2/gpmc.c |   12 ++++++++++--
>  1 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index 070fac5..68123d0 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -85,6 +85,11 @@
>  #define ENABLE_PREFETCH		(0x1 << 7)
>  #define DMA_MPU_MODE		2
>  
> +#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)
> +
> +#define	GPMC_HAS_WR_ACCESS		0x1
> +#define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
> +
>  /* XXX: Only NAND irq has been considered,currently these are the only ones used
>   */
>  #define	GPMC_NR_IRQ		2
> @@ -131,6 +136,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock);
>  static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
>  static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
>  
> +static unsigned gpmc_capability;
>  static void __iomem *gpmc_base;
>  
>  static struct clk *gpmc_l3_clk;
> @@ -356,10 +362,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
>  	GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
>  	GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
>  
> -	if (cpu_is_omap34xx()) {
> +	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
>  		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> +	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
>  		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> -	}
>  
>  	/* caller is expected to have initialized CONFIG1 to cover
>  	 * at least sync vs async
> @@ -922,6 +928,8 @@ static int __init gpmc_init(void)
>  	clk_enable(gpmc_l3_clk);
>  
>  	l = gpmc_read_reg(GPMC_REVISION);
> +	if (GPMC_REVISION_MAJOR(l) > 0x4)
> +		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
>  	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
>  	/* Set smart idle mode and automatic L3 clock gating */
>  	l = gpmc_read_reg(GPMC_SYSCONFIG);
> 

Reviewed-by: Jon Hunter <jon-hunter at ti.com>

Thanks!
Jon


From jon-hunter at ti.com  Tue Aug 21 22:11:51 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 21 Aug 2012 21:11:51 -0500
Subject: [PATCH v6 06/10] ARM: OMAP2+: gpmc: remove cs# in sync clk div
 calc
In-Reply-To: <3cc7885c2ae9055763ba72cae0735b065dae403e.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <3cc7885c2ae9055763ba72cae0735b065dae403e.1345524670.git.afzal@ti.com>
Message-ID: <50343FE7.8030207@ti.com>


On 08/21/2012 05:45 AM, Afzal Mohammed wrote:
> Divider value for a certain sync clk is determined solely
> based on gpmc fclk. CS# does not have any role here, thus
> remove presence of CS# in clock divider calculation API.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  arch/arm/mach-omap2/gpmc-onenand.c     |    3 +--
>  arch/arm/mach-omap2/gpmc.c             |    4 ++--
>  arch/arm/plat-omap/include/plat/gpmc.h |    2 +-
>  3 files changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
> index 8a301f3..e139e3f 100644
> --- a/arch/arm/mach-omap2/gpmc-onenand.c
> +++ b/arch/arm/mach-omap2/gpmc-onenand.c
> @@ -182,7 +182,6 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
>  	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
>  	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns;
>  	int ticks_cez;
> -	int cs = cfg->cs;
>  
>  	if (cfg->flags & ONENAND_SYNC_READ)
>  		onenand_flags = ONENAND_FLAG_SYNCREAD;
> @@ -229,7 +228,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
>  		break;
>  	}
>  
> -	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
> +	div = gpmc_calc_divider(min_gpmc_clk_period);
>  	gpmc_clk_ns = gpmc_ticks_to_ns(div);
>  	if (gpmc_clk_ns < 15) /* >66Mhz */
>  		onenand_flags |= ONENAND_FLAG_HF;
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index 68123d0..d005b3a 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -313,7 +313,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
>  		return -1
>  #endif
>  
> -int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
> +int gpmc_calc_divider(unsigned int sync_clk)
>  {
>  	int div;
>  	u32 l;
> @@ -333,7 +333,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
>  	int div;
>  	u32 l;
>  
> -	div = gpmc_cs_calc_divider(cs, t->sync_clk);
> +	div = gpmc_calc_divider(t->sync_clk);
>  	if (div < 0)
>  		return -1;
>  
> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
> index b7c9ea6..1cafbfd 100644
> --- a/arch/arm/plat-omap/include/plat/gpmc.h
> +++ b/arch/arm/plat-omap/include/plat/gpmc.h
> @@ -179,7 +179,7 @@ extern unsigned long gpmc_get_fclk_period(void);
>  
>  extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
>  extern u32 gpmc_cs_read_reg(int cs, int idx);
> -extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
> +extern int gpmc_calc_divider(unsigned int sync_clk);
>  extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
>  extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
>  extern void gpmc_cs_free(int cs);
> 

Reviewed-by: Jon Hunter <jon-hunter at ti.com>

Thanks!
Jon


From shawn.guo at linaro.org  Tue Aug 21 22:14:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 10:14:27 +0800
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <50338A35.9070803@gmail.com>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
 <CACRpkda2hc2eZaFqRfAPEG7KfLd3mFFdWze=V45=w84nRPqijA@mail.gmail.com>
 <50338A35.9070803@gmail.com>
Message-ID: <20120822021424.GO24242@S2101-09.ap.freescale.net>

On Tue, Aug 21, 2012 at 08:16:37AM -0500, Rob Herring wrote:
> On 08/21/2012 08:01 AM, Linus Walleij wrote:
> > On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > 
> >> Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
> >> driver adopt irqdomain support, so that we can have the mapping
> >> between gpio and irq number available without using virtual_irq_start
> >> and MXS_GPIO_IRQ_START.
> > 
> > Seems like a good thing to do, but with Grant and Rob being better at
> > irqdomain than me I'd prefer one of them to have a look at this too.
> > 
> >> +       irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
> >> +       if (irq_base < 0)
> >> +               return irq_base;
> >> +
> >> +       port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
> >> +                                            &irq_domain_simple_ops, NULL);
> > 
> > For example I want to understand if it'd be possible to use a
> > linear domain here.
> 
> Unfortunately, not if you care about your irq base and need sequential
> irq numbers which is the case for non-DT.
> 
Right.  For for this particular case, it's more because generic-chip
currently does not cope with the driver using linear domain.

-- 
Regards,
Shawn


From xiechao.mail at gmail.com  Tue Aug 21 22:22:54 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Wed, 22 Aug 2012 10:22:54 +0800
Subject: FW: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <AAD1C6EB06EE3649B35B7E026785068D1A754366CB@SC-VEXCH2.marvell.com>
References: <AAD1C6EB06EE3649B35B7E026785068D1A754366CB@SC-VEXCH2.marvell.com>
Message-ID: <CADApbehnsRzwu_LrAEMf+L7AvXv+JBtPBOzWHj578Vs6B_LrCw@mail.gmail.com>

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Monday, August 20, 2012 1:39 PM
> To: Chao Xie
> Cc: haojian.zhuang at gmail.com; mturquette at linaro.org; viresh.linux at gmail.com; s.hauer at pengutronix.de; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Chao Xie
> Subject: Re: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
>
> On Monday 20 August 2012, Chao Xie wrote:
>>
>> From: Chao Xie <chao.xie at marvell.com>
>>
>> v1->v2:
>> replace __raw_xxx with xxx_relax
>> use ioremap to remap the registers. Finaly it will use device tree to
>> get the physical address.
>> do not use macro to register clocks, and directly call the functions.
>>
>> v2->v3:
>> pxa910 will have APB extension clock, so some peripharals will have
>> clocks in APB extension base.
>> change pxa168-pwm to be pxa910-pwm for pxa910. It will fit the current
>> pwm driver.
>>
>> v3->v4:
>> remove addtional clock name definition
>> replace left __raw_xxx
>>
>> v4->v5:
>> change the format of the file
>>
>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
>
>         Arnd

Who will be responsible for merging these patches?


From shawn.guo at linaro.org  Tue Aug 21 22:47:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 10:47:09 +0800
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
Message-ID: <20120822024707.GP24242@S2101-09.ap.freescale.net>

On Mon, Aug 20, 2012 at 12:22:56PM -0500, Matt Sealey wrote:
> It's not bloat just because it is by its very definition "a big list", is it?
> 
Grep for_each_node_by_*() and for_each_*_node() (include/linux/of.h)
in the tree to see how often these global device tree searching is
used, you may know how important not having so many nodes is.

> How do you explain duplicating the clock names in the array AND in the
> device node as NOT being bloated?
> 
> You're going to have to define these clocks as a tree with parents and
> leaf nodes anyway in the clock subsystem. Why not define these in the
> device tree in total and reference them by handle when you build the
> entire clock tree from the ground up? Or will it just be all the
> clocks defined in Linux, but the lookups (which is what I see here)
> moved into the DT? Why not form the lookups as part of the definition
> of the clock tree?
> 
This is something I had tried long time before, but it did not get
accepted because:

* It's unnecessary to encode the entire clock tree which is SoC
  specific in device tree.  Clock driver is a good place for that.

* Again, doing so will bloat device tree with hundreds of nodes.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Tue Aug 21 23:24:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 11:24:13 +0800
Subject: [PATCH] ARM: olinuxino: Add gpio-led support
In-Reply-To: <1345513396-12320-1-git-send-email-festevam@gmail.com>
References: <1345513396-12320-1-git-send-email-festevam@gmail.com>
Message-ID: <20120822032409.GQ24242@S2101-09.ap.freescale.net>

On Mon, Aug 20, 2012 at 10:43:15PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Olinuxino has a LED connected to MX23_PAD_SSP1_DETECT__GPIO_2_1 pin.
> 
> Since mmc0_4bit_pins_a defines MX23_PAD_SSP1_DETECT as SSP function, create
> a new mmc0_4bit_pins_b.
> 

mmc0_4bit_pins_b should be used where there is same number of pins in
the group as mmc0_4bit_pins_a but with a different pinmux option.

I think we drop MX23_PAD_SSP1_DETECT__SSP1_DETECT from mmc0_4bit_pins_a
and change the current mmc0_4bit_pins_a users to have it set up in hog,
so that mmc0_4bit_pins_a becomes more generic.

> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx23-olinuxino.dts |   28 +++++++++++++++++++++++++++-
>  arch/arm/boot/dts/imx23.dtsi          |   15 +++++++++++++++
>  2 files changed, 42 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
> index a286873..dece3fe 100644
> --- a/arch/arm/boot/dts/imx23-olinuxino.dts
> +++ b/arch/arm/boot/dts/imx23-olinuxino.dts
> @@ -27,10 +27,25 @@
>  			ssp0: ssp at 80010000 {
>  				compatible = "fsl,imx23-mmc";
>  				pinctrl-names = "default";
> -				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
> +				pinctrl-0 = <&mmc0_4bit_pins_b &mmc0_pins_fixup>;
>  				bus-width = <4>;
>  				status = "okay";
>  			};
> +
> +			pinctrl at 80018000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&hog_pins_a>;
> +
> +				hog_pins_a: hog-gpios at 0 {

I suggest to have it be:

				hog_pins: hog at 0 {

because I see we will probably need to set up some non-gpio pins here
too.

-- 
Regards,
Shawn

> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
> +					>;
> +					fsl,drive-strength = <0>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +			};
>  		};
>  
>  		apbx at 80040000 {
> @@ -47,4 +62,15 @@
>  			};
>  		};
>  	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		user {
> +			label = "green";
> +			gpios = <&gpio2 1 0>;
> +			linux,default-trigger = "default-on";
> +			default-state = "on";
> +		};
> +	};
>  };
> diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
> index 9700872..a8b423a 100644
> --- a/arch/arm/boot/dts/imx23.dtsi
> +++ b/arch/arm/boot/dts/imx23.dtsi
> @@ -202,6 +202,21 @@
>  					fsl,pull-up = <1>;
>  				};
>  
> +				mmc0_4bit_pins_b: mmc0-4bit_b at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
> +						0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
> +						0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
> +						0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
> +						0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
> +						0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
> +					>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
>  				mmc0_8bit_pins_a: mmc0-8bit at 0 {
>  					reg = <0>;
>  					fsl,pinmux-ids = <
> -- 
> 1.7.9.5
> 


From vinod.koul at linux.intel.com  Tue Aug 21 23:39:26 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 22 Aug 2012 09:09:26 +0530
Subject: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345574589-24757-2-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-2-git-send-email-mporter@ti.com>
Message-ID: <1345606766.1895.40.camel@vkoul-udesk3>

On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>
mostly looks decent and in shape.

> ---
> +config TI_EDMA
> +	tristate "TI EDMA support"
> +	depends on ARCH_DAVINCI
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS
> +	default y
default should be n for new drivers

> +	help
> +	  Enable support for the TI EDMA controller. This DMA
> +	  engine is found on TI DaVinci and AM33xx parts.
> +
>  config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
>  	bool
>  
> +/* Max of 16 segments per channel to conserve PaRAM slots */
> +#define MAX_NR_SG		16
> +#define EDMA_MAX_SLOTS		MAX_NR_SG
> +#define EDMA_DESCRIPTORS	16
> +
> +struct edma_desc {
> +	struct virt_dma_desc		vdesc;
> +	struct list_head		node;
> +
dummy space?
> +	int				absync;
> +	int				pset_nr;
> +	struct edmacc_param		pset[0];
> +};
> +
> +struct edma_cc;
> +
> +struct edma_chan {
> +	struct virt_dma_chan		vchan;
> +	struct list_head		node;
> +	struct edma_desc		*edesc;
> +	struct edma_cc			*ecc;
> +	int				ch_num;
> +	bool				alloced;
> +	int				slot[EDMA_MAX_SLOTS];
> +
> +	dma_addr_t			addr;
> +	int				addr_width;
> +	int				maxburst;
> +};
> +

> +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> +static void edma_execute(struct edma_chan *echan)
> +{
> +	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
> +	struct edma_desc *edesc;
> +	int i;
> +
> +	if (!vdesc) {
> +		echan->edesc = NULL;
> +		return;
> +	}
> +
> +	list_del(&vdesc->node);
> +
> +	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
> +
> +	/* Write descriptor PaRAM set(s) */
> +	for (i = 0; i < edesc->pset_nr; i++) {
> +		edma_write_slot(echan->slot[i], &edesc->pset[i]);
> +		dev_dbg(echan->vchan.chan.device->dev,
> +			"\n pset[%d]:\n"
> +			"  chnum\t%d\n"
> +			"  slot\t%d\n"
> +			"  opt\t%08x\n"
> +			"  src\t%08x\n"
> +			"  dst\t%08x\n"
> +			"  abcnt\t%08x\n"
> +			"  ccnt\t%08x\n"
> +			"  bidx\t%08x\n"
> +			"  cidx\t%08x\n"
> +			"  lkrld\t%08x\n",
> +			i, echan->ch_num, echan->slot[i],
> +			edesc->pset[i].opt,
> +			edesc->pset[i].src,
> +			edesc->pset[i].dst,
> +			edesc->pset[i].a_b_cnt,
> +			edesc->pset[i].ccnt,
> +			edesc->pset[i].src_dst_bidx,
> +			edesc->pset[i].src_dst_cidx,
> +			edesc->pset[i].link_bcntrld);
> +		/* Link to the previous slot if not the last set */
> +		if (i != (edesc->pset_nr - 1))
> +			edma_link(echan->slot[i], echan->slot[i+1]);
> +		/* Final pset links to the dummy pset */
> +		else
> +			edma_link(echan->slot[i], echan->ecc->dummy_slot);
> +	}
> +
> +	edma_start(echan->ch_num);
> +}
> +
> +static int edma_terminate_all(struct edma_chan *echan)
> +{
> +	unsigned long flags;
> +	LIST_HEAD(head);
> +
> +	spin_lock_irqsave(&echan->vchan.lock, flags);
> +
> +	/*
> +	 * Stop DMA activity: we assume the callback will not be called
> +	 * after edma_dma() returns (even if it does, it will see
> +	 * echan->edesc is NULL and exit.)
> +	 */
> +	if (echan->edesc) {
> +		echan->edesc = NULL;
> +		edma_stop(echan->ch_num);
> +	}
> +
> +	vchan_get_all_descriptors(&echan->vchan, &head);
> +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +	vchan_dma_desc_free_list(&echan->vchan, &head);
> +
> +	return 0;
> +}
> +
> +
> +static int edma_slave_config(struct edma_chan *echan,
> +	struct dma_slave_config *config)
> +{
> +	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> +		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +		return -EINVAL;
the indent needs help here
> +
> +	if (config->direction == DMA_MEM_TO_DEV) {
> +		if (config->dst_addr)
> +			echan->addr = config->dst_addr;
> +		if (config->dst_addr_width)
> +			echan->addr_width = config->dst_addr_width;
> +		if (config->dst_maxburst)
> +			echan->maxburst = config->dst_maxburst;
> +	} else if (config->direction == DMA_DEV_TO_MEM) {
> +		if (config->src_addr)
> +			echan->addr = config->src_addr;
> +		if (config->src_addr_width)
> +			echan->addr_width = config->src_addr_width;
> +		if (config->src_maxburst)
> +			echan->maxburst = config->src_maxburst;
> +	}
> +
> +	return 0;
> +}
> +
> +static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> +			unsigned long arg)
> +{
> +	int ret = 0;
> +	struct dma_slave_config *config;
> +	struct edma_chan *echan = to_edma_chan(chan);
> +
> +	switch (cmd) {
> +	case DMA_TERMINATE_ALL:
> +		edma_terminate_all(echan);
> +		break;
> +	case DMA_SLAVE_CONFIG:
> +		config = (struct dma_slave_config *)arg;
> +		ret = edma_slave_config(echan, config);
> +		break;
> +	default:
> +		ret = -ENOSYS;
> +	}
> +
> +	return ret;
> +}
> +
> +static struct dma_async_tx_descriptor *edma_prep_slave_sg(
> +	struct dma_chan *chan, struct scatterlist *sgl,
> +	unsigned int sg_len, enum dma_transfer_direction direction,
> +	unsigned long tx_flags, void *context)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	struct edma_desc *edesc;
> +	struct scatterlist *sg;
> +	int i;
> +	int acnt, bcnt, ccnt, src, dst, cidx;
> +	int src_bidx, dst_bidx, src_cidx, dst_cidx;
> +
> +	if (unlikely(!echan || !sgl || !sg_len))
> +		return NULL;
> +
> +	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
> +		dev_err(dev, "Undefined slave buswidth\n");
> +		return NULL;
> +	}
> +
> +	if (sg_len > MAX_NR_SG) {
> +		dev_err(dev, "Exceeded max SG segments %d > %d\n",
> +			sg_len, MAX_NR_SG);
> +		return NULL;
> +	}
> +
> +	edesc = kzalloc(sizeof(*edesc) + sg_len *
> +		sizeof(edesc->pset[0]), GFP_ATOMIC);
> +	if (!edesc) {
> +		dev_dbg(dev, "Failed to allocate a descriptor\n");
> +		return NULL;
> +	}
> +
> +	edesc->pset_nr = sg_len;
> +
> +	for_each_sg(sgl, sg, sg_len, i) {
> +		/* Allocate a PaRAM slot, if needed */
> +		if (echan->slot[i] < 0) {
> +			echan->slot[i] =
> +				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
> +						EDMA_SLOT_ANY);
> +			if (echan->slot[i] < 0) {
> +				dev_err(dev, "Failed to allocate slot\n");
> +				return NULL;
> +			}
> +		}
> +
> +		acnt = echan->addr_width;
> +
> +		/*
> +		 * If the maxburst is equal to the fifo width, use
> +		 * A-synced transfers. This allows for large contiguous
> +		 * buffer transfers using only one PaRAM set.
> +		 */
> +		if (echan->maxburst == 1) {
> +			edesc->absync = false;
> +			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
> +			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
> +			if (bcnt)
> +				ccnt++;
> +			else
> +				bcnt = SZ_64K - 1;
> +			cidx = acnt;
> +		/*
> +		 * If maxburst is greater than the fifo address_width,
> +		 * use AB-synced transfers where A count is the fifo
> +		 * address_width and B count is the maxburst. In this
> +		 * case, we are limited to transfers of C count frames
> +		 * of (address_width * maxburst) where C count is limited
> +		 * to SZ_64K-1. This places an upper bound on the length
> +		 * of an SG segment that can be handled.
> +		 */
> +		} else {
> +			edesc->absync = true;
> +			bcnt = echan->maxburst;
> +			ccnt = sg_dma_len(sg) / (acnt * bcnt);
> +			if (ccnt > (SZ_64K - 1)) {
> +				dev_err(dev, "Exceeded max SG segment size\n");
> +				return NULL;
> +			}
> +			cidx = acnt * bcnt;
> +		}
> +
> +		if (direction == DMA_MEM_TO_DEV) {
> +			src = sg_dma_address(sg);
> +			dst = echan->addr;
> +			src_bidx = acnt;
> +			src_cidx = cidx;
> +			dst_bidx = 0;
> +			dst_cidx = 0;
> +		} else {
> +			src = echan->addr;
> +			dst = sg_dma_address(sg);
> +			src_bidx = 0;
> +			src_cidx = 0;
> +			dst_bidx = acnt;
> +			dst_cidx = cidx;
> +		}
> +
> +		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
> +		/* Configure A or AB synchronized transfers */
> +		if (edesc->absync)
> +			edesc->pset[i].opt |= SYNCDIM;
> +		/* If this is the last set, enable completion interrupt flag */
> +		if (i == sg_len - 1)
> +			edesc->pset[i].opt |= TCINTEN;
> +
> +		edesc->pset[i].src = src;
> +		edesc->pset[i].dst = dst;
> +
> +		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
> +		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
> +
> +		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
> +		edesc->pset[i].ccnt = ccnt;
> +		edesc->pset[i].link_bcntrld = 0xffffffff;
> +
> +	}
> +
> +	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
> +}
> +
> +static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
> +{
> +	struct edma_chan *echan = data;
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	struct edma_desc *edesc;
> +	unsigned long flags;
> +
> +	/* Stop the channel */
> +	edma_stop(echan->ch_num);
> +
> +	switch (ch_status) {
> +	case DMA_COMPLETE:
> +		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
> +
> +		spin_lock_irqsave(&echan->vchan.lock, flags);
> +
> +		edesc = echan->edesc;
> +		if (edesc) {
> +			edma_execute(echan);
> +			vchan_cookie_complete(&edesc->vdesc);
> +		}
> +
> +		spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +
> +		break;
> +	case DMA_CC_ERROR:
> +		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +/* Alloc channel resources */
> +static int edma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	int ret;
> +	int a_ch_num;
> +	LIST_HEAD(descs);
> +
> +	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
> +					chan, EVENTQ_DEFAULT);
> +
> +	if (a_ch_num < 0) {
> +		ret = -ENODEV;
> +		goto err_no_chan;
> +	}
> +
> +	if (a_ch_num != echan->ch_num) {
> +		dev_err(dev, "failed to allocate requested channel %u:%u\n",
> +			EDMA_CTLR(echan->ch_num),
> +			EDMA_CHAN_SLOT(echan->ch_num));
> +		ret = -ENODEV;
> +		goto err_wrong_chan;
> +	}
> +
> +	echan->alloced = true;
> +	echan->slot[0] = echan->ch_num;
> +
> +	dev_info(dev, "allocated channel for %u:%u\n",
> +		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
> +
> +	return 0;
> +
> +err_wrong_chan:
> +	edma_free_channel(a_ch_num);
> +err_no_chan:
> +	return ret;
> +}
> +
> +/* Free channel resources */
> +static void edma_free_chan_resources(struct dma_chan *chan)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
perhaps, chan->dev->device
> +	int i;
> +
> +	/* Terminate transfers */
> +	edma_stop(echan->ch_num);
> +
> +	vchan_free_chan_resources(&echan->vchan);
> +
> +	/* Free EDMA PaRAM slots */
> +	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
> +		if (echan->slot[i] >= 0) {
> +			edma_free_slot(echan->slot[i]);
> +			echan->slot[i] = -1;
> +		}
> +	}
> +
> +	/* Free EDMA channel */
> +	if (echan->alloced) {
> +		edma_free_channel(echan->ch_num);
> +		echan->alloced = false;
> +	}
> +
> +	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
> +}
> +
> +static void __init edma_chan_init(struct edma_cc *ecc,
> +				  struct dma_device *dma,
> +				  struct edma_chan *echans)
> +{
> +	int i, j;
> +	int chcnt = 0;
> +
> +	for (i = 0; i < EDMA_CHANS; i++) {
> +		struct edma_chan *echan = &echans[chcnt];
> +		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
> +		echan->ecc = ecc;
> +		echan->vchan.desc_free = edma_desc_free;
> +
> +		vchan_init(&echan->vchan, dma);
> +
> +		INIT_LIST_HEAD(&echan->node);
> +		for (j = 0; j < EDMA_MAX_SLOTS; j++)
> +			echan->slot[j] = -1;
> +
> +		chcnt++;
i see no reason why you cant remove "chcnt" and use "i".
> +	}
> +}
> +
> +static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
> +			  struct device *dev)
> +{
> +	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
> +		dma->device_prep_slave_sg = edma_prep_slave_sg;
You have set DMA_SLAVE unconditionally in your probe, so this seems
bogus.
> +
> +	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
> +	dma->device_free_chan_resources = edma_free_chan_resources;
> +	dma->device_issue_pending = edma_issue_pending;
> +	dma->device_tx_status = edma_tx_status;
> +	dma->device_control = edma_control;
> +	dma->dev = dev;
> +
> +	INIT_LIST_HEAD(&dma->channels);
> +}
> +
> +static int __devinit edma_probe(struct platform_device *pdev)
> +{
> +	struct edma_cc *ecc;
> +	int ret;
> +
> +	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
> +	if (!ecc) {
> +		dev_err(&pdev->dev, "Can't allocate controller\n");
> +		ret = -ENOMEM;
> +		goto err_alloc_ecc;
you can just return here, you are using devm_ friends here
> +	}
> +
> +	ecc->ctlr = pdev->id;
> +	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
> +	if (ecc->dummy_slot < 0) {
> +		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
> +		ret = -EIO;
> +		goto err_alloc_slot;
ditto, just return!
> +	}
> +
> +	dma_cap_zero(ecc->dma_slave.cap_mask);
> +	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
> +
> +	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
> +
> +	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
> +
> +	ret = dma_async_device_register(&ecc->dma_slave);
> +	if (ret)
> +		goto err_reg1;
> +
> +	platform_set_drvdata(pdev, ecc);
> +
> +	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
> +
> +	return 0;
> +
> +err_reg1:
> +	edma_free_slot(ecc->dummy_slot);
> +err_alloc_slot:
> +	devm_kfree(&pdev->dev, ecc);
> +err_alloc_ecc:
> +	return ret;
> +}
> +
> +static int __devexit edma_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct edma_cc *ecc = dev_get_drvdata(dev);
> +
> +	dma_async_device_unregister(&ecc->dma_slave);
> +	edma_free_slot(ecc->dummy_slot);
> +	devm_kfree(dev, ecc);
no need to call this, it is *managed* resource
> +
> +	return 0;
> +}
> +

-- 
~Vinod



From vinod.koul at linux.intel.com  Tue Aug 21 23:45:22 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 22 Aug 2012 09:15:22 +0530
Subject: [PATCH v2 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345574589-24757-4-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-4-git-send-email-mporter@ti.com>
Message-ID: <1345607122.1895.44.camel@vkoul-udesk3>

On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> Removes use of the DaVinci EDMA private DMA API and replaces
> it with use of the DMA engine API.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>
> ---

> +		struct dma_slave_config dma_rx_conf = {
> +			.direction = DMA_DEV_TO_MEM,
> +			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
> +			.src_addr_width = data_type,
> +			.src_maxburst = 1,
what does 1 mean in this context? We define as number of units that
needs to be transfered, so are you sure that you want only one unit to
be dma'ed in a single burst. that seems like killing your dmac,
shouldn't you be using larger bursts for a better dma performance?


-- 
~Vinod



From sboyd at codeaurora.org  Wed Aug 22 00:03:49 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Tue, 21 Aug 2012 21:03:49 -0700
Subject: [RFC/PATCH] ARM: smp: Fix cpu_up() racing with sys_reboot
Message-ID: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>

Nothing stops a process from hotplugging in a CPU concurrently
with a sys_reboot() call. In such a situation we could have
ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
fact that the CPU is not really offline and call the
CPU_UP_PREPARE notifier. When this happens stop_machine code will
complain that the cpu thread already exists and BUG_ON().

CPU0                      CPU1

sys_reboot()
 kernel_restart()
  machine_restart()
   machine_shutdown()
    smp_send_stop()
    ...                   ipi_cpu_stop()
                           set_cpu_online(1, false)
                            local_irq_disable()
                             while(1)
    <PREEMPT>
cpu_up()
 _cpu_up()
   if (!cpu_online(1))
    __cpu_notify(CPU_UP_PREPARE...)

cpu_stop_cpu_callback()
  BUG_ON(stopper->thread)

This is easily reproducible by hotplugging in and out in a tight
loop while also rebooting.

Since the CPU is not really offline and hasn't gone through the
proper steps to be marked as such, let's mark the CPU as inactive.
This is just as easily testable as online and avoids any possibility
of _cpu_up() trying to bring the CPU back online when it never was
offline to begin with.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

Perhaps we can take the hotplug lock in the sys_reboot() case but I
don't think that actually fixes everything. For example, in cases
where machine_shutdown() is called from emergency_restart() we would
have to take the hotplug lock which doesn't really seem feasible.

 arch/arm/kernel/smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..836b771 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -478,7 +478,7 @@ static void ipi_cpu_stop(unsigned int cpu)
 		raw_spin_unlock(&stop_lock);
 	}
 
-	set_cpu_online(cpu, false);
+	set_cpu_active(cpu, false);
 
 	local_fiq_disable();
 	local_irq_disable();
@@ -568,10 +568,10 @@ void smp_send_stop(void)
 
 	/* Wait up to one second for other CPUs to stop */
 	timeout = USEC_PER_SEC;
-	while (num_online_cpus() > 1 && timeout--)
+	while (num_active_cpus() > 1 && timeout--)
 		udelay(1);
 
-	if (num_online_cpus() > 1)
+	if (num_active_cpus() > 1)
 		pr_warning("SMP: failed to stop secondary CPUs\n");
 
 	smp_kill_cpus(&mask);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From vinod.koul at linux.intel.com  Wed Aug 22 00:16:34 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 22 Aug 2012 09:46:34 +0530
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345608994.1895.73.camel@vkoul-udesk3>

On Sat, 2012-08-04 at 10:35 +0200, Julia Lawall wrote:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> Fix some problems with the use of devm_ functions.
Applied, thanks


-- 
~Vinod



From thomas.abraham at linaro.org  Wed Aug 22 00:22:51 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 09:52:51 +0530
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
Message-ID: <CAJuYYwQu7OXQEWCumuMeSKJ2RZD7e==pLKDE1=bvPgfXtO=AUw@mail.gmail.com>

Hi Linus,

Thanks for your time to review the Samsung pinctrl driver patches. I
have inlined the reply to your comments.

On 21 August 2012 16:55, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
>> SoC's.
>
> Thanks for doing this Thomas, great work!
>
>> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>
> I don't understand the rules around bindings very well, I would
> suggest you include
> devicetree-discuss at lists.ozlabs.org on the mails, besides you know
> this stuff way
> better than me anyway :-)

Yes, I missed Cc'ing devicetree-discuss at lists.ozlabs.org. I will do
that in the post of this patch set.

>
>> +  The child node can also optionally specify one or more of the pin
>> +  configuration that should be applied on all the pins listed in the
>> +  "samsung,pins" property of the child node. The following pin configuration
>> +  properties are supported.
>> +
>> +  - samsung,pin-pud: Pull up/down configuration.
>> +  - samsung,pin-drv: Drive strength configuration.
>> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
>> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
>
> This looks a bit scary, as it seems to be orthogonal to the pin config
> interface. I.e. this will be programmed "behind the back" of the
> pin config system. However as long as the pin config implementation
> reads back these things from the registers it will work, too.

These properties are converted to a PIN_MAP_TYPE_CONFIGS_GROUP map
type and stored in a instance of 'struct pinctrl_map'. These can be
read back from the registers and reverse-mapped as well.

All the dt bindings defined and used in the Samsung pinctrl driver are
first translated into pinctrl subystem defined data structures and
then used. Hence, there are no register configurations done that skip
over the pinctrl subsystem (except for the gpio/wakeup interrupts).

>
> In the U300 and Ux500 I explicitly use pin config hogs to set up
> the pin configuration, and when we enter a state such as
> "default" the mux setting and config settings are set from the
> framework separately.
>
> See for example:
> arch/arm/mach-ux500/board-mop500-pins.c
>
> This example is using platform data but it should be trivial to do with
> device tree.
>
> I think the Tegra also works this way. Can you elaborate on
> why you need this static setup from the device tree instead
> of using default states?

Sorry, I did not understand this question.

>
> I also think this looks like it could use generic pin config to stash
> the configs, just expand the stuff in <linux/pinctrl/pinconf-generic.h>
>
> (...)
>> +Example 1:
>
> The examples seem to only pertain to the pin controller per se, maybe you
> could include a DT entry for a uart or something showing how the
> uart device binds to a certain pinctrl setting.

Yes, such an example will be informative here. I will add an example for this.

>
>> +       pinctrl_0: pinctrl at 11400000 {
>> +               compatible = "samsung,pinctrl-exynos4210";
>> +               reg = <0x11400000 0x1000>;
>> +               interrupts = <0 47 0>;
>> +
>> +               uart0_data: uart0-data {
>> +                       samsung,pins = "gpa0-0", "gpa0-1";
>> +                       samsung,pin-function = <2>;
>> +                       samsung,pin-pud = <0>;
>> +                       samsung,pin-drv = <0>;
>> +               };
>
> This setup needs to be associated with a certain state, it's possible to
> do in the code or directly in the device tree.
>
> I.e. these settings for pin-pud and pin-drv needs to belong to a
> certain pin config state, typically the state named "default"

Yes, I agree. So, for example, the uart device node would have

                    uart at 13800000 {
                               compatilble = " .... ";
                               <rest of the properties here>

                               pinctrl-names = "default";
                               pinctrl-0 - <&uart0_data>;
                    };

The uart driver during probe can then call

                   devm_pinctrl_get_select_default(&pdev->dev);

For the example above, this call will set the 'mux', 'pud' and 'drv'
values to gpa-0 and gpa-1 pins.

>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>
>> +config PINCTRL_SAMSUNG
>> +       bool "Samsung pinctrl driver"
>> +       depends on OF
>
> I don't understand how this can even compile. Do you need:
>
> select PINMUX
> select PINCONF
>
> to get the framework files you need to compile?
>
> Or are you selecting thes in some platform Kconfig or so?
> In that case please move them here.

These were selected if PINCTRL_EXYNOS4 config option is selected. This
is in the 2/4 patch of this series. But, as you said, PINMUX and
PINCONF should be selected with PINCTRL_SAMSUNG config option. I will
fix this.

>
>> +/* list of all possible config options supported */
>> +struct pin_config {
>> +       char            *prop_cfg;
>> +       unsigned int    cfg_type;
>> +} pcfgs[] = {
>> +       { "samsung,pin-pud", PINCFG_TYPE_PUD },
>> +       { "samsung,pin-drv", PINCFG_TYPE_DRV },
>> +       { "samsung,pin-pud-pdn", PINCFG_TYPE_CON_PND },
>> +       { "samsung,pin-drv-pdn", PINCFG_TYPE_PUD_PND },
>> +};
>
> Hmmmmm it looks very much like this controller could make use of
> the generic pinconf library, but it's not mandatory so just a suggestion.

Ok. The last two entries in the above table are Samsung specific and
not covered by generic-pinconf. So, I am not sure if it can be added
to generic-pinconf. For now, since you are not enforcing the use of
generic-pinconf, I will keep it the way it is now.

>
> (...)
>> +/* create pinctrl_map entries by parsing device tree nodes */
>> +static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
>> +                       struct device_node *np, struct pinctrl_map **maps,
>> +                       unsigned *nmaps)
>> +{
> (...)
>> +       /* Allocate memory for pin group name. The pin group name is derived
>> +        * from the node name from which these map entries are be created.
>> +        */
>> +       gname = kzalloc(strlen(np->name) + 4, GFP_KERNEL);
>
> Why +4? I would have suspected +1 for the null terminator...

The name of the pin group is derived from the node name and hence
strlen(np->name). To this name, "-grp" is appended to imply that this
is a group. Hence +4 is used. I will replace +4 with probably
strlen(PINGRP_SUFFIX) where PINGRP_SUFFIX is defined as "-grp".

>
>> +       if (!gname) {
>> +               dev_err(dev, "failed to alloc memory for group name\n");
>> +               goto free_map;
>> +       }
>> +       sprintf(gname, "%s-grp", np->name);
>
> The rest of the pinmux implementation looks nice!
>
> (...)
>> +/* set the pull up/down and driver strength settings for a specified pin */
>> +static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
>> +                                       unsigned long config)
>> +{
>> +       struct samsung_pinctrl_drv_data *drvdata;
>> +       unsigned long pin_offset;
>> +       struct samsung_pin_bank *bank;
>> +       void __iomem *reg;
>> +
>> +       drvdata = pinctrl_dev_get_drvdata(pctldev);
>> +       pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg,
>> +                                       &pin_offset, &bank);
>> +
>> +       switch (PINCFG_UNPACK_TYPE(config)) {
>> +       case PINCFG_TYPE_PUD:
>> +               samsung_pinconf_set_pud(drvdata, bank, reg, pin_offset, config);
>> +               break;
>> +       case PINCFG_TYPE_DRV:
>> +               samsung_pinconf_set_drv(drvdata, bank, reg, pin_offset, config);
>> +               break;
>
>
> Hm there are two more types defined in the device tree:
>
> +  - samsung,pin-pud: Pull up/down configuration.
> +  - samsung,pin-drv: Drive strength configuration.
> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
>
> I think you should define these as well, especially if you use the
> states to program these things instead of the hack that I'm quite
> sceptical about...

Yes, I missed setting up those two states. Those are used only during
suspend/resume and hence I over-looked those for now. I will add them
here.

>
>> +/* reading pin pull up/down and driver strength settings not implemented */
>
> OK why not? It seems very simple and straight-forward.
> Just read the same registers and switch() then return...

Ok, I will do that. I did not see how those would be used and hence skipped it.

>
> (...)
>
> The gpiolib part looks really good, so no comments on that.
>
> (...)
>> +               /* derive function name from the node name */
>> +               fname = devm_kzalloc(dev, strlen(cfg_np->name) + 4, GFP_KERNEL);
>
> This +4 again...

Same reason as the previous +4 usage. But this time, -mux is appended
to denote it as function setting. I will rework this.

>
> (...)
>> +       drvdata->grange.name = "samsung-pctrl-gpio-range";
>> +       drvdata->grange.id = 0;
>> +       drvdata->grange.base = drvdata->ctrl->base;
>> +       drvdata->grange.npins = drvdata->ctrl->nr_pins;
>> +       drvdata->grange.gc = drvdata->gc;
>> +       pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange);
>
> Grant didn't like custom ranges at all IIRC and wanted a generic
> way of handling this. But doing so requires turning the range registration
> API:s upside down and let the GPIO controller register the ranges.
>
> If noone else is coding that, I guess we might have to live with
> this kind of custom hacks. (No, I don't have time to fix it, sadly.)

Ok.

>
> (...)
>> +static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
> (...)
>> +       if (ctrl->eint_gpio_init)
>> +               ctrl->eint_gpio_init(drvdata);
>> +       if (ctrl->eint_wkup_init)
>> +               ctrl->eint_wkup_init(drvdata);
>
> So this stuff I'm doing in the default states instead.

These callbacks setup the irq domain and irq_chip for gpio and wakeup
interrupts. These are Samsung specific and are dealt with outside of
the pinctrl subsystem framework.

>
> (...)
>> +++ b/drivers/pinctrl/pinctrl-samsung.h
> (...)
>> +#ifndef __PINCTRL_SAMSUNG_H
>> +#define __PINCTRL_SAMSUNG_H
>> +
>> +#include <linux/module.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +#include <linux/pinctrl/pinmux.h>
>> +#include <linux/pinctrl/pinconf.h>
>> +#include <linux/pinctrl/consumer.h>
>> +#include <linux/pinctrl/machine.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/slab.h>
>> +#include <linux/err.h>
>> +#include <linux/gpio.h>
>
> Usually I prefer to have as many as possible of these in the .c file, but this
> works too, and I haven't seen any rationale about it. Especially since this is
> a local include I can live with it...

Ok. I will move as much as of these as possible into .c files.

>
>
>> +/**
>> + * struct samsung_pin_bank: represent a controller pin-bank.
>> + * @reg_offset: starting offset of the pin-bank registers.
>> + * @pin_base: starting pin number of the bank.
>> + * @nr_pins: number of pins included in this bank.
>> + * @func_width: width of the function selector bit field.
>> + * @pud_width: width of the pin pull up/down selector bit field.
>> + * @drc_width: width of the pin driver strength selector bit field.
>> + * @eint_type: type of the external interrupt supported by the bank.
>> + * @irq_base: starting controller local irq number of the bank.
>> + * @name: name to be prefixed for each pin in this pin bank.
>> + */
>> +struct samsung_pin_bank {
>> +       unsigned int            pctl_offset;
>
> Isn't this a u32?
>
>> +       unsigned int            pin_base;
>> +       unsigned int            nr_pins;
>> +       unsigned int            func_width;
>> +       unsigned int            pud_width;
>> +       unsigned int            drv_width;
>
> Are these "widths" really unsigned (32/64) bits?
> Isn't u8 enough?
>
>> +       unsigned int            eint_type;
>
> Shouldn't this be some kund of enum if it denotes a type?

It was done to reduce adding new data types.

>
>> +       unsigned int            irq_base;
>
> u32?
>
>> +       char                    *name;
>> +};
>> +

Yes, I agree to all the above suggestions on the data types. I will
fix them accordingly.


>> +/**
>> + * struct samsung_pin_ctrl: represent a pin controller.
>> + * @pin_banks: list of pin banks included in this controller.
>> + * @nr_banks: number of pin banks.
>> + * @base: starting system wide pin number.
>> + * @nr_pins: number of pins supported by the controller.
>> + * @nr_gint: number of external gpio interrupts supported.
>> + * @nr_wint: number of external wakeup interrupts supported.
>> + * @geint_con: offset of the ext-gpio controller registers.
>
> If it's an offset why not name it geint_con_offset?

I wanted to keep the lines within 80 columns. Splitting a line into
two lines started making the code look unreadable.

>
>> + * @geint_mask: offset of the ext-gpio interrupt mask registers.
>> + * @geint_pend: offset of the ext-gpio interrupt pending registers.
>> + * @weint_con: offset of the ext-wakeup controller registers.
>> + * @weint_mask: offset of the ext-wakeup interrupt mask registers.
>> + * @weint_pend: offset of the ext-wakeup interrupt pending registers.
>
> Dito.
>
>> + * @svc: offset of the interrupt service register.
>> + * @eint_gpio_init: platform specific callback to setup the external gpio
>> + *     interrupts for the controller.
>> + * @eint_wkup_init: platform specific callback to setup the external wakeup
>> + *     interrupts for the controller.
>> + * @label: for debug information.
>
> Could you add some free text here explaining the hardware just a little
> bit? What is a external GPIO? what is an external wakeup? etc.

Yes, I will do that. As a brief note on this here, the Samsung
pin-controllers support two types of interrupts from the pins,
external gpio and external wakeup interrupts. The external gpio
interrupt

>
>> + */
>> +struct samsung_pin_ctrl {
>> +       struct samsung_pin_bank *pin_banks;
>> +       unsigned int            nr_banks;
>> +
>> +       unsigned int            base;
>
> u32?
>
>> +       unsigned int            nr_pins;
>> +       unsigned int            nr_gint;
>> +       unsigned int            nr_wint;
>> +
>> +       unsigned long           geint_con;
>> +       unsigned long           geint_mask;
>> +       unsigned long           geint_pend;
>
> All three u32?
>
>> +       unsigned long           weint_con;
>
> u32?
>
>> +       unsigned long           weint_mask;
>> +       unsigned long           weint_pend;
>
> u32?
>
>> +       unsigned long           svc;
>
> u32?
>

Yes, I agree to all suggestions on data types. I will fix them.

>> +
>> +       int                     (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
>> +       int                     (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
>
> I guess you need to set up these using auxdata?

No, these are populated by the platform (SoC) specific data that the
Samsung pinctrl driver gets during probe. Due to the differences in
the gpio and wakeup interrupt controllers on Samsung SoC's, the setup
and implementations of these  interrupts have been made SoC specific.
The pinctrl driver is responsible only for initiating the setup of the
gpio/wakeup interrupts.

>
>> +       char                    *label;
>> +};
>> +
>> +/**
>> + * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
>> + * @virt_base: register base address of the controller.
>> + * @dev: device instance representing the controller.
>> + * @irq: interrpt number used by the controller to notify gpio interrupts.
>> + * @ctrl: pin controller instance managed by the driver.
>> + * @pctl: pin controller descriptor registered with the pinctrl subsystem.
>
> Maybe name this pctl_desc then?

This name is used to in multiple places in the code and the longer the
name, there is always the case of the line spilling over 80
characters.

>
>> + * @pctl_dev: cookie representing pinctrl device instance.
>> + * @pin_groups: list of pin groups available to the driver.
>> + * @nr_groups: number of such pin groups.
>> + * @pmx_functions: list of pin functions available to the driver.
>> + * @nr_function: number of such pin functions.
>> + * @gc: gpio_chip instance registered with gpiolib.
>> + * @grange: linux gpio pin range supported by this controller.
>> + */
>> +struct samsung_pinctrl_drv_data {
>> +       void __iomem                    *virt_base;
>> +       struct device                   *dev;
>> +       int                             irq;
>> +
>> +       struct samsung_pin_ctrl         *ctrl;
>> +       struct pinctrl_desc             pctl;
>> +       struct pinctrl_dev              *pctl_dev;
>> +
>> +       const struct samsung_pin_group  *pin_groups;
>> +       unsigned int                    nr_groups;
>> +       const struct samsung_pmx_func   *pmx_functions;
>> +       unsigned int                    nr_functions;
>> +
>> +       struct irq_domain               *gpio_irqd;
>> +       struct irq_domain               *wkup_irqd;
>> +
>> +       struct gpio_chip                *gc;
>> +       struct pinctrl_gpio_range       grange;
>> +};
>
> This is looking really good.
>
> No further comments! (Atleast not this time, since it's a big
> driver I have probably missed something...)
>
> Linus Walleij

Thanks,
Thomas.


From thomas.abraham at linaro.org  Wed Aug 22 00:37:01 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 10:07:01 +0530
Subject: [PATCH v2 2/4] pinctrl: add exynos4210 specific extensions for
 samsung pinctrl driver
In-Reply-To: <CACRpkdYiJOkHrjZ22_0onRHc0ApmBLj+tXPa4SrPo2h0d=fJHA@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-3-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYiJOkHrjZ22_0onRHc0ApmBLj+tXPa4SrPo2h0d=fJHA@mail.gmail.com>
Message-ID: <CAJuYYwRyzKyT97kc9UkPgQq8-1_QwBCfgjnN9sv6ccWtg4Fp0Q@mail.gmail.com>

On 21 August 2012 17:32, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> Add information about the Exynos4210 pin banks and driver data which is
>> used by the Samsung pinctrl driver. In addition to this, the support for
>> external gpio and wakeup interrupt support is included and hooked up with
>> the Samsung pinctrl driver.
>
> OK...
>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> +config PINCTRL_EXYNOS4
>> +       bool "Pinctrl driver data for Exynos4 SoC"
>> +       depends on ARCH_EXYNOS4 && OF
>
> Since you depend on PINCTRL_SAMSUNG which depends
> on OF you don't need to depend on OF here.

Ok.

>
>> +       depends on PINCTRL_SAMSUNG
>> +       select PINMUX
>> +       select PINCONF
>
> So as noted in the main driver, let PINCTRL_SAMSUNG
> select PINMUX and PINCONF and you need only select
> PINCTRL_SAMSUNG here.

Ok.

>
>> diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
> (...)
>> +#include <linux/interrupt.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/irq.h>
>> +#include <linux/of_irq.h>
>
> Do you need these includes? Didn't you put them
> all in "pinctrl-samsung.h"?

Yes, I will fix this.

>
> Overall this looks good and straight-forward, but I cannot figure
> out how the samsung_pinctrl_soc_data is passed to the main
> driver, it seems to be through some DT node but I cannot figure
> this out. Can you explain this?

The main driver uses the .data field of the of_device_id structure to
pass the pointer of the SoC data. So, upon match of a compatible value
which is supported by the main driver with that in dt, the
of_match_node() call can be used to find out the corresponding SoC
data. There are included in the first patch (reference:
samsung_pinctrl_get_soc_data() function and samsung_pinctrl_dt_mach
structure).

>
> Yours,
> Linus Walleij

Thanks,
Thomas.


From thomas.abraham at linaro.org  Wed Aug 22 00:38:48 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 10:08:48 +0530
Subject: [PATCH v2 3/4] gpio: exynos4: skip gpiolib registration if
 pinctrl driver is used
In-Reply-To: <CACRpkdYc-iMgKBNfRmxUFftK78G77qQ8h_Rr5td1-95NGo7wZg@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-4-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYc-iMgKBNfRmxUFftK78G77qQ8h_Rr5td1-95NGo7wZg@mail.gmail.com>
Message-ID: <CAJuYYwSaV9=DiAnv_s0yJJGLYUQrEk+P4s0EyX00-P0ae-WEBQ@mail.gmail.com>

On 21 August 2012 17:35, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> Pinctrl driver, when enabled, registers all the gpio pins and hence the
>> registration of gpio pins by this driver can be skipped.
>>
>> Acked-by: Grant Likely <grant.likely at secretlab.ca>
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>
>> +#ifdef CONFIG_OF
>
> Wouldn't it be better to use
> #ifdef CONFIG_PINCTRL_SAMSUNG?

Yes, this would be better. I will fix this.

>
> Yours,
> Linus Walleij

Thanks,
Thomas.


From thomas.abraham at linaro.org  Wed Aug 22 00:39:34 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 10:09:34 +0530
Subject: [PATCH v2 4/4] ARM: EXYNOS: skip wakeup interrupt setup if
 pinctrl driver is used
In-Reply-To: <CACRpkdaxSZZQwefN3FNvv3ctXFHqaLZoAZ5f8CVu7Tx9n6-v1Q@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-5-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdaxSZZQwefN3FNvv3ctXFHqaLZoAZ5f8CVu7Tx9n6-v1Q@mail.gmail.com>
Message-ID: <CAJuYYwTsYNWRo7uraELdv=KJvXm-7F9JFb9ZrFvEYrcwJvBMmA@mail.gmail.com>

On 21 August 2012 17:34, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> Pinctrl driver includes support for configuring the external wakeup
>> interrupts. On exynos platforms that use pinctrl driver, the setup
>> of wakeup interrupts in the exynos platform code can be skipped.
>>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>
>> +#ifdef CONFIG_OF
>
> Don't you actually want to use:
>
> #fidef CONFIG_PINCTRL_SAMSUNG
>
> here? CONFIG_OF is a bit vague.

Ok. I will use CONFIG_PINCTRL_SAMSUNG here.

>
> Yours,
> Linus Walleij

Thanks,
Thomas.


From thomas.abraham at linaro.org  Wed Aug 22 00:58:08 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 10:28:08 +0530
Subject: [PATCH 2/2] ARM: EXYNOS: Enable PINCTRL config option for Exynos4
 device tree enabled platform
In-Reply-To: <CACRpkda9BiGejU+Qs=1CqKgLxLGumcM4QZOb_og-aAAmKr-0VQ@mail.gmail.com>
References: <1345061442-32378-1-git-send-email-thomas.abraham@linaro.org>
 <1345061442-32378-3-git-send-email-thomas.abraham@linaro.org>
 <CACRpkda9BiGejU+Qs=1CqKgLxLGumcM4QZOb_og-aAAmKr-0VQ@mail.gmail.com>
Message-ID: <CAJuYYwQnia6xB0AgmQ9UKH1Ot+-C=ABzQ7LC8shdjxwKGGP0oA@mail.gmail.com>

On 21 August 2012 18:01, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Wed, Aug 15, 2012 at 10:10 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> This enables support for Samsung and Exynos4 pinctrl driver for device
>> tree enabled Exynos4 platforms.
>>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>>  arch/arm/mach-exynos/Kconfig |    1 +
>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index b5b4c8c..ad96c59 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -405,6 +405,7 @@ config MACH_EXYNOS4_DT
>>         select USE_OF
>>         select ARM_AMBA
>>         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
>> +       select PINCTRL
>
> I don't think this works, since PINCTRL_SAMSUNG is not default "y"
> (nor should it be).

I think I got this wrong. PINCTRL_SAMSUNG depends of OF, which is not
correct. The correct way would be select PINCTRL_SAMSUNG from
PINCTRL_EXYNOS4. I will fix this.

>
> For the platforms I converted I had to select both the subsystem and
> the indivudual driver, as is already done for some GPIO controllers
> for example:
>
> select PINCTRL
> select PINCTRL_SAMSUNG
>
> Yours,
> Linus Walleij

Thanks,
Thomas.


From thomas.abraham at linaro.org  Wed Aug 22 01:00:02 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 22 Aug 2012 10:30:02 +0530
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <5033FFE0.5070209@wwwdotorg.org>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
 <5033FFE0.5070209@wwwdotorg.org>
Message-ID: <CAJuYYwQx35bNJdNeNexGoxzenstT7GaOLa3=+6uYMMGoYrCtRQ@mail.gmail.com>

On 22 August 2012 03:08, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/21/2012 05:25 AM, Linus Walleij wrote:
>> On Wed, Aug 15, 2012 at 9:57 PM, Thomas Abraham
>> <thomas.abraham at linaro.org> wrote:
>>
>>> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
>>> SoC's.
> ...
>>> +  The child node can also optionally specify one or more of the pin
>>> +  configuration that should be applied on all the pins listed in the
>>> +  "samsung,pins" property of the child node. The following pin configuration
>>> +  properties are supported.
>>> +
>>> +  - samsung,pin-pud: Pull up/down configuration.
>>> +  - samsung,pin-drv: Drive strength configuration.
>>> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
>>> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
>>
>> This looks a bit scary, as it seems to be orthogonal to the pin config
>> interface. I.e. this will be programmed "behind the back" of the
>> pin config system. However as long as the pin config implementation
>> reads back these things from the registers it will work, too.
>>
>> In the U300 and Ux500 I explicitly use pin config hogs to set up
>> the pin configuration, and when we enter a state such as
>> "default" the mux setting and config settings are set from the
>> framework separately.
>
> I know that some HW has a separate set of registers (or fields) for the
> "awake" and "sleep" configuration, and the HW switches between the two
> automatically when sleeping. I have no idea if the Samsung SoCs do this,
> but I think if this were the case, it'd be quite legitimate to define
> both these HW states as separate sets of properties within a single
> pinctrl SW state. So, that might be the explanation here?
>

Hi Stephen,

Yes, Samsung SoC support the "awake" and "sleep" configuration in that
way you described.

Thanks,
Thomas.


From 21cnbao at gmail.com  Wed Aug 22 01:25:11 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 22 Aug 2012 13:25:11 +0800
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <1345608994.1895.73.camel@vkoul-udesk3>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345608994.1895.73.camel@vkoul-udesk3>
Message-ID: <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>

2012/8/22 Vinod Koul <vinod.koul at linux.intel.com>:
> On Sat, 2012-08-04 at 10:35 +0200, Julia Lawall wrote:
>> From: Julia Lawall <Julia.Lawall at lip6.fr>
>>
>> Fix some problems with the use of devm_ functions.
> Applied, thanks

the git log "drivers/dma/sirf-dma.c: fix usage of devm functions"
should be fixed.

>
>
> --
> ~Vinod
>

-barry


From julia.lawall at lip6.fr  Wed Aug 22 01:30:44 2012
From: julia.lawall at lip6.fr (Julia Lawall)
Date: Wed, 22 Aug 2012 07:30:44 +0200 (CEST)
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345608994.1895.73.camel@vkoul-udesk3>
 <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>
Message-ID: <alpine.DEB.2.02.1208220729440.1966@localhost6.localdomain6>

On Wed, 22 Aug 2012, Barry Song wrote:

> 2012/8/22 Vinod Koul <vinod.koul at linux.intel.com>:
>> On Sat, 2012-08-04 at 10:35 +0200, Julia Lawall wrote:
>>> From: Julia Lawall <Julia.Lawall at lip6.fr>
>>>
>>> Fix some problems with the use of devm_ functions.
>> Applied, thanks
>
> the git log "drivers/dma/sirf-dma.c: fix usage of devm functions"
> should be fixed.

What do you suggest?  The patch is about problems with the use of 
devm_kzalloc, devm_ioremap, and devm_request_irq.

thanks,
julia

>
>>
>>
>> --
>> ~Vinod
>>
>
> -barry
> --
> To unsubscribe from this list: send the line "unsubscribe kernel-janitors" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From hdoyu at nvidia.com  Wed Aug 22 01:30:53 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 08:30:53 +0300
Subject: [Linaro-mm-sig] [PATCH 2/3] ARM: DMA-Mapping: print warning
 when atomic coherent allocation fails
In-Reply-To: <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-3-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120822083053.42efc6162076534250112652@nvidia.com>

On Mon, 20 Aug 2012 12:47:27 +0200
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> Print a loud warning when system runs out of memory from atomic coherent
> pool to let users notice the potential problem.
> 
> Reported-by: Aaro Koskinen <aaro.koskinen at iki.fi>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> ---
>  arch/arm/mm/dma-mapping.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index d1cc9c1..25963ea 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -461,6 +461,9 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
>  		bitmap_set(pool->bitmap, pageno, count);
>  		ptr = pool->vaddr + PAGE_SIZE * pageno;
>  		*ret_page = pool->page + pageno;
> +	} else {
> +		pr_err("Atomic coherent pool too small!\n"
> +		       "Please increase it with  kernel parameter!\n");

It might be a little bit nicer if the current pool size is printed in
the above too. That could be the hint for how much to specify in
"coherent_pool=".



From 21cnbao at gmail.com  Wed Aug 22 01:41:42 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 22 Aug 2012 13:41:42 +0800
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <alpine.DEB.2.02.1208220729440.1966@localhost6.localdomain6>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345608994.1895.73.camel@vkoul-udesk3>
 <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>
 <alpine.DEB.2.02.1208220729440.1966@localhost6.localdomain6>
Message-ID: <CAGsJ_4wkyY7VkrgMwGwmFF4kpGiGEtU8Ox46G-yOspAi27Lqgg@mail.gmail.com>

2012/8/22 Julia Lawall <julia.lawall at lip6.fr>:
> On Wed, 22 Aug 2012, Barry Song wrote:
>
>> 2012/8/22 Vinod Koul <vinod.koul at linux.intel.com>:
>>>
>>> On Sat, 2012-08-04 at 10:35 +0200, Julia Lawall wrote:
>>>>
>>>> From: Julia Lawall <Julia.Lawall at lip6.fr>
>>>>
>>>> Fix some problems with the use of devm_ functions.
>>>
>>> Applied, thanks
>>
>>
>> the git log "drivers/dma/sirf-dma.c: fix usage of devm functions"
>> should be fixed.
>
>
> What do you suggest?  The patch is about problems with the use of
> devm_kzalloc, devm_ioremap, and devm_request_irq.

i mean the prefix

dmaengine: sirf: .............

>
> thanks,
> julia

-barry


From omar.luna at linaro.org  Wed Aug 22 01:42:28 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Wed, 22 Aug 2012 00:42:28 -0500
Subject: [PATCH 0/2] OMAP: hwmod: fix hardreset handling
Message-ID: <1345614150-25723-1-git-send-email-omar.luna@linaro.org>

From: Omar Ramirez Luna <omar.ramirez at ti.com>

The patch to expose hwmod assert/deassert functions through omap_device
has been accepted and queued for 3.7[1], however these two patches are
needed to make the API functional. Hence a revised version is being sent
according to previous comments:

- ARM: OMAP: hwmod: revise deassert sequence
Now it uses enable|disable_module to handle the configuration of the
modulemode inside CLKCTRL. As part of the cleanup of leaf clocks, the
one associated with ipu_mmu will be removed along with the iommu hwmod
migration[2].

- ARM: OMAP: hwmod: partially un-reset hwmods might not be properly
  enabled
More infomation added in the patch description[3].

[1] http://patchwork.kernel.org/patch/1266731/
[2] http://patchwork.kernel.org/patch/1201791/
[3] http://patchwork.kernel.org/patch/1201801/

Omar Ramirez Luna (2):
  ARM: OMAP: hwmod: partially un-reset hwmods might not be properly
    enabled
  ARM: OMAP: hwmod: revise deassert sequence

 arch/arm/mach-omap2/omap_hwmod.c |   74 ++++++++++++++++++++++++++++++--------
 1 file changed, 59 insertions(+), 15 deletions(-)

-- 
1.7.9.5



From omar.luna at linaro.org  Wed Aug 22 01:42:29 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Wed, 22 Aug 2012 00:42:29 -0500
Subject: [PATCH 1/2] ARM: OMAP: hwmod: partially un-reset hwmods might not be
 properly enabled
In-Reply-To: <1345614150-25723-1-git-send-email-omar.luna@linaro.org>
References: <1345614150-25723-1-git-send-email-omar.luna@linaro.org>
Message-ID: <1345614150-25723-2-git-send-email-omar.luna@linaro.org>

Some IP blocks might not be using/controlling more than one
reset line, this check loosens the restriction to fully use
hwmod framework for those drivers.

E.g.: ipu has reset lines: mmu_cache, cpu0 and cpu1.
- As of now cpu1 is not used and hence (with previous check) the
  IP block isn't fully enabled by hwmod code.
- Usually ipu and dsp processors configure their mmu module first
  and then enable the processors, this involves:
    * Deasserting mmu reset line, and enabling the module.
    * Deasserting cpu0 reset line, and enabling the processor.
  The ones portrayed in this example are controlled through
  rproc_fw_boot in drivers/remoteproc/remoteproc_core.c

While at it, prevent _omap4_module_disable if all the hardreset
lines on an IP block are not under reset.

This will allow the driver to:
  a. Deassert the reset line.
  b. Enable the hwmod through runtime PM default callbacks.
  c. Do its usecase.
  d. Disable hwmod through runtime PM.
  e. Assert the reset line.

Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
---
 arch/arm/mach-omap2/omap_hwmod.c |   37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..eaedc33 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1558,25 +1558,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 
 /**
- * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
  * @oh: struct omap_hwmod *
  *
- * If any hardreset line associated with @oh is asserted, then return true.
- * Otherwise, if @oh has no hardreset lines associated with it, or if
- * no hardreset lines associated with @oh are asserted, then return false.
+ * If all hardreset lines associated with @oh are asserted, then return true.
+ * Otherwise, if part of @oh is out hardreset or if no hardreset lines
+ * associated with @oh are asserted, then return false.
  * This function is used to avoid executing some parts of the IP block
- * enable/disable sequence if a hardreset line is set.
+ * enable/disable sequence if its hardreset line is set.
  */
-static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
 {
-	int i;
+	int i, rst_cnt = 0;
 
 	if (oh->rst_lines_cnt == 0)
 		return false;
 
 	for (i = 0; i < oh->rst_lines_cnt; i++)
 		if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
-			return true;
+			rst_cnt++;
+
+	if (oh->rst_lines_cnt == rst_cnt)
+		return true;
 
 	return false;
 }
@@ -1595,6 +1598,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
 		return -EINVAL;
 
+	/*
+	 * Since integration code might still be doing something, only
+	 * disable if all lines are under hardreset.
+	 */
+	if (!_are_all_hardreset_lines_asserted(oh))
+		return 0;
+
 	pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
 
 	omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@@ -1602,9 +1612,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 				    oh->clkdm->clkdm_offs,
 				    oh->prcm.omap4.clkctrl_offs);
 
-	if (_are_any_hardreset_lines_asserted(oh))
-		return 0;
-
 	v = _omap4_wait_target_disable(oh);
 	if (v)
 		pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
@@ -1830,7 +1837,7 @@ static int _enable(struct omap_hwmod *oh)
 	}
 
 	/*
-	 * If an IP block contains HW reset lines and any of them are
+	 * If an IP block contains HW reset lines and all of them are
 	 * asserted, we let integration code associated with that
 	 * block handle the enable.  We've received very little
 	 * information on what those driver authors need, and until
@@ -1838,7 +1845,7 @@ static int _enable(struct omap_hwmod *oh)
 	 * posted to the public lists, this is probably the best we
 	 * can do.
 	 */
-	if (_are_any_hardreset_lines_asserted(oh))
+	if (_are_all_hardreset_lines_asserted(oh))
 		return 0;
 
 	/* Mux pins for device runtime if populated */
@@ -1918,7 +1925,7 @@ static int _idle(struct omap_hwmod *oh)
 		return -EINVAL;
 	}
 
-	if (_are_any_hardreset_lines_asserted(oh))
+	if (_are_all_hardreset_lines_asserted(oh))
 		return 0;
 
 	if (oh->class->sysc)
@@ -2006,7 +2013,7 @@ static int _shutdown(struct omap_hwmod *oh)
 		return -EINVAL;
 	}
 
-	if (_are_any_hardreset_lines_asserted(oh))
+	if (_are_all_hardreset_lines_asserted(oh))
 		return 0;
 
 	pr_debug("omap_hwmod: %s: disabling\n", oh->name);
-- 
1.7.9.5



From omar.luna at linaro.org  Wed Aug 22 01:42:30 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Wed, 22 Aug 2012 00:42:30 -0500
Subject: [PATCH 2/2] ARM: OMAP: hwmod: revise deassert sequence
In-Reply-To: <1345614150-25723-1-git-send-email-omar.luna@linaro.org>
References: <1345614150-25723-1-git-send-email-omar.luna@linaro.org>
Message-ID: <1345614150-25723-3-git-send-email-omar.luna@linaro.org>

For a reset sequence to complete cleanly, a module needs its
associated clocks to be enabled, otherwise the timeout check
in prcm code can print a false failure (failed to hardreset)
that occurs because the clocks aren't powered ON and the status
bit checked can't transition without them.

Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
---
 arch/arm/mach-omap2/omap_hwmod.c |   37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eaedc33..b65e021 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1509,6 +1509,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
 	struct omap_hwmod_rst_info ohri;
 	int ret = -EINVAL;
+	int hwsup = 0;
 
 	if (!oh)
 		return -EINVAL;
@@ -1520,10 +1521,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;
 
+	if (oh->clkdm) {
+		/*
+		 * A clockdomain must be in SW_SUP otherwise reset
+		 * might not be completed. The clockdomain can be set
+		 * in HW_AUTO only when the module become ready.
+		 */
+		hwsup = clkdm_in_hwsup(oh->clkdm);
+		ret = clkdm_hwmod_enable(oh->clkdm, oh);
+		if (ret) {
+			WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+			     oh->name, oh->clkdm->name, ret);
+			return ret;
+		}
+	}
+
+	_enable_clocks(oh);
+	if (soc_ops.enable_module)
+		soc_ops.enable_module(oh);
+
 	ret = soc_ops.deassert_hardreset(oh, &ohri);
+
+	if (soc_ops.disable_module)
+		soc_ops.disable_module(oh);
+	_disable_clocks(oh);
+
 	if (ret == -EBUSY)
 		pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
+	if (!ret) {
+		/*
+		 * Set the clockdomain to HW_AUTO, assuming that the
+		 * previous state was HW_AUTO.
+		 */
+		if (oh->clkdm && hwsup)
+			clkdm_allow_idle(oh->clkdm);
+	} else {
+		if (oh->clkdm)
+			clkdm_hwmod_disable(oh->clkdm, oh);
+	}
+
 	return ret;
 }
 
-- 
1.7.9.5



From tomi.valkeinen at ti.com  Wed Aug 22 02:24:37 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 22 Aug 2012 09:24:37 +0300
Subject: [PATCH 0/3] ARM: OMAP2/3: DSS HWMOD fixes
In-Reply-To: <alpine.DEB.2.00.1207040610310.6760@utopia.booyaka.com>
References: <1336645264-909-1-git-send-email-tomi.valkeinen@ti.com>
 <alpine.DEB.2.00.1206271416420.27496@utopia.booyaka.com>
 <alpine.DEB.2.00.1207040610310.6760@utopia.booyaka.com>
Message-ID: <1345616677.3036.3.camel@deskari>

On Wed, 2012-07-04 at 06:11 -0600, Paul Walmsley wrote:
> Hi Tomi
> 
> On Wed, 27 Jun 2012, Paul Walmsley wrote:
> 
> > On Thu, 10 May 2012, Tomi Valkeinen wrote:
> > 
> > > These patches fix DSS hwmod data related to sysc flags. I haven't seen any
> > > problem produced by these missing bits, but by looking at the TRM it's clear
> > > that they should be defined.
> > > 
> > > However, applying these will cause additional warnings to show during boot:
> > > 
> > > omap_hwmod: dss_dispc: softreset failed (waited 10000 usec)
> > > omap_hwmod: dss_rfbi: softreset failed (waited 10000 usec)
> > > 
> > > Most likely the softreset fails even now, but as there's no check to verify it,
> > > no warnings are visible.
> > > 
> > > I think the reason for the failing softreset is the same problem as we have on
> > > OMAP4: dss_core hwmod should be enabled before other dss hwmods can be enabled
> > > (and reset).
> > 
> > Thanks, queued for 3.6.
> > 
> > Not sure what to do about the softreset issues at the moment, due to 
> > competing priorities.  But for sure the data should match the hardware.
> 
> I've dropped these for 3.6 since they cause a PM regression during a 
> system suspend test:
> 
> [   39.721282] Powerdomain (dss_pwrdm) didn't enter target state 1
> 
> Probably before we can pull these in, we need to figure out what's going 
> on there.

I was testing with omap3 overo, on v3.6-rc2 +
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
fixes-for-linus

I don't seem to be able to enter full suspend even without dss. This is
with DSS compiled as modules, and not loaded:

# echo mem > /sys/power/state 
[   21.697265] PM: Syncing filesystems ... done.
[   21.711059] Freezing user space processes ... (elapsed 0.02 seconds) done.
[   21.740722] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
[   21.911407] PM: suspend of devices complete after 134.399 msecs
[   21.921874] PM: late suspend of devices complete after 4.150 msecs
[   21.934753] PM: noirq suspend of devices complete after 6.256 msecs
[   21.941467] Disabling non-boot CPUs ...
[   24.639495] Powerdomain (iva2_pwrdm) didn't enter target state 1
[   24.645812] Powerdomain (dss_pwrdm) didn't enter target state 1
[   24.652008] Powerdomain (per_pwrdm) didn't enter target state 1
[   24.658233] Powerdomain (core_pwrdm) didn't enter target state 1
[   24.664550] Powerdomain (usbhost_pwrdm) didn't enter target state 1
[   24.671112] Could not enter target state in pm_suspend
[   24.679901] PM: noirq resume of devices complete after 3.173 msecs
[   24.691101] PM: early resume of devices complete after 2.716 msecs
[   25.086517] PM: resume of devices complete after 388.793 msecs
[   25.097564] Restarting tasks ... done.

There's also still the old bug that happens if I have USB ethernet
gadget as built-in:

# echo mem > /sys/power/state 
[   25.011657] PM: Syncing filesystems ... done.
[   25.026184] Freezing user space processes ... (elapsed 0.02 seconds) done.
[   25.055145] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
[   25.086303] Suspending console(s) (use no_console_suspend to debug)
[   25.264953] PM: suspend of devices complete after 166.717 msecs
[   25.269348] PM: late suspend of devices complete after 4.394 msecs
[   25.275482] twl: i2c_read failed to transfer all messages
[   25.275543] twl: i2c_write failed to transfer all messages
[   25.275604] twl: i2c_write failed to transfer all messages
[   25.275634] ------------[ cut here ]------------
[   25.275665] WARNING: at drivers/usb/otg/twl4030-usb.c:360 __twl4030_phy_power+0x88/0x98()
[   25.275665] Modules linked in:
[   25.275726] [<c001b8cc>] (unwind_backtrace+0x0/0xf0) from [<c004217c>] (warn_slowpath_common+0x4c
/0x64)
[   25.275756] [<c004217c>] (warn_slowpath_common+0x4c/0x64) from [<c00421b0>] (warn_slowpath_null+0
x1c/0x24)
[   25.275787] [<c00421b0>] (warn_slowpath_null+0x1c/0x24) from [<c03babe8>] (__twl4030_phy_power+0x
88/0x98)
[   25.275787] [<c03babe8>] (__twl4030_phy_power+0x88/0x98) from [<c03bac84>] (twl4030_phy_power+0x8
c/0xf4)
[   25.275817] [<c03bac84>] (twl4030_phy_power+0x8c/0xf4) from [<c03bad90>] (twl4030_phy_suspend.clo
ne.7+0x18/0x44)
[   25.275848] [<c03bad90>] (twl4030_phy_suspend.clone.7+0x18/0x44) from [<c03bae38>] (twl4030_set_s
uspend+0x1c/0x24)
[   25.275878] [<c03bae38>] (twl4030_set_suspend+0x1c/0x24) from [<c03d92ec>] (omap2430_runtime_susp
end+0x4c/0x54)
[   25.275909] [<c03d92ec>] (omap2430_runtime_suspend+0x4c/0x54) from [<c0328b10>] (pm_generic_runti
me_suspend+0x2c/0x40)
[   25.275939] [<c0328b10>] (pm_generic_runtime_suspend+0x2c/0x40) from [<c003dcd0>] (_od_suspend_no
irq+0x34/0x68)
[   25.275939] [<c003dcd0>] (_od_suspend_noirq+0x34/0x68) from [<c0329bf0>] (dpm_run_callback.clone.
10+0x30/0xb4)
[   25.275970] [<c0329bf0>] (dpm_run_callback.clone.10+0x30/0xb4) from [<c032a3c4>] (dpm_suspend_end
+0x30c/0x514)
[   25.276000] [<c032a3c4>] (dpm_suspend_end+0x30c/0x514) from [<c00830c0>] (suspend_devices_and_ent
er+0xbc/0x2d0)
[   25.276031] [<c00830c0>] (suspend_devices_and_enter+0xbc/0x2d0) from [<c0083460>] (pm_suspend+0x1
8c/0x208)
[   25.276031] [<c0083460>] (pm_suspend+0x18c/0x208) from [<c00826f4>] (state_store+0x120/0x134)
[   25.276062] [<c00826f4>] (state_store+0x120/0x134) from [<c02c0b10>] (kobj_attr_store+0x14/0x20)
[   25.276092] [<c02c0b10>] (kobj_attr_store+0x14/0x20) from [<c0170668>] (sysfs_write_file+0x100/0x
184)
[   25.276123] [<c0170668>] (sysfs_write_file+0x100/0x184) from [<c010e238>] (vfs_write+0xb4/0x148)
[   25.276153] [<c010e238>] (vfs_write+0xb4/0x148) from [<c010e4c0>] (sys_write+0x40/0x70)
[   25.276184] [<c010e4c0>] (sys_write+0x40/0x70) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   25.276184] ---[ end trace 7ca935fb21bbfe5c ]---
[   25.276397] twl: i2c_read failed to transfer all messages
[   25.276397] VUSB1V5: failed to disable
[   25.276428] twl: i2c_read failed to transfer all messages
[   25.276428] VUSB1V8: failed to disable
[   25.276458] twl: i2c_read failed to transfer all messages
[   25.276489] VUSB3V1: failed to disable
[   25.277252] PM: noirq suspend of devices complete after 7.843 msecs
[   25.277313] Disabling non-boot CPUs ...
[   27.809631] Powerdomain (iva2_pwrdm) didn't enter target state 1
[   27.809631] Powerdomain (dss_pwrdm) didn't enter target state 1
[   27.809631] Powerdomain (per_pwrdm) didn't enter target state 1
[   27.809661] Powerdomain (core_pwrdm) didn't enter target state 1
[   27.809661] Powerdomain (usbhost_pwrdm) didn't enter target state 1
[   27.809661] Could not enter target state in pm_suspend
[   27.810699] twl: i2c_write failed to transfer all messages
[   27.810760] twl: i2c_read failed to transfer all messages
[   27.810791] twl: i2c_write failed to transfer all messages
[   27.810821] twl: i2c_write failed to transfer all messages
[   27.810852] ------------[ cut here ]------------
[   27.810882] WARNING: at drivers/usb/otg/twl4030-usb.c:360 __twl4030_phy_power+0x88/0x98()
[   27.810913] Modules linked in:
[   27.810943] [<c001b8cc>] (unwind_backtrace+0x0/0xf0) from [<c004217c>] (warn_slowpath_common+0x4c
/0x64)
[   27.810974] [<c004217c>] (warn_slowpath_common+0x4c/0x64) from [<c00421b0>] (warn_slowpath_null+0
x1c/0x24)
[   27.810974] [<c00421b0>] (warn_slowpath_null+0x1c/0x24) from [<c03babe8>] (__twl4030_phy_power+0x
88/0x98)
[   27.811004] [<c03babe8>] (__twl4030_phy_power+0x88/0x98) from [<c03bac40>] (twl4030_phy_power+0x4
8/0xf4)
[   27.811035] [<c03bac40>] (twl4030_phy_power+0x48/0xf4) from [<c03bacfc>] (__twl4030_phy_resume+0x
10/0x48)
[   27.811065] [<c03bacfc>] (__twl4030_phy_resume+0x10/0x48) from [<c03bad4c>] (twl4030_phy_resume+0
x18/0x44)
[   27.811065] [<c03bad4c>] (twl4030_phy_resume+0x18/0x44) from [<c03bae2c>] (twl4030_set_suspend+0x
10/0x24)
[   27.811096] [<c03bae2c>] (twl4030_set_suspend+0x10/0x24) from [<c03d9298>] (omap2430_runtime_resu
me+0x50/0x58)
[   27.811126] [<c03d9298>] (omap2430_runtime_resume+0x50/0x58) from [<c0328b50>] (pm_generic_runtim
e_resume+0x2c/0x40)
[   27.811157] [<c0328b50>] (pm_generic_runtime_resume+0x2c/0x40) from [<c003dc10>] (_od_resume_noir
q+0x44/0x58)
[   27.811187] [<c003dc10>] (_od_resume_noirq+0x44/0x58) from [<c0329bf0>] (dpm_run_callback.clone.1
0+0x30/0xb4)
[   27.811187] [<c0329bf0>] (dpm_run_callback.clone.10+0x30/0xb4) from [<c0329d00>] (dpm_resume_noir
q+0x8c/0x224)
[   27.811218] [<c0329d00>] (dpm_resume_noirq+0x8c/0x224) from [<c032a5d8>] (dpm_resume_start+0xc/0x
18)
[   27.811248] [<c032a5d8>] (dpm_resume_start+0xc/0x18) from [<c0083118>] (suspend_devices_and_enter
+0x114/0x2d0)
[   27.811279] [<c0083118>] (suspend_devices_and_enter+0x114/0x2d0) from [<c0083460>] (pm_suspend+0x
18c/0x208)
[   27.811279] [<c0083460>] (pm_suspend+0x18c/0x208) from [<c00826f4>] (state_store+0x120/0x134)
[   27.811309] [<c00826f4>] (state_store+0x120/0x134) from [<c02c0b10>] (kobj_attr_store+0x14/0x20)
[   27.811340] [<c02c0b10>] (kobj_attr_store+0x14/0x20) from [<c0170668>] (sysfs_write_file+0x100/0x
184)
[   27.811370] [<c0170668>] (sysfs_write_file+0x100/0x184) from [<c010e238>] (vfs_write+0xb4/0x148)
[   27.811401] [<c010e238>] (vfs_write+0xb4/0x148) from [<c010e4c0>] (sys_write+0x40/0x70)
[   27.811401] [<c010e4c0>] (sys_write+0x40/0x70) from [<c0013ee0>] (ret_fast_syscall+0x0/0x3c)
[   27.811431] ---[ end trace 7ca935fb21bbfe5d ]---
[   27.811462] twl: i2c_read failed to transfer all messages
[   27.811492] twl: i2c_write failed to transfer all messages
[   27.811523] twl: i2c_read failed to transfer all messages
[   27.811553] twl: i2c_write failed to transfer all messages
[   27.811614] twl: i2c_write failed to transfer all messages
[   27.811645] twl: i2c_write failed to transfer all messages
[   27.811676] twl: i2c_read failed to transfer all messages
[   27.814544] PM: noirq resume of devices complete after 4.638 msecs
[   27.819000] PM: early resume of devices complete after 2.960 msecs
[   28.240875] PM: resume of devices complete after 421.783 msecs
[   28.878845] Restarting tasks ... done.
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From vinod.koul at linux.intel.com  Wed Aug 22 02:34:35 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 22 Aug 2012 12:04:35 +0530
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <CAGsJ_4wkyY7VkrgMwGwmFF4kpGiGEtU8Ox46G-yOspAi27Lqgg@mail.gmail.com>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345608994.1895.73.camel@vkoul-udesk3>
 <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>
 <alpine.DEB.2.02.1208220729440.1966@localhost6.localdomain6>
 <CAGsJ_4wkyY7VkrgMwGwmFF4kpGiGEtU8Ox46G-yOspAi27Lqgg@mail.gmail.com>
Message-ID: <1345617275.1895.83.camel@vkoul-udesk3>

On Wed, 2012-08-22 at 13:41 +0800, Barry Song wrote:
> >>
> >>
> >> the git log "drivers/dma/sirf-dma.c: fix usage of devm functions"
> >> should be fixed.
> >
> >
> > What do you suggest?  The patch is about problems with the use of
> > devm_kzalloc, devm_ioremap, and devm_request_irq.
> 
> i mean the prefix
> 
> dmaengine: sirf: .............
That is the usual way, it helps if you see the notation used by
subsystem by checking patches being sent to subsystem, but it is not a
really big deal, pls take care of this in future.


-- 
~Vinod



From linux at prisktech.co.nz  Wed Aug 22 02:34:38 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 18:34:38 +1200
Subject: [PATCHv3 3/9] serial: vt8500: Add devicetree support for
In-Reply-To: <20120821231255.71a7515a@pyramind.ukuu.org.uk>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-4-git-send-email-linux@prisktech.co.nz>
 <20120821231255.71a7515a@pyramind.ukuu.org.uk>
Message-ID: <1345617278.7491.4.camel@gitbox>

On Tue, 2012-08-21 at 23:12 +0100, Alan Cox wrote:
> On Wed, 22 Aug 2012 08:47:32 +1200
> Tony Prisk <linux at prisktech.co.nz> wrote:
> 
> > Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
> > ---
> >  drivers/tty/serial/vt8500_serial.c |   37 ++++++++++++++++++++++++++++++++----
> >  1 file changed, 33 insertions(+), 4 deletions(-)
> 
> Can we have a comment attached to a change this size. In particular one
> describing why it gone from 4 to 6 ports, and why the port id twiddling.
> 
> Is there a reason you can't use the device tree port id ?
> 
> What are the regression risks for existing users expecting the pdev->id
> binding ?
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Sorry Alan,

The original patch was very simple, but I revisited it to fix other
issues and forgot to add the relevant comments.

Port size is changed to fix a problem - WM8505 actually had 6 uart's
defined in platform data but the vt8500_ports variable was only 4.

I have added devicetree port id support as well.

No regression risks as the entire platform is being converted to
devicetree and existing code dropped in this patchset.

Patchv4 3/9 to follow.

Regards

Tony Prisk



From linux at prisktech.co.nz  Wed Aug 22 02:37:36 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 18:37:36 +1200
Subject: [PATCHv4 3/9] serial: vt8500: Add devicetree support for vt8500-serial
Message-ID: <1345617456-10930-1-git-send-email-linux@prisktech.co.nz>

Increase vt8500_max_ports to 6 as the WM8505 has 6 available uarts.
Added max_ports range checking to prevent addressing overflow.
Use devicetree port id as primary addressing for ports but allow
auto-allocation if id not specified.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/tty/serial/vt8500_serial.c |   44 ++++++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006f..c10e21a 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -76,6 +77,8 @@
 #define RX_FIFO_INTS	(RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
 #define TX_FIFO_INTS	(TXFAE | TXFE | TXUDR)
 
+#define VT8500_MAX_PORTS	6
+
 struct vt8500_port {
 	struct uart_port	uart;
 	char			name[16];
@@ -83,6 +86,13 @@ struct vt8500_port {
 	unsigned int		ier;
 };
 
+/*
+ * we use this variable to keep track of which ports
+ * have been allocated as we can't use pdev->id in
+ * devicetree
+ */
+static unsigned long vt8500_ports_in_use;
+
 static inline void vt8500_write(struct uart_port *port, unsigned int val,
 			     unsigned int off)
 {
@@ -431,7 +441,7 @@ static int vt8500_verify_port(struct uart_port *port,
 	return 0;
 }
 
-static struct vt8500_port *vt8500_uart_ports[4];
+static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
 static struct uart_driver vt8500_uart_driver;
 
 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
@@ -548,7 +558,9 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 {
 	struct vt8500_port *vt8500_port;
 	struct resource *mmres, *irqres;
+	struct device_node *np = pdev->dev.of_node;
 	int ret;
+	int port;
 
 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -559,13 +571,31 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 	if (!vt8500_port)
 		return -ENOMEM;
 
+	if (np)
+		port = of_alias_get_id(np, "serial");
+
+	if (port < 0) {
+		/* calculate the port id */
+		port = find_first_zero_bit(&vt8500_ports_in_use,
+					sizeof(vt8500_ports_in_use));
+	}
+
+	if (port > VT8500_MAX_PORTS)
+		return -ENODEV;
+
+	/* reserve the port id */
+	if (test_and_set_bit(port, &vt8500_ports_in_use)) {
+		/* port already in use - shouldn't really happen */
+		return -EBUSY;
+	}
+
 	vt8500_port->uart.type = PORT_VT8500;
 	vt8500_port->uart.iotype = UPIO_MEM;
 	vt8500_port->uart.mapbase = mmres->start;
 	vt8500_port->uart.irq = irqres->start;
 	vt8500_port->uart.fifosize = 16;
 	vt8500_port->uart.ops = &vt8500_uart_pops;
-	vt8500_port->uart.line = pdev->id;
+	vt8500_port->uart.line = port;
 	vt8500_port->uart.dev = &pdev->dev;
 	vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	vt8500_port->uart.uartclk = 24000000;
@@ -579,7 +609,7 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 		goto err;
 	}
 
-	vt8500_uart_ports[pdev->id] = vt8500_port;
+	vt8500_uart_ports[port] = vt8500_port;
 
 	uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
 
@@ -603,12 +633,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-uart", },
+	{}
+};
+
 static struct platform_driver vt8500_platform_driver = {
 	.probe  = vt8500_serial_probe,
 	.remove = __devexit_p(vt8500_serial_remove),
 	.driver = {
 		.name = "vt8500_serial",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -642,4 +678,4 @@ module_exit(vt8500_serial_exit);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("Driver for vt8500 serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From julia.lawall at lip6.fr  Wed Aug 22 02:38:45 2012
From: julia.lawall at lip6.fr (Julia Lawall)
Date: Wed, 22 Aug 2012 08:38:45 +0200 (CEST)
Subject: [PATCH] drivers/dma/sirf-dma.c: fix usage of devm functions
In-Reply-To: <1345617275.1895.83.camel@vkoul-udesk3>
References: <1344069330-29569-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345608994.1895.73.camel@vkoul-udesk3>
 <CAGsJ_4yjzE3eNGz=AA7gGxGNkjBH8bKRAUsYXcG+A1p8PtOQPw@mail.gmail.com>
 <alpine.DEB.2.02.1208220729440.1966@localhost6.localdomain6> 
 <CAGsJ_4wkyY7VkrgMwGwmFF4kpGiGEtU8Ox46G-yOspAi27Lqgg@mail.gmail.com>
 <1345617275.1895.83.camel@vkoul-udesk3>
Message-ID: <alpine.DEB.2.02.1208220837480.1966@localhost6.localdomain6>

>> dmaengine: sirf: .............
> That is the usual way, it helps if you see the notation used by
> subsystem by checking patches being sent to subsystem, but it is not a
> really big deal, pls take care of this in future.

OK.

julia


From mnalajal at codeaurora.org  Wed Aug 22 02:41:10 2012
From: mnalajal at codeaurora.org (Murali Nalajala)
Date: Wed, 22 Aug 2012 12:11:10 +0530
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <5033C428.2050607@codeaurora.org>
References: <50339AF6.1060601@codeaurora.org> <5033C428.2050607@codeaurora.org>
Message-ID: <50347F06.9010902@codeaurora.org>

On 8/21/2012 10:53 PM, Laura Abbott wrote:
> On 8/21/2012 7:28 AM, Murali Nalajala wrote:
>> Hi All,
>> I am doing a below call in my driver to get the virtual address
>> equivalent to physical address 0x0.
>>
>> pdata->v_addr = ioremap(pdata->p_addr, PAGE_SIZE); /* pdata->p_addr=0 */
>>
>> Above call returns me a valid virtual address i.e: 0xfa200000. After
>> that when i try to access the address i am getting a kernel panic like
>> below.
>
> <snip>
>
>> [ 0.161784] ioremap: pfn=0x0 phys=0x0 offset=0x0 size=0x1000
>> [ 0.161813] ioremap: area da0fbdc0: phys_addr=0xc0100000 pfn=0xc0100
>> size=0x1000
>> [ 0.161838] ioremap: area da0fbe20: phys_addr=0xa8600000 pfn=0xa8600
>> size=0x1000
>> [ 0.161861] ioremap: area da0fbd80: phys_addr=0xc0000000 pfn=0xc0000
>> size=0x1000
>> [ 0.161886] ioremap: area da0fbda0: phys_addr=0xc0100000 pfn=0xc0100
>> size=0x1000
>> [ 0.161909] ioremap: area da0fbde0: phys_addr=0xa9200000 pfn=0xa9200
>> size=0x1000
>> [ 0.161933] ioremap: area da0fbe00: phys_addr=0xa9300000 pfn=0xa9300
>> size=0x1000
>> [ 0.161956] ioremap: area da0fbd40: phys_addr=0x0 pfn=0x0 size=0x100000
>> [ 0.161979] ioremap: found: addr fa200000 => 0xfa200000 => 0xfa200000
>> [ 0.161999] *** reset_vector = 0xfa200000
>>
>>
>> Can someone know me what is wrong in ioremap call?
>> Why i am not seeing a crash after i commented out the loop above?
>>
>
> Looks like you are hitting the empty section gap:
>
> 0xfa200000-0xfa300000 1048576 pmd_empty_section_gap+0x0/0x3c ioremap
>
> pmd_empty_section_gap ends up with vm->phys_addr = 0x0 because it was
> never set. This section isn't actually mapped so when searching for the
> range in the static io map it finds this address and returns it but it
> isn't actually a valid address to return. Perhaps ioremap should not
> bother trying to re-use the static iomap if the address is zero and let
> pmd_empty_section_gap use 0x0 as a dummy value?
>
>
>
> diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -228,7 +228,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned
> long pfn,
> */
> read_lock(&vmlist_lock);
> for (area = vmlist; area; area = area->next) {
> - if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
> + if (!size || !pfn || (sizeof(phys_addr_t) == 4 &&
> + pfn >= 0x100000))
> break;
> if (!(area->flags & VM_ARM_STATIC_MAPPING))
> continue;
>
>
>
>>
>> Thanks,
>> Murali N
>>
>
> Thanks,
> Laura
>

Hi Nicolas,
Laura's code helps me to resolve the issue. But not sure of side effects 
of this change and other implications.

If the above changes are ok, can you please provide the ack.

Thanks,
Murali N

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From arnd at arndb.de  Wed Aug 22 02:41:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 06:41:21 +0000
Subject: FW: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <CADApbehnsRzwu_LrAEMf+L7AvXv+JBtPBOzWHj578Vs6B_LrCw@mail.gmail.com>
References: <AAD1C6EB06EE3649B35B7E026785068D1A754366CB@SC-VEXCH2.marvell.com>
 <CADApbehnsRzwu_LrAEMf+L7AvXv+JBtPBOzWHj578Vs6B_LrCw@mail.gmail.com>
Message-ID: <201208220641.21891.arnd@arndb.de>

On Wednesday 22 August 2012, Chao Xie wrote:
> >
> > Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> >
> >         Arnd
> 
> Who will be responsible for merging these patches?
> 

They should go through Mike's tree, unless there is a reason why he
prefers them to go through arm-soc. It would be helpful to add
an 'Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>' line
and my 'Reviewed-by: Arnd Bergmann <arnd at arndb.de>' line to each
patch for that.

	Arnd


From cmahapatra at ti.com  Wed Aug 22 02:36:53 2012
From: cmahapatra at ti.com (Chandrabhanu Mahapatra)
Date: Wed, 22 Aug 2012 12:06:53 +0530
Subject: [PATCH V6 0/6] OMAPDSS: Cleanup cpu_is checks
In-Reply-To: <cover.1345468541.git.cmahapatra@ti.com>
References: <cover.1345468541.git.cmahapatra@ti.com>
Message-ID: <cover.1345616887.git.cmahapatra@ti.com>

Hi everyone,
this patch series aims at cleaning up of DSS of cpu_is checks thereby making it
more generic.

The 1st patch cleans up cpu_is checks from DISPC code.
The 2nd patch removes unused functions from DSS code.
The 3rd patch cleans up cpu_is checks from DSS code.
The 4th patch disables VENC support on OMAP4.
The 5th patch removes cpu_is checks from VENC code.
The 6th patch removes cpu_is checks from DPI code and replaces it with a
dss feature.

Changes from V1 to V5 series:
 1st patch :
	* moved dispc_ops structure definitions from dss_features.c to dispc.c
	  and renamed it to dispc_features
	* moved dispc_features definitions close to dispc_init_features() thereby
	  eliminating various functions declarations from top of dispc.c
	* used __initconst before dispc_features definitions and __init before
	  dispc_init_features()
	* removed definitions of _dispc_lcd_timings_ok_24xx,
	  _dispc_lcd_timings_ok_44xx, _dispc_mgr_set_lcd_timings_hv_24xx and
	  _dispc_mgr_set_lcd_timings_hv_44xx replacing them with appropiate variables
	* renamed various dispc_features structures to give consistent naming

 3rd patch :
	* moved dss_ops structure definitions from dss_features.c to dss.c and
	  renamed it to dss_features
	* removed all functions from dss_features structure and replaced them with
	  appropiate variables
	* used __initconst before dss_features definitions and __init before 
	  dss_init_features()
	* renamed various dss_features structures to give consistent naming
	* renamed factor variable of dss_features structure to dss_fck_multiplier

Changes from V5 to V6 series:
	* The "ARM: OMAP: Disable venc for OMAP4" patch has been placed before
	  "OMAPDSS: VENC: Remove cpu_is_xxxx checks" patch
 1st patch:
	* The dispc_init_features() implementation has been corrected
	* The variables types of variables in dispc_features has been changed
	  to u8 and u16 as found appropiate
 2nd patch:
	* The dss_init_features() implementation has been corrected
	* In dss_features struct char * has been changed to const char * and
	  int replaced with u8

All your comments and suggestions are welcome.

Refenence Tree:
git at gitorious.org:~chandrabhanu/linux-omap-dss2/chandrabhanus-linux.git dss_cleanup

Regards,
Chandrabhanu

Chandrabhanu Mahapatra (6):
  OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks
  OMAPDSS: DSS: Remove redundant functions
  OMAPDSS: DSS: Cleanup cpu_is_xxxx checks
  ARM: OMAP: Disable venc for OMAP4
  OMAPDSS: VENC: Remove cpu_is_xxxx checks
  OMAPDSS: DPI: Remove cpu_is_xxxx checks

 arch/arm/mach-omap2/display.c          |    1 -
 drivers/video/omap2/dss/dispc.c        |  434 ++++++++++++++++++++------------
 drivers/video/omap2/dss/dpi.c          |   12 +-
 drivers/video/omap2/dss/dss.c          |  165 ++++++------
 drivers/video/omap2/dss/dss.h          |    2 -
 drivers/video/omap2/dss/dss_features.c |    1 +
 drivers/video/omap2/dss/dss_features.h |    1 +
 drivers/video/omap2/dss/venc.c         |   11 -
 8 files changed, 367 insertions(+), 260 deletions(-)

-- 
1.7.10



From cmahapatra at ti.com  Wed Aug 22 02:38:38 2012
From: cmahapatra at ti.com (Chandrabhanu Mahapatra)
Date: Wed, 22 Aug 2012 12:08:38 +0530
Subject: [PATCH V6 4/6] ARM: OMAP: Disable venc for OMAP4
In-Reply-To: <cover.1345616887.git.cmahapatra@ti.com>
References: <cover.1345468541.git.cmahapatra@ti.com>
 <cover.1345616887.git.cmahapatra@ti.com>
Message-ID: <1f7081278149b234ce8a03e0621a7a7f927e48d6.1345616887.git.cmahapatra@ti.com>

This is a alternative to "HACK: OMAP: DSS2: VENC: disable VENC on OMAP4 to
prevent crash" (ba02fa37de) by Tomi Valkeinen <tomi.valkeinen at ti.com> to prevent
VENC from crashing OMAP4 kernel. This prevents OMAPDSS from initial registration
of a device for VENC on OMAP4.

Signed-off-by: Chandrabhanu Mahapatra <cmahapatra at ti.com>
---
 arch/arm/mach-omap2/display.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d..ee40739 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -95,7 +95,6 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
-	{ "dss_venc", "omapdss_venc", -1 },
 	{ "dss_dsi1", "omapdss_dsi", 0 },
 	{ "dss_dsi2", "omapdss_dsi", 1 },
 	{ "dss_hdmi", "omapdss_hdmi", -1 },
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 02:44:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 06:44:17 +0000
Subject: [PATCHv3 3/9] serial: vt8500: Add devicetree support for
In-Reply-To: <1345617278.7491.4.camel@gitbox>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <20120821231255.71a7515a@pyramind.ukuu.org.uk>
 <1345617278.7491.4.camel@gitbox>
Message-ID: <201208220644.18059.arnd@arndb.de>

On Wednesday 22 August 2012, Tony Prisk wrote:
> The original patch was very simple, but I revisited it to fix other
> issues and forgot to add the relevant comments.
> 
> Port size is changed to fix a problem - WM8505 actually had 6 uart's
> defined in platform data but the vt8500_ports variable was only 4.
> 
> I have added devicetree port id support as well.

If you do multiple things in one driver, you should normally send multiple
patches as well, each with a description why that change is done.
It may seem silly at first to send out a one-line patch next to a 100-line
patch for the same file, but those cases are actually the ones where it's
most important.

	Arnd


From tsoni at codeaurora.org  Wed Aug 22 02:46:08 2012
From: tsoni at codeaurora.org (Trilok Soni)
Date: Wed, 22 Aug 2012 12:16:08 +0530
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <5033C428.2050607@codeaurora.org>
References: <50339AF6.1060601@codeaurora.org> <5033C428.2050607@codeaurora.org>
Message-ID: <50348030.9080200@codeaurora.org>

Hi Laura,

On 8/21/2012 10:53 PM, Laura Abbott wrote:
>
> Looks like you are hitting the empty section gap:
>
> 0xfa200000-0xfa300000 1048576 pmd_empty_section_gap+0x0/0x3c ioremap
>
> pmd_empty_section_gap ends up with vm->phys_addr = 0x0 because it was
> never set. This section isn't actually mapped so when searching for the
> range in the static io map it finds this address and returns it but it
> isn't actually a valid address to return. Perhaps ioremap should not
> bother trying to re-use the static iomap if the address is zero and let
> pmd_empty_section_gap use 0x0 as a dummy value?
>
>
>
> diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -228,7 +228,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned
> long pfn,
> */
> read_lock(&vmlist_lock);
> for (area = vmlist; area; area = area->next) {
> - if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
> + if (!size || !pfn || (sizeof(phys_addr_t) == 4 &&
> + pfn >= 0x100000))

Thanks for the patch, but how about just checking pmd_none on such 
addresses and since there won't be any mapping created for such gaps? We 
need to check if this is fine for all, since I remember that Nico
added these functions for the OMAP boot issue I guess.

---Trilok Soni

-- 
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From N.Voss at weinmann.de  Wed Aug 22 02:55:15 2012
From: N.Voss at weinmann.de (Voss, Nikolaus)
Date: Wed, 22 Aug 2012 08:55:15 +0200
Subject: [PATCH 1/5] i2c: at91: add new fixes for some TWI ip versions
In-Reply-To: <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <EF2E73589CA71846A15D0B2CDF79505D090EBE8856@wm021.weinmann.com>

Hi Ludovic,

ludovic.desroches at atmel.com wrote on Tuesday, August 21, 2012 4:29 PM
> The at91sam9261 TWI ip version requires also some fixes. The id_entry
> field from the platform device structure has been replaced by the use
> of cpu_is_xxx function to determine when to use these fixes.

I applied your calc_twi_clock() fix using the id_entry stuff instead of
cpu_is_xxx functions as those are deprecated...

I will post the complete series later on. Please test it!

Niko



From gururaja.hebbar at ti.com  Wed Aug 22 03:06:17 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 07:06:17 +0000
Subject: [PATCH 1/5] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <502E89D8.2090304@ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
 <502E89D8.2090304@ti.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA64A1D@DBDE01.ent.ti.com>

On Fri, Aug 17, 2012 at 23:43:44, Nori, Sekhar wrote:
> Hi Gururaja,
> 
> On 8/14/2012 6:12 PM, Hebbar, Gururaja wrote:
> > Davinci McASP header & driver are shared by few OMAP platforms (like
> > TI81xx, AM335x). Splitting asp header into Davinci platform specific
> > header and Audio specific header helps to share them across platforms.
> > 
> > Audio specific defines is moved to to common
> > <linux/platform_data/davinci_asp.h> so that the header can be
> > accessed by all related platforms.
> > 
> > While here, correct the header usage (remove multiple header
> > re-definitions and unused headers) and remove platform names from
> > structures comments and enum
> > 
> > Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> > Acked-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
> 
> This patch looks good to me. See a minor nit below.
> 
> Acked-by: Sekhar Nori <nsekhar at ti.com>
> 
> > diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
> > new file mode 100644
> > index 0000000..8fd5238
> > --- /dev/null
> > +++ b/arch/arm/mach-davinci/asp.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * TI DaVinci Audio definitions
> > + */
> > +#ifndef __ASM_ARCH_DAVINCI_ASP_H
> > +#define __ASM_ARCH_DAVINCI_ASP_H
> > +
> > +/* Bases of dm644x and dm355 register banks */
> > +#define DAVINCI_ASP0_BASE	0x01E02000
> > +#define DAVINCI_ASP1_BASE	0x01E04000
> > +
> > +/* Bases of dm365 register banks */
> > +#define DAVINCI_DM365_ASP0_BASE	0x01D02000
> > +
> > +/* Bases of dm646x register banks */
> > +#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
> > +#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
> 
> Can you remove usage of tabs after 'define'. I understand this is coming
> from existing code.

Ok. I have got few more comments from Mark. Will add this into it.

> 
> Thanks,
> Sekhar
> 


Regards, 
Gururaja

From b29396 at freescale.com  Wed Aug 22 03:18:41 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:41 +0800
Subject: [PATCH 0/7] add imx-syscon driver for general registers access
Message-ID: <1345619928-15446-1-git-send-email-b29396@freescale.com>

This patch series mainly adds an imx-syscon driver which is used to access
general system controller registers like IOMUXC GPR and ANATOP,
after that, we convert all the exist private access general registers code to use
standard API from imx-syscon to access registers.
Finally we remove the old mfd anatop driver which is only for anatop register
access.

The patch series is based on linus's tree since commit 9160338.

Dong Aisheng (7):
  mfd: add imx syscon driver based on regmap
  ARM: imx6q: add iomuxc gpr support into imx-syscon
  ARM: imx6q: add anatop support into imx-syscon
  regulator: anatop-regulator: convert to use imx-syscon to access
    anatop register
  ARM: imx6q: convert to use imx-syscon to access anatop registers
  ARM: dts: imx6q: add simple-bus compatible string for anatop
  mfd: anatop-mfd: remove anatop driver

 .../devicetree/bindings/mfd/imx-syscon.txt         |   11 +
 arch/arm/boot/dts/imx6q.dtsi                       |   15 +-
 arch/arm/mach-imx/Kconfig                          |    2 +-
 arch/arm/mach-imx/mach-imx6q.c                     |   25 +--
 drivers/mfd/Kconfig                                |   14 +-
 drivers/mfd/Makefile                               |    2 +-
 drivers/mfd/anatop-mfd.c                           |  124 --------
 drivers/mfd/imx-syscon.c                           |  193 ++++++++++++
 drivers/regulator/Kconfig                          |    2 +-
 drivers/regulator/anatop-regulator.c               |   17 +-
 include/linux/fsl/imx6q-iomuxc-gpr.h               |  319 ++++++++++++++++++++
 include/linux/mfd/anatop.h                         |   40 ---
 include/linux/mfd/imx-syscon.h                     |   22 ++
 13 files changed, 585 insertions(+), 201 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/imx-syscon.txt
 delete mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 drivers/mfd/imx-syscon.c
 create mode 100644 include/linux/fsl/imx6q-iomuxc-gpr.h
 delete mode 100644 include/linux/mfd/anatop.h
 create mode 100644 include/linux/mfd/imx-syscon.h




From b29396 at freescale.com  Wed Aug 22 03:18:42 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:42 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-2-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Add regmap based imx syscon driver.
This is usually used for access misc bits in registers which does not belong
to a specific module, for example, IOMUXC GPR and ANATOP.
With this driver, we provide a standard API for client driver to call to
access registers which are registered into syscon.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
Currently it's just simply for IMX, however the driver really is not too
much imx specific.
If people want, we probably could extend it to support other platforms too.
---
 .../devicetree/bindings/mfd/imx-syscon.txt         |   11 +
 drivers/mfd/Kconfig                                |    8 +
 drivers/mfd/Makefile                               |    1 +
 drivers/mfd/imx-syscon.c                           |  193 ++++++++++++++++++++
 include/linux/mfd/imx-syscon.h                     |   22 +++
 5 files changed, 235 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
new file mode 100644
index 0000000..4a72994
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
@@ -0,0 +1,11 @@
+* Freescale IMX System Controller Registers R/W driver
+
+Required properties:
+- compatible: Should contain "fsl,imx-syscon".
+- reg: the register range can be access from imx-syscon
+
+Examples:
+gpr: iomuxc-gpr at 020e0000 {
+	compatible = "fsl,imx6q-iomuxc", "fsl,imx-syscon";
+	reg = <0x020e0000 0x38>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b1a1462..20a050e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -993,6 +993,14 @@ config MFD_ANATOP
 	  MFD controller. This controller embeds regulator and
 	  thermal devices for Freescale i.MX platforms.
 
+config MFD_IMX_SYSCON
+        bool "Freescale i.MX System Controller Register R/W Based on Regmap"
+        depends on ARCH_MXC
+        select REGMAP_MMIO
+        help
+          Select this option to enable access Freescale i.MX system control
+	  registers like iomuxc gpr and anatop via regmap.
+
 config MFD_PALMAS
 	bool "Support for the TI Palmas series chips"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..82c7ee1 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
+obj-$(CONFIG_MFD_IMX_SYSCON)	+= imx-syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/imx-syscon.c b/drivers/mfd/imx-syscon.c
new file mode 100644
index 0000000..141b456
--- /dev/null
+++ b/drivers/mfd/imx-syscon.c
@@ -0,0 +1,193 @@
+/*
+ * Freescale IMX System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct platform_driver imx_syscon_driver;
+
+struct imx_syscon {
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *regmap;
+};
+
+static int imx_syscon_match(struct device *dev, void *data)
+{
+	struct imx_syscon *syscon = dev_get_drvdata(dev);
+	struct device_node *dn = data;
+
+	return (syscon->dev->of_node == dn) ? 1 : 0;
+}
+
+int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
+{
+	struct device *dev;
+	struct imx_syscon *syscon;
+	int ret = 0;
+
+	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
+				 imx_syscon_match);
+	if (!dev)
+		return -EPROBE_DEFER;
+
+	syscon = dev_get_drvdata(dev);
+	ret = regmap_write(syscon->regmap, reg, val);
+	if (ret)
+		dev_err(dev, "failed to write regmap(%s) reg 0x%x (%d)\n",
+			np->name, reg, ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(imx_syscon_write);
+
+int imx_syscon_read(struct device_node *np, u32 reg, u32 *val)
+{
+	struct device *dev;
+	struct imx_syscon *syscon;
+	int ret = 0;
+
+	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
+				 imx_syscon_match);
+	if (!dev)
+		return -EPROBE_DEFER;
+
+	syscon = dev_get_drvdata(dev);
+	ret = regmap_read(syscon->regmap, reg, val);
+	if (ret)
+		dev_err(dev, "failed to read regmap(%s) reg 0x%x (%d)\n",
+			np->name, reg, ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(imx_syscon_read);
+
+int imx_syscon_update_bits(struct device_node *np, u32 reg,
+					u32 mask, u32 val)
+{
+	struct device *dev;
+	struct imx_syscon *syscon;
+	int ret = 0;
+
+	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
+				 imx_syscon_match);
+	if (!dev)
+		return -EPROBE_DEFER;
+
+	syscon = dev_get_drvdata(dev);
+	ret = regmap_update_bits(syscon->regmap, reg, mask, val);
+	if (ret)
+		dev_err(dev, "failed to update regmap(%s) reg 0x%x (%d)\n",
+			np->name, reg, ret);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(imx_syscon_update_bits);
+
+static const struct of_device_id of_imx_syscon_match[] = {
+	{ .compatible = "fsl,imx-syscon", },
+	{ },
+};
+
+static struct regmap_config imx_syscon_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int __devinit imx_syscon_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct imx_syscon *syscon;
+	struct resource res;
+	int ret;
+
+	if (!np)
+		return -ENOENT;
+
+	syscon = devm_kzalloc(&pdev->dev, sizeof(struct imx_syscon),
+			    GFP_KERNEL);
+	if (!syscon)
+		return -ENOMEM;
+
+	syscon->base = of_iomap(np, 0);
+	if (!syscon->base)
+		return -EADDRNOTAVAIL;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	imx_syscon_regmap_config.max_register = res.end - res.start - 3;
+	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
+					&imx_syscon_regmap_config);
+	if (IS_ERR(syscon->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(syscon->regmap);
+	}
+
+	regcache_cache_only(syscon->regmap, false);
+
+	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
+		res.start, res.end);
+
+	syscon->dev = &pdev->dev;
+	platform_set_drvdata(pdev, syscon);
+
+	return 0;
+}
+
+static int __devexit imx_syscon_remove(struct platform_device *pdev)
+{
+	struct imx_syscon *syscon;
+
+	syscon = platform_get_drvdata(pdev);
+	iounmap(syscon->base);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver imx_syscon_driver = {
+	.driver = {
+		.name = "imx-syscon",
+		.owner = THIS_MODULE,
+		.of_match_table = of_imx_syscon_match,
+	},
+	.probe		= imx_syscon_probe,
+	.remove		= imx_syscon_remove,
+};
+
+static int __init imx_syscon_init(void)
+{
+	return platform_driver_register(&imx_syscon_driver);
+}
+postcore_initcall(imx_syscon_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&imx_syscon_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX System Control driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/imx-syscon.h b/include/linux/mfd/imx-syscon.h
new file mode 100644
index 0000000..be8b6db
--- /dev/null
+++ b/include/linux/mfd/imx-syscon.h
@@ -0,0 +1,22 @@
+/*
+ * Freescale IMX System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_MFD_IMX_SYSCON_H__
+#define __LINUX_MFD_IMX_SYSCON_H__
+
+extern int imx_syscon_write(struct device_node *np, u32 reg, u32 val);
+extern int imx_syscon_read(struct device_node *np, u32 reg, u32 *val);
+extern int imx_syscon_update_bits(struct device_node *np, u32 reg,
+					u32 mask, u32 val);
+#endif /* __LINUX_MFD_IMX_SYSCON_H__ */
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:43 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:43 +0800
Subject: [PATCH 2/7] ARM: imx6q: add iomuxc gpr support into imx-syscon
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-3-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Include headfile for easy using.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi         |    5 +
 include/linux/fsl/imx6q-iomuxc-gpr.h |  319 ++++++++++++++++++++++++++++++++++
 2 files changed, 324 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..1306868 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -507,6 +507,11 @@
 				interrupts = <0 89 0x04 0 90 0x04>;
 			};
 
+			gpr: iomuxc-gpr at 020e0000 {
+				compatible = "fsl,imx6q-iomuxc-gpr", "fsl,imx-syscon";
+				reg = <0x020e0000 0x38>;
+			};
+
 			iomuxc at 020e0000 {
 				compatible = "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
diff --git a/include/linux/fsl/imx6q-iomuxc-gpr.h b/include/linux/fsl/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..2c44573
--- /dev/null
+++ b/include/linux/fsl/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0	0x00
+#define IOMUXC_GPR1	0x04
+#define IOMUXC_GPR2	0x08
+#define IOMUXC_GPR3	0x0c
+#define IOMUXC_GPR4	0x10
+#define IOMUXC_GPR5	0x14
+#define IOMUXC_GPR6	0x18
+#define IOMUXC_GPR7	0x1c
+#define IOMUXC_GPR8	0x20
+#define IOMUXC_GPR9	0x24
+#define IOMUXC_GPR10	0x28
+#define IOMUXC_GPR11	0x2c
+#define IOMUXC_GPR12	0x30
+#define IOMUXC_GPR13	0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7	(0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED	(0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR	(0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED	(0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7	(0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED	(0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2	(0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED	(0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2	(0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED	(0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1	(0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED	(0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1	(0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1	(0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2	(0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK		BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX	BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK		BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2	BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK		BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1			BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23			BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IMX6Q_GPR1_DPI_OFF			BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY			0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE			BIT(15)
+#define IMX6Q_GPR1_PCIE_INT			BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK		BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER	0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1	BIT(13)
+#define IMX6Q_GPR1_GINT				BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3			BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2			BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1			BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0			BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK	(0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5		(0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3		(0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4		(0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6		(0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK		(0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0		(0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1		(0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2		(0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3		(0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4		(0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5		(0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6		(0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7		(0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK		BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR	0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR	BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK		BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L	BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK		BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L	BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK		BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA	BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK		BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT		BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK		BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA	BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK		BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT		BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN		BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK		(0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE		(0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0	(0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1	(0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK		(0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE		(0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0	(0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK			(0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D		(0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D		(0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG		(0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL		BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL		BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL		BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL		BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK		(0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK		(0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN		BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN		BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN		BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN		BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK		BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK		BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK		BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK		(0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0	(0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1	(0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0	(0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1	(0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK		(0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0	(0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1	(0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0	(0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1	(0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0	(0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1	(0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0	(0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1	(0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL		BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL		BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL		BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL		BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL		BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL		BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL		BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL		BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK		BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK		BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK		BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK		BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK		(0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF		0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL		BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL		BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL		BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK	BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL		BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL		BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN			BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN		BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP		BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR		(0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN		BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK		(0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK		(0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN			BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN			BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK		BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY		0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE		BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK		(0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK		BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1	(0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK		(0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0	(0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1	(0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0	(0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ		BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ		BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB		(0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB		(0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB		(0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB		(0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB		(0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB		(0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB		(0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK		(0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK		(0x7 << 16)
+#define IMX6Q_GPR13_SATA_SPEED_MASK		BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G		0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G		BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5			BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK		(0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16		(0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16		(0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16		(0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16		(0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16		(0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16		(0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK		(0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF		0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF		0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK		(0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST		(0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
+
+#endif /* !__LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:44 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:44 +0800
Subject: [PATCH 3/7] ARM: imx6q: add anatop support into imx-syscon
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-4-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

There're a few anatop registers need to be accessed by different modules.
Add anatop registers into imx-syscon support for easy access.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 1306868..7732b70 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -378,8 +378,8 @@
 				interrupts = <0 87 0x04 0 88 0x04>;
 			};
 
-			anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop";
+			anatop: anatop at 020c8000 {
+				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:45 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:45 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use imx-syscon to
 access anatop register
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-5-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using standard imx syscon API to access anatop register.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi         |    6 ++++++
 drivers/regulator/Kconfig            |    2 +-
 drivers/regulator/anatop-regulator.c |   17 +++++++++++------
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7732b70..7076be0 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -395,6 +395,7 @@
 					anatop-min-bit-val = <4>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1375000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-3p0 at 120 {
@@ -409,6 +410,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2625000>;
 					anatop-max-voltage = <3400000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-2p5 at 130 {
@@ -423,6 +425,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2000000>;
 					anatop-max-voltage = <2750000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddcore at 140 {
@@ -437,6 +440,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddpu at 140 {
@@ -451,6 +455,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddsoc at 140 {
@@ -465,6 +470,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 			};
 
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 4e932cc..7ceea1a 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -112,7 +112,7 @@ config REGULATOR_DA9052
 
 config REGULATOR_ANATOP
 	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
-	depends on MFD_ANATOP
+	depends on MFD_IMX_SYSCON
 	help
 	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
 	  regulators. It is recommended that this option be
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index ce0fe72..e0b9ef1 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -21,19 +21,20 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 #include <linux/module.h>
+#include <linux/mfd/imx-syscon.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
+#include <linux/regmap.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/of_regulator.h>
 
 struct anatop_regulator {
 	const char *name;
 	u32 control_reg;
-	struct anatop *mfd;
+	struct device_node *anatop;
 	int vol_bit_shift;
 	int vol_bit_width;
 	int min_bit_val;
@@ -56,7 +57,8 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val <<= anatop_reg->vol_bit_shift;
-	anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
+	imx_syscon_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
+				mask, val);
 
 	return 0;
 }
@@ -69,7 +71,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 	if (!anatop_reg->control_reg)
 		return -ENOTSUPP;
 
-	val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
+	imx_syscon_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val = (val & mask) >> anatop_reg->vol_bit_shift;
@@ -92,7 +94,6 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	struct regulator_dev *rdev;
 	struct anatop_regulator *sreg;
 	struct regulator_init_data *initdata;
-	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
 	struct regulator_config config = { };
 	int ret = 0;
 
@@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	rdesc->ops = &anatop_rops;
 	rdesc->type = REGULATOR_VOLTAGE;
 	rdesc->owner = THIS_MODULE;
-	sreg->mfd = anatopmfd;
+
+	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
+	if (!sreg->anatop)
+		return -ENODEV;
+
 	ret = of_property_read_u32(np, "anatop-reg-offset",
 				   &sreg->control_reg);
 	if (ret) {
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:46 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:46 +0800
Subject: [PATCH 5/7] ARM: imx6q: convert to use imx-syscon to access anatop
 registers
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-6-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using standard imx syscon API to access anatop registers.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/mach-imx/Kconfig      |    2 +-
 arch/arm/mach-imx/mach-imx6q.c |   25 ++++++-------------------
 2 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..c7b2adb 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -839,7 +839,7 @@ config SOC_IMX6Q
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC
 	select HAVE_SMP
-	select MFD_ANATOP
+	select MFD_IMX_SYSCON
 	select PINCTRL
 	select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..32a9c9e 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,8 +24,9 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/imx-syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -121,20 +122,8 @@ static void __init imx6q_sabrelite_init(void)
 static void __init imx6q_usb_init(void)
 {
 	struct device_node *np;
-	struct platform_device *pdev = NULL;
-	struct anatop *adata = NULL;
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-	if (np)
-		pdev = of_find_device_by_node(np);
-	if (pdev)
-		adata = platform_get_drvdata(pdev);
-	if (!adata) {
-		if (np)
-			of_node_put(np);
-		return;
-	}
-
 #define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT		0x00000210
 
@@ -145,14 +134,12 @@ static void __init imx6q_usb_init(void)
 	 * The external charger detector needs to be disabled,
 	 * or the signal at DP will be poor
 	 */
-	anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
+	imx_syscon_write(np, HW_ANADIG_USB1_CHRG_DETECT,
 			BM_ANADIG_USB_CHRG_DETECT_EN_B
-			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-	anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
+			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+	imx_syscon_write(np, HW_ANADIG_USB2_CHRG_DETECT,
 			BM_ANADIG_USB_CHRG_DETECT_EN_B |
-			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
+			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
 
 	of_node_put(np);
 }
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:47 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:47 +0800
Subject: [PATCH 6/7] ARM: dts: imx6q: add simple-bus compatible string for
 anatop
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-7-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Originally the anatop regulator devices are populated by mfd anatop driver.
Since mfd anatop driver will be deleted later, we change to populate the
regulator devices by devicetree automatically.
This will cause some warning messages as follows during boot due to device
recreation: "vdd1p1: Failed to create debugfs directory"
But it does not break any function.
Later, we will remove mfd anatop driver which can get rid of this
error message.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7076be0..426f735 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -379,7 +379,7 @@
 			};
 
 			anatop: anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon";
+				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon", "simple-bus";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 22 03:18:48 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 15:18:48 +0800
Subject: [PATCH 7/7] mfd: anatop-mfd: remove anatop driver
In-Reply-To: <1345619928-15446-1-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
Message-ID: <1345619928-15446-8-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

The anatop registers are accessed via imx syscon now, no one will use
mfd anatop driver anymore, remove it.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 drivers/mfd/Kconfig        |    8 ---
 drivers/mfd/Makefile       |    1 -
 drivers/mfd/anatop-mfd.c   |  124 --------------------------------------------
 include/linux/mfd/anatop.h |   40 --------------
 4 files changed, 0 insertions(+), 173 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 20a050e..705a3d0 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -985,14 +985,6 @@ config MFD_STA2X11
 	depends on STA2X11
 	select MFD_CORE
 
-config MFD_ANATOP
-	bool "Support for Freescale i.MX on-chip ANATOP controller"
-	depends on SOC_IMX6Q
-	help
-	  Select this option to enable Freescale i.MX on-chip ANATOP
-	  MFD controller. This controller embeds regulator and
-	  thermal devices for Freescale i.MX platforms.
-
 config MFD_IMX_SYSCON
         bool "Freescale i.MX System Controller Register R/W Based on Regmap"
         depends on ARCH_MXC
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 82c7ee1..c352dfe 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -130,6 +130,5 @@ obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
-obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
 obj-$(CONFIG_MFD_IMX_SYSCON)	+= imx-syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
deleted file mode 100644
index 5576e07..0000000
--- a/drivers/mfd/anatop-mfd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- * Copyright (C) 2012 Linaro
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
-
-u32 anatop_read_reg(struct anatop *adata, u32 addr)
-{
-	return readl(adata->ioreg + addr);
-}
-EXPORT_SYMBOL_GPL(anatop_read_reg);
-
-void anatop_write_reg(struct anatop *adata, u32 addr, u32 data, u32 mask)
-{
-	u32 val;
-
-	data &= mask;
-
-	spin_lock(&adata->reglock);
-	val = readl(adata->ioreg + addr);
-	val &= ~mask;
-	val |= data;
-	writel(val, adata->ioreg + addr);
-	spin_unlock(&adata->reglock);
-}
-EXPORT_SYMBOL_GPL(anatop_write_reg);
-
-static const struct of_device_id of_anatop_match[] = {
-	{ .compatible = "fsl,imx6q-anatop", },
-	{ },
-};
-
-static int __devinit of_anatop_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	void *ioreg;
-	struct anatop *drvdata;
-
-	ioreg = of_iomap(np, 0);
-	if (!ioreg)
-		return -EADDRNOTAVAIL;
-	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-	if (!drvdata)
-		return -ENOMEM;
-	drvdata->ioreg = ioreg;
-	spin_lock_init(&drvdata->reglock);
-	platform_set_drvdata(pdev, drvdata);
-	of_platform_populate(np, NULL, NULL, dev);
-
-	return 0;
-}
-
-static int __devexit of_anatop_remove(struct platform_device *pdev)
-{
-	struct anatop *drvdata;
-	drvdata = platform_get_drvdata(pdev);
-	iounmap(drvdata->ioreg);
-
-	return 0;
-}
-
-static struct platform_driver anatop_of_driver = {
-	.driver = {
-		.name = "anatop-mfd",
-		.owner = THIS_MODULE,
-		.of_match_table = of_anatop_match,
-	},
-	.probe		= of_anatop_probe,
-	.remove		= of_anatop_remove,
-};
-
-static int __init anatop_init(void)
-{
-	return platform_driver_register(&anatop_of_driver);
-}
-postcore_initcall(anatop_init);
-
-static void __exit anatop_exit(void)
-{
-	platform_driver_unregister(&anatop_of_driver);
-}
-module_exit(anatop_exit);
-
-MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
-MODULE_DESCRIPTION("ANATOP MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf..0000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * anatop.h - Anatop MFD driver
- *
- *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- *  Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_ANATOP_H
-#define __LINUX_MFD_ANATOP_H
-
-#include <linux/spinlock.h>
-
-/**
- * anatop - MFD data
- * @ioreg: ioremap register
- * @reglock: spinlock for register read/write
- */
-struct anatop {
-	void *ioreg;
-	spinlock_t reglock;
-};
-
-extern u32 anatop_read_reg(struct anatop *, u32);
-extern void anatop_write_reg(struct anatop *, u32, u32, u32);
-
-#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.0.4




From arnd at arndb.de  Wed Aug 22 03:56:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 07:56:30 +0000
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <20120821220145.GA27934@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208212014.01837.arnd@arndb.de> <20120821220145.GA27934@arm.com>
Message-ID: <201208220756.31149.arnd@arndb.de>

On Tuesday 21 August 2012, Catalin Marinas wrote:
> As I understand, sys_mmap_pgoff can be used instead of sys_mmap2 on new
> 32-bit architectures. But on 64-bit architectures we don't have
> sys_mmap2, only sys_mmap with the difference that the last argument is
> the offset in bytes (and multiple of PAGE_SIZE) rather than in pages. So
> unless we change the meaning of this last argument for sys_mmap, we
> cannot just define it to sys_mmap_pgoff.
> 
> Since the other 64-bit architectures seem to have a sys_mmap wrapper
> that does this:
> 
>         sys_mmap_pgoff(..., off >> PAGE_SHIFT);
> 
> I think AArch64 should also use the same sys_mmap convention. We can
> make this wrapper generic.

But the wrapper can just as well be part of glibc, which already has
one. There is no reason for the kernel to export two generic interfaces
for mmap when one of them only works on 64 bit and the other one is
good for both 32 and 64 bit.

All the other 64 bit architectures (besides tile) were added to the
kernel before we had sys_mmap_pgoff.

	Arnd


From haojian.zhuang at gmail.com  Wed Aug 22 04:00:36 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 22 Aug 2012 16:00:36 +0800
Subject: FW: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <201208220641.21891.arnd@arndb.de>
References: <AAD1C6EB06EE3649B35B7E026785068D1A754366CB@SC-VEXCH2.marvell.com>
 <CADApbehnsRzwu_LrAEMf+L7AvXv+JBtPBOzWHj578Vs6B_LrCw@mail.gmail.com>
 <201208220641.21891.arnd@arndb.de>
Message-ID: <CAN1soZxJ87=rL0Mq-3LFRXhqRGrKXcHS+rsMdVeM+yMK+WBCnQ@mail.gmail.com>

On Wed, Aug 22, 2012 at 2:41 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 22 August 2012, Chao Xie wrote:
>> >
>> > Reviewed-by: Arnd Bergmann <arnd at arndb.de>
>> >
>> >         Arnd
>>
>> Who will be responsible for merging these patches?
>>
>
> They should go through Mike's tree, unless there is a reason why he
> prefers them to go through arm-soc. It would be helpful to add
> an 'Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>' line
> and my 'Reviewed-by: Arnd Bergmann <arnd at arndb.de>' line to each
> patch for that.
>
>         Arnd

I'm OK on these patches.

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Regards
Haojian


From lee.jones at linaro.org  Wed Aug 22 04:17:50 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 Aug 2012 09:17:50 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120821165207.GX7995@opensource.wolfsonmicro.com>
References: <20120820125531.GA20242@gmail.com>
 <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
 <20120821120243.GF26899@gmail.com>
 <20120821165207.GX7995@opensource.wolfsonmicro.com>
Message-ID: <20120822081746.GA4089@gmail.com>

On Tue, Aug 21, 2012 at 05:52:07PM +0100, Mark Brown wrote:
> On Tue, Aug 21, 2012 at 01:02:46PM +0100, Lee Jones wrote:
> > On Tue, Aug 21, 2012 at 12:03:29PM +0100, Mark Brown wrote:
> 
> > > > another way to get hold of the domain, because the only way to obtain
> > > > it without having direct access is via a device node.
> 
> > > This doesn't actually hold.
> 
> > Okay, besides irq_find_host(struct device_node *np), how else can you fetch
> > a domain from the irqdomain?
>
> I'm not sure I can parse the above, sorry - I'm not sure I can
> distinguish "domain" and "irqdomain".

Are you being intentionally awkward on this? Picking holes when you know
exactly what I'm trying to say? Not that it matters now, but just out of
principle, let me try to put it in a very clear way so there can be no
misinterpretation.

I was saying that in order for the MFD core to carry out the hwirq->virq
conversion, it needed to obtain the irqdomain pointer pertaining to the
provided hwirq. The only helper function the irqdomain subsystem provides
requires a device node pointer to be passed as an argument, hence the
mention of 'irq_find_host(struct device_node *np)'. Then the Device Tree
is traversed until a specified 'interrupt-controller' is stumbled upon
or is pointed to by the 'interrupt-parent' property. Hence, we have to 
find another way to find the irqdomain pointers for non-DT based MFDs. To
which we now have a solution.

> > What have you done already? 
> 
> Implemented a patch for this which I've now tested a bit and will
> probably post in the next hour or so.
> 
> > Why make suggestions if you're just going to do the work yourself?
> 
> I made the suggestion then later on realised that this was actively
> going to break things I care about so I actually need it fixing.

I'm a little taken aback and annoyed by this. In a previous email thread
you categorically requested that I discuss some of the important changes
with maintainers and people in-the-know prior to actually writing any
code. I was obviously actively working on, had put time into, and was in
the mist of discussing this with you. Then you just go ahead and code it
(the easy part) yourself, essentially wasting my time. Surely there's
some kind of etiquette surrounding such things?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:21 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:21 +0200
Subject: [PATCH v2 0/9] pinctrl: mvebu: pinctrl driver
In-Reply-To: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and
SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood.
The SoC specific stubs use the pinctrl-mvebu core driver that handles
pinctrl API and register accesses for common pinctrl registers.

As especially Dove has some pinctrl registers that do not match the
common pinctrl register layout the core driver has been extended by
some callbacks to allow uncommon Dove pinctrl registers.

DT binding documentation is added for all supported SoCs but as
Dove and Kirkwood are not yet ready for full DT support, the pinctrl
driver is only activated for Armada 370 and XP.

The driver has been tested on Dove, 88f6281 variant of Kirkwood,
Armada 370, and XP.

Changelog:
v2:
- rebased on git://git.infradead.org/users/jcooper/linux.git boards-for-3.7
- removed arch/arm/*/Kconfig patches that enable PINCTRL_ on MACH_MVEBU
  (those will be sent as a different patch set)
- reworked patches wrt reviews from Andrew Lunn and Linus Walleij

Sebastian Hesselbarth (3):
  pinctrl: mvebu: pinctrl driver core
  pinctrl: mvebu: dove pinctrl driver
  pinctrl: mvebu: kirkwood pinctrl driver

Thomas Petazzoni (6):
  pinctrl: mvebu: add pinctrl driver for Armada 370
  pinctrl: mvebu: add pinctrl driver for Armada XP
  ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs
  ARM: mvebu: Add pinctrl support to Armada XP SoCs
  ARM: mvebu: Add pinctrl support to Armada 370 SoC
  ARM: mvebu: adjust Armada XP evaluation board DTS

 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 ++
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 +++++++
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    7 +
 arch/arm/boot/dts/armada-370.dtsi                  |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    4 +-
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   27 +
 drivers/pinctrl/Kconfig                            |   22 +
 drivers/pinctrl/Makefile                           |    5 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 +++++++++++
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++
 drivers/pinctrl/pinctrl-kirkwood.c                 |  462 ++++++++++++
 drivers/pinctrl/pinctrl-mvebu.c                    |  761 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 20 files changed, 3639 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
 create mode 100644 drivers/pinctrl/pinctrl-dove.c
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h
---
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:22 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:22 +0200
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
v2:
- restructured Kconfig to have a common PINCTRL_MVEBU that are selected by
  SoC specific drivers.
- cleaned pinctrl-mvebu and replaced 'magic numbers' by defines
- make use of of_iomap instead of get_resource/ioremap
- extended include documentation and checked with scripts/kernel-doc
- cleaned devicetree binding documentation

Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    6 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  761 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 6 files changed, 1006 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 0000000..dc419e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,45 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a2b6f74..2eb3f6b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..20bfdc3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,12 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..007ed32 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 0000000..5397765
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,761 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+#define MPPS_PER_REG	8
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+
+struct mvebu_pinctrl_function {
+	unsigned fid;
+	const char *name;
+	const char *setting;
+	const char **groups;
+	unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+	const char *name;
+	struct mvebu_mpp_ctrl *ctrl;
+	struct mvebu_mpp_ctrl_setting *settings;
+	unsigned num_settings;
+	unsigned gid;
+	unsigned *pins;
+	unsigned npins;
+};
+
+struct mvebu_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_desc desc;
+	void __iomem *base;
+	struct mvebu_pinctrl_group *groups;
+	unsigned num_groups;
+	struct mvebu_pinctrl_function *functions;
+	unsigned num_functions;
+	u8 variant;
+};
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+	struct mvebu_pinctrl *pctl, unsigned pid)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_groups; n++) {
+		if (pid >= pctl->groups[n].pins[0] &&
+		    pid < pctl->groups[n].pins[0] +
+			pctl->groups[n].npins)
+			return &pctl->groups[n];
+	}
+	return NULL;
+}
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+	struct mvebu_pinctrl *pctl, const char *name)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_groups; n++) {
+		if (strcmp(name, pctl->groups[n].name) == 0)
+			return &pctl->groups[n];
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+	unsigned long config)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (config == grp->settings[n].val) {
+			if (!pctl->variant || (pctl->variant &
+					       grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+	const char *name)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (strcmp(name, grp->settings[n].name) == 0) {
+			if (!pctl->variant || (pctl->variant &
+					       grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+	unsigned n;
+	for (n = 0; n < grp->num_settings; n++) {
+		if (grp->settings[n].flags &
+			(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+			if (!pctl->variant || (pctl->variant &
+						grp->settings[n].variant))
+				return &grp->settings[n];
+		}
+	}
+	return NULL;
+}
+
+struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+	struct mvebu_pinctrl *pctl, const char *name)
+{
+	unsigned n;
+	for (n = 0; n < pctl->num_functions; n++) {
+		if (strcmp(name, pctl->functions[n].name) == 0)
+			return &pctl->functions[n];
+	}
+	return NULL;
+}
+
+/*
+ * Common mpp pin configuration registers on MVEBU are
+ * registers of eight 4-bit values for each mpp setting.
+ * Register offset and bit mask are calculated accordingly below.
+ */
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+				struct mvebu_pinctrl_group *grp,
+				unsigned long *config)
+{
+	unsigned pin = grp->gid;
+	unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+	unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+
+	*config = readl(pctl->base + off);
+	*config >>= shift;
+	*config &= MPP_MASK;
+
+	return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+				struct mvebu_pinctrl_group *grp,
+				unsigned long config)
+{
+	unsigned pin = grp->gid;
+	unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+	unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+	unsigned long reg;
+
+	reg = readl(pctl->base + off);
+	reg &= ~(MPP_MASK << shift);
+	reg |= (config << shift);
+	writel(reg, pctl->base + off);
+
+	return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+				unsigned gid, unsigned long *config)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+	if (!grp->ctrl)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_get)
+		return grp->ctrl->mpp_get(grp->ctrl, config);
+
+	return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+				unsigned gid, unsigned long config)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+	if (!grp->ctrl)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_set)
+		return grp->ctrl->mpp_set(grp->ctrl, config);
+
+	return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+					struct seq_file *s, unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+	struct mvebu_mpp_ctrl_setting *curr;
+	unsigned long config;
+	unsigned n;
+
+	if (mvebu_pinconf_group_get(pctldev, gid, &config))
+		return;
+
+	curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+	if (curr) {
+		seq_printf(s, "current: %s", curr->name);
+		if (curr->subname)
+			seq_printf(s, "(%s)", curr->subname);
+		if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+			seq_printf(s, "(");
+			if (curr->flags & MVEBU_SETTING_GPI)
+				seq_printf(s, "i");
+			if (curr->flags & MVEBU_SETTING_GPO)
+				seq_printf(s, "o");
+			seq_printf(s, ")");
+		}
+	} else
+		seq_printf(s, "current: UNKNOWN");
+
+	if (grp->num_settings > 1) {
+		seq_printf(s, ", available = [");
+		for (n = 0; n < grp->num_settings; n++) {
+			if (curr == &grp->settings[n])
+				continue;
+
+			/* skip unsupported settings for this variant */
+			if (pctl->variant &&
+			    !(pctl->variant & grp->settings[n].variant))
+				continue;
+
+			seq_printf(s, " %s", grp->settings[n].name);
+			if (grp->settings[n].subname)
+				seq_printf(s, "(%s)", grp->settings[n].subname);
+			if (grp->settings[n].flags &
+				(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+				seq_printf(s, "(");
+				if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+					seq_printf(s, "i");
+				if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+					seq_printf(s, "o");
+				seq_printf(s, ")");
+			}
+		}
+		seq_printf(s, " ]");
+	}
+	return;
+}
+
+struct pinconf_ops mvebu_pinconf_ops = {
+	.pin_config_group_get = mvebu_pinconf_group_get,
+	.pin_config_group_set = mvebu_pinconf_group_set,
+	.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+					unsigned fid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+				const char * const **groups,
+				unsigned * const num_groups)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+	*groups = pctl->functions[fid].groups;
+	*num_groups = pctl->functions[fid].num_groups;
+	return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+			unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+	struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+	struct mvebu_mpp_ctrl_setting *setting;
+	int ret;
+
+	setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+						     func->setting);
+	if (!setting) {
+		dev_err(pctl->dev,
+			"unable to find setting %s in group %s\n",
+			func->setting, func->groups[gid]);
+		return -EINVAL;
+	}
+
+	ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+	if (ret) {
+		dev_err(pctl->dev, "cannot set group %s to %s\n",
+			func->groups[gid], func->setting);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+			struct pinctrl_gpio_range *range, unsigned offset)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp;
+	struct mvebu_mpp_ctrl_setting *setting;
+
+	grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_gpio_req)
+		return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+	setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+	if (!setting)
+		return -ENOTSUPP;
+
+	return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+	   struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct mvebu_pinctrl_group *grp;
+	struct mvebu_mpp_ctrl_setting *setting;
+
+	grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+	if (!grp)
+		return -EINVAL;
+
+	if (grp->ctrl->mpp_gpio_dir)
+		return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+	setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+	if (!setting)
+		return -ENOTSUPP;
+
+	if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+	    (!input && (setting->flags & MVEBU_SETTING_GPO)))
+		return 0;
+
+	return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+	.get_functions_count = mvebu_pinmux_get_funcs_count,
+	.get_function_name = mvebu_pinmux_get_func_name,
+	.get_function_groups = mvebu_pinmux_get_groups,
+	.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+	.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+	.enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+						unsigned gid)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+					unsigned gid, const unsigned **pins,
+					unsigned *num_pins)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	*pins = pctl->groups[gid].pins;
+	*num_pins = pctl->groups[gid].npins;
+	return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+					struct device_node *np,
+					struct pinctrl_map **map,
+					unsigned *num_maps)
+{
+	struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+	struct property *prop;
+	const char *function;
+	const char *group;
+	int ret, nmaps, n;
+
+	*map = NULL;
+	*num_maps = 0;
+
+	ret = of_property_read_string(np, "marvell,function", &function);
+	if (ret) {
+		dev_err(pctl->dev,
+			"missing marvell,function in node %s\n", np->name);
+		return 0;
+	}
+
+	nmaps = of_property_count_strings(np, "marvell,pins");
+	if (nmaps < 0) {
+		dev_err(pctl->dev,
+			"missing marvell,pins in node %s\n", np->name);
+		return 0;
+	}
+
+	*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+	if (map == NULL) {
+		dev_err(pctl->dev,
+			"cannot allocate pinctrl_map memory for %s\n",
+			np->name);
+		return -ENOMEM;
+	}
+
+	n = 0;
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			continue;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				function, group);
+			continue;
+		}
+
+		(*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+		(*map)[n].data.mux.group = group;
+		(*map)[n].data.mux.function = np->name;
+		n++;
+	}
+
+	*num_maps = nmaps;
+
+	return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+				struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+	.get_groups_count = mvebu_pinctrl_get_groups_count,
+	.get_group_name = mvebu_pinctrl_get_group_name,
+	.get_group_pins = mvebu_pinctrl_get_group_pins,
+	.dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+	.dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+					struct device_node *np, unsigned idx)
+{
+	struct mvebu_pinctrl_function *func = &pctl->functions[idx];
+	struct property *prop;
+	const char *setting;
+	const char *group;
+	unsigned n = 0;
+	int ret, num_groups;
+
+	ret = of_property_read_string(np, "marvell,function", &setting);
+	if (ret) {
+		dev_err(pctl->dev,
+			"missing marvell,function in node %s\n", np->name);
+		return -EINVAL;
+	}
+
+	num_groups = of_property_count_strings(np, "marvell,pins");
+	if (num_groups <= 0) {
+		dev_err(pctl->dev,
+			"missing marvell,pins in node %s\n", np->name);
+		return -EINVAL;
+	}
+
+	func->fid = idx;
+	func->name = np->name;
+	func->setting = setting;
+	func->num_groups = num_groups;
+	func->groups = devm_kzalloc(pctl->dev, num_groups * sizeof(char *),
+				    GFP_KERNEL);
+	if (!func->groups) {
+		dev_err(pctl->dev,
+			"unable to alloc function groups\n");
+		return -ENOMEM;
+	}
+
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			return -EINVAL;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, setting)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				setting, group);
+			return -EINVAL;
+		}
+
+		func->groups[n++] = group;
+	}
+	return 0;
+}
+
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
+					struct mvebu_pinctrl *pctl)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct device_node *np;
+	unsigned nfuncs = 0, n = 0;
+	int ret;
+
+	if (!node)
+		return -ENODEV;
+
+	nfuncs = of_get_child_count(node);
+	if (nfuncs <= 0) {
+		dev_warn(pctl->dev, "no function defined in device node\n");
+		return 0;
+	}
+
+	pctl->num_functions = nfuncs;
+	pctl->functions = devm_kzalloc(&pdev->dev, nfuncs *
+				sizeof(struct mvebu_pinctrl_function),
+				GFP_KERNEL);
+	if (!pctl->functions) {
+		dev_err(pctl->dev, "unable to alloc functions\n");
+		return -ENOMEM;
+	}
+
+	for_each_child_of_node(node, np) {
+		ret = mvebu_pinctrl_dt_parse_function(pctl, np, n++);
+		if (ret) {
+			dev_warn(pctl->dev, "failed to parse function %s\n",
+				np->name);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+	struct device_node *np = pdev->dev.of_node;
+	struct mvebu_pinctrl *pctl;
+	void __iomem *base;
+	struct pinctrl_pin_desc *pdesc;
+	unsigned gid, n, k;
+	int ret;
+
+	if (!soc || !soc->controls || !soc->modes) {
+		dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+		return -EINVAL;
+	}
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		dev_err(&pdev->dev, "unable to get base address\n");
+		return -ENODEV;
+	}
+
+	pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+			GFP_KERNEL);
+	if (!pctl) {
+		dev_err(&pdev->dev, "unable to alloc driver\n");
+		return -ENOMEM;
+	}
+
+	pctl->desc.name = dev_name(&pdev->dev);
+	pctl->desc.owner = THIS_MODULE;
+	pctl->desc.pctlops = &mvebu_pinctrl_ops;
+	pctl->desc.pmxops = &mvebu_pinmux_ops;
+	pctl->desc.confops = &mvebu_pinconf_ops;
+	pctl->variant = soc->variant;
+	pctl->base = base;
+	pctl->dev = &pdev->dev;
+	platform_set_drvdata(pdev, pctl);
+
+	/* count controls and create names for mvebu generic
+	   register controls; also does sanity checks */
+	pctl->num_groups = 0;
+	pctl->desc.npins = 0;
+	for (n = 0; n < soc->ncontrols; n++) {
+		struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+		char *names;
+
+		pctl->desc.npins += ctrl->npins;
+		/* initial control pins */
+		for (k = 0; k < ctrl->npins; k++)
+			ctrl->pins[k] = ctrl->pid + k;
+
+		/* special soc specific control */
+		if (ctrl->mpp_get || ctrl->mpp_set) {
+			if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+				dev_err(&pdev->dev, "wrong soc control info\n");
+				return -EINVAL;
+			}
+			pctl->num_groups += 1;
+			continue;
+		}
+
+		/* generic mvebu register control */
+		names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+		if (!names) {
+			dev_err(&pdev->dev, "failed to alloc mpp names\n");
+			return -ENOMEM;
+		}
+		for (k = 0; k < ctrl->npins; k++)
+			sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+		ctrl->name = names;
+		pctl->num_groups += ctrl->npins;
+	}
+
+	pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+			     sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+	if (!pdesc) {
+		dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+		return -ENOMEM;
+	}
+
+	for (n = 0; n < pctl->desc.npins; n++)
+		pdesc[n].number = n;
+	pctl->desc.pins = pdesc;
+
+	pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+			     sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+	if (!pctl->groups) {
+		dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+		return -ENOMEM;
+	}
+
+	/* assign mpp controls to groups */
+	gid = 0;
+	for (n = 0; n < soc->ncontrols; n++) {
+		struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+		pctl->groups[gid].gid = gid;
+		pctl->groups[gid].ctrl = ctrl;
+		pctl->groups[gid].name = ctrl->name;
+		pctl->groups[gid].pins = ctrl->pins;
+		pctl->groups[gid].npins = ctrl->npins;
+
+		/* generic mvebu register control maps to a number of groups */
+		if (!ctrl->mpp_get && !ctrl->mpp_set) {
+			pctl->groups[gid].npins = 1;
+
+			for (k = 1; k < ctrl->npins; k++) {
+				gid++;
+				pctl->groups[gid].gid = gid;
+				pctl->groups[gid].ctrl = ctrl;
+				pctl->groups[gid].name = &ctrl->name[8*k];
+				pctl->groups[gid].pins = &ctrl->pins[k];
+				pctl->groups[gid].npins = 1;
+			}
+		}
+		gid++;
+	}
+
+	/* assign mpp modes to groups */
+	for (n = 0; n < soc->nmodes; n++) {
+		struct mvebu_mpp_mode *mode = &soc->modes[n];
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+		unsigned num_settings;
+
+		if (!grp) {
+			dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+				mode->pid);
+			continue;
+		}
+
+		for (num_settings = 0; ;) {
+			struct mvebu_mpp_ctrl_setting *set =
+				&mode->settings[num_settings];
+
+			if (!set->name)
+				break;
+			num_settings++;
+
+			/* skip unsupported settings for this variant */
+			if (pctl->variant && !(pctl->variant & set->variant))
+				continue;
+
+			/* find gpio/gpo/gpi settings */
+			if (strcmp(set->name, "gpio") == 0)
+				set->flags = MVEBU_SETTING_GPI |
+					MVEBU_SETTING_GPO;
+			else if (strcmp(set->name, "gpo") == 0)
+				set->flags = MVEBU_SETTING_GPO;
+			else if (strcmp(set->name, "gpi") == 0)
+				set->flags = MVEBU_SETTING_GPI;
+		}
+
+		grp->settings = mode->settings;
+		grp->num_settings = num_settings;
+	}
+
+	ret = mvebu_pinctrl_dt_parse(pdev, pctl);
+	if (ret) {
+		/* look for pinmux functions in platform_device data */
+		dev_err(&pdev->dev, "unable to parse device tree\n");
+		return ret;
+	}
+
+	pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+	if (!pctl->pctldev) {
+		dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+	/* register gpio ranges */
+	for (n = 0; n < soc->ngpioranges; n++)
+		pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+	return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+	pinctrl_unregister(pctl->pctldev);
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 0000000..90bd3be
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,192 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/**
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
+ * internal function, inside the SoC. Each muxable unit can be switched
+ * between two or more different settings, e.g. assign mpp pin 13 to
+ * uart1 or sata.
+ *
+ * If optional mpp_get/_set functions are set these are used to get/set
+ * a specific mode. Otherwise it is assumed that the mpp control is based
+ * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
+ * functions can be used to allow pin settings with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+	const char *name;
+	u8 pid;
+	u8 npins;
+	unsigned *pins;
+	int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+	int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+	int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+	int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/**
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * A ctrl_setting describes a specific internal mux function that a mpp pin
+ * can be switched to. The value (val) will be written in the corresponding
+ * register for common mpp pin configuration registers on MVEBU. SoC specific
+ * mpp_get/_set function may use val to distinguish between different settings.
+ *
+ * The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes.
+ *
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization and stored in flags.
+ *
+ * The variant can be used to combine different revisions of one SoC to a
+ * common pinctrl driver. It is matched (AND) with variant of soc_info to
+ * determine if a setting is available on the current SoC revision.
+ */
+struct mvebu_mpp_ctrl_setting {
+	u8 val;
+	const char *name;
+	const char *subname;
+	u8 variant;
+	u8 flags;
+#define  MVEBU_SETTING_GPO	(1 << 0)
+#define  MVEBU_SETTING_GPI	(1 << 1)
+};
+
+/**
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ *
+ * A mode connects all available settings with the corresponding mpp_ctrl
+ * given by pid.
+ */
+struct mvebu_mpp_mode {
+	u8 pid;
+	struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/**
+ * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ *
+ * This struct describes all pinctrl related information for a specific SoC.
+ * If variant is unequal 0 it will be matched (AND) with variant of each
+ * setting and allows to distinguish between different revisions of one SoC.
+ */
+struct mvebu_pinctrl_soc_info {
+	u8 variant;
+	struct mvebu_mpp_ctrl *controls;
+	int ncontrols;
+	struct mvebu_mpp_mode *modes;
+	int nmodes;
+	struct pinctrl_gpio_range *gpioranges;
+	int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh)				\
+	{							\
+		.name = NULL,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = NULL,				\
+		.mpp_set = NULL,				\
+		.mpp_gpio_req = NULL,				\
+		.mpp_gpio_dir = NULL,				\
+	}
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func)			\
+	{							\
+		.name = _name,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = _func ## _get,			\
+		.mpp_set = _func ## _set,			\
+		.mpp_gpio_req = NULL,				\
+		.mpp_gpio_dir = NULL,				\
+	}
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func)		\
+	{							\
+		.name = _name,					\
+		.pid = _idl,					\
+		.npins = _idh - _idl + 1,			\
+		.pins = (unsigned[_idh - _idl + 1]) { },	\
+		.mpp_get = _func ## _get,			\
+		.mpp_set = _func ## _set,			\
+		.mpp_gpio_req = _func ## _gpio_req,		\
+		.mpp_gpio_dir = _func ## _gpio_dir,		\
+	}
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	{							\
+		.val = _val,					\
+		.name = _name,					\
+		.subname = _subname,				\
+		.variant = _mask,				\
+		.flags = 0,					\
+	}
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)		\
+	_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname)			\
+	MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...)					\
+	{							\
+		.pid = _id,					\
+		.settings = (struct mvebu_mpp_ctrl_setting[]){	\
+			__VA_ARGS__, { } },			\
+	}
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins)	\
+	{							\
+		.name = "mvebu-gpio",				\
+		.id = _id,					\
+		.pin_base = _pinbase,				\
+		.base = _gpiobase,				\
+		.npins = _npins,				\
+	}
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:23 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:23 +0200
Subject: [PATCH v2 2/9] pinctrl: mvebu: dove pinctrl driver
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-3-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be
  always selected by arch/arm/mach-mvebu/Kconfig
- cleaned pinctrl-dove and replaced 'magic numbers' by defines
- use devm_clk_get for (now optional) pdma clock and add to required
  properties in devicetree binding documentation

Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 +++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++++++
 4 files changed, 699 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 0000000..a648aaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 20bfdc3..f15eba4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -151,6 +151,10 @@ config PINCTRL_MVEBU
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_DOVE
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 007ed32..d1327df 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 0000000..cb31b63
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,622 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE		0xfde00000
+#define DOVE_MPP_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL	(DOVE_MPP_VIRT_BASE + 0x10)
+#define  DOVE_AU0_AC97_SEL		BIT(16)
+#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1	BIT(7)
+#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2	BIT(20)
+#define  DOVE_TWSI_ENABLE_OPTION3	BIT(21)
+#define  DOVE_TWSI_OPTION3_GPIO		BIT(22)
+#define DOVE_SSP_CTRL_STATUS_1		(DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1		BIT(0)
+#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN	BIT(1)
+#define  DOVE_NAND_GPIO_EN		BIT(0)
+#define DOVE_GPIO_LO_VIRT_BASE		(DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define  DOVE_SPI_GPIO_SEL		BIT(5)
+#define  DOVE_UART1_GPIO_SEL		BIT(4)
+#define  DOVE_AU1_GPIO_SEL		BIT(3)
+#define  DOVE_CAM_GPIO_SEL		BIT(2)
+#define  DOVE_SD1_GPIO_SEL		BIT(1)
+#define  DOVE_SD0_GPIO_SEL		BIT(0)
+
+#define MPPS_PER_REG	8
+#define MPP_BITS	4
+#define MPP_MASK	0xf
+
+#define CONFIG_PMU	BIT(4)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				 unsigned long *config)
+{
+	unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+	unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+	if (pmu & (1 << ctrl->pid))
+		*config = CONFIG_PMU;
+	else
+		*config = (mpp >> shift) & MPP_MASK;
+	return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				 unsigned long config)
+{
+	unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+	unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+	unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+	if (config == CONFIG_PMU)
+		writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+	else {
+		writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+		mpp &= ~(MPP_MASK << shift);
+		mpp |= config << shift;
+		writel(mpp, DOVE_MPP_VIRT_BASE + off);
+	}
+	return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long mask;
+
+	switch (ctrl->pid) {
+	case 24: /* mpp_camera */
+		mask = DOVE_CAM_GPIO_SEL;
+		break;
+	case 40: /* mpp_sdio0 */
+		mask = DOVE_SD0_GPIO_SEL;
+		break;
+	case 46: /* mpp_sdio1 */
+		mask = DOVE_SD1_GPIO_SEL;
+		break;
+	case 58: /* mpp_spi0 */
+		mask = DOVE_SPI_GPIO_SEL;
+		break;
+	case 62: /* mpp_uart1 */
+		mask = DOVE_UART1_GPIO_SEL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	*config = ((mpp4 & mask) != 0);
+
+	return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long mask;
+
+	switch (ctrl->pid) {
+	case 24: /* mpp_camera */
+		mask = DOVE_CAM_GPIO_SEL;
+		break;
+	case 40: /* mpp_sdio0 */
+		mask = DOVE_SD0_GPIO_SEL;
+		break;
+	case 46: /* mpp_sdio1 */
+		mask = DOVE_SD1_GPIO_SEL;
+		break;
+	case 58: /* mpp_spi0 */
+		mask = DOVE_SPI_GPIO_SEL;
+		break;
+	case 62: /* mpp_uart1 */
+		mask = DOVE_UART1_GPIO_SEL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	mpp4 &= ~mask;
+	if (config)
+		mpp4 |= mask;
+
+	writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+	return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+	*config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+	return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long config)
+{
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+	gmpp &= ~DOVE_NAND_GPIO_EN;
+	if (config)
+		gmpp |= DOVE_NAND_GPIO_EN;
+
+	writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+	return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long *config)
+{
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+	*config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+	return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+	pmu &= ~DOVE_AU0_AC97_SEL;
+	if (config)
+		pmu |= DOVE_AU0_AC97_SEL;
+	writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+	return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long *config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	*config = 0;
+	if (mpp4 & DOVE_AU1_GPIO_SEL)
+		*config |= BIT(3);
+	if (sspc1 & DOVE_SSP_ON_AU1)
+		*config |= BIT(2);
+	if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+		*config |= BIT(1);
+	if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+		*config |= BIT(0);
+
+	/* SSP/TWSI only if I2S1 not set*/
+	if ((*config & BIT(3)) == 0)
+		*config &= ~(BIT(2) | BIT(0));
+	/* TWSI only if SPDIFO not set*/
+	if ((*config & BIT(1)) == 0)
+		*config &= ~BIT(0);
+	return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+	unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	if (config & BIT(0))
+		gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+	if (config & BIT(1))
+		gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+	if (config & BIT(2))
+		sspc1 |= DOVE_SSP_ON_AU1;
+	if (config & BIT(3))
+		mpp4 |= DOVE_AU1_GPIO_SEL;
+
+	writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+	writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+	writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+	return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+	unsigned long config;
+
+	dove_audio1_ctrl_get(ctrl, &config);
+
+	switch (config) {
+	case 0x02: /* i2s1 : gpio[56:57] */
+	case 0x0e: /* ssp  : gpio[56:57] */
+		if (pid >= 56)
+			return 0;
+		return -ENOTSUPP;
+	case 0x08: /* spdifo : gpio[52:55] */
+	case 0x0b: /* twsi   : gpio[52:55] */
+		if (pid <= 55)
+			return 0;
+		return -ENOTSUPP;
+	case 0x0a: /* all gpio */
+		return 0;
+	/* 0x00 : i2s1/spdifo : no gpio */
+	/* 0x0c : ssp/spdifo  : no gpio */
+	/* 0x0f : ssp/twsi    : no gpio */
+	}
+	return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+				bool input)
+{
+	if (pid < 52 || pid > 57)
+		return -ENOTSUPP;
+	return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	*config = 0;
+	if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+		*config = 1;
+	else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+		*config = 2;
+	else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+		*config = 3;
+
+	return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+	gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+	switch (config) {
+	case 1:
+		gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+		break;
+	case 2:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+		break;
+	case 3:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+	return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+	MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+	MPP_REG_CTRL(16, 23),
+	MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+	MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+	MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+	MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+	MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+	MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(1,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "cts"),
+		MPP_FUNCTION(0x03, "sdio0", "wp"),
+		MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(2,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "prsnt"),
+		MPP_FUNCTION(0x02, "uart2", "txd"),
+		MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x04, "uart1", "rts"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(3,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "act"),
+		MPP_FUNCTION(0x02, "uart2", "rxd"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "uart1", "cts"),
+		MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(4,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rts"),
+		MPP_FUNCTION(0x03, "sdio1", "cd"),
+		MPP_FUNCTION(0x04, "spi1", "miso"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(5,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "cts"),
+		MPP_FUNCTION(0x03, "sdio1", "wp"),
+		MPP_FUNCTION(0x04, "spi1", "cs"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(6,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "txd"),
+		MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x04, "spi1", "mosi"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(7,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rxd"),
+		MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x04, "spi1", "sck"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(8,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "watchdog", "rstout"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(9,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x05, "pex1", "clkreq"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(10,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x05, "ssp", "sclk"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(11,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "prsnt"),
+		MPP_FUNCTION(0x02, "sata-1", "act"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x05, "pex0", "clkreq"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(12,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "sata", "act"),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "audio0", "extclk"),
+		MPP_FUNCTION(0x04, "sdio1", "cd"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(13,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "cts"),
+		MPP_FUNCTION(0x03, "audio1", "extclk"),
+		MPP_FUNCTION(0x04, "sdio1", "wp"),
+		MPP_FUNCTION(0x05, "ssp", "extclk"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(14,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "txd"),
+		MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x05, "ssp", "rxd"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(15,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rxd"),
+		MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x05, "ssp", "sfrm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
+	MPP_MODE(16,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+		MPP_FUNCTION(0x05, "ac97", "sdi1")),
+	MPP_MODE(17,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+		MPP_FUNCTION(0x02, "uart3", "cts"),
+		MPP_FUNCTION(0x03, "sdio0", "wp"),
+		MPP_FUNCTION(0x04, "twsi", "sda"),
+		MPP_FUNCTION(0x05, "ac97", "sdi2")),
+	MPP_MODE(18,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "txd"),
+		MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x04, "lcd0", "pwm"),
+		MPP_FUNCTION(0x05, "ac97", "sdi3")),
+	MPP_MODE(19,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart3", "rxd"),
+		MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x04, "twsi", "sck")),
+	MPP_MODE(20,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "ac97", "sysclko"),
+		MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+		MPP_FUNCTION(0x03, "sdio1", "cd"),
+		MPP_FUNCTION(0x05, "sdio0", "cd"),
+		MPP_FUNCTION(0x06, "spi1", "miso")),
+	MPP_MODE(21,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "uart1", "rts"),
+		MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+		MPP_FUNCTION(0x03, "sdio1", "wp"),
+		MPP_FUNCTION(0x04, "ssp", "sfrm"),
+		MPP_FUNCTION(0x05, "sdio0", "wp"),
+		MPP_FUNCTION(0x06, "spi1", "cs")),
+	MPP_MODE(22,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x01, "uart1", "cts"),
+		MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+		MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+		MPP_FUNCTION(0x04, "ssp", "txd"),
+		MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+		MPP_FUNCTION(0x06, "spi1", "mosi")),
+	MPP_MODE(23,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+		MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+		MPP_FUNCTION(0x04, "ssp", "sclk"),
+		MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+		MPP_FUNCTION(0x06, "spi1", "sck")),
+	MPP_MODE(24,
+		MPP_FUNCTION(0x00, "camera", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(40,
+		MPP_FUNCTION(0x00, "sdio0", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(46,
+		MPP_FUNCTION(0x00, "sdio1", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(52,
+		MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+		MPP_FUNCTION(0x02, "i2s1", NULL),
+		MPP_FUNCTION(0x08, "spdifo", NULL),
+		MPP_FUNCTION(0x0a, "gpio", NULL),
+		MPP_FUNCTION(0x0b, "twsi", NULL),
+		MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+		MPP_FUNCTION(0x0e, "ssp", NULL),
+		MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+	MPP_MODE(58,
+		MPP_FUNCTION(0x00, "spi0", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(62,
+		MPP_FUNCTION(0x00, "uart1", NULL),
+		MPP_FUNCTION(0x01, "gpio", NULL)),
+	MPP_MODE(64,
+		MPP_FUNCTION(0x00, "nand", NULL),
+		MPP_FUNCTION(0x01, "gpo", NULL)),
+	MPP_MODE(72,
+		MPP_FUNCTION(0x00, "i2s", NULL),
+		MPP_FUNCTION(0x01, "ac97", NULL)),
+	MPP_MODE(73,
+		MPP_FUNCTION(0x00, "none", NULL),
+		MPP_FUNCTION(0x01, "opt1", NULL),
+		MPP_FUNCTION(0x02, "opt2", NULL),
+		MPP_FUNCTION(0x03, "opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32, 32),
+	MPP_GPIO_RANGE(2, 64, 64,  8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+	.controls = dove_mpp_controls,
+	.ncontrols = ARRAY_SIZE(dove_mpp_controls),
+	.modes = dove_mpp_modes,
+	.nmodes = ARRAY_SIZE(dove_mpp_modes),
+	.gpioranges = dove_mpp_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+	.variant = 0,
+};
+
+static struct clk *clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+	{ }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match =
+		of_match_device(dove_pinctrl_of_match, &pdev->dev);
+
+	if (match)
+		pdev->dev.platform_data = match->data;
+
+	/*
+	 * General MPP Configuration Register is part of pdma registers.
+	 * grab clk to make sure it is ticking.
+	 */
+	clk = devm_clk_get(&pdev->dev, NULL);
+	if (!IS_ERR(clk))
+		clk_prepare_enable(clk);
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+	int ret;
+
+	ret = mvebu_pinctrl_remove(pdev);
+	if (!IS_ERR(clk))
+		clk_disable_unprepare(clk);
+	return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+	.driver = {
+		.name = "dove-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(dove_pinctrl_of_match),
+	},
+	.probe = dove_pinctrl_probe,
+	.remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:25 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:25 +0200
Subject: [PATCH v2 4/9] pinctrl: mvebu: add pinctrl driver for Armada 370
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-5-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0

Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 521 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 0000000..01ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 31c0bba..e16b8b0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_370
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3006294..e6d6667 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 0000000..c907647
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+	MPP_MODE(0,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "uart0", "rxd")),
+	MPP_MODE(1,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "uart0", "txd")),
+	MPP_MODE(2,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "i2c0", "sck"),
+	   MPP_FUNCTION(0x2, "uart0", "txd")),
+	MPP_MODE(3,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "i2c0", "sda"),
+	   MPP_FUNCTION(0x2, "uart0", "rxd")),
+	MPP_MODE(4,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+	MPP_MODE(5,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txclko"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x4, "spi1", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "mclk")),
+	MPP_MODE(6,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd0"),
+	   MPP_FUNCTION(0x2, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x4, "tdm", "rst"),
+	   MPP_FUNCTION(0x5, "audio", "sdo")),
+	MPP_MODE(7,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd1"),
+	   MPP_FUNCTION(0x4, "tdm", "tdx"),
+	   MPP_FUNCTION(0x5, "audio", "lrclk")),
+	MPP_MODE(8,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd2"),
+	   MPP_FUNCTION(0x2, "uart0", "rts"),
+	   MPP_FUNCTION(0x4, "tdm", "drx"),
+	   MPP_FUNCTION(0x5, "audio", "bclk")),
+	MPP_MODE(9,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd3"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x3, "sd0", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "spdifo")),
+	MPP_MODE(10,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txctl"),
+	   MPP_FUNCTION(0x2, "uart0", "cts"),
+	   MPP_FUNCTION(0x4, "tdm", "fsync"),
+	   MPP_FUNCTION(0x5, "audio", "sdi")),
+	MPP_MODE(11,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd0"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "sd0", "cmd"),
+	   MPP_FUNCTION(0x4, "spi0", "cs1"),
+	   MPP_FUNCTION(0x5, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x6, "spi1", "cs1")),
+	MPP_MODE(12,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd1"),
+	   MPP_FUNCTION(0x2, "i2c1", "sda"),
+	   MPP_FUNCTION(0x3, "sd0", "d0"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0"),
+	   MPP_FUNCTION(0x5, "audio", "spdifi")),
+	MPP_MODE(13,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd2"),
+	   MPP_FUNCTION(0x2, "i2c1", "sck"),
+	   MPP_FUNCTION(0x3, "sd0", "d1"),
+	   MPP_FUNCTION(0x4, "tdm", "pclk"),
+	   MPP_FUNCTION(0x5, "audio", "rmclk")),
+	MPP_MODE(14,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd3"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x3, "sd0", "d2"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi"),
+	   MPP_FUNCTION(0x5, "spi0", "cs2")),
+	MPP_MODE(15,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxctl"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+	   MPP_FUNCTION(0x3, "sd0", "d3"),
+	   MPP_FUNCTION(0x4, "spi1", "miso"),
+	   MPP_FUNCTION(0x5, "spi0", "cs3")),
+	MPP_MODE(16,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxclk"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x4, "tdm", "int"),
+	   MPP_FUNCTION(0x5, "audio", "extclk")),
+	MPP_MODE(17,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge", "mdc")),
+	MPP_MODE(18,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge", "mdio")),
+	MPP_MODE(19,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txclk"),
+	   MPP_FUNCTION(0x2, "ge1", "txclkout"),
+	   MPP_FUNCTION(0x4, "tdm", "pclk")),
+	MPP_MODE(20,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd4"),
+	   MPP_FUNCTION(0x2, "ge1", "txd0")),
+	MPP_MODE(21,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd5"),
+	   MPP_FUNCTION(0x2, "ge1", "txd1"),
+	   MPP_FUNCTION(0x4, "uart1", "txd")),
+	MPP_MODE(22,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd6"),
+	   MPP_FUNCTION(0x2, "ge1", "txd2"),
+	   MPP_FUNCTION(0x4, "uart0", "rts")),
+	MPP_MODE(23,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "txd7"),
+	   MPP_FUNCTION(0x2, "ge1", "txd3"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi")),
+	MPP_MODE(24,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "col"),
+	   MPP_FUNCTION(0x2, "ge1", "txctl"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0")),
+	MPP_MODE(25,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxerr"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd0"),
+	   MPP_FUNCTION(0x4, "uart1", "rxd")),
+	MPP_MODE(26,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "crs"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd1"),
+	   MPP_FUNCTION(0x4, "spi1", "miso")),
+	MPP_MODE(27,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd4"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd2"),
+	   MPP_FUNCTION(0x4, "uart0", "cts")),
+	MPP_MODE(28,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd5"),
+	   MPP_FUNCTION(0x2, "ge1", "rxd3")),
+	MPP_MODE(29,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd6"),
+	   MPP_FUNCTION(0x2, "ge1", "rxctl"),
+	   MPP_FUNCTION(0x4, "i2c1", "sda")),
+	MPP_MODE(30,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "ge0", "rxd7"),
+	   MPP_FUNCTION(0x2, "ge1", "rxclk"),
+	   MPP_FUNCTION(0x4, "i2c1", "sck")),
+	MPP_MODE(31,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x3, "tclk", NULL),
+	   MPP_FUNCTION(0x4, "ge0", "txerr")),
+	MPP_MODE(32,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "cs0")),
+	MPP_MODE(33,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "bootcs"),
+	   MPP_FUNCTION(0x2, "spi0", "cs0")),
+	MPP_MODE(34,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "wen0"),
+	   MPP_FUNCTION(0x2, "spi0", "mosi")),
+	MPP_MODE(35,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "oen"),
+	   MPP_FUNCTION(0x2, "spi0", "sck")),
+	MPP_MODE(36,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a1"),
+	   MPP_FUNCTION(0x2, "spi0", "miso")),
+	MPP_MODE(37,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a0"),
+	   MPP_FUNCTION(0x2, "sata0", "prsnt")),
+	MPP_MODE(38,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ready"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "uart0", "cts")),
+	MPP_MODE(39,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad0"),
+	   MPP_FUNCTION(0x2, "audio", "spdifo")),
+	MPP_MODE(40,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad1"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "uart0", "rts")),
+	MPP_MODE(41,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad2"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd")),
+	MPP_MODE(42,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad3"),
+	   MPP_FUNCTION(0x2, "uart1", "txd")),
+	MPP_MODE(43,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad4"),
+	   MPP_FUNCTION(0x2, "audio", "bclk")),
+	MPP_MODE(44,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad5"),
+	   MPP_FUNCTION(0x2, "audio", "mclk")),
+	MPP_MODE(45,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad6"),
+	   MPP_FUNCTION(0x2, "audio", "lrclk")),
+	MPP_MODE(46,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad7"),
+	   MPP_FUNCTION(0x2, "audio", "sdo")),
+	MPP_MODE(47,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad8"),
+	   MPP_FUNCTION(0x3, "sd0", "clk"),
+	   MPP_FUNCTION(0x5, "audio", "spdifo")),
+	MPP_MODE(48,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad9"),
+	   MPP_FUNCTION(0x2, "uart0", "rts"),
+	   MPP_FUNCTION(0x3, "sd0", "cmd"),
+	   MPP_FUNCTION(0x4, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x5, "spi0", "cs1")),
+	MPP_MODE(49,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad10"),
+	   MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+	   MPP_FUNCTION(0x3, "sd0", "d0"),
+	   MPP_FUNCTION(0x4, "spi1", "cs0"),
+	   MPP_FUNCTION(0x5, "audio", "spdifi")),
+	MPP_MODE(50,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad11"),
+	   MPP_FUNCTION(0x2, "uart0", "cts"),
+	   MPP_FUNCTION(0x3, "sd0", "d1"),
+	   MPP_FUNCTION(0x4, "spi1", "miso"),
+	   MPP_FUNCTION(0x5, "audio", "rmclk")),
+	MPP_MODE(51,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad12"),
+	   MPP_FUNCTION(0x2, "i2c1", "sda"),
+	   MPP_FUNCTION(0x3, "sd0", "d2"),
+	   MPP_FUNCTION(0x4, "spi1", "mosi")),
+	MPP_MODE(52,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad13"),
+	   MPP_FUNCTION(0x2, "i2c1", "sck"),
+	   MPP_FUNCTION(0x3, "sd0", "d3"),
+	   MPP_FUNCTION(0x4, "spi1", "sck")),
+	MPP_MODE(53,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad14"),
+	   MPP_FUNCTION(0x2, "sd0", "clk"),
+	   MPP_FUNCTION(0x3, "tdm", "pclk"),
+	   MPP_FUNCTION(0x4, "spi0", "cs2"),
+	   MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+	MPP_MODE(54,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ad15"),
+	   MPP_FUNCTION(0x3, "tdm", "dtx")),
+	MPP_MODE(55,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs1"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x3, "tdm", "rst"),
+	   MPP_FUNCTION(0x4, "sata1", "prsnt"),
+	   MPP_FUNCTION(0x5, "sata0", "prsnt")),
+	MPP_MODE(56,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs2"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "uart0", "cts"),
+	   MPP_FUNCTION(0x4, "spi0", "cs3"),
+	   MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x6, "spi1", "cs1")),
+	MPP_MODE(57,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs3"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "tdm", "fsync"),
+	   MPP_FUNCTION(0x4, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x5, "audio", "sdo")),
+	MPP_MODE(58,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "cs0"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "tdm", "int"),
+	   MPP_FUNCTION(0x5, "audio", "extclk"),
+	   MPP_FUNCTION(0x6, "uart0", "rts")),
+	MPP_MODE(59,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ale0"),
+	   MPP_FUNCTION(0x2, "uart1", "rts"),
+	   MPP_FUNCTION(0x3, "uart0", "rts"),
+	   MPP_FUNCTION(0x5, "audio", "bclk")),
+	MPP_MODE(60,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "ale1"),
+	   MPP_FUNCTION(0x2, "uart1", "rxd"),
+	   MPP_FUNCTION(0x3, "sata0", "prsnt"),
+	   MPP_FUNCTION(0x4, "pcie", "rst-out"),
+	   MPP_FUNCTION(0x5, "audio", "sdi")),
+	MPP_MODE(61,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "dev", "wen1"),
+	   MPP_FUNCTION(0x2, "uart1", "txd"),
+	   MPP_FUNCTION(0x5, "audio", "rclk")),
+	MPP_MODE(62,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "dev", "a2"),
+	   MPP_FUNCTION(0x2, "uart1", "cts"),
+	   MPP_FUNCTION(0x3, "tdm", "drx"),
+	   MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+	   MPP_FUNCTION(0x5, "audio", "mclk"),
+	   MPP_FUNCTION(0x6, "uart0", "cts")),
+	MPP_MODE(63,
+	   MPP_FUNCTION(0x0, "gpo", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "sck"),
+	   MPP_FUNCTION(0x2, "tclk", NULL)),
+	MPP_MODE(64,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "miso"),
+	   MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+	MPP_MODE(65,
+	   MPP_FUNCTION(0x0, "gpio", NULL),
+	   MPP_FUNCTION(0x1, "spi0", "mosi"),
+	   MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,mv88f6710-pinctrl" },
+	{ },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+	MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+	soc->variant = 0; /* no variants for Armada 370 */
+	soc->controls = mv88f6710_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+	soc->modes = mv88f6710_mpp_modes;
+	soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+	soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+	soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+	.driver = {
+		.name = "armada-370-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+	},
+	.probe = armada_370_pinctrl_probe,
+	.remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:26 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:26 +0200
Subject: [PATCH v2 5/9] pinctrl: mvebu: add pinctrl driver for Armada XP
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-6-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
v2: replaced variant with enum and used bitops.h

Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++++++++++
 4 files changed, 573 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 0000000..bfa0a2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e16b8b0..a754144 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,6 +163,10 @@ config PINCTRL_ARMADA_370
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_XP
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e6d6667..f2ea050 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 0000000..40bd52a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,468 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-mvebu.h"
+
+enum armada_xp_variant {
+	V_MV78230	= BIT(0),
+	V_MV78260	= BIT(1),
+	V_MV78460	= BIT(2),
+	V_MV78230_PLUS	= (V_MV78230 | V_MV78260 | V_MV78460),
+	V_MV78260_PLUS	= (V_MV78260 | V_MV78460),
+};
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txclko",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d0",         V_MV78230_PLUS)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d1",         V_MV78230_PLUS)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d2",         V_MV78230_PLUS)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d3",         V_MV78230_PLUS)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d4",         V_MV78230_PLUS)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d5",         V_MV78230_PLUS)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d6",         V_MV78230_PLUS)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d7",         V_MV78230_PLUS)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d8",         V_MV78230_PLUS)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d9",         V_MV78230_PLUS)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d10",        V_MV78230_PLUS)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d11",        V_MV78230_PLUS)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "clkout",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d12",        V_MV78230_PLUS)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd5",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d13",        V_MV78230_PLUS)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd6",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d14",        V_MV78230_PLUS)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txd7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d15",        V_MV78230_PLUS)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "txclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d16",        V_MV78230_PLUS)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "col",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "txctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d17",        V_MV78230_PLUS)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "trig",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d18",        V_MV78230_PLUS)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "crs",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "evreq",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d19",        V_MV78230_PLUS)),
+	MPP_MODE(20,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "ptp", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d20",        V_MV78230_PLUS)),
+	MPP_MODE(21,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "mem", "bat",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d21",        V_MV78230_PLUS)),
+	MPP_MODE(22,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d22",        V_MV78230_PLUS)),
+	MPP_MODE(23,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "d23",        V_MV78230_PLUS)),
+	MPP_MODE(24,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re",   V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "rst",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "hsync",      V_MV78230_PLUS)),
+	MPP_MODE(25,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we",   V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "pclk",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vsync",      V_MV78230_PLUS)),
+	MPP_MODE(26,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "fsync",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+	MPP_MODE(27,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "trig",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "dtx",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "e",          V_MV78230_PLUS)),
+	MPP_MODE(28,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "evreq",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "drx",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "pwm",        V_MV78230_PLUS)),
+	MPP_MODE(29,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "ptp", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int0",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(30,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "clk",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int1",       V_MV78230_PLUS)),
+	MPP_MODE(31,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "cmd",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(32,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d0",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+	MPP_MODE(33,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d1",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int4",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS)),
+	MPP_MODE(34,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d2",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int5",       V_MV78230_PLUS)),
+	MPP_MODE(35,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "sd0", "d3",         V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int6",       V_MV78230_PLUS)),
+	MPP_MODE(36,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "mosi",       V_MV78230_PLUS)),
+	MPP_MODE(37,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "miso",       V_MV78230_PLUS)),
+	MPP_MODE(38,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "sck",        V_MV78230_PLUS)),
+	MPP_MODE(39,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs0",        V_MV78230_PLUS)),
+	MPP_MODE(40,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
+	MPP_MODE(41,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "spi", "cs2",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart2", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync",  V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1",   V_MV78230_PLUS)),
+	MPP_MODE(42,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "rxd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart0", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "tdm", "int7",       V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+	MPP_MODE(43,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd",  V_MV78460)),
+	MPP_MODE(44,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart3", "rxd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs4",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2",   V_MV78230_PLUS)),
+	MPP_MODE(45,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart2", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart3", "txd",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs5",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",    V_MV78230_PLUS)),
+	MPP_MODE(46,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart3", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart1", "rts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs6",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",    V_MV78230_PLUS)),
+	MPP_MODE(47,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "uart3", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "uart1", "cts",      V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x3, "spi", "cs7",        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x4, "ref", "clkout",     V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3",   V_MV78230_PLUS)),
+	MPP_MODE(48,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "tclk", NULL,        V_MV78230_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+	MPP_MODE(49,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "we3",        V_MV78260_PLUS)),
+	MPP_MODE(50,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "we2",        V_MV78260_PLUS)),
+	MPP_MODE(51,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad16",       V_MV78260_PLUS)),
+	MPP_MODE(52,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad17",       V_MV78260_PLUS)),
+	MPP_MODE(53,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad18",       V_MV78260_PLUS)),
+	MPP_MODE(54,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad19",       V_MV78260_PLUS)),
+	MPP_MODE(55,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd",    V_MV78260_PLUS)),
+	MPP_MODE(56,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd",    V_MV78260_PLUS)),
+	MPP_MODE(57,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd",  V_MV78460)),
+	MPP_MODE(58,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad23",       V_MV78260_PLUS)),
+	MPP_MODE(59,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad24",       V_MV78260_PLUS)),
+	MPP_MODE(60,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad25",       V_MV78260_PLUS)),
+	MPP_MODE(61,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad26",       V_MV78260_PLUS)),
+	MPP_MODE(62,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad27",       V_MV78260_PLUS)),
+	MPP_MODE(63,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad28",       V_MV78260_PLUS)),
+	MPP_MODE(64,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad29",       V_MV78260_PLUS)),
+	MPP_MODE(65,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad30",       V_MV78260_PLUS)),
+	MPP_MODE(66,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+		 MPP_VAR_FUNCTION(0x1, "dev", "ad31",       V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+	{
+		.compatible = "marvell,mv78230-pinctrl",
+		.data       = (void *) V_MV78230,
+	},
+	{
+		.compatible = "marvell,mv78260-pinctrl",
+		.data       = (void *) V_MV78260,
+	},
+	{
+		.compatible = "marvell,mv78460-pinctrl",
+		.data       = (void *) V_MV78460,
+	},
+	{ },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+	MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+	MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+	MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 32),
+	MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+	if (!match)
+		return -ENODEV;
+
+	soc->variant = (unsigned) match->data & 0xff;
+
+	switch (soc->variant) {
+	case V_MV78230:
+		soc->controls = mv78230_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78230_mpp_controls[0].npins;
+		soc->gpioranges = mv78230_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+		break;
+	case V_MV78260:
+		soc->controls = mv78260_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78260_mpp_controls[0].npins;
+		soc->gpioranges = mv78260_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+		break;
+	case V_MV78460:
+		soc->controls = mv78460_mpp_controls;
+		soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+		soc->modes = armada_xp_mpp_modes;
+		/* We don't necessarily want the full list of the
+		 * armada_xp_mpp_modes, but only the first 'n' ones
+		 * that are available on this SoC */
+		soc->nmodes = mv78460_mpp_controls[0].npins;
+		soc->gpioranges = mv78460_mpp_gpio_ranges;
+		soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+		break;
+	}
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+	.driver = {
+		.name = "armada-xp-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+	},
+	.probe = armada_xp_pinctrl_probe,
+	.remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni at free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:24 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:24 +0200
Subject: [PATCH v2 3/9] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-4-git-send-email-sebastian.hesselbarth@gmail.com>

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be
  always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines

Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  462 ++++++++++++++++++++
 4 files changed, 746 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 0000000..361bccb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f15eba4..31c0bba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_KIRKWOOD
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d1327df..3006294 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 0000000..23f493a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,462 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282)		\
+	((f6180 << 0) | (f6190 << 1) | (f6192 << 2) |	\
+	 (f6281 << 3) | (f6282 << 4))
+
+enum kirkwood_variant {
+	VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
+	VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
+	VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
+	VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
+	VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
+};
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io2",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1))),
+	MPP_MODE(1,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io3",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "mosi",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(2,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io4",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(3,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io5",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(4,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io6",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0))),
+	MPP_MODE(5,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io7",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(6,
+		MPP_VAR_FUNCTION(0x0, "sysrst", "out",   V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "spi", "mosi",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(7,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "pex", "rsto",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(8,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sda",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(9,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sck",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "evreq",    V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(10,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0X3, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(11,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq",  V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xc, "ptp-2", "trig",   V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(12,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 0, 1)),
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "clk",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "mosi",     V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(13,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "cmd",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "rmclk",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(14,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d0",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "audio-1", "sdi",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(15,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d1",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "cs",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(16,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d2",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "extclk",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(17,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d3",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "sata1", "act",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(18,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io0",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "pex", "clkreq",   V(0, 0, 0, 0, 1))),
+	MPP_MODE(19,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io1",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(20,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d0",       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(1, 0, 0, 0, 0))),
+	MPP_MODE(21,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d1",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(22,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d2",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(23,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d3",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(24,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d4",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(25,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d5",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(26,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d6",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(27,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d7",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(28,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "col",      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d8",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(29,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d9",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(30,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d10",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(31,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d11",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(32,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclko",   V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d12",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(33,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d13",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(34,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txen",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d14",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(35,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxerr",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d15",      V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(36,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(37,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(38,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d18",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(39,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d19",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(40,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d20",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(41,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d21",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(42,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d22",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(43,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d23",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(44,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "clk",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(45,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "e",        V(0, 0, 0, 0, 1))),
+	MPP_MODE(46,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(47,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(48,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d16",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(49,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "ptp", "clk",      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0xa, "pex", "clkreq",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d17",      V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+	MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32,  4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,88f6180-pinctrl",
+					  .data = (void *)VARIANT_MV88F6180 },
+	{ .compatible = "marvell,88f6190-pinctrl",
+					  .data = (void *)VARIANT_MV88F6190 },
+	{ .compatible = "marvell,88f6192-pinctrl",
+					  .data = (void *)VARIANT_MV88F6192 },
+	{ .compatible = "marvell,88f6281-pinctrl",
+					  .data = (void *)VARIANT_MV88F6281 },
+	{ .compatible = "marvell,88f6282-pinctrl",
+					  .data = (void *)VARIANT_MV88F6282 },
+	{ }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+	if (match) {
+		soc->variant = (unsigned)match->data & 0xff;
+		switch (soc->variant) {
+		case VARIANT_MV88F6180:
+			soc->controls = mv88f6180_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f6180_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+			break;
+		case VARIANT_MV88F6190:
+		case VARIANT_MV88F6192:
+			soc->controls = mv88f619x_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f619x_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+			break;
+		case VARIANT_MV88F6281:
+		case VARIANT_MV88F6282:
+			soc->controls = mv88f628x_mpp_controls;
+			soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+			soc->modes = mv88f6xxx_mpp_modes;
+			soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+			soc->gpioranges = mv88f628x_gpio_ranges;
+			soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+			break;
+		}
+		pdev->dev.platform_data = soc;
+	}
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+	.driver = {
+		.name = "kirkwood-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+	},
+	.probe = kirkwood_pinctrl_probe,
+	.remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:27 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:27 +0200
Subject: [PATCH v2 6/9] ARM: mvebu: add pinctrl device in DT for Armada 370/XP
 SoCs
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-7-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

The Armada 370 and XP SoCs have configurable muxing for a certain
number of their pins, controlled through a pinctrl driver.

The 'compatible' property is defined in the SoC-specific .dtsi files,
since the compatible string identifies the number of pins and other
SoC-specific properties.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 16cc82c..54a944a 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -68,6 +68,13 @@
 			compatible = "marvell,armada-addr-decoding-controller";
 			reg = <0xd0020000 0x258>;
 		};
+
+                pinctrl at d0018000 {
+                               reg = <0xd0018000 0x38>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges;
+                };
 	};
 };
 
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:28 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:28 +0200
Subject: [PATCH v2 7/9] ARM: mvebu: Add pinctrl support to Armada XP SoCs
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-8-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.

Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 0000000..69ad287
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78230-pinctrl";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 0000000..0f38fa9
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78260-pinctrl";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 0000000..9e61836
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78460-pinctrl";
+		};
+	};
+ };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:29 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:29 +0200
Subject: [PATCH v2 8/9] ARM: mvebu: Add pinctrl support to Armada 370 SoC
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-9-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada 370 SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-370.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..875fcd8 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -31,5 +31,9 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+                pinctrl at d0018000 {
+			        compatible = "marvell,mv88f6710-pinctrl";
+	        };
 	};
 };
-- 
1.7.10.4



From sebastian.hesselbarth at gmail.com  Wed Aug 22 04:22:30 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Wed, 22 Aug 2012 10:22:30 +0200
Subject: [PATCH v2 9/9] ARM: mvebu: adjust Armada XP evaluation board DTS
In-Reply-To: <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <1345623750-10645-10-git-send-email-sebastian.hesselbarth@gmail.com>

From: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

The Armada XP evaluation board is based on the MV78460 Armava XP
SoC. Now that we have separate .dtsi files for the three different
SoCs of the Armada XP family, use the appropriate one as include for
the Armada XP evaluation board .dts file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Rob Landley <rob at landley.net>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lior Amsalem <alior at marvell.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Ben Dooks <ben.dooks at codethink.co.uk>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d..b1fc728 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
-- 
1.7.10.4



From richard.zhao at freescale.com  Wed Aug 22 04:29:41 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 22 Aug 2012 16:29:41 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <1345619928-15446-2-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
Message-ID: <20120822082940.GJ4011@b20223-02.ap.freescale.net>

On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Add regmap based imx syscon driver.
> This is usually used for access misc bits in registers which does not belong
> to a specific module, for example, IOMUXC GPR and ANATOP.
> With this driver, we provide a standard API for client driver to call to
> access registers which are registered into syscon.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> Currently it's just simply for IMX, however the driver really is not too
> much imx specific.
> If people want, we probably could extend it to support other platforms too.
> ---
>  .../devicetree/bindings/mfd/imx-syscon.txt         |   11 +
>  drivers/mfd/Kconfig                                |    8 +
>  drivers/mfd/Makefile                               |    1 +
>  drivers/mfd/imx-syscon.c                           |  193 ++++++++++++++++++++
>  include/linux/mfd/imx-syscon.h                     |   22 +++
>  5 files changed, 235 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> new file mode 100644
> index 0000000..4a72994
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> @@ -0,0 +1,11 @@
> +* Freescale IMX System Controller Registers R/W driver
> +
> +Required properties:
> +- compatible: Should contain "fsl,imx-syscon".
> +- reg: the register range can be access from imx-syscon
> +
> +Examples:
> +gpr: iomuxc-gpr at 020e0000 {
> +	compatible = "fsl,imx6q-iomuxc", "fsl,imx-syscon";
why is it compatible with iomuxc?

> +	reg = <0x020e0000 0x38>;
> +};
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index b1a1462..20a050e 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -993,6 +993,14 @@ config MFD_ANATOP
>  	  MFD controller. This controller embeds regulator and
>  	  thermal devices for Freescale i.MX platforms.
>  
> +config MFD_IMX_SYSCON
> +        bool "Freescale i.MX System Controller Register R/W Based on Regmap"
> +        depends on ARCH_MXC
> +        select REGMAP_MMIO
> +        help
> +          Select this option to enable access Freescale i.MX system control
> +	  registers like iomuxc gpr and anatop via regmap.
> +
>  config MFD_PALMAS
>  	bool "Support for the TI Palmas series chips"
>  	select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 79dd22d..82c7ee1 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
>  obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
>  obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
>  obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
> +obj-$(CONFIG_MFD_IMX_SYSCON)	+= imx-syscon.o
>  obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
> diff --git a/drivers/mfd/imx-syscon.c b/drivers/mfd/imx-syscon.c
> new file mode 100644
> index 0000000..141b456
> --- /dev/null
> +++ b/drivers/mfd/imx-syscon.c
> @@ -0,0 +1,193 @@
> +/*
> + * Freescale IMX System Control Driver
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro Ltd.
> + *
> + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +static struct platform_driver imx_syscon_driver;
> +
> +struct imx_syscon {
> +	struct device *dev;
> +	void __iomem *base;
> +	struct regmap *regmap;
> +};
> +
> +static int imx_syscon_match(struct device *dev, void *data)
> +{
> +	struct imx_syscon *syscon = dev_get_drvdata(dev);
> +	struct device_node *dn = data;
> +
> +	return (syscon->dev->of_node == dn) ? 1 : 0;
> +}
> +
> +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
For API function, is it better to use struct device rather not np?
 - it won't need to search dev in below code every time it access
   registers.
> +{
> +	struct device *dev;
> +	struct imx_syscon *syscon;
> +	int ret = 0;
> +
> +	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
> +				 imx_syscon_match);
> +	if (!dev)
> +		return -EPROBE_DEFER;
> +
> +	syscon = dev_get_drvdata(dev);
> +	ret = regmap_write(syscon->regmap, reg, val);
> +	if (ret)
> +		dev_err(dev, "failed to write regmap(%s) reg 0x%x (%d)\n",
> +			np->name, reg, ret);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(imx_syscon_write);
> +
> +int imx_syscon_read(struct device_node *np, u32 reg, u32 *val)
> +{
> +	struct device *dev;
> +	struct imx_syscon *syscon;
> +	int ret = 0;
> +
> +	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
> +				 imx_syscon_match);
> +	if (!dev)
> +		return -EPROBE_DEFER;
> +
> +	syscon = dev_get_drvdata(dev);
> +	ret = regmap_read(syscon->regmap, reg, val);
> +	if (ret)
> +		dev_err(dev, "failed to read regmap(%s) reg 0x%x (%d)\n",
> +			np->name, reg, ret);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(imx_syscon_read);
> +
> +int imx_syscon_update_bits(struct device_node *np, u32 reg,
> +					u32 mask, u32 val)
> +{
> +	struct device *dev;
> +	struct imx_syscon *syscon;
> +	int ret = 0;
> +
> +	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
> +				 imx_syscon_match);
> +	if (!dev)
> +		return -EPROBE_DEFER;
> +
> +	syscon = dev_get_drvdata(dev);
> +	ret = regmap_update_bits(syscon->regmap, reg, mask, val);
> +	if (ret)
> +		dev_err(dev, "failed to update regmap(%s) reg 0x%x (%d)\n",
> +			np->name, reg, ret);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(imx_syscon_update_bits);
> +
> +static const struct of_device_id of_imx_syscon_match[] = {
> +	{ .compatible = "fsl,imx-syscon", },
> +	{ },
> +};
> +
> +static struct regmap_config imx_syscon_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
> +
> +static int __devinit imx_syscon_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct imx_syscon *syscon;
> +	struct resource res;
> +	int ret;
> +
> +	if (!np)
> +		return -ENOENT;
> +
> +	syscon = devm_kzalloc(&pdev->dev, sizeof(struct imx_syscon),
> +			    GFP_KERNEL);
> +	if (!syscon)
> +		return -ENOMEM;
> +
> +	syscon->base = of_iomap(np, 0);
no request? use devm_request_and_ioremap?

Thanks
Richard

> +	if (!syscon->base)
> +		return -EADDRNOTAVAIL;
> +
> +	ret = of_address_to_resource(np, 0, &res);
> +	if (ret)
> +		return ret;
> +
> +	imx_syscon_regmap_config.max_register = res.end - res.start - 3;
> +	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
> +					&imx_syscon_regmap_config);
> +	if (IS_ERR(syscon->regmap)) {
> +		dev_err(&pdev->dev, "regmap init failed\n");
> +		return PTR_ERR(syscon->regmap);
> +	}
> +
> +	regcache_cache_only(syscon->regmap, false);
> +
> +	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
> +		res.start, res.end);
> +
> +	syscon->dev = &pdev->dev;
> +	platform_set_drvdata(pdev, syscon);
> +
> +	return 0;
> +}
> +
> +static int __devexit imx_syscon_remove(struct platform_device *pdev)
> +{
> +	struct imx_syscon *syscon;
> +
> +	syscon = platform_get_drvdata(pdev);
> +	iounmap(syscon->base);
> +	platform_set_drvdata(pdev, NULL);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver imx_syscon_driver = {
> +	.driver = {
> +		.name = "imx-syscon",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_imx_syscon_match,
> +	},
> +	.probe		= imx_syscon_probe,
> +	.remove		= imx_syscon_remove,
> +};
> +
> +static int __init imx_syscon_init(void)
> +{
> +	return platform_driver_register(&imx_syscon_driver);
> +}
> +postcore_initcall(imx_syscon_init);
> +
> +static void __exit anatop_exit(void)
> +{
> +	platform_driver_unregister(&imx_syscon_driver);
> +}
> +module_exit(anatop_exit);
> +
> +MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
> +MODULE_DESCRIPTION("Freescale IMX System Control driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/imx-syscon.h b/include/linux/mfd/imx-syscon.h
> new file mode 100644
> index 0000000..be8b6db
> --- /dev/null
> +++ b/include/linux/mfd/imx-syscon.h
> @@ -0,0 +1,22 @@
> +/*
> + * Freescale IMX System Control Driver
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro Ltd.
> + *
> + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __LINUX_MFD_IMX_SYSCON_H__
> +#define __LINUX_MFD_IMX_SYSCON_H__
> +
> +extern int imx_syscon_write(struct device_node *np, u32 reg, u32 val);
> +extern int imx_syscon_read(struct device_node *np, u32 reg, u32 *val);
> +extern int imx_syscon_update_bits(struct device_node *np, u32 reg,
> +					u32 mask, u32 val);
> +#endif /* __LINUX_MFD_IMX_SYSCON_H__ */
> -- 
> 1.7.0.4
> 



From linux at arm.linux.org.uk  Wed Aug 22 04:32:23 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 Aug 2012 09:32:23 +0100
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <5033891D.90509@calxeda.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <20120821122753.GU18957@n2100.arm.linux.org.uk> <5033891D.90509@calxeda.com>
Message-ID: <20120822083223.GW18957@n2100.arm.linux.org.uk>

On Tue, Aug 21, 2012 at 08:11:57AM -0500, Rob Herring wrote:
> On 08/21/2012 07:27 AM, Russell King - ARM Linux wrote:
> > So now, you're not dealing with inventing a whole load of names for clocks
> > on a platform, instead what you're doing is describing _where_ the clock
> > comes from in the system for a particular device by device node and index
> > into it - just like we do for interrupts.
> 
> That is what we're doing. The names are optional for DT, but happen to
> be required for struct clk now. If we don't put something in DT, then
> the clock names will have to be something generic like ccm-1..ccm-185.

And that's what's wrong.  Clocks themselves should _not_ be required to
be named.

If you use purely "producer node + index" then you don't need to name a
whole bunch of clocks, and you don't need to have an array of clock names
in the DT file.  This also gets rid of the time consuming strcmp against
every clock, which has already been raised as a problem with the existing
clk_get().

And, like it or not, the way they're being describing them in the DT file
at the top of this sub-thread, the matching _is_ done only by producer
name, which is TOTALLY the wrong way to go about this (that's how folk
tried to use the connection ID in the clk API and IT DOESN'T WORK for
reusable drivers.)


From kishon at ti.com  Wed Aug 22 04:40:03 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 22 Aug 2012 14:10:03 +0530
Subject: [RESEND PATCH v4 2/2] arm/dts: omap4: Add ocp2scp data
In-Reply-To: <1345624803-16379-1-git-send-email-kishon@ti.com>
References: <1345624803-16379-1-git-send-email-kishon@ti.com>
Message-ID: <1345624803-16379-3-git-send-email-kishon@ti.com>

Add ocp2scp data node in omap4 device tree file.

Acked-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..8a780b2 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,13 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
 		};
+
+		ocp2scp {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			ti,hwmods = "ocp2scp_usb_phy";
+		};
 	};
 };
-- 
1.7.9.5



From kishon at ti.com  Wed Aug 22 04:40:02 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 22 Aug 2012 14:10:02 +0530
Subject: [RESEND PATCH v4 1/2] drivers: bus: add a new driver for omap-ocp2scp
In-Reply-To: <1345624803-16379-1-git-send-email-kishon@ti.com>
References: <1345624803-16379-1-git-send-email-kishon@ti.com>
Message-ID: <1345624803-16379-2-git-send-email-kishon@ti.com>

Adds a new driver *omap-ocp2scp*. This driver takes the responsibility of
creating all the devices that is connected to OCP2SCP. In the case of OMAP4,
USB2PHY is connected to ocp2scp.

This also includes device tree support for ocp2scp driver and
the documentation with device tree binding information is updated.

Acked-by: Felipe Balbi <balbi at ti.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
---
 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 6 files changed, 122 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
new file mode 100644
index 0000000..d2fe064
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -0,0 +1,10 @@
+* OMAP OCP2SCP - ocp interface to scp interface
+
+properties:
+- compatible : Should be "ti,omap-ocp2scp"
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ranges : the child address space are mapped 1:1 onto the parent address space
+- ti,hwmods : must be "ocp2scp_usb_phy"
+
+Sub-nodes:
+All the devices connected to ocp2scp are described using sub-node to ocp2scp
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ece958d..324e958 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -2,6 +2,8 @@ menu "Device Drivers"
 
 source "drivers/base/Kconfig"
 
+source "drivers/bus/Kconfig"
+
 source "drivers/connector/Kconfig"
 
 source "drivers/mtd/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 5b42184..f8cdeeb 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y				+= bus/
+
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
new file mode 100644
index 0000000..6270415
--- /dev/null
+++ b/drivers/bus/Kconfig
@@ -0,0 +1,15 @@
+#
+# Bus Devices
+#
+
+menu "Bus devices"
+
+config OMAP_OCP2SCP
+	tristate "OMAP OCP2SCP DRIVER"
+	help
+	  Driver to enable ocp2scp module which transforms ocp interface
+	  protocol to scp protocol. In OMAP4, USB PHY is connected via
+	  OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
+	  OCP2SCP.
+
+endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
new file mode 100644
index 0000000..0ec50bc
--- /dev/null
+++ b/drivers/bus/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the bus drivers.
+#
+
+obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
new file mode 100644
index 0000000..881d5bb
--- /dev/null
+++ b/drivers/bus/omap-ocp2scp.c
@@ -0,0 +1,88 @@
+/*
+ * omap-ocp2scp.c - transform ocp interface protocol to scp protocol
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author: Kishon Vijay Abraham I <kishon at ti.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+static int ocp2scp_remove_devices(struct device *dev, void *c)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	platform_device_unregister(pdev);
+
+	return 0;
+}
+
+static int __devinit omap_ocp2scp_probe(struct platform_device *pdev)
+{
+	int			ret;
+	struct device_node	*np = pdev->dev.of_node;
+
+	if (np) {
+		ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to add resources for ocp2scp child\n");
+			goto err0;
+		}
+	}
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+
+err0:
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return ret;
+}
+
+static int __devexit omap_ocp2scp_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+	device_for_each_child(&pdev->dev, NULL, ocp2scp_remove_devices);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id omap_ocp2scp_id_table[] = {
+	{ .compatible = "ti,omap-ocp2scp" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
+static struct platform_driver omap_ocp2scp_driver = {
+	.probe		= omap_ocp2scp_probe,
+	.remove		= __devexit_p(omap_ocp2scp_remove),
+	.driver		= {
+		.name	= "omap-ocp2scp",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),
+	},
+};
+
+module_platform_driver(omap_ocp2scp_driver);
+
+MODULE_ALIAS("platform: omap-ocp2scp");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_DESCRIPTION("OMAP OCP2SCP driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From kishon at ti.com  Wed Aug 22 04:40:01 2012
From: kishon at ti.com (Kishon Vijay Abraham I)
Date: Wed, 22 Aug 2012 14:10:01 +0530
Subject: [RESEND PATCH v4 0/2] omap: add ocp2scp as a bus driver
Message-ID: <1345624803-16379-1-git-send-email-kishon@ti.com>

This patch series has been lying here for long. If no one has any
comments on this patch series, can someone pick it up?

This patch series is done as a preparatory step for adding phy drivers
for dwc3 and musb.

This series adds a new driver for ocp2scp (only dt) to which phy
drivers are connected.

Since currently there is no generic way to create a child device along
with doing a pm_runtime_enable (the exact requirement for ocp2scp), I'm
creating a separate driver for ocp2scp.

Changes from v3:
No functional changes. Fixed few comments on filling *module* details.

Changes from v2:
Fixed Felipe's comments to avoid using arch_initcall and make dependent
drivers return -EPROBE_DEFER case this isn't ready yet.

Changes from v1:
Fixed Sergei's comments to remove the address in the node name of ocp2scp
since the ocp2scp node doesn't have a reg property.

Changes from [RFC PATCH v2 0/2] omap: add ocp2scp as a misc driver:
Created a new folder drivers/bus and moved ocp2scp driver from misc to
drivers/bus.

This patch was developed and tested on
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git

Kishon Vijay Abraham I (2):
  drivers: bus: add a new driver for omap-ocp2scp
  arm/dts: omap4: Add ocp2scp data

 .../devicetree/bindings/bus/omap-ocp2scp.txt       |   10 +++
 arch/arm/boot/dts/omap4.dtsi                       |    8 ++
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    2 +
 drivers/bus/Kconfig                                |   15 ++++
 drivers/bus/Makefile                               |    5 ++
 drivers/bus/omap-ocp2scp.c                         |   88 ++++++++++++++++++++
 7 files changed, 130 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
 create mode 100644 drivers/bus/Kconfig
 create mode 100644 drivers/bus/Makefile
 create mode 100644 drivers/bus/omap-ocp2scp.c

-- 
1.7.9.5



From linus.walleij at stericsson.com  Wed Aug 22 04:43:48 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:43:48 +0200
Subject: [PATCH 1/7] ux500: GIC: MASK_ON_SUSPEND
Message-ID: <1345625028-5608-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7..84d7f7e 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -51,6 +51,8 @@ void __init ux500_init_irq(void)
 	void __iomem *dist_base;
 	void __iomem *cpu_base;
 
+	gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
+
 	if (cpu_is_u8500_family()) {
 		dist_base = __io_address(U8500_GIC_DIST_BASE);
 		cpu_base = __io_address(U8500_GIC_CPU_BASE);
-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:43:06 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:43:06 +0200
Subject: [PATCH 0/7] Ux500 and MASK_ON_SUSPEND
Message-ID: <1345624986-5557-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

We have discovered transient IRQs when going to suspend on the
Ux500 platform. This patch series hits all sources by marking
the applicable IRQchips with MASK_ON_SUSPEND.

I don't know if this is a common problem or seen in other
platforms so comments are welcome.

Else I request that the patches be merged into respective
subtree, I will take care of the ux500, gpio and pinctrl
patches myself, while Sam gets to merge all the MFD stuff.

Etienne Carriere (7):
  ux500: GIC: MASK_ON_SUSPEND
  mfd/ab8500: MASK_ON_SUSPEND
  gpio/ab8500: MASK_ON_SUSPEND
  mfd/db8500-prcmu: MASK_ON_SUSPEND
  pinctrl/nomdik: MASK_ON_SUSPEND
  mfd/stmpe: MASK_ON_SUSPEND
  mfd/tc3589x: MASK_ON_SUSPEND

 arch/arm/mach-ux500/cpu.c         | 2 ++
 drivers/gpio/gpio-ab8500.c        | 1 +
 drivers/gpio/gpio-stmpe.c         | 1 +
 drivers/gpio/gpio-tc3589x.c       | 1 +
 drivers/mfd/ab8500-core.c         | 1 +
 drivers/mfd/db8500-prcmu.c        | 1 +
 drivers/mfd/stmpe.c               | 1 +
 drivers/pinctrl/pinctrl-nomadik.c | 1 +
 8 files changed, 9 insertions(+)

-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:44:09 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:44:09 +0200
Subject: [PATCH 4/7] mfd/db8500-prcmu: MASK_ON_SUSPEND
Message-ID: <1345625049-5714-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/mfd/db8500-prcmu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 7040a00..25d2e9d 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -2615,6 +2615,7 @@ static struct irq_chip prcmu_irq_chip = {
 	.irq_ack	= noop,
 	.irq_mask	= prcmu_irq_mask,
 	.irq_unmask	= prcmu_irq_unmask,
+	.flags		= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static char *fw_project_name(u8 project)
-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:44:02 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:44:02 +0200
Subject: [PATCH 3/7] gpio/ab8500: MASK_ON_SUSPEND
Message-ID: <1345625042-5678-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/gpio-ab8500.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-ab8500.c b/drivers/gpio/gpio-ab8500.c
index 050c05d..3d2cd66 100644
--- a/drivers/gpio/gpio-ab8500.c
+++ b/drivers/gpio/gpio-ab8500.c
@@ -203,6 +203,7 @@ static struct gpio_chip ab8500gpio_chip = {
 	.direction_output	= ab8500_gpio_direction_output,
 	.set			= ab8500_gpio_set,
 	.to_irq			= ab8500_gpio_to_irq,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static unsigned int irq_to_rising(unsigned int irq)
-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:43:56 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:43:56 +0200
Subject: [PATCH 2/7] mfd/ab8500: MASK_ON_SUSPEND
Message-ID: <1345625036-5643-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/mfd/ab8500-core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 626b4ec..b25a0b0 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -386,6 +386,7 @@ static struct irq_chip ab8500_irq_chip = {
 	.irq_mask		= ab8500_irq_mask,
 	.irq_disable		= ab8500_irq_mask,
 	.irq_unmask		= ab8500_irq_unmask,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:44:23 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:44:23 +0200
Subject: [PATCH 6/7] mfd/stmpe: MASK_ON_SUSPEND
Message-ID: <1345625063-5784-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/gpio-stmpe.c | 1 +
 drivers/mfd/stmpe.c       | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index dce3472..2195abc 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -223,6 +223,7 @@ static struct irq_chip stmpe_gpio_irq_chip = {
 	.irq_mask		= stmpe_gpio_irq_mask,
 	.irq_unmask		= stmpe_gpio_irq_unmask,
 	.irq_set_type		= stmpe_gpio_irq_set_type,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
index 2dd8d49..846b9c8 100644
--- a/drivers/mfd/stmpe.c
+++ b/drivers/mfd/stmpe.c
@@ -851,6 +851,7 @@ static struct irq_chip stmpe_irq_chip = {
 	.irq_bus_sync_unlock	= stmpe_irq_sync_unlock,
 	.irq_mask		= stmpe_irq_mask,
 	.irq_unmask		= stmpe_irq_unmask,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static int __devinit stmpe_irq_init(struct stmpe *stmpe)
-- 
1.7.11.3



From tomi.valkeinen at ti.com  Wed Aug 22 04:44:27 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 22 Aug 2012 11:44:27 +0300
Subject: [PATCH V6 0/6] OMAPDSS: Cleanup cpu_is checks
In-Reply-To: <cover.1345616887.git.cmahapatra@ti.com>
References: <cover.1345468541.git.cmahapatra@ti.com>
 <cover.1345616887.git.cmahapatra@ti.com>
Message-ID: <1345625067.3036.19.camel@deskari>

On Wed, 2012-08-22 at 12:06 +0530, Chandrabhanu Mahapatra wrote:
> Hi everyone,
> this patch series aims at cleaning up of DSS of cpu_is checks thereby making it
> more generic.
> 
> The 1st patch cleans up cpu_is checks from DISPC code.
> The 2nd patch removes unused functions from DSS code.
> The 3rd patch cleans up cpu_is checks from DSS code.
> The 4th patch disables VENC support on OMAP4.
> The 5th patch removes cpu_is checks from VENC code.
> The 6th patch removes cpu_is checks from DPI code and replaces it with a
> dss feature.

Thanks, looks good. I'll apply this to omapdss tree.

 Tomi

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From linus.walleij at stericsson.com  Wed Aug 22 04:44:30 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:44:30 +0200
Subject: [PATCH 7/7] mfd/tc3589x: MASK_ON_SUSPEND
Message-ID: <1345625070-5820-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/gpio-tc3589x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c
index 2a82e89..6e48c50 100644
--- a/drivers/gpio/gpio-tc3589x.c
+++ b/drivers/gpio/gpio-tc3589x.c
@@ -199,6 +199,7 @@ static struct irq_chip tc3589x_gpio_irq_chip = {
 	.irq_mask		= tc3589x_gpio_irq_mask,
 	.irq_unmask		= tc3589x_gpio_irq_unmask,
 	.irq_set_type		= tc3589x_gpio_irq_set_type,
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
-- 
1.7.11.3



From linus.walleij at stericsson.com  Wed Aug 22 04:44:16 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 10:44:16 +0200
Subject: [PATCH 5/7] pinctrl/nomdik: MASK_ON_SUSPEND
Message-ID: <1345625056-5749-1-git-send-email-linus.walleij@stericsson.com>

From: Etienne Carriere <etienne.carriere at stericsson.com>

ux500 machines performs pins (GPIO) reconfiguration when entering
in the suspended mode. This reconfiguration aims at reaching an ultra
low power HW configuration.

Due to this HW reconfiguration, some HW devices can change of HW state
and have their output signals at level that could generate IRQs.

If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt
disable feature from the generic irq layer), effective interrupts reach
the system only because the system attempt to enter the suspended mode.

To prevent such IRQs to trig, all irq chips embedded in ux500 platform
should enable their IRQCHIP_MASK_ON_SUSPEND flag.

Signed-off-by: Etienne Carriere <etienne.carriere at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinctrl-nomadik.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index ec6ac50..41f1a3d 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
 	.irq_set_wake	= nmk_gpio_irq_set_wake,
 	.irq_startup	= nmk_gpio_irq_startup,
 	.irq_shutdown	= nmk_gpio_irq_shutdown,
+	.flags		= IRQCHIP_MASK_ON_SUSPEND,
 };
 
 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
-- 
1.7.11.3



From richard.zhao at freescale.com  Wed Aug 22 04:52:36 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 22 Aug 2012 16:52:36 +0800
Subject: [PATCH 6/7] ARM: dts: imx6q: add simple-bus compatible string
 for anatop
In-Reply-To: <1345619928-15446-7-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-7-git-send-email-b29396@freescale.com>
Message-ID: <20120822085236.GK4011@b20223-02.ap.freescale.net>

On Wed, Aug 22, 2012 at 03:18:47PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Originally the anatop regulator devices are populated by mfd anatop driver.
> Since mfd anatop driver will be deleted later, we change to populate the
> regulator devices by devicetree automatically.
> This will cause some warning messages as follows during boot due to device
> recreation: "vdd1p1: Failed to create debugfs directory"
> But it does not break any function.
> Later, we will remove mfd anatop driver which can get rid of this
> error message.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 7076be0..426f735 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -379,7 +379,7 @@
>  			};
>  
>  			anatop: anatop at 020c8000 {
> -				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon";
> +				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon", "simple-bus";
To prevent bisect break, it should merge with patch #4.
It's really strange to use simple-bus, because it's not a bus.
I like more the way how anatop driver handle it. Anatop driver populate
devices in its code.

Thanks
Richard
>  				reg = <0x020c8000 0x1000>;
>  				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
>  
> -- 
> 1.7.0.4
> 



From linus.walleij at stericsson.com  Wed Aug 22 05:12:28 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 22 Aug 2012 11:12:28 +0200
Subject: [PATCH] ARM: ux500: implement set_wake() callback for the GIC
Message-ID: <1345626748-29057-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The Ux500 will be able to wake up on any IRQ, so implement a
.set_wake() callback that just returns 0 instead of the default
in common/gic.c which returns an error if you try to set
wakeup on the GIC.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/cpu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7..24598e2 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -46,11 +46,18 @@ static const struct of_device_id ux500_dt_irq_match[] = {
 	{},
 };
 
+static int ux500_gic_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+	return 0;
+}
+
 void __init ux500_init_irq(void)
 {
 	void __iomem *dist_base;
 	void __iomem *cpu_base;
 
+	gic_arch_extn.irq_set_wake = ux500_gic_irq_set_wake;
+
 	if (cpu_is_u8500_family()) {
 		dist_base = __io_address(U8500_GIC_DIST_BASE);
 		cpu_base = __io_address(U8500_GIC_CPU_BASE);
-- 
1.7.11.3



From linus.walleij at linaro.org  Wed Aug 22 05:21:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 11:21:32 +0200
Subject: [rtc-linux] [PATCHv3 8/9] arm: vt8500: gpio: Devicetree support
 for arch-vt8500
In-Reply-To: <1345582058-2291-9-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-9-git-send-email-linux@prisktech.co.nz>
Message-ID: <CACRpkdZnQyLSRQ6cRpFBurAv2cv44einGAsT86FLCqsj1euDMA@mail.gmail.com>

On Tue, Aug 21, 2012 at 10:47 PM, Tony Prisk <linux at prisktech.co.nz> wrote:

> Converted the existing arch-vt8500 gpio to a platform_device.
> Added support for WM8505 and WM8650 GPIO controllers.
(...)
> +       unsigned val;

I asked about the datatype for this "val", it sure isn't "unsigned".

I suspected the registers were only 8bit and so it should be u8.
But atleast use u32 if you must use all these bits.

(...)
> +       val = readl(vt8500_chip->base + vt8500_chip->regs->en);
> +       val |= BIT(offset);
> +       writel(val, vt8500_chip->base + vt8500_chip->regs->en);

BTW: have you considered [readl|writel]_relaxed?

Yours,
Linus Walleij


From gururaja.hebbar at ti.com  Wed Aug 22 05:26:36 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 09:26:36 +0000
Subject: [PATCH 5/5] ASoC: tlv320aic3x: Add device tree bindings
In-Reply-To: <20120817224512.GL18871@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-6-git-send-email-gururaja.hebbar@ti.com>
 <20120817224512.GL18871@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA64BA4@DBDE01.ent.ti.com>

On Sat, Aug 18, 2012 at 04:15:13, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 06:12:05PM +0530, Hebbar, Gururaja wrote:
> 
> > +- gpio-reset - <int> -  gpio pin number used for codec reset
> 
> This should be a standard DT GPIO reference by phandle like:
> 
> 	gpio = <&gpio1 16 0>;

I will correct in V2

> 
> There's quite a few examples in tree.
> 
> Otherwise this looks good.
> 

Thanks for all the reviews.

Regards, 
Gururaja


From shawn.guo at linaro.org  Wed Aug 22 05:27:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 17:27:29 +0800
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <20120822083223.GW18957@n2100.arm.linux.org.uk>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <20120821122753.GU18957@n2100.arm.linux.org.uk>
 <5033891D.90509@calxeda.com>
 <20120822083223.GW18957@n2100.arm.linux.org.uk>
Message-ID: <20120822092726.GV24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 09:32:23AM +0100, Russell King - ARM Linux wrote:
> On Tue, Aug 21, 2012 at 08:11:57AM -0500, Rob Herring wrote:
> > On 08/21/2012 07:27 AM, Russell King - ARM Linux wrote:
> > > So now, you're not dealing with inventing a whole load of names for clocks
> > > on a platform, instead what you're doing is describing _where_ the clock
> > > comes from in the system for a particular device by device node and index
> > > into it - just like we do for interrupts.
> > 
> > That is what we're doing. The names are optional for DT, but happen to
> > be required for struct clk now. If we don't put something in DT, then
> > the clock names will have to be something generic like ccm-1..ccm-185.
> 
> And that's what's wrong.  Clocks themselves should _not_ be required to
> be named.
> 
> If you use purely "producer node + index" then you don't need to name a
> whole bunch of clocks, and you don't need to have an array of clock names
> in the DT file.  This also gets rid of the time consuming strcmp against
> every clock, which has already been raised as a problem with the existing
> clk_get().
> 
Ok, if I got your point correctly, it's about amending the following
changes, and then we can get rid of that big clock-output-names list
from dts.

Regards,
Shawn

--8<---

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 433c683..d52f3f4 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -387,7 +387,7 @@ int __init mx6q_clocks_init(void)
                        pr_err("i.MX6q clk %d: register failed with %ld\n",
                                i, PTR_ERR(clk[i]));

-       of_clk_add_provider(np, of_clk_src_onecell_get, NULL);
+       of_clk_add_provider(np, of_clk_src_onecell_get, clk);

        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 06bc0b5..a010ed6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1584,16 +1584,10 @@ EXPORT_SYMBOL_GPL(of_clk_src_simple_get);

 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
 {
-       const char *clk_name;
+       struct clk **clks = data;
        int idx = clkspec->args[0];
-       int ret;
-
-       ret = of_property_read_string_index(clkspec->np, "clock-output-names",
-                                           idx, &clk_name);
-       if (ret < 0)
-               return ERR_PTR(ret);

-       return __clk_lookup(clk_name);
+       return clks[idx];
 }
 EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);


From linus.walleij at linaro.org  Wed Aug 22 05:36:51 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 11:36:51 +0200
Subject: [PATCH] mfd: ab8500: Make ab8500_irq_get_virq() static
In-Reply-To: <1345460017-404-1-git-send-email-lee.jones@linaro.org>
References: <1345460017-404-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZu5o9mzY7Foktu0cL5pp2o+CRfvkmGzQj+TQKAL8QfYA@mail.gmail.com>

On Mon, Aug 20, 2012 at 12:53 PM, Lee Jones <lee.jones at linaro.org> wrote:

> MFD core now takes care of  HWIRQ <-> VIRQ mapping, so the helper
> ab8500_irq_get_virq() is no longer used by ab8500 subordinate devices
> to obtain a Linux wide Virtual IRQ. The AB8500 IRQ controller still
> uses it internally though, so we'll just hide it from the rest of the
> world by making it static instead.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Luv this patch, well done!
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From kgene.kim at samsung.com  Wed Aug 22 05:38:36 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 22 Aug 2012 18:38:36 +0900
Subject: [PATCH 14/14] drivers/spi/spi-s3c24xx.c: fix error return code
In-Reply-To: <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>
References: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1b3201cd8049$e753f720$b5fbe560$%kim@samsung.com>

Julia Lawall wrote:
> 
> From: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> Initialize return variable before exiting on an error path.
> 
> A simplified version of the semantic match that finds this problem is as
> follows: (http://coccinelle.lip6.fr/)
> 
> // <smpl>
> (
> if at p1 (\(ret < 0\|ret != 0\))
>  { ... return ret; }
> |
> ret at p1 = 0
> )
> ... when != ret = e1
>     when != &ret
> *if(...)
> {
>   ... when != ret = e2
>       when forall
>  return ret;
> }
> 
> // </smpl>
> 
> Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>
> 
Acked-by: Kukjin Kim <kgene.kim at samsung.com>

(Cc'ed Mark Brown who is handling spi for a moment)

> ---
> Perhaps -EINVAL is not the right value in this case.
> 
Well, if (pin_cs < 0) is true, it is really invalid value. So I think, it
makes sense :-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

>  drivers/spi/spi-s3c24xx.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
> index 8ee7d79..a2a080b 100644
> --- a/drivers/spi/spi-s3c24xx.c
> +++ b/drivers/spi/spi-s3c24xx.c
> @@ -611,6 +611,7 @@ static int __devinit s3c24xx_spi_probe(struct
> platform_device *pdev)
>  	if (!pdata->set_cs) {
>  		if (pdata->pin_cs < 0) {
>  			dev_err(&pdev->dev, "No chipselect pin\n");
> +			err = -EINVAL;
>  			goto err_register;
>  		}
> 



From kgene.kim at samsung.com  Wed Aug 22 05:38:54 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 22 Aug 2012 18:38:54 +0900
Subject: [PATCH] ARM: SAMSUNG: use spin_lock_irqsave() in clk_set_parent
In-Reply-To: <1345058187-18843-1-git-send-email-msb@chromium.org>
References: <1345058187-18843-1-git-send-email-msb@chromium.org>
Message-ID: <1b3701cd8049$f20e16f0$d62a44d0$%kim@samsung.com>

Mandeep Singh Baines wrote:
> 
> From 0cdf3aff, "ARM: SAMSUNG: use spin_lock_irqsave() in
> clk_{enable,disable}":
> 
>   The clk_enable()and clk_disable() can be used process and ISR either.
>   And actually it is used for real product and other platforms use it
>   now. So spin_lock_irqsave() should be used instead.
> 
> We need to make a similar change in clk_set_parent(). Otherwise,
> you can potentially get spinlock recursion:
> 
> BUG: spinlock recursion on CPU#0, kinteractive/68
>  lock: 807832a8, .magic: dead4ead, .owner: kinteractive/68, .owner_cpu: 0
> [<80015f54>] (unwind_backtrace+0x0/0x128) from [<804f2914>]
> (dump_stack+0x20/0x24)
> [<804f2914>] (dump_stack+0x20/0x24) from [<804f57b8>]
(spin_dump+0x80/0x94)
> [<804f57b8>] (spin_dump+0x80/0x94) from [<804f57f8>] (spin_bug+0x2c/0x30)
> [<804f57f8>] (spin_bug+0x2c/0x30) from [<80222730>]
> (do_raw_spin_lock+0x54/0x150)
> [<80222730>] (do_raw_spin_lock+0x54/0x150) from [<804f96ec>]
> (_raw_spin_lock_irqsave+0x20/0x28)
> [<804f96ec>] (_raw_spin_lock_irqsave+0x20/0x28) from [<80022ea4>]
> (clk_enable+0x3c/0x84)
> [<80022ea4>] (clk_enable+0x3c/0x84) from [<8038336c>]
> (s5p_mfc_clock_on+0x60/0x74)
> [<8038336c>] (s5p_mfc_clock_on+0x60/0x74) from [<8038645c>]
> (s5p_mfc_read_info+0x20/0x38)
> [<8038645c>] (s5p_mfc_read_info+0x20/0x38) from [<8037ca3c>]
> (s5p_mfc_handle_frame+0x2e4/0x4bc)
> [<8037ca3c>] (s5p_mfc_handle_frame+0x2e4/0x4bc) from [<8037d420>]
> (s5p_mfc_irq+0x1ec/0x6cc)
> [<8037d420>] (s5p_mfc_irq+0x1ec/0x6cc) from [<8007fc74>]
> (handle_irq_event_percpu+0x8c/0x244)
> [<8007fc74>] (handle_irq_event_percpu+0x8c/0x244) from [<8007fe78>]
> (handle_irq_event+0x4c/0x6c)
> [<8007fe78>] (handle_irq_event+0x4c/0x6c) from [<80082dd8>]
> (handle_fasteoi_irq+0xe4/0x150)
> [<80082dd8>] (handle_fasteoi_irq+0xe4/0x150) from [<8007f424>]
> (generic_handle_irq+0x3c/0x50)
> [<8007f424>] (generic_handle_irq+0x3c/0x50) from [<8000f7c4>]
> (handle_IRQ+0x88/0xc8)
> [<8000f7c4>] (handle_IRQ+0x88/0xc8) from [<80008564>]
> (gic_handle_irq+0x44/0x68)
> [<80008564>] (gic_handle_irq+0x44/0x68) from [<8000e400>]
> (__irq_svc+0x40/0x60)
> Exception stack(0xef3cbe68 to 0xef3cbeb0)
> [<8000e400>] (__irq_svc+0x40/0x60) from [<80022cfc>]
> (clk_set_parent+0x30/0x74)
> [<80022cfc>] (clk_set_parent+0x30/0x74) from [<803ac7f8>]
> (set_apll.isra.0+0x28/0xb0)
> [<803ac7f8>] (set_apll.isra.0+0x28/0xb0) from [<803ac8e4>]
> (exynos5250_set_frequency+0x64/0xb8)
> [<803ac8e4>] (exynos5250_set_frequency+0x64/0xb8) from [<803ac280>]
> (exynos_target+0x1b0/0x220)
> [<803ac280>] (exynos_target+0x1b0/0x220) from [<803a4a0c>]
> (__cpufreq_driver_target+0xb0/0xd4)
> [<803a4a0c>] (__cpufreq_driver_target+0xb0/0xd4) from [<803aab80>]
> (cpufreq_interactive_updown_task+0x214/0x264)
> [<803aab80>] (cpufreq_interactive_updown_task+0x214/0x264) from
> [<80047d04>] (kthread+0x9c/0xa8)
> [<80047d04>] (kthread+0x9c/0xa8) from [<8000fa48>]
> (kernel_thread_exit+0x0/0x8)
> 
> Signed-off-by: Mandeep Singh Baines <msb at chromium.org>
> Suggested-by: Sunil Mazhavanchery <sunilm at samsung.com>
> CC: linux-arm-kernel at lists.infradead.org
> CC: linux-samsung-soc at vger.kernel.org
> CC: Ben Dooks <ben-linux at fluff.org>
> CC: Kukjin Kim <kgene.kim at samsung.com>
> CC: Russell King <linux at arm.linux.org.uk>
> CC: Minho Ban <mhban at samsung.com>
> CC: Jaecheol Lee <jc.lee at samsung.com>
> CC: Sunyoung Kang <sy0816.kang at samsung.com>
> CC: Kukjin Kim <kgene.kim at samsung.com>
> CC: Olof Johansson <olofj at chromium.org>
> ---
>  arch/arm/plat-samsung/clock.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
> index 65c5eca..80eacca 100644
> --- a/arch/arm/plat-samsung/clock.c
> +++ b/arch/arm/plat-samsung/clock.c
> @@ -173,17 +173,18 @@ struct clk *clk_get_parent(struct clk *clk)
> 
>  int clk_set_parent(struct clk *clk, struct clk *parent)
>  {
> +	unsigned long flags;
>  	int ret = 0;
> 
>  	if (IS_ERR(clk))
>  		return -EINVAL;
> 
> -	spin_lock(&clocks_lock);
> +	spin_lock_irqsave(&clocks_lock, flags);
> 
>  	if (clk->ops && clk->ops->set_parent)
>  		ret = (clk->ops->set_parent)(clk, parent);
> 
> -	spin_unlock(&clocks_lock);
> +	spin_unlock_irqrestore(&clocks_lock, flags);
> 
>  	return ret;
>  }
> --
> 1.7.7.3

Yup, right. Applied.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From linux at arm.linux.org.uk  Wed Aug 22 05:53:02 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 Aug 2012 10:53:02 +0100
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <50348030.9080200@codeaurora.org>
References: <50339AF6.1060601@codeaurora.org>
 <5033C428.2050607@codeaurora.org> <50348030.9080200@codeaurora.org>
Message-ID: <20120822095302.GX18957@n2100.arm.linux.org.uk>

On Wed, Aug 22, 2012 at 12:16:08PM +0530, Trilok Soni wrote:
> Thanks for the patch, but how about just checking pmd_none on such  
> addresses and since there won't be any mapping created for such gaps? We  
> need to check if this is fine for all, since I remember that Nico
> added these functions for the OMAP boot issue I guess.

A better solution would be as below - this requires no changes to the
existing ioremap code, we just mark these differently.

diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 2e8a1ef..87fa3f2 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 /* permanent static mappings from iotable_init() */
 #define VM_ARM_STATIC_MAPPING	0x40000000
 
+/* empty mapping */
+#define VM_ARM_EMPTY_MAPPING	0x20000000
+
 /* mapping type (attributes) for permanent static mappings */
 #define VM_ARM_MTYPE(mt)		((mt) << 20)
 #define VM_ARM_MTYPE_MASK	(0x1f << 20)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d..da90ef1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -813,7 +813,7 @@ static void __init pmd_empty_section_gap(unsigned long addr)
 	vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
 	vm->addr = (void *)addr;
 	vm->size = SECTION_SIZE;
-	vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
+	vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 	vm->caller = pmd_empty_section_gap;
 	vm_area_add_early(vm);
 }
@@ -826,7 +826,7 @@ static void __init fill_pmd_gaps(void)
 
 	/* we're still single threaded hence no lock needed here */
 	for (vm = vmlist; vm; vm = vm->next) {
-		if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+		if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))
 			continue;
 		addr = (unsigned long)vm->addr;
 		if (addr < next)



From hdoyu at nvidia.com  Wed Aug 22 06:09:59 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 13:09:59 +0300
Subject: [PATCHv6 2/2] ARM: dma-mapping: remove custom consistent dma
 region
In-Reply-To: <00c301cd7fad$cfc7f3f0$6f57dbd0$%szyprowski@samsung.com>
References: <1343636899-19508-1-git-send-email-m.szyprowski@samsung.com>
 <1343636899-19508-3-git-send-email-m.szyprowski@samsung.com>
 <20120821142235.97984abc9ad98d01015a3338@nvidia.com>
 <20120821.151521.702882672715065253.hdoyu@nvidia.com>
 <00c301cd7fad$cfc7f3f0$6f57dbd0$%szyprowski@samsung.com>
Message-ID: <20120822130959.183933b51c45c4245e44478d@nvidia.com>

Hi Marek,

On Tue, 21 Aug 2012 17:01:08 +0200
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> > > > -__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
> > > > +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
> > > > +                   const void *caller)
> > > >  {
> > > > -       struct arm_vmregion *c;
> > > > -       size_t align;
> > > > -       size_t count = size >> PAGE_SHIFT;
> > > > -       int bit;
> > > > +       unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
> > > > +       struct vm_struct *area;
> > > > +       unsigned long p;
> > > >
> > > > -       if (!consistent_pte[0]) {
> > > > -               pr_err("%s: not initialised\n", __func__);
> > > > -               dump_stack();
> > > > +       area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
> > > > +                                 caller);
> > > > +       if (!area)
> > >
> > > This patch replaced the custom "consistent_pte" with
> > > get_vm_area_caller()", which breaks the compatibility with the
> > > existing driver. This causes the following kernel oops(*1). That
> > > driver has called dma_pool_alloc() to allocate memory from the
> > > interrupt context, and it hits BUG_ON(in_interrpt()) in
> > > "get_vm_area_caller()"(*2). Regardless of the badness of allocation
> > > from interrupt handler in the driver, I have the following question.
> > >
> > > The following "__get_vm_area_node()" can take gfp_mask, it means that
> > > this function is expected to be called from atomic context, but why
> > > it's _NOT_ allowed _ONLY_ from interrupt context?
> > >
> > > According to the following definitions, "in_interrupt()" is in "in_atomic()".
> > >
> > > #define in_interrupt()	(preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK | NMI_MASK))
> > > #define in_atomic()	((preempt_count() & ~PREEMPT_ACTIVE) != 0)
> > >
> > > Does anyone know why BUG_ON(in_interrupt()) is set in __get_vm_area_node(*3)?
> > 
> > For arm_dma_alloc(), it allocates from the pool if GFP_ATOMIC, but for
> > arm_iommu_alloc_attrs() doesn't have pre-allocate pool at all, and it
> > always call "get_vm_area_caller()". That's why it hits BUG(). But
> > still I don't understand why it's not BUG_ON(in_atomic) as Russell
> > already pointed out(*1).
> > 
> > *1: http://article.gmane.org/gmane.linux.kernel.mm/76708
> 
> Ok, now I see the problem. I will try to find out a solution for your issue.

My explanation wasn't so good.

For a solution, I thought that, in order to allow IOMMU'able device
drivers to allocate memory from atomic context/ISR, there were the
following 2 solutions:

(1) To provide the pre-allocate area like arm_dma_alloc() does,
or
(2) __get_vm_area_node() can be called from ISR.

But (2) doesn't work because PGALLOC_GFP(GFP_KERNEL) is used to
allocate a page table. This is called from:

  arm_iommu_alloc_attrs() ->
    __iommu_alloc_remap() ->
      ioremap_page_range() ->
        .....              ->
          pte_alloc_one_kernel() ->
              pte = (pte_t *)__get_free_page(PGALLOC_GFP);

We always have to avoid changing a page table for atomic
allocation. So for me, the only remaining solution is
(1) pre-allocation. We can make use of the same atomic pool both for
DMA and IOMMU. I'll send the patch.


From hdoyu at nvidia.com  Wed Aug 22 06:20:26 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 13:20:26 +0300
Subject: [RFC 0/4] ARM: dma-mapping: IOMMU atomic allocation
Message-ID: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>

Hi,

The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
region" breaks the compatibility with existing drivers. This causes
the following kernel oops(*1). That driver has called dma_pool_alloc()
to allocate memory from the interrupt context, and it hits
BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
fixes this problem with making use of the pre-allocate atomic memory
pool which DMA is using in the same way as DMA does now.

Any comment would be really appreciated.

*1:
[    8.321343] ------------[ cut here ]------------
[    8.325971] kernel BUG at /home/hdoyu/mydroid-k340-cardhu/kernel/mm/vmalloc.c:1322!
[    8.333615] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[    8.339436] Modules linked in:
[    8.342496] CPU: 0    Tainted: G        W     (3.4.6-00067-g5d485f7 #67)
[    8.349192] PC is at __get_vm_area_node.isra.29+0x164/0x16c
[    8.354758] LR is at get_vm_area_caller+0x4c/0x54
[    8.359454] pc : [<c011297c>]    lr : [<c011318c>]    psr: 20000193
[    8.359458] sp : c09edca0  ip : c09ec000  fp : ae278000
[    8.370922] r10: f0000000  r9 : c011aa54  r8 : c0a26cb8
[    8.376136] r7 : 00000001  r6 : 000000d0  r5 : 20000008  r4 : c09edca0
[    8.382651] r3 : 00010000  r2 : 20000008  r1 : 00000001  r0 : 00001000
[    8.389166] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    8.396549] Control: 10c5387d  Table: ad98c04a  DAC: 00000015
....
[    9.169162] dfa0: 412fc099 c09ec000 00000000 c000fdd8 c06df1e4 c0a1b080 00000000 00000000
[    9.177329] dfc0: c0a235cc 8000406a 00000000 c0986818 ffffffff ffffffff c0986404 00000000
[    9.185497] dfe0: 00000000 c09bb070 10c5387d c0a19c58 c09bb064 80008044 00000000 00000000
[    9.193673] [<c011297c>] (__get_vm_area_node.isra.29+0x164/0x16c) from [<c011318c>] (get_vm_area_caller+0x4c/0x54)
[    9.204022] [<c011318c>] (get_vm_area_caller+0x4c/0x54) from [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc)
[    9.214276] [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc) from [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8)
[    9.224795] [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8) from [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8)
[    9.235309] [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8) from [<c011ab60>] (dma_pool_alloc+0x80/0x170)
[    9.245304] [<c011ab60>] (dma_pool_alloc+0x80/0x170) from [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c)
[    9.254344] [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c) from [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8)
[    9.263467] [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8) from [<c03cc140>] (tegra_ep_queue+0x154/0x33c)
[    9.272592] [<c03cc140>] (tegra_ep_queue+0x154/0x33c) from [<c03dd5b4>] (composite_setup+0x364/0x6d4)
[    9.281804] [<c03dd5b4>] (composite_setup+0x364/0x6d4) from [<c03dd9dc>] (android_setup+0xb8/0x14c)
[    9.290843] [<c03dd9dc>] (android_setup+0xb8/0x14c) from [<c03cd144>] (setup_received_irq+0xbc/0x270)
[    9.300053] [<c03cd144>] (setup_received_irq+0xbc/0x270) from [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4)
[    9.309353] [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4) from [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0)
[    9.319087] [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0) from [<c00b59b4>] (handle_irq_event+0x44/0x64)
[    9.328907] [<c00b59b4>] (handle_irq_event+0x44/0x64) from [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c)
[    9.338294] [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c) from [<c00b4f14>] (generic_handle_irq+0x34/0x48)
[    9.347858] [<c00b4f14>] (generic_handle_irq+0x34/0x48) from [<c000f6f4>] (handle_IRQ+0x54/0xb4)
[    9.356637] [<c000f6f4>] (handle_IRQ+0x54/0xb4) from [<c00084b0>] (gic_handle_irq+0x2c/0x60)
[    9.365068] [<c00084b0>] (gic_handle_irq+0x2c/0x60) from [<c000e900>] (__irq_svc+0x40/0x70)
[    9.373405] Exception stack(0xc09edf10 to 0xc09edf58)
[    9.378447] df00:                                     00000000 000f4240 00000003 00000000
[    9.386615] df20: 00000000 e55bbc00 ef66f3ca 00000001 00000000 412fc099 c0abb9c8 00000000
[    9.394781] df40: 3b9ac9ff c09edf58 c027a9bc c0042880 20000113 ffffffff
[    9.401396] [<c000e900>] (__irq_svc+0x40/0x70) from [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78)
[    9.410272] [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78) from [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4)
[    9.419922] [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4) from [<c000fdd8>] (cpu_idle+0xd8/0x134)
[    9.428612] [<c000fdd8>] (cpu_idle+0xd8/0x134) from [<c0986818>] (start_kernel+0x27c/0x2cc)
[    9.436952] Code: e1a00004 e3a04000 eb002265 eaffffe0 (e7f001f2)
[    9.443038] ---[ end trace 1b75b31a2719ed24 ]---
[    9.447645] Kernel panic - not syncing: Fatal exception in interrupt


Hiroshi Doyu (4):
  ARM: dma-mapping: Refactor out to introduce __alloc_fill_pages
  ARM: dma-mapping: IOMMU allocates pages from pool with GFP_ATOMIC
  ARM: dma-mapping: Return cpu addr when dma_alloc(GFP_ATOMIC)
  ARM: dma-mapping: dma_{alloc,free}_coherent with empty attrs

 arch/arm/include/asm/dma-mapping.h |   21 ++++++++++--
 arch/arm/mm/dma-mapping.c          |   59 ++++++++++++++++++++++++++++--------
 2 files changed, 63 insertions(+), 17 deletions(-)

-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Aug 22 06:28:42 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Wed, 22 Aug 2012 12:28:42 +0200
Subject: Kernel oops since v3.5.x on Atmel chips
Message-ID: <5034B45A.5060107@atmel.com>

Hi,

Doing some tests with the help of Lava (a Linaro tool), I get some 
kernel oops with 3.5.x on several chips at91sam9260, at91sam9261 and 
at91sam9m10g45.

Most of the time the oops comes from the cascade BUG() call in 
kernel/timer.c but sometimes it comes from a bad PC value.

With Lava, I got the crash each time. It happens after mounting a mtd 
partition, copying a file from it, removing this file from the flash 
memory and then unmounting the mtd partition.

I couldn't reproduce manually this issue so maybe there is something 
related to time...

Here I paste the usual oops and the one with the bad PC value:

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0
Linux version 3.5.0 (ldesroches at ibiza) (gcc version 4.6.1 (Ubuntu/Linaro 
4.6.1-9ubuntu3) ) #10 Wed Aug 22 09:17:23 CEST 2012
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Atmel AT91SAM9260-EK
Memory policy: ECC disabled, Data cache writeback
AT91: Detected soc type: at91sam9260
AT91: Detected soc subtype: Unknown
AT91: sram at 0x2ff000 of 0x2000 mapped at 0xfef76000
Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: mem=64M console=ttyS0,115200 
mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,70M(rootfs),-(data) 
root=/dev/mtdblock1 rw rootfstype=jffs2 ip=192.168.1.16:::255.255.255.0:::
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 60848k/60848k available, 4688k reserved, 0K highmem
Virtual kernel memory layout:
     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
     vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
     lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
     modules : 0xbf000000 - 0xc0000000   (  16 MB)
       .text : 0xc0008000 - 0xc039fee8   (3680 kB)
       .init : 0xc03a0000 - 0xc03bd7c4   ( 118 kB)
       .data : 0xc03be000 - 0xc03e8f00   ( 172 kB)
        .bss : 0xc03e8f24 - 0xc03fb138   (  73 kB)
NR_IRQS:192
AT91: 96 gpio irqs in 3 banks
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 
4294967286ms
Console: colour dummy device 80x30
Calibrating delay loop... 98.71 BogoMIPS (lpj=493568)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
Setting up static identity map for 0x202af150 - 0x202af1a8
devtmpfs: initialized
NET: Registered protocol family 16
AT91: Power Management (with slow clock mode)
AT91: Starting after software reset
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Advanced Linux Sound Architecture Driver Version 1.0.25.
Switching to clocksource pit
cfg80211: Calling CRDA to update world regulatory domain
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
msgmni has been set to 118
io scheduler noop registered (default)
atmel_usart.0: ttyS0 at MMIO 0xfffff200 (irq = 1) is a ATMEL_SERIAL
console [ttyS0] enabled
atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL
atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL
brd: module loaded
loop: module loaded
atmel_nand: Use On Flash BBT
atmel_nand atmel_nand: No DMA support for NAND access.
NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 
3,3V 8-bit), page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
nand_read_bbt: bad block at 0x000009840000
nand_read_bbt: bad block at 0x00000fb80000
3 cmdlinepart partitions found on MTD device atmel_nand
Creating 3 MTD partitions on "atmel_nand":
0x000000000000-0x000000400000 : "bootstrap/uboot/kernel"
0x000000400000-0x000004a00000 : "rootfs"
0x000004a00000-0x000010000000 : "data"
MACB_mii_bus: probed
macb macb: eth0: Cadence MACB at 0xfffc4000 irq 21 (3a:1f:34:08:54:54)
macb macb: eth0: attached PHY driver [Davicom DM9161A] 
(mii_bus:phy_addr=macb-ffffffff:00, irq=-1)
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
at91_ohci at91_ohci: can't request overcurrent gpio 0
at91_ohci at91_ohci: AT91 OHCI
at91_ohci at91_ohci: new USB bus registered, assigned bus number 1
at91_ohci at91_ohci: irq 20, io mem 0x00500000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: AT91 OHCI
usb usb1: Manufacturer: Linux 3.5.0 ohci_hcd
usb usb1: SerialNumber: at91
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
usbcore: registered new interface driver cdc_acm
cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mousedev: PS/2 mouse device common for all mice
TCP: cubic registered
NET: Registered protocol family 17
lib80211: common routines for IEEE802.11 drivers
VFP support v0.3: not present
input: gpio-keys as /devices/platform/gpio-keys/input/input0
/home/ldesroches/workspace/linux/drivers/rtc/hctosys.c: unable to open 
rtc device (rtc0)
IP-Config: Complete:
      device=eth0, addr=192.168.1.16, mask=255.255.255.0, gw=255.255.255.255
      host=192.168.1.16, domain=, nis-domain=(none)
      bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=
ALSA device list:
   No soundcards found.
macb macb: eth0: link up (100/Full)
jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
VFS: Mounted root (jffs2 filesystem) on device 31:1.
devtmpfs: mounted
Freeing init memory: 116K
Starting logging: OK
Populating  using udev: udevd[468]: starting version 182
done
Starting portmap: done
Initializing random number generator... done.
Starting network...
ip: RTNETLINK answers: File exists
Starting sshd: OK

Welcome to Buildroot
at91 login: root
[root at at91 ~]#
[root at at91 ~]#
[root at at91 ~]# export PS1="$PS1 [rc=$(echo \$?)]: "
[root at at91 ~]#  [rc=0]: mount -t jffs2 /dev/mtdblock2 /mnt/
jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
o_at91_lava/tmp [rc=0]: rm -rf /tmp/lava_results.tgz 
/tmp//srv/lava/instances/rf
[root at at91 ~]#  [rc=0]: mkdir -p /tmp//srv/lava/instances/rfo_at91_lava/tmp
tmp//srv/lava/instances/rfo_at91_lava/tmp/instances/rfo_at91_lava/tmp/*.bundle 
/
eroot at at91 ~]#  [rc=0]: rm -f 
/mnt//srv/lava/instances/rfo_at91_lava/tmp/*.bundl
[root at at91 ~]#  [rc=0]: umount /mnt/
[root at at91 ~]#  [rc=0]: ------------[ cut here ]------------
kernel BUG at /home/ldesroches/workspace/linux/kernel/timer.c:1091!
Internal error: Oops - BUG: 0 [#1] ARM
Modules linked in:
CPU: 0    Not tainted  (3.5.0 #10)
PC is at cascade+0x54/0x78
LR is at cascade+0x60/0x78
pc : [<c0023c80>]    lr : [<c0023c8c>]    psr: a0000093
sp : c03bfec8  ip : ffffae00  fp : 00000000
r10: c03ee540  r9 : 0000000a  r8 : 00000100
r7 : c03bfec8  r6 : c03bfec8  r5 : 0000002e  r4 : c03ee6a0
r3 : 00000000  r2 : 00000068  r1 : c3a60738  r0 : c03ee9ec
Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 0005317f  Table: 23a58000  DAC: 00000017
Process swapper (pid: 0, stack limit = 0xc03be270)
Stack: (0xc03bfec8 to 0xc03c0000)
fec0:                   c03faf70 c3a60738 0000002e c03ee6a0 c03be000 
00000000
fee0: c03ee560 c0023d98 c0145bc4 c3952ba0 00000000 00000000 c03cddf4 
00000001
ff00: 00000004 c03be000 c03ee560 00000100 c03ee540 c001f4b0 000027da 
c03cddf4
ff20: 00000000 00000001 c03bff9c 00000001 00000000 fefff000 c03bff9c 
20004000
ff40: 41069265 203b834c 00000000 c001f890 fefff000 c000dfc8 c000e0cc 
c000e0e0
ff60: a0000013 c000d398 00000000 0005317f 0005217f a0000013 c03be000 
c03c8f54
ff80: c03e8fe8 c047c300 20004000 41069265 203b834c 00000000 a00000d3 
c03bffb0
ffa0: c000e0cc c000e0e0 a0000013 ffffffff c000e0b4 c000e27c c03c60b0 
ffffffff
ffc0: c03b9784 c03a070c ffffffff ffffffff c03a0274 00000000 00000000 
c03b9784
ffe0: 00000000 00053175 c03c603c c03b9780 c03c8f4c 20008040 00000000 
00000000
[<c0023c80>] (cascade+0x54/0x78) from [<c0023d98>] 
(run_timer_softirq+0x68/0x1f4)
[<c0023d98>] (run_timer_softirq+0x68/0x1f4) from [<c001f4b0>] 
(__do_softirq+0x7c/0x110)
[<c001f4b0>] (__do_softirq+0x7c/0x110) from [<c001f890>] 
(irq_exit+0x40/0x4c)
[<c001f890>] (irq_exit+0x40/0x4c) from [<c000dfc8>] (handle_IRQ+0x74/0x98)
[<c000dfc8>] (handle_IRQ+0x74/0x98) from [<c000d398>] (__irq_svc+0x38/0x60)
[<c000d398>] (__irq_svc+0x38/0x60) from [<c000e0e0>] 
(default_idle+0x2c/0x34)
[<c000e0e0>] (default_idle+0x2c/0x34) from [<c000e27c>] (cpu_idle+0x78/0xd8)
[<c000e27c>] (cpu_idle+0x78/0xd8) from [<c03a070c>] 
(start_kernel+0x280/0x2d0)
Code: e591300c e3c33001 e1540003 0a000000 (e7f001f2)
---[ end trace 6105dc3872c7de5d ]---
Kernel panic - not syncing: Fatal exception in interrupt





Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0
Linux version 3.5.0 (ldesroches at ibiza) (gcc version 4.6.1 (Ubuntu/Linaro 
4.6.1-9ubuntu3) ) #10 Wed Aug 22 09:17:23 CEST 2012
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Atmel AT91SAM9260-EK
Memory policy: ECC disabled, Data cache writeback
AT91: Detected soc type: at91sam9260
AT91: Detected soc subtype: Unknown
AT91: sram at 0x2ff000 of 0x2000 mapped at 0xfef76000
Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: mem=64M console=ttyS0,115200 
mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,70M(rootfs),-(data) 
root=/dev/mtdblock1 rw rootfstype=jffs2 ip=192.168.1.16:::255.255.255.0:::
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 60848k/60848k available, 4688k reserved, 0K highmem
Virtual kernel memory layout:
     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
     vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
     lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
     modules : 0xbf000000 - 0xc0000000   (  16 MB)
       .text : 0xc0008000 - 0xc039fee8   (3680 kB)
       .init : 0xc03a0000 - 0xc03bd7c4   ( 118 kB)
       .data : 0xc03be000 - 0xc03e8f00   ( 172 kB)
        .bss : 0xc03e8f24 - 0xc03fb138   (  73 kB)
NR_IRQS:192
AT91: 96 gpio irqs in 3 banks
sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 
4294967286ms
Console: colour dummy device 80x30
Calibrating delay loop... 98.71 BogoMIPS (lpj=493568)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
Setting up static identity map for 0x202af150 - 0x202af1a8
devtmpfs: initialized
NET: Registered protocol family 16
AT91: Power Management (with slow clock mode)
AT91: Starting after software reset
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Advanced Linux Sound Architecture Driver Version 1.0.25.
Switching to clocksource pit
cfg80211: Calling CRDA to update world regulatory domain
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
msgmni has been set to 118
io scheduler noop registered (default)
atmel_usart.0: ttyS0 at MMIO 0xfffff200 (irq = 1) is a ATMEL_SERIAL
console [ttyS0] enabled
atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL
atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL
brd: module loaded
loop: module loaded
atmel_nand: Use On Flash BBT
atmel_nand atmel_nand: No DMA support for NAND access.
NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 
3,3V 8-bit), page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
nand_read_bbt: bad block at 0x000009840000
nand_read_bbt: bad block at 0x00000fb80000
3 cmdlinepart partitions found on MTD device atmel_nand
Creating 3 MTD partitions on "atmel_nand":
0x000000000000-0x000000400000 : "bootstrap/uboot/kernel"
0x000000400000-0x000004a00000 : "rootfs"
0x000004a00000-0x000010000000 : "data"
MACB_mii_bus: probed
macb macb: eth0: Cadence MACB at 0xfffc4000 irq 21 (3a:1f:34:08:54:54)
macb macb: eth0: attached PHY driver [Davicom DM9161A] 
(mii_bus:phy_addr=macb-ffffffff:00, irq=-1)
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
at91_ohci at91_ohci: can't request overcurrent gpio 0
at91_ohci at91_ohci: AT91 OHCI
at91_ohci at91_ohci: new USB bus registered, assigned bus number 1
at91_ohci at91_ohci: irq 20, io mem 0x00500000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: AT91 OHCI
usb usb1: Manufacturer: Linux 3.5.0 ohci_hcd
usb usb1: SerialNumber: at91
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
usbcore: registered new interface driver cdc_acm
cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
mousedev: PS/2 mouse device common for all mice
TCP: cubic registered
NET: Registered protocol family 17
lib80211: common routines for IEEE802.11 drivers
VFP support v0.3: not present
input: gpio-keys as /devices/platform/gpio-keys/input/input0
/home/ldesroches/workspace/linux/drivers/rtc/hctosys.c: unable to open 
rtc device (rtc0)
IP-Config: Complete:
      device=eth0, addr=192.168.1.16, mask=255.255.255.0, gw=255.255.255.255
      host=192.168.1.16, domain=, nis-domain=(none)
      bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=
ALSA device list:
   No soundcards found.
macb macb: eth0: link up (100/Full)
jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
VFS: Mounted root (jffs2 filesystem) on device 31:1.
devtmpfs: mounted
Freeing init memory: 116K
Starting logging: OK
Populating  using udev: done
udevd[468]: starting version 182
Starting portmap: done
Initializing random number generator... done.
Starting network...
ip: RTNETLINK answers: File exists
Starting sshd: OK

Welcome to Buildroot
at91 login: root
[root at at91 ~]#
[root at at91 ~]#
[root at at91 ~]# export PS1="$PS1 [rc=$(echo \$?)]: "
[root at at91 ~]#  [rc=0]: mount -t jffs2 /dev/mtdblock2 /mnt/
jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
o_at91_lava/tmp [rc=0]: rm -rf /tmp/lava_results.tgz 
/tmp//srv/lava/instances/rf
[root at at91 ~]#  [rc=0]: mkdir -p /tmp//srv/lava/instances/rfo_at91_lava/tmp
tmp//srv/lava/instances/rfo_at91_lava/tmp/instances/rfo_at91_lava/tmp/*.bundle 
/
eroot at at91 ~]#  [rc=0]: rm -f 
/mnt//srv/lava/instances/rfo_at91_lava/tmp/*.bundl
[root at at91 ~]#  [rc=0]: umount /mnt/
[root at at91 ~]#  [rc=0]: Unable to handle kernel paging request at 
virtual address 0d0c951c
pgd = c0004000
[0d0c951c] *pgd=00000000
Internal error: Oops: 80000005 [#1] ARM
Modules linked in:
CPU: 0    Not tainted  (3.5.0 #10)
PC is at 0xd0c951c
LR is at run_timer_softirq+0x144/0x1f4
pc : [<0d0c951c>]    lr : [<c0023e74>]    psr: 20000013
sp : c03bfee8  ip : 00200200  fp : 00000000
r10: 0d0c951c  r9 : 0000000a  r8 : c03bfef0
r7 : c03ee560  r6 : 00000100  r5 : c03be000  r4 : c03ee6a0
r3 : 20000013  r2 : 00000000  r1 : c03bfef0  r0 : b5a01535
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 0005317f  Table: 23a58000  DAC: 00000017
Process swapper (pid: 0, stack limit = 0xc03be270)
Stack: (0xc03bfee8 to 0xc03c0000)
fee0:                   c0145bc4 c396dba0 c03bfef0 c03bfef0 c03cddf4 
00000001
ff00: 00000004 c03be000 c03ee560 00000100 c03ee540 c001f4b0 00002870 
c03cddf4
ff20: 00000000 00000001 c03bff9c 00000001 00000000 fefff000 c03bff9c 
20004000
ff40: 41069265 203b834c 00000000 c001f890 fefff000 c000dfc8 c000e0cc 
c000e0e0
ff60: a0000013 c000d398 00000000 0005317f 0005217f a0000013 c03be000 
c03c8f54
ff80: c03e8fe8 c047c300 20004000 41069265 203b834c 00000000 a00000d3 
c03bffb0
ffa0: c000e0cc c000e0e0 a0000013 ffffffff c000e0b4 c000e27c c03c60b0 
ffffffff
ffc0: c03b9784 c03a070c ffffffff ffffffff c03a0274 00000000 00000000 
c03b9784
ffe0: 00000000 00053175 c03c603c c03b9780 c03c8f4c 20008040 00000000 
00000000
[<c0023e74>] (run_timer_softirq+0x144/0x1f4) from [<c001f4b0>] 
(__do_softirq+0x7c/0x110)
[<c001f4b0>] (__do_softirq+0x7c/0x110) from [<c001f890>] 
(irq_exit+0x40/0x4c)
[<c001f890>] (irq_exit+0x40/0x4c) from [<c000dfc8>] (handle_IRQ+0x74/0x98)
[<c000dfc8>] (handle_IRQ+0x74/0x98) from [<c000d398>] (__irq_svc+0x38/0x60)
[<c000d398>] (__irq_svc+0x38/0x60) from [<c000e0e0>] 
(default_idle+0x2c/0x34)
[<c000e0e0>] (default_idle+0x2c/0x34) from [<c000e27c>] (cpu_idle+0x78/0xd8)
[<c000e27c>] (cpu_idle+0x78/0xd8) from [<c03a070c>] 
(start_kernel+0x280/0x2d0)
Code: bad PC value
---[ end trace f65db9c681fbd6e3 ]---
Kernel panic - not syncing: Fatal exception in interrupt



Regards

Ludovic


From catalin.marinas at arm.com  Wed Aug 22 06:29:53 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 Aug 2012 11:29:53 +0100
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <201208220756.31149.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208212014.01837.arnd@arndb.de> <20120821220145.GA27934@arm.com>
 <201208220756.31149.arnd@arndb.de>
Message-ID: <20120822102953.GA24136@arm.com>

On Wed, Aug 22, 2012 at 08:56:30AM +0100, Arnd Bergmann wrote:
> On Tuesday 21 August 2012, Catalin Marinas wrote:
> > As I understand, sys_mmap_pgoff can be used instead of sys_mmap2 on new
> > 32-bit architectures. But on 64-bit architectures we don't have
> > sys_mmap2, only sys_mmap with the difference that the last argument is
> > the offset in bytes (and multiple of PAGE_SIZE) rather than in pages. So
> > unless we change the meaning of this last argument for sys_mmap, we
> > cannot just define it to sys_mmap_pgoff.
> > 
> > Since the other 64-bit architectures seem to have a sys_mmap wrapper
> > that does this:
> > 
> >         sys_mmap_pgoff(..., off >> PAGE_SHIFT);
> > 
> > I think AArch64 should also use the same sys_mmap convention. We can
> > make this wrapper generic.
> 
> But the wrapper can just as well be part of glibc, which already has
> one. There is no reason for the kernel to export two generic interfaces
> for mmap when one of them only works on 64 bit and the other one is
> good for both 32 and 64 bit.

The kernel only exports a single interface for 64-bit, that's
sys_mmap(). For compat we only export sys_mmap2() (which, of course,
would not work for 64-bit).

The generic prototypes for sys_mmap and sys_mmap2 are different with
regards to the last argument: off_t vs unsigned long. While in practice
it's the same size, off_t is used throughout the kernel as offset in
bytes rather than pages (hence the prototype change in sys_mmap2 and
sys_mmap_pgoff).

But what's more important - moving this wrapper to glibc causes issues
with the page size. We support both 4KB and 64KB pages on 64-bit systems
(the latter without compat support). The kernel is in a better position
to do the shift by a compile-time constant. Glibc would need to enquire
the actual page size to do the shift before calling sys_mmap_pgoff. If
we assume in glibc that the shift is always 12, we need another wrapper
in the kernel anyway for 64KB page configuration. So passing the offset
in bytes worked best for us.

> All the other 64 bit architectures (besides tile) were added to the
> kernel before we had sys_mmap_pgoff.

So there is no new 64-bit architecture that defines sys_mmap to
sys_mmap_pgoff. I don't think that AArch64 should introduce this, given
the restrictions I mentioned above. sys_mmap2/sys_mmap_pgoff are a way
to extend the file offset beyond 32-bit but that's not needed on a
64-bit system.

-- 
Catalin


From js at sig21.net  Wed Aug 22 06:34:43 2012
From: js at sig21.net (Johannes Stezenbach)
Date: Wed, 22 Aug 2012 12:34:43 +0200
Subject: [GIT PULL v2] Update LZO compression
In-Reply-To: <5033A78E.3080703@oberhumer.com>
References: <5033A78E.3080703@oberhumer.com>
Message-ID: <20120822103443.GA15245@sig21.net>

On Tue, Aug 21, 2012 at 05:21:50PM +0200, Markus F.X.J. Oberhumer wrote:
> as suggested on the mailing list I have converted the updated LZO
> code into git, so please pull my "lzo-update" branch from
...
> [ Changes in v2: Optimize code for CPUs with inefficient unaligned
>   access => significant speed increase on ARM ]

I can confirm that this new code runs at the same speed
as the current lzo code in the Linux kernel on
my ARM926EJ-S based platform.  I only tested decompression,
using the attached hacky userspace code.

   # time ./lzo-bench/old/unlzop <lzoimage >/dev/null
   real    0m 0.29s
   # time ./lzo-bench/new/unlzop <lzoimage >/dev/null
   real    0m 0.29s

   (where lzoimage is a Linux Image compressed with lzop)

So, from my side there are no more objections.
Thanks for doing this work, Markus.


Johannes
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From b29396 at freescale.com  Wed Aug 22 06:57:30 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 18:57:30 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <20120822082940.GJ4011@b20223-02.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822082940.GJ4011@b20223-02.ap.freescale.net>
Message-ID: <20120822105729.GB10057@shlinux2.ap.freescale.net>

On Wed, Aug 22, 2012 at 04:29:41PM +0800, Zhao Richard-B20223 wrote:
> On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Add regmap based imx syscon driver.
> > This is usually used for access misc bits in registers which does not belong
> > to a specific module, for example, IOMUXC GPR and ANATOP.
> > With this driver, we provide a standard API for client driver to call to
> > access registers which are registered into syscon.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> > Currently it's just simply for IMX, however the driver really is not too
> > much imx specific.
> > If people want, we probably could extend it to support other platforms too.
> > ---
> >  .../devicetree/bindings/mfd/imx-syscon.txt         |   11 +
> >  drivers/mfd/Kconfig                                |    8 +
> >  drivers/mfd/Makefile                               |    1 +
> >  drivers/mfd/imx-syscon.c                           |  193 ++++++++++++++++++++
> >  include/linux/mfd/imx-syscon.h                     |   22 +++
> >  5 files changed, 235 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> > new file mode 100644
> > index 0000000..4a72994
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> > @@ -0,0 +1,11 @@
> > +* Freescale IMX System Controller Registers R/W driver
> > +
> > +Required properties:
> > +- compatible: Should contain "fsl,imx-syscon".
> > +- reg: the register range can be access from imx-syscon
> > +
> > +Examples:
> > +gpr: iomuxc-gpr at 020e0000 {
> > +	compatible = "fsl,imx6q-iomuxc", "fsl,imx-syscon";
> why is it compatible with iomuxc?
> 
The first one usually is describing the device itself,
the second one is the required compatible string for using imx-sycon.

btw, it looks i'd better change "fsl,imx6q-iomuxc" to "fsl,imx6q-iomuxc-gpr"
since the later is the real case for us which is in patch 2/7.

> > +static int imx_syscon_match(struct device *dev, void *data)
> > +{
> > +	struct imx_syscon *syscon = dev_get_drvdata(dev);
> > +	struct device_node *dn = data;
> > +
> > +	return (syscon->dev->of_node == dn) ? 1 : 0;
> > +}
> > +
> > +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
> For API function, is it better to use struct device rather not np?
>  - it won't need to search dev in below code every time it access
>    registers.
The purpose is not require client driver to know the implementation details
of imx_syscon_{read/write} API, it's more easy to use since client only
needs pass the device node to which it wants to read/write.

For search dev, it doesn't look like a big issue since it only search devices
attached on the driver which is very quick.
And hide it in common API does not require every client driver to write
duplicated codes.

> > +static int __devinit imx_syscon_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct device_node *np = dev->of_node;
> > +	struct imx_syscon *syscon;
> > +	struct resource res;
> > +	int ret;
> > +
> > +	if (!np)
> > +		return -ENOENT;
> > +
> > +	syscon = devm_kzalloc(&pdev->dev, sizeof(struct imx_syscon),
> > +			    GFP_KERNEL);
> > +	if (!syscon)
> > +		return -ENOMEM;
> > +
> > +	syscon->base = of_iomap(np, 0);
> no request? use devm_request_and_ioremap?
> 
The io space registered into imx-sycon may be overlapped with other device,
e.g. iomuxc gpr overlapped with iomuxc. So we do not request it here.
There are also some exist examples, imx28 pinctrl with gpio devices contained.

Regards
Dong Aisheng



From broonie at opensource.wolfsonmicro.com  Wed Aug 22 07:19:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 12:19:13 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120822081746.GA4089@gmail.com>
References: <20120820162923.GF26991@opensource.wolfsonmicro.com>
 <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
 <20120821120243.GF26899@gmail.com>
 <20120821165207.GX7995@opensource.wolfsonmicro.com>
 <20120822081746.GA4089@gmail.com>
Message-ID: <20120822111913.GG7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 09:17:50AM +0100, Lee Jones wrote:

> I was saying that in order for the MFD core to carry out the hwirq->virq
> conversion, it needed to obtain the irqdomain pointer pertaining to the
> provided hwirq. The only helper function the irqdomain subsystem provides
> requires a device node pointer to be passed as an argument, hence the
> mention of 'irq_find_host(struct device_node *np)'. Then the Device Tree
> is traversed until a specified 'interrupt-controller' is stumbled upon
> or is pointed to by the 'interrupt-parent' property. Hence, we have to 
> find another way to find the irqdomain pointers for non-DT based MFDs. To
> which we now have a solution.

Oh, right.  Yes, there's no way to get an irqdomain if you don't already
have it or something which has a direct mapping to one like an irqdomain.

> > I made the suggestion then later on realised that this was actively
> > going to break things I care about so I actually need it fixing.

> I'm a little taken aback and annoyed by this. In a previous email thread
> you categorically requested that I discuss some of the important changes
> with maintainers and people in-the-know prior to actually writing any
> code.

No, that's not something I've ever said to do.

I *have* asked you to communicate more clearly about what you're doing
but that doesn't mean to stop sending code, it means to have clearer
words around what you're sending.  The really bad pattern here is that
you're frequently working around issues in your drivers with changes in
the subsystem without mentioning that the driver issues even exist -
this makes it much harder understand what you are trying to achieve,
especially when there is a problem with your subsystem changes and/or
the urgency you're attaching to them.

>       I was obviously actively working on, had put time into, and was in
> the mist of discussing this with you. Then you just go ahead and code it
> (the easy part) yourself, essentially wasting my time. Surely there's
> some kind of etiquette surrounding such things?

To be honest in this case I had expected to send the patch out much
sooner than I did - several priority interrupts stopped me testing it.
Like I say I realised that I really needed a fix and it seemed like the
quickest way to accomplish that was to just send the code.
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From b29396 at freescale.com  Wed Aug 22 07:02:10 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 22 Aug 2012 19:02:10 +0800
Subject: [PATCH 6/7] ARM: dts: imx6q: add simple-bus compatible string
 for anatop
In-Reply-To: <20120822085236.GK4011@b20223-02.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-7-git-send-email-b29396@freescale.com>
 <20120822085236.GK4011@b20223-02.ap.freescale.net>
Message-ID: <20120822110209.GC10057@shlinux2.ap.freescale.net>

On Wed, Aug 22, 2012 at 04:52:36PM +0800, Zhao Richard-B20223 wrote:
> On Wed, Aug 22, 2012 at 03:18:47PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Originally the anatop regulator devices are populated by mfd anatop driver.
> > Since mfd anatop driver will be deleted later, we change to populate the
> > regulator devices by devicetree automatically.
> > This will cause some warning messages as follows during boot due to device
> > recreation: "vdd1p1: Failed to create debugfs directory"
> > But it does not break any function.
> > Later, we will remove mfd anatop driver which can get rid of this
> > error message.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> >  arch/arm/boot/dts/imx6q.dtsi |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> > index 7076be0..426f735 100644
> > --- a/arch/arm/boot/dts/imx6q.dtsi
> > +++ b/arch/arm/boot/dts/imx6q.dtsi
> > @@ -379,7 +379,7 @@
> >  			};
> >  
> >  			anatop: anatop at 020c8000 {
> > -				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon";
> > +				compatible = "fsl,imx6q-anatop", "fsl,imx-syscon", "simple-bus";
> To prevent bisect break, it should merge with patch #4.
Yes, i will try it and merge them if needed.

> It's really strange to use simple-bus, because it's not a bus.
I can't say it's strange or not.
There are existing using examples, imx28.dtsi.

> I like more the way how anatop driver handle it. Anatop driver populate
> devices in its code.
The anatop mfd driver will be deleted later.
So the proper solution may be generating regulator devices automatically when call
of_platform_populate in mach code rather than populate it in driver itself.

Regards
Dong Aisheng



From linux at arm.linux.org.uk  Wed Aug 22 07:23:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 Aug 2012 12:23:39 +0100
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <20120822095302.GX18957@n2100.arm.linux.org.uk>
References: <50339AF6.1060601@codeaurora.org>
 <5033C428.2050607@codeaurora.org> <50348030.9080200@codeaurora.org>
 <20120822095302.GX18957@n2100.arm.linux.org.uk>
Message-ID: <20120822112339.GY18957@n2100.arm.linux.org.uk>

On Wed, Aug 22, 2012 at 10:53:02AM +0100, Russell King - ARM Linux wrote:
> @@ -826,7 +826,7 @@ static void __init fill_pmd_gaps(void)
>  
>  	/* we're still single threaded hence no lock needed here */
>  	for (vm = vmlist; vm; vm = vm->next) {
> -		if (!(vm->flags & VM_ARM_STATIC_MAPPING))
> +		if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))

Not forgetting the additional close paren needed here...


From gururaja.hebbar at ti.com  Wed Aug 22 07:35:11 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 11:35:11 +0000
Subject: [PATCH 4/5] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <20120817224327.GK18871@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-5-git-send-email-gururaja.hebbar@ti.com>
 <20120817224327.GK18871@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA658C7@DBDE01.ent.ti.com>

On Sat, Aug 18, 2012 at 04:13:28, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 06:12:04PM +0530, Hebbar, Gururaja wrote:
> 
> > +- ti,codec-clock : The Codec Clock from the board
> 
> I think this is the clock rate?  Please specify it more specifically.

I will correct it in v2.

> 
> > +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> > +"<evm ops required, evm_ops or evm_spdif_ops>";
> 
> Please be more specific as to what these actually do - consider the user
> who is reading the bindings with a view to implementing them for their
> board, or writing drivers for another OS.

Will add more detail in V2

> 


Regards, 
Gururaja


From shc_work at mail.ru  Wed Aug 22 07:36:23 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Wed, 22 Aug 2012 15:36:23 +0400
Subject: [PATCH] GPIO: Add support for GPIO on CLPS711X-target platform
Message-ID: <1345635383-12224-1-git-send-email-shc_work@mail.ru>

The CLPS711X CPUs provide some GPIOs for use in the system. This
driver provides support for these via gpiolib. Due to platform
limitations, driver does not support interrupts, only inputs and
outputs.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/Kconfig                           |    1 +
 arch/arm/mach-clps711x/include/mach/gpio.h |   13 ++
 drivers/gpio/Kconfig                       |    4 +
 drivers/gpio/Makefile                      |    1 +
 drivers/gpio/gpio-clps711x.c               |  178 ++++++++++++++++++++++++++++
 5 files changed, 197 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-clps711x/include/mach/gpio.h
 create mode 100644 drivers/gpio/gpio-clps711x.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..1f718b0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -384,6 +384,7 @@ config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 	select CPU_ARM720T
 	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_REQUIRE_GPIOLIB
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Cirrus Logic 711x/721x/731x based boards.
diff --git a/arch/arm/mach-clps711x/include/mach/gpio.h b/arch/arm/mach-clps711x/include/mach/gpio.h
new file mode 100644
index 0000000..8ac6889
--- /dev/null
+++ b/arch/arm/mach-clps711x/include/mach/gpio.h
@@ -0,0 +1,13 @@
+/*
+ *  This file contains the CLPS711X GPIO definitions.
+ *
+ *  Copyright (C) 2012 Alexander Shiyan <shc_work at mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/* Simple helper for convert port & pin to GPIO number */
+#define CLPS711X_GPIO(port, bit)	((port) * 8 + (bit))
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b16c8a7..72b9d2f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -91,6 +91,10 @@ config GPIO_MAX730X
 
 comment "Memory mapped GPIO drivers:"
 
+config GPIO_CLPS711X
+	def_bool y
+	depends on ARCH_CLPS711X
+
 config GPIO_GENERIC_PLATFORM
 	tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
 	select GPIO_GENERIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153cace..6a41f79 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
 obj-$(CONFIG_GPIO_BT8XX)	+= gpio-bt8xx.o
+obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
 obj-$(CONFIG_GPIO_CS5535)	+= gpio-cs5535.o
 obj-$(CONFIG_GPIO_DA9052)	+= gpio-da9052.o
 obj-$(CONFIG_ARCH_DAVINCI)	+= gpio-davinci.o
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
new file mode 100644
index 0000000..c527609
--- /dev/null
+++ b/drivers/gpio/gpio-clps711x.c
@@ -0,0 +1,178 @@
+/*
+ *  CLPS711X GPIO driver
+ *
+ *  Copyright (C) 2012 Alexander Shiyan <shc_work at mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+
+#define CLPS711X_GPIO_PORTS	5
+
+struct clps711x_gpio {
+	struct gpio_chip	chip[CLPS711X_GPIO_PORTS];
+	struct mutex		lock;
+};
+
+static inline u32 gpio_clps711x_port_dataaddr(struct gpio_chip *chip)
+{
+	switch (chip->base) {
+	case 0:
+		return PADR;
+	case 8:
+		return PBDR;
+	case 16:
+		return PCDR;
+	case 24:
+		return PDDR;
+	}
+
+	return PEDR;
+}
+
+static inline u32 gpio_clps711x_port_diraddr(struct gpio_chip *chip)
+{
+	switch (chip->base) {
+	case 0:
+		return PADDR;
+	case 8:
+		return PBDDR;
+	case 16:
+		return PCDDR;
+	case 24:
+		return PDDDR;
+	}
+
+	return PEDDR;
+}
+
+static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
+{
+	int ret;
+	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+
+	mutex_lock(&gpio->lock);
+	ret = clps_readb(gpio_clps711x_port_dataaddr(chip)) & (1 << offset);
+	mutex_unlock(&gpio->lock);
+
+	return !!ret;
+}
+
+static void gpio_clps711x_set(struct gpio_chip *chip, unsigned offset,
+			      int value)
+{
+	int tmp;
+	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+
+	mutex_lock(&gpio->lock);
+	tmp = clps_readb(gpio_clps711x_port_dataaddr(chip)) & ~(1 << offset);
+	if (value)
+		tmp |= 1 << offset;
+	clps_writeb(tmp, gpio_clps711x_port_dataaddr(chip));
+	mutex_unlock(&gpio->lock);
+}
+
+static int gpio_clps711x_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+	int tmp;
+	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+
+	mutex_lock(&gpio->lock);
+	tmp = clps_readb(gpio_clps711x_port_diraddr(chip)) & ~(1 << offset);
+	clps_writeb(tmp, gpio_clps711x_port_diraddr(chip));
+	mutex_unlock(&gpio->lock);
+
+	return 0;
+}
+
+static int gpio_clps711x_direction_out(struct gpio_chip *chip, unsigned offset,
+				       int value)
+{
+	int tmp;
+	struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+
+	mutex_lock(&gpio->lock);
+	tmp = clps_readb(gpio_clps711x_port_diraddr(chip)) | (1 << offset);
+	clps_writeb(tmp, gpio_clps711x_port_diraddr(chip));
+	tmp = clps_readb(gpio_clps711x_port_dataaddr(chip)) & ~(1 << offset);
+	if (value)
+		tmp |= 1 << offset;
+	clps_writeb(tmp, gpio_clps711x_port_dataaddr(chip));
+	mutex_unlock(&gpio->lock);
+
+	return 0;
+}
+
+struct clps711x_gpio_port {
+	char	*name;
+	int	nr;
+};
+
+static const struct clps711x_gpio_port clps711x_gpio_ports[] __devinitconst = {
+	{ "PORTA", 8, },
+	{ "PORTB", 8, },
+	{ "PORTC", 8, },
+	{ "PORTD", 8, },
+	{ "PORTE", 3, },
+};
+
+static int __devinit gpio_clps711x_probe(struct platform_device *pdev)
+{
+	int i;
+	struct clps711x_gpio *gpio;
+
+	gpio = kzalloc(sizeof(struct clps711x_gpio), GFP_KERNEL);
+	if (!gpio) {
+		dev_err(&pdev->dev, "GPIO allocating memory error\n");
+		return -ENOMEM;
+	}
+
+	dev_set_drvdata(&pdev->dev, gpio);
+
+	mutex_init(&gpio->lock);
+
+	for (i = 0; i < ARRAY_SIZE(clps711x_gpio_ports); i++) {
+		gpio->chip[i].owner		= THIS_MODULE;
+		gpio->chip[i].dev		= &pdev->dev;
+		gpio->chip[i].label		= clps711x_gpio_ports[i].name;
+		gpio->chip[i].base		= i * 8;
+		gpio->chip[i].ngpio		= clps711x_gpio_ports[i].nr;
+		gpio->chip[i].direction_input	= gpio_clps711x_direction_in;
+		gpio->chip[i].get		= gpio_clps711x_get;
+		gpio->chip[i].direction_output	= gpio_clps711x_direction_out;
+		gpio->chip[i].set		= gpio_clps711x_set;
+		gpiochip_add(&gpio->chip[i]);
+	}
+
+	dev_info(&pdev->dev, "GPIO driver initialized\n");
+
+	return 0;
+}
+
+static struct platform_driver clps711x_gpio_driver = {
+	.driver	= {
+		.name	= "gpio-clps711x",
+		.owner	= THIS_MODULE,
+	},
+	.probe	= gpio_clps711x_probe,
+};
+
+static int __init gpio_clps711x_init(void)
+{
+	return platform_driver_register(&clps711x_gpio_driver);
+}
+postcore_initcall(gpio_clps711x_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Alexander Shiyan <shc_work at mail.ru>");
+MODULE_DESCRIPTION("CLPS711X GPIO driver");
-- 
1.7.3.4



From broonie at opensource.wolfsonmicro.com  Wed Aug 22 07:40:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 12:40:15 +0100
Subject: [PATCH 14/14] drivers/spi/spi-s3c24xx.c: fix error return code
In-Reply-To: <1b3201cd8049$e753f720$b5fbe560$%kim@samsung.com>
References: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>
 <1b3201cd8049$e753f720$b5fbe560$%kim@samsung.com>
Message-ID: <20120822114015.GI7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 06:38:36PM +0900, Kukjin Kim wrote:
> Julia Lawall wrote:

> > Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

> Acked-by: Kukjin Kim <kgene.kim at samsung.com>

> (Cc'ed Mark Brown who is handling spi for a moment)

Please resend the patch to me so I can apply this.
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From julia.lawall at lip6.fr  Wed Aug 22 07:42:47 2012
From: julia.lawall at lip6.fr (Julia Lawall)
Date: Wed, 22 Aug 2012 13:42:47 +0200 (CEST)
Subject: [PATCH 14/14] drivers/spi/spi-s3c24xx.c: fix error return code
In-Reply-To: <20120822114015.GI7995@opensource.wolfsonmicro.com>
References: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>
 <1b3201cd8049$e753f720$b5fbe560$%kim@samsung.com>
 <20120822114015.GI7995@opensource.wolfsonmicro.com>
Message-ID: <alpine.DEB.2.02.1208221342240.1991@hadrien>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Initialize return variable before exiting on an error path.

A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)

// <smpl>
(
if at p1 (\(ret < 0\|ret != 0\))
 { ... return ret; }
|
ret at p1 = 0
)
... when != ret = e1
    when != &ret
*if(...)
{
  ... when != ret = e2
      when forall
 return ret;
}

// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
Perhaps -EINVAL is not the right value in this case.

 drivers/spi/spi-s3c24xx.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 8ee7d79..a2a080b 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -611,6 +611,7 @@ static int __devinit s3c24xx_spi_probe(struct platform_device *pdev)
 	if (!pdata->set_cs) {
 		if (pdata->pin_cs < 0) {
 			dev_err(&pdev->dev, "No chipselect pin\n");
+			err = -EINVAL;
 			goto err_register;
 		}




From linus.walleij at linaro.org  Wed Aug 22 07:49:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:49:22 +0200
Subject: [PATCH 0/7] Ux500 and MASK_ON_SUSPEND
In-Reply-To: <1345624986-5557-1-git-send-email-linus.walleij@stericsson.com>
References: <1345624986-5557-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdYyrFZYuNSj+y7f1uyF53+TYqdSfEcpv28H677uS1fd6A@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:43 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> We have discovered transient IRQs when going to suspend on the
> Ux500 platform. This patch series hits all sources by marking
> the applicable IRQchips with MASK_ON_SUSPEND.
>
> I don't know if this is a common problem or seen in other
> platforms so comments are welcome.
>
> Else I request that the patches be merged into respective
> subtree, I will take care of the ux500, gpio and pinctrl
> patches myself, while Sam gets to merge all the MFD stuff.

Bah it turns out transient IRQs are only occurring on the pinctrl
and maybe GIC. Let's just flag these two, forget the rest of the
patches.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 22 07:50:07 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:50:07 +0200
Subject: [PATCH 2/7] mfd/ab8500: MASK_ON_SUSPEND
In-Reply-To: <1345625036-5643-1-git-send-email-linus.walleij@stericsson.com>
References: <1345625036-5643-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdYd6sHrJ3kW7sUeqZgmLmCPoKsQ2k57=k+TmDud1YBU+Q@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:43 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> ux500 machines performs pins (GPIO) reconfiguration when entering
> in the suspended mode. This reconfiguration aims at reaching an ultra
> low power HW configuration.

Sam, please disregard this patch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 22 07:50:28 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:50:28 +0200
Subject: [PATCH 3/7] gpio/ab8500: MASK_ON_SUSPEND
In-Reply-To: <1345625042-5678-1-git-send-email-linus.walleij@stericsson.com>
References: <1345625042-5678-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdY=n=a=FEzLOp-KpjjcgeP+RqHM+DC_eVJf0KrHR7ytyA@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:44 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> ux500 machines performs pins (GPIO) reconfiguration when entering
> in the suspended mode. This reconfiguration aims at reaching an ultra
> low power HW configuration.

Sam, please disregard this patch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 22 07:50:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:50:45 +0200
Subject: [PATCH 4/7] mfd/db8500-prcmu: MASK_ON_SUSPEND
In-Reply-To: <1345625049-5714-1-git-send-email-linus.walleij@stericsson.com>
References: <1345625049-5714-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdb6-a5qaxJRF6j3Fs+DkwngRRi1f=goOb4Pdfuq5CB-4g@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:44 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> ux500 machines performs pins (GPIO) reconfiguration when entering
> in the suspended mode. This reconfiguration aims at reaching an ultra
> low power HW configuration.

Sam, please disregard this patch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 22 07:51:06 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:51:06 +0200
Subject: [PATCH 6/7] mfd/stmpe: MASK_ON_SUSPEND
In-Reply-To: <1345625063-5784-1-git-send-email-linus.walleij@stericsson.com>
References: <1345625063-5784-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdYX9egAokWMWqbfzhOaoT4=fwu72cJz_gKBYhf3yPgApw@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:44 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> ux500 machines performs pins (GPIO) reconfiguration when entering
> in the suspended mode. This reconfiguration aims at reaching an ultra
> low power HW configuration.

Sam, please disregard this patch.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Aug 22 07:51:18 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 13:51:18 +0200
Subject: [PATCH 7/7] mfd/tc3589x: MASK_ON_SUSPEND
In-Reply-To: <1345625070-5820-1-git-send-email-linus.walleij@stericsson.com>
References: <1345625070-5820-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CACRpkdZd8pEp4N17MWTsMk-Rd7FG1jPaS0sGCBLQ71UaOAMLVw@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:44 AM, Linus Walleij
<linus.walleij at stericsson.com> wrote:

> ux500 machines performs pins (GPIO) reconfiguration when entering
> in the suspended mode. This reconfiguration aims at reaching an ultra
> low power HW configuration.

Sam, please disregard this patch.

Yours,
Linus Walleij


From lee.jones at linaro.org  Wed Aug 22 07:55:25 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 22 Aug 2012 12:55:25 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120822111913.GG7995@opensource.wolfsonmicro.com>
References: <20120820164949.GB22749@gmail.com>
 <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
 <20120821120243.GF26899@gmail.com>
 <20120821165207.GX7995@opensource.wolfsonmicro.com>
 <20120822081746.GA4089@gmail.com>
 <20120822111913.GG7995@opensource.wolfsonmicro.com>
Message-ID: <20120822115524.GA18545@gmail.com>

> > > I made the suggestion then later on realised that this was actively
> > > going to break things I care about so I actually need it fixing.
> 
> > I'm a little taken aback and annoyed by this. In a previous email thread
> > you categorically requested that I discuss some of the important changes
> > with maintainers and people in-the-know prior to actually writing any
> > code.
> 
> No, that's not something I've ever said to do.
> 
> I *have* asked you to communicate more clearly about what you're doing
> but that doesn't mean to stop sending code, it means to have clearer
> words around what you're sending. 

That's not how I interpreted your words:

"What you can do here is to commmunicate about what you're doing more.
Don't just think about the code, think about the communication
surrounding the code - this is the core of the issue."

> The really bad pattern here is that
> you're frequently working around issues in your drivers with changes in
> the subsystem without mentioning that the driver issues even exist -
> this makes it much harder understand what you are trying to achieve,
> especially when there is a problem with your subsystem changes and/or
> the urgency you're attaching to them.

Frequently? I've done this once, and yes I did push hard because I
thought the subsystem was incorrect (I still think folding an entire
driver because of a minor failure is wrong, but we digress).

This is completely different to that. This was a subsystem change
designed to aid DT enabled MFDs which 'chose' to register themselves
in a specific way, by passing their compatible string through the 
mfd_cell only. It doesn't affect any other MFD unless they wrongly
assume the conversion would be automatically done for them. However,
the author would know because they would have tested it. All of this
was discussed at length with Arnd and this is what we came up with. 

I think it's great that you like the idea and want to extend that
functionality to other MFDs which perhaps don't support DT, or the
ones that do but don't want to provide compatible strings or device
nodes for all the MFD's child devices. But that is all we're doing
here. There was no breakage. It served a purpose and it worked well.
So well in fact that you've now provided the intended functionality
to other devices.

> >       I was obviously actively working on, had put time into, and was in
> > the mist of discussing this with you. Then you just go ahead and code it
> > (the easy part) yourself, essentially wasting my time. Surely there's
> > some kind of etiquette surrounding such things?
> 
> To be honest in this case I had expected to send the patch out much
> sooner than I did - several priority interrupts stopped me testing it.
> Like I say I realised that I really needed a fix and it seemed like the
> quickest way to accomplish that was to just send the code.

You only noticed it 2 days ago and I had a patch ready to go yesterday.
I'm confused because I don't understand why would you even complain about
it if you intended to work on it yourself? Surely, "Ah, I see an issue with
xyz, patch to follow." Would have been more appropriate, instead of 
complaining about it, then I go and waste my time trying to fix something
you intend on fixing yourself.

I guess what's done is done now.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From mnalajal at codeaurora.org  Wed Aug 22 08:03:41 2012
From: mnalajal at codeaurora.org (Murali Nalajala)
Date: Wed, 22 Aug 2012 17:33:41 +0530
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <20120822095302.GX18957@n2100.arm.linux.org.uk>
References: <50339AF6.1060601@codeaurora.org>
 <5033C428.2050607@codeaurora.org> <50348030.9080200@codeaurora.org>
 <20120822095302.GX18957@n2100.arm.linux.org.uk>
Message-ID: <5034CA9D.1070001@codeaurora.org>

On 8/22/2012 3:23 PM, Russell King - ARM Linux wrote:
> On Wed, Aug 22, 2012 at 12:16:08PM +0530, Trilok Soni wrote:
>> Thanks for the patch, but how about just checking pmd_none on such
>> addresses and since there won't be any mapping created for such gaps? We
>> need to check if this is fine for all, since I remember that Nico
>> added these functions for the OMAP boot issue I guess.
>
> A better solution would be as below - this requires no changes to the
> existing ioremap code, we just mark these differently.
>
> diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
> index 2e8a1ef..87fa3f2 100644
> --- a/arch/arm/mm/mm.h
> +++ b/arch/arm/mm/mm.h
> @@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
>   /* permanent static mappings from iotable_init() */
>   #define VM_ARM_STATIC_MAPPING	0x40000000
>
> +/* empty mapping */
> +#define VM_ARM_EMPTY_MAPPING	0x20000000
> +
>   /* mapping type (attributes) for permanent static mappings */
>   #define VM_ARM_MTYPE(mt)		((mt)<<  20)
>   #define VM_ARM_MTYPE_MASK	(0x1f<<  20)
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index cf4528d..da90ef1 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -813,7 +813,7 @@ static void __init pmd_empty_section_gap(unsigned long addr)
>   	vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
>   	vm->addr = (void *)addr;
>   	vm->size = SECTION_SIZE;
> -	vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
> +	vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
>   	vm->caller = pmd_empty_section_gap;
>   	vm_area_add_early(vm);
>   }
> @@ -826,7 +826,7 @@ static void __init fill_pmd_gaps(void)
>
>   	/* we're still single threaded hence no lock needed here */
>   	for (vm = vmlist; vm; vm = vm->next) {
> -		if (!(vm->flags&  VM_ARM_STATIC_MAPPING))
> +		if (!(vm->flags&  (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))
>   			continue;
>   		addr = (unsigned long)vm->addr;
>   		if (addr<  next)
>
Tested on MSM platform

Tested-by: Murali Nalajala <mnalajal at codeaurora.org>

Thanks,
Murali N

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From m.szyprowski at samsung.com  Wed Aug 22 08:04:26 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 22 Aug 2012 14:04:26 +0200
Subject: [RFC 0/4] ARM: dma-mapping: IOMMU atomic allocation
In-Reply-To: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <005901cd805e$4afd2e40$e0f78ac0$%szyprowski@samsung.com>

Hi Hiroshi,

On Wednesday, August 22, 2012 12:20 PM Hiroshi Doyu wrote:

> The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
> region" breaks the compatibility with existing drivers. This causes
> the following kernel oops(*1). That driver has called dma_pool_alloc()
> to allocate memory from the interrupt context, and it hits
> BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
> fixes this problem with making use of the pre-allocate atomic memory
> pool which DMA is using in the same way as DMA does now.
> 
> Any comment would be really appreciated.

I was working on the similar patches, but You were faster. ;-)

Basically the patch no 1 and 2 are fine, but I don't like the changes proposed in 
patch 3 and 4. You should not alter the attributes provided by the user nor make any
assumptions that such attributes has been provided - drivers are allowed to call 
dma_alloc_attrs() directly. Please rework your patches to avoid such approach.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From linus.walleij at linaro.org  Wed Aug 22 08:09:30 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 22 Aug 2012 14:09:30 +0200
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <CACRpkdaDi8KMk0tyWuEHGnLWhZ4ufnNY4cUm-+q9kKryBztzkw@mail.gmail.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <CACRpkdaDi8KMk0tyWuEHGnLWhZ4ufnNY4cUm-+q9kKryBztzkw@mail.gmail.com>
Message-ID: <CACRpkdZF-J_P9M2hOZhnJtNrUE_2exefUg1Tj7S_dj0jUPBuKA@mail.gmail.com>

On Thu, Aug 16, 2012 at 2:56 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Mon, Aug 6, 2012 at 6:32 PM, Linus Walleij
> <linus.walleij at stericsson.com> wrote:
>
>> This converts the ARM RealView machine over to using the common
>> clock. The approach is similar to the one used for the Integrator,
>> and we're reusing the ICST wrapper code.
>
> Mike have you had time to look at this? I got Pawel's ACK in the thread.

Ping again on this, if it's OK it would be great to get some rotation in
-next for this patch.

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Wed Aug 22 08:24:19 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 22 Aug 2012 14:24:19 +0200
Subject: [PATCH v2] ARM: at91: select DT support by default
In-Reply-To: <50326887.5050400@atmel.com>
References: <1345477226-23483-1-git-send-email-ludovic.desroches@atmel.com>
 <20120820162651.GB7456@game.jcrosoft.org>
 <50326887.5050400@atmel.com>
Message-ID: <20120822122419.GC7456@game.jcrosoft.org>

On 18:40 Mon 20 Aug     , ludovic.desroches wrote:
> Le 08/20/2012 06:26 PM, Jean-Christophe PLAGNIOL-VILLARD a ?crit :
> >On 17:40 Mon 20 Aug     , ludovic.desroches at atmel.com wrote:
> >>From: Ludovic Desroches <ludovic.desroches at atmel.com>
> >>
> >>Since at91sam9x5, at91sam9n12 and future SOCs only have device tree
> >>support, select it by default.
> >>
> >>Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> >>Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >>Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >>---
> >>  arch/arm/mach-at91/Kconfig | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >>diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> >>index c8050b1..5aee940 100644
> >>--- a/arch/arm/mach-at91/Kconfig
> >>+++ b/arch/arm/mach-at91/Kconfig
> >>@@ -502,6 +502,7 @@ comment "Generic Board Type"
> >>
> >>  config MACH_AT91SAM_DT
> >>  	bool "Atmel AT91SAM Evaluation Kits with device-tree support"
> >>+	default y
> >>  	select USE_OF
> >no you can not force the USE_OF
> >
> >force the machine by default if USE_OF ok otherwise no
> >to this you need to select the USE_OF as SoC level
> 
> Sorry, it seems I have badly understood your first answer and I
> don't understand the second one too.
> 
> So what did you mean by "as we are goig to have more and more soc
> put it as default in the MACH_AT91SAM_DT if the DT is enabled"?
enable the MACH_AT91SAM_DT by default it the right way if USE_OF which means
for sam9x5 and n12 only

for the other soc that can have both OF and non of kernel
you need select the USE_OF only if the MACH_AT91SAM_DT is enable by the end
user (not by default)

Best Regards,
J.


From arnd at arndb.de  Wed Aug 22 08:27:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 12:27:14 +0000
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <20120822102953.GA24136@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208220756.31149.arnd@arndb.de> <20120822102953.GA24136@arm.com>
Message-ID: <201208221227.14274.arnd@arndb.de>

On Wednesday 22 August 2012, Catalin Marinas wrote:
> But what's more important - moving this wrapper to glibc causes issues
> with the page size. We support both 4KB and 64KB pages on 64-bit systems
> (the latter without compat support). The kernel is in a better position
> to do the shift by a compile-time constant. Glibc would need to enquire
> the actual page size to do the shift before calling sys_mmap_pgoff. If
> we assume in glibc that the shift is always 12, we need another wrapper
> in the kernel anyway for 64KB page configuration. So passing the offset
> in bytes worked best for us.

Right, the kernel interface should really be independent of the page
size, as sys_mmap2 normally is, and sys_mmap2 is not provided here.

	Arnd


From m.szyprowski at samsung.com  Wed Aug 22 08:29:47 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 22 Aug 2012 14:29:47 +0200
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
Message-ID: <005a01cd8061$d58998c0$809cca40$%szyprowski@samsung.com>

Hello,

On Wednesday, August 22, 2012 12:20 PM Hiroshi Doyu wrote:

> Makes use of the same atomic pool from DMA, and skips kernel page
> mapping which can involves sleep'able operation at allocating a kernel
> page table.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   22 ++++++++++++++++++----
>  1 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index aec0c06..9260107 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1028,7 +1028,6 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> size,
>  	struct page **pages;
>  	int count = size >> PAGE_SHIFT;
>  	int array_size = count * sizeof(struct page *);
> -	int err;
> 
>  	if (array_size <= PAGE_SIZE)
>  		pages = kzalloc(array_size, gfp);
> @@ -1037,9 +1036,20 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> size,
>  	if (!pages)
>  		return NULL;
> 
> -	err = __alloc_fill_pages(&pages, count, gfp);
> -	if (err)
> -		goto error
> +	if (gfp & GFP_ATOMIC) {
> +		struct page *page;
> +		int i;
> +		void *addr = __alloc_from_pool(size, &page);
> +		if (!addr)
> +			goto err_out;
> +
> +		for (i = 0; i < count; i++)
> +			pages[i] = page + i;
> +	} else {
> +		int err = __alloc_fill_pages(&pages, count, gfp);
> +		if (err)
> +			goto error;
> +	}
> 
>  	return pages;
>  error:
> @@ -1055,6 +1065,10 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages,
> size_t s
>  	int count = size >> PAGE_SHIFT;
>  	int array_size = count * sizeof(struct page *);
>  	int i;
> +
> +	if (__free_from_pool(page_address(pages[0]), size))
> +		return 0;

You leak memory here. pages array should be also freed.

> +
>  	for (i = 0; i < count; i++)
>  		if (pages[i])
>  			__free_pages(pages[i], 0);
> --
> 1.7.5.4


Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From plagnioj at jcrosoft.com  Wed Aug 22 08:32:47 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 22 Aug 2012 14:32:47 +0200
Subject: [PATCH 1/5] i2c: at91: add new fixes for some TWI ip versions
In-Reply-To: <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
References: <1345559345-13988-1-git-send-email-ludovic.desroches@atmel.com>
 <1345559345-13988-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120822123247.GD7456@game.jcrosoft.org>

On 16:29 Tue 21 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> The at91sam9261 TWI ip version requires also some fixes. The id_entry
> field from the platform device structure has been replaced by the use
> of cpu_is_xxx function to determine when to use these fixes.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
>  arch/arm/mach-at91/at91rm9200_devices.c |  9 -------
>  drivers/i2c/busses/i2c-at91.c           | 42 +++++++++++++++++++--------------
>  2 files changed, 24 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
> index 2b9b493..e6b7d05 100644
> --- a/arch/arm/mach-at91/at91rm9200_devices.c
> +++ b/arch/arm/mach-at91/at91rm9200_devices.c
> @@ -494,18 +494,9 @@ static struct resource twi_resources[] = {
>  	},
>  };
>  
> -static const struct platform_device_id twi_id = {
> -	/*
> -	 * driver_data is "1" for hardware with ckdiv upper limit == 5
> -	 * (AT91RM9200 erratum 22), "0" for twi modules without this bug
> -	 */
> -	.driver_data	= 1,
> -};
> -
>  static struct platform_device at91rm9200_twi_device = {
>  	.name		= "at91_i2c",
>  	.id		= -1,
> -	.id_entry	= &twi_id,
>  	.resource	= twi_resources,
>  	.num_resources	= ARRAY_SIZE(twi_resources),
>  };
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> index b1cb780..4599522 100644
> --- a/drivers/i2c/busses/i2c-at91.c
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -27,6 +27,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
>  
> +#include <mach/cpu.h>
> +
>  #define TWI_CLK_HZ		100000			/* max 400 Kbits/s */
>  #define AT91_I2C_TIMEOUT	msecs_to_jiffies(100)	/* transfer timeout */
>  
> @@ -72,7 +74,6 @@ struct at91_twi_dev {
>  	int			irq;
>  	unsigned		transfer_status;
>  	struct i2c_adapter	adapter;
> -	bool			is_rm9200;
>  	unsigned		twi_cwgr_reg;
>  };
>  
> @@ -111,20 +112,28 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
>   */
>  static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
>  {
> -	const int offset = dev->is_rm9200 ? 3 : 4;
> -	const int div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> -						 2 * twi_clk) - offset);
> -	int ckdiv = fls(div >> 8);
> -	int cdiv = div >> ckdiv;
> -
> -	if (dev->is_rm9200 && (ckdiv > 5)) {
> -		dev_warn(dev->dev, "AT91RM9200 erratum 22: using ckdiv = 5.\n");
> -		ckdiv = 5;
> -		cdiv = 255;
> -	} else if (ckdiv > 7) {
> -		dev_warn(dev->dev, "%d exceeds 3 bits for ckdiv, limiting.\n",
> -			 ckdiv);
> -		ckdiv = 7;
> +	int offset, div, max_ckdiv, ckdiv, cdiv;
> +
> +	if (cpu_is_at91rm9200()) {
> +		offset = 3;
> +		max_ckdiv = 5;
> +	} else if (cpu_is_at91sam9261()) {
> +		offset = 4;
> +		max_ckdiv = 5;
> +	} else {
> +		offset = 4;
> +		max_ckdiv = 7;
> +	}
can you read this from the IP version?

I do not like the cpu_is outside of the mach-at91

Best Regards,
J.


From arnd at arndb.de  Wed Aug 22 08:34:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 12:34:30 +0000
Subject: [RESEND PATCH v4 0/2] omap: add ocp2scp as a bus driver
In-Reply-To: <1345624803-16379-1-git-send-email-kishon@ti.com>
References: <1345624803-16379-1-git-send-email-kishon@ti.com>
Message-ID: <201208221234.31193.arnd@arndb.de>

On Wednesday 22 August 2012, Kishon Vijay Abraham I wrote:
> This patch series has been lying here for long. If no one has any
> comments on this patch series, can someone pick it up?

I've added them now as a drivers/ocp2scp branch arm-soc and pulled
them into the next/drivers topic branch.

	Arnd


From gururaja.hebbar at ti.com  Wed Aug 22 08:37:18 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 12:37:18 +0000
Subject: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345574589-24757-2-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-2-git-send-email-mporter@ti.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA65999@DBDE01.ent.ti.com>

On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote:
> Add a DMA engine driver for the TI EDMA controller. This driver
> is implemented as a wrapper around the existing DaVinci private
> DMA implementation. This approach allows for incremental conversion
> of each peripheral driver to the DMA engine API. The EDMA driver
> supports slave transfers but does not yet support cyclic transfers.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>
> ---
>  drivers/dma/Kconfig  |   10 +
>  drivers/dma/Makefile |    1 +
>  drivers/dma/edma.c   |  684 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/edma.h |   29 +++
>  4 files changed, 724 insertions(+)
>  create mode 100644 drivers/dma/edma.c
>  create mode 100644 include/linux/edma.h
> 
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index d06ea29..5064e85 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -208,6 +208,16 @@ config SIRF_DMA
>  	help
>  	  Enable support for the CSR SiRFprimaII DMA engine.
>  
> +config TI_EDMA
> +	tristate "TI EDMA support"
> +	depends on ARCH_DAVINCI
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS
> +	default y
> +	help
> +	  Enable support for the TI EDMA controller. This DMA
> +	  engine is found on TI DaVinci and AM33xx parts.
> +
>  config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
>  	bool
>  
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 4cf6b12..f5cf310 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
>  obj-$(CONFIG_MXS_DMA) += mxs-dma.o
>  obj-$(CONFIG_TIMB_DMA) += timb_dma.o
>  obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
> +obj-$(CONFIG_TI_EDMA) += edma.o
>  obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
>  obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
>  obj-$(CONFIG_PL330_DMA) += pl330.o
> diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
> new file mode 100644
> index 0000000..bf15f81
> --- /dev/null
> +++ b/drivers/dma/edma.c
> @@ -0,0 +1,684 @@
> +/*
> + * TI EDMA DMA engine driver
> + *
> + * Copyright 2012 Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include <mach/edma.h>
> +
> +#include "dmaengine.h"
> +#include "virt-dma.h"
> +
> +/*
> + * This will go away when the private EDMA API is folded
> + * into this driver and the platform device(s) are
> + * instantiated in the arch code. We can only get away
> + * with this simplification because DA8XX may not be built
> + * in the same kernel image with other DaVinci parts. This
> + * avoids having to sprinkle dmaengine driver platform devices
> + * and data throughout all the existing board files.
> + */
> +#ifdef CONFIG_ARCH_DAVINCI_DA8XX
> +#define EDMA_CTLRS	2
> +#define EDMA_CHANS	32
> +#else
> +#define EDMA_CTLRS	1
> +#define EDMA_CHANS	64
> +#endif /* CONFIG_ARCH_DAVINCI_DA8XX */

I believe you already have some modifications for your next version to handle
Different EDMA IP versions (AM335x). 
They use/have cross-bar implementations as-well.

> +
> +/* Max of 16 segments per channel to conserve PaRAM slots */
> +#define MAX_NR_SG		16
> +#define EDMA_MAX_SLOTS		MAX_NR_SG

Is it possible to get this (EDMA_MAX_SLOTS) from platform data?

> +#define EDMA_DESCRIPTORS	16
> +
> +struct edma_desc {
> +	struct virt_dma_desc		vdesc;
> +	struct list_head		node;
> +
> +	int				absync;
> +	int				pset_nr;
> +	struct edmacc_param		pset[0];
> +};
> +
> +struct edma_cc;
> +
> +struct edma_chan {
> +	struct virt_dma_chan		vchan;
> +	struct list_head		node;
> +	struct edma_desc		*edesc;
> +	struct edma_cc			*ecc;
> +	int				ch_num;
> +	bool				alloced;
> +	int				slot[EDMA_MAX_SLOTS];
> +
> +	dma_addr_t			addr;
> +	int				addr_width;
> +	int				maxburst;
> +};
> +
> +struct edma_cc {
> +	int				ctlr;
> +	struct dma_device		dma_slave;
> +	struct edma_chan		slave_chans[EDMA_CHANS];
> +	int				num_slave_chans;
> +	int				dummy_slot;
> +};
> +
> +static inline struct edma_cc *to_edma_cc(struct dma_device *d)
> +{
> +	return container_of(d, struct edma_cc, dma_slave);
> +}
> +
> +static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
> +{
> +	return container_of(c, struct edma_chan, vchan.chan);
> +}
> +
> +static inline struct edma_desc
> +*to_edma_desc(struct dma_async_tx_descriptor *tx)
> +{
> +	return container_of(tx, struct edma_desc, vdesc.tx);
> +}
> +
> +static void edma_desc_free(struct virt_dma_desc *vdesc)
> +{
> +	kfree(container_of(vdesc, struct edma_desc, vdesc));
> +}
> +
> +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> +static void edma_execute(struct edma_chan *echan)
> +{
> +	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
> +	struct edma_desc *edesc;
> +	int i;
> +
> +	if (!vdesc) {
> +		echan->edesc = NULL;
> +		return;
> +	}
> +
> +	list_del(&vdesc->node);
> +
> +	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
> +
> +	/* Write descriptor PaRAM set(s) */
> +	for (i = 0; i < edesc->pset_nr; i++) {
> +		edma_write_slot(echan->slot[i], &edesc->pset[i]);
> +		dev_dbg(echan->vchan.chan.device->dev,
> +			"\n pset[%d]:\n"
> +			"  chnum\t%d\n"
> +			"  slot\t%d\n"
> +			"  opt\t%08x\n"
> +			"  src\t%08x\n"
> +			"  dst\t%08x\n"
> +			"  abcnt\t%08x\n"
> +			"  ccnt\t%08x\n"
> +			"  bidx\t%08x\n"
> +			"  cidx\t%08x\n"
> +			"  lkrld\t%08x\n",
> +			i, echan->ch_num, echan->slot[i],
> +			edesc->pset[i].opt,
> +			edesc->pset[i].src,
> +			edesc->pset[i].dst,
> +			edesc->pset[i].a_b_cnt,
> +			edesc->pset[i].ccnt,
> +			edesc->pset[i].src_dst_bidx,
> +			edesc->pset[i].src_dst_cidx,
> +			edesc->pset[i].link_bcntrld);
> +		/* Link to the previous slot if not the last set */
> +		if (i != (edesc->pset_nr - 1))
> +			edma_link(echan->slot[i], echan->slot[i+1]);
> +		/* Final pset links to the dummy pset */
> +		else
> +			edma_link(echan->slot[i], echan->ecc->dummy_slot);
> +	}
> +
> +	edma_start(echan->ch_num);
> +}
> +
> +static int edma_terminate_all(struct edma_chan *echan)
> +{
> +	unsigned long flags;
> +	LIST_HEAD(head);
> +
> +	spin_lock_irqsave(&echan->vchan.lock, flags);
> +
> +	/*
> +	 * Stop DMA activity: we assume the callback will not be called
> +	 * after edma_dma() returns (even if it does, it will see
> +	 * echan->edesc is NULL and exit.)
> +	 */
> +	if (echan->edesc) {
> +		echan->edesc = NULL;
> +		edma_stop(echan->ch_num);
> +	}
> +
> +	vchan_get_all_descriptors(&echan->vchan, &head);
> +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +	vchan_dma_desc_free_list(&echan->vchan, &head);
> +
> +	return 0;
> +}
> +
> +
> +static int edma_slave_config(struct edma_chan *echan,
> +	struct dma_slave_config *config)
> +{
> +	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> +		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> +		return -EINVAL;
> +
> +	if (config->direction == DMA_MEM_TO_DEV) {
> +		if (config->dst_addr)
> +			echan->addr = config->dst_addr;
> +		if (config->dst_addr_width)
> +			echan->addr_width = config->dst_addr_width;
> +		if (config->dst_maxburst)
> +			echan->maxburst = config->dst_maxburst;
> +	} else if (config->direction == DMA_DEV_TO_MEM) {
> +		if (config->src_addr)
> +			echan->addr = config->src_addr;
> +		if (config->src_addr_width)
> +			echan->addr_width = config->src_addr_width;
> +		if (config->src_maxburst)
> +			echan->maxburst = config->src_maxburst;
> +	}
> +
> +	return 0;
> +}
> +
> +static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> +			unsigned long arg)
> +{
> +	int ret = 0;
> +	struct dma_slave_config *config;
> +	struct edma_chan *echan = to_edma_chan(chan);
> +
> +	switch (cmd) {
> +	case DMA_TERMINATE_ALL:
> +		edma_terminate_all(echan);
> +		break;
> +	case DMA_SLAVE_CONFIG:
> +		config = (struct dma_slave_config *)arg;
> +		ret = edma_slave_config(echan, config);
> +		break;
> +	default:
> +		ret = -ENOSYS;
> +	}
> +
> +	return ret;
> +}
> +
> +static struct dma_async_tx_descriptor *edma_prep_slave_sg(
> +	struct dma_chan *chan, struct scatterlist *sgl,
> +	unsigned int sg_len, enum dma_transfer_direction direction,
> +	unsigned long tx_flags, void *context)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	struct edma_desc *edesc;
> +	struct scatterlist *sg;
> +	int i;
> +	int acnt, bcnt, ccnt, src, dst, cidx;
> +	int src_bidx, dst_bidx, src_cidx, dst_cidx;
> +
> +	if (unlikely(!echan || !sgl || !sg_len))
> +		return NULL;
> +
> +	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
> +		dev_err(dev, "Undefined slave buswidth\n");
> +		return NULL;
> +	}
> +
> +	if (sg_len > MAX_NR_SG) {
> +		dev_err(dev, "Exceeded max SG segments %d > %d\n",
> +			sg_len, MAX_NR_SG);
> +		return NULL;
> +	}
> +
> +	edesc = kzalloc(sizeof(*edesc) + sg_len *
> +		sizeof(edesc->pset[0]), GFP_ATOMIC);
> +	if (!edesc) {
> +		dev_dbg(dev, "Failed to allocate a descriptor\n");
> +		return NULL;
> +	}
> +
> +	edesc->pset_nr = sg_len;
> +
> +	for_each_sg(sgl, sg, sg_len, i) {
> +		/* Allocate a PaRAM slot, if needed */
> +		if (echan->slot[i] < 0) {
> +			echan->slot[i] =
> +				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
> +						EDMA_SLOT_ANY);
> +			if (echan->slot[i] < 0) {
> +				dev_err(dev, "Failed to allocate slot\n");
> +				return NULL;
> +			}
> +		}
> +
> +		acnt = echan->addr_width;
> +
> +		/*
> +		 * If the maxburst is equal to the fifo width, use
> +		 * A-synced transfers. This allows for large contiguous
> +		 * buffer transfers using only one PaRAM set.
> +		 */
> +		if (echan->maxburst == 1) {
> +			edesc->absync = false;
> +			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
> +			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
> +			if (bcnt)
> +				ccnt++;
> +			else
> +				bcnt = SZ_64K - 1;
> +			cidx = acnt;
> +		/*
> +		 * If maxburst is greater than the fifo address_width,
> +		 * use AB-synced transfers where A count is the fifo
> +		 * address_width and B count is the maxburst. In this
> +		 * case, we are limited to transfers of C count frames
> +		 * of (address_width * maxburst) where C count is limited
> +		 * to SZ_64K-1. This places an upper bound on the length
> +		 * of an SG segment that can be handled.
> +		 */
> +		} else {
> +			edesc->absync = true;
> +			bcnt = echan->maxburst;
> +			ccnt = sg_dma_len(sg) / (acnt * bcnt);
> +			if (ccnt > (SZ_64K - 1)) {
> +				dev_err(dev, "Exceeded max SG segment size\n");
> +				return NULL;
> +			}
> +			cidx = acnt * bcnt;
> +		}
> +
> +		if (direction == DMA_MEM_TO_DEV) {
> +			src = sg_dma_address(sg);
> +			dst = echan->addr;
> +			src_bidx = acnt;
> +			src_cidx = cidx;
> +			dst_bidx = 0;
> +			dst_cidx = 0;
> +		} else {
> +			src = echan->addr;
> +			dst = sg_dma_address(sg);
> +			src_bidx = 0;
> +			src_cidx = 0;
> +			dst_bidx = acnt;
> +			dst_cidx = cidx;
> +		}
> +
> +		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
> +		/* Configure A or AB synchronized transfers */
> +		if (edesc->absync)
> +			edesc->pset[i].opt |= SYNCDIM;
> +		/* If this is the last set, enable completion interrupt flag */
> +		if (i == sg_len - 1)
> +			edesc->pset[i].opt |= TCINTEN;
> +
> +		edesc->pset[i].src = src;
> +		edesc->pset[i].dst = dst;
> +
> +		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
> +		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
> +
> +		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
> +		edesc->pset[i].ccnt = ccnt;
> +		edesc->pset[i].link_bcntrld = 0xffffffff;
> +
> +	}
> +
> +	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
> +}
> +
> +static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
> +{
> +	struct edma_chan *echan = data;
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	struct edma_desc *edesc;
> +	unsigned long flags;
> +
> +	/* Stop the channel */
> +	edma_stop(echan->ch_num);
> +
> +	switch (ch_status) {
> +	case DMA_COMPLETE:
> +		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
> +
> +		spin_lock_irqsave(&echan->vchan.lock, flags);
> +
> +		edesc = echan->edesc;
> +		if (edesc) {
> +			edma_execute(echan);
> +			vchan_cookie_complete(&edesc->vdesc);
> +		}
> +
> +		spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +
> +		break;
> +	case DMA_CC_ERROR:
> +		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +/* Alloc channel resources */
> +static int edma_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	int ret;
> +	int a_ch_num;
> +	LIST_HEAD(descs);
> +
> +	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
> +					chan, EVENTQ_DEFAULT);
> +
> +	if (a_ch_num < 0) {
> +		ret = -ENODEV;
> +		goto err_no_chan;
> +	}
> +
> +	if (a_ch_num != echan->ch_num) {
> +		dev_err(dev, "failed to allocate requested channel %u:%u\n",
> +			EDMA_CTLR(echan->ch_num),
> +			EDMA_CHAN_SLOT(echan->ch_num));
> +		ret = -ENODEV;
> +		goto err_wrong_chan;
> +	}
> +
> +	echan->alloced = true;
> +	echan->slot[0] = echan->ch_num;
> +
> +	dev_info(dev, "allocated channel for %u:%u\n",
> +		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
> +
> +	return 0;
> +
> +err_wrong_chan:
> +	edma_free_channel(a_ch_num);
> +err_no_chan:
> +	return ret;
> +}
> +
> +/* Free channel resources */
> +static void edma_free_chan_resources(struct dma_chan *chan)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct device *dev = echan->vchan.chan.device->dev;
> +	int i;
> +
> +	/* Terminate transfers */
> +	edma_stop(echan->ch_num);
> +
> +	vchan_free_chan_resources(&echan->vchan);
> +
> +	/* Free EDMA PaRAM slots */
> +	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
> +		if (echan->slot[i] >= 0) {
> +			edma_free_slot(echan->slot[i]);
> +			echan->slot[i] = -1;
> +		}
> +	}
> +
> +	/* Free EDMA channel */
> +	if (echan->alloced) {
> +		edma_free_channel(echan->ch_num);
> +		echan->alloced = false;
> +	}
> +
> +	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
> +}
> +
> +/* Send pending descriptor to hardware */
> +static void edma_issue_pending(struct dma_chan *chan)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&echan->vchan.lock, flags);
> +	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
> +		edma_execute(echan);
> +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +}
> +
> +static size_t edma_desc_size(struct edma_desc *edesc)
> +{
> +	int i;
> +	size_t size;
> +
> +	if (edesc->absync)
> +		for (size = i = 0; i < edesc->pset_nr; i++)
> +			size += (edesc->pset[i].a_b_cnt & 0xffff) *
> +				(edesc->pset[i].a_b_cnt >> 16) *
> +				 edesc->pset[i].ccnt;
> +	else
> +		size = (edesc->pset[0].a_b_cnt & 0xffff) *
> +			(edesc->pset[0].a_b_cnt >> 16) +
> +			(edesc->pset[0].a_b_cnt & 0xffff) *
> +			(SZ_64K - 1) * edesc->pset[0].ccnt;
> +
> +	return size;
> +}
> +
> +/* Check request completion status */
> +static enum dma_status edma_tx_status(struct dma_chan *chan,
> +				      dma_cookie_t cookie,
> +				      struct dma_tx_state *txstate)
> +{
> +	struct edma_chan *echan = to_edma_chan(chan);
> +	struct virt_dma_desc *vdesc;
> +	enum dma_status ret;
> +	unsigned long flags;
> +
> +	ret = dma_cookie_status(chan, cookie, txstate);
> +	if (ret == DMA_SUCCESS || !txstate)
> +		return ret;
> +
> +	spin_lock_irqsave(&echan->vchan.lock, flags);
> +	vdesc = vchan_find_desc(&echan->vchan, cookie);
> +	if (vdesc) {
> +		txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
> +	} else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
> +		struct edma_desc *edesc = echan->edesc;
> +		txstate->residue = edma_desc_size(edesc);
> +	} else {
> +		txstate->residue = 0;
> +	}
> +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> +
> +	return ret;
> +}
> +
> +static void __init edma_chan_init(struct edma_cc *ecc,
> +				  struct dma_device *dma,
> +				  struct edma_chan *echans)
> +{
> +	int i, j;
> +	int chcnt = 0;
> +
> +	for (i = 0; i < EDMA_CHANS; i++) {
> +		struct edma_chan *echan = &echans[chcnt];
> +		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);

I couldn't find the definition for EDMA_CTLR_CHAN.

> +		echan->ecc = ecc;
> +		echan->vchan.desc_free = edma_desc_free;
> +
> +		vchan_init(&echan->vchan, dma);
> +
> +		INIT_LIST_HEAD(&echan->node);
> +		for (j = 0; j < EDMA_MAX_SLOTS; j++)
> +			echan->slot[j] = -1;
> +
> +		chcnt++;
> +	}
> +}
> +
> +static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
> +			  struct device *dev)
> +{
> +	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
> +		dma->device_prep_slave_sg = edma_prep_slave_sg;
> +
> +	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
> +	dma->device_free_chan_resources = edma_free_chan_resources;
> +	dma->device_issue_pending = edma_issue_pending;
> +	dma->device_tx_status = edma_tx_status;
> +	dma->device_control = edma_control;
> +	dma->dev = dev;
> +
> +	INIT_LIST_HEAD(&dma->channels);
> +}
> +
> +static int __devinit edma_probe(struct platform_device *pdev)
> +{
> +	struct edma_cc *ecc;
> +	int ret;
> +
> +	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
> +	if (!ecc) {
> +		dev_err(&pdev->dev, "Can't allocate controller\n");
> +		ret = -ENOMEM;
> +		goto err_alloc_ecc;
> +	}
> +
> +	ecc->ctlr = pdev->id;
> +	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
> +	if (ecc->dummy_slot < 0) {
> +		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
> +		ret = -EIO;
> +		goto err_alloc_slot;
> +	}
> +
> +	dma_cap_zero(ecc->dma_slave.cap_mask);
> +	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
> +
> +	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
> +
> +	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
> +
> +	ret = dma_async_device_register(&ecc->dma_slave);
> +	if (ret)
> +		goto err_reg1;
> +
> +	platform_set_drvdata(pdev, ecc);
> +
> +	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
> +
> +	return 0;
> +
> +err_reg1:
> +	edma_free_slot(ecc->dummy_slot);
> +err_alloc_slot:
> +	devm_kfree(&pdev->dev, ecc);
> +err_alloc_ecc:
> +	return ret;
> +}
> +
> +static int __devexit edma_remove(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct edma_cc *ecc = dev_get_drvdata(dev);
> +
> +	dma_async_device_unregister(&ecc->dma_slave);
> +	edma_free_slot(ecc->dummy_slot);
> +	devm_kfree(dev, ecc);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver edma_driver = {
> +	.probe		= edma_probe,
> +	.remove		= __devexit_p(edma_remove),
> +	.driver = {
> +		.name = "edma-dma-engine",
> +		.owner = THIS_MODULE,

I believe you already have plans for DT implementations for this as-well.

> +	},
> +};
> +
> +bool edma_filter_fn(struct dma_chan *chan, void *param)
> +{
> +	if (chan->device->dev->driver == &edma_driver.driver) {
> +		struct edma_chan *echan = to_edma_chan(chan);
> +		unsigned ch_req = *(unsigned *)param;
> +		return ch_req == echan->ch_num;
> +	}
> +	return false;
> +}
> +EXPORT_SYMBOL(edma_filter_fn);
> +
> +static struct platform_device *pdev0, *pdev1;
> +
> +static const struct platform_device_info edma_dev_info0 = {
> +	.name = "edma-dma-engine",
> +	.id = 0,
> +	.dma_mask = DMA_BIT_MASK(32),
> +};
> +
> +static const struct platform_device_info edma_dev_info1 = {
> +	.name = "edma-dma-engine",
> +	.id = 1,
> +	.dma_mask = DMA_BIT_MASK(32),
> +};
> +
> +static int edma_init(void)
> +{
> +	int ret = platform_driver_register(&edma_driver);
> +
> +	if (ret == 0) {
> +		pdev0 = platform_device_register_full(&edma_dev_info0);
> +		if (IS_ERR(pdev0)) {
> +			platform_driver_unregister(&edma_driver);
> +			ret = PTR_ERR(pdev0);
> +			goto out;
> +		}
> +	}
> +
> +	if (EDMA_CTLRS == 2) {
> +		pdev1 = platform_device_register_full(&edma_dev_info1);
> +		if (IS_ERR(pdev1)) {
> +			platform_driver_unregister(&edma_driver);
> +			platform_device_unregister(pdev0);
> +			ret = PTR_ERR(pdev1);
> +		}
> +	}
> +
> +out:
> +	return ret;
> +}
> +subsys_initcall(edma_init);
> +
> +static void __exit edma_exit(void)
> +{
> +	platform_device_unregister(pdev0);
> +	if (pdev1)
> +		platform_device_unregister(pdev1);
> +	platform_driver_unregister(&edma_driver);
> +}
> +module_exit(edma_exit);
> +
> +MODULE_AUTHOR("Matt Porter <mporter at ti.com>");
> +MODULE_DESCRIPTION("TI EDMA DMA engine driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/edma.h b/include/linux/edma.h
> new file mode 100644
> index 0000000..a1307e7
> --- /dev/null
> +++ b/include/linux/edma.h
> @@ -0,0 +1,29 @@
> +/*
> + * TI EDMA DMA engine driver
> + *
> + * Copyright 2012 Texas Instruments
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __LINUX_EDMA_H
> +#define __LINUX_EDMA_H
> +
> +struct dma_chan;
> +
> +#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
> +bool edma_filter_fn(struct dma_chan *, void *);
> +#else
> +static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
> +{
> +	return false;
> +}
> +#endif
> +
> +#endif
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> 


Regards, 
Gururaja


From hdoyu at nvidia.com  Wed Aug 22 08:52:28 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 14:52:28 +0200
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool
 with GFP_ATOMIC
In-Reply-To: <005a01cd8061$d58998c0$809cca40$%szyprowski@samsung.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com><1345630830-9586-3-git-send-email-hdoyu@nvidia.com><005a01cd8061$d58998c0$809cca40$%szyprowski@samsung.com>
Message-ID: <20120822.155228.1203479129187316092.hdoyu@nvidia.com>

Marek Szyprowski <m.szyprowski at samsung.com> wrote @ Wed, 22 Aug 2012 14:29:47 +0200:

> Hello,
> 
> On Wednesday, August 22, 2012 12:20 PM Hiroshi Doyu wrote:
> 
> > Makes use of the same atomic pool from DMA, and skips kernel page
> > mapping which can involves sleep'able operation at allocating a kernel
> > page table.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> > ---
> >  arch/arm/mm/dma-mapping.c |   22 ++++++++++++++++++----
> >  1 files changed, 18 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> > index aec0c06..9260107 100644
> > --- a/arch/arm/mm/dma-mapping.c
> > +++ b/arch/arm/mm/dma-mapping.c
> > @@ -1028,7 +1028,6 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> > size,
> >  	struct page **pages;
> >  	int count = size >> PAGE_SHIFT;
> >  	int array_size = count * sizeof(struct page *);
> > -	int err;
> > 
> >  	if (array_size <= PAGE_SIZE)
> >  		pages = kzalloc(array_size, gfp);
> > @@ -1037,9 +1036,20 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> > size,
> >  	if (!pages)
> >  		return NULL;
> > 
> > -	err = __alloc_fill_pages(&pages, count, gfp);
> > -	if (err)
> > -		goto error
> > +	if (gfp & GFP_ATOMIC) {
> > +		struct page *page;
> > +		int i;
> > +		void *addr = __alloc_from_pool(size, &page);
> > +		if (!addr)
> > +			goto err_out;
> > +
> > +		for (i = 0; i < count; i++)
> > +			pages[i] = page + i;
> > +	} else {
> > +		int err = __alloc_fill_pages(&pages, count, gfp);
> > +		if (err)
> > +			goto error;
> > +	}
> > 
> >  	return pages;
> >  error:
> > @@ -1055,6 +1065,10 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages,
> > size_t s
> >  	int count = size >> PAGE_SHIFT;
> >  	int array_size = count * sizeof(struct page *);
> >  	int i;
> > +
> > +	if (__free_from_pool(page_address(pages[0]), size))
> > +		return 0;
> 
> You leak memory here. pages array should be also freed.

Right, I'll fix as below:

	Modified arch/arm/mm/dma-mapping.c
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 47c4978..4656c0f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1121,11 +1121,12 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
 	int i;
 
 	if (__free_from_pool(page_address(pages[0]), size))
-		return 0;
+		goto out;
 
 	for (i = 0; i < count; i++)
 		if (pages[i])
 			__free_pages(pages[i], 0);
+out:
 	if (array_size <= PAGE_SIZE)
 		kfree(pages);
 	else


From kishon at ti.com  Wed Aug 22 08:59:49 2012
From: kishon at ti.com (ABRAHAM, KISHON VIJAY)
Date: Wed, 22 Aug 2012 18:29:49 +0530
Subject: [RESEND PATCH v4 0/2] omap: add ocp2scp as a bus driver
In-Reply-To: <201208221234.31193.arnd@arndb.de>
References: <1345624803-16379-1-git-send-email-kishon@ti.com>
 <201208221234.31193.arnd@arndb.de>
Message-ID: <CAAe_U6+8zF=Xd5RNDo0_DetYdatyaMS+JnOgmzL6FouW0Vo0og@mail.gmail.com>

On Wed, Aug 22, 2012 at 6:04 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 22 August 2012, Kishon Vijay Abraham I wrote:
>> This patch series has been lying here for long. If no one has any
>> comments on this patch series, can someone pick it up?
>
> I've added them now as a drivers/ocp2scp branch arm-soc and pulled
> them into the next/drivers topic branch.

Thanks Arnd :-)

-Kishon


From arnd at arndb.de  Wed Aug 22 08:56:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 12:56:35 +0000
Subject: [PATCH 2/4] [RFC] ARM: mass move of mach-*/plat-* header files
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <201208221256.35657.arnd@arndb.de>

This moves all <mach/*.h> headers to <mach-*/*.h>, and all
<plat/*.h> headers to <plat-*/*.h>, as another step closer
to building kernels for multiple platforms combined.

A script to generate headers with the traditional names including
the headers from the new place is already there, so this move
should be completely transparent.

This patch was created fully automated by a script and
should be redone if the headers change. Note that the
plat-mxc headers move to mach-imx in the process because
they don't follow the <plat/foo.h> naming convention:

for i in arch/arm/mach-* ; do git mv $i/include/mach $i/include/${i##*/} ; done
for i in arch/arm/plat-* ; do git mv $i/include/plat $i/include/${i##*/} ; done
git mv arch/arm/plat-mxc/include/mach/*.h arch/arm/mach-imx/include/mach-imx/

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
   2.1% arch/arm/mach-at91/include/mach-at91/
   2.1% arch/arm/mach-at91/include/mach/
   3.1% arch/arm/mach-bcmring/include/mach-bcmring/csp/
   0.6% arch/arm/mach-bcmring/include/mach-bcmring/
   3.1% arch/arm/mach-bcmring/include/mach/csp/
   0.6% arch/arm/mach-bcmring/include/mach/
   0.3% arch/arm/mach-clps711x/include/mach-clps711x/
   0.3% arch/arm/mach-clps711x/include/mach/
   0.3% arch/arm/mach-cns3xxx/include/mach-cns3xxx/
   0.3% arch/arm/mach-cns3xxx/include/mach/
   1.2% arch/arm/mach-davinci/include/mach-davinci/
   1.2% arch/arm/mach-davinci/include/mach/
   0.1% arch/arm/mach-dove/include/mach-dove/
   0.1% arch/arm/mach-dove/include/mach/
   0.0% arch/arm/mach-ebsa110/include/mach-ebsa110/
   0.0% arch/arm/mach-ebsa110/include/mach/
   0.2% arch/arm/mach-ep93xx/include/mach-ep93xx/
   0.2% arch/arm/mach-ep93xx/include/mach/
   1.1% arch/arm/mach-exynos/include/mach-exynos/
   1.1% arch/arm/mach-exynos/include/mach/
   0.1% arch/arm/mach-footbridge/include/mach-footbridge/
   0.1% arch/arm/mach-footbridge/include/mach/
   0.2% arch/arm/mach-gemini/include/mach-gemini/
   0.2% arch/arm/mach-gemini/include/mach/
   0.2% arch/arm/mach-h720x/include/mach-h720x/
   0.2% arch/arm/mach-h720x/include/mach/
   0.0% arch/arm/mach-highbank/include/mach-highbank/
   0.0% arch/arm/mach-highbank/include/mach/
   7.5% arch/arm/mach-imx/include/mach-imx/
   0.0% arch/arm/mach-imx/include/mach/
   0.3% arch/arm/mach-integrator/include/mach-integrator/
   0.3% arch/arm/mach-integrator/include/mach/
   0.6% arch/arm/mach-iop13xx/include/mach-iop13xx/
   0.6% arch/arm/mach-iop13xx/include/mach/
   0.0% arch/arm/mach-iop32x/include/mach-iop32x/
   0.0% arch/arm/mach-iop32x/include/mach/
   0.0% arch/arm/mach-iop33x/include/mach-iop33x/
   0.0% arch/arm/mach-iop33x/include/mach/
   0.7% arch/arm/mach-ixp4xx/include/mach-ixp4xx/
   0.7% arch/arm/mach-ixp4xx/include/mach/
   0.1% arch/arm/mach-kirkwood/include/mach-kirkwood/
   0.1% arch/arm/mach-kirkwood/include/mach/
   0.4% arch/arm/mach-ks8695/include/mach-ks8695/
   0.4% arch/arm/mach-ks8695/include/mach/
   0.0% arch/arm/mach-l7200/include/mach-l7200/
   0.0% arch/arm/mach-l7200/include/mach/
   0.4% arch/arm/mach-lpc32xx/include/mach-lpc32xx/
   0.4% arch/arm/mach-lpc32xx/include/mach/
   1.0% arch/arm/mach-mmp/include/mach-mmp/
   1.0% arch/arm/mach-mmp/include/mach/
   1.9% arch/arm/mach-msm/include/mach-msm/
   1.9% arch/arm/mach-msm/include/mach/
   0.1% arch/arm/mach-mv78xx0/include/mach-mv78xx0/
   0.1% arch/arm/mach-mv78xx0/include/mach/
   0.0% arch/arm/mach-mvebu/include/mach-mvebu/
   0.0% arch/arm/mach-mvebu/include/mach/
   1.2% arch/arm/mach-mxs/include/mach-mxs/
   1.2% arch/arm/mach-mxs/include/mach/
   0.3% arch/arm/mach-netx/include/mach-netx/
   0.3% arch/arm/mach-netx/include/mach/
   0.1% arch/arm/mach-nomadik/include/mach-nomadik/
   0.1% arch/arm/mach-nomadik/include/mach/
   0.2% arch/arm/mach-omap1/include/mach-omap1/
   0.2% arch/arm/mach-omap1/include/mach/
   1.3% arch/arm/mach-omap2/include/mach-omap2/
   1.3% arch/arm/mach-omap2/include/mach/
   0.1% arch/arm/mach-orion5x/include/mach-orion5x/
   0.1% arch/arm/mach-orion5x/include/mach/
   0.0% arch/arm/mach-picoxcell/include/mach-picoxcell/
   0.0% arch/arm/mach-picoxcell/include/mach/
   0.4% arch/arm/mach-pnx4008/include/mach-pnx4008/
   0.4% arch/arm/mach-pnx4008/include/mach/
   0.0% arch/arm/mach-prima2/include/mach-prima2/
   0.0% arch/arm/mach-prima2/include/mach/
   4.2% arch/arm/mach-pxa/include/mach-pxa/
   4.2% arch/arm/mach-pxa/include/mach/
   0.7% arch/arm/mach-realview/include/mach-realview/
   0.7% arch/arm/mach-realview/include/mach/
   0.1% arch/arm/mach-rpc/include/mach-rpc/
   0.1% arch/arm/mach-rpc/include/mach/
   1.4% arch/arm/mach-s3c24xx/include/mach-s3c24xx/
   1.4% arch/arm/mach-s3c24xx/include/mach/
   0.5% arch/arm/mach-s3c64xx/include/mach-s3c64xx/
   0.5% arch/arm/mach-s3c64xx/include/mach/
   0.3% arch/arm/mach-s5p64x0/include/mach-s5p64x0/
   0.3% arch/arm/mach-s5p64x0/include/mach/
   0.2% arch/arm/mach-s5pc100/include/mach-s5pc100/
   0.2% arch/arm/mach-s5pc100/include/mach/
   0.3% arch/arm/mach-s5pv210/include/mach-s5pv210/
   0.3% arch/arm/mach-s5pv210/include/mach/
   2.0% arch/arm/mach-sa1100/include/mach-sa1100/
   2.0% arch/arm/mach-sa1100/include/mach/
   0.0% arch/arm/mach-shark/include/mach-shark/
   0.0% arch/arm/mach-shark/include/mach/
   1.5% arch/arm/mach-shmobile/include/mach-shmobile/
   1.5% arch/arm/mach-shmobile/include/mach/
   0.0% arch/arm/mach-socfpga/include/mach-socfpga/
   0.0% arch/arm/mach-socfpga/include/mach/
   0.1% arch/arm/mach-spear13xx/include/mach-spear13xx/
   0.1% arch/arm/mach-spear13xx/include/mach/
   0.0% arch/arm/mach-spear3xx/include/mach-spear3xx/
   0.0% arch/arm/mach-spear3xx/include/mach/
   0.0% arch/arm/mach-spear6xx/include/mach-spear6xx/
   0.0% arch/arm/mach-spear6xx/include/mach/
   0.5% arch/arm/mach-tegra/include/mach-tegra/
   0.5% arch/arm/mach-tegra/include/mach/
   0.5% arch/arm/mach-u300/include/mach-u300/
   0.5% arch/arm/mach-u300/include/mach/
   0.3% arch/arm/mach-ux500/include/mach-ux500/
   0.3% arch/arm/mach-ux500/include/mach/
   0.3% arch/arm/mach-versatile/include/mach-versatile/
   0.3% arch/arm/mach-versatile/include/mach/
   0.1% arch/arm/mach-vexpress/include/mach-vexpress/
   0.1% arch/arm/mach-vexpress/include/mach/
   0.2% arch/arm/mach-vt8500/include/mach-vt8500/
   0.2% arch/arm/mach-vt8500/include/mach/
   0.3% arch/arm/mach-w90x900/include/mach-w90x900/
   0.3% arch/arm/mach-w90x900/include/mach/
   0.0% arch/arm/mach-zynq/include/mach-zynq/
   0.0% arch/arm/mach-zynq/include/mach/
   7.5% arch/arm/plat-mxc/include/mach/
   0.2% arch/arm/plat-nomadik/include/plat-nomadik/
   0.2% arch/arm/plat-nomadik/include/plat/
   3.5% arch/arm/plat-omap/include/plat-omap/
   3.5% arch/arm/plat-omap/include/plat/
   0.1% arch/arm/plat-orion/include/plat-orion/
   0.1% arch/arm/plat-orion/include/plat/
   0.2% arch/arm/plat-pxa/include/plat-pxa/
   0.2% arch/arm/plat-pxa/include/plat/
   2.8% arch/arm/plat-samsung/include/plat-samsung/
   2.8% arch/arm/plat-samsung/include/plat/
   0.1% arch/arm/plat-spear/include/plat-spear/
   0.1% arch/arm/plat-spear/include/plat/
   0.0% arch/arm/plat-versatile/include/plat-versatile/
   0.0% arch/arm/plat-versatile/include/plat/

diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach-at91/at91_adc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_adc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_adc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach-at91/at91_aic.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_aic.h
rename to arch/arm/mach-at91/include/mach-at91/at91_aic.h
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_dbgu.h
rename to arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach-at91/at91_matrix.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_matrix.h
rename to arch/arm/mach-at91/include/mach-at91/at91_matrix.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach-at91/at91_pio.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pio.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pio.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach-at91/at91_pit.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pit.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pit.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach-at91/at91_pmc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pmc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_ramc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_ramc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach-at91/at91_rstc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rstc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rstc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach-at91/at91_rtc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach-at91/at91_rtt.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtt.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtt.h
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_shdwc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach-at91/at91_st.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_st.h
rename to arch/arm/mach-at91/include/mach-at91/at91_st.h
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach-at91/at91_tc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_tc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_tc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach-at91/at91_twi.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_twi.h
rename to arch/arm/mach-at91/include/mach-at91/at91_twi.h

Cut here for review purposes. None of the other file renames have any
other changes, so there is no point spamming the mailing lists with
this. The full patch is available at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=62dd65e1ac307d2ba15f31cc2f754b8e348055c7



From arnd at arndb.de  Wed Aug 22 09:01:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 13:01:19 +0000
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <201208221301.19439.arnd@arndb.de>

These are lots of device drivers that include machine
specific header files from ARM platforms and that are
not easily scriptable. The changes have been found through
manual inspection and should cause no visible changes
because of the build script that maps the old names to the
new ones.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/char/ds1620.c                                 |    2 +-
 drivers/char/hw_random/ixp4xx-rng.c                   |    2 +-
 drivers/cpufreq/db8500-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos4210-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos4x12-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos5250-cpufreq.c                  |    6 +++---
 drivers/cpufreq/omap-cpufreq.c                        |    2 +-
 drivers/cpufreq/s5pv210-cpufreq.c                     |    2 +-
 drivers/crypto/omap-sham.c                            |    2 +-
 drivers/crypto/tegra-aes.c                            |    2 +-
 drivers/devfreq/exynos4_bus.c                         |    2 +-
 drivers/dma/ep93xx_dma.c                              |    2 +-
 drivers/dma/imx-dma.c                                 |    4 ++--
 drivers/gpio/gpio-omap.c                              |    4 ++--
 drivers/gpio/gpio-pxa.c                               |    8 +++++++-
 drivers/i2c/busses/i2c-acorn.c                        |    2 +-
 drivers/i2c/busses/i2c-davinci.c                      |    4 ++--
 drivers/i2c/busses/i2c-imx.c                          |    4 ++--
 drivers/i2c/busses/i2c-nuc900.c                       |    4 ++--
 drivers/i2c/busses/i2c-tegra.c                        |    2 +-
 drivers/input/misc/ixp4xx-beeper.c                    |    2 +-
 drivers/input/mouse/rpcmouse.c                        |    2 +-
 drivers/input/serio/rpckbd.c                          |    2 +-
 drivers/input/touchscreen/atmel_tsadcc.c              |    4 ++--
 drivers/input/touchscreen/h3600_ts_input.c            |    4 ++--
 drivers/input/touchscreen/mainstone-wm97xx.c          |    2 +-
 drivers/input/touchscreen/zylonite-wm97xx.c           |    6 +++---
 drivers/leds/leds-fsg.c                               |    2 +-
 drivers/media/video/pxa_camera.c                      |    4 ++--
 drivers/mfd/dbx500-prcmu-regs.h                       |    2 +-
 drivers/misc/ep93xx_pwm.c                             |    2 +-
 drivers/misc/spear13xx_pcie_gadget.c                  |    4 ++--
 drivers/mmc/host/at91_mci.c                           |    4 ++--
 drivers/mmc/host/mxcmmc.c                             |    6 +++---
 drivers/mmc/host/omap_hsmmc.c                         |    2 +-
 drivers/mmc/host/pxamci.c                             |    6 +++---
 drivers/mtd/maps/cdb89712.c                           |    2 +-
 drivers/mtd/maps/h720x-flash.c                        |    2 +-
 drivers/mtd/maps/pxa2xx-flash.c                       |    2 +-
 drivers/mtd/maps/sa1100-flash.c                       |    2 +-
 drivers/mtd/nand/ams-delta.c                          |    2 +-
 drivers/mtd/nand/sharpsl.c                            |    2 +-
 drivers/net/can/at91_can.c                            |    2 +-
 drivers/net/ethernet/amd/am79c961a.c                  |    2 +-
 drivers/net/ethernet/cirrus/ep93xx_eth.c              |    2 +-
 drivers/net/ethernet/nxp/lpc_eth.c                    |    6 +++---
 drivers/net/ethernet/smsc/smc911x.h                   |    2 +-
 drivers/net/ethernet/smsc/smc91x.h                    |    2 +-
 drivers/net/irda/ep7211-sir.c                         |    2 +-
 drivers/net/irda/pxaficp_ir.c                         |    8 ++++----
 drivers/net/irda/sa1100_ir.c                          |    2 +-
 drivers/pcmcia/omap_cf.c                              |    2 +-
 drivers/pcmcia/pxa2xx_cm_x2xx.c                       |    2 +-
 drivers/pcmcia/sa1111_jornada720.c                    |    2 +-
 drivers/pcmcia/sa11xx_base.c                          |    2 +-
 drivers/power/avs/smartreflex.c                       |    1 +
 drivers/pwm/pwm-imx.c                                 |    2 +-
 drivers/rtc/rtc-mxc.c                                 |    2 +-
 drivers/rtc/rtc-pxa.c                                 |    2 +-
 drivers/rtc/rtc-stmp3xxx.c                            |    2 +-
 drivers/scsi/arm/acornscsi-io.S                       |    2 +-
 drivers/spi/spi-imx.c                                 |    2 +-
 drivers/spi/spi-omap-uwire.c                          |    2 +-
 drivers/spi/spi-s3c24xx-fiq.S                         |    4 ++--
 drivers/spi/spi-tegra.c                               |    2 +-
 drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c |    4 ++--
 drivers/tty/serial/21285.c                            |    2 +-
 drivers/tty/serial/atmel_serial.c                     |    6 ++++--
 drivers/tty/serial/clps711x.c                         |    2 +-
 drivers/tty/serial/msm_serial_hs.c                    |    4 ++--
 drivers/tty/serial/sa1100.c                           |    4 ++--
 drivers/tty/serial/serial_ks8695.c                    |    4 ++--
 drivers/uio/uio_pruss.c                               |    2 +-
 drivers/usb/gadget/fsl_mxc_udc.c                      |    2 +-
 drivers/usb/gadget/imx_udc.c                          |    4 ++--
 drivers/usb/gadget/pxa27x_udc.c                       |    4 ++--
 drivers/usb/host/ohci-at91.c                          |    6 +++---
 drivers/usb/host/ohci-exynos.c                        |    2 +-
 drivers/usb/musb/davinci.c                            |    4 ++--
 drivers/usb/musb/ux500_dma.c                          |    2 +-
 drivers/usb/otg/msm_otg.c                             |    2 +-
 drivers/video/backlight/omap1_bl.c                    |    2 +-
 drivers/video/ep93xx-fb.c                             |    2 +-
 drivers/video/nuc900fb.h                              |    4 ++--
 drivers/video/pnx4008/dum.h                           |    2 +-
 drivers/w1/masters/omap_hdq.c                         |    2 +-
 drivers/watchdog/imx2_wdt.c                           |    2 +-
 drivers/watchdog/ixp4xx_wdt.c                         |    2 +-
 drivers/watchdog/ks8695_wdt.c                         |    4 ++--
 drivers/watchdog/wdt285.c                             |    2 +-
 91 files changed, 137 insertions(+), 128 deletions(-)

diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index aab9605..b4c21b1 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <asm/therm.h>
diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c
index 263567f..42889bb 100644
--- a/drivers/char/hw_random/ixp4xx-rng.c
+++ b/drivers/char/hw_random/ixp4xx-rng.c
@@ -23,7 +23,7 @@
 #include <linux/hw_random.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 
 static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer)
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
index 74b830b..c771360 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -13,7 +13,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/mfd/dbx500-prcmu.h>
-#include <mach/id.h>
+#include <mach-ux500/id.h>
 
 static struct cpufreq_frequency_table freq_table[] = {
        [0] = {
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 9382a6b..637782b 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -18,7 +18,7 @@
 #include <linux/cpufreq.h>
 #include <linux/suspend.h>
 
-#include <mach/cpufreq.h>
+#include <mach-exynos/cpufreq.h>
 
 #include <plat-samsung/cpu.h>
 
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index fb148fa..33d3d4c 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END      L5
 
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8c5a7af..e7aa354 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END      (L13 + 1)
 
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index e64c253..74950a3 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -17,9 +17,9 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/map.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END      (L15 + 1)
 
diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 4449907..45b2331 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -35,7 +35,7 @@
 #include <plat-omap/common.h>
 #include <plat-omap/omap_device.h>
 
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 /* OPP tolerance in percentage */
 #define        OPP_TOLERANCE   4
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index a484aae..04dfc10 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -20,7 +20,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/suspend.h>
 
-#include <mach/map.h>
+#include <mach-s5pv210/map.h>
 #include <mach/regs-clock.h>
 
 static struct clk *cpu_clk;
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 737afed..98e877d 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -39,7 +39,7 @@
 
 #include <plat-omap/cpu.h>
 #include <plat-omap/dma.h>
-#include <mach/irqs.h>
+#include <mach-omap2/irqs.h>
 
 #define SHA_REG_DIGEST(x)              (0x00 + ((x) * 0x04))
 #define SHA_REG_DIN(x)                 (0x1C + ((x) * 0x04))
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index ac236f6..971bd27 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -41,7 +41,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #include <crypto/scatterwalk.h>
 #include <crypto/aes.h>
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index c8af6d4..e8d7ce8 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -30,7 +30,7 @@
 extern unsigned int exynos_result_of_asv;
 #endif
 
-#include <mach/regs-clock.h>
+#include <mach-exynos/regs-clock.h>
 
 #include <plat-samsung/map-s5p.h>
 
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index c64917e..09d7112 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/dma.h>
+#include <mach-ep93xx/dma.h>
 
 #include "dmaengine.h"
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fcfeb3c..0597cbc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -28,8 +28,8 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #include "dmaengine.h"
 #define IMXDMA_MAX_CHAN_DESCRIPTORS    16
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..45592ca 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -26,9 +26,9 @@
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <asm/irq.h>
-#include <mach/irqs.h>
+#include <plat-omap/irqs.h>
 #include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 58a6a63..c6440a5 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,7 +26,13 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
+#ifdef CONFIG_ARCH_PXA
+#include <mach-pxa/irqs.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+#include <mach-mmp/irqs.h>
+#endif
 
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index ed9f48d..4d0f7797 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -17,7 +17,7 @@
 #include <linux/i2c-algo-bit.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/ioc.h>
 
 #define FORCE_ONES     0xdc
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 79b4bcb..d163b73 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -39,8 +39,8 @@
 #include <linux/cpufreq.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/i2c.h>
 
 /* ----- global defines ----------------------------------------------- */
 
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0722f86..a8ffc39 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -53,8 +53,8 @@
 #include <linux/of_i2c.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-imx/hardware.h>
+#include <mach-imx/i2c.h>
 
 /** Defines ********************************************************************
 *******************************************************************************/
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
index a26dfb8..cfe6803 100644
--- a/drivers/i2c/busses/i2c-nuc900.c
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -28,8 +28,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 
-#include <mach/mfp.h>
-#include <mach/i2c.h>
+#include <mach-w90x900/mfp.h>
+#include <mach-w90x900/i2c.h>
 
 /* nuc900 i2c registers offset */
 
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 66eb53f..8712414 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -31,7 +31,7 @@
 
 #include <asm/unaligned.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 #define BYTES_PER_FIFO_WORD 4
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
index 50e2830..9b644e1 100644
--- a/drivers/input/misc/ixp4xx-beeper.c
+++ b/drivers/input/misc/ixp4xx-beeper.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 MODULE_AUTHOR("Alessandro Zummo <a.zummo at towertech.it>");
 MODULE_DESCRIPTION("ixp4xx beeper driver");
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 272dedd..41c1fa4 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -24,7 +24,7 @@
 #include <linux/input.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/iomd.h>
 
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index 2af5df6..5bee7e0 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/iomd.h>
 
 MODULE_AUTHOR("Vojtech Pavlik, Russell King");
diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
index 201b2d2..00f8aac 100644
--- a/drivers/input/touchscreen/atmel_tsadcc.c
+++ b/drivers/input/touchscreen/atmel_tsadcc.c
@@ -22,8 +22,8 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 /* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
 
diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
index b9e8686..39a0ce5 100644
--- a/drivers/input/touchscreen/h3600_ts_input.c
+++ b/drivers/input/touchscreen/h3600_ts_input.c
@@ -39,8 +39,8 @@
 #include <linux/delay.h>
 
 /* SA1100 serial defines */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 
 #define DRIVER_DESC    "H3600 touchscreen driver"
 
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index 7d2b213..997e627 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -33,7 +33,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <mach/regs-ac97.h>
+#include <mach-pxa/regs-ac97.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/input/touchscreen/zylonite-wm97xx.c b/drivers/input/touchscreen/zylonite-wm97xx.c
index bf0869a7..be59125 100644
--- a/drivers/input/touchscreen/zylonite-wm97xx.c
+++ b/drivers/input/touchscreen/zylonite-wm97xx.c
@@ -28,9 +28,9 @@
 #include <linux/io.h>
 #include <linux/wm97xx.h>
 
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/regs-ac97.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/mfp.h>
+#include <mach-pxa/regs-ac97.h>
 
 struct continuous {
        u16 id;    /* codec id */
diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c
index b9053fa..683b01d 100644
--- a/drivers/leds/leds-fsg.c
+++ b/drivers/leds/leds-fsg.c
@@ -20,7 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/module.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 #include <asm/io.h>
 
 #define FSG_LED_WLAN_BIT       0
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 9c21e01..0d76655 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -36,8 +36,8 @@
 
 #include <linux/videodev2.h>
 
-#include <mach/dma.h>
-#include <mach/camera.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/camera.h>
 
 #define PXA_CAM_VERSION "0.0.6"
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6..7de55f8 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -13,7 +13,7 @@
 #ifndef __DB8500_PRCMU_REGS_H
 #define __DB8500_PRCMU_REGS_H
 
-#include <mach/hardware.h>
+#include <mach-ux500/hardware.h>
 
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
 
diff --git a/drivers/misc/ep93xx_pwm.c b/drivers/misc/ep93xx_pwm.c
index 16d7179..a996270 100644
--- a/drivers/misc/ep93xx_pwm.c
+++ b/drivers/misc/ep93xx_pwm.c
@@ -24,7 +24,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <mach/platform.h>
+#include <mach-ep93xx/platform.h>
 
 #define EP93XX_PWMx_TERM_COUNT 0x00
 #define EP93XX_PWMx_DUTY_CYCLE 0x04
diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c
index 123ed98..0a32042 100644
--- a/drivers/misc/spear13xx_pcie_gadget.c
+++ b/drivers/misc/spear13xx_pcie_gadget.c
@@ -20,8 +20,8 @@
 #include <linux/platform_device.h>
 #include <linux/pci_regs.h>
 #include <linux/configfs.h>
-#include <mach/pcie.h>
-#include <mach/misc_regs.h>
+#include <mach-spear13xx/pcie.h>
+#include <mach-spear13xx/misc_regs.h>
 
 #define IN0_MEM_SIZE   (200 * 1024 * 1024 - 1)
 /* In current implementation address translation is done using IN0 only.
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index efdb81d..ec7f665 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -75,8 +75,8 @@
 #include <asm/irq.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #include "at91_mci.h"
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 28ed52d..dec1bb1 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -38,10 +38,10 @@
 #include <asm/dma.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <mach/mmc.h>
+#include <mach-imx/mmc.h>
 
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "mxc-mmc"
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 198066c..194bc04 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -39,7 +39,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mmc.h>
 #include <plat-omap/cpu.h>
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e..8b01058 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -33,9 +33,9 @@
 
 #include <asm/sizes.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <mach/mmc.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/mmc.h>
 
 #include "pxamci.h"
 
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
index c29cbf8..c224dd4 100644
--- a/drivers/mtd/maps/cdb89712.c
+++ b/drivers/mtd/maps/cdb89712.c
@@ -9,7 +9,7 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c
index 8ed6cb4..3206fef 100644
--- a/drivers/mtd/maps/h720x-flash.c
+++ b/drivers/mtd/maps/h720x-flash.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
-#include <mach/hardware.h>
+#include <mach-h720x/hardware.h>
 #include <asm/io.h>
 
 static struct mtd_info *mymtd;
diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index 81884c2..8a82445 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -20,7 +20,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c
index a675bdb..2f234e6 100644
--- a/drivers/mtd/maps/sa1100-flash.c
+++ b/drivers/mtd/maps/sa1100-flash.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/concat.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 1386f6b..7a921a1 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -24,7 +24,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/sizes.h>
 #include <linux/gpio.h>
 #include <plat-omap/board-ams-delta.h>
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
index 3421e37..866aaac 100644
--- a/drivers/mtd/nand/sharpsl.c
+++ b/drivers/mtd/nand/sharpsl.c
@@ -25,7 +25,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 #include <asm/mach-types.h>
 
 struct sharpsl_nand {
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index fcff73a..8f14511 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -37,7 +37,7 @@
 #include <linux/can/dev.h>
 #include <linux/can/error.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 #define AT91_MB_MASK(i)                ((1 << (i)) - 1)
 
diff --git a/drivers/net/ethernet/amd/am79c961a.c b/drivers/net/ethernet/amd/am79c961a.c
index e10ffad..89746bf 100644
--- a/drivers/net/ethernet/amd/am79c961a.c
+++ b/drivers/net/ethernet/amd/am79c961a.c
@@ -29,7 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-ebsa110/hardware.h>
 
 #define TX_BUFFERS 15
 #define RX_BUFFERS 25
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..7ad8b0d 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -26,7 +26,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-ep93xx/hardware.h>
 
 #define DRV_MODULE_NAME                "ep93xx-eth"
 #define DRV_MODULE_VERSION     "0.1"
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 4069eda..5be01c0 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -45,9 +45,9 @@
 #include <linux/types.h>
 
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
+#include <mach-lpc32xx/board.h>
+#include <mach-lpc32xx/platform.h>
+#include <mach-lpc32xx/hardware.h>
 
 #define MODNAME "lpc-eth"
 #define DRV_VERSION "1.00"
diff --git a/drivers/net/ethernet/smsc/smc911x.h b/drivers/net/ethernet/smsc/smc911x.h
index 3269292..80eb9d0 100644
--- a/drivers/net/ethernet/smsc/smc911x.h
+++ b/drivers/net/ethernet/smsc/smc911x.h
@@ -211,7 +211,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 
 #ifdef SMC_USE_PXA_DMA
 
-#include <mach/dma.h>
+#include <mach-pxa/dma.h>
 
 /*
  * Define the request and free functions
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
index 7f4beeb..754af90 100644
--- a/drivers/net/ethernet/smsc/smc91x.h
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -364,7 +364,7 @@ struct smc_local {
  * as RX which can overrun memory and lose packets.
  */
 #include <linux/dma-mapping.h>
-#include <mach-sa1100/dma.h>
+#include <mach-pxa/dma.h>
 
 #ifdef SMC_insl
 #undef SMC_insl
diff --git a/drivers/net/irda/ep7211-sir.c b/drivers/net/irda/ep7211-sir.c
index f83c5b8..8f8d91c 100644
--- a/drivers/net/irda/ep7211-sir.c
+++ b/drivers/net/irda/ep7211-sir.c
@@ -14,7 +14,7 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 #include "sir-dev.h"
 
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8d54767..86073eb 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -27,10 +27,10 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/dma.h>
-#include <mach/irda.h>
-#include <mach/regs-uart.h>
-#include <mach/regs-ost.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/irda.h>
+#include <mach-pxa/regs-uart.h>
+#include <mach-pxa/regs-ost.h>
 
 #define FICP           __REG(0x40800000)  /* Start of FICP area */
 #define ICCR0          __REG(0x40800000)  /* ICP Control Register 0 */
diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
index e250675..3f88a39 100644
--- a/drivers/net/irda/sa1100_ir.c
+++ b/drivers/net/irda/sa1100_ir.c
@@ -37,7 +37,7 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/mach/irda.h>
 
 static int power_level = 3;
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index adb5b1e..070eaa6 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -20,7 +20,7 @@
 
 #include <pcmcia/ss.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 
diff --git a/drivers/pcmcia/pxa2xx_cm_x2xx.c b/drivers/pcmcia/pxa2xx_cm_x2xx.c
index 6e7dcfd..61097ba 100644
--- a/drivers/pcmcia/pxa2xx_cm_x2xx.c
+++ b/drivers/pcmcia/pxa2xx_cm_x2xx.c
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 int cmx255_pcmcia_init(void);
 int cmx270_pcmcia_init(void);
diff --git a/drivers/pcmcia/sa1111_jornada720.c b/drivers/pcmcia/sa1111_jornada720.c
index 69428d1..86fc717 100644
--- a/drivers/pcmcia/sa1111_jornada720.c
+++ b/drivers/pcmcia/sa1111_jornada720.c
@@ -10,7 +10,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c
index 6eecd7c..2d689b2 100644
--- a/drivers/pcmcia/sa11xx_base.c
+++ b/drivers/pcmcia/sa11xx_base.c
@@ -39,7 +39,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/irq.h>
 
 #include "soc_common.h"
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..af502d1 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <linux/power/smartreflex.h>
+#include <plat-omap/cpu.h>
 
 #define SMARTREFLEX_NAME_LEN   16
 #define NVALUE_NAME_LEN                40
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..68ff175 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -16,7 +16,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pwm.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 
 /* i.MX1 and i.MX21 share the same PWM function block: */
diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
index e3e50d6..eb4d40e 100644
--- a/drivers/rtc/rtc-mxc.c
+++ b/drivers/rtc/rtc-mxc.c
@@ -17,7 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define RTC_INPUT_CLK_32768HZ  (0x00 << 5)
 #define RTC_INPUT_CLK_32000HZ  (0x01 << 5)
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8f..679ca79 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #define TIMER_FREQ             CLOCK_TICK_RATE
 #define RTC_DEF_DIVIDER                (32768 - 1)
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index 739ef556..9f7ff1d 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/of_device.h>
 
-#include <mach/common.h>
+#include <mach-mxs/common.h>
 
 #define STMP3XXX_RTC_CTRL                      0x0
 #define STMP3XXX_RTC_CTRL_SET                  0x4
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
index 22171b2..6395330 100644
--- a/drivers/scsi/arm/acornscsi-io.S
+++ b/drivers/scsi/arm/acornscsi-io.S
@@ -8,7 +8,7 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 
 #if defined(__APCS_32__)
 #define LOADREGS(t,r,l...)     ldm##t  r, l
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e834ff8..819ddf0 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -39,7 +39,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/spi.h>
+#include <mach-imx/spi.h>
 
 #define DRIVER_NAME "spi_imx"
 
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 177b6cf..dc2ad86 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -48,7 +48,7 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/spi/spi-s3c24xx-fiq.S b/drivers/spi/spi-s3c24xx-fiq.S
index 9718a11..44941ce 100644
--- a/drivers/spi/spi-s3c24xx-fiq.S
+++ b/drivers/spi/spi-s3c24xx-fiq.S
@@ -13,8 +13,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <mach/map.h>
-#include <mach/regs-irq.h>
+#include <mach-s3c24xx/map.h>
+#include <mach-s3c24xx/regs-irq.h>
 #include <plat-samsung/regs-spi.h>
 
 #include "spi-s3c24xx-fiq.h"
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c..77b2810 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -32,7 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/dmaengine.h>
 
-#include <mach/dma.h>
+#include <mach-tegra/dma.h>
 
 #define SLINK_COMMAND          0x000
 #define   SLINK_BIT_LENGTH(x)          (((x) & 0x1f) << 0)
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
index a272e48..1e4f493 100644
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
@@ -5,8 +5,8 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
+#include <mach-ux500/gpio.h>
+#include <mach-ux500/irqs.h>
 #include "synaptics_i2c_rmi4.h"
 
 /*
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index a44345a..8104b07 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #define BAUD_BASE              (mem_fclk_21285/64)
 
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee..ff99a33 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -44,11 +44,13 @@
 #include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
-#include <mach/board.h>
 
 #ifdef CONFIG_ARM
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 #include <asm/gpio.h>
+#else
+#include <mach/board.h>
 #endif
 
 #define PDC_BUFFER_SIZE                512
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
index d0f719f..e4dc87b 100644
--- a/drivers/tty/serial/clps711x.c
+++ b/drivers/tty/serial/clps711x.c
@@ -38,7 +38,7 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 
 #define UART_NR                2
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index fca13dc..949c9e6 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -51,8 +51,8 @@
 #include <linux/atomic.h>
 #include <asm/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
+#include <mach-msm/hardware.h>
+#include <mach-msm/dma.h>
 #include <linux/platform_data/msm_serial_hs.h>
 
 /* HSUART Registers */
diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
index 2ca5959..d5c47f6 100644
--- a/drivers/tty/serial/sa1100.c
+++ b/drivers/tty/serial/sa1100.c
@@ -37,8 +37,8 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 #include <asm/mach/serial_sa1100.h>
 
 /* We've been assigned a range on the "Low-density serial ports" major */
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 7c13639..f5c672c 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -25,8 +25,8 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <mach/regs-uart.h>
-#include <mach/regs-irq.h>
+#include <mach-ks8695/regs-uart.h>
+#include <mach-ks8695/regs-irq.h>
 
 #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 #define SUPPORT_SYSRQ
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
index 33a7a27..4bafe92 100644
--- a/drivers/uio/uio_pruss.c
+++ b/drivers/uio/uio_pruss.c
@@ -25,7 +25,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
-#include <mach/sram.h>
+#include <mach-davinci/sram.h>
 
 #define DRV_NAME "pruss_uio"
 #define DRV_VERSION "1.0"
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 1b0f086..fce80b3 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -18,7 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 static struct clk *mxc_ahb_clk;
 static struct clk *mxc_per_clk;
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index dc53348..476ac2b 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -35,8 +35,8 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
-#include <mach/usb.h>
-#include <mach/hardware.h>
+#include <mach-imx/usb.h>
+#include <mach-imx/hardware.h>
 
 #include "imx_udc.h"
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 644b430..d4ef1fe 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -26,12 +26,12 @@
 #include <linux/prefetch.h>
 
 #include <asm/byteorder.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-#include <mach/udc.h>
+#include <mach-pxa/udc.h>
 
 #include "pxa27x_udc.h"
 
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a665b3e..5add6ce 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -17,11 +17,11 @@
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #ifndef CONFIG_ARCH_AT91
 #error "CONFIG_ARCH_AT91 must be defined."
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 2dce0df..561f56a 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <mach/ohci.h>
+#include <mach-exynos/ohci.h>
 #include <plat-samsung/usb-phy.h>
 
 struct exynos_ohci_hcd {
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 472c8b4..2e8cfb8 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -34,8 +34,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/cputype.h>
-#include <mach/hardware.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/hardware.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index d05c7fb..7c92d86 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -30,7 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/pfn.h>
-#include <mach/usb.h>
+#include <mach-ux500/usb.h>
 #include "musb_core.h"
 
 struct ux500_dma_channel {
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 9f5fc90..e41e6c5 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -40,7 +40,7 @@
 #include <linux/usb/msm_hsusb_hw.h>
 #include <linux/regulator/consumer.h>
 
-#include <mach/clk.h>
+#include <mach-msm/clk.h>
 
 #define MSM_USB_BASE   (motg->regs)
 #define DRIVER_NAME    "msm_otg"
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index 1e39ae3..556b623 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -28,7 +28,7 @@
 #include <linux/backlight.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mux.h>
 
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 345d962..b58f5c5 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 
-#include <mach/fb.h>
+#include <mach-ep93xx/fb.h>
 
 /* Vertical Frame Timing Registers */
 #define EP93XXFB_VLINES_TOTAL                  0x0000  /* SW locked */
diff --git a/drivers/video/nuc900fb.h b/drivers/video/nuc900fb.h
index bc7c930..6f7f59a 100644
--- a/drivers/video/nuc900fb.h
+++ b/drivers/video/nuc900fb.h
@@ -15,8 +15,8 @@
 #ifndef __NUC900FB_H
 #define __NUC900FB_H
 
-#include <mach/map.h>
-#include <mach/fb.h>
+#include <mach-w90x900/map.h>
+#include <mach-w90x900/fb.h>
 
 enum nuc900_lcddrv_type {
        LCDDRV_NUC910,
diff --git a/drivers/video/pnx4008/dum.h b/drivers/video/pnx4008/dum.h
index 1234d43..ddae1c2 100644
--- a/drivers/video/pnx4008/dum.h
+++ b/drivers/video/pnx4008/dum.h
@@ -12,7 +12,7 @@
 #ifndef __PNX008_DUM_H__
 #define __PNX008_DUM_H__
 
-#include <mach/platform.h>
+#include <mach-pnx4008/platform.h>
 
 #define PNX4008_DUMCONF_VA_BASE                IO_ADDRESS(PNX4008_DUMCONF_BASE)
 #define PNX4008_DUM_MAIN_VA_BASE       IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 4b0fcf3..2d9cc12 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -19,7 +19,7 @@
 #include <linux/pm_runtime.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 #include "../w1.h"
 #include "../w1_int.h"
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index bcfab2b..f745c9b 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -33,7 +33,7 @@
 #include <linux/uaccess.h>
 #include <linux/timer.h>
 #include <linux/jiffies.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "imx2-wdt"
 
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index 5580b4f..913d480 100644
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -25,7 +25,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 static bool nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = 60;     /* (secs) Default is 1 minute */
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9..19c1dc1 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -23,8 +23,8 @@
 #include <linux/watchdog.h>
 #include <linux/io.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
-#include <mach/regs-timer.h>
+#include <mach-ks8695/hardware.h>
+#include <mach-ks8695/regs-timer.h>
 
 #define WDT_DEFAULT_TIME       5       /* seconds */
 #define WDT_MAX_TIME           171     /* seconds */
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index 5eec740..1e1c743 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -31,7 +31,7 @@
 #include <linux/interrupt.h>
 #include <linux/uaccess.h>
 #include <linux/irq.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
-- 


From arnd at arndb.de  Wed Aug 22 08:53:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 12:53:06 +0000
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
Message-ID: <201208221253.07278.arnd@arndb.de>

I've created this series some time ago, and updated it now to
v3.6-rc1. The idea is to get us a big step closer to the
single zImage kernel across multiple ARM platforms by
untangling the duplicate header file names.

There are two branches available in the arm-soc tree:

1. This series,
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
   This just moves header files around and changes most of the
   files including them. There are a few remaining drivers
   and platform files that keep including a generic file name
   like <mach/uncompress.h>. It remains possible to do that,
   and I've run extensive tests to ensure I did not break
   anything with this. However, each of these instances means
   that there is something that stops working when you get to
   the real multiplatform kernel and we still need to deal
   with them one by one.

2. Actually enabling CONFIG_ARCH_MULTIPLATFORM
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/multiplatform
   This builds on top of the first series, but is much more
   experimental. It shows how a multiplatform kernel can look
   like, by allowing to build vexpress, ux500, imx and omap2
   together in one kernel, but at the same time breaking some of
   their features.

I would like to get the first series merged in v3.7 if we can agree
on the general approach. So far, feedback in Linaro internal
meetings has been very positive, but Russell had concerns when
we first discussed it a few months ago.

A patch set this large means a lot of churn, and there are a few
ways we could deal with this:

a) Put the branch into linux-next now, and have everyone who
encounters conflicts pull it into their own branch to resolve
the conflicts. This can be a lot of work, and it means we
cannot rebase this branch any more.

b) Involve Linus Torvalds in the process and get him to
take the series at the end of the v3.7 merge window, after
rebasing it on top of all the other branches he merged.
This means it happens pretty much ad-hoc and there is little
testing on the patches that actually get merged.

c) Split the series and submit the first two branches at
the start of the merge window, and do the changes to all
the drivers either at the end of the v3.7 merge window
(after rebasing) or merge them through the subsystem
maintainer trees in small chunks for v3.8. This can minimize
the problems of the other two approaches, but means the process
takes longer to get to the same result.

        Arnd

[second attempt to send these patches, the first one was rejected by
lists.infradead.org, this one uses a different smtp setup]

Arnd Bergmann (4):
  [RFC] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
  [RFC] ARM: mass move of mach-*/plat-* header files
  [RFC] ARM: treewide: scripted conversion to mach-*/*.h
  [RFC] ARM: treewide: manually change more mach-*/*.h includes

   0.0% Documentation/spi/
   0.0% arch/arm/boot/compressed/
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   0.6% arch/arm/mach-bcmring/include/mach-bcmring/
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   0.0% arch/arm/mach-mxs/
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   1.2% arch/arm/mach-omap2/include/mach-omap2/
   1.2% arch/arm/mach-omap2/include/mach/
   0.3% arch/arm/mach-omap2/
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   0.4% arch/arm/mach-pnx4008/include/mach-pnx4008/
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   4.0% arch/arm/mach-pxa/include/mach-pxa/
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From arnd at arndb.de  Wed Aug 22 08:54:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 12:54:22 +0000
Subject: [PATCH 1/4] [RFC] ARM: autogenerate mach-foo/* and plat-foo/* header
 redirects
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <201208221254.22292.arnd@arndb.de>

This is an attempt to simplify the duplicate header problem for
multiplatform kernels, in multiple steps:

1. (this patch)
   for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
   generate a arch/arm/include/generated/mach/*.h file at build time,
   same for plat-*.

2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
   arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
   arch/arm/plat-${PLAT}/include/plat/*.h to
   arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h

3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
   in all files where ${MACHINE} is known.

4. ...

5. Revert this patch again.

We can apply this patch at any time, and do step 2 at the end
of the next merge window to minimize the potential for conflicts.
We will also still need to deal with any inclusion of a mach/*
file, but out of the 6355 ones we have today, I expect only a
few hundred to remain after step 3 and they will be much easier
to spot.

I've picked the format <mach-foo/bar.h> to get a unique name because
it matches the directory name under arch/arm, but other names
would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
have been suggested previously.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Makefile          |    1 +
 arch/arm/tools/Makefile    |    5 ++++
 arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100755 arch/arm/tools/gen-headers

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..761b077 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -274,6 +274,7 @@ boot := arch/arm/boot
 
 archprepare:
        $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
+       $(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
 
 # Convert bzImage to zImage
 bzImage: zImage
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 635cb18..6e18ca9 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
        @echo '  Generating $@'
        @mkdir -p $(dir $@)
        $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
+
+gen_headers:
+       $(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
+
+.PHONY: gen_headers
diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
new file mode 100755
index 0000000..caa6a9a
--- /dev/null
+++ b/arch/arm/tools/gen-headers
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+SRC=$1
+OBJ=$2
+MACH=$3
+PLAT1=$4
+PLAT2=$5
+
+# create $3 to include $2 if it doesn't already have the correct
+# contents, or remove it if it's no longer needed.
+mkfile()
+{
+       if [ -e $1/$2 ] ; then
+               if [ ! -e $3 ] ; then
+                       mkdir -p ${3%/*}
+                       echo "#include <${2}>" > $3
+               elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
+                       echo "#include <${2}>" > $3
+               fi
+       elif [ ! -e $1/$2 -a -e $3 ] ; then
+               rm -f $3
+       fi
+}
+
+# list any header files that are present in the source or
+# destination directories
+find_files()
+{
+       pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
+       find . -type f -name \*.h -o -name \*.S &&
+       popd > /dev/null 2>&1
+       pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
+       find . -type f -name \*.h -o -name \*.S &&
+       popd > /dev/null 2>&1
+}
+
+# process files in either mach-{MACH} or plat-${PLAT}
+mkfiles()
+{
+       mkdir -p ${OBJ}/arch/arm/include/generated/$1
+
+       FILES=`find_files $1 $2 | sort -u`
+       for i in ${FILES} ; do
+               mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
+                       "${OBJ}/arch/arm/include/generated/$1/$i"
+       done
+}
+
+# always process mach-*
+mkfiles mach ${MACH}
+# process plat-* if applicable
+if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
+       mkfiles plat ${PLAT1}
+fi
+if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
+       mkfiles plat ${PLAT2}
+fi
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 09:00:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 13:00:10 +0000
Subject: [PATCH 3/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <201208221300.10798.arnd@arndb.de>

While converting all machine specific headers from
automatically detect the right machine and platform
name in most cases. This script uses a number of
information sources for this:

* any arch/arm/mach-*/ directory uses its own headers,
  with a few exceptions, same for plat-*/
* each mach-*/ directory belongs to at most one plat-*
  directory holding header files
* for any header below mach/* that exists in only one
  machine, we know that the users belong to that machine
* some driver directories or files are manually listed
  here.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
===========================================================

fixup()
{
 echo fixup "$1 $2 $3"
 git ls-files $1 | xargs sed -i "s:^\(#.*include <\)$2/:\1$3/:g"
}

fixup arch/arm/mach-s3c2410 mach mach-s3c24xx
fixup arch/arm/mach-s3c2412 mach mach-s3c24xx
fixup arch/arm/mach-s3c2440 mach mach-s3c24xx

fixup arch/arm/plat-mxc mach mach-imx
fixup arch/arm/plat-s3c24xx mach mach-s3c24xx
fixup arch/arm/plat-s3c24xx plat plat-samsung

for i in arch/arm/mach-*; do
        fixup "$i" mach "${i##*/}"
done

for i in arch/arm/plat-* ; do
        fixup "$i" plat "${i##*/}"
done

fixup arch/arm/mach-spear3xx plat plat-spear
fixup arch/arm/mach-spear6xx plat plat-spear
fixup arch/arm/mach-spear13xx plat plat-spear
fixup arch/arm/mach-pxa plat plat-pxa
fixup arch/arm/mach-mmp plat plat-pxa
fixup arch/arm/mach-orion5x plat plat-orion
fixup arch/arm/mach-kirkwood plat plat-orion
fixup arch/arm/mach-mv78xx0 plat plat-orion
fixup arch/arm/mach-dove plat plat-orion
fixup arch/arm/mach-nomadik plat plat-nomadik
fixup arch/arm/mach-ux500 plat plat-nomadik
fixup arch/arm/mach-s3c2410 plat plat-samsung
fixup arch/arm/mach-s3c2412 plat plat-samsung
fixup arch/arm/mach-s3c2440 plat plat-samsung
fixup arch/arm/mach-s3c24xx plat plat-samsung
fixup arch/arm/mach-s3c64xx plat plat-samsung
fixup arch/arm/mach-s5p64x0 plat plat-samsung
fixup arch/arm/mach-s5pc100 plat plat-samsung
fixup arch/arm/mach-s5pv210 plat plat-samsung
fixup arch/arm/mach-exynos plat plat-samsung
fixup arch/arm/mach-omap1 plat plat-omap
fixup arch/arm/mach-omap2 plat plat-omap
fixup arch/arm/mach-versatile plat plat-versatile
fixup arch/arm/mach-integrator plat plat-versatile
fixup arch/arm/mach-realview plat plat-versatile
fixup arch/arm/mach-vexpress plat plat-versatile
fixup arch/arm/mach-zynq plat plat-versatile

fixup drivers/video/omap plat plat-omap
fixup drivers/video/omap2 plat plat-omap
fixup drivers/video/exynos plat plat-samsung
fixup drivers/char/hw_random/omap\* plat plat-omap
fixup drivers/cpufreq/omap\* plat plat-omap
fixup drivers/crypto/omap\* plat plat-omap
fixup drivers/media/video/omap\* plat plat-omap
fixup drivers/input/keyboard/omap\* plat plat-omap
fixup drivers/mmc/host/omap\* plat plat-omap
fixup drivers/mtd/*nand/omap\* plat plat-omap
fixup drivers/spi/spi-omap\* plat plat-omap
fixup drivers/tty/serial/omap\* plat plat-omap
fixup drivers/usb/gadget/omap\* plat plat-omap
fixup drivers/usb/musb/*omap\* plat plat-omap
fixup drivers/dma/omap-dma.c plat plat-omap
fixup drivers/staging/omapdrm plat plat-omap
fixup drivers/staging/tidspbridge/ plat plat-omap
fixup drivers/input/keyboard/spear-keyboard.c plat plat-spear
fixup drivers/cpufreq/exynos-cpufreq.c plat plat-samsung
fixup drivers/crypto/s5p-sss.c plat plat-samsung
fixup drivers/i2c/busses/i2c-nomadik.c plat plat-nomadik
fixup drivers/mtd/nand/s3c2410.c plat plat-samsung
fixup drivers/tty/serial/samsung.c plat plat-samsung
fixup drivers/usb/gadget/s3c-hsotg.c plat plat-samsung
fixup drivers/gpio/gpio-samsung.c plat plat-samsung
fixup sound/soc/samsung plat plat-samsung
fixup sound/soc/omap plat plat-omap
fixup sound/soc/pxa plat plat-pxa
fixup sound/soc/kirkwood/ plat plat-orion
fixup sound/soc/fsl/imx*.[ch] plat plat-mxc

fixup drivers/video/omap mach mach-omap1
fixup drivers/video/omap2 mach mach-omap2
fixup drivers/video/exynos mach mach-exynos
fixup drivers/media/video/davinci mach mach-davinci

fixup sound/soc/omap/osk5912.c mach mach-omap1
fixup sound/soc/omap mach mach-omap2
fixup sound/soc/pxa mach mach-pxa
fixup sound/soc/davinci mach mach-davinci
fixup sound/soc/ep93xx mach mach-ep93xx
fixup sound/soc/kirkwood/ mach mach-kirkwood
fixup sound/soc/fsl/imx*.[ch] mach mach-imx
fixup sound/soc/mxs mach mach-mxs
fixup sound/soc/tegra mach mach-tegra
fixup sound/soc/nuc900 mach mach-w90x900
fixup sound/arm/pxa\* mach mach-pxa
fixup sound/atmel/ac97c.c mach mach-at91
fixup sound/oss/waveartist.c mach mach-footbridge
fixup sound/oss/vidc\* mach mach-rpc
fixup sound/soc/atmel/ mach mach-at91
fixup sound/soc/ux500/ mach mach-ux500

fixup include/linux/spi/pxa2xx_spi.h mach mach-pxa
fixup include/linux/mfd/dbx500-prcmu.h mach mach-ux500

find_unique_mach()
{
  {
    # find files in other architectures using mach/*.h
    git ls-files | grep /mach/[^/]*.h | while read i ;
        do echo ${i##*/}
    done
    # find files we've already renamed in ARM
    for i in arch/arm/mach-*/include/mach-*/ ; do
        git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_mach()
{
  ALLFILES=`git grep -l "^#include.*<mach/"`
  ALLINCLUDES=`git grep "^#include.*<mach/" ${ALLFILES}`
  find_unique_mach | while read i ; do
    echo "$ALLINCLUDES" | if grep -q "#include.*<mach/$i>" &&
                [ -e arch/arm/mach-*/include/mach-*/"$i" ] ; then
       MACH=`ls arch/arm/mach-*/include/mach-*/$i | cut -f 3 -d /`
       THESEFILES=`git grep -l "^#include.*<mach/$i>" ${ALLFILES}`
       echo mach/$i
       for j in ${THESEFILES} ; do
          fixup $j mach ${MACH}
       done
    fi
  done
}

find_unique_plat()
{
  {
    # all plat/*.h files are already renamed
    for i in arch/arm/plat-*/include/plat-*/ ; do
        git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_plat()
{
  ALLFILES=`git grep -l "#include.*<plat/"`
  if [ "" != "${ALLFILES}" ] ; then
    find_unique_plat | while read i ; do
      PLAT=`ls arch/arm/plat-*/include/plat-*/$i | cut -f 3 -d /`
      THESEFILES=`git grep -l "^#include.*<plat/$i>" ${ALLFILES}`
      echo plat/$i
       for j in ${THESEFILES} ; do
          fixup $j plat ${PLAT}
       done
    done
  fi
}

rename_unique_mach
rename_unique_plat
---
   0.0% Documentation/spi/
   0.0% arch/arm/boot/compressed/
   0.3% arch/arm/mach-at91/include/mach-at91/
   4.7% arch/arm/mach-at91/
   0.1% arch/arm/mach-bcmring/csp/chipc/
   0.1% arch/arm/mach-bcmring/csp/dmac/
   0.0% arch/arm/mach-bcmring/csp/tmr/
   0.0% arch/arm/mach-bcmring/include/csp/
   0.3% arch/arm/mach-bcmring/include/mach-bcmring/csp/
   0.1% arch/arm/mach-bcmring/include/mach-bcmring/
   0.4% arch/arm/mach-bcmring/
   0.0% arch/arm/mach-clps711x/include/mach-clps711x/
   0.1% arch/arm/mach-clps711x/
   0.0% arch/arm/mach-cns3xxx/include/mach-cns3xxx/
   0.1% arch/arm/mach-cns3xxx/
   0.3% arch/arm/mach-davinci/include/mach-davinci/
   3.3% arch/arm/mach-davinci/
   0.0% arch/arm/mach-dove/include/mach-dove/
   0.3% arch/arm/mach-dove/
   0.0% arch/arm/mach-ebsa110/
   0.0% arch/arm/mach-ep93xx/include/mach-ep93xx/
   0.5% arch/arm/mach-ep93xx/
   0.2% arch/arm/mach-exynos/include/mach-exynos/
   3.9% arch/arm/mach-exynos/
   0.0% arch/arm/mach-footbridge/include/mach-footbridge/
   0.0% arch/arm/mach-footbridge/
   0.1% arch/arm/mach-gemini/include/mach-gemini/
   0.1% arch/arm/mach-gemini/
   0.0% arch/arm/mach-h720x/include/mach-h720x/
   0.1% arch/arm/mach-h720x/
   0.6% arch/arm/mach-imx/include/mach-imx/
   5.0% arch/arm/mach-imx/
   0.5% arch/arm/mach-integrator/
   0.0% arch/arm/mach-iop13xx/include/mach-iop13xx/
   0.2% arch/arm/mach-iop13xx/
   0.0% arch/arm/mach-iop32x/include/mach-iop32x/
   0.1% arch/arm/mach-iop32x/
   0.0% arch/arm/mach-iop33x/include/mach-iop33x/
   0.1% arch/arm/mach-iop33x/
   0.1% arch/arm/mach-ixp4xx/include/mach-ixp4xx/
   0.3% arch/arm/mach-ixp4xx/
   0.0% arch/arm/mach-kirkwood/include/mach-kirkwood/
   1.1% arch/arm/mach-kirkwood/
   0.1% arch/arm/mach-ks8695/include/mach-ks8695/
   0.4% arch/arm/mach-ks8695/
   0.0% arch/arm/mach-lpc32xx/include/mach-lpc32xx/
   0.3% arch/arm/mach-lpc32xx/
   0.4% arch/arm/mach-mmp/include/mach-mmp/
   1.5% arch/arm/mach-mmp/
   0.1% arch/arm/mach-msm/include/mach-msm/
   1.2% arch/arm/mach-msm/
   0.0% arch/arm/mach-mv78xx0/include/mach-mv78xx0/
   0.3% arch/arm/mach-mv78xx0/
   0.0% arch/arm/mach-mvebu/include/mach-mvebu/
   0.0% arch/arm/mach-mvebu/
   0.5% arch/arm/mach-mxs/devices/
   0.1% arch/arm/mach-mxs/include/mach-mxs/
   0.5% arch/arm/mach-mxs/
   0.3% arch/arm/mach-netx/
   0.0% arch/arm/mach-nomadik/include/mach-nomadik/
   0.1% arch/arm/mach-nomadik/
   0.2% arch/arm/mach-omap1/include/mach-omap1/
   3.3% arch/arm/mach-omap1/
   0.1% arch/arm/mach-omap2/include/mach-omap2/
   8.1% arch/arm/mach-omap2/
   0.1% arch/arm/mach-orion5x/include/mach-orion5x/
   0.7% arch/arm/mach-orion5x/
   0.0% arch/arm/mach-picoxcell/include/mach-picoxcell/
   0.0% arch/arm/mach-picoxcell/
   0.0% arch/arm/mach-pnx4008/include/mach-pnx4008/
   0.4% arch/arm/mach-pnx4008/
   0.1% arch/arm/mach-prima2/include/mach-prima2/
   0.0% arch/arm/mach-prima2/
   0.7% arch/arm/mach-pxa/include/mach-pxa/
   7.6% arch/arm/mach-pxa/
   0.3% arch/arm/mach-realview/include/mach-realview/
   0.4% arch/arm/mach-realview/
   0.0% arch/arm/mach-rpc/include/mach-rpc/
   0.1% arch/arm/mach-rpc/
   0.1% arch/arm/mach-s3c2410/
   0.1% arch/arm/mach-s3c2412/
   0.2% arch/arm/mach-s3c2440/
   0.3% arch/arm/mach-s3c24xx/include/mach-s3c24xx/
  10.9% arch/arm/mach-s3c24xx/
   0.1% arch/arm/mach-s3c64xx/include/mach-s3c64xx/
   3.9% arch/arm/mach-s3c64xx/
   0.2% arch/arm/mach-s5p64x0/include/mach-s5p64x0/
   2.1% arch/arm/mach-s5p64x0/
   0.2% arch/arm/mach-s5pc100/include/mach-s5pc100/
   1.0% arch/arm/mach-s5pc100/
   0.2% arch/arm/mach-s5pv210/include/mach-s5pv210/
   2.1% arch/arm/mach-s5pv210/
   0.1% arch/arm/mach-sa1100/include/mach-sa1100/
   1.1% arch/arm/mach-sa1100/
   0.0% arch/arm/mach-shmobile/include/mach-shmobile/
   1.9% arch/arm/mach-shmobile/
   0.0% arch/arm/mach-spear13xx/include/mach-spear13xx/
   0.1% arch/arm/mach-spear13xx/
   0.0% arch/arm/mach-spear3xx/include/mach-spear3xx/
   0.2% arch/arm/mach-spear3xx/
   0.0% arch/arm/mach-spear6xx/include/mach-spear6xx/
   0.0% arch/arm/mach-spear6xx/
   0.0% arch/arm/mach-tegra/include/mach-tegra/
   1.0% arch/arm/mach-tegra/
   0.0% arch/arm/mach-u300/include/mach-u300/
   0.2% arch/arm/mach-u300/
   0.1% arch/arm/mach-ux500/include/mach-ux500/
   0.9% arch/arm/mach-ux500/
   0.0% arch/arm/mach-versatile/include/mach-versatile/
   0.1% arch/arm/mach-versatile/
   0.1% arch/arm/mach-vexpress/
   0.1% arch/arm/mach-vt8500/
   0.1% arch/arm/mach-w90x900/include/mach-w90x900/
   0.4% arch/arm/mach-w90x900/
   0.0% arch/arm/mach-zynq/include/mach-zynq/
   0.0% arch/arm/mach-zynq/
   0.0% arch/arm/mm/
   1.0% arch/arm/plat-mxc/devices/
   0.4% arch/arm/plat-mxc/
   0.4% arch/arm/plat-omap/include/plat-omap/
   0.6% arch/arm/plat-omap/
   0.1% arch/arm/plat-orion/
   0.0% arch/arm/plat-pxa/
   0.6% arch/arm/plat-s3c24xx/
   0.2% arch/arm/plat-samsung/include/plat-samsung/
   1.4% arch/arm/plat-samsung/
   0.0% arch/arm/plat-spear/
   0.0% arch/arm/plat-versatile/
   0.1% drivers/ata/
   0.0% drivers/char/hw_random/
   0.0% drivers/char/
   0.0% drivers/clk/mxs/
   0.0% drivers/clk/
   0.0% drivers/clocksource/
   0.0% drivers/cpufreq/
   0.0% drivers/crypto/ux500/cryp/
   0.0% drivers/crypto/ux500/hash/
   0.1% drivers/crypto/
   0.0% drivers/devfreq/
   0.0% drivers/dma/ipu/
   0.2% drivers/dma/
   0.4% drivers/gpio/
   0.0% drivers/gpu/drm/exynos/
   0.0% drivers/hwmon/
   0.0% drivers/i2c/busses/
   0.0% drivers/iio/adc/
   0.3% drivers/input/keyboard/
   0.0% drivers/input/mouse/
   0.0% drivers/input/serio/
   0.1% drivers/input/touchscreen/
   0.2% drivers/iommu/
   0.0% drivers/leds/
   0.1% drivers/media/video/davinci/
   0.0% drivers/media/video/omap/
   0.1% drivers/media/video/omap3isp/
   0.0% drivers/media/video/s5p-fimc/
   0.0% drivers/media/video/s5p-tv/
   0.1% drivers/media/video/
   0.1% drivers/mfd/
   0.3% drivers/mmc/host/
   0.0% drivers/mtd/maps/
   0.4% drivers/mtd/nand/
   0.0% drivers/mtd/onenand/
   0.0% drivers/net/ethernet/cadence/
   0.0% drivers/net/ethernet/micrel/
   0.0% drivers/net/ethernet/smsc/
   0.0% drivers/net/ethernet/xscale/
   0.0% drivers/net/ethernet/
   0.0% drivers/net/wan/
   0.6% drivers/pcmcia/
   0.0% drivers/pinctrl/
   0.0% drivers/power/
   0.0% drivers/ptp/
   0.0% drivers/pwm/
   0.0% drivers/remoteproc/
   0.0% drivers/rtc/
   0.2% drivers/spi/
   0.0% drivers/staging/nvec/
   0.0% drivers/staging/omapdrm/
   0.0% drivers/staging/tidspbridge/core/
   0.0% drivers/staging/tidspbridge/include/dspbridge/
   0.0% drivers/staging/tidspbridge/rmgr/
   0.1% drivers/tty/serial/
   0.2% drivers/usb/gadget/
   0.4% drivers/usb/host/
   0.1% drivers/usb/musb/
   0.0% drivers/usb/otg/
   0.1% drivers/video/backlight/
   0.0% drivers/video/exynos/
   0.2% drivers/video/msm/
   0.1% drivers/video/omap/
   0.1% drivers/video/omap2/dss/
   0.0% drivers/video/omap2/omapfb/
   0.0% drivers/video/omap2/
   0.4% drivers/video/
   0.0% drivers/watchdog/
   0.0% include/linux/mfd/
   0.0% include/linux/platform_data/
   0.0% include/linux/power/
   0.0% include/linux/spi/
   0.0% include/linux/
   0.1% sound/arm/
   0.0% sound/atmel/
   0.0% sound/oss/
   0.0% sound/soc/atmel/
   0.1% sound/soc/davinci/
   0.1% sound/soc/ep93xx/
   0.0% sound/soc/fsl/
   0.0% sound/soc/kirkwood/
   0.0% sound/soc/mxs/
   0.0% sound/soc/nuc900/
   0.6% sound/soc/omap/
   0.5% sound/soc/pxa/
   0.2% sound/soc/samsung/
   0.0% sound/soc/tegra/
   0.1% sound/soc/ux500/

diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
index d8eb01c..f088b4b 100644
--- a/Documentation/spi/ep93xx_spi
+++ b/Documentation/spi/ep93xx_spi
@@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 
-#include <mach/ep93xx_spi.h>
+#include <mach-ep93xx/ep93xx_spi.h>
 
 /* this is our GPIO line used for chip select */
 #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b..4bcb9c7 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -23,7 +23,7 @@
        .section        ".start", "ax"
 
        /* load board-specific initialization code */
-#include <mach/zboot.h>
+#include <mach-shmobile/zboot.h>
 
 #if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
        /* Load image from MMC/SD */
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
index bd3d469..ff0aa20 100644
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ b/arch/arm/boot/compressed/sdhi-shmobile.c
@@ -18,7 +18,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sd.h>
 #include <linux/mmc/tmio.h>
-#include <mach/sdhi.h>
+#include <mach-shmobile/sdhi.h>
 
 #define OCR_FASTBOOT           (1<<29)
 #define OCR_HCS                        (1<<30)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6f50c67..fd81ffe 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -16,11 +16,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_st.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb732..2b63b60 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -18,10 +18,10 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 
-#include <mach/board.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40..aec1da4 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -27,7 +27,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_st.h>
+#include <mach-at91/at91_st.h>
 
 static unsigned long last_crtr;
 static u32 irqmask;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26..e84bddb 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -17,12 +17,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..cb364af 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,13 +19,13 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_adc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index f40762c..58c830b 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -17,11 +17,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8df5c1b..f2e6805 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,11 +21,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9261_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9261_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b3810..51f4f7e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..26dc600 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -20,11 +20,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9263_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index ffc0957..e3b0d36 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -20,7 +20,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_pit.h>
+#include <mach-at91/at91_pit.h>
 
 
 #define PIT_CPIV(x)    ((x) & AT91_PIT_CPIV)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 7af2e10..6d8da98 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -14,9 +14,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
                        .arm
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd..45c79b4 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 0607399..242c850 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,14 +25,14 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/at91_adc.h>
-#include <mach/board.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
-#include <mach/atmel-mci.h>
+#include <mach-at91/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9g45_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
+#include <mach-at91/atmel-mci.h>
 
 #include <media/atmel-isi.h>
 
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 9d45718..0726dad 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -11,9 +11,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
                        .arm
 
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..b5f4e1d 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9n12.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72ce50a..3c17719 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -16,12 +16,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..cf41235 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -17,12 +17,12 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9rl_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9rl_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..d919d0e 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e6..e3224b1 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -17,10 +17,10 @@
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
-#include <mach/at91x40.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_st.h>
-#include <mach/timex.h>
+#include <mach-at91/at91x40.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/timex.h>
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a..478fa8a 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -24,9 +24,9 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/time.h>
-#include <mach/at91_tc.h>
+#include <mach-at91/at91_tc.h>
 
 #define at91_tc_read(field) \
        __raw_readl(AT91_TC + field)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 22d8856..bbfe99a 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be19..ae1469e 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -34,7 +34,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,8 +43,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 477e708..8e3b25a 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -29,7 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f..b2f21fc 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b..2d5334c 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -39,12 +39,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043..73934ef 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -27,7 +27,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,11 +36,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc31..40f5e99 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 872871a..df54c811 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4..346b427 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,8 +15,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 01f66e9..5a0365d 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -24,11 +24,11 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 #include "generic.h"
 
 static void __init at91eb01_init_irq(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3f..3ae9f49 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,8 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb2..f9d2da7 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde..814756e 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -24,11 +24,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a8..d5315ef 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -32,9 +32,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab124..43b5fc2 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -32,7 +32,7 @@
 #include <linux/clk.h>
 #include <linux/w1-gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index a9d5e78..b6d0d6f 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -30,11 +30,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/gsia18s.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/gsia18s.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf..7e98f65 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb8..5b1bf97 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,11 +35,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d..c9e9d89 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 9ca3e32..f809d33 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -29,10 +29,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 1270655..469000d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,10 +37,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e2..0364e46 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -39,11 +39,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf97..9769e97 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e6..2311b39 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43ae..5dfc434 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -24,9 +24,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <linux/gpio.h>
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da7..39546b8 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -28,7 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf..27865bc 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -40,12 +40,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5..e37f30f 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -44,12 +44,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf58..b149347 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -43,12 +43,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee0..cd48ea7 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -34,7 +34,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 3d48ec1..4222519 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -29,7 +29,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <video/atmel_lcdc.h>
 #include <media/soc_camera.h>
 #include <media/atmel-isi.h>
@@ -42,11 +42,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ea..80f805c 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,11 +29,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index a4e031a..dada12c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -31,10 +31,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae16..64c7010 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -25,9 +25,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9..dacfc5b 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -40,11 +40,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340..fed4f0a 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -42,12 +42,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index de2ec6b..c5789a1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -25,9 +25,9 @@
 #include <linux/io.h>
 #include <linux/of_address.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include <asm/proc-fns.h>
 
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c63815..6d03dc6 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -21,7 +21,7 @@
 #include <linux/export.h>
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #include "pm.h"
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..ce21de2 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -28,8 +28,8 @@
 
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pio.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
index d8aeb27..c871a14 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
@@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
 #define AT91_MEMCTRL_SDRAMC    1
 #define AT91_MEMCTRL_DDRSDR    2
 
-#include <mach/at91rm9200_sdramc.h>
-#include <mach/at91sam9_ddrsdr.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
+#include <mach-at91/at91sam9_ddrsdr.h>
+#include <mach-at91/at91sam9_sdramc.h>
 
 #endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
index 175e1fd..2f6393e 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
@@ -16,7 +16,7 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #ifndef __ASSEMBLY__
 struct sam9_smc_config {
diff --git a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
index 998cb0c..d8f4109 100644
--- a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_ATMEL_MCI_H
 #define __MACH_ATMEL_MCI_H
 
-#include <mach/at_hdmac.h>
+#include <mach-at91/at_hdmac.h>
 
 /**
  * struct mci_dma_data - DMA data for MCI interface
diff --git a/arch/arm/mach-at91/include/mach-at91/debug-macro.S b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
index c6bb9e2..8a1599c 100644
--- a/arch/arm/mach-at91/include/mach-at91/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
@@ -11,8 +11,8 @@
  *
 */
 
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_dbgu.h>
 
 #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
 #define AT91_DBGU AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/include/mach-at91/hardware.h b/arch/arm/mach-at91/include/mach-at91/hardware.h
index 09242b6..caef81c 100644
--- a/arch/arm/mach-at91/include/mach-at91/hardware.h
+++ b/arch/arm/mach-at91/include/mach-at91/hardware.h
@@ -23,16 +23,16 @@
 #define AT91_BASE_DBGU1        0xffffee00
 
 #if defined(CONFIG_ARCH_AT91X40)
-#include <mach/at91x40.h>
+#include <mach-at91/at91x40.h>
 #else
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91sam9n12.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91sam9n12.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach-at91/memory.h b/arch/arm/mach-at91/include/mach-at91/memory.h
index 401c207..88c06fd 100644
--- a/arch/arm/mach-at91/include/mach-at91/memory.h
+++ b/arch/arm/mach-at91/include/mach-at91/memory.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach-at91/timex.h b/arch/arm/mach-at91/include/mach-at91/timex.h
index 5e917a6..f4e72e2 100644
--- a/arch/arm/mach-at91/include/mach-at91/timex.h
+++ b/arch/arm/mach-at91/include/mach-at91/timex.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #ifdef CONFIG_ARCH_AT91X40
 
diff --git a/arch/arm/mach-at91/include/mach-at91/uncompress.h b/arch/arm/mach-at91/include/mach-at91/uncompress.h
index 6f6118d..914feb7 100644
--- a/arch/arm/mach-at91/include/mach-at91/uncompress.h
+++ b/arch/arm/mach-at91/include/mach-at91/uncompress.h
@@ -24,10 +24,10 @@
 
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
-#include <mach/at91_dbgu.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/cpu.h>
 
 void __iomem *at91_uart;
 
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 1e02c0e..eeddbec 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,7 +33,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include <mach/at91_aic.h>
+#include <mach-at91/at91_aic.h>
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..f921b1e 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d865..a5b940e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,9 +25,9 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 #include "pm.h"
@@ -36,8 +36,8 @@
  * Show the reason for the previous system reset.
  */
 
-#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/at91_rstc.h>
+#include <mach-at91/at91_shdwc.h>
 
 static void __init show_reset_status(void)
 {
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c..529072a 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,8 +11,8 @@
 #ifndef __ARCH_ARM_MACH_AT91_PM
 #define __ARCH_ARM_MACH_AT91_PM
 
-#include <mach/at91_ramc.h>
-#include <mach/at91rm9200_sdramc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..8f263c6 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,9 +13,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_ramc.h>
 
 
 #ifdef CONFIG_SOC_AT91SAM9263
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 99a0a1d..be40bf2 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -14,7 +14,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb..0fe58d5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -14,11 +14,11 @@
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..f7469da 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -32,11 +32,11 @@
 #include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/dma.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <cfg_global.h>
 
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
index ad237a4..108845f 100644
--- a/arch/arm/mach-bcmring/clock.c
+++ b/arch/arm/mach-bcmring/clock.c
@@ -22,10 +22,10 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/hw_cfg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
index 5e0b981..2e01614 100644
--- a/arch/arm/mach-bcmring/clock.h
+++ b/arch/arm/mach-bcmring/clock.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 #define CLK_TYPE_PRIMARY         1     /* primary clock must NOT have a parent */
 #define CLK_TYPE_PLL1            2     /* PPL1 */
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb19..4d089b3 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -29,8 +29,8 @@
 #include <linux/amba/bus.h>
 #include <linux/clkdev.h>
 
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
+#include <mach-bcmring/csp/mm_addr.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -48,9 +48,9 @@
 #include "clock.h"
 
 #include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/secHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
 static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff..270689d 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75..48e5977 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d88..0aee4f2 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -14,8 +14,8 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 #include <csp/intcHw.h>
 #include <csp/cache.h>
 
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
index 54ad964..d466c49 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -23,7 +23,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e..4a9675a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -30,9 +30,9 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- External Function Prototypes ------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f3283..f4e883a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -30,8 +30,8 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
 
 extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];   /* Declared in dmacHw.c */
 
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e4..220e314 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -30,7 +30,7 @@
 #include <csp/stdint.h>
 
 #include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
 #define tmrHw_MILLISEC_PER_SEC              (1000)
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index e5fd241..e90cfdf 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -31,11 +31,11 @@
 #include <linux/proc_fs.h>
 #include <linux/slab.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 #include <linux/pfn.h>
 #include <linux/atomic.h>
-#include <mach/dma.h>
+#include <mach-bcmring/dma.h>
 
 /* ---- Public Variables ------------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
index e6a1dc4..97d8a04 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -26,7 +26,7 @@
 #include <stddef.h>
 
 #include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
 
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
 
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
index 1c639c8..eb7d3ae 100644
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -28,7 +28,7 @@
 #define _INTCHW_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 /* ---- Public Variable Externs ------------------------------------------ */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
index 56654d2..23ac669 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -69,7 +69,7 @@
 /*  */
 
 #if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/interrupt.h>
 
 #define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
index 933ce68..4a1ecfa 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
@@ -16,7 +16,7 @@
 #define CAP_INLINE_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
+#include <mach-bcmring/csp/cap.h>
 #include <cfg_global.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
index 1619733..fe57b08 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
@@ -20,7 +20,7 @@
 #include <csp/stdint.h>
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
 
 /* ---- Public Constants and Types ---------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
index 03238c2..108209c 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
@@ -19,8 +19,8 @@
 
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 typedef enum {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
index b162448..85b13d7 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
@@ -23,9 +23,9 @@
 #ifndef CHIPCHW_REG_H
 #define CHIPCHW_REG_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 #include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
+#include <mach-bcmring/csp/ddrcReg.h>
 
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
index f1b68e2..462c099 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
@@ -33,7 +33,7 @@ extern "C" {
 #include <csp/reg.h>
 #include <csp/stdint.h>
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
index f1ecf96..1f5263f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
@@ -25,7 +25,7 @@
 #define _DMACHW_REG_H
 
 #include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Data type for 64 bit little endian register */
 typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
index cfa91be..aad4e17 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
@@ -19,10 +19,10 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
+#include <mach-bcmring/csp/cap_inline.h>
 
 #if defined(__KERNEL__)
-#include <mach/memory_settings.h>
+#include <mach-bcmring/memory_settings.h>
 #else
 #include <hw_cfg.h>
 #endif
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
index 0aeb6a6..0770d7d 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
index de92ec6..dcb1eae 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
@@ -27,7 +27,7 @@
 #define _MM_IO_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #if !defined(CSP_SIMULATION)
 #include <cfg_global.h>
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
index d15f5f3..18279ce 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
@@ -26,7 +26,7 @@
 #ifndef SECHW_DEF_H
 #define SECHW_DEF_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Bit mask for various secure device */
 #define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
@@ -95,6 +95,6 @@ static inline void secHw_setUnsecure(uint32_t mask    /*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void);
 
-#include <mach/csp/secHw_inline.h>
+#include <mach-bcmring/csp/secHw_inline.h>
 
 #endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
index 3080ac7..e6069f5 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
@@ -23,8 +23,8 @@
 #ifndef _TMRHW_REG_H
 #define _TMRHW_REG_H
 
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/hw_cfg.h>
 /* Base address */
 #define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
index 7254378..366caa3 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
@@ -28,7 +28,7 @@
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
 #include <csp/dmacHw.h>
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
index 2f316f0..8967896 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
@@ -17,9 +17,9 @@
  * Low-level IRQ helper macros for BCMRing-based platforms
  *
  */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/irqs.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                ldr     \base, =(MM_IO_BASE_INTC0)
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
index 6ae20a6..c708efd 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
@@ -23,7 +23,7 @@
 
 #include <asm/sizes.h>
 #include <cfg_global.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Hardware addresses of major areas.
  *  *_START is the physical address
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
index 387376f..ec773c2 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/reg_umi.h>
+#include <mach-bcmring/reg_umi.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
index 0992842..f659cc1 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
index 9c9821b..b11fb3f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
 #define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index 437fa68..aa88cac 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -22,12 +22,12 @@
 #include <linux/timer.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 static void bcmring_mask_irq0(struct irq_data *d)
 {
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78e..411fa2b 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -17,8 +17,8 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 #define IO_DESC(va, sz) { .virtual = va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7..ba9754d 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include <csp/tmrHw.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
 /* The real time clock should probably be the real linux clocksource. */
 /* In the meantime, this file should agree with core.c as to the */
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3fb79a1..82ec281 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/sizes.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,7 +33,7 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
+#include <mach-clps711x/autcpu12.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index c314f49..6693600 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index a70147e..177fb74 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293b..5b4fa62 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -28,7 +28,7 @@
 #include <linux/sched.h>
 
 #include <asm/sizes.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 4372f06..6d3e94e 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/sizes.h>
  
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 3a3f0b7..12a1368 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/initrd.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
index 118b3d9..52bd3ef 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
                .macro  addruart, rp, rv, tmp
 #ifndef CONFIG_DEBUG_CLPS711X_UART2
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
index 56e5c2c..889521e 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
@@ -7,7 +7,7 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
                .macro  get_irqnr_preamble, base, tmp
                .endm
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
index 13a64fc..29f3409 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
@@ -22,7 +22,7 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
 
-#include <mach/clps711x.h>
+#include <mach-clps711x/clps711x.h>
 
 #define CLPS711X_VIRT_BASE     IOMEM(0xff000000)
 
---
Intentionally cut off for review. If you managed to read this far, you
get the idea. See the rest at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=d59d6b49ed5287dd0131acda9428fdc0bb0a7365



From m.szyprowski at samsung.com  Wed Aug 22 09:02:51 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 22 Aug 2012 15:02:51 +0200
Subject: [PATCH v2] ARM: DMA-Mapping: print warning when atomic coherent
 allocation fails
In-Reply-To: <20120822083053.42efc6162076534250112652@nvidia.com>
References: <20120822083053.42efc6162076534250112652@nvidia.com>
Message-ID: <1345640571-14349-1-git-send-email-m.szyprowski@samsung.com>

Print a loud warning when system runs out of memory from atomic DMA
coherent pool to let users notice the potential problem.

Reported-by: Aaro Koskinen <aaro.koskinen at iki.fi>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mm/dma-mapping.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index d1cc9c1..acced93 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -461,6 +461,10 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 		bitmap_set(pool->bitmap, pageno, count);
 		ptr = pool->vaddr + PAGE_SIZE * pageno;
 		*ret_page = pool->page + pageno;
+	} else {
+		pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
+			    "Please increase it with coherent_pool= kernel parameter!\n",
+			    (unsigned)pool->size / 1024);
 	}
 	spin_unlock_irqrestore(&pool->lock, flags);
 
-- 
1.7.1.569.g6f426



From gururaja.hebbar at ti.com  Wed Aug 22 09:11:23 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 13:11:23 +0000
Subject: [PATCH 1/5] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <20120817223358.GI18871@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-2-git-send-email-gururaja.hebbar@ti.com>
 <20120817223358.GI18871@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA67D44@DBDE01.ent.ti.com>

On Sat, Aug 18, 2012 at 04:03:58, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 06:12:01PM +0530, Hebbar, Gururaja wrote:
> > Davinci McASP header & driver are shared by few OMAP platforms (like
> > TI81xx, AM335x). Splitting asp header into Davinci platform specific
> > header and Audio specific header helps to share them across platforms.
> 
> This doesn't apply against v3.6-rc2, I suspect there's overlapping
> changes in arch/arm.  I was just going to apply it on a separate branch
> to allow cross-tree merge if there's overlap with architecture work.
> Can you please check and resend?

I will re-apply and send it as v2

> 


Regards, 
Gururaja


From nicolas.pitre at linaro.org  Wed Aug 22 09:19:01 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 09:19:01 -0400 (EDT)
Subject: ioremap() fail on physical address 0x0 in 3.4 kernel
In-Reply-To: <20120822112339.GY18957@n2100.arm.linux.org.uk>
References: <50339AF6.1060601@codeaurora.org>
 <5033C428.2050607@codeaurora.org> <50348030.9080200@codeaurora.org>
 <20120822095302.GX18957@n2100.arm.linux.org.uk>
 <20120822112339.GY18957@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1208220918320.1754@xanadu.home>

On Wed, 22 Aug 2012, Russell King - ARM Linux wrote:

> On Wed, Aug 22, 2012 at 10:53:02AM +0100, Russell King - ARM Linux wrote:
> > @@ -826,7 +826,7 @@ static void __init fill_pmd_gaps(void)
> >  
> >  	/* we're still single threaded hence no lock needed here */
> >  	for (vm = vmlist; vm; vm = vm->next) {
> > -		if (!(vm->flags & VM_ARM_STATIC_MAPPING))
> > +		if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))
> 
> Not forgetting the additional close paren needed here...

Acked-by: Nicolas Pitre <nico at linaro.org>


Nicolas


From shawn.guo at linaro.org  Wed Aug 22 09:36:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:36:26 +0800
Subject: [PATCH v2 0/4] Move imx6q/28/23 clock lookup over to device tree
Message-ID: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>

Change since v1:
* Rewrite of_clk_src_onecell_get() to get the clk using the index
  provided by device tree and the clks array provided by clock driver.
  Then we can save that big clock name list in dts and the string
  matching which is relatively slow. 

Shawn Guo (4):
  clk: add of_clk_src_onecell_get() support
  ARM: imx6q: replace clk_register_clkdev with clock DT lookup
  clk: mxs: replace imx28 clk_register_clkdev with clock DT lookup
  clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup

 .../devicetree/bindings/clock/imx23-clock.txt      |   76 +++++++
 .../devicetree/bindings/clock/imx28-clock.txt      |   99 +++++++++
 .../devicetree/bindings/clock/imx6q-clock.txt      |  222 ++++++++++++++++++++
 arch/arm/boot/dts/imx23.dtsi                       |   16 ++-
 arch/arm/boot/dts/imx28.dtsi                       |   33 +++-
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |   73 ++++++-
 arch/arm/mach-imx/clk-imx6q.c                      |   44 +----
 arch/arm/mach-imx/mach-imx6q.c                     |    1 -
 drivers/clk/clk.c                                  |   14 ++
 drivers/clk/mxs/clk-imx23.c                        |   55 +----
 drivers/clk/mxs/clk-imx28.c                        |  113 +---------
 include/linux/clk-provider.h                       |    5 +
 13 files changed, 550 insertions(+), 202 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx23-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/imx28-clock.txt
 create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt

-- 
1.7.5.4



From shawn.guo at linaro.org  Wed Aug 22 09:36:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:36:27 +0800
Subject: [PATCH v2 1/4] clk: add of_clk_src_onecell_get() support
In-Reply-To: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345642590-29905-2-git-send-email-shawn.guo@linaro.org>

For those SoCs that have hundreds of clock outputs, their clock
DT bindings could reasonably define #clock-cells as 1 and require
the client device specify the index of the clock it consumes in the
cell of its "clocks" phandle.

Add a generic of_clk_src_onecell_get() function for this purpose.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk.c            |   14 ++++++++++++++
 include/linux/clk-provider.h |    5 +++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index efdfd00..308f058 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1582,6 +1582,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 }
 EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
 
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct clk_onecell_data *clk_data = data;
+	unsigned int idx = clkspec->args[0];
+
+	if (idx >= clk_data->clk_num) {
+		pr_err("%s: invalid clock index %d\n", __func__, idx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_data->clks[idx];
+}
+EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
+
 /**
  * of_clk_add_provider() - Register a clock provider for a node
  * @np: Device node pointer associated with clock provider
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fa..8fe6ec7 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -360,6 +360,11 @@ int of_clk_add_provider(struct device_node *np,
 void of_clk_del_provider(struct device_node *np);
 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 				  void *data);
+struct clk_onecell_data {
+	struct clk **clks;
+	unsigned int clk_num;
+};
+struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
 void of_clk_init(const struct of_device_id *matches);
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Wed Aug 22 09:36:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:36:28 +0800
Subject: [PATCH v2 2/4] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345642590-29905-3-git-send-email-shawn.guo@linaro.org>

It really becomes an maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx6q client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx6q-clock.txt      |  222 ++++++++++++++++++++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |   73 ++++++-
 arch/arm/mach-imx/clk-imx6q.c                      |   44 +----
 arch/arm/mach-imx/mach-imx6q.c                     |    1 -
 5 files changed, 291 insertions(+), 50 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 0000000..492bd99
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,222 @@
+* Clock bindings for Freescale i.MX6 Quad
+
+Required properties:
+- compatible: Should be "fsl,imx6q-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q
+clocks and IDs.
+
+	Clock			ID
+	---------------------------
+	dummy			0
+	ckil			1
+	ckih			2
+	osc			3
+	pll2_pfd0_352m		4
+	pll2_pfd1_594m		5
+	pll2_pfd2_396m		6
+	pll3_pfd0_720m		7
+	pll3_pfd1_540m		8
+	pll3_pfd2_508m		9
+	pll3_pfd3_454m		10
+	pll2_198m		11
+	pll3_120m		12
+	pll3_80m		13
+	pll3_60m		14
+	twd			15
+	step			16
+	pll1_sw			17
+	periph_pre		18
+	periph2_pre		19
+	periph_clk2_sel		20
+	periph2_clk2_sel	21
+	axi_sel			22
+	esai_sel		23
+	asrc_sel		24
+	spdif_sel		25
+	gpu2d_axi		26
+	gpu3d_axi		27
+	gpu2d_core_sel		28
+	gpu3d_core_sel		29
+	gpu3d_shader_sel	30
+	ipu1_sel		31
+	ipu2_sel		32
+	ldb_di0_sel		33
+	ldb_di1_sel		34
+	ipu1_di0_pre_sel	35
+	ipu1_di1_pre_sel	36
+	ipu2_di0_pre_sel	37
+	ipu2_di1_pre_sel	38
+	ipu1_di0_sel		39
+	ipu1_di1_sel		40
+	ipu2_di0_sel		41
+	ipu2_di1_sel		42
+	hsi_tx_sel		43
+	pcie_axi_sel		44
+	ssi1_sel		45
+	ssi2_sel		46
+	ssi3_sel		47
+	usdhc1_sel		48
+	usdhc2_sel		49
+	usdhc3_sel		50
+	usdhc4_sel		51
+	enfc_sel		52
+	emi_sel			53
+	emi_slow_sel		54
+	vdo_axi_sel		55
+	vpu_axi_sel		56
+	cko1_sel		57
+	periph			58
+	periph2			59
+	periph_clk2		60
+	periph2_clk2		61
+	ipg			62
+	ipg_per			63
+	esai_pred		64
+	esai_podf		65
+	asrc_pred		66
+	asrc_podf		67
+	spdif_pred		68
+	spdif_podf		69
+	can_root		70
+	ecspi_root		71
+	gpu2d_core_podf		72
+	gpu3d_core_podf		73
+	gpu3d_shader		74
+	ipu1_podf		75
+	ipu2_podf		76
+	ldb_di0_podf		77
+	ldb_di1_podf		78
+	ipu1_di0_pre		79
+	ipu1_di1_pre		80
+	ipu2_di0_pre		81
+	ipu2_di1_pre		82
+	hsi_tx_podf		83
+	ssi1_pred		84
+	ssi1_podf		85
+	ssi2_pred		86
+	ssi2_podf		87
+	ssi3_pred		88
+	ssi3_podf		89
+	uart_serial_podf	90
+	usdhc1_podf		91
+	usdhc2_podf		92
+	usdhc3_podf		93
+	usdhc4_podf		94
+	enfc_pred		95
+	enfc_podf		96
+	emi_podf		97
+	emi_slow_podf		98
+	vpu_axi_podf		99
+	cko1_podf		100
+	axi			101
+	mmdc_ch0_axi_podf	102
+	mmdc_ch1_axi_podf	103
+	arm			104
+	ahb			105
+	apbh_dma		106
+	asrc			107
+	can1_ipg		108
+	can1_serial		109
+	can2_ipg		110
+	can2_serial		111
+	ecspi1			112
+	ecspi2			113
+	ecspi3			114
+	ecspi4			115
+	ecspi5			116
+	enet			117
+	esai			118
+	gpt_ipg			119
+	gpt_ipg_per		120
+	gpu2d_core		121
+	gpu3d_core		122
+	hdmi_iahb		123
+	hdmi_isfr		124
+	i2c1			125
+	i2c2			126
+	i2c3			127
+	iim			128
+	enfc			129
+	ipu1			130
+	ipu1_di0		131
+	ipu1_di1		132
+	ipu2			133
+	ipu2_di0		134
+	ldb_di0			135
+	ldb_di1			136
+	ipu2_di1		137
+	hsi_tx			138
+	mlb			139
+	mmdc_ch0_axi		140
+	mmdc_ch1_axi		141
+	ocram			142
+	openvg_axi		143
+	pcie_axi		144
+	pwm1			145
+	pwm2			146
+	pwm3			147
+	pwm4			148
+	per1_bch		149
+	gpmi_bch_apb		150
+	gpmi_bch		151
+	gpmi_io			152
+	gpmi_apb		153
+	sata			154
+	sdma			155
+	spba			156
+	ssi1			157
+	ssi2			158
+	ssi3			159
+	uart_ipg		160
+	uart_serial		161
+	usboh3			162
+	usdhc1			163
+	usdhc2			164
+	usdhc3			165
+	usdhc4			166
+	vdo_axi			167
+	vpu_axi			168
+	cko1			169
+	pll1_sys		170
+	pll2_bus		171
+	pll3_usb_otg		172
+	pll4_audio		173
+	pll5_video		174
+	pll6_mlb		175
+	pll7_usb_host		176
+	pll8_enet		177
+	ssi1_ipg		178
+	ssi2_ipg		179
+	ssi3_ipg		180
+	rom			181
+	usbphy1			182
+	usbphy2			183
+	ldb_di0_div_3_5		184
+	ldb_di1_div_3_5		185
+
+Examples:
+
+clks: ccm at 020c4000 {
+	compatible = "fsl,imx6q-ccm";
+	reg = <0x020c4000 0x4000>;
+	interrupts = <0 87 0x04 0 88 0x04>;
+	#clock-cells = <1>;
+	clock-output-names = ...
+			     "uart_ipg",
+			     "uart_serial",
+			     ...;
+};
+
+uart1: serial at 02020000 {
+	compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+	reg = <0x02020000 0x4000>;
+	interrupts = <0 26 0x04>;
+	clocks = <&clks 160>, <&clks 161>;
+	clock-names = "ipg", "per";
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..cfdbe53 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -111,6 +111,7 @@
 				codec: sgtl5000 at 0a {
 					compatible = "fsl,sgtl5000";
 					reg = <0x0a>;
+					clocks = <&clks 169>;
 					VDDA-supply = <&reg_2p5v>;
 					VDDIO-supply = <&reg_3p3v>;
 				};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e704a65..6e356ec 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -100,18 +100,23 @@
 		dma-apbh at 00110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 			reg = <0x00110000 0x2000>;
+			clocks = <&clks 106>;
 		};
 
 		gpmi-nand at 00112000 {
-		       compatible = "fsl,imx6q-gpmi-nand";
-		       #address-cells = <1>;
-		       #size-cells = <1>;
-		       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-		       reg-names = "gpmi-nand", "bch";
-		       interrupts = <0 13 0x04>, <0 15 0x04>;
-		       interrupt-names = "gpmi-dma", "bch";
-		       fsl,gpmi-dma-channel = <0>;
-		       status = "disabled";
+			compatible = "fsl,imx6q-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <0 13 0x04>, <0 15 0x04>;
+			interrupt-names = "gpmi-dma", "bch";
+			clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+				 <&clks 150>, <&clks 149>;
+			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+				      "gpmi_bch_apb", "per1_bch";
+			fsl,gpmi-dma-channel = <0>;
+			status = "disabled";
 		};
 
 		timer at 00a00600 {
@@ -153,6 +158,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02008000 0x4000>;
 					interrupts = <0 31 0x04>;
+					clocks = <&clks 112>, <&clks 112>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -162,6 +169,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x0200c000 0x4000>;
 					interrupts = <0 32 0x04>;
+					clocks = <&clks 113>, <&clks 113>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -171,6 +180,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02010000 0x4000>;
 					interrupts = <0 33 0x04>;
+					clocks = <&clks 114>, <&clks 114>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -180,6 +191,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02014000 0x4000>;
 					interrupts = <0 34 0x04>;
+					clocks = <&clks 115>, <&clks 115>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -189,6 +202,8 @@
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02018000 0x4000>;
 					interrupts = <0 35 0x04>;
+					clocks = <&clks 116>, <&clks 116>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -196,6 +211,8 @@
 					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 					reg = <0x02020000 0x4000>;
 					interrupts = <0 26 0x04>;
+					clocks = <&clks 160>, <&clks 161>;
+					clock-names = "ipg", "per";
 					status = "disabled";
 				};
 
@@ -208,6 +225,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x02028000 0x4000>;
 					interrupts = <0 46 0x04>;
+					clocks = <&clks 178>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <38 37>;
 					status = "disabled";
@@ -217,6 +235,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x0202c000 0x4000>;
 					interrupts = <0 47 0x04>;
+					clocks = <&clks 179>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <42 41>;
 					status = "disabled";
@@ -226,6 +245,7 @@
 					compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 					reg = <0x02030000 0x4000>;
 					interrupts = <0 48 0x04>;
+					clocks = <&clks 180>;
 					fsl,fifo-depth = <15>;
 					fsl,ssi-dma-events = <46 45>;
 					status = "disabled";
@@ -365,6 +385,7 @@
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <0 80 0x04>;
+				clocks = <&clks 0>;
 				status = "disabled";
 			};
 
@@ -372,13 +393,15 @@
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <0 81 0x04>;
+				clocks = <&clks 0>;
 				status = "disabled";
 			};
 
-			ccm at 020c4000 {
+			clks: ccm at 020c4000 {
 				compatible = "fsl,imx6q-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <0 87 0x04 0 88 0x04>;
+				#clock-cells = <1>;
 			};
 
 			anatop at 020c8000 {
@@ -475,12 +498,14 @@
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 0x04>;
+				clocks = <&clks 182>;
 			};
 
 			usbphy2: usbphy at 020ca000 {
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 0x04>;
+				clocks = <&clks 183>;
 			};
 
 			snvs at 020cc000 {
@@ -615,6 +640,9 @@
 				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <0 2 0x04>;
+				clocks = <&clks 155>, <&clks 155>;
+				clock-names = "ipg", "ahb";
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
 			};
 		};
 
@@ -638,6 +666,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 0x04>;
+				clocks = <&clks 162>;
 				fsl,usbphy = <&usbphy1>;
 				status = "disabled";
 			};
@@ -646,6 +675,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184200 0x200>;
 				interrupts = <0 40 0x04>;
+				clocks = <&clks 162>;
 				fsl,usbphy = <&usbphy2>;
 				status = "disabled";
 			};
@@ -654,6 +684,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184400 0x200>;
 				interrupts = <0 41 0x04>;
+				clocks = <&clks 162>;
 				status = "disabled";
 			};
 
@@ -661,6 +692,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184600 0x200>;
 				interrupts = <0 42 0x04>;
+				clocks = <&clks 162>;
 				status = "disabled";
 			};
 
@@ -668,6 +700,8 @@
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
 				interrupts = <0 118 0x04 0 119 0x04>;
+				clocks = <&clks 117>, <&clks 117>;
+				clock-names = "ipg", "ahb";
 				status = "disabled";
 			};
 
@@ -680,6 +714,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <0 22 0x04>;
+				clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -687,6 +723,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <0 23 0x04>;
+				clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -694,6 +732,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <0 24 0x04>;
+				clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -701,6 +741,8 @@
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x0219c000 0x4000>;
 				interrupts = <0 25 0x04>;
+				clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+				clock-names = "ipg", "ahb", "per";
 				status = "disabled";
 			};
 
@@ -710,6 +752,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a0000 0x4000>;
 				interrupts = <0 36 0x04>;
+				clocks = <&clks 125>;
 				status = "disabled";
 			};
 
@@ -719,6 +762,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a4000 0x4000>;
 				interrupts = <0 37 0x04>;
+				clocks = <&clks 126>;
 				status = "disabled";
 			};
 
@@ -728,6 +772,7 @@
 				compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 				reg = <0x021a8000 0x4000>;
 				interrupts = <0 38 0x04>;
+				clocks = <&clks 127>;
 				status = "disabled";
 			};
 
@@ -791,6 +836,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021e8000 0x4000>;
 				interrupts = <0 27 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -798,6 +845,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021ec000 0x4000>;
 				interrupts = <0 28 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -805,6 +854,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f0000 0x4000>;
 				interrupts = <0 29 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -812,6 +863,8 @@
 				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 				reg = <0x021f4000 0x4000>;
 				interrupts = <0 30 0x04>;
+				clocks = <&clks 160>, <&clks 161>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8e46407..e163a42 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum mx6q_clks const clks_init_on[] __initconst = {
 	mmdc_ch0_axi, rom,
@@ -387,48 +388,13 @@ int __init mx6q_clocks_init(void)
 			pr_err("i.MX6q clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
 
+	clk_data.clks = clk;
+	clk_data.clk_num = ARRAY_SIZE(clk);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
 	clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
 	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
 	clk_register_clkdev(clk[twd], NULL, "smp_twd");
-	clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
-	clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
-	clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
-	clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
-	clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
-	clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
-	clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
-	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
-	clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
-	clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
-	clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
-	clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
-	clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
-	clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
-	clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
-	clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
-	clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
-	clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
-	clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
-	clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
-	clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
-	clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
-	clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
-	clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
-	clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
-	clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
-	clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
 	clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
 	clk_register_clkdev(clk[ahb], "ahb", NULL);
 	clk_register_clkdev(clk[cko1], "cko1", NULL);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..0b30aa8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -100,7 +100,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
 	clk_set_parent(cko1_sel, ahb);
 	rate = clk_round_rate(cko1, 16000000);
 	clk_set_rate(cko1, rate);
-	clk_register_clkdev(cko1, NULL, "0-000a");
 put_clk:
 	if (!IS_ERR(cko1_sel))
 		clk_put(cko1_sel);
-- 
1.7.5.4



From shawn.guo at linaro.org  Wed Aug 22 09:36:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:36:29 +0800
Subject: [PATCH v2 3/4] clk: mxs: replace imx28 clk_register_clkdev with clock
 DT lookup
In-Reply-To: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345642590-29905-4-git-send-email-shawn.guo@linaro.org>

It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx28 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx28-clock.txt      |   99 +++++++++++++++++
 arch/arm/boot/dts/imx28.dtsi                       |   35 ++++++-
 drivers/clk/mxs/clk-imx28.c                        |  113 ++------------------
 3 files changed, 142 insertions(+), 105 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx28-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
new file mode 100644
index 0000000..aa2af28
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -0,0 +1,99 @@
+* Clock bindings for Freescale i.MX28
+
+Required properties:
+- compatible: Should be "fsl,imx28-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX28
+clocks and IDs.
+
+	Clock		ID
+	------------------
+	ref_xtal	0
+	pll0		1
+	pll1		2
+	pll2		3
+	ref_cpu		4
+	ref_emi		5
+	ref_io0		6
+	ref_io1		7
+	ref_pix		8
+	ref_hsadc	9
+	ref_gpmi	10
+	saif0_sel	11
+	saif1_sel	12
+	gpmi_sel	13
+	ssp0_sel	14
+	ssp1_sel	15
+	ssp2_sel	16
+	ssp3_sel	17
+	emi_sel		18
+	etm_sel		19
+	lcdif_sel	20
+	cpu		21
+	ptp_sel		22
+	cpu_pll		23
+	cpu_xtal	24
+	hbus		25
+	xbus		26
+	ssp0_div	27
+	ssp1_div	28
+	ssp2_div	29
+	ssp3_div	30
+	gpmi_div	31
+	emi_pll		32
+	emi_xtal	33
+	lcdif_div	34
+	etm_div		35
+	ptp		36
+	saif0_div	37
+	saif1_div	38
+	clk32k_div	39
+	rtc		40
+	lradc		41
+	spdif_div	42
+	clk32k		43
+	pwm		44
+	uart		45
+	ssp0		46
+	ssp1		47
+	ssp2		48
+	ssp3		49
+	gpmi		50
+	spdif		51
+	emi		52
+	saif0		53
+	saif1		54
+	lcdif		55
+	etm		56
+	fec		57
+	can0		58
+	can1		59
+	usb0		60
+	usb1		61
+	usb0_pwr	62
+	usb1_pwr	63
+	enet_out	64
+
+Examples:
+
+clks: clkctrl at 80040000 {
+	compatible = "fsl,imx28-clkctrl";
+	reg = <0x80040000 0x2000>;
+	#clock-cells = <1>;
+	clock-output-names =
+		...
+		"uart",		/* 45 */
+		...
+		"end_of_list";
+};
+
+auart0: serial at 8006a000 {
+	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+	reg = <0x8006a000 0x2000>;
+	interrupts = <112 70 71>;
+	clocks = <&clks 45>;
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d19..4098309 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -65,6 +65,7 @@
 			dma-apbh at 80004000 {
 				compatible = "fsl,imx28-dma-apbh";
 				reg = <0x80004000 0x2000>;
+				clocks = <&clks 25>;
 			};
 
 			perfmon at 80006000 {
@@ -81,6 +82,7 @@
 				reg-names = "gpmi-nand", "bch";
 				interrupts = <88>, <41>;
 				interrupt-names = "gpmi-dma", "bch";
+				clocks = <&clks 50>;
 				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -88,6 +90,7 @@
 			ssp0: ssp at 80010000 {
 				reg = <0x80010000 0x2000>;
 				interrupts = <96 82>;
+				clocks = <&clks 46>;
 				fsl,ssp-dma-channel = <0>;
 				status = "disabled";
 			};
@@ -95,6 +98,7 @@
 			ssp1: ssp at 80012000 {
 				reg = <0x80012000 0x2000>;
 				interrupts = <97 83>;
+				clocks = <&clks 47>;
 				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
@@ -102,6 +106,7 @@
 			ssp2: ssp at 80014000 {
 				reg = <0x80014000 0x2000>;
 				interrupts = <98 84>;
+				clocks = <&clks 48>;
 				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
@@ -109,6 +114,7 @@
 			ssp3: ssp at 80016000 {
 				reg = <0x80016000 0x2000>;
 				interrupts = <99 85>;
+				clocks = <&clks 49>;
 				fsl,ssp-dma-channel = <3>;
 				status = "disabled";
 			};
@@ -523,6 +529,7 @@
 			dma-apbx at 80024000 {
 				compatible = "fsl,imx28-dma-apbx";
 				reg = <0x80024000 0x2000>;
+				clocks = <&clks 26>;
 			};
 
 			dcp at 80028000 {
@@ -551,6 +558,7 @@
 				compatible = "fsl,imx28-lcdif";
 				reg = <0x80030000 0x2000>;
 				interrupts = <38 86>;
+				clocks = <&clks 55>;
 				status = "disabled";
 			};
 
@@ -558,6 +566,8 @@
 				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
 				reg = <0x80032000 0x2000>;
 				interrupts = <8>;
+				clocks = <&clks 58>, <&clks 58>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -565,6 +575,8 @@
 				compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
 				reg = <0x80034000 0x2000>;
 				interrupts = <9>;
+				clocks = <&clks 59>, <&clks 59>;
+				clock-names = "ipg", "per";
 				status = "disabled";
 			};
 
@@ -611,15 +623,17 @@
 			reg = <0x80040000 0x40000>;
 			ranges;
 
-			clkctl at 80040000 {
+			clks: clkctrl at 80040000 {
+				compatible = "fsl,imx28-clkctrl";
 				reg = <0x80040000 0x2000>;
-				status = "disabled";
+				#clock-cells = <1>;
 			};
 
 			saif0: saif at 80042000 {
 				compatible = "fsl,imx28-saif";
 				reg = <0x80042000 0x2000>;
 				interrupts = <59 80>;
+				clocks = <&clks 53>;
 				fsl,saif-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -633,6 +647,7 @@
 				compatible = "fsl,imx28-saif";
 				reg = <0x80046000 0x2000>;
 				interrupts = <58 81>;
+				clocks = <&clks 54>;
 				fsl,saif-dma-channel = <5>;
 				status = "disabled";
 			};
@@ -677,6 +692,7 @@
 			pwm: pwm at 80064000 {
 				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
 				reg = <0x80064000 0x2000>;
+				clocks = <&clks 44>;
 				#pwm-cells = <2>;
 				fsl,pwm-number = <8>;
 				status = "disabled";
@@ -691,6 +707,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006a000 0x2000>;
 				interrupts = <112 70 71>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -698,6 +715,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006c000 0x2000>;
 				interrupts = <113 72 73>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -705,6 +723,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x8006e000 0x2000>;
 				interrupts = <114 74 75>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -712,6 +731,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x80070000 0x2000>;
 				interrupts = <115 76 77>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -719,6 +739,7 @@
 				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
 				reg = <0x80072000 0x2000>;
 				interrupts = <116 78 79>;
+				clocks = <&clks 45>;
 				status = "disabled";
 			};
 
@@ -726,18 +747,22 @@
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x80074000 0x1000>;
 				interrupts = <47>;
+				clocks = <&clks 45>, <&clks 26>;
+				clock-names = "uart", "apb_pclk";
 				status = "disabled";
 			};
 
 			usbphy0: usbphy at 8007c000 {
 				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
 				reg = <0x8007c000 0x2000>;
+				clocks = <&clks 62>;
 				status = "disabled";
 			};
 
 			usbphy1: usbphy at 8007e000 {
 				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
 				reg = <0x8007e000 0x2000>;
+				clocks = <&clks 63>;
 				status = "disabled";
 			};
 		};
@@ -754,6 +779,7 @@
 			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
 			reg = <0x80080000 0x10000>;
 			interrupts = <93>;
+			clocks = <&clks 60>;
 			fsl,usbphy = <&usbphy0>;
 			status = "disabled";
 		};
@@ -762,6 +788,7 @@
 			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
 			reg = <0x80090000 0x10000>;
 			interrupts = <92>;
+			clocks = <&clks 61>;
 			fsl,usbphy = <&usbphy1>;
 			status = "disabled";
 		};
@@ -775,6 +802,8 @@
 			compatible = "fsl,imx28-fec";
 			reg = <0x800f0000 0x4000>;
 			interrupts = <101>;
+			clocks = <&clks 57>, <&clks 57>;
+			clock-names = "ipg", "ahb";
 			status = "disabled";
 		};
 
@@ -782,6 +811,8 @@
 			compatible = "fsl,imx28-fec";
 			reg = <0x800f4000 0x4000>;
 			interrupts = <102>;
+			clocks = <&clks 57>, <&clks 57>;
+			clock-names = "ipg", "ahb";
 			status = "disabled";
 		};
 
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67..613e76f 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx28.h>
 #include "clk.h"
@@ -120,90 +121,6 @@ static void __init clk_misc_init(void)
 	writel_relaxed(val, FRAC0);
 }
 
-static struct clk_lookup uart_lookups[] = {
-	{ .dev_id = "duart", },
-	{ .dev_id = "mxs-auart.0", },
-	{ .dev_id = "mxs-auart.1", },
-	{ .dev_id = "mxs-auart.2", },
-	{ .dev_id = "mxs-auart.3", },
-	{ .dev_id = "mxs-auart.4", },
-	{ .dev_id = "8006a000.serial", },
-	{ .dev_id = "8006c000.serial", },
-	{ .dev_id = "8006e000.serial", },
-	{ .dev_id = "80070000.serial", },
-	{ .dev_id = "80072000.serial", },
-	{ .dev_id = "80074000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-	{ .dev_id = "imx28-dma-apbh", },
-	{ .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-	{ .dev_id = "duart", .con_id = "apb_pclk"},
-	{ .dev_id = "80074000.serial", .con_id = "apb_pclk"},
-	{ .dev_id = "imx28-dma-apbx", },
-	{ .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp0_lookups[] = {
-	{ .dev_id = "imx28-mmc.0", },
-	{ .dev_id = "80010000.ssp", },
-};
-
-static struct clk_lookup ssp1_lookups[] = {
-	{ .dev_id = "imx28-mmc.1", },
-	{ .dev_id = "80012000.ssp", },
-};
-
-static struct clk_lookup ssp2_lookups[] = {
-	{ .dev_id = "imx28-mmc.2", },
-	{ .dev_id = "80014000.ssp", },
-};
-
-static struct clk_lookup ssp3_lookups[] = {
-	{ .dev_id = "imx28-mmc.3", },
-	{ .dev_id = "80016000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-	{ .dev_id = "imx28-fb", },
-	{ .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-	{ .dev_id = "imx28-gpmi-nand", },
-	{ .dev_id = "8000c000.gpmi-nand", },
-};
-
-static struct clk_lookup fec_lookups[] = {
-	{ .dev_id = "imx28-fec.0", },
-	{ .dev_id = "imx28-fec.1", },
-	{ .dev_id = "800f0000.ethernet", },
-	{ .dev_id = "800f4000.ethernet", },
-};
-
-static struct clk_lookup can0_lookups[] = {
-	{ .dev_id = "flexcan.0", },
-	{ .dev_id = "80032000.can", },
-};
-
-static struct clk_lookup can1_lookups[] = {
-	{ .dev_id = "flexcan.1", },
-	{ .dev_id = "80034000.can", },
-};
-
-static struct clk_lookup saif0_lookups[] = {
-	{ .dev_id = "mxs-saif.0", },
-	{ .dev_id = "80042000.saif", },
-};
-
-static struct clk_lookup saif1_lookups[] = {
-	{ .dev_id = "mxs-saif.1", },
-	{ .dev_id = "80046000.saif", },
-};
-
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
@@ -228,6 +145,7 @@ enum imx28_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx28_clk clks_init_on[] __initdata = {
 	cpu, hbus, xbus, emi, uart,
@@ -235,6 +153,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
 
 int __init mx28_clocks_init(void)
 {
+	struct device_node *np;
 	int i;
 
 	clk_misc_init();
@@ -312,27 +231,15 @@ int __init mx28_clocks_init(void)
 			return PTR_ERR(clks[i]);
 		}
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
+	if (np) {
+		clk_data.clks = clks;
+		clk_data.clk_num = ARRAY_SIZE(clks);
+		of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+	}
+
 	clk_register_clkdev(clks[clk32k], NULL, "timrot");
 	clk_register_clkdev(clks[enet_out], NULL, "enet_out");
-	clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-	clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-	clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-	clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-	clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
-	clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
-	clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
-	clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
-	clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-	clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
-	clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
-	clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
-	clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
-	clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
-	clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
-	clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
-	clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
-	clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
-	clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
-- 
1.7.5.4



From shawn.guo at linaro.org  Wed Aug 22 09:36:30 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:36:30 +0800
Subject: [PATCH v2 4/4] clk: mxs: replace imx23 clk_register_clkdev with clock
 DT lookup
In-Reply-To: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1345642590-29905-5-git-send-email-shawn.guo@linaro.org>

It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx23 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/clock/imx23-clock.txt      |   76 ++++++++++++++++++++
 arch/arm/boot/dts/imx23.dtsi                       |   16 ++++-
 drivers/clk/mxs/clk-imx23.c                        |   55 +++------------
 3 files changed, 100 insertions(+), 47 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx23-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 0000000..a0b867e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,76 @@
+* Clock bindings for Freescale i.MX23
+
+Required properties:
+- compatible: Should be "fsl,imx23-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX23
+clocks and IDs.
+
+	Clock		ID
+	------------------
+	ref_xtal	0
+	pll		1
+	ref_cpu		2
+	ref_emi		3
+	ref_pix		4
+	ref_io		5
+	saif_sel	6
+	lcdif_sel	7
+	gpmi_sel	8
+	ssp_sel		9
+	emi_sel		10
+	cpu		11
+	etm_sel		12
+	cpu_pll		13
+	cpu_xtal	14
+	hbus		15
+	xbus		16
+	lcdif_div	17
+	ssp_div		18
+	gpmi_div	19
+	emi_pll		20
+	emi_xtal	21
+	etm_div		22
+	saif_div	23
+	clk32k_div	24
+	rtc		25
+	adc		26
+	spdif_div	27
+	clk32k		28
+	dri		29
+	pwm		30
+	filt		31
+	uart		32
+	ssp		33
+	gpmi		34
+	spdif		35
+	emi		36
+	saif		37
+	lcdif		38
+	etm		39
+	usb		40
+	usb_pwr		41
+
+Examples:
+
+clks: clkctrl at 80040000 {
+	compatible = "fsl,imx23-clkctrl";
+	reg = <0x80040000 0x2000>;
+	#clock-cells = <1>;
+	clock-output-names =
+		...
+		"uart",		/* 32 */
+		...
+		"end_of_list";
+};
+
+auart0: serial at 8006c000 {
+	compatible = "fsl,imx23-auart";
+	reg = <0x8006c000 0x2000>;
+	interrupts = <24 25 23>;
+	clocks = <&clks 32>;
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e613831..ba55bee 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
 			dma-apbh at 80004000 {
 				compatible = "fsl,imx23-dma-apbh";
 				reg = <0x80004000 0x2000>;
+				clocks = <&clks 15>;
 			};
 
 			ecc at 80008000 {
@@ -67,6 +68,7 @@
 				reg-names = "gpmi-nand", "bch";
 				interrupts = <13>, <56>;
 				interrupt-names = "gpmi-dma", "bch";
+				clocks = <&clks 34>;
 				fsl,gpmi-dma-channel = <4>;
 				status = "disabled";
 			};
@@ -74,6 +76,7 @@
 			ssp0: ssp at 80010000 {
 				reg = <0x80010000 0x2000>;
 				interrupts = <15 14>;
+				clocks = <&clks 33>;
 				fsl,ssp-dma-channel = <1>;
 				status = "disabled";
 			};
@@ -280,6 +283,7 @@
 			dma-apbx at 80024000 {
 				compatible = "fsl,imx23-dma-apbx";
 				reg = <0x80024000 0x2000>;
+				clocks = <&clks 16>;
 			};
 
 			dcp at 80028000 {
@@ -306,12 +310,14 @@
 				compatible = "fsl,imx23-lcdif";
 				reg = <0x80030000 2000>;
 				interrupts = <46 45>;
+				clocks = <&clks 38>;
 				status = "disabled";
 			};
 
 			ssp1: ssp at 80034000 {
 				reg = <0x80034000 0x2000>;
 				interrupts = <2 20>;
+				clocks = <&clks 33>;
 				fsl,ssp-dma-channel = <2>;
 				status = "disabled";
 			};
@@ -329,9 +335,10 @@
 			reg = <0x80040000 0x40000>;
 			ranges;
 
-			clkctl at 80040000 {
+			clks: clkctrl at 80040000 {
+				compatible = "fsl,imx23-clkctrl";
 				reg = <0x80040000 0x2000>;
-				status = "disabled";
+				#clock-cells = <1>;
 			};
 
 			saif0: saif at 80042000 {
@@ -383,6 +390,7 @@
 			pwm: pwm at 80064000 {
 				compatible = "fsl,imx23-pwm";
 				reg = <0x80064000 0x2000>;
+				clocks = <&clks 30>;
 				#pwm-cells = <2>;
 				fsl,pwm-number = <5>;
 				status = "disabled";
@@ -397,6 +405,7 @@
 				compatible = "fsl,imx23-auart";
 				reg = <0x8006c000 0x2000>;
 				interrupts = <24 25 23>;
+				clocks = <&clks 32>;
 				status = "disabled";
 			};
 
@@ -404,6 +413,7 @@
 				compatible = "fsl,imx23-auart";
 				reg = <0x8006e000 0x2000>;
 				interrupts = <59 60 58>;
+				clocks = <&clks 32>;
 				status = "disabled";
 			};
 
@@ -411,6 +421,8 @@
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x80070000 0x2000>;
 				interrupts = <0>;
+				clocks = <&clks 32>, <&clks 16>;
+				clock-names = "uart", "apb_pclk";
 				status = "disabled";
 			};
 
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0..9f6d155 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx23.h>
 #include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
 	__mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
 }
 
-static struct clk_lookup uart_lookups[] = {
-	{ .dev_id = "duart", },
-	{ .dev_id = "mxs-auart.0", },
-	{ .dev_id = "mxs-auart.1", },
-	{ .dev_id = "8006c000.serial", },
-	{ .dev_id = "8006e000.serial", },
-	{ .dev_id = "80070000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-	{ .dev_id = "imx23-dma-apbh", },
-	{ .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-	{ .dev_id = "duart", .con_id = "apb_pclk"},
-	{ .dev_id = "80070000.serial", .con_id = "apb_pclk"},
-	{ .dev_id = "imx23-dma-apbx", },
-	{ .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp_lookups[] = {
-	{ .dev_id = "imx23-mmc.0", },
-	{ .dev_id = "imx23-mmc.1", },
-	{ .dev_id = "80010000.ssp", },
-	{ .dev_id = "80034000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-	{ .dev_id = "imx23-fb", },
-	{ .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-	{ .dev_id = "imx23-gpmi-nand", },
-	{ .dev_id = "8000c000.gpmi-nand", },
-};
-
 static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
@@ -127,6 +90,7 @@ enum imx23_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx23_clk clks_init_on[] __initdata = {
 	cpu, hbus, xbus, emi, uart,
@@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
 
 int __init mx23_clocks_init(void)
 {
+	struct device_node *np;
 	int i;
 
 	clk_misc_init();
@@ -188,14 +153,14 @@ int __init mx23_clocks_init(void)
 			return PTR_ERR(clks[i]);
 		}
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
+	if (np) {
+		clk_data.clks = clks;
+		clk_data.clk_num = ARRAY_SIZE(clks);
+		of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+	}
+
 	clk_register_clkdev(clks[clk32k], NULL, "timrot");
-	clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-	clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-	clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-	clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-	clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
-	clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-	clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
 
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 22 09:36:48 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 15:36:48 +0200
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool
 with GFP_ATOMIC
In-Reply-To: <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com><1345630830-9586-3-git-send-email-hdoyu@nvidia.com><CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
Message-ID: <20120822.163648.3800987367886904.hdoyu@nvidia.com>

Hi,

KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00 +0200:

> vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic context.

Right.

I've been thinking that kzalloc() may be enough here, since
vzalloc() was introduced to avoid allocation failure for big chunk of
memory, but I think that it's unlikely that the number of page array
can be so big. So I propose to drop vzalloc() here, and just simply to
use kzalloc only as below(*1).

For example, 

1920(H) x 1080(W) x 4(bytes) ~= 8MiB

For 8 MiB buffer,
  8(MiB) * 1024 = 8192(KiB)
  8192(KiB) / 4(KiB/page) = 2048 pages
  sizeof(struct page *) = 4 bytes
  2048(pages) * 4(bytes/page) = 8192(bytes) = 8(KiB)
  8(KiB) / 4(KiB/page) = 2 pages

If the above estimation is right(I hope;)), the necessary pages are
_at most_ 2 pages. If the system gets into the situation to fail to
allocate 2 contiguous pages, that's real the problem. I guess that
that kind of fragmentation problem would be solved with page migration
or something, especially nowadays devices are getting larger memories.

*1:
>From a613c40d1b3d4fb1577cdb0807a74e8dbd08a3e6 Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu <hdoyu at nvidia.com>
Date: Wed, 22 Aug 2012 16:25:54 +0300
Subject: [PATCH 1/1] ARM: dma-mapping: Use only kzalloc without vzalloc

Use only kzalloc for atomic allocation.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4656c0f..d4f1cf2 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1083,10 +1083,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 	int count = size >> PAGE_SHIFT;
 	int array_size = count * sizeof(struct page *);
 
-	if (array_size <= PAGE_SIZE)
-		pages = kzalloc(array_size, gfp);
-	else
-		pages = vzalloc(array_size);
+	pages = kzalloc(array_size, gfp);
 	if (!pages)
 		return NULL;
 
@@ -1107,10 +1104,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 
 	return pages;
 error:
-	if (array_size <= PAGE_SIZE)
-		kfree(pages);
-	else
-		vfree(pages);
+	kfree(pages);
 	return NULL;
 }
 
-- 
1.7.5.4


From linux at prisktech.co.nz  Wed Aug 22 09:33:52 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Wed, 22 Aug 2012 13:33:52 +0000
Subject: [rtc-linux] [PATCHv3 8/9] arm: vt8500: gpio: Devicetree support
 for arch-vt8500
In-Reply-To: <CACRpkdZnQyLSRQ6cRpFBurAv2cv44einGAsT86FLCqsj1euDMA@mail.gmail.com>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-9-git-send-email-linux@prisktech.co.nz>,
 <CACRpkdZnQyLSRQ6cRpFBurAv2cv44einGAsT86FLCqsj1euDMA@mail.gmail.com>
Message-ID: <76F764B079F92A4E843589C893D0A022DAF67144@SERVER.prisktech.co.nz>

>> Converted the existing arch-vt8500 gpio to a platform_device.
>> Added support for WM8505 and WM8650 GPIO controllers.
>(...)
>> +       unsigned val;

>I asked about the datatype for this "val", it sure isn't "unsigned".

>I suspected the registers were only 8bit and so it should be u8.
>But atleast use u32 if you must use all these bits.

Sorry - missed adding this to my list of fixes. I've used u32 as the
datasheet advises these are 32-bit registers and must be
read/written as such.
Changes included in v4.

>(...)
>> +       val = readl(vt8500_chip->base + vt8500_chip->regs->en);
>> +       val |= BIT(offset);
>> +       writel(val, vt8500_chip->base + vt8500_chip->regs->en);

>BTW: have you considered [readl|writel]_relaxed?

I haven't - and to be honest I didn't know what difference it would
make until I read up on it.
Most of this code already existed in mainline in
arch/arm/mach-vt8500/gpio.c and I simply moved it across to
drivers/gpio and made some changes/additions. Having looked,
I don't see any reason why it can't use the _relaxed variants.
Changes included in v4.


I'll post up v4 for review when I get home in about 7 hours.

Work always gets in the way of being productive :)


Regards

Tony Prisk

From gururaja.hebbar at ti.com  Wed Aug 22 09:50:09 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 22 Aug 2012 13:50:09 +0000
Subject: [PATCH 3/5] ASoC: Davinci: pcm: Add device tree bindings
In-Reply-To: <20120817223122.GA21445@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>
 <20120817223122.GA21445@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA67DA1@DBDE01.ent.ti.com>

On Sat, Aug 18, 2012 at 04:01:24, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 06:12:03PM +0530, Hebbar, Gururaja wrote:
> > Device tree support for Davinci/OMAP2+ pcm driver.
> 
> This looks like it's a device which maps a shared DMA controller in the
> SoC core into ASoC rather than actual hardware.  Such devices are
> usually instantiated automatically from the DAI rather than being
> represented in the device tree since they are a Linux internal thing
> really - the Tegra and Freescale drivers provide examples of how this
> sort of thing can be done.

>From your for-3.7 branch, I could only find such implementation in Tegra
Platform. 
Most Freescale platforms implements this through a device/driver method.
Exception being sound/soc/mxs/mxs-pcm.c

So should I follow tegra implementation?
> 


Regards, 
Gururaja


From shawn.guo at linaro.org  Wed Aug 22 09:58:07 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 21:58:07 +0800
Subject: [PATCH] ARM: dts: imx51-babbage: fix esdhc cd/wp properties
Message-ID: <1345643887-30606-1-git-send-email-shawn.guo@linaro.org>

The binding doc and dts use properties "fsl,{cd,wp}-internal" while
esdhc driver uses "fsl,{cd,wp}-controller".  Fix binding doc and dts
to get them match driver code.

Reported-by: Chris Ball <cjb at laptop.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Cc: <stable at vger.kernel.org>
---
 .../devicetree/bindings/mmc/fsl-imx-esdhc.txt      |    8 ++++----
 arch/arm/boot/dts/imx51-babbage.dts                |    4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 70cd49b..1dd6225 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -10,8 +10,8 @@ Required properties:
 - compatible : Should be "fsl,<chip>-esdhc"
 
 Optional properties:
-- fsl,cd-internal : Indicate to use controller internal card detection
-- fsl,wp-internal : Indicate to use controller internal write protection
+- fsl,cd-controller : Indicate to use controller internal card detection
+- fsl,wp-controller : Indicate to use controller internal write protection
 
 Examples:
 
@@ -19,8 +19,8 @@ esdhc at 70004000 {
 	compatible = "fsl,imx51-esdhc";
 	reg = <0x70004000 0x4000>;
 	interrupts = <1>;
-	fsl,cd-internal;
-	fsl,wp-internal;
+	fsl,cd-controller;
+	fsl,wp-controller;
 };
 
 esdhc at 70008000 {
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cd86177..59d9789 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,8 +25,8 @@
 		aips at 70000000 { /* aips-1 */
 			spba at 70000000 {
 				esdhc at 70004000 { /* ESDHC1 */
-					fsl,cd-internal;
-					fsl,wp-internal;
+					fsl,cd-controller;
+					fsl,wp-controller;
 					status = "okay";
 				};
 
-- 
1.7.5.4



From cjb at laptop.org  Wed Aug 22 10:02:48 2012
From: cjb at laptop.org (Chris Ball)
Date: Wed, 22 Aug 2012 10:02:48 -0400
Subject: [PATCH] ARM: dts: imx51-babbage: fix esdhc cd/wp properties
In-Reply-To: <1345643887-30606-1-git-send-email-shawn.guo@linaro.org> (Shawn
 Guo's message of "Wed, 22 Aug 2012 21:58:07 +0800")
References: <1345643887-30606-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <87pq6j3tyv.fsf@octavius.laptop.org>

Hi,

(removing stable@ from e-mail)

On Wed, Aug 22 2012, Shawn Guo wrote:
> The binding doc and dts use properties "fsl,{cd,wp}-internal" while
> esdhc driver uses "fsl,{cd,wp}-controller".  Fix binding doc and dts
> to get them match driver code.
>
> Reported-by: Chris Ball <cjb at laptop.org>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: <stable at vger.kernel.org>
> ---
>  .../devicetree/bindings/mmc/fsl-imx-esdhc.txt      |    8 ++++----
>  arch/arm/boot/dts/imx51-babbage.dts                |    4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)

Want to take this through your own tree, to avoid .dts conflicts later?
If so:

Acked-by: Chris Ball <cjb at laptop.org>

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From arnd at arndb.de  Wed Aug 22 10:29:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 16:29:38 +0200
Subject: [PATCH 2/4] ARM: allow PID_IN_CONTEXTIDR only for ARMv7
In-Reply-To: <1345645780-2749-1-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
Message-ID: <1345645780-2749-3-git-send-email-arnd@arndb.de>

When ARMv6 is enabled, we build the kernel with -march=armv6 or
-march=armv6k, which means the bfi instruction is not available.
Instead, it only works with -march=armv6t2 or -march=armv7-a.

Without this patch, building rand-enIHAOL results in:

/tmp/ccwCsCXC.s: Assembler messages:
/tmp/ccwCsCXC.s:49: Error: selected processor does not support ARM mode `bfi r3,r2,#0,#8'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/Kconfig.debug |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f15f82b..11b9ff4 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -398,6 +398,7 @@ config ARM_KPROBES_TEST
 config PID_IN_CONTEXTIDR
 	bool "Write the current PID to the CONTEXTIDR register"
 	depends on CPU_COPY_V6
+	depends on CPU_V7 && !CPU_V6
 	help
 	  Enabling this option causes the kernel to write the current PID to
 	  the PROCID field of the CONTEXTIDR register, at the expense of some
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 10:29:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 16:29:37 +0200
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <1345645780-2749-1-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
Message-ID: <1345645780-2749-2-git-send-email-arnd@arndb.de>

read_current_timer is used in the get_cycles() function when
ARM_ARCH_TIMER is set, and that function can be inlined into
driver modules, so we should export the function to avoid
errors like

ERROR: "read_current_timer" [drivers/video/udlfb.ko] undefined!
ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/kernel/arch_timer.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf25880..6327d1f 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -14,6 +14,7 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/cpu.h>
+#include <linux/export.h>
 #include <linux/jiffies.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -232,6 +233,7 @@ int read_current_timer(unsigned long *timer_val)
 	*timer_val = arch_counter_get_cntpct();
 	return 0;
 }
+EXPORT_SYMBOL_GPL(read_current_timer);
 
 static struct clocksource clocksource_counter = {
 	.name	= "arch_sys_counter",
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 10:29:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 16:29:40 +0200
Subject: [PATCH 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <1345645780-2749-1-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
Message-ID: <1345645780-2749-5-git-send-email-arnd@arndb.de>

The mls instruction is not available in ARMv6K or below, so we
should make the test conditional on at least ARMv7. ldrex/strex
are available in ARMv6K or ARMv7, which we can test by checking
the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.

/tmp/ccuMTZ8D.s: Assembler messages:
/tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
/tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
/tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Jon Medhurst <tixy at yxit.co.uk>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Leif Lindholm <leif.lindholm at arm.com>
---
 arch/arm/kernel/kprobes-test-arm.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 38c1a3b..3e87ff7 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
 	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
 
+#if __LINUX_ARM_ARCH__ >= 7
 	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
 	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
 	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
+#endif
 	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
@@ -454,7 +456,7 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word	0xe1500090") /* Unallocated space */
 	TEST_UNSUPPORTED(".word	0xe1600090") /* Unallocated space */
 	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
-#if __LINUX_ARM_ARCH__ >= 6
+#ifdef CONFIG_CPU_32v6K
 	TEST_UNSUPPORTED("ldrex	r2, [sp]")
 	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
 	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 10:29:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 16:29:39 +0200
Subject: [PATCH 3/4] ARM: export set_irq_flags/irq_set_chip_and_handler
In-Reply-To: <1345645780-2749-1-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
Message-ID: <1345645780-2749-4-git-send-email-arnd@arndb.de>

The recently added Emma Mobile GPIO driver calls set_irq_flags
and irq_set_chip_and_handler for the interrupts it exports and
it can be built as a module, which currently fails with

ERROR: "set_irq_flags" [drivers/gpio/gpio-em.ko] undefined!
ERROR: "irq_set_chip_and_handler_name" [drivers/gpio/gpio-em.ko] undefined!

We either need to replace the call to set_irq_flags with something
else or export that function. This patch does the latter.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Magnus Damm <damm at opensource.se>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/kernel/irq.c |    2 ++
 kernel/irq/chip.c     |    2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 16cedb4..8961650 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -34,6 +34,7 @@
 #include <linux/list.h>
 #include <linux/kallsyms.h>
 #include <linux/proc_fs.h>
+#include <linux/export.h>
 
 #include <asm/exception.h>
 #include <asm/mach/arch.h>
@@ -109,6 +110,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 	/* Order is clear bits in "clr" then set bits in "set" */
 	irq_modify_status(irq, clr, set & ~clr);
 }
+EXPORT_SYMBOL_GPL(set_irq_flags);
 
 void __init init_IRQ(void)
 {
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index eebd6d5..3c3cea3 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/msi.h>
 #include <linux/module.h>
+#include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 
@@ -671,6 +672,7 @@ irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
 	irq_set_chip(irq, chip);
 	__irq_set_handler(irq, handle, 0, name);
 }
+EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
 
 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
 {
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 10:29:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 16:29:36 +0200
Subject: [PATCH 0/4] ARM: patches for randconfig build errors
Message-ID: <1345645780-2749-1-git-send-email-arnd@arndb.de>

Hi Russell,

I've done some testing with the experimental multiplatform tree
and that uncovered a few preexisting bugs. Here are the ones
that should go through your tree. Please have a look to
see if the fixes make sense. I can put the patches in the patch
tracker or send you a pull request then.

	Arnd
---
Cc: Jon Medhurst <tixy at yxit.co.uk>
Cc: Leif Lindholm <leif.lindholm at arm.com>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Magnus Damm <damm at opensource.se>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Rafael J. Wysocki <rjw at sisk.pl>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Will Deacon <will.deacon at arm.com>

Arnd Bergmann (4):
  ARM: export read_current_timer
  ARM: allow PID_IN_CONTEXTIDR only for ARMv7
  ARM: export set_irq_flags/irq_set_chip_and_handler
  ARM: kprobes: make more tests conditional

 arch/arm/Kconfig.debug             |    1 +
 arch/arm/kernel/arch_timer.c       |    2 ++
 arch/arm/kernel/irq.c              |    2 ++
 arch/arm/kernel/kprobes-test-arm.c |    4 +++-
 kernel/irq/chip.c                  |    2 ++
 5 files changed, 10 insertions(+), 1 deletion(-)

-- 
1.7.10



From will.deacon at arm.com  Wed Aug 22 10:39:46 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 Aug 2012 15:39:46 +0100
Subject: [PATCH 2/4] ARM: allow PID_IN_CONTEXTIDR only for ARMv7
In-Reply-To: <1345645780-2749-3-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-3-git-send-email-arnd@arndb.de>
Message-ID: <20120822143946.GM9093@mudshark.cambridge.arm.com>

Hi Arnd,

On Wed, Aug 22, 2012 at 03:29:38PM +0100, Arnd Bergmann wrote:
> When ARMv6 is enabled, we build the kernel with -march=armv6 or
> -march=armv6k, which means the bfi instruction is not available.
> Instead, it only works with -march=armv6t2 or -march=armv7-a.
> 
> Without this patch, building rand-enIHAOL results in:
> 
> /tmp/ccwCsCXC.s: Assembler messages:
> /tmp/ccwCsCXC.s:49: Error: selected processor does not support ARM mode `bfi r3,r2,#0,#8'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Will Deacon <will.deacon at arm.com>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  arch/arm/Kconfig.debug |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index f15f82b..11b9ff4 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -398,6 +398,7 @@ config ARM_KPROBES_TEST
>  config PID_IN_CONTEXTIDR
>  	bool "Write the current PID to the CONTEXTIDR register"
>  	depends on CPU_COPY_V6
> +	depends on CPU_V7 && !CPU_V6
>  	help
>  	  Enabling this option causes the kernel to write the current PID to
>  	  the PROCID field of the CONTEXTIDR register, at the expense of some

Nah, I'll fix the contextidr_notifier instead. I forgot that this stuff gets
used on non-SMP v6 platforms.

Cheers,

Will


From nicolas.pitre at linaro.org  Wed Aug 22 10:42:40 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 10:42:40 -0400 (EDT)
Subject: [PATCH 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <1345645780-2749-5-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-5-git-send-email-arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221040250.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> The mls instruction is not available in ARMv6K or below, so we
> should make the test conditional on at least ARMv7. ldrex/strex
> are available in ARMv6K or ARMv7, which we can test by checking
> the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.

The ldrex/strex instructions are available on ARMv6.  It's only the d 
variants (strexd/ldrexd) which are only available from ARMv6k.


Nicolas


From arnd at arndb.de  Wed Aug 22 10:44:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 14:44:42 +0000
Subject: [PATCH 2/4] ARM: allow PID_IN_CONTEXTIDR only for ARMv7
In-Reply-To: <20120822143946.GM9093@mudshark.cambridge.arm.com>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-3-git-send-email-arnd@arndb.de>
 <20120822143946.GM9093@mudshark.cambridge.arm.com>
Message-ID: <201208221444.42668.arnd@arndb.de>

On Wednesday 22 August 2012, Will Deacon wrote:
> > @@ -398,6 +398,7 @@ config ARM_KPROBES_TEST
> >  config PID_IN_CONTEXTIDR
> >       bool "Write the current PID to the CONTEXTIDR register"
> >       depends on CPU_COPY_V6
> > +     depends on CPU_V7 && !CPU_V6
> >       help
> >         Enabling this option causes the kernel to write the current PID to
> >         the PROCID field of the CONTEXTIDR register, at the expense of some
> 
> Nah, I'll fix the contextidr_notifier instead. I forgot that this stuff gets
> used on non-SMP v6 platforms.
> 

Ok, thanks!

	Arnd


From hdoyu at nvidia.com  Wed Aug 22 10:44:29 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 16:44:29 +0200
Subject: [RFC 0/4] ARM: dma-mapping: IOMMU atomic allocation
In-Reply-To: <005901cd805e$4afd2e40$e0f78ac0$%szyprowski@samsung.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com><005901cd805e$4afd2e40$e0f78ac0$%szyprowski@samsung.com>
Message-ID: <20120822.174429.909991514856769456.hdoyu@nvidia.com>

Hi Marek,

Marek Szyprowski <m.szyprowski at samsung.com> wrote @ Wed, 22 Aug 2012 14:04:26 +0200:

> Hi Hiroshi,
> 
> On Wednesday, August 22, 2012 12:20 PM Hiroshi Doyu wrote:
> 
> > The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
> > region" breaks the compatibility with existing drivers. This causes
> > the following kernel oops(*1). That driver has called dma_pool_alloc()
> > to allocate memory from the interrupt context, and it hits
> > BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
> > fixes this problem with making use of the pre-allocate atomic memory
> > pool which DMA is using in the same way as DMA does now.
> > 
> > Any comment would be really appreciated.
> 
> I was working on the similar patches, but You were faster. ;-)

Thank you for reviewing my patches.

> Basically the patch no 1 and 2 are fine, but I don't like the changes proposed in 
> patch 3 and 4. You should not alter the attributes provided by the user nor make any
> assumptions that such attributes has been provided - drivers are allowed to call 
> dma_alloc_attrs() directly. Please rework your patches to avoid such
> approach.

Sure. I'll send the series again later.

Instead of making use of DMA_ATTR_NO_KERNEL_MAPPING, I use the
following "__in_atomic_pool()" to see if buffer comes from atomic or
not at freeing.

>From cdf8621fd0876f3e56a55885c27e363893df2c98 Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu <hdoyu at nvidia.com>
Date: Wed, 22 Aug 2012 17:26:29 +0300
Subject: [PATCH 1/1] ARM: dma-mapping: Refactor out to introduce
 __in_atomic_pool

Check the given range("start", "size") is included in "atomic_pool" or not.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   20 +++++++++++++++-----
 1 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 30bef80..26080ef 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -450,20 +450,30 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
-static int __free_from_pool(void *start, size_t size)
+static bool __in_atomic_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
-	unsigned long pageno, count;
-	unsigned long flags;
 
 	if (start < pool->vaddr || start > pool->vaddr + pool->size)
-		return 0;
+		return false;
 
 	if (start + size > pool->vaddr + pool->size) {
 		WARN(1, "freeing wrong coherent size from pool\n");
-		return 0;
+		return false;
 	}
 
+	return true;
+}
+
+static int __free_from_pool(void *start, size_t size)
+{
+	struct dma_pool *pool = &atomic_pool;
+	unsigned long pageno, count;
+	unsigned long flags;
+
+	if (!__in_atomic_pool(start, size))
+		return 0;
+
 	pageno = (start - pool->vaddr) >> PAGE_SHIFT;
 	count = size >> PAGE_SHIFT;
 
-- 
1.7.5.4


From shawn.guo at linaro.org  Wed Aug 22 10:52:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 22:52:18 +0800
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
Message-ID: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>

There is an issue reported on imx6q restart function.  The issue is only
seen with the image building ARMv7 and ARMv6 together, where cpu_relax()
is define to do dmb.  It's been root-caused by Russell as below.

Russell King - ARM Linux wrote:
> I suspect having this dmb inside cpu_relax() is flooding the
> interconnects with traffic, which then prevents other CPUs getting
> a look-in (maybe there's no fairness when it comes to dmb's.

Fix the issue by insert a few NOPs into cpu_relax() where doing dmb.

Cc: <stable at vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/include/asm/processor.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 99afa74..7cc67ce 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
 unsigned long get_wchan(struct task_struct *p);
 
 #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
-#define cpu_relax()			smp_mb()
+#define cpu_relax()		do {					\
+					asm("nop");			\
+					asm("nop");			\
+					asm("nop");			\
+					asm("nop");			\
+					asm("nop");			\
+					smp_mb();			\
+				} while (0)
 #else
 #define cpu_relax()			barrier()
 #endif
-- 
1.7.5.4



From arnd at arndb.de  Wed Aug 22 11:13:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:05 +0200
Subject: [PATCH 1/6] ARM: ux500: don't select LEDS_GPIO for snowball
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-2-git-send-email-arnd@arndb.de>

The gpio leds driver can only be built if the generic LED code is
also enabled. Snowball selects LEDS_GPIO for an unknown reason
but it does not select LEDS_CLASS and also does not really require
the LED support at all, so we can just drop this dependency.

Without this patch, building without LEDS_CLASS esults in:

drivers/built-in.o: In function `create_gpio_led.part.2':
governor_userspace.c:(.devinit.text+0x5a58): undefined reference to `led_classdev_register'
drivers/built-in.o: In function `gpio_led_remove':
governor_userspace.c:(.devexit.text+0x6b8): undefined reference to `led_classdev_unregister'

This reverts 8733f53c6 "ARM: ux500: Kconfig: Compile in leds-gpio
support for Snowball", which was not completely thought through.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/Kconfig |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf..53d3d46 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -41,7 +41,6 @@ config MACH_HREFV60
 config MACH_SNOWBALL
 	bool "U8500 Snowball platform"
 	select MACH_MOP500
-	select LEDS_GPIO
 	help
 	  Include support for the snowball development platform.
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:06 +0200
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-3-git-send-email-arnd@arndb.de>

The new omap4 cpuidle implementation currently requires
ARCH_NEEDS_CPU_IDLE_COUPLED, which only works on SMP.

This patch makes it possible to build a non-SMP kernel
for that platform. This is not normally desired for
end-users but can be useful for testing.

Without this patch, building rand-0y2jSKT results in:

drivers/cpuidle/coupled.c: In function 'cpuidle_coupled_poke':
drivers/cpuidle/coupled.c:317:3: error: implicit declaration of function '__smp_call_function_single' [-Werror=implicit-function-declaration]

It's not clear if this patch is the best solution for
the problem at hand. I have made sure that we can now
build the kernel in all configurations, but that does
not mean it will actually work on an OMAP44xx.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig       |    2 +-
 arch/arm/mach-omap2/cpuidle44xx.c |    3 ++-
 include/linux/cpuidle.h           |    4 ++++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd2db02..66a8be3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -62,7 +62,7 @@ config ARCH_OMAP4
 	select PM_OPP if PM
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select ARM_CPU_SUSPEND if PM
-	select ARCH_NEEDS_CPU_IDLE_COUPLED
+	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
 
 config SOC_OMAP5
 	bool "TI OMAP5"
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index ee05e19..288bee6 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -238,8 +238,9 @@ int __init omap4_idle_init(void)
 	for_each_cpu(cpu_id, cpu_online_mask) {
 		dev = &per_cpu(omap4_idle_dev, cpu_id);
 		dev->cpu = cpu_id;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
 		dev->coupled_cpus = *cpu_online_mask;
-
+#endif
 		cpuidle_register_driver(&omap4_idle_driver);
 
 		if (cpuidle_register_device(dev)) {
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 040b13b..279b1ea 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -194,6 +194,10 @@ static inline int cpuidle_play_dead(void) {return -ENODEV; }
 
 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
 void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a);
+#else
+static inline void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a)
+{
+}
 #endif
 
 /******************************
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:10 +0200
Subject: [PATCH 6/6] ARM: imx: select ARM_CPU_SUSPEND when necessary
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-7-git-send-email-arnd@arndb.de>

On i.MX6, we select ARM_CPU_SUSPEND when building with power management
support, but for some reason this was omitted on i.MX5. Normally we
build kernels for both together so the error only showed up in
randconfig tests.

Without this patch, building imx5 standalone results in:

arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Eric Miao <eric.miao at linaro.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: stable at vger.kernel.org
---
 arch/arm/mach-imx/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..8e96573 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -89,6 +89,7 @@ config SOC_IMX5
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX5
+	select ARM_CPU_SUSPEND if PM
 	bool
 
 config SOC_IMX50
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:08 +0200
Subject: [PATCH 4/6] ARM: imx: fix ksz9021rn_phy_fixup
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-5-git-send-email-arnd@arndb.de>

The ksz9021rn_phy_fixup and mx6q_sabrelite functions try to
set up an ethernet phy if they can. They do check whether
phylib is enabled, but unfortunately the functions can only
be called from platform code if phylib is builtin, not
if it is a module

Without this patch, building with a modular phylib results in:

arch/arm/mach-imx/mach-imx6q.c: In function 'imx6q_sabrelite_init':
arch/arm/mach-imx/mach-imx6q.c:120:5: error: 'ksz9021rn_phy_fixup' undeclared (first use in this function)
arch/arm/mach-imx/mach-imx6q.c:120:5: note: each undeclared identifier is reported only once for each function it appears in

The bug was originally reported by Artem Bityutskiy but only
partially fixed in ef441806 "ARM: imx6q: register phy fixup only when
CONFIG_PHYLIB is enabled".

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Artem Bityutskiy <dedekind1 at gmail.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/mach-imx6q.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608..045b3f6 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -71,7 +71,7 @@ soft:
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
-	if (IS_ENABLED(CONFIG_PHYLIB)) {
+	if (IS_BUILTIN(CONFIG_PHYLIB)) {
 		/* min rx data delay */
 		phy_write(phydev, 0x0b, 0x8105);
 		phy_write(phydev, 0x0c, 0x0000);
@@ -112,7 +112,7 @@ put_clk:
 
 static void __init imx6q_sabrelite_init(void)
 {
-	if (IS_ENABLED(CONFIG_PHYLIB))
+	if (IS_BUILTIN(CONFIG_PHYLIB))
 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 				ksz9021rn_phy_fixup);
 	imx6q_sabrelite_cko1_setup();
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:09 +0200
Subject: [PATCH 5/6] ARM: imx: select CPU_FREQ_TABLE when needed
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-6-git-send-email-arnd@arndb.de>

The i.MX cpufreq implementation uses the CPU_FREQ_TABLE helpers,
so it needs to select that code to be built. This problem has
apparently existed since the i.MX cpufreq code was first merged
in v3.6.37.

Building IMX without CPU_FREQ_TABLE results in:

arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_exit':
arch/arm/plat-mxc/cpufreq.c:173: undefined reference to `cpufreq_frequency_table_put_attr'
arch/arm/plat-mxc/built-in.o: In function `mxc_set_target':
arch/arm/plat-mxc/cpufreq.c:84: undefined reference to `cpufreq_frequency_table_target'
arch/arm/plat-mxc/built-in.o: In function `mxc_verify_speed':
arch/arm/plat-mxc/cpufreq.c:65: undefined reference to `cpufreq_frequency_table_verify'
arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_init':
arch/arm/plat-mxc/cpufreq.c:154: undefined reference to `cpufreq_frequency_table_cpuinfo'
arch/arm/plat-mxc/cpufreq.c:162: undefined reference to `cpufreq_frequency_table_get_attr'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Yong Shen <yong.shen at linaro.org>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: stable at vger.kernel.org
---
 arch/arm/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..84b5a0c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2150,6 +2150,7 @@ source "drivers/cpufreq/Kconfig"
 config CPU_FREQ_IMX
 	tristate "CPUfreq driver for i.MX CPUs"
 	depends on ARCH_MXC && CPU_FREQ
+	select CPU_FREQ_TABLE
 	help
 	  This enables the CPUfreq driver for i.MX CPUs.
 
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:07 +0200
Subject: [PATCH 3/6] ARM: imx: build pm-imx5 code only when PM is enabled
In-Reply-To: <1345648390-4234-1-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
Message-ID: <1345648390-4234-4-git-send-email-arnd@arndb.de>

This moves the imx5 pm code out of the list of unconditionally
compiled files for imx5, mirroring what we already do for imx6
and how it was done before the code was move from mach-mx5 to
mach-imx in v3.3.

Without this patch, building with CONFIG_PM disabled results in:

arch/arm/mach-imx/pm-imx5.c:202:116: error: redefinition of 'imx51_pm_init'
arch/arm/mach-imx/include/mach-imx/common.h:154:91: note: previous definition of 'imx51_pm_init' was here
arch/arm/mach-imx/pm-imx5.c:209:116: error: redefinition of 'imx53_pm_init'
arch/arm/mach-imx/include/mach-imx/common.h:155:91: note: previous definition of 'imx53_pm_init' was here

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: stable at vger.kernel.org
---
 arch/arm/mach-imx/Makefile |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 07f7c22..e08adb7 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+imx5-pm-$(CONFIG_PM) += pm-imx5.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
 			    clk-pfd.o clk-busy.o
-- 
1.7.10



From arnd at arndb.de  Wed Aug 22 11:13:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:13:04 +0200
Subject: [PATCH 0/6] ARM: randconfig bugs
Message-ID: <1345648390-4234-1-git-send-email-arnd@arndb.de>

Hi everyone,

Here are some more patches for bugs I found using
'make randconfig' in v3.6-rc+multiplatform. I can
to merge them through the arm-soc tree, but please
have a look and provide Acks.

	Arnd

---
Cc: Artem Bityutskiy <dedekind1 at gmail.com>
Cc: Eric Miao <eric.miao at linaro.org>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Lee Jones <lee.jones at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Yong Shen <yong.shen at linaro.org>


Arnd Bergmann (6):
  ARM: ux500: don't select LEDS_GPIO for snowball
  ARM: omap: allow building omap44xx without SMP
  ARM: imx: build pm-imx5 code only when PM is enabled
  ARM: imx: fix ksz9021rn_phy_fixup
  ARM: imx: select CPU_FREQ_TABLE when needed
  ARM: imx: select ARM_CPU_SUSPEND when necessary

 arch/arm/Kconfig                  |    1 +
 arch/arm/mach-imx/Kconfig         |    1 +
 arch/arm/mach-imx/Makefile        |    3 ++-
 arch/arm/mach-imx/mach-imx6q.c    |    4 ++--
 arch/arm/mach-omap2/Kconfig       |    2 +-
 arch/arm/mach-omap2/cpuidle44xx.c |    3 ++-
 arch/arm/mach-ux500/Kconfig       |    1 -
 include/linux/cpuidle.h           |    4 ++++
 8 files changed, 13 insertions(+), 6 deletions(-)

-- 
1.7.10



From shawn.guo at linaro.org  Wed Aug 22 11:14:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 22 Aug 2012 23:14:58 +0800
Subject: [PATCH] ARM: dts: imx51-babbage: fix esdhc cd/wp properties
In-Reply-To: <87pq6j3tyv.fsf@octavius.laptop.org>
References: <1345643887-30606-1-git-send-email-shawn.guo@linaro.org>
 <87pq6j3tyv.fsf@octavius.laptop.org>
Message-ID: <20120822151455.GX24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 10:02:48AM -0400, Chris Ball wrote:
> Want to take this through your own tree, to avoid .dts conflicts later?
> If so:

Yes, I have another a few IMX fixing queued for 3.6-rc, and would send
this one together shortly.

> 
> Acked-by: Chris Ball <cjb at laptop.org>
> 
Thanks.

-- 
Regards,
Shawn


From arnd at arndb.de  Wed Aug 22 11:19:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 15:19:11 +0000
Subject: [PATCH 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <alpine.LFD.2.02.1208221040250.1754@xanadu.home>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-5-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208221040250.1754@xanadu.home>
Message-ID: <201208221519.12056.arnd@arndb.de>

On Wednesday 22 August 2012, Nicolas Pitre wrote:
> On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> 
> > The mls instruction is not available in ARMv6K or below, so we
> > should make the test conditional on at least ARMv7. ldrex/strex
> > are available in ARMv6K or ARMv7, which we can test by checking
> > the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.
> 
> The ldrex/strex instructions are available on ARMv6.  It's only the d 
> variants (strexd/ldrexd) which are only available from ARMv6k.

Ok. How is the version below then? I haven't tested this one yet.

	Arnd

8<---
From d878ab212cf0ac1957be83ad80dc734ace2b476c Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Thu, 16 Aug 2012 07:49:31 +0000
Subject: [PATCH] ARM: kprobes: make more tests conditional

The mls instruction is not available in ARMv6K or below, so we
should make the test conditional on at least ARMv7. ldrexd/strexd
are available in ARMv6K or ARMv7, which we can test by checking
the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.

/tmp/ccuMTZ8D.s: Assembler messages:
/tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
/tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
/tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Jon Medhurst <tixy at yxit.co.uk>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Leif Lindholm <leif.lindholm at arm.com>
---
 arch/arm/kernel/kprobes-test-arm.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 38c1a3b..fc9f6e0 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
 	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
 
+#if __LINUX_ARM_ARCH__ >= 7
 	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
 	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
 	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
+#endif
 	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
@@ -456,8 +458,10 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
 #if __LINUX_ARM_ARCH__ >= 6
 	TEST_UNSUPPORTED("ldrex	r2, [sp]")
+#ifdef CONFIG_CPU_32v6K
 	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
 	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
+#endif
 	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
 	TEST_UNSUPPORTED("ldrexb	r2, [sp]")
 	TEST_UNSUPPORTED("strexh	r0, r2, [sp]")
-- 
1.7.10



From nicolas.pitre at linaro.org  Wed Aug 22 11:23:23 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:23:23 -0400 (EDT)
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221106010.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> I've created this series some time ago, and updated it now to
> v3.6-rc1. The idea is to get us a big step closer to the
> single zImage kernel across multiple ARM platforms by
> untangling the duplicate header file names.

Thanks for picking up this task.

> There are two branches available in the arm-soc tree:
> 
> 1. This series,
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
>    This just moves header files around and changes most of the
>    files including them. There are a few remaining drivers
>    and platform files that keep including a generic file name
>    like <mach/uncompress.h>. It remains possible to do that,
>    and I've run extensive tests to ensure I did not break
>    anything with this. However, each of these instances means
>    that there is something that stops working when you get to
>    the real multiplatform kernel and we still need to deal
>    with them one by one.

The content of <mach/uncompress.h> is fundamentally machine or SOC 
specific.  We already know it is generally incompatible with a multi 
platform kernel.  So the best way to deal with this at the moment is 
probably to just provide a dummy uncompress.h with empty stubs whenever 
CONFIG_ARCH_MULTIPLATFORM is selected.  The effect from this is that 
there wouldn't be any "Uncompressing the kernel... Done" output anymore, 
which should be an acceptable compromise until a better solution is 
found.

One problem is that some (very few) machines define a method in that 
file to keep a hardware watchdog alive.  This might not be the case for 
all the intended targets to gather in a single kernel binary image 
though.

Another issue is the fact that some platforms do very ugly 
layer-violating hacks where the decompressor selects a serial port for 
early output and then store that selection in some arbitrary memory 
location for the main kernel to blindly use, making the decompressor 
mandatory.  OMAP and Davinci are prime example of such "abuse" which 
would need to be fixed.


Nicolas


From nicolas.pitre at linaro.org  Wed Aug 22 11:24:34 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:24:34 -0400 (EDT)
Subject: [PATCH 1/4] [RFC] ARM: autogenerate mach-foo/* and plat-foo/*
 header redirects
In-Reply-To: <201208221254.22292.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221254.22292.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221124100.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> This is an attempt to simplify the duplicate header problem for
> multiplatform kernels, in multiple steps:
> 
> 1. (this patch)
>    for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
>    generate a arch/arm/include/generated/mach/*.h file at build time,
>    same for plat-*.
> 
> 2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
>    arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
>    arch/arm/plat-${PLAT}/include/plat/*.h to
>    arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h
> 
> 3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
>    in all files where ${MACHINE} is known.
> 
> 4. ...
> 
> 5. Revert this patch again.
> 
> We can apply this patch at any time, and do step 2 at the end
> of the next merge window to minimize the potential for conflicts.
> We will also still need to deal with any inclusion of a mach/*
> file, but out of the 6355 ones we have today, I expect only a
> few hundred to remain after step 3 and they will be much easier
> to spot.
> 
> I've picked the format <mach-foo/bar.h> to get a unique name because
> it matches the directory name under arch/arm, but other names
> would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
> have been suggested previously.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/Makefile          |    1 +
>  arch/arm/tools/Makefile    |    5 ++++
>  arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 63 insertions(+)
>  create mode 100755 arch/arm/tools/gen-headers
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 30eae87..761b077 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -274,6 +274,7 @@ boot := arch/arm/boot
>  
>  archprepare:
>         $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
> +       $(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
>  
>  # Convert bzImage to zImage
>  bzImage: zImage
> diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
> index 635cb18..6e18ca9 100644
> --- a/arch/arm/tools/Makefile
> +++ b/arch/arm/tools/Makefile
> @@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
>         @echo '  Generating $@'
>         @mkdir -p $(dir $@)
>         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
> +
> +gen_headers:
> +       $(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
> +
> +.PHONY: gen_headers
> diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
> new file mode 100755
> index 0000000..caa6a9a
> --- /dev/null
> +++ b/arch/arm/tools/gen-headers
> @@ -0,0 +1,57 @@
> +#!/bin/bash
> +
> +SRC=$1
> +OBJ=$2
> +MACH=$3
> +PLAT1=$4
> +PLAT2=$5
> +
> +# create $3 to include $2 if it doesn't already have the correct
> +# contents, or remove it if it's no longer needed.
> +mkfile()
> +{
> +       if [ -e $1/$2 ] ; then
> +               if [ ! -e $3 ] ; then
> +                       mkdir -p ${3%/*}
> +                       echo "#include <${2}>" > $3
> +               elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
> +                       echo "#include <${2}>" > $3
> +               fi
> +       elif [ ! -e $1/$2 -a -e $3 ] ; then
> +               rm -f $3
> +       fi
> +}
> +
> +# list any header files that are present in the source or
> +# destination directories
> +find_files()
> +{
> +       pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
> +       find . -type f -name \*.h -o -name \*.S &&
> +       popd > /dev/null 2>&1
> +       pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
> +       find . -type f -name \*.h -o -name \*.S &&
> +       popd > /dev/null 2>&1
> +}
> +
> +# process files in either mach-{MACH} or plat-${PLAT}
> +mkfiles()
> +{
> +       mkdir -p ${OBJ}/arch/arm/include/generated/$1
> +
> +       FILES=`find_files $1 $2 | sort -u`
> +       for i in ${FILES} ; do
> +               mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
> +                       "${OBJ}/arch/arm/include/generated/$1/$i"
> +       done
> +}
> +
> +# always process mach-*
> +mkfiles mach ${MACH}
> +# process plat-* if applicable
> +if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
> +       mkfiles plat ${PLAT1}
> +fi
> +if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
> +       mkfiles plat ${PLAT2}
> +fi
> -- 
> 1.7.10
> 
> 
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
> 


From nicolas.pitre at linaro.org  Wed Aug 22 11:28:53 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:28:53 -0400 (EDT)
Subject: [PATCH 2/4] [RFC] ARM: mass move of mach-*/plat-* header files
In-Reply-To: <201208221256.35657.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221256.35657.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221126180.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> This moves all <mach/*.h> headers to <mach-*/*.h>, and all
> <plat/*.h> headers to <plat-*/*.h>, as another step closer
> to building kernels for multiple platforms combined.
> 
> A script to generate headers with the traditional names including
> the headers from the new place is already there, so this move
> should be completely transparent.
> 
> This patch was created fully automated by a script and
> should be redone if the headers change. Note that the
> plat-mxc headers move to mach-imx in the process because
> they don't follow the <plat/foo.h> naming convention:
> 
> for i in arch/arm/mach-* ; do git mv $i/include/mach $i/include/${i##*/} ; done
> for i in arch/arm/plat-* ; do git mv $i/include/plat $i/include/${i##*/} ; done
> git mv arch/arm/plat-mxc/include/mach/*.h arch/arm/mach-imx/include/mach-imx/
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Nicolas Pitre <nico at linaro.org>

Ideally, files such as ...

> rename from arch/arm/mach-at91/include/mach/at91_pio.h
> rename to arch/arm/mach-at91/include/mach-at91/at91_pio.h

should move next to the A91 GPIO driver file.  but that require manual 
operations which can be done later.


Nicolas


From nicolas.pitre at linaro.org  Wed Aug 22 11:31:28 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:31:28 -0400 (EDT)
Subject: [PATCH 3/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221300.10798.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221300.10798.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221129510.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> While converting all machine specific headers from
> automatically detect the right machine and platform
> name in most cases. This script uses a number of
> information sources for this:
> 
> * any arch/arm/mach-*/ directory uses its own headers,
>   with a few exceptions, same for plat-*/
> * each mach-*/ directory belongs to at most one plat-*
>   directory holding header files
> * for any header below mach/* that exists in only one
>   machine, we know that the users belong to that machine
> * some driver directories or files are manually listed
>   here.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Nicolas Pitre <nico at linaro.org>

I think that would be a good idea if you do keep your scripts in the 
commit log like it is done here.

> ===========================================================
> 
> fixup()
> {
>  echo fixup "$1 $2 $3"
>  git ls-files $1 | xargs sed -i "s:^\(#.*include <\)$2/:\1$3/:g"
> }
> 
> fixup arch/arm/mach-s3c2410 mach mach-s3c24xx
> fixup arch/arm/mach-s3c2412 mach mach-s3c24xx
> fixup arch/arm/mach-s3c2440 mach mach-s3c24xx
> 
> fixup arch/arm/plat-mxc mach mach-imx
> fixup arch/arm/plat-s3c24xx mach mach-s3c24xx
> fixup arch/arm/plat-s3c24xx plat plat-samsung
> 
> for i in arch/arm/mach-*; do
>         fixup "$i" mach "${i##*/}"
> done
> 
> for i in arch/arm/plat-* ; do
>         fixup "$i" plat "${i##*/}"
> done
> 
> fixup arch/arm/mach-spear3xx plat plat-spear
> fixup arch/arm/mach-spear6xx plat plat-spear
> fixup arch/arm/mach-spear13xx plat plat-spear
> fixup arch/arm/mach-pxa plat plat-pxa
> fixup arch/arm/mach-mmp plat plat-pxa
> fixup arch/arm/mach-orion5x plat plat-orion
> fixup arch/arm/mach-kirkwood plat plat-orion
> fixup arch/arm/mach-mv78xx0 plat plat-orion
> fixup arch/arm/mach-dove plat plat-orion
> fixup arch/arm/mach-nomadik plat plat-nomadik
> fixup arch/arm/mach-ux500 plat plat-nomadik
> fixup arch/arm/mach-s3c2410 plat plat-samsung
> fixup arch/arm/mach-s3c2412 plat plat-samsung
> fixup arch/arm/mach-s3c2440 plat plat-samsung
> fixup arch/arm/mach-s3c24xx plat plat-samsung
> fixup arch/arm/mach-s3c64xx plat plat-samsung
> fixup arch/arm/mach-s5p64x0 plat plat-samsung
> fixup arch/arm/mach-s5pc100 plat plat-samsung
> fixup arch/arm/mach-s5pv210 plat plat-samsung
> fixup arch/arm/mach-exynos plat plat-samsung
> fixup arch/arm/mach-omap1 plat plat-omap
> fixup arch/arm/mach-omap2 plat plat-omap
> fixup arch/arm/mach-versatile plat plat-versatile
> fixup arch/arm/mach-integrator plat plat-versatile
> fixup arch/arm/mach-realview plat plat-versatile
> fixup arch/arm/mach-vexpress plat plat-versatile
> fixup arch/arm/mach-zynq plat plat-versatile
> 
> fixup drivers/video/omap plat plat-omap
> fixup drivers/video/omap2 plat plat-omap
> fixup drivers/video/exynos plat plat-samsung
> fixup drivers/char/hw_random/omap\* plat plat-omap
> fixup drivers/cpufreq/omap\* plat plat-omap
> fixup drivers/crypto/omap\* plat plat-omap
> fixup drivers/media/video/omap\* plat plat-omap
> fixup drivers/input/keyboard/omap\* plat plat-omap
> fixup drivers/mmc/host/omap\* plat plat-omap
> fixup drivers/mtd/*nand/omap\* plat plat-omap
> fixup drivers/spi/spi-omap\* plat plat-omap
> fixup drivers/tty/serial/omap\* plat plat-omap
> fixup drivers/usb/gadget/omap\* plat plat-omap
> fixup drivers/usb/musb/*omap\* plat plat-omap
> fixup drivers/dma/omap-dma.c plat plat-omap
> fixup drivers/staging/omapdrm plat plat-omap
> fixup drivers/staging/tidspbridge/ plat plat-omap
> fixup drivers/input/keyboard/spear-keyboard.c plat plat-spear
> fixup drivers/cpufreq/exynos-cpufreq.c plat plat-samsung
> fixup drivers/crypto/s5p-sss.c plat plat-samsung
> fixup drivers/i2c/busses/i2c-nomadik.c plat plat-nomadik
> fixup drivers/mtd/nand/s3c2410.c plat plat-samsung
> fixup drivers/tty/serial/samsung.c plat plat-samsung
> fixup drivers/usb/gadget/s3c-hsotg.c plat plat-samsung
> fixup drivers/gpio/gpio-samsung.c plat plat-samsung
> fixup sound/soc/samsung plat plat-samsung
> fixup sound/soc/omap plat plat-omap
> fixup sound/soc/pxa plat plat-pxa
> fixup sound/soc/kirkwood/ plat plat-orion
> fixup sound/soc/fsl/imx*.[ch] plat plat-mxc
> 
> fixup drivers/video/omap mach mach-omap1
> fixup drivers/video/omap2 mach mach-omap2
> fixup drivers/video/exynos mach mach-exynos
> fixup drivers/media/video/davinci mach mach-davinci
> 
> fixup sound/soc/omap/osk5912.c mach mach-omap1
> fixup sound/soc/omap mach mach-omap2
> fixup sound/soc/pxa mach mach-pxa
> fixup sound/soc/davinci mach mach-davinci
> fixup sound/soc/ep93xx mach mach-ep93xx
> fixup sound/soc/kirkwood/ mach mach-kirkwood
> fixup sound/soc/fsl/imx*.[ch] mach mach-imx
> fixup sound/soc/mxs mach mach-mxs
> fixup sound/soc/tegra mach mach-tegra
> fixup sound/soc/nuc900 mach mach-w90x900
> fixup sound/arm/pxa\* mach mach-pxa
> fixup sound/atmel/ac97c.c mach mach-at91
> fixup sound/oss/waveartist.c mach mach-footbridge
> fixup sound/oss/vidc\* mach mach-rpc
> fixup sound/soc/atmel/ mach mach-at91
> fixup sound/soc/ux500/ mach mach-ux500
> 
> fixup include/linux/spi/pxa2xx_spi.h mach mach-pxa
> fixup include/linux/mfd/dbx500-prcmu.h mach mach-ux500
> 
> find_unique_mach()
> {
>   {
>     # find files in other architectures using mach/*.h
>     git ls-files | grep /mach/[^/]*.h | while read i ;
>         do echo ${i##*/}
>     done
>     # find files we've already renamed in ARM
>     for i in arch/arm/mach-*/include/mach-*/ ; do
>         git ls-files "$i" | sed -e "s:^$i::g"
>     done
>   } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
> }
> rename_unique_mach()
> {
>   ALLFILES=`git grep -l "^#include.*<mach/"`
>   ALLINCLUDES=`git grep "^#include.*<mach/" ${ALLFILES}`
>   find_unique_mach | while read i ; do
>     echo "$ALLINCLUDES" | if grep -q "#include.*<mach/$i>" &&
>                 [ -e arch/arm/mach-*/include/mach-*/"$i" ] ; then
>        MACH=`ls arch/arm/mach-*/include/mach-*/$i | cut -f 3 -d /`
>        THESEFILES=`git grep -l "^#include.*<mach/$i>" ${ALLFILES}`
>        echo mach/$i
>        for j in ${THESEFILES} ; do
>           fixup $j mach ${MACH}
>        done
>     fi
>   done
> }
> 
> find_unique_plat()
> {
>   {
>     # all plat/*.h files are already renamed
>     for i in arch/arm/plat-*/include/plat-*/ ; do
>         git ls-files "$i" | sed -e "s:^$i::g"
>     done
>   } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
> }
> rename_unique_plat()
> {
>   ALLFILES=`git grep -l "#include.*<plat/"`
>   if [ "" != "${ALLFILES}" ] ; then
>     find_unique_plat | while read i ; do
>       PLAT=`ls arch/arm/plat-*/include/plat-*/$i | cut -f 3 -d /`
>       THESEFILES=`git grep -l "^#include.*<plat/$i>" ${ALLFILES}`
>       echo plat/$i
>        for j in ${THESEFILES} ; do
>           fixup $j plat ${PLAT}
>        done
>     done
>   fi
> }
> 
> rename_unique_mach
> rename_unique_plat
> ---
>    0.0% Documentation/spi/
>    0.0% arch/arm/boot/compressed/
>    0.3% arch/arm/mach-at91/include/mach-at91/
>    4.7% arch/arm/mach-at91/
>    0.1% arch/arm/mach-bcmring/csp/chipc/
>    0.1% arch/arm/mach-bcmring/csp/dmac/
>    0.0% arch/arm/mach-bcmring/csp/tmr/
>    0.0% arch/arm/mach-bcmring/include/csp/
>    0.3% arch/arm/mach-bcmring/include/mach-bcmring/csp/
>    0.1% arch/arm/mach-bcmring/include/mach-bcmring/
>    0.4% arch/arm/mach-bcmring/
>    0.0% arch/arm/mach-clps711x/include/mach-clps711x/
>    0.1% arch/arm/mach-clps711x/
>    0.0% arch/arm/mach-cns3xxx/include/mach-cns3xxx/
>    0.1% arch/arm/mach-cns3xxx/
>    0.3% arch/arm/mach-davinci/include/mach-davinci/
>    3.3% arch/arm/mach-davinci/
>    0.0% arch/arm/mach-dove/include/mach-dove/
>    0.3% arch/arm/mach-dove/
>    0.0% arch/arm/mach-ebsa110/
>    0.0% arch/arm/mach-ep93xx/include/mach-ep93xx/
>    0.5% arch/arm/mach-ep93xx/
>    0.2% arch/arm/mach-exynos/include/mach-exynos/
>    3.9% arch/arm/mach-exynos/
>    0.0% arch/arm/mach-footbridge/include/mach-footbridge/
>    0.0% arch/arm/mach-footbridge/
>    0.1% arch/arm/mach-gemini/include/mach-gemini/
>    0.1% arch/arm/mach-gemini/
>    0.0% arch/arm/mach-h720x/include/mach-h720x/
>    0.1% arch/arm/mach-h720x/
>    0.6% arch/arm/mach-imx/include/mach-imx/
>    5.0% arch/arm/mach-imx/
>    0.5% arch/arm/mach-integrator/
>    0.0% arch/arm/mach-iop13xx/include/mach-iop13xx/
>    0.2% arch/arm/mach-iop13xx/
>    0.0% arch/arm/mach-iop32x/include/mach-iop32x/
>    0.1% arch/arm/mach-iop32x/
>    0.0% arch/arm/mach-iop33x/include/mach-iop33x/
>    0.1% arch/arm/mach-iop33x/
>    0.1% arch/arm/mach-ixp4xx/include/mach-ixp4xx/
>    0.3% arch/arm/mach-ixp4xx/
>    0.0% arch/arm/mach-kirkwood/include/mach-kirkwood/
>    1.1% arch/arm/mach-kirkwood/
>    0.1% arch/arm/mach-ks8695/include/mach-ks8695/
>    0.4% arch/arm/mach-ks8695/
>    0.0% arch/arm/mach-lpc32xx/include/mach-lpc32xx/
>    0.3% arch/arm/mach-lpc32xx/
>    0.4% arch/arm/mach-mmp/include/mach-mmp/
>    1.5% arch/arm/mach-mmp/
>    0.1% arch/arm/mach-msm/include/mach-msm/
>    1.2% arch/arm/mach-msm/
>    0.0% arch/arm/mach-mv78xx0/include/mach-mv78xx0/
>    0.3% arch/arm/mach-mv78xx0/
>    0.0% arch/arm/mach-mvebu/include/mach-mvebu/
>    0.0% arch/arm/mach-mvebu/
>    0.5% arch/arm/mach-mxs/devices/
>    0.1% arch/arm/mach-mxs/include/mach-mxs/
>    0.5% arch/arm/mach-mxs/
>    0.3% arch/arm/mach-netx/
>    0.0% arch/arm/mach-nomadik/include/mach-nomadik/
>    0.1% arch/arm/mach-nomadik/
>    0.2% arch/arm/mach-omap1/include/mach-omap1/
>    3.3% arch/arm/mach-omap1/
>    0.1% arch/arm/mach-omap2/include/mach-omap2/
>    8.1% arch/arm/mach-omap2/
>    0.1% arch/arm/mach-orion5x/include/mach-orion5x/
>    0.7% arch/arm/mach-orion5x/
>    0.0% arch/arm/mach-picoxcell/include/mach-picoxcell/
>    0.0% arch/arm/mach-picoxcell/
>    0.0% arch/arm/mach-pnx4008/include/mach-pnx4008/
>    0.4% arch/arm/mach-pnx4008/
>    0.1% arch/arm/mach-prima2/include/mach-prima2/
>    0.0% arch/arm/mach-prima2/
>    0.7% arch/arm/mach-pxa/include/mach-pxa/
>    7.6% arch/arm/mach-pxa/
>    0.3% arch/arm/mach-realview/include/mach-realview/
>    0.4% arch/arm/mach-realview/
>    0.0% arch/arm/mach-rpc/include/mach-rpc/
>    0.1% arch/arm/mach-rpc/
>    0.1% arch/arm/mach-s3c2410/
>    0.1% arch/arm/mach-s3c2412/
>    0.2% arch/arm/mach-s3c2440/
>    0.3% arch/arm/mach-s3c24xx/include/mach-s3c24xx/
>   10.9% arch/arm/mach-s3c24xx/
>    0.1% arch/arm/mach-s3c64xx/include/mach-s3c64xx/
>    3.9% arch/arm/mach-s3c64xx/
>    0.2% arch/arm/mach-s5p64x0/include/mach-s5p64x0/
>    2.1% arch/arm/mach-s5p64x0/
>    0.2% arch/arm/mach-s5pc100/include/mach-s5pc100/
>    1.0% arch/arm/mach-s5pc100/
>    0.2% arch/arm/mach-s5pv210/include/mach-s5pv210/
>    2.1% arch/arm/mach-s5pv210/
>    0.1% arch/arm/mach-sa1100/include/mach-sa1100/
>    1.1% arch/arm/mach-sa1100/
>    0.0% arch/arm/mach-shmobile/include/mach-shmobile/
>    1.9% arch/arm/mach-shmobile/
>    0.0% arch/arm/mach-spear13xx/include/mach-spear13xx/
>    0.1% arch/arm/mach-spear13xx/
>    0.0% arch/arm/mach-spear3xx/include/mach-spear3xx/
>    0.2% arch/arm/mach-spear3xx/
>    0.0% arch/arm/mach-spear6xx/include/mach-spear6xx/
>    0.0% arch/arm/mach-spear6xx/
>    0.0% arch/arm/mach-tegra/include/mach-tegra/
>    1.0% arch/arm/mach-tegra/
>    0.0% arch/arm/mach-u300/include/mach-u300/
>    0.2% arch/arm/mach-u300/
>    0.1% arch/arm/mach-ux500/include/mach-ux500/
>    0.9% arch/arm/mach-ux500/
>    0.0% arch/arm/mach-versatile/include/mach-versatile/
>    0.1% arch/arm/mach-versatile/
>    0.1% arch/arm/mach-vexpress/
>    0.1% arch/arm/mach-vt8500/
>    0.1% arch/arm/mach-w90x900/include/mach-w90x900/
>    0.4% arch/arm/mach-w90x900/
>    0.0% arch/arm/mach-zynq/include/mach-zynq/
>    0.0% arch/arm/mach-zynq/
>    0.0% arch/arm/mm/
>    1.0% arch/arm/plat-mxc/devices/
>    0.4% arch/arm/plat-mxc/
>    0.4% arch/arm/plat-omap/include/plat-omap/
>    0.6% arch/arm/plat-omap/
>    0.1% arch/arm/plat-orion/
>    0.0% arch/arm/plat-pxa/
>    0.6% arch/arm/plat-s3c24xx/
>    0.2% arch/arm/plat-samsung/include/plat-samsung/
>    1.4% arch/arm/plat-samsung/
>    0.0% arch/arm/plat-spear/
>    0.0% arch/arm/plat-versatile/
>    0.1% drivers/ata/
>    0.0% drivers/char/hw_random/
>    0.0% drivers/char/
>    0.0% drivers/clk/mxs/
>    0.0% drivers/clk/
>    0.0% drivers/clocksource/
>    0.0% drivers/cpufreq/
>    0.0% drivers/crypto/ux500/cryp/
>    0.0% drivers/crypto/ux500/hash/
>    0.1% drivers/crypto/
>    0.0% drivers/devfreq/
>    0.0% drivers/dma/ipu/
>    0.2% drivers/dma/
>    0.4% drivers/gpio/
>    0.0% drivers/gpu/drm/exynos/
>    0.0% drivers/hwmon/
>    0.0% drivers/i2c/busses/
>    0.0% drivers/iio/adc/
>    0.3% drivers/input/keyboard/
>    0.0% drivers/input/mouse/
>    0.0% drivers/input/serio/
>    0.1% drivers/input/touchscreen/
>    0.2% drivers/iommu/
>    0.0% drivers/leds/
>    0.1% drivers/media/video/davinci/
>    0.0% drivers/media/video/omap/
>    0.1% drivers/media/video/omap3isp/
>    0.0% drivers/media/video/s5p-fimc/
>    0.0% drivers/media/video/s5p-tv/
>    0.1% drivers/media/video/
>    0.1% drivers/mfd/
>    0.3% drivers/mmc/host/
>    0.0% drivers/mtd/maps/
>    0.4% drivers/mtd/nand/
>    0.0% drivers/mtd/onenand/
>    0.0% drivers/net/ethernet/cadence/
>    0.0% drivers/net/ethernet/micrel/
>    0.0% drivers/net/ethernet/smsc/
>    0.0% drivers/net/ethernet/xscale/
>    0.0% drivers/net/ethernet/
>    0.0% drivers/net/wan/
>    0.6% drivers/pcmcia/
>    0.0% drivers/pinctrl/
>    0.0% drivers/power/
>    0.0% drivers/ptp/
>    0.0% drivers/pwm/
>    0.0% drivers/remoteproc/
>    0.0% drivers/rtc/
>    0.2% drivers/spi/
>    0.0% drivers/staging/nvec/
>    0.0% drivers/staging/omapdrm/
>    0.0% drivers/staging/tidspbridge/core/
>    0.0% drivers/staging/tidspbridge/include/dspbridge/
>    0.0% drivers/staging/tidspbridge/rmgr/
>    0.1% drivers/tty/serial/
>    0.2% drivers/usb/gadget/
>    0.4% drivers/usb/host/
>    0.1% drivers/usb/musb/
>    0.0% drivers/usb/otg/
>    0.1% drivers/video/backlight/
>    0.0% drivers/video/exynos/
>    0.2% drivers/video/msm/
>    0.1% drivers/video/omap/
>    0.1% drivers/video/omap2/dss/
>    0.0% drivers/video/omap2/omapfb/
>    0.0% drivers/video/omap2/
>    0.4% drivers/video/
>    0.0% drivers/watchdog/
>    0.0% include/linux/mfd/
>    0.0% include/linux/platform_data/
>    0.0% include/linux/power/
>    0.0% include/linux/spi/
>    0.0% include/linux/
>    0.1% sound/arm/
>    0.0% sound/atmel/
>    0.0% sound/oss/
>    0.0% sound/soc/atmel/
>    0.1% sound/soc/davinci/
>    0.1% sound/soc/ep93xx/
>    0.0% sound/soc/fsl/
>    0.0% sound/soc/kirkwood/
>    0.0% sound/soc/mxs/
>    0.0% sound/soc/nuc900/
>    0.6% sound/soc/omap/
>    0.5% sound/soc/pxa/
>    0.2% sound/soc/samsung/
>    0.0% sound/soc/tegra/
>    0.1% sound/soc/ux500/
> 
> diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
> index d8eb01c..f088b4b 100644
> --- a/Documentation/spi/ep93xx_spi
> +++ b/Documentation/spi/ep93xx_spi
> @@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
>  #include <linux/gpio.h>
>  #include <linux/spi/spi.h>
>  
> -#include <mach/ep93xx_spi.h>
> +#include <mach-ep93xx/ep93xx_spi.h>
>  
>  /* this is our GPIO line used for chip select */
>  #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
> diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
> index fe3719b..4bcb9c7 100644
> --- a/arch/arm/boot/compressed/head-shmobile.S
> +++ b/arch/arm/boot/compressed/head-shmobile.S
> @@ -23,7 +23,7 @@
>         .section        ".start", "ax"
>  
>         /* load board-specific initialization code */
> -#include <mach/zboot.h>
> +#include <mach-shmobile/zboot.h>
>  
>  #if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
>         /* Load image from MMC/SD */
> diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
> index bd3d469..ff0aa20 100644
> --- a/arch/arm/boot/compressed/sdhi-shmobile.c
> +++ b/arch/arm/boot/compressed/sdhi-shmobile.c
> @@ -18,7 +18,7 @@
>  #include <linux/mmc/mmc.h>
>  #include <linux/mmc/sd.h>
>  #include <linux/mmc/tmio.h>
> -#include <mach/sdhi.h>
> +#include <mach-shmobile/sdhi.h>
>  
>  #define OCR_FASTBOOT           (1<<29)
>  #define OCR_HCS                        (1<<30)
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index 6f50c67..fd81ffe 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -16,11 +16,11 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/at91rm9200.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_st.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/at91rm9200.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_st.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
> index 01fb732..2b63b60 100644
> --- a/arch/arm/mach-at91/at91rm9200_devices.c
> +++ b/arch/arm/mach-at91/at91rm9200_devices.c
> @@ -18,10 +18,10 @@
>  #include <linux/platform_device.h>
>  #include <linux/i2c-gpio.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91rm9200.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91rm9200.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index 104ca40..aec1da4 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -27,7 +27,7 @@
>  
>  #include <asm/mach/time.h>
>  
> -#include <mach/at91_st.h>
> +#include <mach-at91/at91_st.h>
>  
>  static unsigned long last_crtr;
>  static u32 irqmask;
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index 30c7f26..e84bddb 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -17,12 +17,12 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_dbgu.h>
> -#include <mach/at91sam9260.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_dbgu.h>
> +#include <mach-at91/at91sam9260.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
> index 7b9c2ba..cb364af 100644
> --- a/arch/arm/mach-at91/at91sam9260_devices.c
> +++ b/arch/arm/mach-at91/at91sam9260_devices.c
> @@ -19,13 +19,13 @@
>  
>  #include <linux/platform_data/at91_adc.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> -#include <mach/at91sam9260.h>
> -#include <mach/at91sam9260_matrix.h>
> -#include <mach/at91_matrix.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_adc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91sam9260.h>
> +#include <mach-at91/at91sam9260_matrix.h>
> +#include <mach-at91/at91_matrix.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_adc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index f40762c..58c830b 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -17,11 +17,11 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/cpu.h>
> -#include <mach/at91sam9261.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91sam9261.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
> index 8df5c1b..f2e6805 100644
> --- a/arch/arm/mach-at91/at91sam9261_devices.c
> +++ b/arch/arm/mach-at91/at91sam9261_devices.c
> @@ -21,11 +21,11 @@
>  #include <linux/fb.h>
>  #include <video/atmel_lcdc.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91sam9261.h>
> -#include <mach/at91sam9261_matrix.h>
> -#include <mach/at91_matrix.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91sam9261.h>
> +#include <mach-at91/at91sam9261_matrix.h>
> +#include <mach-at91/at91_matrix.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 84b3810..51f4f7e 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -17,10 +17,10 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/at91sam9263.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/at91sam9263.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
> index eb6bbf8..26dc600 100644
> --- a/arch/arm/mach-at91/at91sam9263_devices.c
> +++ b/arch/arm/mach-at91/at91sam9263_devices.c
> @@ -20,11 +20,11 @@
>  #include <linux/fb.h>
>  #include <video/atmel_lcdc.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91sam9263.h>
> -#include <mach/at91sam9263_matrix.h>
> -#include <mach/at91_matrix.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91sam9263.h>
> +#include <mach-at91/at91sam9263_matrix.h>
> +#include <mach-at91/at91_matrix.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
> index ffc0957..e3b0d36 100644
> --- a/arch/arm/mach-at91/at91sam926x_time.c
> +++ b/arch/arm/mach-at91/at91sam926x_time.c
> @@ -20,7 +20,7 @@
>  
>  #include <asm/mach/time.h>
>  
> -#include <mach/at91_pit.h>
> +#include <mach-at91/at91_pit.h>
>  
>  
>  #define PIT_CPIV(x)    ((x) & AT91_PIT_CPIV)
> diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
> index 7af2e10..6d8da98 100644
> --- a/arch/arm/mach-at91/at91sam9_alt_reset.S
> +++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
> @@ -14,9 +14,9 @@
>   */
>  
>  #include <linux/linkage.h>
> -#include <mach/hardware.h>
> -#include <mach/at91_ramc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>                         .arm
>  
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index ef6cedd..45c79b4 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -17,10 +17,10 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/at91sam9g45.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/at91sam9g45.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index 0607399..242c850 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -25,14 +25,14 @@
>  #include <linux/fb.h>
>  #include <video/atmel_lcdc.h>
>  
> -#include <mach/at91_adc.h>
> -#include <mach/board.h>
> -#include <mach/at91sam9g45.h>
> -#include <mach/at91sam9g45_matrix.h>
> -#include <mach/at91_matrix.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at_hdmac.h>
> -#include <mach/atmel-mci.h>
> +#include <mach-at91/at91_adc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91sam9g45.h>
> +#include <mach-at91/at91sam9g45_matrix.h>
> +#include <mach-at91/at91_matrix.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at_hdmac.h>
> +#include <mach-at91/atmel-mci.h>
>  
>  #include <media/atmel-isi.h>
>  
> diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
> index 9d45718..0726dad 100644
> --- a/arch/arm/mach-at91/at91sam9g45_reset.S
> +++ b/arch/arm/mach-at91/at91sam9g45_reset.S
> @@ -11,9 +11,9 @@
>   */
>  
>  #include <linux/linkage.h>
> -#include <mach/hardware.h>
> -#include <mach/at91_ramc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>                         .arm
>  
> diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
> index 0849466..b5f4e1d 100644
> --- a/arch/arm/mach-at91/at91sam9n12.c
> +++ b/arch/arm/mach-at91/at91sam9n12.c
> @@ -12,10 +12,10 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> -#include <mach/at91sam9n12.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/cpu.h>
> -#include <mach/board.h>
> +#include <mach-at91/at91sam9n12.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/board.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
> index 72ce50a..3c17719 100644
> --- a/arch/arm/mach-at91/at91sam9rl.c
> +++ b/arch/arm/mach-at91/at91sam9rl.c
> @@ -16,12 +16,12 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/system_misc.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_dbgu.h>
> -#include <mach/at91sam9rl.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_rstc.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_dbgu.h>
> +#include <mach-at91/at91sam9rl.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_rstc.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
> index f09fff9..cf41235 100644
> --- a/arch/arm/mach-at91/at91sam9rl_devices.c
> +++ b/arch/arm/mach-at91/at91sam9rl_devices.c
> @@ -17,12 +17,12 @@
>  #include <linux/fb.h>
>  #include <video/atmel_lcdc.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91sam9rl.h>
> -#include <mach/at91sam9rl_matrix.h>
> -#include <mach/at91_matrix.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at_hdmac.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91sam9rl.h>
> +#include <mach-at91/at91sam9rl_matrix.h>
> +#include <mach-at91/at91_matrix.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at_hdmac.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 477cf9d..d919d0e 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -12,10 +12,10 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> -#include <mach/at91sam9x5.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/cpu.h>
> -#include <mach/board.h>
> +#include <mach-at91/at91sam9x5.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/board.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
> index 46090e6..e3224b1 100644
> --- a/arch/arm/mach-at91/at91x40.c
> +++ b/arch/arm/mach-at91/at91x40.c
> @@ -17,10 +17,10 @@
>  #include <asm/proc-fns.h>
>  #include <asm/system_misc.h>
>  #include <asm/mach/arch.h>
> -#include <mach/at91x40.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91_st.h>
> -#include <mach/timex.h>
> +#include <mach-at91/at91x40.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_st.h>
> +#include <mach-at91/timex.h>
>  #include "generic.h"
>  
>  /*
> diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
> index 6ca680a..478fa8a 100644
> --- a/arch/arm/mach-at91/at91x40_time.c
> +++ b/arch/arm/mach-at91/at91x40_time.c
> @@ -24,9 +24,9 @@
>  #include <linux/irq.h>
>  #include <linux/time.h>
>  #include <linux/io.h>
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/mach/time.h>
> -#include <mach/at91_tc.h>
> +#include <mach-at91/at91_tc.h>
>  
>  #define at91_tc_read(field) \
>         __raw_readl(AT91_TC + field)
> diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
> index 22d8856..bbfe99a 100644
> --- a/arch/arm/mach-at91/board-1arm.c
> +++ b/arch/arm/mach-at91/board-1arm.c
> @@ -25,7 +25,7 @@
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -34,9 +34,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
> index de7be19..ae1469e 100644
> --- a/arch/arm/mach-at91/board-afeb-9260v1.c
> +++ b/arch/arm/mach-at91/board-afeb-9260v1.c
> @@ -34,7 +34,7 @@
>  #include <linux/clk.h>
>  #include <linux/dma-mapping.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -43,8 +43,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
> index 477e708..8e3b25a 100644
> --- a/arch/arm/mach-at91/board-cam60.c
> +++ b/arch/arm/mach-at91/board-cam60.c
> @@ -29,7 +29,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/spi/flash.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -38,9 +38,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
> index a5b002f..b2f21fc 100644
> --- a/arch/arm/mach-at91/board-carmeva.c
> +++ b/arch/arm/mach-at91/board-carmeva.c
> @@ -34,9 +34,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
> index ecbc13b..2d5334c 100644
> --- a/arch/arm/mach-at91/board-cpu9krea.c
> +++ b/arch/arm/mach-at91/board-cpu9krea.c
> @@ -39,12 +39,12 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91sam9260_matrix.h>
> -#include <mach/at91_matrix.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91sam9260_matrix.h>
> +#include <mach-at91/at91_matrix.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
> index 2e6d043..73934ef 100644
> --- a/arch/arm/mach-at91/board-cpuat91.c
> +++ b/arch/arm/mach-at91/board-cpuat91.c
> @@ -27,7 +27,7 @@
>  #include <linux/mtd/physmap.h>
>  #include <linux/mtd/plat-ram.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -36,11 +36,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
> index 462bc31..40f5e99 100644
> --- a/arch/arm/mach-at91/board-csb337.c
> +++ b/arch/arm/mach-at91/board-csb337.c
> @@ -37,9 +37,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
> index 872871a..df54c811 100644
> --- a/arch/arm/mach-at91/board-csb637.c
> +++ b/arch/arm/mach-at91/board-csb637.c
> @@ -34,9 +34,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
> index e8f45c4..346b427 100644
> --- a/arch/arm/mach-at91/board-dt.c
> +++ b/arch/arm/mach-at91/board-dt.c
> @@ -15,8 +15,8 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include <asm/setup.h>
>  #include <asm/irq.h>
> diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
> index 01f66e9..5a0365d 100644
> --- a/arch/arm/mach-at91/board-eb01.c
> +++ b/arch/arm/mach-at91/board-eb01.c
> @@ -24,11 +24,11 @@
>  #include <linux/platform_device.h>
>  #include <linux/irq.h>
>  #include <asm/mach-types.h>
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  #include "generic.h"
>  
>  static void __init at91eb01_init_irq(void)
> diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
> index d1e1f3f..3ae9f49 100644
> --- a/arch/arm/mach-at91/board-eb9200.c
> +++ b/arch/arm/mach-at91/board-eb9200.c
> @@ -26,7 +26,7 @@
>  #include <linux/module.h>
>  #include <linux/device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -35,8 +35,8 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
> index 9c24cb2..f9d2da7 100644
> --- a/arch/arm/mach-at91/board-ecbat91.c
> +++ b/arch/arm/mach-at91/board-ecbat91.c
> @@ -28,7 +28,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/spi/flash.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -37,9 +37,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
> index 82bdfde..814756e 100644
> --- a/arch/arm/mach-at91/board-eco920.c
> +++ b/arch/arm/mach-at91/board-eco920.c
> @@ -24,11 +24,11 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
> index 6cc83a8..d5315ef 100644
> --- a/arch/arm/mach-at91/board-flexibity.c
> +++ b/arch/arm/mach-at91/board-flexibity.c
> @@ -32,9 +32,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
> index 69ab124..43b5fc2 100644
> --- a/arch/arm/mach-at91/board-foxg20.c
> +++ b/arch/arm/mach-at91/board-foxg20.c
> @@ -32,7 +32,7 @@
>  #include <linux/clk.h>
>  #include <linux/w1-gpio.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -41,9 +41,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
> index a9d5e78..b6d0d6f 100644
> --- a/arch/arm/mach-at91/board-gsia18s.c
> +++ b/arch/arm/mach-at91/board-gsia18s.c
> @@ -30,11 +30,11 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/gsia18s.h>
> -#include <mach/stamp9g20.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/gsia18s.h>
> +#include <mach-at91/stamp9g20.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
> index 64c1dbf..7e98f65 100644
> --- a/arch/arm/mach-at91/board-kafa.c
> +++ b/arch/arm/mach-at91/board-kafa.c
> @@ -25,7 +25,7 @@
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -34,9 +34,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
> index 5d96cb8..5b1bf97 100644
> --- a/arch/arm/mach-at91/board-kb9202.c
> +++ b/arch/arm/mach-at91/board-kb9202.c
> @@ -26,7 +26,7 @@
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -35,11 +35,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
> index 18103c5d..c9e9d89 100644
> --- a/arch/arm/mach-at91/board-neocore926.c
> +++ b/arch/arm/mach-at91/board-neocore926.c
> @@ -43,10 +43,10 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
> index 9ca3e32..f809d33 100644
> --- a/arch/arm/mach-at91/board-pcontrol-g20.c
> +++ b/arch/arm/mach-at91/board-pcontrol-g20.c
> @@ -29,10 +29,10 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/stamp9g20.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/stamp9g20.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
> index 1270655..469000d 100644
> --- a/arch/arm/mach-at91/board-picotux200.c
> +++ b/arch/arm/mach-at91/board-picotux200.c
> @@ -28,7 +28,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/mtd/physmap.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -37,10 +37,10 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
> index bf351e2..0364e46 100644
> --- a/arch/arm/mach-at91/board-qil-a9260.c
> +++ b/arch/arm/mach-at91/board-qil-a9260.c
> @@ -39,11 +39,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
> index cc2bf97..9769e97 100644
> --- a/arch/arm/mach-at91/board-rm9200dk.c
> +++ b/arch/arm/mach-at91/board-rm9200dk.c
> @@ -38,11 +38,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
> index 62e19e6..2311b39 100644
> --- a/arch/arm/mach-at91/board-rm9200ek.c
> +++ b/arch/arm/mach-at91/board-rm9200ek.c
> @@ -38,11 +38,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
> index c3b43ae..5dfc434 100644
> --- a/arch/arm/mach-at91/board-rsi-ews.c
> +++ b/arch/arm/mach-at91/board-rsi-ews.c
> @@ -24,9 +24,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
>  
>  #include <linux/gpio.h>
>  
> diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
> index 7bf6da7..39546b8 100644
> --- a/arch/arm/mach-at91/board-sam9-l9260.c
> +++ b/arch/arm/mach-at91/board-sam9-l9260.c
> @@ -28,7 +28,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/spi/spi.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -37,9 +37,9 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
> index 889c1bf..27865bc 100644
> --- a/arch/arm/mach-at91/board-sam9260ek.c
> +++ b/arch/arm/mach-at91/board-sam9260ek.c
> @@ -40,12 +40,12 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> -#include <mach/system_rev.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
> +#include <mach-at91/system_rev.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
> index 2269be5..e37f30f 100644
> --- a/arch/arm/mach-at91/board-sam9261ek.c
> +++ b/arch/arm/mach-at91/board-sam9261ek.c
> @@ -44,12 +44,12 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> -#include <mach/system_rev.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
> +#include <mach-at91/system_rev.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
> index 82adf58..b149347 100644
> --- a/arch/arm/mach-at91/board-sam9263ek.c
> +++ b/arch/arm/mach-at91/board-sam9263ek.c
> @@ -43,12 +43,12 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> -#include <mach/system_rev.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
> +#include <mach-at91/system_rev.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
> index 4ea4ee0..cd48ea7 100644
> --- a/arch/arm/mach-at91/board-sam9g20ek.c
> +++ b/arch/arm/mach-at91/board-sam9g20ek.c
> @@ -34,7 +34,7 @@
>  
>  #include <linux/platform_data/at91_adc.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
> @@ -43,10 +43,10 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/system_rev.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/system_rev.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
> index 3d48ec1..4222519 100644
> --- a/arch/arm/mach-at91/board-sam9m10g45ek.c
> +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
> @@ -29,7 +29,7 @@
>  
>  #include <linux/platform_data/at91_adc.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <video/atmel_lcdc.h>
>  #include <media/soc_camera.h>
>  #include <media/atmel-isi.h>
> @@ -42,11 +42,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> -#include <mach/system_rev.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
> +#include <mach-at91/system_rev.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
> index e7dc3ea..80f805c 100644
> --- a/arch/arm/mach-at91/board-sam9rlek.c
> +++ b/arch/arm/mach-at91/board-sam9rlek.c
> @@ -29,11 +29,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
> index a4e031a..dada12c 100644
> --- a/arch/arm/mach-at91/board-snapper9260.c
> +++ b/arch/arm/mach-at91/board-snapper9260.c
> @@ -31,10 +31,10 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
> index 29eae16..64c7010 100644
> --- a/arch/arm/mach-at91/board-stamp9g20.c
> +++ b/arch/arm/mach-at91/board-stamp9g20.c
> @@ -25,9 +25,9 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
> index c1476b9..dacfc5b 100644
> --- a/arch/arm/mach-at91/board-usb-a926x.c
> +++ b/arch/arm/mach-at91/board-usb-a926x.c
> @@ -40,11 +40,11 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91sam9_smc.h>
> -#include <mach/at91_shdwc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91sam9_smc.h>
> +#include <mach-at91/at91_shdwc.h>
>  
>  #include "sam9_smc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
> index 516d340..fed4f0a 100644
> --- a/arch/arm/mach-at91/board-yl-9200.c
> +++ b/arch/arm/mach-at91/board-yl-9200.c
> @@ -42,12 +42,12 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/board.h>
> -#include <mach/at91_aic.h>
> -#include <mach/at91rm9200_mc.h>
> -#include <mach/at91_ramc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91rm9200_mc.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
> index de2ec6b..c5789a1 100644
> --- a/arch/arm/mach-at91/clock.c
> +++ b/arch/arm/mach-at91/clock.c
> @@ -25,9 +25,9 @@
>  #include <linux/io.h>
>  #include <linux/of_address.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include <asm/proc-fns.h>
>  
> diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
> index 0c63815..6d03dc6 100644
> --- a/arch/arm/mach-at91/cpuidle.c
> +++ b/arch/arm/mach-at91/cpuidle.c
> @@ -21,7 +21,7 @@
>  #include <linux/export.h>
>  #include <asm/proc-fns.h>
>  #include <asm/cpuidle.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "pm.h"
>  
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index be42cf0..ce21de2 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -28,8 +28,8 @@
>  
>  #include <asm/mach/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/at91_pio.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_pio.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
> index d8aeb27..c871a14 100644
> --- a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
> +++ b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
> @@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
>  #define AT91_MEMCTRL_SDRAMC    1
>  #define AT91_MEMCTRL_DDRSDR    2
>  
> -#include <mach/at91rm9200_sdramc.h>
> -#include <mach/at91sam9_ddrsdr.h>
> -#include <mach/at91sam9_sdramc.h>
> +#include <mach-at91/at91rm9200_sdramc.h>
> +#include <mach-at91/at91sam9_ddrsdr.h>
> +#include <mach-at91/at91sam9_sdramc.h>
>  
>  #endif /* __AT91_RAMC_H__ */
> diff --git a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
> index 175e1fd..2f6393e 100644
> --- a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
> +++ b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
> @@ -16,7 +16,7 @@
>  #ifndef AT91SAM9_SMC_H
>  #define AT91SAM9_SMC_H
>  
> -#include <mach/cpu.h>
> +#include <mach-at91/cpu.h>
>  
>  #ifndef __ASSEMBLY__
>  struct sam9_smc_config {
> diff --git a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
> index 998cb0c..d8f4109 100644
> --- a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
> +++ b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
> @@ -1,7 +1,7 @@
>  #ifndef __MACH_ATMEL_MCI_H
>  #define __MACH_ATMEL_MCI_H
>  
> -#include <mach/at_hdmac.h>
> +#include <mach-at91/at_hdmac.h>
>  
>  /**
>   * struct mci_dma_data - DMA data for MCI interface
> diff --git a/arch/arm/mach-at91/include/mach-at91/debug-macro.S b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
> index c6bb9e2..8a1599c 100644
> --- a/arch/arm/mach-at91/include/mach-at91/debug-macro.S
> +++ b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
> @@ -11,8 +11,8 @@
>   *
>  */
>  
> -#include <mach/hardware.h>
> -#include <mach/at91_dbgu.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_dbgu.h>
>  
>  #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
>  #define AT91_DBGU AT91_BASE_DBGU0
> diff --git a/arch/arm/mach-at91/include/mach-at91/hardware.h b/arch/arm/mach-at91/include/mach-at91/hardware.h
> index 09242b6..caef81c 100644
> --- a/arch/arm/mach-at91/include/mach-at91/hardware.h
> +++ b/arch/arm/mach-at91/include/mach-at91/hardware.h
> @@ -23,16 +23,16 @@
>  #define AT91_BASE_DBGU1        0xffffee00
>  
>  #if defined(CONFIG_ARCH_AT91X40)
> -#include <mach/at91x40.h>
> +#include <mach-at91/at91x40.h>
>  #else
> -#include <mach/at91rm9200.h>
> -#include <mach/at91sam9260.h>
> -#include <mach/at91sam9261.h>
> -#include <mach/at91sam9263.h>
> -#include <mach/at91sam9rl.h>
> -#include <mach/at91sam9g45.h>
> -#include <mach/at91sam9x5.h>
> -#include <mach/at91sam9n12.h>
> +#include <mach-at91/at91rm9200.h>
> +#include <mach-at91/at91sam9260.h>
> +#include <mach-at91/at91sam9261.h>
> +#include <mach-at91/at91sam9263.h>
> +#include <mach-at91/at91sam9rl.h>
> +#include <mach-at91/at91sam9g45.h>
> +#include <mach-at91/at91sam9x5.h>
> +#include <mach-at91/at91sam9n12.h>
>  
>  /*
>   * On all at91 except rm9200 and x40 have the System Controller starts
> diff --git a/arch/arm/mach-at91/include/mach-at91/memory.h b/arch/arm/mach-at91/include/mach-at91/memory.h
> index 401c207..88c06fd 100644
> --- a/arch/arm/mach-at91/include/mach-at91/memory.h
> +++ b/arch/arm/mach-at91/include/mach-at91/memory.h
> @@ -21,6 +21,6 @@
>  #ifndef __ASM_ARCH_MEMORY_H
>  #define __ASM_ARCH_MEMORY_H
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  
>  #endif
> diff --git a/arch/arm/mach-at91/include/mach-at91/timex.h b/arch/arm/mach-at91/include/mach-at91/timex.h
> index 5e917a6..f4e72e2 100644
> --- a/arch/arm/mach-at91/include/mach-at91/timex.h
> +++ b/arch/arm/mach-at91/include/mach-at91/timex.h
> @@ -21,7 +21,7 @@
>  #ifndef __ASM_ARCH_TIMEX_H
>  #define __ASM_ARCH_TIMEX_H
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  
>  #ifdef CONFIG_ARCH_AT91X40
>  
> diff --git a/arch/arm/mach-at91/include/mach-at91/uncompress.h b/arch/arm/mach-at91/include/mach-at91/uncompress.h
> index 6f6118d..914feb7 100644
> --- a/arch/arm/mach-at91/include/mach-at91/uncompress.h
> +++ b/arch/arm/mach-at91/include/mach-at91/uncompress.h
> @@ -24,10 +24,10 @@
>  
>  #include <linux/io.h>
>  #include <linux/atmel_serial.h>
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  
> -#include <mach/at91_dbgu.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/at91_dbgu.h>
> +#include <mach-at91/cpu.h>
>  
>  void __iomem *at91_uart;
>  
> diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
> index 1e02c0e..eeddbec 100644
> --- a/arch/arm/mach-at91/irq.c
> +++ b/arch/arm/mach-at91/irq.c
> @@ -33,7 +33,7 @@
>  #include <linux/err.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/irq.h>
>  #include <asm/setup.h>
>  
> @@ -42,7 +42,7 @@
>  #include <asm/mach/irq.h>
>  #include <asm/mach/map.h>
>  
> -#include <mach/at91_aic.h>
> +#include <mach-at91/at91_aic.h>
>  
>  void __iomem *at91_aic_base;
>  static struct irq_domain *at91_aic_domain;
> diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
> index 8dfafe7..f921b1e 100644
> --- a/arch/arm/mach-at91/leds.c
> +++ b/arch/arm/mach-at91/leds.c
> @@ -15,7 +15,7 @@
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
>  
> -#include <mach/board.h>
> +#include <mach-at91/board.h>
>  
>  
>  /* ------------------------------------------------------------------------- */
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 2c2d865..a5b940e 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -25,9 +25,9 @@
>  #include <asm/mach/time.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/at91_aic.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/at91_aic.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "generic.h"
>  #include "pm.h"
> @@ -36,8 +36,8 @@
>   * Show the reason for the previous system reset.
>   */
>  
> -#include <mach/at91_rstc.h>
> -#include <mach/at91_shdwc.h>
> +#include <mach-at91/at91_rstc.h>
> +#include <mach-at91/at91_shdwc.h>
>  
>  static void __init show_reset_status(void)
>  {
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 38f467c..529072a 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -11,8 +11,8 @@
>  #ifndef __ARCH_ARM_MACH_AT91_PM
>  #define __ARCH_ARM_MACH_AT91_PM
>  
> -#include <mach/at91_ramc.h>
> -#include <mach/at91rm9200_sdramc.h>
> +#include <mach-at91/at91_ramc.h>
> +#include <mach-at91/at91rm9200_sdramc.h>
>  
>  /*
>   * The AT91RM9200 goes into self-refresh mode with this command, and will
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 098c28d..8f263c6 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -13,9 +13,9 @@
>   */
>  
>  #include <linux/linkage.h>
> -#include <mach/hardware.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_ramc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_ramc.h>
>  
>  
>  #ifdef CONFIG_SOC_AT91SAM9263
> diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
> index 99a0a1d..be40bf2 100644
> --- a/arch/arm/mach-at91/sam9_smc.c
> +++ b/arch/arm/mach-at91/sam9_smc.c
> @@ -14,7 +14,7 @@
>  #include <linux/of.h>
>  #include <linux/of_address.h>
>  
> -#include <mach/at91sam9_smc.h>
> +#include <mach-at91/at91sam9_smc.h>
>  
>  #include "sam9_smc.h"
>  
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 944bffb..0fe58d5 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -14,11 +14,11 @@
>  #include <asm/system_misc.h>
>  #include <asm/mach/map.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/cpu.h>
> -#include <mach/at91_dbgu.h>
> -#include <mach/at91_pmc.h>
> -#include <mach/at91_shdwc.h>
> +#include <mach-at91/hardware.h>
> +#include <mach-at91/cpu.h>
> +#include <mach-at91/at91_dbgu.h>
> +#include <mach-at91/at91_pmc.h>
> +#include <mach-at91/at91_shdwc.h>
>  
>  #include "soc.h"
>  #include "generic.h"
> diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
> index 45c97b1..f7469da 100644
> --- a/arch/arm/mach-bcmring/arch.c
> +++ b/arch/arm/mach-bcmring/arch.c
> @@ -32,11 +32,11 @@
>  #include <asm/pmu.h>
>  
>  #include <asm/mach/arch.h>
> -#include <mach/dma.h>
> -#include <mach/hardware.h>
> -#include <mach/csp/mm_io.h>
> -#include <mach/csp/chipcHw_def.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/dma.h>
> +#include <mach-bcmring/hardware.h>
> +#include <mach-bcmring/csp/mm_io.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  #include <cfg_global.h>
>  
> diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
> index ad237a4..108845f 100644
> --- a/arch/arm/mach-bcmring/clock.c
> +++ b/arch/arm/mach-bcmring/clock.c
> @@ -22,10 +22,10 @@
>  #include <linux/clk.h>
>  #include <linux/spinlock.h>
>  #include <linux/clkdev.h>
> -#include <mach/csp/hw_cfg.h>
> -#include <mach/csp/chipcHw_def.h>
> -#include <mach/csp/chipcHw_reg.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/hw_cfg.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_reg.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  #include "clock.h"
>  
> diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
> index 5e0b981..2e01614 100644
> --- a/arch/arm/mach-bcmring/clock.h
> +++ b/arch/arm/mach-bcmring/clock.h
> @@ -11,7 +11,7 @@
>  * license other than the GPL, without Broadcom's express prior written
>  * consent.
>  *****************************************************************************/
> -#include <mach/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
>  
>  #define CLK_TYPE_PRIMARY         1     /* primary clock must NOT have a parent */
>  #define CLK_TYPE_PLL1            2     /* PPL1 */
> diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
> index adbfb19..4d089b3 100644
> --- a/arch/arm/mach-bcmring/core.c
> +++ b/arch/arm/mach-bcmring/core.c
> @@ -29,8 +29,8 @@
>  #include <linux/amba/bus.h>
>  #include <linux/clkdev.h>
>  
> -#include <mach/csp/mm_addr.h>
> -#include <mach/hardware.h>
> +#include <mach-bcmring/csp/mm_addr.h>
> +#include <mach-bcmring/hardware.h>
>  #include <linux/io.h>
>  #include <asm/irq.h>
>  #include <asm/hardware/arm_timer.h>
> @@ -48,9 +48,9 @@
>  #include "clock.h"
>  
>  #include <csp/secHw.h>
> -#include <mach/csp/secHw_def.h>
> -#include <mach/csp/chipcHw_inline.h>
> -#include <mach/csp/tmrHw_reg.h>
> +#include <mach-bcmring/csp/secHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/tmrHw_reg.h>
>  
>  static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
>  static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
> diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
> index 96273ff..270689d 100644
> --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
> +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
> @@ -30,8 +30,8 @@
>  #include <csp/stdint.h>
>  #include <csp/module.h>
>  
> -#include <mach/csp/chipcHw_def.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  #include <csp/reg.h>
>  #include <csp/delay.h>
> diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
> index 367df75..48e5977 100644
> --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
> +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
> @@ -30,8 +30,8 @@
>  #include <csp/stdint.h>
>  #include <csp/module.h>
>  
> -#include <mach/csp/chipcHw_def.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  #include <csp/reg.h>
>  #include <csp/delay.h>
> diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
> index 2671d88..0aee4f2 100644
> --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
> +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
> @@ -14,8 +14,8 @@
>  
>  /* ---- Include Files ---------------------------------------------------- */
>  #include <csp/stdint.h>
> -#include <mach/csp/chipcHw_def.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  #include <csp/intcHw.h>
>  #include <csp/cache.h>
>  
> diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
> index 54ad964..d466c49 100644
> --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
> +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
> @@ -23,7 +23,7 @@
>  
>  /* ---- Include Files ---------------------------------------------------- */
>  
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  /* ---- Private Constants and Types --------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
> index 6b9be2e..4a9675a 100644
> --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
> +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
> @@ -30,9 +30,9 @@
>  #include <stddef.h>
>  
>  #include <csp/dmacHw.h>
> -#include <mach/csp/dmacHw_reg.h>
> -#include <mach/csp/dmacHw_priv.h>
> -#include <mach/csp/chipcHw_inline.h>
> +#include <mach-bcmring/csp/dmacHw_reg.h>
> +#include <mach-bcmring/csp/dmacHw_priv.h>
> +#include <mach-bcmring/csp/chipcHw_inline.h>
>  
>  /* ---- External Function Prototypes ------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
> index a1f3283..f4e883a 100644
> --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
> +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
> @@ -30,8 +30,8 @@
>  #include <stddef.h>
>  
>  #include <csp/dmacHw.h>
> -#include <mach/csp/dmacHw_reg.h>
> -#include <mach/csp/dmacHw_priv.h>
> +#include <mach-bcmring/csp/dmacHw_reg.h>
> +#include <mach-bcmring/csp/dmacHw_priv.h>
>  
>  extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];   /* Declared in dmacHw.c */
>  
> diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
> index 16225e4..220e314 100644
> --- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
> +++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
> @@ -30,7 +30,7 @@
>  #include <csp/stdint.h>
>  
>  #include <csp/tmrHw.h>
> -#include <mach/csp/tmrHw_reg.h>
> +#include <mach-bcmring/csp/tmrHw_reg.h>
>  
>  #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
>  #define tmrHw_MILLISEC_PER_SEC              (1000)
> diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
> index e5fd241..e90cfdf 100644
> --- a/arch/arm/mach-bcmring/dma.c
> +++ b/arch/arm/mach-bcmring/dma.c
> @@ -31,11 +31,11 @@
>  #include <linux/proc_fs.h>
>  #include <linux/slab.h>
>  
> -#include <mach/timer.h>
> +#include <mach-bcmring/timer.h>
>  
>  #include <linux/pfn.h>
>  #include <linux/atomic.h>
> -#include <mach/dma.h>
> +#include <mach-bcmring/dma.h>
>  
>  /* ---- Public Variables ------------------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
> index e6a1dc4..97d8a04 100644
> --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
> +++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
> @@ -26,7 +26,7 @@
>  #include <stddef.h>
>  
>  #include <csp/stdint.h>
> -#include <mach/csp/dmacHw_reg.h>
> +#include <mach-bcmring/csp/dmacHw_reg.h>
>  
>  /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
>  
> diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
> index 1c639c8..eb7d3ae 100644
> --- a/arch/arm/mach-bcmring/include/csp/intcHw.h
> +++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
> @@ -28,7 +28,7 @@
>  #define _INTCHW_H
>  
>  /* ---- Include Files ---------------------------------------------------- */
> -#include <mach/csp/intcHw_reg.h>
> +#include <mach-bcmring/csp/intcHw_reg.h>
>  
>  /* ---- Public Constants and Types --------------------------------------- */
>  /* ---- Public Variable Externs ------------------------------------------ */
> diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
> index 56654d2..23ac669 100644
> --- a/arch/arm/mach-bcmring/include/csp/reg.h
> +++ b/arch/arm/mach-bcmring/include/csp/reg.h
> @@ -69,7 +69,7 @@
>  /*  */
>  
>  #if defined(__KERNEL__) && !defined(STANDALONE)
> -#include <mach/hardware.h>
> +#include <mach-bcmring/hardware.h>
>  #include <linux/interrupt.h>
>  
>  #define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
> index 933ce68..4a1ecfa 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
> @@ -16,7 +16,7 @@
>  #define CAP_INLINE_H
>  
>  /* ---- Include Files ---------------------------------------------------- */
> -#include <mach/csp/cap.h>
> +#include <mach-bcmring/csp/cap.h>
>  #include <cfg_global.h>
>  
>  /* ---- Public Constants and Types --------------------------------------- */
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
> index 1619733..fe57b08 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
> @@ -20,7 +20,7 @@
>  #include <csp/stdint.h>
>  #include <csp/errno.h>
>  #include <csp/reg.h>
> -#include <mach/csp/chipcHw_reg.h>
> +#include <mach-bcmring/csp/chipcHw_reg.h>
>  
>  /* ---- Public Constants and Types ---------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
> index 03238c2..108209c 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
> @@ -19,8 +19,8 @@
>  
>  #include <csp/errno.h>
>  #include <csp/reg.h>
> -#include <mach/csp/chipcHw_reg.h>
> -#include <mach/csp/chipcHw_def.h>
> +#include <mach-bcmring/csp/chipcHw_reg.h>
> +#include <mach-bcmring/csp/chipcHw_def.h>
>  
>  /* ---- Private Constants and Types --------------------------------------- */
>  typedef enum {
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
> index b162448..85b13d7 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
> @@ -23,9 +23,9 @@
>  #ifndef CHIPCHW_REG_H
>  #define CHIPCHW_REG_H
>  
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  #include <csp/reg.h>
> -#include <mach/csp/ddrcReg.h>
> +#include <mach-bcmring/csp/ddrcReg.h>
>  
>  #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
> index f1b68e2..462c099 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
> @@ -33,7 +33,7 @@ extern "C" {
>  #include <csp/reg.h>
>  #include <csp/stdint.h>
>  
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* ---- Public Constants and Types --------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
> index f1ecf96..1f5263f 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
> @@ -25,7 +25,7 @@
>  #define _DMACHW_REG_H
>  
>  #include <csp/stdint.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* Data type for 64 bit little endian register */
>  typedef struct {
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
> index cfa91be..aad4e17 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
> @@ -19,10 +19,10 @@
>  /* ---- Include Files ---------------------------------------------------- */
>  
>  #include <cfg_global.h>
> -#include <mach/csp/cap_inline.h>
> +#include <mach-bcmring/csp/cap_inline.h>
>  
>  #if defined(__KERNEL__)
> -#include <mach/memory_settings.h>
> +#include <mach-bcmring/memory_settings.h>
>  #else
>  #include <hw_cfg.h>
>  #endif
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
> index 0aeb6a6..0770d7d 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
> @@ -29,7 +29,7 @@
>  /* ---- Include Files ---------------------------------------------------- */
>  #include <csp/stdint.h>
>  #include <csp/reg.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* ---- Public Constants and Types --------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
> index de92ec6..dcb1eae 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
> @@ -27,7 +27,7 @@
>  #define _MM_IO_H
>  
>  /* ---- Include Files ---------------------------------------------------- */
> -#include <mach/csp/mm_addr.h>
> +#include <mach-bcmring/csp/mm_addr.h>
>  
>  #if !defined(CSP_SIMULATION)
>  #include <cfg_global.h>
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
> index d15f5f3..18279ce 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
> @@ -26,7 +26,7 @@
>  #ifndef SECHW_DEF_H
>  #define SECHW_DEF_H
>  
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* Bit mask for various secure device */
>  #define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
> @@ -95,6 +95,6 @@ static inline void secHw_setUnsecure(uint32_t mask    /*  mask of type secHw_BLK_MA
>  /****************************************************************************/
>  static inline uint32_t secHw_getStatus(void);
>  
> -#include <mach/csp/secHw_inline.h>
> +#include <mach-bcmring/csp/secHw_inline.h>
>  
>  #endif /* SECHW_DEF_H */
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
> index 3080ac7..e6069f5 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
> @@ -23,8 +23,8 @@
>  #ifndef _TMRHW_REG_H
>  #define _TMRHW_REG_H
>  
> -#include <mach/csp/mm_io.h>
> -#include <mach/csp/hw_cfg.h>
> +#include <mach-bcmring/csp/mm_io.h>
> +#include <mach-bcmring/csp/hw_cfg.h>
>  /* Base address */
>  #define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
> index 7254378..366caa3 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
> @@ -28,7 +28,7 @@
>  #include <linux/kernel.h>
>  #include <linux/semaphore.h>
>  #include <csp/dmacHw.h>
> -#include <mach/timer.h>
> +#include <mach-bcmring/timer.h>
>  
>  /* ---- Constants and Types ---------------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
> index 2f316f0..8967896 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
> @@ -17,9 +17,9 @@
>   * Low-level IRQ helper macros for BCMRing-based platforms
>   *
>   */
> -#include <mach/irqs.h>
> -#include <mach/hardware.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/irqs.h>
> +#include <mach-bcmring/hardware.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
>                 ldr     \base, =(MM_IO_BASE_INTC0)
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
> index 6ae20a6..c708efd 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
> @@ -23,7 +23,7 @@
>  
>  #include <asm/sizes.h>
>  #include <cfg_global.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* Hardware addresses of major areas.
>   *  *_START is the physical address
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
> index 387376f..ec773c2 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
> @@ -31,7 +31,7 @@
>  
>  /* ---- Include Files ---------------------------------------------------- */
>  #include <csp/reg.h>
> -#include <mach/reg_umi.h>
> +#include <mach-bcmring/reg_umi.h>
>  
>  /* ---- Constants and Types ---------------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
> index 0992842..f659cc1 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
> @@ -31,7 +31,7 @@
>  
>  /* ---- Include Files ---------------------------------------------------- */
>  #include <csp/reg.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  /* ---- Constants and Types ---------------------------------------------- */
>  
> diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
> index 9c9821b..b11fb3f 100644
> --- a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
> +++ b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
> @@ -11,7 +11,7 @@
>  * license other than the GPL, without Broadcom's express prior written
>  * consent.
>  *****************************************************************************/
> -#include <mach/csp/mm_addr.h>
> +#include <mach-bcmring/csp/mm_addr.h>
>  
>  #define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
>  #define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
> diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
> index 437fa68..aa88cac 100644
> --- a/arch/arm/mach-bcmring/irq.c
> +++ b/arch/arm/mach-bcmring/irq.c
> @@ -22,12 +22,12 @@
>  #include <linux/timer.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-bcmring/hardware.h>
>  #include <asm/irq.h>
>  
>  #include <asm/mach/irq.h>
> -#include <mach/csp/intcHw_reg.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/csp/intcHw_reg.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  static void bcmring_mask_irq0(struct irq_data *d)
>  {
> diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
> index 1adec78e..411fa2b 100644
> --- a/arch/arm/mach-bcmring/mm.c
> +++ b/arch/arm/mach-bcmring/mm.c
> @@ -17,8 +17,8 @@
>  #include <asm/page.h>
>  #include <asm/mach/map.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/csp/mm_io.h>
> +#include <mach-bcmring/hardware.h>
> +#include <mach-bcmring/csp/mm_io.h>
>  
>  #define IO_DESC(va, sz) { .virtual = va, \
>         .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
> diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
> index af9c3d7..ba9754d 100644
> --- a/arch/arm/mach-bcmring/timer.c
> +++ b/arch/arm/mach-bcmring/timer.c
> @@ -16,7 +16,7 @@
>  #include <linux/module.h>
>  #include <csp/tmrHw.h>
>  
> -#include <mach/timer.h>
> +#include <mach-bcmring/timer.h>
>  /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
>  /* The real time clock should probably be the real linux clocksource. */
>  /* In the meantime, this file should agree with core.c as to the */
> diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
> index 3fb79a1..82ec281 100644
> --- a/arch/arm/mach-clps711x/autcpu12.c
> +++ b/arch/arm/mach-clps711x/autcpu12.c
> @@ -24,7 +24,7 @@
>  #include <linux/mm.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/sizes.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
> @@ -33,7 +33,7 @@
>  #include <asm/page.h>
>  
>  #include <asm/mach/map.h>
> -#include <mach/autcpu12.h>
> +#include <mach-clps711x/autcpu12.h>
>  
>  #include "common.h"
>  
> diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
> index c314f49..6693600 100644
> --- a/arch/arm/mach-clps711x/cdb89712.c
> +++ b/arch/arm/mach-clps711x/cdb89712.c
> @@ -24,7 +24,7 @@
>  #include <linux/mm.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/pgtable.h>
>  #include <asm/page.h>
>  #include <asm/setup.h>
> diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
> index a70147e..177fb74 100644
> --- a/arch/arm/mach-clps711x/ceiva.c
> +++ b/arch/arm/mach-clps711x/ceiva.c
> @@ -27,7 +27,7 @@
>  
>  #include <linux/kernel.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/page.h>
>  #include <asm/pgtable.h>
>  #include <asm/sizes.h>
> diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
> index f15293b..5b4fa62 100644
> --- a/arch/arm/mach-clps711x/common.c
> +++ b/arch/arm/mach-clps711x/common.c
> @@ -28,7 +28,7 @@
>  #include <linux/sched.h>
>  
>  #include <asm/sizes.h>
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/irq.h>
>  #include <asm/leds.h>
>  #include <asm/pgtable.h>
> diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
> index 4372f06..6d3e94e 100644
> --- a/arch/arm/mach-clps711x/edb7211-mm.c
> +++ b/arch/arm/mach-clps711x/edb7211-mm.c
> @@ -23,7 +23,7 @@
>  #include <linux/init.h>
>  #include <linux/bug.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/page.h>
>  #include <asm/sizes.h>
>   
> diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
> index 3a3f0b7..12a1368 100644
> --- a/arch/arm/mach-clps711x/fortunet.c
> +++ b/arch/arm/mach-clps711x/fortunet.c
> @@ -23,7 +23,7 @@
>  #include <linux/init.h>
>  #include <linux/initrd.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
>  
> diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
> index 118b3d9..52bd3ef 100644
> --- a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
> +++ b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
> @@ -11,7 +11,7 @@
>   *
>  */
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  
>                 .macro  addruart, rp, rv, tmp
>  #ifndef CONFIG_DEBUG_CLPS711X_UART2
> diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
> index 56e5c2c..889521e 100644
> --- a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
> +++ b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
> @@ -7,7 +7,7 @@
>   * License version 2. This program is licensed "as is" without any
>   * warranty of any kind, whether express or implied.
>   */
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  
>                 .macro  get_irqnr_preamble, base, tmp
>                 .endm
> diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
> index 13a64fc..29f3409 100644
> --- a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
> +++ b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
> @@ -22,7 +22,7 @@
>  #ifndef __MACH_HARDWARE_H
>  #define __MACH_HARDWARE_H
>  
> -#include <mach/clps711x.h>
> +#include <mach-clps711x/clps711x.h>
>  
>  #define CLPS711X_VIRT_BASE     IOMEM(0xff000000)
>  
> ---
> Intentionally cut off for review. If you managed to read this far, you
> get the idea. See the rest at
> http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=d59d6b49ed5287dd0131acda9428fdc0bb0a7365
> 
> 
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
> 


From arnd at arndb.de  Wed Aug 22 11:31:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 15:31:42 +0000
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <alpine.LFD.2.02.1208221106010.1754@xanadu.home>
References: <201208221253.07278.arnd@arndb.de>
 <alpine.LFD.2.02.1208221106010.1754@xanadu.home>
Message-ID: <201208221531.42845.arnd@arndb.de>

On Wednesday 22 August 2012, Nicolas Pitre wrote:
> On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > There are two branches available in the arm-soc tree:
> > 
> > 1. This series,
> >    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
> >    This just moves header files around and changes most of the
> >    files including them. There are a few remaining drivers
> >    and platform files that keep including a generic file name
> >    like <mach/uncompress.h>. It remains possible to do that,
> >    and I've run extensive tests to ensure I did not break
> >    anything with this. However, each of these instances means
> >    that there is something that stops working when you get to
> >    the real multiplatform kernel and we still need to deal
> >    with them one by one.
> 
> The content of <mach/uncompress.h> is fundamentally machine or SOC 
> specific.  We already know it is generally incompatible with a multi 
> platform kernel.  So the best way to deal with this at the moment is 
> probably to just provide a dummy uncompress.h with empty stubs whenever 
> CONFIG_ARCH_MULTIPLATFORM is selected.  The effect from this is that 
> there wouldn't be any "Uncompressing the kernel... Done" output anymore, 
> which should be an acceptable compromise until a better solution is 
> found.

Yes, that is what I do in the second series.

> One problem is that some (very few) machines define a method in that 
> file to keep a hardware watchdog alive.  This might not be the case for 
> all the intended targets to gather in a single kernel binary image 
> though.

Ok. I think we have a list of known issues somewhere, we should add this
one. I just can't remember where that list is located.

> Another issue is the fact that some platforms do very ugly 
> layer-violating hacks where the decompressor selects a serial port for 
> early output and then store that selection in some arbitrary memory 
> location for the main kernel to blindly use, making the decompressor 
> mandatory.  OMAP and Davinci are prime example of such "abuse" which 
> would need to be fixed.

Same thing here I guess.

Thanks for the input!

	Arnd


From nicolas.pitre at linaro.org  Wed Aug 22 11:33:32 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:33:32 -0400 (EDT)
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <201208221301.19439.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221133030.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> These are lots of device drivers that include machine
> specific header files from ARM platforms and that are
> not easily scriptable. The changes have been found through
> manual inspection and should cause no visible changes
> because of the build script that maps the old names to the
> new ones.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  drivers/char/ds1620.c                                 |    2 +-
>  drivers/char/hw_random/ixp4xx-rng.c                   |    2 +-
>  drivers/cpufreq/db8500-cpufreq.c                      |    2 +-
>  drivers/cpufreq/exynos-cpufreq.c                      |    2 +-
>  drivers/cpufreq/exynos4210-cpufreq.c                  |    4 ++--
>  drivers/cpufreq/exynos4x12-cpufreq.c                  |    4 ++--
>  drivers/cpufreq/exynos5250-cpufreq.c                  |    6 +++---
>  drivers/cpufreq/omap-cpufreq.c                        |    2 +-
>  drivers/cpufreq/s5pv210-cpufreq.c                     |    2 +-
>  drivers/crypto/omap-sham.c                            |    2 +-
>  drivers/crypto/tegra-aes.c                            |    2 +-
>  drivers/devfreq/exynos4_bus.c                         |    2 +-
>  drivers/dma/ep93xx_dma.c                              |    2 +-
>  drivers/dma/imx-dma.c                                 |    4 ++--
>  drivers/gpio/gpio-omap.c                              |    4 ++--
>  drivers/gpio/gpio-pxa.c                               |    8 +++++++-
>  drivers/i2c/busses/i2c-acorn.c                        |    2 +-
>  drivers/i2c/busses/i2c-davinci.c                      |    4 ++--
>  drivers/i2c/busses/i2c-imx.c                          |    4 ++--
>  drivers/i2c/busses/i2c-nuc900.c                       |    4 ++--
>  drivers/i2c/busses/i2c-tegra.c                        |    2 +-
>  drivers/input/misc/ixp4xx-beeper.c                    |    2 +-
>  drivers/input/mouse/rpcmouse.c                        |    2 +-
>  drivers/input/serio/rpckbd.c                          |    2 +-
>  drivers/input/touchscreen/atmel_tsadcc.c              |    4 ++--
>  drivers/input/touchscreen/h3600_ts_input.c            |    4 ++--
>  drivers/input/touchscreen/mainstone-wm97xx.c          |    2 +-
>  drivers/input/touchscreen/zylonite-wm97xx.c           |    6 +++---
>  drivers/leds/leds-fsg.c                               |    2 +-
>  drivers/media/video/pxa_camera.c                      |    4 ++--
>  drivers/mfd/dbx500-prcmu-regs.h                       |    2 +-
>  drivers/misc/ep93xx_pwm.c                             |    2 +-
>  drivers/misc/spear13xx_pcie_gadget.c                  |    4 ++--
>  drivers/mmc/host/at91_mci.c                           |    4 ++--
>  drivers/mmc/host/mxcmmc.c                             |    6 +++---
>  drivers/mmc/host/omap_hsmmc.c                         |    2 +-
>  drivers/mmc/host/pxamci.c                             |    6 +++---
>  drivers/mtd/maps/cdb89712.c                           |    2 +-
>  drivers/mtd/maps/h720x-flash.c                        |    2 +-
>  drivers/mtd/maps/pxa2xx-flash.c                       |    2 +-
>  drivers/mtd/maps/sa1100-flash.c                       |    2 +-
>  drivers/mtd/nand/ams-delta.c                          |    2 +-
>  drivers/mtd/nand/sharpsl.c                            |    2 +-
>  drivers/net/can/at91_can.c                            |    2 +-
>  drivers/net/ethernet/amd/am79c961a.c                  |    2 +-
>  drivers/net/ethernet/cirrus/ep93xx_eth.c              |    2 +-
>  drivers/net/ethernet/nxp/lpc_eth.c                    |    6 +++---
>  drivers/net/ethernet/smsc/smc911x.h                   |    2 +-
>  drivers/net/ethernet/smsc/smc91x.h                    |    2 +-
>  drivers/net/irda/ep7211-sir.c                         |    2 +-
>  drivers/net/irda/pxaficp_ir.c                         |    8 ++++----
>  drivers/net/irda/sa1100_ir.c                          |    2 +-
>  drivers/pcmcia/omap_cf.c                              |    2 +-
>  drivers/pcmcia/pxa2xx_cm_x2xx.c                       |    2 +-
>  drivers/pcmcia/sa1111_jornada720.c                    |    2 +-
>  drivers/pcmcia/sa11xx_base.c                          |    2 +-
>  drivers/power/avs/smartreflex.c                       |    1 +
>  drivers/pwm/pwm-imx.c                                 |    2 +-
>  drivers/rtc/rtc-mxc.c                                 |    2 +-
>  drivers/rtc/rtc-pxa.c                                 |    2 +-
>  drivers/rtc/rtc-stmp3xxx.c                            |    2 +-
>  drivers/scsi/arm/acornscsi-io.S                       |    2 +-
>  drivers/spi/spi-imx.c                                 |    2 +-
>  drivers/spi/spi-omap-uwire.c                          |    2 +-
>  drivers/spi/spi-s3c24xx-fiq.S                         |    4 ++--
>  drivers/spi/spi-tegra.c                               |    2 +-
>  drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c |    4 ++--
>  drivers/tty/serial/21285.c                            |    2 +-
>  drivers/tty/serial/atmel_serial.c                     |    6 ++++--
>  drivers/tty/serial/clps711x.c                         |    2 +-
>  drivers/tty/serial/msm_serial_hs.c                    |    4 ++--
>  drivers/tty/serial/sa1100.c                           |    4 ++--
>  drivers/tty/serial/serial_ks8695.c                    |    4 ++--
>  drivers/uio/uio_pruss.c                               |    2 +-
>  drivers/usb/gadget/fsl_mxc_udc.c                      |    2 +-
>  drivers/usb/gadget/imx_udc.c                          |    4 ++--
>  drivers/usb/gadget/pxa27x_udc.c                       |    4 ++--
>  drivers/usb/host/ohci-at91.c                          |    6 +++---
>  drivers/usb/host/ohci-exynos.c                        |    2 +-
>  drivers/usb/musb/davinci.c                            |    4 ++--
>  drivers/usb/musb/ux500_dma.c                          |    2 +-
>  drivers/usb/otg/msm_otg.c                             |    2 +-
>  drivers/video/backlight/omap1_bl.c                    |    2 +-
>  drivers/video/ep93xx-fb.c                             |    2 +-
>  drivers/video/nuc900fb.h                              |    4 ++--
>  drivers/video/pnx4008/dum.h                           |    2 +-
>  drivers/w1/masters/omap_hdq.c                         |    2 +-
>  drivers/watchdog/imx2_wdt.c                           |    2 +-
>  drivers/watchdog/ixp4xx_wdt.c                         |    2 +-
>  drivers/watchdog/ks8695_wdt.c                         |    4 ++--
>  drivers/watchdog/wdt285.c                             |    2 +-
>  91 files changed, 137 insertions(+), 128 deletions(-)
> 
> diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
> index aab9605..b4c21b1 100644
> --- a/drivers/char/ds1620.c
> +++ b/drivers/char/ds1620.c
> @@ -10,7 +10,7 @@
>  #include <linux/init.h>
>  #include <linux/mutex.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-footbridge/hardware.h>
>  #include <asm/mach-types.h>
>  #include <asm/uaccess.h>
>  #include <asm/therm.h>
> diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c
> index 263567f..42889bb 100644
> --- a/drivers/char/hw_random/ixp4xx-rng.c
> +++ b/drivers/char/hw_random/ixp4xx-rng.c
> @@ -23,7 +23,7 @@
>  #include <linux/hw_random.h>
>  
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-ixp4xx/hardware.h>
>  
>  
>  static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer)
> diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
> index 74b830b..c771360 100644
> --- a/drivers/cpufreq/db8500-cpufreq.c
> +++ b/drivers/cpufreq/db8500-cpufreq.c
> @@ -13,7 +13,7 @@
>  #include <linux/delay.h>
>  #include <linux/slab.h>
>  #include <linux/mfd/dbx500-prcmu.h>
> -#include <mach/id.h>
> +#include <mach-ux500/id.h>
>  
>  static struct cpufreq_frequency_table freq_table[] = {
>         [0] = {
> diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
> index 9382a6b..637782b 100644
> --- a/drivers/cpufreq/exynos-cpufreq.c
> +++ b/drivers/cpufreq/exynos-cpufreq.c
> @@ -18,7 +18,7 @@
>  #include <linux/cpufreq.h>
>  #include <linux/suspend.h>
>  
> -#include <mach/cpufreq.h>
> +#include <mach-exynos/cpufreq.h>
>  
>  #include <plat-samsung/cpu.h>
>  
> diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
> index fb148fa..33d3d4c 100644
> --- a/drivers/cpufreq/exynos4210-cpufreq.c
> +++ b/drivers/cpufreq/exynos4210-cpufreq.c
> @@ -17,8 +17,8 @@
>  #include <linux/slab.h>
>  #include <linux/cpufreq.h>
>  
> -#include <mach/regs-clock.h>
> -#include <mach/cpufreq.h>
> +#include <mach-exynos/regs-clock.h>
> +#include <mach-exynos/cpufreq.h>
>  
>  #define CPUFREQ_LEVEL_END      L5
>  
> diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
> index 8c5a7af..e7aa354 100644
> --- a/drivers/cpufreq/exynos4x12-cpufreq.c
> +++ b/drivers/cpufreq/exynos4x12-cpufreq.c
> @@ -17,8 +17,8 @@
>  #include <linux/slab.h>
>  #include <linux/cpufreq.h>
>  
> -#include <mach/regs-clock.h>
> -#include <mach/cpufreq.h>
> +#include <mach-exynos/regs-clock.h>
> +#include <mach-exynos/cpufreq.h>
>  
>  #define CPUFREQ_LEVEL_END      (L13 + 1)
>  
> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
> index e64c253..74950a3 100644
> --- a/drivers/cpufreq/exynos5250-cpufreq.c
> +++ b/drivers/cpufreq/exynos5250-cpufreq.c
> @@ -17,9 +17,9 @@
>  #include <linux/slab.h>
>  #include <linux/cpufreq.h>
>  
> -#include <mach/map.h>
> -#include <mach/regs-clock.h>
> -#include <mach/cpufreq.h>
> +#include <mach-exynos/map.h>
> +#include <mach-exynos/regs-clock.h>
> +#include <mach-exynos/cpufreq.h>
>  
>  #define CPUFREQ_LEVEL_END      (L15 + 1)
>  
> diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
> index 4449907..45b2331 100644
> --- a/drivers/cpufreq/omap-cpufreq.c
> +++ b/drivers/cpufreq/omap-cpufreq.c
> @@ -35,7 +35,7 @@
>  #include <plat-omap/common.h>
>  #include <plat-omap/omap_device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-omap2/hardware.h>
>  
>  /* OPP tolerance in percentage */
>  #define        OPP_TOLERANCE   4
> diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
> index a484aae..04dfc10 100644
> --- a/drivers/cpufreq/s5pv210-cpufreq.c
> +++ b/drivers/cpufreq/s5pv210-cpufreq.c
> @@ -20,7 +20,7 @@
>  #include <linux/regulator/consumer.h>
>  #include <linux/suspend.h>
>  
> -#include <mach/map.h>
> +#include <mach-s5pv210/map.h>
>  #include <mach/regs-clock.h>
>  
>  static struct clk *cpu_clk;
> diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
> index 737afed..98e877d 100644
> --- a/drivers/crypto/omap-sham.c
> +++ b/drivers/crypto/omap-sham.c
> @@ -39,7 +39,7 @@
>  
>  #include <plat-omap/cpu.h>
>  #include <plat-omap/dma.h>
> -#include <mach/irqs.h>
> +#include <mach-omap2/irqs.h>
>  
>  #define SHA_REG_DIGEST(x)              (0x00 + ((x) * 0x04))
>  #define SHA_REG_DIN(x)                 (0x1C + ((x) * 0x04))
> diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
> index ac236f6..971bd27 100644
> --- a/drivers/crypto/tegra-aes.c
> +++ b/drivers/crypto/tegra-aes.c
> @@ -41,7 +41,7 @@
>  #include <linux/completion.h>
>  #include <linux/workqueue.h>
>  
> -#include <mach/clk.h>
> +#include <mach-tegra/clk.h>
>  
>  #include <crypto/scatterwalk.h>
>  #include <crypto/aes.h>
> diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
> index c8af6d4..e8d7ce8 100644
> --- a/drivers/devfreq/exynos4_bus.c
> +++ b/drivers/devfreq/exynos4_bus.c
> @@ -30,7 +30,7 @@
>  extern unsigned int exynos_result_of_asv;
>  #endif
>  
> -#include <mach/regs-clock.h>
> +#include <mach-exynos/regs-clock.h>
>  
>  #include <plat-samsung/map-s5p.h>
>  
> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index c64917e..09d7112 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -26,7 +26,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/slab.h>
>  
> -#include <mach/dma.h>
> +#include <mach-ep93xx/dma.h>
>  
>  #include "dmaengine.h"
>  
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index fcfeb3c..0597cbc 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -28,8 +28,8 @@
>  #include <linux/module.h>
>  
>  #include <asm/irq.h>
> -#include <mach/dma.h>
> -#include <mach/hardware.h>
> +#include <mach-imx/dma.h>
> +#include <mach-imx/hardware.h>
>  
>  #include "dmaengine.h"
>  #define IMXDMA_MAX_CHAN_DESCRIPTORS    16
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index e6efd77..45592ca 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -26,9 +26,9 @@
>  #include <linux/of_device.h>
>  #include <linux/irqdomain.h>
>  
> -#include <mach/hardware.h>
> +#include <plat-omap/hardware.h>
>  #include <asm/irq.h>
> -#include <mach/irqs.h>
> +#include <plat-omap/irqs.h>
>  #include <asm/gpio.h>
>  #include <asm/mach/irq.h>
>  
> diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
> index 58a6a63..c6440a5 100644
> --- a/drivers/gpio/gpio-pxa.c
> +++ b/drivers/gpio/gpio-pxa.c
> @@ -26,7 +26,13 @@
>  #include <linux/syscore_ops.h>
>  #include <linux/slab.h>
>  
> -#include <mach/irqs.h>
> +#ifdef CONFIG_ARCH_PXA
> +#include <mach-pxa/irqs.h>
> +#endif
> +
> +#ifdef CONFIG_ARCH_MMP
> +#include <mach-mmp/irqs.h>
> +#endif
>  
>  /*
>   * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
> diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
> index ed9f48d..4d0f7797 100644
> --- a/drivers/i2c/busses/i2c-acorn.c
> +++ b/drivers/i2c/busses/i2c-acorn.c
> @@ -17,7 +17,7 @@
>  #include <linux/i2c-algo-bit.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-rpc/hardware.h>
>  #include <asm/hardware/ioc.h>
>  
>  #define FORCE_ONES     0xdc
> diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
> index 79b4bcb..d163b73 100644
> --- a/drivers/i2c/busses/i2c-davinci.c
> +++ b/drivers/i2c/busses/i2c-davinci.c
> @@ -39,8 +39,8 @@
>  #include <linux/cpufreq.h>
>  #include <linux/gpio.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/i2c.h>
> +#include <mach-davinci/hardware.h>
> +#include <mach-davinci/i2c.h>
>  
>  /* ----- global defines ----------------------------------------------- */
>  
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index 0722f86..a8ffc39 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -53,8 +53,8 @@
>  #include <linux/of_i2c.h>
>  #include <linux/pinctrl/consumer.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/i2c.h>
> +#include <mach-imx/hardware.h>
> +#include <mach-imx/i2c.h>
>  
>  /** Defines ********************************************************************
>  *******************************************************************************/
> diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
> index a26dfb8..cfe6803 100644
> --- a/drivers/i2c/busses/i2c-nuc900.c
> +++ b/drivers/i2c/busses/i2c-nuc900.c
> @@ -28,8 +28,8 @@
>  #include <linux/slab.h>
>  #include <linux/io.h>
>  
> -#include <mach/mfp.h>
> -#include <mach/i2c.h>
> +#include <mach-w90x900/mfp.h>
> +#include <mach-w90x900/i2c.h>
>  
>  /* nuc900 i2c registers offset */
>  
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 66eb53f..8712414 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -31,7 +31,7 @@
>  
>  #include <asm/unaligned.h>
>  
> -#include <mach/clk.h>
> +#include <mach-tegra/clk.h>
>  
>  #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
>  #define BYTES_PER_FIFO_WORD 4
> diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
> index 50e2830..9b644e1 100644
> --- a/drivers/input/misc/ixp4xx-beeper.c
> +++ b/drivers/input/misc/ixp4xx-beeper.c
> @@ -20,7 +20,7 @@
>  #include <linux/delay.h>
>  #include <linux/platform_device.h>
>  #include <linux/interrupt.h>
> -#include <mach/hardware.h>
> +#include <mach-ixp4xx/hardware.h>
>  
>  MODULE_AUTHOR("Alessandro Zummo <a.zummo at towertech.it>");
>  MODULE_DESCRIPTION("ixp4xx beeper driver");
> diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
> index 272dedd..41c1fa4 100644
> --- a/drivers/input/mouse/rpcmouse.c
> +++ b/drivers/input/mouse/rpcmouse.c
> @@ -24,7 +24,7 @@
>  #include <linux/input.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-rpc/hardware.h>
>  #include <asm/irq.h>
>  #include <asm/hardware/iomd.h>
>  
> diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
> index 2af5df6..5bee7e0 100644
> --- a/drivers/input/serio/rpckbd.c
> +++ b/drivers/input/serio/rpckbd.c
> @@ -36,7 +36,7 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-rpc/hardware.h>
>  #include <asm/hardware/iomd.h>
>  
>  MODULE_AUTHOR("Vojtech Pavlik, Russell King");
> diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
> index 201b2d2..00f8aac 100644
> --- a/drivers/input/touchscreen/atmel_tsadcc.c
> +++ b/drivers/input/touchscreen/atmel_tsadcc.c
> @@ -22,8 +22,8 @@
>  #include <linux/clk.h>
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
>  
>  /* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
>  
> diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
> index b9e8686..39a0ce5 100644
> --- a/drivers/input/touchscreen/h3600_ts_input.c
> +++ b/drivers/input/touchscreen/h3600_ts_input.c
> @@ -39,8 +39,8 @@
>  #include <linux/delay.h>
>  
>  /* SA1100 serial defines */
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> +#include <mach-sa1100/hardware.h>
> +#include <mach-sa1100/irqs.h>
>  
>  #define DRIVER_DESC    "H3600 touchscreen driver"
>  
> diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
> index 7d2b213..997e627 100644
> --- a/drivers/input/touchscreen/mainstone-wm97xx.c
> +++ b/drivers/input/touchscreen/mainstone-wm97xx.c
> @@ -33,7 +33,7 @@
>  #include <linux/io.h>
>  #include <linux/gpio.h>
>  
> -#include <mach/regs-ac97.h>
> +#include <mach-pxa/regs-ac97.h>
>  
>  #include <asm/mach-types.h>
>  
> diff --git a/drivers/input/touchscreen/zylonite-wm97xx.c b/drivers/input/touchscreen/zylonite-wm97xx.c
> index bf0869a7..be59125 100644
> --- a/drivers/input/touchscreen/zylonite-wm97xx.c
> +++ b/drivers/input/touchscreen/zylonite-wm97xx.c
> @@ -28,9 +28,9 @@
>  #include <linux/io.h>
>  #include <linux/wm97xx.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/mfp.h>
> -#include <mach/regs-ac97.h>
> +#include <mach-pxa/hardware.h>
> +#include <mach-pxa/mfp.h>
> +#include <mach-pxa/regs-ac97.h>
>  
>  struct continuous {
>         u16 id;    /* codec id */
> diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c
> index b9053fa..683b01d 100644
> --- a/drivers/leds/leds-fsg.c
> +++ b/drivers/leds/leds-fsg.c
> @@ -20,7 +20,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/leds.h>
>  #include <linux/module.h>
> -#include <mach/hardware.h>
> +#include <mach-ixp4xx/hardware.h>
>  #include <asm/io.h>
>  
>  #define FSG_LED_WLAN_BIT       0
> diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
> index 9c21e01..0d76655 100644
> --- a/drivers/media/video/pxa_camera.c
> +++ b/drivers/media/video/pxa_camera.c
> @@ -36,8 +36,8 @@
>  
>  #include <linux/videodev2.h>
>  
> -#include <mach/dma.h>
> -#include <mach/camera.h>
> +#include <mach-pxa/dma.h>
> +#include <mach-pxa/camera.h>
>  
>  #define PXA_CAM_VERSION "0.0.6"
>  #define PXA_CAM_DRV_NAME "pxa27x-camera"
> diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
> index 23108a6..7de55f8 100644
> --- a/drivers/mfd/dbx500-prcmu-regs.h
> +++ b/drivers/mfd/dbx500-prcmu-regs.h
> @@ -13,7 +13,7 @@
>  #ifndef __DB8500_PRCMU_REGS_H
>  #define __DB8500_PRCMU_REGS_H
>  
> -#include <mach/hardware.h>
> +#include <mach-ux500/hardware.h>
>  
>  #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
>  
> diff --git a/drivers/misc/ep93xx_pwm.c b/drivers/misc/ep93xx_pwm.c
> index 16d7179..a996270 100644
> --- a/drivers/misc/ep93xx_pwm.c
> +++ b/drivers/misc/ep93xx_pwm.c
> @@ -24,7 +24,7 @@
>  #include <linux/err.h>
>  #include <linux/io.h>
>  
> -#include <mach/platform.h>
> +#include <mach-ep93xx/platform.h>
>  
>  #define EP93XX_PWMx_TERM_COUNT 0x00
>  #define EP93XX_PWMx_DUTY_CYCLE 0x04
> diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c
> index 123ed98..0a32042 100644
> --- a/drivers/misc/spear13xx_pcie_gadget.c
> +++ b/drivers/misc/spear13xx_pcie_gadget.c
> @@ -20,8 +20,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/pci_regs.h>
>  #include <linux/configfs.h>
> -#include <mach/pcie.h>
> -#include <mach/misc_regs.h>
> +#include <mach-spear13xx/pcie.h>
> +#include <mach-spear13xx/misc_regs.h>
>  
>  #define IN0_MEM_SIZE   (200 * 1024 * 1024 - 1)
>  /* In current implementation address translation is done using IN0 only.
> diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
> index efdb81d..ec7f665 100644
> --- a/drivers/mmc/host/at91_mci.c
> +++ b/drivers/mmc/host/at91_mci.c
> @@ -75,8 +75,8 @@
>  #include <asm/irq.h>
>  #include <asm/gpio.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
>  
>  #include "at91_mci.h"
>  
> diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
> index 28ed52d..dec1bb1 100644
> --- a/drivers/mmc/host/mxcmmc.c
> +++ b/drivers/mmc/host/mxcmmc.c
> @@ -38,10 +38,10 @@
>  #include <asm/dma.h>
>  #include <asm/irq.h>
>  #include <asm/sizes.h>
> -#include <mach/mmc.h>
> +#include <mach-imx/mmc.h>
>  
> -#include <mach/dma.h>
> -#include <mach/hardware.h>
> +#include <mach-imx/dma.h>
> +#include <mach-imx/hardware.h>
>  
>  #define DRIVER_NAME "mxc-mmc"
>  
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 198066c..194bc04 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -39,7 +39,7 @@
>  #include <linux/gpio.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/pm_runtime.h>
> -#include <mach/hardware.h>
> +#include <plat-omap/hardware.h>
>  #include <plat-omap/board.h>
>  #include <plat-omap/mmc.h>
>  #include <plat-omap/cpu.h>
> diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
> index cb2dc0e..8b01058 100644
> --- a/drivers/mmc/host/pxamci.c
> +++ b/drivers/mmc/host/pxamci.c
> @@ -33,9 +33,9 @@
>  
>  #include <asm/sizes.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/dma.h>
> -#include <mach/mmc.h>
> +#include <mach-pxa/hardware.h>
> +#include <mach-pxa/dma.h>
> +#include <mach-pxa/mmc.h>
>  
>  #include "pxamci.h"
>  
> diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
> index c29cbf8..c224dd4 100644
> --- a/drivers/mtd/maps/cdb89712.c
> +++ b/drivers/mtd/maps/cdb89712.c
> @@ -9,7 +9,7 @@
>  #include <linux/ioport.h>
>  #include <linux/init.h>
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/map.h>
>  #include <linux/mtd/partitions.h>
> diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c
> index 8ed6cb4..3206fef 100644
> --- a/drivers/mtd/maps/h720x-flash.c
> +++ b/drivers/mtd/maps/h720x-flash.c
> @@ -16,7 +16,7 @@
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/map.h>
>  #include <linux/mtd/partitions.h>
> -#include <mach/hardware.h>
> +#include <mach-h720x/hardware.h>
>  #include <asm/io.h>
>  
>  static struct mtd_info *mymtd;
> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
> index 81884c2..8a82445 100644
> --- a/drivers/mtd/maps/pxa2xx-flash.c
> +++ b/drivers/mtd/maps/pxa2xx-flash.c
> @@ -20,7 +20,7 @@
>  #include <linux/mtd/partitions.h>
>  
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-pxa/hardware.h>
>  
>  #include <asm/mach/flash.h>
>  
> diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c
> index a675bdb..2f234e6 100644
> --- a/drivers/mtd/maps/sa1100-flash.c
> +++ b/drivers/mtd/maps/sa1100-flash.c
> @@ -19,7 +19,7 @@
>  #include <linux/mtd/partitions.h>
>  #include <linux/mtd/concat.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-sa1100/hardware.h>
>  #include <asm/sizes.h>
>  #include <asm/mach/flash.h>
>  
> diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
> index 1386f6b..7a921a1 100644
> --- a/drivers/mtd/nand/ams-delta.c
> +++ b/drivers/mtd/nand/ams-delta.c
> @@ -24,7 +24,7 @@
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-omap1/hardware.h>
>  #include <asm/sizes.h>
>  #include <linux/gpio.h>
>  #include <plat-omap/board-ams-delta.h>
> diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
> index 3421e37..866aaac 100644
> --- a/drivers/mtd/nand/sharpsl.c
> +++ b/drivers/mtd/nand/sharpsl.c
> @@ -25,7 +25,7 @@
>  #include <linux/platform_device.h>
>  
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-pxa/hardware.h>
>  #include <asm/mach-types.h>
>  
>  struct sharpsl_nand {
> diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
> index fcff73a..8f14511 100644
> --- a/drivers/net/can/at91_can.c
> +++ b/drivers/net/can/at91_can.c
> @@ -37,7 +37,7 @@
>  #include <linux/can/dev.h>
>  #include <linux/can/error.h>
>  
> -#include <mach/board.h>
> +#include <mach-at91/board.h>
>  
>  #define AT91_MB_MASK(i)                ((1 << (i)) - 1)
>  
> diff --git a/drivers/net/ethernet/amd/am79c961a.c b/drivers/net/ethernet/amd/am79c961a.c
> index e10ffad..89746bf 100644
> --- a/drivers/net/ethernet/amd/am79c961a.c
> +++ b/drivers/net/ethernet/amd/am79c961a.c
> @@ -29,7 +29,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-ebsa110/hardware.h>
>  
>  #define TX_BUFFERS 15
>  #define RX_BUFFERS 25
> diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> index 78c5521..7ad8b0d 100644
> --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
> +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> @@ -26,7 +26,7 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-ep93xx/hardware.h>
>  
>  #define DRV_MODULE_NAME                "ep93xx-eth"
>  #define DRV_MODULE_VERSION     "0.1"
> diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
> index 4069eda..5be01c0 100644
> --- a/drivers/net/ethernet/nxp/lpc_eth.c
> +++ b/drivers/net/ethernet/nxp/lpc_eth.c
> @@ -45,9 +45,9 @@
>  #include <linux/types.h>
>  
>  #include <linux/io.h>
> -#include <mach/board.h>
> -#include <mach/platform.h>
> -#include <mach/hardware.h>
> +#include <mach-lpc32xx/board.h>
> +#include <mach-lpc32xx/platform.h>
> +#include <mach-lpc32xx/hardware.h>
>  
>  #define MODNAME "lpc-eth"
>  #define DRV_VERSION "1.00"
> diff --git a/drivers/net/ethernet/smsc/smc911x.h b/drivers/net/ethernet/smsc/smc911x.h
> index 3269292..80eb9d0 100644
> --- a/drivers/net/ethernet/smsc/smc911x.h
> +++ b/drivers/net/ethernet/smsc/smc911x.h
> @@ -211,7 +211,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
>  
>  #ifdef SMC_USE_PXA_DMA
>  
> -#include <mach/dma.h>
> +#include <mach-pxa/dma.h>
>  
>  /*
>   * Define the request and free functions
> diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
> index 7f4beeb..754af90 100644
> --- a/drivers/net/ethernet/smsc/smc91x.h
> +++ b/drivers/net/ethernet/smsc/smc91x.h
> @@ -364,7 +364,7 @@ struct smc_local {
>   * as RX which can overrun memory and lose packets.
>   */
>  #include <linux/dma-mapping.h>
> -#include <mach-sa1100/dma.h>
> +#include <mach-pxa/dma.h>
>  
>  #ifdef SMC_insl
>  #undef SMC_insl
> diff --git a/drivers/net/irda/ep7211-sir.c b/drivers/net/irda/ep7211-sir.c
> index f83c5b8..8f8d91c 100644
> --- a/drivers/net/irda/ep7211-sir.c
> +++ b/drivers/net/irda/ep7211-sir.c
> @@ -14,7 +14,7 @@
>  #include <net/irda/irda_device.h>
>  
>  #include <asm/io.h>
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  
>  #include "sir-dev.h"
>  
> diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
> index 8d54767..86073eb 100644
> --- a/drivers/net/irda/pxaficp_ir.c
> +++ b/drivers/net/irda/pxaficp_ir.c
> @@ -27,10 +27,10 @@
>  #include <net/irda/wrapper.h>
>  #include <net/irda/irda_device.h>
>  
> -#include <mach/dma.h>
> -#include <mach/irda.h>
> -#include <mach/regs-uart.h>
> -#include <mach/regs-ost.h>
> +#include <mach-pxa/dma.h>
> +#include <mach-pxa/irda.h>
> +#include <mach-pxa/regs-uart.h>
> +#include <mach-pxa/regs-ost.h>
>  
>  #define FICP           __REG(0x40800000)  /* Start of FICP area */
>  #define ICCR0          __REG(0x40800000)  /* ICP Control Register 0 */
> diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
> index e250675..3f88a39 100644
> --- a/drivers/net/irda/sa1100_ir.c
> +++ b/drivers/net/irda/sa1100_ir.c
> @@ -37,7 +37,7 @@
>  #include <net/irda/wrapper.h>
>  #include <net/irda/irda_device.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-sa1100/hardware.h>
>  #include <asm/mach/irda.h>
>  
>  static int power_level = 3;
> diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
> index adb5b1e..070eaa6 100644
> --- a/drivers/pcmcia/omap_cf.c
> +++ b/drivers/pcmcia/omap_cf.c
> @@ -20,7 +20,7 @@
>  
>  #include <pcmcia/ss.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-omap1/hardware.h>
>  #include <asm/io.h>
>  #include <asm/sizes.h>
>  
> diff --git a/drivers/pcmcia/pxa2xx_cm_x2xx.c b/drivers/pcmcia/pxa2xx_cm_x2xx.c
> index 6e7dcfd..61097ba 100644
> --- a/drivers/pcmcia/pxa2xx_cm_x2xx.c
> +++ b/drivers/pcmcia/pxa2xx_cm_x2xx.c
> @@ -13,7 +13,7 @@
>  #include <linux/module.h>
>  
>  #include <asm/mach-types.h>
> -#include <mach/hardware.h>
> +#include <mach-pxa/hardware.h>
>  
>  int cmx255_pcmcia_init(void);
>  int cmx270_pcmcia_init(void);
> diff --git a/drivers/pcmcia/sa1111_jornada720.c b/drivers/pcmcia/sa1111_jornada720.c
> index 69428d1..86fc717 100644
> --- a/drivers/pcmcia/sa1111_jornada720.c
> +++ b/drivers/pcmcia/sa1111_jornada720.c
> @@ -10,7 +10,7 @@
>  #include <linux/errno.h>
>  #include <linux/init.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-sa1100/hardware.h>
>  #include <asm/hardware/sa1111.h>
>  #include <asm/mach-types.h>
>  
> diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c
> index 6eecd7c..2d689b2 100644
> --- a/drivers/pcmcia/sa11xx_base.c
> +++ b/drivers/pcmcia/sa11xx_base.c
> @@ -39,7 +39,7 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-sa1100/hardware.h>
>  #include <asm/irq.h>
>  
>  #include "soc_common.h"
> diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
> index 44efc6e..af502d1 100644
> --- a/drivers/power/avs/smartreflex.c
> +++ b/drivers/power/avs/smartreflex.c
> @@ -26,6 +26,7 @@
>  #include <linux/slab.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/power/smartreflex.h>
> +#include <plat-omap/cpu.h>
>  
>  #define SMARTREFLEX_NAME_LEN   16
>  #define NVALUE_NAME_LEN                40
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index 2a0b353..68ff175 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -16,7 +16,7 @@
>  #include <linux/clk.h>
>  #include <linux/io.h>
>  #include <linux/pwm.h>
> -#include <mach/hardware.h>
> +#include <mach-imx/hardware.h>
>  
>  
>  /* i.MX1 and i.MX21 share the same PWM function block: */
> diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
> index e3e50d6..eb4d40e 100644
> --- a/drivers/rtc/rtc-mxc.c
> +++ b/drivers/rtc/rtc-mxc.c
> @@ -17,7 +17,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/clk.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-imx/hardware.h>
>  
>  #define RTC_INPUT_CLK_32768HZ  (0x00 << 5)
>  #define RTC_INPUT_CLK_32000HZ  (0x01 << 5)
> diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
> index 0075c8f..679ca79 100644
> --- a/drivers/rtc/rtc-pxa.c
> +++ b/drivers/rtc/rtc-pxa.c
> @@ -28,7 +28,7 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-pxa/hardware.h>
>  
>  #define TIMER_FREQ             CLOCK_TICK_RATE
>  #define RTC_DEF_DIVIDER                (32768 - 1)
> diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
> index 739ef556..9f7ff1d 100644
> --- a/drivers/rtc/rtc-stmp3xxx.c
> +++ b/drivers/rtc/rtc-stmp3xxx.c
> @@ -27,7 +27,7 @@
>  #include <linux/slab.h>
>  #include <linux/of_device.h>
>  
> -#include <mach/common.h>
> +#include <mach-mxs/common.h>
>  
>  #define STMP3XXX_RTC_CTRL                      0x0
>  #define STMP3XXX_RTC_CTRL_SET                  0x4
> diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
> index 22171b2..6395330 100644
> --- a/drivers/scsi/arm/acornscsi-io.S
> +++ b/drivers/scsi/arm/acornscsi-io.S
> @@ -8,7 +8,7 @@
>  #include <linux/linkage.h>
>  
>  #include <asm/assembler.h>
> -#include <mach/hardware.h>
> +#include <mach-rpc/hardware.h>
>  
>  #if defined(__APCS_32__)
>  #define LOADREGS(t,r,l...)     ldm##t  r, l
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index e834ff8..819ddf0 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -39,7 +39,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pinctrl/consumer.h>
>  
> -#include <mach/spi.h>
> +#include <mach-imx/spi.h>
>  
>  #define DRIVER_NAME "spi_imx"
>  
> diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
> index 177b6cf..dc2ad86 100644
> --- a/drivers/spi/spi-omap-uwire.c
> +++ b/drivers/spi/spi-omap-uwire.c
> @@ -48,7 +48,7 @@
>  #include <linux/module.h>
>  
>  #include <asm/irq.h>
> -#include <mach/hardware.h>
> +#include <mach-omap1/hardware.h>
>  #include <asm/io.h>
>  #include <asm/mach-types.h>
>  
> diff --git a/drivers/spi/spi-s3c24xx-fiq.S b/drivers/spi/spi-s3c24xx-fiq.S
> index 9718a11..44941ce 100644
> --- a/drivers/spi/spi-s3c24xx-fiq.S
> +++ b/drivers/spi/spi-s3c24xx-fiq.S
> @@ -13,8 +13,8 @@
>  #include <linux/linkage.h>
>  #include <asm/assembler.h>
>  
> -#include <mach/map.h>
> -#include <mach/regs-irq.h>
> +#include <mach-s3c24xx/map.h>
> +#include <mach-s3c24xx/regs-irq.h>
>  #include <plat-samsung/regs-spi.h>
>  
>  #include "spi-s3c24xx-fiq.h"
> diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
> index ef52c1c..77b2810 100644
> --- a/drivers/spi/spi-tegra.c
> +++ b/drivers/spi/spi-tegra.c
> @@ -32,7 +32,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/dmaengine.h>
>  
> -#include <mach/dma.h>
> +#include <mach-tegra/dma.h>
>  
>  #define SLINK_COMMAND          0x000
>  #define   SLINK_BIT_LENGTH(x)          (((x) & 0x1f) << 0)
> diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
> index a272e48..1e4f493 100644
> --- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
> +++ b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
> @@ -5,8 +5,8 @@
>  #include <linux/i2c.h>
>  #include <linux/gpio.h>
>  #include <linux/interrupt.h>
> -#include <mach/gpio.h>
> -#include <mach/irqs.h>
> +#include <mach-ux500/gpio.h>
> +#include <mach-ux500/irqs.h>
>  #include "synaptics_i2c_rmi4.h"
>  
>  /*
> diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
> index a44345a..8104b07 100644
> --- a/drivers/tty/serial/21285.c
> +++ b/drivers/tty/serial/21285.c
> @@ -18,7 +18,7 @@
>  #include <asm/mach-types.h>
>  #include <asm/system_info.h>
>  #include <asm/hardware/dec21285.h>
> -#include <mach/hardware.h>
> +#include <mach-footbridge/hardware.h>
>  
>  #define BAUD_BASE              (mem_fclk_21285/64)
>  
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index 3d7e1ee..ff99a33 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -44,11 +44,13 @@
>  #include <asm/ioctls.h>
>  
>  #include <asm/mach/serial_at91.h>
> -#include <mach/board.h>
>  
>  #ifdef CONFIG_ARM
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
>  #include <asm/gpio.h>
> +#else
> +#include <mach/board.h>
>  #endif
>  
>  #define PDC_BUFFER_SIZE                512
> diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
> index d0f719f..e4dc87b 100644
> --- a/drivers/tty/serial/clps711x.c
> +++ b/drivers/tty/serial/clps711x.c
> @@ -38,7 +38,7 @@
>  #include <linux/serial.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-clps711x/hardware.h>
>  #include <asm/irq.h>
>  
>  #define UART_NR                2
> diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
> index fca13dc..949c9e6 100644
> --- a/drivers/tty/serial/msm_serial_hs.c
> +++ b/drivers/tty/serial/msm_serial_hs.c
> @@ -51,8 +51,8 @@
>  #include <linux/atomic.h>
>  #include <asm/irq.h>
>  
> -#include <mach/hardware.h>
> -#include <mach/dma.h>
> +#include <mach-msm/hardware.h>
> +#include <mach-msm/dma.h>
>  #include <linux/platform_data/msm_serial_hs.h>
>  
>  /* HSUART Registers */
> diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
> index 2ca5959..d5c47f6 100644
> --- a/drivers/tty/serial/sa1100.c
> +++ b/drivers/tty/serial/sa1100.c
> @@ -37,8 +37,8 @@
>  #include <linux/io.h>
>  
>  #include <asm/irq.h>
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> +#include <mach-sa1100/hardware.h>
> +#include <mach-sa1100/irqs.h>
>  #include <asm/mach/serial_sa1100.h>
>  
>  /* We've been assigned a range on the "Low-density serial ports" major */
> diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
> index 7c13639..f5c672c 100644
> --- a/drivers/tty/serial/serial_ks8695.c
> +++ b/drivers/tty/serial/serial_ks8695.c
> @@ -25,8 +25,8 @@
>  #include <asm/irq.h>
>  #include <asm/mach/irq.h>
>  
> -#include <mach/regs-uart.h>
> -#include <mach/regs-irq.h>
> +#include <mach-ks8695/regs-uart.h>
> +#include <mach-ks8695/regs-irq.h>
>  
>  #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
>  #define SUPPORT_SYSRQ
> diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
> index 33a7a27..4bafe92 100644
> --- a/drivers/uio/uio_pruss.c
> +++ b/drivers/uio/uio_pruss.c
> @@ -25,7 +25,7 @@
>  #include <linux/clk.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/slab.h>
> -#include <mach/sram.h>
> +#include <mach-davinci/sram.h>
>  
>  #define DRV_NAME "pruss_uio"
>  #define DRV_VERSION "1.0"
> diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
> index 1b0f086..fce80b3 100644
> --- a/drivers/usb/gadget/fsl_mxc_udc.c
> +++ b/drivers/usb/gadget/fsl_mxc_udc.c
> @@ -18,7 +18,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-imx/hardware.h>
>  
>  static struct clk *mxc_ahb_clk;
>  static struct clk *mxc_per_clk;
> diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
> index dc53348..476ac2b 100644
> --- a/drivers/usb/gadget/imx_udc.c
> +++ b/drivers/usb/gadget/imx_udc.c
> @@ -35,8 +35,8 @@
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
>  
> -#include <mach/usb.h>
> -#include <mach/hardware.h>
> +#include <mach-imx/usb.h>
> +#include <mach-imx/hardware.h>
>  
>  #include "imx_udc.h"
>  
> diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
> index 644b430..d4ef1fe 100644
> --- a/drivers/usb/gadget/pxa27x_udc.c
> +++ b/drivers/usb/gadget/pxa27x_udc.c
> @@ -26,12 +26,12 @@
>  #include <linux/prefetch.h>
>  
>  #include <asm/byteorder.h>
> -#include <mach/hardware.h>
> +#include <mach-pxa/hardware.h>
>  
>  #include <linux/usb.h>
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
> -#include <mach/udc.h>
> +#include <mach-pxa/udc.h>
>  
>  #include "pxa27x_udc.h"
>  
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index a665b3e..5add6ce 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -17,11 +17,11 @@
>  #include <linux/of_platform.h>
>  #include <linux/of_gpio.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-at91/hardware.h>
>  #include <asm/gpio.h>
>  
> -#include <mach/board.h>
> -#include <mach/cpu.h>
> +#include <mach-at91/board.h>
> +#include <mach-at91/cpu.h>
>  
>  #ifndef CONFIG_ARCH_AT91
>  #error "CONFIG_ARCH_AT91 must be defined."
> diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
> index 2dce0df..561f56a 100644
> --- a/drivers/usb/host/ohci-exynos.c
> +++ b/drivers/usb/host/ohci-exynos.c
> @@ -14,7 +14,7 @@
>  #include <linux/clk.h>
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
> -#include <mach/ohci.h>
> +#include <mach-exynos/ohci.h>
>  #include <plat-samsung/usb-phy.h>
>  
>  struct exynos_ohci_hcd {
> diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
> index 472c8b4..2e8cfb8 100644
> --- a/drivers/usb/musb/davinci.c
> +++ b/drivers/usb/musb/davinci.c
> @@ -34,8 +34,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/dma-mapping.h>
>  
> -#include <mach/cputype.h>
> -#include <mach/hardware.h>
> +#include <mach-davinci/cputype.h>
> +#include <mach-davinci/hardware.h>
>  
>  #include <asm/mach-types.h>
>  
> diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
> index d05c7fb..7c92d86 100644
> --- a/drivers/usb/musb/ux500_dma.c
> +++ b/drivers/usb/musb/ux500_dma.c
> @@ -30,7 +30,7 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/dmaengine.h>
>  #include <linux/pfn.h>
> -#include <mach/usb.h>
> +#include <mach-ux500/usb.h>
>  #include "musb_core.h"
>  
>  struct ux500_dma_channel {
> diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
> index 9f5fc90..e41e6c5 100644
> --- a/drivers/usb/otg/msm_otg.c
> +++ b/drivers/usb/otg/msm_otg.c
> @@ -40,7 +40,7 @@
>  #include <linux/usb/msm_hsusb_hw.h>
>  #include <linux/regulator/consumer.h>
>  
> -#include <mach/clk.h>
> +#include <mach-msm/clk.h>
>  
>  #define MSM_USB_BASE   (motg->regs)
>  #define DRIVER_NAME    "msm_otg"
> diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
> index 1e39ae3..556b623 100644
> --- a/drivers/video/backlight/omap1_bl.c
> +++ b/drivers/video/backlight/omap1_bl.c
> @@ -28,7 +28,7 @@
>  #include <linux/backlight.h>
>  #include <linux/slab.h>
>  
> -#include <mach/hardware.h>
> +#include <mach-omap1/hardware.h>
>  #include <plat-omap/board.h>
>  #include <plat-omap/mux.h>
>  
> diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
> index 345d962..b58f5c5 100644
> --- a/drivers/video/ep93xx-fb.c
> +++ b/drivers/video/ep93xx-fb.c
> @@ -24,7 +24,7 @@
>  #include <linux/clk.h>
>  #include <linux/fb.h>
>  
> -#include <mach/fb.h>
> +#include <mach-ep93xx/fb.h>
>  
>  /* Vertical Frame Timing Registers */
>  #define EP93XXFB_VLINES_TOTAL                  0x0000  /* SW locked */
> diff --git a/drivers/video/nuc900fb.h b/drivers/video/nuc900fb.h
> index bc7c930..6f7f59a 100644
> --- a/drivers/video/nuc900fb.h
> +++ b/drivers/video/nuc900fb.h
> @@ -15,8 +15,8 @@
>  #ifndef __NUC900FB_H
>  #define __NUC900FB_H
>  
> -#include <mach/map.h>
> -#include <mach/fb.h>
> +#include <mach-w90x900/map.h>
> +#include <mach-w90x900/fb.h>
>  
>  enum nuc900_lcddrv_type {
>         LCDDRV_NUC910,
> diff --git a/drivers/video/pnx4008/dum.h b/drivers/video/pnx4008/dum.h
> index 1234d43..ddae1c2 100644
> --- a/drivers/video/pnx4008/dum.h
> +++ b/drivers/video/pnx4008/dum.h
> @@ -12,7 +12,7 @@
>  #ifndef __PNX008_DUM_H__
>  #define __PNX008_DUM_H__
>  
> -#include <mach/platform.h>
> +#include <mach-pnx4008/platform.h>
>  
>  #define PNX4008_DUMCONF_VA_BASE                IO_ADDRESS(PNX4008_DUMCONF_BASE)
>  #define PNX4008_DUM_MAIN_VA_BASE       IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
> diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
> index 4b0fcf3..2d9cc12 100644
> --- a/drivers/w1/masters/omap_hdq.c
> +++ b/drivers/w1/masters/omap_hdq.c
> @@ -19,7 +19,7 @@
>  #include <linux/pm_runtime.h>
>  
>  #include <asm/irq.h>
> -#include <mach/hardware.h>
> +#include <mach-omap2/hardware.h>
>  
>  #include "../w1.h"
>  #include "../w1_int.h"
> diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
> index bcfab2b..f745c9b 100644
> --- a/drivers/watchdog/imx2_wdt.c
> +++ b/drivers/watchdog/imx2_wdt.c
> @@ -33,7 +33,7 @@
>  #include <linux/uaccess.h>
>  #include <linux/timer.h>
>  #include <linux/jiffies.h>
> -#include <mach/hardware.h>
> +#include <mach-imx/hardware.h>
>  
>  #define DRIVER_NAME "imx2-wdt"
>  
> diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
> index 5580b4f..913d480 100644
> --- a/drivers/watchdog/ixp4xx_wdt.c
> +++ b/drivers/watchdog/ixp4xx_wdt.c
> @@ -25,7 +25,7 @@
>  #include <linux/init.h>
>  #include <linux/bitops.h>
>  #include <linux/uaccess.h>
> -#include <mach/hardware.h>
> +#include <mach-ixp4xx/hardware.h>
>  
>  static bool nowayout = WATCHDOG_NOWAYOUT;
>  static int heartbeat = 60;     /* (secs) Default is 1 minute */
> diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
> index 59e75d9..19c1dc1 100644
> --- a/drivers/watchdog/ks8695_wdt.c
> +++ b/drivers/watchdog/ks8695_wdt.c
> @@ -23,8 +23,8 @@
>  #include <linux/watchdog.h>
>  #include <linux/io.h>
>  #include <linux/uaccess.h>
> -#include <mach/hardware.h>
> -#include <mach/regs-timer.h>
> +#include <mach-ks8695/hardware.h>
> +#include <mach-ks8695/regs-timer.h>
>  
>  #define WDT_DEFAULT_TIME       5       /* seconds */
>  #define WDT_MAX_TIME           171     /* seconds */
> diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
> index 5eec740..1e1c743 100644
> --- a/drivers/watchdog/wdt285.c
> +++ b/drivers/watchdog/wdt285.c
> @@ -31,7 +31,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/uaccess.h>
>  #include <linux/irq.h>
> -#include <mach/hardware.h>
> +#include <mach-footbridge/hardware.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/system_info.h>
> -- 
> 
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
> 


From swarren at wwwdotorg.org  Wed Aug 22 11:34:48 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 09:34:48 -0600
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
Message-ID: <5034FC18.2090400@wwwdotorg.org>

On 08/15/2012 08:38 AM, Linus Walleij wrote:
> (Hm maybe I should've read this patch first, well whatever.)
> 
> On Fri, Aug 10, 2012 at 3:02 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj at jcrosoft.com> wrote:
> 
>> This is also include the gpio controller as the IP share both.
>> Each soc will have to describe the SoC limitation and pin configuration via
>> DT.

>> +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt

>> +Required properties for iomux controller:
>> +- compatible: "atmel,at91rm9200-pinctrl"
>> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
>> +  configured in this periph mode. All the periph and bank need to be describe.
> 
> Can you please be more elaborate on this mux-mask, like what each bit
> means and why the bits are arranged like that and what it means on the
> AT91 platform.... I was first reading the .dts and was like ?woot? so
> I go to the bindings doc and I read this and I'm still like ?woot?..

Yes, I'm a little confused what this is, and wouldn't have a clue how to
fill it in.

>> +static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
>> +                       struct device_node *np,
>> +                       struct pinctrl_map **map, unsigned *num_maps)
> 
> DT parse code, looks nice but would request Stephen to have a look
> at it.

I think it looks reasonable; I don't see any obvious issues at a quick
glance.



From santosh.shilimkar at ti.com  Wed Aug 22 11:36:38 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 22 Aug 2012 21:06:38 +0530
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <1345648390-4234-3-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-3-git-send-email-arnd@arndb.de>
Message-ID: <CAMQu2gw0x6saWrK-M3teu49tJDGvS8RhGrVSh6JTs5DEy+22pA@mail.gmail.com>

On Wed, Aug 22, 2012 at 8:43 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> The new omap4 cpuidle implementation currently requires
> ARCH_NEEDS_CPU_IDLE_COUPLED, which only works on SMP.
>
> This patch makes it possible to build a non-SMP kernel
> for that platform. This is not normally desired for
> end-users but can be useful for testing.
>
> Without this patch, building rand-0y2jSKT results in:
>
> drivers/cpuidle/coupled.c: In function 'cpuidle_coupled_poke':
> drivers/cpuidle/coupled.c:317:3: error: implicit declaration of function '__smp_call_function_single' [-Werror=implicit-function-declaration]
>
> It's not clear if this patch is the best solution for
> the problem at hand. I have made sure that we can now
> build the kernel in all configurations, but that does
> not mean it will actually work on an OMAP44xx.
>
Am not sure either about the subject patch.

> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/Kconfig       |    2 +-
>  arch/arm/mach-omap2/cpuidle44xx.c |    3 ++-
>  include/linux/cpuidle.h           |    4 ++++
>  3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index dd2db02..66a8be3 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -62,7 +62,7 @@ config ARCH_OMAP4
>         select PM_OPP if PM
>         select USB_ARCH_HAS_EHCI if USB_SUPPORT
>         select ARM_CPU_SUSPEND if PM
> -       select ARCH_NEEDS_CPU_IDLE_COUPLED
> +       select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
>
>  config SOC_OMAP5
>         bool "TI OMAP5"
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index ee05e19..288bee6 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -238,8 +238,9 @@ int __init omap4_idle_init(void)
>         for_each_cpu(cpu_id, cpu_online_mask) {
>                 dev = &per_cpu(omap4_idle_dev, cpu_id);
>                 dev->cpu = cpu_id;
> +#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
>                 dev->coupled_cpus = *cpu_online_mask;
> -
> +#endif

Was just thinking whether we should just take care of it at
core cpuidle level itself. Will below be enough to kill the build
error what you mentioned in the change log ?

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 2c9bf26..df34534 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -314,7 +314,9 @@ static void cpuidle_coupled_poke(int cpu)
        struct call_single_data *csd = &per_cpu(cpuidle_coupled_poke_cb, cpu);

        if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask))
+#ifdef CONFIG_SMP
                __smp_call_function_single(cpu, csd, 0);
+#endif
 }

 /**

Regards
Santosh


From snijsure at grid-net.com  Wed Aug 22 11:37:22 2012
From: snijsure at grid-net.com (Subodh Nijsure)
Date: Wed, 22 Aug 2012 08:37:22 -0700
Subject: Can one  set GPIO direction in pinmux definition?
Message-ID: <5034FCB2.5040709@grid-net.com>


For a MX28 based hardware I am working with I need to use AUART4

I need to configure this AUART4 as uart only when necessary and at all 
other times pins associated with AUART4 need to be configured as inputs.

I am using following DT definitions to setup AUART4 mux  but can't 
figure out how to setup pin direction via DT, can it be done or I need 
to do it in C code?

         apb at 80000000 {
                 apbh at 80000000 {
                                 auart4_pins_a: auart4 at 0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x3142 /* 
MX28_PAD_SAIF0_MCLK__AUART4_CTS */
                                                 0x3152 /* 
MX28_PAD_SAIF0_LRCLK__AUART4_RTS */
                                                 0x3162 /* 
MX28_PAD_SAIF0_BITCLK__AUART4_RX */
                                                 0x3172 /* 
MX28_PAD_SAIF0_SDATA0__AUART4_TX */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
                                 auart4_highz_pins: auart4-gpio at 0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x3143 /* 
MX28_PAD_SAIF0_MCLK__GPIO_3_20 */
                                                 0x3153 /* 
MX28_PAD_SAIF0_LRCLK__GPIO_3_21 */
                                                 0x3163 /* 
MX28_PAD_SAIF0_BITCLK__GPIO_3_22 */
                                                 0x3173 /* 
MX28_PAD_SAIF0_SDATA0__GPIO_3_23 */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
                  };
           };

                 apbx at 80040000 {
                         auart4: serial at 80072000 {
                                 pinctrl-names = "default", "auart";
                                 pinctrl-0 = <&auart4_highz_pins>;
                                 pinctrl-1 = <&auart4_pins_a>;
                                 status = "okay";
                         };
                };



From arnd at arndb.de  Wed Aug 22 11:37:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 15:37:53 +0000
Subject: [PATCH 2/4] [RFC] ARM: mass move of mach-*/plat-* header files
In-Reply-To: <alpine.LFD.2.02.1208221126180.1754@xanadu.home>
References: <201208221253.07278.arnd@arndb.de>
 <201208221256.35657.arnd@arndb.de>
 <alpine.LFD.2.02.1208221126180.1754@xanadu.home>
Message-ID: <201208221537.53904.arnd@arndb.de>

On Wednesday 22 August 2012, Nicolas Pitre wrote:
> Ideally, files such as ...
> 
> > rename from arch/arm/mach-at91/include/mach/at91_pio.h
> > rename to arch/arm/mach-at91/include/mach-at91/at91_pio.h
> 
> should move next to the A91 GPIO driver file.  but that require manual 
> operations which can be done later.

Right. There are cases where we have to do this eventually because the
files are duplicated, e.g. at91/avr32, pxa/mmp, s3c/s5p/exynos, or
sa1100/pxa.

For the majority of cases where it's desirable to move the header file
closer to the driver, it's not actually a prerequisite to do this
in order to get a complete multiplatform setup.

	Arnd


From nicolas.pitre at linaro.org  Wed Aug 22 11:38:46 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 11:38:46 -0400 (EDT)
Subject: [PATCH 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <201208221519.12056.arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-5-git-send-email-arnd@arndb.de>
 <alpine.LFD.2.02.1208221040250.1754@xanadu.home>
 <201208221519.12056.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221136180.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> On Wednesday 22 August 2012, Nicolas Pitre wrote:
> > On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > 
> > > The mls instruction is not available in ARMv6K or below, so we
> > > should make the test conditional on at least ARMv7. ldrex/strex
> > > are available in ARMv6K or ARMv7, which we can test by checking
> > > the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.
> > 
> > The ldrex/strex instructions are available on ARMv6.  It's only the d 
> > variants (strexd/ldrexd) which are only available from ARMv6k.
> 
> Ok. How is the version below then? I haven't tested this one yet.

In fact, I think the b variants are ARMv6k+ as well.  Only the plain 
(non b non d) variants are available on ARMv6.


> 
> 	Arnd
> 
> 8<---
> From d878ab212cf0ac1957be83ad80dc734ace2b476c Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Thu, 16 Aug 2012 07:49:31 +0000
> Subject: [PATCH] ARM: kprobes: make more tests conditional
> 
> The mls instruction is not available in ARMv6K or below, so we
> should make the test conditional on at least ARMv7. ldrexd/strexd
> are available in ARMv6K or ARMv7, which we can test by checking
> the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.
> 
> /tmp/ccuMTZ8D.s: Assembler messages:
> /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
> /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
> /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Jon Medhurst <tixy at yxit.co.uk>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
> Cc: Leif Lindholm <leif.lindholm at arm.com>
> ---
>  arch/arm/kernel/kprobes-test-arm.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
> index 38c1a3b..fc9f6e0 100644
> --- a/arch/arm/kernel/kprobes-test-arm.c
> +++ b/arch/arm/kernel/kprobes-test-arm.c
> @@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> +#endif
>  	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
> @@ -456,8 +458,10 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
>  #if __LINUX_ARM_ARCH__ >= 6
>  	TEST_UNSUPPORTED("ldrex	r2, [sp]")
> +#ifdef CONFIG_CPU_32v6K
>  	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
>  	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
> +#endif
>  	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
>  	TEST_UNSUPPORTED("ldrexb	r2, [sp]")
>  	TEST_UNSUPPORTED("strexh	r0, r2, [sp]")
> -- 
> 1.7.10
> 


From broonie at opensource.wolfsonmicro.com  Wed Aug 22 11:48:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 16:48:12 +0100
Subject: [PATCH 5/8] mfd: Provide the PRCMU with its own IRQ domain
In-Reply-To: <20120822115524.GA18545@gmail.com>
References: <20120820175155.GH26991@opensource.wolfsonmicro.com>
 <20120821085618.GA26899@gmail.com>
 <20120821095026.GU26991@opensource.wolfsonmicro.com>
 <20120821105413.GD26899@gmail.com>
 <20120821110329.GA7995@opensource.wolfsonmicro.com>
 <20120821120243.GF26899@gmail.com>
 <20120821165207.GX7995@opensource.wolfsonmicro.com>
 <20120822081746.GA4089@gmail.com>
 <20120822111913.GG7995@opensource.wolfsonmicro.com>
 <20120822115524.GA18545@gmail.com>
Message-ID: <20120822154812.GK7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 12:55:25PM +0100, Lee Jones wrote:

> > I *have* asked you to communicate more clearly about what you're doing
> > but that doesn't mean to stop sending code, it means to have clearer
> > words around what you're sending. 

> That's not how I interpreted your words:

> "What you can do here is to commmunicate about what you're doing more.
> Don't just think about the code, think about the communication
> surrounding the code - this is the core of the issue."

Just to be clear I'd include things like commit messages, cover letters
and so on in the general area of communication.

> I think it's great that you like the idea and want to extend that
> functionality to other MFDs which perhaps don't support DT, or the
> ones that do but don't want to provide compatible strings or device
> nodes for all the MFD's child devices. But that is all we're doing
> here. There was no breakage. It served a purpose and it worked well.
> So well in fact that you've now provided the intended functionality
> to other devices.

I'm looking at this from the point of view of adding the compatible
strings and then finding that the core starts remapping things in the
case where you're probing from DT - and this behaviour will vary
depending on the device tree that the user is using so the driver can't
even make a decision based on if device tree is being used by the
system.

> You only noticed it 2 days ago and I had a patch ready to go yesterday.
> I'm confused because I don't understand why would you even complain about
> it if you intended to work on it yourself? Surely, "Ah, I see an issue with
> xyz, patch to follow." Would have been more appropriate, instead of 
> complaining about it, then I go and waste my time trying to fix something
> you intend on fixing yourself.

I didn't originally intend to do anything, if I had done I'd just have
sent a patch as you say.  Originally I'd just noticed it as being an
awkwardly designed interface at the wrong abstraction layer, it was only
later on that I realised how it could blow up.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 11:58:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 16:58:08 +0100
Subject: [PATCH 3/5] ASoC: Davinci: pcm: Add device tree bindings
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EA67DA1@DBDE01.ent.ti.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>
 <20120817223122.GA21445@opensource.wolfsonmicro.com>
 <1BAFE6F6C881BF42822005164F1491C33EA67DA1@DBDE01.ent.ti.com>
Message-ID: <20120822155808.GP7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 01:50:09PM +0000, Hebbar, Gururaja wrote:

> From your for-3.7 branch, I could only find such implementation in Tegra
> Platform. 
> Most Freescale platforms implements this through a device/driver method.
> Exception being sound/soc/mxs/mxs-pcm.c

> So should I follow tegra implementation?

Tegra and mxs should be good examples, yes.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 11:59:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 16:59:53 +0100
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <1345619928-15446-5-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
Message-ID: <20120822155953.GQ7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 03:18:45PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Using standard imx syscon API to access anatop register.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

With the conversion to regmap it'd also be good to convert the driver to
use the regmap helper functions for enable and voltage operations if
possible.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 12:02:41 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 17:02:41 +0100
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <1345619928-15446-2-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
Message-ID: <20120822160241.GR7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:

> From: Dong Aisheng <dong.aisheng at linaro.org>

> Add regmap based imx syscon driver.

Nice to see more regmap-mmio usage!

Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

from a regmap point of view.

> +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
> +{
> +	struct device *dev;
> +	struct imx_syscon *syscon;
> +	int ret = 0;
> +
> +	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
> +				 imx_syscon_match);
> +	if (!dev)
> +		return -EPROBE_DEFER;
> +
> +	syscon = dev_get_drvdata(dev);
> +	ret = regmap_write(syscon->regmap, reg, val);

It'd be good to provide a way of retrieving the regmap so that drivers
for subsystems with generic regmap code could use the framework features
(regulator is one example that I just mentioned in my other mail).
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From mporter at ti.com  Wed Aug 22 12:04:17 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 12:04:17 -0400
Subject: [PATCH v2 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345607122.1895.44.camel@vkoul-udesk3>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-4-git-send-email-mporter@ti.com>
 <1345607122.1895.44.camel@vkoul-udesk3>
Message-ID: <20120822160417.GA27758@beef>

On Wed, Aug 22, 2012 at 09:15:22AM +0530, Vinod Koul wrote:
> On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> > Removes use of the DaVinci EDMA private DMA API and replaces
> > it with use of the DMA engine API.
> > 
> > Signed-off-by: Matt Porter <mporter at ti.com>
> > ---
> 
> > +		struct dma_slave_config dma_rx_conf = {
> > +			.direction = DMA_DEV_TO_MEM,
> > +			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
> > +			.src_addr_width = data_type,
> > +			.src_maxburst = 1,
> what does 1 mean in this context? We define as number of units that
> needs to be transfered, so are you sure that you want only one unit to
> be dma'ed in a single burst. that seems like killing your dmac,
> shouldn't you be using larger bursts for a better dma performance?

This device can't handle bursts, it's a simple shift register based
SPI master that always asserts a DMA req for each SPI word transfer.

The other important thing to note is that the EDMA driver itself
is able to handle a maxburst of 1 as a special case. That is, the
EDMA has some limitations in transfer sizes it can handle if you
need burst support. So, on the EDMA end of things you'll see that
if maxburst if 1, it's able to handle setting up an A-synchronized
transfer to handle any sized segment coming in with a single transfer
slot. However, is maxburst is >1, EDMA requires up to set up an
AB-synchronized transfer. This type of transfer limits allows for
a DMA req per burst, but the maximum segment size we can handle is
SZ_64K-1. An annoying hardware design limitation, indeed.

It works out ok because in this spi driver conversion we always
map a SPI transfer into a single segment (similar to the
spi-omap2-mcspi conversion). Since the SPI master can't handle
bursts, the EDMA driver is able to handle any sized transfer
without any performance penalty. If this SPI master could
handle bursts, we'd be in trouble because we quickly run
into our AB-synced max segment limitation.

In the mmc driver, we have a device that can handle bursts for
performance reasons. It sets maxburst appropriately and the
EDMA driver does the required AB-synced transfer at the h/w
level. However, this is subject to our limitation of SZ_64K-1
per segment. Luckily we aren't the first to need to limit the
segment size coming into an mmc host driver. The mmc
subsystem already handles this case and the existing driver
using the private EDMA API was already advertising a maximum
number of segments and segments size to the mmc subsystem.
Ideally, we should have a dmaengine interface that allows
for querying of these types of limitations. Right now, the
mmc driver implicitly knows that EDMA needs this restriction
but it's something that should be queried before calling
prep_slave().

-Matt


From mporter at ti.com  Wed Aug 22 12:21:02 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 12:21:02 -0400
Subject: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345606766.1895.40.camel@vkoul-udesk3>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-2-git-send-email-mporter@ti.com>
 <1345606766.1895.40.camel@vkoul-udesk3>
Message-ID: <20120822162101.GB27758@beef>

On Wed, Aug 22, 2012 at 09:09:26AM +0530, Vinod Koul wrote:
> On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
> > Add a DMA engine driver for the TI EDMA controller. This driver
> > is implemented as a wrapper around the existing DaVinci private
> > DMA implementation. This approach allows for incremental conversion
> > of each peripheral driver to the DMA engine API. The EDMA driver
> > supports slave transfers but does not yet support cyclic transfers.
> > 
> > Signed-off-by: Matt Porter <mporter at ti.com>
> mostly looks decent and in shape.

ok, thanks for the review. I'll be addressing these comments in v3.
Should happen before I go on holiday for the next week.

> > ---
> > +config TI_EDMA
> > +	tristate "TI EDMA support"
> > +	depends on ARCH_DAVINCI
> > +	select DMA_ENGINE
> > +	select DMA_VIRTUAL_CHANNELS
> > +	default y
> default should be n for new drivers

ok
 
> > +	help
> > +	  Enable support for the TI EDMA controller. This DMA
> > +	  engine is found on TI DaVinci and AM33xx parts.
> > +
> >  config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
> >  	bool
> >  
> > +/* Max of 16 segments per channel to conserve PaRAM slots */
> > +#define MAX_NR_SG		16
> > +#define EDMA_MAX_SLOTS		MAX_NR_SG
> > +#define EDMA_DESCRIPTORS	16
> > +
> > +struct edma_desc {
> > +	struct virt_dma_desc		vdesc;
> > +	struct list_head		node;
> > +
> dummy space?

will remove

> > +	int				absync;
> > +	int				pset_nr;
> > +	struct edmacc_param		pset[0];
> > +};
> > +
> > +struct edma_cc;
> > +
> > +struct edma_chan {
> > +	struct virt_dma_chan		vchan;
> > +	struct list_head		node;
> > +	struct edma_desc		*edesc;
> > +	struct edma_cc			*ecc;
> > +	int				ch_num;
> > +	bool				alloced;
> > +	int				slot[EDMA_MAX_SLOTS];
> > +
> > +	dma_addr_t			addr;
> > +	int				addr_width;
> > +	int				maxburst;
> > +};
> > +
> 
> > +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> > +static void edma_execute(struct edma_chan *echan)
> > +{
> > +	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
> > +	struct edma_desc *edesc;
> > +	int i;
> > +
> > +	if (!vdesc) {
> > +		echan->edesc = NULL;
> > +		return;
> > +	}
> > +
> > +	list_del(&vdesc->node);
> > +
> > +	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
> > +
> > +	/* Write descriptor PaRAM set(s) */
> > +	for (i = 0; i < edesc->pset_nr; i++) {
> > +		edma_write_slot(echan->slot[i], &edesc->pset[i]);
> > +		dev_dbg(echan->vchan.chan.device->dev,
> > +			"\n pset[%d]:\n"
> > +			"  chnum\t%d\n"
> > +			"  slot\t%d\n"
> > +			"  opt\t%08x\n"
> > +			"  src\t%08x\n"
> > +			"  dst\t%08x\n"
> > +			"  abcnt\t%08x\n"
> > +			"  ccnt\t%08x\n"
> > +			"  bidx\t%08x\n"
> > +			"  cidx\t%08x\n"
> > +			"  lkrld\t%08x\n",
> > +			i, echan->ch_num, echan->slot[i],
> > +			edesc->pset[i].opt,
> > +			edesc->pset[i].src,
> > +			edesc->pset[i].dst,
> > +			edesc->pset[i].a_b_cnt,
> > +			edesc->pset[i].ccnt,
> > +			edesc->pset[i].src_dst_bidx,
> > +			edesc->pset[i].src_dst_cidx,
> > +			edesc->pset[i].link_bcntrld);
> > +		/* Link to the previous slot if not the last set */
> > +		if (i != (edesc->pset_nr - 1))
> > +			edma_link(echan->slot[i], echan->slot[i+1]);
> > +		/* Final pset links to the dummy pset */
> > +		else
> > +			edma_link(echan->slot[i], echan->ecc->dummy_slot);
> > +	}
> > +
> > +	edma_start(echan->ch_num);
> > +}
> > +
> > +static int edma_terminate_all(struct edma_chan *echan)
> > +{
> > +	unsigned long flags;
> > +	LIST_HEAD(head);
> > +
> > +	spin_lock_irqsave(&echan->vchan.lock, flags);
> > +
> > +	/*
> > +	 * Stop DMA activity: we assume the callback will not be called
> > +	 * after edma_dma() returns (even if it does, it will see
> > +	 * echan->edesc is NULL and exit.)
> > +	 */
> > +	if (echan->edesc) {
> > +		echan->edesc = NULL;
> > +		edma_stop(echan->ch_num);
> > +	}
> > +
> > +	vchan_get_all_descriptors(&echan->vchan, &head);
> > +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +	vchan_dma_desc_free_list(&echan->vchan, &head);
> > +
> > +	return 0;
> > +}
> > +
> > +
> > +static int edma_slave_config(struct edma_chan *echan,
> > +	struct dma_slave_config *config)
> > +{
> > +	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> > +		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> > +		return -EINVAL;
> the indent needs help here

ok

> > +
> > +	if (config->direction == DMA_MEM_TO_DEV) {
> > +		if (config->dst_addr)
> > +			echan->addr = config->dst_addr;
> > +		if (config->dst_addr_width)
> > +			echan->addr_width = config->dst_addr_width;
> > +		if (config->dst_maxburst)
> > +			echan->maxburst = config->dst_maxburst;
> > +	} else if (config->direction == DMA_DEV_TO_MEM) {
> > +		if (config->src_addr)
> > +			echan->addr = config->src_addr;
> > +		if (config->src_addr_width)
> > +			echan->addr_width = config->src_addr_width;
> > +		if (config->src_maxburst)
> > +			echan->maxburst = config->src_maxburst;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> > +			unsigned long arg)
> > +{
> > +	int ret = 0;
> > +	struct dma_slave_config *config;
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +
> > +	switch (cmd) {
> > +	case DMA_TERMINATE_ALL:
> > +		edma_terminate_all(echan);
> > +		break;
> > +	case DMA_SLAVE_CONFIG:
> > +		config = (struct dma_slave_config *)arg;
> > +		ret = edma_slave_config(echan, config);
> > +		break;
> > +	default:
> > +		ret = -ENOSYS;
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static struct dma_async_tx_descriptor *edma_prep_slave_sg(
> > +	struct dma_chan *chan, struct scatterlist *sgl,
> > +	unsigned int sg_len, enum dma_transfer_direction direction,
> > +	unsigned long tx_flags, void *context)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	struct edma_desc *edesc;
> > +	struct scatterlist *sg;
> > +	int i;
> > +	int acnt, bcnt, ccnt, src, dst, cidx;
> > +	int src_bidx, dst_bidx, src_cidx, dst_cidx;
> > +
> > +	if (unlikely(!echan || !sgl || !sg_len))
> > +		return NULL;
> > +
> > +	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
> > +		dev_err(dev, "Undefined slave buswidth\n");
> > +		return NULL;
> > +	}
> > +
> > +	if (sg_len > MAX_NR_SG) {
> > +		dev_err(dev, "Exceeded max SG segments %d > %d\n",
> > +			sg_len, MAX_NR_SG);
> > +		return NULL;
> > +	}
> > +
> > +	edesc = kzalloc(sizeof(*edesc) + sg_len *
> > +		sizeof(edesc->pset[0]), GFP_ATOMIC);
> > +	if (!edesc) {
> > +		dev_dbg(dev, "Failed to allocate a descriptor\n");
> > +		return NULL;
> > +	}
> > +
> > +	edesc->pset_nr = sg_len;
> > +
> > +	for_each_sg(sgl, sg, sg_len, i) {
> > +		/* Allocate a PaRAM slot, if needed */
> > +		if (echan->slot[i] < 0) {
> > +			echan->slot[i] =
> > +				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
> > +						EDMA_SLOT_ANY);
> > +			if (echan->slot[i] < 0) {
> > +				dev_err(dev, "Failed to allocate slot\n");
> > +				return NULL;
> > +			}
> > +		}
> > +
> > +		acnt = echan->addr_width;
> > +
> > +		/*
> > +		 * If the maxburst is equal to the fifo width, use
> > +		 * A-synced transfers. This allows for large contiguous
> > +		 * buffer transfers using only one PaRAM set.
> > +		 */
> > +		if (echan->maxburst == 1) {
> > +			edesc->absync = false;
> > +			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
> > +			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
> > +			if (bcnt)
> > +				ccnt++;
> > +			else
> > +				bcnt = SZ_64K - 1;
> > +			cidx = acnt;
> > +		/*
> > +		 * If maxburst is greater than the fifo address_width,
> > +		 * use AB-synced transfers where A count is the fifo
> > +		 * address_width and B count is the maxburst. In this
> > +		 * case, we are limited to transfers of C count frames
> > +		 * of (address_width * maxburst) where C count is limited
> > +		 * to SZ_64K-1. This places an upper bound on the length
> > +		 * of an SG segment that can be handled.
> > +		 */
> > +		} else {
> > +			edesc->absync = true;
> > +			bcnt = echan->maxburst;
> > +			ccnt = sg_dma_len(sg) / (acnt * bcnt);
> > +			if (ccnt > (SZ_64K - 1)) {
> > +				dev_err(dev, "Exceeded max SG segment size\n");
> > +				return NULL;
> > +			}
> > +			cidx = acnt * bcnt;
> > +		}
> > +
> > +		if (direction == DMA_MEM_TO_DEV) {
> > +			src = sg_dma_address(sg);
> > +			dst = echan->addr;
> > +			src_bidx = acnt;
> > +			src_cidx = cidx;
> > +			dst_bidx = 0;
> > +			dst_cidx = 0;
> > +		} else {
> > +			src = echan->addr;
> > +			dst = sg_dma_address(sg);
> > +			src_bidx = 0;
> > +			src_cidx = 0;
> > +			dst_bidx = acnt;
> > +			dst_cidx = cidx;
> > +		}
> > +
> > +		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
> > +		/* Configure A or AB synchronized transfers */
> > +		if (edesc->absync)
> > +			edesc->pset[i].opt |= SYNCDIM;
> > +		/* If this is the last set, enable completion interrupt flag */
> > +		if (i == sg_len - 1)
> > +			edesc->pset[i].opt |= TCINTEN;
> > +
> > +		edesc->pset[i].src = src;
> > +		edesc->pset[i].dst = dst;
> > +
> > +		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
> > +		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
> > +
> > +		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
> > +		edesc->pset[i].ccnt = ccnt;
> > +		edesc->pset[i].link_bcntrld = 0xffffffff;
> > +
> > +	}
> > +
> > +	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
> > +}
> > +
> > +static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
> > +{
> > +	struct edma_chan *echan = data;
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	struct edma_desc *edesc;
> > +	unsigned long flags;
> > +
> > +	/* Stop the channel */
> > +	edma_stop(echan->ch_num);
> > +
> > +	switch (ch_status) {
> > +	case DMA_COMPLETE:
> > +		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
> > +
> > +		spin_lock_irqsave(&echan->vchan.lock, flags);
> > +
> > +		edesc = echan->edesc;
> > +		if (edesc) {
> > +			edma_execute(echan);
> > +			vchan_cookie_complete(&edesc->vdesc);
> > +		}
> > +
> > +		spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +
> > +		break;
> > +	case DMA_CC_ERROR:
> > +		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
> > +		break;
> > +	default:
> > +		break;
> > +	}
> > +}
> > +
> > +/* Alloc channel resources */
> > +static int edma_alloc_chan_resources(struct dma_chan *chan)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	int ret;
> > +	int a_ch_num;
> > +	LIST_HEAD(descs);
> > +
> > +	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
> > +					chan, EVENTQ_DEFAULT);
> > +
> > +	if (a_ch_num < 0) {
> > +		ret = -ENODEV;
> > +		goto err_no_chan;
> > +	}
> > +
> > +	if (a_ch_num != echan->ch_num) {
> > +		dev_err(dev, "failed to allocate requested channel %u:%u\n",
> > +			EDMA_CTLR(echan->ch_num),
> > +			EDMA_CHAN_SLOT(echan->ch_num));
> > +		ret = -ENODEV;
> > +		goto err_wrong_chan;
> > +	}
> > +
> > +	echan->alloced = true;
> > +	echan->slot[0] = echan->ch_num;
> > +
> > +	dev_info(dev, "allocated channel for %u:%u\n",
> > +		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
> > +
> > +	return 0;
> > +
> > +err_wrong_chan:
> > +	edma_free_channel(a_ch_num);
> > +err_no_chan:
> > +	return ret;
> > +}
> > +
> > +/* Free channel resources */
> > +static void edma_free_chan_resources(struct dma_chan *chan)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> perhaps, chan->dev->device
> > +	int i;
> > +
> > +	/* Terminate transfers */
> > +	edma_stop(echan->ch_num);
> > +
> > +	vchan_free_chan_resources(&echan->vchan);
> > +
> > +	/* Free EDMA PaRAM slots */
> > +	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
> > +		if (echan->slot[i] >= 0) {
> > +			edma_free_slot(echan->slot[i]);
> > +			echan->slot[i] = -1;
> > +		}
> > +	}
> > +
> > +	/* Free EDMA channel */
> > +	if (echan->alloced) {
> > +		edma_free_channel(echan->ch_num);
> > +		echan->alloced = false;
> > +	}
> > +
> > +	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
> > +}
> > +
> > +static void __init edma_chan_init(struct edma_cc *ecc,
> > +				  struct dma_device *dma,
> > +				  struct edma_chan *echans)
> > +{
> > +	int i, j;
> > +	int chcnt = 0;
> > +
> > +	for (i = 0; i < EDMA_CHANS; i++) {
> > +		struct edma_chan *echan = &echans[chcnt];
> > +		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
> > +		echan->ecc = ecc;
> > +		echan->vchan.desc_free = edma_desc_free;
> > +
> > +		vchan_init(&echan->vchan, dma);
> > +
> > +		INIT_LIST_HEAD(&echan->node);
> > +		for (j = 0; j < EDMA_MAX_SLOTS; j++)
> > +			echan->slot[j] = -1;
> > +
> > +		chcnt++;
> i see no reason why you cant remove "chcnt" and use "i".

ok. This is an artifact of how the driver started. I originally
had memcpy transfer support in the driver. The problem is that
the amount of platform data and logic required to tell the driver
which channels are available to be memcpy usable was making
things quite ugly. I opted to dump that out since I really only
care about slave support in the short-term. I'll add that back
in once the private EDMA API goes away.

In any case, I'll simplify this as noted.

> > +	}
> > +}
> > +
> > +static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
> > +			  struct device *dev)
> > +{
> > +	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
> > +		dma->device_prep_slave_sg = edma_prep_slave_sg;
> You have set DMA_SLAVE unconditionally in your probe, so this seems
> bogus.

ok. Same reason as above. I'll simplify this since I dropped
out memcpy handling.

> > +
> > +	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
> > +	dma->device_free_chan_resources = edma_free_chan_resources;
> > +	dma->device_issue_pending = edma_issue_pending;
> > +	dma->device_tx_status = edma_tx_status;
> > +	dma->device_control = edma_control;
> > +	dma->dev = dev;
> > +
> > +	INIT_LIST_HEAD(&dma->channels);
> > +}
> > +
> > +static int __devinit edma_probe(struct platform_device *pdev)
> > +{
> > +	struct edma_cc *ecc;
> > +	int ret;
> > +
> > +	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
> > +	if (!ecc) {
> > +		dev_err(&pdev->dev, "Can't allocate controller\n");
> > +		ret = -ENOMEM;
> > +		goto err_alloc_ecc;
> you can just return here, you are using devm_ friends here

ok

> > +	}
> > +
> > +	ecc->ctlr = pdev->id;
> > +	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
> > +	if (ecc->dummy_slot < 0) {
> > +		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
> > +		ret = -EIO;
> > +		goto err_alloc_slot;
> ditto, just return!

ok

> > +	}
> > +
> > +	dma_cap_zero(ecc->dma_slave.cap_mask);
> > +	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
> > +
> > +	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
> > +
> > +	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
> > +
> > +	ret = dma_async_device_register(&ecc->dma_slave);
> > +	if (ret)
> > +		goto err_reg1;
> > +
> > +	platform_set_drvdata(pdev, ecc);
> > +
> > +	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
> > +
> > +	return 0;
> > +
> > +err_reg1:
> > +	edma_free_slot(ecc->dummy_slot);
> > +err_alloc_slot:
> > +	devm_kfree(&pdev->dev, ecc);
> > +err_alloc_ecc:
> > +	return ret;
> > +}
> > +
> > +static int __devexit edma_remove(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct edma_cc *ecc = dev_get_drvdata(dev);
> > +
> > +	dma_async_device_unregister(&ecc->dma_slave);
> > +	edma_free_slot(ecc->dummy_slot);
> > +	devm_kfree(dev, ecc);
> no need to call this, it is *managed* resource

ok

> > +
> > +	return 0;
> > +}
> > +


From matthew.leach at arm.com  Wed Aug 22 12:25:22 2012
From: matthew.leach at arm.com (Matthew Leach)
Date: Wed, 22 Aug 2012 17:25:22 +0100
Subject: [PATCH v3] serial: pl011: honour serial aliases in device tree
Message-ID: <1345652722-22668-1-git-send-email-matthew.leach@arm.com>

If the order of UART nodes is changed in the device tree, then tty dev
devices are attached to different serial ports causing the console to
be directed to a different physical serial port. The "serial" aliases
in the device tree should prevent this.

This patch ensures that the UART driver creates tty devices that
honour these aliases if a device tree is present.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Matthew Leach <matthew.leach at arm.com>
---
v3: minor consistency correction
v2: use IS_ENABLED instead of ifdefs
 drivers/tty/serial/amba-pl011.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d3553b5..dc05dd1 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,8 @@
 #include <linux/scatterlist.h>
 #include <linux/delay.h>
 #include <linux/types.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/sizes.h>
 
@@ -1869,6 +1871,38 @@ static struct uart_driver amba_reg = {
 	.cons			= AMBA_CONSOLE,
 };
 
+static int pl011_probe_dt_alias(int index, struct device *dev)
+{
+	struct device_node *np;
+	static bool seen_dev_with_alias = false;
+	static bool seen_dev_without_alias = false;
+	int ret = index;
+
+	if (!IS_ENABLED(CONFIG_OF))
+		return ret;
+
+	np = dev->of_node;
+	if (!np)
+		return ret;
+
+	ret = of_alias_get_id(np, "serial");
+	if (IS_ERR_VALUE(ret)) {
+		seen_dev_without_alias = true;
+		ret = index;
+	} else {
+		seen_dev_with_alias = true;
+		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
+			dev_warn(dev, "requested serial port %d  not available.\n", ret);
+			ret = index;
+		}
+	}
+
+	if (seen_dev_with_alias && seen_dev_without_alias)
+		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
+
+	return ret;
+}
+
 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 {
 	struct uart_amba_port *uap;
@@ -1891,6 +1925,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto out;
 	}
 
+	i = pl011_probe_dt_alias(i, &dev->dev);
+
 	base = ioremap(dev->res.start, resource_size(&dev->res));
 	if (!base) {
 		ret = -ENOMEM;
-- 
1.7.0.4



From festevam at gmail.com  Wed Aug 22 12:25:31 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 22 Aug 2012 13:25:31 -0300
Subject: [PATCH 1/3] ARM: mxs: Rename 'hog-gpios'
Message-ID: <1345652733-13265-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

hog_pins is used to setup the pin functions, and it is not neccesarily used only
for GPIO pins, so use only 'hog' to describe a more generic term.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx23-evk.dts           |    2 +-
 arch/arm/boot/dts/imx23-stmp378x_devb.dts |    2 +-
 arch/arm/boot/dts/imx28-apx4devkit.dts    |    2 +-
 arch/arm/boot/dts/imx28-evk.dts           |    2 +-
 arch/arm/boot/dts/imx28-m28evk.dts        |    2 +-
 arch/arm/boot/dts/imx28-tx28.dts          |    2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f4..1093dd5 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,7 +42,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327..85c3864 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417..5171667 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e8..ab78ee5 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -50,7 +50,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd..ac3eff9 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -69,7 +69,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index a56ae05..37be532 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
 
-				hog_pins_a: hog-gpios at 0 {
+				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
 						0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
-- 
1.7.9.5



From festevam at gmail.com  Wed Aug 22 12:25:32 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 22 Aug 2012 13:25:32 -0300
Subject: [PATCH 2/3] ARM: mxs: Let mmc0 pin detect be generic
In-Reply-To: <1345652733-13265-1-git-send-email-festevam@gmail.com>
References: <1345652733-13265-1-git-send-email-festevam@gmail.com>
Message-ID: <1345652733-13265-2-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Instead of assigning SSP1_DETECT inside mmc0_4bit_pins_a, let the board dts
handle this setup.

Not every board will use MX23_PAD_SSP1_DETECT as SSP1 functionality. 

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx23-evk.dts |    1 +
 arch/arm/boot/dts/imx23.dtsi    |    1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 1093dd5..035c13f 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -48,6 +48,7 @@
 						0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
 						0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
 						0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+						0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
 					>;
 					fsl,drive-strength = <0>;
 					fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 9700872..b00f3cf 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -194,7 +194,6 @@
 						0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
 						0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
 						0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
-						0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
 						0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
 					>;
 					fsl,drive-strength = <1>;
-- 
1.7.9.5



From festevam at gmail.com  Wed Aug 22 12:25:33 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 22 Aug 2012 13:25:33 -0300
Subject: [PATCH 3/3] ARM: olinuxino: Add gpio-led support
In-Reply-To: <1345652733-13265-1-git-send-email-festevam@gmail.com>
References: <1345652733-13265-1-git-send-email-festevam@gmail.com>
Message-ID: <1345652733-13265-3-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Olinuxino has a LED connected to MX23_PAD_SSP1_DETECT__GPIO_2_1 pin.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx23-olinuxino.dts |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index a286873..711dcf5 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,21 @@
 				bus-width = <4>;
 				status = "okay";
 			};
+
+			pinctrl at 80018000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&hog_pins_a>;
+
+				hog_pins_a: hog at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+			};
 		};
 
 		apbx at 80040000 {
@@ -47,4 +62,14 @@
 			};
 		};
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		user {
+			label = "green";
+			gpios = <&gpio2 1 0>;
+			linux,default-trigger = "default-on";
+		};
+	};
 };
-- 
1.7.9.5



From broonie at opensource.wolfsonmicro.com  Wed Aug 22 13:00:25 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 18:00:25 +0100
Subject: [PATCH 14/14] drivers/spi/spi-s3c24xx.c: fix error return code
In-Reply-To: <alpine.DEB.2.02.1208221342240.1991@hadrien>
References: <1345365870-29831-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345365870-29831-15-git-send-email-Julia.Lawall@lip6.fr>
 <1b3201cd8049$e753f720$b5fbe560$%kim@samsung.com>
 <20120822114015.GI7995@opensource.wolfsonmicro.com>
 <alpine.DEB.2.02.1208221342240.1991@hadrien>
Message-ID: <20120822170025.GV7995@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 01:42:47PM +0200, Julia Lawall wrote:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> Initialize return variable before exiting on an error path.

Applied, thanks.
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From mporter at ti.com  Wed Aug 22 13:10:26 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 13:10:26 -0400
Subject: [PATCH v2 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EA65999@DBDE01.ent.ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-2-git-send-email-mporter@ti.com>
 <1BAFE6F6C881BF42822005164F1491C33EA65999@DBDE01.ent.ti.com>
Message-ID: <20120822171026.GC27758@beef>

On Wed, Aug 22, 2012 at 12:37:18PM +0000, Hebbar, Gururaja wrote:
> On Wed, Aug 22, 2012 at 00:13:07, Porter, Matt wrote:
> > Add a DMA engine driver for the TI EDMA controller. This driver
> > is implemented as a wrapper around the existing DaVinci private
> > DMA implementation. This approach allows for incremental conversion
> > of each peripheral driver to the DMA engine API. The EDMA driver
> > supports slave transfers but does not yet support cyclic transfers.
> > 
> > Signed-off-by: Matt Porter <mporter at ti.com>
> > ---
> >  drivers/dma/Kconfig  |   10 +
> >  drivers/dma/Makefile |    1 +
> >  drivers/dma/edma.c   |  684 ++++++++++++++++++++++++++++++++++++++++++++++++++
> >  include/linux/edma.h |   29 +++
> >  4 files changed, 724 insertions(+)
> >  create mode 100644 drivers/dma/edma.c
> >  create mode 100644 include/linux/edma.h
> > 
> > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> > index d06ea29..5064e85 100644
> > --- a/drivers/dma/Kconfig
> > +++ b/drivers/dma/Kconfig
> > @@ -208,6 +208,16 @@ config SIRF_DMA
> >  	help
> >  	  Enable support for the CSR SiRFprimaII DMA engine.
> >  
> > +config TI_EDMA
> > +	tristate "TI EDMA support"
> > +	depends on ARCH_DAVINCI
> > +	select DMA_ENGINE
> > +	select DMA_VIRTUAL_CHANNELS
> > +	default y
> > +	help
> > +	  Enable support for the TI EDMA controller. This DMA
> > +	  engine is found on TI DaVinci and AM33xx parts.
> > +
> >  config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
> >  	bool
> >  
> > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> > index 4cf6b12..f5cf310 100644
> > --- a/drivers/dma/Makefile
> > +++ b/drivers/dma/Makefile
> > @@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
> >  obj-$(CONFIG_MXS_DMA) += mxs-dma.o
> >  obj-$(CONFIG_TIMB_DMA) += timb_dma.o
> >  obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
> > +obj-$(CONFIG_TI_EDMA) += edma.o
> >  obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
> >  obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
> >  obj-$(CONFIG_PL330_DMA) += pl330.o
> > diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
> > new file mode 100644
> > index 0000000..bf15f81
> > --- /dev/null
> > +++ b/drivers/dma/edma.c
> > @@ -0,0 +1,684 @@
> > +/*
> > + * TI EDMA DMA engine driver
> > + *
> > + * Copyright 2012 Texas Instruments
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/dmaengine.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/list.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <mach/edma.h>
> > +
> > +#include "dmaengine.h"
> > +#include "virt-dma.h"
> > +
> > +/*
> > + * This will go away when the private EDMA API is folded
> > + * into this driver and the platform device(s) are
> > + * instantiated in the arch code. We can only get away
> > + * with this simplification because DA8XX may not be built
> > + * in the same kernel image with other DaVinci parts. This
> > + * avoids having to sprinkle dmaengine driver platform devices
> > + * and data throughout all the existing board files.
> > + */
> > +#ifdef CONFIG_ARCH_DAVINCI_DA8XX
> > +#define EDMA_CTLRS	2
> > +#define EDMA_CHANS	32
> > +#else
> > +#define EDMA_CTLRS	1
> > +#define EDMA_CHANS	64
> > +#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
> 
> I believe you already have some modifications for your next version to handle
> Different EDMA IP versions (AM335x). 
> They use/have cross-bar implementations as-well.

I don't have those yet. That effort is a WIP atm. However, I should 
probably add more details to the approach I mentioned in the cover
letter for this series.  AM335x support will happen by migrating the
private EDMA API to arm/common/. There's an incremental change
to the private EDMA API implementation to handle AM335x's cross-bar
support that exists right now only in the TI vendor tree. I'm going
to add that, align the platform devices generated from hwmod data
with the existing private EDMA driver expectations, and also add
the DT bindings necessary to communicate all the hardware config
that's currently carried in the mach-davinci/ board files. That
will enable the private EDMA API on AM335x. What I have pushed so
far to my WIP branch is:

https://github.com/ohporter/linux/tree/WIP/edma-dmaengine-private-migration

Completely non-functional on AM335x, but you can at least see
where I'm going there. I'm working on the pdev/pdata/DT part
mentioned above atm.

In turn, since this driver is completely self-contained and
sits only on top of the private EDMA API, it will then work
on AM335x. This approach avoids having to first convert the
remaining McASP driver (also requiring addition of cyclic
transfer support) and refactoring the private EDMA API into
drivers/dma/edma.c. Instead we can get this wrapper driver
immediately working for AM335x at least for slave transfers.
Then go back to handle cyclic/McASP...then the later private
EDMA API removal.

> 
> > +
> > +/* Max of 16 segments per channel to conserve PaRAM slots */
> > +#define MAX_NR_SG		16
> > +#define EDMA_MAX_SLOTS		MAX_NR_SG
> 
> Is it possible to get this (EDMA_MAX_SLOTS) from platform data?

Absolutely. Once the private EDMA API goes away. The whole
point of this driver is to be completely standalone around
the private EDMA API.

Also, keep in mind that this is an arbitrary value chosen to
handle the fact that we have this finite resource of PaRAM slots
and we can't have a single channel getting allocated and someone
passing in a scatterlist that will consume every slot in the
system. Doing a better job of managing the slot resources is
something that's on the long-range list. Right now it's more
important to address just getting all the drivers converted
and support on both davinci and omap2+.

> 
> > +#define EDMA_DESCRIPTORS	16
> > +
> > +struct edma_desc {
> > +	struct virt_dma_desc		vdesc;
> > +	struct list_head		node;
> > +
> > +	int				absync;
> > +	int				pset_nr;
> > +	struct edmacc_param		pset[0];
> > +};
> > +
> > +struct edma_cc;
> > +
> > +struct edma_chan {
> > +	struct virt_dma_chan		vchan;
> > +	struct list_head		node;
> > +	struct edma_desc		*edesc;
> > +	struct edma_cc			*ecc;
> > +	int				ch_num;
> > +	bool				alloced;
> > +	int				slot[EDMA_MAX_SLOTS];
> > +
> > +	dma_addr_t			addr;
> > +	int				addr_width;
> > +	int				maxburst;
> > +};
> > +
> > +struct edma_cc {
> > +	int				ctlr;
> > +	struct dma_device		dma_slave;
> > +	struct edma_chan		slave_chans[EDMA_CHANS];
> > +	int				num_slave_chans;
> > +	int				dummy_slot;
> > +};
> > +
> > +static inline struct edma_cc *to_edma_cc(struct dma_device *d)
> > +{
> > +	return container_of(d, struct edma_cc, dma_slave);
> > +}
> > +
> > +static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
> > +{
> > +	return container_of(c, struct edma_chan, vchan.chan);
> > +}
> > +
> > +static inline struct edma_desc
> > +*to_edma_desc(struct dma_async_tx_descriptor *tx)
> > +{
> > +	return container_of(tx, struct edma_desc, vdesc.tx);
> > +}
> > +
> > +static void edma_desc_free(struct virt_dma_desc *vdesc)
> > +{
> > +	kfree(container_of(vdesc, struct edma_desc, vdesc));
> > +}
> > +
> > +/* Dispatch a queued descriptor to the controller (caller holds lock) */
> > +static void edma_execute(struct edma_chan *echan)
> > +{
> > +	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
> > +	struct edma_desc *edesc;
> > +	int i;
> > +
> > +	if (!vdesc) {
> > +		echan->edesc = NULL;
> > +		return;
> > +	}
> > +
> > +	list_del(&vdesc->node);
> > +
> > +	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
> > +
> > +	/* Write descriptor PaRAM set(s) */
> > +	for (i = 0; i < edesc->pset_nr; i++) {
> > +		edma_write_slot(echan->slot[i], &edesc->pset[i]);
> > +		dev_dbg(echan->vchan.chan.device->dev,
> > +			"\n pset[%d]:\n"
> > +			"  chnum\t%d\n"
> > +			"  slot\t%d\n"
> > +			"  opt\t%08x\n"
> > +			"  src\t%08x\n"
> > +			"  dst\t%08x\n"
> > +			"  abcnt\t%08x\n"
> > +			"  ccnt\t%08x\n"
> > +			"  bidx\t%08x\n"
> > +			"  cidx\t%08x\n"
> > +			"  lkrld\t%08x\n",
> > +			i, echan->ch_num, echan->slot[i],
> > +			edesc->pset[i].opt,
> > +			edesc->pset[i].src,
> > +			edesc->pset[i].dst,
> > +			edesc->pset[i].a_b_cnt,
> > +			edesc->pset[i].ccnt,
> > +			edesc->pset[i].src_dst_bidx,
> > +			edesc->pset[i].src_dst_cidx,
> > +			edesc->pset[i].link_bcntrld);
> > +		/* Link to the previous slot if not the last set */
> > +		if (i != (edesc->pset_nr - 1))
> > +			edma_link(echan->slot[i], echan->slot[i+1]);
> > +		/* Final pset links to the dummy pset */
> > +		else
> > +			edma_link(echan->slot[i], echan->ecc->dummy_slot);
> > +	}
> > +
> > +	edma_start(echan->ch_num);
> > +}
> > +
> > +static int edma_terminate_all(struct edma_chan *echan)
> > +{
> > +	unsigned long flags;
> > +	LIST_HEAD(head);
> > +
> > +	spin_lock_irqsave(&echan->vchan.lock, flags);
> > +
> > +	/*
> > +	 * Stop DMA activity: we assume the callback will not be called
> > +	 * after edma_dma() returns (even if it does, it will see
> > +	 * echan->edesc is NULL and exit.)
> > +	 */
> > +	if (echan->edesc) {
> > +		echan->edesc = NULL;
> > +		edma_stop(echan->ch_num);
> > +	}
> > +
> > +	vchan_get_all_descriptors(&echan->vchan, &head);
> > +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +	vchan_dma_desc_free_list(&echan->vchan, &head);
> > +
> > +	return 0;
> > +}
> > +
> > +
> > +static int edma_slave_config(struct edma_chan *echan,
> > +	struct dma_slave_config *config)
> > +{
> > +	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
> > +		(config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> > +		return -EINVAL;
> > +
> > +	if (config->direction == DMA_MEM_TO_DEV) {
> > +		if (config->dst_addr)
> > +			echan->addr = config->dst_addr;
> > +		if (config->dst_addr_width)
> > +			echan->addr_width = config->dst_addr_width;
> > +		if (config->dst_maxburst)
> > +			echan->maxburst = config->dst_maxburst;
> > +	} else if (config->direction == DMA_DEV_TO_MEM) {
> > +		if (config->src_addr)
> > +			echan->addr = config->src_addr;
> > +		if (config->src_addr_width)
> > +			echan->addr_width = config->src_addr_width;
> > +		if (config->src_maxburst)
> > +			echan->maxburst = config->src_maxburst;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> > +			unsigned long arg)
> > +{
> > +	int ret = 0;
> > +	struct dma_slave_config *config;
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +
> > +	switch (cmd) {
> > +	case DMA_TERMINATE_ALL:
> > +		edma_terminate_all(echan);
> > +		break;
> > +	case DMA_SLAVE_CONFIG:
> > +		config = (struct dma_slave_config *)arg;
> > +		ret = edma_slave_config(echan, config);
> > +		break;
> > +	default:
> > +		ret = -ENOSYS;
> > +	}
> > +
> > +	return ret;
> > +}
> > +
> > +static struct dma_async_tx_descriptor *edma_prep_slave_sg(
> > +	struct dma_chan *chan, struct scatterlist *sgl,
> > +	unsigned int sg_len, enum dma_transfer_direction direction,
> > +	unsigned long tx_flags, void *context)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	struct edma_desc *edesc;
> > +	struct scatterlist *sg;
> > +	int i;
> > +	int acnt, bcnt, ccnt, src, dst, cidx;
> > +	int src_bidx, dst_bidx, src_cidx, dst_cidx;
> > +
> > +	if (unlikely(!echan || !sgl || !sg_len))
> > +		return NULL;
> > +
> > +	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
> > +		dev_err(dev, "Undefined slave buswidth\n");
> > +		return NULL;
> > +	}
> > +
> > +	if (sg_len > MAX_NR_SG) {
> > +		dev_err(dev, "Exceeded max SG segments %d > %d\n",
> > +			sg_len, MAX_NR_SG);
> > +		return NULL;
> > +	}
> > +
> > +	edesc = kzalloc(sizeof(*edesc) + sg_len *
> > +		sizeof(edesc->pset[0]), GFP_ATOMIC);
> > +	if (!edesc) {
> > +		dev_dbg(dev, "Failed to allocate a descriptor\n");
> > +		return NULL;
> > +	}
> > +
> > +	edesc->pset_nr = sg_len;
> > +
> > +	for_each_sg(sgl, sg, sg_len, i) {
> > +		/* Allocate a PaRAM slot, if needed */
> > +		if (echan->slot[i] < 0) {
> > +			echan->slot[i] =
> > +				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
> > +						EDMA_SLOT_ANY);
> > +			if (echan->slot[i] < 0) {
> > +				dev_err(dev, "Failed to allocate slot\n");
> > +				return NULL;
> > +			}
> > +		}
> > +
> > +		acnt = echan->addr_width;
> > +
> > +		/*
> > +		 * If the maxburst is equal to the fifo width, use
> > +		 * A-synced transfers. This allows for large contiguous
> > +		 * buffer transfers using only one PaRAM set.
> > +		 */
> > +		if (echan->maxburst == 1) {
> > +			edesc->absync = false;
> > +			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
> > +			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
> > +			if (bcnt)
> > +				ccnt++;
> > +			else
> > +				bcnt = SZ_64K - 1;
> > +			cidx = acnt;
> > +		/*
> > +		 * If maxburst is greater than the fifo address_width,
> > +		 * use AB-synced transfers where A count is the fifo
> > +		 * address_width and B count is the maxburst. In this
> > +		 * case, we are limited to transfers of C count frames
> > +		 * of (address_width * maxburst) where C count is limited
> > +		 * to SZ_64K-1. This places an upper bound on the length
> > +		 * of an SG segment that can be handled.
> > +		 */
> > +		} else {
> > +			edesc->absync = true;
> > +			bcnt = echan->maxburst;
> > +			ccnt = sg_dma_len(sg) / (acnt * bcnt);
> > +			if (ccnt > (SZ_64K - 1)) {
> > +				dev_err(dev, "Exceeded max SG segment size\n");
> > +				return NULL;
> > +			}
> > +			cidx = acnt * bcnt;
> > +		}
> > +
> > +		if (direction == DMA_MEM_TO_DEV) {
> > +			src = sg_dma_address(sg);
> > +			dst = echan->addr;
> > +			src_bidx = acnt;
> > +			src_cidx = cidx;
> > +			dst_bidx = 0;
> > +			dst_cidx = 0;
> > +		} else {
> > +			src = echan->addr;
> > +			dst = sg_dma_address(sg);
> > +			src_bidx = 0;
> > +			src_cidx = 0;
> > +			dst_bidx = acnt;
> > +			dst_cidx = cidx;
> > +		}
> > +
> > +		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
> > +		/* Configure A or AB synchronized transfers */
> > +		if (edesc->absync)
> > +			edesc->pset[i].opt |= SYNCDIM;
> > +		/* If this is the last set, enable completion interrupt flag */
> > +		if (i == sg_len - 1)
> > +			edesc->pset[i].opt |= TCINTEN;
> > +
> > +		edesc->pset[i].src = src;
> > +		edesc->pset[i].dst = dst;
> > +
> > +		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
> > +		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
> > +
> > +		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
> > +		edesc->pset[i].ccnt = ccnt;
> > +		edesc->pset[i].link_bcntrld = 0xffffffff;
> > +
> > +	}
> > +
> > +	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
> > +}
> > +
> > +static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
> > +{
> > +	struct edma_chan *echan = data;
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	struct edma_desc *edesc;
> > +	unsigned long flags;
> > +
> > +	/* Stop the channel */
> > +	edma_stop(echan->ch_num);
> > +
> > +	switch (ch_status) {
> > +	case DMA_COMPLETE:
> > +		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
> > +
> > +		spin_lock_irqsave(&echan->vchan.lock, flags);
> > +
> > +		edesc = echan->edesc;
> > +		if (edesc) {
> > +			edma_execute(echan);
> > +			vchan_cookie_complete(&edesc->vdesc);
> > +		}
> > +
> > +		spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +
> > +		break;
> > +	case DMA_CC_ERROR:
> > +		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
> > +		break;
> > +	default:
> > +		break;
> > +	}
> > +}
> > +
> > +/* Alloc channel resources */
> > +static int edma_alloc_chan_resources(struct dma_chan *chan)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	int ret;
> > +	int a_ch_num;
> > +	LIST_HEAD(descs);
> > +
> > +	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
> > +					chan, EVENTQ_DEFAULT);
> > +
> > +	if (a_ch_num < 0) {
> > +		ret = -ENODEV;
> > +		goto err_no_chan;
> > +	}
> > +
> > +	if (a_ch_num != echan->ch_num) {
> > +		dev_err(dev, "failed to allocate requested channel %u:%u\n",
> > +			EDMA_CTLR(echan->ch_num),
> > +			EDMA_CHAN_SLOT(echan->ch_num));
> > +		ret = -ENODEV;
> > +		goto err_wrong_chan;
> > +	}
> > +
> > +	echan->alloced = true;
> > +	echan->slot[0] = echan->ch_num;
> > +
> > +	dev_info(dev, "allocated channel for %u:%u\n",
> > +		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
> > +
> > +	return 0;
> > +
> > +err_wrong_chan:
> > +	edma_free_channel(a_ch_num);
> > +err_no_chan:
> > +	return ret;
> > +}
> > +
> > +/* Free channel resources */
> > +static void edma_free_chan_resources(struct dma_chan *chan)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct device *dev = echan->vchan.chan.device->dev;
> > +	int i;
> > +
> > +	/* Terminate transfers */
> > +	edma_stop(echan->ch_num);
> > +
> > +	vchan_free_chan_resources(&echan->vchan);
> > +
> > +	/* Free EDMA PaRAM slots */
> > +	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
> > +		if (echan->slot[i] >= 0) {
> > +			edma_free_slot(echan->slot[i]);
> > +			echan->slot[i] = -1;
> > +		}
> > +	}
> > +
> > +	/* Free EDMA channel */
> > +	if (echan->alloced) {
> > +		edma_free_channel(echan->ch_num);
> > +		echan->alloced = false;
> > +	}
> > +
> > +	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
> > +}
> > +
> > +/* Send pending descriptor to hardware */
> > +static void edma_issue_pending(struct dma_chan *chan)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	unsigned long flags;
> > +
> > +	spin_lock_irqsave(&echan->vchan.lock, flags);
> > +	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
> > +		edma_execute(echan);
> > +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +}
> > +
> > +static size_t edma_desc_size(struct edma_desc *edesc)
> > +{
> > +	int i;
> > +	size_t size;
> > +
> > +	if (edesc->absync)
> > +		for (size = i = 0; i < edesc->pset_nr; i++)
> > +			size += (edesc->pset[i].a_b_cnt & 0xffff) *
> > +				(edesc->pset[i].a_b_cnt >> 16) *
> > +				 edesc->pset[i].ccnt;
> > +	else
> > +		size = (edesc->pset[0].a_b_cnt & 0xffff) *
> > +			(edesc->pset[0].a_b_cnt >> 16) +
> > +			(edesc->pset[0].a_b_cnt & 0xffff) *
> > +			(SZ_64K - 1) * edesc->pset[0].ccnt;
> > +
> > +	return size;
> > +}
> > +
> > +/* Check request completion status */
> > +static enum dma_status edma_tx_status(struct dma_chan *chan,
> > +				      dma_cookie_t cookie,
> > +				      struct dma_tx_state *txstate)
> > +{
> > +	struct edma_chan *echan = to_edma_chan(chan);
> > +	struct virt_dma_desc *vdesc;
> > +	enum dma_status ret;
> > +	unsigned long flags;
> > +
> > +	ret = dma_cookie_status(chan, cookie, txstate);
> > +	if (ret == DMA_SUCCESS || !txstate)
> > +		return ret;
> > +
> > +	spin_lock_irqsave(&echan->vchan.lock, flags);
> > +	vdesc = vchan_find_desc(&echan->vchan, cookie);
> > +	if (vdesc) {
> > +		txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
> > +	} else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
> > +		struct edma_desc *edesc = echan->edesc;
> > +		txstate->residue = edma_desc_size(edesc);
> > +	} else {
> > +		txstate->residue = 0;
> > +	}
> > +	spin_unlock_irqrestore(&echan->vchan.lock, flags);
> > +
> > +	return ret;
> > +}
> > +
> > +static void __init edma_chan_init(struct edma_cc *ecc,
> > +				  struct dma_device *dma,
> > +				  struct edma_chan *echans)
> > +{
> > +	int i, j;
> > +	int chcnt = 0;
> > +
> > +	for (i = 0; i < EDMA_CHANS; i++) {
> > +		struct edma_chan *echan = &echans[chcnt];
> > +		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
> 
> I couldn't find the definition for EDMA_CTLR_CHAN.

arch/arm/mach-davinci/include/mach/edma.h

> > +		echan->ecc = ecc;
> > +		echan->vchan.desc_free = edma_desc_free;
> > +
> > +		vchan_init(&echan->vchan, dma);
> > +
> > +		INIT_LIST_HEAD(&echan->node);
> > +		for (j = 0; j < EDMA_MAX_SLOTS; j++)
> > +			echan->slot[j] = -1;
> > +
> > +		chcnt++;
> > +	}
> > +}
> > +
> > +static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
> > +			  struct device *dev)
> > +{
> > +	if (dma_has_cap(DMA_SLAVE, dma->cap_mask))
> > +		dma->device_prep_slave_sg = edma_prep_slave_sg;
> > +
> > +	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
> > +	dma->device_free_chan_resources = edma_free_chan_resources;
> > +	dma->device_issue_pending = edma_issue_pending;
> > +	dma->device_tx_status = edma_tx_status;
> > +	dma->device_control = edma_control;
> > +	dma->dev = dev;
> > +
> > +	INIT_LIST_HEAD(&dma->channels);
> > +}
> > +
> > +static int __devinit edma_probe(struct platform_device *pdev)
> > +{
> > +	struct edma_cc *ecc;
> > +	int ret;
> > +
> > +	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
> > +	if (!ecc) {
> > +		dev_err(&pdev->dev, "Can't allocate controller\n");
> > +		ret = -ENOMEM;
> > +		goto err_alloc_ecc;
> > +	}
> > +
> > +	ecc->ctlr = pdev->id;
> > +	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
> > +	if (ecc->dummy_slot < 0) {
> > +		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
> > +		ret = -EIO;
> > +		goto err_alloc_slot;
> > +	}
> > +
> > +	dma_cap_zero(ecc->dma_slave.cap_mask);
> > +	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
> > +
> > +	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
> > +
> > +	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
> > +
> > +	ret = dma_async_device_register(&ecc->dma_slave);
> > +	if (ret)
> > +		goto err_reg1;
> > +
> > +	platform_set_drvdata(pdev, ecc);
> > +
> > +	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
> > +
> > +	return 0;
> > +
> > +err_reg1:
> > +	edma_free_slot(ecc->dummy_slot);
> > +err_alloc_slot:
> > +	devm_kfree(&pdev->dev, ecc);
> > +err_alloc_ecc:
> > +	return ret;
> > +}
> > +
> > +static int __devexit edma_remove(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct edma_cc *ecc = dev_get_drvdata(dev);
> > +
> > +	dma_async_device_unregister(&ecc->dma_slave);
> > +	edma_free_slot(ecc->dummy_slot);
> > +	devm_kfree(dev, ecc);
> > +
> > +	return 0;
> > +}
> > +
> > +static struct platform_driver edma_driver = {
> > +	.probe		= edma_probe,
> > +	.remove		= __devexit_p(edma_remove),
> > +	.driver = {
> > +		.name = "edma-dma-engine",
> > +		.owner = THIS_MODULE,
> 
> I believe you already have plans for DT implementations for this as-well.

Yes, but DT support for the wrapper is not required. See the above
explanation. This works exactly like omap-dma.c. I do have to create
DT bindings to encapsulate the hardware configuration and the plan
is that those will be used to populate the private EDMA API
platform data...and when the private EDMA API goes away (refactored
into drivers/dma/edma.c) then the same DT support will live in the
dmaengine driver.

> > +	},
> > +};
> > +
> > +bool edma_filter_fn(struct dma_chan *chan, void *param)
> > +{
> > +	if (chan->device->dev->driver == &edma_driver.driver) {
> > +		struct edma_chan *echan = to_edma_chan(chan);
> > +		unsigned ch_req = *(unsigned *)param;
> > +		return ch_req == echan->ch_num;
> > +	}
> > +	return false;
> > +}
> > +EXPORT_SYMBOL(edma_filter_fn);
> > +
> > +static struct platform_device *pdev0, *pdev1;
> > +
> > +static const struct platform_device_info edma_dev_info0 = {
> > +	.name = "edma-dma-engine",
> > +	.id = 0,
> > +	.dma_mask = DMA_BIT_MASK(32),
> > +};
> > +
> > +static const struct platform_device_info edma_dev_info1 = {
> > +	.name = "edma-dma-engine",
> > +	.id = 1,
> > +	.dma_mask = DMA_BIT_MASK(32),
> > +};
> > +
> > +static int edma_init(void)
> > +{
> > +	int ret = platform_driver_register(&edma_driver);
> > +
> > +	if (ret == 0) {
> > +		pdev0 = platform_device_register_full(&edma_dev_info0);
> > +		if (IS_ERR(pdev0)) {
> > +			platform_driver_unregister(&edma_driver);
> > +			ret = PTR_ERR(pdev0);
> > +			goto out;
> > +		}
> > +	}
> > +
> > +	if (EDMA_CTLRS == 2) {
> > +		pdev1 = platform_device_register_full(&edma_dev_info1);
> > +		if (IS_ERR(pdev1)) {
> > +			platform_driver_unregister(&edma_driver);
> > +			platform_device_unregister(pdev0);
> > +			ret = PTR_ERR(pdev1);
> > +		}
> > +	}
> > +
> > +out:
> > +	return ret;
> > +}
> > +subsys_initcall(edma_init);
> > +
> > +static void __exit edma_exit(void)
> > +{
> > +	platform_device_unregister(pdev0);
> > +	if (pdev1)
> > +		platform_device_unregister(pdev1);
> > +	platform_driver_unregister(&edma_driver);
> > +}
> > +module_exit(edma_exit);
> > +
> > +MODULE_AUTHOR("Matt Porter <mporter at ti.com>");
> > +MODULE_DESCRIPTION("TI EDMA DMA engine driver");
> > +MODULE_LICENSE("GPL v2");
> > diff --git a/include/linux/edma.h b/include/linux/edma.h
> > new file mode 100644
> > index 0000000..a1307e7
> > --- /dev/null
> > +++ b/include/linux/edma.h
> > @@ -0,0 +1,29 @@
> > +/*
> > + * TI EDMA DMA engine driver
> > + *
> > + * Copyright 2012 Texas Instruments
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +#ifndef __LINUX_EDMA_H
> > +#define __LINUX_EDMA_H
> > +
> > +struct dma_chan;
> > +
> > +#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
> > +bool edma_filter_fn(struct dma_chan *, void *);
> > +#else
> > +static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
> > +{
> > +	return false;
> > +}
> > +#endif
> > +
> > +#endif
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source at linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > 
> 
> 
> Regards, 
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source


From catalin.marinas at arm.com  Wed Aug 22 13:13:10 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 22 Aug 2012 18:13:10 +0100
Subject: [PATCH v2 17/31] arm64: System calls handling
In-Reply-To: <201208221227.14274.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208220756.31149.arnd@arndb.de> <20120822102953.GA24136@arm.com>
 <201208221227.14274.arnd@arndb.de>
Message-ID: <20120822171309.GC2582@arm.com>

On Wed, Aug 22, 2012 at 01:27:14PM +0100, Arnd Bergmann wrote:
> On Wednesday 22 August 2012, Catalin Marinas wrote:
> > But what's more important - moving this wrapper to glibc causes issues
> > with the page size. We support both 4KB and 64KB pages on 64-bit systems
> > (the latter without compat support). The kernel is in a better position
> > to do the shift by a compile-time constant. Glibc would need to enquire
> > the actual page size to do the shift before calling sys_mmap_pgoff. If
> > we assume in glibc that the shift is always 12, we need another wrapper
> > in the kernel anyway for 64KB page configuration. So passing the offset
> > in bytes worked best for us.
> 
> Right, the kernel interface should really be independent of the page
> size, as sys_mmap2 normally is, and sys_mmap2 is not provided here.

sys_mmap2 is indeed independent of the page size on most architectures
assuming that the last argument represents the offset in units of 4096.
The cris and ia64 seem to differ (one being 8K, the other variable).

sys_mmap is also independent of the page size.

But using sys_mmap2 for a 64-bit architecture, especially when the page
size is not always 4K, does not bring any advantages. We end up doing a
shift by 12 in glibc and another shift by (PAGE_SHIFT - 12) in the
kernel wrapper. Unless I missed your point, I don't see the reason for
using sys_mmap2 on a 64-bit architecture, apart from it being newer (and
compat support should not have any relevance, we have different syscall
tables anyway).

-- 
Catalin


From sboyd at codeaurora.org  Wed Aug 22 13:15:14 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 10:15:14 -0700
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <1345645780-2749-2-git-send-email-arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
Message-ID: <503513A2.1030002@codeaurora.org>

On 08/22/12 07:29, Arnd Bergmann wrote:
> read_current_timer is used in the get_cycles() function when
> ARM_ARCH_TIMER is set, and that function can be inlined into
> driver modules, so we should export the function to avoid
> errors like
>
> ERROR: "read_current_timer" [drivers/video/udlfb.ko] undefined!
> ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>

Acked-by: Stephen Boyd <sboyd at codeaurora.org>

I ran into this last week but forgot to send the patch. Thanks.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From arnd at arndb.de  Wed Aug 22 13:22:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 17:22:06 +0000
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <CAMQu2gw0x6saWrK-M3teu49tJDGvS8RhGrVSh6JTs5DEy+22pA@mail.gmail.com>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-3-git-send-email-arnd@arndb.de>
 <CAMQu2gw0x6saWrK-M3teu49tJDGvS8RhGrVSh6JTs5DEy+22pA@mail.gmail.com>
Message-ID: <201208221722.06775.arnd@arndb.de>

On Wednesday 22 August 2012, Shilimkar, Santosh wrote:

> Was just thinking whether we should just take care of it at
> core cpuidle level itself. Will below be enough to kill the build
> error what you mentioned in the change log ?
> 
> diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
> index 2c9bf26..df34534 100644
> --- a/drivers/cpuidle/coupled.c
> +++ b/drivers/cpuidle/coupled.c
> @@ -314,7 +314,9 @@ static void cpuidle_coupled_poke(int cpu)
>         struct call_single_data *csd = &per_cpu(cpuidle_coupled_poke_cb, cpu);
> 
>         if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask))
> +#ifdef CONFIG_SMP
>                 __smp_call_function_single(cpu, csd, 0);
> +#endif
>  }
> 

That would work, but isn't the entire concept of the cpuidle-coupled driver
dependent on SMP? If this driver makes no sense on UP, I think we should
not attempt to build it.

	Arnd


From dromede at gmail.com  Wed Aug 22 13:27:04 2012
From: dromede at gmail.com (dromede at gmail.com)
Date: Wed, 22 Aug 2012 19:27:04 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
Message-ID: <1345656424-31234-1-git-send-email-dromede@gmail.com>

From: Marko Katic <dromede.gmail.com>


I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It 
hanged almost immediately after uncompressing the kernel. I tracked the
problem down to a single line in arch/arm/common/sharpsl_param.c:

memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));

Commenting out the line makes the kernel boot just fine. This left me
wondering whether sharpsl_param.c is actually needed. Here's a comment
from sharpsl_param.c that describes what sharpsl_param.c actually does:

/*
 * Certain hardware parameters determined at the time of device manufacture,
 * typically including LCD parameters are loaded by the bootloader at the
 * address PARAM_BASE. As the kernel will overwrite them, we need to store
 * them early in the boot process, then pass them to the appropriate drivers.
 * Not all devices use all parameters but the format is common to all.
 */
 
 So sharpsl_save_param() is supposed to fill the sharpsl_param_info struct
 with various parameters or fill some of the struct fields with -1. 
 I found only four drivers that use some of these
 parameters (only two parameters are used by these drivers, comadj and phadadj). 
 These drivers are:
 
 drivers/video/backlight/corgi_lcd.c
 drivers/video/backlight/locomolcd.c
 drivers/video/backlight/tosa_bl.c
 drivers/video/backlight/tosa_lcd.c
 
 These drivers also have default values when comadj or phadadj == -1.
 I checked what values are actually contained in this struct in
 earlier kernels. 3.2.24 kernel is the latest one i know of where
 sharpsl_save_param() works properly. And it also has these fields initialised
 to -1.
 
 So it seems to me that sharpsl_param.c is redundant as it currently only  
 serves to assign -1 to a few variables. And drivers that use these variables
 then handle -1 with assigning default values.
 
 I propose a patch that completely removes the usage of sharpsl_param.c.
 I confirm that this patch works fine on a C-1000 and therefore i assume that
 it should work fine on all machines that use the corgi_lcd.c driver.
 
 This patch should be tested on collie and tosa machines.

---
 arch/arm/common/Kconfig                   |    3 -
 arch/arm/common/Makefile                  |    1 -
 arch/arm/common/sharpsl_param.c           |   62 -----------------------------
 arch/arm/include/asm/mach/sharpsl_param.h |   37 -----------------
 arch/arm/mach-pxa/Kconfig                 |    1 -
 arch/arm/mach-pxa/corgi.c                 |    2 -
 arch/arm/mach-pxa/poodle.c                |    2 -
 arch/arm/mach-pxa/spitz.c                 |    2 -
 arch/arm/mach-pxa/tosa.c                  |    2 -
 arch/arm/mach-sa1100/Kconfig              |    1 -
 arch/arm/mach-sa1100/collie.c             |    2 -
 drivers/power/collie_battery.c            |    1 -
 drivers/video/backlight/corgi_lcd.c       |    9 +---
 drivers/video/backlight/locomolcd.c       |    8 +--
 drivers/video/backlight/tosa_bl.c         |    4 +-
 drivers/video/backlight/tosa_lcd.c        |    2 -
 16 files changed, 6 insertions(+), 133 deletions(-)
 delete mode 100644 arch/arm/common/sharpsl_param.c
 delete mode 100644 arch/arm/include/asm/mach/sharpsl_param.h

diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 283fa1d..8a2688a 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -35,8 +35,5 @@ config DMABOUNCE
 config SHARP_LOCOMO
 	bool
 
-config SHARP_PARAM
-	bool
-
 config SHARP_SCOOP
 	bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..c8634c8 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_SA1111)		+= sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
 obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o
-obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
deleted file mode 100644
index d56c932..0000000
--- a/arch/arm/common/sharpsl_param.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Hardware parameter area specific to Sharp SL series devices
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <asm/mach/sharpsl_param.h>
-
-/*
- * Certain hardware parameters determined at the time of device manufacture,
- * typically including LCD parameters are loaded by the bootloader at the
- * address PARAM_BASE. As the kernel will overwrite them, we need to store
- * them early in the boot process, then pass them to the appropriate drivers.
- * Not all devices use all parameters but the format is common to all.
- */
-#ifdef CONFIG_ARCH_SA1100
-#define PARAM_BASE	0xe8ffc000
-#else
-#define PARAM_BASE	0xa0000a00
-#endif
-#define MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 )  | ( b << 8 ) | a )
-
-#define COMADJ_MAGIC	MAGIC_CHG('C','M','A','D')
-#define UUID_MAGIC	MAGIC_CHG('U','U','I','D')
-#define TOUCH_MAGIC	MAGIC_CHG('T','U','C','H')
-#define AD_MAGIC	MAGIC_CHG('B','V','A','D')
-#define PHAD_MAGIC	MAGIC_CHG('P','H','A','D')
-
-struct sharpsl_param_info sharpsl_param;
-EXPORT_SYMBOL(sharpsl_param);
-
-void sharpsl_save_param(void)
-{
-	memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));
-
-	if (sharpsl_param.comadj_keyword != COMADJ_MAGIC)
-		sharpsl_param.comadj=-1;
-
-	if (sharpsl_param.phad_keyword != PHAD_MAGIC)
-		sharpsl_param.phadadj=-1;
-
-	if (sharpsl_param.uuid_keyword != UUID_MAGIC)
-		sharpsl_param.uuid[0]=-1;
-
-	if (sharpsl_param.touch_keyword != TOUCH_MAGIC)
-		sharpsl_param.touch_xp=-1;
-
-	if (sharpsl_param.adadj_keyword != AD_MAGIC)
-		sharpsl_param.adadj=-1;
-}
-
-
diff --git a/arch/arm/include/asm/mach/sharpsl_param.h b/arch/arm/include/asm/mach/sharpsl_param.h
deleted file mode 100644
index 7a24ecf..0000000
--- a/arch/arm/include/asm/mach/sharpsl_param.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Hardware parameter area specific to Sharp SL series devices
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * Based on Sharp's 2.4 kernel patches
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-struct sharpsl_param_info {
-  unsigned int comadj_keyword;
-  unsigned int comadj;
-
-  unsigned int uuid_keyword;
-  unsigned char uuid[16];
-
-  unsigned int touch_keyword;
-  unsigned int touch_xp;
-  unsigned int touch_yp;
-  unsigned int touch_xd;
-  unsigned int touch_yd;
-
-  unsigned int adadj_keyword;
-  unsigned int adadj;
-
-  unsigned int phad_keyword;
-  unsigned int phadadj;
-} __attribute__((packed));
-
-
-extern struct sharpsl_param_info sharpsl_param;
-extern void sharpsl_save_param(void);
-
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f8..71e9429 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -471,7 +471,6 @@ config MACH_RAUMFELD_SPEAKER
 config PXA_SHARPSL
 	bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
 	select SHARP_SCOOP
-	select SHARP_PARAM
 	help
 	  Say Y here if you intend to run this kernel on a
 	  Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi),
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index c1fe32d..1ddf87f 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -52,7 +52,6 @@
 #include <mach/corgi.h>
 #include <mach/sharpsl_pm.h>
 
-#include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
 #include "generic.h"
@@ -716,7 +715,6 @@ static void __init corgi_init(void)
 static void __init fixup_corgi(struct tag *tags, char **cmdline,
 			       struct meminfo *mi)
 {
-	sharpsl_save_param();
 	mi->nr_banks=1;
 	mi->bank[0].start = 0xa0000000;
 	if (machine_is_corgi())
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 89d98c8..0c4c083 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -48,7 +48,6 @@
 
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
-#include <asm/mach/sharpsl_param.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -457,7 +456,6 @@ static void __init poodle_init(void)
 static void __init fixup_poodle(struct tag *tags, char **cmdline,
 				struct meminfo *mi)
 {
-	sharpsl_save_param();
 	mi->nr_banks=1;
 	mi->bank[0].start = 0xa0000000;
 	mi->bank[0].size = (32*1024*1024);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 363d91b..9a0d583 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -35,7 +35,6 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
 #include <mach/pxa27x.h>
@@ -971,7 +970,6 @@ static void __init spitz_init(void)
 static void __init spitz_fixup(struct tag *tags, char **cmdline,
 			       struct meminfo *mi)
 {
-	sharpsl_save_param();
 	mi->nr_banks = 1;
 	mi->bank[0].start = 0xa0000000;
 	mi->bank[0].size = (64*1024*1024);
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 4d4eb60..3f8fe17 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -53,7 +53,6 @@
 #include <mach/tosa.h>
 
 #include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -968,7 +967,6 @@ static void __init tosa_init(void)
 static void __init fixup_tosa(struct tag *tags, char **cmdline,
 			      struct meminfo *mi)
 {
-	sharpsl_save_param();
 	mi->nr_banks=1;
 	mi->bank[0].start = 0xa0000000;
 	mi->bank[0].size = (64*1024*1024);
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 42625e4..87b8604 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -50,7 +50,6 @@ config SA1100_COLLIE
 	# FIXME: select CPU_FREQ_SA11x0
 	select SHARP_LOCOMO
 	select SHARP_SCOOP
-	select SHARP_PARAM
 	help
 	  Say Y here to support the Sharp Zaurus SL5500 PDAs.
 
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index ea5cff3..98287a4 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -43,7 +43,6 @@
 #include <asm/mach/serial_sa1100.h>
 
 #include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/locomo.h>
 #include <mach/mcp.h>
 #include <mach/irqs.h>
@@ -366,7 +365,6 @@ static void __init collie_init(void)
 			    ARRAY_SIZE(collie_flash_resources));
 	sa11x0_register_mcp(&collie_mcp_data);
 
-	sharpsl_save_param();
 }
 
 static struct map_desc collie_io_desc[] __initdata = {
diff --git a/drivers/power/collie_battery.c b/drivers/power/collie_battery.c
index 74c6b23..e83b963 100644
--- a/drivers/power/collie_battery.c
+++ b/drivers/power/collie_battery.c
@@ -19,7 +19,6 @@
 #include <linux/gpio.h>
 #include <linux/mfd/ucb1x00.h>
 
-#include <asm/mach/sharpsl_param.h>
 #include <asm/mach-types.h>
 #include <mach/collie.h>
 
diff --git a/drivers/video/backlight/corgi_lcd.c b/drivers/video/backlight/corgi_lcd.c
index c781768..c28838a 100644
--- a/drivers/video/backlight/corgi_lcd.c
+++ b/drivers/video/backlight/corgi_lcd.c
@@ -25,7 +25,6 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/corgi_lcd.h>
 #include <linux/slab.h>
-#include <asm/mach/sharpsl_param.h>
 
 #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)
 
@@ -195,9 +194,7 @@ static void lcdtg_set_phadadj(struct corgi_lcd *lcd, int mode)
 	switch(mode) {
 	case CORGI_LCD_MODE_VGA:
 		/* Setting for VGA */
-		adj = sharpsl_param.phadadj;
-		adj = (adj < 0) ? PHACTRL_PHASE_MANUAL :
-				  PHACTRL_PHASE_MANUAL | ((adj & 0xf) << 1);
+		adj = PHACTRL_PHASE_MANUAL;
 		break;
 	case CORGI_LCD_MODE_QVGA:
 	default:
@@ -242,9 +239,7 @@ static void corgi_lcd_power_on(struct corgi_lcd *lcd)
 			PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
 
 	/* Set Common Voltage */
-	comadj = sharpsl_param.comadj;
-	if (comadj < 0)
-		comadj = DEFAULT_COMADJ;
+	comadj = DEFAULT_COMADJ;
 
 	lcdtg_set_common_voltage(lcd, POWER0_DAC_ON | POWER0_COM_OFF |
 				 POWER0_VCC5_OFF, comadj);
diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c
index 3a6d541..62c4cb9 100644
--- a/drivers/video/backlight/locomolcd.c
+++ b/drivers/video/backlight/locomolcd.c
@@ -21,7 +21,6 @@
 
 #include <asm/hardware/locomo.h>
 #include <asm/irq.h>
-#include <asm/mach/sharpsl_param.h>
 #include <asm/mach-types.h>
 
 #include "../../../arch/arm/mach-sa1100/generic.h"
@@ -82,7 +81,7 @@ static void locomolcd_off(int comadj)
 
 void locomolcd_power(int on)
 {
-	int comadj = sharpsl_param.comadj;
+	int comadj;
 	unsigned long flags;
 
 	local_irq_save(flags);
@@ -92,10 +91,9 @@ void locomolcd_power(int on)
 		return;
 	}
 
-	/* read comadj */
-	if (comadj == -1 && machine_is_collie())
+	if (machine_is_collie())
 		comadj = 128;
-	if (comadj == -1 && machine_is_poodle())
+	if (machine_is_poodle())
 		comadj = 118;
 
 	if (on)
diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c
index 49342e1..2918075 100644
--- a/drivers/video/backlight/tosa_bl.c
+++ b/drivers/video/backlight/tosa_bl.c
@@ -20,8 +20,6 @@
 #include <linux/backlight.h>
 #include <linux/slab.h>
 
-#include <asm/mach/sharpsl_param.h>
-
 #include <mach/tosa.h>
 
 #define COMADJ_DEFAULT	97
@@ -90,7 +88,7 @@ static int __devinit tosa_bl_probe(struct i2c_client *client,
 	if (!data)
 		return -ENOMEM;
 
-	data->comadj = sharpsl_param.comadj == -1 ? COMADJ_DEFAULT : sharpsl_param.comadj;
+	data->comadj = COMADJ_DEFAULT;
 
 	ret = devm_gpio_request(&client->dev, TOSA_GPIO_BL_C20MA, "backlight");
 	if (ret) {
diff --git a/drivers/video/backlight/tosa_lcd.c b/drivers/video/backlight/tosa_lcd.c
index 33047a66..6fc575f 100644
--- a/drivers/video/backlight/tosa_lcd.c
+++ b/drivers/video/backlight/tosa_lcd.c
@@ -21,8 +21,6 @@
 #include <linux/lcd.h>
 #include <linux/fb.h>
 
-#include <asm/mach/sharpsl_param.h>
-
 #include <mach/tosa.h>
 
 #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)
-- 
1.7.4.1



From will.deacon at arm.com  Wed Aug 22 13:49:45 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 Aug 2012 18:49:45 +0100
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <503513A2.1030002@codeaurora.org>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
 <503513A2.1030002@codeaurora.org>
Message-ID: <20120822174945.GS9093@mudshark.cambridge.arm.com>

On Wed, Aug 22, 2012 at 06:15:14PM +0100, Stephen Boyd wrote:
> On 08/22/12 07:29, Arnd Bergmann wrote:
> > read_current_timer is used in the get_cycles() function when
> > ARM_ARCH_TIMER is set, and that function can be inlined into
> > driver modules, so we should export the function to avoid
> > errors like
> >
> > ERROR: "read_current_timer" [drivers/video/udlfb.ko] undefined!
> > ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
> >
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > Cc: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>
> 
> Acked-by: Stephen Boyd <sboyd at codeaurora.org>
> 
> I ran into this last week but forgot to send the patch. Thanks.

Looks good to me, thanks Arnd:

Acked-by: Will Deacon <will.deacon at arm.com>

On the topic of the timer stuff: Shinya/Stephen, did you have a chance to
look at the registration stuff that was proposed? I'm happy to push it if
people will actually use it.

Cheers,

Will


From sboyd at codeaurora.org  Wed Aug 22 13:57:20 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 10:57:20 -0700
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <20120822174945.GS9093@mudshark.cambridge.arm.com>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
 <503513A2.1030002@codeaurora.org>
 <20120822174945.GS9093@mudshark.cambridge.arm.com>
Message-ID: <50351D80.6010600@codeaurora.org>

On 08/22/12 10:49, Will Deacon wrote:
> On the topic of the timer stuff: Shinya/Stephen, did you have a chance to
> look at the registration stuff that was proposed? I'm happy to push it if
> people will actually use it.

Yes I have tested it on our internal trees and it looks good. I plan to
send a patch to move MSM's timers over to it later this week so that we
have at least two users upstream.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From will.deacon at arm.com  Wed Aug 22 13:58:10 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 22 Aug 2012 18:58:10 +0100
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <50351D80.6010600@codeaurora.org>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
 <503513A2.1030002@codeaurora.org>
 <20120822174945.GS9093@mudshark.cambridge.arm.com>
 <50351D80.6010600@codeaurora.org>
Message-ID: <20120822175810.GT9093@mudshark.cambridge.arm.com>

On Wed, Aug 22, 2012 at 06:57:20PM +0100, Stephen Boyd wrote:
> On 08/22/12 10:49, Will Deacon wrote:
> > On the topic of the timer stuff: Shinya/Stephen, did you have a chance to
> > look at the registration stuff that was proposed? I'm happy to push it if
> > people will actually use it.
> 
> Yes I have tested it on our internal trees and it looks good. I plan to
> send a patch to move MSM's timers over to it later this week so that we
> have at least two users upstream.

Awesome, I'll dust that series off at -rc3 then.

Will


From arnd at arndb.de  Wed Aug 22 14:41:29 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 18:41:29 +0000
Subject: [PATCHv3 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <alpine.LFD.2.02.1208221136180.1754@xanadu.home>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221519.12056.arnd@arndb.de>
 <alpine.LFD.2.02.1208221136180.1754@xanadu.home>
Message-ID: <201208221841.29645.arnd@arndb.de>

On Wednesday 22 August 2012, Nicolas Pitre wrote:
> On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > > 
> > > The ldrex/strex instructions are available on ARMv6.  It's only the d 
> > > variants (strexd/ldrexd) which are only available from ARMv6k.
> > 
> > Ok. How is the version below then? I haven't tested this one yet.
> 
> In fact, I think the b variants are ARMv6k+ as well.  Only the plain 
> (non b non d) variants are available on ARMv6.

Ok, third attempt then. This leaves ldrex for ARMv6 but marks
{st,ld}rex{b,h,d} as V6K specific (which includes ARMv7).

	Arnd

8<-----
From 6eab418c61c18393006f30d189e2f28d6e403040 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Thu, 16 Aug 2012 07:49:31 +0000
Subject: [PATCH] ARM: kprobes: make more tests conditional

The mls instruction is not available in ARMv6K or below, so we
should make the test conditional on at least ARMv7. ldrexd/strexd
are available in ARMv6K or ARMv7, which we can test by checking
the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.

/tmp/ccuMTZ8D.s: Assembler messages:
/tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
/tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
/tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Jon Medhurst <tixy at yxit.co.uk>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
Cc: Leif Lindholm <leif.lindholm at arm.com>
---
 arch/arm/kernel/kprobes-test-arm.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 38c1a3b..58dd6c3 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
 	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
 
+#if __LINUX_ARM_ARCH__ >= 7
 	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
 	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
 	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
+#endif
 	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
@@ -456,6 +458,7 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
 #if __LINUX_ARM_ARCH__ >= 6
 	TEST_UNSUPPORTED("ldrex	r2, [sp]")
+#ifdef CONFIG_CPU_32v6K
 	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
 	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
 	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
@@ -463,6 +466,7 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED("strexh	r0, r2, [sp]")
 	TEST_UNSUPPORTED("ldrexh	r2, [sp]")
 #endif
+#endif
 	TEST_GROUP("Extra load/store instructions")
 
 	TEST_RPR(  "strh	r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")
-- 
1.7.10





From sboyd at codeaurora.org  Wed Aug 22 14:56:33 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 11:56:33 -0700
Subject: [PATCHv2] ARM: Sort exception table at compile time
In-Reply-To: <1343683803-15507-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345661793-26468-1-git-send-email-sboyd@codeaurora.org>

Add the ARM machine identifier to sortextable and select the
config option so that we can sort the exception table at compile
time. sortextable relies on a section named __ex_table existing
in the vmlinux, but ARM's linker script places the exception
table in the data section. Give the exception table its own
section so that sortextable can find it.

This allows us to skip the sorting step during boot.

Cc: David Daney <david.daney at cavium.com>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

Changes since v1:
 * Moved exception table next to RO data for XIP builds

 arch/arm/Kconfig              |  1 +
 arch/arm/kernel/vmlinux.lds.S | 19 +++++++++----------
 scripts/sortextable.c         |  1 +
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..ccf830b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,6 +1,7 @@
 config ARM
 	bool
 	default y
+	select BUILDTIME_EXTABLE_SORT if MMU
 	select ARCH_HAVE_CUSTOM_GPIO_H
 	select HAVE_AOUT
 	select HAVE_DMA_API_DEBUG
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 36ff15b..b9f38e3 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -114,6 +114,15 @@ SECTIONS
 
 	RO_DATA(PAGE_SIZE)
 
+	. = ALIGN(4);
+	__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
+		__start___ex_table = .;
+#ifdef CONFIG_MMU
+		*(__ex_table)
+#endif
+		__stop___ex_table = .;
+	}
+
 #ifdef CONFIG_ARM_UNWIND
 	/*
 	 * Stack unwinding tables
@@ -220,16 +229,6 @@ SECTIONS
 		READ_MOSTLY_DATA(L1_CACHE_BYTES)
 
 		/*
-		 * The exception fixup table (might need resorting at runtime)
-		 */
-		. = ALIGN(4);
-		__start___ex_table = .;
-#ifdef CONFIG_MMU
-		*(__ex_table)
-#endif
-		__stop___ex_table = .;
-
-		/*
 		 * and the usual data section
 		 */
 		DATA_DATA
diff --git a/scripts/sortextable.c b/scripts/sortextable.c
index 6acf834..ba8f7c1 100644
--- a/scripts/sortextable.c
+++ b/scripts/sortextable.c
@@ -247,6 +247,7 @@ do_file(char const *const fname)
 	case EM_X86_64:
 		custom_sort = sort_x86_table;
 		break;
+	case EM_ARM:
 	case EM_S390:
 	case EM_MIPS:
 		break;
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 15:05:38 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 12:05:38 -0700
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <50297B34.5090504@codeaurora.org>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>
 <50297B34.5090504@codeaurora.org>
Message-ID: <50352D82.2050509@codeaurora.org>

On 08/13/12 15:09, Stephen Boyd wrote:
> On 08/07/12 23:52, Magnus Damm wrote:
>> So I finally managed to try this out on my KZM9D board. The SMP bring
>> up code continues to work as expected, so it seems that SGI0 can be
>> used instead of SGI1 on EMEV2. Let's just say that the boot protocol
>> implemented by the mask ROM is rather poorly documented. Anyway, to
>> test I used the following patch on top of linux git 42a579a.
>>
>> --- 0001/arch/arm/mach-shmobile/smp-emev2.c
>> +++ work/arch/arm/mach-shmobile/smp-emev2.c	2012-08-08 15:42:54.000000000 +0900
>> @@ -82,7 +82,7 @@ int __cpuinit emev2_boot_secondary(unsig
>>  	/* Tell ROM loader about our vector (in headsmp.S) */
>>  	emev2_set_boot_vector(__pa(shmobile_secondary_vector));
>>
>> -	gic_raise_softirq(cpumask_of(cpu), 1);
>> +	gic_raise_softirq(cpumask_of(cpu), 0);
>>  	return 0;
>>  }
>>
>> So if/where needed, please add my:
>>
>> Acked-by: Magnus Damm <damm at opensource.se>
>>
> Thanks Magnus, would you be able to merge this through the shmobile
> tree? Otherwise I can put it in the patch tracker.
>

Ok, I've put it in the patch tracker.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:10:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:10:44 +0100
Subject: [PATCH v3 1/9] ARM/ASoC: omap-mcbsp: Move OMAP2+ clock parenting
 code to ASoC driver
In-Reply-To: <1345124468-8876-2-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-2-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191043.GH7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:00PM +0300, Peter Ujfalusi wrote:
> Move the McBSP CLKS re-parenting code to ASoC driver from
> arch/arm/mach-omap2.
> The call fort the re-parenting has been already limited to OMAP2+ SoC in
> the ASoC driver. There is no longer need to have callback function for it.

Applied, thanks.
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From sboyd at codeaurora.org  Wed Aug 22 15:10:49 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 12:10:49 -0700
Subject: [PATCH] ARM: Fix XIP build due to PHYS_OFFSET definition moving
In-Reply-To: <5024AE2D.5050506@codeaurora.org>
References: <1343956994-27513-1-git-send-email-sboyd@codeaurora.org>
 <5024AE2D.5050506@codeaurora.org>
Message-ID: <50352EB9.4000402@codeaurora.org>

On 08/09/12 23:46, Stephen Boyd wrote:
> On 8/2/2012 6:23 PM, Stephen Boyd wrote:
>> During the p2v changes, the PHYS_OFFSET #define moved into a
>> !__ASSEMBLY__ section. This causes a XIP build to fail with
>>
>>  arch/arm/kernel/head.o: In function 'stext':
>>  arch/arm/kernel/head.S:146: undefined reference to 'PHYS_OFFSET'
>>
>> Momentarily leave the #ifndef __ASSEMBLY__ section so we can
>> define PHYS_OFFSET for all compilation units.
>>
>> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
>> ---
>>
>> I don't know if it's worth stable, seems that nobody has compiled XIP for
>> a year (back to 2.6.39 days?).
> Is this approach acceptable? Shall I put this in the patch tracker?
>

I'll take silence to mean "yes", so I'll put this in the patch tracker
unless someone objects.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:11:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:11:40 +0100
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191139.GI7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:01PM +0300, Peter Ujfalusi wrote:
> On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
> the FIFO for the audio stack.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

I applied this - Tony, from the thread it seemed you were OK even though
you didn't explicitly ack it?
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:12:05 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:12:05 +0100
Subject: [PATCH v3 3/9] ARM: OMAP: board-am3517evm: Configure McBSP1
 CLKR/FSR signal source
In-Reply-To: <1345124468-8876-4-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191205.GJ7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:02PM +0300, Peter Ujfalusi wrote:
> am3517evm board uses McBSP1 for audio with 4pin configuration.
> The CLKR/FSR signals need to be connected to CLKX/FSX pin of the SoC in
> this case.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:13:35 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:13:35 +0100
Subject: [PATCH v3 4/9] ASoC: am3517evm: Do not configure McBSP1 CLKR/FSR
 signal muxing
In-Reply-To: <1345124468-8876-5-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-5-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191335.GK7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:03PM +0300, Peter Ujfalusi wrote:
> The muxing is done at board level, no need to do it in the ASoC machine
> driver.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:15:06 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:15:06 +0100
Subject: [PATCH v3 5/9] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux
 configuration code
In-Reply-To: <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191506.GL7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:04PM +0300, Peter Ujfalusi wrote:
> Remove the feature to configure the CLKR/FSR mux on McBSP port with 6pin
> configuration.
> When moving to devicetree these callback can no longer be used in a clean
> way anymore.

Applied but this didn't quite apply cleanly, please check that it did so.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:15:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:15:34 +0100
Subject: [PATCH v3 6/9] ASoC: omap-mcbsp: Remove unused defines
In-Reply-To: <1345124468-8876-7-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-7-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191534.GM7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:05PM +0300, Peter Ujfalusi wrote:
> NUM_LINKS is no longer in use by the code.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:15:48 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:15:48 +0100
Subject: [PATCH v3 7/9] ASoC: omap-mcbsp: Remove cpu_is_omap* checks from
 the code
In-Reply-To: <1345124468-8876-8-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-8-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191547.GN7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:06PM +0300, Peter Ujfalusi wrote:
> We can use the has_ccr flag to replace the cpu_is_omap* checks.
> This provides future proof implementation and we do not need to update the
> code if new OMAP revision starts to use the McBSP driver.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:16:02 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:16:02 +0100
Subject: [PATCH v3 8/9] ARM: OMAP2+: McBSP: Do not create legacy devices
 when booting with DT data
In-Reply-To: <1345124468-8876-9-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-9-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191601.GO7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:07PM +0300, Peter Ujfalusi wrote:
> Only create the devices in a legacy way if we do not have the DT data.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:16:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:16:40 +0100
Subject: [PATCH v3 9/9] ASoC: omap-mcbsp: Add device tree bindings
In-Reply-To: <1345124468-8876-10-git-send-email-peter.ujfalusi@ti.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-10-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191640.GP7995@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 04:41:08PM +0300, Peter Ujfalusi wrote:
> Device tree support for McBSP modules on OMAP2+ SoC.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:18:35 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:18:35 +0100
Subject: [PATCH] ASoC: omap-mcbsp: Device tree binding documentation update
In-Reply-To: <1345559636-23370-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345559636-23370-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120822191835.GQ7995@opensource.wolfsonmicro.com>

On Tue, Aug 21, 2012 at 05:33:56PM +0300, Peter Ujfalusi wrote:
> To reflect the final devicetree node structure of McBSPs.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>

Applied, thanks.

> the initial OMAP McBSP DT structure was not able to describe the IP (and it's
> versions) correctly.
> The main issue was the sidetone block of McBSP2/3 on OMAP3.
> With this change in the DT description the OS can get the needed information
> about the IP.
> 
> The sidetone is still not supported when the Linux kernel is booted with DT
> since we still depend on hwmod to fill the resources.

I pasted this into the changelog to explain what's going on.
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From richard.purdie at linuxfoundation.org  Wed Aug 22 15:19:42 2012
From: richard.purdie at linuxfoundation.org (Richard Purdie)
Date: Wed, 22 Aug 2012 20:19:42 +0100
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <1345656424-31234-1-git-send-email-dromede@gmail.com>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
Message-ID: <1345663182.3907.134.camel@ted>

On Wed, 2012-08-22 at 19:27 +0200, dromede at gmail.com wrote:
> From: Marko Katic <dromede.gmail.com>
>
> I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It 
> hanged almost immediately after uncompressing the kernel. I tracked the
> problem down to a single line in arch/arm/common/sharpsl_param.c:
> 
> memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));
> 
> Commenting out the line makes the kernel boot just fine. This left me
> wondering whether sharpsl_param.c is actually needed. Here's a comment
> from sharpsl_param.c that describes what sharpsl_param.c actually does:

Sharp went to the trouble of saving these values into the hardware and
passing them into the drivers. They're basically used by the LCD
initialisation code from what I remember. I don't remember what the
risks are of incorrect values.

>  So sharpsl_save_param() is supposed to fill the sharpsl_param_info struct
>  with various parameters or fill some of the struct fields with -1. 
>  I found only four drivers that use some of these
>  parameters (only two parameters are used by these drivers, comadj and phadadj). 
>  These drivers are:
>  
>  drivers/video/backlight/corgi_lcd.c
>  drivers/video/backlight/locomolcd.c
>  drivers/video/backlight/tosa_bl.c
>  drivers/video/backlight/tosa_lcd.c
>  
>  These drivers also have default values when comadj or phadadj == -1.
>  I checked what values are actually contained in this struct in
>  earlier kernels. 3.2.24 kernel is the latest one i know of where
>  sharpsl_save_param() works properly. And it also has these fields initialised
>  to -1.

What values was it loading from the bootloader? Or are you saying that
it wasn't finding the bootloader information and therefore just using -1
for everything?
 
>  So it seems to me that sharpsl_param.c is redundant as it currently only  
>  serves to assign -1 to a few variables. And drivers that use these variables
>  then handle -1 with assigning default values.

Its not redundant, it sounds like its just broken at some point, at
least on the platform you tested and nobody has noticed/cared. The
better solution would be to fix it. Obviously its much easier to delete
the code though.

Cheers,

Richard





From koen at dominion.thruhere.net  Wed Aug 22 14:53:43 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Wed, 22 Aug 2012 20:53:43 +0200
Subject: [PATCH v2 2/3] mmc: davinci_mmc: convert to DMA engine API
In-Reply-To: <1345574589-24757-3-git-send-email-mporter@ti.com>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-3-git-send-email-mporter@ti.com>
Message-ID: <k139rl$gbm$2@ger.gmane.org>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Op 21-08-12 20:43, Matt Porter schreef:
> Removes use of the DaVinci EDMA private DMA API and replaces it with use
> of the DMA engine API.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>

Runtime tested on hawkboard with 3.6.0-rc2 with rootfs on SD and running
bonnie++ on it.

Tested-by: Koen Kooi <koen at dominion.thruhere.net>

> --- drivers/mmc/host/davinci_mmc.c |  271
> ++++++++++++---------------------------- 1 file changed, 82
> insertions(+), 189 deletions(-)
> 
> diff --git a/drivers/mmc/host/davinci_mmc.c
> b/drivers/mmc/host/davinci_mmc.c index 7cf6c62..c5e1eeb 100644 ---
> a/drivers/mmc/host/davinci_mmc.c +++ b/drivers/mmc/host/davinci_mmc.c @@
> -30,11 +30,12 @@ #include <linux/io.h> #include <linux/irq.h> #include
> <linux/delay.h> +#include <linux/dmaengine.h> #include
> <linux/dma-mapping.h> +#include <linux/edma.h> #include
> <linux/mmc/mmc.h>
> 
> #include <mach/mmc.h> -#include <mach/edma.h>
> 
> /* * Register Definitions @@ -200,21 +201,13 @@ struct mmc_davinci_host
> { u32 bytes_left;
> 
> u32 rxdma, txdma; +	struct dma_chan *dma_tx; +	struct dma_chan *dma_rx; 
> bool use_dma; bool do_dma; bool sdio_int; bool active_request;
> 
> -	/* Scatterlist DMA uses one or more parameter RAM entries: -	 * the
> main one (associated with rxdma or txdma) plus zero or -	 * more links.
> The entries for a given transfer differ only -	 * by memory buffer
> (address, length) and link field. -	 */ -	struct edmacc_param
> tx_template; -	struct edmacc_param	rx_template; -	unsigned		n_link; -	u32
> links[MAX_NR_SG - 1]; - /* For PIO we walk scatterlists one segment at a
> time. */ unsigned int		sg_len; struct scatterlist *sg; @@ -410,153
> +403,74 @@ static void mmc_davinci_start_command(struct mmc_davinci_host
> *host,
> 
> static void davinci_abort_dma(struct mmc_davinci_host *host) { -	int
> sync_dev; +	struct dma_chan *sync_dev;
> 
> if (host->data_dir == DAVINCI_MMC_DATADIR_READ) -		sync_dev =
> host->rxdma; +		sync_dev = host->dma_rx; else -		sync_dev = host->txdma; 
> - -	edma_stop(sync_dev); -	edma_clean_channel(sync_dev); -} - -static
> void -mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct
> mmc_data *data); - -static void mmc_davinci_dma_cb(unsigned channel, u16
> ch_status, void *data) -{ -	if (DMA_COMPLETE != ch_status) { -		struct
> mmc_davinci_host *host = data; - -		/* Currently means:  DMA Event
> Missed, or "null" transfer -		 * request was seen.  In the future, TC
> errors (like bad -		 * addresses) might be presented too. -		 */ -
> dev_warn(mmc_dev(host->mmc), "DMA %s error\n", -			(host->data->flags &
> MMC_DATA_WRITE) -				? "write" : "read"); -		host->data->error = -EIO; -
> mmc_davinci_xfer_done(host, host->data); -	} -} - -/* Set up tx or rx
> template, to be modified and updated later */ -static void __init
> mmc_davinci_dma_setup(struct mmc_davinci_host *host, -		bool tx, struct
> edmacc_param *template) -{ -	unsigned	sync_dev; -	const u16	acnt = 4; -
> const u16	bcnt = rw_threshold >> 2; -	const u16	ccnt = 0; -	u32		src_port
> = 0; -	u32		dst_port = 0; -	s16		src_bidx, dst_bidx; -	s16		src_cidx,
> dst_cidx; - -	/* -	 * A-B Sync transfer:  each DMA request is for one
> "frame" of -	 * rw_threshold bytes, broken into "acnt"-size chunks
> repeated -	 * "bcnt" times.  Each segment needs "ccnt" such frames;
> since -	 * we tell the block layer our mmc->max_seg_size limit, we can -
> * trust (later) that it's within bounds. -	 * -	 * The FIFOs are
> read/written in 4-byte chunks (acnt == 4) and -	 * EDMA will optimize
> memory operations to use larger bursts. -	 */ -	if (tx) { -		sync_dev =
> host->txdma; - -		/* src_prt, ccnt, and link to be set up later */ -
> src_bidx = acnt; -		src_cidx = acnt * bcnt; - -		dst_port =
> host->mem_res->start + DAVINCI_MMCDXR; -		dst_bidx = 0; -		dst_cidx = 0; 
> -	} else { -		sync_dev = host->rxdma; - -		src_port =
> host->mem_res->start + DAVINCI_MMCDRR; -		src_bidx = 0; -		src_cidx = 0; 
> - -		/* dst_prt, ccnt, and link to be set up later */ -		dst_bidx =
> acnt; -		dst_cidx = acnt * bcnt; -	} - -	/* -	 * We can't use FIFO mode
> for the FIFOs because MMC FIFO addresses -	 * are not 256-bit (32-byte)
> aligned.  So we use INCR, and the W8BIT -	 * parameter is ignored. -	 */ 
> -	edma_set_src(sync_dev, src_port, INCR, W8BIT); -
> edma_set_dest(sync_dev, dst_port, INCR, W8BIT); +		sync_dev =
> host->dma_tx;
> 
> -	edma_set_src_index(sync_dev, src_bidx, src_cidx); -
> edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); - -
> edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); - -
> edma_read_slot(sync_dev, template); - -	/* don't bother with irqs or
> chaining */ -	template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; +
> dmaengine_terminate_all(sync_dev); }
> 
> -static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 
> +static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 
> struct mmc_data *data) { -	struct edmacc_param	*template; -	int
> channel, slot; -	unsigned		link; -	struct scatterlist	*sg; -	unsigned
> sg_len; -	unsigned		bytes_left = host->bytes_left; -	const unsigned
> shift = ffs(rw_threshold) - 1; +	struct dma_chan *chan; +	struct
> dma_async_tx_descriptor *desc; +	int ret = 0;
> 
> if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { -		template =
> &host->tx_template; -		channel = host->txdma; +		struct dma_slave_config
> dma_tx_conf = { +			.direction = DMA_MEM_TO_DEV, +			.dst_addr =
> host->mem_res->start + DAVINCI_MMCDXR, +			.dst_addr_width =
> DMA_SLAVE_BUSWIDTH_4_BYTES, +			.dst_maxburst = +				rw_threshold /
> DMA_SLAVE_BUSWIDTH_4_BYTES, +		}; +		chan = host->dma_tx; +
> dmaengine_slave_config(host->dma_tx, &dma_tx_conf); + +		desc =
> dmaengine_prep_slave_sg(host->dma_tx, +				data->sg, +				host->sg_len, +
> DMA_MEM_TO_DEV, +				DMA_PREP_INTERRUPT | DMA_CTRL_ACK); +		if (!desc) { 
> +			dev_dbg(mmc_dev(host->mmc), +				"failed to allocate DMA TX
> descriptor"); +			ret = -1; +			goto out; +		} } else { -		template =
> &host->rx_template; -		channel = host->rxdma; -	} - -	/* We know sg_len
> and ccnt will never be out of range because -	 * we told the mmc layer
> which in turn tells the block layer -	 * to ensure that it only hands us
> one scatterlist segment -	 * per EDMA PARAM entry.  Update the PARAM -	 *
> entries needed for each segment of this scatterlist. -	 */ -	for (slot =
> channel, link = 0, sg = data->sg, sg_len = host->sg_len; -			sg_len-- !=
> 0 && bytes_left; -			sg = sg_next(sg), slot = host->links[link++]) { -
> u32		buf = sg_dma_address(sg); -		unsigned	count = sg_dma_len(sg); - -
> template->link_bcntrld = sg_len -				? (EDMA_CHAN_SLOT(host->links[link])
> << 5) -				: 0xffff; - -		if (count > bytes_left) -			count =
> bytes_left; -		bytes_left -= count; - -		if (host->data_dir ==
> DAVINCI_MMC_DATADIR_WRITE) -			template->src = buf; -		else -
> template->dst = buf; -		template->ccnt = count >> shift; - -
> edma_write_slot(slot, template); +		struct dma_slave_config dma_rx_conf =
> { +			.direction = DMA_DEV_TO_MEM, +			.src_addr = host->mem_res->start +
> DAVINCI_MMCDRR, +			.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, +
> .src_maxburst = +				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, +		}; +
> chan = host->dma_rx; +		dmaengine_slave_config(host->dma_rx,
> &dma_rx_conf); + +		desc = dmaengine_prep_slave_sg(host->dma_rx, +
> data->sg, +				host->sg_len, +				DMA_DEV_TO_MEM, +				DMA_PREP_INTERRUPT
> | DMA_CTRL_ACK); +		if (!desc) { +			dev_dbg(mmc_dev(host->mmc), +
> "failed to allocate DMA RX descriptor"); +			ret = -1; +			goto out; +
> } }
> 
> -	if (host->version == MMC_CTLR_VERSION_2) -		edma_clear_event(channel); 
> +	dmaengine_submit(desc); +	dma_async_issue_pending(chan);
> 
> -	edma_start(channel); +out: +	return ret; }
> 
> static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 
> @@ -564,6 +478,7 @@ static int mmc_davinci_start_dma_transfer(struct
> mmc_davinci_host *host, { int i; int mask = rw_threshold - 1; +	int ret =
> 0;
> 
> host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 
> ((data->flags & MMC_DATA_WRITE) @@ -583,70 +498,48 @@ static int
> mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, }
> 
> host->do_dma = 1; -	mmc_davinci_send_dma_request(host, data); +	ret =
> mmc_davinci_send_dma_request(host, data);
> 
> -	return 0; +	return ret; }
> 
> static void __init_or_module davinci_release_dma_channels(struct
> mmc_davinci_host *host) { -	unsigned	i; - if (!host->use_dma) return;
> 
> -	for (i = 0; i < host->n_link; i++) -		edma_free_slot(host->links[i]); 
> - -	edma_free_channel(host->txdma); -	edma_free_channel(host->rxdma); +
> dma_release_channel(host->dma_tx); +	dma_release_channel(host->dma_rx); 
> }
> 
> static int __init davinci_acquire_dma_channels(struct mmc_davinci_host
> *host) { -	u32 link_size; -	int r, i; - -	/* Acquire master DMA write
> channel */ -	r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb,
> host, -			EVENTQ_DEFAULT); -	if (r < 0) { -		dev_warn(mmc_dev(host->mmc),
> "alloc %s channel err %d\n", -				"tx", r); -		return r; -	} -
> mmc_davinci_dma_setup(host, true, &host->tx_template); - -	/* Acquire
> master DMA read channel */ -	r = edma_alloc_channel(host->rxdma,
> mmc_davinci_dma_cb, host, -			EVENTQ_DEFAULT); -	if (r < 0) { -
> dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", -				"rx", r); 
> -		goto free_master_write; +	int r; +	dma_cap_mask_t mask; + +
> dma_cap_zero(mask); +	dma_cap_set(DMA_SLAVE, mask); + +	host->dma_tx = +
> dma_request_channel(mask, edma_filter_fn, &host->txdma); +	if
> (!host->dma_tx) { +		dev_err(mmc_dev(host->mmc), "Can't get dma_tx
> channel\n"); +		return -ENODEV; } -	mmc_davinci_dma_setup(host, false,
> &host->rx_template);
> 
> -	/* Allocate parameter RAM slots, which will later be bound to a -	 *
> channel as needed to handle a scatterlist. -	 */ -	link_size =
> min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); -	for (i = 0; i <
> link_size; i++) { -		r = edma_alloc_slot(EDMA_CTLR(host->txdma),
> EDMA_SLOT_ANY); -		if (r < 0) { -			dev_dbg(mmc_dev(host->mmc), "dma
> PaRAM alloc --> %d\n", -				r); -			break; -		} -		host->links[i] = r; +
> host->dma_rx = +		dma_request_channel(mask, edma_filter_fn,
> &host->rxdma); +	if (!host->dma_rx) { +		dev_err(mmc_dev(host->mmc),
> "Can't get dma_rx channel\n"); +		r = -ENODEV; +		goto
> free_master_write; } -	host->n_link = i;
> 
> return 0;
> 
> free_master_write: -	edma_free_channel(host->txdma); +
> dma_release_channel(host->dma_tx);
> 
> return r; } @@ -1359,7 +1252,7 @@ static int __init
> davinci_mmcsd_probe(struct platform_device *pdev) * Each hw_seg uses one
> EDMA parameter RAM slot, always one * channel and then usually some
> linked slots. */ -	mmc->max_segs		= 1 + host->n_link; +	mmc->max_segs		=
> MAX_NR_SG;
> 
> /* EDMA limit per hw segment (one or two MBytes) */ mmc->max_seg_size	=
> MAX_CCNT * rw_threshold;
> 

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From broonie at opensource.wolfsonmicro.com  Wed Aug 22 15:27:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 22 Aug 2012 20:27:23 +0100
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
References: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120822192723.GS7995@opensource.wolfsonmicro.com>

On Mon, Aug 20, 2012 at 09:39:22AM -0300, Fabio Estevam wrote:
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.

Tested-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

in that it stops boot hanging on the board, though it still doesn't make
AC'97 come out of reset happily.  That's probably some separate issue
(pinmux perhaps?) though.
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From festevam at gmail.com  Wed Aug 22 15:38:26 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 22 Aug 2012 16:38:26 -0300
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <20120822192723.GS7995@opensource.wolfsonmicro.com>
References: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
 <20120822192723.GS7995@opensource.wolfsonmicro.com>
Message-ID: <CAOMZO5B2feJzbqEQgJm_gKDcZPSKuckXWj=s+b+5R39Tnv7-kw@mail.gmail.com>

On Wed, Aug 22, 2012 at 4:27 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:

> Tested-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
>
> in that it stops boot hanging on the board, though it still doesn't make
> AC'97 come out of reset happily.  That's probably some separate issue
> (pinmux perhaps?) though.

Yes, looks like a separate issue.

Did imx_ssi_probe go successfully? What is the error log you are getting?

Regards,

Fabio Estevam


From nicolas.pitre at linaro.org  Wed Aug 22 15:43:57 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 22 Aug 2012 15:43:57 -0400 (EDT)
Subject: [PATCHv3 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <201208221841.29645.arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221519.12056.arnd@arndb.de>
 <alpine.LFD.2.02.1208221136180.1754@xanadu.home>
 <201208221841.29645.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208221543240.1754@xanadu.home>

On Wed, 22 Aug 2012, Arnd Bergmann wrote:

> On Wednesday 22 August 2012, Nicolas Pitre wrote:
> > On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > > > 
> > > > The ldrex/strex instructions are available on ARMv6.  It's only the d 
> > > > variants (strexd/ldrexd) which are only available from ARMv6k.
> > > 
> > > Ok. How is the version below then? I haven't tested this one yet.
> > 
> > In fact, I think the b variants are ARMv6k+ as well.  Only the plain 
> > (non b non d) variants are available on ARMv6.
> 
> Ok, third attempt then. This leaves ldrex for ARMv6 but marks
> {st,ld}rex{b,h,d} as V6K specific (which includes ARMv7).
> 
> 	Arnd
> 
> 8<-----
> From 6eab418c61c18393006f30d189e2f28d6e403040 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Thu, 16 Aug 2012 07:49:31 +0000
> Subject: [PATCH] ARM: kprobes: make more tests conditional
> 
> The mls instruction is not available in ARMv6K or below, so we
> should make the test conditional on at least ARMv7. ldrexd/strexd
> are available in ARMv6K or ARMv7, which we can test by checking
> the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.
> 
> /tmp/ccuMTZ8D.s: Assembler messages:
> /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
> /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
> /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Jon Medhurst <tixy at yxit.co.uk>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
> Cc: Leif Lindholm <leif.lindholm at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/kernel/kprobes-test-arm.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
> index 38c1a3b..58dd6c3 100644
> --- a/arch/arm/kernel/kprobes-test-arm.c
> +++ b/arch/arm/kernel/kprobes-test-arm.c
> @@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> +#endif
>  	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
> @@ -456,6 +458,7 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
>  #if __LINUX_ARM_ARCH__ >= 6
>  	TEST_UNSUPPORTED("ldrex	r2, [sp]")
> +#ifdef CONFIG_CPU_32v6K
>  	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
>  	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
>  	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
> @@ -463,6 +466,7 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED("strexh	r0, r2, [sp]")
>  	TEST_UNSUPPORTED("ldrexh	r2, [sp]")
>  #endif
> +#endif
>  	TEST_GROUP("Extra load/store instructions")
>  
>  	TEST_RPR(  "strh	r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")
> -- 
> 1.7.10
> 
> 
> 


From swarren at wwwdotorg.org  Wed Aug 22 15:44:09 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 13:44:09 -0600
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <50353689.6060404@wwwdotorg.org>

On 08/22/2012 06:53 AM, Arnd Bergmann wrote:
> I've created this series some time ago, and updated it now to
> v3.6-rc1. The idea is to get us a big step closer to the
> single zImage kernel across multiple ARM platforms by
> untangling the duplicate header file names.
> 
> There are two branches available in the arm-soc tree:
> 
> 1. This series,
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
>    This just moves header files around and changes most of the
>    files including them. There are a few remaining drivers
>    and platform files that keep including a generic file name
>    like <mach/uncompress.h>....

FWIW, I merged this with next-20120820, ignored all the non-Tegra
conflicts, and it built and ran just fine on Tegra. There were a lot of
conflicts overall though...

...
> I would like to get the first series merged in v3.7 if we can agree
> on the general approach. So far, feedback in Linaro internal
> meetings has been very positive, but Russell had concerns when
> we first discussed it a few months ago.
> 
> A patch set this large means a lot of churn, and there are a few
> ways we could deal with this:
> 
> a) Put the branch into linux-next now, and have everyone who
> encounters conflicts pull it into their own branch to resolve
> the conflicts. This can be a lot of work, and it means we
> cannot rebase this branch any more.

I did a very quick test of rebasing all the Tegra branches onto this,
and it worked out to be very easy; very few conflicts and mostly just
files deleted in the Tegra tree this time around. One of the Tegra
branches depends on v3.6-rc2 in order to pick up some changes that
conflict with changes made there. If we convert to dmaengine in 3.7,
then we'll probably depend on a later v3.6-rc for a dmaengine driver
bug-fix. Does it make sense to rebase this mach-headers onto a later
v3.6-rc? I suppose I could branch from v3.6-rc2, merge in mach-headers,
and then build on that if needed.

> b) Involve Linus Torvalds in the process and get him to
> take the series at the end of the v3.7 merge window, after
> rebasing it on top of all the other branches he merged.
> This means it happens pretty much ad-hoc and there is little
> testing on the patches that actually get merged.

Given the number of merge conflicts this has with next-20120820, that
sounds like a lot of work you need to do at the end of the merge window,
but I suppose if it's mostly scripted, it wouldn't be too hard to
recreate the series in a short time.


From swarren at wwwdotorg.org  Wed Aug 22 15:52:45 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 13:52:45 -0600
Subject: Can one  set GPIO direction in pinmux definition?
In-Reply-To: <5034FCB2.5040709@grid-net.com>
References: <5034FCB2.5040709@grid-net.com>
Message-ID: <5035388D.2060909@wwwdotorg.org>

On 08/22/2012 09:37 AM, Subodh Nijsure wrote:
> 
> For a MX28 based hardware I am working with I need to use AUART4
> 
> I need to configure this AUART4 as uart only when necessary and at all
> other times pins associated with AUART4 need to be configured as inputs.

Out of curiosity, why?

BTW, you didn't CC any of the IMX maintainers, so it's likely they won't
see your question. I've CC'd LinusW, Shawn, and Dong.

> I am using following DT definitions to setup AUART4 mux  but can't
> figure out how to setup pin direction via DT, can it be done or I need
> to do it in C code?
> 
>         apb at 80000000 {
>                 apbh at 80000000 {
>                                 auart4_pins_a: auart4 at 0 {
>                                         reg = <0>;
>                                         fsl,pinmux-ids = <
>                                                 0x3142 /*
> MX28_PAD_SAIF0_MCLK__AUART4_CTS */
>                                                 0x3152 /*
> MX28_PAD_SAIF0_LRCLK__AUART4_RTS */
>                                                 0x3162 /*
> MX28_PAD_SAIF0_BITCLK__AUART4_RX */
>                                                 0x3172 /*
> MX28_PAD_SAIF0_SDATA0__AUART4_TX */
>                                         >;
>                                         fsl,drive-strength = <0>;
>                                         fsl,voltage = <1>;
>                                         fsl,pull-up = <0>;
>                                 };
>                                 auart4_highz_pins: auart4-gpio at 0 {
>                                         reg = <0>;
>                                         fsl,pinmux-ids = <
>                                                 0x3143 /*
> MX28_PAD_SAIF0_MCLK__GPIO_3_20 */
>                                                 0x3153 /*
> MX28_PAD_SAIF0_LRCLK__GPIO_3_21 */
>                                                 0x3163 /*
> MX28_PAD_SAIF0_BITCLK__GPIO_3_22 */
>                                                 0x3173 /*
> MX28_PAD_SAIF0_SDATA0__GPIO_3_23 */
>                                         >;
>                                         fsl,drive-strength = <0>;
>                                         fsl,voltage = <1>;
>                                         fsl,pull-up = <0>;
>                                 };
>                  };
>           };

I don't know IMX HW, but where is highz controlled? On other SoCs I'm
familiar with, when a pad is configured as a GPIO, the highz state is
controlled by the GPIO module, so there's nothing pinmux can do about
it. Even if the pinmux HW does control highz, gpio_direction_*() are
still meant to communicate with the pinctrl driver to implement this, so
overriding it through the pinctrl configuration seems like a bad thing.

So I think your UART driver would have to request the GPIOs, and set
them as inputs. So, I guess your UART node below would need a property
listing the GPIOs to do this to.

>                 apbx at 80040000 {
>                         auart4: serial at 80072000 {
>                                 pinctrl-names = "default", "auart";
>                                 pinctrl-0 = <&auart4_highz_pins>;
>                                 pinctrl-1 = <&auart4_pins_a>;
>                                 status = "okay";
>                         };
>                };



From arnd at arndb.de  Wed Aug 22 16:04:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 22 Aug 2012 20:04:05 +0000
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <50353689.6060404@wwwdotorg.org>
References: <201208221253.07278.arnd@arndb.de> <50353689.6060404@wwwdotorg.org>
Message-ID: <201208222004.06179.arnd@arndb.de>

On Wednesday 22 August 2012, Stephen Warren wrote:
> On 08/22/2012 06:53 AM, Arnd Bergmann wrote:
> > I've created this series some time ago, and updated it now to
> > v3.6-rc1. The idea is to get us a big step closer to the
> > single zImage kernel across multiple ARM platforms by
> > untangling the duplicate header file names.
> > 
> > There are two branches available in the arm-soc tree:
> > 
> > 1. This series,
> >    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
> >    This just moves header files around and changes most of the
> >    files including them. There are a few remaining drivers
> >    and platform files that keep including a generic file name
> >    like <mach/uncompress.h>....
> 
> FWIW, I merged this with next-20120820, ignored all the non-Tegra
> conflicts, and it built and ran just fine on Tegra. There were a lot of
> conflicts overall though...

Ah, very cool, thanks for the testing. If you want, you can also
try to merge in the testing/randconfig branch and see how far
you get with enabling tegra in there. That does however require
that you also use the COMMON_CLK and SPARSE_IRQ options, and I'm
not sure what your status on those is.

> > I would like to get the first series merged in v3.7 if we can agree
> > on the general approach. So far, feedback in Linaro internal
> > meetings has been very positive, but Russell had concerns when
> > we first discussed it a few months ago.
> > 
> > A patch set this large means a lot of churn, and there are a few
> > ways we could deal with this:
> > 
> > a) Put the branch into linux-next now, and have everyone who
> > encounters conflicts pull it into their own branch to resolve
> > the conflicts. This can be a lot of work, and it means we
> > cannot rebase this branch any more.
> 
> I did a very quick test of rebasing all the Tegra branches onto this,
> and it worked out to be very easy; very few conflicts and mostly just
> files deleted in the Tegra tree this time around. One of the Tegra
> branches depends on v3.6-rc2 in order to pick up some changes that
> conflict with changes made there. If we convert to dmaengine in 3.7,
> then we'll probably depend on a later v3.6-rc for a dmaengine driver
> bug-fix. Does it make sense to rebase this mach-headers onto a later
> v3.6-rc? I suppose I could branch from v3.6-rc2, merge in mach-headers,
> and then build on that if needed.

It's only problematic if multiple people merge the same branch with
later -rc releases and fix the same conflicts in different ways.
If we get such conflicts, it would probably be best if I merge a
new -rc into my branch and let other people base on my merge
commit.

> > b) Involve Linus Torvalds in the process and get him to
> > take the series at the end of the v3.7 merge window, after
> > rebasing it on top of all the other branches he merged.
> > This means it happens pretty much ad-hoc and there is little
> > testing on the patches that actually get merged.
> 
> Given the number of merge conflicts this has with next-20120820, that
> sounds like a lot of work you need to do at the end of the merge window,
> but I suppose if it's mostly scripted, it wouldn't be too hard to
> recreate the series in a short time.

Yes, I've done it a few times.

	Arnd


From marex at denx.de  Wed Aug 22 16:38:35 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 22 Aug 2012 22:38:35 +0200
Subject: [PATCH] spi/mxs: Make the SPI block clock speed configurable via DT
Message-ID: <1345667915-26189-1-git-send-email-marex@denx.de>

Add "clock-frequency" property, which allows configuring the SPI block's
base speed.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 Documentation/devicetree/bindings/spi/mxs-spi.txt |    4 ++++
 drivers/spi/spi-mxs.c                             |   21 +++++++++++++++------
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt
index c36296f..e2e1395 100644
--- a/Documentation/devicetree/bindings/spi/mxs-spi.txt
+++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt
@@ -6,6 +6,10 @@ Required properties:
 - interrupts: Should contain SSP interrupts (error irq first, dma irq second)
 - fsl,ssp-dma-channel: APBX DMA channel for the SSP
 
+Optional properties:
+- clock-frequency : Input clock frequency to the SPI block in Hz.
+		    Default is 160000000 Hz.
+
 Example:
 
 ssp0: ssp at 80010000 {
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 130a436..331f600 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -485,10 +485,17 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	struct pinctrl *pinctrl;
 	struct clk *clk;
 	void __iomem *base;
-	int devid, dma_channel;
+	int devid, dma_channel, clk_freq;
 	int ret = 0, irq_err, irq_dma;
 	dma_cap_mask_t mask;
 
+	/*
+	 * Default clock speed for the SPI core. 160MHz seems to
+	 * work reasonably well with most SPI flashes, so use this
+	 * as a default. Override with "clock-frequency" DT prop.
+	 */
+	const int clk_freq_default = 160000000;
+
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irq_err = platform_get_irq(pdev, 0);
 	irq_dma = platform_get_irq(pdev, 1);
@@ -520,12 +527,18 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 				"Failed to get DMA channel\n");
 			return -EINVAL;
 		}
+
+		ret = of_property_read_u32(np, "clock-frequency",
+					   &clk_freq);
+		if (ret)
+			clk_freq = clk_freq_default;
 	} else {
 		dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 		if (!dmares)
 			return -EINVAL;
 		devid = pdev->id_entry->driver_data;
 		dma_channel = dmares->start;
+		clk_freq = clk_freq_default;
 	}
 
 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
@@ -561,12 +574,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 		goto out_master_free;
 	}
 
-	/*
-	 * Crank up the clock to 120MHz, this will be further divided onto a
-	 * proper speed.
-	 */
 	clk_prepare_enable(ssp->clk);
-	clk_set_rate(ssp->clk, 120 * 1000 * 1000);
+	clk_set_rate(ssp->clk, clk_freq);
 	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
 
 	stmp_reset_block(ssp->base);
-- 
1.7.10.4



From swarren at wwwdotorg.org  Wed Aug 22 16:43:07 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 14:43:07 -0600
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <5035445B.6000500@wwwdotorg.org>

On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This patch adds a pinctrl driver core for Marvell SoCs plus DT
> binding documentation. This core driver will be used by SoC family
> specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt

This, and all the other binding documents in this series, all look sane
to me.

> +++ b/drivers/pinctrl/pinctrl-mvebu.c

> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,


> +	of_property_for_each_string(np, "marvell,pins", prop, group) {
> +		struct mvebu_pinctrl_group *grp =
> +			mvebu_pinctrl_find_group_by_name(pctl, group);
> +
> +		if (!grp) {
> +			dev_err(pctl->dev, "unknown pin %s", group);
> +			continue;
> +		}
> +
> +		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
> +			dev_err(pctl->dev, "unsupported function %s on pin %s",
> +				function, group);
> +			continue;
> +		}

The error-checking here isn't strictly necessary; the pinctrl core will
error-check all the names if/when the map entries are used. So, you
could probably get away with just assigning the pin/function names
directly into (*map) and hence remove some code here. Still, it's not a
big deal either way.

> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,

> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
> +					struct mvebu_pinctrl *pctl)

I don't understand what those two functions do, or a good chunk of
probe(). It seems like they're setting up the ability to get/set pin
configrations in addition to pin muxing, although if that's so, it seems
odd that none of the binding documents specify any way of controlling
pin configuration from device tree. Are you expecting drivers to call
APIs such as pin_config_set() directly, rather than controlling pin
config through DT?



From swarren at wwwdotorg.org  Wed Aug 22 16:45:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 14:45:18 -0600
Subject: [PATCH v2 7/9] ARM: mvebu: Add pinctrl support to Armada XP SoCs
In-Reply-To: <1345623750-10645-8-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-8-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <503544DE.20003@wwwdotorg.org>

On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada XP SoCs.
> 
> Until now, the device tree representation considered the Armada XP as
> a single SoC. But in fact, there are three different SoCs in the
> Armada XP families, with different number of CPU cores, different
> number of Ethernet interfaces... and different number of muxable pins
> or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
> the three SoCs of the Armada XP family. The current armada-xp-db.dts
> evaluation board uses the MV78460 variant of the SoC.

> diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi

> +/include/ "armada-xp.dtsi"
> +
> +/ {
> +	model = "Marvell Armada XP family SoC";
> +	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

Since each of these files is specifically for a different SoC, I'd
expect them all to say something different in the model property?

> diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi

> +	model = "Marvell Armada XP family SoC";
> +	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

> diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi

> +	model = "Marvell Armada XP family SoC";
> +	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";



From swarren at wwwdotorg.org  Wed Aug 22 16:46:19 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 14:46:19 -0600
Subject: [PATCH v2 8/9] ARM: mvebu: Add pinctrl support to Armada 370 SoC
In-Reply-To: <1345623750-10645-9-git-send-email-sebastian.hesselbarth@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-9-git-send-email-sebastian.hesselbarth@gmail.com>
Message-ID: <5035451B.3020708@wwwdotorg.org>

On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
> This commits adds the necessary device tree information to define the
> compatible property for the pinctrl driver instance of Armada 370 SoC.

> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi

> +
> +                pinctrl at d0018000 {
> +			        compatible = "marvell,mv88f6710-pinctrl";
> +	        };

The indentation here is a mix of spaces and TABs.


From marex at denx.de  Wed Aug 22 16:57:45 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 22 Aug 2012 22:57:45 +0200
Subject: [PATCH] mxs/spi: Fix misuse of init_completion
Message-ID: <1345669065-17750-1-git-send-email-marex@denx.de>

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/spi/spi-mxs.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 331f600..c965cc6 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -230,7 +230,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 		return -EINVAL;
 	}
 
-	init_completion(&spi->c);
+	INIT_COMPLETION(spi->c);
 
 	if (*first)
 		pio |= BM_SSP_CTRL0_LOCK_CS;
@@ -560,6 +560,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ssp->devid = devid;
 	ssp->dma_channel = dma_channel;
 
+	init_completion(&spi->c);
+
 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 			       DRIVER_NAME, ssp);
 	if (ret)
-- 
1.7.10.4



From cjb at laptop.org  Wed Aug 22 17:07:11 2012
From: cjb at laptop.org (Chris Ball)
Date: Wed, 22 Aug 2012 17:07:11 -0400
Subject: [PATCH] mxs/spi: Fix misuse of init_completion
In-Reply-To: <1345669065-17750-1-git-send-email-marex@denx.de> (Marek Vasut's
 message of "Wed, 22 Aug 2012 22:57:45 +0200")
References: <1345669065-17750-1-git-send-email-marex@denx.de>
Message-ID: <87ehmyzlds.fsf@octavius.laptop.org>

Hi,

On Wed, Aug 22 2012, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  drivers/spi/spi-mxs.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
> index 331f600..c965cc6 100644
> --- a/drivers/spi/spi-mxs.c
> +++ b/drivers/spi/spi-mxs.c
> @@ -230,7 +230,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
>  		return -EINVAL;
>  	}
>  
> -	init_completion(&spi->c);
> +	INIT_COMPLETION(spi->c);
>  
>  	if (*first)
>  		pio |= BM_SSP_CTRL0_LOCK_CS;
> @@ -560,6 +560,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
>  	ssp->devid = devid;
>  	ssp->dma_channel = dma_channel;
>  
> +	init_completion(&spi->c);
> +
>  	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
>  			       DRIVER_NAME, ssp);
>  	if (ret)

Please be more specific with commit messages -- is there an observed
symptom that this fixes?  Does the patch need to go to stable@, too?

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From swarren at wwwdotorg.org  Wed Aug 22 17:07:21 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 15:07:21 -0600
Subject: [PATCHv3 7/9] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <1345582058-2291-8-git-send-email-linux@prisktech.co.nz>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-8-git-send-email-linux@prisktech.co.nz>
Message-ID: <50354A09.7070507@wwwdotorg.org>

On 08/21/2012 02:47 PM, Tony Prisk wrote:
> Bindings for gpio, interrupt controller, power management controller,
> timer, realtime clock, serial uart, ehci and uhci controllers and
> framebuffer controllers used on the arch-vt8500 platform.
> 
> Framebuffer binding also specifies a 'display' node which is required
> for determining the lcd panel data.

> diff --git a/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt

> +- #gpio-cells : should be <3>.
> +	1) bank
> +	2) pin number
> +	3) flags

Should this enumerate what legal values are for flags, or point at a
standard document that does?

> diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt

> +	uart at d8210000 {
> +		compatible = "via,vt8500-uart";
> +		reg = <0xd8210000 0x1040>;
> +		interrupts = <47>;
> +	};

How does the UART know what frequency its clock input is, in order to
calculate dividers? Should there be a clocks property to link to the
input clock, so the rate can be queried? If so, a reference to the
common clock binding, plus a specification of which clocks must be
listed in the clock property should be included here.

> diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt

> +VIA VT8500 Display
> +-----------------------------------------------------
> +Required properties:
> +- xres : lcd panel horizontal resolution
> +- yres : lcd panel vertical resolution
> +- left-margin,
> +- right-margin,
> +- hsync-len: lcd panel horizontal timings in pixels
> +- upper-margin,
> +- lower-margin,
> +- vsync-len: lcd panel verticals timings in pixels
> +- bpp: lcd panel bit-depth.
> +	<16> for RGB565, <32> for RGB888

Shouldn't this reference Sascha Hauer's binding document (although I
suppose it isn't checked in yet), and just document the additions? I
wonder if this binding should be written assuming Sascha's binding doc
will be checked in?


From magnus.damm at gmail.com  Wed Aug 22 17:23:33 2012
From: magnus.damm at gmail.com (Magnus Damm)
Date: Thu, 23 Aug 2012 06:23:33 +0900
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <50352D82.2050509@codeaurora.org>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>
 <50297B34.5090504@codeaurora.org> <50352D82.2050509@codeaurora.org>
Message-ID: <CANqRtoTi_4Te-Nvbj6eq6Jwj4UJ4OTdA9e+H_qtOAToZVmLL+A@mail.gmail.com>

On Thu, Aug 23, 2012 at 4:05 AM, Stephen Boyd <sboyd at codeaurora.org> wrote:
> On 08/13/12 15:09, Stephen Boyd wrote:
>> On 08/07/12 23:52, Magnus Damm wrote:
>>> So I finally managed to try this out on my KZM9D board. The SMP bring
>>> up code continues to work as expected, so it seems that SGI0 can be
>>> used instead of SGI1 on EMEV2. Let's just say that the boot protocol
>>> implemented by the mask ROM is rather poorly documented. Anyway, to
>>> test I used the following patch on top of linux git 42a579a.
>>>
>>> --- 0001/arch/arm/mach-shmobile/smp-emev2.c
>>> +++ work/arch/arm/mach-shmobile/smp-emev2.c  2012-08-08 15:42:54.000000000 +0900
>>> @@ -82,7 +82,7 @@ int __cpuinit emev2_boot_secondary(unsig
>>>      /* Tell ROM loader about our vector (in headsmp.S) */
>>>      emev2_set_boot_vector(__pa(shmobile_secondary_vector));
>>>
>>> -    gic_raise_softirq(cpumask_of(cpu), 1);
>>> +    gic_raise_softirq(cpumask_of(cpu), 0);
>>>      return 0;
>>>  }
>>>
>>> So if/where needed, please add my:
>>>
>>> Acked-by: Magnus Damm <damm at opensource.se>
>>>
>> Thanks Magnus, would you be able to merge this through the shmobile
>> tree? Otherwise I can put it in the patch tracker.
>>
>
> Ok, I've put it in the patch tracker.

Oh, thanks a lot! We're currently in the middle of rearranging our
kernel repository handling so things move a bit slower than usual...

Thanks for your help!

/ magnus


From marek.vasut at gmail.com  Wed Aug 22 17:30:37 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 22 Aug 2012 23:30:37 +0200
Subject: [PATCH] mxs/spi: Fix misuse of init_completion
In-Reply-To: <87ehmyzlds.fsf@octavius.laptop.org>
References: <1345669065-17750-1-git-send-email-marex@denx.de>
 <87ehmyzlds.fsf@octavius.laptop.org>
Message-ID: <201208222330.37925.marex@denx.de>

Dear Chris Ball,

> Hi,
> 
> On Wed, Aug 22 2012, Marek Vasut wrote:
> > Signed-off-by: Marek Vasut <marex at denx.de>
> > Cc: Chris Ball <cjb at laptop.org>
> > Cc: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> > Cc: Fabio Estevam <fabio.estevam at freescale.com>
> > ---
> > 
> >  drivers/spi/spi-mxs.c |    4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
> > index 331f600..c965cc6 100644
> > --- a/drivers/spi/spi-mxs.c
> > +++ b/drivers/spi/spi-mxs.c
> > @@ -230,7 +230,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int
> > cs,
> > 
> >  		return -EINVAL;
> >  	
> >  	}
> > 
> > -	init_completion(&spi->c);
> > +	INIT_COMPLETION(spi->c);
> > 
> >  	if (*first)
> >  	
> >  		pio |= BM_SSP_CTRL0_LOCK_CS;
> > 
> > @@ -560,6 +560,8 @@ static int __devinit mxs_spi_probe(struct
> > platform_device *pdev)
> > 
> >  	ssp->devid = devid;
> >  	ssp->dma_channel = dma_channel;
> > 
> > +	init_completion(&spi->c);
> > +
> > 
> >  	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
> >  	
> >  			       DRIVER_NAME, ssp);
> >  	
> >  	if (ret)
> 
> Please be more specific with commit messages

I kind of expected this change was pretty obvious.

> is there an observed symptom that this fixes?

None. I noticed this misuse, so I fixed it.

> Does the patch need to go to stable@, too?

No, this driver is in -next currently.

> Thanks,
> 
> - Chris.

Best regards,
Marek Vasut


From linux at prisktech.co.nz  Wed Aug 22 17:32:35 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 09:32:35 +1200
Subject: [PATCHv3 7/9] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <50354A09.7070507@wwwdotorg.org>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <1345582058-2291-8-git-send-email-linux@prisktech.co.nz>
 <50354A09.7070507@wwwdotorg.org>
Message-ID: <1345671155.2090.8.camel@gitbox>

On Wed, 2012-08-22 at 15:07 -0600, Stephen Warren wrote:
> On 08/21/2012 02:47 PM, Tony Prisk wrote:
> > Bindings for gpio, interrupt controller, power management controller,
> > timer, realtime clock, serial uart, ehci and uhci controllers and
> > framebuffer controllers used on the arch-vt8500 platform.
> > 
> > Framebuffer binding also specifies a 'display' node which is required
> > for determining the lcd panel data.
> 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio_vt8500.txt
> 
> > +- #gpio-cells : should be <3>.
> > +	1) bank
> > +	2) pin number
> > +	3) flags
> 
> Should this enumerate what legal values are for flags, or point at a
> standard document that does?

There currently are no supported flags - guess this was an oversight.
I'll take a look if there are any that we might require in the future
and implement them otherwise I'll drop the flags reference.

> 
> > diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
> 
> > +	uart at d8210000 {
> > +		compatible = "via,vt8500-uart";
> > +		reg = <0xd8210000 0x1040>;
> > +		interrupts = <47>;
> > +	};
> 
> How does the UART know what frequency its clock input is, in order to
> calculate dividers? Should there be a clocks property to link to the
> input clock, so the rate can be queried? If so, a reference to the
> common clock binding, plus a specification of which clocks must be
> listed in the clock property should be included here.
> 

I didn't revisit the code that had already been posted in v1/v2 when I
added the common clock code and there was no clock handling code at that
point. The uart's are all clocked via a clkgen that outputs 24Mhz and
this was hardcoded in the driver.
I will correct this and add the appropriate device tree entries and
documentation.

> > diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
> 
> > +VIA VT8500 Display
> > +-----------------------------------------------------
> > +Required properties:
> > +- xres : lcd panel horizontal resolution
> > +- yres : lcd panel vertical resolution
> > +- left-margin,
> > +- right-margin,
> > +- hsync-len: lcd panel horizontal timings in pixels
> > +- upper-margin,
> > +- lower-margin,
> > +- vsync-len: lcd panel verticals timings in pixels
> > +- bpp: lcd panel bit-depth.
> > +	<16> for RGB565, <32> for RGB888
> 
> Shouldn't this reference Sascha Hauer's binding document (although I
> suppose it isn't checked in yet), and just document the additions? I
> wonder if this binding should be written assuming Sascha's binding doc
> will be checked in?

I haven't seen Sascha's binding yet - I'm not even sure its been agreed
upon but it does seem to be the most likely candidate so far. Hopefully
it will get accepted in this window, and I will have time to do exactly
as you commented, which was the plan from the start. This binding was
based on the most current one I had seen suggested at the time.


Given the additional comments for this patch set, and the required
changes I'll hold off posting v4 until everything is tidied up.

Regards

Tony Prisk



From linux at arm.linux.org.uk  Wed Aug 22 17:43:23 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 22 Aug 2012 22:43:23 +0100
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more
 mach-*/*.h includes
In-Reply-To: <201208221301.19439.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
Message-ID: <20120822214323.GA12255@n2100.arm.linux.org.uk>

On Wed, Aug 22, 2012 at 01:01:19PM +0000, Arnd Bergmann wrote:
> These are lots of device drivers that include machine
> specific header files from ARM platforms and that are
> not easily scriptable. The changes have been found through
> manual inspection and should cause no visible changes
> because of the build script that maps the old names to the
> new ones.

And you end up missing a bunch of drivers in the process, such as the
sa1100 RTC driver which is shared between sa11x0 and PXA.  I wonder
how many of the Samsung platforms get broken by this as well...

In any case, what we _should_ be doing here as well is moving the headers
included by drivers for platform data out of the arch/arm/mach/ subtrees
and into include/linux/platform_data.  That will substantially reduce the
amount of mach/ headers to deal with.

Where I want this to get to is not a persistence of the existing crappy
situation where platforms stuff platform data definitions into arch/arm,
but instead put them in the right place.  That means providing them with
a good reason why the existing solution won't work, and not allowing
mach/ includes in drivers is a very good way to achieve that.


From dromede at gmail.com  Wed Aug 22 17:48:30 2012
From: dromede at gmail.com (=?UTF-8?B?TWFya28gS2F0acSH?=)
Date: Wed, 22 Aug 2012 23:48:30 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <1345663182.3907.134.camel@ted>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
 <1345663182.3907.134.camel@ted>
Message-ID: <CAHod+Ge_xVNmm7Y8vn+99mXW0Q_X1tgqMGLUCgMykWja8OikGg@mail.gmail.com>

On Wed, Aug 22, 2012 at 9:19 PM, Richard Purdie
<richard.purdie at linuxfoundation.org> wrote:
>
> On Wed, 2012-08-22 at 19:27 +0200, dromede at gmail.com wrote:
> > From: Marko Katic <dromede.gmail.com>
> >
> > I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It
> > hanged almost immediately after uncompressing the kernel. I tracked the
> > problem down to a single line in arch/arm/common/sharpsl_param.c:
> >
> > memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct
> > sharpsl_param_info));
> >
> > Commenting out the line makes the kernel boot just fine. This left me
> > wondering whether sharpsl_param.c is actually needed. Here's a comment
> > from sharpsl_param.c that describes what sharpsl_param.c actually does:
>
> Sharp went to the trouble of saving these values into the hardware and
> passing them into the drivers. They're basically used by the LCD
> initialisation code from what I remember. I don't remember what the
> risks are of incorrect values.
>
> >  So sharpsl_save_param() is supposed to fill the sharpsl_param_info
> > struct
> >  with various parameters or fill some of the struct fields with -1.
> >  I found only four drivers that use some of these
> >  parameters (only two parameters are used by these drivers, comadj and
> > phadadj).
> >  These drivers are:
> >
> >  drivers/video/backlight/corgi_lcd.c
> >  drivers/video/backlight/locomolcd.c
> >  drivers/video/backlight/tosa_bl.c
> >  drivers/video/backlight/tosa_lcd.c
> >
> >  These drivers also have default values when comadj or phadadj == -1.
> >  I checked what values are actually contained in this struct in
> >  earlier kernels. 3.2.24 kernel is the latest one i know of where
> >  sharpsl_save_param() works properly. And it also has these fields
> > initialised
> >  to -1.
>
> What values was it loading from the bootloader? Or are you saying that
> it wasn't finding the bootloader information and therefore just using -1
> for everything?
>
> >  So it seems to me that sharpsl_param.c is redundant as it currently
> > only
> >  serves to assign -1 to a few variables. And drivers that use these
> > variables
> >  then handle -1 with assigning default values.
>
> Its not redundant, it sounds like its just broken at some point, at
> least on the platform you tested and nobody has noticed/cared. The
> better solution would be to fix it. Obviously its much easier to delete
> the code though.
>
> Cheers,
>
> Richard
>
>
>

Hmmm, i ran some tests again and it seems that my previous tests were
wrong. Sharpsl_param works properly in 3.2.24. I see proper values in
comadj and phadaj fields. Please disregard this patch, i should've
been more thorough with my tests. I'll try to bisect and find out why
it doesn't work in 3.6-rc2. Actually, it's broken since at least 3.4,
that should narrow my search down.


From snijsure at grid-net.com  Wed Aug 22 18:10:00 2012
From: snijsure at grid-net.com (Subodh Nijsure)
Date: Wed, 22 Aug 2012 15:10:00 -0700
Subject: Can one  set GPIO direction in pinmux definition?
In-Reply-To: <5035388D.2060909@wwwdotorg.org>
References: <5034FCB2.5040709@grid-net.com> <5035388D.2060909@wwwdotorg.org>
Message-ID: <503558B8.4010603@grid-net.com>

On 08/22/2012 12:52 PM, Stephen Warren wrote:
> On 08/22/2012 09:37 AM, Subodh Nijsure wrote:
>> For a MX28 based hardware I am working with I need to use AUART4
>>
>> I need to configure this AUART4 as uart only when necessary and at all
>> other times pins associated with AUART4 need to be configured as inputs.
> Out of curiosity, why?
Out hardware is connected to external equipment, electric meter via this 
UART.
This electricity meter can also be read externally by an optical reader.
Since this is a shared bus, we can't be sitting on that bus with our 
interface configured as UART as it prevents optical reader from talking 
to the meter. There are ways we can tell is optical meter is connected, 
if we detect that its connected we configure these pins as input else 
configure them for UART functionality.

> BTW, you didn't CC any of the IMX maintainers, so it's likely they won't
> see your question. I've CC'd LinusW, Shawn, and Dong.
thanks.
>> I am using following DT definitions to setup AUART4 mux  but can't
>> figure out how to setup pin direction via DT, can it be done or I need
>> to do it in C code?
>>
>>          apb at 80000000 {
>>                  apbh at 80000000 {
>>                                  auart4_pins_a: auart4 at 0 {
>>                                          reg = <0>;
>>                                          fsl,pinmux-ids = <
>>                                                  0x3142 /*
>> MX28_PAD_SAIF0_MCLK__AUART4_CTS */
>>                                                  0x3152 /*
>> MX28_PAD_SAIF0_LRCLK__AUART4_RTS */
>>                                                  0x3162 /*
>> MX28_PAD_SAIF0_BITCLK__AUART4_RX */
>>                                                  0x3172 /*
>> MX28_PAD_SAIF0_SDATA0__AUART4_TX */
>>                                          >;
>>                                          fsl,drive-strength = <0>;
>>                                          fsl,voltage = <1>;
>>                                          fsl,pull-up = <0>;
>>                                  };
>>                                  auart4_highz_pins: auart4-gpio at 0 {
>>                                          reg = <0>;
>>                                          fsl,pinmux-ids = <
>>                                                  0x3143 /*
>> MX28_PAD_SAIF0_MCLK__GPIO_3_20 */
>>                                                  0x3153 /*
>> MX28_PAD_SAIF0_LRCLK__GPIO_3_21 */
>>                                                  0x3163 /*
>> MX28_PAD_SAIF0_BITCLK__GPIO_3_22 */
>>                                                  0x3173 /*
>> MX28_PAD_SAIF0_SDATA0__GPIO_3_23 */
>>                                          >;
>>                                          fsl,drive-strength = <0>;
>>                                          fsl,voltage = <1>;
>>                                          fsl,pull-up = <0>;
>>                                  };
>>                   };
>>            };
> I don't know IMX HW, but where is highz controlled? On other SoCs I'm
> familiar with, when a pad is configured as a GPIO, the highz state is
> controlled by the GPIO module, so there's nothing pinmux can do about
> it. Even if the pinmux HW does control highz, gpio_direction_*() are
> still meant to communicate with the pinctrl driver to implement this, so
> overriding it through the pinctrl configuration seems like a bad thing.
>
> So I think your UART driver would have to request the GPIOs, and set
> them as inputs. So, I guess your UART node below would need a property
> listing the GPIOs to do this to.
Right now that is what I am doing in my code, requesting GPIOs in UART 
drivers and setting up the direction. I just wanted to make sure there 
wasn't way to setup pin direction using pinmux itself.

>>                  apbx at 80040000 {
>>                          auart4: serial at 80072000 {
>>                                  pinctrl-names = "default", "auart";
>>                                  pinctrl-0 = <&auart4_highz_pins>;
>>                                  pinctrl-1 = <&auart4_pins_a>;
>>                                  status = "okay";
>>                          };
>>                 };
>>

Thanks.
-Subodh


From stigge at antcom.de  Wed Aug 22 18:16:12 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 00:16:12 +0200
Subject: [PATCH 1/2] usb: change the dependency chain for LPC32XX and
 ISP1301
In-Reply-To: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
References: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
Message-ID: <50355A2C.9010505@antcom.de>

Hi,

On 22/08/12 21:49, Alan Stern wrote:
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index c3f619b..cac3ee2 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -292,7 +292,6 @@ config USB_OHCI_HCD
>>  	depends on USB && USB_ARCH_HAS_OHCI
>>  	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
>>  	select USB_OTG_UTILS if ARCH_OMAP
>> -	select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
> 
> You want to avoid selecting USB_ISP1301, right?

The ultimate goal is just to prevent the compile error that currently
occurs when I2C isn't selected on LPC32XX but UDC is. It's an invalid
config combination, not easy to prevent by current Kconfig mechanism.

>> @@ -412,6 +411,15 @@ config USB_CNS3XXX_OHCI
>>  	  Enable support for the CNS3XXX SOC's on-chip OHCI controller.
>>  	  It is needed for low-speed USB 1.0 device support.
>>  
>> +config USB_OHCI_LPC32XX_PNX4008
>> +	bool "LPC32XX or PNX4008 OHCI Module"
>> +	depends on USB_OHCI_HCD
>> +	depends on USB_ISP1301
>> +	---help---
>> +	  Enable support for the LPC32XX or PNX4008 SOC's on-chip
>> +	  OHCI controller.
>> +	  It is needed for low-speed USB 1.0 device support.
> 
> Instead you introduce a new symbol to control whether or not ohci-nxp.c
> gets compiled.  The new symbol depends on USB_ISP1301 but not on
> ARCH_LPC32XX or ARCH_PNX4008, which means in theory it could be defined
> even under a totally different arch.

This issue could be resolved in a different way: Have you followed the
discussion at linux-arm-kernel at lists.infradead.org on 2012-08-20,
Subject "i2c: pnx: Fix bit definitions"? If nothing unexpected turns
out, PNX4008 should probably be removed altogether. (Practically
abandoned arch for 6 years.) Easily possible for v3.7.

Then, the resulting solution is much simpler and Sebastian's patch obsolete.

Thanks,

Roland


From stigge at antcom.de  Wed Aug 22 18:25:10 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 00:25:10 +0200
Subject: [PATCH RESEND] mtd: lpc32xx_mlc: Make driver independent of AMBA DMA
 engine driver
Message-ID: <1345674311-16874-1-git-send-email-stigge@antcom.de>

This patch makes the MLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.

(This also fixes the build error of the MLC NAND driver in case of module
linking because the (not exported) reference to pl08x_filter_id is gone now.)

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
Applies to: v3.6-rc2

 drivers/mtd/nand/lpc32xx_mlc.c  |   13 +++++++++++--
 include/linux/mtd/lpc32xx_mlc.h |   20 ++++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_mlc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_mlc.c
@@ -37,7 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_mtd.h>
 #include <linux/of_gpio.h>
-#include <linux/amba/pl08x.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
@@ -171,6 +171,7 @@ static struct nand_bbt_descr lpc32xx_nan
 
 struct lpc32xx_nand_host {
 	struct nand_chip	nand_chip;
+	struct lpc32xx_mlc_platform_data *pdata;
 	struct clk		*clk;
 	struct mtd_info		mtd;
 	void __iomem		*io_base;
@@ -581,9 +582,15 @@ static int lpc32xx_dma_setup(struct lpc3
 	struct mtd_info *mtd = &host->mtd;
 	dma_cap_mask_t mask;
 
+	if (!host->pdata || !host->pdata->dma_filter) {
+		dev_err(mtd->dev.parent, "no DMA platform data\n");
+		return -ENOENT;
+	}
+
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
-	host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-mlc");
+	host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
+					     "nand-mlc");
 	if (!host->dma_chan) {
 		dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 		return -EBUSY;
@@ -703,6 +710,8 @@ static int __devinit lpc32xx_nand_probe(
 	}
 	lpc32xx_wp_disable(host);
 
+	host->pdata = pdev->dev.platform_data;
+
 	nand_chip->priv = host;		/* link the private data structures */
 	mtd->priv = nand_chip;
 	mtd->owner = THIS_MODULE;
--- /dev/null
+++ linux-2.6/include/linux/mtd/lpc32xx_mlc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC MLC NAND controller
+ *
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_MLC_H
+#define __LINUX_MTD_LPC32XX_MLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_mlc_platform_data {
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_MLC_H */


From stigge at antcom.de  Wed Aug 22 18:25:11 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 00:25:11 +0200
Subject: [PATCH RESEND] mtd: lpc32xx_slc: Make driver independent of AMBA DMA
 engine driver
In-Reply-To: <1345674311-16874-1-git-send-email-stigge@antcom.de>
References: <1345674311-16874-1-git-send-email-stigge@antcom.de>
Message-ID: <1345674311-16874-2-git-send-email-stigge@antcom.de>

This patch makes the SLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.

(This also fixes the build error of the SLC NAND driver in case of module
linking because the (not exported) reference to pl08x_filter_id is gone now.)

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
Applies to: v3.6-rc2

 drivers/mtd/nand/lpc32xx_slc.c  |   13 +++++++++++--
 include/linux/mtd/lpc32xx_slc.h |   20 ++++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_slc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_slc.c
@@ -37,7 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_mtd.h>
 #include <linux/of_gpio.h>
-#include <linux/amba/pl08x.h>
+#include <linux/mtd/lpc32xx_slc.h>
 
 #define LPC32XX_MODNAME		"lpc32xx-nand"
 
@@ -199,6 +199,7 @@ struct lpc32xx_nand_cfg_slc {
 
 struct lpc32xx_nand_host {
 	struct nand_chip	nand_chip;
+	struct lpc32xx_slc_platform_data *pdata;
 	struct clk		*clk;
 	struct mtd_info		mtd;
 	void __iomem		*io_base;
@@ -714,9 +715,15 @@ static int lpc32xx_nand_dma_setup(struct
 	struct mtd_info *mtd = &host->mtd;
 	dma_cap_mask_t mask;
 
+	if (!host->pdata || !host->pdata->dma_filter) {
+		dev_err(mtd->dev.parent, "no DMA platform data\n");
+		return -ENOENT;
+	}
+
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
-	host->dma_chan = dma_request_channel(mask, pl08x_filter_id, "nand-slc");
+	host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
+					     "nand-slc");
 	if (!host->dma_chan) {
 		dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 		return -EBUSY;
@@ -814,6 +821,8 @@ static int __devinit lpc32xx_nand_probe(
 	}
 	lpc32xx_wp_disable(host);
 
+	host->pdata = pdev->dev.platform_data;
+
 	mtd = &host->mtd;
 	chip = &host->nand_chip;
 	chip->priv = host;
--- /dev/null
+++ linux-2.6/include/linux/mtd/lpc32xx_slc.h
@@ -0,0 +1,20 @@
+/*
+ * Platform data for LPC32xx SoC SLC NAND controller
+ *
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_LPC32XX_SLC_H
+#define __LINUX_MTD_LPC32XX_SLC_H
+
+#include <linux/dmaengine.h>
+
+struct lpc32xx_slc_platform_data {
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+};
+
+#endif  /* __LINUX_MTD_LPC32XX_SLC_H */


From tony at atomide.com  Wed Aug 22 17:01:14 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 22 Aug 2012 14:01:14 -0700
Subject: [PATCH v3 2/9] ARM: OMAP: mcbsp: Enable FIFO use for OMAP2430
In-Reply-To: <20120822191139.GI7995@opensource.wolfsonmicro.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-3-git-send-email-peter.ujfalusi@ti.com>
 <20120822191139.GI7995@opensource.wolfsonmicro.com>
Message-ID: <20120822210114.GL11011@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120822 12:12]:
> On Thu, Aug 16, 2012 at 04:41:01PM +0300, Peter Ujfalusi wrote:
> > On OMAP2430 all McBSP ports have 128 word long buffer, enable the use of
> > the FIFO for the audio stack.
> > 
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> > Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
> 
> I applied this - Tony, from the thread it seemed you were OK even though
> you didn't explicitly ack it?

Ah yes sorry, I'm fine with it. Sounds like you already applied it,
so too late to ack. But just in case:

Acked-by: Tony Lindgren <tony at atomide.com>


From matt at genesi-usa.com  Wed Aug 22 18:50:23 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 22 Aug 2012 17:50:23 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <503384E3.4030705@calxeda.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <503384E3.4030705@calxeda.com>
Message-ID: <CAKGA1bkNGJhsCGVBsHnaQn=Dg5T==QP_JnqOXycq8jQn-W-0Kw@mail.gmail.com>

On Tue, Aug 21, 2012 at 7:53 AM, Rob Herring <rob.herring at calxeda.com> wrote:
>
>> How do you explain duplicating the clock names in the array AND in the
>> device node as NOT being bloated?
>
> Read the clock binding doc. Names are optional and the 2 names are not
> the same. One is the name of the output on the CCM and one is the name
> on input to the module.

My understanding of the i.MX clock tree naming in the docs, though, is
that the names in the DT don't match the ones in the docs, regardless.

I also don't understand how lots of nodes in a tree *is* lots of
bloat, by Shawn's definition, but lots of entirely Linux- and
common-clock-framework-specific names in a table *isn't* bloat even if
most of these clocks and names are not used for devices in the tree
anyway.

Device trees shouldn't encode data that is entirely specific to a
Linux driver. Even if the only user is Linux, you are not describing
the Linux driver, you are describing the hardware. The names match the
hardware specification in the CCM chapters of the manual, but just
barely. All Shawn has done here is make the lookup in the DT, which is
at the very least internally consistent (it's not referencing the
order of an array elsewhere than the device tree), but an index into
an array of strings is not the way we generally encode things in
device trees since the dawn of time, and certainly shouldn't be
acceptable behavior now.

I might agree somewhat with Shawn that encoding every clock for the
chip in the tree (some 190+ entries) and it's bits and entries is a
ridiculous amount, but most boards don't need all the clocks or
selects defined if they're not using those peripherals. There are ways
to make sure boards do not over-define their clock tree (and any
clocks not defined will not get enabled anyway).

That the clock tree is SoC-specific doesn't mean it should not be
encoded in the tree; the fact that Sascha could write a fairly
comprehensive common clock subsystem shows that for certain families
of SoC, certain groupings of clock mux, select and associations
between unit clock (for instance to write to registers) and peripheral
output clock (for instance to clock data to an MMC card or SPI bus or
whatever) are fairly "common" as it stands. What is not common is the
naming and the meaning of that naming, which in the end is only useful
to drivers as debugging information anyway.

What I don't get is why you'd implement a clock lookup as <&clk 160>
<&clk 161> and then futher give them names like "ipg" "per", even if
these were seperate clocks, it makes no sense to NAME them. If clock
160 is "uart_ipg" and 161 is "uart_serial", what are you gaining from
the clock-names property inside the actual device definition? You're
encoding the "ipg" root clock name twice, and "per" doesn't make any
sense here.

What's the difference with moving ALL the definitions of clock values
from the driver (such as arch/arm/mach-imx/clk-mx51-mx53.c) into the
DT and parsing it all out of the DT? Once it's registered then you
have to look it up by name, but if each DT driver node (uart@ for
example) references the clock node by phandle, it will be able to look
up that exact clock by that phandle, correct? What I'm confused about
right now is what the difference is between naming them "ipg" and
"per" vs. "donkey" and "shrek"? This is just a driver-specific naming
such that it can find these things and turn on and off the right
clocks at the right time, but it doesn't make any sense to refer to
the CCM node, then an index to a an array of names, then two more
names defining the clock definition. uart_serial cannot be used for
ANYTHING besides the uart "per" clock, so just encode this as a clock
type in the individual clock node. The clkdev subsystem can resolve
"per" to some magic value or the string in the tree...

uart_ipg_clk: clock at foo {
     clock-name = "uart";
     fsl,clock-type = "ipg";
     ...
};

uart at bar {
     clocks = <&uart_ipg_clk, &uart_per_clk>
};

I counted here and we're not "bloating" anything in terms of bytes
used to define the clocks - what we save in not doing an array lookup,
we lose in defining a node. Tthis is not going to end the world. What
you "waste" in the device tree, you get to automate in the Linux
driver anyway and remove a bunch of tables, which is what Shawn's
trying to do anyway. If the UART driver needs to do;

        sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");

Then it has all the information it needs here; one of the phandle
references points to a clock which has "ipg" as it's fsl,clock-type
property. Or something else.

It is going to be an SoC-specific binding, that's for sure, but since
there is a definition for a fixed clock, why can't there be a
definition for a gated clock (enable/disable), mux select defined as a
group and possible selections, and the right clocks being defined with
the right potential parents? The entire clock tree AND it's lookups
can be built from device tree, per documentation, per actual SoC
layout and the driver has to live with getting the information from
somewhere other than the heady mix of a table in DT, and a table in
Linux which don't necessarily depend on each other?

You only have to do these lookups once when the clock subsystem starts
on Linux, it's not like every time you want to go find a clock you
have to actually enter a firmware interface, parse the entire device
tree, come back out with a small snippet of data and then go off and
do the stuff; it's been put in a readily-accessible structure, and
gets done at device probe. Register them at boot, find them in the
clock subsystem, you're ready to go.

I would rather see every clock defined in the tree, as much "bloat" as
you would seem to think it is, it makes no sense to have a huge table
of clock definitions who's names and numbers are defined in the device
tree, yet register offsets and bit widths and values and defaults and
parents are defined in the driver itself along with lots of other
lists and tables. The table in the DT is making a huge assumption
about the subsystem needs to do the clock lookups and the way the
*Linux drivers* themself actually works; this is wrong, wrong, wrong
on so many levels.

> While generally optional, Shawn has chosen to require at least the
> output names. In the case of defining a signal clock controller node
> with lots of outputs, that is the right choice.

You only need to define the inputs and outputs you use, and in the end
I think referencing an array of strings by phandle and index into a
property contained in that handle, then looking up another string in
it's own device node to make sure which clock is which, is more
complex and takes longer than referencing a clock by phandle and
looking at two specific properties defining that clock. If we're going
this far, we should DEFINITELY be encoding the clock subsystems in the
SoC entirely in the device tree and automating clock setup. If the
common clock framework lives up to it's name, all you'd need is a
single arch/arm/mach-imx/clk.c to map the specific operation for every
i.MX SoC (i.e. bindings for i.MX) and not one for *every* i.MX SoC,
and all this data can be adequately encoded in the DT.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From sboyd at codeaurora.org  Wed Aug 22 18:55:42 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 15:55:42 -0700
Subject: [PATCH 0/3] Miscellaneous MSM fixes
Message-ID: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>

Here's a small collection of MSM patches I have lying around.
The first removes a useless file and hook that nobody is using.
The second marks some functions static in clock-pcom.c since
they aren't used outside the file and the last removes idle.c
because it's dead code.

Stephen Boyd (3):
  ARM: MSM: Remove msm_hw_reset_hook
  ARM: MSM: clock-pcom: Mark functions static
  ARM: MSM: Remove unused idle.c

 arch/arm/mach-msm/Makefile              |  2 +-
 arch/arm/mach-msm/board-mahimahi.c      |  1 -
 arch/arm/mach-msm/board-sapphire.c      |  1 -
 arch/arm/mach-msm/clock-pcom.c          | 18 ++++++------
 arch/arm/mach-msm/idle.c                | 49 ---------------------------------
 arch/arm/mach-msm/include/mach/system.h | 19 -------------
 arch/arm/mach-msm/proc_comm.c           |  1 -
 arch/arm/mach-msm/smd.c                 |  7 -----
 8 files changed, 10 insertions(+), 88 deletions(-)
 delete mode 100644 arch/arm/mach-msm/idle.c
 delete mode 100644 arch/arm/mach-msm/include/mach/system.h

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 18:55:43 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 15:55:43 -0700
Subject: [PATCH 1/3] ARM: MSM: Remove msm_hw_reset_hook
In-Reply-To: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
References: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345676145-12321-2-git-send-email-sboyd@codeaurora.org>

This reset hook is never assigned and is dead code. Remove it so
we have one less header file in the mach directory.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/board-mahimahi.c      |  1 -
 arch/arm/mach-msm/board-sapphire.c      |  1 -
 arch/arm/mach-msm/include/mach/system.h | 19 -------------------
 arch/arm/mach-msm/proc_comm.c           |  1 -
 arch/arm/mach-msm/smd.c                 |  7 -------
 5 files changed, 29 deletions(-)
 delete mode 100644 arch/arm/mach-msm/include/mach/system.h

diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a..df00bc0 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
 
 #include <mach/board.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 
 #include "board-mahimahi.h"
 #include "devices.h"
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab..b7b0fc7 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
 
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec..0000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-msm/include/mach/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* low level hardware reset hook -- for example, hitting the
- * PSHOLD line on the PMIC to hard reset the system
- */
-extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc7..8f1eecd 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <mach/msm_iomap.h>
-#include <mach/system.h>
 
 #include "proc_comm.h"
 
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73..84183ed 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
 #include <linux/delay.h>
 
 #include <mach/msm_smd.h>
-#include <mach/system.h>
 
 #include "smd_private.h"
 #include "proc_comm.h"
@@ -39,8 +38,6 @@
 #define CONFIG_QDSP6 1
 #endif
 
-void (*msm_hw_reset_hook)(void);
-
 #define MODULE_NAME "msm_smd"
 
 enum {
@@ -101,10 +98,6 @@ static void handle_modem_crash(void)
 	pr_err("ARM9 has CRASHED\n");
 	smd_diag();
 
-	/* hard reboot if possible */
-	if (msm_hw_reset_hook)
-		msm_hw_reset_hook();
-
 	/* in this case the modem or watchdog should reboot us */
 	for (;;)
 		;
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 18:55:44 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 15:55:44 -0700
Subject: [PATCH 2/3] ARM: MSM: clock-pcom: Mark functions static
In-Reply-To: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
References: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345676145-12321-3-git-send-email-sboyd@codeaurora.org>

These functions are only used within clock-pcom.c, therefore mark
them as static.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/clock-pcom.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b7113..a52c970 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
 /*
  * glue for the proc_comm interface
  */
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
 	if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
 {
 	msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
 {
 	/* The rate _might_ be rounded off to the nearest KHz value by the
 	 * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
 	if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
 	if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
 {
 	int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
 	if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
 		return (int)id < 0 ? -EINVAL : 0;
 }
 
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
 {
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
 		return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
 		return id;
 }
 
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
 {
 	if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
 		return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
 		return id;
 }
 
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
 {
 
 	/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 18:55:45 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 15:55:45 -0700
Subject: [PATCH 3/3] ARM: MSM: Remove unused idle.c
In-Reply-To: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
References: <1345676145-12321-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345676145-12321-4-git-send-email-sboyd@codeaurora.org>

Forcing arm_pm_idle to be msm_idle() doesn't make sense in
configurations that don't have CONFIG_MSM7X00A_IDLE=y (i.e. any
targets that aren't 7x00a). Furthermore, that config doesn't even
exist, so this entire file is dead code. Just remove it so we can
use the default idle support on MSM.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/Makefile |  2 +-
 arch/arm/mach-msm/idle.c   | 49 ----------------------------------------------
 2 files changed, 1 insertion(+), 50 deletions(-)
 delete mode 100644 arch/arm/mach-msm/idle.c

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969..5fd0464 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,4 +1,4 @@
-obj-y += io.o idle.o timer.o
+obj-y += io.o timer.o
 obj-y += clock.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c..0000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* arch/arm/mach-msm/idle.c
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <asm/system.h>
-
-static void msm_idle(void)
-{
-#ifdef CONFIG_MSM7X00A_IDLE
-	asm volatile (
-
-	"mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
-	"bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
-	"bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
-	"mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
-
-	"mov     r0, #0                   /* prepare wfi value  */ \n\t"
-	"mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
-	"mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
-	"mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
-
-	"mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
-
-	: : : "r0","r1" );
-#endif
-}
-
-static int __init msm_idle_init(void)
-{
-	arm_pm_idle = msm_idle;
-	return 0;
-}
-
-arch_initcall(msm_idle_init);
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 19:00:12 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 16:00:12 -0700
Subject: [PATCH 0/2] 8660 DT fixlets
Message-ID: <1345676414-16635-1-git-send-email-sboyd@codeaurora.org>

Two small fixes to 8660 DT support so that it boots up
and gets interrupts and so that we can build the dtb via
kernel Makefiles with 'make dtbs'.

Stephen Boyd (2):
  ARM: MSM: Add handle_irq handler for 8660 DT machine
  ARM: MSM: Add msm8660-surf.dts to Makefile.boot

 arch/arm/mach-msm/Makefile.boot   | 2 ++
 arch/arm/mach-msm/board-msm8x60.c | 1 +
 2 files changed, 3 insertions(+)

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 19:00:13 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 16:00:13 -0700
Subject: [PATCH 1/2] ARM: MSM: Add handle_irq handler for 8660 DT machine
In-Reply-To: <1345676414-16635-1-git-send-email-sboyd@codeaurora.org>
References: <1345676414-16635-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345676414-16635-2-git-send-email-sboyd@codeaurora.org>

Commit 041f777 (ARM: msm: convert SMP platforms to
CONFIG_MULTI_IRQ_HANDLER, 2011-09-06) forgot to add the
.handle_irq for the DT machine record. Add it so we get
interrupts instead of panics on DT enabled bootloaders.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/board-msm8x60.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index e37a724..13ca9bb 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -158,6 +158,7 @@ MACHINE_END
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_dt_init,
 	.init_late = msm8x60_init_late,
 	.timer = &msm_timer,
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 22 19:00:14 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 22 Aug 2012 16:00:14 -0700
Subject: [PATCH 2/2] ARM: MSM: Add msm8660-surf.dts to Makefile.boot
In-Reply-To: <1345676414-16635-1-git-send-email-sboyd@codeaurora.org>
References: <1345676414-16635-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <1345676414-16635-3-git-send-email-sboyd@codeaurora.org>

Add this entry to the Makefile so that we can build the dtb
automatically with 'make dtbs'.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/Makefile.boot | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index 9b803a5..8de0678 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -1,3 +1,5 @@
   zreladdr-y		+= 0x10008000
 params_phys-y		:= 0x10000100
 initrd_phys-y		:= 0x10800000
+
+dtb-$(CONFIG_ARCH_MSM8X60) += msm8660-surf.dtb
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From swarren at wwwdotorg.org  Wed Aug 22 19:18:16 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 17:18:16 -0600
Subject: Can one  set GPIO direction in pinmux definition?
In-Reply-To: <503558B8.4010603@grid-net.com>
References: <5034FCB2.5040709@grid-net.com> <5035388D.2060909@wwwdotorg.org>
 <503558B8.4010603@grid-net.com>
Message-ID: <503568B8.4080501@wwwdotorg.org>

On 08/22/2012 04:10 PM, Subodh Nijsure wrote:
> On 08/22/2012 12:52 PM, Stephen Warren wrote:
>> On 08/22/2012 09:37 AM, Subodh Nijsure wrote:
>>> For a MX28 based hardware I am working with I need to use AUART4
>>>
>>> I need to configure this AUART4 as uart only when necessary and at all
>>> other times pins associated with AUART4 need to be configured as inputs.
>> Out of curiosity, why?
>
> Our hardware is connected to external equipment, electric meter via this
> UART.
> This electricity meter can also be read externally by an optical reader.
> Since this is a shared bus, we can't be sitting on that bus with our
> interface configured as UART as it prevents optical reader from talking
> to the meter. There are ways we can tell is optical meter is connected,
> if we detect that its connected we configure these pins as input else
> configure them for UART functionality.

OK, I guess it was something like that. Can the optical be
plugged/unplugged at run-time, or is it a one-off thing? pinctrl would
be appropriate for runtime. Maybe not so much for one-off detection at
boot-time.

I wonder whether making the UART driver do the switching is the right
thing though. I assume that:

* The UART driver can be used on systems (boards) that never have this
HW configuration, and don't care about this at all.

* The detection of optical meter presence is entirely unrelated to the UART.

So probably, the muxing can be seen as completely external and unrelated
to the UART HW module itself. Would it be better represented as a
completely standalone and custom "RS232 bus mux" node/device instead of
tacking this into the UART driver?


From tixy at yxit.co.uk  Wed Aug 22 19:51:01 2012
From: tixy at yxit.co.uk (Tixy)
Date: Thu, 23 Aug 2012 00:51:01 +0100
Subject: [PATCHv3 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <201208221841.29645.arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221519.12056.arnd@arndb.de>
 <alpine.LFD.2.02.1208221136180.1754@xanadu.home>
 <201208221841.29645.arnd@arndb.de>
Message-ID: <1345679461.3601.20.camel@computer5.home>

On Wed, 2012-08-22 at 18:41 +0000, Arnd Bergmann wrote:
> On Wednesday 22 August 2012, Nicolas Pitre wrote:
> > On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > > > 
> > > > The ldrex/strex instructions are available on ARMv6.  It's only the d 
> > > > variants (strexd/ldrexd) which are only available from ARMv6k.
> > > 
> > > Ok. How is the version below then? I haven't tested this one yet.
> > 
> > In fact, I think the b variants are ARMv6k+ as well.  Only the plain 
> > (non b non d) variants are available on ARMv6.
> 
> Ok, third attempt then. This leaves ldrex for ARMv6 but marks
> {st,ld}rex{b,h,d} as V6K specific (which includes ARMv7).

ARMv7 does set CPU_32v6K, because arch/arm/mm/Kconfig has

config CPU_V7
	bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
	select CPU_32v6K
	select CPU_32v7

but this seems more for peripheral reasons not because all the various
CPU configs systematically select the earlier architecture variants,
e.g. CPU_V7 doesn't select CPU_32v6.

So I would have been inclined to test for

#if defined(CONFIG_CPU_32v6K) || (__LINUX_ARM_ARCH__ >= 7) 

but as the current patch is functionally correct I'm not going to
suggest a v4 patch :-)

If you do feel so inclined for a v4 however ;-) you could also make the
mls part of the patch tidier by moving the added #endif to instead
terminate the preceding "#if __LINUX_ARM_ARCH__ >= 6", i.e.

@@ -367,8 +367,10 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
 	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
+#endif
 
+#if __LINUX_ARM_ARCH__ >= 7
 	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
 	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
 	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")


this looks funny in patch form, but the resulting source file is more
consistent with other conditional tests.


> 	Arnd
> 
> 8<-----
> From 6eab418c61c18393006f30d189e2f28d6e403040 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Thu, 16 Aug 2012 07:49:31 +0000
> Subject: [PATCH] ARM: kprobes: make more tests conditional
> 
> The mls instruction is not available in ARMv6K or below, so we
> should make the test conditional on at least ARMv7. ldrexd/strexd
> are available in ARMv6K or ARMv7, which we can test by checking
> the CONFIG_CPU_32v6K symbol. Just testing for ARMv6 is not enough.
> 
> /tmp/ccuMTZ8D.s: Assembler messages:
> /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
> /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
> /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Jon Medhurst <tixy at yxit.co.uk>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
> Cc: Leif Lindholm <leif.lindholm at arm.com>
> ---
>  arch/arm/kernel/kprobes-test-arm.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
> index 38c1a3b..58dd6c3 100644
> --- a/arch/arm/kernel/kprobes-test-arm.c
> +++ b/arch/arm/kernel/kprobes-test-arm.c
> @@ -367,9 +367,11 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> +#endif
>  	TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
> @@ -456,6 +458,7 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
>  #if __LINUX_ARM_ARCH__ >= 6
>  	TEST_UNSUPPORTED("ldrex	r2, [sp]")
> +#ifdef CONFIG_CPU_32v6K
>  	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
>  	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
>  	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
> @@ -463,6 +466,7 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED("strexh	r0, r2, [sp]")
>  	TEST_UNSUPPORTED("ldrexh	r2, [sp]")
>  #endif
> +#endif
>  	TEST_GROUP("Extra load/store instructions")
>  
>  	TEST_RPR(  "strh	r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")




From matt at genesi-usa.com  Wed Aug 22 20:08:40 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 22 Aug 2012 19:08:40 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock DT
 lookup
In-Reply-To: <CAKGA1bkNGJhsCGVBsHnaQn=Dg5T==QP_JnqOXycq8jQn-W-0Kw@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <503384E3.4030705@calxeda.com>
 <CAKGA1bkNGJhsCGVBsHnaQn=Dg5T==QP_JnqOXycq8jQn-W-0Kw@mail.gmail.com>
Message-ID: <CAKGA1bnCk=FqANsVFD123y3uP5dn9AMZydR__mMXrzh6StrBjg@mail.gmail.com>

Ugh. Okay my blood sugar was super low. Can I just condense that into
I agree with Russell and the binding makes no sense once it gets past
the simple definition described in the binding?

If we take the pinctrl mess as an example, all the DT serves to do is
define an SoC-specific or family-specific binding into data the
pinctrl subsystem can use, via an SoC-specific abstraction in a driver
to make a generic subsystem in Linux work the way it should.

The common clock subsystem is no different - divider, fixed factor,
fixed rate, mux, gate, highbank (??) are defined in a way that
abstracts most of the actual SoC-specific stuff out to register
offsets, values, bit definitions and masks.

Right now for i.MX we have several abstraction interfaces
(imx_clk_XXX) which move values from tables around and call the
appropriate common clock function to register the clock. These
abstractions are identical for all the possible i.MX SoCs
(imx_clk_gate2, imx_clk_mux etc.) and move the values around so they
can be passed to clk_register_##same.

So if we can define a fixed-clock, why can't we define an
fsl,gated-clock or fsl,muxed-clock which defines an i.MX clock of that
type, and a much smaller subset of code that stuffs these values in
through a small abstraction and remove all these seperate
clk-imx51-imx53.c, clk-imx6q.c, clk-imx31.c files which are sharing
common functionality into one mega-abstraction which works across the
whole family?

The way I understand the binding right now (and I'm looking at this;
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob_plain;f=Documentation/devicetree/bindings/clock/clock-bindings.txt;hb=766e6a4ec602d0c107553b91b3434fe9c03474f4),
this is entirely what the clock binding is saying we should do. But I
don't understand why we're naming inputs and outputs, but not defining
how these signals are routed (possibly through gate bits in registers)
and leaving that down to some driver somewhere. Or why we have to name
clocks twice, once for the canonical name of the output in reference
to a higher level or root clock "uart_serial", vs. a driver-level name
for that input or output in the driver ("per"), since most clocks at
the driver level can't be re-used for other things anyway. If they
could, the whole prepare/unprepare and some explicit parenting/muxing
of clocks would handle that anyway so that the clock was enabled while
there was at least one user.

I do understand that in Shawn's patch and using UART as an example
again, "ipg" and "per" are definitely needed by the driver, and these
names are defined by the driver and implicit in the documentation to
enable the use of this unit, but at the end of the day the definition
at the *device* level (uart@) makes no sense except to perform a
lookup on a string, and in the end this string lookup only gets done
at the driver probe time anyway. With a standard definition of these
"ipg" and "per" strings per family of SoC or even in a generic fashion
across all possible SoCs (in this case, both are defined using
imx_clk_gate2()) then a node defining that clock and it's magical
driver-specific name would work just as well by phandle reference, and
it's parents are referenced by phandle, and all this stays within
SoC-specific abstraction of the common clocks and turns into normal
common clock structure stuff anyway (so you still get to do a string
lookup, but it's being stuffed by an i.MX driver and registered from
data it pulled from the DT).

Wouldn't we rather have a single device tree parser and clock
registration for i.MX than the current 7 which would get split into 7
clock registration drivers with some helpers that parsed half of it
via device tree? I don't really see what benefit you get out of going
for the halfway-defined model.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


On Wed, Aug 22, 2012 at 5:50 PM, Matt Sealey <matt at genesi-usa.com> wrote:
> On Tue, Aug 21, 2012 at 7:53 AM, Rob Herring <rob.herring at calxeda.com> wrote:
>>
>>> How do you explain duplicating the clock names in the array AND in the
>>> device node as NOT being bloated?
>>
>> Read the clock binding doc. Names are optional and the 2 names are not
>> the same. One is the name of the output on the CCM and one is the name
>> on input to the module.
>
> My understanding of the i.MX clock tree naming in the docs, though, is
> that the names in the DT don't match the ones in the docs, regardless.
>
> I also don't understand how lots of nodes in a tree *is* lots of
> bloat, by Shawn's definition, but lots of entirely Linux- and
> common-clock-framework-specific names in a table *isn't* bloat even if
> most of these clocks and names are not used for devices in the tree
> anyway.
>
> Device trees shouldn't encode data that is entirely specific to a
> Linux driver. Even if the only user is Linux, you are not describing
> the Linux driver, you are describing the hardware. The names match the
> hardware specification in the CCM chapters of the manual, but just
> barely. All Shawn has done here is make the lookup in the DT, which is
> at the very least internally consistent (it's not referencing the
> order of an array elsewhere than the device tree), but an index into
> an array of strings is not the way we generally encode things in
> device trees since the dawn of time, and certainly shouldn't be
> acceptable behavior now.
>
> I might agree somewhat with Shawn that encoding every clock for the
> chip in the tree (some 190+ entries) and it's bits and entries is a
> ridiculous amount, but most boards don't need all the clocks or
> selects defined if they're not using those peripherals. There are ways
> to make sure boards do not over-define their clock tree (and any
> clocks not defined will not get enabled anyway).
>
> That the clock tree is SoC-specific doesn't mean it should not be
> encoded in the tree; the fact that Sascha could write a fairly
> comprehensive common clock subsystem shows that for certain families
> of SoC, certain groupings of clock mux, select and associations
> between unit clock (for instance to write to registers) and peripheral
> output clock (for instance to clock data to an MMC card or SPI bus or
> whatever) are fairly "common" as it stands. What is not common is the
> naming and the meaning of that naming, which in the end is only useful
> to drivers as debugging information anyway.
>
> What I don't get is why you'd implement a clock lookup as <&clk 160>
> <&clk 161> and then futher give them names like "ipg" "per", even if
> these were seperate clocks, it makes no sense to NAME them. If clock
> 160 is "uart_ipg" and 161 is "uart_serial", what are you gaining from
> the clock-names property inside the actual device definition? You're
> encoding the "ipg" root clock name twice, and "per" doesn't make any
> sense here.
>
> What's the difference with moving ALL the definitions of clock values
> from the driver (such as arch/arm/mach-imx/clk-mx51-mx53.c) into the
> DT and parsing it all out of the DT? Once it's registered then you
> have to look it up by name, but if each DT driver node (uart@ for
> example) references the clock node by phandle, it will be able to look
> up that exact clock by that phandle, correct? What I'm confused about
> right now is what the difference is between naming them "ipg" and
> "per" vs. "donkey" and "shrek"? This is just a driver-specific naming
> such that it can find these things and turn on and off the right
> clocks at the right time, but it doesn't make any sense to refer to
> the CCM node, then an index to a an array of names, then two more
> names defining the clock definition. uart_serial cannot be used for
> ANYTHING besides the uart "per" clock, so just encode this as a clock
> type in the individual clock node. The clkdev subsystem can resolve
> "per" to some magic value or the string in the tree...
>
> uart_ipg_clk: clock at foo {
>      clock-name = "uart";
>      fsl,clock-type = "ipg";
>      ...
> };
>
> uart at bar {
>      clocks = <&uart_ipg_clk, &uart_per_clk>
> };
>
> I counted here and we're not "bloating" anything in terms of bytes
> used to define the clocks - what we save in not doing an array lookup,
> we lose in defining a node. Tthis is not going to end the world. What
> you "waste" in the device tree, you get to automate in the Linux
> driver anyway and remove a bunch of tables, which is what Shawn's
> trying to do anyway. If the UART driver needs to do;
>
>         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
>
> Then it has all the information it needs here; one of the phandle
> references points to a clock which has "ipg" as it's fsl,clock-type
> property. Or something else.
>
> It is going to be an SoC-specific binding, that's for sure, but since
> there is a definition for a fixed clock, why can't there be a
> definition for a gated clock (enable/disable), mux select defined as a
> group and possible selections, and the right clocks being defined with
> the right potential parents? The entire clock tree AND it's lookups
> can be built from device tree, per documentation, per actual SoC
> layout and the driver has to live with getting the information from
> somewhere other than the heady mix of a table in DT, and a table in
> Linux which don't necessarily depend on each other?
>
> You only have to do these lookups once when the clock subsystem starts
> on Linux, it's not like every time you want to go find a clock you
> have to actually enter a firmware interface, parse the entire device
> tree, come back out with a small snippet of data and then go off and
> do the stuff; it's been put in a readily-accessible structure, and
> gets done at device probe. Register them at boot, find them in the
> clock subsystem, you're ready to go.
>
> I would rather see every clock defined in the tree, as much "bloat" as
> you would seem to think it is, it makes no sense to have a huge table
> of clock definitions who's names and numbers are defined in the device
> tree, yet register offsets and bit widths and values and defaults and
> parents are defined in the driver itself along with lots of other
> lists and tables. The table in the DT is making a huge assumption
> about the subsystem needs to do the clock lookups and the way the
> *Linux drivers* themself actually works; this is wrong, wrong, wrong
> on so many levels.
>
>> While generally optional, Shawn has chosen to require at least the
>> output names. In the case of defining a signal clock controller node
>> with lots of outputs, that is the right choice.
>
> You only need to define the inputs and outputs you use, and in the end
> I think referencing an array of strings by phandle and index into a
> property contained in that handle, then looking up another string in
> it's own device node to make sure which clock is which, is more
> complex and takes longer than referencing a clock by phandle and
> looking at two specific properties defining that clock. If we're going
> this far, we should DEFINITELY be encoding the clock subsystems in the
> SoC entirely in the device tree and automating clock setup. If the
> common clock framework lives up to it's name, all you'd need is a
> single arch/arm/mach-imx/clk.c to map the specific operation for every
> i.MX SoC (i.e. bindings for i.MX) and not one for *every* i.MX SoC,
> and all this data can be adequately encoded in the DT.
>
> --
> Matt Sealey <matt at genesi-usa.com>
> Product Development Analyst, Genesi USA, Inc.


From matt at genesi-usa.com  Wed Aug 22 20:17:50 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Wed, 22 Aug 2012 19:17:50 -0500
Subject: Can one set GPIO direction in pinmux definition?
In-Reply-To: <5034FCB2.5040709@grid-net.com>
References: <5034FCB2.5040709@grid-net.com>
Message-ID: <CAKGA1b=ko_KBW5KwSLmJ2W1KioZt2s2fuezfrB+oZFcwjC7LGg@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:37 AM, Subodh Nijsure <snijsure at grid-net.com> wrote:
>
> For a MX28 based hardware I am working with I need to use AUART4
>
> I need to configure this AUART4 as uart only when necessary and at all other
> times pins associated with AUART4 need to be configured as inputs.
>
> I am using following DT definitions to setup AUART4 mux  but can't figure
> out how to setup pin direction via DT, can it be done or I need to do it in
> C code?
>
>         apb at 80000000 {
>                 apbh at 80000000 {
>                                 auart4_pins_a: auart4 at 0 {
>                                         reg = <0>;
>                                         fsl,pinmux-ids = <
>                                                 0x3142 /*
> MX28_PAD_SAIF0_MCLK__AUART4_CTS */
>                                                 0x3152 /*
> MX28_PAD_SAIF0_LRCLK__AUART4_RTS */
>                                                 0x3162 /*
> MX28_PAD_SAIF0_BITCLK__AUART4_RX */
>                                                 0x3172 /*
> MX28_PAD_SAIF0_SDATA0__AUART4_TX */
>                                         >;
>                                         fsl,drive-strength = <0>;
>                                         fsl,voltage = <1>;
>                                         fsl,pull-up = <0>;
>                                 };
>                                 auart4_highz_pins: auart4-gpio at 0 {
>                                         reg = <0>;
>                                         fsl,pinmux-ids = <
>                                                 0x3143 /*
> MX28_PAD_SAIF0_MCLK__GPIO_3_20 */
>                                                 0x3153 /*
> MX28_PAD_SAIF0_LRCLK__GPIO_3_21 */
>                                                 0x3163 /*
> MX28_PAD_SAIF0_BITCLK__GPIO_3_22 */
>                                                 0x3173 /*
> MX28_PAD_SAIF0_SDATA0__GPIO_3_23 */
>                                         >;
>                                         fsl,drive-strength = <0>;
>                                         fsl,voltage = <1>;
>                                         fsl,pull-up = <0>;
>                                 };
>                  };
>           };
>
>                 apbx at 80040000 {
>                         auart4: serial at 80072000 {
>                                 pinctrl-names = "default", "auart";
>                                 pinctrl-0 = <&auart4_highz_pins>;
>                                 pinctrl-1 = <&auart4_pins_a>;
>                                 status = "okay";
>                         };
>                };

Those pin definitions are defined per-device but they're parsed at
module init - so you'd load uart, then your gpio stuff and your uart
would stop working as it's input paths would have moved in the iomux
controller. Until you unloaded the gpio and uart drivers, then loaded
the right one. I am guessing you don't want to be forcibly loading and
unloading drivers just to swap modes.

Someone did some kind of external bus muxing implementation
("extbus"?) a while back which could sort this out; it's since lost in
time and space, or at least I can't figure out the terms I need to
Google to recover it or how I saved my bookmark. You'd have to
(re-)write the drivers to support the switch (i.e. dynamically parse
pinctrl nodes for the swap or pass them by reference to the muxing
implementation) and stop "working" while the other is in use, but I
feel like I remember that only really supported the case where you had
multiple potential plugin boards at boot (not hotpluggable).

In order to set the directions you'd need to define them in a
driver-specific way, but IMO there needs to be a binding that
configures gpio directions anyway since there's not one currently
which is perplexing - for interrupt-capable GPIO sources it is
implicit through the gpio interrupt domain, but for just inputs you
can read, you have to rely on the bootloader setting it up and your
driver knowing exactly what to do..

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From mporter at ti.com  Wed Aug 22 21:09:33 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 21:09:33 -0400
Subject: [PATCH v3 0/3] DaVinci DMA engine conversion
Message-ID: <1345684176-21472-1-git-send-email-mporter@ti.com>

Changes since v1:
	- Add virt-dma support. Better error checks
	  and simplified descriptor handling.
	- Fix support for multiple EDMA controllers
	  Tested on AM18x EVM with WL12xx on MMC1

Changes since v2:
	- Set default Kconfig state to off
	- Fix whitespace and indent issues
	- Simplify struct device * assignments
	- Remove unneeded chcnt in edma_chan_init
	- Remove unneeded conditional assignment of prep_slave_sg
	- Fix devm_* usage

This series begins the conversion of the DaVinci private EDMA API
implementation to a DMA engine driver and converts two of the three
in-kernel users of the private EDMA API to DMA engine.

The approach taken is similar to the recent OMAP DMA Engine
conversion. The EDMA DMA Engine driver is a wrapper around the existing
private EDMA implementation and registers the platform device within
the driver.  This allows the conversion series to stand alone with just
the drivers and no changes to platform code. It also allows peripheral
drivers to continue to use the private EDMA implementation until they
are converted.

The EDMA DMA Engine driver supports slave transfers only at this time. It
is planned to add cyclic transfers in support of audio peripherals.

There are three users of the private EDMA API in the kernel now:
davinci_mmc, spi-davinci, and davinci-mcasp.  This series provides DMA
Engine conversions for the davinci_mmc and spi-davinci drivers which
use the supported slave transfers.

This series has been tested on an AM18x EVM and Hawkboard with
driver performance comparable to that of the private EDMA API
implementations. Both MMC0 and MMC1 are tested which handles the
DA850/OMAP-L138/AM18x specific case where MMC1 uses DMA channels on
a second EDMA channel controller.  All other platforms have a simpler
design with just a single EDMA channel controller.

For those wanting to easily test this series, I've pushed a branch for
each version to my github tree at https://github.com/ohporter/linux. The
current branch is edma-dmaengine-v3.

After this series, the current plan is to complete the mcasp driver
conversion which includes adding cyclic dma support. This will then
enable the removal and refactoring of the private EDMA API functionality
into the EDMA DMA Engine driver.  Since EDMA is also used on the AM33xx
family of parts in mach-omap2/, the plan is to enable this driver on
that platform as well.

Matt Porter (3):
  dmaengine: add TI EDMA DMA engine driver
  mmc: davinci_mmc: convert to DMA engine API
  spi: spi-davinci: convert to DMA engine API

 drivers/dma/Kconfig            |   10 +
 drivers/dma/Makefile           |    1 +
 drivers/dma/edma.c             |  671 ++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/davinci_mmc.c |  271 +++++-----------
 drivers/spi/spi-davinci.c      |  292 ++++++++---------
 include/linux/edma.h           |   29 ++
 6 files changed, 923 insertions(+), 351 deletions(-)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

-- 
1.7.9.5



From mporter at ti.com  Wed Aug 22 21:09:34 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 21:09:34 -0400
Subject: [PATCH v3 1/3] dmaengine: add TI EDMA DMA engine driver
In-Reply-To: <1345684176-21472-1-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
Message-ID: <1345684176-21472-2-git-send-email-mporter@ti.com>

Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine API. The EDMA driver
supports slave transfers but does not yet support cyclic transfers.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/dma/Kconfig  |   10 +
 drivers/dma/Makefile |    1 +
 drivers/dma/edma.c   |  671 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/edma.h |   29 +++
 4 files changed, 711 insertions(+)
 create mode 100644 drivers/dma/edma.c
 create mode 100644 include/linux/edma.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d06ea29..0351719 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -208,6 +208,16 @@ config SIRF_DMA
 	help
 	  Enable support for the CSR SiRFprimaII DMA engine.
 
+config TI_EDMA
+	tristate "TI EDMA support"
+	depends on ARCH_DAVINCI
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	default n
+	help
+	  Enable support for the TI EDMA controller. This DMA
+	  engine is found on TI DaVinci and AM33xx parts.
+
 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 4cf6b12..f5cf310 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_IMX_DMA) += imx-dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
+obj-$(CONFIG_TI_EDMA) += edma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
new file mode 100644
index 0000000..05aea3c
--- /dev/null
+++ b/drivers/dma/edma.c
@@ -0,0 +1,671 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <mach/edma.h>
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+/*
+ * This will go away when the private EDMA API is folded
+ * into this driver and the platform device(s) are
+ * instantiated in the arch code. We can only get away
+ * with this simplification because DA8XX may not be built
+ * in the same kernel image with other DaVinci parts. This
+ * avoids having to sprinkle dmaengine driver platform devices
+ * and data throughout all the existing board files.
+ */
+#ifdef CONFIG_ARCH_DAVINCI_DA8XX
+#define EDMA_CTLRS	2
+#define EDMA_CHANS	32
+#else
+#define EDMA_CTLRS	1
+#define EDMA_CHANS	64
+#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
+
+/* Max of 16 segments per channel to conserve PaRAM slots */
+#define MAX_NR_SG		16
+#define EDMA_MAX_SLOTS		MAX_NR_SG
+#define EDMA_DESCRIPTORS	16
+
+struct edma_desc {
+	struct virt_dma_desc		vdesc;
+	struct list_head		node;
+	int				absync;
+	int				pset_nr;
+	struct edmacc_param		pset[0];
+};
+
+struct edma_cc;
+
+struct edma_chan {
+	struct virt_dma_chan		vchan;
+	struct list_head		node;
+	struct edma_desc		*edesc;
+	struct edma_cc			*ecc;
+	int				ch_num;
+	bool				alloced;
+	int				slot[EDMA_MAX_SLOTS];
+	dma_addr_t			addr;
+	int				addr_width;
+	int				maxburst;
+};
+
+struct edma_cc {
+	int				ctlr;
+	struct dma_device		dma_slave;
+	struct edma_chan		slave_chans[EDMA_CHANS];
+	int				num_slave_chans;
+	int				dummy_slot;
+};
+
+static inline struct edma_cc *to_edma_cc(struct dma_device *d)
+{
+	return container_of(d, struct edma_cc, dma_slave);
+}
+
+static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct edma_chan, vchan.chan);
+}
+
+static inline struct edma_desc
+*to_edma_desc(struct dma_async_tx_descriptor *tx)
+{
+	return container_of(tx, struct edma_desc, vdesc.tx);
+}
+
+static void edma_desc_free(struct virt_dma_desc *vdesc)
+{
+	kfree(container_of(vdesc, struct edma_desc, vdesc));
+}
+
+/* Dispatch a queued descriptor to the controller (caller holds lock) */
+static void edma_execute(struct edma_chan *echan)
+{
+	struct virt_dma_desc *vdesc = vchan_next_desc(&echan->vchan);
+	struct edma_desc *edesc;
+	int i;
+
+	if (!vdesc) {
+		echan->edesc = NULL;
+		return;
+	}
+
+	list_del(&vdesc->node);
+
+	echan->edesc = edesc = to_edma_desc(&vdesc->tx);
+
+	/* Write descriptor PaRAM set(s) */
+	for (i = 0; i < edesc->pset_nr; i++) {
+		edma_write_slot(echan->slot[i], &edesc->pset[i]);
+		dev_dbg(echan->vchan.chan.device->dev,
+			"\n pset[%d]:\n"
+			"  chnum\t%d\n"
+			"  slot\t%d\n"
+			"  opt\t%08x\n"
+			"  src\t%08x\n"
+			"  dst\t%08x\n"
+			"  abcnt\t%08x\n"
+			"  ccnt\t%08x\n"
+			"  bidx\t%08x\n"
+			"  cidx\t%08x\n"
+			"  lkrld\t%08x\n",
+			i, echan->ch_num, echan->slot[i],
+			edesc->pset[i].opt,
+			edesc->pset[i].src,
+			edesc->pset[i].dst,
+			edesc->pset[i].a_b_cnt,
+			edesc->pset[i].ccnt,
+			edesc->pset[i].src_dst_bidx,
+			edesc->pset[i].src_dst_cidx,
+			edesc->pset[i].link_bcntrld);
+		/* Link to the previous slot if not the last set */
+		if (i != (edesc->pset_nr - 1))
+			edma_link(echan->slot[i], echan->slot[i+1]);
+		/* Final pset links to the dummy pset */
+		else
+			edma_link(echan->slot[i], echan->ecc->dummy_slot);
+	}
+
+	edma_start(echan->ch_num);
+}
+
+static int edma_terminate_all(struct edma_chan *echan)
+{
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+
+	/*
+	 * Stop DMA activity: we assume the callback will not be called
+	 * after edma_dma() returns (even if it does, it will see
+	 * echan->edesc is NULL and exit.)
+	 */
+	if (echan->edesc) {
+		echan->edesc = NULL;
+		edma_stop(echan->ch_num);
+	}
+
+	vchan_get_all_descriptors(&echan->vchan, &head);
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+	vchan_dma_desc_free_list(&echan->vchan, &head);
+
+	return 0;
+}
+
+
+static int edma_slave_config(struct edma_chan *echan,
+	struct dma_slave_config *config)
+{
+	if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
+	    (config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+		return -EINVAL;
+
+	if (config->direction == DMA_MEM_TO_DEV) {
+		if (config->dst_addr)
+			echan->addr = config->dst_addr;
+		if (config->dst_addr_width)
+			echan->addr_width = config->dst_addr_width;
+		if (config->dst_maxburst)
+			echan->maxburst = config->dst_maxburst;
+	} else if (config->direction == DMA_DEV_TO_MEM) {
+		if (config->src_addr)
+			echan->addr = config->src_addr;
+		if (config->src_addr_width)
+			echan->addr_width = config->src_addr_width;
+		if (config->src_maxburst)
+			echan->maxburst = config->src_maxburst;
+	}
+
+	return 0;
+}
+
+static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			unsigned long arg)
+{
+	int ret = 0;
+	struct dma_slave_config *config;
+	struct edma_chan *echan = to_edma_chan(chan);
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		edma_terminate_all(echan);
+		break;
+	case DMA_SLAVE_CONFIG:
+		config = (struct dma_slave_config *)arg;
+		ret = edma_slave_config(echan, config);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	return ret;
+}
+
+static struct dma_async_tx_descriptor *edma_prep_slave_sg(
+	struct dma_chan *chan, struct scatterlist *sgl,
+	unsigned int sg_len, enum dma_transfer_direction direction,
+	unsigned long tx_flags, void *context)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = chan->device->dev;
+	struct edma_desc *edesc;
+	struct scatterlist *sg;
+	int i;
+	int acnt, bcnt, ccnt, src, dst, cidx;
+	int src_bidx, dst_bidx, src_cidx, dst_cidx;
+
+	if (unlikely(!echan || !sgl || !sg_len))
+		return NULL;
+
+	if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
+		dev_err(dev, "Undefined slave buswidth\n");
+		return NULL;
+	}
+
+	if (sg_len > MAX_NR_SG) {
+		dev_err(dev, "Exceeded max SG segments %d > %d\n",
+			sg_len, MAX_NR_SG);
+		return NULL;
+	}
+
+	edesc = kzalloc(sizeof(*edesc) + sg_len *
+		sizeof(edesc->pset[0]), GFP_ATOMIC);
+	if (!edesc) {
+		dev_dbg(dev, "Failed to allocate a descriptor\n");
+		return NULL;
+	}
+
+	edesc->pset_nr = sg_len;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		/* Allocate a PaRAM slot, if needed */
+		if (echan->slot[i] < 0) {
+			echan->slot[i] =
+				edma_alloc_slot(EDMA_CTLR(echan->ch_num),
+						EDMA_SLOT_ANY);
+			if (echan->slot[i] < 0) {
+				dev_err(dev, "Failed to allocate slot\n");
+				return NULL;
+			}
+		}
+
+		acnt = echan->addr_width;
+
+		/*
+		 * If the maxburst is equal to the fifo width, use
+		 * A-synced transfers. This allows for large contiguous
+		 * buffer transfers using only one PaRAM set.
+		 */
+		if (echan->maxburst == 1) {
+			edesc->absync = false;
+			ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
+			bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
+			if (bcnt)
+				ccnt++;
+			else
+				bcnt = SZ_64K - 1;
+			cidx = acnt;
+		/*
+		 * If maxburst is greater than the fifo address_width,
+		 * use AB-synced transfers where A count is the fifo
+		 * address_width and B count is the maxburst. In this
+		 * case, we are limited to transfers of C count frames
+		 * of (address_width * maxburst) where C count is limited
+		 * to SZ_64K-1. This places an upper bound on the length
+		 * of an SG segment that can be handled.
+		 */
+		} else {
+			edesc->absync = true;
+			bcnt = echan->maxburst;
+			ccnt = sg_dma_len(sg) / (acnt * bcnt);
+			if (ccnt > (SZ_64K - 1)) {
+				dev_err(dev, "Exceeded max SG segment size\n");
+				return NULL;
+			}
+			cidx = acnt * bcnt;
+		}
+
+		if (direction == DMA_MEM_TO_DEV) {
+			src = sg_dma_address(sg);
+			dst = echan->addr;
+			src_bidx = acnt;
+			src_cidx = cidx;
+			dst_bidx = 0;
+			dst_cidx = 0;
+		} else {
+			src = echan->addr;
+			dst = sg_dma_address(sg);
+			src_bidx = 0;
+			src_cidx = 0;
+			dst_bidx = acnt;
+			dst_cidx = cidx;
+		}
+
+		edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
+		/* Configure A or AB synchronized transfers */
+		if (edesc->absync)
+			edesc->pset[i].opt |= SYNCDIM;
+		/* If this is the last set, enable completion interrupt flag */
+		if (i == sg_len - 1)
+			edesc->pset[i].opt |= TCINTEN;
+
+		edesc->pset[i].src = src;
+		edesc->pset[i].dst = dst;
+
+		edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
+		edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
+
+		edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
+		edesc->pset[i].ccnt = ccnt;
+		edesc->pset[i].link_bcntrld = 0xffffffff;
+
+	}
+
+	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
+}
+
+static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
+{
+	struct edma_chan *echan = data;
+	struct device *dev = echan->vchan.chan.device->dev;
+	struct edma_desc *edesc;
+	unsigned long flags;
+
+	/* Stop the channel */
+	edma_stop(echan->ch_num);
+
+	switch (ch_status) {
+	case DMA_COMPLETE:
+		dev_dbg(dev, "transfer complete on channel %d\n", ch_num);
+
+		spin_lock_irqsave(&echan->vchan.lock, flags);
+
+		edesc = echan->edesc;
+		if (edesc) {
+			edma_execute(echan);
+			vchan_cookie_complete(&edesc->vdesc);
+		}
+
+		spin_unlock_irqrestore(&echan->vchan.lock, flags);
+
+		break;
+	case DMA_CC_ERROR:
+		dev_dbg(dev, "transfer error on channel %d\n", ch_num);
+		break;
+	default:
+		break;
+	}
+}
+
+/* Alloc channel resources */
+static int edma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = chan->device->dev;
+	int ret;
+	int a_ch_num;
+	LIST_HEAD(descs);
+
+	a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
+					chan, EVENTQ_DEFAULT);
+
+	if (a_ch_num < 0) {
+		ret = -ENODEV;
+		goto err_no_chan;
+	}
+
+	if (a_ch_num != echan->ch_num) {
+		dev_err(dev, "failed to allocate requested channel %u:%u\n",
+			EDMA_CTLR(echan->ch_num),
+			EDMA_CHAN_SLOT(echan->ch_num));
+		ret = -ENODEV;
+		goto err_wrong_chan;
+	}
+
+	echan->alloced = true;
+	echan->slot[0] = echan->ch_num;
+
+	dev_info(dev, "allocated channel for %u:%u\n",
+		 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
+
+	return 0;
+
+err_wrong_chan:
+	edma_free_channel(a_ch_num);
+err_no_chan:
+	return ret;
+}
+
+/* Free channel resources */
+static void edma_free_chan_resources(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct device *dev = chan->device->dev;
+	int i;
+
+	/* Terminate transfers */
+	edma_stop(echan->ch_num);
+
+	vchan_free_chan_resources(&echan->vchan);
+
+	/* Free EDMA PaRAM slots */
+	for (i = 1; i < EDMA_MAX_SLOTS; i++) {
+		if (echan->slot[i] >= 0) {
+			edma_free_slot(echan->slot[i]);
+			echan->slot[i] = -1;
+		}
+	}
+
+	/* Free EDMA channel */
+	if (echan->alloced) {
+		edma_free_channel(echan->ch_num);
+		echan->alloced = false;
+	}
+
+	dev_info(dev, "freeing channel for %u\n", echan->ch_num);
+}
+
+/* Send pending descriptor to hardware */
+static void edma_issue_pending(struct dma_chan *chan)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
+		edma_execute(echan);
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+}
+
+static size_t edma_desc_size(struct edma_desc *edesc)
+{
+	int i;
+	size_t size;
+
+	if (edesc->absync)
+		for (size = i = 0; i < edesc->pset_nr; i++)
+			size += (edesc->pset[i].a_b_cnt & 0xffff) *
+				(edesc->pset[i].a_b_cnt >> 16) *
+				 edesc->pset[i].ccnt;
+	else
+		size = (edesc->pset[0].a_b_cnt & 0xffff) *
+			(edesc->pset[0].a_b_cnt >> 16) +
+			(edesc->pset[0].a_b_cnt & 0xffff) *
+			(SZ_64K - 1) * edesc->pset[0].ccnt;
+
+	return size;
+}
+
+/* Check request completion status */
+static enum dma_status edma_tx_status(struct dma_chan *chan,
+				      dma_cookie_t cookie,
+				      struct dma_tx_state *txstate)
+{
+	struct edma_chan *echan = to_edma_chan(chan);
+	struct virt_dma_desc *vdesc;
+	enum dma_status ret;
+	unsigned long flags;
+
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret == DMA_SUCCESS || !txstate)
+		return ret;
+
+	spin_lock_irqsave(&echan->vchan.lock, flags);
+	vdesc = vchan_find_desc(&echan->vchan, cookie);
+	if (vdesc) {
+		txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
+	} else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
+		struct edma_desc *edesc = echan->edesc;
+		txstate->residue = edma_desc_size(edesc);
+	} else {
+		txstate->residue = 0;
+	}
+	spin_unlock_irqrestore(&echan->vchan.lock, flags);
+
+	return ret;
+}
+
+static void __init edma_chan_init(struct edma_cc *ecc,
+				  struct dma_device *dma,
+				  struct edma_chan *echans)
+{
+	int i, j;
+
+	for (i = 0; i < EDMA_CHANS; i++) {
+		struct edma_chan *echan = &echans[i];
+		echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
+		echan->ecc = ecc;
+		echan->vchan.desc_free = edma_desc_free;
+
+		vchan_init(&echan->vchan, dma);
+
+		INIT_LIST_HEAD(&echan->node);
+		for (j = 0; j < EDMA_MAX_SLOTS; j++)
+			echan->slot[j] = -1;
+	}
+}
+
+static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
+			  struct device *dev)
+{
+	dma->device_prep_slave_sg = edma_prep_slave_sg;
+	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
+	dma->device_free_chan_resources = edma_free_chan_resources;
+	dma->device_issue_pending = edma_issue_pending;
+	dma->device_tx_status = edma_tx_status;
+	dma->device_control = edma_control;
+	dma->dev = dev;
+
+	INIT_LIST_HEAD(&dma->channels);
+}
+
+static int __devinit edma_probe(struct platform_device *pdev)
+{
+	struct edma_cc *ecc;
+	int ret;
+
+	ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
+	if (!ecc) {
+		dev_err(&pdev->dev, "Can't allocate controller\n");
+		return -ENOMEM;
+	}
+
+	ecc->ctlr = pdev->id;
+	ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
+	if (ecc->dummy_slot < 0) {
+		dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
+		return -EIO;
+	}
+
+	dma_cap_zero(ecc->dma_slave.cap_mask);
+	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
+
+	edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
+
+	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
+
+	ret = dma_async_device_register(&ecc->dma_slave);
+	if (ret)
+		goto err_reg1;
+
+	platform_set_drvdata(pdev, ecc);
+
+	dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
+
+	return 0;
+
+err_reg1:
+	edma_free_slot(ecc->dummy_slot);
+	return ret;
+}
+
+static int __devexit edma_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct edma_cc *ecc = dev_get_drvdata(dev);
+
+	dma_async_device_unregister(&ecc->dma_slave);
+	edma_free_slot(ecc->dummy_slot);
+
+	return 0;
+}
+
+static struct platform_driver edma_driver = {
+	.probe		= edma_probe,
+	.remove		= __devexit_p(edma_remove),
+	.driver = {
+		.name = "edma-dma-engine",
+		.owner = THIS_MODULE,
+	},
+};
+
+bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	if (chan->device->dev->driver == &edma_driver.driver) {
+		struct edma_chan *echan = to_edma_chan(chan);
+		unsigned ch_req = *(unsigned *)param;
+		return ch_req == echan->ch_num;
+	}
+	return false;
+}
+EXPORT_SYMBOL(edma_filter_fn);
+
+static struct platform_device *pdev0, *pdev1;
+
+static const struct platform_device_info edma_dev_info0 = {
+	.name = "edma-dma-engine",
+	.id = 0,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
+static const struct platform_device_info edma_dev_info1 = {
+	.name = "edma-dma-engine",
+	.id = 1,
+	.dma_mask = DMA_BIT_MASK(32),
+};
+
+static int edma_init(void)
+{
+	int ret = platform_driver_register(&edma_driver);
+
+	if (ret == 0) {
+		pdev0 = platform_device_register_full(&edma_dev_info0);
+		if (IS_ERR(pdev0)) {
+			platform_driver_unregister(&edma_driver);
+			ret = PTR_ERR(pdev0);
+			goto out;
+		}
+	}
+
+	if (EDMA_CTLRS == 2) {
+		pdev1 = platform_device_register_full(&edma_dev_info1);
+		if (IS_ERR(pdev1)) {
+			platform_driver_unregister(&edma_driver);
+			platform_device_unregister(pdev0);
+			ret = PTR_ERR(pdev1);
+		}
+	}
+
+out:
+	return ret;
+}
+subsys_initcall(edma_init);
+
+static void __exit edma_exit(void)
+{
+	platform_device_unregister(pdev0);
+	if (pdev1)
+		platform_device_unregister(pdev1);
+	platform_driver_unregister(&edma_driver);
+}
+module_exit(edma_exit);
+
+MODULE_AUTHOR("Matt Porter <mporter at ti.com>");
+MODULE_DESCRIPTION("TI EDMA DMA engine driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/edma.h b/include/linux/edma.h
new file mode 100644
index 0000000..a1307e7
--- /dev/null
+++ b/include/linux/edma.h
@@ -0,0 +1,29 @@
+/*
+ * TI EDMA DMA engine driver
+ *
+ * Copyright 2012 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __LINUX_EDMA_H
+#define __LINUX_EDMA_H
+
+struct dma_chan;
+
+#if defined(CONFIG_TI_EDMA) || defined(CONFIG_TI_EDMA_MODULE)
+bool edma_filter_fn(struct dma_chan *, void *);
+#else
+static inline bool edma_filter_fn(struct dma_chan *chan, void *param)
+{
+	return false;
+}
+#endif
+
+#endif
-- 
1.7.9.5



From mporter at ti.com  Wed Aug 22 21:09:35 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 21:09:35 -0400
Subject: [PATCH v3 2/3] mmc: davinci_mmc: convert to DMA engine API
In-Reply-To: <1345684176-21472-1-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
Message-ID: <1345684176-21472-3-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/mmc/host/davinci_mmc.c |  271 ++++++++++++----------------------------
 1 file changed, 82 insertions(+), 189 deletions(-)

diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 7cf6c62..c5e1eeb 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -30,11 +30,12 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/mmc/mmc.h>
 
 #include <mach/mmc.h>
-#include <mach/edma.h>
 
 /*
  * Register Definitions
@@ -200,21 +201,13 @@ struct mmc_davinci_host {
 	u32 bytes_left;
 
 	u32 rxdma, txdma;
+	struct dma_chan *dma_tx;
+	struct dma_chan *dma_rx;
 	bool use_dma;
 	bool do_dma;
 	bool sdio_int;
 	bool active_request;
 
-	/* Scatterlist DMA uses one or more parameter RAM entries:
-	 * the main one (associated with rxdma or txdma) plus zero or
-	 * more links.  The entries for a given transfer differ only
-	 * by memory buffer (address, length) and link field.
-	 */
-	struct edmacc_param	tx_template;
-	struct edmacc_param	rx_template;
-	unsigned		n_link;
-	u32			links[MAX_NR_SG - 1];
-
 	/* For PIO we walk scatterlists one segment at a time. */
 	unsigned int		sg_len;
 	struct scatterlist *sg;
@@ -410,153 +403,74 @@ static void mmc_davinci_start_command(struct mmc_davinci_host *host,
 
 static void davinci_abort_dma(struct mmc_davinci_host *host)
 {
-	int sync_dev;
+	struct dma_chan *sync_dev;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
-		sync_dev = host->rxdma;
+		sync_dev = host->dma_rx;
 	else
-		sync_dev = host->txdma;
-
-	edma_stop(sync_dev);
-	edma_clean_channel(sync_dev);
-}
-
-static void
-mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
-
-static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
-{
-	if (DMA_COMPLETE != ch_status) {
-		struct mmc_davinci_host *host = data;
-
-		/* Currently means:  DMA Event Missed, or "null" transfer
-		 * request was seen.  In the future, TC errors (like bad
-		 * addresses) might be presented too.
-		 */
-		dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
-			(host->data->flags & MMC_DATA_WRITE)
-				? "write" : "read");
-		host->data->error = -EIO;
-		mmc_davinci_xfer_done(host, host->data);
-	}
-}
-
-/* Set up tx or rx template, to be modified and updated later */
-static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
-		bool tx, struct edmacc_param *template)
-{
-	unsigned	sync_dev;
-	const u16	acnt = 4;
-	const u16	bcnt = rw_threshold >> 2;
-	const u16	ccnt = 0;
-	u32		src_port = 0;
-	u32		dst_port = 0;
-	s16		src_bidx, dst_bidx;
-	s16		src_cidx, dst_cidx;
-
-	/*
-	 * A-B Sync transfer:  each DMA request is for one "frame" of
-	 * rw_threshold bytes, broken into "acnt"-size chunks repeated
-	 * "bcnt" times.  Each segment needs "ccnt" such frames; since
-	 * we tell the block layer our mmc->max_seg_size limit, we can
-	 * trust (later) that it's within bounds.
-	 *
-	 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
-	 * EDMA will optimize memory operations to use larger bursts.
-	 */
-	if (tx) {
-		sync_dev = host->txdma;
-
-		/* src_prt, ccnt, and link to be set up later */
-		src_bidx = acnt;
-		src_cidx = acnt * bcnt;
-
-		dst_port = host->mem_res->start + DAVINCI_MMCDXR;
-		dst_bidx = 0;
-		dst_cidx = 0;
-	} else {
-		sync_dev = host->rxdma;
-
-		src_port = host->mem_res->start + DAVINCI_MMCDRR;
-		src_bidx = 0;
-		src_cidx = 0;
-
-		/* dst_prt, ccnt, and link to be set up later */
-		dst_bidx = acnt;
-		dst_cidx = acnt * bcnt;
-	}
-
-	/*
-	 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
-	 * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
-	 * parameter is ignored.
-	 */
-	edma_set_src(sync_dev, src_port, INCR, W8BIT);
-	edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
+		sync_dev = host->dma_tx;
 
-	edma_set_src_index(sync_dev, src_bidx, src_cidx);
-	edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
-
-	edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
-
-	edma_read_slot(sync_dev, template);
-
-	/* don't bother with irqs or chaining */
-	template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
+	dmaengine_terminate_all(sync_dev);
 }
 
-static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
+static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
 		struct mmc_data *data)
 {
-	struct edmacc_param	*template;
-	int			channel, slot;
-	unsigned		link;
-	struct scatterlist	*sg;
-	unsigned		sg_len;
-	unsigned		bytes_left = host->bytes_left;
-	const unsigned		shift = ffs(rw_threshold) - 1;
+	struct dma_chan *chan;
+	struct dma_async_tx_descriptor *desc;
+	int ret = 0;
 
 	if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
-		template = &host->tx_template;
-		channel = host->txdma;
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
+			.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.dst_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_tx;
+		dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_tx,
+				data->sg,
+				host->sg_len,
+				DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA TX descriptor");
+			ret = -1;
+			goto out;
+		}
 	} else {
-		template = &host->rx_template;
-		channel = host->rxdma;
-	}
-
-	/* We know sg_len and ccnt will never be out of range because
-	 * we told the mmc layer which in turn tells the block layer
-	 * to ensure that it only hands us one scatterlist segment
-	 * per EDMA PARAM entry.  Update the PARAM
-	 * entries needed for each segment of this scatterlist.
-	 */
-	for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
-			sg_len-- != 0 && bytes_left;
-			sg = sg_next(sg), slot = host->links[link++]) {
-		u32		buf = sg_dma_address(sg);
-		unsigned	count = sg_dma_len(sg);
-
-		template->link_bcntrld = sg_len
-				? (EDMA_CHAN_SLOT(host->links[link]) << 5)
-				: 0xffff;
-
-		if (count > bytes_left)
-			count = bytes_left;
-		bytes_left -= count;
-
-		if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
-			template->src = buf;
-		else
-			template->dst = buf;
-		template->ccnt = count >> shift;
-
-		edma_write_slot(slot, template);
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = host->mem_res->start + DAVINCI_MMCDRR,
+			.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+			.src_maxburst =
+				rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
+		};
+		chan = host->dma_rx;
+		dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
+
+		desc = dmaengine_prep_slave_sg(host->dma_rx,
+				data->sg,
+				host->sg_len,
+				DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_dbg(mmc_dev(host->mmc),
+				"failed to allocate DMA RX descriptor");
+			ret = -1;
+			goto out;
+		}
 	}
 
-	if (host->version == MMC_CTLR_VERSION_2)
-		edma_clear_event(channel);
+	dmaengine_submit(desc);
+	dma_async_issue_pending(chan);
 
-	edma_start(channel);
+out:
+	return ret;
 }
 
 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
@@ -564,6 +478,7 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 {
 	int i;
 	int mask = rw_threshold - 1;
+	int ret = 0;
 
 	host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 				((data->flags & MMC_DATA_WRITE)
@@ -583,70 +498,48 @@ static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
 	}
 
 	host->do_dma = 1;
-	mmc_davinci_send_dma_request(host, data);
+	ret = mmc_davinci_send_dma_request(host, data);
 
-	return 0;
+	return ret;
 }
 
 static void __init_or_module
 davinci_release_dma_channels(struct mmc_davinci_host *host)
 {
-	unsigned	i;
-
 	if (!host->use_dma)
 		return;
 
-	for (i = 0; i < host->n_link; i++)
-		edma_free_slot(host->links[i]);
-
-	edma_free_channel(host->txdma);
-	edma_free_channel(host->rxdma);
+	dma_release_channel(host->dma_tx);
+	dma_release_channel(host->dma_rx);
 }
 
 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
 {
-	u32 link_size;
-	int r, i;
-
-	/* Acquire master DMA write channel */
-	r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"tx", r);
-		return r;
-	}
-	mmc_davinci_dma_setup(host, true, &host->tx_template);
-
-	/* Acquire master DMA read channel */
-	r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
-				"rx", r);
-		goto free_master_write;
+	int r;
+	dma_cap_mask_t mask;
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	host->dma_tx =
+		dma_request_channel(mask, edma_filter_fn, &host->txdma);
+	if (!host->dma_tx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
+		return -ENODEV;
 	}
-	mmc_davinci_dma_setup(host, false, &host->rx_template);
 
-	/* Allocate parameter RAM slots, which will later be bound to a
-	 * channel as needed to handle a scatterlist.
-	 */
-	link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
-	for (i = 0; i < link_size; i++) {
-		r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
-		if (r < 0) {
-			dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
-				r);
-			break;
-		}
-		host->links[i] = r;
+	host->dma_rx =
+		dma_request_channel(mask, edma_filter_fn, &host->rxdma);
+	if (!host->dma_rx) {
+		dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
+		r = -ENODEV;
+		goto free_master_write;
 	}
-	host->n_link = i;
 
 	return 0;
 
 free_master_write:
-	edma_free_channel(host->txdma);
+	dma_release_channel(host->dma_tx);
 
 	return r;
 }
@@ -1359,7 +1252,7 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
 	 * Each hw_seg uses one EDMA parameter RAM slot, always one
 	 * channel and then usually some linked slots.
 	 */
-	mmc->max_segs		= 1 + host->n_link;
+	mmc->max_segs		= MAX_NR_SG;
 
 	/* EDMA limit per hw segment (one or two MBytes) */
 	mmc->max_seg_size	= MAX_CCNT * rw_threshold;
-- 
1.7.9.5



From mporter at ti.com  Wed Aug 22 21:09:36 2012
From: mporter at ti.com (Matt Porter)
Date: Wed, 22 Aug 2012 21:09:36 -0400
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345684176-21472-1-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
Message-ID: <1345684176-21472-4-git-send-email-mporter@ti.com>

Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.

Signed-off-by: Matt Porter <mporter at ti.com>
---
 drivers/spi/spi-davinci.c |  292 ++++++++++++++++++++-------------------------
 1 file changed, 130 insertions(+), 162 deletions(-)

diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 9b2901f..c1ec52d 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -25,13 +25,14 @@
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
+#include <linux/edma.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
 #include <mach/spi.h>
-#include <mach/edma.h>
 
 #define SPI_NO_RESOURCE		((resource_size_t)-1)
 
@@ -113,14 +114,6 @@
 #define SPIDEF		0x4c
 #define SPIFMT0		0x50
 
-/* We have 2 DMA channels per CS, one for RX and one for TX */
-struct davinci_spi_dma {
-	int			tx_channel;
-	int			rx_channel;
-	int			dummy_param_slot;
-	enum dma_event_q	eventq;
-};
-
 /* SPI Controller driver's private data. */
 struct davinci_spi {
 	struct spi_bitbang	bitbang;
@@ -134,11 +127,14 @@ struct davinci_spi {
 
 	const void		*tx;
 	void			*rx;
-#define SPI_TMP_BUFSZ	(SMP_CACHE_BYTES + 1)
-	u8			rx_tmp_buf[SPI_TMP_BUFSZ];
 	int			rcount;
 	int			wcount;
-	struct davinci_spi_dma	dma;
+
+	struct dma_chan		*dma_rx;
+	struct dma_chan		*dma_tx;
+	int			dma_rx_chnum;
+	int			dma_tx_chnum;
+
 	struct davinci_spi_platform_data *pdata;
 
 	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
@@ -496,21 +492,23 @@ out:
 	return errors;
 }
 
-static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
+static void davinci_spi_dma_rx_callback(void *data)
 {
-	struct davinci_spi *dspi = data;
-	struct davinci_spi_dma *dma = &dspi->dma;
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
 
-	edma_stop(lch);
+	dspi->rcount = 0;
 
-	if (status == DMA_COMPLETE) {
-		if (lch == dma->rx_channel)
-			dspi->rcount = 0;
-		if (lch == dma->tx_channel)
-			dspi->wcount = 0;
-	}
+	if (!dspi->wcount && !dspi->rcount)
+		complete(&dspi->done);
+}
 
-	if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
+static void davinci_spi_dma_tx_callback(void *data)
+{
+	struct davinci_spi *dspi = (struct davinci_spi *)data;
+
+	dspi->wcount = 0;
+
+	if (!dspi->wcount && !dspi->rcount)
 		complete(&dspi->done);
 }
 
@@ -526,20 +524,20 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
 	struct davinci_spi *dspi;
-	int data_type, ret;
+	int data_type, ret = -ENOMEM;
 	u32 tx_data, spidat1;
 	u32 errors = 0;
 	struct davinci_spi_config *spicfg;
 	struct davinci_spi_platform_data *pdata;
 	unsigned uninitialized_var(rx_buf_count);
-	struct device *sdev;
+	void *dummy_buf = NULL;
+	struct scatterlist sg_rx, sg_tx;
 
 	dspi = spi_master_get_devdata(spi->master);
 	pdata = dspi->pdata;
 	spicfg = (struct davinci_spi_config *)spi->controller_data;
 	if (!spicfg)
 		spicfg = &davinci_spi_default_cfg;
-	sdev = dspi->bitbang.master->dev.parent;
 
 	/* convert len to words based on bits_per_word */
 	data_type = dspi->bytes_per_word[spi->chip_select];
@@ -567,112 +565,83 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 		spidat1 |= tx_data & 0xFFFF;
 		iowrite32(spidat1, dspi->base + SPIDAT1);
 	} else {
-		struct davinci_spi_dma *dma;
-		unsigned long tx_reg, rx_reg;
-		struct edmacc_param param;
-		void *rx_buf;
-		int b, c;
-
-		dma = &dspi->dma;
-
-		tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
-		rx_reg = (unsigned long)dspi->pbase + SPIBUF;
-
-		/*
-		 * Transmit DMA setup
-		 *
-		 * If there is transmit data, map the transmit buffer, set it
-		 * as the source of data and set the source B index to data
-		 * size. If there is no transmit data, set the transmit register
-		 * as the source of data, and set the source B index to zero.
-		 *
-		 * The destination is always the transmit register itself. And
-		 * the destination never increments.
-		 */
-
-		if (t->tx_buf) {
-			t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
-						t->len, DMA_TO_DEVICE);
-			if (dma_mapping_error(&spi->dev, t->tx_dma)) {
-				dev_dbg(sdev, "Unable to DMA map %d bytes"
-						"TX buffer\n", t->len);
-				return -ENOMEM;
-			}
-		}
-
-		/*
-		 * If number of words is greater than 65535, then we need
-		 * to configure a 3 dimension transfer.  Use the BCNTRLD
-		 * feature to allow for transfers that aren't even multiples
-		 * of 65535 (or any other possible b size) by first transferring
-		 * the remainder amount then grabbing the next N blocks of
-		 * 65535 words.
-		 */
-
-		c = dspi->wcount / (SZ_64K - 1);	/* N 65535 Blocks */
-		b = dspi->wcount - c * (SZ_64K - 1);	/* Remainder */
-		if (b)
-			c++;
+		struct dma_slave_config dma_rx_conf = {
+			.direction = DMA_DEV_TO_MEM,
+			.src_addr = (unsigned long)dspi->pbase + SPIBUF,
+			.src_addr_width = data_type,
+			.src_maxburst = 1,
+		};
+		struct dma_slave_config dma_tx_conf = {
+			.direction = DMA_MEM_TO_DEV,
+			.dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
+			.dst_addr_width = data_type,
+			.dst_maxburst = 1,
+		};
+		struct dma_async_tx_descriptor *rxdesc;
+		struct dma_async_tx_descriptor *txdesc;
+		void *buf;
+
+		dummy_buf = kzalloc(t->len, GFP_KERNEL);
+		if (!dummy_buf)
+			goto err_alloc_dummy_buf;
+
+		dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
+		dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
+
+		sg_init_table(&sg_rx, 1);
+		if (!t->rx_buf)
+			buf = dummy_buf;
 		else
-			b = SZ_64K - 1;
-
-		param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
-		param.src = t->tx_buf ? t->tx_dma : tx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = tx_reg;
-		param.src_dst_bidx = t->tx_buf ? data_type : 0;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = t->tx_buf ? data_type : 0;
-		param.ccnt = c;
-		edma_write_slot(dma->tx_channel, &param);
-		edma_link(dma->tx_channel, dma->dummy_param_slot);
-
-		/*
-		 * Receive DMA setup
-		 *
-		 * If there is receive buffer, use it to receive data. If there
-		 * is none provided, use a temporary receive buffer. Set the
-		 * destination B index to 0 so effectively only one byte is used
-		 * in the temporary buffer (address does not increment).
-		 *
-		 * The source of receive data is the receive data register. The
-		 * source address never increments.
-		 */
-
-		if (t->rx_buf) {
-			rx_buf = t->rx_buf;
-			rx_buf_count = t->len;
-		} else {
-			rx_buf = dspi->rx_tmp_buf;
-			rx_buf_count = sizeof(dspi->rx_tmp_buf);
+			buf = t->rx_buf;
+		t->rx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->rx_dma) {
+			ret = -EFAULT;
+			goto err_rx_map;
 		}
+		sg_dma_address(&sg_rx) = t->rx_dma;
+		sg_dma_len(&sg_rx) = t->len;
 
-		t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
-							DMA_FROM_DEVICE);
-		if (dma_mapping_error(&spi->dev, t->rx_dma)) {
-			dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
-								rx_buf_count);
-			if (t->tx_buf)
-				dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-			return -ENOMEM;
+		sg_init_table(&sg_tx, 1);
+		if (!t->tx_buf)
+			buf = dummy_buf;
+		else
+			buf = (void *)t->tx_buf;
+		t->tx_dma = dma_map_single(&spi->dev, buf,
+				t->len, DMA_FROM_DEVICE);
+		if (!t->tx_dma) {
+			ret = -EFAULT;
+			goto err_tx_map;
 		}
-
-		param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
-		param.src = rx_reg;
-		param.a_b_cnt = b << 16 | data_type;
-		param.dst = t->rx_dma;
-		param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
-		param.link_bcntrld = 0xffffffff;
-		param.src_dst_cidx = (t->rx_buf ? data_type : 0) << 16;
-		param.ccnt = c;
-		edma_write_slot(dma->rx_channel, &param);
+		sg_dma_address(&sg_tx) = t->tx_dma;
+		sg_dma_len(&sg_tx) = t->len;
+
+		rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
+				&sg_rx, 1, DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!rxdesc)
+			goto err_desc;
+
+		txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
+				&sg_tx, 1, DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!txdesc)
+			goto err_desc;
+
+		rxdesc->callback = davinci_spi_dma_rx_callback;
+		rxdesc->callback_param = (void *)dspi;
+		txdesc->callback = davinci_spi_dma_tx_callback;
+		txdesc->callback_param = (void *)dspi;
 
 		if (pdata->cshold_bug)
 			iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
 
-		edma_start(dma->rx_channel);
-		edma_start(dma->tx_channel);
+		dmaengine_submit(rxdesc);
+		dmaengine_submit(txdesc);
+
+		dma_async_issue_pending(dspi->dma_rx);
+		dma_async_issue_pending(dspi->dma_tx);
+
 		set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
 	}
 
@@ -690,15 +659,13 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 
 	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
 	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
-
-		if (t->tx_buf)
-			dma_unmap_single(&spi->dev, t->tx_dma, t->len,
-								DMA_TO_DEVICE);
-
-		dma_unmap_single(&spi->dev, t->rx_dma, rx_buf_count,
-							DMA_FROM_DEVICE);
-
 		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
+
+		dma_unmap_single(&spi->dev, t->rx_dma,
+				t->len, DMA_FROM_DEVICE);
+		dma_unmap_single(&spi->dev, t->tx_dma,
+				t->len, DMA_TO_DEVICE);
+		kfree(dummy_buf);
 	}
 
 	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
@@ -716,11 +683,20 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 	}
 
 	if (dspi->rcount != 0 || dspi->wcount != 0) {
-		dev_err(sdev, "SPI data transfer error\n");
+		dev_err(&spi->dev, "SPI data transfer error\n");
 		return -EIO;
 	}
 
 	return t->len;
+
+err_desc:
+	dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
+err_tx_map:
+	dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
+err_rx_map:
+	kfree(dummy_buf);
+err_alloc_dummy_buf:
+	return ret;
 }
 
 /**
@@ -751,39 +727,33 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *data)
 
 static int davinci_spi_request_dma(struct davinci_spi *dspi)
 {
+	dma_cap_mask_t mask;
+	struct device *sdev = dspi->bitbang.master->dev.parent;
 	int r;
-	struct davinci_spi_dma *dma = &dspi->dma;
 
-	r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI RX\n");
-		r = -EAGAIN;
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_rx_chnum);
+	if (!dspi->dma_rx) {
+		dev_err(sdev, "request RX DMA channel failed\n");
+		r = -ENODEV;
 		goto rx_dma_failed;
 	}
 
-	r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		pr_err("Unable to request DMA channel for SPI TX\n");
-		r = -EAGAIN;
+	dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
+					   &dspi->dma_tx_chnum);
+	if (!dspi->dma_tx) {
+		dev_err(sdev, "request TX DMA channel failed\n");
+		r = -ENODEV;
 		goto tx_dma_failed;
 	}
 
-	r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
-	if (r < 0) {
-		pr_err("Unable to request SPI TX DMA param slot\n");
-		r = -EAGAIN;
-		goto param_failed;
-	}
-	dma->dummy_param_slot = r;
-	edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
-
 	return 0;
-param_failed:
-	edma_free_channel(dma->tx_channel);
+
 tx_dma_failed:
-	edma_free_channel(dma->rx_channel);
+	dma_release_channel(dspi->dma_rx);
 rx_dma_failed:
 	return r;
 }
@@ -898,9 +868,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	dspi->bitbang.txrx_bufs = davinci_spi_bufs;
 	if (dma_rx_chan != SPI_NO_RESOURCE &&
 	    dma_tx_chan != SPI_NO_RESOURCE) {
-		dspi->dma.rx_channel = dma_rx_chan;
-		dspi->dma.tx_channel = dma_tx_chan;
-		dspi->dma.eventq = pdata->dma_event_q;
+		dspi->dma_rx_chnum = dma_rx_chan;
+		dspi->dma_tx_chnum = dma_tx_chan;
 
 		ret = davinci_spi_request_dma(dspi);
 		if (ret)
@@ -955,9 +924,8 @@ static int __devinit davinci_spi_probe(struct platform_device *pdev)
 	return ret;
 
 free_dma:
-	edma_free_channel(dspi->dma.tx_channel);
-	edma_free_channel(dspi->dma.rx_channel);
-	edma_free_slot(dspi->dma.dummy_param_slot);
+	dma_release_channel(dspi->dma_rx);
+	dma_release_channel(dspi->dma_tx);
 free_clk:
 	clk_disable(dspi->clk);
 	clk_put(dspi->clk);
-- 
1.7.9.5



From shawn.guo at linaro.org  Wed Aug 22 21:32:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 09:32:53 +0800
Subject: Can one  set GPIO direction in pinmux definition?
In-Reply-To: <503558B8.4010603@grid-net.com>
References: <5034FCB2.5040709@grid-net.com> <5035388D.2060909@wwwdotorg.org>
 <503558B8.4010603@grid-net.com>
Message-ID: <20120823013250.GY24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 03:10:00PM -0700, Subodh Nijsure wrote:
> Right now that is what I am doing in my code, requesting GPIOs in
> UART drivers and setting up the direction. I just wanted to make
> sure there wasn't way to setup pin direction using pinmux itself.
> 
No, there is no way for pinctrl driver to set up gpio direction, which
is completely gpio driver's job.

-- 
Regards,
Shawn


From robherring2 at gmail.com  Wed Aug 22 21:32:19 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 22 Aug 2012 20:32:19 -0500
Subject: [PATCH 2/2] ARM: imx6q: replace clk_register_clkdev with clock
 DT lookup
In-Reply-To: <CAKGA1bnCk=FqANsVFD123y3uP5dn9AMZydR__mMXrzh6StrBjg@mail.gmail.com>
References: <1345104526-14797-1-git-send-email-shawn.guo@linaro.org>
 <1345104526-14797-3-git-send-email-shawn.guo@linaro.org>
 <503232E0.3000007@gmail.com>
 <CAKGA1bn2uCWE8YkGR4EzTxZ_bXJ_ov2diq63uxQ=dT7b6Fu9GQ@mail.gmail.com>
 <20120820151609.GN24242@S2101-09.ap.freescale.net>
 <CAKGA1bnfhMC8QG9OqBbpy5iq6ZAfEgrYMg_LVd50U7yikLhDAg@mail.gmail.com>
 <503384E3.4030705@calxeda.com>
 <CAKGA1bkNGJhsCGVBsHnaQn=Dg5T==QP_JnqOXycq8jQn-W-0Kw@mail.gmail.com>
 <CAKGA1bnCk=FqANsVFD123y3uP5dn9AMZydR__mMXrzh6StrBjg@mail.gmail.com>
Message-ID: <50358823.90400@gmail.com>

On 08/22/2012 07:08 PM, Matt Sealey wrote:
> Ugh. Okay my blood sugar was super low. Can I just condense that into
> I agree with Russell and the binding makes no sense once it gets past
> the simple definition described in the binding?

I can't speak for Russell, but I think his issue is addressed in v2.

> If we take the pinctrl mess as an example, all the DT serves to do is
> define an SoC-specific or family-specific binding into data the
> pinctrl subsystem can use, via an SoC-specific abstraction in a driver
> to make a generic subsystem in Linux work the way it should.

pinctrl changes much more board to board, so it's more valuable to have
in device tree. The changes from board to board in the clock tree are
much less.

> The common clock subsystem is no different - divider, fixed factor,
> fixed rate, mux, gate, highbank (??) are defined in a way that
> abstracts most of the actual SoC-specific stuff out to register
> offsets, values, bit definitions and masks.
> 
> Right now for i.MX we have several abstraction interfaces
> (imx_clk_XXX) which move values from tables around and call the
> appropriate common clock function to register the clock. These
> abstractions are identical for all the possible i.MX SoCs
> (imx_clk_gate2, imx_clk_mux etc.) and move the values around so they
> can be passed to clk_register_##same.
> 
> So if we can define a fixed-clock, why can't we define an
> fsl,gated-clock or fsl,muxed-clock which defines an i.MX clock of that
> type, and a much smaller subset of code that stuffs these values in
> through a small abstraction and remove all these seperate
> clk-imx51-imx53.c, clk-imx6q.c, clk-imx31.c files which are sharing
> common functionality into one mega-abstraction which works across the
> whole family?
>
> The way I understand the binding right now (and I'm looking at this;
> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob_plain;f=Documentation/devicetree/bindings/clock/clock-bindings.txt;hb=766e6a4ec602d0c107553b91b3434fe9c03474f4),
> this is entirely what the clock binding is saying we should do. But I
> don't understand why we're naming inputs and outputs, but not defining
> how these signals are routed (possibly through gate bits in registers)
> and leaving that down to some driver somewhere. Or why we have to name
> clocks twice, once for the canonical name of the output in reference
> to a higher level or root clock "uart_serial", vs. a driver-level name
> for that input or output in the driver ("per"), since most clocks at
> the driver level can't be re-used for other things anyway. If they
> could, the whole prepare/unprepare and some explicit parenting/muxing
> of clocks would handle that anyway so that the clock was enabled while
> there was at least one user.

The binding defines connections on clocks between nodes. Whether this is
a single clock controller node with many outputs or a node per mux,
divider, gate, etc. is up to the implementer. I did the latter on
highbank because I've got about 8 clocks and half are the same (pll
outputs). Having worked on many generations of iMX and knowing all the
pitfalls of their clock controllers, I would do exactly what Shawn has
done for any part with complex clock trees. I don't think trying to
abstract things to completely generic code will be worth the effort or
be able to describe all the interactions between clocks.

The value in device tree is handling board differences as there are 10's
of boards per SOC.

> I do understand that in Shawn's patch and using UART as an example
> again, "ipg" and "per" are definitely needed by the driver, and these
> names are defined by the driver and implicit in the documentation to
> enable the use of this unit, but at the end of the day the definition
> at the *device* level (uart@) makes no sense except to perform a
> lookup on a string, and in the end this string lookup only gets done
> at the driver probe time anyway. With a standard definition of these
> "ipg" and "per" strings per family of SoC or even in a generic fashion
> across all possible SoCs (in this case, both are defined using
> imx_clk_gate2()) then a node defining that clock and it's magical
> driver-specific name would work just as well by phandle reference, and
> it's parents are referenced by phandle, and all this stays within
> SoC-specific abstraction of the common clocks and turns into normal
> common clock structure stuff anyway (so you still get to do a string
> lookup, but it's being stuffed by an i.MX driver and registered from
> data it pulled from the DT).

Why don't you read v2 which removes the strings.

> Wouldn't we rather have a single device tree parser and clock
> registration for i.MX than the current 7 which would get split into 7
> clock registration drivers with some helpers that parsed half of it
> via device tree? I don't really see what benefit you get out of going
> for the halfway-defined model.

All this has been discussed already over the 2 years of iterations of
common struct clock and clock bindings.

Rob


From robherring2 at gmail.com  Wed Aug 22 21:42:37 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 22 Aug 2012 20:42:37 -0500
Subject: [PATCH v2 1/4] clk: add of_clk_src_onecell_get() support
In-Reply-To: <1345642590-29905-2-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
 <1345642590-29905-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <50358A8D.3090803@gmail.com>

On 08/22/2012 08:36 AM, Shawn Guo wrote:
> For those SoCs that have hundreds of clock outputs, their clock
> DT bindings could reasonably define #clock-cells as 1 and require
> the client device specify the index of the clock it consumes in the
> cell of its "clocks" phandle.
> 
> Add a generic of_clk_src_onecell_get() function for this purpose.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---

I have some reservations about how generic this will end up being, but
we have to start somewhere. So, for the series:

Reviewed-by: Rob Herring <rob.herring at calxeda.com>

>  drivers/clk/clk.c            |   14 ++++++++++++++
>  include/linux/clk-provider.h |    5 +++++
>  2 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index efdfd00..308f058 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1582,6 +1582,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
>  }
>  EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
>  
> +struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
> +{
> +	struct clk_onecell_data *clk_data = data;
> +	unsigned int idx = clkspec->args[0];
> +
> +	if (idx >= clk_data->clk_num) {
> +		pr_err("%s: invalid clock index %d\n", __func__, idx);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return clk_data->clks[idx];
> +}
> +EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
> +
>  /**
>   * of_clk_add_provider() - Register a clock provider for a node
>   * @np: Device node pointer associated with clock provider
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 77335fa..8fe6ec7 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -360,6 +360,11 @@ int of_clk_add_provider(struct device_node *np,
>  void of_clk_del_provider(struct device_node *np);
>  struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
>  				  void *data);
> +struct clk_onecell_data {
> +	struct clk **clks;
> +	unsigned int clk_num;
> +};
> +struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
>  const char *of_clk_get_parent_name(struct device_node *np, int index);
>  void of_clk_init(const struct of_device_id *matches);
>  
> 



From shawn.guo at linaro.org  Wed Aug 22 22:02:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 10:02:24 +0800
Subject: [PATCH 1/3] ARM: mxs: Rename 'hog-gpios'
In-Reply-To: <1345652733-13265-1-git-send-email-festevam@gmail.com>
References: <1345652733-13265-1-git-send-email-festevam@gmail.com>
Message-ID: <20120823020220.GZ24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 01:25:31PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> hog_pins is used to setup the pin functions, and it is not neccesarily used only
> for GPIO pins, so use only 'hog' to describe a more generic term.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied all 3 patches, thanks.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Wed Aug 22 22:07:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 10:07:48 +0800
Subject: [PATCH 3/6] ARM: imx: build pm-imx5 code only when PM is enabled
In-Reply-To: <1345648390-4234-4-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-4-git-send-email-arnd@arndb.de>
Message-ID: <20120823020746.GA24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 05:13:07PM +0200, Arnd Bergmann wrote:
> This moves the imx5 pm code out of the list of unconditionally
> compiled files for imx5, mirroring what we already do for imx6
> and how it was done before the code was move from mach-mx5 to
> mach-imx in v3.3.
> 
> Without this patch, building with CONFIG_PM disabled results in:
> 
> arch/arm/mach-imx/pm-imx5.c:202:116: error: redefinition of 'imx51_pm_init'
> arch/arm/mach-imx/include/mach-imx/common.h:154:91: note: previous definition of 'imx51_pm_init' was here
> arch/arm/mach-imx/pm-imx5.c:209:116: error: redefinition of 'imx53_pm_init'
> arch/arm/mach-imx/include/mach-imx/common.h:155:91: note: previous definition of 'imx53_pm_init' was here
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: stable at vger.kernel.org

Acked-by: Shawn Guo <shawn.guo at linaro.org>


From shawn.guo at linaro.org  Wed Aug 22 22:10:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 10:10:20 +0800
Subject: [PATCH 4/6] ARM: imx: fix ksz9021rn_phy_fixup
In-Reply-To: <1345648390-4234-5-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-5-git-send-email-arnd@arndb.de>
Message-ID: <20120823021017.GB24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 05:13:08PM +0200, Arnd Bergmann wrote:
> The ksz9021rn_phy_fixup and mx6q_sabrelite functions try to
> set up an ethernet phy if they can. They do check whether
> phylib is enabled, but unfortunately the functions can only
> be called from platform code if phylib is builtin, not
> if it is a module
> 
> Without this patch, building with a modular phylib results in:
> 
> arch/arm/mach-imx/mach-imx6q.c: In function 'imx6q_sabrelite_init':
> arch/arm/mach-imx/mach-imx6q.c:120:5: error: 'ksz9021rn_phy_fixup' undeclared (first use in this function)
> arch/arm/mach-imx/mach-imx6q.c:120:5: note: each undeclared identifier is reported only once for each function it appears in
> 
> The bug was originally reported by Artem Bityutskiy but only
> partially fixed in ef441806 "ARM: imx6q: register phy fixup only when
> CONFIG_PHYLIB is enabled".
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Artem Bityutskiy <dedekind1 at gmail.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>

Acked-by: Shawn Guo <shawn.guo at linaro.org>


From shawn.guo at linaro.org  Wed Aug 22 22:13:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 10:13:21 +0800
Subject: [PATCH 5/6] ARM: imx: select CPU_FREQ_TABLE when needed
In-Reply-To: <1345648390-4234-6-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-6-git-send-email-arnd@arndb.de>
Message-ID: <20120823021318.GC24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 05:13:09PM +0200, Arnd Bergmann wrote:
> The i.MX cpufreq implementation uses the CPU_FREQ_TABLE helpers,
> so it needs to select that code to be built. This problem has
> apparently existed since the i.MX cpufreq code was first merged
> in v3.6.37.
> 
s/v3.6.37/v2.6.37?

Otherwise,

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> Building IMX without CPU_FREQ_TABLE results in:
> 
> arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_exit':
> arch/arm/plat-mxc/cpufreq.c:173: undefined reference to `cpufreq_frequency_table_put_attr'
> arch/arm/plat-mxc/built-in.o: In function `mxc_set_target':
> arch/arm/plat-mxc/cpufreq.c:84: undefined reference to `cpufreq_frequency_table_target'
> arch/arm/plat-mxc/built-in.o: In function `mxc_verify_speed':
> arch/arm/plat-mxc/cpufreq.c:65: undefined reference to `cpufreq_frequency_table_verify'
> arch/arm/plat-mxc/built-in.o: In function `mxc_cpufreq_init':
> arch/arm/plat-mxc/cpufreq.c:154: undefined reference to `cpufreq_frequency_table_cpuinfo'
> arch/arm/plat-mxc/cpufreq.c:162: undefined reference to `cpufreq_frequency_table_get_attr'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Yong Shen <yong.shen at linaro.org>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: stable at vger.kernel.org
> ---
>  arch/arm/Kconfig |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..84b5a0c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -2150,6 +2150,7 @@ source "drivers/cpufreq/Kconfig"
>  config CPU_FREQ_IMX
>  	tristate "CPUfreq driver for i.MX CPUs"
>  	depends on ARCH_MXC && CPU_FREQ
> +	select CPU_FREQ_TABLE
>  	help
>  	  This enables the CPUfreq driver for i.MX CPUs.
>  
> -- 
> 1.7.10
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From shawn.guo at linaro.org  Wed Aug 22 22:41:23 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 10:41:23 +0800
Subject: [PATCH 6/6] ARM: imx: select ARM_CPU_SUSPEND when necessary
In-Reply-To: <1345648390-4234-7-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-7-git-send-email-arnd@arndb.de>
Message-ID: <20120823024119.GD24242@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 05:13:10PM +0200, Arnd Bergmann wrote:
> On i.MX6, we select ARM_CPU_SUSPEND when building with power management
> support, but for some reason this was omitted on i.MX5. Normally we
> build kernels for both together so the error only showed up in
> randconfig tests.
> 
> Without this patch, building imx5 standalone results in:
> 
> arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
> arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume'
> 
So far, none of the functions in head-v7.S is used on imx5.  Also
since imx5 SoCs implement State Retention Power Gating in hardware,
ARM_CPU_SUSPEND support will never be used on imx5.

Maybe we should make head-v7.S only compile for imx6?

Regards,
Shawn

> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Eric Miao <eric.miao at linaro.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: stable at vger.kernel.org
> ---
>  arch/arm/mach-imx/Kconfig |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index afd542a..8e96573 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -89,6 +89,7 @@ config SOC_IMX5
>  	select ARCH_MXC_IOMUX_V3
>  	select ARCH_HAS_CPUFREQ
>  	select ARCH_MX5
> +	select ARM_CPU_SUSPEND if PM
>  	bool
>  
>  config SOC_IMX50
> -- 
> 1.7.10
> 


From jason77.wang at gmail.com  Wed Aug 22 22:47:41 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Thu, 23 Aug 2012 10:47:41 +0800
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <503599CD.4060907@gmail.com>

Shawn Guo wrote:
> There is an issue reported on imx6q restart function.  The issue is only
> seen with the image building ARMv7 and ARMv6 together, where cpu_relax()
> is define to do dmb.  It's been root-caused by Russell as below.
>
> Russell King - ARM Linux wrote:
>   
>> I suspect having this dmb inside cpu_relax() is flooding the
>> interconnects with traffic, which then prevents other CPUs getting
>> a look-in (maybe there's no fairness when it comes to dmb's.
>>     
>
> Fix the issue by insert a few NOPs into cpu_relax() where doing dmb.
>   
Tested-by: Hui Wang <jason77.wang at gmail.com>



From Barry.Song at csr.com  Wed Aug 22 22:47:52 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 10:47:52 +0800
Subject: [PATCH 1/3] ARM: PRIMA2: add missing interrupts property for pinctrl
 node
In-Reply-To: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
References: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345690074-31327-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

commit 5130216265f6f924a4 missed the interrupts property

Signed-off-by: Barry Song <Barry.Song at csr.com>
---
 arch/arm/boot/dts/prima2-cb.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
index 34ae3a6..4245306 100644
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -284,6 +284,7 @@
 				#interrupt-cells = <2>;
 				compatible = "sirf,prima2-gpio-pinmux";
 				reg = <0xb0120000 0x10000>;
+				interrupts = <43 44 45 46 47>;
 				gpio-controller;
 				interrupt-controller;
 			};
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Wed Aug 22 22:47:51 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 10:47:51 +0800
Subject: [PATCH 0/3] pinctrl: sirf: add DT binding pinmux mapping support
Message-ID: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>

This series makes us possible to define pinmux mapping support in board
specific .dts files directly.

As we want to add more SoCs(Marco, Polo) in mach-prima2, we want the dir
have no trivial PIN_MAP_MUX_GROUP_DEFAULT and pinctrl_register_mappings
codes.

we will have a clean mach-prima2/common.c file then.

Barry Song (3):
  ARM: PRIMA2: add missing interrupts property for pinctrl node
  ARM: PRIMA2: rename prima2-cb.dts to prima2.dtsi as it only has SoC
    features
  pinctrl: sirf: add DT-binding pinmux mapping support

 arch/arm/boot/dts/prima2-cb.dts    |  424 ------------------------
 arch/arm/boot/dts/prima2-evb.dts   |   37 ++
 arch/arm/boot/dts/prima2.dtsi      |  640 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-prima2/Makefile.boot |    2 +
 drivers/pinctrl/pinctrl-sirf.c     |   58 ++++-
 5 files changed, 736 insertions(+), 425 deletions(-)
 delete mode 100644 arch/arm/boot/dts/prima2-cb.dts
 create mode 100644 arch/arm/boot/dts/prima2-evb.dts
 create mode 100644 arch/arm/boot/dts/prima2.dtsi



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Wed Aug 22 22:47:53 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 10:47:53 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: rename prima2-cb.dts to prima2.dtsi as it
 only has SoC features
In-Reply-To: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
References: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345690074-31327-3-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

The current prima2-cb.dts only includes prima2 SoC feature without board-
specific descriptions. This patches rename it to dtsi and clean some useless
content.

Signed-off-by: Barry Song <Barry.Song at csr.com>
---
 arch/arm/boot/dts/{prima2-cb.dts => prima2.dtsi} |   22 ++++++++++------------
 1 files changed, 10 insertions(+), 12 deletions(-)
 rename arch/arm/boot/dts/{prima2-cb.dts => prima2.dtsi} (96%)

diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2.dtsi
similarity index 96%
rename from arch/arm/boot/dts/prima2-cb.dts
rename to arch/arm/boot/dts/prima2.dtsi
index 4245306..1b716aa 100644
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -1,20 +1,18 @@
-/dts-v1/;
+/*
+ * DTS file for CSR SiRFprimaII SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
 / {
-	model = "SiRF Prima2 eVB";
-	compatible = "sirf,prima2-cb", "sirf,prima2";
+	compatible = "sirf,prima2";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	interrupt-parent = <&intc>;
 
-	memory {
-		reg = <0x00000000 0x20000000>;
-	};
-
-	chosen {
-		bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
-		linux,stdout-path = &uart1;
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Wed Aug 22 22:47:54 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 10:47:54 +0800
Subject: [PATCH 3/3] pinctrl: sirf: add DT-binding pinmux mapping support
In-Reply-To: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
References: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345690074-31327-4-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

This makes us possible to define pinmux mapping in board-specific DTS.
prima2.dtsi provides all possible (groups,functions) configuration, and
device in .dts select configurations from dtsi files.

Signed-off-by: Barry Song <Barry.Song at csr.com>
---
 arch/arm/boot/dts/prima2-evb.dts   |   37 ++++++
 arch/arm/boot/dts/prima2.dtsi      |  221 +++++++++++++++++++++++++++++++++++-
 arch/arm/mach-prima2/Makefile.boot |    2 +
 drivers/pinctrl/pinctrl-sirf.c     |   58 +++++++++-
 4 files changed, 315 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/prima2-evb.dts

diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 0000000..57286b4
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "prima2.dtsi"
+
+/ {
+	model = "CSR SiRFprimaII Evaluation Board";
+	compatible = "sirf,prima2", "sirf,prima2-cb";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	axi {
+		peri-iobg {
+			uart at b0060000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins_a>;
+			};
+			spi at b00d0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi0_pins_a>;
+			};
+			spi at b0170000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi1_pins_a>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 1b716aa..055fca5 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -277,14 +277,231 @@
 				interrupts = <33>;
 			};
 
-			gpio: gpio-controller at b0120000 {
+			gpio: pinctrl at b0120000 {
 				#gpio-cells = <2>;
 				#interrupt-cells = <2>;
-				compatible = "sirf,prima2-gpio-pinmux";
+				compatible = "sirf,prima2-pinctrl";
 				reg = <0xb0120000 0x10000>;
 				interrupts = <43 44 45 46 47>;
 				gpio-controller;
 				interrupt-controller;
+
+				lcd_16pins_a: lcd0 at 0 {
+					lcd {
+						sirf,pins = "lcd_16bitsgrp";
+						sirf,function = "lcd_16bits";
+					};
+				};
+				lcd_18pins_a: lcd0 at 1 {
+					lcd {
+						sirf,pins = "lcd_18bitsgrp";
+						sirf,function = "lcd_18bits";
+					};
+				};
+				lcd_24pins_a: lcd0 at 2 {
+					lcd {
+						sirf,pins = "lcd_24bitsgrp";
+						sirf,function = "lcd_24bits";
+					};
+				};
+				lcdrom_pins_a: lcdrom0 at 0 {
+					lcd {
+						sirf,pins = "lcdromgrp";
+						sirf,function = "lcdrom";
+					};
+				};
+				uart0_pins_a: uart0 at 0 {
+					uart {
+						sirf,pins = "uart0grp";
+						sirf,function = "uart0";
+					};
+				};
+				uart1_pins_a: uart1 at 0 {
+					uart {
+						sirf,pins = "uart1grp";
+						sirf,function = "uart1";
+					};
+				};
+				uart2_pins_a: uart2 at 0 {
+					uart {
+						sirf,pins = "uart2grp";
+						sirf,function = "uart2";
+					};
+				};
+				uart2_noflow_pins_a: uart2 at 1 {
+					uart {
+						sirf,pins = "uart2_nostreamctrlgrp";
+						sirf,function = "uart2_nostreamctrl";
+					};
+				};
+				spi0_pins_a: spi0 at 0 {
+					spi {
+						sirf,pins = "spi0grp";
+						sirf,function = "spi0";
+					};
+				};
+				spi1_pins_a: spi1 at 0 {
+					spi {
+						sirf,pins = "spi1grp";
+						sirf,function = "spi1";
+					};
+				};
+				i2c0_pins_a: i2c0 at 0 {
+					i2c {
+						sirf,pins = "i2c0grp";
+						sirf,function = "i2c0";
+					};
+				};
+				i2c1_pins_a: i2c1 at 0 {
+					i2c {
+						sirf,pins = "i2c1grp";
+						sirf,function = "i2c1";
+					};
+				};
+                                pwm0_pins_a: pwm0 at 0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1 at 0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2 at 0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3 at 0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                gps_pins_a: gps at 0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip at 0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0 at 0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1 at 0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2 at 0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3 at 0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc4_pins_a: sdmmc4 at 0 {
+                                        sdmmc4 {
+                                                sirf,pins = "sdmmc4grp";
+                                                sirf,function = "sdmmc4";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5 at 0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s at 0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                ac97_pins_a: ac97 at 0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand at 0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0 at 0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1 at 0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usp2_pins_a: usp2 at 0 {
+                                        usp2 {
+                                                sirf,pins = "usp2grp";
+                                                sirf,function = "usp2";
+                                        };
+                                };
+                                usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus at 0 {
+                                        usb0_utmi_drvbus {
+                                                sirf,pins = "usb0_utmi_drvbusgrp";
+                                                sirf,function = "usb0_utmi_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus at 0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst at 0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count at 0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst at 0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst at 0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
 			};
 
 			pwm at b0130000 {
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
index c77a488..98167da 100644
--- a/arch/arm/mach-prima2/Makefile.boot
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y		+= 0x00008000
 params_phys-y		:= 0x00000100
 initrd_phys-y		:= 0x00800000
+
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 7fca6ce..304360c 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -17,6 +17,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 	seq_printf(s, " " DRIVER_NAME);
 }
 
+static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np_config,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
+	struct device_node *np;
+	struct property *prop;
+	const char *function, *group;
+	int ret, index = 0, count = 0;
+
+	/* calculate number of maps required */
+	for_each_child_of_node(np_config, np) {
+		ret = of_property_read_string(np, "sirf,function", &function);
+		if (ret < 0)
+			return ret;
+
+		ret = of_property_count_strings(np, "sirf,pins");
+		if (ret < 0)
+			return ret;
+
+		count += ret;
+	}
+
+	if (!count) {
+		dev_err(spmx->dev, "No child nodes passed via DT\n");
+		return -ENODEV;
+	}
+
+	*map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+	if (!*map)
+		return -ENOMEM;
+
+	for_each_child_of_node(np_config, np) {
+		of_property_read_string(np, "sirf,function", &function);
+		of_property_for_each_string(np, "sirf,pins", prop, group) {
+			(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+			(*map)[index].data.mux.group = group;
+			(*map)[index].data.mux.function = function;
+			index++;
+		}
+	}
+
+	*num_maps = count;
+
+	return 0;
+}
+
+static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
+		struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
 	.get_groups_count = sirfsoc_get_groups_count,
 	.get_group_name = sirfsoc_get_group_name,
 	.get_group_pins = sirfsoc_get_group_pins,
 	.pin_dbg_show = sirfsoc_pin_dbg_show,
+	.dt_node_to_map = sirfsoc_dt_node_to_map,
+	.dt_free_map = sirfsoc_dt_free_map,
 };
 
 struct sirfsoc_pmx_func {
@@ -1221,7 +1277,7 @@ out_no_gpio_remap:
 }
 
 static const struct of_device_id pinmux_ids[] __devinitconst = {
-	{ .compatible = "sirf,prima2-gpio-pinmux" },
+	{ .compatible = "sirf,prima2-pinctrl" },
 	{}
 };
 
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From jon-hunter at TI.COM  Wed Aug 22 22:58:44 2012
From: jon-hunter at TI.COM (Jon Hunter)
Date: Wed, 22 Aug 2012 21:58:44 -0500
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
Message-ID: <50359C64.40603@ti.com>

Hi Afzal,

On 08/21/2012 05:45 AM, Afzal Mohammed wrote:
> Presently there are three peripherals that gets it timing
> by runtime calculation. Those peripherals can work with
> frequency scaling that affects gpmc clock. But timing
> calculation for them are in different ways.
> 
> Here a generic runtime calculation method is proposed. Input
> to this function were selected so that they represent timing
> variables that are present in peripheral datasheets. Motive
> behind this was to achieve DT bindings for the inputs as is.
> Even though a few of the tusb6010 timings could not be made
> directly related to timings normally found on peripherals,
> expressions used were translated to those that could be
> justified.
> 
> There are possibilities of improving the calculations, like
> calculating timing for read & write operations in a more
> similar way. Expressions derived here were tested for async
> onenand on omap3evm (as vanilla Kernel does not have omap3evm
> onenand support, local patch was used). Other peripherals,
> tusb6010, smc91x calculations were validated by simulating
> on omap3evm.
> 
> Regarding "we_on" for onenand async, it was found that even
> for muxed address/data, it need not be greater than
> "adv_wr_off", but rather could be derived from write setup
> time for peripheral from start of access time, hence would
> more be in line with peripheral timings. With this method
> it was working fine. If it is required in some cases to
> have "we_on" same as "wr_data_mux_bus" (i.e. greater than
> "adv_wr_off"), another variable could be added to indicate
> it. But such a requirement is not expected though.
> 
> Whole of this exercise is being done to achieve driver and
> DT conversion. If timings could not be calculated in a
> peripheral agnostic way, either gpmc driver would have to
> be peripheral gnostic or a wrapper arrangement over gpmc
> driver would be required.
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
>  arch/arm/mach-omap2/gpmc.c             |  302 ++++++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/gpmc.h |   61 +++++++
>  2 files changed, 363 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index d005b3a..d8e5b08 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -233,6 +233,18 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
>  	return ticks * gpmc_get_fclk_period() / 1000;
>  }
>  
> +unsigned int gpmc_ticks_to_ps(unsigned int ticks)
> +{
> +	return ticks * gpmc_get_fclk_period();
> +}
> +
> +unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
> +{
> +	unsigned long ticks = gpmc_ps_to_ticks(time_ps);
> +
> +	return ticks * gpmc_get_fclk_period();
> +}
> +
>  static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
>  {
>  	u32 l;
> @@ -884,6 +896,296 @@ static void __init gpmc_mem_init(void)
>  	}
>  }
>  
> +static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
> +{
> +	u32 temp;
> +	int div;
> +
> +	div = gpmc_calc_divider(sync_clk);
> +	temp = gpmc_ps_to_ticks(time_ps);
> +	temp = (temp + div - 1) / div;
> +	return gpmc_ticks_to_ps(temp * div);
> +}
> +
> +/* can the cycles be avoided ? */

What is the above comment referring too?

> +static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
> +				struct gpmc_device_timings *dev_t)
> +{
> +	bool mux = dev_t->mux;
> +	u32 temp;
> +
> +	/* adv_rd_off */
> +	temp = dev_t->t_avdp_r;
> +	/* mux check required ? */
> +	if (mux) {
> +		/* t_avdp not to be required for sync, only added for tusb this
> +		 * indirectly necessitates requirement of t_avdp_r & t_avdp_w
> +		 * instead of having a single t_avdp
> +		 */
> +		temp = max_t(u32, temp,	gpmc_t->clk_activation * 1000 +
> +							dev_t->t_avdh);
> +		temp = max_t(u32,
> +			(gpmc_t->adv_on + gpmc_ticks_to_ns(1)) * 1000, temp);
> +	}
> +	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp) / 1000;
> +
> +	/* oe_on */
> +	temp = dev_t->t_oeasu; /* remove this ? */
> +	if (mux) {
> +		temp = max_t(u32, temp,
> +			gpmc_t->clk_activation * 1000 + dev_t->t_ach);
> +		temp = max_t(u32, temp, (gpmc_t->adv_rd_off +
> +				gpmc_ticks_to_ns(dev_t->cyc_aavdh_oe)) * 1000);
> +	}
> +	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp) / 1000;
> +
> +	/* access */
> +	/* any scope for improvement ?, by combining oe_on & clk_activation,
> +	 * need to check whether access = clk_activation + round to sync clk ?
> +	 */
> +	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);
> +	temp += gpmc_t->clk_activation * 1000;
> +	if (dev_t->cyc_oe)
> +		temp = max_t(u32, temp, (gpmc_t->oe_on +
> +				gpmc_ticks_to_ns(dev_t->cyc_oe)) * 1000);
> +	gpmc_t->access = gpmc_round_ps_to_ticks(temp) / 1000;
> +
> +	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ns(1);
> +	gpmc_t->cs_rd_off = gpmc_t->oe_off;
> +
> +	/* rd_cycle */
> +	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
> +	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
> +							gpmc_t->access * 1000;
> +	/* barter t_ce_rdyz with t_cez_r ? */
> +	if (dev_t->t_ce_rdyz)
> +		temp = max_t(u32, temp,
> +				gpmc_t->cs_rd_off * 1000 + dev_t->t_ce_rdyz);
> +	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp) / 1000;
> +
> +	return 0;
> +}

[...]

> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
> index 1cafbfd..e59a932 100644
> --- a/arch/arm/plat-omap/include/plat/gpmc.h
> +++ b/arch/arm/plat-omap/include/plat/gpmc.h
> @@ -152,6 +152,67 @@ struct gpmc_timings {
>  	struct gpmc_bool_timings bool_timings;
>  };
>  
> +/* Device timings in picoseconds */

Why pico seconds and not nanoseconds? I understand you may need to
temporarily convert to pico-secs for rounding, but when providing timing
it seems nano-secs is more suitable.

> +struct gpmc_device_timings {
> +	u32     t_ceasu;	/* address setup to CS valid */
> +	u32     t_avdasu;	/* address setup to ADV valid */
> +	/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
> +	 * of tusb using these timings even for sync whilst
> +	 * ideally for adv_rd/(wr)_off it should have considered
> +	 * t_avdh instead. This indirectly necessitates r/w
> +	 * variations of t_avdp as it is possible to have one
> +	 * sync & other async
> +	 */
> +	u32	t_avdp_r;	/* ADV low time (what about t_cer ?) */
> +	u32	t_avdp_w;
> +	u32	t_aavdh;	/* address hold time */
> +	u32     t_oeasu;	/* address setup to OE valid */
> +	u32     t_aa;		/* access time from ADV assertion */
> +	u32     t_iaa;		/* initial access time */
> +	u32     t_oe;		/* access time from OE assertion */
> +	u32     t_ce;		/* access time from CS asertion */
> +	u32     t_rd_cycle;	/* read cycle time */
> +	u32     t_cez_r;	/* read CS deassertion to high Z */
> +	u32     t_cez_w;	/* write CS deassertion to high Z */
> +	u32     t_oez;		/* OE deassertion to high Z */
> +	u32     t_weasu;	/* address setup to WE valid */
> +	u32     t_wpl;		/* write assertion time */
> +	u32     t_wph;		/* write deassertion time */
> +	u32     t_wr_cycle;	/* write cycle time */
> +
> +	u32	clk;
> +	u32	t_bacc;		/* burst access valid clock to output delay */
> +	u32	t_ces;		/* CS setup time to clk */
> +	u32	t_avds;		/* ADV setup time to clk */
> +	u32	t_avdh;		/* ADV hold time from clk */
> +	u32     t_ach;		/* address hold time from clk */
> +	u32	t_rdyo;		/* clk to ready valid */
> +
> +	u32	t_ce_rdyz;	/* XXX: description ?, or use t_cez instead */
> +	u32	t_ce_avd;	/* CS on to ADV on delay */
> +
> +	/* XXX: check the possibility of combining
> +	 * cyc_aavhd_oe & cyc_aavdh_we
> +	 */
> +	u8	cyc_aavdh_oe;
> +	u8	cyc_aavdh_we;
> +	u8	cyc_oe;
> +	u8	cyc_wpl;
> +	u32     cyc_iaa;
> +
> +	bool	mux;		/* address & data muxed */
> +	bool	sync_write;	/* synchronous write */
> +	bool	sync_read;	/* synchronous read */
> +
> +	bool	ce_xdelay;
> +	bool	avd_xdelay;
> +	bool	oe_xdelay;
> +	bool	we_xdelay;
> +};

I am a little concerned about the above timings structure. For example,
if I am adding support for a new devices it is not clear ...

1. Which are required
2. Which are applicable for async, sync, address-data multiplexed etc.
3. Exactly how these relate to the fields in the gpmc registers.

I understand that this is based upon how timings for onenand and tusb
are being calculated today, but I am not sure that this is the way to go
for all devices. Personally, I would like to see us get away from how
those devices are calculating timings for any new device.

In general, I am concerned that we are abstracting the timings further
from the actual register fields. For example, the timings parameter
"t_ceasu" is described "address setup to CS valid" which is not
incorrect but this value is really just programming the CSONTIME field
and so why not call this cs_on?

So although this may consolidate how the timings are calculated today, I
am concerned it will be confusing to add timings for a new device. At
least if I am calculating timings, I am taking the timing information
for the device and translating that to the how I need to program the
gpmc register fields.

Cheers
Jon


From Barry.Song at csr.com  Wed Aug 22 23:01:17 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 11:01:17 +0800
Subject: [PATCH RESEND 3/3] pinctrl: sirf: add DT-binding pinmux mapping
 support
Message-ID: <1345690877-31621-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

This makes us possible to define pinmux mapping in board-specific DTS.
prima2.dtsi provides all possible (groups,functions) configuration, and
device in .dts select configurations from dtsi files.

Signed-off-by: Barry Song <Barry.Song at csr.com>
---
 .../devicetree/bindings/pinctrl/pinctrl-sirf.txt   |   44 ++++
 arch/arm/boot/dts/prima2-evb.dts                   |   37 ++++
 arch/arm/boot/dts/prima2.dtsi                      |  221 +++++++++++++++++++-
 arch/arm/mach-prima2/Makefile.boot                 |    2 +
 drivers/pinctrl/pinctrl-sirf.c                     |   58 +++++-
 5 files changed, 359 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
 create mode 100644 arch/arm/boot/dts/prima2-evb.dts

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
new file mode 100644
index 0000000..a2896df
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt
@@ -0,0 +1,44 @@
+CSR SiRFprimaII pinmux controller
+
+Required properties:
+- compatible	: "sirf,prima2-pinctrl"
+- reg		: Address range of the pinctrl registers
+- interrupts    : Interrupts used by every GPIO group
+- gpio-controller : Indicates this device is a GPIO controller
+- interrupt-controller  : Marks the device node as an interrupt controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes.
+Each of these subnodes represents some desired configuration for a group of pins.
+
+Required subnode-properties:
+- sirf,pins : An array of strings. Each string contains the name of a group.
+- sirf,function: A string containing the name of the function to mux to the
+  group.
+
+  Valid values for group and function names can be found from looking at the
+  group and function arrays in driver files:
+  drivers/pinctrl/pinctrl-sirf.c
+
+For example, pinctrl might have subnodes like the following:
+ uart2_pins_a: uart2 at 0 {
+         uart {
+                 sirf,pins = "uart2grp";
+                 sirf,function = "uart2";
+         };
+ };
+ uart2_noflow_pins_a: uart2 at 1 {
+         uart {
+                 sirf,pins = "uart2_nostreamctrlgrp";
+                 sirf,function = "uart2_nostreamctrl";
+         };
+ };
+
+For a specific board, if it wants to use uart2 without hardware flow control,
+it can add the following to its board-specific .dts file.
+uart2: uart at 0xb0070000 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_noflow_pins_a>;
+}
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 0000000..57286b4
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "prima2.dtsi"
+
+/ {
+	model = "CSR SiRFprimaII Evaluation Board";
+	compatible = "sirf,prima2", "sirf,prima2-cb";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	axi {
+		peri-iobg {
+			uart at b0060000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins_a>;
+			};
+			spi at b00d0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi0_pins_a>;
+			};
+			spi at b0170000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi1_pins_a>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 1b716aa..39ba5fc 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -277,14 +277,231 @@
 				interrupts = <33>;
 			};
 
-			gpio: gpio-controller at b0120000 {
+			gpio: pinctrl at b0120000 {
 				#gpio-cells = <2>;
 				#interrupt-cells = <2>;
-				compatible = "sirf,prima2-gpio-pinmux";
+				compatible = "sirf,prima2-pinctrl";
 				reg = <0xb0120000 0x10000>;
 				interrupts = <43 44 45 46 47>;
 				gpio-controller;
 				interrupt-controller;
+
+				lcd_16pins_a: lcd0 at 0 {
+					lcd {
+						sirf,pins = "lcd_16bitsgrp";
+						sirf,function = "lcd_16bits";
+					};
+				};
+				lcd_18pins_a: lcd0 at 1 {
+					lcd {
+						sirf,pins = "lcd_18bitsgrp";
+						sirf,function = "lcd_18bits";
+					};
+				};
+				lcd_24pins_a: lcd0 at 2 {
+					lcd {
+						sirf,pins = "lcd_24bitsgrp";
+						sirf,function = "lcd_24bits";
+					};
+				};
+				lcdrom_pins_a: lcdrom0 at 0 {
+					lcd {
+						sirf,pins = "lcdromgrp";
+						sirf,function = "lcdrom";
+					};
+				};
+				uart0_pins_a: uart0 at 0 {
+					uart {
+						sirf,pins = "uart0grp";
+						sirf,function = "uart0";
+					};
+				};
+				uart1_pins_a: uart1 at 0 {
+					uart {
+						sirf,pins = "uart1grp";
+						sirf,function = "uart1";
+					};
+				};
+				uart2_pins_a: uart2 at 0 {
+					uart {
+						sirf,pins = "uart2grp";
+						sirf,function = "uart2";
+					};
+				};
+				uart2_noflow_pins_a: uart2 at 1 {
+					uart {
+						sirf,pins = "uart2_nostreamctrlgrp";
+						sirf,function = "uart2_nostreamctrl";
+					};
+				};
+				spi0_pins_a: spi0 at 0 {
+					spi {
+						sirf,pins = "spi0grp";
+						sirf,function = "spi0";
+					};
+				};
+				spi1_pins_a: spi1 at 0 {
+					spi {
+						sirf,pins = "spi1grp";
+						sirf,function = "spi1";
+					};
+				};
+				i2c0_pins_a: i2c0 at 0 {
+					i2c {
+						sirf,pins = "i2c0grp";
+						sirf,function = "i2c0";
+					};
+				};
+				i2c1_pins_a: i2c1 at 0 {
+					i2c {
+						sirf,pins = "i2c1grp";
+						sirf,function = "i2c1";
+					};
+				};
+				pwm0_pins_a: pwm0 at 0 {
+				        pwm {
+				                sirf,pins = "pwm0grp";
+				                sirf,function = "pwm0";
+				        };
+				};
+				pwm1_pins_a: pwm1 at 0 {
+				        pwm {
+				                sirf,pins = "pwm1grp";
+				                sirf,function = "pwm1";
+				        };
+				};
+				pwm2_pins_a: pwm2 at 0 {
+				        pwm {
+				                sirf,pins = "pwm2grp";
+				                sirf,function = "pwm2";
+				        };
+				};
+				pwm3_pins_a: pwm3 at 0 {
+				        pwm {
+				                sirf,pins = "pwm3grp";
+				                sirf,function = "pwm3";
+				        };
+				};
+				gps_pins_a: gps at 0 {
+				        gps {
+				                sirf,pins = "gpsgrp";
+				                sirf,function = "gps";
+				        };
+				};
+				vip_pins_a: vip at 0 {
+				        vip {
+				                sirf,pins = "vipgrp";
+				                sirf,function = "vip";
+				        };
+				};
+				sdmmc0_pins_a: sdmmc0 at 0 {
+				        sdmmc0 {
+				                sirf,pins = "sdmmc0grp";
+				                sirf,function = "sdmmc0";
+				        };
+				};
+				sdmmc1_pins_a: sdmmc1 at 0 {
+				        sdmmc1 {
+				                sirf,pins = "sdmmc1grp";
+				                sirf,function = "sdmmc1";
+				        };
+				};
+				sdmmc2_pins_a: sdmmc2 at 0 {
+				        sdmmc2 {
+				                sirf,pins = "sdmmc2grp";
+				                sirf,function = "sdmmc2";
+				        };
+				};
+				sdmmc3_pins_a: sdmmc3 at 0 {
+				        sdmmc3 {
+				                sirf,pins = "sdmmc3grp";
+				                sirf,function = "sdmmc3";
+				        };
+				};
+				sdmmc4_pins_a: sdmmc4 at 0 {
+				        sdmmc4 {
+				                sirf,pins = "sdmmc4grp";
+				                sirf,function = "sdmmc4";
+				        };
+				};
+				sdmmc5_pins_a: sdmmc5 at 0 {
+				        sdmmc5 {
+				                sirf,pins = "sdmmc5grp";
+				                sirf,function = "sdmmc5";
+				        };
+				};
+				i2s_pins_a: i2s at 0 {
+				        i2s {
+				                sirf,pins = "i2sgrp";
+				                sirf,function = "i2s";
+				        };
+				};
+				ac97_pins_a: ac97 at 0 {
+				        ac97 {
+				                sirf,pins = "ac97grp";
+				                sirf,function = "ac97";
+				        };
+				};
+				nand_pins_a: nand at 0 {
+				        nand {
+				                sirf,pins = "nandgrp";
+				                sirf,function = "nand";
+				        };
+				};
+				usp0_pins_a: usp0 at 0 {
+				        usp0 {
+				                sirf,pins = "usp0grp";
+				                sirf,function = "usp0";
+				        };
+				};
+				usp1_pins_a: usp1 at 0 {
+				        usp1 {
+				                sirf,pins = "usp1grp";
+				                sirf,function = "usp1";
+				        };
+				};
+				usp2_pins_a: usp2 at 0 {
+				        usp2 {
+				                sirf,pins = "usp2grp";
+				                sirf,function = "usp2";
+				        };
+				};
+				usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus at 0 {
+				        usb0_utmi_drvbus {
+				                sirf,pins = "usb0_utmi_drvbusgrp";
+				                sirf,function = "usb0_utmi_drvbus";
+				        };
+				};
+				usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus at 0 {
+				        usb1_utmi_drvbus {
+				                sirf,pins = "usb1_utmi_drvbusgrp";
+				                sirf,function = "usb1_utmi_drvbus";
+				        };
+				};
+				warm_rst_pins_a: warm_rst at 0 {
+				        warm_rst {
+				                sirf,pins = "warm_rstgrp";
+				                sirf,function = "warm_rst";
+				        };
+				};
+				pulse_count_pins_a: pulse_count at 0 {
+				        pulse_count {
+				                sirf,pins = "pulse_countgrp";
+				                sirf,function = "pulse_count";
+				        };
+				};
+				cko0_rst_pins_a: cko0_rst at 0 {
+				        cko0_rst {
+				                sirf,pins = "cko0_rstgrp";
+				                sirf,function = "cko0_rst";
+				        };
+				};
+				cko1_rst_pins_a: cko1_rst at 0 {
+				        cko1_rst {
+				                sirf,pins = "cko1_rstgrp";
+				                sirf,function = "cko1_rst";
+				        };
+				};
 			};
 
 			pwm at b0130000 {
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
index c77a488..98167da 100644
--- a/arch/arm/mach-prima2/Makefile.boot
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y		+= 0x00008000
 params_phys-y		:= 0x00000100
 initrd_phys-y		:= 0x00800000
+
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 7fca6ce..304360c 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -17,6 +17,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 	seq_printf(s, " " DRIVER_NAME);
 }
 
+static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np_config,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
+	struct device_node *np;
+	struct property *prop;
+	const char *function, *group;
+	int ret, index = 0, count = 0;
+
+	/* calculate number of maps required */
+	for_each_child_of_node(np_config, np) {
+		ret = of_property_read_string(np, "sirf,function", &function);
+		if (ret < 0)
+			return ret;
+
+		ret = of_property_count_strings(np, "sirf,pins");
+		if (ret < 0)
+			return ret;
+
+		count += ret;
+	}
+
+	if (!count) {
+		dev_err(spmx->dev, "No child nodes passed via DT\n");
+		return -ENODEV;
+	}
+
+	*map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+	if (!*map)
+		return -ENOMEM;
+
+	for_each_child_of_node(np_config, np) {
+		of_property_read_string(np, "sirf,function", &function);
+		of_property_for_each_string(np, "sirf,pins", prop, group) {
+			(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+			(*map)[index].data.mux.group = group;
+			(*map)[index].data.mux.function = function;
+			index++;
+		}
+	}
+
+	*num_maps = count;
+
+	return 0;
+}
+
+static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
+		struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
 	.get_groups_count = sirfsoc_get_groups_count,
 	.get_group_name = sirfsoc_get_group_name,
 	.get_group_pins = sirfsoc_get_group_pins,
 	.pin_dbg_show = sirfsoc_pin_dbg_show,
+	.dt_node_to_map = sirfsoc_dt_node_to_map,
+	.dt_free_map = sirfsoc_dt_free_map,
 };
 
 struct sirfsoc_pmx_func {
@@ -1221,7 +1277,7 @@ out_no_gpio_remap:
 }
 
 static const struct of_device_id pinmux_ids[] __devinitconst = {
-	{ .compatible = "sirf,prima2-gpio-pinmux" },
+	{ .compatible = "sirf,prima2-pinctrl" },
 	{}
 };
 
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From 21cnbao at gmail.com  Wed Aug 22 23:04:52 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 23 Aug 2012 11:04:52 +0800
Subject: [PATCH 3/3] pinctrl: sirf: add DT-binding pinmux mapping support
In-Reply-To: <1345690074-31327-4-git-send-email-Barry.Song@csr.com>
References: <1345690074-31327-1-git-send-email-Barry.Song@csr.com>
 <1345690074-31327-4-git-send-email-Barry.Song@csr.com>
Message-ID: <CAGsJ_4ziz=11DQGnnO5pEutrZzq4h3d-WU7UkGEVs2bzgmjq_w@mail.gmail.com>

> From: Barry Song <Baohua.Song at csr.com>
>
> This makes us possible to define pinmux mapping in board-specific DTS.
> prima2.dtsi provides all possible (groups,functions) configuration, and
> device in .dts select configurations from dtsi files.
>
> Signed-off-by: Barry Song <Barry.Song at csr.com>
> ---
>  arch/arm/boot/dts/prima2-evb.dts   |   37 ++++++
>  arch/arm/boot/dts/prima2.dtsi      |  221 +++++++++++++++++++++++++++++++++++-
>  arch/arm/mach-prima2/Makefile.boot |    2 +
>  drivers/pinctrl/pinctrl-sirf.c     |   58 +++++++++-
>  4 files changed, 315 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/boot/dts/prima2-evb.dts

Sorry for missing dt binding document, pls ignore this and take

[PATCH RESEND 3/3] pinctrl: sirf: add DT-binding pinmux mapping support

-barry


From minchan at kernel.org  Wed Aug 22 23:49:35 2012
From: minchan at kernel.org (Minchan Kim)
Date: Thu, 23 Aug 2012 12:49:35 +0900
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <20120822.163648.3800987367886904.hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
 <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
 <20120822.163648.3800987367886904.hdoyu@nvidia.com>
Message-ID: <20120823034935.GC5369@bbox>

On Wed, Aug 22, 2012 at 03:36:48PM +0200, Hiroshi Doyu wrote:
> Hi,
> 
> KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00 +0200:
> 
> > vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic context.
> 
> Right.
> 
> I've been thinking that kzalloc() may be enough here, since
> vzalloc() was introduced to avoid allocation failure for big chunk of
> memory, but I think that it's unlikely that the number of page array
> can be so big. So I propose to drop vzalloc() here, and just simply to
> use kzalloc only as below(*1).
> 
> For example, 
> 
> 1920(H) x 1080(W) x 4(bytes) ~= 8MiB
> 
> For 8 MiB buffer,
>   8(MiB) * 1024 = 8192(KiB)
>   8192(KiB) / 4(KiB/page) = 2048 pages
>   sizeof(struct page *) = 4 bytes
>   2048(pages) * 4(bytes/page) = 8192(bytes) = 8(KiB)
>   8(KiB) / 4(KiB/page) = 2 pages
> 
> If the above estimation is right(I hope;)), the necessary pages are
> _at most_ 2 pages. If the system gets into the situation to fail to
> allocate 2 contiguous pages, that's real the problem. I guess that
> that kind of fragmentation problem would be solved with page migration
> or something, especially nowadays devices are getting larger memories.

In atomic context, VM have no choice except relying on kswapd so
high order allocation can fail easily when memory fragementation
is high.

-- 
Kind regards,
Minchan Kim


From anton.vorontsov at linaro.org  Wed Aug 22 23:48:18 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Wed, 22 Aug 2012 20:48:18 -0700
Subject: [V4 3/4] power_supply: Enable battery-charger for 88pm860x
In-Reply-To: <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
References: <20120714081254.GD20018@lizard>
 <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
Message-ID: <20120823034815.GB16674@lizard>

On Fri, Jul 27, 2012 at 04:27:16PM +0800, Jett.Zhou wrote:
> There are charger and battery measurement feature for 88pm860x PMIC.
> 
> For charger, it can support pre-charge with small current when battery is
> nearly exausted and then changed into fast-charge with CC&CV mode.
> 
> For battery monitor, it can support battery measurement such as
> vbat,vsys,vchg and ibat etc,it can aslo accumulating the Coulomb value
> charged or discharged from battery based on Conlomb Counter, we use it
> to estimate battery capacity.
> 
> Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
> ---

A very nice driver, looks neat!

It slightly touches MFD parts, so Samuel, Mark, can I get your Acks
to pass the driver via battery tree? (For convenience I didn't snip
the MFD parts, they are at the very end of this email.)


Jett,

I also noticed these warnings:

  CHECK   drivers/power/88pm860x_battery.c
drivers/power/88pm860x_battery.c:128:5: warning: symbol 'array_soc' was not declared. Should it be static?
  CHECK   drivers/power/88pm860x_charger.c
drivers/power/88pm860x_charger.c:640:3: warning: symbol 'pm860x_irq_descs' was not declared. Should it be static?
  CHECK   drivers/mfd/88pm860x-core.c
drivers/mfd/88pm860x-core.c:803:53: warning: incorrect type in assignment (different base types)
drivers/mfd/88pm860x-core.c:803:53:    expected struct charger_regulator *charger_regulators
drivers/mfd/88pm860x-core.c:803:53:    got struct regulator_bulk_data static [toplevel] *

They are minor, except for the last one. You seemed to use
'regulator_bulk_data' struct (just as charger manager documentation
wrongly tells you, yup), but in real it should have been
'struct charger_regulator'. The only reason that it worked is
because both 'supply' and 'regulator_name' struct members are the
first in these structs. :-)

So, I had to apply these small fixes on top of you patch, just FYI.

--->8---->8--->8

diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 229cb29..76b5b7d 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -157,8 +157,8 @@ static struct regulator_init_data preg_init_data = {
 	.consumer_supplies	= &preg_supply[0],
 };
 
-static struct regulator_bulk_data chg_desc_regulator_data[] = {
-	{ .supply = "preg", },
+static struct charger_regulator chg_desc_regulator_data[] = {
+	{ .regulator_name = "preg", },
 };
 
 static struct mfd_cell power_devs[] = {
diff --git a/drivers/power/88pm860x_battery.c b/drivers/power/88pm860x_battery.c
index e84e98d..1c19828 100644
--- a/drivers/power/88pm860x_battery.c
+++ b/drivers/power/88pm860x_battery.c
@@ -125,7 +125,7 @@ struct ccnt {
  * State of Charge.
  * The first number is mAh(=3.6C), and the second number is percent point.
  */
-int array_soc[][2] = {
+static int array_soc[][2] = {
 	{4170, 100}, {4154, 99}, {4136, 98}, {4122, 97}, {4107, 96},
 	{4102, 95}, {4088, 94}, {4081, 93}, {4070, 92}, {4060, 91},
 	{4053, 90}, {4044, 89}, {4035, 88}, {4028, 87}, {4019, 86},
diff --git a/drivers/power/88pm860x_charger.c b/drivers/power/88pm860x_charger.c
index 52b59d8..4eeef9b 100644
--- a/drivers/power/88pm860x_charger.c
+++ b/drivers/power/88pm860x_charger.c
@@ -634,7 +634,7 @@ static int pm860x_init_charger(struct pm860x_charger_info *info)
 	return 0;
 }
 
-struct pm860x_irq_desc {
+static struct pm860x_irq_desc {
 	const char *name;
 	irqreturn_t (*handler)(int irq, void *data);
 } pm860x_irq_descs[] = {

--->8---->8--->8


And the MFD parts for which I'd need some Acks:

> diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
> index d09918c..229cb29 100644
> --- a/drivers/mfd/88pm860x-core.c
> +++ b/drivers/mfd/88pm860x-core.c
> @@ -18,6 +18,7 @@
>  #include <linux/mfd/core.h>
>  #include <linux/mfd/88pm860x.h>
>  #include <linux/regulator/machine.h>
> +#include <linux/power/charger-manager.h>
>  
>  #define INT_STATUS_NUM			3
>  
> @@ -84,7 +85,8 @@ static struct resource battery_resources[] __devinitdata = {
>  static struct resource charger_resources[] __devinitdata = {
>  	{PM8607_IRQ_CHG,  PM8607_IRQ_CHG,  "charger detect",  IORESOURCE_IRQ,},
>  	{PM8607_IRQ_CHG_DONE,  PM8607_IRQ_CHG_DONE,  "charging done",       IORESOURCE_IRQ,},
> -	{PM8607_IRQ_CHG_FAULT, PM8607_IRQ_CHG_FAULT, "charging timeout",    IORESOURCE_IRQ,},
> +	{PM8607_IRQ_CHG_FAIL,  PM8607_IRQ_CHG_FAIL,  "charging timeout",    IORESOURCE_IRQ,},
> +	{PM8607_IRQ_CHG_FAULT, PM8607_IRQ_CHG_FAULT, "charging fault",	    IORESOURCE_IRQ,},
>  	{PM8607_IRQ_GPADC1,    PM8607_IRQ_GPADC1,    "battery temperature", IORESOURCE_IRQ,},
>  	{PM8607_IRQ_VBAT, PM8607_IRQ_VBAT, "battery voltage", IORESOURCE_IRQ,},
>  	{PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage",    IORESOURCE_IRQ,},
> @@ -155,10 +157,15 @@ static struct regulator_init_data preg_init_data = {
>  	.consumer_supplies	= &preg_supply[0],
>  };
>  
> +static struct regulator_bulk_data chg_desc_regulator_data[] = {
> +	{ .supply = "preg", },
> +};
> +
>  static struct mfd_cell power_devs[] = {
>  	{"88pm860x-battery", -1,},
>  	{"88pm860x-charger", -1,},
>  	{"88pm860x-preg",    -1,},
> +	{"charger-manager", -1,},
>  };
>  
>  static struct mfd_cell rtc_devs[] = {
> @@ -791,6 +798,19 @@ static void __devinit device_power_init(struct pm860x_chip *chip,
>  			      &preg_resources[0], chip->irq_base);
>  	if (ret < 0)
>  		dev_err(chip->dev, "Failed to add preg subdev\n");
> +
> +	if (pdata->chg_desc) {
> +		pdata->chg_desc->charger_regulators =
> +			&chg_desc_regulator_data[0];
> +		pdata->chg_desc->num_charger_regulators	=
> +			ARRAY_SIZE(chg_desc_regulator_data),
> +		power_devs[3].platform_data = pdata->chg_desc;
> +		power_devs[3].pdata_size = sizeof(*pdata->chg_desc);
> +		ret = mfd_add_devices(chip->dev, 0, &power_devs[3], 1,
> +				      NULL, chip->irq_base);
> +		if (ret < 0)
> +			dev_err(chip->dev, "Failed to add chg-manager subdev\n");
> +	}
>  }
>  
>  static void __devinit device_onkey_init(struct pm860x_chip *chip,

> diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
> index 7b24943..b7c5a3c 100644
> --- a/include/linux/mfd/88pm860x.h
> +++ b/include/linux/mfd/88pm860x.h
> @@ -55,6 +55,21 @@ enum {
>  #define PM8606_DCM_BOOST		(0x00)
>  #define PM8606_PWM			(0x01)
>  
> +#define PM8607_MISC2			(0x42)
> +
> +/* Power Up Log Register */
> +#define PM8607_POWER_UP_LOG		(0x3F)
> +
> +/* Charger Control Registers */
> +#define PM8607_CCNT			(0x47)
> +#define PM8607_CHG_CTRL1		(0x48)
> +#define PM8607_CHG_CTRL2		(0x49)
> +#define PM8607_CHG_CTRL3		(0x4A)
> +#define PM8607_CHG_CTRL4		(0x4B)
> +#define PM8607_CHG_CTRL5		(0x4C)
> +#define PM8607_CHG_CTRL6		(0x4D)
> +#define PM8607_CHG_CTRL7		(0x4E)
> +
>  /* Backlight Registers */
>  #define PM8606_WLED1A			(0x02)
>  #define PM8606_WLED1B			(0x03)
> @@ -205,6 +220,71 @@ enum {
>  #define PM8607_PD_PREBIAS		(0x56)	/* prebias time */
>  #define PM8607_GPADC_MISC1		(0x57)
>  
> +/* bit definitions of  MEAS_EN1*/
> +#define PM8607_MEAS_EN1_VBAT		(1 << 0)
> +#define PM8607_MEAS_EN1_VCHG		(1 << 1)
> +#define PM8607_MEAS_EN1_VSYS		(1 << 2)
> +#define PM8607_MEAS_EN1_TINT		(1 << 3)
> +#define PM8607_MEAS_EN1_RFTMP		(1 << 4)
> +#define PM8607_MEAS_EN1_TBAT		(1 << 5)
> +#define PM8607_MEAS_EN1_GPADC2		(1 << 6)
> +#define PM8607_MEAS_EN1_GPADC3		(1 << 7)
> +
> +/* Battery Monitor Registers */
> +#define PM8607_GP_BIAS2			(0x5A)
> +#define PM8607_VBAT_LOWTH		(0x5B)
> +#define PM8607_VCHG_LOWTH		(0x5C)
> +#define PM8607_VSYS_LOWTH		(0x5D)
> +#define PM8607_TINT_LOWTH		(0x5E)
> +#define PM8607_GPADC0_LOWTH		(0x5F)
> +#define PM8607_GPADC1_LOWTH		(0x60)
> +#define PM8607_GPADC2_LOWTH		(0x61)
> +#define PM8607_GPADC3_LOWTH		(0x62)
> +#define PM8607_VBAT_HIGHTH		(0x63)
> +#define PM8607_VCHG_HIGHTH		(0x64)
> +#define PM8607_VSYS_HIGHTH		(0x65)
> +#define PM8607_TINT_HIGHTH		(0x66)
> +#define PM8607_GPADC0_HIGHTH		(0x67)
> +#define PM8607_GPADC1_HIGHTH		(0x68)
> +#define PM8607_GPADC2_HIGHTH		(0x69)
> +#define PM8607_GPADC3_HIGHTH		(0x6A)
> +#define PM8607_IBAT_MEAS1		(0x6B)
> +#define PM8607_IBAT_MEAS2		(0x6C)
> +#define PM8607_VBAT_MEAS1		(0x6D)
> +#define PM8607_VBAT_MEAS2		(0x6E)
> +#define PM8607_VCHG_MEAS1		(0x6F)
> +#define PM8607_VCHG_MEAS2		(0x70)
> +#define PM8607_VSYS_MEAS1		(0x71)
> +#define PM8607_VSYS_MEAS2		(0x72)
> +#define PM8607_TINT_MEAS1		(0x73)
> +#define PM8607_TINT_MEAS2		(0x74)
> +#define PM8607_GPADC0_MEAS1		(0x75)
> +#define PM8607_GPADC0_MEAS2		(0x76)
> +#define PM8607_GPADC1_MEAS1		(0x77)
> +#define PM8607_GPADC1_MEAS2		(0x78)
> +#define PM8607_GPADC2_MEAS1		(0x79)
> +#define PM8607_GPADC2_MEAS2		(0x7A)
> +#define PM8607_GPADC3_MEAS1		(0x7B)
> +#define PM8607_GPADC3_MEAS2		(0x7C)
> +#define PM8607_CCNT_MEAS1		(0x95)
> +#define PM8607_CCNT_MEAS2		(0x96)
> +#define PM8607_VBAT_AVG			(0x97)
> +#define PM8607_VCHG_AVG			(0x98)
> +#define PM8607_VSYS_AVG			(0x99)
> +#define PM8607_VBAT_MIN			(0x9A)
> +#define PM8607_VCHG_MIN			(0x9B)
> +#define PM8607_VSYS_MIN			(0x9C)
> +#define PM8607_VBAT_MAX			(0x9D)
> +#define PM8607_VCHG_MAX			(0x9E)
> +#define PM8607_VSYS_MAX			(0x9F)
> +
> +#define PM8607_GPADC_MISC2		(0x59)
> +#define PM8607_GPADC0_GP_BIAS_A0	(1 << 0)
> +#define PM8607_GPADC1_GP_BIAS_A1	(1 << 1)
> +#define PM8607_GPADC2_GP_BIAS_A2	(1 << 2)
> +#define PM8607_GPADC3_GP_BIAS_A3	(1 << 3)
> +#define PM8607_GPADC2_GP_BIAS_OUT2	(1 << 6)
> +
>  /* RTC Control Registers */
>  #define PM8607_RTC1			(0xA0)
>  #define PM8607_RTC_COUNTER1		(0xA1)
> @@ -370,7 +450,8 @@ struct pm860x_touch_pdata {
>  };
>  
>  struct pm860x_power_pdata {
> -	unsigned	fast_charge;	/* charge current */
> +	int		max_capacity;
> +	int		resistor;
>  };
>  
>  struct pm860x_platform_data {
> @@ -379,6 +460,7 @@ struct pm860x_platform_data {
>  	struct pm860x_rtc_pdata		*rtc;
>  	struct pm860x_touch_pdata	*touch;
>  	struct pm860x_power_pdata	*power;
> +	struct charger_desc		*chg_desc;
>  	struct regulator_init_data	*regulator;
>  
>  	unsigned short	companion_addr;	/* I2C address of companion chip */
> -- 
> 1.7.0.4


From vinod.koul at linux.intel.com  Wed Aug 22 23:59:40 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Thu, 23 Aug 2012 09:29:40 +0530
Subject: [PATCH v2 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <20120822160417.GA27758@beef>
References: <1345574589-24757-1-git-send-email-mporter@ti.com>
 <1345574589-24757-4-git-send-email-mporter@ti.com>
 <1345607122.1895.44.camel@vkoul-udesk3>  <20120822160417.GA27758@beef>
Message-ID: <1345694380.1895.87.camel@vkoul-udesk3>

On Wed, 2012-08-22 at 12:04 -0400, Matt Porter wrote:
> for querying of these types of limitations. Right now, the
> mmc driver implicitly knows that EDMA needs this restriction
> but it's something that should be queried before calling
> prep_slave().
that's something we need to add; exporting channel capabilities. We only
tell that it slave or memcpy today, but we need to tell clients what are
channel supported parameter ranges.

-- 
~Vinod



From shinya.kuribayashi.px at renesas.com  Wed Aug 22 23:56:59 2012
From: shinya.kuribayashi.px at renesas.com (Shinya Kuribayashi)
Date: Thu, 23 Aug 2012 12:56:59 +0900
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <20120822174945.GS9093@mudshark.cambridge.arm.com>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
 <503513A2.1030002@codeaurora.org>
 <20120822174945.GS9093@mudshark.cambridge.arm.com>
Message-ID: <5035AA0B.7090003@renesas.com>

On 8/23/2012 2:49 AM, Will Deacon wrote:
> On Wed, Aug 22, 2012 at 06:15:14PM +0100, Stephen Boyd wrote:
>> On 08/22/12 07:29, Arnd Bergmann wrote:
>>> read_current_timer is used in the get_cycles() function when
>>> ARM_ARCH_TIMER is set, and that function can be inlined into
>>> driver modules, so we should export the function to avoid
>>> errors like
>>>
>>> ERROR: "read_current_timer" [drivers/video/udlfb.ko] undefined!
>>> ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined!
>>>
>>> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>>> Cc: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>
>>
>> Acked-by: Stephen Boyd <sboyd at codeaurora.org>
>>
>> I ran into this last week but forgot to send the patch. Thanks.
> 
> Looks good to me, thanks Arnd:
> 
> Acked-by: Will Deacon <will.deacon at arm.com>

I haven't hit with this so far with our configs though, but why not?

Acked-by: Shinya Kuribayashi <shinya.kuribayashi.px at renesas.com>


From shinya.kuribayashi.px at renesas.com  Thu Aug 23 00:23:56 2012
From: shinya.kuribayashi.px at renesas.com (Shinya Kuribayashi)
Date: Thu, 23 Aug 2012 13:23:56 +0900
Subject: [PATCH 1/4] ARM: export read_current_timer
In-Reply-To: <20120822175810.GT9093@mudshark.cambridge.arm.com>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <1345645780-2749-2-git-send-email-arnd@arndb.de>
 <503513A2.1030002@codeaurora.org>
 <20120822174945.GS9093@mudshark.cambridge.arm.com>
 <50351D80.6010600@codeaurora.org>
 <20120822175810.GT9093@mudshark.cambridge.arm.com>
Message-ID: <5035B05C.4020104@renesas.com>

On 8/23/2012 2:58 AM, Will Deacon wrote:
> On Wed, Aug 22, 2012 at 06:57:20PM +0100, Stephen Boyd wrote:
>> On 08/22/12 10:49, Will Deacon wrote:
>>> On the topic of the timer stuff: Shinya/Stephen, did you have a chance to
>>> look at the registration stuff that was proposed? I'm happy to push it if
>>> people will actually use it.
>>
>> Yes I have tested it on our internal trees and it looks good. I plan to
>> send a patch to move MSM's timers over to it later this week so that we
>> have at least two users upstream.

And I think other A9 MPcore platforms, namely OMAP and EXYNOS, would
also be candidates, who tried to skip calibrate_delay() in the past
(OMAP) or currently provide non-smp_twd timers as localtimers (EXYNOS).
I may miss the latest status of those BSPs, but believe that we would
have more users (>2) in the future.

> Awesome, I'll dust that series off at -rc3 then.

It works for me for weeks without troubles, looking forward to it.
--
Shinya Kuribayashi
Renesas Electronics


From anton.vorontsov at linaro.org  Thu Aug 23 00:43:48 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Wed, 22 Aug 2012 21:43:48 -0700
Subject: [V4 3/4] power_supply: Enable battery-charger for 88pm860x
In-Reply-To: <20120823034815.GB16674@lizard>
References: <20120714081254.GD20018@lizard>
 <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
 <20120823034815.GB16674@lizard>
Message-ID: <20120823044348.GA415@lizard>

On Wed, Aug 22, 2012 at 08:48:15PM -0700, Anton Vorontsov wrote:
[....]
> drivers/mfd/88pm860x-core.c:803:53: warning: incorrect type in assignment (different base types)
> drivers/mfd/88pm860x-core.c:803:53:    expected struct charger_regulator *charger_regulators
> drivers/mfd/88pm860x-core.c:803:53:    got struct regulator_bulk_data static [toplevel] *
> 
> They are minor, except for the last one. You seemed to use
> 'regulator_bulk_data' struct (just as charger manager documentation
> wrongly tells you, yup), but in real it should have been
> 'struct charger_regulator'. The only reason that it worked is
> because both 'supply' and 'regulator_name' struct members are the
> first in these structs. :-)

Oh, actually, I see that this is a result of extcon rework, so not
your fault at all.

Anton.


From gururaja.hebbar at ti.com  Thu Aug 23 01:13:59 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Thu, 23 Aug 2012 05:13:59 +0000
Subject: [PATCH 3/5] ASoC: Davinci: pcm: Add device tree bindings
In-Reply-To: <20120822155808.GP7995@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-4-git-send-email-gururaja.hebbar@ti.com>
 <20120817223122.GA21445@opensource.wolfsonmicro.com>
 <1BAFE6F6C881BF42822005164F1491C33EA67DA1@DBDE01.ent.ti.com>
 <20120822155808.GP7995@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA68662@DBDE01.ent.ti.com>

On Wed, Aug 22, 2012 at 21:28:08, Mark Brown wrote:
> On Wed, Aug 22, 2012 at 01:50:09PM +0000, Hebbar, Gururaja wrote:
> 
> > From your for-3.7 branch, I could only find such implementation in Tegra
> > Platform. 
> > Most Freescale platforms implements this through a device/driver method.
> > Exception being sound/soc/mxs/mxs-pcm.c
> 
> > So should I follow tegra implementation?
> 
> Tegra and mxs should be good examples, yes.

Ok. Will update in V2

> 


Regards, 
Gururaja


From swarren at wwwdotorg.org  Thu Aug 23 01:16:33 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 23:16:33 -0600
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <20120822105729.GB10057@shlinux2.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822082940.GJ4011@b20223-02.ap.freescale.net>
 <20120822105729.GB10057@shlinux2.ap.freescale.net>
Message-ID: <5035BCB1.8000801@wwwdotorg.org>

On 08/22/2012 04:57 AM, Dong Aisheng wrote:
> On Wed, Aug 22, 2012 at 04:29:41PM +0800, Zhao Richard-B20223 wrote:
>> On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
>>> Add regmap based imx syscon driver.
>>> This is usually used for access misc bits in registers which does not belong
>>> to a specific module, for example, IOMUXC GPR and ANATOP.
>>> With this driver, we provide a standard API for client driver to call to
>>> access registers which are registered into syscon.

>>> +static int imx_syscon_match(struct device *dev, void *data)
>>> +{
>>> +	struct imx_syscon *syscon = dev_get_drvdata(dev);
>>> +	struct device_node *dn = data;
>>> +
>>> +	return (syscon->dev->of_node == dn) ? 1 : 0;
>>> +}
>>> +
>>> +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
>>
>> For API function, is it better to use struct device rather not np?
>>  - it won't need to search dev in below code every time it access
>>    registers.
>
> The purpose is not require client driver to know the implementation details
> of imx_syscon_{read/write} API, it's more easy to use since client only
> needs pass the device node to which it wants to read/write.
> 
> For search dev, it doesn't look like a big issue since it only search devices
> attached on the driver which is very quick.
> And hide it in common API does not require every client driver to write
> duplicated codes.

You could still implement a function:

struct device *imx_syscon_lookup(struct device_node *np)

... and require all clients to call that, and pass the dev to the other
functions. That'd still keep all the lookup code in one place, but
prevent it having to run every time, no matter how small it is.

I think such an API is required anyway, since client drivers need some
way to determine whether the imx_syscon driver is available yet, and if
not defer their probe until it is.

So, clients would do:

foo->syscon_dev = imx_syscon_lookup(np);
if (!foo->syscon_dev)
    return -EPROBE_DEFER;

rather than:

foo->syscon_np = np;

Not too much overhead/boiler-plate in each client driver.


From swarren at wwwdotorg.org  Thu Aug 23 01:21:03 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 22 Aug 2012 23:21:03 -0600
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use imx-syscon
 to access anatop register
In-Reply-To: <1345619928-15446-5-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
Message-ID: <5035BDBF.9020602@wwwdotorg.org>

On 08/22/2012 01:18 AM, Dong Aisheng wrote:
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>

> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c

> @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
>  	rdesc->ops = &anatop_rops;
>  	rdesc->type = REGULATOR_VOLTAGE;
>  	rdesc->owner = THIS_MODULE;
> -	sreg->mfd = anatopmfd;
> +
> +	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
> +	if (!sreg->anatop)
> +		return -ENODEV;

In fact, that imx_syscon_lookup function I proposed could even do the
of_parse_phandle() internally, so perhaps:

foo->syscon_dev = imx_syscon_lookup(np, "fsl,anatop", 0);
if (IS_ERR(foo->syscon_dev))
    return PTR_ERR(foo->syscon_dev);

with imx_syscon_lookup() internally knowing when to return EPROBE_DEFER
rather than any other permanent error code (e.g. for missing property,
bad phandle, etc.)


From kgene.kim at samsung.com  Thu Aug 23 01:40:45 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 Aug 2012 14:40:45 +0900
Subject: [PATCH] spi/s3c64xx: Drop extra calls to spi_master_get in
 suspend/remove functions
In-Reply-To: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
References: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
Message-ID: <1d0b01cd80f1$d77eaf90$867c0eb0$%kim@samsung.com>

Guenter Roeck wrote:
> 
> Suspend and resume functions call spi_master_get() without matching
> spi_master_put(). The extra references are unnecessary and cause
> subsequent
> module unload attempts to fail. Drop the calls.
> 
> Signed-off-by: Guenter Roeck <linux at roeck-us.net>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

(Cc'ed Mark Brown who is handling spi now)

Guenter, maybe you need to re-send this patch to Mark so that he can apply
;-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> ---
>  drivers/spi/spi-s3c64xx.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 646a765..d7a87df 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1409,7 +1409,7 @@ static int s3c64xx_spi_remove(struct platform_device
> *pdev)
>  #ifdef CONFIG_PM
>  static int s3c64xx_spi_suspend(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd =
> spi_master_get_devdata(master);
> 
>  	spi_master_suspend(master);
> @@ -1428,7 +1428,7 @@ static int s3c64xx_spi_suspend(struct device *dev)
> 
>  static int s3c64xx_spi_resume(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd =
> spi_master_get_devdata(master);
>  	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> 
> @@ -1452,7 +1452,7 @@ static int s3c64xx_spi_resume(struct device *dev)
>  #ifdef CONFIG_PM_RUNTIME
>  static int s3c64xx_spi_runtime_suspend(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd =
> spi_master_get_devdata(master);
> 
>  	clk_disable(sdd->clk);
> @@ -1463,7 +1463,7 @@ static int s3c64xx_spi_runtime_suspend(struct device
> *dev)
> 
>  static int s3c64xx_spi_runtime_resume(struct device *dev)
>  {
> -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> +	struct spi_master *master = dev_get_drvdata(dev);
>  	struct s3c64xx_spi_driver_data *sdd =
> spi_master_get_devdata(master);
> 
>  	clk_enable(sdd->src_clk);
> --
> 1.7.9.7



From Barry.Song at csr.com  Thu Aug 23 01:41:58 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 13:41:58 +0800
Subject: [PATCH v2 2/3] ARM: PRIMA2: adjust Kconfig to support select SoC
 features
In-Reply-To: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
References: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345700519-667-3-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Now we have primaII, but will include Marco and Polo in mach-prima2
as well. We add Kconfig menu so that we can select necessary SoC
features.

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2:
 fix typo;
 don't rename mach-prima2 to mach-sirf;
 make ARCH_PRIMA2 become an enable feature but not a choice of SoC types;

 arch/arm/Kconfig                  |   10 +++++-----
 arch/arm/configs/prima2_defconfig |    7 +++----
 arch/arm/mach-prima2/Kconfig      |   15 +++++++++++++++
 3 files changed, 23 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/mach-prima2/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fb60148..2c1ca9f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -407,9 +407,8 @@ config ARCH_GEMINI
 	help
 	  Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_PRIMA2
-	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-	select CPU_V7
+config ARCH_SIRF
+	bool "CSR SiRF"
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
@@ -419,9 +418,8 @@ config ARCH_PRIMA2
 	select PINCTRL
 	select PINCTRL_SIRF
 	select USE_OF
-	select ZONE_DMA
 	help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
+	  Support for CSR SiRFprimaII/Marco/Polo platforms
 
 config ARCH_EBSA110
 	bool "EBSA-110"
@@ -1118,6 +1116,8 @@ source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
+source "arch/arm/mach-prima2/Kconfig"
+
 source "arch/arm/mach-tegra/Kconfig"
 
 source "arch/arm/mach-u300/Kconfig"
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index c328ac6..807d4e2 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -1,4 +1,6 @@
 CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
@@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_SIRF=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
@@ -36,7 +36,6 @@ CONFIG_SPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_MASS_STORAGE=m
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
new file mode 100644
index 0000000..65438e1
--- /dev/null
+++ b/arch/arm/mach-prima2/Kconfig
@@ -0,0 +1,15 @@
+if ARCH_SIRF
+
+menu "CSR SiRF primaII/Marco/Polo Specific Features"
+
+config ARCH_PRIMA2
+	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+	default y
+	select CPU_V7
+	select ZONE_DMA
+	help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+endmenu
+
+endif
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Thu Aug 23 01:41:56 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 13:41:56 +0800
Subject: [PATCH v2 0/3] ARM: PRIMA2: some patches prepared to support new SiRF
 SoCs
Message-ID: <1345700519-667-1-git-send-email-Barry.Song@csr.com>

we will support SiRFmarco and SiRFpolo SMP SoCs, this series is making
mach-prima2 common for all of them.

Barry Song (3):
  ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
  ARM: PRIMA2: adjust Kconfig to support select SoC features
  ARM: SIRF: make sirf irqchip driver optional since new SoCs will have
    GIC

 arch/arm/Kconfig                            |   10 +++++-----
 arch/arm/configs/prima2_defconfig           |    7 +++----
 arch/arm/mach-prima2/Kconfig                |   19 +++++++++++++++++++
 arch/arm/mach-prima2/Makefile               |    4 ++--
 arch/arm/mach-prima2/{prima2.c => common.c} |   11 ++++++-----
 arch/arm/mach-prima2/irq.c                  |    2 +-
 6 files changed, 36 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/mach-prima2/Kconfig
 rename arch/arm/mach-prima2/{prima2.c => common.c} (81%)



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Thu Aug 23 01:41:57 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 13:41:57 +0800
Subject: [PATCH v2 1/3] ARM: PRIMA2: use DT_MACHINE_START and convert to
 generic board
In-Reply-To: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
References: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345700519-667-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

we will have SiRFMarco and SiRFPolo, all of them will be in the
generic board.

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2: rename prima2.c to common.c instead of board-generic.c
 delete redundant atag_offset

 arch/arm/mach-prima2/Makefile               |    2 +-
 arch/arm/mach-prima2/{prima2.c => common.c} |   11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)
 rename arch/arm/mach-prima2/{prima2.c => common.c} (81%)

diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 841847d..f2cde60 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,7 +1,7 @@
 obj-y := timer.o
 obj-y += irq.o
 obj-y += rstc.o
-obj-y += prima2.o
+obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c
similarity index 81%
rename from arch/arm/mach-prima2/prima2.c
rename to arch/arm/mach-prima2/common.c
index e9a17ae..f25a541 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/common.c
@@ -30,20 +30,21 @@ void __init sirfsoc_init_late(void)
 	sirfsoc_pm_init();
 }
 
-static const char *prima2cb_dt_match[] __initdata = {
-       "sirf,prima2-cb",
+#ifdef CONFIG_ARCH_PRIMA2
+static const char *prima2_dt_match[] __initdata = {
+       "sirf,prima2",
        NULL
 };
 
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
-	.atag_offset	= 0x100,
 	.map_io         = sirfsoc_map_lluart,
 	.init_irq	= sirfsoc_of_irq_init,
 	.timer		= &sirfsoc_timer,
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
-	.dt_compat      = prima2cb_dt_match,
+	.dt_compat      = prima2_dt_match,
 	.restart	= sirfsoc_restart,
 MACHINE_END
+#endif
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Thu Aug 23 01:41:59 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 13:41:59 +0800
Subject: [PATCH v2 3/3] ARM: SIRF: make sirf irqchip driver optional since new
 SoCs will have GIC
In-Reply-To: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
References: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1345700519-667-4-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

New MARCO and POLO SoC use GIC, so make irq.c optional and enable it
only if we enable ARCH_PRIMA2 in Kconfig

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2: if dt node is not found, return but not panic since we might enable
 ARCH_PRIMA2 even we work on ARCH_MARCO

 arch/arm/mach-prima2/Kconfig  |    4 ++++
 arch/arm/mach-prima2/Makefile |    2 +-
 arch/arm/mach-prima2/irq.c    |    2 +-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 65438e1..41fc853 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -7,9 +7,13 @@ config ARCH_PRIMA2
 	default y
 	select CPU_V7
 	select ZONE_DMA
+	select SIRF_IRQ
 	help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
 endmenu
 
+config SIRF_IRQ
+	bool
+
 endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index f2cde60..fc9ce22 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,8 +1,8 @@
 obj-y := timer.o
-obj-y += irq.o
 obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index a7b9415..7dee917 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void)
 
 	np = of_find_matching_node(NULL, intc_ids);
 	if (!np)
-		panic("unable to find compatible intc node in dtb\n");
+		return;
 
 	sirfsoc_intc_base = of_iomap(np, 0);
 	if (!sirfsoc_intc_base)
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From kgene.kim at samsung.com  Thu Aug 23 01:45:54 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 Aug 2012 14:45:54 +0900
Subject: [PATCH 4/9] ARM: pmu: remove arm_pmu_type enumeration
In-Reply-To: <1344620195-22372-5-git-send-email-will.deacon@arm.com>
References: <1344620195-22372-1-git-send-email-will.deacon@arm.com>
 <1344620195-22372-5-git-send-email-will.deacon@arm.com>
Message-ID: <1d0c01cd80f2$8f974970$aec5dc50$%kim@samsung.com>

Will Deacon wrote:
> 
> From: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
> 
> The arm_pmu_type enumeration was initially introduced to identify
> different PMU types in the system, the usual one being that on the CPU
> (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and
> the introduction of devicetree bindings for the CPU PMU, the enumeration
> is no longer required.
> 
> This patch removes the enumeration and updates the various CPU PMU
> platform devices so that they no longer pass an .id field referring
> to identify the PMU type.
> 
> Cc: JD Zheng <jdzheng at broadcom.com>
> Cc: Jon Hunter <jon-hunter at ti.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> Cc: Pawel Moll <pawel.moll at arm.com>
> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha at arm.com>
> [will: cosmetic edits and actual removal of the enum type]
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/include/asm/pmu.h               |   10 ----------
>  arch/arm/mach-bcmring/arch.c             |    3 +--
>  arch/arm/mach-omap2/devices.c            |    3 +--
>  arch/arm/mach-pxa/devices.c              |    3 +--
>  arch/arm/mach-realview/realview_eb.c     |    3 +--
>  arch/arm/mach-realview/realview_pb1176.c |    3 +--
>  arch/arm/mach-realview/realview_pb11mp.c |    3 +--
>  arch/arm/mach-realview/realview_pba8.c   |    3 +--
>  arch/arm/mach-realview/realview_pbx.c    |    3 +--
>  arch/arm/mach-tegra/devices.c            |    3 +--
>  arch/arm/mach-ux500/cpu-db8500.c         |    3 +--
>  arch/arm/mach-vexpress/ct-ca9x4.c        |    3 +--
>  arch/arm/plat-iop/pmu.c                  |    3 +--
>  arch/arm/plat-samsung/devs.c             |    3 +--
>  14 files changed, 13 insertions(+), 36 deletions(-)



From m.szyprowski at samsung.com  Thu Aug 23 01:58:34 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 23 Aug 2012 07:58:34 +0200
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <20120822.163648.3800987367886904.hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
 <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
 <20120822.163648.3800987367886904.hdoyu@nvidia.com>
Message-ID: <012401cd80f4$59727020$0c575060$%szyprowski@samsung.com>

Hello,

On Wednesday, August 22, 2012 3:37 PM Hiroshi Doyu wrote:

> KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00 +0200:
> 
> > vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic context.
> 
> Right.
> 
> I've been thinking that kzalloc() may be enough here, since
> vzalloc() was introduced to avoid allocation failure for big chunk of
> memory, but I think that it's unlikely that the number of page array
> can be so big. So I propose to drop vzalloc() here, and just simply to
> use kzalloc only as below(*1).

We already had a discussion about this, so I don't think it makes much sense to
change it back to kzalloc. This vmalloc() call won't hurt anyone. It should not
be considered a problem for atomic allocations, because no sane driver will try
to allocate buffers larger than a dozen KiB with GFP_ATOMIC flag. I would call
such try a serious bug, which we should not care here.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From trini at ti.com  Thu Aug 23 02:01:23 2012
From: trini at ti.com (Tom Rini)
Date: Wed, 22 Aug 2012 23:01:23 -0700
Subject: [PATCH v3 0/3] DaVinci DMA engine conversion
In-Reply-To: <1345684176-21472-1-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
Message-ID: <20120823060123.GA12312@bill-the-cat>

On Wed, Aug 22, 2012 at 09:09:33PM -0400, Matt Porter wrote:

[snip]
> Matt Porter (3):
>   dmaengine: add TI EDMA DMA engine driver
>   mmc: davinci_mmc: convert to DMA engine API
>   spi: spi-davinci: convert to DMA engine API
> 
>  drivers/dma/Kconfig            |   10 +
>  drivers/dma/Makefile           |    1 +
>  drivers/dma/edma.c             |  671 ++++++++++++++++++++++++++++++++++++++++
>  drivers/mmc/host/davinci_mmc.c |  271 +++++-----------
>  drivers/spi/spi-davinci.c      |  292 ++++++++---------
>  include/linux/edma.h           |   29 ++
>  6 files changed, 923 insertions(+), 351 deletions(-)
>  create mode 100644 drivers/dma/edma.c
>  create mode 100644 include/linux/edma.h

On the Logic PD AM1808 EVM:
mmc0 rootfs: http://pastebin.com/HKVdmA0G
jffs2 on the SPI flash rootfs: http://pastebin.com/cpAHgdug

Tested-by: Tom Rini <trini at ti.com>

-- 
Tom
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From richard.zhao at freescale.com  Thu Aug 23 02:09:38 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Thu, 23 Aug 2012 14:09:38 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <5035BCB1.8000801@wwwdotorg.org>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822082940.GJ4011@b20223-02.ap.freescale.net>
 <20120822105729.GB10057@shlinux2.ap.freescale.net>
 <5035BCB1.8000801@wwwdotorg.org>
Message-ID: <20120823060937.GL4011@b20223-02.ap.freescale.net>

On Wed, Aug 22, 2012 at 11:16:33PM -0600, Stephen Warren wrote:
> On 08/22/2012 04:57 AM, Dong Aisheng wrote:
> > On Wed, Aug 22, 2012 at 04:29:41PM +0800, Zhao Richard-B20223 wrote:
> >> On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> >>> Add regmap based imx syscon driver.
> >>> This is usually used for access misc bits in registers which does not belong
> >>> to a specific module, for example, IOMUXC GPR and ANATOP.
> >>> With this driver, we provide a standard API for client driver to call to
> >>> access registers which are registered into syscon.
> 
> >>> +static int imx_syscon_match(struct device *dev, void *data)
> >>> +{
> >>> +	struct imx_syscon *syscon = dev_get_drvdata(dev);
> >>> +	struct device_node *dn = data;
> >>> +
> >>> +	return (syscon->dev->of_node == dn) ? 1 : 0;
> >>> +}
> >>> +
> >>> +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
> >>
> >> For API function, is it better to use struct device rather not np?
> >>  - it won't need to search dev in below code every time it access
> >>    registers.
> >
> > The purpose is not require client driver to know the implementation details
> > of imx_syscon_{read/write} API, it's more easy to use since client only
> > needs pass the device node to which it wants to read/write.
> > 
> > For search dev, it doesn't look like a big issue since it only search devices
> > attached on the driver which is very quick.
> > And hide it in common API does not require every client driver to write
> > duplicated codes.
> 
> You could still implement a function:
> 
> struct device *imx_syscon_lookup(struct device_node *np)
> 
> ... and require all clients to call that, and pass the dev to the other
> functions. That'd still keep all the lookup code in one place, but
> prevent it having to run every time, no matter how small it is.
> 
> I think such an API is required anyway, since client drivers need some
> way to determine whether the imx_syscon driver is available yet, and if
> not defer their probe until it is.
> 
> So, clients would do:
> 
> foo->syscon_dev = imx_syscon_lookup(np);
> if (!foo->syscon_dev)
>     return -EPROBE_DEFER;
> 
> rather than:
> 
> foo->syscon_np = np;
> 
> Not too much overhead/boiler-plate in each client driver.
I think it's good idea.

Thanks
Richard



From hdoyu at nvidia.com  Thu Aug 23 02:10:25 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:10:25 +0300
Subject: [v2 0/4] ARM: dma-mapping: IOMMU atomic allocation
Message-ID: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>

Hi,

The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
region" breaks the compatibility with existing drivers. This causes
the following kernel oops(*1). That driver has called dma_pool_alloc()
to allocate memory from the interrupt context, and it hits
BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
fixes this problem with making use of the pre-allocate atomic memory
pool which DMA is using in the same way as DMA does now.

Any comment would be really appreciated.

v2:
Don't modify attrs(DMA_ATTR_NO_KERNEL_MAPPING) for atomic allocation. (Marek)
Skip vzalloc (KyongHo, Minchan)
v1:
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002398.html

*1:
[    8.321343] ------------[ cut here ]------------
[    8.325971] kernel BUG at kernel/mm/vmalloc.c:1322!
[    8.333615] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[    8.339436] Modules linked in:
[    8.342496] CPU: 0    Tainted: G        W     (3.4.6-00067-g5d485f7 #67)
[    8.349192] PC is at __get_vm_area_node.isra.29+0x164/0x16c
[    8.354758] LR is at get_vm_area_caller+0x4c/0x54
[    8.359454] pc : [<c011297c>]    lr : [<c011318c>]    psr: 20000193
[    8.359458] sp : c09edca0  ip : c09ec000  fp : ae278000
[    8.370922] r10: f0000000  r9 : c011aa54  r8 : c0a26cb8
[    8.376136] r7 : 00000001  r6 : 000000d0  r5 : 20000008  r4 : c09edca0
[    8.382651] r3 : 00010000  r2 : 20000008  r1 : 00000001  r0 : 00001000
[    8.389166] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    8.396549] Control: 10c5387d  Table: ad98c04a  DAC: 00000015
....
[    9.169162] dfa0: 412fc099 c09ec000 00000000 c000fdd8 c06df1e4 c0a1b080 00000000 00000000
[    9.177329] dfc0: c0a235cc 8000406a 00000000 c0986818 ffffffff ffffffff c0986404 00000000
[    9.185497] dfe0: 00000000 c09bb070 10c5387d c0a19c58 c09bb064 80008044 00000000 00000000
[    9.193673] [<c011297c>] (__get_vm_area_node.isra.29+0x164/0x16c) from [<c011318c>] (get_vm_area_caller+0x4c/0x54)
[    9.204022] [<c011318c>] (get_vm_area_caller+0x4c/0x54) from [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc)
[    9.214276] [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc) from [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8)
[    9.224795] [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8) from [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8)
[    9.235309] [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8) from [<c011ab60>] (dma_pool_alloc+0x80/0x170)
[    9.245304] [<c011ab60>] (dma_pool_alloc+0x80/0x170) from [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c)
[    9.254344] [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c) from [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8)
[    9.263467] [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8) from [<c03cc140>] (tegra_ep_queue+0x154/0x33c)
[    9.272592] [<c03cc140>] (tegra_ep_queue+0x154/0x33c) from [<c03dd5b4>] (composite_setup+0x364/0x6d4)
[    9.281804] [<c03dd5b4>] (composite_setup+0x364/0x6d4) from [<c03dd9dc>] (android_setup+0xb8/0x14c)
[    9.290843] [<c03dd9dc>] (android_setup+0xb8/0x14c) from [<c03cd144>] (setup_received_irq+0xbc/0x270)
[    9.300053] [<c03cd144>] (setup_received_irq+0xbc/0x270) from [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4)
[    9.309353] [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4) from [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0)
[    9.319087] [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0) from [<c00b59b4>] (handle_irq_event+0x44/0x64)
[    9.328907] [<c00b59b4>] (handle_irq_event+0x44/0x64) from [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c)
[    9.338294] [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c) from [<c00b4f14>] (generic_handle_irq+0x34/0x48)
[    9.347858] [<c00b4f14>] (generic_handle_irq+0x34/0x48) from [<c000f6f4>] (handle_IRQ+0x54/0xb4)
[    9.356637] [<c000f6f4>] (handle_IRQ+0x54/0xb4) from [<c00084b0>] (gic_handle_irq+0x2c/0x60)
[    9.365068] [<c00084b0>] (gic_handle_irq+0x2c/0x60) from [<c000e900>] (__irq_svc+0x40/0x70)
[    9.373405] Exception stack(0xc09edf10 to 0xc09edf58)
[    9.378447] df00:                                     00000000 000f4240 00000003 00000000
[    9.386615] df20: 00000000 e55bbc00 ef66f3ca 00000001 00000000 412fc099 c0abb9c8 00000000
[    9.394781] df40: 3b9ac9ff c09edf58 c027a9bc c0042880 20000113 ffffffff
[    9.401396] [<c000e900>] (__irq_svc+0x40/0x70) from [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78)
[    9.410272] [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78) from [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4)
[    9.419922] [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4) from [<c000fdd8>] (cpu_idle+0xd8/0x134)
[    9.428612] [<c000fdd8>] (cpu_idle+0xd8/0x134) from [<c0986818>] (start_kernel+0x27c/0x2cc)
[    9.436952] Code: e1a00004 e3a04000 eb002265 eaffffe0 (e7f001f2)
[    9.443038] ---[ end trace 1b75b31a2719ed24 ]---
[    9.447645] Kernel panic - not syncing: Fatal exception in interrupt

Hiroshi Doyu (4):
  ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
  ARM: dma-mapping: Use kzalloc() with GFP_ATOMIC
  ARM: dma-mapping: Refactor out to introduce __alloc_fill_pages
  ARM: dma-mapping: IOMMU allocates pages from atomic_pool with
    GFP_ATOMIC

 arch/arm/mm/dma-mapping.c |  102 ++++++++++++++++++++++++++++++++++-----------
 1 files changed, 77 insertions(+), 25 deletions(-)

-- 
1.7.5.4



From Barry.Song at csr.com  Thu Aug 23 02:09:52 2012
From: Barry.Song at csr.com (Barry Song)
Date: Thu, 23 Aug 2012 14:09:52 +0800
Subject: [PATCH] ARM: PRIMA2: rstc: use of_property_read_u32 to replace
 of_get_property and be32_to_cpup
Message-ID: <1345702192-1153-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/mach-prima2/rstc.c |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 762adb7..d03ff19 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -42,13 +42,10 @@ early_initcall(sirfsoc_of_rstc_init);
 
 int sirfsoc_reset_device(struct device *dev)
 {
-	const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
-	unsigned int reset_bit;
+	u32 reset_bit;
 
-	if (!prop)
-		return -ENODEV;
-
-	reset_bit = be32_to_cpup(prop);
+	if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+		return -EINVAL;
 
 	mutex_lock(&rstc_lock);
 
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From richard.zhao at freescale.com  Thu Aug 23 02:12:03 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Thu, 23 Aug 2012 14:12:03 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <5035BDBF.9020602@wwwdotorg.org>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <5035BDBF.9020602@wwwdotorg.org>
Message-ID: <20120823061202.GM4011@b20223-02.ap.freescale.net>

On Wed, Aug 22, 2012 at 11:21:03PM -0600, Stephen Warren wrote:
> On 08/22/2012 01:18 AM, Dong Aisheng wrote:
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> > diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> 
> > @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
> >  	rdesc->ops = &anatop_rops;
> >  	rdesc->type = REGULATOR_VOLTAGE;
> >  	rdesc->owner = THIS_MODULE;
> > -	sreg->mfd = anatopmfd;
> > +
> > +	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
> > +	if (!sreg->anatop)
> > +		return -ENODEV;
> 
> In fact, that imx_syscon_lookup function I proposed could even do the
> of_parse_phandle() internally, so perhaps:
> 
> foo->syscon_dev = imx_syscon_lookup(np, "fsl,anatop", 0);
> if (IS_ERR(foo->syscon_dev))
>     return PTR_ERR(foo->syscon_dev);
> 
> with imx_syscon_lookup() internally knowing when to return EPROBE_DEFER
> rather than any other permanent error code (e.g. for missing property,
> bad phandle, etc.)
In some case that we access register in machine code, we don't have any
phandler. The node is got by find compatible or by path.

Thanks
Richard 



From hdoyu at nvidia.com  Thu Aug 23 02:15:19 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:15:19 +0300
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool
 with GFP_ATOMIC
In-Reply-To: <012401cd80f4$59727020$0c575060$%szyprowski@samsung.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
 <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
 <20120822.163648.3800987367886904.hdoyu@nvidia.com>
 <012401cd80f4$59727020$0c575060$%szyprowski@samsung.com>
Message-ID: <20120823091519.804aeae4ba93bcfe011e787c@nvidia.com>

Hi,

On Thu, 23 Aug 2012 07:58:34 +0200
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> Hello,
> 
> On Wednesday, August 22, 2012 3:37 PM Hiroshi Doyu wrote:
> 
> > KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00 +0200:
> > 
> > > vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic context.
> > 
> > Right.
> > 
> > I've been thinking that kzalloc() may be enough here, since
> > vzalloc() was introduced to avoid allocation failure for big chunk of
> > memory, but I think that it's unlikely that the number of page array
> > can be so big. So I propose to drop vzalloc() here, and just simply to
> > use kzalloc only as below(*1).
> 
> We already had a discussion about this, so I don't think it makes much sense to
> change it back to kzalloc. This vmalloc() call won't hurt anyone. It should not
> be considered a problem for atomic allocations, because no sane driver will try
> to allocate buffers larger than a dozen KiB with GFP_ATOMIC flag. I would call
> such try a serious bug, which we should not care here.

Ok, I've already sent v2 just now, where, instead of changing it back,
just with GFP_ATOMIC, kzalloc() would be selected, just in case. I guess
that this would be ok(a bit safer?)


From artem.bityutskiy at linux.intel.com  Thu Aug 23 02:35:18 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Thu, 23 Aug 2012 09:35:18 +0300
Subject: JFFS2 issue with v3.5.x and later on Atmel chips at least (was:
 Kernel oops since v3.5.x on Atmel chips)
In-Reply-To: <5034F3F8.9080802@atmel.com>
References: <5034B45A.5060107@atmel.com> <5034F3F8.9080802@atmel.com>
Message-ID: <1345703718.2848.200.camel@sauron.fi.intel.com>

On Wed, 2012-08-22 at 17:00 +0200, ludovic.desroches wrote:
> After bisection the commit causing this issue is:
> 
> commit 8bdc81c5069e43755d6e59e5e990e21ca200e8e2
> Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Date:   Mon May 7 19:56:53 2012 +0300
> 
>      jffs2: get rid of jffs2_sync_super

Thanks Ludovic for bisecting the issue, I'll take a look at this.

-- 
Best Regards,
Artem Bityutskiy
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From balbi at ti.com  Thu Aug 23 02:26:47 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 09:26:47 +0300
Subject: [PATCH v2 00/13] OMAP Serial patches
In-Reply-To: <1345551371-18862-1-git-send-email-balbi@ti.com>
References: <1345540555-24359-1-git-send-email-balbi@ti.com>
 <1345551371-18862-1-git-send-email-balbi@ti.com>
Message-ID: <20120823062646.GC31295@arwen.pp.htv.fi>

Hi,

On Tue, Aug 21, 2012 at 03:15:58PM +0300, Felipe Balbi wrote:
> Hi guys,
> 
> here's a series of cleanup patches to the OMAP serial
> driver. A later series could be made re-implementing
> DMA using the DMA Engine API. Note that for RX DMA
> we could be using RX Timeout IRQ as a hint that we better
> use PIO instead ;-)
> 
> All patches were tested on my pandaboard, but I'd really
> like to receive Tested-by on other platforms.
> 
> After this goes in, I'll probably try to get UART wakeup
> working again and only after that look at DMA.
> 
> Changes since v1:
> 
> 	. improved commit log on patch 9/13 (formerly 10/13)
> 	. removed patch 2/13
> 	. added a new patch switching from spin_lock_irqsave() to spin_lock and
> 		spin_unlock_irqrestore to spin_unlock
> 
> Retested with my pandaboard, UART continues to work:
> 
>  # grep -i uart /proc/interrupts
>  106:        124          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        189          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        255          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        321          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        387          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        453          0       GIC  OMAP UART2
>  #  grep -i uart /proc/interrupts
>  106:        519          0       GIC  OMAP UART2
> 
> cheers
> 
> ps: if anyone knows a better test for UART, let me know.
> 
> for convenience of anyone testing, patches are available on my git tree [1] on
> branch uart
> 
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart

Well, it turns out we found a small issue with one of these patches. We
have already fixed the isse. Will re-send the series soon with a few
more patches added. cheers

-- 
balbi
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From peter.ujfalusi at ti.com  Thu Aug 23 02:35:01 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 09:35:01 +0300
Subject: [PATCH] ARM: OMAP2+: twl-common: Fix compile time error when
 omap-twl4030 audio is not enabled
Message-ID: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>

Fixes:
CC      arch/arm/mach-omap2/twl-common.o arch/arm/mach-omap2/twl-common.c:562: error: conflicting types for ?omap_twl4030_audio_init?
arch/arm/mach-omap2/twl-common.h:62: error: previous declaration of ?omap_twl4030_audio_init? was here
make[1]: *** [arch/arm/mach-omap2/twl-common.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2

When building the kernel with !SND_OMAP_SOC_OMAP_TWL4030

Reported-by: Brian Austin <brian.austin at cirrus.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/twl-common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 1c6045a..2919d7a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -544,7 +544,7 @@ void __init omap_twl4030_audio_init(char *card_name)
 }
 
 #else /* SOC_OMAP_TWL4030 */
-void __init omap_twl4030_audio_init(char *card_name, int codec_sysclk)
+void __init omap_twl4030_audio_init(char *card_name)
 {
 	return;
 }
-- 
1.7.8.6



From minchan at kernel.org  Thu Aug 23 02:43:57 2012
From: minchan at kernel.org (Minchan Kim)
Date: Thu, 23 Aug 2012 15:43:57 +0900
Subject: [v2 0/4] ARM: dma-mapping: IOMMU atomic allocation
In-Reply-To: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <20120823064357.GD5369@bbox>

On Thu, Aug 23, 2012 at 09:10:25AM +0300, Hiroshi Doyu wrote:
> Hi,
> 
> The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
> region" breaks the compatibility with existing drivers. This causes
> the following kernel oops(*1). That driver has called dma_pool_alloc()
> to allocate memory from the interrupt context, and it hits
> BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
> fixes this problem with making use of the pre-allocate atomic memory
> pool which DMA is using in the same way as DMA does now.
> 
> Any comment would be really appreciated.
> 
> v2:
> Don't modify attrs(DMA_ATTR_NO_KERNEL_MAPPING) for atomic allocation. (Marek)
> Skip vzalloc (KyongHo, Minchan)

Huh? I would like to correct exactly. I didn't say that kzalloc unify is okay.
As KyongHo said, there are other usecases for allocating big buffer but
I can't agree his opinion that it's system memory shortage if the allocation
fails. Because there are lots of freeable pages(cached page + anon pages
with swap , shrinkable slab and so on). But as I said early, VM can't do
anything except relying on kswapd in atomic context while there are a ton
of freeable pages in system and we can't gaurantee kswapd will do something
for us before seeing the page allocation failure in process context.
Especially, UP is more problem. So, it never indicate system needs more memory.

Atomic high order allocation is very fragile in VM POV
so caller should have fallback mechanism. Otherwise, don't do that.

-- 
Kind regards,
Minchan Kim


From santosh.shilimkar at ti.com  Thu Aug 23 03:05:08 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 23 Aug 2012 12:35:08 +0530
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <201208221722.06775.arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-3-git-send-email-arnd@arndb.de>
 <CAMQu2gw0x6saWrK-M3teu49tJDGvS8RhGrVSh6JTs5DEy+22pA@mail.gmail.com>
 <201208221722.06775.arnd@arndb.de>
Message-ID: <CAMQu2gw_090MiWxs6m=5o0wQhL=ovmN1Y_7DUVhTbJU6mHPS5Q@mail.gmail.com>

On Wed, Aug 22, 2012 at 10:52 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>
> On Wednesday 22 August 2012, Shilimkar, Santosh wrote:
>
> > Was just thinking whether we should just take care of it at
> > core cpuidle level itself. Will below be enough to kill the build
> > error what you mentioned in the change log ?
> >
> > diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
> > index 2c9bf26..df34534 100644
> > --- a/drivers/cpuidle/coupled.c
> > +++ b/drivers/cpuidle/coupled.c
> > @@ -314,7 +314,9 @@ static void cpuidle_coupled_poke(int cpu)
> >         struct call_single_data *csd = &per_cpu(cpuidle_coupled_poke_cb,
> > cpu);
> >
> >         if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask))
> > +#ifdef CONFIG_SMP
> >                 __smp_call_function_single(cpu, csd, 0);
> > +#endif
> >  }
> >
>
> That would work, but isn't the entire concept of the cpuidle-coupled
> driver
> dependent on SMP? If this driver makes no sense on UP, I think we should
> not attempt to build it.
>
I see your point but alternate patch is pushing down the fix to the low
level driver and that means you end up patching more drivers when they
use COUPLE idle infrastructure. That was the only reason I was thinking
of suppressing the error at the source.

Since it is just for the random builds and actually doesn't impact the real
functionality as such, I am fine with your proposed patch too.

Regards
santosh


From richard.genoud at gmail.com  Thu Aug 23 03:06:46 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Thu, 23 Aug 2012 09:06:46 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <5034FC18.2090400@wwwdotorg.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <5034FC18.2090400@wwwdotorg.org>
Message-ID: <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>

2012/8/22 Stephen Warren <swarren at wwwdotorg.org>:
>>> +Required properties for iomux controller:
>>> +- compatible: "atmel,at91rm9200-pinctrl"
>>> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
>>> +  configured in this periph mode. All the periph and bank need to be describe.
>>
>> Can you please be more elaborate on this mux-mask, like what each bit
>> means and why the bits are arranged like that and what it means on the
>> AT91 platform.... I was first reading the .dts and was like ?woot? so
>> I go to the bindings doc and I read this and I'm still like ?woot?..
>
> Yes, I'm a little confused what this is, and wouldn't have a clue how to
> fill it in.
With a practical example it's easier to understand.
Take a SAM9X5 release manual (here is sam9g35):
http://www.atmel.com/Images/doc11053.pdf page 11 (?4.3 package pinout)
in the file arch/arm/boot/dts/at91sam9x5.dtsi you've got the the
atmel,mux-mask like that:
/* periphA  periphB    periphC     */
0xffffffff 0xffe0399f 0xc000001c  /* pioA */
0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
0x003fffff 0x003f8000 0x00000000  /* pioD */

Let's take the PioA - peripheral B: 0xffe0399f
>From the documentation table 4-3, we can extract the column PIO
Periperal B for all signals PA0-PA31:
     PIO Peripheral B
PA0  SPI1_NPCS1
PA1  SPI1_NPCS2
PA2  MCI1_DA1
PA3  MCI1_DA2
PA4  MCI1_DA3
PA5  --------
PA6  --------
PA7  SPI0_NPCS1
PA8  SPI1_NPCS0
PA9  --------
PA10 --------
PA11 MCI1_DA0
PA12 MCI1_CDA
PA13 MCI1_CK
PA14 --------
PA15 --------
etc...
Each time it's possible to mux a pin to the peripheral B function (ie
when there's no "-----") the corresponding bit is set:
     PIO Peripheral B
PA0  SPI1_NPCS1   1
PA1  SPI1_NPCS2   1
PA2  MCI1_DA1     1
PA3  MCI1_DA2     1

PA4  MCI1_DA3     1
PA5  --------     0
PA6  --------     0
PA7  SPI0_NPCS1   1

PA8  SPI1_NPCS0   1
PA9  --------     0
PA10 --------     0
PA11 MCI1_DA0     1

PA12 MCI1_CDA     1
PA13 MCI1_CK      1
PA14 --------     0
PA15 --------     0

=> this gives 0x399f



Best regards,
Richard


From bigeasy at linutronix.de  Thu Aug 23 03:21:04 2012
From: bigeasy at linutronix.de (Sebastian Andrzej Siewior)
Date: Thu, 23 Aug 2012 09:21:04 +0200
Subject: [PATCH 1/2] usb: change the dependency chain for LPC32XX and
 ISP1301
In-Reply-To: <50355A2C.9010505@antcom.de>
References: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
 <50355A2C.9010505@antcom.de>
Message-ID: <5035D9E0.1000905@linutronix.de>

On 08/23/2012 12:16 AM, Roland Stigge wrote:
> This issue could be resolved in a different way: Have you followed the
> discussion at linux-arm-kernel at lists.infradead.org on 2012-08-20,
> Subject "i2c: pnx: Fix bit definitions"? If nothing unexpected turns
> out, PNX4008 should probably be removed altogether. (Practically
> abandoned arch for 6 years.) Easily possible for v3.7.

Ach. I assumed that is being merged. The PNX arch does not define
USB_ARCH_HAS_OHCI so I goes that you can't select it there?

> Then, the resulting solution is much simpler and Sebastian's patch obsolete.

That would be what?

>
> Thanks,
>
> Roland

Sebastian


From b29396 at freescale.com  Thu Aug 23 03:06:58 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 23 Aug 2012 15:06:58 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <5035BCB1.8000801@wwwdotorg.org>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822082940.GJ4011@b20223-02.ap.freescale.net>
 <20120822105729.GB10057@shlinux2.ap.freescale.net>
 <5035BCB1.8000801@wwwdotorg.org>
Message-ID: <20120823070657.GE10057@shlinux2.ap.freescale.net>

On Thu, Aug 23, 2012 at 01:16:33PM +0800, Stephen Warren wrote:
> On 08/22/2012 04:57 AM, Dong Aisheng wrote:
> > On Wed, Aug 22, 2012 at 04:29:41PM +0800, Zhao Richard-B20223 wrote:
> >> On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> >>> Add regmap based imx syscon driver.
> >>> This is usually used for access misc bits in registers which does not belong
> >>> to a specific module, for example, IOMUXC GPR and ANATOP.
> >>> With this driver, we provide a standard API for client driver to call to
> >>> access registers which are registered into syscon.
> 
> >>> +static int imx_syscon_match(struct device *dev, void *data)
> >>> +{
> >>> +	struct imx_syscon *syscon = dev_get_drvdata(dev);
> >>> +	struct device_node *dn = data;
> >>> +
> >>> +	return (syscon->dev->of_node == dn) ? 1 : 0;
> >>> +}
> >>> +
> >>> +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
> >>
> >> For API function, is it better to use struct device rather not np?
> >>  - it won't need to search dev in below code every time it access
> >>    registers.
> >
> > The purpose is not require client driver to know the implementation details
> > of imx_syscon_{read/write} API, it's more easy to use since client only
> > needs pass the device node to which it wants to read/write.
> > 
> > For search dev, it doesn't look like a big issue since it only search devices
> > attached on the driver which is very quick.
> > And hide it in common API does not require every client driver to write
> > duplicated codes.
> 
> You could still implement a function:
> 
> struct device *imx_syscon_lookup(struct device_node *np)
> 
> ... and require all clients to call that, and pass the dev to the other
> functions. That'd still keep all the lookup code in one place, but
> prevent it having to run every time, no matter how small it is.
> 
> I think such an API is required anyway, since client drivers need some
> way to determine whether the imx_syscon driver is available yet, and if
> not defer their probe until it is.
> 
> So, clients would do:
> 
> foo->syscon_dev = imx_syscon_lookup(np);
> if (!foo->syscon_dev)
>     return -EPROBE_DEFER;
> 
> rather than:
> 
> foo->syscon_np = np;
> 
> Not too much overhead/boiler-plate in each client driver.
> 
Looks like a good idea.

Regards
Dong Aisheng



From m.szyprowski at samsung.com  Thu Aug 23 03:33:05 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 23 Aug 2012 09:33:05 +0200
Subject: [v2 4/4] ARM: dma-mapping: IOMMU allocates pages from atomic_pool
 with GFP_ATOMIC
In-Reply-To: <1345702229-9539-5-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
 <1345702229-9539-5-git-send-email-hdoyu@nvidia.com>
Message-ID: <013c01cd8101$8ccfa020$a66ee060$%szyprowski@samsung.com>

Hi Hiroshi,

On Thursday, August 23, 2012 8:10 AM Hiroshi Doyu wrote:

> Makes use of the same atomic pool from DMA, and skips kernel page
> mapping which can involve sleep'able operations at allocating a kernel
> page table.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   30 +++++++++++++++++++++++++-----
>  1 files changed, 25 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 7ab016b..433312a 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1063,7 +1063,6 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> size,
>  	struct page **pages;
>  	int count = size >> PAGE_SHIFT;
>  	int array_size = count * sizeof(struct page *);
> -	int err;
> 
>  	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
>  		pages = kzalloc(array_size, gfp);
> @@ -1072,9 +1071,20 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t
> size,
>  	if (!pages)
>  		return NULL;
> 
> -	err = __alloc_fill_pages(&pages, count, gfp);
> -	if (err)
> -		goto error
> +	if (gfp & GFP_ATOMIC) {
> +		struct page *page;
> +		int i;
> +		void *addr = __alloc_from_pool(size, &page);
> +		if (!addr)
> +			goto error;
> +
> +		for (i = 0; i < count; i++)
> +			pages[i] = page + i;
> +	} else {
> +		int err = __alloc_fill_pages(&pages, count, gfp);
> +		if (err)
> +			goto error;
> +	}
> 
>  	return pages;
> 
> @@ -1091,9 +1101,15 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages,
> size_t s
>  	int count = size >> PAGE_SHIFT;
>  	int array_size = count * sizeof(struct page *);
>  	int i;
> +
> +	if (__free_from_pool(page_address(pages[0]), size))
> +		goto out;
> +
>  	for (i = 0; i < count; i++)
>  		if (pages[i])
>  			__free_pages(pages[i], 0);
> +
> +out:
>  	if ((array_size <= PAGE_SIZE) ||
>  	    __in_atomic_pool(page_address(pages[0]), size))
>  		kfree(pages);
> @@ -1221,6 +1237,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
>  	if (*handle == DMA_ERROR_CODE)
>  		goto err_buffer;
> 
> +	if (gfp & GFP_ATOMIC)
> +		return page_address(pages[0]);
> +
>  	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
>  		return pages;
> 

I've read the whole code and it looks that it starts to become a little spaghetti - there are too
many places altered by those atomic changes and it is hard to follow the logic at the first sight.

IMHO it will be better to add a following function:

static void *__iommu_alloc_atomic(struct device *dev, size_t size,
                                  dma_addr_t *handle)
{
        struct page *page, **pages;
        int count = size >> PAGE_SHIFT;
        int array_size = count * sizeof(struct page *);
        void *addr;
        int i;

        pages = kzalloc(array_size, gfp);
        if (!pages)
                return NULL;

        addr = __alloc_from_pool(size, &page);
        if (!addr)
                goto err_pool;

        for (i = 0; i < count; i++)
                pages[i] = page + i;

        *handle = __iommu_create_mapping(dev, pages, size);
        if (*handle == DMA_ERROR_CODE)
                goto err_mapping;

        return addr;

err_mapping:
        __free_from_pool(addr, size);
err_pool:
        kfree(pages);
        return NULL;
}

and then call it at the beginning of the arm_iommu_alloc_attrs():

        if (gfp & GFP_ATOMIC)
                return __iommu_alloc_atomic(dev, size, handle);

You should also add support for the allocation from atomic_pool to __iommu_get_pages() function
to get dma_mmap() and dma_get_sgtable() working correctly.
 
> @@ -1279,7 +1298,8 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void
> *cpu_addr,
>  		return;
>  	}
> 
> -	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
> +	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs) ||
> +	    !__in_atomic_pool(cpu_addr, size)) {
>  		unmap_kernel_range((unsigned long)cpu_addr, size);
>  		vunmap(cpu_addr);
>  	}

Are you sure this one works?  __iommu_get_pages() won't find pages array, because atomic
allocations don't get their separate vm_struct area, so this check will be never reached. Maybe
a __iommu_free_atomic() function would also make it safer and easier to understand.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From b29396 at freescale.com  Thu Aug 23 03:15:04 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 23 Aug 2012 15:15:04 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <20120822155953.GQ7995@opensource.wolfsonmicro.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <20120822155953.GQ7995@opensource.wolfsonmicro.com>
Message-ID: <20120823071503.GF10057@shlinux2.ap.freescale.net>

On Wed, Aug 22, 2012 at 11:59:53PM +0800, Mark Brown wrote:
> On Wed, Aug 22, 2012 at 03:18:45PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Using standard imx syscon API to access anatop register.
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
Thanks

> With the conversion to regmap it'd also be good to convert the driver to
> use the regmap helper functions for enable and voltage operations if
> possible.

The anatop-regulator driver only implements set_voltage_sel/get_voltage_sel
which i have already converted, what do you mean others like
'for enable and voltage operations' i should also convert?

Regards
Dong Aisheng



From linux at prisktech.co.nz  Thu Aug 23 03:35:39 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:39 +1200
Subject: [PATCHv4 3/9] serial: vt8500: Add devicetree support for vt8500-serial
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-4-git-send-email-linux@prisktech.co.nz>

Increase vt8500_max_ports to 6 as the WM8505 as 6 available uarts.
Use devicetree port id as primary addressing for ports but allow
auto-allocation if id not specified.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/tty/serial/vt8500_serial.c |   58 ++++++++++++++++++++++++++++++++----
 1 file changed, 53 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006f..205d4cf 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -76,6 +77,8 @@
 #define RX_FIFO_INTS	(RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
 #define TX_FIFO_INTS	(TXFAE | TXFE | TXUDR)
 
+#define VT8500_MAX_PORTS	6
+
 struct vt8500_port {
 	struct uart_port	uart;
 	char			name[16];
@@ -83,6 +86,13 @@ struct vt8500_port {
 	unsigned int		ier;
 };
 
+/*
+ * we use this variable to keep track of which ports
+ * have been allocated as we can't use pdev->id in
+ * devicetree
+ */
+static unsigned long vt8500_ports_in_use;
+
 static inline void vt8500_write(struct uart_port *port, unsigned int val,
 			     unsigned int off)
 {
@@ -431,7 +441,7 @@ static int vt8500_verify_port(struct uart_port *port,
 	return 0;
 }
 
-static struct vt8500_port *vt8500_uart_ports[4];
+static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
 static struct uart_driver vt8500_uart_driver;
 
 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
@@ -548,7 +558,9 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 {
 	struct vt8500_port *vt8500_port;
 	struct resource *mmres, *irqres;
+	struct device_node *np = pdev->dev.of_node;
 	int ret;
+	int port;
 
 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -559,16 +571,46 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 	if (!vt8500_port)
 		return -ENOMEM;
 
+	if (np)
+		port = of_alias_get_id(np, "serial");
+		if (port > VT8500_MAX_PORTS)
+			port = -1;
+	else
+		port = -1;
+
+	if (port < 0) {
+		/* calculate the port id */
+		port = find_first_zero_bit(&vt8500_ports_in_use,
+					sizeof(vt8500_ports_in_use));
+	}
+
+	if (port > VT8500_MAX_PORTS)
+		return -ENODEV;
+
+	/* reserve the port id */
+	if (test_and_set_bit(port, &vt8500_ports_in_use)) {
+		/* port already in use - shouldn't really happen */
+		return -EBUSY;
+	}
+
 	vt8500_port->uart.type = PORT_VT8500;
 	vt8500_port->uart.iotype = UPIO_MEM;
 	vt8500_port->uart.mapbase = mmres->start;
 	vt8500_port->uart.irq = irqres->start;
 	vt8500_port->uart.fifosize = 16;
 	vt8500_port->uart.ops = &vt8500_uart_pops;
-	vt8500_port->uart.line = pdev->id;
+	vt8500_port->uart.line = port;
 	vt8500_port->uart.dev = &pdev->dev;
 	vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
-	vt8500_port->uart.uartclk = 24000000;
+
+	vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
+	if (vt8500_port->clk) {
+		vt8500_port->uart.uartclk = clk_get_rate(vt8500_port->clk);
+	} else {
+		/* use the default of 24Mhz if not specified and warn */
+		pr_warn("%s: serial clock source not specified\n", __func__);
+		vt8500_port->uart.uartclk = 24000000;
+	}
 
 	snprintf(vt8500_port->name, sizeof(vt8500_port->name),
 		 "VT8500 UART%d", pdev->id);
@@ -579,7 +621,7 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 		goto err;
 	}
 
-	vt8500_uart_ports[pdev->id] = vt8500_port;
+	vt8500_uart_ports[port] = vt8500_port;
 
 	uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
 
@@ -603,12 +645,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-uart", },
+	{}
+};
+
 static struct platform_driver vt8500_platform_driver = {
 	.probe  = vt8500_serial_probe,
 	.remove = __devexit_p(vt8500_serial_remove),
 	.driver = {
 		.name = "vt8500_serial",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -642,4 +690,4 @@ module_exit(vt8500_serial_exit);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("Driver for vt8500 serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:44 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:44 +1200
Subject: [PATCHv4 8/9] arm: vt8500: gpio: Devicetree support for arch-vt8500
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-9-git-send-email-linux@prisktech.co.nz>

Converted the existing arch-vt8500 gpio to a platform_device.
Added support for WM8505 and WM8650 GPIO controllers.
Replaced existing readl/writel calls with _relaxed variants.
Replaced existing unsigned variables with u32 to match register size.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/gpio/Kconfig       |    6 +
 drivers/gpio/Makefile      |    1 +
 drivers/gpio/gpio-vt8500.c |  316 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 323 insertions(+)
 create mode 100644 drivers/gpio/gpio-vt8500.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 542f0c0..3c8897a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,12 @@ config GPIO_STA2X11
 	  Say yes here to support the STA2x11/ConneXt GPIO device.
 	  The GPIO module has 128 GPIO pins with alternate functions.
 
+config GPIO_VT8500
+	bool "VIA/Wondermedia SoC GPIO Support"
+	depends on ARCH_VT8500
+	help
+	  Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
 config GPIO_XILINX
 	bool "Xilinx GPIO support"
 	depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0f55662..2c014b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)	+= gpio-twl4030.o
 obj-$(CONFIG_GPIO_UCB1400)	+= gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)	+= gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500)	+= gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)	+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)	+= gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
new file mode 100644
index 0000000..bcd8e4a
--- /dev/null
+++ b/drivers/gpio/gpio-vt8500.c
@@ -0,0 +1,316 @@
+/* drivers/gpio/gpio-vt8500.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ * Based on arch/arm/mach-vt8500/gpio.c:
+ * - Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+
+/*
+	We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
+	by one set of registers (although not all may be valid).
+
+	Because different SoC's have different register offsets, we pass the
+	register offsets as data in vt8500_gpio_dt_ids[].
+
+	A value of NO_REG is used to indicate that this register is not
+	supported. Only used for ->en at the moment.
+*/
+
+#define NO_REG	0xFFFF
+
+/*
+ * struct vt8500_gpio_bank_regoffsets
+ * @en: offset to enable register of the bank
+ * @dir: offset to direction register of the bank
+ * @data_out: offset to the data out register of the bank
+ * @data_in: offset to the data in register of the bank
+ * @ngpio: highest valid pin in this bank
+ */
+
+struct vt8500_gpio_bank_regoffsets {
+	unsigned int	en;
+	unsigned int	dir;
+	unsigned int	data_out;
+	unsigned int	data_in;
+	unsigned char	ngpio;
+};
+
+struct vt8500_gpio_data {
+	unsigned int				num_banks;
+	struct vt8500_gpio_bank_regoffsets	banks[];
+};
+
+#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)		\
+{								\
+	.en = __en,						\
+	.dir = __dir,						\
+	.data_out = __out,					\
+	.data_in = __in,					\
+	.ngpio = __ngpio,					\
+}
+
+static struct vt8500_gpio_data vt8500_data = {
+	.num_banks	= 7,
+	.banks	= {
+		VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
+		VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
+		VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
+		VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
+		VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
+		VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
+		VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
+	},
+};
+
+static struct vt8500_gpio_data wm8505_data = {
+	.num_banks	= 10,
+	.banks	= {
+		VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
+		VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
+		VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
+		VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
+		VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
+		VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
+		VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
+		VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
+		VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
+		VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+	},
+};
+
+/*
+ * No information about which bits are valid so we just make
+ * them all available until its figured out.
+ */
+static struct vt8500_gpio_data wm8650_data = {
+	.num_banks	= 9,
+	.banks	= {
+		VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
+		VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
+		VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
+		VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
+		VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
+		VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
+		VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
+		VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
+		VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+	},
+};
+
+struct vt8500_gpio_chip {
+	struct gpio_chip		chip;
+
+	const struct vt8500_gpio_bank_regoffsets *regs;
+	void __iomem	*base;
+};
+
+
+#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
+
+static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	u32 val;
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return 0;
+
+	val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
+	val |= BIT(offset);
+	writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
+
+	return 0;
+}
+
+static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+	u32 val;
+
+	if (vt8500_chip->regs->en == NO_REG)
+		return;
+
+	val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
+	val &= ~BIT(offset);
+	writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
+}
+
+static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
+	val &= ~BIT(offset);
+	writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	return 0;
+}
+
+static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
+	val |= BIT(offset);
+	writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+	if (value) {
+		val = readl_relaxed(vt8500_chip->base +
+						vt8500_chip->regs->data_out);
+		val |= BIT(offset);
+		writel_relaxed(val, vt8500_chip->base +
+						vt8500_chip->regs->data_out);
+	}
+	return 0;
+}
+
+static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	return (readl_relaxed(vt8500_chip->base + vt8500_chip->regs->data_in) >>
+								offset) & 1;
+}
+
+static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+								int value)
+{
+	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+	u32 val = readl_relaxed(vt8500_chip->base +
+						vt8500_chip->regs->data_out);
+	if (value)
+		val |= BIT(offset);
+	else
+		val &= ~BIT(offset);
+
+	writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+}
+
+static int vt8500_of_xlate(struct gpio_chip *gc,
+			    const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	/* bank if specificed in gpiospec->args[0] */
+	if (flags)
+		*flags = gpiospec->args[2];
+
+	return gpiospec->args[1];
+}
+
+static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
+				const struct vt8500_gpio_data *data)
+{
+	struct vt8500_gpio_chip *vtchip;
+	struct gpio_chip *chip;
+	int i;
+	int pin_cnt = 0;
+
+	vtchip = devm_kzalloc(&pdev->dev,
+			sizeof(struct vt8500_gpio_chip) * data->num_banks,
+			GFP_KERNEL);
+	if (!vtchip) {
+		pr_err("%s: failed to allocate chip memory\n", __func__);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < data->num_banks; i++) {
+		vtchip[i].base = base;
+		vtchip[i].regs = &data->banks[i];
+
+		chip = &vtchip[i].chip;
+
+		chip->of_xlate = vt8500_of_xlate;
+		chip->of_gpio_n_cells = 3;
+		chip->of_node = pdev->dev.of_node;
+
+		chip->request = vt8500_gpio_request;
+		chip->free = vt8500_gpio_free;
+		chip->direction_input = vt8500_gpio_direction_input;
+		chip->direction_output = vt8500_gpio_direction_output;
+		chip->get = vt8500_gpio_get_value;
+		chip->set = vt8500_gpio_set_value;
+		chip->can_sleep = 0;
+		chip->base = pin_cnt;
+		chip->ngpio = data->banks[i].ngpio;
+
+		pin_cnt += data->banks[i].ngpio;
+
+		gpiochip_add(chip);
+	}
+	return 0;
+}
+
+static struct of_device_id vt8500_gpio_dt_ids[] = {
+	{ .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
+	{ .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
+	{ .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
+	{ /* Sentinel */ },
+};
+
+static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
+{
+	void __iomem *gpio_base;
+	struct device_node *np;
+	const struct of_device_id *of_id =
+				of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
+
+	if (!of_id) {
+		dev_err(&pdev->dev, "Failed to find gpio controller\n");
+		return -ENODEV;
+	}
+
+	np = pdev->dev.of_node;
+	if (!np) {
+		dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
+		return -EFAULT;
+	}
+
+	gpio_base = of_iomap(np, 0);
+	if (!gpio_base) {
+		dev_err(&pdev->dev, "Unable to map GPIO registers\n");
+		of_node_put(np);
+		return -ENOMEM;
+	}
+
+	vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+	return 0;
+}
+
+static struct platform_driver vt8500_gpio_driver = {
+	.probe		= vt8500_gpio_probe,
+	.driver		= {
+		.name	= "vt8500-gpio",
+		.owner	= THIS_MODULE,
+		.of_match_table = vt8500_gpio_dt_ids,
+	},
+};
+
+module_platform_driver(vt8500_gpio_driver);
+
+MODULE_DESCRIPTION("VT8500 GPIO Driver");
+MODULE_AUTHOR("Tony Prisk <linux at prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:38 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:38 +1200
Subject: [PATCHv4 2/9] rtc: vt8500: Add devicetree support for vt8500-rtc
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-3-git-send-email-linux@prisktech.co.nz>

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/rtc/rtc-vt8500.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-vt8500.c b/drivers/rtc/rtc-vt8500.c
index 9e94fb1..07bf193 100644
--- a/drivers/rtc/rtc-vt8500.c
+++ b/drivers/rtc/rtc-vt8500.c
@@ -23,6 +23,7 @@
 #include <linux/bcd.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 /*
  * Register definitions
@@ -302,12 +303,18 @@ static int __devexit vt8500_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "via,vt8500-rtc", },
+	{}
+};
+
 static struct platform_driver vt8500_rtc_driver = {
 	.probe		= vt8500_rtc_probe,
 	.remove		= __devexit_p(vt8500_rtc_remove),
 	.driver		= {
 		.name	= "vt8500-rtc",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -315,5 +322,5 @@ module_platform_driver(vt8500_rtc_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:vt8500-rtc");
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:45 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:45 +1200
Subject: [PATCHv4 9/9] arm: vt8500: clk: Add Common Clock Framework support
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-10-git-send-email-linux@prisktech.co.nz>

This patch adds common clock framework support for arch-vt8500.
Support for PLL and device clocks on VT8500, WM8505 and WM8650
are included.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/clk/Makefile     |    1 +
 drivers/clk/clk-vt8500.c |  511 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 512 insertions(+)
 create mode 100644 drivers/clk/clk-vt8500.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..42fb173 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
new file mode 100644
index 0000000..2f7c77d
--- /dev/null
+++ b/drivers/clk/clk-vt8500.c
@@ -0,0 +1,511 @@
+/* drivers/clk/clk-vt8500.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+/* All clocks share the same lock as none can be changed concurrently */
+static DEFINE_SPINLOCK(_lock);
+
+struct clk_device {
+	struct clk_hw	hw;
+	void __iomem	*div_reg;
+	unsigned int	div_mask;
+	void __iomem	*en_reg;
+	int		en_bit;
+	spinlock_t	*lock;
+};
+
+/*
+ * Add new PLL_TYPE_x definitions here as required. Use the first known model
+ * to support the new type as the name.
+ * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
+ * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
+ */
+
+#define PLL_TYPE_VT8500		0
+#define PLL_TYPE_WM8650		1
+
+struct clk_pll {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	spinlock_t	*lock;
+	int		type;
+};
+
+static void __iomem *pmc_base;
+
+#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
+
+
+#define VT8500_PMC_BUSY_MASK		0x18
+
+static void vt8500_pmc_wait_busy(void)
+{
+	while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
+		cpu_relax();
+}
+
+static void vt8500_dclk_endisable(struct clk_hw *hw, int enable)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 en_val;
+	unsigned long flags = 0;
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	en_val = readl(cdev->en_reg);
+
+	if (enable)
+		en_val |= BIT(cdev->en_bit);
+	else
+		en_val &= ~BIT(cdev->en_bit);
+
+	writel(en_val, cdev->en_reg);
+
+	spin_unlock_irqrestore(cdev->lock, flags);
+}
+
+static int vt8500_dclk_enable(struct clk_hw *hw)
+{
+	vt8500_dclk_endisable(hw, 1);
+	return 0;
+}
+
+static void vt8500_dclk_disable(struct clk_hw *hw)
+{
+	vt8500_dclk_endisable(hw, 0);
+}
+
+static int vt8500_dclk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
+
+	return en_val ? 1 : 0;
+}
+
+static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 div = readl(cdev->div_reg) & cdev->div_mask;
+
+	/* Special case for SDMMC devices */
+	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
+		div = 64 * (div & 0x1f);
+
+	/* div == 0 is actually the highest divisor */
+	if (div == 0)
+		div = (cdev->div_mask + 1);
+
+	return parent_rate / div;
+}
+
+static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	u32 divisor = rate / *prate;
+
+	return *prate / divisor;
+}
+
+static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_device *cdev = to_clk_device(hw);
+	u32 divisor = rate / parent_rate;
+	unsigned long flags = 0;
+
+	if (divisor == cdev->div_mask + 1)
+		divisor = 0;
+
+	if (divisor > cdev->div_mask) {
+		pr_err("%s: invalid divisor for clock\n", __func__);
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	vt8500_pmc_wait_busy();
+	writel(divisor, cdev->div_reg);
+	vt8500_pmc_wait_busy();
+
+	spin_lock_irqsave(cdev->lock, flags);
+
+	return 0;
+}
+
+
+static const struct clk_ops vt8500_gated_clk_ops = {
+	.enable = vt8500_dclk_enable,
+	.disable = vt8500_dclk_disable,
+	.is_enabled = vt8500_dclk_is_enabled,
+};
+
+static const struct clk_ops vt8500_divisor_clk_ops = {
+	.round_rate = vt8500_dclk_round_rate,
+	.set_rate = vt8500_dclk_set_rate,
+	.recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+static const struct clk_ops vt8500_gated_divisor_clk_ops = {
+	.enable = vt8500_dclk_enable,
+	.disable = vt8500_dclk_disable,
+	.is_enabled = vt8500_dclk_is_enabled,
+	.round_rate = vt8500_dclk_round_rate,
+	.set_rate = vt8500_dclk_set_rate,
+	.recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+#define CLK_INIT_GATED			BIT(0)
+#define CLK_INIT_DIVISOR		BIT(1)
+#define CLK_INIT_GATED_DIVISOR		(CLK_INIT_DIVISOR | CLK_INIT_GATED)
+
+static __init void vtwm_device_clk_init(struct device_node *node)
+{
+	u32 en_reg, div_reg;
+	struct clk *clk;
+	struct clk_device *dev_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+	int clk_init_flags = 0;
+
+	dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
+	if (WARN_ON(!dev_clk))
+		return;
+
+	dev_clk->lock = &_lock;
+
+	rc = of_property_read_u32(node, "enable-reg", &en_reg);
+	if (!rc) {
+		dev_clk->en_reg = pmc_base + en_reg;
+		rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
+		if (rc) {
+			pr_err("%s: enable-bit property required for gated clock\n",
+								__func__);
+			return;
+		}
+		clk_init_flags |= CLK_INIT_GATED;
+	}
+
+	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
+	if (!rc) {
+		dev_clk->div_reg = pmc_base + div_reg;
+		/*
+		 * use 0x1f as the default mask since it covers
+		 * almost all the clocks and reduces dts properties
+		 */
+		dev_clk->div_mask = 0x1f;
+
+		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
+		clk_init_flags |= CLK_INIT_DIVISOR;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	switch (clk_init_flags) {
+	case CLK_INIT_GATED:
+		init.ops = &vt8500_gated_clk_ops;
+		break;
+	case CLK_INIT_DIVISOR:
+		init.ops = &vt8500_divisor_clk_ops;
+		break;
+	case CLK_INIT_GATED_DIVISOR:
+		init.ops = &vt8500_gated_divisor_clk_ops;
+		break;
+	default:
+		pr_err("%s: Invalid clock description in device tree\n",
+								__func__);
+		kfree(dev_clk);
+		return;
+	}
+
+	init.name = clk_name;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	dev_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &dev_clk->hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(dev_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* PLL clock related functions */
+
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Helper macros for PLL_VT8500 */
+#define VT8500_PLL_MUL(x)	((x & 0x1F) << 1)
+#define VT8500_PLL_DIV(x)	((x & 0x100) ? 1 : 2)
+
+#define VT8500_BITS_TO_FREQ(r, m, d)					\
+				((r / d) * m)
+
+#define VT8500_BITS_TO_VAL(m, d)					\
+				((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
+
+/* Helper macros for PLL_WM8650 */
+#define WM8650_PLL_MUL(x)	(x & 0x3FF)
+#define WM8650_PLL_DIV(x)	(((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
+
+#define WM8650_BITS_TO_FREQ(r, m, d1, d2)				\
+				(r * m / (d1 * (1 << d2)))
+
+#define WM8650_BITS_TO_VAL(m, d1, d2)					\
+				((d2 << 13) | (d1 << 10) | (m & 0x3FF))
+
+
+static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *prediv)
+{
+	unsigned long tclk;
+
+	/* sanity check */
+	if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
+		pr_err("%s: requested rate out of range\n", __func__);
+		*multiplier = 0;
+		*prediv = 1;
+		return;
+	}
+	if (rate <= parent_rate * 31)
+		/* use the prediv to double the resolution */
+		*prediv = 2;
+	else
+		*prediv = 1;
+
+	*multiplier = rate / (parent_rate / *prediv);
+	tclk = (parent_rate / *prediv) * *multiplier;
+
+	if (tclk != rate)
+		pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
+								rate, tclk);
+}
+
+static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+{
+	u32 mul, div1, div2;
+	u32 best_mul, best_div1, best_div2;
+	unsigned long tclk, rate_err, best_err;
+
+	best_err = (unsigned long)-1;
+
+	/* Find the closest match (lower or equal to requested) */
+	for (div1 = 5; div1 >= 3; div1--)
+		for (div2 = 3; div2 >= 0; div2--)
+			for (mul = 3; mul <= 1023; mul++) {
+				tclk = parent_rate * mul / (div1 * (1 << div2));
+				if (tclk > rate)
+					continue;
+				/* error will always be +ve */
+				rate_err = rate - tclk;
+				if (rate_err == 0) {
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
+					return;
+				}
+
+				if (rate_err < best_err) {
+					best_err = rate_err;
+					best_mul = mul;
+					best_div1 = div1;
+					best_div2 = div2;
+				}
+			}
+
+	/* if we got here, it wasn't an exact match */
+	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
+							rate - best_err);
+	*multiplier = mul;
+	*divisor1 = div1;
+	*divisor2 = div2;
+}
+
+static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mul, div1, div2;
+	u32 pll_val;
+	unsigned long flags = 0;
+
+	/* sanity check */
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
+		pll_val = VT8500_BITS_TO_VAL(mul, div1);
+		break;
+	case PLL_TYPE_WM8650:
+		wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
+		pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
+		break;
+	default:
+		pr_err("%s: invalid pll type\n", __func__);
+		return 0;
+	}
+
+	spin_lock_irqsave(pll->lock, flags);
+
+	vt8500_pmc_wait_busy();
+	writel(pll_val, pll->reg);
+	vt8500_pmc_wait_busy();
+
+	spin_unlock_irqrestore(pll->lock, flags);
+
+	return 0;
+}
+
+static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 mul, div1, div2;
+	long round_rate;
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		vt8500_find_pll_bits(rate, *prate, &mul, &div1);
+		round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
+		break;
+	case PLL_TYPE_WM8650:
+		wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
+		round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
+		break;
+	default:
+		round_rate = 0;
+	}
+
+	return round_rate;
+}
+
+static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	u32 pll_val = readl(pll->reg);
+	unsigned long pll_freq;
+
+	switch (pll->type) {
+	case PLL_TYPE_VT8500:
+		pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
+		pll_freq /= VT8500_PLL_DIV(pll_val);
+		break;
+	case PLL_TYPE_WM8650:
+		pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
+		pll_freq /= WM8650_PLL_DIV(pll_val);
+		break;
+	default:
+		pll_freq = 0;
+	}
+
+	return pll_freq;
+}
+
+const struct clk_ops vtwm_pll_ops = {
+	.round_rate = vtwm_pll_round_rate,
+	.set_rate = vtwm_pll_set_rate,
+	.recalc_rate = vtwm_pll_recalc_rate,
+};
+
+static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
+{
+	u32 reg;
+	struct clk *clk;
+	struct clk_pll *pll_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	rc = of_property_read_u32(node, "reg", &reg);
+	if (WARN_ON(rc))
+		return;
+
+	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+	if (WARN_ON(!pll_clk))
+		return;
+
+	pll_clk->reg = pmc_base + reg;
+	pll_clk->lock = &_lock;
+	pll_clk->type = pll_type;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = &vtwm_pll_ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	pll_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &pll_clk->hw);
+	if (WARN_ON(IS_ERR(clk))) {
+		kfree(pll_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* Wrappers for initialization functions */
+
+static void __init vt8500_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
+}
+
+static void __init wm8650_pll_init(struct device_node *node)
+{
+	vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
+}
+
+static const __initconst struct of_device_id clk_match[] = {
+	{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{ .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
+	{ .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
+	{ .compatible = "via,vt8500-device-clock",
+					.data = vtwm_device_clk_init, },
+	{ /* sentinel */ }
+};
+
+void __init vtwm_clk_init(void __iomem *base)
+{
+	if (!base)
+		return;
+
+	pmc_base = base;
+
+	of_clk_init(clk_match);
+}
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:43 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:43 +1200
Subject: [PATCHv4 7/9] arm: vt8500: doc: Add device tree bindings for
 arch-vt8500 devices
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-8-git-send-email-linux@prisktech.co.nz>

Bindings for gpio, interrupt controller, power management controller,
timer, realtime clock, serial uart, ehci and uhci controllers and
framebuffer controllers used on the arch-vt8500 platform.

Framebuffer binding also specifies a 'display' node which is required
for determining the lcd panel data.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 ++++
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +++++
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 ++++
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 ++++
 Documentation/devicetree/bindings/clock/vt8500.txt |   72 ++++++++++++++++++++
 .../devicetree/bindings/gpio/gpio-vt8500.txt       |   24 +++++++
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 ++++
 .../bindings/tty/serial/via,vt8500-uart.txt        |   17 +++++
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 ++++
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 ++++
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   48 +++++++++++++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 ++++
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   22 ++++++
 14 files changed, 302 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt

diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
new file mode 100644
index 0000000..1b3b187
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the VIA VT8500 SoC shall have the following properties:
+Required root node property:
+compatible = "via,vt8500";
+
+Boards with the Wondermedia WM8505 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8505";
+
+Boards with the Wondermedia WM8650 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8650";
+
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
new file mode 100644
index 0000000..0a4ce10
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
@@ -0,0 +1,16 @@
+VIA/Wondermedia VT8500 Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-intc"
+- reg : Should contain 1 register ranges(address and length)
+- #interrupt-cells : should be <1>
+
+Example:
+
+	intc: interrupt-controller at d8140000 {
+		compatible = "via,vt8500-intc";
+		interrupt-controller;
+		reg = <0xd8140000 0x10000>;
+		#interrupt-cells = <1>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
new file mode 100644
index 0000000..521b9c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia VT8500 Power Management Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-pmc"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	pmc at d8130000 {
+		compatible = "via,vt8500-pmc";
+		reg = <0xd8130000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
new file mode 100644
index 0000000..901c73f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+	timer at d8130100 {
+		compatible = "via,vt8500-timer";
+		reg = <0xd8130100 0x28>;
+		interrupts = <36>;
+	};
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
new file mode 100644
index 0000000..a880c70
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -0,0 +1,72 @@
+Device Tree Clock bindings for arch-vt8500
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
+	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
+	"via,vt8500-device-clock" - for a VT/WM device clock
+
+Required properties for PLL clocks:
+- reg : shall be the control register offset from PMC base for the pll clock.
+- clocks : shall be the input parent clock phandle for the clock. This should
+	be the reference clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Required properties for device clocks:
+- clocks : shall be the input parent clock phandle for the clock. This should
+	be a pll output.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+
+Device Clocks
+
+Device clocks are required to have one or both of the following sets of
+properties:
+
+
+Gated device clocks:
+
+Required properties:
+- enable-reg : shall be the register offset from PMC base for the enable
+	register.
+- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
+
+
+Divisor device clocks:
+
+Required property:
+- divisor-reg : shall be the register offset from PMC base for the divisor
+	register.
+Optional property:
+- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
+	if not specified.
+
+
+For example:
+
+ref25: ref25M {
+	#clock-cells = <0>;
+	compatible = "fixed-clock";
+	clock-frequency = <25000000>;
+};
+
+plla: plla {
+	#clock-cells = <0>;
+	compatible = "wm,wm8650-pll-clock";
+	clocks = <&ref25>;
+	reg = <0x200>;
+};
+
+sdhc: sdhc {
+	#clock-cells = <0>;
+	compatible = "via,vt8500-device-clock";
+	clocks = <&pllb>;
+	divisor-reg = <0x328>;
+	divisor-mask = <0x3f>;
+	enable-reg = <0x254>;
+	enable-bit = <18>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
new file mode 100644
index 0000000..f4dc523
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+	or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+	1) bank
+	2) pin number
+	3) flags - should be 0
+
+Example:
+
+	gpio: gpio-controller at d8110000 {
+		compatible = "via,vt8500-gpio";
+		gpio-controller;
+		reg = <0xd8110000 0x10000>;
+		#gpio-cells = <3>;
+	};
+
+	vibrate {
+		gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+	};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 0000000..3c0484c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+	rtc at d8100000 {
+		compatible = "via,vt8500-rtc";
+		reg = <0xd8100000 0x10000>;
+		interrupts = <48>;
+	};
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
new file mode 100644
index 0000000..5feef1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
@@ -0,0 +1,17 @@
+VIA/Wondermedia VT8500 UART Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-uart"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UART interrupt
+- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
+
+Example:
+
+	uart at d8210000 {
+		compatible = "via,vt8500-uart";
+		reg = <0xd8210000 0x1040>;
+		interrupts = <47>;
+		clocks = <&ref24>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
new file mode 100644
index 0000000..a4fb071
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/platform-uhci.txt
@@ -0,0 +1,15 @@
+Generic Platform UHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "platform-uhci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UHCI controller interrupt
+
+Example:
+
+	uhci at d8007b00 {
+		compatible = "platform-uhci";
+		reg = <0xd8007b00 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
new file mode 100644
index 0000000..17b3ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 EHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-ehci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : ehci controller interrupt
+
+Example:
+
+	ehci at d8007900 {
+		compatible = "via,vt8500-ehci";
+		reg = <0xd8007900 0x200>;
+		interrupts = <43>;
+	};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af..5c63da2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -47,5 +47,7 @@ sirf	SiRF Technology, Inc.
 st	STMicroelectronics
 stericsson	ST-Ericsson
 ti	Texas Instruments
+via	VIA Technologies, Inc.
 wlf	Wolfson Microelectronics
+wm	Wondermedia Technologies, Inc.
 xlnx	Xilinx
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
new file mode 100644
index 0000000..98ad14c
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
@@ -0,0 +1,48 @@
+VIA VT8500 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-fb"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : framebuffer controller interrupt
+- via,display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts.
+
+Example:
+
+	fb at d800e400 {
+		compatible = "via,vt8500-fb";
+		reg = <0xd800e400 0x400>;
+		interrupts = <12>;
+		via,display = <&display>;
+	};
+
+VIA VT8500 Display
+-----------------------------------------------------
+Required properties:
+- xres : lcd panel horizontal resolution
+- yres : lcd panel vertical resolution
+- left-margin,
+- right-margin,
+- hsync-len: lcd panel horizontal timings in pixels
+- upper-margin,
+- lower-margin,
+- vsync-len: lcd panel verticals timings in pixels
+- bpp: lcd panel bit-depth.
+	<16> for RGB565, <32> for RGB888
+
+Example:
+	display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
new file mode 100644
index 0000000..a850fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia Graphics Engine Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,prizm-ge-rops"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+	ge_rops at d8050400 {
+		compatible = "wm,prizm-ge-rops";
+		reg = <0xd8050400 0x100>;
+	};
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
new file mode 100644
index 0000000..64f016a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -0,0 +1,22 @@
+Wondermedia WM8505 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,wm8505-fb"
+- reg : Should contain 1 register ranges(address and length)
+- via,display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+	This should be in the board dts. See definition in
+	Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+
+
+Example:
+
+	fb at d8050800 {
+		compatible = "wm,wm8505-fb";
+		reg = <0xd8050800 0x200>;
+		via,display = <&display>;
+	};
+
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:41 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:41 +1200
Subject: [PATCHv4 5/9] video: vt8500: Add devicetree support for vt8500-fb and
 wm8505-fb
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-6-git-send-email-linux@prisktech.co.nz>

Update vt8500-fb, wm8505-fb and wmt-ge-rops to support device
tree bindings.
Small change in wm8505-fb.c to support WM8650 framebuffer color
format.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/video/Kconfig       |    6 +--
 drivers/video/vt8500lcdfb.c |   79 ++++++++++++++++++++++++++++++-----
 drivers/video/wm8505fb.c    |   97 ++++++++++++++++++++++++++++++++++++-------
 drivers/video/wmt_ge_rops.c |    9 +++-
 4 files changed, 161 insertions(+), 30 deletions(-)

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..b66d951 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1788,7 +1788,7 @@ config FB_AU1200
 
 config FB_VT8500
 	bool "VT8500 LCD Driver"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
@@ -1797,11 +1797,11 @@ config FB_VT8500
 
 config FB_WM8505
 	bool "WM8505 frame buffer support"
-	depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+	depends on (FB = y) && ARM && ARCH_VT8500
 	select FB_WMT_GE_ROPS
 	select FB_SYS_IMAGEBLIT
 	help
-	  This is the framebuffer driver for WonderMedia WM8505
+	  This is the framebuffer driver for WonderMedia WM8505/WM8650
 	  integrated LCD controller.
 
 source "drivers/video/geode/Kconfig"
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6e..758e359 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -35,6 +35,13 @@
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
 
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
+#endif
+
+
 #define to_vt8500lcd_info(__info) container_of(__info, \
 						struct vt8500lcd_info, fb)
 
@@ -270,15 +277,21 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 {
 	struct vt8500lcd_info *fbi;
 	struct resource *res;
-	struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
 	void *addr;
 	int irq, ret;
 
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
+
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+			+ sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -333,9 +346,45 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
+	np = of_parse_phandle(pdev->dev.of_node, "via,display", 0);
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.fix.smem_start	= fb_mem_phys;
+	fbi->fb.fix.smem_len	= fb_mem_len;
+	fbi->fb.screen_base	= fb_mem_virt;
 
 	fbi->palette_size	= PAGE_ALIGN(512);
 	fbi->palette_cpu	= dma_alloc_coherent(&pdev->dev,
@@ -370,10 +419,11 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 		goto failed_free_irq;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
 
 	ret = vt8500lcd_set_par(&fbi->fb);
 	if (ret) {
@@ -448,12 +498,18 @@ static int __devexit vt8500lcd_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id via_dt_ids[] = {
+	{ .compatible = "via,vt8500-fb", },
+	{}
+};
+
 static struct platform_driver vt8500lcd_driver = {
 	.probe		= vt8500lcd_probe,
 	.remove		= __devexit_p(vt8500lcd_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "vt8500-lcd",
+		.of_match_table = of_match_ptr(via_dt_ids),
 	},
 };
 
@@ -461,4 +517,5 @@ module_platform_driver(vt8500lcd_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com>");
 MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, via_dt_ids);
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd..d4448b0 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/wait.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
 
 #include <mach/vt8500fb.h>
 
@@ -59,8 +62,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
 	writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
 
-	/* Set in-memory picture format to RGB 32bpp */
-	writel(0x1c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
+	/*
+	 * Set in-memory picture format to RGB
+	 * 0x31C sets the correct color mode (RGB565) for WM8650
+	 * Bit 8+9 (0x300) are ignored on WM8505 as reserved
+	 */
+	writel(0x31c,		       fbi->regbase + WMT_GOVR_COLORSPACE);
 	writel(1,		       fbi->regbase + WMT_GOVR_COLORSPACE1);
 
 	/* Virtual buffer size */
@@ -127,6 +134,18 @@ static int wm8505fb_set_par(struct fb_info *info)
 		info->var.blue.msb_right = 0;
 		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		info->fix.line_length = info->var.xres_virtual << 2;
+	} else if (info->var.bits_per_pixel == 16) {
+		info->var.red.offset = 11;
+		info->var.red.length = 5;
+		info->var.red.msb_right = 0;
+		info->var.green.offset = 5;
+		info->var.green.length = 6;
+		info->var.green.msb_right = 0;
+		info->var.blue.offset = 0;
+		info->var.blue.length = 5;
+		info->var.blue.msb_right = 0;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+		info->fix.line_length = info->var.xres_virtual << 1;
 	}
 
 	wm8505fb_set_timing(info);
@@ -246,16 +265,20 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 	struct wm8505fb_info	*fbi;
 	struct resource		*res;
 	void			*addr;
-	struct vt8500fb_platform_data *pdata;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
+	struct fb_videomode	of_mode;
+	struct device_node	*np;
+	u32			bpp;
+	dma_addr_t fb_mem_phys;
+	unsigned long fb_mem_len;
+	void *fb_mem_virt;
 
 	ret = -ENOMEM;
 	fbi = NULL;
 
-	fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
-							GFP_KERNEL);
+	fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
+			sizeof(u32) * 16, GFP_KERNEL);
 	if (!fbi) {
 		dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
 		ret = -ENOMEM;
@@ -305,21 +328,58 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
 		goto failed_free_res;
 	}
 
-	fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+	np = of_parse_phandle(pdev->dev.of_node, "via,display", 0);
+	if (!np) {
+		pr_err("%s: No display description in Device Tree\n", __func__);
+		ret = -EINVAL;
+		goto failed_free_res;
+	}
+
+	/*
+	 * This code is copied from Sascha Hauer's of_videomode helper
+	 * and can be replaced with a call to the helper once mainlined
+	 */
+	ret = 0;
+	ret |= of_property_read_u32(np, "xres", &of_mode.xres);
+	ret |= of_property_read_u32(np, "yres", &of_mode.yres);
+	ret |= of_property_read_u32(np, "left-margin", &of_mode.left_margin);
+	ret |= of_property_read_u32(np, "right-margin", &of_mode.right_margin);
+	ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+	ret |= of_property_read_u32(np, "upper-margin", &of_mode.upper_margin);
+	ret |= of_property_read_u32(np, "lower-margin", &of_mode.lower_margin);
+	ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+	ret |= of_property_read_u32(np, "bpp", &bpp);
+	if (ret) {
+		pr_err("%s: Unable to read display properties\n", __func__);
+		goto failed_free_res;
+	}
+
+	of_mode.vmode = FB_VMODE_NONINTERLACED;
+	fb_videomode_to_var(&fbi->fb.var, &of_mode);
 
 	fbi->fb.var.nonstd		= 0;
 	fbi->fb.var.activate		= FB_ACTIVATE_NOW;
 
 	fbi->fb.var.height		= -1;
 	fbi->fb.var.width		= -1;
-	fbi->fb.var.xres_virtual	= pdata->xres_virtual;
-	fbi->fb.var.yres_virtual	= pdata->yres_virtual;
-	fbi->fb.var.bits_per_pixel	= pdata->bpp;
 
-	fbi->fb.fix.smem_start	= pdata->video_mem_phys;
-	fbi->fb.fix.smem_len	= pdata->video_mem_len;
-	fbi->fb.screen_base	= pdata->video_mem_virt;
-	fbi->fb.screen_size	= pdata->video_mem_len;
+	/* try allocating the framebuffer */
+	fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+	fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+				GFP_KERNEL);
+	if (!fb_mem_virt) {
+		pr_err("%s: Failed to allocate framebuffer\n", __func__);
+		return -ENOMEM;
+	};
+
+	fbi->fb.var.xres_virtual	= of_mode.xres;
+	fbi->fb.var.yres_virtual	= of_mode.yres * 2;
+	fbi->fb.var.bits_per_pixel	= bpp;
+
+	fbi->fb.fix.smem_start		= fb_mem_phys;
+	fbi->fb.fix.smem_len		= fb_mem_len;
+	fbi->fb.screen_base		= fb_mem_virt;
+	fbi->fb.screen_size		= fb_mem_len;
 
 	if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
 		dev_err(&pdev->dev, "Failed to allocate color map\n");
@@ -395,12 +455,18 @@ static int __devexit wm8505fb_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,wm8505-fb", },
+	{}
+};
+
 static struct platform_driver wm8505fb_driver = {
 	.probe		= wm8505fb_probe,
 	.remove		= __devexit_p(wm8505fb_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -408,4 +474,5 @@ module_platform_driver(wm8505fb_driver);
 
 MODULE_AUTHOR("Ed Spiridonov <edo.rus at gmail.com>");
 MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 55be386..ba025b4 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -158,12 +158,18 @@ static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+	{ .compatible = "wm,prizm-ge-rops", },
+	{ /* sentinel */ }
+};
+
 static struct platform_driver wmt_ge_rops_driver = {
 	.probe		= wmt_ge_rops_probe,
 	.remove		= __devexit_p(wmt_ge_rops_remove),
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "wmt_ge_rops",
+		.of_match_table = of_match_ptr(wmt_dt_ids),
 	},
 };
 
@@ -172,4 +178,5 @@ module_platform_driver(wmt_ge_rops_driver);
 MODULE_AUTHOR("Alexey Charkov <alchark at gmail.com");
 MODULE_DESCRIPTION("Accelerators for raster operations using "
 		   "WonderMedia Graphics Engine");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:42 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:42 +1200
Subject: [PATCHv4 6/9] arm: vt8500: Update arch-vt8500 to devicetree support.
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-7-git-send-email-linux@prisktech.co.nz>

Merged existing board files to a single dt-capable file.
Converted irq and timer code to devicetree.
Removed existing device files that are no longer required with
devicetree support.
All existing platform devices are converted to devicetree nodes
except PWM.

Removed restart.c and moved code into vt8500.c to remove
duplicate PMC code.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/Kconfig                                |    5 +
 arch/arm/mach-vt8500/Kconfig                    |   72 +-----
 arch/arm/mach-vt8500/Makefile                   |    9 +-
 arch/arm/mach-vt8500/bv07.c                     |   80 -------
 arch/arm/mach-vt8500/common.h                   |   28 +++
 arch/arm/mach-vt8500/devices-vt8500.c           |   91 --------
 arch/arm/mach-vt8500/devices-wm8505.c           |   99 ---------
 arch/arm/mach-vt8500/devices.c                  |  270 -----------------------
 arch/arm/mach-vt8500/devices.h                  |   88 --------
 arch/arm/mach-vt8500/gpio.c                     |  240 --------------------
 arch/arm/mach-vt8500/include/mach/restart.h     |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h |   88 --------
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h |   79 -------
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h |  115 ----------
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h |   78 -------
 arch/arm/mach-vt8500/irq.c                      |  209 +++++++++++-------
 arch/arm/mach-vt8500/restart.c                  |   54 -----
 arch/arm/mach-vt8500/timer.c                    |   67 ++++--
 arch/arm/mach-vt8500/vt8500.c                   |  196 ++++++++++++++++
 arch/arm/mach-vt8500/wm8505_7in.c               |   79 -------
 20 files changed, 413 insertions(+), 1538 deletions(-)
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6774c80..ea8ec75 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -996,6 +996,10 @@ config ARCH_VT8500
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_PWM
+	select USE_OF
+	select COMMON_CLK
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
 	help
 	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1613,6 +1617,7 @@ config ARCH_NR_GPIO
 	default 355 if ARCH_U8500
 	default 264 if MACH_H4700
 	default 512 if SOC_OMAP5
+	default 288 if ARCH_VT8500
 	default 0
 	help
 	  Maximum number of GPIOs in the system.
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2c20a34..44f9f9d 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,73 +1,15 @@
 if ARCH_VT8500
 
-config VTWM_VERSION_VT8500
+config VTWM_VERSION_WMT_DT
 	bool
 
-config VTWM_VERSION_WM8505
-	bool
-
-config MACH_BV07
-	bool "Benign BV07-8500 Mini Netbook"
-	depends on ARCH_VT8500
-	select VTWM_VERSION_VT8500
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-	bool "WM8505 7-inch generic netbook"
+config MACH_WMT_DT
+	bool "VIA/Wondermedia SoC based boards (Device Tree Support)"
 	depends on ARCH_VT8500
-	select VTWM_VERSION_WM8505
-	help
-	  Add support for the inexpensive 7-inch netbooks sold by many
-	  Chinese distributors under various names. Note that there are
-	  many hardware implementations in identical exterior, make sure
-	  that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-	bool "7-inch with 800x480 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	default y
-	help
-	  These are found in most of the netbooks in generic cases, as
-	  well as in Eken M001 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x480' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_800X600
-	bool "8-inch with 800x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M003 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=800x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X576
-	bool "10-inch with 1024x576 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
+	select VTWM_VERSION_WMT_DT
 	help
-	  These are found in CherryPal netbooks and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x576' to your kernel command line. Otherwise, the
-	  largest one available will be used.
-
-config WMT_PANEL_1024X600
-	bool "10-inch with 1024x600 resolution"
-	depends on (FB_VT8500 || FB_WM8505)
-	help
-	  These are found in Eken M006 tablets and possibly elsewhere.
-
-	  To select this panel at runtime, say y here and append
-	  'panel=1024x600' to your kernel command line. Otherwise, the
-	  largest one available will be used.
+	  Add support for netbooks, tablets and other devices based on
+	  the reference board design as produced by VIA/WonderMedia, using
+	  VT8500/WM8505/WM8650 System-on-Chip.
 
 endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 54e6997..1966183 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,9 +1,4 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_VTWM_VERSION_WMT_DT) += irq.o timer.o
+obj-$(CONFIG_MACH_WMT_DT) += vt8500.o
 
 obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index f9fbeb2..0000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_lcdc,
-	&vt8500_device_ehci,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-	wmt_setup_restart();
-	vt8500_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= vt8500_reserve_mem,
-	.map_io		= vt8500_map_io,
-	.init_irq	= vt8500_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
new file mode 100644
index 0000000..2b24196
--- /dev/null
+++ b/arch/arm/mach-vt8500/common.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/mach-vt8500/dt_common.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
+
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+				struct device_node *parent);
+
+/* defined in drivers/clk/clk-vt8500.c */
+void __init vtwm_clk_init(void __iomem *pmc_base);
+
+#endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index 19519ae..0000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-	tmp[1] = wmt_irq_res(IRQ_LCDC);
-	wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = VT8500_IC_BASE;
-	wmt_gpio_base = VT8500_GPIO_BASE;
-	wmt_pmc_base = VT8500_PMC_BASE;
-	wmt_i8042_base = VT8500_PS2_BASE;
-
-	wmt_nr_irqs = VT8500_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index db4594e..0000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-	struct resource tmp[3];
-
-	tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-	wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART0);
-	wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART1);
-	wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART2);
-	wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART3);
-	wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART4);
-	wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-	tmp[1] = wmt_irq_res(IRQ_UART5);
-	wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-	tmp[1] = wmt_irq_res(IRQ_EHCI);
-	wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-	tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-	wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-	wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-	tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-	tmp[1] = wmt_irq_res(IRQ_RTC);
-	tmp[2] = wmt_irq_res(IRQ_RTCSM);
-	wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-	/* Non-resource-aware stuff */
-	wmt_ic_base = WM8505_IC_BASE;
-	wmt_sic_base = WM8505_SIC_BASE;
-	wmt_gpio_base = WM8505_GPIO_BASE;
-	wmt_pmc_base = WM8505_PMC_BASE;
-	wmt_i8042_base = WM8505_PS2_BASE;
-
-	wmt_nr_irqs = WM8505_NR_IRQS;
-	wmt_timer_irq = IRQ_PMCOS0;
-	wmt_gpio_ext_irq[0] = IRQ_EXT0;
-	wmt_gpio_ext_irq[1] = IRQ_EXT1;
-	wmt_gpio_ext_irq[2] = IRQ_EXT2;
-	wmt_gpio_ext_irq[3] = IRQ_EXT3;
-	wmt_gpio_ext_irq[4] = IRQ_EXT4;
-	wmt_gpio_ext_irq[5] = IRQ_EXT5;
-	wmt_gpio_ext_irq[6] = IRQ_EXT6;
-	wmt_gpio_ext_irq[7] = IRQ_EXT7;
-	wmt_i8042_kbd_irq = IRQ_PS2KBD;
-	wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	/* Should be done before interrupts and timers are initialized */
-	wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 1fcdc36..0000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-	.name           = "vt8500-lcd",
-	.id             = 0,
-	.dev		= {
-		.dma_mask	= &fb_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-	.name           = "wm8505-fb",
-	.id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 480 * 2,
-	.mode		= {
-		.name		= "800x480",
-		.xres		= 800,
-		.yres		= 480,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-	.xres_virtual	= 800,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "800x600",
-		.xres		= 800,
-		.yres		= 600,
-		.left_margin	= 88,
-		.right_margin	= 40,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 0,
-		.vsync_len	= 1,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 576 * 2,
-	.mode		= {
-		.name		= "1024x576",
-		.xres		= 1024,
-		.yres		= 576,
-		.left_margin	= 40,
-		.right_margin	= 24,
-		.upper_margin	= 32,
-		.lower_margin	= 11,
-		.hsync_len	= 96,
-		.vsync_len	= 2,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-	.xres_virtual	= 1024,
-	.yres_virtual	= 600 * 2,
-	.mode		= {
-		.name		= "1024x600",
-		.xres		= 1024,
-		.yres		= 600,
-		.left_margin	= 66,
-		.right_margin	= 2,
-		.upper_margin	= 19,
-		.lower_margin	= 1,
-		.hsync_len	= 23,
-		.vsync_len	= 8,
-		.vmode		= FB_VMODE_NONINTERLACED,
-	},
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(panels); i++) {
-		if (strcmp(panels[i].mode.name, str) == 0) {
-			current_panel_idx = i;
-			break;
-		}
-	}
-	return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-				  unsigned long align) {
-	p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-			(p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-					(8 / p->bpp) + 1));
-	p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-							  align);
-	p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-	.name		= "vt8500_serial",
-	.id		= 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-	.name		= "vt8500_serial",
-	.id		= 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-	.name		= "vt8500_serial",
-	.id		= 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-	.name		= "vt8500_serial",
-	.id		= 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-	.name		= "vt8500_serial",
-	.id		= 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-	.name		= "vt8500_serial",
-	.id		= 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-	.name		= "vt8500-ehci",
-	.id		= 0,
-	.dev		= {
-		.dma_mask	= &ehci_dma_mask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device vt8500_device_ge_rops = {
-	.name		= "wmt_ge_rops",
-	.id		= -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-	.name		= "vt8500-pwm",
-	.id		= 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-	.pwm_id		= 0,
-	.max_brightness	= 128,
-	.dft_brightness = 70,
-	.pwm_period_ns	= 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-	.name		= "pwm-backlight",
-	.id		= 0,
-	.dev		= {
-		.platform_data = &vt8500_pwmbl_data,
-	},
-};
-
-struct platform_device vt8500_device_rtc = {
-	.name		= "vt8500-rtc",
-	.id		= 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-	/* SoC MMIO registers */
-	[0] = {
-		.virtual	= 0xf8000000,
-		.pfn		= __phys_to_pfn(0xd8000000),
-		.length		= 0x00390000, /* max of all chip variants */
-		.type		= MT_DEVICE
-	},
-	/* PCI I/O space, numbers tied to those in <mach/io.h> */
-	[1] = {
-		.virtual	= 0xf0000000,
-		.pfn		= __phys_to_pfn(0xc0000000),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE
-	},
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-	panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-	preallocate_fb(&panels[current_panel_idx], SZ_4M);
-	vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-	panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-	preallocate_fb(&panels[current_panel_idx], 32);
-	vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 188d4e1..0000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_MEM,
-		.start = start,
-		.end = start + size - 1,
-	};
-
-	return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-	struct resource tmp = {
-		.flags = IORESOURCE_IRQ,
-		.start = irq,
-		.end = irq,
-	};
-
-	return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-			       const struct resource *res, unsigned int num)
-{
-	if (unlikely(platform_device_add_resources(pdev, res, num)))
-		pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec..0000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS	0x0
-#define DIRECTION_REGS	0x20
-#define OUTVALUE_REGS	0x40
-#define INVALUE_REGS	0x60
-
-#define EXT_REGOFF	0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-	struct gpio_chip	chip;
-	unsigned int		shift;
-	unsigned int		regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-				     unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-				   unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val &= ~(1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	val |= (1 << vt8500_chip->shift << offset);
-	writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-		val |= (1 << vt8500_chip->shift << offset);
-		writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-	}
-	return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-	return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-		>> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-	unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-	if (value)
-		val |= (1 << vt8500_chip->shift << offset);
-	else
-		val &= ~(1 << vt8500_chip->shift << offset);
-
-	writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)		\
-{									\
-	.chip = {							\
-		.label			= __name,			\
-		.request		= vt8500_muxed_gpio_request,	\
-		.free			= vt8500_muxed_gpio_free,	\
-		.direction_input  = vt8500_muxed_gpio_direction_input,	\
-		.direction_output = vt8500_muxed_gpio_direction_output,	\
-		.get			= vt8500_muxed_gpio_get_value,	\
-		.set			= vt8500_muxed_gpio_set_value,	\
-		.can_sleep		= 0,				\
-		.base			= __base,			\
-		.ngpio			= __num,			\
-	},								\
-	.shift		= __shift,					\
-	.regoff		= __off,					\
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-	VT8500_GPIO_BANK("uart0",	0,	0x0,	8,	4),
-	VT8500_GPIO_BANK("uart1",	4,	0x0,	12,	4),
-	VT8500_GPIO_BANK("spi0",	8,	0x0,	16,	4),
-	VT8500_GPIO_BANK("spi1",	12,	0x0,	20,	4),
-	VT8500_GPIO_BANK("spi2",	16,	0x0,	24,	4),
-	VT8500_GPIO_BANK("pwmout",	24,	0x0,	28,	2),
-
-	VT8500_GPIO_BANK("sdmmc",	0,	0x4,	30,	11),
-	VT8500_GPIO_BANK("ms",		16,	0x4,	41,	7),
-	VT8500_GPIO_BANK("i2c0",	24,	0x4,	48,	2),
-	VT8500_GPIO_BANK("i2c1",	26,	0x4,	50,	2),
-
-	VT8500_GPIO_BANK("mii",		0,	0x8,	52,	20),
-	VT8500_GPIO_BANK("see",		20,	0x8,	72,	4),
-	VT8500_GPIO_BANK("ide",		24,	0x8,	76,	7),
-
-	VT8500_GPIO_BANK("ccir",	0,	0xc,	83,	19),
-
-	VT8500_GPIO_BANK("ts",		8,	0x10,	102,	11),
-
-	VT8500_GPIO_BANK("lcd",		0,	0x14,	113,	23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val &= ~(1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-	return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	val |= (1 << offset);
-	writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-	if (value) {
-		val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-		val |= (1 << offset);
-		writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-	}
-	return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-				       unsigned offset)
-{
-	return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-	if (value)
-		val |= (1 << offset);
-	else
-		val &= ~(1 << offset);
-
-	writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	if (offset > 7)
-		return -EINVAL;
-
-	return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-	.label			= "extgpio",
-	.direction_input	= vt8500_gpio_direction_input,
-	.direction_output	= vt8500_gpio_direction_output,
-	.get			= vt8500_gpio_get_value,
-	.set			= vt8500_gpio_set_value,
-	.to_irq			= vt8500_gpio_to_irq,
-	.can_sleep		= 0,
-	.base			= 0,
-	.ngpio			= 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-	int i;
-
-	for (i = 0; i < 8; i++)
-		gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-	regbase = ioremap(wmt_gpio_base, SZ_64K);
-	if (!regbase) {
-		printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-		return;
-	}
-
-	gpiochip_add(&vt8500_external_gpios);
-
-	for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-		gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b78..7389795 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee91..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC	0	/* JPEG Encoder */
-#define IRQ_JPEGDEC	1	/* JPEG Decoder */
-				/* Reserved */
-#define IRQ_PATA	3	/* PATA Controller */
-				/* Reserved */
-#define IRQ_DMA		5	/* DMA Controller */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_GE		8	/* Graphic Engine */
-#define IRQ_GOV		9	/* Graphic Overlay Engine */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-#define IRQ_MPEGTS	11	/* Transport Stream Interface */
-#define IRQ_LCDC	12	/* LCD Controller */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_CIPHER	16	/* Cipher */
-#define IRQ_VPP		17	/* Video Post-Processor */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-				/* Reserved */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_LCDDF	27	/* LCD Data Formatter */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_MS		30	/* MemoryStick Controller */
-#define IRQ_MS_DMA	31	/* MemoryStick Controller DMA */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_I2S		34	/* I2S */
-#define IRQ_PCM		35	/* PCM */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_VPU		40	/* Video Processing Unit */
-#define IRQ_VID		41	/* Video Digital Input Interface */
-#define IRQ_AC97	42	/* AC97 Interface */
-#define IRQ_EHCI	43	/* USB */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_PS2MOUSE	45	/* PS/2 Mouse */
-#define IRQ_PS2KBD	46	/* PS/2 Keyboard */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_ADC		51	/* ADC */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_DMA0	56	/* DMA Channel 0 */
-#define IRQ_DMA1	57	/* DMA Channel 1 */
-#define IRQ_DMA2	58	/* DMA Channel 2 */
-#define IRQ_DMA3	59	/* DMA Channel 3 */
-#define IRQ_DMA4	60	/* DMA Channel 4 */
-#define IRQ_DMA5	61	/* DMA Channel 5 */
-#define IRQ_DMA6	62	/* DMA Channel 6 */
-#define IRQ_DMA7	63	/* DMA Channel 7 */
-
-#define VT8500_NR_IRQS		64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ec..0000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define VT8500_DDR_BASE		0xd8000000	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define VT8500_DMA_BASE		0xd8001000	/* 1k	DMA Controller */
-#define VT8500_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define VT8500_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define VT8500_USB_BASE		0xd8007800	/* 2k	USB OTG */
-# define VT8500_EHCI_BASE	0xd8007900	/*	EHCI */
-# define VT8500_UHCI_BASE	0xd8007b01	/*	UHCI */
-#define VT8500_PATA_BASE	0xd8008000	/* 512	PATA */
-#define VT8500_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define VT8500_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define VT8500_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define VT8500_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define VT8500_MS_BASE		0xd800b000	/* 1k	MS/MSPRO Controller */
-#define VT8500_LCDC_BASE	0xd800e400	/* 1k	LCD Controller */
-#define VT8500_VPU_BASE		0xd8050000	/* 256	VPU */
-#define VT8500_GOV_BASE		0xd8050300	/* 256	GOV */
-#define VT8500_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE	0xd8050900	/* 256	LCD Formatter */
-#define VT8500_VID_BASE		0xd8050a00	/* 256	VID */
-#define VT8500_VPP_BASE		0xd8050b00	/* 256	VPP */
-#define VT8500_TSBK_BASE	0xd80f4000	/* 4k	TSBK */
-#define VT8500_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define VT8500_JPEGENC_BASE	0xd80ff000	/* 4k	JPEG Encoder */
-#define VT8500_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define VT8500_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define VT8500_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define VT8500_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define VT8500_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define VT8500_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define VT8500_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define VT8500_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define VT8500_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define VT8500_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define VT8500_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define VT8500_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define VT8500_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define VT8500_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define VT8500_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define VT8500_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define VT8500_PCM_BASE		0xd82d0000	/* 64k	PCM */
-#define VT8500_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define VT8500_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define VT8500_ADC_BASE		0xd8340000	/* 64k	ADC */
-
-#define VT8500_REGS_END_PHYS	0xd834ffff	/* End of MMIO registers */
-#define VT8500_REGS_LENGTH	(VT8500_REGS_END_PHYS \
-				- VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI	0	/* UHC FS (UHCI?) */
-#define IRQ_EHCI	1	/* UHC HS */
-#define IRQ_UDCDMA	2	/* UDC DMA */
-				/* Reserved */
-#define IRQ_PS2MOUSE	4	/* PS/2 Mouse */
-#define IRQ_UDC		5	/* UDC */
-#define IRQ_EXT0	6	/* External Interrupt 0 */
-#define IRQ_EXT1	7	/* External Interrupt 1 */
-#define IRQ_KEYPAD	8	/* Keypad */
-#define IRQ_DMA		9	/* DMA Controller */
-#define IRQ_ETHER	10	/* Ethernet MAC */
-				/* Reserved */
-				/* Reserved */
-#define IRQ_EXT2	13	/* External Interrupt 2 */
-#define IRQ_EXT3	14	/* External Interrupt 3 */
-#define IRQ_EXT4	15	/* External Interrupt 4 */
-#define IRQ_APB		16	/* APB Bridge */
-#define IRQ_DMA0	17	/* DMA Channel 0 */
-#define IRQ_I2C1	18	/* I2C 1 */
-#define IRQ_I2C0	19	/* I2C 0 */
-#define IRQ_SDMMC	20	/* SD/MMC Controller */
-#define IRQ_SDMMC_DMA	21	/* SD/MMC Controller DMA */
-#define IRQ_PMC_WU	22	/* Power Management Controller Wakeup */
-#define IRQ_PS2KBD	23	/* PS/2 Keyboard */
-#define IRQ_SPI0	24	/* SPI 0 */
-#define IRQ_SPI1	25	/* SPI 1 */
-#define IRQ_SPI2	26	/* SPI 2 */
-#define IRQ_DMA1	27	/* DMA Channel 1 */
-#define IRQ_NAND	28	/* NAND Flash Controller */
-#define IRQ_NAND_DMA	29	/* NAND Flash Controller DMA */
-#define IRQ_UART5	30	/* UART 5 */
-#define IRQ_UART4	31	/* UART 4 */
-#define IRQ_UART0	32	/* UART 0 */
-#define IRQ_UART1	33	/* UART 1 */
-#define IRQ_DMA2	34	/* DMA Channel 2 */
-#define IRQ_I2S		35	/* I2S */
-#define IRQ_PMCOS0	36	/* PMC OS Timer 0 */
-#define IRQ_PMCOS1	37	/* PMC OS Timer 1 */
-#define IRQ_PMCOS2	38	/* PMC OS Timer 2 */
-#define IRQ_PMCOS3	39	/* PMC OS Timer 3 */
-#define IRQ_DMA3	40	/* DMA Channel 3 */
-#define IRQ_DMA4	41	/* DMA Channel 4 */
-#define IRQ_AC97	42	/* AC97 Interface */
-				/* Reserved */
-#define IRQ_NOR		44	/* NOR Flash Controller */
-#define IRQ_DMA5	45	/* DMA Channel 5 */
-#define IRQ_DMA6	46	/* DMA Channel 6 */
-#define IRQ_UART2	47	/* UART 2 */
-#define IRQ_RTC		48	/* RTC Interrupt */
-#define IRQ_RTCSM	49	/* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3	50	/* UART 3 */
-#define IRQ_DMA7	51	/* DMA Channel 7 */
-#define IRQ_EXT5	52	/* External Interrupt 5 */
-#define IRQ_EXT6	53	/* External Interrupt 6 */
-#define IRQ_EXT7	54	/* External Interrupt 7 */
-#define IRQ_CIR		55	/* CIR */
-#define IRQ_SIC0	56	/* SIC IRQ0 */
-#define IRQ_SIC1	57	/* SIC IRQ1 */
-#define IRQ_SIC2	58	/* SIC IRQ2 */
-#define IRQ_SIC3	59	/* SIC IRQ3 */
-#define IRQ_SIC4	60	/* SIC IRQ4 */
-#define IRQ_SIC5	61	/* SIC IRQ5 */
-#define IRQ_SIC6	62	/* SIC IRQ6 */
-#define IRQ_SIC7	63	/* SIC IRQ7 */
-				/* Reserved */
-#define IRQ_JPEGDEC	65	/* JPEG Decoder */
-#define IRQ_SAE		66	/* SAE (?) */
-				/* Reserved */
-#define IRQ_VPU		79	/* Video Processing Unit */
-#define IRQ_VPP		80	/* Video Post-Processor */
-#define IRQ_VID		81	/* Video Digital Input Interface */
-#define IRQ_SPU		82	/* SPU (?) */
-#define IRQ_PIP		83	/* PIP Error */
-#define IRQ_GE		84	/* Graphic Engine */
-#define IRQ_GOV		85	/* Graphic Overlay Engine */
-#define IRQ_DVO		86	/* Digital Video Output */
-				/* Reserved */
-#define IRQ_DMA8	92	/* DMA Channel 8 */
-#define IRQ_DMA9	93	/* DMA Channel 9 */
-#define IRQ_DMA10	94	/* DMA Channel 10 */
-#define IRQ_DMA11	95	/* DMA Channel 11 */
-#define IRQ_DMA12	96	/* DMA Channel 12 */
-#define IRQ_DMA13	97	/* DMA Channel 13 */
-#define IRQ_DMA14	98	/* DMA Channel 14 */
-#define IRQ_DMA15	99	/* DMA Channel 15 */
-				/* Reserved */
-#define IRQ_GOVW	111	/* GOVW (?) */
-#define IRQ_GOVRSDSCD	112	/* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF	113	/* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD	114	/* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF	115	/* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS		116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df15509..0000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS	0xd8000000	/* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT	0xf8000000	/* Virtual mapping start */
-
-#define WM8505_DDR_BASE		0xd8000400	/* 1k	DDR/DDR2 Memory
-							Controller */
-#define WM8505_DMA_BASE		0xd8001800	/* 1k	DMA Controller */
-#define WM8505_VDMA_BASE	0xd8001c00	/* 1k	VDMA */
-#define WM8505_SFLASH_BASE	0xd8002000	/* 1k	Serial Flash Memory
-							Controller */
-#define WM8505_ETHER_BASE	0xd8004000	/* 1k	Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE	0xd8006000	/* 4k	Cipher */
-#define WM8505_USB_BASE		0xd8007000	/* 2k	USB 2.0 Host */
-# define WM8505_EHCI_BASE	0xd8007100	/*	EHCI */
-# define WM8505_UHCI_BASE	0xd8007301	/*	UHCI */
-#define WM8505_PS2_BASE		0xd8008800	/* 1k	PS/2 */
-#define WM8505_NAND_BASE	0xd8009000	/* 1k	NAND Controller */
-#define WM8505_NOR_BASE		0xd8009400	/* 1k	NOR Controller */
-#define WM8505_SDMMC_BASE	0xd800a000	/* 1k	SD/MMC Controller */
-#define WM8505_VPU_BASE		0xd8050000	/* 256	VPU */
-#define WM8505_GOV_BASE		0xd8050300	/* 256	GOV */
-#define WM8505_GEGEA_BASE	0xd8050400	/* 768	GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE	0xd8050800	/* 512	GOVR (frambuffer) */
-#define WM8505_VID_BASE		0xd8050a00	/* 256	VID */
-#define WM8505_SCL_BASE		0xd8050d00	/* 256	SCL */
-#define WM8505_VPP_BASE		0xd8050f00	/* 256	VPP */
-#define WM8505_JPEGDEC_BASE	0xd80fe000	/* 4k	JPEG Decoder */
-#define WM8505_RTC_BASE		0xd8100000	/* 64k	RTC */
-#define WM8505_GPIO_BASE	0xd8110000	/* 64k	GPIO Configuration */
-#define WM8505_SCC_BASE		0xd8120000	/* 64k	System Configuration*/
-#define WM8505_PMC_BASE		0xd8130000	/* 64k	PMC Configuration */
-#define WM8505_IC_BASE		0xd8140000	/* 64k	Interrupt Controller*/
-#define WM8505_SIC_BASE		0xd8150000	/* 64k	Secondary IC */
-#define WM8505_UART0_BASE	0xd8200000	/* 64k	UART 0 */
-#define WM8505_UART2_BASE	0xd8210000	/* 64k	UART 2 */
-#define WM8505_PWM_BASE		0xd8220000	/* 64k	PWM Configuration */
-#define WM8505_SPI0_BASE	0xd8240000	/* 64k	SPI 0 */
-#define WM8505_SPI1_BASE	0xd8250000	/* 64k	SPI 1 */
-#define WM8505_KEYPAD_BASE	0xd8260000	/* 64k	Keypad control */
-#define WM8505_CIR_BASE		0xd8270000	/* 64k	CIR */
-#define WM8505_I2C0_BASE	0xd8280000	/* 64k	I2C 0 */
-#define WM8505_AC97_BASE	0xd8290000	/* 64k	AC97 */
-#define WM8505_SPI2_BASE	0xd82a0000	/* 64k	SPI 2 */
-#define WM8505_UART1_BASE	0xd82b0000	/* 64k	UART 1 */
-#define WM8505_UART3_BASE	0xd82c0000	/* 64k	UART 3 */
-#define WM8505_I2C1_BASE	0xd8320000	/* 64k	I2C 1 */
-#define WM8505_I2S_BASE		0xd8330000	/* 64k	I2S */
-#define WM8505_UART4_BASE	0xd8370000	/* 64k	UART 4 */
-#define WM8505_UART5_BASE	0xd8380000	/* 64k	UART 5 */
-
-#define WM8505_REGS_END_PHYS	0xd838ffff	/* End of MMIO registers */
-#define WM8505_REGS_LENGTH	(WM8505_REGS_END_PHYS \
-				- WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de04..f8f9ab9 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
  *  arch/arm/mach-vt8500/irq.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,81 +19,102 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR		0x40		/* Destination control
-						register, 64*u8 */
-#define VT8500_INT_ENABLE	(1 << 3)
-#define VT8500_TRIGGER_HIGH	(0 << 4)
-#define VT8500_TRIGGER_RISING	(1 << 4)
-#define VT8500_TRIGGER_FALLING	(2 << 4)
+#define VT8500_ICPC_IRQ		0x20
+#define VT8500_ICPC_FIQ		0x24
+#define VT8500_ICDC		0x40		/* Destination Control 64*u32 */
+#define VT8500_ICIS		0x80		/* Interrupt status, 16*u32 */
+
+/* ICPC */
+#define ICPC_MASK		0x3F
+#define ICPC_ROTATE		BIT(6)
+
+/* IC_DCTR */
+#define ICDC_IRQ		0x00
+#define ICDC_FIQ		0x01
+#define ICDC_DSS0		0x02
+#define ICDC_DSS1		0x03
+#define ICDC_DSS2		0x04
+#define ICDC_DSS3		0x05
+#define ICDC_DSS4		0x06
+#define ICDC_DSS5		0x07
+
+#define VT8500_INT_DISABLE	0
+#define VT8500_INT_ENABLE	BIT(3)
+
+#define VT8500_TRIGGER_HIGH	0
+#define VT8500_TRIGGER_RISING	BIT(5)
+#define VT8500_TRIGGER_FALLING	BIT(6)
 #define VT8500_EDGE		( VT8500_TRIGGER_RISING \
 				| VT8500_TRIGGER_FALLING)
-#define VT8500_IC_STATUS	0x80		/* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt;
+
+struct vt8500_irq_priv {
+	void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 edge;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
 	if (edge) {
-		void __iomem *stat_reg = base + VT8500_IC_STATUS
-						+ (irq < 32 ? 0 : 4);
+		void __iomem *stat_reg = base + VT8500_ICIS
+						+ (d->hwirq < 32 ? 0 : 4);
 		unsigned status = readl(stat_reg);
 
-		status |= (1 << (irq & 0x1f));
+		status |= (1 << (d->hwirq & 0x1f));
 		writel(status, stat_reg);
 	} else {
-		u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+		u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
 
 		dctr &= ~VT8500_INT_ENABLE;
-		writeb(dctr, base + VT8500_IC_DCTR + irq);
+		writeb(dctr, base + VT8500_ICDC + d->hwirq);
 	}
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_ICDC + d->hwirq);
 	dctr |= VT8500_INT_ENABLE;
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_ICDC + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-	void __iomem *base = ic_regbase;
-	unsigned irq = d->irq;
-	unsigned orig_irq = irq;
+	struct vt8500_irq_priv *priv =
+			(struct vt8500_irq_priv *)(d->domain->host_data);
+	void __iomem *base = priv->base;
 	u8 dctr;
 
-	if (irq >= 64) {
-		base = sic_regbase;
-		irq -= 64;
-	}
-
-	dctr = readb(base + VT8500_IC_DCTR + irq);
+	dctr = readb(base + VT8500_ICDC + d->hwirq);
 	dctr &= ~VT8500_EDGE;
 
 	switch (flow_type) {
@@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 		return -EINVAL;
 	case IRQF_TRIGGER_HIGH:
 		dctr |= VT8500_TRIGGER_HIGH;
-		__irq_set_handler_locked(orig_irq, handle_level_irq);
+		__irq_set_handler_locked(d->irq, handle_level_irq);
 		break;
 	case IRQF_TRIGGER_FALLING:
 		dctr |= VT8500_TRIGGER_FALLING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	case IRQF_TRIGGER_RISING:
 		dctr |= VT8500_TRIGGER_RISING;
-		__irq_set_handler_locked(orig_irq, handle_edge_irq);
+		__irq_set_handler_locked(d->irq, handle_edge_irq);
 		break;
 	}
-	writeb(dctr, base + VT8500_IC_DCTR + irq);
+	writeb(dctr, base + VT8500_ICDC + d->hwirq);
 
 	return 0;
 }
@@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = {
 	.irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
 	unsigned int i;
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+	/* Enable rotating priority for IRQ */
+	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
+	writel(0x00, base + VT8500_ICPC_FIQ);
 
-	if (ic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
+	for (i = 0; i < 64; i++) {
+		/* Disable all interrupts and route them to IRQ */
+		writeb(VT8500_INT_DISABLE | ICDC_IRQ,
+						base + VT8500_ICDC + i);
+	}
+}
 
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+							irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
 
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
-		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-	}
+	return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+	.map = vt8500_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-	unsigned int i;
+	struct irq_domain *vt8500_irq_domain;
+	struct vt8500_irq_priv *priv;
+	int irq, i;
+	struct device_node *np = node;
+
+	priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+	priv->base = of_iomap(np, 0);
+
+	vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+				&vt8500_irq_domain_ops, priv);
+	if (!vt8500_irq_domain)
+		pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+
+	irq_set_default_host(vt8500_irq_domain);
+
+	vt8500_init_irq_hw(priv->base);
 
-	ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-	sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-	if (ic_regbase && sic_regbase) {
-		/* Enable rotating priority for IRQ */
-		writel((1 << 6), ic_regbase + 0x20);
-		writel(0, ic_regbase + 0x24);
-		writel((1 << 6), sic_regbase + 0x20);
-		writel(0, sic_regbase + 0x24);
-
-		for (i = 0; i < wmt_nr_irqs; i++) {
-			/* Disable all interrupts and route them to IRQ */
-			if (i < 64)
-				writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-			else
-				writeb(0x00, sic_regbase + VT8500_IC_DCTR
-								+ i - 64);
-
-			irq_set_chip_and_handler(i, &vt8500_irq_chip,
-						 handle_level_irq);
-			set_irq_flags(i, IRQF_VALID);
+	pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+						(u32)(priv->base), irq_cnt);
+
+	/* check if this is a slaved controller */
+	if (of_irq_count(np) != 0) {
+		/* check that we have the correct number of interrupts */
+		if (of_irq_count(np) != 8) {
+			pr_err("%s: Incorrect IRQ map for slave controller\n",
+					__func__);
+			return -EINVAL;
 		}
-	} else {
-		printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
+
+		for (i = 0; i < 8; i++) {
+			irq = irq_of_parse_and_map(np, i);
+			enable_irq(irq);
+		}
+
+		pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
 	}
+
+	irq_cnt += 64;
+
+	return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a..0000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE		0xD8130000
-#define WMT_PRIZM_PMSR_REG	0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-	struct device_node *np;
-
-	/*
-	 * Check if Power Mgmt Controller node is present in device tree. If no
-	 * device tree node, use the legacy PMSR value (valid for all current
-	 * SoCs).
-	 */
-	np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-	if (np) {
-		pmc_base = of_iomap(np, 0);
-
-		if (!pmc_base)
-			pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-		of_node_put(np);
-	} else {
-		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-		if (!pmc_base) {
-			pr_err("%s:ioremap(rstc) failed\n", __func__);
-			return;
-		}
-	}
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-	if (pmc_base)
-		writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c5..050e183 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET	0x0100
+#define VT8500_TIMER_HZ		3000000
 #define TIMER_MATCH_VAL		0x0000
 #define TIMER_COUNT_VAL		0x0010
 #define TIMER_STATUS_VAL	0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE	(1 << 5)	/* not ready for read */
 #define TIMER_COUNT_W_ACTIVE	(1 << 4)	/* not ready for write */
 #define TIMER_MATCH_W_ACTIVE	(1 << 0)	/* not ready for write */
-#define VT8500_TIMER_HZ		3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
 	return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
 	.name           = "vt8500_timer",
 	.rating         = 200,
 	.read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
 	}
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
 	.name           = "vt8500_timer",
 	.features       = CLOCK_EVT_FEAT_ONESHOT,
 	.rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
 	.name    = "vt8500_timer",
 	.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler = vt8500_timer_interrupt,
 	.dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+	{ .compatible = "via,vt8500-timer" },
+	{ }
+};
+
+void __init vt8500_timer_init(void)
 {
-	regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-	if (!regbase)
-		printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+	struct device_node *np;
+	int timer_irq;
+
+	np = of_find_matching_node(NULL, vt8500_timer_ids);
+	if (!np) {
+		pr_err("%s: Timer description missing from Device Tree\n",
+								__func__);
+		return;
+	}
+	regbase = of_iomap(np, 0);
+	if (!regbase) {
+		pr_err("%s: Missing iobase description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
+	timer_irq = irq_of_parse_and_map(np, 0);
+	if (!timer_irq) {
+		pr_err("%s: Missing irq description in Device Tree\n",
+								__func__);
+		of_node_put(np);
+		return;
+	}
 
 	writel(1, regbase + TIMER_CTRL_VAL);
 	writel(0xf, regbase + TIMER_STATUS_VAL);
 	writel(~0, regbase + TIMER_MATCH_VAL);
 
 	if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-		printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
-					clocksource.name);
+		pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
+					__func__, clocksource.name);
 
 	clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
 
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
 	clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
 	clockevent.cpumask = cpumask_of(0);
 
-	if (setup_irq(wmt_timer_irq, &irq))
-		printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
-					clockevent.name);
+	if (setup_irq(timer_irq, &irq))
+		pr_err("%s: setup_irq failed for %s\n", __func__,
+							clockevent.name);
 	clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-	.init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 0000000..4494993
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,196 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+#include <mach/gpio.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE	0xD8110000
+#define LEGACY_PMC_BASE		0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG	0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG		0x12
+#define VT8500_PMSR_REG		0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+	if (pmc_base)
+		writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+	/* SoC MMIO registers */
+	[0] = {
+		.virtual	= 0xf8000000,
+		.pfn		= __phys_to_pfn(0xd8000000),
+		.length		= 0x00390000, /* max of all chip variants */
+		.type		= MT_DEVICE
+	},
+};
+
+void __init vt8500_map_io(void)
+{
+	iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+	local_irq_disable();
+	writew(5, pmc_base + VT8500_HCR_REG);
+	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+	struct device_node *np, *fb;
+	void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+	fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+				gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+#ifdef CONFIG_FB_WM8505
+	fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+	if (fb) {
+		np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+		if (!np)
+			np = of_find_compatible_node(NULL, NULL,
+							"wm,wm8650-gpio");
+		if (np) {
+			gpio_base = of_iomap(np, 0);
+
+			if (!gpio_base)
+				pr_err("%s: of_iomap(gpio_mux) failed\n",
+								__func__);
+
+			of_node_put(np);
+		} else {
+			gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+			if (!gpio_base)
+				pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+								__func__);
+		}
+		if (gpio_base) {
+			writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+				0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+			iounmap(gpio_base);
+		} else
+			pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+		of_node_put(fb);
+	}
+#endif
+
+	np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+	if (np) {
+		pmc_base = of_iomap(np, 0);
+
+		if (!pmc_base)
+			pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+		of_node_put(np);
+	} else {
+		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+		if (!pmc_base)
+			pr_err("%s:ioremap(power_off) failed\n", __func__);
+	}
+	if (pmc_base)
+		pm_power_off = &vt8500_power_off;
+	else
+		pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+	vtwm_clk_init(pmc_base);
+
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+	{ .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+	{ /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+	of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+	.init = vt8500_timer_init,
+};
+
+static const char * const vt8500_dt_compat[] = {
+	"via,vt8500",
+	"wm,wm8650",
+	"wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+	.dt_compat	= vt8500_dt_compat,
+	.map_io		= vt8500_map_io,
+	.init_irq	= vt8500_init_irq,
+	.timer		= &vt8500_timer,
+	.init_machine	= vt8500_init,
+	.restart	= vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index db19886..0000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-	&vt8500_device_uart0,
-	&vt8500_device_ehci,
-	&vt8500_device_wm8505_fb,
-	&vt8500_device_ge_rops,
-	&vt8500_device_pwm,
-	&vt8500_device_pwmbl,
-	&vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-	local_irq_disable();
-	writew(5, pmc_hiber);
-	asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-	void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-	if (gpio_mux_reg) {
-		writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-		iounmap(gpio_mux_reg);
-	} else {
-		printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-	}
-#endif
-	pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-	if (pmc_hiber)
-		pm_power_off = &vt8500_power_off;
-	else
-		printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-	wmt_setup_restart();
-	wm8505_set_resources();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-	.atag_offset	= 0x100,
-	.restart	= wmt_restart,
-	.reserve	= wm8505_reserve_mem,
-	.map_io		= wm8505_map_io,
-	.init_irq	= wm8505_init_irq,
-	.timer		= &vt8500_timer,
-	.init_machine	= wm8505_7in_init,
-MACHINE_END
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:40 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:40 +1200
Subject: [PATCHv4 4/9] usb: vt8500: Add devicetree support for vt8500-ehci and
 -uhci.
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-5-git-send-email-linux@prisktech.co.nz>

Add devicetree support for vt8500-ehci.
Convert vt8500-uhci to a generic non-pci platform-uhci with
device tree support.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 drivers/usb/host/Kconfig         |    4 +-
 drivers/usb/host/ehci-vt8500.c   |   25 ++++--
 drivers/usb/host/uhci-hcd.c      |    5 ++
 drivers/usb/host/uhci-platform.c |  169 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 195 insertions(+), 8 deletions(-)
 create mode 100644 drivers/usb/host/uhci-platform.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index dcfaaa9..d7a6b10 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -450,7 +450,7 @@ config USB_OHCI_LITTLE_ENDIAN
 
 config USB_UHCI_HCD
 	tristate "UHCI HCD (most Intel and VIA) support"
-	depends on USB && (PCI || SPARC_LEON)
+	depends on USB && (PCI || SPARC_LEON || ARCH_VT8500)
 	---help---
 	  The Universal Host Controller Interface is a standard by Intel for
 	  accessing the USB hardware in the PC (which is also called the USB
@@ -468,7 +468,7 @@ config USB_UHCI_HCD
 config USB_UHCI_SUPPORT_NON_PCI_HC
 	bool
 	depends on USB_UHCI_HCD
-	default y if SPARC_LEON
+	default y if (SPARC_LEON  || ARCH_VT8500)
 
 config USB_UHCI_BIG_ENDIAN_MMIO
 	bool
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c
index c1eda73..0e1637b 100644
--- a/drivers/usb/host/ehci-vt8500.c
+++ b/drivers/usb/host/ehci-vt8500.c
@@ -16,6 +16,7 @@
  *
  */
 
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
@@ -84,20 +85,23 @@ static const struct hc_driver vt8500_ehci_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static u64 wmt_ehci_dma_mask = DMA_BIT_MASK(32);
+
 static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
+	int irq;
 	int ret;
 
 	if (usb_disabled())
 		return -ENODEV;
 
-	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
-		pr_debug("resource[1] is not IORESOURCE_IRQ");
-		return -ENOMEM;
-	}
+	/* devicetree created devices don't specify a dma mask */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &wmt_ehci_dma_mask;
+
 	hcd = usb_create_hcd(&vt8500_ehci_hc_driver, &pdev->dev, "VT8500");
 	if (!hcd)
 		return -ENOMEM;
@@ -134,8 +138,9 @@ static int vt8500_ehci_drv_probe(struct platform_device *pdev)
 
 	ehci_reset(ehci);
 
-	ret = usb_add_hcd(hcd, pdev->resource[1].start,
-			  IRQF_SHARED);
+	irq = platform_get_irq(pdev, 0);
+
+	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret == 0) {
 		platform_set_drvdata(pdev, hcd);
 		return ret;
@@ -162,6 +167,11 @@ static int vt8500_ehci_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id vt8500_ehci_ids[] = {
+	{ .compatible = "via,vt8500-ehci", },
+	{}
+};
+
 static struct platform_driver vt8500_ehci_driver = {
 	.probe		= vt8500_ehci_drv_probe,
 	.remove		= vt8500_ehci_drv_remove,
@@ -169,7 +179,10 @@ static struct platform_driver vt8500_ehci_driver = {
 	.driver = {
 		.name	= "vt8500-ehci",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(vt8500_ehci_ids),
 	}
 };
 
 MODULE_ALIAS("platform:vt8500-ehci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index e4db350..5da5c99 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -846,6 +846,11 @@ static const char hcd_name[] = "uhci_hcd";
 #define PLATFORM_DRIVER		uhci_grlib_driver
 #endif
 
+#ifdef CONFIG_ARCH_VT8500
+#include "uhci-platform.c"
+#define PLATFORM_DRIVER		uhci_platform_driver
+#endif
+
 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
 #error "missing bus glue for uhci-hcd"
 #endif
diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
new file mode 100644
index 0000000..35ca094
--- /dev/null
+++ b/drivers/usb/host/uhci-platform.c
@@ -0,0 +1,169 @@
+/*
+ * Generic UHCI HCD (Host Controller Driver) for Platform Devices
+ *
+ * Copyright (c) 2011 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * This file is based on uhci-grlib.c
+ * (C) Copyright 2004-2007 Alan Stern, stern at rowland.harvard.edu
+ */
+
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static int uhci_platform_init(struct usb_hcd *hcd)
+{
+	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+	uhci->rh_numports = uhci_count_ports(hcd);
+
+	/* Set up pointers to to generic functions */
+	uhci->reset_hc = uhci_generic_reset_hc;
+	uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc;
+
+	/* No special actions need to be taken for the functions below */
+	uhci->configure_hc = NULL;
+	uhci->resume_detect_interrupts_are_broken = NULL;
+	uhci->global_suspend_mode_is_broken = NULL;
+
+	/* Reset if the controller isn't already safely quiescent. */
+	check_and_reset_hc(uhci);
+	return 0;
+}
+
+static const struct hc_driver uhci_platform_hc_driver = {
+	.description =          hcd_name,
+	.product_desc =         "Generic UHCI Host Controller",
+	.hcd_priv_size =        sizeof(struct uhci_hcd),
+
+	/* Generic hardware linkage */
+	.irq =                  uhci_irq,
+	.flags =                HCD_MEMORY | HCD_USB11,
+
+	/* Basic lifecycle operations */
+	.reset =                uhci_platform_init,
+	.start =                uhci_start,
+#ifdef CONFIG_PM
+	.pci_suspend =          NULL,
+	.pci_resume =           NULL,
+	.bus_suspend =          uhci_rh_suspend,
+	.bus_resume =           uhci_rh_resume,
+#endif
+	.stop =                 uhci_stop,
+
+	.urb_enqueue =          uhci_urb_enqueue,
+	.urb_dequeue =          uhci_urb_dequeue,
+
+	.endpoint_disable =     uhci_hcd_endpoint_disable,
+	.get_frame_number =     uhci_hcd_get_frame_number,
+
+	.hub_status_data =      uhci_hub_status_data,
+	.hub_control =          uhci_hub_control,
+};
+
+static u64 platform_uhci_dma_mask = DMA_BIT_MASK(32);
+
+static int __devinit uhci_hcd_platform_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd;
+	struct uhci_hcd *uhci;
+	struct resource *res;
+	int ret;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &platform_uhci_dma_mask;
+
+	hcd = usb_create_hcd(&uhci_platform_hc_driver, &pdev->dev,
+				pdev->name);
+	if (!hcd)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	hcd->rsrc_start = res->start;
+	hcd->rsrc_len = resource_size(res);
+
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		pr_err("%s: request_mem_region failed\n", __func__);
+		ret = -EBUSY;
+		goto err_rmr;
+	}
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		pr_err("%s: ioremap failed\n", __func__);
+		ret = -ENOMEM;
+		goto err_irq;
+	}
+	uhci = hcd_to_uhci(hcd);
+
+	uhci->regs = hcd->regs;
+
+	ret = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED |
+								IRQF_SHARED);
+	if (ret)
+		goto err_uhci;
+
+	return 0;
+
+err_uhci:
+	iounmap(hcd->regs);
+err_irq:
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+	usb_put_hcd(hcd);
+
+	return ret;
+}
+
+static int uhci_hcd_platform_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more.  This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel.  Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_hcd_platform_shutdown(struct platform_device *op)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+	uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+static const struct of_device_id platform_uhci_ids[] = {
+	{ .compatible = "platform-uhci", },
+	{}
+};
+
+static struct platform_driver uhci_platform_driver = {
+	.probe          = uhci_hcd_platform_probe,
+	.remove         = uhci_hcd_platform_remove,
+	.shutdown       = uhci_hcd_platform_shutdown,
+	.driver = {
+		.name = "platform-uhci",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(platform_uhci_ids),
+	},
+};
+
+MODULE_ALIAS("platform:platform-uhci");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, platform_uhci_ids);
-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:36 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:36 +1200
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
Message-ID: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>

This patchset updates arch-vt8500 to devicetree and removes all the old-style
code. Support for WM8650 has also been added.

Example dts/dtsi files are given for the three currently supported models.

Major changes:

GPIO code has been converted to a platform_device and rewritten as WM8505
support was broken. Add support for WM8650 gpio controller.

UHCI support was missing. Added this as a generic non-pci uhci controller as
it doesn't require anything special. Should be usable by any system that doesn't
have special requirements to get the UHCI controller working.

Framebuffer code patched to support WM8650. The bindings for this are of concern
but there doesn't seem to be a formalized binding yet. This patch is based off
Sascha Hauer's current patch on the dri-devel mailing list and should be easily
patched out when its finalized.

Patchset based on Arnd's arm-soc/for-next branch.


Could I get this reviewed, hopefully for inclusion into v3.7.

Regards
Tony Prisk

Changes
v2:
Cleanup style/formatting errors
Removed erroneous commit message about GPIO not being converted to devicetree
Corrected arch-vt8500/irq.c header to correct filename
Changed GPIO driver to use module_platform_driver()
Renamed vt8500_gpio_bank_regs -> vt8500_gpio_bank_regoffsets
Changed vt8500_gpio_bank_regoffset fields to unsigned int
Changed bit-setting code to use BIT() macro
Removed of_find_compatible() and use pdev->dev.of_node in _probe()
Removed regoff field and related code - leftover from old design
Added kerneldoc regarding struct vt8500_gpio_bank_regoffsets fields
Update MODULE_LICENSE on all platform devices to "GPL v2" to match their headers
Renamed dts board files to clarify product names

v3:
Corrected serial driver issue after porting to device tree. pdev->id no longer
valid.
Corrected irq.c to properly initialize slaved interrupt controller.
Updated framebuffer drivers to use phandles for display node.
Corrected dts definitions for updated framebuffer driver.

EHCI/UHCI patch (Patch 4/9) already in -next via usb-next tree.

Included common clock frame support.
Added initialization code to arch/arm/mach-vt8500/vt8500.c for clocks.
Updated wm8650.dtsi to include basic clocks.

v4:
Added missing GPL header to clk-vt8500.c
Corrected unsigned variables in gpio-vt8500.c
Changed gpio-vt8500.c to use readl/writel _relaxed variants.
Update serial driver to get clock source from device tree.
Update dtsi files for uart clock sources.
Renamed vt8500_gpio.txt to vt8500-gpio.txt
Describe gpio flags property - currently no flags are defined, but will need
to be when gpio interrupts are supported. Kept for future compatibility.

Stephen W: I've taken a look on dri-devel mailing list and -next but haven't
seen a new binding document for Sascha's of_videomode_helper yet. I've left the
code as is for now - hopefully the OF helper will be formalized in this cycle.
I took a look at the GPIO flags - this was added on Arnd's recommendation as it
will be needed later once the GPIO controller is also an interrupt-controller.
I've add documentation that it should be =0 for now.


Tony Prisk (9):
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  rtc: vt8500: Add devicetree support for vt8500-rtc
  serial: vt8500: Add devicetree support for vt8500-serial
  usb: vt8500: Add devicetree support for vt8500-ehci and -uhci.
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  arm: vt8500: gpio: Devicetree support for arch-vt8500
  arm: vt8500: clk: Add Common Clock Framework support

 Documentation/devicetree/bindings/arm/vt8500.txt   |   15 +
 .../bindings/arm/vt8500/via,vt8500-intc.txt        |   16 +
 .../bindings/arm/vt8500/via,vt8500-pmc.txt         |   13 +
 .../bindings/arm/vt8500/via,vt8500-timer.txt       |   15 +
 Documentation/devicetree/bindings/clock/vt8500.txt |   72 +++
 .../devicetree/bindings/gpio/gpio-vt8500.txt       |   24 +
 .../devicetree/bindings/rtc/via,vt8500-rtc.txt     |   15 +
 .../bindings/tty/serial/via,vt8500-uart.txt        |   17 +
 .../devicetree/bindings/usb/platform-uhci.txt      |   15 +
 .../devicetree/bindings/usb/via,vt8500-ehci.txt    |   15 +
 .../devicetree/bindings/vendor-prefixes.txt        |    2 +
 .../devicetree/bindings/video/via,vt8500-fb.txt    |   48 ++
 .../devicetree/bindings/video/wm,prizm-ge-rops.txt |   13 +
 .../devicetree/bindings/video/wm,wm8505-fb.txt     |   22 +
 arch/arm/Kconfig                                   |    5 +
 arch/arm/boot/dts/vt8500-bv07.dts                  |   31 ++
 arch/arm/boot/dts/vt8500.dtsi                      |  115 +++++
 arch/arm/boot/dts/wm8505-ref.dts                   |   31 ++
 arch/arm/boot/dts/wm8505.dtsi                      |  142 ++++++
 arch/arm/boot/dts/wm8650-mid.dts                   |   31 ++
 arch/arm/boot/dts/wm8650.dtsi                      |  146 ++++++
 arch/arm/mach-vt8500/Kconfig                       |   72 +--
 arch/arm/mach-vt8500/Makefile                      |    9 +-
 arch/arm/mach-vt8500/bv07.c                        |   80 ---
 arch/arm/mach-vt8500/common.h                      |   28 ++
 arch/arm/mach-vt8500/devices-vt8500.c              |   91 ----
 arch/arm/mach-vt8500/devices-wm8505.c              |   99 ----
 arch/arm/mach-vt8500/devices.c                     |  270 -----------
 arch/arm/mach-vt8500/devices.h                     |   88 ----
 arch/arm/mach-vt8500/gpio.c                        |  240 ---------
 arch/arm/mach-vt8500/include/mach/restart.h        |    4 +-
 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h    |   88 ----
 arch/arm/mach-vt8500/include/mach/vt8500_regs.h    |   79 ---
 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h    |  115 -----
 arch/arm/mach-vt8500/include/mach/wm8505_regs.h    |   78 ---
 arch/arm/mach-vt8500/irq.c                         |  209 ++++----
 arch/arm/mach-vt8500/restart.c                     |   54 ---
 arch/arm/mach-vt8500/timer.c                       |   67 ++-
 arch/arm/mach-vt8500/vt8500.c                      |  196 ++++++++
 arch/arm/mach-vt8500/wm8505_7in.c                  |   79 ---
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-vt8500.c                           |  511 ++++++++++++++++++++
 drivers/gpio/Kconfig                               |    6 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-vt8500.c                         |  316 ++++++++++++
 drivers/rtc/rtc-vt8500.c                           |    9 +-
 drivers/tty/serial/vt8500_serial.c                 |   58 ++-
 drivers/usb/host/Kconfig                           |    4 +-
 drivers/usb/host/ehci-vt8500.c                     |   25 +-
 drivers/usb/host/uhci-hcd.c                        |    5 +
 drivers/usb/host/uhci-platform.c                   |  169 +++++++
 drivers/video/Kconfig                              |    6 +-
 drivers/video/vt8500lcdfb.c                        |   79 ++-
 drivers/video/wm8505fb.c                           |   97 +++-
 drivers/video/wmt_ge_rops.c                        |    9 +-
 55 files changed, 2463 insertions(+), 1582 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
 create mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
 create mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
 create mode 100644 Documentation/devicetree/bindings/video/via,vt8500-fb.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
 create mode 100644 Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
 create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505-ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650-mid.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi
 delete mode 100644 arch/arm/mach-vt8500/bv07.c
 create mode 100644 arch/arm/mach-vt8500/common.h
 delete mode 100644 arch/arm/mach-vt8500/devices-vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/devices-wm8505.c
 delete mode 100644 arch/arm/mach-vt8500/devices.c
 delete mode 100644 arch/arm/mach-vt8500/devices.h
 delete mode 100644 arch/arm/mach-vt8500/gpio.c
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/vt8500_regs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/wm8505_regs.h
 delete mode 100644 arch/arm/mach-vt8500/restart.c
 create mode 100644 arch/arm/mach-vt8500/vt8500.c
 delete mode 100644 arch/arm/mach-vt8500/wm8505_7in.c
 create mode 100644 drivers/clk/clk-vt8500.c
 create mode 100644 drivers/gpio/gpio-vt8500.c
 create mode 100644 drivers/usb/host/uhci-platform.c

-- 
1.7.9.5



From linux at prisktech.co.nz  Thu Aug 23 03:35:37 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 19:35:37 +1200
Subject: [PATCHv4 1/9] arm: vt8500: Add device tree files for VIA/Wondermedia
 SoC's
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <1345707346-9035-2-git-send-email-linux@prisktech.co.nz>

Add device tree files for VT8500, WM8505 and WM8650 SoC's and
reference boards.

Signed-off-by: Tony Prisk <linux at prisktech.co.nz>
---
 arch/arm/boot/dts/vt8500-bv07.dts |   31 ++++++++
 arch/arm/boot/dts/vt8500.dtsi     |  115 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8505-ref.dts  |   31 ++++++++
 arch/arm/boot/dts/wm8505.dtsi     |  142 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/wm8650-mid.dts  |   31 ++++++++
 arch/arm/boot/dts/wm8650.dtsi     |  146 +++++++++++++++++++++++++++++++++++++
 6 files changed, 496 insertions(+)
 create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts
 create mode 100644 arch/arm/boot/dts/vt8500.dtsi
 create mode 100644 arch/arm/boot/dts/wm8505-ref.dts
 create mode 100644 arch/arm/boot/dts/wm8505.dtsi
 create mode 100644 arch/arm/boot/dts/wm8650-mid.dts
 create mode 100644 arch/arm/boot/dts/wm8650.dtsi

diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 0000000..339a664
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,31 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+	model = "Benign BV07 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 0000000..17a1d0d
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,115 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "via,vt8500";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc>;
+
+		intc: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "via,vt8500-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ref24: ref24M {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <24000000>;
+				};
+			};
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d800e400 {
+			compatible = "via,vt8500-fb";
+			reg = <0xd800e400 0x400>;
+			interrupts = <12>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+			clocks = <&ref24>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+			clocks = <&ref24>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+			clocks = <&ref24>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+			clocks = <&ref24>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 0000000..fcd9836
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+	model = "Wondermedia WM8505 Netbook";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <32>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 0000000..aa6d492
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,142 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8505";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8505-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ref24: ref24M {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <24000000>;
+				};
+			};
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007100 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007100 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007300 {
+			compatible = "platform-uhci";
+			reg = <0xd8007300 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+			clocks = <&ref24>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+			clocks = <&ref24>;
+		};
+
+		uart at d8210000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8210000 0x1040>;
+			interrupts = <47>;
+			clocks = <&ref24>;
+		};
+
+		uart at d82c0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82c0000 0x1040>;
+			interrupts = <50>;
+			clocks = <&ref24>;
+		};
+
+		uart at d8370000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8370000 0x1040>;
+			interrupts = <31>;
+			clocks = <&ref24>;
+		};
+
+		uart at d8380000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8380000 0x1040>;
+			interrupts = <30>;
+			clocks = <&ref24>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 0000000..d37dbf0
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,31 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+	model = "Wondermedia WM8650-MID Tablet";
+
+	/*
+	 * Display node is based on Sascha Hauer's patch on dri-devel.
+	 * Added a bpp property to calculate the size of the framebuffer
+	 * until the binding is formalized.
+	 */
+	display: display {
+		xres = <800>;
+		yres = <480>;
+		left-margin = <88>;
+		right-margin = <40>;
+		hsync-len = <0>;
+		upper-margin = <32>;
+		lower-margin = <11>;
+		vsync-len = <1>;
+		bpp = <16>;
+	};
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 0000000..372a734
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,146 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux at prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "wm,wm8650";
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc0>;
+
+		intc0: interrupt-controller at d8140000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			reg = <0xd8140000 0x10000>;
+			#interrupt-cells = <1>;
+		};
+
+		/* Secondary IC cascaded to intc0 */
+		intc1: interrupt-controller at d8150000 {
+			compatible = "via,vt8500-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0xD8150000 0x10000>;
+			interrupts = <56 57 58 59 60 61 62 63>;
+		};
+
+		gpio: gpio-controller at d8110000 {
+			compatible = "wm,wm8650-gpio";
+			gpio-controller;
+			reg = <0xd8110000 0x10000>;
+			#gpio-cells = <3>;
+		};
+
+		pmc at d8130000 {
+			compatible = "via,vt8500-pmc";
+			reg = <0xd8130000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ref25: ref25M {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <25000000>;
+				};
+
+				ref24: ref24M {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <24000000>;
+				};
+
+				plla: plla {
+					#clock-cells = <0>;
+					compatible = "wm,wm8650-pll-clock";
+					clocks = <&ref25>;
+					reg = <0x200>;
+				};
+
+				pllb: pllb {
+					#clock-cells = <0>;
+					compatible = "wm,wm8650-pll-clock";
+					clocks = <&ref25>;
+					reg = <0x204>;
+				};
+
+				arm: arm {
+					#clock-cells = <0>;
+					compatible = "via,vt8500-device-clock";
+					clocks = <&plla>;
+					divisor-reg = <0x300>;
+				};
+
+				sdhc: sdhc {
+					#clock-cells = <0>;
+					compatible = "via,vt8500-device-clock";
+					clocks = <&pllb>;
+					divisor-reg = <0x328>;
+					divisor-mask = <0x3f>;
+					enable-reg = <0x254>;
+					enable-bit = <18>;
+				};
+			};
+		};
+
+		timer at d8130100 {
+			compatible = "via,vt8500-timer";
+			reg = <0xd8130100 0x28>;
+			interrupts = <36>;
+		};
+
+		ehci at d8007900 {
+			compatible = "via,vt8500-ehci";
+			reg = <0xd8007900 0x200>;
+			interrupts = <43>;
+		};
+
+		uhci at d8007b00 {
+			compatible = "platform-uhci";
+			reg = <0xd8007b00 0x200>;
+			interrupts = <43>;
+		};
+
+		fb at d8050800 {
+			compatible = "wm,wm8505-fb";
+			reg = <0xd8050800 0x200>;
+			via,display = <&display>;
+		};
+
+		ge_rops at d8050400 {
+			compatible = "wm,prizm-ge-rops";
+			reg = <0xd8050400 0x100>;
+		};
+
+		uart at d8200000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd8200000 0x1040>;
+			interrupts = <32>;
+			clocks = <&ref24>;
+		};
+
+		uart at d82b0000 {
+			compatible = "via,vt8500-uart";
+			reg = <0xd82b0000 0x1040>;
+			interrupts = <33>;
+			clocks = <&ref24>;
+		};
+
+		rtc at d8100000 {
+			compatible = "via,vt8500-rtc";
+			reg = <0xd8100000 0x10000>;
+			interrupts = <48>;
+		};
+	};
+};
-- 
1.7.9.5



From artem.bityutskiy at linux.intel.com  Thu Aug 23 03:41:29 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Thu, 23 Aug 2012 10:41:29 +0300
Subject: JFFS2 issue with v3.5.x and later on Atmel chips at least (was:
 Kernel oops since v3.5.x on Atmel chips)
In-Reply-To: <5034F3F8.9080802@atmel.com>
References: <5034B45A.5060107@atmel.com> <5034F3F8.9080802@atmel.com>
Message-ID: <1345707689.2848.203.camel@sauron.fi.intel.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date: Thu, 23 Aug 2012 10:10:07 +0300
Subject: [PATCH] JFFS2: fix unmount regression

This patch fixes regression introduced by
"8bdc81c jffs2: get rid of jffs2_sync_super". We submit a delayed work in order
to make sure the write-buffer is synchronized at some point. But we do not
flush it when we unmount, which causes an oops when we unmount the file-system
and then the delayed work is executed.

This patch fixes the issue by adding a "cancel_delayed_work_sync()" infocation
in the '->sync_fs()' handler. This will make sure the delayed work is canceled
on sync, unmount and re-mount. And because VFS always callse 'sync_fs()' before
unmounting or remounting, this fixes the issue.

Reported-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: stable at vger.kernel.org [3.5+]
Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---

Ludovic, would you please give this patch a test? Also attached.

 fs/jffs2/super.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/fs/jffs2/super.c b/fs/jffs2/super.c
index 61ea413..e385fa3 100644
--- a/fs/jffs2/super.c
+++ b/fs/jffs2/super.c
@@ -100,6 +100,9 @@ static int jffs2_sync_fs(struct super_block *sb, int wait)
 {
 	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
 
+	if (IS_ENABLED(CONFIG_JFFS2_FS_WRITEBUFFER))
+		cancel_delayed_work_sync(&c->wbuf_dwork);
+
 	mutex_lock(&c->alloc_sem);
 	jffs2_flush_wbuf_pad(c);
 	mutex_unlock(&c->alloc_sem);
-- 
1.7.10.4
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From arnd at arndb.de  Thu Aug 23 02:46:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 06:46:30 +0000
Subject: PER_LINUX32,
 Was: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <20120816102808.GH31784@mudshark.cambridge.arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
 <20120816102808.GH31784@mudshark.cambridge.arm.com>
Message-ID: <201208230646.31276.arnd@arndb.de>

On Thursday 16 August 2012, Will Deacon wrote:
> On Wed, Aug 15, 2012 at 03:34:04PM +0100, Arnd Bergmann wrote:
> > On Tuesday 14 August 2012, Catalin Marinas wrote:
> > > +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> > > +{
> > > +	int ret;
> > > +
> > > +	if (personality(current->personality) == PER_LINUX32 &&
> > > +		personality == PER_LINUX)
> > > +		personality = PER_LINUX32;
> > > +	ret = sys_personality(personality);
> > > +	if (ret == PER_LINUX32)
> > > +		ret = PER_LINUX;
> > > +	return ret;
> > > +}
> > 
> > Where did you get this from?
> > 
> > You should not need compat_sys_personality, just call the native function.
> 
> Hmm, but in that case an aarch32 application doing a personality(PER_LINUX)
> syscall will start seeing the wrong uname.

Coming back at this topic, I noticed another issue. Jiri Kosina
has recently posted patches to fix this function in the other architectures
in order to mask out the other personality bits, which is a correct fix,
but the above function is odd for other reasons.

* On MIPS, it is used only for compat tasks, like you have it above.
* On PA-RISC, it is used for native 32 bit tasks and for compat 32 bit tasks,
  but not for native 64 bit ones.
* On IA64, it was used for compat tasks (support for which has since
  been removed from the kernel), plus all 32 bit tasks would start with
  PER_LINUX32.
* On PowerPC, Sparc and s390, it is used for native 64 bit tasks and for
  compat 32 bit tasks, but not for native 32 bit ones.
* On Tile, it was never used.
* On x86_64, it used to be defined (copied from ia64) but not used
  throughout the git history.

The semantics of the function are also interesting: The intention seems
to be that to a compat task, PER_LINUX32 would appear as PER_LINUX.
The effect is that any process can set PER_LINUX32 but it can never
be unset except by a 64 bit MIPS or PA-RISC task.

Since x86_64 does not implement this behavior at all, I suspect that
there are now lots of things depending on not having it, while all
the other architectures might also have some (even predating the
x86_64 port) use cases that depend on depend on not being able to
observe PER_LINUX32 in 32 bit compat tasks.

I think we should try to agree on how this is all supposed to work
and use common code, either put the ppc/sparc/s390 version into
sys_personality, or remove all of them and just do what x86 and tile
do, using the regular sys_personality for all tasks.

	Arnd


From b29396 at freescale.com  Thu Aug 23 03:26:30 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 23 Aug 2012 15:26:30 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <20120822160241.GR7995@opensource.wolfsonmicro.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822160241.GR7995@opensource.wolfsonmicro.com>
Message-ID: <20120823072629.GG10057@shlinux2.ap.freescale.net>

On Thu, Aug 23, 2012 at 12:02:41AM +0800, Mark Brown wrote:
> On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> 
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> > Add regmap based imx syscon driver.
> 
> Nice to see more regmap-mmio usage!
> 
> Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
> from a regmap point of view.
> 
Thanks

> > +int imx_syscon_write(struct device_node *np, u32 reg, u32 val)
> > +{
> > +	struct device *dev;
> > +	struct imx_syscon *syscon;
> > +	int ret = 0;
> > +
> > +	dev = driver_find_device(&imx_syscon_driver.driver, NULL, np,
> > +				 imx_syscon_match);
> > +	if (!dev)
> > +		return -EPROBE_DEFER;
> > +
> > +	syscon = dev_get_drvdata(dev);
> > +	ret = regmap_write(syscon->regmap, reg, val);
> 
> It'd be good to provide a way of retrieving the regmap so that drivers
> for subsystems with generic regmap code could use the framework features
> (regulator is one example that I just mentioned in my other mail).

Do you mean something like:
regmap = syscon_regmap_dev_lookup(np, "fsl,anatop");
regmap_write(regmap, reg, val);

Then drivers can use generic regmap framework features rather than depend
on what imx-syscon implemented, is that correct?

Regards
Dong Aisheng



From b29396 at freescale.com  Thu Aug 23 03:32:04 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 23 Aug 2012 15:32:04 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <5035BDBF.9020602@wwwdotorg.org>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <5035BDBF.9020602@wwwdotorg.org>
Message-ID: <20120823073203.GH10057@shlinux2.ap.freescale.net>

On Thu, Aug 23, 2012 at 01:21:03PM +0800, Stephen Warren wrote:
> On 08/22/2012 01:18 AM, Dong Aisheng wrote:
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> > diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> 
> > @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
> >  	rdesc->ops = &anatop_rops;
> >  	rdesc->type = REGULATOR_VOLTAGE;
> >  	rdesc->owner = THIS_MODULE;
> > -	sreg->mfd = anatopmfd;
> > +
> > +	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
> > +	if (!sreg->anatop)
> > +		return -ENODEV;
> 
> In fact, that imx_syscon_lookup function I proposed could even do the
> of_parse_phandle() internally, so perhaps:
> 
> foo->syscon_dev = imx_syscon_lookup(np, "fsl,anatop", 0);
> if (IS_ERR(foo->syscon_dev))
>     return PTR_ERR(foo->syscon_dev);
> 
> with imx_syscon_lookup() internally knowing when to return EPROBE_DEFER
> rather than any other permanent error code (e.g. for missing property,
> bad phandle, etc.)
> 
This also looks reasonable to me.
btw, see my last reply to mark in another mail.
I'm not sure but Mark may want something slightly different as this one,
imx_syscon_lookup directly return regmap rather than dev, then we do not
need implement any register read/write API in imx-syscon driver, just
using the exist regmap r/w API is ok.

Regards
Dong Aisheng



From m.szyprowski at samsung.com  Thu Aug 23 03:52:07 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 23 Aug 2012 09:52:07 +0200
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <20120823091519.804aeae4ba93bcfe011e787c@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
 <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
 <20120822.163648.3800987367886904.hdoyu@nvidia.com>
 <012401cd80f4$59727020$0c575060$%szyprowski@samsung.com>
 <20120823091519.804aeae4ba93bcfe011e787c@nvidia.com>
Message-ID: <014501cd8104$35a8ce40$a0fa6ac0$%szyprowski@samsung.com>

Hi Hiroshi,

On Thursday, August 23, 2012 8:15 AM Hiroshi Doyu wrote:

> On Thu, 23 Aug 2012 07:58:34 +0200
> Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> 
> > Hello,
> >
> > On Wednesday, August 22, 2012 3:37 PM Hiroshi Doyu wrote:
> >
> > > KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00 +0200:
> > >
> > > > vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic context.
> > >
> > > Right.
> > >
> > > I've been thinking that kzalloc() may be enough here, since
> > > vzalloc() was introduced to avoid allocation failure for big chunk of
> > > memory, but I think that it's unlikely that the number of page array
> > > can be so big. So I propose to drop vzalloc() here, and just simply to
> > > use kzalloc only as below(*1).
> >
> > We already had a discussion about this, so I don't think it makes much sense to
> > change it back to kzalloc. This vmalloc() call won't hurt anyone. It should not
> > be considered a problem for atomic allocations, because no sane driver will try
> > to allocate buffers larger than a dozen KiB with GFP_ATOMIC flag. I would call
> > such try a serious bug, which we should not care here.
> 
> Ok, I've already sent v2 just now, where, instead of changing it back,
> just with GFP_ATOMIC, kzalloc() would be selected, just in case. I guess
> that this would be ok(a bit safer?)

I've posted some comments to v2. If you agree with my suggestion, no changes around
those vmalloc() calls will be needed.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From gururaja.hebbar at ti.com  Thu Aug 23 03:56:44 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Thu, 23 Aug 2012 07:56:44 +0000
Subject: [PATCH 2/5] ASoC: Davinci: McASP: add device tree support for
 McASP
In-Reply-To: <20120817224131.GJ18871@opensource.wolfsonmicro.com>
References: <1344948125-5649-1-git-send-email-gururaja.hebbar@ti.com>
 <1344948125-5649-3-git-send-email-gururaja.hebbar@ti.com>
 <20120817224131.GJ18871@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA68834@DBDE01.ent.ti.com>

On Sat, Aug 18, 2012 at 04:11:32, Mark Brown wrote:
> On Tue, Aug 14, 2012 at 06:12:02PM +0530, Hebbar, Gururaja wrote:
> 
> > +- op-mode : I2S/DIT ops mode.
> 
> This would normally be part of the machine binding since it needs to be
> applied to both ends of the link.

But in case of McASP driver, it is used when calling snd_soc_register_dai()
To pick the proper dai depending on the McASP operation mode.


> When adding it could you come up with
> a generic binding for this in terms of the current ASoC DAI paremeters
> please?  That way we'll be able to have other machine drivers be
> consistent with this one.

Will look into this once I complete the initial DT porting.

> 
> > +- tdm-slots : Slots for TDM operation.
> 
> This would normally also be a machine driver thing though it's less
> normal to need to configure this on both ends.
> 

This parameter is used by McASP hardware controller for managing slots and
Isn't related to any machine modules.

Regards, 
Gururaja


From peter.ujfalusi at ti.com  Thu Aug 23 04:12:46 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 11:12:46 +0300
Subject: [PATCH v3 5/9] ARM/ASoC: omap-mcbsp: Remove CLKR/FSR mux
 configuration code
In-Reply-To: <20120822191506.GL7995@opensource.wolfsonmicro.com>
References: <1345124468-8876-1-git-send-email-peter.ujfalusi@ti.com>
 <1345124468-8876-6-git-send-email-peter.ujfalusi@ti.com>
 <20120822191506.GL7995@opensource.wolfsonmicro.com>
Message-ID: <5035E5FE.90401@ti.com>

Hi Mark,

On 08/22/2012 10:15 PM, Mark Brown wrote:
> Applied but this didn't quite apply cleanly, please check that it did so.

The part which removes the omap_mcbsp_6pin_src_mux() function from
sound/soc/omap/mcbsp.c is the one which did not made it.

It failed to apply on top of topic/omap is that the branch does not have the
following commit:
d0db84e ASoC: omap-mcbsp: Fix 6pin mux configuration

This patch is in your for-next branch. I can not find it in the for-3.6 or
for-3.7 branch either.

Commit d0db84e was planed to be part of 3.6 AFAIK. Without that patch in
topic/omap we are going to have merge issue with 3.7.

I can send a patch which removes the omap_mcbsp_6pin_src_mux() in topic/omap
but the patch will similarly fail when we going to have d0db84e already
applied mainline.

-- 
P?ter


From stigge at antcom.de  Thu Aug 23 04:18:39 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 10:18:39 +0200
Subject: [PATCH 1/2] usb: change the dependency chain for LPC32XX and
 ISP1301
In-Reply-To: <5035D9E0.1000905@linutronix.de>
References: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
 <50355A2C.9010505@antcom.de> <5035D9E0.1000905@linutronix.de>
Message-ID: <5035E75F.5080801@antcom.de>

On 08/23/2012 09:21 AM, Sebastian Andrzej Siewior wrote:
> On 08/23/2012 12:16 AM, Roland Stigge wrote:
>> This issue could be resolved in a different way: Have you followed the
>> discussion at linux-arm-kernel at lists.infradead.org on 2012-08-20,
>> Subject "i2c: pnx: Fix bit definitions"? If nothing unexpected turns
>> out, PNX4008 should probably be removed altogether. (Practically
>> abandoned arch for 6 years.) Easily possible for v3.7.
> 
> Ach. I assumed that is being merged. The PNX arch does not define
> USB_ARCH_HAS_OHCI so I goes that you can't select it there?

Yes, this issue will be gone also.

>> Then, the resulting solution is much simpler and Sebastian's patch
>> obsolete.
> 
> That would be what?

Well, your idea won't be obsolete completely. :-) But much simpler
without all the "PNX4008 || LPC32XX" stuff. Following Alan's proposal,
I'd prefer not introducing new symbols, and much of the "PNX4008 ||
LPC32XX" logic won't be necessary anymore.

For the PNX4008 removal - should I already post a patch to build the
respective changes on top of, without PNX4008 references?

Thanks,

Roland


From bigeasy at linutronix.de  Thu Aug 23 04:29:04 2012
From: bigeasy at linutronix.de (Sebastian Andrzej Siewior)
Date: Thu, 23 Aug 2012 10:29:04 +0200
Subject: [PATCH 1/2] usb: change the dependency chain for LPC32XX and
 ISP1301
In-Reply-To: <5035E75F.5080801@antcom.de>
References: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
 <50355A2C.9010505@antcom.de> <5035D9E0.1000905@linutronix.de>
 <5035E75F.5080801@antcom.de>
Message-ID: <5035E9D0.9020107@linutronix.de>

On 08/23/2012 10:18 AM, Roland Stigge wrote:
> On 08/23/2012 09:21 AM, Sebastian Andrzej Siewior wrote:
>> On 08/23/2012 12:16 AM, Roland Stigge wrote:
>>> This issue could be resolved in a different way: Have you followed the
>>> discussion at linux-arm-kernel at lists.infradead.org on 2012-08-20,
>>> Subject "i2c: pnx: Fix bit definitions"? If nothing unexpected turns
>>> out, PNX4008 should probably be removed altogether. (Practically
>>> abandoned arch for 6 years.) Easily possible for v3.7.
>>
>> Ach. I assumed that is being merged. The PNX arch does not define
>> USB_ARCH_HAS_OHCI so I goes that you can't select it there?
>
> Yes, this issue will be gone also.
>
>>> Then, the resulting solution is much simpler and Sebastian's patch
>>> obsolete.
>>
>> That would be what?
>
> Well, your idea won't be obsolete completely. :-) But much simpler
> without all the "PNX4008 || LPC32XX" stuff. Following Alan's proposal,
> I'd prefer not introducing new symbols, and much of the "PNX4008 ||
> LPC32XX" logic won't be necessary anymore.
>
> For the PNX4008 removal - should I already post a patch to build the
> respective changes on top of, without PNX4008 references?

If nobody cares about PNX4008 and nobody tested if it actually works in
the OHCI mode I don't see the point in keeping it around especially if
there are rumors to remove the arch.

It would be nice, if you could manage to compile this thingy without
I2C. In the end one could attach something different than isp1301, no?
So I think, in the perfect world you would probe for your phy and
notice that it is not there and print a message: "Dude! Select isp1301
for OHCI, aight?!"

>
> Thanks,
>
> Roland

Sebastian


From maxime.ripard at free-electrons.com  Thu Aug 23 04:42:27 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 Aug 2012 10:42:27 +0200
Subject: [PATCHv3 0/4] 
Message-ID: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>

Hi everyone,

This patchset adds support for the solomon SSD1307 OLED controller present
in the CFA-10036 board.

It first adds the framebuffer driver for this controller, and then the
needed bits to enable it in the cfa10036 dts.

Thanks,
Maxime

Changes from v2:
  * Add the pin name as comment to the pwm4 pinctrl declaration
  * Change slightly the documentation of the dt bindings for the gpios to remove
    the mxs-specific cell.

Changes from v1:
  * Did some factorisation of the ssd1307fb_write* functions.
  * Filled the smem_start field of the fb_fix_screeninfo structure
  * Fixed the broken pwm declaration
  * Change the names of oled-reset-gpios and reset-active-low properties in the
    device tree to oled-reset-gpio and oled-reset-active-low for consistency

Maxime Ripard (4):
  video: Add support for the Solomon SSD1307 OLED Controller
  ARM: dts: mxs: Add alternative I2C muxing options for imx28
  ARM: dts: mxs: Add pwm4 muxing options for imx28
  ARM: dts: mxs: add oled support for the cfa-10036

 .../devicetree/bindings/video/ssd1307fb.txt        |   24 ++
 arch/arm/boot/dts/imx28-cfa10036.dts               |   20 +
 arch/arm/boot/dts/imx28.dtsi                       |   21 ++
 drivers/video/Kconfig                              |   13 +
 drivers/video/Makefile                             |    1 +
 drivers/video/ssd1307fb.c                          |  386 ++++++++++++++++++++
 6 files changed, 465 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/ssd1307fb.txt
 create mode 100644 drivers/video/ssd1307fb.c

-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Thu Aug 23 04:42:29 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 Aug 2012 10:42:29 +0200
Subject: [PATCH 2/4] ARM: dts: mxs: Add alternative I2C muxing options for
 imx28
In-Reply-To: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1345711351-16367-3-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Brian Lilly <brian at crystalfontz.com>
---
 arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 787efac..f6ffcd9 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -410,6 +410,17 @@
 					fsl,pull-up = <1>;
 				};
 
+				i2c0_pins_b: i2c0 at 1 {
+					reg = <1>;
+					fsl,pinmux-ids = <
+						0x3001 /* MX28_PAD_AUART0_RX__DUART_CTS */
+						0x3011 /* MX28_PAD_AUART0_TX__DUART_RTS */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
 				saif0_pins_a: saif0 at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Thu Aug 23 04:42:28 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 Aug 2012 10:42:28 +0200
Subject: [PATCH 1/4] video: Add support for the Solomon SSD1307 OLED Controller
In-Reply-To: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1345711351-16367-2-git-send-email-maxime.ripard@free-electrons.com>

This patch adds support for the Solomon SSD1307 OLED
controller found on the Crystalfontz CFA10036 board.

This controller can drive a display with a resolution up
to 128x39 and can operate over I2C or SPI.

The current driver has only been tested on the CFA-10036,
that is using this controller over I2C to driver a 96x16
OLED screen.

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Brian Lilly <brian at crystalfontz.com>
---
 .../devicetree/bindings/video/ssd1307fb.txt        |   24 ++
 drivers/video/Kconfig                              |   13 +
 drivers/video/Makefile                             |    1 +
 drivers/video/ssd1307fb.c                          |  386 ++++++++++++++++++++
 4 files changed, 424 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/ssd1307fb.txt
 create mode 100644 drivers/video/ssd1307fb.c

diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt
new file mode 100644
index 0000000..a709efa
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt
@@ -0,0 +1,24 @@
+* Solomon SSD1307 Framebuffer Driver
+
+Required properties:
+  - compatible: Should be "solomon,ssd1307fb-<bus>". The only supported bus for
+    now is i2c.
+  - reg: Should contain address of the controller on the I2C bus. Most likely
+         0x3c or 0x3d
+  - pwm: Should contain the pwm to use according to the OF device tree PWM
+         specification [0]
+  - oled-reset-gpio: Should contain the GPIO used to reset the OLED display
+
+Optional properties:
+  - oled-reset-active-low: Is the reset gpio is active on physical low?
+
+[0]: Documentation/devicetree/bindings/pwm/pwm.txt
+
+Examples:
+ssd1307: oled at 3c {
+        compatible = "solomon,ssd1307fb-i2c";
+        reg = <0x3c>;
+        pwms = <&pwm 4 3000>;
+        oled-reset-gpio = <&gpio2 7>;
+        oled-reset-active-low;
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f74..2776829 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2469,4 +2469,17 @@ config FB_SH_MOBILE_MERAM
 	  Up to 4 memory channels can be configured, allowing 4 RGB or
 	  2 YCbCr framebuffers to be configured.
 
+config FB_SSD1307
+	tristate "Solomon SSD1307 framebuffer support"
+	depends on FB && I2C
+	select FB_SYS_FOPS
+	select FB_SYS_FILLRECT
+	select FB_SYS_COPYAREA
+	select FB_SYS_IMAGEBLIT
+	select FB_DEFERRED_IO
+	select PWM
+	help
+	  This driver implements support for the Solomon SSD1307
+	  OLED controller over I2C.
+
 endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ee8dafb..6bbb72c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -164,6 +164,7 @@ obj-$(CONFIG_FB_BFIN_7393)        += bfin_adv7393fb.o
 obj-$(CONFIG_FB_MX3)		  += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
 obj-$(CONFIG_FB_MXS)		  += mxsfb.o
+obj-$(CONFIG_FB_SSD1307)	  += ssd1307fb.o
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/ssd1307fb.c b/drivers/video/ssd1307fb.c
new file mode 100644
index 0000000..544dca6
--- /dev/null
+++ b/drivers/video/ssd1307fb.c
@@ -0,0 +1,386 @@
+/*
+ * Driver for the Solomon SSD1307 OLED controler
+ *
+ * Copyright 2012 Free Electrons
+ *
+ * Licensed under the GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/uaccess.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pwm.h>
+#include <linux/delay.h>
+
+#define SSD1307FB_WIDTH			96
+#define SSD1307FB_HEIGHT		16
+
+#define SSD1307FB_DATA			0x40
+#define SSD1307FB_COMMAND		0x80
+
+#define SSD1307FB_CONTRAST		0x81
+#define SSD1307FB_SEG_REMAP_ON		0xa1
+#define SSD1307FB_DISPLAY_OFF		0xae
+#define SSD1307FB_DISPLAY_ON		0xaf
+#define SSD1307FB_START_PAGE_ADDRESS	0xb0
+
+struct ssd1307fb_par {
+	struct i2c_client *client;
+	struct fb_info *info;
+	struct pwm_device *pwm;
+	u32 pwm_period;
+	int reset;
+};
+
+static struct fb_fix_screeninfo ssd1307fb_fix __devinitdata = {
+	.id		= "Solomon SSD1307",
+	.type		= FB_TYPE_PACKED_PIXELS,
+	.visual		= FB_VISUAL_MONO10,
+	.xpanstep	= 0,
+	.ypanstep	= 0,
+	.ywrapstep	= 0,
+	.line_length	= SSD1307FB_WIDTH / 8,
+	.accel		= FB_ACCEL_NONE,
+};
+
+static struct fb_var_screeninfo ssd1307fb_var __devinitdata = {
+	.xres		= SSD1307FB_WIDTH,
+	.yres		= SSD1307FB_HEIGHT,
+	.xres_virtual	= SSD1307FB_WIDTH,
+	.yres_virtual	= SSD1307FB_HEIGHT,
+	.bits_per_pixel	= 1,
+};
+
+static int ssd1307fb_write_array(struct i2c_client *client, u8 type, u8* cmd, u32 len)
+{
+	u8 *buf;
+	int ret = 0;
+
+	buf = kzalloc(len + 1, GFP_KERNEL);
+	if (!buf) {
+		dev_err(&client->dev, "Couldn't allocate sending buffer.\n");
+		return -ENOMEM;
+	}
+
+	buf[0] = type;
+	memcpy(buf + 1, cmd, len);
+
+	ret = i2c_master_send(client, buf, len + 1);
+	if (ret != len + 1) {
+		dev_err(&client->dev, "Couldn't send I2C command.\n");
+		goto error;
+	}
+
+error:
+	kfree(buf);
+	return ret;
+}
+
+static inline int ssd1307fb_write_cmd_array(struct i2c_client *client, u8* cmd, u32 len)
+{
+	return ssd1307fb_write_array(client, SSD1307FB_COMMAND, cmd, len);
+}
+
+static inline int ssd1307fb_write_cmd(struct i2c_client *client, u8 cmd)
+{
+	return ssd1307fb_write_cmd_array(client, &cmd, 1);
+}
+
+static inline int ssd1307fb_write_data_array(struct i2c_client *client, u8* cmd, u32 len)
+{
+	return ssd1307fb_write_array(client, SSD1307FB_DATA, cmd, len);
+}
+
+static inline int ssd1307fb_write_data(struct i2c_client *client, u8 data)
+{
+	return ssd1307fb_write_data_array(client, &data, 1);
+}
+
+static void ssd1307fb_update_display(struct ssd1307fb_par *par)
+{
+	u8 *vmem = par->info->screen_base;
+	int i, j, k;
+
+	/*
+	 * The screen is divided in pages, each having a height of 8
+	 * pixels, and the width of the screen. When sending a byte of
+	 * data to the controller, it gives the 8 bits for the current
+	 * column. I.e, the first byte are the 8 bits of the first
+	 * column, then the 8 bits for the second column, etc.
+	 *
+	 *
+	 * Representation of the screen, assuming it is 5 bits
+	 * wide. Each letter-number combination is a bit that controls
+	 * one pixel.
+	 *
+	 * A0 A1 A2 A3 A4
+	 * B0 B1 B2 B3 B4
+	 * C0 C1 C2 C3 C4
+	 * D0 D1 D2 D3 D4
+	 * E0 E1 E2 E3 E4
+	 * F0 F1 F2 F3 F4
+	 * G0 G1 G2 G3 G4
+	 * H0 H1 H2 H3 H4
+	 *
+	 * If you want to update this screen, you need to send 5 bytes:
+	 *  (1) A0 B0 C0 D0 E0 F0 G0 H0
+	 *  (2) A1 B1 C1 D1 E1 F1 G1 H1
+	 *  (3) A2 B2 C2 D2 E2 F2 G2 H2
+	 *  (4) A3 B3 C3 D3 E3 F3 G3 H3
+	 *  (5) A4 B4 C4 D4 E4 F4 G4 H4
+	 */
+
+	for (i = 0; i < (SSD1307FB_HEIGHT / 8); i++) {
+		ssd1307fb_write_cmd(par->client, SSD1307FB_START_PAGE_ADDRESS + (i + 1));
+		ssd1307fb_write_cmd(par->client, 0x00);
+		ssd1307fb_write_cmd(par->client, 0x10);
+
+		for (j = 0; j < SSD1307FB_WIDTH; j++) {
+			u8 buf = 0;
+			for (k = 0; k < 8; k++) {
+				u32 page_length = SSD1307FB_WIDTH * i;
+				u32 index = page_length + (SSD1307FB_WIDTH * k + j) / 8;
+				u8 byte = *(vmem + index);
+				u8 bit = byte & (1 << (7 - (j % 8)));
+				bit = bit >> (7 - (j % 8));
+				buf |= bit << k;
+			}
+			ssd1307fb_write_data(par->client, buf);
+		}
+	}
+}
+
+
+static ssize_t ssd1307fb_write(struct fb_info *info, const char __user *buf,
+		size_t count, loff_t *ppos)
+{
+	struct ssd1307fb_par *par = info->par;
+	unsigned long p = *ppos;
+	void *dst;
+	int err = 0;
+
+	dst = (void __force *) (info->screen_base + p);
+
+	if (copy_from_user(dst, buf, count))
+		err = -EFAULT;
+
+	if  (!err)
+		*ppos += count;
+
+	ssd1307fb_update_display(par);
+
+	return (err) ? err : count;
+}
+
+static void ssd1307fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
+	struct ssd1307fb_par *par = info->par;
+	sys_fillrect(info, rect);
+	ssd1307fb_update_display(par);
+}
+
+static void ssd1307fb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 
+{
+	struct ssd1307fb_par *par = info->par;
+	sys_copyarea(info, area);
+	ssd1307fb_update_display(par);
+}
+
+static void ssd1307fb_imageblit(struct fb_info *info, const struct fb_image *image) 
+{
+	struct ssd1307fb_par *par = info->par;
+	sys_imageblit(info, image);
+	ssd1307fb_update_display(par);
+}
+
+static struct fb_ops ssd1307fb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_read	= fb_sys_read,
+	.fb_write	= ssd1307fb_write,
+	.fb_fillrect	= ssd1307fb_fillrect,
+	.fb_copyarea	= ssd1307fb_copyarea,
+	.fb_imageblit	= ssd1307fb_imageblit,
+};
+
+static void ssd1307fb_deferred_io(struct fb_info *info,
+				struct list_head *pagelist)
+{
+	ssd1307fb_update_display(info->par);
+}
+
+static struct fb_deferred_io ssd1307fb_defio = {
+	.delay		= HZ,
+	.deferred_io	= ssd1307fb_deferred_io,
+};
+
+static int __devinit ssd1307fb_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct fb_info *info;
+	u32 vmem_size = SSD1307FB_WIDTH * SSD1307FB_HEIGHT / 8;
+	struct ssd1307fb_par *par;
+	u8 *vmem;
+	int ret;
+
+	if (!client->dev.of_node) {
+		dev_err(&client->dev, "No device tree data found!\n");
+		return -EINVAL;
+	}
+
+	info = framebuffer_alloc(sizeof(struct ssd1307fb_par), &client->dev);
+	if (!info) {
+		dev_err(&client->dev, "Couldn't allocate framebuffer.\n");
+		return -ENOMEM;
+	}
+
+	vmem = devm_kzalloc(&client->dev, vmem_size, GFP_KERNEL);
+	if (!vmem) {
+		dev_err(&client->dev, "Couldn't allocate graphical memory.\n");
+		ret = -ENOMEM;
+		goto fb_alloc_error;
+	}
+
+	info->fbops = &ssd1307fb_ops;
+	info->fix = ssd1307fb_fix;
+	info->fbdefio = &ssd1307fb_defio;
+
+	info->var = ssd1307fb_var;
+	info->var.red.length = 1;
+	info->var.red.offset = 0;
+	info->var.green.length = 1;
+	info->var.green.offset = 0;
+	info->var.blue.length = 1;
+	info->var.blue.offset = 0;
+
+	info->screen_base = (u8 __force __iomem *)vmem;
+	info->fix.smem_start = (unsigned long)vmem;
+	info->fix.smem_len = vmem_size;
+
+	fb_deferred_io_init(info);
+
+	par = info->par;
+	par->info = info;
+	par->client = client;
+
+	par->reset = of_get_named_gpio(client->dev.of_node,
+					 "oled-reset-gpio", 0);
+	if (gpio_is_valid(par->reset)) {
+		int flags = GPIOF_OUT_INIT_HIGH;
+		if (of_get_property(client->dev.of_node,
+				    "oled-reset-active-low", NULL))
+			flags = GPIOF_OUT_INIT_LOW;
+		ret = devm_gpio_request_one(&client->dev, par->reset,
+					    flags, "oled-reset");
+		if (ret) {
+			dev_err(&client->dev,
+				"failed to request gpio %d: %d\n",
+				par->reset, ret);
+			goto reset_oled_error;
+		}
+	}
+
+	par->pwm = pwm_get(&client->dev, NULL);
+	if (IS_ERR(par->pwm)) {
+		dev_err(&client->dev, "Could not get PWM from device tree!\n");
+		ret = PTR_ERR(par->pwm);
+		goto pwm_error;
+	}
+
+	par->pwm_period = pwm_get_period(par->pwm);
+
+	dev_dbg(&client->dev, "Using PWM%d with a %dns period.\n", par->pwm->pwm, par->pwm_period);
+
+	ret = register_framebuffer(info);
+	if (ret) {
+		dev_err(&client->dev, "Couldn't register the framebuffer\n");
+		goto fbreg_error;
+	}
+
+	i2c_set_clientdata(client, info);
+
+	/* Reset the screen */
+	gpio_set_value(par->reset, 1);
+	udelay(4);
+	gpio_set_value(par->reset, 0);
+	udelay(4);
+
+	/* Enable the PWM */
+	pwm_config(par->pwm, par->pwm_period / 2, par->pwm_period);
+	pwm_enable(par->pwm);
+
+	/* Map column 127 of the OLED to segment 0 */
+	ret = ssd1307fb_write_cmd(client, SSD1307FB_SEG_REMAP_ON);
+	if (ret < 0) {
+		dev_err(&client->dev, "Couldn't remap the screen.\n");
+		goto remap_error;
+	}
+
+	/* Turn on the display */
+	ret = ssd1307fb_write_cmd(client, SSD1307FB_DISPLAY_ON);
+	if (ret < 0) {
+		dev_err(&client->dev, "Couldn't turn the display on.\n");
+		goto remap_error;
+	}
+
+	dev_info(&client->dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n", info->node, info->fix.id, vmem_size);
+
+	return 0;
+
+remap_error:
+	unregister_framebuffer(info);
+	pwm_disable(par->pwm);
+fbreg_error:
+	pwm_put(par->pwm);
+pwm_error:
+reset_oled_error:
+	fb_deferred_io_cleanup(info);
+fb_alloc_error:
+	framebuffer_release(info);
+	return ret;
+}
+
+static int __devexit ssd1307fb_remove(struct i2c_client *client)
+{
+	struct fb_info *info = i2c_get_clientdata(client);
+	struct ssd1307fb_par *par = info->par;
+
+	unregister_framebuffer(info);
+	pwm_disable(par->pwm);
+	pwm_put(par->pwm);
+	fb_deferred_io_cleanup(info);
+	framebuffer_release(info);
+
+	return 0;
+}
+
+static const struct i2c_device_id ssd1307fb_i2c_id[] = {
+	{ "ssd1307fb", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, ssd1307fb_i2c_id);
+
+static const struct of_device_id ssd1307fb_of_match[] = {
+	{ .compatible = "solomon,ssd1307fb-i2c" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ssd1307fb_of_match);
+
+static struct i2c_driver ssd1307fb_driver = {
+	.probe = ssd1307fb_probe,
+	.remove = __devexit_p(ssd1307fb_remove),
+	.id_table = ssd1307fb_i2c_id,
+	.driver = {
+		.name = "ssd1307fb",
+		.of_match_table = of_match_ptr(ssd1307fb_of_match),
+		.owner = THIS_MODULE,
+	},
+};
+
+module_i2c_driver(ssd1307fb_driver);
+
+MODULE_DESCRIPTION("FB driver for the Solomon SSD1307 OLED controler");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard at free-electrons.com>");
+MODULE_LICENSE("GPL");
-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Thu Aug 23 04:42:30 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 Aug 2012 10:42:30 +0200
Subject: [PATCH 3/4] ARM: dts: mxs: Add pwm4 muxing options for imx28
In-Reply-To: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1345711351-16367-4-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Brian Lilly <brian at crystalfontz.com>
---
 arch/arm/boot/dts/imx28.dtsi |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index f6ffcd9..60d10d7 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -464,6 +464,16 @@
 					fsl,pull-up = <0>;
 				};
 
+				pwm4_pins_a: pwm4 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
 				lcdif_24bit_pins_a: lcdif-24bit at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Thu Aug 23 04:42:31 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Thu, 23 Aug 2012 10:42:31 +0200
Subject: [PATCH 4/4] ARM: dts: mxs: add oled support for the cfa-10036
In-Reply-To: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1345711351-16367-5-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Cc: Brian Lilly <brian at crystalfontz.com>
---
 arch/arm/boot/dts/imx28-cfa10036.dts |   20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index c03a577..92784a9 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -33,11 +33,31 @@
 		};
 
 		apbx at 80040000 {
+			pwm: pwm at 80064000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pwm4_pins_a>;
+				status = "okay";
+			};
+
 			duart: serial at 80074000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&duart_pins_b>;
 				status = "okay";
 			};
+
+			i2c0: i2c at 80058000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins_b>;
+				status = "okay";
+
+				ssd1307: oled at 3c {
+					compatible = "solomon,ssd1307fb-i2c";
+					reg = <0x3c>;
+					pwms = <&pwm 4 3000>;
+					oled-reset-gpio = <&gpio2 7 1>;
+					oled-reset-active-low;
+				};
+			};
 		};
 	};
 
-- 
1.7.9.5



From arnd at arndb.de  Thu Aug 23 04:48:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 08:48:51 +0000
Subject: [PATCH v2 0/3] ARM: PRIMA2: some patches prepared to support new
 SiRF SoCs
In-Reply-To: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
References: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
Message-ID: <201208230848.51650.arnd@arndb.de>

On Thursday 23 August 2012, Barry Song wrote:
> we will support SiRFmarco and SiRFpolo SMP SoCs, this series is making
> mach-prima2 common for all of them.
> 
> Barry Song (3):
>   ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
>   ARM: PRIMA2: adjust Kconfig to support select SoC features
>   ARM: SIRF: make sirf irqchip driver optional since new SoCs will have
>     GIC

Looks all good. Are you planning to send a git pull request, or should
we apply the patches from email?

	Arnd


From stigge at antcom.de  Thu Aug 23 04:59:00 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 10:59:00 +0200
Subject: [PATCH 1/2] usb: change the dependency chain for LPC32XX and
 ISP1301
In-Reply-To: <5035E9D0.9020107@linutronix.de>
References: <Pine.LNX.4.44L0.1208221537260.1328-100000@iolanthe.rowland.org>
 <50355A2C.9010505@antcom.de> <5035D9E0.1000905@linutronix.de>
 <5035E75F.5080801@antcom.de> <5035E9D0.9020107@linutronix.de>
Message-ID: <5035F0D4.9020001@antcom.de>

On 08/23/2012 10:29 AM, Sebastian Andrzej Siewior wrote:
>> For the PNX4008 removal - should I already post a patch to build the
>> respective changes on top of, without PNX4008 references?
> 
> If nobody cares about PNX4008 and nobody tested if it actually works in
> the OHCI mode I don't see the point in keeping it around especially if
> there are rumors to remove the arch.
> 
> It would be nice, if you could manage to compile this thingy without
> I2C. In the end one could attach something different than isp1301, no?
> So I think, in the perfect world you would probe for your phy and
> notice that it is not there and print a message: "Dude! Select isp1301
> for OHCI, aight?!"

Currently, we really need I2C for OHCI on LPC32XX, so actually need to
depend on it. Removing the I2C calls in ohci-nxp.c is waiting for the
phy framework so that I don't need to introduce new API in isp1301.c at
this point.

And right, in the ideal world, we have no I2C dependency and can control
a phy in an abstract way, even without depending on ISP1301, which could
be replaced by sth. else (not sure if this will be done/soldered
practically, though).

For now, will post patches for the current I2C dependency and the
PNX4008 removal.

Roland


From ludovic.desroches at atmel.com  Thu Aug 23 05:05:42 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Thu, 23 Aug 2012 11:05:42 +0200
Subject: JFFS2 issue with v3.5.x and later on Atmel chips at least
In-Reply-To: <1345707689.2848.203.camel@sauron.fi.intel.com>
References: <5034B45A.5060107@atmel.com> <5034F3F8.9080802@atmel.com>
 <1345707689.2848.203.camel@sauron.fi.intel.com>
Message-ID: <5035F266.2040909@atmel.com>

Hi Artem,

Le 08/23/2012 09:41 AM, Artem Bityutskiy a ?crit :
> From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Date: Thu, 23 Aug 2012 10:10:07 +0300
> Subject: [PATCH] JFFS2: fix unmount regression
>
> This patch fixes regression introduced by
> "8bdc81c jffs2: get rid of jffs2_sync_super". We submit a delayed work in order
> to make sure the write-buffer is synchronized at some point. But we do not
> flush it when we unmount, which causes an oops when we unmount the file-system
> and then the delayed work is executed.
>
> This patch fixes the issue by adding a "cancel_delayed_work_sync()" infocation
> in the '->sync_fs()' handler. This will make sure the delayed work is canceled
> on sync, unmount and re-mount. And because VFS always callse 'sync_fs()' before
> unmounting or remounting, this fixes the issue.
>
> Reported-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Cc: stable at vger.kernel.org [3.5+]
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> ---
>
> Ludovic, would you please give this patch a test? Also attached.
>

Thanks for your reactivity. I tested your patch on sam9m10g45 with 3.5 
and 3.5.2 and it fixes the issue.

Tested-by: Ludovic Desroches <ludovic.desroches at atmel.com>

>   fs/jffs2/super.c |    3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/fs/jffs2/super.c b/fs/jffs2/super.c
> index 61ea413..e385fa3 100644
> --- a/fs/jffs2/super.c
> +++ b/fs/jffs2/super.c
> @@ -100,6 +100,9 @@ static int jffs2_sync_fs(struct super_block *sb, int wait)
>   {
>   	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
>
> +	if (IS_ENABLED(CONFIG_JFFS2_FS_WRITEBUFFER))
> +		cancel_delayed_work_sync(&c->wbuf_dwork);
> +
>   	mutex_lock(&c->alloc_sem);
>   	jffs2_flush_wbuf_pad(c);
>   	mutex_unlock(&c->alloc_sem);
>



From 21cnbao at gmail.com  Thu Aug 23 05:09:57 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Thu, 23 Aug 2012 17:09:57 +0800
Subject: [PATCH v2 0/3] ARM: PRIMA2: some patches prepared to support new
 SiRF SoCs
In-Reply-To: <201208230848.51650.arnd@arndb.de>
References: <1345700519-667-1-git-send-email-Barry.Song@csr.com>
 <201208230848.51650.arnd@arndb.de>
Message-ID: <CAGsJ_4wfh+f0Orgr5T0A8DCT+9p7MqQbf-ybS1wGbf-_Nd115g@mail.gmail.com>

Hi Arnd,
2012/8/23 Arnd Bergmann <arnd at arndb.de>:
> On Thursday 23 August 2012, Barry Song wrote:
>> we will support SiRFmarco and SiRFpolo SMP SoCs, this series is making
>> mach-prima2 common for all of them.
>>
>> Barry Song (3):
>>   ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
>>   ARM: PRIMA2: adjust Kconfig to support select SoC features
>>   ARM: SIRF: make sirf irqchip driver optional since new SoCs will have
>>     GIC
>
> Looks all good. Are you planning to send a git pull request, or should
> we apply the patches from email?

I will send a git pull request based on -rc.

>
>         Arnd

-barry


From lee.jones at linaro.org  Thu Aug 23 05:22:17 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 10:22:17 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <006d01cd7f5a$65937840$30ba68c0$@se>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
Message-ID: <20120823092216.GA27264@gmail.com>

Mark,

> > > I'm sorry but this patch is breaking the design of ASoC.
> > > The ASoC-platform is the DMA-block (in combination with the
> > > MSP-block), and there should be a platform-driver for the DMA/PCM.
> > > The
> > > platform-driver then has a DAI which is the MSP. The ASoC
> > > DAI-link-struct should have one driver for each of these, so the
> > > dummy-driver for PCM should be there.
> > 
> > Just thinking about this now. I converted it to the current format at
> > the request of Mark. If this isn't the correct method I'm not quite
> > sure what is. If you want it to be registered as a device, then it
> > needs to go into the Device Tree, but Mark doesn't want it in there
> > because it doesn't actually represent hardware.

I've just taken a closer look at this with a view to finding the most
suitable solution. My conclusion is that although the PCM doesn't
contain any registers, or represent hardware it should be a device and
therefore be present in the Device Tree.

These are my findings:

PCM devices already represented in DTs:
  fsl,mpc5200-pcm - written by Grant Likely, the author of Device Tree
  phytec,pcm030   - written by Grant Likely, the author of Device Tree

PCM devices which register as actual devices (should be in DT):
  samsung  - samsung-pcm
  sh       - siu-pcm-audio
  omap     - omap-pcm-audio
  pxa      - pxa-pcm-audio
  jz4740   - jz4740-pcm-audio
  kirkwood - kirkwood-pcm-audio
  ep93xx   - ep93xx-pcm-audio
  ...

The later was basically every PCM device bar one I think.

The Open Firmware used to stipulate that each device represented in
the Device Tree to own registers and therefore be an actual hardware
device, but that has since been lifted as it didn't make sense.

I propose to represent the PCM in the Device Tree again and have it
probe just like all the other PCM devices in sound/soc.

If you give me the nod, I'll revert this patch, enable the PCM for DT
again and resent the patch-set in full.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From peter.ujfalusi at ti.com  Thu Aug 23 05:29:07 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:07 +0300
Subject: [PATCH 0/6] ARM/dts: omap McBSP and audio support for BeagleBoard
Message-ID: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

The following series will add the needed entries for OMAP McBSP for DeviceTree
and enable the audio support on BeagleBoard when booted with DT.

Regards,
Peter
---
Peter Ujfalusi (6):
  ARM/dts: OMAP2: Add McBSP entries for OMAP2420 and OMAP2430 SoC
  ARM/dts: omap2420-h4: Include omap2420.dtsi file instead the common
    omap2
  ARM/dts: OMAP3: Add McBSP entries
  ARM/dts: OMAP4: Add McBSP entries
  ARM/dts: OMAP5: Add McBSP entries
  ARM/dts: omap3-beagle: Enable audio support

 arch/arm/boot/dts/omap2420-h4.dts  |    2 +-
 arch/arm/boot/dts/omap2420.dtsi    |   39 +++++++++++++++++
 arch/arm/boot/dts/omap2430.dtsi    |   83 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-beagle.dts |   14 ++++++
 arch/arm/boot/dts/omap3.dtsi       |   69 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi       |   47 ++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi       |   36 +++++++++++++++
 7 files changed, 289 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap2420.dtsi
 create mode 100644 arch/arm/boot/dts/omap2430.dtsi

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:08 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:08 +0300
Subject: [PATCH 1/6] ARM/dts: OMAP2: Add McBSP entries for OMAP2420 and
 OMAP2430 SoC
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-2-git-send-email-peter.ujfalusi@ti.com>

The McBSP IP within OMAP2420 and 2430 is different we need to create separate
dtsi files for them.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap2420.dtsi |   39 ++++++++++++++++++
 arch/arm/boot/dts/omap2430.dtsi |   83 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 122 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap2420.dtsi
 create mode 100644 arch/arm/boot/dts/omap2430.dtsi

diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 0000000..f375c68
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+	compatible = "ti,omap2420", "ti,omap2";
+
+	ocp {
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap2420-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>; /* RX interrupt */
+			interrupt-names = "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 48076000 {
+			compatible = "ti,omap2420-mcbsp";
+			reg = <0x48076000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>; /* RX interrupt */
+			interrupt-names = "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,hwmods = "mcbsp2";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 0000000..531e346
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+	compatible = "ti,omap2430", "ti,omap2";
+
+	ocp {
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 64 0x4>, /* OCP compliant interrupt */
+				     <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>, /* RX interrupt */
+				     <0 61 0x4>; /* RX overflow interrupt */
+			interrupt-names = "common", "tx", "rx", "rx_overflow";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 48076000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48076000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>, /* OCP compliant interrupt */
+				     <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 4808c000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x4808c000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+				     <0 89 0x4>, /* TX interrupt */
+				     <0 90 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 4808e000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x4808e000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 18 0x4>, /* OCP compliant interrupt */
+				     <0 54 0x4>, /* TX interrupt */
+				     <0 55 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
+
+		mcbsp5: mcbsp at 48096000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48096000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 19 0x4>, /* OCP compliant interrupt */
+				     <0 81 0x4>, /* TX interrupt */
+				     <0 82 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp5";
+		};
+	};
+};
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:09 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:09 +0300
Subject: [PATCH 2/6] ARM/dts: omap2420-h4: Include omap2420.dtsi file instead
 the common omap2
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-3-git-send-email-peter.ujfalusi@ti.com>

Since the board is based on OMAP2420 we should include the dedicated dtsi
file (which includes the common omap2 dtsi).

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap2420-h4.dts |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b7..77b84e1 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:10 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:10 +0300
Subject: [PATCH 3/6] ARM/dts: OMAP3: Add McBSP entries
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-4-git-send-email-peter.ujfalusi@ti.com>

Create the needed sections to be able to probe McBSP ports via DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap3.dtsi |   69 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 8109471..5c14b00 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -220,5 +220,74 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>, /* OCP compliant interrupt */
+				     <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 49022000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49022000 0xff>,
+			      <0x49028000 0xff>;
+			reg-names = "mpu", "sidetone";
+			interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+				     <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>, /* RX interrupt */
+				     <0 4 0x4>;  /* Sidetone */
+			interrupt-names = "common", "tx", "rx", "sidetone";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <1280>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 49024000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49024000 0xff>,
+			      <0x4902a000 0xff>;
+			reg-names = "mpu", "sidetone";
+			interrupts = <0 22 0x4>, /* OCP compliant interrupt */
+				     <0 89 0x4>, /* TX interrupt */
+				     <0 90 0x4>, /* RX interrupt */
+				     <0 5 0x4>;  /* Sidetone */
+			interrupt-names = "common", "tx", "rx", "sidetone";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 49026000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49026000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 23 0x4>, /* OCP compliant interrupt */
+				     <0 54 0x4>, /* TX interrupt */
+				     <0 55 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
+
+		mcbsp5: mcbsp at 48096000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x48096000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 27 0x4>, /* OCP compliant interrupt */
+				     <0 81 0x4>, /* TX interrupt */
+				     <0 82 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp5";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:11 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:11 +0300
Subject: [PATCH 4/6] ARM/dts: OMAP4: Add McBSP entries
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-5-git-send-email-peter.ujfalusi@ti.com>

Create the sections describing the McBSP ports to be able to use them via
DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |   47 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..258435f 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,52 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
 		};
+
+		mcbsp1: mcbsp at 40122000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40122000 0xff>, /* MPU private access */
+			      <0x49022000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 17 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 40124000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40124000 0xff>, /* MPU private access */
+			      <0x49024000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 22 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 40126000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40126000 0xff>, /* MPU private access */
+			      <0x49026000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 23 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 48096000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x48096000 0xff>; /* L4 Interconnect */
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:12 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:12 +0300
Subject: [PATCH 5/6] ARM/dts: OMAP5: Add McBSP entries
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-6-git-send-email-peter.ujfalusi@ti.com>

Create the sections describing the McBSP ports to be able to use them via
DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e5270..c5f9242 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -180,5 +180,41 @@
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 		};
+
+		mcbsp1: mcbsp at 40122000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40122000 0xff>, /* MPU private access */
+			      <0x49022000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 17 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 40124000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40124000 0xff>, /* MPU private access */
+			      <0x49024000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 22 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 40126000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40126000 0xff>, /* MPU private access */
+			      <0x49026000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 23 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Thu Aug 23 05:29:13 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 12:29:13 +0300
Subject: [PATCH 6/6] ARM/dts: omap3-beagle: Enable audio support
In-Reply-To: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345714153-13094-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1345714153-13094-7-git-send-email-peter.ujfalusi@ti.com>

Add the needed sections to enable audio support on BeagleBoard when booted
with DT blob.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap3-beagle.dts |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index cdcb98c..28cf180 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -17,6 +17,14 @@
 		device_type = "memory";
 		reg = <0x80000000 0x20000000>; /* 512 MB */
 	};
+
+	sound {
+		compatible = "ti,omap-twl4030";
+		ti,model = "omap3beagle";
+
+		ti,mcbsp = <&mcbsp2>;
+		ti,codec = <&twl_audio>;
+	};
 };
 
 &i2c1 {
@@ -32,6 +40,12 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <3000000>;
 		};
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			codec {
+			};
+		};
 	};
 };
 
-- 
1.7.8.6



From stigge at antcom.de  Thu Aug 23 05:30:54 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 11:30:54 +0200
Subject: mxc_nand.c on mach-imx/imx53
Message-ID: <5035F84E.3000901@antcom.de>

Hi,

I'd like to know about the current state of mxc_nand.c on imx53, because
I got an error on probe() because the clock that mxc_nand is requesting
is "nfc" but imx53 only defines the clock "mxc_nand".

Even after adjusting the name, probe() couldn't find the clock, so I'm
wondering if mxc_nand.c is supported on imx53 at all because other mx'es
have IMX_HAVE_PLATFORM_MXC_NAND in arch/arm/mach-imx/Kconfig but not imx53.

In a custom board BSP, I found an mxc_nd2.c besides mxc_nand.c but not
in mainline. Are there any plans here?

But maybe I just missed sth. - a hint or link would be very much
appreciated.

Thanks in advance,

Roland


From shawn.guo at linaro.org  Thu Aug 23 05:34:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 17:34:11 +0800
Subject: [GIT PULL] imx fixes for 3.6 (take 2)
Message-ID: <20120823093407.GE24242@S2101-09.ap.freescale.net>

Hi Arnd, Olof,

Please pull the following imx fixes for 3.6-rc.  Thanks.

Regards,
Shawn

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:
  git://git.linaro.org/people/shawnguo/linux-2.6.git imx/fixes-for-3.6

Philipp Zabel (1):
      ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path

Shawn Guo (3):
      ARM: imx6q: remove imx_src_prepare_restart() call
      ARM: imx6: spin the cpu until hardware takes it down
      ARM: dts: imx51-babbage: fix esdhc cd/wp properties

 .../devicetree/bindings/mmc/fsl-imx-esdhc.txt      |    8 +++---
 arch/arm/boot/dts/imx51-babbage.dts                |    4 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    8 ++++--
 arch/arm/mach-imx/hotplug.c                        |   23 ++-----------------
 arch/arm/mach-imx/mach-imx6q.c                     |    2 -
 arch/arm/mach-imx/src.c                            |   13 -----------
 arch/arm/plat-mxc/include/mach/common.h            |    1 -
 7 files changed, 14 insertions(+), 45 deletions(-)


From kgene.kim at samsung.com  Thu Aug 23 05:45:19 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 Aug 2012 18:45:19 +0900
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <20120813122359.GA13446@opensource.wolfsonmicro.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
 <20120810100713.GH24328@opensource.wolfsonmicro.com>
 <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>
 <20120813122359.GA13446@opensource.wolfsonmicro.com>
Message-ID: <1d5901cd8114$023550f0$069ff2d0$%kim@samsung.com>

Mark Brown wrote:
> 
> On Sat, Aug 11, 2012 at 02:08:09PM +0900, Kukjin Kim wrote:
> 
> > BTW, don't you need to enable your Cragganmore board in the defconfig?
> 
> Well, it doesn't really matter that much to us - it's more a question
> for whoever uses the defconfig.

Yeah, actually SoC defconfig in mainline doesn't cover _real_ requirements
for (mass) product. But I think, it's time we need to sort out the
defconfigs so that we could use them efficiently on product. BTW, if
enabling board in defconfig, at least, unexpected build breakages could be
detected by testing defconfig before merge for mainline...

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From sebastian.hesselbarth at gmail.com  Thu Aug 23 05:45:27 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 23 Aug 2012 11:45:27 +0200
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <5035445B.6000500@wwwdotorg.org>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
Message-ID: <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>

On 8/22/12, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
>> +++ b/drivers/pinctrl/pinctrl-mvebu.c
>
>> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
>
>> +	of_property_for_each_string(np, "marvell,pins", prop, group) {
>> +		struct mvebu_pinctrl_group *grp =
>> +			mvebu_pinctrl_find_group_by_name(pctl, group);
>> +
>> +		if (!grp) {
>> +			dev_err(pctl->dev, "unknown pin %s", group);
>> +			continue;
>> +		}
>> +
>> +		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
>> +			dev_err(pctl->dev, "unsupported function %s on pin %s",
>> +				function, group);
>> +			continue;
>> +		}
>
> The error-checking here isn't strictly necessary; the pinctrl core will
> error-check all the names if/when the map entries are used. So, you
> could probably get away with just assigning the pin/function names
> directly into (*map) and hence remove some code here. Still, it's not a
> big deal either way.

Hi Stephen,

as these error checks are only performed once, I'd like to have them there
as they give hints when someone uses wrong marvell,pins/function names
in DT.

>> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl
>> *pctl,
>
>> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device
>> *pdev,
>> +					struct mvebu_pinctrl *pctl)
>
> I don't understand what those two functions do, or a good chunk of
> probe(). It seems like they're setting up the ability to get/set pin
> configrations in addition to pin muxing, although if that's so, it seems
> odd that none of the binding documents specify any way of controlling
> pin configuration from device tree. Are you expecting drivers to call
> APIs such as pin_config_set() directly, rather than controlling pin
> config through DT?

probe() receives some structs from the SoC specific driver stubs that
describe, e.g. how many muxable pins are available, which pingroup they
belong to (marvell,pins), what valid register values are and how they are
named (marvell,function). Although, all mvebu SoC share a good part of
pinmux register layout, there are especially for dove some very different
ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no
pin drive strength or pin direction configuration, we decided not to have
single pins controlable but only pingroups even if they comprise only a
single pin.

dt_parse() and dt_parse_function() build up structs that get used later on
in mvebu_pinmux_ops that require indexed functions. I can join them with
dt_node_to_map() but that would require incremental kzalloc for the
corresponding array. Or I could (functionally) leave dt_parse() to allocate
the array and only join dt_parse_function() with dt_node_to_map().

There is an example of how to use pinctrl in marvell.mvebu-pinctrl.txt:
uart1: serial at 12100 {
	compatible = "ns16550a";
	reg = <0x12100 0x100>;
	reg-shift = <2>;
	interrupts = <7>;

	pinctrl-0 = <&pmx_uart1_sw>;
};

pinctrl: pinctrl at d0200 {
	compatible = "marvell,dove-pinctrl";
	reg = <0xd0200 0x20>;

	pmx_uart1_sw: pmx-uart1-sw {
		marvell,pins = "mpp_uart1";
		marvell,function = "uart1";
	};
};

In my understanding this will allow uart1 to switch the pingroup "mpp_uart1"
to the function "uart1". The pinctrl core driver is taking care of
translating mpp_uart1
to the corresponding pingroup and mvebu core driver of translating
uart1 into the required
register values to set the requested function. Is it so odd, that we
use names instead
of direct register values in DT? I agree, that maybe picking an example for dove
that is a little bit different in pingroup naming isn't the best
choice but it still gives
you an idea how to use it.

Consider this (virtual) example:
Muxing some SATA functions to pins 24 and 37 would require to set
register values
to 0x3 on pin 24 and 0x6 on pin 37. The proposed driver still allows
us to have a DT
description of

pmx_sata_example: pmx-sata-example {
	marvell,pins = "mpp24", "mpp37";
	marvell,function = "sata";
};

because the SoC specific driver passes function "sata" on pins 24 and
37 with the
corresponding register values. These are fed by the mvebu core driver
that builds
up all required pins, pingroups, and pinmux functions.

Sebastian


From kgene.kim at samsung.com  Thu Aug 23 05:55:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 Aug 2012 18:55:37 +0900
Subject: [PATCH V2 0/5] arm: samsung: Move FIMD headers to include/video/
In-Reply-To: <5018FDF6.4020205@gmx.de>
References: <1343737385-23337-1-git-send-email-l.krishna@samsung.com>
 <02f701cd6f8d$5ca3e850$15ebb8f0$%kim@samsung.com> <5018FDF6.4020205@gmx.de>
Message-ID: <1d5a01cd8115$7251eb40$56f5c1c0$%kim@samsung.com>

Florian Tobias Schandinat wrote:
> 
> On 08/01/2012 02:28 AM, Kukjin Kim wrote:
> > Leela Krishna Amudala wrote:
> >>
> >> This patchset moves the contents of regs-fb-v4.h and regs-fb.h from
> arch
> >> side
> >> to include/video/samsung_fimd.h
> >>
> >> This patchset is created and rebased against master branch of torvalds
> >> tree.
> >> Tested on smdk5250 board, build tested for other boards.
> >>
> > (Cc'ed Florian Tobias Schandinat)
> >
> > Yeah, since it's merge window, this series could be created against on
> > mainline. And IMO, would be helpful to us if this series could be sent
> to
> > upstream via samsung tree after reviewing, because this touches too many
> > files in samsung tree and just adds include/video/samsung_fimd.h. But
> I'm
> > not sure the added inclusion will be used in other file of
drivers/video.
> If
> > so, I can provide some topic branch can be merged into Florian's tree.
> > Florian, how about?
> 
> Using a topic branch to merge it in both trees sounds like a good plan
> to me.
> 
Florian,

Please pull following topic branch we talked. I already merged it into my
-next.

git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
v3.7-for-florian

Note, I applied Leela's V4 patches not this V2 series.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
v3.7-for-florian

Leela Krishna Amudala (2):
      include/video: move fimd register headers from platform to
include/video
      include/video: Add register offsets for FIMD version 8

 arch/arm/mach-exynos/mach-nuri.c                   |    2 +-
 arch/arm/mach-exynos/mach-origen.c                 |    2 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |    2 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159
--------------------
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/video/s3c-fb.c                             |    2 +-
 .../plat/regs-fb.h => include/video/samsung_fimd.h |  152
+++++++++++++++++--
 26 files changed, 165 insertions(+), 194 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 rename arch/arm/plat-samsung/include/plat/regs-fb.h =>
include/video/samsung_fimd.h (73%)



From will.deacon at arm.com  Thu Aug 23 05:56:49 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 23 Aug 2012 10:56:49 +0100
Subject: [PATCH] ARM: contextidr: avoid using bfi instruction during notifier
Message-ID: <1345715809-12312-1-git-send-email-will.deacon@arm.com>

The bfi instruction is not available on ARMv6, so instead use an and/orr
sequence in the contextidr_notifier. This gets rid of the assembler
error:

  Assembler messages:
  Error: selected processor does not support ARM mode `bfi r3,r2,#0,#8'

Reported-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

Tested on my Integrator/CP w/ an 1136 tile.

 arch/arm/mm/context.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 119bc52..4e07eec 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
 	pid = task_pid_nr(thread->task) << ASID_BITS;
 	asm volatile(
 	"	mrc	p15, 0, %0, c13, c0, 1\n"
-	"	bfi	%1, %0, #0, %2\n"
-	"	mcr	p15, 0, %1, c13, c0, 1\n"
+	"	and	%0, %0, %2\n"
+	"	orr	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c13, c0, 1\n"
 	: "=r" (contextidr), "+r" (pid)
-	: "I" (ASID_BITS));
+	: "I" (~ASID_MASK));
 	isb();
 
 	return NOTIFY_OK;
-- 
1.7.4.1



From nicolas.ferre at atmel.com  Thu Aug 23 05:57:19 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 11:57:19 +0200
Subject: [PATCH v2 1/2] ARM: at91: fix system timer irq issue due to sparse
 irq support
In-Reply-To: <1344935962-18871-2-git-send-email-ludovic.desroches@atmel.com>
References: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
 <1344935962-18871-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5035FE7F.3000406@atmel.com>

On 08/14/2012 11:19 AM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> AT91_ID_SYS as virq is incorrect because of spare irq support which
> introduces NR_IRQS_LEGACY offset.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> Tested-by: Joachim Eastwood <joachim.eastwood at jotron.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

And pushed in at91-fixes branch for 3.6.
Thanks,

> ---
>  arch/arm/mach-at91/at91rm9200_time.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index 104ca40..aaa443b 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
>  	at91_st_read(AT91_ST_SR);
>  
>  	/* Make IRQs happen for the system timer */
> -	setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
> +	setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
>  
>  	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
>  	 * directly for the clocksource and all clockevents, after adjusting
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Aug 23 05:58:09 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 11:58:09 +0200
Subject: [PATCH v2 2/2] ARM: at91: fix rtc-at91sam9 irq issue due to sparse
 irq support
In-Reply-To: <1344935962-18871-3-git-send-email-ludovic.desroches@atmel.com>
References: <1344935962-18871-1-git-send-email-ludovic.desroches@atmel.com>
 <1344935962-18871-3-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <5035FEB1.8010701@atmel.com>

On 08/14/2012 11:19 AM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> AT91_ID_SYS as virq is incorrect because of spare irq support which
> introduces NR_IRQS_LEGACY offset. It modifies rtc-at91sam9 driver in
> order to get irq from resources.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

And pushed to at91-fices branch for 3.6

Thanks,

> ---
>  arch/arm/mach-at91/at91sam9260_devices.c |  6 +++++-
>  arch/arm/mach-at91/at91sam9261_devices.c |  6 +++++-
>  arch/arm/mach-at91/at91sam9263_devices.c | 10 ++++++++--
>  arch/arm/mach-at91/at91sam9g45_devices.c |  6 +++++-
>  arch/arm/mach-at91/at91sam9rl_devices.c  |  6 +++++-
>  drivers/rtc/rtc-at91sam9.c               | 22 +++++++++++++++-------
>  6 files changed, 43 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
> index 7b9c2ba..bce572a 100644
> --- a/arch/arm/mach-at91/at91sam9260_devices.c
> +++ b/arch/arm/mach-at91/at91sam9260_devices.c
> @@ -726,6 +726,8 @@ static struct resource rtt_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	},
>  };
>  
> @@ -744,10 +746,12 @@ static void __init at91_add_device_rtt_rtc(void)
>  	 * The second resource is needed:
>  	 * GPBR will serve as the storage for RTC time offset
>  	 */
> -	at91sam9260_rtt_device.num_resources = 2;
> +	at91sam9260_rtt_device.num_resources = 3;
>  	rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
>  				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
>  	rtt_resources[1].end = rtt_resources[1].start + 3;
> +	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
> +	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
>  }
>  #else
>  static void __init at91_add_device_rtt_rtc(void)
> diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
> index 8df5c1b..bc2590d 100644
> --- a/arch/arm/mach-at91/at91sam9261_devices.c
> +++ b/arch/arm/mach-at91/at91sam9261_devices.c
> @@ -609,6 +609,8 @@ static struct resource rtt_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	}
>  };
>  
> @@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void)
>  	 * The second resource is needed:
>  	 * GPBR will serve as the storage for RTC time offset
>  	 */
> -	at91sam9261_rtt_device.num_resources = 2;
> +	at91sam9261_rtt_device.num_resources = 3;
>  	rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
>  				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
>  	rtt_resources[1].end = rtt_resources[1].start + 3;
> +	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
> +	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
>  }
>  #else
>  static void __init at91_add_device_rtt_rtc(void)
> diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
> index eb6bbf8..9b6ca73 100644
> --- a/arch/arm/mach-at91/at91sam9263_devices.c
> +++ b/arch/arm/mach-at91/at91sam9263_devices.c
> @@ -990,6 +990,8 @@ static struct resource rtt0_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	}
>  };
>  
> @@ -1006,6 +1008,8 @@ static struct resource rtt1_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	}
>  };
>  
> @@ -1027,14 +1031,14 @@ static void __init at91_add_device_rtt_rtc(void)
>  		 * The second resource is needed only for the chosen RTT:
>  		 * GPBR will serve as the storage for RTC time offset
>  		 */
> -		at91sam9263_rtt0_device.num_resources = 2;
> +		at91sam9263_rtt0_device.num_resources = 3;
>  		at91sam9263_rtt1_device.num_resources = 1;
>  		pdev = &at91sam9263_rtt0_device;
>  		r = rtt0_resources;
>  		break;
>  	case 1:
>  		at91sam9263_rtt0_device.num_resources = 1;
> -		at91sam9263_rtt1_device.num_resources = 2;
> +		at91sam9263_rtt1_device.num_resources = 3;
>  		pdev = &at91sam9263_rtt1_device;
>  		r = rtt1_resources;
>  		break;
> @@ -1047,6 +1051,8 @@ static void __init at91_add_device_rtt_rtc(void)
>  	pdev->name = "rtc-at91sam9";
>  	r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
>  	r[1].end = r[1].start + 3;
> +	r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
> +	r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
>  }
>  #else
>  static void __init at91_add_device_rtt_rtc(void)
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index 0607399..1b47319 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -1293,6 +1293,8 @@ static struct resource rtt_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	}
>  };
>  
> @@ -1310,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void)
>  	 * The second resource is needed:
>  	 * GPBR will serve as the storage for RTC time offset
>  	 */
> -	at91sam9g45_rtt_device.num_resources = 2;
> +	at91sam9g45_rtt_device.num_resources = 3;
>  	rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
>  				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
>  	rtt_resources[1].end = rtt_resources[1].start + 3;
> +	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
> +	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
>  }
>  #else
>  static void __init at91_add_device_rtt_rtc(void)
> diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
> index f09fff9..b3d365d 100644
> --- a/arch/arm/mach-at91/at91sam9rl_devices.c
> +++ b/arch/arm/mach-at91/at91sam9rl_devices.c
> @@ -688,6 +688,8 @@ static struct resource rtt_resources[] = {
>  		.flags	= IORESOURCE_MEM,
>  	}, {
>  		.flags	= IORESOURCE_MEM,
> +	}, {
> +		.flags  = IORESOURCE_IRQ,
>  	}
>  };
>  
> @@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void)
>  	 * The second resource is needed:
>  	 * GPBR will serve as the storage for RTC time offset
>  	 */
> -	at91sam9rl_rtt_device.num_resources = 2;
> +	at91sam9rl_rtt_device.num_resources = 3;
>  	rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
>  				 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
>  	rtt_resources[1].end = rtt_resources[1].start + 3;
> +	rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
> +	rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
>  }
>  #else
>  static void __init at91_add_device_rtt_rtc(void)
> diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
> index 8318689..1dd61f4 100644
> --- a/drivers/rtc/rtc-at91sam9.c
> +++ b/drivers/rtc/rtc-at91sam9.c
> @@ -58,6 +58,7 @@ struct sam9_rtc {
>  	struct rtc_device	*rtcdev;
>  	u32			imr;
>  	void __iomem		*gpbr;
> +	int 			irq;
>  };
>  
>  #define rtt_readl(rtc, field) \
> @@ -292,7 +293,7 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
>  {
>  	struct resource	*r, *r_gpbr;
>  	struct sam9_rtc	*rtc;
> -	int		ret;
> +	int		ret, irq;
>  	u32		mr;
>  
>  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -302,10 +303,18 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		dev_err(&pdev->dev, "failed to get interrupt resource\n");
> +		return irq;
> +	}
> +
>  	rtc = kzalloc(sizeof *rtc, GFP_KERNEL);
>  	if (!rtc)
>  		return -ENOMEM;
>  
> +	rtc->irq = irq;
> +
>  	/* platform setup code should have handled this; sigh */
>  	if (!device_can_wakeup(&pdev->dev))
>  		device_init_wakeup(&pdev->dev, 1);
> @@ -345,11 +354,10 @@ static int __devinit at91_rtc_probe(struct platform_device *pdev)
>  	}
>  
>  	/* register irq handler after we know what name we'll use */
> -	ret = request_irq(AT91_ID_SYS, at91_rtc_interrupt,
> -				IRQF_SHARED,
> +	ret = request_irq(rtc->irq, at91_rtc_interrupt, IRQF_SHARED,
>  				dev_name(&rtc->rtcdev->dev), rtc);
>  	if (ret) {
> -		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", AT91_ID_SYS);
> +		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
>  		rtc_device_unregister(rtc->rtcdev);
>  		goto fail_register;
>  	}
> @@ -386,7 +394,7 @@ static int __devexit at91_rtc_remove(struct platform_device *pdev)
>  
>  	/* disable all interrupts */
>  	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
> -	free_irq(AT91_ID_SYS, rtc);
> +	free_irq(rtc->irq, rtc);
>  
>  	rtc_device_unregister(rtc->rtcdev);
>  
> @@ -423,7 +431,7 @@ static int at91_rtc_suspend(struct platform_device *pdev,
>  	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
>  	if (rtc->imr) {
>  		if (device_may_wakeup(&pdev->dev) && (mr & AT91_RTT_ALMIEN)) {
> -			enable_irq_wake(AT91_ID_SYS);
> +			enable_irq_wake(rtc->irq);
>  			/* don't let RTTINC cause wakeups */
>  			if (mr & AT91_RTT_RTTINCIEN)
>  				rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
> @@ -441,7 +449,7 @@ static int at91_rtc_resume(struct platform_device *pdev)
>  
>  	if (rtc->imr) {
>  		if (device_may_wakeup(&pdev->dev))
> -			disable_irq_wake(AT91_ID_SYS);
> +			disable_irq_wake(rtc->irq);
>  		mr = rtt_readl(rtc, MR);
>  		rtt_writel(rtc, MR, mr | rtc->imr);
>  	}
> 


-- 
Nicolas Ferre


From dirk.behme at de.bosch.com  Thu Aug 23 06:23:30 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 23 Aug 2012 12:23:30 +0200
Subject: [PATCH] ARM: imx6q: remove imx_src_prepare_restart() call
In-Reply-To: <1345180316-9209-1-git-send-email-shawn.guo@linaro.org>
References: <1345180316-9209-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <503604A2.3050001@de.bosch.com>

On 17.08.2012 07:11, Shawn Guo wrote:
> Currently, imx_src_prepare_restart which is called by imx6q_restart
> assumes that cpu0 must be the running cpu, so it disables all secondary
> cpus.  However this is not the case, the restart routine could possibly
> running on cpu1 or any other secondary cores.  In that case, disabling
> the cpu that runs restart routine will hang up system.
> 
> Also it turns out that everything that is done by imx_src_prepare_restart
> is not really necessary, because the watchdog reset will have those
> registers reset properly.  So let's remove the imx_src_prepare_restart
> call completely.
> 
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Tested on a i.MX6 SabreLite board together with the patch 'ARM: fix 
cpu_relax() in case of doing dmb':

Tested-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk

> ---
>  arch/arm/mach-imx/mach-imx6q.c          |    2 --
>  arch/arm/mach-imx/src.c                 |   13 -------------
>  arch/arm/plat-mxc/include/mach/common.h |    1 -
>  3 files changed, 0 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 5ec0608..d9b0614 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -48,8 +48,6 @@ void imx6q_restart(char mode, const char *cmd)
>  	if (!wdog_base)
>  		goto soft;
>  
> -	imx_src_prepare_restart();
> -
>  	/* enable wdog */
>  	writew_relaxed(1 << 2, wdog_base);
>  	/* write twice to ensure the request will not get ignored */
> diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
> index e15f155..900b3c1 100644
> --- a/arch/arm/mach-imx/src.c
> +++ b/arch/arm/mach-imx/src.c
> @@ -43,19 +43,6 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
>  		       src_base + SRC_GPR1 + cpu * 8);
>  }
>  
> -void imx_src_prepare_restart(void)
> -{
> -	u32 val;
> -
> -	/* clear enable bits of secondary cores */
> -	val = readl_relaxed(src_base + SRC_SCR);
> -	val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
> -	writel_relaxed(val, src_base + SRC_SCR);
> -
> -	/* clear persistent entry register of primary core */
> -	writel_relaxed(0, src_base + SRC_GPR1);
> -}
> -
>  void __init imx_src_init(void)
>  {
>  	struct device_node *np;
> diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> index 7128e97..e94073f 100644
> --- a/arch/arm/plat-mxc/include/mach/common.h
> +++ b/arch/arm/plat-mxc/include/mach/common.h
> @@ -133,7 +133,6 @@ static inline void imx_smp_prepare(void) {}
>  extern void imx_enable_cpu(int cpu, bool enable);
>  extern void imx_set_cpu_jump(int cpu, void *jump_addr);
>  extern void imx_src_init(void);
> -extern void imx_src_prepare_restart(void);
>  extern void imx_gpc_init(void);
>  extern void imx_gpc_pre_suspend(void);
>  extern void imx_gpc_post_resume(void);



From dirk.behme at de.bosch.com  Thu Aug 23 06:23:45 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Thu, 23 Aug 2012 12:23:45 +0200
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <503604B1.7030207@de.bosch.com>

On 22.08.2012 16:52, Shawn Guo wrote:
> There is an issue reported on imx6q restart function.  The issue is only
> seen with the image building ARMv7 and ARMv6 together, where cpu_relax()
> is define to do dmb.  It's been root-caused by Russell as below.
> 
> Russell King - ARM Linux wrote:
>> I suspect having this dmb inside cpu_relax() is flooding the
>> interconnects with traffic, which then prevents other CPUs getting
>> a look-in (maybe there's no fairness when it comes to dmb's.
> 
> Fix the issue by insert a few NOPs into cpu_relax() where doing dmb.
> 
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Tested on a i.MX6 SabreLite board together with the patch 'ARM: imx6q: 
remove imx_src_prepare_restart() call':

Tested-by: Dirk Behme <dirk.behme at de.bosch.com>

Thanks

Dirk

> ---
>  arch/arm/include/asm/processor.h |    9 ++++++++-
>  1 files changed, 8 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index 99afa74..7cc67ce 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
>  unsigned long get_wchan(struct task_struct *p);
>  
>  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> -#define cpu_relax()			smp_mb()
> +#define cpu_relax()		do {					\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\
> +					smp_mb();			\
> +				} while (0)
>  #else
>  #define cpu_relax()			barrier()
>  #endif



From alan at linux.intel.com  Thu Aug 23 06:53:00 2012
From: alan at linux.intel.com (Alan Cox)
Date: Thu, 23 Aug 2012 11:53:00 +0100
Subject: [PATCHv4 3/9] serial: vt8500: Add devicetree support for
 vt8500-serial
In-Reply-To: <1345707346-9035-4-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <1345707346-9035-4-git-send-email-linux@prisktech.co.nz>
Message-ID: <20120823115300.5fdb5cd1@bob.linux.org.uk>

On Thu, 23 Aug 2012 19:35:39 +1200
Tony Prisk <linux at prisktech.co.nz> wrote:

> Increase vt8500_max_ports to 6 as the WM8505 as 6 available uarts.
> Use devicetree port id as primary addressing for ports but allow
> auto-allocation if id not specified.

Acked-by: Alan Cox <alan at linux.intel.com>

for the serial bits


From balbi at ti.com  Thu Aug 23 06:32:40 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:40 +0300
Subject: [PATCH v3 00/23] OMAP UART patches
Message-ID: <1345717983-18179-1-git-send-email-balbi@ti.com>

Hi guys,

here's v3 and hopefully final version of this series. A whole bunch of new
patches added but the good thing is that now I had another engineer's help to
test, so he's got his Tested-by in all patches.

Changes since v2:
	. Added a bunch of new patches
	. Fixed a problem where we would always return IRQ_NONE even though we
		handled IRQ

Changes since v1:
        . improved commit log on patch 9/13 (formerly 10/13)
        . removed patch 2/13
        . added a new patch switching from spin_lock_irqsave() to spin_lock and
                spin_unlock_irqrestore to spin_unlock

Alan, if you prefer in pull request form, here it is:

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart

for you to fetch changes up to a29230f14d8466c9b8c25171715378bf52189453:

  serial: omap: enable RX and TX FIFO usage (2012-08-23 09:25:16 +0300)

----------------------------------------------------------------
Felipe Balbi (20):
      serial: omap: define and use to_uart_omap_port()
      serial: omap: define helpers for pdata function pointers
      serial: omap: don't access the platform_device
      serial: omap: drop DMA support
      serial: add OMAP-specific defines
      serial: omap: simplify IRQ handling
      serial: omap: refactor receive_chars() into rdi/rlsi handlers
      serial: omap: move THRE check to transmit_chars()
      serial: omap: stick to put_autosuspend
      serial: omap: set dev->drvdata before enabling pm_runtime
      serial: omap: drop unnecessary check from remove
      serial: omap: make sure to suspend device before remove
      serial: omap: don't save IRQ flags on hardirq
      serial: omap: optimization with section annotations
      serial: omap: drop "inline" from IRQ handler prototype
      serial: omap: implement set_wake
      serial: omap: make sure to put() on poll_get_char
      serial: omap: remove unnecessary header and add a missing one
      serial: omap: move uart_omap_port definition to C file
      serial: omap: enable RX and TX FIFO usage

Ruchika Kharwar (2):
      serial: omap: fix sequence of pm_runtime_* calls.
      serial: omap: unlock the port lock

Vikram Pandita (1):
      serial: omap: fix software flow control

 arch/arm/mach-omap2/serial.c                  |  15 +-
 arch/arm/plat-omap/include/plat/omap-serial.h |  47 +-
 drivers/tty/serial/omap-serial.c              | 808 ++++++++++----------------
 include/linux/serial_reg.h                    |   4 +
 4 files changed, 330 insertions(+), 544 deletions(-)

-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:42 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:42 +0300
Subject: [PATCH v3 02/23] serial: omap: define helpers for pdata function
 pointers
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-3-git-send-email-balbi@ti.com>

this patch is in preparation to a few other changes
which will align on the prototype for function
pointers passed through pdata.

It also helps cleaning up the driver a little by
agregating checks for pdata in a single location.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 66 ++++++++++++++++++++++++++++------------
 1 file changed, 47 insertions(+), 19 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 5c0d0bc..6814a26 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -101,6 +101,40 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 	serial_out(up, UART_FCR, 0);
 }
 
+static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (!pdata->get_context_loss_count)
+		return 0;
+
+	return pdata->get_context_loss_count(&up->pdev->dev);
+}
+
+static void serial_omap_set_forceidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_forceidle)
+		pdata->set_forceidle(up->pdev);
+}
+
+static void serial_omap_set_noidle(struct uart_omap_port *up)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->set_noidle)
+		pdata->set_noidle(up->pdev);
+}
+
+static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
+{
+	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+
+	if (pdata->enable_wakeup)
+		pdata->enable_wakeup(up->pdev, enable);
+}
+
 /*
  * serial_omap_get_divisor - calculate divisor value
  * @port: uart port info
@@ -177,8 +211,8 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata && pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+	if (!up->use_dma && pdata)
+		serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(&up->pdev->dev);
 	pm_runtime_put_autosuspend(&up->pdev->dev);
@@ -308,7 +342,6 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
 	int ret = 0;
@@ -316,8 +349,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	if (!up->use_dma) {
 		pm_runtime_get_sync(&up->pdev->dev);
 		serial_omap_enable_ier_thri(up);
-		if (pdata && pdata->set_noidle)
-			pdata->set_noidle(up->pdev);
+		serial_omap_set_noidle(up);
 		pm_runtime_mark_last_busy(&up->pdev->dev);
 		pm_runtime_put_autosuspend(&up->pdev->dev);
 		return;
@@ -1648,28 +1680,26 @@ static int serial_omap_runtime_suspend(struct device *dev)
 	if (!up)
 		return -EINVAL;
 
-	if (!pdata || !pdata->enable_wakeup)
+	if (!pdata)
 		return 0;
 
-	if (pdata->get_context_loss_count)
-		up->context_loss_cnt = pdata->get_context_loss_count(dev);
+	up->context_loss_cnt = serial_omap_get_context_loss_count(up);
 
 	if (device_may_wakeup(dev)) {
 		if (!up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, true);
+			serial_omap_enable_wakeup(up, true);
 			up->wakeups_enabled = true;
 		}
 	} else {
 		if (up->wakeups_enabled) {
-			pdata->enable_wakeup(up->pdev, false);
+			serial_omap_enable_wakeup(up, false);
 			up->wakeups_enabled = false;
 		}
 	}
 
 	/* Errata i291 */
-	if (up->use_dma && pdata->set_forceidle &&
-			(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		pdata->set_forceidle(up->pdev);
+	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
+		serial_omap_set_forceidle(up);
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
@@ -1683,17 +1713,15 @@ static int serial_omap_runtime_resume(struct device *dev)
 	struct omap_uart_port_info *pdata = dev->platform_data;
 
 	if (up && pdata) {
-		if (pdata->get_context_loss_count) {
-			u32 loss_cnt = pdata->get_context_loss_count(dev);
+			u32 loss_cnt = serial_omap_get_context_loss_count(up);
 
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
-		}
 
 		/* Errata i291 */
-		if (up->use_dma && pdata->set_noidle &&
-				(up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-			pdata->set_noidle(up->pdev);
+		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
+				up->use_dma)
+			serial_omap_set_noidle(up);
 
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:43 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:43 +0300
Subject: [PATCH v3 03/23] serial: omap: don't access the platform_device
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-4-git-send-email-balbi@ti.com>

The driver doesn't need to know about its platform_device.

Everything the driver needs can be done through the
struct device pointer. In case we need to use the
OMAP-specific PM function pointers, those can make
sure to find the device's platform_device pointer
so they can find the struct omap_device through
pdev->archdata field.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/mach-omap2/serial.c                  |  15 ++--
 arch/arm/plat-omap/include/plat/omap-serial.h |  10 +--
 drivers/tty/serial/omap-serial.c              | 124 +++++++++++++-------------
 3 files changed, 76 insertions(+), 73 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c7..8f07841 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
 };
 
 #ifdef CONFIG_PM
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	if (!od)
@@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
  * in Smartidle Mode When Configured for DMA Operations.
  * WA: configure uart in force idle mode.
  */
-static void omap_uart_set_noidle(struct platform_device *pdev)
+static void omap_uart_set_noidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
 	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
 }
 
-static void omap_uart_set_smartidle(struct platform_device *pdev)
+static void omap_uart_set_smartidle(struct device *dev)
 {
+	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 	u8 idlemode;
 
@@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev)
 }
 
 #else
-static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
+static void omap_uart_enable_wakeup(struct device *dev, bool enable)
 {}
-static void omap_uart_set_noidle(struct platform_device *pdev) {}
-static void omap_uart_set_smartidle(struct platform_device *pdev) {}
+static void omap_uart_set_noidle(struct device *dev) {}
+static void omap_uart_set_smartidle(struct device *dev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index f3b35d9..743ac80 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -18,7 +18,7 @@
 #define __OMAP_SERIAL_H__
 
 #include <linux/serial_core.h>
-#include <linux/platform_device.h>
+#include <linux/device.h>
 #include <linux/pm_qos.h>
 
 #include <plat/mux.h>
@@ -71,9 +71,9 @@ struct omap_uart_port_info {
 	unsigned int		dma_rx_poll_rate;
 
 	int (*get_context_loss_count)(struct device *);
-	void (*set_forceidle)(struct platform_device *);
-	void (*set_noidle)(struct platform_device *);
-	void (*enable_wakeup)(struct platform_device *, bool);
+	void (*set_forceidle)(struct device *);
+	void (*set_noidle)(struct device *);
+	void (*enable_wakeup)(struct device *, bool);
 };
 
 struct uart_omap_dma {
@@ -105,7 +105,7 @@ struct uart_omap_dma {
 struct uart_omap_port {
 	struct uart_port	port;
 	struct uart_omap_dma	uart_dma;
-	struct platform_device	*pdev;
+	struct device		*dev;
 
 	unsigned char		ier;
 	unsigned char		lcr;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6814a26..6ab3582 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -103,36 +103,36 @@ static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 
 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (!pdata->get_context_loss_count)
 		return 0;
 
-	return pdata->get_context_loss_count(&up->pdev->dev);
+	return pdata->get_context_loss_count(up->dev);
 }
 
 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_forceidle)
-		pdata->set_forceidle(up->pdev);
+		pdata->set_forceidle(up->dev);
 }
 
 static void serial_omap_set_noidle(struct uart_omap_port *up)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->set_noidle)
-		pdata->set_noidle(up->pdev);
+		pdata->set_noidle(up->dev);
 }
 
 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 {
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (pdata->enable_wakeup)
-		pdata->enable_wakeup(up->pdev, enable);
+		pdata->enable_wakeup(up->dev, enable);
 }
 
 /*
@@ -168,8 +168,8 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 		omap_free_dma(up->uart_dma.rx_dma_channel);
 		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
 		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 }
 
@@ -179,16 +179,16 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
+	struct omap_uart_port_info *pdata = up->dev->platform_data;
 
 	if (up->use_dma &&
 		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
@@ -201,11 +201,11 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		omap_stop_dma(up->uart_dma.tx_dma_channel);
 		omap_free_dma(up->uart_dma.tx_dma_channel);
 		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 	}
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
 		up->ier &= ~UART_IER_THRI;
 		serial_out(up, UART_IER, up->ier);
@@ -214,22 +214,22 @@ static void serial_omap_stop_tx(struct uart_port *port)
 	if (!up->use_dma && pdata)
 		serial_omap_set_forceidle(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	if (up->use_dma)
 		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static inline void receive_chars(struct uart_omap_port *up,
@@ -347,11 +347,11 @@ static void serial_omap_start_tx(struct uart_port *port)
 	int ret = 0;
 
 	if (!up->use_dma) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		serial_omap_enable_ier_thri(up);
 		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return;
 	}
 
@@ -361,7 +361,7 @@ static void serial_omap_start_tx(struct uart_port *port)
 	xmit = &up->port.state->xmit;
 
 	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
 				"UART Tx DMA",
 				(void *)uart_tx_dma_callback, up,
@@ -444,11 +444,11 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	unsigned int iir, lsr;
 	unsigned long flags;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
 	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(&up->pdev->dev);
-		pm_runtime_put_autosuspend(&up->pdev->dev);
+		pm_runtime_mark_last_busy(up->dev);
+		pm_runtime_put_autosuspend(up->dev);
 		return IRQ_NONE;
 	}
 
@@ -472,8 +472,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 		transmit_chars(up);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	up->port_activity = jiffies;
 	return IRQ_HANDLED;
@@ -485,12 +485,12 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return ret;
 }
 
@@ -500,9 +500,9 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 	unsigned int status;
 	unsigned int ret = 0;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -534,11 +534,11 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	if (mctrl & TIOCM_LOOP)
 		mcr |= UART_MCR_LOOP;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -547,7 +547,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 	if (break_state == -1)
 		up->lcr |= UART_LCR_SBC;
@@ -555,7 +555,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -574,7 +574,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Clear the FIFO buffers and disable them.
 	 * (they will be reenabled in set_termios())
@@ -630,8 +630,8 @@ static int serial_omap_startup(struct uart_port *port)
 	/* Enable module level wake up */
 	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
 	return 0;
 }
@@ -643,7 +643,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	/*
 	 * Disable interrupts from this port
 	 */
@@ -678,7 +678,7 @@ static void serial_omap_shutdown(struct uart_port *port)
 		up->uart_dma.rx_buf = NULL;
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -807,7 +807,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	 * Ok, we're now changing the port state. Do it with
 	 * interrupts disabled.
 	 */
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	spin_lock_irqsave(&up->port.lock, flags);
 
 	/*
@@ -956,7 +956,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -969,7 +969,7 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 	efr = serial_in(up, UART_EFR);
 	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
@@ -980,14 +980,14 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 	serial_out(up, UART_EFR, efr);
 	serial_out(up, UART_LCR, 0);
 
-	if (!device_may_wakeup(&up->pdev->dev)) {
+	if (!device_may_wakeup(up->dev)) {
 		if (!state)
-			pm_runtime_forbid(&up->pdev->dev);
+			pm_runtime_forbid(up->dev);
 		else
-			pm_runtime_allow(&up->pdev->dev);
+			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -1066,10 +1066,10 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -1077,13 +1077,13 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 	status = serial_in(up, UART_LSR);
 	if (!(status & UART_LSR_DR))
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(&up->pdev->dev);
+	pm_runtime_put(up->dev);
 	return status;
 }
 
@@ -1112,7 +1112,7 @@ serial_omap_console_write(struct console *co, const char *s,
 	unsigned int ier;
 	int locked = 1;
 
-	pm_runtime_get_sync(&up->pdev->dev);
+	pm_runtime_get_sync(up->dev);
 
 	local_irq_save(flags);
 	if (up->port.sysrq)
@@ -1146,8 +1146,8 @@ serial_omap_console_write(struct console *co, const char *s,
 	if (up->msr_saved_flags)
 		check_modem_status(up);
 
-	pm_runtime_mark_last_busy(&up->pdev->dev);
-	pm_runtime_put_autosuspend(&up->pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	if (locked)
 		spin_unlock(&up->port.lock);
 	local_irq_restore(flags);
@@ -1309,7 +1309,7 @@ static int serial_omap_start_rxdma(struct uart_omap_port *up)
 	int ret = 0;
 
 	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(&up->pdev->dev);
+		pm_runtime_get_sync(up->dev);
 		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
 				"UART Rx DMA",
 				(void *)uart_rx_dma_callback, up,
@@ -1421,7 +1421,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 		break;
 	default:
-		dev_warn(&up->pdev->dev,
+		dev_warn(up->dev,
 			"Unknown %s revision, defaulting to highest\n",
 			up->name);
 		/* highest possible revision */
@@ -1502,7 +1502,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (!up)
 		return -ENOMEM;
 
-	up->pdev = pdev;
+	up->dev = &pdev->dev;
 	up->port.dev = &pdev->dev;
 	up->port.type = PORT_OMAP;
 	up->port.iotype = UPIO_MEM;
@@ -1599,7 +1599,7 @@ static int serial_omap_remove(struct platform_device *dev)
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
 	if (up) {
-		pm_runtime_disable(&up->pdev->dev);
+		pm_runtime_disable(up->dev);
 		uart_remove_one_port(&serial_omap_reg, &up->port);
 		pm_qos_remove_request(&up->pm_qos_request);
 	}
@@ -1634,7 +1634,7 @@ static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
 		timeout--;
 		if (!timeout) {
 			/* Should *never* happen. we warn and carry on */
-			dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
+			dev_crit(up->dev, "Errata i202: timedout %x\n",
 						serial_in(up, UART_LSR));
 			break;
 		}
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:41 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:41 +0300
Subject: [PATCH v3 01/23] serial: omap: define and use to_uart_omap_port()
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-2-git-send-email-balbi@ti.com>

current code only works because struct uart_port
is the first member on the uart_omap_port structure.

If, for whatever reason, someone puts another
member as the first of the structure, that cast
won't work anymore. In order to be safe, let's use
a container_of() which, for now, gets optimized into
a cast anyway.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h |  2 ++
 drivers/tty/serial/omap-serial.c              | 36 +++++++++++++--------------
 2 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725..f3b35d9 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -137,4 +137,6 @@ struct uart_omap_port {
 	struct work_struct	qos_work;
 };
 
+#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
+
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d3cda0c..5c0d0bc 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -141,7 +141,7 @@ static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 
 static void serial_omap_enable_ms(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 
@@ -153,7 +153,7 @@ static void serial_omap_enable_ms(struct uart_port *port)
 
 static void serial_omap_stop_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 
 	if (up->use_dma &&
@@ -186,7 +186,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 
 static void serial_omap_stop_rx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	if (up->use_dma)
@@ -307,7 +307,7 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 
 static void serial_omap_start_tx(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
 	struct circ_buf *xmit;
 	unsigned int start;
@@ -449,7 +449,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 
 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	unsigned int ret = 0;
 
@@ -464,7 +464,7 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 
 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 	unsigned int ret = 0;
 
@@ -487,7 +487,7 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char mcr = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
@@ -511,7 +511,7 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
@@ -528,7 +528,7 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 
 static int serial_omap_startup(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 	int retval;
 
@@ -606,7 +606,7 @@ static int serial_omap_startup(struct uart_port *port)
 
 static void serial_omap_shutdown(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned long flags = 0;
 
 	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
@@ -721,7 +721,7 @@ static void
 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 			struct ktermios *old)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char cval = 0;
 	unsigned char efr = 0;
 	unsigned long flags = 0;
@@ -932,7 +932,7 @@ static void
 serial_omap_pm(struct uart_port *port, unsigned int state,
 	       unsigned int oldstate)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned char efr;
 
 	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
@@ -971,7 +971,7 @@ static int serial_omap_request_port(struct uart_port *port)
 
 static void serial_omap_config_port(struct uart_port *port, int flags)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 							up->port.line);
@@ -989,7 +989,7 @@ serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 static const char *
 serial_omap_type(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 	return up->name;
@@ -1032,7 +1032,7 @@ static inline void wait_for_xmitr(struct uart_omap_port *up)
 
 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(&up->pdev->dev);
 	wait_for_xmitr(up);
@@ -1042,7 +1042,7 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 
 static int serial_omap_poll_get_char(struct uart_port *port)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 	unsigned int status;
 
 	pm_runtime_get_sync(&up->pdev->dev);
@@ -1065,7 +1065,7 @@ static struct uart_driver serial_omap_reg;
 
 static void serial_omap_console_putchar(struct uart_port *port, int ch)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)port;
+	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
@@ -1341,7 +1341,7 @@ static void serial_omap_continue_tx(struct uart_omap_port *up)
 
 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
 {
-	struct uart_omap_port *up = (struct uart_omap_port *)data;
+	struct uart_omap_port *up = data;
 	struct circ_buf *xmit = &up->port.state->xmit;
 
 	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:45 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:45 +0300
Subject: [PATCH v3 05/23] serial: add OMAP-specific defines
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-6-git-send-email-balbi@ti.com>

OMAP has some extra Interrupt types which can
be really useful for SW. Let's define them
so we can later use those in OMAP's serial driver.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 include/linux/serial_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 8ce70d7..5ed325e 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -40,6 +40,10 @@
 
 #define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
 
+#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
+
 #define UART_FCR	2	/* Out: FIFO Control Register */
 #define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
 #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:44 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:44 +0300
Subject: [PATCH v3 04/23] serial: omap: drop DMA support
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-5-git-send-email-balbi@ti.com>

The current support is known to be broken and
a later patch will come re-adding it using
dma engine API.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 330 ++-------------------------------------
 1 file changed, 12 insertions(+), 318 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 6ab3582..16808b6 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -33,14 +33,12 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/io.h>
-#include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/serial_core.h>
 #include <linux/irq.h>
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 
-#include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/omap-serial.h>
 
@@ -74,9 +72,6 @@
 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 
 /* Forward declaration of functions */
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
-static void serial_omap_rxdma_poll(unsigned long uart_no);
-static int serial_omap_start_rxdma(struct uart_omap_port *up);
 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 
 static struct workqueue_struct *serial_omap_uart_wq;
@@ -160,19 +155,6 @@ serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 	return port->uartclk/(baud * divisor);
 }
 
-static void serial_omap_stop_rxdma(struct uart_omap_port *up)
-{
-	if (up->uart_dma.rx_dma_used) {
-		del_timer(&up->uart_dma.rx_timer);
-		omap_stop_dma(up->uart_dma.rx_dma_channel);
-		omap_free_dma(up->uart_dma.rx_dma_channel);
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_used = false;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
-}
-
 static void serial_omap_enable_ms(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
@@ -188,22 +170,6 @@ static void serial_omap_enable_ms(struct uart_port *port)
 static void serial_omap_stop_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct omap_uart_port_info *pdata = up->dev->platform_data;
-
-	if (up->use_dma &&
-		up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
-		/*
-		 * Check if dma is still active. If yes do nothing,
-		 * return. Else stop dma
-		 */
-		if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
-			return;
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		omap_free_dma(up->uart_dma.tx_dma_channel);
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-	}
 
 	pm_runtime_get_sync(up->dev);
 	if (up->ier & UART_IER_THRI) {
@@ -211,8 +177,7 @@ static void serial_omap_stop_tx(struct uart_port *port)
 		serial_out(up, UART_IER, up->ier);
 	}
 
-	if (!up->use_dma && pdata)
-		serial_omap_set_forceidle(up);
+	serial_omap_set_forceidle(up);
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
@@ -223,8 +188,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	struct uart_omap_port *up = to_uart_omap_port(port);
 
 	pm_runtime_get_sync(up->dev);
-	if (up->use_dma)
-		serial_omap_stop_rxdma(up);
 	up->ier &= ~UART_IER_RLSI;
 	up->port.read_status_mask &= ~UART_LSR_DR;
 	serial_out(up, UART_IER, up->ier);
@@ -342,67 +305,12 @@ static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 static void serial_omap_start_tx(struct uart_port *port)
 {
 	struct uart_omap_port *up = to_uart_omap_port(port);
-	struct circ_buf *xmit;
-	unsigned int start;
-	int ret = 0;
-
-	if (!up->use_dma) {
-		pm_runtime_get_sync(up->dev);
-		serial_omap_enable_ier_thri(up);
-		serial_omap_set_noidle(up);
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return;
-	}
-
-	if (up->uart_dma.tx_dma_used)
-		return;
-
-	xmit = &up->port.state->xmit;
-
-	if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_tx,
-				"UART Tx DMA",
-				(void *)uart_tx_dma_callback, up,
-				&(up->uart_dma.tx_dma_channel));
 
-		if (ret < 0) {
-			serial_omap_enable_ier_thri(up);
-			return;
-		}
-	}
-	spin_lock(&(up->uart_dma.tx_lock));
-	up->uart_dma.tx_dma_used = true;
-	spin_unlock(&(up->uart_dma.tx_lock));
-
-	start = up->uart_dma.tx_buf_dma_phys +
-				(xmit->tail & (UART_XMIT_SIZE - 1));
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys +
-			UART_XMIT_SIZE) - start;
-
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
+	pm_runtime_get_sync(up->dev);
+	serial_omap_enable_ier_thri(up);
+	serial_omap_set_noidle(up);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static unsigned int check_modem_status(struct uart_omap_port *up)
@@ -455,16 +363,8 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	spin_lock_irqsave(&up->port.lock, flags);
 	lsr = serial_in(up, UART_LSR);
 	if (iir & UART_IIR_RLSI) {
-		if (!up->use_dma) {
-			if (lsr & UART_LSR_DR)
-				receive_chars(up, &lsr);
-		} else {
-			up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-			if ((serial_omap_start_rxdma(up) != 0) &&
-					(lsr & UART_LSR_DR))
-				receive_chars(up, &lsr);
-		}
+		if (lsr & UART_LSR_DR)
+			receive_chars(up, &lsr);
 	}
 
 	check_modem_status(up);
@@ -605,20 +505,6 @@ static int serial_omap_startup(struct uart_port *port)
 	spin_unlock_irqrestore(&up->port.lock, flags);
 
 	up->msr_saved_flags = 0;
-	if (up->use_dma) {
-		free_page((unsigned long)up->port.state->xmit.buf);
-		up->port.state->xmit.buf = dma_alloc_coherent(NULL,
-			UART_XMIT_SIZE,
-			(dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
-			0);
-		init_timer(&(up->uart_dma.rx_timer));
-		up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
-		up->uart_dma.rx_timer.data = up->port.line;
-		/* Currently the buffer size is 4KB. Can increase it */
-		up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
-			up->uart_dma.rx_buf_size,
-			(dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
-	}
 	/*
 	 * Finally, enable interrupts. Note: Modem status interrupts
 	 * are set via set_termios(), which will be occurring imminently
@@ -666,17 +552,6 @@ static void serial_omap_shutdown(struct uart_port *port)
 	 */
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
-	if (up->use_dma) {
-		dma_free_coherent(up->port.dev,
-			UART_XMIT_SIZE,	up->port.state->xmit.buf,
-			up->uart_dma.tx_buf_dma_phys);
-		up->port.state->xmit.buf = NULL;
-		serial_omap_stop_rx(port);
-		dma_free_coherent(up->port.dev,
-			up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
-			up->uart_dma.rx_buf_dma_phys);
-		up->uart_dma.rx_buf = NULL;
-	}
 
 	pm_runtime_put(up->dev);
 	free_irq(up->port.irq, up);
@@ -800,8 +675,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 			UART_FCR_ENABLE_FIFO;
-	if (up->use_dma)
-		up->fcr |= UART_FCR_DMA_SELECT;
 
 	/*
 	 * Ok, we're now changing the port state. Do it with
@@ -877,14 +750,9 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 
-	if (up->use_dma) {
-		serial_out(up, UART_TI752_TLR, 0);
-		up->scr |= UART_FCR_TRIGGER_4;
-	} else {
-		/* Set receive FIFO threshold to 1 byte */
-		up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
-		up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
-	}
+	/* Set receive FIFO threshold to 1 byte */
+	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
+	up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
 
 	serial_out(up, UART_FCR, up->fcr);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
@@ -1253,149 +1121,6 @@ static int serial_omap_resume(struct device *dev)
 }
 #endif
 
-static void serial_omap_rxdma_poll(unsigned long uart_no)
-{
-	struct uart_omap_port *up = ui[uart_no];
-	unsigned int curr_dma_pos, curr_transmitted_size;
-	int ret = 0;
-
-	curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
-	if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
-			     (curr_dma_pos == 0)) {
-		if (jiffies_to_msecs(jiffies - up->port_activity) <
-						up->uart_dma.rx_timeout) {
-			mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-		} else {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-		return;
-	}
-
-	curr_transmitted_size = curr_dma_pos -
-					up->uart_dma.prev_rx_dma_pos;
-	up->port.icount.rx += curr_transmitted_size;
-	tty_insert_flip_string(up->port.state->port.tty,
-			up->uart_dma.rx_buf +
-			(up->uart_dma.prev_rx_dma_pos -
-			up->uart_dma.rx_buf_dma_phys),
-			curr_transmitted_size);
-	tty_flip_buffer_push(up->port.state->port.tty);
-	up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
-	if (up->uart_dma.rx_buf_size +
-			up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
-		ret = serial_omap_start_rxdma(up);
-		if (ret < 0) {
-			serial_omap_stop_rxdma(up);
-			up->ier |= (UART_IER_RDI | UART_IER_RLSI);
-			serial_out(up, UART_IER, up->ier);
-		}
-	} else  {
-		mod_timer(&up->uart_dma.rx_timer, jiffies +
-			usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	}
-	up->port_activity = jiffies;
-}
-
-static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	return;
-}
-
-static int serial_omap_start_rxdma(struct uart_omap_port *up)
-{
-	int ret = 0;
-
-	if (up->uart_dma.rx_dma_channel == -1) {
-		pm_runtime_get_sync(up->dev);
-		ret = omap_request_dma(up->uart_dma.uart_dma_rx,
-				"UART Rx DMA",
-				(void *)uart_rx_dma_callback, up,
-				&(up->uart_dma.rx_dma_channel));
-		if (ret < 0)
-			return ret;
-
-		omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-		omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC,
-				up->uart_dma.rx_buf_dma_phys, 0, 0);
-		omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.rx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_rx, 0);
-	}
-	up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.rx_dma_channel);
-	mod_timer(&up->uart_dma.rx_timer, jiffies +
-				usecs_to_jiffies(up->uart_dma.rx_poll_rate));
-	up->uart_dma.rx_dma_used = true;
-	return ret;
-}
-
-static void serial_omap_continue_tx(struct uart_omap_port *up)
-{
-	struct circ_buf *xmit = &up->port.state->xmit;
-	unsigned int start = up->uart_dma.tx_buf_dma_phys
-			+ (xmit->tail & (UART_XMIT_SIZE - 1));
-
-	if (uart_circ_empty(xmit))
-		return;
-
-	up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
-	/*
-	 * It is a circular buffer. See if the buffer has wounded back.
-	 * If yes it will have to be transferred in two separate dma
-	 * transfers
-	 */
-	if (start + up->uart_dma.tx_buf_size >=
-			up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
-		up->uart_dma.tx_buf_size =
-			(up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
-	omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_CONSTANT,
-				up->uart_dma.uart_base, 0, 0);
-	omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
-				OMAP_DMA_AMODE_POST_INC, start, 0, 0);
-	omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
-				OMAP_DMA_DATA_TYPE_S8,
-				up->uart_dma.tx_buf_size, 1,
-				OMAP_DMA_SYNC_ELEMENT,
-				up->uart_dma.uart_dma_tx, 0);
-	/* FIXME: Cache maintenance needed here? */
-	omap_start_dma(up->uart_dma.tx_dma_channel);
-}
-
-static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
-	struct uart_omap_port *up = data;
-	struct circ_buf *xmit = &up->port.state->xmit;
-
-	xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
-			(UART_XMIT_SIZE - 1);
-	up->port.icount.tx += up->uart_dma.tx_buf_size;
-
-	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-		uart_write_wakeup(&up->port);
-
-	if (uart_circ_empty(xmit)) {
-		spin_lock(&(up->uart_dma.tx_lock));
-		serial_omap_stop_tx(&up->port);
-		up->uart_dma.tx_dma_used = false;
-		spin_unlock(&(up->uart_dma.tx_lock));
-	} else {
-		omap_stop_dma(up->uart_dma.tx_dma_channel);
-		serial_omap_continue_tx(up);
-	}
-	up->port_activity = jiffies;
-	return;
-}
-
 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 {
 	u32 mvr, scheme;
@@ -1465,7 +1190,7 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 static int serial_omap_probe(struct platform_device *pdev)
 {
 	struct uart_omap_port	*up;
-	struct resource		*mem, *irq, *dma_tx, *dma_rx;
+	struct resource		*mem, *irq;
 	struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
 	int ret = -ENOSPC;
 
@@ -1490,14 +1215,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-	if (!dma_rx)
-		return -ENXIO;
-
-	dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-	if (!dma_tx)
-		return -ENXIO;
-
 	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
 	if (!up)
 		return -ENOMEM;
@@ -1541,20 +1258,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 		dev_warn(&pdev->dev, "No clock speed specified: using default:"
 						"%d\n", DEFAULT_CLK_SPEED);
 	}
-	up->uart_dma.uart_base = mem->start;
-
-	if (omap_up_info->dma_enabled) {
-		up->uart_dma.uart_dma_tx = dma_tx->start;
-		up->uart_dma.uart_dma_rx = dma_rx->start;
-		up->use_dma = 1;
-		up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
-		up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
-		up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
-		spin_lock_init(&(up->uart_dma.tx_lock));
-		spin_lock_init(&(up->uart_dma.rx_lock));
-		up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
-		up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
-	}
 
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
@@ -1697,10 +1400,6 @@ static int serial_omap_runtime_suspend(struct device *dev)
 		}
 	}
 
-	/* Errata i291 */
-	if (up->use_dma && (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
-		serial_omap_set_forceidle(up);
-
 	up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
 	schedule_work(&up->qos_work);
 
@@ -1718,11 +1417,6 @@ static int serial_omap_runtime_resume(struct device *dev)
 			if (up->context_loss_cnt != loss_cnt)
 				serial_omap_restore_context(up);
 
-		/* Errata i291 */
-		if ((up->errata & UART_ERRATA_i291_DMA_FORCEIDLE) &&
-				up->use_dma)
-			serial_omap_set_noidle(up);
-
 		up->latency = up->calc_latency;
 		schedule_work(&up->qos_work);
 	}
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:46 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:46 +0300
Subject: [PATCH v3 06/23] serial: omap: simplify IRQ handling
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-7-git-send-email-balbi@ti.com>

quite a few changes here, though they are
pretty obvious. In summary we're making sure
to detect which interrupt type we need to
handle before calling the underlying interrupt
handling procedure.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 51 ++++++++++++++++++++++++++++++----------
 1 file changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 16808b6..1e91ca6 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -350,33 +350,58 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
 	unsigned int iir, lsr;
+	unsigned int type;
 	unsigned long flags;
+	irqreturn_t ret = IRQ_NONE;
 
+	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
 	iir = serial_in(up, UART_IIR);
-	if (iir & UART_IIR_NO_INT) {
-		pm_runtime_mark_last_busy(up->dev);
-		pm_runtime_put_autosuspend(up->dev);
-		return IRQ_NONE;
-	}
+again:
+	if (iir & UART_IIR_NO_INT)
+		goto out;
 
-	spin_lock_irqsave(&up->port.lock, flags);
+	ret = IRQ_HANDLED;
 	lsr = serial_in(up, UART_LSR);
-	if (iir & UART_IIR_RLSI) {
+
+	/* extract IRQ type from IIR register */
+	type = iir & 0x3e;
+
+	switch (type) {
+	case UART_IIR_MSI:
+		check_modem_status(up);
+		break;
+	case UART_IIR_THRI:
+		if (lsr & UART_LSR_THRE)
+			transmit_chars(up);
+		break;
+	case UART_IIR_RDI:
 		if (lsr & UART_LSR_DR)
 			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RLSI:
+		if (lsr & UART_LSR_BRK_ERROR_BITS)
+			receive_chars(up, &lsr);
+		break;
+	case UART_IIR_RX_TIMEOUT:
+		receive_chars(up, &lsr);
+		break;
+	case UART_IIR_CTS_RTS_DSR:
+		iir = serial_in(up, UART_IIR);
+		goto again;
+	case UART_IIR_XOFF:
+		/* FALLTHROUGH */
+	default:
+		break;
 	}
 
-	check_modem_status(up);
-	if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
-		transmit_chars(up);
-
+out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-
 	up->port_activity = jiffies;
-	return IRQ_HANDLED;
+
+	return ret;
 }
 
 static unsigned int serial_omap_tx_empty(struct uart_port *port)
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:51 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:51 +0300
Subject: [PATCH v3 11/23] serial: omap: drop unnecessary check from remove
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-12-git-send-email-balbi@ti.com>

if platform_get_drvdata() returns NULL, that's
quite a nasty bug on the driver which we want to
catch ASAP. Otherwise, that check is hugely
unneeded.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 9f709d4..9581741 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1336,13 +1336,10 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
-	if (up) {
-		pm_runtime_disable(up->dev);
-		uart_remove_one_port(&serial_omap_reg, &up->port);
-		pm_qos_remove_request(&up->pm_qos_request);
-	}
+	pm_runtime_disable(up->dev);
+	uart_remove_one_port(&serial_omap_reg, &up->port);
+	pm_qos_remove_request(&up->pm_qos_request);
 
-	platform_set_drvdata(dev, NULL);
 	return 0;
 }
 
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:48 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:48 +0300
Subject: [PATCH v3 08/23] serial: omap: move THRE check to transmit_chars()
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-9-git-send-email-balbi@ti.com>

since all other IRQ types now do all necessary
checks inside their handlers, transmit_chars()
was the only one left expecting serial_omap_irq()
to check THRE for it. We can move THRE check to
transmit_chars() in order to make serial_omap_irq()
more uniform.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index e55f9f1..50ba51e 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,11 +195,14 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static void transmit_chars(struct uart_omap_port *up)
+static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
 	int count;
 
+	if (!(lsr & UART_LSR_THRE))
+		return;
+
 	if (up->port.x_char) {
 		serial_out(up, UART_TX, up->port.x_char);
 		up->port.icount.tx++;
@@ -369,8 +372,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 			check_modem_status(up);
 			break;
 		case UART_IIR_THRI:
-			if (lsr & UART_LSR_THRE)
-				transmit_chars(up);
+			transmit_chars(up, lsr);
 			break;
 		case UART_IIR_RX_TIMEOUT:
 			/* FALLTHROUGH */
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:50 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:50 +0300
Subject: [PATCH v3 10/23] serial: omap: set dev->drvdata before enabling
 pm_runtime
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-11-git-send-email-balbi@ti.com>

by the time we call our first pm_runtme_get_sync()
after enable pm_runtime, our resume method might
be called. To avoid problems, we must make sure
that our dev->drvdata is set correctly before
our resume method gets called.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index e07afb3..9f709d4 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1300,6 +1300,7 @@ static int serial_omap_probe(struct platform_device *pdev)
 	serial_omap_uart_wq = create_singlethread_workqueue(up->name);
 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
 
+	platform_set_drvdata(pdev, up);
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
 			omap_up_info->autosuspend_timeout);
@@ -1319,7 +1320,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
-	platform_set_drvdata(pdev, up);
 	return 0;
 
 err_add_port:
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:49 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:49 +0300
Subject: [PATCH v3 09/23] serial: omap: stick to put_autosuspend
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-10-git-send-email-balbi@ti.com>

Everytime we're done using our TTY, we want
the pm timer to be reinitilized. By sticking
to pm_runtime_pm_autosuspend() we make sure
that this will always be the case.

The idea behind this patch is to make sure we
will always reinitialize the pm timer so that
we don't fall into a situation where pm_runtime_put()
expires right away (if timer was already about to
expire when we made the call to pm_runtime_put()).

While suspending right away wouldn't cause any
issues, reinitializing the pm timer can help us
avoiding unnecessary context save & restore
operations (which are somewhat expensive) if there's
another read/write/set_termios request coming right
after. IOW, we are trying to make sure UART is still
powered up while it's still under heavy usage.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 50ba51e..e07afb3 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -164,7 +164,8 @@ static void serial_omap_enable_ms(struct uart_port *port)
 	pm_runtime_get_sync(up->dev);
 	up->ier |= UART_IER_MSI;
 	serial_out(up, UART_IER, up->ier);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_stop_tx(struct uart_port *port)
@@ -414,7 +415,8 @@ static unsigned int serial_omap_tx_empty(struct uart_port *port)
 	spin_lock_irqsave(&up->port.lock, flags);
 	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return ret;
 }
 
@@ -426,7 +428,8 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	status = check_modem_status(up);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 
 	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 
@@ -462,7 +465,8 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	up->mcr = serial_in(up, UART_MCR);
 	up->mcr |= mcr;
 	serial_out(up, UART_MCR, up->mcr);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
@@ -479,7 +483,8 @@ static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 		up->lcr &= ~UART_LCR_SBC;
 	serial_out(up, UART_LCR, up->lcr);
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_startup(struct uart_port *port)
@@ -577,7 +582,8 @@ static void serial_omap_shutdown(struct uart_port *port)
 	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 		(void) serial_in(up, UART_RX);
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	free_irq(up->port.irq, up);
 }
 
@@ -848,7 +854,8 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	serial_omap_configure_xonxoff(up, termios);
 
 	spin_unlock_irqrestore(&up->port.lock, flags);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
@@ -879,7 +886,8 @@ serial_omap_pm(struct uart_port *port, unsigned int state,
 			pm_runtime_allow(up->dev);
 	}
 
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static void serial_omap_release_port(struct uart_port *port)
@@ -961,7 +969,8 @@ static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 	pm_runtime_get_sync(up->dev);
 	wait_for_xmitr(up);
 	serial_out(up, UART_TX, ch);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 }
 
 static int serial_omap_poll_get_char(struct uart_port *port)
@@ -975,7 +984,8 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 		return NO_POLL_CHAR;
 
 	status = serial_in(up, UART_RX);
-	pm_runtime_put(up->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	return status;
 }
 
@@ -1307,7 +1317,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	if (ret != 0)
 		goto err_add_port;
 
-	pm_runtime_put(&pdev->dev);
+	pm_runtime_mark_last_busy(up->dev);
+	pm_runtime_put_autosuspend(up->dev);
 	platform_set_drvdata(pdev, up);
 	return 0;
 
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:52 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:52 +0300
Subject: [PATCH v3 12/23] serial: omap: make sure to suspend device before
 remove
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-13-git-send-email-balbi@ti.com>

before removing the driver, let's make sure
to force device into a suspended state in order
to conserve power.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 9581741..2df725b 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1336,6 +1336,7 @@ static int serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
+	pm_runtime_put_sync(up->dev);
 	pm_runtime_disable(up->dev);
 	uart_remove_one_port(&serial_omap_reg, &up->port);
 	pm_qos_remove_request(&up->pm_qos_request);
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:53 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:53 +0300
Subject: [PATCH v3 13/23] serial: omap: don't save IRQ flags on hardirq
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-14-git-send-email-balbi@ti.com>

When we're running our hardirq handler, there's
not need to disable IRQs with spin_lock_irqsave()
because IRQs are already disabled. It also makes
no difference if we save or not IRQ flags.

Switch over to simple spin_lock/spin_unlock and
drop the "flags" variable.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 2df725b..8a60212 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -350,11 +350,10 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 	struct tty_struct *tty = up->port.state->port.tty;
 	unsigned int iir, lsr;
 	unsigned int type;
-	unsigned long flags;
 	irqreturn_t ret = IRQ_NONE;
 	int max_count = 256;
 
-	spin_lock_irqsave(&up->port.lock, flags);
+	spin_lock(&up->port.lock);
 	pm_runtime_get_sync(up->dev);
 
 	do {
@@ -393,7 +392,7 @@ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 		}
 	} while (!(iir & UART_IIR_NO_INT) && max_count--);
 
-	spin_unlock_irqrestore(&up->port.lock, flags);
+	spin_unlock(&up->port.lock);
 
 	tty_flip_buffer_push(tty);
 
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:54 +0300
Subject: [PATCH v3 14/23] serial: omap: fix sequence of pm_runtime_* calls.
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-15-git-send-email-balbi@ti.com>

From: Ruchika Kharwar <ruchika at ti.com>

pm_runtime_enable() needs to be invoked before
pm_runtime_use_autosuspend(), and
pm_runtime_set_autosuspend_delay() functions.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Ruchika Kharwar <ruchika at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 8a60212..8254561 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1300,12 +1300,12 @@ static int serial_omap_probe(struct platform_device *pdev)
 	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
 
 	platform_set_drvdata(pdev, up);
+	pm_runtime_enable(&pdev->dev);
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev,
 			omap_up_info->autosuspend_timeout);
 
 	pm_runtime_irq_safe(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
 
 	omap_serial_fill_features_erratas(up);
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:55 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:55 +0300
Subject: [PATCH v3 15/23] serial: omap: optimization with section annotations
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-16-git-send-email-balbi@ti.com>

Two functions:
omap_serial_fill_features_erratas() and
of_get_uart_port_info() are only called from probe().
Marking them as __devinit gives us another
oportunity to free some code after .init.text
is done.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Ruchika Kharwar <ruchika at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 8254561..bdfd019 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1154,7 +1154,7 @@ static int serial_omap_resume(struct device *dev)
 }
 #endif
 
-static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
+static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
 {
 	u32 mvr, scheme;
 	u16 revision, major, minor;
@@ -1207,7 +1207,7 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 	}
 }
 
-static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
+static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 {
 	struct omap_uart_port_info *omap_up_info;
 
@@ -1220,7 +1220,7 @@ static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 	return omap_up_info;
 }
 
-static int serial_omap_probe(struct platform_device *pdev)
+static int __devinit serial_omap_probe(struct platform_device *pdev)
 {
 	struct uart_omap_port	*up;
 	struct resource		*mem, *irq;
@@ -1331,7 +1331,7 @@ err_port_line:
 	return ret;
 }
 
-static int serial_omap_remove(struct platform_device *dev)
+static int __devexit serial_omap_remove(struct platform_device *dev)
 {
 	struct uart_omap_port *up = platform_get_drvdata(dev);
 
@@ -1475,7 +1475,7 @@ MODULE_DEVICE_TABLE(of, omap_serial_of_match);
 
 static struct platform_driver serial_omap_driver = {
 	.probe          = serial_omap_probe,
-	.remove         = serial_omap_remove,
+	.remove         = __devexit_p(serial_omap_remove),
 	.driver		= {
 		.name	= DRIVER_NAME,
 		.pm	= &serial_omap_dev_pm_ops,
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:56 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:56 +0300
Subject: [PATCH v3 16/23] serial: omap: drop "inline" from IRQ handler
 prototype
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-17-git-send-email-balbi@ti.com>

it makes no sense to mark our IRQ handler inline
since it's passed as a function pointer when
enabling the IRQ line.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index bdfd019..ba22247 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -344,7 +344,7 @@ static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
  * @irq: uart port irq number
  * @dev_id: uart port info
  */
-static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
+static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
 	struct tty_struct *tty = up->port.state->port.tty;
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:47 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:47 +0300
Subject: [PATCH v3 07/23] serial: omap: refactor receive_chars() into rdi/rlsi
 handlers
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-8-git-send-email-balbi@ti.com>

receive_chars() was getting too big and too difficult
to follow. By splitting it into separate RDI and RSLI
handlers, we have smaller functions which are easy
to understand and only touch the pieces which they need
to touch.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 205 +++++++++++++++++++--------------------
 1 file changed, 101 insertions(+), 104 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 1e91ca6..e55f9f1 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -195,74 +195,6 @@ static void serial_omap_stop_rx(struct uart_port *port)
 	pm_runtime_put_autosuspend(up->dev);
 }
 
-static inline void receive_chars(struct uart_omap_port *up,
-		unsigned int *status)
-{
-	struct tty_struct *tty = up->port.state->port.tty;
-	unsigned int flag, lsr = *status;
-	unsigned char ch = 0;
-	int max_count = 256;
-
-	do {
-		if (likely(lsr & UART_LSR_DR))
-			ch = serial_in(up, UART_RX);
-		flag = TTY_NORMAL;
-		up->port.icount.rx++;
-
-		if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
-			/*
-			 * For statistics only
-			 */
-			if (lsr & UART_LSR_BI) {
-				lsr &= ~(UART_LSR_FE | UART_LSR_PE);
-				up->port.icount.brk++;
-				/*
-				 * We do the SysRQ and SAK checking
-				 * here because otherwise the break
-				 * may get masked by ignore_status_mask
-				 * or read_status_mask.
-				 */
-				if (uart_handle_break(&up->port))
-					goto ignore_char;
-			} else if (lsr & UART_LSR_PE) {
-				up->port.icount.parity++;
-			} else if (lsr & UART_LSR_FE) {
-				up->port.icount.frame++;
-			}
-
-			if (lsr & UART_LSR_OE)
-				up->port.icount.overrun++;
-
-			/*
-			 * Mask off conditions which should be ignored.
-			 */
-			lsr &= up->port.read_status_mask;
-
-#ifdef CONFIG_SERIAL_OMAP_CONSOLE
-			if (up->port.line == up->port.cons->index) {
-				/* Recover the break flag from console xmit */
-				lsr |= up->lsr_break_flag;
-			}
-#endif
-			if (lsr & UART_LSR_BI)
-				flag = TTY_BREAK;
-			else if (lsr & UART_LSR_PE)
-				flag = TTY_PARITY;
-			else if (lsr & UART_LSR_FE)
-				flag = TTY_FRAME;
-		}
-
-		if (uart_handle_sysrq_char(&up->port, ch))
-			goto ignore_char;
-		uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
-ignore_char:
-		lsr = serial_in(up, UART_LSR);
-	} while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
-	spin_unlock(&up->port.lock);
-	tty_flip_buffer_push(tty);
-	spin_lock(&up->port.lock);
-}
-
 static void transmit_chars(struct uart_omap_port *up)
 {
 	struct circ_buf *xmit = &up->port.state->xmit;
@@ -341,6 +273,68 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 	return status;
 }
 
+static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned int flag;
+
+	up->port.icount.rx++;
+	flag = TTY_NORMAL;
+
+	if (lsr & UART_LSR_BI) {
+		flag = TTY_BREAK;
+		lsr &= ~(UART_LSR_FE | UART_LSR_PE);
+		up->port.icount.brk++;
+		/*
+		 * We do the SysRQ and SAK checking
+		 * here because otherwise the break
+		 * may get masked by ignore_status_mask
+		 * or read_status_mask.
+		 */
+		if (uart_handle_break(&up->port))
+			return;
+
+	}
+
+	if (lsr & UART_LSR_PE) {
+		flag = TTY_PARITY;
+		up->port.icount.parity++;
+	}
+
+	if (lsr & UART_LSR_FE) {
+		flag = TTY_FRAME;
+		up->port.icount.frame++;
+	}
+
+	if (lsr & UART_LSR_OE)
+		up->port.icount.overrun++;
+
+#ifdef CONFIG_SERIAL_OMAP_CONSOLE
+	if (up->port.line == up->port.cons->index) {
+		/* Recover the break flag from console xmit */
+		lsr |= up->lsr_break_flag;
+	}
+#endif
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
+}
+
+static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
+{
+	unsigned char ch = 0;
+	unsigned int flag;
+
+	if (!(lsr & UART_LSR_DR))
+		return;
+
+	ch = serial_in(up, UART_RX);
+	flag = TTY_NORMAL;
+	up->port.icount.rx++;
+
+	if (uart_handle_sysrq_char(&up->port, ch))
+		return;
+
+	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
+}
+
 /**
  * serial_omap_irq() - This handles the interrupt from one port
  * @irq: uart port irq number
@@ -349,54 +343,57 @@ static unsigned int check_modem_status(struct uart_omap_port *up)
 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 {
 	struct uart_omap_port *up = dev_id;
+	struct tty_struct *tty = up->port.state->port.tty;
 	unsigned int iir, lsr;
 	unsigned int type;
 	unsigned long flags;
 	irqreturn_t ret = IRQ_NONE;
+	int max_count = 256;
 
 	spin_lock_irqsave(&up->port.lock, flags);
 	pm_runtime_get_sync(up->dev);
-	iir = serial_in(up, UART_IIR);
-again:
-	if (iir & UART_IIR_NO_INT)
-		goto out;
 
-	ret = IRQ_HANDLED;
-	lsr = serial_in(up, UART_LSR);
+	do {
+		iir = serial_in(up, UART_IIR);
+		if (iir & UART_IIR_NO_INT)
+			break;
 
-	/* extract IRQ type from IIR register */
-	type = iir & 0x3e;
+		ret = IRQ_HANDLED;
+		lsr = serial_in(up, UART_LSR);
 
-	switch (type) {
-	case UART_IIR_MSI:
-		check_modem_status(up);
-		break;
-	case UART_IIR_THRI:
-		if (lsr & UART_LSR_THRE)
-			transmit_chars(up);
-		break;
-	case UART_IIR_RDI:
-		if (lsr & UART_LSR_DR)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RLSI:
-		if (lsr & UART_LSR_BRK_ERROR_BITS)
-			receive_chars(up, &lsr);
-		break;
-	case UART_IIR_RX_TIMEOUT:
-		receive_chars(up, &lsr);
-		break;
-	case UART_IIR_CTS_RTS_DSR:
-		iir = serial_in(up, UART_IIR);
-		goto again;
-	case UART_IIR_XOFF:
-		/* FALLTHROUGH */
-	default:
-		break;
-	}
+		/* extract IRQ type from IIR register */
+		type = iir & 0x3e;
+
+		switch (type) {
+		case UART_IIR_MSI:
+			check_modem_status(up);
+			break;
+		case UART_IIR_THRI:
+			if (lsr & UART_LSR_THRE)
+				transmit_chars(up);
+			break;
+		case UART_IIR_RX_TIMEOUT:
+			/* FALLTHROUGH */
+		case UART_IIR_RDI:
+			serial_omap_rdi(up, lsr);
+			break;
+		case UART_IIR_RLSI:
+			serial_omap_rlsi(up, lsr);
+			break;
+		case UART_IIR_CTS_RTS_DSR:
+			/* simply try again */
+			break;
+		case UART_IIR_XOFF:
+			/* FALLTHROUGH */
+		default:
+			break;
+		}
+	} while (!(iir & UART_IIR_NO_INT) && max_count--);
 
-out:
 	spin_unlock_irqrestore(&up->port.lock, flags);
+
+	tty_flip_buffer_push(tty);
+
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
 	up->port_activity = jiffies;
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:57 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:57 +0300
Subject: [PATCH v3 17/23] serial: omap: unlock the port lock
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-18-git-send-email-balbi@ti.com>

From: Ruchika Kharwar <ruchika at ti.com>

This patch unlocks the port lock before calling a serial_core API
and re-acquires the port lock after calling it.
This patch fixes a system freeze issue seen when the serial_core
API uart_write_wakeup() eventually attempts to acquire the port lock
already acquired by omap serial interrupt handler.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Ruchika Kharwar <ruchika at ti.com>
Signed-off-by: Pavan Savoy <pavan_savoy at ti.com>
Signed-off-by: Vijay Badawadagi <bvijay at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index ba22247..e871635 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -223,8 +223,11 @@ static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 			break;
 	} while (--count > 0);
 
-	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
+		spin_unlock(&up->port.lock);
 		uart_write_wakeup(&up->port);
+		spin_lock(&up->port.lock);
+	}
 
 	if (uart_circ_empty(xmit))
 		serial_omap_stop_tx(&up->port);
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:58 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:58 +0300
Subject: [PATCH v3 18/23] serial: omap: implement set_wake
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-19-git-send-email-balbi@ti.com>

This has been missing from OMAP UART driver
for quite a while and it's simple enough
to implement it.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index e871635..d6f5eed 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -861,6 +861,15 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 }
 
+static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
+{
+	struct uart_omap_port *up = to_uart_omap_port(port);
+
+	serial_omap_enable_wakeup(up, state);
+
+	return 0;
+}
+
 static void
 serial_omap_pm(struct uart_port *port, unsigned int state,
 	       unsigned int oldstate)
@@ -1115,6 +1124,7 @@ static struct uart_ops serial_omap_pops = {
 	.shutdown	= serial_omap_shutdown,
 	.set_termios	= serial_omap_set_termios,
 	.pm		= serial_omap_pm,
+	.set_wake	= serial_omap_set_wake,
 	.type		= serial_omap_type,
 	.release_port	= serial_omap_release_port,
 	.request_port	= serial_omap_request_port,
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:32:59 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:32:59 +0300
Subject: [PATCH v3 19/23] serial: omap: make sure to put() on poll_get_char
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-20-git-send-email-balbi@ti.com>

if we would reach serial_omap_get_char() while
Data Ready bit isn't set, we would return from
it without kicking our pm timer. This would mean
we would, eventually, have an unbalanced
pm_runtime_get on our device which would prevent
it from ever sleeping again.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d6f5eed..c3579c0 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -991,12 +991,17 @@ static int serial_omap_poll_get_char(struct uart_port *port)
 
 	pm_runtime_get_sync(up->dev);
 	status = serial_in(up, UART_LSR);
-	if (!(status & UART_LSR_DR))
-		return NO_POLL_CHAR;
+	if (!(status & UART_LSR_DR)) {
+		status = NO_POLL_CHAR;
+		goto out;
+	}
 
 	status = serial_in(up, UART_RX);
+
+out:
 	pm_runtime_mark_last_busy(up->dev);
 	pm_runtime_put_autosuspend(up->dev);
+
 	return status;
 }
 
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:33:00 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:33:00 +0300
Subject: [PATCH v3 20/23] serial: omap: fix software flow control
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-21-git-send-email-balbi@ti.com>

From: Vikram Pandita <vikram.pandita at ti.com>

Software flow control register bits were not defined correctly.

Also clarify the IXON and IXOFF logic to reflect what userspace wants.

Cc: stable at vger.kernel.org
Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Vikram Pandita <vikram.pandita at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h |  4 ++--
 drivers/tty/serial/omap-serial.c              | 12 ++++++------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 743ac80..12e6805 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -42,10 +42,10 @@
 #define OMAP_UART_WER_MOD_WKUP	0X7F
 
 /* Enable XON/XOFF flow control on output */
-#define OMAP_UART_SW_TX		0x04
+#define OMAP_UART_SW_TX		0x8
 
 /* Enable XON/XOFF flow control on input */
-#define OMAP_UART_SW_RX		0x04
+#define OMAP_UART_SW_RX		0x2
 
 #define OMAP_UART_SYSC_RESET	0X07
 #define OMAP_UART_TCR_TRIG	0X0F
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index c3579c0..d49981d 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -606,19 +606,19 @@ serial_omap_configure_xonxoff
 
 	/*
 	 * IXON Flag:
-	 * Enable XON/XOFF flow control on output.
-	 * Transmit XON1, XOFF1
+	 * Flow control for OMAP.TX
+	 * OMAP.RX should listen for XON/XOFF
 	 */
 	if (termios->c_iflag & IXON)
-		up->efr |= OMAP_UART_SW_TX;
+		up->efr |= OMAP_UART_SW_RX;
 
 	/*
 	 * IXOFF Flag:
-	 * Enable XON/XOFF flow control on input.
-	 * Receiver compares XON1, XOFF1.
+	 * Flow control for OMAP.RX
+	 * OMAP.TX should send XON/XOFF
 	 */
 	if (termios->c_iflag & IXOFF)
-		up->efr |= OMAP_UART_SW_RX;
+		up->efr |= OMAP_UART_SW_TX;
 
 	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:33:01 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:33:01 +0300
Subject: [PATCH v3 21/23] serial: omap: remove unnecessary header and add a
 missing one
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-22-git-send-email-balbi@ti.com>

this driver doesn't use any from <plat/dmtimer.h>, so
we can remove it without any problems.

This will, however cause a problem because omap-serial.c
was relying on indirect inclusion of <linux/platform_device.h>,
let's fix the issue by including <linux/platform_device.h>
on omap-serial.c as it should be.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index d49981d..e5a56cb 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -32,6 +32,7 @@
 #include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
+#include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/serial_core.h>
@@ -39,7 +40,6 @@
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 
-#include <plat/dmtimer.h>
 #include <plat/omap-serial.h>
 
 #define UART_BUILD_REVISION(x, y)	(((x) << 8) | (y))
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:33:02 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:33:02 +0300
Subject: [PATCH v3 22/23] serial: omap: move uart_omap_port definition to C
 file
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-23-git-send-email-balbi@ti.com>

nobody needs to access the uart_omap_port structure
other than omap-serial.c file. Let's move that
structure definition to the C source file in order
to prevent anyone from accessing our structure.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h | 37 --------------------------
 drivers/tty/serial/omap-serial.c              | 38 +++++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 12e6805..c266934 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -102,41 +102,4 @@ struct uart_omap_dma {
 	unsigned int		rx_timeout;
 };
 
-struct uart_omap_port {
-	struct uart_port	port;
-	struct uart_omap_dma	uart_dma;
-	struct device		*dev;
-
-	unsigned char		ier;
-	unsigned char		lcr;
-	unsigned char		mcr;
-	unsigned char		fcr;
-	unsigned char		efr;
-	unsigned char		dll;
-	unsigned char		dlh;
-	unsigned char		mdr1;
-	unsigned char		scr;
-
-	int			use_dma;
-	/*
-	 * Some bits in registers are cleared on a read, so they must
-	 * be saved whenever the register is read but the bits will not
-	 * be immediately processed.
-	 */
-	unsigned int		lsr_break_flag;
-	unsigned char		msr_saved_flags;
-	char			name[20];
-	unsigned long		port_activity;
-	u32			context_loss_cnt;
-	u32			errata;
-	u8			wakeups_enabled;
-
-	struct pm_qos_request	pm_qos_request;
-	u32			latency;
-	u32			calc_latency;
-	struct work_struct	qos_work;
-};
-
-#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
-
 #endif /* __OMAP_SERIAL_H__ */
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index e5a56cb..0e5ffdf 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -69,6 +69,44 @@
 #define OMAP_UART_MVR_MAJ_SHIFT		8
 #define OMAP_UART_MVR_MIN_MASK		0x3f
 
+struct uart_omap_port {
+	struct uart_port	port;
+	struct uart_omap_dma	uart_dma;
+	struct device		*dev;
+
+	unsigned char		ier;
+	unsigned char		lcr;
+	unsigned char		mcr;
+	unsigned char		fcr;
+	unsigned char		efr;
+	unsigned char		dll;
+	unsigned char		dlh;
+	unsigned char		mdr1;
+	unsigned char		scr;
+
+	int			use_dma;
+	/*
+	 * Some bits in registers are cleared on a read, so they must
+	 * be saved whenever the register is read but the bits will not
+	 * be immediately processed.
+	 */
+	unsigned int		lsr_break_flag;
+	unsigned char		msr_saved_flags;
+	char			name[20];
+	unsigned long		port_activity;
+	u32			context_loss_cnt;
+	u32			errata;
+	u8			wakeups_enabled;
+	unsigned int		irq_pending:1;
+
+	struct pm_qos_request	pm_qos_request;
+	u32			latency;
+	u32			calc_latency;
+	struct work_struct	qos_work;
+};
+
+#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
+
 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 
 /* Forward declaration of functions */
-- 
1.7.12.rc3



From balbi at ti.com  Thu Aug 23 06:33:03 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 23 Aug 2012 13:33:03 +0300
Subject: [PATCH v3 23/23] serial: omap: enable RX and TX FIFO usage
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <1345717983-18179-24-git-send-email-balbi@ti.com>

enable RX FIFO for 16 characters and TX FIFO
for 16 spaces.

Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/tty/serial/omap-serial.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 0e5ffdf..137d475 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -55,8 +55,8 @@
 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK		(1 << 7)
 
 /* FCR register bitmasks */
-#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT		6
 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK			(0x3 << 6)
+#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK			(0x3 << 4)
 
 /* MVR register bitmasks */
 #define OMAP_UART_MVR_SCHEME_SHIFT	30
@@ -820,9 +820,13 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 
-	/* Set receive FIFO threshold to 1 byte */
+	/* Set receive FIFO threshold to 16 characters and
+	 * transmit FIFO threshold to 16 spaces
+	 */
 	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
-	up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
+	up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
+	up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
+		UART_FCR_ENABLE_FIFO;
 
 	serial_out(up, UART_FCR, up->fcr);
 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-- 
1.7.12.rc3



From m.grzeschik at pengutronix.de  Thu Aug 23 06:35:57 2012
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Thu, 23 Aug 2012 12:35:57 +0200
Subject: [PATCH] ARM: dts: imx: add imx5x usb entries
Message-ID: <1345718157-7927-1-git-send-email-m.grzeschik@pengutronix.de>

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/boot/dts/imx51.dtsi |   28 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx53.dtsi |   28 ++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc..4ec015f 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
 				};
 			};
 
+			usb at 73f80000 {
+				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+				reg = <0x73f80000 0x0200>;
+				interrupts = <18>;
+				status = "disabled";
+			};
+
+			usb at 73f80200 {
+				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+				reg = <0x73f80200 0x0200>;
+				interrupts = <14>;
+				status = "disabled";
+			};
+
+			usb at 73f80400 {
+				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+				reg = <0x73f80400 0x0200>;
+				interrupts = <16>;
+				status = "disabled";
+			};
+
+			usb at 73f80600 {
+				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+				reg = <0x73f80600 0x0200>;
+				interrupts = <17>;
+				status = "disabled";
+			};
+
 			gpio1: gpio at 73f84000 {
 				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 				reg = <0x73f84000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165..24280a4 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
 				};
 			};
 
+			usb at 53f80000 {
+				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+				reg = <0x53f80000 0x0200>;
+				interrupts = <18>;
+				status = "disabled";
+			};
+
+			usb at 53f80200 {
+				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+				reg = <0x53f80200 0x0200>;
+				interrupts = <14>;
+				status = "disabled";
+			};
+
+			usb at 53f80400 {
+				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+				reg = <0x53f80400 0x0200>;
+				interrupts = <16>;
+				status = "disabled";
+			};
+
+			usb at 53f80600 {
+				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+				reg = <0x53f80600 0x0200>;
+				interrupts = <17>;
+				status = "disabled";
+			};
+
 			gpio1: gpio at 53f84000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 				reg = <0x53f84000 0x4000>;
-- 
1.7.10.4



From m.grzeschik at pengutronix.de  Thu Aug 23 06:38:48 2012
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Thu, 23 Aug 2012 12:38:48 +0200
Subject: [PATCH] ARM: imx: add imx5x usb controller clock lookups
Message-ID: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx51-imx53.c |   36 +++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..6ce49b1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -258,18 +258,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
 	clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
 	clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
-	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
-	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
-	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
-	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
-	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
-	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
-	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
-	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
-	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
-	clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
-	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
-	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
@@ -351,6 +339,18 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
 	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
 	clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");
 	clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
 	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
 	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -439,6 +439,18 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
 	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
 	clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80000.usb");
 	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
 	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
 	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
-- 
1.7.10.4



From arnd at arndb.de  Thu Aug 23 06:40:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 10:40:16 +0000
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <201208231040.16702.arnd@arndb.de>

On Thursday 23 August 2012, Tony Prisk wrote:
> Patchset based on Arnd's arm-soc/for-next branch.
> 
> 
> Could I get this reviewed, hopefully for inclusion into v3.7.

I can take them into the arm-soc tree if there are no new comments.
For the last two patches, you need to get an Acked-by comment from the
gpio and clk maintainers, respectively, or you should send them
the patches for inclusion in those subsystem trees.

	Arnd


From will.deacon at arm.com  Thu Aug 23 06:43:56 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 23 Aug 2012 11:43:56 +0100
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120823104356.GA13622@mudshark.cambridge.arm.com>

On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index 99afa74..7cc67ce 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
>  unsigned long get_wchan(struct task_struct *p);
>  
>  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> -#define cpu_relax()			smp_mb()
> +#define cpu_relax()		do {					\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\
> +					asm("nop");			\

Can you use nop() instead of the explicit asm? Also, I think we should try
and use some methodology on deciding the number of nops to insert. Without
having a full handle on the problem at the moment, it would seem that we
need at least NR_CPUS worth (since the number of spinning secondaries is
NR_CPUS-1 and they may execute their barriers in lock-step).

Will


From catalin.marinas at arm.com  Thu Aug 23 06:42:52 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 23 Aug 2012 11:42:52 +0100
Subject: PER_LINUX32, Was: [PATCH v2 21/31] arm64: 32-bit (compat)
 applications support
In-Reply-To: <201208230646.31276.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
 <20120816102808.GH31784@mudshark.cambridge.arm.com>
 <201208230646.31276.arnd@arndb.de>
Message-ID: <20120823104252.GA7585@arm.com>

On Thu, Aug 23, 2012 at 07:46:30AM +0100, Arnd Bergmann wrote:
> On Thursday 16 August 2012, Will Deacon wrote:
> > On Wed, Aug 15, 2012 at 03:34:04PM +0100, Arnd Bergmann wrote:
> > > On Tuesday 14 August 2012, Catalin Marinas wrote:
> > > > +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> > > > +{
> > > > +	int ret;
> > > > +
> > > > +	if (personality(current->personality) == PER_LINUX32 &&
> > > > +		personality == PER_LINUX)
> > > > +		personality = PER_LINUX32;
> > > > +	ret = sys_personality(personality);
> > > > +	if (ret == PER_LINUX32)
> > > > +		ret = PER_LINUX;
> > > > +	return ret;
> > > > +}
> > > 
> > > Where did you get this from?
> > > 
> > > You should not need compat_sys_personality, just call the native function.
> > 
> > Hmm, but in that case an aarch32 application doing a personality(PER_LINUX)
> > syscall will start seeing the wrong uname.
> 
> Coming back at this topic, I noticed another issue. Jiri Kosina
> has recently posted patches to fix this function in the other architectures
> in order to mask out the other personality bits, which is a correct fix,
> but the above function is odd for other reasons.
> 
> * On MIPS, it is used only for compat tasks, like you have it above.
> * On PA-RISC, it is used for native 32 bit tasks and for compat 32 bit tasks,
>   but not for native 64 bit ones.
> * On IA64, it was used for compat tasks (support for which has since
>   been removed from the kernel), plus all 32 bit tasks would start with
>   PER_LINUX32.
> * On PowerPC, Sparc and s390, it is used for native 64 bit tasks and for
>   compat 32 bit tasks, but not for native 32 bit ones.
> * On Tile, it was never used.
> * On x86_64, it used to be defined (copied from ia64) but not used
>   throughout the git history.
> 
> The semantics of the function are also interesting: The intention seems
> to be that to a compat task, PER_LINUX32 would appear as PER_LINUX.
> The effect is that any process can set PER_LINUX32 but it can never
> be unset except by a 64 bit MIPS or PA-RISC task.

IMHO, it makes sense to keep the compat_sys_personality() as implemented
above. You may want to start a chroot ARMv7 environment using "linux32"
but don't want some 32-bit app calling personality(PER_LINUX) (as that's
the default personality on an ARMv7 system) and unknowingly changing the
personality that you wanted to enforce via "linux32".

I agree with not setting the personality based on the ELF type, but
that's different from the compat_sys_personality().

> Since x86_64 does not implement this behavior at all, I suspect that
> there are now lots of things depending on not having it, while all
> the other architectures might also have some (even predating the
> x86_64 port) use cases that depend on depend on not being able to
> observe PER_LINUX32 in 32 bit compat tasks.
> 
> I think we should try to agree on how this is all supposed to work
> and use common code, either put the ppc/sparc/s390 version into
> sys_personality, or remove all of them and just do what x86 and tile
> do, using the regular sys_personality for all tasks.

Late topic for the KS :).

I don't think we can move this behaviour to sys_personality. We may want
to add a generic compat_sys_personality() if we agree on the above
use-case.

-- 
Catalin


From thomas.abraham at linaro.org  Thu Aug 23 07:15:25 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:45:25 +0530
Subject: [PATCH v3 0/4] pinctrl: add support for samsung pinctrl driver
Message-ID: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>

Changes since v2:
- Fixes as suggested by Linus Walleij <linus.walleij at linaro.org>

Changes since v1:
- Added support for external gpio and wakeup interrupts for Exynos4.

This patch series adds a common pinctrl driver for all Samsung platforms and
enables the pinctrl driver support for Exynos4210 based device tree enabled
platforms. The scope of this driver is limited to only device tree enabled
platforms.

The intention of this driver is to replace the existing gpiolib driver and
provide pinctrl subsystem interface to configure the pins/mux instead
of existing platform callbacks.

Note that, the Samsung pinctrl driver is usable only on device tree enabled
Samsung platforms. Legacy platforms would still continue to use the older
gpiolib driver and hence updates to device drivers to use the pinctrl api
should ensure that support for legacy platforms is maintained.

The first patch adds a new pinctrl driver for Samsung. It provides interfaces
to the pinctrl and gpiolib subsystems. This driver provides a common framework
for all Samsung SoC's to enable the pinctrl and gpiolib support. The driver
accepts the information about pins, groups and functions from the device tree
and the information about gpio banks is supplied using driver data.

The second patch adds the driver data required to operate the pinctrl driver
on Exynos4210 based platforms. It allows includes support for Exynos4210
specific external gpio and wakeup interrupts which are provides to the Samsung
pinctrl driver as extensions.

The third patch modifies the existing gpiolib driver to skip the gpio pin
registrations if pinctrl driver support is found to be enabled. The fourth
patch skips the external wakeup interrupt configuration process in the
Exynos4 platform code if the external wakeup interrupt support is provided
by the pin-control driver.

Thomas Abraham (4):
  pinctrl: add samsung pinctrl and gpiolib driver
  pinctrl: add exynos4210 specific extensions for samsung pinctrl driver
  gpio: exynos4: skip gpiolib registration if pinctrl driver is used
  ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used

 .../bindings/pinctrl/samsung-pinctrl.txt           |  196 +++++
 arch/arm/mach-exynos/common.c                      |   26 +
 drivers/gpio/gpio-samsung.c                        |   21 +
 drivers/pinctrl/Kconfig                            |    9 +
 drivers/pinctrl/Makefile                           |    2 +
 drivers/pinctrl/pinctrl-exynos.c                   |  560 ++++++++++++
 drivers/pinctrl/pinctrl-exynos.h                   |  217 +++++
 drivers/pinctrl/pinctrl-samsung.c                  |  888 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h                  |  239 ++++++
 9 files changed, 2158 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-exynos.c
 create mode 100644 drivers/pinctrl/pinctrl-exynos.h
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h



From thomas.abraham at linaro.org  Thu Aug 23 07:15:28 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:45:28 +0530
Subject: [PATCH v3 3/4] gpio: exynos4: skip gpiolib registration if pinctrl
 driver is used
In-Reply-To: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345720529-32315-4-git-send-email-thomas.abraham@linaro.org>

Pinctrl driver, when enabled, registers all the gpio pins and hence the
registration of gpio pins by this driver can be skipped.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/gpio-samsung.c |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..41ab7f6 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2734,6 +2734,27 @@ static __init void exynos4_gpiolib_init(void)
 	int group = 0;
 	void __iomem *gpx_base;
 
+#ifdef CONFIG_PINCTRL_SAMSUNG
+		/*
+		 * This gpio driver includes support for device tree support and
+		 * there are platforms using it. In order to maintain
+		 * compatibility with those platforms, and to allow non-dt
+		 * Exynos4210 platforms to use this gpiolib support, a check
+		 * is added to find out if there is a active pin-controller
+		 * driver support available. If it is available, this gpiolib
+		 * support is ignored and the gpiolib support available in
+		 * pin-controller driver is used. This is a temporary check and
+		 * will go away when all of the Exynos4210 platforms have
+		 * switched to using device tree and the pin-ctrl driver.
+		 */
+		struct device_node *pctrl_np;
+		const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+		pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat);
+		if (pctrl_np)
+			if (of_device_is_available(pctrl_np))
+				return;
+#endif
+
 	/* gpio part1 */
 	gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
 	if (gpio_base1 == NULL) {
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Thu Aug 23 07:15:26 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:45:26 +0530
Subject: [PATCH v3 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345720529-32315-2-git-send-email-thomas.abraham@linaro.org>

Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../bindings/pinctrl/samsung-pinctrl.txt           |  196 +++++
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-samsung.c                  |  888 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h                  |  239 ++++++
 5 files changed, 1329 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h

diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
new file mode 100644
index 0000000..000ca20
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -0,0 +1,196 @@
+Samsung GPIO and Pin Mux/Config controller
+
+Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pads/pins
+and also provides ability to multiplex and configure the output of various
+on-chip controllers onto these pads.
+
+Required Properties:
+- compatible: should be one of the following.
+  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
+  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
+
+- reg: Base address of the pin controller hardware module and length of
+  the address space it occupies.
+
+- interrupts: interrupt specifier for the controller. The format and value of
+  the interrupt specifier depends on the interrupt parent for the controller.
+
+- Pin mux/config groups as child nodes: The pin mux (selecting pin function
+  mode) and pin config (pull up/down, driver strength) settings are represented
+  as child nodes of the pin-controller node. There should be atleast one
+  child node and there is no limit on the count of these child nodes.
+
+  The child node should contain a list of pin(s) on which a particular pin
+  function selection or pin configuration (or both) have to applied. This
+  list of pins is specified using the property name "samsung,pins". There
+  should be atleast one pin specfied for this property and there is no upper
+  limit on the count of pins that can be specified. The pins are specified
+  using pin names which are derived from the hardware manual of the SoC. As
+  an example, the pins in GPA0 bank of the pin controller can be represented
+  as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
+  The format of the pin names should be (as per the hardware manual)
+  "[pin bank name]-[pin number within the bank]".
+
+  The pin function selection that should be applied on the pins listed in the
+  child node is specified using the "samsung,pin-function" property. The value
+  of this property that should be applied to each of the pins listed in the
+  "samsung,pins" property should be picked from the hardware manual of the SoC
+  for the specified pin group. This property is optional in the child node if
+  no specific function selection is desired for the pins listed in the child
+  node. The value of this property is used as-is to program the pin-controller
+  function selector register of the pin-bank.
+
+  The child node can also optionally specify one or more of the pin
+  configuration that should be applied on all the pins listed in the
+  "samsung,pins" property of the child node. The following pin configuration
+  properties are supported.
+
+  - samsung,pin-pud: Pull up/down configuration.
+  - samsung,pin-drv: Drive strength configuration.
+  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
+  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
+
+  The values specified by these config properties should be dervied from the
+  hardware manual and these values are programmed as-is into the pin
+  pull up/down and driver strength register of the pin-controller.
+
+  Note: A child should include atleast a pin function selection property or
+  pin configuration property (one or more) or both.
+
+  The client nodes that require a particular pin function selection and/or
+  pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
+  file.
+
+External GPIO and Wakeup Interrupts:
+
+The controller supports two types of external interrupts over gpio. The first
+is the external gpio interrupt and second is the external wakeup interrupts.
+The difference between the two is that the external wakeup interrupts can be
+used as system wakeup events.
+
+A. External GPIO Interrupts: For supporting external gpio interrupts, the
+   properties should be specified in the pin-controller device node.
+
+- interrupt-controller: identifies the controller node as interrupt-parent.
+- #interrupt-cells: the value of this property should be 2.
+  - First Cell: represents the external gpio interrupt number local to the
+    external gpio interrupt space of the controller.
+  - Second Cell: flags to identify the type of the interrupt
+    - 1 = rising edge triggered
+    - 2 = falling edge triggered
+    - 3 = rising and falling edge triggered
+    - 4 = high level triggered
+    - 8 = low level triggered
+
+B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
+   child node representing the external wakeup interrupt controller should be
+   included in the pin-controller device node. This child node should include
+   the following properties.
+
+   - compatible: identifies the type of the external wakeup interrupt controller
+     The possible values are:
+     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung Exynos4210 SoC.
+   - interrupt-parent: phandle of the interrupt parent to which the external
+     wakeup interrupts are forwarded to.
+   - interrupt-controller: identifies the node as interrupt-parent.
+   - #interrupt-cells: the value of this property should be 2
+     - First Cell: represents the external wakeup interrupt number local to
+       the external wakeup interrupt space of the controller.
+     - Second Cell: flags to identify the type of the interrupt
+       - 1 = rising edge triggered
+       - 2 = falling edge triggered
+       - 3 = rising and falling edge triggered
+       - 4 = high level triggered
+       - 8 = low level triggered
+
+Aliases:
+
+All the pin controller nodes should be represented in the aliases node using
+the following format 'pinctrl{n}' where n is a unique number for the alias.
+
+Example 1: A pin-controller node with pin groups.
+
+	pinctrl_0: pinctrl at 11400000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa0-4", "gpa0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_bus: i2c2-bus {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+Example 2: A pin-controller node with external wakeup interrupt controller node.
+
+	pinctrl_1: pinctrl at 11000000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+					<0 32 0>;
+		};
+	};
+
+Example 3: A uart client node that supports 'default' and 'flow-control' states.
+
+	uart at 13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 52 0>;
+		pinctrl-names = "default", "flow-control;
+		pinctrl-0 = <&uart0_data>;
+		pinctrl-1 = <&uart0_data &uart0_fctl>;
+	};
+
+Example 4: Set up the default pin state for uart controller.
+
+	static int s3c24xx_serial_probe(struct platform_device *pdev) {
+		struct pinctrl *pinctrl;
+		...
+		...
+		pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 73aafd9..b4503cd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -161,6 +161,11 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_SAMSUNG
+	bool "Samsung pinctrl driver"
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index cda3984..7155301 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
new file mode 100644
index 0000000..8a24223
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -0,0 +1,888 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This driver implements the Samsung pinctrl driver. It supports setting up of
+ * pinmux and pinconf configurations. The gpiolib interface is also included.
+ * External interrupt (gpio and wakeup) support are not included in this driver
+ * but provides extensions to which platform specific implementation of the gpio
+ * and wakeup interrupts can be hooked to.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+
+#include "core.h"
+#include "pinctrl-samsung.h"
+
+#define GROUP_SUFFIX		"-grp"
+#define GSUFFIX_LEN		sizeof(GROUP_SUFFIX)
+#define FUNCTION_SUFFIX		"-mux"
+#define FSUFFIX_LEN		sizeof(FUNCTION_SUFFIX)
+
+/* list of all possible config options supported */
+struct pin_config {
+	char		*prop_cfg;
+	unsigned int	cfg_type;
+} pcfgs[] = {
+	{ "samsung,pin-pud", PINCFG_TYPE_PUD },
+	{ "samsung,pin-drv", PINCFG_TYPE_DRV },
+	{ "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
+	{ "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
+};
+
+/* check if the selector is a valid pin group selector */
+static int samsung_get_group_count(struct pinctrl_dev *pctldev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->nr_groups;
+}
+
+/* return the name of the group selected by the group selector */
+static const char *samsung_get_group_name(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pin_groups[selector].name;
+}
+
+/* return the pin numbers associated with the specified group */
+static int samsung_get_group_pins(struct pinctrl_dev *pctldev,
+		unsigned selector, const unsigned **pins, unsigned *num_pins)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*pins = drvdata->pin_groups[selector].pins;
+	*num_pins = drvdata->pin_groups[selector].num_pins;
+	return 0;
+}
+
+/* create pinctrl_map entries by parsing device tree nodes */
+static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
+			struct device_node *np, struct pinctrl_map **maps,
+			unsigned *nmaps)
+{
+	struct device *dev = pctldev->dev;
+	struct pinctrl_map *map;
+	unsigned long *cfg = NULL;
+	char *gname, *fname;
+	int cfg_cnt = 0, map_cnt = 0, idx = 0;
+
+	/* count the number of config options specfied in the node */
+	for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+		if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
+			cfg_cnt++;
+	}
+
+	/*
+	 * Find out the number of map entries to create. All the config options
+	 * can be accomadated into a single config map entry.
+	 */
+	if (cfg_cnt)
+		map_cnt = 1;
+	if (of_find_property(np, "samsung,pin-function", NULL))
+		map_cnt++;
+	if (!map_cnt) {
+		dev_err(dev, "node %s does not have either config or function "
+				"configurations\n", np->name);
+		return -EINVAL;
+	}
+
+	/* Allocate memory for pin-map entries */
+	map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
+	if (!map) {
+		dev_err(dev, "could not alloc memory for pin-maps\n");
+		return -ENOMEM;
+	}
+	*nmaps = 0;
+
+	/*
+	 * Allocate memory for pin group name. The pin group name is derived
+	 * from the node name from which these map entries are be created.
+	 */
+	gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL);
+	if (!gname) {
+		dev_err(dev, "failed to alloc memory for group name\n");
+		goto free_map;
+	}
+	sprintf(gname, "%s%s", np->name, GROUP_SUFFIX);
+
+	/*
+	 * don't have config options? then skip over to creating function
+	 * map entries.
+	 */
+	if (!cfg_cnt)
+		goto skip_cfgs;
+
+	/* Allocate memory for config entries */
+	cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
+	if (!cfg) {
+		dev_err(dev, "failed to alloc memory for configs\n");
+		goto free_gname;
+	}
+
+	/* Prepare a list of config settings */
+	for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
+		u32 value;
+		if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
+			cfg[cfg_cnt++] =
+				PINCFG_PACK(pcfgs[idx].cfg_type, value);
+	}
+
+	/* create the config map entry */
+	map[*nmaps].data.configs.group_or_pin = gname;
+	map[*nmaps].data.configs.configs = cfg;
+	map[*nmaps].data.configs.num_configs = cfg_cnt;
+	map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+	*nmaps += 1;
+
+skip_cfgs:
+	/* create the function map entry */
+	if (of_find_property(np, "samsung,pin-function", NULL)) {
+		fname = kzalloc(strlen(np->name) + FSUFFIX_LEN,	GFP_KERNEL);
+		if (!fname) {
+			dev_err(dev, "failed to alloc memory for func name\n");
+			goto free_cfg;
+		}
+		sprintf(fname, "%s%s", np->name, FUNCTION_SUFFIX);
+
+		map[*nmaps].data.mux.group = gname;
+		map[*nmaps].data.mux.function = fname;
+		map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+		*nmaps += 1;
+	}
+
+	*maps = map;
+	return 0;
+
+free_cfg:
+	kfree(cfg);
+free_gname:
+	kfree(gname);
+free_map:
+	kfree(map);
+	return -ENOMEM;
+}
+
+/* free the memory allocated to hold the pin-map table */
+static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
+			     struct pinctrl_map *map, unsigned num_maps)
+{
+	int idx;
+
+	for (idx = 0; idx < num_maps; idx++) {
+		if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
+			kfree(map[idx].data.mux.function);
+			if (!idx)
+				kfree(map[idx].data.mux.group);
+		} else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
+			kfree(map[idx].data.configs.configs);
+			if (!idx)
+				kfree(map[idx].data.configs.group_or_pin);
+		}
+	};
+
+	kfree(map);
+}
+
+/* list of pinctrl callbacks for the pinctrl core */
+static struct pinctrl_ops samsung_pctrl_ops = {
+	.get_groups_count	= samsung_get_group_count,
+	.get_group_name		= samsung_get_group_name,
+	.get_group_pins		= samsung_get_group_pins,
+	.dt_node_to_map		= samsung_dt_node_to_map,
+	.dt_free_map		= samsung_dt_free_map,
+};
+
+/* check if the selector is a valid pin function selector */
+static int samsung_get_functions_count(struct pinctrl_dev *pctldev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->nr_functions;
+}
+
+/* return the name of the pin function specified */
+static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pmx_functions[selector].name;
+}
+
+/* return the groups associated for the specified function selector */
+static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
+		unsigned selector, const char * const **groups,
+		unsigned * const num_groups)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*groups = drvdata->pmx_functions[selector].groups;
+	*num_groups = drvdata->pmx_functions[selector].num_groups;
+	return 0;
+}
+
+/*
+ * given a pin number that is local to a pin controller, find out the pin bank
+ * and the register base of the pin bank.
+ */
+static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
+			void __iomem **reg, u32 *offset,
+			struct samsung_pin_bank **bank)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct samsung_pin_bank *b;
+
+	drvdata = dev_get_drvdata(gc->dev);
+	b = drvdata->ctrl->pin_banks;
+
+	while ((pin >= b->pin_base) &&
+			((b->pin_base + b->nr_pins - 1) < pin))
+		b++;
+
+	*reg = drvdata->virt_base + b->pctl_offset;
+	*offset = pin - b->pin_base;
+	if (bank)
+		*bank = b;
+
+	/* some banks have two config registers in a single bank */
+	if (*offset * b->func_width > BITS_PER_LONG)
+		*reg += 4;
+}
+
+/* enable or disable a pinmux function */
+static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group, bool enable)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pins;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	u32 mask, shift, data, pin_offset, cnt;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pins = drvdata->pin_groups[group].pins;
+
+	/*
+	 * for each pin in the pin group selected, program the correspoding pin
+	 * pin function number in the config register.
+	 */
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
+		pin_to_reg_bank(drvdata->gc, pins[cnt] - drvdata->ctrl->base,
+				&reg, &pin_offset, &bank);
+		mask = (1 << bank->func_width) - 1;
+		shift = pin_offset * bank->func_width;
+
+		data = readl(reg);
+		data &= ~(mask << shift);
+		if (enable)
+			data |= drvdata->pin_groups[group].func << shift;
+		writel(data, reg);
+	}
+}
+
+/* enable a specified pinmux by writing to registers */
+static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group)
+{
+	samsung_pinmux_setup(pctldev, selector, group, true);
+	return 0;
+}
+
+/* disable a specified pinmux by writing to registers */
+static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
+					unsigned selector, unsigned group)
+{
+	samsung_pinmux_setup(pctldev, selector, group, false);
+}
+
+/*
+ * The calls to gpio_direction_output() and gpio_direction_input()
+ * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
+ * function called from the gpiolib interface).
+ */
+static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+		struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	u32 data, pin_offset, mask, shift;
+
+	pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank);
+	mask = (1 << bank->func_width) - 1;
+	shift = pin_offset * bank->func_width;
+
+	data = readl(reg);
+	data &= ~(mask << shift);
+	if (!input)
+		data |= FUNC_OUTPUT << shift;
+	writel(data, reg);
+	return 0;
+}
+
+/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
+static struct pinmux_ops samsung_pinmux_ops = {
+	.get_functions_count	= samsung_get_functions_count,
+	.get_function_name	= samsung_pinmux_get_fname,
+	.get_function_groups	= samsung_pinmux_get_groups,
+	.enable			= samsung_pinmux_enable,
+	.disable		= samsung_pinmux_disable,
+	.gpio_set_direction	= samsung_pinmux_gpio_set_direction,
+};
+
+/* set or get the pin config settings for a specified pin */
+static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
+				unsigned long *config, bool set)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg_base;
+	enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
+	u32 data, width, pin_offset, mask, shift;
+	u32 cfg_value, cfg_reg;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg_base,
+					&pin_offset, &bank);
+
+	switch (cfg_type) {
+	case PINCFG_TYPE_PUD:
+		width = bank->pud_width;
+		cfg_reg = PUD_REG;
+		break;
+	case PINCFG_TYPE_DRV:
+		width = bank->drv_width;
+		cfg_reg = DRV_REG;
+		break;
+	case PINCFG_TYPE_CON_PDN:
+		width = bank->conpdn_width;
+		cfg_reg = CONPDN_REG;
+		break;
+	case PINCFG_TYPE_PUD_PDN:
+		width = bank->pudpdn_width;
+		cfg_reg = PUDPDN_REG;
+		break;
+	default:
+		WARN_ON(1);
+		return -EINVAL;
+	}
+
+	mask = (1 << width) - 1;
+	shift = pin_offset * width;
+	data = readl(reg_base + cfg_reg);
+
+	if (set) {
+		cfg_value = PINCFG_UNPACK_VALUE(*config);
+		data &= ~(mask << shift);
+		data |= (cfg_value << shift);
+		writel(data, reg_base + cfg_reg);
+	} else {
+		data >>= shift;
+		data &= mask;
+		*config = PINCFG_PACK(cfg_type, data);
+	}
+	return 0;
+}
+
+/* set the pin config settings for a specified pin */
+static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+				unsigned long config)
+{
+	return samsung_pinconf_rw(pctldev, pin, &config, true);
+}
+
+/* get the pin config settings for a specified pin */
+static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+					unsigned long *config)
+{
+	return samsung_pinconf_rw(pctldev, pin, config, false);
+}
+
+/* set the pin config settings for a specified pin group */
+static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
+			unsigned group, unsigned long config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pins;
+	unsigned int cnt;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pins = drvdata->pin_groups[group].pins;
+
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++)
+		samsung_pinconf_set(pctldev, pins[cnt], config);
+
+	return 0;
+}
+
+/* get the pin config settings for a specified pin group */
+static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
+				unsigned int group, unsigned long *config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pins;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pins = drvdata->pin_groups[group].pins;
+	samsung_pinconf_get(pctldev, pins[0], config);
+	return 0;
+}
+
+/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
+static struct pinconf_ops samsung_pinconf_ops = {
+	.pin_config_get		= samsung_pinconf_get,
+	.pin_config_set		= samsung_pinconf_set,
+	.pin_config_group_get	= samsung_pinconf_group_get,
+	.pin_config_group_set	= samsung_pinconf_group_set,
+};
+
+/* gpiolib gpio_set callback function */
+static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+	void __iomem *reg;
+	u32 pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data &= ~(1 << pin_offset);
+	if (value)
+		data |= 1 << pin_offset;
+	writel(data, reg + DAT_REG);
+}
+
+/* gpiolib gpio_get callback function */
+static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+	void __iomem *reg;
+	u32 pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data >>= pin_offset;
+	data &= 1;
+	return data;
+}
+
+/*
+ * gpiolib gpio_direction_input callback function. The setting of the pin
+ * mux function as 'gpio input' will be handled by the pinctrl susbsystem
+ * interface.
+ */
+static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+	return pinctrl_gpio_direction_input(gc->base + offset);
+}
+
+/*
+ * gpiolib gpio_direction_output callback function. The setting of the pin
+ * mux function as 'gpio output' will be handled by the pinctrl susbsystem
+ * interface.
+ */
+static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+							int value)
+{
+	samsung_gpio_set(gc, offset, value);
+	return pinctrl_gpio_direction_output(gc->base + offset);
+}
+
+/*
+ * Parse the pin names listed in the 'samsung,pins' property and convert it
+ * into a list of gpio numbers are create a pin group from it.
+ */
+static int __init samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
+			struct device_node *cfg_np, struct pinctrl_desc *pctl,
+			unsigned int **pin_list, unsigned int *npins)
+{
+	struct device *dev = &pdev->dev;
+	struct property *prop;
+	struct pinctrl_pin_desc const *pdesc = pctl->pins;
+	unsigned int idx = 0, cnt;
+	const char *pin_name;
+
+	*npins = of_property_count_strings(cfg_np, "samsung,pins");
+	if (*npins < 0) {
+		dev_err(dev, "invalid pin list in %s node", cfg_np->name);
+		return -EINVAL;
+	}
+
+	*pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
+	if (!*pin_list) {
+		dev_err(dev, "failed to allocate memory for pin list\n");
+		return -ENOMEM;
+	}
+
+	of_property_for_each_string(cfg_np, "samsung,pins", prop, pin_name) {
+		for (cnt = 0; cnt < pctl->npins; cnt++) {
+			if (pdesc[cnt].name) {
+				if (!strcmp(pin_name, pdesc[cnt].name)) {
+					(*pin_list)[idx++] = pdesc[cnt].number;
+					break;
+				}
+			}
+		}
+		if (cnt == pctl->npins) {
+			dev_err(dev, "pin %s not valid in %s node\n",
+					pin_name, cfg_np->name);
+			devm_kfree(dev, *pin_list);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Parse the information about all the available pin groups and pin functions
+ * from device node of the pin-controller. A pin group is formed with all
+ * the pins listed in the "samsung,pins" property.
+ */
+static int __init samsung_pinctrl_parse_dt(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *dev_np = dev->of_node;
+	struct device_node *cfg_np;
+	struct samsung_pin_group *groups, *grp;
+	struct samsung_pmx_func *functions, *func;
+	unsigned *pin_list;
+	unsigned int npins, grp_cnt, func_idx = 0;
+	char *gname, *fname;
+	int ret;
+
+	grp_cnt = of_get_child_count(dev_np);
+	if (!grp_cnt)
+		return -EINVAL;
+
+	groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
+	if (!groups) {
+		dev_err(dev, "failed allocate memory for ping group list\n");
+		return -EINVAL;
+	}
+	grp = groups;
+
+	functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
+	if (!functions) {
+		dev_err(dev, "failed to allocate memory for function list\n");
+		return -EINVAL;
+	}
+	func = functions;
+
+	/*
+	 * Iterate over all the child nodes of the pin controller node
+	 * and create pin groups and pin function lists.
+	 */
+	for_each_child_of_node(dev_np, cfg_np) {
+		u32 function;
+		if (of_find_property(cfg_np, "interrupt-controller", NULL))
+			continue;
+
+		ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
+					&drvdata->pctl,	&pin_list, &npins);
+		if (ret)
+			return ret;
+
+		/* derive pin group name from the node name */
+		gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN,
+					GFP_KERNEL);
+		if (!gname) {
+			dev_err(dev, "failed to alloc memory for group name\n");
+			return -ENOMEM;
+		}
+		sprintf(gname, "%s%s", cfg_np->name, GROUP_SUFFIX);
+
+		grp->name = gname;
+		grp->pins = pin_list;
+		grp->num_pins = npins;
+		of_property_read_u32(cfg_np, "samsung,pin-function", &function);
+		grp->func = function;
+		grp++;
+
+		if (!of_find_property(cfg_np, "samsung,pin-function", NULL))
+			continue;
+
+		/* derive function name from the node name */
+		fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN,
+					GFP_KERNEL);
+		if (!fname) {
+			dev_err(dev, "failed to alloc memory for func name\n");
+			return -ENOMEM;
+		}
+		sprintf(fname, "%s%s", cfg_np->name, FUNCTION_SUFFIX);
+
+		func->name = fname;
+		func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
+		if (!func->groups) {
+			dev_err(dev, "failed to alloc memory for group list "
+					"in pin function");
+			return -ENOMEM;
+		}
+		func->groups[0] = gname;
+		func->num_groups = 1;
+		func++;
+		func_idx++;
+	}
+
+	drvdata->pin_groups = groups;
+	drvdata->nr_groups = grp_cnt;
+	drvdata->pmx_functions = functions;
+	drvdata->nr_functions = func_idx;
+
+	return 0;
+}
+
+/* register the pinctrl interface with the pinctrl subsystem */
+static int __init samsung_pinctrl_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct pinctrl_desc *ctrldesc = &drvdata->pctl;
+	struct pinctrl_pin_desc *pindesc, *pdesc;
+	struct samsung_pin_bank *pin_bank;
+	char *pin_names;
+	int pin, bank, ret;
+
+	ctrldesc->name = "samsung-pinctrl";
+	ctrldesc->owner = THIS_MODULE;
+	ctrldesc->pctlops = &samsung_pctrl_ops;
+	ctrldesc->pmxops = &samsung_pinmux_ops;
+	ctrldesc->confops = &samsung_pinconf_ops;
+
+	pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
+			drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pindesc) {
+		dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
+		return -ENOMEM;
+	}
+	ctrldesc->pins = pindesc;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+
+	/* dynamically populate the pin number and pin name for pindesc */
+	for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
+		pdesc->number = pin + drvdata->ctrl->base;
+
+	/*
+	 * allocate space for storing the dynamically generated names for all
+	 * the pins which belong to this pin-controller.
+	 */
+	pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
+					drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pin_names) {
+		dev_err(&pdev->dev, "mem alloc for pin names failed\n");
+		return -ENOMEM;
+	}
+
+	/* for each pin, the name of the pin is pin-bank name + pin number */
+	for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) {
+		pin_bank = &drvdata->ctrl->pin_banks[bank];
+		for (pin = 0; pin < pin_bank->nr_pins; pin++) {
+			sprintf(pin_names, "%s-%d", pin_bank->name, pin);
+			pdesc = pindesc + pin_bank->pin_base + pin;
+			pdesc->name = pin_names;
+			pin_names += PIN_NAME_LENGTH;
+		}
+	}
+
+	drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
+	if (!drvdata->pctl_dev) {
+		dev_err(&pdev->dev, "could not register pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	drvdata->grange.name = "samsung-pctrl-gpio-range";
+	drvdata->grange.id = 0;
+	drvdata->grange.base = drvdata->ctrl->base;
+	drvdata->grange.npins = drvdata->ctrl->nr_pins;
+	drvdata->grange.gc = drvdata->gc;
+	pinctrl_add_gpio_range(drvdata->pctl_dev, &drvdata->grange);
+
+	ret = samsung_pinctrl_parse_dt(pdev, drvdata);
+	if (ret) {
+		pinctrl_unregister(drvdata->pctl_dev);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* register the gpiolib interface with the gpiolib subsystem */
+static int __init samsung_gpiolib_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct gpio_chip *gc;
+	int ret;
+
+	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
+	if (!gc) {
+		dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
+		return -ENOMEM;
+	}
+
+	drvdata->gc = gc;
+	gc->base = drvdata->ctrl->base;
+	gc->ngpio = drvdata->ctrl->nr_pins;
+	gc->dev = &pdev->dev;
+	gc->set = samsung_gpio_set;
+	gc->get = samsung_gpio_get;
+	gc->direction_input = samsung_gpio_direction_input;
+	gc->direction_output = samsung_gpio_direction_output;
+	gc->label = drvdata->ctrl->label;
+	gc->owner = THIS_MODULE;
+	ret = gpiochip_add(gc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
+					"code: %d\n", gc->label, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/* unregister the gpiolib interface with the gpiolib subsystem */
+static int __init samsung_gpiolib_unregister(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	int ret = gpiochip_remove(drvdata->gc);
+	if (ret) {
+		dev_err(&pdev->dev, "gpio chip remove failed\n");
+		return ret;
+	}
+	return 0;
+}
+
+static const struct of_device_id samsung_pinctrl_dt_match[];
+
+/* retrieve the soc specific data */
+static inline struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
+				struct platform_device *pdev)
+{
+	int id;
+	const struct of_device_id *match;
+	const struct device_node *node = pdev->dev.of_node;
+
+	id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
+	if (id < 0) {
+		dev_err(&pdev->dev, "failed to get alias id\n");
+		return NULL;
+	}
+	match = of_match_node(samsung_pinctrl_dt_match, node);
+	return (struct samsung_pin_ctrl *)match->data + id;
+}
+
+static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct device *dev = &pdev->dev;
+	struct samsung_pin_ctrl *ctrl;
+	struct resource *res;
+	int ret;
+
+	if (!dev->of_node) {
+		dev_err(dev, "device tree node not found\n");
+		return -ENODEV;
+	}
+
+	ctrl = samsung_pinctrl_get_soc_data(pdev);
+	if (!ctrl) {
+		dev_err(&pdev->dev, "driver data not available\n");
+		return -EINVAL;
+	}
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata) {
+		dev_err(dev, "failed to allocate memory for driver's "
+				"private data\n");
+		return -ENOMEM;
+	}
+	drvdata->ctrl = ctrl;
+	drvdata->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "cannot find IO resource\n");
+		return -ENOENT;
+	}
+
+	drvdata->virt_base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!drvdata->virt_base) {
+		dev_err(dev, "ioremap failed\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (res)
+		drvdata->irq = res->start;
+
+	ret = samsung_gpiolib_register(pdev, drvdata);
+	if (ret)
+		return ret;
+
+	ret = samsung_pinctrl_register(pdev, drvdata);
+	if (ret) {
+		samsung_gpiolib_unregister(pdev, drvdata);
+		return ret;
+	}
+
+	if (ctrl->eint_gpio_init)
+		ctrl->eint_gpio_init(drvdata);
+	if (ctrl->eint_wkup_init)
+		ctrl->eint_wkup_init(drvdata);
+
+	platform_set_drvdata(pdev, drvdata);
+	return 0;
+}
+
+static const struct of_device_id samsung_pinctrl_dt_match[] = {
+	{ .compatible = "samsung,pinctrl-exynos4210",
+		.data = (void *)exynos4210_pin_ctrl },
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
+
+static struct platform_driver samsung_pinctrl_driver = {
+	.probe		= samsung_pinctrl_probe,
+	.driver = {
+		.name	= "samsung-pinctrl",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(samsung_pinctrl_dt_match),
+	},
+};
+
+static int __init samsung_pinctrl_drv_register(void)
+{
+	return platform_driver_register(&samsung_pinctrl_driver);
+}
+postcore_initcall(samsung_pinctrl_drv_register);
+
+static void __exit samsung_pinctrl_drv_unregister(void)
+{
+	platform_driver_unregister(&samsung_pinctrl_driver);
+}
+module_exit(samsung_pinctrl_drv_unregister);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab at samsung.com>");
+MODULE_DESCRIPTION("Samsung pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
new file mode 100644
index 0000000..b895693
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -0,0 +1,239 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_SAMSUNG_H
+#define __PINCTRL_SAMSUNG_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+
+/* register offsets within a pin bank */
+#define DAT_REG		0x4
+#define PUD_REG		0x8
+#define DRV_REG		0xC
+#define CONPDN_REG	0x10
+#define PUDPDN_REG	0x14
+
+/* pinmux function number for pin as gpio output line */
+#define FUNC_OUTPUT	0x1
+
+/**
+ * enum pincfg_type - possible pin configuration types supported.
+ * @PINCFG_TYPE_PUD: Pull up/down configuration.
+ * @PINCFG_TYPE_DRV: Drive strength configuration.
+ * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
+ * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
+ */
+enum pincfg_type {
+	PINCFG_TYPE_PUD,
+	PINCFG_TYPE_DRV,
+	PINCFG_TYPE_CON_PDN,
+	PINCFG_TYPE_PUD_PDN,
+};
+
+/*
+ * pin configuration (pull up/down and drive strength) type and its value are
+ * packed together into a 16-bits. The upper 8-bits represent the configuration
+ * type and the lower 8-bits hold the value of the configuration type.
+ */
+#define PINCFG_TYPE_MASK		0xFF
+#define PINCFG_VALUE_SHIFT		8
+#define PINCFG_VALUE_MASK		(0xFF << PINCFG_VALUE_SHIFT)
+#define PINCFG_PACK(type, value)	(((value) << PINCFG_VALUE_SHIFT) | type)
+#define PINCFG_UNPACK_TYPE(cfg)		((cfg) & PINCFG_TYPE_MASK)
+#define PINCFG_UNPACK_VALUE(cfg)	(((cfg) & PINCFG_VALUE_MASK) >> \
+						PINCFG_VALUE_SHIFT)
+/**
+ * enum eint_type - possible external interrupt types.
+ * @EINT_TYPE_NONE: bank does not support external interrupts
+ * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
+ * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
+ *
+ * Samsung GPIO controller groups all the available pins into banks. The pins
+ * in a pin bank can support external gpio interrupts or external wakeup
+ * interrupts or no interrupts at all. From a software perspective, the only
+ * difference between external gpio and external wakeup interrupts is that
+ * the wakeup interrupts can additionally wakeup the system if it is in
+ * suspended state.
+ */
+enum eint_type {
+	EINT_TYPE_NONE,
+	EINT_TYPE_GPIO,
+	EINT_TYPE_WKUP,
+};
+
+/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
+#define PIN_NAME_LENGTH	10
+
+#define PIN_GROUP(n, p, f)				\
+	{						\
+		.name		= n,			\
+		.pins		= p,			\
+		.num_pins	= ARRAY_SIZE(p),	\
+		.func		= f			\
+	}
+
+#define PMX_FUNC(n, g)					\
+	{						\
+		.name		= n,			\
+		.groups		= g,			\
+		.num_groups	= ARRAY_SIZE(g),	\
+	}
+
+struct samsung_pinctrl_drv_data;
+
+/**
+ * struct samsung_pin_bank: represent a controller pin-bank.
+ * @reg_offset: starting offset of the pin-bank registers.
+ * @pin_base: starting pin number of the bank.
+ * @nr_pins: number of pins included in this bank.
+ * @func_width: width of the function selector bit field.
+ * @pud_width: width of the pin pull up/down selector bit field.
+ * @drv_width: width of the pin driver strength selector bit field.
+ * @conpdn_width: width of the sleep mode function selector bin field.
+ * @pudpdn_width: width of the sleep mode pull up/down selector bit field.
+ * @eint_type: type of the external interrupt supported by the bank.
+ * @irq_base: starting controller local irq number of the bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank {
+	u32		pctl_offset;
+	u32		pin_base;
+	u8		nr_pins;
+	u8		func_width;
+	u8		pud_width;
+	u8		drv_width;
+	u8		conpdn_width;
+	u8		pudpdn_width;
+	enum eint_type	eint_type;
+	u32		irq_base;
+	char		*name;
+};
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ * @base: starting system wide pin number.
+ * @nr_pins: number of pins supported by the controller.
+ * @nr_gint: number of external gpio interrupts supported.
+ * @nr_wint: number of external wakeup interrupts supported.
+ * @geint_con: offset of the ext-gpio controller registers.
+ * @geint_mask: offset of the ext-gpio interrupt mask registers.
+ * @geint_pend: offset of the ext-gpio interrupt pending registers.
+ * @weint_con: offset of the ext-wakeup controller registers.
+ * @weint_mask: offset of the ext-wakeup interrupt mask registers.
+ * @weint_pend: offset of the ext-wakeup interrupt pending registers.
+ * @svc: offset of the interrupt service register.
+ * @eint_gpio_init: platform specific callback to setup the external gpio
+ *	interrupts for the controller.
+ * @eint_wkup_init: platform specific callback to setup the external wakeup
+ *	interrupts for the controller.
+ * @label: for debug information.
+ */
+struct samsung_pin_ctrl {
+	struct samsung_pin_bank	*pin_banks;
+	u32		nr_banks;
+
+	u32		base;
+	u32		nr_pins;
+	u32		nr_gint;
+	u32		nr_wint;
+
+	u32		geint_con;
+	u32		geint_mask;
+	u32		geint_pend;
+
+	u32		weint_con;
+	u32		weint_mask;
+	u32		weint_pend;
+
+	u32		svc;
+
+	int		(*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
+	int		(*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
+	char		*label;
+};
+
+/**
+ * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
+ * @virt_base: register base address of the controller.
+ * @dev: device instance representing the controller.
+ * @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @ctrl: pin controller instance managed by the driver.
+ * @pctl: pin controller descriptor registered with the pinctrl subsystem.
+ * @pctl_dev: cookie representing pinctrl device instance.
+ * @pin_groups: list of pin groups available to the driver.
+ * @nr_groups: number of such pin groups.
+ * @pmx_functions: list of pin functions available to the driver.
+ * @nr_function: number of such pin functions.
+ * @gc: gpio_chip instance registered with gpiolib.
+ * @grange: linux gpio pin range supported by this controller.
+ */
+struct samsung_pinctrl_drv_data {
+	void __iomem			*virt_base;
+	struct device			*dev;
+	int				irq;
+
+	struct samsung_pin_ctrl		*ctrl;
+	struct pinctrl_desc		pctl;
+	struct pinctrl_dev		*pctl_dev;
+
+	const struct samsung_pin_group	*pin_groups;
+	unsigned int			nr_groups;
+	const struct samsung_pmx_func	*pmx_functions;
+	unsigned int			nr_functions;
+
+	struct irq_domain		*gpio_irqd;
+	struct irq_domain		*wkup_irqd;
+
+	struct gpio_chip		*gc;
+	struct pinctrl_gpio_range	grange;
+};
+
+/**
+ * struct samsung_pin_group: represent group of pins of a pinmux function.
+ * @name: name of the pin group, used to lookup the group.
+ * @pins: the pins included in this group.
+ * @num_pins: number of pins included in this group.
+ * @func: the function number to be programmed when selected.
+ */
+struct samsung_pin_group {
+	const char		*name;
+	const unsigned int	*pins;
+	u8			num_pins;
+	u8			func;
+};
+
+/**
+ * struct samsung_pmx_func: represent a pin function.
+ * @name: name of the pin function, used to lookup the function.
+ * @groups: one or more names of pin groups that provide this function.
+ * @num_groups: number of groups included in @groups.
+ */
+struct samsung_pmx_func {
+	const char		*name;
+	const char		**groups;
+	u8			num_groups;
+};
+
+/* list of all exported SoC specific data */
+extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
+
+#endif /* __PINCTRL_SAMSUNG_H */
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Thu Aug 23 07:15:29 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:45:29 +0530
Subject: [PATCH v3 4/4] ARM: EXYNOS: skip wakeup interrupt setup if pinctrl
 driver is used
In-Reply-To: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345720529-32315-5-git-send-email-thomas.abraham@linaro.org>

Pinctrl driver includes support for configuring the external wakeup
interrupts. On exynos platforms that use pinctrl driver, the setup
of wakeup interrupts in the exynos platform code can be skipped.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/common.c |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..715b690 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -980,6 +980,32 @@ static int __init exynos_init_irq_eint(void)
 {
 	int irq;
 
+#ifdef CONFIG_PINCTRL_SAMSUNG
+	/*
+	 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
+	 * functionality along with support for external gpio and wakeup
+	 * interrupts. If the samsung pinctrl driver is enabled and includes
+	 * the wakeup interrupt support, then the setting up external wakeup
+	 * interrupts here can be skipped. This check here is temporary to
+	 * allow exynos4 platforms that do not use Samsung pinctrl driver to
+	 * co-exist with platforms that do. When all of the Samsung Exynos4
+	 * platforms switch over to using the pinctrl driver, the wakeup
+	 * interrupt support code here can be completely removed.
+	 */
+	struct device_node *pctrl_np, *wkup_np;
+	const char *pctrl_compat = "samsung,pinctrl-exynos4210";
+	const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
+
+	for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
+		if (of_device_is_available(pctrl_np)) {
+			wkup_np = of_find_compatible_node(pctrl_np, NULL,
+							wkup_compat);
+			if (wkup_np)
+				return -ENODEV;
+		}
+	}
+#endif
+
 	if (soc_is_exynos5250())
 		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 	else
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Thu Aug 23 07:15:27 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:45:27 +0530
Subject: [PATCH v3 2/4] pinctrl: add exynos4210 specific extensions for samsung
 pinctrl driver
In-Reply-To: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345720529-32315-3-git-send-email-thomas.abraham@linaro.org>

Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.

Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 drivers/pinctrl/Kconfig          |    4 +
 drivers/pinctrl/Makefile         |    1 +
 drivers/pinctrl/pinctrl-exynos.c |  560 ++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-exynos.h |  217 +++++++++++++++
 4 files changed, 782 insertions(+), 0 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-exynos.c
 create mode 100644 drivers/pinctrl/pinctrl-exynos.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b4503cd..bcaf274 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -166,6 +166,10 @@ config PINCTRL_SAMSUNG
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_EXYNOS4
+	bool "Pinctrl driver data for Exynos4 SoC"
+	select PINCTRL_SAMSUNG
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 7155301..9665411 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
+obj-$(CONFIG_PINCTRL_EXYNOS4)	+= pinctrl-exynos.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
new file mode 100644
index 0000000..447818d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -0,0 +1,560 @@
+/*
+ * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file contains the Samsung Exynos specific information required by the
+ * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+ * external gpio and wakeup interrupt support.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <asm/mach/irq.h>
+
+#include "pinctrl-samsung.h"
+#include "pinctrl-exynos.h"
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+	{ .compatible = "samsung,exynos4210-wakeup-eint", },
+};
+
+static void exynos_gpio_irq_unmask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << edata->pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_gpio_irq_mask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask |= ~(1 << edata->pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_gpio_irq_ack(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
+
+	writel(1 << edata->pin, d->virt_base + reg_pend);
+}
+
+static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
+{
+	struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
+	struct samsung_pin_ctrl *ctrl = d->ctrl;
+	struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
+	unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
+	unsigned int con, trig_type;
+	unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		trig_type = EXYNOS_EINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		trig_type = EXYNOS_EINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		trig_type = EXYNOS_EINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		trig_type = EXYNOS_EINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		trig_type = EXYNOS_EINT_LEVEL_LOW;
+		break;
+	default:
+		pr_err("unsupported external interrupt type\n");
+		return -EINVAL;
+	}
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		__irq_set_handler_locked(irqd->irq, handle_edge_irq);
+	else
+		__irq_set_handler_locked(irqd->irq, handle_level_irq);
+
+	con = readl(d->virt_base + reg_con);
+	con &= ~(EXYNOS_EINT_CON_MASK << shift);
+	con |= trig_type << shift;
+	writel(con, d->virt_base + reg_con);
+	return 0;
+}
+
+/*
+ * irq_chip for gpio interrupts.
+ */
+static struct irq_chip exynos_gpio_irq_chip = {
+	.name		= "exynos_gpio_irq_chip",
+	.irq_unmask	= exynos_gpio_irq_unmask,
+	.irq_mask	= exynos_gpio_irq_mask,
+	.irq_ack		= exynos_gpio_irq_ack,
+	.irq_set_type	= exynos_gpio_irq_set_type,
+};
+
+/*
+ * given a controller-local external gpio interrupt number, prepare the handler
+ * data for it.
+ */
+static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
+				struct samsung_pinctrl_drv_data *d)
+{
+	struct samsung_pin_bank *bank = d->ctrl->pin_banks;
+	struct exynos_geint_data *eint_data;
+	unsigned int nr_banks = d->ctrl->nr_banks, idx;
+	unsigned int irq_base = 0, eint_offset = 0;
+
+	if (hw >= d->ctrl->nr_gint) {
+		dev_err(d->dev, "unsupported ext-gpio interrupt\n");
+		return NULL;
+	}
+
+	for (idx = 0; idx < nr_banks; idx++, bank++) {
+		if (bank->eint_type != EINT_TYPE_GPIO)
+			continue;
+		if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
+			break;
+		irq_base += bank->nr_pins;
+		eint_offset += 4;
+	}
+
+	if (idx == nr_banks) {
+		dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
+		return NULL;
+	}
+
+	eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
+	if (!eint_data) {
+		dev_err(d->dev, "no memory for eint-gpio data\n");
+		return NULL;
+	}
+
+	eint_data->bank	= bank;
+	eint_data->pin = hw - irq_base;
+	eint_data->eint_offset = eint_offset;
+	return eint_data;
+}
+
+static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	struct samsung_pinctrl_drv_data *d = h->host_data;
+	struct exynos_geint_data *eint_data;
+
+	eint_data = exynos_get_eint_data(hw, d);
+	if (!eint_data)
+		return -EINVAL;
+
+	irq_set_handler_data(virq, eint_data);
+	irq_set_chip_data(virq, h->host_data);
+	irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
+					handle_level_irq);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
+{
+	struct samsung_pinctrl_drv_data *d = h->host_data;
+	struct exynos_geint_data *eint_data;
+
+	eint_data = irq_get_handler_data(virq);
+	devm_kfree(d->dev, eint_data);
+}
+
+/*
+ * irq domain callbacks for external gpio interrupt controller.
+ */
+static const struct irq_domain_ops exynos_gpio_irqd_ops = {
+	.map	= exynos_gpio_irq_map,
+	.unmap	= exynos_gpio_irq_unmap,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
+{
+	struct samsung_pinctrl_drv_data *d = data;
+	struct samsung_pin_ctrl *ctrl = d->ctrl;
+	struct samsung_pin_bank *bank = ctrl->pin_banks;
+	unsigned int svc, group, pin, virq;
+
+	svc = readl(d->virt_base + ctrl->svc);
+	group = EXYNOS_SVC_GROUP(svc);
+	pin = svc & EXYNOS_SVC_NUM_MASK;
+
+	if (!group)
+		return IRQ_HANDLED;
+	bank += (group - 1);
+
+	virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
+	if (!virq)
+		return IRQ_NONE;
+	generic_handle_irq(virq);
+	return IRQ_HANDLED;
+}
+
+/*
+ * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
+ * @d: driver data of samsung pinctrl driver.
+ */
+static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
+{
+	struct device *dev = d->dev;
+	unsigned int ret;
+
+	if (!d->irq) {
+		dev_err(dev, "irq number not available\n");
+		return -EINVAL;
+	}
+
+	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
+					0, dev_name(dev), d);
+	if (ret) {
+		dev_err(dev, "irq request failed\n");
+		return -ENXIO;
+	}
+
+	d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
+				&exynos_gpio_irqd_ops, d);
+	if (!d->gpio_irqd) {
+		dev_err(dev, "gpio irq domain allocation failed\n");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
+static void exynos_wkup_irq_unmask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_wkup_irq_mask(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
+	unsigned long mask;
+
+	mask = readl(d->virt_base + reg_mask);
+	mask &= ~(1 << pin);
+	writel(mask, d->virt_base + reg_mask);
+}
+
+static void exynos_wkup_irq_ack(struct irq_data *irqd)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long pend = d->ctrl->weint_pend + (bank << 2);
+
+	writel(1 << pin, d->virt_base + pend);
+}
+
+static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
+{
+	struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
+	unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
+	unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
+	unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
+	unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
+	unsigned long con, trig_type;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		trig_type = EXYNOS_EINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		trig_type = EXYNOS_EINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		trig_type = EXYNOS_EINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		trig_type = EXYNOS_EINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		trig_type = EXYNOS_EINT_LEVEL_LOW;
+		break;
+	default:
+		pr_err("unsupported external interrupt type\n");
+		return -EINVAL;
+	}
+
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		__irq_set_handler_locked(irqd->irq, handle_edge_irq);
+	else
+		__irq_set_handler_locked(irqd->irq, handle_level_irq);
+
+	con = readl(d->virt_base + reg_con);
+	con &= ~(EXYNOS_EINT_CON_MASK << shift);
+	con |= trig_type << shift;
+	writel(con, d->virt_base + reg_con);
+	return 0;
+}
+
+/*
+ * irq_chip for wakeup interrupts
+ */
+static struct irq_chip exynos_wkup_irq_chip = {
+	.name	= "exynos_wkup_irq_chip",
+	.irq_unmask	= exynos_wkup_irq_unmask,
+	.irq_mask	= exynos_wkup_irq_mask,
+	.irq_ack	= exynos_wkup_irq_ack,
+	.irq_set_type	= exynos_wkup_irq_set_type,
+};
+
+/* interrupt handler for wakeup interrupts 0..15 */
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+	struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
+
+	chained_irq_enter(chip, desc);
+	chip->irq_mask(&desc->irq_data);
+
+	if (chip->irq_ack)
+		chip->irq_ack(&desc->irq_data);
+
+	eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
+	generic_handle_irq(eint_irq);
+	chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(chip, desc);
+}
+
+static void exynos_irq_demux_eint(int irq_base, unsigned long pend,
+					struct irq_domain *domain)
+{
+	unsigned int irq;
+
+	while (pend) {
+		irq = fls(pend) - 1;
+		generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
+		pend &= ~(1 << irq);
+	}
+}
+
+/* interrupt handler for wakeup interrupt 16 */
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_get_chip(irq);
+	struct exynos_weint_data *eintd = irq_get_handler_data(irq);
+	struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
+	unsigned long pend;
+
+	chained_irq_enter(chip, desc);
+	pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
+	exynos_irq_demux_eint(16, pend, eintd->domain);
+	pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
+	exynos_irq_demux_eint(24, pend, eintd->domain);
+	chained_irq_exit(chip, desc);
+}
+
+static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
+	irq_set_chip_data(virq, h->host_data);
+	set_irq_flags(virq, IRQF_VALID);
+	return 0;
+}
+
+/*
+ * irq domain callbacks for external wakeup interrupt controller.
+ */
+static const struct irq_domain_ops exynos_wkup_irqd_ops = {
+	.map	= exynos_wkup_irq_map,
+	.xlate	= irq_domain_xlate_twocell,
+};
+
+/*
+ * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
+ * @d: driver data of samsung pinctrl driver.
+ */
+static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
+{
+	struct device *dev = d->dev;
+	struct device_node *wkup_np;
+	struct exynos_weint_data *weint_data;
+	int idx, irq;
+
+	wkup_np = of_find_matching_node(dev->of_node, exynos_wkup_irq_ids);
+	if (!wkup_np) {
+		dev_err(dev, "wakeup controller node not found\n");
+		return -ENODEV;
+	}
+
+	d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
+				&exynos_wkup_irqd_ops, d);
+	if (!d->gpio_irqd) {
+		dev_err(dev, "wakeup irq domain allocation failed\n");
+		return -ENXIO;
+	}
+
+	weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
+	if (!weint_data) {
+		dev_err(dev, "could not allocate memory for weint_data\n");
+		return -ENOMEM;
+	}
+
+	irq = irq_of_parse_and_map(wkup_np, 16);
+	if (irq) {
+		weint_data[16].domain = d->wkup_irqd;
+		irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
+		irq_set_handler_data(irq, &weint_data[16]);
+	} else {
+		dev_err(dev, "irq number for EINT16-32 not found\n");
+	}
+
+	for (idx = 0; idx < 16; idx++) {
+		weint_data[idx].domain = d->wkup_irqd;
+		weint_data[idx].irq = idx;
+
+		irq = irq_of_parse_and_map(wkup_np, idx);
+		if (irq) {
+			irq_set_handler_data(irq, &weint_data[idx]);
+			irq_set_chained_handler(irq, exynos_irq_eint0_15);
+		} else {
+			dev_err(dev, "irq number for eint-%x not found\n", idx);
+		}
+	}
+	return 0;
+}
+
+/* pin banks of exynos4210 pin-controller 0 */
+static struct samsung_pin_bank exynos4210_pin_banks0[] = {
+	EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
+	EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
+	EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
+	EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
+	EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
+	EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
+	EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
+	EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
+	EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
+	EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
+	EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
+	EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
+	EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
+	EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
+	EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
+	EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
+};
+
+/* pin banks of exynos4210 pin-controller 1 */
+static struct samsung_pin_bank exynos4210_pin_banks1[] = {
+	EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
+	EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
+	EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
+	EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
+	EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
+	EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
+	EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
+	EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
+	EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
+	EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
+	EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
+	EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
+	EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
+	EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
+	EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
+	EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
+	EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
+	EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
+	EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
+	EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
+};
+
+/* pin banks of exynos4210 pin-controller 2 */
+static struct samsung_pin_bank exynos4210_pin_banks2[] = {
+	EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
+ * three gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
+	{
+		/* pin-controller instance 0 data */
+		.pin_banks	= exynos4210_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks0),
+		.base		= EXYNOS4210_GPIO_A0_START,
+		.nr_pins	= EXYNOS4210_GPIOA_NR_PINS,
+		.nr_gint	= EXYNOS4210_GPIOA_NR_GINT,
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.label		= "exynos4210-gpio-ctrl0",
+	}, {
+		/* pin-controller instance 1 data */
+		.pin_banks	= exynos4210_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks1),
+		.base		= EXYNOS4210_GPIOA_NR_PINS,
+		.nr_pins	= EXYNOS4210_GPIOB_NR_PINS,
+		.nr_gint	= EXYNOS4210_GPIOB_NR_GINT,
+		.nr_wint	= 32,
+		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,
+		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,
+		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,
+		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,
+		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,
+		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,
+		.svc		= EXYNOS_SVC_OFFSET,
+		.eint_gpio_init = exynos_eint_gpio_init,
+		.eint_wkup_init = exynos_eint_wkup_init,
+		.label		= "exynos4210-gpio-ctrl1",
+	}, {
+		/* pin-controller instance 2 data */
+		.pin_banks	= exynos4210_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks2),
+		.base		= EXYNOS4210_GPIOA_NR_PINS +
+					EXYNOS4210_GPIOB_NR_PINS,
+		.nr_pins	= EXYNOS4210_GPIOC_NR_PINS,
+		.label		= "exynos4210-gpio-ctrl2",
+	},
+};
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
new file mode 100644
index 0000000..5f27ba9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -0,0 +1,217 @@
+/*
+ * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * This file contains the Exynos specific definitions for the Samsung
+ * pinctrl/gpiolib interface drivers.
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define EXYNOS_GPIO_START(__gpio)	((__gpio##_START) + (__gpio##_NR))
+
+#define EXYNOS4210_GPIO_A0_NR	(8)
+#define EXYNOS4210_GPIO_A1_NR	(6)
+#define EXYNOS4210_GPIO_B_NR	(8)
+#define EXYNOS4210_GPIO_C0_NR	(5)
+#define EXYNOS4210_GPIO_C1_NR	(5)
+#define EXYNOS4210_GPIO_D0_NR	(4)
+#define EXYNOS4210_GPIO_D1_NR	(4)
+#define EXYNOS4210_GPIO_E0_NR	(5)
+#define EXYNOS4210_GPIO_E1_NR	(8)
+#define EXYNOS4210_GPIO_E2_NR	(6)
+#define EXYNOS4210_GPIO_E3_NR	(8)
+#define EXYNOS4210_GPIO_E4_NR	(8)
+#define EXYNOS4210_GPIO_F0_NR	(8)
+#define EXYNOS4210_GPIO_F1_NR	(8)
+#define EXYNOS4210_GPIO_F2_NR	(8)
+#define EXYNOS4210_GPIO_F3_NR	(6)
+#define EXYNOS4210_GPIO_J0_NR	(8)
+#define EXYNOS4210_GPIO_J1_NR	(5)
+#define EXYNOS4210_GPIO_K0_NR	(7)
+#define EXYNOS4210_GPIO_K1_NR	(7)
+#define EXYNOS4210_GPIO_K2_NR	(7)
+#define EXYNOS4210_GPIO_K3_NR	(7)
+#define EXYNOS4210_GPIO_L0_NR	(8)
+#define EXYNOS4210_GPIO_L1_NR	(3)
+#define EXYNOS4210_GPIO_L2_NR	(8)
+#define EXYNOS4210_GPIO_Y0_NR	(6)
+#define EXYNOS4210_GPIO_Y1_NR	(4)
+#define EXYNOS4210_GPIO_Y2_NR	(6)
+#define EXYNOS4210_GPIO_Y3_NR	(8)
+#define EXYNOS4210_GPIO_Y4_NR	(8)
+#define EXYNOS4210_GPIO_Y5_NR	(8)
+#define EXYNOS4210_GPIO_Y6_NR	(8)
+#define EXYNOS4210_GPIO_X0_NR	(8)
+#define EXYNOS4210_GPIO_X1_NR	(8)
+#define EXYNOS4210_GPIO_X2_NR	(8)
+#define EXYNOS4210_GPIO_X3_NR	(8)
+#define EXYNOS4210_GPIO_Z_NR	(7)
+
+enum exynos4210_gpio_xa_start {
+	EXYNOS4210_GPIO_A0_START	= 0,
+	EXYNOS4210_GPIO_A1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
+	EXYNOS4210_GPIO_B_START		= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
+	EXYNOS4210_GPIO_C0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
+	EXYNOS4210_GPIO_C1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
+	EXYNOS4210_GPIO_D0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
+	EXYNOS4210_GPIO_D1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
+	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
+	EXYNOS4210_GPIO_E1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
+	EXYNOS4210_GPIO_E2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
+	EXYNOS4210_GPIO_E3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
+	EXYNOS4210_GPIO_E4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
+	EXYNOS4210_GPIO_F0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
+	EXYNOS4210_GPIO_F1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
+	EXYNOS4210_GPIO_F2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
+	EXYNOS4210_GPIO_F3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
+};
+
+enum exynos4210_gpio_xb_start {
+	EXYNOS4210_GPIO_J0_START	= 0,
+	EXYNOS4210_GPIO_J1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
+	EXYNOS4210_GPIO_K0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
+	EXYNOS4210_GPIO_K1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
+	EXYNOS4210_GPIO_K2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
+	EXYNOS4210_GPIO_K3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
+	EXYNOS4210_GPIO_L0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
+	EXYNOS4210_GPIO_L1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
+	EXYNOS4210_GPIO_L2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
+	EXYNOS4210_GPIO_Y0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
+	EXYNOS4210_GPIO_Y1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
+	EXYNOS4210_GPIO_Y2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
+	EXYNOS4210_GPIO_Y3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
+	EXYNOS4210_GPIO_Y4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
+	EXYNOS4210_GPIO_Y5_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
+	EXYNOS4210_GPIO_Y6_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
+	EXYNOS4210_GPIO_X0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
+	EXYNOS4210_GPIO_X1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
+	EXYNOS4210_GPIO_X2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
+	EXYNOS4210_GPIO_X3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
+};
+
+enum exynos4210_gpio_xc_start {
+	EXYNOS4210_GPIO_Z_START		= 0,
+};
+
+#define	EXYNOS4210_GPIO_A0_IRQ		EXYNOS4210_GPIO_A0_START
+#define	EXYNOS4210_GPIO_A1_IRQ		EXYNOS4210_GPIO_A1_START
+#define	EXYNOS4210_GPIO_B_IRQ		EXYNOS4210_GPIO_B_START
+#define	EXYNOS4210_GPIO_C0_IRQ		EXYNOS4210_GPIO_C0_START
+#define	EXYNOS4210_GPIO_C1_IRQ		EXYNOS4210_GPIO_C1_START
+#define	EXYNOS4210_GPIO_D0_IRQ		EXYNOS4210_GPIO_D0_START
+#define	EXYNOS4210_GPIO_D1_IRQ		EXYNOS4210_GPIO_D1_START
+#define	EXYNOS4210_GPIO_E0_IRQ		EXYNOS4210_GPIO_E0_START
+#define	EXYNOS4210_GPIO_E1_IRQ		EXYNOS4210_GPIO_E1_START
+#define	EXYNOS4210_GPIO_E2_IRQ		EXYNOS4210_GPIO_E2_START
+#define	EXYNOS4210_GPIO_E3_IRQ		EXYNOS4210_GPIO_E3_START
+#define	EXYNOS4210_GPIO_E4_IRQ		EXYNOS4210_GPIO_E4_START
+#define	EXYNOS4210_GPIO_F0_IRQ		EXYNOS4210_GPIO_F0_START
+#define	EXYNOS4210_GPIO_F1_IRQ		EXYNOS4210_GPIO_F1_START
+#define	EXYNOS4210_GPIO_F2_IRQ		EXYNOS4210_GPIO_F2_START
+#define	EXYNOS4210_GPIO_F3_IRQ		EXYNOS4210_GPIO_F3_START
+#define	EXYNOS4210_GPIO_J0_IRQ		EXYNOS4210_GPIO_J0_START
+#define	EXYNOS4210_GPIO_J1_IRQ		EXYNOS4210_GPIO_J1_START
+#define	EXYNOS4210_GPIO_K0_IRQ		EXYNOS4210_GPIO_K0_START
+#define	EXYNOS4210_GPIO_K1_IRQ		EXYNOS4210_GPIO_K1_START
+#define	EXYNOS4210_GPIO_K2_IRQ		EXYNOS4210_GPIO_K2_START
+#define	EXYNOS4210_GPIO_K3_IRQ		EXYNOS4210_GPIO_K3_START
+#define	EXYNOS4210_GPIO_L0_IRQ		EXYNOS4210_GPIO_L0_START
+#define	EXYNOS4210_GPIO_L1_IRQ		EXYNOS4210_GPIO_L1_START
+#define	EXYNOS4210_GPIO_L2_IRQ		EXYNOS4210_GPIO_L2_START
+#define	EXYNOS4210_GPIO_Z_IRQ		EXYNOS4210_GPIO_Z_START
+
+#define EXYNOS4210_GPIOA_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
+#define EXYNOS4210_GPIOA_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
+#define EXYNOS4210_GPIOB_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
+#define EXYNOS4210_GPIOB_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
+#define EXYNOS4210_GPIOC_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
+
+/* External GPIO and wakeup interrupt related definitions */
+#define EXYNOS_GPIO_ECON_OFFSET		0x700
+#define EXYNOS_GPIO_EMASK_OFFSET	0x900
+#define EXYNOS_GPIO_EPEND_OFFSET	0xA00
+#define EXYNOS_WKUP_ECON_OFFSET		0xE00
+#define EXYNOS_WKUP_EMASK_OFFSET	0xF00
+#define EXYNOS_WKUP_EPEND_OFFSET	0xF40
+#define EXYNOS_SVC_OFFSET		0xB08
+
+/* helpers to access interrupt service register */
+#define EXYNOS_SVC_GROUP_SHIFT		3
+#define EXYNOS_SVC_GROUP_MASK		0x1f
+#define EXYNOS_SVC_NUM_MASK		7
+#define EXYNOS_SVC_GROUP(x)		((x >> EXYNOS_SVC_GROUP_SHIFT) & \
+						EXYNOS_SVC_GROUP_MASK)
+
+/* Exynos specific external interrupt trigger types */
+#define EXYNOS_EINT_LEVEL_LOW		0
+#define EXYNOS_EINT_LEVEL_HIGH		1
+#define EXYNOS_EINT_EDGE_FALLING	2
+#define EXYNOS_EINT_EDGE_RISING		3
+#define EXYNOS_EINT_EDGE_BOTH		4
+#define EXYNOS_EINT_CON_MASK		0xF
+#define EXYNOS_EINT_CON_LEN		4
+
+#define EXYNOS_EINT_MAX_PER_BANK	8
+#define EXYNOS_EINT_NR_WKUP_EINT
+
+#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id)		\
+	{						\
+		.pctl_offset	= reg,			\
+		.pin_base	= (__gpio##_START),	\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.conpdn_width	= 2,			\
+		.pudpdn_width	= 2,			\
+		.eint_type	= EINT_TYPE_NONE,	\
+		.name		= id			\
+	}
+
+#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id)		\
+	{						\
+		.pctl_offset	= reg,			\
+		.pin_base	= (__gpio##_START),	\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.conpdn_width	= 2,			\
+		.pudpdn_width	= 2,			\
+		.eint_type	= EINT_TYPE_GPIO,	\
+		.irq_base	= (__gpio##_IRQ),	\
+		.name		= id			\
+	}
+
+/**
+ * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.
+ * @bank: pin bank from which this gpio interrupt originates.
+ * @pin: pin number within the bank.
+ * @eint_offset: offset to be added to the con/pend/mask register bank base.
+ */
+struct exynos_geint_data {
+	struct samsung_pin_bank	*bank;
+	u32			pin;
+	u32			eint_offset;
+};
+
+/**
+ * struct exynos_weint_data: irq specific data for all the wakeup interrupts
+ * generated by the external wakeup interrupt controller.
+ * @domain: irq domain representing the external wakeup interrupts
+ * @irq: interrupt number within the domain.
+ */
+struct exynos_weint_data {
+	struct irq_domain	*domain;
+	u32			irq;
+};
-- 
1.6.6.rc2



From m.grzeschik at pengutronix.de  Thu Aug 23 07:01:36 2012
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Thu, 23 Aug 2012 13:01:36 +0200
Subject: [PATCH v2] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
Message-ID: <1345719696-25738-1-git-send-email-m.grzeschik@pengutronix.de>

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx51-imx53.c |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..7eba6ab 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -351,6 +351,18 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
 	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
 	clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80600.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80400.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80200.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");
 	clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
 	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
 	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -439,6 +451,18 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
 	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
 	clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80600.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80400.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80200.usb");
+	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80000.usb");
+	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80000.usb");
 	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
 	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
 	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
-- 
1.7.10.4



From kgene.kim at samsung.com  Thu Aug 23 07:06:35 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 23 Aug 2012 20:06:35 +0900
Subject: [GIT PULL] Samsung fixes for v3.6
Message-ID: <1d5f01cd811f$5c5de8c0$1519ba40$%kim@samsung.com>

Hi Arnd, Olof,

Here are Samsung fixes for v3.6

For HDMI, already HDMI support for EXYNOS in mainline kernel is broken
because its configuration moved to platform data but regarding platform data
didn't support yet. And others are for fix warnings.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
v3.6-samsung-fixes-1

Heiko Stuebner (2):
      ARM: S3C24XX: Add missing DMACH_DT_PROP
      ARM: S3C24XX: Fix s3c2410_dma_enqueue parameters

Sachin Kamat (3):
      ARM: Samsung: Make uart_save static in pm.c file
      ARM: SAMSUNG: Set HDMI platform data for Exynos4x12 SoCs
      ARM: EXYNOS: Set HDMI platform data in SMDKV310

Tushar Behera (2):
      ARM: SAMSUNG: Add API to set platform data for s5p-tv driver
      ARM: EXYNOS: Set HDMI platform data in Origen board

 arch/arm/mach-exynos/mach-origen.c        |    7 +++++++
 arch/arm/mach-exynos/mach-smdkv310.c      |    7 +++++++
 arch/arm/mach-s3c24xx/include/mach/dma.h  |    3 ++-
 arch/arm/plat-s3c24xx/dma.c               |    2 +-
 arch/arm/plat-samsung/devs.c              |   29
++++++++++++++++++++++++++++-
 arch/arm/plat-samsung/include/plat/hdmi.h |   16 ++++++++++++++++
 arch/arm/plat-samsung/pm.c                |    2 +-
 7 files changed, 62 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/hdmi.h



From broonie at opensource.wolfsonmicro.com  Thu Aug 23 07:06:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 12:06:47 +0100
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <20120823072629.GG10057@shlinux2.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822160241.GR7995@opensource.wolfsonmicro.com>
 <20120823072629.GG10057@shlinux2.ap.freescale.net>
Message-ID: <20120823110647.GU7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 03:26:30PM +0800, Dong Aisheng wrote:
> On Thu, Aug 23, 2012 at 12:02:41AM +0800, Mark Brown wrote:

> > It'd be good to provide a way of retrieving the regmap so that drivers
> > for subsystems with generic regmap code could use the framework features
> > (regulator is one example that I just mentioned in my other mail).

> Do you mean something like:
> regmap = syscon_regmap_dev_lookup(np, "fsl,anatop");
> regmap_write(regmap, reg, val);

> Then drivers can use generic regmap framework features rather than depend
> on what imx-syscon implemented, is that correct?

Yes, this is mainly for cases where the subsystem has helper functions
that can work with regmap.
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From thomas.abraham at linaro.org  Thu Aug 23 07:24:56 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:54:56 +0530
Subject: [PATCH v2 0/2] ARM: Exynos4-DT: Enable pinctrl driver support
Message-ID: <1345721098-32459-1-git-send-email-thomas.abraham@linaro.org>

This patch series enables support for pin controller driver for Exynos4210 SoC
based device tree enabled platforms. The first patch in this series adds the
pin group nodes for each of the three pin controller instances, but it is not
a exhaustive list of all possible pin group nodes. As the coverage of pinctrl
driver is extended device drivers used on Exynos4210 platforms, additional
pin group nodes can be added as required.

Thomas Abraham (2):
  ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
  ARM: EXYNOS: Enable pinctrl driver support for Exynos4 device tree enabled platform

 arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
 arch/arm/mach-exynos/Kconfig              |    2 +
 3 files changed, 496 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi



From thomas.abraham at linaro.org  Thu Aug 23 07:24:57 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:54:57 +0530
Subject: [PATCH v2 1/2] ARM: dts: Add pinctrl node entries for Samsung
 Exynos4210 SoC
In-Reply-To: <1345721098-32459-1-git-send-email-thomas.abraham@linaro.org>
References: <1345721098-32459-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345721098-32459-2-git-send-email-thomas.abraham@linaro.org>

Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/boot/dts/exynos4210-pinctrl.dtsi |  457 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi         |   37 +++
 2 files changed, 494 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi

diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 0000000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+	pinctrl at 11400000 {
+		uart0_data: uart0-data {
+			samsung,pins = "gpa0-0", "gpa0-1";
+			samsung,pin-function = <0x2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart0_fctl: uart0-fctl {
+			samsung,pins = "gpa0-2", "gpa0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_data: uart1-data {
+			samsung,pins = "gpa0-4", "gpa0-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart1_fctl: uart1-fctl {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c2_bus: i2c2-bus {
+			samsung,pins = "gpa0-6", "gpa0-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart2_data: uart2-data {
+			samsung,pins = "gpa1-0", "gpa1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart2_fctl: uart2-fctl {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart_audio_a: uart-audio-a {
+			samsung,pins = "gpa1-0", "gpa1-1";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c3_bus: i2c3-bus {
+			samsung,pins = "gpa1-2", "gpa1-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart3_data: uart3-data {
+			samsung,pins = "gpa1-4", "gpa1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		uart_audio_b: uart-audio-b {
+			samsung,pins = "gpa1-4", "gpa1-5";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi0_bus: spi0-bus {
+			samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c4_bus: i2c4-bus {
+			samsung,pins = "gpb-2", "gpb-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi1_bus: spi1-bus {
+			samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c5_bus: i2c5-bus {
+			samsung,pins = "gpb-6", "gpb-7";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s1_bus: i2s1-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm1_bus: pcm1-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		ac97_bus: ac97-bus {
+			samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+					"gpc0-4";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2s2_bus: i2s2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm2_bus: pcm2-bus {
+			samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+					"gpc1-4";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		spdif_bus: spdif-bus {
+			samsung,pins = "gpc1-0", "gpc1-1";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c6_bus: i2c6-bus {
+			samsung,pins = "gpc1-3", "gpc1-4";
+			samsung,pin-function = <4>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		spi2_bus: spi2-bus {
+			samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+			samsung,pin-function = <5>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c7_bus: i2c7-bus {
+			samsung,pins = "gpd0-2", "gpd0-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c0_bus: i2c0-bus {
+			samsung,pins = "gpd1-0", "gpd1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		i2c1_bus: i2c1-bus {
+			samsung,pins = "gpd1-2", "gpd1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl at 11000000 {
+		sd0_clk: sd0-clk {
+			samsung,pins = "gpk0-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_cmd: sd0-cmd {
+			samsung,pins = "gpk0-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_cd: sd0-cd {
+			samsung,pins = "gpk0-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus1: sd0-bus-width1 {
+			samsung,pins = "gpk0-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus4: sd0-bus-width4 {
+			samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd0_bus8: sd0-bus-width8 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_clk: sd4-clk {
+			samsung,pins = "gpk0-0";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_cmd: sd4-cmd {
+			samsung,pins = "gpk0-1";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_cd: sd4-cd {
+			samsung,pins = "gpk0-2";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus1: sd4-bus-width1 {
+			samsung,pins = "gpk0-3";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus4: sd4-bus-width4 {
+			samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd4_bus8: sd4-bus-width8 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <4>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_clk: sd1-clk {
+			samsung,pins = "gpk1-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_cmd: sd1-cmd {
+			samsung,pins = "gpk1-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_cd: sd1-cd {
+			samsung,pins = "gpk1-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_bus1: sd1-bus-width1 {
+			samsung,pins = "gpk1-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd1_bus4: sd1-bus-width4 {
+			samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_clk: sd2-clk {
+			samsung,pins = "gpk2-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_cmd: sd2-cmd {
+			samsung,pins = "gpk2-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_cd: sd2-cd {
+			samsung,pins = "gpk2-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus1: sd2-bus-width1 {
+			samsung,pins = "gpk2-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus4: sd2-bus-width4 {
+			samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd2_bus8: sd2-bus-width8 {
+			samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_clk: sd3-clk {
+			samsung,pins = "gpk3-0";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_cmd: sd3-cmd {
+			samsung,pins = "gpk3-1";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_cd: sd3-cd {
+			samsung,pins = "gpk3-2";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_bus1: sd3-bus-width1 {
+			samsung,pins = "gpk3-3";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		sd3_bus4: sd3-bus-width4 {
+			samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint0: ext-int0 {
+			samsung,pins = "gpx0-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint8: ext-int8 {
+			samsung,pins = "gpx1-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint15: ext-int15 {
+			samsung,pins = "gpx1-7";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint16: ext-int16 {
+			samsung,pins = "gpx2-0";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		eint31: ext-int31 {
+			samsung,pins = "gpx3-7";
+			samsung,pin-function = <0xf>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+
+	pinctrl at 03860000 {
+		i2s0_bus: i2s0-bus {
+			samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+					"gpz-4", "gpz-5", "gpz-6";
+			samsung,pin-function = <0x2>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+
+		pcm0_bus: pcm0-bus {
+			samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+					"gpz-4";
+			samsung,pin-function = <0x3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..a4bd0c9 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -20,6 +20,7 @@
 */
 
 /include/ "skeleton.dtsi"
+/include/ "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
@@ -29,6 +30,9 @@
 		spi0 = &spi_0;
 		spi1 = &spi_1;
 		spi2 = &spi_2;
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
 	};
 
 	gic:interrupt-controller at 10490000 {
@@ -50,6 +54,39 @@
 			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 	};
 
+	pinctrl_0: pinctrl at 11400000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11400000 0x1000>;
+		interrupts = <0 47 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	pinctrl_1: pinctrl at 11000000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x11000000 0x1000>;
+		interrupts = <0 46 0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		wakup_eint: wakeup-interrupt-controller {
+			compatible = "samsung,exynos4210-wakeup-eint";
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+					<0 32 0>;
+		};
+	};
+
+	pinctrl_2: pinctrl at 03860000 {
+		compatible = "samsung,pinctrl-exynos4210";
+		reg = <0x03860000 0x1000>;
+	};
+
 	watchdog at 10060000 {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x10060000 0x100>;
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Thu Aug 23 07:24:58 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Thu, 23 Aug 2012 16:54:58 +0530
Subject: [PATCH v2 2/2] ARM: EXYNOS: Enable pinctrl driver support for Exynos4
 device tree enabled platform
In-Reply-To: <1345721098-32459-1-git-send-email-thomas.abraham@linaro.org>
References: <1345721098-32459-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345721098-32459-3-git-send-email-thomas.abraham@linaro.org>

This enables support for Samsung and Exynos4 pinctrl driver for device
tree enabled Exynos4 platforms.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..195b50e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -405,6 +405,8 @@ config MACH_EXYNOS4_DT
 	select USE_OF
 	select ARM_AMBA
 	select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+	select PINCTRL
+	select PINCTRL_EXYNOS4
 	help
 	  Machine support for Samsung Exynos4 machine with device tree enabled.
 	  Select this if a fdt blob is available for the Exynos4 SoC based board.
-- 
1.6.6.rc2



From festevam at gmail.com  Thu Aug 23 07:13:38 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 23 Aug 2012 08:13:38 -0300
Subject: [PATCH v2] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <1345719696-25738-1-git-send-email-m.grzeschik@pengutronix.de>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
 <1345719696-25738-1-git-send-email-m.grzeschik@pengutronix.de>
Message-ID: <CAOMZO5AV5eYgjuxAHBi-r1-kA4w2ue3kGVqYYG83d4=qxUxhDw@mail.gmail.com>

Hi Michael,

On Thu, Aug 23, 2012 at 8:01 AM, Michael Grzeschik
<m.grzeschik at pengutronix.de> wrote:
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c |   24 ++++++++++++++++++++++++

Just curious: does the current Chip Idea USB driver work 'as is' on mx5?

Are you also going to submit the <soc>.dtsi and <board>.dts patches?

I would like to try it on a mx53qsb.

Regards,

Fabio Estevam


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 07:17:41 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 12:17:41 +0100
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <20120823071503.GF10057@shlinux2.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <20120822155953.GQ7995@opensource.wolfsonmicro.com>
 <20120823071503.GF10057@shlinux2.ap.freescale.net>
Message-ID: <20120823111741.GX7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 03:15:04PM +0800, Dong Aisheng wrote:
> On Wed, Aug 22, 2012 at 11:59:53PM +0800, Mark Brown wrote:

> > With the conversion to regmap it'd also be good to convert the driver to
> > use the regmap helper functions for enable and voltage operations if
> > possible.

> The anatop-regulator driver only implements set_voltage_sel/get_voltage_sel
> which i have already converted, what do you mean others like
> 'for enable and voltage operations' i should also convert?

Those operations should ideally be converted to use the generic regmap
implementation now the device uses regmap - regmap_get_voltage_sel_regmap
and so on.
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From broonie at opensource.wolfsonmicro.com  Thu Aug 23 07:22:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 12:22:04 +0100
Subject: [PATCH] ARM: OMAP2+: twl-common: Fix compile time error when
 omap-twl4030 audio is not enabled
In-Reply-To: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120823112204.GY7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 09:35:01AM +0300, Peter Ujfalusi wrote:
> Fixes:
> CC      arch/arm/mach-omap2/twl-common.o arch/arm/mach-omap2/twl-common.c:562: error: conflicting types for ?omap_twl4030_audio_init?
> arch/arm/mach-omap2/twl-common.h:62: error: previous declaration of ?omap_twl4030_audio_init? was here
> make[1]: *** [arch/arm/mach-omap2/twl-common.o] Error 1
> make: *** [arch/arm/mach-omap2] Error 2
> 
> When building the kernel with !SND_OMAP_SOC_OMAP_TWL4030

Which branch needs this?
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From arnd at arndb.de  Thu Aug 23 07:35:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 11:35:11 +0000
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <20120822214323.GA12255@n2100.arm.linux.org.uk>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
Message-ID: <201208231135.11688.arnd@arndb.de>

On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
> 
> On Wed, Aug 22, 2012 at 01:01:19PM +0000, Arnd Bergmann wrote:
> > These are lots of device drivers that include machine
> > specific header files from ARM platforms and that are
> > not easily scriptable. The changes have been found through
> > manual inspection and should cause no visible changes
> > because of the build script that maps the old names to the
> > new ones.
> 
> And you end up missing a bunch of drivers in the process, such as the
> sa1100 RTC driver which is shared between sa11x0 and PXA.  I wonder
> how many of the Samsung platforms get broken by this as well...

I'm well aware of the files that are not converted in this series,
but I'm also reasonably sure that I'm not breaking them in the process,
as long as we don't revert the first patch before the conversion is
done. I have added a list of the remaining ones at the end of this
email for reference. Most of them are for the Samsung platforms, and
they are already working on cleaning that up.

> In any case, what we should be doing here as well is moving the headers
> included by drivers for platform data out of the arch/arm/mach/ subtrees
> and into include/linux/platform_data.  That will substantially reduce the
> amount of mach/ headers to deal with.

I've just looked at the {mach,plat}/*.h files that get included in ARM
specific drivers. Out of the 342 header files that get used in this way,
I found 93 that are practically just platform data, and a few that
are platform_data mixed with something else.

How about I move all the pure platform data definition files now and
rebase the other patches on top of that. Here is a list of suggested
file names in include/linux/platform_data/:

mach-at91/at_hdmac.h		-> dma-atmel.h
mach-davinci/aemif.h		-> mtd-davinci-aemif.h
mach-davinci/asp.h		-> asoc-davinci-evm.h
mach-davinci/i2c.h		-> i2c-davinci.h
mach-davinci/keyscan.h		-> keyscan-davinci.h
mach-davinci/mmc.h		-> mmc-davinci.h
mach-davinci/nand.h		-> mtd-davinci.h
mach-davinci/spi.h		-> spi-davinci.h
mach-davinci/usb.h		-> usb-davinci.h
mach-ep93xx/dma.h		-> dma-ep93xx.h
mach-ep93xx/ep93xx_keypad.h	-> keypad-ep93xx.h
mach-ep93xx/ep93xx_spi.h	-> spi-ep93xx.h
mach-ep93xx/fb.h		-> video-ep93xx.h
mach-exynos/ohci.h		-> usb-exynos.h
mach-imx/dma.h			-> dma-imx.h
mach-imx/esdhc.h		-> mmc-esdhc-imx.h
mach-imx/i2c.h			-> i2c-imx.h
mach-imx/imx-uart.h		-> serial-imx.h
mach-imx/imxfb.h		-> video-imxfb.h
mach-imx/mmc.h			-> mmc-mxcmmc.h
mach-imx/mx1_camera.h		-> camera-mx1.h
mach-imx/mx21-usbhost.h		-> usb-mx2.h
mach-imx/mx2_cam.h		-> camera-mx2.h
mach-imx/mx3_camera.h		-> camera-mx3.h
mach-imx/mx3fb.h		-> video-mx3fb.h
mach-imx/mxc_ehci.h		-> usb-ehci-mxc.h
mach-imx/mxc_nand.h		-> mtd-mxc_nand.h
mach-imx/sdma.h			-> dma-imx-sdma.h
mach-imx/spi.h			-> spi-imx.h
mach-imx/ssi.h			-> asoc-imx-ssi.h
mach-imx/usb.h			-> usb-imx_udc.h
mach-kirkwood/leds-netxbig.h	-> leds-kirkwood-netxbig.h
mach-kirkwood/leds-ns2.h	-> leds-kirkwood-ns2.h
mach-mmp/sram.h			-> dma-mmp_tdma.h
mach-msm/mmc.h			-> mmc-msm_sdcc.h
mach-msm/msm_fb.h		-> video-msm_fb.h
mach-netx/eth.h			-> eth-netx.h
mach-nomadik/nand.h		-> mtd-nomadik-nand.h
mach-pxa/arcom-pcmcia.h		-> pcmcia-pxa2xx_viper.h
mach-pxa/camera.h		-> camera-pxa.h
mach-pxa/irda.h			-> irda-pxaficp.h
mach-pxa/mmc.h			-> mmc-pxamci.h
mach-pxa/ohci.h			-> usb-ohci-pxa27x.h
mach-pxa/palmasoc.h		-> asoc-palm27x.h
mach-pxa/pata_pxa.h		-> ata-pxa.h
mach-pxa/pxa3xx-u2d.h		-> usb-ohci-pxa27x.h
mach-pxa/pxa930_rotary.h	-> keyboard-pxa930_rotary.h
mach-pxa/pxa930_trkball.h	-> mouse-pxa930_trkball.h
mach-pxa/pxafb.h		-> video-pxafb.h
mach-s3c24xx/leds-gpio.h	-> leds-s3c24xx.h
mach-sa1100/mcp.h		-> mfd-mcp-sa11x0.h
mach-tegra/kbc.h		-> keyboard-tegra-kbc.h
mach-tegra/sdhci.h		-> mmc-sdhci-tegra.h
mach-tegra/tegra_wm8903_pdata.h	-> asoc-tegra_wm8903.h
mach-u300/gpio-u300.h		-> pinctrl-coh901.h
mach-ux500/crypto-ux500.h	-> crypto-ux500.h
mach-ux500/usb.h		-> usb-musb-ux500.h
mach-ux500/msp.h		-> asoc-ux500-msp.h
mach-vt8500/vt8500fb.h		-> video-vt8500lcdfb.h
mach-w90x900/fb.h		-> video-nuc900fb.h
mach-w90x900/i2c.h		-> i2c-nuc900.h
mach-w90x900/nuc900_spi.h	-> spi-nuc900.h
mach-w90x900/w90p910_keypad.h	-> keypad-w90p910.h
plat-nomadik/ske.h		-> keypad-nomadik-ske.h
plat-omap/dsp.h			-> dsp-omap.h
plat-omap/keypad.h		-> keypad-omap.h
plat-omap/lcd_mipid.h		-> lcd-mipid.h
plat-omap/mcbsp.h		-> dsp-mcbsp.h
plat-omap/mcspi.h		-> spi-omap2-mcspi.h
plat-omap/nand.h		-> mtd-nand-omap2.h
plat-omap/onenand.h		-> mtd-onenand-omap2.h
plat-omap/remoteproc.h		-> remoteproc-omap.h
plat-omap/voltage.h		-> smartreflex-omap.h
plat-orion/audio.h		-> asoc-kirkwood.h
plat-orion/ehci-orion.h		-> usb-ehci-orion.h
plat-orion/mv_xor.h		-> dma-mv_xor.h
plat-orion/mvsdio.h		-> mmc-mvsdio.h
plat-orion/orion_nand.h		-> mtd-orion_nand.h
plat-pxa/pxa27x_keypad.h	-> keypad-pxa27x.h
plat-pxa/pxa3xx_nand.h		-> mtd-nand-pxa3xx.h
plat-samsung/ata.h		-> ata-samsung_cf.h
plat-samsung/audio-simtec.h	-> asoc-s3c24xx_simtec.h
plat-samsung/audio.h		-> asoc-s3c.h
plat-samsung/ehci.h		-> usb-ehci-s5p.h
plat-samsung/hwmon.h		-> hwmon-s3c.h
plat-samsung/iic.h		-> i2c-s3c2410.h
plat-samsung/mci.h		-> mmc-s3cmci.h
plat-samsung/mipi_csis.h	-> mipi-csis.h
plat-samsung/nand.h		-> mtd-nand-s3c2410.h
plat-samsung/s3c64xx-spi.h	-> spi-s3c64xx.h
plat-samsung/ts.h		-> touchscreen-s3c2410.h
plat-samsung/udc.h		-> usb-s3c2410_udc.h
plat-samsung/usb-control.h	-> usb-ohci-s3c2410.h
plat-spear/keyboard.h		-> keyboard-spear.h

> Where I want this to get to is not a persistence of the existing crappy
> situation where platforms stuff platform data definitions into arch/arm,
> but instead put them in the right place.

Agreed.

> That means providing them with a good reason why the existing solution
> won't work, and not allowing mach/ includes in drivers is a very good
> way to achieve that.

About two third of the platform header files included in device drivers
are not related to platform_data according to what I found. Most of them
are also wrong (hardcoding interrupt numbers or addresses, headers
included by accident but not actually used, driver specific definitions
that don't belong in the platform, platform specific abstraction layers,
...), but they tend to be harder to clean up.

I hope we can get there eventually, but I think the intermediate step
of enforcing a mach-${MACH}/foo.h is a step in the right direction on
that way. While my immediate goal of course is to get the multiplatform
kernel running and not to clean up the mess with mach headers, I think
it's good if the dependency on a specific platform is highlighted in the
source code so it can be picked on better in reviews.

	Arnd

** list of mach/* inclusions that I could not match with
** exactly one ARM platform:

$ git grep ^#include.*\<mach/  drivers/ sound/ include/ arch/arm/
arch/arm/boot/compressed/head.S:#include <mach/debug-macro.S>
arch/arm/boot/compressed/misc.c:#include <mach/uncompress.h>
arch/arm/boot/compressed/mmcif-sh7372.c:#include <mach/mmc.h>
arch/arm/boot/compressed/sdhi-sh7372.c:#include <mach/mmc.h>
arch/arm/common/locomo.c:#include <mach/hardware.h>
arch/arm/common/sa1111.c:#include <mach/hardware.h>
arch/arm/include/asm/barrier.h:#include <mach/barriers.h>
arch/arm/include/asm/clkdev.h:#include <mach/clkdev.h>
arch/arm/include/asm/dma.h:#include <mach/isa-dma.h>
arch/arm/include/asm/floppy.h:#include <mach/floppy.h>
arch/arm/include/asm/gpio.h:#include <mach/gpio.h>
arch/arm/include/asm/hardware/dec21285.h:#include <mach/hardware.h>
arch/arm/include/asm/hardware/iop3xx-adma.h:#include <mach/hardware.h>
arch/arm/include/asm/hardware/iop3xx-gpio.h:#include <mach/hardware.h>
arch/arm/include/asm/hardware/it8152.h:#include <mach/irqs.h>
arch/arm/include/asm/hardware/sa1111.h:#include <mach/bitfield.h>
arch/arm/include/asm/io.h:#include <mach/io.h>
arch/arm/include/asm/irq.h:#include <mach/irqs.h>
arch/arm/include/asm/memory.h:#include <mach/memory.h>
arch/arm/include/asm/mtd-xip.h:#include <mach/mtd-xip.h>
arch/arm/include/asm/timex.h:#include <mach/timex.h>
arch/arm/kernel/debug.S:#include <mach/debug-macro.S>
arch/arm/kernel/entry-armv.S:#include <mach/entry-macro.S>
arch/arm/kernel/entry-common.S:#include <mach/entry-macro.S>
arch/arm/kernel/head.S:#include <mach/debug-macro.S>
arch/arm/mm/proc-sa110.S:#include <mach/hardware.h>
arch/arm/mm/proc-sa1100.S:#include <mach/hardware.h>
arch/arm/plat-iop/adma.c:#include <mach/adma.h>
arch/arm/plat-iop/i2c.c:#include <mach/hardware.h>
arch/arm/plat-iop/pci.c:#include <mach/hardware.h>
arch/arm/plat-iop/pmu.c:#include <mach/irqs.h>
arch/arm/plat-iop/restart.c:#include <mach/hardware.h>
arch/arm/plat-iop/time.c:#include <mach/hardware.h>
arch/arm/plat-iop/time.c:#include <mach/time.h>
arch/arm/plat-omap/debug-devices.c:#include <mach/hardware.h>
arch/arm/plat-omap/debug-leds.c:#include <mach/hardware.h>
arch/arm/plat-omap/devices.c:#include <mach/hardware.h>
arch/arm/plat-omap/dma.c:#include <mach/hardware.h>
arch/arm/plat-omap/dmtimer.c:#include <mach/hardware.h>
arch/arm/plat-omap/fb.c:#include <mach/hardware.h>
arch/arm/plat-omap/i2c.c:#include <mach/irqs.h>
arch/arm/plat-omap/include/plat-omap/gpio.h:#include <mach/irqs.h>
arch/arm/plat-omap/include/plat-omap/irqs.h:#include <mach/hardware.h>
arch/arm/plat-orion/common.c:#include <mach/bridge-regs.h>
arch/arm/plat-orion/mpp.c:#include <mach/hardware.h>
arch/arm/plat-pxa/dma.c:#include <mach/hardware.h>
arch/arm/plat-pxa/dma.c:#include <mach/dma.h>
arch/arm/plat-pxa/ssp.c:#include <mach/hardware.h>
arch/arm/plat-samsung/clock.c:#include <mach/hardware.h>
arch/arm/plat-samsung/cpu.c:#include <mach/map.h>
arch/arm/plat-samsung/devs.c:#include <mach/hardware.h>
arch/arm/plat-samsung/devs.c:#include <mach/dma.h>
arch/arm/plat-samsung/devs.c:#include <mach/irqs.h>
arch/arm/plat-samsung/devs.c:#include <mach/map.h>
arch/arm/plat-samsung/dma-ops.c:#include <mach/dma.h>
arch/arm/plat-samsung/dma.c:#include <mach/dma.h>
arch/arm/plat-samsung/dma.c:#include <mach/irqs.h>
arch/arm/plat-samsung/include/plat-samsung/dma-ops.h:#include <mach/dma.h>
arch/arm/plat-samsung/include/plat-samsung/irq.h:#include <mach/hardware.h>
arch/arm/plat-samsung/include/plat-samsung/irq.h:#include <mach/regs-irq.h>
arch/arm/plat-samsung/include/plat-samsung/irq.h:#include <mach/regs-gpio.h>
arch/arm/plat-samsung/include/plat-samsung/regs-onenand.h:#include <mach/hardware.h>
arch/arm/plat-samsung/include/plat-samsung/regs-srom.h:#include <mach/map.h>
arch/arm/plat-samsung/include/plat-samsung/watchdog-reset.h:#include <mach/map.h>
arch/arm/plat-samsung/init.c:#include <mach/hardware.h>
arch/arm/plat-samsung/irq-vic-timer.c:#include <mach/map.h>
arch/arm/plat-samsung/pm.c:#include <mach/hardware.h>
arch/arm/plat-samsung/pm.c:#include <mach/map.h>
arch/arm/plat-samsung/pm.c:#include <mach/regs-clock.h>
arch/arm/plat-samsung/pm.c:#include <mach/regs-irq.h>
arch/arm/plat-samsung/pm.c:#include <mach/pm-core.h>
arch/arm/plat-samsung/pwm-clock.c:#include <mach/hardware.h>
arch/arm/plat-samsung/pwm-clock.c:#include <mach/map.h>
arch/arm/plat-samsung/s3c-dma-ops.c:#include <mach/dma.h>
arch/arm/plat-samsung/s5p-clock.c:#include <mach/regs-clock.h>
arch/arm/plat-samsung/s5p-dev-mfc.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-dev-uart.c:#include <mach/hardware.h>
arch/arm/plat-samsung/s5p-dev-uart.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-irq-eint.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-irq-eint.c:#include <mach/regs-gpio.h>
arch/arm/plat-samsung/s5p-irq-gpioint.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-irq-pm.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-irq-pm.c:#include <mach/regs-gpio.h>
arch/arm/plat-samsung/s5p-irq-pm.c:#include <mach/regs-irq.h>
arch/arm/plat-samsung/s5p-irq.c:#include <mach/map.h>
arch/arm/plat-samsung/s5p-time.c:#include <mach/map.h>
arch/arm/plat-samsung/setup-mipiphy.c:#include <mach/regs-clock.h>
arch/arm/plat-samsung/time.c:#include <mach/map.h>
arch/arm/plat-samsung/time.c:#include <mach/regs-irq.h>
arch/arm/plat-samsung/time.c:#include <mach/tick.h>
arch/arm/plat-spear/include/plat-spear/debug-macro.S:#include <mach/spear.h>
arch/arm/plat-spear/include/plat-spear/uncompress.h:#include <mach/spear.h>
arch/arm/plat-spear/pl080.c:#include <mach/spear.h>
arch/arm/plat-spear/pl080.c:#include <mach/misc_regs.h>
arch/arm/plat-spear/restart.c:#include <mach/spear.h>
arch/arm/plat-spear/restart.c:#include <mach/generic.h>
arch/arm/plat-spear/time.c:#include <mach/generic.h>
arch/arm/plat-versatile/clock.c:#include <mach/clkdev.h>
arch/arm/plat-versatile/leds.c:#include <mach/hardware.h>
arch/arm/plat-versatile/leds.c:#include <mach/platform.h>
drivers/ata/pata_at32.c:#include <mach/board.h>
drivers/ata/pata_at32.c:#include <mach/smc.h>
drivers/ata/pata_ep93xx.c:#include <mach/dma.h>
drivers/ata/pata_ep93xx.c:#include <mach/platform.h>
drivers/cdrom/gdrom.c:#include <mach/dma.h>
drivers/cdrom/gdrom.c:#include <mach/sysasic.h>
drivers/clk/spear/spear1310_clock.c:#include <mach/spear.h>
drivers/clk/spear/spear1340_clock.c:#include <mach/spear.h>
drivers/clk/spear/spear3xx_clock.c:#include <mach/misc_regs.h>
drivers/clk/spear/spear6xx_clock.c:#include <mach/misc_regs.h>
drivers/clk/versatile/clk-integrator.c:#include <mach/hardware.h>
drivers/clk/versatile/clk-integrator.c:#include <mach/platform.h>
drivers/cpufreq/s5pv210-cpufreq.c:#include <mach/regs-clock.h>
drivers/crypto/ux500/cryp/cryp.c:#include <mach/hardware.h>
drivers/dma/iop-adma.c:#include <mach/adma.h>
drivers/dma/tegra20-apb-dma.c:#include <mach/clk.h>
drivers/gpio/gpio-sa1100.c:#include <mach/hardware.h>
drivers/gpio/gpio-sa1100.c:#include <mach/irqs.h>
drivers/gpio/gpio-samsung.c:#include <mach/hardware.h>
drivers/gpio/gpio-samsung.c:#include <mach/map.h>
drivers/gpio/gpio-samsung.c:#include <mach/regs-clock.h>
drivers/gpio/gpio-samsung.c:#include <mach/regs-gpio.h>
drivers/i2c/busses/i2c-puv3.c:#include <mach/hardware.h>
drivers/input/keyboard/bf54x-keys.c:#include <mach/bf54x_keys.h>
drivers/input/keyboard/omap-keypad.c:#include <mach/hardware.h>
drivers/input/keyboard/pxa27x_keypad.c:#include <mach/hardware.h>
drivers/input/serio/i8042-unicore32io.h:#include <mach/hardware.h>
drivers/input/touchscreen/hp680_ts_input.c:#include <mach/hp6xx.h>
drivers/leds/leds-hp6xx.c:#include <mach/hp6xx.h>
drivers/leds/leds-locomo.c:#include <mach/hardware.h>
drivers/media/video/s5p-tv/sii9234_drv.c:#include <mach/gpio.h>
drivers/mmc/host/atmel-mci.c:#include <mach/atmel-mci.h>
drivers/mmc/host/atmel-mci.c:#include <mach/cpu.h>
drivers/mmc/host/atmel-mci.c:#include <mach/board.h>
drivers/mtd/maps/ixp2000.c:#include <mach/hardware.h>
drivers/mtd/nand/atmel_nand.c:#include <mach/cpu.h>
drivers/mtd/nand/h1910.c:#include <mach/hardware.h>
drivers/mtd/nand/h1910.c:#include <mach/h1900-gpio.h>
drivers/mtd/nand/h1910.c:#include <mach/ipaq.h>
drivers/mtd/nand/orion_nand.c:#include <mach/hardware.h>
drivers/mtd/nand/pxa3xx_nand.c:#include <mach/dma.h>
drivers/net/caif/caif_shm_u5500.c:#include <mach/mbox-db5500.h>
drivers/net/ethernet/adi/bfin_mac.c:#include <mach/pll.h>
drivers/pcmcia/pxa2xx_sharpsl.c:#include <mach/hardware.h>
drivers/pcmcia/sa1111_generic.c:#include <mach/hardware.h>
drivers/pcmcia/soc_common.c:#include <mach/hardware.h>
drivers/pwm/pwm-samsung.c:#include <mach/map.h>
drivers/rtc/rtc-ds1302.c:#include <mach/secureedge5410.h>
drivers/rtc/rtc-puv3.c:#include <mach/hardware.h>
drivers/rtc/rtc-s3c.c:#include <mach/hardware.h>
drivers/rtc/rtc-sa1100.c:#include <mach/hardware.h>
drivers/rtc/rtc-sa1100.c:#include <mach/irqs.h>
drivers/rtc/rtc-sa1100.c:#include <mach/regs-rtc.h>
drivers/sh/maple/maple.c:#include <mach/dma.h>
drivers/sh/maple/maple.c:#include <mach/sysasic.h>
drivers/spi/spi-atmel.c:#include <mach/board.h>
drivers/spi/spi-atmel.c:#include <mach/cpu.h>
drivers/spi/spi-s3c64xx.c:#include <mach/dma.h>
drivers/spi/spi-stmp.c:#include <mach/platform.h>
drivers/spi/spi-stmp.c:#include <mach/stmp3xxx.h>
drivers/spi/spi-stmp.c:#include <mach/dma.h>
drivers/spi/spi-stmp.c:#include <mach/regs-ssp.h>
drivers/spi/spi-stmp.c:#include <mach/regs-apbh.h>
drivers/tty/serial/atmel_serial.c:#include <mach/board.h>
drivers/tty/serial/samsung.c:#include <mach/hardware.h>
drivers/tty/serial/samsung.c:#include <mach/map.h>
drivers/usb/gadget/lpc32xx_udc.c:#include <mach/hardware.h>
drivers/usb/gadget/lpc32xx_udc.c:#include <mach/platform.h>
drivers/usb/gadget/lpc32xx_udc.c:#include <mach/irqs.h>
drivers/usb/gadget/lpc32xx_udc.c:#include <mach/board.h>
drivers/usb/gadget/omap_udc.c:#include <mach/usb.h>
drivers/usb/gadget/s3c-hsotg.c:#include <mach/map.h>
drivers/usb/gadget/s3c2410_udc.c:#include <mach/irqs.h>
drivers/usb/gadget/s3c2410_udc.c:#include <mach/hardware.h>
drivers/usb/gadget/s3c2410_udc.c:#include <mach/regs-irq.h>
drivers/usb/host/ohci-nxp.c:#include <mach/hardware.h>
drivers/usb/host/ohci-nxp.c:#include <mach/platform.h>
drivers/usb/host/ohci-nxp.c:#include <mach/irqs.h>
drivers/usb/host/ohci-omap.c:#include <mach/hardware.h>
drivers/usb/host/ohci-omap.c:#include <mach/irqs.h>
drivers/usb/host/ohci-omap.c:#include <mach/usb.h>
drivers/usb/otg/isp1301_omap.c:#include <mach/usb.h>
drivers/video/atmel_lcdfb.c:#include <mach/board.h>
drivers/video/atmel_lcdfb.c:#include <mach/cpu.h>
drivers/video/backlight/hp680_bl.c:#include <mach/hp6xx.h>
drivers/video/bf54x-lq043fb.c:#include <mach/bf54x-lq043.h>
drivers/video/fb-puv3.c:#include <mach/hardware.h>
drivers/video/pvr2fb.c:#include <mach/dma.h>
drivers/video/s3c-fb.c:#include <mach/map.h>
drivers/video/s3c2410fb.c:#include <mach/regs-lcd.h>
drivers/video/s3c2410fb.c:#include <mach/regs-gpio.h>
drivers/video/s3c2410fb.c:#include <mach/fb.h>
drivers/watchdog/iop_wdt.c:#include <mach/hardware.h>
drivers/watchdog/omap_wdt.c:#include <mach/hardware.h>
drivers/watchdog/orion_wdt.c:#include <mach/bridge-regs.h>
drivers/watchdog/pnx4008_wdt.c:#include <mach/hardware.h>
drivers/watchdog/s3c2410_wdt.c:#include <mach/map.h>
drivers/watchdog/sa1100_wdt.c:#include <mach/regs-ost.h>
drivers/watchdog/sa1100_wdt.c:#include <mach/reset.h>
drivers/watchdog/sa1100_wdt.c:#include <mach/hardware.h>
drivers/watchdog/stmp3xxx_wdt.c:#include <mach/platform.h>
drivers/watchdog/stmp3xxx_wdt.c:#include <mach/regs-rtc.h>
include/linux/maple.h:#include <mach/maple.h>
sound/sh/aica.c:#include <mach/sysasic.h>
sound/sh/sh_dac_audio.c:#include <mach/hp6xx.h>
sound/soc/fsl/imx-pcm-dma.c:#include <mach/dma.h>
sound/soc/fsl/imx-ssi.h:#include <mach/dma.h>
sound/soc/samsung/ac97.c:#include <mach/dma.h>
sound/soc/samsung/dma.c:#include <mach/hardware.h>
sound/soc/samsung/dma.c:#include <mach/dma.h>
sound/soc/samsung/goni_wm8994.c:#include <mach/gpio.h>
sound/soc/samsung/s3c-i2s-v2.c:#include <mach/dma.h>
sound/soc/samsung/s3c2412-i2s.c:#include <mach/dma.h>
sound/soc/samsung/s3c24xx-i2s.c:#include <mach/dma.h>
sound/soc/samsung/spdif.c:#include <mach/dma.h>


From mgr at pengutronix.de  Thu Aug 23 07:36:08 2012
From: mgr at pengutronix.de (Michael Grzeschik)
Date: Thu, 23 Aug 2012 13:36:08 +0200
Subject: [PATCH v2] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <CAOMZO5AV5eYgjuxAHBi-r1-kA4w2ue3kGVqYYG83d4=qxUxhDw@mail.gmail.com>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
 <1345719696-25738-1-git-send-email-m.grzeschik@pengutronix.de>
 <CAOMZO5AV5eYgjuxAHBi-r1-kA4w2ue3kGVqYYG83d4=qxUxhDw@mail.gmail.com>
Message-ID: <20120823113608.GF10429@pengutronix.de>

Hi Fabio,

On Thu, Aug 23, 2012 at 08:13:38AM -0300, Fabio Estevam wrote:
> On Thu, Aug 23, 2012 at 8:01 AM, Michael Grzeschik
> <m.grzeschik at pengutronix.de> wrote:
> > Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> > ---
> >  arch/arm/mach-imx/clk-imx51-imx53.c |   24 ++++++++++++++++++++++++
> 
> Just curious: does the current Chip Idea USB driver work 'as is' on mx5?

Not "as is" but we are working on it to get all patches for that
mainline. Currently there is the static CI13XXX_REQUIRE_TRANSCEIVER flag
in the ci13xxx_imx_data, which makes the socs with no real xceiver
depend on the nop-xceiver. But that one lags clk_prepare_{enable, disable}.
But we already prepared that in some, "hopefully ready for mainline", patches.

> Are you also going to submit the <soc>.dtsi and <board>.dts patches?

Yes, the dtsi patch is alread on the list:
http://www.spinics.net/lists/arm-kernel/msg190737.html

> I would like to try it on a mx53qsb.

we got it already running with that board and the above mentioned
dependencies.

Cheers,

Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 07:39:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 12:39:23 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823092216.GA27264@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
Message-ID: <20120823113922.GZ7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 10:22:17AM +0100, Lee Jones wrote:

> > > Just thinking about this now. I converted it to the current format at
> > > the request of Mark. If this isn't the correct method I'm not quite
> > > sure what is. If you want it to be registered as a device, then it
> > > needs to go into the Device Tree, but Mark doesn't want it in there
> > > because it doesn't actually represent hardware.

> I've just taken a closer look at this with a view to finding the most
> suitable solution. My conclusion is that although the PCM doesn't
> contain any registers, or represent hardware it should be a device and
> therefore be present in the Device Tree.

Your assumption that being a device in Linux means that something should
appear in the device tree definitely doesn't follow.

> PCM devices already represented in DTs:
>   fsl,mpc5200-pcm - written by Grant Likely, the author of Device Tree
>   phytec,pcm030   - written by Grant Likely, the author of Device Tree

I suspect Mitch might have a word or two to say about the above...  in
any case, these are *really* old PowerPC bindings which means they're
not always a good model.  Though in this case if you look at the code
you'll also see that the driver is actually directly managing hardware
with register I/O rather than just purely proxying an underlying DMA
API.  Clearly if there's actual hardware control involved a device is
appropriate.

> PCM devices which register as actual devices (should be in DT):

These are all Linux platform devices, things that are OK for purely
internal Linux usage which we can rewrite at will aren't always
appropriate for a cross platform DT.

> I propose to represent the PCM in the Device Tree again and have it
> probe just like all the other PCM devices in sound/soc.

> If you give me the nod, I'll revert this patch, enable the PCM for DT
> again and resent the patch-set in full.

I say I don't understand the motivation for this change.  All the modern
DT bindings are perfectly happy handling this without an explicit shim
in the device tree to bodge things for Linux, adding them in seems like
it'd be a retrograde step.  What benefit do you believe this brings?
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From festevam at gmail.com  Thu Aug 23 07:54:00 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 23 Aug 2012 08:54:00 -0300
Subject: [PATCH v2] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <20120823113608.GF10429@pengutronix.de>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
 <1345719696-25738-1-git-send-email-m.grzeschik@pengutronix.de>
 <CAOMZO5AV5eYgjuxAHBi-r1-kA4w2ue3kGVqYYG83d4=qxUxhDw@mail.gmail.com>
 <20120823113608.GF10429@pengutronix.de>
Message-ID: <CAOMZO5CVK4MAS7kJprBuDR7rD7wqrUvzajCw=7LBf-j+LX4sjQ@mail.gmail.com>

Hi Michael,

On Thu, Aug 23, 2012 at 8:36 AM, Michael Grzeschik <mgr at pengutronix.de> wrote:

> we got it already running with that board and the above mentioned
> dependencies.

This is very good news. I will wait for the patches to reach the
mainling lists and then will have a try.

Thanks,

Fabio Estevam


From arnd at arndb.de  Thu Aug 23 08:09:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 12:09:26 +0000
Subject: [PATCHv4 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <1345679461.3601.20.camel@computer5.home>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221841.29645.arnd@arndb.de> <1345679461.3601.20.camel@computer5.home>
Message-ID: <201208231209.26707.arnd@arndb.de>

On Wednesday 22 August 2012, Tixy wrote:

> If you do feel so inclined for a v4 however ;-) you could also make the
> mls part of the patch tidier by moving the added #endif to instead
> terminate the preceding "#if __LINUX_ARM_ARCH__ >= 6", i.e.
> 
> @@ -367,8 +367,10 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
> +#endif
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> 
> 
> this looks funny in patch form, but the resulting source file is more
> consistent with other conditional tests.

Ok, here we go.

	Arnd


commit abfef4db8731591fbb721262bd4712662aaa6d14
Author: Arnd Bergmann <arnd at arndb.de>
Date:   Thu Aug 16 07:49:31 2012 +0000

    ARM: kprobes: make more tests conditional
    
    The mls instruction is not available in ARMv6K or below, so we
    should make the test conditional on at least ARMv7. ldrexd/strexd
    are available in ARMv6K or ARMv7, which we can test by checking
    the CONFIG_CPU_32v6K symbol.
    
    /tmp/ccuMTZ8D.s: Assembler messages:
    /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
    /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
    /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
    
    Signed-off-by: Arnd Bergmann <arnd at arndb.de>
    Cc: Jon Medhurst <tixy at yxit.co.uk>
    Cc: Russell King <rmk+kernel at arm.linux.org.uk>
    Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
    Cc: Leif Lindholm <leif.lindholm at arm.com>

diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 38c1a3b..8393129 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -366,7 +366,9 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
 	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
 	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
+#endif
 
+#if __LINUX_ARM_ARCH__ >= 7
 	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
 	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
 	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
@@ -456,6 +458,8 @@ void kprobe_arm_test_cases(void)
 	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
 #if __LINUX_ARM_ARCH__ >= 6
 	TEST_UNSUPPORTED("ldrex	r2, [sp]")
+#endif
+#if (__LINUX_ARM_ARCH__ >= 7) || defined(CONFIG_CPU_32v6K)
 	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
 	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
 	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")


From arnd at arndb.de  Thu Aug 23 08:12:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 12:12:04 +0000
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <CAMQu2gw_090MiWxs6m=5o0wQhL=ovmN1Y_7DUVhTbJU6mHPS5Q@mail.gmail.com>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <201208221722.06775.arnd@arndb.de>
 <CAMQu2gw_090MiWxs6m=5o0wQhL=ovmN1Y_7DUVhTbJU6mHPS5Q@mail.gmail.com>
Message-ID: <201208231212.04869.arnd@arndb.de>

On Thursday 23 August 2012, Shilimkar, Santosh wrote:
> I see your point but alternate patch is pushing down the fix to the low
> level driver and that means you end up patching more drivers when they
> use COUPLE idle infrastructure. That was the only reason I was thinking
> of suppressing the error at the source.
> 
> Since it is just for the random builds and actually doesn't impact the real
> functionality as such, I am fine with your proposed patch too.

Ok. It would be nice of course to test if this actually works on uniprocessor
configurations.

	Arnd


From Brian.Austin at cirrus.com  Thu Aug 23 08:14:29 2012
From: Brian.Austin at cirrus.com (Austin, Brian)
Date: Thu, 23 Aug 2012 12:14:29 +0000
Subject: [PATCH] ARM: OMAP2+: twl-common: Fix compile time error when
 omap-twl4030 audio is not enabled
In-Reply-To: <20120823112204.GY7995@opensource.wolfsonmicro.com>
References: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>,
 <20120823112204.GY7995@opensource.wolfsonmicro.com>
Message-ID: <6FD69376-72D1-4FA0-BDBE-47F581018244@cirrus.com>


> Which branch needs this?

for-next for sure, haven't tested on any other 



From lee.jones at linaro.org  Thu Aug 23 08:20:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 13:20:03 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823113922.GZ7995@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
Message-ID: <20120823121936.GA1047@gmail.com>

> I say I don't understand the motivation for this change.  All the modern
> DT bindings are perfectly happy handling this without an explicit shim
> in the device tree to bodge things for Linux, adding them in seems like
> it'd be a retrograde step.  What benefit do you believe this brings?

How do the all the other DT:ed audio drivers handle the PCM then? More
importantly, how would you like to see it handled? Ola has NACKed this
patch and explained why:

"I'm sorry but this patch is breaking the design of ASoC. The ASoC-
platform is the DMA-block (in combination with the MSP-block), and
there should be a platform-driver for the DMA/PCM. The platform-driver 
then has a DAI which is the MSP. The ASoC DAI-link-struct should have
one driver for each of these, so the dummy-driver for PCM should be
there."

So I don't really know where to go with it. Any ideas?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From anton.vorontsov at linaro.org  Thu Aug 23 08:22:39 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Thu, 23 Aug 2012 05:22:39 -0700
Subject: [V4 3/4] power_supply: Enable battery-charger for 88pm860x
In-Reply-To: <CACDDiy-ZzUxi4MvjELwHzYC+AxF0b0+LuOh=JdFBBgSA2ijjNw@mail.gmail.com>
References: <20120714081254.GD20018@lizard>
 <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
 <20120823034815.GB16674@lizard> <20120823044348.GA415@lizard>
 <CACDDiy-ZzUxi4MvjELwHzYC+AxF0b0+LuOh=JdFBBgSA2ijjNw@mail.gmail.com>
Message-ID: <20120823122239.GA29485@lizard>

On Thu, Aug 23, 2012 at 05:06:22PM +0800, jett zhou wrote:
> Thanks for helping me to amend these patch.  I got many good
> suggestions and learn a lot in this process:) BTW, you mean you will
> help to amend that several minor warning with battery tree?

Yup, I have these small fixups locally in my tree already, so if/once
Samuel gives me an Ack for the mfd part, I'll merge it into battery git
tree.

Thanks,

Anton.


From peter.ujfalusi at ti.com  Thu Aug 23 08:25:45 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 15:25:45 +0300
Subject: [PATCH] ARM: OMAP2+: twl-common: Fix compile time error when
 omap-twl4030 audio is not enabled
In-Reply-To: <20120823112204.GY7995@opensource.wolfsonmicro.com>
References: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>
 <20120823112204.GY7995@opensource.wolfsonmicro.com>
Message-ID: <50362149.6020107@ti.com>

On 08/23/2012 02:22 PM, Mark Brown wrote:
> Which branch needs this?

for-3.7, for-next and topic/omap needs this patch.

-- 
P?ter


From will.deacon at arm.com  Thu Aug 23 08:25:49 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 23 Aug 2012 13:25:49 +0100
Subject: [PATCHv3 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <1345679461.3601.20.camel@computer5.home>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221519.12056.arnd@arndb.de>
 <alpine.LFD.2.02.1208221136180.1754@xanadu.home>
 <201208221841.29645.arnd@arndb.de>
 <1345679461.3601.20.camel@computer5.home>
Message-ID: <20120823122549.GD13622@mudshark.cambridge.arm.com>

On Thu, Aug 23, 2012 at 12:51:01AM +0100, Tixy wrote:
> On Wed, 2012-08-22 at 18:41 +0000, Arnd Bergmann wrote:
> > On Wednesday 22 August 2012, Nicolas Pitre wrote:
> > > On Wed, 22 Aug 2012, Arnd Bergmann wrote:
> > > > > 
> > > > > The ldrex/strex instructions are available on ARMv6.  It's only the d 
> > > > > variants (strexd/ldrexd) which are only available from ARMv6k.
> > > > 
> > > > Ok. How is the version below then? I haven't tested this one yet.
> > > 
> > > In fact, I think the b variants are ARMv6k+ as well.  Only the plain 
> > > (non b non d) variants are available on ARMv6.
> > 
> > Ok, third attempt then. This leaves ldrex for ARMv6 but marks
> > {st,ld}rex{b,h,d} as V6K specific (which includes ARMv7).
> 
> ARMv7 does set CPU_32v6K, because arch/arm/mm/Kconfig has
> 
> config CPU_V7
> 	bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
> 	select CPU_32v6K
> 	select CPU_32v7
> 
> but this seems more for peripheral reasons not because all the various
> CPU configs systematically select the earlier architecture variants,
> e.g. CPU_V7 doesn't select CPU_32v6.
> 
> So I would have been inclined to test for
> 
> #if defined(CONFIG_CPU_32v6K) || (__LINUX_ARM_ARCH__ >= 7) 

FWIW, the selection of the optimised atomic64 implementation for ARM (which
uses the double-word exclusive instructions) boils down to CONFIG_CPU_32v6K,
so I think the additional __LINUX_ARM_ARCH__ check is probably overkill.

Will


From artem.bityutskiy at linux.intel.com  Thu Aug 23 08:37:39 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Thu, 23 Aug 2012 15:37:39 +0300
Subject: JFFS2 issue with v3.5.x and later on Atmel chips at least
In-Reply-To: <5035F266.2040909@atmel.com>
References: <5034B45A.5060107@atmel.com> <5034F3F8.9080802@atmel.com>
 <1345707689.2848.203.camel@sauron.fi.intel.com>
 <5035F266.2040909@atmel.com>
Message-ID: <1345725459.2848.238.camel@sauron.fi.intel.com>

On Thu, 2012-08-23 at 11:05 +0200, ludovic.desroches wrote:
> 
> Tested-by: Ludovic Desroches <ludovic.desroches at atmel.com> 

Thanks, pushed to l2-mtd.git tree a bit modified patch. Will ping dwmw2
about merging it to Linus.

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date: Thu, 23 Aug 2012 10:10:07 +0300
Subject: [PATCH] JFFS2: fix unmount regression

This patch fixes regression introduced by
"8bdc81c jffs2: get rid of jffs2_sync_super". We submit a delayed work in order
to make sure the write-buffer is synchronized at some point. But we do not
flush it when we unmount, which causes an oops when we unmount the file-system
and then the delayed work is executed.

This patch fixes the issue by adding a "cancel_delayed_work_sync()" infocation
in the '->sync_fs()' handler. This will make sure the delayed work is canceled
on sync, unmount and re-mount. And because VFS always callse 'sync_fs()' before
unmounting or remounting, this fixes the issue.

Reported-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: stable at vger.kernel.org [3.5+]
Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Tested-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 fs/jffs2/super.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/fs/jffs2/super.c b/fs/jffs2/super.c
index 61ea413..1224d6b 100644
--- a/fs/jffs2/super.c
+++ b/fs/jffs2/super.c
@@ -100,6 +100,10 @@ static int jffs2_sync_fs(struct super_block *sb, int wait)
 {
 	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
 
+#ifdef CONFIG_JFFS2_FS_WRITEBUFFER
+	cancel_delayed_work_sync(&c->wbuf_dwork);
+#endif
+
 	mutex_lock(&c->alloc_sem);
 	jffs2_flush_wbuf_pad(c);
 	mutex_unlock(&c->alloc_sem);
-- 
1.7.10.4


-- 
Best Regards,
Artem Bityutskiy
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From nicolas.ferre at atmel.com  Thu Aug 23 08:37:43 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 14:37:43 +0200
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <201208231135.11688.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de>
Message-ID: <50362417.9070600@atmel.com>

On 08/23/2012 01:35 PM, Arnd Bergmann :
> On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
>>
>> On Wed, Aug 22, 2012 at 01:01:19PM +0000, Arnd Bergmann wrote:
>>> These are lots of device drivers that include machine
>>> specific header files from ARM platforms and that are
>>> not easily scriptable. The changes have been found through
>>> manual inspection and should cause no visible changes
>>> because of the build script that maps the old names to the
>>> new ones.

[..]

> How about I move all the pure platform data definition files now and
> rebase the other patches on top of that. Here is a list of suggested
> file names in include/linux/platform_data/:
> 
> mach-at91/at_hdmac.h		-> dma-atmel.h

Fine with me. Maybe atmel-dma.h can better match what we already have in
this directory, but I do not know what is the policy in this directory...

[..]


> ** list of mach/* inclusions that I could not match with
> ** exactly one ARM platform:

In fact, for "*atmel*" type of files, they usually match *both* AVR32
and ARM/AT91 devices: so, we have to be careful about them...

Best regards,
-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Aug 23 08:41:28 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 14:41:28 +0200
Subject: [PATCH] arm: dts: remove partial parameter in at91sam9g25ek.dts
In-Reply-To: <1345191836-16523-1-git-send-email-voice.shen@atmel.com>
References: <1345191836-16523-1-git-send-email-voice.shen@atmel.com>
Message-ID: <503624F8.4070906@atmel.com>

On 08/17/2012 10:23 AM, Bo Shen :
> Remove the partial parameter in at91sam9g25ek.dts file
> 
> Signed-off-by: Bo Shen <voice.shen at atmel.com>

Included in at91-fixes for 3.6: thanks a lot.

> ---
>  arch/arm/boot/dts/at91sam9g25ek.dts |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
> index 7829a4d..96514c1 100644
> --- a/arch/arm/boot/dts/at91sam9g25ek.dts
> +++ b/arch/arm/boot/dts/at91sam9g25ek.dts
> @@ -15,7 +15,7 @@
>  	compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
>  
>  	chosen {
> -		bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
> +		bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
>  	};
>  
>  	ahb {
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Aug 23 08:44:38 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 14:44:38 +0200
Subject: [PATCH] atmel-ssc: include linux/io.h for raw io
In-Reply-To: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
References: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
Message-ID: <503625B6.1090204@atmel.com>

On 08/13/2012 09:59 PM, Joachim Eastwood :
> Include linux/io.h for raw io operations in atmel-scc header.
> 
> This fixes the following build error:
>   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
> sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
> sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'
> 
> Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>

Added to at91-fixes for 3.6. Thanks!

Arnd, can I queue this one in my upcoming pull-request to you?

> ---
>  include/linux/atmel-ssc.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
> index 0602339..4eb3175 100644
> --- a/include/linux/atmel-ssc.h
> +++ b/include/linux/atmel-ssc.h
> @@ -3,6 +3,7 @@
>  
>  #include <linux/platform_device.h>
>  #include <linux/list.h>
> +#include <linux/io.h>
>  
>  struct ssc_device {
>  	struct list_head	list;
> 


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Aug 23 08:51:25 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 14:51:25 +0200
Subject: [PATCH] atmel-ssc: include linux/io.h for raw io
In-Reply-To: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
References: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
Message-ID: <5036274D.8000803@atmel.com>

On 08/13/2012 09:59 PM, Joachim Eastwood :
> Include linux/io.h for raw io operations in atmel-scc header.
> 
> This fixes the following build error:
>   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
> sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
> sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'
>
> Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>

Liam, Mark,

May I have your Acked-by for this patch, I plan to queue it with my
other at91-related fixes in arm-soc tree?

Thanks, best regards,

> ---
>  include/linux/atmel-ssc.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
> index 0602339..4eb3175 100644
> --- a/include/linux/atmel-ssc.h
> +++ b/include/linux/atmel-ssc.h
> @@ -3,6 +3,7 @@
>  
>  #include <linux/platform_device.h>
>  #include <linux/list.h>
> +#include <linux/io.h>
>  
>  struct ssc_device {
>  	struct list_head	list;
> 


-- 
Nicolas Ferre


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 08:59:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 13:59:04 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823121936.GA1047@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
 <20120823121936.GA1047@gmail.com>
Message-ID: <20120823125903.GA7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 01:20:03PM +0100, Lee Jones wrote:
> > I say I don't understand the motivation for this change.  All the modern
> > DT bindings are perfectly happy handling this without an explicit shim
> > in the device tree to bodge things for Linux, adding them in seems like
> > it'd be a retrograde step.  What benefit do you believe this brings?

> How do the all the other DT:ed audio drivers handle the PCM then? More
> importantly, how would you like to see it handled? Ola has NACKed this
> patch and explained why:

They instantiate the PCM driver dynamically from the DAI when it's
probed which is pretty much what you're patch is doing.

> "I'm sorry but this patch is breaking the design of ASoC. The ASoC-
> platform is the DMA-block (in combination with the MSP-block), and
> there should be a platform-driver for the DMA/PCM. The platform-driver 
> then has a DAI which is the MSP. The ASoC DAI-link-struct should have
> one driver for each of these, so the dummy-driver for PCM should be
> there."

> So I don't really know where to go with it. Any ideas?

I think Ola is suggesting probing the DMA driver from the machine which
will also work though I'm not 100% sure if I'm parsing the above
correctly.  The issue in DT terms is that if the DMA controller is
shared with a bunch of other IPs then it should have one node shared
between them all and not a bunch of shim nodes inserted in the middle
which only exists due to the way Linux instantiates stuff.
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From santosh.shilimkar at ti.com  Thu Aug 23 09:00:18 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 23 Aug 2012 18:30:18 +0530
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <201208231212.04869.arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <201208221722.06775.arnd@arndb.de>
 <CAMQu2gw_090MiWxs6m=5o0wQhL=ovmN1Y_7DUVhTbJU6mHPS5Q@mail.gmail.com>
 <201208231212.04869.arnd@arndb.de>
Message-ID: <CAMQu2gzPMkbDvTfTOZVp+Qh=2=AHOuyt4NXtxAps=RmMF+mf6Q@mail.gmail.com>

On Thu, Aug 23, 2012 at 5:42 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>
> On Thursday 23 August 2012, Shilimkar, Santosh wrote:
> > I see your point but alternate patch is pushing down the fix to the low
> > level driver and that means you end up patching more drivers when they
> > use COUPLE idle infrastructure. That was the only reason I was thinking
> > of suppressing the error at the source.
> >
> > Since it is just for the random builds and actually doesn't impact the
> > real
> > functionality as such, I am fine with your proposed patch too.
>
> Ok. It would be nice of course to test if this actually works on
> uniprocessor
> configurations.
>
Have tested the patch and it does boot with UP build on OMAP.

Acked-tested-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From linux at prisktech.co.nz  Thu Aug 23 08:58:29 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 12:58:29 +0000
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <201208231040.16702.arnd@arndb.de>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>,
 <201208231040.16702.arnd@arndb.de>
Message-ID: <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>

>On Thursday 23 August 2012, Tony Prisk wrote:
>> Patchset based on Arnd's arm-soc/for-next branch.
>>
>>
>> Could I get this reviewed, hopefully for inclusion into v3.7.

>I can take them into the arm-soc tree if there are no new comments.
>For the last two patches, you need to get an Acked-by comment from the
>gpio and clk maintainers, respectively, or you should send them
>the patches for inclusion in those subsystem trees.

>        Arnd


Linus W has provided some feedback on the gpio driver - I missed the
issues he raised the first time around so just waiting for him to take a look
at v4 when he's got time.

I haven't heard from Mike T in regards to the new clock code - He did
reply about the original patch (pre-devicetree) but I asked him to hold off
reviewing it because it was going to be rewritten.

EHCI/UHCI has gone to -next (on patchv2) via usb-next
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
There haven't been any changes to it in v3/v4.

GPIO going via another tree isn't really an issue if necessary.

Without the clock patch (9/9), the mach-vt8500 patch (6/9) won't compile
due to unresolved symbols.

In arch/arm/mach-vt8500/vt8500.c - you will get an unresolved symbol
for 'vtwm_clk_init'

Not sure if this matters, thought I should point it out.
Does it need to compile cleanly in your tree (which is what I would assume),
or just once its all combined in -next?
Does it matter that the usb patches are already in -next?

I don't really understand the requirements around submitting to individual
trees and which (if any) of these points are actually issues.

Regards

Tony Prisk

From shawn.guo at linaro.org  Thu Aug 23 09:13:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 21:13:46 +0800
Subject: [GIT PULL] imx fixes for 3.6 (take 2)
In-Reply-To: <20120823093407.GE24242@S2101-09.ap.freescale.net>
References: <20120823093407.GE24242@S2101-09.ap.freescale.net>
Message-ID: <20120823131342.GF24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 05:34:11PM +0800, Shawn Guo wrote:
> Hi Arnd, Olof,
> 
> Please pull the following imx fixes for 3.6-rc.  Thanks.
> 
> Regards,
> Shawn
> 
> The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:
> 
>   Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)
> 
> are available in the git repository at:
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/fixes-for-3.6
> 
> Philipp Zabel (1):
>       ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path
> 
> Shawn Guo (3):
>       ARM: imx6q: remove imx_src_prepare_restart() call

I just noticed something wrong with this patch, so updated the branch
to drop it.  Please do not pull this one (if you already pulled the
branch).

Regards,
Shawn

>       ARM: imx6: spin the cpu until hardware takes it down
>       ARM: dts: imx51-babbage: fix esdhc cd/wp properties
> 
>  .../devicetree/bindings/mmc/fsl-imx-esdhc.txt      |    8 +++---
>  arch/arm/boot/dts/imx51-babbage.dts                |    4 +-
>  arch/arm/mach-imx/clk-imx6q.c                      |    8 ++++--
>  arch/arm/mach-imx/hotplug.c                        |   23 ++-----------------
>  arch/arm/mach-imx/mach-imx6q.c                     |    2 -
>  arch/arm/mach-imx/src.c                            |   13 -----------
>  arch/arm/plat-mxc/include/mach/common.h            |    1 -
>  7 files changed, 14 insertions(+), 45 deletions(-)


From arnd at arndb.de  Thu Aug 23 09:22:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 13:22:22 +0000
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231040.16702.arnd@arndb.de>
 <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>
Message-ID: <201208231322.23077.arnd@arndb.de>

On Thursday 23 August 2012, Tony Prisk wrote:
> >On Thursday 23 August 2012, Tony Prisk wrote:

> 
> Without the clock patch (9/9), the mach-vt8500 patch (6/9) won't compile
> due to unresolved symbols.
> 
> In arch/arm/mach-vt8500/vt8500.c - you will get an unresolved symbol
> for 'vtwm_clk_init'
> 
> Not sure if this matters, thought I should point it out.
> Does it need to compile cleanly in your tree (which is what I would assume),
> or just once its all combined in -next?
> Does it matter that the usb patches are already in -next?
> 
> I don't really understand the requirements around submitting to individual
> trees and which (if any) of these points are actually issues.

The rule is that each changeset should be free of regressions compared
to the version before. So if you have a set of 7 patches in one branch
that you want me to pick up, the result after applying those 7 patches
should work, and each previous step should also work. You cannot for
instance add a call to a function in one patch and then provide that
function in the following patch.

There are multiple ways to achieve this:

* when you have dependencies, get everything merged through one
maintainer tree, and get Acks for each patch that belongs to another
maintainer.

* submit a branch with the patches that other stuff depends on to
both the subsystem maintainer who is responsible for it and to
the subsystem maintainer who gets the other patches that are built
on top of this branch. If you do this, you have to make sure that
the first branch never gets rebased and that the second branch is
not sent before the first one is upstream.

* change the code so that no dependencies exist, e.g. by introducing
a dummy implementation in one patch and the proper one in another.
This can generate merge conflicts, but that's usually ok.

	Arnd



From lee.jones at linaro.org  Thu Aug 23 09:26:19 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 14:26:19 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823125903.GA7995@opensource.wolfsonmicro.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
 <20120823121936.GA1047@gmail.com>
 <20120823125903.GA7995@opensource.wolfsonmicro.com>
Message-ID: <20120823132618.GB1047@gmail.com>

> > "I'm sorry but this patch is breaking the design of ASoC. The ASoC-
> > platform is the DMA-block (in combination with the MSP-block), and
> > there should be a platform-driver for the DMA/PCM. The platform-driver 
> > then has a DAI which is the MSP. The ASoC DAI-link-struct should have
> > one driver for each of these, so the dummy-driver for PCM should be
> > there."
> 
> > So I don't really know where to go with it. Any ideas?
> 
> I think Ola is suggesting probing the DMA driver from the machine which
> will also work though I'm not 100% sure if I'm parsing the above
> correctly.  The issue in DT terms is that if the DMA controller is
> shared with a bunch of other IPs then it should have one node shared
> between them all and not a bunch of shim nodes inserted in the middle
> which only exists due to the way Linux instantiates stuff.

When you say 'machine', do you mean from arch/<arch>/mach-*? If so, I'm
keen for that not to happen.

> > How do the all the other DT:ed audio drivers handle the PCM then? More
> > importantly, how would you like to see it handled? Ola has NACKed this
> > patch and explained why:
> 
> They instantiate the PCM driver dynamically from the DAI when it's
> probed which is pretty much what you're patch is doing.

So they do it in the same why I have with this patch? Do you know why
Ola might think this is a bad idea?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From nicolas.ferre at atmel.com  Thu Aug 23 09:27:28 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 15:27:28 +0200
Subject: [PATCH] ARM: at91/feature-removal-schedule: delay at91_mci removal
Message-ID: <1345728448-29384-1-git-send-email-nicolas.ferre@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Delay sd/mmc driver at91_mci.c removal because of tight schedule to
move platform data to new driver atmel-mci.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi,

I plan to queue this one with the at91-fixes pull-request for 3.6. If you do
not feel it is a good idea, please say so.


 Documentation/feature-removal-schedule.txt |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index afaff31..f4d8c71 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -579,7 +579,7 @@ Why:	KVM tracepoints provide mostly equivalent information in a much more
 ----------------------------
 
 What:	at91-mci driver ("CONFIG_MMC_AT91")
-When:	3.7
+When:	3.8
 Why:	There are two mci drivers: at91-mci and atmel-mci. The PDC support
 	was added to atmel-mci as a first step to support more chips.
 	Then at91-mci was kept only for old IP versions (on at91rm9200 and
-- 
1.7.10



From arnd at arndb.de  Thu Aug 23 09:31:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 13:31:09 +0000
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <50362417.9070600@atmel.com>
References: <201208221253.07278.arnd@arndb.de>
 <201208231135.11688.arnd@arndb.de> <50362417.9070600@atmel.com>
Message-ID: <201208231331.09612.arnd@arndb.de>

On Thursday 23 August 2012, Nicolas Ferre wrote:
> > How about I move all the pure platform data definition files now and
> > rebase the other patches on top of that. Here is a list of suggested
> > file names in include/linux/platform_data/:
> > 
> > mach-at91/at_hdmac.h          -> dma-atmel.h
> 
> Fine with me. Maybe atmel-dma.h can better match what we already have in
> this directory, but I do not know what is the policy in this directory...

There does not seem to be a clear policy in that directory yet, so I
chose to put the subsystem name first. There have been a few subsystems
recently which adopted this naming scheme for their drivers, so it
seemed to be a good choice if we want to start a naming scheme that
sticks.
 
> > ** list of mach/* inclusions that I could not match with
> > ** exactly one ARM platform:
> 
> In fact, for "*atmel*" type of files, they usually match both AVR32
> and ARM/AT91 devices: so, we have to be careful about them...

Yes, I'm aware of that. My list did not include the mach/atmel-mci.h
or the mach/board.h files, which suffer from this problem and cannot
easily be merged.

	Arnd


From arnd at arndb.de  Thu Aug 23 09:31:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 13:31:38 +0000
Subject: [PATCH] atmel-ssc: include linux/io.h for raw io
In-Reply-To: <503625B6.1090204@atmel.com>
References: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
 <503625B6.1090204@atmel.com>
Message-ID: <201208231331.38883.arnd@arndb.de>

On Thursday 23 August 2012, Nicolas Ferre wrote:
> On 08/13/2012 09:59 PM, Joachim Eastwood :
> > Include linux/io.h for raw io operations in atmel-scc header.
> > 
> > This fixes the following build error:
> >   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
> > sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
> > sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
> > sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
> > sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'
> > 
> > Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
> 
> Added to at91-fixes for 3.6. Thanks!
> 
> Arnd, can I queue this one in my upcoming pull-request to you?
> 

Sure, no problem.

	Arnd


From linus.walleij at linaro.org  Thu Aug 23 09:31:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 Aug 2012 15:31:56 +0200
Subject: [rtc-linux] [PATCHv4 8/9] arm: vt8500: gpio: Devicetree support
 for arch-vt8500
In-Reply-To: <1345707346-9035-9-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <1345707346-9035-9-git-send-email-linux@prisktech.co.nz>
Message-ID: <CACRpkdYsUydqAfvYOKtQw9nBA4TpwF-=Af3kDUwwm6jbuiE68w@mail.gmail.com>

On Thu, Aug 23, 2012 at 9:35 AM, Tony Prisk <linux at prisktech.co.nz> wrote:

> Converted the existing arch-vt8500 gpio to a platform_device.
> Added support for WM8505 and WM8650 GPIO controllers.
> Replaced existing readl/writel calls with _relaxed variants.
> Replaced existing unsigned variables with u32 to match register size.
>
> Signed-off-by: Tony Prisk <linux at prisktech.co.nz>

Sweet!
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From arnd at arndb.de  Thu Aug 23 09:32:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 13:32:40 +0000
Subject: [PATCH 2/6] ARM: omap: allow building omap44xx without SMP
In-Reply-To: <CAMQu2gzPMkbDvTfTOZVp+Qh=2=AHOuyt4NXtxAps=RmMF+mf6Q@mail.gmail.com>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <201208231212.04869.arnd@arndb.de>
 <CAMQu2gzPMkbDvTfTOZVp+Qh=2=AHOuyt4NXtxAps=RmMF+mf6Q@mail.gmail.com>
Message-ID: <201208231332.40530.arnd@arndb.de>

On Thursday 23 August 2012, Shilimkar, Santosh wrote:
> 
> On Thu, Aug 23, 2012 at 5:42 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> >
> > On Thursday 23 August 2012, Shilimkar, Santosh wrote:
> > > I see your point but alternate patch is pushing down the fix to the low
> > > level driver and that means you end up patching more drivers when they
> > > use COUPLE idle infrastructure. That was the only reason I was thinking
> > > of suppressing the error at the source.
> > >
> > > Since it is just for the random builds and actually doesn't impact the
> > > real
> > > functionality as such, I am fine with your proposed patch too.
> >
> > Ok. It would be nice of course to test if this actually works on
> > uniprocessor
> > configurations.
> >
> Have tested the patch and it does boot with UP build on OMAP.
> 
> Acked-tested-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Ok, thanks a lot!

	Arnd


From linus.walleij at linaro.org  Thu Aug 23 09:34:08 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 Aug 2012 15:34:08 +0200
Subject: [rtc-linux] RE: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to
 Devicetree ***
In-Reply-To: <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231040.16702.arnd@arndb.de>
 <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>
Message-ID: <CACRpkda-xuo1+cunCb6bYdRsCn4CWuSLdxTjib=Gz1kqMz-xEQ@mail.gmail.com>

On Thu, Aug 23, 2012 at 2:58 PM, Tony Prisk <linux at prisktech.co.nz> wrote:

> Linus W has provided some feedback on the gpio driver - I missed the
> issues he raised the first time around so just waiting for him to take a look
> at v4 when he's got time.

Reviewed and OK:ed, looking good now.

Yours,
Linus Walleij


From benoit.thebaudeau at advansee.com  Thu Aug 23 09:36:54 2012
From: benoit.thebaudeau at advansee.com (=?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?=)
Date: Thu, 23 Aug 2012 15:36:54 +0200 (CEST)
Subject: [BUG] leds-pwm: First setting of brightness does nothing
In-Reply-To: <322770447.2755463.1345727876098.JavaMail.root@advansee.com>
Message-ID: <320569847.2756382.1345729013971.JavaMail.root@advansee.com>

Hi all,

I have found a bug using leds-pwm with the i.MX PWM driver. The first time a
non-0 brightness is set through sysfs, this has no effect. It works fine from
the 2nd time.

The cause of this bug is that leds-pwm.c:led_pwm_set() calls pwm_config() before
pwm_enable(), while in the i.MX PWM driver pwm_enable() enables the PWM IP
clock, so that a call to pwm_config() has no effect before the first call to
pwm_enable().

Several other PWM drivers in drivers/pwm/ work in the same way. pwm-beeper.c and
pwm_bl.c also call pwm_config() before pwm_enable(). The PWM documentation does
not say if the wrong doers are these PWM users or the i.MX-like PWM drivers.

So what should be fixed? Fixing these PWM users would be quite easy since it's a
simple swap of the pwm_config() and pwm_enable() calls. This should not produce
any glitch since the duty cycle is always set to 0 by these PWM users before
calling pwm_disable().

Best regards,
Beno?t


From linux at roeck-us.net  Thu Aug 23 09:39:31 2012
From: linux at roeck-us.net (Guenter Roeck)
Date: Thu, 23 Aug 2012 06:39:31 -0700
Subject: [PATCH] spi/s3c64xx: Drop extra calls to spi_master_get in
 suspend/remove functions
In-Reply-To: <1d0b01cd80f1$d77eaf90$867c0eb0$%kim@samsung.com>
References: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
 <1d0b01cd80f1$d77eaf90$867c0eb0$%kim@samsung.com>
Message-ID: <20120823133931.GB24319@roeck-us.net>

On Thu, Aug 23, 2012 at 02:40:45PM +0900, Kukjin Kim wrote:
> Guenter Roeck wrote:
> > 
> > Suspend and resume functions call spi_master_get() without matching
> > spi_master_put(). The extra references are unnecessary and cause
> > subsequent
> > module unload attempts to fail. Drop the calls.
> > 
> > Signed-off-by: Guenter Roeck <linux at roeck-us.net>
> 
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> (Cc'ed Mark Brown who is handling spi now)
> 
> Guenter, maybe you need to re-send this patch to Mark so that he can apply
> ;-)
> 
Guess you are right - and I did copy Mark on my later patches. Mark, I just
bounced the patch to you, so you should have it now.

Thanks,
Guenter

> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> > ---
> >  drivers/spi/spi-s3c64xx.c |    8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> > index 646a765..d7a87df 100644
> > --- a/drivers/spi/spi-s3c64xx.c
> > +++ b/drivers/spi/spi-s3c64xx.c
> > @@ -1409,7 +1409,7 @@ static int s3c64xx_spi_remove(struct platform_device
> > *pdev)
> >  #ifdef CONFIG_PM
> >  static int s3c64xx_spi_suspend(struct device *dev)
> >  {
> > -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> > +	struct spi_master *master = dev_get_drvdata(dev);
> >  	struct s3c64xx_spi_driver_data *sdd =
> > spi_master_get_devdata(master);
> > 
> >  	spi_master_suspend(master);
> > @@ -1428,7 +1428,7 @@ static int s3c64xx_spi_suspend(struct device *dev)
> > 
> >  static int s3c64xx_spi_resume(struct device *dev)
> >  {
> > -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> > +	struct spi_master *master = dev_get_drvdata(dev);
> >  	struct s3c64xx_spi_driver_data *sdd =
> > spi_master_get_devdata(master);
> >  	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> > 
> > @@ -1452,7 +1452,7 @@ static int s3c64xx_spi_resume(struct device *dev)
> >  #ifdef CONFIG_PM_RUNTIME
> >  static int s3c64xx_spi_runtime_suspend(struct device *dev)
> >  {
> > -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> > +	struct spi_master *master = dev_get_drvdata(dev);
> >  	struct s3c64xx_spi_driver_data *sdd =
> > spi_master_get_devdata(master);
> > 
> >  	clk_disable(sdd->clk);
> > @@ -1463,7 +1463,7 @@ static int s3c64xx_spi_runtime_suspend(struct device
> > *dev)
> > 
> >  static int s3c64xx_spi_runtime_resume(struct device *dev)
> >  {
> > -	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
> > +	struct spi_master *master = dev_get_drvdata(dev);
> >  	struct s3c64xx_spi_driver_data *sdd =
> > spi_master_get_devdata(master);
> > 
> >  	clk_enable(sdd->src_clk);
> > --
> > 1.7.9.7
> 
> 


From steve.capper at arm.com  Thu Aug 23 09:51:11 2012
From: steve.capper at arm.com (Steve Capper)
Date: Thu, 23 Aug 2012 14:51:11 +0100
Subject: ARM hugetlb support?
In-Reply-To: <CANOLnOMaV_urZvRL5NF++3UpOQSa_RwL1jfOTdGkn7fN+yZ28Q@mail.gmail.com>
References: <20120820082514.GF27631@e103986-lin>
 <CANOLnOMaV_urZvRL5NF++3UpOQSa_RwL1jfOTdGkn7fN+yZ28Q@mail.gmail.com>
Message-ID: <20120823135109.GA22158@e103986-lin>

On Tue, Aug 21, 2012 at 10:57:40AM +0100, Grazvydas Ignotas wrote:
> 
> Sounds promising. If you CC me when sending those patches, I can test
> them on CortexA8 with my application.

Will do; I too would be very interested in the performance difference.

> BTW as you probably know know, Catalin seems to have hugetlb branch for LPAE:
> http://git.kernel.org/?p=linux/kernel/git/cmarinas/linux-arm-arch.git;a=shortlog;h=refs/heads/hugetlb
> 

Yes thanks, I know.

-- 
Steve



From peter.ujfalusi at ti.com  Thu Aug 23 09:54:09 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 23 Aug 2012 16:54:09 +0300
Subject: [PATCH] ARM: omap_hwmod: Fix up resource names when booted with
 devicetree
Message-ID: <1345730049-12675-1-git-send-email-peter.ujfalusi@ti.com>

When booted with some resource will have their name set to NULL. This can
cause later kernel crash since this is not expected by the platform code.

When we boot without DT the devices are created with platform_device_add()
which itself fixes up the missing resource names:
if (r->name == NULL)
	r->name = dev_name(&pdev->dev);

The of core also fixes up the resource names when taking the information
from DT data - in __of_address_to_resource():
r->name = name ? name : dev->full_name;

When we boot OMAP with devicetree: of will create the devices based on the
DT data so the resource names are guarantied to be not NULL. Since we have
the 'ti,hwmod' tag, we remove the of created resources from the device and
re-create them based on hwmod data. If the hwmod data does not specify a
name for a resource it will be NULL.
This can cause kernel crash if the driver uses
platform_get_resource_byname() to get any resource.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/plat-omap/omap_device.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..ff57b5a 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -370,6 +370,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
 		goto odbfd_exit1;
 	}
 
+	/* Fix up missing resource names */
+	for (i = 0; i < pdev->num_resources; i++) {
+		struct resource *r = &pdev->resource[i];
+
+		if (r->name == NULL)
+			r->name = dev_name(&pdev->dev);
+	}
+
 	if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
 		omap_device_disable_idle_on_suspend(pdev);
 
-- 
1.7.8.6



From shawn.guo at linaro.org  Thu Aug 23 09:58:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 21:58:09 +0800
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <20120823104356.GA13622@mudshark.cambridge.arm.com>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
 <20120823104356.GA13622@mudshark.cambridge.arm.com>
Message-ID: <20120823135806.GG24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 11:43:56AM +0100, Will Deacon wrote:
> On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> > diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> > index 99afa74..7cc67ce 100644
> > --- a/arch/arm/include/asm/processor.h
> > +++ b/arch/arm/include/asm/processor.h
> > @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
> >  unsigned long get_wchan(struct task_struct *p);
> >  
> >  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> > -#define cpu_relax()			smp_mb()
> > +#define cpu_relax()		do {					\
> > +					asm("nop");			\
> > +					asm("nop");			\
> > +					asm("nop");			\
> > +					asm("nop");			\
> > +					asm("nop");			\
> 
> Can you use nop() instead of the explicit asm?

Yes.  I just tried, and it works too.

> Also, I think we should try
> and use some methodology on deciding the number of nops to insert. Without
> having a full handle on the problem at the moment, it would seem that we
> need at least NR_CPUS worth (since the number of spinning secondaries is
> NR_CPUS-1 and they may execute their barriers in lock-step).
> 
I'm not sure we get something like that.  In my testing here, I need
at least 5 nops to get rid of the issue.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Aug 23 10:12:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:12:58 +0800
Subject: [PATCH] ARM: dts: imx: add imx5x usb entries
In-Reply-To: <1345718157-7927-1-git-send-email-m.grzeschik@pengutronix.de>
References: <1345718157-7927-1-git-send-email-m.grzeschik@pengutronix.de>
Message-ID: <20120823141254.GH24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 12:35:57PM +0200, Michael Grzeschik wrote:
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
>  arch/arm/boot/dts/imx51.dtsi |   28 ++++++++++++++++++++++++++++
>  arch/arm/boot/dts/imx53.dtsi |   28 ++++++++++++++++++++++++++++
>  2 files changed, 56 insertions(+)

Applied, thanks.


From koen at dominion.thruhere.net  Thu Aug 23 10:13:48 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Thu, 23 Aug 2012 16:13:48 +0200
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <1345547850-29761-5-git-send-email-anilkumar@ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
Message-ID: <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>


Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:

> Add tps65217 regulator device tree data to AM335x-Bone by adding
> regulator consumers with tightened constraints and regulator-name.
> TPS65217 regulator handle can be obtained by using this regulator
> name.
> 
> This patch also add I2C node with I2C frequency and tps65217 PMIC
> I2C slave address.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>

I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?




From benoit.thebaudeau at advansee.com  Thu Aug 23 10:19:47 2012
From: benoit.thebaudeau at advansee.com (=?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?=)
Date: Thu, 23 Aug 2012 16:19:47 +0200 (CEST)
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <320569847.2756382.1345729013971.JavaMail.root@advansee.com>
Message-ID: <217877237.2758643.1345731587941.JavaMail.root@advansee.com>

Some PWM drivers enable the clock of the PWM peripheral in pwm_enable(). Hence,
for these drivers, a call to pwm_config() does not have any effect before
pwm_enable() has been called.

This patch fixes the PWM users to make sure that they call pwm_enable() before
pwm_config().

This fixes the first setting of brightness through sysfs that had no effect with
leds-pwm and the i.MX PWM driver.

Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: <linux-kernel at vger.kernel.org>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: <linux-arm-kernel at lists.infradead.org>
Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: <linux-input at vger.kernel.org>
Cc: Bryan Wu <bryan.wu at canonical.com>
Cc: Richard Purdie <rpurdie at rpsys.net>
Cc: <linux-leds at vger.kernel.org>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
Cc: <linux-fbdev at vger.kernel.org>
Cc: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
---
 .../drivers/input/misc/pwm-beeper.c                |    6 +++---
 .../drivers/leds/leds-pwm.c                        |    2 +-
 .../drivers/video/backlight/pwm_bl.c               |    2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git linux-next-c94456b.orig/drivers/input/misc/pwm-beeper.c linux-next-c94456b/drivers/input/misc/pwm-beeper.c
index fc84c8a..97d322b 100644
--- linux-next-c94456b.orig/drivers/input/misc/pwm-beeper.c
+++ linux-next-c94456b/drivers/input/misc/pwm-beeper.c
@@ -53,10 +53,10 @@ static int pwm_beeper_event(struct input_dev *input,
 		pwm_disable(beeper->pwm);
 	} else {
 		period = HZ_TO_NANOSECONDS(value);
-		ret = pwm_config(beeper->pwm, period / 2, period);
+		ret = pwm_enable(beeper->pwm);
 		if (ret)
 			return ret;
-		ret = pwm_enable(beeper->pwm);
+		ret = pwm_config(beeper->pwm, period / 2, period);
 		if (ret)
 			return ret;
 		beeper->period = period;
@@ -156,8 +156,8 @@ static int pwm_beeper_resume(struct device *dev)
 	struct pwm_beeper *beeper = dev_get_drvdata(dev);
 
 	if (beeper->period) {
-		pwm_config(beeper->pwm, beeper->period / 2, beeper->period);
 		pwm_enable(beeper->pwm);
+		pwm_config(beeper->pwm, beeper->period / 2, beeper->period);
 	}
 
 	return 0;
diff --git linux-next-c94456b.orig/drivers/leds/leds-pwm.c linux-next-c94456b/drivers/leds/leds-pwm.c
index f2e44c7..c2e0c22 100644
--- linux-next-c94456b.orig/drivers/leds/leds-pwm.c
+++ linux-next-c94456b/drivers/leds/leds-pwm.c
@@ -42,8 +42,8 @@ static void led_pwm_set(struct led_classdev *led_cdev,
 		pwm_config(led_dat->pwm, 0, period);
 		pwm_disable(led_dat->pwm);
 	} else {
-		pwm_config(led_dat->pwm, brightness * period / max, period);
 		pwm_enable(led_dat->pwm);
+		pwm_config(led_dat->pwm, brightness * period / max, period);
 	}
 }
 
diff --git linux-next-c94456b.orig/drivers/video/backlight/pwm_bl.c linux-next-c94456b/drivers/video/backlight/pwm_bl.c
index 995f016..a4bb95c 100644
--- linux-next-c94456b.orig/drivers/video/backlight/pwm_bl.c
+++ linux-next-c94456b/drivers/video/backlight/pwm_bl.c
@@ -65,8 +65,8 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
 
 		duty_cycle = pb->lth_brightness +
 		     (duty_cycle * (pb->period - pb->lth_brightness) / max);
-		pwm_config(pb->pwm, duty_cycle, pb->period);
 		pwm_enable(pb->pwm);
+		pwm_config(pb->pwm, duty_cycle, pb->period);
 	}
 
 	if (pb->notify_after)


From shawn.guo at linaro.org  Thu Aug 23 10:18:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:18:18 +0800
Subject: [PATCH] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
Message-ID: <20120823141815.GI24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 12:38:48PM +0200, Michael Grzeschik wrote:
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
>  arch/arm/mach-imx/clk-imx51-imx53.c |   36 +++++++++++++++++++++++------------
>  1 file changed, 24 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index 4bdcaa9..6ce49b1 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -258,18 +258,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
>  	clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
>  	clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");

Removing those will break some in-tree users, right?

>  	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
>  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
>  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
> @@ -351,6 +339,18 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
>  	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
>  	clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80600.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80600.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80600.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80400.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80400.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80400.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80200.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80200.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80200.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");

I haven't seen new driver requesting these clocks, so would postpone
the changes until the driver actually requests them.

Regards,
Shawn

>  	clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
>  	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
>  	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
> @@ -439,6 +439,18 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
>  	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
>  	clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80600.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80600.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80600.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80400.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80400.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80400.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80200.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80200.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80200.usb");
> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80000.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80000.usb");
> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80000.usb");
>  	clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
>  	clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
>  	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
> -- 
> 1.7.10.4
> 


From arnd at arndb.de  Thu Aug 23 10:20:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 14:20:50 +0000
Subject: [PATCH 6/6] ARM: imx: select ARM_CPU_SUSPEND when necessary
In-Reply-To: <20120823024119.GD24242@S2101-09.ap.freescale.net>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-7-git-send-email-arnd@arndb.de>
 <20120823024119.GD24242@S2101-09.ap.freescale.net>
Message-ID: <201208231420.50247.arnd@arndb.de>

On Thursday 23 August 2012, Shawn Guo wrote:
> On Wed, Aug 22, 2012 at 05:13:10PM +0200, Arnd Bergmann wrote:
> > On i.MX6, we select ARM_CPU_SUSPEND when building with power management
> > support, but for some reason this was omitted on i.MX5. Normally we
> > build kernels for both together so the error only showed up in
> > randconfig tests.
> > 
> > Without this patch, building imx5 standalone results in:
> > 
> > arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
> > arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume'
> > 
> So far, none of the functions in head-v7.S is used on imx5.  Also
> since imx5 SoCs implement State Retention Power Gating in hardware,
> ARM_CPU_SUSPEND support will never be used on imx5.
> 
> Maybe we should make head-v7.S only compile for imx6?

In tegra and shmobile, the respective file is called headsmp.S, so
I would suggest we rename it to the same here and only build it when
CONFIG_SMP is set, which comes down to imx6 at the moment.

How is this version?

	Arnd

From 4036e8f292887e7b1abc8eacec7d619abd608178 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Fri, 17 Aug 2012 00:16:08 +0000
Subject: [PATCH] ARM: imx: build i.MX6 functions only when needed

The head-v7.S contains a call to the generic cpu_suspend function,
which is only available when selected by the i.MX6 code. As
pointed out by Shawn Guo, i.MX does not actually use any
functions defined in head-v7.S. It is also needed only for
the i.MX6 power management code and for the SMP code, so
we can restrict building this file to situations in which
at least one of those two is present.

Finally, other platforms with a similar file call it headsmp.S,
so we can rename it to the same for consistency.

Without this patch, building imx5 standalone results in:

arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume'

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Eric Miao <eric.miao at linaro.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: stable at vger.kernel.org

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e08adb7..d004d37 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -71,14 +71,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-obj-$(CONFIG_CPU_V7) += head-v7.o
-AFLAGS_head-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SMP) += platsmp.o
+AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
 endif
 
 # i.MX5 based machines
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/headsmp.S
similarity index 100%
rename from arch/arm/mach-imx/head-v7.S
rename to arch/arm/mach-imx/headsmp.S


From arnd at arndb.de  Thu Aug 23 10:26:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 14:26:42 +0000
Subject: [PATCH 1/6] ARM: ux500: don't select LEDS_GPIO for snowball
In-Reply-To: <1345648390-4234-2-git-send-email-arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-2-git-send-email-arnd@arndb.de>
Message-ID: <201208231426.43105.arnd@arndb.de>

On Wednesday 22 August 2012, Arnd Bergmann wrote:
> The gpio leds driver can only be built if the generic LED code is
> also enabled. Snowball selects LEDS_GPIO for an unknown reason
> but it does not select LEDS_CLASS and also does not really require
> the LED support at all, so we can just drop this dependency.
> 
> Without this patch, building without LEDS_CLASS esults in:
> 
> drivers/built-in.o: In function `create_gpio_led.part.2':
> governor_userspace.c:(.devinit.text+0x5a58): undefined reference to `led_classdev_register'
> drivers/built-in.o: In function `gpio_led_remove':
> governor_userspace.c:(.devexit.text+0x6b8): undefined reference to `led_classdev_unregister'
> 
> This reverts 8733f53c6 "ARM: ux500: Kconfig: Compile in leds-gpio
> support for Snowball", which was not completely thought through.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Lee Jones <lee.jones at linaro.org>

I discussed this with Lee on IRC, he really wants to keep the LED enabled for snowball
for his own convenience. How is this version instead?

	Arnd

From 53c4e002b7ebd70ad9dcfa7a97c0ae58e874e643 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd at arndb.de>
Date: Wed, 15 Aug 2012 20:34:48 +0000
Subject: [PATCH] ARM: ux500: don't select LEDS_GPIO for snowball

The gpio leds driver can only be built if the generic LED code is
also enabled. Snowball selects LEDS_GPIO for an unknown reason
but it does not select LEDS_CLASS and also does not really require
the LED support at all, so we can just drop this dependency.

Without this patch, building without LEDS_CLASS esults in:

drivers/built-in.o: In function `create_gpio_led.part.2':
governor_userspace.c:(.devinit.text+0x5a58): undefined reference to `led_classdev_register'
drivers/built-in.o: In function `gpio_led_remove':
governor_userspace.c:(.devexit.text+0x6b8): undefined reference to `led_classdev_unregister'

This reverts 8733f53c6 "ARM: ux500: Kconfig: Compile in leds-gpio
support for Snowball", which was not completely thought through.

In order to leave the GPIO LED code still present in normal
builds, this also enables the symbol in u8500_defconfig, in addition
to the other LED drivers that are already selected there.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Lee Jones <lee.jones at linaro.org>

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d4f661..da68454 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -86,6 +86,7 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
 CONFIG_LEDS_LP5521=y
+CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AB8500=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf..53d3d46 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -41,7 +41,6 @@ config MACH_HREFV60
 config MACH_SNOWBALL
 	bool "U8500 Snowball platform"
 	select MACH_MOP500
-	select LEDS_GPIO
 	help
 	  Include support for the snowball development platform.
 


From shawn.guo at linaro.org  Thu Aug 23 10:33:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:33:48 +0800
Subject: [PATCH 2/4] ARM: dts: mxs: Add alternative I2C muxing options
 for imx28
In-Reply-To: <1345711351-16367-3-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
 <1345711351-16367-3-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120823143344.GJ24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 10:42:29AM +0200, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Cc: Brian Lilly <brian at crystalfontz.com>
> ---
>  arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 787efac..f6ffcd9 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -410,6 +410,17 @@
>  					fsl,pull-up = <1>;
>  				};
>  
> +				i2c0_pins_b: i2c0 at 1 {
> +					reg = <1>;
> +					fsl,pinmux-ids = <
> +						0x3001 /* MX28_PAD_AUART0_RX__DUART_CTS */
> +						0x3011 /* MX28_PAD_AUART0_TX__DUART_RTS */

The comments are wrong.  I fixed them as below and applied the patch.

						0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
						0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */

Regards,
Shawn


> +					>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
>  				saif0_pins_a: saif0 at 0 {
>  					reg = <0>;
>  					fsl,pinmux-ids = <
> -- 
> 1.7.9.5
> 


From shawn.guo at linaro.org  Thu Aug 23 10:34:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:34:53 +0800
Subject: [PATCH 3/4] ARM: dts: mxs: Add pwm4 muxing options for imx28
In-Reply-To: <1345711351-16367-4-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
 <1345711351-16367-4-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120823143450.GK24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 10:42:30AM +0200, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Cc: Brian Lilly <brian at crystalfontz.com>

Applied, thanks.

> ---
>  arch/arm/boot/dts/imx28.dtsi |   10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index f6ffcd9..60d10d7 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -464,6 +464,16 @@
>  					fsl,pull-up = <0>;
>  				};
>  
> +				pwm4_pins_a: pwm4 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x31d0 /* MX28_PAD_PWM4__PWM_4 */
> +					>;
> +					fsl,drive-strength = <0>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +
>  				lcdif_24bit_pins_a: lcdif-24bit at 0 {
>  					reg = <0>;
>  					fsl,pinmux-ids = <
> -- 
> 1.7.9.5
> 


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 10:37:57 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 15:37:57 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823132618.GB1047@gmail.com>
References: <1344527268-5964-8-git-send-email-lee.jones@linaro.org>
 <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
 <20120823121936.GA1047@gmail.com>
 <20120823125903.GA7995@opensource.wolfsonmicro.com>
 <20120823132618.GB1047@gmail.com>
Message-ID: <20120823143757.GB7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 02:26:19PM +0100, Lee Jones wrote:

> > I think Ola is suggesting probing the DMA driver from the machine which
> > will also work though I'm not 100% sure if I'm parsing the above
> > correctly.  The issue in DT terms is that if the DMA controller is
> > shared with a bunch of other IPs then it should have one node shared
> > between them all and not a bunch of shim nodes inserted in the middle
> > which only exists due to the way Linux instantiates stuff.

> When you say 'machine', do you mean from arch/<arch>/mach-*? If so, I'm
> keen for that not to happen.

No, sound/soc/ux500/snowball.c or whatever.  At least that's my guess.

> > They instantiate the PCM driver dynamically from the DAI when it's
> > probed which is pretty much what you're patch is doing.

> So they do it in the same why I have with this patch? Do you know why
> Ola might think this is a bad idea?

I'm not 100% sure, I'm guessing it might be down to the fact that you
end up with multiple PCM drivers.  We could avoid that with refcounting
but nobody's really worried about it.
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From broonie at opensource.wolfsonmicro.com  Thu Aug 23 10:39:43 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 15:39:43 +0100
Subject: [PATCH] ARM: OMAP2+: twl-common: Fix compile time error when
 omap-twl4030 audio is not enabled
In-Reply-To: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345703701-27283-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120823143943.GC7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 09:35:01AM +0300, Peter Ujfalusi wrote:
> Fixes:
> CC      arch/arm/mach-omap2/twl-common.o arch/arm/mach-omap2/twl-common.c:562: error: conflicting types for ?omap_twl4030_audio_init?
> arch/arm/mach-omap2/twl-common.h:62: error: previous declaration of ?omap_twl4030_audio_init? was here
> make[1]: *** [arch/arm/mach-omap2/twl-common.o] Error 1
> make: *** [arch/arm/mach-omap2] Error 2

Applied, thanks.
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From mkl at pengutronix.de  Thu Aug 23 10:41:29 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Thu, 23 Aug 2012 16:41:29 +0200
Subject: [PATCH] ARM: imx: add imx5x usb controller clock lookups
In-Reply-To: <20120823141815.GI24242@S2101-09.ap.freescale.net>
References: <1345718328-6547-1-git-send-email-m.grzeschik@pengutronix.de>
 <20120823141815.GI24242@S2101-09.ap.freescale.net>
Message-ID: <50364119.300@pengutronix.de>

On 08/23/2012 04:18 PM, Shawn Guo wrote:
> On Thu, Aug 23, 2012 at 12:38:48PM +0200, Michael Grzeschik wrote:
>> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
>> ---
>>  arch/arm/mach-imx/clk-imx51-imx53.c |   36 +++++++++++++++++++++++------------
>>  1 file changed, 24 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
>> index 4bdcaa9..6ce49b1 100644
>> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
>> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
>> @@ -258,18 +258,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>>  	clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
>>  	clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
>>  	clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
>> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
>> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
>> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
>> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
>> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
>> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
>> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
>> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
>> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
>> -	clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
>> -	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
>> -	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
> 
> Removing those will break some in-tree users, right?

Yes, there was a v2 fixing this.

>>  	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
>>  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
>>  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
>> @@ -351,6 +339,18 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>>  	clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
>>  	clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
>>  	clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
>> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80600.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80600.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80600.usb");
>> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80400.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80400.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80400.usb");
>> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80200.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80200.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80200.usb");
>> +	clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
>> +	clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");
> 
> I haven't seen new driver requesting these clocks, so would postpone
> the changes until the driver actually requests them.

I'm going to post a driver ci13xxx_imx driver update in a few minutes.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From shawn.guo at linaro.org  Thu Aug 23 10:45:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:45:45 +0800
Subject: [PATCH 4/4] ARM: dts: mxs: add oled support for the cfa-10036
In-Reply-To: <1345711351-16367-5-git-send-email-maxime.ripard@free-electrons.com>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
 <1345711351-16367-5-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120823144541.GL24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 10:42:31AM +0200, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> Cc: Brian Lilly <brian at crystalfontz.com>
> ---
>  arch/arm/boot/dts/imx28-cfa10036.dts |   20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
Looks mostly good, but I have to postpone it until driver part gets
accepted.

Some minor comments below.

> diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
> index c03a577..92784a9 100644
> --- a/arch/arm/boot/dts/imx28-cfa10036.dts
> +++ b/arch/arm/boot/dts/imx28-cfa10036.dts
> @@ -33,11 +33,31 @@
>  		};
>  
>  		apbx at 80040000 {
> +			pwm: pwm at 80064000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pwm4_pins_a>;
> +				status = "okay";
> +			};
> +
>  			duart: serial at 80074000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&duart_pins_b>;
>  				status = "okay";
>  			};
> +
> +			i2c0: i2c at 80058000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&i2c0_pins_b>;
> +				status = "okay";
> +
> +				ssd1307: oled at 3c {
> +					compatible = "solomon,ssd1307fb-i2c";
> +					reg = <0x3c>;
> +					pwms = <&pwm 4 3000>;
> +					oled-reset-gpio = <&gpio2 7 1>;

The idiom of naming gpio in DT is *-gpios, even though most of times
there is only one pin.

> +					oled-reset-active-low;

I would drop oled- prefix for above two properties.

Regards,
Shawn

> +				};
> +			};
>  		};
>  	};
>  
> -- 
> 1.7.9.5
> 


From shawn.guo at linaro.org  Thu Aug 23 10:55:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 23 Aug 2012 22:55:27 +0800
Subject: [PATCH 6/6] ARM: imx: select ARM_CPU_SUSPEND when necessary
In-Reply-To: <201208231420.50247.arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-7-git-send-email-arnd@arndb.de>
 <20120823024119.GD24242@S2101-09.ap.freescale.net>
 <201208231420.50247.arnd@arndb.de>
Message-ID: <20120823145524.GM24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 02:20:50PM +0000, Arnd Bergmann wrote:
> From 4036e8f292887e7b1abc8eacec7d619abd608178 Mon Sep 17 00:00:00 2001
> From: Arnd Bergmann <arnd at arndb.de>
> Date: Fri, 17 Aug 2012 00:16:08 +0000
> Subject: [PATCH] ARM: imx: build i.MX6 functions only when needed
> 
> The head-v7.S contains a call to the generic cpu_suspend function,
> which is only available when selected by the i.MX6 code. As
> pointed out by Shawn Guo, i.MX does not actually use any

s/i.MX/i.MX5

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> functions defined in head-v7.S. It is also needed only for
> the i.MX6 power management code and for the SMP code, so
> we can restrict building this file to situations in which
> at least one of those two is present.
> 
> Finally, other platforms with a similar file call it headsmp.S,
> so we can rename it to the same for consistency.
> 
> Without this patch, building imx5 standalone results in:
> 
> arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume':
> arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume'
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Eric Miao <eric.miao at linaro.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: stable at vger.kernel.org
> 
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index e08adb7..d004d37 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -71,14 +71,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
>  obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
>  obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
>  obj-$(CONFIG_HAVE_IMX_SRC) += src.o
> -obj-$(CONFIG_CPU_V7) += head-v7.o
> -AFLAGS_head-v7.o :=-Wa,-march=armv7-a
> -obj-$(CONFIG_SMP) += platsmp.o
> +AFLAGS_headsmp.o :=-Wa,-march=armv7-a
> +obj-$(CONFIG_SMP) += headsmp.o platsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
>  obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
>  
>  ifeq ($(CONFIG_PM),y)
> -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
> +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
>  endif
>  
>  # i.MX5 based machines
> diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/headsmp.S
> similarity index 100%
> rename from arch/arm/mach-imx/head-v7.S
> rename to arch/arm/mach-imx/headsmp.S

-- 
Regards,
Shawn


From lee.jones at linaro.org  Thu Aug 23 10:59:06 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 15:59:06 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823143757.GB7995@opensource.wolfsonmicro.com>
References: <CACRpkdbc6bGC4Yp7Bcdfev=Uc=1h4L1v+Lj9RbmJV3F+knQOZQ@mail.gmail.com>
 <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
 <20120823121936.GA1047@gmail.com>
 <20120823125903.GA7995@opensource.wolfsonmicro.com>
 <20120823132618.GB1047@gmail.com>
 <20120823143757.GB7995@opensource.wolfsonmicro.com>
Message-ID: <20120823145904.GC1047@gmail.com>

On Thu, Aug 23, 2012 at 03:37:57PM +0100, Mark Brown wrote:
> On Thu, Aug 23, 2012 at 02:26:19PM +0100, Lee Jones wrote:
> 
> > > I think Ola is suggesting probing the DMA driver from the machine which
> > > will also work though I'm not 100% sure if I'm parsing the above
> > > correctly.  The issue in DT terms is that if the DMA controller is
> > > shared with a bunch of other IPs then it should have one node shared
> > > between them all and not a bunch of shim nodes inserted in the middle
> > > which only exists due to the way Linux instantiates stuff.
> 
> > When you say 'machine', do you mean from arch/<arch>/mach-*? If so, I'm
> > keen for that not to happen.
> 
> No, sound/soc/ux500/snowball.c or whatever.  At least that's my guess.

Ah, I see. Maybe the mop500.c file then.

> > > They instantiate the PCM driver dynamically from the DAI when it's
> > > probed which is pretty much what you're patch is doing.
> 
> > So they do it in the same why I have with this patch? Do you know why
> > Ola might think this is a bad idea?
> 
> I'm not 100% sure, I'm guessing it might be down to the fact that you
> end up with multiple PCM drivers.  We could avoid that with refcounting
> but nobody's really worried about it.

I think I'll wait for Ola to get back, as he's the expert on this stuff.

I'll attempt to re-jig the patch-set, as this is a blocker atm.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 11:00:24 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 16:00:24 +0100
Subject: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe rather
 than as a device
In-Reply-To: <20120823145904.GC1047@gmail.com>
References: <002801cd7c31$14d3d0c0$3e7b7240$@se>
 <20120820085111.GJ8450@gmail.com>
 <006d01cd7f5a$65937840$30ba68c0$@se>
 <20120823092216.GA27264@gmail.com>
 <20120823113922.GZ7995@opensource.wolfsonmicro.com>
 <20120823121936.GA1047@gmail.com>
 <20120823125903.GA7995@opensource.wolfsonmicro.com>
 <20120823132618.GB1047@gmail.com>
 <20120823143757.GB7995@opensource.wolfsonmicro.com>
 <20120823145904.GC1047@gmail.com>
Message-ID: <20120823150024.GF7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 03:59:06PM +0100, Lee Jones wrote:

> I'll attempt to re-jig the patch-set, as this is a blocker atm.

OK, if we could get at least the DAI driver and arch/arm changes in
that'd at least make the series smaller.
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From lee.jones at linaro.org  Thu Aug 23 11:01:25 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 16:01:25 +0100
Subject: [PATCH 1/3] ARM: ux500: Add i2c configurations to the Device Tree for
 DB8500 based devices
Message-ID: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>

Since initial support was provided for the Nomadik I2C driver, it
has been converted to an AMBA device. AMBA devices are probed in
a slightly different way to other devices, so we have to identify
them using an "arm,primecell" compatible string. As well as doing
just that, this patch specifies which regulators the controller
should use and requests a clock-speed. The latter is provided as
more of an example, as it's the same as the recently changed
default configuration.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |   25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 51209a8..3708a6b 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -480,43 +480,58 @@
 		};
 
 		i2c at 80004000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80004000 0x1000>;
 			interrupts = <0 21 0x4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			v-i2c-supply = <&db8500_vape_reg>;
+
+			clock-frequency = <400000>;
 		};
 
 		i2c at 80122000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80122000 0x1000>;
 			interrupts = <0 22 0x4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			v-i2c-supply = <&db8500_vape_reg>;
+
+			clock-frequency = <400000>;
 		};
 
 		i2c at 80128000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80128000 0x1000>;
 			interrupts = <0 55 0x4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			v-i2c-supply = <&db8500_vape_reg>;
+
+			clock-frequency = <400000>;
 		};
 
 		i2c at 80110000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80110000 0x1000>;
 			interrupts = <0 12 0x4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			v-i2c-supply = <&db8500_vape_reg>;
+
+			clock-frequency = <400000>;
 		};
 
 		i2c at 8012a000 {
-			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x8012a000 0x1000>;
 			interrupts = <0 51 0x4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			v-i2c-supply = <&db8500_vape_reg>;
+
+			clock-frequency = <400000>;
 		};
 
 		ssp at 80002000 {
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug 23 11:01:26 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 16:01:26 +0100
Subject: [PATCH 2/3] Documentation: Device Tree binding information for
 i2c-nomadik driver
In-Reply-To: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345734087-21803-2-git-send-email-lee.jones@linaro.org>

This document describes each of the non-standard Device Tree bindings
used in the Nomadik I2C driver.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/i2c/nomadik.txt |   23 +++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/nomadik.txt

diff --git a/Documentation/devicetree/bindings/i2c/nomadik.txt b/Documentation/devicetree/bindings/i2c/nomadik.txt
new file mode 100644
index 0000000..72065b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nomadik.txt
@@ -0,0 +1,23 @@
+I2C for Nomadik based systems
+
+Required (non-standard) properties:
+ - Nil
+
+Recommended (non-standard) properties:
+ - clock-frequency : Maximum bus clock frequency for the device
+
+Optional (non-standard) properties:
+ - Nil
+
+Example :
+
+i2c at 80004000 {
+        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+        reg = <0x80004000 0x1000>;
+        interrupts = <0 21 0x4>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        v-i2c-supply = <&db8500_vape_reg>;
+
+        clock-frequency = <400000>;
+};
-- 
1.7.9.5



From lee.jones at linaro.org  Thu Aug 23 11:01:27 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 23 Aug 2012 16:01:27 +0100
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the Nomadik I2C
 driver
In-Reply-To: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345734087-21803-3-git-send-email-lee.jones@linaro.org>

Here we apply the bindings required for successful Device Tree
probing of the i2c-nomadik driver.

Cc: linux-i2c at vger.kernel.org
Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/i2c/busses/i2c-nomadik.c |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 61b00ed..8168389 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -25,6 +25,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
 #include <linux/platform_data/i2c-nomadik.h>
+#include <linux/of.h>
 
 #define DRIVER_NAME "nmk-i2c"
 
@@ -920,15 +921,42 @@ static struct nmk_i2c_controller u8500_i2c = {
 	.sm             = I2C_FREQ_MODE_FAST,
 };
 
+static void nmk_i2c_of_probe(struct device_node *np,
+			struct nmk_i2c_controller *pdata)
+{
+	/* Provide the default configuration as a base. */
+	pdata = &u8500_i2c;
+
+	of_property_read_u32(np, "clock-frequency", (u32*)&pdata->clk_freq);
+
+	/* This driver only supports 'standard' and 'fast' modes of operation. */
+	if (pdata->clk_freq <= 100000)
+		pdata->sm = I2C_FREQ_MODE_STANDARD;
+	else
+		pdata->sm = I2C_FREQ_MODE_FAST;
+}
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
 	struct nmk_i2c_controller *pdata = adev->dev.platform_data;
+	struct device_node *np = adev->dev.of_node;
 	struct nmk_i2c_dev	*dev;
 	struct i2c_adapter *adap;
 
+	if (np) {
+		if (!pdata) {
+			pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
+			if (!pdata) {
+				ret = -ENOMEM;
+				goto err_no_mem;
+			}
+		}
+		nmk_i2c_of_probe(np, pdata);
+	}
+
 	if (!pdata)
 		/* No i2c configuration found, using the default. */
 		pdata = &u8500_i2c;
-- 
1.7.9.5



From arnd at arndb.de  Thu Aug 23 11:04:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 15:04:48 +0000
Subject: [GIT PULL] Samsung fixes for v3.6
In-Reply-To: <1d5f01cd811f$5c5de8c0$1519ba40$%kim@samsung.com>
References: <1d5f01cd811f$5c5de8c0$1519ba40$%kim@samsung.com>
Message-ID: <201208231504.49021.arnd@arndb.de>

On Thursday 23 August 2012, Kukjin Kim wrote:
> For HDMI, already HDMI support for EXYNOS in mainline kernel is broken
> because its configuration moved to platform data but regarding platform data
> didn't support yet. And others are for fix warnings.

Pulled into fixes branch. Thanks,

	Arnd


From arnd at arndb.de  Thu Aug 23 11:05:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 15:05:46 +0000
Subject: [GIT PULL] imx fixes for 3.6 (take 2)
In-Reply-To: <20120823093407.GE24242@S2101-09.ap.freescale.net>
References: <20120823093407.GE24242@S2101-09.ap.freescale.net>
Message-ID: <201208231505.46361.arnd@arndb.de>

On Thursday 23 August 2012, Shawn Guo wrote:
> are available in the git repository at:
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/fixes-for-3.6
> 
> Philipp Zabel (1):
>       ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path
> 
> Shawn Guo (3):
>       ARM: imx6q: remove imx_src_prepare_restart() call
>       ARM: imx6: spin the cpu until hardware takes it down
>       ARM: dts: imx51-babbage: fix esdhc cd/wp properties

Pulled into the fixes branch now, without the "ARM: imx6q: remove
imx_src_prepare_restart() call" patch.

Thanks,

	Arnd


From arnd at arndb.de  Thu Aug 23 11:07:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 15:07:07 +0000
Subject: [GIT PULL] ux500 fixes
In-Reply-To: <CACRpkdZeTb35naqs7UXo127syN7iPgsHUokRE7B=ER8iJRNhmw@mail.gmail.com>
References: <CACRpkdZeTb35naqs7UXo127syN7iPgsHUokRE7B=ER8iJRNhmw@mail.gmail.com>
Message-ID: <201208231507.07434.arnd@arndb.de>

On Tuesday 21 August 2012, Linus Walleij wrote:
> Hi Arnd, Olof,
> 
> here are two audio fixes from Lee Jones for ux500 for the -rc series.
> Using a signed tag now!
> 

Very good, pulled into the fixes branch now. Thanks!

	Arnd


From broonie at opensource.wolfsonmicro.com  Thu Aug 23 11:20:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 16:20:31 +0100
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <1d5901cd8114$023550f0$069ff2d0$%kim@samsung.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
 <20120810100713.GH24328@opensource.wolfsonmicro.com>
 <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>
 <20120813122359.GA13446@opensource.wolfsonmicro.com>
 <1d5901cd8114$023550f0$069ff2d0$%kim@samsung.com>
Message-ID: <20120823152031.GH7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 06:45:19PM +0900, Kukjin Kim wrote:

> Yeah, actually SoC defconfig in mainline doesn't cover _real_ requirements
> for (mass) product. But I think, it's time we need to sort out the
> defconfigs so that we could use them efficiently on product. BTW, if
> enabling board in defconfig, at least, unexpected build breakages could be
> detected by testing defconfig before merge for mainline...

Right, sure.  I guess the main thing I'm saying here is that I don't
mind what happens here, it's certainly no problem for me turn them on in
the build if that's what people wants.
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From broonie at opensource.wolfsonmicro.com  Thu Aug 23 11:23:24 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 23 Aug 2012 16:23:24 +0100
Subject: [PATCH] atmel-ssc: include linux/io.h for raw io
In-Reply-To: <5036274D.8000803@atmel.com>
References: <1344887950-25596-1-git-send-email-joachim.eastwood@jotron.com>
 <5036274D.8000803@atmel.com>
Message-ID: <20120823152324.GI7995@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 02:51:25PM +0200, Nicolas Ferre wrote:

> May I have your Acked-by for this patch, I plan to queue it with my
> other at91-related fixes in arm-soc tree?

Don't think the original patch was CCed to me - can you send me a copy
please and I'll take a look?
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From dedekind1 at gmail.com  Thu Aug 23 11:34:43 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 23 Aug 2012 18:34:43 +0300
Subject: [PATCH v6] ARM: mtd: nand: davinci: add OF support for davinci
 nand controller
In-Reply-To: <1343632944-25971-1-git-send-email-hs@denx.de>
References: <1343632944-25971-1-git-send-email-hs@denx.de>
Message-ID: <1345736083.2848.248.camel@sauron.fi.intel.com>

On Mon, 2012-07-30 at 09:22 +0200, Heiko Schocher wrote:
> add OF support for the davinci nand controller.
> 
> Signed-off-by: Heiko Schocher <hs at denx.de>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From hachimi.samir at gmail.com  Thu Aug 23 11:32:37 2012
From: hachimi.samir at gmail.com (hachimi.samir at gmail.com)
Date: Thu, 23 Aug 2012 17:32:37 +0200
Subject: [PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto enable
 after configuration
In-Reply-To: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto
 enable after configuration>
References: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto enable
 after configuration>
Message-ID: <1345735959-12964-1-git-send-email-hachimi.samir@gmail.com>

This patch series enables support for pwm driver on imx6q SoC. The first
patch of the series configure the pinctrl for pwm in device-tree. Actually
they are several pin who can be set to pwmO for each pwm, so I assume that
all of them must be enabled when configuring pin.
The second patch activate stop_enable mode and unset the enable bit during
configuration of pwm, and set the enable bit in pwm CR register during enable.

Samir Hachimi (2):
imx6q: Configure the pwm node for pinmux support.
imx6q: Set pwm control register during enable and config call
---
 arch/arm/boot/dts/imx6q.dtsi  |   50 ++++++++
 arch/arm/mach-imx/clk-imx6q.c |    4 ++++
 drivers/pwm/pwm-imx.c         |   37 ++++++++++++++++++++++++++-----------
 3 files changed, 80 insertions(+), 11 deletions(-)



From hachimi.samir at gmail.com  Thu Aug 23 11:32:38 2012
From: hachimi.samir at gmail.com (hachimi.samir at gmail.com)
Date: Thu, 23 Aug 2012 17:32:38 +0200
Subject: [PATCH 1/2] imx6q: Configure the pwm node for pinmux support
In-Reply-To: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto
 enable after configuration>
References: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto enable
 after configuration>
Message-ID: <1345735959-12964-2-git-send-email-hachimi.samir@gmail.com>

From: Samir Hachimi <hachimi.samir at gmail.com>

 Add the pinmux support for pwm.
 Several pin can be set to PwmO for the same Pwm. This configuration set all
 of them when enabled.

Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   42 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..c913b99 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -248,23 +248,35 @@
 			};
 
 			pwm at 02080000 { /* PWM1 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_pwm1_1>;
 				reg = <0x02080000 0x4000>;
 				interrupts = <0 83 0x04>;
+				status = "disabled";
 			};
 
 			pwm at 02084000 { /* PWM2 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_pwm2_1>;
 				reg = <0x02084000 0x4000>;
 				interrupts = <0 84 0x04>;
+				status = "disabled";
 			};
 
 			pwm at 02088000 { /* PWM3 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_pwm3_1>;
 				reg = <0x02088000 0x4000>;
 				interrupts = <0 85 0x04>;
+				status = "disabled";
 			};
 
 			pwm at 0208c000 { /* PWM4 */
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_pwm4_1>;
 				reg = <0x0208c000 0x4000>;
 				interrupts = <0 86 0x04>;
+				status = "disabled";
 			};
 
 			flexcan at 02090000 { /* CAN1 */
@@ -559,6 +571,36 @@
 					};
 				};
 
+				pwm1 {
+				     	pinctrl_pwm1_1: pwm1grp-1 {
+						fsl,pins = <1543 0x80000000	/* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
+							    574 0x80000000      /* MX6Q_PAD_DISPO_DAT8__PWM1_PWMO */
+							    971 0x80000000>;	/* MX6Q_PAD_GPIO_9__PWM1_PWMO */
+					};
+				};
+
+				pwm2 {
+				     	pinctrl_pwm2_1: pwm2grp-1 {
+						fsl,pins = <1557 0x80000000     /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
+							    582 0x80000000	/* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
+							    963 0x80000000>;	/* MX6Q_PAD_GPIO_1__PWM2_PWMO */
+					};
+				};
+
+				pwm3 {
+				     	pinctrl_pwm3_1: pwm3grp-1 {
+						fsl,pins = <1471 0x80000000	/* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
+							    1526 0x80000000>;	/* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
+					};
+				};
+
+				pwm4 {
+				     	pinctrl_pwm4_1: pwm4grp-1 {
+						fsl,pins = <1479 0x80000000	/* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
+							    1550 0x80000000>;	/* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
+					};
+				};
+
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
 						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-- 
1.7.1



From hachimi.samir at gmail.com  Thu Aug 23 11:32:39 2012
From: hachimi.samir at gmail.com (hachimi.samir at gmail.com)
Date: Thu, 23 Aug 2012 17:32:39 +0200
Subject: [PATCH 2/2] imx6q: Set pwm control register during enable and config
 call
In-Reply-To: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto
 enable after configuration>
References: <[PATCH 0/2] imx6q: pwm: Activate stop_mode and remove auto enable
 after configuration>
Message-ID: <1345735959-12964-3-git-send-email-hachimi.samir@gmail.com>

From: Samir Hachimi <hachimi.samir at gmail.com>

Bind pwm node with driver.
Activate stop_enable mode when imx_pwm_config and set enable bit in pwm
CR register during imx_pwm_enable.

Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
---
 arch/arm/boot/dts/imx6q.dtsi  |    8 ++++++++
 arch/arm/mach-imx/clk-imx6q.c |    4 ++++
 drivers/pwm/pwm-imx.c         |   34 +++++++++++++++++++++++-----------
 3 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index c913b99..7ce9dc1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -248,6 +248,8 @@
 			};
 
 			pwm at 02080000 { /* PWM1 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_pwm1_1>;
 				reg = <0x02080000 0x4000>;
@@ -256,6 +258,8 @@
 			};
 
 			pwm at 02084000 { /* PWM2 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_pwm2_1>;
 				reg = <0x02084000 0x4000>;
@@ -264,6 +268,8 @@
 			};
 
 			pwm at 02088000 { /* PWM3 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_pwm3_1>;
 				reg = <0x02088000 0x4000>;
@@ -272,6 +278,8 @@
 			};
 
 			pwm at 0208c000 { /* PWM4 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_pwm4_1>;
 				reg = <0x0208c000 0x4000>;
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520..057740b 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -430,6 +430,10 @@ int __init mx6q_clocks_init(void)
 	clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
 	clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
 	clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
+	clk_register_clkdev(clk[pwm1], "pwm", "2080000.pwm");
+	clk_register_clkdev(clk[pwm2], "pwm", "2084000.pwm");
+	clk_register_clkdev(clk[pwm3], "pwm", "2088000.pwm");
+	clk_register_clkdev(clk[pwm4], "pwm", "208c000.pwm");
 	clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
 	clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
 	clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..0b13f34 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -32,6 +33,7 @@
 #define MX3_PWMSAR                0x0C    /* PWM Sample Register */
 #define MX3_PWMPR                 0x10    /* PWM Period Register */
 #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
+#define MX3_PWMCR_STOPEN		(1 << 25)
 #define MX3_PWMCR_DOZEEN                (1 << 24)
 #define MX3_PWMCR_WAITEN                (1 << 23)
 #define MX3_PWMCR_DBGEN			(1 << 22)
@@ -68,25 +70,21 @@ static int imx_pwm_config(struct pwm_chip *chip,
 		prescale = period_cycles / 0x10000 + 1;
 
 		period_cycles /= prescale;
-		c = (unsigned long long)period_cycles * duty_ns;
-		do_div(c, period_ns);
-		duty_cycles = c;
 
-		/*
-		 * according to imx pwm RM, the real period value should be
-		 * PERIOD value in PWMPR plus 2.
+		/* the chip documentation says the counter counts up to
+		 * period_cycles + 1 and then is reset to 0, so the
+		 *  actual period of the PWM wave is period_cycles + 2
 		 */
-		if (period_cycles > 2)
-			period_cycles -= 2;
-		else
-			period_cycles = 0;
+		c = (unsigned long long)(period_cycles + 2) * duty_ns;
+		do_div(c, period_ns);
+		duty_cycles = c;
 
 		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
 		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 
 		cr = MX3_PWMCR_PRESCALER(prescale) |
 			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
+			MX3_PWMCR_DBGEN | MX3_PWMCR_STOPEN;
 
 		if (cpu_is_mx25())
 			cr |= MX3_PWMCR_CLKSRC_IPG;
@@ -124,6 +122,7 @@ static int imx_pwm_config(struct pwm_chip *chip,
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
+	unsigned long reg;
 	int rc = 0;
 
 	if (!imx->clk_enabled) {
@@ -131,6 +130,11 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 		if (!rc)
 			imx->clk_enabled = 1;
 	}
+
+	reg = readl(imx->mmio_base + MX3_PWMCR);
+	reg |= MX3_PWMCR_EN;
+	writel(reg, imx->mmio_base + MX3_PWMCR);
+
 	return rc;
 }
 
@@ -206,9 +212,15 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
 	return pwmchip_remove(&imx->chip);
 }
 
+static const struct of_device_id mxc_pwm_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-pwm", },
+	{ /* sentinel */ }
+};
+
 static struct platform_driver imx_pwm_driver = {
 	.driver		= {
 		.name	= "mxc_pwm",
+		.of_match_table = of_match_ptr(mxc_pwm_dt_ids),
 	},
 	.probe		= imx_pwm_probe,
 	.remove		= __devexit_p(imx_pwm_remove),
-- 
1.7.1



From lars at metafoo.de  Thu Aug 23 11:43:32 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 23 Aug 2012 17:43:32 +0200
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <217877237.2758643.1345731587941.JavaMail.root@advansee.com>
References: <217877237.2758643.1345731587941.JavaMail.root@advansee.com>
Message-ID: <50364FA4.7000401@metafoo.de>

On 08/23/2012 04:19 PM, Beno?t Th?baudeau wrote:
> Some PWM drivers enable the clock of the PWM peripheral in pwm_enable(). Hence,
> for these drivers, a call to pwm_config() does not have any effect before
> pwm_enable() has been called.
> 
> This patch fixes the PWM users to make sure that they call pwm_enable() before
> pwm_config().
> 
> This fixes the first setting of brightness through sysfs that had no effect with
> leds-pwm and the i.MX PWM driver.

But isn't this a bug in the PWM peripheral driver? With this change the PWM
will start with the old settings first. While this is not so much of a problem
for a backlight (although it might cause a short flickering) it might cause
problems for other applications, like using the PWM pin as a timing generator.
In my opinion it's better to fix the PWM peripheral drivers which have this
problem instead of trying to work around it in every user of the PWM API.

- Lars


From arnd at arndb.de  Thu Aug 23 12:01:18 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 16:01:18 +0000
Subject: [GIT PULL] arm-soc fixes for v3.6-rc3
Message-ID: <201208231601.18358.arnd@arndb.de>

Hi Linus,

I don't know what happened with the set of patches that I sent, so I'm
hoping you dropped accidentally. Here are the same patches and then
some more that came in since.

	Arnd

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-3.6-rc3

for you to fetch changes up to 57f0b2014135235d5bf03834dee1284629ce50d2:

  Merge branch 'randconfig/mach' into fixes (2012-08-23 17:30:54 +0200)

----------------------------------------------------------------

arm-soc fixes for v3.6-rc3

Bug fixes for various ARM platforms. About half of these are
for OMAP and submitted before but did not make it into v3.6-rc2.

----------------------------------------------------------------
Afzal Mohammed (1):
      arm/dts: Fix am33xx wdt node

Arnaud Patard (3):
      ARM: Orion: Set eth packet size csum offload limit
      ARM: Kirkwood: Fix iconnect leds
      ARM: Kirkwood: fix Makefile.boot

Arnd Bergmann (14):
      ARM: mv78xx0: fix win_cfg_base prototype
      Merge tag 'omap-fixes-for-v3.6-rc1' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge branch 'fixes-for-v3.6' of git://git.infradead.org/users/jcooper/linux into fixes
      Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes
      Merge branch 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
      Merge branch 'v3.6-samsung-fixes-1' of git://git.kernel.org/.../kgene/linux-samsung into fixes
      Merge tag 'ux500-fixes-v3.6-rc2' of git://git.kernel.org/.../linusw/linux-stericsson into fixes
      ARM: omap: allow building omap44xx without SMP
      ARM: imx: build pm-imx5 code only when PM is enabled
      ARM: imx: fix ksz9021rn_phy_fixup
      ARM: imx: select CPU_FREQ_TABLE when needed
      ARM: imx: build i.MX6 functions only when needed
      ARM: ux500: don't select LEDS_GPIO for snowball
      Merge branch 'randconfig/mach' into fixes

Domenico Andreoli (1):
      OMAP: remove unused parameter arch_id from uncompress.h

Heiko Stuebner (2):
      ARM: S3C24XX: Add missing DMACH_DT_PROP
      ARM: S3C24XX: Fix s3c2410_dma_enqueue parameters

Igor Grinberg (1):
      Revert "ARM: OMAP3530evm: set pendown_state and debounce time for ads7846"

Jan Luebbe (1):
      omap: Fix multi.h when only ARCH_OMAP3 and SOC_AM33XX are selected

Javier Martinez Canillas (1):
      ARM: OMAP3: igep0020: set GPIO mode for mux mcspi1_cs2 pin

Jon Hunter (1):
      ARM: OMAP2+: Fix dmtimer set source clock failure

Kevin Hilman (2):
      ARM: OMAP3: TWL4030: ensure sys_nirq1 is mux'd and wakeup enabled
      Revert "ARM: OMAP3: PM: call pre/post transition per powerdomain"

Lee Jones (2):
      ARM: ux500: Fix merge error, no matching driver name for 'snd_soc_u8500'
      ARM: ux500: Ensure probing of Audio devices when Device Tree is enabled

Michael Jones (1):
      omap2: mux: remove comment for nonexistent member

Philipp Zabel (1):
      ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path

Rajendra Nayak (3):
      arm/dts: Mark vcxio, v2v1 and v1v8 regulators as always on
      cpufreq: OMAP: Handle missing frequency table on SMP systems
      ARM: OMAP4: Register the OPP table only for 4430 device

Sachin Kamat (3):
      ARM: Samsung: Make uart_save static in pm.c file
      ARM: SAMSUNG: Set HDMI platform data for Exynos4x12 SoCs
      ARM: EXYNOS: Set HDMI platform data in SMDKV310

Santosh Shilimkar (2):
      OMAP2+: Fix random config build break with !ARM_CPU_SUSPEND
      ARM: OMAP4: sleep: Save the complete used register stack frame

Shawn Guo (2):
      ARM: imx6: spin the cpu until hardware takes it down
      ARM: dts: imx51-babbage: fix esdhc cd/wp properties

Timo Kokkonen (1):
      ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*()

Tony Lindgren (2):
      Merge branch 'for_3.6/fixes/ads7846-2' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes
      Merge branch 'for_3.6/fixes/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into fixes

Tushar Behera (2):
      ARM: SAMSUNG: Add API to set platform data for s5p-tv driver
      ARM: EXYNOS: Set HDMI platform data in Origen board

Vaibhav Hiremath (1):
      ARM: OMAP2+: cpu: Add am33xx device under cpu_class_is_omap2

Yuanhan Liu (1):
      ARM: mmp: fix potential NULL dereference

 .../devicetree/bindings/mmc/fsl-imx-esdhc.txt      |    8 +++---
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/am33xx.dtsi                      |    5 ++++
 arch/arm/boot/dts/imx51-babbage.dts                |    4 +--
 arch/arm/boot/dts/kirkwood-iconnect.dts            |    6 +++-
 arch/arm/boot/dts/twl6030.dtsi                     |    3 ++
 arch/arm/configs/u8500_defconfig                   |    1 +
 arch/arm/mach-dove/common.c                        |    3 +-
 arch/arm/mach-exynos/mach-origen.c                 |    7 +++++
 arch/arm/mach-exynos/mach-smdkv310.c               |    7 +++++
 arch/arm/mach-imx/Makefile                         |   10 +++----
 arch/arm/mach-imx/clk-imx6q.c                      |    8 ++++--
 arch/arm/mach-imx/{head-v7.S => headsmp.S}         |    0
 arch/arm/mach-imx/hotplug.c                        |   23 ++--------------
 arch/arm/mach-imx/mach-imx6q.c                     |    4 +--
 arch/arm/mach-kirkwood/Makefile.boot               |    3 +-
 arch/arm/mach-kirkwood/common.c                    |    4 +--
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |    6 ++--
 arch/arm/mach-omap2/Kconfig                        |    3 +-
 arch/arm/mach-omap2/board-igep0020.c               |    2 ++
 arch/arm/mach-omap2/board-omap3evm.c               |    1 +
 arch/arm/mach-omap2/common-board-devices.c         |   11 --------
 arch/arm/mach-omap2/common-board-devices.h         |    1 -
 arch/arm/mach-omap2/cpuidle44xx.c                  |    3 +-
 arch/arm/mach-omap2/mux.h                          |    1 -
 arch/arm/mach-omap2/opp4xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/pm34xx.c                       |   19 +++----------
 arch/arm/mach-omap2/sleep44xx.S                    |    8 ++++--
 arch/arm/mach-omap2/twl-common.c                   |    1 +
 arch/arm/mach-orion5x/common.c                     |    3 +-
 arch/arm/mach-s3c24xx/include/mach/dma.h           |    3 +-
 arch/arm/mach-ux500/Kconfig                        |    1 -
 arch/arm/mach-ux500/board-mop500-msp.c             |   10 +++----
 arch/arm/mach-ux500/board-mop500.c                 |    4 +++
 arch/arm/plat-omap/dmtimer.c                       |    6 ++--
 arch/arm/plat-omap/include/plat/cpu.h              |    3 +-
 arch/arm/plat-omap/include/plat/multi.h            |    9 ++++++
 arch/arm/plat-omap/include/plat/uncompress.h       |    4 +--
 arch/arm/plat-orion/common.c                       |    8 ++++--
 arch/arm/plat-orion/include/plat/common.h          |    6 ++--
 arch/arm/plat-s3c24xx/dma.c                        |    2 +-
 arch/arm/plat-samsung/devs.c                       |   29 +++++++++++++++++++-
 arch/arm/plat-samsung/include/plat/hdmi.h          |   16 +++++++++++
 arch/arm/plat-samsung/pm.c                         |    2 +-
 drivers/cpufreq/omap-cpufreq.c                     |    4 ++-
 include/linux/cpuidle.h                            |    4 +++
 include/linux/mv643xx_eth.h                        |    2 ++
 49 files changed, 174 insertions(+), 101 deletions(-)
 rename arch/arm/mach-imx/{head-v7.S => headsmp.S} (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat/hdmi.h


From nicolas.ferre at atmel.com  Thu Aug 23 12:14:54 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 23 Aug 2012 18:14:54 +0200
Subject: [PATCH] ASoC: atmel-ssc: include linux/io.h for raw io
In-Reply-To: <20120823152324.GI7995@opensource.wolfsonmicro.com>
References: <20120823152324.GI7995@opensource.wolfsonmicro.com>
Message-ID: <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>

From: Joachim Eastwood <manabian at gmail.com>

Include linux/io.h for raw io operations in atmel-scc header.

This fixes the following build error:
  CC [M]  sound/soc/atmel/atmel_ssc_dai.o
sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'

Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Mark,

Here is a copy of the original patch by Joachim. Can you please take a look and
give your acknowledgement so that I can queue it in arm-soc tree.

Thanks, bye,

 include/linux/atmel-ssc.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
index 0602339..4eb3175 100644
--- a/include/linux/atmel-ssc.h
+++ b/include/linux/atmel-ssc.h
@@ -3,6 +3,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
 struct ssc_device {
 	struct list_head	list;
-- 
1.7.10



From plagnioj at jcrosoft.com  Thu Aug 23 12:46:22 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 23 Aug 2012 18:46:22 +0200
Subject: [PATCH] ASoC: atmel-ssc: include linux/io.h for raw io
In-Reply-To: <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
References: <20120823152324.GI7995@opensource.wolfsonmicro.com>
 <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20120823164622.GA7629@game.jcrosoft.org>

On 18:14 Thu 23 Aug     , Nicolas Ferre wrote:
> From: Joachim Eastwood <manabian at gmail.com>
> 
> Include linux/io.h for raw io operations in atmel-scc header.
> 
> This fixes the following build error:
>   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
> sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
> sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'
> 
> Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Best Regards,
J.
> ---
> Mark,
> 
> Here is a copy of the original patch by Joachim. Can you please take a look and
> give your acknowledgement so that I can queue it in arm-soc tree.
> 
> Thanks, bye,
> 
>  include/linux/atmel-ssc.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
> index 0602339..4eb3175 100644
> --- a/include/linux/atmel-ssc.h
> +++ b/include/linux/atmel-ssc.h
> @@ -3,6 +3,7 @@
>  
>  #include <linux/platform_device.h>
>  #include <linux/list.h>
> +#include <linux/io.h>
>  
>  struct ssc_device {
>  	struct list_head	list;
> -- 
> 1.7.10
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From olof at lixom.net  Thu Aug 23 12:51:29 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 23 Aug 2012 09:51:29 -0700
Subject: [PATCH] ARM: omap: add dtb targets
Message-ID: <1345740689-21676-1-git-send-email-olof@lixom.net>

Makes it easier to just do 'make dtbs' for whatever the kernel was
configured for, just like some other platforms.

Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-omap2/Makefile.boot | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
index b03e562..6cf1c2d 100644
--- a/arch/arm/mach-omap2/Makefile.boot
+++ b/arch/arm/mach-omap2/Makefile.boot
@@ -1,3 +1,9 @@
   zreladdr-y		+= 0x80008000
 params_phys-y		:= 0x80000100
 initrd_phys-y		:= 0x80800000
+
+dtb-$(CONFIG_SOC_OMAP2420)	+= omap2420-h4.dtb
+dtb-$(CONFIG_ARCH_OMAP3)	+= omap3-beagle.dtb omap3-evm.dtb
+dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-panda.dtb omap4-pandaES.dtb
+dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-var_som.dtb omap4-sdp.dtb
+dtb-$(CONFIG_SOC_OMAP5)		+= omap5-evm.dtb
-- 
1.7.10.1.488.g05fbf7a



From benoit.thebaudeau at advansee.com  Thu Aug 23 12:57:05 2012
From: benoit.thebaudeau at advansee.com (=?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?=)
Date: Thu, 23 Aug 2012 18:57:05 +0200 (CEST)
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <50364FA4.7000401@metafoo.de>
Message-ID: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>

On Thursday, August 23, 2012 5:43:32 PM, Lars-Peter Clausen wrote:
> On 08/23/2012 04:19 PM, Beno?t Th?baudeau wrote:
> > Some PWM drivers enable the clock of the PWM peripheral in
> > pwm_enable(). Hence,
> > for these drivers, a call to pwm_config() does not have any effect
> > before
> > pwm_enable() has been called.
> > 
> > This patch fixes the PWM users to make sure that they call
> > pwm_enable() before
> > pwm_config().
> > 
> > This fixes the first setting of brightness through sysfs that had
> > no effect with
> > leds-pwm and the i.MX PWM driver.
> 
> But isn't this a bug in the PWM peripheral driver? With this change
> the PWM
> will start with the old settings first. While this is not so much of
> a problem
> for a backlight (although it might cause a short flickering) it might
> cause
> problems for other applications, like using the PWM pin as a timing
> generator.
> In my opinion it's better to fix the PWM peripheral drivers which
> have this
> problem instead of trying to work around it in every user of the PWM
> API.

I don't know. See my detailed description of this issue here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/115667.html

Where the bug is depends on the detailed definition of the PWM API, which I
don't find documented anywhere.

If pwm_enable() means "start PWM timer with the configured settings", then the
bug is in the drivers. If it means "enable the PWM peripheral so that we can
work with it", then the bug is in the PWM users.

I don't really have time to work on this, so I suggested this patch as a simple
solution. Otherwise, it means reworking several PWM drivers for different
hardware that is not available to everyone for testing.

If we decide to only change the i.MX PWM driver, the fix would be:
pwm_config()
{
        save passed config in private data;
        if (pwm enabled)
                apply passed config;
}

pwm_enable()
{
        if (!(pwm enabled)) {
                enable pwm ip clk;
                apply config from private data;
        }
}

If we fix only this driver, we must not forget that the same issue probably
exists with several other PWM drivers.

As I said in my bug description, the PWM users set the duty cycle to 0 before
calling pwm_disable(), so fixing the PWM users should not be an issue, even in
the timing generator use case you're talking about.

I don't have a strong opinion about what should be fixed here.

Best regards,
Beno?t


From lars at metafoo.de  Thu Aug 23 13:12:04 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 23 Aug 2012 19:12:04 +0200
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>
References: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>
Message-ID: <50366464.4070801@metafoo.de>

On 08/23/2012 06:57 PM, Beno?t Th?baudeau wrote:
> On Thursday, August 23, 2012 5:43:32 PM, Lars-Peter Clausen wrote:
>> On 08/23/2012 04:19 PM, Beno?t Th?baudeau wrote:
>>> Some PWM drivers enable the clock of the PWM peripheral in
>>> pwm_enable(). Hence,
>>> for these drivers, a call to pwm_config() does not have any effect
>>> before
>>> pwm_enable() has been called.
>>>
>>> This patch fixes the PWM users to make sure that they call
>>> pwm_enable() before
>>> pwm_config().
>>>
>>> This fixes the first setting of brightness through sysfs that had
>>> no effect with
>>> leds-pwm and the i.MX PWM driver.
>>
>> But isn't this a bug in the PWM peripheral driver? With this change
>> the PWM
>> will start with the old settings first. While this is not so much of
>> a problem
>> for a backlight (although it might cause a short flickering) it might
>> cause
>> problems for other applications, like using the PWM pin as a timing
>> generator.
>> In my opinion it's better to fix the PWM peripheral drivers which
>> have this
>> problem instead of trying to work around it in every user of the PWM
>> API.
> 
> I don't know. See my detailed description of this issue here:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/115667.html
> 
> Where the bug is depends on the detailed definition of the PWM API, which I
> don't find documented anywhere.
> 
> If pwm_enable() means "start PWM timer with the configured settings", then the
> bug is in the drivers. If it means "enable the PWM peripheral so that we can
> work with it", then the bug is in the PWM users.

It really is the former. See the description of pwm_enable() in drivers/pwm/core.c

> 
> I don't really have time to work on this, so I suggested this patch as a simple
> solution. Otherwise, it means reworking several PWM drivers for different
> hardware that is not available to everyone for testing.
> 
> If we decide to only change the i.MX PWM driver, the fix would be:
> pwm_config()
> {
>         save passed config in private data;
>         if (pwm enabled)
>                 apply passed config;
> }
> 
> pwm_enable()
> {
>         if (!(pwm enabled)) {
>                 enable pwm ip clk;
>                 apply config from private data;
>         }
> }

Another option is to enable the clock if it is disabled when the device is
configured. E.g. that's what tegra does.

> 
> If we fix only this driver, we must not forget that the same issue probably
> exists with several other PWM drivers.
> 

Since this seems to be a common pattern in a number of PWM drivers it might
make sense to simply add support for enabling/disabling a clk to the pwm core.
Or maybe just use the runtime pm API for this. This probably makes even more
sense and grab a reference to the pm context when the enable() is called,
release it when disable() is called and also grab it before calling the
device's config callback and release it afterward.

- Lars


From lars at metafoo.de  Thu Aug 23 13:19:36 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 23 Aug 2012 19:19:36 +0200
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <50366464.4070801@metafoo.de>
References: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>
 <50366464.4070801@metafoo.de>
Message-ID: <50366628.5020007@metafoo.de>

On 08/23/2012 07:12 PM, Lars-Peter Clausen wrote:
>[...]
> Or maybe just use the runtime pm API for this. This probably makes even more
> sense and grab a reference to the pm context when the enable() is called,
> release it when disable() is called and also grab it before calling the
> device's config callback and release it afterward.

Btw. this seems to be exactly what the pwm-tiecap and pwm-tiehrpwm drivers
already do today. I'd just make that a core PWM framework feature.


From arnd at arndb.de  Thu Aug 23 13:26:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 23 Aug 2012 17:26:10 +0000
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <201208231135.11688.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de>
Message-ID: <201208231726.11293.arnd@arndb.de>

On Thursday 23 August 2012, Arnd Bergmann wrote:
> On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
> > In any case, what we should be doing here as well is moving the headers
> > included by drivers for platform data out of the arch/arm/mach/ subtrees
> > and into include/linux/platform_data.  That will substantially reduce the
> > amount of mach/ headers to deal with.
> 
> I've just looked at the {mach,plat}/*.h files that get included in ARM
> specific drivers. Out of the 342 header files that get used in this way,
> I found 93 that are practically just platform data, and a few that
> are platform_data mixed with something else.
> 
> How about I move all the pure platform data definition files now and
> rebase the other patches on top of that. Here is a list of suggested
> file names in include/linux/platform_data/:

I've just scripted this and am running my build testsuite over it now.

Please let me know what you think about it.

	Arnd

The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git 

for you to fetch changes up to 25296e032db173e8376123c2801cd233c9dc9b78:

  ARM: spear: move platform_data definitions (2012-08-23 19:15:49 +0200)

----------------------------------------------------------------
Arnd Bergmann (16):
      ARM: at91: move platform_data definitions
      ARM: davinci: move platform_data definitions
      ARM: ep93xx: move platform_data definitions
      ARM: imx: move platform_data definitions
      ARM: msm: move platform_data definitions
      ARM: netx: move platform_data definitions
      ARM: pxa: move platform_data definitions
      ARM: sa1100: move platform_data definitions
      ARM: tegra: move platform_data definitions
      ARM: vt8500: move platform_data definitions
      ARM: w90x900: move platform_data definitions
      ARM: nomadik: move platform_data definitions
      ARM: omap: move platform_data definitions
      ARM: orion: move platform_data definitions
      ARM: samsung: move platform_data definitions
      ARM: spear: move platform_data definitions

 Documentation/spi/ep93xx_spi                       |    2 +-
 arch/arm/mach-at91/at91sam9g45_devices.c           |    2 +-
 arch/arm/mach-at91/at91sam9rl_devices.c            |    2 +-
 arch/arm/mach-at91/include/mach/atmel-mci.h        |    2 +-
 arch/arm/mach-davinci/aemif.c                      |    2 +-
 arch/arm/mach-davinci/board-da830-evm.c            |    8 ++++----
 arch/arm/mach-davinci/board-da850-evm.c            |    6 +++---
 arch/arm/mach-davinci/board-dm355-evm.c            |    8 ++++----
 arch/arm/mach-davinci/board-dm355-leopard.c        |    8 ++++----
 arch/arm/mach-davinci/board-dm365-evm.c            |    8 ++++----
 arch/arm/mach-davinci/board-dm644x-evm.c           |   10 +++++-----
 arch/arm/mach-davinci/board-dm646x-evm.c           |    6 +++---
 arch/arm/mach-davinci/board-mityomapl138.c         |    4 ++--
 arch/arm/mach-davinci/board-neuros-osd2.c          |    8 ++++----
 arch/arm/mach-davinci/board-sffsdr.c               |    4 ++--
 arch/arm/mach-davinci/davinci.h                    |    4 ++--
 arch/arm/mach-davinci/devices.c                    |    4 ++--
 arch/arm/mach-davinci/dm355.c                      |    4 ++--
 arch/arm/mach-davinci/dm365.c                      |    6 +++---
 arch/arm/mach-davinci/dm644x.c                     |    2 +-
 arch/arm/mach-davinci/dm646x.c                     |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h         |   10 +++++-----
 arch/arm/mach-davinci/include/mach/tnetv107x.h     |    4 ++--
 arch/arm/mach-davinci/usb.c                        |    2 +-
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-ep93xx/core.c                        |    6 +++---
 arch/arm/mach-ep93xx/dma.c                         |    2 +-
 arch/arm/mach-ep93xx/edb93xx.c                     |    4 ++--
 arch/arm/mach-ep93xx/simone.c                      |    2 +-
 arch/arm/mach-ep93xx/snappercl15.c                 |    2 +-
 arch/arm/mach-ep93xx/vision_ep9307.c               |    4 ++--
 arch/arm/mach-exynos/dev-audio.c                   |    2 +-
 arch/arm/mach-exynos/dev-ohci.c                    |    2 +-
 arch/arm/mach-exynos/mach-nuri.c                   |    6 +++---
 arch/arm/mach-exynos/mach-origen.c                 |    6 +++---
 arch/arm/mach-exynos/mach-smdk4x12.c               |    2 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |    6 +++---
 arch/arm/mach-exynos/mach-universal_c210.c         |    4 ++--
 arch/arm/mach-exynos/setup-i2c0.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c1.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c2.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c3.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c4.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c5.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c6.c                  |    2 +-
 arch/arm/mach-exynos/setup-i2c7.c                  |    2 +-
 arch/arm/mach-kirkwood/board-dreamplug.c           |    2 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   10 +++++-----
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    2 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    2 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    2 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    2 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    2 +-
 arch/arm/mach-mmp/aspenite.c                       |    2 +-
 arch/arm/mach-mmp/include/mach/mmp2.h              |    2 +-
 arch/arm/mach-mmp/include/mach/pxa168.h            |    4 ++--
 arch/arm/mach-mmp/include/mach/pxa910.h            |    2 +-
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mmp/teton_bga.c                      |    2 +-
 arch/arm/mach-msm/board-qsd8x50.c                  |    2 +-
 arch/arm/mach-msm/board-trout-mmc.c                |    2 +-
 arch/arm/mach-msm/board-trout-panel.c              |    2 +-
 arch/arm/mach-msm/devices-msm7x00.c                |    2 +-
 arch/arm/mach-msm/devices-msm7x30.c                |    2 +-
 arch/arm/mach-msm/devices-qsd8x50.c                |    2 +-
 arch/arm/mach-msm/include/mach/board.h             |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |    4 ++--
 arch/arm/mach-netx/nxdb500.c                       |    2 +-
 arch/arm/mach-netx/nxdkn.c                         |    2 +-
 arch/arm/mach-netx/nxeb500hmi.c                    |    2 +-
 arch/arm/mach-nomadik/board-nhk8815.c              |    2 +-
 arch/arm/mach-omap1/board-ams-delta.c              |    2 +-
 arch/arm/mach-omap1/board-fsample.c                |    2 +-
 arch/arm/mach-omap1/board-h2.c                     |    2 +-
 arch/arm/mach-omap1/board-h3.c                     |    2 +-
 arch/arm/mach-omap1/board-htcherald.c              |    2 +-
 arch/arm/mach-omap1/board-innovator.c              |    2 +-
 arch/arm/mach-omap1/board-nokia770.c               |    4 ++--
 arch/arm/mach-omap1/board-osk.c                    |    2 +-
 arch/arm/mach-omap1/board-palmte.c                 |    2 +-
 arch/arm/mach-omap1/board-palmtt.c                 |    2 +-
 arch/arm/mach-omap1/board-palmz71.c                |    2 +-
 arch/arm/mach-omap1/board-perseus2.c               |    2 +-
 arch/arm/mach-omap1/board-sx1.c                    |    2 +-
 arch/arm/mach-omap1/mcbsp.c                        |    2 +-
 arch/arm/mach-omap2/board-3430sdp.c                |    2 +-
 arch/arm/mach-omap2/board-cm-t35.c                 |    4 ++--
 arch/arm/mach-omap2/board-cm-t3517.c               |    2 +-
 arch/arm/mach-omap2/board-devkit8000.c             |    4 ++--
 arch/arm/mach-omap2/board-flash.c                  |    4 ++--
 arch/arm/mach-omap2/board-igep0020.c               |    2 +-
 arch/arm/mach-omap2/board-ldp.c                    |    2 +-
 arch/arm/mach-omap2/board-n8x0.c                   |    4 ++--
 arch/arm/mach-omap2/board-omap3beagle.c            |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c               |    4 ++--
 arch/arm/mach-omap2/board-omap3pandora.c           |    4 ++--
 arch/arm/mach-omap2/board-omap3stalker.c           |    4 ++--
 arch/arm/mach-omap2/board-omap3touchbook.c         |    4 ++--
 arch/arm/mach-omap2/board-overo.c                  |    4 ++--
 arch/arm/mach-omap2/board-rm680.c                  |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c       |    4 ++--
 arch/arm/mach-omap2/board-rx51-video.c             |    2 +-
 arch/arm/mach-omap2/board-rx51.c                   |    2 +-
 arch/arm/mach-omap2/board-zoom-display.c           |    2 +-
 arch/arm/mach-omap2/common-board-devices.c         |    4 ++--
 arch/arm/mach-omap2/devices.c                      |    2 +-
 arch/arm/mach-omap2/dsp.c                          |    2 +-
 arch/arm/mach-omap2/gpmc-nand.c                    |    2 +-
 arch/arm/mach-omap2/gpmc-onenand.c                 |    2 +-
 arch/arm/mach-omap2/mcbsp.c                        |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    4 ++--
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    4 ++--
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    4 ++--
 arch/arm/mach-omap2/voltage.h                      |    2 +-
 arch/arm/mach-orion5x/common.c                     |    4 ++--
 arch/arm/mach-orion5x/db88f5281-setup.c            |    2 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    2 +-
 arch/arm/mach-pxa/am200epd.c                       |    2 +-
 arch/arm/mach-pxa/am300epd.c                       |    2 +-
 arch/arm/mach-pxa/balloon3.c                       |    8 ++++----
 arch/arm/mach-pxa/cm-x270.c                        |    4 ++--
 arch/arm/mach-pxa/cm-x2xx.c                        |    2 +-
 arch/arm/mach-pxa/cm-x300.c                        |   10 +++++-----
 arch/arm/mach-pxa/colibri-evalboard.c              |    4 ++--
 arch/arm/mach-pxa/colibri-pxa270-income.c          |    6 +++---
 arch/arm/mach-pxa/colibri-pxa300.c                 |    4 ++--
 arch/arm/mach-pxa/colibri-pxa320.c                 |    4 ++--
 arch/arm/mach-pxa/colibri-pxa3xx.c                 |    6 +++---
 arch/arm/mach-pxa/corgi.c                          |    4 ++--
 arch/arm/mach-pxa/csb726.c                         |    4 ++--
 arch/arm/mach-pxa/devices.c                        |   16 ++++++++--------
 arch/arm/mach-pxa/em-x270.c                        |   10 +++++-----
 arch/arm/mach-pxa/eseries.c                        |    4 ++--
 arch/arm/mach-pxa/ezx.c                            |    8 ++++----
 arch/arm/mach-pxa/gumstix.c                        |    2 +-
 arch/arm/mach-pxa/hx4700.c                         |    2 +-
 arch/arm/mach-pxa/idp.c                            |    4 ++--
 arch/arm/mach-pxa/littleton.c                      |    8 ++++----
 arch/arm/mach-pxa/lpd270.c                         |    8 ++++----
 arch/arm/mach-pxa/lubbock.c                        |    6 +++---
 arch/arm/mach-pxa/magician.c                       |    8 ++++----
 arch/arm/mach-pxa/mainstone.c                      |   10 +++++-----
 arch/arm/mach-pxa/mioa701.c                        |    8 ++++----
 arch/arm/mach-pxa/mxm8x10.c                        |    8 ++++----
 arch/arm/mach-pxa/palm27x.c                        |    8 ++++----
 arch/arm/mach-pxa/palmld.c                         |   10 +++++-----
 arch/arm/mach-pxa/palmt5.c                         |   10 +++++-----
 arch/arm/mach-pxa/palmtc.c                         |    6 +++---
 arch/arm/mach-pxa/palmte2.c                        |    8 ++++----
 arch/arm/mach-pxa/palmtreo.c                       |   14 +++++++-------
 arch/arm/mach-pxa/palmtx.c                         |   10 +++++-----
 arch/arm/mach-pxa/palmz72.c                        |   12 ++++++------
 arch/arm/mach-pxa/pcm990-baseboard.c               |    8 ++++----
 arch/arm/mach-pxa/poodle.c                         |    6 +++---
 arch/arm/mach-pxa/pxa27x.c                         |    2 +-
 arch/arm/mach-pxa/pxa2xx.c                         |    2 +-
 arch/arm/mach-pxa/pxa3xx-ulpi.c                    |    2 +-
 arch/arm/mach-pxa/pxa3xx.c                         |    2 +-
 arch/arm/mach-pxa/raumfeld.c                       |    8 ++++----
 arch/arm/mach-pxa/saar.c                           |    2 +-
 arch/arm/mach-pxa/spitz.c                          |    8 ++++----
 arch/arm/mach-pxa/stargate2.c                      |    2 +-
 arch/arm/mach-pxa/tavorevb.c                       |    4 ++--
 arch/arm/mach-pxa/tosa.c                           |    4 ++--
 arch/arm/mach-pxa/trizeps4.c                       |    8 ++++----
 arch/arm/mach-pxa/viper.c                          |    4 ++--
 arch/arm/mach-pxa/vpac270.c                        |    8 ++++----
 arch/arm/mach-pxa/z2.c                             |    6 +++---
 arch/arm/mach-pxa/zeus.c                           |    8 ++++----
 arch/arm/mach-pxa/zylonite.c                       |   10 +++++-----
 arch/arm/mach-s3c24xx/common-smdk.c                |    4 ++--
 arch/arm/mach-s3c24xx/mach-amlm5900.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-anubis.c                |    6 +++---
 arch/arm/mach-s3c24xx/mach-at2440evb.c             |    6 +++---
 arch/arm/mach-s3c24xx/mach-bast.c                  |    8 ++++----
 arch/arm/mach-s3c24xx/mach-gta02.c                 |   10 +++++-----
 arch/arm/mach-s3c24xx/mach-h1940.c                 |    8 ++++----
 arch/arm/mach-s3c24xx/mach-jive.c                  |    6 +++---
 arch/arm/mach-s3c24xx/mach-mini2440.c              |   10 +++++-----
 arch/arm/mach-s3c24xx/mach-n30.c                   |    8 ++++----
 arch/arm/mach-s3c24xx/mach-nexcoder.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-osiris.c                |    4 ++--
 arch/arm/mach-s3c24xx/mach-otom.c                  |    2 +-
 arch/arm/mach-s3c24xx/mach-qt2410.c                |    8 ++++----
 arch/arm/mach-s3c24xx/mach-rx1950.c                |   10 +++++-----
 arch/arm/mach-s3c24xx/mach-rx3715.c                |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c              |    4 ++--
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |    8 ++++----
 arch/arm/mach-s3c24xx/mach-smdk2440.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |    2 +-
 arch/arm/mach-s3c24xx/mach-tct_hammer.c            |    2 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c                |    6 +++---
 arch/arm/mach-s3c24xx/mach-vstms.c                 |    4 ++--
 arch/arm/mach-s3c24xx/setup-i2c.c                  |    2 +-
 arch/arm/mach-s3c24xx/simtec-audio.c               |    2 +-
 arch/arm/mach-s3c24xx/simtec-usb.c                 |    2 +-
 arch/arm/mach-s3c64xx/dev-audio.c                  |    2 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410-module.c       |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    4 ++--
 arch/arm/mach-s3c64xx/mach-hmt.c                   |    4 ++--
 arch/arm/mach-s3c64xx/mach-mini6410.c              |    4 ++--
 arch/arm/mach-s3c64xx/mach-ncp.c                   |    2 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |    4 ++--
 arch/arm/mach-s3c64xx/mach-smartq.c                |    8 ++++----
 arch/arm/mach-s3c64xx/mach-smdk6400.c              |    2 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |    6 +++---
 arch/arm/mach-s3c64xx/setup-i2c0.c                 |    2 +-
 arch/arm/mach-s3c64xx/setup-i2c1.c                 |    2 +-
 arch/arm/mach-s3c64xx/setup-ide.c                  |    2 +-
 arch/arm/mach-s5p64x0/dev-audio.c                  |    2 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |    4 ++--
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |    4 ++--
 arch/arm/mach-s5p64x0/setup-i2c0.c                 |    2 +-
 arch/arm/mach-s5p64x0/setup-i2c1.c                 |    2 +-
 arch/arm/mach-s5pc100/dev-audio.c                  |    2 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |    8 ++++----
 arch/arm/mach-s5pc100/setup-i2c0.c                 |    2 +-
 arch/arm/mach-s5pc100/setup-i2c1.c                 |    2 +-
 arch/arm/mach-s5pv210/dev-audio.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
 arch/arm/mach-s5pv210/mach-smdkc110.c              |    4 ++--
 arch/arm/mach-s5pv210/mach-smdkv210.c              |    6 +++---
 arch/arm/mach-s5pv210/mach-torbreck.c              |    2 +-
 arch/arm/mach-s5pv210/setup-i2c0.c                 |    2 +-
 arch/arm/mach-s5pv210/setup-i2c1.c                 |    2 +-
 arch/arm/mach-s5pv210/setup-i2c2.c                 |    2 +-
 arch/arm/mach-sa1100/assabet.c                     |    2 +-
 arch/arm/mach-sa1100/cerf.c                        |    2 +-
 arch/arm/mach-sa1100/collie.c                      |    2 +-
 arch/arm/mach-sa1100/lart.c                        |    2 +-
 arch/arm/mach-sa1100/shannon.c                     |    2 +-
 arch/arm/mach-sa1100/simpad.c                      |    2 +-
 arch/arm/mach-tegra/board-harmony.c                |    4 ++--
 arch/arm/mach-tegra/board-paz00.c                  |    2 +-
 arch/arm/mach-tegra/board-trimslice.c              |    2 +-
 arch/arm/mach-u300/core.c                          |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |    2 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |    2 +-
 arch/arm/mach-ux500/devices-common.h               |    2 +-
 arch/arm/mach-ux500/usb.c                          |    2 +-
 arch/arm/mach-vt8500/devices.c                     |    2 +-
 arch/arm/mach-w90x900/dev.c                        |    6 +++---
 arch/arm/mach-w90x900/mach-nuc950evb.c             |    2 +-
 arch/arm/plat-omap/common.c                        |    2 +-
 arch/arm/plat-orion/common.c                       |    4 ++--
 arch/arm/plat-samsung/devs.c                       |   20 ++++++++++----------
 drivers/ata/pata_ep93xx.c                          |    2 +-
 drivers/ata/pata_pxa.c                             |    2 +-
 drivers/ata/pata_samsung_cf.c                      |    2 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |    2 +-
 drivers/crypto/ux500/hash/hash_core.c              |    2 +-
 drivers/dma/at_hdmac_regs.h                        |    2 +-
 drivers/dma/ep93xx_dma.c                           |    2 +-
 drivers/dma/mmp_tdma.c                             |    2 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/hwmon/s3c-hwmon.c                          |    2 +-
 drivers/i2c/busses/i2c-davinci.c                   |    2 +-
 drivers/i2c/busses/i2c-nuc900.c                    |    2 +-
 drivers/i2c/busses/i2c-s3c2410.c                   |    2 +-
 drivers/input/keyboard/davinci_keyscan.c           |    2 +-
 drivers/input/keyboard/ep93xx_keypad.c             |    2 +-
 drivers/input/keyboard/nomadik-ske-keypad.c        |    2 +-
 drivers/input/keyboard/omap-keypad.c               |    2 +-
 drivers/input/keyboard/pxa27x_keypad.c             |    2 +-
 drivers/input/keyboard/pxa930_rotary.c             |    2 +-
 drivers/input/keyboard/spear-keyboard.c            |    2 +-
 drivers/input/keyboard/tegra-kbc.c                 |    2 +-
 drivers/input/keyboard/w90p910_keypad.c            |    2 +-
 drivers/input/mouse/pxa930_trkball.c               |    2 +-
 drivers/input/touchscreen/s3c2410_ts.c             |    2 +-
 drivers/leds/leds-netxbig.c                        |    2 +-
 drivers/leds/leds-ns2.c                            |    2 +-
 drivers/leds/leds-s3c24xx.c                        |    2 +-
 drivers/media/video/davinci/vpbe_venc.c            |    2 +-
 drivers/media/video/pxa_camera.c                   |    2 +-
 drivers/media/video/s5p-fimc/mipi-csis.c           |    2 +-
 drivers/mfd/mcp-sa11x0.c                           |    2 +-
 drivers/mmc/host/davinci_mmc.c                     |    2 +-
 drivers/mmc/host/msm_sdcc.c                        |    2 +-
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mmc/host/pxamci.c                          |    2 +-
 drivers/mmc/host/s3cmci.c                          |    2 +-
 drivers/mmc/host/sdhci-tegra.c                     |    2 +-
 drivers/mtd/nand/davinci_nand.c                    |    4 ++--
 drivers/mtd/nand/nomadik_nand.c                    |    2 +-
 drivers/mtd/nand/omap2.c                           |    2 +-
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c                     |    2 +-
 drivers/mtd/nand/s3c2410.c                         |    2 +-
 drivers/mtd/onenand/omap2.c                        |    2 +-
 drivers/net/ethernet/netx-eth.c                    |    2 +-
 drivers/net/irda/pxaficp_ir.c                      |    2 +-
 drivers/pcmcia/pxa2xx_viper.c                      |    2 +-
 drivers/pinctrl/pinctrl-coh901.c                   |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |    2 +-
 drivers/spi/spi-davinci.c                          |    2 +-
 drivers/spi/spi-ep93xx.c                           |    4 ++--
 drivers/spi/spi-nuc900.c                           |    2 +-
 drivers/spi/spi-omap2-mcspi.c                      |    2 +-
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/staging/tidspbridge/core/dsp-clock.c       |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430.c      |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430_pwr.c  |    2 +-
 drivers/staging/tidspbridge/core/tiomap_io.c       |    2 +-
 drivers/staging/tidspbridge/rmgr/drv_interface.c   |    2 +-
 drivers/usb/gadget/s3c2410_udc.c                   |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 drivers/usb/host/ehci-s5p.c                        |    2 +-
 drivers/usb/host/ohci-da8xx.c                      |    2 +-
 drivers/usb/host/ohci-exynos.c                     |    2 +-
 drivers/usb/host/ohci-pxa27x.c                     |    4 ++--
 drivers/usb/host/ohci-s3c2410.c                    |    2 +-
 drivers/usb/musb/da8xx.c                           |    2 +-
 drivers/usb/musb/ux500_dma.c                       |    2 +-
 drivers/video/ep93xx-fb.c                          |    2 +-
 drivers/video/msm/mddi.c                           |    2 +-
 drivers/video/msm/mddi_client_dummy.c              |    2 +-
 drivers/video/msm/mddi_client_nt35399.c            |    2 +-
 drivers/video/msm/mddi_client_toshiba.c            |    2 +-
 drivers/video/msm/mdp.c                            |    2 +-
 drivers/video/msm/mdp_hw.h                         |    2 +-
 drivers/video/msm/mdp_ppp.c                        |    2 +-
 drivers/video/msm/msm_fb.c                         |    2 +-
 drivers/video/nuc900fb.c                           |    2 +-
 drivers/video/nuc900fb.h                           |    2 +-
 drivers/video/omap/lcd_mipid.c                     |    2 +-
 drivers/video/pxafb.c                              |    2 +-
 drivers/video/vt8500lcdfb.c                        |    2 +-
 drivers/video/wm8505fb.c                           |    2 +-
 .../linux/platform_data/asoc-davinci-evm.h         |    0
 .../linux/platform_data/asoc-imx-ssi.h             |    0
 .../linux/platform_data/asoc-kirkwood.h            |    0
 .../linux/platform_data/asoc-palm27x.h             |    0
 .../linux/platform_data/asoc-s3c.h                 |    0
 .../linux/platform_data/asoc-s3c24xx_simtec.h      |    0
 .../linux/platform_data/asoc-tegra_wm8903.h        |    0
 .../linux/platform_data/ata-pxa.h                  |    0
 .../linux/platform_data/ata-samsung_cf.h           |    0
 include/linux/platform_data/atmel-aes.h            |    2 +-
 .../linux/platform_data/camera-mx1.h               |    0
 .../linux/platform_data/camera-mx2.h               |    0
 .../linux/platform_data/camera-mx3.h               |    0
 .../linux/platform_data/camera-pxa.h               |    0
 .../linux/platform_data}/crypto-ux500.h            |    0
 .../linux/platform_data/dma-atmel.h                |    0
 .../linux/platform_data/dma-ep93xx.h               |    0
 .../linux/platform_data/dma-imx-sdma.h             |    0
 .../dma.h => include/linux/platform_data/dma-imx.h |    0
 .../linux/platform_data/dma-mmp_tdma.h             |    0
 .../linux/platform_data/dma-mv_xor.h               |    0
 .../linux/platform_data/dsp-mcbsp.h                |    0
 .../linux/platform_data/dsp-omap.h                 |    0
 .../linux/platform_data/eth-netx.h                 |    0
 .../linux/platform_data/hwmon-s3c.h                |    0
 .../linux/platform_data/i2c-davinci.h              |    0
 .../i2c.h => include/linux/platform_data/i2c-imx.h |    0
 .../linux/platform_data/i2c-nuc900.h               |    0
 .../linux/platform_data/i2c-s3c2410.h              |    0
 .../linux/platform_data/irda-pxaficp.h             |    0
 .../linux/platform_data/keyboard-pxa930_rotary.h   |    0
 .../linux/platform_data/keyboard-spear.h           |    0
 .../linux/platform_data/keyboard-tegra-kbc.h       |    0
 .../linux/platform_data/keypad-ep93xx.h            |    0
 .../linux/platform_data/keypad-nomadik-ske.h       |    0
 .../linux/platform_data/keypad-omap.h              |    0
 .../linux/platform_data/keypad-pxa27x.h            |    0
 .../linux/platform_data/keypad-w90p910.h           |    0
 .../linux/platform_data/keyscan-davinci.h          |    0
 .../linux/platform_data/lcd-mipid.h                |    0
 .../linux/platform_data/leds-kirkwood-netxbig.h    |    0
 .../linux/platform_data/leds-kirkwood-ns2.h        |    0
 .../linux/platform_data/leds-s3c24xx.h             |    0
 .../linux/platform_data/mfd-mcp-sa11x0.h           |    0
 .../linux/platform_data/mipi-csis.h                |    0
 .../linux/platform_data/mmc-davinci.h              |    0
 .../linux/platform_data/mmc-esdhc-imx.h            |    0
 .../linux/platform_data/mmc-msm_sdcc.h             |    0
 .../linux/platform_data/mmc-mvsdio.h               |    0
 .../linux/platform_data/mmc-mxcmmc.h               |    0
 .../linux/platform_data/mmc-pxamci.h               |    0
 .../linux/platform_data/mmc-s3cmci.h               |    0
 .../linux/platform_data/mmc-sdhci-tegra.h          |    0
 .../linux/platform_data/mouse-pxa930_trkball.h     |    0
 .../linux/platform_data/mtd-davinci-aemif.h        |    0
 .../linux/platform_data/mtd-davinci.h              |    0
 .../linux/platform_data/mtd-mxc_nand.h             |    0
 .../linux/platform_data/mtd-nand-omap2.h           |    0
 .../linux/platform_data/mtd-nand-pxa3xx.h          |    0
 .../linux/platform_data/mtd-nand-s3c2410.h         |    0
 .../linux/platform_data/mtd-nomadik-nand.h         |    0
 .../linux/platform_data/mtd-onenand-omap2.h        |    0
 .../linux/platform_data/mtd-orion_nand.h           |    0
 .../linux/platform_data/pcmcia-pxa2xx_viper.h      |    0
 .../linux/platform_data/pinctrl-coh901.h           |    0
 .../linux/platform_data/remoteproc-omap.h          |    0
 .../linux/platform_data/serial-imx.h               |    0
 .../linux/platform_data/smartreflex-omap.h         |    0
 .../linux/platform_data/spi-davinci.h              |    0
 .../linux/platform_data/spi-ep93xx.h               |    0
 .../linux/platform_data/spi-nuc900.h               |    0
 .../linux/platform_data/spi-omap2-mcspi.h          |    0
 .../linux/platform_data/spi-s3c64xx.h              |    0
 .../linux/platform_data/touchscreen-s3c2410.h      |    0
 .../linux/platform_data/usb-davinci.h              |    0
 .../linux/platform_data/usb-ehci-mxc.h             |    0
 .../linux/platform_data/usb-ehci-orion.h           |    0
 .../linux/platform_data/usb-ehci-s5p.h             |    0
 .../linux/platform_data/usb-exynos.h               |    0
 .../linux/platform_data/usb-imx_udc.h              |    0
 .../linux/platform_data/usb-musb-ux500.h           |    0
 .../linux/platform_data/usb-mx2.h                  |    0
 .../linux/platform_data/usb-ohci-pxa27x.h          |    0
 .../linux/platform_data/usb-ohci-s3c2410.h         |    0
 .../linux/platform_data/usb-pxa3xx-ulpi.h          |    0
 .../linux/platform_data/usb-s3c2410_udc.h          |    0
 .../linux/platform_data/video-ep93xx.h             |    0
 .../linux/platform_data/video-imxfb.h              |    0
 .../linux/platform_data/video-msm_fb.h             |    0
 .../linux/platform_data/video-mx3fb.h              |    0
 .../linux/platform_data/video-nuc900fb.h           |    0
 .../linux/platform_data/video-pxafb.h              |    0
 .../linux/platform_data/video-vt8500lcdfb.h        |    0
 include/linux/power/smartreflex.h                  |    2 +-
 sound/soc/davinci/davinci-evm.c                    |    2 +-
 sound/soc/davinci/davinci-i2s.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.h                  |    2 +-
 sound/soc/davinci/davinci-pcm.h                    |    2 +-
 sound/soc/ep93xx/ep93xx-ac97.c                     |    2 +-
 sound/soc/ep93xx/ep93xx-i2s.c                      |    2 +-
 sound/soc/ep93xx/ep93xx-pcm.c                      |    2 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    2 +-
 sound/soc/kirkwood/kirkwood-t5325.c                |    2 +-
 sound/soc/omap/am3517evm.c                         |    2 +-
 sound/soc/omap/ams-delta.c                         |    2 +-
 sound/soc/omap/igep0020.c                          |    2 +-
 sound/soc/omap/mcbsp.c                             |    2 +-
 sound/soc/omap/n810.c                              |    2 +-
 sound/soc/omap/omap-mcbsp.c                        |    2 +-
 sound/soc/omap/omap3beagle.c                       |    2 +-
 sound/soc/omap/omap3evm.c                          |    2 +-
 sound/soc/omap/omap3pandora.c                      |    2 +-
 sound/soc/omap/osk5912.c                           |    2 +-
 sound/soc/omap/overo.c                             |    2 +-
 sound/soc/omap/rx51.c                              |    2 +-
 sound/soc/omap/sdp3430.c                           |    2 +-
 sound/soc/omap/zoom2.c                             |    2 +-
 sound/soc/pxa/palm27x.c                            |    2 +-
 sound/soc/samsung/ac97.c                           |    2 +-
 sound/soc/samsung/i2s.c                            |    2 +-
 sound/soc/samsung/pcm.c                            |    2 +-
 sound/soc/samsung/s3c24xx_simtec.c                 |    2 +-
 sound/soc/samsung/spdif.c                          |    2 +-
 sound/soc/tegra/tegra_wm8903.c                     |    2 +-
 463 files changed, 625 insertions(+), 625 deletions(-)
 rename arch/arm/mach-davinci/include/mach/asp.h => include/linux/platform_data/asoc-davinci-evm.h (100%)
 rename arch/arm/plat-mxc/include/mach/ssi.h => include/linux/platform_data/asoc-imx-ssi.h (100%)
 rename arch/arm/plat-orion/include/plat/audio.h => include/linux/platform_data/asoc-kirkwood.h (100%)
 rename arch/arm/mach-pxa/include/mach/palmasoc.h => include/linux/platform_data/asoc-palm27x.h (100%)
 rename arch/arm/plat-samsung/include/plat/audio.h => include/linux/platform_data/asoc-s3c.h (100%)
 rename arch/arm/plat-samsung/include/plat/audio-simtec.h => include/linux/platform_data/asoc-s3c24xx_simtec.h (100%)
 rename arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h => include/linux/platform_data/asoc-tegra_wm8903.h (100%)
 rename arch/arm/mach-pxa/include/mach/pata_pxa.h => include/linux/platform_data/ata-pxa.h (100%)
 rename arch/arm/plat-samsung/include/plat/ata.h => include/linux/platform_data/ata-samsung_cf.h (100%)
 rename arch/arm/plat-mxc/include/mach/mx1_camera.h => include/linux/platform_data/camera-mx1.h (100%)
 rename arch/arm/plat-mxc/include/mach/mx2_cam.h => include/linux/platform_data/camera-mx2.h (100%)
 rename arch/arm/plat-mxc/include/mach/mx3_camera.h => include/linux/platform_data/camera-mx3.h (100%)
 rename arch/arm/mach-pxa/include/mach/camera.h => include/linux/platform_data/camera-pxa.h (100%)
 rename {arch/arm/mach-ux500/include/mach => include/linux/platform_data}/crypto-ux500.h (100%)
 rename arch/arm/mach-at91/include/mach/at_hdmac.h => include/linux/platform_data/dma-atmel.h (100%)
 rename arch/arm/mach-ep93xx/include/mach/dma.h => include/linux/platform_data/dma-ep93xx.h (100%)
 rename arch/arm/plat-mxc/include/mach/sdma.h => include/linux/platform_data/dma-imx-sdma.h (100%)
 rename arch/arm/plat-mxc/include/mach/dma.h => include/linux/platform_data/dma-imx.h (100%)
 rename arch/arm/mach-mmp/include/mach/sram.h => include/linux/platform_data/dma-mmp_tdma.h (100%)
 rename arch/arm/plat-orion/include/plat/mv_xor.h => include/linux/platform_data/dma-mv_xor.h (100%)
 rename arch/arm/plat-omap/include/plat/mcbsp.h => include/linux/platform_data/dsp-mcbsp.h (100%)
 rename arch/arm/plat-omap/include/plat/dsp.h => include/linux/platform_data/dsp-omap.h (100%)
 rename arch/arm/mach-netx/include/mach/eth.h => include/linux/platform_data/eth-netx.h (100%)
 rename arch/arm/plat-samsung/include/plat/hwmon.h => include/linux/platform_data/hwmon-s3c.h (100%)
 rename arch/arm/mach-davinci/include/mach/i2c.h => include/linux/platform_data/i2c-davinci.h (100%)
 rename arch/arm/plat-mxc/include/mach/i2c.h => include/linux/platform_data/i2c-imx.h (100%)
 rename arch/arm/mach-w90x900/include/mach/i2c.h => include/linux/platform_data/i2c-nuc900.h (100%)
 rename arch/arm/plat-samsung/include/plat/iic.h => include/linux/platform_data/i2c-s3c2410.h (100%)
 rename arch/arm/mach-pxa/include/mach/irda.h => include/linux/platform_data/irda-pxaficp.h (100%)
 rename arch/arm/mach-pxa/include/mach/pxa930_rotary.h => include/linux/platform_data/keyboard-pxa930_rotary.h (100%)
 rename arch/arm/plat-spear/include/plat/keyboard.h => include/linux/platform_data/keyboard-spear.h (100%)
 rename arch/arm/mach-tegra/include/mach/kbc.h => include/linux/platform_data/keyboard-tegra-kbc.h (100%)
 rename arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h => include/linux/platform_data/keypad-ep93xx.h (100%)
 rename arch/arm/plat-nomadik/include/plat/ske.h => include/linux/platform_data/keypad-nomadik-ske.h (100%)
 rename arch/arm/plat-omap/include/plat/keypad.h => include/linux/platform_data/keypad-omap.h (100%)
 rename arch/arm/plat-pxa/include/plat/pxa27x_keypad.h => include/linux/platform_data/keypad-pxa27x.h (100%)
 rename arch/arm/mach-w90x900/include/mach/w90p910_keypad.h => include/linux/platform_data/keypad-w90p910.h (100%)
 rename arch/arm/mach-davinci/include/mach/keyscan.h => include/linux/platform_data/keyscan-davinci.h (100%)
 rename arch/arm/plat-omap/include/plat/lcd_mipid.h => include/linux/platform_data/lcd-mipid.h (100%)
 rename arch/arm/mach-kirkwood/include/mach/leds-netxbig.h => include/linux/platform_data/leds-kirkwood-netxbig.h (100%)
 rename arch/arm/mach-kirkwood/include/mach/leds-ns2.h => include/linux/platform_data/leds-kirkwood-ns2.h (100%)
 rename arch/arm/mach-s3c24xx/include/mach/leds-gpio.h => include/linux/platform_data/leds-s3c24xx.h (100%)
 rename arch/arm/mach-sa1100/include/mach/mcp.h => include/linux/platform_data/mfd-mcp-sa11x0.h (100%)
 rename arch/arm/plat-samsung/include/plat/mipi_csis.h => include/linux/platform_data/mipi-csis.h (100%)
 rename arch/arm/mach-davinci/include/mach/mmc.h => include/linux/platform_data/mmc-davinci.h (100%)
 rename arch/arm/plat-mxc/include/mach/esdhc.h => include/linux/platform_data/mmc-esdhc-imx.h (100%)
 rename arch/arm/mach-msm/include/mach/mmc.h => include/linux/platform_data/mmc-msm_sdcc.h (100%)
 rename arch/arm/plat-orion/include/plat/mvsdio.h => include/linux/platform_data/mmc-mvsdio.h (100%)
 rename arch/arm/plat-mxc/include/mach/mmc.h => include/linux/platform_data/mmc-mxcmmc.h (100%)
 rename arch/arm/mach-pxa/include/mach/mmc.h => include/linux/platform_data/mmc-pxamci.h (100%)
 rename arch/arm/plat-samsung/include/plat/mci.h => include/linux/platform_data/mmc-s3cmci.h (100%)
 rename arch/arm/mach-tegra/include/mach/sdhci.h => include/linux/platform_data/mmc-sdhci-tegra.h (100%)
 rename arch/arm/mach-pxa/include/mach/pxa930_trkball.h => include/linux/platform_data/mouse-pxa930_trkball.h (100%)
 rename arch/arm/mach-davinci/include/mach/aemif.h => include/linux/platform_data/mtd-davinci-aemif.h (100%)
 rename arch/arm/mach-davinci/include/mach/nand.h => include/linux/platform_data/mtd-davinci.h (100%)
 rename arch/arm/plat-mxc/include/mach/mxc_nand.h => include/linux/platform_data/mtd-mxc_nand.h (100%)
 rename arch/arm/plat-omap/include/plat/nand.h => include/linux/platform_data/mtd-nand-omap2.h (100%)
 rename arch/arm/plat-pxa/include/plat/pxa3xx_nand.h => include/linux/platform_data/mtd-nand-pxa3xx.h (100%)
 rename arch/arm/plat-samsung/include/plat/nand.h => include/linux/platform_data/mtd-nand-s3c2410.h (100%)
 rename arch/arm/mach-nomadik/include/mach/nand.h => include/linux/platform_data/mtd-nomadik-nand.h (100%)
 rename arch/arm/plat-omap/include/plat/onenand.h => include/linux/platform_data/mtd-onenand-omap2.h (100%)
 rename arch/arm/plat-orion/include/plat/orion_nand.h => include/linux/platform_data/mtd-orion_nand.h (100%)
 rename arch/arm/mach-pxa/include/mach/arcom-pcmcia.h => include/linux/platform_data/pcmcia-pxa2xx_viper.h (100%)
 rename arch/arm/mach-u300/include/mach/gpio-u300.h => include/linux/platform_data/pinctrl-coh901.h (100%)
 rename arch/arm/plat-omap/include/plat/remoteproc.h => include/linux/platform_data/remoteproc-omap.h (100%)
 rename arch/arm/plat-mxc/include/mach/imx-uart.h => include/linux/platform_data/serial-imx.h (100%)
 rename arch/arm/plat-omap/include/plat/voltage.h => include/linux/platform_data/smartreflex-omap.h (100%)
 rename arch/arm/mach-davinci/include/mach/spi.h => include/linux/platform_data/spi-davinci.h (100%)
 rename arch/arm/mach-ep93xx/include/mach/ep93xx_spi.h => include/linux/platform_data/spi-ep93xx.h (100%)
 rename arch/arm/mach-w90x900/include/mach/nuc900_spi.h => include/linux/platform_data/spi-nuc900.h (100%)
 rename arch/arm/plat-omap/include/plat/mcspi.h => include/linux/platform_data/spi-omap2-mcspi.h (100%)
 rename arch/arm/plat-samsung/include/plat/s3c64xx-spi.h => include/linux/platform_data/spi-s3c64xx.h (100%)
 rename arch/arm/plat-samsung/include/plat/ts.h => include/linux/platform_data/touchscreen-s3c2410.h (100%)
 rename arch/arm/mach-davinci/include/mach/usb.h => include/linux/platform_data/usb-davinci.h (100%)
 rename arch/arm/plat-mxc/include/mach/mxc_ehci.h => include/linux/platform_data/usb-ehci-mxc.h (100%)
 rename arch/arm/plat-orion/include/plat/ehci-orion.h => include/linux/platform_data/usb-ehci-orion.h (100%)
 rename arch/arm/plat-samsung/include/plat/ehci.h => include/linux/platform_data/usb-ehci-s5p.h (100%)
 rename arch/arm/mach-exynos/include/mach/ohci.h => include/linux/platform_data/usb-exynos.h (100%)
 rename arch/arm/plat-mxc/include/mach/usb.h => include/linux/platform_data/usb-imx_udc.h (100%)
 rename arch/arm/mach-ux500/include/mach/usb.h => include/linux/platform_data/usb-musb-ux500.h (100%)
 rename arch/arm/plat-mxc/include/mach/mx21-usbhost.h => include/linux/platform_data/usb-mx2.h (100%)
 rename arch/arm/mach-pxa/include/mach/ohci.h => include/linux/platform_data/usb-ohci-pxa27x.h (100%)
 rename arch/arm/plat-samsung/include/plat/usb-control.h => include/linux/platform_data/usb-ohci-s3c2410.h (100%)
 rename arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h => include/linux/platform_data/usb-pxa3xx-ulpi.h (100%)
 rename arch/arm/plat-samsung/include/plat/udc.h => include/linux/platform_data/usb-s3c2410_udc.h (100%)
 rename arch/arm/mach-ep93xx/include/mach/fb.h => include/linux/platform_data/video-ep93xx.h (100%)
 rename arch/arm/plat-mxc/include/mach/imxfb.h => include/linux/platform_data/video-imxfb.h (100%)
 rename arch/arm/mach-msm/include/mach/msm_fb.h => include/linux/platform_data/video-msm_fb.h (100%)
 rename arch/arm/plat-mxc/include/mach/mx3fb.h => include/linux/platform_data/video-mx3fb.h (100%)
 rename arch/arm/mach-w90x900/include/mach/fb.h => include/linux/platform_data/video-nuc900fb.h (100%)
 rename arch/arm/mach-pxa/include/mach/pxafb.h => include/linux/platform_data/video-pxafb.h (100%)
 rename arch/arm/mach-vt8500/include/mach/vt8500fb.h => include/linux/platform_data/video-vt8500lcdfb.h (100%)


From tixy at yxit.co.uk  Thu Aug 23 13:28:54 2012
From: tixy at yxit.co.uk (Tixy)
Date: Thu, 23 Aug 2012 18:28:54 +0100
Subject: [PATCHv4 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <201208231209.26707.arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221841.29645.arnd@arndb.de>
 <1345679461.3601.20.camel@computer5.home>
 <201208231209.26707.arnd@arndb.de>
Message-ID: <1345742934.2586.6.camel@computer5.home>

On Thu, 2012-08-23 at 12:09 +0000, Arnd Bergmann wrote:
> commit abfef4db8731591fbb721262bd4712662aaa6d14
> Author: Arnd Bergmann <arnd at arndb.de>
> Date:   Thu Aug 16 07:49:31 2012 +0000
> 
>     ARM: kprobes: make more tests conditional
>     
>     The mls instruction is not available in ARMv6K or below, so we
>     should make the test conditional on at least ARMv7. ldrexd/strexd
>     are available in ARMv6K or ARMv7, which we can test by checking
>     the CONFIG_CPU_32v6K symbol.
>     
>     /tmp/ccuMTZ8D.s: Assembler messages:
>     /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
>     /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
>     /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
>     
>     Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>     Cc: Jon Medhurst <tixy at yxit.co.uk>
>     Cc: Russell King <rmk+kernel at arm.linux.org.uk>
>     Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
>     Cc: Leif Lindholm <leif.lindholm at arm.com>

Thanks for your indulgence :-) With the white-space damage fixed...

Acked-by: Jon Medhurst <tixy at yxit.co.uk>

I test built this for v6, v6k and v7 before and after applying the patch
to verify if behaves as expected, so you can add my Tested-by if you
want.

I also tried a v4 platform (forgot we supported those) and there will be
a patch coming to fix that...


> diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
> index 38c1a3b..8393129 100644
> --- a/arch/arm/kernel/kprobes-test-arm.c
> +++ b/arch/arm/kernel/kprobes-test-arm.c
> @@ -366,7 +366,9 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
> +#endif
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> @@ -456,6 +458,8 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
>  #if __LINUX_ARM_ARCH__ >= 6
>  	TEST_UNSUPPORTED("ldrex	r2, [sp]")
> +#endif
> +#if (__LINUX_ARM_ARCH__ >= 7) || defined(CONFIG_CPU_32v6K)
>  	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
>  	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
>  	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")




From will.deacon at arm.com  Thu Aug 23 13:48:43 2012
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 23 Aug 2012 18:48:43 +0100
Subject: [PATCH] ARM: decompressor: reset ttbcr for VMSA ARMv7 cores
Message-ID: <1345744123-4121-1-git-send-email-will.deacon@arm.com>

When enabling the MMU for ARMv7 CPUs, the decompressor does not touch
the ttbcr register, assuming that it will be zeroed (N == 0, EAE == 0).
Given that only EAE is defined as 0 for non-secure copies of the
register (and a bootloader such as kexec may leave it set to 1 anyway),
we should ensure that we reset the register ourselves before turning on
the MMU.

This patch zeroes TTBCR.EAE and TTBCR.N prior to enabling the MMU for
ARMv7 cores in the decompressor, configuring us exclusively for 32-bit
translation tables via TTBR0.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Matthew Leach <matthew.leach at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/boot/compressed/head.S |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b8c64b8..81769c1 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
 #ifdef CONFIG_CPU_ENDIAN_BE8
 		orr	r0, r0, #1 << 25	@ big-endian page tables
 #endif
+		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
 		orrne	r0, r0, #1		@ MMU enabled
 		movne	r1, #0xfffffffd		@ domain 0 = client
+		bic     r6, r6, #1 << 31        @ 32-bit translation system
+		bic     r6, r6, #3 << 0         @ use only ttbr0
 		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
 		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
+		mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
 #endif
 		mcr	p15, 0, r0, c7, c5, 4	@ ISB
 		mcr	p15, 0, r0, c1, c0, 0	@ load control register
-- 
1.7.4.1



From swarren at wwwdotorg.org  Thu Aug 23 13:49:31 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 11:49:31 -0600
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <5034FC18.2090400@wwwdotorg.org>
 <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>
Message-ID: <50366D2B.4010807@wwwdotorg.org>

On 08/23/2012 01:06 AM, Richard Genoud wrote:
> 2012/8/22 Stephen Warren <swarren at wwwdotorg.org>:
>>>> +Required properties for iomux controller:
>>>> +- compatible: "atmel,at91rm9200-pinctrl"
>>>> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
>>>> +  configured in this periph mode. All the periph and bank need to be describe.
>>>
>>> Can you please be more elaborate on this mux-mask, like what each bit
>>> means and why the bits are arranged like that and what it means on the
>>> AT91 platform.... I was first reading the .dts and was like ?woot? so
>>> I go to the bindings doc and I read this and I'm still like ?woot?..
>>
>> Yes, I'm a little confused what this is, and wouldn't have a clue how to
>> fill it in.
>
> With a practical example it's easier to understand.
> Take a SAM9X5 release manual (here is sam9g35):
> http://www.atmel.com/Images/doc11053.pdf page 11 (?4.3 package pinout)
> in the file arch/arm/boot/dts/at91sam9x5.dtsi you've got the the
> atmel,mux-mask like that:
>
> /* periphA  periphB    periphC     */
> 0xffffffff 0xffe0399f 0xc000001c  /* pioA */
> 0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
> 0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
> 0x003fffff 0x003f8000 0x00000000  /* pioD */
> 
> Let's take the PioA - peripheral B: 0xffe0399f
> From the documentation table 4-3, we can extract the column PIO
> Periperal B for all signals PA0-PA31:
...
> Each time it's possible to mux a pin to the peripheral B function (ie
> when there's no "-----") the corresponding bit is set:
...
> => this gives 0x399f

Ah OK. It would be a good idea to briefly describe this process in the
binding document I think. I assume this property exists to avoid the
kernel driver having to contain tables for each Atmel device; the driver
is generic.


From swarren at wwwdotorg.org  Thu Aug 23 13:54:12 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 11:54:12 -0600
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
Message-ID: <50366E44.4030606@wwwdotorg.org>

On 08/23/2012 03:45 AM, Sebastian Hesselbarth wrote:
> On 8/22/12, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> On 08/22/2012 02:22 AM, Sebastian Hesselbarth wrote:
>>> +++ b/drivers/pinctrl/pinctrl-mvebu.c
>>
>>> +static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
>>
>>> +	of_property_for_each_string(np, "marvell,pins", prop, group) {
>>> +		struct mvebu_pinctrl_group *grp =
>>> +			mvebu_pinctrl_find_group_by_name(pctl, group);
>>> +
>>> +		if (!grp) {
>>> +			dev_err(pctl->dev, "unknown pin %s", group);
>>> +			continue;
>>> +		}
>>> +
>>> +		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
>>> +			dev_err(pctl->dev, "unsupported function %s on pin %s",
>>> +				function, group);
>>> +			continue;
>>> +		}
>>
>> The error-checking here isn't strictly necessary; the pinctrl core will
>> error-check all the names if/when the map entries are used. So, you
>> could probably get away with just assigning the pin/function names
>> directly into (*map) and hence remove some code here. Still, it's not a
>> big deal either way.
> 
> Hi Stephen,
> 
> as these error checks are only performed once, I'd like to have them there
> as they give hints when someone uses wrong marvell,pins/function names
> in DT.
> 
>>> +static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl
>>> *pctl,
>>
>>> +static int __devinit mvebu_pinctrl_dt_parse(struct platform_device
>>> *pdev,
>>> +					struct mvebu_pinctrl *pctl)
>>
>> I don't understand what those two functions do, or a good chunk of
>> probe(). It seems like they're setting up the ability to get/set pin
>> configrations in addition to pin muxing, although if that's so, it seems
>> odd that none of the binding documents specify any way of controlling
>> pin configuration from device tree. Are you expecting drivers to call
>> APIs such as pin_config_set() directly, rather than controlling pin
>> config through DT?
> 
> probe() receives some structs from the SoC specific driver stubs that
> describe, e.g. how many muxable pins are available, which pingroup they
> belong to (marvell,pins), what valid register values are and how they are
> named (marvell,function). Although, all mvebu SoC share a good part of
> pinmux register layout, there are especially for dove some very different
> ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no
> pin drive strength or pin direction configuration, we decided not to have
> single pins controlable but only pingroups even if they comprise only a
> single pin.
> 
> dt_parse() and dt_parse_function() build up structs that get used later on
> in mvebu_pinmux_ops that require indexed functions. I can join them with
> dt_node_to_map() but that would require incremental kzalloc for the
> corresponding array. Or I could (functionally) leave dt_parse() to allocate
> the array and only join dt_parse_function() with dt_node_to_map().

So everything you said makes sense, in that the core driver is
parameterizable and receives data from a SoC-variant-specific driver
indicating which pins/groups/functions are available. I'm still not sure
though why the translation of the pin/group/function structures passed
to probe into other data structures requires accessing the DT at all;
the set of available pins/groups/functions isn't configured through DT,
and doesn't need to be limited to only those options actually used in
DT, so can't you just process all the data that's passed to probe
without interaction with the DT?



From swarren at wwwdotorg.org  Thu Aug 23 13:56:58 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 11:56:58 -0600
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use imx-syscon
 to access anatop register
In-Reply-To: <20120823061202.GM4011@b20223-02.ap.freescale.net>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <5035BDBF.9020602@wwwdotorg.org>
 <20120823061202.GM4011@b20223-02.ap.freescale.net>
Message-ID: <50366EEA.2070200@wwwdotorg.org>

On 08/23/2012 12:12 AM, Richard Zhao wrote:
> On Wed, Aug 22, 2012 at 11:21:03PM -0600, Stephen Warren wrote:
>> On 08/22/2012 01:18 AM, Dong Aisheng wrote:
>>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
>>
>>> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
>>
>>> @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
>>>  	rdesc->ops = &anatop_rops;
>>>  	rdesc->type = REGULATOR_VOLTAGE;
>>>  	rdesc->owner = THIS_MODULE;
>>> -	sreg->mfd = anatopmfd;
>>> +
>>> +	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
>>> +	if (!sreg->anatop)
>>> +		return -ENODEV;
>>
>> In fact, that imx_syscon_lookup function I proposed could even do the
>> of_parse_phandle() internally, so perhaps:
>>
>> foo->syscon_dev = imx_syscon_lookup(np, "fsl,anatop", 0);
>> if (IS_ERR(foo->syscon_dev))
>>     return PTR_ERR(foo->syscon_dev);
>>
>> with imx_syscon_lookup() internally knowing when to return EPROBE_DEFER
>> rather than any other permanent error code (e.g. for missing property,
>> bad phandle, etc.)
>
> In some case that we access register in machine code, we don't have any
> phandle. The node is got by find compatible or by path.

That sounds a little odd; why not just use a phandle consistently
everywhere?

Either way though, I could imagine still putting all the lookup code
into the syscon driver; just have different functions for the different
lookup methods:

imx_syscon_lookup_by_phandle(np, char *property_name)
imx_syscon_lookup_by_compatible(char *compatible
imx_syscon_lookup_by_path(char *node_path)


From nico at fluxnic.net  Thu Aug 23 14:02:14 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 23 Aug 2012 14:02:14 -0400 (EDT)
Subject: [PATCH] ARM: decompressor: reset ttbcr for VMSA ARMv7 cores
In-Reply-To: <1345744123-4121-1-git-send-email-will.deacon@arm.com>
References: <1345744123-4121-1-git-send-email-will.deacon@arm.com>
Message-ID: <alpine.LFD.2.02.1208231401460.1754@xanadu.home>

On Thu, 23 Aug 2012, Will Deacon wrote:

> When enabling the MMU for ARMv7 CPUs, the decompressor does not touch
> the ttbcr register, assuming that it will be zeroed (N == 0, EAE == 0).
> Given that only EAE is defined as 0 for non-secure copies of the
> register (and a bootloader such as kexec may leave it set to 1 anyway),
> we should ensure that we reset the register ourselves before turning on
> the MMU.
> 
> This patch zeroes TTBCR.EAE and TTBCR.N prior to enabling the MMU for
> ARMv7 cores in the decompressor, configuring us exclusively for 32-bit
> translation tables via TTBR0.
> 
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Signed-off-by: Matthew Leach <matthew.leach at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/boot/compressed/head.S |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index b8c64b8..81769c1 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
>  #ifdef CONFIG_CPU_ENDIAN_BE8
>  		orr	r0, r0, #1 << 25	@ big-endian page tables
>  #endif
> +		mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
>  		orrne	r0, r0, #1		@ MMU enabled
>  		movne	r1, #0xfffffffd		@ domain 0 = client
> +		bic     r6, r6, #1 << 31        @ 32-bit translation system
> +		bic     r6, r6, #3 << 0         @ use only ttbr0
>  		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
>  		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
> +		mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
>  #endif
>  		mcr	p15, 0, r0, c7, c5, 4	@ ISB
>  		mcr	p15, 0, r0, c1, c0, 0	@ load control register
> -- 
> 1.7.4.1
> 


From nicolas.pitre at linaro.org  Thu Aug 23 14:04:21 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 23 Aug 2012 14:04:21 -0400 (EDT)
Subject: [PATCHv4 4/4] ARM: kprobes: make more tests conditional
In-Reply-To: <201208231209.26707.arnd@arndb.de>
References: <1345645780-2749-1-git-send-email-arnd@arndb.de>
 <201208221841.29645.arnd@arndb.de> <1345679461.3601.20.camel@computer5.home>
 <201208231209.26707.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1208231403440.1754@xanadu.home>

On Thu, 23 Aug 2012, Arnd Bergmann wrote:

> On Wednesday 22 August 2012, Tixy wrote:
> 
> > If you do feel so inclined for a v4 however ;-) you could also make the
> > mls part of the patch tidier by moving the added #endif to instead
> > terminate the preceding "#if __LINUX_ARM_ARCH__ >= 6", i.e.
> > 
> > @@ -367,8 +367,10 @@ void kprobe_arm_test_cases(void)
> >  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
> >  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
> > +#endif
> >  
> > +#if __LINUX_ARM_ARCH__ >= 7
> >  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
> >  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
> >  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> > 
> > 
> > this looks funny in patch form, but the resulting source file is more
> > consistent with other conditional tests.
> 
> Ok, here we go.
> 
> 	Arnd
> 
> 
> commit abfef4db8731591fbb721262bd4712662aaa6d14
> Author: Arnd Bergmann <arnd at arndb.de>
> Date:   Thu Aug 16 07:49:31 2012 +0000
> 
>     ARM: kprobes: make more tests conditional
>     
>     The mls instruction is not available in ARMv6K or below, so we
>     should make the test conditional on at least ARMv7. ldrexd/strexd
>     are available in ARMv6K or ARMv7, which we can test by checking
>     the CONFIG_CPU_32v6K symbol.
>     
>     /tmp/ccuMTZ8D.s: Assembler messages:
>     /tmp/ccuMTZ8D.s:22188: Error: selected processor does not support ARM mode `mls r0,r1,r2,r3'
>     /tmp/ccuMTZ8D.s:22222: Error: selected processor does not support ARM mode `mlshi r7,r8,r9,r10'
>     /tmp/ccuMTZ8D.s:22252: Error: selected processor does not support ARM mode `mls lr,r1,r2,r13'
>     
>     Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>     Cc: Jon Medhurst <tixy at yxit.co.uk>
>     Cc: Russell King <rmk+kernel at arm.linux.org.uk>
>     Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
>     Cc: Leif Lindholm <leif.lindholm at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>


> 
> diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
> index 38c1a3b..8393129 100644
> --- a/arch/arm/kernel/kprobes-test-arm.c
> +++ b/arch/arm/kernel/kprobes-test-arm.c
> @@ -366,7 +366,9 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
>  	TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
>  	TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
> +#endif
>  
> +#if __LINUX_ARM_ARCH__ >= 7
>  	TEST_RRR(  "mls		r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
>  	TEST_RRR(  "mlshi	r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
>  	TEST_RR(   "mls		lr, r",1, VAL2,", r",2, VAL3,", r13")
> @@ -456,6 +458,8 @@ void kprobe_arm_test_cases(void)
>  	TEST_UNSUPPORTED(".word	0xe1700090") /* Unallocated space */
>  #if __LINUX_ARM_ARCH__ >= 6
>  	TEST_UNSUPPORTED("ldrex	r2, [sp]")
> +#endif
> +#if (__LINUX_ARM_ARCH__ >= 7) || defined(CONFIG_CPU_32v6K)
>  	TEST_UNSUPPORTED("strexd	r0, r2, r3, [sp]")
>  	TEST_UNSUPPORTED("ldrexd	r2, r3, [sp]")
>  	TEST_UNSUPPORTED("strexb	r0, r2, [sp]")
> 


From matt at genesi-usa.com  Thu Aug 23 14:04:04 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 23 Aug 2012 13:04:04 -0500
Subject: [PATCH 1/2] imx6q: Configure the pwm node for pinmux support
In-Reply-To: <1345735959-12964-2-git-send-email-hachimi.samir@gmail.com>
References: <1345735959-12964-2-git-send-email-hachimi.samir@gmail.com>
Message-ID: <CAKGA1bk86r_0rZQ20S1Zii7UGuhGFSq5GLzcBpPJfyvoEAPfaA@mail.gmail.com>

On Thu, Aug 23, 2012 at 10:32 AM,  <hachimi.samir at gmail.com> wrote:
> From: Samir Hachimi <hachimi.samir at gmail.com>
>
>  Add the pinmux support for pwm.
>  Several pin can be set to PwmO for the same Pwm. This configuration set all
>  of them when enabled.
>
> Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   42 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 42 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index fd57079..c913b99 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -248,23 +248,35 @@
>                         };
>
>                         pwm at 02080000 { /* PWM1 */
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&pinctrl_pwm1_1>;
>                                 reg = <0x02080000 0x4000>;
>                                 interrupts = <0 83 0x04>;
> +                               status = "disabled";
>                         };
>
>                         pwm at 02084000 { /* PWM2 */
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&pinctrl_pwm2_1>;
>                                 reg = <0x02084000 0x4000>;
>                                 interrupts = <0 84 0x04>;
> +                               status = "disabled";
>                         };
>
>                         pwm at 02088000 { /* PWM3 */
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&pinctrl_pwm3_1>;
>                                 reg = <0x02088000 0x4000>;
>                                 interrupts = <0 85 0x04>;
> +                               status = "disabled";
>                         };
>
>                         pwm at 0208c000 { /* PWM4 */
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&pinctrl_pwm4_1>;
>                                 reg = <0x0208c000 0x4000>;
>                                 interrupts = <0 86 0x04>;
> +                               status = "disabled";
>                         };
>
>                         flexcan at 02090000 { /* CAN1 */
> @@ -559,6 +571,36 @@
>                                         };
>                                 };
>
> +                               pwm1 {
> +                                       pinctrl_pwm1_1: pwm1grp-1 {
> +                                               fsl,pins = <1543 0x80000000     /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
> +                                                           574 0x80000000      /* MX6Q_PAD_DISPO_DAT8__PWM1_PWMO */
> +                                                           971 0x80000000>;    /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
> +                                       };
> +                               };
> +
> +                               pwm2 {
> +                                       pinctrl_pwm2_1: pwm2grp-1 {
> +                                               fsl,pins = <1557 0x80000000     /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
> +                                                           582 0x80000000      /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
> +                                                           963 0x80000000>;    /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
> +                                       };
> +                               };
> +
> +                               pwm3 {
> +                                       pinctrl_pwm3_1: pwm3grp-1 {
> +                                               fsl,pins = <1471 0x80000000     /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
> +                                                           1526 0x80000000>;   /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
> +                                       };
> +                               };
> +
> +                               pwm4 {
> +                                       pinctrl_pwm4_1: pwm4grp-1 {
> +                                               fsl,pins = <1479 0x80000000     /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
> +                                                           1550 0x80000000>;   /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
> +                                       };
> +                               };
> +
>                                 usdhc3 {
>                                         pinctrl_usdhc3_1: usdhc3grp-1 {
>                                                 fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
> --
> 1.7.1

Surely you only specify the pinmux for the pad you want to use, not
every combination.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From tixy at linaro.org  Thu Aug 23 14:31:26 2012
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Thu, 23 Aug 2012 19:31:26 +0100
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <20120823135806.GG24242@S2101-09.ap.freescale.net>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
 <20120823104356.GA13622@mudshark.cambridge.arm.com>
 <20120823135806.GG24242@S2101-09.ap.freescale.net>
Message-ID: <1345746686.4894.7.camel@computer5.home>

On Thu, 2012-08-23 at 21:58 +0800, Shawn Guo wrote:
> On Thu, Aug 23, 2012 at 11:43:56AM +0100, Will Deacon wrote:
> > On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> > > diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> > > index 99afa74..7cc67ce 100644
> > > --- a/arch/arm/include/asm/processor.h
> > > +++ b/arch/arm/include/asm/processor.h
> > > @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
> > >  unsigned long get_wchan(struct task_struct *p);
> > >  
> > >  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> > > -#define cpu_relax()			smp_mb()
> > > +#define cpu_relax()		do {					\
> > > +					asm("nop");			\
> > > +					asm("nop");			\
> > > +					asm("nop");			\
> > > +					asm("nop");			\
> > > +					asm("nop");			\
> > 
> > Can you use nop() instead of the explicit asm?
> 
> Yes.  I just tried, and it works too.
> 
> > Also, I think we should try
> > and use some methodology on deciding the number of nops to insert. Without
> > having a full handle on the problem at the moment, it would seem that we
> > need at least NR_CPUS worth (since the number of spinning secondaries is
> > NR_CPUS-1 and they may execute their barriers in lock-step).
> > 
> I'm not sure we get something like that.  In my testing here, I need
> at least 5 nops to get rid of the issue.

Doesn't A9 do dual issue? If so, the maths for your 4 core iMX6Q might
match up with Will's hypothesis. You could try the theory by building
say with CONFIG_NR_CPUS == 3.

-- 
Tixy 




From thierry.reding at avionic-design.de  Thu Aug 23 15:04:02 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 23 Aug 2012 21:04:02 +0200
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <50366628.5020007@metafoo.de>
References: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>
 <50366464.4070801@metafoo.de> <50366628.5020007@metafoo.de>
Message-ID: <20120823190402.GA8127@avionic-0098.mockup.avionic-design.de>

On Thu, Aug 23, 2012 at 07:19:36PM +0200, Lars-Peter Clausen wrote:
> On 08/23/2012 07:12 PM, Lars-Peter Clausen wrote:
> >[...]
> > Or maybe just use the runtime pm API for this. This probably makes even more
> > sense and grab a reference to the pm context when the enable() is called,
> > release it when disable() is called and also grab it before calling the
> > device's config callback and release it afterward.
> 
> Btw. this seems to be exactly what the pwm-tiecap and pwm-tiehrpwm drivers
> already do today. I'd just make that a core PWM framework feature.

Using runtime PM for this sounds indeed like the most generic approach.
I'm not very familiar with the API, but I thought it required explicit
architecture or bus support (or the driver itself can provide hooks via
pm_ops), so it might be difficult to implement for platforms that don't
have working runtime PM support. I'll have to look into this some more.

Anyway, if we add this kind of support to the PWM core we should take it
through next first. For drivers that are currently broken, they should
be, as you said, fixed by enabling the clock before reconfiguring and
disable it after (unless the PWM is enabled) like Tegra does.

Thierry
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From thierry.reding at avionic-design.de  Thu Aug 23 15:11:08 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 23 Aug 2012 21:11:08 +0200
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <50366464.4070801@metafoo.de>
References: <36966374.2768747.1345741025741.JavaMail.root@advansee.com>
 <50366464.4070801@metafoo.de>
Message-ID: <20120823191108.GB8127@avionic-0098.mockup.avionic-design.de>

On Thu, Aug 23, 2012 at 07:12:04PM +0200, Lars-Peter Clausen wrote:
> On 08/23/2012 06:57 PM, Beno?t Th?baudeau wrote:
> > On Thursday, August 23, 2012 5:43:32 PM, Lars-Peter Clausen wrote:
> >> On 08/23/2012 04:19 PM, Beno?t Th?baudeau wrote:
> >>> Some PWM drivers enable the clock of the PWM peripheral in
> >>> pwm_enable(). Hence,
> >>> for these drivers, a call to pwm_config() does not have any effect
> >>> before
> >>> pwm_enable() has been called.
> >>>
> >>> This patch fixes the PWM users to make sure that they call
> >>> pwm_enable() before
> >>> pwm_config().
> >>>
> >>> This fixes the first setting of brightness through sysfs that had
> >>> no effect with
> >>> leds-pwm and the i.MX PWM driver.
> >>
> >> But isn't this a bug in the PWM peripheral driver? With this change
> >> the PWM
> >> will start with the old settings first. While this is not so much of
> >> a problem
> >> for a backlight (although it might cause a short flickering) it might
> >> cause
> >> problems for other applications, like using the PWM pin as a timing
> >> generator.
> >> In my opinion it's better to fix the PWM peripheral drivers which
> >> have this
> >> problem instead of trying to work around it in every user of the PWM
> >> API.
> > 
> > I don't know. See my detailed description of this issue here:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/115667.html
> > 
> > Where the bug is depends on the detailed definition of the PWM API, which I
> > don't find documented anywhere.
> > 
> > If pwm_enable() means "start PWM timer with the configured settings", then the
> > bug is in the drivers. If it means "enable the PWM peripheral so that we can
> > work with it", then the bug is in the PWM users.
> 
> It really is the former. See the description of pwm_enable() in drivers/pwm/core.c

Yes. pwm_enable() is only for starting the PWM and *not* the peripheral.
I should update the documentation to make this clearer.

> > I don't really have time to work on this, so I suggested this patch as a simple
> > solution. Otherwise, it means reworking several PWM drivers for different
> > hardware that is not available to everyone for testing.
> > 
> > If we decide to only change the i.MX PWM driver, the fix would be:
> > pwm_config()
> > {
> >         save passed config in private data;
> >         if (pwm enabled)
> >                 apply passed config;
> > }
> > 
> > pwm_enable()
> > {
> >         if (!(pwm enabled)) {
> >                 enable pwm ip clk;
> >                 apply config from private data;
> >         }
> > }
> 
> Another option is to enable the clock if it is disabled when the device is
> configured. E.g. that's what tegra does.

Yes, that would have been my proposal as well.

> > If we fix only this driver, we must not forget that the same issue probably
> > exists with several other PWM drivers.
> 
> Since this seems to be a common pattern in a number of PWM drivers it might
> make sense to simply add support for enabling/disabling a clk to the pwm core.
> Or maybe just use the runtime pm API for this. This probably makes even more
> sense and grab a reference to the pm context when the enable() is called,
> release it when disable() is called and also grab it before calling the
> device's config callback and release it afterward.

The problem with adding this kind of support in the core is that the
device or platform doesn't necessarily support runtime PM. Perhaps
adding a flag to mark compatible drivers would be an option. If the
runtime PM API gracefully handles cases where no callbacks are
implemented (and therefore assumed unneeded) things should also work.

On the other hand this really is very driver-specific stuff. A lot of
hardware doesn't require an explicit clock being enabled to write
registers so those wouldn't need the implicit PM calls either.

Thierry
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From sebastian.hesselbarth at gmail.com  Thu Aug 23 16:31:01 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Thu, 23 Aug 2012 22:31:01 +0200
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <50366E44.4030606@wwwdotorg.org>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org>
Message-ID: <50369305.6050304@gmail.com>

On 08/23/2012 07:54 PM, Stephen Warren wrote:
>> dt_parse() and dt_parse_function() build up structs that get used later on
>> in mvebu_pinmux_ops that require indexed functions. I can join them with
>> dt_node_to_map() but that would require incremental kzalloc for the
>> corresponding array. Or I could (functionally) leave dt_parse() to allocate
>> the array and only join dt_parse_function() with dt_node_to_map().
>
> So everything you said makes sense, in that the core driver is
> parameterizable and receives data from a SoC-variant-specific driver
> indicating which pins/groups/functions are available. I'm still not sure
> though why the translation of the pin/group/function structures passed
> to probe into other data structures requires accessing the DT at all;
> the set of available pins/groups/functions isn't configured through DT,
> and doesn't need to be limited to only those options actually used in
> DT, so can't you just process all the data that's passed to probe
> without interaction with the DT?

Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux
core completely. What exactly should mvebu_pinmux_get_funcs_count return
if not the number of DT node children?

I thought that a "function" in the terminology of pinctrl/pinmux core is
a list of pingroups and corresponding values to actually set it to e.g. uart1.
In pinctrl-mvebu this would be one marvell,function assigned to one or more
marvell,pins.

If the above is correct, I still need to access DT in probe() at least to count
the number of children passed to allocate an array for mvebu_pinmux_ops callbacks
that get indexed by "fid" (pctl->functions).

Sebastian


From dgreid at chromium.org  Thu Aug 23 16:51:09 2012
From: dgreid at chromium.org (Dylan Reid)
Date: Thu, 23 Aug 2012 13:51:09 -0700
Subject: [PATCH] ASoC: samsung dma - prepare dma in start/resume trigger path
Message-ID: <1345755069-9512-1-git-send-email-dgreid@chromium.org>

On suspend all dma transactions are terminated (by the stop/suspend
trigger calling ops->stop), they need to be set up again during resume.
Move the prepare op to the start/resume/unpause trigger path so that dma
and audio will restart on resume/unpause.

Signed-off-by: Dylan Reid <dgreid at chromium.org>
---
 sound/soc/samsung/dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index f3ebc38..5772762 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -250,6 +250,7 @@ static int dma_trigger(struct snd_pcm_substream *substream, int cmd)
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_RESUME:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		dma_prepare(substream);
 		prtd->state |= ST_RUNNING;
 		prtd->params->ops->trigger(prtd->params->ch);
 		break;
@@ -352,7 +353,6 @@ static struct snd_pcm_ops dma_ops = {
 	.ioctl		= snd_pcm_lib_ioctl,
 	.hw_params	= dma_hw_params,
 	.hw_free	= dma_hw_free,
-	.prepare	= dma_prepare,
 	.trigger	= dma_trigger,
 	.pointer	= dma_pointer,
 	.mmap		= dma_mmap,
-- 
1.7.7.3



From dgreid at chromium.org  Thu Aug 23 16:54:21 2012
From: dgreid at chromium.org (Dylan Reid)
Date: Thu, 23 Aug 2012 13:54:21 -0700
Subject: [PATCH] ASoC: samsung dma - prepare dma in start/resume trigger
 path
In-Reply-To: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
Message-ID: <CAEUnVG57R87KmO0BMMQ1hwnJ2Gx=g+PxMZH0=2XE7uxUzk84iQ@mail.gmail.com>

On Thu, Aug 23, 2012 at 1:51 PM, Dylan Reid <dgreid at chromium.org> wrote:
> On suspend all dma transactions are terminated (by the stop/suspend
> trigger calling ops->stop), they need to be set up again during resume.
> Move the prepare op to the start/resume/unpause trigger path so that dma
> and audio will restart on resume/unpause.
>
> Signed-off-by: Dylan Reid <dgreid at chromium.org>
> ---
>  sound/soc/samsung/dma.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
> index f3ebc38..5772762 100644
> --- a/sound/soc/samsung/dma.c
> +++ b/sound/soc/samsung/dma.c
> @@ -250,6 +250,7 @@ static int dma_trigger(struct snd_pcm_substream *substream, int cmd)
>         case SNDRV_PCM_TRIGGER_START:
>         case SNDRV_PCM_TRIGGER_RESUME:
>         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> +               dma_prepare(substream);
>                 prtd->state |= ST_RUNNING;
>                 prtd->params->ops->trigger(prtd->params->ch);
>                 break;
> @@ -352,7 +353,6 @@ static struct snd_pcm_ops dma_ops = {
>         .ioctl          = snd_pcm_lib_ioctl,
>         .hw_params      = dma_hw_params,
>         .hw_free        = dma_hw_free,
> -       .prepare        = dma_prepare,
>         .trigger        = dma_trigger,
>         .pointer        = dma_pointer,
>         .mmap           = dma_mmap,
> --
> 1.7.7.3
>


From benoit.thebaudeau at advansee.com  Thu Aug 23 17:03:57 2012
From: benoit.thebaudeau at advansee.com (=?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?=)
Date: Thu, 23 Aug 2012 23:03:57 +0200 (CEST)
Subject: [PATCH] pwm-imx: Fix config / enable / disable
In-Reply-To: <20120823191108.GB8127@avionic-0098.mockup.avionic-design.de>
Message-ID: <1305545087.2775440.1345755837651.JavaMail.root@advansee.com>

imx_pwm_config() did not enable the PWM IP clock while accessing the registers.
Hence, a call to pwm_config() had no effect before pwm_enable() had been called,
which does not comply to the PWM API.

Moreover, calling pwm_disable() then pwm_enable() must be a transparent
operation.

This fixes the first setting of brightness through sysfs that had no effect with
leds-pwm.

Cc: Thierry Reding <thierry.reding at avionic-design.de>
Cc: <linux-kernel at vger.kernel.org>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: <linux-arm-kernel at lists.infradead.org>
Cc: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
---
 .../drivers/pwm/pwm-imx.c                          |   55 +++++++++++++++-----
 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git linux-next-c94456b.orig/drivers/pwm/pwm-imx.c linux-next-c94456b/drivers/pwm/pwm-imx.c
index 2a0b353..0519bf2 100644
--- linux-next-c94456b.orig/drivers/pwm/pwm-imx.c
+++ linux-next-c94456b/drivers/pwm/pwm-imx.c
@@ -55,6 +55,16 @@ static int imx_pwm_config(struct pwm_chip *chip,
 {
 	struct imx_chip *imx = to_imx_chip(chip);
 
+	/*
+	 * If the PWM is disabled, make sure to turn on the clock before
+	 * accessing the registers.
+	 */
+	if (!imx->clk_enabled) {
+		int rc = clk_prepare_enable(imx->clk);
+		if (rc)
+			return rc;
+	}
+
 	if (!(cpu_is_mx1() || cpu_is_mx21())) {
 		unsigned long long c;
 		unsigned long period_cycles, duty_cycles, prescale;
@@ -85,8 +95,11 @@ static int imx_pwm_config(struct pwm_chip *chip,
 		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 
 		cr = MX3_PWMCR_PRESCALER(prescale) |
-			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
+			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN;
+
+		/* If the PWM is enabled, keep it so. */
+		if (imx->clk_enabled)
+			cr |= MX3_PWMCR_EN;
 
 		if (cpu_is_mx25())
 			cr |= MX3_PWMCR_CLKSRC_IPG;
@@ -118,32 +131,50 @@ static int imx_pwm_config(struct pwm_chip *chip,
 		BUG();
 	}
 
+	/* If the PWM is disabled, turn the clock off again to save power. */
+	if (!imx->clk_enabled)
+		clk_disable_unprepare(imx->clk);
+
 	return 0;
 }
 
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
-	int rc = 0;
+	int rc;
 
-	if (!imx->clk_enabled) {
-		rc = clk_prepare_enable(imx->clk);
-		if (!rc)
-			imx->clk_enabled = 1;
+	if (imx->clk_enabled)
+		return 0;
+
+	rc = clk_prepare_enable(imx->clk);
+	if (rc)
+		return rc;
+
+	if (!(cpu_is_mx1() || cpu_is_mx21())) {
+		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
+		cr |= MX3_PWMCR_EN;
+		writel(cr, imx->mmio_base + MX3_PWMCR);
 	}
-	return rc;
+
+	imx->clk_enabled = 1;
+	return 0;
 }
 
 static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
 
-	writel(0, imx->mmio_base + MX3_PWMCR);
+	if (!imx->clk_enabled)
+		return;
 
-	if (imx->clk_enabled) {
-		clk_disable_unprepare(imx->clk);
-		imx->clk_enabled = 0;
+	if (!(cpu_is_mx1() || cpu_is_mx21())) {
+		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
+		cr &= ~MX3_PWMCR_EN;
+		writel(cr, imx->mmio_base + MX3_PWMCR);
 	}
+
+	clk_disable_unprepare(imx->clk);
+	imx->clk_enabled = 0;
 }
 
 static struct pwm_ops imx_pwm_ops = {


From pmeerw at pmeerw.net  Thu Aug 23 17:00:42 2012
From: pmeerw at pmeerw.net (Peter Meerwald)
Date: Thu, 23 Aug 2012 23:00:42 +0200 (CEST)
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
References: <1342485005-5178-1-git-send-email-javier@dowhile0.org>
 <CAMQu2gxaF8K78puE84+=8VJLbsdtdD97ww81XJxG6sCtYTYXww@mail.gmail.com>
 <CABxcv=nsmeVLspzXERYXebmPaNO6rKCsVnak7dMtvGjiYH4vOw@mail.gmail.com>
 <20120718065951.GH6522@atomide.com>
 <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
Message-ID: <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>

On Wed, 18 Jul 2012, Javier Martinez Canillas wrote:

> On Wed, Jul 18, 2012 at 10:36 AM, Shilimkar, Santosh
> <santosh.shilimkar at ti.com> wrote:
> > On Wed, Jul 18, 2012 at 1:14 PM, S, Venkatraman <svenkatr at ti.com> wrote:
> >> On Wed, Jul 18, 2012 at 12:40 PM, Tony Lindgren <tony at atomide.com> wrote:
> >>> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120718 00:09]:
> >>>> On Wed, Jul 18, 2012 at 12:29 PM, Tony Lindgren <tony at atomide.com> wrote:
> >>>> > * Javier Martinez Canillas <javier at dowhile0.org> [120716 23:56]:
> >>>> >> On Tue, Jul 17, 2012 at 8:45 AM, Shilimkar, Santosh
> >>>> >> <santosh.shilimkar at ti.com> wrote:
> >>>> >> > Hi,
> >>>> >> >
> >>>> >> > On Tue, Jul 17, 2012 at 6:00 AM, Javier Martinez Canillas
> >>>> >> > <javier at dowhile0.org> wrote:
> >>>> >> >> The OMAP MMC and OMAP High Speed MMC hosts now use entirely the DMA
> >>>> >> >> engine API instead of the previous private DMA API implementation.
> >>>> >> >>
> >>>> >> >> So, if the kernel is built with support for any of these hosts but it
> >>>> >> >> doesn't support DMA devices nor OMAP DMA support, it fails when trying
> >>>> >> >> to obtain a DMA channel which leads to the following error on an OMAP3
> >>>> >> >> IGEPv2 Rev.C board (and probably on most OMAP boards with MMC support):
> >>>> >> >>
> >>>> >> >> [ 2.199981] omap_hsmmc omap_hsmmc.1: unable to obtain RX DMA engine channel 48
> >>>> >> >> [    2.215087] omap_hsmmc omap_hsmmc.0: unable to obtain RX DMA engine channel 62
> >>>> >> >>
> >>>> >> >> selecting automatically CONFIG_DMADEVICES and CONFIG_DMA_OMAP solves it.
> >>>> >> >>
> >>>> >> >> Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
> >>>> >> >> ---
> >>>> >> > Considering, we are updating drivers to select the DMA engine, can you
> >>>> >> > also include
> >>>> >> > "drivers/spi/spi-omap2-mcspi.c" which is also updated for DMA engine.
> >>>> >> >
> >>>> >> > Regards
> >>>> >> > Santosh
> >>>> >>
> >>>> >> Hi Santosh,
> >>>> >>
> >>>> >> Ok, I'll send a v2 now which includes spi-omap2-mcspi then.
> >>>> >
> >>>> > I don't think we should do this, the drivers should work with and without
> >>>> > dma. This just needs to be added to the omap2plus_defconfig.
> >>>> >
> >>>> Well this was not decided based on any DMA CONFIG option before for
> >>>> the subject drivers. It is already by default enabled if the DMA is supported
> >>>> by the driver IP. There is a possibility to disable it from driver platform/dt
> >>>> data so that still remains.
> >>>
> >>> I think it should rather be that if the driver is broken and does not work
> >>> without DMA, it should have depends on CONFIG_DMA_OMAP.
> >>>
> >> I can confirm that omap MMC can't work without DMA; polled mode is not
> >> supported / implemented.
> >
> > Same case for SPI driver as well. It uses DMA for everything except the cases
> > where DMA doesn't make sense like 1 byte/2 byte etc. And its not configurable,
> >
> > At least considering this, it is better we do this per driver than enabling
> > it at SOC config.
> >
> > Regards
> > Santosh
> > --
> 
> Hi Santosh,
> 
> And what about enabling it at the SoC config level but making the
> drivers dependant on CONFIG_DMADEVICES and CONFIG_DMA_OMAP? If you
> agree I can send something like this in two different patches (one for
> the omap2plus_defconfig and another to make the drivers dependant on
> the config option):
> 
> diff --git a/arch/arm/configs/omap2plus_defconfig
> b/arch/arm/configs/omap2plus_defconfig
> index b152de7..e58edc3 100644
> --- a/arch/arm/configs/omap2plus_defconfig
> +++ b/arch/arm/configs/omap2plus_defconfig
> @@ -193,6 +193,8 @@ CONFIG_MMC_OMAP_HS=y
>  CONFIG_RTC_CLASS=y
>  CONFIG_RTC_DRV_TWL92330=y
>  CONFIG_RTC_DRV_TWL4030=y
> +CONFIG_DMADEVICES=y
> +CONFIG_DMA_OMAP=y
>  CONFIG_EXT2_FS=y
>  CONFIG_EXT3_FS=y
>  # CONFIG_EXT3_FS_XATTR is not set

above has been merged, 89269ef1f0abc72c551198123e19cd4edfd43cf4
but I am missing the patches below in mainline (3.6-rc3) -- what happened?

as Javier pointed out in https://patchwork.kernel.org/patch/1203391/, 
MMC is broken support e.g. on beagleboard unless DMA_OMAP is defined

I suggest to take below patches and help to avoid some extra gray hair for 
people looking for a fix for non-booting beagleboards

thanks, p.

> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index aa131b3..314c7bd 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -231,7 +231,7 @@ config MMC_SDHCI_S3C_DMA
> 
>  config MMC_OMAP
>  	tristate "TI OMAP Multimedia Card Interface support"
> -	depends on ARCH_OMAP
> +	depends on ARCH_OMAP && DMADEVICES && DMA_OMAP
>  	select TPS65010 if MACH_OMAP_H2
>  	help
>  	  This selects the TI OMAP Multimedia card Interface.
> @@ -242,7 +242,8 @@ config MMC_OMAP
> 
>  config MMC_OMAP_HS
>  	tristate "TI OMAP High Speed Multimedia Card Interface support"
> -	depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
> +	depends on (SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4) && \
> +		    DMADEVICES && DMA_OMAP
>  	help
>  	  This selects the TI OMAP High Speed Multimedia card Interface.
>  	  If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index cd2fe35..1c23242 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -237,7 +237,7 @@ config SPI_OMAP_UWIRE
> 
>  config SPI_OMAP24XX
>  	tristate "McSPI driver for OMAP"
> -	depends on ARCH_OMAP2PLUS
> +	depends on ARCH_OMAP2PLUS && DMADEVICES && DMA_OMAP
>  	help
>  	  SPI master controller for OMAP24XX and later Multichannel SPI
>  	  (McSPI) modules.


-- 

Peter Meerwald
+43-664-2444418 (mobile)


From dromede at gmail.com  Thu Aug 23 17:14:15 2012
From: dromede at gmail.com (dromede at gmail.com)
Date: Thu, 23 Aug 2012 23:14:15 +0200
Subject: [PATCH] backlight: corgi_lcd: Fix WARN_ON() when calling
 corgi_bl_set_intensity.
Message-ID: <1345756455-27503-1-git-send-email-dromede@gmail.com>

From: Marko Katic <dromede.gmail.com>


Signed-off-by: Marko Katic <dromede.gmail.com>
---
 drivers/video/backlight/corgi_lcd.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/backlight/corgi_lcd.c b/drivers/video/backlight/corgi_lcd.c
index c781768..8b002d7 100644
--- a/drivers/video/backlight/corgi_lcd.c
+++ b/drivers/video/backlight/corgi_lcd.c
@@ -409,10 +409,10 @@ static int corgi_bl_set_intensity(struct corgi_lcd *lcd, int intensity)
 	cont = !!(intensity & 0x20) ^ lcd->gpio_backlight_cont_inverted;
 
 	if (gpio_is_valid(lcd->gpio_backlight_cont))
-		gpio_set_value(lcd->gpio_backlight_cont, cont);
+		gpio_set_value_cansleep(lcd->gpio_backlight_cont, cont);
 
 	if (gpio_is_valid(lcd->gpio_backlight_on))
-		gpio_set_value(lcd->gpio_backlight_on, intensity);
+		gpio_set_value_cansleep(lcd->gpio_backlight_on, intensity);
 
 	if (lcd->kick_battery)
 		lcd->kick_battery();
-- 
1.7.4.1



From swarren at wwwdotorg.org  Thu Aug 23 17:26:06 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 15:26:06 -0600
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <50369305.6050304@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org> <50369305.6050304@gmail.com>
Message-ID: <50369FEE.8000003@wwwdotorg.org>

On 08/23/2012 02:31 PM, Sebastian Hesselbarth wrote:
> On 08/23/2012 07:54 PM, Stephen Warren wrote:
>>> dt_parse() and dt_parse_function() build up structs that get used
>>> later on
>>> in mvebu_pinmux_ops that require indexed functions. I can join them with
>>> dt_node_to_map() but that would require incremental kzalloc for the
>>> corresponding array. Or I could (functionally) leave dt_parse() to
>>> allocate
>>> the array and only join dt_parse_function() with dt_node_to_map().
>>
>> So everything you said makes sense, in that the core driver is
>> parameterizable and receives data from a SoC-variant-specific driver
>> indicating which pins/groups/functions are available. I'm still not sure
>> though why the translation of the pin/group/function structures passed
>> to probe into other data structures requires accessing the DT at all;
>> the set of available pins/groups/functions isn't configured through DT,
>> and doesn't need to be limited to only those options actually used in
>> DT, so can't you just process all the data that's passed to probe
>> without interaction with the DT?
> 
> Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux
> core completely. What exactly should mvebu_pinmux_get_funcs_count return
> if not the number of DT node children?

In HW, you have:

* A number of pins

* In some cases, multiple pins are controlled by a single register
field, so there are groups of pins, whose pins all get mux'd at once.

* In some cases, SW chooses to control multiple pins at once even if the
HW allows otherwise, and these are also represented as groups.

* A (mux) function represents what options (signals, modules, ...) are
available to be mux'd onto any given pin or group of pins.

If all of your pins/groups can support 4 different mux choices 0..3
(even though the interpretation of values 0..3 may differ per pin/group)
you may simply have functions 0, 1, 2, 3 exposed by your driver.

Alternatively, you may define a function for each logical HW module
(e.g. UART1, UART2, SPI1, SPI2, MMC1...) that exists in your SoC, or
even per each separate subset of signals (e.g. UART1 RX/TX, UART 1
RTS/CTS, UART 2 RX/TX/RTS/CTS, ...).

In a driver where the set of pins, groups, and functions known to the
driver is defined as static data in the driver itself (which I believe
covers your driver; IIRC I saw all those tables in the patch), then
you'd simply count up all the defined function names/IDs available, and
return that from pinmux_ops.get_functions_count(). In this case, the
number of functions is entirely static, being defined by the SoC HW
design, and hence DT content has absolutely no impact on it. For
reference, this is how the Tegra pinctrl drivers work.

In a driver where the set of pins, groups, and functions known to the
driver is not hard-coded into the driver itself, but instead derived
from DT content (which is useful for a driver that works for say 10
different similar SoCs, each with slightly different sets of actual
pins/groups/functions, but where you don't want to hard-code all the
tables into the driver), then you may need to parse DT to extract the
definitions of those pins/groups/functions. Then, there's the question
of how to represent the set of known pins/groups/function in DT; do you
have explicit tables for this, or reverse engineer the tables based on
whichever pins/groups/function just happen to be used by the board
you're running on, in which cases the reverse-engineered lists will
probably not include all options the HW could support, given one
particular DT file. Anyway, as I said, I don't think this approach
applies to your driver anyway since IIRC I did see all the data tables
in the patch.

As you may have guessed, I strongly prefer the hard-coded static table
based approach, or at least separating the definition of known
pins/groups/functions from the configuration nodes that define which
particular mux settings to actually use.

Puting this all a little more simply, the pinctrl core wants to generate
a list of all known functions. It is a single global/unified list. It
first calls pinmux_ops.get_functions_count() to find out how many
functions there are in the list, then pinmux_ops.get_function_name() for
each one to find its name, then pinmux_ops.get_function_groups() to find
out which groups allow that function to be mux'd onto them.


From rob at landley.net  Thu Aug 23 17:29:37 2012
From: rob at landley.net (Rob Landley)
Date: Thu, 23 Aug 2012 16:29:37 -0500
Subject: [PATCHv3 3/9] serial: vt8500: Add devicetree support for
In-Reply-To: <201208220644.18059.arnd@arndb.de>
References: <1345582058-2291-1-git-send-email-linux@prisktech.co.nz>
 <20120821231255.71a7515a@pyramind.ukuu.org.uk>
 <1345617278.7491.4.camel@gitbox> <201208220644.18059.arnd@arndb.de>
Message-ID: <5036A0C1.4030209@landley.net>

On 08/22/2012 01:44 AM, Arnd Bergmann wrote:
> On Wednesday 22 August 2012, Tony Prisk wrote:
>> The original patch was very simple, but I revisited it to fix other
>> issues and forgot to add the relevant comments.
>>
>> Port size is changed to fix a problem - WM8505 actually had 6 uart's
>> defined in platform data but the vt8500_ports variable was only 4.
>>
>> I have added devicetree port id support as well.
> 
> If you do multiple things in one driver, you should normally send multiple
> patches as well, each with a description why that change is done.
> It may seem silly at first to send out a one-line patch next to a 100-line
> patch for the same file, but those cases are actually the ones where it's
> most important.

Think of us poor git-bisect monkeys who have no idea why something broke
but can (purely mechanically) figure out which commit did it. If it's a
patch that does three unrelated things, we're kinda stuck.

Rob
-- 
GNU/Linux isn't: Linux=GPLv2, GNU=GPLv3+, they can't share code.
Either it's "mere aggregation", or a license violation.  Pick one.


From linus.walleij at linaro.org  Thu Aug 23 17:49:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 23 Aug 2012 23:49:50 +0200
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <CACRpkdbSaa6ZOZYB1Cm7WjW0O51kvwsTAxhjefEKd-7XaBB3dw@mail.gmail.com>

On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:

> Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
> driver adopt irqdomain support, so that we can have the mapping
> between gpio and irq number available without using virtual_irq_start
> and MXS_GPIO_IRQ_START.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Linus Walleij <linus.walleij at linaro.org>

OK patch applied, thanks!

Yours,
Linus Walleij


From linux at prisktech.co.nz  Thu Aug 23 17:48:54 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Thu, 23 Aug 2012 21:48:54 +0000
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <201208231322.23077.arnd@arndb.de>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231040.16702.arnd@arndb.de>
 <76F764B079F92A4E843589C893D0A022DAF68C14@SERVER.prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de>
Message-ID: <1345758702.2061.6.camel@gitbox>

On Thu, 2012-08-23 at 13:22 +0000, Arnd Bergmann wrote:
> On Thursday 23 August 2012, Tony Prisk wrote:
> > >On Thursday 23 August 2012, Tony Prisk wrote:
> 
> > 
> > Without the clock patch (9/9), the mach-vt8500 patch (6/9) won't compile
> > due to unresolved symbols.
> > 
> > In arch/arm/mach-vt8500/vt8500.c - you will get an unresolved symbol
> > for 'vtwm_clk_init'
> > 
> > Not sure if this matters, thought I should point it out.
> > Does it need to compile cleanly in your tree (which is what I would assume),
> > or just once its all combined in -next?
> > Does it matter that the usb patches are already in -next?
> > 
> > I don't really understand the requirements around submitting to individual
> > trees and which (if any) of these points are actually issues.
> 
> The rule is that each changeset should be free of regressions compared
> to the version before. So if you have a set of 7 patches in one branch
> that you want me to pick up, the result after applying those 7 patches
> should work, and each previous step should also work. You cannot for
> instance add a call to a function in one patch and then provide that
> function in the following patch.
> 
> There are multiple ways to achieve this:
> 
> * when you have dependencies, get everything merged through one
> maintainer tree, and get Acks for each patch that belongs to another
> maintainer.
> 
> * submit a branch with the patches that other stuff depends on to
> both the subsystem maintainer who is responsible for it and to
> the subsystem maintainer who gets the other patches that are built
> on top of this branch. If you do this, you have to make sure that
> the first branch never gets rebased and that the second branch is
> not sent before the first one is upstream.
> 
> * change the code so that no dependencies exist, e.g. by introducing
> a dummy implementation in one patch and the proper one in another.
> This can generate merge conflicts, but that's usually ok.
> 
> 	Arnd
> 

I was about to say that if Mike has any issues with the driver that I
can fix the patch conflict at the same time, but I just realised that
its more work than I originally thought :)

I was going to move the arch-vt8500 part of the clocks patch back into
the clocks patch - but that will just move the issue from arm-soc to
clocks because Mike's branch won't have the arch-vt8500 patch so the
patch will fail.

If Mike is OK with it once the clocks driver is reviewed, it will be a
lot easier for the whole lot to go in via arm-soc, otherwise I can try
figuring out how to get the arch-vt8500 patch to Mike first, and then
the clocks patch.


Regards
Tony Prisk

From linus.walleij at linaro.org  Thu Aug 23 18:08:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 Aug 2012 00:08:45 +0200
Subject: [PATCH] GPIO: Add support for GPIO on CLPS711X-target platform
In-Reply-To: <1345635383-12224-1-git-send-email-shc_work@mail.ru>
References: <1345635383-12224-1-git-send-email-shc_work@mail.ru>
Message-ID: <CACRpkdZrcBLz+sg-AwWnBD0SA697uWQzocUYnbC1nPYG14LYyA@mail.gmail.com>

On Wed, Aug 22, 2012 at 1:36 PM, Alexander Shiyan <shc_work at mail.ru> wrote:

> The CLPS711X CPUs provide some GPIOs for use in the system. This
> driver provides support for these via gpiolib. Due to platform
> limitations, driver does not support interrupts, only inputs and
> outputs.

OK...

(...)
> +#include <mach/hardware.h>

> +struct clps711x_gpio {
> +       struct gpio_chip        chip[CLPS711X_GPIO_PORTS];
> +       struct mutex            lock;
> +};

That lock is just protecting a few register reads/writes. Use a
spinlock instead, it's more apropriate.

(...)
> +static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
> +{
> +       int ret;
> +       struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
> +
> +       mutex_lock(&gpio->lock);
> +       ret = clps_readb(gpio_clps711x_port_dataaddr(chip)) & (1 << offset);
> +       mutex_unlock(&gpio->lock);
> +
> +       return !!ret;
> +}

Please get rid of this clps_readb() business. I can see it's just this:
#define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))

This makes stuff hard to understand, please pass the virtual base as
a memory resource to the platform device, store it in the state holder
and just use readb() in the driver from that offset.

(...)
> +static int __devinit gpio_clps711x_probe(struct platform_device *pdev)

This should just be __init, you have made it very certain that this
cannot be loaded and unloaded at runtime. (No remove function!)
and its a bool in the Kconfig.

Yours,
Linus Walleij


From sebastian.hesselbarth at gmail.com  Thu Aug 23 19:01:13 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 24 Aug 2012 01:01:13 +0200
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <50369FEE.8000003@wwwdotorg.org>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org> <50369305.6050304@gmail.com>
 <50369FEE.8000003@wwwdotorg.org>
Message-ID: <5036B639.20608@gmail.com>

On 08/23/2012 11:26 PM, Stephen Warren wrote:
> As you may have guessed, I strongly prefer the hard-coded static table
> based approach, or at least separating the definition of known
> pins/groups/functions from the configuration nodes that define which
> particular mux settings to actually use.
>
> Puting this all a little more simply, the pinctrl core wants to generate
> a list of all known functions. It is a single global/unified list. It
> first calls pinmux_ops.get_functions_count() to find out how many
> functions there are in the list, then pinmux_ops.get_function_name() for
> each one to find its name, then pinmux_ops.get_function_groups() to find
> out which groups allow that function to be mux'd onto them.

Ok, now this becomes a little bit more clear to me.

Consider uart1 on dove is muxable to:
mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts),
and finally mpp_uart1(rx and tx).

So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;

Now what we currently do is, use DT to setup all known functions with e.g.
marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1".
This requires to count all pinctrl DT node children to count the known
functions that can ever be muxed to. It will never allow to mux uart1 to sw
flow control during run-time when there was no DT child node for it.

But you are proposing to scan the list passed from SoC specific driver for all
possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up lists
of pingroups that can be used with this specific marvell,function; or even build
up lists of pingroups that allow uart1(rts), and another one for uart1(cts), ...?

Sebastian


From rjw at sisk.pl  Thu Aug 23 19:18:16 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Fri, 24 Aug 2012 01:18:16 +0200
Subject: [GIT PULL] Renesas ARM-based SoC fix for v3.6
Message-ID: <201208240118.16563.rjw@sisk.pl>

Hi,

Please pull from the git repository at

  git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas.git fixes

to receive one fix for the sh73a0 SoC support code as commit
6c0274cbe63ec265f842537825684a619e6cce93

  ARM: shmobile: sh73a0: fixup RELOC_BASE of intca_irq_pins_desc

on top of commit d9875690d9b89a866022ff49e3fcea892345ad92

  Linux 3.6-rc2

It fixes an IRQ configuration issue uncovered by the addition of
preliminary irqdomain support.

Thanks!


 arch/arm/mach-shmobile/intc-sh73a0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

---------------

Kuninori Morimoto (1):
      ARM: shmobile: sh73a0: fixup RELOC_BASE of intca_irq_pins_desc



From swarren at wwwdotorg.org  Thu Aug 23 19:12:43 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 17:12:43 -0600
Subject: [PATCH v3 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1345720529-32315-2-git-send-email-thomas.abraham@linaro.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
 <1345720529-32315-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <5036B8EB.5050502@wwwdotorg.org>

On 08/23/2012 05:15 AM, Thomas Abraham wrote:
> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
> SoC's. This driver provides a common and extensible framework for all
> Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
> driver supports only device tree based instantiation and hence can be
> used only on those Samsung platforms that have device tree enabled.
> 
> This driver is split into two parts: the pinctrl interface and the gpiolib
> interface. The pinctrl interface registers pinctrl devices with the pinctrl
> subsystem and gpiolib interface registers gpio chips with the gpiolib
> subsystem. The information about the pins, pin groups, pin functions and
> gpio chips, which are SoC specific, are parsed from device tree node.

> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

BTW, this is a very nicely written and complete/precise binding
document. Well done.

> +Samsung GPIO and Pin Mux/Config controller
> +
> +Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
> +controller. It controls the input/output settings on the available pads/pins
> +and also provides ability to multiplex and configure the output of various
> +on-chip controllers onto these pads.
> +
> +Required Properties:
> +- compatible: should be one of the following.
> +  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
> +  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
> +
> +- reg: Base address of the pin controller hardware module and length of
> +  the address space it occupies.
> +
> +- interrupts: interrupt specifier for the controller. The format and value of
> +  the interrupt specifier depends on the interrupt parent for the controller.
> +
> +- Pin mux/config groups as child nodes: The pin mux (selecting pin function

Direct child nodes of the pin-controller, not a second level?

While that's quite legal, it means that if you need a particular client
module to use 4 pins, 2 of which need one samsung,pin-function value and
2 of which need a different pin-function value, then the client device's
pinctrl-0 property has to have two entries.

i.e. a completely hypothetical example roughly based on yours below:

	pinctrl_1: pinctrl at 11000000 {
		uart0_rxd: uart0-rxd {
			samsung,pins = "gpa0-0";
			samsung,pin-function = <2>;
			samsung,pin-pud = <0>;
			samsung,pin-drv = <0>;
		};

		uart0_txd: uart0-txd {
			samsung,pins = "gpa0-1";
			samsung,pin-function = <1>;
			samsung,pin-pud = <0>;
			samsung,pin-drv = <0>;
		};
	};

	uart at 13800000 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_rxd &uart0_txd>;
	};

rather than:

	pinctrl_1: pinctrl at 11000000 {
		uart0_opt1: uart0-opt1 {
			uart0_rxd: uart0-rxd {
				samsung,pins = "gpa0-0";
				samsung,pin-function = <2>;
				samsung,pin-pud = <0>;
				samsung,pin-drv = <0>;
			};

			uart0_txd: uart0-txd {
				samsung,pins = "gpa0-1";
				samsung,pin-function = <1>;
				samsung,pin-pud = <0>;
				samsung,pin-drv = <0>;
			};
		};
	};

	uart at 13800000 {
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_opt1;
	};

The latter layout simplifies writing the client nodes, since all the
related settings can be grouped together by whoever writes the pinctrl
node, rather than every client author having to work out all the entries
to include in the list.

That all said, the way you've defined the binding is perfectly
legitimate, and I don't have any kind of issue with it; it's just
something you might want to consider.

Irrespective of whether you choose to keep the binding as-is, or change
it, please consider it:

Acked-by: Stephen Warren <swarren at wwwdotorg.org>

> +  The values specified by these config properties should be dervied from the

s/dervied/derived/

> +External GPIO and Wakeup Interrupts:
> +
> +The controller supports two types of external interrupts over gpio. The first
> +is the external gpio interrupt and second is the external wakeup interrupts.
> +The difference between the two is that the external wakeup interrupts can be
> +used as system wakeup events.
> +
> +A. External GPIO Interrupts: For supporting external gpio interrupts, the
> +   properties should be specified in the pin-controller device node.

s/the properties/the following properties/ ?

> +Aliases:
> +
> +All the pin controller nodes should be represented in the aliases node using
> +the following format 'pinctrl{n}' where n is a unique number for the alias.

There /should/ be an alias, or there /may/ be; I'm not sure why
requiring or recommending an alias would be particularly important for
this device?

I've only had time to review the binding document so far.


From kmpark at infradead.org  Thu Aug 23 20:24:37 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 24 Aug 2012 09:24:37 +0900
Subject: [PATCH v4 1/2] ARM: Make a compile firmware conditionally
Message-ID: <20120824002437.GA17038@july>

From: Kyungmin Park <kyungmin.park at samsung.com>

Some boards can use the firmware at trustzone but others can't use this.
However we need to build it simultaneously. To address this issue,
introduce arm firmware support and use it at each board files.

e.g., In boot_secondary at mach-exynos/platsmp.c

        __raw_writel(virt_to_phys(exynos4_secondary_startup),
                CPU1_BOOT_REG);

        if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
                /* Call Exynos specific smc call */
                firmware_ops->cpu_boot(cpu);
        }

        gic_raise_softirq(cpumask_of(cpu), 1);

        if (pen_release == -1)

Now smp_ops is not yet merged, now just call the firmware_init at init_early
 at board file

e.g., exynos4412 based board

static void __init board_init_early(void)
{
        exynos_firmware_init();
}

TODO
        1. DT support.
        2. call firmware init by smp_ops.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 283fa1d..5b097ca 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -21,6 +21,9 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config ARM_FIRMWARE
+	bool
+
 config ICST
 	bool
 
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..4af6568 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_ARM_GIC)		+= gic.o
 obj-$(CONFIG_ARM_VIC)		+= vic.o
+obj-$(CONFIG_ARM_FIRMWARE)	+= firmware.o
 obj-$(CONFIG_ICST)		+= icst.o
 obj-$(CONFIG_SA1111)		+= sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
diff --git a/arch/arm/common/firmware.c b/arch/arm/common/firmware.c
new file mode 100644
index 0000000..d2c5d37
--- /dev/null
+++ b/arch/arm/common/firmware.c
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+
+#include <asm/firmware.h>
+
+struct firmware_ops *firmware_ops;
+
+static void cpu_boot(int cpu)
+{
+	/* Do nothing */
+}
+
+static struct firmware_ops __firmware_ops = {
+	.do_idle		= cpu_do_idle,
+	.cpu_boot		= cpu_boot,
+};
+
+static int __init firmware_init(void)
+{
+	firmware_ops = __firmware_ops;
+	return 0;
+}
+
+core_initcall(firmware_init);
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
new file mode 100644
index 0000000..8f47cf7
--- /dev/null
+++ b/arch/arm/include/asm/firmware.h
@@ -0,0 +1,20 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_FIRMWARE_H
+#define __ASM_ARM_FIRMWARE_H
+
+struct firmware_ops {
+	int	(*do_idle)(void);
+	void	(*cpu_boot)(int cpu);
+};
+
+extern struct firmware_ops *firmware_ops;
+
+#endif


From kmpark at infradead.org  Thu Aug 23 20:24:45 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 24 Aug 2012 09:24:45 +0900
Subject: [PATCH v4 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
Message-ID: <20120824002445.GA17053@july>

From: Kyungmin Park <kyungmin.park at samsung.com>

Some boards, e.g., exynos4412, can use smc instruction (aka firmware) interally.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024..8ee779c 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)	+= mct.o
 
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
+obj-$(CONFIG_ARM_FIRMWARE)	+= exynos-smc.o firmware.o
+
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
 # machine support
 
 obj-$(CONFIG_MACH_SMDKC210)		+= mach-smdkv310.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index aed2eeb..540918f 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,8 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+void exynos_firmware_init(void);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/exynos-smc.S b/arch/arm/mach-exynos/exynos-smc.S
new file mode 100644
index 0000000..2e27aa3
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-smc.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ *
+ * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+ */
+
+ENTRY(exynos_smc)
+	stmfd	sp!, {r4-r11, lr}
+	dsb
+	smc	#0
+	ldmfd	sp!, {r4-r11, pc}
+ENDPROC(exynos_smc)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
new file mode 100644
index 0000000..a144593
--- /dev/null
+++ b/arch/arm/mach-exynos/firmware.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/firmware.h>
+
+#include "smc.h"
+
+static int exynos_do_idle(void)
+{
+        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        return 0;
+}
+
+static void exynos_cpu_boot(int cpu)
+{
+	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+}
+
+static struct firmware_ops exynos_firmware_ops __initdata = {
+	.do_idle	= exynos_do_idle,
+	.cpu_boot	= exynos_cpu_boot,
+};
+
+int __init exynos_firmware_init(void)
+{
+	firmware_ops = exynos_firmware_ops;
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..25f039d 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -25,6 +25,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include <asm/firmware.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
@@ -139,6 +140,12 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
 			CPU1_BOOT_REG);
+
+		if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
+			/* Call Exynos specific smc call */
+			firmware_ops->cpu_boot(cpu);
+		}
+
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
new file mode 100644
index 0000000..e972390
--- /dev/null
+++ b/arch/arm/mach-exynos/smc.h
@@ -0,0 +1,31 @@
+/*
+ *  Copyright (c) 2012 Samsung Electronics.
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SMC_H
+#define __ASM_ARCH_EXYNOS_SMC_H
+
+#define SMC_CMD_INIT            (-1)
+#define SMC_CMD_INFO            (-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP           (-3)
+#define SMC_CMD_CPU1BOOT        (-4)
+#define SMC_CMD_CPU0AFTR        (-5)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME       (-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL        (-21)
+#define SMC_CMD_L2X0SETUP1      (-22)
+#define SMC_CMD_L2X0SETUP2      (-23)
+#define SMC_CMD_L2X0INVALL      (-24)
+#define SMC_CMD_L2X0DEBUG       (-25)
+
+extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+
+#endif


From johnhlinn at gmail.com  Thu Aug 23 20:58:50 2012
From: johnhlinn at gmail.com (John Linn)
Date: Thu, 23 Aug 2012 17:58:50 -0700
Subject: Cortex A9 with ACP needing mixed coherency model
Message-ID: <CAB9O=CPx2PKjyWiKa6B+MJnO0G=805Gb_rnjULb+xw1YOZjCyQ@mail.gmail.com>

It doesn't look like there's any good way to have a mixed coherency
model to support using the ACP where there is coherency and using
other ports where there is not coherency.
ARM Linux kernel can support arch_is_coherent(), which means all DMA
I/O is coherent. We have multiple DMA engines and they can go to thru
coherent or non-coherent ports.

Am I missing something, or has someone figured out a way to deal with this?

Thanks,
John


From shawn.guo at linaro.org  Thu Aug 23 21:09:07 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 09:09:07 +0800
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <CACRpkdbSaa6ZOZYB1Cm7WjW0O51kvwsTAxhjefEKd-7XaBB3dw@mail.gmail.com>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
 <CACRpkdbSaa6ZOZYB1Cm7WjW0O51kvwsTAxhjefEKd-7XaBB3dw@mail.gmail.com>
Message-ID: <20120824010904.GN24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 11:49:50PM +0200, Linus Walleij wrote:
> On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
> 
> > Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
> > driver adopt irqdomain support, so that we can have the mapping
> > between gpio and irq number available without using virtual_irq_start
> > and MXS_GPIO_IRQ_START.
> >
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Linus Walleij <linus.walleij at linaro.org>
> 
> OK patch applied, thanks!
> 
I was planning to have the patch to go via arm-soc tree with your ACK.
But it also works to have it on gpio tree and I ask arm-soc people to
pull gpio tree into arm-soc, but you need to ensure the branch is
stable (no rebase).

-- 
Regards,
Shawn


From jason77.wang at gmail.com  Thu Aug 23 21:10:43 2012
From: jason77.wang at gmail.com (Hui Wang)
Date: Fri, 24 Aug 2012 09:10:43 +0800
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <20120823104356.GA13622@mudshark.cambridge.arm.com>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
 <20120823104356.GA13622@mudshark.cambridge.arm.com>
Message-ID: <5036D493.7050204@gmail.com>

Will Deacon wrote:
> On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
>   
>> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
>> index 99afa74..7cc67ce 100644
>> --- a/arch/arm/include/asm/processor.h
>> +++ b/arch/arm/include/asm/processor.h
>> @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
>>  unsigned long get_wchan(struct task_struct *p);
>>  
>>  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
>> -#define cpu_relax()			smp_mb()
>> +#define cpu_relax()		do {					\
>> +					asm("nop");			\
>> +					asm("nop");			\
>> +					asm("nop");			\
>> +					asm("nop");			\
>> +					asm("nop");			\
>>     
>
> Can you use nop() instead of the explicit asm? Also, I think we should try
> and use some methodology on deciding the number of nops to insert. Without
> having a full handle on the problem at the moment, it would seem that we
> need at least NR_CPUS worth (since the number of spinning secondaries is
> NR_CPUS-1 and they may execute their barriers in lock-step).
>   
Your concern sounds reasonable, but i did a test, the result show there 
is no explicit relation between NR_CPUS and the number of nop needed.

NR_CPUS = 4 and NR_CPUS = 2 need at least the same number of nop.


Regards,
Hui.

> Will
>
>   



From shawn.guo at linaro.org  Thu Aug 23 21:15:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 09:15:59 +0800
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <1345746686.4894.7.camel@computer5.home>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
 <20120823104356.GA13622@mudshark.cambridge.arm.com>
 <20120823135806.GG24242@S2101-09.ap.freescale.net>
 <1345746686.4894.7.camel@computer5.home>
Message-ID: <20120824011557.GO24242@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 07:31:26PM +0100, Jon Medhurst (Tixy) wrote:
> On Thu, 2012-08-23 at 21:58 +0800, Shawn Guo wrote:
> > On Thu, Aug 23, 2012 at 11:43:56AM +0100, Will Deacon wrote:
> > > On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> > > > diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> > > > index 99afa74..7cc67ce 100644
> > > > --- a/arch/arm/include/asm/processor.h
> > > > +++ b/arch/arm/include/asm/processor.h
> > > > @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
> > > >  unsigned long get_wchan(struct task_struct *p);
> > > >  
> > > >  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> > > > -#define cpu_relax()			smp_mb()
> > > > +#define cpu_relax()		do {					\
> > > > +					asm("nop");			\
> > > > +					asm("nop");			\
> > > > +					asm("nop");			\
> > > > +					asm("nop");			\
> > > > +					asm("nop");			\
> > > 
> > > Can you use nop() instead of the explicit asm?
> > 
> > Yes.  I just tried, and it works too.
> > 
> > > Also, I think we should try
> > > and use some methodology on deciding the number of nops to insert. Without
> > > having a full handle on the problem at the moment, it would seem that we
> > > need at least NR_CPUS worth (since the number of spinning secondaries is
> > > NR_CPUS-1 and they may execute their barriers in lock-step).
> > > 
> > I'm not sure we get something like that.  In my testing here, I need
> > at least 5 nops to get rid of the issue.
> 
> Doesn't A9 do dual issue?

Do you have some details about the issue to share?

> If so, the maths for your 4 core iMX6Q might
> match up with Will's hypothesis. You could try the theory by building
> say with CONFIG_NR_CPUS == 3.
> 
I'm still not quite sure about the hypothesis, but I assume you are
asking if 3 NOPs will fix the issue.  If so, the answer is NO.
I increase the number of NOP incrementally starting from 1, and the
issue remains until we have 5 NOPs in there.

-- 
Regards,
Shawn


From josephl at nvidia.com  Thu Aug 23 21:40:33 2012
From: josephl at nvidia.com (Joseph Lo)
Date: Fri, 24 Aug 2012 09:40:33 +0800
Subject: [PATCH] mmc: tegra: convert to device tree support only
In-Reply-To: <502E950B.2010205@wwwdotorg.org>
References: <1345187071-6619-1-git-send-email-josephl@nvidia.com>
 <502E950B.2010205@wwwdotorg.org>
Message-ID: <1345772433.5081.1.camel@jlo-ubuntu-64.nvidia.com>

On Sat, 2012-08-18 at 03:01 +0800, Stephen Warren wrote:
> On 08/17/2012 01:04 AM, Joseph Lo wrote:
> > When compiling a kernel that supports only Tegra30 and not Tegra20,
> > the SDHCI driver will fail to compile since the of_match_device() failure
> > fallback code unconditinally references soc_data_tegra20, which is only
> > compiled in when Tegra20 support is enabled.
> > 
> > In Kernel 3.7, both Tegra20 and Tegra30 will only support booting using
> > device tree, Hence, there is never a need to fall back to using
> > soc_data_tegra20 if of_mach_device() fails. Instead, make this case an
> > error. This removes the reference to soc_data_tegra20, and hence solves
> > the compile failure.
> 
> Tested-by: Stephen Warren <swarren at wwwdotorg.org>
> 
> (built and tested both Tegra20-only and Tegr30-only kernels with this
> applied on top of next-20120816).

Ping.

Could anyone help to review this?
Thanks.




From mturquette at ti.com  Thu Aug 23 22:31:35 2012
From: mturquette at ti.com (Mike Turquette)
Date: Thu, 23 Aug 2012 19:31:35 -0700
Subject: [PATCH 1/1] clk: add DT support for clock gating control
In-Reply-To: <1341767726-25630-1-git-send-email-sebastian.hesselbarth@googlemail.com>
References: <1341767726-25630-1-git-send-email-sebastian.hesselbarth@googlemail.com>
Message-ID: <20120824023135.4547.2534@nucleus>

Quoting Sebastian Hesselbarth (2012-07-08 10:15:26)
> This patch adds support for using clock gates (clk-gate) from DT based
> on Rob Herrings DT clk binding support for 3.6.
> 
> It adds a helper function to clk-gate to allocate all resources required by
> a set of individual clock gates, i.e. register base address and lock. Each
> clock gate is described as a child of the clock-gating-control in DT and
> also created by the helper function.
> 

Hi Sebastian,

Thanks for submitting this.  I'd prefer for Rob or someone with a more vested
interest in DT to review your binding.  I have some comments on the code below.

<snip>
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index 578465e..1e88907 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -15,6 +15,9 @@
>  #include <linux/io.h>
>  #include <linux/err.h>
>  #include <linux/string.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
>  
>  /**
>   * DOC: basic gatable clock which can gate and ungate it's ouput
> @@ -148,3 +151,84 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
>  
>         return clk;
>  }
> +
> +#ifdef CONFIG_OF
> +/**
> + * of_clock_gating_control_setup() - Setup function for clock gate control
> + *   This is a helper for using clk-gate from OF device tree. It allocates
> + *   a common lock for a base register and creates the individual clk-gates.
> + */
> +void __init of_clock_gating_control_setup(struct device_node *np)
> +{
> +       struct device_node *child;
> +       const char *pclk_name;
> +       void __iomem *base;
> +       spinlock_t *lockp;
> +       unsigned int rnum;
> +       u64 addr;
> +
> +       pclk_name = of_clk_get_parent_name(np, 0);
> +       if (!pclk_name) {
> +               pr_debug("%s: unable to get parent clock for %s\n",
> +                       __func__, np->full_name);
> +               return;
> +       }
> +
> +       lockp = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
> +       if (!lockp) {
> +               pr_debug("%s: unable to allocate spinlock for %s\n",
> +                        __func__, np->full_name);
> +               return;
> +       }
> +
> +       spin_lock_init(lockp);

The spinlocks for the basic clock types have always been optional.  This
code should reflect that and not assume the spinlock.

Also I wonder if the assumption is true that a single spinlock
corresponding to a device_node is always the right thing for every
platform.  What about a 32-bit register that contains some gating bits
and a 3-bit wide field for a mux which we perform read-modify-write
operations on?

You'll have to pardon my DT ignorance.  My concerns above may be totally
crazy with respect to DT.

> +       base = of_iomap(np, 0);
> +       rnum = sizeof(resource_size_t) * 8;
> +       addr = of_translate_address(np, of_get_property(np, "reg", NULL));
> +
> +       pr_debug("create clock gate control %s\n", np->full_name);

There are some inconsistent prints here.  How about leading this trace
with a __func__ like you do below for the error messages?

> +
> +       for_each_child_of_node(np, child) {
> +               struct clk *cg;
> +               const char *cg_name;
> +               const char *cg_pclk_name;
> +               u32 propval[2];
> +               unsigned int rbit;
> +
> +               if (of_property_read_u32_array(child, "reg", propval, 2)) {
> +                       pr_debug("%s: wrong #reg on %s\n",
> +                                __func__, child->full_name);
> +                       continue;
> +               }
> +
> +               rbit = propval[0];
> +               if (rbit >= rnum) {
> +                       pr_debug("%s: bit position of %s exceeds resources\n",
> +                                __func__, child->full_name);
> +                       continue;
> +               }
> +
> +               cg_pclk_name = of_clk_get_parent_name(child, 0);
> +               if (!pclk_name)
> +                       cg_pclk_name = pclk_name;

!pclk_name would have caused an early return above, so this conditional
will never evaluate as true.  Even if it did, I'm not sure I follow the
logic.  Why set cg_pclk_name to NULL if pclk_name is NULL?

> +
> +               if (of_property_read_string(child, "clock-output-names",
> +                                           &cg_name)) {
> +                       unsigned int nlen = 4 + 16 + strlen(child->name);
> +                       char *name = kzalloc(nlen+1, GFP_KERNEL);
> +                       if (!name)
> +                               continue;
> +                       snprintf(name, nlen, "%u@%llx.%s", rbit,
> +                                (unsigned long long)addr, child->name);
> +                       cg_name = name;
> +               }
> +
> +               pr_debug("  create clock gate: %s\n", cg_name);

Extra whitespace typo?  Again, would be nice to lead this trace with a
__func__ string.

> +
> +               cg = clk_register_gate(NULL, cg_name, cg_pclk_name, 0,
> +                                      base, rbit, propval[1], lockp);
> +               if (cg)
> +                       of_clk_add_provider(child, of_clk_src_simple_get, cg);

Need to check if clk_register_gate fails and do memory leak cleanup of
name and maybe lockp for the corner case where none of the clock
registration operations succeed.

Regards,
Mike


From marex at denx.de  Thu Aug 23 22:33:44 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 04:33:44 +0200
Subject: [PATCH V2] mxs/spi: Fix misuse of init_completion
Message-ID: <1345775624-9696-1-git-send-email-marex@denx.de>

The init_completion() call does reinit not only the variable carrying
the flag that the completion finished, but also initialized the
waitqueue associated with the completion. On the contrary, the
INIT_WAITQUEUE() call only reinits the flag.

In case there was anything still stuck in the waitqueue, subsequent call
to init_completion() would be able to create possible race condition. This
patch uses the proper function and moves init_completion() into .probe() call
of the driver, to be issued only once.

Note that such scenario is impossible, since two threads can never enter the
mxs_spi_txrx_dma(), since whole this section is protected by mutex in SPI core.
This by no means allows this issue to exit though.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/spi/spi-mxs.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

V2: Update the patch description and snap a whip over myself for being lazy to
    write one in the first place!

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 331f600..c965cc6 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -230,7 +230,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 		return -EINVAL;
 	}
 
-	init_completion(&spi->c);
+	INIT_COMPLETION(spi->c);
 
 	if (*first)
 		pio |= BM_SSP_CTRL0_LOCK_CS;
@@ -560,6 +560,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ssp->devid = devid;
 	ssp->dma_channel = dma_channel;
 
+	init_completion(&spi->c);
+
 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 			       DRIVER_NAME, ssp);
 	if (ret)
-- 
1.7.10.4



From marex at denx.de  Thu Aug 23 22:34:18 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 04:34:18 +0200
Subject: [PATCH] mxs/spi: Restart the block after unsuccessful transfer
Message-ID: <1345775658-9739-1-git-send-email-marex@denx.de>

Restart the SSP block in case the SSP transfer failed in any way.
The block hung in some cases otherwise.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/spi/spi-mxs.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 746359e..8075683 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -445,8 +445,10 @@ static int mxs_spi_transfer_one(struct spi_master *master,
 		}
 
 		m->actual_length += t->len;
-		if (status)
+		if (status) {
+			stmp_reset_block(ssp->base);
 			break;
+		}
 
 		first = last = 0;
 	}
-- 
1.7.10.4



From marex at denx.de  Thu Aug 23 22:42:41 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 04:42:41 +0200
Subject: [PATCH] mxs/spi: Add SPI slave mode operation DT prop
Message-ID: <1345776161-9778-1-git-send-email-marex@denx.de>

This allows user to select the slave mode of operation of the controller.
This is by no means standard, see the binding documentation for details,
there is plenty of them. Sadly, such knowledge is not provided in the chip
documentation. Hopefully, this mode of operation might come useful for
people who do know very well what they are doing, otherwise this should
never be touched.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 Documentation/devicetree/bindings/spi/mxs-spi.txt |   16 +++++++++++++
 drivers/spi/spi-mxs.c                             |   25 +++++++++++++--------
 include/linux/spi/mxs-spi.h                       |    1 +
 3 files changed, 33 insertions(+), 9 deletions(-)

NOTE1: I think I'll be crucified for bringing this up ;-)
NOTE2: I wonder if bringing such option in is good idea, but I hope it is.
       This thing seems to be useful at least to some people.
NOTE3: This at least documents the actual way of how to use the SPI slave mode
       on the MX28. The documentation for MX28 provided by Freescale is severely
       lacking in this matter. Some information (CPOL and CPHA note) were
       therefore retrieved from STMP36xx manual, which seems to have similar SSP
       IP core. The rest of the information (that the clock must run at much
       higher speed) was retrieved by performing long going slave work.
       Freescale only immersed themself in management shenanigans and were in
       the end not helpful at all. I hope someone will find the supplied
       information useful, even if this patch was only to be archived in the
       kernel list archives.

diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt
index e2e1395..16c7287 100644
--- a/Documentation/devicetree/bindings/spi/mxs-spi.txt
+++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt
@@ -9,6 +9,22 @@ Required properties:
 Optional properties:
 - clock-frequency : Input clock frequency to the SPI block in Hz.
 		    Default is 160000000 Hz.
+- fsl,slave-mode : Enable the slave mode operation of the controller.
+		   USE THIS OPTION WITH UTMOST CAUTION, READ ON FOR DETAILS!
+		   The i.MX23/i.MX28 controller can do SPI slave mode and
+		   behaves very closely as it does in master mode, but:
+		   - This is by no mean standard mode of operation, please
+		     use only if you do know what you're doing.
+		   - If the SPI master generates clock at n MHz, the speed
+		     of the SPI slave controller must be at least 4-8 times
+		     faster, this is due to the controller samples the CLK
+		     line multiple times in one clock pulse to be able to
+		     reliably deploy data. Otherwise, no data are received
+		     at all. Successful test was done with:
+		     - Master controller @ 120MHz, master device @ 30MHz
+		     - Slave controller @ 240MHz, slave device @ 120MHz
+		   - The CPOL and CPHA bits must be set.
+		   - The DMA has to wait indefinitelly for the arriving data.
 
 Example:
 
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index c965cc6..746359e 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -61,6 +61,7 @@
 struct mxs_spi {
 	struct mxs_ssp		ssp;
 	struct completion	c;
+	bool			slave_mode;
 };
 
 static int mxs_spi_setup_transfer(struct spi_device *dev,
@@ -95,7 +96,8 @@ static int mxs_spi_setup_transfer(struct spi_device *dev,
 		     BF_SSP_CTRL1_WORD_LENGTH
 		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
 		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
-		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
+		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) |
+		     (spi->slave_mode ? BM_SSP_CTRL1_SLAVE_MODE : 0),
 		     ssp->base + HW_SSP_CTRL1(ssp));
 
 	writel(0x0, ssp->base + HW_SSP_CMD0);
@@ -287,16 +289,20 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 	dmaengine_submit(desc);
 	dma_async_issue_pending(ssp->dmach);
 
-	ret = wait_for_completion_timeout(&spi->c,
+	if (spi->slave_mode)
+		ret = wait_for_completion_killable(&spi->c);
+	else {
+		ret = wait_for_completion_timeout(&spi->c,
 				msecs_to_jiffies(SSP_TIMEOUT));
 
-	if (!ret) {
-		dev_err(ssp->dev, "DMA transfer timeout\n");
-		ret = -ETIMEDOUT;
-		goto err;
-	}
+		if (!ret) {
+			dev_err(ssp->dev, "DMA transfer timeout\n");
+			ret = -ETIMEDOUT;
+			goto err;
+		}
 
-	ret = 0;
+		ret = 0;
+	}
 
 err:
 	for (--sg_count; sg_count >= 0; sg_count--) {
@@ -410,7 +416,7 @@ static int mxs_spi_transfer_one(struct spi_master *master,
 		 * DMA only: 2.164808 seconds, 473.0KB/s
 		 * Combined: 1.676276 seconds, 610.9KB/s
 		 */
-		if (t->len <= 256) {
+		if ((t->len <= 256) && !spi->slave_mode) {
 			writel(BM_SSP_CTRL1_DMA_ENABLE,
 				ssp->base + HW_SSP_CTRL1(ssp) +
 				STMP_OFFSET_REG_CLR);
@@ -561,6 +567,7 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ssp->dma_channel = dma_channel;
 
 	init_completion(&spi->c);
+	spi->slave_mode = of_property_read_bool(np, "fsl,slave-mode");
 
 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 			       DRIVER_NAME, ssp);
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
index 61ae130..6c6ae34 100644
--- a/include/linux/spi/mxs-spi.h
+++ b/include/linux/spi/mxs-spi.h
@@ -94,6 +94,7 @@
 #define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
 #define  BM_SSP_CTRL1_PHASE			(1 << 10)
 #define  BM_SSP_CTRL1_POLARITY			(1 << 9)
+#define  BM_SSP_CTRL1_SLAVE_MODE		(1 << 8)
 #define  BP_SSP_CTRL1_WORD_LENGTH		4
 #define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
 #define  BF_SSP_CTRL1_WORD_LENGTH(v)		\
-- 
1.7.10.4



From cjb at laptop.org  Thu Aug 23 22:44:17 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 23 Aug 2012 22:44:17 -0400
Subject: [PATCH V2] mxs/spi: Fix misuse of init_completion
In-Reply-To: <1345775624-9696-1-git-send-email-marex@denx.de> (Marek Vasut's
 message of "Fri, 24 Aug 2012 04:33:44 +0200")
References: <1345775624-9696-1-git-send-email-marex@denx.de>
Message-ID: <87393dt3em.fsf@octavius.laptop.org>

Hi Marek,

On Thu, Aug 23 2012, Marek Vasut wrote:
> The init_completion() call does reinit not only the variable carrying
> the flag that the completion finished, but also initialized the
> waitqueue associated with the completion. On the contrary, the
> INIT_WAITQUEUE() call only reinits the flag.
>
> In case there was anything still stuck in the waitqueue, subsequent call
> to init_completion() would be able to create possible race condition. This
> patch uses the proper function and moves init_completion() into .probe() call
> of the driver, to be issued only once.
>
> Note that such scenario is impossible, since two threads can never enter the
> mxs_spi_txrx_dma(), since whole this section is protected by mutex in SPI core.
> This by no means allows this issue to exit though.
>
> Signed-off-by: Marek Vasut <marex at denx.de>

Thanks for writing that up -- I appreciate seeing the explanation of the
problems this could have caused.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From b29396 at freescale.com  Thu Aug 23 22:28:09 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 24 Aug 2012 10:28:09 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <20120823110647.GU7995@opensource.wolfsonmicro.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
 <20120822160241.GR7995@opensource.wolfsonmicro.com>
 <20120823072629.GG10057@shlinux2.ap.freescale.net>
 <20120823110647.GU7995@opensource.wolfsonmicro.com>
Message-ID: <20120824022807.GA5822@shlinux2.ap.freescale.net>

On Thu, Aug 23, 2012 at 07:06:47PM +0800, Mark Brown wrote:
> On Thu, Aug 23, 2012 at 03:26:30PM +0800, Dong Aisheng wrote:
> > On Thu, Aug 23, 2012 at 12:02:41AM +0800, Mark Brown wrote:
> 
> > > It'd be good to provide a way of retrieving the regmap so that drivers
> > > for subsystems with generic regmap code could use the framework features
> > > (regulator is one example that I just mentioned in my other mail).
> 
> > Do you mean something like:
> > regmap = syscon_regmap_dev_lookup(np, "fsl,anatop");
> > regmap_write(regmap, reg, val);
> 
> > Then drivers can use generic regmap framework features rather than depend
> > on what imx-syscon implemented, is that correct?
> 
> Yes, this is mainly for cases where the subsystem has helper functions
> that can work with regmap.

Okay, then imx-syscon only implements regmap register mechanism and regmap
lookup mechanism, for accessors, client driver can directly use the generic
regmap API defined in include/linux/regmap.h.

Then it looks to me the driver is more like a generic feature which may also be
needed for other SoCs, IIRC, Tegra ahb and ux500 PRCMU,

Do you think if we should implement it in a more generic way at first?
e.g, drop 'imx-' prefix first.

Linus,
You're the first guy to raise the idea that we could implement a syscon
framework to generic register access, what's your comment on this?

Regards
Dong Aisheng



From b29396 at freescale.com  Thu Aug 23 22:29:47 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 24 Aug 2012 10:29:47 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <20120823111741.GX7995@opensource.wolfsonmicro.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <20120822155953.GQ7995@opensource.wolfsonmicro.com>
 <20120823071503.GF10057@shlinux2.ap.freescale.net>
 <20120823111741.GX7995@opensource.wolfsonmicro.com>
Message-ID: <20120824022946.GB5822@shlinux2.ap.freescale.net>

On Thu, Aug 23, 2012 at 07:17:41PM +0800, Mark Brown wrote:
> On Thu, Aug 23, 2012 at 03:15:04PM +0800, Dong Aisheng wrote:
> > On Wed, Aug 22, 2012 at 11:59:53PM +0800, Mark Brown wrote:
> 
> > > With the conversion to regmap it'd also be good to convert the driver to
> > > use the regmap helper functions for enable and voltage operations if
> > > possible.
> 
> > The anatop-regulator driver only implements set_voltage_sel/get_voltage_sel
> > which i have already converted, what do you mean others like
> > 'for enable and voltage operations' i should also convert?
> 
> Those operations should ideally be converted to use the generic regmap
> implementation now the device uses regmap - regmap_get_voltage_sel_regmap
> and so on.

Okay, got it.

Regards
Dong Aisheng



From marek.vasut at gmail.com  Thu Aug 23 22:54:40 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 24 Aug 2012 04:54:40 +0200
Subject: [PATCH V2] mxs/spi: Fix misuse of init_completion
In-Reply-To: <87393dt3em.fsf@octavius.laptop.org>
References: <1345775624-9696-1-git-send-email-marex@denx.de>
 <87393dt3em.fsf@octavius.laptop.org>
Message-ID: <201208240454.40561.marex@denx.de>

Dear Chris Ball,

> Hi Marek,
> 
> On Thu, Aug 23 2012, Marek Vasut wrote:
> > The init_completion() call does reinit not only the variable carrying
> > the flag that the completion finished, but also initialized the
> > waitqueue associated with the completion. On the contrary, the
> > INIT_WAITQUEUE() call only reinits the flag.

Darn, it's INIT_COMPLETION() of course.

> > In case there was anything still stuck in the waitqueue, subsequent call
> > to init_completion() would be able to create possible race condition.
> > This patch uses the proper function and moves init_completion() into
> > .probe() call of the driver, to be issued only once.
> > 
> > Note that such scenario is impossible, since two threads can never enter
> > the mxs_spi_txrx_dma(), since whole this section is protected by mutex
> > in SPI core. This by no means allows this issue to exit though.
> > 
> > Signed-off-by: Marek Vasut <marex at denx.de>
> 
> Thanks for writing that up -- I appreciate seeing the explanation of the
> problems this could have caused.

You're very welcome, I was really lazy, sorry about that and thanks for pushing 
me ;-) I hope someone might eventually even find this explanation useful.

> - Chris.

Best regards,
Marek Vasut


From marex at denx.de  Thu Aug 23 22:56:27 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 04:56:27 +0200
Subject: [PATCH V3] mxs/spi: Fix misuse of init_completion
Message-ID: <1345776987-15350-1-git-send-email-marex@denx.de>

The init_completion() call does reinit not only the variable carrying
the flag that the completion finished, but also initialized the
waitqueue associated with the completion. On the contrary, the
INIT_COMPLETION() call only reinits the flag.

In case there was anything still stuck in the waitqueue, subsequent call
to init_completion() would be able to create possible race condition. This
patch uses the proper function and moves init_completion() into .probe() call
of the driver, to be issued only once.

Note that such scenario is impossible, since two threads can never enter the
mxs_spi_txrx_dma(), since whole this section is protected by mutex in SPI core.
This by no means allows this issue to exit though.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/spi/spi-mxs.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

V2: Update the patch description and snap a whip over myself for being lazy to
    write one in the first place!
V3: Replace INIT_WORKQUEUE() with INIT_COMPLETION(), typo in patch description.

diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 331f600..c965cc6 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -230,7 +230,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 		return -EINVAL;
 	}
 
-	init_completion(&spi->c);
+	INIT_COMPLETION(spi->c);
 
 	if (*first)
 		pio |= BM_SSP_CTRL0_LOCK_CS;
@@ -560,6 +560,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
 	ssp->devid = devid;
 	ssp->dma_channel = dma_channel;
 
+	init_completion(&spi->c);
+
 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 			       DRIVER_NAME, ssp);
 	if (ret)
-- 
1.7.10.4



From b29396 at freescale.com  Thu Aug 23 22:37:50 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 24 Aug 2012 10:37:50 +0800
Subject: [PATCH 4/7] regulator: anatop-regulator: convert to use
 imx-syscon to access anatop register
In-Reply-To: <50366EEA.2070200@wwwdotorg.org>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-5-git-send-email-b29396@freescale.com>
 <5035BDBF.9020602@wwwdotorg.org>
 <20120823061202.GM4011@b20223-02.ap.freescale.net>
 <50366EEA.2070200@wwwdotorg.org>
Message-ID: <20120824023749.GC5822@shlinux2.ap.freescale.net>

On Fri, Aug 24, 2012 at 01:56:58AM +0800, Stephen Warren wrote:
> On 08/23/2012 12:12 AM, Richard Zhao wrote:
> > On Wed, Aug 22, 2012 at 11:21:03PM -0600, Stephen Warren wrote:
> >> On 08/22/2012 01:18 AM, Dong Aisheng wrote:
> >>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> >>
> >>> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> >>
> >>> @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
> >>>  	rdesc->ops = &anatop_rops;
> >>>  	rdesc->type = REGULATOR_VOLTAGE;
> >>>  	rdesc->owner = THIS_MODULE;
> >>> -	sreg->mfd = anatopmfd;
> >>> +
> >>> +	sreg->anatop = of_parse_phandle(np, "fsl,anatop", 0);
> >>> +	if (!sreg->anatop)
> >>> +		return -ENODEV;
> >>
> >> In fact, that imx_syscon_lookup function I proposed could even do the
> >> of_parse_phandle() internally, so perhaps:
> >>
> >> foo->syscon_dev = imx_syscon_lookup(np, "fsl,anatop", 0);
> >> if (IS_ERR(foo->syscon_dev))
> >>     return PTR_ERR(foo->syscon_dev);
> >>
> >> with imx_syscon_lookup() internally knowing when to return EPROBE_DEFER
> >> rather than any other permanent error code (e.g. for missing property,
> >> bad phandle, etc.)
> >
> > In some case that we access register in machine code, we don't have any
> > phandle. The node is got by find compatible or by path.
> 
> That sounds a little odd; why not just use a phandle consistently
> everywhere?
Maybe for some places we do not have that device node, e.g:
arch/arm/mach-imx/mach-imx6q.c

> 
> Either way though, I could imagine still putting all the lookup code
> into the syscon driver; just have different functions for the different
> lookup methods:
> 
> imx_syscon_lookup_by_phandle(np, char *property_name)
Probably we do not need the left two lookup, below seems also ok if needed:
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
regmap = imx_syscon_lookup_by_phandle(np, property_name)
Then we do not need to handle how to find the compatible node.

> imx_syscon_lookup_by_compatible(char *compatible
> imx_syscon_lookup_by_path(char *node_path)

Regards
Dong Aisheng



From marex at denx.de  Thu Aug 23 23:25:41 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 05:25:41 +0200
Subject: [PATCH 1/2] ARM: mx28: Add SPI pinmux into imx28.dtsi
Message-ID: <1345778742-20994-1-git-send-email-marex@denx.de>

Add this SSP pin multiplexing configuration into the imx28.dtsi file.
This covers pinmux for all four SSP ports available on the i.MX28.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28.dtsi |   61 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

NOTE: Shawn, I'd like to add this altogether. I have a board scheduled in my
      queue that uses other SSP ports, so I consider it pointless to split this.
      Fabio, what does MX28EVK use?

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 91b43e9..327a33f 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -507,6 +507,67 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <0>;
 				};
+
+				spi0_pins_a: spi0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+						0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+						0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+						0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+						0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
+						0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
+						0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
+						0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
+						0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+						0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+						0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi1_pins_a: spi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x20c0 /* MX28_PAD_SSP1_SCK__SSP1_SCK */
+						0x20d0 /* MX28_PAD_SSP1_CMD__SSP1_CMD */
+						0x20e0 /* MX28_PAD_SSP1_DATA0__SSP1_D0 */
+						0x20f0 /* MX28_PAD_SSP1_DATA3__SSP1_D3 */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi2_pins_a: spi2 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+						0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+						0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+						0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+						0x2140 /* MX28_PAD_SSP2_SS1__SSP2_D4 */
+						0x2150 /* MX28_PAD_SSP2_SS2__SSP2_D5 */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				spi3_pins_a: spi3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */
+						0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */
+						0x21a0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */
+						0x21b0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
 			};
 
 			digctl at 8001c000 {
-- 
1.7.10.4



From marex at denx.de  Thu Aug 23 23:25:42 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 05:25:42 +0200
Subject: [PATCH 2/2] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <1345778742-20994-1-git-send-email-marex@denx.de>
References: <1345778742-20994-1-git-send-email-marex@denx.de>
Message-ID: <1345778742-20994-2-git-send-email-marex@denx.de>

Update the mach-mxs machine by removing the enet_clkout(). The new
revision of the board doesn't need that. Also, update the DTS file
with all the new drivers pulled in the mainline recently, that is,
SPI, LRADC, USB. Also, remove bogus AUART3.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28-m28evk.dts |   98 +++++++++++++++++++++++++++++++++---
 arch/arm/mach-mxs/mach-mxs.c       |    1 -
 2 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd..e418b75 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
 	apb at 80000000 {
 		apbh at 80000000 {
 			gpmi-nand at 8000c000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
 				status = "okay";
@@ -62,9 +64,28 @@
 					     &mmc0_sck_cfg>;
 				bus-width = <8>;
 				wp-gpios = <&gpio3 10 1>;
+				vmmc-supply = <&reg_vddio_sd0>;
 				status = "okay";
 			};
 
+			ssp2: ssp at 80014000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi2_pins_a>;
+				status = "okay";
+
+				flash: m25p80 at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "m25p80";
+					spi-max-frequency = <40000000>;
+					m25p,fast-read;
+					reg = <0>;
+				};
+			};
+
 			pinctrl at 80018000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
@@ -72,8 +93,11 @@
 				hog_pins_a: hog-gpios at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
+						0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
 						0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
 						0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+						0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+						0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
 					>;
 					fsl,drive-strength = <0>;
 					fsl,voltage = <1>;
@@ -90,6 +114,22 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <0>;
 				};
+
+				usb0_pins_a: usb0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2152>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				usb1_pins_a: usb1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2142>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
 			};
 
 			lcdif at 80030000 {
@@ -99,6 +139,10 @@
 				status = "okay";
 			};
 
+			lradc at 80050000 {
+				status = "okay";
+			};
+
 			can0: can at 80032000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&can0_pins_a>;
@@ -129,6 +173,7 @@
 			i2c0: i2c at 80058000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2c0_pins_a>;
+				clock-frequency = <400000>;
 				status = "okay";
 
 				sgtl5000: codec at 0a {
@@ -157,26 +202,41 @@
 				status = "okay";
 			};
 
-			auart0: serial at 8006a000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&auart0_2pins_a>;
+			usbphy0: usbphy at 8007c000 {
 				status = "okay";
 			};
 
-			auart3: serial at 80070000 {
+			usbphy1: usbphy at 8007e000 {
+				status = "okay";
+			};
+
+			auart0: serial at 8006a000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&auart3_pins_a>;
+				pinctrl-0 = <&auart0_2pins_a>;
 				status = "okay";
 			};
 		};
 	};
 
 	ahb at 80080000 {
+		usb0: usb at 80080000 {
+			vbus-supply = <&reg_usb0_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb0_pins_a>;
+			status = "okay";
+		};
+
+		usb1: usb at 80090000 {
+			vbus-supply = <&reg_usb1_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usb1_pins_a>;
+			status = "okay";
+		};
+
 		mac0: ethernet at 800f0000 {
 			phy-mode = "rmii";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mac0_pins_a>;
-			phy-reset-gpios = <&gpio3 11 0>;
 			status = "okay";
 		};
 
@@ -198,6 +258,32 @@
 			regulator-max-microvolt = <3300000>;
 			regulator-always-on;
 		};
+
+		reg_vddio_sd0: vddio-sd0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vddio-sd0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 28 0>;
+		};
+
+		reg_usb0_vbus: usb0_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 12 0>;
+			enable-active-low;
+		};
+
+		reg_usb1_vbus: usb1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 13 0>;
+			enable-active-low;
+		};
 	};
 
 	sound {
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe8..5ac45a1 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -241,7 +241,6 @@ static void __init imx28_evk_init(void)
 
 static void __init m28evk_init(void)
 {
-	enable_clk_enet_out();
 	update_fec_mac_prop(OUI_DENX);
 
 	mxsfb_pdata.mode_list = m28evk_video_modes;
-- 
1.7.10.4



From shawn.guo at linaro.org  Thu Aug 23 23:33:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 11:33:47 +0800
Subject: [PATCH] ARM: imx: fix imx51 babbage SD2 CD/WP
Message-ID: <1345779227-3700-1-git-send-email-shawn.guo@linaro.org>

Pads GPIO1_6 and GPIO1_5 are used as SD2 CD/WP on imx51 babbage board.
Before commit 5d23b39 (ARM: i.MX51 iomux: add missed definitions for
SION-bit and mode for some pads) gets in, we use the pad settings
configured by bootloader with NO_PAD_CTRL and SD2 CD/WP just works.
The commit changes the pad settings and causes SD2 CD/WP stop working.

Set up pads GPIO1_6 and GPIO1_5 in the configuation that bootloader
uses on imx51 babbage board to fix the SD2 CD/WP regression.

Cc: <stable at vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-mx51_babbage.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 7b31cbd..83f49c4 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -154,8 +154,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
 	MX51_PAD_SD2_DATA2__SD2_DATA2,
 	MX51_PAD_SD2_DATA3__SD2_DATA3,
 	/* CD/WP gpio */
-	MX51_PAD_GPIO1_6__GPIO1_6,
-	MX51_PAD_GPIO1_5__GPIO1_5,
+	NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
+	NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
 
 	/* eCSPI1 */
 	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-- 
1.7.5.4



From swarren at wwwdotorg.org  Thu Aug 23 23:34:41 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 23 Aug 2012 21:34:41 -0600
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <5036B639.20608@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org> <50369305.6050304@gmail.com>
 <50369FEE.8000003@wwwdotorg.org> <5036B639.20608@gmail.com>
Message-ID: <5036F651.4020700@wwwdotorg.org>

On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
> On 08/23/2012 11:26 PM, Stephen Warren wrote:
>> As you may have guessed, I strongly prefer the hard-coded static table
>> based approach, or at least separating the definition of known
>> pins/groups/functions from the configuration nodes that define which
>> particular mux settings to actually use.
>>
>> Puting this all a little more simply, the pinctrl core wants to generate
>> a list of all known functions. It is a single global/unified list. It
>> first calls pinmux_ops.get_functions_count() to find out how many
>> functions there are in the list, then pinmux_ops.get_function_name() for
>> each one to find its name, then pinmux_ops.get_function_groups() to find
>> out which groups allow that function to be mux'd onto them.
> 
> Ok, now this becomes a little bit more clear to me.
> 
> Consider uart1 on dove is muxable to:
> mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts),
> and finally mpp_uart1(rx and tx).
> 
> So possible, valid combinations for uart1 would be:
> (a) mpp_uart1;
> (b) mpp_uart1, mpp2, mpp3;
> (c) mpp_uart1, mpp21, mpp22;
> (d) mpp_uart1, mpp2, mpp22;
> (e) mpp_uart1, mpp21, mpp3;
> 
> Now what we currently do is, use DT to setup all known functions with e.g.
> marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1".
> This requires to count all pinctrl DT node children to count the known
> functions that can ever be muxed to. It will never allow to mux uart1 to sw
> flow control during run-time when there was no DT child node for it.

In the example above, there is a single function named "uart1". If this
was all the HW supported, I'd expect the driver's
pinmux_ops.get_functions_count() to return 1,
pinmux_ops.get_function_name(0) to return "uart1", and
pinmux_ops.get_function_name(n>0) to return an error.

In practice, I assume there are many other options that can be muxed
onto mpp2/3/21/22/uart1, so they'd be included in the list as well.

> But you are proposing to scan the list passed from SoC specific driver
> for all
> possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up
> lists
> of pingroups that can be used with this specific marvell,function; or
> even build
> up lists of pingroups that allow uart1(rts), and another one for
> uart1(cts), ...?

I don't expect any scanning, no. I'd expect that tables provided by the
SoC-specific drivers to be:

* A table of pins
* A table of groups
* A table of functions

No scanning involved.


From shc_work at mail.ru  Thu Aug 23 23:45:52 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Fri, 24 Aug 2012 07:45:52 +0400
Subject: [PATCH] GPIO: Add support for GPIO on CLPS711X-target platform
In-Reply-To: <CACRpkdZrcBLz+sg-AwWnBD0SA697uWQzocUYnbC1nPYG14LYyA@mail.gmail.com>
References: <1345635383-12224-1-git-send-email-shc_work@mail.ru>
 <CACRpkdZrcBLz+sg-AwWnBD0SA697uWQzocUYnbC1nPYG14LYyA@mail.gmail.com>
Message-ID: <20120824074552.97d32478.shc_work@mail.ru>

Hello.

On Fri, 24 Aug 2012 00:08:45 +0200
Linus Walleij <linus.walleij at linaro.org> wrote:

...
> > +static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
> > +{
> > +       int ret;
> > +       struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
> > +
> > +       mutex_lock(&gpio->lock);
> > +       ret = clps_readb(gpio_clps711x_port_dataaddr(chip)) & (1 << offset);
> > +       mutex_unlock(&gpio->lock);
> > +
> > +       return !!ret;
> > +}
> 
> Please get rid of this clps_readb() business. I can see it's just this:
> #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
> 
> This makes stuff hard to understand, please pass the virtual base as
> a memory resource to the platform device, store it in the state holder
> and just use readb() in the driver from that offset.

This will break the whole concept of this platform. All the CPU registers
are in one particular area, and therefore access to the registers of all
the drivers performed using the macro.
Maybe just add a short comment?

-- 
Alexander Shiyan <shc_work at mail.ru>


From marex at denx.de  Thu Aug 23 23:44:31 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 05:44:31 +0200
Subject: [PATCH V4] MXS: Implement DMA support into mxs-i2c
Message-ID: <1345779871-7677-1-git-send-email-marex@denx.de>

This patch implements DMA support into mxs-i2c. DMA transfers are now enabled
via DT. The DMA operation is enabled by default.

Signed-off-by: Marek Vasut <marex at denx.de>
CC: Fabio Estevam <fabio.estevam at freescale.com>
Cc: linux-i2c at vger.kernel.org
CC: Shawn Guo <shawn.guo at linaro.org>
Cc: Wolfram Sang <w.sang at pengutronix.de>
---
 Documentation/devicetree/bindings/i2c/i2c-mxs.txt |    2 +
 arch/arm/boot/dts/imx28.dtsi                      |    2 +
 drivers/i2c/busses/i2c-mxs.c                      |  269 +++++++++++++++++++--
 3 files changed, 251 insertions(+), 22 deletions(-)

V2: Fixed return value from mxs_i2c_dma_setup_xfer().
    Fixed coding style nitpicks
    Call mxs_i2c_dma_finish() in failpath only if DMA is active
V3: Align with changes in previous patch
V4: Succumb to nonsense for the greater good ... like working EEPROMs
    Add "use_pioqueue" module parameter

diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
index 30ac3a0..7a3fe9e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt
@@ -6,6 +6,7 @@ Required properties:
 - interrupts: Should contain ERROR and DMA interrupts
 - clock-frequency: Desired I2C bus clock frequency in Hz.
                    Only 100000Hz and 400000Hz modes are supported.
+- fsl,i2c-dma-channel: APBX DMA channel for the I2C
 
 Examples:
 
@@ -16,4 +17,5 @@ i2c0: i2c at 80058000 {
 	reg = <0x80058000 2000>;
 	interrupts = <111 68>;
 	clock-frequency = <100000>;
+	fsl,i2c-dma-channel = <6>;
 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d19..ba8227e 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -661,6 +661,7 @@
 				reg = <0x80058000 0x2000>;
 				interrupts = <111 68>;
 				clock-frequency = <100000>;
+				fsl,i2c-dma-channel = <6>;
 				status = "disabled";
 			};
 
@@ -671,6 +672,7 @@
 				reg = <0x8005a000 0x2000>;
 				interrupts = <110 69>;
 				clock-frequency = <100000>;
+				fsl,i2c-dma-channel = <7>;
 				status = "disabled";
 			};
 
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 088c5c1..83c3a7e 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -7,8 +7,6 @@
  *
  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
- * TODO: add dma-support if platform-support for it is available
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -31,9 +29,16 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_i2c.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/fsl/mxs-dma.h>
 
 #define DRIVER_NAME "mxs-i2c"
 
+static bool use_pioqueue;
+module_param(use_pioqueue, bool, 0);
+MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA");
+
 #define MXS_I2C_CTRL0		(0x00)
 #define MXS_I2C_CTRL0_SET	(0x04)
 
@@ -146,6 +151,16 @@ struct mxs_i2c_dev {
 	u32 cmd_err;
 	struct i2c_adapter adapter;
 	const struct mxs_i2c_speed_config *speed;
+
+	/* DMA support components */
+	bool				dma_mode;
+	int				dma_channel;
+	struct dma_chan         	*dmach;
+	struct mxs_dma_data		dma_data;
+	uint32_t			pio_data[2];
+	uint32_t			addr_data;
+	struct scatterlist		sg_io[2];
+	bool				dma_read;
 };
 
 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
@@ -157,7 +172,11 @@ static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 	writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
 
 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
-	writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
+	if (i2c->dma_mode)
+		writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
+			i2c->regs + MXS_I2C_QUEUECTRL_CLR);
+	else
+		writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
 }
 
@@ -248,6 +267,150 @@ static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
 	return 0;
 }
 
+static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
+{
+	if (i2c->dma_read) {
+		dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
+		dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
+	} else {
+		dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
+	}
+}
+
+static void mxs_i2c_dma_irq_callback(void *param)
+{
+	struct mxs_i2c_dev *i2c = param;
+
+	complete(&i2c->cmd_complete);
+	mxs_i2c_dma_finish(i2c);
+}
+
+static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
+			struct i2c_msg *msg, uint32_t flags)
+{
+	struct dma_async_tx_descriptor *desc;
+	struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
+
+	if (msg->flags & I2C_M_RD) {
+		i2c->dma_read = 1;
+		i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
+
+		/*
+		 * SELECT command.
+		 */
+
+		/* Queue the PIO register write transfer. */
+		i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
+		desc = dmaengine_prep_slave_sg(i2c->dmach,
+					(struct scatterlist *)&i2c->pio_data[0],
+					1, DMA_TRANS_NONE, 0);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get PIO reg. write descriptor.\n");
+			goto select_init_pio_fail;
+		}
+
+		/* Queue the DMA data transfer. */
+		sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
+		dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
+		desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
+					DMA_MEM_TO_DEV,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get DMA data write descriptor.\n");
+			goto select_init_dma_fail;
+		}
+
+		/*
+		 * READ command.
+		 */
+
+		/* Queue the PIO register write transfer. */
+		i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
+				MXS_I2C_CTRL0_XFER_COUNT(msg->len);
+		desc = dmaengine_prep_slave_sg(i2c->dmach,
+					(struct scatterlist *)&i2c->pio_data[1],
+					1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get PIO reg. write descriptor.\n");
+			goto select_init_dma_fail;
+		}
+
+		/* Queue the DMA data transfer. */
+		sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
+		dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
+		desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
+					DMA_DEV_TO_MEM,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get DMA data write descriptor.\n");
+			goto read_init_dma_fail;
+		}
+	} else {
+		i2c->dma_read = 0;
+		i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
+
+		/*
+		 * WRITE command.
+		 */
+
+		/* Queue the PIO register write transfer. */
+		i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
+				MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
+		desc = dmaengine_prep_slave_sg(i2c->dmach,
+					(struct scatterlist *)&i2c->pio_data[0],
+					1, DMA_TRANS_NONE, 0);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get PIO reg. write descriptor.\n");
+			goto write_init_pio_fail;
+		}
+
+		/* Queue the DMA data transfer. */
+		sg_init_table(i2c->sg_io, 2);
+		sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
+		sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
+		dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
+		desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
+					DMA_MEM_TO_DEV,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc) {
+			dev_err(i2c->dev,
+				"Failed to get DMA data write descriptor.\n");
+			goto write_init_dma_fail;
+		}
+	}
+
+	/*
+	 * The last descriptor must have this callback,
+	 * to finish the DMA transaction.
+	 */
+	desc->callback = mxs_i2c_dma_irq_callback;
+	desc->callback_param = i2c;
+
+	/* Start the transfer. */
+	dmaengine_submit(desc);
+	dma_async_issue_pending(i2c->dmach);
+	return 0;
+
+/* Read failpath. */
+read_init_dma_fail:
+	dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
+select_init_dma_fail:
+	dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
+select_init_pio_fail:
+	return -EINVAL;
+
+/* Write failpath. */
+write_init_dma_fail:
+	dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
+write_init_pio_fail:
+	return -EINVAL;
+}
+
 /*
  * Low level master read/write transaction.
  */
@@ -258,6 +421,8 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 	int ret;
 	int flags;
 
+	flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
+
 	dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 		msg->addr, msg->len, msg->flags, stop);
 
@@ -267,23 +432,29 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 	init_completion(&i2c->cmd_complete);
 	i2c->cmd_err = 0;
 
-	flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
-
-	if (msg->flags & I2C_M_RD)
-		mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
-	else
-		mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
-					flags);
+	if (i2c->dma_mode) {
+		ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
+		if (ret)
+			return ret;
+	} else {
+		if (msg->flags & I2C_M_RD) {
+			mxs_i2c_pioq_setup_read(i2c, msg->addr,
+						msg->len, flags);
+		} else {
+			mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf,
+						msg->len, flags);
+		}
 
-	writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
+		writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
+	}
 
 	ret = wait_for_completion_timeout(&i2c->cmd_complete,
 						msecs_to_jiffies(1000));
 	if (ret == 0)
 		goto timeout;
 
-	if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
+	if (!i2c->dma_mode && !i2c->cmd_err && (msg->flags & I2C_M_RD)) {
 		ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
 		if (ret)
 			goto timeout;
@@ -301,6 +472,8 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 
 timeout:
 	dev_dbg(i2c->dev, "Timeout!\n");
+	if (i2c->dma_mode)
+		mxs_i2c_dma_finish(i2c);
 	mxs_i2c_reset(i2c);
 	return -ETIMEDOUT;
 }
@@ -342,11 +515,13 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 		/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 		i2c->cmd_err = -EIO;
 
-	is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
-		MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
+	if (!i2c->dma_mode) {
+		is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
+			MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
 
-	if (is_last_cmd || i2c->cmd_err)
-		complete(&i2c->cmd_complete);
+		if (is_last_cmd || i2c->cmd_err)
+			complete(&i2c->cmd_complete);
+	}
 
 	writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 
@@ -358,6 +533,21 @@ static const struct i2c_algorithm mxs_i2c_algo = {
 	.functionality = mxs_i2c_func,
 };
 
+static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
+{
+	struct mxs_i2c_dev *i2c = param;
+
+	if (!mxs_dma_is_apbx(chan))
+		return false;
+
+	if (chan->chan_id != i2c->dma_channel)
+		return false;
+
+	chan->private = &i2c->dma_data;
+
+	return true;
+}
+
 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 {
 	uint32_t speed;
@@ -368,6 +558,26 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 	if (!node)
 		return -EINVAL;
 
+	/*
+	 * The MXS I2C DMA mode is prefered and enabled by default.
+	 * The PIO mode is still supported, but should be used only
+	 * for debuging purposes etc.
+	 */
+	i2c->dma_mode = !use_pioqueue;
+	if (!i2c->dma_mode)
+		dev_info(dev, "Using PIOQUEUE mode for I2C transfers!\n");
+
+	/*
+	 * TODO: This is a temporary solution and should be changed
+	 * to use generic DMA binding later when the helpers get in.
+	 */
+	ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
+				   &i2c->dma_channel);
+	if (ret) {
+		dev_warn(dev, "Failed to get DMA channel, using PIOQUEUE!\n");
+		i2c->dma_mode = 0;
+	}
+
 	i2c->speed = &mxs_i2c_95kHz_config;
 	ret = of_property_read_u32(node, "clock-frequency", &speed);
 	if (ret)
@@ -388,7 +598,8 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 	struct pinctrl *pinctrl;
 	struct resource *res;
 	resource_size_t res_size;
-	int err, irq;
+	int err, irq, dmairq;
+	dma_cap_mask_t mask;
 
 	pinctrl = devm_pinctrl_get_select_default(dev);
 	if (IS_ERR(pinctrl))
@@ -399,7 +610,10 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
+	irq = platform_get_irq(pdev, 0);
+	dmairq = platform_get_irq(pdev, 1);
+
+	if (!res || irq < 0 || dmairq < 0)
 		return -ENOENT;
 
 	res_size = resource_size(res);
@@ -410,10 +624,6 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 	if (!i2c->regs)
 		return -EBUSY;
 
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
 	err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 	if (err)
 		return err;
@@ -424,6 +634,18 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 	if (err)
 		return err;
 
+	/* Setup the DMA */
+	if (i2c->dma_mode) {
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_SLAVE, mask);
+		i2c->dma_data.chan_irq = dmairq;
+		i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
+		if (!i2c->dmach) {
+			dev_err(dev, "Failed to request dma\n");
+			return -ENODEV;
+		}
+	}
+
 	platform_set_drvdata(pdev, i2c);
 
 	/* Do reset to enforce correct startup after pinmuxing */
@@ -459,6 +681,9 @@ static int __devexit mxs_i2c_remove(struct platform_device *pdev)
 	if (ret)
 		return -EBUSY;
 
+	if (i2c->dmach)
+		dma_release_channel(i2c->dmach);
+
 	writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 
 	platform_set_drvdata(pdev, NULL);
-- 
1.7.10.4



From thomas.abraham at linaro.org  Fri Aug 24 00:25:16 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 24 Aug 2012 09:55:16 +0530
Subject: [PATCH v3 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <5036B8EB.5050502@wwwdotorg.org>
References: <1345720529-32315-1-git-send-email-thomas.abraham@linaro.org>
 <1345720529-32315-2-git-send-email-thomas.abraham@linaro.org>
 <5036B8EB.5050502@wwwdotorg.org>
Message-ID: <CAJuYYwQ2fGxVddWiaUGXQWfSUCw9LBBpYF=pKPFkU5RmZfpJRg@mail.gmail.com>

On 24 August 2012 04:42, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 08/23/2012 05:15 AM, Thomas Abraham wrote:
>> Add a new device tree enabled pinctrl and gpiolib driver for Samsung
>> SoC's. This driver provides a common and extensible framework for all
>> Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
>> driver supports only device tree based instantiation and hence can be
>> used only on those Samsung platforms that have device tree enabled.
>>
>> This driver is split into two parts: the pinctrl interface and the gpiolib
>> interface. The pinctrl interface registers pinctrl devices with the pinctrl
>> subsystem and gpiolib interface registers gpio chips with the gpiolib
>> subsystem. The information about the pins, pin groups, pin functions and
>> gpio chips, which are SoC specific, are parsed from device tree node.
>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>
> BTW, this is a very nicely written and complete/precise binding
> document. Well done.

Thank you!

>
>> +Samsung GPIO and Pin Mux/Config controller
>> +
>> +Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
>> +controller. It controls the input/output settings on the available pads/pins
>> +and also provides ability to multiplex and configure the output of various
>> +on-chip controllers onto these pads.
>> +
>> +Required Properties:
>> +- compatible: should be one of the following.
>> +  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
>> +  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
>> +
>> +- reg: Base address of the pin controller hardware module and length of
>> +  the address space it occupies.
>> +
>> +- interrupts: interrupt specifier for the controller. The format and value of
>> +  the interrupt specifier depends on the interrupt parent for the controller.
>> +
>> +- Pin mux/config groups as child nodes: The pin mux (selecting pin function
>
> Direct child nodes of the pin-controller, not a second level?

The child nodes would be direct child nodes.

>
> While that's quite legal, it means that if you need a particular client
> module to use 4 pins, 2 of which need one samsung,pin-function value and
> 2 of which need a different pin-function value, then the client device's
> pinctrl-0 property has to have two entries.
>
> i.e. a completely hypothetical example roughly based on yours below:
>
>         pinctrl_1: pinctrl at 11000000 {
>                 uart0_rxd: uart0-rxd {
>                         samsung,pins = "gpa0-0";
>                         samsung,pin-function = <2>;
>                         samsung,pin-pud = <0>;
>                         samsung,pin-drv = <0>;
>                 };
>
>                 uart0_txd: uart0-txd {
>                         samsung,pins = "gpa0-1";
>                         samsung,pin-function = <1>;
>                         samsung,pin-pud = <0>;
>                         samsung,pin-drv = <0>;
>                 };
>         };
>
>         uart at 13800000 {
>                 pinctrl-names = "default";
>                 pinctrl-0 = <&uart0_rxd &uart0_txd>;
>         };
>
> rather than:
>
>         pinctrl_1: pinctrl at 11000000 {
>                 uart0_opt1: uart0-opt1 {
>                         uart0_rxd: uart0-rxd {
>                                 samsung,pins = "gpa0-0";
>                                 samsung,pin-function = <2>;
>                                 samsung,pin-pud = <0>;
>                                 samsung,pin-drv = <0>;
>                         };
>
>                         uart0_txd: uart0-txd {
>                                 samsung,pins = "gpa0-1";
>                                 samsung,pin-function = <1>;
>                                 samsung,pin-pud = <0>;
>                                 samsung,pin-drv = <0>;
>                         };
>                 };
>         };
>
>         uart at 13800000 {
>                 pinctrl-names = "default";
>                 pinctrl-0 = <&uart0_opt1;
>         };
>
> The latter layout simplifies writing the client nodes, since all the
> related settings can be grouped together by whoever writes the pinctrl
> node, rather than every client author having to work out all the entries
> to include in the list.
>
> That all said, the way you've defined the binding is perfectly
> legitimate, and I don't have any kind of issue with it; it's just
> something you might want to consider.

Thanks for suggesting this alternate method. I do agree with your
point. But, for now, I would prefer to stabilize this driver without
changing the dt parsing code and make it usable for client nodes. I
will revisit your suggested approach at a later point. I assume for
now that the author's of client nodes know which pin settings to
select.

>
> Irrespective of whether you choose to keep the binding as-is, or change
> it, please consider it:
>
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>

Thanks.

>
>> +  The values specified by these config properties should be dervied from the
>
> s/dervied/derived/

Ok.

>
>> +External GPIO and Wakeup Interrupts:
>> +
>> +The controller supports two types of external interrupts over gpio. The first
>> +is the external gpio interrupt and second is the external wakeup interrupts.
>> +The difference between the two is that the external wakeup interrupts can be
>> +used as system wakeup events.
>> +
>> +A. External GPIO Interrupts: For supporting external gpio interrupts, the
>> +   properties should be specified in the pin-controller device node.
>
> s/the properties/the following properties/ ?

Ok.

>
>> +Aliases:
>> +
>> +All the pin controller nodes should be represented in the aliases node using
>> +the following format 'pinctrl{n}' where n is a unique number for the alias.
>
> There /should/ be an alias, or there /may/ be; I'm not sure why
> requiring or recommending an alias would be particularly important for
> this device?

The alias is required since the SoC data for a particular instance is
dependent on the instance number. And the instance number is derived
from the alias.

>
> I've only had time to review the binding document so far.

Ok. Thanks Stephen for your comments on this patch.

Regards,
Thomas.


From linux at prisktech.co.nz  Fri Aug 24 00:29:19 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 24 Aug 2012 16:29:19 +1200
Subject: [PATCH 1/1] clk: add DT support for clock gating control
In-Reply-To: <20120824023135.4547.2534@nucleus>
References: <1341767726-25630-1-git-send-email-sebastian.hesselbarth@googlemail.com>
 <20120824023135.4547.2534@nucleus>
Message-ID: <1345782559.20538.22.camel@gitbox>

On Thu, 2012-08-23 at 19:31 -0700, Mike Turquette wrote:
> Quoting Sebastian Hesselbarth (2012-07-08 10:15:26)
> > This patch adds support for using clock gates (clk-gate) from DT based
> > on Rob Herrings DT clk binding support for 3.6.
> > 
> > It adds a helper function to clk-gate to allocate all resources required by
> > a set of individual clock gates, i.e. register base address and lock. Each
> > clock gate is described as a child of the clock-gating-control in DT and
> > also created by the helper function.
> > 
> 
> Hi Sebastian,
> 
> Thanks for submitting this.  I'd prefer for Rob or someone with a more vested
> interest in DT to review your binding.  I have some comments on the code below.
> 
> <snip>
> > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> > index 578465e..1e88907 100644
> > --- a/drivers/clk/clk-gate.c
> > +++ b/drivers/clk/clk-gate.c
> > @@ -15,6 +15,9 @@
> >  #include <linux/io.h>
> >  #include <linux/err.h>
> >  #include <linux/string.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_platform.h>
> >  
> >  /**
> >   * DOC: basic gatable clock which can gate and ungate it's ouput
> > @@ -148,3 +151,84 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
> >  
> >         return clk;
> >  }
> > +
> > +#ifdef CONFIG_OF
> > +/**
> > + * of_clock_gating_control_setup() - Setup function for clock gate control
> > + *   This is a helper for using clk-gate from OF device tree. It allocates
> > + *   a common lock for a base register and creates the individual clk-gates.
> > + */
> > +void __init of_clock_gating_control_setup(struct device_node *np)
> > +{
> > +       struct device_node *child;
> > +       const char *pclk_name;
> > +       void __iomem *base;
> > +       spinlock_t *lockp;
> > +       unsigned int rnum;
> > +       u64 addr;
> > +
> > +       pclk_name = of_clk_get_parent_name(np, 0);
> > +       if (!pclk_name) {
> > +               pr_debug("%s: unable to get parent clock for %s\n",
> > +                       __func__, np->full_name);
> > +               return;
> > +       }
> > +
> > +       lockp = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
> > +       if (!lockp) {
> > +               pr_debug("%s: unable to allocate spinlock for %s\n",
> > +                        __func__, np->full_name);
> > +               return;
> > +       }
> > +
> > +       spin_lock_init(lockp);
> 
> The spinlocks for the basic clock types have always been optional.  This
> code should reflect that and not assume the spinlock.
> 
> Also I wonder if the assumption is true that a single spinlock
> corresponding to a device_node is always the right thing for every
> platform.  What about a 32-bit register that contains some gating bits
> and a 3-bit wide field for a mux which we perform read-modify-write
> operations on?
> 
> You'll have to pardon my DT ignorance.  My concerns above may be totally
> crazy with respect to DT.

This also requires you to split your gated clocks in seperate nodes by
register if you don't want unrelated clocks locking each other out.
Also, you need a method of 'sharing' the lock outside of the gated-clock
for use by other clock types that may share the same register.

> 
> > +       base = of_iomap(np, 0);
> > +       rnum = sizeof(resource_size_t) * 8;
> > +       addr = of_translate_address(np, of_get_property(np, "reg", NULL));
> > +
> > +       pr_debug("create clock gate control %s\n", np->full_name);
> 
> There are some inconsistent prints here.  How about leading this trace
> with a __func__ like you do below for the error messages?
> 
> > +
> > +       for_each_child_of_node(np, child) {
> > +               struct clk *cg;
> > +               const char *cg_name;
> > +               const char *cg_pclk_name;
> > +               u32 propval[2];
> > +               unsigned int rbit;
> > +
> > +               if (of_property_read_u32_array(child, "reg", propval, 2)) {
> > +                       pr_debug("%s: wrong #reg on %s\n",
> > +                                __func__, child->full_name);
> > +                       continue;
> > +               }
Are you assuming that all gated-clocks will be contained within a parent
node with:
#address-cells = <1>;
#size-cells = <1>;
with no other types of clocks? This generally isn't how people are
writing their device tree files.

Looking through the current dts files, the platforms that are using
clocks to any real degree are using address=1, size=0.
The only ones I see with 1/1 are only defining a fixed-clock and don't
use the reg property anyway so could just as well be 1/0.

It might be better to pass the bit field as a separate property rather
than requiring people change their reg property to suit.

myclock {
	reg = <0x0120>;
	enable-bit = <22>;
};


Regards

Tony Prisk



From arnd at arndb.de  Fri Aug 24 01:40:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 24 Aug 2012 05:40:12 +0000
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1345758702.2061.6.camel@gitbox>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de> <1345758702.2061.6.camel@gitbox>
Message-ID: <201208240540.12316.arnd@arndb.de>

On Thursday 23 August 2012, Tony Prisk wrote:
> I was about to say that if Mike has any issues with the driver that I
> can fix the patch conflict at the same time, but I just realised that
> its more work than I originally thought :)
> 
> I was going to move the arch-vt8500 part of the clocks patch back into
> the clocks patch - but that will just move the issue from arm-soc to
> clocks because Mike's branch won't have the arch-vt8500 patch so the
> patch will fail.

But that's ok, because without the arch-v8500 part, nothing uses
the vt8500-clock driver, so nothing breaks. You can introduce broken
code in the meantime as long as it's impossible to enable and it will
work afterwards.

	Arnd


From anilkumar at ti.com  Fri Aug 24 01:50:17 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Fri, 24 Aug 2012 05:50:17 +0000
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>

Hi Koen,

On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
> 
> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
> 
> > Add tps65217 regulator device tree data to AM335x-Bone by adding
> > regulator consumers with tightened constraints and regulator-name.
> > TPS65217 regulator handle can be obtained by using this regulator
> > name.
> > 
> > This patch also add I2C node with I2C frequency and tps65217 PMIC
> > I2C slave address.
> > 
> > Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> 
> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?

Use this repo to test on beaglebone
https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl

This wiki talks about how to build and use?
https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree

Note: Enable tps65217 regulator in kernel config.

Regards
AnilKumar


From linux at prisktech.co.nz  Fri Aug 24 01:52:16 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 24 Aug 2012 17:52:16 +1200
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <201208240540.12316.arnd@arndb.de>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de> <1345758702.2061.6.camel@gitbox>
 <201208240540.12316.arnd@arndb.de>
Message-ID: <1345787536.23177.3.camel@gitbox>

On Fri, 2012-08-24 at 05:40 +0000, Arnd Bergmann wrote:
> On Thursday 23 August 2012, Tony Prisk wrote:
> > I was about to say that if Mike has any issues with the driver that I
> > can fix the patch conflict at the same time, but I just realised that
> > its more work than I originally thought :)
> > 
> > I was going to move the arch-vt8500 part of the clocks patch back into
> > the clocks patch - but that will just move the issue from arm-soc to
> > clocks because Mike's branch won't have the arch-vt8500 patch so the
> > patch will fail.
> 
> But that's ok, because without the arch-v8500 part, nothing uses
> the vt8500-clock driver, so nothing breaks. You can introduce broken
> code in the meantime as long as it's impossible to enable and it will
> work afterwards.
> 
> 	Arnd

You lost me a little bit there :)
If it stays as is now, the arch-vt8500 patch will introduce an
unresolved symbol.
If I move the clock code from the arch-vt8500 patch to the clock patch,
then the clock patch won't apply because it needs the arch-vt8500 patch
first and Mike won't have that patch, but it would be fine if both
patches went in via your tree.

Or are you saying to apply the clock patch as is before the arch-vt8500
patch?

Tony P



From alchark at gmail.com  Fri Aug 24 01:54:25 2012
From: alchark at gmail.com (Alexey Charkov)
Date: Fri, 24 Aug 2012 09:54:25 +0400
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1345787536.23177.3.camel@gitbox>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de> <1345758702.2061.6.camel@gitbox>
 <201208240540.12316.arnd@arndb.de>
 <1345787536.23177.3.camel@gitbox>
Message-ID: <CABjd4Yxxf5XDc6gs0WABZgF3SOd89J7CfjsU9uitOg4qpQ4WEQ@mail.gmail.com>

2012/8/24 Tony Prisk <linux at prisktech.co.nz>:
> On Fri, 2012-08-24 at 05:40 +0000, Arnd Bergmann wrote:
>> On Thursday 23 August 2012, Tony Prisk wrote:
>> > I was about to say that if Mike has any issues with the driver that I
>> > can fix the patch conflict at the same time, but I just realised that
>> > its more work than I originally thought :)
>> >
>> > I was going to move the arch-vt8500 part of the clocks patch back into
>> > the clocks patch - but that will just move the issue from arm-soc to
>> > clocks because Mike's branch won't have the arch-vt8500 patch so the
>> > patch will fail.
>>
>> But that's ok, because without the arch-v8500 part, nothing uses
>> the vt8500-clock driver, so nothing breaks. You can introduce broken
>> code in the meantime as long as it's impossible to enable and it will
>> work afterwards.
>>
>>       Arnd
>
> You lost me a little bit there :)
> If it stays as is now, the arch-vt8500 patch will introduce an
> unresolved symbol.
> If I move the clock code from the arch-vt8500 patch to the clock patch,
> then the clock patch won't apply because it needs the arch-vt8500 patch
> first and Mike won't have that patch, but it would be fine if both
> patches went in via your tree.

Why don't you add a #define in the first patch that makes your
to-be-unresolved symbol a no-op and then drop it within the clock
patch?

Best,
Alexey


From paul at pwsan.com  Fri Aug 24 02:00:18 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 24 Aug 2012 06:00:18 +0000 (UTC)
Subject: [PATCH] MMC: OMAP MSDI: fix broken PIO mode
Message-ID: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com>


After commit 26b88520b80695a6fa5fd95b5d97c03f4daf87e0 ("mmc:
omap_hsmmc: remove private DMA API implementation"), the Nokia N800
here stopped booting:

[    2.086181] Waiting for root device /dev/mmcblk0p1...
[    2.324066] Unhandled fault: imprecise external abort (0x406) at 0x00000000
[    2.331451] Internal error: : 406 [#1] ARM
[    2.335784] Modules linked in:
[    2.339050] CPU: 0    Not tainted  (3.6.0-rc3 #60)
[    2.344146] PC is at default_idle+0x28/0x30
[    2.348602] LR is at trace_hardirqs_on_caller+0x15c/0x1b0

...

This turned out to be due to memory corruption caused by long-broken
PIO code in drivers/mmc/host/omap.c.  (Previously, this driver had
been using DMA; but the above commit caused the MMC driver to fall
back to PIO mode with an unmodified Kconfig.)

The PIO code, added with the rest of the driver in commit
730c9b7e6630f786fcec026fb11d2e6f2c90fdcb ("[MMC] Add OMAP MMC host
driver"), confused bytes with 16-bit words.  This bug caused memory
located after the PIO transfer buffer to be corrupted with transfers
larger than 32 bytes.  The driver also did not increment the buffer
pointer after the transfer occurred.  This bug resulted in data
corruption during any transfer larger than 64 bytes.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Juha Yrj?l? <juha.yrjola at nokia.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Carlos Aguiar <carlos.aguiar at indt.org.br>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/mmc/host/omap.c |   14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 50e08f0..a5999a7 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -668,7 +668,7 @@ mmc_omap_clk_timer(unsigned long data)
 static void
 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 {
-	int n;
+	int n, nwords;
 
 	if (host->buffer_bytes_left == 0) {
 		host->sg_idx++;
@@ -678,15 +678,23 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 	n = 64;
 	if (n > host->buffer_bytes_left)
 		n = host->buffer_bytes_left;
+
+	nwords = n / 2;
+	nwords += n & 1; /* handle odd number of bytes to transfer */
+
 	host->buffer_bytes_left -= n;
 	host->total_bytes_left -= n;
 	host->data->bytes_xfered += n;
 
 	if (write) {
-		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
+		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
+			      host->buffer, nwords);
 	} else {
-		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
+		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
+			     host->buffer, nwords);
 	}
+
+	host->buffer += nwords;
 }
 
 static inline void mmc_omap_report_irq(u16 status)
-- 
1.7.10.4

From koen at dominion.thruhere.net  Fri Aug 24 02:28:34 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 24 Aug 2012 08:28:34 +0200
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
Message-ID: <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>


Op 24 aug. 2012, om 07:50 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:

> Hi Koen,
> 
> On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
>> 
>> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
>> 
>>> Add tps65217 regulator device tree data to AM335x-Bone by adding
>>> regulator consumers with tightened constraints and regulator-name.
>>> TPS65217 regulator handle can be obtained by using this regulator
>>> name.
>>> 
>>> This patch also add I2C node with I2C frequency and tps65217 PMIC
>>> I2C slave address.
>>> 
>>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>> 
>> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?
> 
> Use this repo to test on beaglebone
> https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl
> 
> This wiki talks about how to build and use?
> https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree
> 
> Note: Enable tps65217 regulator in kernel config.

I used that repo and as a seperate test I rebased that to latest mainline, same thing: as soon as I turn on the TPS in the .config it crashes on boot. Is the pinctrl repo the *exact* repo you used to test the patches on beaglebone?

From shawn.guo at linaro.org  Fri Aug 24 02:43:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 14:43:00 +0800
Subject: [PATCH 1/7] mfd: add imx syscon driver based on regmap
In-Reply-To: <1345619928-15446-2-git-send-email-b29396@freescale.com>
References: <1345619928-15446-1-git-send-email-b29396@freescale.com>
 <1345619928-15446-2-git-send-email-b29396@freescale.com>
Message-ID: <20120824064257.GA31998@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 03:18:42PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Add regmap based imx syscon driver.
> This is usually used for access misc bits in registers which does not belong
> to a specific module, for example, IOMUXC GPR and ANATOP.
> With this driver, we provide a standard API for client driver to call to
> access registers which are registered into syscon.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> Currently it's just simply for IMX, however the driver really is not too
> much imx specific.
> If people want, we probably could extend it to support other platforms too.

Right.  I do not see anything IMX specific there.  We should probably
at least give the driver a generic name from day one.

-- 
Regards,
Shawn


From xiechao.mail at gmail.com  Fri Aug 24 03:07:19 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Fri, 24 Aug 2012 15:07:19 +0800
Subject: FW: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <CAN1soZxJ87=rL0Mq-3LFRXhqRGrKXcHS+rsMdVeM+yMK+WBCnQ@mail.gmail.com>
References: <AAD1C6EB06EE3649B35B7E026785068D1A754366CB@SC-VEXCH2.marvell.com>
 <CADApbehnsRzwu_LrAEMf+L7AvXv+JBtPBOzWHj578Vs6B_LrCw@mail.gmail.com>
 <201208220641.21891.arnd@arndb.de>
 <CAN1soZxJ87=rL0Mq-3LFRXhqRGrKXcHS+rsMdVeM+yMK+WBCnQ@mail.gmail.com>
Message-ID: <CADApbehj-AFDeJq=ig4AU5u9XGKgOK0imC=qNR9jet9kx3zW2g@mail.gmail.com>

hi, Mike
Can you help to review and merge these patches?

On Wed, Aug 22, 2012 at 4:00 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> On Wed, Aug 22, 2012 at 2:41 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>> On Wednesday 22 August 2012, Chao Xie wrote:
>>> >
>>> > Reviewed-by: Arnd Bergmann <arnd at arndb.de>
>>> >
>>> >         Arnd
>>>
>>> Who will be responsible for merging these patches?
>>>
>>
>> They should go through Mike's tree, unless there is a reason why he
>> prefers them to go through arm-soc. It would be helpful to add
>> an 'Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>' line
>> and my 'Reviewed-by: Arnd Bergmann <arnd at arndb.de>' line to each
>> patch for that.
>>
>>         Arnd
>
> I'm OK on these patches.
>
> Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>
>
> Regards
> Haojian


From santosh.shilimkar at ti.com  Fri Aug 24 03:10:12 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 24 Aug 2012 12:40:12 +0530
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
References: <1342485005-5178-1-git-send-email-javier@dowhile0.org>
 <CAMQu2gxaF8K78puE84+=8VJLbsdtdD97ww81XJxG6sCtYTYXww@mail.gmail.com>
 <CABxcv=nsmeVLspzXERYXebmPaNO6rKCsVnak7dMtvGjiYH4vOw@mail.gmail.com>
 <20120718065951.GH6522@atomide.com>
 <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
Message-ID: <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>

On Fri, Aug 24, 2012 at 2:30 AM, Peter Meerwald <pmeerw at pmeerw.net> wrote:
>
> On Wed, 18 Jul 2012, Javier Martinez Canillas wrote:
>
> > On Wed, Jul 18, 2012 at 10:36 AM, Shilimkar, Santosh
> > <santosh.shilimkar at ti.com> wrote:
> > > On Wed, Jul 18, 2012 at 1:14 PM, S, Venkatraman <svenkatr at ti.com>
> > > wrote:
> > >> On Wed, Jul 18, 2012 at 12:40 PM, Tony Lindgren <tony at atomide.com>
> > >> wrote:
> > >>> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120718 00:09]:
> > >>>> On Wed, Jul 18, 2012 at 12:29 PM, Tony Lindgren <tony at atomide.com>
> > >>>> wrote:
> > >>>> > * Javier Martinez Canillas <javier at dowhile0.org> [120716 23:56]:
> > >>>> >> On Tue, Jul 17, 2012 at 8:45 AM, Shilimkar, Santosh
> > >>>> >> <santosh.shilimkar at ti.com> wrote:
> > >>>> >> > Hi,
> > >>>> >> >
> > >>>> >> > On Tue, Jul 17, 2012 at 6:00 AM, Javier Martinez Canillas
> > >>>> >> > <javier at dowhile0.org> wrote:
> > >>>> >> >> The OMAP MMC and OMAP High Speed MMC hosts now use entirely
> > >>>> >> >> the DMA
> > >>>> >> >> engine API instead of the previous private DMA API
> > >>>> >> >> implementation.
> > >>>> >> >>
> > >>>> >> >> So, if the kernel is built with support for any of these
> > >>>> >> >> hosts but it
> > >>>> >> >> doesn't support DMA devices nor OMAP DMA support, it fails
> > >>>> >> >> when trying
> > >>>> >> >> to obtain a DMA channel which leads to the following error on
> > >>>> >> >> an OMAP3
> > >>>> >> >> IGEPv2 Rev.C board (and probably on most OMAP boards with MMC
> > >>>> >> >> support):
> > >>>> >> >>
> > >>>> >> >> [ 2.199981] omap_hsmmc omap_hsmmc.1: unable to obtain RX DMA
> > >>>> >> >> engine channel 48
> > >>>> >> >> [    2.215087] omap_hsmmc omap_hsmmc.0: unable to obtain RX
> > >>>> >> >> DMA engine channel 62
> > >>>> >> >>
> > >>>> >> >> selecting automatically CONFIG_DMADEVICES and CONFIG_DMA_OMAP
> > >>>> >> >> solves it.
> > >>>> >> >>
> > >>>> >> >> Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
> > >>>> >> >> ---
> > >>>> >> > Considering, we are updating drivers to select the DMA engine,
> > >>>> >> > can you
> > >>>> >> > also include
> > >>>> >> > "drivers/spi/spi-omap2-mcspi.c" which is also updated for DMA
> > >>>> >> > engine.
> > >>>> >> >
> > >>>> >> > Regards
> > >>>> >> > Santosh
> > >>>> >>
> > >>>> >> Hi Santosh,
> > >>>> >>
> > >>>> >> Ok, I'll send a v2 now which includes spi-omap2-mcspi then.
> > >>>> >
> > >>>> > I don't think we should do this, the drivers should work with and
> > >>>> > without
> > >>>> > dma. This just needs to be added to the omap2plus_defconfig.
> > >>>> >
> > >>>> Well this was not decided based on any DMA CONFIG option before for
> > >>>> the subject drivers. It is already by default enabled if the DMA is
> > >>>> supported
> > >>>> by the driver IP. There is a possibility to disable it from driver
> > >>>> platform/dt
> > >>>> data so that still remains.
> > >>>
> > >>> I think it should rather be that if the driver is broken and does
> > >>> not work
> > >>> without DMA, it should have depends on CONFIG_DMA_OMAP.
> > >>>
> > >> I can confirm that omap MMC can't work without DMA; polled mode is
> > >> not
> > >> supported / implemented.
> > >
> > > Same case for SPI driver as well. It uses DMA for everything except
> > > the cases
> > > where DMA doesn't make sense like 1 byte/2 byte etc. And its not
> > > configurable,
> > >
> > > At least considering this, it is better we do this per driver than
> > > enabling
> > > it at SOC config.
> > >
> > > Regards
> > > Santosh
> > > --
> >
> > Hi Santosh,
> >
> > And what about enabling it at the SoC config level but making the
> > drivers dependant on CONFIG_DMADEVICES and CONFIG_DMA_OMAP? If you
> > agree I can send something like this in two different patches (one for
> > the omap2plus_defconfig and another to make the drivers dependant on
> > the config option):
> >
> > diff --git a/arch/arm/configs/omap2plus_defconfig
> > b/arch/arm/configs/omap2plus_defconfig
> > index b152de7..e58edc3 100644
> > --- a/arch/arm/configs/omap2plus_defconfig
> > +++ b/arch/arm/configs/omap2plus_defconfig
> > @@ -193,6 +193,8 @@ CONFIG_MMC_OMAP_HS=y
> >  CONFIG_RTC_CLASS=y
> >  CONFIG_RTC_DRV_TWL92330=y
> >  CONFIG_RTC_DRV_TWL4030=y
> > +CONFIG_DMADEVICES=y
> > +CONFIG_DMA_OMAP=y
> >  CONFIG_EXT2_FS=y
> >  CONFIG_EXT3_FS=y
> >  # CONFIG_EXT3_FS_XATTR is not set
>
> above has been merged, 89269ef1f0abc72c551198123e19cd4edfd43cf4
> but I am missing the patches below in mainline (3.6-rc3) -- what happened?
>
> as Javier pointed out in https://patchwork.kernel.org/patch/1203391/,
> MMC is broken support e.g. on beagleboard unless DMA_OMAP is defined
>
> I suggest to take below patches and help to avoid some extra gray hair for
> people looking for a fix for non-booting beagleboards
>
May be I am missing something, but why you would need below patch
for beagle with "89269ef1f0abc72c551198123e19cd4edfd43cf4" commit
enabling the DMA_OMAP for all OMAP boards.

Regards
Santosh


From sebastian.hesselbarth at gmail.com  Fri Aug 24 03:14:15 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 24 Aug 2012 09:14:15 +0200
Subject: [PATCH 1/1] clk: add DT support for clock gating control
In-Reply-To: <1345782559.20538.22.camel@gitbox>
References: <1341767726-25630-1-git-send-email-sebastian.hesselbarth@googlemail.com>
 <20120824023135.4547.2534@nucleus> <1345782559.20538.22.camel@gitbox>
Message-ID: <503729C7.8040508@gmail.com>

On 08/24/2012 06:29 AM, Tony Prisk wrote:
> On Thu, 2012-08-23 at 19:31 -0700, Mike Turquette wrote:
>> Quoting Sebastian Hesselbarth (2012-07-08 10:15:26)
>>> This patch adds support for using clock gates (clk-gate) from DT based
>>> on Rob Herrings DT clk binding support for 3.6.
>>>
>>> It adds a helper function to clk-gate to allocate all resources required by
>>> a set of individual clock gates, i.e. register base address and lock. Each
>>> clock gate is described as a child of the clock-gating-control in DT and
>>> also created by the helper function.
>>>
>> Thanks for submitting this.  I'd prefer for Rob or someone with a more vested
>> interest in DT to review your binding.  I have some comments on the code below.

Mike, Tony,

thanks for reviewing this, I didn't even remember submitting it ;)

>> <snip>
>>> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
>>> +
>>> +       lockp = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
>>> +       if (!lockp) {
>>> +               pr_debug("%s: unable to allocate spinlock for %s\n",
>>> +                        __func__, np->full_name);
>>> +               return;
>>> +       }
>>> +
>>> +       spin_lock_init(lockp);
>>
>> The spinlocks for the basic clock types have always been optional.  This
>> code should reflect that and not assume the spinlock.
>>
>> Also I wonder if the assumption is true that a single spinlock
>> corresponding to a device_node is always the right thing for every
>> platform.  What about a 32-bit register that contains some gating bits
>> and a 3-bit wide field for a mux which we perform read-modify-write
>> operations on?
>>
>> You'll have to pardon my DT ignorance.  My concerns above may be totally
>> crazy with respect to DT.
>
> This also requires you to split your gated clocks in seperate nodes by
> register if you don't want unrelated clocks locking each other out.
> Also, you need a method of 'sharing' the lock outside of the gated-clock
> for use by other clock types that may share the same register.

The clock-gatining-control was inspired by a single 32b register that only
has clock gating bits. Some weeks of more insight into kernel code and DT,
I agree to do this differently.

> Are you assuming that all gated-clocks will be contained within a parent
> node with:
> #address-cells =<1>;
> #size-cells =<1>;
> with no other types of clocks? This generally isn't how people are
> writing their device tree files.
>
> Looking through the current dts files, the platforms that are using
> clocks to any real degree are using address=1, size=0.
> The only ones I see with 1/1 are only defining a fixed-clock and don't
> use the reg property anyway so could just as well be 1/0.
>
> It might be better to pass the bit field as a separate property rather
> than requiring people change their reg property to suit.
>
> myclock {
> 	reg =<0x0120>;
> 	enable-bit =<22>;
> };

Actually, today I would rather have some platform specific node for the
clock gating register and don't name each individual clock but only use
the clocks phandle to sort out the corresponding bit.

cgc: clock-gating-control {
	compatible = "marvell,orion-clkctrl";
	reg = <0x12340 0x8>;
	#clock-cells = <1>;
};

some_device: gateable-device {
	...
	clocks = <&cgc 13>;
};

The platform specific node will take care of all requirements like
spinlock or not. Maybe there will have to be a property to mask out
reserved bits in the 32b register or maybe I can assume that reserved
bits do no harm if set.

Sebastian


From linux at prisktech.co.nz  Fri Aug 24 03:14:18 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 24 Aug 2012 19:14:18 +1200
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <CABjd4Yxxf5XDc6gs0WABZgF3SOd89J7CfjsU9uitOg4qpQ4WEQ@mail.gmail.com>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de> <1345758702.2061.6.camel@gitbox>
 <201208240540.12316.arnd@arndb.de> <1345787536.23177.3.camel@gitbox>
 <CABjd4Yxxf5XDc6gs0WABZgF3SOd89J7CfjsU9uitOg4qpQ4WEQ@mail.gmail.com>
Message-ID: <1345792458.23550.0.camel@gitbox>

On Fri, 2012-08-24 at 09:54 +0400, Alexey Charkov wrote:
> 2012/8/24 Tony Prisk <linux at prisktech.co.nz>:
> > On Fri, 2012-08-24 at 05:40 +0000, Arnd Bergmann wrote:
> >> On Thursday 23 August 2012, Tony Prisk wrote:
> >> > I was about to say that if Mike has any issues with the driver that I
> >> > can fix the patch conflict at the same time, but I just realised that
> >> > its more work than I originally thought :)
> >> >
> >> > I was going to move the arch-vt8500 part of the clocks patch back into
> >> > the clocks patch - but that will just move the issue from arm-soc to
> >> > clocks because Mike's branch won't have the arch-vt8500 patch so the
> >> > patch will fail.
> >>
> >> But that's ok, because without the arch-v8500 part, nothing uses
> >> the vt8500-clock driver, so nothing breaks. You can introduce broken
> >> code in the meantime as long as it's impossible to enable and it will
> >> work afterwards.
> >>
> >>       Arnd
> >
> > You lost me a little bit there :)
> > If it stays as is now, the arch-vt8500 patch will introduce an
> > unresolved symbol.
> > If I move the clock code from the arch-vt8500 patch to the clock patch,
> > then the clock patch won't apply because it needs the arch-vt8500 patch
> > first and Mike won't have that patch, but it would be fine if both
> > patches went in via your tree.
> 
> Why don't you add a #define in the first patch that makes your
> to-be-unresolved symbol a no-op and then drop it within the clock
> patch?
> 
> Best,
> Alexey
> 
I knew we kept you around for a reason :)

Cheers,
Tony P



From clemens at ladisch.de  Fri Aug 24 03:15:00 2012
From: clemens at ladisch.de (Clemens Ladisch)
Date: Fri, 24 Aug 2012 09:15:00 +0200
Subject: [alsa-devel] [PATCH] ASoC: samsung dma - prepare dma in
 start/resume trigger path
In-Reply-To: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
Message-ID: <503729F4.5090805@ladisch.de>

Dylan Reid wrote:
> On suspend all dma transactions are terminated (by the stop/suspend
> trigger calling ops->stop), they need to be set up again during resume.
> Move the prepare op to the start/resume/unpause trigger path so that dma
> and audio will restart on resume/unpause.

TRIGGER_RESUME must restart the stream at the buffer position at which
it was suspended.  If the driver is not capable of that, it must not
support TRIGGER_SUSPEND/RESUME in the first place (i.e., remove
SNDRV_PCM_INFO_RESUME).


Regards,
Clemens


From linux at prisktech.co.nz  Fri Aug 24 03:18:12 2012
From: linux at prisktech.co.nz (Tony Prisk)
Date: Fri, 24 Aug 2012 19:18:12 +1200
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <CABjd4Yxxf5XDc6gs0WABZgF3SOd89J7CfjsU9uitOg4qpQ4WEQ@mail.gmail.com>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
 <201208231322.23077.arnd@arndb.de> <1345758702.2061.6.camel@gitbox>
 <201208240540.12316.arnd@arndb.de> <1345787536.23177.3.camel@gitbox>
 <CABjd4Yxxf5XDc6gs0WABZgF3SOd89J7CfjsU9uitOg4qpQ4WEQ@mail.gmail.com>
Message-ID: <1345792692.23550.3.camel@gitbox>

On Fri, 2012-08-24 at 09:54 +0400, Alexey Charkov wrote:
> 2012/8/24 Tony Prisk <linux at prisktech.co.nz>:
> > On Fri, 2012-08-24 at 05:40 +0000, Arnd Bergmann wrote:
> >> On Thursday 23 August 2012, Tony Prisk wrote:
> >> > I was about to say that if Mike has any issues with the driver that I
> >> > can fix the patch conflict at the same time, but I just realised that
> >> > its more work than I originally thought :)
> >> >
> >> > I was going to move the arch-vt8500 part of the clocks patch back into
> >> > the clocks patch - but that will just move the issue from arm-soc to
> >> > clocks because Mike's branch won't have the arch-vt8500 patch so the
> >> > patch will fail.
> >>
> >> But that's ok, because without the arch-v8500 part, nothing uses
> >> the vt8500-clock driver, so nothing breaks. You can introduce broken
> >> code in the meantime as long as it's impossible to enable and it will
> >> work afterwards.
> >>
> >>       Arnd
> >
> > You lost me a little bit there :)
> > If it stays as is now, the arch-vt8500 patch will introduce an
> > unresolved symbol.
> > If I move the clock code from the arch-vt8500 patch to the clock patch,
> > then the clock patch won't apply because it needs the arch-vt8500 patch
> > first and Mike won't have that patch, but it would be fine if both
> > patches went in via your tree.
> 
> Why don't you add a #define in the first patch that makes your
> to-be-unresolved symbol a no-op and then drop it within the clock
> patch?
> 
> Best,
> Alexey
> 
Actually - that doesn't resolve the problem unless it all goes in via
the same tree still because the clock patch can only drop the #define if
the arch-vt8500 patch exists still - same as problem #2 I mentioned.

If the clock patch goes via Mikes tree he will need the arch-vt8500
patch as well - don't think it can be avoided.

Still easier to send the whole lot via arm-soc, then at least we can
resolve the patch conflicts without having to apply the patches twice.

Regards
Tony P



From shawn.guo at linaro.org  Fri Aug 24 03:21:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 15:21:05 +0800
Subject: [PATCH 1/2] imx6q: Configure the pwm node for pinmux support
In-Reply-To: <1345735959-12964-2-git-send-email-hachimi.samir@gmail.com>
References: <1345735959-12964-2-git-send-email-hachimi.samir@gmail.com>
Message-ID: <20120824072102.GB31998@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 05:32:38PM +0200, hachimi.samir at gmail.com wrote:
> From: Samir Hachimi <hachimi.samir at gmail.com>
> 
>  Add the pinmux support for pwm.
>  Several pin can be set to PwmO for the same Pwm. This configuration set all
>  of them when enabled.

No, not at all.  See more below.

> 
> Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   42 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 42 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index fd57079..c913b99 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -248,23 +248,35 @@
>  			};
>  
>  			pwm at 02080000 { /* PWM1 */
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_pwm1_1>;
>  				reg = <0x02080000 0x4000>;
>  				interrupts = <0 83 0x04>;
> +				status = "disabled";
>  			};
>  
>  			pwm at 02084000 { /* PWM2 */
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_pwm2_1>;
>  				reg = <0x02084000 0x4000>;
>  				interrupts = <0 84 0x04>;
> +				status = "disabled";
>  			};
>  
>  			pwm at 02088000 { /* PWM3 */
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_pwm3_1>;
>  				reg = <0x02088000 0x4000>;
>  				interrupts = <0 85 0x04>;
> +				status = "disabled";
>  			};
>  
>  			pwm at 0208c000 { /* PWM4 */
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_pwm4_1>;
>  				reg = <0x0208c000 0x4000>;
>  				interrupts = <0 86 0x04>;
> +				status = "disabled";
>  			};
>  
>  			flexcan at 02090000 { /* CAN1 */
> @@ -559,6 +571,36 @@
>  					};
>  				};
>  
> +				pwm1 {
> +				     	pinctrl_pwm1_1: pwm1grp-1 {
> +						fsl,pins = <1543 0x80000000	/* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
> +							    574 0x80000000      /* MX6Q_PAD_DISPO_DAT8__PWM1_PWMO */
> +							    971 0x80000000>;	/* MX6Q_PAD_GPIO_9__PWM1_PWMO */
> +					};

It really should be something like the below.

				     	pinctrl_pwm1_1: pwm1grp-1 {
						fsl,pins = <
							1543 0x80000000	/* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
						>;
					};


				     	pinctrl_pwm1_2: pwm1grp-2 {
						fsl,pins = <
							574 0x80000000	/* MX6Q_PAD_DISPO_DAT8__PWM1_PWMO */
						>;
					};

				     	pinctrl_pwm1_3: pwm1grp-3 {
						fsl,pins = <
							971 0x80000000	/* MX6Q_PAD_GPIO_9__PWM1_PWMO */
						>;
					};

The rationale behind this is there are 3 possible pads on SoC imx6q,
MX6Q_PAD_SD1_DAT3, MX6Q_PAD_DISPO_DAT8 and MX6Q_PAD_GPIO_9 could be
muxed on function PWM1_PWMO.  But for particular user (board design),
only one option is needed.

You do not need to enumerate all the possible options from the
beginning.  We would add an option when it's actually used by some
board.

Regards,
Shawn

> +				};
> +
> +				pwm2 {
> +				     	pinctrl_pwm2_1: pwm2grp-1 {
> +						fsl,pins = <1557 0x80000000     /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
> +							    582 0x80000000	/* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
> +							    963 0x80000000>;	/* MX6Q_PAD_GPIO_1__PWM2_PWMO */
> +					};
> +				};
> +
> +				pwm3 {
> +				     	pinctrl_pwm3_1: pwm3grp-1 {
> +						fsl,pins = <1471 0x80000000	/* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
> +							    1526 0x80000000>;	/* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
> +					};
> +				};
> +
> +				pwm4 {
> +				     	pinctrl_pwm4_1: pwm4grp-1 {
> +						fsl,pins = <1479 0x80000000	/* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
> +							    1550 0x80000000>;	/* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
> +					};
> +				};
> +
>  				usdhc3 {
>  					pinctrl_usdhc3_1: usdhc3grp-1 {
>  						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
> -- 
> 1.7.1
> 


From anilkumar at ti.com  Fri Aug 24 03:26:09 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Fri, 24 Aug 2012 07:26:09 +0000
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
 <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA1F3B0@DBDE01.ent.ti.com>

Hi Koen,

On Fri, Aug 24, 2012 at 11:58:34, Koen Kooi wrote:
> 
> Op 24 aug. 2012, om 07:50 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
> 
> > Hi Koen,
> > 
> > On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
> >> 
> >> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
> >> 
> >>> Add tps65217 regulator device tree data to AM335x-Bone by adding
> >>> regulator consumers with tightened constraints and regulator-name.
> >>> TPS65217 regulator handle can be obtained by using this regulator
> >>> name.
> >>> 
> >>> This patch also add I2C node with I2C frequency and tps65217 PMIC
> >>> I2C slave address.
> >>> 
> >>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> >> 
> >> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?
> > 
> > Use this repo to test on beaglebone
> > https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl
> > 
> > This wiki talks about how to build and use?
> > https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree
> > 
> > Note: Enable tps65217 regulator in kernel config.
> 
> I used that repo and as a seperate test I rebased that to latest mainline, same thing: as soon as I turn on the TPS in the .config it crashes on boot. Is the pinctrl repo the *exact* repo you used to test the patches on beaglebone?

I tested on latest mainline after merging to
am335x-upstream-staging-pinctrl (voltage also changing)

Can you share your .config and uImage?

My config details:- (After merge)
1. omap2plus_defconfig
2. Enable tps65217 MFD driver
3. Enable tps65217 regulator driver

Thanks
AnilKumar


From balbi at ti.com  Fri Aug 24 03:25:11 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 24 Aug 2012 10:25:11 +0300
Subject: [PATCH] MMC: OMAP MSDI: fix broken PIO mode
In-Reply-To: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com>
References: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com>
Message-ID: <20120824072509.GC3334@arwen.pp.htv.fi>

Hi,

On Fri, Aug 24, 2012 at 06:00:18AM +0000, Paul Walmsley wrote:
> 
> After commit 26b88520b80695a6fa5fd95b5d97c03f4daf87e0 ("mmc:
> omap_hsmmc: remove private DMA API implementation"), the Nokia N800
> here stopped booting:
> 
> [    2.086181] Waiting for root device /dev/mmcblk0p1...
> [    2.324066] Unhandled fault: imprecise external abort (0x406) at 0x00000000
> [    2.331451] Internal error: : 406 [#1] ARM
> [    2.335784] Modules linked in:
> [    2.339050] CPU: 0    Not tainted  (3.6.0-rc3 #60)
> [    2.344146] PC is at default_idle+0x28/0x30
> [    2.348602] LR is at trace_hardirqs_on_caller+0x15c/0x1b0
> 
> ...
> 
> This turned out to be due to memory corruption caused by long-broken
> PIO code in drivers/mmc/host/omap.c.  (Previously, this driver had
> been using DMA; but the above commit caused the MMC driver to fall
> back to PIO mode with an unmodified Kconfig.)
> 
> The PIO code, added with the rest of the driver in commit
> 730c9b7e6630f786fcec026fb11d2e6f2c90fdcb ("[MMC] Add OMAP MMC host
> driver"), confused bytes with 16-bit words.  This bug caused memory
> located after the PIO transfer buffer to be corrupted with transfers
> larger than 32 bytes.  The driver also did not increment the buffer
> pointer after the transfer occurred.  This bug resulted in data
> corruption during any transfer larger than 64 bytes.
> 
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Juha Yrj?l? <juha.yrjola at nokia.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Carlos Aguiar <carlos.aguiar at indt.org.br>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>

this looks good to me, though I don't have how to test. FWIW:

Reviewed-by: Felipe Balbi <balbi at ti.com>

> ---
>  drivers/mmc/host/omap.c |   14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
> index 50e08f0..a5999a7 100644
> --- a/drivers/mmc/host/omap.c
> +++ b/drivers/mmc/host/omap.c
> @@ -668,7 +668,7 @@ mmc_omap_clk_timer(unsigned long data)
>  static void
>  mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
>  {
> -	int n;
> +	int n, nwords;
>  
>  	if (host->buffer_bytes_left == 0) {
>  		host->sg_idx++;
> @@ -678,15 +678,23 @@ mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
>  	n = 64;
>  	if (n > host->buffer_bytes_left)
>  		n = host->buffer_bytes_left;
> +
> +	nwords = n / 2;
> +	nwords += n & 1; /* handle odd number of bytes to transfer */
> +
>  	host->buffer_bytes_left -= n;
>  	host->total_bytes_left -= n;
>  	host->data->bytes_xfered += n;
>  
>  	if (write) {
> -		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
> +		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
> +			      host->buffer, nwords);
>  	} else {
> -		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
> +		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
> +			     host->buffer, nwords);
>  	}
> +
> +	host->buffer += nwords;
>  }
>  
>  static inline void mmc_omap_report_irq(u16 status)
> -- 
> 1.7.10.4


-- 
balbi
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From shawn.guo at linaro.org  Fri Aug 24 03:30:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 15:30:04 +0800
Subject: [PATCH 2/2] imx6q: Set pwm control register during enable and
 config call
In-Reply-To: <1345735959-12964-3-git-send-email-hachimi.samir@gmail.com>
References: <1345735959-12964-3-git-send-email-hachimi.samir@gmail.com>
Message-ID: <20120824073002.GC31998@S2101-09.ap.freescale.net>

On Thu, Aug 23, 2012 at 05:32:39PM +0200, hachimi.samir at gmail.com wrote:
> From: Samir Hachimi <hachimi.samir at gmail.com>
> 
> Bind pwm node with driver.
> Activate stop_enable mode when imx_pwm_config and set enable bit in pwm
> CR register during imx_pwm_enable.
> 
> Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>

You should use same one email address for author/From: and
Signed-off-by.

> ---
>  arch/arm/boot/dts/imx6q.dtsi  |    8 ++++++++
>  arch/arm/mach-imx/clk-imx6q.c |    4 ++++
>  drivers/pwm/pwm-imx.c         |   34 +++++++++++++++++++++++-----------
>  3 files changed, 35 insertions(+), 11 deletions(-)

The patch should be split into two, one for arch/arm/ part, and the
other for drivers/pwm part.  The arch/arm/ part will go via arm-soc
tree, while drivers/pwm part should go via pwm tree.

See following info from MAINTAINERS file for drivers/pwm part.

PWM SUBSYSTEM
M:      Thierry Reding <thierry.reding at avionic-design.de>
L:      linux-kernel at vger.kernel.org
S:      Maintained
W:      http://gitorious.org/linux-pwm
T:      git git://gitorious.org/linux-pwm/linux-pwm.git
F:      Documentation/pwm.txt
F:      Documentation/devicetree/bindings/pwm/
F:      include/linux/pwm.h
F:      include/linux/of_pwm.h
F:      drivers/pwm/


> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index c913b99..7ce9dc1 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -248,6 +248,8 @@
>  			};
>  
>  			pwm at 02080000 { /* PWM1 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_pwm1_1>;
>  				reg = <0x02080000 0x4000>;
> @@ -256,6 +258,8 @@
>  			};
>  
>  			pwm at 02084000 { /* PWM2 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_pwm2_1>;
>  				reg = <0x02084000 0x4000>;
> @@ -264,6 +268,8 @@
>  			};
>  
>  			pwm at 02088000 { /* PWM3 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_pwm3_1>;
>  				reg = <0x02088000 0x4000>;
> @@ -272,6 +278,8 @@
>  			};
>  
>  			pwm at 0208c000 { /* PWM4 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&pinctrl_pwm4_1>;
>  				reg = <0x0208c000 0x4000>;
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index ea89520..057740b 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -430,6 +430,10 @@ int __init mx6q_clocks_init(void)
>  	clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
>  	clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
>  	clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
> +	clk_register_clkdev(clk[pwm1], "pwm", "2080000.pwm");
> +	clk_register_clkdev(clk[pwm2], "pwm", "2084000.pwm");
> +	clk_register_clkdev(clk[pwm3], "pwm", "2088000.pwm");
> +	clk_register_clkdev(clk[pwm4], "pwm", "208c000.pwm");

We are moving clock lookup into device tree, so these changes are not
welcomed at this point.

>  	clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
>  	clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
>  	clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index 2a0b353..0b13f34 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -32,6 +33,7 @@
>  #define MX3_PWMSAR                0x0C    /* PWM Sample Register */
>  #define MX3_PWMPR                 0x10    /* PWM Period Register */
>  #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
> +#define MX3_PWMCR_STOPEN		(1 << 25)
>  #define MX3_PWMCR_DOZEEN                (1 << 24)
>  #define MX3_PWMCR_WAITEN                (1 << 23)
>  #define MX3_PWMCR_DBGEN			(1 << 22)
> @@ -68,25 +70,21 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  		prescale = period_cycles / 0x10000 + 1;
>  
>  		period_cycles /= prescale;
> -		c = (unsigned long long)period_cycles * duty_ns;
> -		do_div(c, period_ns);
> -		duty_cycles = c;
>  
> -		/*
> -		 * according to imx pwm RM, the real period value should be
> -		 * PERIOD value in PWMPR plus 2.
> +		/* the chip documentation says the counter counts up to
> +		 * period_cycles + 1 and then is reset to 0, so the
> +		 *  actual period of the PWM wave is period_cycles + 2
>  		 */
> -		if (period_cycles > 2)
> -			period_cycles -= 2;
> -		else
> -			period_cycles = 0;
> +		c = (unsigned long long)(period_cycles + 2) * duty_ns;
> +		do_div(c, period_ns);
> +		duty_cycles = c;
>  
>  		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
>  		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
>  
>  		cr = MX3_PWMCR_PRESCALER(prescale) |
>  			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
> -			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
> +			MX3_PWMCR_DBGEN | MX3_PWMCR_STOPEN;
>  
>  		if (cpu_is_mx25())
>  			cr |= MX3_PWMCR_CLKSRC_IPG;
> @@ -124,6 +122,7 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
>  	struct imx_chip *imx = to_imx_chip(chip);
> +	unsigned long reg;
>  	int rc = 0;
>  
>  	if (!imx->clk_enabled) {
> @@ -131,6 +130,11 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  		if (!rc)
>  			imx->clk_enabled = 1;
>  	}
> +
> +	reg = readl(imx->mmio_base + MX3_PWMCR);
> +	reg |= MX3_PWMCR_EN;
> +	writel(reg, imx->mmio_base + MX3_PWMCR);
> +
>  	return rc;
>  }
>  
> @@ -206,9 +212,15 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
>  	return pwmchip_remove(&imx->chip);
>  }
>  
> +static const struct of_device_id mxc_pwm_dt_ids[] = {
> +	{ .compatible = "fsl,imx6q-pwm", },

The driver really needs a cleanup before we add device tree support for
it.  For example, all these cpu_is_xxx stuff need to go and use
device_id instead.

Regards,
Shawn

> +	{ /* sentinel */ }
> +};
> +
>  static struct platform_driver imx_pwm_driver = {
>  	.driver		= {
>  		.name	= "mxc_pwm",
> +		.of_match_table = of_match_ptr(mxc_pwm_dt_ids),
>  	},
>  	.probe		= imx_pwm_probe,
>  	.remove		= __devexit_p(imx_pwm_remove),
> -- 
> 1.7.1
> 


From sbkim73 at samsung.com  Fri Aug 24 03:41:32 2012
From: sbkim73 at samsung.com (Sangbeom Kim)
Date: Fri, 24 Aug 2012 16:41:32 +0900
Subject: [alsa-devel] [PATCH] ASoC: samsung dma - prepare dma in
 start/resume trigger path
In-Reply-To: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
Message-ID: <00df01cd81cb$e21d2f00$a6578d00$@com>

Hi!

On Thu, Aug 24, 2012 at 5:51 AM, Dylan Reid wrote:
> On suspend all dma transactions are terminated (by the stop/suspend
> trigger calling ops->stop), they need to be set up again during resume.
> Move the prepare op to the start/resume/unpause trigger path so that dma
> and audio will restart on resume/unpause.
Do you mean that currently, suspend/resume can't be supported?

Thanks,
Sangbeom.



From pmeerw at pmeerw.net  Fri Aug 24 03:51:15 2012
From: pmeerw at pmeerw.net (Peter Meerwald)
Date: Fri, 24 Aug 2012 09:51:15 +0200 (CEST)
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
References: <1342485005-5178-1-git-send-email-javier@dowhile0.org>
 <CAMQu2gxaF8K78puE84+=8VJLbsdtdD97ww81XJxG6sCtYTYXww@mail.gmail.com>
 <CABxcv=nsmeVLspzXERYXebmPaNO6rKCsVnak7dMtvGjiYH4vOw@mail.gmail.com>
 <20120718065951.GH6522@atomide.com>
 <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
Message-ID: <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>

On Fri, 24 Aug 2012, Shilimkar, Santosh wrote:

> On Fri, Aug 24, 2012 at 2:30 AM, Peter Meerwald <pmeerw at pmeerw.net> wrote:
> >
> > On Wed, 18 Jul 2012, Javier Martinez Canillas wrote:
> >
> > > On Wed, Jul 18, 2012 at 10:36 AM, Shilimkar, Santosh
> > > <santosh.shilimkar at ti.com> wrote:
> > > > On Wed, Jul 18, 2012 at 1:14 PM, S, Venkatraman <svenkatr at ti.com>
> > > > wrote:
> > > >> On Wed, Jul 18, 2012 at 12:40 PM, Tony Lindgren <tony at atomide.com>
> > > >> wrote:
> > > >>> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120718 00:09]:
> > > >>>> On Wed, Jul 18, 2012 at 12:29 PM, Tony Lindgren <tony at atomide.com>
> > > >>>> wrote:
> > > >>>> > * Javier Martinez Canillas <javier at dowhile0.org> [120716 23:56]:
> > > >>>> >> On Tue, Jul 17, 2012 at 8:45 AM, Shilimkar, Santosh
> > > >>>> >> <santosh.shilimkar at ti.com> wrote:
> > > >>>> >> > Hi,
> > > >>>> >> >
> > > >>>> >> > On Tue, Jul 17, 2012 at 6:00 AM, Javier Martinez Canillas
> > > >>>> >> > <javier at dowhile0.org> wrote:
> > > >>>> >> >> The OMAP MMC and OMAP High Speed MMC hosts now use entirely
> > > >>>> >> >> the DMA
> > > >>>> >> >> engine API instead of the previous private DMA API
> > > >>>> >> >> implementation.
> > > >>>> >> >>
> > > >>>> >> >> So, if the kernel is built with support for any of these
> > > >>>> >> >> hosts but it
> > > >>>> >> >> doesn't support DMA devices nor OMAP DMA support, it fails
> > > >>>> >> >> when trying
> > > >>>> >> >> to obtain a DMA channel which leads to the following error on
> > > >>>> >> >> an OMAP3
> > > >>>> >> >> IGEPv2 Rev.C board (and probably on most OMAP boards with MMC
> > > >>>> >> >> support):
> > > >>>> >> >>
> > > >>>> >> >> [ 2.199981] omap_hsmmc omap_hsmmc.1: unable to obtain RX DMA
> > > >>>> >> >> engine channel 48
> > > >>>> >> >> [    2.215087] omap_hsmmc omap_hsmmc.0: unable to obtain RX
> > > >>>> >> >> DMA engine channel 62
> > > >>>> >> >>
> > > >>>> >> >> selecting automatically CONFIG_DMADEVICES and CONFIG_DMA_OMAP
> > > >>>> >> >> solves it.
> > > >>>> >> >>
> > > >>>> >> >> Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
> > > >>>> >> >> ---
> > > >>>> >> > Considering, we are updating drivers to select the DMA engine,
> > > >>>> >> > can you
> > > >>>> >> > also include
> > > >>>> >> > "drivers/spi/spi-omap2-mcspi.c" which is also updated for DMA
> > > >>>> >> > engine.
> > > >>>> >> >
> > > >>>> >> > Regards
> > > >>>> >> > Santosh
> > > >>>> >>
> > > >>>> >> Hi Santosh,
> > > >>>> >>
> > > >>>> >> Ok, I'll send a v2 now which includes spi-omap2-mcspi then.
> > > >>>> >
> > > >>>> > I don't think we should do this, the drivers should work with and
> > > >>>> > without
> > > >>>> > dma. This just needs to be added to the omap2plus_defconfig.
> > > >>>> >
> > > >>>> Well this was not decided based on any DMA CONFIG option before for
> > > >>>> the subject drivers. It is already by default enabled if the DMA is
> > > >>>> supported
> > > >>>> by the driver IP. There is a possibility to disable it from driver
> > > >>>> platform/dt
> > > >>>> data so that still remains.
> > > >>>
> > > >>> I think it should rather be that if the driver is broken and does
> > > >>> not work
> > > >>> without DMA, it should have depends on CONFIG_DMA_OMAP.
> > > >>>
> > > >> I can confirm that omap MMC can't work without DMA; polled mode is
> > > >> not
> > > >> supported / implemented.
> > > >
> > > > Same case for SPI driver as well. It uses DMA for everything except
> > > > the cases
> > > > where DMA doesn't make sense like 1 byte/2 byte etc. And its not
> > > > configurable,
> > > >
> > > > At least considering this, it is better we do this per driver than
> > > > enabling
> > > > it at SOC config.
> > > >
> > > > Regards
> > > > Santosh
> > > > --
> > >
> > > Hi Santosh,
> > >
> > > And what about enabling it at the SoC config level but making the
> > > drivers dependant on CONFIG_DMADEVICES and CONFIG_DMA_OMAP? If you
> > > agree I can send something like this in two different patches (one for
> > > the omap2plus_defconfig and another to make the drivers dependant on
> > > the config option):
> > >
> > > diff --git a/arch/arm/configs/omap2plus_defconfig
> > > b/arch/arm/configs/omap2plus_defconfig
> > > index b152de7..e58edc3 100644
> > > --- a/arch/arm/configs/omap2plus_defconfig
> > > +++ b/arch/arm/configs/omap2plus_defconfig
> > > @@ -193,6 +193,8 @@ CONFIG_MMC_OMAP_HS=y
> > >  CONFIG_RTC_CLASS=y
> > >  CONFIG_RTC_DRV_TWL92330=y
> > >  CONFIG_RTC_DRV_TWL4030=y
> > > +CONFIG_DMADEVICES=y
> > > +CONFIG_DMA_OMAP=y
> > >  CONFIG_EXT2_FS=y
> > >  CONFIG_EXT3_FS=y
> > >  # CONFIG_EXT3_FS_XATTR is not set
> >
> > above has been merged, 89269ef1f0abc72c551198123e19cd4edfd43cf4
> > but I am missing the patches below in mainline (3.6-rc3) -- what happened?
> >
> > as Javier pointed out in https://patchwork.kernel.org/patch/1203391/,
> > MMC is broken support e.g. on beagleboard unless DMA_OMAP is defined
> >
> > I suggest to take below patches and help to avoid some extra gray hair for
> > people looking for a fix for non-booting beagleboards
> >
> May be I am missing something, but why you would need below patch
> for beagle with "89269ef1f0abc72c551198123e19cd4edfd43cf4" commit
> enabling the DMA_OMAP for all OMAP boards.

the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in 
omap2plus_defconfig; this does not help people updating the kernel while 
keeping the config, nor does it help people in configuring the kernel

there is a dependency (at least for beagleboard) between MMC_OMAP_HS and 
DMA_OMAP, and I think this should be made explicit

regards, p.

-- 

Peter Meerwald
+43-664-2444418 (mobile)


From dgreid at chromium.org  Fri Aug 24 03:52:10 2012
From: dgreid at chromium.org (Dylan Reid)
Date: Fri, 24 Aug 2012 00:52:10 -0700
Subject: [alsa-devel] [PATCH] ASoC: samsung dma - prepare dma in
 start/resume trigger path
In-Reply-To: <00df01cd81cb$e21d2f00$a6578d00$@com>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
 <00df01cd81cb$e21d2f00$a6578d00$@com>
Message-ID: <CAEUnVG58NPNKuf_PRyBEegYnH95dkTN81PGZGYxDt41jhH2uaQ@mail.gmail.com>

On Fri, Aug 24, 2012 at 12:41 AM, Sangbeom Kim <sbkim73 at samsung.com> wrote:
> Hi!
>
> On Thu, Aug 24, 2012 at 5:51 AM, Dylan Reid wrote:
>> On suspend all dma transactions are terminated (by the stop/suspend
>> trigger calling ops->stop), they need to be set up again during resume.
>> Move the prepare op to the start/resume/unpause trigger path so that dma
>> and audio will restart on resume/unpause.
> Do you mean that currently, suspend/resume can't be supported?

Yes. Currently, if I suspend while playing, after resume it won't work
until I close and reopen the device.  the call to snd_pcm_resume is
not indicating an error, but a write error comes from snd_pcm_write a
little later.

The suspend trigger calls ops->stop, which in turn sends
DMA_TERMINATE_ALL to the pl330.  I think this causes resume's call to
ops->trigger to fail because there is nothing enqueued, but I'm pretty
new to this system.

Thanks for the help!

Dylan

>
> Thanks,
> Sangbeom.
>


From koen at dominion.thruhere.net  Fri Aug 24 03:56:30 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 24 Aug 2012 09:56:30 +0200
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <331ABD5ECB02734CA317220B2BBEABC13EA1F3B0@DBDE01.ent.ti.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
 <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F3B0@DBDE01.ent.ti.com>
Message-ID: <6C2AC14D-1CAC-4B93-910C-B7E52D3355FD@dominion.thruhere.net>


Op 24 aug. 2012, om 09:26 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:

> Hi Koen,
> 
> On Fri, Aug 24, 2012 at 11:58:34, Koen Kooi wrote:
>> 
>> Op 24 aug. 2012, om 07:50 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
>> 
>>> Hi Koen,
>>> 
>>> On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
>>>> 
>>>> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
>>>> 
>>>>> Add tps65217 regulator device tree data to AM335x-Bone by adding
>>>>> regulator consumers with tightened constraints and regulator-name.
>>>>> TPS65217 regulator handle can be obtained by using this regulator
>>>>> name.
>>>>> 
>>>>> This patch also add I2C node with I2C frequency and tps65217 PMIC
>>>>> I2C slave address.
>>>>> 
>>>>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>>>> 
>>>> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?
>>> 
>>> Use this repo to test on beaglebone
>>> https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl
>>> 
>>> This wiki talks about how to build and use?
>>> https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree
>>> 
>>> Note: Enable tps65217 regulator in kernel config.
>> 
>> I used that repo and as a seperate test I rebased that to latest mainline, same thing: as soon as I turn on the TPS in the .config it crashes on boot. Is the pinctrl repo the *exact* repo you used to test the patches on beaglebone?
> 
> I tested on latest mainline after merging to
> am335x-upstream-staging-pinctrl (voltage also changing)
> 
> Can you share your .config and uImage?

Config: https://github.com/beagleboard/kernel/blob/beaglebone-3.6/patches/configs/beaglebone

> My config details:- (After merge)
> 1. omap2plus_defconfig
> 2. Enable tps65217 MFD driver
> 3. Enable tps65217 regulator driver


I rebased onto latest mainline and refreshed the base patches from Vaibhav and I now get: 

[    0.246796] tps65217 0-0024: TPS65217 ID 0xf version 1.1

So it boots! I don't know what made it break before, but it's working now :)

regards,

Koen

From shawn.guo at linaro.org  Fri Aug 24 04:00:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 16:00:55 +0800
Subject: [PATCH 1/2] ARM: mx28: Add SPI pinmux into imx28.dtsi
In-Reply-To: <1345778742-20994-1-git-send-email-marex@denx.de>
References: <1345778742-20994-1-git-send-email-marex@denx.de>
Message-ID: <20120824080052.GD31998@S2101-09.ap.freescale.net>

On Fri, Aug 24, 2012 at 05:25:41AM +0200, Marek Vasut wrote:
> Add this SSP pin multiplexing configuration into the imx28.dtsi file.
> This covers pinmux for all four SSP ports available on the i.MX28.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx28.dtsi |   61 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 61 insertions(+)
> 
> NOTE: Shawn, I'd like to add this altogether. I have a board scheduled in my
>       queue that uses other SSP ports, so I consider it pointless to split this.

No.  Please only add the one you're using and testing with.  I do not
want to have any unneeded and untested settings there.

>       Fabio, what does MX28EVK use?
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 91b43e9..327a33f 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -507,6 +507,67 @@
>  					fsl,voltage = <1>;
>  					fsl,pull-up = <0>;
>  				};
> +
> +				spi0_pins_a: spi0 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
> +						0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
> +						0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
> +						0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
> +						0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
> +						0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
> +						0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
> +						0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
> +						0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
> +						0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
> +						0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
> +					>;

You have a SPI connection that needs so many pins?  Please note that
we already have mmc pins setup in place.

> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi1_pins_a: spi1 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x20c0 /* MX28_PAD_SSP1_SCK__SSP1_SCK */
> +						0x20d0 /* MX28_PAD_SSP1_CMD__SSP1_CMD */
> +						0x20e0 /* MX28_PAD_SSP1_DATA0__SSP1_D0 */
> +						0x20f0 /* MX28_PAD_SSP1_DATA3__SSP1_D3 */
> +					>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi2_pins_a: spi2 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
> +						0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
> +						0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
> +						0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
> +						0x2140 /* MX28_PAD_SSP2_SS1__SSP2_D4 */
> +						0x2150 /* MX28_PAD_SSP2_SS2__SSP2_D5 */
> +					>;

The SPI flash on imx28-evk uses this one but with only SS0.  So we will
probably need to have the group only define SS0 and set up the extra SS
in board's hog node, so that the group can be shared across more boards.
Or, we name the group spi2_3cs_pins_a and leave the name spi2_pins_a to
the more general case, one SS?

Regards,
Shawn

> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
> +
> +				spi3_pins_a: spi3 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */
> +						0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */
> +						0x21a0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */
> +						0x21b0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */
> +					>;
> +					fsl,drive-strength = <1>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <1>;
> +				};
>  			};
>  
>  			digctl at 8001c000 {
> -- 
> 1.7.10.4
> 


From koen at dominion.thruhere.net  Fri Aug 24 04:02:17 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 24 Aug 2012 10:02:17 +0200
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <6C2AC14D-1CAC-4B93-910C-B7E52D3355FD@dominion.thruhere.net>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
 <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F3B0@DBDE01.ent.ti.com>
 <6C2AC14D-1CAC-4B93-910C-B7E52D3355FD@dominion.thruhere.net>
Message-ID: <45D5714B-BB2C-49BB-8C5D-F69749EC324A@dominion.thruhere.net>


Op 24 aug. 2012, om 09:56 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:

> 
> Op 24 aug. 2012, om 09:26 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
> 
>> Hi Koen,
>> 
>> On Fri, Aug 24, 2012 at 11:58:34, Koen Kooi wrote:
>>> 
>>> Op 24 aug. 2012, om 07:50 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
>>> 
>>>> Hi Koen,
>>>> 
>>>> On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
>>>>> 
>>>>> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
>>>>> 
>>>>>> Add tps65217 regulator device tree data to AM335x-Bone by adding
>>>>>> regulator consumers with tightened constraints and regulator-name.
>>>>>> TPS65217 regulator handle can be obtained by using this regulator
>>>>>> name.
>>>>>> 
>>>>>> This patch also add I2C node with I2C frequency and tps65217 PMIC
>>>>>> I2C slave address.
>>>>>> 
>>>>>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>>>>> 
>>>>> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?
>>>> 
>>>> Use this repo to test on beaglebone
>>>> https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl
>>>> 
>>>> This wiki talks about how to build and use?
>>>> https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree
>>>> 
>>>> Note: Enable tps65217 regulator in kernel config.
>>> 
>>> I used that repo and as a seperate test I rebased that to latest mainline, same thing: as soon as I turn on the TPS in the .config it crashes on boot. Is the pinctrl repo the *exact* repo you used to test the patches on beaglebone?
>> 
>> I tested on latest mainline after merging to
>> am335x-upstream-staging-pinctrl (voltage also changing)
>> 
>> Can you share your .config and uImage?
> 
> Config: https://github.com/beagleboard/kernel/blob/beaglebone-3.6/patches/configs/beaglebone
> 
>> My config details:- (After merge)
>> 1. omap2plus_defconfig
>> 2. Enable tps65217 MFD driver
>> 3. Enable tps65217 regulator driver
> 
> 
> I rebased onto latest mainline and refreshed the base patches from Vaibhav and I now get: 
> 
> [    0.246796] tps65217 0-0024: TPS65217 ID 0xf version 1.1
> 
> So it boots! I don't know what made it break before, but it's working now :)

*sigh* I'm an idiot:

root at beaglebone:~# uname -a
Linux beaglebone 3.6.0-rc3-00103-gfd02083 #86 SMP Fri Aug 24 09:45:54 CEST 2012 armv7l GNU/Linux
root at beaglebone:~# zcat /proc/config.gz | grep 217
CONFIG_MFD_TPS65217=y
# CONFIG_REGULATOR_TPS65217 is not set

Will retry with regulator driver actually turned on in a bit.

From dedekind1 at gmail.com  Fri Aug 24 04:09:52 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 11:09:52 +0300
Subject: [PATCH v3] mtd: gpmi: fix the compiler warnings
In-Reply-To: <CAMiH66G+srHsfUn6eCByHMgjZXE6k7zM6qLagqBuQCzx954aOA@mail.gmail.com>
References: <1342451569.7270.11.camel@brekeke>
 <1342505642-31109-1-git-send-email-b32955@freescale.com>
 <CAMiH66G+srHsfUn6eCByHMgjZXE6k7zM6qLagqBuQCzx954aOA@mail.gmail.com>
Message-ID: <1345795792.2848.265.camel@sauron.fi.intel.com>

On Wed, 2012-08-01 at 10:27 +0800, Huang Shijie wrote:
> Hi Artem;
> Just a ping.
> 
> Please do not miss this patch.

I actually missed it, pushed now to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From bilhuang at nvidia.com  Fri Aug 24 04:23:39 2012
From: bilhuang at nvidia.com (Bill Huang)
Date: Fri, 24 Aug 2012 16:23:39 +0800
Subject: Shutdown problem in SMP system happened on Tegra20
Message-ID: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>

Hi,

When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC registers through I2C
to perform the power off sequence. Unfortunately, sometimes we'll fail to shutdown
due to I2C timeout on Tegra20. And the cause of the timeout is due to the CPU which I2C
controller IRQ affined to will have chance to be offlined without migrating all irqs affined 
to it, so the following I2C transactions will fail (no any CPU will handle that interrupt
since then).

Some snippet of the shutdown codes:

void kernel_power_off(void)
{
	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
	:
	disable_nonboot_cpus();
	:
	machine_power_off();
}

void machine_power_off(void)
{
	machine_shutdown();
	if (pm_power_off)
		pm_power_off(); /* this is where we send I2C write to shutdown */
}

void machine_shutdown(void)
{
#ifdef CONFIG_SMP
	smp_send_stop();
#endif
}

In "smp_send_stop()", it will send "IPI_CPU_STOPS" to offline other cpus except
current cpu (smp_processor_id()), however, current cpu will not always be cpu0 at
least at Tegra20, that said for example cpu1 might be the current cpu and cpu0 will
be offlined and this is the case why the I2C transaction will timeout. 

For normal case, "disable_nonboot_cpus()" call will disable all other Cpus except
cpu0, that means we won't hit the problem mentioned here since cpu0 will always be
the current cpu in the call "smp_send_stop", but the call to "disable_nonboot_cpus" 
will happen only when "CONFIG_PM_SLEEP_SMP" is enabled which is not the case for
Tegra20/Tegra30, we don't support suspend yet so this can't be enabled.

There are two known fix for this, the first one is enable suspend (ARCH_SUSPEND_POSSIBLE)
so the cpu0 will be the only online cpu while doing "machine_shutdown". The second
fix is adding call to "migrate_irqs()" in "ipi_cpu_stop" so all irqs can be migrated to
the active cpu.

Could someone familiar with the ARM SMP design help to answer my two questions?

1. Does it make sense that "smp_processor_id()" could be non-cpu0 in the call
   "smp_send_stop()"? In Tegra30 it will always be cpu0 but Tegra20 will be 50-50,
   I just can't find the magic.

2. If current cpu is not necessarily be cpu0 in the call "smp_send_stop()", then
   does it make sense to add "migrate_irqs()" in "ipi_cpu_stop()"? Or is there any
   other fix which makes more sense?

Thanks,
Bill
nvpublic


From shawn.guo at linaro.org  Fri Aug 24 04:26:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 16:26:11 +0800
Subject: [PATCH 2/2] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <1345778742-20994-2-git-send-email-marex@denx.de>
References: <1345778742-20994-1-git-send-email-marex@denx.de>
 <1345778742-20994-2-git-send-email-marex@denx.de>
Message-ID: <20120824082609.GE31998@S2101-09.ap.freescale.net>

On Fri, Aug 24, 2012 at 05:25:42AM +0200, Marek Vasut wrote:
> Update the mach-mxs machine by removing the enet_clkout(). The new
> revision of the board doesn't need that. Also, update the DTS file
> with all the new drivers pulled in the mainline recently, that is,
> SPI, LRADC, USB. Also, remove bogus AUART3.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx28-m28evk.dts |   98 +++++++++++++++++++++++++++++++++---
>  arch/arm/mach-mxs/mach-mxs.c       |    1 -
>  2 files changed, 92 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
> index 183a3fd..e418b75 100644
> --- a/arch/arm/boot/dts/imx28-m28evk.dts
> +++ b/arch/arm/boot/dts/imx28-m28evk.dts
> @@ -23,6 +23,8 @@
>  	apb at 80000000 {
>  		apbh at 80000000 {
>  			gpmi-nand at 8000c000 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
>  				status = "okay";
> @@ -62,9 +64,28 @@
>  					     &mmc0_sck_cfg>;
>  				bus-width = <8>;
>  				wp-gpios = <&gpio3 10 1>;
> +				vmmc-supply = <&reg_vddio_sd0>;
>  				status = "okay";
>  			};
>  
> +			ssp2: ssp at 80014000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx28-spi";
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&spi2_pins_a>;
> +				status = "okay";
> +
> +				flash: m25p80 at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					compatible = "m25p80";
> +					spi-max-frequency = <40000000>;
> +					m25p,fast-read;
> +					reg = <0>;
> +				};
> +			};
> +
>  			pinctrl at 80018000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&hog_pins_a>;
> @@ -72,8 +93,11 @@
>  				hog_pins_a: hog-gpios at 0 {
>  					reg = <0>;
>  					fsl,pinmux-ids = <
> +						0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
>  						0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
>  						0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
> +						0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
> +						0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
>  					>;
>  					fsl,drive-strength = <0>;
>  					fsl,voltage = <1>;
> @@ -90,6 +114,22 @@
>  					fsl,voltage = <1>;
>  					fsl,pull-up = <0>;
>  				};
> +
> +				usb0_pins_a: usb0 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <0x2152>;
> +					fsl,drive-strength = <2>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +
> +				usb1_pins_a: usb1 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <0x2142>;
> +					fsl,drive-strength = <2>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};

These two nodes should be put into imx28.dtsi.  Also, please put
a comment after the pinmux-id.

Regards,
Shawn

>  			};
>  
>  			lcdif at 80030000 {
> @@ -99,6 +139,10 @@
>  				status = "okay";
>  			};
>  
> +			lradc at 80050000 {
> +				status = "okay";
> +			};
> +
>  			can0: can at 80032000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&can0_pins_a>;
> @@ -129,6 +173,7 @@
>  			i2c0: i2c at 80058000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&i2c0_pins_a>;
> +				clock-frequency = <400000>;
>  				status = "okay";
>  
>  				sgtl5000: codec at 0a {
> @@ -157,26 +202,41 @@
>  				status = "okay";
>  			};
>  
> -			auart0: serial at 8006a000 {
> -				pinctrl-names = "default";
> -				pinctrl-0 = <&auart0_2pins_a>;
> +			usbphy0: usbphy at 8007c000 {
>  				status = "okay";
>  			};
>  
> -			auart3: serial at 80070000 {
> +			usbphy1: usbphy at 8007e000 {
> +				status = "okay";
> +			};
> +
> +			auart0: serial at 8006a000 {
>  				pinctrl-names = "default";
> -				pinctrl-0 = <&auart3_pins_a>;
> +				pinctrl-0 = <&auart0_2pins_a>;
>  				status = "okay";
>  			};
>  		};
>  	};
>  
>  	ahb at 80080000 {
> +		usb0: usb at 80080000 {
> +			vbus-supply = <&reg_usb0_vbus>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&usb0_pins_a>;
> +			status = "okay";
> +		};
> +
> +		usb1: usb at 80090000 {
> +			vbus-supply = <&reg_usb1_vbus>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&usb1_pins_a>;
> +			status = "okay";
> +		};
> +
>  		mac0: ethernet at 800f0000 {
>  			phy-mode = "rmii";
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&mac0_pins_a>;
> -			phy-reset-gpios = <&gpio3 11 0>;
>  			status = "okay";
>  		};
>  
> @@ -198,6 +258,32 @@
>  			regulator-max-microvolt = <3300000>;
>  			regulator-always-on;
>  		};
> +
> +		reg_vddio_sd0: vddio-sd0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "vddio-sd0";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio3 28 0>;
> +		};
> +
> +		reg_usb0_vbus: usb0_vbus {
> +			compatible = "regulator-fixed";
> +			regulator-name = "usb0_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 12 0>;
> +			enable-active-low;
> +		};
> +
> +		reg_usb1_vbus: usb1_vbus {
> +			compatible = "regulator-fixed";
> +			regulator-name = "usb1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 13 0>;
> +			enable-active-low;
> +		};
>  	};
>  
>  	sound {
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 8dabfe8..5ac45a1 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -241,7 +241,6 @@ static void __init imx28_evk_init(void)
>  
>  static void __init m28evk_init(void)
>  {
> -	enable_clk_enet_out();
>  	update_fec_mac_prop(OUI_DENX);
>  
>  	mxsfb_pdata.mode_list = m28evk_video_modes;
> -- 
> 1.7.10.4
> 


From hdoyu at nvidia.com  Fri Aug 24 04:29:01 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 11:29:01 +0300
Subject: [v3 0/4] ARM: dma-mapping: IOMMU atomic allocation
Message-ID: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>

Hi,

The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
region" breaks the compatibility with existing drivers. This causes
the following kernel oops(*1). That driver has called dma_pool_alloc()
to allocate memory from the interrupt context, and it hits
BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
fixes this problem with making use of the pre-allocate atomic memory
pool which DMA is using in the same way as DMA does now.

Any comment would be really appreciated.

v3:
Provide a different path for IOMMU for more clean code. (Marek)
atomic_pool is backed with struct page *pages[].
v2:
Don't modify attrs(DMA_ATTR_NO_KERNEL_MAPPING) for atomic allocation. (Marek)
Modify vzalloc (KyongHo, Minchan)
v1:
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002398.html

*1:
[    8.321343] ------------[ cut here ]------------
[    8.325971] kernel BUG at kernel/mm/vmalloc.c:1322!
[    8.333615] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[    8.339436] Modules linked in:
[    8.342496] CPU: 0    Tainted: G        W     (3.4.6-00067-g5d485f7 #67)
[    8.349192] PC is at __get_vm_area_node.isra.29+0x164/0x16c
[    8.354758] LR is at get_vm_area_caller+0x4c/0x54
[    8.359454] pc : [<c011297c>]    lr : [<c011318c>]    psr: 20000193
[    8.359458] sp : c09edca0  ip : c09ec000  fp : ae278000
[    8.370922] r10: f0000000  r9 : c011aa54  r8 : c0a26cb8
[    8.376136] r7 : 00000001  r6 : 000000d0  r5 : 20000008  r4 : c09edca0
[    8.382651] r3 : 00010000  r2 : 20000008  r1 : 00000001  r0 : 00001000
[    8.389166] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    8.396549] Control: 10c5387d  Table: ad98c04a  DAC: 00000015
....
[    9.169162] dfa0: 412fc099 c09ec000 00000000 c000fdd8 c06df1e4 c0a1b080 00000000 00000000
[    9.177329] dfc0: c0a235cc 8000406a 00000000 c0986818 ffffffff ffffffff c0986404 00000000
[    9.185497] dfe0: 00000000 c09bb070 10c5387d c0a19c58 c09bb064 80008044 00000000 00000000
[    9.193673] [<c011297c>] (__get_vm_area_node.isra.29+0x164/0x16c) from [<c011318c>] (get_vm_area_caller+0x4c/0x54)
[    9.204022] [<c011318c>] (get_vm_area_caller+0x4c/0x54) from [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc)
[    9.214276] [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc) from [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8)
[    9.224795] [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8) from [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8)
[    9.235309] [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8) from [<c011ab60>] (dma_pool_alloc+0x80/0x170)
[    9.245304] [<c011ab60>] (dma_pool_alloc+0x80/0x170) from [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c)
[    9.254344] [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c) from [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8)
[    9.263467] [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8) from [<c03cc140>] (tegra_ep_queue+0x154/0x33c)
[    9.272592] [<c03cc140>] (tegra_ep_queue+0x154/0x33c) from [<c03dd5b4>] (composite_setup+0x364/0x6d4)
[    9.281804] [<c03dd5b4>] (composite_setup+0x364/0x6d4) from [<c03dd9dc>] (android_setup+0xb8/0x14c)
[    9.290843] [<c03dd9dc>] (android_setup+0xb8/0x14c) from [<c03cd144>] (setup_received_irq+0xbc/0x270)
[    9.300053] [<c03cd144>] (setup_received_irq+0xbc/0x270) from [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4)
[    9.309353] [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4) from [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0)
[    9.319087] [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0) from [<c00b59b4>] (handle_irq_event+0x44/0x64)
[    9.328907] [<c00b59b4>] (handle_irq_event+0x44/0x64) from [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c)
[    9.338294] [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c) from [<c00b4f14>] (generic_handle_irq+0x34/0x48)
[    9.347858] [<c00b4f14>] (generic_handle_irq+0x34/0x48) from [<c000f6f4>] (handle_IRQ+0x54/0xb4)
[    9.356637] [<c000f6f4>] (handle_IRQ+0x54/0xb4) from [<c00084b0>] (gic_handle_irq+0x2c/0x60)
[    9.365068] [<c00084b0>] (gic_handle_irq+0x2c/0x60) from [<c000e900>] (__irq_svc+0x40/0x70)
[    9.373405] Exception stack(0xc09edf10 to 0xc09edf58)
[    9.378447] df00:                                     00000000 000f4240 00000003 00000000
[    9.386615] df20: 00000000 e55bbc00 ef66f3ca 00000001 00000000 412fc099 c0abb9c8 00000000
[    9.394781] df40: 3b9ac9ff c09edf58 c027a9bc c0042880 20000113 ffffffff
[    9.401396] [<c000e900>] (__irq_svc+0x40/0x70) from [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78)
[    9.410272] [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78) from [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4)
[    9.419922] [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4) from [<c000fdd8>] (cpu_idle+0xd8/0x134)
[    9.428612] [<c000fdd8>] (cpu_idle+0xd8/0x134) from [<c0986818>] (start_kernel+0x27c/0x2cc)
[    9.436952] Code: e1a00004 e3a04000 eb002265 eaffffe0 (e7f001f2)
[    9.443038] ---[ end trace 1b75b31a2719ed24 ]---
[    9.447645] Kernel panic - not syncing: Fatal exception in interrupt


Hiroshi Doyu (4):
  ARM: dma-mapping: atomic_pool with struct page **pages
  ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
  ARM: dma-mapping: Introduce __atomic_get_pages() for
    __iommu_get_pages()
  ARM: dma-mapping: IOMMU allocates pages from atomic_pool with
    GFP_ATOMIC

 arch/arm/mm/dma-mapping.c |   90 ++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 80 insertions(+), 10 deletions(-)

-- 
1.7.5.4



From kmpark at infradead.org  Fri Aug 24 04:33:51 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 24 Aug 2012 17:33:51 +0900
Subject: [PATCH v5 1/2] ARM: Make a compile firmware conditionally
Message-ID: <20120824083351.GA25369@july>

From: Kyungmin Park <kyungmin.park at samsung.com>

Some boards can use the firmware at trustzone but others can't use this.
However we need to build it simultaneously. To address this issue,
introduce arm firmware support and use it at each board files.

e.g., In boot_secondary at mach-exynos/platsmp.c

        __raw_writel(virt_to_phys(exynos4_secondary_startup),
                CPU1_BOOT_REG);

        if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
                /* Call Exynos specific smc call */
                do_firmware_op(cpu_boot, cpu);
        }

        gic_raise_softirq(cpumask_of(cpu), 1);

        if (pen_release == -1)

e.g., exynos4412 based board

static void __init board_init_early(void)
{
        exynos_firmware_init();
}

TODO
        1. DT support.
        2. call firmware init by smp_ops.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
Changelog v4
	use call_firmware_op commented by Tomasz Figa.
	remove useless core_initcall
	
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 283fa1d..5b097ca 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -21,6 +21,9 @@ config ARM_VIC_NR
 	  The maximum number of VICs available in the system, for
 	  power management.
 
+config ARM_FIRMWARE
+	bool
+
 config ICST
 	bool
 
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..4af6568 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_ARM_GIC)		+= gic.o
 obj-$(CONFIG_ARM_VIC)		+= vic.o
+obj-$(CONFIG_ARM_FIRMWARE)	+= firmware.o
 obj-$(CONFIG_ICST)		+= icst.o
 obj-$(CONFIG_SA1111)		+= sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
diff --git a/arch/arm/common/firmware.c b/arch/arm/common/firmware.c
new file mode 100644
index 0000000..e375e9f
--- /dev/null
+++ b/arch/arm/common/firmware.c
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+
+#include <asm/firmware.h>
+
+static void cpu_boot(int cpu)
+{
+	/* Do nothing */
+}
+
+static struct firmware_ops default_firmware_ops = {
+	.do_idle		= cpu_do_idle,
+	.cpu_boot		= cpu_boot,
+};
+
+struct firmware_ops *firmware_ops = &default_firmware_ops;
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
new file mode 100644
index 0000000..99c97ff
--- /dev/null
+++ b/arch/arm/include/asm/firmware.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_FIRMWARE_H
+#define __ASM_ARM_FIRMWARE_H
+
+struct firmware_ops {
+	int	(*do_idle)(void);
+	void	(*cpu_boot)(int cpu);
+};
+
+extern struct firmware_ops *firmware_ops;
+
+#ifdef CONFIG_ARM_FIRMWARE
+#define call_firmware_op(op, ...)					\
+	((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : 0)
+#else
+#define call_firmware_op(op, ...)		do { } while (0)
+#endif
+
+#endif


From kmpark at infradead.org  Fri Aug 24 04:33:57 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 24 Aug 2012 17:33:57 +0900
Subject: [PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
Message-ID: <20120824083357.GA25384@july>

From: Kyungmin Park <kyungmin.park at samsung.com>

Some boards, e.g., exynos4412, can use smc instruction (aka firmware) interally.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
Changelog v4
	use call_firmware_op instead of indirect call

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9b58024..8ee779c 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)	+= mct.o
 
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
+obj-$(CONFIG_ARM_FIRMWARE)	+= exynos-smc.o firmware.o
+
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
 # machine support
 
 obj-$(CONFIG_MACH_SMDKC210)		+= mach-smdkv310.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index aed2eeb..540918f 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -21,6 +21,8 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+void exynos_firmware_init(void);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/exynos-smc.S b/arch/arm/mach-exynos/exynos-smc.S
new file mode 100644
index 0000000..2e27aa3
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-smc.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ *
+ * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+ */
+
+ENTRY(exynos_smc)
+	stmfd	sp!, {r4-r11, lr}
+	dsb
+	smc	#0
+	ldmfd	sp!, {r4-r11, pc}
+ENDPROC(exynos_smc)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
new file mode 100644
index 0000000..a144593
--- /dev/null
+++ b/arch/arm/mach-exynos/firmware.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics.
+ *  Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/firmware.h>
+
+#include "smc.h"
+
+static int exynos_do_idle(void)
+{
+        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        return 0;
+}
+
+static void exynos_cpu_boot(int cpu)
+{
+	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+}
+
+static struct firmware_ops exynos_firmware_ops __initdata = {
+	.do_idle	= exynos_do_idle,
+	.cpu_boot	= exynos_cpu_boot,
+};
+
+int __init exynos_firmware_init(void)
+{
+	firmware_ops = exynos_firmware_ops;
+	return 0;
+}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..c664a86 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -25,6 +25,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include <asm/firmware.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
@@ -139,6 +140,12 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
 			CPU1_BOOT_REG);
+
+		if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
+			/* Call Exynos specific smc call */
+			call_firmware_op(cpu_boot, cpu);
+		}
+
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
new file mode 100644
index 0000000..e972390
--- /dev/null
+++ b/arch/arm/mach-exynos/smc.h
@@ -0,0 +1,31 @@
+/*
+ *  Copyright (c) 2012 Samsung Electronics.
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SMC_H
+#define __ASM_ARCH_EXYNOS_SMC_H
+
+#define SMC_CMD_INIT            (-1)
+#define SMC_CMD_INFO            (-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP           (-3)
+#define SMC_CMD_CPU1BOOT        (-4)
+#define SMC_CMD_CPU0AFTR        (-5)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME       (-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL        (-21)
+#define SMC_CMD_L2X0SETUP1      (-22)
+#define SMC_CMD_L2X0SETUP2      (-23)
+#define SMC_CMD_L2X0INVALL      (-24)
+#define SMC_CMD_L2X0DEBUG       (-25)
+
+extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+
+#endif


From will.deacon at arm.com  Fri Aug 24 04:54:41 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 09:54:41 +0100
Subject: Cortex A9 with ACP needing mixed coherency model
In-Reply-To: <CAB9O=CPx2PKjyWiKa6B+MJnO0G=805Gb_rnjULb+xw1YOZjCyQ@mail.gmail.com>
References: <CAB9O=CPx2PKjyWiKa6B+MJnO0G=805Gb_rnjULb+xw1YOZjCyQ@mail.gmail.com>
Message-ID: <20120824085440.GC5400@mudshark.cambridge.arm.com>

On Fri, Aug 24, 2012 at 01:58:50AM +0100, John Linn wrote:
> It doesn't look like there's any good way to have a mixed coherency
> model to support using the ACP where there is coherency and using
> other ports where there is not coherency.
> ARM Linux kernel can support arch_is_coherent(), which means all DMA
> I/O is coherent. We have multiple DMA engines and they can go to thru
> coherent or non-coherent ports.
> 
> Am I missing something, or has someone figured out a way to deal with this?

Didn't Rob have a crack at fixing this with his recent DMA series?

  http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/113929.html

It's a really nice set of patches, so take a look.

Will


From gregory.clement at free-electrons.com  Fri Aug 24 05:09:15 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:15 +0200
Subject: Add support for Aurora L2 Cache Controller
Message-ID: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>

Hello,

As I didn't receive any arguments against modify the l2x0 driver to
add Aurora Cache Controller support on the RFC, then I post it as a
patch series. I hope this time my patch series won't be bounced, as I
had no clue about the reason it happened last time.

The purpose of this patch set is to add support for Aurora L2 Cache
Controller used by Armada 370 and Armada XP SoCs. As it was initially
designed by Marvell engineer to be compatible with the ARM L2 Cache
Controller, we chose to reuse the existing code and to just extend it
to support the differences and improvements brought by the Aurora
controller.The diffstat looks like:

 Documentation/devicetree/bindings/arm/l2cc.txt  |    9 +
 arch/arm/boot/dts/armada-370.dtsi               |    6 +
 arch/arm/boot/dts/armada-xp.dtsi                |    7 +
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 ++++
 arch/arm/include/asm/hardware/cache-l2x0.h      |    1 +
 arch/arm/mach-mvebu/Kconfig                     |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c         |    4 +
 arch/arm/mm/cache-l2x0.c                        |  297 +++++++++++++++++++++--

The main differences and improvements are:

- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller 'outer cache' and 'system cache' (the
  last one meaning maintenance operations on L1 are broadcasted to the
  L2 and L2 performs the same operation).
- in outer cache mode, the cache maintenance operations are improved
  and can be done on a range inside a page and are not limited to a
  cache line.
- during resume the controller need to restore the ctrl register.

The first patch adds some modifications in the driver
infrastructure. As most of the outer cache functions can use the
Aurora improvements, we had to introduce new functions. So we thought
it was better to use a outer_cache_fns field inside l2x0_of_data and
just memcopy it into outer_cache depending of the type of the l2x0
cache.

Since the RFC patch I rebased the series on to V3.6-rc3, add missing
Signed-off-by, corrected a compilation warning that I have missed and
run benchmarks without seeing any regression:

https://github.com/MISL-EBU-System-SW/mainline-public/wiki/Non-official-cache-bench-results-on-the-mainline-Linux-port-%28-kernels-3.6-rc2-and-3.6-rc1-%29-of-Armada-XP-and-Armada-370

The git branch aurora-L2-cache-ctrl is visible at
https://github.com/MISL-EBU-System-SW/mainline-public.git

Regards,

Gregory



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:16 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:16 +0200
Subject: [PATCH 1/6] arm: cache-l2x0: make outer_cache_fns a field of
 l2x0_of_data
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-2-git-send-email-gregory.clement@free-electrons.com>

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mm/cache-l2x0.c |   38 ++++++++++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380..3591940 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -39,7 +39,7 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
@@ -376,6 +376,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
+#ifndef CONFIG_OF
 	outer_cache.inv_range = l2x0_inv_range;
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
@@ -383,6 +384,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+#endif
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -533,15 +535,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
@@ -583,7 +604,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 
 	l2x0_init(l2x0_base, aux_val, aux_mask);
 
-	outer_cache.resume = data->resume;
+	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
 	return 0;
 }
 #endif
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:17 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:17 +0200
Subject: [PATCH 2/6] arm: cache-l2x0: add an optional register to save/restore
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-3-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c4c87bc..5f2c7b4 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -126,6 +126,7 @@ struct l2x0_regs {
 	unsigned long filter_end;
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
+	unsigned long ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:19 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:19 +0200
Subject: [PATCH 4/6] arm: mvebu: add L2 cache support
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-5-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-mvebu/Kconfig             |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..e20c5e9 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CACHE_L2X0
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..570be84 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -130,4 +131,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:20 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:20 +0200
Subject: [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday at marvell.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/armada-370.dtsi |    6 ++++++
 arch/arm/boot/dts/armada-xp.dtsi  |    7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..43fa832 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-with-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
 
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..f045a63 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,13 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-no-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
+
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021870 0x58>;
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:18 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:18 +0200
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday at marvell.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 +++++
 arch/arm/mm/cache-l2x0.c                        |  259 ++++++++++++++++++++++-
 2 files changed, 304 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/hardware/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
new file mode 100644
index 0000000..65dad20
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -0,0 +1,51 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3591940..94d96c2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-aurora-l2.h>
 
 #define CACHE_LINE_SIZE		32
 
@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -275,6 +281,130 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	unsigned long range_end;
+
+	BUG_ON(start & (CACHE_LINE_SIZE - 1));
+	BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+	/*
+	 * Try to process all cache lines between 'start' and 'end'.
+	 */
+	range_end = end;
+
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (range_end > start + MAX_RANGE_SIZE)
+		range_end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+		range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+	return range_end;
+}
+
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	/*
+	 * Make sure 'start' and 'end' reference the same page, as
+	 * L2 is PIPT and range operations only do a TLB lookup on
+	 * the start address.
+	 */
+	BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * Clean and invalidate partial first cache line.
+	 */
+	if (start & (CACHE_LINE_SIZE - 1)) {
+		writel((start & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+	}
+
+	/*
+	 * Clean and invalidate partial last cache line.
+	 */
+	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
+		writel((end & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		end &= ~(CACHE_LINE_SIZE - 1);
+	}
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+
+	dsb();
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+
+	dsb();
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+	dsb();
+}
+
+
 
 static void l2x0_disable(void)
 {
@@ -292,11 +422,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +449,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = 3;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -340,6 +481,30 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+
+		switch ((aux >> 13) & 0xf) {
+		case 3:
+			ways = 4;
+			break;
+		case 7:
+			ways = 8;
+			break;
+		case 11:
+			ways = 16;
+			break;
+		case 15:
+			ways = 32;
+			break;
+		default:
+			ways = 8;
+			break;
+		}
+		way_size_shift = 2;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -353,7 +518,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -489,6 +655,12 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
@@ -534,6 +706,48 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	u32 u;
+
+	u = readl(l2x0_base + L2X0_CTRL);
+	if (!(u & 1)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= 0x100;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -565,10 +779,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-cache-no-outer",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-cache-with-outer",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -597,6 +838,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Fri Aug 24 05:09:21 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 11:09:21 +0200
Subject: [PATCH 6/6] arm: l2x0: add aurora related properties to OF binding
In-Reply-To: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1345799361-23735-7-git-send-email-gregory.clement@free-electrons.com>

Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday at marvell.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 7ca5216..1e41b8e 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-cache-no-outer": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,aurora-cache-with-outer": Marvell Controller designed to
+	be compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example:
 
-- 
1.7.9.5



From tixy at linaro.org  Fri Aug 24 05:14:12 2012
From: tixy at linaro.org (Jon Medhurst (Tixy))
Date: Fri, 24 Aug 2012 10:14:12 +0100
Subject: [PATCH] ARM: fix cpu_relax() in case of doing dmb
In-Reply-To: <20120824011557.GO24242@S2101-09.ap.freescale.net>
References: <1345647138-8815-1-git-send-email-shawn.guo@linaro.org>
 <20120823104356.GA13622@mudshark.cambridge.arm.com>
 <20120823135806.GG24242@S2101-09.ap.freescale.net>
 <1345746686.4894.7.camel@computer5.home>
 <20120824011557.GO24242@S2101-09.ap.freescale.net>
Message-ID: <1345799652.3125.35.camel@linaro1.home>

On Fri, 2012-08-24 at 09:15 +0800, Shawn Guo wrote:
> On Thu, Aug 23, 2012 at 07:31:26PM +0100, Jon Medhurst (Tixy) wrote:
> > On Thu, 2012-08-23 at 21:58 +0800, Shawn Guo wrote:
> > > On Thu, Aug 23, 2012 at 11:43:56AM +0100, Will Deacon wrote:
> > > > On Wed, Aug 22, 2012 at 03:52:18PM +0100, Shawn Guo wrote:
> > > > > diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> > > > > index 99afa74..7cc67ce 100644
> > > > > --- a/arch/arm/include/asm/processor.h
> > > > > +++ b/arch/arm/include/asm/processor.h
> > > > > @@ -80,7 +80,14 @@ extern void release_thread(struct task_struct *);
> > > > >  unsigned long get_wchan(struct task_struct *p);
> > > > >  
> > > > >  #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
> > > > > -#define cpu_relax()			smp_mb()
> > > > > +#define cpu_relax()		do {					\
> > > > > +					asm("nop");			\
> > > > > +					asm("nop");			\
> > > > > +					asm("nop");			\
> > > > > +					asm("nop");			\
> > > > > +					asm("nop");			\
> > > > 
> > > > Can you use nop() instead of the explicit asm?
> > > 
> > > Yes.  I just tried, and it works too.
> > > 
> > > > Also, I think we should try
> > > > and use some methodology on deciding the number of nops to insert. Without
> > > > having a full handle on the problem at the moment, it would seem that we
> > > > need at least NR_CPUS worth (since the number of spinning secondaries is
> > > > NR_CPUS-1 and they may execute their barriers in lock-step).
> > > > 
> > > I'm not sure we get something like that.  In my testing here, I need
> > > at least 5 nops to get rid of the issue.
> > 
> > Doesn't A9 do dual issue?
> 
> Do you have some details about the issue to share?

I don't have any particular insight, I was just making the observation
that if CPU clock cycles executed in the loop were a consideration, then
the fact that the A9 would probably execute two nops in a clock cycle
would be pertinent.

> > If so, the maths for your 4 core iMX6Q might
> > match up with Will's hypothesis. You could try the theory by building
> > say with CONFIG_NR_CPUS == 3.
> > 
> I'm still not quite sure about the hypothesis, but I assume you are
> asking if 3 NOPs will fix the issue.  If so, the answer is NO.
> I increase the number of NOP incrementally starting from 1, and the
> issue remains until we have 5 NOPs in there.

Right, your and Hui test seems to scupper the idea that number of nops
should be related to number of CPUs. (Which I didn't really under
either.)

Perhaps the issue is related to the size of the loop buffer,
or possibly cache line boundaries?

-- 
Tixy 





From p.zabel at pengutronix.de  Fri Aug 24 05:17:43 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:43 +0200
Subject: [PATCH 2/5] ARM i.MX53, i.MX6q: Add IRAM to device tree
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1345799866-19876-3-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/boot/dts/imx53.dtsi |    5 +++++
 arch/arm/boot/dts/imx6q.dtsi |    5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e8694..6d99d8a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -330,5 +330,10 @@
 				status = "disabled";
 			};
 		};
+
+		iram at f8000000 {
+			compatible = "fsl,imx-iram";
+			reg = <0xf8000000 0x20000>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cba..bb34a28 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -87,6 +87,11 @@
 		interrupt-parent = <&intc>;
 		ranges;
 
+		iram at 00900000 {
+			compatible = "fsl,imx-iram";
+			reg = <0x00900000 0x3f000>;
+		};
+
 		timer at 00a00600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x00a00600 0x20>;
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 24 05:17:46 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:46 +0200
Subject: [PATCH 5/5] ARM i.MX: Remove iram_alloc/free,
 as they are unused in-tree
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1345799866-19876-6-git-send-email-p.zabel@pengutronix.de>

Users of the iram_alloc/free API should
convert to the genalloc API instead:

-	virt = iram_alloc(SIZE, &phys);
+	gen_pool_alloc(iram_pool, SIZE);
+	phys = gen_pool_virt_to_phys(iram_pool, virt);
 	/* ... */
-	iram_free(virt, SIZE);
+	gen_pool_free(iram_pool, virt, SIZE);

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/iram.h |   35 ---------------------------------
 arch/arm/plat-mxc/iram_alloc.c        |   26 ------------------------
 2 files changed, 61 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/iram.h

diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
deleted file mode 100644
index d5c863f..0000000
--- a/arch/arm/plat-mxc/include/mach/iram.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-
-#ifdef CONFIG_IRAM_ALLOC
-
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
-void iram_free(unsigned long dma_addr, unsigned int size);
-
-#else
-
-static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	return NULL;
-}
-
-static inline void iram_free(unsigned long base, unsigned long size) {}
-
-#endif
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
index 343e96d..0eed213 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -28,32 +28,6 @@
 
 static struct gen_pool *iram_pool;
 
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	unsigned long virt;
-
-	if (!iram_pool)
-		return NULL;
-
-	virt = gen_pool_alloc(iram_pool, size);
-	pr_debug("iram alloc - %dB at 0x%lX\n", size, *dma_addr);
-	if (!virt)
-		return NULL;
-
-	*dma_addr = gen_pool_virt_to_phys(iram_pool, virt);
-	return (void __iomem *)virt;
-}
-EXPORT_SYMBOL(iram_alloc);
-
-void iram_free(unsigned long addr, unsigned int size)
-{
-	if (!iram_pool)
-		return;
-
-	gen_pool_free(iram_pool, addr, size);
-}
-EXPORT_SYMBOL(iram_free);
-
 static int __devinit iram_probe(struct platform_device *pdev)
 {
 	void __iomem *virt_base;
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 24 05:17:44 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:44 +0200
Subject: [PATCH 3/5] iram_alloc: store the virt and phys mem address in
 gen_pool chunks
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1345799866-19876-4-git-send-email-p.zabel@pengutronix.de>

This improves the symmetry of iram_alloc and iram_free in that
iram_free has to be called with the virtual address now.
Also, gen_pool_virt_to_phys is now functional.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/iram_alloc.c |   39 ++++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
index 673deb4..343e96d 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -26,25 +26,22 @@
 #include <linux/platform_device.h>
 #include <mach/iram.h>
 
-static unsigned long iram_phys_base;
-static void __iomem *iram_virt_base;
 static struct gen_pool *iram_pool;
 
-static inline void __iomem *iram_phys_to_virt(unsigned long p)
-{
-	return iram_virt_base + (p - iram_phys_base);
-}
-
 void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
 {
+	unsigned long virt;
+
 	if (!iram_pool)
 		return NULL;
 
-	*dma_addr = gen_pool_alloc(iram_pool, size);
+	virt = gen_pool_alloc(iram_pool, size);
 	pr_debug("iram alloc - %dB at 0x%lX\n", size, *dma_addr);
-	if (!*dma_addr)
+	if (!virt)
 		return NULL;
-	return iram_phys_to_virt(*dma_addr);
+
+	*dma_addr = gen_pool_virt_to_phys(iram_pool, virt);
+	return (void __iomem *)virt;
 }
 EXPORT_SYMBOL(iram_alloc);
 
@@ -59,29 +56,37 @@ EXPORT_SYMBOL(iram_free);
 
 static int __devinit iram_probe(struct platform_device *pdev)
 {
+	void __iomem *virt_base;
 	struct resource *res;
 	unsigned long size;
+	int ret;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
 		return -EINVAL;
 
-	if (iram_phys_base)
+	if (iram_pool)
 		return -EBUSY;
 
-	iram_phys_base = res->start;
 	size = resource_size(res);
 
+	virt_base = devm_ioremap(&pdev->dev, res->start, size);
+	if (!virt_base)
+		return -ENOMEM;
+
 	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
 	if (!iram_pool)
 		return -ENOMEM;
 
-	gen_pool_add(iram_pool, res->start, size, -1);
-	iram_virt_base = ioremap(iram_phys_base, size);
-	if (!iram_virt_base)
-		return -EIO;
+	ret = gen_pool_add_virt(iram_pool, (unsigned long)virt_base,
+				res->start, size, -1);
+	if (ret < 0) {
+		gen_pool_destroy(iram_pool);
+		iram_pool = NULL;
+		return ret;
+	}
 
-	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, iram_virt_base);
+	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, virt_base);
 	return 0;
 }
 
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 24 05:17:41 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:41 +0200
Subject: [PATCH 0/5] Add device tree support for on-chip SRAM
Message-ID: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>

These patches add support to configure the on-chip SRAM via device-tree
node and to obtain the resulting genalloc pool from a phandle pointing   
at the node.
This allows drivers to allocate SRAM with the genalloc API without
hard-coding the genalloc pool address.

regards
Philipp

---
 arch/arm/boot/dts/imx53.dtsi          |    5 ++
 arch/arm/boot/dts/imx6q.dtsi          |    5 ++
 arch/arm/plat-mxc/include/mach/iram.h |   41 -----------------
 arch/arm/plat-mxc/iram_alloc.c        |   81 ++++++++++++++++++++-------------
 include/linux/genalloc.h              |   14 ++++++
 lib/genalloc.c                        |   77 +++++++++++++++++++++++++++++++
 6 files changed, 150 insertions(+), 73 deletions(-)



From p.zabel at pengutronix.de  Fri Aug 24 05:17:45 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:45 +0200
Subject: [PATCH 4/5] genalloc: add a global pool list,
 allow to find pools by phys address
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1345799866-19876-5-git-send-email-p.zabel@pengutronix.de>

This patch keeps all created pools in a global list and adds two
functions that allow to retrieve the gen_pool pointer from a known
physical address and from a device tree node.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 include/linux/genalloc.h |   14 +++++++++
 lib/genalloc.c           |   77 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+)

diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h
index 5e98eeb..46ff435 100644
--- a/include/linux/genalloc.h
+++ b/include/linux/genalloc.h
@@ -33,6 +33,7 @@
  *  General purpose special memory pool descriptor.
  */
 struct gen_pool {
+	struct list_head next_pool;	/* pool in global list */
 	spinlock_t lock;
 	struct list_head chunks;	/* list of chunks in this pool */
 	int min_alloc_order;		/* minimum allocation order */
@@ -78,4 +79,17 @@ extern void gen_pool_for_each_chunk(struct gen_pool *,
 	void (*)(struct gen_pool *, struct gen_pool_chunk *, void *), void *);
 extern size_t gen_pool_avail(struct gen_pool *);
 extern size_t gen_pool_size(struct gen_pool *);
+extern struct gen_pool *gen_pool_find_by_phys(phys_addr_t phys);
+
+#ifdef CONFIG_OF
+struct device_node;
+extern struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index);
+#else
+inline struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index)
+{
+	return NULL;
+}
+#endif
 #endif /* __GENALLOC_H__ */
diff --git a/lib/genalloc.c b/lib/genalloc.c
index 6bc04aa..df2d8f9 100644
--- a/lib/genalloc.c
+++ b/lib/genalloc.c
@@ -34,6 +34,11 @@
 #include <linux/rculist.h>
 #include <linux/interrupt.h>
 #include <linux/genalloc.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+static LIST_HEAD(pools);
+static DEFINE_SPINLOCK(list_lock);
 
 static int set_bits_ll(unsigned long *addr, unsigned long mask_to_set)
 {
@@ -152,6 +157,9 @@ struct gen_pool *gen_pool_create(int min_alloc_order, int nid)
 		spin_lock_init(&pool->lock);
 		INIT_LIST_HEAD(&pool->chunks);
 		pool->min_alloc_order = min_alloc_order;
+		spin_lock(&list_lock);
+		list_add_rcu(&pool->next_pool, &pools);
+		spin_unlock(&list_lock);
 	}
 	return pool;
 }
@@ -234,6 +242,9 @@ void gen_pool_destroy(struct gen_pool *pool)
 	int order = pool->min_alloc_order;
 	int bit, end_bit;
 
+	spin_lock(&list_lock);
+	list_del_rcu(&pool->next_pool);
+	spin_unlock(&list_lock);
 	list_for_each_safe(_chunk, _next_chunk, &pool->chunks) {
 		chunk = list_entry(_chunk, struct gen_pool_chunk, next_chunk);
 		list_del(&chunk->next_chunk);
@@ -400,3 +411,69 @@ size_t gen_pool_size(struct gen_pool *pool)
 	return size;
 }
 EXPORT_SYMBOL_GPL(gen_pool_size);
+
+/**
+ * gen_pool_find_by_phys - find a pool by physical start address
+ * @phys: physical address as added with gen_pool_add_virt
+ *
+ * Returns the pool that contains the chunk starting at phys,
+ * or NULL if not found.
+ */
+struct gen_pool *gen_pool_find_by_phys(phys_addr_t phys)
+{
+	struct gen_pool *pool, *found = NULL;
+	struct gen_pool_chunk *chunk;
+
+	rcu_read_lock();
+	list_for_each_entry_rcu(pool, &pools, next_pool) {
+		list_for_each_entry_rcu(chunk, &pool->chunks, next_chunk) {
+			if (phys == chunk->phys_addr) {
+				found = pool;
+				break;
+			}
+		}
+	}
+	rcu_read_unlock();
+
+	return found;
+}
+EXPORT_SYMBOL_GPL(gen_pool_find_by_phys);
+
+#ifdef CONFIG_OF
+/**
+ * of_get_named_gen_pool - find a pool by the physical address in
+ * @np: device node
+ *
+ * Returns the pool that contains the chunk starting at the physical
+ * address of the np device node, or NULL if not found.
+ */
+struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index)
+{
+	struct property *prop;
+	const __be32 *list;
+	int size;
+	phandle phandle;
+	struct device_node *np_pool;
+	const u32 *reg;
+	u64 addr;
+
+	prop = of_find_property(np, propname, &size);
+	if (!prop)
+		return NULL;
+	list = prop->value;
+	size /= sizeof(*list);
+	phandle = be32_to_cpup(list);
+	np_pool = of_find_node_by_phandle(phandle);
+	if (!np_pool)
+		return NULL;
+	reg = of_get_property(np_pool, "reg", NULL);
+	if (!reg)
+		return NULL;
+	addr = of_translate_address(np_pool, reg);
+	if (addr == OF_BAD_ADDR)
+		return NULL;
+	return gen_pool_find_by_phys((phys_addr_t) addr);
+}
+EXPORT_SYMBOL_GPL(of_get_named_gen_pool);
+#endif /* CONFIG_OF */
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 24 05:17:42 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 24 Aug 2012 11:17:42 +0200
Subject: [PATCH 1/5] ARM i.MX: Switch IRAM allocator to device tree
 initialization
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1345799866-19876-2-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/iram.h |    6 -----
 arch/arm/plat-mxc/iram_alloc.c        |   44 ++++++++++++++++++++++++++++++---
 2 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
index 022690c..d5c863f 100644
--- a/arch/arm/plat-mxc/include/mach/iram.h
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -20,17 +20,11 @@
 
 #ifdef CONFIG_IRAM_ALLOC
 
-int __init iram_init(unsigned long base, unsigned long size);
 void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
 void iram_free(unsigned long dma_addr, unsigned int size);
 
 #else
 
-static inline int __init iram_init(unsigned long base, unsigned long size)
-{
-	return -ENOMEM;
-}
-
 static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
 {
 	return NULL;
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
index 074c386..673deb4 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -22,6 +22,8 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/genalloc.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
 #include <mach/iram.h>
 
 static unsigned long iram_phys_base;
@@ -55,15 +57,26 @@ void iram_free(unsigned long addr, unsigned int size)
 }
 EXPORT_SYMBOL(iram_free);
 
-int __init iram_init(unsigned long base, unsigned long size)
+static int __devinit iram_probe(struct platform_device *pdev)
 {
-	iram_phys_base = base;
+	struct resource *res;
+	unsigned long size;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -EINVAL;
+
+	if (iram_phys_base)
+		return -EBUSY;
+
+	iram_phys_base = res->start;
+	size = resource_size(res);
 
 	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
 	if (!iram_pool)
 		return -ENOMEM;
 
-	gen_pool_add(iram_pool, base, size, -1);
+	gen_pool_add(iram_pool, res->start, size, -1);
 	iram_virt_base = ioremap(iram_phys_base, size);
 	if (!iram_virt_base)
 		return -EIO;
@@ -71,3 +84,28 @@ int __init iram_init(unsigned long base, unsigned long size)
 	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, iram_virt_base);
 	return 0;
 }
+
+static int __devexit iram_remove(struct platform_device *pdev)
+{
+	gen_pool_destroy(iram_pool);
+	iram_pool = NULL;
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static struct of_device_id iram_dt_ids[] = {
+	{ .compatible = "fsl,imx-iram" },
+	{ /* sentinel */ }
+};
+#endif
+
+static struct platform_driver iram_driver = {
+	.driver = {
+		.name = "imx-iram",
+		.of_match_table = of_match_ptr(iram_dt_ids),
+	},
+	.probe = iram_probe,
+	.remove = __devexit_p(iram_remove),
+};
+
+module_platform_driver(iram_driver);
-- 
1.7.10.4



From linux at arm.linux.org.uk  Fri Aug 24 05:42:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 10:42:31 +0100
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
References: <CABxcv=nsmeVLspzXERYXebmPaNO6rKCsVnak7dMtvGjiYH4vOw@mail.gmail.com>
 <20120718065951.GH6522@atomide.com>
 <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
Message-ID: <20120824094231.GA25765@n2100.arm.linux.org.uk>

On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter Meerwald wrote:
> the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in 
> omap2plus_defconfig; this does not help people updating the kernel while 
> keeping the config, nor does it help people in configuring the kernel
> 
> there is a dependency (at least for beagleboard) between MMC_OMAP_HS and 
> DMA_OMAP, and I think this should be made explicit

Well, this is where stuff starts to get really yucky, because that
means if you have DMA_OMAP as a module, you have to have MMC_OMAP_HS
as a module too.  Or vice versa.  Which is a real pain for further
development of DMA_OMAP.

Whatever, the solution here is NOT to add select statements to the
Kconfig to force DMA engine support and DMA_OMAP to 'y' for OMAP.
The best solution is for MMC_OMAP_HS to depend on DMA_OMAP, but that
will just mean that you'll end up with MMC_OMAP_HS disabled in your
config witout DMA engine support.  Another less desirable solution
is to have MMC_OMAP_HS select DMA engine and DMA_OMAP.


From catalin.marinas at arm.com  Fri Aug 24 05:50:12 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 Aug 2012 10:50:12 +0100
Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation
In-Reply-To: <20120817131358.GF11011@atomide.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-3-git-send-email-catalin.marinas@arm.com>
 <502E11B6.4020104@ti.com> <20120817100533.GE24389@arm.com>
 <CAMQu2gzz0j+SnxCY0u3H__H4U-Lor_xV-eyiMBSohCMngbkD2w@mail.gmail.com>
 <20120817131358.GF11011@atomide.com>
Message-ID: <20120824095012.GF7585@arm.com>

On Fri, Aug 17, 2012 at 02:13:59PM +0100, Tony Lindgren wrote:
> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120817 03:11]:
> > On Fri, Aug 17, 2012 at 3:35 PM, Catalin Marinas
> > <catalin.marinas at arm.com> wrote:
> > >
> > > On Fri, Aug 17, 2012 at 10:41:10AM +0100, Santosh Shilimkar wrote:
> > > >
> > > > So you expect all the secondary CPUs to be in wakeup state and probably
> > > > looping in WFE for a signal from kernel to boot. There is one issue
> > > > with this requirement though. For large CPU system, you need to reset
> > > > all the CPUs and hit this waiting loop. This will lead to large inrush
> > > > current need at bootup which may be not be supported. To avoid this
> > > > issue, secondary CPUs are kept in OFF state and then they are woken
> > > > up from kernel one by one whenever they need to be brought into the
> > > > system. This requirement should be considered.
> > >
> > > I agree, this part will be extended. That's one method that we currently
> > > support and suitable to the model.
> > >
> > > The better method is the SMC standardisation that Charles Garcia-Tobin
> > > has written (to be made available soon) and was presented at the last
> > > Linaro Connect in HK. Given that the CPU power is usually controlled by
> > > the secure side, we'll ask for an SMC to be issued for waking up
> > > secondary CPUs, so it's up to the secure firmware to write the correct
> > > hardware registers.
> > >
> > Thanks for the information. SMC standardization would indeed help
> > to overcome some of these. Will wait for that information before
> > next set of questions.
> 
> Yes please. If the SMC is not standardized for most calls at least,
> we'll end up with a horrible mess of SoC specific calls like we
> currently have. Related to that, the virtualization calls should be
> also standardized so we don't end up with multiple different hypervisors
> with different calls.

The Power State Coordination Interface initial proposal has been
published here:

http://infocenter.arm.com/help/topic/com.arm.doc.den0022a/index.html

(as with other ARM documents, they are public but free registration
required).

-- 
Catalin


From sbkim73 at samsung.com  Fri Aug 24 06:06:52 2012
From: sbkim73 at samsung.com (Sangbeom Kim)
Date: Fri, 24 Aug 2012 19:06:52 +0900
Subject: [alsa-devel] [PATCH] ASoC: samsung dma - prepare dma in
 start/resume trigger path
In-Reply-To: <CAEUnVG58NPNKuf_PRyBEegYnH95dkTN81PGZGYxDt41jhH2uaQ@mail.gmail.com>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
 <00df01cd81cb$e21d2f00$a6578d00$@com>
 <CAEUnVG58NPNKuf_PRyBEegYnH95dkTN81PGZGYxDt41jhH2uaQ@mail.gmail.com>
Message-ID: <00f001cd81e0$2ed8ccf0$8c8a66d0$@com>

On Thu, Aug 24, 2012 at 4:52 PM, Dylan Reid wrote:
> Yes. Currently, if I suspend while playing, after resume it won't work
> until I close and reopen the device.  the call to snd_pcm_resume is
> not indicating an error, but a write error comes from snd_pcm_write a
> little later.

Ok, 
Please let me know your test environment.

Thanks,
Sangbeom.



From santosh.shilimkar at ti.com  Fri Aug 24 06:21:26 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 24 Aug 2012 15:51:26 +0530
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <20120824094231.GA25765@n2100.arm.linux.org.uk>
References: <CABxcv=nsmeVLspzXERYXebmPaNO6rKCsVnak7dMtvGjiYH4vOw@mail.gmail.com>
 <20120718065951.GH6522@atomide.com>
 <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
 <20120824094231.GA25765@n2100.arm.linux.org.uk>
Message-ID: <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>

On Fri, Aug 24, 2012 at 3:12 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
>
> On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter Meerwald wrote:
> > the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in
> > omap2plus_defconfig; this does not help people updating the kernel while
> > keeping the config, nor does it help people in configuring the kernel
> >
> > there is a dependency (at least for beagleboard) between MMC_OMAP_HS and
> > DMA_OMAP, and I think this should be made explicit
>
> Well, this is where stuff starts to get really yucky, because that
> means if you have DMA_OMAP as a module, you have to have MMC_OMAP_HS
> as a module too.  Or vice versa.  Which is a real pain for further
> development of DMA_OMAP.
>
> Whatever, the solution here is NOT to add select statements to the
> Kconfig to force DMA engine support and DMA_OMAP to 'y' for OMAP.
> The best solution is for MMC_OMAP_HS to depend on DMA_OMAP, but that
> will just mean that you'll end up with MMC_OMAP_HS disabled in your
> config witout DMA engine support.  Another less desirable solution
> is to have MMC_OMAP_HS select DMA engine and DMA_OMAP.

Part of the patch [1] does the last part.
MMC_OMAP_HS select DMA engine and DMA_OMAP.

Regards
Santosh

[1] https://patchwork.kernel.org/patch/1203391/


From linux at arm.linux.org.uk  Fri Aug 24 06:39:13 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 11:39:13 +0100
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>
References: <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
 <20120824094231.GA25765@n2100.arm.linux.org.uk>
 <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>
Message-ID: <20120824103913.GB25765@n2100.arm.linux.org.uk>

On Fri, Aug 24, 2012 at 03:51:26PM +0530, Shilimkar, Santosh wrote:
> On Fri, Aug 24, 2012 at 3:12 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> >
> > On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter Meerwald wrote:
> > > the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in
> > > omap2plus_defconfig; this does not help people updating the kernel while
> > > keeping the config, nor does it help people in configuring the kernel
> > >
> > > there is a dependency (at least for beagleboard) between MMC_OMAP_HS and
> > > DMA_OMAP, and I think this should be made explicit
> >
> > Well, this is where stuff starts to get really yucky, because that
> > means if you have DMA_OMAP as a module, you have to have MMC_OMAP_HS
> > as a module too.  Or vice versa.  Which is a real pain for further
> > development of DMA_OMAP.
> >
> > Whatever, the solution here is NOT to add select statements to the
> > Kconfig to force DMA engine support and DMA_OMAP to 'y' for OMAP.
> > The best solution is for MMC_OMAP_HS to depend on DMA_OMAP, but that
> > will just mean that you'll end up with MMC_OMAP_HS disabled in your
> > config witout DMA engine support.  Another less desirable solution
> > is to have MMC_OMAP_HS select DMA engine and DMA_OMAP.
> 
> Part of the patch [1] does the last part.
> MMC_OMAP_HS select DMA engine and DMA_OMAP.
> 
> Regards
> Santosh
> 
> [1] https://patchwork.kernel.org/patch/1203391/

Well, I never saw that patch.  When I say "I'm going to be away for most
of July, and I won't be reading email, and I won't catch up with email
when I'm back" and when I get back I explicitly ask for stuff which needs
my attention sending, that's hardly surprising...

But anyway, as I said above, the "select" option is less desirable because
it forces stuff.  And if you've seen the kind of crap that you have to go
through to figure out why the hell you can't disable an option, you'll
understand why I consider that solution revolting.

Take, for instance, a list of dependencies spits out by menuconfig that
fills your entire screen, and you have to work out by reading carefully
through 2K of characters which combination of options is forcing the one
you want to turn off back on.  That is why "select" used inappropriately
is pure evil incarnate.


From will.deacon at arm.com  Fri Aug 24 06:43:10 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 11:43:10 +0100
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <20120824104309.GE5400@mudshark.cambridge.arm.com>

On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
> +static void __init aurora_broadcast_l2_commands(void)
> +{
> +       __u32 u;
> +       /* Enable Broadcasting of cache commands to L2*/
> +       __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
> +       u |= 0x100;             /* Set the FW bit */
> +       __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
> +}

Couple of questions about this code:

1. Is this register r/w from non-secure?
2. I'm surprised that there aren't barriers and/or maintenance operations
   needed around this operation. It might be worth checking in the
   documentation that you have (you probably need at least an isb()
   following the mcr).

Will


From catalin.marinas at arm.com  Fri Aug 24 06:43:39 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 24 Aug 2012 11:43:39 +0100
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <201208151434.05145.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <1344966752-16102-22-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
Message-ID: <20120824104338.GI7585@arm.com>

On Wed, Aug 15, 2012 at 03:34:04PM +0100, Arnd Bergmann wrote:
> On Tuesday 14 August 2012, Catalin Marinas wrote:
> 
> > +#ifdef CONFIG_AARCH32_EMULATION
> > +#include <linux/compat.h>
> > +
> > +#define AARCH32_KERN_SIGRET_CODE_OFFSET	0x500
> > +
> > +extern const compat_ulong_t aarch32_sigret_code[6];
> > +
> > +int compat_setup_frame(int usig, struct k_sigaction *ka, sigset_t *set,
> > +		       struct pt_regs *regs);
> > +int compat_setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
> > +			  sigset_t *set, struct pt_regs *regs);
> > +
> > +void compat_setup_restart_syscall(struct pt_regs *regs);
> > +#else
> > +
> > +static inline int compat_setup_frame(int usid, struct k_sigaction *ka,
> > +				     sigset_t *set, struct pt_regs *regs)
> > +{
> > +	BUG();
> > +}
> 
> What good is the run-time BUG() here? Nothing should be calling these
> when CONFIG_COMPAT is disabled, so I think you should just remove
> the #ifdef around the declarations, and the entire #else case.

They are called from handle_signal(), so that's to avoid #ifdef inside
functions. I can drop the BUG() (but keep the empty function) and
change the checks to is_compat_task() so that the compiler optimises the
condition out when !COMPAT.

-- 
Catalin


From balbi at ti.com  Fri Aug 24 06:40:47 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 24 Aug 2012 13:40:47 +0300
Subject: [PATCH v3 00/23] OMAP UART patches
In-Reply-To: <1345717983-18179-1-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
Message-ID: <20120824104045.GC5172@arwen.pp.htv.fi>

Forgot to Cc greg initially, my bad

On Thu, Aug 23, 2012 at 01:32:40PM +0300, Felipe Balbi wrote:
> Hi guys,
> 
> here's v3 and hopefully final version of this series. A whole bunch of new
> patches added but the good thing is that now I had another engineer's help to
> test, so he's got his Tested-by in all patches.
> 
> Changes since v2:
> 	. Added a bunch of new patches
> 	. Fixed a problem where we would always return IRQ_NONE even though we
> 		handled IRQ
> 
> Changes since v1:
>         . improved commit log on patch 9/13 (formerly 10/13)
>         . removed patch 2/13
>         . added a new patch switching from spin_lock_irqsave() to spin_lock and
>                 spin_unlock_irqrestore to spin_unlock
> 
> Alan, if you prefer in pull request form, here it is:
> 
> The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:
> 
>   Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git uart
> 
> for you to fetch changes up to a29230f14d8466c9b8c25171715378bf52189453:
> 
>   serial: omap: enable RX and TX FIFO usage (2012-08-23 09:25:16 +0300)
> 
> ----------------------------------------------------------------
> Felipe Balbi (20):
>       serial: omap: define and use to_uart_omap_port()
>       serial: omap: define helpers for pdata function pointers
>       serial: omap: don't access the platform_device
>       serial: omap: drop DMA support
>       serial: add OMAP-specific defines
>       serial: omap: simplify IRQ handling
>       serial: omap: refactor receive_chars() into rdi/rlsi handlers
>       serial: omap: move THRE check to transmit_chars()
>       serial: omap: stick to put_autosuspend
>       serial: omap: set dev->drvdata before enabling pm_runtime
>       serial: omap: drop unnecessary check from remove
>       serial: omap: make sure to suspend device before remove
>       serial: omap: don't save IRQ flags on hardirq
>       serial: omap: optimization with section annotations
>       serial: omap: drop "inline" from IRQ handler prototype
>       serial: omap: implement set_wake
>       serial: omap: make sure to put() on poll_get_char
>       serial: omap: remove unnecessary header and add a missing one
>       serial: omap: move uart_omap_port definition to C file
>       serial: omap: enable RX and TX FIFO usage
> 
> Ruchika Kharwar (2):
>       serial: omap: fix sequence of pm_runtime_* calls.
>       serial: omap: unlock the port lock
> 
> Vikram Pandita (1):
>       serial: omap: fix software flow control
> 
>  arch/arm/mach-omap2/serial.c                  |  15 +-
>  arch/arm/plat-omap/include/plat/omap-serial.h |  47 +-
>  drivers/tty/serial/omap-serial.c              | 808 ++++++++++----------------
>  include/linux/serial_reg.h                    |   4 +
>  4 files changed, 330 insertions(+), 544 deletions(-)
> 
> -- 
> 1.7.12.rc3
> 

-- 
balbi
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From santosh.shilimkar at ti.com  Fri Aug 24 06:45:26 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 24 Aug 2012 16:15:26 +0530
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <20120824103913.GB25765@n2100.arm.linux.org.uk>
References: <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
 <20120824094231.GA25765@n2100.arm.linux.org.uk>
 <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>
 <20120824103913.GB25765@n2100.arm.linux.org.uk>
Message-ID: <CAMQu2gw-vEguFU9naxsHtDVOfJkZVsFNMWJbvbc=ZuULy7TZNA@mail.gmail.com>

On Fri, Aug 24, 2012 at 4:09 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Fri, Aug 24, 2012 at 03:51:26PM +0530, Shilimkar, Santosh wrote:
>> On Fri, Aug 24, 2012 at 3:12 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>> >
>> > On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter Meerwald wrote:
>> > > the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in
>> > > omap2plus_defconfig; this does not help people updating the kernel while
>> > > keeping the config, nor does it help people in configuring the kernel
>> > >
>> > > there is a dependency (at least for beagleboard) between MMC_OMAP_HS and
>> > > DMA_OMAP, and I think this should be made explicit
>> >
>> > Well, this is where stuff starts to get really yucky, because that
>> > means if you have DMA_OMAP as a module, you have to have MMC_OMAP_HS
>> > as a module too.  Or vice versa.  Which is a real pain for further
>> > development of DMA_OMAP.
>> >
>> > Whatever, the solution here is NOT to add select statements to the
>> > Kconfig to force DMA engine support and DMA_OMAP to 'y' for OMAP.
>> > The best solution is for MMC_OMAP_HS to depend on DMA_OMAP, but that
>> > will just mean that you'll end up with MMC_OMAP_HS disabled in your
>> > config witout DMA engine support.  Another less desirable solution
>> > is to have MMC_OMAP_HS select DMA engine and DMA_OMAP.
>>
>> Part of the patch [1] does the last part.
>> MMC_OMAP_HS select DMA engine and DMA_OMAP.
>>
>> Regards
>> Santosh
>>
>> [1] https://patchwork.kernel.org/patch/1203391/
>
> Well, I never saw that patch.  When I say "I'm going to be away for most
> of July, and I won't be reading email, and I won't catch up with email
> when I'm back" and when I get back I explicitly ask for stuff which needs
> my attention sending, that's hardly surprising...
>
> But anyway, as I said above, the "select" option is less desirable because
> it forces stuff.  And if you've seen the kind of crap that you have to go
> through to figure out why the hell you can't disable an option, you'll
> understand why I consider that solution revolting.
>
> Take, for instance, a list of dependencies spits out by menuconfig that
> fills your entire screen, and you have to work out by reading carefully
> through 2K of characters which combination of options is forcing the one
> you want to turn off back on.  That is why "select" used inappropriately
> is pure evil incarnate.
I fully agree on the select and it's undesirable side effects.
Since the polling mode isn't supported yet on OMAP MMC drivers, there
was no choice. As per the previous discussion on [1], MMC and SPI driver
folks are looking at supporting polling mode support which can remove
the force select needed for OMAP_DMA.

Regards
santosh

Regards
Santosh


From pavel at ucw.cz  Fri Aug 24 07:12:11 2012
From: pavel at ucw.cz (Pavel Machek)
Date: Fri, 24 Aug 2012 13:12:11 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <1345663182.3907.134.camel@ted>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
 <1345663182.3907.134.camel@ted>
Message-ID: <20120824111211.GA28183@elf.ucw.cz>

Hi!

> > From: Marko Katic <dromede.gmail.com>
> >
> > I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It 
> > hanged almost immediately after uncompressing the kernel. I tracked the
> > problem down to a single line in arch/arm/common/sharpsl_param.c:
> > 
> > memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));
> > 
> > Commenting out the line makes the kernel boot just fine. This left me
> > wondering whether sharpsl_param.c is actually needed. Here's a comment
> > from sharpsl_param.c that describes what sharpsl_param.c actually does:
> 
> Sharp went to the trouble of saving these values into the hardware and
> passing them into the drivers. They're basically used by the LCD
> initialisation code from what I remember. I don't remember what the
> risks are of incorrect values.

We were seeing strange flicker on LCD on some machines...? Particulary
metan's machine with wifi on did that. OTOH it looked like some kind
of DMA issue.

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From konrad.wilk at oracle.com  Fri Aug 24 07:13:23 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Fri, 24 Aug 2012 07:13:23 -0400
Subject: [v3 1/4] ARM: dma-mapping: atomic_pool with struct page **pages
In-Reply-To: <1345796945-21115-2-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
 <1345796945-21115-2-git-send-email-hdoyu@nvidia.com>
Message-ID: <20120824111323.GB11007@konrad-lan.dumpdata.com>

On Fri, Aug 24, 2012 at 11:29:02AM +0300, Hiroshi Doyu wrote:
> struct page **pages is necessary to align with non atomic path in
> __iommu_get_pages(). atomic_pool() has the intialized **pages instead
> of just *page.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   17 +++++++++++++----
>  1 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 601da7a..b14ee64 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -296,7 +296,7 @@ struct dma_pool {
>  	unsigned long *bitmap;
>  	unsigned long nr_pages;
>  	void *vaddr;
> -	struct page *page;
> +	struct page **pages;
>  };
>  
>  static struct dma_pool atomic_pool = {
> @@ -335,12 +335,16 @@ static int __init atomic_pool_init(void)
>  	unsigned long nr_pages = pool->size >> PAGE_SHIFT;
>  	unsigned long *bitmap;
>  	struct page *page;
> +	struct page **pages;
>  	void *ptr;
>  	int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
> +	size_t size = nr_pages * sizeof(struct page *);
>  
> -	bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> +	size += bitmap_size;
> +	bitmap = kzalloc(size, GFP_KERNEL);
>  	if (!bitmap)
>  		goto no_bitmap;
> +	pages = (void *)bitmap + bitmap_size;

So you stuck a bitmap field in front of the array then?
Why not just define a structure where this is clearly defined
instead of doing the casting.

>  
>  	if (IS_ENABLED(CONFIG_CMA))
>  		ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
> @@ -348,9 +352,14 @@ static int __init atomic_pool_init(void)
>  		ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
>  					   &page, NULL);
>  	if (ptr) {
> +		int i;
> +
> +		for (i = 0; i < nr_pages; i++)
> +			pages[i] = page + i;
> +
>  		spin_lock_init(&pool->lock);
>  		pool->vaddr = ptr;
> -		pool->page = page;
> +		pool->pages = pages;
>  		pool->bitmap = bitmap;
>  		pool->nr_pages = nr_pages;
>  		pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
> @@ -481,7 +490,7 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
>  	if (pageno < pool->nr_pages) {
>  		bitmap_set(pool->bitmap, pageno, count);
>  		ptr = pool->vaddr + PAGE_SIZE * pageno;
> -		*ret_page = pool->page + pageno;
> +		*ret_page = pool->pages[pageno];
>  	} else {
>  		pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
>  			    "Please increase it with coherent_pool= kernel parameter!\n",
> -- 
> 1.7.5.4
> 


From konrad.wilk at oracle.com  Fri Aug 24 07:14:55 2012
From: konrad.wilk at oracle.com (Konrad Rzeszutek Wilk)
Date: Fri, 24 Aug 2012 07:14:55 -0400
Subject: [v3 2/4] ARM: dma-mapping: Refactor out to introduce
 __in_atomic_pool
In-Reply-To: <1345796945-21115-3-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
 <1345796945-21115-3-git-send-email-hdoyu@nvidia.com>
Message-ID: <20120824111455.GC11007@konrad-lan.dumpdata.com>

On Fri, Aug 24, 2012 at 11:29:03AM +0300, Hiroshi Doyu wrote:
> Check the given range("start", "size") is included in "atomic_pool" or not.
> 
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   25 +++++++++++++++++++------
>  1 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index b14ee64..508fde1 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -501,19 +501,32 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
>  	return ptr;
>  }
>  
> +static bool __in_atomic_pool(void *start, size_t size)
> +{
> +	struct dma_pool *pool = &atomic_pool;
> +	void *end = start + size;
> +	void *pool_start = pool->vaddr;
> +	void *pool_end = pool->vaddr + pool->size;
> +
> +	if (start < pool_start || start > pool_end)
> +		return false;
> +
> +	if (end > pool_end) {
> +		WARN(1, "freeing wrong coherent size from pool\n");

That does not tell what size or from what pool. Perhaps you should
include some details, such as the 'size' value, the pool used, the
range of the pool, etc. Something that will help _you_in the field
be able to narrow down what might be wrong.

> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  static int __free_from_pool(void *start, size_t size)
>  {
>  	struct dma_pool *pool = &atomic_pool;
>  	unsigned long pageno, count;
>  	unsigned long flags;
>  
> -	if (start < pool->vaddr || start > pool->vaddr + pool->size)
> -		return 0;
> -
> -	if (start + size > pool->vaddr + pool->size) {
> -		WARN(1, "freeing wrong coherent size from pool\n");
> +	if (!__in_atomic_pool(start, size))
>  		return 0;
> -	}
>  
>  	pageno = (start - pool->vaddr) >> PAGE_SHIFT;
>  	count = size >> PAGE_SHIFT;
> -- 
> 1.7.5.4
> 


From dedekind1 at gmail.com  Fri Aug 24 07:25:37 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 14:25:37 +0300
Subject: [PATCH] mtd: use %*ph[CN] to dump small buffers
In-Reply-To: <1343912807-29355-1-git-send-email-andriy.shevchenko@linux.intel.com>
References: <1343912807-29355-1-git-send-email-andriy.shevchenko@linux.intel.com>
Message-ID: <1345807537.2848.280.camel@sauron.fi.intel.com>

On Thu, 2012-08-02 at 16:06 +0300, Andy Shevchenko wrote:
> There is new format specified that helps to dump small buffers. It makes the
> code simplier and nicer.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From metan at ucw.cz  Fri Aug 24 07:25:36 2012
From: metan at ucw.cz (Cyril Hrubis)
Date: Fri, 24 Aug 2012 13:25:36 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <20120824111211.GA28183@elf.ucw.cz>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
 <1345663182.3907.134.camel@ted> <20120824111211.GA28183@elf.ucw.cz>
Message-ID: <20120824112536.GA19675@atrey.karlin.mff.cuni.cz>

Hi!
> > > I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It 
> > > hanged almost immediately after uncompressing the kernel. I tracked the
> > > problem down to a single line in arch/arm/common/sharpsl_param.c:
> > > 
> > > memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));
> > > 
> > > Commenting out the line makes the kernel boot just fine. This left me
> > > wondering whether sharpsl_param.c is actually needed. Here's a comment
> > > from sharpsl_param.c that describes what sharpsl_param.c actually does:
> > 
> > Sharp went to the trouble of saving these values into the hardware and
> > passing them into the drivers. They're basically used by the LCD
> > initialisation code from what I remember. I don't remember what the
> > risks are of incorrect values.
> 
> We were seeing strange flicker on LCD on some machines...? Particulary
> metan's machine with wifi on did that. OTOH it looked like some kind
> of DMA issue.

Yes, the problems with my LCD are DMA related (too much DMA to wifi cf card
causes timing issues on display refresh). When there is no network activity
it's okay.

And as far as I remeber there are some magic values needed for the LCD in order
not to have distorted picture (blurred, etc.) There is a callibration program
in the service menu that allows you to modify the values stored in the flash.

I remeber Stanislav did some research on that (CCing).

-- 
metan


From ulf.hansson at stericsson.com  Fri Aug 24 07:26:03 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 24 Aug 2012 13:26:03 +0200
Subject: [PATCH 2/4] clk: ux500: First version of clock definitions for ux500
In-Reply-To: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1345807565-7729-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

In this first version of the clock definitions, the structure for
ux500 are set. Support for u8500, u9540 and u8540 are prepared.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/Makefile              |    5 +++++
 drivers/clk/ux500/u8500_clk.c           |   21 +++++++++++++++++++++
 drivers/clk/ux500/u8540_clk.c           |   21 +++++++++++++++++++++
 drivers/clk/ux500/u9540_clk.c           |   21 +++++++++++++++++++++
 include/linux/platform_data/clk-ux500.h |   17 +++++++++++++++++
 5 files changed, 85 insertions(+)
 create mode 100644 drivers/clk/ux500/u8500_clk.c
 create mode 100644 drivers/clk/ux500/u8540_clk.c
 create mode 100644 drivers/clk/ux500/u9540_clk.c
 create mode 100644 include/linux/platform_data/clk-ux500.h

diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index a3ccd1b..858fbfe 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -5,3 +5,8 @@
 # Clock types
 obj-y += clk-prcc.o
 obj-y += clk-prcmu.o
+
+# Clock definitions
+obj-y += u8500_clk.o
+obj-y += u9540_clk.o
+obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
new file mode 100644
index 0000000..2bc4901
--- /dev/null
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u8500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8500_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
new file mode 100644
index 0000000..10adfd2
--- /dev/null
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u8540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8540_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
new file mode 100644
index 0000000..dbc0191
--- /dev/null
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u9540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u9540_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
new file mode 100644
index 0000000..3af0da1
--- /dev/null
+++ b/include/linux/platform_data/clk-ux500.h
@@ -0,0 +1,17 @@
+/*
+ * Clock definitions for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __CLK_UX500_H
+#define __CLK_UX500_H
+
+void u8500_clk_init(void);
+void u9540_clk_init(void);
+void u8540_clk_init(void);
+
+#endif /* __CLK_UX500_H */
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 24 07:26:01 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 24 Aug 2012 13:26:01 +0200
Subject: [PATCH 0/4] clk: Convert ARM ux500 to common clock
Message-ID: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

This converts the ux500 machine specific clocks to the common
clock framework. Old clock code are then removed from the ux500
machine directory.

This first version contains PRCMU and PRCC clock implementation.
Additional clock types shall be implemented as the next step,
although the u8500 platform is able to boot without having to
manage these.

Clock definitions are setup for u8500 and are prepared to be
setup for u9540 and as well for u8540.

This patchseries is based upon Linux 3.6 rc.2.

Compile wise a cross dependency exist to the arm-soc-tree for
the last patch (PATCH 4) affecting the ux500 machine code files.
Hopefully Arnd Bergmann can assist in getting those patches, pushed
by Linus Walleij merged prior to these onces.

Ulf Hansson (4):
  clk: ux500: Adapt PRCMU and PRCC clocks for common clk
  clk: ux500: First version of clock definitions for ux500
  clk: ux500: Clock definitions for u8500
  ARM: ux500: Switch to use common clock framework

 arch/arm/mach-ux500/Kconfig             |    1 +
 arch/arm/mach-ux500/Makefile            |    2 +-
 arch/arm/mach-ux500/clock.c             |  715 -------------------------------
 arch/arm/mach-ux500/clock.h             |  164 -------
 arch/arm/mach-ux500/cpu.c               |   14 +-
 drivers/clk/Makefile                    |    1 +
 drivers/clk/ux500/Makefile              |   12 +
 drivers/clk/ux500/clk-prcc.c            |  162 +++++++
 drivers/clk/ux500/clk-prcmu.c           |  238 ++++++++++
 drivers/clk/ux500/clk.h                 |   43 ++
 drivers/clk/ux500/u8500_clk.c           |  473 ++++++++++++++++++++
 drivers/clk/ux500/u8540_clk.c           |   21 +
 drivers/clk/ux500/u9540_clk.c           |   21 +
 include/linux/platform_data/clk-ux500.h |   17 +
 14 files changed, 998 insertions(+), 886 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/clock.c
 delete mode 100644 arch/arm/mach-ux500/clock.h
 create mode 100644 drivers/clk/ux500/Makefile
 create mode 100644 drivers/clk/ux500/clk-prcc.c
 create mode 100644 drivers/clk/ux500/clk-prcmu.c
 create mode 100644 drivers/clk/ux500/clk.h
 create mode 100644 drivers/clk/ux500/u8500_clk.c
 create mode 100644 drivers/clk/ux500/u8540_clk.c
 create mode 100644 drivers/clk/ux500/u9540_clk.c
 create mode 100644 include/linux/platform_data/clk-ux500.h

-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 24 07:26:04 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 24 Aug 2012 13:26:04 +0200
Subject: [PATCH 3/4] clk: ux500: Clock definitions for u8500
In-Reply-To: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1345807565-7729-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

First version of clock definitions of PRCMU and PRCC clocks
for the u8500 platform.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/u8500_clk.c |  454 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 453 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 2bc4901..5c1fca1 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -17,5 +17,457 @@
 
 void u8500_clk_init(void)
 {
-	/* register clocks here */
+	struct prcmu_fw_version *fw_version;
+	const char *sgaclk_parent = NULL;
+	struct clk *clk;
+
+	/* Clock sources */
+	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc0_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc1_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "ddr_pll", NULL);
+
+	/* FIXME: Add sys, ulp and int clocks here. */
+
+	clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+				32768);
+	clk_register_clkdev(clk, "clk32k", NULL);
+	clk_register_clkdev(clk, NULL, "rtc-pl031");
+
+	/* PRCMU clocks */
+	fw_version = prcmu_get_fw_version();
+	if (fw_version != NULL) {
+		switch (fw_version->project) {
+		case PRCMU_FW_PROJECT_U8500_C2:
+		case PRCMU_FW_PROJECT_U8520:
+		case PRCMU_FW_PROJECT_U8420:
+			sgaclk_parent = "soc0_pll";
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (sgaclk_parent)
+		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
+					PRCMU_SGACLK, 0);
+	else
+		clk = clk_reg_prcmu_gate("sgclk", NULL,
+					PRCMU_SGACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mali");
+
+	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "UART");
+
+	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "MSP02");
+
+	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "MSP1");
+
+	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "I2C");
+
+	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "slim");
+
+	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH1");
+
+	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH2");
+
+	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH3");
+
+	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH5");
+
+	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH6");
+
+	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH7");
+
+	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "lcd");
+	clk_register_clkdev(clk, "lcd", "mcde");
+
+	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "bml");
+
+	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "hdmi");
+	clk_register_clkdev(clk, "hdmi", "mcde");
+
+	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apeat");
+
+	clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apetrace");
+
+	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mcde");
+	clk_register_clkdev(clk, "mcde", "mcde");
+	clk_register_clkdev(clk, "dsisys", "dsilink.0");
+	clk_register_clkdev(clk, "dsisys", "dsilink.1");
+	clk_register_clkdev(clk, "dsisys", "dsilink.2");
+
+	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "ipi2");
+
+	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dsialt");
+
+	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dma40.0");
+
+	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "b2r2");
+	clk_register_clkdev(clk, NULL, "b2r2_core");
+	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
+
+	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "tv");
+	clk_register_clkdev(clk, "tv", "mcde");
+
+	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "SSP");
+
+	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "rngclk");
+
+	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "uicc");
+
+	/*
+	 * FIXME: The MTU clocks might need some kind of "parent muxed join"
+	 * and these have no K-clocks. For now, we ignore the missing
+	 * connection to the corresponding P-clocks, p6_mtu0_clk and
+	 * p6_mtu1_clk. Instead timclk is used which is the valid parent.
+	 */
+	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mtu0");
+	clk_register_clkdev(clk, NULL, "mtu1");
+
+	clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "sdmmc");
+
+
+	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
+				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs2", "mcde");
+	clk_register_clkdev(clk, "dsihs2", "dsilink.2");
+
+
+	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
+				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs0", "mcde");
+	clk_register_clkdev(clk, "dsihs0", "dsilink.0");
+
+	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
+				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs1", "mcde");
+	clk_register_clkdev(clk, "dsihs1", "dsilink.1");
+
+	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
+				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp0", "dsilink.0");
+	clk_register_clkdev(clk, "dsilp0", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
+				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp1", "dsilink.1");
+	clk_register_clkdev(clk, "dsilp1", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
+				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp2", "dsilink.2");
+	clk_register_clkdev(clk, "dsilp2", "mcde");
+
+	/*
+	 * FIXME: Add special handled PRCMU clocks here:
+	 * 1. smp_twd, use PRCMU_ARMSS.
+	 * 2. clk_arm, use PRCMU_ARMCLK.
+	 * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
+	 * 4. ab9540_clkout1yuv, see clkout0yuv
+	 */
+
+	/* PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart1");
+
+	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
+				BIT(2), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
+				BIT(3), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
+				BIT(4), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
+				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
+				BIT(6), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, NULL, "spi3");
+
+	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
+				BIT(8), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
+				BIT(9), 0);
+	clk_register_clkdev(clk, NULL, "gpio.0");
+	clk_register_clkdev(clk, NULL, "gpio.1");
+	clk_register_clkdev(clk, NULL, "gpioblock0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
+				BIT(10), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
+				BIT(11), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
+				BIT(0), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "spi2");
+
+	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "spi1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pwl");
+
+	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi4");
+
+	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
+				BIT(5), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi1");
+
+
+	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi3");
+
+	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "spi0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
+				BIT(9), 0);
+	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
+				BIT(10), 0);
+	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
+				BIT(11), 0);
+	clk_register_clkdev(clk, NULL, "gpio.6");
+	clk_register_clkdev(clk, NULL, "gpio.7");
+	clk_register_clkdev(clk, NULL, "gpioblock1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+				BIT(11), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, NULL, "fsmc");
+
+	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+				BIT(1), 0);
+	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
+				BIT(2), 0);
+	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
+				BIT(3), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
+				BIT(5), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi5");
+
+	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "gpio.2");
+	clk_register_clkdev(clk, NULL, "gpio.3");
+	clk_register_clkdev(clk, NULL, "gpio.4");
+	clk_register_clkdev(clk, NULL, "gpio.5");
+	clk_register_clkdev(clk, NULL, "gpioblock2");
+
+	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "usb", "musb-ux500.0");
+
+	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "gpio.8");
+	clk_register_clkdev(clk, NULL, "gpioblock3");
+
+	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
+				BIT(0), 0);
+
+	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "cryp0");
+	clk_register_clkdev(clk, NULL, "cryp1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "hash0");
+
+	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pka");
+
+	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, NULL, "hash1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
+				BIT(5), 0);
+	clk_register_clkdev(clk, NULL, "cfgreg");
+
+	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
+				BIT(6), 0);
+	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
+				BIT(7), 0);
+
+	/* PRCC K-clocks
+	 *
+	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
+	 * by enabling just the K-clock, even if it is not a valid parent to
+	 * the K-clock. Until drivers get fixed we might need some kind of
+	 * "parent muxed join".
+	 */
+
+	/* Periph1 */
+	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
+			U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart0");
+
+	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
+			U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart1");
+
+	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
+			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
+			U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
+			U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi0");
+
+	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
+			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+	/* FIXME: Redefinition of BIT(3). */
+	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
+			U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+
+	/* Periph2 */
+	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
+			U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi4");
+
+	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
+			U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi1");
+
+	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi3");
+
+	/* Note that rate is received from parent. */
+	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
+			U8500_CLKRST2_BASE, BIT(6),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
+			U8500_CLKRST2_BASE, BIT(7),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+
+	/* Periph3 */
+	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
+			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
+			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
+			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
+			U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi2");
+
+	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
+			U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
+			U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart2");
+
+	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
+			U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi5");
+
+	/* Periph6 */
+	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
+			U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
+
 }
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 24 07:26:05 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 24 Aug 2012 13:26:05 +0200
Subject: [PATCH 4/4] ARM: ux500: Switch to use common clock framework
In-Reply-To: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1345807565-7729-5-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Remove machine specific clock implementation and switch to use
new common clock framework.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/Kconfig  |    1 +
 arch/arm/mach-ux500/Makefile |    2 +-
 arch/arm/mach-ux500/clock.c  |  715 ------------------------------------------
 arch/arm/mach-ux500/clock.h  |  164 ----------
 arch/arm/mach-ux500/cpu.c    |   14 +-
 drivers/clk/Makefile         |    1 +
 6 files changed, 11 insertions(+), 886 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/clock.c
 delete mode 100644 arch/arm/mach-ux500/clock.h

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf..2d76e4f 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
 	select CACHE_L2X0
 	select PINCTRL
 	select PINCTRL_NOMADIK
+	select COMMON_CLK
 
 config UX500_SOC_DB8500
 	bool
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086f..5691ef6 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y				:= clock.o cpu.o devices.o devices-common.o \
+obj-y				:= cpu.o devices.o devices-common.o \
 				   id.o usb.o timer.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b06..0000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
-
-#include <plat/mtu.h>
-#include <mach/hardware.h>
-#include "clock.h"
-
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>	/* for copy_from_user */
-static LIST_HEAD(clk_list);
-#endif
-
-#define PRCC_PCKEN		0x00
-#define PRCC_PCKDIS		0x04
-#define PRCC_KCKEN		0x08
-#define PRCC_KCKDIS		0x0C
-
-#define PRCM_YYCLKEN0_MGT_SET	0x510
-#define PRCM_YYCLKEN1_MGT_SET	0x514
-#define PRCM_YYCLKEN0_MGT_CLR	0x518
-#define PRCM_YYCLKEN1_MGT_CLR	0x51C
-#define PRCM_YYCLKEN0_MGT_VAL	0x520
-#define PRCM_YYCLKEN1_MGT_VAL	0x524
-
-#define PRCM_SVAMMDSPCLK_MGT	0x008
-#define PRCM_SIAMMDSPCLK_MGT	0x00C
-#define PRCM_SGACLK_MGT		0x014
-#define PRCM_UARTCLK_MGT	0x018
-#define PRCM_MSP02CLK_MGT	0x01C
-#define PRCM_MSP1CLK_MGT	0x288
-#define PRCM_I2CCLK_MGT		0x020
-#define PRCM_SDMMCCLK_MGT	0x024
-#define PRCM_SLIMCLK_MGT	0x028
-#define PRCM_PER1CLK_MGT	0x02C
-#define PRCM_PER2CLK_MGT	0x030
-#define PRCM_PER3CLK_MGT	0x034
-#define PRCM_PER5CLK_MGT	0x038
-#define PRCM_PER6CLK_MGT	0x03C
-#define PRCM_PER7CLK_MGT	0x040
-#define PRCM_LCDCLK_MGT		0x044
-#define PRCM_BMLCLK_MGT		0x04C
-#define PRCM_HSITXCLK_MGT	0x050
-#define PRCM_HSIRXCLK_MGT	0x054
-#define PRCM_HDMICLK_MGT	0x058
-#define PRCM_APEATCLK_MGT	0x05C
-#define PRCM_APETRACECLK_MGT	0x060
-#define PRCM_MCDECLK_MGT	0x064
-#define PRCM_IPI2CCLK_MGT	0x068
-#define PRCM_DSIALTCLK_MGT	0x06C
-#define PRCM_DMACLK_MGT		0x074
-#define PRCM_B2R2CLK_MGT	0x078
-#define PRCM_TVCLK_MGT		0x07C
-#define PRCM_TCR		0x1C8
-#define PRCM_TCR_STOPPED	(1 << 16)
-#define PRCM_TCR_DOZE_MODE	(1 << 17)
-#define PRCM_UNIPROCLK_MGT	0x278
-#define PRCM_SSPCLK_MGT		0x280
-#define PRCM_RNGCLK_MGT		0x284
-#define PRCM_UICCCLK_MGT	0x27C
-
-#define PRCM_MGT_ENABLE		(1 << 8)
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (clk->enabled++ == 0) {
-		if (clk->parent_cluster)
-			__clk_enable(clk->parent_cluster);
-
-		if (clk->parent_periph)
-			__clk_enable(clk->parent_periph);
-
-		if (clk->ops && clk->ops->enable)
-			clk->ops->enable(clk);
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (--clk->enabled == 0) {
-		if (clk->ops && clk->ops->disable)
-			clk->ops->disable(clk);
-
-		if (clk->parent_periph)
-			__clk_disable(clk->parent_periph);
-
-		if (clk->parent_cluster)
-			__clk_disable(clk->parent_cluster);
-	}
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	WARN_ON(!clk->enabled);
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/*
- * The MTU has a separate, rather complex muxing setup
- * with alternative parents (peripheral cluster or
- * ULP or fixed 32768 Hz) depending on settings
- */
-static unsigned long clk_mtu_get_rate(struct clk *clk)
-{
-	void __iomem *addr;
-	u32 tcr;
-	int mtu = (int) clk->data;
-	/*
-	 * One of these is selected eventually
-	 * TODO: Replace the constant with a reference
-	 * to the ULP source once this is modeled.
-	 */
-	unsigned long clk32k = 32768;
-	unsigned long mturate;
-	unsigned long retclk;
-
-	if (cpu_is_u8500_family())
-		addr = __io_address(U8500_PRCMU_BASE);
-	else
-		ux500_unknown_soc();
-
-	/*
-	 * On a startup, always conifgure the TCR to the doze mode;
-	 * bootloaders do it for us. Do this in the kernel too.
-	 */
-	writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
-
-	tcr = readl(addr + PRCM_TCR);
-
-	/* Get the rate from the parent as a default */
-	if (clk->parent_periph)
-		mturate = clk_get_rate(clk->parent_periph);
-	else if (clk->parent_cluster)
-		mturate = clk_get_rate(clk->parent_cluster);
-	else
-		/* We need to be connected SOMEWHERE */
-		BUG();
-
-	/* Return the clock selected for this MTU */
-	if (tcr & (1 << mtu))
-		retclk = clk32k;
-	else
-		retclk = mturate;
-
-	pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
-	return retclk;
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long rate;
-
-	/*
-	 * If there is a custom getrate callback for this clock,
-	 * it will take precedence.
-	 */
-	if (clk->get_rate)
-		return clk->get_rate(clk);
-
-	if (clk->ops && clk->ops->get_rate)
-		return clk->ops->get_rate(clk);
-
-	rate = clk->rate;
-	if (!rate) {
-		if (clk->parent_periph)
-			rate = clk_get_rate(clk->parent_periph);
-		else if (clk->parent_cluster)
-			rate = clk_get_rate(clk->parent_cluster);
-	}
-
-	return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	/*TODO*/
-	return rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	clk->rate = rate;
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	/*TODO*/
-	return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-static void clk_prcmu_enable(struct clk *clk)
-{
-	void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
-				   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
-
-	writel(1 << clk->prcmu_cg_bit, cg_set_reg);
-}
-
-static void clk_prcmu_disable(struct clk *clk)
-{
-	void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
-				   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
-
-	writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
-}
-
-static struct clkops clk_prcmu_ops = {
-	.enable = clk_prcmu_enable,
-	.disable = clk_prcmu_disable,
-};
-
-static unsigned int clkrst_base[] = {
-	[1] = U8500_CLKRST1_BASE,
-	[2] = U8500_CLKRST2_BASE,
-	[3] = U8500_CLKRST3_BASE,
-	[5] = U8500_CLKRST5_BASE,
-	[6] = U8500_CLKRST6_BASE,
-};
-
-static void clk_prcc_enable(struct clk *clk)
-{
-	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-	if (clk->prcc_kernel != -1)
-		writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
-
-	if (clk->prcc_bus != -1)
-		writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
-}
-
-static void clk_prcc_disable(struct clk *clk)
-{
-	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-	if (clk->prcc_bus != -1)
-		writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
-
-	if (clk->prcc_kernel != -1)
-		writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
-}
-
-static struct clkops clk_prcc_ops = {
-	.enable = clk_prcc_enable,
-	.disable = clk_prcc_disable,
-};
-
-static struct clk clk_32khz = {
-	.name =  "clk_32khz",
-	.rate = 32000,
-};
-
-/*
- * PRCMU level clock gating
- */
-
-/* Bank 0 */
-static DEFINE_PRCMU_CLK(svaclk,		0x0, 2, SVAMMDSPCLK);
-static DEFINE_PRCMU_CLK(siaclk,		0x0, 3, SIAMMDSPCLK);
-static DEFINE_PRCMU_CLK(sgaclk,		0x0, 4, SGACLK);
-static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
-static DEFINE_PRCMU_CLK(msp02clk,	0x0, 6, MSP02CLK);
-static DEFINE_PRCMU_CLK(msp1clk,	0x0, 7, MSP1CLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(i2cclk,	0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,	0x0, 9, SDMMCCLK, 100000000);
-static DEFINE_PRCMU_CLK(slimclk,	0x0, 10, SLIMCLK);
-static DEFINE_PRCMU_CLK(per1clk,	0x0, 11, PER1CLK);
-static DEFINE_PRCMU_CLK(per2clk,	0x0, 12, PER2CLK);
-static DEFINE_PRCMU_CLK(per3clk,	0x0, 13, PER3CLK);
-static DEFINE_PRCMU_CLK(per5clk,	0x0, 14, PER5CLK);
-static DEFINE_PRCMU_CLK_RATE(per6clk,	0x0, 15, PER6CLK, 133330000);
-static DEFINE_PRCMU_CLK(lcdclk,		0x0, 17, LCDCLK);
-static DEFINE_PRCMU_CLK(bmlclk,		0x0, 18, BMLCLK);
-static DEFINE_PRCMU_CLK(hsitxclk,	0x0, 19, HSITXCLK);
-static DEFINE_PRCMU_CLK(hsirxclk,	0x0, 20, HSIRXCLK);
-static DEFINE_PRCMU_CLK(hdmiclk,	0x0, 21, HDMICLK);
-static DEFINE_PRCMU_CLK(apeatclk,	0x0, 22, APEATCLK);
-static DEFINE_PRCMU_CLK(apetraceclk,	0x0, 23, APETRACECLK);
-static DEFINE_PRCMU_CLK(mcdeclk,	0x0, 24, MCDECLK);
-static DEFINE_PRCMU_CLK(ipi2clk,	0x0, 25, IPI2CCLK);
-static DEFINE_PRCMU_CLK(dsialtclk,	0x0, 26, DSIALTCLK); /* v1 */
-static DEFINE_PRCMU_CLK(dmaclk,		0x0, 27, DMACLK);
-static DEFINE_PRCMU_CLK(b2r2clk,	0x0, 28, B2R2CLK);
-static DEFINE_PRCMU_CLK(tvclk,		0x0, 29, TVCLK);
-static DEFINE_PRCMU_CLK(uniproclk,	0x0, 30, UNIPROCLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(sspclk,	0x0, 31, SSPCLK, 48000000); /* v1 */
-
-/* Bank 1 */
-static DEFINE_PRCMU_CLK(rngclk,		0x4, 0, RNGCLK); /* v1 */
-static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
-
-/*
- * PRCC level clock gating
- * Format: per#, clk, PCKEN bit, KCKEN bit, parent
- */
-
-/* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, msp3,		11, 10, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, i2c4,		10, 9, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, gpio0,	9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,	8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3,		7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,		6,  6, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, sdi0,		5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1,		4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,		3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,		2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,	1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,	0,  0, &clk_uartclk);
-
-/* Peripheral Cluster #2 */
-static DEFINE_PRCC_CLK(2, gpio1,	11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx,	10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx,	 9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0,		8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3,		7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1,		6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2,		5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4,		4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl,		3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1,		2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2,		1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3,		0,  0, &clk_i2cclk);
-
-/* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,	8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,		7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,	6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,		5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,		4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,		3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1,		2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0,		1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,		0, -1, NULL);
-
-/* Peripheral Cluster #4 is in the always on domain */
-
-/* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,	1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb,		0,  0, NULL);
-
-/* Peripheral Cluster #6 */
-
-/* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg,	7,  7, NULL);
-static DEFINE_PRCC_CLK(6, hash1,	6, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro,	5,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, pka,		4, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,	3, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,	2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp1,    1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng,	0,  0, &clk_rngclk);
-
-static struct clk clk_dummy_apb_pclk = {
-	.name = "apb_pclk",
-};
-
-static struct clk_lookup u8500_clks[] = {
-	CLK(dummy_apb_pclk, NULL,	"apb_pclk"),
-
-	/* Peripheral Cluster #1 */
-	CLK(gpio0,	"gpio.0",	NULL),
-	CLK(gpio0,	"gpio.1",	NULL),
-	CLK(slimbus0,	"slimbus0",	NULL),
-	CLK(i2c2,	"nmk-i2c.2",	NULL),
-	CLK(sdi0,	"sdi0",		NULL),
-	CLK(msp0,	"ux500-msp-i2s.0",	NULL),
-	CLK(i2c1,	"nmk-i2c.1",	NULL),
-	CLK(uart1,	"uart1",	NULL),
-	CLK(uart0,	"uart0",	NULL),
-
-	/* Peripheral Cluster #3 */
-	CLK(gpio2,	"gpio.2",	NULL),
-	CLK(gpio2,	"gpio.3",	NULL),
-	CLK(gpio2,	"gpio.4",	NULL),
-	CLK(gpio2,	"gpio.5",	NULL),
-	CLK(sdi5,	"sdi5",		NULL),
-	CLK(uart2,	"uart2",	NULL),
-	CLK(ske,	"ske",		NULL),
-	CLK(ske,	"nmk-ske-keypad",	NULL),
-	CLK(sdi2,	"sdi2",		NULL),
-	CLK(i2c0,	"nmk-i2c.0",	NULL),
-	CLK(fsmc,	"fsmc",		NULL),
-
-	/* Peripheral Cluster #5 */
-	CLK(gpio3,	"gpio.8",	NULL),
-
-	/* Peripheral Cluster #6 */
-	CLK(hash1,	"hash1",	NULL),
-	CLK(pka,	"pka",		NULL),
-	CLK(hash0,	"hash0",	NULL),
-	CLK(cryp0,	"cryp0",	NULL),
-	CLK(cryp1,  "cryp1",    NULL),
-
-	/* PRCMU level clock gating */
-
-	/* Bank 0 */
-	CLK(svaclk,	"sva",		NULL),
-	CLK(siaclk,	"sia",		NULL),
-	CLK(sgaclk,	"sga",		NULL),
-	CLK(slimclk,	"slim",		NULL),
-	CLK(lcdclk,	"lcd",		NULL),
-	CLK(bmlclk,	"bml",		NULL),
-	CLK(hsitxclk,	"stm-hsi.0",	NULL),
-	CLK(hsirxclk,	"stm-hsi.1",	NULL),
-	CLK(hdmiclk,	"hdmi",		NULL),
-	CLK(apeatclk,	"apeat",	NULL),
-	CLK(apetraceclk,	"apetrace",	NULL),
-	CLK(mcdeclk,	"mcde",		NULL),
-	CLK(ipi2clk,	"ipi2",		NULL),
-	CLK(dmaclk,	"dma40.0",	NULL),
-	CLK(b2r2clk,	"b2r2",		NULL),
-	CLK(tvclk,	"tv",		NULL),
-
-	/* Peripheral Cluster #1 */
-	CLK(i2c4,	"nmk-i2c.4",	NULL),
-	CLK(spi3,	"spi3",		NULL),
-	CLK(msp1,	"ux500-msp-i2s.1",	NULL),
-	CLK(msp3,	"ux500-msp-i2s.3",	NULL),
-
-	/* Peripheral Cluster #2 */
-	CLK(gpio1,	"gpio.6",	NULL),
-	CLK(gpio1,	"gpio.7",	NULL),
-	CLK(ssitx,	"ssitx",	NULL),
-	CLK(ssirx,	"ssirx",	NULL),
-	CLK(spi0,	"spi0",		NULL),
-	CLK(sdi3,	"sdi3",		NULL),
-	CLK(sdi1,	"sdi1",		NULL),
-	CLK(msp2,	"ux500-msp-i2s.2",	NULL),
-	CLK(sdi4,	"sdi4",		NULL),
-	CLK(pwl,	"pwl",		NULL),
-	CLK(spi1,	"spi1",		NULL),
-	CLK(spi2,	"spi2",		NULL),
-	CLK(i2c3,	"nmk-i2c.3",	NULL),
-
-	/* Peripheral Cluster #3 */
-	CLK(ssp1,	"ssp1",		NULL),
-	CLK(ssp0,	"ssp0",		NULL),
-
-	/* Peripheral Cluster #5 */
-	CLK(usb,	"musb-ux500.0",	"usb"),
-
-	/* Peripheral Cluster #6 */
-	CLK(mtu1,	"mtu1",		NULL),
-	CLK(mtu0,	"mtu0",		NULL),
-	CLK(cfgreg,	"cfgreg",	NULL),
-	CLK(hash1,	"hash1",	NULL),
-	CLK(unipro,	"unipro",	NULL),
-	CLK(rng,	"rng",		NULL),
-
-	/* PRCMU level clock gating */
-
-	/* Bank 0 */
-	CLK(uniproclk,	"uniproclk",	NULL),
-	CLK(dsialtclk,	"dsialt",	NULL),
-
-	/* Bank 1 */
-	CLK(rngclk,	"rng",		NULL),
-	CLK(uiccclk,	"uicc",		NULL),
-};
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *	debugfs support to trace clock tree hierarchy and attributes with
- *	powerdebug
- */
-static struct dentry *clk_debugfs_root;
-
-void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
-{
-	while (num--) {
-		/* Check that the clock has not been already registered */
-		if (!(cl->clk->list.prev != cl->clk->list.next))
-			list_add_tail(&cl->clk->list, &clk_list);
-
-		cl++;
-	}
-}
-
-static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
-						  size_t size, loff_t *off)
-{
-	struct clk *clk = file->f_dentry->d_inode->i_private;
-	char cusecount[128];
-	unsigned int len;
-
-	len = sprintf(cusecount, "%u\n", clk->enabled);
-	return simple_read_from_buffer(buf, size, off, cusecount, len);
-}
-
-static ssize_t rate_dbg_read(struct file *file, char __user *buf,
-					  size_t size, loff_t *off)
-{
-	struct clk *clk = file->f_dentry->d_inode->i_private;
-	char crate[128];
-	unsigned int rate;
-	unsigned int len;
-
-	rate = clk_get_rate(clk);
-	len = sprintf(crate, "%u\n", rate);
-	return simple_read_from_buffer(buf, size, off, crate, len);
-}
-
-static const struct file_operations usecount_fops = {
-	.read = usecount_dbg_read,
-};
-
-static const struct file_operations set_rate_fops = {
-	.read = rate_dbg_read,
-};
-
-static struct dentry *clk_debugfs_register_dir(struct clk *c,
-						struct dentry *p_dentry)
-{
-	struct dentry *d, *clk_d;
-	const char *p = c->name;
-
-	if (!p)
-		p = "BUG";
-
-	clk_d = debugfs_create_dir(p, p_dentry);
-	if (!clk_d)
-		return NULL;
-
-	d = debugfs_create_file("usecount", S_IRUGO,
-				clk_d, c, &usecount_fops);
-	if (!d)
-		goto err_out;
-	d = debugfs_create_file("rate", S_IRUGO,
-				clk_d, c, &set_rate_fops);
-	if (!d)
-		goto err_out;
-	/*
-	 * TODO : not currently available in ux500
-	 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
-	 * if (!d)
-	 *	goto err_out;
-	 */
-
-	return clk_d;
-
-err_out:
-	debugfs_remove_recursive(clk_d);
-	return NULL;
-}
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-	struct clk *pa = c->parent_periph;
-	struct clk *bpa = c->parent_cluster;
-
-	if (!(bpa && !pa)) {
-		c->dent = clk_debugfs_register_dir(c,
-				pa ? pa->dent : clk_debugfs_root);
-		if (!c->dent)
-			return -ENOMEM;
-	}
-
-	if (bpa) {
-		c->dent_bus = clk_debugfs_register_dir(c,
-				bpa->dent_bus ? bpa->dent_bus : bpa->dent);
-		if ((!c->dent_bus) &&  (c->dent)) {
-			debugfs_remove_recursive(c->dent);
-			c->dent = NULL;
-			return -ENOMEM;
-		}
-	}
-	return 0;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-	int err;
-	struct clk *pa = c->parent_periph;
-	struct clk *bpa = c->parent_cluster;
-
-	if (pa && (!pa->dent && !pa->dent_bus)) {
-		err = clk_debugfs_register(pa);
-		if (err)
-			return err;
-	}
-
-	if (bpa && (!bpa->dent && !bpa->dent_bus)) {
-		err = clk_debugfs_register(bpa);
-		if (err)
-			return err;
-	}
-
-	if ((!c->dent) && (!c->dent_bus)) {
-		err = clk_debugfs_register_one(c);
-		if (err)
-			return err;
-	}
-	return 0;
-}
-
-int __init clk_debugfs_init(void)
-{
-	struct clk *c;
-	struct dentry *d;
-	int err;
-
-	d = debugfs_create_dir("clock", NULL);
-	if (!d)
-		return -ENOMEM;
-	clk_debugfs_root = d;
-
-	list_for_each_entry(c, &clk_list, list) {
-		err = clk_debugfs_register(c);
-		if (err)
-			goto err_out;
-	}
-	return 0;
-err_out:
-	debugfs_remove_recursive(clk_debugfs_root);
-	return err;
-}
-
-#endif /* defined(CONFIG_DEBUG_FS) */
-
-unsigned long clk_smp_twd_rate = 500000000;
-
-unsigned long clk_smp_twd_get_rate(struct clk *clk)
-{
-	return clk_smp_twd_rate;
-}
-
-static struct clk clk_smp_twd = {
-	.get_rate = clk_smp_twd_get_rate,
-	.name =  "smp_twd",
-};
-
-static struct clk_lookup clk_smp_twd_lookup = {
-	.dev_id = "smp_twd",
-	.clk = &clk_smp_twd,
-};
-
-#ifdef CONFIG_CPU_FREQ
-
-static int clk_twd_cpufreq_transition(struct notifier_block *nb,
-				      unsigned long state, void *data)
-{
-	struct cpufreq_freqs *f = data;
-
-	if (state == CPUFREQ_PRECHANGE) {
-		/* Save frequency in simple Hz */
-		clk_smp_twd_rate = (f->new * 1000) / 2;
-	}
-
-	return NOTIFY_OK;
-}
-
-static struct notifier_block clk_twd_cpufreq_nb = {
-	.notifier_call = clk_twd_cpufreq_transition,
-};
-
-int clk_init_smp_twd_cpufreq(void)
-{
-	return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
-				  CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-#endif
-
-int __init clk_init(void)
-{
-	clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-	clkdev_add(&clk_smp_twd_lookup);
-
-#ifdef CONFIG_DEBUG_FS
-	clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-#endif
-	return 0;
-}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a1..0000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- *  Copyright (C) 2010 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/**
- * struct clkops - ux500 clock operations
- * @enable:	function to enable the clock
- * @disable:	function to disable the clock
- * @get_rate:	function to get the current clock rate
- *
- * This structure contains function pointers to functions that will be used to
- * control the clock.  All of these functions are optional.  If get_rate is
- * NULL, the rate in the struct clk will be used.
- */
-struct clkops {
-	void (*enable) (struct clk *);
-	void (*disable) (struct clk *);
-	unsigned long (*get_rate) (struct clk *);
-	int (*set_parent)(struct clk *, struct clk *);
-};
-
-/**
- * struct clk - ux500 clock structure
- * @ops:		pointer to clkops struct used to control this clock
- * @name:		name, for debugging
- * @enabled:		refcount. positive if enabled, zero if disabled
- * @get_rate:		custom callback for getting the clock rate
- * @data:		custom per-clock data for example for the get_rate
- *			callback
- * @rate:		fixed rate for clocks which don't implement
- * 			ops->getrate
- * @prcmu_cg_off:	address offset of the combined enable/disable register
- * 			(used on u8500v1)
- * @prcmu_cg_bit:	bit in the combined enable/disable register (used on
- * 			u8500v1)
- * @prcmu_cg_mgt:	address of the enable/disable register (used on
- * 			u8500ed)
- * @cluster:		peripheral cluster number
- * @prcc_bus:		bit for the bus clock in the peripheral's CLKRST
- * @prcc_kernel:	bit for the kernel clock in the peripheral's CLKRST.
- * 			-1 if no kernel clock exists.
- * @parent_cluster:	pointer to parent's cluster clk struct
- * @parent_periph:	pointer to parent's peripheral clk struct
- *
- * Peripherals are organised into clusters, and each cluster has an associated
- * bus clock.  Some peripherals also have a parent peripheral clock.
- *
- * In order to enable a clock for a peripheral, we need to enable:
- * 	(1) the parent cluster (bus) clock at the PRCMU level
- * 	(2) the parent peripheral clock (if any) at the PRCMU level
- * 	(3) the peripheral's bus & kernel clock at the PRCC level
- *
- * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
- * of the cluster and peripheral clocks, and hooking these as the parents of
- * the individual peripheral clocks.
- *
- * (3) is handled by specifying the bits in the PRCC control registers required
- * to enable these clocks and modifying them in the ->enable and
- * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
- *
- * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
- * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
- * prcc, and parent pointers are only used for the PRCC-level clocks.
- */
-struct clk {
-	const struct clkops	*ops;
-	const char 		*name;
-	unsigned int		enabled;
-	unsigned long		(*get_rate)(struct clk *);
-	void			*data;
-
-	unsigned long		rate;
-	struct list_head	list;
-
-	/* These three are only for PRCMU clks */
-
-	unsigned int		prcmu_cg_off;
-	unsigned int		prcmu_cg_bit;
-	unsigned int		prcmu_cg_mgt;
-
-	/* The rest are only for PRCC clks */
-
-	int			cluster;
-	unsigned int		prcc_bus;
-	unsigned int		prcc_kernel;
-
-	struct clk		*parent_cluster;
-	struct clk		*parent_periph;
-#if defined(CONFIG_DEBUG_FS)
-	struct dentry		*dent;		/* For visible tree hierarchy */
-	struct dentry		*dent_bus;	/* For visible tree hierarchy */
-#endif
-};
-
-#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)		\
-struct clk clk_##_name = {					\
-		.name		= #_name,			\
-		.ops    	= &clk_prcmu_ops, 		\
-		.prcmu_cg_off	= _cg_off, 			\
-		.prcmu_cg_bit	= _cg_bit,			\
-		.prcmu_cg_mgt	= PRCM_##_reg##_MGT		\
-	}
-
-#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate)	\
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops    	= &clk_prcmu_ops, 			\
-		.prcmu_cg_off	= _cg_off, 				\
-		.prcmu_cg_bit	= _cg_bit,				\
-		.rate		= _rate,				\
-		.prcmu_cg_mgt	= PRCM_##_reg##_MGT			\
-	}
-
-#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk)	\
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops    	= &clk_prcc_ops, 			\
-		.cluster 	= _pclust,				\
-		.prcc_bus 	= _bus_en, 				\
-		.prcc_kernel 	= _kernel_en, 				\
-		.parent_cluster = &clk_per##_pclust##clk,		\
-		.parent_periph 	= _kernclk				\
-	}
-
-#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops		= &clk_prcc_ops,			\
-		.cluster	= _pclust,				\
-		.prcc_bus	= _bus_en,				\
-		.prcc_kernel	= _kernel_en,				\
-		.parent_cluster = &clk_per##_pclust##clk,		\
-		.parent_periph	= _kernclk,				\
-		.get_rate	= _callback,				\
-		.data		= (void *) _data			\
-	}
-
-
-#define CLK(_clk, _devname, _conname)			\
-	{						\
-		.clk	= &clk_##_clk,			\
-		.dev_id	= _devname,			\
-		.con_id = _conname,			\
-	}
-
-int __init clk_db8500_ed_fixup(void);
-int __init clk_init(void);
-
-#ifdef CONFIG_DEBUG_FS
-int clk_debugfs_init(void);
-#else
-static inline int clk_debugfs_init(void) { return 0; }
-#endif
-
-#ifdef CONFIG_CPU_FREQ
-int clk_init_smp_twd_cpufreq(void);
-#else
-static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
-#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 4b0a9b3..3d62c64 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
 #include <linux/stat.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/platform_data/clk-ux500.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -25,8 +25,6 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 
-#include "clock.h"
-
 void __iomem *_PRCMU_BASE;
 
 /*
@@ -70,13 +68,17 @@ void __init ux500_init_irq(void)
 	 */
 	if (cpu_is_u8500_family())
 		db8500_prcmu_early_init();
-	clk_init();
+
+	if (cpu_is_u8500_family())
+		u8500_clk_init();
+	else if (cpu_is_u9540())
+		u9540_clk_init();
+	else if (cpu_is_u8540())
+		u8540_clk_init();
 }
 
 void __init ux500_init_late(void)
 {
-	clk_debugfs_init();
-	clk_init_smp_twd_cpufreq();
 }
 
 static const char * __init ux500_get_machine(void)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..96df01b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
+obj-$(CONFIG_ARCH_U8500)	+= ux500/
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
 
 # Chip specific
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 24 07:26:02 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 24 Aug 2012 13:26:02 +0200
Subject: [PATCH 1/4] clk: ux500: Adapt PRCMU and PRCC clocks for common clk
In-Reply-To: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1345807565-7729-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

First version of common clock implementation of PRCMU clocks
and PRCC clocks for ux500 platforms.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/Makefile    |    7 ++
 drivers/clk/ux500/clk-prcc.c  |  162 ++++++++++++++++++++++++++++
 drivers/clk/ux500/clk-prcmu.c |  238 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/ux500/clk.h       |   43 ++++++++
 4 files changed, 450 insertions(+)
 create mode 100644 drivers/clk/ux500/Makefile
 create mode 100644 drivers/clk/ux500/clk-prcc.c
 create mode 100644 drivers/clk/ux500/clk-prcmu.c
 create mode 100644 drivers/clk/ux500/clk.h

diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
new file mode 100644
index 0000000..a3ccd1b
--- /dev/null
+++ b/drivers/clk/ux500/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for ux500 clocks
+#
+
+# Clock types
+obj-y += clk-prcc.o
+obj-y += clk-prcmu.o
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
new file mode 100644
index 0000000..12c7a89
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -0,0 +1,162 @@
+/*
+ * PRCC clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <mach/hardware.h>
+
+#include "clk.h"
+
+#define PRCC_PCKEN			0x000
+#define PRCC_PCKDIS			0x004
+#define PRCC_KCKEN			0x008
+#define PRCC_KCKDIS			0x00C
+#define PRCC_PCKSR			0x010
+#define PRCC_KCKSR			0x014
+
+#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
+
+struct clk_prcc {
+	struct clk_hw hw;
+	unsigned int io_base;
+	u32 cg_sel;
+	int is_enabled;
+};
+
+/* PRCC clock operations. */
+
+static int clk_prcc_pclk_enable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	void __iomem *io_base = __io_address(clk->io_base);
+
+	writel(clk->cg_sel, (io_base + PRCC_PCKEN));
+	while (!(readl(io_base + PRCC_PCKSR) & clk->cg_sel))
+		cpu_relax();
+
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcc_pclk_disable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	void __iomem *io_base = __io_address(clk->io_base);
+
+	writel(clk->cg_sel, (io_base + PRCC_PCKDIS));
+	clk->is_enabled = 0;
+}
+
+static int clk_prcc_kclk_enable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	void __iomem *io_base = __io_address(clk->io_base);
+
+	writel(clk->cg_sel, (io_base + PRCC_KCKEN));
+	while (!(readl(io_base + PRCC_KCKSR) & clk->cg_sel))
+		cpu_relax();
+
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcc_kclk_disable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	void __iomem *io_base = __io_address(clk->io_base);
+
+	writel(clk->cg_sel, (io_base + PRCC_KCKDIS));
+	clk->is_enabled = 0;
+}
+
+static int clk_prcc_is_enabled(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	return clk->is_enabled;
+}
+
+static struct clk_ops clk_prcc_pclk_ops = {
+	.enable = clk_prcc_pclk_enable,
+	.disable = clk_prcc_pclk_disable,
+	.is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk_ops clk_prcc_kclk_ops = {
+	.enable = clk_prcc_kclk_enable,
+	.disable = clk_prcc_kclk_disable,
+	.is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk *clk_reg_prcc(const char *name,
+				const char *parent_name,
+				unsigned int io_base,
+				u32 cg_sel,
+				unsigned long flags,
+				struct clk_ops *clk_prcc_ops)
+{
+	struct clk_prcc *clk;
+	struct clk_init_data clk_prcc_init;
+	struct clk *clk_reg;
+
+	if (!name) {
+		pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
+	if (!clk) {
+		pr_err("clk_prcc: %s could not allocate clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk->io_base = io_base;
+	clk->cg_sel = cg_sel;
+	clk->is_enabled = 1;
+
+	clk_prcc_init.name = name;
+	clk_prcc_init.ops = clk_prcc_ops;
+	clk_prcc_init.flags = flags;
+	clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
+	clk_prcc_init.num_parents = (parent_name ? 1 : 0);
+	clk->hw.init = &clk_prcc_init;
+
+	clk_reg = clk_register(NULL, &clk->hw);
+	if (IS_ERR_OR_NULL(clk_reg))
+		goto free_clk;
+
+	return clk_reg;
+
+free_clk:
+	kfree(clk);
+	pr_err("clk_prcc: %s failed to register clk\n", __func__);
+	return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+			      const char *parent_name,
+			      unsigned int io_base,
+			      u32 cg_sel,
+			      unsigned long flags)
+{
+	return clk_reg_prcc(name, parent_name, io_base, cg_sel, flags,
+			&clk_prcc_pclk_ops);
+}
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+			      const char *parent_name,
+			      unsigned int io_base,
+			      u32 cg_sel,
+			      unsigned long flags)
+{
+	return clk_reg_prcc(name, parent_name, io_base, cg_sel, flags,
+			&clk_prcc_kclk_ops);
+}
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
new file mode 100644
index 0000000..1d779ad
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -0,0 +1,238 @@
+/*
+ * PRCMU clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
+
+struct clk_prcmu {
+	struct clk_hw hw;
+	u8 cg_sel;
+	int is_enabled;
+};
+
+/* PRCMU clock operations. */
+
+static int clk_prcmu_prepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_request_clock(clk->cg_sel, true);
+}
+
+static void clk_prcmu_unprepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	if (prcmu_request_clock(clk->cg_sel, false))
+		pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+			hw->init->name);
+}
+
+static int clk_prcmu_enable(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcmu_disable(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	clk->is_enabled = 0;
+}
+
+static int clk_prcmu_is_enabled(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return clk->is_enabled;
+}
+
+static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_clock_rate(clk->cg_sel);
+}
+
+static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long *parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_round_clock_rate(clk->cg_sel, rate);
+}
+
+static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_set_clock_rate(clk->cg_sel, rate);
+}
+
+static int request_ape_opp100(bool enable)
+{
+	static int reqs;
+	int err = 0;
+
+	if (enable) {
+		if (!reqs)
+			err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
+							"clock", 100);
+		if (!err)
+			reqs++;
+	} else {
+		reqs--;
+		if (!reqs)
+			prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
+						"clock");
+	}
+	return err;
+}
+
+static int clk_prcmu_opp_prepare(struct clk_hw *hw)
+{
+	int err;
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+	err = request_ape_opp100(true);
+	if (err) {
+		pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
+			__func__, hw->init->name);
+		return err;
+	}
+
+	err = prcmu_request_clock(clk->cg_sel, true);
+	if (err)
+		request_ape_opp100(false);
+
+	return err;
+}
+
+static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+	if (prcmu_request_clock(clk->cg_sel, false))
+		goto out_error;
+	if (request_ape_opp100(false))
+		goto out_error;
+	return;
+
+out_error:
+	pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+		hw->init->name);
+}
+
+static struct clk_ops clk_prcmu_scalable_ops = {
+	.prepare = clk_prcmu_prepare,
+	.unprepare = clk_prcmu_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+	.round_rate = clk_prcmu_round_rate,
+	.set_rate = clk_prcmu_set_rate,
+};
+
+static struct clk_ops clk_prcmu_gate_ops = {
+	.prepare = clk_prcmu_prepare,
+	.unprepare = clk_prcmu_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk_ops clk_prcmu_opp_gate_ops = {
+	.prepare = clk_prcmu_opp_prepare,
+	.unprepare = clk_prcmu_opp_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk *clk_reg_prcmu(const char *name,
+				 const char *parent_name,
+				 u8 cg_sel,
+				 unsigned long rate,
+				 unsigned long flags,
+				 struct clk_ops *clk_prcmu_ops)
+{
+	struct clk_prcmu *clk;
+	struct clk_init_data clk_prcmu_init;
+	struct clk *clk_reg;
+
+	if (!name) {
+		pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
+	if (!clk) {
+		pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk->cg_sel = cg_sel;
+	clk->is_enabled = 1;
+	/* "rate" can be used for changing the initial frequency */
+	if (rate)
+		prcmu_set_clock_rate(cg_sel, rate);
+
+	clk_prcmu_init.name = name;
+	clk_prcmu_init.ops = clk_prcmu_ops;
+	clk_prcmu_init.flags = flags;
+	clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
+	clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
+	clk->hw.init = &clk_prcmu_init;
+
+	clk_reg = clk_register(NULL, &clk->hw);
+	if (IS_ERR_OR_NULL(clk_reg))
+		goto free_clk;
+
+	return clk_reg;
+
+free_clk:
+	kfree(clk);
+	pr_err("clk_prcmu: %s failed to register clk\n", __func__);
+	return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long rate,
+				   unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
+			&clk_prcmu_scalable_ops);
+}
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+			&clk_prcmu_gate_ops);
+}
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+			&clk_prcmu_opp_gate_ops);
+}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
new file mode 100644
index 0000000..b15382b
--- /dev/null
+++ b/drivers/clk/ux500/clk.h
@@ -0,0 +1,43 @@
+/*
+ * Clocks for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __UX500_CLK_H
+#define __UX500_CLK_H
+
+#include <linux/clk.h>
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+			      const char *parent_name,
+			      unsigned int io_base,
+			      u32 cg_sel,
+			      unsigned long flags);
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+			      const char *parent_name,
+			      unsigned int io_base,
+			      u32 cg_sel,
+			      unsigned long flags);
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long rate,
+				   unsigned long flags);
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags);
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long flags);
+
+#endif /* __UX500_CLK_H */
-- 
1.7.10



From hdoyu at nvidia.com  Fri Aug 24 07:39:55 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 13:39:55 +0200
Subject: [v3 2/4] ARM: dma-mapping: Refactor out to introduce
 __in_atomic_pool
In-Reply-To: <20120824111455.GC11007@konrad-lan.dumpdata.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com><1345796945-21115-3-git-send-email-hdoyu@nvidia.com><20120824111455.GC11007@konrad-lan.dumpdata.com>
Message-ID: <20120824.143955.659265444078193982.hdoyu@nvidia.com>

Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> wrote @ Fri, 24 Aug 2012 13:14:55 +0200:

> On Fri, Aug 24, 2012 at 11:29:03AM +0300, Hiroshi Doyu wrote:
> > Check the given range("start", "size") is included in "atomic_pool" or not.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> > ---
> >  arch/arm/mm/dma-mapping.c |   25 +++++++++++++++++++------
> >  1 files changed, 19 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> > index b14ee64..508fde1 100644
> > --- a/arch/arm/mm/dma-mapping.c
> > +++ b/arch/arm/mm/dma-mapping.c
> > @@ -501,19 +501,32 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
> >  	return ptr;
> >  }
> >  
> > +static bool __in_atomic_pool(void *start, size_t size)
> > +{
> > +	struct dma_pool *pool = &atomic_pool;
> > +	void *end = start + size;
> > +	void *pool_start = pool->vaddr;
> > +	void *pool_end = pool->vaddr + pool->size;
> > +
> > +	if (start < pool_start || start > pool_end)
> > +		return false;
> > +
> > +	if (end > pool_end) {
> > +		WARN(1, "freeing wrong coherent size from pool\n");
> 
> That does not tell what size or from what pool. Perhaps you should
> include some details, such as the 'size' value, the pool used, the
> range of the pool, etc. Something that will help _you_in the field
> be able to narrow down what might be wrong.

True. I'll.


From dedekind1 at gmail.com  Fri Aug 24 07:51:53 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 14:51:53 +0300
Subject: [PATCH 14/14] MTD: atmel_nand: add pinctrl consumer support
In-Reply-To: <1344603731-32667-14-git-send-email-plagnioj@jcrosoft.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-14-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1345809113.2848.293.camel@sauron.fi.intel.com>

On Fri, 2012-08-10 at 15:02 +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: linux-mtd at lists.infradead.org
> ---
> Hi David,
> 
> 	if you don't mind I would like to apply with the rest of the pinctrl
> 	patch series

Acked-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
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From hdoyu at nvidia.com  Fri Aug 24 07:52:00 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 13:52:00 +0200
Subject: [v3 1/4] ARM: dma-mapping: atomic_pool with struct page **pages
In-Reply-To: <20120824111323.GB11007@konrad-lan.dumpdata.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com><1345796945-21115-2-git-send-email-hdoyu@nvidia.com><20120824111323.GB11007@konrad-lan.dumpdata.com>
Message-ID: <20120824.145200.843951079622652894.hdoyu@nvidia.com>

Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> wrote @ Fri, 24 Aug 2012 13:13:23 +0200:

> On Fri, Aug 24, 2012 at 11:29:02AM +0300, Hiroshi Doyu wrote:
> > struct page **pages is necessary to align with non atomic path in
> > __iommu_get_pages(). atomic_pool() has the intialized **pages instead
> > of just *page.
> > 
> > Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> > ---
> >  arch/arm/mm/dma-mapping.c |   17 +++++++++++++----
> >  1 files changed, 13 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> > index 601da7a..b14ee64 100644
> > --- a/arch/arm/mm/dma-mapping.c
> > +++ b/arch/arm/mm/dma-mapping.c
> > @@ -296,7 +296,7 @@ struct dma_pool {
> >  	unsigned long *bitmap;
> >  	unsigned long nr_pages;
> >  	void *vaddr;
> > -	struct page *page;
> > +	struct page **pages;
> >  };
> >  
> >  static struct dma_pool atomic_pool = {
> > @@ -335,12 +335,16 @@ static int __init atomic_pool_init(void)
> >  	unsigned long nr_pages = pool->size >> PAGE_SHIFT;
> >  	unsigned long *bitmap;
> >  	struct page *page;
> > +	struct page **pages;
> >  	void *ptr;
> >  	int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
> > +	size_t size = nr_pages * sizeof(struct page *);
> >  
> > -	bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> > +	size += bitmap_size;
> > +	bitmap = kzalloc(size, GFP_KERNEL);
> >  	if (!bitmap)
> >  		goto no_bitmap;
> > +	pages = (void *)bitmap + bitmap_size;
> 
> So you stuck a bitmap field in front of the array then?
> Why not just define a structure where this is clearly defined
> instead of doing the casting.

I just wanted to allocate only once for the members "pool->bitmap" and
"pool->pages" at once. Since the size of a whole bitmap isn't known in
advance, I couldn't find any fixed type for this bitmap, which pointer
can be shifted without casting. IOW, they are variable length.


From thomas.petazzoni at free-electrons.com  Fri Aug 24 07:52:03 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 Aug 2012 13:52:03 +0200
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120810155128.GM2066@mudshark.cambridge.arm.com>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
Message-ID: <20120824135203.1bfd2b14@skate>

Hello Will,

Le Fri, 10 Aug 2012 16:51:28 +0100,
Will Deacon <will.deacon at arm.com> a ?crit :

> The invitation email was slightly misleading as it only referred to Tuesday
> 28 August, when in fact the mini-summit will be held on *both* Monday 27
> and Tuesday 28. We will run topics in the morning (and allow an hour in
> the afternoon for overflow discussion) and dedicate the rest of the time
> to hacking. Initial topic proposals are:

The "Kernel Summit Attendee Information" e-mail that we have received
on August 22th still mentions that the workshops will only take place
on Tuesday 28, with the ARM workshop being in room Marina 6, starting
at 9:00 AM.

In what room will take place the ARM workshop on Monday 27 ? I guess
the starting time will be 9:00 AM as well, is this correct?

Thanks,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Fri Aug 24 08:00:12 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 13:00:12 +0100
Subject: [PATCH] ARM: ux500: Provide SMSC911x fixed-regulator when not booting
 DT
Message-ID: <1345809612-30992-1-git-send-email-lee.jones@linaro.org>

The SMSC911x Ethernet chip requires a fixed-regulator in order to
function correctly. We have previously provided a means to obtain
this during a Device Tree boot, however nothing has been put into
place when booting with a non-DT kernel. This patch aims to change
that.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
 arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
 arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500.h            |    2 +-
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 52426a4..11ddda7 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -13,6 +13,23 @@
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
 
+#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
+static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
+       REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+
+struct regulator_init_data gpio_en_3v3_regulator = {
+       .constraints = {
+               .name = "EN-3V3",
+               .min_uV = 3300000,
+               .max_uV = 3300000,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
+       .consumer_supplies = gpio_en_3v3_consumers,
+};
+#endif
+
 /*
  * TPS61052 regulator
  */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 9499215..78a0642 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
 ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
 extern struct regulator_init_data tps61052_regulator;
+extern struct regulator_init_data gpio_en_3v3_regulator;
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index de10f8f..0e904c8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -23,6 +23,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/regulator/ab8500.h>
+#include <linux/regulator/fixed.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
@@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
 	},
 };
 
+#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
+static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
+	.supply_name		= "EN-3V3",
+	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
+	.microvolts		= 3300000,
+	.enable_high		= 1,
+	.init_data		= &gpio_en_3v3_regulator,
+	.startup_delay		= 5000, /* 1200us */
+};
+
+static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
+	.name	= "reg-fixed-voltage",
+	.id	= 1,
+	.dev	= {
+		.platform_data	= &snowball_gpio_en_3v3_data,
+	},
+};
+#endif
+
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
 	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
 	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
 	&snowball_led_dev,
 	&snowball_key_dev,
 	&snowball_sbnet_dev,
+	&snowball_gpio_en_3v3_regulator_dev,
 };
 
 static void __init mop500_init_machine(void)
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index a0f920d..4ace165 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -13,6 +13,7 @@
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
+#define SNOWBALL_EN_3V3_ETH_GPIO	26
 #define SNOWBALL_ACCEL_INT1_GPIO	163
 #define SNOWBALL_ACCEL_INT2_GPIO	164
 #define SNOWBALL_MAGNET_DRDY_GPIO	165
@@ -76,7 +77,6 @@
 #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
 #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
 #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
-#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
 
 struct device;
 struct i2c_board_info;
-- 
1.7.9.5



From will.deacon at arm.com  Fri Aug 24 08:06:56 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 13:06:56 +0100
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120824135203.1bfd2b14@skate>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
 <20120824135203.1bfd2b14@skate>
Message-ID: <20120824120656.GH5400@mudshark.cambridge.arm.com>

On Fri, Aug 24, 2012 at 12:52:03PM +0100, Thomas Petazzoni wrote:
> Hello Will,

Hi Thomas,

> Le Fri, 10 Aug 2012 16:51:28 +0100,
> Will Deacon <will.deacon at arm.com> a ?crit :
> 
> > The invitation email was slightly misleading as it only referred to Tuesday
> > 28 August, when in fact the mini-summit will be held on *both* Monday 27
> > and Tuesday 28. We will run topics in the morning (and allow an hour in
> > the afternoon for overflow discussion) and dedicate the rest of the time
> > to hacking. Initial topic proposals are:
> 
> The "Kernel Summit Attendee Information" e-mail that we have received
> on August 22th still mentions that the workshops will only take place
> on Tuesday 28, with the ARM workshop being in room Marina 6, starting
> at 9:00 AM.

Thanks for pointing this out.

> In what room will take place the ARM workshop on Monday 27 ? I guess
> the starting time will be 9:00 AM as well, is this correct?

That's right, we have the room from 9am both days and plan to start then.

Sorry again for the confusion,

Will


From pmeerw at pmeerw.net  Fri Aug 24 08:10:38 2012
From: pmeerw at pmeerw.net (Peter Meerwald)
Date: Fri, 24 Aug 2012 14:10:38 +0200 (CEST)
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <CAMQu2gw-vEguFU9naxsHtDVOfJkZVsFNMWJbvbc=ZuULy7TZNA@mail.gmail.com>
References: <CAMQu2gzX1d1FQtE3z=cwfA6daDgxJe6UFUaSY0PzGGLQOz_-ZQ@mail.gmail.com>
 <20120718071039.GI6522@atomide.com>
 <CANfBPZ97onLov1TwXYaT5A6D5XzXxwpvk+=y09W_9FmcOne4Mw@mail.gmail.com>
 <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
 <20120824094231.GA25765@n2100.arm.linux.org.uk>
 <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>
 <20120824103913.GB25765@n2100.arm.linux.org.uk>
 <CAMQu2gw-vEguFU9naxsHtDVOfJkZVsFNMWJbvbc=ZuULy7TZNA@mail.gmail.com>
Message-ID: <alpine.DEB.2.01.1208241404440.21552@pmeerw.net>


> >> > > the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in
> >> > > omap2plus_defconfig; this does not help people updating the kernel while
> >> > > keeping the config, nor does it help people in configuring the kernel
> >> > >
> >> > > there is a dependency (at least for beagleboard) between MMC_OMAP_HS and
> >> > > DMA_OMAP, and I think this should be made explicit
> >> >
> >> > Well, this is where stuff starts to get really yucky, because that
> >> > means if you have DMA_OMAP as a module, you have to have MMC_OMAP_HS
> >> > as a module too.  Or vice versa.  Which is a real pain for further
> >> > development of DMA_OMAP.
> >> >
> >> > Whatever, the solution here is NOT to add select statements to the
> >> > Kconfig to force DMA engine support and DMA_OMAP to 'y' for OMAP.
> >> > The best solution is for MMC_OMAP_HS to depend on DMA_OMAP, but that
> >> > will just mean that you'll end up with MMC_OMAP_HS disabled in your
> >> > config witout DMA engine support.  Another less desirable solution
> >> > is to have MMC_OMAP_HS select DMA engine and DMA_OMAP.
> >>
> >> Part of the patch [1] does the last part.
> >> MMC_OMAP_HS select DMA engine and DMA_OMAP.
> >>
> >> Regards
> >> Santosh
> >>
> >> [1] https://patchwork.kernel.org/patch/1203391/
> >
> > Well, I never saw that patch.  When I say "I'm going to be away for most
> > of July, and I won't be reading email, and I won't catch up with email
> > when I'm back" and when I get back I explicitly ask for stuff which needs
> > my attention sending, that's hardly surprising...
> >
> > But anyway, as I said above, the "select" option is less desirable because
> > it forces stuff.  And if you've seen the kind of crap that you have to go
> > through to figure out why the hell you can't disable an option, you'll
> > understand why I consider that solution revolting.
> >
> > Take, for instance, a list of dependencies spits out by menuconfig that
> > fills your entire screen, and you have to work out by reading carefully
> > through 2K of characters which combination of options is forcing the one
> > you want to turn off back on.  That is why "select" used inappropriately
> > is pure evil incarnate.
> I fully agree on the select and it's undesirable side effects.
> Since the polling mode isn't supported yet on OMAP MMC drivers, there
> was no choice. As per the previous discussion on [1], MMC and SPI driver
> folks are looking at supporting polling mode support which can remove
> the force select needed for OMAP_DMA.

with Linux 3.6-rc3:

CONFIG_DMA_OMAP=m
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=m
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_OMAP24XX=y
CONFIG_MTD_NAND_OMAP2=y

  LD      init/built-in.o
drivers/built-in.o: In function `omap2_mcspi_setup':
/home/pmeerw/linux-pmeerw/drivers/spi/spi-omap2-mcspi.c:859: undefined reference to `omap_dma_filter_fn'
drivers/built-in.o: In function `omap_nand_probe':
/home/pmeerw/linux-pmeerw/drivers/mtd/nand/omap2.c:1371: undefined reference to `omap_dma_filter_fn'
drivers/built-in.o: In function `omap_hsmmc_probe':
/home/pmeerw/linux-pmeerw/drivers/mmc/host/omap_hsmmc.c:2039: undefined reference to `omap_dma_filter_fn'
make: *** [vmlinux] Error 1

in addition to SPI and MMC, there seems to be also a NAND dependency

regards, p.

-- 

Peter Meerwald
+43-664-2444418 (mobile)


From sebastian.hesselbarth at gmail.com  Fri Aug 24 08:18:56 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Fri, 24 Aug 2012 14:18:56 +0200
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <CABJ1b_Sk2jb=xmnvcY5AHHLUs5j6vGWJWqL_q0Rc5akAfdJhRw@mail.gmail.com>

On 8/24/12, Gregory CLEMENT <gregory.clement at free-electrons.com> wrote:
> +++ b/arch/arm/mm/cache-l2x0.c
> ...
> @@ -597,6 +838,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)

Hi all,

IMHO l2x0_of_init shouldn't rely on anything else but the compatible device node
found. Is there any other way to set aux_val and aux_mask from DT or match data?

Sebastian


From m.szyprowski at samsung.com  Fri Aug 24 08:21:22 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 24 Aug 2012 14:21:22 +0200
Subject: [v3 1/4] ARM: dma-mapping: atomic_pool with struct page **pages
In-Reply-To: <20120824.145200.843951079622652894.hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
 <1345796945-21115-2-git-send-email-hdoyu@nvidia.com>
 <20120824111323.GB11007@konrad-lan.dumpdata.com>
 <20120824.145200.843951079622652894.hdoyu@nvidia.com>
Message-ID: <026901cd81f2$fffea680$fffbf380$%szyprowski@samsung.com>

Hello,

On Friday, August 24, 2012 1:52 PM Hiroshi Doyu wrote:

> Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> wrote @ Fri, 24 Aug 2012 13:13:23 +0200:
> 
> > On Fri, Aug 24, 2012 at 11:29:02AM +0300, Hiroshi Doyu wrote:
> > > struct page **pages is necessary to align with non atomic path in
> > > __iommu_get_pages(). atomic_pool() has the intialized **pages instead
> > > of just *page.
> > >
> > > Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> > > ---
> > >  arch/arm/mm/dma-mapping.c |   17 +++++++++++++----
> > >  1 files changed, 13 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> > > index 601da7a..b14ee64 100644
> > > --- a/arch/arm/mm/dma-mapping.c
> > > +++ b/arch/arm/mm/dma-mapping.c
> > > @@ -296,7 +296,7 @@ struct dma_pool {
> > >  	unsigned long *bitmap;
> > >  	unsigned long nr_pages;
> > >  	void *vaddr;
> > > -	struct page *page;
> > > +	struct page **pages;
> > >  };
> > >
> > >  static struct dma_pool atomic_pool = {
> > > @@ -335,12 +335,16 @@ static int __init atomic_pool_init(void)
> > >  	unsigned long nr_pages = pool->size >> PAGE_SHIFT;
> > >  	unsigned long *bitmap;
> > >  	struct page *page;
> > > +	struct page **pages;
> > >  	void *ptr;
> > >  	int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
> > > +	size_t size = nr_pages * sizeof(struct page *);
> > >
> > > -	bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> > > +	size += bitmap_size;
> > > +	bitmap = kzalloc(size, GFP_KERNEL);
> > >  	if (!bitmap)
> > >  		goto no_bitmap;
> > > +	pages = (void *)bitmap + bitmap_size;
> >
> > So you stuck a bitmap field in front of the array then?
> > Why not just define a structure where this is clearly defined
> > instead of doing the casting.
> 
> I just wanted to allocate only once for the members "pool->bitmap" and
> "pool->pages" at once. Since the size of a whole bitmap isn't known in
> advance, I couldn't find any fixed type for this bitmap, which pointer
> can be shifted without casting. IOW, they are variable length.

IMHO it is better to avoid any non-trivial things in generic arch code. Merging
those 2 allocations doesn't save any significant bit of memory and might confuse
someone. Better just allocate them separately.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From dedekind1 at gmail.com  Fri Aug 24 08:28:08 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 15:28:08 +0300
Subject: [PATCH v2] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <1345035872-11314-1-git-send-email-gcembed@gmail.com>
References: <1345035872-11314-1-git-send-email-gcembed@gmail.com>
Message-ID: <1345811288.2848.308.camel@sauron.fi.intel.com>

Hi,

On Wed, 2012-08-15 at 15:04 +0200, Ga?tan Carlier wrote:
> diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
> index 3f94e1f..7f5847a 100644
> --- a/drivers/mtd/nand/mxc_nand.c
> +++ b/drivers/mtd/nand/mxc_nand.c
> @@ -682,6 +682,26 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
>  	return 0;
>  }
>  
> +/*
> + * Swap the BI-byte on position 0x7D0 with a data byte at 0x835.
> + * To fix a bug in NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> + * Warning: The same solution needs to be applied to the boot loader and the
> + * flash programmer.
> + */
> +static void imx_bi_swap(struct mtd_info *mtd)

Could you please name the function 'nfcv1_bi_swap_quirk()' or something
like this, to make it clear that this is a work-around.

> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	struct mxc_nand_host *host = nand_chip->priv;
> +	unsigned short temp1, temp2, new_temp1;
> +
> +	temp1 = *((volatile unsigned short*)(host->main_area0 + 0x7D0));
> +	temp2 = *((volatile unsigned short*)(host->main_area0 + 0x834));
> +	new_temp1 = (temp1 & 0xFF00) | (temp2 >> 8);
> +	temp2 = (temp2 & 0x00FF) | (temp1 << 8);
> +	*((volatile unsigned short*)(host->main_area0 + 0x7D0)) = new_temp1;
> +	*((volatile unsigned short*)(host->main_area0 + 0x834)) = temp2;

Within the linux kernel all the I/O memory accesses should be done using
accessor functions, not directly.

-- 
Best Regards,
Artem Bityutskiy
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From will.deacon at arm.com  Fri Aug 24 08:36:47 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 13:36:47 +0100
Subject: [PATCH] ARM: 7467/1: mutex: use generic xchg-based implementation for
 ARMv6+
Message-ID: <1345811807-7971-1-git-send-email-will.deacon@arm.com>

The open-coded mutex implementation for ARMv6+ cores suffers from a
severe lack of barriers, so in the uncontended case we don't actually
protect any accesses performed during the critical section.

Furthermore, the code is largely a duplication of the ARMv6+ atomic_dec
code but optimised to remove a branch instruction, as the mutex fastpath
was previously inlined. Now that this is executed out-of-line, we can
reuse the atomic access code for the locking (in fact, we use the xchg
code as this produces shorter critical sections).

This patch uses the generic xchg based implementation for mutexes on
ARMv6+, which introduces barriers to the lock/unlock operations and also
has the benefit of removing a fair amount of inline assembly code.

Cc: <stable at vger.kernel.org> : 0bce9c46: mutex: Place lock in contended...
Cc: <stable at vger.kernel.org>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Nicolas Pitre <nico at linaro.org>
Reported-by: Shan Kang <kangshan0910 at gmail.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---

Greg, Ben: Here's a re-send of this mutex patch now that the dependency
has been merged into mainline. Although that patch also has a CC: stable,
I added an explicit dependency here too.

Cheers,

Will

 arch/arm/include/asm/mutex.h |  119 ++----------------------------------------
 1 files changed, 4 insertions(+), 115 deletions(-)

diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index 93226cf..b1479fd 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -7,121 +7,10 @@
  */
 #ifndef _ASM_MUTEX_H
 #define _ASM_MUTEX_H
-
-#if __LINUX_ARM_ARCH__ < 6
-/* On pre-ARMv6 hardware the swp based implementation is the most efficient. */
-# include <asm-generic/mutex-xchg.h>
-#else
-
 /*
- * Attempting to lock a mutex on ARMv6+ can be done with a bastardized
- * atomic decrement (it is not a reliable atomic decrement but it satisfies
- * the defined semantics for our purpose, while being smaller and faster
- * than a real atomic decrement or atomic swap.  The idea is to attempt
- * decrementing the lock value only once.  If once decremented it isn't zero,
- * or if its store-back fails due to a dispute on the exclusive store, we
- * simply bail out immediately through the slow path where the lock will be
- * reattempted until it succeeds.
+ * On pre-ARMv6 hardware this results in a swp-based implementation,
+ * which is the most efficient. For ARMv6+, we emit a pair of exclusive
+ * accesses instead.
  */
-static inline void
-__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-	int __ex_flag, __res;
-
-	__asm__ (
-
-		"ldrex	%0, [%2]	\n\t"
-		"sub	%0, %0, #1	\n\t"
-		"strex	%1, %0, [%2]	"
-
-		: "=&r" (__res), "=&r" (__ex_flag)
-		: "r" (&(count)->counter)
-		: "cc","memory" );
-
-	__res |= __ex_flag;
-	if (unlikely(__res != 0))
-		fail_fn(count);
-}
-
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-	int __ex_flag, __res;
-
-	__asm__ (
-
-		"ldrex	%0, [%2]	\n\t"
-		"sub	%0, %0, #1	\n\t"
-		"strex	%1, %0, [%2]	"
-
-		: "=&r" (__res), "=&r" (__ex_flag)
-		: "r" (&(count)->counter)
-		: "cc","memory" );
-
-	__res |= __ex_flag;
-	if (unlikely(__res != 0))
-		__res = fail_fn(count);
-	return __res;
-}
-
-/*
- * Same trick is used for the unlock fast path. However the original value,
- * rather than the result, is used to test for success in order to have
- * better generated assembly.
- */
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-	int __ex_flag, __res, __orig;
-
-	__asm__ (
-
-		"ldrex	%0, [%3]	\n\t"
-		"add	%1, %0, #1	\n\t"
-		"strex	%2, %1, [%3]	"
-
-		: "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)
-		: "r" (&(count)->counter)
-		: "cc","memory" );
-
-	__orig |= __ex_flag;
-	if (unlikely(__orig != 0))
-		fail_fn(count);
-}
-
-/*
- * If the unlock was done on a contended lock, or if the unlock simply fails
- * then the mutex remains locked.
- */
-#define __mutex_slowpath_needs_to_unlock()	1
-
-/*
- * For __mutex_fastpath_trylock we use another construct which could be
- * described as a "single value cmpxchg".
- *
- * This provides the needed trylock semantics like cmpxchg would, but it is
- * lighter and less generic than a true cmpxchg implementation.
- */
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-	int __ex_flag, __res, __orig;
-
-	__asm__ (
-
-		"1: ldrex	%0, [%3]	\n\t"
-		"subs		%1, %0, #1	\n\t"
-		"strexeq	%2, %1, [%3]	\n\t"
-		"movlt		%0, #0		\n\t"
-		"cmpeq		%2, #0		\n\t"
-		"bgt		1b		"
-
-		: "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)
-		: "r" (&count->counter)
-		: "cc", "memory" );
-
-	return __orig;
-}
-
-#endif
+#include <asm-generic/mutex-xchg.h>
 #endif
-- 
1.7.4.1



From gregory.clement at free-electrons.com  Fri Aug 24 08:45:30 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 14:45:30 +0200
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <20120824104309.GE5400@mudshark.cambridge.arm.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
 <20120824104309.GE5400@mudshark.cambridge.arm.com>
Message-ID: <5037776A.6050605@free-electrons.com>

On 08/24/2012 12:43 PM, Will Deacon wrote:> On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
>> +static void __init aurora_broadcast_l2_commands(void)
>> +{
>> +       __u32 u;
>> +       /* Enable Broadcasting of cache commands to L2*/
>> +       __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
>> +       u |= 0x100;             /* Set the FW bit */
>> +       __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
>> +}
>
> Couple of questions about this code:
>
> 1. Is this register r/w from non-secure?

This register is banked.

> 2. I'm surprised that there aren't barriers and/or maintenance operations
>    needed around this operation. It might be worth checking in the
>    documentation that you have (you probably need at least an isb()
>    following the mcr).

I didn't find any mention of barriers and/or maintenance operations
needed around this operation, but maybe I have missed something, or it
was implicit for the people who wrote the documentation. I will ask
confirmation that we don't need this.

>
> Will
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From lee.jones at linaro.org  Fri Aug 24 08:47:51 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 13:47:51 +0100
Subject: [PATCH] ARM: ux500: Provide SMSC911x fixed-regulator when not
 booting DT
In-Reply-To: <1345809612-30992-1-git-send-email-lee.jones@linaro.org>
References: <1345809612-30992-1-git-send-email-lee.jones@linaro.org>
Message-ID: <20120824124750.GL32491@gmail.com>

Sorry, this patch appears to contain whitespace errors which I missed.

Please wait for v2.

On Fri, Aug 24, 2012 at 01:00:12PM +0100, Lee Jones wrote:
> The SMSC911x Ethernet chip requires a fixed-regulator in order to
> function correctly. We have previously provided a means to obtain
> this during a Device Tree boot, however nothing has been put into
> place when booting with a non-DT kernel. This patch aims to change
> that.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
>  arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
>  arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
>  arch/arm/mach-ux500/board-mop500.h            |    2 +-
>  4 files changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
> index 52426a4..11ddda7 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.c
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
> @@ -13,6 +13,23 @@
>  #include <linux/regulator/ab8500.h>
>  #include "board-mop500-regulators.h"
>  
> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> +static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
> +       REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> +};
> +
> +struct regulator_init_data gpio_en_3v3_regulator = {
> +       .constraints = {
> +               .name = "EN-3V3",
> +               .min_uV = 3300000,
> +               .max_uV = 3300000,
> +               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
> +       },
> +       .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
> +       .consumer_supplies = gpio_en_3v3_consumers,
> +};
> +#endif
> +
>  /*
>   * TPS61052 regulator
>   */
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
> index 9499215..78a0642 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.h
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.h
> @@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
>  ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
>  extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
>  extern struct regulator_init_data tps61052_regulator;
> +extern struct regulator_init_data gpio_en_3v3_regulator;
>  
>  #endif
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index de10f8f..0e904c8 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -23,6 +23,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/mfd/abx500/ab8500.h>
>  #include <linux/regulator/ab8500.h>
> +#include <linux/regulator/fixed.h>
>  #include <linux/mfd/tc3589x.h>
>  #include <linux/mfd/tps6105x.h>
>  #include <linux/mfd/abx500/ab8500-gpio.h>
> @@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
>  	},
>  };
>  
> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> +static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
> +	.supply_name		= "EN-3V3",
> +	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
> +	.microvolts		= 3300000,
> +	.enable_high		= 1,
> +	.init_data		= &gpio_en_3v3_regulator,
> +	.startup_delay		= 5000, /* 1200us */
> +};
> +
> +static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
> +	.name	= "reg-fixed-voltage",
> +	.id	= 1,
> +	.dev	= {
> +		.platform_data	= &snowball_gpio_en_3v3_data,
> +	},
> +};
> +#endif
> +
>  static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
>  	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
>  	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
> @@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
>  	&snowball_led_dev,
>  	&snowball_key_dev,
>  	&snowball_sbnet_dev,
> +	&snowball_gpio_en_3v3_regulator_dev,
>  };
>  
>  static void __init mop500_init_machine(void)
> diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
> index a0f920d..4ace165 100644
> --- a/arch/arm/mach-ux500/board-mop500.h
> +++ b/arch/arm/mach-ux500/board-mop500.h
> @@ -13,6 +13,7 @@
>  #include <linux/amba/mmci.h>
>  
>  /* Snowball specific GPIO assignments, this board has no GPIO expander */
> +#define SNOWBALL_EN_3V3_ETH_GPIO	26
>  #define SNOWBALL_ACCEL_INT1_GPIO	163
>  #define SNOWBALL_ACCEL_INT2_GPIO	164
>  #define SNOWBALL_MAGNET_DRDY_GPIO	165
> @@ -76,7 +77,6 @@
>  #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
>  #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
>  #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
> -#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
>  
>  struct device;
>  struct i2c_board_info;
> -- 
> 1.7.9.5
> 

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Fri Aug 24 08:48:01 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 13:48:01 +0100
Subject: [PATCH 1/1 v2] ARM: ux500: Provide SMSC911x fixed-regulator when not
 booting DT
Message-ID: <1345812481-2384-1-git-send-email-lee.jones@linaro.org>

The SMSC911x Ethernet chip requires a fixed-regulator in order to
function correctly. We have previously provided a means to obtain
this during a Device Tree boot, however nothing has been put into
place when booting with a non-DT kernel. This patch aims to change
that.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
 arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
 arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500.h            |    2 +-
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 52426a4..139f31e 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -13,6 +13,23 @@
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
 
+#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
+static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
+	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+
+struct regulator_init_data gpio_en_3v3_regulator = {
+	.constraints = {
+		.name = "EN-3V3",
+		.min_uV = 3300000,
+		.max_uV = 3300000,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
+	.consumer_supplies = gpio_en_3v3_consumers,
+};
+#endif
+
 /*
  * TPS61052 regulator
  */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 9499215..78a0642 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
 ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
 extern struct regulator_init_data tps61052_regulator;
+extern struct regulator_init_data gpio_en_3v3_regulator;
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 42e1759..c7f0973 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -23,6 +23,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/regulator/ab8500.h>
+#include <linux/regulator/fixed.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
@@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
 	},
 };
 
+#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
+static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
+	.supply_name		= "EN-3V3",
+	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
+	.microvolts		= 3300000,
+	.enable_high		= 1,
+	.init_data		= &gpio_en_3v3_regulator,
+	.startup_delay		= 5000, /* 1200us */
+};
+
+static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
+	.name	= "reg-fixed-voltage",
+	.id	= 1,
+	.dev	= {
+		.platform_data	= &snowball_gpio_en_3v3_data,
+	},
+};
+#endif
+
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
 	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
 	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
 	&snowball_led_dev,
 	&snowball_key_dev,
 	&snowball_sbnet_dev,
+	&snowball_gpio_en_3v3_regulator_dev,
 };
 
 static void __init mop500_init_machine(void)
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 9e9dd5a..d3a02d5 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -13,6 +13,7 @@
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
+#define SNOWBALL_EN_3V3_ETH_GPIO	26
 #define SNOWBALL_ACCEL_INT1_GPIO	163
 #define SNOWBALL_ACCEL_INT2_GPIO	164
 #define SNOWBALL_MAGNET_DRDY_GPIO	165
@@ -76,7 +77,6 @@
 #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
 #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
 #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
-#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
 
 struct device;
 struct i2c_board_info;
-- 
1.7.9.5



From dromede at gmail.com  Fri Aug 24 08:53:15 2012
From: dromede at gmail.com (=?UTF-8?B?TWFya28gS2F0acSH?=)
Date: Fri, 24 Aug 2012 14:53:15 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <20120824112536.GA19675@atrey.karlin.mff.cuni.cz>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
 <1345663182.3907.134.camel@ted> <20120824111211.GA28183@elf.ucw.cz>
 <20120824112536.GA19675@atrey.karlin.mff.cuni.cz>
Message-ID: <CAHod+Gc8udMVChaezqte3dEns5E-udduwugL0o_VCYu=UCP9Tg@mail.gmail.com>

On Fri, Aug 24, 2012 at 1:25 PM, Cyril Hrubis <metan at ucw.cz> wrote:
> Hi!
>> > > I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000. It
>> > > hanged almost immediately after uncompressing the kernel. I tracked the
>> > > problem down to a single line in arch/arm/common/sharpsl_param.c:
>> > >
>> > > memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info));
>> > >
>> > > Commenting out the line makes the kernel boot just fine. This left me
>> > > wondering whether sharpsl_param.c is actually needed. Here's a comment
>> > > from sharpsl_param.c that describes what sharpsl_param.c actually does:
>> >
>> > Sharp went to the trouble of saving these values into the hardware and
>> > passing them into the drivers. They're basically used by the LCD
>> > initialisation code from what I remember. I don't remember what the
>> > risks are of incorrect values.
>>
>> We were seeing strange flicker on LCD on some machines...? Particulary
>> metan's machine with wifi on did that. OTOH it looked like some kind
>> of DMA issue.
>
> Yes, the problems with my LCD are DMA related (too much DMA to wifi cf card
> causes timing issues on display refresh). When there is no network activity
> it's okay.
>
> And as far as I remeber there are some magic values needed for the LCD in order
> not to have distorted picture (blurred, etc.) There is a callibration program
> in the service menu that allows you to modify the values stored in the flash.
>
> I remeber Stanislav did some research on that (CCing).
>
> --
> metan


From dromede at gmail.com  Fri Aug 24 08:56:05 2012
From: dromede at gmail.com (=?UTF-8?B?TWFya28gS2F0acSH?=)
Date: Fri, 24 Aug 2012 14:56:05 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
In-Reply-To: <CAHod+Gc8udMVChaezqte3dEns5E-udduwugL0o_VCYu=UCP9Tg@mail.gmail.com>
References: <1345656424-31234-1-git-send-email-dromede@gmail.com>
 <1345663182.3907.134.camel@ted> <20120824111211.GA28183@elf.ucw.cz>
 <20120824112536.GA19675@atrey.karlin.mff.cuni.cz>
 <CAHod+Gc8udMVChaezqte3dEns5E-udduwugL0o_VCYu=UCP9Tg@mail.gmail.com>
Message-ID: <CAHod+GcpVuutgU6uUrc1X5G=_B2YU2J4zsERqX8zcTobi-f6dw@mail.gmail.com>

On Fri, Aug 24, 2012 at 2:53 PM, Marko Kati? <dromede at gmail.com> wrote:
> On Fri, Aug 24, 2012 at 1:25 PM, Cyril Hrubis <metan at ucw.cz> wrote:
>> Hi!
>>> > > I recently tried running 3.6-rc2 kernel on my Sharp Zaurus C-1000.
>>> > > It
>>> > > hanged almost immediately after uncompressing the kernel. I tracked
>>> > > the
>>> > > problem down to a single line in arch/arm/common/sharpsl_param.c:
>>> > >
>>> > > memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct
>>> > > sharpsl_param_info));
>>> > >
>>> > > Commenting out the line makes the kernel boot just fine. This left
>>> > > me
>>> > > wondering whether sharpsl_param.c is actually needed. Here's a
>>> > > comment
>>> > > from sharpsl_param.c that describes what sharpsl_param.c actually
>>> > > does:
>>> >
>>> > Sharp went to the trouble of saving these values into the hardware and
>>> > passing them into the drivers. They're basically used by the LCD
>>> > initialisation code from what I remember. I don't remember what the
>>> > risks are of incorrect values.
>>>
>>> We were seeing strange flicker on LCD on some machines...? Particulary
>>> metan's machine with wifi on did that. OTOH it looked like some kind
>>> of DMA issue.
>>
>> Yes, the problems with my LCD are DMA related (too much DMA to wifi cf
>> card
>> causes timing issues on display refresh). When there is no network
>> activity
>> it's okay.
>>
>> And as far as I remeber there are some magic values needed for the LCD in
>> order
>> not to have distorted picture (blurred, etc.) There is a callibration
>> program
>> in the service menu that allows you to modify the values stored in the
>> flash.
>>
>> I remeber Stanislav did some research on that (CCing).
>>
>> --
>> metan

As i said, this patch is not valid since i wrote it under false
assumptions. My tests were wrong, sharpsl_save_param() works as it
should in all kernels before 3.3-rc1.

3.3-rc1 breaks sharpsl_save_param() with this commit:

[72662e01088394577be4a3f14da94cf87bea2591] ARM: head.S: only include
__turn_mmu_on in the initial identity mapping

I already have a patch ready for 3.6-rc3 that fixes this (confirmed
working on my akita), i just need to test it on a SA1100 machine
before commiting.

As for your lcd/dma problems, the arbiter control register might help.
There's a paragraph in the pxa270 dev manual that says that the lcd
controller should have top priority when large lcd displays are used.
Try setting ARB_CNTRL in your machine init code so the lcd controller
has top priority or lower the dma controller priority.

Actually i've written a nice sysfs interface for the arbiter bus
register a while ago and i can't find the patch...


From linus.walleij at stericsson.com  Fri Aug 24 09:01:04 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 24 Aug 2012 15:01:04 +0200
Subject: [PATCH] ARM: ux500: set proper GIC flags
Message-ID: <1345813264-4896-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The Ux500 will be able to wake up on any IRQ, so flag it with
IRQCHIP_SKIP_SET_WAKE, and we want to mask off the IRQs when
going to suspend to avoid transient effects so also flag
this with IRQCHIP_MASK_ON_SUSPEND.

Cc: Etienne Carriere <etienne.carriere at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7..2957432 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -51,6 +51,8 @@ void __init ux500_init_irq(void)
 	void __iomem *dist_base;
 	void __iomem *cpu_base;
 
+	gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+
 	if (cpu_is_u8500_family()) {
 		dist_base = __io_address(U8500_GIC_DIST_BASE);
 		cpu_base = __io_address(U8500_GIC_CPU_BASE);
-- 
1.7.11.3



From robherring2 at gmail.com  Fri Aug 24 09:05:50 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 24 Aug 2012 08:05:50 -0500
Subject: Cortex A9 with ACP needing mixed coherency model
In-Reply-To: <20120824085440.GC5400@mudshark.cambridge.arm.com>
References: <CAB9O=CPx2PKjyWiKa6B+MJnO0G=805Gb_rnjULb+xw1YOZjCyQ@mail.gmail.com>
 <20120824085440.GC5400@mudshark.cambridge.arm.com>
Message-ID: <50377C2E.4080408@gmail.com>

On 08/24/2012 03:54 AM, Will Deacon wrote:
> On Fri, Aug 24, 2012 at 01:58:50AM +0100, John Linn wrote:
>> It doesn't look like there's any good way to have a mixed coherency
>> model to support using the ACP where there is coherency and using
>> other ports where there is not coherency.
>> ARM Linux kernel can support arch_is_coherent(), which means all DMA
>> I/O is coherent. We have multiple DMA engines and they can go to thru
>> coherent or non-coherent ports.
>>
>> Am I missing something, or has someone figured out a way to deal with this?
> 
> Didn't Rob have a crack at fixing this with his recent DMA series?
> 
>   http://lists.infradead.org/pipermail/linux-arm-kernel/2012-August/113929.html
> 
> It's a really nice set of patches, so take a look.

It's queued up in Marek's dma-mapping tree for 3.7.

Rob



From ola.o.lilja at stericsson.com  Fri Aug 24 09:05:17 2012
From: ola.o.lilja at stericsson.com (Ola Lilja)
Date: Fri, 24 Aug 2012 15:05:17 +0200
Subject: FW: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe
 rather than as a device
In-Reply-To: <014401cd8165$99960c40$ccc224c0$@se>
References: <014401cd8165$99960c40$ccc224c0$@se>
Message-ID: <50377C0D.2060905@stericsson.com>

On 08/23/2012 09:29 PM, Ola Lilja wrote:

> 
> 
>> -----Original Message-----
>> From: Lee Jones [mailto:lee.jones at linaro.org]
>> Sent: den 23 augusti 2012 16:59
>> To: Mark Brown
>> Cc: Ola Lilja; 'Linus Walleij'; roger.xr.nilsson at stericsson.com; linux-
>> arm-kernel at lists.infradead.org; alsa-devel at alsa-project.org
>> Subject: Re: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe
>> rather than as a device
>> 
>> On Thu, Aug 23, 2012 at 03:37:57PM +0100, Mark Brown wrote:
>> > On Thu, Aug 23, 2012 at 02:26:19PM +0100, Lee Jones wrote:
>> >
>> > > > I think Ola is suggesting probing the DMA driver from the machine
>> > > > which will also work though I'm not 100% sure if I'm parsing the
>> > > > above correctly.  The issue in DT terms is that if the DMA
>> > > > controller is shared with a bunch of other IPs then it should
>> have
>> > > > one node shared between them all and not a bunch of shim nodes
>> > > > inserted in the middle which only exists due to the way Linux
>> instantiates stuff.


I haven't followed everything in this discussion, but what I meant in an earlier
mail was that using the device for platform-DAI (MSP_I2S) also
as platform int the DAI-link struct is not anything I can see fit (as in the
patch Lee first submitted).
I can see a few acceptable solutions:
1) Use it as it is! (A virtual device for PCM is created in arch/arm and the
probe is invoked from the machine-driver).
2) Since the actual platform is the DMA-block, maybe there is some way of making
the device "non-virtual" by having some sub-device in the DMA-driver that is
instead triggered in the same way as in 1).
3) Move it to DT, but it seems that it is not possible when it is now a virtual
device.

Any of these three would be fine with me.

>> >
>> > > When you say 'machine', do you mean from arch/<arch>/mach-*? If so,
>> > > I'm keen for that not to happen.
>> >
>> > No, sound/soc/ux500/snowball.c or whatever.  At least that's my
>> guess.
>> 
>> Ah, I see. Maybe the mop500.c file then.
>> 
>> > > > They instantiate the PCM driver dynamically from the DAI when
>> it's
>> > > > probed which is pretty much what you're patch is doing.
>> >
>> > > So they do it in the same why I have with this patch? Do you know
>> > > why Ola might think this is a bad idea?
>> >
>> > I'm not 100% sure, I'm guessing it might be down to the fact that you
>> > end up with multiple PCM drivers.  We could avoid that with
>> > refcounting but nobody's really worried about it.
>> 
>> I think I'll wait for Ola to get back, as he's the expert on this
>> stuff.
>> 
>> I'll attempt to re-jig the patch-set, as this is a blocker atm.
>> 
>> --
>> Lee Jones
>> Linaro ST-Ericsson Landing Team Lead
>> Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook
>> | Twitter | Blog
> 




From stigge at antcom.de  Fri Aug 24 09:06:52 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 24 Aug 2012 15:06:52 +0200
Subject: [PATCH 2/2] mtd: lpc32xx_mlc: Cleanup after DT-only conversion
In-Reply-To: <1345813612-4234-1-git-send-email-stigge@antcom.de>
References: <1345813612-4234-1-git-send-email-stigge@antcom.de>
Message-ID: <1345813612-4234-2-git-send-email-stigge@antcom.de>

The LPC32xx's DT-only conversion of the MLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.

Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.

There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/mtd/nand/lpc32xx_mlc.c |   46 ++++++++++++++++-------------------------
 1 file changed, 18 insertions(+), 28 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_mlc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_mlc.c
@@ -621,43 +621,36 @@ out1:
 	return -ENXIO;
 }
 
-#ifdef CONFIG_OF
 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
 {
-	struct lpc32xx_nand_cfg_mlc *pdata;
+	struct lpc32xx_nand_cfg_mlc *ncfg;
 	struct device_node *np = dev->of_node;
 
-	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
-	if (!pdata) {
+	ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
+	if (!ncfg) {
 		dev_err(dev, "could not allocate memory for platform data\n");
 		return NULL;
 	}
 
-	of_property_read_u32(np, "nxp,tcea-delay", &pdata->tcea_delay);
-	of_property_read_u32(np, "nxp,busy-delay", &pdata->busy_delay);
-	of_property_read_u32(np, "nxp,nand-ta", &pdata->nand_ta);
-	of_property_read_u32(np, "nxp,rd-high", &pdata->rd_high);
-	of_property_read_u32(np, "nxp,rd-low", &pdata->rd_low);
-	of_property_read_u32(np, "nxp,wr-high", &pdata->wr_high);
-	of_property_read_u32(np, "nxp,wr-low", &pdata->wr_low);
-
-	if (!pdata->tcea_delay || !pdata->busy_delay || !pdata->nand_ta ||
-	    !pdata->rd_high || !pdata->rd_low || !pdata->wr_high ||
-	    !pdata->wr_low) {
+	of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
+	of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
+	of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
+	of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
+	of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
+	of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
+	of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
+
+	if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
+	    !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
+	    !ncfg->wr_low) {
 		dev_err(dev, "chip parameters not specified correctly\n");
 		return NULL;
 	}
 
-	pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0);
+	ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
 
-	return pdata;
+	return ncfg;
 }
-#else
-static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
-{
-	return NULL;
-}
-#endif
 
 /*
  * Probe for NAND controller
@@ -695,10 +688,9 @@ static int __devinit lpc32xx_nand_probe(
 	nand_chip = &host->nand_chip;
 	if (pdev->dev.of_node)
 		host->ncfg = lpc32xx_parse_dt(&pdev->dev);
-	else
-		host->ncfg = pdev->dev.platform_data;
 	if (!host->ncfg) {
-		dev_err(&pdev->dev, "Missing platform data\n");
+		dev_err(&pdev->dev,
+			"Missing or bad NAND config from device tree\n");
 		return -ENOENT;
 	}
 	if (host->ncfg->wp_gpio == -EPROBE_DEFER)
@@ -907,13 +899,11 @@ static int lpc32xx_nand_suspend(struct p
 #define lpc32xx_nand_suspend NULL
 #endif
 
-#if defined(CONFIG_OF)
 static const struct of_device_id lpc32xx_nand_match[] = {
 	{ .compatible = "nxp,lpc3220-mlc" },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
-#endif
 
 static struct platform_driver lpc32xx_nand_driver = {
 	.probe		= lpc32xx_nand_probe,


From stigge at antcom.de  Fri Aug 24 09:06:51 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 24 Aug 2012 15:06:51 +0200
Subject: [PATCH 1/2] mtd: lpc32xx_slc: Cleanup after DT-only conversion
Message-ID: <1345813612-4234-1-git-send-email-stigge@antcom.de>

The LPC32xx's DT-only conversion of the SLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.

Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.

There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/mtd/nand/lpc32xx_slc.c |   52 ++++++++++++++++-------------------------
 1 file changed, 21 insertions(+), 31 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/lpc32xx_slc.c
+++ linux-2.6/drivers/mtd/nand/lpc32xx_slc.c
@@ -732,45 +732,38 @@ static int lpc32xx_nand_dma_setup(struct
 	return 0;
 }
 
-#ifdef CONFIG_OF
 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
 {
-	struct lpc32xx_nand_cfg_slc *pdata;
+	struct lpc32xx_nand_cfg_slc *ncfg;
 	struct device_node *np = dev->of_node;
 
-	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
-	if (!pdata) {
-		dev_err(dev, "could not allocate memory for platform data\n");
+	ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
+	if (!ncfg) {
+		dev_err(dev, "could not allocate memory for NAND config\n");
 		return NULL;
 	}
 
-	of_property_read_u32(np, "nxp,wdr-clks", &pdata->wdr_clks);
-	of_property_read_u32(np, "nxp,wwidth", &pdata->wwidth);
-	of_property_read_u32(np, "nxp,whold", &pdata->whold);
-	of_property_read_u32(np, "nxp,wsetup", &pdata->wsetup);
-	of_property_read_u32(np, "nxp,rdr-clks", &pdata->rdr_clks);
-	of_property_read_u32(np, "nxp,rwidth", &pdata->rwidth);
-	of_property_read_u32(np, "nxp,rhold", &pdata->rhold);
-	of_property_read_u32(np, "nxp,rsetup", &pdata->rsetup);
-
-	if (!pdata->wdr_clks || !pdata->wwidth || !pdata->whold ||
-	    !pdata->wsetup || !pdata->rdr_clks || !pdata->rwidth ||
-	    !pdata->rhold || !pdata->rsetup) {
+	of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
+	of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
+	of_property_read_u32(np, "nxp,whold", &ncfg->whold);
+	of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
+	of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
+	of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
+	of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
+	of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
+
+	if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
+	    !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
+	    !ncfg->rhold || !ncfg->rsetup) {
 		dev_err(dev, "chip parameters not specified correctly\n");
 		return NULL;
 	}
 
-	pdata->use_bbt = of_get_nand_on_flash_bbt(np);
-	pdata->wp_gpio = of_get_named_gpio(np, "gpios", 0);
+	ncfg->use_bbt = of_get_nand_on_flash_bbt(np);
+	ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
 
-	return pdata;
+	return ncfg;
 }
-#else
-static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
-{
-	return NULL;
-}
-#endif
 
 /*
  * Probe for NAND controller
@@ -806,10 +799,9 @@ static int __devinit lpc32xx_nand_probe(
 
 	if (pdev->dev.of_node)
 		host->ncfg = lpc32xx_parse_dt(&pdev->dev);
-	else
-		host->ncfg = pdev->dev.platform_data;
 	if (!host->ncfg) {
-		dev_err(&pdev->dev, "Missing platform data\n");
+		dev_err(&pdev->dev,
+			"Missing or bad NAND config from device tree\n");
 		return -ENOENT;
 	}
 	if (host->ncfg->wp_gpio == -EPROBE_DEFER)
@@ -1035,13 +1027,11 @@ static int lpc32xx_nand_suspend(struct p
 #define lpc32xx_nand_suspend NULL
 #endif
 
-#if defined(CONFIG_OF)
 static const struct of_device_id lpc32xx_nand_match[] = {
 	{ .compatible = "nxp,lpc3220-slc" },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
-#endif
 
 static struct platform_driver lpc32xx_nand_driver = {
 	.probe		= lpc32xx_nand_probe,


From santosh.shilimkar at ti.com  Fri Aug 24 09:08:39 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 24 Aug 2012 18:38:39 +0530
Subject: [PATCH] ARM: ux500: set proper GIC flags
In-Reply-To: <1345813264-4896-1-git-send-email-linus.walleij@stericsson.com>
References: <1345813264-4896-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAMQu2gx9kU4sPL5-TsJTq_2pUvm3Jm6rNWS=XYQJihTUpm1nHg@mail.gmail.com>

On Fri, Aug 24, 2012 at 6:31 PM, Linus Walleij
<linus.walleij at stericsson.com> wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
>
> The Ux500 will be able to wake up on any IRQ, so flag it with
> IRQCHIP_SKIP_SET_WAKE, and we want to mask off the IRQs when
> going to suspend to avoid transient effects so also flag
> this with IRQCHIP_MASK_ON_SUSPEND.
>
> Cc: Etienne Carriere <etienne.carriere at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/mach-ux500/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
> index e2360e7..2957432 100644
> --- a/arch/arm/mach-ux500/cpu.c
> +++ b/arch/arm/mach-ux500/cpu.c
> @@ -51,6 +51,8 @@ void __init ux500_init_irq(void)
>         void __iomem *dist_base;
>         void __iomem *cpu_base;
>
> +       gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
> +
With this patch, you should no longer need the dummy set_irq_wake()
patch which I was form
you for ux500.

Regards
Santosh


From shawn.guo at linaro.org  Fri Aug 24 09:19:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 21:19:38 +0800
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <20120824131935.GF31998@S2101-09.ap.freescale.net>

On Wed, Aug 22, 2012 at 12:53:06PM +0000, Arnd Bergmann wrote:
> I've created this series some time ago, and updated it now to
> v3.6-rc1. The idea is to get us a big step closer to the
> single zImage kernel across multiple ARM platforms by
> untangling the duplicate header file names.
> 
> There are two branches available in the arm-soc tree:
> 
> 1. This series,
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
>    This just moves header files around and changes most of the
>    files including them. There are a few remaining drivers
>    and platform files that keep including a generic file name
>    like <mach/uncompress.h>. It remains possible to do that,
>    and I've run extensive tests to ensure I did not break
>    anything with this. However, each of these instances means
>    that there is something that stops working when you get to
>    the real multiplatform kernel and we still need to deal
>    with them one by one.
> 
> 2. Actually enabling CONFIG_ARCH_MULTIPLATFORM
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/multiplatform
>    This builds on top of the first series, but is much more
>    experimental. It shows how a multiplatform kernel can look
>    like, by allowing to build vexpress, ux500, imx and omap2
>    together in one kernel, but at the same time breaking some of
>    their features.
> 
I just merged Marc's smp_ops branch below into above branch, and built
a kernel from there with vexpress and imx support together.

 git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git smp_ops-v3.5-rc2

The kernel boots fine on both imx5 and imx6, and I did not notice any
obvious feature breaking \o/

-- 
Regards,
Shawn


From robherring2 at gmail.com  Fri Aug 24 09:44:51 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 24 Aug 2012 08:44:51 -0500
Subject: [PATCH 1/4] [RFC] ARM: autogenerate mach-foo/* and plat-foo/*
 header redirects
In-Reply-To: <201208221254.22292.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221254.22292.arnd@arndb.de>
Message-ID: <50378553.5040102@gmail.com>

On 08/22/2012 07:54 AM, Arnd Bergmann wrote:
> This is an attempt to simplify the duplicate header problem for
> multiplatform kernels, in multiple steps:
> 
> 1. (this patch)
>    for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
>    generate a arch/arm/include/generated/mach/*.h file at build time,
>    same for plat-*.
> 
> 2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
>    arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
>    arch/arm/plat-${PLAT}/include/plat/*.h to
>    arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h
> 
> 3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
>    in all files where ${MACHINE} is known.
> 
> 4. ...
> 
> 5. Revert this patch again.
> 
> We can apply this patch at any time, and do step 2 at the end
> of the next merge window to minimize the potential for conflicts.
> We will also still need to deal with any inclusion of a mach/*
> file, but out of the 6355 ones we have today, I expect only a

Don't you mean 635? That's about what I counted in drivers/ and sound/.
It's important as 635 is within the realm of manually fixing, but 6355
is not. More comments comming on 0/4...

Rob


> few hundred to remain after step 3 and they will be much easier
> to spot.
> 
> I've picked the format <mach-foo/bar.h> to get a unique name because
> it matches the directory name under arch/arm, but other names
> would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
> have been suggested previously.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/Makefile          |    1 +
>  arch/arm/tools/Makefile    |    5 ++++
>  arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 63 insertions(+)
>  create mode 100755 arch/arm/tools/gen-headers
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 30eae87..761b077 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -274,6 +274,7 @@ boot := arch/arm/boot
>  
>  archprepare:
>         $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
> +       $(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
>  
>  # Convert bzImage to zImage
>  bzImage: zImage
> diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
> index 635cb18..6e18ca9 100644
> --- a/arch/arm/tools/Makefile
> +++ b/arch/arm/tools/Makefile
> @@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
>         @echo '  Generating $@'
>         @mkdir -p $(dir $@)
>         $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
> +
> +gen_headers:
> +       $(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
> +
> +.PHONY: gen_headers
> diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
> new file mode 100755
> index 0000000..caa6a9a
> --- /dev/null
> +++ b/arch/arm/tools/gen-headers
> @@ -0,0 +1,57 @@
> +#!/bin/bash
> +
> +SRC=$1
> +OBJ=$2
> +MACH=$3
> +PLAT1=$4
> +PLAT2=$5
> +
> +# create $3 to include $2 if it doesn't already have the correct
> +# contents, or remove it if it's no longer needed.
> +mkfile()
> +{
> +       if [ -e $1/$2 ] ; then
> +               if [ ! -e $3 ] ; then
> +                       mkdir -p ${3%/*}
> +                       echo "#include <${2}>" > $3
> +               elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
> +                       echo "#include <${2}>" > $3
> +               fi
> +       elif [ ! -e $1/$2 -a -e $3 ] ; then
> +               rm -f $3
> +       fi
> +}
> +
> +# list any header files that are present in the source or
> +# destination directories
> +find_files()
> +{
> +       pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
> +       find . -type f -name \*.h -o -name \*.S &&
> +       popd > /dev/null 2>&1
> +       pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
> +       find . -type f -name \*.h -o -name \*.S &&
> +       popd > /dev/null 2>&1
> +}
> +
> +# process files in either mach-{MACH} or plat-${PLAT}
> +mkfiles()
> +{
> +       mkdir -p ${OBJ}/arch/arm/include/generated/$1
> +
> +       FILES=`find_files $1 $2 | sort -u`
> +       for i in ${FILES} ; do
> +               mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
> +                       "${OBJ}/arch/arm/include/generated/$1/$i"
> +       done
> +}
> +
> +# always process mach-*
> +mkfiles mach ${MACH}
> +# process plat-* if applicable
> +if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
> +       mkfiles plat ${PLAT1}
> +fi
> +if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
> +       mkfiles plat ${PLAT2}
> +fi
> 



From philippe.langlais at st.com  Fri Aug 24 09:52:31 2012
From: philippe.langlais at st.com (Philippe LANGLAIS)
Date: Fri, 24 Aug 2012 15:52:31 +0200
Subject: [PATCH 1/1 v2] ARM: ux500: Provide SMSC911x fixed-regulator
 when not booting DT
In-Reply-To: <1345812481-2384-1-git-send-email-lee.jones@linaro.org>
References: <1345812481-2384-1-git-send-email-lee.jones@linaro.org>
Message-ID: <5037871F.7080300@st.com>

Hi Lee,

I have checked in Snowball schematics and I can confirm that the fixed
3.3V regulator is GPIO26 on AB8500 not DB8500, so its numero is 
MOP500_AB8500_PIN_GPIO(26)
and you have first to update the upstream gpio-ab8500 driver.

BR,
Philippe

On 08/24/2012 02:48 PM, Lee Jones wrote:
> The SMSC911x Ethernet chip requires a fixed-regulator in order to
> function correctly. We have previously provided a means to obtain
> this during a Device Tree boot, however nothing has been put into
> place when booting with a non-DT kernel. This patch aims to change
> that.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>   arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
>   arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
>   arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
>   arch/arm/mach-ux500/board-mop500.h            |    2 +-
>   4 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
> index 52426a4..139f31e 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.c
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
> @@ -13,6 +13,23 @@
>   #include <linux/regulator/ab8500.h>
>   #include "board-mop500-regulators.h"
>   
> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> +static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
> +	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> +};
> +
> +struct regulator_init_data gpio_en_3v3_regulator = {
> +	.constraints = {
> +		.name = "EN-3V3",
> +		.min_uV = 3300000,
> +		.max_uV = 3300000,
> +		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
> +	},
> +	.num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
> +	.consumer_supplies = gpio_en_3v3_consumers,
> +};
> +#endif
> +
>   /*
>    * TPS61052 regulator
>    */
> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
> index 9499215..78a0642 100644
> --- a/arch/arm/mach-ux500/board-mop500-regulators.h
> +++ b/arch/arm/mach-ux500/board-mop500-regulators.h
> @@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
>   ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
>   extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
>   extern struct regulator_init_data tps61052_regulator;
> +extern struct regulator_init_data gpio_en_3v3_regulator;
>   
>   #endif
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index 42e1759..c7f0973 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -23,6 +23,7 @@
>   #include <linux/spi/spi.h>
>   #include <linux/mfd/abx500/ab8500.h>
>   #include <linux/regulator/ab8500.h>
> +#include <linux/regulator/fixed.h>
>   #include <linux/mfd/tc3589x.h>
>   #include <linux/mfd/tps6105x.h>
>   #include <linux/mfd/abx500/ab8500-gpio.h>
> @@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
>   	},
>   };
>   
> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> +static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
> +	.supply_name		= "EN-3V3",
> +	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
> +	.microvolts		= 3300000,
> +	.enable_high		= 1,
> +	.init_data		= &gpio_en_3v3_regulator,
> +	.startup_delay		= 5000, /* 1200us */
> +};
> +
> +static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
> +	.name	= "reg-fixed-voltage",
> +	.id	= 1,
> +	.dev	= {
> +		.platform_data	= &snowball_gpio_en_3v3_data,
> +	},
> +};
> +#endif
> +
>   static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
>   	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
>   	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
> @@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
>   	&snowball_led_dev,
>   	&snowball_key_dev,
>   	&snowball_sbnet_dev,
> +	&snowball_gpio_en_3v3_regulator_dev,
>   };
>   
>   static void __init mop500_init_machine(void)
> diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
> index 9e9dd5a..d3a02d5 100644
> --- a/arch/arm/mach-ux500/board-mop500.h
> +++ b/arch/arm/mach-ux500/board-mop500.h
> @@ -13,6 +13,7 @@
>   #include <linux/amba/mmci.h>
>   
>   /* Snowball specific GPIO assignments, this board has no GPIO expander */
> +#define SNOWBALL_EN_3V3_ETH_GPIO	26
No it's MOP500_AB8500_PIN_GPIO(26)
>   #define SNOWBALL_ACCEL_INT1_GPIO	163
>   #define SNOWBALL_ACCEL_INT2_GPIO	164
>   #define SNOWBALL_MAGNET_DRDY_GPIO	165
> @@ -76,7 +77,6 @@
>   #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
>   #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
>   #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
> -#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
keep this line
>   
>   struct device;
>   struct i2c_board_info;


From robherring2 at gmail.com  Fri Aug 24 09:55:33 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 24 Aug 2012 08:55:33 -0500
Subject: [PATCH 0/4] [RFC] ARM: multiplatform: rename all mach headers
In-Reply-To: <201208221253.07278.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
Message-ID: <503787D5.7040401@gmail.com>

On 08/22/2012 07:53 AM, Arnd Bergmann wrote:
> I've created this series some time ago, and updated it now to
> v3.6-rc1. The idea is to get us a big step closer to the
> single zImage kernel across multiple ARM platforms by
> untangling the duplicate header file names.
> 
> There are two branches available in the arm-soc tree:
> 
> 1. This series,
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
>    This just moves header files around and changes most of the
>    files including them. There are a few remaining drivers
>    and platform files that keep including a generic file name
>    like <mach/uncompress.h>. It remains possible to do that,
>    and I've run extensive tests to ensure I did not break
>    anything with this. However, each of these instances means
>    that there is something that stops working when you get to
>    the real multiplatform kernel and we still need to deal
>    with them one by one.
> 
> 2. Actually enabling CONFIG_ARCH_MULTIPLATFORM
>    http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/multiplatform
>    This builds on top of the first series, but is much more
>    experimental. It shows how a multiplatform kernel can look
>    like, by allowing to build vexpress, ux500, imx and omap2
>    together in one kernel, but at the same time breaking some of
>    their features.

Can't we treat these as independent problems? The mach headers are a
problem for enabling some (most) platforms, but strictly speaking are
not a blocker for enabling multi-platform builds. I successfully built
highbank and vexpress without all this header renaming. This did require
pushing the mach/plat include path down into the mach directory for
vexpress adding this to its Makefile:

ccflags-y := -I$(srctree)/$(src)/include
-I$(srctree)/arch/arm/plat-versatile/include

Any new DT only platforms probably don't even need this.

I think fixing the headers by adding mach names doesn't force further
clean-up of drivers. I suspect there are still drivers which get their
irq number from an include rather than a resource for example.

A quarter of the 600 something includes are hardware.h which pulls in
anything and everything. I removed them and did a build. At least with
pxa, there's only a handful of errors and nearly all where on cpu_is_X
not being defined. This is something we should implement in a
standardized way or figure out how to remove.

Rob

> I would like to get the first series merged in v3.7 if we can agree
> on the general approach. So far, feedback in Linaro internal
> meetings has been very positive, but Russell had concerns when
> we first discussed it a few months ago.
> 
> A patch set this large means a lot of churn, and there are a few
> ways we could deal with this:
> 
> a) Put the branch into linux-next now, and have everyone who
> encounters conflicts pull it into their own branch to resolve
> the conflicts. This can be a lot of work, and it means we
> cannot rebase this branch any more.
> 
> b) Involve Linus Torvalds in the process and get him to
> take the series at the end of the v3.7 merge window, after
> rebasing it on top of all the other branches he merged.
> This means it happens pretty much ad-hoc and there is little
> testing on the patches that actually get merged.
> 
> c) Split the series and submit the first two branches at
> the start of the merge window, and do the changes to all
> the drivers either at the end of the v3.7 merge window
> (after rebasing) or merge them through the subsystem
> maintainer trees in small chunks for v3.8. This can minimize
> the problems of the other two approaches, but means the process
> takes longer to get to the same result.
> 
>         Arnd
> 
> [second attempt to send these patches, the first one was rejected by
> lists.infradead.org, this one uses a different smtp setup]
> 
> Arnd Bergmann (4):
>   [RFC] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
>   [RFC] ARM: mass move of mach-*/plat-* header files
>   [RFC] ARM: treewide: scripted conversion to mach-*/*.h
>   [RFC] ARM: treewide: manually change more mach-*/*.h includes
> 
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>    0.0% drivers/video/backlight/
>    0.0% drivers/video/exynos/
>    0.0% drivers/video/msm/
>    0.0% drivers/video/omap/
>    0.0% drivers/video/omap2/dss/
>    0.0% drivers/video/omap2/omapfb/
>    0.0% drivers/video/omap2/
>    0.0% drivers/video/pnx4008/
>    0.0% drivers/video/
>    0.0% drivers/w1/masters/
>    0.0% drivers/watchdog/
>    0.0% include/linux/mfd/
>    0.0% include/linux/platform_data/
>    0.0% include/linux/power/
>    0.0% include/linux/spi/
>    0.0% include/linux/
>    0.0% sound/arm/
>    0.0% sound/atmel/
>    0.0% sound/oss/
>    0.0% sound/soc/atmel/
>    0.0% sound/soc/davinci/
>    0.0% sound/soc/ep93xx/
>    0.0% sound/soc/fsl/
>    0.0% sound/soc/kirkwood/
>    0.0% sound/soc/mxs/
>    0.0% sound/soc/nuc900/
>    0.0% sound/soc/omap/
>    0.0% sound/soc/pxa/
>    0.0% sound/soc/samsung/
>    0.0% sound/soc/tegra/
>    0.0% sound/soc/ux500/
> 
> 
> _______________________________________________
> linaro-kernel mailing list
> linaro-kernel at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-kernel
> 



From lee.jones at linaro.org  Fri Aug 24 10:01:36 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:36 +0100
Subject: [PATCH 00/17] MOP500 Audio fix-ups and DT enablement
Message-ID: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>

This patch-set provides the MOP500 Audio driver with a few small
fix-ups along with Device Tree enablement for MOP500 Core and the
MSPs. You'll notice that we've left the PCM out for the time being
and continue to register that using platform code. This is because
we're still in the middle of discussions pertaining to how this
pseudo-device should be handled. We also pass pinctrl responsibility
to the MSP driver instead of setting it up in platform code, which
is an unnecessary over-head. 

 Documentation/devicetree/bindings/mfd/ab8500.txt   |   15 ++
 .../devicetree/bindings/sound/ux500-mop500.txt     |   39 +++
 .../devicetree/bindings/sound/ux500-msp.txt        |   43 ++++
 arch/arm/boot/dts/dbx5x0.dtsi                      |   39 +++
 arch/arm/boot/dts/snowball.dts                     |   16 ++
 arch/arm/mach-ux500/Makefile                       |    2 +-
 arch/arm/mach-ux500/board-mop500-audio.c           |  199 +++++++++++++++
 arch/arm/mach-ux500/board-mop500-msp.c             |  267 --------------------
 arch/arm/mach-ux500/board-mop500-msp.h             |   14 -
 arch/arm/mach-ux500/board-mop500.c                 |   22 +-
 arch/arm/mach-ux500/board-mop500.h                 |    8 +
 arch/arm/mach-ux500/include/mach/msp.h             |    2 -
 include/linux/mfd/abx500/ab8500-codec.h            |    6 +-
 sound/soc/codecs/ab8500-codec.c                    |   81 ++++++
 sound/soc/ux500/mop500.c                           |   47 +++-
 sound/soc/ux500/ux500_msp_dai.c                    |    6 +
 sound/soc/ux500/ux500_msp_i2s.c                    |   89 +++++--
 sound/soc/ux500/ux500_msp_i2s.h                    |    8 +-
 18 files changed, 584 insertions(+), 319 deletions(-)



From lee.jones at linaro.org  Fri Aug 24 10:01:37 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:37 +0100
Subject: [PATCH 01/17] ASoC: Ux500: Move MSP pinctrl setup into the MSP driver
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-2-git-send-email-lee.jones@linaro.org>

In the initial submission of the MSP driver msp1 and msp3's associated
pinctrl mechanism was passed back to platform code using a plat_init()
call-back routine, but it has no place in platform code. The MSP driver
should set this up for the appropriate ports. Instead we use a use_pinctrl
identifier which is passed from platform_data/Device Tree which indicates
which ports should use pinctrl.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   75 +-------------------------------
 arch/arm/mach-ux500/include/mach/msp.h |    2 -
 sound/soc/ux500/ux500_msp_i2s.c        |   67 +++++++++++++++++++++-------
 sound/soc/ux500/ux500_msp_i2s.h        |    8 +++-
 4 files changed, 58 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index df15646..fc78d5d 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -23,53 +23,6 @@
 #include "devices-db8500.h"
 #include "pins-db8500.h"
 
-/* MSP1/3 Tx/Rx usage protection */
-static DEFINE_SPINLOCK(msp_rxtx_lock);
-
-/* Reference Count */
-static int msp_rxtx_ref;
-
-/* Pin modes */
-struct pinctrl *msp1_p;
-struct pinctrl_state *msp1_def;
-struct pinctrl_state *msp1_sleep;
-
-int msp13_i2s_init(void)
-{
-	int retval = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&msp_rxtx_lock, flags);
-	if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
-		retval = pinctrl_select_state(msp1_p, msp1_def);
-		if (retval)
-			pr_err("could not set MSP1 defstate\n");
-	}
-	if (!retval)
-		msp_rxtx_ref++;
-	spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-	return retval;
-}
-
-int msp13_i2s_exit(void)
-{
-	int retval = 0;
-	unsigned long flags;
-
-	spin_lock_irqsave(&msp_rxtx_lock, flags);
-	WARN_ON(!msp_rxtx_ref);
-	msp_rxtx_ref--;
-	if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
-		retval = pinctrl_select_state(msp1_p, msp1_sleep);
-		if (retval)
-			pr_err("could not set MSP1 sleepstate\n");
-	}
-	spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-	return retval;
-}
-
 static struct stedma40_chan_cfg msp0_dma_rx = {
 	.high_priority = true,
 	.dir = STEDMA40_PERIPH_TO_MEM,
@@ -132,8 +85,6 @@ static struct msp_i2s_platform_data msp1_platform_data = {
 	.id = MSP_I2S_1,
 	.msp_i2s_dma_rx = NULL,
 	.msp_i2s_dma_tx = &msp1_dma_tx,
-	.msp_i2s_init = msp13_i2s_init,
-	.msp_i2s_exit = msp13_i2s_exit,
 };
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -219,47 +170,23 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.id		= MSP_I2S_3,
 	.msp_i2s_dma_rx	= &msp1_dma_rx,
 	.msp_i2s_dma_tx	= NULL,
-	.msp_i2s_init = msp13_i2s_init,
-	.msp_i2s_exit = msp13_i2s_exit,
 };
 
 int mop500_msp_init(struct device *parent)
 {
-	struct platform_device *msp1;
-
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
 	platform_device_register(&snd_soc_mop500);
 
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
 			   &msp0_platform_data);
-	msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
 			   &msp1_platform_data);
 	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
 			   &msp2_platform_data);
 	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
 			   &msp3_platform_data);
 
-	/* Get the pinctrl handle for MSP1 */
-	if (msp1) {
-		msp1_p = pinctrl_get(&msp1->dev);
-		if (IS_ERR(msp1_p))
-			dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
-		else {
-			msp1_def = pinctrl_lookup_state(msp1_p,
-							PINCTRL_STATE_DEFAULT);
-			if (IS_ERR(msp1_def)) {
-				dev_err(&msp1->dev,
-					"could not get MSP1 defstate\n");
-			}
-			msp1_sleep = pinctrl_lookup_state(msp1_p,
-							  PINCTRL_STATE_SLEEP);
-			if (IS_ERR(msp1_sleep))
-				dev_err(&msp1->dev,
-					"could not get MSP1 idlestate\n");
-		}
-	}
-
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
 
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19..3cc7142 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
 	enum msp_i2s_id id;
 	struct stedma40_chan_cfg *msp_i2s_dma_rx;
 	struct stedma40_chan_cfg *msp_i2s_dma_tx;
-	int (*msp_i2s_init) (void);
-	int (*msp_i2s_exit) (void);
 };
 
 #endif
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index 36be11e..08813c5 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -15,6 +15,7 @@
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 
@@ -25,6 +26,9 @@
 
 #include "ux500_msp_i2s.h"
 
+/* MSP1/3 Tx/Rx usage protection */
+static DEFINE_SPINLOCK(msp_rxtx_lock);
+
  /* Protocol desciptors */
 static const struct msp_protdesc prot_descs[] = {
 	{ /* I2S */
@@ -352,17 +356,23 @@ static int configure_multichannel(struct ux500_msp *msp,
 
 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
 {
-	int status = 0;
+	int status = 0, retval = 0;
 	u32 reg_val_DMACR, reg_val_GCR;
+	unsigned long flags;
 
 	/* Check msp state whether in RUN or CONFIGURED Mode */
-	if ((msp->msp_state == MSP_STATE_IDLE) && (msp->plat_init)) {
-		status = msp->plat_init();
-		if (status) {
-			dev_err(msp->dev, "%s: ERROR: Failed to init MSP (%d)!\n",
-				__func__, status);
-			return status;
+	if (msp->msp_state == MSP_STATE_IDLE) {
+		spin_lock_irqsave(&msp_rxtx_lock, flags);
+		if (msp->pinctrl_rxtx_ref == 0 &&
+			!(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) {
+			retval = pinctrl_select_state(msp->pinctrl_p,
+						msp->pinctrl_def);
+			if (retval)
+				pr_err("could not set MSP defstate\n");
 		}
+		if (!retval)
+			msp->pinctrl_rxtx_ref++;
+		spin_unlock_irqrestore(&msp_rxtx_lock, flags);
 	}
 
 	/* Configure msp with protocol dependent settings */
@@ -620,7 +630,8 @@ int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
 
 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
 {
-	int status = 0;
+	int status = 0, retval = 0;
+	unsigned long flags;
 
 	dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
 
@@ -631,12 +642,19 @@ int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
 		writel((readl(msp->registers + MSP_GCR) &
 			       (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
 			      msp->registers + MSP_GCR);
-		if (msp->plat_exit)
-			status = msp->plat_exit();
-			if (status)
-				dev_warn(msp->dev,
-					"%s: WARN: ux500_msp_i2s_exit failed (%d)!\n",
-					__func__, status);
+
+		spin_lock_irqsave(&msp_rxtx_lock, flags);
+		WARN_ON(!msp->pinctrl_rxtx_ref);
+		msp->pinctrl_rxtx_ref--;
+		if (msp->pinctrl_rxtx_ref == 0 &&
+			!(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) {
+			retval = pinctrl_select_state(msp->pinctrl_p,
+						msp->pinctrl_sleep);
+			if (retval)
+				pr_err("could not set MSP sleepstate\n");
+		}
+		spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+
 		writel(0, msp->registers + MSP_GCR);
 		writel(0, msp->registers + MSP_TCF);
 		writel(0, msp->registers + MSP_RCF);
@@ -678,8 +696,6 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 
 	msp->id = platform_data->id;
 	msp->dev = &pdev->dev;
-	msp->plat_init = platform_data->msp_i2s_init;
-	msp->plat_exit = platform_data->msp_i2s_exit;
 	msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
 	msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
 
@@ -717,6 +733,25 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 	dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
 	msp->i2s_cont = i2s_cont;
 
+	msp->pinctrl_p = pinctrl_get(msp->dev);
+	if (IS_ERR(msp->pinctrl_p))
+		dev_err(&pdev->dev, "could not get MSP pinctrl\n");
+	else {
+		msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p,
+						PINCTRL_STATE_DEFAULT);
+		if (IS_ERR(msp->pinctrl_def)) {
+			dev_err(&pdev->dev,
+				"could not get MSP defstate (%li)\n",
+				PTR_ERR(msp->pinctrl_def));
+		}
+		msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p,
+						PINCTRL_STATE_SLEEP);
+		if (IS_ERR(msp->pinctrl_sleep))
+			dev_err(&pdev->dev,
+				"could not get MSP idlestate (%li)\n",
+				PTR_ERR(msp->pinctrl_def));
+	}
+
 	return 0;
 
 err_i2s_cont:
diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h
index 2d9136d..1311c0d 100644
--- a/sound/soc/ux500/ux500_msp_i2s.h
+++ b/sound/soc/ux500/ux500_msp_i2s.h
@@ -524,14 +524,18 @@ struct ux500_msp {
 	struct dma_chan *rx_pipeid;
 	enum msp_state msp_state;
 	int (*transfer) (struct ux500_msp *msp, struct i2s_message *message);
-	int (*plat_init) (void);
-	int (*plat_exit) (void);
 	struct timer_list notify_timer;
 	int def_elem_len;
 	unsigned int dir_busy;
 	int loopback_enable;
 	u32 backup_regs[MAX_MSP_BACKUP_REGS];
 	unsigned int f_bitclk;
+	/* Pin modes */
+	struct pinctrl *pinctrl_p;
+	struct pinctrl_state *pinctrl_def;
+	struct pinctrl_state *pinctrl_sleep;
+	/* Reference Count */
+	int pinctrl_rxtx_ref;
 };
 
 struct ux500_msp_dma_params {
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:38 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:38 +0100
Subject: [PATCH 02/17] ASoC: Ux500: Enable MOP500 driver for Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-3-git-send-email-lee.jones@linaro.org>

Here we ensure that the MOP500 audio driver will be probed during a
Device Tree boot. We also parse the sound node to link together the
codec, dma and the CPU-side Digital Audio Interface.

CC: alsa-devel at alsa-project.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/mop500.c |   40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/sound/soc/ux500/mop500.c b/sound/soc/ux500/mop500.c
index 31c4d26..6840df7 100644
--- a/sound/soc/ux500/mop500.c
+++ b/sound/soc/ux500/mop500.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/spi/spi.h>
+#include <linux/of.h>
 
 #include <sound/soc.h>
 #include <sound/initval.h>
@@ -56,8 +57,35 @@ static struct snd_soc_card mop500_card = {
 	.num_links = ARRAY_SIZE(mop500_dai_links),
 };
 
+static int __devinit mop500_of_probe(struct platform_device *pdev,
+				struct device_node *np)
+{
+	struct device_node *codec_np, *msp_np[2];
+	int i;
+
+	msp_np[0] = of_parse_phandle(np, "stericsson,cpu-dai", 0);
+	msp_np[1] = of_parse_phandle(np, "stericsson,cpu-dai", 1);
+	codec_np  = of_parse_phandle(np, "stericsson,audio-codec", 0);
+
+	if (!(msp_np[0] && msp_np[1] && codec_np)) {
+		dev_err(&pdev->dev, "Phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < 2; i++) {
+		mop500_dai_links[i].cpu_of_node = msp_np[i];
+		mop500_dai_links[i].cpu_dai_name = NULL;
+		mop500_dai_links[i].codec_of_node = codec_np;
+		mop500_dai_links[i].codec_name = NULL;
+	}
+
+	snd_soc_of_parse_card_name(&mop500_card, "stericsson,card-name");
+
+	return 0;
+}
 static int __devinit mop500_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	int ret;
 
 	pr_debug("%s: Enter.\n", __func__);
@@ -66,6 +94,12 @@ static int __devinit mop500_probe(struct platform_device *pdev)
 
 	mop500_card.dev = &pdev->dev;
 
+	if (np) {
+		ret = mop500_of_probe(pdev, np);
+		if (ret)
+			return ret;
+	}
+
 	dev_dbg(&pdev->dev, "%s: Card %s: Set platform drvdata.\n",
 		__func__, mop500_card.name);
 	platform_set_drvdata(pdev, &mop500_card);
@@ -101,10 +135,16 @@ static int __devexit mop500_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id snd_soc_mop500_match[] = {
+	{ .compatible = "stericsson,snd-soc-mop500", },
+	{},
+};
+
 static struct platform_driver snd_soc_mop500_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = "snd-soc-mop500",
+		.of_match_table = snd_soc_mop500_match,
 	},
 	.probe = mop500_probe,
 	.remove = __devexit_p(mop500_remove),
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:39 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:39 +0100
Subject: [PATCH 03/17] ASoC: Ux500: Enable ux500 MSP driver for Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-4-git-send-email-lee.jones@linaro.org>

Register both parts of the MSP driver from Device Tree so that they
are probed when Device Tree is enabled. Also, as there is platform
data involved, we ensure that there is allocated memory to place the
configuration into and that the correct information is extracted from
the DT binary.

CC: alsa-devel at alsa-project.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/ux500_msp_dai.c |    6 ++++++
 sound/soc/ux500/ux500_msp_i2s.c |   22 +++++++++++++++++++---
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 772cb19..0f7dd49 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -833,10 +833,16 @@ static int __devexit ux500_msp_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct of_device_id ux500_msp_i2c_match[] = {
+	{ .compatible = "stericsson,ux500-msp-i2s", },
+	{},
+};
+
 static struct platform_driver msp_i2s_driver = {
 	.driver = {
 		.name = "ux500-msp-i2s",
 		.owner = THIS_MODULE,
+		.of_match_table = ux500_msp_i2c_match,
 	},
 	.probe = ux500_msp_drv_probe,
 	.remove = ux500_msp_drv_remove,
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index 08813c5..cb7bdae 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -18,6 +18,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <mach/hardware.h>
 #include <mach/msp.h>
@@ -684,16 +685,31 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 	int ret = 0;
 	struct resource *res = NULL;
 	struct i2s_controller *i2s_cont;
+	struct device_node *np = pdev->dev.of_node;
 	struct ux500_msp *msp;
 
-	dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
-		pdev->name, platform_data->id);
-
 	*msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
 	msp = *msp_p;
 	if (!msp)
 		return -ENOMEM;
 
+	if (np) {
+		if (!platform_data) {
+			platform_data = devm_kzalloc(&pdev->dev,
+				sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
+			if (!platform_data)
+				ret = -ENOMEM;
+		}
+	} else
+		if (!platform_data)
+			ret = -EINVAL;
+
+	if (ret)
+		goto err_res;
+
+	dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
+		pdev->name, platform_data->id);
+
 	msp->id = platform_data->id;
 	msp->dev = &pdev->dev;
 	msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:40 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:40 +0100
Subject: [PATCH 04/17] ASoC: codecs: Enable AB8500 CODEC for Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-5-git-send-email-lee.jones@linaro.org>

We continue to allow the AB8500 CODEC to be registered via the AB8500
Multi Functional Device API, only this time we extract its configuration
from the Device Tree binary.

CC: alsa-devel at alsa-project.org
Acked-by: Ola Lilja <ola.o.lilja at stericsson.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 include/linux/mfd/abx500/ab8500-codec.h |    6 ++-
 sound/soc/codecs/ab8500-codec.c         |   81 +++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/include/linux/mfd/abx500/ab8500-codec.h b/include/linux/mfd/abx500/ab8500-codec.h
index dc65292..d707941 100644
--- a/include/linux/mfd/abx500/ab8500-codec.h
+++ b/include/linux/mfd/abx500/ab8500-codec.h
@@ -23,7 +23,8 @@ enum amic_type {
 /* Mic-biases */
 enum amic_micbias {
 	AMIC_MICBIAS_VAMIC1,
-	AMIC_MICBIAS_VAMIC2
+	AMIC_MICBIAS_VAMIC2,
+	AMIC_MICBIAS_UNKNOWN
 };
 
 /* Bias-voltage */
@@ -31,7 +32,8 @@ enum ear_cm_voltage {
 	EAR_CMV_0_95V,
 	EAR_CMV_1_10V,
 	EAR_CMV_1_27V,
-	EAR_CMV_1_58V
+	EAR_CMV_1_58V,
+	EAR_CMV_UNKNOWN
 };
 
 /* Analog microphone settings */
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 23b4018..99dffcf 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -34,6 +34,7 @@
 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 #include <linux/mfd/abx500/ab8500-codec.h>
 #include <linux/regulator/consumer.h>
+#include <linux/of.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -2394,9 +2395,65 @@ struct snd_soc_dai_driver ab8500_codec_dai[] = {
 	}
 };
 
+static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
+				struct ab8500_codec_platform_data *codec)
+{
+	u32 value;
+
+	if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
+		codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
+
+	if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
+		codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
+	else
+		codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
+
+	/* Has a non-standard Vamic been requested? */
+	if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
+	else
+		codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
+
+	if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
+	else
+		codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
+
+	if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
+		switch (value) {
+		case 950 :
+			codec->ear_cmv = EAR_CMV_0_95V;
+			break;
+		case 1100 :
+			codec->ear_cmv = EAR_CMV_1_10V;
+			break;
+		case 1270 :
+			codec->ear_cmv = EAR_CMV_1_27V;
+			break;
+		case 1580 :
+			codec->ear_cmv = EAR_CMV_1_58V;
+			break;
+		default :
+			codec->ear_cmv = EAR_CMV_UNKNOWN;
+			dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
+		}
+	} else {
+		dev_warn(dev, "No earpiece voltage found in DT - using default\n");
+		codec->ear_cmv = EAR_CMV_0_95V;
+	}
+}
+
 static int ab8500_codec_probe(struct snd_soc_codec *codec)
 {
 	struct device *dev = codec->dev;
+	struct device_node *np = dev->of_node;
 	struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
 	struct ab8500_platform_data *pdata;
 	struct filter_control *fc;
@@ -2407,6 +2464,30 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
 	/* Setup AB8500 according to board-settings */
 	pdata = (struct ab8500_platform_data *)dev_get_platdata(dev->parent);
 
+	if (np) {
+		if (!pdata)
+			pdata = devm_kzalloc(dev,
+					sizeof(struct ab8500_platform_data),
+					GFP_KERNEL);
+
+		if (pdata && !pdata->codec)
+			pdata->codec
+				= devm_kzalloc(dev,
+					sizeof(struct ab8500_codec_platform_data),
+					GFP_KERNEL);
+
+		if (!(pdata && pdata->codec))
+			return -ENOMEM;
+
+		ab8500_codec_of_probe(dev, np, pdata->codec);
+
+	} else {
+		if (!(pdata && pdata->codec)) {
+			dev_err(dev, "No codec platform data or DT found\n");
+			return -EINVAL;
+		}
+	}
+
 	/* Inform SoC Core that we have our own I/O arrangements. */
 	codec->control_data = (void *)true;
 
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:41 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:41 +0100
Subject: [PATCH 05/17] ASoC: Ux500: Minor coding layout changes
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-6-git-send-email-lee.jones@linaro.org>

Includes removal of duplicate debug print affirming entry into
the probe function, an unnecessary line break of a coding line
<80 chars and a white space change (unintentional tab).

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 sound/soc/ux500/mop500.c |    7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/sound/soc/ux500/mop500.c b/sound/soc/ux500/mop500.c
index 6840df7..356611d 100644
--- a/sound/soc/ux500/mop500.c
+++ b/sound/soc/ux500/mop500.c
@@ -88,8 +88,6 @@ static int __devinit mop500_probe(struct platform_device *pdev)
 	struct device_node *np = pdev->dev.of_node;
 	int ret;
 
-	pr_debug("%s: Enter.\n", __func__);
-
 	dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
 
 	mop500_card.dev = &pdev->dev;
@@ -117,8 +115,7 @@ static int __devinit mop500_probe(struct platform_device *pdev)
 	ret = snd_soc_register_card(&mop500_card);
 	if (ret)
 		dev_err(&pdev->dev,
-			"Error: snd_soc_register_card failed (%d)!\n",
-			ret);
+			"Error: snd_soc_register_card failed (%d)!\n", ret);
 
 	return ret;
 }
@@ -131,7 +128,7 @@ static int __devexit mop500_remove(struct platform_device *pdev)
 
 	snd_soc_unregister_card(mop500_card);
 	mop500_ab8500_remove(mop500_card);
-	
+
 	return 0;
 }
 
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:42 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:42 +0100
Subject: [PATCH 06/17] Documentation: Define the MOP500 Audio Machine Driver
 Device Tree bindings
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-7-git-send-email-lee.jones@linaro.org>

Here we add the required documentation for the new Device Tree
bindings pertaining to the MOP500 Audio Machine driver.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/sound/ux500-mop500.txt     |   39 ++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ux500-mop500.txt

diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
new file mode 100644
index 0000000..48e071c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
@@ -0,0 +1,39 @@
+* MOP500 Audio Machine Driver
+
+This node is responsible for linking together all ux500 Audio Driver components.
+
+Required properties:
+ - compatible              : "stericsson,snd-soc-mop500"
+
+Non-standard properties:
+ - stericsson,cpu-dai      : Phandle to the CPU-side DAI
+ - stericsson,audio-codec  : Phandle to the Audio CODEC
+ - stericsson,card-name    : Over-ride default card name
+
+Example:
+
+	sound {
+		compatible = "stericsson,snd-soc-mop500";
+
+		stericsson,cpu-dai = <&msp1 &msp3>;
+		stericsson,audio-codec = <&codec>;
+	};
+
+	msp1: msp at 80124000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80124000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	msp3: msp at 80125000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80125000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:43 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:43 +0100
Subject: [PATCH 07/17] Documentation: Define the MSP Driver Device Tree
 bindings
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-8-git-send-email-lee.jones@linaro.org>

Here we add the required documentation for the new Device Tree
bindings pertaining to the MSP CPU-side DAI Driver.

CC: alsa-devel at alsa-project.org
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 .../devicetree/bindings/sound/ux500-msp.txt        |   43 ++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/ux500-msp.txt

diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt
new file mode 100644
index 0000000..99acd9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-msp.txt
@@ -0,0 +1,43 @@
+* ux500 MSP (CPU-side Digital Audio Interface)
+
+Required properties:
+ - compatible       :"stericsson,ux500-msp-i2s"
+ - reg              : Physical base address and length of the device's registers.
+
+Optional properties:
+ - interrupts       : The interrupt output from the device.
+ - interrupt-parent : The parent interrupt controller.
+ - <name>-supply    : Phandle to the regulator <name> supply
+
+Example:
+
+	sound {
+		compatible = "stericsson,snd-soc-mop500";
+
+		stericsson,platform-pcm-dma = <&pcm>;
+		stericsson,cpu-dai = <&msp1 &msp3>;
+		stericsson,audio-codec = <&codec>;
+	};
+
+	pcm: ux500-pcm {
+		compatible = "stericsson,ux500-pcm";
+	};
+
+	msp1: msp at 80124000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80124000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	msp3: msp at 80125000 {
+		compatible = "stericsson,ux500-msp-i2s";
+		reg = <0x80125000 0x1000>;
+		interrupts = <0 62 0x4>;
+		v-ape-supply = <&db8500_vape_reg>;
+	};
+
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:44 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:44 +0100
Subject: [PATCH 08/17] ARM: ux500: Clean-up MSP platform code
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-9-git-send-email-lee.jones@linaro.org>

This patch contains a couple of general MSP clean-ups pertaining to
layout changes and changing functions to be void instead of int instead
of regardlessly returning '0'.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   24 +++++++++++-------------
 arch/arm/mach-ux500/board-mop500-msp.h |   14 --------------
 arch/arm/mach-ux500/board-mop500.c     |    1 -
 arch/arm/mach-ux500/board-mop500.h     |    3 +++
 4 files changed, 14 insertions(+), 28 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/board-mop500-msp.h

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index fc78d5d..1a67577 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -144,20 +144,20 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 
 /* Platform device for ASoC MOP500 machine */
 static struct platform_device snd_soc_mop500 = {
-		.name = "snd-soc-mop500",
-		.id = 0,
-		.dev = {
-			.platform_data = NULL,
-		},
+	.name = "snd-soc-mop500",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
 };
 
 /* Platform device for Ux500-PCM */
 static struct platform_device ux500_pcm = {
-		.name = "ux500-pcm",
-		.id = 0,
-		.dev = {
-			.platform_data = NULL,
-		},
+	.name = "ux500-pcm",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
 };
 
 static struct msp_i2s_platform_data msp2_platform_data = {
@@ -172,7 +172,7 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
-int mop500_msp_init(struct device *parent)
+void mop500_msp_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
 	platform_device_register(&snd_soc_mop500);
@@ -189,6 +189,4 @@ int mop500_msp_init(struct device *parent)
 
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
-
-	return 0;
 }
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e..0000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja at stericsson.com>,
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5d9600b..11dd962 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -54,7 +54,6 @@
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-#include "board-mop500-msp.h"
 
 static struct gpio_led snowball_led_array[] = {
 	{
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d04a8e6..1d7316b 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -92,6 +92,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
+void mop500_msp_init(struct device *parent);
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_msp_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:45 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:45 +0100
Subject: [PATCH 09/17] ARM: ux500: Add AB8500 CODEC node to DB8500 Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-10-git-send-email-lee.jones@linaro.org>

Ensure correct probing and pass though important configuration
options to the AB8500 CODEC driver when DT is enabled

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c..7f8c9db 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -389,6 +389,12 @@
 					compatible = "stericsson,ab8500-debug";
 				};
 
+				codec: ab8500-codec {
+					compatible = "stericsson,ab8500-codec";
+
+					stericsson,earpeice-cmv = <950>; /* Units in mV. */
+				};
+
 				ab8500-regulators {
 					compatible = "stericsson,ab8500-regulator";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:46 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:46 +0100
Subject: [PATCH 10/17] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-11-git-send-email-lee.jones@linaro.org>

We've done this before and it worked well last time. Here we're
duplicating a complex registration function to ease the process
of enabling it for Device Tree. As there are quite a few steps
taken during the registration process, it makes sense to break
them up into more manageable chunks. This patch will aid us.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   20 ++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500.c     |    2 +-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 1a67577..24a3604 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -172,6 +172,26 @@ static struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_msp_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
+
+	pr_info("Initialize MSP I2S-devices.\n");
+	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+			   &msp0_platform_data);
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+			   &msp1_platform_data);
+	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+			   &msp2_platform_data);
+	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+			   &msp3_platform_data);
+
+	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+	platform_device_register(&ux500_pcm);
+}
+
 void mop500_msp_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 11dd962..8f419b1 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
 		mop500_uib_init();
 
 	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-		mop500_msp_init(parent);
+		mop500_of_msp_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:48 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:48 +0100
Subject: [PATCH 12/17] ARM: ux500: Stop registering the MOP500 Audio driver
 from platform code
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-13-git-send-email-lee.jones@linaro.org>

In this patch we prevent MOP500 driver registration from platform
code and rely solely on Device Tree to do the probing for us.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |    3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index ec802d0..41e4df2 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -175,9 +175,6 @@ struct msp_i2s_platform_data msp3_platform_data = {
 /* Due for removal once the MSP driver has been fully DT:ed. */
 void mop500_of_msp_init(struct device *parent)
 {
-	pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
-	platform_device_register(&snd_soc_mop500);
-
 	pr_info("Initialize MSP I2S-devices.\n");
 	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
 			   &msp0_platform_data);
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:47 +0100
Subject: [PATCH 11/17] ARM: ux500: Pass MSP DMA platform data though AUXDATA
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-12-git-send-email-lee.jones@linaro.org>

It isn't currently possible to pass all platform specific configuration
though Device Tree. Thinks like device names used in the clock
infrastructure, call-backs and DMA information have to be passed in via
AUXDATA structures and the MSP is no exception. Here we're passing DMA
settings.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |    8 ++++----
 arch/arm/mach-ux500/board-mop500.c     |    9 +++++++++
 arch/arm/mach-ux500/board-mop500.h     |    5 +++++
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 24a3604..ec802d0 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -49,7 +49,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
 	/* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp0_platform_data = {
+struct msp_i2s_platform_data msp0_platform_data = {
 	.id = MSP_I2S_0,
 	.msp_i2s_dma_rx = &msp0_dma_rx,
 	.msp_i2s_dma_tx = &msp0_dma_tx,
@@ -81,7 +81,7 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
 	/* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp1_platform_data = {
+struct msp_i2s_platform_data msp1_platform_data = {
 	.id = MSP_I2S_1,
 	.msp_i2s_dma_rx = NULL,
 	.msp_i2s_dma_tx = &msp1_dma_tx,
@@ -160,13 +160,13 @@ static struct platform_device ux500_pcm = {
 	},
 };
 
-static struct msp_i2s_platform_data msp2_platform_data = {
+struct msp_i2s_platform_data msp2_platform_data = {
 	.id = MSP_I2S_2,
 	.msp_i2s_dma_rx = &msp2_dma_rx,
 	.msp_i2s_dma_tx = &msp2_dma_tx,
 };
 
-static struct msp_i2s_platform_data msp3_platform_data = {
+struct msp_i2s_platform_data msp3_platform_data = {
 	.id		= MSP_I2S_3,
 	.msp_i2s_dma_rx	= &msp1_dma_rx,
 	.msp_i2s_dma_tx	= NULL,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8f419b1..0c141d5 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -758,6 +758,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 	/* Requires device name bindings. */
 	OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+	/* Requires clock name and DMA bindings. */
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+		"ux500-msp-i2s.0", &msp0_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+		"ux500-msp-i2s.1", &msp1_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+		"ux500-msp-i2s.2", &msp2_platform_data),
+	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+		"ux500-msp-i2s.3", &msp3_platform_data),
 	{},
 };
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 1d7316b..3fbf48f 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <mach/msp.h>
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -81,6 +82,10 @@ struct device;
 struct i2c_board_info;
 extern struct mmci_platform_data mop500_sdi0_data;
 extern struct mmci_platform_data mop500_sdi4_data;
+extern struct msp_i2s_platform_data msp0_platform_data;
+extern struct msp_i2s_platform_data msp1_platform_data;
+extern struct msp_i2s_platform_data msp2_platform_data;
+extern struct msp_i2s_platform_data msp3_platform_data;
 extern struct arm_pmu_platdata db8500_pmu_platdata;
 
 extern void mop500_sdi_init(struct device *parent);
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:49 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:49 +0100
Subject: [PATCH 13/17] ARM: ux500: Remove platform registration of MSP devices
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-14-git-send-email-lee.jones@linaro.org>

This patch removes platform device registration of all 4 MSP
devices. It also takes care of all redundant infrastructure now
that each of the ux500 audio components have been Device Tree
enabled.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500-msp.c |   10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 41e4df2..2af017f 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -175,16 +175,6 @@ struct msp_i2s_platform_data msp3_platform_data = {
 /* Due for removal once the MSP driver has been fully DT:ed. */
 void mop500_of_msp_init(struct device *parent)
 {
-	pr_info("Initialize MSP I2S-devices.\n");
-	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-			   &msp0_platform_data);
-	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
-			   &msp1_platform_data);
-	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
-			   &msp2_platform_data);
-	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
-			   &msp3_platform_data);
-
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
 }
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:50 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:50 +0100
Subject: [PATCH 14/17] ARM: ux500: Rename MSP board file to something more
 meaningful
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-15-git-send-email-lee.jones@linaro.org>

The 'msp' board file does more than just register MSP devices. It
also registers some other components necessary to get audio working
on ux500 based platforms; such as the PCM and Machine Drivers. For
that reason we're changing the filename to be more encompassing -
'audio'.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/Makefile             |    2 +-
 arch/arm/mach-ux500/board-mop500-audio.c |  199 ++++++++++++++++++++++++++++++
 arch/arm/mach-ux500/board-mop500-msp.c   |  199 ------------------------------
 arch/arm/mach-ux500/board-mop500.c       |   12 +-
 arch/arm/mach-ux500/board-mop500.h       |    4 +-
 5 files changed, 208 insertions(+), 208 deletions(-)
 create mode 100644 arch/arm/mach-ux500/board-mop500-audio.c
 delete mode 100644 arch/arm/mach-ux500/board-mop500-msp.c

diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086f..1dc2cfa 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
 				board-mop500-uib.o board-mop500-stuib.o \
 				board-mop500-u8500uib.o \
 				board-mop500-pins.o \
-				board-mop500-msp.o
+				board-mop500-audio.o
 obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
new file mode 100644
index 0000000..18f6c5a
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/consumer.h>
+
+#include <plat/gpio-nomadik.h>
+#include <plat/pincfg.h>
+#include <plat/ste_dma40.h>
+
+#include <mach/devices.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/msp.h>
+
+#include "ste-dma40-db8500.h"
+#include "board-mop500.h"
+#include "devices-db8500.h"
+#include "pins-db8500.h"
+
+static struct stedma40_chan_cfg msp0_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp0_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+struct msp_i2s_platform_data msp0_platform_data = {
+	.id = MSP_I2S_0,
+	.msp_i2s_dma_rx = &msp0_dma_rx,
+	.msp_i2s_dma_tx = &msp0_dma_tx,
+};
+
+static struct stedma40_chan_cfg msp1_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp1_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	/* data_width is set during configuration */
+};
+
+struct msp_i2s_platform_data msp1_platform_data = {
+	.id = MSP_I2S_1,
+	.msp_i2s_dma_rx = NULL,
+	.msp_i2s_dma_tx = &msp1_dma_tx,
+};
+
+static struct stedma40_chan_cfg msp2_dma_rx = {
+	.high_priority = true,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+
+	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+
+	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
+	.src_info.psize = STEDMA40_PSIZE_LOG_1,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
+
+	/* data_width is set during configuration */
+};
+
+static struct stedma40_chan_cfg msp2_dma_tx = {
+	.high_priority = true,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+
+	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
+
+	.src_info.psize = STEDMA40_PSIZE_LOG_4,
+	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+
+	.use_fixed_channel = true,
+	.phy_channel = 1,
+
+	/* data_width is set during configuration */
+};
+
+static struct platform_device *db8500_add_msp_i2s(struct device *parent,
+			int id,
+			resource_size_t base, int irq,
+			struct msp_i2s_platform_data *pdata)
+{
+	struct platform_device *pdev;
+	struct resource res[] = {
+		DEFINE_RES_MEM(base, SZ_4K),
+		DEFINE_RES_IRQ(irq),
+	};
+
+	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
+		id, irq);
+	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
+						res, ARRAY_SIZE(res),
+						pdata, sizeof(*pdata));
+	if (!pdev) {
+		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
+			id);
+		return NULL;
+	}
+
+	return pdev;
+}
+
+/* Platform device for ASoC MOP500 machine */
+static struct platform_device snd_soc_mop500 = {
+	.name = "snd-soc-mop500",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
+};
+
+/* Platform device for Ux500-PCM */
+static struct platform_device ux500_pcm = {
+	.name = "ux500-pcm",
+	.id = 0,
+	.dev = {
+		.platform_data = NULL,
+	},
+};
+
+struct msp_i2s_platform_data msp2_platform_data = {
+	.id = MSP_I2S_2,
+	.msp_i2s_dma_rx = &msp2_dma_rx,
+	.msp_i2s_dma_tx = &msp2_dma_tx,
+};
+
+struct msp_i2s_platform_data msp3_platform_data = {
+	.id		= MSP_I2S_3,
+	.msp_i2s_dma_rx	= &msp1_dma_rx,
+	.msp_i2s_dma_tx	= NULL,
+};
+
+void mop500_audio_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
+	platform_device_register(&snd_soc_mop500);
+
+	pr_info("Initialize MSP I2S-devices.\n");
+	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+			   &msp0_platform_data);
+	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+			   &msp1_platform_data);
+	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+			   &msp2_platform_data);
+	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+			   &msp3_platform_data);
+
+	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+	platform_device_register(&ux500_pcm);
+}
+
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+	platform_device_register(&ux500_pcm);
+}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
deleted file mode 100644
index 2af017f..0000000
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL), version 2
- */
-
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/pinctrl/consumer.h>
-
-#include <plat/gpio-nomadik.h>
-#include <plat/pincfg.h>
-#include <plat/ste_dma40.h>
-
-#include <mach/devices.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/msp.h>
-
-#include "ste-dma40-db8500.h"
-#include "board-mop500.h"
-#include "devices-db8500.h"
-#include "pins-db8500.h"
-
-static struct stedma40_chan_cfg msp0_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp0_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-struct msp_i2s_platform_data msp0_platform_data = {
-	.id = MSP_I2S_0,
-	.msp_i2s_dma_rx = &msp0_dma_rx,
-	.msp_i2s_dma_tx = &msp0_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp1_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp1_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	/* data_width is set during configuration */
-};
-
-struct msp_i2s_platform_data msp1_platform_data = {
-	.id = MSP_I2S_1,
-	.msp_i2s_dma_rx = NULL,
-	.msp_i2s_dma_tx = &msp1_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp2_dma_rx = {
-	.high_priority = true,
-	.dir = STEDMA40_PERIPH_TO_MEM,
-
-	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-	.src_info.psize = STEDMA40_PSIZE_LOG_1,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
-
-	/* data_width is set during configuration */
-};
-
-static struct stedma40_chan_cfg msp2_dma_tx = {
-	.high_priority = true,
-	.dir = STEDMA40_MEM_TO_PERIPH,
-
-	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
-	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
-
-	.src_info.psize = STEDMA40_PSIZE_LOG_4,
-	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-	.use_fixed_channel = true,
-	.phy_channel = 1,
-
-	/* data_width is set during configuration */
-};
-
-static struct platform_device *db8500_add_msp_i2s(struct device *parent,
-			int id,
-			resource_size_t base, int irq,
-			struct msp_i2s_platform_data *pdata)
-{
-	struct platform_device *pdev;
-	struct resource res[] = {
-		DEFINE_RES_MEM(base, SZ_4K),
-		DEFINE_RES_IRQ(irq),
-	};
-
-	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
-		id, irq);
-	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
-						res, ARRAY_SIZE(res),
-						pdata, sizeof(*pdata));
-	if (!pdev) {
-		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
-			id);
-		return NULL;
-	}
-
-	return pdev;
-}
-
-/* Platform device for ASoC MOP500 machine */
-static struct platform_device snd_soc_mop500 = {
-	.name = "snd-soc-mop500",
-	.id = 0,
-	.dev = {
-		.platform_data = NULL,
-	},
-};
-
-/* Platform device for Ux500-PCM */
-static struct platform_device ux500_pcm = {
-	.name = "ux500-pcm",
-	.id = 0,
-	.dev = {
-		.platform_data = NULL,
-	},
-};
-
-struct msp_i2s_platform_data msp2_platform_data = {
-	.id = MSP_I2S_2,
-	.msp_i2s_dma_rx = &msp2_dma_rx,
-	.msp_i2s_dma_tx = &msp2_dma_tx,
-};
-
-struct msp_i2s_platform_data msp3_platform_data = {
-	.id		= MSP_I2S_3,
-	.msp_i2s_dma_rx	= &msp1_dma_rx,
-	.msp_i2s_dma_tx	= NULL,
-};
-
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent)
-{
-	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-	platform_device_register(&ux500_pcm);
-}
-
-void mop500_msp_init(struct device *parent)
-{
-	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
-	platform_device_register(&snd_soc_mop500);
-
-	pr_info("Initialize MSP I2S-devices.\n");
-	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
-			   &msp0_platform_data);
-	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
-			   &msp1_platform_data);
-	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
-			   &msp2_platform_data);
-	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
-			   &msp3_platform_data);
-
-	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-	platform_device_register(&ux500_pcm);
-}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0c141d5..7152635 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -607,7 +607,7 @@ static void __init mop500_init_machine(void)
 	mop500_i2c_init(parent);
 	mop500_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	u8500_cryp1_hash1_init(parent);
@@ -641,7 +641,7 @@ static void __init snowball_init_machine(void)
 	mop500_i2c_init(parent);
 	snowball_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	/* This board has full regulator constraints */
@@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
 	mop500_i2c_init(parent);
 	hrefv60_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		mop500_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 		i2c_register_board_info(2, mop500_i2c2_devices,
@@ -816,7 +816,7 @@ static void __init u8500_init_machine(void)
 		mop500_uib_init();
 
 	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-		mop500_of_msp_init(parent);
+		mop500_of_audio_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
@@ -828,7 +828,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		hrefv60_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3fbf48f..9e9dd5a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -97,9 +97,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
-void mop500_msp_init(struct device *parent);
+void mop500_audio_init(struct device *parent);
 /* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent);
+void mop500_of_audio_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:51 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:51 +0100
Subject: [PATCH 15/17] ARM: ux500: Add nodes for the MSP into Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-16-git-send-email-lee.jones@linaro.org>

This patch inserts all known MSP devices into the DBx5x0 Device Tree
disabled and enables the two important ones for the Snowball low-cost
development board.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/dbx5x0.dtsi  |   33 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts |    8 ++++++++
 2 files changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 7f8c9db..b297957 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -586,6 +586,39 @@
 			status = "disabled";
 		};
 
+		msp0: msp at 80123000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80123000 0x1000>;
+			interrupts = <0 31 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		msp1: msp at 80124000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80124000 0x1000>;
+			interrupts = <0 62 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		// HDMI sound
+		msp2: msp at 80117000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80117000 0x1000>;
+			interrupts = <0 98 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
+		msp3: msp at 80125000 {
+			compatible = "stericsson,ux500-msp-i2s";
+			reg = <0x80125000 0x1000>;
+			interrupts = <0 62 0x4>;
+			v-ape-supply = <&db8500_vape_reg>;
+			status = "disabled";
+		};
+
 		external-bus at 50000000 {
 			compatible = "simple-bus";
 			reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index df6fc57..fce4a00 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -83,6 +83,14 @@
 	};
 
 	soc-u9500 {
+		msp1: msp at 80124000 {
+			status = "okay";
+		};
+
+		msp3: msp at 80125000 {
+			status = "okay";
+		};
+
 		external-bus at 50000000 {
 			status = "okay";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:52 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:52 +0100
Subject: [PATCH 16/17] ARM: ux500: Add all encompassing sound node to the
 Snowball Device Tree
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-17-git-send-email-lee.jones@linaro.org>

This is where we link together all of the SoC sound components for
a given platform. This all encompassing sound node is only found
in the very lowest hierarchical DTS file, since the component mix may
well change from board variant to board variant.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/snowball.dts |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index fce4a00..2969997 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -83,6 +83,14 @@
 	};
 
 	soc-u9500 {
+
+		sound {
+			compatible = "stericsson,snd-soc-mop500";
+
+			stericsson,cpu-dai = <&msp1 &msp3>;
+			stericsson,audio-codec = <&codec>;
+		};
+
 		msp1: msp at 80124000 {
 			status = "okay";
 		};
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:01:53 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:01:53 +0100
Subject: [PATCH 17/17] Documentation: Add the AB8500 CODEC device to the MFD
 AB8500 doc
In-Reply-To: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1345816913-4113-18-git-send-email-lee.jones@linaro.org>

Here we document the AB8500 Audio CODEC in the existing MFD AB8500 document.

CC: alsa-devel at alsa-project.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/mfd/ab8500.txt |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index 69e757a..ce83c8d 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -23,6 +23,7 @@ Device                     IRQ Names              Supply Names   Description
 ab8500-bm                :                      :              : Battery Manager
 ab8500-btemp             :                      :              : Battery Temperature
 ab8500-charger           :                      :              : Battery Charger
+ab8500-codec             :                      :              : Audio Codec
 ab8500-fg                :                      :              : Fuel Gauge
 ab8500-gpadc             : HW_CONV_END          : vddadc       : Analogue to Digital Converter
                            SW_CONV_END          :              :
@@ -52,6 +53,14 @@ Optional child device properties:
                            supplied in the interrupts property
 - <supply_name>-supply   : contains a phandle to the regulator supply node in Device Tree
 
+Non-standard child device properties:
+ - Audio CODEC:
+   - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential)
+   - stericsson,amic1a-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic1b-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic2-bias-vamic1           : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,earpeice-cmv                : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
+
 ab8500 at 5 {
          compatible = "stericsson,ab8500";
          reg = <5>; /* mailbox 5 is i2c */
@@ -110,6 +119,12 @@ ab8500 at 5 {
                 compatible = "stericsson,ab8500-pwm";
         };
 
+	codec: ab8500-codec {
+		compatible = "stericsson,ab8500-codec";
+
+		stericsson,earpeice-cmv = <950>; /* Units in mV. */
+	};
+
         ab8500-regulators {
                 compatible = "stericsson,ab8500-regulator";
 
-- 
1.7.9.5



From lee.jones at linaro.org  Fri Aug 24 10:08:51 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 15:08:51 +0100
Subject: [PATCH 1/1 v2] ARM: ux500: Provide SMSC911x fixed-regulator when
 not booting DT
In-Reply-To: <5037871F.7080300@st.com>
References: <1345812481-2384-1-git-send-email-lee.jones@linaro.org>
 <5037871F.7080300@st.com>
Message-ID: <20120824140849.GM32491@gmail.com>

> I have checked in Snowball schematics and I can confirm that the fixed
> 3.3V regulator is GPIO26 on AB8500 not DB8500, so its numero is 
> MOP500_AB8500_PIN_GPIO(26)

We're also using GPIO26 on the DB8500 in the Device Tree solution.
Odd that is should work? I wonder if we're just getting lucky, or if
it's just not required?

> and you have first to update the upstream gpio-ab8500 driver.

I see. Do you know what needs to be updated to get it working?

> On 08/24/2012 02:48 PM, Lee Jones wrote:
> > The SMSC911x Ethernet chip requires a fixed-regulator in order to
> > function correctly. We have previously provided a means to obtain
> > this during a Device Tree boot, however nothing has been put into
> > place when booting with a non-DT kernel. This patch aims to change
> > that.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> > ---
> >   arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
> >   arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
> >   arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
> >   arch/arm/mach-ux500/board-mop500.h            |    2 +-
> >   4 files changed, 40 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
> > index 52426a4..139f31e 100644
> > --- a/arch/arm/mach-ux500/board-mop500-regulators.c
> > +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
> > @@ -13,6 +13,23 @@
> >   #include <linux/regulator/ab8500.h>
> >   #include "board-mop500-regulators.h"
> >   
> > +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> > +static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
> > +	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> > +};
> > +
> > +struct regulator_init_data gpio_en_3v3_regulator = {
> > +	.constraints = {
> > +		.name = "EN-3V3",
> > +		.min_uV = 3300000,
> > +		.max_uV = 3300000,
> > +		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
> > +	},
> > +	.num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
> > +	.consumer_supplies = gpio_en_3v3_consumers,
> > +};
> > +#endif
> > +
> >   /*
> >    * TPS61052 regulator
> >    */
> > diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
> > index 9499215..78a0642 100644
> > --- a/arch/arm/mach-ux500/board-mop500-regulators.h
> > +++ b/arch/arm/mach-ux500/board-mop500-regulators.h
> > @@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
> >   ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
> >   extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
> >   extern struct regulator_init_data tps61052_regulator;
> > +extern struct regulator_init_data gpio_en_3v3_regulator;
> >   
> >   #endif
> > diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> > index 42e1759..c7f0973 100644
> > --- a/arch/arm/mach-ux500/board-mop500.c
> > +++ b/arch/arm/mach-ux500/board-mop500.c
> > @@ -23,6 +23,7 @@
> >   #include <linux/spi/spi.h>
> >   #include <linux/mfd/abx500/ab8500.h>
> >   #include <linux/regulator/ab8500.h>
> > +#include <linux/regulator/fixed.h>
> >   #include <linux/mfd/tc3589x.h>
> >   #include <linux/mfd/tps6105x.h>
> >   #include <linux/mfd/abx500/ab8500-gpio.h>
> > @@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
> >   	},
> >   };
> >   
> > +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
> > +static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
> > +	.supply_name		= "EN-3V3",
> > +	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
> > +	.microvolts		= 3300000,
> > +	.enable_high		= 1,
> > +	.init_data		= &gpio_en_3v3_regulator,
> > +	.startup_delay		= 5000, /* 1200us */
> > +};
> > +
> > +static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
> > +	.name	= "reg-fixed-voltage",
> > +	.id	= 1,
> > +	.dev	= {
> > +		.platform_data	= &snowball_gpio_en_3v3_data,
> > +	},
> > +};
> > +#endif
> > +
> >   static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
> >   	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
> >   	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
> > @@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
> >   	&snowball_led_dev,
> >   	&snowball_key_dev,
> >   	&snowball_sbnet_dev,
> > +	&snowball_gpio_en_3v3_regulator_dev,
> >   };
> >   
> >   static void __init mop500_init_machine(void)
> > diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
> > index 9e9dd5a..d3a02d5 100644
> > --- a/arch/arm/mach-ux500/board-mop500.h
> > +++ b/arch/arm/mach-ux500/board-mop500.h
> > @@ -13,6 +13,7 @@
> >   #include <linux/amba/mmci.h>
> >   
> >   /* Snowball specific GPIO assignments, this board has no GPIO expander */
> > +#define SNOWBALL_EN_3V3_ETH_GPIO	26
> No it's MOP500_AB8500_PIN_GPIO(26)
> >   #define SNOWBALL_ACCEL_INT1_GPIO	163
> >   #define SNOWBALL_ACCEL_INT2_GPIO	164
> >   #define SNOWBALL_MAGNET_DRDY_GPIO	165
> > @@ -76,7 +77,6 @@
> >   #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
> >   #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
> >   #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
> > -#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
> keep this line
> >   
> >   struct device;
> >   struct i2c_board_info;

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From will.deacon at arm.com  Fri Aug 24 10:13:23 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 15:13:23 +0100
Subject: [PATCH 1/2] ARM: delay: set loops_per_jiffy when moving to
 timer-based loop
Message-ID: <1345817604-9004-1-git-send-email-will.deacon@arm.com>

The delay functions may be called by some platforms between switching to
the timer-based delay loop but before calibration. In this case, the
initial loops_per_jiffy may not be suitable for the timer (although a
compromise may be achievable) and delay times may be considered too
inaccurate.

This patch updates loops_per_jiffy when switching to the timer-based
delay loop so that delays are consistent prior to calibration.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/lib/delay.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index d6dacc6..395d5fb 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq)
 {
 	pr_info("Switching to timer-based delay loop\n");
 	lpj_fine			= freq / HZ;
+	loops_per_jiffy			= lpj_fine;
 	arm_delay_ops.delay		= __timer_delay;
 	arm_delay_ops.const_udelay	= __timer_const_udelay;
 	arm_delay_ops.udelay		= __timer_udelay;
-- 
1.7.4.1



From will.deacon at arm.com  Fri Aug 24 10:13:24 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 24 Aug 2012 15:13:24 +0100
Subject: [PATCH 2/2] ARM: delay: add registration mechanism for delay timer
 sources
In-Reply-To: <1345817604-9004-1-git-send-email-will.deacon@arm.com>
References: <1345817604-9004-1-git-send-email-will.deacon@arm.com>
Message-ID: <1345817604-9004-2-git-send-email-will.deacon@arm.com>

From: Jonathan Austin <Jonathan.Austin at arm.com>

The current timer-based delay loop relies on the architected timer to
initiate the switch away from the polling-based implementation. This is
unfortunate for platforms without the architected timers but with a
suitable delay source (that is, constant frequency, always powered-up
and ticking as long as the CPUs are online).

This patch introduces a registration mechanism for the delay timer
(which provides an unconditional read_current_timer implementation) and
updates the architected timer code to use the new interface.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

Resending this as Stephen and Shinya say that they can use it for MSM and
shmobile.

 arch/arm/include/asm/arch_timer.h |    1 -
 arch/arm/include/asm/delay.h      |    9 +++++++++
 arch/arm/include/asm/timex.h      |    6 ------
 arch/arm/kernel/arch_timer.c      |   12 +++++++-----
 arch/arm/lib/delay.c              |   31 ++++++++++++++++++++++---------
 5 files changed, 38 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e7547..88401c2 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -4,7 +4,6 @@
 #include <asm/errno.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
 #else
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index dc61451..17deac7 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -15,6 +15,11 @@
 
 #ifndef __ASSEMBLY__
 
+struct delay_timer {
+	int (*read_current_timer)(unsigned long *timer_val);
+	unsigned long freq;
+};
+
 extern struct arm_delay_ops {
 	void (*delay)(unsigned long);
 	void (*const_udelay)(unsigned long);
@@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
 extern void __loop_const_udelay(unsigned long);
 
+/* Delay-loop timer registration. */
+#define ARCH_HAS_READ_CURRENT_TIMER
+extern void register_current_timer_delay(struct delay_timer *timer);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* defined(_ARM_DELAY_H) */
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce11944..9acc135 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,15 +12,9 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#include <asm/arch_timer.h>
 #include <mach/timex.h>
 
 typedef unsigned long cycles_t;
-
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()	({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()	(0)
-#endif
 
 #endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf25880..70eea73 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 
 #include <asm/cputype.h>
+#include <asm/delay.h>
 #include <asm/localtimer.h>
 #include <asm/arch_timer.h>
 #include <asm/system_info.h>
@@ -31,8 +32,7 @@ static int arch_timer_ppi;
 static int arch_timer_ppi2;
 
 static struct clock_event_device __percpu **arch_timer_evt;
-
-extern void init_current_timer_delay(unsigned long freq);
+static struct delay_timer arch_delay_timer;
 
 /*
  * Architected system timer support.
@@ -225,7 +225,7 @@ static cycle_t arch_counter_read(struct clocksource *cs)
 	return arch_counter_get_cntpct();
 }
 
-int read_current_timer(unsigned long *timer_val)
+static int arch_timer_read_current_timer(unsigned long *timer_val)
 {
 	if (!arch_timer_rate)
 		return -ENXIO;
@@ -302,11 +302,13 @@ static int __init arch_timer_register(void)
 		arch_timer_global_evt.cpumask = cpumask_of(0);
 		err = arch_timer_setup(&arch_timer_global_evt);
 	}
-
 	if (err)
 		goto out_free_irq;
 
-	init_current_timer_delay(arch_timer_rate);
+	/* Use the architected timer for the delay loop. */
+	arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+	arch_delay_timer.freq = arch_timer_rate;
+	register_current_timer_delay(&arch_delay_timer);
 	return 0;
 
 out_free_irq:
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 395d5fb..fff305b 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -34,7 +34,14 @@ struct arm_delay_ops arm_delay_ops = {
 	.udelay		= __loop_udelay,
 };
 
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static struct delay_timer *delay_timer;
+static bool delay_calibrated;
+
+int read_current_timer(unsigned long *timer_val)
+{
+	return delay_timer ? delay_timer->read_current_timer(timer_val) : -ENXIO;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
 	cycles_t start = get_cycles();
@@ -55,18 +62,24 @@ static void __timer_udelay(unsigned long usecs)
 	__timer_const_udelay(usecs * UDELAY_MULT);
 }
 
-void __init init_current_timer_delay(unsigned long freq)
+void __init register_current_timer_delay(struct delay_timer *timer)
 {
-	pr_info("Switching to timer-based delay loop\n");
-	lpj_fine			= freq / HZ;
-	loops_per_jiffy			= lpj_fine;
-	arm_delay_ops.delay		= __timer_delay;
-	arm_delay_ops.const_udelay	= __timer_const_udelay;
-	arm_delay_ops.udelay		= __timer_udelay;
+	if (!delay_calibrated) {
+		pr_info("Switching to timer-based delay loop\n");
+		delay_timer			= timer;
+		lpj_fine			= timer->freq / HZ;
+		loops_per_jiffy			= lpj_fine;
+		arm_delay_ops.delay		= __timer_delay;
+		arm_delay_ops.const_udelay	= __timer_const_udelay;
+		arm_delay_ops.udelay		= __timer_udelay;
+		delay_calibrated		= true;
+	} else {
+		pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
+	}
 }
 
 unsigned long __cpuinit calibrate_delay_is_known(void)
 {
+	delay_calibrated = true;
 	return lpj_fine;
 }
-#endif
-- 
1.7.4.1



From shawn.guo at linaro.org  Fri Aug 24 10:16:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 24 Aug 2012 22:16:13 +0800
Subject: [PATCH 0/5] Add device tree support for on-chip SRAM
In-Reply-To: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
References: <1345799866-19876-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <20120824141610.GG31998@S2101-09.ap.freescale.net>

On Fri, Aug 24, 2012 at 11:17:41AM +0200, Philipp Zabel wrote:
> These patches add support to configure the on-chip SRAM via device-tree
> node and to obtain the resulting genalloc pool from a phandle pointing   
> at the node.
> This allows drivers to allocate SRAM with the genalloc API without
> hard-coding the genalloc pool address.
> 
It looks like a good stuff.  But in the end, there is nothing IMX
specific with iram_alloc.c.  Why do we name it in IMX?

Regards,
Shawn

> regards
> Philipp
> 
> ---
>  arch/arm/boot/dts/imx53.dtsi          |    5 ++
>  arch/arm/boot/dts/imx6q.dtsi          |    5 ++
>  arch/arm/plat-mxc/include/mach/iram.h |   41 -----------------
>  arch/arm/plat-mxc/iram_alloc.c        |   81 ++++++++++++++++++++-------------
>  include/linux/genalloc.h              |   14 ++++++
>  lib/genalloc.c                        |   77 +++++++++++++++++++++++++++++++
>  6 files changed, 150 insertions(+), 73 deletions(-)
> 


From dedekind1 at gmail.com  Fri Aug 24 10:23:19 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 17:23:19 +0300
Subject: [PATCH] mtd: kill MTD_NAND_VERIFY_WRITE
In-Reply-To: <1344998325-3279-1-git-send-email-shijie8@gmail.com>
References: <1344998325-3279-1-git-send-email-shijie8@gmail.com>
Message-ID: <1345818199.2848.314.camel@sauron.fi.intel.com>

On Tue, 2012-08-14 at 22:38 -0400, Huang Shijie wrote:
> Just as Artem suggested:
> 
> "Both UBI and JFFS2 are able to read verify what they wrote already.
> There are also MTD tests which do this verification. So I think there
> is no reason to keep this in the NAND layer, let alone wasting RAM in
> the driver to support this feature."
> 
> So kill MTD_NAND_VERIFY_WRITE entirely.
> 
> Signed-off-by: Huang Shijie <shijie8 at gmail.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From dedekind1 at gmail.com  Fri Aug 24 10:23:50 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 17:23:50 +0300
Subject: [PATCH] kconfig: remove CONFIG_MTD_NAND_VERIFY_WRITE
In-Reply-To: <1345021930-5033-1-git-send-email-b32955@freescale.com>
References: <1345021930-5033-1-git-send-email-b32955@freescale.com>
Message-ID: <1345818230.2848.315.camel@sauron.fi.intel.com>

On Wed, 2012-08-15 at 17:12 +0800, Huang Shijie wrote:
> Just as Artem suggested:
> 
> "Both UBI and JFFS2 are able to read verify what they wrote already.
> There are also MTD tests which do this verification. So I think there
> is no reason to keep this in the NAND layer, let alone wasting RAM in
> the driver to support this feature."
> 
> So kill MTD_NAND_VERIFY_WRITE entirely. Please see the patch:
> http://lists.infradead.org/pipermail/linux-mtd/2012-August/043189.html
>   
> This patch removes the CONFIG_MTD_NAND_VERIFY_WRITE in the defconfigs.
> 
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From philippe.langlais at st.com  Fri Aug 24 10:27:14 2012
From: philippe.langlais at st.com (Philippe LANGLAIS)
Date: Fri, 24 Aug 2012 16:27:14 +0200
Subject: [PATCH 1/1 v2] ARM: ux500: Provide SMSC911x fixed-regulator
 when not booting DT
In-Reply-To: <20120824140849.GM32491@gmail.com>
References: <1345812481-2384-1-git-send-email-lee.jones@linaro.org>
 <5037871F.7080300@st.com> <20120824140849.GM32491@gmail.com>
Message-ID: <50378F42.3060409@st.com>

On 08/24/2012 04:08 PM, Lee Jones wrote:
>> I have checked in Snowball schematics and I can confirm that the fixed
>> 3.3V regulator is GPIO26 on AB8500 not DB8500, so its numero is
>> MOP500_AB8500_PIN_GPIO(26)
> We're also using GPIO26 on the DB8500 in the Device Tree solution.
> Odd that is should work? I wonder if we're just getting lucky, or if
> it's just not required?
Yes, we are lucky that the AB8500 GPIO26 is in the right state to make 
the ethernet working
and changing the state of GPIO26 doesn't seems to break something on 
Snowball.
>
>> and you have first to update the upstream gpio-ab8500 driver.
> I see. Do you know what needs to be updated to get it working?
I can't remember exactly, changes have been done recently on the 
internal driver and I know that the upstream driver is BROKEN (use 
obsolete IRQ API).
>
>> On 08/24/2012 02:48 PM, Lee Jones wrote:
>>> The SMSC911x Ethernet chip requires a fixed-regulator in order to
>>> function correctly. We have previously provided a means to obtain
>>> this during a Device Tree boot, however nothing has been put into
>>> place when booting with a non-DT kernel. This patch aims to change
>>> that.
>>>
>>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>> ---
>>>    arch/arm/mach-ux500/board-mop500-regulators.c |   17 +++++++++++++++++
>>>    arch/arm/mach-ux500/board-mop500-regulators.h |    1 +
>>>    arch/arm/mach-ux500/board-mop500.c            |   21 +++++++++++++++++++++
>>>    arch/arm/mach-ux500/board-mop500.h            |    2 +-
>>>    4 files changed, 40 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
>>> index 52426a4..139f31e 100644
>>> --- a/arch/arm/mach-ux500/board-mop500-regulators.c
>>> +++ b/arch/arm/mach-ux500/board-mop500-regulators.c
>>> @@ -13,6 +13,23 @@
>>>    #include <linux/regulator/ab8500.h>
>>>    #include "board-mop500-regulators.h"
>>>    
>>> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
>>> +static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
>>> +	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
>>> +};
>>> +
>>> +struct regulator_init_data gpio_en_3v3_regulator = {
>>> +	.constraints = {
>>> +		.name = "EN-3V3",
>>> +		.min_uV = 3300000,
>>> +		.max_uV = 3300000,
>>> +		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
>>> +	},
>>> +	.num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers),
>>> +	.consumer_supplies = gpio_en_3v3_consumers,
>>> +};
>>> +#endif
>>> +
>>>    /*
>>>     * TPS61052 regulator
>>>     */
>>> diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
>>> index 9499215..78a0642 100644
>>> --- a/arch/arm/mach-ux500/board-mop500-regulators.h
>>> +++ b/arch/arm/mach-ux500/board-mop500-regulators.h
>>> @@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init
>>>    ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
>>>    extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
>>>    extern struct regulator_init_data tps61052_regulator;
>>> +extern struct regulator_init_data gpio_en_3v3_regulator;
>>>    
>>>    #endif
>>> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
>>> index 42e1759..c7f0973 100644
>>> --- a/arch/arm/mach-ux500/board-mop500.c
>>> +++ b/arch/arm/mach-ux500/board-mop500.c
>>> @@ -23,6 +23,7 @@
>>>    #include <linux/spi/spi.h>
>>>    #include <linux/mfd/abx500/ab8500.h>
>>>    #include <linux/regulator/ab8500.h>
>>> +#include <linux/regulator/fixed.h>
>>>    #include <linux/mfd/tc3589x.h>
>>>    #include <linux/mfd/tps6105x.h>
>>>    #include <linux/mfd/abx500/ab8500-gpio.h>
>>> @@ -75,6 +76,25 @@ static struct platform_device snowball_led_dev = {
>>>    	},
>>>    };
>>>    
>>> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
>>> +static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
>>> +	.supply_name		= "EN-3V3",
>>> +	.gpio			= SNOWBALL_EN_3V3_ETH_GPIO,
>>> +	.microvolts		= 3300000,
>>> +	.enable_high		= 1,
>>> +	.init_data		= &gpio_en_3v3_regulator,
>>> +	.startup_delay		= 5000, /* 1200us */
>>> +};
>>> +
>>> +static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
>>> +	.name	= "reg-fixed-voltage",
>>> +	.id	= 1,
>>> +	.dev	= {
>>> +		.platform_data	= &snowball_gpio_en_3v3_data,
>>> +	},
>>> +};
>>> +#endif
>>> +
>>>    static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
>>>    	.gpio_base		= MOP500_AB8500_PIN_GPIO(1),
>>>    	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
>>> @@ -585,6 +605,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
>>>    	&snowball_led_dev,
>>>    	&snowball_key_dev,
>>>    	&snowball_sbnet_dev,
>>> +	&snowball_gpio_en_3v3_regulator_dev,
>>>    };
>>>    
>>>    static void __init mop500_init_machine(void)
>>> diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
>>> index 9e9dd5a..d3a02d5 100644
>>> --- a/arch/arm/mach-ux500/board-mop500.h
>>> +++ b/arch/arm/mach-ux500/board-mop500.h
>>> @@ -13,6 +13,7 @@
>>>    #include <linux/amba/mmci.h>
>>>    
>>>    /* Snowball specific GPIO assignments, this board has no GPIO expander */
>>> +#define SNOWBALL_EN_3V3_ETH_GPIO	26
>> No it's MOP500_AB8500_PIN_GPIO(26)
>>>    #define SNOWBALL_ACCEL_INT1_GPIO	163
>>>    #define SNOWBALL_ACCEL_INT2_GPIO	164
>>>    #define SNOWBALL_MAGNET_DRDY_GPIO	165
>>> @@ -76,7 +77,6 @@
>>>    #define SNOWBALL_PM_GPIO4_GPIO		MOP500_AB8500_PIN_GPIO(4)	/* SYSCLKREQ6/GPIO4 */
>>>    #define SNOWBALL_EN_3V6_GPIO		MOP500_AB8500_PIN_GPIO(16)	/* PWMOUT3/GPIO16 */
>>>    #define SNOWBALL_PME_ETH_GPIO		MOP500_AB8500_PIN_GPIO(24)	/* SYSCLKREQ7/GPIO24 */
>>> -#define SNOWBALL_EN_3V3_ETH_GPIO	MOP500_AB8500_PIN_GPIO(26)	/* GPIO26 */
>> keep this line
>>>    
>>>    struct device;
>>>    struct i2c_board_info;

From benoit.thebaudeau at advansee.com  Fri Aug 24 10:52:57 2012
From: benoit.thebaudeau at advansee.com (=?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?=)
Date: Fri, 24 Aug 2012 16:52:57 +0200 (CEST)
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <1596192785.2810155.1345817566620.JavaMail.root@advansee.com>
Message-ID: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>

Hi Sascha,

On Thu, Jun 14, 09:43:26 EDT 2012, Sascha Hauer wrote:
> The IPU is the Image Processing Unit found on i.MX51/53 SoCs. It
> features several units for image processing, this patch adds support
> for the units needed for Framebuffer support, namely:
> 
> - Display Controller (dc)
> - Display Interface (di)
> - Display Multi Fifo Controller (dmfc)
> - Display Processor (dp)
> - Image DMA Controller (idmac)
> 
> This patch is based on the Freescale driver, but follows a different
> approach. The Freescale code implements logical idmac channels and
> the handling of the subunits is hidden in common idmac code pathes
> in big switch/case statements. This patch instead just provides code
> and resource management for the different subunits. The user, in this
> case the framebuffer driver, decides how the different units play
> together.

What is the status of this series, and especially of this patch, as to its
integration into upstream? At some point, you were talking about pushing it to
staging, but since things don't seem to have evolved.

> The IPU has other units missing in this patch:
> 
> - CMOS Sensor Interface (csi)
> - Video Deinterlacer (vdi)
> - Sensor Multi FIFO Controler (smfc)
> - Image Converter (ic)
> - Image Rotator (irt)
> 
> So expect more files to come in this directory.

Do you have a schedule for that? Are you waiting for more customer projects at
Pengutronix to do that?

Would your customers_pengutronix_mx5_master-20120612 tag be the starting point
for these new files? Can it be used as a working solution in the meantime, or
does it have limitations?

That would be great to finally have full IPU/VPU/GPU support for i.MX5 into
upstream. As you already know, Linaro also have some video support for i.MX5 in
this head:
http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=shortlog;h=refs/heads/lt-3.2-imx5

Matt, I think you also have video support for efikamx, don't you?

Is there a plan to merge all these developments into upstream?

Best regards,
Beno?t


From chander.kashyap at linaro.org  Fri Aug 24 10:52:16 2012
From: chander.kashyap at linaro.org (Chander Kashyap)
Date: Fri, 24 Aug 2012 20:22:16 +0530
Subject: [PATCH] ARM: Exynos4: Turn off clocks for NAND,
 OneNAND and TSI controllers
Message-ID: <1345819936-6503-1-git-send-email-chander.kashyap@linaro.org>

The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
controllers could be either enabled or disabled at boot. To ensure
that these are turned off until used, add them to the list of clocks
to be turned off during boot.

Signed-off-by: Chander Kashyap <chander.kashyap at linaro.org>
---
 arch/arm/mach-exynos/clock-exynos4.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293..7cc5491 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 3),
 	}, {
+		.name		= "tsi",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
 		.name		= "hsmmc",
 		.devname	= "exynos4-sdhci.0",
 		.parent		= &exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
+		.name		= "onenand",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos4_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
 		.name		= "dac",
 		.devname	= "s5p-sdo",
 		.enable		= exynos4_clk_ip_tv_ctrl,
-- 
1.7.9.5



From marc.zyngier at arm.com  Fri Aug 24 10:52:56 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 24 Aug 2012 15:52:56 +0100
Subject: [PATCH v3 2/2] ARM: arch_timers: register a time/cycle counter
In-Reply-To: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
References: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1345819976-6339-3-git-send-email-marc.zyngier@arm.com>

Some subsystems (KVM for example) need access to a cycle counter.
In the KVM case, this is used to measure the time delta between
host and guest in order to accurately generate timer events for
the guest.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/include/asm/arch_timer.h |  7 +++++++
 arch/arm/kernel/arch_timer.c      | 25 +++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e7547..ad9b155 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -2,11 +2,13 @@
 #define __ASMARM_ARCH_TIMER_H
 
 #include <asm/errno.h>
+#include <linux/clocksource.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
 #define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
+struct timecounter *arch_timer_get_timecounter(void);
 #else
 static inline int arch_timer_of_register(void)
 {
@@ -17,6 +19,11 @@ static inline int arch_timer_sched_clock_init(void)
 {
 	return -ENXIO;
 }
+
+static inline struct timecounter *arch_timer_get_timecounter(void)
+{
+	return NULL;
+}
 #endif
 
 #endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 3f63b90..f999d11 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -323,6 +323,15 @@ int read_current_timer(unsigned long *timer_val)
 	return 0;
 }
 
+static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
+{
+	/*
+	 * Always use the physical counter for the clocksource.
+	 * CNTHCTL.PL1PCTEN must be set to 1.
+	 */
+	return arch_counter_get_cntpct();
+}
+
 static struct clocksource clocksource_counter = {
 	.name	= "arch_sys_counter",
 	.rating	= 400,
@@ -331,6 +340,18 @@ static struct clocksource clocksource_counter = {
 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct cyclecounter cyclecounter = {
+	.read	= arch_counter_read_cc,
+	.mask	= CLOCKSOURCE_MASK(56),
+};
+
+static struct timecounter timecounter;
+
+struct timecounter *arch_timer_get_timecounter(void)
+{
+	return &timecounter;
+}
+
 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
 	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
@@ -370,6 +391,10 @@ static int __init arch_timer_register(void)
 	}
 
 	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+	cyclecounter.mult = clocksource_counter.mult;
+	cyclecounter.shift = clocksource_counter.shift;
+	timecounter_init(&timecounter, &cyclecounter,
+			 arch_counter_get_cntpct());
 
 	if (arch_timer_use_virtual) {
 		ppi = arch_timer_ppi[VIRT_PPI];
-- 
1.7.11.4




From marc.zyngier at arm.com  Fri Aug 24 10:52:55 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 24 Aug 2012 15:52:55 +0100
Subject: [PATCH v3 1/2] ARM: arch_timers: enable the use of the virtual timer
In-Reply-To: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
References: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <1345819976-6339-2-git-send-email-marc.zyngier@arm.com>

At the moment, the arch_timer driver only uses the physical timer,
which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
which is likely in a virtualized environment. Instead, the virtual
timer is always available.

This patch enables the use of the virtual timer, unless no
interrupt is provided in the DT for it, in which case it falls
back to the physical timer.

Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
 arch/arm/kernel/arch_timer.c | 337 ++++++++++++++++++++++++++++++-------------
 1 file changed, 233 insertions(+), 104 deletions(-)

diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf25880..3f63b90 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -27,13 +27,23 @@
 #include <asm/sched_clock.h>
 
 static unsigned long arch_timer_rate;
-static int arch_timer_ppi;
-static int arch_timer_ppi2;
+
+enum ppi_nr {
+	PHYS_SECURE_PPI,
+	PHYS_NONSECURE_PPI,
+	VIRT_PPI,
+	HYP_PPI,
+	MAX_TIMER_PPI
+};
+
+static int arch_timer_ppi[MAX_TIMER_PPI];
 
 static struct clock_event_device __percpu **arch_timer_evt;
 
 extern void init_current_timer_delay(unsigned long freq);
 
+static bool arch_timer_use_virtual = true;
+
 /*
  * Architected system timer support.
  */
@@ -43,53 +53,98 @@ extern void init_current_timer_delay(unsigned long freq);
 #define ARCH_TIMER_CTRL_IT_STAT		(1 << 2)
 
 #define ARCH_TIMER_REG_CTRL		0
-#define ARCH_TIMER_REG_FREQ		1
-#define ARCH_TIMER_REG_TVAL		2
+#define ARCH_TIMER_REG_TVAL		1
 
-static void arch_timer_reg_write(int reg, u32 val)
+#define ARCH_TIMER_PHYS_ACCESS		0
+#define ARCH_TIMER_VIRT_ACCESS		1
+
+/*
+ * These register accessors are marked inline so the compiler can
+ * nicely work out which register we want, and chuck away the rest of
+ * the code. At least it does so with a recent GCC (4.6.3).
+ */
+static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
 {
-	switch (reg) {
-	case ARCH_TIMER_REG_CTRL:
-		asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
-		break;
-	case ARCH_TIMER_REG_TVAL:
-		asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
-		break;
+	if (access == ARCH_TIMER_PHYS_ACCESS) {
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+			break;
+		}
+	}
+
+	if (access == ARCH_TIMER_VIRT_ACCESS) {
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
+			break;
+		}
 	}
 
 	isb();
 }
 
-static u32 arch_timer_reg_read(int reg)
+static inline u32 arch_timer_reg_read(const int access, const int reg)
 {
-	u32 val;
+	u32 val = 0;
+
+	if (access == ARCH_TIMER_PHYS_ACCESS) {
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+			break;
+		}
+	}
 
-	switch (reg) {
-	case ARCH_TIMER_REG_CTRL:
-		asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
-		break;
-	case ARCH_TIMER_REG_FREQ:
-		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
-		break;
-	case ARCH_TIMER_REG_TVAL:
-		asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
-		break;
-	default:
-		BUG();
+	if (access == ARCH_TIMER_VIRT_ACCESS) {
+		switch (reg) {
+		case ARCH_TIMER_REG_CTRL:
+			asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
+			break;
+		case ARCH_TIMER_REG_TVAL:
+			asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
+			break;
+		}
 	}
 
 	return val;
 }
 
-static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+static inline cycle_t arch_counter_get_cntpct(void)
 {
-	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-	unsigned long ctrl;
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
 
-	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static irqreturn_t inline timer_handler(const int access,
+					struct clock_event_device *evt)
+{
+	unsigned long ctrl;
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
 	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
-		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 		evt->event_handler(evt);
 		return IRQ_HANDLED;
 	}
@@ -97,63 +152,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id)
 	return IRQ_NONE;
 }
 
-static void arch_timer_disable(void)
+static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 {
-	unsigned long ctrl;
+	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
 
-	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
-	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
-	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 }
 
-static void arch_timer_set_mode(enum clock_event_mode mode,
-				struct clock_event_device *clk)
+static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 {
+	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+
+	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
+}
+
+static inline void timer_set_mode(const int access, int mode)
+{
+	unsigned long ctrl;
 	switch (mode) {
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
-		arch_timer_disable();
+		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
+		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 		break;
 	default:
 		break;
 	}
 }
 
-static int arch_timer_set_next_event(unsigned long evt,
-				     struct clock_event_device *unused)
+static void arch_timer_set_mode_virt(enum clock_event_mode mode,
+				     struct clock_event_device *clk)
 {
-	unsigned long ctrl;
+	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
+}
+
+static void arch_timer_set_mode_phys(enum clock_event_mode mode,
+				     struct clock_event_device *clk)
+{
+	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
+}
 
-	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+static inline void set_next_event(const int access, unsigned long evt)
+{
+	unsigned long ctrl;
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
 	ctrl |= ARCH_TIMER_CTRL_ENABLE;
 	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
+}
 
-	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
-	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+static int arch_timer_set_next_event_virt(unsigned long evt,
+					  struct clock_event_device *unused)
+{
+	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
+	return 0;
+}
 
+static int arch_timer_set_next_event_phys(unsigned long evt,
+					  struct clock_event_device *unused)
+{
+	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
 	return 0;
 }
 
 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 {
-	/* Be safe... */
-	arch_timer_disable();
-
 	clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
 	clk->name = "arch_sys_timer";
 	clk->rating = 450;
-	clk->set_mode = arch_timer_set_mode;
-	clk->set_next_event = arch_timer_set_next_event;
-	clk->irq = arch_timer_ppi;
+	if (arch_timer_use_virtual) {
+		arch_timer_set_mode_virt(CLOCK_EVT_MODE_SHUTDOWN, NULL);
+		clk->set_mode = arch_timer_set_mode_virt;
+		clk->set_next_event = arch_timer_set_next_event_virt;
+	} else {
+		arch_timer_set_mode_phys(CLOCK_EVT_MODE_SHUTDOWN, NULL);
+		clk->set_mode = arch_timer_set_mode_phys;
+		clk->set_next_event = arch_timer_set_next_event_phys;
+	}
+		
+	clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
 
 	clockevents_config_and_register(clk, arch_timer_rate,
 					0xf, 0x7fffffff);
 
 	*__this_cpu_ptr(arch_timer_evt) = clk;
 
-	enable_percpu_irq(clk->irq, 0);
-	if (arch_timer_ppi2)
-		enable_percpu_irq(arch_timer_ppi2, 0);
+	if (arch_timer_use_virtual)
+		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
+	else {
+		enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
+		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+			enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
+	}
 
 	return 0;
 }
@@ -173,8 +265,7 @@ static int arch_timer_available(void)
 		return -ENXIO;
 
 	if (arch_timer_rate == 0) {
-		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
-		freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
 
 		/* Check the timer frequency. */
 		if (freq == 0) {
@@ -185,43 +276,42 @@ static int arch_timer_available(void)
 		arch_timer_rate = freq;
 	}
 
-	pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
-		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
+		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
+		     arch_timer_use_virtual ? "virt" : "phys");
 	return 0;
 }
 
-static inline cycle_t arch_counter_get_cntpct(void)
+static u32 notrace arch_counter_get_cntpct32(void)
 {
-	u32 cvall, cvalh;
+	cycle_t cnt = arch_counter_get_cntpct();
 
-	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
-}
-
-static inline cycle_t arch_counter_get_cntvct(void)
-{
-	u32 cvall, cvalh;
-
-	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
-
-	return ((cycle_t) cvalh << 32) | cvall;
+	/*
+	 * The sched_clock infrastructure only knows about counters
+	 * with at most 32bits. Forget about the upper 24 bits for the
+	 * time being...
+	 */
+	return (u32)(cnt & (u32)~0);
 }
 
 static u32 notrace arch_counter_get_cntvct32(void)
 {
-	cycle_t cntvct = arch_counter_get_cntvct();
+	cycle_t cnt = arch_counter_get_cntvct();
 
 	/*
 	 * The sched_clock infrastructure only knows about counters
 	 * with at most 32bits. Forget about the upper 24 bits for the
 	 * time being...
 	 */
-	return (u32)(cntvct & (u32)~0);
+	return (u32)(cnt & (u32)~0);
 }
 
 static cycle_t arch_counter_read(struct clocksource *cs)
 {
+	/*
+	 * Always use the physical counter for the clocksource.
+	 * CNTHCTL.PL1PCTEN must be set to 1.
+	 */
 	return arch_counter_get_cntpct();
 }
 
@@ -245,10 +335,16 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 {
 	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 		 clk->irq, smp_processor_id());
-	disable_percpu_irq(clk->irq);
-	if (arch_timer_ppi2)
-		disable_percpu_irq(arch_timer_ppi2);
-	arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+
+	if (arch_timer_use_virtual) {
+		disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
+		arch_timer_set_mode_virt(CLOCK_EVT_MODE_UNUSED, clk);
+	} else {
+		disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
+		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+			disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+		arch_timer_set_mode_phys(CLOCK_EVT_MODE_UNUSED, clk);
+	}
 }
 
 static struct local_timer_ops arch_timer_ops __cpuinitdata = {
@@ -261,36 +357,44 @@ static struct clock_event_device arch_timer_global_evt;
 static int __init arch_timer_register(void)
 {
 	int err;
+	int ppi;
 
 	err = arch_timer_available();
 	if (err)
-		return err;
+		goto out;
 
 	arch_timer_evt = alloc_percpu(struct clock_event_device *);
-	if (!arch_timer_evt)
-		return -ENOMEM;
+	if (!arch_timer_evt) {
+		err = -ENOMEM;
+		goto out;
+	}
 
 	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 
-	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
-				 "arch_timer", arch_timer_evt);
+	if (arch_timer_use_virtual) {
+		ppi = arch_timer_ppi[VIRT_PPI];
+		err = request_percpu_irq(ppi, arch_timer_handler_virt,
+					 "arch_timer", arch_timer_evt);
+	} else {
+		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
+		err = request_percpu_irq(ppi, arch_timer_handler_phys,
+					 "arch_timer", arch_timer_evt);
+		if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+			err = request_percpu_irq(ppi, arch_timer_handler_phys,
+						 "arch_timer", arch_timer_evt);
+			if (err)
+				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+						arch_timer_evt);
+		}
+	}
+
 	if (err) {
 		pr_err("arch_timer: can't register interrupt %d (%d)\n",
-		       arch_timer_ppi, err);
+		       ppi, err);
 		goto out_free;
 	}
 
-	if (arch_timer_ppi2) {
-		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
-					 "arch_timer", arch_timer_evt);
-		if (err) {
-			pr_err("arch_timer: can't register interrupt %d (%d)\n",
-			       arch_timer_ppi2, err);
-			arch_timer_ppi2 = 0;
-			goto out_free_irq;
-		}
-	}
-
 	err = local_timer_register(&arch_timer_ops);
 	if (err) {
 		/*
@@ -310,13 +414,19 @@ static int __init arch_timer_register(void)
 	return 0;
 
 out_free_irq:
-	free_percpu_irq(arch_timer_ppi, arch_timer_evt);
-	if (arch_timer_ppi2)
-		free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+	if (arch_timer_use_virtual)
+		free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
+	else {
+		free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+				arch_timer_evt);
+		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
+			free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+					arch_timer_evt);
+	}
 
 out_free:
 	free_percpu(arch_timer_evt);
-
+out:
 	return err;
 }
 
@@ -329,6 +439,7 @@ int __init arch_timer_of_register(void)
 {
 	struct device_node *np;
 	u32 freq;
+	int i;
 
 	np = of_find_matching_node(NULL, arch_timer_of_match);
 	if (!np) {
@@ -340,22 +451,40 @@ int __init arch_timer_of_register(void)
 	if (!of_property_read_u32(np, "clock-frequency", &freq))
 		arch_timer_rate = freq;
 
-	arch_timer_ppi = irq_of_parse_and_map(np, 0);
-	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
-	pr_info("arch_timer: found %s irqs %d %d\n",
-		np->name, arch_timer_ppi, arch_timer_ppi2);
+	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
+
+	/*
+	 * If no interrupt provided for virtual timer, we'll have to
+	 * stick to the physical timer. It'd better be accessible...
+	 */
+	if (!arch_timer_ppi[VIRT_PPI]) {
+		arch_timer_use_virtual = false;
+
+		if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
+		    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
+			pr_warn("arch_timer: No interrupt available, giving up\n");
+			return -EINVAL;
+		}
+	}
 
 	return arch_timer_register();
 }
 
 int __init arch_timer_sched_clock_init(void)
 {
+	u32 (*cnt32)(void);
 	int err;
 
 	err = arch_timer_available();
 	if (err)
 		return err;
 
-	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+	if (arch_timer_use_virtual)
+		cnt32 = arch_counter_get_cntvct32;
+	else
+		cnt32 = arch_counter_get_cntpct32;
+
+	setup_sched_clock(cnt32, 32, arch_timer_rate);
 	return 0;
 }
-- 
1.7.11.4




From marc.zyngier at arm.com  Fri Aug 24 10:52:54 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Fri, 24 Aug 2012 15:52:54 +0100
Subject: [PATCH v3 0/2] arch_timers patches to enable KVM support
Message-ID: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>

This series is aimed at offering the minimum level of support that KVM
needs when it comes to architected timers.

The first patch changes the driver to use the virtual timer by default
instead of the physical one (access to the later is conditioned by the
hypervisor settings, while the former is always available). This could
be required even if the kernel is not running as a guest.

The second patch exposes a clockcycle counter that can be used by
other subsystems.

Tested on A15 (VE+TC2), both as a host and a KVM guest. Patches
against v3.6-rc3.

* From v2:
- Trick the compiler into generating really nice code, at the expense
  of a certain lack of abstraction
- Don't mandate physical timer non-secure PPI, in order to stay
  compatible with existing and possibly incomplete DTs.
  
Marc Zyngier (2):
  ARM: arch_timers: enable the use of the virtual timer
  ARM: arch_timers: register a time/cycle counter

 arch/arm/include/asm/arch_timer.h |   7 +
 arch/arm/kernel/arch_timer.c      | 362 +++++++++++++++++++++++++++-----------
 2 files changed, 265 insertions(+), 104 deletions(-)

-- 
1.7.11.4




From hvaibhav at ti.com  Fri Aug 24 10:54:24 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 24 Aug 2012 20:24:24 +0530
Subject: [PATCH] ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for
 common functions
Message-ID: <1345820064-5243-1-git-send-email-hvaibhav@ti.com>

Add missing soc_is_am33xx() check for DPLL common control & clock
related functions, without this dpll programmability would be broken
for am33xx family of devices.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
---
Not sure whether this should go as a fix in -rc, as AM33XX device
doesn't still boot without hwmod data (which is not yet upstream).

 arch/arm/mach-omap2/clkt_dpll.c |    4 ++--
 arch/arm/mach-omap2/dpll3xxx.c  |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..05ff99e 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
 		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
 			clk_reparent(clk, dd->clk_bypass);
-	} else if (cpu_is_omap44xx()) {
+	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
 		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
 			return dd->clk_bypass->rate;
-	} else if (cpu_is_omap44xx()) {
+	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
 		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..063e1f9 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 	 * Set jitter correction. No jitter correction for OMAP4 and 3630
 	 * since freqsel field is no longer present
 	 */
-	if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+	if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
 		v = __raw_readl(dd->control_reg);
 		v &= ~dd->freqsel_mask;
 		v |= freqsel << __ffs(dd->freqsel_mask);
@@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 			return -EINVAL;

 		/* No freqsel on OMAP4 and OMAP3630 */
-		if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+		if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
 			freqsel = _omap3_dpll_compute_freqsel(clk,
 						dd->last_rounded_n);
 			if (!freqsel)
--
1.7.0.4



From ian.molton at codethink.co.uk  Fri Aug 24 10:56:09 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Fri, 24 Aug 2012 16:56:09 +0200
Subject: [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <50379609.1020006@codethink.co.uk>

On 24/08/12 11:09, Gregory CLEMENT wrote:
> + compatible = "marvell,aurora-cache-with-outer";

This reads wrong.

perhaps aurora-with-outer-cache?

or better, perhaps something like:

compatible = "marvell,armada370", "marvell,armada-370-xp";
    L2: l2-cache {
        compatible = "marvell,aurora-cache-with-outer";
        reg = <0xd0008000 0x1000>;
        cache-id-part = <0x100>;
        wt-override;
        with-outer="yes";
    };



From carlo_bastelli at yahoo.it  Fri Aug 24 10:57:08 2012
From: carlo_bastelli at yahoo.it (Bastelli Carlo (yahoo))
Date: Fri, 24 Aug 2012 15:57:08 +0100 (BST)
Subject: SLAVE Side SPI kernel driver development
Message-ID: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>

Hello, I'm Carlo, I have a difficult task at work, my boss asked me to 
develop
 a driver SPI slave side on embedded ARM processor running Linux. 
Precisely linux occur on the SPI bus as a slave, not master as required 
by the hierarchical structure of the current kernel. The new driver 
will
 receive via interrupt and respond when selected by its chip select. Can
 anyone suggest the best way to develop this driver?. Personally, I 
have identified two main roads, the first if possible to exploit the 
structure SPI master driver, with a few tricks that now I can not 
define. The second most radical, write a driver for a UART like, but 
managing the SPI device.
Thank you for any suggestions or examples.

Carlo Bastelli


From dedekind1 at gmail.com  Fri Aug 24 11:08:44 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 24 Aug 2012 18:08:44 +0300
Subject: [PATCH v2] mtd: physmap_of: Add "no-unaligned-direct-access" DT
 property
In-Reply-To: <1345209752-22938-1-git-send-email-sr@denx.de>
References: <1345209752-22938-1-git-send-email-sr@denx.de>
Message-ID: <1345820924.2848.320.camel@sauron.fi.intel.com>

On Fri, 2012-08-17 at 15:22 +0200, Stefan Roese wrote:
> On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
> problems with JFFS2 usage, as the local bus (LPB) doesn't support
> unaligned accesses as implemented in the JFFS2 code via memcpy().
> By defining "no-unaligned-direct-access", the flash will not be
> exposed directly to the MTD users (e.g. JFFS2) any more.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From gururaja.hebbar at ti.com  Fri Aug 24 11:05:39 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 24 Aug 2012 15:05:39 +0000
Subject: [alsa-devel] [PATCH 14/17] ARM: ux500: Rename MSP board file to
 something more meaningful
In-Reply-To: <1345816913-4113-15-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-15-git-send-email-lee.jones@linaro.org>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>

On Fri, Aug 24, 2012 at 19:31:50, Lee Jones wrote:
> The 'msp' board file does more than just register MSP devices. It
> also registers some other components necessary to get audio working
> on ux500 based platforms; such as the PCM and Machine Drivers. For
> that reason we're changing the filename to be more encompassing -
> 'audio'.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/Makefile             |    2 +-
>  arch/arm/mach-ux500/board-mop500-audio.c |  199 ++++++++++++++++++++++++++++++
>  arch/arm/mach-ux500/board-mop500-msp.c   |  199 ------------------------------

Please use _M option when generating patches (git-format-patch -M ...).
This will reduce the final patch size

>  arch/arm/mach-ux500/board-mop500.c       |   12 +-
>  arch/arm/mach-ux500/board-mop500.h       |    4 +-
>  5 files changed, 208 insertions(+), 208 deletions(-)
>  create mode 100644 arch/arm/mach-ux500/board-mop500-audio.c
>  delete mode 100644 arch/arm/mach-ux500/board-mop500-msp.c
> 
> diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
> index 026086f..1dc2cfa 100644
> --- a/arch/arm/mach-ux500/Makefile
> +++ b/arch/arm/mach-ux500/Makefile
> @@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
>  				board-mop500-uib.o board-mop500-stuib.o \
>  				board-mop500-u8500uib.o \
>  				board-mop500-pins.o \
> -				board-mop500-msp.o
> +				board-mop500-audio.o
>  obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
> diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
> new file mode 100644
> index 0000000..18f6c5a
> --- /dev/null
> +++ b/arch/arm/mach-ux500/board-mop500-audio.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright (C) ST-Ericsson SA 2010
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/init.h>
> +#include <linux/gpio.h>
> +#include <linux/pinctrl/consumer.h>
> +
> +#include <plat/gpio-nomadik.h>
> +#include <plat/pincfg.h>
> +#include <plat/ste_dma40.h>
> +
> +#include <mach/devices.h>
> +#include <mach/hardware.h>
> +#include <mach/irqs.h>
> +#include <mach/msp.h>
> +
> +#include "ste-dma40-db8500.h"
> +#include "board-mop500.h"
> +#include "devices-db8500.h"
> +#include "pins-db8500.h"
> +
> +static struct stedma40_chan_cfg msp0_dma_rx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_PERIPH_TO_MEM,
> +
> +	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
> +	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> +
> +	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +static struct stedma40_chan_cfg msp0_dma_tx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_MEM_TO_PERIPH,
> +
> +	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> +	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
> +
> +	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +struct msp_i2s_platform_data msp0_platform_data = {
> +	.id = MSP_I2S_0,
> +	.msp_i2s_dma_rx = &msp0_dma_rx,
> +	.msp_i2s_dma_tx = &msp0_dma_tx,
> +};
> +
> +static struct stedma40_chan_cfg msp1_dma_rx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_PERIPH_TO_MEM,
> +
> +	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
> +	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> +
> +	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +static struct stedma40_chan_cfg msp1_dma_tx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_MEM_TO_PERIPH,
> +
> +	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> +	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
> +
> +	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +struct msp_i2s_platform_data msp1_platform_data = {
> +	.id = MSP_I2S_1,
> +	.msp_i2s_dma_rx = NULL,
> +	.msp_i2s_dma_tx = &msp1_dma_tx,
> +};
> +
> +static struct stedma40_chan_cfg msp2_dma_rx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_PERIPH_TO_MEM,
> +
> +	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
> +	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> +
> +	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
> +	.src_info.psize = STEDMA40_PSIZE_LOG_1,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +static struct stedma40_chan_cfg msp2_dma_tx = {
> +	.high_priority = true,
> +	.dir = STEDMA40_MEM_TO_PERIPH,
> +
> +	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> +	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
> +
> +	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> +	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> +
> +	.use_fixed_channel = true,
> +	.phy_channel = 1,
> +
> +	/* data_width is set during configuration */
> +};
> +
> +static struct platform_device *db8500_add_msp_i2s(struct device *parent,
> +			int id,
> +			resource_size_t base, int irq,
> +			struct msp_i2s_platform_data *pdata)
> +{
> +	struct platform_device *pdev;
> +	struct resource res[] = {
> +		DEFINE_RES_MEM(base, SZ_4K),
> +		DEFINE_RES_IRQ(irq),
> +	};
> +
> +	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
> +		id, irq);
> +	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
> +						res, ARRAY_SIZE(res),
> +						pdata, sizeof(*pdata));
> +	if (!pdev) {
> +		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
> +			id);
> +		return NULL;
> +	}
> +
> +	return pdev;
> +}
> +
> +/* Platform device for ASoC MOP500 machine */
> +static struct platform_device snd_soc_mop500 = {
> +	.name = "snd-soc-mop500",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = NULL,
> +	},
> +};
> +
> +/* Platform device for Ux500-PCM */
> +static struct platform_device ux500_pcm = {
> +	.name = "ux500-pcm",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = NULL,
> +	},
> +};
> +
> +struct msp_i2s_platform_data msp2_platform_data = {
> +	.id = MSP_I2S_2,
> +	.msp_i2s_dma_rx = &msp2_dma_rx,
> +	.msp_i2s_dma_tx = &msp2_dma_tx,
> +};
> +
> +struct msp_i2s_platform_data msp3_platform_data = {
> +	.id		= MSP_I2S_3,
> +	.msp_i2s_dma_rx	= &msp1_dma_rx,
> +	.msp_i2s_dma_tx	= NULL,
> +};
> +
> +void mop500_audio_init(struct device *parent)
> +{
> +	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
> +	platform_device_register(&snd_soc_mop500);
> +
> +	pr_info("Initialize MSP I2S-devices.\n");
> +	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
> +			   &msp0_platform_data);
> +	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
> +			   &msp1_platform_data);
> +	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
> +			   &msp2_platform_data);
> +	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
> +			   &msp3_platform_data);
> +
> +	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> +	platform_device_register(&ux500_pcm);
> +}
> +
> +/* Due for removal once the MSP driver has been fully DT:ed. */
> +void mop500_of_audio_init(struct device *parent)
> +{
> +	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> +	platform_device_register(&ux500_pcm);
> +}
> diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
> deleted file mode 100644
> index 2af017f..0000000
> --- a/arch/arm/mach-ux500/board-mop500-msp.c
> +++ /dev/null
> @@ -1,199 +0,0 @@
> -/*
> - * Copyright (C) ST-Ericsson SA 2010
> - *
> - * License terms: GNU General Public License (GPL), version 2
> - */
> -
> -#include <linux/platform_device.h>
> -#include <linux/init.h>
> -#include <linux/gpio.h>
> -#include <linux/pinctrl/consumer.h>
> -
> -#include <plat/gpio-nomadik.h>
> -#include <plat/pincfg.h>
> -#include <plat/ste_dma40.h>
> -
> -#include <mach/devices.h>
> -#include <mach/hardware.h>
> -#include <mach/irqs.h>
> -#include <mach/msp.h>
> -
> -#include "ste-dma40-db8500.h"
> -#include "board-mop500.h"
> -#include "devices-db8500.h"
> -#include "pins-db8500.h"
> -
> -static struct stedma40_chan_cfg msp0_dma_rx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_PERIPH_TO_MEM,
> -
> -	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
> -	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -static struct stedma40_chan_cfg msp0_dma_tx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_MEM_TO_PERIPH,
> -
> -	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> -	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -struct msp_i2s_platform_data msp0_platform_data = {
> -	.id = MSP_I2S_0,
> -	.msp_i2s_dma_rx = &msp0_dma_rx,
> -	.msp_i2s_dma_tx = &msp0_dma_tx,
> -};
> -
> -static struct stedma40_chan_cfg msp1_dma_rx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_PERIPH_TO_MEM,
> -
> -	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
> -	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -static struct stedma40_chan_cfg msp1_dma_tx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_MEM_TO_PERIPH,
> -
> -	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> -	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -struct msp_i2s_platform_data msp1_platform_data = {
> -	.id = MSP_I2S_1,
> -	.msp_i2s_dma_rx = NULL,
> -	.msp_i2s_dma_tx = &msp1_dma_tx,
> -};
> -
> -static struct stedma40_chan_cfg msp2_dma_rx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_PERIPH_TO_MEM,
> -
> -	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
> -	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> -
> -	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
> -	.src_info.psize = STEDMA40_PSIZE_LOG_1,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_1,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -static struct stedma40_chan_cfg msp2_dma_tx = {
> -	.high_priority = true,
> -	.dir = STEDMA40_MEM_TO_PERIPH,
> -
> -	.src_dev_type = STEDMA40_DEV_DST_MEMORY,
> -	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
> -
> -	.src_info.psize = STEDMA40_PSIZE_LOG_4,
> -	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
> -
> -	.use_fixed_channel = true,
> -	.phy_channel = 1,
> -
> -	/* data_width is set during configuration */
> -};
> -
> -static struct platform_device *db8500_add_msp_i2s(struct device *parent,
> -			int id,
> -			resource_size_t base, int irq,
> -			struct msp_i2s_platform_data *pdata)
> -{
> -	struct platform_device *pdev;
> -	struct resource res[] = {
> -		DEFINE_RES_MEM(base, SZ_4K),
> -		DEFINE_RES_IRQ(irq),
> -	};
> -
> -	pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
> -		id, irq);
> -	pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
> -						res, ARRAY_SIZE(res),
> -						pdata, sizeof(*pdata));
> -	if (!pdev) {
> -		pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
> -			id);
> -		return NULL;
> -	}
> -
> -	return pdev;
> -}
> -
> -/* Platform device for ASoC MOP500 machine */
> -static struct platform_device snd_soc_mop500 = {
> -	.name = "snd-soc-mop500",
> -	.id = 0,
> -	.dev = {
> -		.platform_data = NULL,
> -	},
> -};
> -
> -/* Platform device for Ux500-PCM */
> -static struct platform_device ux500_pcm = {
> -	.name = "ux500-pcm",
> -	.id = 0,
> -	.dev = {
> -		.platform_data = NULL,
> -	},
> -};
> -
> -struct msp_i2s_platform_data msp2_platform_data = {
> -	.id = MSP_I2S_2,
> -	.msp_i2s_dma_rx = &msp2_dma_rx,
> -	.msp_i2s_dma_tx = &msp2_dma_tx,
> -};
> -
> -struct msp_i2s_platform_data msp3_platform_data = {
> -	.id		= MSP_I2S_3,
> -	.msp_i2s_dma_rx	= &msp1_dma_rx,
> -	.msp_i2s_dma_tx	= NULL,
> -};
> -
> -/* Due for removal once the MSP driver has been fully DT:ed. */
> -void mop500_of_msp_init(struct device *parent)
> -{
> -	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> -	platform_device_register(&ux500_pcm);
> -}
> -
> -void mop500_msp_init(struct device *parent)
> -{
> -	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
> -	platform_device_register(&snd_soc_mop500);
> -
> -	pr_info("Initialize MSP I2S-devices.\n");
> -	db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
> -			   &msp0_platform_data);
> -	db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
> -			   &msp1_platform_data);
> -	db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
> -			   &msp2_platform_data);
> -	db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
> -			   &msp3_platform_data);
> -
> -	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> -	platform_device_register(&ux500_pcm);
> -}
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index 0c141d5..7152635 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -607,7 +607,7 @@ static void __init mop500_init_machine(void)
>  	mop500_i2c_init(parent);
>  	mop500_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	u8500_cryp1_hash1_init(parent);
> @@ -641,7 +641,7 @@ static void __init snowball_init_machine(void)
>  	mop500_i2c_init(parent);
>  	snowball_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	/* This board has full regulator constraints */
> @@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
>  	mop500_i2c_init(parent);
>  	hrefv60_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
> @@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
>  				ARRAY_SIZE(mop500_platform_devs));
>  
>  		mop500_sdi_init(parent);
> -		mop500_msp_init(parent);
> +		mop500_audio_init(parent);
>  		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>  		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>  		i2c_register_board_info(2, mop500_i2c2_devices,
> @@ -816,7 +816,7 @@ static void __init u8500_init_machine(void)
>  		mop500_uib_init();
>  
>  	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
> -		mop500_of_msp_init(parent);
> +		mop500_of_audio_init(parent);
>  	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
>  		/*
>  		 * The HREFv60 board removed a GPIO expander and routed
> @@ -828,7 +828,7 @@ static void __init u8500_init_machine(void)
>  				ARRAY_SIZE(mop500_platform_devs));
>  
>  		hrefv60_sdi_init(parent);
> -		mop500_msp_init(parent);
> +		mop500_audio_init(parent);
>  
>  		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>  		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
> diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
> index 3fbf48f..9e9dd5a 100644
> --- a/arch/arm/mach-ux500/board-mop500.h
> +++ b/arch/arm/mach-ux500/board-mop500.h
> @@ -97,9 +97,9 @@ void __init mop500_stuib_init(void);
>  void __init mop500_pinmaps_init(void);
>  void __init snowball_pinmaps_init(void);
>  void __init hrefv60_pinmaps_init(void);
> -void mop500_msp_init(struct device *parent);
> +void mop500_audio_init(struct device *parent);
>  /* Due for removal once the MSP driver has been fully DT:ed. */
> -void mop500_of_msp_init(struct device *parent);
> +void mop500_of_audio_init(struct device *parent);
>  
>  int __init mop500_uib_init(void);
>  void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
> 


Regards, 
Gururaja


From lee.jones at linaro.org  Fri Aug 24 11:08:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 16:08:03 +0100
Subject: [alsa-devel] [PATCH 14/17] ARM: ux500: Rename MSP board file to
 something more meaningful
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-15-git-send-email-lee.jones@linaro.org>
 <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>
Message-ID: <20120824150802.GP32491@gmail.com>

> >  arch/arm/mach-ux500/Makefile             |    2 +-
> >  arch/arm/mach-ux500/board-mop500-audio.c |  199 ++++++++++++++++++++++++++++++
> >  arch/arm/mach-ux500/board-mop500-msp.c   |  199 ------------------------------
> 
> Please use _M option when generating patches (git-format-patch -M ...).
> This will reduce the final patch size

Ah, I see. That's what Linus was going on about!

I can do that.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From festevam at gmail.com  Fri Aug 24 11:14:00 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 24 Aug 2012 12:14:00 -0300
Subject: SLAVE Side SPI kernel driver development
In-Reply-To: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>
Message-ID: <CAOMZO5Ds6NKsTCptQXDGZDJasb119hYWqXMzX8nG5WFArysL7A@mail.gmail.com>

On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)
<carlo_bastelli at yahoo.it> wrote:
> Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
> develop
>  a driver SPI slave side on embedded ARM processor running Linux.
> Precisely linux occur on the SPI bus as a slave, not master as required
> by the hierarchical structure of the current kernel. The new driver
> will
>  receive via interrupt and respond when selected by its chip select. Can
>  anyone suggest the best way to develop this driver?. Personally, I
> have identified two main roads, the first if possible to exploit the
> structure SPI master driver, with a few tricks that now I can not
> define. The second most radical, write a driver for a UART like, but
> managing the SPI device.
> Thank you for any suggestions or examples.

Marek got spi slave running on a mx28. See his patch:
http://www.spinics.net/lists/arm-kernel/msg190860.html

Regards,

Fabio Estevam


From lee.jones at linaro.org  Fri Aug 24 11:14:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 24 Aug 2012 16:14:47 +0100
Subject: [alsa-devel] [PATCH 14/17] ARM: ux500: Rename MSP board file to
 something more meaningful
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-15-git-send-email-lee.jones@linaro.org>
 <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>
Message-ID: <20120824151446.GQ32491@gmail.com>

Like this?

From: Lee Jones <lee.jones at linaro.org>
Date: Fri, 24 Aug 2012 13:16:06 +0100
Subject: [PATCH 1/1] ARM: ux500: Rename MSP board file to something more meaningful

The 'msp' board file does more than just register MSP devices. It
also registers some other components necessary to get audio working
on ux500 based platforms; such as the PCM and Machine Drivers. For
that reason we're changing the filename to be more encompassing -
'audio'.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/Makefile                       |    2 +-
 .../{board-mop500-msp.c => board-mop500-audio.c}   |   16 ++++++++--------
 arch/arm/mach-ux500/board-mop500.c                 |   12 ++++++------
 arch/arm/mach-ux500/board-mop500.h                 |    4 ++--
 4 files changed, 17 insertions(+), 17 deletions(-)
 rename arch/arm/mach-ux500/{board-mop500-msp.c => board-mop500-audio.c} (98%)

diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086f..1dc2cfa 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
 				board-mop500-uib.o board-mop500-stuib.o \
 				board-mop500-u8500uib.o \
 				board-mop500-pins.o \
-				board-mop500-msp.o
+				board-mop500-audio.o
 obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
similarity index 98%
rename from arch/arm/mach-ux500/board-mop500-msp.c
rename to arch/arm/mach-ux500/board-mop500-audio.c
index 2af017f..18f6c5a 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -172,14 +172,7 @@ struct msp_i2s_platform_data msp3_platform_data = {
 	.msp_i2s_dma_tx	= NULL,
 };
 
-/* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent)
-{
-	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
-	platform_device_register(&ux500_pcm);
-}
-
-void mop500_msp_init(struct device *parent)
+void mop500_audio_init(struct device *parent)
 {
 	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
 	platform_device_register(&snd_soc_mop500);
@@ -197,3 +190,10 @@ void mop500_msp_init(struct device *parent)
 	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
 	platform_device_register(&ux500_pcm);
 }
+
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent)
+{
+	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+	platform_device_register(&ux500_pcm);
+}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0c141d5..7152635 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -607,7 +607,7 @@ static void __init mop500_init_machine(void)
 	mop500_i2c_init(parent);
 	mop500_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	u8500_cryp1_hash1_init(parent);
@@ -641,7 +641,7 @@ static void __init snowball_init_machine(void)
 	mop500_i2c_init(parent);
 	snowball_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	/* This board has full regulator constraints */
@@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
 	mop500_i2c_init(parent);
 	hrefv60_sdi_init(parent);
 	mop500_spi_init(parent);
-	mop500_msp_init(parent);
+	mop500_audio_init(parent);
 	mop500_uart_init(parent);
 
 	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		mop500_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 		i2c_register_board_info(2, mop500_i2c2_devices,
@@ -816,7 +816,7 @@ static void __init u8500_init_machine(void)
 		mop500_uib_init();
 
 	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-		mop500_of_msp_init(parent);
+		mop500_of_audio_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
@@ -828,7 +828,7 @@ static void __init u8500_init_machine(void)
 				ARRAY_SIZE(mop500_platform_devs));
 
 		hrefv60_sdi_init(parent);
-		mop500_msp_init(parent);
+		mop500_audio_init(parent);
 
 		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
 		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 3fbf48f..9e9dd5a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -97,9 +97,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
-void mop500_msp_init(struct device *parent);
+void mop500_audio_init(struct device *parent);
 /* Due for removal once the MSP driver has been fully DT:ed. */
-void mop500_of_msp_init(struct device *parent);
+void mop500_of_audio_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
-- 
1.7.9.5


From gregory.clement at free-electrons.com  Fri Aug 24 11:15:34 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Fri, 24 Aug 2012 17:15:34 +0200
Subject: [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <50379609.1020006@codethink.co.uk>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>
 <50379609.1020006@codethink.co.uk>
Message-ID: <50379A96.1050409@free-electrons.com>

On 08/24/2012 04:56 PM, Ian Molton wrote:> On 24/08/12 11:09, Gregory CLEMENT wrote:
>> + compatible = "marvell,aurora-cache-with-outer";
>
> This reads wrong.
>
> perhaps aurora-with-outer-cache?

We can use
compatible = "marvell,aurora-outer-cache"
and
compatible = "marvell,aurora-system-cache"

which is a better description of the L2 cache controller indeed.

>
> or better, perhaps something like:
>
> compatible = "marvell,armada370", "marvell,armada-370-xp";
>     L2: l2-cache {										
>         compatible = "marvell,aurora-cache-with-outer";	
>         reg = <0xd0008000 0x1000>;						
>         cache-id-part = <0x100>;							
>         wt-override;										
>         with-outer="yes";									
>     };


I guess you meant:

compatible = "marvell,armada370", "marvell,armada-370-xp";
    L2: l2-cache {										
        compatible = "marvell,aurora-cache";
        reg = <0xd0008000 0x1000>;
        cache-id-part = <0x100>;
        wt-override;
        with-outer="yes";
    };

But in this case the association between compatible strings and data
won't work (see PATCH 3/6).

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gururaja.hebbar at ti.com  Fri Aug 24 11:16:01 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 24 Aug 2012 15:16:01 +0000
Subject: [alsa-devel] [PATCH 14/17] ARM: ux500: Rename MSP board file to
 something more meaningful
In-Reply-To: <20120824151446.GQ32491@gmail.com>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-15-git-send-email-lee.jones@linaro.org>
 <1BAFE6F6C881BF42822005164F1491C33EA69B3A@DBDE01.ent.ti.com>
 <20120824151446.GQ32491@gmail.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA69C0E@DBDE01.ent.ti.com>

On Fri, Aug 24, 2012 at 20:44:47, Lee Jones wrote:
> Like this?

Exactly. Thanks

> 
> From: Lee Jones <lee.jones at linaro.org>
> Date: Fri, 24 Aug 2012 13:16:06 +0100
> Subject: [PATCH 1/1] ARM: ux500: Rename MSP board file to something more meaningful
> 
> The 'msp' board file does more than just register MSP devices. It
> also registers some other components necessary to get audio working
> on ux500 based platforms; such as the PCM and Machine Drivers. For
> that reason we're changing the filename to be more encompassing -
> 'audio'.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/mach-ux500/Makefile                       |    2 +-
>  .../{board-mop500-msp.c => board-mop500-audio.c}   |   16 ++++++++--------
>  arch/arm/mach-ux500/board-mop500.c                 |   12 ++++++------
>  arch/arm/mach-ux500/board-mop500.h                 |    4 ++--
>  4 files changed, 17 insertions(+), 17 deletions(-)
>  rename arch/arm/mach-ux500/{board-mop500-msp.c => board-mop500-audio.c} (98%)
> 
> diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
> index 026086f..1dc2cfa 100644
> --- a/arch/arm/mach-ux500/Makefile
> +++ b/arch/arm/mach-ux500/Makefile
> @@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
>  				board-mop500-uib.o board-mop500-stuib.o \
>  				board-mop500-u8500uib.o \
>  				board-mop500-pins.o \
> -				board-mop500-msp.o
> +				board-mop500-audio.o
>  obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
> diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
> similarity index 98%
> rename from arch/arm/mach-ux500/board-mop500-msp.c
> rename to arch/arm/mach-ux500/board-mop500-audio.c
> index 2af017f..18f6c5a 100644
> --- a/arch/arm/mach-ux500/board-mop500-msp.c
> +++ b/arch/arm/mach-ux500/board-mop500-audio.c
> @@ -172,14 +172,7 @@ struct msp_i2s_platform_data msp3_platform_data = {
>  	.msp_i2s_dma_tx	= NULL,
>  };
>  
> -/* Due for removal once the MSP driver has been fully DT:ed. */
> -void mop500_of_msp_init(struct device *parent)
> -{
> -	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> -	platform_device_register(&ux500_pcm);
> -}
> -
> -void mop500_msp_init(struct device *parent)
> +void mop500_audio_init(struct device *parent)
>  {
>  	pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
>  	platform_device_register(&snd_soc_mop500);
> @@ -197,3 +190,10 @@ void mop500_msp_init(struct device *parent)
>  	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
>  	platform_device_register(&ux500_pcm);
>  }
> +
> +/* Due for removal once the MSP driver has been fully DT:ed. */
> +void mop500_of_audio_init(struct device *parent)
> +{
> +	pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
> +	platform_device_register(&ux500_pcm);
> +}
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index 0c141d5..7152635 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -607,7 +607,7 @@ static void __init mop500_init_machine(void)
>  	mop500_i2c_init(parent);
>  	mop500_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	u8500_cryp1_hash1_init(parent);
> @@ -641,7 +641,7 @@ static void __init snowball_init_machine(void)
>  	mop500_i2c_init(parent);
>  	snowball_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	/* This board has full regulator constraints */
> @@ -673,7 +673,7 @@ static void __init hrefv60_init_machine(void)
>  	mop500_i2c_init(parent);
>  	hrefv60_sdi_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_msp_init(parent);
> +	mop500_audio_init(parent);
>  	mop500_uart_init(parent);
>  
>  	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
> @@ -807,7 +807,7 @@ static void __init u8500_init_machine(void)
>  				ARRAY_SIZE(mop500_platform_devs));
>  
>  		mop500_sdi_init(parent);
> -		mop500_msp_init(parent);
> +		mop500_audio_init(parent);
>  		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>  		i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>  		i2c_register_board_info(2, mop500_i2c2_devices,
> @@ -816,7 +816,7 @@ static void __init u8500_init_machine(void)
>  		mop500_uib_init();
>  
>  	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
> -		mop500_of_msp_init(parent);
> +		mop500_of_audio_init(parent);
>  	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
>  		/*
>  		 * The HREFv60 board removed a GPIO expander and routed
> @@ -828,7 +828,7 @@ static void __init u8500_init_machine(void)
>  				ARRAY_SIZE(mop500_platform_devs));
>  
>  		hrefv60_sdi_init(parent);
> -		mop500_msp_init(parent);
> +		mop500_audio_init(parent);
>  
>  		i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
>  		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
> diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
> index 3fbf48f..9e9dd5a 100644
> --- a/arch/arm/mach-ux500/board-mop500.h
> +++ b/arch/arm/mach-ux500/board-mop500.h
> @@ -97,9 +97,9 @@ void __init mop500_stuib_init(void);
>  void __init mop500_pinmaps_init(void);
>  void __init snowball_pinmaps_init(void);
>  void __init hrefv60_pinmaps_init(void);
> -void mop500_msp_init(struct device *parent);
> +void mop500_audio_init(struct device *parent);
>  /* Due for removal once the MSP driver has been fully DT:ed. */
> -void mop500_of_msp_init(struct device *parent);
> +void mop500_of_audio_init(struct device *parent);
>  
>  int __init mop500_uib_init(void);
>  void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
> -- 
> 1.7.9.5
> 


Regards, 
Gururaja


From swarren at wwwdotorg.org  Fri Aug 24 11:19:09 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 24 Aug 2012 09:19:09 -0600
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
Message-ID: <50379B6D.6070706@wwwdotorg.org>

On 08/24/2012 02:23 AM, Bill Huang wrote:
> Hi,
> 

[Explicitly CCing a few people, and dropping the linux-kernel mailing
list since the ARM list is most useful]

> When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC registers through I2C
> to perform the power off sequence. Unfortunately, sometimes we'll fail to shutdown
> due to I2C timeout on Tegra20. And the cause of the timeout is due to the CPU which I2C
> controller IRQ affined to will have chance to be offlined without migrating all irqs affined 
> to it, so the following I2C transactions will fail (no any CPU will handle that interrupt
> since then).
> 
> Some snippet of the shutdown codes:
> 
> void kernel_power_off(void)
> {
> 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
> 	:
> 	disable_nonboot_cpus();
> 	:
> 	machine_power_off();
> }
> 
> void machine_power_off(void)
> {
> 	machine_shutdown();
> 	if (pm_power_off)
> 		pm_power_off(); /* this is where we send I2C write to shutdown */
> }
> 
> void machine_shutdown(void)
> {
> #ifdef CONFIG_SMP
> 	smp_send_stop();
> #endif
> }
> 
> In "smp_send_stop()", it will send "IPI_CPU_STOPS" to offline other cpus except
> current cpu (smp_processor_id()), however, current cpu will not always be cpu0 at
> least at Tegra20, that said for example cpu1 might be the current cpu and cpu0 will
> be offlined and this is the case why the I2C transaction will timeout. 
> 
> For normal case, "disable_nonboot_cpus()" call will disable all other Cpus except
> cpu0, that means we won't hit the problem mentioned here since cpu0 will always be
> the current cpu in the call "smp_send_stop", but the call to "disable_nonboot_cpus" 
> will happen only when "CONFIG_PM_SLEEP_SMP" is enabled which is not the case for
> Tegra20/Tegra30, we don't support suspend yet so this can't be enabled.
> 
> There are two known fix for this, the first one is enable suspend (ARCH_SUSPEND_POSSIBLE)
> so the cpu0 will be the only online cpu while doing "machine_shutdown". The second
> fix is adding call to "migrate_irqs()" in "ipi_cpu_stop" so all irqs can be migrated to
> the active cpu.
> 
> Could someone familiar with the ARM SMP design help to answer my two questions?
> 
> 1. Does it make sense that "smp_processor_id()" could be non-cpu0 in the call
>    "smp_send_stop()"? In Tegra30 it will always be cpu0 but Tegra20 will be 50-50,
>    I just can't find the magic.
> 
> 2. If current cpu is not necessarily be cpu0 in the call "smp_send_stop()", then
>    does it make sense to add "migrate_irqs()" in "ipi_cpu_stop()"? Or is there any
>    other fix which makes more sense?
> 
> Thanks,
> Bill



From festevam at gmail.com  Fri Aug 24 11:24:50 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 24 Aug 2012 12:24:50 -0300
Subject: [PATCH] ARM: imx6q-sabrelite: Rename 'pinctrl_gpio_hog'
Message-ID: <1345821890-2922-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

'pinctrl_gpio_hog' is used to setup the pin functions, and it is not neccesarily used only
for GPIO pins, so remove 'gpio' from its name to describe a more generic term.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..2e01478 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,10 +46,10 @@
 
 			iomuxc at 020e0000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_gpio_hog>;
+				pinctrl-0 = <&pinctrl_hog>;
 
 				gpios {
-					pinctrl_gpio_hog: gpiohog {
+					pinctrl_hog: hog {
 						fsl,pins = <
 							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
 							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-- 
1.7.9.5



From paul at pwsan.com  Fri Aug 24 11:38:01 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 24 Aug 2012 15:38:01 +0000 (UTC)
Subject: [PATCH] ARM: omap_hwmod: Fix up resource names when booted with
 devicetree
In-Reply-To: <1345730049-12675-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345730049-12675-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <alpine.DEB.2.00.1208241536290.25436@utopia.booyaka.com>

Hello P?ter,

On Thu, 23 Aug 2012, Peter Ujfalusi wrote:

> When booted with some resource will have their name set to NULL. This can
> cause later kernel crash since this is not expected by the platform code.
> 
> When we boot without DT the devices are created with platform_device_add()
> which itself fixes up the missing resource names:
> if (r->name == NULL)
> 	r->name = dev_name(&pdev->dev);
> 
> The of core also fixes up the resource names when taking the information
> from DT data - in __of_address_to_resource():
> r->name = name ? name : dev->full_name;
> 
> When we boot OMAP with devicetree: of will create the devices based on the
> DT data so the resource names are guarantied to be not NULL. Since we have
> the 'ti,hwmod' tag, we remove the of created resources from the device and
> re-create them based on hwmod data. If the hwmod data does not specify a
> name for a resource it will be NULL.
> This can cause kernel crash if the driver uses
> platform_get_resource_byname() to get any resource.

Do we need both this one and your '[PATCH] driver core: Check if r->name 
is valid in platform_get_resource_byname()' ?  Or would that second patch 
be enough?  Is the crash happening in the platform_get_resource_byname() 
iterator?


- Paul

From marex at denx.de  Fri Aug 24 11:38:45 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 24 Aug 2012 17:38:45 +0200
Subject: SLAVE Side SPI kernel driver development
In-Reply-To: <CAOMZO5Ds6NKsTCptQXDGZDJasb119hYWqXMzX8nG5WFArysL7A@mail.gmail.com>
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>
 <CAOMZO5Ds6NKsTCptQXDGZDJasb119hYWqXMzX8nG5WFArysL7A@mail.gmail.com>
Message-ID: <201208241738.45601.marex@denx.de>

Dear Fabio Estevam,

> On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)

CCing SPI list

> <carlo_bastelli at yahoo.it> wrote:
> > Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
> > develop
> > 
> >  a driver SPI slave side on embedded ARM processor running Linux.
> > 
> > Precisely linux occur on the SPI bus as a slave, not master as required
> > by the hierarchical structure of the current kernel. The new driver
> > will
> > 
> >  receive via interrupt and respond when selected by its chip select.

So a soft-spi ? It's gonna be slow as hell and unstable too.

> >  Can
> >  anyone suggest the best way to develop this driver?

Get a CPU which has SPI-slave capable IP, start from there. If you were to 
implement soft-spi this way, you'd have to use FIQ on ARM, to be able to handle 
stuff with reasonable latency ... check how the ps/2-gpio driver is done in 
Linux ... I tried it, it barely worked, you don't want to go down that road.

> >  Personally, I
> > 
> > have identified two main roads, the first if possible to exploit the
> > structure SPI master driver

Not happening. You'd have to split the parts from the struct spi_master into 
common and master-only parts. That's for starters.

> > with a few tricks that now I can not
> > define. The second most radical, write a driver for a UART like, but
> > managing the SPI device.
> > Thank you for any suggestions or examples.

First of all, the SPI slave mode is COMPLETELY different from the master mode. 
You need to react on incoming CS-low ASAP, which might turn out to be a problem 
on it's own. Then, even if you do, you do not know how long the transfer is 
going to be, so you need to allocate enough buffers as the transfer progresses 
onwards.

In case of your soft-spi, how do you plan to sample the CLK line to sync clock?

> Marek got spi slave running on a mx28. See his patch:
> http://www.spinics.net/lists/arm-kernel/msg190860.html

This was tested (and developed) on this board:
http://www.denx-cs.de/?q=M28

The userland code is really easy too, simply pump it into spidev or read from 
it. But all that is only possible because of the SPI IP in the mx28 is nice.

> Regards,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From tony at atomide.com  Fri Aug 24 11:53:48 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 08:53:48 -0700
Subject: [PATCH] MMC: OMAP MSDI: fix broken PIO mode
In-Reply-To: <20120824072509.GC3334@arwen.pp.htv.fi>
References: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com>
 <20120824072509.GC3334@arwen.pp.htv.fi>
Message-ID: <20120824155347.GO11011@atomide.com>

* Felipe Balbi <balbi at ti.com> [120824 00:29]:
> 
> this looks good to me, though I don't have how to test. FWIW:
> 
> Reviewed-by: Felipe Balbi <balbi at ti.com>

Works for me:

Tested-by: Tony Lindgren <tony at atomide.com>


From hvaibhav at ti.com  Fri Aug 24 11:56:13 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 24 Aug 2012 15:56:13 +0000
Subject: [RFC RESEND 2/4] ARM: OMAP3: Dynamically disable secure timer
 nodes for secure devices
In-Reply-To: <502E37E9.3060201@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-3-git-send-email-jon-hunter@ti.com>
 <502B6838.9080907@ti.com> <502D2686.4090107@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA91D63@DBDE01.ent.ti.com>
 <502E37E9.3060201@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA980D4@DBDE01.ent.ti.com>

On Fri, Aug 17, 2012 at 17:54:09, Hunter, Jon wrote:
> 
> On 08/17/2012 12:32 AM, Hiremath, Vaibhav wrote:
> > On Thu, Aug 16, 2012 at 22:27:42, Hunter, Jon wrote:
> >>
> >> On 08/15/2012 04:13 AM, Vaibhav Hiremath wrote:
> >>>
> >>>
> >>> On 7/14/2012 3:56 AM, Jon Hunter wrote:
> >>>> OMAP3 devices may or may not have security features enabled. Security enabled
> >>>> devices are known as high-secure (HS) and devices without security are known as
> >>>> general purpose (GP).
> >>>>
> >>>> For OMAP3 devices there are 12 general purpose timers available. On secure
> >>>> devices the 12th timer is reserved for secure usage and so cannot be used by
> >>>> the kernel, where as for a GP device it is available. We can detect the OMAP
> >>>> device type, secure or GP, at runtime via an on-chip register. Today, when not
> >>>> using DT, we do not register the 12th timer as a linux device if the device is
> >>>> secure.
> >>>>
> >>>> When using device tree, device tree is going to register all the timer devices
> >>>> it finds in the device tree blob. To prevent device tree from registering 12th
> >>>> timer on a secure OMAP3 device we can add a status property to the timer
> >>>> binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
> >>>> device has a property "ti,timer-secure" to indicate that it will not be
> >>>> available on a secure device and so for secure OMAP3 devices, we search for
> >>>> timers with this property and then disable them. Using the prom_add_property()
> >>>> function to dynamically add a property was a recommended approach suggested by
> >>>> Rob Herring [1].
> >>>>
> >>>> I have tested this on an OMAP3 GP device and faking it to pretend to be a
> >>>> secure device to ensure that any timers marked with "ti,timer-secure" are not
> >>>> registered on boot. I have also made sure that all timers are registered as
> >>>> expected on a GP device by default.
> >>>>
> >>>> [1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
> >>>>
> >>>> Signed-off-by: Jon Hunter <jon-hunter at ti.com>
> >>>> ---
> >>>>  arch/arm/mach-omap2/board-generic.c |    1 +
> >>>>  arch/arm/mach-omap2/common.h        |    1 +
> >>>>  arch/arm/mach-omap2/timer.c         |   36 +++++++++++++++++++++++++++++++++++
> >>>>  3 files changed, 38 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> >>>> index 6f93a20..20124d7 100644
> >>>> --- a/arch/arm/mach-omap2/board-generic.c
> >>>> +++ b/arch/arm/mach-omap2/board-generic.c
> >>>> @@ -40,6 +40,7 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
> >>>>  static void __init omap_generic_init(void)
> >>>>  {
> >>>>  	omap_sdrc_init(NULL, NULL);
> >>>> +	omap_dmtimer_init();
> >>>>  
> >>>>  	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
> >>>>  }
> >>>> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> >>>> index 1f65b18..d6a4875 100644
> >>>> --- a/arch/arm/mach-omap2/common.h
> >>>> +++ b/arch/arm/mach-omap2/common.h
> >>>> @@ -326,6 +326,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
> >>>>  				      struct omap_sdrc_params *sdrc_cs1);
> >>>>  struct omap2_hsmmc_info;
> >>>>  extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
> >>>> +extern void omap_dmtimer_init(void);
> >>>>  
> >>>>  #endif /* __ASSEMBLER__ */
> >>>>  #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
> >>>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> >>>> index 13d20c8..e3b9931 100644
> >>>> --- a/arch/arm/mach-omap2/timer.c
> >>>> +++ b/arch/arm/mach-omap2/timer.c
> >>>> @@ -36,6 +36,7 @@
> >>>>  #include <linux/clocksource.h>
> >>>>  #include <linux/clockchips.h>
> >>>>  #include <linux/slab.h>
> >>>> +#include <linux/of.h>
> >>>>  
> >>>>  #include <asm/mach/time.h>
> >>>>  #include <plat/dmtimer.h>
> >>>> @@ -482,6 +483,41 @@ static int __init omap2_dm_timer_init(void)
> >>>>  }
> >>>>  arch_initcall(omap2_dm_timer_init);
> >>>>  
> >>>> +static struct property timer_disabled = {
> >>>> +	.name = "status",
> >>>> +	.length = sizeof("disabled"),
> >>>> +	.value = "disabled",
> >>>> +};
> >>>> +
> >>>> +static struct of_device_id omap3_timer_match[] __initdata = {
> >>>> +	{ .compatible = "ti,omap3-timer", },
> >>>> +	{ }
> >>>> +};
> >>>> +
> >>>> +/**
> >>>> + * omap_dmtimer_init - initialisation function when device tree is used
> >>>> + *
> >>>> + * For secure OMAP3 devices, timers with device type "timer-secure" cannot
> >>>> + * be used by the kernel as they are reserved. Therefore, to prevent the
> >>>> + * kernel registering these devices remove them dynamically from the device
> >>>> + * tree on boot.
> >>>> + */
> >>>> +void __init omap_dmtimer_init(void)
> >>>> +{
> >>>> +	struct device_node *np;
> >>>> +
> >>>> +	if (!cpu_is_omap34xx())
> >>>> +		return;
> >>>> +
> >>>
> >>> Sorry for responding so late, but why only omap34xx check here?
> >>> Isn't this applicable to all omap & non-omap devices?
> >>
> >> It is only applicable to omap3 devices as far as omap is concerned.
> >>
> >> By non-omap, you are referring to the AMxxx stuff?
> >>
> >> Do AMxxx devices even support security (ie. secure boot and have secure
> >> peripherals)? If not then this will work for AMxxx devices too.
> >>
> > 
> > Yes it does. 
> > 
> > AM33xx has 8 timers and Timer-0 is a secure timer. As in case of OMAP3, we 
> > do not even register timer-0 to kernel.
> 
> Ok, however, please note that the omap3 timer 12 is a special case,
> because on a non-secure device it is available for general purpose use
> and only reserved for secure use on a secure device.
> 
> For omap4/5 timer 12 is always a secure timer and so we never register
> it for any device (secure or non-secure) by using the "ti,timer-secure"
> property in DT.
> 
> So, for AM33xx, is timer0 always reserved for secure used on non-secure
> and secure devices? If so, then timer0 just needs to add the
> "ti,timer-secure" property in device-tree file and it will not be
> registered and no change is needed in the above code.
> 

I think you may be right here, AM33XX secure timer is similar to omap4, so
Just "ti,timer-secure" property should be enough.

Thanks,
Vaibhav


From dirk.behme at gmail.com  Fri Aug 24 11:58:43 2012
From: dirk.behme at gmail.com (Dirk Behme)
Date: Fri, 24 Aug 2012 17:58:43 +0200
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
References: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
Message-ID: <5037A4B3.7030001@gmail.com>

On 24.08.2012 16:52, Beno?t Th?baudeau wrote:
> Hi Sascha,
>
> On Thu, Jun 14, 09:43:26 EDT 2012, Sascha Hauer wrote:
>> The IPU is the Image Processing Unit found on i.MX51/53 SoCs. It
>> features several units for image processing, this patch adds support
>> for the units needed for Framebuffer support, namely:
>>
>> - Display Controller (dc)
>> - Display Interface (di)
>> - Display Multi Fifo Controller (dmfc)
>> - Display Processor (dp)
>> - Image DMA Controller (idmac)
>>
>> This patch is based on the Freescale driver, but follows a different
>> approach. The Freescale code implements logical idmac channels and
>> the handling of the subunits is hidden in common idmac code pathes
>> in big switch/case statements. This patch instead just provides code
>> and resource management for the different subunits. The user, in this
>> case the framebuffer driver, decides how the different units play
>> together.
>
> What is the status of this series, and especially of this patch, as to its
> integration into upstream? At some point, you were talking about pushing it to
> staging, but since things don't seem to have evolved.
>
>> The IPU has other units missing in this patch:
>>
>> - CMOS Sensor Interface (csi)
>> - Video Deinterlacer (vdi)
>> - Sensor Multi FIFO Controler (smfc)
>> - Image Converter (ic)
>> - Image Rotator (irt)
>>
>> So expect more files to come in this directory.
>
> Do you have a schedule for that? Are you waiting for more customer projects at
> Pengutronix to do that?
>
> Would your customers_pengutronix_mx5_master-20120612 tag be the starting point
> for these new files? Can it be used as a working solution in the meantime, or
> does it have limitations?
>
> That would be great to finally have full IPU/VPU/GPU support for i.MX5 into
> upstream. As you already know, Linaro also have some video support for i.MX5 in
> this head:
> http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=shortlog;h=refs/heads/lt-3.2-imx5
>
> Matt, I think you also have video support for efikamx, don't you?
>
> Is there a plan to merge all these developments into upstream?

It's my understanding that Richard is looking at the VPU for i.MX6, 
based on Sascha's IPU patches (this thread) and Javier Martin's i.MX27 
coda patches.

Best regards

Dirk

P.S.: Sascha might be on holiday, just in case there is no immediate 
answer from him ;)


From nicolas.ferre at atmel.com  Fri Aug 24 11:59:47 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 24 Aug 2012 17:59:47 +0200
Subject: [GIT PULL] at91: fixes for 3.6 (take 1)
Message-ID: <5037A4F3.9090608@atmel.com>

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-fixes

for you to fetch changes up to 0d4d1e37ca732615717d4434b58682f81a6bb61c:

  ARM: at91/feature-removal-schedule: delay at91_mci removal (2012-08-24 10:45:07 +0200)

----------------------------------------------------------------
Fixes for AT91 related to:
- move to sparse IRQ: some drivers were forgotten
- a build error in sound driver & a DTS typo
- the delay for removal of old at91_mci driver

----------------------------------------------------------------
Bo Shen (1):
      ARM: at91/dts: remove partial parameter in at91sam9g25ek.dts

Joachim Eastwood (1):
      ASoC: atmel-ssc: include linux/io.h for raw io

Ludovic Desroches (3):
      ARM: at91: fix system timer irq issue due to sparse irq support
      ARM: at91: fix rtc-at91sam9 irq issue due to sparse irq support
      ARM: at91/feature-removal-schedule: delay at91_mci removal

Nicolas Ferre (1):
      ARM: at91/clock: fix PLLA overclock warning

 Documentation/feature-removal-schedule.txt |    2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts        |    2 +-
 arch/arm/mach-at91/at91rm9200_time.c       |    2 +-
 arch/arm/mach-at91/at91sam9260_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9261_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9263_devices.c   |   10 ++++++++--
 arch/arm/mach-at91/at91sam9g45_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9rl_devices.c    |    6 +++++-
 arch/arm/mach-at91/clock.c                 |   12 ++++++++++++
 drivers/rtc/rtc-at91sam9.c                 |   22 +++++++++++++++-------
 include/linux/atmel-ssc.h                  |    1 +
 11 files changed, 59 insertions(+), 16 deletions(-)

Thanks, best regards,
-- 
Nicolas Ferre


From gcembed at gmail.com  Fri Aug 24 12:17:44 2012
From: gcembed at gmail.com (=?UTF-8?q?Ga=C3=ABtan=20Carlier?=)
Date: Fri, 24 Aug 2012 18:17:44 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <1345811288.2848.308.camel@sauron.fi.intel.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
Message-ID: <1345825064-9147-1-git-send-email-gcembed@gmail.com>

Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
Warning: The same solution needs to be applied to the boot loader and the
flash programmer.

This is a modified version of patch sent by J?rgen Lambrecht :
[PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block Indicator,
and use for imx27pdk nand support.

 v3: - use accessor function for I/O memory accesses as suggested by Artem
       Bityutskiy
     - rename function name as suggested by Artem Bityutskiy

 v2: - Use a flag in a mxc_nand_platform structure instead of adding option
       in Kconfig

 v1: - Original patch "Add 'config IMX_NFC_V1_BISWAP'" by J?rgen Lambrecht

Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
---
 arch/arm/plat-mxc/include/mach/mxc_nand.h |    2 ++
 drivers/mtd/nand/mxc_nand.c               |   26 ++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 6bb96ef..7c04437 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -26,6 +26,8 @@ struct mxc_nand_platform_data {
 	unsigned int width;	/* data bus width in bytes */
 	unsigned int hw_ecc:1;	/* 0 if suppress hardware ECC */
 	unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+	unsigned int biswap:1;	/* set to 1 to swap the Bad Block Indicator
+				   NFC v1 workaround */
 	struct mtd_partition *parts;	/* partition table */
 	int nr_parts;			/* size of parts */
 };
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 3f94e1f..24fc9e1 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -682,6 +682,26 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 	return 0;
 }
 
+/*
+ * Swap the BI-byte on position 0x7D0 with a data byte at 0x835.
+ * To fix a bug in NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
+ * Warning: The same solution needs to be applied to the boot loader and the
+ * flash programmer.
+ */
+static void nfcv1_bi_swap_quirk(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	struct mxc_nand_host *host = nand_chip->priv;
+	unsigned short temp1, temp2, new_temp1;
+
+	temp1 = ioread16(host->main_area0 + 0x7D0);
+	temp2 = ioread16(host->main_area0 + 0x834);
+	new_temp1 = (temp1 & 0xFF00) | (temp2 >> 8);
+	temp2 = (temp2 & 0x00FF) | (temp1 << 8);
+	iowrite16(new_temp1, host->main_area0 + 0x7D0);
+	iowrite16(temp2, host->main_area0 + 0x834);
+}
+
 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = mtd->priv;
@@ -1093,6 +1113,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 
 		host->devtype_data->send_page(mtd, NFC_OUTPUT);
 
+		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
+			nfcv1_bi_swap_quirk(mtd);
+
 		memcpy32_fromio(host->data_buf, host->main_area0,
 				mtd->writesize);
 		copy_spare(mtd, true);
@@ -1112,6 +1135,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 	case NAND_CMD_PAGEPROG:
 		memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
 		copy_spare(mtd, false);
+		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
+			nfcv1_bi_swap_quirk(mtd);
+
 		host->devtype_data->send_page(mtd, NFC_INPUT);
 		host->devtype_data->send_cmd(host, command, true);
 		mxc_do_addr_cycle(mtd, column, page_addr);
-- 
1.7.7.4



From peter.ujfalusi at ti.com  Fri Aug 24 12:20:30 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri, 24 Aug 2012 19:20:30 +0300
Subject: [PATCH] ARM: omap_hwmod: Fix up resource names when booted with
 devicetree
In-Reply-To: <alpine.DEB.2.00.1208241536290.25436@utopia.booyaka.com>
References: <1345730049-12675-1-git-send-email-peter.ujfalusi@ti.com>
 <alpine.DEB.2.00.1208241536290.25436@utopia.booyaka.com>
Message-ID: <5037A9CE.1080809@ti.com>

Hi Paul,

On 08/24/2012 06:38 PM, Paul Walmsley wrote:
> Do we need both this one and your '[PATCH] driver core: Check if r->name 
> is valid in platform_get_resource_byname()' ?  Or would that second patch 
> be enough?  Is the crash happening in the platform_get_resource_byname() 
> iterator?

The crash happens in platform_get_resource_byname(). What I see as a problem
that when we boot without DT the r->name is configured for the hwmods. If we
boot with DT we discard the resources created by the OF (which also have the
r->name configured). We replace the resources from hwmods but we do not fix up
the resource names (which is done in other cases).
I have sent the patch for the drivers core as well since I think it is a good
practice anyway to check for NULL pointer before strcmp().

Either is good, but IMHO we should fix this in omap_hwmod (at least).

-- 
P?ter


From tomasz.figa at gmail.com  Fri Aug 24 12:40:16 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 24 Aug 2012 18:40:16 +0200
Subject: [PATCH v5 1/2] ARM: Make a compile firmware conditionally
In-Reply-To: <20120824083351.GA25369@july>
References: <20120824083351.GA25369@july>
Message-ID: <1672307.utfAA3y7zd@flatron>

Hello,

On Friday 24 of August 2012 17:33:51 Kyungmin Park wrote:
> From: Kyungmin Park <kyungmin.park at samsung.com>
> 
> Some boards can use the firmware at trustzone but others can't use this.
> However we need to build it simultaneously. To address this issue,
> introduce arm firmware support and use it at each board files.
> 
> e.g., In boot_secondary at mach-exynos/platsmp.c
> 
>         __raw_writel(virt_to_phys(exynos4_secondary_startup),
>                 CPU1_BOOT_REG);
> 
>         if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
>                 /* Call Exynos specific smc call */
>                 do_firmware_op(cpu_boot, cpu);
>         }

There is no need for if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) now when we have 
conditional call_firmware_op macro.

Also I guess there is a typo: s/do_firmware_op/call_firmware_op/ .

--
Best regards,
Tomasz Figa

>         gic_raise_softirq(cpumask_of(cpu), 1);
> 
>         if (pen_release == -1)
> 
> e.g., exynos4412 based board
> 
> static void __init board_init_early(void)
> {
>         exynos_firmware_init();
> }
> 
> TODO
>         1. DT support.
>         2. call firmware init by smp_ops.
> 
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> Changelog v4
> 	use call_firmware_op commented by Tomasz Figa.
> 	remove useless core_initcall
> 
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index 283fa1d..5b097ca 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -21,6 +21,9 @@ config ARM_VIC_NR
>  	  The maximum number of VICs available in the system, for
>  	  power management.
> 
> +config ARM_FIRMWARE
> +	bool
> +
>  config ICST
>  	bool
> 
> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> index e8a4e58..4af6568 100644
> --- a/arch/arm/common/Makefile
> +++ b/arch/arm/common/Makefile
> @@ -4,6 +4,7 @@
> 
>  obj-$(CONFIG_ARM_GIC)		+= gic.o
>  obj-$(CONFIG_ARM_VIC)		+= vic.o
> +obj-$(CONFIG_ARM_FIRMWARE)	+= firmware.o
>  obj-$(CONFIG_ICST)		+= icst.o
>  obj-$(CONFIG_SA1111)		+= sa1111.o
>  obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
> diff --git a/arch/arm/common/firmware.c b/arch/arm/common/firmware.c
> new file mode 100644
> index 0000000..e375e9f
> --- /dev/null
> +++ b/arch/arm/common/firmware.c
> @@ -0,0 +1,25 @@
> +/*
> + *  Copyright (C) 2012 Samsung Electronics.
> + *  Kyungmin Park <kyungmin.park at samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/suspend.h>
> +
> +#include <asm/firmware.h>
> +
> +static void cpu_boot(int cpu)
> +{
> +	/* Do nothing */
> +}
> +
> +static struct firmware_ops default_firmware_ops = {
> +	.do_idle		= cpu_do_idle,
> +	.cpu_boot		= cpu_boot,
> +};
> +
> +struct firmware_ops *firmware_ops = &default_firmware_ops;
> diff --git a/arch/arm/include/asm/firmware.h
> b/arch/arm/include/asm/firmware.h new file mode 100644
> index 0000000..99c97ff
> --- /dev/null
> +++ b/arch/arm/include/asm/firmware.h
> @@ -0,0 +1,27 @@
> +/*
> + *  Copyright (C) 2012 Samsung Electronics.
> + *  Kyungmin Park <kyungmin.park at samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_ARM_FIRMWARE_H
> +#define __ASM_ARM_FIRMWARE_H
> +
> +struct firmware_ops {
> +	int	(*do_idle)(void);
> +	void	(*cpu_boot)(int cpu);
> +};
> +
> +extern struct firmware_ops *firmware_ops;
> +
> +#ifdef CONFIG_ARM_FIRMWARE
> +#define call_firmware_op(op, ...)					\
> +	((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : 0)
> +#else
> +#define call_firmware_op(op, ...)		do { } while (0)
> +#endif
> +
> +#endif
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From nforrester at whoi.edu  Fri Aug 24 12:54:55 2012
From: nforrester at whoi.edu (Ned Forrester)
Date: Fri, 24 Aug 2012 12:54:55 -0400
Subject: SLAVE Side SPI kernel driver development
In-Reply-To: <201208241738.45601.marex@denx.de>
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>	<CAOMZO5Ds6NKsTCptQXDGZDJasb119hYWqXMzX8nG5WFArysL7A@mail.gmail.com>
 <201208241738.45601.marex@denx.de>
Message-ID: <5037B1DF.40503@whoi.edu>

On 08/24/2012 11:38 AM, Marek Vasut wrote:
> Dear Fabio Estevam,
> 
>> On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)
> 
> CCing SPI list
> 
>> <carlo_bastelli at yahoo.it> wrote:
>>> Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
>>> develop
>>>
>>>  a driver SPI slave side on embedded ARM processor running Linux.
>>>
>>> Precisely linux occur on the SPI bus as a slave, not master as required
>>> by the hierarchical structure of the current kernel. The new driver
>>> will
>>>
>>>  receive via interrupt and respond when selected by its chip select.
> 
> So a soft-spi ? It's gonna be slow as hell and unstable too.
> 
>>>  Can
>>>  anyone suggest the best way to develop this driver?
> 
> Get a CPU which has SPI-slave capable IP, start from there. If you were to 
> implement soft-spi this way, you'd have to use FIQ on ARM, to be able to handle 
> stuff with reasonable latency ... check how the ps/2-gpio driver is done in 
> Linux ... I tried it, it barely worked, you don't want to go down that road.
> 
>>>  Personally, I
>>>
>>> have identified two main roads, the first if possible to exploit the
>>> structure SPI master driver
> 
> Not happening. You'd have to split the parts from the struct spi_master into 
> common and master-only parts. That's for starters.
> 
>>> with a few tricks that now I can not
>>> define. The second most radical, write a driver for a UART like, but
>>> managing the SPI device.
>>> Thank you for any suggestions or examples.
> 
> First of all, the SPI slave mode is COMPLETELY different from the master mode. 
> You need to react on incoming CS-low ASAP, which might turn out to be a problem 
> on it's own. Then, even if you do, you do not know how long the transfer is 
> going to be, so you need to allocate enough buffers as the transfer progresses 
> onwards.
> 
> In case of your soft-spi, how do you plan to sample the CLK line to sync clock?
> 
>> Marek got spi slave running on a mx28. See his patch:
>> http://www.spinics.net/lists/arm-kernel/msg190860.html
> 
> This was tested (and developed) on this board:
> http://www.denx-cs.de/?q=M28
> 
> The userland code is really easy too, simply pump it into spidev or read from 
> it. But all that is only possible because of the SPI IP in the mx28 is nice.
> 
>> Regards,
>>
>> Fabio Estevam
> 
> Best regards,
> Marek Vasut

I generally agree with the above comments.  A generalized SPI slave must
be able to respond instantly, often within one clock cycle.  This can
only work in hardware, or in an OS like Linux when the activity on the
bus is completely predictable by the Linux slave.  The only cases I know
of are streaming of data in a predictable way between a single master
and single slave (no other devices on the bus).

This topic comes up periodically, but I don't think there has been any
change in the situation for all the time I've followed the discussion.
I recommend that you read the archives of this mailing list to
understand the limitations of a potential slave mode.  The archives can
be found at:

http://sourceforge.net/mailarchive/forum.php?forum_name=spi-devel-general

then look for threads with "slave" in the subject in the following
months (I'd give thread start dates, but parts of the threads are
disconnected in the archives, and this is the easiest way to see all the
parts, day ranges are in parentheses):

2007/04	(13-18)
2007/09/27 and 2007/10 (13-17)
2009/03 (2-3)
2009/12/18 and 2010/1/19 and 2010/02 (14-16)
2010/07 (26) and 2010/08 (13)
2011/01 (28-31) and 2011/02 (1-10)
2011/10 (18)
2012/06 (29-30 and 2012/07 (1-17)

-- 
Ned Forrester                                       nforrester at whoi.edu
Oceanographic Systems Lab                           508-289-2226 Office
Applied Ocean Physics and Engineering Dept.
Woods Hole Oceanographic Institution          Woods Hole, MA 02543, USA
http://www.whoi.edu/
http://www.whoi.edu/page.do?pid=29856
http://www.whoi.edu/hpb/Site.do?id=1532



From tomasz.figa at gmail.com  Fri Aug 24 13:15:51 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Fri, 24 Aug 2012 19:15:51 +0200
Subject: [PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
In-Reply-To: <20120824083357.GA25384@july>
References: <20120824083357.GA25384@july>
Message-ID: <1708287.hpZdyEpgtl@flatron>

Hello,

Please see my comments inline.

On Friday 24 of August 2012 17:33:57 Kyungmin Park wrote:
> From: Kyungmin Park <kyungmin.park at samsung.com>
> 
> Some boards, e.g., exynos4412, can use smc instruction (aka firmware)
> interally.
> 
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> Changelog v4
> 	use call_firmware_op instead of indirect call
> 
> diff --git a/arch/arm/mach-exynos/Makefile
> b/arch/arm/mach-exynos/Makefile index 9b58024..8ee779c 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)	+= mct.o
> 
>  obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
> 
> +obj-$(CONFIG_ARM_FIRMWARE)	+= exynos-smc.o firmware.o
> +
> +plus_sec := $(call as-instr,.arch_extension sec,+sec)
> +AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
> +
>  # machine support
> 
>  obj-$(CONFIG_MACH_SMDKC210)		+= mach-smdkv310.o
> diff --git a/arch/arm/mach-exynos/common.h
> b/arch/arm/mach-exynos/common.h index aed2eeb..540918f 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -21,6 +21,8 @@ void exynos4_restart(char mode, const char *cmd);
>  void exynos5_restart(char mode, const char *cmd);
>  void exynos_init_late(void);
> 
> +void exynos_firmware_init(void);
> +
>  #ifdef CONFIG_PM_GENERIC_DOMAINS
>  int exynos_pm_late_initcall(void);
>  #else
> diff --git a/arch/arm/mach-exynos/exynos-smc.S
> b/arch/arm/mach-exynos/exynos-smc.S new file mode 100644
> index 0000000..2e27aa3
> --- /dev/null
> +++ b/arch/arm/mach-exynos/exynos-smc.S
> @@ -0,0 +1,22 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics.
> + *
> + * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
> + *
> + * This program is free software,you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +
> +/*
> + * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32
> arg3) + */
> +
> +ENTRY(exynos_smc)
> +	stmfd	sp!, {r4-r11, lr}
> +	dsb
> +	smc	#0
> +	ldmfd	sp!, {r4-r11, pc}
> +ENDPROC(exynos_smc)
> diff --git a/arch/arm/mach-exynos/firmware.c
> b/arch/arm/mach-exynos/firmware.c new file mode 100644
> index 0000000..a144593
> --- /dev/null
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -0,0 +1,37 @@
> +/*
> + *  Copyright (C) 2012 Samsung Electronics.
> + *  Kyungmin Park <kyungmin.park at samsung.com>
> + *
> + * This program is free software,you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +
> +#include <asm/firmware.h>
> +
> +#include "smc.h"
> +
> +static int exynos_do_idle(void)
> +{
> +        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
> +        return 0;
> +}
> +
> +static void exynos_cpu_boot(int cpu)
> +{
> +	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> +}
> +
> +static struct firmware_ops exynos_firmware_ops __initdata = {
> +	.do_idle	= exynos_do_idle,
> +	.cpu_boot	= exynos_cpu_boot,
> +};
> +
> +int __init exynos_firmware_init(void)
> +{
> +	firmware_ops = exynos_firmware_ops;
> +	return 0;
> +}
> diff --git a/arch/arm/mach-exynos/platsmp.c
> b/arch/arm/mach-exynos/platsmp.c index 36c3984..c664a86 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -25,6 +25,7 @@
>  #include <asm/hardware/gic.h>
>  #include <asm/smp_plat.h>
>  #include <asm/smp_scu.h>
> +#include <asm/firmware.h>
> 
>  #include <mach/hardware.h>
>  #include <mach/regs-clock.h>
> @@ -139,6 +140,12 @@ int __cpuinit boot_secondary(unsigned int cpu,
> struct task_struct *idle)
> 
>  		__raw_writel(virt_to_phys(exynos4_secondary_startup),
>  			CPU1_BOOT_REG);
> +
> +		if (IS_ENABLED(CONFIG_ARM_FIRMWARE)) {
> +			/* Call Exynos specific smc call */
> +			call_firmware_op(cpu_boot, cpu);
> +		}

We don't need to check IS_ENABLED(CONFIG_ARM_FIRMWARE) now as 
call_firmware_op does it for us.

--
Best regards,
Tomasz Figa

> +
>  		gic_raise_softirq(cpumask_of(cpu), 1);
> 
>  		if (pen_release == -1)
> diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
> new file mode 100644
> index 0000000..e972390
> --- /dev/null
> +++ b/arch/arm/mach-exynos/smc.h
> @@ -0,0 +1,31 @@
> +/*
> + *  Copyright (c) 2012 Samsung Electronics.
> + *
> + * EXYNOS - SMC Call
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_ARCH_EXYNOS_SMC_H
> +#define __ASM_ARCH_EXYNOS_SMC_H
> +
> +#define SMC_CMD_INIT            (-1)
> +#define SMC_CMD_INFO            (-2)
> +/* For Power Management */
> +#define SMC_CMD_SLEEP           (-3)
> +#define SMC_CMD_CPU1BOOT        (-4)
> +#define SMC_CMD_CPU0AFTR        (-5)
> +/* For CP15 Access */
> +#define SMC_CMD_C15RESUME       (-11)
> +/* For L2 Cache Access */
> +#define SMC_CMD_L2X0CTRL        (-21)
> +#define SMC_CMD_L2X0SETUP1      (-22)
> +#define SMC_CMD_L2X0SETUP2      (-23)
> +#define SMC_CMD_L2X0INVALL      (-24)
> +#define SMC_CMD_L2X0DEBUG       (-25)
> +
> +extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
> +
> +#endif
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From thomas.petazzoni at free-electrons.com  Fri Aug 24 13:26:02 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Fri, 24 Aug 2012 19:26:02 +0200
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120824120656.GH5400@mudshark.cambridge.arm.com>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
 <20120824135203.1bfd2b14@skate>
 <20120824120656.GH5400@mudshark.cambridge.arm.com>
Message-ID: <20120824192602.45f48636@skate>

Le Fri, 24 Aug 2012 13:06:56 +0100,
Will Deacon <will.deacon at arm.com> a ?crit :

> > The "Kernel Summit Attendee Information" e-mail that we have
> > received on August 22th still mentions that the workshops will only
> > take place on Tuesday 28, with the ARM workshop being in room
> > Marina 6, starting at 9:00 AM.
> 
> Thanks for pointing this out.
> 
> > In what room will take place the ARM workshop on Monday 27 ? I guess
> > the starting time will be 9:00 AM as well, is this correct?
> 
> That's right, we have the room from 9am both days and plan to start
> then.

Great, thanks for the confirmation.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From dgreid at chromium.org  Fri Aug 24 13:29:01 2012
From: dgreid at chromium.org (Dylan Reid)
Date: Fri, 24 Aug 2012 10:29:01 -0700
Subject: [alsa-devel] [PATCH] ASoC: samsung dma - prepare dma in
 start/resume trigger path
In-Reply-To: <00f001cd81e0$2ed8ccf0$8c8a66d0$@com>
References: <1345755069-9512-1-git-send-email-dgreid@chromium.org>
 <00df01cd81cb$e21d2f00$a6578d00$@com>
 <CAEUnVG58NPNKuf_PRyBEegYnH95dkTN81PGZGYxDt41jhH2uaQ@mail.gmail.com>
 <00f001cd81e0$2ed8ccf0$8c8a66d0$@com>
Message-ID: <CAEUnVG5WKsxML8L-ZUo_sNupjZYa11qFY4fPOX2SpUzLPFLWkg@mail.gmail.com>

On Fri, Aug 24, 2012 at 3:06 AM, Sangbeom Kim <sbkim73 at samsung.com> wrote:
> On Thu, Aug 24, 2012 at 4:52 PM, Dylan Reid wrote:
>> Yes. Currently, if I suspend while playing, after resume it won't work
>> until I close and reopen the device.  the call to snd_pcm_resume is
>> not indicating an error, but a write error comes from snd_pcm_write a
>> little later.
>
> Ok,
> Please let me know your test environment.

I'm using a 5250 evaluation board with a max98095 codec.

>
> Thanks,
> Sangbeom.
>


From r.schwebel at pengutronix.de  Fri Aug 24 13:38:08 2012
From: r.schwebel at pengutronix.de (Robert Schwebel)
Date: Fri, 24 Aug 2012 19:38:08 +0200
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
References: <1596192785.2810155.1345817566620.JavaMail.root@advansee.com>
 <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
Message-ID: <20120824173808.GN31821@pengutronix.de>

Beno?t,

On Fri, Aug 24, 2012 at 04:52:57PM +0200, Beno?t Th?baudeau wrote:
> What is the status of this series, and especially of this patch, as to
> its integration into upstream? At some point, you were talking about
> pushing it to staging, but since things don't seem to have evolved.

Things are making progress. The intention is to get the base patches
into staging; however, the holiday season made the progress a bit slow
recently.

> > The IPU has other units missing in this patch:
> >
> > - CMOS Sensor Interface (csi)
> > - Video Deinterlacer (vdi)
> > - Sensor Multi FIFO Controler (smfc)
> > - Image Converter (ic)
> > - Image Rotator (irt)
> >
> > So expect more files to come in this directory.
>
> Do you have a schedule for that? Are you waiting for more customer
> projects at Pengutronix to do that?

We don't have a fixed schedule; things make progress according to what
our projects make possible. The more customers we get behind this
effort, the more time we can spent on it.

- CSI is running on MX6 here
- Deinterlacer is WIP on MX53
- VPU was posted today, based on the Vista Silicon patches; we can do
  encoding and decoding, but not in all possible formats
- scaler works here
- We have a m2m plugin for GStreamer (which needs polishing as well, but
  works)

> That would be great to finally have full IPU/VPU/GPU support for i.MX5
> into upstream. As you already know, Linaro also have some video
> support for i.MX5 in this head:
> http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=shortlog;h=refs/heads/lt-3.2-imx5

That's quite an old tree... especially the port to 3.5 made a lot of
headache until all the oftree and clock issues were solved. However,
it's still good for reference.

> Is there a plan to merge all these developments into upstream?

>From our side: definitely! Everything is posted here on the lists when
it's in a state that we think we can show it to you folks.

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From matt at genesi-usa.com  Fri Aug 24 14:00:13 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Fri, 24 Aug 2012 13:00:13 -0500
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
References: <1596192785.2810155.1345817566620.JavaMail.root@advansee.com>
 <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
Message-ID: <CAKGA1bkjJXK8bUxLxRYz_4Rj9YW0mJxBMyg7ir+Hfo+s6Lza0w@mail.gmail.com>

On Fri, Aug 24, 2012 at 9:52 AM, Beno?t Th?baudeau
<benoit.thebaudeau at advansee.com> wrote:
> Hi Sascha,
>
> On Thu, Jun 14, 09:43:26 EDT 2012, Sascha Hauer wrote:
>> The IPU is the Image Processing Unit found on i.MX51/53 SoCs. It
>> features several units for image processing, this patch adds support
>> for the units needed for Framebuffer support, namely:
>>
>> - Display Controller (dc)
>> - Display Interface (di)
>> - Display Multi Fifo Controller (dmfc)
>> - Display Processor (dp)
>> - Image DMA Controller (idmac)
>>
>> This patch is based on the Freescale driver, but follows a different
>> approach. The Freescale code implements logical idmac channels and
>> the handling of the subunits is hidden in common idmac code pathes
>> in big switch/case statements. This patch instead just provides code
>> and resource management for the different subunits. The user, in this
>> case the framebuffer driver, decides how the different units play
>> together.
>
> What is the status of this series, and especially of this patch, as to its
> integration into upstream? At some point, you were talking about pushing it to
> staging, but since things don't seem to have evolved.

DRM guys "don't have time to review it", apparently.

I can't find the patch series in any patchwork (I probably am not
looking hard enough) but the base driver should be an MFD or something
or placed somewhere other than in DRM directories as it has been in
the past. It might make it quicker to review the core driver.

Then there is a major problem here; Sascha's DRM helper functions are
also basically rejected again (which is a shame..) and nobody really
has a cohesive device tree binding that would let us individually
initialize and specify IPU units. It's not something easy to
"tree-ize". I thought about it and walked away as it made my head
hurt. Those two make it INCREDIBLY difficult to engineer a solution
whereby a modular, independent IPU subsystem can support modular,
independent encoder/connector pairs (which are usually 1:1 the same
chip) without making the encoder/connector itself entirely dependent
on the DRM driver underneath. In the case of the SII9022 which is on
the Efika MX, this driver would need to be written for the Efika MX,
have specific support for MX53 Quickstart, debouncing of hotplug or
not depending on the board, some Beagle clones and TI's OMAP3 EVK have
the chip too, and many others floating around. Nobody wants to write
the same driver 5 times, and while the Silicon Image controllers are
wonderfully generic with a common API ("TPI") and there could be a
generic MFD solution with shim drivers on top for DRM, nobody else's
are quite as nice.

DRM just doesn't support the passing of information that makes this
generic, even if you had the binding. I was thinking of hijacking the
"slave encoder" subsystem which is designed to help PCI/AGP cards
register i2c buses local to the card (i.e. after PCI probe is done,
while the DRM subsystem is handling things) and access i2c data like
EDID or just talk to external encoder chips on these cards which
change every 5 minutes. It would need to be told which i2c bus it
needs to talk on (maybe a phandle to a ddc@ node for generic access,
or a phandle
to a specific encoder if the DDC is bounded by some kind of locking or
access restriction during normal use like on SII9022 - each slave
encoder would need to supply it's DDC access functions or push in good
default ones from another driver, but at the time of init, it cannot
know the driver information to get this..). There are also several
known flaws in the way DRM works (you cannot validate mode ids at the
level you need to - it is a "connector" task, but it needs to be a
crtc task too especially for IPU where bandwidth is defined by the
IDMAC FIFO settings and units in use) which might require more than a
rudimentary rework of parts of DRM (more like, a new API entirely..)

It's horrible, hideous even, and could require several years of
development for something which nobody had the foresight to see, even
though the configurations required have existed since the early 90's -
a SoC with parallel or serial display bus, with transmitters to the
panels or connectors connected over i2c for configuration and EDID
data gathering. DRM just doesn't really support it in a generic way.

>> The IPU has other units missing in this patch:
>>
>> - CMOS Sensor Interface (csi)
>> - Video Deinterlacer (vdi)
>> - Sensor Multi FIFO Controler (smfc)
>> - Image Converter (ic)
>> - Image Rotator (irt)
>>
>> So expect more files to come in this directory.
>
> Do you have a schedule for that? Are you waiting for more customer projects at
> Pengutronix to do that?

Both Pengutronix and Genesi have slightly differing implementations of
these (especially csi, ic) which might need to be merged together and
coordinated. I am not sure what the schedule for this is, Genesi's
customer doesn't in the final result need actual Linux support (it's
just a better case for proof of concept development and feature
comparison/development than FSL's BSP code which is a spaghetti
factory).

> That would be great to finally have full IPU/VPU/GPU support for i.MX5 into
> upstream. As you already know, Linaro also have some video support for i.MX5 in
> this head:
> http://git.linaro.org/gitweb?p=landing-teams/working/freescale/kernel.git;a=shortlog;h=refs/heads/lt-3.2-imx5
>
> Matt, I think you also have video support for efikamx, don't you?

Well, here is the problem;

IPU, VPU and GPU are basically completely seperate. They do not need
to depend on each other for anything, but the most EXCITING uses would
coordinate these three units together through some userspace API (DRM
for IPU-DI and GPU access, dma_buf for sharing, v4l2 mem2mem for VPU
and IPU processing tasks..) such that you could send H.264 for example
to decode, deinterlace, rotate and colour convert it in IPU then use
it as a GPU texture (if only because the GPU doesn't support some
common YUV formats without expensive shader) without copying anything
around and just signalling your intent to the kernel.

That kind of coordination is simply missing from pretty much
everyone's SoCs right now except perhaps Samsung's Exynos5.

VPU would be better serviced by improving the CODA driver someone
submitted a month ago. The CODA driver ported uses the same v4l2
mem2mem API as Samsung's MFC video codec, but that codec is a
different core than CODA. This is Chips&Media IP core, roughly
compatible with it's various versions and included in i.MX series for
a long time.. it is also shared by *older* Exynos (I think Exynos3)
designs and probably exists in some lower-end ARM processor cores too
from other manufacturers). It may by that legacy be in the original
iPhone :)

GPU couldn't even get into mainline when developed by Qualcomm (same
GPU for i.MX51 and i.MX53 as their "Adreno 200") - some significant
coordination between companies here is required. Qualcomm uses a
custom GPU access API called "GSL" which does somewhat of the same job
as DRM could/should, but it needs porting, then there is a significant
problem here after that in that the userspace is completely closed.
Genesi has access to most of the source (some parts are still binaries
even to us), some other companies do too, but the terms of the NDA are
extremely restrictive. I cannot recommend Freedreno because I am
technically not even allowed to look at it, but it might be your best
chance for opensource here.

> Is there a plan to merge all these developments into upstream?

At some point. I would love to do it, but there's so much to actually
do. It would benefit far more here than just Freescale chips, except
the IPU, which would benefit far more than just a single Freescale SoC
(i.MX51, 53, 6 and onwards would be supported) anyway due to a pretty
much 99% shared API implementation with a few subtle but almost
irrelevant differences.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From linux at arm.linux.org.uk  Fri Aug 24 14:21:33 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 19:21:33 +0100
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
Message-ID: <20120824182133.GB18957@n2100.arm.linux.org.uk>

On Fri, Aug 24, 2012 at 04:23:39PM +0800, Bill Huang wrote:
> When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC
> registers through I2C to perform the power off sequence. Unfortunately,
> sometimes we'll fail to shutdown due to I2C timeout on Tegra20. And the
> cause of the timeout is due to the CPU which I2C controller IRQ affined
> to will have chance to be offlined without migrating all irqs affined 
> to it, so the following I2C transactions will fail (no any CPU will
> handle that interrupt since then).

> Some snippet of the shutdown codes:
> 
> void kernel_power_off(void)
> {
> 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
> 	:
> 	disable_nonboot_cpus();
> 	:
> 	machine_power_off();
> }
> 
> void machine_power_off(void)
> {
> 	machine_shutdown();
> 	if (pm_power_off)
> 		pm_power_off(); /* this is where we send I2C write to shutdown */
> }
> 
> void machine_shutdown(void)
> {
> #ifdef CONFIG_SMP
> 	smp_send_stop();
> #endif
> }
> 
> In "smp_send_stop()", it will send "IPI_CPU_STOPS" to offline other cpus except
> current cpu (smp_processor_id()), however, current cpu will not always be cpu0 at
> least at Tegra20, that said for example cpu1 might be the current cpu and cpu0 will
> be offlined and this is the case why the I2C transaction will timeout. 
> 
> For normal case, "disable_nonboot_cpus()" call will disable all other Cpus except
> cpu0, that means we won't hit the problem mentioned here since cpu0 will always be
> the current cpu in the call "smp_send_stop", but the call to "disable_nonboot_cpus" 
> will happen only when "CONFIG_PM_SLEEP_SMP" is enabled which is not the case for
> Tegra20/Tegra30, we don't support suspend yet so this can't be enabled.

So what you're asking for is a feature to do what CONFIG_PM_SLEEP_SMP
does, but without CONFIG_PM_SLEEP_SMP enabled?

Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
requires that the lowest CPU number be the CPU dealing with reboot?


From linux at arm.linux.org.uk  Fri Aug 24 14:31:19 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 19:31:19 +0100
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <CAKGA1bkjJXK8bUxLxRYz_4Rj9YW0mJxBMyg7ir+Hfo+s6Lza0w@mail.gmail.com>
References: <1596192785.2810155.1345817566620.JavaMail.root@advansee.com>
 <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
 <CAKGA1bkjJXK8bUxLxRYz_4Rj9YW0mJxBMyg7ir+Hfo+s6Lza0w@mail.gmail.com>
Message-ID: <20120824183119.GD18957@n2100.arm.linux.org.uk>

On Fri, Aug 24, 2012 at 01:00:13PM -0500, Matt Sealey wrote:
> Nobody wants to write
> the same driver 5 times, and while the Silicon Image controllers are
> wonderfully generic with a common API ("TPI") and there could be a
> generic MFD solution with shim drivers on top for DRM, nobody else's
> are quite as nice.

I got here and immediately thought "oh god not more layers to DRM".
DRM does _not_ need any more bloody layers on top of the existing
layers.  It needs a library of helper functions to provide common
functionality so that folk don't have to write the same bloody stuff
time and time again.

A library of helpers, not a shim layer to convert it to something else.


From tony at atomide.com  Fri Aug 24 15:07:14 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:07:14 -0700
Subject: [PATCH v3 01/23] serial: omap: define and use to_uart_omap_port()
In-Reply-To: <1345717983-18179-2-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
 <1345717983-18179-2-git-send-email-balbi@ti.com>
Message-ID: <20120824190713.GP11011@atomide.com>

* Felipe Balbi <balbi at ti.com> [120823 03:37]:
> current code only works because struct uart_port
> is the first member on the uart_omap_port structure.
> 
> If, for whatever reason, someone puts another
> member as the first of the structure, that cast
> won't work anymore. In order to be safe, let's use
> a container_of() which, for now, gets optimized into
> a cast anyway.
> 
> Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> ---
>  arch/arm/plat-omap/include/plat/omap-serial.h |  2 ++
>  drivers/tty/serial/omap-serial.c              | 36 +++++++++++++--------------
>  2 files changed, 20 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
> index 1a52725..f3b35d9 100644
> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
> @@ -137,4 +137,6 @@ struct uart_omap_port {
>  	struct work_struct	qos_work;
>  };
>  
> +#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))
> +
>  #endif /* __OMAP_SERIAL_H__ */

For the arch/arm/*omap*/* parts:

Acked-by: Tony Lindgren <tony at atomide.com>

FYI, note that there are ARM SoC patches to move various header files to
live under include/linux/platform_data which may cause conflicts with these
changes.

Regards,

Tony


From tony at atomide.com  Fri Aug 24 15:07:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:07:33 -0700
Subject: [PATCH v3 03/23] serial: omap: don't access the platform_device
In-Reply-To: <1345717983-18179-4-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
 <1345717983-18179-4-git-send-email-balbi@ti.com>
Message-ID: <20120824190733.GQ11011@atomide.com>

* Felipe Balbi <balbi at ti.com> [120823 03:37]:
> The driver doesn't need to know about its platform_device.
> 
> Everything the driver needs can be done through the
> struct device pointer. In case we need to use the
> OMAP-specific PM function pointers, those can make
> sure to find the device's platform_device pointer
> so they can find the struct omap_device through
> pdev->archdata field.
> 
> Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Signed-off-by: Felipe Balbi <balbi at ti.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 24 15:08:19 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:08:19 -0700
Subject: [PATCH v3 20/23] serial: omap: fix software flow control
In-Reply-To: <1345717983-18179-21-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
 <1345717983-18179-21-git-send-email-balbi@ti.com>
Message-ID: <20120824190819.GR11011@atomide.com>

* Felipe Balbi <balbi at ti.com> [120823 03:38]:
> From: Vikram Pandita <vikram.pandita at ti.com>
> 
> Software flow control register bits were not defined correctly.
> 
> Also clarify the IXON and IXOFF logic to reflect what userspace wants.
> 
> Cc: stable at vger.kernel.org
> Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> Signed-off-by: Vikram Pandita <vikram.pandita at ti.com>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> Signed-off-by: Felipe Balbi <balbi at ti.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Aug 24 15:08:39 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:08:39 -0700
Subject: [PATCH v3 22/23] serial: omap: move uart_omap_port definition
 to C file
In-Reply-To: <1345717983-18179-23-git-send-email-balbi@ti.com>
References: <1345717983-18179-1-git-send-email-balbi@ti.com>
 <1345717983-18179-23-git-send-email-balbi@ti.com>
Message-ID: <20120824190839.GS11011@atomide.com>

* Felipe Balbi <balbi at ti.com> [120823 03:38]:
> nobody needs to access the uart_omap_port structure
> other than omap-serial.c file. Let's move that
> structure definition to the C source file in order
> to prevent anyone from accessing our structure.
> 
> Tested-by: Shubhrajyoti D <shubhrajyoti at ti.com>
> Signed-off-by: Felipe Balbi <balbi at ti.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From mturquette at ti.com  Fri Aug 24 15:12:34 2012
From: mturquette at ti.com (Mike Turquette)
Date: Fri, 24 Aug 2012 12:12:34 -0700
Subject: [PATCH v4 1/2] ARM: PRIMA2: convert to common clk and finish full
 clk tree
In-Reply-To: <CAGsJ_4xAoa_w9BYKvtFS7=TdgXY6QReb7ja9QUWn=njbEq98vg@mail.gmail.com>
References: <1345444957-16039-1-git-send-email-Barry.Song@csr.com>
 <CAGsJ_4xAoa_w9BYKvtFS7=TdgXY6QReb7ja9QUWn=njbEq98vg@mail.gmail.com>
Message-ID: <20120824191234.5710.5552@nucleus>

Quoting Barry Song (2012-08-21 02:44:02)
> Hi Mike,
> 
> can you pls merge these two patches as our discussion at:
> 
> http://comments.gmane.org/gmane.linux.ports.arm.kernel/178760
> 
> our following many patches depend on these two.
> 

Done!  Sorry about the long wait but I've been traveling for work and
got sidetracked.  I'm catching up on clk patches now and will push out
my clk-next branch towards 3.7 this evening.

Regards,
Mike

> -barry
> 
> 2012/8/20 Barry Song <Barry.Song at csr.com>:
> > From: Binghua Duan <Binghua.Duan at csr.com>
> >
> > Commit 02c981c07bc95ac1e only implements a little part of primaII clk tree
> > due to common clk framework was not ready at that time.
> > This patch converts the old driver to common clk and finish the full clk
> > tree.
> >
> > Signed-off-by: Binghua Duan <Binghua.Duan at csr.com>
> > Signed-off-by: Barry Song <Baohua.Song at csr.com>
> > ---
> >  -v4: fix a typo


From tony at atomide.com  Fri Aug 24 15:46:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:46:30 -0700
Subject: [PATCH v6 10/10] ARM: OMAP2+: tusb6010: generic timing calculation
In-Reply-To: <bc000ac53bb1b3ae1a951bbcf372caf6336d2a19.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <bc000ac53bb1b3ae1a951bbcf372caf6336d2a19.1345524670.git.afzal@ti.com>
Message-ID: <20120824194630.GU11011@atomide.com>

* Afzal Mohammed <afzal at ti.com> [120821 03:46]:
> Generic gpmc timing calculation helper is available now, use
> it instead of custom timing calculation.

This hangs n800 during the boot.

Tony


From robherring2 at gmail.com  Fri Aug 24 15:50:52 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 24 Aug 2012 14:50:52 -0500
Subject: [RFC PATCH] ARM: initial multiplatform support
Message-ID: <1345837852-10277-1-git-send-email-robherring2@gmail.com>

From: Arnd Bergmann <arnd at arndb.de>

This lets us build a multiplatform kernel for experimental purposes.
However, it will not be useful for any real work, because it relies
on a number of useful things to be disabled for now:

* SMP support is turned off because of conflicting symbols.
  Marc Zyngier has proposed a solution by adding a new SOC
  operations structure to hold indirect function pointers
  for these, but that work is currently stalled

* We turn on SPARSE_IRQ unconditionally, which is not supported
  on most platforms. Each of them is currently in a different
  state, but most are being worked on.

* A common clock framework is in place since v3.4 but not yet
  being used. Work on this is on its way.

* DEBUG_LL for early debugging is currently disabled.

* THUMB2_KERNEL does not work with allyesconfig because the
  kernel gets too big

[Rob Herring]: Rebased to not be dependent on the mass mach header rename.
As a result, omap2plus, imx, mxs and ux500 are not converted. Highbank,
socfpga, and vexpress are converted. There's probably a few others that can
be converted easily, too.

The kconfig and makefile changes have been simplified some. Instead of 3 kconfig
symbols per mach, there are only 2. arch/arm/Kconfig is getting kind of large.
I think it should be split between Kconfig and Kconfig.mach to separate out the
mach specific parts.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                              |  107 +++++++++++++++----------
 arch/arm/Makefile                             |   16 ++--
 arch/arm/mach-multi/Kconfig                   |   42 ++++++++++
 arch/arm/mach-multi/Makefile                  |    1 +
 arch/arm/mach-multi/include/mach/gpio.h       |    1 +
 arch/arm/mach-multi/include/mach/timex.h      |    3 +
 arch/arm/mach-multi/include/mach/uncompress.h |   10 +++
 arch/arm/mach-vexpress/Makefile               |    1 +
 arch/arm/plat-versatile/Makefile              |    2 +
 9 files changed, 136 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/mach-multi/Kconfig
 create mode 100644 arch/arm/mach-multi/Makefile
 create mode 100644 arch/arm/mach-multi/include/mach/gpio.h
 create mode 100644 arch/arm/mach-multi/include/mach/timex.h
 create mode 100644 arch/arm/mach-multi/include/mach/uncompress.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..e841262 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -255,22 +255,18 @@ choice
 	prompt "ARM system type"
 	default ARCH_VERSATILE
 
-config ARCH_SOCFPGA
-	bool "Altera SOCFPGA family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
+config ARCH_MULTIPLATFORM
+	bool "Allow multiple platforms to be selected"
+	select USE_OF
 	select COMMON_CLK
-	select CPU_V7
-	select DW_APB_TIMER
-	select DW_APB_TIMER_OF
-	select GENERIC_CLOCKEVENTS
-	select GPIO_PL061 if GPIOLIB
-	select HAVE_ARM_SCU
 	select SPARSE_IRQ
-	select USE_OF
+	select MULTI_IRQ_HANDLER
+	select AUTO_ZRELADDR
+	depends on MMU
+
+config ARCH_SOCFPGA_CHOICE
+	bool "Altera SOCFPGA family"
+	select ARCH_SOCFPGA
 	help
 	  This enables support for Altera SOCFPGA Cyclone V platform
 
@@ -327,21 +323,9 @@ config ARCH_VERSATILE
 	help
 	  This enables support for ARM Ltd Versatile board.
 
-config ARCH_VEXPRESS
+config ARCH_VEXPRESS_CHOICE
 	bool "ARM Ltd. Versatile Express family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select GENERIC_CLOCKEVENTS
-	select HAVE_CLK
-	select HAVE_PATA_PLATFORM
-	select ICST
-	select NO_IOPORT
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLCD
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select ARCH_VEXPRESS
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
 
@@ -368,21 +352,8 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
-config ARCH_HIGHBANK
+config ARCH_HIGHBANK_CHOICE
 	bool "Calxeda Highbank-based"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select ARM_TIMER_SP804
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select HAVE_ARM_SCU
-	select HAVE_SMP
-	select SPARSE_IRQ
-	select USE_OF
 	help
 	  Support for the Calxeda Highbank SoC based boards.
 
@@ -1028,6 +999,58 @@ config ARCH_ZYNQ
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
 
+source "arch/arm/mach-multi/Kconfig"
+
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
+
+config ARCH_VEXPRESS
+	bool "" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK
+	select HAVE_PATA_PLATFORM
+	select ICST
+	select NO_IOPORT
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLCD
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select MAY_HAVE_SPARSE_IRQ
+
+config ARCH_HIGHBANK
+	bool "Highbank" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_TIMER_SP804
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU
+	select HAVE_SMP
+	select SPARSE_IRQ
+	select USE_OF
+
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..c113e53 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -133,6 +133,9 @@ textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 
+# multiplatform directory must be first
+machine-$(CONFIG_ARCH_MULTIPLATFORM)	:= multi
+
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		:= at91
@@ -145,7 +148,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
 machine-$(CONFIG_ARCH_H720X)		:= h720x
-machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
+machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
@@ -186,11 +189,11 @@ machine-$(CONFIG_ARCH_TEGRA)		:= tegra
 machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)		:= ux500
 machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
-machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
+machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
 machine-$(CONFIG_ARCH_VT8500)		:= vt8500
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
-machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
+machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
 machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
 machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
 machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
@@ -230,14 +233,17 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
+ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+MACHINE  :=
+endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 
 ifeq ($(KBUILD_SRC),)
-KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
+KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(word 1,$(machdirs) $(platdirs)))
 else
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
+KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(word 1,$(machdirs) $(platdirs)))
 endif
 
 export	TEXT_OFFSET GZFLAGS MMUEXT
diff --git a/arch/arm/mach-multi/Kconfig b/arch/arm/mach-multi/Kconfig
new file mode 100644
index 0000000..0a6369f
--- /dev/null
+++ b/arch/arm/mach-multi/Kconfig
@@ -0,0 +1,42 @@
+menu "Multiple platform selection"
+	depends on ARCH_MULTIPLATFORM
+
+comment "CPU Core family selection"
+
+config ARCH_MULTI_V4
+	bool "ARMv4 based platforms (FA526, StrongARM)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4T
+	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V5
+	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4_V5
+	bool
+
+config ARCH_MULTI_V6
+	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V7
+	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+	default y
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V6_V7
+	bool
+
+config ARCH_MULTI_CPU_AUTO
+	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
+	select ARCH_MULTI_V5
+
+endmenu
+
+comment "SoC family selection"
diff --git a/arch/arm/mach-multi/Makefile b/arch/arm/mach-multi/Makefile
new file mode 100644
index 0000000..1bb8bf6
--- /dev/null
+++ b/arch/arm/mach-multi/Makefile
@@ -0,0 +1 @@
+# empty
diff --git a/arch/arm/mach-multi/include/mach/gpio.h b/arch/arm/mach-multi/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-multi/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-multi/include/mach/timex.h b/arch/arm/mach-multi/include/mach/timex.h
new file mode 100644
index 0000000..929b4c4
--- /dev/null
+++ b/arch/arm/mach-multi/include/mach/timex.h
@@ -0,0 +1,3 @@
+#ifndef CLOCK_TICK_RATE
+#define CLOCK_TICK_RATE 1000000
+#endif
diff --git a/arch/arm/mach-multi/include/mach/uncompress.h b/arch/arm/mach-multi/include/mach/uncompress.h
new file mode 100644
index 0000000..a4dec68
--- /dev/null
+++ b/arch/arm/mach-multi/include/mach/uncompress.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+/* no-op dummies for the uncompress debugging for multiplatform kernels */
+
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+
+#endif
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9..1666f6e 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,6 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-y := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 272769a8..15411b1 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,3 +1,5 @@
+ccflags-y := -I$(srctree)/$(src)/include
+
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
-- 
1.7.9.5



From tony at atomide.com  Fri Aug 24 15:54:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 12:54:47 -0700
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <50359C64.40603@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
 <50359C64.40603@ti.com>
Message-ID: <20120824195446.GV11011@atomide.com>

* Jon Hunter <jon-hunter at TI.COM> [120822 19:58]:
> 
> So although this may consolidate how the timings are calculated today, I
> am concerned it will be confusing to add timings for a new device. At
> least if I am calculating timings, I am taking the timing information
> for the device and translating that to the how I need to program the
> gpmc register fields.

Yes agreed. Also as some values make sense only in cycles, converting them
back and forth to time is wrong. So at least some values should have an
option to specify them in cycles directly, and then ignore any time based
values.

Regards,

Tony


From swarren at wwwdotorg.org  Fri Aug 24 16:01:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 24 Aug 2012 14:01:32 -0600
Subject: [RFC PATCH] ARM: initial multiplatform support
In-Reply-To: <1345837852-10277-1-git-send-email-robherring2@gmail.com>
References: <1345837852-10277-1-git-send-email-robherring2@gmail.com>
Message-ID: <5037DD9C.2090403@wwwdotorg.org>

On 08/24/2012 01:50 PM, Rob Herring wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> This lets us build a multiplatform kernel for experimental purposes.
> However, it will not be useful for any real work, because it relies
> on a number of useful things to be disabled for now:
...

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig

> +config ARCH_SOCFPGA_CHOICE
> +	bool "Altera SOCFPGA family"
> +	select ARCH_SOCFPGA

> -config ARCH_VEXPRESS
> +config ARCH_VEXPRESS_CHOICE
...
> +	select ARCH_VEXPRESS

> -config ARCH_HIGHBANK
> +config ARCH_HIGHBANK_CHOICE
...
>  	help

Doesn't that need "select ARCH_HIGHBANK" too?

I see Tegra doesn't work with SPARSE_IRQ:-( I'll have to look into
what's required to make that work...


From tony at atomide.com  Fri Aug 24 16:02:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:02:22 -0700
Subject: [PATCH] arm/dts: omap5: Add mmc controller nodes and board data
In-Reply-To: <201208070830.01776.arnd@arndb.de>
References: <1344323901-20342-1-git-send-email-balajitk@ti.com>
 <201208070830.01776.arnd@arndb.de>
Message-ID: <20120824200221.GW11011@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120807 02:21]:
> On Tuesday 07 August 2012, Balaji T K wrote:
> > 
> > Add OMAP MMC related device tree data for OMAP5.
> > 
> > Signed-off-by: Balaji T K <balajitk at ti.com>
> > ---
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Applying this into omap devel-dt branch. 

Tony


From tony at atomide.com  Fri Aug 24 16:07:36 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:07:36 -0700
Subject: [PATCH-V2] arm/dts: AM33XX: Set the default status of module
 to "disabled" state
In-Reply-To: <1345029805-27987-1-git-send-email-hvaibhav@ti.com>
References: <1345029805-27987-1-git-send-email-hvaibhav@ti.com>
Message-ID: <20120824200736.GX11011@atomide.com>

* Vaibhav Hiremath <hvaibhav at ti.com> [120815 04:24]:
> Ideally in common SoC dtsi file should set all modules
> to "disabled" state and it should get enabled in respective
> EVM/Board dts file as per usage.
> 
> This patch sets default status of all modules to "disabled"
> state in am33xx.dtsi file. Currently there are no modules
> supported as part of Bone and EVM dts support, so care
> to add entry "status = "okay"" while adding support for any
> module.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Tony Lindgren <tony at atomide.com>
> ---
> Changes from V1:
> 	- Fixed indentation issue caused due to extra spaces.

Thanks applying into devel-dt branch.

Tony


From tony at atomide.com  Fri Aug 24 16:14:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:14:47 -0700
Subject: [PATCH v3 3/4] arm/dts: AM33XX: Configure pinmuxs for D_CAN1
 on AM335x-EVM
In-Reply-To: <1345119610-5247-4-git-send-email-anilkumar@ti.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
 <1345119610-5247-4-git-send-email-anilkumar@ti.com>
Message-ID: <20120824201447.GY11011@atomide.com>

* AnilKumar Ch <anilkumar at ti.com> [120816 05:20]:
> Add D_CAN1 pinctrl node to am3358_pinmux master node to export
> D_CAN functionality on AM335x EVM according to pinctrl-single
> driver.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
> Changes from v2:
> 	- Incorporated Vaibhav H's comments on v2
> 	  * Added dcan0 instances to am33xx.dtsi file
> 
> Changes from v1:
> 	- These two patches separated from c_can DT support
> 	  patch series.
> 
>  arch/arm/boot/dts/am335x-evm.dts |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> index 5dd8a6b..a64c30a 100644
> --- a/arch/arm/boot/dts/am335x-evm.dts
> +++ b/arch/arm/boot/dts/am335x-evm.dts
> @@ -18,6 +18,18 @@
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
>  
> +	am3358_pinmux: pinmux at 44E10800 {

This should be just &am3358_pinmux as you already include it.

> +		pinctrl-names = "default";
> +		pinctrl-0 = <&d_can1_pins>;
> +
> +		d_can1_pins: pinmux_d_can_pins {
> +			pinctrl-single,pins = <
> +				0x168 0x2	/* uart0_ctsn.d_can1_tx, OUTPUT | MODE2 */
> +				0x16C 0x32	/* uart0_rtsn.d_can1_rx, INPUT_PULLUP | MODE2 */
> +			>;
> +		};
> +	};
> +

It would better to claim these pins in the dcan driver entry
rather than set them as pins enabled by the pinctrl driver.
The reason is that in case you want to enable runtime PM related
stuff, like some more advanced wake-up features, for the rx pin
you can do it in the driver.

Then one nit.. Please lowercase all hex number in this series as that's the style
here.

Regards,

Tony


From tony at atomide.com  Fri Aug 24 16:16:34 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:16:34 -0700
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <20120821180847.GC7995@opensource.wolfsonmicro.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
 <5033ADC5.4030002@wwwdotorg.org>
 <20120821163805.GW7995@opensource.wolfsonmicro.com>
 <5033CDDB.808@wwwdotorg.org>
 <20120821180847.GC7995@opensource.wolfsonmicro.com>
Message-ID: <20120824201634.GZ11011@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120821 11:09]:
> On Tue, Aug 21, 2012 at 12:05:15PM -0600, Stephen Warren wrote:
> > On 08/21/2012 10:38 AM, Mark Brown wrote:
> 
> > > This isn't the general view for the regualtor API - we generally
> > > want all regulators to be registered in order to allow us to see
> > > what's going on with things even if we've not figured them out from
> > > software.
> 
> > Oh, I said the above specifically because when I added the LDO
> > configuration for the regulators that weren't used to the Tegra .dts
> > files, you told me to remove it, based on the comment I put in there
> > that they weren't used on the board.
> 
> The board shouldn't have to define the regulators, the regulator driver
> really ought to be able to figure out that they're there by itself if
> there's no configuration based purely on knowing which chip is there.
> From that point of view it's OK for the chip .dtsi to have them (though
> ideally the driver wouldn't *need* that either) which was what was
> happening here.

So I assume no changes needed here then?

Regards,

Tony


From tony at atomide.com  Fri Aug 24 16:18:13 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:18:13 -0700
Subject: [PATCH] ARM: omap: add dtb targets
In-Reply-To: <1345740689-21676-1-git-send-email-olof@lixom.net>
References: <1345740689-21676-1-git-send-email-olof@lixom.net>
Message-ID: <20120824201813.GA11011@atomide.com>

* Olof Johansson <olof at lixom.net> [120823 09:52]:
> Makes it easier to just do 'make dtbs' for whatever the kernel was
> configured for, just like some other platforms.

Thanks applying into omap devel-dt branch.

Tony
 
> Signed-off-by: Olof Johansson <olof at lixom.net>
> ---
>  arch/arm/mach-omap2/Makefile.boot | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
> index b03e562..6cf1c2d 100644
> --- a/arch/arm/mach-omap2/Makefile.boot
> +++ b/arch/arm/mach-omap2/Makefile.boot
> @@ -1,3 +1,9 @@
>    zreladdr-y		+= 0x80008000
>  params_phys-y		:= 0x80000100
>  initrd_phys-y		:= 0x80800000
> +
> +dtb-$(CONFIG_SOC_OMAP2420)	+= omap2420-h4.dtb
> +dtb-$(CONFIG_ARCH_OMAP3)	+= omap3-beagle.dtb omap3-evm.dtb
> +dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-panda.dtb omap4-pandaES.dtb
> +dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-var_som.dtb omap4-sdp.dtb
> +dtb-$(CONFIG_SOC_OMAP5)		+= omap5-evm.dtb
> -- 
> 1.7.10.1.488.g05fbf7a
> 


From tony at atomide.com  Fri Aug 24 16:27:25 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:27:25 -0700
Subject: [PATCH 2/2] arm/dts: Cleanup regulator naming and remove @0,1..
In-Reply-To: <1343653940-16614-3-git-send-email-rnayak@ti.com>
References: <1343653940-16614-1-git-send-email-rnayak@ti.com>
 <1343653940-16614-3-git-send-email-rnayak@ti.com>
Message-ID: <20120824202725.GA1303@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120730 06:17]:
> regulators do not have a 'reg' property, hence the regulator at 0,
> regulator at 1 do not make sense. get rid of it.

Looks like this needs to be refreshed to apply. Care to
refresh against current devel-dt branch in case other
places need the same change?

Regards,

Tony


From linus.walleij at linaro.org  Fri Aug 24 16:28:40 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 24 Aug 2012 22:28:40 +0200
Subject: [PATCH] ARM: ux500: set proper GIC flags
In-Reply-To: <CAMQu2gx9kU4sPL5-TsJTq_2pUvm3Jm6rNWS=XYQJihTUpm1nHg@mail.gmail.com>
References: <1345813264-4896-1-git-send-email-linus.walleij@stericsson.com>
 <CAMQu2gx9kU4sPL5-TsJTq_2pUvm3Jm6rNWS=XYQJihTUpm1nHg@mail.gmail.com>
Message-ID: <CACRpkdZS1-XMR2JJsu77SHigb4PENo0UXFxp_i8pUrb6AWHqJw@mail.gmail.com>

On Fri, Aug 24, 2012 at 3:08 PM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
>> +       gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
>> +
> With this patch, you should no longer need the dummy set_irq_wake()
> patch which I was form
> you for ux500.

Yep, it's somehow gone already (though it was preserved on the
internal kernel...)

Yours,
Linus Walleij


From tony at atomide.com  Fri Aug 24 16:36:23 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 24 Aug 2012 13:36:23 -0700
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more
 mach-*/*.h includes
In-Reply-To: <201208231726.11293.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de>
 <201208231726.11293.arnd@arndb.de>
Message-ID: <20120824203622.GB1303@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120823 10:27]:
> On Thursday 23 August 2012, Arnd Bergmann wrote:
> > On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
> > > In any case, what we should be doing here as well is moving the headers
> > > included by drivers for platform data out of the arch/arm/mach/ subtrees
> > > and into include/linux/platform_data.  That will substantially reduce the
> > > amount of mach/ headers to deal with.
> > 
> > I've just looked at the {mach,plat}/*.h files that get included in ARM
> > specific drivers. Out of the 342 header files that get used in this way,
> > I found 93 that are practically just platform data, and a few that
> > are platform_data mixed with something else.
> > 
> > How about I move all the pure platform data definition files now and
> > rebase the other patches on top of that. Here is a list of suggested
> > file names in include/linux/platform_data/:
> 
> I've just scripted this and am running my build testsuite over it now.
> 
> Please let me know what you think about it.
> 
> 	Arnd
> 
> The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
> 
>   Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git 

I'd like to run some checks on this, but branch name missing here for
pulling a branch in for testing..
 
> for you to fetch changes up to 25296e032db173e8376123c2801cd233c9dc9b78:

..and -ENOSUCHCOMMIT after fetching in arm-soc tree.

Regards,

Tony


From linux at arm.linux.org.uk  Fri Aug 24 16:47:37 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 21:47:37 +0100
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more
 mach-*/*.h includes
In-Reply-To: <201208231726.11293.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de> <201208231726.11293.arnd@arndb.de>
Message-ID: <20120824204737.GE18957@n2100.arm.linux.org.uk>

On Thu, Aug 23, 2012 at 05:26:10PM +0000, Arnd Bergmann wrote:
> On Thursday 23 August 2012, Arnd Bergmann wrote:
> > On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
> > > In any case, what we should be doing here as well is moving the headers
> > > included by drivers for platform data out of the arch/arm/mach/ subtrees
> > > and into include/linux/platform_data.  That will substantially reduce the
> > > amount of mach/ headers to deal with.
> > 
> > I've just looked at the {mach,plat}/*.h files that get included in ARM
> > specific drivers. Out of the 342 header files that get used in this way,
> > I found 93 that are practically just platform data, and a few that
> > are platform_data mixed with something else.
> > 
> > How about I move all the pure platform data definition files now and
> > rebase the other patches on top of that. Here is a list of suggested
> > file names in include/linux/platform_data/:
> 
> I've just scripted this and am running my build testsuite over it now.
> 
> Please let me know what you think about it.

This certainly looks like a step in the right direction, thanks for doing
this.


From linux at arm.linux.org.uk  Fri Aug 24 16:52:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 24 Aug 2012 21:52:56 +0100
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more
 mach-*/*.h includes
In-Reply-To: <201208231135.11688.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de>
Message-ID: <20120824205256.GF18957@n2100.arm.linux.org.uk>

On Thu, Aug 23, 2012 at 11:35:11AM +0000, Arnd Bergmann wrote:
> About two third of the platform header files included in device drivers
> are not related to platform_data according to what I found. Most of them
> are also wrong (hardcoding interrupt numbers or addresses, headers
> included by accident but not actually used, driver specific definitions
> that don't belong in the platform, platform specific abstraction layers,
> ...), but they tend to be harder to clean up.
> 
> I hope we can get there eventually, but I think the intermediate step
> of enforcing a mach-${MACH}/foo.h is a step in the right direction on
> that way.

I think the opposite: if a platform wishes to be part of the multiplatform
kernel, it must clean up its header files first to become part of that,
otherwise it will not be configured into such a kernel.

Otherwise there's no incentive for platform maintainers to do anything
other than sit around waiting for someone else to do it for them.
There's also no incentive to avoid introducing new dependencies between
drivers and mach/ include files in the future either.

Yes, some platforms are going to need a lot more work than others to get
them ready (such as the Samsung suite) but that doesn't mean that we
should work around that, especially when the end-goal is to get rid of
these platform dependencies between drivers and mach includes.


From olof at lixom.net  Fri Aug 24 17:27:19 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 24 Aug 2012 14:27:19 -0700
Subject: [RFC PATCH] ARM: initial multiplatform support
In-Reply-To: <1345837852-10277-1-git-send-email-robherring2@gmail.com>
References: <1345837852-10277-1-git-send-email-robherring2@gmail.com>
Message-ID: <20120824212719.GA16828@quad.lixom.net>

Hi,

A few comments below.

On Fri, Aug 24, 2012 at 02:50:52PM -0500, Rob Herring wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> This lets us build a multiplatform kernel for experimental purposes.
> However, it will not be useful for any real work, because it relies
> on a number of useful things to be disabled for now:
> 
> * SMP support is turned off because of conflicting symbols.
>   Marc Zyngier has proposed a solution by adding a new SOC
>   operations structure to hold indirect function pointers
>   for these, but that work is currently stalled

On what? Review? or something else? It'd be nice to get some movement
going on it again. I guess we'll bring it up next week.

> * We turn on SPARSE_IRQ unconditionally, which is not supported
>   on most platforms. Each of them is currently in a different
>   state, but most are being worked on.
> 
> * A common clock framework is in place since v3.4 but not yet
>   being used. Work on this is on its way.
> 
> * DEBUG_LL for early debugging is currently disabled.

Being able to turn it on for one platform just to debug a boot issue is
still very useful. It's how powerpc handles it -- even if you can do a
multiplatform kernel, for the low level debug console you have to pick
one static entry.  Still useful during development.

> * THUMB2_KERNEL does not work with allyesconfig because the
>   kernel gets too big

Ironic, but understandable.

> ---
>  arch/arm/Kconfig                              |  107 +++++++++++++++----------
>  arch/arm/Makefile                             |   16 ++--
>  arch/arm/mach-multi/Kconfig                   |   42 ++++++++++
>  arch/arm/mach-multi/Makefile                  |    1 +
>  arch/arm/mach-multi/include/mach/gpio.h       |    1 +
>  arch/arm/mach-multi/include/mach/timex.h      |    3 +
>  arch/arm/mach-multi/include/mach/uncompress.h |   10 +++
>  arch/arm/mach-vexpress/Makefile               |    1 +
>  arch/arm/plat-versatile/Makefile              |    2 +
>  9 files changed, 136 insertions(+), 47 deletions(-)
>  create mode 100644 arch/arm/mach-multi/Kconfig
>  create mode 100644 arch/arm/mach-multi/Makefile
>  create mode 100644 arch/arm/mach-multi/include/mach/gpio.h
>  create mode 100644 arch/arm/mach-multi/include/mach/timex.h
>  create mode 100644 arch/arm/mach-multi/include/mach/uncompress.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e91c7cd..e841262 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -255,22 +255,18 @@ choice
>  	prompt "ARM system type"
>  	default ARCH_VERSATILE
>  
> -config ARCH_SOCFPGA
> -	bool "Altera SOCFPGA family"
> -	select ARCH_WANT_OPTIONAL_GPIOLIB
> -	select ARM_AMBA
> -	select ARM_GIC
> -	select CACHE_L2X0
> -	select CLKDEV_LOOKUP
> +config ARCH_MULTIPLATFORM
> +	bool "Allow multiple platforms to be selected"
> +	select USE_OF

Should this be a toplevel config option and the choice menu disabled if it's
set, instead of a meta-platform?

> @@ -1028,6 +999,58 @@ config ARCH_ZYNQ
>  	  Support for Xilinx Zynq ARM Cortex A9 Platform
>  endchoice
>  
> +source "arch/arm/mach-multi/Kconfig"
> +
> +config ARCH_SOCFPGA
> +	bool "Altera SOCFPGA family" if ARCH_MULTI_V7
> +	select ARCH_WANT_OPTIONAL_GPIOLIB
> +	select ARM_AMBA
> +	select ARM_GIC
> +	select CACHE_L2X0
> +	select CLKDEV_LOOKUP
> +	select COMMON_CLK
> +	select CPU_V7
> +	select DW_APB_TIMER
> +	select DW_APB_TIMER_OF
> +	select GENERIC_CLOCKEVENTS
> +	select GPIO_PL061 if GPIOLIB
> +	select HAVE_ARM_SCU
> +	select SPARSE_IRQ
> +	select USE_OF

There's no need to keep these in the common arm/Kconfig now, is there? Might as
well push them out to the respective mach-*/Kconfig, that will cause less churn
on the common file and in general scale better.

> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 30eae87..c113e53 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -133,6 +133,9 @@ textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
>  textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
>  textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
>  
> +# multiplatform directory must be first
> +machine-$(CONFIG_ARCH_MULTIPLATFORM)	:= multi
> +
>  # Machine directory name.  This list is sorted alphanumerically
>  # by CONFIG_* macro name.
>  machine-$(CONFIG_ARCH_AT91)		:= at91
> @@ -145,7 +148,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
>  machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
>  machine-$(CONFIG_ARCH_GEMINI)		:= gemini
>  machine-$(CONFIG_ARCH_H720X)		:= h720x
> -machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
> +machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
>  machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
>  machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
>  machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
> @@ -186,11 +189,11 @@ machine-$(CONFIG_ARCH_TEGRA)		:= tegra
>  machine-$(CONFIG_ARCH_U300)		:= u300
>  machine-$(CONFIG_ARCH_U8500)		:= ux500
>  machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
> -machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
> +machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
>  machine-$(CONFIG_ARCH_VT8500)		:= vt8500
>  machine-$(CONFIG_ARCH_W90X900)		:= w90x900
>  machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
> -machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
> +machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
>  machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
>  machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
>  machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
> @@ -230,14 +233,17 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
>  else
>  MACHINE  :=
>  endif
> +ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
> +MACHINE  :=
> +endif
>  
>  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>  platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
>  
>  ifeq ($(KBUILD_SRC),)
> -KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
> +KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(word 1,$(machdirs) $(platdirs)))
>  else
> -KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
> +KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(word 1,$(machdirs) $(platdirs)))
>  endif

Since the only purpose of mach-multi is to provide a few dummy header files,
how about adding those under arch/arm/include/ instead and do away with the
mach directory? They could then be prepended in front of these so the search
path would be in the right order.

> diff --git a/arch/arm/mach-multi/Kconfig b/arch/arm/mach-multi/Kconfig
> new file mode 100644
> index 0000000..0a6369f
> --- /dev/null
> +++ b/arch/arm/mach-multi/Kconfig
> @@ -0,0 +1,42 @@
> +menu "Multiple platform selection"
> +	depends on ARCH_MULTIPLATFORM
> +
> +comment "CPU Core family selection"
> +
> +config ARCH_MULTI_V4
> +	bool "ARMv4 based platforms (FA526, StrongARM)"
> +	select ARCH_MULTI_V4_V5
> +	depends on !ARCH_MULTI_V6_V7
> +
> +config ARCH_MULTI_V4T
> +	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
> +	select ARCH_MULTI_V4_V5
> +	depends on !ARCH_MULTI_V6_V7
> +
> +config ARCH_MULTI_V5
> +	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
> +	select ARCH_MULTI_V4_V5
> +	depends on !ARCH_MULTI_V6_V7
> +
> +config ARCH_MULTI_V4_V5
> +	bool
> +
> +config ARCH_MULTI_V6
> +	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
> +	select ARCH_MULTI_V6_V7

Does it make sense to add these before any platforms are ready? I'd argue no,
but I don't feel strongly about it.

> +config ARCH_MULTI_V7
> +	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
> +	default y
> +	select ARCH_MULTI_V6_V7
> +
> +config ARCH_MULTI_V6_V7
> +	bool
> +
> +config ARCH_MULTI_CPU_AUTO
> +	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
> +	select ARCH_MULTI_V5
> +
> +endmenu
> +
> +comment "SoC family selection"
> diff --git a/arch/arm/mach-multi/Makefile b/arch/arm/mach-multi/Makefile
> new file mode 100644
> index 0000000..1bb8bf6
> --- /dev/null
> +++ b/arch/arm/mach-multi/Makefile
> @@ -0,0 +1 @@
> +# empty
> diff --git a/arch/arm/mach-multi/include/mach/gpio.h b/arch/arm/mach-multi/include/mach/gpio.h
> new file mode 100644
> index 0000000..40a8c17
> --- /dev/null
> +++ b/arch/arm/mach-multi/include/mach/gpio.h
> @@ -0,0 +1 @@
> +/* empty */
> diff --git a/arch/arm/mach-multi/include/mach/timex.h b/arch/arm/mach-multi/include/mach/timex.h
> new file mode 100644
> index 0000000..929b4c4
> --- /dev/null
> +++ b/arch/arm/mach-multi/include/mach/timex.h
> @@ -0,0 +1,3 @@
> +#ifndef CLOCK_TICK_RATE
> +#define CLOCK_TICK_RATE 1000000
> +#endif
> diff --git a/arch/arm/mach-multi/include/mach/uncompress.h b/arch/arm/mach-multi/include/mach/uncompress.h
> new file mode 100644
> index 0000000..a4dec68
> --- /dev/null
> +++ b/arch/arm/mach-multi/include/mach/uncompress.h
> @@ -0,0 +1,10 @@
> +#ifndef __MACH_UNCOMPRESS_H
> +#define __MACH_UNCOMPRESS_H
> +
> +/* no-op dummies for the uncompress debugging for multiplatform kernels */
> +
> +static inline void putc(int c) {}
> +static inline void flush(void) {}
> +static inline void arch_decomp_setup(void) {}
> +
> +#endif
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 90551b9..1666f6e 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -1,6 +1,7 @@
>  #
>  # Makefile for the linux kernel.
>  #
> +ccflags-y := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-versatile/include

cc-flags-$(CONFIG_ARCH_MULTIPLATFORM) here and for versatile?


-Olof


From robherring2 at gmail.com  Fri Aug 24 17:50:42 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 24 Aug 2012 16:50:42 -0500
Subject: [RFC PATCH] ARM: initial multiplatform support
In-Reply-To: <20120824212719.GA16828@quad.lixom.net>
References: <1345837852-10277-1-git-send-email-robherring2@gmail.com>
 <20120824212719.GA16828@quad.lixom.net>
Message-ID: <5037F732.7070900@gmail.com>

On 08/24/2012 04:27 PM, Olof Johansson wrote:
> Hi,
> 
> A few comments below.
> 
> On Fri, Aug 24, 2012 at 02:50:52PM -0500, Rob Herring wrote:
>> From: Arnd Bergmann <arnd at arndb.de>
>>
>> This lets us build a multiplatform kernel for experimental purposes.
>> However, it will not be useful for any real work, because it relies
>> on a number of useful things to be disabled for now:
>>
>> * SMP support is turned off because of conflicting symbols.
>>   Marc Zyngier has proposed a solution by adding a new SOC
>>   operations structure to hold indirect function pointers
>>   for these, but that work is currently stalled
> 
> On what? Review? or something else? It'd be nice to get some movement
> going on it again. I guess we'll bring it up next week.

It tends to get sent out again during/after every conference. Marc would
be best to comment on the status.

>> * We turn on SPARSE_IRQ unconditionally, which is not supported
>>   on most platforms. Each of them is currently in a different
>>   state, but most are being worked on.
>>
>> * A common clock framework is in place since v3.4 but not yet
>>   being used. Work on this is on its way.
>>
>> * DEBUG_LL for early debugging is currently disabled.
> 
> Being able to turn it on for one platform just to debug a boot issue is
> still very useful. It's how powerpc handles it -- even if you can do a
> multiplatform kernel, for the low level debug console you have to pick
> one static entry.  Still useful during development.

This comment is misleading. It is possible to select it, but then you
just can only use that 1 platform.

>> * THUMB2_KERNEL does not work with allyesconfig because the
>>   kernel gets too big
> 
> Ironic, but understandable.
> 
>> ---
>>  arch/arm/Kconfig                              |  107 +++++++++++++++----------
>>  arch/arm/Makefile                             |   16 ++--
>>  arch/arm/mach-multi/Kconfig                   |   42 ++++++++++
>>  arch/arm/mach-multi/Makefile                  |    1 +
>>  arch/arm/mach-multi/include/mach/gpio.h       |    1 +
>>  arch/arm/mach-multi/include/mach/timex.h      |    3 +
>>  arch/arm/mach-multi/include/mach/uncompress.h |   10 +++
>>  arch/arm/mach-vexpress/Makefile               |    1 +
>>  arch/arm/plat-versatile/Makefile              |    2 +
>>  9 files changed, 136 insertions(+), 47 deletions(-)
>>  create mode 100644 arch/arm/mach-multi/Kconfig
>>  create mode 100644 arch/arm/mach-multi/Makefile
>>  create mode 100644 arch/arm/mach-multi/include/mach/gpio.h
>>  create mode 100644 arch/arm/mach-multi/include/mach/timex.h
>>  create mode 100644 arch/arm/mach-multi/include/mach/uncompress.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index e91c7cd..e841262 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -255,22 +255,18 @@ choice
>>  	prompt "ARM system type"
>>  	default ARCH_VERSATILE
>>  
>> -config ARCH_SOCFPGA
>> -	bool "Altera SOCFPGA family"
>> -	select ARCH_WANT_OPTIONAL_GPIOLIB
>> -	select ARM_AMBA
>> -	select ARM_GIC
>> -	select CACHE_L2X0
>> -	select CLKDEV_LOOKUP
>> +config ARCH_MULTIPLATFORM
>> +	bool "Allow multiple platforms to be selected"
>> +	select USE_OF
> 
> Should this be a toplevel config option and the choice menu disabled if it's
> set, instead of a meta-platform?

If we get rid of mach-multi, yes.

>> @@ -1028,6 +999,58 @@ config ARCH_ZYNQ
>>  	  Support for Xilinx Zynq ARM Cortex A9 Platform
>>  endchoice
>>  
>> +source "arch/arm/mach-multi/Kconfig"
>> +
>> +config ARCH_SOCFPGA
>> +	bool "Altera SOCFPGA family" if ARCH_MULTI_V7
>> +	select ARCH_WANT_OPTIONAL_GPIOLIB
>> +	select ARM_AMBA
>> +	select ARM_GIC
>> +	select CACHE_L2X0
>> +	select CLKDEV_LOOKUP
>> +	select COMMON_CLK
>> +	select CPU_V7
>> +	select DW_APB_TIMER
>> +	select DW_APB_TIMER_OF
>> +	select GENERIC_CLOCKEVENTS
>> +	select GPIO_PL061 if GPIOLIB
>> +	select HAVE_ARM_SCU
>> +	select SPARSE_IRQ
>> +	select USE_OF
> 
> There's no need to keep these in the common arm/Kconfig now, is there? Might as
> well push them out to the respective mach-*/Kconfig, that will cause less churn
> on the common file and in general scale better.

Good point. That's better than creating a Kconfig.mach. This can
probably be done for all platforms independent of multi-platform support.

>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
>> index 30eae87..c113e53 100644
>> --- a/arch/arm/Makefile
>> +++ b/arch/arm/Makefile
>> @@ -133,6 +133,9 @@ textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
>>  textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
>>  textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
>>  
>> +# multiplatform directory must be first
>> +machine-$(CONFIG_ARCH_MULTIPLATFORM)	:= multi
>> +
>>  # Machine directory name.  This list is sorted alphanumerically
>>  # by CONFIG_* macro name.
>>  machine-$(CONFIG_ARCH_AT91)		:= at91
>> @@ -145,7 +148,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
>>  machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
>>  machine-$(CONFIG_ARCH_GEMINI)		:= gemini
>>  machine-$(CONFIG_ARCH_H720X)		:= h720x
>> -machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
>> +machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
>>  machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
>>  machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
>>  machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
>> @@ -186,11 +189,11 @@ machine-$(CONFIG_ARCH_TEGRA)		:= tegra
>>  machine-$(CONFIG_ARCH_U300)		:= u300
>>  machine-$(CONFIG_ARCH_U8500)		:= ux500
>>  machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
>> -machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
>> +machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
>>  machine-$(CONFIG_ARCH_VT8500)		:= vt8500
>>  machine-$(CONFIG_ARCH_W90X900)		:= w90x900
>>  machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
>> -machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
>> +machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
>>  machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
>>  machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
>>  machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
>> @@ -230,14 +233,17 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
>>  else
>>  MACHINE  :=
>>  endif
>> +ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
>> +MACHINE  :=
>> +endif
>>  
>>  machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>>  platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
>>  
>>  ifeq ($(KBUILD_SRC),)
>> -KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
>> +KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(word 1,$(machdirs) $(platdirs)))
>>  else
>> -KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
>> +KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(word 1,$(machdirs) $(platdirs)))
>>  endif
> 
> Since the only purpose of mach-multi is to provide a few dummy header files,
> how about adding those under arch/arm/include/ instead and do away with the
> mach directory? They could then be prepended in front of these so the search
> path would be in the right order.

Yes, good idea.

>> diff --git a/arch/arm/mach-multi/Kconfig b/arch/arm/mach-multi/Kconfig
>> new file mode 100644
>> index 0000000..0a6369f
>> --- /dev/null
>> +++ b/arch/arm/mach-multi/Kconfig
>> @@ -0,0 +1,42 @@
>> +menu "Multiple platform selection"
>> +	depends on ARCH_MULTIPLATFORM
>> +
>> +comment "CPU Core family selection"
>> +
>> +config ARCH_MULTI_V4
>> +	bool "ARMv4 based platforms (FA526, StrongARM)"
>> +	select ARCH_MULTI_V4_V5
>> +	depends on !ARCH_MULTI_V6_V7
>> +
>> +config ARCH_MULTI_V4T
>> +	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
>> +	select ARCH_MULTI_V4_V5
>> +	depends on !ARCH_MULTI_V6_V7
>> +
>> +config ARCH_MULTI_V5
>> +	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
>> +	select ARCH_MULTI_V4_V5
>> +	depends on !ARCH_MULTI_V6_V7
>> +
>> +config ARCH_MULTI_V4_V5
>> +	bool
>> +
>> +config ARCH_MULTI_V6
>> +	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
>> +	select ARCH_MULTI_V6_V7
> 
> Does it make sense to add these before any platforms are ready? I'd argue no,
> but I don't feel strongly about it.

I'll defer that to Arnd. I'm not sure where he was going with the AUTO
selection stuff.

>> +config ARCH_MULTI_V7
>> +	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
>> +	default y
>> +	select ARCH_MULTI_V6_V7
>> +
>> +config ARCH_MULTI_V6_V7
>> +	bool
>> +
>> +config ARCH_MULTI_CPU_AUTO
>> +	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
>> +	select ARCH_MULTI_V5
>> +
>> +endmenu
>> +
>> +comment "SoC family selection"
>> diff --git a/arch/arm/mach-multi/Makefile b/arch/arm/mach-multi/Makefile
>> new file mode 100644
>> index 0000000..1bb8bf6
>> --- /dev/null
>> +++ b/arch/arm/mach-multi/Makefile
>> @@ -0,0 +1 @@
>> +# empty
>> diff --git a/arch/arm/mach-multi/include/mach/gpio.h b/arch/arm/mach-multi/include/mach/gpio.h
>> new file mode 100644
>> index 0000000..40a8c17
>> --- /dev/null
>> +++ b/arch/arm/mach-multi/include/mach/gpio.h
>> @@ -0,0 +1 @@
>> +/* empty */
>> diff --git a/arch/arm/mach-multi/include/mach/timex.h b/arch/arm/mach-multi/include/mach/timex.h
>> new file mode 100644
>> index 0000000..929b4c4
>> --- /dev/null
>> +++ b/arch/arm/mach-multi/include/mach/timex.h
>> @@ -0,0 +1,3 @@
>> +#ifndef CLOCK_TICK_RATE
>> +#define CLOCK_TICK_RATE 1000000
>> +#endif
>> diff --git a/arch/arm/mach-multi/include/mach/uncompress.h b/arch/arm/mach-multi/include/mach/uncompress.h
>> new file mode 100644
>> index 0000000..a4dec68
>> --- /dev/null
>> +++ b/arch/arm/mach-multi/include/mach/uncompress.h
>> @@ -0,0 +1,10 @@
>> +#ifndef __MACH_UNCOMPRESS_H
>> +#define __MACH_UNCOMPRESS_H
>> +
>> +/* no-op dummies for the uncompress debugging for multiplatform kernels */
>> +
>> +static inline void putc(int c) {}
>> +static inline void flush(void) {}
>> +static inline void arch_decomp_setup(void) {}
>> +
>> +#endif
>> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
>> index 90551b9..1666f6e 100644
>> --- a/arch/arm/mach-vexpress/Makefile
>> +++ b/arch/arm/mach-vexpress/Makefile
>> @@ -1,6 +1,7 @@
>>  #
>>  # Makefile for the linux kernel.
>>  #
>> +ccflags-y := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-versatile/include
> 
> cc-flags-$(CONFIG_ARCH_MULTIPLATFORM) here and for versatile?

Yes. I'd really like to find a way to do this in arch/arm/Makefile instead.

Rob


From mturquette at ti.com  Fri Aug 24 19:51:39 2012
From: mturquette at ti.com (Mike Turquette)
Date: Fri, 24 Aug 2012 16:51:39 -0700
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <CACRpkdZF-J_P9M2hOZhnJtNrUE_2exefUg1Tj7S_dj0jUPBuKA@mail.gmail.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <CACRpkdaDi8KMk0tyWuEHGnLWhZ4ufnNY4cUm-+q9kKryBztzkw@mail.gmail.com>
 <CACRpkdZF-J_P9M2hOZhnJtNrUE_2exefUg1Tj7S_dj0jUPBuKA@mail.gmail.com>
Message-ID: <20120824235139.18366.17586@nucleus>

Quoting Linus Walleij (2012-08-22 05:09:30)
> On Thu, Aug 16, 2012 at 2:56 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> > On Mon, Aug 6, 2012 at 6:32 PM, Linus Walleij
> > <linus.walleij at stericsson.com> wrote:
> >
> >> This converts the ARM RealView machine over to using the common
> >> clock. The approach is similar to the one used for the Integrator,
> >> and we're reusing the ICST wrapper code.
> >
> > Mike have you had time to look at this? I got Pawel's ACK in the thread.
> 
> Ping again on this, if it's OK it would be great to get some rotation in
> -next for this patch.
> 

Hi Linus,

Apologies for the delayed response.  I've been AWOL on clk patches since
the 3.5 release.

I've taken this into clk-next which will be published (based on 3.6-rc3)
this evening.

Regards,
Mike

> Yours,
> Linus Walleij


From marex at denx.de  Fri Aug 24 19:51:37 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 25 Aug 2012 01:51:37 +0200
Subject: [PATCH 1/4 V2] ARM: mx28: Add SPI 2 pinmux into imx28.dtsi
Message-ID: <1345852300-2213-1-git-send-email-marex@denx.de>

Add this SSP port 2 pin multiplexing configuration into the imx28.dtsi file.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28.dtsi |   13 +++++++++++++
 1 file changed, 13 insertions(+)

V2: Add only SSP2 pinmux.

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 91b43e9..b996c2d 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -507,6 +507,19 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <0>;
 				};
+
+				spi2_pins_a: spi2 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+						0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+						0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+						0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
 			};
 
 			digctl at 8001c000 {
-- 
1.7.10.4



From marex at denx.de  Fri Aug 24 19:51:38 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 25 Aug 2012 01:51:38 +0200
Subject: [PATCH 2/4 V2] ARM: mx28: Add USB PHY overcurrent pinmux
In-Reply-To: <1345852300-2213-1-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
Message-ID: <1345852300-2213-2-git-send-email-marex@denx.de>

Add the pinmux settings for USB PHY overcurrent pins.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chris Ball <cjb at laptop.org>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28.dtsi |   30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

V2: This is pulled from the M28EVK and SPS1 board files, put it into common
    file.

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index b996c2d..3cba62d 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -520,6 +520,36 @@
 					fsl,voltage = <1>;
 					fsl,pull-up = <1>;
 				};
+
+				usbphy0_pins_a: usbphy0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+					>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				usbphy0_pins_b: usbphy0 at 1 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+					>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				usbphy1_pins_a: usbphy1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+					>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
 			};
 
 			digctl at 8001c000 {
-- 
1.7.10.4



From marex at denx.de  Fri Aug 24 19:51:39 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 25 Aug 2012 01:51:39 +0200
Subject: [PATCH 3/4 V2] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <1345852300-2213-1-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
Message-ID: <1345852300-2213-3-git-send-email-marex@denx.de>

Update the mach-mxs machine by removing the enet_clkout(). The new
revision of the board doesn't need that. Also, update the DTS file
with all the new drivers pulled in the mainline recently, that is,
SPI, LRADC, USB.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28-m28evk.dts |   81 +++++++++++++++++++++++++++++++++---
 arch/arm/mach-mxs/mach-mxs.c       |    1 -
 2 files changed, 75 insertions(+), 7 deletions(-)

Move the usbphy overcurrent definition to include file.

diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd..229d26c 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
 	apb at 80000000 {
 		apbh at 80000000 {
 			gpmi-nand at 8000c000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
 				status = "okay";
@@ -62,9 +64,27 @@
 					     &mmc0_sck_cfg>;
 				bus-width = <8>;
 				wp-gpios = <&gpio3 10 1>;
+				vmmc-supply = <&reg_vddio_sd0>;
 				status = "okay";
 			};
 
+			ssp2: ssp at 80014000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi2_pins_a>;
+				status = "okay";
+
+				flash: m25p80 at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "m25p80";
+					spi-max-frequency = <40000000>;
+					reg = <0>;
+				};
+			};
+
 			pinctrl at 80018000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
@@ -72,8 +92,11 @@
 				hog_pins_a: hog-gpios at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
+						0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
 						0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
 						0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+						0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+						0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
 					>;
 					fsl,drive-strength = <0>;
 					fsl,voltage = <1>;
@@ -129,6 +152,7 @@
 			i2c0: i2c at 80058000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2c0_pins_a>;
+				clock-frequency = <400000>;
 				status = "okay";
 
 				sgtl5000: codec at 0a {
@@ -151,32 +175,51 @@
 				};
 			};
 
+			lradc at 80050000 {
+				status = "okay";
+			};
+
 			duart: serial at 80074000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&duart_pins_a>;
 				status = "okay";
 			};
 
-			auart0: serial at 8006a000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&auart0_2pins_a>;
+			usbphy0: usbphy at 8007c000 {
 				status = "okay";
 			};
 
-			auart3: serial at 80070000 {
+			usbphy1: usbphy at 8007e000 {
+				status = "okay";
+			};
+
+			auart0: serial at 8006a000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&auart3_pins_a>;
+				pinctrl-0 = <&auart0_2pins_a>;
 				status = "okay";
 			};
 		};
 	};
 
 	ahb at 80080000 {
+		usb0: usb at 80080000 {
+			vbus-supply = <&reg_usb0_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usbphy0_pins_a>;
+			status = "okay";
+		};
+
+		usb1: usb at 80090000 {
+			vbus-supply = <&reg_usb1_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usbphy1_pins_a>;
+			status = "okay";
+		};
+
 		mac0: ethernet at 800f0000 {
 			phy-mode = "rmii";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mac0_pins_a>;
-			phy-reset-gpios = <&gpio3 11 0>;
 			status = "okay";
 		};
 
@@ -198,6 +241,32 @@
 			regulator-max-microvolt = <3300000>;
 			regulator-always-on;
 		};
+
+		reg_vddio_sd0: vddio-sd0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vddio-sd0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 28 0>;
+		};
+
+		reg_usb0_vbus: usb0_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 12 0>;
+			enable-active-low;
+		};
+
+		reg_usb1_vbus: usb1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 13 0>;
+			enable-active-low;
+		};
 	};
 
 	sound {
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe8..5ac45a1 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -241,7 +241,6 @@ static void __init imx28_evk_init(void)
 
 static void __init m28evk_init(void)
 {
-	enable_clk_enet_out();
 	update_fec_mac_prop(OUI_DENX);
 
 	mxsfb_pdata.mode_list = m28evk_video_modes;
-- 
1.7.10.4



From marex at denx.de  Fri Aug 24 19:51:40 2012
From: marex at denx.de (Marek Vasut)
Date: Sat, 25 Aug 2012 01:51:40 +0200
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <1345852300-2213-1-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
Message-ID: <1345852300-2213-4-git-send-email-marex@denx.de>

Add DTS file for this custom board.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28-sps1.dts |  168 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mxs/mach-mxs.c     |    3 +
 2 files changed, 171 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx28-sps1.dts

diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
new file mode 100644
index 0000000..d05b1cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "SchulerControl GmbH, SC SPS 1";
+	compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	apb at 80000000 {
+		apbh at 80000000 {
+			pinctrl at 80018000 {
+				led_pins_sps1: leds at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
+						0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
+						0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
+					>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+			};
+
+			ssp0: ssp at 80010000 {
+				compatible = "fsl,imx28-mmc";
+				pinctrl-names = "default";
+				pinctrl-0 = <&mmc0_4bit_pins_a>;
+				bus-width = <4>;
+				status = "okay";
+			};
+
+			ssp2: ssp at 80014000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi2_pins_a>;
+				status = "okay";
+
+				flash: m25p80 at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "everspin,mr25h256", "mr25h256";
+					spi-max-frequency = <40000000>;
+					reg = <0>;
+				};
+			};
+		};
+
+		apbx at 80040000 {
+			i2c0: i2c at 80058000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins_a>;
+				clock-frequency = <400000>;
+				status = "okay";
+
+				rtc: rtc at 51 {
+					compatible = "nxp,pcf8563";
+					reg = <0x51>;
+				};
+
+				eeprom: eeprom at 52 {
+					compatible = "atmel,24c64";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+			};
+
+			duart: serial at 80074000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&duart_pins_a>;
+				status = "okay";
+			};
+
+			usbphy0: usbphy at 8007c000 {
+				status = "okay";
+			};
+
+			auart0: serial at 8006a000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&auart0_pins_a>;
+				status = "okay";
+			};
+
+			rtc at 80056000 {
+				status = "okay";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		usb0: usb at 80080000 {
+			vbus-supply = <&reg_usb0_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usbphy0_pins_b>;
+			status = "okay";
+		};
+
+		mac0: ethernet at 800f0000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac0_pins_a>;
+			status = "okay";
+		};
+
+		mac1: ethernet at 800f4000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac1_pins_a>;
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_usb0_vbus: usb0_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 9 0>;
+			enable-active-low;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_sps1>;
+		status = "okay";
+
+		led at 1 {
+			label = "sps1-1:yellow:user";
+			gpios = <&gpio0 6 0>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led at 2 {
+			label = "sps1-2:red:user";
+			gpios = <&gpio0 3 0>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led at 3 {
+			label = "sps1-3:red:user";
+			gpios = <&gpio0 0 0>;
+			default-trigger = "heartbeat";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5ac45a1..f131ff1 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -279,6 +279,8 @@ static void __init mxs_machine_init(void)
 		m28evk_init();
 	else if (of_machine_is_compatible("bluegiga,apx4devkit"))
 		apx4devkit_init();
+	else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
+		imx28_evk_init();
 
 	of_platform_populate(NULL, of_default_bus_match_table,
 			     mxs_auxdata_lookup, NULL);
@@ -298,6 +300,7 @@ static const char *imx28_dt_compat[] __initdata = {
 	"denx,m28evk",
 	"fsl,imx28-evk",
 	"karo,tx28",
+	"schulercontrol,imx28-sps1",
 	"fsl,imx28",
 	NULL,
 };
-- 
1.7.10.4



From bilhuang at nvidia.com  Fri Aug 24 20:00:56 2012
From: bilhuang at nvidia.com (Bill Huang)
Date: Sat, 25 Aug 2012 08:00:56 +0800
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <20120824182133.GB18957@n2100.arm.linux.org.uk>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
Message-ID: <A7051F87A141B744BCAF487D48E5B3BDF5BA98284A@HKMAIL02.nvidia.com>

nvpublic
> On Fri, Aug 24, 2012 at 04:23:39PM +0800, Bill Huang wrote:
> > When doing shutdown on Tegra20/Tegra30, we need to read/write PMIC
> > registers through I2C to perform the power off sequence.
> > Unfortunately, sometimes we'll fail to shutdown due to I2C timeout on
> > Tegra20. And the cause of the timeout is due to the CPU which I2C
> > controller IRQ affined to will have chance to be offlined without
> > migrating all irqs affined to it, so the following I2C transactions
> > will fail (no any CPU will handle that interrupt since then).
> 
> > Some snippet of the shutdown codes:
> >
> > void kernel_power_off(void)
> > {
> > 	kernel_shutdown_prepare(SYSTEM_POWER_OFF);
> > 	:
> > 	disable_nonboot_cpus();
> > 	:
> > 	machine_power_off();
> > }
> >
> > void machine_power_off(void)
> > {
> > 	machine_shutdown();
> > 	if (pm_power_off)
> > 		pm_power_off(); /* this is where we send I2C write to shutdown */ }
> >
> > void machine_shutdown(void)
> > {
> > #ifdef CONFIG_SMP
> > 	smp_send_stop();
> > #endif
> > }
> >
> > In "smp_send_stop()", it will send "IPI_CPU_STOPS" to offline other
> > cpus except current cpu (smp_processor_id()), however, current cpu
> > will not always be cpu0 at least at Tegra20, that said for example
> > cpu1 might be the current cpu and cpu0 will be offlined and this is the case why the I2C transaction
> will timeout.
> >
> > For normal case, "disable_nonboot_cpus()" call will disable all other
> > Cpus except cpu0, that means we won't hit the problem mentioned here
> > since cpu0 will always be the current cpu in the call "smp_send_stop", but the call to
> "disable_nonboot_cpus"
> > will happen only when "CONFIG_PM_SLEEP_SMP" is enabled which is not
> > the case for Tegra20/Tegra30, we don't support suspend yet so this can't be enabled.
> 
> So what you're asking for is a feature to do what CONFIG_PM_SLEEP_SMP does, but without
> CONFIG_PM_SLEEP_SMP enabled?

Yeah pretty much, I'm actually asking should we take care of this since maybe not all platforms 
will have this config enabled?
> 
> Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform requires that the lowest CPU
> number be the CPU dealing with reboot?

Someday we will have it enabled, but before that we'll hit the issue, so you don't think
this should be taken care of? Thanks.



From mturquette at linaro.org  Fri Aug 24 20:21:51 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 24 Aug 2012 17:21:51 -0700
Subject: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <20120825002151.18366.99434@nucleus>

Quoting Chao Xie (2012-08-19 19:55:10)
> From: Chao Xie <chao.xie at marvell.com>
>  arch/arm/mach-mmp/Kconfig    |    3 +
>  drivers/clk/Makefile         |    3 +
>  drivers/clk/mmp/Makefile     |    9 +
>  drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++++
>  drivers/clk/mmp/clk-apmu.c   |   97 +++++++++
>  drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++++
>  drivers/clk/mmp/clk-mmp2.c   |  449 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/mmp/clk-pxa168.c |  346 ++++++++++++++++++++++++++++++++
>  drivers/clk/mmp/clk-pxa910.c |  320 ++++++++++++++++++++++++++++++
>  drivers/clk/mmp/clk.h        |   35 ++++

Looks like you are not removing your arch/arm/mach-mmp/clock.c.  Is that
intentional?

When I apply your series against v3.6-rc3 I find that compilation breaks
with mmp2_defconfig due to conflicting definitions for the clk api
(clk_enable, clk_set_rate, etc).  This is not surprising since your
legacy clock code is neither deleted nor removed from compilation
conditionally by checking for CONFIG_COMMON_CLK.

Did I somehow manage to misapply your patches or should your patches
have removed the arch-specific clock framework as well?

Regards,
Mike

>  10 files changed, 1567 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/mmp/Makefile
>  create mode 100644 drivers/clk/mmp/clk-apbc.c
>  create mode 100644 drivers/clk/mmp/clk-apmu.c
>  create mode 100644 drivers/clk/mmp/clk-frac.c
>  create mode 100644 drivers/clk/mmp/clk-mmp2.c
>  create mode 100644 drivers/clk/mmp/clk-pxa168.c
>  create mode 100644 drivers/clk/mmp/clk-pxa910.c
>  create mode 100644 drivers/clk/mmp/clk.h


From omycle at gmail.com  Fri Aug 24 23:12:09 2012
From: omycle at gmail.com (Li Haifeng)
Date: Sat, 25 Aug 2012 11:12:09 +0800
Subject: For physical memory management, why take holes page as free pages?
Message-ID: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>

Hi, everybody.

Sorry to disturb you. When I study memory management of boot_mem, I
have question about 505~506 lines below code for initialization of
physical memory management. The function of these two lines is to make
the holes between adjacent bank free in node_bootmem_map of
corresponding node, which is a bitmap.

IMO, the holes between two bank should be marked reserved in page
bitmap, because it couldn't be used for allocating memory in buddy
system.

start_kernel->mm_init->mem_init-> free_unused_memmap:
-------------------------------->
arch/arm/mm/init.c:

472 static void __init free_unused_memmap(struct meminfo *mi)
473 {
474         unsigned long bank_start, prev_bank_end = 0;
475         unsigned int i;
476
477         /*
478          * This relies on each bank being in address order.
479          * The banks are sorted previously in bootmem_init().
480          */
481         for_each_bank(i, mi) {
482                 struct membank *bank = &mi->bank[i];
483
484                 bank_start = bank_pfn_start(bank);
485
486 #ifdef CONFIG_SPARSEMEM
487                 /*
488                  * Take care not to free memmap entries that don't exist
489                  * due to SPARSEMEM sections which aren't present.
490                  */
491                 bank_start = min(bank_start,
492                                  ALIGN(prev_bank_end, PAGES_PER_SECTION));
493 #else
494                 /*
495                  * Align down here since the VM subsystem insists that the
496                  * memmap entries are valid from the bank start aligned to
497                  * MAX_ORDER_NR_PAGES.
498                  */
499                 bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
500 #endif
501                 /*
502                  * If we had a previous bank, and there is a space
503                  * between the current bank and the previous, free it.
504                  */
505                 if (prev_bank_end && prev_bank_end < bank_start)
506                         free_memmap(prev_bank_end, bank_start);
507
508                 /*
509                  * Align up here since the VM subsystem insists that the
510                  * memmap entries are valid from the bank end aligned to
511                  * MAX_ORDER_NR_PAGES.
512                  */
513                 prev_bank_end = ALIGN(bank_pfn_end(bank),
MAX_ORDER_NR_PAGES);
514         }


Thanks.


From swarren at nvidia.com  Fri Aug 24 23:32:02 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 24 Aug 2012 21:32:02 -0600
Subject: [PATCHv4 0/9] *** ARM: Update arch-vt8500 to Devicetree ***
In-Reply-To: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
References: <1345707346-9035-1-git-send-email-linux@prisktech.co.nz>
Message-ID: <50384732.9060304@nvidia.com>

On 08/23/2012 01:35 AM, Tony Prisk wrote:
> This patchset updates arch-vt8500 to devicetree and removes all the old-style
> code. Support for WM8650 has also been added.
> 
> Example dts/dtsi files are given for the three currently supported models.
> 
> Major changes:
> 
> GPIO code has been converted to a platform_device and rewritten as WM8505
> support was broken. Add support for WM8650 gpio controller.
> 
> UHCI support was missing. Added this as a generic non-pci uhci controller as
> it doesn't require anything special. Should be usable by any system that doesn't
> have special requirements to get the UHCI controller working.
> 
> Framebuffer code patched to support WM8650. The bindings for this are of concern
> but there doesn't seem to be a formalized binding yet. This patch is based off
> Sascha Hauer's current patch on the dri-devel mailing list and should be easily
> patched out when its finalized.
> 
> Patchset based on Arnd's arm-soc/for-next branch.

I believe all the issues I pointed out are fixed in this series. I'm not
sure I reviewed it in enough detail to ack it, but I'm fine with what I saw.


From shawn.guo at linaro.org  Sat Aug 25 01:01:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 13:01:26 +0800
Subject: [PATCH] ARM: imx6q-sabrelite: Rename 'pinctrl_gpio_hog'
In-Reply-To: <1345821890-2922-1-git-send-email-festevam@gmail.com>
References: <1345821890-2922-1-git-send-email-festevam@gmail.com>
Message-ID: <20120825050123.GH31998@S2101-09.ap.freescale.net>

On Fri, Aug 24, 2012 at 12:24:50PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> 'pinctrl_gpio_hog' is used to setup the pin functions, and it is not neccesarily used only
> for GPIO pins, so remove 'gpio' from its name to describe a more generic term.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied with the following changes amended.

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 38755b1..1c57e19 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -48,8 +48,8 @@
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_hog>;

-                               gpios {
-                                       pinctrl_hog: hog {
+                               hog {
+                                       pinctrl_hog: hoggrp {
                                                fsl,pins = <
                                                        1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
                                                        1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */


> ---
>  arch/arm/boot/dts/imx6q-sabrelite.dts |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
> index 72f30f3..2e01478 100644
> --- a/arch/arm/boot/dts/imx6q-sabrelite.dts
> +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
> @@ -46,10 +46,10 @@
>  
>  			iomuxc at 020e0000 {
>  				pinctrl-names = "default";
> -				pinctrl-0 = <&pinctrl_gpio_hog>;
> +				pinctrl-0 = <&pinctrl_hog>;
>  
>  				gpios {
> -					pinctrl_gpio_hog: gpiohog {
> +					pinctrl_hog: hog {
>  						fsl,pins = <
>  							   144  0x80000000	/* MX6Q_PAD_EIM_D22__GPIO_3_22 */
>  							   121  0x80000000	/* MX6Q_PAD_EIM_D19__GPIO_3_19 */
> -- 
> 1.7.9.5
> 


From horms at verge.net.au  Sat Aug 25 03:13:44 2012
From: horms at verge.net.au (Simon Horman)
Date: Sat, 25 Aug 2012 16:13:44 +0900
Subject: [PATCH 0/2] Renesas IPMMU driver for sh7372
In-Reply-To: <1343197742-13630-1-git-send-email-hdk@igel.co.jp>
References: <1343197742-13630-1-git-send-email-hdk@igel.co.jp>
Message-ID: <20120825071344.GI29755@verge.net.au>

On Wed, Jul 25, 2012 at 03:29:00PM +0900, Hideki EIRAKU wrote:
> This is the Renesas IPMMU driver, IOMMU API implementation and IPMMU
> device support for sh7372 (AP4EVB and Mackerel).
> 
> The IPMMU module supports the MMU function and the PMB function.  The
> MMU function provides address translation by pagetable compatible with
> ARMv6.  The PMB function provides address translation including
> tile-linear translation.  This is implementation of the MMU function.

Hi,

I am wondering if anyone has had a chance to review this short series.
It seems reasonable to me with the minor exception that I would
be happier the second patch to update the relevant defconfigs
to either enable or disable the driver.

I am also curious to know how this driver may be tested.


From linux at arm.linux.org.uk  Sat Aug 25 03:17:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 25 Aug 2012 08:17:56 +0100
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <A7051F87A141B744BCAF487D48E5B3BDF5BA98284A@HKMAIL02.nvidia.com>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
 <A7051F87A141B744BCAF487D48E5B3BDF5BA98284A@HKMAIL02.nvidia.com>
Message-ID: <20120825071755.GG18957@n2100.arm.linux.org.uk>

On Sat, Aug 25, 2012 at 08:00:56AM +0800, Bill Huang wrote:
> nvpublic
> > So what you're asking for is a feature to do what CONFIG_PM_SLEEP_SMP does, but without
> > CONFIG_PM_SLEEP_SMP enabled?
> 
> Yeah pretty much, I'm actually asking should we take care of this since maybe not all platforms 
> will have this config enabled?
> > 
> > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform requires that the lowest CPU
> > number be the CPU dealing with reboot?
> 
> Someday we will have it enabled, but before that we'll hit the issue, so you don't think
> this should be taken care of? Thanks.

Well, just enable CONFIG_PM_SLEEP_SMP then - it'll be far better than
trying to implement something in the ARM code, especially as sysrq can
be used for poweroff/reboot etc (which will run from atomic contexts
where you can't switch to another CPU.)

What you're asking for will make these callbacks fragile for other
platforms.


From rmallon at gmail.com  Sat Aug 25 03:18:28 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Sat, 25 Aug 2012 17:18:28 +1000
Subject: [PATCH v3] ARM: ep93xx: Use HW MAC filter in ethernet driver
In-Reply-To: <1345548967.4262.2.camel@localhost>
References: <1345548967.4262.2.camel@localhost>
Message-ID: <50387C44.3050507@gmail.com>

On 21/08/12 21:36, Yan Burman wrote:

> ARM: ep93xx: Use HW MAC filter in ethernet driver
> Use HW MAC filtering for broadcasts and multicasts.
> Do not always work in promiscuous mode.
> Partially based on kernel 2.6.20.4 driver from cirrus logic.
> Tested on 9302 and 9315 based boards.


Hi Yan,

This looks fine to me, but can you please resend and Cc the appropriate
network list and maintainer so they can have a look to please.
Otherwise I am happy to take this in my tree.

Thanks,
~Ryan

> 
> Changes from v2:
> * Some more minor style changes
> 
> Changes from v1:
> * Some minor style fixes
> * Use CRC32 code instead of duplicating code
> * Fixed multicast reception (tested with omping)
> 
> Signed-off-by: Yan Burman <burman.yan at gmail.com>
> 
> diff --git a/drivers/net/ethernet/cirrus/Kconfig b/drivers/net/ethernet/cirrus/Kconfig
> index 8388e36..b7b154f 100644
> --- a/drivers/net/ethernet/cirrus/Kconfig
> +++ b/drivers/net/ethernet/cirrus/Kconfig
> @@ -46,6 +46,7 @@ config EP93XX_ETH
>  	depends on ARM && ARCH_EP93XX
>  	select NET_CORE
>  	select MII
> +	select CRC32
>  	help
>  	  This is a driver for the ethernet hardware included in EP93xx CPUs.
>  	  Say Y if you are building a kernel for EP93xx based devices.
> diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> index 78c5521..a92a033 100644
> --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
> +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
> @@ -25,6 +25,7 @@
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> +#include <linux/crc32.h>
>  
>  #include <mach/hardware.h>
>  
> @@ -37,8 +38,32 @@
>  #define MAX_PKT_SIZE		2044
>  #define PKT_BUF_SIZE		2048
>  
> +#define HASH_TBL_ENTRIES	8
> +
>  #define REG_RXCTL		0x0000
> -#define  REG_RXCTL_DEFAULT	0x00073800
> +#define  REG_RXCTL_PAUSEA  (1 << 20)
> +#define  REG_RXCTL_RXFCE1  (1 << 19)
> +#define  REG_RXCTL_RXFCE0  (1 << 18)
> +#define  REG_RXCTL_BCRC    (1 << 17)
> +#define  REG_RXCTL_SRXON   (1 << 16)
> +#define  REG_RXCTL_RCRCA   (1 << 13)
> +#define  REG_RXCTL_RA      (1 << 12)
> +#define  REG_RXCTL_PA      (1 << 11)
> +#define  REG_RXCTL_BA      (1 << 10)
> +#define  REG_RXCTL_MA      (1 << 9)
> +#define  REG_RXCTL_IAHA    (1 << 8)
> +#define  REG_RXCTL_IA3     (1 << 3)
> +#define  REG_RXCTL_IA2     (1 << 2)
> +#define  REG_RXCTL_IA1     (1 << 1)
> +#define  REG_RXCTL_IA0     (1 << 0)
> +#define  REG_RXCTL_DEFAULT	(REG_RXCTL_BA | \
> +				REG_RXCTL_RA | \
> +				REG_RXCTL_RCRCA | \
> +				REG_RXCTL_SRXON | \
> +				REG_RXCTL_BCRC | \
> +				REG_RXCTL_RXFCE0 | \
> +				REG_RXCTL_IA0)
> +
>  #define REG_TXCTL		0x0004
>  #define  REG_TXCTL_ENABLE	0x00000001
>  #define REG_MIICMD		0x0010
> @@ -57,6 +82,12 @@
>  #define  REG_INTSTS_RX		0x00000004
>  #define REG_INTSTSC		0x002c
>  #define REG_AFP			0x004c
> +#define  REG_AFP_IA0		0
> +#define  REG_AFP_IA1		1
> +#define  REG_AFP_IA2		2
> +#define  REG_AFP_IA3		3
> +#define  REG_AFP_DTxP		6
> +#define  REG_AFP_HASH		7
>  #define REG_INDAD0		0x0050
>  #define REG_INDAD1		0x0051
>  #define REG_INDAD2		0x0052
> @@ -386,6 +417,51 @@ static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
>  	return NETDEV_TX_OK;
>  }
>  
> +static void ep93xx_set_mcast_tbl(struct net_device *dev, u8 *buf)
> +{
> +	struct netdev_hw_addr *ha;
> +	u32 crc;
> +
> +	netdev_for_each_mc_addr(ha, dev) {
> +		crc = ether_crc_le(ETH_ALEN, ha->addr);
> +		buf[crc >> 29] |= (1 << ((crc >> 26) & 7));
> +	}
> +}
> +
> +static int ep93xx_ind_addr_write(struct net_device *dev, int afp, char *buf)
> +{
> +	u32 rxctl;
> +	unsigned int i, len;
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	switch (afp) {
> +	case REG_AFP_IA0:
> +	case REG_AFP_IA1:
> +	case REG_AFP_IA2:
> +	case REG_AFP_IA3:
> +	case REG_AFP_DTxP:
> +		len = ETH_ALEN;
> +		break;
> +
> +	case REG_AFP_HASH:
> +		len = HASH_TBL_ENTRIES;
> +		break;
> +
> +	default:
> +		pr_crit("invalid afp value: %d\n", afp);
> +		return -EINVAL;
> +	}
> +
> +	rxctl = rdl(ep, REG_RXCTL);
> +	wrl(ep, REG_RXCTL, rxctl & ~REG_RXCTL_SRXON);
> +	wrl(ep, REG_AFP, afp);
> +	for (i = 0; i < len; i++)
> +		wrb(ep, REG_INDAD0 + i, buf[i]);
> +	wrl(ep, REG_RXCTL, rxctl);
> +
> +	return 0;
> +}
> +
>  static void ep93xx_tx_complete(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -615,13 +691,7 @@ static int ep93xx_start_hw(struct net_device *dev)
>  	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
>  	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
>  
> -	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
> -	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
> -	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
> -	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
> -	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
> -	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
> -	wrl(ep, REG_AFP, 0);
> +	ep93xx_ind_addr_write(dev, REG_AFP_IA0, dev->dev_addr);
>  
>  	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
>  
> @@ -647,6 +717,30 @@ static void ep93xx_stop_hw(struct net_device *dev)
>  		pr_crit("hw failed to reset\n");
>  }
>  
> +static void ep93xx_set_multicast_list(struct net_device *dev)
> +{
> +	struct ep93xx_priv *ep = netdev_priv(dev);
> +
> +	if (dev->flags & IFF_PROMISC) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_PA | rdl(ep, REG_RXCTL));
> +	} else if (dev->flags & IFF_ALLMULTI) {
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(rdl(ep, REG_RXCTL) & ~REG_RXCTL_PA));
> +		ep93xx_ind_addr_write(dev, REG_AFP_HASH,
> +			      "\xff\xff\xff\xff\xff\xff\xff\xff");
> +	} else if (!netdev_mc_empty(dev)) {
> +		u8 tbl_multi[HASH_TBL_ENTRIES + 1] = {0};
> +
> +		ep93xx_set_mcast_tbl(dev, tbl_multi);
> +		wrl(ep, REG_RXCTL, REG_RXCTL_MA |
> +			(rdl(ep, REG_RXCTL) & ~REG_RXCTL_PA));
> +		ep93xx_ind_addr_write(dev, REG_AFP_HASH, tbl_multi);
> +	} else {
> +		wrl(ep, REG_RXCTL,
> +			rdl(ep, REG_RXCTL) & ~(REG_RXCTL_PA | REG_RXCTL_MA));
> +	}
> +}
> +
>  static int ep93xx_open(struct net_device *dev)
>  {
>  	struct ep93xx_priv *ep = netdev_priv(dev);
> @@ -754,6 +848,7 @@ static const struct net_device_ops ep93xx_netdev_ops = {
>  	.ndo_validate_addr	= eth_validate_addr,
>  	.ndo_change_mtu		= eth_change_mtu,
>  	.ndo_set_mac_address	= eth_mac_addr,
> +	.ndo_set_rx_mode	= ep93xx_set_multicast_list,
>  };
>  
>  static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
> 
> 




From shawn.guo at linaro.org  Sat Aug 25 03:36:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 15:36:27 +0800
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <20120824182133.GB18957@n2100.arm.linux.org.uk>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
Message-ID: <20120825073624.GI31998@S2101-09.ap.freescale.net>

On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> requires that the lowest CPU number be the CPU dealing with reboot?

I have CONFIG_PM_SLEEP_SMP enabled for imx6q, but still see the imx6q
restart hook running on cpu1 than cpu0.  It seems that
disable_nonboot_cpus is only called in kernel_power_off but never
kernel_restart.  We should probably patch kernel_restart or
machine_restart to have disable_nonboot_cpus called? 

-- 
Regards,
Shawn


From carlo_bastelli at yahoo.it  Sat Aug 25 03:46:28 2012
From: carlo_bastelli at yahoo.it (Bastelli Carlo)
Date: Sat, 25 Aug 2012 09:46:28 +0200
Subject: SLAVE Side SPI kernel driver development
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>	<CAOMZO5Ds6NKsTCptQXDGZDJasb119hYWqXMzX8nG5WFArysL7A@mail.gmail.com>
 <201208241738.45601.marex@denx.de> <5037B1DF.40503@whoi.edu>
Message-ID: <000f01cd8295$bd728770$0702a8c0@spectrekizxcpt>

In my application in fact the slave is connected to the master without other 
devices on the bus, a simple point to point, and receives a frame of known 
dimensions.
I think I will be very busy to read post in the coming days  :)

Thanks to all of you who provided suggestions.
Carlo Bastelli

----- Original Message ----- 
From: "Ned Forrester" <nforrester at whoi.edu>
To: "Marek Vasut" <marex at denx.de>
Cc: "Fabio Estevam" <festevam at gmail.com>; 
<spi-devel-general at lists.sourceforge.net>; "Bastelli Carlo (yahoo)" 
<carlo_bastelli at yahoo.it>; <linux-kernel at vger.kernel.org>; 
<linux-arm-kernel at lists.infradead.org>
Sent: Friday, August 24, 2012 6:54 PM
Subject: Re: SLAVE Side SPI kernel driver development


On 08/24/2012 11:38 AM, Marek Vasut wrote:
> Dear Fabio Estevam,
>
>> On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)
>
> CCing SPI list
>
>> <carlo_bastelli at yahoo.it> wrote:
>>> Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
>>> develop
>>>
>>>  a driver SPI slave side on embedded ARM processor running Linux.
>>>
>>> Precisely linux occur on the SPI bus as a slave, not master as required
>>> by the hierarchical structure of the current kernel. The new driver
>>> will
>>>
>>>  receive via interrupt and respond when selected by its chip select.
>
> So a soft-spi ? It's gonna be slow as hell and unstable too.
>
>>>  Can
>>>  anyone suggest the best way to develop this driver?
>
> Get a CPU which has SPI-slave capable IP, start from there. If you were to
> implement soft-spi this way, you'd have to use FIQ on ARM, to be able to 
> handle
> stuff with reasonable latency ... check how the ps/2-gpio driver is done 
> in
> Linux ... I tried it, it barely worked, you don't want to go down that 
> road.
>
>>>  Personally, I
>>>
>>> have identified two main roads, the first if possible to exploit the
>>> structure SPI master driver
>
> Not happening. You'd have to split the parts from the struct spi_master 
> into
> common and master-only parts. That's for starters.
>
>>> with a few tricks that now I can not
>>> define. The second most radical, write a driver for a UART like, but
>>> managing the SPI device.
>>> Thank you for any suggestions or examples.
>
> First of all, the SPI slave mode is COMPLETELY different from the master 
> mode.
> You need to react on incoming CS-low ASAP, which might turn out to be a 
> problem
> on it's own. Then, even if you do, you do not know how long the transfer 
> is
> going to be, so you need to allocate enough buffers as the transfer 
> progresses
> onwards.
>
> In case of your soft-spi, how do you plan to sample the CLK line to sync 
> clock?
>
>> Marek got spi slave running on a mx28. See his patch:
>> http://www.spinics.net/lists/arm-kernel/msg190860.html
>
> This was tested (and developed) on this board:
> http://www.denx-cs.de/?q=M28
>
> The userland code is really easy too, simply pump it into spidev or read 
> from
> it. But all that is only possible because of the SPI IP in the mx28 is 
> nice.
>
>> Regards,
>>
>> Fabio Estevam
>
> Best regards,
> Marek Vasut

I generally agree with the above comments.  A generalized SPI slave must
be able to respond instantly, often within one clock cycle.  This can
only work in hardware, or in an OS like Linux when the activity on the
bus is completely predictable by the Linux slave.  The only cases I know
of are streaming of data in a predictable way between a single master
and single slave (no other devices on the bus).

This topic comes up periodically, but I don't think there has been any
change in the situation for all the time I've followed the discussion.
I recommend that you read the archives of this mailing list to
understand the limitations of a potential slave mode.  The archives can
be found at:

http://sourceforge.net/mailarchive/forum.php?forum_name=spi-devel-general

then look for threads with "slave" in the subject in the following
months (I'd give thread start dates, but parts of the threads are
disconnected in the archives, and this is the easiest way to see all the
parts, day ranges are in parentheses):

2007/04 (13-18)
2007/09/27 and 2007/10 (13-17)
2009/03 (2-3)
2009/12/18 and 2010/1/19 and 2010/02 (14-16)
2010/07 (26) and 2010/08 (13)
2011/01 (28-31) and 2011/02 (1-10)
2011/10 (18)
2012/06 (29-30 and 2012/07 (1-17)

-- 
Ned Forrester                                       nforrester at whoi.edu
Oceanographic Systems Lab                           508-289-2226 Office
Applied Ocean Physics and Engineering Dept.
Woods Hole Oceanographic Institution          Woods Hole, MA 02543, USA
http://www.whoi.edu/
http://www.whoi.edu/page.do?pid=29856
http://www.whoi.edu/hpb/Site.do?id=1532



From linux at arm.linux.org.uk  Sat Aug 25 03:52:21 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 25 Aug 2012 08:52:21 +0100
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <20120825073624.GI31998@S2101-09.ap.freescale.net>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
 <20120825073624.GI31998@S2101-09.ap.freescale.net>
Message-ID: <20120825075221.GH18957@n2100.arm.linux.org.uk>

On Sat, Aug 25, 2012 at 03:36:27PM +0800, Shawn Guo wrote:
> On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> > requires that the lowest CPU number be the CPU dealing with reboot?
> 
> I have CONFIG_PM_SLEEP_SMP enabled for imx6q, but still see the imx6q
> restart hook running on cpu1 than cpu0.  It seems that
> disable_nonboot_cpus is only called in kernel_power_off but never
> kernel_restart.  We should probably patch kernel_restart or
> machine_restart to have disable_nonboot_cpus called? 

Remember that this path gets called from IRQ context which makes calling
functions which sleep very dodgy.


From shawn.guo at linaro.org  Sat Aug 25 03:56:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 15:56:10 +0800
Subject: [PATCH 1/4 V2] ARM: mx28: Add SPI 2 pinmux into imx28.dtsi
In-Reply-To: <1345852300-2213-1-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
Message-ID: <20120825075606.GJ31998@S2101-09.ap.freescale.net>

On Sat, Aug 25, 2012 at 01:51:37AM +0200, Marek Vasut wrote:
> Add this SSP port 2 pin multiplexing configuration into the imx28.dtsi file.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>

Applied, thanks.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Sat Aug 25 03:57:06 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 15:57:06 +0800
Subject: [PATCH 2/4 V2] ARM: mx28: Add USB PHY overcurrent pinmux
In-Reply-To: <1345852300-2213-2-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-2-git-send-email-marex@denx.de>
Message-ID: <20120825075704.GK31998@S2101-09.ap.freescale.net>

On Sat, Aug 25, 2012 at 01:51:38AM +0200, Marek Vasut wrote:
> Add the pinmux settings for USB PHY overcurrent pins.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx28.dtsi |   30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> V2: This is pulled from the M28EVK and SPS1 board files, put it into common
>     file.
> 
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index b996c2d..3cba62d 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -520,6 +520,36 @@
>  					fsl,voltage = <1>;
>  					fsl,pull-up = <1>;
>  				};
> +
> +				usbphy0_pins_a: usbphy0 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
> +					>;
> +					fsl,drive-strength = <2>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +
> +				usbphy0_pins_b: usbphy0 at 1 {
> +					reg = <0>;

This should be
					reg = <1>;

Fixed it up and applied the patch.

> +					fsl,pinmux-ids = <
> +						0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
> +					>;
> +					fsl,drive-strength = <2>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +
> +				usbphy1_pins_a: usbphy1 at 0 {
> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
> +					>;
> +					fsl,drive-strength = <2>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
>  			};
>  
>  			digctl at 8001c000 {
> -- 
> 1.7.10.4
> 

-- 
Regards,
Shawn


From linux at arm.linux.org.uk  Sat Aug 25 03:57:42 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 25 Aug 2012 08:57:42 +0100
Subject: [PATCH 1/1] mmc: host: enable OMAP DMA engine support for omap
 hosts by default
In-Reply-To: <alpine.DEB.2.01.1208241404440.21552@pmeerw.net>
References: <CAMQu2gy-U1WmgGOGZ+VyXjZmLem9TEWbq5kR8jzC0qXvqF-=BA@mail.gmail.com>
 <CAAwP0s2Efuuc7vsX3bZuwz175zUjnmsOV87OcZ06p_eoe4T3Ug@mail.gmail.com>
 <alpine.DEB.2.01.1208232246530.15831@pmeerw.net>
 <CAMQu2gyEGPbNEE0ur0wh9RoJKuBe4B5NkQMUafQNWGVLX8t9vg@mail.gmail.com>
 <alpine.DEB.2.01.1208240942100.21552@pmeerw.net>
 <20120824094231.GA25765@n2100.arm.linux.org.uk>
 <CAMQu2gxs0bzNMtxb0LFyFKM9s4M4yXxFpopaBO+Hah3RjhCpLA@mail.gmail.com>
 <20120824103913.GB25765@n2100.arm.linux.org.uk>
 <CAMQu2gw-vEguFU9naxsHtDVOfJkZVsFNMWJbvbc=ZuULy7TZNA@mail.gmail.com>
 <alpine.DEB.2.01.1208241404440.21552@pmeerw.net>
Message-ID: <20120825075742.GC25765@n2100.arm.linux.org.uk>

On Fri, Aug 24, 2012 at 02:10:38PM +0200, Peter Meerwald wrote:
> with Linux 3.6-rc3:
> 
> CONFIG_DMA_OMAP=m
> CONFIG_DMA_ENGINE=y
> CONFIG_DMA_VIRTUAL_CHANNELS=m
> CONFIG_MMC_OMAP_HS=y
> CONFIG_SPI_OMAP24XX=y
> CONFIG_MTD_NAND_OMAP2=y
> 
>   LD      init/built-in.o
> drivers/built-in.o: In function `omap2_mcspi_setup':
> /home/pmeerw/linux-pmeerw/drivers/spi/spi-omap2-mcspi.c:859: undefined reference to `omap_dma_filter_fn'
> drivers/built-in.o: In function `omap_nand_probe':
> /home/pmeerw/linux-pmeerw/drivers/mtd/nand/omap2.c:1371: undefined reference to `omap_dma_filter_fn'
> drivers/built-in.o: In function `omap_hsmmc_probe':
> /home/pmeerw/linux-pmeerw/drivers/mmc/host/omap_hsmmc.c:2039: undefined reference to `omap_dma_filter_fn'
> make: *** [vmlinux] Error 1
> 
> in addition to SPI and MMC, there seems to be also a NAND dependency

Yes.  Unlike the PL08x driver, OMAP has no way to pass the filter function
into its drivers, and I didn't want the pain of fiddling around with DT
crap to try and work out how to do this.  So what you have here is
something that I got as far as I could, and TI then wanted it pushed into
mainline.

I have no solution for the above at present - the long term solution is
to sort out how to deal with DMA engine with DT etc.  At the moment,
there has been discussion about this but no solution.


From shawn.guo at linaro.org  Sat Aug 25 04:05:07 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 16:05:07 +0800
Subject: [PATCH 3/4 V2] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <1345852300-2213-3-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-3-git-send-email-marex@denx.de>
Message-ID: <20120825080504.GL31998@S2101-09.ap.freescale.net>

On Sat, Aug 25, 2012 at 01:51:39AM +0200, Marek Vasut wrote:
> +
> +		reg_vddio_sd0: vddio-sd0 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "vddio-sd0";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +			gpio = <&gpio3 28 0>;
> +		};
> +
> +		reg_usb0_vbus: usb0_vbus {
> +			compatible = "regulator-fixed";
> +			regulator-name = "usb0_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 12 0>;
> +			enable-active-low;

Documentation/devicetree/bindings/regulator/fixed-regulator.txt:

- enable-active-high: Polarity of GPIO is Active high
If this property is missing, the default assumed is Active low.

I suspect you need to recheck this aspect for all these 3 fixed
regulators.

> +		};
> +
> +		reg_usb1_vbus: usb1_vbus {
> +			compatible = "regulator-fixed";
> +			regulator-name = "usb1_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 13 0>;
> +			enable-active-low;
> +		};

-- 
Regards,
Shawn


From andrew at lunn.ch  Sat Aug 25 04:22:31 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 25 Aug 2012 10:22:31 +0200
Subject: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkda0wUW4E3y=ucGRFu5fwwyFWo2dc=4qBaH6CFSOW2ZL_A@mail.gmail.com>
Message-ID: <20120825082231.GG9886@lunn.ch>

On Mon, Aug 20, 2012 at 11:09:51AM +0200, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <sebastian.hesselbarth at gmail.com> wrote:
> 
> > This patch adds a pinctrl driver core for Marvell SoCs plus DT
> > binding documentation. This core driver will be used by SoC family
> > specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
> 
> Thanks for dealing with this, much appreaciated!
> 
> Are you taking this patch series through some Marvell tree or do you want
> me to carry it in the pinctrl tree?

Hi Linus

We can carry it thought the Marvell tree. 

   Andrew


From shawn.guo at linaro.org  Sat Aug 25 04:30:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 16:30:45 +0800
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <1345852300-2213-4-git-send-email-marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-4-git-send-email-marex@denx.de>
Message-ID: <20120825083042.GM31998@S2101-09.ap.freescale.net>

Please base it on my mxs/dt-for-3.7 branch.

On Sat, Aug 25, 2012 at 01:51:40AM +0200, Marek Vasut wrote:
> Add DTS file for this custom board.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx28-sps1.dts |  168 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-mxs/mach-mxs.c     |    3 +
>  2 files changed, 171 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx28-sps1.dts
> 
> diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
> new file mode 100644
> index 0000000..d05b1cb
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-sps1.dts
> @@ -0,0 +1,168 @@
> +/*
> + * Copyright (C) 2012 Marek Vasut <marex at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "SchulerControl GmbH, SC SPS 1";
> +	compatible = "schulercontrol,imx28-sps1", "fsl,imx28";

We should use the short name as prefix if it has one.

> +
> +	memory {
> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	apb at 80000000 {
> +		apbh at 80000000 {
> +			pinctrl at 80018000 {
> +				led_pins_sps1: leds at 0 {

It should be referenced by the pinctrl state directly under node
pinctrl at 80018000, otherwise the pins will not be set up.

Also we usually use a generic name here something like

				hog_pins_a: hog at 0 {

so that we do not need to create new node every time we add pins
for a new module.

> +					reg = <0>;
> +					fsl,pinmux-ids = <
> +						0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
> +						0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
> +						0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
> +					>;
> +					fsl,drive-strength = <0>;
> +					fsl,voltage = <1>;
> +					fsl,pull-up = <0>;
> +				};
> +
> +			};
> +
> +			ssp0: ssp at 80010000 {
> +				compatible = "fsl,imx28-mmc";
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&mmc0_4bit_pins_a>;
> +				bus-width = <4>;
> +				status = "okay";
> +			};
> +
> +			ssp2: ssp at 80014000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx28-spi";
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&spi2_pins_a>;
> +				status = "okay";
> +
> +				flash: m25p80 at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					compatible = "everspin,mr25h256", "mr25h256";

Node name "m25p80" and "mr25h256", same thing?

> +					spi-max-frequency = <40000000>;
> +					reg = <0>;
> +				};
> +			};
> +		};
> +
> +		apbx at 80040000 {
> +			i2c0: i2c at 80058000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&i2c0_pins_a>;
> +				clock-frequency = <400000>;
> +				status = "okay";
> +
> +				rtc: rtc at 51 {
> +					compatible = "nxp,pcf8563";
> +					reg = <0x51>;
> +				};
> +
> +				eeprom: eeprom at 52 {
> +					compatible = "atmel,24c64";
> +					reg = <0x52>;
> +					pagesize = <32>;
> +				};
> +			};
> +
> +			duart: serial at 80074000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&duart_pins_a>;
> +				status = "okay";
> +			};
> +
> +			usbphy0: usbphy at 8007c000 {
> +				status = "okay";
> +			};
> +
> +			auart0: serial at 8006a000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&auart0_pins_a>;
> +				status = "okay";
> +			};
> +
> +			rtc at 80056000 {
> +				status = "okay";
> +			};

This is not needed.  We have rtc enabled in imx28.dtsi by default now.

> +		};
> +	};
> +
> +	ahb at 80080000 {
> +		usb0: usb at 80080000 {
> +			vbus-supply = <&reg_usb0_vbus>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&usbphy0_pins_b>;
> +			status = "okay";
> +		};
> +
> +		mac0: ethernet at 800f0000 {
> +			phy-mode = "rmii";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&mac0_pins_a>;
> +			status = "okay";
> +		};
> +
> +		mac1: ethernet at 800f4000 {
> +			phy-mode = "rmii";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&mac1_pins_a>;
> +			status = "okay";
> +		};
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +
> +		reg_usb0_vbus: usb0_vbus {
> +			compatible = "regulator-fixed";
> +			regulator-name = "usb0_vbus";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			gpio = <&gpio3 9 0>;
> +			enable-active-low;

Same comment I put on patch #3.

> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&led_pins_sps1>;

Aha, you put it here.  But do you have leds-gpio driver call pinctrl
to set them up?

> +		status = "okay";
> +
> +		led at 1 {

There should be a "reg" property matching the number after @.  So you
need to either give it a unique node name without @?, or you add a reg
property.

> +			label = "sps1-1:yellow:user";
> +			gpios = <&gpio0 6 0>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +
> +		led at 2 {
> +			label = "sps1-2:red:user";
> +			gpios = <&gpio0 3 0>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +
> +		led at 3 {
> +			label = "sps1-3:red:user";
> +			gpios = <&gpio0 0 0>;
> +			default-trigger = "heartbeat";
> +		};
> +
> +	};
> +};
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 5ac45a1..f131ff1 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -279,6 +279,8 @@ static void __init mxs_machine_init(void)
>  		m28evk_init();
>  	else if (of_machine_is_compatible("bluegiga,apx4devkit"))
>  		apx4devkit_init();
> +	else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
> +		imx28_evk_init();

Call imx28_evk_init for imx28-sps1 board?

>  
>  	of_platform_populate(NULL, of_default_bus_match_table,
>  			     mxs_auxdata_lookup, NULL);
> @@ -298,6 +300,7 @@ static const char *imx28_dt_compat[] __initdata = {
>  	"denx,m28evk",
>  	"fsl,imx28-evk",
>  	"karo,tx28",
> +	"schulercontrol,imx28-sps1",

See mxs/dt-for-3.7 branch.  We are using generic compat string for
matching.

>  	"fsl,imx28",
>  	NULL,
>  };
> -- 
> 1.7.10.4
> 

-- 
Regards,
Shawn


From plagnioj at jcrosoft.com  Sat Aug 25 04:38:11 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 25 Aug 2012 10:38:11 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <50366D2B.4010807@wwwdotorg.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <5034FC18.2090400@wwwdotorg.org>
 <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>
 <50366D2B.4010807@wwwdotorg.org>
Message-ID: <20120825083811.GB7629@game.jcrosoft.org>

On 11:49 Thu 23 Aug     , Stephen Warren wrote:
> On 08/23/2012 01:06 AM, Richard Genoud wrote:
> > 2012/8/22 Stephen Warren <swarren at wwwdotorg.org>:
> >>>> +Required properties for iomux controller:
> >>>> +- compatible: "atmel,at91rm9200-pinctrl"
> >>>> +- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
> >>>> +  configured in this periph mode. All the periph and bank need to be describe.
> >>>
> >>> Can you please be more elaborate on this mux-mask, like what each bit
> >>> means and why the bits are arranged like that and what it means on the
> >>> AT91 platform.... I was first reading the .dts and was like ?woot? so
> >>> I go to the bindings doc and I read this and I'm still like ?woot?..
> >>
> >> Yes, I'm a little confused what this is, and wouldn't have a clue how to
> >> fill it in.
> >
> > With a practical example it's easier to understand.
> > Take a SAM9X5 release manual (here is sam9g35):
> > http://www.atmel.com/Images/doc11053.pdf page 11 (?4.3 package pinout)
> > in the file arch/arm/boot/dts/at91sam9x5.dtsi you've got the the
> > atmel,mux-mask like that:
> >
> > /* periphA  periphB    periphC     */
> > 0xffffffff 0xffe0399f 0xc000001c  /* pioA */
> > 0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
> > 0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
> > 0x003fffff 0x003f8000 0x00000000  /* pioD */
> > 
> > Let's take the PioA - peripheral B: 0xffe0399f
> > From the documentation table 4-3, we can extract the column PIO
> > Periperal B for all signals PA0-PA31:
> ...
> > Each time it's possible to mux a pin to the peripheral B function (ie
> > when there's no "-----") the corresponding bit is set:
> ...
> > => this gives 0x399f
> 
> Ah OK. It would be a good idea to briefly describe this process in the
> binding document I think. I assume this property exists to avoid the
> kernel driver having to contain tables for each Atmel device; the driver
> is generic.
Yeap I did this exactly for this

I do not want to maintain such code for the whole bunch of at91
and this way I add other SoC with just via dtsi without touching c code

I think other driver should do so too

Best Regards,
J.


From shawn.guo at linaro.org  Sat Aug 25 06:33:01 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 18:33:01 +0800
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <20120825075221.GH18957@n2100.arm.linux.org.uk>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
 <20120825073624.GI31998@S2101-09.ap.freescale.net>
 <20120825075221.GH18957@n2100.arm.linux.org.uk>
Message-ID: <20120825103257.GN31998@S2101-09.ap.freescale.net>

On Sat, Aug 25, 2012 at 08:52:21AM +0100, Russell King - ARM Linux wrote:
> On Sat, Aug 25, 2012 at 03:36:27PM +0800, Shawn Guo wrote:
> > On Fri, Aug 24, 2012 at 07:21:33PM +0100, Russell King - ARM Linux wrote:
> > > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your platform
> > > requires that the lowest CPU number be the CPU dealing with reboot?
> > 
> > I have CONFIG_PM_SLEEP_SMP enabled for imx6q, but still see the imx6q
> > restart hook running on cpu1 than cpu0.  It seems that
> > disable_nonboot_cpus is only called in kernel_power_off but never
> > kernel_restart.  We should probably patch kernel_restart or
> > machine_restart to have disable_nonboot_cpus called? 
> 
> Remember that this path gets called from IRQ context which makes calling
> functions which sleep very dodgy.

I'm so familiar with the code/context.  Are you saying disable_nonboot_cpus
sleeps and kernel_power_off never gets called from IRQ context?

I tested the code change below on kernel_restart with
CONFIG_DEBUG_ATOMIC_SLEEP enabled.  It fixes imx6q restart issue (with
no change on cpu_relax) while no sleep-inside-atomic-section warning
is seen. 

Regards,
Shawn

diff --git a/kernel/sys.c b/kernel/sys.c
index 241507f..0359328 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -373,6 +373,7 @@ void kernel_restart(char *cmd)
        else
                printk(KERN_EMERG "Restarting system with command '%s'.\n", cmd);
        kmsg_dump(KMSG_DUMP_RESTART);
+       disable_nonboot_cpus();
        machine_restart(cmd);
 }
 EXPORT_SYMBOL_GPL(kernel_restart);


From sylvester.nawrocki at gmail.com  Sat Aug 25 08:20:40 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sat, 25 Aug 2012 14:20:40 +0200
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
Message-ID: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>

This short patch series converts remaining users of the s3c24xx SoC
specific gpiolib functions to the gpiolib API and finally removes
all s3c2410_* functions from drivers/gpio/gpio-samsung.c.

Sylwester Nawrocki (3):
  ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to gpiolib API
  ARM: S3C24XX: Remove obsolete GPIO API declarations
  gpio-samsung: Remove now unused s3c2410_gpio* API

 arch/arm/mach-s3c24xx/mach-anubis.c           |    3 +-
 arch/arm/mach-s3c24xx/mach-jive.c             |   12 ++--
 arch/arm/mach-s3c24xx/mach-mini2440.c         |    4 +-
 arch/arm/mach-s3c24xx/mach-nexcoder.c         |   22 +++---
 arch/arm/mach-s3c24xx/mach-osiris.c           |    7 +-
 arch/arm/plat-samsung/include/plat/gpio-fns.h |   97 -------------------------
 drivers/gpio/gpio-samsung.c                   |   40 ----------
 7 files changed, 25 insertions(+), 160 deletions(-)

--
1.7.4.1



From sylvester.nawrocki at gmail.com  Sat Aug 25 08:20:41 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sat, 25 Aug 2012 14:20:41 +0200
Subject: [PATCH 1/3] ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to
 gpiolib API
In-Reply-To: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <1345897243-15619-2-git-send-email-sylvester.nawrocki@gmail.com>

This is a prerequisite for removal of deprecated s3c2410_gpio* API
from the Samsung gpiolib driver.

Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Guillaume Gourat <guillaume.gourat at nexvision.tv>
Cc: Michel Pollet <buserror at gmail.com>
Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>
---
 arch/arm/mach-s3c24xx/mach-anubis.c   |    3 ++-
 arch/arm/mach-s3c24xx/mach-jive.c     |   12 ++++++------
 arch/arm/mach-s3c24xx/mach-mini2440.c |    4 ++--
 arch/arm/mach-s3c24xx/mach-nexcoder.c |   22 +++++++++++-----------
 arch/arm/mach-s3c24xx/mach-osiris.c   |    7 ++++---
 5 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 5a7d0c0..0c7ed7a 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -424,7 +424,8 @@ static void __init anubis_map_io(void)
 		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
 	} else {
 		/* ensure that the GPIO is setup */
-		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+		gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+		gpio_free(S3C2410_GPA(0));
 	}
 }
 
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba3..4713347 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -512,8 +512,8 @@ static void jive_power_off(void)
 {
 	printk(KERN_INFO "powering system down...\n");
 
-	s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-	s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+	gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPC(5));
 }
 
 static void __init jive_machine_init(void)
@@ -623,11 +623,11 @@ static void __init jive_machine_init(void)
 	gpio_request(S3C2410_GPB(7), "jive spi");
 	gpio_direction_output(S3C2410_GPB(7), 1);
 
-	s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-	s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+	gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
+	gpio_free(S3C2410_GPB(6));
 
-	s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-	s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+	gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPG(8));
 
 	/* initialise the WM8750 spi */
 
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index bd6d252..734bbfe 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -638,9 +638,9 @@ static void __init mini2440_init(void)
 	gpio_free(S3C2410_GPG(4));
 
 	/* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+	gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
 	s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
-	s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-	s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+	gpio_free(S3C2410_GPB(1));
 
 	/* mark the key as input, without pullups (there is one on the board) */
 	for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5c05ba1..a71a551 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 
 static void __init nexcoder_sensorboard_init(void)
 {
-	// Initialize SCCB bus
-	s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-	s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
-	s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-	s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
-
-	// Power up the sensor board
-	s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-	s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-	s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-	s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+	/* Initialize SCCB bus */
+	gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPE(14)); /* IICSCL */
+	gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPE(15)); /* IICSDA */
+
+	/* Power up the sensor board */
+	gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
+	gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+	gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 95d0772..c0fb3c1 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -274,8 +274,8 @@ static int osiris_pm_suspend(void)
 	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
 
 	/* ensure that an nRESET is not generated on resume. */
-	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+	gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
+	gpio_free(S3C2410_GPA(21));
 
 	return 0;
 }
@@ -396,7 +396,8 @@ static void __init osiris_map_io(void)
 		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 	} else {
 		/* write-protect line to the NAND */
-		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+		gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+		gpio_free(S3C2410_GPA(0));
 	}
 
 	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
-- 
1.7.4.1



From sylvester.nawrocki at gmail.com  Sat Aug 25 08:20:42 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sat, 25 Aug 2012 14:20:42 +0200
Subject: [PATCH 2/3] ARM: S3C24XX: Remove obsolete GPIO API declarations
In-Reply-To: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <1345897243-15619-3-git-send-email-sylvester.nawrocki@gmail.com>

It's safe to empty the plat-samsung/incude/plat/gpio-fns.h header
now when all users of those functions have been converted to
generic gpiolib API or to s3c_gpio_cfg().

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>
---
 arch/arm/plat-samsung/include/plat/gpio-fns.h |   97 -------------------------
 1 files changed, 0 insertions(+), 97 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
index bab1392..d1ecef0 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *	Ben Dooks <ben at simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
 #include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-	/* 1:1 mapping between cfgpin and setcfg calls at the moment */
-	s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *	< 0 = no interrupt for this pin
- *	>=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-				  unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
-- 
1.7.4.1



From sylvester.nawrocki at gmail.com  Sat Aug 25 08:20:43 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Sat, 25 Aug 2012 14:20:43 +0200
Subject: [PATCH 3/3] gpio-samsung: Remove now unused s3c2410_gpio* API
In-Reply-To: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <1345897243-15619-4-git-send-email-sylvester.nawrocki@gmail.com>

There is no more users of s3c2410_gpio_pullup(), s3c2410_gpio_setpin()
and s3c2410_gpio_getpin() so remove theese functions.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>
---
 drivers/gpio/gpio-samsung.c |   40 ----------------------------------------
 1 files changed, 0 insertions(+), 40 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 92f7b2b..9e71340 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3131,46 +3131,6 @@ samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
 }
 EXPORT_SYMBOL(s3c_gpio_getpull);
 
-/* gpiolib wrappers until these are totally eliminated */
-
-void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
-{
-	int ret;
-
-	WARN_ON(to);	/* should be none of these left */
-
-	if (!to) {
-		/* if pull is enabled, try first with up, and if that
-		 * fails, try using down */
-
-		ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
-		if (ret)
-			s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
-	} else {
-		s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
-	}
-}
-EXPORT_SYMBOL(s3c2410_gpio_pullup);
-
-void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
-{
-	/* do this via gpiolib until all users removed */
-
-	gpio_request(pin, "temporary");
-	gpio_set_value(pin, to);
-	gpio_free(pin);
-}
-EXPORT_SYMBOL(s3c2410_gpio_setpin);
-
-unsigned int s3c2410_gpio_getpin(unsigned int pin)
-{
-	struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-	unsigned long offs = pin - chip->chip.base;
-
-	return __raw_readl(chip->base + 0x04) & (1 << offs);
-}
-EXPORT_SYMBOL(s3c2410_gpio_getpin);
-
 #ifdef CONFIG_S5P_GPIO_DRVSTR
 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 {
-- 
1.7.4.1



From dedekind1 at gmail.com  Sat Aug 25 08:33:27 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 25 Aug 2012 15:33:27 +0300
Subject: [PATCH RESEND] mtd: lpc32xx_mlc: Make driver independent of
 AMBA DMA engine driver
In-Reply-To: <1345674311-16874-1-git-send-email-stigge@antcom.de>
References: <1345674311-16874-1-git-send-email-stigge@antcom.de>
Message-ID: <1345898007.1815.7.camel@kyv>

On Thu, 2012-08-23 at 00:25 +0200, Roland Stigge wrote:
> This patch makes the MLC NAND driver independent of the single AMBA DMA engine
> driver by using the platform data provided dma_filter callback.
> 
> (This also fixes the build error of the MLC NAND driver in case of module
> linking because the (not exported) reference to pl08x_filter_id is gone now.)
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

I already have both patches in l2-mtd.git. Please, use it as the
baseline for sending patches.

-- 
Best Regards,
Artem Bityutskiy
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From marek.vasut at gmail.com  Sat Aug 25 07:44:10 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 25 Aug 2012 13:44:10 +0200
Subject: SLAVE Side SPI kernel driver development
In-Reply-To: <000f01cd8295$bd728770$0702a8c0@spectrekizxcpt>
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>
 <5037B1DF.40503@whoi.edu> <000f01cd8295$bd728770$0702a8c0@spectrekizxcpt>
Message-ID: <201208251344.10746.marex@denx.de>

Dear Bastelli Carlo,

> In my application in fact the slave is connected to the master without
> other devices on the bus, a simple point to point, and receives a frame of
> known dimensions.

What hardware do you use? What CPU is it?

> I think I will be very busy to read post in the coming days  :)

Good luck with that.

> Thanks to all of you who provided suggestions.
> Carlo Bastelli
> 
> ----- Original Message -----
> From: "Ned Forrester" <nforrester at whoi.edu>
> To: "Marek Vasut" <marex at denx.de>
> Cc: "Fabio Estevam" <festevam at gmail.com>;
> <spi-devel-general at lists.sourceforge.net>; "Bastelli Carlo (yahoo)"
> <carlo_bastelli at yahoo.it>; <linux-kernel at vger.kernel.org>;
> <linux-arm-kernel at lists.infradead.org>
> Sent: Friday, August 24, 2012 6:54 PM
> Subject: Re: SLAVE Side SPI kernel driver development
> 
> On 08/24/2012 11:38 AM, Marek Vasut wrote:
> > Dear Fabio Estevam,
> > 
> >> On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)
> > 
> > CCing SPI list
> > 
> >> <carlo_bastelli at yahoo.it> wrote:
> >>> Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
> >>> develop
> >>> 
> >>>  a driver SPI slave side on embedded ARM processor running Linux.
> >>> 
> >>> Precisely linux occur on the SPI bus as a slave, not master as required
> >>> by the hierarchical structure of the current kernel. The new driver
> >>> will
> >>> 
> >>>  receive via interrupt and respond when selected by its chip select.
> > 
> > So a soft-spi ? It's gonna be slow as hell and unstable too.
> > 
> >>>  Can
> >>>  anyone suggest the best way to develop this driver?
> > 
> > Get a CPU which has SPI-slave capable IP, start from there. If you were
> > to implement soft-spi this way, you'd have to use FIQ on ARM, to be able
> > to handle
> > stuff with reasonable latency ... check how the ps/2-gpio driver is done
> > in
> > Linux ... I tried it, it barely worked, you don't want to go down that
> > road.
> > 
> >>>  Personally, I
> >>> 
> >>> have identified two main roads, the first if possible to exploit the
> >>> structure SPI master driver
> > 
> > Not happening. You'd have to split the parts from the struct spi_master
> > into
> > common and master-only parts. That's for starters.
> > 
> >>> with a few tricks that now I can not
> >>> define. The second most radical, write a driver for a UART like, but
> >>> managing the SPI device.
> >>> Thank you for any suggestions or examples.
> > 
> > First of all, the SPI slave mode is COMPLETELY different from the master
> > mode.
> > You need to react on incoming CS-low ASAP, which might turn out to be a
> > problem
> > on it's own. Then, even if you do, you do not know how long the transfer
> > is
> > going to be, so you need to allocate enough buffers as the transfer
> > progresses
> > onwards.
> > 
> > In case of your soft-spi, how do you plan to sample the CLK line to sync
> > clock?
> > 
> >> Marek got spi slave running on a mx28. See his patch:
> >> http://www.spinics.net/lists/arm-kernel/msg190860.html
> > 
> > This was tested (and developed) on this board:
> > http://www.denx-cs.de/?q=M28
> > 
> > The userland code is really easy too, simply pump it into spidev or read
> > from
> > it. But all that is only possible because of the SPI IP in the mx28 is
> > nice.
> > 
> >> Regards,
> >> 
> >> Fabio Estevam
> > 
> > Best regards,
> > Marek Vasut
> 
> I generally agree with the above comments.  A generalized SPI slave must
> be able to respond instantly, often within one clock cycle.  This can
> only work in hardware, or in an OS like Linux when the activity on the
> bus is completely predictable by the Linux slave.  The only cases I know
> of are streaming of data in a predictable way between a single master
> and single slave (no other devices on the bus).
> 
> This topic comes up periodically, but I don't think there has been any
> change in the situation for all the time I've followed the discussion.
> I recommend that you read the archives of this mailing list to
> understand the limitations of a potential slave mode.  The archives can
> be found at:
> 
> http://sourceforge.net/mailarchive/forum.php?forum_name=spi-devel-general
> 
> then look for threads with "slave" in the subject in the following
> months (I'd give thread start dates, but parts of the threads are
> disconnected in the archives, and this is the easiest way to see all the
> parts, day ranges are in parentheses):
> 
> 2007/04 (13-18)
> 2007/09/27 and 2007/10 (13-17)
> 2009/03 (2-3)
> 2009/12/18 and 2010/1/19 and 2010/02 (14-16)
> 2010/07 (26) and 2010/08 (13)
> 2011/01 (28-31) and 2011/02 (1-10)
> 2011/10 (18)
> 2012/06 (29-30 and 2012/07 (1-17)

Best regards,
Marek Vasut


From marek.vasut at gmail.com  Sat Aug 25 08:35:52 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 25 Aug 2012 14:35:52 +0200
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <20120825083042.GM31998@S2101-09.ap.freescale.net>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-4-git-send-email-marex@denx.de>
 <20120825083042.GM31998@S2101-09.ap.freescale.net>
Message-ID: <201208251435.52411.marex@denx.de>

Dear Shawn Guo,

> Please base it on my mxs/dt-for-3.7 branch.
> 
> On Sat, Aug 25, 2012 at 01:51:40AM +0200, Marek Vasut wrote:
> > Add DTS file for this custom board.
> > 
> > Signed-off-by: Marek Vasut <marex at denx.de>
> > Cc: Fabio Estevam <fabio.estevam at freescale.com>
> > Cc: Shawn Guo <shawn.guo at linaro.org>
> > ---
> > 
> >  arch/arm/boot/dts/imx28-sps1.dts |  168
> >  ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mxs/mach-mxs.c    
> >  |    3 +
> >  2 files changed, 171 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx28-sps1.dts
> > 
> > diff --git a/arch/arm/boot/dts/imx28-sps1.dts
> > b/arch/arm/boot/dts/imx28-sps1.dts new file mode 100644
> > index 0000000..d05b1cb
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx28-sps1.dts
> > @@ -0,0 +1,168 @@
> > +/*
> > + * Copyright (C) 2012 Marek Vasut <marex at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "imx28.dtsi"
> > +
> > +/ {
> > +	model = "SchulerControl GmbH, SC SPS 1";
> > +	compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
> 
> We should use the short name as prefix if it has one.
> 
> > +
> > +	memory {
> > +		reg = <0x40000000 0x08000000>;
> > +	};
> > +
> > +	apb at 80000000 {
> > +		apbh at 80000000 {
> > +			pinctrl at 80018000 {
> > +				led_pins_sps1: leds at 0 {
> 
> It should be referenced by the pinctrl state directly under node
> pinctrl at 80018000, otherwise the pins will not be set up.
> 
> Also we usually use a generic name here something like
> 
> 				hog_pins_a: hog at 0 {
> 
> so that we do not need to create new node every time we add pins
> for a new module.

So I'll ignore this comment and add pinctrl call into leds-gpio ... can we agree 
on that ?

[...]


From shawn.guo at linaro.org  Sat Aug 25 09:03:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 25 Aug 2012 21:03:53 +0800
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <201208251435.52411.marex@denx.de>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-4-git-send-email-marex@denx.de>
 <20120825083042.GM31998@S2101-09.ap.freescale.net>
 <201208251435.52411.marex@denx.de>
Message-ID: <20120825130346.GO31998@S2101-09.ap.freescale.net>

On Sat, Aug 25, 2012 at 02:35:52PM +0200, Marek Vasut wrote:
> So I'll ignore this comment and add pinctrl call into leds-gpio ... can we agree 
> on that ?
> 
I'm fine.  But I have to postpone this part of dts change until I see
the driver part gets accepted.

-- 
Regards,
Shawn


From mikpe at it.uu.se  Sat Aug 25 09:01:33 2012
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Sat, 25 Aug 2012 15:01:33 +0200
Subject: [3.6-rc3 regression] sata_mv cannot get optional clkdev breaking boot
 on QNAP TS-119P+
Message-ID: <20536.52397.140042.917795@pilspetsen.it.uu.se>

My Kirkwood-based QNAP TS-119P+ boots fine with the 3.5 kernel.  With
3.6-rc2 and 3.6-rc3 however sata_mv complains:

sata_mv sata_mv.0: cannot get optional clkdev
sata_mv sata_mv.0: slots 32 ports 2

and then the kernel grinds to a halt with no further messages.

Full boot log from 3.6-rc3 appended below.  .config available upon
request, but this is a non-DT kernel.

/Mikael

Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0
Linux version 3.6.0-rc3 (mikpe at hallertau) (gcc version 4.6.4 20120706 (prerelease) (GCC) ) #1 Sat Aug 25 14:43:24 CEST 2012
CPU: Feroceon 88FR131 [56251311] revision 1 (ARMv5TE), cr=00053977
CPU: VIVT data cache, VIVT instruction cache
Machine: QNAP TS-119/TS-219
Ignoring unrecognised tag 0x41000403
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyS0,115200n8 ro root=/dev/sda1
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 512MB = 512MB total
Memory: 515884k/515884k available, 8404k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    modules : 0xbf000000 - 0xc0000000   (  16 MB)
      .text : 0xc0008000 - 0xc0366000   (3448 kB)
      .init : 0xc0366000 - 0xc03844b8   ( 122 kB)
      .data : 0xc0386000 - 0xc03b32a0   ( 181 kB)
       .bss : 0xc03b32c4 - 0xc03c67c0   (  78 kB)
NR_IRQS:114
sched_clock: 32 bits at 200MHz, resolution 5ns, wraps every 21474ms
Console: colour dummy device 80x30
Calibrating delay loop... 1587.60 BogoMIPS (lpj=7938048)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
Setting up static identity map for 0x2961e8 - 0x296224
devtmpfs: initialized
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
Kirkwood: MV88F6282-Rev-A0, TCLK=200000000.
Feroceon L2: Enabling L2
Feroceon L2: Cache support initialised.
Kirkwood PCIe port 0: 
link down, ignoring
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource orion_clocksource
NET: Registered protocol family 2
TCP established hash table entries: 16384 (order: 5, 131072 bytes)
TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
msgmni has been set to 1007
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
mv_xor_shared mv_xor_shared.0: Marvell shared XOR driver
mv_xor_shared mv_xor_shared.1: Marvell shared XOR driver
mv_xor mv_xor.0: Marvell XOR: ( xor cpy )
mv_xor mv_xor.1: Marvell XOR: ( xor fill cpy )
mv_xor mv_xor.2: Marvell XOR: ( xor cpy )
mv_xor mv_xor.3: Marvell XOR: ( xor fill cpy )
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
console [ttyS0] enabled
serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 34) is a 16550A
loop: module loaded
sata_mv sata_mv.0: cannot get optional clkdev
sata_mv sata_mv.0: slots 32 ports 2


From carlo_bastelli at yahoo.it  Sat Aug 25 10:06:34 2012
From: carlo_bastelli at yahoo.it (Bastelli Carlo)
Date: Sat, 25 Aug 2012 16:06:34 +0200
Subject: SLAVE Side SPI kernel driver development
References: <1345820228.87750.YahooMailNeo@web29604.mail.ird.yahoo.com>
 <5037B1DF.40503@whoi.edu> <000f01cd8295$bd728770$0702a8c0@spectrekizxcpt>
 <201208251344.10746.marex@denx.de>
Message-ID: <000301cd82ca$d80e4170$0702a8c0@spectrekizxcpt>

I will use an ARM processor from Atmel, do not yet know the exact model, but 
I know for a fact that the SPI controller included in their ARM processor 
supports slave mode. When I have more details on the hardware used will not 
forget to update the forum.

Thanks & Regards

Carlo Bastelli

----- Original Message ----- 
From: "Marek Vasut" <marek.vasut at gmail.com>
To: "Bastelli Carlo" <carlo_bastelli at yahoo.it>
Cc: "Ned Forrester" <nforrester at whoi.edu>; "Fabio Estevam" 
<festevam at gmail.com>; <spi-devel-general at lists.sourceforge.net>; 
<linux-kernel at vger.kernel.org>; <linux-arm-kernel at lists.infradead.org>
Sent: Saturday, August 25, 2012 1:44 PM
Subject: Re: SLAVE Side SPI kernel driver development


Dear Bastelli Carlo,

> In my application in fact the slave is connected to the master without
> other devices on the bus, a simple point to point, and receives a frame of
> known dimensions.

What hardware do you use? What CPU is it?

> I think I will be very busy to read post in the coming days  :)

Good luck with that.

> Thanks to all of you who provided suggestions.
> Carlo Bastelli
>
> ----- Original Message -----
> From: "Ned Forrester" <nforrester at whoi.edu>
> To: "Marek Vasut" <marex at denx.de>
> Cc: "Fabio Estevam" <festevam at gmail.com>;
> <spi-devel-general at lists.sourceforge.net>; "Bastelli Carlo (yahoo)"
> <carlo_bastelli at yahoo.it>; <linux-kernel at vger.kernel.org>;
> <linux-arm-kernel at lists.infradead.org>
> Sent: Friday, August 24, 2012 6:54 PM
> Subject: Re: SLAVE Side SPI kernel driver development
>
> On 08/24/2012 11:38 AM, Marek Vasut wrote:
> > Dear Fabio Estevam,
> >
> >> On Fri, Aug 24, 2012 at 11:57 AM, Bastelli Carlo (yahoo)
> >
> > CCing SPI list
> >
> >> <carlo_bastelli at yahoo.it> wrote:
> >>> Hello, I'm Carlo, I have a difficult task at work, my boss asked me to
> >>> develop
> >>>
> >>>  a driver SPI slave side on embedded ARM processor running Linux.
> >>>
> >>> Precisely linux occur on the SPI bus as a slave, not master as 
> >>> required
> >>> by the hierarchical structure of the current kernel. The new driver
> >>> will
> >>>
> >>>  receive via interrupt and respond when selected by its chip select.
> >
> > So a soft-spi ? It's gonna be slow as hell and unstable too.
> >
> >>>  Can
> >>>  anyone suggest the best way to develop this driver?
> >
> > Get a CPU which has SPI-slave capable IP, start from there. If you were
> > to implement soft-spi this way, you'd have to use FIQ on ARM, to be able
> > to handle
> > stuff with reasonable latency ... check how the ps/2-gpio driver is done
> > in
> > Linux ... I tried it, it barely worked, you don't want to go down that
> > road.
> >
> >>>  Personally, I
> >>>
> >>> have identified two main roads, the first if possible to exploit the
> >>> structure SPI master driver
> >
> > Not happening. You'd have to split the parts from the struct spi_master
> > into
> > common and master-only parts. That's for starters.
> >
> >>> with a few tricks that now I can not
> >>> define. The second most radical, write a driver for a UART like, but
> >>> managing the SPI device.
> >>> Thank you for any suggestions or examples.
> >
> > First of all, the SPI slave mode is COMPLETELY different from the master
> > mode.
> > You need to react on incoming CS-low ASAP, which might turn out to be a
> > problem
> > on it's own. Then, even if you do, you do not know how long the transfer
> > is
> > going to be, so you need to allocate enough buffers as the transfer
> > progresses
> > onwards.
> >
> > In case of your soft-spi, how do you plan to sample the CLK line to sync
> > clock?
> >
> >> Marek got spi slave running on a mx28. See his patch:
> >> http://www.spinics.net/lists/arm-kernel/msg190860.html
> >
> > This was tested (and developed) on this board:
> > http://www.denx-cs.de/?q=M28
> >
> > The userland code is really easy too, simply pump it into spidev or read
> > from
> > it. But all that is only possible because of the SPI IP in the mx28 is
> > nice.
> >
> >> Regards,
> >>
> >> Fabio Estevam
> >
> > Best regards,
> > Marek Vasut
>
> I generally agree with the above comments.  A generalized SPI slave must
> be able to respond instantly, often within one clock cycle.  This can
> only work in hardware, or in an OS like Linux when the activity on the
> bus is completely predictable by the Linux slave.  The only cases I know
> of are streaming of data in a predictable way between a single master
> and single slave (no other devices on the bus).
>
> This topic comes up periodically, but I don't think there has been any
> change in the situation for all the time I've followed the discussion.
> I recommend that you read the archives of this mailing list to
> understand the limitations of a potential slave mode.  The archives can
> be found at:
>
> http://sourceforge.net/mailarchive/forum.php?forum_name=spi-devel-general
>
> then look for threads with "slave" in the subject in the following
> months (I'd give thread start dates, but parts of the threads are
> disconnected in the archives, and this is the easiest way to see all the
> parts, day ranges are in parentheses):
>
> 2007/04 (13-18)
> 2007/09/27 and 2007/10 (13-17)
> 2009/03 (2-3)
> 2009/12/18 and 2010/1/19 and 2010/02 (14-16)
> 2010/07 (26) and 2010/08 (13)
> 2011/01 (28-31) and 2011/02 (1-10)
> 2011/10 (18)
> 2012/06 (29-30 and 2012/07 (1-17)

Best regards,
Marek Vasut 



From andrew at lunn.ch  Sat Aug 25 11:15:24 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 25 Aug 2012 17:15:24 +0200
Subject: [3.6-rc3 regression] sata_mv cannot get optional clkdev breaking
 boot on QNAP TS-119P+
In-Reply-To: <20536.52397.140042.917795@pilspetsen.it.uu.se>
References: <20536.52397.140042.917795@pilspetsen.it.uu.se>
Message-ID: <20120825151524.GH9886@lunn.ch>

On Sat, Aug 25, 2012 at 03:01:33PM +0200, Mikael Pettersson wrote:
> My Kirkwood-based QNAP TS-119P+ boots fine with the 3.5 kernel.  With
> 3.6-rc2 and 3.6-rc3 however sata_mv complains:
> 
> sata_mv sata_mv.0: cannot get optional clkdev
> sata_mv sata_mv.0: slots 32 ports 2
> 
> and then the kernel grinds to a halt with no further messages.
> 
> Full boot log from 3.6-rc3 appended below.  .config available upon
> request, but this is a non-DT kernel.

Hi Mikael

This is a known issue. See:

http://comments.gmane.org/gmane.linux.ports.arm.kernel/181989

There are patches being developed to fix this. I hope we can push them
to an RC soon.

   Andrew


From mikpe at it.uu.se  Sat Aug 25 11:41:08 2012
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Sat, 25 Aug 2012 17:41:08 +0200
Subject: [3.6-rc3 regression] sata_mv cannot get optional clkdev breaking
 boot on QNAP TS-119P+
In-Reply-To: <20120825151524.GH9886@lunn.ch>
References: <20536.52397.140042.917795@pilspetsen.it.uu.se>
 <20120825151524.GH9886@lunn.ch>
Message-ID: <20536.61972.508189.308675@pilspetsen.it.uu.se>

Andrew Lunn writes:
 > On Sat, Aug 25, 2012 at 03:01:33PM +0200, Mikael Pettersson wrote:
 > > My Kirkwood-based QNAP TS-119P+ boots fine with the 3.5 kernel.  With
 > > 3.6-rc2 and 3.6-rc3 however sata_mv complains:
 > > 
 > > sata_mv sata_mv.0: cannot get optional clkdev
 > > sata_mv sata_mv.0: slots 32 ports 2
 > > 
 > > and then the kernel grinds to a halt with no further messages.
 > > 
 > > Full boot log from 3.6-rc3 appended below.  .config available upon
 > > request, but this is a non-DT kernel.
 > 
 > Hi Mikael
 > 
 > This is a known issue. See:
 > 
 > http://comments.gmane.org/gmane.linux.ports.arm.kernel/181989
 > 
 > There are patches being developed to fix this. I hope we can push them
 > to an RC soon.

Thanks for the pointer.  Aaro Koskinen's suggestion of passing
coherent_pool=1M to the kernel allowed it to boot successfully.
I'll use that workaround for now.

/Mikael


From sebastian.hesselbarth at gmail.com  Sat Aug 25 11:53:50 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Sat, 25 Aug 2012 17:53:50 +0200
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <5036F651.4020700@wwwdotorg.org>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org> <50369305.6050304@gmail.com>
 <50369FEE.8000003@wwwdotorg.org> <5036B639.20608@gmail.com>
 <5036F651.4020700@wwwdotorg.org>
Message-ID: <5038F50E.7030807@gmail.com>

On 08/24/2012 05:34 AM, Stephen Warren wrote:
> On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
>> So possible, valid combinations for uart1 would be:
>> (a) mpp_uart1;
>> (b) mpp_uart1, mpp2, mpp3;
>> (c) mpp_uart1, mpp21, mpp22;
>> (d) mpp_uart1, mpp2, mpp22;
>> (e) mpp_uart1, mpp21, mpp3;
>>  [...]
> In the example above, there is a single function named "uart1". If this
> was all the HW supported, I'd expect the driver's
> pinmux_ops.get_functions_count() to return 1,
> pinmux_ops.get_function_name(0) to return "uart1", and
> pinmux_ops.get_function_name(n>0) to return an error.
>
> In practice, I assume there are many other options that can be muxed
> onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
>
> I don't expect any scanning, no. I'd expect that tables provided by the
> SoC-specific drivers to be:
>
> * A table of pins
> * A table of groups
> * A table of functions
>
> No scanning involved.

Stephen,

now I do understand but in the current driver we pass pingroups associated
with the available functions, i.e. "mpp2" with "uart1", "uart2", "sdio0", aso.
IMHO for the above three functions it would be better to have functions associated
with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2", "mpp3", aso.

That would require some larger rework of the driver and therefore I just
wanted to make sure, that I hit your expectations/explanations.

Sebastian


From rabin at rab.in  Sat Aug 25 15:23:33 2012
From: rabin at rab.in (Rabin Vincent)
Date: Sat, 25 Aug 2012 21:23:33 +0200
Subject: For physical memory management, why take holes page as free pages?
In-Reply-To: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>
References: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>
Message-ID: <CAH+eYFCUOVnc81jLkDafN-9qzy+B66DWQ4zvdj7tzjeN=OS0nA@mail.gmail.com>

2012/8/25 Li Haifeng <omycle at gmail.com>:
> Sorry to disturb you. When I study memory management of boot_mem, I
> have question about 505~506 lines below code for initialization of
> physical memory management. The function of these two lines is to make
> the holes between adjacent bank free in node_bootmem_map of
> corresponding node, which is a bitmap.

What's being freed here is the unused parts of the mem_map array, i.e.
those parts which would have held the struct page structures which cover
the pages in the memory holes.

> IMO, the holes between two bank should be marked reserved in page
> bitmap, because it couldn't be used for allocating memory in buddy
> system.

The pages in the memory holes are simply never released to the page
allocator, and are therefore never available for allocation in the buddy
system.  This code frees the holes in the mem_map array itself.


From broonie at opensource.wolfsonmicro.com  Sat Aug 25 16:25:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 25 Aug 2012 13:25:16 -0700
Subject: [PATCH] ASoC: atmel-ssc: include linux/io.h for raw io
In-Reply-To: <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
References: <20120823152324.GI7995@opensource.wolfsonmicro.com>
 <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20120825202515.GF6520@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 06:14:54PM +0200, Nicolas Ferre wrote:
> From: Joachim Eastwood <manabian at gmail.com>
> 
> Include linux/io.h for raw io operations in atmel-scc header.
> 
> This fixes the following build error:
>   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
> sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
> sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

but why not just apply it to the ASoC tree?


From heiko at sntech.de  Sat Aug 25 17:53:59 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Sat, 25 Aug 2012 23:53:59 +0200
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
Message-ID: <201208252353.59345.heiko@sntech.de>

Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
via the device tree. This patch implements dt-support for the
s3c24xx arches.

The controllers contain only 3 cells, as the underlying gpio controller
does not support controlling the drive strength on a gpio level.

Tested with the gpio-keys driver on a s3c2416 based machine.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 .../devicetree/bindings/gpio/gpio-samsung.txt      |   38 ++++++++++++
 drivers/gpio/gpio-samsung.c                        |   63 ++++++++++++++++++++
 2 files changed, 101 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625..ce6a7d4 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,41 @@ Example:
 		#gpio-cells = <4>;
 		gpio-controller;
 	};
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [flags and pull up/down]
+
+  Values for gpio specifier:
+  - Pin number: depending on the controller a number from 0 up to 15.
+  - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
+                            1 - Pull Down Enabled.
+                            3 - Pull Up Enabled.
+          Bit 16 (0x00010000) - Input is active low.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+	gpa: gpio-controller at 56000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "samsung,s3c24xx-gpio";
+		reg = <0x56000000 0x10>;
+		#gpio-cells = <3>;
+		gpio-controller;
+	};
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a150d2e..80a2817 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
 		s3c_gpiolib_track(chip);
 }
 
+#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+			const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	unsigned int pin;
+
+	if (WARN_ON(gc->of_gpio_n_cells < 3))
+		return -EINVAL;
+
+	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+		return -EINVAL;
+
+	if (gpiospec->args[0] > gc->ngpio)
+		return -EINVAL;
+
+	pin = gc->base + gpiospec->args[0];
+
+	if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
+		pr_warn("gpio_xlate: failed to set pin function\n");
+	if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
+		pr_warn("gpio_xlate: failed to set pin pull up/down\n");
+
+	if (flags)
+		*flags = gpiospec->args[2] >> 16;
+
+	return gpiospec->args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+	{ .compatible = "samsung,s3c24xx-gpio", },
+	{}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+						 u64 base, u64 offset)
+{
+	struct gpio_chip *gc =  &chip->chip;
+	u64 address;
+
+	if (!of_have_populated_dt())
+		return;
+
+	address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
+	gc->of_node = of_find_matching_node_by_address(NULL,
+			s3c24xx_gpio_dt_match, address);
+	if (!gc->of_node) {
+		pr_info("gpio: device tree node not found for gpio controller"
+			" with base address %08llx\n", address);
+		return;
+	}
+	gc->of_gpio_n_cells = 3;
+	gc->of_xlate = s3c24xx_gpio_xlate;
+}
+#elif defined(CONFIG_PLAT_S3C24XX)
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+						 u64 base, u64 offset)
+{
+	return;
+}
+#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
+
 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
 					     int nr_chips, void __iomem *base)
 {
@@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
 			gc->direction_output = samsung_gpiolib_2bit_output;
 
 		samsung_gpiolib_add(chip);
+
+		s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
 	}
 }
 
-- 
1.7.2.3



From weiyj.lk at gmail.com  Sat Aug 25 21:43:00 2012
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Sun, 26 Aug 2012 09:43:00 +0800
Subject: [PATCH] usb: gadget: remove duplicated include from pxa25x_udc.c
Message-ID: <CAPgLHd-CLDf3ki+fX8P_QRLu8ErCQpGbywM2z5SE4xJp6XpePA@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 drivers/usb/gadget/pxa25x_udc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 907ad3e..c246c08 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -33,7 +33,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
-#include <linux/err.h>
 #include <linux/seq_file.h>
 #include <linux/debugfs.h>
 #include <linux/io.h>



From weiyj.lk at gmail.com  Sat Aug 25 21:48:11 2012
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Sun, 26 Aug 2012 09:48:11 +0800
Subject: [PATCH] ARM i.MX: remove duplicated include from clk-imx21.c
Message-ID: <CAPgLHd_pYM3otnZBZ=nz7aYTP4dorBSjQtj=x9Z+zz7yr1NgSg@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/mach-imx/clk-imx21.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61..cf65148 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -23,7 +23,6 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 #include <linux/err.h>
 
 #include <mach/hardware.h>



From weiyj.lk at gmail.com  Sat Aug 25 21:48:39 2012
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Sun, 26 Aug 2012 09:48:39 +0800
Subject: [PATCH] ARM: LPC32xx: remove duplicated include from phy3250.c
Message-ID: <CAPgLHd972bujPnZ-Pj_a13gychY+z3SVag4tLaxqZh+2kuh+dQ@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/mach-lpc32xx/phy3250.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b07dcc9..ed0a50d 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -23,7 +23,6 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
-#include <linux/device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
 #include <linux/gpio.h>



From weiyj.lk at gmail.com  Sat Aug 25 21:49:34 2012
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Sun, 26 Aug 2012 09:49:34 +0800
Subject: [PATCH] ARM: mxs: remove duplicated include from mach-mxs.c
Message-ID: <CAPgLHd_QDRHKBybnCtD_K-JJvJG_f4x6wTXczQZqraiLch4wEg@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/mach-mxs/mach-mxs.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8dabfe8..5c91870 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -14,7 +14,6 @@
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/init.h>
-#include <linux/init.h>
 #include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>



From weiyj.lk at gmail.com  Sat Aug 25 21:49:58 2012
From: weiyj.lk at gmail.com (Wei Yongjun)
Date: Sun, 26 Aug 2012 09:49:58 +0800
Subject: [PATCH] ARM: mach-shmobile: remove duplicated include from
 board-ag5evm.c
Message-ID: <CAPgLHd_LaGpVqgWa-5EfYbkmjuM_rhT47y2-z6E3ExZ8Rmw4vw@mail.gmail.com>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
---
 arch/arm/mach-shmobile/board-ag5evm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d82c010..cfc3b5c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,7 +40,6 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
-#include <linux/videodev2.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>



From shawn.guo at linaro.org  Sat Aug 25 22:13:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 26 Aug 2012 10:13:58 +0800
Subject: [PATCH] ARM: mxs: remove duplicated include from mach-mxs.c
In-Reply-To: <CAPgLHd_QDRHKBybnCtD_K-JJvJG_f4x6wTXczQZqraiLch4wEg@mail.gmail.com>
References: <CAPgLHd_QDRHKBybnCtD_K-JJvJG_f4x6wTXczQZqraiLch4wEg@mail.gmail.com>
Message-ID: <CAAQ0ZWTLES1DtDEaYuhfHZOd-5UUje6xOj06O-GDcHBk4GSgUg@mail.gmail.com>

On 26 August 2012 09:49, Wei Yongjun <weiyj.lk at gmail.com> wrote:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
>
> Remove duplicated include.
>
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Thanks for the patch.  But the duplicated inclusion has been fixed on
branch below, which is queued for 3.7.

 git://git.linaro.org/people/shawnguo/linux-2.6.git mxs/dt-for-3.7

Regards,
Shawn

> ---
>  arch/arm/mach-mxs/mach-mxs.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> index 8dabfe8..5c91870 100644
> --- a/arch/arm/mach-mxs/mach-mxs.c
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -14,7 +14,6 @@
>  #include <linux/clkdev.h>
>  #include <linux/err.h>
>  #include <linux/init.h>
> -#include <linux/init.h>
>  #include <linux/irqdomain.h>
>  #include <linux/micrel_phy.h>
>  #include <linux/mxsfb.h>
>


From anton.vorontsov at linaro.org  Sun Aug 26 00:24:40 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 25 Aug 2012 21:24:40 -0700
Subject: [PATCH 0/9] Get rid of FIQ_START/enable/disable_fiq() + some FIQ
 cleanups
In-Reply-To: <20120805230238.GA1663@lizard>
References: <20120805230238.GA1663@lizard>
Message-ID: <20120826042437.GA26164@lizard>

Hello Russell,

On Sun, Aug 05, 2012 at 04:02:38PM -0700, Anton Vorontsov wrote:
> During KDB FIQ patches review you mentioned that I should not introduce
> another FIQ_START. It seems that in v3.6-rc the FIQ_START issue was
> somewhat band-aided, i.e. machines don't necessary need to define this
> stuff any longer, but I also read the background of the issue, and you
> once said that you don't want the FIQ subsystem to mess with genirq.

Just wonder if you had a chance to look into this patch set...

Plus, I also realized that maybe it's a good time to get rid of
init_FIQ() altogether? Maybe there are some not so obvious reasons for
its existence, but if not, does the following patch on top of this
series makes sense?

(Also, I noticed that we save no_fiq_insn w/o bothering about
!CONFIG_CPU_USE_DOMAINS case, but set_fiq_handler() has a special
handling for this. I wonder, was that on purpose, e.g. it does not
matter for init_FIQ(), or it was just overlooked? In latter case,
the patch fixes the issue.)

- - - -
[PATCH] ARM: FIQ: Get rid of init_FIQ()

The function only saves initial arch-specific "no FIQ" instruction,
by placing the code into set_fiq_handler() we can:

- Have less code and logic in the platform-specific files;
- Have the code that manages FIQ vector overwriting in one place, i.e.
  not spread the logic around (both code placement wise and execution
  time wise).

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/include/asm/mach/irq.h |  2 --
 arch/arm/kernel/fiq.c           | 17 ++++++++---------
 arch/arm/mach-rpc/irq.c         |  2 --
 arch/arm/plat-mxc/avic.c        |  3 ---
 arch/arm/plat-mxc/tzic.c        |  3 ---
 arch/arm/plat-s3c24xx/irq.c     |  2 --
 6 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 8be5ba9..6e70ae3 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -18,10 +18,8 @@ struct seq_file;
  * This is internal.  Do not use it.
  */
 #ifdef CONFIG_FIQ
-extern void init_FIQ(void);
 extern void show_fiq_list(struct seq_file *, int);
 #else
-static inline void init_FIQ(void) {}
 static inline void show_fiq_list(struct seq_file *p, int prec) {}
 #endif
 
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 9bf3a60..3602df6 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -49,6 +49,7 @@
 #include <asm/mach/irq.h>
 
 static unsigned long no_fiq_insn;
+static int got_no_fiq_insn;
 
 /* Default reacquire function
  * - we always relinquish FIQ control
@@ -78,11 +79,14 @@ void show_fiq_list(struct seq_file *p, int prec)
 
 void set_fiq_handler(void *start, unsigned int length)
 {
-#if defined(CONFIG_CPU_USE_DOMAINS)
-	memcpy((void *)0xffff001c, start, length);
-#else
-	memcpy(vectors_page + 0x1c, start, length);
+	unsigned long *addr = (void *)0xffff001c;
+
+#ifndef CONFIG_CPU_USE_DOMAINS
+	addr = vectors_page + 0x1c;
 #endif
+	if (!cmpxchg(&got_no_fiq_insn, 0, 1))
+		no_fiq_insn = *addr;
+	memcpy(addr, start, length);
 	flush_icache_range(0xffff001c, 0xffff001c + length);
 	if (!vectors_high())
 		flush_icache_range(0x1c, 0x1c + length);
@@ -126,8 +130,3 @@ EXPORT_SYMBOL(__set_fiq_regs);	/* defined in fiqasm.S */
 EXPORT_SYMBOL(__get_fiq_regs);	/* defined in fiqasm.S */
 EXPORT_SYMBOL(claim_fiq);
 EXPORT_SYMBOL(release_fiq);
-
-void __init init_FIQ(void)
-{
-	no_fiq_insn = *(unsigned long *)0xffff001c;
-}
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 07770c8..2d915ba 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -151,7 +151,5 @@ void __init rpc_init_irq(void)
 			break;
 		}
 	}
-
-	init_FIQ();
 }
 
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 426980c..b173dc6 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -216,8 +216,5 @@ void __init mxc_init_irq(void __iomem *irqbase)
 	for (i = 0; i < 8; i++)
 		__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-	/* Initialize FIQ */
-	init_FIQ();
-
 	printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 8a5a633..889267c 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -191,9 +191,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
 	for (i = 0; i < 4; i++, irq_base += 32)
 		tzic_init_gc(i, irq_base);
 
-	/* Initialize FIQ */
-	init_FIQ();
-
 	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 531d6a4..66b8856 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -532,8 +532,6 @@ void __init s3c24xx_init_irq(void)
 	int irqno;
 	int i;
 
-	init_FIQ();
-
 	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
 
 	/* first, clear all interrupts pending... */
-- 
1.7.11.5



From omycle at gmail.com  Sun Aug 26 00:29:13 2012
From: omycle at gmail.com (Li Haifeng)
Date: Sun, 26 Aug 2012 12:29:13 +0800
Subject: For physical memory management, why take holes page as free pages?
In-Reply-To: <CAH+eYFCUOVnc81jLkDafN-9qzy+B66DWQ4zvdj7tzjeN=OS0nA@mail.gmail.com>
References: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>
 <CAH+eYFCUOVnc81jLkDafN-9qzy+B66DWQ4zvdj7tzjeN=OS0nA@mail.gmail.com>
Message-ID: <CAFNq8R7w7nFSoR1S=r0_Uo3wvKzCALCFgC_TB9Vi_aSuuLwC+g@mail.gmail.com>

Thanks for your attention.

2012/8/26 Rabin Vincent <rabin at rab.in>:
> 2012/8/25 Li Haifeng <omycle at gmail.com>:
>> Sorry to disturb you. When I study memory management of boot_mem, I
>> have question about 505~506 lines below code for initialization of
>> physical memory management. The function of these two lines is to make
>> the holes between adjacent bank free in node_bootmem_map of
>> corresponding node, which is a bitmap.
>
> What's being freed here is the unused parts of the mem_map array, i.e.
> those parts which would have held the struct page structures which cover
> the pages in the memory holes.

I understand, but also confused. More seriously, mem_map array is a
obsoleted comment in the code, right? It really means node_bootmem_map
of a memory node, and it 's a bitmap, which a bit indicated a
page,right?

But the code free the holes between banks. For example, a soc have two
banks, one is [0x800000~0x10000000], the other is
[0x10800000~0x20000000].

>From the code, it set bit 0 in node_bootmem_map for range
[0x10000000~0x10800000]. And when initialize the buddy system, the bit
0 in node_bootmem_map will be looked as free page and be available for
allocation in buddy system.

Maybe I misunderstand the code.

>
>> IMO, the holes between two bank should be marked reserved in page
>> bitmap, because it couldn't be used for allocating memory in buddy
>> system.
>
> The pages in the memory holes are simply never released to the page
> allocator, and are therefore never available for allocation in the buddy
> system.  This code frees the holes in the mem_map array itself.

Yes, I also agree this point. But I am still confused with the code.

Thanks for your attention again.


From arnd at arndb.de  Sun Aug 26 00:41:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 Aug 2012 04:41:25 +0000
Subject: [GIT PULL] ARM: mach-pnx4008: Remove architecture
In-Reply-To: <50378084.3080102@antcom.de>
References: <1345724548-18130-1-git-send-email-stigge@antcom.de>
 <50378084.3080102@antcom.de>
Message-ID: <201208260441.25905.arnd@arndb.de>

On Friday 24 August 2012, Roland Stigge wrote:
> On 23/08/12 14:22, Roland Stigge wrote:
> > This patch removes the ARM architecture mach-pnx4008. No direct support or user
> > feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
> > maintainers.
> > 
> > Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> The patch was a bit too big for the mailing list - sorry.
> 
> Now re-proposing via pull request, below.

I think the removal of the frame buffer driver should go separately via the
framebuffer maintainer (Florian Schandinat), I can take the rest through the
arm-soc tree.

	Arnd


From arnd at arndb.de  Sun Aug 26 00:47:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 Aug 2012 04:47:58 +0000
Subject: [PATCH 1/4] clk: ux500: Adapt PRCMU and PRCC clocks for common clk
In-Reply-To: <1345807565-7729-2-git-send-email-ulf.hansson@stericsson.com>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
 <1345807565-7729-2-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <201208260447.58396.arnd@arndb.de>

On Friday 24 August 2012, Ulf Hansson wrote:
> From: Ulf Hansson <ulf.hansson at linaro.org>
> 
> First version of common clock implementation of PRCMU clocks
> and PRCC clocks for ux500 platforms.
> 
> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>

Very nice, glad to see you got this working!

I only noticed one thing that you should improve:

> +#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
> +
> +struct clk_prcc {
> +	struct clk_hw hw;
> +	unsigned int io_base;
> +	u32 cg_sel;
> +	int is_enabled;
> +};
> +
> +/* PRCC clock operations. */
> +
> +static int clk_prcc_pclk_enable(struct clk_hw *hw)
> +{
> +	struct clk_prcc *clk = to_clk_prcc(hw);
> +	void __iomem *io_base = __io_address(clk->io_base);

In a proper device driver, we should not use hacks like __io_address. Please
change the driver to ioremap the register area at initialization time, and
don't pass a physical io_base like above but instead pass an offset into
the register area.

	Arnd


From arnd at arndb.de  Sun Aug 26 00:49:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 Aug 2012 04:49:32 +0000
Subject: [PATCH v2 21/31] arm64: 32-bit (compat) applications support
In-Reply-To: <20120824104338.GI7585@arm.com>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de> <20120824104338.GI7585@arm.com>
Message-ID: <201208260449.32807.arnd@arndb.de>

On Friday 24 August 2012, Catalin Marinas wrote:
> > What good is the run-time BUG() here? Nothing should be calling these
> > when CONFIG_COMPAT is disabled, so I think you should just remove
> > the #ifdef around the declarations, and the entire #else case.
> 
> They are called from handle_signal(), so that's to avoid #ifdef inside
> functions. I can drop the BUG() (but keep the empty function) and
> change the checks to is_compat_task() so that the compiler optimises the
> condition out when !COMPAT.
> 

Sounds good. Note that you can turn a lot of #ifdef into
if(IS_ENABLED(CONFIG_FOO)) as well, even if there is no other runtime
check for them.

	Arnd


From sangsu4u.park at samsung.com  Sun Aug 26 04:04:37 2012
From: sangsu4u.park at samsung.com (=?ks_c_5601-1987?B?udq787z2?=)
Date: Sun, 26 Aug 2012 17:04:37 +0900
Subject: ASoC: SAMSUNG: Change Kconfig to support all EXYNOSs
Message-ID: <003001cd8361$7016a110$5043e330$@samsung.com>

All EXYNOSs use SND_SOC_SAMSUNG configuration.
This patch change Kconfig to support all EXYNOSs like EXYNOS4 and EXYNOS5.

Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>
---
 sound/soc/samsung/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index f17dd25..9e64ae6 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,6 +1,6 @@
 config SND_SOC_SAMSUNG
 	tristate "ASoC support for Samsung"
-	depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 ||
ARCH_EXYNOS4
+	depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 ||
ARCH_EXYNOS
 	select S3C64XX_DMA if ARCH_S3C64XX
 	select S3C2410_DMA if ARCH_S3C24XX
 	help
-- 
1.7.1



From linux at arm.linux.org.uk  Sun Aug 26 04:40:49 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 26 Aug 2012 09:40:49 +0100
Subject: For physical memory management, why take holes page as free pages?
In-Reply-To: <CAFNq8R7w7nFSoR1S=r0_Uo3wvKzCALCFgC_TB9Vi_aSuuLwC+g@mail.gmail.com>
References: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>
 <CAH+eYFCUOVnc81jLkDafN-9qzy+B66DWQ4zvdj7tzjeN=OS0nA@mail.gmail.com>
 <CAFNq8R7w7nFSoR1S=r0_Uo3wvKzCALCFgC_TB9Vi_aSuuLwC+g@mail.gmail.com>
Message-ID: <20120826084049.GK18957@n2100.arm.linux.org.uk>

On Sun, Aug 26, 2012 at 12:29:13PM +0800, Li Haifeng wrote:
> I understand, but also confused. More seriously, mem_map array is a
> obsoleted comment in the code, right? It really means node_bootmem_map
> of a memory node, and it 's a bitmap, which a bit indicated a
> page,right?

No.  You're confusing two things - the bootmem bitmap array, and the
mem_map array, which is an array of "struct page"s.  One struct page
exists per page, where each struct page is normally around 32 bytes.
So one 4K page of struct pages is 128 entries in the map, which covers
512kB of memory.

Take the case where you have a hole of 128MB between your memory banks.
That's 256 pages of unused page structures, or a total of 1MB of memory
consumed by unused page structures.


From sangsu4u.park at samsung.com  Sun Aug 26 04:45:54 2012
From: sangsu4u.park at samsung.com (=?ks_c_5601-1987?B?udq787z2?=)
Date: Sun, 26 Aug 2012 17:45:54 +0900
Subject: [PATCH] ASoC: SAMSUNG: Add SND_SOC_DAIFMT_CONT option for
 snd_soc_set_fmt()
Message-ID: <003101cd8367$3476e650$9d64b2f0$@samsung.com>

SND_SOC_DAIFMT_CONT option is now needed because of below commit:

ASoC: Allow DAI formats to be specified in the dai_link

Otherwise, s3c_pcm_set_fmt() returns -EINVAL.

Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>
---
 sound/soc/samsung/smdk_wm8994pcm.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/sound/soc/samsung/smdk_wm8994pcm.c b/sound/soc/samsung/smdk_wm8994pcm.c
index 77ecba9..cb88cbc 100644
--- a/sound/soc/samsung/smdk_wm8994pcm.c
+++ b/sound/soc/samsung/smdk_wm8994pcm.c
@@ -77,6 +77,7 @@ static int smdk_wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
 
 	/* Set the cpu DAI configuration */
 	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B
+				| SND_SOC_DAIFMT_CONT
 				| SND_SOC_DAIFMT_IB_NF
 				| SND_SOC_DAIFMT_CBS_CFS);
 	if (ret < 0)
-- 
1.7.1



From omycle at gmail.com  Sun Aug 26 05:06:35 2012
From: omycle at gmail.com (Li Haifeng)
Date: Sun, 26 Aug 2012 17:06:35 +0800
Subject: For physical memory management, why take holes page as free pages?
In-Reply-To: <20120826084049.GK18957@n2100.arm.linux.org.uk>
References: <CAFNq8R6FL3bVnht2b16zsCm82N+WyrobH3kXzXv3Z-YERfeudw@mail.gmail.com>
 <CAH+eYFCUOVnc81jLkDafN-9qzy+B66DWQ4zvdj7tzjeN=OS0nA@mail.gmail.com>
 <CAFNq8R7w7nFSoR1S=r0_Uo3wvKzCALCFgC_TB9Vi_aSuuLwC+g@mail.gmail.com>
 <20120826084049.GK18957@n2100.arm.linux.org.uk>
Message-ID: <CAFNq8R60JkNj-rHXUgb6J6tXyBBaMD-qRYwoFEHRA1uyvFsrCA@mail.gmail.com>

Thanks for your patience.

2012/8/26 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> On Sun, Aug 26, 2012 at 12:29:13PM +0800, Li Haifeng wrote:
>> I understand, but also confused. More seriously, mem_map array is a
>> obsoleted comment in the code, right? It really means node_bootmem_map
>> of a memory node, and it 's a bitmap, which a bit indicated a
>> page,right?
>
> No.  You're confusing two things - the bootmem bitmap array, and the
> mem_map array, which is an array of "struct page"s.  One struct page
> exists per page, where each struct page is normally around 32 bytes.
> So one 4K page of struct pages is 128 entries in the map, which covers
> 512kB of memory.

Yes. The key is mem_map. And I understand now.

Thanks very much again.

>
> Take the case where you have a hole of 128MB between your memory banks.
> That's 256 pages of unused page structures, or a total of 1MB of memory
> consumed by unused page structures.

Regards,
Haifeng Li


From omycle at gmail.com  Sun Aug 26 06:39:47 2012
From: omycle at gmail.com (Li Haifeng)
Date: Sun, 26 Aug 2012 18:39:47 +0800
Subject: For buddy system initialization, the holes between banks adjacent
 will be released to buddy allocator?
Message-ID: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>

Sorry to disturb you again.

I am still confused about holes between banks adjacent.

The lines 180~181 get the low memory's range, and the range includes holes.
But while releasing the memory to buddy allocator, the code doesn't
prevent the holes from releasing to the buddy allocator.

172 static unsigned long __init free_all_bootmem_core(bootmem_data_t *bdata)
173 {
174         struct page *page;
175         unsigned long start, end, pages, count = 0;
176
177         if (!bdata->node_bootmem_map)
178                 return 0;
179
180         start = bdata->node_min_pfn;
181         end = bdata->node_low_pfn;
182
183         bdebug("nid=%td start=%lx end=%lx\n",
184                 bdata - bootmem_node_data, start, end);
185
186         while (start < end) {
187                 unsigned long *map, idx, vec;
188
189                 map = bdata->node_bootmem_map;
190                 idx = start - bdata->node_min_pfn;
191                 vec = ~map[idx / BITS_PER_LONG];
192                 /*
193                  * If we have a properly aligned and fully unreserved
194                  * BITS_PER_LONG block of pages in front of us, free
195                  * it in one go.
196                  */
197                 if (IS_ALIGNED(start, BITS_PER_LONG) && vec == ~0UL) {
198                         int order = ilog2(BITS_PER_LONG);
199
200                         __free_pages_bootmem(pfn_to_page(start), order);
201                         count += BITS_PER_LONG;
202                         start += BITS_PER_LONG;
203                 } else {
204                         unsigned long off = 0;
205
206                         while (vec && off < BITS_PER_LONG) {
207                                 if (vec & 1) {
208                                         page = pfn_to_page(start + off);
209                                         __free_pages_bootmem(page, 0);
210                                         count++;
211                                 }
212                                 vec >>= 1;
213                                 off++;
214                         }
215                         start = ALIGN(start + 1, BITS_PER_LONG);
216                 }
217         }
218
219         page = virt_to_page(bdata->node_bootmem_map);
220         pages = bdata->node_low_pfn - bdata->node_min_pfn;
221         pages = bootmem_bootmap_pages(pages);
222         count += pages;
223         while (pages--)
224                 __free_pages_bootmem(page++, 0);
225
226         bdebug("nid=%td released=%lx\n", bdata - bootmem_node_data, count);
227
228         return count;
229 }


From thomas.abraham at linaro.org  Sun Aug 26 07:59:29 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 26 Aug 2012 17:29:29 +0530
Subject: [PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller clocks
In-Reply-To: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345982371-26483-2-git-send-email-thomas.abraham@linaro.org>

Add clock instances for bus interface unit clock and card interface unit
clock of the all four MSHC controller instances.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/clock-exynos5.c |   45 ++++++++++++----------------------
 1 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e29..16d8bef 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 19),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "biu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "biu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 13),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "biu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "biu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 15),
 	}, {
-		.name		= "dwmci",
-		.parent		= &exynos5_clk_aclk_200.clk,
-		.enable		= exynos5_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 16),
-	}, {
 		.name		= "sata",
 		.devname	= "ahci",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
@@ -1006,8 +1001,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "ciu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_dout_mmc0.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 0),
@@ -1017,8 +1012,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "ciu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_dout_mmc1.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 4),
@@ -1028,8 +1023,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "ciu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_dout_mmc2.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
@@ -1039,8 +1034,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "ciu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_dout_mmc3.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
@@ -1114,14 +1109,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
 static struct clksrc_clk exynos5_clksrcs[] = {
 	{
 		.clk	= {
-			.name		= "sclk_dwmci",
-			.parent		= &exynos5_clk_dout_mmc4.clk,
-			.enable		= exynos5_clksrc_mask_fsys_ctrl,
-			.ctrlbit	= (1 << 16),
-		},
-		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-	}, {
-		.clk	= {
 			.name		= "sclk_fimd",
 			.devname	= "s3cfb.1",
 			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sun Aug 26 07:59:28 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 26 Aug 2012 17:29:28 +0530
Subject: [PATCH v3 0/3] ARM: Exynos5: Add support for MSHC controller
Message-ID: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>

This patch series adds Exynos5250 platform support for MSHC controllers.

Thomas Abraham (3):
  ARM: Samsung: Add support for MSHC controller clocks
  ARM: Exynos5: Add AUXDATA support for MSHC controllers
  ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

 arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
 arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
 arch/arm/mach-exynos/clock-exynos5.c      |   45 ++++++++---------------
 arch/arm/mach-exynos/include/mach/map.h   |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c    |    8 ++++
 5 files changed, 113 insertions(+), 30 deletions(-)



From thomas.abraham at linaro.org  Sun Aug 26 07:59:30 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 26 Aug 2012 17:29:30 +0530
Subject: [PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC controllers
In-Reply-To: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345982371-26483-3-git-send-email-thomas.abraham@linaro.org>

Add entries if MSHC controllers in AUXDATA table for correct device name
initialization.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/include/mach/map.h |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9d1f3ac..5b0ee41 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -172,6 +172,7 @@
 
 #define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI		0x12550000
+#define EXYNOS5_PA_DWMCI(x)		(0x12200000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_HSOTG		0x12480000
 #define EXYNOS4_PA_USB_HSPHY		0x125B0000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..4257cc1 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s3c2440-i2c.0", NULL),
 	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 				"s3c2440-i2c.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),
+				"dw_mmc.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(1),
+				"dw_mmc.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(2),
+				"dw_mmc.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(3),
+				"dw_mmc.3", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 				"exynos4210-spi.0", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sun Aug 26 07:59:31 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 26 Aug 2012 17:29:31 +0530
Subject: [PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung
 Exynos5250 platforms
In-Reply-To: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1345982371-26483-4-git-send-email-thomas.abraham@linaro.org>

Add device nodes for the four instances of dw_mmc controllers in Exynos5250
and enable instance 0 and 2 for the smdk5250 board.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
 arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
 2 files changed, 88 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..6dc9faf 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,12 +16,19 @@
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
 	compatible = "samsung,smdk5250", "samsung,exynos5250";
 
+	aliases {
+		mshc0 = &mshc_0;
+		mshc1 = &mshc_1;
+		mshc2 = &mshc_2;
+		mshc3 = &mshc_3;
+	};
+
 	memory {
 		reg = <0x40000000 0x80000000>;
 	};
 
 	chosen {
-		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
 	i2c at 12C60000 {
@@ -72,6 +79,54 @@
 		status = "disabled";
 	};
 
+	mshc_0: dwmmc0 at 12200000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <8>;
+			gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+				<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+				<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+				<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+				<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+		};
+	};
+
+	mshc_1: dwmmc1 at 12210000 {
+		status = "disabled";
+	};
+
+	mshc_2: dwmmc2 at 12220000 {
+		num-slots = <1>;
+		supports-highspeed;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+			samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+			gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+				<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+				<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+				<&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+				<&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+		};
+	};
+
+	mshc_3: dwmmc3 at 12230000 {
+		status = "disabled";
+	};
+
 	spi_0: spi at 12d20000 {
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..f69e389 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -182,6 +182,38 @@
 		#size-cells = <0>;
 	};
 
+	dwmmc0 at 12200000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc1 at 12210000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc2 at 12220000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc3 at 12230000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.6.6.rc2



From marek.vasut at gmail.com  Sun Aug 26 07:42:34 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 26 Aug 2012 13:42:34 +0200
Subject: [PATCH 3/4 V2] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <20120825080504.GL31998@S2101-09.ap.freescale.net>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-3-git-send-email-marex@denx.de>
 <20120825080504.GL31998@S2101-09.ap.freescale.net>
Message-ID: <201208261342.34653.marex@denx.de>

Dear Shawn Guo,

> On Sat, Aug 25, 2012 at 01:51:39AM +0200, Marek Vasut wrote:
> > +
> > +		reg_vddio_sd0: vddio-sd0 {
> > +			compatible = "regulator-fixed";
> > +			regulator-name = "vddio-sd0";
> > +			regulator-min-microvolt = <3300000>;
> > +			regulator-max-microvolt = <3300000>;
> > +			gpio = <&gpio3 28 0>;
> > +		};
> > +
> > +		reg_usb0_vbus: usb0_vbus {
> > +			compatible = "regulator-fixed";
> > +			regulator-name = "usb0_vbus";
> > +			regulator-min-microvolt = <5000000>;
> > +			regulator-max-microvolt = <5000000>;
> > +			gpio = <&gpio3 12 0>;
> > +			enable-active-low;
> 
> Documentation/devicetree/bindings/regulator/fixed-regulator.txt:
> 
> - enable-active-high: Polarity of GPIO is Active high
> If this property is missing, the default assumed is Active low.
> 
> I suspect you need to recheck this aspect for all these 3 fixed
> regulators.

Ok, so the prop had no impact? I'll retest and resubmit. Also, put the SPS1 on 
hold until the led issue is done for.

Thanks

> > +		};
> > +
> > +		reg_usb1_vbus: usb1_vbus {
> > +			compatible = "regulator-fixed";
> > +			regulator-name = "usb1_vbus";
> > +			regulator-min-microvolt = <5000000>;
> > +			regulator-max-microvolt = <5000000>;
> > +			gpio = <&gpio3 13 0>;
> > +			enable-active-low;
> > +		};

Best regards,
Marek Vasut


From marex at denx.de  Sun Aug 26 08:59:31 2012
From: marex at denx.de (Marek Vasut)
Date: Sun, 26 Aug 2012 14:59:31 +0200
Subject: [PATCH V3] ARM: mxs: Update DENX M28 machine and dts file
Message-ID: <1345985971-12061-1-git-send-email-marex@denx.de>

Update the mach-mxs machine by removing the enet_clkout(). The new
revision of the board doesn't need that. Also, update the DTS file
with all the new drivers pulled in the mainline recently, that is,
SPI, LRADC, USB.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Fabio Estevam <fabio.estevam at freescale.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx28-m28evk.dts |   79 +++++++++++++++++++++++++++++++++---
 arch/arm/mach-mxs/mach-mxs.c       |    1 -
 2 files changed, 73 insertions(+), 7 deletions(-)

V2: Move the usbphy overcurrent definition to include file.
V3: Fixed regulator issue is now ... fixed.

diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index ac3eff9..8118b64 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
 	apb at 80000000 {
 		apbh at 80000000 {
 			gpmi-nand at 8000c000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
 				status = "okay";
@@ -62,9 +64,27 @@
 					     &mmc0_sck_cfg>;
 				bus-width = <8>;
 				wp-gpios = <&gpio3 10 1>;
+				vmmc-supply = <&reg_vddio_sd0>;
 				status = "okay";
 			};
 
+			ssp2: ssp at 80014000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi2_pins_a>;
+				status = "okay";
+
+				flash: m25p80 at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "m25p80";
+					spi-max-frequency = <40000000>;
+					reg = <0>;
+				};
+			};
+
 			pinctrl at 80018000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
@@ -72,8 +92,11 @@
 				hog_pins_a: hog at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
+						0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
 						0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
 						0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+						0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+						0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
 					>;
 					fsl,drive-strength = <0>;
 					fsl,voltage = <1>;
@@ -129,6 +152,7 @@
 			i2c0: i2c at 80058000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2c0_pins_a>;
+				clock-frequency = <400000>;
 				status = "okay";
 
 				sgtl5000: codec at 0a {
@@ -151,32 +175,51 @@
 				};
 			};
 
+			lradc at 80050000 {
+				status = "okay";
+			};
+
 			duart: serial at 80074000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&duart_pins_a>;
 				status = "okay";
 			};
 
-			auart0: serial at 8006a000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&auart0_2pins_a>;
+			usbphy0: usbphy at 8007c000 {
 				status = "okay";
 			};
 
-			auart3: serial at 80070000 {
+			usbphy1: usbphy at 8007e000 {
+				status = "okay";
+			};
+
+			auart0: serial at 8006a000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&auart3_pins_a>;
+				pinctrl-0 = <&auart0_2pins_a>;
 				status = "okay";
 			};
 		};
 	};
 
 	ahb at 80080000 {
+		usb0: usb at 80080000 {
+			vbus-supply = <&reg_usb0_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usbphy0_pins_a>;
+			status = "okay";
+		};
+
+		usb1: usb at 80090000 {
+			vbus-supply = <&reg_usb1_vbus>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&usbphy1_pins_a>;
+			status = "okay";
+		};
+
 		mac0: ethernet at 800f0000 {
 			phy-mode = "rmii";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mac0_pins_a>;
-			phy-reset-gpios = <&gpio3 11 0>;
 			status = "okay";
 		};
 
@@ -198,6 +241,30 @@
 			regulator-max-microvolt = <3300000>;
 			regulator-always-on;
 		};
+
+		reg_vddio_sd0: vddio-sd0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vddio-sd0";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 28 0>;
+		};
+
+		reg_usb0_vbus: usb0_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb0_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 12 0>;
+		};
+
+		reg_usb1_vbus: usb1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 13 0>;
+		};
 	};
 
 	sound {
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 3b0d9c6..5cbb637 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -288,7 +288,6 @@ static void __init imx28_evk_post_init(void)
 
 static void __init m28evk_init(void)
 {
-	enable_clk_enet_out();
 	update_fec_mac_prop(OUI_DENX);
 
 	mxsfb_pdata.mode_list = m28evk_video_modes;
-- 
1.7.10.4



From stigge at antcom.de  Sun Aug 26 10:23:21 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 26 Aug 2012 16:23:21 +0200
Subject: [PATCH] video: Remove pnx4008 driver
In-Reply-To: <1345991001-32462-1-git-send-email-stigge@antcom.de>
References: <1345991001-32462-1-git-send-email-stigge@antcom.de>
Message-ID: <1345991001-32462-2-git-send-email-stigge@antcom.de>

This patch removes the video driver for pnx4008. The architecture is being
removed via the arm-soc tree.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/video/Kconfig            |   15 
 drivers/video/Makefile           |    2 
 drivers/video/pnx4008/Makefile   |    7 
 drivers/video/pnx4008/dum.h      |  211 ---------
 drivers/video/pnx4008/fbcommon.h |   43 -
 drivers/video/pnx4008/pnxrgbfb.c |  198 --------
 drivers/video/pnx4008/sdum.c     |  861 ---------------------------------------
 drivers/video/pnx4008/sdum.h     |  136 ------
 8 files changed, 1473 deletions(-)

--- linux-2.6.orig/drivers/video/Kconfig
+++ linux-2.6/drivers/video/Kconfig
@@ -2151,21 +2151,6 @@ config FB_UDL
 	  mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
 	  To compile as a module, choose M here: the module name is udlfb.
 
-config FB_PNX4008_DUM
-	tristate "Display Update Module support on Philips PNX4008 board"
-	depends on FB && ARCH_PNX4008
-	---help---
-	  Say Y here to enable support for PNX4008 Display Update Module (DUM)
-
-config FB_PNX4008_DUM_RGB
-	tristate "RGB Framebuffer support on Philips PNX4008 board"
-	depends on FB_PNX4008_DUM
-	select FB_CFB_FILLRECT
-	select FB_CFB_COPYAREA
-	select FB_CFB_IMAGEBLIT
-	---help---
-	  Say Y here to enable support for PNX4008 RGB Framebuffer
-
 config FB_IBM_GXT4500
 	tristate "Framebuffer support for IBM GXT4500P adaptor"
 	depends on FB && PPC
--- linux-2.6.orig/drivers/video/Makefile
+++ linux-2.6/drivers/video/Makefile
@@ -128,8 +128,6 @@ obj-$(CONFIG_FB_S3C)		  += s3c-fb.o
 obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
 obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o
 obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
-obj-$(CONFIG_FB_PNX4008_DUM)	  += pnx4008/
-obj-$(CONFIG_FB_PNX4008_DUM_RGB)  += pnx4008/
 obj-$(CONFIG_FB_IBM_GXT4500)	  += gxt4500.o
 obj-$(CONFIG_FB_PS3)		  += ps3fb.o
 obj-$(CONFIG_FB_SM501)            += sm501fb.o
--- linux-2.6.orig/drivers/video/pnx4008/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the new PNX4008 framebuffer device driver
-#
-
-obj-$(CONFIG_FB_PNX4008_DUM) += sdum.o
-obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnxrgbfb.o
-
--- linux-2.6.orig/drivers/video/pnx4008/dum.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * linux/drivers/video/pnx4008/dum.h
- *
- * Internal header for SDUM
- *
- * 2005 (c) Koninklijke Philips N.V. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX008_DUM_H__
-#define __PNX008_DUM_H__
-
-#include <mach/platform.h>
-
-#define PNX4008_DUMCONF_VA_BASE		IO_ADDRESS(PNX4008_DUMCONF_BASE)
-#define PNX4008_DUM_MAIN_VA_BASE	IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
-
-/* DUM CFG ADDRESSES */
-#define DUM_CH_BASE_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)
-#define DUM_CH_MIN_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)
-#define DUM_CH_MAX_ADR		(PNX4008_DUMCONF_VA_BASE + 0x04)
-#define DUM_CH_CONF_ADR		(PNX4008_DUMCONF_VA_BASE + 0x08)
-#define DUM_CH_STAT_ADR		(PNX4008_DUMCONF_VA_BASE + 0x0C)
-#define DUM_CH_CTRL_ADR		(PNX4008_DUMCONF_VA_BASE + 0x10)
-
-#define CH_MARG		(0x100 / sizeof(u32))
-#define DUM_CH_MIN(i)	(*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))
-#define DUM_CH_MAX(i)	(*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))
-#define DUM_CH_CONF(i)	(*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))
-#define DUM_CH_STAT(i)	(*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))
-#define DUM_CH_CTRL(i)	(*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))
-
-#define DUM_CONF_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x00)
-#define DUM_CTRL_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x04)
-#define DUM_STAT_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x08)
-#define DUM_DECODE_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x0C)
-#define DUM_COM_BASE_ADR      (PNX4008_DUM_MAIN_VA_BASE + 0x10)
-#define DUM_SYNC_C_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x14)
-#define DUM_CLK_DIV_ADR       (PNX4008_DUM_MAIN_VA_BASE + 0x18)
-#define DUM_DIRTY_LOW_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x20)
-#define DUM_DIRTY_HIGH_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x24)
-#define DUM_FORMAT_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x28)
-#define DUM_WTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x30)
-#define DUM_RTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x34)
-#define DUM_WTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x38)
-#define DUM_RTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x3C)
-#define DUM_TCFG_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x40)
-#define DUM_OUTP_FORMAT1_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x44)
-#define DUM_OUTP_FORMAT2_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x48)
-#define DUM_SYNC_MODE_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x4C)
-#define DUM_SYNC_OUT_C_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x50)
-
-#define DUM_CONF              (*(volatile u32 *)(DUM_CONF_ADR))
-#define DUM_CTRL              (*(volatile u32 *)(DUM_CTRL_ADR))
-#define DUM_STAT              (*(volatile u32 *)(DUM_STAT_ADR))
-#define DUM_DECODE            (*(volatile u32 *)(DUM_DECODE_ADR))
-#define DUM_COM_BASE          (*(volatile u32 *)(DUM_COM_BASE_ADR))
-#define DUM_SYNC_C            (*(volatile u32 *)(DUM_SYNC_C_ADR))
-#define DUM_CLK_DIV           (*(volatile u32 *)(DUM_CLK_DIV_ADR))
-#define DUM_DIRTY_LOW         (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))
-#define DUM_DIRTY_HIGH        (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))
-#define DUM_FORMAT            (*(volatile u32 *)(DUM_FORMAT_ADR))
-#define DUM_WTCFG1            (*(volatile u32 *)(DUM_WTCFG1_ADR))
-#define DUM_RTCFG1            (*(volatile u32 *)(DUM_RTCFG1_ADR))
-#define DUM_WTCFG2            (*(volatile u32 *)(DUM_WTCFG2_ADR))
-#define DUM_RTCFG2            (*(volatile u32 *)(DUM_RTCFG2_ADR))
-#define DUM_TCFG              (*(volatile u32 *)(DUM_TCFG_ADR))
-#define DUM_OUTP_FORMAT1      (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))
-#define DUM_OUTP_FORMAT2      (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))
-#define DUM_SYNC_MODE         (*(volatile u32 *)(DUM_SYNC_MODE_ADR))
-#define DUM_SYNC_OUT_C        (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))
-
-/* DUM SLAVE ADDRESSES */
-#define DUM_SLAVE_WRITE_ADR      (PNX4008_DUM_MAINCFG_BASE + 0x0000000)
-#define DUM_SLAVE_READ1_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000000)
-#define DUM_SLAVE_READ1_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000004)
-#define DUM_SLAVE_READ2_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000008)
-#define DUM_SLAVE_READ2_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x100000C)
-
-#define DUM_SLAVE_WRITE_W  ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))
-#define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))
-#define DUM_SLAVE_READ1_I  ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))
-#define DUM_SLAVE_READ1_R  ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))
-#define DUM_SLAVE_READ2_I  ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))
-#define DUM_SLAVE_READ2_R  ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))
-
-/* Sony display register addresses */
-#define DISP_0_REG            (0x00)
-#define DISP_1_REG            (0x01)
-#define DISP_CAL_REG          (0x20)
-#define DISP_ID_REG           (0x2A)
-#define DISP_XMIN_L_REG       (0x30)
-#define DISP_XMIN_H_REG       (0x31)
-#define DISP_YMIN_REG         (0x32)
-#define DISP_XMAX_L_REG       (0x34)
-#define DISP_XMAX_H_REG       (0x35)
-#define DISP_YMAX_REG         (0x36)
-#define DISP_SYNC_EN_REG      (0x38)
-#define DISP_SYNC_RISE_L_REG  (0x3C)
-#define DISP_SYNC_RISE_H_REG  (0x3D)
-#define DISP_SYNC_FALL_L_REG  (0x3E)
-#define DISP_SYNC_FALL_H_REG  (0x3F)
-#define DISP_PIXEL_REG        (0x0B)
-#define DISP_DUMMY1_REG       (0x28)
-#define DISP_DUMMY2_REG       (0x29)
-#define DISP_TIMING_REG       (0x98)
-#define DISP_DUMP_REG         (0x99)
-
-/* Sony display constants */
-#define SONY_ID1              (0x22)
-#define SONY_ID2              (0x23)
-
-/* Philips display register addresses */
-#define PH_DISP_ORIENT_REG    (0x003)
-#define PH_DISP_YPOINT_REG    (0x200)
-#define PH_DISP_XPOINT_REG    (0x201)
-#define PH_DISP_PIXEL_REG     (0x202)
-#define PH_DISP_YMIN_REG      (0x406)
-#define PH_DISP_YMAX_REG      (0x407)
-#define PH_DISP_XMIN_REG      (0x408)
-#define PH_DISP_XMAX_REG      (0x409)
-
-/* Misc constants */
-#define NO_VALID_DISPLAY_FOUND      (0)
-#define DISPLAY2_IS_NOT_CONNECTED   (0)
-
-/* register values */
-#define V_BAC_ENABLE		(BIT(0))
-#define V_BAC_DISABLE_IDLE	(BIT(1))
-#define V_BAC_DISABLE_TRIG	(BIT(2))
-#define V_DUM_RESET		(BIT(3))
-#define V_MUX_RESET		(BIT(4))
-#define BAC_ENABLED		(BIT(0))
-#define BAC_DISABLED		0
-
-/* Sony LCD commands */
-#define V_LCD_STANDBY_OFF	((BIT(25)) | (0 << 16) | DISP_0_REG)
-#define V_LCD_USE_9BIT_BUS	((BIT(25)) | (2 << 16) | DISP_1_REG)
-#define V_LCD_SYNC_RISE_L	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)
-#define V_LCD_SYNC_RISE_H	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)
-#define V_LCD_SYNC_FALL_L	((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)
-#define V_LCD_SYNC_FALL_H	((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)
-#define V_LCD_SYNC_ENABLE	((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)
-#define V_LCD_DISPLAY_ON	((BIT(25)) | (64 << 16) | DISP_0_REG)
-
-enum {
-	PAD_NONE,
-	PAD_512,
-	PAD_1024
-};
-
-enum {
-	RGB888,
-	RGB666,
-	RGB565,
-	BGR565,
-	ARGB1555,
-	ABGR1555,
-	ARGB4444,
-	ABGR4444
-};
-
-struct dum_setup {
-	int sync_neg_edge;
-	int round_robin;
-	int mux_int;
-	int synced_dirty_flag_int;
-	int dirty_flag_int;
-	int error_int;
-	int pf_empty_int;
-	int sf_empty_int;
-	int bac_dis_int;
-	u32 dirty_base_adr;
-	u32 command_base_adr;
-	u32 sync_clk_div;
-	int sync_output;
-	u32 sync_restart_val;
-	u32 set_sync_high;
-	u32 set_sync_low;
-};
-
-struct dum_ch_setup {
-	int disp_no;
-	u32 xmin;
-	u32 ymin;
-	u32 xmax;
-	u32 ymax;
-	int xmirror;
-	int ymirror;
-	int rotate;
-	u32 minadr;
-	u32 maxadr;
-	u32 dirtybuffer;
-	int pad;
-	int format;
-	int hwdirty;
-	int slave_trans;
-};
-
-struct disp_window {
-	u32 xmin_l;
-	u32 xmin_h;
-	u32 ymin;
-	u32 xmax_l;
-	u32 xmax_h;
-	u32 ymax;
-};
-
-#endif				/* #ifndef __PNX008_DUM_H__ */
--- linux-2.6.orig/drivers/video/pnx4008/fbcommon.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2005 Philips Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
-*/
-
-#define QCIF_W  (176)
-#define QCIF_H  (144)
-
-#define CIF_W   (352)
-#define CIF_H   (288)
-
-#define LCD_X_RES	208
-#define LCD_Y_RES	320
-#define LCD_X_PAD	256
-#define LCD_BBP		4	/* Bytes Per Pixel */
-
-#define DISP_MAX_X_SIZE     (320)
-#define DISP_MAX_Y_SIZE     (208)
-
-#define RETURNVAL_BASE (0x400)
-
-enum fb_ioctl_returntype {
-	ENORESOURCESLEFT = RETURNVAL_BASE,
-	ERESOURCESNOTFREED,
-	EPROCNOTOWNER,
-	EFBNOTOWNER,
-	ECOPYFAILED,
-	EIOREMAPFAILED,
-};
--- linux-2.6.orig/drivers/video/pnx4008/pnxrgbfb.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * drivers/video/pnx4008/pnxrgbfb.c
- *
- * PNX4008's framebuffer support
- *
- * Author: Grigory Tolstolytkin <gtolstolytkin at ru.mvista.com>
- * Based on Philips Semiconductors's code
- *
- * Copyrght (c) 2005 MontaVista Software, Inc.
- * Copyright (c) 2005 Philips Semiconductors
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include "sdum.h"
-#include "fbcommon.h"
-
-static u32 colreg[16];
-
-static struct fb_var_screeninfo rgbfb_var __initdata = {
-	.xres = LCD_X_RES,
-	.yres = LCD_Y_RES,
-	.xres_virtual = LCD_X_RES,
-	.yres_virtual = LCD_Y_RES,
-	.bits_per_pixel = 32,
-	.red.offset = 16,
-	.red.length = 8,
-	.green.offset = 8,
-	.green.length = 8,
-	.blue.offset = 0,
-	.blue.length = 8,
-	.left_margin = 0,
-	.right_margin = 0,
-	.upper_margin = 0,
-	.lower_margin = 0,
-	.vmode = FB_VMODE_NONINTERLACED,
-};
-static struct fb_fix_screeninfo rgbfb_fix __initdata = {
-	.id = "RGBFB",
-	.line_length = LCD_X_RES * LCD_BBP,
-	.type = FB_TYPE_PACKED_PIXELS,
-	.visual = FB_VISUAL_TRUECOLOR,
-	.xpanstep = 0,
-	.ypanstep = 0,
-	.ywrapstep = 0,
-	.accel = FB_ACCEL_NONE,
-};
-
-static int channel_owned;
-
-static int no_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
-	return 0;
-}
-
-static int rgbfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
-			   u_int transp, struct fb_info *info)
-{
-	if (regno > 15)
-		return 1;
-
-	colreg[regno] = ((red & 0xff00) << 8) | (green & 0xff00) |
-	    ((blue & 0xff00) >> 8);
-	return 0;
-}
-
-static int rgbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
-	return pnx4008_sdum_mmap(info, vma, NULL);
-}
-
-static struct fb_ops rgbfb_ops = {
-	.fb_mmap = rgbfb_mmap,
-	.fb_setcolreg = rgbfb_setcolreg,
-	.fb_fillrect = cfb_fillrect,
-	.fb_copyarea = cfb_copyarea,
-	.fb_imageblit = cfb_imageblit,
-};
-
-static int rgbfb_remove(struct platform_device *pdev)
-{
-	struct fb_info *info = platform_get_drvdata(pdev);
-
-	if (info) {
-		unregister_framebuffer(info);
-		fb_dealloc_cmap(&info->cmap);
-		framebuffer_release(info);
-		platform_set_drvdata(pdev, NULL);
-	}
-
-	pnx4008_free_dum_channel(channel_owned, pdev->id);
-	pnx4008_set_dum_exit_notification(pdev->id);
-
-	return 0;
-}
-
-static int __devinit rgbfb_probe(struct platform_device *pdev)
-{
-	struct fb_info *info;
-	struct dumchannel_uf chan_uf;
-	int ret;
-	char *option;
-
-	info = framebuffer_alloc(sizeof(u32) * 16, &pdev->dev);
-	if (!info) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	pnx4008_get_fb_addresses(FB_TYPE_RGB, (void **)&info->screen_base,
-				 (dma_addr_t *) &rgbfb_fix.smem_start,
-				 &rgbfb_fix.smem_len);
-
-	if ((ret = pnx4008_alloc_dum_channel(pdev->id)) < 0)
-		goto err0;
-	else {
-		channel_owned = ret;
-		chan_uf.channelnr = channel_owned;
-		chan_uf.dirty = (u32 *) NULL;
-		chan_uf.source = (u32 *) rgbfb_fix.smem_start;
-		chan_uf.x_offset = 0;
-		chan_uf.y_offset = 0;
-		chan_uf.width = LCD_X_RES;
-		chan_uf.height = LCD_Y_RES;
-
-		if ((ret = pnx4008_put_dum_channel_uf(chan_uf, pdev->id))< 0)
-			goto err1;
-
-		if ((ret =
-		     pnx4008_set_dum_channel_sync(channel_owned, CONF_SYNC_ON,
-						  pdev->id)) < 0)
-			goto err1;
-
-		if ((ret =
-		     pnx4008_set_dum_channel_dirty_detect(channel_owned,
-							 CONF_DIRTYDETECTION_ON,
-							 pdev->id)) < 0)
-			goto err1;
-	}
-
-	if (!fb_get_options("pnxrgbfb", &option) && option &&
-			!strcmp(option, "nocursor"))
-		rgbfb_ops.fb_cursor = no_cursor;
-
-	info->node = -1;
-	info->flags = FBINFO_FLAG_DEFAULT;
-	info->fbops = &rgbfb_ops;
-	info->fix = rgbfb_fix;
-	info->var = rgbfb_var;
-	info->screen_size = rgbfb_fix.smem_len;
-	info->pseudo_palette = info->par;
-	info->par = NULL;
-
-	ret = fb_alloc_cmap(&info->cmap, 256, 0);
-	if (ret < 0)
-		goto err1;
-
-	ret = register_framebuffer(info);
-	if (ret < 0)
-		goto err2;
-	platform_set_drvdata(pdev, info);
-
-	return 0;
-
-err2:
-	fb_dealloc_cmap(&info->cmap);
-err1:
-	pnx4008_free_dum_channel(channel_owned, pdev->id);
-err0:
-	framebuffer_release(info);
-err:
-	return ret;
-}
-
-static struct platform_driver rgbfb_driver = {
-	.driver = {
-		.name = "pnx4008-rgbfb",
-	},
-	.probe = rgbfb_probe,
-	.remove = rgbfb_remove,
-};
-
-module_platform_driver(rgbfb_driver);
-
-MODULE_LICENSE("GPL");
--- linux-2.6.orig/drivers/video/pnx4008/sdum.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/*
- * drivers/video/pnx4008/sdum.c
- *
- * Display Update Master support
- *
- * Authors: Grigory Tolstolytkin <gtolstolytkin at ru.mvista.com>
- *          Vitaly Wool <vitalywool at gmail.com>
- * Based on Philips Semiconductors's code
- *
- * Copyrght (c) 2005-2006 MontaVista Software, Inc.
- * Copyright (c) 2005 Philips Semiconductors
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/gfp.h>
-#include <asm/uaccess.h>
-#include <asm/gpio.h>
-
-#include "sdum.h"
-#include "fbcommon.h"
-#include "dum.h"
-
-/* Framebuffers we have */
-
-static struct pnx4008_fb_addr {
-	int fb_type;
-	long addr_offset;
-	long fb_length;
-} fb_addr[] = {
-	[0] = {
-		FB_TYPE_YUV, 0, 0xB0000
-	},
-	[1] = {
-		FB_TYPE_RGB, 0xB0000, 0x50000
-	},
-};
-
-static struct dum_data {
-	u32 lcd_phys_start;
-	u32 lcd_virt_start;
-	u32 slave_phys_base;
-	u32 *slave_virt_base;
-	int fb_owning_channel[MAX_DUM_CHANNELS];
-	struct dumchannel_uf chan_uf_store[MAX_DUM_CHANNELS];
-} dum_data;
-
-/* Different local helper functions */
-
-static u32 nof_pixels_dx(struct dum_ch_setup *ch_setup)
-{
-	return (ch_setup->xmax - ch_setup->xmin + 1);
-}
-
-static u32 nof_pixels_dy(struct dum_ch_setup *ch_setup)
-{
-	return (ch_setup->ymax - ch_setup->ymin + 1);
-}
-
-static u32 nof_pixels_dxy(struct dum_ch_setup *ch_setup)
-{
-	return (nof_pixels_dx(ch_setup) * nof_pixels_dy(ch_setup));
-}
-
-static u32 nof_bytes(struct dum_ch_setup *ch_setup)
-{
-	u32 r = nof_pixels_dxy(ch_setup);
-	switch (ch_setup->format) {
-	case RGB888:
-	case RGB666:
-		r *= 4;
-		break;
-
-	default:
-		r *= 2;
-		break;
-	}
-	return r;
-}
-
-static u32 build_command(int disp_no, u32 reg, u32 val)
-{
-	return ((disp_no << 26) | BIT(25) | (val << 16) | (disp_no << 10) |
-		(reg << 0));
-}
-
-static u32 build_double_index(int disp_no, u32 val)
-{
-	return ((disp_no << 26) | (val << 16) | (disp_no << 10) | (val << 0));
-}
-
-static void build_disp_window(struct dum_ch_setup * ch_setup, struct disp_window * dw)
-{
-	dw->ymin = ch_setup->ymin;
-	dw->ymax = ch_setup->ymax;
-	dw->xmin_l = ch_setup->xmin & 0xFF;
-	dw->xmin_h = (ch_setup->xmin & BIT(8)) >> 8;
-	dw->xmax_l = ch_setup->xmax & 0xFF;
-	dw->xmax_h = (ch_setup->xmax & BIT(8)) >> 8;
-}
-
-static int put_channel(struct dumchannel chan)
-{
-	int i = chan.channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else {
-		DUM_CH_MIN(i) = chan.dum_ch_min;
-		DUM_CH_MAX(i) = chan.dum_ch_max;
-		DUM_CH_CONF(i) = chan.dum_ch_conf;
-		DUM_CH_CTRL(i) = chan.dum_ch_ctrl;
-	}
-
-	return 0;
-}
-
-static void clear_channel(int channr)
-{
-	struct dumchannel chan;
-
-	chan.channelnr = channr;
-	chan.dum_ch_min = 0;
-	chan.dum_ch_max = 0;
-	chan.dum_ch_conf = 0;
-	chan.dum_ch_ctrl = 0;
-
-	put_channel(chan);
-}
-
-static int put_cmd_string(struct cmdstring cmds)
-{
-	u16 *cmd_str_virtaddr;
-	u32 *cmd_ptr0_virtaddr;
-	u32 cmd_str_physaddr;
-
-	int i = cmds.channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if ((cmd_ptr0_virtaddr =
-		  (int *)ioremap_nocache(DUM_COM_BASE,
-					 sizeof(int) * MAX_DUM_CHANNELS)) ==
-		 NULL)
-		return -EIOREMAPFAILED;
-	else {
-		cmd_str_physaddr = ioread32(&cmd_ptr0_virtaddr[cmds.channelnr]);
-		if ((cmd_str_virtaddr =
-		     (u16 *) ioremap_nocache(cmd_str_physaddr,
-					     sizeof(cmds))) == NULL) {
-			iounmap(cmd_ptr0_virtaddr);
-			return -EIOREMAPFAILED;
-		} else {
-			int t;
-			for (t = 0; t < 8; t++)
-				iowrite16(*((u16 *)&cmds.prestringlen + t),
-					  cmd_str_virtaddr + t);
-
-			for (t = 0; t < cmds.prestringlen / 2; t++)
-				 iowrite16(*((u16 *)&cmds.precmd + t),
-					   cmd_str_virtaddr + t + 8);
-
-			for (t = 0; t < cmds.poststringlen / 2; t++)
-				iowrite16(*((u16 *)&cmds.postcmd + t),
-					  cmd_str_virtaddr + t + 8 +
-					  	cmds.prestringlen / 2);
-
-			iounmap(cmd_ptr0_virtaddr);
-			iounmap(cmd_str_virtaddr);
-		}
-	}
-
-	return 0;
-}
-
-static u32 dum_ch_setup(int ch_no, struct dum_ch_setup * ch_setup)
-{
-	struct cmdstring cmds_c;
-	struct cmdstring *cmds = &cmds_c;
-	struct disp_window dw;
-	int standard;
-	u32 orientation = 0;
-	struct dumchannel chan = { 0 };
-	int ret;
-
-	if ((ch_setup->xmirror) || (ch_setup->ymirror) || (ch_setup->rotate)) {
-		standard = 0;
-
-		orientation = BIT(1);	/* always set 9-bit-bus */
-		if (ch_setup->xmirror)
-			orientation |= BIT(4);
-		if (ch_setup->ymirror)
-			orientation |= BIT(3);
-		if (ch_setup->rotate)
-			orientation |= BIT(0);
-	} else
-		standard = 1;
-
-	cmds->channelnr = ch_no;
-
-	/* build command string header */
-	if (standard) {
-		cmds->prestringlen = 32;
-		cmds->poststringlen = 0;
-	} else {
-		cmds->prestringlen = 48;
-		cmds->poststringlen = 16;
-	}
-
-	cmds->format =
-	    (u16) ((ch_setup->disp_no << 4) | (BIT(3)) | (ch_setup->format));
-	cmds->reserved = 0x0;
-	cmds->startaddr_low = (ch_setup->minadr & 0xFFFF);
-	cmds->startaddr_high = (ch_setup->minadr >> 16);
-
-	if ((ch_setup->minadr == 0) && (ch_setup->maxadr == 0)
-	    && (ch_setup->xmin == 0)
-	    && (ch_setup->ymin == 0) && (ch_setup->xmax == 0)
-	    && (ch_setup->ymax == 0)) {
-		cmds->pixdatlen_low = 0;
-		cmds->pixdatlen_high = 0;
-	} else {
-		u32 nbytes = nof_bytes(ch_setup);
-		cmds->pixdatlen_low = (nbytes & 0xFFFF);
-		cmds->pixdatlen_high = (nbytes >> 16);
-	}
-
-	if (ch_setup->slave_trans)
-		cmds->pixdatlen_high |= BIT(15);
-
-	/* build pre-string */
-	build_disp_window(ch_setup, &dw);
-
-	if (standard) {
-		cmds->precmd[0] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG, 0x99);
-		cmds->precmd[1] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-				  dw.xmin_l);
-		cmds->precmd[2] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
-				  dw.xmin_h);
-		cmds->precmd[3] =
-		    build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
-		cmds->precmd[4] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
-				  dw.xmax_l);
-		cmds->precmd[5] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
-				  dw.xmax_h);
-		cmds->precmd[6] =
-		    build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
-		cmds->precmd[7] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-	} else {
-		if (dw.xmin_l == ch_no)
-			cmds->precmd[0] =
-			    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-					  0x99);
-		else
-			cmds->precmd[0] =
-			    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-					  ch_no);
-
-		cmds->precmd[1] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-				  dw.xmin_l);
-		cmds->precmd[2] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
-				  dw.xmin_h);
-		cmds->precmd[3] =
-		    build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
-		cmds->precmd[4] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
-				  dw.xmax_l);
-		cmds->precmd[5] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
-				  dw.xmax_h);
-		cmds->precmd[6] =
-		    build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
-		cmds->precmd[7] =
-		    build_command(ch_setup->disp_no, DISP_1_REG, orientation);
-		cmds->precmd[8] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[9] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[0xA] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[0xB] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->postcmd[0] =
-		    build_command(ch_setup->disp_no, DISP_1_REG, BIT(1));
-		cmds->postcmd[1] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 1);
-		cmds->postcmd[2] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 2);
-		cmds->postcmd[3] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 3);
-	}
-
-	if ((ret = put_cmd_string(cmds_c)) != 0) {
-		return ret;
-	}
-
-	chan.channelnr = cmds->channelnr;
-	chan.dum_ch_min = ch_setup->dirtybuffer + ch_setup->minadr;
-	chan.dum_ch_max = ch_setup->dirtybuffer + ch_setup->maxadr;
-	chan.dum_ch_conf = 0x002;
-	chan.dum_ch_ctrl = 0x04;
-
-	put_channel(chan);
-
-	return 0;
-}
-
-static u32 display_open(int ch_no, int auto_update, u32 * dirty_buffer,
-			u32 * frame_buffer, u32 xpos, u32 ypos, u32 w, u32 h)
-{
-
-	struct dum_ch_setup k;
-	int ret;
-
-	/* keep width & height within display area */
-	if ((xpos + w) > DISP_MAX_X_SIZE)
-		w = DISP_MAX_X_SIZE - xpos;
-
-	if ((ypos + h) > DISP_MAX_Y_SIZE)
-		h = DISP_MAX_Y_SIZE - ypos;
-
-	/* assume 1 display only */
-	k.disp_no = 0;
-	k.xmin = xpos;
-	k.ymin = ypos;
-	k.xmax = xpos + (w - 1);
-	k.ymax = ypos + (h - 1);
-
-	/* adjust min and max values if necessary */
-	if (k.xmin > DISP_MAX_X_SIZE - 1)
-		k.xmin = DISP_MAX_X_SIZE - 1;
-	if (k.ymin > DISP_MAX_Y_SIZE - 1)
-		k.ymin = DISP_MAX_Y_SIZE - 1;
-
-	if (k.xmax > DISP_MAX_X_SIZE - 1)
-		k.xmax = DISP_MAX_X_SIZE - 1;
-	if (k.ymax > DISP_MAX_Y_SIZE - 1)
-		k.ymax = DISP_MAX_Y_SIZE - 1;
-
-	k.xmirror = 0;
-	k.ymirror = 0;
-	k.rotate = 0;
-	k.minadr = (u32) frame_buffer;
-	k.maxadr = (u32) frame_buffer + (((w - 1) << 10) | ((h << 2) - 2));
-	k.pad = PAD_1024;
-	k.dirtybuffer = (u32) dirty_buffer;
-	k.format = RGB888;
-	k.hwdirty = 0;
-	k.slave_trans = 0;
-
-	ret = dum_ch_setup(ch_no, &k);
-
-	return ret;
-}
-
-static void lcd_reset(void)
-{
-	u32 *dum_pio_base = (u32 *)IO_ADDRESS(PNX4008_PIO_BASE);
-
-	udelay(1);
-	iowrite32(BIT(19), &dum_pio_base[2]);
-	udelay(1);
-	iowrite32(BIT(19), &dum_pio_base[1]);
-	udelay(1);
-}
-
-static int dum_init(struct platform_device *pdev)
-{
-	struct clk *clk;
-
-	/* enable DUM clock */
-	clk = clk_get(&pdev->dev, "dum_ck");
-	if (IS_ERR(clk)) {
-		printk(KERN_ERR "pnx4008_dum: Unable to access DUM clock\n");
-		return PTR_ERR(clk);
-	}
-
-	clk_set_rate(clk, 1);
-	clk_put(clk);
-
-	DUM_CTRL = V_DUM_RESET;
-
-	/* set priority to "round-robin". All other params to "false" */
-	DUM_CONF = BIT(9);
-
-	/* Display 1 */
-	DUM_WTCFG1 = PNX4008_DUM_WT_CFG;
-	DUM_RTCFG1 = PNX4008_DUM_RT_CFG;
-	DUM_TCFG = PNX4008_DUM_T_CFG;
-
-	return 0;
-}
-
-static void dum_chan_init(void)
-{
-	int i = 0, ch = 0;
-	u32 *cmdptrs;
-	u32 *cmdstrings;
-
-	DUM_COM_BASE =
-		CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS;
-
-	if ((cmdptrs =
-	     (u32 *) ioremap_nocache(DUM_COM_BASE,
-				     sizeof(u32) * NR_OF_CMDSTRINGS)) == NULL)
-		return;
-
-	for (ch = 0; ch < NR_OF_CMDSTRINGS; ch++)
-		iowrite32(CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * ch,
-			  cmdptrs + ch);
-
-	for (ch = 0; ch < MAX_DUM_CHANNELS; ch++)
-		clear_channel(ch);
-
-	/* Clear the cmdstrings */
-	cmdstrings =
-	    (u32 *)ioremap_nocache(*cmdptrs,
-				   BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS);
-
-	if (!cmdstrings)
-		goto out;
-
-	for (i = 0; i < NR_OF_CMDSTRINGS * BYTES_PER_CMDSTRING / sizeof(u32);
-	     i++)
-		iowrite32(0, cmdstrings + i);
-
-	iounmap((u32 *)cmdstrings);
-
-out:
-	iounmap((u32 *)cmdptrs);
-}
-
-static void lcd_init(void)
-{
-	lcd_reset();
-
-	DUM_OUTP_FORMAT1 = 0; /* RGB666 */
-
-	udelay(1);
-	iowrite32(V_LCD_STANDBY_OFF, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_USE_9BIT_BUS, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_RISE_L, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_RISE_H, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_FALL_L, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_FALL_H, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_ENABLE, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_DISPLAY_ON, dum_data.slave_virt_base);
-	udelay(1);
-}
-
-/* Interface exported to framebuffer drivers */
-
-int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
-			     dma_addr_t *phys_addr, int *fb_length)
-{
-	int i;
-	int ret = -1;
-	for (i = 0; i < ARRAY_SIZE(fb_addr); i++)
-		if (fb_addr[i].fb_type == fb_type) {
-			*virt_addr = (void *)(dum_data.lcd_virt_start +
-					fb_addr[i].addr_offset);
-			*phys_addr =
-			    dum_data.lcd_phys_start + fb_addr[i].addr_offset;
-			*fb_length = fb_addr[i].fb_length;
-			ret = 0;
-			break;
-		}
-
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_get_fb_addresses);
-
-int pnx4008_alloc_dum_channel(int dev_id)
-{
-	int i = 0;
-
-	while ((i < MAX_DUM_CHANNELS) && (dum_data.fb_owning_channel[i] != -1))
-		i++;
-
-	if (i == MAX_DUM_CHANNELS)
-		return -ENORESOURCESLEFT;
-	else {
-		dum_data.fb_owning_channel[i] = dev_id;
-		return i;
-	}
-}
-
-EXPORT_SYMBOL(pnx4008_alloc_dum_channel);
-
-int pnx4008_free_dum_channel(int channr, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		clear_channel(channr);
-		dum_data.fb_owning_channel[channr] = -1;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_free_dum_channel);
-
-int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id)
-{
-	int i = chan_uf.channelnr;
-	int ret;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[i] != dev_id)
-		return -EFBNOTOWNER;
-	else if ((ret =
-		  display_open(chan_uf.channelnr, 0, chan_uf.dirty,
-			       chan_uf.source, chan_uf.y_offset,
-			       chan_uf.x_offset, chan_uf.height,
-			       chan_uf.width)) != 0)
-		return ret;
-	else {
-		dum_data.chan_uf_store[i].dirty = chan_uf.dirty;
-		dum_data.chan_uf_store[i].source = chan_uf.source;
-		dum_data.chan_uf_store[i].x_offset = chan_uf.x_offset;
-		dum_data.chan_uf_store[i].y_offset = chan_uf.y_offset;
-		dum_data.chan_uf_store[i].width = chan_uf.width;
-		dum_data.chan_uf_store[i].height = chan_uf.height;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_put_dum_channel_uf);
-
-int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		if (val == CONF_SYNC_ON) {
-			DUM_CH_CONF(channr) |= CONF_SYNCENABLE;
-			DUM_CH_CONF(channr) |= DUM_CHANNEL_CFG_SYNC_MASK |
-				DUM_CHANNEL_CFG_SYNC_MASK_SET;
-		} else if (val == CONF_SYNC_OFF)
-			DUM_CH_CONF(channr) &= ~CONF_SYNCENABLE;
-		else
-			return -EINVAL;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_channel_sync);
-
-int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		if (val == CONF_DIRTYDETECTION_ON)
-			DUM_CH_CONF(channr) |= CONF_DIRTYENABLE;
-		else if (val == CONF_DIRTYDETECTION_OFF)
-			DUM_CH_CONF(channr) &= ~CONF_DIRTYENABLE;
-		else
-			return -EINVAL;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_channel_dirty_detect);
-
-#if 0 /* Functions not used currently, but likely to be used in future */
-
-static int get_channel(struct dumchannel *p_chan)
-{
-	int i = p_chan->channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else {
-		p_chan->dum_ch_min = DUM_CH_MIN(i);
-		p_chan->dum_ch_max = DUM_CH_MAX(i);
-		p_chan->dum_ch_conf = DUM_CH_CONF(i);
-		p_chan->dum_ch_stat = DUM_CH_STAT(i);
-		p_chan->dum_ch_ctrl = 0;	/* WriteOnly control register */
-	}
-
-	return 0;
-}
-
-int pnx4008_get_dum_channel_uf(struct dumchannel_uf *p_chan_uf, int dev_id)
-{
-	int i = p_chan_uf->channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[i] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		p_chan_uf->dirty = dum_data.chan_uf_store[i].dirty;
-		p_chan_uf->source = dum_data.chan_uf_store[i].source;
-		p_chan_uf->x_offset = dum_data.chan_uf_store[i].x_offset;
-		p_chan_uf->y_offset = dum_data.chan_uf_store[i].y_offset;
-		p_chan_uf->width = dum_data.chan_uf_store[i].width;
-		p_chan_uf->height = dum_data.chan_uf_store[i].height;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_get_dum_channel_uf);
-
-int pnx4008_get_dum_channel_config(int channr, int dev_id)
-{
-	int ret;
-	struct dumchannel chan;
-
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		chan.channelnr = channr;
-		if ((ret = get_channel(&chan)) != 0)
-			return ret;
-	}
-
-	return (chan.dum_ch_conf & DUM_CHANNEL_CFG_MASK);
-}
-
-EXPORT_SYMBOL(pnx4008_get_dum_channel_config);
-
-int pnx4008_force_update_dum_channel(int channr, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else
-		DUM_CH_CTRL(channr) = CTRL_SETDIRTY;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_force_update_dum_channel);
-
-#endif
-
-int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma,
-		      struct device *dev)
-{
-	unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
-
-	if (off < info->fix.smem_len) {
-		vma->vm_pgoff += 1;
-		return dma_mmap_writecombine(dev, vma,
-				(void *)dum_data.lcd_virt_start,
-				dum_data.lcd_phys_start,
-				FB_DMA_SIZE);
-	}
-	return -EINVAL;
-}
-
-EXPORT_SYMBOL(pnx4008_sdum_mmap);
-
-int pnx4008_set_dum_exit_notification(int dev_id)
-{
-	int i;
-
-	for (i = 0; i < MAX_DUM_CHANNELS; i++)
-		if (dum_data.fb_owning_channel[i] == dev_id)
-			return -ERESOURCESNOTFREED;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_exit_notification);
-
-/* Platform device driver for DUM */
-
-static int sdum_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	int retval = 0;
-	struct clk *clk;
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 0);
-		clk_put(clk);
-	} else
-		retval = PTR_ERR(clk);
-
-	/* disable BAC */
-	DUM_CTRL = V_BAC_DISABLE_IDLE;
-
-	/* LCD standby & turn off display */
-	lcd_reset();
-
-	return retval;
-}
-
-static int sdum_resume(struct platform_device *pdev)
-{
-	int retval = 0;
-	struct clk *clk;
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 1);
-		clk_put(clk);
-	} else
-		retval = PTR_ERR(clk);
-
-	/* wait for BAC disable */
-	DUM_CTRL = V_BAC_DISABLE_TRIG;
-
-	while (DUM_CTRL & BAC_ENABLED)
-		udelay(10);
-
-	/* re-init LCD */
-	lcd_init();
-
-	/* enable BAC and reset MUX */
-	DUM_CTRL = V_BAC_ENABLE;
-	udelay(1);
-	DUM_CTRL = V_MUX_RESET;
-	return 0;
-}
-
-static int __devinit sdum_probe(struct platform_device *pdev)
-{
-	int ret = 0, i = 0;
-
-	/* map frame buffer */
-	dum_data.lcd_virt_start = (u32) dma_alloc_writecombine(&pdev->dev,
-						       FB_DMA_SIZE,
-						       &dum_data.lcd_phys_start,
-						       GFP_KERNEL);
-
-	if (!dum_data.lcd_virt_start) {
-		ret = -ENOMEM;
-		goto out_3;
-	}
-
-	/* map slave registers */
-	dum_data.slave_phys_base = PNX4008_DUM_SLAVE_BASE;
-	dum_data.slave_virt_base =
-	    (u32 *) ioremap_nocache(dum_data.slave_phys_base, sizeof(u32));
-
-	if (dum_data.slave_virt_base == NULL) {
-		ret = -ENOMEM;
-		goto out_2;
-	}
-
-	/* initialize DUM and LCD display */
-	ret = dum_init(pdev);
-	if (ret)
-		goto out_1;
-
-	dum_chan_init();
-	lcd_init();
-
-	DUM_CTRL = V_BAC_ENABLE;
-	udelay(1);
-	DUM_CTRL = V_MUX_RESET;
-
-	/* set decode address and sync clock divider */
-	DUM_DECODE = dum_data.lcd_phys_start & DUM_DECODE_MASK;
-	DUM_CLK_DIV = PNX4008_DUM_CLK_DIV;
-
-	for (i = 0; i < MAX_DUM_CHANNELS; i++)
-		dum_data.fb_owning_channel[i] = -1;
-
-	/*setup wakeup interrupt */
-	start_int_set_rising_edge(SE_DISP_SYNC_INT);
-	start_int_ack(SE_DISP_SYNC_INT);
-	start_int_umask(SE_DISP_SYNC_INT);
-
-	return 0;
-
-out_1:
-	iounmap((void *)dum_data.slave_virt_base);
-out_2:
-	dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
-			(void *)dum_data.lcd_virt_start,
-			dum_data.lcd_phys_start);
-out_3:
-	return ret;
-}
-
-static int sdum_remove(struct platform_device *pdev)
-{
-	struct clk *clk;
-
-	start_int_mask(SE_DISP_SYNC_INT);
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 0);
-		clk_put(clk);
-	}
-
-	iounmap((void *)dum_data.slave_virt_base);
-
-	dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
-			(void *)dum_data.lcd_virt_start,
-			dum_data.lcd_phys_start);
-
-	return 0;
-}
-
-static struct platform_driver sdum_driver = {
-	.driver = {
-		.name = "pnx4008-sdum",
-	},
-	.probe = sdum_probe,
-	.remove = sdum_remove,
-	.suspend = sdum_suspend,
-	.resume = sdum_resume,
-};
-
-module_platform_driver(sdum_driver);
-
-MODULE_LICENSE("GPL");
--- linux-2.6.orig/drivers/video/pnx4008/sdum.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2005 Philips Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
-*/
-
-#define MAX_DUM_CHANNELS	64
-
-#define RGB_MEM_WINDOW(x) (0x10000000 + (x)*0x00100000)
-
-#define QCIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x30000: -1)
-#define CIF_OFFSET(x)  (((x) == 0) ? 0x00000: ((x) == 1) ? 0x60000: -1)
-
-#define CTRL_SETDIRTY	 	(0x00000001)
-#define CONF_DIRTYENABLE	(0x00000020)
-#define CONF_SYNCENABLE		(0x00000004)
-
-#define DIRTY_ENABLED(conf)	((conf) & 0x0020)
-#define SYNC_ENABLED(conf) 	((conf) & 0x0004)
-
-/* Display 1 & 2 Write Timing Configuration */
-#define PNX4008_DUM_WT_CFG		0x00372000
-
-/* Display 1 & 2 Read Timing Configuration */
-#define PNX4008_DUM_RT_CFG		0x00003A47
-
-/* DUM Transit State Timing Configuration */
-#define PNX4008_DUM_T_CFG		0x1D	/* 29 HCLK cycles */
-
-/* DUM Sync count clock divider */
-#define PNX4008_DUM_CLK_DIV		0x02DD
-
-/* Memory size for framebuffer, allocated through dma_alloc_writecombine().
- * Must be PAGE aligned
- */
-#define FB_DMA_SIZE (PAGE_ALIGN(SZ_1M + PAGE_SIZE))
-
-#define OFFSET_RGBBUFFER (0xB0000)
-#define OFFSET_YUVBUFFER (0x00000)
-
-#define YUVBUFFER (lcd_video_start + OFFSET_YUVBUFFER)
-#define RGBBUFFER (lcd_video_start + OFFSET_RGBBUFFER)
-
-#define CMDSTRING_BASEADDR	(0x00C000)	/* iram */
-#define BYTES_PER_CMDSTRING	(0x80)
-#define NR_OF_CMDSTRINGS	(64)
-
-#define MAX_NR_PRESTRINGS (0x40)
-#define MAX_NR_POSTSTRINGS (0x40)
-
-/* various mask definitions */
-#define DUM_CLK_ENABLE 0x01
-#define DUM_CLK_DISABLE 0
-#define DUM_DECODE_MASK 0x1FFFFFFF
-#define DUM_CHANNEL_CFG_MASK 0x01FF
-#define DUM_CHANNEL_CFG_SYNC_MASK 0xFFFE00FF
-#define DUM_CHANNEL_CFG_SYNC_MASK_SET 0x0CA00
-
-#define SDUM_RETURNVAL_BASE (0x500)
-
-#define CONF_SYNC_OFF		(0x602)
-#define CONF_SYNC_ON		(0x603)
-
-#define CONF_DIRTYDETECTION_OFF	(0x600)
-#define CONF_DIRTYDETECTION_ON	(0x601)
-
-struct dumchannel_uf {
-	int channelnr;
-	u32 *dirty;
-	u32 *source;
-	u32 x_offset;
-	u32 y_offset;
-	u32 width;
-	u32 height;
-};
-
-enum {
-	FB_TYPE_YUV,
-	FB_TYPE_RGB
-};
-
-struct cmdstring {
-	int channelnr;
-	uint16_t prestringlen;
-	uint16_t poststringlen;
-	uint16_t format;
-	uint16_t reserved;
-	uint16_t startaddr_low;
-	uint16_t startaddr_high;
-	uint16_t pixdatlen_low;
-	uint16_t pixdatlen_high;
-	u32 precmd[MAX_NR_PRESTRINGS];
-	u32 postcmd[MAX_NR_POSTSTRINGS];
-
-};
-
-struct dumchannel {
-	int channelnr;
-	int dum_ch_min;
-	int dum_ch_max;
-	int dum_ch_conf;
-	int dum_ch_stat;
-	int dum_ch_ctrl;
-};
-
-int pnx4008_alloc_dum_channel(int dev_id);
-int pnx4008_free_dum_channel(int channr, int dev_id);
-
-int pnx4008_get_dum_channel_uf(struct dumchannel_uf *pChan_uf, int dev_id);
-int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id);
-
-int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id);
-int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id);
-
-int pnx4008_force_dum_update_channel(int channr, int dev_id);
-
-int pnx4008_get_dum_channel_config(int channr, int dev_id);
-
-int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma, struct device *dev);
-int pnx4008_set_dum_exit_notification(int dev_id);
-
-int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
-			     dma_addr_t * phys_addr, int *fb_length);


From stigge at antcom.de  Sun Aug 26 10:27:06 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 26 Aug 2012 16:27:06 +0200
Subject: [PATCH RESEND] mtd: lpc32xx_mlc: Make driver independent of AMBA
 DMA engine driver
In-Reply-To: <1345898007.1815.7.camel@kyv>
References: <1345674311-16874-1-git-send-email-stigge@antcom.de>
 <1345898007.1815.7.camel@kyv>
Message-ID: <503A323A.9090309@antcom.de>

Hi,

On 25/08/12 14:33, Artem Bityutskiy wrote:
> On Thu, 2012-08-23 at 00:25 +0200, Roland Stigge wrote:
>> This patch makes the MLC NAND driver independent of the single
>> AMBA DMA engine driver by using the platform data provided
>> dma_filter callback.
>> 
>> (This also fixes the build error of the MLC NAND driver in case
>> of module linking because the (not exported) reference to
>> pl08x_filter_id is gone now.)
>> 
>> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> I already have both patches in l2-mtd.git. Please, use it as the 
> baseline for sending patches.

Yes, noticed to late that you have already applied it, sorry.

The recently posted cleanup patches for LPC32xx SLC and MLC drivers
apply to l2-mtd.git, anyway.

Thanks,

Roland


From arnd at arndb.de  Sun Aug 26 10:32:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 26 Aug 2012 14:32:00 +0000
Subject: [PATCH] video: Remove pnx4008 driver
In-Reply-To: <1345991001-32462-2-git-send-email-stigge@antcom.de>
References: <1345991001-32462-1-git-send-email-stigge@antcom.de>
 <1345991001-32462-2-git-send-email-stigge@antcom.de>
Message-ID: <201208261432.00531.arnd@arndb.de>

On Sunday 26 August 2012, Roland Stigge wrote:
> This patch removes the video driver for pnx4008. The architecture is being
> removed via the arm-soc tree.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Acked-by: Arnd Bergmann <arnd at arndb.de>

Florian, can you take this into your tree?

	Arnd


From stigge at antcom.de  Sun Aug 26 10:34:42 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 26 Aug 2012 16:34:42 +0200
Subject: [GIT PULL] ARM: mach-pnx4008: Remove architecture
In-Reply-To: <201208260441.25905.arnd@arndb.de>
References: <1345724548-18130-1-git-send-email-stigge@antcom.de>
 <50378084.3080102@antcom.de> <201208260441.25905.arnd@arndb.de>
Message-ID: <503A3402.7090508@antcom.de>

On 26/08/12 06:41, Arnd Bergmann wrote:
> On Friday 24 August 2012, Roland Stigge wrote:
>> On 23/08/12 14:22, Roland Stigge wrote:
>>> This patch removes the ARM architecture mach-pnx4008. No direct support or user
>>> feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
>>> maintainers.
>>>
>>> Signed-off-by: Roland Stigge <stigge at antcom.de>
>>
>> The patch was a bit too big for the mailing list - sorry.
>>
>> Now re-proposing via pull request, below.
> 
> I think the removal of the frame buffer driver should go separately via the
> framebuffer maintainer (Florian Schandinat), I can take the rest through the
> arm-soc tree.

Fine - consider the new pull request for arch-pnx4008, below.

(Patch for video is separate, now.)

Thanks,

Roland


The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.antcom.de/linux-2.6.git pnx4008-removal

for you to fetch changes up to d684f05f2d55655eee93d86974e9271010aaed09:

  ARM: mach-pnx4008: Remove architecture (2012-08-26 16:30:37 +0200)

----------------------------------------------------------------
Roland Stigge (1):
      ARM: mach-pnx4008: Remove architecture

 arch/arm/Kconfig                                  |    8 -
 arch/arm/Makefile                                 |    1 -
 arch/arm/configs/pnx4008_defconfig                |  472 -----------------------------
 arch/arm/mach-pnx4008/Makefile                    |   12 -
 arch/arm/mach-pnx4008/Makefile.boot               |    4 -
 arch/arm/mach-pnx4008/clock.c                     | 1001 ------------------------------------------------------------
 arch/arm/mach-pnx4008/clock.h                     |   43 ---
 arch/arm/mach-pnx4008/core.c                      |  290 ------------------
 arch/arm/mach-pnx4008/dma.c                       | 1105 -------------------------------------------------------------------
 arch/arm/mach-pnx4008/gpio.c                      |  328 --------------------
 arch/arm/mach-pnx4008/i2c.c                       |   86 ------
 arch/arm/mach-pnx4008/include/mach/clock.h        |   62 ----
 arch/arm/mach-pnx4008/include/mach/debug-macro.S  |   21 --
 arch/arm/mach-pnx4008/include/mach/dma.h          |  160 ----------
 arch/arm/mach-pnx4008/include/mach/entry-macro.S  |  116 -------
 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h |  241 ---------------
 arch/arm/mach-pnx4008/include/mach/hardware.h     |   32 --
 arch/arm/mach-pnx4008/include/mach/irq.h          |   42 ---
 arch/arm/mach-pnx4008/include/mach/irqs.h         |  215 -------------
 arch/arm/mach-pnx4008/include/mach/param.h        |   21 --
 arch/arm/mach-pnx4008/include/mach/platform.h     |   69 -----
 arch/arm/mach-pnx4008/include/mach/pm.h           |   33 --
 arch/arm/mach-pnx4008/include/mach/timex.h        |   19 --
 arch/arm/mach-pnx4008/include/mach/uncompress.h   |   46 ---
 arch/arm/mach-pnx4008/irq.c                       |  121 --------
 arch/arm/mach-pnx4008/pm.c                        |  153 ----------
 arch/arm/mach-pnx4008/serial.c                    |   67 -----
 arch/arm/mach-pnx4008/sleep.S                     |  195 ------------
 arch/arm/mach-pnx4008/time.c                      |  134 ---------
 arch/arm/mach-pnx4008/time.h                      |   70 -----
 arch/arm/tools/mach-types                         |    1 -
 drivers/i2c/busses/Kconfig                        |    2 +-
 drivers/usb/Kconfig                               |    1 -
 drivers/usb/host/Kconfig                          |    2 +-
 drivers/usb/host/ohci-hcd.c                       |    2 +-
 drivers/usb/host/ohci-nxp.c                       |   84 +-----
 drivers/watchdog/Kconfig                          |    6 +-
 37 files changed, 7 insertions(+), 5258 deletions(-)
 delete mode 100644 arch/arm/configs/pnx4008_defconfig
 delete mode 100644 arch/arm/mach-pnx4008/Makefile
 delete mode 100644 arch/arm/mach-pnx4008/Makefile.boot
 delete mode 100644 arch/arm/mach-pnx4008/clock.c
 delete mode 100644 arch/arm/mach-pnx4008/clock.h
 delete mode 100644 arch/arm/mach-pnx4008/core.c
 delete mode 100644 arch/arm/mach-pnx4008/dma.c
 delete mode 100644 arch/arm/mach-pnx4008/gpio.c
 delete mode 100644 arch/arm/mach-pnx4008/i2c.c
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/clock.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/dma.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/irq.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/param.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/platform.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/pm.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/timex.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-pnx4008/irq.c
 delete mode 100644 arch/arm/mach-pnx4008/pm.c
 delete mode 100644 arch/arm/mach-pnx4008/serial.c
 delete mode 100644 arch/arm/mach-pnx4008/sleep.S
 delete mode 100644 arch/arm/mach-pnx4008/time.c
 delete mode 100644 arch/arm/mach-pnx4008/time.h


From Julia.Lawall at lip6.fr  Sun Aug 26 12:00:57 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 26 Aug 2012 18:00:57 +0200
Subject: [PATCH 5/13] arch/arm: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345996865-32082-6-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
clk_enable, and clk_disable and clk_unprepare.  They make the code more
concise, and ensure that clk_unprepare is called when clk_enable fails.

A simplified version of the semantic patch that introduces calls to these
functions is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e;
@@

- clk_prepare(e);
- clk_enable(e);
+ clk_prepare_enable(e);

@@
expression e;
@@

- clk_disable(e);
- clk_unprepare(e);
+ clk_disable_unprepare(e);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
 arch/arm/common/sa1111.c   |    3 +--
 arch/arm/common/timer-sp.c |   16 ++++------------
 arch/arm/kernel/smp_twd.c  |   13 +++----------
 3 files changed, 8 insertions(+), 24 deletions(-)

diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 9173d11..bd58414 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -834,8 +834,7 @@ static void __sa1111_remove(struct sa1111 *sachip)
 	sa1111_writel(0, irqbase + SA1111_WAKEEN0);
 	sa1111_writel(0, irqbase + SA1111_WAKEEN1);
 
-	clk_disable(sachip->clk);
-	clk_unprepare(sachip->clk);
+	clk_disable_unprepare(sachip->clk);
 
 	if (sachip->irq != NO_IRQ) {
 		irq_set_chained_handler(sachip->irq, NULL);
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index df13a3f..af1a4ab 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -42,17 +42,10 @@ static long __init sp804_get_clock_rate(const char *name)
 		return PTR_ERR(clk);
 	}
 
-	err = clk_prepare(clk);
+	err = clk_prepare_enable(clk);
 	if (err) {
-		pr_err("sp804: %s clock failed to prepare: %d\n", name, err);
-		clk_put(clk);
-		return err;
-	}
-
-	err = clk_enable(clk);
-	if (err) {
-		pr_err("sp804: %s clock failed to enable: %d\n", name, err);
-		clk_unprepare(clk);
+		pr_err("sp804: %s clock failed to prepare or to enable: %d\n",
+		       name, err);
 		clk_put(clk);
 		return err;
 	}
@@ -60,8 +53,7 @@ static long __init sp804_get_clock_rate(const char *name)
 	rate = clk_get_rate(clk);
 	if (rate < 0) {
 		pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
-		clk_disable(clk);
-		clk_unprepare(clk);
+		clk_disable_unprepare(clk);
 		clk_put(clk);
 	}
 
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index fef42b2..8c94b8b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -204,17 +204,10 @@ static struct clk *twd_get_clock(void)
 		return clk;
 	}
 
-	err = clk_prepare(clk);
+	err = clk_prepare_enable(clk);
 	if (err) {
-		pr_err("smp_twd: clock failed to prepare: %d\n", err);
-		clk_put(clk);
-		return ERR_PTR(err);
-	}
-
-	err = clk_enable(clk);
-	if (err) {
-		pr_err("smp_twd: clock failed to enable: %d\n", err);
-		clk_unprepare(clk);
+		pr_err("smp_twd: clock failed to prepare or to enable: %d\n",
+		       err);
 		clk_put(clk);
 		return ERR_PTR(err);
 	}



From Julia.Lawall at lip6.fr  Sun Aug 26 12:00:56 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 26 Aug 2012 18:00:56 +0200
Subject: [PATCH 4/13] i2c: sirf: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345996865-32082-5-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
clk_enable, and clk_disable and clk_unprepare.  They make the code more
concise, and ensure that clk_unprepare is called when clk_enable fails.

A simplified version of the semantic patch that introduces calls to these
functions is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e;
@@

- clk_prepare(e);
- clk_enable(e);
+ clk_prepare_enable(e);

@@
expression e;
@@

- clk_disable(e);
- clk_unprepare(e);
+ clk_disable_unprepare(e);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
 drivers/i2c/busses/i2c-sirf.c |   14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
index 5574a47..110660a 100644
--- a/drivers/i2c/busses/i2c-sirf.c
+++ b/drivers/i2c/busses/i2c-sirf.c
@@ -278,18 +278,12 @@ static int __devinit i2c_sirfsoc_probe(struct platform_device *pdev)
 		goto err_get_clk;
 	}
 
-	err = clk_prepare(clk);
+	err = clk_prepare_enable(clk);
 	if (err) {
-		dev_err(&pdev->dev, "Clock prepare failed\n");
+		dev_err(&pdev->dev, "Clock prepare or enable failed\n");
 		goto err_clk_prep;
 	}
 
-	err = clk_enable(clk);
-	if (err) {
-		dev_err(&pdev->dev, "Clock enable failed\n");
-		goto err_clk_en;
-	}
-
 	ctrl_speed = clk_get_rate(clk);
 
 	siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
@@ -376,9 +370,7 @@ static int __devinit i2c_sirfsoc_probe(struct platform_device *pdev)
 	return 0;
 
 out:
-	clk_disable(clk);
-err_clk_en:
-	clk_unprepare(clk);
+	clk_disable_unprepare(clk);
 err_clk_prep:
 	clk_put(clk);
 err_get_clk:



From Julia.Lawall at lip6.fr  Sun Aug 26 12:01:03 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 26 Aug 2012 18:01:03 +0200
Subject: [PATCH 11/13] arch/arm/mach-at91/gpio.c: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345996865-32082-12-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
clk_enable, and clk_disable and clk_unprepare.  They make the code more
concise, and ensure that clk_unprepare is called when clk_enable fails.

A simplified version of the semantic patch that introduces calls to these
functions is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e;
@@

- clk_prepare(e);
- clk_enable(e);
+ clk_prepare_enable(e);

@@
expression e;
@@

- clk_disable(e);
- clk_unprepare(e);
+ clk_disable_unprepare(e);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
 arch/arm/mach-at91/gpio.c |    9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..7760f35 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -956,19 +956,14 @@ static int __init at91_gpio_setup_clk(int idx)
 		goto err;
 	}
 
-	if (clk_prepare(at91_gpio->clock))
-		goto clk_prep_err;
-
 	/* enable PIO controller's clock */
-	if (clk_enable(at91_gpio->clock)) {
+	if (clk_prepare_enable(at91_gpio->clock)) {
 		pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
-		goto clk_err;
+		goto clk_prep_err;
 	}
 
 	return 0;
 
-clk_err:
-	clk_unprepare(at91_gpio->clock);
 clk_prep_err:
 	clk_put(at91_gpio->clock);
 err:



From Julia.Lawall at lip6.fr  Sun Aug 26 12:01:05 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 26 Aug 2012 18:01:05 +0200
Subject: [PATCH 13/13] drivers/rtc/rtc-coh901331.c: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1345996865-32082-14-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
clk_enable, and clk_disable and clk_unprepare.  They make the code more
concise, and ensure that clk_unprepare is called when clk_enable fails.

A simplified version of the semantic patch that introduces calls to these
functions is as follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e;
@@

- clk_prepare(e);
- clk_enable(e);
+ clk_prepare_enable(e);

@@
expression e;
@@

- clk_disable(e);
- clk_unprepare(e);
+ clk_disable_unprepare(e);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
I'm not sure about this.  Maybe it would be better to leave the disable and
unprepare separated, since there is no matching nearby clk_prepare.

 drivers/rtc/rtc-coh901331.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c
index 76b2156..c8115b8 100644
--- a/drivers/rtc/rtc-coh901331.c
+++ b/drivers/rtc/rtc-coh901331.c
@@ -276,8 +276,7 @@ static void coh901331_shutdown(struct platform_device *pdev)
 
 	clk_enable(rtap->clk);
 	writel(0, rtap->virtbase + COH901331_IRQ_MASK);
-	clk_disable(rtap->clk);
-	clk_unprepare(rtap->clk);
+	clk_disable_unprepare(rtap->clk);
 }
 
 static struct platform_driver coh901331_driver = {



From will.deacon at arm.com  Sun Aug 26 15:44:29 2012
From: will.deacon at arm.com (Will Deacon)
Date: Sun, 26 Aug 2012 20:44:29 +0100
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120810155128.GM2066@mudshark.cambridge.arm.com>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
Message-ID: <20120826194429.GA5010@mudshark.cambridge.arm.com>

Hello again,

By now I suspect most of you have either arrived in San Diego or are on
your way there at the moment. In preparation for the mini-summit starting
tomorrow morning, some useful links are:

  Agenda: https://sites.google.com/site/kernelsummit2012/workshops/arm
  IRC: #armsummit on freenode
  Etherpad: http://pad.linaro.org/arm-mini-summit-2012

David Brown is local to the area, so he can probably advise on places to
eat, visit etc.

We will be looking for people to take `moderator' roles in the topic
sessions, so if you feel that you have something to contribute, please
let us know before the session (otherwise we'll nominate people that we
know are involved in the subject :).

Looking forward to it,

Will


From ben.dooks at codethink.co.uk  Sun Aug 26 17:15:08 2012
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Sun, 26 Aug 2012 14:15:08 -0700
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <20120810155128.GM2066@mudshark.cambridge.arm.com>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
Message-ID: <8968365a6cd8adb4c4863b365facb2c2@codethink.co.uk>

On 10/08/2012 08:51, Will Deacon wrote:
> Hello,
>
> By now, those of you on CC should have received your invitation codes 
> for
> the ARM mini-summit in a couple of weeks time. If not, please contact 
> me
> separately and I'll look into it [Magnus -- I'm aware you haven't
> received anything yet, hopefully this will be fixed soon].
>
> The invitation email was slightly misleading as it only referred to 
> Tuesday
> 28 August, when in fact the mini-summit will be held on *both* Monday 
> 27
> and Tuesday 28. We will run topics in the morning (and allow an hour 
> in
> the afternoon for overflow discussion) and dedicate the rest of the 
> time
> to hacking. Initial topic proposals are:

Does this include the Sunday Evening event? If not, are people planning 
on
getting together this evening?


From jaccon.bastiaansen at gmail.com  Sun Aug 26 17:35:38 2012
From: jaccon.bastiaansen at gmail.com (Jaccon Bastiaansen)
Date: Sun, 26 Aug 2012 23:35:38 +0200
Subject: [PATCH] imx21ads : avoid overlapping static i/o mappings
Message-ID: <1346016938-28175-1-git-send-email-jaccon.bastiaansen@gmail.com>

The static I/O mappings for the cs89x0 ethernet controller and the
secondary AHB port 1 (SAHB1) overlapped, causing a kernel crash
at startup. This is fixed by mapping the cs89x0 to 0xf6000000 (which
is free to use according to arch/arm/plat-mxc/include/mach/hardware.h).

Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
---
 arch/arm/mach-imx/mach-mx21ads.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index ed22e3f..712c90e 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -31,7 +31,7 @@
 /*
  * Memory-mapped I/O on MX21ADS base board
  */
-#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_MMIO_BASE_ADDR   0xf6000000
 #define MX21ADS_MMIO_SIZE        0xc00000
 
 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-- 
1.7.1



From jaccon.bastiaansen at gmail.com  Sun Aug 26 17:39:06 2012
From: jaccon.bastiaansen at gmail.com (Jaccon Bastiaansen)
Date: Sun, 26 Aug 2012 23:39:06 +0200
Subject: [PATCH] cs89x0 : packet reception not working
Message-ID: <1346017146-28248-1-git-send-email-jaccon.bastiaansen@gmail.com>

The RxCFG register of the CS89x0 could be configured incorrectly
(because of misplaced parentheses), resulting in the disabling
of packet reception.

Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
---
 drivers/net/ethernet/cirrus/cs89x0.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/cirrus/cs89x0.c b/drivers/net/ethernet/cirrus/cs89x0.c
index 845b202..ea521fa 100644
--- a/drivers/net/ethernet/cirrus/cs89x0.c
+++ b/drivers/net/ethernet/cirrus/cs89x0.c
@@ -1261,10 +1261,10 @@ static void set_multicast_list(struct net_device *dev)
 	 * so we have to enable interrupts on them also
 	 */
 	writereg(dev, PP_RxCFG,
-		 (lp->curr_rx_cfg |
-		  (lp->rx_mode == RX_ALL_ACCEPT)
-		  ? (RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL)
-		  : 0));
+		 lp->curr_rx_cfg |
+		 (lp->rx_mode == RX_ALL_ACCEPT
+		 ? (RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL)
+		 : 0));
 	spin_unlock_irqrestore(&lp->lock, flags);
 }
 
-- 
1.7.1



From hein_tibosch at yahoo.es  Sun Aug 26 16:22:02 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Mon, 27 Aug 2012 04:22:02 +0800
Subject: [PATCH 2/2] mmc: atmel-mci: AP700x PDC is not connected to MCI
Message-ID: <503A856A.9020303@yahoo.es>

Earlier, atmel-mci was adapter to make use of the peripheral DMA
controller (PDC), in case normal DMA wouldn't work.
( http://comments.gmane.org/gmane.linux.kernel.mmc/9403 )
This works OK on ARM platforms (AT91), but it broke the driver
for AVR32, the AP700x.
This patch makes the use of PDC depend on CONFIG_AVR32

Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>

---
 drivers/mmc/host/atmel-mci-regs.h |    7 +++++++
 drivers/mmc/host/atmel-mci.c      |    2 +-
 2 files changed, 8 insertions(+), 1 deletions(-)
 
diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index ab56f7d..c97001e 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -140,6 +140,13 @@
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
 
+/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
+#ifdef CONFIG_AVR32
+#	define ATMCI_PDC_CONNECTED	0
+#else
+#	define ATMCI_PDC_CONNECTED	1
+#endif
+
 /*
  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 66e9fdc..702ab5c 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2205,7 +2205,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 			"version: 0x%x\n", version);
 
 	host->caps.has_dma_conf_reg = 0;
-	host->caps.has_pdc = 1;
+	host->caps.has_pdc = ATMCI_PDC_CONNECTED;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
 	host->caps.has_highspeed = 0;
-- 
1.7.8.0



From hein_tibosch at yahoo.es  Sun Aug 26 16:36:00 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Mon, 27 Aug 2012 04:36:00 +0800
Subject: [PATCH 0/2] mmc: atmel-mci: repair driver for use with AVR32 (AP7000)
Message-ID: <503A88B0.30103@yahoo.es>

Due to changes after 2.6.38, the drivers atmel-mci and dw_dmac got broken
for the AVR32 platform: the AP7000.

These two patches repair the atmel-mci driver

Thanks to Ludovic for reviewing/styling!

Hein Tibosch (2):

  mmc: atmel-mci: DMA can be used with other controller
  mmc: atmel-mci: AP700x PDC is not connected to MCI

 drivers/mmc/host/atmel-mci-regs.h |    7 +++++++
 drivers/mmc/host/atmel-mci.c      |   23 ++++++++++-------------
 2 files changed, 17 insertions(+), 13 deletions(-)

-- 



From olof at lixom.net  Sun Aug 26 18:06:36 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 26 Aug 2012 15:06:36 -0700
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <8968365a6cd8adb4c4863b365facb2c2@codethink.co.uk>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
 <8968365a6cd8adb4c4863b365facb2c2@codethink.co.uk>
Message-ID: <35F49889-05C9-4BB3-B1B7-4A733D48A96D@lixom.net>





On Aug 26, 2012, at 2:15 PM, Ben Dooks <ben.dooks at codethink.co.uk> wrote:

> On 10/08/2012 08:51, Will Deacon wrote:
>> Hello,
>> 
>> By now, those of you on CC should have received your invitation codes for
>> the ARM mini-summit in a couple of weeks time. If not, please contact me
>> separately and I'll look into it [Magnus -- I'm aware you haven't
>> received anything yet, hopefully this will be fixed soon].
>> 
>> The invitation email was slightly misleading as it only referred to Tuesday
>> 28 August, when in fact the mini-summit will be held on *both* Monday 27
>> and Tuesday 28. We will run topics in the morning (and allow an hour in
>> the afternoon for overflow discussion) and dedicate the rest of the time
>> to hacking. Initial topic proposals are:
> 
> Does this include the Sunday Evening event? If not, are people planning on
> getting together this evening?

ARM summit members are not invited to any KS events besides the one on Tuesday night as far as I know. I will arrive late tonight myself, so I'll see everyone in the morning.

-Olof

From hein_tibosch at yahoo.es  Sun Aug 26 16:20:59 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Mon, 27 Aug 2012 04:20:59 +0800
Subject: [PATCH 1/2] mmc: atmel-mci: DMA can be used with other controller
Message-ID: <503A852B.8010902@yahoo.es>

After the latest changes to atmel-mci, it could not be used with
DMA on the AVR32 platform. This patch will allow to use DMA again
and it will avoid access to MCI register ATMCI_DMA.

Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>

---
 drivers/mmc/host/atmel-mci.c |   21 +++++++++------------
 1 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index f2c115e..66e9fdc 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -71,7 +71,7 @@ enum atmci_pdc_buf {
 };
 
 struct atmel_mci_caps {
-	bool    has_dma;
+	bool    has_dma_conf_reg;
 	bool    has_pdc;
 	bool    has_cfg_reg;
 	bool    has_cstor_reg;
@@ -411,7 +411,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
 	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 
-	if (host->caps.has_dma) {
+	if (host->caps.has_dma_conf_reg) {
 		u32 val;
 
 		val = buf[ATMCI_DMA / 4];
@@ -767,7 +767,7 @@ static void atmci_dma_complete(void *arg)
 
 	dev_vdbg(&host->pdev->dev, "DMA complete\n");
 
-	if (host->caps.has_dma)
+	if (host->caps.has_dma_conf_reg)
 		/* Disable DMA hardware handshaking on MCI */
 		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 
@@ -954,7 +954,9 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 		maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
 	}
 
-	atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | ATMCI_DMAEN);
+	if (host->caps.has_dma_conf_reg)
+		atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
+			ATMCI_DMAEN);
 
 	sglen = dma_map_sg(chan->device->dev, data->sg,
 			data->sg_len, direction);
@@ -2202,7 +2204,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 	dev_info(&host->pdev->dev,
 			"version: 0x%x\n", version);
 
-	host->caps.has_dma = 0;
+	host->caps.has_dma_conf_reg = 0;
 	host->caps.has_pdc = 1;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
@@ -2219,12 +2221,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 		host->caps.has_odd_clk_div = 1;
 	case 0x400:
 	case 0x300:
-#ifdef CONFIG_AT_HDMAC
-		host->caps.has_dma = 1;
-#else
-		dev_info(&host->pdev->dev,
-			"has dma capability but dma engine is not selected, then use pio\n");
-#endif
+		host->caps.has_dma_conf_reg = 1;
 		host->caps.has_pdc = 0;
 		host->caps.has_cfg_reg = 1;
 		host->caps.has_cstor_reg = 1;
@@ -2298,7 +2295,7 @@ static int __init atmci_probe(struct platform_device *pdev)
 
 	/* Get MCI capabilities and set operations according to it */
 	atmci_get_cap(host);
-	if (host->caps.has_dma && atmci_configure_dma(host)) {
+	if (atmci_configure_dma(host)) {
 		host->prepare_data = &atmci_prepare_data_dma;
 		host->submit_data = &atmci_submit_data_dma;
 		host->stop_transfer = &atmci_stop_transfer_dma;
-- 
1.7.8.0



From joe at perches.com  Sun Aug 26 18:26:01 2012
From: joe at perches.com (Joe Perches)
Date: Sun, 26 Aug 2012 15:26:01 -0700
Subject: [PATCH] cs89x0 : packet reception not working
In-Reply-To: <1346017146-28248-1-git-send-email-jaccon.bastiaansen@gmail.com>
References: <1346017146-28248-1-git-send-email-jaccon.bastiaansen@gmail.com>
Message-ID: <1346019961.2064.4.camel@joe2Laptop>

On Sun, 2012-08-26 at 23:39 +0200, Jaccon Bastiaansen wrote:
> The RxCFG register of the CS89x0 could be configured incorrectly
> (because of misplaced parentheses), resulting in the disabling
> of packet reception.

Thanks.

> diff --git a/drivers/net/ethernet/cirrus/cs89x0.c b/drivers/net/ethernet/cirrus/cs89x0.c
[]
> @@ -1261,10 +1261,10 @@ static void set_multicast_list(struct net_device *dev)
>  	 * so we have to enable interrupts on them also
>  	 */
>  	writereg(dev, PP_RxCFG,
> -		 (lp->curr_rx_cfg |
> -		  (lp->rx_mode == RX_ALL_ACCEPT)
> -		  ? (RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL)
> -		  : 0));
> +		 lp->curr_rx_cfg |
> +		 (lp->rx_mode == RX_ALL_ACCEPT
> +		 ? (RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL)
> +		 : 0));
>  	spin_unlock_irqrestore(&lp->lock, flags);
>  }

Perhaps it would be better to use something like:

	int cfg = lp->curr_rx_cfg;

	if (lp->rx_mode == RX_ALL_ACCEPT)
		cfg |= RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL;

	writereg(dev, PP_RxCFG, cfg);



From davidb at codeaurora.org  Sun Aug 26 18:32:02 2012
From: davidb at codeaurora.org (David Brown)
Date: Sun, 26 Aug 2012 15:32:02 -0700
Subject: Preliminary topic proposals for the ARM mini-summit
In-Reply-To: <8968365a6cd8adb4c4863b365facb2c2@codethink.co.uk>
References: <20120810155128.GM2066@mudshark.cambridge.arm.com>
 <8968365a6cd8adb4c4863b365facb2c2@codethink.co.uk>
Message-ID: <20120826223202.GA17211@codeaurora.org>

On Sun, Aug 26, 2012 at 02:15:08PM -0700, Ben Dooks wrote:

> Does this include the Sunday Evening event? If not, are people
> planning on getting together this evening?

I hadn't planned on driving down just for this evening (it's about 30
minutes away for me).

Ping me on IRC if anyone needs any ideas for dining.  Unfortunately,
nothing is particularly close to the hotel, but there are many things
about 5 miles away in several directions.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From ccross at android.com  Sun Aug 26 18:46:56 2012
From: ccross at android.com (Colin Cross)
Date: Sun, 26 Aug 2012 15:46:56 -0700
Subject: [PATCH 2/2] ARM: unwind: enable dumping stacks for SMP && ARM_UNWIND
In-Reply-To: <1346021216-21979-1-git-send-email-ccross@android.com>
References: <1346021216-21979-1-git-send-email-ccross@android.com>
Message-ID: <1346021216-21979-3-git-send-email-ccross@android.com>

Unwinding with CONFIG_ARM_UNWIND is much more complicated than
unwinding with CONFIG_FRAME_POINTER, but there are only a few points
that require validation in order to avoid faults or infinite loops.
Avoiding faults is easy by adding checks to verify that all accesses
relative to the frame's stack pointer remain inside the stack.

When CONFIG_FRAME_POINTER is not set it is possible for two frames to
have the same SP, so there is no way to avoid repeated calls to
unwind_frame continuing forever.

Signed-off-by: Colin Cross <ccross at android.com>
---
 arch/arm/kernel/stacktrace.c |   12 ------------
 arch/arm/kernel/unwind.c     |   31 +++++++++++++++++++++++++++----
 2 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 45e6b7e..f51dd68 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -105,23 +105,11 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 	data.skip = trace->skip;
 
 	if (tsk != current) {
-#if defined(CONFIG_SMP) || \
-	(defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND))
-		/*
-		 * What guarantees do we have here that 'tsk' is not
-		 * running on another CPU?  For now, ignore it as we
-		 * can't guarantee we won't explode.
-		 */
-		if (trace->nr_entries < trace->max_entries)
-			trace->entries[trace->nr_entries++] = ULONG_MAX;
-		return;
-#else
 		data.no_sched_functions = 1;
 		frame.fp = thread_saved_fp(tsk);
 		frame.sp = thread_saved_sp(tsk);
 		frame.lr = 0;		/* recovered from the stack */
 		frame.pc = thread_saved_pc(tsk);
-#endif
 	} else {
 		register unsigned long current_sp asm ("sp");
 
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
 00df012..b3a09ad 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -98,6 +98,16 @@ enum regs {
 	(unsigned long)(ptr) + offset;			\
 })
 
+static bool valid_stack_addr(unsigned long sp, unsigned long *vsp)
+{
+	unsigned long low;
+	unsigned long high;
+
+	low = round_down(sp, THREAD_SIZE) + sizeof(struct thread_info);
+	high = ALIGN(sp, THREAD_SIZE);
+	return ((unsigned long)vsp >= low && (unsigned long)vsp < high);
+}
+
 /*
  * Binary search in the unwind index. The entries are
  * guaranteed to be sorted in ascending order by the linker.
@@ -241,6 +251,7 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
 static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 {
 	unsigned long insn = unwind_get_byte(ctrl);
+	unsigned long orig_sp = ctrl->vrs[SP];
 
 	pr_debug("%s: insn = %08lx\n", __func__, insn);
 
@@ -264,8 +275,11 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 		/* pop R4-R15 according to mask */
 		load_sp = mask & (1 << (13 - 4));
 		while (mask) {
-			if (mask & 1)
+			if (mask & 1) {
+				if (!valid_stack_addr(orig_sp, vsp))
+					return -URC_FAILURE;
 				ctrl->vrs[reg] = *vsp++;
+			}
 			mask >>= 1;
 			reg++;
 		}
@@ -279,10 +293,16 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 		int reg;
 
 		/* pop R4-R[4+bbb] */
-		for (reg = 4; reg <= 4 + (insn & 7); reg++)
+		for (reg = 4; reg <= 4 + (insn & 7); reg++) {
+			if (!valid_stack_addr(orig_sp, vsp))
+				return -URC_FAILURE;
 			ctrl->vrs[reg] = *vsp++;
-		if (insn & 0x80)
+		}
+		if (insn & 0x80) {
+			if (!valid_stack_addr(orig_sp, vsp))
+				return -URC_FAILURE;
 			ctrl->vrs[14] = *vsp++;
+		}
 		ctrl->vrs[SP] = (unsigned long)vsp;
 	} else if (insn == 0xb0) {
 		if (ctrl->vrs[PC] == 0)
@@ -302,8 +322,11 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 
 		/* pop R0-R3 according to mask */
 		while (mask) {
-			if (mask & 1)
+			if (mask & 1) {
+				if (!valid_stack_addr(orig_sp, vsp))
+					return -URC_FAILURE;
 				ctrl->vrs[reg] = *vsp++;
+			}
 			mask >>= 1;
 			reg++;
 		}
-- 
1.7.7.3



From ccross at android.com  Sun Aug 26 18:46:55 2012
From: ccross at android.com (Colin Cross)
Date: Sun, 26 Aug 2012 15:46:55 -0700
Subject: [PATCH 1/2] ARM: stacktrace: enable dumping stacks for SMP &&
 FRAME_POINTER
In-Reply-To: <1346021216-21979-1-git-send-email-ccross@android.com>
References: <1346021216-21979-1-git-send-email-ccross@android.com>
Message-ID: <1346021216-21979-2-git-send-email-ccross@android.com>

Dumping stacktraces is currently disabled in ARM SMP for all tasks
except the current task due to the worry that the task may be running
on another CPU and that the unwinder may be unstable when presented
with a stack that is being modified.

Unwinding with CONFIG_FRAME_POINTER is fairly simple compared to
when CONFIG_ARM_UNWIND is set.  The next frame's FP and SP registers
are read from the stack and can be validated against the current
values to ensure that they do not leave the stack and make progress
towards the upper end of the stack.  This guarantees that accesses
do not fault and that execution is bounded.

Add additional validations to unwind_frame and enable dumping
stacktraces when CONFIG_SMP is set if CONFIG_FRAME_POINTER is set.

Signed-off-by: Colin Cross <ccross at android.com>
---
 arch/arm/kernel/stacktrace.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 00f79e5..45e6b7e 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -34,11 +34,24 @@ int notrace unwind_frame(struct stackframe *frame)
 	if (fp < (low + 12) || fp + 4 >= high)
 		return -EINVAL;
 
+	if (fp % 4 != 0)
+		return -EINVAL;
+
 	/* restore the registers from the stack frame */
 	frame->fp = *(unsigned long *)(fp - 12);
 	frame->sp = *(unsigned long *)(fp - 8);
 	frame->pc = *(unsigned long *)(fp - 4);
 
+	/*
+	 * ensure the next stack pointer is above this one to guarantee
+	 * bounded execution
+	 */
+	if (frame->sp < fp || frame->sp > high)
+		return -EINVAL;
+
+	if (frame->sp % 4 != 0)
+		return -EINVAL;
+
 	return 0;
 }
 #endif
@@ -92,7 +105,8 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 	data.skip = trace->skip;
 
 	if (tsk != current) {
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) || \
+	(defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND))
 		/*
 		 * What guarantees do we have here that 'tsk' is not
 		 * running on another CPU?  For now, ignore it as we
-- 
1.7.7.3



From ccross at android.com  Sun Aug 26 18:46:54 2012
From: ccross at android.com (Colin Cross)
Date: Sun, 26 Aug 2012 15:46:54 -0700
Subject: [PATCH 0/2] ARM: enable dumping stacks for CONFIG_SMP
Message-ID: <1346021216-21979-1-git-send-email-ccross@android.com>

This topic has come up before, see
http://comments.gmane.org/gmane.linux.ports.arm.kernel/102458
for the previous discussion.

SMP is now the norm for new ARM systems, and the limitation that
CONFIG_STACKTRACE doesn't work for tasks besides 'current' causes
problems.  The particular case I'm dealing with is automated
debugging information collected from /proc/<pid>/stack when
userspace detects a process is not responding.

Dumping stacktraces is currently disabled due to the worry that the
task may be running on another CPU and that the unwinder may be
unstable when presented with a stack that is being modified.  I have
attempted to harden the frame pointer based unwinder and the unwind
table based unwinder against invalid stacks.  I separated the two
into individual patches, as I expect the patch to the table unwinder
to be more controversial than the frame pointer unwinder.

Even without the hardening, unwinding a stack for a running process
is not completely untested.  When CONFIG_ARM_UNWIND is enabled,
sysrq-t calls unwind_backtrace for all tasks including running ones.
In addition, any callers to unwind_frame with preemption enabled,
including proc_pid_stack, could see a modified stack even on a UP
system (pointed out by Rabin Vincent the last time this topic came
up).

 arch/arm/kernel/stacktrace.c |   24 +++++++++++++-----------
 arch/arm/kernel/unwind.c     |   31 +++++++++++++++++++++++++++----
 2 files changed, 40 insertions(+), 15 deletions(-)


From xiechao.mail at gmail.com  Sun Aug 26 21:19:02 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 09:19:02 +0800
Subject: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <20120825002151.18366.99434@nucleus>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
 <20120825002151.18366.99434@nucleus>
Message-ID: <CADApbehotHB7JSCHdo_eoTb08C5Pe6ewh7whwckQTyuCcMM=BQ@mail.gmail.com>

On Sat, Aug 25, 2012 at 8:21 AM, Mike Turquette <mturquette at linaro.org> wrote:
> Quoting Chao Xie (2012-08-19 19:55:10)
>> From: Chao Xie <chao.xie at marvell.com>
>>  arch/arm/mach-mmp/Kconfig    |    3 +
>>  drivers/clk/Makefile         |    3 +
>>  drivers/clk/mmp/Makefile     |    9 +
>>  drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++++
>>  drivers/clk/mmp/clk-apmu.c   |   97 +++++++++
>>  drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++++
>>  drivers/clk/mmp/clk-mmp2.c   |  449 ++++++++++++++++++++++++++++++++++++++++++
>>  drivers/clk/mmp/clk-pxa168.c |  346 ++++++++++++++++++++++++++++++++
>>  drivers/clk/mmp/clk-pxa910.c |  320 ++++++++++++++++++++++++++++++
>>  drivers/clk/mmp/clk.h        |   35 ++++
>
> Looks like you are not removing your arch/arm/mach-mmp/clock.c.  Is that
> intentional?
>
> When I apply your series against v3.6-rc3 I find that compilation breaks
> with mmp2_defconfig due to conflicting definitions for the clk api
> (clk_enable, clk_set_rate, etc).  This is not surprising since your
> legacy clock code is neither deleted nor removed from compilation
> conditionally by checking for CONFIG_COMMON_CLK.
>
> Did I somehow manage to misapply your patches or should your patches
> have removed the arch-specific clock framework as well?
>
hi, Mike
Yes. There are some patches for seperate the original clock code in arch.
I had sent these patches before, but it seems that too many patches
sent, and haojian missed it.
I will sent out the patches for arch today. Thanks.

> Regards,
> Mike
>
>>  10 files changed, 1567 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/clk/mmp/Makefile
>>  create mode 100644 drivers/clk/mmp/clk-apbc.c
>>  create mode 100644 drivers/clk/mmp/clk-apmu.c
>>  create mode 100644 drivers/clk/mmp/clk-frac.c
>>  create mode 100644 drivers/clk/mmp/clk-mmp2.c
>>  create mode 100644 drivers/clk/mmp/clk-pxa168.c
>>  create mode 100644 drivers/clk/mmp/clk-pxa910.c
>>  create mode 100644 drivers/clk/mmp/clk.h


From 21cnbao at gmail.com  Sun Aug 26 21:44:54 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Mon, 27 Aug 2012 09:44:54 +0800
Subject: [PATCH 4/13] i2c: sirf: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-5-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345996865-32082-5-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <CAGsJ_4zSsnyJ0sn385g_1OvGXTwXbW-E1P_o7EWtM75+CSxDww@mail.gmail.com>

2012/8/27 Julia Lawall <Julia.Lawall at lip6.fr>:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
>
> Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
> clk_enable, and clk_disable and clk_unprepare.  They make the code more
> concise, and ensure that clk_unprepare is called when clk_enable fails.
>
> A simplified version of the semantic patch that introduces calls to these
> functions is as follows: (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @@
> expression e;
> @@
>
> - clk_prepare(e);
> - clk_enable(e);
> + clk_prepare_enable(e);
>
> @@
> expression e;
> @@
>
> - clk_disable(e);
> - clk_unprepare(e);
> + clk_disable_unprepare(e);
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

Acked-by: Barry Song <21cnbao at gmail.com>


From omycle at gmail.com  Sun Aug 26 22:42:40 2012
From: omycle at gmail.com (Li Haifeng)
Date: Mon, 27 Aug 2012 10:42:40 +0800
Subject: For buddy system initialization, the holes between banks adjacent
 will be released to buddy allocator?
In-Reply-To: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>
References: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>
Message-ID: <CAFNq8R7fCyD5P4mAA8LGzcOvVynSJa8mOBDwrLOF9mVvo9q5VA@mail.gmail.com>

Just now, I tested it on my ARM development board.

The holes between banks does be released to buddy allocator. And the
buddy system will allocate holes for thread, which will cause fault.
Is it right?

2012/8/26 Li Haifeng <omycle at gmail.com>:
> Sorry to disturb you again.
>
> I am still confused about holes between banks adjacent.
>
> The lines 180~181 get the low memory's range, and the range includes holes.
> But while releasing the memory to buddy allocator, the code doesn't
> prevent the holes from releasing to the buddy allocator.
>
> 172 static unsigned long __init free_all_bootmem_core(bootmem_data_t *bdata)
> 173 {
> 174         struct page *page;
> 175         unsigned long start, end, pages, count = 0;
> 176
> 177         if (!bdata->node_bootmem_map)
> 178                 return 0;
> 179
> 180         start = bdata->node_min_pfn;
> 181         end = bdata->node_low_pfn;
> 182
> 183         bdebug("nid=%td start=%lx end=%lx\n",
> 184                 bdata - bootmem_node_data, start, end);
> 185
> 186         while (start < end) {
> 187                 unsigned long *map, idx, vec;
> 188
> 189                 map = bdata->node_bootmem_map;
> 190                 idx = start - bdata->node_min_pfn;
> 191                 vec = ~map[idx / BITS_PER_LONG];
> 192                 /*
> 193                  * If we have a properly aligned and fully unreserved
> 194                  * BITS_PER_LONG block of pages in front of us, free
> 195                  * it in one go.
> 196                  */
> 197                 if (IS_ALIGNED(start, BITS_PER_LONG) && vec == ~0UL) {
> 198                         int order = ilog2(BITS_PER_LONG);
> 199
> 200                         __free_pages_bootmem(pfn_to_page(start), order);
> 201                         count += BITS_PER_LONG;
> 202                         start += BITS_PER_LONG;
> 203                 } else {
> 204                         unsigned long off = 0;
> 205
> 206                         while (vec && off < BITS_PER_LONG) {
> 207                                 if (vec & 1) {
> 208                                         page = pfn_to_page(start + off);
> 209                                         __free_pages_bootmem(page, 0);
> 210                                         count++;
> 211                                 }
> 212                                 vec >>= 1;
> 213                                 off++;
> 214                         }
> 215                         start = ALIGN(start + 1, BITS_PER_LONG);
> 216                 }
> 217         }
> 218
> 219         page = virt_to_page(bdata->node_bootmem_map);
> 220         pages = bdata->node_low_pfn - bdata->node_min_pfn;
> 221         pages = bootmem_bootmap_pages(pages);
> 222         count += pages;
> 223         while (pages--)
> 224                 __free_pages_bootmem(page++, 0);
> 225
> 226         bdebug("nid=%td released=%lx\n", bdata - bootmem_node_data, count);
> 227
> 228         return count;
> 229 }


From xiechao.mail at gmail.com  Sun Aug 26 22:53:59 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 10:53:59 +0800
Subject: [PATCH 1/5] arm: mmp: make private clock definition exclude from
 common clock
Message-ID: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

the clock.c is mmp private implementation, make it excluded
from common clock framework

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Makefile |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e..815c3e7 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,16 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y				+= common.o clock.o devices.o time.o irq.o
+obj-y				+= common.o devices.o time.o irq.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)	+= pxa168.o
 obj-$(CONFIG_CPU_PXA910)	+= pxa910.o
 obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o
 
+ifeq ($(CONFIG_COMMON_CLK), )
+obj-y				+= clock.o
+endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o
 obj-$(CONFIG_CPU_MMP2)		+= pm-mmp2.o
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 26 22:54:00 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 10:54:00 +0800
Subject: [PATCH 2/5] arm: mmp: move pxa168 clock definition to separated file
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1346036043-20115-2-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

move pxa168 clock definition to another file. Then pxa168 can
choose common clock framework or private clock framework.

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Makefile       |    1 +
 arch/arm/mach-mmp/clock-pxa168.c |   91 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mmp/common.h       |    1 +
 arch/arm/mach-mmp/pxa168.c       |   58 ++----------------------
 4 files changed, 98 insertions(+), 53 deletions(-)
 create mode 100644 arch/arm/mach-mmp/clock-pxa168.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 815c3e7..bb63f86 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o
 
 ifeq ($(CONFIG_COMMON_CLK), )
 obj-y				+= clock.o
+obj-$(CONFIG_CPU_PXA168)	+= clock-pxa168.o
 endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 0000000..5e6c18c
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_UART1	APBC_REG(0x000)
+#define APBC_UART2	APBC_REG(0x004)
+#define APBC_GPIO	APBC_REG(0x008)
+#define APBC_PWM1	APBC_REG(0x00c)
+#define APBC_PWM2	APBC_REG(0x010)
+#define APBC_PWM3	APBC_REG(0x014)
+#define APBC_PWM4	APBC_REG(0x018)
+#define APBC_RTC	APBC_REG(0x028)
+#define APBC_TWSI0	APBC_REG(0x02c)
+#define APBC_KPC	APBC_REG(0x030)
+#define APBC_TWSI1	APBC_REG(0x06c)
+#define APBC_UART3	APBC_REG(0x070)
+#define APBC_SSP1	APBC_REG(0x81c)
+#define APBC_SSP2	APBC_REG(0x820)
+#define APBC_SSP3	APBC_REG(0x84c)
+#define APBC_SSP4	APBC_REG(0x858)
+#define APBC_SSP5	APBC_REG(0x85c)
+
+#define APMU_NAND	APMU_REG(0x060)
+#define APMU_LCD	APMU_REG(0x04c)
+#define APMU_ETH	APMU_REG(0x0fc)
+#define APMU_USB	APMU_REG(0x05c)
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 14745600);
+static APBC_CLK(uart2, UART2, 1, 14745600);
+static APBC_CLK(uart3, UART3, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(ssp1, SSP1, 4, 0);
+static APBC_CLK(ssp2, SSP2, 4, 0);
+static APBC_CLK(ssp3, SSP3, 4, 0);
+static APBC_CLK(ssp4, SSP4, 4, 0);
+static APBC_CLK(ssp5, SSP5, 4, 0);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(keypad, KPC, 0, 32000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
+static APMU_CLK(usb, USB, 0x12, 0);
+
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+	INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+	INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+	INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+	INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+	INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+	INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+	INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+	INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+	INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+	INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+	INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
+	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+	INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+	INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+	INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
+	INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
+	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa168_clk_init(void)
+{
+	clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1..e47f73f 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,4 @@ extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
+extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c..b7f074f 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/addr-map.h>
 #include <mach/cputype.h>
+#include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
 	icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
-static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
-static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
-static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
-static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
-	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-	INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
-	INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
-	INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
-	INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
-	INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
-	INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
-	INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
-	INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
-	INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
-	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-	INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
-	INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
-	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa168_init(void)
 {
 	if (cpu_is_pxa168()) {
 		mfp_init_base(MFPR_VIRT_BASE);
 		mfp_init_addr(pxa168_mfp_addr_map);
 		pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-		clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+		pxa168_clk_init();
 	}
 
 	return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS	APBC_REG(0x34)
 
 static void __init pxa168_timer_init(void)
 {
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
 	 * ourselves instead of using clk_* API. Clock rate is defined
 	 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
 	 */
-	__raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+	__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
 	/* 3.25MHz, bus/functional clock enabled, release reset */
-	__raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+	__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
 	timer_init(IRQ_PXA168_TIMER1);
 }
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 26 22:54:01 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 10:54:01 +0800
Subject: [PATCH 3/5] arm: mmp: move pxa910 clock definition to separated file
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1346036043-20115-3-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

move pxa910 clock definition to another file. Then pxa910 can
choose common clock framework or private clock framework.

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Makefile       |    1 +
 arch/arm/mach-mmp/clock-pxa910.c |   67 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mmp/common.h       |    1 +
 arch/arm/mach-mmp/pxa910.c       |   40 ++--------------------
 4 files changed, 73 insertions(+), 36 deletions(-)
 create mode 100644 arch/arm/mach-mmp/clock-pxa910.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index bb63f86..ac0e885 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_MMP2)		+= mmp2.o sram.o
 ifeq ($(CONFIG_COMMON_CLK), )
 obj-y				+= clock.o
 obj-$(CONFIG_CPU_PXA168)	+= clock-pxa168.o
+obj-$(CONFIG_CPU_PXA910)	+= clock-pxa910.o
 endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 0000000..933ea71
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_UART0	APBC_REG(0x000)
+#define APBC_UART1	APBC_REG(0x004)
+#define APBC_GPIO	APBC_REG(0x008)
+#define APBC_PWM1	APBC_REG(0x00c)
+#define APBC_PWM2	APBC_REG(0x010)
+#define APBC_PWM3	APBC_REG(0x014)
+#define APBC_PWM4	APBC_REG(0x018)
+#define APBC_SSP1	APBC_REG(0x01c)
+#define APBC_SSP2	APBC_REG(0x020)
+#define APBC_RTC	APBC_REG(0x028)
+#define APBC_TWSI0	APBC_REG(0x02c)
+#define APBC_KPC	APBC_REG(0x030)
+#define APBC_SSP3	APBC_REG(0x04c)
+#define APBC_TWSI1	APBC_REG(0x06c)
+
+#define APMU_NAND	APMU_REG(0x060)
+#define APMU_USB	APMU_REG(0x05c)
+
+static APBC_CLK(uart1, UART0, 1, 14745600);
+static APBC_CLK(uart2, UART1, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+	INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+	INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+	INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+	INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+	INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+	INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
+	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa910_clk_init(void)
+{
+	clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index e47f73f..1cad41b 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -8,3 +8,4 @@ extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
 extern void __init pxa168_clk_init(void);
+extern void __init pxa910_clk_init(void);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9..7d84521 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -17,7 +17,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -25,7 +24,6 @@
 #include <mach/devices.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE	(APB_VIRT_BASE + 0x1e000)
 
@@ -82,44 +80,13 @@ void __init pxa910_init_irq(void)
 	icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
-static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
-static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
-	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-	INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
-	INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
-	INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
-	INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
-	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-	INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
-	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa910_init(void)
 {
 	if (cpu_is_pxa910()) {
 		mfp_init_base(MFPR_VIRT_BASE);
 		mfp_init_addr(pxa910_mfp_addr_map);
 		pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-		clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+		pxa910_clk_init();
 	}
 
 	return 0;
@@ -128,12 +95,13 @@ postcore_initcall(pxa910_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS	APBC_REG(0x34)
 
 static void __init pxa910_timer_init(void)
 {
 	/* reset and configure */
-	__raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
-	__raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+	__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
+	__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
 	timer_init(IRQ_PXA910_AP1_TIMER1);
 }
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 26 22:54:02 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 10:54:02 +0800
Subject: [PATCH 4/5] arm: mmp: move mmp2 clock definition to separated file
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1346036043-20115-4-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

move mmp2 clock definition to another file. Then mmp2 can
choose common clock framework or private clock framework.

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/Makefile     |    1 +
 arch/arm/mach-mmp/clock-mmp2.c |  111 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mmp/common.h     |    1 +
 arch/arm/mach-mmp/mmp2.c       |   71 ++------------------------
 4 files changed, 118 insertions(+), 66 deletions(-)
 create mode 100644 arch/arm/mach-mmp/clock-mmp2.c

diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index ac0e885..095c155 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -13,6 +13,7 @@ ifeq ($(CONFIG_COMMON_CLK), )
 obj-y				+= clock.o
 obj-$(CONFIG_CPU_PXA168)	+= clock-pxa168.o
 obj-$(CONFIG_CPU_PXA910)	+= clock-pxa910.o
+obj-$(CONFIG_CPU_MMP2)		+= clock-mmp2.o
 endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)	+= pm-pxa910.o
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 0000000..21d2200
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_RTC	APBC_REG(0x000)
+#define APBC_TWSI1	APBC_REG(0x004)
+#define APBC_TWSI2	APBC_REG(0x008)
+#define APBC_TWSI3	APBC_REG(0x00c)
+#define APBC_TWSI4	APBC_REG(0x010)
+#define APBC_KPC	APBC_REG(0x018)
+#define APBC_UART1	APBC_REG(0x02c)
+#define APBC_UART2	APBC_REG(0x030)
+#define APBC_UART3	APBC_REG(0x034)
+#define APBC_GPIO	APBC_REG(0x038)
+#define APBC_PWM0	APBC_REG(0x03c)
+#define APBC_PWM1	APBC_REG(0x040)
+#define APBC_PWM2	APBC_REG(0x044)
+#define APBC_PWM3	APBC_REG(0x048)
+#define APBC_SSP0	APBC_REG(0x04c)
+#define APBC_SSP1	APBC_REG(0x050)
+#define APBC_SSP2	APBC_REG(0x054)
+#define APBC_SSP3	APBC_REG(0x058)
+#define APBC_SSP4	APBC_REG(0x05c)
+#define APBC_SSP5	APBC_REG(0x060)
+#define APBC_TWSI5	APBC_REG(0x07c)
+#define APBC_TWSI6	APBC_REG(0x080)
+#define APBC_UART4	APBC_REG(0x088)
+
+#define APMU_USB	APMU_REG(0x05c)
+#define APMU_NAND	APMU_REG(0x060)
+#define APMU_SDH0	APMU_REG(0x054)
+#define APMU_SDH1	APMU_REG(0x058)
+#define APMU_SDH2	APMU_REG(0x0e8)
+#define APMU_SDH3	APMU_REG(0x0ec)
+
+static void sdhc_clk_enable(struct clk *clk)
+{
+	uint32_t clk_rst;
+
+	clk_rst  =  __raw_readl(clk->clk_rst);
+	clk_rst |= clk->enable_val;
+	__raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+	uint32_t clk_rst;
+
+	clk_rst  =  __raw_readl(clk->clk_rst);
+	clk_rst &= ~clk->enable_val;
+	__raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+	.enable		= sdhc_clk_enable,
+	.disable	= sdhc_clk_disable,
+};
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 26000000);
+static APBC_CLK(uart2, UART2, 1, 26000000);
+static APBC_CLK(uart3, UART3, 1, 26000000);
+static APBC_CLK(uart4, UART4, 1, 26000000);
+static APBC_CLK(twsi1, TWSI1, 0, 26000000);
+static APBC_CLK(twsi2, TWSI2, 0, 26000000);
+static APBC_CLK(twsi3, TWSI3, 0, 26000000);
+static APBC_CLK(twsi4, TWSI4, 0, 26000000);
+static APBC_CLK(twsi5, TWSI5, 0, 26000000);
+static APBC_CLK(twsi6, TWSI6, 0, 26000000);
+static APBC_CLK(gpio, GPIO, 0, 26000000);
+
+static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
+
+static struct clk_lookup mmp2_clkregs[] = {
+	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+	INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+	INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
+	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
+	INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
+	INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
+	INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
+	INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
+	INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
+	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+	INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+	INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
+};
+
+void __init mmp2_clk_init(void)
+{
+	clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1cad41b..bd45327 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -9,3 +9,4 @@ extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
 extern void __init pxa168_clk_init(void);
 extern void __init pxa910_clk_init(void);
+extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24..c2ce3d0 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -29,7 +28,6 @@
 #include <mach/mmp2.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE	(APB_VIRT_BASE + 0x1e000)
 
@@ -98,67 +96,6 @@ void __init mmp2_init_irq(void)
 	mmp2_init_icu();
 }
 
-static void sdhc_clk_enable(struct clk *clk)
-{
-	uint32_t clk_rst;
-
-	clk_rst  =  __raw_readl(clk->clk_rst);
-	clk_rst |= clk->enable_val;
-	__raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void sdhc_clk_disable(struct clk *clk)
-{
-	uint32_t clk_rst;
-
-	clk_rst  =  __raw_readl(clk->clk_rst);
-	clk_rst &= ~clk->enable_val;
-	__raw_writel(clk_rst, clk->clk_rst);
-}
-
-struct clkops sdhc_clk_ops = {
-	.enable		= sdhc_clk_enable,
-	.disable	= sdhc_clk_disable,
-};
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
-static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
-static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
-static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
-static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
-
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-
-static struct clk_lookup mmp2_clkregs[] = {
-	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
-	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
-	INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
-	INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
-	INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
-	INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
-	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-	INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
-	INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
-	INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
-	INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
-
 static int __init mmp2_init(void)
 {
 	if (cpu_is_mmp2()) {
@@ -168,25 +105,27 @@ static int __init mmp2_init(void)
 		mfp_init_base(MFPR_VIRT_BASE);
 		mfp_init_addr(mmp2_addr_map);
 		pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
-		clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+		mmp2_clk_init();
 	}
 
 	return 0;
 }
 postcore_initcall(mmp2_init);
 
+#define APBC_TIMERS	APBC_REG(0x024)
+
 static void __init mmp2_timer_init(void)
 {
 	unsigned long clk_rst;
 
-	__raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
+	__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
 	/*
 	 * enable bus/functional clock, enable 6.5MHz (divider 4),
 	 * release reset
 	 */
 	clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
-	__raw_writel(clk_rst, APBC_MMP2_TIMERS);
+	__raw_writel(clk_rst, APBC_TIMERS);
 
 	timer_init(IRQ_MMP2_TIMER1);
 }
-- 
1.7.0.4



From xiechao.mail at gmail.com  Sun Aug 26 22:54:03 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Mon, 27 Aug 2012 10:54:03 +0800
Subject: [PATCH 5/5] arm: mmp: remove unused definition in regs-apbc and
 regs-apmu
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <1346036043-20115-5-git-send-email-xiechao.mail@gmail.com>

From: Chao Xie <chao.xie at marvell.com>

Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
---
 arch/arm/mach-mmp/include/mach/regs-apbc.h |   95 ----------------------------
 arch/arm/mach-mmp/include/mach/regs-apmu.h |   15 -----
 2 files changed, 0 insertions(+), 110 deletions(-)

diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93..ddc812f 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
 
 #include <mach/addr-map.h>
 
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_PXA168_UART1	APBC_REG(0x000)
-#define APBC_PXA168_UART2	APBC_REG(0x004)
-#define APBC_PXA168_GPIO	APBC_REG(0x008)
-#define APBC_PXA168_PWM1	APBC_REG(0x00c)
-#define APBC_PXA168_PWM2	APBC_REG(0x010)
-#define APBC_PXA168_PWM3	APBC_REG(0x014)
-#define APBC_PXA168_PWM4	APBC_REG(0x018)
-#define APBC_PXA168_RTC		APBC_REG(0x028)
-#define APBC_PXA168_TWSI0	APBC_REG(0x02c)
-#define APBC_PXA168_KPC		APBC_REG(0x030)
-#define APBC_PXA168_TIMERS	APBC_REG(0x034)
-#define APBC_PXA168_AIB		APBC_REG(0x03c)
-#define APBC_PXA168_SW_JTAG	APBC_REG(0x040)
-#define APBC_PXA168_ONEWIRE	APBC_REG(0x048)
-#define APBC_PXA168_ASFAR	APBC_REG(0x050)
-#define APBC_PXA168_ASSAR	APBC_REG(0x054)
-#define APBC_PXA168_TWSI1	APBC_REG(0x06c)
-#define APBC_PXA168_UART3	APBC_REG(0x070)
-#define APBC_PXA168_AC97	APBC_REG(0x084)
-#define APBC_PXA168_SSP1	APBC_REG(0x81c)
-#define APBC_PXA168_SSP2	APBC_REG(0x820)
-#define APBC_PXA168_SSP3	APBC_REG(0x84c)
-#define APBC_PXA168_SSP4	APBC_REG(0x858)
-#define APBC_PXA168_SSP5	APBC_REG(0x85c)
-
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_PXA910_UART0	APBC_REG(0x000)
-#define APBC_PXA910_UART1	APBC_REG(0x004)
-#define APBC_PXA910_GPIO	APBC_REG(0x008)
-#define APBC_PXA910_PWM1	APBC_REG(0x00c)
-#define APBC_PXA910_PWM2	APBC_REG(0x010)
-#define APBC_PXA910_PWM3	APBC_REG(0x014)
-#define APBC_PXA910_PWM4	APBC_REG(0x018)
-#define APBC_PXA910_SSP1	APBC_REG(0x01c)
-#define APBC_PXA910_SSP2	APBC_REG(0x020)
-#define APBC_PXA910_IPC		APBC_REG(0x024)
-#define APBC_PXA910_RTC		APBC_REG(0x028)
-#define APBC_PXA910_TWSI0	APBC_REG(0x02c)
-#define APBC_PXA910_KPC		APBC_REG(0x030)
-#define APBC_PXA910_TIMERS	APBC_REG(0x034)
-#define APBC_PXA910_TBROT	APBC_REG(0x038)
-#define APBC_PXA910_AIB		APBC_REG(0x03c)
-#define APBC_PXA910_SW_JTAG	APBC_REG(0x040)
-#define APBC_PXA910_TIMERS1	APBC_REG(0x044)
-#define APBC_PXA910_ONEWIRE	APBC_REG(0x048)
-#define APBC_PXA910_SSP3	APBC_REG(0x04c)
-#define APBC_PXA910_ASFAR	APBC_REG(0x050)
-#define APBC_PXA910_ASSAR	APBC_REG(0x054)
-
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_MMP2_RTC		APBC_REG(0x000)
-#define APBC_MMP2_TWSI1		APBC_REG(0x004)
-#define APBC_MMP2_TWSI2		APBC_REG(0x008)
-#define APBC_MMP2_TWSI3		APBC_REG(0x00c)
-#define APBC_MMP2_TWSI4		APBC_REG(0x010)
-#define APBC_MMP2_ONEWIRE	APBC_REG(0x014)
-#define APBC_MMP2_KPC		APBC_REG(0x018)
-#define APBC_MMP2_TB_ROTARY	APBC_REG(0x01c)
-#define APBC_MMP2_SW_JTAG	APBC_REG(0x020)
-#define APBC_MMP2_TIMERS	APBC_REG(0x024)
-#define APBC_MMP2_UART1		APBC_REG(0x02c)
-#define APBC_MMP2_UART2		APBC_REG(0x030)
-#define APBC_MMP2_UART3		APBC_REG(0x034)
-#define APBC_MMP2_GPIO		APBC_REG(0x038)
-#define APBC_MMP2_PWM0		APBC_REG(0x03c)
-#define APBC_MMP2_PWM1		APBC_REG(0x040)
-#define APBC_MMP2_PWM2		APBC_REG(0x044)
-#define APBC_MMP2_PWM3		APBC_REG(0x048)
-#define APBC_MMP2_SSP0		APBC_REG(0x04c)
-#define APBC_MMP2_SSP1		APBC_REG(0x050)
-#define APBC_MMP2_SSP2		APBC_REG(0x054)
-#define APBC_MMP2_SSP3		APBC_REG(0x058)
-#define APBC_MMP2_SSP4		APBC_REG(0x05c)
-#define APBC_MMP2_SSP5		APBC_REG(0x060)
-#define APBC_MMP2_AIB		APBC_REG(0x064)
-#define APBC_MMP2_ASFAR		APBC_REG(0x068)
-#define APBC_MMP2_ASSAR		APBC_REG(0x06c)
-#define APBC_MMP2_USIM		APBC_REG(0x070)
-#define APBC_MMP2_MPMU		APBC_REG(0x074)
-#define APBC_MMP2_IPC		APBC_REG(0x078)
-#define APBC_MMP2_TWSI5		APBC_REG(0x07c)
-#define APBC_MMP2_TWSI6		APBC_REG(0x080)
-#define APBC_MMP2_TWSI_INTSTS	APBC_REG(0x084)
-#define APBC_MMP2_UART4		APBC_REG(0x088)
-#define APBC_MMP2_RIPC		APBC_REG(0x08c)
-#define APBC_MMP2_THSENS1	APBC_REG(0x090)	/* Thermal Sensor */
-#define APBC_MMP2_THSENS_INTSTS	APBC_REG(0x0a4)
-
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb..93c8d0e 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
 
 #include <mach/addr-map.h>
 
-/* Clock Reset Control */
-#define APMU_IRE	APMU_REG(0x048)
-#define APMU_LCD	APMU_REG(0x04c)
-#define APMU_CCIC	APMU_REG(0x050)
-#define APMU_SDH0	APMU_REG(0x054)
-#define APMU_SDH1	APMU_REG(0x058)
-#define APMU_USB	APMU_REG(0x05c)
-#define APMU_NAND	APMU_REG(0x060)
-#define APMU_DMA	APMU_REG(0x064)
-#define APMU_GEU	APMU_REG(0x068)
-#define APMU_BUS	APMU_REG(0x06c)
-#define APMU_SDH2	APMU_REG(0x0e8)
-#define APMU_SDH3	APMU_REG(0x0ec)
-#define APMU_ETH	APMU_REG(0x0fc)
-
 #define APMU_FNCLK_EN	(1 << 4)
 #define APMU_AXICLK_EN	(1 << 3)
 #define APMU_FNRST_DIS	(1 << 1)
-- 
1.7.0.4



From thomas.abraham at linaro.org  Mon Aug 27 00:20:49 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 27 Aug 2012 09:50:49 +0530
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208252353.59345.heiko@sntech.de>
References: <201208252353.59345.heiko@sntech.de>
Message-ID: <CAJuYYwQBOP7-D0fepDsCr+43ASKQ3CmMBMH-M79QH7r=xS85Eg@mail.gmail.com>

Hi Heiko,

On 26 August 2012 03:23, Heiko St?bner <heiko at sntech.de> wrote:
> Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
> via the device tree. This patch implements dt-support for the
> s3c24xx arches.
>
> The controllers contain only 3 cells, as the underlying gpio controller
> does not support controlling the drive strength on a gpio level.
>
> Tested with the gpio-keys driver on a s3c2416 based machine.
>
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> ---
>  .../devicetree/bindings/gpio/gpio-samsung.txt      |   38 ++++++++++++
>  drivers/gpio/gpio-samsung.c                        |   63 ++++++++++++++++++++
>  2 files changed, 101 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> index 5375625..ce6a7d4 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> @@ -39,3 +39,41 @@ Example:
>                 #gpio-cells = <4>;
>                 gpio-controller;
>         };
> +
> +
> +Samsung S3C24XX GPIO Controller
> +
> +Required properties:
> +- compatible: Compatible property value should be "samsung,s3c24xx-gpio".

This is debatable, but I would choose to be specific here and use
"samsing,s3c2416-gpio". For instance, SoC's in s3c24xx family have
differing value for pull none/down/up.

> +
> +- reg: Physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
> +  should be the following with values derived from the SoC user manual.
> +     <[phandle of the gpio controller node]
> +      [pin number within the gpio controller]
> +      [mux function]
> +      [flags and pull up/down]
> +
> +  Values for gpio specifier:
> +  - Pin number: depending on the controller a number from 0 up to 15.
> +  - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
> +                            1 - Pull Down Enabled.
> +                            3 - Pull Up Enabled.

As per s3c2416 user manual, 2 is used for Pull Up and 3 is listed as
reserved value. Any particular reason to use 3 here for pull up and
not 2 as per the user manual?

> +          Bit 16 (0x00010000) - Input is active low.
> +
> +- gpio-controller: Specifies that the node is a gpio controller.
> +- #address-cells: should be 1.
> +- #size-cells: should be 1.

It would be informative to add information about the 'mux function'
cell here as well. Specifically, on how to handle the banks that have
an extended GPxSEL register that allow additional pin function
selection.

> +
> +Example:
> +
> +       gpa: gpio-controller at 56000000 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "samsung,s3c24xx-gpio";
> +               reg = <0x56000000 0x10>;
> +               #gpio-cells = <3>;
> +               gpio-controller;
> +       };
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index a150d2e..80a2817 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
>                 s3c_gpiolib_track(chip);
>  }
>
> +#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
> +static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
> +                       const struct of_phandle_args *gpiospec, u32 *flags)
> +{
> +       unsigned int pin;
> +
> +       if (WARN_ON(gc->of_gpio_n_cells < 3))
> +               return -EINVAL;
> +
> +       if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
> +               return -EINVAL;
> +
> +       if (gpiospec->args[0] > gc->ngpio)
> +               return -EINVAL;
> +
> +       pin = gc->base + gpiospec->args[0];
> +
> +       if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
> +               pr_warn("gpio_xlate: failed to set pin function\n");
> +       if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
> +               pr_warn("gpio_xlate: failed to set pin pull up/down\n");
> +
> +       if (flags)
> +               *flags = gpiospec->args[2] >> 16;
> +
> +       return gpiospec->args[0];
> +}
> +
> +static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
> +       { .compatible = "samsung,s3c24xx-gpio", },
> +       {}
> +};
> +
> +static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> +                                                u64 base, u64 offset)
> +{
> +       struct gpio_chip *gc =  &chip->chip;
> +       u64 address;
> +
> +       if (!of_have_populated_dt())
> +               return;
> +
> +       address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
> +       gc->of_node = of_find_matching_node_by_address(NULL,
> +                       s3c24xx_gpio_dt_match, address);
> +       if (!gc->of_node) {
> +               pr_info("gpio: device tree node not found for gpio controller"
> +                       " with base address %08llx\n", address);
> +               return;
> +       }
> +       gc->of_gpio_n_cells = 3;
> +       gc->of_xlate = s3c24xx_gpio_xlate;
> +}
> +#elif defined(CONFIG_PLAT_S3C24XX)
> +static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> +                                                u64 base, u64 offset)
> +{
> +       return;
> +}
> +#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
> +
>  static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
>                                              int nr_chips, void __iomem *base)
>  {
> @@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
>                         gc->direction_output = samsung_gpiolib_2bit_output;
>
>                 samsung_gpiolib_add(chip);
> +
> +               s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
>         }
>  }
>
> --
> 1.7.2.3
>

Overall, this is patch looks fine.

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From swarren at wwwdotorg.org  Mon Aug 27 00:33:56 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Sun, 26 Aug 2012 21:33:56 -0700
Subject: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core
In-Reply-To: <5038F50E.7030807@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1345623750-10645-2-git-send-email-sebastian.hesselbarth@gmail.com>
 <5035445B.6000500@wwwdotorg.org>
 <CABJ1b_Tdr80DGqb-FRzwDbF3m7g6fBguk5GtRAfRUYx5Sqy_cA@mail.gmail.com>
 <50366E44.4030606@wwwdotorg.org> <50369305.6050304@gmail.com>
 <50369FEE.8000003@wwwdotorg.org> <5036B639.20608@gmail.com>
 <5036F651.4020700@wwwdotorg.org> <5038F50E.7030807@gmail.com>
Message-ID: <503AF8B4.1070206@wwwdotorg.org>

On 08/25/2012 08:53 AM, Sebastian Hesselbarth wrote:
> On 08/24/2012 05:34 AM, Stephen Warren wrote:
>> On 08/23/2012 05:01 PM, Sebastian Hesselbarth wrote:
>>> So possible, valid combinations for uart1 would be:
>>> (a) mpp_uart1;
>>> (b) mpp_uart1, mpp2, mpp3;
>>> (c) mpp_uart1, mpp21, mpp22;
>>> (d) mpp_uart1, mpp2, mpp22;
>>> (e) mpp_uart1, mpp21, mpp3;
>>>  [...]
>> In the example above, there is a single function named "uart1". If this
>> was all the HW supported, I'd expect the driver's
>> pinmux_ops.get_functions_count() to return 1,
>> pinmux_ops.get_function_name(0) to return "uart1", and
>> pinmux_ops.get_function_name(n>0) to return an error.
>>
>> In practice, I assume there are many other options that can be muxed
>> onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
>>
>> I don't expect any scanning, no. I'd expect that tables provided by the
>> SoC-specific drivers to be:
>>
>> * A table of pins
>> * A table of groups
>> * A table of functions
>>
>> No scanning involved.
> 
> Stephen,
> 
> now I do understand but in the current driver we pass pingroups associated
> with the available functions, i.e. "mpp2" with "uart1", "uart2",
> "sdio0", aso.
> IMHO for the above three functions it would be better to have functions
> associated
> with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2",
> "mpp3", aso.

The pinctrl subsystem does expect a list of functions, and for each
function, a list of the groups where it can be selected. I admit that
when I think about this, it's slightly backward, since HW typically has
a list of pins/groups, and for each, a certain set of functions can be
selected. Oh well...


From bilhuang at nvidia.com  Mon Aug 27 01:43:07 2012
From: bilhuang at nvidia.com (Bill Huang)
Date: Mon, 27 Aug 2012 13:43:07 +0800
Subject: Shutdown problem in SMP system happened on Tegra20
In-Reply-To: <20120825071755.GG18957@n2100.arm.linux.org.uk>
References: <A7051F87A141B744BCAF487D48E5B3BDF5BA982848@HKMAIL02.nvidia.com>
 <20120824182133.GB18957@n2100.arm.linux.org.uk>
 <A7051F87A141B744BCAF487D48E5B3BDF5BA98284A@HKMAIL02.nvidia.com>
 <20120825071755.GG18957@n2100.arm.linux.org.uk>
Message-ID: <A7051F87A141B744BCAF487D48E5B3BDF5BA98284F@HKMAIL02.nvidia.com>

> On Sat, Aug 25, 2012 at 08:00:56AM +0800, Bill Huang wrote:
> > nvpublic
> > > So what you're asking for is a feature to do what
> > > CONFIG_PM_SLEEP_SMP does, but without CONFIG_PM_SLEEP_SMP enabled?
> >
> > Yeah pretty much, I'm actually asking should we take care of this
> > since maybe not all platforms will have this config enabled?
> > >
> > > Why not just ensure that CONFIG_PM_SLEEP_SMP is enabled if your
> > > platform requires that the lowest CPU number be the CPU dealing with reboot?
> >
> > Someday we will have it enabled, but before that we'll hit the issue,
> > so you don't think this should be taken care of? Thanks.
> 
> Well, just enable CONFIG_PM_SLEEP_SMP then - it'll be far better than trying to implement something in
> the ARM code, especially as sysrq can be used for poweroff/reboot etc (which will run from atomic
> contexts where you can't switch to another CPU.)
> 
> What you're asking for will make these callbacks fragile for other platforms.

OK, thanks.


From jangra.pankaj9 at gmail.com  Mon Aug 27 01:57:33 2012
From: jangra.pankaj9 at gmail.com (Pankaj Jangra)
Date: Mon, 27 Aug 2012 11:27:33 +0530
Subject: [PATCH 5/13] arch/arm: use clk_prepare_enable and
 clk_disable_unprepare
In-Reply-To: <1345996865-32082-6-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345996865-32082-6-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <CADTbHxqm9Nktcn++-+GFqX8n_CwNzgp79XRJGf21-eDgtm8jsg@mail.gmail.com>

Hi,

On Sun, Aug 26, 2012 at 9:30 PM, Julia Lawall <Julia.Lawall at lip6.fr> wrote:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
>
> Clk_prepare_enable and clk_disable_unprepare combine clk_prepare and
> clk_enable, and clk_disable and clk_unprepare.  They make the code more
> concise, and ensure that clk_unprepare is called when clk_enable fails.
>
> A simplified version of the semantic patch that introduces calls to these
> functions is as follows: (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @@
> expression e;
> @@
>
> - clk_prepare(e);
> - clk_enable(e);
> + clk_prepare_enable(e);
>
> @@
> expression e;
> @@
>
> - clk_disable(e);
> - clk_unprepare(e);
> + clk_disable_unprepare(e);
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>
>
> ---
>  arch/arm/common/sa1111.c   |    3 +--
>  arch/arm/common/timer-sp.c |   16 ++++------------
>  arch/arm/kernel/smp_twd.c  |   13 +++----------
>  3 files changed, 8 insertions(+), 24 deletions(-)
>

Reviewed-by: Pankaj Jangra <jangra.pankaj9 at gmail.com>

Regards,
Pankaj Jangra


From anilkumar at ti.com  Mon Aug 27 02:00:44 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Mon, 27 Aug 2012 11:30:44 +0530
Subject: [PATCH] ARM: OMAP2+: select PINCTRL in Kconfig
Message-ID: <1346047244-26909-1-git-send-email-anilkumar@ti.com>

Select PINCTRL in Kconfig under Typical OMAP configuration, this
is required to add pinctrl driver to omap2+ family of devices.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/mach-omap2/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd2db02..a164568 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,6 +18,7 @@ config ARCH_OMAP2PLUS_TYPICAL
 	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
 	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
 	select HIGHMEM
+	select PINCTRL
 	help
 	  Compile a kernel suitable for booting most boards
 
-- 
1.7.9.5



From horms at verge.net.au  Mon Aug 27 02:40:09 2012
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 Aug 2012 15:40:09 +0900
Subject: [PATCH 1/2] ARM: mach-shmobile: armadillo800eva: Fix GPIO buttons
 descriptions
In-Reply-To: <1346049610-2266-1-git-send-email-horms@verge.net.au>
References: <1346049610-2266-1-git-send-email-horms@verge.net.au>
Message-ID: <1346049610-2266-2-git-send-email-horms@verge.net.au>

From: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

The GPIO buttons are named SW3, SW4, SW5 and SW6 on the board
silkscreen. Update the buttons descriptions accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index cf10f92..a002504 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -523,10 +523,10 @@ static struct platform_device hdmi_lcdc_device = {
 #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
 
 static struct gpio_keys_button gpio_buttons[] = {
-	GPIO_KEY(KEY_POWER,	GPIO_PORT99,	"SW1"),
-	GPIO_KEY(KEY_BACK,	GPIO_PORT100,	"SW2"),
-	GPIO_KEY(KEY_MENU,	GPIO_PORT97,	"SW3"),
-	GPIO_KEY(KEY_HOME,	GPIO_PORT98,	"SW4"),
+	GPIO_KEY(KEY_POWER,	GPIO_PORT99,	"SW3"),
+	GPIO_KEY(KEY_BACK,	GPIO_PORT100,	"SW4"),
+	GPIO_KEY(KEY_MENU,	GPIO_PORT97,	"SW5"),
+	GPIO_KEY(KEY_HOME,	GPIO_PORT98,	"SW6"),
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Mon Aug 27 02:40:08 2012
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 Aug 2012 15:40:08 +0900
Subject: No subject
Message-ID: <1346049610-2266-1-git-send-email-horms@verge.net.au>

Hi Arnd, Hi Olaf,

please consider the following enhancements for the Armadillo800EVA board
from Laurent Pinchart for inclusion in 3.7.

I am currently in the processes of taking over maintenance
of shmoble from Rafael Wysocki and this my the first pull request
in that role.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git armadillo800eva

for you to fetch changes up to 5c1d2d16772e2d7d4e2e8da99a92d6f50b9102f0:

  ARM: mach-shmobile: armadillo800eva: Enable power button as wakeup source (2012-08-25 15:44:53 +0900)

----------------------------------------------------------------
Laurent Pinchart (2):
      ARM: mach-shmobile: armadillo800eva: Fix GPIO buttons descriptions
      ARM: mach-shmobile: armadillo800eva: Enable power button as wakeup source

 arch/arm/mach-shmobile/board-armadillo800eva.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)


From horms at verge.net.au  Mon Aug 27 02:40:10 2012
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 Aug 2012 15:40:10 +0900
Subject: [PATCH 2/2] ARM: mach-shmobile: armadillo800eva: Enable power button
 as wakeup source
In-Reply-To: <1346049610-2266-1-git-send-email-horms@verge.net.au>
References: <1346049610-2266-1-git-send-email-horms@verge.net.au>
Message-ID: <1346049610-2266-3-git-send-email-horms@verge.net.au>

From: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index a002504..65cb793 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -520,10 +520,11 @@ static struct platform_device hdmi_lcdc_device = {
 };
 
 /* GPIO KEY */
-#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+#define GPIO_KEY(c, g, d, ...) \
+	{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
 
 static struct gpio_keys_button gpio_buttons[] = {
-	GPIO_KEY(KEY_POWER,	GPIO_PORT99,	"SW3"),
+	GPIO_KEY(KEY_POWER,	GPIO_PORT99,	"SW3", .wakeup = 1),
 	GPIO_KEY(KEY_BACK,	GPIO_PORT100,	"SW4"),
 	GPIO_KEY(KEY_MENU,	GPIO_PORT97,	"SW5"),
 	GPIO_KEY(KEY_HOME,	GPIO_PORT98,	"SW6"),
-- 
1.7.10.2.484.gcd07cc5



From hvaibhav at ti.com  Mon Aug 27 02:52:53 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 27 Aug 2012 12:22:53 +0530
Subject: [PATCH] ARM: OMAP2+: am33xx: Fix the timer fck clock naming
 convention
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA6E8B1@DBDE01.ent.ti.com>
References: <1342462158-15998-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1207161754230.28834@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA6E8B1@DBDE01.ent.ti.com>
Message-ID: <503B1945.5010308@ti.com>



On 7/17/2012 10:14 AM, Hiremath, Vaibhav wrote:
> On Tue, Jul 17, 2012 at 05:24:39, Paul Walmsley wrote:
>> On Mon, 16 Jul 2012, Vaibhav Hiremath wrote:
>>
>>> With commit ae6df418a21f3a361c5f9b878e32a8aba4e17692
>>> Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage)
>>> The Timer functional clock naming convention has changed from
>>> gptX_fck => timerXfck, and so as the timer init function
>>> in mach-omap2/timer.c.
>>> OMAP4 clocktree also has changed accordingly.
>>>
>>> AM33xx Clock Tree has been merged during rc3-4 timeframe,
>>> before above commit got merged, so similar change is required
>>> for AM33xx as well (Change the gptX_fck => timerX_fck).
>>>
>>> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
>>
>> Thanks, this looks like 3.6-rc material, right?
>>
>>
> 
> Yes, that's correct.
> 

Tony/Paul,

Ping !!!

Thanks,
Vaibhav

> Thanks,
> Vaibhav
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From afzal at ti.com  Mon Aug 27 03:35:43 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 07:35:43 +0000
Subject: [PATCH v3 0/6] omap-am33xx rtc dt support
In-Reply-To: <50256797.3020505@ti.com>
References: <cover.1343383616.git.afzal@ti.com> <50256797.3020505@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA4EB@DBDE01.ent.ti.com>

Hi Alessandro,

On Sat, Aug 11, 2012 at 01:27:11, Nori, Sekhar wrote:
> On 7/27/2012 5:53 PM, Afzal Mohammed wrote:

> > This series makes rtc-omap driver DT capable, adds AM33xx
> > RTC DT support along with a few enchancments to the driver.
> > 
> > rtc-omap driver is made intelligent enough to handle kicker
> > mechanism. This helps in removing kicker mechanism support
> > done for DaVinci at platform level.
> > 
> > This has been tested on Beaglebone (AM33xx platform) and on
> > DaVinci DA850 EVM.
> > 
> > This series is based over linux-omap master and can be
> > directly applied over linux-next, except for
> > [PATCH 6/6] arm/dts: am33xx rtc node.
> > 
> > PATCH 6/6 should go through linux-omap tree and needs
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg71644.html
> > (arm/dts: am33xx wdt node) to get applied cleanly
> 
> I tested patches 1-5 on AM18x EVM using rtcwake and hwclock commands.
> Also tested on DT enabled AM18x EVM using hwclock.
> 
> For patched 1-5:
> 
> Acked-by: Sekhar Nori <nsekhar at ti.com>
> 
> Alessandro,
> 
> I assume you would want me to queue 2/6 through DaVinci tree. That patch
> depends on 1/6 being accepted and merged by you. Let me know how you
> want to move forward here.

Can you please help 1-5 patches in this series to get into mainline.
1-5 of this series is a prerequisite for adding RTC support for AM335X
SoC's, which is present in beaglebone, AM335X EVM.

Also this series does cleanup on DaVinci platform by moving kicker handling
mechanism to driver. And we have Ack from DaVinci maintainer on 1-5 of this
series.

Patch 6/6 adds AM335X RTC DT support, not sure whether you can take 6/6
or Tony should be taking it.

The series applies cleanly over linux-next (now including 6/6)

Regards
Afzal

From dirk.behme at de.bosch.com  Mon Aug 27 03:36:50 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Mon, 27 Aug 2012 09:36:50 +0200
Subject: [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP
Message-ID: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>

The following two patches are a port from Freescale's patch

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/drivers/tty/serial/imx.c?h=imx_3.0.15_android&id=80e525d66d1818722db18e21dc7f1dc41f314156

Using a 3.6-rc3 kernel on a i.MX6 SabreLite board and increasing the
verbosity of the kernel's serial console output with some debug printk
like [1] results in two issues:

1. After some time the kernel output hangs [2]. The debugger tells us that
it hangs in drivers/tty/serial/imx.c at

...
/*
 *	Finally, wait for transmitter to become empty
 *	and restore UCR1/2/3
 */
while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
...

with permanently reading 0x1000 from USR2 while it waits for bit USR2_TXDC
(0x8).

2. Even after applying the first patch, there happens to be some garbage in the
   output [3].

Both issues are gone applying these two patches.

Note: If these patches are fine, they should go to stable, too.

Best regards

Dirk

[1]

Index: a/mm/mmap.c
===================================================================
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -1290,6 +1290,9 @@ munmap_back:
 	vma->vm_pgoff = pgoff;
 	INIT_LIST_HEAD(&vma->anon_vma_chain);
 
+	printk(" => mmap_region: start: 0x%08X end: 0x%08X len: %d\n",
+		(unsigned int)vma->vm_start, (unsigned int)vma->vm_end, (int)len);
+
 	error = -EINVAL;	/* when rejecting VM_GROWSDOWN|VM_GROWSUP */
 
 	if (file) {

[2]
...
=> mmap_region: start: 0x76DBC000 end: 0x76DBE000 len: 8192
=> mmap_region: start: 0x76DBE000 end: 0x76DC0000 len: 8192
=> mmap_region: start: 0x76D5C000 end: 0x76DA0000 ??
<hang, no output any more>

[3]
...
=> mmap_region: start: 0x0011C000 end: 0x0011D000 len: 4096
=> mmap_region: start: 0x00008000 end: 0x000B500f??#.??????R????r????j???????}???????????? start: 0x000BD000 end: 0x000BE000 len: 4096
=> mmap_region: start: 0x000BD000 end: 0x000BE000 len: 4096
...


From dirk.behme at de.bosch.com  Mon Aug 27 03:36:51 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Mon, 27 Aug 2012 09:36:51 +0200
Subject: [PATCH 1/2] tty: serial: imx: console write routing is unsafe on SMP
In-Reply-To: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <1346053012-25686-2-git-send-email-dirk.behme@de.bosch.com>

From: Xinyu Chen <xinyu.chen at freescale.com>

The console feature's write routing is unsafe on SMP with
the startup/shutdown call.

There could be several consumers of the console
* the kernel printk
* the init process using /dev/kmsg to call printk to show log
* shell, which open /dev/console and write with sys_write()

The shell goes into the normal uart open/write routing,
but the other two go into the console operations.
The open routing calls imx serial startup, which will write USR1/2
register without any lock and critical with imx_console_write call.

Add a spin_lock for startup/shutdown/console_write routing.

This patch is a port from Freescale's Android kernel.

Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
CC: Shawn Guo <shawn.guo at linaro.org>
CC: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/tty/serial/imx.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index d5c689d..908178f 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -754,6 +754,7 @@ static int imx_startup(struct uart_port *port)
 		}
 	}
 
+	spin_lock_irqsave(&sport->port.lock, flags);
 	/*
 	 * Finally, clear and enable interrupts
 	 */
@@ -807,7 +808,6 @@ static int imx_startup(struct uart_port *port)
 	/*
 	 * Enable modem status interrupts
 	 */
-	spin_lock_irqsave(&sport->port.lock,flags);
 	imx_enable_ms(&sport->port);
 	spin_unlock_irqrestore(&sport->port.lock,flags);
 
@@ -837,10 +837,13 @@ static void imx_shutdown(struct uart_port *port)
 {
 	struct imx_port *sport = (struct imx_port *)port;
 	unsigned long temp;
+	unsigned long flags;
 
+	spin_lock_irqsave(&sport->port.lock, flags);
 	temp = readl(sport->port.membase + UCR2);
 	temp &= ~(UCR2_TXEN);
 	writel(temp, sport->port.membase + UCR2);
+	spin_unlock_irqrestore(&sport->port.lock, flags);
 
 	if (USE_IRDA(sport)) {
 		struct imxuart_platform_data *pdata;
@@ -869,12 +872,14 @@ static void imx_shutdown(struct uart_port *port)
 	 * Disable all interrupts, port and break condition.
 	 */
 
+	spin_lock_irqsave(&sport->port.lock, flags);
 	temp = readl(sport->port.membase + UCR1);
 	temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
 	if (USE_IRDA(sport))
 		temp &= ~(UCR1_IREN);
 
 	writel(temp, sport->port.membase + UCR1);
+	spin_unlock_irqrestore(&sport->port.lock, flags);
 }
 
 static void
@@ -1217,6 +1222,9 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
 	struct imx_port *sport = imx_ports[co->index];
 	struct imx_port_ucrs old_ucr;
 	unsigned int ucr1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sport->port.lock, flags);
 
 	/*
 	 *	First, save UCR1/2/3 and then disable interrupts
@@ -1242,6 +1250,8 @@ imx_console_write(struct console *co, const char *s, unsigned int count)
 	while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
 
 	imx_port_ucrs_restore(&sport->port, &old_ucr);
+
+	spin_unlock_irqrestore(&sport->port.lock, flags);
 }
 
 /*
-- 
1.7.0.4



From dirk.behme at de.bosch.com  Mon Aug 27 03:36:52 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Mon, 27 Aug 2012 09:36:52 +0200
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled console
In-Reply-To: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>

From: Xinyu Chen <xinyu.chen at freescale.com>

Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
as this will cause clock reinit, and output garbage.

This patch is a port from Freescale's Android kernel.

Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
CC: Shawn Guo <shawn.guo at linaro.org>
CC: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/tty/serial/imx.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 908178f..31ce414 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
 	int retval;
 	unsigned long flags, temp;
 
+#ifndef CONFIG_SERIAL_CORE_CONSOLE
 	imx_setup_ufcr(sport, 0);
+#endif
 
 	/* disable the DREN bit (Data Ready interrupt enable) before
 	 * requesting IRQs
-- 
1.7.0.4



From b29396 at freescale.com  Mon Aug 27 03:24:38 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:38 +0800
Subject: [PATCH v2 0/7] add syscon driver based on regmap for general
 registers access
Message-ID: <1346052285-4344-1-git-send-email-b29396@freescale.com>

This patch series mainly adds an syscon driver which is used to access
general system controller registers like FSL IOMUXC GPR and ANATOP,
after that, we convert all the exist private access general registers code to use
standard API from regmap to access registers.
Finally we remove the old mfd anatop driver which is only for anatop register
access.

The patch series is based on linus's tree 3.6-rc3 since commit 9160338.

Dong Aisheng (7):
  mfd: add syscon driver based on regmap
  ARM: imx6q: add iomuxc gpr support into syscon
  ARM: imx6q: add anatop support into syscon
  regulator: anatop-regulator: convert to use syscon to access anatop
    register
  ARM: imx6q: convert to use syscon to access anatop registers
  ARM: dts: imx6q: add simple-bus compatible string for anatop
  mfd: anatop-mfd: remove anatop driver

 .../devicetree/bindings/mfd/imx-syscon.txt         |   11 +
 arch/arm/boot/dts/imx6q.dtsi                       |   15 +-
 arch/arm/mach-imx/Kconfig                          |    2 +-
 arch/arm/mach-imx/mach-imx6q.c                     |   43 ++--
 drivers/mfd/Kconfig                                |   13 +-
 drivers/mfd/Makefile                               |    2 +-
 drivers/mfd/anatop-mfd.c                           |  124 --------
 drivers/mfd/syscon.c                               |  169 +++++++++++
 drivers/regulator/Kconfig                          |    2 +-
 drivers/regulator/anatop-regulator.c               |   25 +-
 include/linux/fsl/imx6q-iomuxc-gpr.h               |  319 ++++++++++++++++++++
 include/linux/mfd/anatop.h                         |   40 ---
 include/linux/mfd/syscon.h                         |   22 ++
 13 files changed, 576 insertions(+), 211 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/imx-syscon.txt
 delete mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 drivers/mfd/syscon.c
 create mode 100644 include/linux/fsl/imx6q-iomuxc-gpr.h
 delete mode 100644 include/linux/mfd/anatop.h
 create mode 100644 include/linux/mfd/syscon.h




From b29396 at freescale.com  Mon Aug 27 03:24:39 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:39 +0800
Subject: [PATCH v2 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-2-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Add regmap based syscon driver.
This is usually used for access misc bits in registers which does not belong
to a specific module, for example, IMX IOMUXC GPR and ANATOP.
With this driver, client can use generic regmap API to access registers
which are registered into syscon.

Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog:
v1->v2:
 * provide a way of retrieving the regmap, suggested by Mark Brown.
 * delete imx-syscon io accessors and using generic regmap API for client drivers.
 * change to a more generic name for other SoCs to use.
---
 .../devicetree/bindings/mfd/imx-syscon.txt         |   11 ++
 drivers/mfd/Kconfig                                |    7 +
 drivers/mfd/Makefile                               |    1 +
 drivers/mfd/syscon.c                               |  169 ++++++++++++++++++++
 include/linux/mfd/syscon.h                         |   22 +++
 5 files changed, 210 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
new file mode 100644
index 0000000..c1a13b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
@@ -0,0 +1,11 @@
+* System Controller Registers R/W driver
+
+Required properties:
+- compatible: Should contain "syscon".
+- reg: the register range can be access from syscon
+
+Examples:
+gpr: iomuxc-gpr at 020e0000 {
+	compatible = "fsl,imx6q-iomuxc", "syscon";
+	reg = <0x020e0000 0x38>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b1a1462..4a6c48e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -993,6 +993,13 @@ config MFD_ANATOP
 	  MFD controller. This controller embeds regulator and
 	  thermal devices for Freescale i.MX platforms.
 
+config MFD_SYSCON
+        bool "System Controller Register R/W Based on Regmap"
+        select REGMAP_MMIO
+        help
+          Select this option to enable accessing system control registers
+	  via regmap.
+
 config MFD_PALMAS
 	bool "Support for the TI Palmas series chips"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..8384bc9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
+obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
new file mode 100644
index 0000000..da2464f
--- /dev/null
+++ b/drivers/mfd/syscon.c
@@ -0,0 +1,169 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct platform_driver syscon_driver;
+
+struct syscon {
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *regmap;
+};
+
+static int syscon_match(struct device *dev, void *data)
+{
+	struct syscon *syscon = dev_get_drvdata(dev);
+	struct device_node *dn = data;
+
+	return (syscon->dev->of_node == dn) ? 1 : 0;
+}
+
+static struct regmap *syscon_node_to_regmap(struct device_node *np)
+{
+	struct syscon *syscon;
+	struct device *dev;
+
+	dev = driver_find_device(&syscon_driver.driver, NULL, np,
+				 syscon_match);
+	of_node_put(np);
+
+	if (!dev)
+		return ERR_PTR(-EPROBE_DEFER);
+
+	syscon = dev_get_drvdata(dev);
+
+	return syscon->regmap;
+}
+
+struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_find_compatible_node(NULL, NULL, s);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+
+struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
+					const char *property)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_parse_phandle(np, property, 0);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+
+static const struct of_device_id of_syscon_match[] = {
+	{ .compatible = "syscon", },
+	{ },
+};
+
+static struct regmap_config syscon_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int __devinit syscon_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct syscon *syscon;
+	struct resource res;
+	int ret;
+
+	if (!np)
+		return -ENOENT;
+
+	syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
+			    GFP_KERNEL);
+	if (!syscon)
+		return -ENOMEM;
+
+	syscon->base = of_iomap(np, 0);
+	if (!syscon->base)
+		return -EADDRNOTAVAIL;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	syscon_regmap_config.max_register = res.end - res.start - 3;
+	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
+					&syscon_regmap_config);
+	if (IS_ERR(syscon->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(syscon->regmap);
+	}
+
+	regcache_cache_only(syscon->regmap, false);
+
+	syscon->dev = &pdev->dev;
+	platform_set_drvdata(pdev, syscon);
+
+	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
+		res.start, res.end);
+
+	return 0;
+}
+
+static int __devexit syscon_remove(struct platform_device *pdev)
+{
+	struct syscon *syscon;
+
+	syscon = platform_get_drvdata(pdev);
+	iounmap(syscon->base);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver syscon_driver = {
+	.driver = {
+		.name = "syscon",
+		.owner = THIS_MODULE,
+		.of_match_table = of_syscon_match,
+	},
+	.probe		= syscon_probe,
+	.remove		= syscon_remove,
+};
+
+static int __init syscon_init(void)
+{
+	return platform_driver_register(&syscon_driver);
+}
+postcore_initcall(syscon_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&syscon_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("System Control driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
new file mode 100644
index 0000000..990d7cf
--- /dev/null
+++ b/include/linux/mfd/syscon.h
@@ -0,0 +1,22 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_MFD_SYSCON_H__
+#define __LINUX_MFD_SYSCON_H__
+
+extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
+extern struct regmap *syscon_regmap_lookup_by_phandle(
+					struct device_node *np,
+					const char *property);
+#endif /* __LINUX_MFD_SYSCON_H__ */
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:41 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:41 +0800
Subject: [PATCH v2 3/7] ARM: imx6q: add anatop support into syscon
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-4-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

There're a few anatop registers need to be accessed by different modules.
Add anatop registers into syscon support for easy access.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bea21bc..db3fa15 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -378,8 +378,8 @@
 				interrupts = <0 87 0x04 0 88 0x04>;
 			};
 
-			anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop";
+			anatop: anatop at 020c8000 {
+				compatible = "fsl,imx6q-anatop", "syscon";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:40 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:40 +0800
Subject: [PATCH v2 2/7] ARM: imx6q: add iomuxc gpr support into syscon
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-3-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Include headfile for easy using.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi         |    5 +
 include/linux/fsl/imx6q-iomuxc-gpr.h |  319 ++++++++++++++++++++++++++++++++++
 2 files changed, 324 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..bea21bc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -507,6 +507,11 @@
 				interrupts = <0 89 0x04 0 90 0x04>;
 			};
 
+			gpr: iomuxc-gpr at 020e0000 {
+				compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+				reg = <0x020e0000 0x38>;
+			};
+
 			iomuxc at 020e0000 {
 				compatible = "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
diff --git a/include/linux/fsl/imx6q-iomuxc-gpr.h b/include/linux/fsl/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..2c44573
--- /dev/null
+++ b/include/linux/fsl/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0	0x00
+#define IOMUXC_GPR1	0x04
+#define IOMUXC_GPR2	0x08
+#define IOMUXC_GPR3	0x0c
+#define IOMUXC_GPR4	0x10
+#define IOMUXC_GPR5	0x14
+#define IOMUXC_GPR6	0x18
+#define IOMUXC_GPR7	0x1c
+#define IOMUXC_GPR8	0x20
+#define IOMUXC_GPR9	0x24
+#define IOMUXC_GPR10	0x28
+#define IOMUXC_GPR11	0x2c
+#define IOMUXC_GPR12	0x30
+#define IOMUXC_GPR13	0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7	(0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED	(0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR	(0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED	(0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7	(0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED	(0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2	(0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED	(0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2	(0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED	(0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1	(0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED	(0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1	(0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1	(0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2	(0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK		BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX	BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK		BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2	BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK		BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1			BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23			BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IMX6Q_GPR1_DPI_OFF			BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY			0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE			BIT(15)
+#define IMX6Q_GPR1_PCIE_INT			BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK		BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER	0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1	BIT(13)
+#define IMX6Q_GPR1_GINT				BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3			BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2			BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1			BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0			BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK	(0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5		(0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3		(0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4		(0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6		(0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK		(0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0		(0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1		(0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2		(0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3		(0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4		(0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5		(0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6		(0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7		(0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK		BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR	0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR	BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK		BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L	BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK		BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L	BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK		BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA	BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK		BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT		BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK		BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA	BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK		BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT		BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN		BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK		(0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE		(0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0	(0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1	(0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK		(0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE		(0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0	(0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK			(0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D		(0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D		(0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG		(0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL		BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL		BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL		BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL		BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK		(0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK		(0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN		BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN		BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN		BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN		BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK		BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK		BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK		BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK		(0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0	(0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1	(0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0	(0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1	(0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK		(0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0	(0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1	(0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0	(0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1	(0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0	(0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1	(0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0	(0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1	(0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL		BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL		BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL		BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL		BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL		BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL		BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL		BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL		BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK		BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK		BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK		BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK		BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK		(0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF		0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL		BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL		BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL		BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK	BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL		BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL		BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN			BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN		BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP		BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR		(0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN		BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK		(0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK		(0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN			BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN			BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK		BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY		0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE		BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK		(0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK		BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1	(0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK		(0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0	(0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1	(0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0	(0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ		BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ		BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB		(0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB		(0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB		(0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB		(0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB		(0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB		(0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB		(0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK		(0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK		(0x7 << 16)
+#define IMX6Q_GPR13_SATA_SPEED_MASK		BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G		0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G		BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5			BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK		(0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16		(0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16		(0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16		(0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16		(0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16		(0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16		(0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK		(0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF		0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF		0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK		(0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST		(0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
+
+#endif /* !__LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:42 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:42 +0800
Subject: [PATCH v2 4/7] regulator: anatop-regulator: convert to use syscon to
 access anatop register
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-5-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop register.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v1-v2:
 * update to use generic regmap api
---
 arch/arm/boot/dts/imx6q.dtsi         |    6 ++++++
 drivers/regulator/Kconfig            |    2 +-
 drivers/regulator/anatop-regulator.c |   25 +++++++++++++++----------
 3 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index db3fa15..da2bb71 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -395,6 +395,7 @@
 					anatop-min-bit-val = <4>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1375000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-3p0 at 120 {
@@ -409,6 +410,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2625000>;
 					anatop-max-voltage = <3400000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-2p5 at 130 {
@@ -423,6 +425,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2000000>;
 					anatop-max-voltage = <2750000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddcore at 140 {
@@ -437,6 +440,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddpu at 140 {
@@ -451,6 +455,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 
 				regulator-vddsoc at 140 {
@@ -465,6 +470,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					fsl,anatop = <&anatop>;
 				};
 			};
 
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 4e932cc..2ae1d97 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -112,7 +112,7 @@ config REGULATOR_DA9052
 
 config REGULATOR_ANATOP
 	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
-	depends on MFD_ANATOP
+	depends on MFD_SYSCON
 	help
 	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
 	  regulators. It is recommended that this option be
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index ce0fe72..71586a7 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -21,19 +21,20 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 #include <linux/module.h>
+#include <linux/mfd/syscon.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
+#include <linux/regmap.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/of_regulator.h>
 
 struct anatop_regulator {
 	const char *name;
 	u32 control_reg;
-	struct anatop *mfd;
+	struct regmap *anatop;
 	int vol_bit_shift;
 	int vol_bit_width;
 	int min_bit_val;
@@ -43,7 +44,7 @@ struct anatop_regulator {
 	struct regulator_init_data *initdata;
 };
 
-static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
+static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -56,12 +57,13 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val <<= anatop_reg->vol_bit_shift;
-	anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
+	regmap_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
+				mask, val);
 
 	return 0;
 }
 
-static int anatop_get_voltage_sel(struct regulator_dev *reg)
+static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -69,7 +71,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 	if (!anatop_reg->control_reg)
 		return -ENOTSUPP;
 
-	val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
+	regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val = (val & mask) >> anatop_reg->vol_bit_shift;
@@ -78,8 +80,8 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 }
 
 static struct regulator_ops anatop_rops = {
-	.set_voltage_sel = anatop_set_voltage_sel,
-	.get_voltage_sel = anatop_get_voltage_sel,
+	.set_voltage_sel = anatop_regmap_set_voltage_sel,
+	.get_voltage_sel = anatop_regmap_get_voltage_sel,
 	.list_voltage = regulator_list_voltage_linear,
 	.map_voltage = regulator_map_voltage_linear,
 };
@@ -92,7 +94,6 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	struct regulator_dev *rdev;
 	struct anatop_regulator *sreg;
 	struct regulator_init_data *initdata;
-	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
 	struct regulator_config config = { };
 	int ret = 0;
 
@@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	rdesc->ops = &anatop_rops;
 	rdesc->type = REGULATOR_VOLTAGE;
 	rdesc->owner = THIS_MODULE;
-	sreg->mfd = anatopmfd;
+
+	sreg->anatop = syscon_regmap_lookup_by_phandle(np, "fsl,anatop");
+	if (IS_ERR(sreg->anatop))
+		return PTR_ERR(sreg->anatop);
+
 	ret = of_property_read_u32(np, "anatop-reg-offset",
 				   &sreg->control_reg);
 	if (ret) {
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:44 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:44 +0800
Subject: [PATCH v2 6/7] ARM: dts: imx6q: add simple-bus compatible string for
 anatop
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-7-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Originally the anatop regulator devices are populated by mfd anatop driver.
Since mfd anatop driver will be deleted later, we change to populate the
regulator devices by devicetree automatically.
This will cause some warning messages as follows during boot due to device
recreation: "vdd1p1: Failed to create debugfs directory"
But it does not break any function.
Later, we will remove mfd anatop driver which can get rid of this
error message.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index da2bb71..0ebf853 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -379,7 +379,7 @@
 			};
 
 			anatop: anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop", "syscon";
+				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:43 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:43 +0800
Subject: [PATCH v2 5/7] ARM: imx6q: convert to use syscon to access anatop
 registers
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-6-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop registers.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v1->v2:
 * update to use generic regmap api
---
 arch/arm/mach-imx/Kconfig      |    2 +-
 arch/arm/mach-imx/mach-imx6q.c |   43 ++++++++++++++++-----------------------
 2 files changed, 19 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..7bba253 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -839,7 +839,7 @@ config SOC_IMX6Q
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC
 	select HAVE_SMP
-	select MFD_ANATOP
+	select MFD_SYSCON
 	select PINCTRL
 	select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6..5de869a 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,8 +24,9 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -121,38 +122,30 @@ static void __init imx6q_sabrelite_init(void)
 static void __init imx6q_usb_init(void)
 {
 	struct device_node *np;
-	struct platform_device *pdev = NULL;
-	struct anatop *adata = NULL;
+	struct regmap *anatop;
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-	if (np)
-		pdev = of_find_device_by_node(np);
-	if (pdev)
-		adata = platform_get_drvdata(pdev);
-	if (!adata) {
-		if (np)
-			of_node_put(np);
-		return;
-	}
-
 #define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT		0x00000210
 
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000
 
-	/*
-	 * The external charger detector needs to be disabled,
-	 * or the signal at DP will be poor
-	 */
-	anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B
-			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-	anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B |
-			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
+	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+	if (!IS_ERR(anatop)) {
+		/*
+		 * The external charger detector needs to be disabled,
+		 * or the signal at DP will be poor
+		 */
+		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B
+				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B |
+				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+	} else {
+		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+	}
 
 	of_node_put(np);
 }
-- 
1.7.0.4




From b29396 at freescale.com  Mon Aug 27 03:24:45 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Mon, 27 Aug 2012 15:24:45 +0800
Subject: [PATCH v2 7/7] mfd: anatop-mfd: remove anatop driver
In-Reply-To: <1346052285-4344-1-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
Message-ID: <1346052285-4344-8-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

The anatop registers are accessed via syscon now, no one will use
mfd anatop driver anymore, remove it.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 drivers/mfd/Kconfig        |    8 ---
 drivers/mfd/Makefile       |    1 -
 drivers/mfd/anatop-mfd.c   |  124 --------------------------------------------
 include/linux/mfd/anatop.h |   40 --------------
 4 files changed, 0 insertions(+), 173 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4a6c48e..4fb3f49 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -985,14 +985,6 @@ config MFD_STA2X11
 	depends on STA2X11
 	select MFD_CORE
 
-config MFD_ANATOP
-	bool "Support for Freescale i.MX on-chip ANATOP controller"
-	depends on SOC_IMX6Q
-	help
-	  Select this option to enable Freescale i.MX on-chip ANATOP
-	  MFD controller. This controller embeds regulator and
-	  thermal devices for Freescale i.MX platforms.
-
 config MFD_SYSCON
         bool "System Controller Register R/W Based on Regmap"
         select REGMAP_MMIO
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8384bc9..0f10a95 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -130,6 +130,5 @@ obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
-obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
 obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
deleted file mode 100644
index 5576e07..0000000
--- a/drivers/mfd/anatop-mfd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- * Copyright (C) 2012 Linaro
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
-
-u32 anatop_read_reg(struct anatop *adata, u32 addr)
-{
-	return readl(adata->ioreg + addr);
-}
-EXPORT_SYMBOL_GPL(anatop_read_reg);
-
-void anatop_write_reg(struct anatop *adata, u32 addr, u32 data, u32 mask)
-{
-	u32 val;
-
-	data &= mask;
-
-	spin_lock(&adata->reglock);
-	val = readl(adata->ioreg + addr);
-	val &= ~mask;
-	val |= data;
-	writel(val, adata->ioreg + addr);
-	spin_unlock(&adata->reglock);
-}
-EXPORT_SYMBOL_GPL(anatop_write_reg);
-
-static const struct of_device_id of_anatop_match[] = {
-	{ .compatible = "fsl,imx6q-anatop", },
-	{ },
-};
-
-static int __devinit of_anatop_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	void *ioreg;
-	struct anatop *drvdata;
-
-	ioreg = of_iomap(np, 0);
-	if (!ioreg)
-		return -EADDRNOTAVAIL;
-	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-	if (!drvdata)
-		return -ENOMEM;
-	drvdata->ioreg = ioreg;
-	spin_lock_init(&drvdata->reglock);
-	platform_set_drvdata(pdev, drvdata);
-	of_platform_populate(np, NULL, NULL, dev);
-
-	return 0;
-}
-
-static int __devexit of_anatop_remove(struct platform_device *pdev)
-{
-	struct anatop *drvdata;
-	drvdata = platform_get_drvdata(pdev);
-	iounmap(drvdata->ioreg);
-
-	return 0;
-}
-
-static struct platform_driver anatop_of_driver = {
-	.driver = {
-		.name = "anatop-mfd",
-		.owner = THIS_MODULE,
-		.of_match_table = of_anatop_match,
-	},
-	.probe		= of_anatop_probe,
-	.remove		= of_anatop_remove,
-};
-
-static int __init anatop_init(void)
-{
-	return platform_driver_register(&anatop_of_driver);
-}
-postcore_initcall(anatop_init);
-
-static void __exit anatop_exit(void)
-{
-	platform_driver_unregister(&anatop_of_driver);
-}
-module_exit(anatop_exit);
-
-MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
-MODULE_DESCRIPTION("ANATOP MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf..0000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * anatop.h - Anatop MFD driver
- *
- *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- *  Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_ANATOP_H
-#define __LINUX_MFD_ANATOP_H
-
-#include <linux/spinlock.h>
-
-/**
- * anatop - MFD data
- * @ioreg: ioremap register
- * @reglock: spinlock for register read/write
- */
-struct anatop {
-	void *ioreg;
-	spinlock_t reglock;
-};
-
-extern u32 anatop_read_reg(struct anatop *, u32);
-extern void anatop_write_reg(struct anatop *, u32, u32, u32);
-
-#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.0.4




From heiko at sntech.de  Mon Aug 27 04:01:03 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 27 Aug 2012 10:01:03 +0200
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <CAJuYYwQBOP7-D0fepDsCr+43ASKQ3CmMBMH-M79QH7r=xS85Eg@mail.gmail.com>
References: <201208252353.59345.heiko@sntech.de>
 <CAJuYYwQBOP7-D0fepDsCr+43ASKQ3CmMBMH-M79QH7r=xS85Eg@mail.gmail.com>
Message-ID: <201208271001.05026.heiko@sntech.de>

Hi Thomas,

thanks for your review:

Am Montag, 27. August 2012, 06:20:49 schrieb Thomas Abraham:
> Hi Heiko,
> 
> On 26 August 2012 03:23, Heiko St?bner <heiko at sntech.de> wrote:
> > Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
> > via the device tree. This patch implements dt-support for the
> > s3c24xx arches.
> > 
> > The controllers contain only 3 cells, as the underlying gpio controller
> > does not support controlling the drive strength on a gpio level.
> > 
> > Tested with the gpio-keys driver on a s3c2416 based machine.
> > 
> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> > ---
> > 
> >  .../devicetree/bindings/gpio/gpio-samsung.txt      |   38 ++++++++++++
> >  drivers/gpio/gpio-samsung.c                        |   63
> >  ++++++++++++++++++++ 2 files changed, 101 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt index
> > 5375625..ce6a7d4 100644
> > --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > 
> > @@ -39,3 +39,41 @@ Example:
> >                 #gpio-cells = <4>;
> >                 gpio-controller;
> >         
> >         };
> > 
> > +
> > +
> > +Samsung S3C24XX GPIO Controller
> > +
> > +Required properties:
> > +- compatible: Compatible property value should be
> > "samsung,s3c24xx-gpio".
> 
> This is debatable, but I would choose to be specific here and use
> "samsing,s3c2416-gpio". For instance, SoC's in s3c24xx family have
> differing value for pull none/down/up.

Hmmm, but the logic to drive the gpio controller is the same for all arches. 
The only difference is the number to use for the different pull up/down 
settings. So I think the "samsung,s3c24xx-gpio" is ok but the documentation 
should simply reflect the different pull settings.


> > +
> > +- reg: Physical base address of the controller and length of memory
> > mapped +  region.
> > +
> > +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by
> > client nodes +  should be the following with values derived from the SoC
> > user manual. +     <[phandle of the gpio controller node]
> > +      [pin number within the gpio controller]
> > +      [mux function]
> > +      [flags and pull up/down]
> > +
> > +  Values for gpio specifier:
> > +  - Pin number: depending on the controller a number from 0 up to 15.
> > +  - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
> > +                            1 - Pull Down Enabled.
> > +                            3 - Pull Up Enabled.
> 
> As per s3c2416 user manual, 2 is used for Pull Up and 3 is listed as
> reserved value. Any particular reason to use 3 here for pull up and
> not 2 as per the user manual?

Sorry, copy and paste error :-)


> > +          Bit 16 (0x00010000) - Input is active low.
> > +
> > +- gpio-controller: Specifies that the node is a gpio controller.
> > +- #address-cells: should be 1.
> > +- #size-cells: should be 1.
> 
> It would be informative to add information about the 'mux function'
> cell here as well. Specifically, on how to handle the banks that have
> an extended GPxSEL register that allow additional pin function
> selection.

Will add a mux function description.

Until now I've never realised the existence of the GPxSEL registers, so thanks 
for the pointer :-).

But is this used in the driver at all? All the setcfg/getcfg functions in 
gpio-samsung.c only handle the GPxCON registers - I haven't found code to 
handle the GPxSEL registers at all. So my guess is that this was never 
implemented - or that I'm blind ;-) .


> > +
> > +Example:
> > +
> > +       gpa: gpio-controller at 56000000 {
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               compatible = "samsung,s3c24xx-gpio";
> > +               reg = <0x56000000 0x10>;
> > +               #gpio-cells = <3>;
> > +               gpio-controller;
> > +       };
> > diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> > index a150d2e..80a2817 100644
> > --- a/drivers/gpio/gpio-samsung.c
> > +++ b/drivers/gpio/gpio-samsung.c
> > @@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct
> > samsung_gpio_chip *chip)
> > 
> >                 s3c_gpiolib_track(chip);
> >  
> >  }
> > 
> > +#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
> > +static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
> > +                       const struct of_phandle_args *gpiospec, u32
> > *flags) +{
> > +       unsigned int pin;
> > +
> > +       if (WARN_ON(gc->of_gpio_n_cells < 3))
> > +               return -EINVAL;
> > +
> > +       if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
> > +               return -EINVAL;
> > +
> > +       if (gpiospec->args[0] > gc->ngpio)
> > +               return -EINVAL;
> > +
> > +       pin = gc->base + gpiospec->args[0];
> > +
> > +       if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
> > +               pr_warn("gpio_xlate: failed to set pin function\n");
> > +       if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
> > +               pr_warn("gpio_xlate: failed to set pin pull up/down\n");
> > +
> > +       if (flags)
> > +               *flags = gpiospec->args[2] >> 16;
> > +
> > +       return gpiospec->args[0];
> > +}
> > +
> > +static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
> > +       { .compatible = "samsung,s3c24xx-gpio", },
> > +       {}
> > +};
> > +
> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
> > samsung_gpio_chip *chip, +                                              
> >  u64 base, u64 offset) +{
> > +       struct gpio_chip *gc =  &chip->chip;
> > +       u64 address;
> > +
> > +       if (!of_have_populated_dt())
> > +               return;
> > +
> > +       address = chip->base ? base + ((u32)chip->base & 0xfff) : base +
> > offset; +       gc->of_node = of_find_matching_node_by_address(NULL,
> > +                       s3c24xx_gpio_dt_match, address);
> > +       if (!gc->of_node) {
> > +               pr_info("gpio: device tree node not found for gpio
> > controller" +                       " with base address %08llx\n",
> > address); +               return;
> > +       }
> > +       gc->of_gpio_n_cells = 3;
> > +       gc->of_xlate = s3c24xx_gpio_xlate;
> > +}
> > +#elif defined(CONFIG_PLAT_S3C24XX)
> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
> > samsung_gpio_chip *chip, +                                              
> >  u64 base, u64 offset) +{
> > +       return;
> > +}
> > +#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
> > +
> > 
> >  static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip
> >  *chip,
> >  
> >                                              int nr_chips, void __iomem
> >                                              *base)
> >  
> >  {
> > 
> > @@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct
> > samsung_gpio_chip *chip,
> > 
> >                         gc->direction_output =
> >                         samsung_gpiolib_2bit_output;
> >                 
> >                 samsung_gpiolib_add(chip);
> > 
> > +
> > +               s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i *
> > 0x10);
> > 
> >         }
> >  
> >  }
> > 
> > --
> > 1.7.2.3
> 
> Overall, this is patch looks fine.
> 
> Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


Heiko


From nicolas.ferre at atmel.com  Mon Aug 27 04:01:21 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 27 Aug 2012 10:01:21 +0200
Subject: [PATCH] ASoC: atmel-ssc: include linux/io.h for raw io
In-Reply-To: <20120825202515.GF6520@opensource.wolfsonmicro.com>
References: <20120823152324.GI7995@opensource.wolfsonmicro.com>
 <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
 <20120825202515.GF6520@opensource.wolfsonmicro.com>
Message-ID: <503B2951.3010508@atmel.com>

On 08/25/2012 10:25 PM, Mark Brown :
> On Thu, Aug 23, 2012 at 06:14:54PM +0200, Nicolas Ferre wrote:
>> From: Joachim Eastwood <manabian at gmail.com>
>>
>> Include linux/io.h for raw io operations in atmel-scc header.
>>
>> This fixes the following build error:
>>   CC [M]  sound/soc/atmel/atmel_ssc_dai.o
>> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_interrupt':
>> sound/soc/atmel/atmel_ssc_dai.c:171: error: implicit declaration of function '__raw_readl'
>> sound/soc/atmel/atmel_ssc_dai.c: In function 'atmel_ssc_shutdown':
>> sound/soc/atmel/atmel_ssc_dai.c:249: error: implicit declaration of function '__raw_writel'
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
> but why not just apply it to the ASoC tree?

Fine by me then: so Mark, can you take it for a 3.6 fixes branch?

(I remove it from my at91-fixes branch that will go through arm-soc tree).

Best regards,
-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Mon Aug 27 04:03:45 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 27 Aug 2012 10:03:45 +0200
Subject: [GIT PULL] at91: fixes for 3.6 (take 1)
In-Reply-To: <5037A4F3.9090608@atmel.com>
References: <5037A4F3.9090608@atmel.com>
Message-ID: <503B29E1.5080901@atmel.com>

On 08/24/2012 05:59 PM, Nicolas Ferre :
> The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:
> 
>   Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/at91linux/linux-at91.git tags/at91-fixes
> 
> for you to fetch changes up to 0d4d1e37ca732615717d4434b58682f81a6bb61c:
> 
>   ARM: at91/feature-removal-schedule: delay at91_mci removal (2012-08-24 10:45:07 +0200)
> 
> ----------------------------------------------------------------
> Fixes for AT91 related to:
> - move to sparse IRQ: some drivers were forgotten
> - a build error in sound driver & a DTS typo
> - the delay for removal of old at91_mci driver
> 
> ----------------------------------------------------------------
> Bo Shen (1):
>       ARM: at91/dts: remove partial parameter in at91sam9g25ek.dts
> 
> Joachim Eastwood (1):
>       ASoC: atmel-ssc: include linux/io.h for raw io

Hi,

As per Mark's suggestion, this one will go through ASoC tree. So I have
removed it from the tag. I resend a pull request now.

Best regards,


> Ludovic Desroches (3):
>       ARM: at91: fix system timer irq issue due to sparse irq support
>       ARM: at91: fix rtc-at91sam9 irq issue due to sparse irq support
>       ARM: at91/feature-removal-schedule: delay at91_mci removal
> 
> Nicolas Ferre (1):
>       ARM: at91/clock: fix PLLA overclock warning
> 
>  Documentation/feature-removal-schedule.txt |    2 +-
>  arch/arm/boot/dts/at91sam9g25ek.dts        |    2 +-
>  arch/arm/mach-at91/at91rm9200_time.c       |    2 +-
>  arch/arm/mach-at91/at91sam9260_devices.c   |    6 +++++-
>  arch/arm/mach-at91/at91sam9261_devices.c   |    6 +++++-
>  arch/arm/mach-at91/at91sam9263_devices.c   |   10 ++++++++--
>  arch/arm/mach-at91/at91sam9g45_devices.c   |    6 +++++-
>  arch/arm/mach-at91/at91sam9rl_devices.c    |    6 +++++-
>  arch/arm/mach-at91/clock.c                 |   12 ++++++++++++
>  drivers/rtc/rtc-at91sam9.c                 |   22 +++++++++++++++-------
>  include/linux/atmel-ssc.h                  |    1 +
>  11 files changed, 59 insertions(+), 16 deletions(-)
> 
> Thanks, best regards,
> 


-- 
Nicolas Ferre


From linux at arm.linux.org.uk  Mon Aug 27 04:09:13 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 27 Aug 2012 09:09:13 +0100
Subject: For buddy system initialization, the holes between banks
 adjacent will be released to buddy allocator?
In-Reply-To: <CAFNq8R7fCyD5P4mAA8LGzcOvVynSJa8mOBDwrLOF9mVvo9q5VA@mail.gmail.com>
References: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>
 <CAFNq8R7fCyD5P4mAA8LGzcOvVynSJa8mOBDwrLOF9mVvo9q5VA@mail.gmail.com>
Message-ID: <20120827080913.GL18957@n2100.arm.linux.org.uk>

On Mon, Aug 27, 2012 at 10:42:40AM +0800, Li Haifeng wrote:
> Just now, I tested it on my ARM development board.
> 
> The holes between banks does be released to buddy allocator. And the
> buddy system will allocate holes for thread, which will cause fault.
> Is it right?

Could you rephrase your question please?


From zhangfei.gao at gmail.com  Mon Aug 27 04:23:31 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Mon, 27 Aug 2012 16:23:31 +0800
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
Message-ID: <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>

On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> On Mon, Aug 27, 2012 at 9:51 AM, zhangfei gao <zhangfei.gao at gmail.com> wrote:
>> Hi, All
>>
>> We met question about dmac_map_area & dmac_flush_range from user addr.
>> mcr would not return on armv7 processor.
>>
>> Existing ion carveout heap does not support partial cache flush.
>> Total cache will be flushed at all.
>>
>> There is only one dirty bit for carveout heap, as well as sg_table->nents.
>> drivers/gpu/ion/ion_carveout_heap.c
>> ion_carveout_heap_map_dma -> sg_alloc_table(table, 1, GFP_KERNEL);
>> ion_buffer_alloc_dirty -> pages = buffer->sg_table->nents;
>>
>> We want to support partial cache flush.
>> Align to cache line, instead of PAGE_SIZE, for efficiency consideration.
>> We have considered extended dirty bit, but looks like only align to PAGE_SIZE.
>>
>> For experiment we modify ioctl ION_IOC_SYNC on armv7.
>> And directly use dmac_map_area & dmac_flush_range with add from user space.
>> However, we find dmac_map_area can not work with this addr from user space.
>> In fact, it is  mcr can not work with addr from user space, it would hung.
>
> Let me summerize it. First, user space address is mapped. Then,
> flushing user space
> address is triggered. It's a workaround of fixing non-existed virtual
> address without fixing
> vmap() or any other solution. It's just a quick fix.
>
> Zhangfei,
> I doubt that the issue may be caused by missing memory barrier.
> Flushing is using
> coprocessor instructions. It's a little different.

Is there any limitation that dmac_map_area & dmac_flush_range
supporting addr mapped from user space?
And mcr can not return with user space addr.
While __davt_svc -> page fault happen, even the page table has already
been set up.

Thanks


From linux at arm.linux.org.uk  Mon Aug 27 04:27:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 27 Aug 2012 09:27:55 +0100
Subject: [GIT PULL] io.h clean-up for PCI
In-Reply-To: <5016A0B8.5010607@gmail.com>
References: <50049285.1060100@gmail.com> <50130F36.4090902@gmail.com>
 <20120728143850.GA11713@mudshark.cambridge.arm.com>
 <50166A60.8000502@gmail.com> <20120730143119.GN6802@n2100.arm.linux.org.uk>
 <5016A0B8.5010607@gmail.com>
Message-ID: <20120827082755.GM18957@n2100.arm.linux.org.uk>

On Mon, Jul 30, 2012 at 09:56:56AM -0500, Rob Herring wrote:
> On 07/30/2012 09:31 AM, Russell King - ARM Linux wrote:
> > On Mon, Jul 30, 2012 at 06:05:04AM -0500, Rob Herring wrote:
> >> On 07/28/2012 09:38 AM, Will Deacon wrote:
> >>> Hi Rob,
> >>>
> >>> On Fri, Jul 27, 2012 at 10:59:18PM +0100, Rob Herring wrote:
> >>>> Please pull updated io.h cleanup for PCI branch. I rebased this as the
> >>>> changes shifted things around a bit. This has the following changes:
> >>>>
> >>>> - Incorporated fixes from you and Stephen
> >>>> - Add early i/o mapping pci_map_io_early and enable on footbridge and
> >>>> integrator for VGA console
> >>>
> >>> Unfortunately, I still experience the same hang on integrator with this
> >>> revised patch series. Given the turnaround time for testing this, I don't
> >>> think this should block the series, but I would like to get to the bottom of
> >>> it if possible.
> >>>
> >>> I tried annotating the PCI code (including fault handlers) and the VGA
> >>> console code but I couldn't find the culprit. I suppose the next step is
> >>> JTAG, but that requires steal^Wborrowing some hardware from work.
> >>
> >> I did do some tests with qemu by adding i/o setup to integrator/cp.
> >> Without it, I would abort on 0xfee003xx (vga regs). Once I added the
> >> setup, I got to an abort on a PCI memory address which I did not setup.
> >>
> >> We can always revert integrator change if we can figure this out...
> > 
> > Err, Integrator/CP doesn't have PCI nor does it have VGA.  Only the
> > Integrator/AP has that.
> 
> Yes, I know. But there is no AP model within qemu. I added the mapping
> to AP and enabled VGA console to do some basic checks that i/o accesses
> happen. It didn't really have to be integrator platform at all for this
> test. I know it's not much of a test, but it's something beyond
> compiling and staring at the code.
> 
> I've also tested PCI i/o with versatile under qemu.

What's the conflict resolution for the fix for ioremap of phys 0 (posted
by me previously) and your reoganisation and creation of
vm_reserve_area_early() ?

Note that I'm taking the autobuilder offline until this is resolved because
the tree currently isn't in a buildable state because of this.


From linux at arm.linux.org.uk  Mon Aug 27 04:29:14 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 27 Aug 2012 09:29:14 +0100
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
 <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
Message-ID: <20120827082914.GN18957@n2100.arm.linux.org.uk>

On Mon, Aug 27, 2012 at 04:23:31PM +0800, zhangfei gao wrote:
> On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
> > Let me summerize it. First, user space address is mapped. Then,
> > flushing user space
> > address is triggered. It's a workaround of fixing non-existed virtual
> > address without fixing
> > vmap() or any other solution. It's just a quick fix.
> >
> > Zhangfei,
> > I doubt that the issue may be caused by missing memory barrier.
> > Flushing is using
> > coprocessor instructions. It's a little different.
> 
> Is there any limitation that dmac_map_area & dmac_flush_range
> supporting addr mapped from user space?

They DEFINITELY DO NOT SUPPORT FLUSHING USER SPACE.


From s.hauer at pengutronix.de  Mon Aug 27 04:30:21 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 27 Aug 2012 10:30:21 +0200
Subject: [PATCH 4/5] DRM: add i.MX IPUv3 base driver
In-Reply-To: <5037A4B3.7030001@gmail.com>
References: <806769921.2812305.1345819977325.JavaMail.root@advansee.com>
 <5037A4B3.7030001@gmail.com>
Message-ID: <20120827083021.GB26594@pengutronix.de>

Hi Dirk,

On Fri, Aug 24, 2012 at 05:58:43PM +0200, Dirk Behme wrote:
> >
> >Matt, I think you also have video support for efikamx, don't you?
> >
> >Is there a plan to merge all these developments into upstream?
> 
> It's my understanding that Richard is looking at the VPU for i.MX6,
> based on Sascha's IPU patches (this thread) and Javier Martin's
> i.MX27 coda patches.

The VPU has no dependencies on the IPU, it's completely orthogonal.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From afzal at ti.com  Mon Aug 27 04:34:44 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 08:34:44 +0000
Subject: [PATCH v6 10/10] ARM: OMAP2+: tusb6010: generic timing calculation
In-Reply-To: <20120824194630.GU11011@atomide.com>
References: <cover.1345524670.git.afzal@ti.com>
 <bc000ac53bb1b3ae1a951bbcf372caf6336d2a19.1345524670.git.afzal@ti.com>
 <20120824194630.GU11011@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA589@DBDE01.ent.ti.com>

Hi Tony,

On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote:

> This hangs n800 during the boot.

Shall I read the above as n800 boot without patch 10/10,
but with the other patches in this series ?

As per the board file, n800 has tusb6010 as well as
OneNAND in sync read & async write mode, was OneNAND
working without 10/10.

Do you have any idea, which timing could have gone wrong,
can you please sent me DEBUG enabled gpmc log with and
without 10/10.

Regards
Afzal


From ulf.hansson at linaro.org  Mon Aug 27 04:36:56 2012
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Mon, 27 Aug 2012 10:36:56 +0200
Subject: [PATCH 1/4] clk: ux500: Adapt PRCMU and PRCC clocks for common clk
In-Reply-To: <201208260447.58396.arnd@arndb.de>
References: <1345807565-7729-1-git-send-email-ulf.hansson@stericsson.com>
 <1345807565-7729-2-git-send-email-ulf.hansson@stericsson.com>
 <201208260447.58396.arnd@arndb.de>
Message-ID: <CAPDyKFqntUxx2Sr=myk42xT2_Gf=dZJQq+ytxph5tYxAFLCVog@mail.gmail.com>

On 26 August 2012 06:47, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 24 August 2012, Ulf Hansson wrote:
>> From: Ulf Hansson <ulf.hansson at linaro.org>
>>
>> First version of common clock implementation of PRCMU clocks
>> and PRCC clocks for ux500 platforms.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
>
> Very nice, glad to see you got this working!
>
> I only noticed one thing that you should improve:
>

Thanks for your input. I will send an updated patch.

>> +#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
>> +
>> +struct clk_prcc {
>> +     struct clk_hw hw;
>> +     unsigned int io_base;
>> +     u32 cg_sel;
>> +     int is_enabled;
>> +};
>> +
>> +/* PRCC clock operations. */
>> +
>> +static int clk_prcc_pclk_enable(struct clk_hw *hw)
>> +{
>> +     struct clk_prcc *clk = to_clk_prcc(hw);
>> +     void __iomem *io_base = __io_address(clk->io_base);
>
> In a proper device driver, we should not use hacks like __io_address. Please
> change the driver to ioremap the register area at initialization time, and
> don't pass a physical io_base like above but instead pass an offset into
> the register area.
>
>         Arnd

Kind regards
Ulf Hansson


From zhangfei.gao at gmail.com  Mon Aug 27 04:56:44 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Mon, 27 Aug 2012 16:56:44 +0800
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <20120827082914.GN18957@n2100.arm.linux.org.uk>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
 <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
 <20120827082914.GN18957@n2100.arm.linux.org.uk>
Message-ID: <CAMj5BkjqUNV2o_BMyHH8C5ZCsUf6qChamc6h4H-a9otEGVBx4A@mail.gmail.com>

On Mon, Aug 27, 2012 at 4:29 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 27, 2012 at 04:23:31PM +0800, zhangfei gao wrote:
>> On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
>> <haojian.zhuang at gmail.com> wrote:
>> > Let me summerize it. First, user space address is mapped. Then,
>> > flushing user space
>> > address is triggered. It's a workaround of fixing non-existed virtual
>> > address without fixing
>> > vmap() or any other solution. It's just a quick fix.
>> >
>> > Zhangfei,
>> > I doubt that the issue may be caused by missing memory barrier.
>> > Flushing is using
>> > coprocessor instructions. It's a little different.
>>
>> Is there any limitation that dmac_map_area & dmac_flush_range
>> supporting addr mapped from user space?
>
> They DEFINITELY DO NOT SUPPORT FLUSHING USER SPACE.

Thanks Russell

Any suggestion of flushing cache according to cache line, instead of PAGE_SIZE.
In order to get specific area, we use addr from user directly, which
may not be the PAGE start.

We have some usage case to flush cache according to cache line.
CPU - cache - ddr - gpu
1. For correctness, driver only flush used size, if align to PAGE_SIZE,
other area may be flushed by mistake.
2. for efficiency, cache line align will be perfered.

Thanks


From anarsoul at gmail.com  Mon Aug 27 04:57:04 2012
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Mon, 27 Aug 2012 11:57:04 +0300
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208271001.05026.heiko@sntech.de>
References: <201208252353.59345.heiko@sntech.de>
 <CAJuYYwQBOP7-D0fepDsCr+43ASKQ3CmMBMH-M79QH7r=xS85Eg@mail.gmail.com>
 <201208271001.05026.heiko@sntech.de>
Message-ID: <CA+E=qVfV1DL1ikjVnLd7qTeCx9C8Z7dGvhh_9NSgxPYrOCJ=0g@mail.gmail.com>

Hi,

On Mon, Aug 27, 2012 at 11:01 AM, Heiko St?bner <heiko at sntech.de> wrote:
> Hi Thomas,
>
> thanks for your review:
>
> Hmmm, but the logic to drive the gpio controller is the same for all arches.
> The only difference is the number to use for the different pull up/down
> settings. So I think the "samsung,s3c24xx-gpio" is ok but the documentation
> should simply reflect the different pull settings.
>

Also s3c2410 and s3c2440 has different count of GPIOs. And that could
be a problem on machines
with GPIO-expanders (h1940 machine)

>> It would be informative to add information about the 'mux function'
>> cell here as well. Specifically, on how to handle the banks that have
>> an extended GPxSEL register that allow additional pin function
>> selection.
>
> Will add a mux function description.
>
> Until now I've never realised the existence of the GPxSEL registers, so thanks
> for the pointer :-).
>
> But is this used in the driver at all? All the setcfg/getcfg functions in
> gpio-samsung.c only handle the GPxCON registers - I haven't found code to
> handle the GPxSEL registers at all. So my guess is that this was never
> implemented - or that I'm blind ;-) .

There're no GPxSEL registers on s3c2410/s3c2440/s3c2442. Is it
something s3c2412/sec2416 specific?

Regards
Vasily


From horms at verge.net.au  Mon Aug 27 05:08:51 2012
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 Aug 2012 18:08:51 +0900
Subject: New Renesas Tree
Message-ID: <20120827090851.GK29274@verge.net.au>

Hi,

I am in the process of taking over the maintenance work that Rafael Wysocki
was previously handling through his renesas tree. That is basically the ARM
side of things for Renesas. As such I have created my own renesas tree:

	git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git

The basic structure that I am aiming for is to have topic-branches that
I will request that the arm-soc team pull. And a merge-branch next, which
will be frequently rebased to include all pending topic-branches and
should be included in linux-next.

As things stand I have now sifted through the backlog of patches and I have
either queued up or sent an email query about all patches that I could
find. In either case, if you have an outstanding patch for the renesas tree
and you have not received an email from me about it in the past few days
that means that I have missed it, so please repost.

I will endeavour to get all currently queued patches included in 3.7.



From ian.molton at codethink.co.uk  Mon Aug 27 05:25:20 2012
From: ian.molton at codethink.co.uk (Ian Molton)
Date: Mon, 27 Aug 2012 11:25:20 +0200
Subject: [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <50379A96.1050409@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>
 <50379609.1020006@codethink.co.uk> <50379A96.1050409@free-electrons.com>
Message-ID: <503B3D00.2000500@codethink.co.uk>

On 24/08/12 17:15, Gregory CLEMENT wrote:
> On 08/24/2012 04:56 PM, Ian Molton wrote:> On 24/08/12 11:09, Gregory CLEMENT wrote:
>>> + compatible = "marvell,aurora-cache-with-outer";
>> This reads wrong.
>>
>> perhaps aurora-with-outer-cache?
> We can use
> compatible = "marvell,aurora-outer-cache"
> and
> compatible = "marvell,aurora-system-cache"
>
> which is a better description of the L2 cache controller indeed.

Yes, much clearer.

> I guess you meant:
>
> compatible = "marvell,armada370", "marvell,armada-370-xp";
>     L2: l2-cache {										
>         compatible = "marvell,aurora-cache";
>         reg = <0xd0008000 0x1000>;
>         cache-id-part = <0x100>;
>         wt-override;
>         with-outer="yes";
>     };

Yes :)

-Ian


From heiko at sntech.de  Mon Aug 27 05:44:03 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Mon, 27 Aug 2012 11:44:03 +0200
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <CA+E=qVfV1DL1ikjVnLd7qTeCx9C8Z7dGvhh_9NSgxPYrOCJ=0g@mail.gmail.com>
References: <201208252353.59345.heiko@sntech.de>
 <201208271001.05026.heiko@sntech.de>
 <CA+E=qVfV1DL1ikjVnLd7qTeCx9C8Z7dGvhh_9NSgxPYrOCJ=0g@mail.gmail.com>
Message-ID: <201208271144.03681.heiko@sntech.de>

Hi Vasily,

Am Montag, 27. August 2012, 10:57:04 schrieb Vasily Khoruzhick:
> Hi,
> 
> On Mon, Aug 27, 2012 at 11:01 AM, Heiko St?bner <heiko at sntech.de> wrote:
> > Hi Thomas,
> > 
> > thanks for your review:
> > 
> > Hmmm, but the logic to drive the gpio controller is the same for all
> > arches. The only difference is the number to use for the different pull
> > up/down settings. So I think the "samsung,s3c24xx-gpio" is ok but the
> > documentation should simply reflect the different pull settings.
> 
> Also s3c2410 and s3c2440 has different count of GPIOs. And that could
> be a problem on machines
> with GPIO-expanders (h1940 machine)

I'm not sure I follow :-) . 

The compatible property here only sets the mechanism on how to handle the 
gpios defined in the devicetree - here to use the s3c24xx-style. As you can 
see in gpio-samsung.c the handling is already unified for all the s3c24xx 
architectures.

The definition of what gpio banks exist is then done in the respective 
devicetree file for the individual SoC. And of course here one would have 
individual definitions, depending on the banks present.

For reference my quite empty s3c2416.dtsi file currently looks like:

/include/ "skeleton.dtsi"

/ {
	compatible = "samsung,s3c2416";

	cpus {
		cpu at 0 {
			compatible = "arm,arm926ejs";
		};
	};

	gpio-controllers {
		#address-cells = <1>;
		#size-cells = <1>;
		gpio-controller;
		ranges;

		gpa: gpio-controller at 56000000 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000000 0x10>;
			#gpio-cells = <3>;
		};

		gpb: gpio-controller at 56000010 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000010 0x10>;
			#gpio-cells = <3>;
		};

		gpc: gpio-controller at 56000020 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000020 0x10>;
			#gpio-cells = <3>;
		};

		gpd: gpio-controller at 56000030 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000030 0x10>;
			#gpio-cells = <3>;
		};

		gpe: gpio-controller at 56000040 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000040 0x10>;
			#gpio-cells = <3>;
		};

		gpf: gpio-controller at 56000050 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000050 0x10>;
			#gpio-cells = <3>;
		};

		gpg: gpio-controller at 56000060 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000060 0x10>;
			#gpio-cells = <3>;
		};

		gph: gpio-controller at 56000070 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000070 0x10>;
			#gpio-cells = <3>;
		};

		/* s3c2443 and later */
		gpj: gpio-controller at 560000D0 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x560000D0 0x10>;
			#gpio-cells = <3>;
		};

		gpk: gpio-controller at 560000E0 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x560000E0 0x10>;
			#gpio-cells = <3>;
		};

		gpl: gpio-controller at 560000F0 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x560000F0 0x10>;
			#gpio-cells = <3>;
		};

		gpm: gpio-controller at 56000100 {
			compatible = "samsung,s3c24xx-gpio";
			reg = <0x56000100 0x10>;
			#gpio-cells = <3>;
		};
	};
};

Other s3c24xx SoCs would of course need to define their own.

> >> It would be informative to add information about the 'mux function'
> >> cell here as well. Specifically, on how to handle the banks that have
> >> an extended GPxSEL register that allow additional pin function
> >> selection.
> > 
> > Will add a mux function description.
> > 
> > Until now I've never realised the existence of the GPxSEL registers, so
> > thanks for the pointer :-).
> > 
> > But is this used in the driver at all? All the setcfg/getcfg functions in
> > gpio-samsung.c only handle the GPxCON registers - I haven't found code to
> > handle the GPxSEL registers at all. So my guess is that this was never
> > implemented - or that I'm blind ;-) .
> 
> There're no GPxSEL registers on s3c2410/s3c2440/s3c2442. Is it
> something s3c2412/sec2416 specific?

s3c2412 also does not have it ... it seems entirely specific to 
s3c2416/s3c2450 and as written also seems to be unused.
So I would tend to ignore it for now :-) .


Heiko


From anarsoul at gmail.com  Mon Aug 27 05:51:27 2012
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Mon, 27 Aug 2012 12:51:27 +0300
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208271144.03681.heiko@sntech.de>
References: <201208252353.59345.heiko@sntech.de>
 <201208271001.05026.heiko@sntech.de>
 <CA+E=qVfV1DL1ikjVnLd7qTeCx9C8Z7dGvhh_9NSgxPYrOCJ=0g@mail.gmail.com>
 <201208271144.03681.heiko@sntech.de>
Message-ID: <CA+E=qVf9+J1rtvr7snhfRgqKHgWZ+g7TfcQuP8qm00+HH86CDQ@mail.gmail.com>

On Mon, Aug 27, 2012 at 12:44 PM, Heiko St?bner <heiko at sntech.de> wrote:
> Hi Vasily,
>
> I'm not sure I follow :-) .
>
> The compatible property here only sets the mechanism on how to handle the
> gpios defined in the devicetree - here to use the s3c24xx-style. As you can
> see in gpio-samsung.c the handling is already unified for all the s3c24xx
> architectures.
>
> The definition of what gpio banks exist is then done in the respective
> devicetree file for the individual SoC. And of course here one would have
> individual definitions, depending on the banks present.
>
> For reference my quite empty s3c2416.dtsi file currently looks like:
>
> /include/ "skeleton.dtsi"
>
> / {
>         compatible = "samsung,s3c2416";
>
>         cpus {
>                 cpu at 0 {
>                         compatible = "arm,arm926ejs";
>                 };
>         };
>
>         gpio-controllers {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 gpio-controller;
>                 ranges;
>
>                 gpa: gpio-controller at 56000000 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000000 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpb: gpio-controller at 56000010 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000010 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpc: gpio-controller at 56000020 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000020 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpd: gpio-controller at 56000030 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000030 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpe: gpio-controller at 56000040 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000040 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpf: gpio-controller at 56000050 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000050 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpg: gpio-controller at 56000060 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000060 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gph: gpio-controller at 56000070 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000070 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 /* s3c2443 and later */
>                 gpj: gpio-controller at 560000D0 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x560000D0 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpk: gpio-controller at 560000E0 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x560000E0 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpl: gpio-controller at 560000F0 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x560000F0 0x10>;
>                         #gpio-cells = <3>;
>                 };
>
>                 gpm: gpio-controller at 56000100 {
>                         compatible = "samsung,s3c24xx-gpio";
>                         reg = <0x56000100 0x10>;
>                         #gpio-cells = <3>;
>                 };
>         };
> };
>
> Other s3c24xx SoCs would of course need to define their own.

I see. But how does it handle GPA bank (which is output-only, and
GPACON differs a bit from GP{B-J}CON? And some banks has lower number
(not 16) of GPIOs, like GPH.

Also, what would be value for S3C_GPIO_END?

Regards
Vasily


From hvaibhav at ti.com  Mon Aug 27 06:04:02 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 27 Aug 2012 15:34:02 +0530
Subject: [PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
Message-ID: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>

Currently, the device names for the dcan module follows the
format "dcan.X", where 'X' is the dcan instance number.
On other side, driver may request for clock with/without con_id
and dev_id, and it is expected that platform should respect this
request and return the requested clock handle.

Now, when using device tree, the format of the device name created
by OF layer is different, "<reg-address>.<device-name>",
assuming that the device-tree "reg" property is specified.
This causes the look-up failure for clock node in dcan driver

To fix this add new dcan clock alias for using device-tree.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <robherring2 at gmail.com>
---
 arch/arm/mach-omap2/clock33xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index ae27de8..a4006b2 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),
 	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),
 	CLK(NULL,	"dcan0_fck",		&dcan0_fck,	CK_AM33XX),
+	CLK("481cc000.d_can",	NULL,		&dcan0_fck,	CK_AM33XX),
 	CLK(NULL,	"dcan1_fck",		&dcan1_fck,	CK_AM33XX),
+	CLK("481d0000.d_can",	NULL,		&dcan1_fck,	CK_AM33XX),
 	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
 	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
 	CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
-- 
1.7.0.4



From heiko at sntech.de  Mon Aug 27 06:12:19 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Mon, 27 Aug 2012 12:12:19 +0200
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <CA+E=qVf9+J1rtvr7snhfRgqKHgWZ+g7TfcQuP8qm00+HH86CDQ@mail.gmail.com>
References: <201208252353.59345.heiko@sntech.de>
 <201208271144.03681.heiko@sntech.de>
 <CA+E=qVf9+J1rtvr7snhfRgqKHgWZ+g7TfcQuP8qm00+HH86CDQ@mail.gmail.com>
Message-ID: <201208271212.20016.heiko@sntech.de>

Am Montag, 27. August 2012, 11:51:27 schrieb Vasily Khoruzhick:
> On Mon, Aug 27, 2012 at 12:44 PM, Heiko St?bner <heiko at sntech.de> wrote:
> > Hi Vasily,
> > 
> > I'm not sure I follow :-) .
> > 
> > The compatible property here only sets the mechanism on how to handle the
> > gpios defined in the devicetree - here to use the s3c24xx-style. As you
> > can see in gpio-samsung.c the handling is already unified for all the
> > s3c24xx architectures.
> > 
> > The definition of what gpio banks exist is then done in the respective
> > devicetree file for the individual SoC. And of course here one would have
> > individual definitions, depending on the banks present.
> > 
> > For reference my quite empty s3c2416.dtsi file currently looks like:
> > 
> > /include/ "skeleton.dtsi"
> > 
> > / {
> > 
> >         compatible = "samsung,s3c2416";
> >         
> >         cpus {
> >         
> >                 cpu at 0 {
> >                 
> >                         compatible = "arm,arm926ejs";
> >                 
> >                 };
> >         
> >         };
> >         
> >         gpio-controllers {
> >         
> >                 #address-cells = <1>;
> >                 #size-cells = <1>;
> >                 gpio-controller;
> >                 ranges;
> >                 
> >                 gpa: gpio-controller at 56000000 {
> >                 
> >                         compatible = "samsung,s3c24xx-gpio";
> >                         reg = <0x56000000 0x10>;
> >                         #gpio-cells = <3>;
> >                 
> >                 };
> >                 
> >                 gpb: gpio-controller at 56000010 {
> >                 
> >                         compatible = "samsung,s3c24xx-gpio";
> >                         reg = <0x56000010 0x10>;
> >                         #gpio-cells = <3>;
> >                 
> >                 };

[ ... ]

> >         };
> > 
> > };
> > 
> > Other s3c24xx SoCs would of course need to define their own.
> 
> I see. But how does it handle GPA bank (which is output-only, and
> GPACON differs a bit from GP{B-J}CON? And some banks has lower number
> (not 16) of GPIOs, like GPH.
> 
> Also, what would be value for S3C_GPIO_END?

The creation of the banks is still done in gpio-samsung.c and the special 
handling of bank-a is still sitting in the s3c24xx_gpios[] array there.

In general the gpios are still created completely like before and the 
devicetree information is only attached to them so that dt-devices can 
reference them.

As you can see in the original patch, after the respective chip got created in 
s3c24xx_gpiolib_add_chips, s3c24xx_gpiolib_attach_ofnode searches for the 
representation of it in the device tree and attaches this to the chip.

So nothing really changed, except that dt-devices can now reference gpios and 
if they do s3c24xx_gpio_xlate will get called to configure them with the 
target values from the dt.

Currently I'm also only using it in a mixed mode configuration [1], 
supplementing a normal machine file with some devices from the devicetree - 
especially as I still need to figure out, what to do about the interrupt 
controller.


Heiko


[1] https://github.com/mmind/linux-es600/blob/topic/es600-
devel/arch/arm/boot/dts/s3c24xx-sg06.dts


From ludovic.desroches at atmel.com  Mon Aug 27 06:16:57 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 27 Aug 2012 12:16:57 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>
Message-ID: <503B4919.6080306@atmel.com>

Hi Nikolaus,

Le 11/08/2011 11:49 AM, Nikolaus Voss a ?crit :
> This driver has the following properties compared to the old driver:
> 1. Support for multiple interfaces.
> 2. Interrupt driven I/O as opposed to polling/busy waiting.
> 3. Support for _one_ repeated start (Sr) condition, which is enough
>     for most real-world applications including all SMBus transfer types.
>     (The hardware does not support issuing arbitrary Sr conditions on the
>      bus.)
>
> testing: SoC: at91sam9g45
> 	 - BQ20Z80 battery SMBus client.
> 	 - on a 2.6.38 kernel with several i2c clients (temp-sensor,
> 	   audio-codec, touchscreen-controller, w1-bridge, io-expanders)
>
> Signed-off-by: Nikolaus Voss <n.voss at weinmann.de>
> Reviewed-by: Felipe Balbi <balbi at ti.com>
> Tested-by: Hubert Feurstein <h.feurstein at gmail.com>
>

Tested-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with 
eeprom, temperature sensor and rtc devices (and wolfson chip for sam9g20).

Thanks for your work on this driver and sorry for the delay.

Regards

Ludovic

> v11: - fix for flags persistency suggested by Carsten Behling
>       - calc_twi_clock fix for sam9261 by Ludovic Desroches
> v10: - applied fix for RXRDY overrun bug submitted by Hubert Feurstein
>       - applied fix for calculating twi_clk
> v9: - merge i2c-at91.c patches to single patch
>      - rewrite cwgr reg after timeout
> v8: - remove local include
>      - remove cpu_is_rm9200() and put twi hw bug info in platform_device
>      - use readl/writel_relaxed instead of __raw_readl/writel
> v7: i)  fix bug if internal address > 1 byte
>      ii) send stop when len == 1 (both reported by Carsten Behling)
> v6: support for I2C_SMBUS_BLOCK_DATA transfers.
>      Better use of clk_(un)prepare().
>      More sensible transfer timeout.
> v5: Another round of review comments from Ryan Mallon, Felipe Balbi
>      and Russell King: convert twi clk to use .dev_id, cleanups
> v4: Integrated more review comments from Ryan Mallon and Felipe Balbi:
>      Moved register include file to local include, code cleanups
> v3: Integrated review comments from Ryan Mallon and Felipe Balbi
> v2: Fixed whitespace issue
> ---
>   arch/arm/mach-at91/at91rm9200_devices.c  |    9 +
>   arch/arm/mach-at91/at91sam9261_devices.c |    9 +
>   drivers/i2c/busses/Kconfig               |   11 +-
>   drivers/i2c/busses/Makefile              |    1 +
>   drivers/i2c/busses/i2c-at91.c            |  493 ++++++++++++++++++++++++++++++
>   5 files changed, 516 insertions(+), 7 deletions(-)
>   create mode 100644 drivers/i2c/busses/i2c-at91.c
>
> diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
> index e6b7d05..2977a2d 100644
> --- a/arch/arm/mach-at91/at91rm9200_devices.c
> +++ b/arch/arm/mach-at91/at91rm9200_devices.c
> @@ -494,9 +494,18 @@ static struct resource twi_resources[] = {
>   	},
>   };
>
> +static const struct platform_device_id twi_ip_type = {
> +	/*
> +	 * driver_data is 1 for RM9200 compatible ip, see enum twi_ip_id in
> +	 * drivers/i2c/busses/i2c-at91.c
> +	 */
> +	.driver_data	= 1,
> +};
> +
>   static struct platform_device at91rm9200_twi_device = {
>   	.name		= "at91_i2c",
>   	.id		= -1,
> +	.id_entry	= &twi_ip_type,
>   	.resource	= twi_resources,
>   	.num_resources	= ARRAY_SIZE(twi_resources),
>   };
> diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
> index 9295e90..27fddc1 100644
> --- a/arch/arm/mach-at91/at91sam9261_devices.c
> +++ b/arch/arm/mach-at91/at91sam9261_devices.c
> @@ -283,9 +283,18 @@ static struct i2c_gpio_platform_data pdata = {
>   	.udelay			= 2,		/* ~100 kHz */
>   };
>
> +static const struct platform_device_id twi_ip_type = {
> +	/*
> +	 * driver_data is 2 for SAM9261 compatible ip, see enum twi_ip_id in
> +	 * drivers/i2c/busses/i2c-at91.c
> +	 */
> +	.driver_data	= 2,
> +};
> +
>   static struct platform_device at91sam9261_twi_device = {
>   	.name			= "i2c-gpio",
>   	.id			= -1,
> +	.id_entry		= &twi_ip_type,
>   	.dev.platform_data	= &pdata,
>   };
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 7244c8b..6b74287 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -286,18 +286,15 @@ comment "I2C system bus drivers (mostly embedded / system-on-chip)"
>
>   config I2C_AT91
>   	tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
> -	depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
> +	depends on ARCH_AT91 && EXPERIMENTAL
>   	help
>   	  This supports the use of the I2C interface on Atmel AT91
>   	  processors.
>
> -	  This driver is BROKEN because the controller which it uses
> -	  will easily trigger RX overrun and TX underrun errors.  Using
> -	  low I2C clock rates may partially work around those issues
> -	  on some systems.  Another serious problem is that there is no
> -	  documented way to issue repeated START conditions, as needed
> +	  A serious problem is that there is no documented way to issue
> +	  repeated START conditions for more than two messages, as needed
>   	  to support combined I2C messages.  Use the i2c-gpio driver
> -	  unless your system can cope with those limitations.
> +	  unless your system can cope with this limitation.
>
>   config I2C_AU1550
>   	tristate "Au1550/Au1200/Au1300 SMBus interface"
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 4f46873..ce3c2be 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_I2C_HYDRA)		+= i2c-hydra.o
>   obj-$(CONFIG_I2C_POWERMAC)	+= i2c-powermac.o
>
>   # Embedded system I2C/SMBus host controller drivers
> +obj-$(CONFIG_I2C_AT91)		+= i2c-at91.o
>   obj-$(CONFIG_I2C_AU1550)	+= i2c-au1550.o
>   obj-$(CONFIG_I2C_BLACKFIN_TWI)	+= i2c-bfin-twi.o
>   obj-$(CONFIG_I2C_CPM)		+= i2c-cpm.o
> diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> new file mode 100644
> index 0000000..2b8b2c2
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-at91.c
> @@ -0,0 +1,493 @@
> +/*
> + *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
> + *
> + *  Copyright (C) 2011 Weinmann Medical GmbH
> + *  Author: Nikolaus Voss <n.voss at weinmann.de>
> + *
> + *  Evolved from original work by:
> + *  Copyright (C) 2004 Rick Bronson
> + *  Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
> + *
> + *  Borrowed heavily from original work by:
> + *  Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#define TWI_CLK_HZ		100000			/* max 400 Kbits/s */
> +#define AT91_I2C_TIMEOUT	msecs_to_jiffies(100)	/* transfer timeout */
> +
> +/* AT91 TWI register definitions */
> +#define	AT91_TWI_CR		0x0000	/* Control Register */
> +#define	AT91_TWI_START		0x0001	/* Send a Start Condition */
> +#define	AT91_TWI_STOP		0x0002	/* Send a Stop Condition */
> +#define	AT91_TWI_MSEN		0x0004	/* Master Transfer Enable */
> +#define	AT91_TWI_SVDIS		0x0020	/* Slave Transfer Disable */
> +#define	AT91_TWI_SWRST		0x0080	/* Software Reset */
> +
> +#define	AT91_TWI_MMR		0x0004	/* Master Mode Register */
> +#define	AT91_TWI_IADRSZ_1	0x0100	/* Internal Device Address Size */
> +#define	AT91_TWI_MREAD		0x1000	/* Master Read Direction */
> +
> +#define	AT91_TWI_IADR		0x000c	/* Internal Address Register */
> +
> +#define	AT91_TWI_CWGR		0x0010	/* Clock Waveform Generator Reg */
> +
> +#define	AT91_TWI_SR		0x0020	/* Status Register */
> +#define	AT91_TWI_TXCOMP		0x0001	/* Transmission Complete */
> +#define	AT91_TWI_RXRDY		0x0002	/* Receive Holding Register Ready */
> +#define	AT91_TWI_TXRDY		0x0004	/* Transmit Holding Register Ready */
> +
> +#define	AT91_TWI_OVRE		0x0040	/* Overrun Error */
> +#define	AT91_TWI_UNRE		0x0080	/* Underrun Error */
> +#define	AT91_TWI_NACK		0x0100	/* Not Acknowledged */
> +
> +#define	AT91_TWI_IER		0x0024	/* Interrupt Enable Register */
> +#define	AT91_TWI_IDR		0x0028	/* Interrupt Disable Register */
> +#define	AT91_TWI_IMR		0x002c	/* Interrupt Mask Register */
> +#define	AT91_TWI_RHR		0x0030	/* Receive Holding Register */
> +#define	AT91_TWI_THR		0x0034	/* Transmit Holding Register */
> +
> +enum twi_ip_id {
> +	DEFAULT		= 0, /* default ip, no known limitations */
> +	RM9200		= 1,
> +	SAM9261		= 2,
> +};
> +
> +struct at91_twi_dev {
> +	struct device		*dev;
> +	void __iomem		*base;
> +	struct completion	cmd_complete;
> +	struct clk		*clk;
> +	u8			*buf;
> +	size_t			buf_len;
> +	struct i2c_msg		*msg;
> +	int			irq;
> +	unsigned		transfer_status;
> +	struct i2c_adapter	adapter;
> +	enum twi_ip_id		ip_id;
> +	unsigned		twi_cwgr_reg;
> +};
> +
> +static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
> +{
> +	return readl_relaxed(dev->base + reg);
> +}
> +
> +static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
> +{
> +	writel_relaxed(val, dev->base + reg);
> +}
> +
> +static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
> +{
> +	at91_twi_write(dev, AT91_TWI_IDR,
> +		       AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
> +}
> +
> +static void at91_init_twi_bus(struct at91_twi_dev *dev)
> +{
> +	at91_disable_twi_interrupts(dev);
> +	at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
> +	at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
> +	at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
> +	at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
> +}
> +
> +/*
> + * Calculate symmetric clock as stated in datasheet:
> + * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
> + */
> +static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
> +{
> +	int ckdiv, cdiv, div;
> +	int offset = 4;
> +	int max_ckdiv = 7;
> +
> +	if (dev->ip_id == RM9200) {
> +		offset = 3;
> +		max_ckdiv = 5;
> +	} else if (dev->ip_id == SAM9261) {
> +		offset = 4;
> +		max_ckdiv = 5;
> +	}
> +
> +	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
> +				       2 * twi_clk) - offset);
> +	ckdiv = fls(div >> 8);
> +	cdiv = div >> ckdiv;
> +
> +	if (ckdiv > max_ckdiv) {
> +		dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
> +			 ckdiv, max_ckdiv);
> +		ckdiv = max_ckdiv;
> +		cdiv = 255;
> +	}
> +
> +	dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
> +	dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
> +}
> +
> +static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
> +{
> +	if (dev->buf_len <= 0)
> +		return;
> +
> +	at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
> +
> +	/* send stop when last byte has been written */
> +	if (--dev->buf_len == 0)
> +		at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
> +
> +	dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
> +
> +	++dev->buf;
> +}
> +
> +static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
> +{
> +	if (dev->buf_len <= 0)
> +		return;
> +
> +	*dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
> +	--dev->buf_len;
> +
> +	/* handle I2C_SMBUS_BLOCK_DATA */
> +	if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
> +		dev->msg->flags &= ~I2C_M_RECV_LEN;
> +		dev->buf_len += *dev->buf;
> +		dev->msg->len = dev->buf_len + 1;
> +		dev_dbg(dev->dev, "received block length %d\n", dev->buf_len);
> +	}
> +
> +	/* send stop if second but last byte has been read */
> +	if (dev->buf_len == 1)
> +		at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
> +
> +	dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
> +
> +	++dev->buf;
> +}
> +
> +static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
> +{
> +	struct at91_twi_dev *dev = dev_id;
> +	const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
> +	const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
> +
> +	if (!irqstatus)
> +		return IRQ_NONE;
> +	else if (irqstatus & AT91_TWI_RXRDY)
> +		at91_twi_read_next_byte(dev);
> +	else if (irqstatus & AT91_TWI_TXRDY)
> +		at91_twi_write_next_byte(dev);
> +
> +	/* catch error flags */
> +	dev->transfer_status |= status;
> +
> +	if (irqstatus & AT91_TWI_TXCOMP) {
> +		at91_disable_twi_interrupts(dev);
> +		complete(&dev->cmd_complete);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int at91_do_twi_transfer(struct at91_twi_dev *dev)
> +{
> +	int ret;
> +
> +	dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
> +		(dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
> +
> +	INIT_COMPLETION(dev->cmd_complete);
> +	dev->transfer_status = 0;
> +	if (dev->msg->flags & I2C_M_RD) {
> +		unsigned start_flags = AT91_TWI_START;
> +
> +		if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
> +			dev_err(dev->dev, "RXRDY still set!");
> +			at91_twi_read(dev, AT91_TWI_RHR);
> +		}
> +
> +		/* if only one byte is to be read, immediately stop transfer */
> +		if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
> +			start_flags |= AT91_TWI_STOP;
> +		at91_twi_write(dev, AT91_TWI_CR, start_flags);
> +		at91_twi_write(dev, AT91_TWI_IER,
> +			       AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
> +	} else {
> +		at91_twi_write_next_byte(dev);
> +		at91_twi_write(dev, AT91_TWI_IER,
> +			       AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
> +	}
> +
> +	ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
> +							dev->adapter.timeout);
> +	if (ret == 0) {
> +		dev_err(dev->dev, "controller timed out\n");
> +		at91_init_twi_bus(dev);
> +		return -ETIMEDOUT;
> +	}
> +	if (dev->transfer_status & AT91_TWI_NACK) {
> +		dev_dbg(dev->dev, "received nack\n");
> +		return -EREMOTEIO;
> +	}
> +	if (dev->transfer_status & AT91_TWI_OVRE) {
> +		dev_err(dev->dev, "overrun while reading\n");
> +		return -EIO;
> +	}
> +	if (dev->transfer_status & AT91_TWI_UNRE && dev->ip_id == RM9200) {
> +		dev_err(dev->dev, "underrun while writing\n");
> +		return -EIO;
> +	}
> +	dev_dbg(dev->dev, "transfer complete\n");
> +
> +	return 0;
> +}
> +
> +static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
> +{
> +	struct at91_twi_dev *dev = i2c_get_adapdata(adap);
> +	int ret;
> +	unsigned int_addr_flag = 0;
> +	struct i2c_msg *m_start = msg;
> +
> +	dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
> +
> +	/*
> +	 * The hardware can handle at most two messages concatenated by a
> +	 * repeated start via it's internal address feature.
> +	 */
> +	if (num > 2) {
> +		dev_err(dev->dev,
> +			"cannot handle more than two concatenated messages.\n");
> +		return 0;
> +	} else if (num == 2) {
> +		int internal_address = 0;
> +		int i;
> +
> +		if (msg->flags & I2C_M_RD) {
> +			dev_err(dev->dev, "first transfer must be write.\n");
> +			return -EINVAL;
> +		}
> +		if (msg->len > 3) {
> +			dev_err(dev->dev, "first message size must be <= 3.\n");
> +			return -EINVAL;
> +		}
> +
> +		/* 1st msg is put into the internal address, start with 2nd */
> +		m_start = &msg[1];
> +		for (i = 0; i < msg->len; ++i) {
> +			const unsigned addr = msg->buf[msg->len - 1 - i];
> +
> +			internal_address |= addr << (8 * i);
> +			int_addr_flag += AT91_TWI_IADRSZ_1;
> +		}
> +		at91_twi_write(dev, AT91_TWI_IADR, internal_address);
> +	}
> +
> +	at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
> +		       | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
> +
> +	dev->buf_len = m_start->len;
> +	dev->buf = m_start->buf;
> +	dev->msg = m_start;
> +
> +	ret = at91_do_twi_transfer(dev);
> +
> +	return (ret < 0) ? ret : num;
> +}
> +
> +static u32 at91_twi_func(struct i2c_adapter *adapter)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
> +		| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
> +}
> +
> +static struct i2c_algorithm at91_twi_algorithm = {
> +	.master_xfer	= at91_twi_xfer,
> +	.functionality	= at91_twi_func,
> +};
> +
> +static int __devinit at91_twi_probe(struct platform_device *pdev)
> +{
> +	struct at91_twi_dev *dev;
> +	struct resource *mem, *ioarea;
> +	int irq, rc;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!mem)
> +		return -ENODEV;
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return irq;
> +
> +	ioarea = request_mem_region(mem->start, resource_size(mem), pdev->name);
> +	if (!ioarea)
> +		return -EBUSY;
> +
> +	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> +	if (!dev) {
> +		rc = -ENOMEM;
> +		goto err_release_region;
> +	}
> +
> +	if (pdev->id_entry)
> +		dev->ip_id = pdev->id_entry->driver_data;
> +
> +	init_completion(&dev->cmd_complete);
> +
> +	dev->dev = &pdev->dev;
> +	dev->irq = irq;
> +	platform_set_drvdata(pdev, dev);
> +
> +	dev->clk = clk_get(dev->dev, NULL);
> +	if (IS_ERR(dev->clk)) {
> +		dev_err(dev->dev, "no clock defined\n");
> +		rc = -ENODEV;
> +		goto err_free_mem;
> +	}
> +	clk_prepare(dev->clk);
> +	clk_enable(dev->clk);
> +
> +	dev->base = ioremap(mem->start, resource_size(mem));
> +	if (!dev->base) {
> +		rc = -EBUSY;
> +		goto err_mem_ioremap;
> +	}
> +
> +	at91_calc_twi_clock(dev, TWI_CLK_HZ);
> +	at91_init_twi_bus(dev);
> +
> +	rc = request_irq(dev->irq, atmel_twi_interrupt, 0,
> +			 dev_name(dev->dev), dev);
> +	if (rc) {
> +		dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
> +		goto err_unuse_clocks;
> +	}
> +
> +	snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
> +	i2c_set_adapdata(&dev->adapter, dev);
> +	dev->adapter.owner = THIS_MODULE;
> +	dev->adapter.class = I2C_CLASS_HWMON;
> +	dev->adapter.algo = &at91_twi_algorithm;
> +	dev->adapter.dev.parent = dev->dev;
> +	dev->adapter.nr = pdev->id;
> +	dev->adapter.timeout = AT91_I2C_TIMEOUT;
> +
> +	rc = i2c_add_numbered_adapter(&dev->adapter);
> +	if (rc) {
> +		dev_err(dev->dev, "Adapter %s registration failed\n",
> +			dev->adapter.name);
> +		goto err_free_irq;
> +	}
> +
> +	dev_info(dev->dev, "AT91 i2c bus driver.\n");
> +	return 0;
> +
> +err_free_irq:
> +	free_irq(dev->irq, dev);
> +err_unuse_clocks:
> +	iounmap(dev->base);
> +err_mem_ioremap:
> +	clk_disable(dev->clk);
> +	clk_unprepare(dev->clk);
> +	clk_put(dev->clk);
> +err_free_mem:
> +	kfree(dev);
> +err_release_region:
> +	release_mem_region(mem->start, resource_size(mem));
> +
> +	return rc;
> +}
> +
> +static int __devexit at91_twi_remove(struct platform_device *pdev)
> +{
> +	struct at91_twi_dev *dev = platform_get_drvdata(pdev);
> +	struct resource *mem;
> +	int rc;
> +
> +	rc = i2c_del_adapter(&dev->adapter);
> +	clk_disable(dev->clk);
> +	clk_unprepare(dev->clk);
> +	clk_put(dev->clk);
> +	free_irq(dev->irq, dev);
> +	iounmap(dev->base);
> +	kfree(dev);
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	release_mem_region(mem->start, resource_size(mem));
> +
> +	return rc;
> +}
> +
> +#ifdef CONFIG_PM
> +
> +static int at91_twi_runtime_suspend(struct device *dev)
> +{
> +	struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
> +
> +	clk_disable(twi_dev->clk);
> +
> +	return 0;
> +}
> +
> +static int at91_twi_runtime_resume(struct device *dev)
> +{
> +	struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
> +
> +	return clk_enable(twi_dev->clk);
> +}
> +
> +static const struct dev_pm_ops at91_twi_pm = {
> +	.runtime_suspend	= at91_twi_runtime_suspend,
> +	.runtime_resume		= at91_twi_runtime_resume,
> +};
> +
> +#define at91_twi_pm_ops (&at91_twi_pm)
> +#else
> +#define at91_twi_pm_ops NULL
> +#endif
> +
> +static struct platform_driver at91_twi_driver = {
> +	.probe		= at91_twi_probe,
> +	.remove		= __devexit_p(at91_twi_remove),
> +	.driver		= {
> +		.name	= "at91_i2c",
> +		.owner	= THIS_MODULE,
> +		.pm	= at91_twi_pm_ops,
> +	},
> +};
> +
> +static int __init at91_twi_init(void)
> +{
> +	return platform_driver_register(&at91_twi_driver);
> +}
> +
> +static void __exit at91_twi_exit(void)
> +{
> +	platform_driver_unregister(&at91_twi_driver);
> +}
> +
> +subsys_initcall(at91_twi_init);
> +module_exit(at91_twi_exit);
> +
> +MODULE_AUTHOR("Nikolaus Voss <n.voss at weinmann.de>");
> +MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:at91_i2c");
>



From ludovic.desroches at atmel.com  Mon Aug 27 06:24:38 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 27 Aug 2012 12:24:38 +0200
Subject: [PATCH v11 4/4] G45 TWI: remove open drain setting for twi
 function gpios
In-Reply-To: <6acdbd0f06cb9902efc510346564e10b07fa0b91.1345618760.git.n.voss@weinmann.de>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <6acdbd0f06cb9902efc510346564e10b07fa0b91.1345618760.git.n.voss@weinmann.de>
Message-ID: <503B4AE6.4090107@atmel.com>

Hi Nikolaus,

Le 11/08/2011 12:11 PM, Nikolaus Voss a ?crit :
> The G45 datasheets explicitly states that setting the open drain property
> on peripheral function gpios is not allowed. (How about other A91 chips?)
>


Did you remove open drain because you had some issues or because you had 
seen it into datasheet?

I tried with and without open drain. The behavior was the same. Looking 
to the G45 datasheet, I didn't see that the open drain property is not 
allowed on peripheral function gpios:

'The Multi Drive can be selected whether the I/O line
is controlled by the PIO controller or assigned to a peripheral function.'

The datasheet should have been updated or there is another place where 
it is mentioned that open drain property is not allowed in this case.


Regards

Ludovic

> Signed-off-by: Nikolaus Voss <n.voss at weinmann.de>
> ---
>   arch/arm/mach-at91/at91sam9g45_devices.c |    6 ------
>   1 file changed, 6 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index eec5eb6..2134663 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -686,18 +686,12 @@ void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, in
>   	/* pins used for TWI interface */
>   	if (i2c_id == 0) {
>   		at91_set_A_periph(AT91_PIN_PA20, 0);		/* TWD */
> -		at91_set_multi_drive(AT91_PIN_PA20, 1);
> -
>   		at91_set_A_periph(AT91_PIN_PA21, 0);		/* TWCK */
> -		at91_set_multi_drive(AT91_PIN_PA21, 1);
>
>   		platform_device_register(&at91sam9g45_twi0_device);
>   	} else {
>   		at91_set_A_periph(AT91_PIN_PB10, 0);		/* TWD */
> -		at91_set_multi_drive(AT91_PIN_PB10, 1);
> -
>   		at91_set_A_periph(AT91_PIN_PB11, 0);		/* TWCK */
> -		at91_set_multi_drive(AT91_PIN_PB11, 1);
>
>   		platform_device_register(&at91sam9g45_twi1_device);
>   	}
>



From wni at nvidia.com  Mon Aug 27 06:25:08 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:08 +0800
Subject: [PATCH 0/6] ARM: tegra: enable wlan for t20 and t30
Message-ID: <1346063114-30361-1-git-send-email-wni@nvidia.com>

Enable wlan for following tegra board:
Tegra30: Cardhu.
Tegra20: Seaboard, Ventana.

Wei Ni (6):
  ARM: tegra: set up wlan clocks for tegra dt
  brcmfmac: Handling the interrupt in ISR directly for non-OOB
  ARM: dt: t20 seaboard: turn on the power for wlan
  ARM: dt: t20 ventana: set pinmux and power for wlan
  ARM: dt: t30 cardhu: set pinmux and power for wlan
  ARM: tegra: enable wireless in defconfig

 arch/arm/boot/dts/tegra20-seaboard.dts             |    5 +++
 arch/arm/boot/dts/tegra20-ventana.dts              |   15 +++++++++
 arch/arm/boot/dts/tegra30-cardhu.dtsi              |   32 ++++++++++++++++++++
 arch/arm/configs/tegra_defconfig                   |    4 ++
 arch/arm/mach-tegra/board-dt-tegra20.c             |    4 ++
 arch/arm/mach-tegra/board-dt-tegra30.c             |    4 ++
 drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c   |    2 +
 drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c |    8 ++++-
 8 files changed, 73 insertions(+), 1 deletions(-)



From wni at nvidia.com  Mon Aug 27 06:25:09 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:09 +0800
Subject: [PATCH 1/6] ARM: tegra: set up wlan clocks for tegra dt
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-2-git-send-email-wni@nvidia.com>

Set up the wlan clock tree for Tegra20 and Tegra30.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 arch/arm/mach-tegra/board-dt-tegra20.c |    4 ++++
 arch/arm/mach-tegra/board-dt-tegra30.c |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index d9eeae6..5efc219 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -79,8 +79,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	{ "pll_a",      "pll_p_out1",   56448000,       true },
 	{ "pll_a_out0", "pll_a",        11289600,       true },
 	{ "cdev1",      NULL,           0,              true },
+	{ "blink",      "clk_32k",      32768,          true },
 	{ "i2s1",       "pll_a_out0",   11289600,       false},
 	{ "i2s2",       "pll_a_out0",   11289600,       false},
+	{ "sdmmc1",	"pll_p",	48000000,	false},
+	{ "sdmmc3",	"pll_p",	48000000,	false},
+	{ "sdmmc4",	"pll_p",	48000000,	false},
 	{ NULL,		NULL,		0,		0},
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 53bf60f..3277d1e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -61,11 +61,15 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	{ "pll_a_out0",	"pll_a",	11289600,	true },
 	{ "extern1",	"pll_a_out0",	0,		true },
 	{ "clk_out_1",	"extern1",	0,		true },
+	{ "blink",	"clk_32k",	32768,		true },
 	{ "i2s0",	"pll_a_out0",	11289600,	false},
 	{ "i2s1",	"pll_a_out0",	11289600,	false},
 	{ "i2s2",	"pll_a_out0",	11289600,	false},
 	{ "i2s3",	"pll_a_out0",	11289600,	false},
 	{ "i2s4",	"pll_a_out0",	11289600,	false},
+	{ "sdmmc1",	"pll_p",	48000000,	false},
+	{ "sdmmc3",	"pll_p",	48000000,	false},
+	{ "sdmmc4",	"pll_p",	48000000,	false},
 	{ NULL,		NULL,		0,		0},
 };
 
-- 
1.7.1



From wni at nvidia.com  Mon Aug 27 06:25:11 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:11 +0800
Subject: [PATCH 3/6] ARM: dt: t20 seaboard: turn on the power for wlan
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-4-git-send-email-wni@nvidia.com>

Enable the SDHCI1 controller. This is connected to the WiFi module.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 arch/arm/boot/dts/tegra20-seaboard.dts |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 92deb36..f783f31 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -590,6 +590,11 @@
 		status = "okay";
 	};
 
+	sdhci at c8000000 {
+		status = "okay";
+		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+	};
+
 	sdhci at c8000400 {
 		status = "okay";
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-- 
1.7.1



From wni at nvidia.com  Mon Aug 27 06:25:10 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:10 +0800
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly for
 non-OOB
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-3-git-send-email-wni@nvidia.com>

In case of inband interrupts, if we handle the interrupt in dpc thread,
two level of thread switching takes place to process wifi interrupts.
One in SDHCI driver and the other in Wifi driver. This may cause the system
instability.
Because the SDHCI calls sdio_irq_thread() to handle the irq, this thread locks
mmc host and calls wifi handler. It expects WiFi handler to be quick and
enables sdio interrupt from card at end. If wifi handler defers this work for
a different thread, sdio_irq_thread() will be stuck on next wifi interrupt
since mmc lock is not freed.

Handling the interrupt in ISR directly will prevent thread context switching in
wifi driver. It can fix the instability problems.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c   |    2 ++
 drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c |    8 +++++++-
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
index 8e7e692..5cf6c3b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
@@ -121,7 +121,9 @@ static void brcmf_sdio_irqhandler(struct sdio_func *func)
 
 	brcmf_dbg(INTR, "ib intr triggered\n");
 
+	sdio_release_host(sdiodev->func[1]);
 	brcmf_sdbrcm_isr(sdiodev->bus);
+	sdio_claim_host(sdiodev->func[1]);
 }
 
 /* dummy handler for SDIO function 2 interrupt */
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
index 472f2ef..4576d59 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
@@ -2347,7 +2347,7 @@ static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
 	uint framecnt = 0;	/* Temporary counter of tx/rx frames */
 	bool rxdone = true;	/* Flag for no more read data */
 	bool resched = false;	/* Flag indicating resched wanted */
-	int err;
+	int err = 0;
 
 	brcmf_dbg(TRACE, "Enter\n");
 
@@ -3786,11 +3786,17 @@ void brcmf_sdbrcm_isr(void *arg)
 	if (!bus->intr)
 		brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
 
+
+#ifndef CONFIG_BRCMFMAC_SDIO_OOB
+	while (brcmf_sdbrcm_dpc(bus))
+		;
+#else
 	bus->dpc_sched = true;
 	if (bus->dpc_tsk) {
 		brcmf_sdbrcm_adddpctsk(bus);
 		complete(&bus->dpc_wait);
 	}
+#endif
 }
 
 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
-- 
1.7.1



From wni at nvidia.com  Mon Aug 27 06:25:12 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:12 +0800
Subject: [PATCH 4/6] ARM: dt: t20 ventana: set pinmux and power for wlan
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-5-git-send-email-wni@nvidia.com>

Configure pinmux as required for WiFi.
Enable the SDHCI1 controller, which is connectted to the WiFi module.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 arch/arm/boot/dts/tegra20-ventana.dts |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 4ec6b4c..3cbe54c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -237,6 +237,16 @@
 					"ld23_22";
 				nvidia,pull = <1>;
 			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <0>;
+				nvidia,schmitt = <1>;
+				nvidia,low-power-mode = <3>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <3>;
+				nvidia,slew-rate-falling = <3>;
+			};
 		};
 	};
 
@@ -454,6 +464,11 @@
 		status = "okay";
 	};
 
+	sdhci at c8000000 {
+		status = "okay";
+		power-gpios = <&gpio 86 0>; /* gpio PK6 */
+	};
+
 	sdhci at c8000400 {
 		status = "okay";
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-- 
1.7.1



From wni at nvidia.com  Mon Aug 27 06:25:13 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:13 +0800
Subject: [PATCH 5/6] ARM: dt: t30 cardhu: set pinmux and power for wlan
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-6-git-send-email-wni@nvidia.com>

Configure pinmux as required for WiFi.
Enable the SDHCI1 controller. This is connectted to the WiFi module.
For now, always enable the regulator that provides power to the Wifi module.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 arch/arm/boot/dts/tegra30-cardhu.dtsi |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 4794693..ed9b530 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -52,6 +52,22 @@
 				nvidia,pull = <2>;
 				nvidia,tristate = <0>;
 			};
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc3_cmd_pa7 {
+				nvidia,pins =	"sdmmc3_cmd_pa7",
+						"sdmmc3_dat0_pb7",
+						"sdmmc3_dat1_pb6",
+						"sdmmc3_dat2_pb5",
+						"sdmmc3_dat3_pb4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
 			sdmmc4_clk_pcc4 {
 				nvidia,pins =	"sdmmc4_clk_pcc4",
 						"sdmmc4_rst_n_pcc3";
@@ -81,6 +97,15 @@
 				nvidia,pull = <0>;
 				nvidia,tristate = <0>;
 			};
+			sdio3 {
+				nvidia,pins = "drive_sdio3";
+				nvidia,high-speed-mode = <0>;
+				nvidia,schmitt = <0>;
+				nvidia,pull-down-strength = <46>;
+				nvidia,pull-up-strength = <42>;
+				nvidia,slew-rate-rising = <1>;
+				nvidia,slew-rate-falling = <1>;
+			};
 		};
 	};
 
@@ -292,6 +317,11 @@
 		bus-width = <4>;
 	};
 
+	sdhci at 78000400 {
+		status = "okay";
+		power-gpios = <&gpio 28 0>; /* gpio PD4 */
+	};
+
 	sdhci at 78000600 {
 		status = "okay";
 		bus-width = <8>;
@@ -407,6 +437,8 @@
 			regulator-name = "vdd_com";
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+			regulator-boot-on;
 			enable-active-high;
 			gpio = <&gpio 24 0>; /* gpio PD0 */
 			vin-supply = <&sys_3v3_reg>;
-- 
1.7.1



From wni at nvidia.com  Mon Aug 27 06:25:14 2012
From: wni at nvidia.com (Wei Ni)
Date: Mon, 27 Aug 2012 18:25:14 +0800
Subject: [PATCH 6/6] ARM: tegra: enable wireless in defconfig
In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
Message-ID: <1346063114-30361-7-git-send-email-wni@nvidia.com>

New options enabled:
* WIRELESS: (dependency)
* CFG80211_WEXT: (dependency)
* WLAN: (dependency)
* BRCMFMAC: wlan driver, enable as module.

Signed-off-by: Wei Ni <wni at nvidia.com>
---
 arch/arm/configs/tegra_defconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index ef2c679..8fab9e0 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -73,7 +73,11 @@ CONFIG_BT_RFCOMM=y
 CONFIG_BT_BNEP=y
 CONFIG_BT_HIDP=y
 CONFIG_BT_HCIBTUSB=m
+CONFIG_WLAN=y
+CONFIG_BRCMFMAC=m
+CONFIG_WIRELESS=y
 CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
 CONFIG_MAC80211=y
 CONFIG_RFKILL=y
 CONFIG_RFKILL_INPUT=y
-- 
1.7.1



From omycle at gmail.com  Mon Aug 27 06:30:42 2012
From: omycle at gmail.com (Li Haifeng)
Date: Mon, 27 Aug 2012 18:30:42 +0800
Subject: For buddy system initialization, the holes between banks adjacent
 will be released to buddy allocator?
In-Reply-To: <20120827080913.GL18957@n2100.arm.linux.org.uk>
References: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>
 <CAFNq8R7fCyD5P4mAA8LGzcOvVynSJa8mOBDwrLOF9mVvo9q5VA@mail.gmail.com>
 <20120827080913.GL18957@n2100.arm.linux.org.uk>
Message-ID: <CAFNq8R6TgfdAbDDTQTyt6hncA+OHAy7SkNpzdGuABcAtaegTiw@mail.gmail.com>

2012/8/27 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> On Mon, Aug 27, 2012 at 10:42:40AM +0800, Li Haifeng wrote:
>> Just now, I tested it on my ARM development board.
>>
>> The holes between banks does be released to buddy allocator. And the
>> buddy system will allocate holes for thread, which will cause fault.
>> Is it right?
>
> Could you rephrase your question please?

The code below is to release free memory to buddy allocator, according
to node_bootmem_map.

The lines 180~181 get the low memory's range, and the range includes holes.
But while releasing the memory to buddy allocator, the code doesn't
prevent the holes from releasing to the buddy allocator. So, if the
holes are allocated to thread, fault will happen.

IMO, it is a bug. Is it right?

172 static unsigned long __init free_all_bootmem_core(bootmem_data_t *bdata)
173 {
174         struct page *page;
175         unsigned long start, end, pages, count = 0;
176
177         if (!bdata->node_bootmem_map)
178                 return 0;
179
180         start = bdata->node_min_pfn;
181         end = bdata->node_low_pfn;
182
183         bdebug("nid=%td start=%lx end=%lx\n",
184                 bdata - bootmem_node_data, start, end);
185
186         while (start < end) {
187                 unsigned long *map, idx, vec;
188
189                 map = bdata->node_bootmem_map;
190                 idx = start - bdata->node_min_pfn;
191                 vec = ~map[idx / BITS_PER_LONG];
192                 /*
193                  * If we have a properly aligned and fully unreserved
194                  * BITS_PER_LONG block of pages in front of us, free
195                  * it in one go.
196                  */
197                 if (IS_ALIGNED(start, BITS_PER_LONG) && vec == ~0UL) {
198                         int order = ilog2(BITS_PER_LONG);
199
200                         __free_pages_bootmem(pfn_to_page(start), order);
201                         count += BITS_PER_LONG;
202                         start += BITS_PER_LONG;
203                 } else {
204                         unsigned long off = 0;
205
206                         while (vec && off < BITS_PER_LONG) {
207                                 if (vec & 1) {
208                                         page = pfn_to_page(start + off);
209                                         __free_pages_bootmem(page, 0);
210                                         count++;
211                                 }
212                                 vec >>= 1;
213                                 off++;
214                         }
215                         start = ALIGN(start + 1, BITS_PER_LONG);
216                 }
217         }
218
219         page = virt_to_page(bdata->node_bootmem_map);
220         pages = bdata->node_low_pfn - bdata->node_min_pfn;
221         pages = bootmem_bootmap_pages(pages);
222         count += pages;
223         while (pages--)
224                 __free_pages_bootmem(page++, 0);
225
226         bdebug("nid=%td released=%lx\n", bdata - bootmem_node_data, count);
227
228         return count;
229 }


From afzal at ti.com  Mon Aug 27 06:37:42 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 10:37:42 +0000
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <50359C64.40603@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
 <50359C64.40603@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA63D@DBDE01.ent.ti.com>

Hi Jon,

On Thu, Aug 23, 2012 at 08:28:44, Hunter, Jon wrote:
> On 08/21/2012 05:45 AM, Afzal Mohammed wrote:

> > +/* can the cycles be avoided ? */
> 
> What is the above comment referring too?

This was added in the initial stages and refers to the usage of
cycles in struct gpmc_device_timings. I wanted to avoid usage
of cycles, but it seems it is required logically as well. This
was mentioned as a note for future to find out whether at any
future point of time this can be removed.

> > +/* Device timings in picoseconds */
> 
> Why pico seconds and not nanoseconds? I understand you may need to
> temporarily convert to pico-secs for rounding, but when providing timing
> it seems nano-secs is more suitable.

For more accuracy, if you see some of the tusb6010 calculation
are in picoseconds, this can be true for any device although
only tusb does so. If we hold on to picoseconds till the last
moment, value would be more accurate. For eg. 300 ps has to be
used in the case of tusb, and with ns, it can't be accounted for

> I am a little concerned about the above timings structure. For example,
> if I am adding support for a new devices it is not clear ...
> 
> 1. Which are required
> 2. Which are applicable for async, sync, address-data multiplexed etc.
> 3. Exactly how these relate to the fields in the gpmc registers.

Please see at the end

> 
> I understand that this is based upon how timings for onenand and tusb
> are being calculated today, but I am not sure that this is the way to go
> for all devices. Personally, I would like to see us get away from how
> those devices are calculating timings for any new device.

You cannot do away with many of the those, as logically they
are right. Eg. read data should be available at access time,
assuming a zero data hold time, we can very well derive an
expression as,

read de-assertion time (oe_off) = access time plus 1 gpmc clock,

and this is what the existing calculations do, and also the
generic routine. There could be other constraints, but this
certainly should be one (I do realize that oe_off could be
optimized to be less than access time, by relying on read
hold time, then again effect of it would be in similar way
for different peripherals, but let's forget about
optimization in the beginning)

> In general, I am concerned that we are abstracting the timings further
> from the actual register fields. For example, the timings parameter
> "t_ceasu" is described "address setup to CS valid" which is not
> incorrect but this value is really just programming the CSONTIME field
> and so why not call this cs_on?

Timing fields of struct gpmc_device_timings are selected such
that they should be bindable by DT. At least one of the peripheral
datasheet has these fields. If user knows timings in terms of
gpmc values, he can directly use struct gpmc_timings, but
then all the values should be updated in struct gpmc_timings.
User should not update some of the values in terms of
peripheral timings, others in terms of gpmc timings, that
would make things complex and does not seem the right way
to me.

cs_on and other gpmc aware timings could be binded by DT, not as
peripheral timing, but as gpmc timing.

Bindings for peripheral DT timings should be something that
can be obtained from peripheral datasheet, here accidentally
it is same as gpmc timings, but not most timings are this way.
Also there could be other constraints that can come for cs_on,
even though I have not come across any till now.

> 
> So although this may consolidate how the timings are calculated today, I
> am concerned it will be confusing to add timings for a new device. At
> least if I am calculating timings, I am taking the timing information
> for the device and translating that to the how I need to program the
> gpmc register fields.

If I am not wrong, GPMC IP has been present for around a
decade, and so far I have not come across any generic time
calculation method that can be applied to all peripherals.
Getting to work same peripheral for a different gpmc
frequency is another problem.

Here we are trying to generalize based on the understanding of
gpmc & peripheral timings, as well as by a kind of reverse
engineering without most of the hardware or datasheet. Think of
this as an attempt to create one, let it evolve and become a
robust one. If a new user want to add a peripheral, let him add
support, input timings are selected such that it is found in
peripheral datasheet, if that does not work, let him try
to add any new timing field or alter existing expression
as he deems to be proper and verify that it does not break
others. And I can help provided I am not heavily loaded
with other works.

And at least for initial users, they are expected to have
some grasp on how to calculate timings, such a user will
not be much worried about your 3 concerns above, anyway as
of now they need to have a good grasp on it.

Meanwhile I will try to document more.

Regards
Afzal


From adrian.yanes at aalto.fi  Mon Aug 27 06:40:37 2012
From: adrian.yanes at aalto.fi (Yanes Martinez Adrian)
Date: Mon, 27 Aug 2012 10:40:37 +0000
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <503B4919.6080306@atmel.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
Message-ID: <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>

Hi Ludovic,

>Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>eeprom, temperature sensor and rtc devices (and wolfson chip for
>sam9g20).

concerning the at91rm9200, what was the amount of bytes you transmitted?

Some months ago I performed some testing[1] with the previous version of
the patch and the main conclusion was that the absence of PDC in the
AT91RM9200 made this driver unusable in such platform.

Please double check this.

Thanks in advance,

Adrian.

1 - http://thread.gmane.org/gmane.linux.drivers.i2c/10367/focus=1287445

From nareshgbhat at gmail.com  Mon Aug 27 06:46:02 2012
From: nareshgbhat at gmail.com (Naresh Bhat)
Date: Mon, 27 Aug 2012 16:16:02 +0530
Subject: Boot v3.5 kernel on QEMU for vexpress-a15 architecture with cpu as
 cortex-a15
Message-ID: <CAJXQGfLUyP=J6=Asd8eM6wcHN90Vc52=wekM=16XoH_D_KXPbA@mail.gmail.com>

Hi All,

I want to boot kernel.org v3.5 image (zImage) using QEMU with machine
architecture as vexpress-a15 and cpu as cortex-a15 on my Fedora-17
desktop machine.  I have followed the below method but resulted
nothing.  Can anybody please point me in a right direction ?

1. Clone the Torvalds kernel
   # git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

2. Checkout to v3.5-rc7 branch
    # git branch linux-3.5-rc7 v3.5-rc7

3. Cross compile the kernel
    # make ARCH=arm CROSS_COMPILE=arm-cortex_a15-linux-gnueabi-
vexpress_defconfig
    # make ARCH=arm CROSS_COMPILE=arm-cortex_a15-linux-gnueabi- uImage modules

4. Grab Pawe?'s DTS tree: git://linux-arm.org/arm-dts.git

5. From your kernel tree, run:
    # ./script/dtc/dtc -O dtb -o rtsm_ve-cortex_a15x4.dtb
wherever_your_arm-dts_tree_is/fast_models/rtsm_ve-cortex_a15x4.dts
    # cat rtsm_ve-cortex_a15x2.dtb >>arch/arm/boot/zImage

6.  Try to boot using QEMU

# qemu-system-arm -kernel arch/arm/boot/zImage -dtb
./rtsm_ve-cortex_a15x4.dtb -m 512 -M vexpress-a15 -cpu cortex-a15
-append "console=ttyAMA0"
oss: Could not initialize DAC
oss: Failed to open `/dev/dsp'
oss: Reason: No such file or directory
oss: Could not initialize DAC
oss: Failed to open `/dev/dsp'
oss: Reason: No such file or directory
audio: Failed to create voice `lm4549.out'
.................
........................

I am just a beginner in QEMU.  Am I doing any steps wrong ?? can you
please suggest right method ? I will appreciate your help.

-- Thanks and Regards
"For things to change, we must change"
-Naresh Bhat


From linux at arm.linux.org.uk  Mon Aug 27 06:54:48 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 27 Aug 2012 11:54:48 +0100
Subject: For buddy system initialization, the holes between banks
 adjacent will be released to buddy allocator?
In-Reply-To: <CAFNq8R6TgfdAbDDTQTyt6hncA+OHAy7SkNpzdGuABcAtaegTiw@mail.gmail.com>
References: <CAFNq8R6kBonhW4Q+Zj_6GV7y88pcAUJ_MrYn1nYM9LHtMZqdvQ@mail.gmail.com>
 <CAFNq8R7fCyD5P4mAA8LGzcOvVynSJa8mOBDwrLOF9mVvo9q5VA@mail.gmail.com>
 <20120827080913.GL18957@n2100.arm.linux.org.uk>
 <CAFNq8R6TgfdAbDDTQTyt6hncA+OHAy7SkNpzdGuABcAtaegTiw@mail.gmail.com>
Message-ID: <20120827105448.GO18957@n2100.arm.linux.org.uk>

On Mon, Aug 27, 2012 at 06:30:42PM +0800, Li Haifeng wrote:
> 2012/8/27 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> > On Mon, Aug 27, 2012 at 10:42:40AM +0800, Li Haifeng wrote:
> >> Just now, I tested it on my ARM development board.
> >>
> >> The holes between banks does be released to buddy allocator. And the
> >> buddy system will allocate holes for thread, which will cause fault.
> >> Is it right?
> >
> > Could you rephrase your question please?
> 
> The code below is to release free memory to buddy allocator, according
> to node_bootmem_map.
> 
> The lines 180~181 get the low memory's range, and the range includes holes.
> But while releasing the memory to buddy allocator, the code doesn't
> prevent the holes from releasing to the buddy allocator. So, if the
> holes are allocated to thread, fault will happen.

The whole purpose _is_ to allow these pages to be re-used, rather than
being tied up uselessly in the map where they're not being used.


From nareshgbhat at gmail.com  Mon Aug 27 07:24:10 2012
From: nareshgbhat at gmail.com (Naresh Bhat)
Date: Mon, 27 Aug 2012 16:54:10 +0530
Subject: Boot v3.5 kernel on QEMU for vexpress-a15 architecture with cpu
 as cortex-a15
In-Reply-To: <CAJXQGfLUyP=J6=Asd8eM6wcHN90Vc52=wekM=16XoH_D_KXPbA@mail.gmail.com>
References: <CAJXQGfLUyP=J6=Asd8eM6wcHN90Vc52=wekM=16XoH_D_KXPbA@mail.gmail.com>
Message-ID: <CAJXQGfJSSsEh4sKnN5n=QSGGQN1j2STiJB3WF=h3evMQNycRWQ@mail.gmail.com>

Hi All,

I am able to boot the machine by using following command

# qemu-system-arm -kernel arch/arm/boot/zImage -dtb
./rtsm_ve-cortex_a15x4.dtb -m 512 -M vexpress-a15 -serial stdio
-append "console=ttyAMA0"

Thanks and Regards
-Naresh Bhat

On Mon, Aug 27, 2012 at 4:16 PM, Naresh Bhat <nareshgbhat at gmail.com> wrote:
> Hi All,
>
> I want to boot kernel.org v3.5 image (zImage) using QEMU with machine
> architecture as vexpress-a15 and cpu as cortex-a15 on my Fedora-17
> desktop machine.  I have followed the below method but resulted
> nothing.  Can anybody please point me in a right direction ?
>
> 1. Clone the Torvalds kernel
>    # git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>
> 2. Checkout to v3.5-rc7 branch
>     # git branch linux-3.5-rc7 v3.5-rc7
>
> 3. Cross compile the kernel
>     # make ARCH=arm CROSS_COMPILE=arm-cortex_a15-linux-gnueabi-
> vexpress_defconfig
>     # make ARCH=arm CROSS_COMPILE=arm-cortex_a15-linux-gnueabi- uImage modules
>
> 4. Grab Pawe?'s DTS tree: git://linux-arm.org/arm-dts.git
>
> 5. From your kernel tree, run:
>     # ./script/dtc/dtc -O dtb -o rtsm_ve-cortex_a15x4.dtb
> wherever_your_arm-dts_tree_is/fast_models/rtsm_ve-cortex_a15x4.dts
>     # cat rtsm_ve-cortex_a15x2.dtb >>arch/arm/boot/zImage
>
> 6.  Try to boot using QEMU
>
> # qemu-system-arm -kernel arch/arm/boot/zImage -dtb
> ./rtsm_ve-cortex_a15x4.dtb -m 512 -M vexpress-a15 -cpu cortex-a15
> -append "console=ttyAMA0"
> oss: Could not initialize DAC
> oss: Failed to open `/dev/dsp'
> oss: Reason: No such file or directory
> oss: Could not initialize DAC
> oss: Failed to open `/dev/dsp'
> oss: Reason: No such file or directory
> audio: Failed to create voice `lm4549.out'
> .................
> ........................
>
> I am just a beginner in QEMU.  Am I doing any steps wrong ?? can you
> please suggest right method ? I will appreciate your help.
>
> -- Thanks and Regards
> "For things to change, we must change"
> -Naresh Bhat


From afzal at ti.com  Mon Aug 27 07:46:02 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 11:46:02 +0000
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <20120824195446.GV11011@atomide.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
 <50359C64.40603@ti.com> <20120824195446.GV11011@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA684@DBDE01.ent.ti.com>

Hi Tony,

On Sat, Aug 25, 2012 at 01:24:47, Tony Lindgren wrote:

> Yes agreed. Also as some values make sense only in cycles, converting them
> back and forth to time is wrong. So at least some values should have an
> option to specify them in cycles directly, and then ignore any time based
> values.

Which values in struct gpmc_device_timings are you referring to ?

Values that need to have an option to specify in cycles has been provided
such an option, while not updating time based field value, you can
achieve what you mentioned above. But if you want that to be handled in
in generic routine, I will do so.

Regards
Afzal


From ludovic.desroches at atmel.com  Mon Aug 27 08:04:12 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 27 Aug 2012 14:04:12 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>
Message-ID: <503B623C.4030304@atmel.com>

Hi Adrian,

Le 08/27/2012 12:40 PM, Yanes Martinez Adrian a ?crit :
> Hi Ludovic,
>
>> Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>> eeprom, temperature sensor and rtc devices (and wolfson chip for
>> sam9g20).
>
> concerning the at91rm9200, what was the amount of bytes you transmitted?
>

I have only checked that I can communicate with i2c devices so the 
amount is very low (1-4 bytes).

> Some months ago I performed some testing[1] with the previous version of
> the patch and the main conclusion was that the absence of PDC in the
> AT91RM9200 made this driver unusable in such platform.
>

Does the new driver break something? Was it working with the old one?

There are some issues with which are not related to the driver but to 
the design of the IP. With old I2C versions, using GPIO I2C is recommended.

> Please double check this.
>
> Thanks in advance,
>
> Adrian.
>
> 1 - http://thread.gmane.org/gmane.linux.drivers.i2c/10367/focus=1287445
>

Regards

Ludovic


From zonque at gmail.com  Mon Aug 27 08:16:17 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 27 Aug 2012 14:16:17 +0200
Subject: [PATCH v6 00/10] OMAP-GPMC: generic time calc, prepare for driver
In-Reply-To: <cover.1345524670.git.afzal@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
Message-ID: <503B6511.4050909@gmail.com>

Hi Afzal,

On 21.08.2012 12:41, Afzal Mohammed wrote:
> This series provides a generic gpmc timing calculation routine. There
> were three peripherals (OneNAND, tusb6010, smc91x) using custom timing
> calculations, they are migrated to use the generic timing calculation.
> 
> Such a generic routine would help create a driver out of gpmc platform
> code, which would be peripheral agnostic and thus lead to DT finally.
> Input to generic timing calculation routine would be gpmc peripheral
> timings, output - translated timings that gpmc can understand. Later,
> to DT'ify, gpmc peripheral timings could be passed through DT. Input
> timings that has been used here are selected such that it represents
> those that are present in peripheral timing datasheets.

What I don't understand yet about this new approach is where the gpmc
client code should live in. In order to probe the drivers via DT, each
driver would need to call the gpmc support functions itself, right? Is
the plan to obsolete helper functions like gpmc_nand_init() and move
that functionality to the drivers?

I applied these patches locally and would like to help get the NAND
controller on my AX33xx DT-driven board going. Let me know if I can do
anything here.


Regards,
Daniel



From hvaibhav at ti.com  Mon Aug 27 08:31:52 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 27 Aug 2012 18:01:52 +0530
Subject: [PATCH 0/2] arm/dts: AM33XX: Add reg and interrupt property for all
 nodes
Message-ID: <1346070714-6122-1-git-send-email-hvaibhav@ti.com>

This series is trivial patch-series and should be considered as
preparation for the future where we supposed to get rid of
hwmod dependency.

1/2: Converts all hex numbers to lowercase, fixing inconsistency
2/2: Add reg and interrupt property  to all device/module nodes inside
     DTS files. 

Although currently hwmod overwrites resources, I have validated this
patch series by changing the omap_device layer to respect DT resources
and boot Tested on BeagleBone platform.
I will be submitting the changes for omap_device layer as well, still
needs to fix on certain things.

Vaibhav Hiremath (2):
  arm/dts: AM33XX: Convert all hex numbers to lower-case
  arm/dts: AM33XX: Specify reg and interrupt property for all nodes

 arch/arm/boot/dts/am335x-bone.dts |    2 +-
 arch/arm/boot/dts/am335x-evm.dts  |    2 +-
 arch/arm/boot/dts/am33xx.dtsi     |   62 +++++++++++++++++++++++++++++++------
 3 files changed, 54 insertions(+), 12 deletions(-)



From hvaibhav at ti.com  Mon Aug 27 08:31:53 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 27 Aug 2012 18:01:53 +0530
Subject: [PATCH 1/2] arm/dts: AM33XX: Convert all hex numbers to lower-case
In-Reply-To: <1346070714-6122-1-git-send-email-hvaibhav@ti.com>
References: <1346070714-6122-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1346070714-6122-2-git-send-email-hvaibhav@ti.com>

To make it consistent, convert all hex number presentation
to lower-case from all am33xx specific nodes.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/boot/dts/am335x-bone.dts |    2 +-
 arch/arm/boot/dts/am335x-evm.dts  |    2 +-
 arch/arm/boot/dts/am33xx.dtsi     |   20 ++++++++++----------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a7906cb..c64f7fa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -19,7 +19,7 @@
 	};
 
 	ocp {
-		uart1: serial at 44E09000 {
+		uart1: serial at 44e09000 {
 			status = "okay";
 		};
 	};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 5dd8a6b..8963f20 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -19,7 +19,7 @@
 	};
 
 	ocp {
-		uart1: serial at 44E09000 {
+		uart1: serial at 44e09000 {
 			status = "okay";
 		};
 	};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dde76f7..be43511 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -71,7 +71,7 @@
 			#interrupt-cells = <1>;
 		};
 
-		gpio2: gpio at 4804C000 {
+		gpio2: gpio at 4804c000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio2";
 			gpio-controller;
@@ -80,7 +80,7 @@
 			#interrupt-cells = <1>;
 		};
 
-		gpio3: gpio at 481AC000 {
+		gpio3: gpio at 481ac000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio3";
 			gpio-controller;
@@ -89,7 +89,7 @@
 			#interrupt-cells = <1>;
 		};
 
-		gpio4: gpio at 481AE000 {
+		gpio4: gpio at 481ae000 {
 			compatible = "ti,omap4-gpio";
 			ti,hwmods = "gpio4";
 			gpio-controller;
@@ -98,7 +98,7 @@
 			#interrupt-cells = <1>;
 		};
 
-		uart1: serial at 44E09000 {
+		uart1: serial at 44e09000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
@@ -119,28 +119,28 @@
 			status = "disabled";
 		};
 
-		uart4: serial at 481A6000 {
+		uart4: serial at 481a6000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 			status = "disabled";
 		};
 
-		uart5: serial at 481A8000 {
+		uart5: serial at 481a8000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 			status = "disabled";
 		};
 
-		uart6: serial at 481AA000 {
+		uart6: serial at 481aa000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 			status = "disabled";
 		};
 
-		i2c1: i2c at 44E0B000 {
+		i2c1: i2c at 44e0b000 {
 			compatible = "ti,omap4-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -148,7 +148,7 @@
 			status = "disabled";
 		};
 
-		i2c2: i2c at 4802A000 {
+		i2c2: i2c at 4802a000 {
 			compatible = "ti,omap4-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -156,7 +156,7 @@
 			status = "disabled";
 		};
 
-		i2c3: i2c at 4819C000 {
+		i2c3: i2c at 4819c000 {
 			compatible = "ti,omap4-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
1.7.0.4



From hvaibhav at ti.com  Mon Aug 27 08:31:54 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Mon, 27 Aug 2012 18:01:54 +0530
Subject: [PATCH 2/2] arm/dts: AM33XX: Specify reg and interrupt property for
 all nodes
In-Reply-To: <1346070714-6122-1-git-send-email-hvaibhav@ti.com>
References: <1346070714-6122-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1346070714-6122-3-git-send-email-hvaibhav@ti.com>

The device/node resources (like, IORESOURCE_MEM and IORESOURCE_IRQ)
are overwritten by hwmod resources, due to all known reasons but
that should not be the reason for not providing all the information
in the DTS blob. Ideally we should use DTS resource and use HWMOD
framework wherever required and for only specific things.

Newer platforms like, OMAP5 and AM33XX, we only support DT boot mode,
so this patch is preparation for the future where we supposed to get
rid of hwmod dependency anyway.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Benoit Cousson <b-cousson at ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi |   42 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index be43511..f0642e1 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,6 +69,9 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			reg = <0x44e07000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <96>;
 		};
 
 		gpio2: gpio at 4804c000 {
@@ -78,6 +81,9 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			reg = <0x4804c000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <98>;
 		};
 
 		gpio3: gpio at 481ac000 {
@@ -87,6 +93,9 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			reg = <0x481ac000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <32>;
 		};
 
 		gpio4: gpio at 481ae000 {
@@ -96,12 +105,18 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			reg = <0x481ae000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <62>;
 		};
 
 		uart1: serial at 44e09000 {
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			reg = <0x44e09000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <72>;
 			status = "disabled";
 		};
 
@@ -109,6 +124,9 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			reg = <0x48022000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <73>;
 			status = "disabled";
 		};
 
@@ -116,6 +134,9 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			reg = <0x48024000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <74>;
 			status = "disabled";
 		};
 
@@ -123,6 +144,9 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			reg = <0x481a6000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <44>;
 			status = "disabled";
 		};
 
@@ -130,6 +154,9 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
+			reg = <0x481a8000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <45>;
 			status = "disabled";
 		};
 
@@ -137,6 +164,9 @@
 			compatible = "ti,omap3-uart";
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
+			reg = <0x481aa000 0x2000>;
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <46>;
 			status = "disabled";
 		};
 
@@ -145,6 +175,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			reg = <0x44e0b000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <70>;
 			status = "disabled";
 		};
 
@@ -153,6 +186,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			reg = <0x4802a000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <71>;
 			status = "disabled";
 		};
 
@@ -161,12 +197,18 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			reg = <0x4819c000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <30>;
 			status = "disabled";
 		};
 
 		wdt2: wdt at 44e35000 {
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
+			reg = <0x44e35000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <91>;
 		};
 	};
 };
-- 
1.7.0.4



From afzal at ti.com  Mon Aug 27 08:38:35 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 12:38:35 +0000
Subject: [PATCH v6 00/10] OMAP-GPMC: generic time calc, prepare for driver
In-Reply-To: <503B6511.4050909@gmail.com>
References: <cover.1345524670.git.afzal@ti.com> <503B6511.4050909@gmail.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA713@DBDE01.ent.ti.com>

Hi Daniel,

On Mon, Aug 27, 2012 at 17:46:17, Daniel Mack wrote:

> > Such a generic routine would help create a driver out of gpmc platform
> > code, which would be peripheral agnostic and thus lead to DT finally.
> > Input to generic timing calculation routine would be gpmc peripheral
> > timings, output - translated timings that gpmc can understand. Later,
> > to DT'ify, gpmc peripheral timings could be passed through DT. Input
> > timings that has been used here are selected such that it represents
> > those that are present in peripheral timing datasheets.
> 
> What I don't understand yet about this new approach is where the gpmc
> client code should live in. In order to probe the drivers via DT, each
> driver would need to call the gpmc support functions itself, right? Is

By gpmc client code, if you are referring to helper functions in
mach-omap2/gpmc-*, if things go as per plan, with DT, they will go away
and gpmc driver would handle those based on the information from DT.

No change would be needed for client drivers like smc91x ethernet drivers,
but NAND driver may need some change to live with DT as it is tightly
coupled with GPMC.

> the plan to obsolete helper functions like gpmc_nand_init() and move
> that functionality to the drivers?

Yes, plan is to obsolete the functions like gpmc_nand_init, those tasks
would be handled by gpmc driver

> 
> I applied these patches locally and would like to help get the NAND
> controller on my AX33xx DT-driven board going. Let me know if I can do
> anything here.

Thanks for offering the help, will take liberty to ask you for help
when required. BTW, do you have any OMAP family boards ?

Regards
Afzal


From adrian.yanes at aalto.fi  Mon Aug 27 08:45:39 2012
From: adrian.yanes at aalto.fi (Yanes Martinez Adrian)
Date: Mon, 27 Aug 2012 12:45:39 +0000
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <503B623C.4030304@atmel.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>,
 <503B623C.4030304@atmel.com>
Message-ID: <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>

>Hi Adrian,

Le 08/27/2012 12:40 PM, Yanes Martinez Adrian a ?crit :
> Hi Ludovic,
>
>> Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>> eeprom, temperature sensor and rtc devices (and wolfson chip for
>> sam9g20).
>
> concerning the at91rm9200, what was the amount of bytes you transmitted?
>

> I have only checked that I can communicate with i2c devices so the
> amount is very low (1-4 bytes).

IIRC it was from >7 bytes when the issues appeared.

> Some months ago I performed some testing[1] with the previous version of
> the patch and the main conclusion was that the absence of PDC in the
> AT91RM9200 made this driver unusable in such platform.
>

> Does the new driver break something? Was it working with the old one?

The old driver never worked properly. GPIO I2C has been the only alternative
to use I2C over AT91RM9200. With the proposed driver I just encountered
the same issues mentioned in the previous thread (so at the end nothing
changed for the AT91RM9200, GPIO is the only way to go).

>There are some issues with which are not related to the driver but to
>the design of the IP. With old I2C versions, using GPIO I2C is recommended.

I think a warning should be included in the proposed driver for that reason.
Despite the driver will work in the mentioned SoCs, the users will encounter
issues in boards like AT91RM9200 and other legacy products.

Regards,

Adrian.

From knut.wohlrab at de.bosch.com  Mon Aug 27 09:18:41 2012
From: knut.wohlrab at de.bosch.com (Knut Wohlrab)
Date: Mon, 27 Aug 2012 15:18:41 +0200
Subject: [PATCH] SPI: IMX5/6: Set inactive state of SPI clock (SCLK CTL)
 according to SPI clock polarity
Message-ID: <503B73B1.9010801@de.bosch.com>

For our SPI device we need a SPI clock with active low polarity and a a 
high inactive state.

We add the setting of the inactive state ECSPIx_CONFIGREG:SCLK CTL 
according to the clock polarity ECSPIx_CONFIGREG:SCLK POL:

Device tree _without_ "spi-cpol" = 0 = clock active high polarity = 
inactive state low
Device tree with "spi-cpol" = 1 = clock active low polarity = inactive 
state high

Are there real world examples for a need of an individual setting of 
clock polarity/inactive state?


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From N.Voss at weinmann.de  Mon Aug 27 09:22:17 2012
From: N.Voss at weinmann.de (Voss, Nikolaus)
Date: Mon, 27 Aug 2012 15:22:17 +0200
Subject: [PATCH v11 4/4] G45 TWI: remove open drain setting for twi
 function gpios
In-Reply-To: <503B4AE6.4090107@atmel.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <6acdbd0f06cb9902efc510346564e10b07fa0b91.1345618760.git.n.voss@weinmann.de>
 <503B4AE6.4090107@atmel.com>
Message-ID: <EF2E73589CA71846A15D0B2CDF79505D090EC3D6E4@wm021.weinmann.com>

Hi Ludovic,

ludovic.desroches wrote on Monday, August 27, 2012 12:25 PM:
> Le 11/08/2011 12:11 PM, Nikolaus Voss a ?crit :
>> The G45 datasheets explicitly states that setting the open drain property
>> on peripheral function gpios is not allowed. (How about other A91 chips?)
>
> Did you remove open drain because you had some issues or because you
> had  seen it into datasheet?
> 
> I tried with and without open drain. The behavior was the same. Looking
> to the G45 datasheet, I didn't see that the open drain property is not
> allowed on peripheral function gpios:
> 
> 'The Multi Drive can be selected whether the I/O line
> is controlled by the PIO controller or assigned to a peripheral function.'
> 
> The datasheet should have been updated or there is another place where
> it is mentioned that open drain property is not allowed in this case.

well, it didn't work on my G45. I found the following note in the
TWI chapter 31.6.1 of the G45 datasheet:
"The user must not program TWD and TWCK as open-drain.
It is already done by the hardware."

After removing the open-drain setting, it worked.

Regards,
Nikolaus




From ludovic.desroches at atmel.com  Mon Aug 27 09:27:48 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 27 Aug 2012 15:27:48 +0200
Subject: [PATCH v11 4/4] G45 TWI: remove open drain setting for twi
 function gpios
In-Reply-To: <EF2E73589CA71846A15D0B2CDF79505D090EC3D6E4@wm021.weinmann.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <6acdbd0f06cb9902efc510346564e10b07fa0b91.1345618760.git.n.voss@weinmann.de>
 <503B4AE6.4090107@atmel.com>
 <EF2E73589CA71846A15D0B2CDF79505D090EC3D6E4@wm021.weinmann.com>
Message-ID: <503B75D4.2030803@atmel.com>

Le 08/27/2012 03:22 PM, Voss, Nikolaus a ?crit :
> Hi Ludovic,
>
> ludovic.desroches wrote on Monday, August 27, 2012 12:25 PM:
>> Le 11/08/2011 12:11 PM, Nikolaus Voss a ?crit :
>>> The G45 datasheets explicitly states that setting the open drain property
>>> on peripheral function gpios is not allowed. (How about other A91 chips?)
>>
>> Did you remove open drain because you had some issues or because you
>> had  seen it into datasheet?
>>
>> I tried with and without open drain. The behavior was the same. Looking
>> to the G45 datasheet, I didn't see that the open drain property is not
>> allowed on peripheral function gpios:
>>
>> 'The Multi Drive can be selected whether the I/O line
>> is controlled by the PIO controller or assigned to a peripheral function.'
>>
>> The datasheet should have been updated or there is another place where
>> it is mentioned that open drain property is not allowed in this case.
>
> well, it didn't work on my G45. I found the following note in the
> TWI chapter 31.6.1 of the G45 datasheet:
> "The user must not program TWD and TWCK as open-drain.
> It is already done by the hardware."

Ok so it seems there is a contradiction. I'll try to inquire about this 
point.

Regards

Ludovic

>
> After removing the open-drain setting, it worked.
>
> Regards,
> Nikolaus
>
>
>
>



From zonque at gmail.com  Mon Aug 27 09:30:32 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 27 Aug 2012 15:30:32 +0200
Subject: [PATCH v6 00/10] OMAP-GPMC: generic time calc, prepare for driver
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9BA713@DBDE01.ent.ti.com>
References: <cover.1345524670.git.afzal@ti.com> <503B6511.4050909@gmail.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9BA713@DBDE01.ent.ti.com>
Message-ID: <503B7678.90308@gmail.com>

On 27.08.2012 14:38, Mohammed, Afzal wrote:
> On Mon, Aug 27, 2012 at 17:46:17, Daniel Mack wrote:
> 
>>> Such a generic routine would help create a driver out of gpmc platform
>>> code, which would be peripheral agnostic and thus lead to DT finally.
>>> Input to generic timing calculation routine would be gpmc peripheral
>>> timings, output - translated timings that gpmc can understand. Later,
>>> to DT'ify, gpmc peripheral timings could be passed through DT. Input
>>> timings that has been used here are selected such that it represents
>>> those that are present in peripheral timing datasheets.
>>
>> What I don't understand yet about this new approach is where the gpmc
>> client code should live in. In order to probe the drivers via DT, each
>> driver would need to call the gpmc support functions itself, right? Is
> 
> By gpmc client code, if you are referring to helper functions in
> mach-omap2/gpmc-*, if things go as per plan, with DT, they will go away
> and gpmc driver would handle those based on the information from DT.

So the GPMC driver is the one that is matched from DT, and the NAND
driver will the be instanciated from the (generic) GPMC driver?

> No change would be needed for client drivers like smc91x ethernet drivers,
> but NAND driver may need some change to live with DT as it is tightly
> coupled with GPMC.

NAND drivers also typically parse partition entries that are children of
the DT node the are owning.

>> the plan to obsolete helper functions like gpmc_nand_init() and move
>> that functionality to the drivers?
> 
> Yes, plan is to obsolete the functions like gpmc_nand_init, those tasks
> would be handled by gpmc driver
> 
>>
>> I applied these patches locally and would like to help get the NAND
>> controller on my AX33xx DT-driven board going. Let me know if I can do
>> anything here.
> 
> Thanks for offering the help, will take liberty to ask you for help
> when required. BTW, do you have any OMAP family boards ?

I do have a beaglboard xM, but the board I'm currently working with is a
custom one based on an AM33xx.


Thanks,
Daniel



From N.Voss at weinmann.de  Mon Aug 27 09:32:11 2012
From: N.Voss at weinmann.de (Voss, Nikolaus)
Date: Mon, 27 Aug 2012 15:32:11 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>,
 <503B623C.4030304@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>
Message-ID: <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>

Hi Adian,

Yanes Martinez Adrian wrote on Monday, August 27, 2012 2:46 PM:
> Le 08/27/2012 12:40 PM, Yanes Martinez Adrian a ?crit :
>> Hi Ludovic,
>>
>>> Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>>> eeprom, temperature sensor and rtc devices (and wolfson chip for
>>> sam9g20).
>>
>> concerning the at91rm9200, what was the amount of bytes you
> transmitted?
>>
> 
>> I have only checked that I can communicate with i2c devices so the
>> amount is very low (1-4 bytes).
> 
> IIRC it was from >7 bytes when the issues appeared.
> 
>> Some months ago I performed some testing[1] with the previous version of
>> the patch and the main conclusion was that the absence of PDC in the
>> AT91RM9200 made this driver unusable in such platform.

I didn't get your last post  in that thread. In my opinion RM9200 should really
be excluded from being configured with this driver, what's your opinion
Ludovic?

Regards,
Niko



From haojian.zhuang at gmail.com  Mon Aug 27 09:43:10 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 27 Aug 2012 21:43:10 +0800
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <20120827082914.GN18957@n2100.arm.linux.org.uk>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
 <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
 <20120827082914.GN18957@n2100.arm.linux.org.uk>
Message-ID: <CAN1soZw4Qk5qSyuyMko9SZWu3u3_7OPA2yNVYz6C1WQWVimbvg@mail.gmail.com>

On Mon, Aug 27, 2012 at 4:29 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Aug 27, 2012 at 04:23:31PM +0800, zhangfei gao wrote:
>> On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
>> <haojian.zhuang at gmail.com> wrote:
>> > Let me summerize it. First, user space address is mapped. Then,
>> > flushing user space
>> > address is triggered. It's a workaround of fixing non-existed virtual
>> > address without fixing
>> > vmap() or any other solution. It's just a quick fix.
>> >
>> > Zhangfei,
>> > I doubt that the issue may be caused by missing memory barrier.
>> > Flushing is using
>> > coprocessor instructions. It's a little different.
>>
>> Is there any limitation that dmac_map_area & dmac_flush_range
>> supporting addr mapped from user space?
>
> They DEFINITELY DO NOT SUPPORT FLUSHING USER SPACE.

I agree that those API are defined to support kernel space address only.
But the implementation is only flushing address by assembly code.

If we don't care the original goal of API, the problem should be caused
by address mapping isn't set up yet. I doubt that the first step isn't fully
finished. Since the second step is using coprocessor instruction, that's
a shortcut. If we add delay such as memory barrier, the first step can
be really finished before the second step running.


From ben.dooks at codethink.co.uk  Mon Aug 27 09:43:31 2012
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Mon, 27 Aug 2012 06:43:31 -0700
Subject: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <CACRpkdbG4jkFcVP_6AmAZzciffQCamKXw7PcFnTdccyq7AMa8A@mail.gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdbG4jkFcVP_6AmAZzciffQCamKXw7PcFnTdccyq7AMa8A@mail.gmail.com>
Message-ID: <343192fa3698ed0575444a5603ed734d@codethink.co.uk>

On 20/08/2012 06:49, Linus Walleij wrote:
> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
> <sebastian.hesselbarth at gmail.com> wrote:
>
>> This patch adds a SoC specific pinctrl driver for Marvell Kirkwood 
>> SoCs
>> plus DT binding documentation. This driver will use the mvebu 
>> pinctrl
>> driver core.
>
> Thanks for working on Kirkwood. Love this platform.
>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index cd3d827..361f513 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
>>         select GENERIC_CLOCKEVENTS
>>         select NEED_MACH_IO_H
>>         select PLAT_ORION
>> +       select PINCTRL
>
> select PINCTRL_KIRKWOOD too I think.
> Then it's just automatic.
>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index e2427eb..1f84090 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -147,7 +147,7 @@ config PINCTRL_COH901
>>
>>  config PINCTRL_MVEBU
>>         bool "Marvell SoC pin controller drivers"
>> -       depends on ARCH_MVEBU || ARCH_DOVE
>> +       depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
>
> As stated elsewhere I think this should be
> depends on PLAT_ORION
>
>> +config PINCTRL_KIRKWOOD
>> +       bool "Support for Marvell Kirkwood SoCs"
>> +       depends on PINCTRL_MVEBU
>
> depends on ARCH_KIRKWOOD
> select PINCTRL_MVEBU
>
> (...)
>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c 
>> b/drivers/pinctrl/pinctrl-kirkwood.c
>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>> +
>> +static struct of_device_id kirkwood_pinctrl_of_match[] 
>> __devinitdata = {
>> +       { .compatible = "marvell,88f6180-pinctrl",
>> +                                         .data = (void 
>> *)VARIANT_MV88F6180 },
>> +       { .compatible = "marvell,88f6190-pinctrl",
>> +                                         .data = (void 
>> *)VARIANT_MV88F6190 },
>> +       { .compatible = "marvell,88f6192-pinctrl",
>> +                                         .data = (void 
>> *)VARIANT_MV88F6192 },
>> +       { .compatible = "marvell,88f6281-pinctrl",
>> +                                         .data = (void 
>> *)VARIANT_MV88F6281 },
>> +       { .compatible = "marvell,88f6282-pinctrl",
>> +                                         .data = (void 
>> *)VARIANT_MV88F6282 },
>> +       { }
>> +};
>
> I'm thinking this variant should maybe be an enum... unless it is
> strongly established somewhere in Orion/Marvell stuff.
>
>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device 
>> *pdev)
>> +{
>> +       struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>> +       const struct of_device_id *match =
>> +               of_match_device(kirkwood_pinctrl_of_match, 
>> &pdev->dev);
>> +
>> +       if (match) {
>> +               soc->variant = (unsigned)match->data & 0xff;
>> +               switch (soc->variant) {
>> +               case VARIANT_MV88F6180:
>> +                       soc->controls = mv88f6180_mpp_controls;
>> +                       soc->ncontrols = 
>> ARRAY_SIZE(mv88f6180_mpp_controls);
>> +                       soc->modes = mv88f6xxx_mpp_modes;
>> +                       soc->nmodes = 
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> +                       soc->gpioranges = mv88f6180_gpio_ranges;
>> +                       soc->ngpioranges = 
>> ARRAY_SIZE(mv88f6180_gpio_ranges);
>> +                       break;
>> +               case VARIANT_MV88F6190:
>> +               case VARIANT_MV88F6192:
>> +                       soc->controls = mv88f619x_mpp_controls;
>> +                       soc->ncontrols = 
>> ARRAY_SIZE(mv88f619x_mpp_controls);
>> +                       soc->modes = mv88f6xxx_mpp_modes;
>> +                       soc->nmodes = 
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> +                       soc->gpioranges = mv88f619x_gpio_ranges;
>> +                       soc->ngpioranges = 
>> ARRAY_SIZE(mv88f619x_gpio_ranges);
>> +                       break;
>> +               case VARIANT_MV88F6281:
>> +               case VARIANT_MV88F6282:
>> +                       soc->controls = mv88f628x_mpp_controls;
>> +                       soc->ncontrols = 
>> ARRAY_SIZE(mv88f628x_mpp_controls);
>> +                       soc->modes = mv88f6xxx_mpp_modes;
>> +                       soc->nmodes = 
>> ARRAY_SIZE(mv88f6xxx_mpp_modes);
>> +                       soc->gpioranges = mv88f628x_gpio_ranges;
>> +                       soc->ngpioranges = 
>> ARRAY_SIZE(mv88f628x_gpio_ranges);
>> +                       break;
>> +               }
>> +               pdev->dev.platform_data = soc;
>> +       }
>> +       return mvebu_pinctrl_probe(pdev);
>> +}

Why not have structures defining the soc-> parameters and use that in 
the
of_match list?

-- 
Ben



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:44 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:44 +0530
Subject: [PATCH V2 6/6] ASoC: tlv320aic3x: Add device tree bindings
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-7-git-send-email-gururaja.hebbar@ti.com>

Device tree support for tlv320aic3x CODEC driver.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- use standard DT GPIO reference by phandle to populate gpio based DT
	  parameters

:000000 100644 0000000... e7b98f4... A	Documentation/devicetree/bindings/sound/tlv320aic3x.txt
:100644 100644 01485bd... 5708a97... M	sound/soc/codecs/tlv320aic3x.c
 .../devicetree/bindings/sound/tlv320aic3x.txt      |   20 +++++++++++++
 sound/soc/codecs/tlv320aic3x.c                     |   31 ++++++++++++++++++++
 2 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
new file mode 100644
index 0000000..e7b98f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
@@ -0,0 +1,20 @@
+Texas Instruments - tlv320aic3x Codec module
+
+The tlv320aic3x serial control bus communicates through I2C protocols
+
+Required properties:
+- compatible - "string" -  "ti,tlv320aic3x"
+- reg - <int> -  I2C slave address
+
+
+Optional properties:
+
+- gpio-reset - gpio pin number used for codec reset
+- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
+
+Example:
+
+tlv320aic3x: tlv320aic3x at 1b {
+	compatible = "ti,tlv320aic3x";
+	reg = <0x1b>;
+};
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 01485bd..5708a97 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -40,6 +40,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
+#include <linux/of_gpio.h>
 #include <linux/slab.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -1457,6 +1458,8 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
 {
 	struct aic3x_pdata *pdata = i2c->dev.platform_data;
 	struct aic3x_priv *aic3x;
+	struct aic3x_setup_data *ai3x_setup;
+	struct device_node *np = i2c->dev.of_node;
 	int ret;
 
 	aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
@@ -1471,6 +1474,25 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
 	if (pdata) {
 		aic3x->gpio_reset = pdata->gpio_reset;
 		aic3x->setup = pdata->setup;
+	} else if (np) {
+		ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
+								GFP_KERNEL);
+		if (ai3x_setup == NULL) {
+			dev_err(&i2c->dev, "failed to create private data\n");
+			return -ENOMEM;
+		}
+
+		ret = of_get_named_gpio(np, "gpio-reset", 0);
+		if (ret >= 0)
+			aic3x->gpio_reset = ret;
+		else
+			aic3x->gpio_reset = -1;
+
+		if (of_property_read_u32_array(np, "ai3x-gpio-func",
+					ai3x_setup->gpio_func, 2) >= 0) {
+			aic3x->setup = ai3x_setup;
+		}
+
 	} else {
 		aic3x->gpio_reset = -1;
 	}
@@ -1488,11 +1510,20 @@ static int aic3x_i2c_remove(struct i2c_client *client)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id tlv320aic3x_of_match[] = {
+	{ .compatible = "ti,tlv320aic3x", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
+#endif
+
 /* machine i2c codec control layer */
 static struct i2c_driver aic3x_i2c_driver = {
 	.driver = {
 		.name = "tlv320aic3x-codec",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(tlv320aic3x_of_match),
 	},
 	.probe	= aic3x_i2c_probe,
 	.remove = aic3x_i2c_remove,
-- 
1.7.1



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:39 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:39 +0530
Subject: [PATCH V2 1/6] ASoC: davinci: davinci-pcm does not need to be a
 plaform_driver
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>

Same as the commit 518de86 (ASoC: tegra: register 'platform' from DAIs,
get rid of pdev). It makes davinci-pcm not a platform_driver but helper
to register "platform", so that the platform_device for davinci-pcm can
be saved completely.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- New Commit. Instanciate seudo-device (davinci-pcm) directly from DAI
	  driver rather than having a separate virtual-device registered

:100644 100644 c80c20a... 4b37e2a... M	sound/soc/davinci/davinci-evm.c
:100644 100644 0a74b95... 407df72... M	sound/soc/davinci/davinci-i2s.c
:100644 100644 6a2c54c... 34ee2f1... M	sound/soc/davinci/davinci-mcasp.c
:100644 100644 97d77b2... 4b70828... M	sound/soc/davinci/davinci-pcm.c
:100644 100644 c0d6c9b... 5e55164... M	sound/soc/davinci/davinci-pcm.h
:100644 100644 f71175b... 5be65aa... M	sound/soc/davinci/davinci-sffsdr.c
:100644 100644 da030ff... 07bde2e... M	sound/soc/davinci/davinci-vcif.c
 sound/soc/davinci/davinci-evm.c    |   15 ++++++++-------
 sound/soc/davinci/davinci-i2s.c    |   10 ++++++++++
 sound/soc/davinci/davinci-mcasp.c  |   10 ++++++++++
 sound/soc/davinci/davinci-pcm.c    |   23 ++++++-----------------
 sound/soc/davinci/davinci-pcm.h    |    3 +++
 sound/soc/davinci/davinci-sffsdr.c |    2 +-
 sound/soc/davinci/davinci-vcif.c   |    8 ++++++++
 7 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index c80c20a..4b37e2a 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -159,7 +159,7 @@ static struct snd_soc_dai_link dm6446_evm_dai = {
 	.cpu_dai_name = "davinci-mcbsp",
 	.codec_dai_name = "tlv320aic3x-hifi",
 	.codec_name = "tlv320aic3x-codec.1-001b",
-	.platform_name = "davinci-pcm-audio",
+	.platform_name = "davinci-mcbsp",
 	.init = evm_aic3x_init,
 	.ops = &evm_ops,
 };
@@ -170,7 +170,7 @@ static struct snd_soc_dai_link dm355_evm_dai = {
 	.cpu_dai_name = "davinci-mcbsp.1",
 	.codec_dai_name = "tlv320aic3x-hifi",
 	.codec_name = "tlv320aic3x-codec.1-001b",
-	.platform_name = "davinci-pcm-audio",
+	.platform_name = "davinci-mcbsp.1",
 	.init = evm_aic3x_init,
 	.ops = &evm_ops,
 };
@@ -184,14 +184,15 @@ static struct snd_soc_dai_link dm365_evm_dai = {
 	.init = evm_aic3x_init,
 	.codec_name = "tlv320aic3x-codec.1-0018",
 	.ops = &evm_ops,
+	.platform_name = "davinci-mcbsp",
 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
 	.name = "Voice Codec - CQ93VC",
 	.stream_name = "CQ93",
 	.cpu_dai_name = "davinci-vcif",
 	.codec_dai_name = "cq93vc-hifi",
 	.codec_name = "cq93vc-codec",
+	.platform_name = "avinci-vcif",
 #endif
-	.platform_name = "davinci-pcm-audio",
 };
 
 static struct snd_soc_dai_link dm6467_evm_dai[] = {
@@ -200,7 +201,7 @@ static struct snd_soc_dai_link dm6467_evm_dai[] = {
 		.stream_name = "AIC3X",
 		.cpu_dai_name= "davinci-mcasp.0",
 		.codec_dai_name = "tlv320aic3x-hifi",
-		.platform_name ="davinci-pcm-audio",
+		.platform_name = "davinci-mcasp.0",
 		.codec_name = "tlv320aic3x-codec.0-001a",
 		.init = evm_aic3x_init,
 		.ops = &evm_ops,
@@ -211,7 +212,7 @@ static struct snd_soc_dai_link dm6467_evm_dai[] = {
 		.cpu_dai_name= "davinci-mcasp.1",
 		.codec_dai_name = "dit-hifi",
 		.codec_name = "spdif_dit",
-		.platform_name = "davinci-pcm-audio",
+		.platform_name = "davinci-mcasp.1",
 		.ops = &evm_spdif_ops,
 	},
 };
@@ -222,7 +223,7 @@ static struct snd_soc_dai_link da830_evm_dai = {
 	.cpu_dai_name = "davinci-mcasp.1",
 	.codec_dai_name = "tlv320aic3x-hifi",
 	.codec_name = "tlv320aic3x-codec.1-0018",
-	.platform_name = "davinci-pcm-audio",
+	.platform_name = "davinci-mcasp.1",
 	.init = evm_aic3x_init,
 	.ops = &evm_ops,
 };
@@ -233,7 +234,7 @@ static struct snd_soc_dai_link da850_evm_dai = {
 	.cpu_dai_name= "davinci-mcasp.0",
 	.codec_dai_name = "tlv320aic3x-hifi",
 	.codec_name = "tlv320aic3x-codec.1-0018",
-	.platform_name = "davinci-pcm-audio",
+	.platform_name = "davinci-mcasp.0",
 	.init = evm_aic3x_init,
 	.ops = &evm_ops,
 };
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 0a74b95..407df72 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -732,8 +732,16 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 	if (ret != 0)
 		goto err_release_clk;
 
+	ret = davinci_soc_platform_register(&pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
+		goto err_unregister_dai;
+	}
+
 	return 0;
 
+err_unregister_dai:
+	snd_soc_unregister_dai(&pdev->dev);
 err_release_clk:
 	clk_disable(dev->clk);
 	clk_put(dev->clk);
@@ -745,6 +753,8 @@ static int davinci_i2s_remove(struct platform_device *pdev)
 	struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
 
 	snd_soc_unregister_dai(&pdev->dev);
+	davinci_soc_platform_unregister(&pdev->dev);
+
 	clk_disable(dev->clk);
 	clk_put(dev->clk);
 	dev->clk = NULL;
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 6a2c54c..34ee2f1 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -951,8 +951,17 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 
 	if (ret != 0)
 		goto err_release_clk;
+
+	ret = davinci_soc_platform_register(&pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
+		goto err_unregister_dai;
+	}
+
 	return 0;
 
+err_unregister_dai:
+	snd_soc_unregister_dai(&pdev->dev);
 err_release_clk:
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
@@ -963,6 +972,7 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
 {
 
 	snd_soc_unregister_dai(&pdev->dev);
+	davinci_soc_platform_unregister(&pdev->dev);
 
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index 97d77b2..4b70828 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -864,28 +864,17 @@ static struct snd_soc_platform_driver davinci_soc_platform = {
 	.pcm_free = 	davinci_pcm_free,
 };
 
-static int __devinit davinci_soc_platform_probe(struct platform_device *pdev)
+int davinci_soc_platform_register(struct device *dev)
 {
-	return snd_soc_register_platform(&pdev->dev, &davinci_soc_platform);
+	return snd_soc_register_platform(dev, &davinci_soc_platform);
 }
+EXPORT_SYMBOL_GPL(davinci_soc_platform_register);
 
-static int __devexit davinci_soc_platform_remove(struct platform_device *pdev)
+void davinci_soc_platform_unregister(struct device *dev)
 {
-	snd_soc_unregister_platform(&pdev->dev);
-	return 0;
+	snd_soc_unregister_platform(dev);
 }
-
-static struct platform_driver davinci_pcm_driver = {
-	.driver = {
-			.name = "davinci-pcm-audio",
-			.owner = THIS_MODULE,
-	},
-
-	.probe = davinci_soc_platform_probe,
-	.remove = __devexit_p(davinci_soc_platform_remove),
-};
-
-module_platform_driver(davinci_pcm_driver);
+EXPORT_SYMBOL_GPL(davinci_soc_platform_unregister);
 
 MODULE_AUTHOR("Vladimir Barinov");
 MODULE_DESCRIPTION("TI DAVINCI PCM DMA module");
diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
index c0d6c9b..5e55164 100644
--- a/sound/soc/davinci/davinci-pcm.h
+++ b/sound/soc/davinci/davinci-pcm.h
@@ -28,4 +28,7 @@ struct davinci_pcm_dma_params {
 	unsigned int fifo_level;
 };
 
+int davinci_soc_platform_register(struct device *dev);
+void davinci_soc_platform_unregister(struct device *dev);
+
 #endif
diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
index f71175b..5be65aa 100644
--- a/sound/soc/davinci/davinci-sffsdr.c
+++ b/sound/soc/davinci/davinci-sffsdr.c
@@ -86,7 +86,7 @@ static struct snd_soc_dai_link sffsdr_dai = {
 	.cpu_dai_name = "davinci-mcbsp",
 	.codec_dai_name = "pcm3008-hifi",
 	.codec_name = "pcm3008-codec",
-	.platform_name = "davinci-pcm-audio",
+	.platform_name = "davinci-mcbsp",
 	.ops = &sffsdr_ops,
 };
 
diff --git a/sound/soc/davinci/davinci-vcif.c b/sound/soc/davinci/davinci-vcif.c
index da030ff..07bde2e 100644
--- a/sound/soc/davinci/davinci-vcif.c
+++ b/sound/soc/davinci/davinci-vcif.c
@@ -240,12 +240,20 @@ static int davinci_vcif_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = davinci_soc_platform_register(&pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
+		snd_soc_unregister_dai(&pdev->dev);
+		return ret;
+	}
+
 	return 0;
 }
 
 static int davinci_vcif_remove(struct platform_device *pdev)
 {
 	snd_soc_unregister_dai(&pdev->dev);
+	davinci_soc_platform_unregister(&pdev->dev);
 
 	return 0;
 }
-- 
1.7.1



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:40 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:40 +0530
Subject: [PATCH V2 2/6] ARM: Davinci: Remove references to davinci pcm
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-3-git-send-email-gururaja.hebbar@ti.com>

Since davinci-pcm is no more a platform_driver but helper to register
"platform" pcm driver, remove  davinci-pcm device registration

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- New Commit. 

:100644 100644 783eab6... 4735d64... M	arch/arm/mach-davinci/devices-da8xx.c
:100644 100644 d2f96662.. 70056fb... M	arch/arm/mach-davinci/devices.c
 arch/arm/mach-davinci/devices-da8xx.c |    7 -------
 arch/arm/mach-davinci/devices.c       |   11 -----------
 2 files changed, 0 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 783eab6..4735d64 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -505,15 +505,8 @@ static struct platform_device da850_mcasp_device = {
 	.resource	= da850_mcasp_resources,
 };
 
-static struct platform_device davinci_pcm_device = {
-	.name	= "davinci-pcm-audio",
-	.id	= -1,
-};
-
 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 {
-	platform_device_register(&davinci_pcm_device);
-
 	/* DA830/OMAP-L137 has 3 instances of McASP */
 	if (cpu_is_davinci_da830() && id == 1) {
 		da830_mcasp1_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f9666..70056fb 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -313,16 +313,6 @@ static void davinci_init_wdt(void)
 
 /*-------------------------------------------------------------------------*/
 
-static struct platform_device davinci_pcm_device = {
-	.name		= "davinci-pcm-audio",
-	.id		= -1,
-};
-
-static void davinci_init_pcm(void)
-{
-	platform_device_register(&davinci_pcm_device);
-}
-
 /*-------------------------------------------------------------------------*/
 
 struct davinci_timer_instance davinci_timer_instance[2] = {
@@ -345,7 +335,6 @@ static int __init davinci_init_devices(void)
 	/* please keep these calls, and their implementations above,
 	 * in alphabetical order so they're easier to sort through.
 	 */
-	davinci_init_pcm();
 	davinci_init_wdt();
 
 	return 0;
-- 
1.7.1



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:38 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:38 +0530
Subject: [PATCH V2 0/6]  ARM/ASoC: Davinci: Add Device Tree Support
Message-ID: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>

This patch-set is a cumulative of below tasks
1. Split asp header into platform and audio specific
   Davinci driver is shared by few OMAP platforms (like TI81xx, AM335x).
   Splitting asp header into Davinci platform specific and Audio specific helps
   to share them across platforms.

2. Add DT support for Davinci Audio Module (McASP, machine, pcm & Codec)


This patch was tested on AM18x Board (Tested to check if the commits doesn't
break on compile or runtime) and is based on repo at 
http://git.kernel.org/?p=linux/kernel/git/broonie/sound.git;
a=shortlog;h=refs/heads/for-3.7 (v3.6-rc2)

Note:
Matt Porter from TI is working on DMA engine conversion of DaVinci EDMA
support and DT conversion of DMA parts will be taken up post that is
complete.
Since Audio requires DMA to work, this patch set does not yet provide
complete functionality required to use sound on DT-based platforms, but
is a step towards that direction.

Changes from V1:
	- Instanciate seudo-device (davinci-pcm) directly from DAI driver rather
	  than having a separate virtual-device registered
	- add more explanation to DT parameters
	- Change DT parameter from "ti,codec-clock" to "ti,codec-clock-rate"
	- use standard DT GPIO reference by phandle to populate gpio based DT
	  parameters
	- Dont return err if some DT parameters are missing. They will be
	  treated as 0.
	- Through Error warning if num-serializer != "serial-dir" array size
	- Coding Style correction

Hebbar, Gururaja (6):
  ASoC: davinci: davinci-pcm does not need to be a plaform_driver
  ARM: Davinci: Remove references to davinci pcm
  ASoC/ARM: Davinci: McASP: split asp header into platform and audio
    specific
  ASoC: Davinci: McASP: add device tree support for McASP
  ASoC: Davinci: machine: Add device tree binding
  ASoC: tlv320aic3x: Add device tree bindings

 .../bindings/sound/davinci-evm-audio.txt           |   63 ++++++
 .../bindings/sound/davinci-mcasp-audio.txt         |   44 +++++
 .../devicetree/bindings/sound/tlv320aic3x.txt      |   20 ++
 arch/arm/mach-davinci/asp.h                        |   49 +++++
 arch/arm/mach-davinci/davinci.h                    |    3 +-
 arch/arm/mach-davinci/devices-da8xx.c              |    8 +-
 arch/arm/mach-davinci/devices.c                    |   11 -
 arch/arm/mach-davinci/dm355.c                      |    2 +-
 arch/arm/mach-davinci/dm365.c                      |    2 +-
 arch/arm/mach-davinci/dm644x.c                     |    2 +-
 arch/arm/mach-davinci/dm646x.c                     |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h         |    2 +-
 .../linux/platform_data/davinci_asp.h              |   73 ++-----
 sound/soc/codecs/tlv320aic3x.c                     |   31 +++
 sound/soc/davinci/davinci-evm.c                    |  203 +++++++++++++++++---
 sound/soc/davinci/davinci-i2s.c                    |   13 +-
 sound/soc/davinci/davinci-mcasp.c                  |  134 +++++++++++++-
 sound/soc/davinci/davinci-mcasp.h                  |    3 +-
 sound/soc/davinci/davinci-pcm.c                    |   24 +--
 sound/soc/davinci/davinci-pcm.h                    |    6 +-
 sound/soc/davinci/davinci-sffsdr.c                 |    2 +-
 sound/soc/davinci/davinci-vcif.c                   |    8 +
 22 files changed, 573 insertions(+), 132 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
 create mode 100644 Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
 create mode 100644 Documentation/devicetree/bindings/sound/tlv320aic3x.txt
 create mode 100644 arch/arm/mach-davinci/asp.h
 rename arch/arm/mach-davinci/include/mach/asp.h => include/linux/platform_data/davinci_asp.h (56%)



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:42 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:42 +0530
Subject: [PATCH V2 4/6] ASoC: Davinci: McASP: add device tree support for McASP
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-5-git-send-email-gururaja.hebbar@ti.com>

Add device tree probe for McASP driver.

Note:
DMA parameters are not populated from DT and will be done later.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- add more explanation to DT parameters
	- Dont return err if some DT parameters are missing. They will be
	  treated as 0.
	- Through Error warning if num-serializer != "serial-dir" array size

:000000 100644 0000000... e6148ec... A	Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
:100644 100644 34ee2f1... c3eae1d... M	sound/soc/davinci/davinci-mcasp.c
 .../bindings/sound/davinci-mcasp-audio.txt         |   44 +++++++
 sound/soc/davinci/davinci-mcasp.c                  |  124 +++++++++++++++++++-
 2 files changed, 167 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
new file mode 100644
index 0000000..e6148ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
@@ -0,0 +1,44 @@
+Texas Instruments McASP controller
+
+Required properties:
+- compatible :
+	"ti,dm646x-mcasp-audio"	: for DM646x platforms
+	"ti,da830-mcasp-audio"	: for both DA830 & DA850 platforms
+
+- reg : Should contain McASP registers offset and length
+- interrupts : Interrupt number for McASP
+- op-mode : I2S/DIT ops mode.
+- tdm-slots : Slots for TDM operation.
+- num-serializer : Serializers used by McASP.
+- serial-dir : A list of serializer pin mode. The list number should be equal
+		to "num-serializer" parameter. Each entry is a number indication
+		serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX)
+
+
+Optional properties:
+
+- ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0
+- tx-num-evt : FIFO levels.
+- rx-num-evt : FIFO levels.
+- sram-size-playback : size of sram to be allocated during playback
+- sram-size-capture  : size of sram to be allocated during capture
+
+Example:
+
+mcasp0: mcasp0 at 1d00000 {
+	compatible = "ti,da830-mcasp-audio";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x100000 0x3000>;
+	interrupts = <82 83>;
+	op-mode = <0>;		/* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	num-serializer = <16>;
+	serial-dir = <
+			0 0 0 0	/* 0: INACTIVE, 1: TX, 2: RX */
+			0 0 0 0
+			0 0 0 1
+			2 0 0 0 >;
+	tx-num-evt = <1>;
+	rx-num-evt = <1>;
+};
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 34ee2f1..c3eae1d 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -22,6 +22,9 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -862,6 +865,114 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
 
 };
 
+static const struct of_device_id mcasp_dt_ids[] = {
+	{
+		.compatible = "ti,dm646x-mcasp-audio",
+		.data = (void *)MCASP_VERSION_1,
+	},
+	{
+		.compatible = "ti,da830-mcasp-audio",
+		.data = (void *)MCASP_VERSION_2,
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
+
+static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
+						struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct snd_platform_data *pdata = NULL;
+	const struct of_device_id *match =
+			of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
+
+	const u32 *of_serial_dir32;
+	u8 *of_serial_dir;
+	u32 val;
+	int i, ret = 0;
+
+	if (pdev->dev.platform_data) {
+		pdata = pdev->dev.platform_data;
+		return pdata;
+	} else if (match) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata) {
+			ret = -ENOMEM;
+			goto nodata;
+		}
+	} else {
+		/* control shouldn't reach here. something is wrong */
+		ret = -EINVAL;
+		goto nodata;
+	}
+
+	if (match->data)
+		pdata->version = (u8)((int)match->data);
+
+	ret = of_property_read_u32(np, "op-mode", &val);
+	if (ret >= 0)
+		pdata->op_mode = val;
+
+	ret = of_property_read_u32(np, "tdm-slots", &val);
+	if (ret >= 0)
+		pdata->tdm_slots = val;
+
+	ret = of_property_read_u32(np, "num-serializer", &val);
+	if (ret >= 0)
+		pdata->num_serializer = val;
+
+	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
+	val /= sizeof(u32);
+	if (val != pdata->num_serializer) {
+		dev_err(&pdev->dev,
+				"num-serializer(%d) != serial-dir size(%d)\n",
+				pdata->num_serializer, val);
+		ret = -EINVAL;
+		goto nodata;
+	}
+
+	if (of_serial_dir32) {
+		of_serial_dir = devm_kzalloc(&pdev->dev,
+						(sizeof(*of_serial_dir) * val),
+						GFP_KERNEL);
+		if (!of_serial_dir) {
+			ret = -ENOMEM;
+			goto nodata;
+		}
+
+		for (i = 0; i < pdata->num_serializer; i++)
+			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
+
+		pdata->serial_dir = of_serial_dir;
+	}
+
+	ret = of_property_read_u32(np, "tx-num-evt", &val);
+	if (ret >= 0)
+		pdata->txnumevt = val;
+
+	ret = of_property_read_u32(np, "rx-num-evt", &val);
+	if (ret >= 0)
+		pdata->rxnumevt = val;
+
+	ret = of_property_read_u32(np, "sram-size-playback", &val);
+	if (ret >= 0)
+		pdata->sram_size_playback = val;
+
+	ret = of_property_read_u32(np, "sram-size-capture", &val);
+	if (ret >= 0)
+		pdata->sram_size_capture = val;
+
+	return  pdata;
+
+nodata:
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
+			ret);
+		pdata = NULL;
+	}
+	return  pdata;
+}
+
 static int davinci_mcasp_probe(struct platform_device *pdev)
 {
 	struct davinci_pcm_dma_params *dma_data;
@@ -870,11 +981,22 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 	struct davinci_audio_dev *dev;
 	int ret;
 
+	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
+		dev_err(&pdev->dev, "No platform data supplied\n");
+		return -EINVAL;
+	}
+
 	dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
 			   GFP_KERNEL);
 	if (!dev)
 		return	-ENOMEM;
 
+	pdata = davinci_mcasp_set_pdata_from_of(pdev);
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data\n");
+		return -EINVAL;
+	}
+
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
 		dev_err(&pdev->dev, "no mem resource?\n");
@@ -888,7 +1010,6 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
 		return -EBUSY;
 	}
 
-	pdata = pdev->dev.platform_data;
 	pm_runtime_enable(&pdev->dev);
 
 	ret = pm_runtime_get_sync(&pdev->dev);
@@ -986,6 +1107,7 @@ static struct platform_driver davinci_mcasp_driver = {
 	.driver		= {
 		.name	= "davinci-mcasp",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(mcasp_dt_ids),
 	},
 };
 
-- 
1.7.1



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:43 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:43 +0530
Subject: [PATCH V2 5/6] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-6-git-send-email-gururaja.hebbar@ti.com>

Device tree support for tlv320aic3x CODEC driver

When the board boots with device tree, the driver will receive card,
codec, dai interface details (like the card name, DAPM routing map,
phandle for the audio components described in the dts file, codec mclk
speed).

The card will be set up based on this information.
Since the routing is provided via DT we can mark the card fully routed
so core can take care of disconnecting the unused pins.

When here, code indentation and comment style is also fixed

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- Change DT parameter from "ti,codec-clock" to "ti,codec-clock-rate"
	- add more explanation to DT parameters

:000000 100644 0000000... fcbcd24... A	Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
:100644 100644 ab0ad45... ca2a547... M	sound/soc/davinci/davinci-evm.c
 .../bindings/sound/davinci-evm-audio.txt           |   63 +++++++
 sound/soc/davinci/davinci-evm.c                    |  185 +++++++++++++++++--
 2 files changed, 228 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
new file mode 100644
index 0000000..fcbcd24
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -0,0 +1,63 @@
+* Texas Instruments SoC audio setups with TLV320AIC3X Codec
+
+Required properties:
+- compatible : "ti,davinci-evm-audio"
+- ti,model : The user-visible name of this sound complex.
+- ti,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the codec's pins, and the jacks on the board:
+
+  Codec pins:
+
+  * MIC3L
+  * MIC3R
+  * LINE1L
+  * LINE2L
+  * LINE1R
+  * LINE2R
+
+  Board connectors:
+
+  * Headphone Jack
+  * Line Out
+  * Mic Jack
+
+- ti,mcasp-controller : The phandle of the McASP controller
+- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
+- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
+
+- dai-data		: A list of DAI data used by SOC code to register
+			  DAI, Codecs platform.
+			  The string index "should" be as shown below.
+dai-data =
+"<DAI Name>", 		"<DAI Stream Name>",
+"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
+"<evm ops required (evm_ops or evm_spdif_ops)>";
+
+Here fields
+"<DAI Name>"		: used to indicate the DAI Name
+"<DAI Stream Name>"	: used to indicate the Stream Name
+"<CODEC DAI Name>"	: used to bind the link between Codec DAI and ASOC DAI
+
+Machine related options
+"<true/false>"		: Whether the machine specific initialization
+			: evm_aic3x_init() is required
+
+"<evm ops required>"	: Which hardware ops function is to be used.
+			: (evm_ops or evm_spdif_ops)
+
+
+Example:
+
+sound {
+	compatible = "ti,davinci-evm-audio";
+	ti,model = "DA830 EVM";
+	ti,audio-codec = <&tlv320aic3x>;
+	ti,mcasp-controller = <&mcasp1>;
+	ti,codec-clock-rate = <12000000>;
+	dai-data =
+		"TLV320AIC3X", 		"AIC3X",
+		"tlv320aic3x-hifi",	"true",
+		"evm-ops";
+};
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index ab0ad45..ca2a547 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -34,27 +34,38 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_card *soc_card = codec->card;
+	struct device_node *np = soc_card->dev->of_node;
 	int ret = 0;
 	unsigned sysclk;
 
-	/* ASP1 on DM355 EVM is clocked by an external oscillator */
-	if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
-	    machine_is_davinci_dm365_evm())
-		sysclk = 27000000;
-
-	/* ASP0 in DM6446 EVM is clocked by U55, as configured by
-	 * board-dm644x-evm.c using GPIOs from U18.  There are six
-	 * options; here we "know" we use a 48 KHz sample rate.
-	 */
-	else if (machine_is_davinci_evm())
-		sysclk = 12288000;
-
-	else if (machine_is_davinci_da830_evm() ||
-				machine_is_davinci_da850_evm())
-		sysclk = 24576000;
-
-	else
-		return -EINVAL;
+	if (np) {
+		ret = of_property_read_u32(np, "ti,codec-clock-rate", &sysclk);
+		if (ret < 0)
+			return ret;
+	} else {
+		/* ASP1 on DM355 EVM is clocked by an external oscillator */
+		if (machine_is_davinci_dm355_evm() ||
+			machine_is_davinci_dm6467_evm() ||
+			machine_is_davinci_dm365_evm())
+			sysclk = 27000000;
+
+		/*
+		 * ASP0 in DM6446 EVM is clocked by U55, as configured by
+		 * board-dm644x-evm.c using GPIOs from U18.  There are six
+		 * options; here we "know" we use a 48 KHz sample rate.
+		 */
+		else if (machine_is_davinci_evm())
+			sysclk = 12288000;
+
+		else if (machine_is_davinci_da830_evm() ||
+					machine_is_davinci_da850_evm())
+			sysclk = 24576000;
+
+		else
+			return -EINVAL;
+	}
 
 	/* set codec DAI configuration */
 	ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
@@ -127,13 +138,22 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_codec *codec = rtd->codec;
 	struct snd_soc_dapm_context *dapm = &codec->dapm;
+	struct device_node *np = codec->card->dev->of_node;
+	int ret;
 
 	/* Add davinci-evm specific widgets */
 	snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
 				  ARRAY_SIZE(aic3x_dapm_widgets));
 
-	/* Set up davinci-evm specific audio path audio_map */
-	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	if (np) {
+		ret = snd_soc_of_parse_audio_routing(codec->card,
+							"ti,audio-routing");
+		if (ret)
+			return ret;
+	} else {
+		/* Set up davinci-evm specific audio path audio_map */
+		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	}
 
 	/* not connected */
 	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
@@ -282,6 +302,113 @@ static struct snd_soc_card da850_snd_soc_card = {
 	.num_links = 1,
 };
 
+#if defined(CONFIG_OF)
+/*
+ * This struct is just used as place holder. It will be filled with
+ * data from dt node
+ */
+static struct snd_soc_dai_link evm_dai = {
+};
+
+/* davinci evm audio machine driver */
+static struct snd_soc_card evm_soc_card = {
+	.owner = THIS_MODULE,
+	.dai_link = &evm_dai,
+	.num_links = 1,
+};
+
+static int davinci_evm_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const char *stringPtr, *propname;
+	u32 val;
+	int ret = 0;
+
+	propname = "dai-data";
+	val = of_property_count_strings(np, propname);
+	if (val < 0)
+		return val;
+
+	ret = of_property_read_string_index(np, propname, 0, &evm_dai.name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 1,
+						&evm_dai.stream_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 2,
+						&evm_dai.codec_dai_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 3, &stringPtr);
+	if (ret < 0)
+		return ret;
+	else
+		if (strcasecmp(stringPtr, "true") == 0)
+			evm_dai.init = evm_aic3x_init;
+
+	ret = of_property_read_string_index(np, propname, 4, &stringPtr);
+	if (ret < 0) {
+		return ret;
+	} else {
+		if (strcasecmp(stringPtr, "evm-ops") == 0)
+			evm_dai.ops = &evm_ops;
+		else if (strcasecmp(stringPtr, "evm-spdif-ops") == 0)
+			evm_dai.ops = &evm_spdif_ops;
+	}
+
+	evm_dai.codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
+	if (!evm_dai.codec_of_node)
+		return -EINVAL;
+
+	evm_dai.cpu_dai_of_node = of_parse_phandle(np,
+						"ti,mcasp-controller", 0);
+	if (!evm_dai.cpu_dai_of_node)
+		return -EINVAL;
+
+	evm_dai.platform_of_node = evm_dai.cpu_dai_of_node;
+
+	evm_soc_card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
+	if (ret)
+		return ret;
+
+	ret = snd_soc_register_card(&evm_soc_card);
+	if (ret)
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+
+	return ret;
+}
+
+static int __devexit davinci_evm_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(card);
+
+	return 0;
+}
+
+static const struct of_device_id davinci_evm_dt_ids[] = {
+	{ .compatible = "ti,davinci-evm-audio", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, davinci_mcasp_dt_ids);
+
+static struct platform_driver davinci_evm_driver = {
+	.probe		= davinci_evm_probe,
+	.remove		= __devexit_p(davinci_evm_remove),
+	.driver		= {
+		.name	= "davinci_evm",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(davinci_evm_dt_ids),
+	},
+};
+#endif
+
 static struct platform_device *evm_snd_device;
 
 static int __init evm_init(void)
@@ -289,6 +416,14 @@ static int __init evm_init(void)
 	struct snd_soc_card *evm_snd_dev_data;
 	int index;
 	int ret;
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		return platform_driver_register(&davinci_evm_driver);
+	}
+#endif
 
 	if (machine_is_davinci_evm()) {
 		evm_snd_dev_data = &dm6446_snd_soc_card_evm;
@@ -325,6 +460,16 @@ static int __init evm_init(void)
 
 static void __exit evm_exit(void)
 {
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		platform_driver_unregister(&davinci_evm_driver);
+		return;
+	}
+#endif
+
 	platform_device_unregister(evm_snd_device);
 }
 
-- 
1.7.1



From gururaja.hebbar at ti.com  Mon Aug 27 09:26:41 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Mon, 27 Aug 2012 18:56:41 +0530
Subject: [PATCH V2 3/6] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346074004-22172-4-git-send-email-gururaja.hebbar@ti.com>

Davinci McASP header & driver are shared by few OMAP platforms (like
TI81xx, AM335x). Splitting asp header into Davinci platform specific
header and Audio specific header helps to share them across platforms.

Audio specific defines is moved to to common
<linux/platform_data/davinci_asp.h> so that the header can be
accessed by all related platforms.

While here, correct the header usage (remove multiple header
re-definitions and unused headers) and remove platform names from
structures comments and enum. Also some some coding style errors.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia at ti.com>

---
Changes from V1:
	- Coding Style Correction

:000000 100644 0000000... d9b2acd... A	arch/arm/mach-davinci/asp.h
:100644 100644 8db0fc6... 8661b20... M	arch/arm/mach-davinci/davinci.h
:100644 100644 4735d64... bd2f72b... M	arch/arm/mach-davinci/devices-da8xx.c
:100644 100644 678cd99... e47a3f0... M	arch/arm/mach-davinci/dm355.c
:100644 100644 a50d49de.. f473745... M	arch/arm/mach-davinci/dm365.c
:100644 100644 c8b8666... 0755d46... M	arch/arm/mach-davinci/dm644x.c
:100644 100644 9eb87c1... 97c0f8e... M	arch/arm/mach-davinci/dm646x.c
:100644 100644 a2f1f27... c74a6ab... M	arch/arm/mach-davinci/include/mach/da8xx.h
:100644 100644 9aa2409... 79c26aa... R056	arch/arm/mach-davinci/include/mach/asp.h	include/linux/platform_data/davinci_asp.h
:100644 100644 4b37e2a... ab0ad45... M	sound/soc/davinci/davinci-evm.c
:100644 100644 407df72... 8218312... M	sound/soc/davinci/davinci-i2s.c
:100644 100644 51479f9... 0de9ed6... M	sound/soc/davinci/davinci-mcasp.h
:100644 100644 4b70828... 93ea3bf... M	sound/soc/davinci/davinci-pcm.c
:100644 100644 5e55164... fc4d01c... M	sound/soc/davinci/davinci-pcm.h
 arch/arm/mach-davinci/asp.h                        |   49 +++++++++++++
 arch/arm/mach-davinci/davinci.h                    |    3 +-
 arch/arm/mach-davinci/devices-da8xx.c              |    1 +
 arch/arm/mach-davinci/dm355.c                      |    2 +-
 arch/arm/mach-davinci/dm365.c                      |    2 +-
 arch/arm/mach-davinci/dm644x.c                     |    2 +-
 arch/arm/mach-davinci/dm646x.c                     |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h         |    2 +-
 .../linux/platform_data/davinci_asp.h              |   73 ++++++--------------
 sound/soc/davinci/davinci-evm.c                    |    3 -
 sound/soc/davinci/davinci-i2s.c                    |    3 +-
 sound/soc/davinci/davinci-mcasp.h                  |    3 +-
 sound/soc/davinci/davinci-pcm.c                    |    1 -
 sound/soc/davinci/davinci-pcm.h                    |    3 +-
 14 files changed, 81 insertions(+), 68 deletions(-)

diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
new file mode 100644
index 0000000..d9b2acd
--- /dev/null
+++ b/arch/arm/mach-davinci/asp.h
@@ -0,0 +1,49 @@
+/*
+ * TI DaVinci Audio definitions
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+/* Bases of dm644x and dm355 register banks */
+#define DAVINCI_ASP0_BASE	0x01E02000
+#define DAVINCI_ASP1_BASE	0x01E04000
+
+/* Bases of dm365 register banks */
+#define DAVINCI_DM365_ASP0_BASE	0x01D02000
+
+/* Bases of dm646x register banks */
+#define DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
+#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
+
+/* Bases of da850/da830 McASP0  register banks */
+#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
+
+/* Bases of da830 McASP1 register banks */
+#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
+
+/* EDMA channels of dm644x and dm355 */
+#define DAVINCI_DMA_ASP0_TX	2
+#define DAVINCI_DMA_ASP0_RX	3
+#define DAVINCI_DMA_ASP1_TX	8
+#define DAVINCI_DMA_ASP1_RX	9
+
+/* EDMA channels of dm646x */
+#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
+#define DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
+#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
+
+/* EDMA channels of da850/da830 McASP0 */
+#define DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
+#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
+
+/* EDMA channels of da830 McASP1 */
+#define DAVINCI_DA830_DMA_MCASP1_AREVT	2
+#define DAVINCI_DA830_DMA_MCASP1_AXEVT	3
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6..8661b20 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -22,10 +22,11 @@
 #include <linux/davinci_emac.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/hardware.h>
+#include <mach/edma.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 4735d64..bd2f72b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,6 +24,7 @@
 #include <mach/cpuidle.h>
 
 #include "clock.h"
+#include "asp.h"
 
 #define DA8XX_TPCC_BASE			0x01c00000
 #define DA8XX_TPTC0_BASE		0x01c08000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..e47a3f0 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -26,13 +26,13 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM355_UART2_BASE	(IO_PHYS + 0x206000)
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49d..f473745 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -29,7 +29,6 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
@@ -37,6 +36,7 @@
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
 
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..0755d46 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -23,12 +23,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 /*
  * Device specific clocks
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1..97c0f8e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -24,12 +24,12 @@
 #include <mach/time.h>
 #include <mach/serial.h>
 #include <mach/common.h>
-#include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
 #include "mux.h"
+#include "asp.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
 
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f27..c74a6ab 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -16,11 +16,11 @@
 #include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
-#include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 #include <mach/pm.h>
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/include/linux/platform_data/davinci_asp.h
similarity index 56%
rename from arch/arm/mach-davinci/include/mach/asp.h
rename to include/linux/platform_data/davinci_asp.h
index 9aa2409..79c26aa 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -1,59 +1,26 @@
 /*
- * <mach/asp.h> - DaVinci Audio Serial Port support
+ * TI DaVinci Audio Serial Port support
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
  */
-#ifndef __ASM_ARCH_DAVINCI_ASP_H
-#define __ASM_ARCH_DAVINCI_ASP_H
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
-
-/* Bases of dm644x and dm355 register banks */
-#define DAVINCI_ASP0_BASE	0x01E02000
-#define DAVINCI_ASP1_BASE	0x01E04000
-
-/* Bases of dm365 register banks */
-#define DAVINCI_DM365_ASP0_BASE	0x01D02000
-
-/* Bases of dm646x register banks */
-#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
-#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
-
-/* Bases of da850/da830 McASP0  register banks */
-#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
-
-/* Bases of da830 McASP1 register banks */
-#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
-
-/* EDMA channels of dm644x and dm355 */
-#define DAVINCI_DMA_ASP0_TX	2
-#define DAVINCI_DMA_ASP0_RX	3
-#define DAVINCI_DMA_ASP1_TX	8
-#define DAVINCI_DMA_ASP1_RX	9
-
-/* EDMA channels of dm646x */
-#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
-#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
-#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
-
-/* EDMA channels of da850/da830 McASP0 */
-#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
-#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
-
-/* EDMA channels of da830 McASP1 */
-#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
-#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
-
-/* Interrupts */
-#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
+#ifndef __DAVINCI_ASP_H
+#define __DAVINCI_ASP_H
 
 struct snd_platform_data {
 	u32 tx_dma_offset;
 	u32 rx_dma_offset;
-	enum dma_event_q asp_chan_q;	/* event queue number for ASP channel */
-	enum dma_event_q ram_chan_q;	/* event queue number for RAM channel */
+	int asp_chan_q;	/* event queue number for ASP channel */
+	int ram_chan_q;	/* event queue number for RAM channel */
 	unsigned int codec_fmt;
 	/*
 	 * Allowing this is more efficient and eliminates left and right swaps
@@ -70,7 +37,7 @@ struct snd_platform_data {
 	 * and MCBSP_CLKS.
 	 * Depending on different hardware connections it is possible
 	 * to use this setting to change the behaviour of McBSP
-	 * driver. The dm365_clk_input_pin enum is available for dm365
+	 * driver.
 	 */
 	int clk_input_pin;
 
@@ -122,8 +89,8 @@ enum {
 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
 };
 
-enum dm365_clk_input_pin {
-	MCBSP_CLKR = 0,		/* DM365 */
+enum mcbsp_clk_input_pin {
+	MCBSP_CLKR = 0,		/* as in DM365 */
 	MCBSP_CLKS,
 };
 
@@ -134,4 +101,4 @@ enum dm365_clk_input_pin {
 #define DAVINCI_MCASP_IIS_MODE	0
 #define DAVINCI_MCASP_DIT_MODE	1
 
-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
+#endif
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 4b37e2a..ab0ad45 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -22,9 +22,6 @@
 #include <asm/dma.h>
 #include <asm/mach-types.h>
 
-#include <mach/asp.h>
-#include <mach/edma.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 #include "davinci-mcasp.h"
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 407df72..8218312 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -16,6 +16,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/platform_data/davinci_asp.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -23,8 +24,6 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <mach/asp.h>
-
 #include "davinci-pcm.h"
 #include "davinci-i2s.h"
 
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
index 51479f9..0de9ed6 100644
--- a/sound/soc/davinci/davinci-mcasp.h
+++ b/sound/soc/davinci/davinci-mcasp.h
@@ -19,7 +19,8 @@
 #define DAVINCI_MCASP_H
 
 #include <linux/io.h>
-#include <mach/asp.h>
+#include <linux/platform_data/davinci_asp.h>
+
 #include "davinci-pcm.h"
 
 #define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_96000
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index 4b70828..93ea3bf 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -23,7 +23,6 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
-#include <mach/edma.h>
 #include <mach/sram.h>
 
 #include "davinci-pcm.h"
diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
index 5e55164..fc4d01c 100644
--- a/sound/soc/davinci/davinci-pcm.h
+++ b/sound/soc/davinci/davinci-pcm.h
@@ -12,9 +12,8 @@
 #ifndef _DAVINCI_PCM_H
 #define _DAVINCI_PCM_H
 
+#include <linux/platform_data/davinci_asp.h>
 #include <mach/edma.h>
-#include <mach/asp.h>
-
 
 struct davinci_pcm_dma_params {
 	int channel;			/* sync dma channel ID */
-- 
1.7.1



From haojian.zhuang at gmail.com  Mon Aug 27 09:45:23 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 27 Aug 2012 21:45:23 +0800
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <CAMj5BkjqUNV2o_BMyHH8C5ZCsUf6qChamc6h4H-a9otEGVBx4A@mail.gmail.com>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
 <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
 <20120827082914.GN18957@n2100.arm.linux.org.uk>
 <CAMj5BkjqUNV2o_BMyHH8C5ZCsUf6qChamc6h4H-a9otEGVBx4A@mail.gmail.com>
Message-ID: <CAN1soZyPp4--G3GjSpy8JZViFE4ed8dSyRnxgBfORam21SzpDQ@mail.gmail.com>

On Mon, Aug 27, 2012 at 4:56 PM, zhangfei gao <zhangfei.gao at gmail.com> wrote:
>
> Any suggestion of flushing cache according to cache line, instead of PAGE_SIZE.
> In order to get specific area, we use addr from user directly, which
> may not be the PAGE start.
>
> We have some usage case to flush cache according to cache line.
> CPU - cache - ddr - gpu
> 1. For correctness, driver only flush used size, if align to PAGE_SIZE,
> other area may be flushed by mistake.
> 2. for efficiency, cache line align will be perfered.

I think that maybe flushing PAGE_SIZE is acceptable. ION/PMEM is always designed
for large memory sharing. Maybe you can monitor the partial flushing
user case, I doubt
they're always flushing several pages, not several cachelines.


From ulf.hansson at stericsson.com  Mon Aug 27 09:45:49 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 Aug 2012 15:45:49 +0200
Subject: [PATCH V2 0/4] clk: Convert ARM ux500 to common clock
Message-ID: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

This converts the ux500 machine specific clocks to the common
clock framework. Old clock code are then removed from the ux500
machine directory.

This first version contains PRCMU and PRCC clock implementation.
Additional clock types shall be implemented as the next step,
although the u8500 platform is able to boot without having to
manage these.

Clock definitions are setup for u8500 and are prepared to be
setup for u9540 and as well for u8540.

This patchseries is based upon Linux 3.6 rc.2.

Compile wise a cross dependency exist to the arm-soc-tree for
the last patch (PATCH 4) affecting the ux500 machine code files.
Hopefully Arnd Bergmann can assist in getting those patches, pushed
by Linus Walleij merged prior to these onces.

Ulf Hansson (4):
  clk: ux500: Adapt PRCMU and PRCC clocks for common clk
  clk: ux500: First version of clock definitions for ux500
  clk: ux500: Clock definitions for u8500
  ARM: ux500: Switch to use common clock framework

 arch/arm/mach-ux500/Kconfig             |    1 +
 arch/arm/mach-ux500/Makefile            |    2 +-
 arch/arm/mach-ux500/clock.c             |  715 -------------------------------
 arch/arm/mach-ux500/clock.h             |  164 -------
 arch/arm/mach-ux500/cpu.c               |   14 +-
 drivers/clk/Makefile                    |    1 +
 drivers/clk/ux500/Makefile              |   12 +
 drivers/clk/ux500/clk-prcc.c            |  164 +++++++
 drivers/clk/ux500/clk-prcmu.c           |  238 ++++++++++
 drivers/clk/ux500/clk.h                 |   43 ++
 drivers/clk/ux500/u8500_clk.c           |  473 ++++++++++++++++++++
 drivers/clk/ux500/u8540_clk.c           |   21 +
 drivers/clk/ux500/u9540_clk.c           |   21 +
 include/linux/platform_data/clk-ux500.h |   17 +
 14 files changed, 1000 insertions(+), 886 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/clock.c
 delete mode 100644 arch/arm/mach-ux500/clock.h
 create mode 100644 drivers/clk/ux500/Makefile
 create mode 100644 drivers/clk/ux500/clk-prcc.c
 create mode 100644 drivers/clk/ux500/clk-prcmu.c
 create mode 100644 drivers/clk/ux500/clk.h
 create mode 100644 drivers/clk/ux500/u8500_clk.c
 create mode 100644 drivers/clk/ux500/u8540_clk.c
 create mode 100644 drivers/clk/ux500/u9540_clk.c
 create mode 100644 include/linux/platform_data/clk-ux500.h

-- 
1.7.10



From ulf.hansson at stericsson.com  Mon Aug 27 09:45:50 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 Aug 2012 15:45:50 +0200
Subject: [PATCH V2 1/4] clk: ux500: Adapt PRCMU and PRCC clocks for common clk
In-Reply-To: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346075153-14180-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

First version of common clock implementation of PRCMU clocks
and PRCC clocks for ux500 platforms.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---

Changes in v2:
	- Remove use of "__io_address" and use "ioremap" instead.

---
 drivers/clk/ux500/Makefile    |    7 ++
 drivers/clk/ux500/clk-prcc.c  |  164 ++++++++++++++++++++++++++++
 drivers/clk/ux500/clk-prcmu.c |  238 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/ux500/clk.h       |   43 ++++++++
 4 files changed, 452 insertions(+)
 create mode 100644 drivers/clk/ux500/Makefile
 create mode 100644 drivers/clk/ux500/clk-prcc.c
 create mode 100644 drivers/clk/ux500/clk-prcmu.c
 create mode 100644 drivers/clk/ux500/clk.h

diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
new file mode 100644
index 0000000..a3ccd1b
--- /dev/null
+++ b/drivers/clk/ux500/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for ux500 clocks
+#
+
+# Clock types
+obj-y += clk-prcc.o
+obj-y += clk-prcmu.o
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
new file mode 100644
index 0000000..7eee7f7
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -0,0 +1,164 @@
+/*
+ * PRCC clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <mach/hardware.h>
+
+#include "clk.h"
+
+#define PRCC_PCKEN			0x000
+#define PRCC_PCKDIS			0x004
+#define PRCC_KCKEN			0x008
+#define PRCC_KCKDIS			0x00C
+#define PRCC_PCKSR			0x010
+#define PRCC_KCKSR			0x014
+
+#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
+
+struct clk_prcc {
+	struct clk_hw hw;
+	void __iomem *base;
+	u32 cg_sel;
+	int is_enabled;
+};
+
+/* PRCC clock operations. */
+
+static int clk_prcc_pclk_enable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+
+	writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
+	while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
+		cpu_relax();
+
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcc_pclk_disable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+
+	writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
+	clk->is_enabled = 0;
+}
+
+static int clk_prcc_kclk_enable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+
+	writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
+	while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel))
+		cpu_relax();
+
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcc_kclk_disable(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+
+	writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
+	clk->is_enabled = 0;
+}
+
+static int clk_prcc_is_enabled(struct clk_hw *hw)
+{
+	struct clk_prcc *clk = to_clk_prcc(hw);
+	return clk->is_enabled;
+}
+
+static struct clk_ops clk_prcc_pclk_ops = {
+	.enable = clk_prcc_pclk_enable,
+	.disable = clk_prcc_pclk_disable,
+	.is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk_ops clk_prcc_kclk_ops = {
+	.enable = clk_prcc_kclk_enable,
+	.disable = clk_prcc_kclk_disable,
+	.is_enabled = clk_prcc_is_enabled,
+};
+
+static struct clk *clk_reg_prcc(const char *name,
+				const char *parent_name,
+				resource_size_t phy_base,
+				u32 cg_sel,
+				unsigned long flags,
+				struct clk_ops *clk_prcc_ops)
+{
+	struct clk_prcc *clk;
+	struct clk_init_data clk_prcc_init;
+	struct clk *clk_reg;
+
+	if (!name) {
+		pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
+	if (!clk) {
+		pr_err("clk_prcc: %s could not allocate clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk->base = ioremap(phy_base, SZ_4K);
+	if (!clk->base)
+		goto free_clk;
+
+	clk->cg_sel = cg_sel;
+	clk->is_enabled = 1;
+
+	clk_prcc_init.name = name;
+	clk_prcc_init.ops = clk_prcc_ops;
+	clk_prcc_init.flags = flags;
+	clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
+	clk_prcc_init.num_parents = (parent_name ? 1 : 0);
+	clk->hw.init = &clk_prcc_init;
+
+	clk_reg = clk_register(NULL, &clk->hw);
+	if (IS_ERR_OR_NULL(clk_reg))
+		goto unmap_clk;
+
+	return clk_reg;
+
+unmap_clk:
+	iounmap(clk->base);
+free_clk:
+	kfree(clk);
+	pr_err("clk_prcc: %s failed to register clk\n", __func__);
+	return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+			      const char *parent_name,
+			      resource_size_t phy_base,
+			      u32 cg_sel,
+			      unsigned long flags)
+{
+	return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
+			&clk_prcc_pclk_ops);
+}
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+			      const char *parent_name,
+			      resource_size_t phy_base,
+			      u32 cg_sel,
+			      unsigned long flags)
+{
+	return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
+			&clk_prcc_kclk_ops);
+}
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
new file mode 100644
index 0000000..1d779ad
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -0,0 +1,238 @@
+/*
+ * PRCMU clock implementation for ux500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
+
+struct clk_prcmu {
+	struct clk_hw hw;
+	u8 cg_sel;
+	int is_enabled;
+};
+
+/* PRCMU clock operations. */
+
+static int clk_prcmu_prepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_request_clock(clk->cg_sel, true);
+}
+
+static void clk_prcmu_unprepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	if (prcmu_request_clock(clk->cg_sel, false))
+		pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+			hw->init->name);
+}
+
+static int clk_prcmu_enable(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	clk->is_enabled = 1;
+	return 0;
+}
+
+static void clk_prcmu_disable(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	clk->is_enabled = 0;
+}
+
+static int clk_prcmu_is_enabled(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return clk->is_enabled;
+}
+
+static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_clock_rate(clk->cg_sel);
+}
+
+static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long *parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_round_clock_rate(clk->cg_sel, rate);
+}
+
+static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+	return prcmu_set_clock_rate(clk->cg_sel, rate);
+}
+
+static int request_ape_opp100(bool enable)
+{
+	static int reqs;
+	int err = 0;
+
+	if (enable) {
+		if (!reqs)
+			err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
+							"clock", 100);
+		if (!err)
+			reqs++;
+	} else {
+		reqs--;
+		if (!reqs)
+			prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
+						"clock");
+	}
+	return err;
+}
+
+static int clk_prcmu_opp_prepare(struct clk_hw *hw)
+{
+	int err;
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+	err = request_ape_opp100(true);
+	if (err) {
+		pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
+			__func__, hw->init->name);
+		return err;
+	}
+
+	err = prcmu_request_clock(clk->cg_sel, true);
+	if (err)
+		request_ape_opp100(false);
+
+	return err;
+}
+
+static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
+{
+	struct clk_prcmu *clk = to_clk_prcmu(hw);
+
+	if (prcmu_request_clock(clk->cg_sel, false))
+		goto out_error;
+	if (request_ape_opp100(false))
+		goto out_error;
+	return;
+
+out_error:
+	pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
+		hw->init->name);
+}
+
+static struct clk_ops clk_prcmu_scalable_ops = {
+	.prepare = clk_prcmu_prepare,
+	.unprepare = clk_prcmu_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+	.round_rate = clk_prcmu_round_rate,
+	.set_rate = clk_prcmu_set_rate,
+};
+
+static struct clk_ops clk_prcmu_gate_ops = {
+	.prepare = clk_prcmu_prepare,
+	.unprepare = clk_prcmu_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk_ops clk_prcmu_opp_gate_ops = {
+	.prepare = clk_prcmu_opp_prepare,
+	.unprepare = clk_prcmu_opp_unprepare,
+	.enable = clk_prcmu_enable,
+	.disable = clk_prcmu_disable,
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+};
+
+static struct clk *clk_reg_prcmu(const char *name,
+				 const char *parent_name,
+				 u8 cg_sel,
+				 unsigned long rate,
+				 unsigned long flags,
+				 struct clk_ops *clk_prcmu_ops)
+{
+	struct clk_prcmu *clk;
+	struct clk_init_data clk_prcmu_init;
+	struct clk *clk_reg;
+
+	if (!name) {
+		pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
+	if (!clk) {
+		pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	clk->cg_sel = cg_sel;
+	clk->is_enabled = 1;
+	/* "rate" can be used for changing the initial frequency */
+	if (rate)
+		prcmu_set_clock_rate(cg_sel, rate);
+
+	clk_prcmu_init.name = name;
+	clk_prcmu_init.ops = clk_prcmu_ops;
+	clk_prcmu_init.flags = flags;
+	clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
+	clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
+	clk->hw.init = &clk_prcmu_init;
+
+	clk_reg = clk_register(NULL, &clk->hw);
+	if (IS_ERR_OR_NULL(clk_reg))
+		goto free_clk;
+
+	return clk_reg;
+
+free_clk:
+	kfree(clk);
+	pr_err("clk_prcmu: %s failed to register clk\n", __func__);
+	return ERR_PTR(-ENOMEM);
+}
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long rate,
+				   unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
+			&clk_prcmu_scalable_ops);
+}
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+			&clk_prcmu_gate_ops);
+}
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+			&clk_prcmu_opp_gate_ops);
+}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
new file mode 100644
index 0000000..32085aa
--- /dev/null
+++ b/drivers/clk/ux500/clk.h
@@ -0,0 +1,43 @@
+/*
+ * Clocks for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __UX500_CLK_H
+#define __UX500_CLK_H
+
+#include <linux/clk.h>
+
+struct clk *clk_reg_prcc_pclk(const char *name,
+			      const char *parent_name,
+			      unsigned int phy_base,
+			      u32 cg_sel,
+			      unsigned long flags);
+
+struct clk *clk_reg_prcc_kclk(const char *name,
+			      const char *parent_name,
+			      unsigned int phy_base,
+			      u32 cg_sel,
+			      unsigned long flags);
+
+struct clk *clk_reg_prcmu_scalable(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long rate,
+				   unsigned long flags);
+
+struct clk *clk_reg_prcmu_gate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags);
+
+struct clk *clk_reg_prcmu_opp_gate(const char *name,
+				   const char *parent_name,
+				   u8 cg_sel,
+				   unsigned long flags);
+
+#endif /* __UX500_CLK_H */
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon Aug 27 09:45:53 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 Aug 2012 15:45:53 +0200
Subject: [PATCH V2 4/4] ARM: ux500: Switch to use common clock framework
In-Reply-To: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346075153-14180-5-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

Remove machine specific clock implementation and switch to use
new common clock framework.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 arch/arm/mach-ux500/Kconfig  |    1 +
 arch/arm/mach-ux500/Makefile |    2 +-
 arch/arm/mach-ux500/clock.c  |  715 ------------------------------------------
 arch/arm/mach-ux500/clock.h  |  164 ----------
 arch/arm/mach-ux500/cpu.c    |   14 +-
 drivers/clk/Makefile         |    1 +
 6 files changed, 11 insertions(+), 886 deletions(-)
 delete mode 100644 arch/arm/mach-ux500/clock.c
 delete mode 100644 arch/arm/mach-ux500/clock.h

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf..2d76e4f 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
 	select CACHE_L2X0
 	select PINCTRL
 	select PINCTRL_NOMADIK
+	select COMMON_CLK
 
 config UX500_SOC_DB8500
 	bool
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086f..5691ef6 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y				:= clock.o cpu.o devices.o devices-common.o \
+obj-y				:= cpu.o devices.o devices-common.o \
 				   id.o usb.o timer.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b06..0000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/cpufreq.h>
-
-#include <plat/mtu.h>
-#include <mach/hardware.h>
-#include "clock.h"
-
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include <linux/uaccess.h>	/* for copy_from_user */
-static LIST_HEAD(clk_list);
-#endif
-
-#define PRCC_PCKEN		0x00
-#define PRCC_PCKDIS		0x04
-#define PRCC_KCKEN		0x08
-#define PRCC_KCKDIS		0x0C
-
-#define PRCM_YYCLKEN0_MGT_SET	0x510
-#define PRCM_YYCLKEN1_MGT_SET	0x514
-#define PRCM_YYCLKEN0_MGT_CLR	0x518
-#define PRCM_YYCLKEN1_MGT_CLR	0x51C
-#define PRCM_YYCLKEN0_MGT_VAL	0x520
-#define PRCM_YYCLKEN1_MGT_VAL	0x524
-
-#define PRCM_SVAMMDSPCLK_MGT	0x008
-#define PRCM_SIAMMDSPCLK_MGT	0x00C
-#define PRCM_SGACLK_MGT		0x014
-#define PRCM_UARTCLK_MGT	0x018
-#define PRCM_MSP02CLK_MGT	0x01C
-#define PRCM_MSP1CLK_MGT	0x288
-#define PRCM_I2CCLK_MGT		0x020
-#define PRCM_SDMMCCLK_MGT	0x024
-#define PRCM_SLIMCLK_MGT	0x028
-#define PRCM_PER1CLK_MGT	0x02C
-#define PRCM_PER2CLK_MGT	0x030
-#define PRCM_PER3CLK_MGT	0x034
-#define PRCM_PER5CLK_MGT	0x038
-#define PRCM_PER6CLK_MGT	0x03C
-#define PRCM_PER7CLK_MGT	0x040
-#define PRCM_LCDCLK_MGT		0x044
-#define PRCM_BMLCLK_MGT		0x04C
-#define PRCM_HSITXCLK_MGT	0x050
-#define PRCM_HSIRXCLK_MGT	0x054
-#define PRCM_HDMICLK_MGT	0x058
-#define PRCM_APEATCLK_MGT	0x05C
-#define PRCM_APETRACECLK_MGT	0x060
-#define PRCM_MCDECLK_MGT	0x064
-#define PRCM_IPI2CCLK_MGT	0x068
-#define PRCM_DSIALTCLK_MGT	0x06C
-#define PRCM_DMACLK_MGT		0x074
-#define PRCM_B2R2CLK_MGT	0x078
-#define PRCM_TVCLK_MGT		0x07C
-#define PRCM_TCR		0x1C8
-#define PRCM_TCR_STOPPED	(1 << 16)
-#define PRCM_TCR_DOZE_MODE	(1 << 17)
-#define PRCM_UNIPROCLK_MGT	0x278
-#define PRCM_SSPCLK_MGT		0x280
-#define PRCM_RNGCLK_MGT		0x284
-#define PRCM_UICCCLK_MGT	0x27C
-
-#define PRCM_MGT_ENABLE		(1 << 8)
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (clk->enabled++ == 0) {
-		if (clk->parent_cluster)
-			__clk_enable(clk->parent_cluster);
-
-		if (clk->parent_periph)
-			__clk_enable(clk->parent_periph);
-
-		if (clk->ops && clk->ops->enable)
-			clk->ops->enable(clk);
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (--clk->enabled == 0) {
-		if (clk->ops && clk->ops->disable)
-			clk->ops->disable(clk);
-
-		if (clk->parent_periph)
-			__clk_disable(clk->parent_periph);
-
-		if (clk->parent_cluster)
-			__clk_disable(clk->parent_cluster);
-	}
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	WARN_ON(!clk->enabled);
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/*
- * The MTU has a separate, rather complex muxing setup
- * with alternative parents (peripheral cluster or
- * ULP or fixed 32768 Hz) depending on settings
- */
-static unsigned long clk_mtu_get_rate(struct clk *clk)
-{
-	void __iomem *addr;
-	u32 tcr;
-	int mtu = (int) clk->data;
-	/*
-	 * One of these is selected eventually
-	 * TODO: Replace the constant with a reference
-	 * to the ULP source once this is modeled.
-	 */
-	unsigned long clk32k = 32768;
-	unsigned long mturate;
-	unsigned long retclk;
-
-	if (cpu_is_u8500_family())
-		addr = __io_address(U8500_PRCMU_BASE);
-	else
-		ux500_unknown_soc();
-
-	/*
-	 * On a startup, always conifgure the TCR to the doze mode;
-	 * bootloaders do it for us. Do this in the kernel too.
-	 */
-	writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
-
-	tcr = readl(addr + PRCM_TCR);
-
-	/* Get the rate from the parent as a default */
-	if (clk->parent_periph)
-		mturate = clk_get_rate(clk->parent_periph);
-	else if (clk->parent_cluster)
-		mturate = clk_get_rate(clk->parent_cluster);
-	else
-		/* We need to be connected SOMEWHERE */
-		BUG();
-
-	/* Return the clock selected for this MTU */
-	if (tcr & (1 << mtu))
-		retclk = clk32k;
-	else
-		retclk = mturate;
-
-	pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
-	return retclk;
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long rate;
-
-	/*
-	 * If there is a custom getrate callback for this clock,
-	 * it will take precedence.
-	 */
-	if (clk->get_rate)
-		return clk->get_rate(clk);
-
-	if (clk->ops && clk->ops->get_rate)
-		return clk->ops->get_rate(clk);
-
-	rate = clk->rate;
-	if (!rate) {
-		if (clk->parent_periph)
-			rate = clk_get_rate(clk->parent_periph);
-		else if (clk->parent_cluster)
-			rate = clk_get_rate(clk->parent_cluster);
-	}
-
-	return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	/*TODO*/
-	return rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	clk->rate = rate;
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	/*TODO*/
-	return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-static void clk_prcmu_enable(struct clk *clk)
-{
-	void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
-				   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
-
-	writel(1 << clk->prcmu_cg_bit, cg_set_reg);
-}
-
-static void clk_prcmu_disable(struct clk *clk)
-{
-	void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
-				   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
-
-	writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
-}
-
-static struct clkops clk_prcmu_ops = {
-	.enable = clk_prcmu_enable,
-	.disable = clk_prcmu_disable,
-};
-
-static unsigned int clkrst_base[] = {
-	[1] = U8500_CLKRST1_BASE,
-	[2] = U8500_CLKRST2_BASE,
-	[3] = U8500_CLKRST3_BASE,
-	[5] = U8500_CLKRST5_BASE,
-	[6] = U8500_CLKRST6_BASE,
-};
-
-static void clk_prcc_enable(struct clk *clk)
-{
-	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-	if (clk->prcc_kernel != -1)
-		writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
-
-	if (clk->prcc_bus != -1)
-		writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
-}
-
-static void clk_prcc_disable(struct clk *clk)
-{
-	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
-
-	if (clk->prcc_bus != -1)
-		writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
-
-	if (clk->prcc_kernel != -1)
-		writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
-}
-
-static struct clkops clk_prcc_ops = {
-	.enable = clk_prcc_enable,
-	.disable = clk_prcc_disable,
-};
-
-static struct clk clk_32khz = {
-	.name =  "clk_32khz",
-	.rate = 32000,
-};
-
-/*
- * PRCMU level clock gating
- */
-
-/* Bank 0 */
-static DEFINE_PRCMU_CLK(svaclk,		0x0, 2, SVAMMDSPCLK);
-static DEFINE_PRCMU_CLK(siaclk,		0x0, 3, SIAMMDSPCLK);
-static DEFINE_PRCMU_CLK(sgaclk,		0x0, 4, SGACLK);
-static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
-static DEFINE_PRCMU_CLK(msp02clk,	0x0, 6, MSP02CLK);
-static DEFINE_PRCMU_CLK(msp1clk,	0x0, 7, MSP1CLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(i2cclk,	0x0, 8, I2CCLK, 48000000);
-static DEFINE_PRCMU_CLK_RATE(sdmmcclk,	0x0, 9, SDMMCCLK, 100000000);
-static DEFINE_PRCMU_CLK(slimclk,	0x0, 10, SLIMCLK);
-static DEFINE_PRCMU_CLK(per1clk,	0x0, 11, PER1CLK);
-static DEFINE_PRCMU_CLK(per2clk,	0x0, 12, PER2CLK);
-static DEFINE_PRCMU_CLK(per3clk,	0x0, 13, PER3CLK);
-static DEFINE_PRCMU_CLK(per5clk,	0x0, 14, PER5CLK);
-static DEFINE_PRCMU_CLK_RATE(per6clk,	0x0, 15, PER6CLK, 133330000);
-static DEFINE_PRCMU_CLK(lcdclk,		0x0, 17, LCDCLK);
-static DEFINE_PRCMU_CLK(bmlclk,		0x0, 18, BMLCLK);
-static DEFINE_PRCMU_CLK(hsitxclk,	0x0, 19, HSITXCLK);
-static DEFINE_PRCMU_CLK(hsirxclk,	0x0, 20, HSIRXCLK);
-static DEFINE_PRCMU_CLK(hdmiclk,	0x0, 21, HDMICLK);
-static DEFINE_PRCMU_CLK(apeatclk,	0x0, 22, APEATCLK);
-static DEFINE_PRCMU_CLK(apetraceclk,	0x0, 23, APETRACECLK);
-static DEFINE_PRCMU_CLK(mcdeclk,	0x0, 24, MCDECLK);
-static DEFINE_PRCMU_CLK(ipi2clk,	0x0, 25, IPI2CCLK);
-static DEFINE_PRCMU_CLK(dsialtclk,	0x0, 26, DSIALTCLK); /* v1 */
-static DEFINE_PRCMU_CLK(dmaclk,		0x0, 27, DMACLK);
-static DEFINE_PRCMU_CLK(b2r2clk,	0x0, 28, B2R2CLK);
-static DEFINE_PRCMU_CLK(tvclk,		0x0, 29, TVCLK);
-static DEFINE_PRCMU_CLK(uniproclk,	0x0, 30, UNIPROCLK); /* v1 */
-static DEFINE_PRCMU_CLK_RATE(sspclk,	0x0, 31, SSPCLK, 48000000); /* v1 */
-
-/* Bank 1 */
-static DEFINE_PRCMU_CLK(rngclk,		0x4, 0, RNGCLK); /* v1 */
-static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
-
-/*
- * PRCC level clock gating
- * Format: per#, clk, PCKEN bit, KCKEN bit, parent
- */
-
-/* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, msp3,		11, 10, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, i2c4,		10, 9, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, gpio0,	9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,	8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3,		7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,		6,  6, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, sdi0,		5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1,		4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,		3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,		2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,	1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,	0,  0, &clk_uartclk);
-
-/* Peripheral Cluster #2 */
-static DEFINE_PRCC_CLK(2, gpio1,	11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx,	10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx,	 9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0,		8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3,		7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1,		6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2,		5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4,		4,  2, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, pwl,		3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1,		2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2,		1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3,		0,  0, &clk_i2cclk);
-
-/* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,	8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,		7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,	6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,		5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,		4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,		3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1,		2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0,		1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,		0, -1, NULL);
-
-/* Peripheral Cluster #4 is in the always on domain */
-
-/* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,	1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb,		0,  0, NULL);
-
-/* Peripheral Cluster #6 */
-
-/* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg,	7,  7, NULL);
-static DEFINE_PRCC_CLK(6, hash1,	6, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro,	5,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, pka,		4, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,	3, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,	2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp1,    1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng,	0,  0, &clk_rngclk);
-
-static struct clk clk_dummy_apb_pclk = {
-	.name = "apb_pclk",
-};
-
-static struct clk_lookup u8500_clks[] = {
-	CLK(dummy_apb_pclk, NULL,	"apb_pclk"),
-
-	/* Peripheral Cluster #1 */
-	CLK(gpio0,	"gpio.0",	NULL),
-	CLK(gpio0,	"gpio.1",	NULL),
-	CLK(slimbus0,	"slimbus0",	NULL),
-	CLK(i2c2,	"nmk-i2c.2",	NULL),
-	CLK(sdi0,	"sdi0",		NULL),
-	CLK(msp0,	"ux500-msp-i2s.0",	NULL),
-	CLK(i2c1,	"nmk-i2c.1",	NULL),
-	CLK(uart1,	"uart1",	NULL),
-	CLK(uart0,	"uart0",	NULL),
-
-	/* Peripheral Cluster #3 */
-	CLK(gpio2,	"gpio.2",	NULL),
-	CLK(gpio2,	"gpio.3",	NULL),
-	CLK(gpio2,	"gpio.4",	NULL),
-	CLK(gpio2,	"gpio.5",	NULL),
-	CLK(sdi5,	"sdi5",		NULL),
-	CLK(uart2,	"uart2",	NULL),
-	CLK(ske,	"ske",		NULL),
-	CLK(ske,	"nmk-ske-keypad",	NULL),
-	CLK(sdi2,	"sdi2",		NULL),
-	CLK(i2c0,	"nmk-i2c.0",	NULL),
-	CLK(fsmc,	"fsmc",		NULL),
-
-	/* Peripheral Cluster #5 */
-	CLK(gpio3,	"gpio.8",	NULL),
-
-	/* Peripheral Cluster #6 */
-	CLK(hash1,	"hash1",	NULL),
-	CLK(pka,	"pka",		NULL),
-	CLK(hash0,	"hash0",	NULL),
-	CLK(cryp0,	"cryp0",	NULL),
-	CLK(cryp1,  "cryp1",    NULL),
-
-	/* PRCMU level clock gating */
-
-	/* Bank 0 */
-	CLK(svaclk,	"sva",		NULL),
-	CLK(siaclk,	"sia",		NULL),
-	CLK(sgaclk,	"sga",		NULL),
-	CLK(slimclk,	"slim",		NULL),
-	CLK(lcdclk,	"lcd",		NULL),
-	CLK(bmlclk,	"bml",		NULL),
-	CLK(hsitxclk,	"stm-hsi.0",	NULL),
-	CLK(hsirxclk,	"stm-hsi.1",	NULL),
-	CLK(hdmiclk,	"hdmi",		NULL),
-	CLK(apeatclk,	"apeat",	NULL),
-	CLK(apetraceclk,	"apetrace",	NULL),
-	CLK(mcdeclk,	"mcde",		NULL),
-	CLK(ipi2clk,	"ipi2",		NULL),
-	CLK(dmaclk,	"dma40.0",	NULL),
-	CLK(b2r2clk,	"b2r2",		NULL),
-	CLK(tvclk,	"tv",		NULL),
-
-	/* Peripheral Cluster #1 */
-	CLK(i2c4,	"nmk-i2c.4",	NULL),
-	CLK(spi3,	"spi3",		NULL),
-	CLK(msp1,	"ux500-msp-i2s.1",	NULL),
-	CLK(msp3,	"ux500-msp-i2s.3",	NULL),
-
-	/* Peripheral Cluster #2 */
-	CLK(gpio1,	"gpio.6",	NULL),
-	CLK(gpio1,	"gpio.7",	NULL),
-	CLK(ssitx,	"ssitx",	NULL),
-	CLK(ssirx,	"ssirx",	NULL),
-	CLK(spi0,	"spi0",		NULL),
-	CLK(sdi3,	"sdi3",		NULL),
-	CLK(sdi1,	"sdi1",		NULL),
-	CLK(msp2,	"ux500-msp-i2s.2",	NULL),
-	CLK(sdi4,	"sdi4",		NULL),
-	CLK(pwl,	"pwl",		NULL),
-	CLK(spi1,	"spi1",		NULL),
-	CLK(spi2,	"spi2",		NULL),
-	CLK(i2c3,	"nmk-i2c.3",	NULL),
-
-	/* Peripheral Cluster #3 */
-	CLK(ssp1,	"ssp1",		NULL),
-	CLK(ssp0,	"ssp0",		NULL),
-
-	/* Peripheral Cluster #5 */
-	CLK(usb,	"musb-ux500.0",	"usb"),
-
-	/* Peripheral Cluster #6 */
-	CLK(mtu1,	"mtu1",		NULL),
-	CLK(mtu0,	"mtu0",		NULL),
-	CLK(cfgreg,	"cfgreg",	NULL),
-	CLK(hash1,	"hash1",	NULL),
-	CLK(unipro,	"unipro",	NULL),
-	CLK(rng,	"rng",		NULL),
-
-	/* PRCMU level clock gating */
-
-	/* Bank 0 */
-	CLK(uniproclk,	"uniproclk",	NULL),
-	CLK(dsialtclk,	"dsialt",	NULL),
-
-	/* Bank 1 */
-	CLK(rngclk,	"rng",		NULL),
-	CLK(uiccclk,	"uicc",		NULL),
-};
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *	debugfs support to trace clock tree hierarchy and attributes with
- *	powerdebug
- */
-static struct dentry *clk_debugfs_root;
-
-void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
-{
-	while (num--) {
-		/* Check that the clock has not been already registered */
-		if (!(cl->clk->list.prev != cl->clk->list.next))
-			list_add_tail(&cl->clk->list, &clk_list);
-
-		cl++;
-	}
-}
-
-static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
-						  size_t size, loff_t *off)
-{
-	struct clk *clk = file->f_dentry->d_inode->i_private;
-	char cusecount[128];
-	unsigned int len;
-
-	len = sprintf(cusecount, "%u\n", clk->enabled);
-	return simple_read_from_buffer(buf, size, off, cusecount, len);
-}
-
-static ssize_t rate_dbg_read(struct file *file, char __user *buf,
-					  size_t size, loff_t *off)
-{
-	struct clk *clk = file->f_dentry->d_inode->i_private;
-	char crate[128];
-	unsigned int rate;
-	unsigned int len;
-
-	rate = clk_get_rate(clk);
-	len = sprintf(crate, "%u\n", rate);
-	return simple_read_from_buffer(buf, size, off, crate, len);
-}
-
-static const struct file_operations usecount_fops = {
-	.read = usecount_dbg_read,
-};
-
-static const struct file_operations set_rate_fops = {
-	.read = rate_dbg_read,
-};
-
-static struct dentry *clk_debugfs_register_dir(struct clk *c,
-						struct dentry *p_dentry)
-{
-	struct dentry *d, *clk_d;
-	const char *p = c->name;
-
-	if (!p)
-		p = "BUG";
-
-	clk_d = debugfs_create_dir(p, p_dentry);
-	if (!clk_d)
-		return NULL;
-
-	d = debugfs_create_file("usecount", S_IRUGO,
-				clk_d, c, &usecount_fops);
-	if (!d)
-		goto err_out;
-	d = debugfs_create_file("rate", S_IRUGO,
-				clk_d, c, &set_rate_fops);
-	if (!d)
-		goto err_out;
-	/*
-	 * TODO : not currently available in ux500
-	 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
-	 * if (!d)
-	 *	goto err_out;
-	 */
-
-	return clk_d;
-
-err_out:
-	debugfs_remove_recursive(clk_d);
-	return NULL;
-}
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-	struct clk *pa = c->parent_periph;
-	struct clk *bpa = c->parent_cluster;
-
-	if (!(bpa && !pa)) {
-		c->dent = clk_debugfs_register_dir(c,
-				pa ? pa->dent : clk_debugfs_root);
-		if (!c->dent)
-			return -ENOMEM;
-	}
-
-	if (bpa) {
-		c->dent_bus = clk_debugfs_register_dir(c,
-				bpa->dent_bus ? bpa->dent_bus : bpa->dent);
-		if ((!c->dent_bus) &&  (c->dent)) {
-			debugfs_remove_recursive(c->dent);
-			c->dent = NULL;
-			return -ENOMEM;
-		}
-	}
-	return 0;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-	int err;
-	struct clk *pa = c->parent_periph;
-	struct clk *bpa = c->parent_cluster;
-
-	if (pa && (!pa->dent && !pa->dent_bus)) {
-		err = clk_debugfs_register(pa);
-		if (err)
-			return err;
-	}
-
-	if (bpa && (!bpa->dent && !bpa->dent_bus)) {
-		err = clk_debugfs_register(bpa);
-		if (err)
-			return err;
-	}
-
-	if ((!c->dent) && (!c->dent_bus)) {
-		err = clk_debugfs_register_one(c);
-		if (err)
-			return err;
-	}
-	return 0;
-}
-
-int __init clk_debugfs_init(void)
-{
-	struct clk *c;
-	struct dentry *d;
-	int err;
-
-	d = debugfs_create_dir("clock", NULL);
-	if (!d)
-		return -ENOMEM;
-	clk_debugfs_root = d;
-
-	list_for_each_entry(c, &clk_list, list) {
-		err = clk_debugfs_register(c);
-		if (err)
-			goto err_out;
-	}
-	return 0;
-err_out:
-	debugfs_remove_recursive(clk_debugfs_root);
-	return err;
-}
-
-#endif /* defined(CONFIG_DEBUG_FS) */
-
-unsigned long clk_smp_twd_rate = 500000000;
-
-unsigned long clk_smp_twd_get_rate(struct clk *clk)
-{
-	return clk_smp_twd_rate;
-}
-
-static struct clk clk_smp_twd = {
-	.get_rate = clk_smp_twd_get_rate,
-	.name =  "smp_twd",
-};
-
-static struct clk_lookup clk_smp_twd_lookup = {
-	.dev_id = "smp_twd",
-	.clk = &clk_smp_twd,
-};
-
-#ifdef CONFIG_CPU_FREQ
-
-static int clk_twd_cpufreq_transition(struct notifier_block *nb,
-				      unsigned long state, void *data)
-{
-	struct cpufreq_freqs *f = data;
-
-	if (state == CPUFREQ_PRECHANGE) {
-		/* Save frequency in simple Hz */
-		clk_smp_twd_rate = (f->new * 1000) / 2;
-	}
-
-	return NOTIFY_OK;
-}
-
-static struct notifier_block clk_twd_cpufreq_nb = {
-	.notifier_call = clk_twd_cpufreq_transition,
-};
-
-int clk_init_smp_twd_cpufreq(void)
-{
-	return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
-				  CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-#endif
-
-int __init clk_init(void)
-{
-	clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-	clkdev_add(&clk_smp_twd_lookup);
-
-#ifdef CONFIG_DEBUG_FS
-	clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
-#endif
-	return 0;
-}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a1..0000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- *  Copyright (C) 2010 ST-Ericsson
- *  Copyright (C) 2009 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/**
- * struct clkops - ux500 clock operations
- * @enable:	function to enable the clock
- * @disable:	function to disable the clock
- * @get_rate:	function to get the current clock rate
- *
- * This structure contains function pointers to functions that will be used to
- * control the clock.  All of these functions are optional.  If get_rate is
- * NULL, the rate in the struct clk will be used.
- */
-struct clkops {
-	void (*enable) (struct clk *);
-	void (*disable) (struct clk *);
-	unsigned long (*get_rate) (struct clk *);
-	int (*set_parent)(struct clk *, struct clk *);
-};
-
-/**
- * struct clk - ux500 clock structure
- * @ops:		pointer to clkops struct used to control this clock
- * @name:		name, for debugging
- * @enabled:		refcount. positive if enabled, zero if disabled
- * @get_rate:		custom callback for getting the clock rate
- * @data:		custom per-clock data for example for the get_rate
- *			callback
- * @rate:		fixed rate for clocks which don't implement
- * 			ops->getrate
- * @prcmu_cg_off:	address offset of the combined enable/disable register
- * 			(used on u8500v1)
- * @prcmu_cg_bit:	bit in the combined enable/disable register (used on
- * 			u8500v1)
- * @prcmu_cg_mgt:	address of the enable/disable register (used on
- * 			u8500ed)
- * @cluster:		peripheral cluster number
- * @prcc_bus:		bit for the bus clock in the peripheral's CLKRST
- * @prcc_kernel:	bit for the kernel clock in the peripheral's CLKRST.
- * 			-1 if no kernel clock exists.
- * @parent_cluster:	pointer to parent's cluster clk struct
- * @parent_periph:	pointer to parent's peripheral clk struct
- *
- * Peripherals are organised into clusters, and each cluster has an associated
- * bus clock.  Some peripherals also have a parent peripheral clock.
- *
- * In order to enable a clock for a peripheral, we need to enable:
- * 	(1) the parent cluster (bus) clock at the PRCMU level
- * 	(2) the parent peripheral clock (if any) at the PRCMU level
- * 	(3) the peripheral's bus & kernel clock at the PRCC level
- *
- * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
- * of the cluster and peripheral clocks, and hooking these as the parents of
- * the individual peripheral clocks.
- *
- * (3) is handled by specifying the bits in the PRCC control registers required
- * to enable these clocks and modifying them in the ->enable and
- * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
- *
- * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
- * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
- * prcc, and parent pointers are only used for the PRCC-level clocks.
- */
-struct clk {
-	const struct clkops	*ops;
-	const char 		*name;
-	unsigned int		enabled;
-	unsigned long		(*get_rate)(struct clk *);
-	void			*data;
-
-	unsigned long		rate;
-	struct list_head	list;
-
-	/* These three are only for PRCMU clks */
-
-	unsigned int		prcmu_cg_off;
-	unsigned int		prcmu_cg_bit;
-	unsigned int		prcmu_cg_mgt;
-
-	/* The rest are only for PRCC clks */
-
-	int			cluster;
-	unsigned int		prcc_bus;
-	unsigned int		prcc_kernel;
-
-	struct clk		*parent_cluster;
-	struct clk		*parent_periph;
-#if defined(CONFIG_DEBUG_FS)
-	struct dentry		*dent;		/* For visible tree hierarchy */
-	struct dentry		*dent_bus;	/* For visible tree hierarchy */
-#endif
-};
-
-#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)		\
-struct clk clk_##_name = {					\
-		.name		= #_name,			\
-		.ops    	= &clk_prcmu_ops, 		\
-		.prcmu_cg_off	= _cg_off, 			\
-		.prcmu_cg_bit	= _cg_bit,			\
-		.prcmu_cg_mgt	= PRCM_##_reg##_MGT		\
-	}
-
-#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate)	\
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops    	= &clk_prcmu_ops, 			\
-		.prcmu_cg_off	= _cg_off, 				\
-		.prcmu_cg_bit	= _cg_bit,				\
-		.rate		= _rate,				\
-		.prcmu_cg_mgt	= PRCM_##_reg##_MGT			\
-	}
-
-#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk)	\
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops    	= &clk_prcc_ops, 			\
-		.cluster 	= _pclust,				\
-		.prcc_bus 	= _bus_en, 				\
-		.prcc_kernel 	= _kernel_en, 				\
-		.parent_cluster = &clk_per##_pclust##clk,		\
-		.parent_periph 	= _kernclk				\
-	}
-
-#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
-struct clk clk_##_name = {						\
-		.name		= #_name,				\
-		.ops		= &clk_prcc_ops,			\
-		.cluster	= _pclust,				\
-		.prcc_bus	= _bus_en,				\
-		.prcc_kernel	= _kernel_en,				\
-		.parent_cluster = &clk_per##_pclust##clk,		\
-		.parent_periph	= _kernclk,				\
-		.get_rate	= _callback,				\
-		.data		= (void *) _data			\
-	}
-
-
-#define CLK(_clk, _devname, _conname)			\
-	{						\
-		.clk	= &clk_##_clk,			\
-		.dev_id	= _devname,			\
-		.con_id = _conname,			\
-	}
-
-int __init clk_db8500_ed_fixup(void);
-int __init clk_init(void);
-
-#ifdef CONFIG_DEBUG_FS
-int clk_debugfs_init(void);
-#else
-static inline int clk_debugfs_init(void) { return 0; }
-#endif
-
-#ifdef CONFIG_CPU_FREQ
-int clk_init_smp_twd_cpufreq(void);
-#else
-static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
-#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 4b0a9b3..3d62c64 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
 #include <linux/stat.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/platform_data/clk-ux500.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -25,8 +25,6 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 
-#include "clock.h"
-
 void __iomem *_PRCMU_BASE;
 
 /*
@@ -70,13 +68,17 @@ void __init ux500_init_irq(void)
 	 */
 	if (cpu_is_u8500_family())
 		db8500_prcmu_early_init();
-	clk_init();
+
+	if (cpu_is_u8500_family())
+		u8500_clk_init();
+	else if (cpu_is_u9540())
+		u9540_clk_init();
+	else if (cpu_is_u8540())
+		u8540_clk_init();
 }
 
 void __init ux500_init_late(void)
 {
-	clk_debugfs_init();
-	clk_init_smp_twd_cpufreq();
 }
 
 static const char * __init ux500_get_machine(void)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..96df01b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
+obj-$(CONFIG_ARCH_U8500)	+= ux500/
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
 
 # Chip specific
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon Aug 27 09:45:52 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 Aug 2012 15:45:52 +0200
Subject: [PATCH V2 3/4] clk: ux500: Clock definitions for u8500
In-Reply-To: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346075153-14180-4-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

First version of clock definitions of PRCMU and PRCC clocks
for the u8500 platform.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/u8500_clk.c |  454 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 453 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 2bc4901..5c1fca1 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -17,5 +17,457 @@
 
 void u8500_clk_init(void)
 {
-	/* register clocks here */
+	struct prcmu_fw_version *fw_version;
+	const char *sgaclk_parent = NULL;
+	struct clk *clk;
+
+	/* Clock sources */
+	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc0_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "soc1_pll", NULL);
+
+	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, "ddr_pll", NULL);
+
+	/* FIXME: Add sys, ulp and int clocks here. */
+
+	clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
+				CLK_IS_ROOT|CLK_IGNORE_UNUSED,
+				32768);
+	clk_register_clkdev(clk, "clk32k", NULL);
+	clk_register_clkdev(clk, NULL, "rtc-pl031");
+
+	/* PRCMU clocks */
+	fw_version = prcmu_get_fw_version();
+	if (fw_version != NULL) {
+		switch (fw_version->project) {
+		case PRCMU_FW_PROJECT_U8500_C2:
+		case PRCMU_FW_PROJECT_U8520:
+		case PRCMU_FW_PROJECT_U8420:
+			sgaclk_parent = "soc0_pll";
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (sgaclk_parent)
+		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
+					PRCMU_SGACLK, 0);
+	else
+		clk = clk_reg_prcmu_gate("sgclk", NULL,
+					PRCMU_SGACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mali");
+
+	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "UART");
+
+	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "MSP02");
+
+	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "MSP1");
+
+	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "I2C");
+
+	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "slim");
+
+	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH1");
+
+	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH2");
+
+	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH3");
+
+	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH5");
+
+	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH6");
+
+	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "PERIPH7");
+
+	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "lcd");
+	clk_register_clkdev(clk, "lcd", "mcde");
+
+	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "bml");
+
+	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "hdmi");
+	clk_register_clkdev(clk, "hdmi", "mcde");
+
+	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apeat");
+
+	clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "apetrace");
+
+	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mcde");
+	clk_register_clkdev(clk, "mcde", "mcde");
+	clk_register_clkdev(clk, "dsisys", "dsilink.0");
+	clk_register_clkdev(clk, "dsisys", "dsilink.1");
+	clk_register_clkdev(clk, "dsisys", "dsilink.2");
+
+	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "ipi2");
+
+	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
+				CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dsialt");
+
+	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "dma40.0");
+
+	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "b2r2");
+	clk_register_clkdev(clk, NULL, "b2r2_core");
+	clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
+
+	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
+				CLK_IS_ROOT|CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "tv");
+	clk_register_clkdev(clk, "tv", "mcde");
+
+	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "SSP");
+
+	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "rngclk");
+
+	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "uicc");
+
+	/*
+	 * FIXME: The MTU clocks might need some kind of "parent muxed join"
+	 * and these have no K-clocks. For now, we ignore the missing
+	 * connection to the corresponding P-clocks, p6_mtu0_clk and
+	 * p6_mtu1_clk. Instead timclk is used which is the valid parent.
+	 */
+	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "mtu0");
+	clk_register_clkdev(clk, NULL, "mtu1");
+
+	clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
+	clk_register_clkdev(clk, NULL, "sdmmc");
+
+
+	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
+				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs2", "mcde");
+	clk_register_clkdev(clk, "dsihs2", "dsilink.2");
+
+
+	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
+				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs0", "mcde");
+	clk_register_clkdev(clk, "dsihs0", "dsilink.0");
+
+	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
+				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsihs1", "mcde");
+	clk_register_clkdev(clk, "dsihs1", "dsilink.1");
+
+	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
+				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp0", "dsilink.0");
+	clk_register_clkdev(clk, "dsilp0", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
+				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp1", "dsilink.1");
+	clk_register_clkdev(clk, "dsilp1", "mcde");
+
+	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
+				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, "dsilp2", "dsilink.2");
+	clk_register_clkdev(clk, "dsilp2", "mcde");
+
+	/*
+	 * FIXME: Add special handled PRCMU clocks here:
+	 * 1. smp_twd, use PRCMU_ARMSS.
+	 * 2. clk_arm, use PRCMU_ARMCLK.
+	 * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
+	 * 4. ab9540_clkout1yuv, see clkout0yuv
+	 */
+
+	/* PRCC P-clocks */
+	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart1");
+
+	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
+				BIT(2), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
+				BIT(3), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
+				BIT(4), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
+				BIT(5), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
+				BIT(6), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, NULL, "spi3");
+
+	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
+				BIT(8), 0);
+
+	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
+				BIT(9), 0);
+	clk_register_clkdev(clk, NULL, "gpio.0");
+	clk_register_clkdev(clk, NULL, "gpio.1");
+	clk_register_clkdev(clk, NULL, "gpioblock0");
+
+	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
+				BIT(10), 0);
+	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
+				BIT(11), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
+				BIT(0), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "spi2");
+
+	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "spi1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pwl");
+
+	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi4");
+
+	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
+				BIT(5), 0);
+
+	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi1");
+
+
+	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi3");
+
+	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "spi0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
+				BIT(9), 0);
+	clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
+				BIT(10), 0);
+	clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
+
+	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
+				BIT(11), 0);
+	clk_register_clkdev(clk, NULL, "gpio.6");
+	clk_register_clkdev(clk, NULL, "gpio.7");
+	clk_register_clkdev(clk, NULL, "gpioblock1");
+
+	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+				BIT(11), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, NULL, "fsmc");
+
+	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+				BIT(1), 0);
+	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
+				BIT(2), 0);
+	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
+				BIT(3), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
+				BIT(5), 0);
+
+	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
+				BIT(6), 0);
+	clk_register_clkdev(clk, "apb_pclk", "uart2");
+
+	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
+				BIT(7), 0);
+	clk_register_clkdev(clk, "apb_pclk", "sdi5");
+
+	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
+				BIT(8), 0);
+	clk_register_clkdev(clk, NULL, "gpio.2");
+	clk_register_clkdev(clk, NULL, "gpio.3");
+	clk_register_clkdev(clk, NULL, "gpio.4");
+	clk_register_clkdev(clk, NULL, "gpio.5");
+	clk_register_clkdev(clk, NULL, "gpioblock2");
+
+	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
+				BIT(0), 0);
+	clk_register_clkdev(clk, "usb", "musb-ux500.0");
+
+	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "gpio.8");
+	clk_register_clkdev(clk, NULL, "gpioblock3");
+
+	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
+				BIT(0), 0);
+
+	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
+				BIT(1), 0);
+	clk_register_clkdev(clk, NULL, "cryp0");
+	clk_register_clkdev(clk, NULL, "cryp1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
+				BIT(2), 0);
+	clk_register_clkdev(clk, NULL, "hash0");
+
+	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
+				BIT(3), 0);
+	clk_register_clkdev(clk, NULL, "pka");
+
+	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
+				BIT(4), 0);
+	clk_register_clkdev(clk, NULL, "hash1");
+
+	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
+				BIT(5), 0);
+	clk_register_clkdev(clk, NULL, "cfgreg");
+
+	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
+				BIT(6), 0);
+	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
+				BIT(7), 0);
+
+	/* PRCC K-clocks
+	 *
+	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
+	 * by enabling just the K-clock, even if it is not a valid parent to
+	 * the K-clock. Until drivers get fixed we might need some kind of
+	 * "parent muxed join".
+	 */
+
+	/* Periph1 */
+	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
+			U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart0");
+
+	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
+			U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart1");
+
+	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
+			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
+			U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
+			U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi0");
+
+	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
+			U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
+	/* FIXME: Redefinition of BIT(3). */
+	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
+			U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
+			U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
+
+	/* Periph2 */
+	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
+			U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi4");
+
+	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
+			U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi1");
+
+	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
+			U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi3");
+
+	/* Note that rate is received from parent. */
+	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
+			U8500_CLKRST2_BASE, BIT(6),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
+			U8500_CLKRST2_BASE, BIT(7),
+			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
+
+	/* Periph3 */
+	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
+			U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
+			U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
+	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
+			U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
+			U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi2");
+
+	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
+			U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
+
+	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
+			U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "uart2");
+
+	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
+			U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
+	clk_register_clkdev(clk, NULL, "sdi5");
+
+	/* Periph6 */
+	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
+			U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
+
 }
-- 
1.7.10



From ulf.hansson at stericsson.com  Mon Aug 27 09:45:51 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Mon, 27 Aug 2012 15:45:51 +0200
Subject: [PATCH V2 2/4] clk: ux500: First version of clock definitions for
 ux500
In-Reply-To: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346075153-14180-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

In this first version of the clock definitions, the structure for
ux500 are set. Support for u8500, u9540 and u8540 are prepared.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/Makefile              |    5 +++++
 drivers/clk/ux500/u8500_clk.c           |   21 +++++++++++++++++++++
 drivers/clk/ux500/u8540_clk.c           |   21 +++++++++++++++++++++
 drivers/clk/ux500/u9540_clk.c           |   21 +++++++++++++++++++++
 include/linux/platform_data/clk-ux500.h |   17 +++++++++++++++++
 5 files changed, 85 insertions(+)
 create mode 100644 drivers/clk/ux500/u8500_clk.c
 create mode 100644 drivers/clk/ux500/u8540_clk.c
 create mode 100644 drivers/clk/ux500/u9540_clk.c
 create mode 100644 include/linux/platform_data/clk-ux500.h

diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index a3ccd1b..858fbfe 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -5,3 +5,8 @@
 # Clock types
 obj-y += clk-prcc.o
 obj-y += clk-prcmu.o
+
+# Clock definitions
+obj-y += u8500_clk.o
+obj-y += u9540_clk.o
+obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
new file mode 100644
index 0000000..2bc4901
--- /dev/null
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u8500 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8500_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
new file mode 100644
index 0000000..10adfd2
--- /dev/null
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u8540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u8540_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
new file mode 100644
index 0000000..dbc0191
--- /dev/null
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -0,0 +1,21 @@
+/*
+ * Clock definitions for u9540 platform.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/clk-ux500.h>
+
+#include "clk.h"
+
+void u9540_clk_init(void)
+{
+	/* register clocks here */
+}
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
new file mode 100644
index 0000000..3af0da1
--- /dev/null
+++ b/include/linux/platform_data/clk-ux500.h
@@ -0,0 +1,17 @@
+/*
+ * Clock definitions for ux500 platforms
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Author: Ulf Hansson <ulf.hansson at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __CLK_UX500_H
+#define __CLK_UX500_H
+
+void u8500_clk_init(void);
+void u9540_clk_init(void);
+void u8540_clk_init(void);
+
+#endif /* __CLK_UX500_H */
-- 
1.7.10



From ludovic.desroches at atmel.com  Mon Aug 27 10:00:14 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Mon, 27 Aug 2012 16:00:14 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>,
 <503B623C.4030304@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>
 <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>
Message-ID: <503B7D6E.7090906@atmel.com>

Le 08/27/2012 03:32 PM, Voss, Nikolaus a ?crit :
> Hi Adian,
>
> Yanes Martinez Adrian wrote on Monday, August 27, 2012 2:46 PM:
>> Le 08/27/2012 12:40 PM, Yanes Martinez Adrian a ?crit :
>>> Hi Ludovic,
>>>
>>>> Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>>>> eeprom, temperature sensor and rtc devices (and wolfson chip for
>>>> sam9g20).
>>>
>>> concerning the at91rm9200, what was the amount of bytes you
>> transmitted?
>>>
>>
>>> I have only checked that I can communicate with i2c devices so the
>>> amount is very low (1-4 bytes).
>>
>> IIRC it was from >7 bytes when the issues appeared.
>>
>>> Some months ago I performed some testing[1] with the previous version of
>>> the patch and the main conclusion was that the absence of PDC in the
>>> AT91RM9200 made this driver unusable in such platform.
>
> I didn't get your last post  in that thread. In my opinion RM9200 should really
> be excluded from being configured with this driver, what's your opinion
> Ludovic?

Yes, the use of the TWI controller may be removed for some chips since 
there are issues that are dependent on the controller itself. RM9200 is 
not the only one.

For the moment, I don't have the necessary knowledge about the TWI 
controller to take a decision. I would say it can be done in an other 
patch in order to have your driver included in the mainline quickly 
since it doesn't introduce a breakage.

Regards

Ludovic

>
> Regards,
> Niko
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>



From afzal at ti.com  Mon Aug 27 10:01:00 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 27 Aug 2012 14:01:00 +0000
Subject: [PATCH v6 00/10] OMAP-GPMC: generic time calc, prepare for driver
In-Reply-To: <503B7678.90308@gmail.com>
References: <cover.1345524670.git.afzal@ti.com> <503B6511.4050909@gmail.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9BA713@DBDE01.ent.ti.com>
 <503B7678.90308@gmail.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9BA7DA@DBDE01.ent.ti.com>

Hi Daniel,

On Mon, Aug 27, 2012 at 19:00:32, Daniel Mack wrote:

> So the GPMC driver is the one that is matched from DT, and the NAND
> driver will the be instanciated from the (generic) GPMC driver?

I think you were referring to nand device being instantiated from
gpmc driver?, hence resulting in nand driver getting probed. What I
have in mind is to represent peripherals connected to gpmc as childs
of gpmc node. For devices like smsc911x, as they already have DT
bindings, creating an of device for childs by parsing DT hopefully
should relieve task of handling their platform data.

Similarly for nand, creating an of device is to be done by gpmc
driver.

Once the bigger issue of timing is resolved, I am planning to
implement DT as said above

Also for the existing boards on non-DT boot, plan is to keep the
existing interface as such, with no change needed in board files.

> 
> > No change would be needed for client drivers like smc91x ethernet drivers,
> > but NAND driver may need some change to live with DT as it is tightly
> > coupled with GPMC.
> 
> NAND drivers also typically parse partition entries that are children of
> the DT node the are owning.

Yes, in addition to the above, omap nand driver would need to determine a
few gpmc specific like transfer mode.

> I do have a beaglboard xM, but the board I'm currently working with is a
> custom one based on an AM33xx.

I was in need of a board like rx51, n800 that currently calculate gpmc
timings at runtime to test the generic timing function, np, thanks again

Regards
Afzal


From N.Voss at weinmann.de  Mon Aug 27 10:29:47 2012
From: N.Voss at weinmann.de (Voss, Nikolaus)
Date: Mon, 27 Aug 2012 16:29:47 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <503B7D6E.7090906@atmel.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>,
 <503B623C.4030304@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>
 <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>
 <503B7D6E.7090906@atmel.com>
Message-ID: <EF2E73589CA71846A15D0B2CDF79505D090EC3D747@wm021.weinmann.com>

ludovic.desroches wrote on Monday, August 27, 2012 4:00 PM :
> For the moment, I don't have the necessary knowledge about the TWI
> controller to take a decision. I would say it can be done in an other
> patch in order to have your driver included in the mainline quickly
> since it doesn't introduce a breakage.

That would be the most pragmatic approach.
Wolfram, is the anything left to do from my side?

Regards,
Niko
 


From eric at eukrea.com  Mon Aug 27 10:30:06 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Mon, 27 Aug 2012 16:30:06 +0200
Subject: [PATCH] dma: imx-dma: Fix kernel crash due to missing clock
 conversion
In-Reply-To: <1341341045-9472-1-git-send-email-fabio.estevam@freescale.com>
References: <1341341045-9472-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120827163006.0cffd20c@eb-e6520>

Hi Greg, Hi Fabio,

this patch went into 3.4.10 as commit
9ea2c02bafe276e97b592a046ac733610a6d57fd
which seems wrong as devm_clk_get seems to be added in linux-3.5 so
compiling a 3.4.10 kernel with imx-dma enabled now leads :

drivers/dma/imx-dma.c: In function 'imxdma_probe':
drivers/dma/imx-dma.c:980: error: implicit declaration of function
'devm_clk_get'
drivers/dma/imx-dma.c:980: warning: assignment makes pointer from
integer without a cast
drivers/dma/imx-dma.c:986: warning: assignment makes pointer from
integer without a cast

Reverting 9ea2c02bafe276e97b592a046ac733610a6d57fd allows to get a
3.4.10 kernel running fine on an i.MX35.

Best regards
Eric

Le Tue, 3 Jul 2012 15:44:04-0300, Fabio Estevam
<fabio.estevam at freescale.com> a ?crit :

> From: Fabio Estevam <festevam at gmail.com>
> 
> With the new i.MX clock infrastructure we need to request the dma clocks
> seperately: ahb and ipg clocks.
> 
> This fixes the following kernel crash and make audio to be functional again:
> 
> root at freescale /home$ aplay audio48k16S.wav 
> Playing WAVE 'audio48k16S.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
> Unable to handle kernel NULL pointer dereference at virtual address 00000000
> pgd = c7b74000
> [00000000] *pgd=a7bb5831, *pte=00000000, *ppte=00000000
> Internal error: Oops: 17 [#1] PREEMPT ARM
> Modules linked in:
> CPU: 0    Not tainted  (3.5.0-rc5-next-20120702-00007-g3028b64 #1128)
> PC is at snd_dmaengine_pcm_get_chan+0x8/0x10
> LR is at snd_imx_pcm_hw_params+0x18/0xdc
> pc : [<c02d3cf8>]    lr : [<c02e95ec>]    psr: a0000013
> sp : c7b45e30  ip : ffffffff  fp : c7ae58e0
> r10: 00000000  r9 : c7ae981c  r8 : c7b88800
> r7 : c7ae5a60  r6 : c7ae5b20  r5 : c7ae9810  r4 : c7afa060
> r3 : 00000000  r2 : 00000001  r1 : c7b88800  r0 : c7afa060
> Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
> Control: 0005317f  Table: a7b74000  DAC: 00000015
> Process aplay (pid: 701, stack limit = 0xc7b44270)
> Stack: (0xc7b45e30 to 0xc7b46000)
> 5e20:                                     00100000 00000029 c7b88800 c02db870
> 5e40: c7ae5a60 c02d4594 00000010 01ae5a60 c7ae5a60 c7ae9810 c7ae9810 c7afa060
> 5e60: c7ae5b20 c7ae5a60 c7b88800 c02e3ef0 c02e3e08 c7b1e400 c7afa060 c7b88800
> 5e80: 00000000 c0014da8 c7b44000 00000000 bec566ac c02cd400 c7afa060 c7afa060
> 5ea0: bec56800 c7b88800 c0014da8 c02cdd7c c04ee710 c04ee7b8 00000003 c005fc74
> 5ec0: 00000000 7fffffff c7b45f00 c7afa060 c7b67420 c7ba3070 00000004 c0014da8
> 5ee0: c7b44000 00000000 bec566ac c02ced88 c04e95f8 b6f5ab04 c7b45fb0 0145a468
> 5f00: 0145a600 bec566bc bec56800 c7b67420 c7ba3070 c00d499c c7b45f18 c7b45f18
> 5f20: 0000001a 00000004 00000001 c7b44000 c0527f40 00000009 00000008 00000000
> 5f40: c7b44000 c002c9ec 00000001 c04f0ab0 c04ebec0 00000101 00000000 0000000a
> 5f60: 60000093 c7b67420 bec56800 c25c4111 00000004 c0014da8 c7b44000 00000000
> 5f80: bec566ac c00d4f38 b6ffb658 00000000 c0522d80 0145a468 b6fd5000 0145a418
> 5fa0: 00000036 c0014c00 0145a468 b6fd5000 00000004 c25c4111 bec56800 00020001
> 5fc0: 0145a468 b6fd5000 0145a418 00000036 0145a468 0145a600 bec566bc bec566ac
> 5fe0: 0145a468 bec56388 b6f65ce4 b6dcebec 20000010 00000004 00000000 00000000
> [<c02d3cf8>] (snd_dmaengine_pcm_get_chan+0x8/0x10) from [<c02e95ec>] (snd_imx_pcm_hw_params+0x18/0xdc)
> [<c02e95ec>] (snd_imx_pcm_hw_params+0x18/0xdc) from [<c02e3ef0>] (soc_pcm_hw_params+0xe8/0x1f0)
> [<c02e3ef0>] (soc_pcm_hw_params+0xe8/0x1f0) from [<c02cd400>] (snd_pcm_hw_params+0x124/0x474)
> [<c02cd400>] (snd_pcm_hw_params+0x124/0x474) from [<c02cdd7c>] (snd_pcm_common_ioctl1+0x4b4/0xf74)
> [<c02cdd7c>] (snd_pcm_common_ioctl1+0x4b4/0xf74) from [<c02ced88>] (snd_pcm_playback_ioctl1+0x30/0x510)
> [<c02ced88>] (snd_pcm_playback_ioctl1+0x30/0x510) from [<c00d499c>] (do_vfs_ioctl+0x80/0x5e4)
> [<c00d499c>] (do_vfs_ioctl+0x80/0x5e4) from [<c00d4f38>] (sys_ioctl+0x38/0x60)
> [<c00d4f38>] (sys_ioctl+0x38/0x60) from [<c0014c00>] (ret_fast_syscall+0x0/0x2c)
> Code: e593000c e12fff1e e59030a0 e59330bc (e5930000) 
> ---[ end trace fa518c8ba3a74e97 ]--
> 
> Reported-by: Javier Martin <javier.martin at vista-silicon.com>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  drivers/dma/imx-dma.c |   36 +++++++++++++++++++++++++-----------
>  1 files changed, 25 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index fcfeb3c..5084975 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -172,7 +172,8 @@ struct imxdma_engine {
>  	struct device_dma_parameters	dma_parms;
>  	struct dma_device		dma_device;
>  	void __iomem			*base;
> -	struct clk			*dma_clk;
> +	struct clk			*dma_ahb;
> +	struct clk			*dma_ipg;
>  	spinlock_t			lock;
>  	struct imx_dma_2d_config	slots_2d[IMX_DMA_2D_SLOTS];
>  	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
> @@ -976,10 +977,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
>  		return 0;
>  	}
>  
> -	imxdma->dma_clk = clk_get(NULL, "dma");
> -	if (IS_ERR(imxdma->dma_clk))
> -		return PTR_ERR(imxdma->dma_clk);
> -	clk_enable(imxdma->dma_clk);
> +	imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
> +	if (IS_ERR(imxdma->dma_ipg)) {
> +		ret = PTR_ERR(imxdma->dma_ipg);
> +		goto err_clk;
> +	}
> +
> +	imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
> +	if (IS_ERR(imxdma->dma_ahb)) {
> +		ret = PTR_ERR(imxdma->dma_ahb);
> +		goto err_clk;
> +	}
> +
> +	clk_prepare_enable(imxdma->dma_ipg);
> +	clk_prepare_enable(imxdma->dma_ahb);
>  
>  	/* reset DMA module */
>  	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
> @@ -988,16 +999,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
>  		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
>  		if (ret) {
>  			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
> -			kfree(imxdma);
> -			return ret;
> +			goto err_enable;
>  		}
>  
>  		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
>  		if (ret) {
>  			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
>  			free_irq(MX1_DMA_INT, NULL);
> -			kfree(imxdma);
> -			return ret;
> +			goto err_enable;
>  		}
>  	}
>  
> @@ -1094,7 +1103,10 @@ err_init:
>  		free_irq(MX1_DMA_INT, NULL);
>  		free_irq(MX1_DMA_ERR, NULL);
>  	}
> -
> +err_enable:
> +	clk_disable_unprepare(imxdma->dma_ipg);
> +	clk_disable_unprepare(imxdma->dma_ahb);
> +err_clk:
>  	kfree(imxdma);
>  	return ret;
>  }
> @@ -1114,7 +1126,9 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>  		free_irq(MX1_DMA_ERR, NULL);
>  	}
>  
> -        kfree(imxdma);
> +	clk_disable_unprepare(imxdma->dma_ipg);
> +	clk_disable_unprepare(imxdma->dma_ahb);
> +	kfree(imxdma);
>  
>          return 0;
>  }



From zonque at gmail.com  Mon Aug 27 11:33:19 2012
From: zonque at gmail.com (Daniel Mack)
Date: Mon, 27 Aug 2012 17:33:19 +0200
Subject: [PATCH v3 0/3] DaVinci DMA engine conversion
In-Reply-To: <1345684176-21472-1-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
Message-ID: <503B933F.2030803@gmail.com>

Hi Matt,

On 23.08.2012 03:09, Matt Porter wrote:
> This series begins the conversion of the DaVinci private EDMA API
> implementation to a DMA engine driver and converts two of the three
> in-kernel users of the private EDMA API to DMA engine.
> 
> The approach taken is similar to the recent OMAP DMA Engine
> conversion. The EDMA DMA Engine driver is a wrapper around the existing
> private EDMA implementation and registers the platform device within
> the driver.  This allows the conversion series to stand alone with just
> the drivers and no changes to platform code. It also allows peripheral
> drivers to continue to use the private EDMA implementation until they
> are converted.
> 
> The EDMA DMA Engine driver supports slave transfers only at this time. It
> is planned to add cyclic transfers in support of audio peripherals.
> 
> There are three users of the private EDMA API in the kernel now:
> davinci_mmc, spi-davinci, and davinci-mcasp.  This series provides DMA
> Engine conversions for the davinci_mmc and spi-davinci drivers which
> use the supported slave transfers.
> 
> This series has been tested on an AM18x EVM and Hawkboard with
> driver performance comparable to that of the private EDMA API
> implementations. Both MMC0 and MMC1 are tested which handles the
> DA850/OMAP-L138/AM18x specific case where MMC1 uses DMA channels on
> a second EDMA channel controller.  All other platforms have a simpler
> design with just a single EDMA channel controller.
> 
> For those wanting to easily test this series, I've pushed a branch for
> each version to my github tree at https://github.com/ohporter/linux. The
> current branch is edma-dmaengine-v3.
> 
> After this series, the current plan is to complete the mcasp driver
> conversion which includes adding cyclic dma support. This will then
> enable the removal and refactoring of the private EDMA API functionality
> into the EDMA DMA Engine driver.  Since EDMA is also used on the AM33xx
> family of parts in mach-omap2/, the plan is to enable this driver on
> that platform as well.

Once you have a patch for the McASP driver conversion, I can happily
test this on a AM33xx board, together with Gururaja's latest McASP
refactoring series. Let me know how I can help you here.


Thanks,
Daniel



From shachimi at adeneo-embedded.com  Mon Aug 27 11:34:30 2012
From: shachimi at adeneo-embedded.com (HACHIMI Samir)
Date: Mon, 27 Aug 2012 17:34:30 +0200
Subject: [PATCH v2 0/2] imx6q: pwm: Activate stop_mode and configure pinmux
Message-ID: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFC@frontmail.adetel.com>

From: Samir Hachimi <shachimi at adeneo-embedded.com>

This patch series enables support for pwm driver on imx6q SoC. The first
patch of the series configure the pinctrl for pwm in device-tree. Actually
they are several pin who can be set to pwmO for each pwm, so I assume that
all of them must be enabled when configuring pin.
The second patch activate stop_enable mode and unset the enable bit during
configuration of pwm, and set the enable bit in pwm CR register during enable.

Changes since v1:
Remove default pwm pinmux configuration in DT as Shawn and Matt suggested.
Now, pwm used pwm's clocks properties to configure pwm's clock.
Need Shawn's patch '[PATCH v2 0/4] Move imx6q/28/23 clock lookup over to device tree' to work.
Use Beno??t's '[PATCH] pwm-imx: Fix config / enable / disable' (un)setting the cr enable bit to enable/disable pwm.
The second patch used driver_data instead of cpu_is_xxx macros, to check used architecture and enabled stop_enable mode.


Samir Hachimi (2):
  Add clock look-up for pwm.
  Enable Stop_enable mode during configuration of pwm.

 arch/arm/boot/dts/imx6q.dtsi |   68 ++++++++++++++++++++++++++++++++++++++++++
 drivers/pwm/pwm-imx.c        |   59 ++++++++++++++++++++++++++----------
 2 files changed, 111 insertions(+), 16 deletions(-)


From shachimi at adeneo-embedded.com  Mon Aug 27 11:34:31 2012
From: shachimi at adeneo-embedded.com (HACHIMI Samir)
Date: Mon, 27 Aug 2012 17:34:31 +0200
Subject: [PATCH v2 1/2] imx6q: pwm: Add device tree support
In-Reply-To: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
References: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
Message-ID: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFD@frontmail.adetel.com>

From: Samir Hachimi <shachimi at adeneo-embedded.com>

 Add clock look-up for pwm.
 Add the pinmux support for pwm.
 Several pin can be set to PwmO for the same Pwm.

Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   68 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 925da33..346ae9c 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -268,23 +268,43 @@
 			};
 
 			pwm at 02080000 { /* PWM1 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				reg = <0x02080000 0x4000>;
 				interrupts = <0 83 0x04>;
+				clocks = <&clks 145>;
+				clock-names = "pwm";
+				status = "disabled";
 			};
 
 			pwm at 02084000 { /* PWM2 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				reg = <0x02084000 0x4000>;
 				interrupts = <0 84 0x04>;
+				clocks = <&clks 146>;
+				clock-names = "pwm";
+				status = "disabled";
 			};
 
 			pwm at 02088000 { /* PWM3 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				reg = <0x02088000 0x4000>;
 				interrupts = <0 85 0x04>;
+				clocks = <&clks 147>;
+				clock-names = "pwm";
+				status = "disabled";
 			};
 
 			pwm at 0208c000 { /* PWM4 */
+				compatible = "fsl,imx6q-pwm";
+				#pwm-cells = <2>;
 				reg = <0x0208c000 0x4000>;
 				interrupts = <0 86 0x04>;
+				clocks = <&clks 148>;
+				clock-names = "pwm";
+				status = "disabled";
 			};
 
 			flexcan at 02090000 { /* CAN1 */
@@ -584,6 +604,54 @@
 					};
 				};
 
+				pwm1 {
+				     	pinctrl_pwm1_1: pwm1grp-1 {
+						fsl,pins = <1543 0x80000000>;	/* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
+					};
+
+				     	pinctrl_pwm1_2: pwm1grp-2 {
+						fsl,pins = <971 0x80000000>;	/* MX6Q_PAD_GPIO_9__PWM1_PWMO */
+					};
+
+				     	pinctrl_pwm1_3: pwm1grp-3 {
+						fsl,pins = <574 0x80000000>;	/* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
+					};
+				};
+
+				pwm2 {
+				     	pinctrl_pwm2_1: pwm2grp-1 {
+						fsl,pins = <1557 0x80000000>;	/* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
+					};
+
+				     	pinctrl_pwm2_2: pwm2grp-2 {
+						fsl,pins = <963 0x80000000>;	/* MX6Q_PAD_GPIO_1__PWM2_PWMO */
+					};
+
+				     	pinctrl_pwm2_3: pwm2grp-3 {
+						fsl,pins = <582 0x80000000>;	/* MX6Q_PAD_DISP0_DAT8__PWM2_PWMO */
+					};
+				};
+
+				pwm3 {
+				     	pinctrl_pwm3_1: pwm3grp-1 {
+						fsl,pins = <1471 0x80000000>;	/* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
+					};
+
+				     	pinctrl_pwm3_2: pwm3grp-2 {
+						fsl,pins = <1526 0x80000000>;	/* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
+					};
+				};
+
+				pwm4 {
+				     	pinctrl_pwm4_1: pwm4grp-1 {
+						fsl,pins = <1479 0x80000000>;	/* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
+					};
+
+				     	pinctrl_pwm4_2: pwm4grp-2 {
+						fsl,pins = <1550 0x80000000>;	/* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
+					};
+				};
+
 				usdhc3 {
 					pinctrl_usdhc3_1: usdhc3grp-1 {
 						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-- 
1.7.1


From shachimi at adeneo-embedded.com  Mon Aug 27 11:34:32 2012
From: shachimi at adeneo-embedded.com (HACHIMI Samir)
Date: Mon, 27 Aug 2012 17:34:32 +0200
Subject: [PATCH v2 2/2] Enable Stop_enable mode during configuration of pwm.
In-Reply-To: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
References: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
Message-ID: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFE@frontmail.adetel.com>

From: Samir Hachimi <shachimi at adeneo-embedded.com>

 Enable Stop_enable mode during configuration of pwm.
 Check architecture by looking in driver_data instead of cpu_is_xxx.

Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
---
 drivers/pwm/pwm-imx.c |   59 +++++++++++++++++++++++++++++++++++-------------
 1 files changed, 43 insertions(+), 16 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 0519bf2..7df919f 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -32,6 +32,7 @@
 #define MX3_PWMSAR                0x0C    /* PWM Sample Register */
 #define MX3_PWMPR                 0x10    /* PWM Period Register */
 #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
+#define MX3_PWMCR_STOPEN		(1 << 25)
 #define MX3_PWMCR_DOZEEN                (1 << 24)
 #define MX3_PWMCR_WAITEN                (1 << 23)
 #define MX3_PWMCR_DBGEN			(1 << 22)
@@ -39,6 +40,16 @@
 #define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
 
+/* Use the platform_id to distinguish different Archs. */
+#define IS_MX1			0x0
+#define IS_MX21			0x1
+#define IS_MX25			0x2
+#define IS_MX6Q			0x3
+#define PWM_IS_MX1(x)		((x)->id_entry->driver_data == IS_MX1)
+#define PWM_IS_MX21(x)		((x)->id_entry->driver_data == IS_MX21)
+#define PWM_IS_MX25(x)		((x)->id_entry->driver_data == IS_MX25)
+#define PWM_IS_MX6Q(x)		((x)->id_entry->driver_data == IS_MX6Q)
+
 struct imx_chip {
 	struct clk	*clk;
 
@@ -46,6 +57,7 @@ struct imx_chip {
 	void __iomem	*mmio_base;
 
 	struct pwm_chip	chip;
+	struct platform_device	*pdev;
 };
 
 #define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
@@ -65,7 +77,7 @@ static int imx_pwm_config(struct pwm_chip *chip,
 			return rc;
 	}
 
-	if (!(cpu_is_mx1() || cpu_is_mx21())) {
+	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
 		unsigned long long c;
 		unsigned long period_cycles, duty_cycles, prescale;
 		u32 cr;
@@ -78,36 +90,33 @@ static int imx_pwm_config(struct pwm_chip *chip,
 		prescale = period_cycles / 0x10000 + 1;
 
 		period_cycles /= prescale;
-		c = (unsigned long long)period_cycles * duty_ns;
-		do_div(c, period_ns);
-		duty_cycles = c;
 
-		/*
-		 * according to imx pwm RM, the real period value should be
-		 * PERIOD value in PWMPR plus 2.
+		/* the chip documentation says the counter counts up to
+		 * period_cycles + 1 and then is reset to 0, so the
+		 *  actual period of the PWM wave is period_cycles + 2
 		 */
-		if (period_cycles > 2)
-			period_cycles -= 2;
-		else
-			period_cycles = 0;
+		c = (unsigned long long)(period_cycles + 2) * duty_ns;
+		do_div(c, period_ns);
+		duty_cycles = c;
 
 		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
 		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 
 		cr = MX3_PWMCR_PRESCALER(prescale) |
-			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN;
+			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+			MX3_PWMCR_DBGEN | MX3_PWMCR_STOPEN;
 
 		/* If the PWM is enabled, keep it so. */
 		if (imx->clk_enabled)
 			cr |= MX3_PWMCR_EN;
 
-		if (cpu_is_mx25())
+		if (PWM_IS_MX25(imx->pdev))
 			cr |= MX3_PWMCR_CLKSRC_IPG;
 		else
 			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
 
 		writel(cr, imx->mmio_base + MX3_PWMCR);
-	} else if (cpu_is_mx1() || cpu_is_mx21()) {
+	} else if (PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev)) {
 		/* The PWM subsystem allows for exact frequencies. However,
 		 * I cannot connect a scope on my device to the PWM line and
 		 * thus cannot provide the program the PWM controller
@@ -150,7 +159,7 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	if (rc)
 		return rc;
 
-	if (!(cpu_is_mx1() || cpu_is_mx21())) {
+	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
 		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
 		cr |= MX3_PWMCR_EN;
 		writel(cr, imx->mmio_base + MX3_PWMCR);
@@ -167,7 +176,7 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	if (!imx->clk_enabled)
 		return;
 
-	if (!(cpu_is_mx1() || cpu_is_mx21())) {
+	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
 		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
 		cr &= ~MX3_PWMCR_EN;
 		writel(cr, imx->mmio_base + MX3_PWMCR);
@@ -207,6 +216,7 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	imx->chip.npwm = 1;
 
 	imx->clk_enabled = 0;
+	imx->pdev = pdev;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -237,9 +247,26 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
 	return pwmchip_remove(&imx->chip);
 }
 
+static const struct platform_device_id pwm_ids[] = {
+	{ .name = "imx1-pwm", .driver_data = IS_MX1, },
+	{ .name = "imx21-pwm", .driver_data = IS_MX21, },
+	{ .name = "imx25-pwm", .driver_data = IS_MX25, },
+	{ .name = "imx6q-pwm", .driver_data = IS_MX6Q, },
+	{},
+};
+
+static const struct of_device_id mxc_pwm_dt_ids[] = {
+	{
+		.compatible = "fsl,imx6q-pwm",
+		.data = (void *)&pwm_ids[IS_MX6Q]
+	},
+	{ /* sentinel */ }
+};
+
 static struct platform_driver imx_pwm_driver = {
 	.driver		= {
 		.name	= "mxc_pwm",
+		.of_match_table = of_match_ptr(mxc_pwm_dt_ids),
 	},
 	.probe		= imx_pwm_probe,
 	.remove		= __devexit_p(imx_pwm_remove),
-- 
1.7.1


From fabio.estevam at freescale.com  Mon Aug 27 12:23:27 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 13:23:27 -0300
Subject: [PATCH 1/3] ARM: mx28evk: Add SPI flash support
Message-ID: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>

mx28evk has a free slot (J89) which can be used to populate an SPI NOR Flash.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28-evk.dts |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ab78ee5..8a9a2f4 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,6 +46,23 @@
 				wp-gpios = <&gpio0 28 0>;
 			};
 
+			ssp2: ssp at 80014000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi2_pins_a>;
+				status = "okay";
+
+				flash: m25p80 at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "sst,sst25vf016b";
+					spi-max-frequency = <40000000>;
+					reg = <0>;
+				};
+			};
+
 			pinctrl at 80018000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&hog_pins_a>;
-- 
1.7.9.5




From fabio.estevam at freescale.com  Mon Aug 27 12:23:28 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 13:23:28 -0300
Subject: [PATCH 2/3] ARM: mx28evk: Add LRADC support
In-Reply-To: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <1346084609-31407-2-git-send-email-fabio.estevam@freescale.com>

Add LRADC support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28-evk.dts |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 8a9a2f4..ed92d61 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -145,6 +145,10 @@
 				status = "okay";
 			};
 
+			lradc at 80050000 {
+				status = "okay";
+			};
+
 			i2c0: i2c at 80058000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2c0_pins_a>;
-- 
1.7.9.5




From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:23:46 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:23:46 -0700
Subject: [PATCH] ASoC: atmel-ssc: include linux/io.h for raw io
In-Reply-To: <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
References: <20120823152324.GI7995@opensource.wolfsonmicro.com>
 <1345738494-4014-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20120827162346.GB4339@opensource.wolfsonmicro.com>

On Thu, Aug 23, 2012 at 06:14:54PM +0200, Nicolas Ferre wrote:
> From: Joachim Eastwood <manabian at gmail.com>
> 
> Include linux/io.h for raw io operations in atmel-scc header.

Applied, thanks.


From fabio.estevam at freescale.com  Mon Aug 27 12:23:29 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 13:23:29 -0300
Subject: [PATCH 3/3] ARM: mxs_defconfig: Add SPI and LRADC support
In-Reply-To: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <1346084609-31407-3-git-send-email-fabio.estevam@freescale.com>

Add SPI and LRADC support.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/configs/mxs_defconfig |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 36d60dd..d2910f9 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -53,6 +53,9 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
 CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
@@ -82,6 +85,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
+CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
@@ -110,7 +114,11 @@ CONFIG_RTC_DRV_DS1307=m
 CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
+CONFIG_STAGING=y
+CONFIG_MXS_LRADC=y
+CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_IIO=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
-- 
1.7.9.5




From arend at broadcom.com  Mon Aug 27 12:24:17 2012
From: arend at broadcom.com (Arend van Spriel)
Date: Mon, 27 Aug 2012 18:24:17 +0200
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR
 directly for non-OOB
In-Reply-To: <1346063114-30361-3-git-send-email-wni@nvidia.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
Message-ID: <503B9F31.5050502@broadcom.com>

On 08/27/2012 12:25 PM, Wei Ni wrote:
> In case of inband interrupts, if we handle the interrupt in dpc thread,
> two level of thread switching takes place to process wifi interrupts.
> One in SDHCI driver and the other in Wifi driver. This may cause the system
> instability.

Looking into the sdhci/mmc code indeed shows that the brcmfmac irq 
handler is not called in true IRQ context. So the dpc thread may add 
unnecessary complexity, but to me there is not indication that there is 
a stability issue.

> Because the SDHCI calls sdio_irq_thread() to handle the irq, this thread locks
> mmc host and calls wifi handler. It expects WiFi handler to be quick and
> enables sdio interrupt from card at end. If wifi handler defers this work for
> a different thread, sdio_irq_thread() will be stuck on next wifi interrupt
> since mmc lock is not freed.

Not sure if I can follow this explanation. The isr is called with host 
claimed (by sdio_irq_thread) and all it does is at a linked list member 
and signal the dpc thread. After doing this the host is released.

> Handling the interrupt in ISR directly will prevent thread context switching in
> wifi driver. It can fix the instability problems.

This basically increases the duration of the isr in brcmfmac.

> Signed-off-by: Wei Ni <wni at nvidia.com>
> ---
>   drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c   |    2 ++
>   drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c |    8 +++++++-
>   2 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> index 8e7e692..5cf6c3b 100644
> --- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> +++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> @@ -121,7 +121,9 @@ static void brcmf_sdio_irqhandler(struct sdio_func *func)
>
>   	brcmf_dbg(INTR, "ib intr triggered\n");
>
> +	sdio_release_host(sdiodev->func[1]);
>   	brcmf_sdbrcm_isr(sdiodev->bus);
> +	sdio_claim_host(sdiodev->func[1]);

This is probably needed because the ISR now locks the host to long 
because brcmf_sdbrcm_dpc() is called directly.

>   }
>
>   /* dummy handler for SDIO function 2 interrupt */
> diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> index 472f2ef..4576d59 100644
> --- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> +++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> @@ -2347,7 +2347,7 @@ static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
>   	uint framecnt = 0;	/* Temporary counter of tx/rx frames */
>   	bool rxdone = true;	/* Flag for no more read data */
>   	bool resched = false;	/* Flag indicating resched wanted */
> -	int err;
> +	int err = 0;
>
>   	brcmf_dbg(TRACE, "Enter\n");
>
> @@ -3786,11 +3786,17 @@ void brcmf_sdbrcm_isr(void *arg)
>   	if (!bus->intr)
>   		brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
>
> +
> +#ifndef CONFIG_BRCMFMAC_SDIO_OOB
> +	while (brcmf_sdbrcm_dpc(bus))
> +		;
> +#else
>   	bus->dpc_sched = true;
>   	if (bus->dpc_tsk) {
>   		brcmf_sdbrcm_adddpctsk(bus);
>   		complete(&bus->dpc_wait);
>   	}
> +#endif
>   }
>
>   static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
>

I would really like to know what issue is solved by this change. Could 
you provide more details.

Franky,

Do you have anything to add here?

Gr. AvS



From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:33:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:33:38 -0700
Subject: FW: [PATCH 07/22] ASoC: Ux500: Initialise PCM from MSP probe
 rather than as a device
In-Reply-To: <50377C0D.2060905@stericsson.com>
References: <014401cd8165$99960c40$ccc224c0$@se>
 <50377C0D.2060905@stericsson.com>
Message-ID: <20120827163337.GC4339@opensource.wolfsonmicro.com>

On Fri, Aug 24, 2012 at 03:05:17PM +0200, Ola Lilja wrote:

> I haven't followed everything in this discussion, but what I meant in an earlier
> mail was that using the device for platform-DAI (MSP_I2S) also
> as platform int the DAI-link struct is not anything I can see fit (as in the
> patch Lee first submitted).

I'm not sure I fully understand the above - I didn't notice anything
with the dai links but I have to say that I could've looked more closely
as I was waiting for ARM side reviews.

> I can see a few acceptable solutions:
> 1) Use it as it is! (A virtual device for PCM is created in arch/arm and the
> probe is invoked from the machine-driver).
> 2) Since the actual platform is the DMA-block, maybe there is some way of making
> the device "non-virtual" by having some sub-device in the DMA-driver that is
> instead triggered in the same way as in 1).

The option we're using is essentially your option 2 but doing it from
the DAI driver rather than from the DMA driver (keeping things in the
audio subsystem since it's an audio specific issue).


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:37:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:37:12 -0700
Subject: [PATCH] mxs/spi: Restart the block after unsuccessful transfer
In-Reply-To: <1345775658-9739-1-git-send-email-marex@denx.de>
References: <1345775658-9739-1-git-send-email-marex@denx.de>
Message-ID: <20120827163711.GD4339@opensource.wolfsonmicro.com>

On Fri, Aug 24, 2012 at 04:34:18AM +0200, Marek Vasut wrote:
> Restart the SSP block in case the SSP transfer failed in any way.
> The block hung in some cases otherwise.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:37:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:37:28 -0700
Subject: [PATCH V3] mxs/spi: Fix misuse of init_completion
In-Reply-To: <1345776987-15350-1-git-send-email-marex@denx.de>
References: <1345776987-15350-1-git-send-email-marex@denx.de>
Message-ID: <20120827163727.GE4339@opensource.wolfsonmicro.com>

On Fri, Aug 24, 2012 at 04:56:27AM +0200, Marek Vasut wrote:
> The init_completion() call does reinit not only the variable carrying
> the flag that the completion finished, but also initialized the
> waitqueue associated with the completion. On the contrary, the
> INIT_COMPLETION() call only reinits the flag.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:39:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:39:31 -0700
Subject: [PATCH] mxs/spi: Add SPI slave mode operation DT prop
In-Reply-To: <1345776161-9778-1-git-send-email-marex@denx.de>
References: <1345776161-9778-1-git-send-email-marex@denx.de>
Message-ID: <20120827163930.GG4339@opensource.wolfsonmicro.com>

On Fri, Aug 24, 2012 at 04:42:41AM +0200, Marek Vasut wrote:
> This allows user to select the slave mode of operation of the controller.
> This is by no means standard, see the binding documentation for details,
> there is plenty of them. Sadly, such knowledge is not provided in the chip
> documentation. Hopefully, this mode of operation might come useful for
> people who do know very well what they are doing, otherwise this should
> never be touched.

I was going to touch this but I appear to have misplaced my bargepole :)

More seriously as you say this is a bit controversial so given that
Grant's now finished his move and should reappear soon I'll punt for
now.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 12:51:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 09:51:38 -0700
Subject: [PATCH v3 1/4] arm/dts: regulator: Add tps65910 device tree data
In-Reply-To: <20120824201634.GZ11011@atomide.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-2-git-send-email-anilkumar@ti.com>
 <5033ADC5.4030002@wwwdotorg.org>
 <20120821163805.GW7995@opensource.wolfsonmicro.com>
 <5033CDDB.808@wwwdotorg.org>
 <20120821180847.GC7995@opensource.wolfsonmicro.com>
 <20120824201634.GZ11011@atomide.com>
Message-ID: <20120827165137.GL4339@opensource.wolfsonmicro.com>

On Fri, Aug 24, 2012 at 01:16:34PM -0700, Tony Lindgren wrote:
> * Mark Brown <broonie at opensource.wolfsonmicro.com> [120821 11:09]:

> > The board shouldn't have to define the regulators, the regulator driver
> > really ought to be able to figure out that they're there by itself if
> > there's no configuration based purely on knowing which chip is there.
> > From that point of view it's OK for the chip .dtsi to have them (though
> > ideally the driver wouldn't *need* that either) which was what was
> > happening here.

> So I assume no changes needed here then?

Seems that way.


From gregkh at linuxfoundation.org  Mon Aug 27 12:52:42 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Mon, 27 Aug 2012 09:52:42 -0700
Subject: [PATCH] dma: imx-dma: Fix kernel crash due to missing clock
 conversion
In-Reply-To: <20120827163006.0cffd20c@eb-e6520>
References: <1341341045-9472-1-git-send-email-fabio.estevam@freescale.com>
 <20120827163006.0cffd20c@eb-e6520>
Message-ID: <20120827165242.GA11102@kroah.com>

On Mon, Aug 27, 2012 at 04:30:06PM +0200, Eric B?nard wrote:
> Hi Greg, Hi Fabio,
> 
> this patch went into 3.4.10 as commit
> 9ea2c02bafe276e97b592a046ac733610a6d57fd
> which seems wrong as devm_clk_get seems to be added in linux-3.5 so
> compiling a 3.4.10 kernel with imx-dma enabled now leads :
> 
> drivers/dma/imx-dma.c: In function 'imxdma_probe':
> drivers/dma/imx-dma.c:980: error: implicit declaration of function
> 'devm_clk_get'
> drivers/dma/imx-dma.c:980: warning: assignment makes pointer from
> integer without a cast
> drivers/dma/imx-dma.c:986: warning: assignment makes pointer from
> integer without a cast
> 
> Reverting 9ea2c02bafe276e97b592a046ac733610a6d57fd allows to get a
> 3.4.10 kernel running fine on an i.MX35.

Ok, should I just revert it?  It's still needed on 3.5, right?

greg k-h


From marex at denx.de  Mon Aug 27 12:58:16 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 27 Aug 2012 18:58:16 +0200
Subject: [PATCH 1/3] ARM: mx28evk: Add SPI flash support
In-Reply-To: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <201208271858.16842.marex@denx.de>

Dear Fabio Estevam,

> mx28evk has a free slot (J89) which can be used to populate an SPI NOR
> Flash.
> 
> Add support for it.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/boot/dts/imx28-evk.dts |   17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28-evk.dts
> b/arch/arm/boot/dts/imx28-evk.dts index ab78ee5..8a9a2f4 100644
> --- a/arch/arm/boot/dts/imx28-evk.dts
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -46,6 +46,23 @@
>  				wp-gpios = <&gpio0 28 0>;
>  			};
> 
> +			ssp2: ssp at 80014000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx28-spi";
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&spi2_pins_a>;
> +				status = "okay";
> +
> +				flash: m25p80 at 0 {

Shouldn't this also be sst25vf016b at 0 ?

> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					compatible = "sst,sst25vf016b";
> +					spi-max-frequency = <40000000>;
> +					reg = <0>;
> +				};
> +			};
> +
>  			pinctrl at 80018000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&hog_pins_a>;

Best regards,
Marek Vasut


From marex at denx.de  Mon Aug 27 12:58:35 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 27 Aug 2012 18:58:35 +0200
Subject: [PATCH 2/3] ARM: mx28evk: Add LRADC support
In-Reply-To: <1346084609-31407-2-git-send-email-fabio.estevam@freescale.com>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
 <1346084609-31407-2-git-send-email-fabio.estevam@freescale.com>
Message-ID: <201208271858.35749.marex@denx.de>

Dear Fabio Estevam,

> Add LRADC support.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Acked-by: Marek Vasut <marex at denx.de>

> ---
>  arch/arm/boot/dts/imx28-evk.dts |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx28-evk.dts
> b/arch/arm/boot/dts/imx28-evk.dts index 8a9a2f4..ed92d61 100644
> --- a/arch/arm/boot/dts/imx28-evk.dts
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -145,6 +145,10 @@
>  				status = "okay";
>  			};
> 
> +			lradc at 80050000 {
> +				status = "okay";
> +			};
> +
>  			i2c0: i2c at 80058000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&i2c0_pins_a>;

Best regards,
Marek Vasut


From jangra.pankaj9 at gmail.com  Mon Aug 27 13:05:29 2012
From: jangra.pankaj9 at gmail.com (Pankaj Jangra)
Date: Mon, 27 Aug 2012 22:35:29 +0530
Subject: [PATCH v2 1/4] [RFC] clk: new locking scheme for reentrancy
In-Reply-To: <1345074214-17531-2-git-send-email-mturquette@linaro.org>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
 <1345074214-17531-2-git-send-email-mturquette@linaro.org>
Message-ID: <CADTbHxob_pkYN_73AD4YL_Ki5i40iLTJuN0rPuFzYcyyhfoMAQ@mail.gmail.com>

Hi Mike,

On Thu, Aug 16, 2012 at 5:13 AM, Mike Turquette <mturquette at linaro.org> wrote:
> The global prepare_lock mutex prevents concurrent operations in the clk
> api.  This incurs a performance penalty when unrelated clock subtrees
> are contending for the lock.
>
> Additionally there are use cases which benefit from reentrancy into the
> clk api.  A simple example is reparenting a mux clock with a call to
> clk_set_rate.  Patch #4 in this series demonstrates this without the use
> of internal helper functions.
>
> A more complex example is performing dynamic frequency and voltage
> scaling from clk_set_rate.  Patches #2 and #3 in this series demonstrate
> this.
>
> This commit affects users of the global prepare_lock mutex, namely
> clk_prepare, clk_unprepare, clk_set_rate and clk_set_parent.
>
> This patch introduces an enum inside of struct clk which tracks whether
> the framework has LOCKED or UNLOCKED the clk.
>
> Access to clk->state must be protected by the global prepare_lock mutex.
> In the future maybe the global mutex can be dropped and all operations
> will only use a global spinlock to protect access to the per-clk enums.
> A general outline of the new locking scheme is as follows:
>
> 1) hold the global prepare_lock mutex
> 2) traverse the tree checking to make sure that any clk's needed are
> UNLOCKED and not LOCKED
>         a) if a clk in the subtree of affected clk's is LOCKED then
>            release the global lock, wait_for_completion and then try
>            again up to a maximum of WAIT_TRIES times
>         b) After WAIT_TRIES times return -EBUSY
> 3) if all clk's are UNLOCKED then mark them as LOCKED
> 4) release the global prepare_lock mutex
> 5) do the real work
> 6) hold the global prepare_lock mutex
> 7) set all of the clocks previously marked as LOCKED to UNLOCKED
> 8) release the global prepare_lock mutex and return
>
> The primary down-side to this approach is that the clk api's might
> return -EBUSY due to lock contention.  This is only after having tried
> several times.  Bailing out like this is necessary to prevent deadlocks.
>
> The enum approach in this version of the patchset does not benefit from
> lockdep checking the lock order (but neither did v1).  It is possible
> for circular dependencies to pop up for the careless developer and
> bailing out after a number of unsuccessful tries is the sanest strategy.
>
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> ---
>  drivers/clk/clk.c            |  354 +++++++++++++++++++++++++++++++++++++-----
>  include/linux/clk-private.h  |    1 +
>  include/linux/clk-provider.h |    4 +-
>  3 files changed, 318 insertions(+), 41 deletions(-)
>

> +}
> +
> +void __clk_unprepare(struct clk *clk, struct clk *top)

Why do you need to change the signature of __clk_prepare and
__clk_unprepare functions ?
I mean i did not understand the use of passing struct clk *top? As i
understand, it tells when you reach at the last
clk struct in the tree which needs to be prepared/unprepared. Do we
have extra benefit of this or if i am missing something?

> +{
>         if (clk->ops->unprepare)
>                 clk->ops->unprepare(clk->hw);
>
> -       __clk_unprepare(clk->parent);
> +       if (clk != top)
> +               __clk_unprepare(clk->parent, top);
> +}
> +
> +static void __clk_prepare_unlock(struct clk *clk, struct clk *top)
> +{
> +       clk->state = UNLOCKED;
> +
> +       if (clk != top)
> +               __clk_prepare_unlock(clk->parent, top);
>  }
>
>  /**
> @@ -404,35 +437,94 @@ void __clk_unprepare(struct clk *clk)
>   */
>  void clk_unprepare(struct clk *clk)
>  {
> +       struct clk *top = ERR_PTR(-EBUSY);
> +       int tries = 0;
> +
> +       /*
> +        * walk the list of parents checking clk->state along the way.  If all
> +        * clk->state is UNLOCKED then continue.  If a clk->state is LOCKED then
> +        * bail out with -EBUSY.
> +        */
> +       while (IS_ERR(top)) {
> +               mutex_lock(&prepare_lock);
> +               top = __clk_unprepare_lock(clk);
> +               mutex_unlock(&prepare_lock);
> +
> +               if (IS_ERR(top)) {
> +                       pr_debug("%s: %s failed with %ld on attempt %d\n",
> +                                       __func__, clk->name, PTR_ERR(top),
> +                                       tries);
> +                       wait_for_completion(&clk_completion);
> +                       if (WAIT_TRIES == ++tries)
> +                               break;
> +               } else
> +                       break;

Braces around else part please.

> +       }
> +
> +       if (WAIT_TRIES == tries) {
> +               pr_warning("%s: failed to lock clocks; cyclical dependency?\n",
> +                               __func__);
> +               return;
> +       }
> +
> +       /* unprepare the list of clocks from clk to top */
> +       __clk_unprepare(clk, top);
> +

> +       /* unprepare the list of clocks from clk to top */
> +       __clk_prepare(clk, top);

You mean prepare right ? :)



Regards,
Pankaj Kumar


From festevam at gmail.com  Mon Aug 27 13:12:10 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 14:12:10 -0300
Subject: [PATCH] dma: imx-dma: Fix kernel crash due to missing clock
 conversion
In-Reply-To: <20120827165242.GA11102@kroah.com>
References: <1341341045-9472-1-git-send-email-fabio.estevam@freescale.com>
 <20120827163006.0cffd20c@eb-e6520>
 <20120827165242.GA11102@kroah.com>
Message-ID: <CAOMZO5A3v-K3OGghy2wYqkyqba5y=NcGSXa4C=9bEFHn1x6vaQ@mail.gmail.com>

On Mon, Aug 27, 2012 at 1:52 PM, Greg Kroah-Hartman
<gregkh at linuxfoundation.org> wrote:

> Ok, should I just revert it?  It's still needed on 3.5, right?

Yes, please revert it from 3.4 and keep it on 3.5.

Thanks,

Fabio Estevam


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 13:13:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 10:13:30 -0700
Subject: ASoC: SAMSUNG: Change Kconfig to support all EXYNOSs
In-Reply-To: <003001cd8361$7016a110$5043e330$@samsung.com>
References: <003001cd8361$7016a110$5043e330$@samsung.com>
Message-ID: <20120827171329.GO4339@opensource.wolfsonmicro.com>

On Sun, Aug 26, 2012 at 05:04:37PM +0900, ????? wrote:
> All EXYNOSs use SND_SOC_SAMSUNG configuration.
> This patch change Kconfig to support all EXYNOSs like EXYNOS4 and EXYNOS5.

git can't figure out how to apply your patch due to your character set:

   fatal: cannot convert from ks_c_5601-1987 to UTF-8



From paul at pwsan.com  Mon Aug 27 13:15:35 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:15:35 +0000 (UTC)
Subject: [PATCH] ARM: OMAP2+: am33xx: Fix the timer fck clock naming
 convention
In-Reply-To: <1342462158-15998-1-git-send-email-hvaibhav@ti.com>
References: <1342462158-15998-1-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.00.1208271715240.26953@utopia.booyaka.com>

On Mon, 16 Jul 2012, Vaibhav Hiremath wrote:

> With commit ae6df418a21f3a361c5f9b878e32a8aba4e17692
> Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage)
> The Timer functional clock naming convention has changed from
> gptX_fck => timerXfck, and so as the timer init function
> in mach-omap2/timer.c.
> OMAP4 clocktree also has changed accordingly.
> 
> AM33xx Clock Tree has been merged during rc3-4 timeframe,
> before above commit got merged, so similar change is required
> for AM33xx as well (Change the gptX_fck => timerX_fck).
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>

Thanks, queued for v3.6-rc.


- Paul


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 13:19:06 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 10:19:06 -0700
Subject: [PATCH] spi/s3c64xx: Drop extra calls to spi_master_get in
 suspend/remove functions
In-Reply-To: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
References: <1345173265-1721-1-git-send-email-linux@roeck-us.net>
Message-ID: <20120827171904.GP4339@opensource.wolfsonmicro.com>

On Thu, Aug 16, 2012 at 08:14:25PM -0700, Guenter Roeck wrote:
> Suspend and resume functions call spi_master_get() without matching
> spi_master_put(). The extra references are unnecessary and cause subsequent
> module unload attempts to fail. Drop the calls.

Applied, thanks.


From paul at pwsan.com  Mon Aug 27 13:20:12 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:20:12 +0000 (UTC)
Subject: [PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
In-Reply-To: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>
References: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.00.1208271717420.26953@utopia.booyaka.com>

Hi

On Mon, 27 Aug 2012, Vaibhav Hiremath wrote:

> Currently, the device names for the dcan module follows the
> format "dcan.X", where 'X' is the dcan instance number.
> On other side, driver may request for clock with/without con_id
> and dev_id, and it is expected that platform should respect this
> request and return the requested clock handle.
> 
> Now, when using device tree, the format of the device name created
> by OF layer is different, "<reg-address>.<device-name>",
> assuming that the device-tree "reg" property is specified.
> This causes the look-up failure for clock node in dcan driver
> 
> To fix this add new dcan clock alias for using device-tree.

Is the dcan driver present in v3.6-rc kernels?  Doesn't look like it but 
maybe it's under an alias.


- Paul


From gregkh at linuxfoundation.org  Mon Aug 27 13:25:10 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Mon, 27 Aug 2012 10:25:10 -0700
Subject: [PATCH] dma: imx-dma: Fix kernel crash due to missing clock
 conversion
In-Reply-To: <CAOMZO5A3v-K3OGghy2wYqkyqba5y=NcGSXa4C=9bEFHn1x6vaQ@mail.gmail.com>
References: <1341341045-9472-1-git-send-email-fabio.estevam@freescale.com>
 <20120827163006.0cffd20c@eb-e6520>
 <20120827165242.GA11102@kroah.com>
 <CAOMZO5A3v-K3OGghy2wYqkyqba5y=NcGSXa4C=9bEFHn1x6vaQ@mail.gmail.com>
Message-ID: <20120827172510.GA25335@kroah.com>

On Mon, Aug 27, 2012 at 02:12:10PM -0300, Fabio Estevam wrote:
> On Mon, Aug 27, 2012 at 1:52 PM, Greg Kroah-Hartman
> <gregkh at linuxfoundation.org> wrote:
> 
> > Ok, should I just revert it?  It's still needed on 3.5, right?
> 
> Yes, please revert it from 3.4 and keep it on 3.5.

Thanks for letting me know, now reverted.

greg k-h


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 13:26:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 10:26:20 -0700
Subject: [PATCH V2 6/6] ASoC: tlv320aic3x: Add device tree bindings
In-Reply-To: <1346074004-22172-7-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-7-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827172620.GQ4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:44PM +0530, Hebbar, Gururaja wrote:

> Device tree support for tlv320aic3x CODEC driver.

Applied, thanks.


From gregory.clement at free-electrons.com  Mon Aug 27 13:31:19 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 27 Aug 2012 19:31:19 +0200
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <5037776A.6050605@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
 <20120824104309.GE5400@mudshark.cambridge.arm.com>
 <5037776A.6050605@free-electrons.com>
Message-ID: <503BAEE7.5080401@free-electrons.com>

On 08/24/2012 02:45 PM, Gregory CLEMENT wrote:
> On 08/24/2012 12:43 PM, Will Deacon wrote:> On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
>>> +static void __init aurora_broadcast_l2_commands(void)
>>> +{
>>> +       __u32 u;
>>> +       /* Enable Broadcasting of cache commands to L2*/
>>> +       __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
>>> +       u |= 0x100;             /* Set the FW bit */
>>> +       __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
>>> +}
>>
>> Couple of questions about this code:
>>
>> 1. Is this register r/w from non-secure?
> 
> This register is banked.
> 
>> 2. I'm surprised that there aren't barriers and/or maintenance operations
>>    needed around this operation. It might be worth checking in the
>>    documentation that you have (you probably need at least an isb()
>>    following the mcr).
> 
> I didn't find any mention of barriers and/or maintenance operations
> needed around this operation, but maybe I have missed something, or it
> was implicit for the people who wrote the documentation. I will ask
> confirmation that we don't need this.

I've just received confirmation that this register is  r/w from non-secure.
And that it would be good practice to have an ISB after this MCR, so I
will add this for the next version coming soon.

> 
>>
>> Will
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From gregory.clement at free-electrons.com  Mon Aug 27 13:32:44 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Mon, 27 Aug 2012 19:32:44 +0200
Subject: [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <503B3D00.2000500@codethink.co.uk>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-6-git-send-email-gregory.clement@free-electrons.com>
 <50379609.1020006@codethink.co.uk> <50379A96.1050409@free-electrons.com>
 <503B3D00.2000500@codethink.co.uk>
Message-ID: <503BAF3C.9010703@free-electrons.com>

On 08/27/2012 11:25 AM, Ian Molton wrote:
> On 24/08/12 17:15, Gregory CLEMENT wrote:
>> On 08/24/2012 04:56 PM, Ian Molton wrote:> On 24/08/12 11:09, Gregory CLEMENT wrote:
>>>> + compatible = "marvell,aurora-cache-with-outer";
>>> This reads wrong.
>>>
>>> perhaps aurora-with-outer-cache?
>> We can use
>> compatible = "marvell,aurora-outer-cache"
>> and
>> compatible = "marvell,aurora-system-cache"
>>
>> which is a better description of the L2 cache controller indeed.
> 
> Yes, much clearer.

OK I will change this in next version.

> 
>> I guess you meant:
>>
>> compatible = "marvell,armada370", "marvell,armada-370-xp";
>>     L2: l2-cache {										
>>         compatible = "marvell,aurora-cache";
>>         reg = <0xd0008000 0x1000>;
>>         cache-id-part = <0x100>;
>>         wt-override;
>>         with-outer="yes";
>>     };
> 
> Yes :)
> 
> -Ian
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From hvaibhav at ti.com  Mon Aug 27 14:02:35 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 27 Aug 2012 18:02:35 +0000
Subject: [PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
In-Reply-To: <alpine.DEB.2.00.1208271717420.26953@utopia.booyaka.com>
References: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1208271717420.26953@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA99396@DBDE01.ent.ti.com>

On Mon, Aug 27, 2012 at 22:50:12, Paul Walmsley wrote:
> Hi
> 
> On Mon, 27 Aug 2012, Vaibhav Hiremath wrote:
> 
> > Currently, the device names for the dcan module follows the
> > format "dcan.X", where 'X' is the dcan instance number.
> > On other side, driver may request for clock with/without con_id
> > and dev_id, and it is expected that platform should respect this
> > request and return the requested clock handle.
> > 
> > Now, when using device tree, the format of the device name created
> > by OF layer is different, "<reg-address>.<device-name>",
> > assuming that the device-tree "reg" property is specified.
> > This causes the look-up failure for clock node in dcan driver
> > 
> > To fix this add new dcan clock alias for using device-tree.
> 
> Is the dcan driver present in v3.6-rc kernels?  

Multiple versions have been submitted already, I have validated using them.
Irrespective of this, it is independent change and required for the driver.

Thanks,
Vaibhav



From kgene.kim at samsung.com  Mon Aug 27 14:06:47 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 11:06:47 -0700
Subject: ASoC: SAMSUNG: Change Kconfig to support all EXYNOSs
In-Reply-To: <003001cd8361$7016a110$5043e330$@samsung.com>
References: <003001cd8361$7016a110$5043e330$@samsung.com>
Message-ID: <503BB737.7090004@samsung.com>

On 08/26/12 01:04, ??? wrote:
> All EXYNOSs use SND_SOC_SAMSUNG configuration.
> This patch change Kconfig to support all EXYNOSs like EXYNOS4 and EXYNOS5.
> 
> Signed-off-by: Sangsu Park<sangsu4u.park at samsung.com>
> ---
>   sound/soc/samsung/Kconfig |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
> index f17dd25..9e64ae6 100644
> --- a/sound/soc/samsung/Kconfig
> +++ b/sound/soc/samsung/Kconfig
> @@ -1,6 +1,6 @@
>   config SND_SOC_SAMSUNG
>   	tristate "ASoC support for Samsung"
> -	depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 ||
> ARCH_EXYNOS4
> +	depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 ||
> ARCH_EXYNOS

Hmm, all of Samsung stuff is available...so how about?

+	depends on PLAT_SAMSUNG

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:08:25 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:08:25 -0700
Subject: [PATCH V2 4/6] ASoC: Davinci: McASP: add device tree support for
 McASP
In-Reply-To: <1346074004-22172-5-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-5-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827180824.GR4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:42PM +0530, Hebbar, Gururaja wrote:

> +- sram-size-playback : size of sram to be allocated during playback
> +- sram-size-capture  : size of sram to be allocated during capture

These smell like runtime/policy configuration rather than fixed
properties of the device so it probably shouldn't appear in the device
tree, ideally at some point in the future we'll be able to work out some
wonderful way of automatically allocating the resources.

That said if the rest of the series looks OK I'll apply this but it'd be
nice to get these numbers from somewhere else.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:08:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:08:52 -0700
Subject: ASoC: SAMSUNG: Change Kconfig to support all EXYNOSs
In-Reply-To: <503BB737.7090004@samsung.com>
References: <003001cd8361$7016a110$5043e330$@samsung.com>
 <503BB737.7090004@samsung.com>
Message-ID: <20120827180851.GS4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 11:06:47AM -0700, Kukjin Kim wrote:

> Hmm, all of Samsung stuff is available...so how about?
> 
> +	depends on PLAT_SAMSUNG

Yes, that's a very good idea!


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:12:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:12:52 -0700
Subject: [PATCH V2 1/6] ASoC: davinci: davinci-pcm does not need to be a
 plaform_driver
In-Reply-To: <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827181251.GT4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:39PM +0530, Hebbar, Gururaja wrote:
> Same as the commit 518de86 (ASoC: tegra: register 'platform' from DAIs,
> get rid of pdev). It makes davinci-pcm not a platform_driver but helper
> to register "platform", so that the platform_device for davinci-pcm can
> be saved completely.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:13:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:13:00 -0700
Subject: [PATCH V2 2/6] ARM: Davinci: Remove references to davinci pcm
In-Reply-To: <1346074004-22172-3-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-3-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827181259.GU4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:40PM +0530, Hebbar, Gururaja wrote:
> Since davinci-pcm is no more a platform_driver but helper to register
> "platform" pcm driver, remove  davinci-pcm device registration

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:13:11 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:13:11 -0700
Subject: [PATCH V2 3/6] ASoC/ARM: Davinci: McASP: split asp header into
 platform and audio specific
In-Reply-To: <1346074004-22172-4-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-4-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827181311.GV4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:41PM +0530, Hebbar, Gururaja wrote:
> Davinci McASP header & driver are shared by few OMAP platforms (like
> TI81xx, AM335x). Splitting asp header into Davinci platform specific
> header and Audio specific header helps to share them across platforms.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:13:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:13:23 -0700
Subject: [PATCH V2 4/6] ASoC: Davinci: McASP: add device tree support for
 McASP
In-Reply-To: <1346074004-22172-5-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-5-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827181322.GW4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:42PM +0530, Hebbar, Gururaja wrote:
> Add device tree probe for McASP driver.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 14:19:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 11:19:40 -0700
Subject: [PATCH V2 5/6] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1346074004-22172-6-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-6-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120827181939.GX4339@opensource.wolfsonmicro.com>

On Mon, Aug 27, 2012 at 06:56:43PM +0530, Hebbar, Gururaja wrote:
> Device tree support for tlv320aic3x CODEC driver

Not really for the CODEC - this is a machine driver.

> +- dai-data		: A list of DAI data used by SOC code to register
> +			  DAI, Codecs platform.
> +			  The string index "should" be as shown below.
> +dai-data =
> +"<DAI Name>", 		"<DAI Stream Name>",
> +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> +"<evm ops required (evm_ops or evm_spdif_ops)>";

What do these different ops do - how would the user figure it out or if
they're needed at all?


From troy.kisky at boundarydevices.com  Mon Aug 27 14:20:10 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Mon, 27 Aug 2012 11:20:10 -0700
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled
 console
In-Reply-To: <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <503BBA5A.8040609@boundarydevices.com>

On 8/27/2012 12:36 AM, Dirk Behme wrote:
> From: Xinyu Chen <xinyu.chen at freescale.com>
>
> Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
> as this will cause clock reinit, and output garbage.
>
> This patch is a port from Freescale's Android kernel.
>
> Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
> Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
> CC: Shawn Guo <shawn.guo at linaro.org>
> CC: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>   drivers/tty/serial/imx.c |    2 ++
>   1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
> index 908178f..31ce414 100644
> --- a/drivers/tty/serial/imx.c
> +++ b/drivers/tty/serial/imx.c
> @@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
>   	int retval;
>   	unsigned long flags, temp;
>   
> +#ifndef CONFIG_SERIAL_CORE_CONSOLE
>   	imx_setup_ufcr(sport, 0);
> +#endif
>   
>   	/* disable the DREN bit (Data Ready interrupt enable) before
>   	 * requesting IRQs


I'd rather do something like this

static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
{
         unsigned int val;

         /* set receiver / transmitter trigger level. */
         val = readl(sport->port.membase + UFCR) & UFCR_RFDIV;
         val |= TXTL << 10 | RXTL;
         writel(val, sport->port.membase + UFCR);
         return 0;
}

There is no need for imx_setup_ufcr to change divisor.


Troy



From rvaswani at codeaurora.org  Mon Aug 27 14:34:22 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Mon, 27 Aug 2012 11:34:22 -0700
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <6e478bc5efb598b4a15ff9d534b94001@localhost>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
 <6e478bc5efb598b4a15ff9d534b94001@localhost>
Message-ID: <503BBDAE.7020302@codeaurora.org>

On 8/11/2012 3:04 AM, Marc Zyngier wrote:
> Hi Rohit,
>
> On Fri, 10 Aug 2012 14:58:41 -0700, Rohit Vaswani
> <rvaswani at codeaurora.org>
> wrote:
>> The current arch_timer only support accessing through CP15 interface.
>> Add support for ARM processors that only support IO mapped register
>> interface
> This is quite a departure from the current implementation, which raises a
> couple of questions:
> - What does CP15 ID_PFR1[19:16] report? Can we easily detect that we do
> not have the CP15 interface?
> - What about HYP mode? Is there any way to control the access of the
> physical timer at PL1?
Yes - we can easily detect if CP15 interface is not present. The PFR1 
[19:16] are 0 for this implementation.
How is the access control managed currently for the Physical timer ?
>> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
>> ---
>>   .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>>   arch/arm/kernel/arch_timer.c                       |  259
>>   ++++++++++++++++----
>>   2 files changed, 223 insertions(+), 43 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> index 52478c8..1c71799 100644
>> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its
>> per-processor interrupts.
>>   
>>   - clock-frequency : The frequency of the main counter, in Hz. Optional.
>>   
>> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu (PPI)
>> interrupt
>> +  In the default case i.e without this property, the timer irq is
> treated
>> as a
>> +  PPI interrupt. Optional.
> Ouch! How do you specify the various interrupts for all CPUs? Do you end
> up with 4 SPIs per CPU?
>
>> +- If the node address and reg is specified, the arch_timer will try to
>> use the memory
>> +  mapped timer. Optional.
>> +
>>   Example:
>>   
>>   	timer {
>> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
>> index 1d0d9df..09604b7 100644
>> --- a/arch/arm/kernel/arch_timer.c
>> +++ b/arch/arm/kernel/arch_timer.c
>> @@ -18,6 +18,7 @@
>>   #include <linux/clockchips.h>
>>   #include <linux/interrupt.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>>   #include <linux/io.h>
>>   
>>   #include <asm/cputype.h>
>> @@ -29,8 +30,17 @@
>>   static unsigned long arch_timer_rate;
>>   static int arch_timer_ppi;
>>   static int arch_timer_ppi2;
>> +static int is_irq_percpu;
>>   
>>   static struct clock_event_device __percpu **arch_timer_evt;
>> +static void __iomem *timer_base;
>> +
>> +struct arch_timer_operations {
>> +	void (*reg_write)(int, u32);
>> +	u32 (*reg_read)(int);
>> +	cycle_t (*get_cntpct)(void);
>> +	cycle_t (*get_cntvct)(void);
>> +};
> I already have something similar in a patch series that I'd like to get
> merged in 3.7, implementing support for the virtual timers (needed for
> virtualisation). Have a look at:
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> timers-next
I am working on a patch based on this and will send this out soon.
> <snip> 


Thanks,
Rohit Vaswani

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From paul at pwsan.com  Mon Aug 27 14:36:45 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 18:36:45 +0000 (UTC)
Subject: [PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA99396@DBDE01.ent.ti.com>
References: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1208271717420.26953@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA99396@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1208271836270.26953@utopia.booyaka.com>

On Mon, 27 Aug 2012, Hiremath, Vaibhav wrote:

> On Mon, Aug 27, 2012 at 22:50:12, Paul Walmsley wrote:
>
> > Is the dcan driver present in v3.6-rc kernels?  
> 
> Multiple versions have been submitted already, I have validated using them.
> Irrespective of this, it is independent change and required for the driver.

OK, will queue it for 3.7.

- Paul


From hvaibhav at ti.com  Mon Aug 27 14:38:36 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 27 Aug 2012 18:38:36 +0000
Subject: [PATCH] ARM: AM33XX: clock: Add dcan clock aliases for device-tree
In-Reply-To: <alpine.DEB.2.00.1208271836270.26953@utopia.booyaka.com>
References: <1346061842-28714-1-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1208271717420.26953@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A83EA99396@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1208271836270.26953@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA99446@DBDE01.ent.ti.com>

On Tue, Aug 28, 2012 at 00:06:45, Paul Walmsley wrote:
> On Mon, 27 Aug 2012, Hiremath, Vaibhav wrote:
> 
> > On Mon, Aug 27, 2012 at 22:50:12, Paul Walmsley wrote:
> >
> > > Is the dcan driver present in v3.6-rc kernels?  
> > 
> > Multiple versions have been submitted already, I have validated using them.
> > Irrespective of this, it is independent change and required for the driver.
> 
> OK, will queue it for 3.7.
> 

Thanks Paul.

Thanks,
Vaibhav



From rvaswani at codeaurora.org  Mon Aug 27 14:40:36 2012
From: rvaswani at codeaurora.org (Rohit Vaswani)
Date: Mon, 27 Aug 2012 11:40:36 -0700
Subject: [PATCH 2/2] ARM: local timers: add timer support using IO mapped
 register
In-Reply-To: <5025C62B.10407@ti.com>
References: <1344635921-5147-1-git-send-email-rvaswani@codeaurora.org>
 <5025C62B.10407@ti.com>
Message-ID: <503BBF24.2010107@codeaurora.org>

On 8/10/2012 7:40 PM, Cyril Chemparathy wrote:
> On 8/10/2012 5:58 PM, Rohit Vaswani wrote:
>> The current arch_timer only support accessing through CP15 interface.
>> Add support for ARM processors that only support IO mapped register
>> interface
>>
>
> It looks like this patch attempts to address both (a) non-percpu arch 
> timers, and (b) memory mapped arch timers in one go.  These should 
> probably be broken out into two distinct logical changes.
>
Will split them.

> More below...
>
>> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
>> ---
>>   .../devicetree/bindings/arm/arch_timer.txt         |    7 +
>>   arch/arm/kernel/arch_timer.c                       |  259 
>> ++++++++++++++++----
>>   2 files changed, 223 insertions(+), 43 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt 
>> b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> index 52478c8..1c71799 100644
>> --- a/Documentation/devicetree/bindings/arm/arch_timer.txt
>> +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
>> @@ -14,6 +14,13 @@ The timer is attached to a GIC to deliver its 
>> per-processor interrupts.
>>
>>   - clock-frequency : The frequency of the main counter, in Hz. 
>> Optional.
>>
>> +- irq-is-not-percpu: Specify is the timer irq is *NOT* a percpu 
>> (PPI) interrupt
>> +  In the default case i.e without this property, the timer irq is 
>> treated as a
>> +  PPI interrupt. Optional.
>> +
>
> The handling of non-percpu IRQs looks broken.  The code does 
> (enable/disable)_percpu_irq() on IRQs that may no longer be percpu.
I am thinking of adding a wrapper function (function pointer in the 
timer_ops) that will call  (enable/disable)_percpu_irq() based on if the 
said property is defined or not.
>
>> +- If the node address and reg is specified, the arch_timer will try 
>> to use the memory
>> +  mapped timer. Optional.
>> +
>>   Example:
>>
>>       timer {
>> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
>> index 1d0d9df..09604b7 100644
>> --- a/arch/arm/kernel/arch_timer.c
>> +++ b/arch/arm/kernel/arch_timer.c
>> @@ -18,6 +18,7 @@
>>   #include <linux/clockchips.h>
>>   #include <linux/interrupt.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>>   #include <linux/io.h>
>>
>>   #include <asm/cputype.h>
>> @@ -29,8 +30,17 @@
>>   static unsigned long arch_timer_rate;
>>   static int arch_timer_ppi;
>>   static int arch_timer_ppi2;
>> +static int is_irq_percpu;
>>
>>   static struct clock_event_device __percpu **arch_timer_evt;
>> +static void __iomem *timer_base;
>> +
>
> Are percpu memory mapped arch timers an impossibility?
I will make sure to keep this open , as in add memory mapped timers as 
well as the possibility of percpu timer interrupts for both memory 
mapped and the cp15 interface.
>
>> +struct arch_timer_operations {
>> +    void (*reg_write)(int, u32);
>> +    u32 (*reg_read)(int);
>> +    cycle_t (*get_cntpct)(void);
>> +    cycle_t (*get_cntvct)(void);
>> +};
>>
>>   /*
>>    * Architected system timer support.
>> @@ -44,7 +54,29 @@ static struct clock_event_device __percpu 
>> **arch_timer_evt;
>>   #define ARCH_TIMER_REG_FREQ        1
>>   #define ARCH_TIMER_REG_TVAL        2
>>
>> -static void arch_timer_reg_write(int reg, u32 val)
>> +/* Iomapped Register Offsets */
>> +#define ARCH_TIMER_CNTP_LOW_REG        0x000
>> +#define ARCH_TIMER_CNTP_HIGH_REG    0x004
>> +#define ARCH_TIMER_CNTV_LOW_REG        0x008
>> +#define ARCH_TIMER_CNTV_HIGH_REG    0x00C
>> +#define ARCH_TIMER_CTRL_REG        0x02C
>> +#define ARCH_TIMER_FREQ_REG        0x010
>> +#define ARCH_TIMER_CNTP_TVAL_REG    0x028
>> +#define ARCH_TIMER_CNTV_TVAL_REG    0x038
>> +
>
> ARCH_TIMER_CNTV_TVAL_REG appears to be unused here.
>
>> +static void timer_reg_write_mem(int reg, u32 val)
>> +{
>> +    switch (reg) {
>> +    case ARCH_TIMER_REG_CTRL:
>> +        __raw_writel(val, timer_base + ARCH_TIMER_CTRL_REG);
>> +        break;
>> +    case ARCH_TIMER_REG_TVAL:
>> +        __raw_writel(val, timer_base + ARCH_TIMER_CNTP_TVAL_REG);
>> +        break;
>> +    }
>> +}
>> +
>
> Wouldn't an array of offsets to map from ARCH_TIMER_REG_* to these 
> memory mapped registers eliminate the need to switch-case your way 
> through each register?
Done.
>
>> +static void timer_reg_write_cp15(int reg, u32 val)
>>   {
>>       switch (reg) {
>>       case ARCH_TIMER_REG_CTRL:
>> @@ -58,7 +90,28 @@ static void arch_timer_reg_write(int reg, u32 val)
>>       isb();
>>   }
>>
>> -static u32 arch_timer_reg_read(int reg)
>> +static u32 timer_reg_read_mem(int reg)
>> +{
>> +    u32 val;
>> +
>> +    switch (reg) {
>> +    case ARCH_TIMER_REG_CTRL:
>> +        val = __raw_readl(timer_base + ARCH_TIMER_CTRL_REG);
>> +        break;
>> +    case ARCH_TIMER_REG_FREQ:
>> +        val = __raw_readl(timer_base + ARCH_TIMER_FREQ_REG);
>> +        break;
>> +    case ARCH_TIMER_REG_TVAL:
>> +        val = __raw_readl(timer_base + ARCH_TIMER_CNTP_TVAL_REG);
>> +        break;
>> +    default:
>> +        BUG();
>> +    }
>> +
>> +    return val;
>> +}
>> +
>
> Same as above.
>
>> +static u32 timer_reg_read_cp15(int reg)
>>   {
>>       u32 val;
>>
>> @@ -79,6 +132,103 @@ static u32 arch_timer_reg_read(int reg)
>>       return val;
>>   }
>>
>> +static cycle_t arch_counter_get_cntpct_mem(void)
>> +{
>> +    u32 cvall, cvalh, thigh;
>> +
>> +    do {
>> +        cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
>> +        cvall = __raw_readl(timer_base + ARCH_TIMER_CNTP_LOW_REG);
>> +        thigh = __raw_readl(timer_base + ARCH_TIMER_CNTP_HIGH_REG);
>> +    } while (cvalh != thigh);
>> +
>> +    return ((cycle_t) cvalh << 32) | cvall;
>> +}
>> +
>> +static cycle_t arch_counter_get_cntpct_cp15(void)
>> +{
>> +    u32 cvall, cvalh;
>> +
>> +    asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" 
>> (cvalh));
>> +
>> +    return ((cycle_t) cvalh << 32) | cvall;
>> +}
>> +
>> +static cycle_t arch_counter_get_cntvct_mem(void)
>> +{
>> +    u32 cvall, cvalh, thigh;
>> +
>> +    do {
>> +        cvalh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
>> +        cvall = __raw_readl(timer_base + ARCH_TIMER_CNTV_LOW_REG);
>> +        thigh = __raw_readl(timer_base + ARCH_TIMER_CNTV_HIGH_REG);
>> +    } while (cvalh != thigh);
>> +
>> +    return ((cycle_t) cvalh << 32) | cvall;
>> +}
>> +
>
> Repetitive - the logic is identical to arch_counter_get_cntpct_mem() 
> above.
>
>> +static cycle_t arch_counter_get_cntvct_cp15(void)
>> +{
>> +    u32 cvall, cvalh;
>> +
>> +    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" 
>> (cvalh));
>> +
>> +    return ((cycle_t) cvalh << 32) | cvall;
>> +}
>> +
>> +static struct arch_timer_operations arch_timer_ops_cp15 = {
>> +    .reg_read = &timer_reg_read_cp15,
>> +    .reg_write = &timer_reg_write_cp15,
>> +    .get_cntpct = &arch_counter_get_cntpct_cp15,
>> +    .get_cntvct = &arch_counter_get_cntvct_cp15,
>> +};
>> +
>> +static struct arch_timer_operations arch_timer_ops_mem = {
>> +    .reg_read = &timer_reg_read_mem,
>> +    .reg_write = &timer_reg_write_mem,
>> +    .get_cntpct = &arch_counter_get_cntpct_mem,
>> +    .get_cntvct = &arch_counter_get_cntvct_mem,
>> +};
>> +
>> +static struct arch_timer_operations *arch_specific_timer = 
>> &arch_timer_ops_cp15;
>> +
>> +static inline void arch_timer_reg_write(int reg, u32 val)
>> +{
>> +    arch_specific_timer->reg_write(reg, val);
>> +}
>> +
>> +static inline u32 arch_timer_reg_read(int reg)
>> +{
>> +    return arch_specific_timer->reg_read(reg);
>> +}
>> +
>> +static inline cycle_t arch_counter_get_cntpct(void)
>> +{
>> +    return arch_specific_timer->get_cntpct();
>> +}
>> +
>> +static inline cycle_t arch_counter_get_cntvct(void)
>> +{
>> +    return arch_specific_timer->get_cntvct();
>> +}
>> +
>
> The 4 pointer chasers above could lose some verbosity by being #defines.
I am rebasing this patch on top of Marc's similar patch to add support 
for virtual timers and will fix up the problems you have mentioned.
Thanks for your feedback.
>
> <snip>


Thanks,
Rohit Vaswani

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From festevam at gmail.com  Mon Aug 27 14:54:30 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 15:54:30 -0300
Subject: [PATCH V4] MXS: Implement DMA support into mxs-i2c
In-Reply-To: <1345779871-7677-1-git-send-email-marex@denx.de>
References: <1345779871-7677-1-git-send-email-marex@denx.de>
Message-ID: <CAOMZO5CSvP3nXNq4VLYALh+U9OZRnjtgXqTr7zsKdeHpUdJ4cQ@mail.gmail.com>

On Fri, Aug 24, 2012 at 12:44 AM, Marek Vasut <marex at denx.de> wrote:
> This patch implements DMA support into mxs-i2c. DMA transfers are now enabled
> via DT. The DMA operation is enabled by default.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> CC: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: linux-i2c at vger.kernel.org
> CC: Shawn Guo <shawn.guo at linaro.org>
> Cc: Wolfram Sang <w.sang at pengutronix.de>

On a mx28evk:

Tested-by: Fabio Estevam <fabio.estevam at freescale.com>

Wolfram,

Adding dma support into mxs-i2c has also the benefit to allow i2c on
mx23 to work.

Please consider applying this one.

Thanks,

Fabio Estevam


From linux at arm.linux.org.uk  Mon Aug 27 15:14:58 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 27 Aug 2012 20:14:58 +0100
Subject: Question about ION carveout heap support partial cache flush
In-Reply-To: <CAN1soZw4Qk5qSyuyMko9SZWu3u3_7OPA2yNVYz6C1WQWVimbvg@mail.gmail.com>
References: <CAMj5BkgffAW6azUjwz+iCF1tBLmBDRBvBjR-_fTr=4G=h+BLZw@mail.gmail.com>
 <CAN1soZyZ=4wjKkVrk5--2U_8SeT7qee9QAfhss7NgqtQAz+RrA@mail.gmail.com>
 <CAMj5BkiVq9ayJjUrwh3S-gDfezUTNiPFW-xd_dsbTJYTyLv2WQ@mail.gmail.com>
 <20120827082914.GN18957@n2100.arm.linux.org.uk>
 <CAN1soZw4Qk5qSyuyMko9SZWu3u3_7OPA2yNVYz6C1WQWVimbvg@mail.gmail.com>
Message-ID: <20120827191458.GP18957@n2100.arm.linux.org.uk>

On Mon, Aug 27, 2012 at 09:43:10PM +0800, Haojian Zhuang wrote:
> On Mon, Aug 27, 2012 at 4:29 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Mon, Aug 27, 2012 at 04:23:31PM +0800, zhangfei gao wrote:
> >> On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
> >> <haojian.zhuang at gmail.com> wrote:
> >> > Let me summerize it. First, user space address is mapped. Then,
> >> > flushing user space
> >> > address is triggered. It's a workaround of fixing non-existed virtual
> >> > address without fixing
> >> > vmap() or any other solution. It's just a quick fix.
> >> >
> >> > Zhangfei,
> >> > I doubt that the issue may be caused by missing memory barrier.
> >> > Flushing is using
> >> > coprocessor instructions. It's a little different.
> >>
> >> Is there any limitation that dmac_map_area & dmac_flush_range
> >> supporting addr mapped from user space?
> >
> > They DEFINITELY DO NOT SUPPORT FLUSHING USER SPACE.
> 
> I agree that those API are defined to support kernel space address only.
> But the implementation is only flushing address by assembly code.

No.  Have you looked at what the dma_map_page() and scatterlist stuff
does?  It all wants to deal with a 'struct page'.  Have you looked at
how L2 caches are handled?  That wants to be able to use virt_to_phys
and similar to convert addresses, which only work on the linear mapped
region.

Have you thought about what happens when the user's page gets unmapped
or swapped out (or even just aged) ?  I don't think you've given any of
this any consideration what so ever.

There's more here than just "oh we can just pass random address X into
this function and hope that nothing goes wrong."  It's really not that
simple.


From sebastian.hesselbarth at gmail.com  Mon Aug 27 15:19:12 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Mon, 27 Aug 2012 21:19:12 +0200
Subject: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <343192fa3698ed0575444a5603ed734d@codethink.co.uk>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdbG4jkFcVP_6AmAZzciffQCamKXw7PcFnTdccyq7AMa8A@mail.gmail.com>
 <343192fa3698ed0575444a5603ed734d@codethink.co.uk>
Message-ID: <503BC830.7090705@gmail.com>

On 08/27/2012 03:43 PM, Ben Dooks wrote:
> On 20/08/2012 06:49, Linus Walleij wrote:
>> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
>> <sebastian.hesselbarth at gmail.com> wrote:
>> (...)
>>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c
>>> b/drivers/pinctrl/pinctrl-kirkwood.c
>>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>>> +
>>> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
>>> = {
>>> + { .compatible = "marvell,88f6180-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6180 },
>>> + { .compatible = "marvell,88f6190-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6190 },
>>> + { .compatible = "marvell,88f6192-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6192 },
>>> + { .compatible = "marvell,88f6281-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6281 },
>>> + { .compatible = "marvell,88f6282-pinctrl",
>>> + .data = (void *)VARIANT_MV88F6282 },
>>> + { }
>>> +};
>>
>> I'm thinking this variant should maybe be an enum... unless it is
>> strongly established somewhere in Orion/Marvell stuff.
>>
>>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device
>>> *pdev)
>>> +{
>>> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>>> + const struct of_device_id *match =
>>> + of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
>>> +
>>> + if (match) {
>>> + soc->variant = (unsigned)match->data & 0xff;
>>> + switch (soc->variant) {
>>> + case VARIANT_MV88F6180:
>>> + soc->controls = mv88f6180_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f6180_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
>>> + break;
>>> + case VARIANT_MV88F6190:
>>> + case VARIANT_MV88F6192:
>>> + soc->controls = mv88f619x_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f619x_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
>>> + break;
>>> + case VARIANT_MV88F6281:
>>> + case VARIANT_MV88F6282:
>>> + soc->controls = mv88f628x_mpp_controls;
>>> + soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
>>> + soc->modes = mv88f6xxx_mpp_modes;
>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>> + soc->gpioranges = mv88f628x_gpio_ranges;
>>> + soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
>>> + break;
>>> + }
>>> + pdev->dev.platform_data = soc;
>>> + }
>>> + return mvebu_pinctrl_probe(pdev);
>>> +}
>
> Why not have structures defining the soc-> parameters and use that in the
> of_match list?

Ben,

functionally it is equivalent and IMHO using soc structs doesn't improve
readability here. I there any other good reason to have structs for each
soc?

Sebastian


From fabio.estevam at freescale.com  Mon Aug 27 15:39:59 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 16:39:59 -0300
Subject: [PATCH] ARM: mx28evk: Add I2C EEPROM support
Message-ID: <1346096399-10114-1-git-send-email-fabio.estevam@freescale.com>

mx28evk has a free slot U50 that can be used to populate an I2C EEPROM.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx28-evk.dts |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ed92d61..a0ad71c 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -161,6 +161,12 @@
 					VDDIO-supply = <&reg_3p3v>;
 
 				};
+
+				at24 at 51 {
+					compatible = "at24,24c32";
+					pagesize = <32>;
+					reg = <0x51>;
+				};
 			};
 
 			pwm: pwm at 80064000 {
-- 
1.7.9.5




From festevam at gmail.com  Mon Aug 27 15:46:58 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 27 Aug 2012 16:46:58 -0300
Subject: [PATCH 1/3] ARM: mx28evk: Add SPI flash support
In-Reply-To: <201208271858.16842.marex@denx.de>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
 <201208271858.16842.marex@denx.de>
Message-ID: <CAOMZO5BfPnFXShGQx7eB1JcTfq39j_4iDsdd-heLBdsDfF7WJA@mail.gmail.com>

On Mon, Aug 27, 2012 at 1:58 PM, Marek Vasut <marex at denx.de> wrote:

>> +                     ssp2: ssp at 80014000 {
>> +                             #address-cells = <1>;
>> +                             #size-cells = <0>;
>> +                             compatible = "fsl,imx28-spi";
>> +                             pinctrl-names = "default";
>> +                             pinctrl-0 = <&spi2_pins_a>;
>> +                             status = "okay";
>> +
>> +                             flash: m25p80 at 0 {
>
> Shouldn't this also be sst25vf016b at 0 ?

The alias is still m25p80 in this case.

Regards,

Fabio Estevam


From swarren at wwwdotorg.org  Mon Aug 27 16:02:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 27 Aug 2012 13:02:32 -0700
Subject: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver
In-Reply-To: <503BC830.7090705@gmail.com>
References: <1344689809-6223-1-git-send-email-sebastian.hesselbarth@gmail.com>
 <1344689809-6223-4-git-send-email-sebastian.hesselbarth@gmail.com>
 <CACRpkdbG4jkFcVP_6AmAZzciffQCamKXw7PcFnTdccyq7AMa8A@mail.gmail.com>
 <343192fa3698ed0575444a5603ed734d@codethink.co.uk>
 <503BC830.7090705@gmail.com>
Message-ID: <503BD258.8050209@wwwdotorg.org>

On 08/27/2012 12:19 PM, Sebastian Hesselbarth wrote:
> On 08/27/2012 03:43 PM, Ben Dooks wrote:
>> On 20/08/2012 06:49, Linus Walleij wrote:
>>> On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth
>>> <sebastian.hesselbarth at gmail.com> wrote:
>>> (...)
>>>> diff --git a/drivers/pinctrl/pinctrl-kirkwood.c
>>>> b/drivers/pinctrl/pinctrl-kirkwood.c
>>>> +static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
>>>> +
>>>> +static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
>>>> = {
>>>> + { .compatible = "marvell,88f6180-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6180 },
>>>> + { .compatible = "marvell,88f6190-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6190 },
>>>> + { .compatible = "marvell,88f6192-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6192 },
>>>> + { .compatible = "marvell,88f6281-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6281 },
>>>> + { .compatible = "marvell,88f6282-pinctrl",
>>>> + .data = (void *)VARIANT_MV88F6282 },
>>>> + { }
>>>> +};
>>>
>>> I'm thinking this variant should maybe be an enum... unless it is
>>> strongly established somewhere in Orion/Marvell stuff.
>>>
>>>> +static int __devinit kirkwood_pinctrl_probe(struct platform_device
>>>> *pdev)
>>>> +{
>>>> + struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
>>>> + const struct of_device_id *match =
>>>> + of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
>>>> +
>>>> + if (match) {
>>>> + soc->variant = (unsigned)match->data & 0xff;
>>>> + switch (soc->variant) {
>>>> + case VARIANT_MV88F6180:
>>>> + soc->controls = mv88f6180_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f6180_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
>>>> + break;
>>>> + case VARIANT_MV88F6190:
>>>> + case VARIANT_MV88F6192:
>>>> + soc->controls = mv88f619x_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f619x_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
>>>> + break;
>>>> + case VARIANT_MV88F6281:
>>>> + case VARIANT_MV88F6282:
>>>> + soc->controls = mv88f628x_mpp_controls;
>>>> + soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
>>>> + soc->modes = mv88f6xxx_mpp_modes;
>>>> + soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
>>>> + soc->gpioranges = mv88f628x_gpio_ranges;
>>>> + soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
>>>> + break;
>>>> + }
>>>> + pdev->dev.platform_data = soc;
>>>> + }
>>>> + return mvebu_pinctrl_probe(pdev);
>>>> +}
>>
>> Why not have structures defining the soc-> parameters and use that in the
>> of_match list?
> 
> Ben,
> 
> functionally it is equivalent and IMHO using soc structs doesn't improve
> readability here. I there any other good reason to have structs for each
> soc?

Well, it does change from 6 assignments down to one, and remove the need
for a switch statement - i.e. all of the code quoted above becomes just
roughly:

*soc = *match->data;



From swarren at wwwdotorg.org  Mon Aug 27 16:06:29 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 27 Aug 2012 13:06:29 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly
 for non-OOB
In-Reply-To: <503B9F31.5050502@broadcom.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com>
Message-ID: <503BD345.6030501@wwwdotorg.org>

On 08/27/2012 09:24 AM, Arend van Spriel wrote:
> On 08/27/2012 12:25 PM, Wei Ni wrote:
>> In case of inband interrupts, if we handle the interrupt in dpc thread,
>> two level of thread switching takes place to process wifi interrupts.
>> One in SDHCI driver and the other in Wifi driver. This may cause the
>> system
>> instability.
> 
> Looking into the sdhci/mmc code indeed shows that the brcmfmac irq
> handler is not called in true IRQ context. So the dpc thread may add
> unnecessary complexity, but to me there is not indication that there is
> a stability issue.
> 
>> Because the SDHCI calls sdio_irq_thread() to handle the irq, this
>> thread locks
>> mmc host and calls wifi handler. It expects WiFi handler to be quick and
>> enables sdio interrupt from card at end. If wifi handler defers this
>> work for
>> a different thread, sdio_irq_thread() will be stuck on next wifi
>> interrupt
>> since mmc lock is not freed.
> 
> Not sure if I can follow this explanation. The isr is called with host
> claimed (by sdio_irq_thread) and all it does is at a linked list member
> and signal the dpc thread. After doing this the host is released.

Is the issue something like the ISR handler or first level of threading
does:

* Trigger DPC
* Re-enable interrupt

So that the interrupt then fires again before the triggered DPC can run
to handle/clear it, thus causing an interrupt storm?

Whereas handling the interrupt directly prevents this race condition?


From sylvester.nawrocki at gmail.com  Mon Aug 27 16:12:09 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Mon, 27 Aug 2012 22:12:09 +0200
Subject: [PATCH] ARM: S3C24XX: Add .get_rate callback for "camif-upll" clock
Message-ID: <1346098329-32059-1-git-send-email-sylvester.nawrocki@gmail.com>

Add missing get_rate callback for the "camif-upll" clock, so frequency
of this clock is properly reported with clk_get_rate().

Signed-off-by: Sylwester Nawrocki <sylvester.nawrocki at gmail.com>
---
 arch/arm/mach-s3c24xx/clock-s3c2440.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d..749220f 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
 	return 0;
 }

+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
+
+	if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
+		return parent_rate;
+
+	camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
+
+	return parent_rate / (camdivn + 1) / 2;
+}
+
 /* Extra S3C2440 clocks */

 static struct clk s3c2440_clk_cam = {
@@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = {
 	.name		= "camif-upll",
 	.ops		= &(struct clk_ops) {
 		.set_rate	= s3c2440_camif_upll_setrate,
+		.get_rate	= s3c2440_camif_upll_getrate,
 		.round_rate	= s3c2440_camif_upll_round,
 	},
 };
--
1.7.4.1



From jon-hunter at ti.com  Mon Aug 27 16:30:13 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Mon, 27 Aug 2012 15:30:13 -0500
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9BA63D@DBDE01.ent.ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
 <50359C64.40603@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9BA63D@DBDE01.ent.ti.com>
Message-ID: <503BD8D5.5060400@ti.com>

Hi Afzal,

On 08/27/2012 05:37 AM, Mohammed, Afzal wrote:
> On Thu, Aug 23, 2012 at 08:28:44, Hunter, Jon wrote:

[snip]

>> I understand that this is based upon how timings for onenand and tusb
>> are being calculated today, but I am not sure that this is the way to go
>> for all devices. Personally, I would like to see us get away from how
>> those devices are calculating timings for any new device.
> 
> You cannot do away with many of the those, as logically they
> are right. Eg. read data should be available at access time,
> assuming a zero data hold time, we can very well derive an
> expression as,

I am not saying that we do away with them for current devices, just
maintain them as is.

> read de-assertion time (oe_off) = access time plus 1 gpmc clock,
> 
> and this is what the existing calculations do, and also the
> generic routine. There could be other constraints, but this
> certainly should be one (I do realize that oe_off could be
> optimized to be less than access time, by relying on read
> hold time, then again effect of it would be in similar way
> for different peripherals, but let's forget about
> optimization in the beginning)
> 
>> In general, I am concerned that we are abstracting the timings further
>> from the actual register fields. For example, the timings parameter
>> "t_ceasu" is described "address setup to CS valid" which is not
>> incorrect but this value is really just programming the CSONTIME field
>> and so why not call this cs_on?
> 
> Timing fields of struct gpmc_device_timings are selected such
> that they should be bindable by DT. At least one of the peripheral
> datasheet has these fields.

Right, but these are not applicable to every device and so I worry this
could be confusing. However, more documentation may help clear this up.

> If user knows timings in terms of
> gpmc values, he can directly use struct gpmc_timings, but
> then all the values should be updated in struct gpmc_timings.
> User should not update some of the values in terms of
> peripheral timings, others in terms of gpmc timings, that
> would make things complex and does not seem the right way
> to me.
> 
> cs_on and other gpmc aware timings could be binded by DT, not as
> peripheral timing, but as gpmc timing.
> 
> Bindings for peripheral DT timings should be something that
> can be obtained from peripheral datasheet, here accidentally
> it is same as gpmc timings, but not most timings are this way.
> Also there could be other constraints that can come for cs_on,
> even though I have not come across any till now.
> 
>>
>> So although this may consolidate how the timings are calculated today, I
>> am concerned it will be confusing to add timings for a new device. At
>> least if I am calculating timings, I am taking the timing information
>> for the device and translating that to the how I need to program the
>> gpmc register fields.
> 
> If I am not wrong, GPMC IP has been present for around a
> decade, and so far I have not come across any generic time
> calculation method that can be applied to all peripherals.

Yes not an easy problem to solve :-(

> Getting to work same peripheral for a different gpmc
> frequency is another problem.
> 
> Here we are trying to generalize based on the understanding of
> gpmc & peripheral timings, as well as by a kind of reverse
> engineering without most of the hardware or datasheet. Think of
> this as an attempt to create one, let it evolve and become a
> robust one. If a new user want to add a peripheral, let him add
> support, input timings are selected such that it is found in
> peripheral datasheet, if that does not work, let him try
> to add any new timing field or alter existing expression
> as he deems to be proper and verify that it does not break
> others. And I can help provided I am not heavily loaded
> with other works.

So long as it is maintainable ;-)

> And at least for initial users, they are expected to have
> some grasp on how to calculate timings, such a user will
> not be much worried about your 3 concerns above, anyway as
> of now they need to have a good grasp on it.

I would consider myself to be an initial user and I am concerned,
doesn't that count?

An example, would be the following where you have 4 timing parameters
for access time. You need to dig through the code to understand how
these are being used.

+	u32     t_aa;		/* access time from ADV assertion */
+	u32     t_iaa;		/* initial access time */
+	u32     t_oe;		/* access time from OE assertion */
+	u32     t_ce;		/* access time from CS asertion */

> Meanwhile I will try to document more.

Yes more documentation is definitely needed.

Cheers
Jon


From broonie at opensource.wolfsonmicro.com  Mon Aug 27 16:45:51 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 27 Aug 2012 13:45:51 -0700
Subject: [PATCH] ASoC: SAMSUNG: Add SND_SOC_DAIFMT_CONT option for
 snd_soc_set_fmt()
In-Reply-To: <003101cd8367$3476e650$9d64b2f0$@samsung.com>
References: <003101cd8367$3476e650$9d64b2f0$@samsung.com>
Message-ID: <20120827204550.GA4400@opensource.wolfsonmicro.com>

On Sun, Aug 26, 2012 at 05:45:54PM +0900, ????? wrote:
> SND_SOC_DAIFMT_CONT option is now needed because of below commit:
> 
> ASoC: Allow DAI formats to be specified in the dai_link

Clearly it's not a direct consequence of this commit, that just
introduces a new optional facility which...

>  	/* Set the cpu DAI configuration */
>  	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B
> +				| SND_SOC_DAIFMT_CONT
>  				| SND_SOC_DAIFMT_IB_NF
>  				| SND_SOC_DAIFMT_CBS_CFS);

...isn't being used by the driver.

Looking at the above it looks like the PCM driver is doing something
very odd - _CONT doesn't make a whole lot of sense on the slave side,
it's related to the clock generation so should have no effect at all on
the slave side.  The driver code looks reasonably sensible though.

What specifically is going wrong here?


From shawn.guo at linaro.org  Mon Aug 27 16:45:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 04:45:56 +0800
Subject: [PATCH V3] ARM: mxs: Update DENX M28 machine and dts file
In-Reply-To: <1345985971-12061-1-git-send-email-marex@denx.de>
References: <1345985971-12061-1-git-send-email-marex@denx.de>
Message-ID: <20120827204554.GA2281@r65073-Latitude-D630>

On Sun, Aug 26, 2012 at 02:59:31PM +0200, Marek Vasut wrote:
> Update the mach-mxs machine by removing the enet_clkout(). The new
> revision of the board doesn't need that. Also, update the DTS file
> with all the new drivers pulled in the mainline recently, that is,
> SPI, LRADC, USB.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <fabio.estevam at freescale.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>

Applied, thanks.


From aaro.koskinen at iki.fi  Mon Aug 27 17:03:23 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 28 Aug 2012 00:03:23 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
Message-ID: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>

When booting kernel on RM-680/N950, the console is flooded with:

[    6.894348] In-band Error seen by MPU  at address 0
[    6.894348] ------------[ cut here ]------------
[    6.894378] WARNING: at arch/arm/mach-omap2/omap_l3_smx.c:162 omap3_l3_app_irq+0xd4/0x12c()
[    6.894378] Modules linked in:
[    6.894409] Backtrace:
[    6.894409] [<c0012440>] (dump_backtrace+0x0/0x10c) from [<c02fb698>] (dump_stack+0x18/0x1c)
[    6.894439]  r6:c002de58 r5:00000009 r4:00000000 r3:c0880180
[    6.894470] [<c02fb680>] (dump_stack+0x0/0x1c) from [<c0039854>] (warn_slowpath_common+0x54/0x6c)
[    6.894500] [<c0039800>] (warn_slowpath_common+0x0/0x6c) from [<c0039890>] (warn_slowpath_null+0x24/0x2c)
[    6.894500]  r8:0000000a r7:00000000 r6:f8001400 r5:00000000 r4:84001b00
[    6.894500] r3:00000009
[    6.894561] [<c003986c>] (warn_slowpath_null+0x0/0x2c) from [<c002de58>] (omap3_l3_app_irq+0xd4/0x12c)
[    6.894561] [<c002dd84>] (omap3_l3_app_irq+0x0/0x12c) from [<c008561c>] (handle_irq_event_percpu+0x54/0x19c)
[    6.894592]  r7:00000000 r6:00000000 r5:c082c710 r4:ef072340
[    6.894622] [<c00855c8>] (handle_irq_event_percpu+0x0/0x19c) from [<c00857c4>] (handle_irq_event+0x60/0x80)
[    6.894653] [<c0085764>] (handle_irq_event+0x0/0x80) from [<c0088300>] (handle_level_irq+0xb4/0x134)
[    6.894653]  r5:c082c710 r4:c082c6c0
[    6.894683] [<c008824c>] (handle_level_irq+0x0/0x134) from [<c0084e18>] (generic_handle_irq+0x2c/0x44)
[    6.894683]  r6:ef02c000 r5:c0829014 r4:c0841e18 r3:c008824c
[    6.894744] [<c0084dec>] (generic_handle_irq+0x0/0x44) from [<c000f228>] (handle_IRQ+0x54/0xb8)
[    6.894744] [<c000f1d4>] (handle_IRQ+0x0/0xb8) from [<c000873c>] (omap3_intc_handle_irq+0x68/0x7c)
[    6.894775]  r8:c08415cc r7:0000000a r6:c0898c38 r5:ef02de88 r4:fa200000
[    6.894775] r3:00000000
[    6.894805] [<c00086d4>] (omap3_intc_handle_irq+0x0/0x7c) from [<c0302e80>] (__irq_svc+0x40/0x54)
[    6.894836] Exception stack(0xef02de88 to 0xef02ded0)
[    6.894836] de80:                   f0048000 00000000 00007000 00000000 0000 3035 f004bfca
[    6.894866] dea0: 00000000 00000000 c08415cc c0898140 ef02c000 ef02def4 ef02 def8 ef02ded0
[    6.894866] dec0: c042b1dc c0016efc 20000013 ffffffff
[    6.894897]  r7:ef02debc r6:ffffffff r5:20000013 r4:c0016efc
[    6.894927] [<c0016ed0>] (_memset_io+0x0/0x50) from [<c042b1dc>] (omap_sram_init+0x228/0x56c)
[    6.894927]  r8:c0445cf4 r7:c0417208 r6:c0898140 r5:c0899840 r4:c0899a3c
[    6.894927] r3:f004f000
[    6.894989] [<c042afb4>] (omap_sram_init+0x0/0x56c) from [<c041f01c>] (omap_sdrc_init+0x18/0xb8)
[    6.894989]  r6:c0898140 r5:c0899840 r4:c0899840 r3:0005e601
[    6.895019] [<c041f004>] (omap_sdrc_init+0x0/0xb8) from [<c0427e38>] (rm680_init+0x34/0xc0)
[    6.895050]  r5:c04518e0 r4:c0875da0
[    6.895080] [<c0427e04>] (rm680_init+0x0/0xc0) from [<c0419934>] (customize_machine+0x24/0x30)
[    6.895080]  r5:00000003 r4:00000000
[    6.895111] [<c0419910>] (customize_machine+0x0/0x30) from [<c00088e0>] (do_one_initcall+0x11c/0x184)
[    6.895141] [<c00087c4>] (do_one_initcall+0x0/0x184) from [<c041799c>] (kernel_init+0x100/0x1c4)
[    6.895141] [<c041789c>] (kernel_init+0x0/0x1c4) from [<c003ef18>] (do_exit+0x0/0x794)
[    6.895172] ---[ end trace 1b75b31a271a0d00 ]---

This is repeated maybe a thousand times. While the root cause remains
unknown (they seem to occur during SDRC and DMA init), the errors should
be at least ratelimited so that user will also have chance to see other
boot messages.

Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>
---
 arch/arm/mach-omap2/omap_l3_smx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index acc2164..e3b4948 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -155,11 +155,11 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
 	u8 multi = error & L3_ERROR_LOG_MULTI;
 	u32 address = omap3_l3_decode_addr(error_addr);
 
-	pr_err("%s seen by %s %s at address %x\n",
+	pr_err_ratelimited("%s seen by %s %s at address %x\n",
 			omap3_l3_code_string(code),
 			omap3_l3_initiator_string(initid),
 			multi ? "Multiple Errors" : "", address);
-	WARN_ON(1);
+	WARN_ON_ONCE(1);
 
 	return IRQ_HANDLED;
 }
-- 
1.7.2.5



From sboyd at codeaurora.org  Mon Aug 27 17:18:39 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 27 Aug 2012 14:18:39 -0700
Subject: [PATCH] ARM: MSM: Implement read_current_timer for msm timers
In-Reply-To: <1345817604-9004-2-git-send-email-will.deacon@arm.com>
Message-ID: <1346102319-24497-1-git-send-email-sboyd@codeaurora.org>

Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

I have some patches to send that add DT support to the MSM timer that
this conflicts with slightly. I'm not too concerned though, but we may
want to decide what tree this goes through when I send out those patches.

 arch/arm/mach-msm/timer.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 81280825..1997ab1 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -25,6 +25,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
+#include <asm/delay.h>
 
 #include <mach/msm_iomap.h>
 #include <mach/cpu.h>
@@ -172,6 +173,16 @@ static notrace u32 msm_sched_clock_read(void)
 	return msm_clocksource.read(&msm_clocksource);
 }
 
+static int msm_read_current_timer(unsigned long *timer_val)
+{
+	*timer_val = msm_clocksource.read(&msm_clocksource);
+	return 0;
+}
+
+static struct delay_timer msm_delay_timer = {
+	.read_current_timer = msm_read_current_timer,
+};
+
 static void __init msm_timer_init(void)
 {
 	struct clock_event_device *ce = &msm_clockevent;
@@ -240,6 +251,8 @@ err:
 		pr_err("clocksource_register failed\n");
 	setup_sched_clock(msm_sched_clock_read,
 			cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
+	msm_delay_timer.freq = dgt_hz;
+	register_current_timer_delay(&msm_delay_timer);
 }
 
 struct sys_timer msm_timer = {
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From santosh.shilimkar at ti.com  Mon Aug 27 17:35:57 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 27 Aug 2012 14:35:57 -0700
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
Message-ID: <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>

On Mon, Aug 27, 2012 at 2:03 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
>
> When booting kernel on RM-680/N950, the console is flooded with:
>
> [    6.894348] In-band Error seen by MPU  at address 0
> [    6.894348] ------------[ cut here ]------------
> [    6.894378] WARNING: at arch/arm/mach-omap2/omap_l3_smx.c:162
> omap3_l3_app_irq+0xd4/0x12c()
> [    6.894378] Modules linked in:
> [    6.894409] Backtrace:
> [    6.894409] [<c0012440>] (dump_backtrace+0x0/0x10c) from [<c02fb698>]
> (dump_stack+0x18/0x1c)
> [    6.894439]  r6:c002de58 r5:00000009 r4:00000000 r3:c0880180
> [    6.894470] [<c02fb680>] (dump_stack+0x0/0x1c) from [<c0039854>]
> (warn_slowpath_common+0x54/0x6c)
> [    6.894500] [<c0039800>] (warn_slowpath_common+0x0/0x6c) from
> [<c0039890>] (warn_slowpath_null+0x24/0x2c)
> [    6.894500]  r8:0000000a r7:00000000 r6:f8001400 r5:00000000
> r4:84001b00
> [    6.894500] r3:00000009
> [    6.894561] [<c003986c>] (warn_slowpath_null+0x0/0x2c) from
> [<c002de58>] (omap3_l3_app_irq+0xd4/0x12c)
> [    6.894561] [<c002dd84>] (omap3_l3_app_irq+0x0/0x12c) from [<c008561c>]
> (handle_irq_event_percpu+0x54/0x19c)
> [    6.894592]  r7:00000000 r6:00000000 r5:c082c710 r4:ef072340
> [    6.894622] [<c00855c8>] (handle_irq_event_percpu+0x0/0x19c) from
> [<c00857c4>] (handle_irq_event+0x60/0x80)
> [    6.894653] [<c0085764>] (handle_irq_event+0x0/0x80) from [<c0088300>]
> (handle_level_irq+0xb4/0x134)
> [    6.894653]  r5:c082c710 r4:c082c6c0
> [    6.894683] [<c008824c>] (handle_level_irq+0x0/0x134) from [<c0084e18>]
> (generic_handle_irq+0x2c/0x44)
> [    6.894683]  r6:ef02c000 r5:c0829014 r4:c0841e18 r3:c008824c
> [    6.894744] [<c0084dec>] (generic_handle_irq+0x0/0x44) from
> [<c000f228>] (handle_IRQ+0x54/0xb8)
> [    6.894744] [<c000f1d4>] (handle_IRQ+0x0/0xb8) from [<c000873c>]
> (omap3_intc_handle_irq+0x68/0x7c)
> [    6.894775]  r8:c08415cc r7:0000000a r6:c0898c38 r5:ef02de88
> r4:fa200000
> [    6.894775] r3:00000000
> [    6.894805] [<c00086d4>] (omap3_intc_handle_irq+0x0/0x7c) from
> [<c0302e80>] (__irq_svc+0x40/0x54)
> [    6.894836] Exception stack(0xef02de88 to 0xef02ded0)
> [    6.894836] de80:                   f0048000 00000000 00007000 00000000
> 0000 3035 f004bfca
> [    6.894866] dea0: 00000000 00000000 c08415cc c0898140 ef02c000 ef02def4
> ef02 def8 ef02ded0
> [    6.894866] dec0: c042b1dc c0016efc 20000013 ffffffff
> [    6.894897]  r7:ef02debc r6:ffffffff r5:20000013 r4:c0016efc
> [    6.894927] [<c0016ed0>] (_memset_io+0x0/0x50) from [<c042b1dc>]
> (omap_sram_init+0x228/0x56c)
> [    6.894927]  r8:c0445cf4 r7:c0417208 r6:c0898140 r5:c0899840
> r4:c0899a3c
> [    6.894927] r3:f004f000
> [    6.894989] [<c042afb4>] (omap_sram_init+0x0/0x56c) from [<c041f01c>]
> (omap_sdrc_init+0x18/0xb8)
> [    6.894989]  r6:c0898140 r5:c0899840 r4:c0899840 r3:0005e601
> [    6.895019] [<c041f004>] (omap_sdrc_init+0x0/0xb8) from [<c0427e38>]
> (rm680_init+0x34/0xc0)
> [    6.895050]  r5:c04518e0 r4:c0875da0
> [    6.895080] [<c0427e04>] (rm680_init+0x0/0xc0) from [<c0419934>]
> (customize_machine+0x24/0x30)
> [    6.895080]  r5:00000003 r4:00000000
> [    6.895111] [<c0419910>] (customize_machine+0x0/0x30) from [<c00088e0>]
> (do_one_initcall+0x11c/0x184)
> [    6.895141] [<c00087c4>] (do_one_initcall+0x0/0x184) from [<c041799c>]
> (kernel_init+0x100/0x1c4)
> [    6.895141] [<c041789c>] (kernel_init+0x0/0x1c4) from [<c003ef18>]
> (do_exit+0x0/0x794)
> [    6.895172] ---[ end trace 1b75b31a271a0d00 ]---
>
> This is repeated maybe a thousand times. While the root cause remains
> unknown (they seem to occur during SDRC and DMA init), the errors should
> be at least ratelimited so that user will also have chance to see other
> boot messages.
>
> Signed-off-by: Aaro Koskinen <aaro.koskinen at iki.fi>
> ---
>  arch/arm/mach-omap2/omap_l3_smx.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_l3_smx.c
> b/arch/arm/mach-omap2/omap_l3_smx.c
> index acc2164..e3b4948 100644
> --- a/arch/arm/mach-omap2/omap_l3_smx.c
> +++ b/arch/arm/mach-omap2/omap_l3_smx.c
> @@ -155,11 +155,11 @@ static irqreturn_t omap3_l3_block_irq(struct
> omap3_l3 *l3,
>         u8 multi = error & L3_ERROR_LOG_MULTI;
>         u32 address = omap3_l3_decode_addr(error_addr);
>
> -       pr_err("%s seen by %s %s at address %x\n",
> +       pr_err_ratelimited("%s seen by %s %s at address %x\n",
>                         omap3_l3_code_string(code),
>                         omap3_l3_initiator_string(initid),
>                         multi ? "Multiple Errors" : "", address);
> -       WARN_ON(1);
> +       WARN_ON_ONCE(1);
>
The issue needs to be fixed instead of WARN_ON_ONCE() and then
just moving ahead. Interconnect in bad states is really bad state and you
won't have reliable operations post that on SOC.

Regards
Santosh


From olof at lixom.net  Mon Aug 27 17:53:26 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 14:53:26 -0700
Subject: [PATCH 2/5] Documentation: add description of DT binding for the
 gpio-mvebu driver
In-Reply-To: <1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1344691906-15985-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120827215133.GA7431@lumpy>

Hi,

On Sat, Aug 11, 2012 at 03:31:43PM +0200, Thomas Petazzoni wrote:
> +- gpio-controller: marks the device node as a gpio controller
> +
> +- ngpios: number of GPIOs this controller has
> +
> +- #gpio-cells: Should be one. It is the pin number.

Most platforms will hit a need to encode polarity of the GPIO, in
particular on inputs. Having an extra cell for flags is quite useful.



From jaccon.bastiaansen at gmail.com  Mon Aug 27 17:53:51 2012
From: jaccon.bastiaansen at gmail.com (Jaccon Bastiaansen)
Date: Mon, 27 Aug 2012 23:53:51 +0200
Subject: [PATCH v2] cs89x0 : packet reception not working
Message-ID: <1346104431-3784-1-git-send-email-jaccon.bastiaansen@gmail.com>

The RxCFG register of the CS89x0 could be configured incorrectly
(because of misplaced parentheses), resulting in the disabling
of packet reception.

Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
---
 drivers/net/ethernet/cirrus/cs89x0.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/cirrus/cs89x0.c b/drivers/net/ethernet/cirrus/cs89x0.c
index 845b202..1384469 100644
--- a/drivers/net/ethernet/cirrus/cs89x0.c
+++ b/drivers/net/ethernet/cirrus/cs89x0.c
@@ -1243,6 +1243,7 @@ static void set_multicast_list(struct net_device *dev)
 {
 	struct net_local *lp = netdev_priv(dev);
 	unsigned long flags;
+	u16 cfg;
 
 	spin_lock_irqsave(&lp->lock, flags);
 	if (dev->flags & IFF_PROMISC)
@@ -1260,11 +1261,10 @@ static void set_multicast_list(struct net_device *dev)
 	/* in promiscuous mode, we accept errored packets,
 	 * so we have to enable interrupts on them also
 	 */
-	writereg(dev, PP_RxCFG,
-		 (lp->curr_rx_cfg |
-		  (lp->rx_mode == RX_ALL_ACCEPT)
-		  ? (RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL)
-		  : 0));
+	cfg = lp->curr_rx_cfg;
+	if (lp->rx_mode == RX_ALL_ACCEPT)
+		cfg |= RX_CRC_ERROR_ENBL | RX_RUNT_ENBL | RX_EXTRA_DATA_ENBL;
+	writereg(dev, PP_RxCFG, cfg);
 	spin_unlock_irqrestore(&lp->lock, flags);
 }
 
-- 
1.7.1



From aaro.koskinen at iki.fi  Mon Aug 27 18:02:54 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 28 Aug 2012 01:02:54 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
Message-ID: <20120827220254.GA783@harshnoise.musicnaut.iki.fi>

Hi,

On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote:
> > -       pr_err("%s seen by %s %s at address %x\n",
> > +       pr_err_ratelimited("%s seen by %s %s at address %x\n",
> >                         omap3_l3_code_string(code),
> >                         omap3_l3_initiator_string(initid),
> >                         multi ? "Multiple Errors" : "", address);
> > -       WARN_ON(1);
> > +       WARN_ON_ONCE(1);
> >
> The issue needs to be fixed instead of WARN_ON_ONCE() and then
> just moving ahead. Interconnect in bad states is really bad state and you
> won't have reliable operations post that on SOC.

How printing megabytes of identical stack traces helps anything?

This has been there always (since the L3 driver was added) on every boot
with N950/N9 (which BTW are HS devices, not sure if that has anything
to do with it). There is no apparent effect on device functionality,
at least nothing unusual has been observed...

Is there any documentation how to interpret and debug this error report?

A.


From olof at lixom.net  Mon Aug 27 18:05:53 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 15:05:53 -0700
Subject: [PATCH v5 1/2] ARM: Make a compile firmware conditionally
In-Reply-To: <20120824083351.GA25369@july>
References: <20120824083351.GA25369@july>
Message-ID: <20120827220553.GB7431@lumpy>

Hi,

On Fri, Aug 24, 2012 at 05:33:51PM +0900, Kyungmin Park wrote:
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index 283fa1d..5b097ca 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -21,6 +21,9 @@ config ARM_VIC_NR
>  	  The maximum number of VICs available in the system, for
>  	  power management.
>  
> +config ARM_FIRMWARE
> +	bool
> +

I don't think you need a config option for this now, it only adds 12
bytes of data to the kernel and it makes the below simpler.

> diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
> new file mode 100644
> index 0000000..99c97ff
> --- /dev/null
> +++ b/arch/arm/include/asm/firmware.h
> @@ -0,0 +1,27 @@
> +/*
> + *  Copyright (C) 2012 Samsung Electronics.
> + *  Kyungmin Park <kyungmin.park at samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_ARM_FIRMWARE_H
> +#define __ASM_ARM_FIRMWARE_H
> +
> +struct firmware_ops {
> +	int	(*do_idle)(void);
> +	void	(*cpu_boot)(int cpu);
> +};
> +
> +extern struct firmware_ops *firmware_ops;
> +
> +#ifdef CONFIG_ARM_FIRMWARE
> +#define call_firmware_op(op, ...)					\
> +	((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : 0)
> +#else
> +#define call_firmware_op(op, ...)		do { } while (0)
> +#endif

If you always include the firmware.c file, then you don't need the ifdef
above either, since the default version fills in dummy versions.


-Olof


From shawn.guo at linaro.org  Mon Aug 27 18:08:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 06:08:32 +0800
Subject: [PATCH v2 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346052285-4344-2-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-2-git-send-email-b29396@freescale.com>
Message-ID: <20120827220830.GB2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 03:24:39PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Add regmap based syscon driver.
> This is usually used for access misc bits in registers which does not belong
> to a specific module, for example, IMX IOMUXC GPR and ANATOP.
> With this driver, client can use generic regmap API to access registers
> which are registered into syscon.
> 
> Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog:
> v1->v2:
>  * provide a way of retrieving the regmap, suggested by Mark Brown.
>  * delete imx-syscon io accessors and using generic regmap API for client drivers.
>  * change to a more generic name for other SoCs to use.
> ---
>  .../devicetree/bindings/mfd/imx-syscon.txt         |   11 ++

So, this file should be renamed as well.

>  drivers/mfd/Kconfig                                |    7 +
>  drivers/mfd/Makefile                               |    1 +
>  drivers/mfd/syscon.c                               |  169 ++++++++++++++++++++
>  include/linux/mfd/syscon.h                         |   22 +++
>  5 files changed, 210 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> new file mode 100644
> index 0000000..c1a13b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> @@ -0,0 +1,11 @@
> +* System Controller Registers R/W driver
> +
> +Required properties:
> +- compatible: Should contain "syscon".
> +- reg: the register range can be access from syscon
> +
> +Examples:
> +gpr: iomuxc-gpr at 020e0000 {
> +	compatible = "fsl,imx6q-iomuxc", "syscon";
> +	reg = <0x020e0000 0x38>;
> +};
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index b1a1462..4a6c48e 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -993,6 +993,13 @@ config MFD_ANATOP
>  	  MFD controller. This controller embeds regulator and
>  	  thermal devices for Freescale i.MX platforms.
>  
> +config MFD_SYSCON
> +        bool "System Controller Register R/W Based on Regmap"
> +        select REGMAP_MMIO
> +        help
> +          Select this option to enable accessing system control registers
> +	  via regmap.
> +
>  config MFD_PALMAS
>  	bool "Support for the TI Palmas series chips"
>  	select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 79dd22d..8384bc9 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
>  obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
>  obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
>  obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
> +obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
>  obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
> diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
> new file mode 100644
> index 0000000..da2464f
> --- /dev/null
> +++ b/drivers/mfd/syscon.c
> @@ -0,0 +1,169 @@
> +/*
> + * System Control Driver
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro Ltd.
> + *
> + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +static struct platform_driver syscon_driver;
> +
> +struct syscon {
> +	struct device *dev;
> +	void __iomem *base;
> +	struct regmap *regmap;
> +};
> +
> +static int syscon_match(struct device *dev, void *data)
> +{
> +	struct syscon *syscon = dev_get_drvdata(dev);
> +	struct device_node *dn = data;
> +
> +	return (syscon->dev->of_node == dn) ? 1 : 0;
> +}
> +
> +static struct regmap *syscon_node_to_regmap(struct device_node *np)
> +{
> +	struct syscon *syscon;
> +	struct device *dev;
> +
> +	dev = driver_find_device(&syscon_driver.driver, NULL, np,
> +				 syscon_match);
> +	of_node_put(np);
> +
> +	if (!dev)
> +		return ERR_PTR(-EPROBE_DEFER);
> +
> +	syscon = dev_get_drvdata(dev);
> +
> +	return syscon->regmap;
> +}
> +
> +struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
> +{
> +	struct device_node *syscon_np;
> +
> +	syscon_np = of_find_compatible_node(NULL, NULL, s);
> +	if (!syscon_np)
> +		return ERR_PTR(-ENODEV);
> +
> +	return syscon_node_to_regmap(syscon_np);
> +}
> +
> +struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
> +					const char *property)
> +{
> +	struct device_node *syscon_np;
> +
> +	syscon_np = of_parse_phandle(np, property, 0);
> +	if (!syscon_np)
> +		return ERR_PTR(-ENODEV);
> +
> +	return syscon_node_to_regmap(syscon_np);
> +}

The above two APIs are all about finding the device_node for syscon,
and can be done by clients in whatever way that is easy for them.
Then we can save these APIs and export syscon_node_to_regmap directly.

> +
> +static const struct of_device_id of_syscon_match[] = {
> +	{ .compatible = "syscon", },
> +	{ },
> +};
> +
> +static struct regmap_config syscon_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
> +
> +static int __devinit syscon_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct syscon *syscon;
> +	struct resource res;
> +	int ret;
> +
> +	if (!np)
> +		return -ENOENT;
> +
> +	syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
> +			    GFP_KERNEL);
> +	if (!syscon)
> +		return -ENOMEM;
> +
> +	syscon->base = of_iomap(np, 0);
> +	if (!syscon->base)
> +		return -EADDRNOTAVAIL;
> +
> +	ret = of_address_to_resource(np, 0, &res);
> +	if (ret)
> +		return ret;
> +
> +	syscon_regmap_config.max_register = res.end - res.start - 3;
> +	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
> +					&syscon_regmap_config);
> +	if (IS_ERR(syscon->regmap)) {
> +		dev_err(&pdev->dev, "regmap init failed\n");
> +		return PTR_ERR(syscon->regmap);
> +	}
> +
> +	regcache_cache_only(syscon->regmap, false);
> +
> +	syscon->dev = &pdev->dev;
> +	platform_set_drvdata(pdev, syscon);
> +
> +	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
> +		res.start, res.end);
> +
> +	return 0;
> +}
> +
> +static int __devexit syscon_remove(struct platform_device *pdev)
> +{
> +	struct syscon *syscon;
> +
> +	syscon = platform_get_drvdata(pdev);
> +	iounmap(syscon->base);
> +	platform_set_drvdata(pdev, NULL);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver syscon_driver = {
> +	.driver = {
> +		.name = "syscon",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_syscon_match,
> +	},
> +	.probe		= syscon_probe,
> +	.remove		= syscon_remove,
> +};
> +
> +static int __init syscon_init(void)
> +{
> +	return platform_driver_register(&syscon_driver);
> +}
> +postcore_initcall(syscon_init);
> +
> +static void __exit anatop_exit(void)

s/anatop_exit/syscon_exit

> +{
> +	platform_driver_unregister(&syscon_driver);
> +}
> +module_exit(anatop_exit);

Ditto.

Regards,
Shawn

> +
> +MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
> +MODULE_DESCRIPTION("System Control driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
> new file mode 100644
> index 0000000..990d7cf
> --- /dev/null
> +++ b/include/linux/mfd/syscon.h
> @@ -0,0 +1,22 @@
> +/*
> + * System Control Driver
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2012 Linaro Ltd.
> + *
> + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __LINUX_MFD_SYSCON_H__
> +#define __LINUX_MFD_SYSCON_H__
> +
> +extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
> +extern struct regmap *syscon_regmap_lookup_by_phandle(
> +					struct device_node *np,
> +					const char *property);
> +#endif /* __LINUX_MFD_SYSCON_H__ */
> -- 
> 1.7.0.4
> 
> 


From olof at lixom.net  Mon Aug 27 18:10:30 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 15:10:30 -0700
Subject: [PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
In-Reply-To: <20120824083357.GA25384@july>
References: <20120824083357.GA25384@july>
Message-ID: <20120827221030.GC7431@lumpy>

Hi,

See below.

On Fri, Aug 24, 2012 at 05:33:57PM +0900, Kyungmin Park wrote:

> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 9b58024..8ee779c 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)	+= mct.o
>  
>  obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
>  
> +obj-$(CONFIG_ARM_FIRMWARE)	+= exynos-smc.o firmware.o
> +
> +plus_sec := $(call as-instr,.arch_extension sec,+sec)
> +AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)

Again, no need for a config option here.

> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> new file mode 100644
> index 0000000..a144593
> --- /dev/null
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -0,0 +1,37 @@
> +/*
> + *  Copyright (C) 2012 Samsung Electronics.
> + *  Kyungmin Park <kyungmin.park at samsung.com>
> + *
> + * This program is free software,you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +
> +#include <asm/firmware.h>
> +
> +#include "smc.h"
> +
> +static int exynos_do_idle(void)
> +{
> +        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
> +        return 0;
> +}
> +
> +static void exynos_cpu_boot(int cpu)
> +{
> +	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> +}
> +
> +static struct firmware_ops exynos_firmware_ops __initdata = {
> +	.do_idle	= exynos_do_idle,
> +	.cpu_boot	= exynos_cpu_boot,
> +};
> +
> +int __init exynos_firmware_init(void)
> +{
> +	firmware_ops = exynos_firmware_ops;
> +	return 0;
> +}

If you add a check for SMC presence/execution mode here, then you can
make this a runtime instead of boot time option, thus making it possible
to build a kernel that boots and runs both with and without SMC support.


-Olof


From santosh.shilimkar at ti.com  Mon Aug 27 18:12:07 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 27 Aug 2012 15:12:07 -0700
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
Message-ID: <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>

On Mon, Aug 27, 2012 at 3:02 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> Hi,
>
> On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote:
>> > -       pr_err("%s seen by %s %s at address %x\n",
>> > +       pr_err_ratelimited("%s seen by %s %s at address %x\n",
>> >                         omap3_l3_code_string(code),
>> >                         omap3_l3_initiator_string(initid),
>> >                         multi ? "Multiple Errors" : "", address);
>> > -       WARN_ON(1);
>> > +       WARN_ON_ONCE(1);
>> >
>> The issue needs to be fixed instead of WARN_ON_ONCE() and then
>> just moving ahead. Interconnect in bad states is really bad state and you
>> won't have reliable operations post that on SOC.
>
> How printing megabytes of identical stack traces helps anything?
>
It just says repeatedly and  loudly... Fix the issue :-)

> This has been there always (since the L3 driver was added) on every boot
> with N950/N9 (which BTW are HS devices, not sure if that has anything
> to do with it). There is no apparent effect on device functionality,
> at least nothing unusual has been observed...
>
I assumed this is secure device when I saw the SRAM memset is causing the
issue.

> Is there any documentation how to interpret and debug this error report?
>
The issue could be, there is memset tried on Secure portion of SRAM or
CPU speculatively accessed adjacent SRAM region of public SRAM which
is secure and hence the error.

If you just bypass the SRAM init [1], does the issue go away ?

Regards
Santosh

[1]
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181c..305e6de 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -384,6 +384,7 @@ static inline int am33xx_sram_init(void)

 int __init omap_sram_init(void)
 {
+#if 0
        omap_detect_sram();
        omap_map_sram();

@@ -397,6 +398,6 @@ int __init omap_sram_init(void)
                am33xx_sram_init();
        else if (cpu_is_omap34xx())
                omap34xx_sram_init();
-
+#endif
        return 0;
 }


From shawn.guo at linaro.org  Mon Aug 27 18:15:35 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 06:15:35 +0800
Subject: [PATCH v2 4/7] regulator: anatop-regulator: convert to use
 syscon to access anatop register
In-Reply-To: <1346052285-4344-5-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-5-git-send-email-b29396@freescale.com>
Message-ID: <20120827221532.GC2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 03:24:42PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Using syscon to access anatop register.
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog v1-v2:
>  * update to use generic regmap api
> ---
>  arch/arm/boot/dts/imx6q.dtsi         |    6 ++++++
>  drivers/regulator/Kconfig            |    2 +-
>  drivers/regulator/anatop-regulator.c |   25 +++++++++++++++----------
>  3 files changed, 22 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index db3fa15..da2bb71 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -395,6 +395,7 @@
>  					anatop-min-bit-val = <4>;
>  					anatop-min-voltage = <800000>;
>  					anatop-max-voltage = <1375000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  
>  				regulator-3p0 at 120 {
> @@ -409,6 +410,7 @@
>  					anatop-min-bit-val = <0>;
>  					anatop-min-voltage = <2625000>;
>  					anatop-max-voltage = <3400000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  
>  				regulator-2p5 at 130 {
> @@ -423,6 +425,7 @@
>  					anatop-min-bit-val = <0>;
>  					anatop-min-voltage = <2000000>;
>  					anatop-max-voltage = <2750000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  
>  				regulator-vddcore at 140 {
> @@ -437,6 +440,7 @@
>  					anatop-min-bit-val = <1>;
>  					anatop-min-voltage = <725000>;
>  					anatop-max-voltage = <1450000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  
>  				regulator-vddpu at 140 {
> @@ -451,6 +455,7 @@
>  					anatop-min-bit-val = <1>;
>  					anatop-min-voltage = <725000>;
>  					anatop-max-voltage = <1450000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  
>  				regulator-vddsoc at 140 {
> @@ -465,6 +470,7 @@
>  					anatop-min-bit-val = <1>;
>  					anatop-min-voltage = <725000>;
>  					anatop-max-voltage = <1450000>;
> +					fsl,anatop = <&anatop>;
>  				};
>  			};
>  
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 4e932cc..2ae1d97 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -112,7 +112,7 @@ config REGULATOR_DA9052
>  
>  config REGULATOR_ANATOP
>  	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
> -	depends on MFD_ANATOP
> +	depends on MFD_SYSCON
>  	help
>  	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
>  	  regulators. It is recommended that this option be
> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> index ce0fe72..71586a7 100644
> --- a/drivers/regulator/anatop-regulator.c
> +++ b/drivers/regulator/anatop-regulator.c
> @@ -21,19 +21,20 @@
>  #include <linux/slab.h>
>  #include <linux/device.h>
>  #include <linux/module.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
> -#include <linux/mfd/anatop.h>
> +#include <linux/regmap.h>
>  #include <linux/regulator/driver.h>
>  #include <linux/regulator/of_regulator.h>
>  
>  struct anatop_regulator {
>  	const char *name;
>  	u32 control_reg;
> -	struct anatop *mfd;
> +	struct regmap *anatop;
>  	int vol_bit_shift;
>  	int vol_bit_width;
>  	int min_bit_val;
> @@ -43,7 +44,7 @@ struct anatop_regulator {
>  	struct regulator_init_data *initdata;
>  };
>  
> -static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
> +static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
>  {
>  	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
>  	u32 val, mask;
> @@ -56,12 +57,13 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
>  	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
>  		anatop_reg->vol_bit_shift;
>  	val <<= anatop_reg->vol_bit_shift;
> -	anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
> +	regmap_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
> +				mask, val);
>  
>  	return 0;
>  }
>  
> -static int anatop_get_voltage_sel(struct regulator_dev *reg)
> +static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
>  {
>  	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
>  	u32 val, mask;
> @@ -69,7 +71,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
>  	if (!anatop_reg->control_reg)
>  		return -ENOTSUPP;
>  
> -	val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
> +	regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
>  	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
>  		anatop_reg->vol_bit_shift;
>  	val = (val & mask) >> anatop_reg->vol_bit_shift;
> @@ -78,8 +80,8 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
>  }
>  
>  static struct regulator_ops anatop_rops = {
> -	.set_voltage_sel = anatop_set_voltage_sel,
> -	.get_voltage_sel = anatop_get_voltage_sel,
> +	.set_voltage_sel = anatop_regmap_set_voltage_sel,
> +	.get_voltage_sel = anatop_regmap_get_voltage_sel,
>  	.list_voltage = regulator_list_voltage_linear,
>  	.map_voltage = regulator_map_voltage_linear,
>  };
> @@ -92,7 +94,6 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
>  	struct regulator_dev *rdev;
>  	struct anatop_regulator *sreg;
>  	struct regulator_init_data *initdata;
> -	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
>  	struct regulator_config config = { };
>  	int ret = 0;
>  
> @@ -109,7 +110,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
>  	rdesc->ops = &anatop_rops;
>  	rdesc->type = REGULATOR_VOLTAGE;
>  	rdesc->owner = THIS_MODULE;
> -	sreg->mfd = anatopmfd;
> +
> +	sreg->anatop = syscon_regmap_lookup_by_phandle(np, "fsl,anatop");
> +	if (IS_ERR(sreg->anatop))
> +		return PTR_ERR(sreg->anatop);
> +

All the anatop regulators are child nodes of anatop.  It looks a little
odd to use phandle there.  of_get_parent should just works.

>  	ret = of_property_read_u32(np, "anatop-reg-offset",
>  				   &sreg->control_reg);
>  	if (ret) {
> -- 
> 1.7.0.4
> 
> 

-- 
Regards,
Shawn


From haojian.zhuang at gmail.com  Mon Aug 27 18:16:35 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 Aug 2012 06:16:35 +0800
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more mach-*/*.h
 includes
In-Reply-To: <201208221301.19439.arnd@arndb.de>
References: <201208221253.07278.arnd@arndb.de>
 <201208221301.19439.arnd@arndb.de>
Message-ID: <CAN1soZw4scDo7mgcBKrk_kdMt7aP_ty+hRGX=iMDjkfSbO6k8A@mail.gmail.com>

On Wed, Aug 22, 2012 at 9:01 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> These are lots of device drivers that include machine
> specific header files from ARM platforms and that are
> not easily scriptable. The changes have been found through
> manual inspection and should cause no visible changes
> because of the build script that maps the old names to the
> new ones.
>
Here's the potential issues.

arch/arm/include/asm/irq.h:
#ifndef CONFIG_SPARSE_IRQ
#include <mach/irqs.h>
#else
#define NR_IRQS NR_IRQS_LEGACY
#endif

arch/arm/include/asm/io.h:
#ifdef CONFIG_NEED_MACH_IO_H
#include <mach/io.h>
#else
#define __io(a)         __typesafe_io((a) & IO_SPACE_LIMIT)
#endif


And you also need the code in below.

diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c
index 8ea3b33..0258c06 100644
--- a/drivers/gpio/gpio-sa1100.c
+++ b/drivers/gpio/gpio-sa1100.c
@@ -11,8 +11,8 @@
 #include <linux/init.h>
 #include <linux/module.h>

-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>

 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
diff --git a/drivers/input/keyboard/pxa27x_keypad.c
b/drivers/input/keyboard/pxa27x_keypad.c
index b2e642a..d4b1e80 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -31,7 +31,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

-#include <mach/hardware.h>
+#ifdef CONFIG_ARCH_PXA
+#include <mach-pxa/hardware.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+#include <mach-mmp/hardware.h>
+#endif
+
 #include <plat-pxa/pxa27x_keypad.h>
 /*
  * Keypad Controller registers
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d6683b7..f83d5ce 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -23,7 +23,7 @@
 #include <linux/irq.h>
 #include <linux/slab.h>

-#include <mach/dma.h>
+#include <mach-pxa/dma.h>
 #include <plat-pxa/pxa3xx_nand.h>

 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c
index b066273..77264ba 100644
--- a/drivers/pcmcia/pxa2xx_sharpsl.c
+++ b/drivers/pcmcia/pxa2xx_sharpsl.c
@@ -19,9 +19,9 @@
 #include <linux/platform_device.h>

 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/scoop.h>
+#include <mach-pxa/hardware.h>

 #include "soc_common.h"

diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c
index 70f728c..ebfd5eb 100644
--- a/drivers/pcmcia/sa1111_generic.c
+++ b/drivers/pcmcia/sa1111_generic.c
@@ -16,7 +16,7 @@

 #include <pcmcia/ss.h>

-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/irq.h>

diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 50a5c4a..812f39c 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -35,11 +35,21 @@
 #include <linux/bitops.h>
 #include <linux/io.h>

-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#ifdef CONFIG_ARCH_MMP
+#include <mach-mmp/hardware.h>
+#include <mach-mmp/irqs.h>
+#include <mach-mmp/regs-rtc.h>
+#endif
+
+#ifdef CONFIG_ARCH_PXA
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/irqs.h>
+#include <mach-pxa/regs-rtc.h>
+#endif

-#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
-#include <mach/regs-rtc.h>
+#ifdef CONFIG_ARCH_SA1100
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 #endif

 #define RTC_DEF_DIVIDER		(32768 - 1)
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index ccd6b29..3579d90 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -34,11 +34,15 @@
 #include <linux/timex.h>

 #ifdef CONFIG_ARCH_PXA
-#include <mach/regs-ost.h>
+#include <mach-pxa/regs-ost.h>
+#include <mach-pxa/reset.h>
+#include <mach-pxa/hardware.h>
 #endif

-#include <mach/reset.h>
-#include <mach/hardware.h>
+#ifdef CONFIG_ARCH_SA1100
+#include <mach-sa1100/reset.h>
+#include <mach-sa1100/hardware.h>
+#endif

 static unsigned long oscr_freq;
 static unsigned long sa1100wdt_users;


From grinberg at compulab.co.il  Mon Aug 27 18:26:14 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 28 Aug 2012 01:26:14 +0300
Subject: [PATCH] ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
Message-ID: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>

Currently, omap2_sync32k_clocksource_init() function initializes the 32K
timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
setting.
Fix this by providing a default implementation for
!CONFIG_OMAP_32K_TIMER case.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Reviewed-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/timer.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 840929b..2cdbcc7 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -263,6 +263,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
 	return 0;
 }
 
+#ifdef CONFIG_OMAP_32K_TIMER
 /* Setup free-running counter for clocksource */
 static int __init omap2_sync32k_clocksource_init(void)
 {
@@ -302,6 +303,12 @@ static int __init omap2_sync32k_clocksource_init(void)
 
 	return ret;
 }
+#else
+static inline int omap2_sync32k_clocksource_init(void)
+{
+	return -ENODEV;
+}
+#endif
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 						const char *fck_source)
-- 
1.7.3.4



From cjb at laptop.org  Mon Aug 27 18:28:35 2012
From: cjb at laptop.org (Chris Ball)
Date: Mon, 27 Aug 2012 18:28:35 -0400
Subject: [PATCH] mmc: tegra: convert to device tree support only
In-Reply-To: <1345772433.5081.1.camel@jlo-ubuntu-64.nvidia.com> (Joseph Lo's
 message of "Fri, 24 Aug 2012 09:40:33 +0800")
References: <1345187071-6619-1-git-send-email-josephl@nvidia.com>
 <502E950B.2010205@wwwdotorg.org>
 <1345772433.5081.1.camel@jlo-ubuntu-64.nvidia.com>
Message-ID: <87a9xgynos.fsf@octavius.laptop.org>

Hi,

On Thu, Aug 23 2012, Joseph Lo wrote:
> On Sat, 2012-08-18 at 03:01 +0800, Stephen Warren wrote:
>> On 08/17/2012 01:04 AM, Joseph Lo wrote:
>> > When compiling a kernel that supports only Tegra30 and not Tegra20,
>> > the SDHCI driver will fail to compile since the of_match_device() failure
>> > fallback code unconditinally references soc_data_tegra20, which is only
>> > compiled in when Tegra20 support is enabled.
>> > 
>> > In Kernel 3.7, both Tegra20 and Tegra30 will only support booting using
>> > device tree, Hence, there is never a need to fall back to using
>> > soc_data_tegra20 if of_mach_device() fails. Instead, make this case an
>> > error. This removes the reference to soc_data_tegra20, and hence solves
>> > the compile failure.
>> 
>> Tested-by: Stephen Warren <swarren at wwwdotorg.org>
>> 
>> (built and tested both Tegra20-only and Tegr30-only kernels with this
>> applied on top of next-20120816).
>
> Ping.

Thanks, pushed to mmc-next for 3.7.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From shawn.guo at linaro.org  Mon Aug 27 18:31:35 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 06:31:35 +0800
Subject: [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP
In-Reply-To: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20120827223134.GD2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 09:36:50AM +0200, Dirk Behme wrote:
> Both issues are gone applying these two patches.
> 
> Note: If these patches are fine, they should go to stable, too.
> 
Then you should have Cc: <stable at vger.kernel.org> tag on these patches.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Mon Aug 27 18:33:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 06:33:05 +0800
Subject: [PATCH 1/2] tty: serial: imx: console write routing is unsafe on
 SMP
In-Reply-To: <1346053012-25686-2-git-send-email-dirk.behme@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <1346053012-25686-2-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20120827223304.GE2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 09:36:51AM +0200, Dirk Behme wrote:
> From: Xinyu Chen <xinyu.chen at freescale.com>
> 
> The console feature's write routing is unsafe on SMP with
> the startup/shutdown call.
> 
> There could be several consumers of the console
> * the kernel printk
> * the init process using /dev/kmsg to call printk to show log
> * shell, which open /dev/console and write with sys_write()
> 
> The shell goes into the normal uart open/write routing,
> but the other two go into the console operations.
> The open routing calls imx serial startup, which will write USR1/2
> register without any lock and critical with imx_console_write call.
> 
> Add a spin_lock for startup/shutdown/console_write routing.
> 
> This patch is a port from Freescale's Android kernel.
> 
> Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
> Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
> CC: Shawn Guo <shawn.guo at linaro.org>
> CC: Sascha Hauer <s.hauer at pengutronix.de>

Acked-by: Shawn Guo <shawn.guo at linaro.org>


From haojian.zhuang at gmail.com  Mon Aug 27 18:42:33 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 28 Aug 2012 06:42:33 +0800
Subject: [PATCH 1/5] arm: mmp: make private clock definition exclude from
 common clock
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <CAN1soZy54UcoQ_qrN2Wh4ZWVMCXj3gpHZas57GqQeT988dnkQQ@mail.gmail.com>

On Mon, Aug 27, 2012 at 10:53 AM, Chao Xie <xiechao.mail at gmail.com> wrote:
> From: Chao Xie <chao.xie at marvell.com>
>
> the clock.c is mmp private implementation, make it excluded
> from common clock framework
>
> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
> ---
>  arch/arm/mach-mmp/Makefile |    5 ++++-
>  1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
> index b786f7e..815c3e7 100644
> --- a/arch/arm/mach-mmp/Makefile
> +++ b/arch/arm/mach-mmp/Makefile
> @@ -2,13 +2,16 @@
>  # Makefile for Marvell's PXA168 processors line
>  #
>
> -obj-y                          += common.o clock.o devices.o time.o irq.o
> +obj-y                          += common.o devices.o time.o irq.o
>
>  # SoC support
>  obj-$(CONFIG_CPU_PXA168)       += pxa168.o
>  obj-$(CONFIG_CPU_PXA910)       += pxa910.o
>  obj-$(CONFIG_CPU_MMP2)         += mmp2.o sram.o
>
> +ifeq ($(CONFIG_COMMON_CLK), )
> +obj-y                          += clock.o
> +endif

Why not to discard all private clock code? Maybe you can use common
clk in arch-mmp directly.


From cjb at laptop.org  Mon Aug 27 18:42:42 2012
From: cjb at laptop.org (Chris Ball)
Date: Mon, 27 Aug 2012 18:42:42 -0400
Subject: [PATCH] MMC: OMAP MSDI: fix broken PIO mode
In-Reply-To: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com> (Paul
 Walmsley's message of "Fri, 24 Aug 2012 06:00:18 +0000 (UTC)")
References: <alpine.DEB.2.00.1208240555210.25436@utopia.booyaka.com>
Message-ID: <873938yn19.fsf@octavius.laptop.org>

Hi,

On Fri, Aug 24 2012, Paul Walmsley wrote:
> After commit 26b88520b80695a6fa5fd95b5d97c03f4daf87e0 ("mmc:
> omap_hsmmc: remove private DMA API implementation"), the Nokia N800
> here stopped booting:
>
> [    2.086181] Waiting for root device /dev/mmcblk0p1...
> [    2.324066] Unhandled fault: imprecise external abort (0x406) at 0x00000000
> [    2.331451] Internal error: : 406 [#1] ARM
> [    2.335784] Modules linked in:
> [    2.339050] CPU: 0    Not tainted  (3.6.0-rc3 #60)
> [    2.344146] PC is at default_idle+0x28/0x30
> [    2.348602] LR is at trace_hardirqs_on_caller+0x15c/0x1b0
>
> ...
>
> This turned out to be due to memory corruption caused by long-broken
> PIO code in drivers/mmc/host/omap.c.  (Previously, this driver had
> been using DMA; but the above commit caused the MMC driver to fall
> back to PIO mode with an unmodified Kconfig.)
>
> The PIO code, added with the rest of the driver in commit
> 730c9b7e6630f786fcec026fb11d2e6f2c90fdcb ("[MMC] Add OMAP MMC host
> driver"), confused bytes with 16-bit words.  This bug caused memory
> located after the PIO transfer buffer to be corrupted with transfers
> larger than 32 bytes.  The driver also did not increment the buffer
> pointer after the transfer occurred.  This bug resulted in data
> corruption during any transfer larger than 64 bytes.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>

Yuck.  Thanks for tracking that down, Paul -- pushed to mmc-next for 3.6.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From santosh.shilimkar at ti.com  Mon Aug 27 18:43:04 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 27 Aug 2012 15:43:04 -0700
Subject: [PATCH] ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
In-Reply-To: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>
References: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <CAMQu2gxZBq0wMw4rgbFpDT2pmA83ULKAJ-Mwv+VKvQQZMRQ4Dw@mail.gmail.com>

On Mon, Aug 27, 2012 at 3:26 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> Currently, omap2_sync32k_clocksource_init() function initializes the 32K
> timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
> setting.
> Fix this by providing a default implementation for
> !CONFIG_OMAP_32K_TIMER case.
>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> Reviewed-by: Paul Walmsley <paul at pwsan.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From shawn.guo at linaro.org  Mon Aug 27 18:44:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 06:44:38 +0800
Subject: [PATCH v2 1/2] imx6q: pwm: Add device tree support
In-Reply-To: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFD@frontmail.adetel.com>
References: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
 <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFD@frontmail.adetel.com>
Message-ID: <20120827224435.GF2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 05:34:31PM +0200, HACHIMI Samir wrote:
> From: Samir Hachimi <shachimi at adeneo-embedded.com>
> 
>  Add clock look-up for pwm.
>  Add the pinmux support for pwm.
>  Several pin can be set to PwmO for the same Pwm.
> 
> Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   68 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 68 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 925da33..346ae9c 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -268,23 +268,43 @@
>  			};
>  
>  			pwm at 02080000 { /* PWM1 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				reg = <0x02080000 0x4000>;
>  				interrupts = <0 83 0x04>;
> +				clocks = <&clks 145>;
> +				clock-names = "pwm";
> +				status = "disabled";
>  			};
>  
>  			pwm at 02084000 { /* PWM2 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				reg = <0x02084000 0x4000>;
>  				interrupts = <0 84 0x04>;
> +				clocks = <&clks 146>;
> +				clock-names = "pwm";
> +				status = "disabled";
>  			};
>  
>  			pwm at 02088000 { /* PWM3 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				reg = <0x02088000 0x4000>;
>  				interrupts = <0 85 0x04>;
> +				clocks = <&clks 147>;
> +				clock-names = "pwm";
> +				status = "disabled";
>  			};
>  
>  			pwm at 0208c000 { /* PWM4 */
> +				compatible = "fsl,imx6q-pwm";
> +				#pwm-cells = <2>;
>  				reg = <0x0208c000 0x4000>;
>  				interrupts = <0 86 0x04>;
> +				clocks = <&clks 148>;
> +				clock-names = "pwm";
> +				status = "disabled";
>  			};
>  
>  			flexcan at 02090000 { /* CAN1 */
> @@ -584,6 +604,54 @@
>  					};
>  				};
>  
> +				pwm1 {
> +				     	pinctrl_pwm1_1: pwm1grp-1 {
> +						fsl,pins = <1543 0x80000000>;	/* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
> +					};
> +
> +				     	pinctrl_pwm1_2: pwm1grp-2 {
> +						fsl,pins = <971 0x80000000>;	/* MX6Q_PAD_GPIO_9__PWM1_PWMO */
> +					};
> +
> +				     	pinctrl_pwm1_3: pwm1grp-3 {
> +						fsl,pins = <574 0x80000000>;	/* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
> +					};

Please do not enumerate all the possible options from the beginning.
Instead, you should only add the one your board uses.  Then we can
know the added configuration is actually used and tested.

Regards,
Shawn

> +				};
> +
> +				pwm2 {
> +				     	pinctrl_pwm2_1: pwm2grp-1 {
> +						fsl,pins = <1557 0x80000000>;	/* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
> +					};
> +
> +				     	pinctrl_pwm2_2: pwm2grp-2 {
> +						fsl,pins = <963 0x80000000>;	/* MX6Q_PAD_GPIO_1__PWM2_PWMO */
> +					};
> +
> +				     	pinctrl_pwm2_3: pwm2grp-3 {
> +						fsl,pins = <582 0x80000000>;	/* MX6Q_PAD_DISP0_DAT8__PWM2_PWMO */
> +					};
> +				};
> +
> +				pwm3 {
> +				     	pinctrl_pwm3_1: pwm3grp-1 {
> +						fsl,pins = <1471 0x80000000>;	/* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
> +					};
> +
> +				     	pinctrl_pwm3_2: pwm3grp-2 {
> +						fsl,pins = <1526 0x80000000>;	/* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
> +					};
> +				};
> +
> +				pwm4 {
> +				     	pinctrl_pwm4_1: pwm4grp-1 {
> +						fsl,pins = <1479 0x80000000>;	/* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
> +					};
> +
> +				     	pinctrl_pwm4_2: pwm4grp-2 {
> +						fsl,pins = <1550 0x80000000>;	/* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
> +					};
> +				};
> +
>  				usdhc3 {
>  					pinctrl_usdhc3_1: usdhc3grp-1 {
>  						fsl,pins = <1273 0x17059	/* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
> -- 
> 1.7.1


From kgene.kim at samsung.com  Mon Aug 27 18:46:43 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 15:46:43 -0700
Subject: [PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for
 Samsung Exynos5250 platforms
In-Reply-To: <1345982371-26483-4-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <503BF8D3.9060507@samsung.com>

On 08/26/12 04:59, Thomas Abraham wrote:
> Add device nodes for the four instances of dw_mmc controllers in Exynos5250
> and enable instance 0 and 2 for the smdk5250 board.
>
> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> ---
>   arch/arm/boot/dts/exynos5250-smdk5250.dts |   57 ++++++++++++++++++++++++++++-
>   arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
>   2 files changed, 88 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index 8a5e348..6dc9faf 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -16,12 +16,19 @@
>   	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
>   	compatible = "samsung,smdk5250", "samsung,exynos5250";
>
> +	aliases {
> +		mshc0 =&mshc_0;
> +		mshc1 =&mshc_1;
> +		mshc2 =&mshc_2;
> +		mshc3 =&mshc_3;
> +	};
> +
>   	memory {
>   		reg =<0x40000000 0x80000000>;
>   	};
>
>   	chosen {
> -		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
> +		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";

Yes, we need to sort out the 'bootargs' for using uart2 as a console, 
but you know, this should be separated :-)

>   	};
>
>   	i2c at 12C60000 {
> @@ -72,6 +79,54 @@
>   		status = "disabled";
>   	};
>
> +	mshc_0: dwmmc0 at 12200000 {

How about to keep the consistent naming? dwmmc or dw_mmc? I think, 
'dw_mmc' makes more sense?

> +		num-slots =<1>;
> +		supports-highspeed;
> +		broken-cd;
> +		fifo-depth =<0x80>;
> +		card-detect-delay =<200>;
> +		samsung,dw-mshc-sdr-timing =<2 3 3>;
> +		samsung,dw-mshc-ddr-timing =<1 2 3>;

We need to think again the name of dw-mshc-sdr-timing, dw-mshc-ddr-timing?

[...]

> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 004aaa8..f69e389 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -182,6 +182,38 @@
>   		#size-cells =<0>;
>   	};
>
> +	dwmmc0 at 12200000 {
> +		compatible = "samsung,exynos5250-dw-mshc";

I'm not sure, 'exynos5250-dw-mshc' is right here. Because it is just 
dw_mmc controller on exynos5250. So...hmm...

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From gregkh at linuxfoundation.org  Mon Aug 27 18:51:42 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Mon, 27 Aug 2012 15:51:42 -0700
Subject: [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP
In-Reply-To: <20120827223134.GD2281@r65073-Latitude-D630>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <20120827223134.GD2281@r65073-Latitude-D630>
Message-ID: <20120827225142.GA11302@kroah.com>

On Tue, Aug 28, 2012 at 06:31:35AM +0800, Shawn Guo wrote:
> On Mon, Aug 27, 2012 at 09:36:50AM +0200, Dirk Behme wrote:
> > Both issues are gone applying these two patches.
> > 
> > Note: If these patches are fine, they should go to stable, too.
> > 
> Then you should have Cc: <stable at vger.kernel.org> tag on these patches.

On both of them?  I can do that if needed.  How far back should they go?

greg k-h


From kgene.kim at samsung.com  Mon Aug 27 18:58:14 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 15:58:14 -0700
Subject: [PATCH] ARM: S3C24XX: Add .get_rate callback for "camif-upll"
 clock
In-Reply-To: <1346098329-32059-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1346098329-32059-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <503BFB86.20607@samsung.com>

On 08/27/12 13:12, Sylwester Nawrocki wrote:
> Add missing get_rate callback for the "camif-upll" clock, so frequency
> of this clock is properly reported with clk_get_rate().
>
> Signed-off-by: Sylwester Nawrocki<sylvester.nawrocki at gmail.com>
> ---
>   arch/arm/mach-s3c24xx/clock-s3c2440.c |   14 ++++++++++++++
>   1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
> index cb2883d..749220f 100644
> --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
> +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
> @@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
>   	return 0;
>   }
>
> +static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
> +{
> +	unsigned long parent_rate = clk_get_rate(clk->parent);
> +	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
> +
> +	if (!(camdivn&  S3C2440_CAMDIVN_CAMCLK_SEL))
> +		return parent_rate;
> +
> +	camdivn&= S3C2440_CAMDIVN_CAMCLK_MASK;
> +
> +	return parent_rate / (camdivn + 1) / 2;

Well, why do we need '/ 2' here?

> +}
> +
>   /* Extra S3C2440 clocks */
>
>   static struct clk s3c2440_clk_cam = {
> @@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = {
>   	.name		= "camif-upll",
>   	.ops		=&(struct clk_ops) {
>   		.set_rate	= s3c2440_camif_upll_setrate,
> +		.get_rate	= s3c2440_camif_upll_getrate,
>   		.round_rate	= s3c2440_camif_upll_round,
>   	},
>   };

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Mon Aug 27 18:59:58 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 15:59:58 -0700
Subject: ASoC: SAMSUNG: Change Kconfig to support all EXYNOSs
In-Reply-To: <20120827180851.GS4339@opensource.wolfsonmicro.com>
References: <003001cd8361$7016a110$5043e330$@samsung.com>
 <503BB737.7090004@samsung.com>
 <20120827180851.GS4339@opensource.wolfsonmicro.com>
Message-ID: <503BFBEE.9050401@samsung.com>

On 08/27/12 11:08, Mark Brown wrote:
> On Mon, Aug 27, 2012 at 11:06:47AM -0700, Kukjin Kim wrote:
>
>> Hmm, all of Samsung stuff is available...so how about?
>>
>> +	depends on PLAT_SAMSUNG
>
> Yes, that's a very good idea!

Mark, thanks.

Sangsu, could you please re-submit as per my suggestion?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From robherring2 at gmail.com  Mon Aug 27 19:03:52 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 27 Aug 2012 18:03:52 -0500
Subject: [PATCH v3 06/25] docs: Xen ARM DT bindings
In-Reply-To: <1345131377-14713-6-git-send-email-stefano.stabellini@eu.citrix.com>
References: <alpine.DEB.2.02.1208161618550.4850@kaball.uk.xensource.com>
 <1345131377-14713-6-git-send-email-stefano.stabellini@eu.citrix.com>
Message-ID: <503BFCD8.5090804@gmail.com>

On 08/16/2012 10:35 AM, Stefano Stabellini wrote:
> Add a doc to describe the Xen ARM device tree bindings
> 
> Signed-off-by: Stefano Stabellini <stefano.stabellini at eu.citrix.com>
> CC: devicetree-discuss at lists.ozlabs.org
> CC: David Vrabel <david.vrabel at citrix.com>
> ---
>  Documentation/devicetree/bindings/arm/xen.txt |   22 ++++++++++++++++++++++
>  1 files changed, 22 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/xen.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt
> new file mode 100644
> index 0000000..ec6d884
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/xen.txt
> @@ -0,0 +1,22 @@
> +* Xen hypervisor device tree bindings
> +
> +Xen ARM virtual platforms shall have the following properties:
> +
> +- compatible:
> +	compatible = "xen,xen", "xen,xen-<version>";
> +  where <version> is the version of the Xen ABI of the platform.
> +
> +- reg: specifies the base physical address and size of a region in
> +  memory where the grant table should be mapped to, using an
> +  HYPERVISOR_memory_op hypercall. 
> +
> +- interrupts: the interrupt used by Xen to inject event notifications.

You should look at ePAPR 1.1 which defines hypervisor related bindings.
While it is a PPC doc, we should reuse or extend what makes sense.

See section 7.5:

https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf

Rob

> +
> +
> +Example:
> +
> +hypervisor {
> +	compatible = "xen,xen", "xen,xen-4.3";
> +	reg = <0xb0000000 0x20000>;
> +	interrupts = <1 15 0xf08>;
> +};
> 



From shawn.guo at linaro.org  Mon Aug 27 19:05:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 07:05:13 +0800
Subject: [PATCH v2 2/2] Enable Stop_enable mode during configuration of
 pwm.
In-Reply-To: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFE@frontmail.adetel.com>
References: <1346081672-27866-1-git-send-email-shachimi@adeneo-embedded.com>
 <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFE@frontmail.adetel.com>
Message-ID: <20120827230511.GG2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 05:34:32PM +0200, HACHIMI Samir wrote:
> From: Samir Hachimi <shachimi at adeneo-embedded.com>
> 
>  Enable Stop_enable mode during configuration of pwm.
>  Check architecture by looking in driver_data instead of cpu_is_xxx.

It does 2 things, and should be split into 2 patches.  Also you should
have a better commit log for the thing you are doing.  For example, why
you need to enable STOPEN during configuration, what problem you are
running into without doing so, etc.

> 
> Signed-off-by: Samir Hachimi <shachimi at adeneo-embedded.com>
> ---
>  drivers/pwm/pwm-imx.c |   59 +++++++++++++++++++++++++++++++++++-------------
>  1 files changed, 43 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index 0519bf2..7df919f 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -32,6 +32,7 @@
>  #define MX3_PWMSAR                0x0C    /* PWM Sample Register */
>  #define MX3_PWMPR                 0x10    /* PWM Period Register */
>  #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
> +#define MX3_PWMCR_STOPEN		(1 << 25)
>  #define MX3_PWMCR_DOZEEN                (1 << 24)
>  #define MX3_PWMCR_WAITEN                (1 << 23)
>  #define MX3_PWMCR_DBGEN			(1 << 22)
> @@ -39,6 +40,16 @@
>  #define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
>  #define MX3_PWMCR_EN              (1 << 0)
>  
> +/* Use the platform_id to distinguish different Archs. */
> +#define IS_MX1			0x0
> +#define IS_MX21			0x1
> +#define IS_MX25			0x2
> +#define IS_MX6Q			0x3

I prefer to use enum for these ...

> +#define PWM_IS_MX1(x)		((x)->id_entry->driver_data == IS_MX1)
> +#define PWM_IS_MX21(x)		((x)->id_entry->driver_data == IS_MX21)
> +#define PWM_IS_MX25(x)		((x)->id_entry->driver_data == IS_MX25)
> +#define PWM_IS_MX6Q(x)		((x)->id_entry->driver_data == IS_MX6Q)
> +

... and inline function for these.  drivers/mmc/host/sdhci-esdhc-imx.c
could be an example here.

Also, I see PWM_IS_MX6Q used nowhere, which probably means the pwm on
imx6q is compatible with imx25 one, and we should not introduce MX6Q
type at all.

>  struct imx_chip {
>  	struct clk	*clk;
>  
> @@ -46,6 +57,7 @@ struct imx_chip {
>  	void __iomem	*mmio_base;
>  
>  	struct pwm_chip	chip;
> +	struct platform_device	*pdev;
>  };
>  
>  #define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
> @@ -65,7 +77,7 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  			return rc;
>  	}
>  
> -	if (!(cpu_is_mx1() || cpu_is_mx21())) {
> +	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
>  		unsigned long long c;
>  		unsigned long period_cycles, duty_cycles, prescale;
>  		u32 cr;
> @@ -78,36 +90,33 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  		prescale = period_cycles / 0x10000 + 1;
>  
>  		period_cycles /= prescale;
> -		c = (unsigned long long)period_cycles * duty_ns;
> -		do_div(c, period_ns);
> -		duty_cycles = c;
>  
> -		/*
> -		 * according to imx pwm RM, the real period value should be
> -		 * PERIOD value in PWMPR plus 2.
> +		/* the chip documentation says the counter counts up to
> +		 * period_cycles + 1 and then is reset to 0, so the
> +		 *  actual period of the PWM wave is period_cycles + 2
>  		 */
> -		if (period_cycles > 2)
> -			period_cycles -= 2;
> -		else
> -			period_cycles = 0;
> +		c = (unsigned long long)(period_cycles + 2) * duty_ns;
> +		do_div(c, period_ns);
> +		duty_cycles = c;
>  
>  		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
>  		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
>  
>  		cr = MX3_PWMCR_PRESCALER(prescale) |
> -			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN;
> +			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
> +			MX3_PWMCR_DBGEN | MX3_PWMCR_STOPEN;
>  
>  		/* If the PWM is enabled, keep it so. */
>  		if (imx->clk_enabled)
>  			cr |= MX3_PWMCR_EN;
>  
> -		if (cpu_is_mx25())
> +		if (PWM_IS_MX25(imx->pdev))
>  			cr |= MX3_PWMCR_CLKSRC_IPG;
>  		else
>  			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
>  
>  		writel(cr, imx->mmio_base + MX3_PWMCR);
> -	} else if (cpu_is_mx1() || cpu_is_mx21()) {
> +	} else if (PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev)) {
>  		/* The PWM subsystem allows for exact frequencies. However,
>  		 * I cannot connect a scope on my device to the PWM line and
>  		 * thus cannot provide the program the PWM controller
> @@ -150,7 +159,7 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  	if (rc)
>  		return rc;
>  
> -	if (!(cpu_is_mx1() || cpu_is_mx21())) {
> +	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
>  		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
>  		cr |= MX3_PWMCR_EN;
>  		writel(cr, imx->mmio_base + MX3_PWMCR);
> @@ -167,7 +176,7 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>  	if (!imx->clk_enabled)
>  		return;
>  
> -	if (!(cpu_is_mx1() || cpu_is_mx21())) {
> +	if (!(PWM_IS_MX1(imx->pdev) || PWM_IS_MX21(imx->pdev))) {
>  		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
>  		cr &= ~MX3_PWMCR_EN;
>  		writel(cr, imx->mmio_base + MX3_PWMCR);
> @@ -207,6 +216,7 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
>  	imx->chip.npwm = 1;
>  
>  	imx->clk_enabled = 0;
> +	imx->pdev = pdev;
>  
>  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (r == NULL) {
> @@ -237,9 +247,26 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
>  	return pwmchip_remove(&imx->chip);
>  }
>  
> +static const struct platform_device_id pwm_ids[] = {
> +	{ .name = "imx1-pwm", .driver_data = IS_MX1, },
> +	{ .name = "imx21-pwm", .driver_data = IS_MX21, },
> +	{ .name = "imx25-pwm", .driver_data = IS_MX25, },
> +	{ .name = "imx6q-pwm", .driver_data = IS_MX6Q, },
> +	{},
> +};

You are not using the table as .id_table of imx_pwm_driver, so these
PWM_IS_xxx stuff does not work at all.  Also, changing to use
platform_device_id will require updates to machine code that registers
platform_device for non-DT case.

> +
> +static const struct of_device_id mxc_pwm_dt_ids[] = {
> +	{
> +		.compatible = "fsl,imx6q-pwm",
> +		.data = (void *)&pwm_ids[IS_MX6Q]
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static struct platform_driver imx_pwm_driver = {
>  	.driver		= {
>  		.name	= "mxc_pwm",
> +		.of_match_table = of_match_ptr(mxc_pwm_dt_ids),
>  	},
>  	.probe		= imx_pwm_probe,
>  	.remove		= __devexit_p(imx_pwm_remove),
> -- 
> 1.7.1

-- 
Regards,
Shawn


From linus.walleij at linaro.org  Mon Aug 27 19:07:58 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:07:58 -0700
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <20120820080632.GD8450@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
 <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>
 <20120820080632.GD8450@gmail.com>
Message-ID: <CACRpkdZRJ1yX-o8-NUuMzXMz5ebbp=H21Xa6JMy1y56Chq-T9g@mail.gmail.com>

On Mon, Aug 20, 2012 at 1:06 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Tue, Aug 14, 2012 at 01:13:49PM +0200, Linus Walleij wrote:
>> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > We've done this before and it worked well last time. Here we're
>> > duplicating a complex registration function to ease the process
>> > of enabling it for Device Tree. As there are quite a few steps
>> > taken during the registration process, it makes sense to break
>> > them up into more manageable chunks. This patch will aid us.
>> >
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> I understand you have used this approach before so:
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>
> Does this comment take back your previous one:
>
> NOTE: it seems this patch set contains some churn. First you
> add in the forked device init, put in a big chunk of code and
> then in the *same* patch set delete it again. It's not like
> we're dying to see all the development history... can this
> be squashed down a bit?
>
> ... hence leave the patch-set as it is?

No. I just meant leave it like that for the devices outside of this
set.

If you're adding and then removing *all* of them in this set,
why add them in the first place?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 27 19:09:46 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:09:46 -0700
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <20120820115914.GP8450@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
 <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
 <20120820115914.GP8450@gmail.com>
Message-ID: <CACRpkdZse9Nq1acoAujV8ojhRKxykNX0ymcr51QAoanUbDW14g@mail.gmail.com>

On Mon, Aug 20, 2012 at 4:59 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Tue, Aug 14, 2012 at 10:51:02AM +0200, Linus Walleij wrote:

>> But wait. These are just local statics. Surelty you can put these into
>> struct ux500_msp instead? Here it looks like these will be used for
>> all ports, so MSP2 will enable the pins requested by MSP1 etc
>> completely broken. So put it into the struct ux500_msp state
>> container from ux500_msp_i2s.h where it belongs.
>>
>> Refer to drivers/tty/serial/amba-pl011.c when in trouble. This
>> one is a good pinctrl example.
>
> How do you see the MSP1 and MSP3 usage protection working if I hide it
> all away in MSP specific structs?

Usage protection? Sorry not following. Please elaborate...

Yours,
Linus Walleij


From kgene.kim at samsung.com  Mon Aug 27 19:11:32 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 16:11:32 -0700
Subject: [PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC
 controllers
In-Reply-To: <1345982371-26483-3-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <503BFEA4.1070601@samsung.com>

On 08/26/12 04:59, Thomas Abraham wrote:
> Add entries if MSHC controllers in AUXDATA table for correct device name
> initialization.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> ---
>   arch/arm/mach-exynos/include/mach/map.h |    1 +
>   arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
>   2 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 9d1f3ac..5b0ee41 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -172,6 +172,7 @@
>
>   #define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
>   #define EXYNOS4_PA_DWMCI		0x12550000
> +#define EXYNOS5_PA_DWMCI(x)		(0x12200000 + ((x) * 0x10000))

Just, how about EXYNOS5_PA_DWMMC0, EXYNOS5_PA_DWMMC1, ... EXYNOS_PA_DWMMC3?

And if the addresses are different on other EXYNOS5 SoC, how do we 
handle it for auxdata?

>
>   #define EXYNOS4_PA_HSOTG		0x12480000
>   #define EXYNOS4_PA_USB_HSPHY		0x125B0000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index ef770bc..4257cc1 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>   				"s3c2440-i2c.0", NULL),
>   	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
>   				"s3c2440-i2c.1", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),

As I commented, how about just 'samsung,dw-mmc'? but I'm not sure.

> +				"dw_mmc.0", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(1),
> +				"dw_mmc.1", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(2),
> +				"dw_mmc.2", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(3),
> +				"dw_mmc.3", NULL),
>   	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
>   				"exynos4210-spi.0", NULL),
>   	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Mon Aug 27 19:15:26 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 16:15:26 -0700
Subject: [PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller
 clocks
In-Reply-To: <1345982371-26483-2-git-send-email-thomas.abraham@linaro.org>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <503BFF8E.80503@samsung.com>

On 08/26/12 04:59, Thomas Abraham wrote:
> Add clock instances for bus interface unit clock and card interface unit
> clock of the all four MSHC controller instances.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> ---
>   arch/arm/mach-exynos/clock-exynos5.c |   45 ++++++++++++----------------------
>   1 files changed, 16 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
> index 3b00e29..16d8bef 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
>   		.enable		= exynos5_clk_ip_peris_ctrl,
>   		.ctrlbit	= (1<<  19),
>   	}, {
> -		.name		= "hsmmc",
> -		.devname	= "exynos4-sdhci.0",
> +		.name		= "biu",

I have no idea why we change the clock name to 'biu' (bus interface 
unit). Just let me know.

[...]

>   static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
>   	.clk	= {
> -		.name		= "sclk_mmc",
> -		.devname	= "exynos4-sdhci.0",
> +		.name		= "ciu",

Same as above.

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From linus.walleij at linaro.org  Mon Aug 27 19:22:57 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:22:57 -0700
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <CAJuYYwQu7OXQEWCumuMeSKJ2RZD7e==pLKDE1=bvPgfXtO=AUw@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
 <CAJuYYwQu7OXQEWCumuMeSKJ2RZD7e==pLKDE1=bvPgfXtO=AUw@mail.gmail.com>
Message-ID: <CACRpkdbVY1mmzb9H4ZfmVScW1ZNf1FTMLdgo5UFgqTftycMyrQ@mail.gmail.com>

On Tue, Aug 21, 2012 at 9:22 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

>>> +  - samsung,pin-pud: Pull up/down configuration.
>>> +  - samsung,pin-drv: Drive strength configuration.
>>> +  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
>>> +  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.
>>
>> This looks a bit scary, as it seems to be orthogonal to the pin config
>> interface. I.e. this will be programmed "behind the back" of the
>> pin config system. However as long as the pin config implementation
>> reads back these things from the registers it will work, too.
>
> These properties are converted to a PIN_MAP_TYPE_CONFIGS_GROUP map
> type and stored in a instance of 'struct pinctrl_map'. These can be
> read back from the registers and reverse-mapped as well.

OK

> All the dt bindings defined and used in the Samsung pinctrl driver are
> first translated into pinctrl subystem defined data structures and
> then used. Hence, there are no register configurations done that skip
> over the pinctrl subsystem (except for the gpio/wakeup interrupts).

OK fine.

>> In the U300 and Ux500 I explicitly use pin config hogs to set up
>> the pin configuration, and when we enter a state such as
>> "default" the mux setting and config settings are set from the
>> framework separately.
>>
>> See for example:
>> arch/arm/mach-ux500/board-mop500-pins.c
>>
>> This example is using platform data but it should be trivial to do with
>> device tree.
>>
>> I think the Tegra also works this way. Can you elaborate on
>> why you need this static setup from the device tree instead
>> of using default states?
>
> Sorry, I did not understand this question.

You answered above, no problem.

>>> +       pinctrl_0: pinctrl at 11400000 {
>>> +               compatible = "samsung,pinctrl-exynos4210";
>>> +               reg = <0x11400000 0x1000>;
>>> +               interrupts = <0 47 0>;
>>> +
>>> +               uart0_data: uart0-data {
>>> +                       samsung,pins = "gpa0-0", "gpa0-1";
>>> +                       samsung,pin-function = <2>;
>>> +                       samsung,pin-pud = <0>;
>>> +                       samsung,pin-drv = <0>;
>>> +               };
>>
>> This setup needs to be associated with a certain state, it's possible to
>> do in the code or directly in the device tree.
>>
>> I.e. these settings for pin-pud and pin-drv needs to belong to a
>> certain pin config state, typically the state named "default"
>
> Yes, I agree. So, for example, the uart device node would have
>
>                     uart at 13800000 {
>                                compatilble = " .... ";
>                                <rest of the properties here>
>
>                                pinctrl-names = "default";
>                                pinctrl-0 - <&uart0_data>;
>                     };
>
> The uart driver during probe can then call
>
>                    devm_pinctrl_get_select_default(&pdev->dev);
>
> For the example above, this call will set the 'mux', 'pud' and 'drv'
> values to gpa-0 and gpa-1 pins.

OK perfect, that's how it should work.

>>> +/* list of all possible config options supported */
>>> +struct pin_config {
>>> +       char            *prop_cfg;
>>> +       unsigned int    cfg_type;
>>> +} pcfgs[] = {
>>> +       { "samsung,pin-pud", PINCFG_TYPE_PUD },
>>> +       { "samsung,pin-drv", PINCFG_TYPE_DRV },
>>> +       { "samsung,pin-pud-pdn", PINCFG_TYPE_CON_PND },
>>> +       { "samsung,pin-drv-pdn", PINCFG_TYPE_PUD_PND },
>>> +};
>>
>> Hmmmmm it looks very much like this controller could make use of
>> the generic pinconf library, but it's not mandatory so just a suggestion.
>
> Ok. The last two entries in the above table are Samsung specific and
> not covered by generic-pinconf. So, I am not sure if it can be added
> to generic-pinconf.

What is so Samsung-specific about them?

If you tell us the electrical property of setting them we can figure out
if they should be generic or not...

> For now, since you are not enforcing the use of
> generic-pinconf, I will keep it the way it is now.

Sure that's OK.

>>> +       /* Allocate memory for pin group name. The pin group name is derived
>>> +        * from the node name from which these map entries are be created.
>>> +        */
>>> +       gname = kzalloc(strlen(np->name) + 4, GFP_KERNEL);
>>
>> Why +4? I would have suspected +1 for the null terminator...
>
> The name of the pin group is derived from the node name and hence
> strlen(np->name). To this name, "-grp" is appended to imply that this
> is a group. Hence +4 is used. I will replace +4 with probably
> strlen(PINGRP_SUFFIX) where PINGRP_SUFFIX is defined as "-grp".

Aha OK I get it.

>>> +/* reading pin pull up/down and driver strength settings not implemented */
>>
>> OK why not? It seems very simple and straight-forward.
>> Just read the same registers and switch() then return...
>
> Ok, I will do that. I did not see how those would be used and hence skipped it.

One good usecase is to look at the state of pins in debugfs.

>>> +static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
>> (...)
>>> +       if (ctrl->eint_gpio_init)
>>> +               ctrl->eint_gpio_init(drvdata);
>>> +       if (ctrl->eint_wkup_init)
>>> +               ctrl->eint_wkup_init(drvdata);
>>
>> So this stuff I'm doing in the default states instead.
>
> These callbacks setup the irq domain and irq_chip for gpio and wakeup
> interrupts. These are Samsung specific and are dealt with outside of
> the pinctrl subsystem framework.

Aha I get it, OK.

>>> +       unsigned int            eint_type;
>>
>> Shouldn't this be some kund of enum if it denotes a type?
>
> It was done to reduce adding new data types.

Oh I like new data types if they make the code easier to read
and reduce the risk for errors so just go ahead :-)

>>> +/**
>>> + * struct samsung_pin_ctrl: represent a pin controller.
>>> + * @pin_banks: list of pin banks included in this controller.
>>> + * @nr_banks: number of pin banks.
>>> + * @base: starting system wide pin number.
>>> + * @nr_pins: number of pins supported by the controller.
>>> + * @nr_gint: number of external gpio interrupts supported.
>>> + * @nr_wint: number of external wakeup interrupts supported.
>>> + * @geint_con: offset of the ext-gpio controller registers.
>>
>> If it's an offset why not name it geint_con_offset?
>
> I wanted to keep the lines within 80 columns. Splitting a line into
> two lines started making the code look unreadable.

OK no big deal.

>>> +       int                     (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
>>> +       int                     (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
>>
>> I guess you need to set up these using auxdata?
>
> No, these are populated by the platform (SoC) specific data that the
> Samsung pinctrl driver gets during probe. Due to the differences in
> the gpio and wakeup interrupt controllers on Samsung SoC's, the setup
> and implementations of these  interrupts have been made SoC specific.
> The pinctrl driver is responsible only for initiating the setup of the
> gpio/wakeup interrupts.

I see, OK.

>>> +/**
>>> + * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
>>> + * @virt_base: register base address of the controller.
>>> + * @dev: device instance representing the controller.
>>> + * @irq: interrpt number used by the controller to notify gpio interrupts.
>>> + * @ctrl: pin controller instance managed by the driver.
>>> + * @pctl: pin controller descriptor registered with the pinctrl subsystem.
>>
>> Maybe name this pctl_desc then?
>
> This name is used to in multiple places in the code and the longer the
> name, there is always the case of the line spilling over 80
> characters.

OK whatever... looking formward to next iteration!

Yours,
Linus Walleij


From aaro.koskinen at iki.fi  Mon Aug 27 19:26:13 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 28 Aug 2012 02:26:13 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
Message-ID: <20120827232613.GB783@harshnoise.musicnaut.iki.fi>

On Mon, Aug 27, 2012 at 03:12:07PM -0700, Shilimkar, Santosh wrote:
> On Mon, Aug 27, 2012 at 3:02 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> > Hi,
> >
> > On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote:
> >> > -       pr_err("%s seen by %s %s at address %x\n",
> >> > +       pr_err_ratelimited("%s seen by %s %s at address %x\n",
> >> >                         omap3_l3_code_string(code),
> >> >                         omap3_l3_initiator_string(initid),
> >> >                         multi ? "Multiple Errors" : "", address);
> >> > -       WARN_ON(1);
> >> > +       WARN_ON_ONCE(1);
> >> >
> >> The issue needs to be fixed instead of WARN_ON_ONCE() and then
> >> just moving ahead. Interconnect in bad states is really bad state and you
> >> won't have reliable operations post that on SOC.
> >
> > How printing megabytes of identical stack traces helps anything?
> >
> It just says repeatedly and  loudly... Fix the issue :-)
> 
> > This has been there always (since the L3 driver was added) on every boot
> > with N950/N9 (which BTW are HS devices, not sure if that has anything
> > to do with it). There is no apparent effect on device functionality,
> > at least nothing unusual has been observed...
> >
> I assumed this is secure device when I saw the SRAM memset is causing the
> issue.
> 
> > Is there any documentation how to interpret and debug this error report?
> >
> The issue could be, there is memset tried on Secure portion of SRAM or
> CPU speculatively accessed adjacent SRAM region of public SRAM which
> is secure and hence the error.

Thanks, that makes sense.

> If you just bypass the SRAM init [1], does the issue go away ?

I tried bypassing the whole SRAM init, but the device does not seem to
boot up at all.

If I comment out the memset alone, then it boots and the issue is gone:

+#if 0
	memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
		  omap_sram_size - SRAM_BOOTLOADER_SZ);
+#endif

A.


From kgene.kim at samsung.com  Mon Aug 27 19:33:43 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 27 Aug 2012 16:33:43 -0700
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
In-Reply-To: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <503C03D7.5050801@samsung.com>

On 08/25/12 05:20, Sylwester Nawrocki wrote:
> This short patch series converts remaining users of the s3c24xx SoC
> specific gpiolib functions to the gpiolib API and finally removes
> all s3c2410_* functions from drivers/gpio/gpio-samsung.c.
>
> Sylwester Nawrocki (3):
>    ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to gpiolib API
>    ARM: S3C24XX: Remove obsolete GPIO API declarations
>    gpio-samsung: Remove now unused s3c2410_gpio* API
>
>   arch/arm/mach-s3c24xx/mach-anubis.c           |    3 +-
>   arch/arm/mach-s3c24xx/mach-jive.c             |   12 ++--
>   arch/arm/mach-s3c24xx/mach-mini2440.c         |    4 +-
>   arch/arm/mach-s3c24xx/mach-nexcoder.c         |   22 +++---
>   arch/arm/mach-s3c24xx/mach-osiris.c           |    7 +-
>   arch/arm/plat-samsung/include/plat/gpio-fns.h |   97 -------------------------
>   drivers/gpio/gpio-samsung.c                   |   40 ----------
>   7 files changed, 25 insertions(+), 160 deletions(-)
>

Nice cleanup.

Accordingly, we need to sort out the 
'Documentation/arm/Samsung-S3C24XX/GPIO.txt' later?

Linus, this series should be sent to upstream via both trees, samsung 
and gpio to avoid useless merge conflicts. How do you think?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From olof at lixom.net  Mon Aug 27 19:33:57 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 16:33:57 -0700
Subject: [GIT PULL] Renesas ARM-based SoC fix for v3.6
In-Reply-To: <201208240118.16563.rjw@sisk.pl>
References: <201208240118.16563.rjw@sisk.pl>
Message-ID: <20120827233357.GA3571@quad.lixom.net>

On Fri, Aug 24, 2012 at 01:18:16AM +0200, Rafael J. Wysocki wrote:
> Hi,
> 
> Please pull from the git repository at
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas.git fixes
> 
> to receive one fix for the sh73a0 SoC support code as commit
> 6c0274cbe63ec265f842537825684a619e6cce93
> 
>   ARM: shmobile: sh73a0: fixup RELOC_BASE of intca_irq_pins_desc
> 
> on top of commit d9875690d9b89a866022ff49e3fcea892345ad92
> 
>   Linux 3.6-rc2

Thanks, pulled.

-Olof


From sboyd at codeaurora.org  Mon Aug 27 19:35:21 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 27 Aug 2012 16:35:21 -0700
Subject: [PATCH] ARM: MSM: Fix early debug uart mapping on some memory configs
Message-ID: <1346110521-24999-1-git-send-email-sboyd@codeaurora.org>

The uart mapping runs into the space allocated for lowmem on some
8960 boards when we have more than 512Mb of memory. We were
getting lucky before and our mapping wasn't part of DDR. Move the
mapping up into the vmalloc area which will always be outside of
the lowmem mapping regardless of how much lowmem actually exists.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h | 2 +-
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index a1752c0..facf434 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -46,7 +46,7 @@
 #define MSM8960_TMR0_SIZE	SZ_4K
 
 #ifdef CONFIG_DEBUG_MSM8960_UART
-#define MSM_DEBUG_UART_BASE	0xE1040000
+#define MSM_DEBUG_UART_BASE	0xF0040000
 #define MSM_DEBUG_UART_PHYS	0x16440000
 #endif
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 5aed57d..21a2a88 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -63,7 +63,7 @@
 #define MSM8X60_TMR0_SIZE	SZ_4K
 
 #ifdef CONFIG_DEBUG_MSM8660_UART
-#define MSM_DEBUG_UART_BASE	0xE1040000
+#define MSM_DEBUG_UART_BASE	0xF0040000
 #define MSM_DEBUG_UART_PHYS	0x19C40000
 #endif
 
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From thomas.petazzoni at free-electrons.com  Mon Aug 27 19:35:28 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 01:35:28 +0200
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>

Commit c085d965fb63ac3b4cc7379d45588c0b39e2bdb0 made the ARCH_MVEBU
platform select PLAT_ORION, which means that now all Orion drivers can
be enabled on ARCH_MVEBU. This works fine for most drivers, except for
orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
not have a mach/hardware.h header (it is considered as a deprecated
practice).

It turns out that the <mach/hardware.h> include in orion_nand is not
necessary: the driver builds perfectly fine without it, so we simply
get rid of it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <dedekind1 at gmail.com>
---
 drivers/mtd/nand/orion_nand.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index fc5a868..9ee436d 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -21,7 +21,6 @@
 #include <linux/err.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
-#include <mach/hardware.h>
 #include <plat/orion_nand.h>
 
 static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-- 
1.7.9.5



From shawn.guo at linaro.org  Mon Aug 27 19:37:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 07:37:59 +0800
Subject: [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP
In-Reply-To: <20120827225142.GA11302@kroah.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <20120827223134.GD2281@r65073-Latitude-D630>
 <20120827225142.GA11302@kroah.com>
Message-ID: <20120827233756.GH2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 03:51:42PM -0700, Greg Kroah-Hartman wrote:
> On both of them?  I can do that if needed.  How far back should they go?
> 
It should be okay to apply on 3.4 and 3.5.  But patch #2 is still in
question.  I do not like the #ifdef.

-- 
Regards,
Shawn


From paul at pwsan.com  Mon Aug 27 19:36:06 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:06 -0600
Subject: [PATCH 0/5] hwrng/ARM: OMAP: convert to use runtime PM
Message-ID: <20120827232922.15045.56522.stgit@dusk.lan>

This series converts the OMAP hardware random number generator driver
to use runtime PM.  Hardware integration data is added for OMAP2xxx
systems.  I'm pretty sure this device is available on other OMAP chips
too, but may require some experimentation with the integration details.

There are still a few rough edges with this series.  Something is
still not right with the reset behavior on OMAP2430, at least.  But it
would be good to get acks from the hwrng folks for the three patches that
touch files in that directory.  Will continue with the testing process
here.


- Paul

---

Paul Walmsley (5):
      ARM: OMAP2/3: hwmod: add RNG integration data
      hwrng: OMAP: store per-device data in per-device variables, not file statics
      hwrng: OMAP: convert to use runtime PM
      ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
      hwrng: OMAP: remove SoC restrictions from driver registration


 arch/arm/mach-omap1/devices.c                      |   28 +++++
 arch/arm/mach-omap2/devices.c                      |   18 +++
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    1 
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |   17 +++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   37 ++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    5 -
 arch/arm/plat-omap/Makefile                        |    3 
 arch/arm/plat-omap/devices.c                       |   92 ---------------
 drivers/char/hw_random/omap-rng.c                  |  121 ++++++++++++--------
 10 files changed, 176 insertions(+), 147 deletions(-)
 delete mode 100644 arch/arm/plat-omap/devices.c



From paul at pwsan.com  Mon Aug 27 19:36:10 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:10 -0600
Subject: [PATCH 2/5] hwrng: OMAP: store per-device data in per-device
 variables, not file statics
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120827233609.15045.38385.stgit@dusk.lan>

Encapsulate all of the RNG per-device state into a single per-device
structure record, as opposed to a set of per-driver file variables.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Matt Mackall <mpm at selenic.com>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
---
 drivers/char/hw_random/omap-rng.c |  115 +++++++++++++++++++++++++------------
 1 file changed, 77 insertions(+), 38 deletions(-)

diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 4fbdceb..e0f0b98 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/hw_random.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 
 #include <asm/io.h>
 
@@ -46,26 +47,38 @@
 #define RNG_SYSSTATUS		0x44		/* System status
 							[0] = RESETDONE */
 
-static void __iomem *rng_base;
-static struct clk *rng_ick;
-static struct platform_device *rng_dev;
+/**
+ * struct omap_rng_private_data - RNG IP block-specific data
+ * @base: virtual address of the beginning of the RNG IP block registers
+ * @clk: RNG clock
+ * @mem_res: struct resource * for the IP block registers physical memory
+ */
+struct omap_rng_private_data {
+	void __iomem *base;
+	struct clk *clk;
+	struct resource *mem_res;
+};
 
-static inline u32 omap_rng_read_reg(int reg)
+static inline u32 omap_rng_read_reg(struct omap_rng_private_data *priv, int reg)
 {
-	return __raw_readl(rng_base + reg);
+	return __raw_readl(priv->base + reg);
 }
 
-static inline void omap_rng_write_reg(int reg, u32 val)
+static inline void omap_rng_write_reg(struct omap_rng_private_data *priv,
+				      int reg, u32 val)
 {
-	__raw_writel(val, rng_base + reg);
+	__raw_writel(val, priv->base + reg);
 }
 
 static int omap_rng_data_present(struct hwrng *rng, int wait)
 {
+	struct omap_rng_private_data *priv;
 	int data, i;
 
+	priv = (struct omap_rng_private_data *)rng->priv;
+
 	for (i = 0; i < 20; i++) {
-		data = omap_rng_read_reg(RNG_STAT_REG) ? 0 : 1;
+		data = omap_rng_read_reg(priv, RNG_STAT_REG) ? 0 : 1;
 		if (data || !wait)
 			break;
 		/* RNG produces data fast enough (2+ MBit/sec, even
@@ -80,9 +93,13 @@ static int omap_rng_data_present(struct hwrng *rng, int wait)
 
 static int omap_rng_data_read(struct hwrng *rng, u32 *data)
 {
-	*data = omap_rng_read_reg(RNG_OUT_REG);
+	struct omap_rng_private_data *priv;
+
+	priv = (struct omap_rng_private_data *)rng->priv;
+
+	*data = omap_rng_read_reg(priv, RNG_OUT_REG);
 
-	return 4;
+	return sizeof(u32);
 }
 
 static struct hwrng omap_rng_ops = {
@@ -93,69 +110,85 @@ static struct hwrng omap_rng_ops = {
 
 static int __devinit omap_rng_probe(struct platform_device *pdev)
 {
-	struct resource *res;
+	struct omap_rng_private_data *priv;
 	int ret;
 
-	/*
-	 * A bit ugly, and it will never actually happen but there can
-	 * be only one RNG and this catches any bork
-	 */
-	if (rng_dev)
-		return -EBUSY;
+	priv = kzalloc(sizeof(struct omap_rng_private_data), GFP_KERNEL);
+	if (!priv) {
+		dev_err(&pdev->dev, "could not allocate memory\n");
+		return -ENOMEM;
+	};
+
+	omap_rng_ops.priv = (unsigned long)priv;
+	dev_set_drvdata(&pdev->dev, priv);
 
 	if (cpu_is_omap24xx()) {
-		rng_ick = clk_get(&pdev->dev, "ick");
-		if (IS_ERR(rng_ick)) {
+		priv->clk = clk_get(&pdev->dev, "ick");
+		if (IS_ERR(priv->clk)) {
 			dev_err(&pdev->dev, "Could not get rng_ick\n");
-			ret = PTR_ERR(rng_ick);
+			ret = PTR_ERR(priv->clk);
 			return ret;
-		} else
-			clk_enable(rng_ick);
+		} else {
+			clk_enable(priv->clk);
+		}
 	}
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!priv->mem_res) {
+		ret = -ENOENT;
+		goto err_ioremap;
+	}
 
-	rng_base = devm_request_and_ioremap(&pdev->dev, res);
-	if (!rng_base) {
+	priv->base = devm_request_and_ioremap(&pdev->dev, priv->mem_res);
+	if (!priv->base) {
 		ret = -ENOMEM;
 		goto err_ioremap;
 	}
-	dev_set_drvdata(&pdev->dev, res);
+	dev_set_drvdata(&pdev->dev, priv);
 
 	ret = hwrng_register(&omap_rng_ops);
 	if (ret)
 		goto err_register;
 
 	dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
-		omap_rng_read_reg(RNG_REV_REG));
-	omap_rng_write_reg(RNG_MASK_REG, 0x1);
+		 omap_rng_read_reg(priv, RNG_REV_REG));
+
 
-	rng_dev = pdev;
+	omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
 
 	return 0;
 
 err_register:
-	rng_base = NULL;
+	priv->base = NULL;
 err_ioremap:
 	if (cpu_is_omap24xx()) {
-		clk_disable(rng_ick);
-		clk_put(rng_ick);
+		clk_disable(priv->clk);
+		clk_put(priv->clk);
 	}
+
+	kfree(priv);
+
 	return ret;
 }
 
 static int __exit omap_rng_remove(struct platform_device *pdev)
 {
+	struct omap_rng_private_data *priv = dev_get_drvdata(&pdev->dev);
+
 	hwrng_unregister(&omap_rng_ops);
 
-	omap_rng_write_reg(RNG_MASK_REG, 0x0);
+	omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
+
+	iounmap(priv->base);
 
 	if (cpu_is_omap24xx()) {
-		clk_disable(rng_ick);
-		clk_put(rng_ick);
+		clk_disable(priv->clk);
+		clk_put(priv->clk);
 	}
 
-	rng_base = NULL;
+	release_mem_region(priv->mem_res->start, resource_size(priv->mem_res));
+
+	kfree(priv);
 
 	return 0;
 }
@@ -164,13 +197,19 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
 
 static int omap_rng_suspend(struct device *dev)
 {
-	omap_rng_write_reg(RNG_MASK_REG, 0x0);
+	struct omap_rng_private_data *priv = dev_get_drvdata(dev);
+
+	omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
+
 	return 0;
 }
 
 static int omap_rng_resume(struct device *dev)
 {
-	omap_rng_write_reg(RNG_MASK_REG, 0x1);
+	struct omap_rng_private_data *priv = dev_get_drvdata(dev);
+
+	omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
+
 	return 0;
 }
 




From paul at pwsan.com  Mon Aug 27 19:36:12 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:12 -0600
Subject: [PATCH 5/5] hwrng: OMAP: remove SoC restrictions from driver
 registration
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120827233611.15045.19688.stgit@dusk.lan>

Remove the SoC restriction code from the OMAP RNG driver.  The
integration code in arch/arm/*omap* should handle this.  The device
shouldn't be created if it doesn't exist on the currently-booted SoC.

This allows us to remove some OMAP-specific cpu_is_omap*() calls from
the driver.  Also, if other OMAP chips have RNGs that can be used
by Linux, there will be no need to modify the driver.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Matt Mackall <mpm at selenic.com>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
---
 arch/arm/mach-omap1/devices.c     |    3 +++
 drivers/char/hw_random/omap-rng.c |    3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 7f3d9d2..aedd7a4 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -377,6 +377,9 @@ static struct platform_device omap1_rng_device = {
 
 static void omap1_init_rng(void)
 {
+	if (!cpu_is_omap16xx())
+		return;
+
 	(void) platform_device_register(&omap1_rng_device);
 }
 
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 748fcc8..a5effd8 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -220,9 +220,6 @@ static struct platform_driver omap_rng_driver = {
 
 static int __init omap_rng_init(void)
 {
-	if (!cpu_is_omap16xx() && !cpu_is_omap24xx())
-		return -ENODEV;
-
 	return platform_driver_register(&omap_rng_driver);
 }
 




From paul at pwsan.com  Mon Aug 27 19:36:11 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:11 -0600
Subject: [PATCH 3/5] hwrng: OMAP: convert to use runtime PM
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120827233610.15045.10090.stgit@dusk.lan>

Convert the OMAP onboard hardware RNG driver to use runtime PM.

This allows us to remove some OMAP-specific cpu_is_omap*() calls from
the RNG driver.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Matt Mackall <mpm at selenic.com>
Cc: Herbert Xu <herbert at gondor.apana.org.au>
---
 drivers/char/hw_random/omap-rng.c |   35 +++++++++--------------------------
 1 file changed, 9 insertions(+), 26 deletions(-)

diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index e0f0b98..748fcc8 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -18,12 +18,12 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/random.h>
-#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/hw_random.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <asm/io.h>
 
@@ -50,12 +50,10 @@
 /**
  * struct omap_rng_private_data - RNG IP block-specific data
  * @base: virtual address of the beginning of the RNG IP block registers
- * @clk: RNG clock
  * @mem_res: struct resource * for the IP block registers physical memory
  */
 struct omap_rng_private_data {
 	void __iomem *base;
-	struct clk *clk;
 	struct resource *mem_res;
 };
 
@@ -122,17 +120,6 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
 	omap_rng_ops.priv = (unsigned long)priv;
 	dev_set_drvdata(&pdev->dev, priv);
 
-	if (cpu_is_omap24xx()) {
-		priv->clk = clk_get(&pdev->dev, "ick");
-		if (IS_ERR(priv->clk)) {
-			dev_err(&pdev->dev, "Could not get rng_ick\n");
-			ret = PTR_ERR(priv->clk);
-			return ret;
-		} else {
-			clk_enable(priv->clk);
-		}
-	}
-
 	priv->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!priv->mem_res) {
 		ret = -ENOENT;
@@ -146,6 +133,9 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
 	}
 	dev_set_drvdata(&pdev->dev, priv);
 
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_get_sync(&pdev->dev);
+
 	ret = hwrng_register(&omap_rng_ops);
 	if (ret)
 		goto err_register;
@@ -153,19 +143,14 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
 	dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
 		 omap_rng_read_reg(priv, RNG_REV_REG));
 
-
 	omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
 
 	return 0;
 
 err_register:
 	priv->base = NULL;
+	pm_runtime_disable(&pdev->dev);
 err_ioremap:
-	if (cpu_is_omap24xx()) {
-		clk_disable(priv->clk);
-		clk_put(priv->clk);
-	}
-
 	kfree(priv);
 
 	return ret;
@@ -179,12 +164,8 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
 
 	omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
 
-	iounmap(priv->base);
-
-	if (cpu_is_omap24xx()) {
-		clk_disable(priv->clk);
-		clk_put(priv->clk);
-	}
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
 
 	release_mem_region(priv->mem_res->start, resource_size(priv->mem_res));
 
@@ -200,6 +181,7 @@ static int omap_rng_suspend(struct device *dev)
 	struct omap_rng_private_data *priv = dev_get_drvdata(dev);
 
 	omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
+	pm_runtime_put_sync(dev);
 
 	return 0;
 }
@@ -208,6 +190,7 @@ static int omap_rng_resume(struct device *dev)
 {
 	struct omap_rng_private_data *priv = dev_get_drvdata(dev);
 
+	pm_runtime_get_sync(dev);
 	omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
 
 	return 0;




From paul at pwsan.com  Mon Aug 27 19:36:11 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:11 -0600
Subject: [PATCH 4/5] ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120827233611.15045.34581.stgit@dusk.lan>

Move the OMAP1-specific RNG device creation off to mach-omap1/devices.c,
and create a omap_device-backed registration function for OMAP2+ devices
in mach-omap2/devices.c.

As a nice side-benefit, we can also get rid of
arch/arm/plat-omap/devices.c, thanks to some of the recent changes
from Tony.

One change from the previous behavior is that the RNG devices are now
registered unconditionally.  This should allow the RNG drivers to be
loaded as modules, even if the original kernel was not built that way.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap1/devices.c |   25 +++++++++++
 arch/arm/mach-omap2/devices.c |   18 ++++++++
 arch/arm/plat-omap/Makefile   |    3 -
 arch/arm/plat-omap/devices.c  |   92 -----------------------------------------
 4 files changed, 44 insertions(+), 94 deletions(-)
 delete mode 100644 arch/arm/plat-omap/devices.c

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index fa1fa4d..7f3d9d2 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -358,6 +358,30 @@ static inline void omap_init_uwire(void) {}
 #endif
 
 
+#define OMAP1_RNG_BASE		0xfffe5000
+
+static struct resource omap1_rng_resources[] = {
+	{
+		.start		= OMAP1_RNG_BASE,
+		.end		= OMAP1_RNG_BASE + 0x4f,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device omap1_rng_device = {
+	.name		= "omap_rng",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(omap1_rng_resources),
+	.resource	= omap1_rng_resources,
+};
+
+static void omap1_init_rng(void)
+{
+	(void) platform_device_register(&omap1_rng_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -396,6 +420,7 @@ static int __init omap1_init_devices(void)
 	omap_init_spi100k();
 	omap_init_sti();
 	omap_init_uwire();
+	omap1_init_rng();
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c00c689..bc62f1e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -464,6 +464,23 @@ static void omap_init_pmu(void)
 	platform_device_register(&omap_pmu_device);
 }
 
+/**
+ * omap_init_rng - bind the RNG hwmod to the RNG omap_device
+ *
+ * Bind the RNG hwmod to the RNG omap_device.  No return value.
+ */
+static void omap_init_rng(void)
+{
+	struct omap_hwmod *oh;
+	struct platform_device *pdev;
+
+	oh = omap_hwmod_lookup("rng");
+	if (!oh)
+		return;
+
+	pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+	WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
+}
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 
@@ -647,6 +664,7 @@ static int __init omap2_init_devices(void)
 	}
 	omap_init_pmu();
 	omap_init_sti();
+	omap_init_rng();
 	omap_init_sham();
 	omap_init_aes();
 	omap_init_vout();
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf85..a017e99 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-	 fb.o counter_32k.o
+obj-y := common.o sram.o clock.o dma.o mux.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 1cba927..0000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/devices.c
- *
- * Common platform device setup/initialization for OMAP1 and OMAP2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/memblock.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-
-#include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/mmc.h>
-#include <plat/menelaus.h>
-#include <plat/omap44xx.h>
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-#define	OMAP_RNG_BASE		0x480A0000
-#else
-#define	OMAP_RNG_BASE		0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-	{
-		.start		= OMAP_RNG_BASE,
-		.end		= OMAP_RNG_BASE + 0x4f,
-		.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap_rng_device = {
-	.name		= "omap_rng",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(rng_resources),
-	.resource	= rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-	(void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
-/*
- * This gets called after board-specific INIT_MACHINE, and initializes most
- * on-chip peripherals accessible on this board (except for few like USB):
- *
- *  (a) Does any "standard config" pin muxing needed.  Board-specific
- *	code will have muxed GPIO pins and done "nonstandard" setup;
- *	that code could live in the boot loader.
- *  (b) Populating board-specific platform_data with the data drivers
- *	rely on to handle wiring variations.
- *  (c) Creating platform devices as meaningful on this board and
- *	with this kernel configuration.
- *
- * Claiming GPIOs, and setting their direction and initial values, is the
- * responsibility of the device drivers.  So is responding to probe().
- *
- * Board-specific knowledge like creating devices or pin setup is to be
- * kept out of drivers as much as possible.  In particular, pin setup
- * may be handled by the boot loader, and drivers should expect it will
- * normally have been done by the time they're probed.
- */
-static int __init omap_init_devices(void)
-{
-	/* please keep these calls, and their implementations above,
-	 * in alphabetical order so they're easier to sort through.
-	 */
-	omap_init_rng();
-	return 0;
-}
-arch_initcall(omap_init_devices);




From paul at pwsan.com  Mon Aug 27 19:36:09 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 27 Aug 2012 17:36:09 -0600
Subject: [PATCH 1/5] ARM: OMAP2/3: hwmod: add RNG integration data
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120827233606.15045.59388.stgit@dusk.lan>

Add integration data for the hardware random number generator IP block
on some OMAP SoCs.  This appears to be present on OMAP2xxx and OMAP3xxx
SoCs, although it is not so easy to tell.  It may also be present on
other OMAP2+ SoCs.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 +
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    1 +
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |   17 +++++++++
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   37 ++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    5 ++-
 5 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 50cfab6..5a53287 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -587,6 +587,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__mcbsp1,
 	&omap2420_l4_core__mcbsp2,
 	&omap2420_l4_core__msdi1,
+	&omap2xxx_l4_core__rng,
 	&omap2420_l4_core__hdq1w,
 	&omap2420_l4_wkup__counter_32k,
 	NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 58b5bc1..256d8f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -947,6 +947,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 	&omap2430_l4_core__mcbsp4,
 	&omap2430_l4_core__mcbsp5,
 	&omap2430_l4_core__hdq1w,
+	&omap2xxx_l4_core__rng,
 	&omap2430_l4_wkup__counter_32k,
 	NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5178e40..14dc5ca 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
 	{ }
 };
 
+static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
+	{
+		.pa_start	= 0x480a0000,
+		.pa_end		= 0x480a004f,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
 /*
  * Common interconnect data
  */
@@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_rng_hwmod,
+	.clk		= "l4_ck",
+	.addr		= omap2_rng_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index afad69c..06a37db 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -745,3 +745,40 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 	},
 	.class		= &omap2xxx_counter_hwmod_class,
 };
+
+/* RNG */
+
+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
+	.rev_offs	= 0x3c,
+	.sysc_offs	= 0x40,
+	.syss_offs	= 0x44,
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2_rng_hwmod_class = {
+	.name		= "rng",
+	.sysc		= &omap2_rng_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
+	{ .irq = 52 },
+	{ .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_rng_hwmod = {
+	.name		= "rng",
+	.mpu_irqs	= omap2_rng_mpu_irqs,
+	.main_clk	= "l4_ck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 4,
+			.module_bit = OMAP24XX_EN_RNG_SHIFT,
+			.idlest_reg_id = 4,
+			.idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
+		},
+	},
+	.class		= &omap2_rng_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index e7e8eea..4363610 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -2,9 +2,8 @@
  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
  *
  * Copyright (C) 2010-2011 Nokia Corporation
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
  * Paul Walmsley
- *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Beno?t Cousson
  *
  * This program is free software; you can redistribute it and/or modify
@@ -76,6 +75,7 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_rng_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -102,6 +102,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];




From linus.walleij at linaro.org  Mon Aug 27 19:40:11 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:40:11 -0700
Subject: [PATCH 1/6] ARM: ux500: don't select LEDS_GPIO for snowball
In-Reply-To: <201208231426.43105.arnd@arndb.de>
References: <1345648390-4234-1-git-send-email-arnd@arndb.de>
 <1345648390-4234-2-git-send-email-arnd@arndb.de>
 <201208231426.43105.arnd@arndb.de>
Message-ID: <CACRpkdYbyrXRYTujEsKPofEpw01S8_B8b97edO-SpHjgfJ6V1Q@mail.gmail.com>

On Thu, Aug 23, 2012 at 7:26 AM, Arnd Bergmann <arnd at arndb.de> wrote:

> I discussed this with Lee on IRC, he really wants to keep the LED enabled for snowball
> for his own convenience. How is this version instead?

Sure, I guess you already merged it though?

Acked-by.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 27 19:42:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:42:49 -0700
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the Nomadik
 I2C driver
In-Reply-To: <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
 <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdapY3JvZmLxK7dX917O-E+aDgVE9ELnysjqAyETXMZHNw@mail.gmail.com>

On Thu, Aug 23, 2012 at 8:01 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Here we apply the bindings required for successful Device Tree
> probing of the i2c-nomadik driver.
>
> Cc: linux-i2c at vger.kernel.org
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Aug 27 19:46:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 16:46:45 -0700
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <20120825083811.GB7629@game.jcrosoft.org>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <5034FC18.2090400@wwwdotorg.org>
 <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>
 <50366D2B.4010807@wwwdotorg.org>
 <20120825083811.GB7629@game.jcrosoft.org>
Message-ID: <CACRpkdYWXZLNdgMhqoMZsaaszZ5Uz9pZ1EO=mrnuY5Der4O+Mw@mail.gmail.com>

On Sat, Aug 25, 2012 at 1:38 AM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> On 11:49 Thu 23 Aug     , Stephen Warren wrote:
>> On 08/23/2012 01:06 AM, Richard Genoud wrote:

>> > Let's take the PioA - peripheral B: 0xffe0399f
>> > From the documentation table 4-3, we can extract the column PIO
>> > Periperal B for all signals PA0-PA31:
>> ...
>> > Each time it's possible to mux a pin to the peripheral B function (ie
>> > when there's no "-----") the corresponding bit is set:
>> ...
>> > => this gives 0x399f
>>
>> Ah OK. It would be a good idea to briefly describe this process in the
>> binding document I think. I assume this property exists to avoid the
>> kernel driver having to contain tables for each Atmel device; the driver
>> is generic.
> Yeap I did this exactly for this
>
> I do not want to maintain such code for the whole bunch of at91
> and this way I add other SoC with just via dtsi without touching c code
>
> I think other driver should do so too

I'm following it now I think, after some discussion here at the kernel summit
I have come to the conclusion that the real problem with readability comes
from a shortcoming in the device tree compiler, that it cannot handle
macros and defines (no preprocessor) so it's currently hard to make
it more readable.

But that's not the implementers fault so I'm OK with this looking like
this for the moment.

Yours,
Linus Walleij


From will.deacon at arm.com  Mon Aug 27 19:49:45 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 Aug 2012 00:49:45 +0100
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <503BAEE7.5080401@free-electrons.com>
References: <1345799361-23735-1-git-send-email-gregory.clement@free-electrons.com>
 <1345799361-23735-4-git-send-email-gregory.clement@free-electrons.com>
 <20120824104309.GE5400@mudshark.cambridge.arm.com>
 <5037776A.6050605@free-electrons.com>
 <503BAEE7.5080401@free-electrons.com>
Message-ID: <20120827234944.GB7804@mudshark.cambridge.arm.com>

On Mon, Aug 27, 2012 at 06:31:19PM +0100, Gregory CLEMENT wrote:
> On 08/24/2012 02:45 PM, Gregory CLEMENT wrote:
> > On 08/24/2012 12:43 PM, Will Deacon wrote:> On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
> >> 2. I'm surprised that there aren't barriers and/or maintenance operations
> >>    needed around this operation. It might be worth checking in the
> >>    documentation that you have (you probably need at least an isb()
> >>    following the mcr).
> > 
> > I didn't find any mention of barriers and/or maintenance operations
> > needed around this operation, but maybe I have missed something, or it
> > was implicit for the people who wrote the documentation. I will ask
> > confirmation that we don't need this.
> 
> I've just received confirmation that this register is  r/w from non-secure.
> And that it would be good practice to have an ISB after this MCR, so I
> will add this for the next version coming soon.

That sounds about right, thanks for checking. Can you also confirm that
we don't need an explicit L2 invalidation, like we have for the
memory-mapped interface?

Cheers,

Will


From will.deacon at arm.com  Mon Aug 27 19:59:32 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 28 Aug 2012 00:59:32 +0100
Subject: [PATCH] ARM: MSM: Implement read_current_timer for msm timers
In-Reply-To: <1346102319-24497-1-git-send-email-sboyd@codeaurora.org>
References: <1345817604-9004-2-git-send-email-will.deacon@arm.com>
 <1346102319-24497-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <20120827235932.GA8468@mudshark.cambridge.arm.com>

On Mon, Aug 27, 2012 at 10:18:39PM +0100, Stephen Boyd wrote:
> Setup the same timer used as the clocksource to be used as the
> read_current_timer implementation. This allows us to support a
> stable udelay implementation on MSMs where it's possible for the
> CPUs to scale speeds independently of one another.
> 
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---
> 
> I have some patches to send that add DT support to the MSM timer that
> this conflicts with slightly. I'm not too concerned though, but we may
> want to decide what tree this goes through when I send out those patches.

Cheers Stephen, this looks good to me. After looking at this code some more
I think I'll change the read_current_timer function pointer type to be:

	unsigned long (*read_current_timer)(void);

since it doesn't make sense to return an error code from the platform
implementation (in fact, it will cause havoc in the delay loop).

I'll post a new patch -- rebasing your code should be trivial.

Cheers,

Will


From olof at lixom.net  Mon Aug 27 20:00:58 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 17:00:58 -0700
Subject: [GIT PULL] at91: fixes for 3.6 (take 1 bis)
In-Reply-To: <503B2AE7.4020704@atmel.com>
References: <5037A4F3.9090608@atmel.com>
 <503B2AE7.4020704@atmel.com>
Message-ID: <20120828000058.GB3571@quad.lixom.net>

On Mon, Aug 27, 2012 at 10:08:07AM +0200, Nicolas Ferre wrote:
> Hi,
> 
> This pull request supersedes the previous one from August 24th. It removes
> the ASoC SSC part which is now handled by Mark Brown.
> 
> The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:
> 
>   Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)
> 
> are available in the git repository at:
> 
>   git://github.com/at91linux/linux-at91.git tags/at91-fixes

Merged, thanks.


-Olof


From linus.walleij at linaro.org  Mon Aug 27 20:02:53 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 17:02:53 -0700
Subject: [PATCH V2 0/4] clk: Convert ARM ux500 to common clock
In-Reply-To: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346075153-14180-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdbH-vCfAYavO4Ef78Dy1dnphXc+JD76YHAhOiORsCWFHA@mail.gmail.com>

On Mon, Aug 27, 2012 at 6:45 AM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> This converts the ux500 machine specific clocks to the common
> clock framework. Old clock code are then removed from the ux500
> machine directory.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

For this whole patch set, Mike when you're pleased with the looks of this I'd
be very happy if you could merge this to your tree for some rotation
in linux-next....

Yours,
Linus Walleij


From olof at lixom.net  Mon Aug 27 20:05:04 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 27 Aug 2012 17:05:04 -0700
Subject: [GIT PULL] Renesas ARM-based SoC: Armadillo800EVA for 3.7
In-Reply-To: <20120827064506.GB26953@verge.net.au>
References: <1346049610-2266-1-git-send-email-horms@verge.net.au>
 <20120827064506.GB26953@verge.net.au>
Message-ID: <20120828000504.GC3571@quad.lixom.net>

On Mon, Aug 27, 2012 at 03:45:06PM +0900, Simon Horman wrote:
> Somehow I forgot to give the previous email a subject, not a good start :(
> 
> On Mon, Aug 27, 2012 at 03:40:08PM +0900, Simon Horman wrote:
> > Hi Arnd, Hi Olaf,
> > 
> > please consider the following enhancements for the Armadillo800EVA board
> > from Laurent Pinchart for inclusion in 3.7.
> > 
> > I am currently in the processes of taking over maintenance
> > of shmoble from Rafael Wysocki and this my the first pull request
> > in that role.
> > 
> > ----------------------------------------------------------------
> > The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
> > 
> >   Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git armadillo800eva

Thanks, pulled.


-Olof


From linus.walleij at linaro.org  Mon Aug 27 20:13:39 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 17:13:39 -0700
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
In-Reply-To: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
Message-ID: <CACRpkdaspHBDUjwf_bPtZoFeYK7q97oX4Jat=pmX810RtGJOpA@mail.gmail.com>

On Sat, Aug 25, 2012 at 5:20 AM, Sylwester Nawrocki
<sylvester.nawrocki at gmail.com> wrote:

> This short patch series converts remaining users of the s3c24xx SoC
> specific gpiolib functions to the gpiolib API and finally removes
> all s3c2410_* functions from drivers/gpio/gpio-samsung.c.

I'm fine with this as long as the Samsung maintainer is, so
Acked-by: Linus Walleij <linus.walleij at linaro.org>

But I suspect this will be merged through the Samsung SoC tree?

Yours,
Linus Walleij


From robherring2 at gmail.com  Mon Aug 27 20:14:12 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 27 Aug 2012 19:14:12 -0500
Subject: [GIT PULL] io.h clean-up for PCI
In-Reply-To: <20120827082755.GM18957@n2100.arm.linux.org.uk>
References: <50049285.1060100@gmail.com> <50130F36.4090902@gmail.com>
 <20120728143850.GA11713@mudshark.cambridge.arm.com>
 <50166A60.8000502@gmail.com> <20120730143119.GN6802@n2100.arm.linux.org.uk>
 <5016A0B8.5010607@gmail.com> <20120827082755.GM18957@n2100.arm.linux.org.uk>
Message-ID: <503C0D54.5090103@gmail.com>

On 08/27/2012 03:27 AM, Russell King - ARM Linux wrote:
> On Mon, Jul 30, 2012 at 09:56:56AM -0500, Rob Herring wrote:
>> On 07/30/2012 09:31 AM, Russell King - ARM Linux wrote:
>>> On Mon, Jul 30, 2012 at 06:05:04AM -0500, Rob Herring wrote:
>>>> On 07/28/2012 09:38 AM, Will Deacon wrote:
>>>>> Hi Rob,
>>>>>
>>>>> On Fri, Jul 27, 2012 at 10:59:18PM +0100, Rob Herring wrote:
>>>>>> Please pull updated io.h cleanup for PCI branch. I rebased this as the
>>>>>> changes shifted things around a bit. This has the following changes:
>>>>>>
>>>>>> - Incorporated fixes from you and Stephen
>>>>>> - Add early i/o mapping pci_map_io_early and enable on footbridge and
>>>>>> integrator for VGA console
>>>>>
>>>>> Unfortunately, I still experience the same hang on integrator with this
>>>>> revised patch series. Given the turnaround time for testing this, I don't
>>>>> think this should block the series, but I would like to get to the bottom of
>>>>> it if possible.
>>>>>
>>>>> I tried annotating the PCI code (including fault handlers) and the VGA
>>>>> console code but I couldn't find the culprit. I suppose the next step is
>>>>> JTAG, but that requires steal^Wborrowing some hardware from work.
>>>>
>>>> I did do some tests with qemu by adding i/o setup to integrator/cp.
>>>> Without it, I would abort on 0xfee003xx (vga regs). Once I added the
>>>> setup, I got to an abort on a PCI memory address which I did not setup.
>>>>
>>>> We can always revert integrator change if we can figure this out...
>>>
>>> Err, Integrator/CP doesn't have PCI nor does it have VGA.  Only the
>>> Integrator/AP has that.
>>
>> Yes, I know. But there is no AP model within qemu. I added the mapping
>> to AP and enabled VGA console to do some basic checks that i/o accesses
>> happen. It didn't really have to be integrator platform at all for this
>> test. I know it's not much of a test, but it's something beyond
>> compiling and staring at the code.
>>
>> I've also tested PCI i/o with versatile under qemu.
> 
> What's the conflict resolution for the fix for ioremap of phys 0 (posted
> by me previously) and your reoganisation and creation of
> vm_reserve_area_early() ?
> 
> Note that I'm taking the autobuilder offline until this is resolved because
> the tree currently isn't in a buildable state because of this.

I believe you can just replace VM_ARM_STATIC_MAPPING with
VM_ARM_EMPTY_MAPPING in vm_reserve_area_early. The pci i/o space and
empty sections are the same until pci_ioremap_io is called, and it does
not care what the vm flags are.

Rob



From linus.walleij at linaro.org  Mon Aug 27 20:16:01 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 17:16:01 -0700
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
In-Reply-To: <503C03D7.5050801@samsung.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
 <503C03D7.5050801@samsung.com>
Message-ID: <CACRpkdbh=vkZBpdf1p9VTpMw833iAxmBcq50mM=c3a6hYk0b-g@mail.gmail.com>

On Mon, Aug 27, 2012 at 4:33 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:

> Linus, this series should be sent to upstream via both trees, samsung and
> gpio to avoid useless merge conflicts. How do you think?

Take it all in the Samsung tree. You just need my ACK, which you have.

I don't have any big Samsung patches in my tree, just fixes that
will go into the -rc:s anyway.

Yours,
Linus Walleij


From santosh.shilimkar at ti.com  Mon Aug 27 20:17:30 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 27 Aug 2012 17:17:30 -0700
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
Message-ID: <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>

On Mon, Aug 27, 2012 at 4:26 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> On Mon, Aug 27, 2012 at 03:12:07PM -0700, Shilimkar, Santosh wrote:
>> On Mon, Aug 27, 2012 at 3:02 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
>> > Hi,
>> >
>> > On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote:
>> >> > -       pr_err("%s seen by %s %s at address %x\n",
>> >> > +       pr_err_ratelimited("%s seen by %s %s at address %x\n",
>> >> >                         omap3_l3_code_string(code),
>> >> >                         omap3_l3_initiator_string(initid),
>> >> >                         multi ? "Multiple Errors" : "", address);
>> >> > -       WARN_ON(1);
>> >> > +       WARN_ON_ONCE(1);
>> >> >
>> >> The issue needs to be fixed instead of WARN_ON_ONCE() and then
>> >> just moving ahead. Interconnect in bad states is really bad state and you
>> >> won't have reliable operations post that on SOC.
>> >
>> > How printing megabytes of identical stack traces helps anything?
>> >
>> It just says repeatedly and  loudly... Fix the issue :-)
>>
>> > This has been there always (since the L3 driver was added) on every boot
>> > with N950/N9 (which BTW are HS devices, not sure if that has anything
>> > to do with it). There is no apparent effect on device functionality,
>> > at least nothing unusual has been observed...
>> >
>> I assumed this is secure device when I saw the SRAM memset is causing the
>> issue.
>>
>> > Is there any documentation how to interpret and debug this error report?
>> >
>> The issue could be, there is memset tried on Secure portion of SRAM or
>> CPU speculatively accessed adjacent SRAM region of public SRAM which
>> is secure and hence the error.
>
> Thanks, that makes sense.
>
>> If you just bypass the SRAM init [1], does the issue go away ?
>
> I tried bypassing the whole SRAM init, but the device does not seem to
> boot up at all.
>
> If I comment out the memset alone, then it boots and the issue is gone:
>
> +#if 0
>         memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
>                   omap_sram_size - SRAM_BOOTLOADER_SZ);
> +#endif
>
Good. So the issue is indeed direct or indirect access to the secure SRAM.
As security can dynamically resize the secure RAM size it is even harder
to fix this issue properly. One easier way to deal with the issue is map only
needed SRAM and leave rest for security.

For now, Can you check if reducing the size of the SRAM in init is helping you
to get way with the issue. Sorry it might need few iterations for you to get
a working SRAM size.

Regards
Santosh


From horms at verge.net.au  Mon Aug 27 20:18:35 2012
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 Aug 2012 09:18:35 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: KZM-9A-GT for 3.7
Message-ID: <1346113116-20252-1-git-send-email-horms@verge.net.au>

Hi Olaf, Hi Arnd,

please consider the following enhancement for the KZM-9A-GT board
from Tetsuyuki Kobayashi for inclusion in 3.7.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git kzm9g

for you to fetch changes up to 7952717adb69efc1d2443a1858f96d23c2fb93e0:

  ARM: shmobile: kzm9g: enable restarting (2012-08-25 14:39:44 +0900)

----------------------------------------------------------------
Tetsuyuki Kobayashi (1):
      ARM: shmobile: kzm9g: enable restarting

 arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++++++
 1 file changed, 8 insertions(+)


From horms at verge.net.au  Mon Aug 27 20:18:36 2012
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 Aug 2012 09:18:36 +0900
Subject: [PATCH] ARM: shmobile: kzm9g: enable restarting
In-Reply-To: <1346113116-20252-1-git-send-email-horms@verge.net.au>
References: <1346113116-20252-1-git-send-email-horms@verge.net.au>
Message-ID: <1346113116-20252-2-git-send-email-horms@verge.net.au>

From: Tetsuyuki Kobayashi <koba at kmckk.co.jp>

Do soft-power-on-reset in sys_reboot system call.

How to test this patch
  Execute "sudo reboot" from command line. The system will start shutdown
  sequence and finally reboot and U-Boot restarts.

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 53b7ea9..fd21fb6 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -763,6 +763,13 @@ static void __init kzm_init(void)
 	platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
 }
 
+static void kzm9g_restart(char mode, const char *cmd)
+{
+#define RESCNT2 0xe6188020
+	/* Do soft power on reset */
+	writel((1 << 31), RESCNT2);
+}
+
 static const char *kzm9g_boards_compat_dt[] __initdata = {
 	"renesas,kzm9g",
 	NULL,
@@ -777,5 +784,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
 	.init_machine	= kzm_init,
 	.init_late	= shmobile_init_late,
 	.timer		= &shmobile_timer,
+	.restart	= kzm9g_restart,
 	.dt_compat	= kzm9g_boards_compat_dt,
 MACHINE_END
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Mon Aug 27 20:22:01 2012
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 Aug 2012 09:22:01 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: Core for 3.7
Message-ID: <1346113322-21133-1-git-send-email-horms@verge.net.au>

Hi Olaf, Hi Arnd,

please consider the following enhancement for the Renesas ARM-based SoC Core
from Tetsuyuki Kobayashi for inclusion in 3.7.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git soc-core

for you to fetch changes up to e3586c612e3a13118f0dbd2f6e9a4901b1695b81:

  ARM: mach-shmobile: Add compilation support for dtbs using 'make dtbs' (2012-08-25 14:38:13 +0900)

----------------------------------------------------------------
Tetsuyuki Kobayashi (1):
      ARM: mach-shmobile: Add compilation support for dtbs using 'make dtbs'

 arch/arm/mach-shmobile/Makefile.boot | 4 ++++
 1 file changed, 4 insertions(+)


From horms at verge.net.au  Mon Aug 27 20:22:02 2012
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 Aug 2012 09:22:02 +0900
Subject: [PATCH] ARM: mach-shmobile: Add compilation support for dtbs using
 'make dtbs'
In-Reply-To: <1346113322-21133-1-git-send-email-horms@verge.net.au>
References: <1346113322-21133-1-git-send-email-horms@verge.net.au>
Message-ID: <1346113322-21133-2-git-send-email-horms@verge.net.au>

From: Tetsuyuki Kobayashi <koba at kmckk.co.jp>

Add compilation support for dtbs using 'make dtbs'

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/Makefile.boot | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd9..a1227ce 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,3 +7,7 @@ __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
 #
 #params_phys-y (Instead: Pass atags pointer in r2)
 #initrd_phys-y (Instead: Use compiled-in initramfs)
+
+dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb
+dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dts
+dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dts
-- 
1.7.10.2.484.gcd07cc5



From linus.walleij at linaro.org  Mon Aug 27 20:25:51 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 27 Aug 2012 17:25:51 -0700
Subject: [PATCH 13/13] drivers/rtc/rtc-coh901331.c: use clk_prepare_enable
 and clk_disable_unprepare
In-Reply-To: <1345996865-32082-14-git-send-email-Julia.Lawall@lip6.fr>
References: <1345996865-32082-1-git-send-email-Julia.Lawall@lip6.fr>
 <1345996865-32082-14-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <CACRpkdYm9kOSD_czm8Co1cXybzkPXRLHkPH5auN-fPhcBBs0gw@mail.gmail.com>

On Sun, Aug 26, 2012 at 9:01 AM, Julia Lawall <Julia.Lawall at lip6.fr> wrote:

> I'm not sure about this.  Maybe it would be better to leave the disable and
> unprepare separated, since there is no matching nearby clk_prepare.

This is OK.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From sboyd at codeaurora.org  Mon Aug 27 20:27:05 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Mon, 27 Aug 2012 17:27:05 -0700
Subject: [PATCH] ARM: mach-shmobile: Add compilation support for dtbs
 using 'make dtbs'
In-Reply-To: <1346113322-21133-2-git-send-email-horms@verge.net.au>
References: <1346113322-21133-1-git-send-email-horms@verge.net.au>
 <1346113322-21133-2-git-send-email-horms@verge.net.au>
Message-ID: <503C1059.10300@codeaurora.org>

On 8/27/2012 5:22 PM, Simon Horman wrote:
> +dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dts
> +dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dts

Shouldn't these be dtb instead of dts?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From shawn.guo at linaro.org  Mon Aug 27 20:28:30 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 08:28:30 +0800
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <20120825083042.GM31998@S2101-09.ap.freescale.net>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <1345852300-2213-4-git-send-email-marex@denx.de>
 <20120825083042.GM31998@S2101-09.ap.freescale.net>
Message-ID: <20120828002828.GI2281@r65073-Latitude-D630>

On Sat, Aug 25, 2012 at 04:30:45PM +0800, Shawn Guo wrote:
> > +				flash: m25p80 at 0 {
> > +					#address-cells = <1>;
> > +					#size-cells = <1>;
> > +					compatible = "everspin,mr25h256", "mr25h256";
> 
> Node name "m25p80" and "mr25h256", same thing?
> 
Ok, just got reminded by Fabio, m25p80 covers many devices including
mr25h256 here.

-- 
Regards,
Shawn


From swarren at wwwdotorg.org  Mon Aug 27 20:38:37 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 27 Aug 2012 17:38:37 -0700
Subject: [PATCH] ARM: tegra: remove tegra_timer from tegra_list_clks
Message-ID: <1346114317-28486-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

tegra_time is a struct sys_timer, not a struct clk, so can't be included
in an array of struct clk *.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/tegra20_clocks_data.c |    1 -
 arch/arm/mach-tegra/tegra30_clocks_data.c |    1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index b9cb82b..be57764 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -926,7 +926,6 @@ PERIPH_CLK(pcie_xclk,	NULL,		  "pcie_xclk",  74,     0,	26000000,  mux_clk_m,
 static struct clk *tegra_list_clks[] = {
 	&tegra_apbdma,
 	&tegra_rtc,
-	&tegra_timer,
 	&tegra_i2s1,
 	&tegra_i2s2,
 	&tegra_spdif_out,
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e553..d92cb55 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1143,7 +1143,6 @@ struct clk *tegra_list_clks[] = {
 	&tegra_apbdma,
 	&tegra_rtc,
 	&tegra_kbc,
-	&tegra_timer,
 	&tegra_kfuse,
 	&tegra_fuse,
 	&tegra_fuse_burn,
-- 
1.7.9.5



From shawn.guo at linaro.org  Mon Aug 27 20:40:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 28 Aug 2012 08:40:29 +0800
Subject: [PATCH 1/3] ARM: mx28evk: Add SPI flash support
In-Reply-To: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
References: <1346084609-31407-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120828004027.GJ2281@r65073-Latitude-D630>

On Mon, Aug 27, 2012 at 01:23:27PM -0300, Fabio Estevam wrote:
> mx28evk has a free slot (J89) which can be used to populate an SPI NOR Flash.
> 
> Add support for it.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied all three patches, thanks.


From marek.vasut at gmail.com  Mon Aug 27 20:44:56 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 28 Aug 2012 02:44:56 +0200
Subject: [PATCH 4/4] ARM: mxs: Add SchulerControl SPS1 DTS file
In-Reply-To: <20120828002828.GI2281@r65073-Latitude-D630>
References: <1345852300-2213-1-git-send-email-marex@denx.de>
 <20120825083042.GM31998@S2101-09.ap.freescale.net>
 <20120828002828.GI2281@r65073-Latitude-D630>
Message-ID: <201208280244.56564.marex@denx.de>

Dear Shawn Guo,

> On Sat, Aug 25, 2012 at 04:30:45PM +0800, Shawn Guo wrote:
> > > +				flash: m25p80 at 0 {
> > > +					#address-cells = <1>;
> > > +					#size-cells = <1>;
> > > +					compatible = "everspin,mr25h256", 
"mr25h256";
> > 
> > Node name "m25p80" and "mr25h256", same thing?
> 
> Ok, just got reminded by Fabio, m25p80 covers many devices including
> mr25h256 here.

I still need to look into the OUI

Best regards,
Marek Vasut


From koba at kmckk.co.jp  Mon Aug 27 21:00:08 2012
From: koba at kmckk.co.jp (Tetsuyuki Kobayashi)
Date: Tue, 28 Aug 2012 10:00:08 +0900
Subject: [PATCH] ARM: mach-shmobile: Add compilation support for dtbs
 using 'make dtbs'
In-Reply-To: <503C1059.10300@codeaurora.org>
References: <1346113322-21133-1-git-send-email-horms@verge.net.au>
 <1346113322-21133-2-git-send-email-horms@verge.net.au>
 <503C1059.10300@codeaurora.org>
Message-ID: <503C1818.7020402@kmckk.co.jp>

Simon-san,

(2012/08/28 9:27), Stephen Boyd wrote:
> On 8/27/2012 5:22 PM, Simon Horman wrote:
>> +dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dts
>> +dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dts
>
> Shouldn't these be dtb instead of dts?
>

Please use my v2 patch.
I paste v2 patch here. (It was posted on 2012/07/23)

==============================================================
From: Tetsuyuki Kobayashi <koba at kmckk.co.jp>

Add compilation support for dtbs using 'make dtbs'

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Cc: Simon Horman <horms at verge.net.au>
Signed-off-by: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
---
Sorry, I found mistake. it should be dtb insted of dts.

Changes for v2
- replace dts to dtb in the 3rd and 4th line of patch.

  arch/arm/mach-shmobile/Makefile.boot |    4 ++++
  1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-shmobile/Makefile.boot 
b/arch/arm/mach-shmobile/Makefile.boot
index 498efd9..5e41019 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,3 +7,7 @@ __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
  #
  #params_phys-y (Instead: Pass atags pointer in r2)
  #initrd_phys-y (Instead: Use compiled-in initramfs)
+
+dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb
+dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb
+dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb
-- 1.7.9.5


From horms at verge.net.au  Mon Aug 27 21:06:43 2012
From: horms at verge.net.au (Simon Horman)
Date: Tue, 28 Aug 2012 10:06:43 +0900
Subject: [PATCH] ARM: mach-shmobile: Add compilation support for dtbs
 using 'make dtbs'
In-Reply-To: <503C1818.7020402@kmckk.co.jp>
References: <1346113322-21133-1-git-send-email-horms@verge.net.au>
 <1346113322-21133-2-git-send-email-horms@verge.net.au>
 <503C1059.10300@codeaurora.org> <503C1818.7020402@kmckk.co.jp>
Message-ID: <20120828010643.GA24108@verge.net.au>

On Tue, Aug 28, 2012 at 10:00:08AM +0900, Tetsuyuki Kobayashi wrote:
> Simon-san,
> 
> (2012/08/28 9:27), Stephen Boyd wrote:
> >On 8/27/2012 5:22 PM, Simon Horman wrote:
> >>+dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dts
> >>+dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dts
> >
> >Shouldn't these be dtb instead of dts?
> >
> 
> Please use my v2 patch.
> I paste v2 patch here. (It was posted on 2012/07/23)

Sorry about that. Please ignore this pull request.
I will repost.

> 
> ==============================================================
> From: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
> 
> Add compilation support for dtbs using 'make dtbs'
> 
> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> Cc: Simon Horman <horms at verge.net.au>
> Signed-off-by: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
> ---
> Sorry, I found mistake. it should be dtb insted of dts.
> 
> Changes for v2
> - replace dts to dtb in the 3rd and 4th line of patch.
> 
>  arch/arm/mach-shmobile/Makefile.boot |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/Makefile.boot
> b/arch/arm/mach-shmobile/Makefile.boot
> index 498efd9..5e41019 100644
> --- a/arch/arm/mach-shmobile/Makefile.boot
> +++ b/arch/arm/mach-shmobile/Makefile.boot
> @@ -7,3 +7,7 @@ __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
>  #
>  #params_phys-y (Instead: Pass atags pointer in r2)
>  #initrd_phys-y (Instead: Use compiled-in initramfs)
> +
> +dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb
> +dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb
> +dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb
> -- 1.7.9.5
> 


From koba at kmckk.co.jp  Mon Aug 27 21:15:03 2012
From: koba at kmckk.co.jp (Tetsuyuki Kobayashi)
Date: Tue, 28 Aug 2012 10:15:03 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: KZM-9A-GT for 3.7
In-Reply-To: <1346113116-20252-1-git-send-email-horms@verge.net.au>
References: <1346113116-20252-1-git-send-email-horms@verge.net.au>
Message-ID: <503C1B97.3070004@kmckk.co.jp>

(2012/08/28 9:18), Simon Horman wrote:
> Hi Olaf, Hi Arnd,
> 
> please consider the following enhancement for the KZM-9A-GT board

Just a minor correction :)
The board name is KZM-A9-GT.


> from Tetsuyuki Kobayashi for inclusion in 3.7.
> 
> ----------------------------------------------------------------
> The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
> 
>    Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
> 
> are available in the git repository at:
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git kzm9g
> 
> for you to fetch changes up to 7952717adb69efc1d2443a1858f96d23c2fb93e0:
> 
>    ARM: shmobile: kzm9g: enable restarting (2012-08-25 14:39:44 +0900)
> 
> ----------------------------------------------------------------
> Tetsuyuki Kobayashi (1):
>        ARM: shmobile: kzm9g: enable restarting
> 
>   arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From xiechao.mail at gmail.com  Mon Aug 27 21:40:07 2012
From: xiechao.mail at gmail.com (Chao Xie)
Date: Tue, 28 Aug 2012 09:40:07 +0800
Subject: [PATCH 1/5] arm: mmp: make private clock definition exclude from
 common clock
In-Reply-To: <CAN1soZy54UcoQ_qrN2Wh4ZWVMCXj3gpHZas57GqQeT988dnkQQ@mail.gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
 <CAN1soZy54UcoQ_qrN2Wh4ZWVMCXj3gpHZas57GqQeT988dnkQQ@mail.gmail.com>
Message-ID: <CADApbegJwd3jQr+rKd-54AxhZG=On0LSEG5ioX-jnq9S0xY=ug@mail.gmail.com>

On Tue, Aug 28, 2012 at 6:42 AM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> On Mon, Aug 27, 2012 at 10:53 AM, Chao Xie <xiechao.mail at gmail.com> wrote:
>> From: Chao Xie <chao.xie at marvell.com>
>>
>> the clock.c is mmp private implementation, make it excluded
>> from common clock framework
>>
>> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
>> ---
>>  arch/arm/mach-mmp/Makefile |    5 ++++-
>>  1 files changed, 4 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
>> index b786f7e..815c3e7 100644
>> --- a/arch/arm/mach-mmp/Makefile
>> +++ b/arch/arm/mach-mmp/Makefile
>> @@ -2,13 +2,16 @@
>>  # Makefile for Marvell's PXA168 processors line
>>  #
>>
>> -obj-y                          += common.o clock.o devices.o time.o irq.o
>> +obj-y                          += common.o devices.o time.o irq.o
>>
>>  # SoC support
>>  obj-$(CONFIG_CPU_PXA168)       += pxa168.o
>>  obj-$(CONFIG_CPU_PXA910)       += pxa910.o
>>  obj-$(CONFIG_CPU_MMP2)         += mmp2.o sram.o
>>
>> +ifeq ($(CONFIG_COMMON_CLK), )
>> +obj-y                          += clock.o
>> +endif
>
> Why not to discard all private clock code? Maybe you can use common
> clk in arch-mmp directly.
Our dvfs and devfreq are set up based on private clock code. The
migration of dvfs and devfreq is on going. Checking in common clock
framework code will help us mirgarate the dvfs and devfreq, but i do
not want to block the our product development, so I would like to keep
the private clock code untile we have settle down all the problems.


From b29396 at freescale.com  Mon Aug 27 22:01:42 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 10:01:42 +0800
Subject: [PATCH v2 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <20120827220830.GB2281@r65073-Latitude-D630>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-2-git-send-email-b29396@freescale.com>
 <20120827220830.GB2281@r65073-Latitude-D630>
Message-ID: <20120828020141.GD5822@shlinux2.ap.freescale.net>

On Tue, Aug 28, 2012 at 06:08:32AM +0800, Shawn Guo wrote:
> On Mon, Aug 27, 2012 at 03:24:39PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Add regmap based syscon driver.
> > This is usually used for access misc bits in registers which does not belong
> > to a specific module, for example, IMX IOMUXC GPR and ANATOP.
> > With this driver, client can use generic regmap API to access registers
> > which are registered into syscon.
> > 
> > Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> > ChangeLog:
> > v1->v2:
> >  * provide a way of retrieving the regmap, suggested by Mark Brown.
> >  * delete imx-syscon io accessors and using generic regmap API for client drivers.
> >  * change to a more generic name for other SoCs to use.
> > ---
> >  .../devicetree/bindings/mfd/imx-syscon.txt         |   11 ++
> 
> So, this file should be renamed as well.
> 
Correct.
I missed it, thanks for reminder.

> >  drivers/mfd/Kconfig                                |    7 +
> >  drivers/mfd/Makefile                               |    1 +
> >  drivers/mfd/syscon.c                               |  169 ++++++++++++++++++++
> >  include/linux/mfd/syscon.h                         |   22 +++
> >  5 files changed, 210 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mfd/imx-syscon.txt b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> > new file mode 100644
> > index 0000000..c1a13b4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/imx-syscon.txt
> > @@ -0,0 +1,11 @@
> > +* System Controller Registers R/W driver
> > +
> > +Required properties:
> > +- compatible: Should contain "syscon".
> > +- reg: the register range can be access from syscon
> > +
> > +Examples:
> > +gpr: iomuxc-gpr at 020e0000 {
> > +	compatible = "fsl,imx6q-iomuxc", "syscon";
> > +	reg = <0x020e0000 0x38>;
> > +};
> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> > index b1a1462..4a6c48e 100644
> > --- a/drivers/mfd/Kconfig
> > +++ b/drivers/mfd/Kconfig
> > @@ -993,6 +993,13 @@ config MFD_ANATOP
> >  	  MFD controller. This controller embeds regulator and
> >  	  thermal devices for Freescale i.MX platforms.
> >  
> > +config MFD_SYSCON
> > +        bool "System Controller Register R/W Based on Regmap"
> > +        select REGMAP_MMIO
> > +        help
> > +          Select this option to enable accessing system control registers
> > +	  via regmap.
> > +
> >  config MFD_PALMAS
> >  	bool "Support for the TI Palmas series chips"
> >  	select MFD_CORE
> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> > index 79dd22d..8384bc9 100644
> > --- a/drivers/mfd/Makefile
> > +++ b/drivers/mfd/Makefile
> > @@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
> >  obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
> >  obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
> >  obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
> > +obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
> >  obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
> > diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
> > new file mode 100644
> > index 0000000..da2464f
> > --- /dev/null
> > +++ b/drivers/mfd/syscon.c
> > @@ -0,0 +1,169 @@
> > +/*
> > + * System Control Driver
> > + *
> > + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2012 Linaro Ltd.
> > + *
> > + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +static struct platform_driver syscon_driver;
> > +
> > +struct syscon {
> > +	struct device *dev;
> > +	void __iomem *base;
> > +	struct regmap *regmap;
> > +};
> > +
> > +static int syscon_match(struct device *dev, void *data)
> > +{
> > +	struct syscon *syscon = dev_get_drvdata(dev);
> > +	struct device_node *dn = data;
> > +
> > +	return (syscon->dev->of_node == dn) ? 1 : 0;
> > +}
> > +
> > +static struct regmap *syscon_node_to_regmap(struct device_node *np)
> > +{
> > +	struct syscon *syscon;
> > +	struct device *dev;
> > +
> > +	dev = driver_find_device(&syscon_driver.driver, NULL, np,
> > +				 syscon_match);
> > +	of_node_put(np);
> > +
> > +	if (!dev)
> > +		return ERR_PTR(-EPROBE_DEFER);
> > +
> > +	syscon = dev_get_drvdata(dev);
> > +
> > +	return syscon->regmap;
> > +}
> > +
> > +struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
> > +{
> > +	struct device_node *syscon_np;
> > +
> > +	syscon_np = of_find_compatible_node(NULL, NULL, s);
> > +	if (!syscon_np)
> > +		return ERR_PTR(-ENODEV);
> > +
> > +	return syscon_node_to_regmap(syscon_np);
> > +}
> > +
> > +struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
> > +					const char *property)
> > +{
> > +	struct device_node *syscon_np;
> > +
> > +	syscon_np = of_parse_phandle(np, property, 0);
> > +	if (!syscon_np)
> > +		return ERR_PTR(-ENODEV);
> > +
> > +	return syscon_node_to_regmap(syscon_np);
> > +}
> 
> The above two APIs are all about finding the device_node for syscon,
> and can be done by clients in whatever way that is easy for them.
> Then we can save these APIs and export syscon_node_to_regmap directly.
> 
Yes, we probably should also export syscon_node_to_regmap.
For other two, since they're common to be used, i prefer to keep them too
for user to choose to use, it saves client to write duplicate code.

> > +
> > +static const struct of_device_id of_syscon_match[] = {
> > +	{ .compatible = "syscon", },
> > +	{ },
> > +};
> > +
> > +static struct regmap_config syscon_regmap_config = {
> > +	.reg_bits = 32,
> > +	.val_bits = 32,
> > +	.reg_stride = 4,
> > +};
> > +
> > +static int __devinit syscon_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct device_node *np = dev->of_node;
> > +	struct syscon *syscon;
> > +	struct resource res;
> > +	int ret;
> > +
> > +	if (!np)
> > +		return -ENOENT;
> > +
> > +	syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
> > +			    GFP_KERNEL);
> > +	if (!syscon)
> > +		return -ENOMEM;
> > +
> > +	syscon->base = of_iomap(np, 0);
> > +	if (!syscon->base)
> > +		return -EADDRNOTAVAIL;
> > +
> > +	ret = of_address_to_resource(np, 0, &res);
> > +	if (ret)
> > +		return ret;
> > +
> > +	syscon_regmap_config.max_register = res.end - res.start - 3;
> > +	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
> > +					&syscon_regmap_config);
> > +	if (IS_ERR(syscon->regmap)) {
> > +		dev_err(&pdev->dev, "regmap init failed\n");
> > +		return PTR_ERR(syscon->regmap);
> > +	}
> > +
> > +	regcache_cache_only(syscon->regmap, false);
> > +
> > +	syscon->dev = &pdev->dev;
> > +	platform_set_drvdata(pdev, syscon);
> > +
> > +	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
> > +		res.start, res.end);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __devexit syscon_remove(struct platform_device *pdev)
> > +{
> > +	struct syscon *syscon;
> > +
> > +	syscon = platform_get_drvdata(pdev);
> > +	iounmap(syscon->base);
> > +	platform_set_drvdata(pdev, NULL);
> > +
> > +	return 0;
> > +}
> > +
> > +static struct platform_driver syscon_driver = {
> > +	.driver = {
> > +		.name = "syscon",
> > +		.owner = THIS_MODULE,
> > +		.of_match_table = of_syscon_match,
> > +	},
> > +	.probe		= syscon_probe,
> > +	.remove		= syscon_remove,
> > +};
> > +
> > +static int __init syscon_init(void)
> > +{
> > +	return platform_driver_register(&syscon_driver);
> > +}
> > +postcore_initcall(syscon_init);
> > +
> > +static void __exit anatop_exit(void)
> 
> s/anatop_exit/syscon_exit
> 
> > +{
> > +	platform_driver_unregister(&syscon_driver);
> > +}
> > +module_exit(anatop_exit);
> 
> Ditto.
> 
Correct, Thanks.
Will fix those typo in updated patches.

Regards
Dong Aisheng
> > +
> > +MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
> > +MODULE_DESCRIPTION("System Control driver");
> > +MODULE_LICENSE("GPL v2");
> > diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
> > new file mode 100644
> > index 0000000..990d7cf
> > --- /dev/null
> > +++ b/include/linux/mfd/syscon.h
> > @@ -0,0 +1,22 @@
> > +/*
> > + * System Control Driver
> > + *
> > + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2012 Linaro Ltd.
> > + *
> > + * Author: Dong Aisheng <dong.aisheng at linaro.org>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef __LINUX_MFD_SYSCON_H__
> > +#define __LINUX_MFD_SYSCON_H__
> > +
> > +extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
> > +extern struct regmap *syscon_regmap_lookup_by_phandle(
> > +					struct device_node *np,
> > +					const char *property);
> > +#endif /* __LINUX_MFD_SYSCON_H__ */
> > -- 
> > 1.7.0.4
> > 
> > 
> 



From b29396 at freescale.com  Mon Aug 27 22:08:07 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 10:08:07 +0800
Subject: [PATCH v2 4/7] regulator: anatop-regulator: convert to use
 syscon to access anatop register
In-Reply-To: <20120827221532.GC2281@r65073-Latitude-D630>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-5-git-send-email-b29396@freescale.com>
 <20120827221532.GC2281@r65073-Latitude-D630>
Message-ID: <20120828020806.GE5822@shlinux2.ap.freescale.net>

On Tue, Aug 28, 2012 at 06:15:35AM +0800, Shawn Guo wrote:
....
> > +	sreg->anatop = syscon_regmap_lookup_by_phandle(np, "fsl,anatop");
> > +	if (IS_ERR(sreg->anatop))
> > +		return PTR_ERR(sreg->anatop);
> > +
> 
> All the anatop regulators are child nodes of anatop.  It looks a little
> odd to use phandle there.  of_get_parent should just works.
> 
Yes, this is a special case.
It's also ok for me to use of_get_parent if you want.
Will update it.

Regards
Dong Aisheng



From richard.zhao at freescale.com  Mon Aug 27 23:23:10 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 11:23:10 +0800
Subject: [PATCH v2 5/7] ARM: imx6q: convert to use syscon to access
 anatop registers
In-Reply-To: <1346052285-4344-6-git-send-email-b29396@freescale.com>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-6-git-send-email-b29396@freescale.com>
Message-ID: <20120828032309.GW4011@b20223-02.ap.freescale.net>

On Mon, Aug 27, 2012 at 03:24:43PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Using syscon to access anatop registers.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog v1->v2:
>  * update to use generic regmap api
> ---
>  arch/arm/mach-imx/Kconfig      |    2 +-
>  arch/arm/mach-imx/mach-imx6q.c |   43 ++++++++++++++++-----------------------
>  2 files changed, 19 insertions(+), 26 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index afd542a..7bba253 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -839,7 +839,7 @@ config SOC_IMX6Q
>  	select HAVE_IMX_MMDC
>  	select HAVE_IMX_SRC
>  	select HAVE_SMP
> -	select MFD_ANATOP
> +	select MFD_SYSCON
>  	select PINCTRL
>  	select PINCTRL_IMX6Q
>  
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index 045b3f6..5de869a 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -24,8 +24,9 @@
>  #include <linux/of_platform.h>
>  #include <linux/pinctrl/machine.h>
>  #include <linux/phy.h>
> +#include <linux/regmap.h>
>  #include <linux/micrel_phy.h>
> -#include <linux/mfd/anatop.h>
> +#include <linux/mfd/syscon.h>
>  #include <asm/cpuidle.h>
>  #include <asm/smp_twd.h>
>  #include <asm/hardware/cache-l2x0.h>
> @@ -121,38 +122,30 @@ static void __init imx6q_sabrelite_init(void)
>  static void __init imx6q_usb_init(void)
>  {
>  	struct device_node *np;
> -	struct platform_device *pdev = NULL;
> -	struct anatop *adata = NULL;
> +	struct regmap *anatop;
>  
>  	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
np unused.
> -	if (np)
> -		pdev = of_find_device_by_node(np);
> -	if (pdev)
> -		adata = platform_get_drvdata(pdev);
> -	if (!adata) {
> -		if (np)
> -			of_node_put(np);
> -		return;
> -	}
> -
>  #define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
>  #define HW_ANADIG_USB2_CHRG_DETECT		0x00000210
>  
>  #define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
>  #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000
>  
> -	/*
> -	 * The external charger detector needs to be disabled,
> -	 * or the signal at DP will be poor
> -	 */
> -	anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
> -			BM_ANADIG_USB_CHRG_DETECT_EN_B
> -			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
> -			~0);
> -	anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
> -			BM_ANADIG_USB_CHRG_DETECT_EN_B |
> -			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
> -			~0);
> +	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
> +	if (!IS_ERR(anatop)) {
> +		/*
> +		 * The external charger detector needs to be disabled,
> +		 * or the signal at DP will be poor
> +		 */
> +		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
> +				BM_ANADIG_USB_CHRG_DETECT_EN_B
> +				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
> +		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
> +				BM_ANADIG_USB_CHRG_DETECT_EN_B |
> +				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
> +	} else {
> +		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
> +	}
>  
>  	of_node_put(np);
unneeded.

Thanks
Richard
>  }
> -- 
> 1.7.0.4
> 



From thomas.abraham at linaro.org  Tue Aug 28 00:44:02 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 10:14:02 +0530
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208271001.05026.heiko@sntech.de>
References: <201208252353.59345.heiko@sntech.de>
 <CAJuYYwQBOP7-D0fepDsCr+43ASKQ3CmMBMH-M79QH7r=xS85Eg@mail.gmail.com>
 <201208271001.05026.heiko@sntech.de>
Message-ID: <CAJuYYwT0dot7pqq_buDWj+8taK6oaPhGZKS+Z2p7tF0mT2Mexg@mail.gmail.com>

On 27 August 2012 13:31, Heiko St?bner <heiko at sntech.de> wrote:
> Hi Thomas,
>
> thanks for your review:
>
> Am Montag, 27. August 2012, 06:20:49 schrieb Thomas Abraham:
>> Hi Heiko,
>>
>> On 26 August 2012 03:23, Heiko St?bner <heiko at sntech.de> wrote:
>> > Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
>> > via the device tree. This patch implements dt-support for the
>> > s3c24xx arches.
>> >
>> > The controllers contain only 3 cells, as the underlying gpio controller
>> > does not support controlling the drive strength on a gpio level.
>> >
>> > Tested with the gpio-keys driver on a s3c2416 based machine.
>> >
>> > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
>> > ---
>> >
>> >  .../devicetree/bindings/gpio/gpio-samsung.txt      |   38 ++++++++++++
>> >  drivers/gpio/gpio-samsung.c                        |   63
>> >  ++++++++++++++++++++ 2 files changed, 101 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
>> > b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt index
>> > 5375625..ce6a7d4 100644
>> > --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
>> > +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
>> >
>> > @@ -39,3 +39,41 @@ Example:
>> >                 #gpio-cells = <4>;
>> >                 gpio-controller;
>> >
>> >         };
>> >
>> > +
>> > +
>> > +Samsung S3C24XX GPIO Controller
>> > +
>> > +Required properties:
>> > +- compatible: Compatible property value should be
>> > "samsung,s3c24xx-gpio".
>>
>> This is debatable, but I would choose to be specific here and use
>> "samsing,s3c2416-gpio". For instance, SoC's in s3c24xx family have
>> differing value for pull none/down/up.
>
> Hmmm, but the logic to drive the gpio controller is the same for all arches.
> The only difference is the number to use for the different pull up/down
> settings. So I think the "samsung,s3c24xx-gpio" is ok but the documentation
> should simply reflect the different pull settings.

Ok.

>
>
>> > +
>> > +- reg: Physical base address of the controller and length of memory
>> > mapped +  region.
>> > +
>> > +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by
>> > client nodes +  should be the following with values derived from the SoC
>> > user manual. +     <[phandle of the gpio controller node]
>> > +      [pin number within the gpio controller]
>> > +      [mux function]
>> > +      [flags and pull up/down]
>> > +
>> > +  Values for gpio specifier:
>> > +  - Pin number: depending on the controller a number from 0 up to 15.
>> > +  - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
>> > +                            1 - Pull Down Enabled.
>> > +                            3 - Pull Up Enabled.
>>
>> As per s3c2416 user manual, 2 is used for Pull Up and 3 is listed as
>> reserved value. Any particular reason to use 3 here for pull up and
>> not 2 as per the user manual?
>
> Sorry, copy and paste error :-)

Ok.

>
>
>> > +          Bit 16 (0x00010000) - Input is active low.
>> > +
>> > +- gpio-controller: Specifies that the node is a gpio controller.
>> > +- #address-cells: should be 1.
>> > +- #size-cells: should be 1.
>>
>> It would be informative to add information about the 'mux function'
>> cell here as well. Specifically, on how to handle the banks that have
>> an extended GPxSEL register that allow additional pin function
>> selection.
>
> Will add a mux function description.
>
> Until now I've never realised the existence of the GPxSEL registers, so thanks
> for the pointer :-).
>
> But is this used in the driver at all? All the setcfg/getcfg functions in
> gpio-samsung.c only handle the GPxCON registers - I haven't found code to
> handle the GPxSEL registers at all. So my guess is that this was never
> implemented - or that I'm blind ;-) .

You are right, there is no code that is handling the GPxCON registers.

Thanks,
Thomas.

>
>
>> > +
>> > +Example:
>> > +
>> > +       gpa: gpio-controller at 56000000 {
>> > +               #address-cells = <1>;
>> > +               #size-cells = <1>;
>> > +               compatible = "samsung,s3c24xx-gpio";
>> > +               reg = <0x56000000 0x10>;
>> > +               #gpio-cells = <3>;
>> > +               gpio-controller;
>> > +       };
>> > diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
>> > index a150d2e..80a2817 100644
>> > --- a/drivers/gpio/gpio-samsung.c
>> > +++ b/drivers/gpio/gpio-samsung.c
>> > @@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct
>> > samsung_gpio_chip *chip)
>> >
>> >                 s3c_gpiolib_track(chip);
>> >
>> >  }
>> >
>> > +#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
>> > +static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
>> > +                       const struct of_phandle_args *gpiospec, u32
>> > *flags) +{
>> > +       unsigned int pin;
>> > +
>> > +       if (WARN_ON(gc->of_gpio_n_cells < 3))
>> > +               return -EINVAL;
>> > +
>> > +       if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
>> > +               return -EINVAL;
>> > +
>> > +       if (gpiospec->args[0] > gc->ngpio)
>> > +               return -EINVAL;
>> > +
>> > +       pin = gc->base + gpiospec->args[0];
>> > +
>> > +       if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
>> > +               pr_warn("gpio_xlate: failed to set pin function\n");
>> > +       if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
>> > +               pr_warn("gpio_xlate: failed to set pin pull up/down\n");
>> > +
>> > +       if (flags)
>> > +               *flags = gpiospec->args[2] >> 16;
>> > +
>> > +       return gpiospec->args[0];
>> > +}
>> > +
>> > +static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
>> > +       { .compatible = "samsung,s3c24xx-gpio", },
>> > +       {}
>> > +};
>> > +
>> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
>> > samsung_gpio_chip *chip, +
>> >  u64 base, u64 offset) +{
>> > +       struct gpio_chip *gc =  &chip->chip;
>> > +       u64 address;
>> > +
>> > +       if (!of_have_populated_dt())
>> > +               return;
>> > +
>> > +       address = chip->base ? base + ((u32)chip->base & 0xfff) : base +
>> > offset; +       gc->of_node = of_find_matching_node_by_address(NULL,
>> > +                       s3c24xx_gpio_dt_match, address);
>> > +       if (!gc->of_node) {
>> > +               pr_info("gpio: device tree node not found for gpio
>> > controller" +                       " with base address %08llx\n",
>> > address); +               return;
>> > +       }
>> > +       gc->of_gpio_n_cells = 3;
>> > +       gc->of_xlate = s3c24xx_gpio_xlate;
>> > +}
>> > +#elif defined(CONFIG_PLAT_S3C24XX)
>> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
>> > samsung_gpio_chip *chip, +
>> >  u64 base, u64 offset) +{
>> > +       return;
>> > +}
>> > +#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
>> > +
>> >
>> >  static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip
>> >  *chip,
>> >
>> >                                              int nr_chips, void __iomem
>> >                                              *base)
>> >
>> >  {
>> >
>> > @@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct
>> > samsung_gpio_chip *chip,
>> >
>> >                         gc->direction_output =
>> >                         samsung_gpiolib_2bit_output;
>> >
>> >                 samsung_gpiolib_add(chip);
>> >
>> > +
>> > +               s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i *
>> > 0x10);
>> >
>> >         }
>> >
>> >  }
>> >
>> > --
>> > 1.7.2.3
>>
>> Overall, this is patch looks fine.
>>
>> Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>
>
>
> Heiko


From thomas.abraham at linaro.org  Tue Aug 28 00:59:17 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 10:29:17 +0530
Subject: [PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller
 clocks
In-Reply-To: <503BFF8E.80503@samsung.com>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-2-git-send-email-thomas.abraham@linaro.org>
 <503BFF8E.80503@samsung.com>
Message-ID: <CAJuYYwT6L+Nfd_k2f9hCyJTbrqzedgOUcr7F2MbPvmstin=y4g@mail.gmail.com>

On 28 August 2012 04:45, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add clock instances for bus interface unit clock and card interface unit
>> clock of the all four MSHC controller instances.
>>
>> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>> ---
>>   arch/arm/mach-exynos/clock-exynos5.c |   45
>> ++++++++++++----------------------
>>   1 files changed, 16 insertions(+), 29 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>> b/arch/arm/mach-exynos/clock-exynos5.c
>> index 3b00e29..16d8bef 100644
>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>> @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
>>                 .enable         = exynos5_clk_ip_peris_ctrl,
>>                 .ctrlbit        = (1<<  19),
>>         }, {
>> -               .name           = "hsmmc",
>> -               .devname        = "exynos4-sdhci.0",
>> +               .name           = "biu",
>
>
> I have no idea why we change the clock name to 'biu' (bus interface unit).
> Just let me know.

The dw-mmc controller requires two clocks - bus interface unit and
card interface unit clock. Since this controller driver can be used on
platforms other than exynos, the name of the clock has to be generic.
Hence the name of the clocks used are "biu" and "ciu" as the per the
dw-mmc data sheet.

>
> [...]
>
>
>>   static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
>>         .clk    = {
>> -               .name           = "sclk_mmc",
>> -               .devname        = "exynos4-sdhci.0",
>> +               .name           = "ciu",
>
>
> Same as above.

Thanks,
Thomas.


From thomas.abraham at linaro.org  Tue Aug 28 01:02:11 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 10:32:11 +0530
Subject: [PATCH v3 2/3] ARM: Exynos5: Add AUXDATA support for MSHC
 controllers
In-Reply-To: <503BFEA4.1070601@samsung.com>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-3-git-send-email-thomas.abraham@linaro.org>
 <503BFEA4.1070601@samsung.com>
Message-ID: <CAJuYYwSxro48mY4jZj7ZJhW+4ncDCe=id17PdFOf7ypRGcuKmQ@mail.gmail.com>

On 28 August 2012 04:41, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add entries if MSHC controllers in AUXDATA table for correct device name
>> initialization.
>>
>> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>> ---
>>   arch/arm/mach-exynos/include/mach/map.h |    1 +
>>   arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
>>   2 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h
>> b/arch/arm/mach-exynos/include/mach/map.h
>> index 9d1f3ac..5b0ee41 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -172,6 +172,7 @@
>>
>>   #define EXYNOS4_PA_HSMMC(x)           (0x12510000 + ((x) * 0x10000))
>>   #define EXYNOS4_PA_DWMCI              0x12550000
>> +#define EXYNOS5_PA_DWMCI(x)            (0x12200000 + ((x) * 0x10000))
>
>
> Just, how about EXYNOS5_PA_DWMMC0, EXYNOS5_PA_DWMMC1, ... EXYNOS_PA_DWMMC3?

Ok.

>
> And if the addresses are different on other EXYNOS5 SoC, how do we handle it
> for auxdata?

I hope that does not happen. So do you suggest that I change this to
EYNOS5250_PA_DWMMC0 ?

>
>
>>
>>   #define EXYNOS4_PA_HSOTG              0x12480000
>>   #define EXYNOS4_PA_USB_HSPHY          0x125B0000
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> index ef770bc..4257cc1 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -47,6 +47,14 @@ static const struct of_dev_auxdata
>> exynos5250_auxdata_lookup[] __initconst = {
>>                                 "s3c2440-i2c.0", NULL),
>>         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
>>                                 "s3c2440-i2c.1", NULL),
>> +       OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI(0),
>
>
> As I commented, how about just 'samsung,dw-mmc'? but I'm not sure.

The dw-mmc controllers on Exynos 4210/4412/5250 have incremental
features. So different compatible strings are required to identify the
type of the controller.

Thanks for reviewing this patch series.

Regards,
Thomas.


From thomas.abraham at linaro.org  Tue Aug 28 01:06:45 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 10:36:45 +0530
Subject: [PATCH v3 3/3] ARM: dts: Add nodes for dw_mmc controllers for
 Samsung Exynos5250 platforms
In-Reply-To: <503BF8D3.9060507@samsung.com>
References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org>
 <1345982371-26483-4-git-send-email-thomas.abraham@linaro.org>
 <503BF8D3.9060507@samsung.com>
Message-ID: <CAJuYYwTHXbWLchv-426hZjkqP9-eS_hg10G4CJuKox96Q2JQXQ@mail.gmail.com>

On 28 August 2012 04:16, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/26/12 04:59, Thomas Abraham wrote:
>>
>> Add device nodes for the four instances of dw_mmc controllers in
>> Exynos5250
>> and enable instance 0 and 2 for the smdk5250 board.
>>
>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>> ---
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts |   57
>> ++++++++++++++++++++++++++++-
>>   arch/arm/boot/dts/exynos5250.dtsi         |   32 ++++++++++++++++
>>   2 files changed, 88 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index 8a5e348..6dc9faf 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -16,12 +16,19 @@
>>         model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
>>         compatible = "samsung,smdk5250", "samsung,exynos5250";
>>
>> +       aliases {
>> +               mshc0 =&mshc_0;
>> +               mshc1 =&mshc_1;
>> +               mshc2 =&mshc_2;
>> +               mshc3 =&mshc_3;
>> +       };
>> +
>>         memory {
>>                 reg =<0x40000000 0x80000000>;
>>         };
>>
>>         chosen {
>> -               bootargs = "root=/dev/ram0 rw ramdisk=8192
>> console=ttySAC1,115200";
>> +               bootargs = "root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
>
>
> Yes, we need to sort out the 'bootargs' for using uart2 as a console, but
> you know, this should be separated :-)
>

Sorry, that was never intended to be in this patch. My mistake.

>
>>         };
>>
>>         i2c at 12C60000 {
>> @@ -72,6 +79,54 @@
>>                 status = "disabled";
>>         };
>>
>> +       mshc_0: dwmmc0 at 12200000 {
>
>
> How about to keep the consistent naming? dwmmc or dw_mmc? I think, 'dw_mmc'
> makes more sense?

Ok.

>
>
>> +               num-slots =<1>;
>> +               supports-highspeed;
>> +               broken-cd;
>> +               fifo-depth =<0x80>;
>> +               card-detect-delay =<200>;
>> +               samsung,dw-mshc-sdr-timing =<2 3 3>;
>> +               samsung,dw-mshc-ddr-timing =<1 2 3>;
>
>
> We need to think again the name of dw-mshc-sdr-timing, dw-mshc-ddr-timing?

Synopsis calls this controller "Mobile Storage Host Controller (MSHC)"
in their online data sheets. Hence, all the bindings (which are used
on non-samsung platforms as well) follow the this name. For any
Samsung specific code for this controller, we are free to choose any
name.

>
> [...]
>
>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index 004aaa8..f69e389 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -182,6 +182,38 @@
>>                 #size-cells =<0>;
>>         };
>>
>> +       dwmmc0 at 12200000 {
>> +               compatible = "samsung,exynos5250-dw-mshc";
>
>
> I'm not sure, 'exynos5250-dw-mshc' is right here. Because it is just dw_mmc
> controller on exynos5250. So...hmm...

There are differences in the implementation of the dw-mmc controller
in Exynos SoC's. So it has to be exynos5250-dw-mshc.

Thanks,
Thomas.


From hdoyu at nvidia.com  Tue Aug 28 01:13:00 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 08:13:00 +0300
Subject: [v4 0/4] ARM: dma-mapping: IOMMU atomic allocation
Message-ID: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>

Hi,

The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
region" breaks the compatibility with existing drivers. This causes
the following kernel oops(*1). That driver has called dma_pool_alloc()
to allocate memory from the interrupt context, and it hits
BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
fixes this problem with making use of the pre-allocate atomic memory
pool which DMA is using in the same way as DMA does now.

Any comment would be really appreciated.

v4:
Fix plain memory allocation. (Konrad,Marek)
Print nicer error message at __in_atomic_pool() (Konrad)
v3:
Provide a different path for IOMMU for more clean code. (Marek)
atomic_pool is backed with struct page *pages[].
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002446.html
v2:
Don't modify attrs(DMA_ATTR_NO_KERNEL_MAPPING) for atomic allocation. (Marek)
Modify vzalloc (KyongHo,Minchan)
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002430.html
v1:
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-August/002398.html

*1:
[    8.321343] ------------[ cut here ]------------
[    8.325971] kernel BUG at kernel/mm/vmalloc.c:1322!
[    8.333615] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[    8.339436] Modules linked in:
[    8.342496] CPU: 0    Tainted: G        W     (3.4.6-00067-g5d485f7 #67)
[    8.349192] PC is at __get_vm_area_node.isra.29+0x164/0x16c
[    8.354758] LR is at get_vm_area_caller+0x4c/0x54
[    8.359454] pc : [<c011297c>]    lr : [<c011318c>]    psr: 20000193
[    8.359458] sp : c09edca0  ip : c09ec000  fp : ae278000
[    8.370922] r10: f0000000  r9 : c011aa54  r8 : c0a26cb8
[    8.376136] r7 : 00000001  r6 : 000000d0  r5 : 20000008  r4 : c09edca0
[    8.382651] r3 : 00010000  r2 : 20000008  r1 : 00000001  r0 : 00001000
[    8.389166] Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[    8.396549] Control: 10c5387d  Table: ad98c04a  DAC: 00000015
....
[    9.169162] dfa0: 412fc099 c09ec000 00000000 c000fdd8 c06df1e4 c0a1b080 00000000 00000000
[    9.177329] dfc0: c0a235cc 8000406a 00000000 c0986818 ffffffff ffffffff c0986404 00000000
[    9.185497] dfe0: 00000000 c09bb070 10c5387d c0a19c58 c09bb064 80008044 00000000 00000000
[    9.193673] [<c011297c>] (__get_vm_area_node.isra.29+0x164/0x16c) from [<c011318c>] (get_vm_area_caller+0x4c/0x54)
[    9.204022] [<c011318c>] (get_vm_area_caller+0x4c/0x54) from [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc)
[    9.214276] [<c001aed8>] (__iommu_alloc_remap.isra.14+0x2c/0xfc) from [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8)
[    9.224795] [<c001b06c>] (arm_iommu_alloc_attrs+0xc4/0xf8) from [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8)
[    9.235309] [<c011aa54>] (pool_alloc_page.constprop.5+0x6c/0xf8) from [<c011ab60>] (dma_pool_alloc+0x80/0x170)
[    9.245304] [<c011ab60>] (dma_pool_alloc+0x80/0x170) from [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c)
[    9.254344] [<c03cbbcc>] (tegra_build_dtd+0x48/0x14c) from [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8)
[    9.263467] [<c03cbd4c>] (tegra_req_to_dtd+0x7c/0xa8) from [<c03cc140>] (tegra_ep_queue+0x154/0x33c)
[    9.272592] [<c03cc140>] (tegra_ep_queue+0x154/0x33c) from [<c03dd5b4>] (composite_setup+0x364/0x6d4)
[    9.281804] [<c03dd5b4>] (composite_setup+0x364/0x6d4) from [<c03dd9dc>] (android_setup+0xb8/0x14c)
[    9.290843] [<c03dd9dc>] (android_setup+0xb8/0x14c) from [<c03cd144>] (setup_received_irq+0xbc/0x270)
[    9.300053] [<c03cd144>] (setup_received_irq+0xbc/0x270) from [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4)
[    9.309353] [<c03cda64>] (tegra_udc_irq+0x2ac/0x2c4) from [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0)
[    9.319087] [<c00b5708>] (handle_irq_event_percpu+0x78/0x2e0) from [<c00b59b4>] (handle_irq_event+0x44/0x64)
[    9.328907] [<c00b59b4>] (handle_irq_event+0x44/0x64) from [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c)
[    9.338294] [<c00b8688>] (handle_fasteoi_irq+0xc4/0x16c) from [<c00b4f14>] (generic_handle_irq+0x34/0x48)
[    9.347858] [<c00b4f14>] (generic_handle_irq+0x34/0x48) from [<c000f6f4>] (handle_IRQ+0x54/0xb4)
[    9.356637] [<c000f6f4>] (handle_IRQ+0x54/0xb4) from [<c00084b0>] (gic_handle_irq+0x2c/0x60)
[    9.365068] [<c00084b0>] (gic_handle_irq+0x2c/0x60) from [<c000e900>] (__irq_svc+0x40/0x70)
[    9.373405] Exception stack(0xc09edf10 to 0xc09edf58)
[    9.378447] df00:                                     00000000 000f4240 00000003 00000000
[    9.386615] df20: 00000000 e55bbc00 ef66f3ca 00000001 00000000 412fc099 c0abb9c8 00000000
[    9.394781] df40: 3b9ac9ff c09edf58 c027a9bc c0042880 20000113 ffffffff
[    9.401396] [<c000e900>] (__irq_svc+0x40/0x70) from [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78)
[    9.410272] [<c0042880>] (tegra_idle_enter_lp3+0x68/0x78) from [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4)
[    9.419922] [<c04701d4>] (cpuidle_idle_call+0xdc/0x3a4) from [<c000fdd8>] (cpu_idle+0xd8/0x134)
[    9.428612] [<c000fdd8>] (cpu_idle+0xd8/0x134) from [<c0986818>] (start_kernel+0x27c/0x2cc)
[    9.436952] Code: e1a00004 e3a04000 eb002265 eaffffe0 (e7f001f2)
[    9.443038] ---[ end trace 1b75b31a2719ed24 ]---
[    9.447645] Kernel panic - not syncing: Fatal exception in interrupt

Hiroshi Doyu (4):
  ARM: dma-mapping: atomic_pool with struct page **pages
  ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
  ARM: dma-mapping: Introduce __atomic_get_pages() for
    __iommu_get_pages()
  ARM: dma-mapping: IOMMU allocates pages from atomic_pool with
    GFP_ATOMIC

 arch/arm/mm/dma-mapping.c |   91 ++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 82 insertions(+), 9 deletions(-)

-- 
1.7.5.4



From thomas.abraham at linaro.org  Tue Aug 28 01:25:52 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 10:55:52 +0530
Subject: [PATCH v2 1/4] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <CACRpkdbVY1mmzb9H4ZfmVScW1ZNf1FTMLdgo5UFgqTftycMyrQ@mail.gmail.com>
References: <1345060656-32201-1-git-send-email-thomas.abraham@linaro.org>
 <1345060656-32201-2-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYqPYesgE-YxPLZqROw1T2fsPWR6R+aDTTz2=XbP7oe9A@mail.gmail.com>
 <CAJuYYwQu7OXQEWCumuMeSKJ2RZD7e==pLKDE1=bvPgfXtO=AUw@mail.gmail.com>
 <CACRpkdbVY1mmzb9H4ZfmVScW1ZNf1FTMLdgo5UFgqTftycMyrQ@mail.gmail.com>
Message-ID: <CAJuYYwRRQ-kd3ABrK82x2onFRFvHYnbVznuSssW_hXYhncDNWg@mail.gmail.com>

On 28 August 2012 04:52, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Tue, Aug 21, 2012 at 9:22 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:

[...]

>>>> +/* list of all possible config options supported */
>>>> +struct pin_config {
>>>> +       char            *prop_cfg;
>>>> +       unsigned int    cfg_type;
>>>> +} pcfgs[] = {
>>>> +       { "samsung,pin-pud", PINCFG_TYPE_PUD },
>>>> +       { "samsung,pin-drv", PINCFG_TYPE_DRV },
>>>> +       { "samsung,pin-pud-pdn", PINCFG_TYPE_CON_PND },
>>>> +       { "samsung,pin-drv-pdn", PINCFG_TYPE_PUD_PND },
>>>> +};
>>>
>>> Hmmmmm it looks very much like this controller could make use of
>>> the generic pinconf library, but it's not mandatory so just a suggestion.
>>
>> Ok. The last two entries in the above table are Samsung specific and
>> not covered by generic-pinconf. So, I am not sure if it can be added
>> to generic-pinconf.
>
> What is so Samsung-specific about them?
>
> If you tell us the electrical property of setting them we can figure out
> if they should be generic or not...
>

The PINCFG_TYPE_CON_PND and PINCFG_TYPE_PUD_PND are "mux function" and
"pull up/down" settings that are automatically applied to the pin in
powert-down mode. It is same as the usual "mux function" and "pull
up/down" settings, but just that it is applied at suspend.

[...]

>
> OK whatever... looking formward to next iteration!

I have posted the updated version of this patch series based on your
comments (https://lkml.org/lkml/2012/8/23/183).

The only pending comment to be addressed at this point is about the
use of generic-pinconf as mentioned in the comment above. If
PINCFG_TYPE_CON_PND and PINCFG_TYPE_PUD_PND is available in
generic-pinconf, I wil switch to using generic-pinconf. Will that
qualify this Samsung pinctrl driver to be merged into your -devel
branch?

Thanks,
Thomas.


From anilkumar at ti.com  Tue Aug 28 01:34:02 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Tue, 28 Aug 2012 05:34:02 +0000
Subject: [PATCH v3 4/4] arm/dts: Add tps65217 regulator DT data to
 am335x-bone.dts
In-Reply-To: <45D5714B-BB2C-49BB-8C5D-F69749EC324A@dominion.thruhere.net>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <1345547850-29761-5-git-send-email-anilkumar@ti.com>
 <A823657F-0D26-429F-8E1C-DF1AE5AB78F4@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F1D7@DBDE01.ent.ti.com>
 <583C0877-1C4C-46B6-A5D0-BDD34D6BB7C8@dominion.thruhere.net>
 <331ABD5ECB02734CA317220B2BBEABC13EA1F3B0@DBDE01.ent.ti.com>
 <6C2AC14D-1CAC-4B93-910C-B7E52D3355FD@dominion.thruhere.net>
 <45D5714B-BB2C-49BB-8C5D-F69749EC324A@dominion.thruhere.net>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA20AA6@DBDE01.ent.ti.com>

Hi Koen,

On Fri, Aug 24, 2012 at 13:32:17, Koen Kooi wrote:
> 
> Op 24 aug. 2012, om 09:56 heeft Koen Kooi <koen at dominion.thruhere.net> het volgende geschreven:
> 
> > 
> > Op 24 aug. 2012, om 09:26 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
> > 
> >> Hi Koen,
> >> 
> >> On Fri, Aug 24, 2012 at 11:58:34, Koen Kooi wrote:
> >>> 
> >>> Op 24 aug. 2012, om 07:50 heeft "AnilKumar, Chimata" <anilkumar at ti.com> het volgende geschreven:
> >>> 
> >>>> Hi Koen,
> >>>> 
> >>>> On Thu, Aug 23, 2012 at 19:43:48, Koen Kooi wrote:
> >>>>> 
> >>>>> Op 21 aug. 2012, om 13:17 heeft AnilKumar Ch <anilkumar at ti.com> het volgende geschreven:
> >>>>> 
> >>>>>> Add tps65217 regulator device tree data to AM335x-Bone by adding
> >>>>>> regulator consumers with tightened constraints and regulator-name.
> >>>>>> TPS65217 regulator handle can be obtained by using this regulator
> >>>>>> name.
> >>>>>> 
> >>>>>> This patch also add I2C node with I2C frequency and tps65217 PMIC
> >>>>>> I2C slave address.
> >>>>>> 
> >>>>>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> >>>>> 
> >>>>> I tried this and the kernel immediately crashes on my beaglebone. Could you upload the complete git tree and .config you used to test this to somewhere public please?
> >>>> 
> >>>> Use this repo to test on beaglebone
> >>>> https://github.com/hvaibhav/am335x-linux/commits/am335x-upstream-staging-pinctrl
> >>>> 
> >>>> This wiki talks about how to build and use?
> >>>> https://github.com/hvaibhav/am335x-linux/wiki/How-To-Use-Upstream-Tree
> >>>> 
> >>>> Note: Enable tps65217 regulator in kernel config.
> >>> 
> >>> I used that repo and as a seperate test I rebased that to latest mainline, same thing: as soon as I turn on the TPS in the .config it crashes on boot. Is the pinctrl repo the *exact* repo you used to test the patches on beaglebone?
> >> 
> >> I tested on latest mainline after merging to
> >> am335x-upstream-staging-pinctrl (voltage also changing)
> >> 
> >> Can you share your .config and uImage?
> > 
> > Config: https://github.com/beagleboard/kernel/blob/beaglebone-3.6/patches/configs/beaglebone
> > 
> >> My config details:- (After merge)
> >> 1. omap2plus_defconfig
> >> 2. Enable tps65217 MFD driver
> >> 3. Enable tps65217 regulator driver
> > 
> > 
> > I rebased onto latest mainline and refreshed the base patches from Vaibhav and I now get: 
> > 
> > [    0.246796] tps65217 0-0024: TPS65217 ID 0xf version 1.1
> > 
> > So it boots! I don't know what made it break before, but it's working now :)
> 
> *sigh* I'm an idiot:
> 
> root at beaglebone:~# uname -a
> Linux beaglebone 3.6.0-rc3-00103-gfd02083 #86 SMP Fri Aug 24 09:45:54 CEST 2012 armv7l GNU/Linux
> root at beaglebone:~# zcat /proc/config.gz | grep 217
> CONFIG_MFD_TPS65217=y
> # CONFIG_REGULATOR_TPS65217 is not set
> 
> Will retry with regulator driver actually turned on in a bit.

Is it working after enabling the regulator?

Thanks
AnilKumar


From b29396 at freescale.com  Tue Aug 28 01:33:37 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 13:33:37 +0800
Subject: [PATCH v2 5/7] ARM: imx6q: convert to use syscon to access
 anatop registers
In-Reply-To: <20120828032309.GW4011@b20223-02.ap.freescale.net>
References: <1346052285-4344-1-git-send-email-b29396@freescale.com>
 <1346052285-4344-6-git-send-email-b29396@freescale.com>
 <20120828032309.GW4011@b20223-02.ap.freescale.net>
Message-ID: <20120828053336.GF5822@shlinux2.ap.freescale.net>

On Tue, Aug 28, 2012 at 11:23:10AM +0800, Zhao Richard-B20223 wrote:
...
> >  	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
> np unused.

Correct.
Will drop it.

Regards
Dong Aisheng



From dirk.behme at de.bosch.com  Tue Aug 28 02:03:18 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Tue, 28 Aug 2012 08:03:18 +0200
Subject: [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP
In-Reply-To: <20120827233756.GH2281@r65073-Latitude-D630>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <20120827223134.GD2281@r65073-Latitude-D630>
 <20120827225142.GA11302@kroah.com>
 <20120827233756.GH2281@r65073-Latitude-D630>
Message-ID: <503C5F26.4020108@de.bosch.com>

On 28.08.2012 01:37, Shawn Guo wrote:
> On Mon, Aug 27, 2012 at 03:51:42PM -0700, Greg Kroah-Hartman wrote:
>> On both of them?  I can do that if needed.  How far back should they go?
>>
> It should be okay to apply on 3.4 and 3.5. 

For patch #1/2: Yes, thanks!

> But patch #2 is still in
> question.  I do not like the #ifdef.

For patch #2/2: Yes, understood. I'll look at Troy's proposal and will 
update #2/2.

Many thanks and best regards

Dirk


From wni at nvidia.com  Tue Aug 28 02:08:29 2012
From: wni at nvidia.com (Wei Ni)
Date: Tue, 28 Aug 2012 14:08:29 +0800
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly
 for non-OOB
In-Reply-To: <503B9F31.5050502@broadcom.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com>
Message-ID: <1346134109.3516.39.camel@tegra-chromium-2>

On Tue, 2012-08-28 at 00:24 +0800, Arend van Spriel wrote:
> On 08/27/2012 12:25 PM, Wei Ni wrote:
> > In case of inband interrupts, if we handle the interrupt in dpc thread,
> > two level of thread switching takes place to process wifi interrupts.
> > One in SDHCI driver and the other in Wifi driver. This may cause the system
> > instability.
> 
> Looking into the sdhci/mmc code indeed shows that the brcmfmac irq 
> handler is not called in true IRQ context. So the dpc thread may add 
> unnecessary complexity, but to me there is not indication that there is 
> a stability issue.
> 
> > Because the SDHCI calls sdio_irq_thread() to handle the irq, this thread locks
> > mmc host and calls wifi handler. It expects WiFi handler to be quick and
> > enables sdio interrupt from card at end. If wifi handler defers this work for
> > a different thread, sdio_irq_thread() will be stuck on next wifi interrupt
> > since mmc lock is not freed.
> 
> Not sure if I can follow this explanation. The isr is called with host 
> claimed (by sdio_irq_thread) and all it does is at a linked list member 
> and signal the dpc thread. After doing this the host is released.
> 
> > Handling the interrupt in ISR directly will prevent thread context switching in
> > wifi driver. It can fix the instability problems.
> 
> This basically increases the duration of the isr in brcmfmac.
> 
> > Signed-off-by: Wei Ni <wni at nvidia.com>
> > ---
> >   drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c   |    2 ++
> >   drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c |    8 +++++++-
> >   2 files changed, 9 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> > index 8e7e692..5cf6c3b 100644
> > --- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> > +++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
> > @@ -121,7 +121,9 @@ static void brcmf_sdio_irqhandler(struct sdio_func *func)
> >
> >   	brcmf_dbg(INTR, "ib intr triggered\n");
> >
> > +	sdio_release_host(sdiodev->func[1]);
> >   	brcmf_sdbrcm_isr(sdiodev->bus);
> > +	sdio_claim_host(sdiodev->func[1]);
> 
> This is probably needed because the ISR now locks the host to long 
> because brcmf_sdbrcm_dpc() is called directly.
> 
> >   }
> >
> >   /* dummy handler for SDIO function 2 interrupt */
> > diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> > index 472f2ef..4576d59 100644
> > --- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> > +++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
> > @@ -2347,7 +2347,7 @@ static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
> >   	uint framecnt = 0;	/* Temporary counter of tx/rx frames */
> >   	bool rxdone = true;	/* Flag for no more read data */
> >   	bool resched = false;	/* Flag indicating resched wanted */
> > -	int err;
> > +	int err = 0;
> >
> >   	brcmf_dbg(TRACE, "Enter\n");
> >
> > @@ -3786,11 +3786,17 @@ void brcmf_sdbrcm_isr(void *arg)
> >   	if (!bus->intr)
> >   		brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
> >
> > +
> > +#ifndef CONFIG_BRCMFMAC_SDIO_OOB
> > +	while (brcmf_sdbrcm_dpc(bus))
> > +		;
> > +#else
> >   	bus->dpc_sched = true;
> >   	if (bus->dpc_tsk) {
> >   		brcmf_sdbrcm_adddpctsk(bus);
> >   		complete(&bus->dpc_wait);
> >   	}
> > +#endif
> >   }
> >
> >   static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
> >
> 
> I would really like to know what issue is solved by this change. Could 
> you provide more details.

If without this fix, the system is instability, we observed interrupt
from Wi-Fi cards pilling up in the system. We observed following issue
because of this:
1. Device is slow while downloading file through WiFi
2. WiFi performance is bad
3. WiFi does not turn on single CPU
4. Sometimes it will show following spew from kernel, and system will
hang up, it was caused by the semaphore which didn't be released.

INFO: task brcmf_watchdog:248 blocked for more than 120 seconds.
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this
message.
brcmf_watchdog  D c041aeac     0   248      2 0x00000000
[<c041aeac>] (__schedule+0x3c4/0x6d0) from [<c0418fe0>]
(schedule_timeout+0x1b0/0x218)
[<c0418fe0>] (schedule_timeout+0x1b0/0x218) from [<c041a748>] (__down
+0x68/0x98)
[<c041a748>] (__down+0x68/0x98) from [<c004c13c>] (down+0x44/0x4c)
[<c004c13c>] (down+0x44/0x4c) from [<bf017210>]
(brcmf_sdbrcm_bus_watchdog+0x28/0x1d0 [brcmfmac])
[<bf017210>] (brcmf_sdbrcm_bus_watchdog+0x28/0x1d0 [brcmfmac]) from
[<bf0173e4>] (brcmf_sdbrcm_watchdog_thread+0x2c/0x50 [brcmfmac])
[<bf0173e4>] (brcmf_sdbrcm_watchdog_thread+0x2c/0x50 [brcmfmac]) from
[<c0046328>] (kthread+0x8c/0x98)
[<c0046328>] (kthread+0x8c/0x98) from [<c000f5e4>] (kernel_thread_exit
+0x0/0x8)

After add this fix, everything looks ok.

I noticed that in the old version driver, it also has this fix, but
removed in http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-
2.6.git;a=commit;h=b61c23c846978a4381fdc499055bd66b7bd24120

Thanks.
Wei.

> 
> Franky,
> 
> Do you have anything to add here?
> 
> Gr. AvS
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html




From 21cnbao at gmail.com  Tue Aug 28 02:15:26 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 Aug 2012 14:15:26 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <201208210920.52816.arnd@arndb.de>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210757.32852.arnd@arndb.de>
 <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
 <201208210920.52816.arnd@arndb.de>
Message-ID: <CAGsJ_4x4DdHsNgh7ArkD1fCHT22rxRs18vcobHtpSXJ-cq3o4Q@mail.gmail.com>

2012/8/21 Arnd Bergmann <arnd at arndb.de>:
> On Tuesday 21 August 2012, Barry Song wrote:
>> then i add these to Kconfig.debug as it is a common way
>>
>>         config DEBUG_PRIMA2_UART1
>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
>>                 depends on ARCH_PRIMA2
>>                 help
>>                   Say Y here if you want the debug print routines to direct
>>                   their output to UART1 serial port on SiRFprimaII devices.
>>
>>         config DEBUG_MARCO_UART1
>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
>>                 depends on ARCH_MARCO
>>                 help
>>                   Say Y here if you want the debug print routines to direct
>>                   their output to UART1 serial port on SiRFmarco devices.
>>
>> and these in mach-prima2/include/mach/uart.h
>>
>>   #ifdef CONFIG_DEBUG_PRIMA2_UART1
>>   #define SIRFSOC_UART1_PA_BASE          0xb0060000
>>   #elif defined(CONFIG_DEBUG_MARCO_UART1)
>>   #define SIRFSOC_UART1_PA_BASE          0xcc060000
>>   #endif
>>
>> the above codes seem still ugly ?
>>
>
> No, that's fine, about as a good as it gets with today's kernel
> capabilities. Just fix the description to have the correct
> SoC name instead of "DaVinci DA8XX" ;-)

except the DEBUG_LL uart base address, i missed the zreladdr-y. for
primaii, it is 0x00008000, for marco, it is 0x40008000 as marco's
memory space begins from 0x4000000.
i would to have AUTO_ZRELADDR for the whole SiRF series.
but for uImage load address difference in uImage header, which blocks
multiple SoCs from using same uImage, is "KERNEL_NOLOAD" uImage type
the current generic solution?

>
>         Arnd

-barry


From hvaibhav at ti.com  Tue Aug 28 02:21:32 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Tue, 28 Aug 2012 11:51:32 +0530
Subject: [PATCH v3 3/4] arm/dts: AM33XX: Configure pinmuxs for D_CAN1
 on AM335x-EVM
In-Reply-To: <20120824201447.GY11011@atomide.com>
References: <1345119610-5247-1-git-send-email-anilkumar@ti.com>
 <1345119610-5247-4-git-send-email-anilkumar@ti.com>
 <20120824201447.GY11011@atomide.com>
Message-ID: <503C636C.6080708@ti.com>



On 8/25/2012 1:44 AM, Tony Lindgren wrote:
> * AnilKumar Ch <anilkumar at ti.com> [120816 05:20]:
>> Add D_CAN1 pinctrl node to am3358_pinmux master node to export
>> D_CAN functionality on AM335x EVM according to pinctrl-single
>> driver.
>>
>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>> ---
>> Changes from v2:
>> 	- Incorporated Vaibhav H's comments on v2
>> 	  * Added dcan0 instances to am33xx.dtsi file
>>
>> Changes from v1:
>> 	- These two patches separated from c_can DT support
>> 	  patch series.
>>
>>  arch/arm/boot/dts/am335x-evm.dts |   12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
>> index 5dd8a6b..a64c30a 100644
>> --- a/arch/arm/boot/dts/am335x-evm.dts
>> +++ b/arch/arm/boot/dts/am335x-evm.dts
>> @@ -18,6 +18,18 @@
>>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>>  	};
>>  
>> +	am3358_pinmux: pinmux at 44E10800 {
> 
> This should be just &am3358_pinmux as you already include it.
> 

I think it won't work this way, it will result into syntax error.
The reason being is, unlike OMAP (and like other platforms, like, imx)
here we are again representing device hierarchy starting from root,

am335x-evm.dts:
/ {

	ocp {
		...
	};

};

Although I am not too familiar with DTS compiler, but below code results
in syntax error:

am335x-evm.dts:
/ {

	ocp {
		...
		&am3358_pinmux {
			...
		};
	};

};


Thanks,
Vaibhav

>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&d_can1_pins>;
>> +
>> +		d_can1_pins: pinmux_d_can_pins {
>> +			pinctrl-single,pins = <
>> +				0x168 0x2	/* uart0_ctsn.d_can1_tx, OUTPUT | MODE2 */
>> +				0x16C 0x32	/* uart0_rtsn.d_can1_rx, INPUT_PULLUP | MODE2 */
>> +			>;
>> +		};
>> +	};
>> +
> 
> It would better to claim these pins in the dcan driver entry
> rather than set them as pins enabled by the pinctrl driver.
> The reason is that in case you want to enable runtime PM related
> stuff, like some more advanced wake-up features, for the rx pin
> you can do it in the driver.
> 
> Then one nit.. Please lowercase all hex number in this series as that's the style
> here.
> 
> Regards,
> 
> Tony
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 


From rnayak at ti.com  Tue Aug 28 02:21:52 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 28 Aug 2012 11:51:52 +0530
Subject: [PATCH 2/2] arm/dts: Cleanup regulator naming and remove @0,1..
In-Reply-To: <20120824202725.GA1303@atomide.com>
References: <1343653940-16614-1-git-send-email-rnayak@ti.com>
 <1343653940-16614-3-git-send-email-rnayak@ti.com>
 <20120824202725.GA1303@atomide.com>
Message-ID: <503C6380.4090107@ti.com>

Hi Tony,

> * Rajendra Nayak<rnayak at ti.com>  [120730 06:17]:
>> regulators do not have a 'reg' property, hence the regulator at 0,
>> regulator at 1 do not make sense. get rid of it.
>
> Looks like this needs to be refreshed to apply. Care to
> refresh against current devel-dt branch in case other
> places need the same change?

Looks like devel-dt is missing the PATCH 1/2 from this series,
which you have already pushed in the -rc for merge.
With that applied, this ones applies cleanly too.

regards,
Rajendra

>
> Regards,
>
> Tony



From s.hauer at pengutronix.de  Tue Aug 28 02:39:19 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 08:39:19 +0200
Subject: [PATCH v2 0/2] imx6q: pwm: Activate stop_mode and configure pinmux
In-Reply-To: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFC@frontmail.adetel.com>
References: <3465D313FDFB824F9A9C8CD24FA4F6BCB4ACFC@frontmail.adetel.com>
Message-ID: <20120828063919.GN26594@pengutronix.de>

Hi,

On Mon, Aug 27, 2012 at 05:34:30PM +0200, HACHIMI Samir wrote:
> From: Samir Hachimi <shachimi at adeneo-embedded.com>
> 
> This patch series enables support for pwm driver on imx6q SoC. The first
> patch of the series configure the pinctrl for pwm in device-tree. Actually
> they are several pin who can be set to pwmO for each pwm, so I assume that
> all of them must be enabled when configuring pin.
> The second patch activate stop_enable mode and unset the enable bit during
> configuration of pwm, and set the enable bit in pwm CR register during enable.
> 
> Changes since v1:
> Remove default pwm pinmux configuration in DT as Shawn and Matt suggested.
> Now, pwm used pwm's clocks properties to configure pwm's clock.
> Need Shawn's patch '[PATCH v2 0/4] Move imx6q/28/23 clock lookup over to device tree' to work.
> Use Beno??t's '[PATCH] pwm-imx: Fix config / enable / disable' (un)setting the cr enable bit to enable/disable pwm.
> The second patch used driver_data instead of cpu_is_xxx macros, to check used architecture and enabled stop_enable mode.
> 

Before doing anything else to this driver I suggest the following patch.
It makes further changes and cleanups easier.

Also, I have a second patch here which consistently switches the pwm to
use the ipg clock for its output instead of the per clock. This
eliminates the use of another cpu_is_*. The patch is not ready though
because I read some thread about the clock being disabled during
pwm_config.

Sascha

8<-------------------------------------------------------------------

pwm i.MX: factor out cpu specific functions

To make the code more flexible.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |  145 ++++++++++++++++++++++++++++---------------------
 1 file changed, 82 insertions(+), 63 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..38270f4 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -46,81 +46,95 @@ struct imx_chip {
 	void __iomem	*mmio_base;
 
 	struct pwm_chip	chip;
+
+	int (*config)(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns);
 };
 
 #define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
 
-static int imx_pwm_config(struct pwm_chip *chip,
+static int imx_pwm_config_v1(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
 
-	if (!(cpu_is_mx1() || cpu_is_mx21())) {
-		unsigned long long c;
-		unsigned long period_cycles, duty_cycles, prescale;
-		u32 cr;
-
-		c = clk_get_rate(imx->clk);
-		c = c * period_ns;
-		do_div(c, 1000000000);
-		period_cycles = c;
-
-		prescale = period_cycles / 0x10000 + 1;
-
-		period_cycles /= prescale;
-		c = (unsigned long long)period_cycles * duty_ns;
-		do_div(c, period_ns);
-		duty_cycles = c;
-
-		/*
-		 * according to imx pwm RM, the real period value should be
-		 * PERIOD value in PWMPR plus 2.
-		 */
-		if (period_cycles > 2)
-			period_cycles -= 2;
-		else
-			period_cycles = 0;
-
-		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
-		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
-
-		cr = MX3_PWMCR_PRESCALER(prescale) |
-			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
-
-		if (cpu_is_mx25())
-			cr |= MX3_PWMCR_CLKSRC_IPG;
-		else
-			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
-
-		writel(cr, imx->mmio_base + MX3_PWMCR);
-	} else if (cpu_is_mx1() || cpu_is_mx21()) {
-		/* The PWM subsystem allows for exact frequencies. However,
-		 * I cannot connect a scope on my device to the PWM line and
-		 * thus cannot provide the program the PWM controller
-		 * exactly. Instead, I'm relying on the fact that the
-		 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
-		 * function group already. So I'll just modify the PWM sample
-		 * register to follow the ratio of duty_ns vs. period_ns
-		 * accordingly.
-		 *
-		 * This is good enough for programming the brightness of
-		 * the LCD backlight.
-		 *
-		 * The real implementation would divide PERCLK[0] first by
-		 * both the prescaler (/1 .. /128) and then by CLKSEL
-		 * (/2 .. /16).
-		 */
-		u32 max = readl(imx->mmio_base + MX1_PWMP);
-		u32 p = max * duty_ns / period_ns;
-		writel(max - p, imx->mmio_base + MX1_PWMS);
-	} else {
-		BUG();
-	}
+	/* The PWM subsystem allows for exact frequencies. However,
+	 * I cannot connect a scope on my device to the PWM line and
+	 * thus cannot provide the program the PWM controller
+	 * exactly. Instead, I'm relying on the fact that the
+	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
+	 * function group already. So I'll just modify the PWM sample
+	 * register to follow the ratio of duty_ns vs. period_ns
+	 * accordingly.
+	 *
+	 * This is good enough for programming the brightness of
+	 * the LCD backlight.
+	 *
+	 * The real implementation would divide PERCLK[0] first by
+	 * both the prescaler (/1 .. /128) and then by CLKSEL
+	 * (/2 .. /16).
+	 */
+	u32 max = readl(imx->mmio_base + MX1_PWMP);
+	u32 p = max * duty_ns / period_ns;
+	writel(max - p, imx->mmio_base + MX1_PWMS);
+
+	return 0;
+}
+
+static int imx_pwm_config_v2(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+	unsigned long long c;
+	unsigned long period_cycles, duty_cycles, prescale;
+	u32 cr;
+
+	c = clk_get_rate(imx->clk);
+	c = c * period_ns;
+	do_div(c, 1000000000);
+	period_cycles = c;
+
+	prescale = period_cycles / 0x10000 + 1;
+
+	period_cycles /= prescale;
+	c = (unsigned long long)period_cycles * duty_ns;
+	do_div(c, period_ns);
+	duty_cycles = c;
+
+	/*
+	 * according to imx pwm RM, the real period value should be
+	 * PERIOD value in PWMPR plus 2.
+	 */
+	if (period_cycles > 2)
+		period_cycles -= 2;
+	else
+		period_cycles = 0;
+
+	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
+	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
+
+	cr = MX3_PWMCR_PRESCALER(prescale) |
+		MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+		MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
+
+	if (cpu_is_mx25())
+		cr |= MX3_PWMCR_CLKSRC_IPG;
+	else
+		cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
+
+	writel(cr, imx->mmio_base + MX3_PWMCR);
 
 	return 0;
 }
 
+static int imx_pwm_config(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+
+	return imx->config(chip, pwm, duty_ns, period_ns);
+}
+
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
@@ -187,6 +201,11 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	if (imx->mmio_base == NULL)
 		return -EADDRNOTAVAIL;
 
+	if (cpu_is_mx1() || cpu_is_mx21())
+		imx->config = imx_pwm_config_v1;
+	else
+		imx->config = imx_pwm_config_v2;
+
 	ret = pwmchip_add(&imx->chip);
 	if (ret < 0)
 		return ret;
-- 
1.7.10.4

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 02:43:53 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 08:43:53 +0200
Subject: [PATCH] ARM i.MX: remove duplicated include from clk-imx21.c
In-Reply-To: <CAPgLHd_pYM3otnZBZ=nz7aYTP4dorBSjQtj=x9Z+zz7yr1NgSg@mail.gmail.com>
References: <CAPgLHd_pYM3otnZBZ=nz7aYTP4dorBSjQtj=x9Z+zz7yr1NgSg@mail.gmail.com>
Message-ID: <20120828064353.GO26594@pengutronix.de>

On Sun, Aug 26, 2012 at 09:48:11AM +0800, Wei Yongjun wrote:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Applied, thanks

Sascha

> 
> Remove duplicated include.
> 
> Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> ---
>  arch/arm/mach-imx/clk-imx21.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
> index ea13e61..cf65148 100644
> --- a/arch/arm/mach-imx/clk-imx21.c
> +++ b/arch/arm/mach-imx/clk-imx21.c
> @@ -23,7 +23,6 @@
>  #include <linux/clk-provider.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> -#include <linux/clkdev.h>
>  #include <linux/err.h>
>  
>  #include <mach/hardware.h>
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 02:47:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 08:47:10 +0200
Subject: [PATCH] imx21ads : avoid overlapping static i/o mappings
In-Reply-To: <1346016938-28175-1-git-send-email-jaccon.bastiaansen@gmail.com>
References: <1346016938-28175-1-git-send-email-jaccon.bastiaansen@gmail.com>
Message-ID: <20120828064710.GP26594@pengutronix.de>

On Sun, Aug 26, 2012 at 11:35:38PM +0200, Jaccon Bastiaansen wrote:
> The static I/O mappings for the cs89x0 ethernet controller and the
> secondary AHB port 1 (SAHB1) overlapped, causing a kernel crash
> at startup. This is fixed by mapping the cs89x0 to 0xf6000000 (which
> is free to use according to arch/arm/plat-mxc/include/mach/hardware.h).
> 
> Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
> ---
>  arch/arm/mach-imx/mach-mx21ads.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
> index ed22e3f..712c90e 100644
> --- a/arch/arm/mach-imx/mach-mx21ads.c
> +++ b/arch/arm/mach-imx/mach-mx21ads.c
> @@ -31,7 +31,7 @@
>  /*
>   * Memory-mapped I/O on MX21ADS base board
>   */
> -#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
> +#define MX21ADS_MMIO_BASE_ADDR   0xf6000000

I would prefer to ioremap the region instead. This makes sure this
problem is solved once and for all.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From richard.genoud at gmail.com  Tue Aug 28 02:51:44 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 28 Aug 2012 08:51:44 +0200
Subject: [PATCH 05/14] ARM: at91: add pinctrl support
In-Reply-To: <CACRpkdYWXZLNdgMhqoMZsaaszZ5Uz9pZ1EO=mrnuY5Der4O+Mw@mail.gmail.com>
References: <20120810124820.GA20557@game.jcrosoft.org>
 <1344603731-32667-1-git-send-email-plagnioj@jcrosoft.com>
 <1344603731-32667-5-git-send-email-plagnioj@jcrosoft.com>
 <CACRpkdZ2__V06Eo8JH451Sup5Nw2jJXVOH2FOfZBp5nNYpCtbg@mail.gmail.com>
 <5034FC18.2090400@wwwdotorg.org>
 <CACQ1gAieByr5vMmyyCuGtS8AgnnRZPPhLZY8sKvwvcQYe5ieUA@mail.gmail.com>
 <50366D2B.4010807@wwwdotorg.org> <20120825083811.GB7629@game.jcrosoft.org>
 <CACRpkdYWXZLNdgMhqoMZsaaszZ5Uz9pZ1EO=mrnuY5Der4O+Mw@mail.gmail.com>
Message-ID: <CACQ1gAiFQAwn34mCYXWi9cTZPLRNiDVHT0qLNtJ4cgL51kRQBw@mail.gmail.com>

2012/8/28 Linus Walleij <linus.walleij at linaro.org>:
> I'm following it now I think, after some discussion here at the kernel summit
> I have come to the conclusion that the real problem with readability comes
> from a shortcoming in the device tree compiler, that it cannot handle
> macros and defines (no preprocessor) so it's currently hard to make
> it more readable.
Definitively, I've seen quite some hex (or dec) voodoo with comment
next to them like that:
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
linux,code = <102>; /* KEY_HOME */
linux,code = <158>; /* KEY_BACK */
fsl,pinmux-ids = <
		0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
		0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
		0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
		>;
Those bits of code are crying out "We want defines !"
(And even bitwise OR would be usefull, instead of having to choose
between hex voodoo and one bool for each bit in a register)

> But that's not the implementers fault so I'm OK with this looking like
> this for the moment.
>
> Yours,
> Linus Walleij

Best regards,
Richard.


From richard.zhao at freescale.com  Tue Aug 28 02:58:26 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 14:58:26 +0800
Subject: [PATCH v6 0/3] imx: add usbmisc support
Message-ID: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>

usbmisc driver handles the SoC specific non-core usb registers.

Changes since last version:
 goto err when usbmisc_ops->init failed rather than return directly.

Richard Zhao (3):
  USB: chipidea: add imx usbmisc support
  ARM: imx6q: clk_register_clkdev usbmisc clock
  ARM: dts: imx6q-sabrelite: add usbmisc device

 .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
 .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
 arch/arm/boot/dts/imx6q-sabrelite.dts              |    1 +
 arch/arm/boot/dts/imx6q.dtsi                       |   10 ++
 arch/arm/mach-imx/clk-imx6q.c                      |    1 +
 drivers/usb/chipidea/Makefile                      |    2 +-
 drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
 drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
 drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
 9 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
 create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
 create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c

-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 02:58:27 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 14:58:27 +0800
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>

i.MX usb controllers shares non-core registers, which may include
SoC specific controls. We take it as a usbmisc device and usbmisc
driver set operations needed by ci13xxx_imx driver.

For example, Sabrelite board has bad over-current design, we can
usbmisc to disable over-current detect.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
 .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
 drivers/usb/chipidea/Makefile                      |    2 +-
 drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
 drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
 drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
 6 files changed, 274 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
 create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
 create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c

diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
index 2c29041..5778b9c 100644
--- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
@@ -7,7 +7,10 @@ Required properties:
 
 Optional properties:
 - fsl,usbphy: phandler of usb phy that connects to the only one port
+- fsl,usbmisc: phandler of non-core register device, with one argument
+  that indicate usb controller index
 - vbus-supply: regulator for vbus
+- disable-over-current: disable over current detect
 
 Examples:
 usb at 02184000 { /* USB OTG */
@@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
 	reg = <0x02184000 0x200>;
 	interrupts = <0 43 0x04>;
 	fsl,usbphy = <&usbphy1>;
+	fsl,usbmisc = <&usbmisc 0>;
+	disable-over-current;
 };
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
new file mode 100644
index 0000000..97ce94e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
@@ -0,0 +1,14 @@
+* Freescale i.MX non-core registers
+
+Required properties:
+- #index-cells: Cells used to descibe usb controller index. Should be <1>
+- compatible: Should be one of below:
+	"fsl,imx6q-usbmisc" for imx6q
+- reg: Should contain registers location and length
+
+Examples:
+usbmisc at 02184800 {
+	#index-cells = <1>;
+	compatible = "fsl,imx6q-usbmisc";
+	reg = <0x02184800 0x200>;
+};
diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
index 5c66d9c..57e510f 100644
--- a/drivers/usb/chipidea/Makefile
+++ b/drivers/usb/chipidea/Makefile
@@ -15,5 +15,5 @@ ifneq ($(CONFIG_PCI),)
 endif
 
 ifneq ($(CONFIG_OF_DEVICE),)
-	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o
+	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o usbmisc_imx6q.o
 endif
diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index ef60d06..96ac67b 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -22,6 +22,7 @@
 #include <linux/regulator/consumer.h>
 
 #include "ci.h"
+#include "ci13xxx_imx.h"
 
 #define pdev_to_phy(pdev) \
 	((struct usb_phy *)platform_get_drvdata(pdev))
@@ -34,6 +35,55 @@ struct ci13xxx_imx_data {
 	struct regulator *reg_vbus;
 };
 
+static const struct usbmisc_ops *usbmisc_ops;
+
+/* Common functions shared by usbmisc drivers */
+
+int usbmisc_set_ops(const struct usbmisc_ops *ops)
+{
+	if (usbmisc_ops)
+		return -EBUSY;
+
+	usbmisc_ops = ops;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(usbmisc_set_ops);
+
+void usbmisc_unset_ops(const struct usbmisc_ops *ops)
+{
+	usbmisc_ops = NULL;
+}
+EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
+
+int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args args;
+	int ret;
+
+	usbdev->dev = dev;
+
+	ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
+					0, &args);
+	if (ret) {
+		dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
+			ret);
+		memset(usbdev, 0, sizeof(*usbdev));
+		return ret;
+	}
+	usbdev->index = args.args[0];
+	of_node_put(args.np);
+
+	if (of_find_property(np, "disable-over-current", NULL))
+		usbdev->disable_oc = 1;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
+
+/* End of common functions shared by usbmisc drivers*/
+
 static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
 	.name			= "ci13xxx_imx",
 	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
@@ -51,6 +101,10 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 	struct regulator *reg_vbus;
 	int ret;
 
+	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
+		&& !usbmisc_ops)
+		return -EPROBE_DEFER;
+
 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 	if (!data) {
 		dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
@@ -120,6 +174,16 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
 		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
 	}
+
+	if (usbmisc_ops && usbmisc_ops->init) {
+		ret = usbmisc_ops->init(&pdev->dev);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"usbmisc init failed, ret=%d\n", ret);
+			goto err;
+		}
+	}
+
 	plat_ci = ci13xxx_add_device(&pdev->dev,
 				pdev->resource, pdev->num_resources,
 				&ci13xxx_imx_platdata);
diff --git a/drivers/usb/chipidea/ci13xxx_imx.h b/drivers/usb/chipidea/ci13xxx_imx.h
new file mode 100644
index 0000000..2e88acc
--- /dev/null
+++ b/drivers/usb/chipidea/ci13xxx_imx.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* Used to set SoC specific callbacks */
+struct usbmisc_ops {
+	/* It's called once when probe a usb device */
+	int (*init)(struct device *dev);
+};
+
+struct usbmisc_usb_device {
+	struct device *dev; /* usb controller device */
+	int index;
+
+	int disable_oc:1; /* over current detect disabled */
+};
+
+int usbmisc_set_ops(const struct usbmisc_ops *ops);
+void usbmisc_unset_ops(const struct usbmisc_ops *ops);
+int
+usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev);
diff --git a/drivers/usb/chipidea/usbmisc_imx6q.c b/drivers/usb/chipidea/usbmisc_imx6q.c
new file mode 100644
index 0000000..416e3fc
--- /dev/null
+++ b/drivers/usb/chipidea/usbmisc_imx6q.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "ci13xxx_imx.h"
+
+#define USB_DEV_MAX 4
+
+#define BM_OVER_CUR_DIS		BIT(7)
+
+struct imx6q_usbmisc {
+	void __iomem *base;
+	spinlock_t lock;
+	struct clk *clk;
+	struct usbmisc_usb_device usbdev[USB_DEV_MAX];
+};
+
+static struct imx6q_usbmisc *usbmisc;
+
+static struct usbmisc_usb_device *get_usbdev(struct device *dev)
+{
+	int i, ret;
+
+	for (i = 0; i < USB_DEV_MAX; i++) {
+		if (usbmisc->usbdev[i].dev == dev)
+			return &usbmisc->usbdev[i];
+		else if (!usbmisc->usbdev[i].dev)
+			break;
+	}
+
+	if (i >= USB_DEV_MAX)
+		return ERR_PTR(-EBUSY);
+
+	ret = usbmisc_get_init_data(dev, &usbmisc->usbdev[i]);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return &usbmisc->usbdev[i];
+}
+
+static int usbmisc_imx6q_init(struct device *dev)
+{
+
+	struct usbmisc_usb_device *usbdev;
+	unsigned long flags;
+	u32 reg;
+
+	usbdev = get_usbdev(dev);
+	if (IS_ERR(usbdev))
+		return PTR_ERR(usbdev);
+
+	if (usbdev->disable_oc) {
+		spin_lock_irqsave(&usbmisc->lock, flags);
+		reg = readl(usbmisc->base + usbdev->index * 4);
+		writel(reg | BM_OVER_CUR_DIS,
+			usbmisc->base + usbdev->index * 4);
+		spin_unlock_irqrestore(&usbmisc->lock, flags);
+	}
+
+	return 0;
+}
+
+static const struct usbmisc_ops imx6q_usbmisc_ops = {
+	.init = usbmisc_imx6q_init,
+};
+
+static const struct of_device_id usbmisc_imx6q_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-usbmisc"},
+	{ /* sentinel */ }
+};
+
+static int __devinit usbmisc_imx6q_probe(struct platform_device *pdev)
+{
+	struct resource	*res;
+	struct imx6q_usbmisc *data;
+	int ret;
+
+	if (usbmisc)
+		return -EBUSY;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	spin_lock_init(&data->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!data->base)
+		return -EADDRNOTAVAIL;
+
+	data->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(data->clk)) {
+		dev_err(&pdev->dev,
+			"failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+		return PTR_ERR(data->clk);
+	}
+
+	ret = clk_prepare_enable(data->clk);
+	if (ret) {
+		dev_err(&pdev->dev,
+			"clk_prepare_enable failed, err=%d\n", ret);
+		return ret;
+	}
+
+	ret = usbmisc_set_ops(&imx6q_usbmisc_ops);
+	if (ret) {
+		clk_disable_unprepare(data->clk);
+		return ret;
+	}
+
+	usbmisc = data;
+
+	return 0;
+}
+
+static int __devexit usbmisc_imx6q_remove(struct platform_device *pdev)
+{
+	usbmisc_unset_ops(&imx6q_usbmisc_ops);
+	clk_disable_unprepare(usbmisc->clk);
+	return 0;
+}
+
+static struct platform_driver usbmisc_imx6q_driver = {
+	.probe = usbmisc_imx6q_probe,
+	.remove = __devexit_p(usbmisc_imx6q_remove),
+	.driver = {
+		.name = "usbmisc_imx6q",
+		.owner = THIS_MODULE,
+		.of_match_table = usbmisc_imx6q_dt_ids,
+	 },
+};
+
+int __init usbmisc_imx6q_drv_init(void)
+{
+	return platform_driver_register(&usbmisc_imx6q_driver);
+}
+subsys_initcall(usbmisc_imx6q_drv_init);
+
+void __exit usbmisc_imx6q_drv_exit(void)
+{
+	platform_driver_unregister(&usbmisc_imx6q_driver);
+}
+module_exit(usbmisc_imx6q_drv_exit);
+
+MODULE_ALIAS("platform:usbmisc-imx6q");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("driver for imx6q usb non-core registers");
+MODULE_AUTHOR("Richard Zhao <richard.zhao at freescale.com>");
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 02:58:29 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 14:58:29 +0800
Subject: [PATCH v6 3/3] ARM: dts: imx6q-sabrelite: add usbmisc device
In-Reply-To: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137109-32247-4-git-send-email-richard.zhao@freescale.com>

- add usbmisc device
- set property fsl,usbmisc for usb controllers
- set disable-over-current for imx6q-sabrelite usb otg

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boot/dts/imx6q-sabrelite.dts |    1 +
 arch/arm/boot/dts/imx6q.dtsi          |   10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3..aee0568 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -63,6 +63,7 @@
 		aips-bus at 02100000 { /* AIPS2 */
 			usb at 02184000 { /* USB OTG */
 				vbus-supply = <&reg_usb_otg_vbus>;
+				disable-over-current;
 				status = "okay";
 			};
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..7c27267 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -636,6 +636,7 @@
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 0x04>;
 				fsl,usbphy = <&usbphy1>;
+				fsl,usbmisc = <&usbmisc 0>;
 				status = "disabled";
 			};
 
@@ -644,6 +645,7 @@
 				reg = <0x02184200 0x200>;
 				interrupts = <0 40 0x04>;
 				fsl,usbphy = <&usbphy2>;
+				fsl,usbmisc = <&usbmisc 1>;
 				status = "disabled";
 			};
 
@@ -651,6 +653,7 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184400 0x200>;
 				interrupts = <0 41 0x04>;
+				fsl,usbmisc = <&usbmisc 2>;
 				status = "disabled";
 			};
 
@@ -658,9 +661,16 @@
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184600 0x200>;
 				interrupts = <0 42 0x04>;
+				fsl,usbmisc = <&usbmisc 3>;
 				status = "disabled";
 			};
 
+			usbmisc: usbmisc at 02184800 {
+				#index-cells = <1>;
+				compatible = "fsl,imx6q-usbmisc";
+				reg = <0x02184800 0x200>;
+			};
+
 			ethernet at 02188000 {
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 02:58:28 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 14:58:28 +0800
Subject: [PATCH v6 2/3] ARM: imx6q: clk_register_clkdev usbmisc clock
In-Reply-To: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137109-32247-3-git-send-email-richard.zhao@freescale.com>

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx6q.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520..660fcbb 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -405,6 +405,7 @@ int __init mx6q_clocks_init(void)
 	clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
 	clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
 	clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
+	clk_register_clkdev(clk[usboh3], NULL, "2184800.usbmisc");
 	clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
 	clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
 	clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:06 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:06 +0800
Subject: [PATCH v2 00/11] chipidea/imx: add otg support and some bug fix
Message-ID: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>

The patch set is tested on imx6q_sabrelite board.

The patch can also be found at
https://github.com/riczhao/kernel-imx/commits/topics/usb-driver

For test which merged platform patches:
https://github.com/riczhao/kernel-imx/commits/topics/usb-test

Changes since v1:
 - move usbmisc as the other patch series.
 - remove regulater_disable and old comments in ci13xxx_imx.

Richard Zhao (11):
  USB: chipidea: imx: add pinctrl support
  USB: chipidea: delay 2ms before read ID status at probe time
  USB: chipidea: move OTGSC_IDIS clearing from ci_role_work to irq
    handler
  USB: chipidea: clear gadget struct at udc_start fail path
  USB: chipidea: don't let probe fail if otg controller start one role
    failed
  USB: mxs-phy: add basic otg support
  USB: chipidea: add vbus detect for udc
  USB: chipidea: convert to use devm_request_irq
  USB: chipidea: add -DDEBUG if CONFIG_USB_CHIPIDEA_DEBUG
  USB: chipidea: add set_vbus_power support
  USB: chipidea: re-order irq handling to avoid unhandled irq

 drivers/usb/chipidea/Makefile      |    2 ++
 drivers/usb/chipidea/ci.h          |    1 +
 drivers/usb/chipidea/ci13xxx_imx.c |   51 +++++++++++++++++++++++-------------
 drivers/usb/chipidea/core.c        |   36 +++++++++++++++----------
 drivers/usb/chipidea/host.c        |    8 ++++++
 drivers/usb/chipidea/udc.c         |   40 +++++++++++++++++++++++++++-
 drivers/usb/otg/mxs-phy.c          |   21 +++++++++++++++
 include/linux/usb/chipidea.h       |    2 ++
 8 files changed, 128 insertions(+), 33 deletions(-)

-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:10 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:10 +0800
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start fail
 path
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>

States in gadget are not needed any more, set it to zero.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/udc.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index c7a032a..9fb6394 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1746,6 +1746,7 @@ free_pools:
 	dma_pool_destroy(ci->td_pool);
 free_qh_pool:
 	dma_pool_destroy(ci->qh_pool);
+	memset(&ci->gadget, 0, sizeof(ci->gadget));
 	return retval;
 }
 
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:07 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:07 +0800
Subject: [PATCH v2 01/11] USB: chipidea: imx: add pinctrl support
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-2-git-send-email-richard.zhao@freescale.com>

Some controllers may not need to setup pinctrl, so we don't fail the
probe if pinctrl get/select failed.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/ci13xxx_imx.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index 96ac67b..0f5ca4b 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -20,6 +20,7 @@
 #include <linux/usb/chipidea.h>
 #include <linux/clk.h>
 #include <linux/regulator/consumer.h>
+#include <linux/pinctrl/consumer.h>
 
 #include "ci.h"
 #include "ci13xxx_imx.h"
@@ -99,6 +100,7 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 	struct device_node *phy_np;
 	struct resource *res;
 	struct regulator *reg_vbus;
+	struct pinctrl *pinctrl;
 	int ret;
 
 	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
@@ -117,6 +119,11 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 		return -ENOENT;
 	}
 
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl))
+		dev_warn(&pdev->dev, "pinctrl get/select failed, err=%ld\n",
+			PTR_ERR(pinctrl));
+
 	data->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(data->clk)) {
 		dev_err(&pdev->dev,
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:08 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:08 +0800
Subject: [PATCH v2 02/11] USB: chipidea: delay 2ms before read ID status at
 probe time
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-3-git-send-email-richard.zhao@freescale.com>

The ID pin needs 1ms debounce time, event at probe time. We delay 2ms
for safe.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/core.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 1083585..3c3ed77 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -462,6 +462,8 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
 
 	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
 		ci->is_otg = true;
+		/* ID pin needs 1ms debouce time, we delay 2ms for safe */
+		mdelay(2);
 		ci->role = ci_otg_role(ci);
 	} else {
 		ci->role = ci->roles[CI_ROLE_HOST]
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:11 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:11 +0800
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>

One role failed, but the other role will possiblly still work.
For example, when udc start failed, if plug in a host device,
it works.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/core.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 19ef324..8fd390a 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
 	ret = ci_role_start(ci, ci->role);
 	if (ret) {
 		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
-		ret = -ENODEV;
-		goto rm_wq;
+		ci->role = CI_ROLE_END;
+		if (!ci->is_otg) {
+			ret = -ENODEV;
+			goto rm_wq;
+		}
 	}
 
 	platform_set_drvdata(pdev, ci);
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:09 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:09 +0800
Subject: [PATCH v2 03/11] USB: chipidea: move OTGSC_IDIS clearing from
 ci_role_work to irq handler
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-4-git-send-email-richard.zhao@freescale.com>

OTGSC_IDIS must be cleared in irq handler to avoid re-queue the work.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/core.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 3c3ed77..19ef324 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -273,8 +273,6 @@ static void ci_role_work(struct work_struct *work)
 	struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
 	enum ci_role role = ci_otg_role(ci);
 
-	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
-
 	if (role != ci->role) {
 		dev_dbg(ci->dev, "switching from %s to %s\n",
 			ci_role(ci)->name, ci->roles[role]->name);
@@ -325,6 +323,7 @@ static irqreturn_t ci_irq(int irq, void *data)
 		u32 sts = hw_read(ci, OP_OTGSC, ~0);
 
 		if (sts & OTGSC_IDIS) {
+			hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
 			queue_work(ci->wq, &ci->work);
 			ret = IRQ_HANDLED;
 		}
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:12 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:12 +0800
Subject: [PATCH v2 06/11] USB: mxs-phy: add basic otg support
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-7-git-send-email-richard.zhao@freescale.com>

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/otg/mxs-phy.c |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/usb/otg/mxs-phy.c b/drivers/usb/otg/mxs-phy.c
index c1a67cb..6a03e97 100644
--- a/drivers/usb/otg/mxs-phy.c
+++ b/drivers/usb/otg/mxs-phy.c
@@ -97,12 +97,24 @@ static int mxs_phy_on_disconnect(struct usb_phy *phy, int port)
 	return 0;
 }
 
+static int mxs_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+	return 0;
+}
+
+static int mxs_phy_set_peripheral(struct usb_otg *otg,
+					struct usb_gadget *gadget)
+{
+	return 0;
+}
+
 static int mxs_phy_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	void __iomem *base;
 	struct clk *clk;
 	struct mxs_phy *mxs_phy;
+	struct usb_otg *otg;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
@@ -139,6 +151,15 @@ static int mxs_phy_probe(struct platform_device *pdev)
 
 	mxs_phy->clk = clk;
 
+	otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), GFP_KERNEL);
+	if (!otg)
+		return -ENOMEM;
+	otg->phy = &mxs_phy->phy;
+	otg->set_host = mxs_phy_set_host;
+	otg->set_peripheral = mxs_phy_set_peripheral;
+
+	mxs_phy->phy.otg = otg;
+
 	platform_set_drvdata(pdev, &mxs_phy->phy);
 
 	return 0;
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:13 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:13 +0800
Subject: [PATCH v2 07/11] USB: chipidea: add vbus detect for udc
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-8-git-send-email-richard.zhao@freescale.com>

Using vbus valid interrupt to detect vbus.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/ci.h  |    1 +
 drivers/usb/chipidea/udc.c |   39 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index d738603..e25d126 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -139,6 +139,7 @@ struct ci13xxx {
 	enum ci_role			role;
 	bool				is_otg;
 	struct work_struct		work;
+	struct work_struct		vbus_work;
 	struct workqueue_struct		*wq;
 
 	struct dma_pool			*qh_pool;
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 9fb6394..2cb4498 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -308,6 +308,18 @@ static u32 hw_test_and_clear_intr_active(struct ci13xxx *ci)
 	return reg;
 }
 
+static void hw_enable_vbus_intr(struct ci13xxx *ci)
+{
+	hw_write(ci, OP_OTGSC, OTGSC_AVVIS, OTGSC_AVVIS);
+	hw_write(ci, OP_OTGSC, OTGSC_AVVIE, OTGSC_AVVIE);
+	queue_work(ci->wq, &ci->vbus_work);
+}
+
+static void hw_disable_vbus_intr(struct ci13xxx *ci)
+{
+	hw_write(ci, OP_OTGSC, OTGSC_AVVIE, 0);
+}
+
 /**
  * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  *                                interruption)
@@ -374,6 +386,16 @@ static int hw_usb_reset(struct ci13xxx *ci)
 	return 0;
 }
 
+static void vbus_work(struct work_struct *work)
+{
+	struct ci13xxx *ci = container_of(work, struct ci13xxx, vbus_work);
+
+	if (hw_read(ci, OP_OTGSC, OTGSC_AVV))
+		usb_gadget_vbus_connect(&ci->gadget);
+	else
+		usb_gadget_vbus_disconnect(&ci->gadget);
+}
+
 /******************************************************************************
  * UTIL block
  *****************************************************************************/
@@ -1376,6 +1398,7 @@ static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
 		if (is_active) {
 			pm_runtime_get_sync(&_gadget->dev);
 			hw_device_reset(ci, USBMODE_CM_DC);
+			hw_enable_vbus_intr(ci);
 			hw_device_state(ci, ci->ep0out->qh.dma);
 		} else {
 			hw_device_state(ci, 0);
@@ -1517,8 +1540,10 @@ static int ci13xxx_start(struct usb_gadget *gadget,
 	pm_runtime_get_sync(&ci->gadget.dev);
 	if (ci->platdata->flags & CI13XXX_PULLUP_ON_VBUS) {
 		if (ci->vbus_active) {
-			if (ci->platdata->flags & CI13XXX_REGS_SHARED)
+			if (ci->platdata->flags & CI13XXX_REGS_SHARED) {
 				hw_device_reset(ci, USBMODE_CM_DC);
+				hw_enable_vbus_intr(ci);
+			}
 		} else {
 			pm_runtime_put_sync(&ci->gadget.dev);
 			goto done;
@@ -1624,6 +1649,13 @@ static irqreturn_t udc_irq(struct ci13xxx *ci)
 	} else {
 		retval = IRQ_NONE;
 	}
+
+	intr = hw_read(ci, OP_OTGSC, ~0);
+	hw_write(ci, OP_OTGSC, ~0, intr);
+
+	if (intr & (OTGSC_AVVIE & OTGSC_AVVIS))
+		queue_work(ci->wq, &ci->vbus_work);
+
 	spin_unlock(&ci->lock);
 
 	return retval;
@@ -1699,6 +1731,7 @@ static int udc_start(struct ci13xxx *ci)
 		retval = hw_device_reset(ci, USBMODE_CM_DC);
 		if (retval)
 			goto put_transceiver;
+		hw_enable_vbus_intr(ci);
 	}
 
 	retval = device_register(&ci->gadget.dev);
@@ -1762,6 +1795,9 @@ static void udc_stop(struct ci13xxx *ci)
 	if (ci == NULL)
 		return;
 
+	hw_disable_vbus_intr(ci);
+	cancel_work_sync(&ci->vbus_work);
+
 	usb_del_gadget_udc(&ci->gadget);
 
 	for (i = 0; i < ci->hw_ep_max; i++) {
@@ -1806,6 +1842,7 @@ int ci_hdrc_gadget_init(struct ci13xxx *ci)
 	rdrv->irq	= udc_irq;
 	rdrv->name	= "gadget";
 	ci->roles[CI_ROLE_GADGET] = rdrv;
+	INIT_WORK(&ci->vbus_work, vbus_work);
 
 	return 0;
 }
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:14 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:14 +0800
Subject: [PATCH v2 08/11] USB: chipidea: convert to use devm_request_irq
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-9-git-send-email-richard.zhao@freescale.com>

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/core.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 8fd390a..7485c84 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -481,8 +481,8 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, ci);
-	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
-			  ci);
+	ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
+				ci->platdata->name, ci);
 	if (ret)
 		goto stop;
 
@@ -513,7 +513,6 @@ static int __devexit ci_hdrc_remove(struct platform_device *pdev)
 	flush_workqueue(ci->wq);
 	destroy_workqueue(ci->wq);
 	device_remove_file(ci->dev, &dev_attr_role);
-	free_irq(ci->irq, ci);
 	ci_role_stop(ci);
 
 	return 0;
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:15 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:15 +0800
Subject: [PATCH v2 09/11] USB: chipidea: add -DDEBUG if
 CONFIG_USB_CHIPIDEA_DEBUG
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-10-git-send-email-richard.zhao@freescale.com>

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/Makefile |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
index 57e510f..d92ca32 100644
--- a/drivers/usb/chipidea/Makefile
+++ b/drivers/usb/chipidea/Makefile
@@ -1,3 +1,5 @@
+ccflags-$(CONFIG_USB_CHIPIDEA_DEBUG) := -DDEBUG
+
 obj-$(CONFIG_USB_CHIPIDEA)		+= ci_hdrc.o
 
 ci_hdrc-y				:= core.o
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:16 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:16 +0800
Subject: [PATCH v2 10/11] USB: chipidea: add set_vbus_power support
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-11-git-send-email-richard.zhao@freescale.com>

set_vbus_power is used to enable or disable vbus power for usb host.

[Marc Kleine-Budde <mkl at pengutronix.de>: fix regulator unbalance disable]

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/ci13xxx_imx.c |   44 +++++++++++++++++++++---------------
 drivers/usb/chipidea/host.c        |    8 +++++++
 include/linux/usb/chipidea.h       |    2 ++
 3 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
index 0f5ca4b..5c0be08 100644
--- a/drivers/usb/chipidea/ci13xxx_imx.c
+++ b/drivers/usb/chipidea/ci13xxx_imx.c
@@ -27,6 +27,8 @@
 
 #define pdev_to_phy(pdev) \
 	((struct usb_phy *)platform_get_drvdata(pdev))
+#define ci_to_imx_data(ci) \
+	((struct ci13xxx_imx_data *)dev_get_drvdata(ci->dev->parent))
 
 struct ci13xxx_imx_data {
 	struct device_node *phy_np;
@@ -85,12 +87,32 @@ EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
 
 /* End of common functions shared by usbmisc drivers*/
 
+static int ci13xxx_imx_vbus(struct ci13xxx *ci, int enable)
+{
+	struct ci13xxx_imx_data *data = ci_to_imx_data(ci);
+	int ret;
+
+	if (!data->reg_vbus)
+		return 0;
+
+	if (enable)
+		ret = regulator_enable(data->reg_vbus);
+	else
+		ret = regulator_disable(data->reg_vbus);
+	if (ret)
+		dev_err(ci->dev, "ci13xxx_imx_vbus failed, enable:%d err:%d\n",
+			enable, ret);
+
+	return ret;
+}
+
 static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
 	.name			= "ci13xxx_imx",
 	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
 				  CI13XXX_PULLUP_ON_VBUS |
 				  CI13XXX_DISABLE_STREAMING,
 	.capoffset		= DEF_CAPOFFSET,
+	.set_vbus_power		= ci13xxx_imx_vbus,
 };
 
 static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
@@ -153,20 +175,11 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 		}
 	}
 
-	/* we only support host now, so enable vbus here */
 	reg_vbus = devm_regulator_get(&pdev->dev, "vbus");
-	if (!IS_ERR(reg_vbus)) {
-		ret = regulator_enable(reg_vbus);
-		if (ret) {
-			dev_err(&pdev->dev,
-				"Failed to enable vbus regulator, err=%d\n",
-				ret);
-			goto put_np;
-		}
+	if (!IS_ERR(reg_vbus))
 		data->reg_vbus = reg_vbus;
-	} else {
+	else
 		reg_vbus = NULL;
-	}
 
 	ci13xxx_imx_platdata.phy = data->phy;
 
@@ -191,6 +204,8 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 		}
 	}
 
+	platform_set_drvdata(pdev, data);
+
 	plat_ci = ci13xxx_add_device(&pdev->dev,
 				pdev->resource, pdev->num_resources,
 				&ci13xxx_imx_platdata);
@@ -203,7 +218,6 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 	}
 
 	data->ci_pdev = plat_ci;
-	platform_set_drvdata(pdev, data);
 
 	pm_runtime_no_callbacks(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
@@ -211,9 +225,6 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
 	return 0;
 
 err:
-	if (reg_vbus)
-		regulator_disable(reg_vbus);
-put_np:
 	if (phy_np)
 		of_node_put(phy_np);
 	clk_disable_unprepare(data->clk);
@@ -227,9 +238,6 @@ static int __devexit ci13xxx_imx_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 	ci13xxx_remove_device(data->ci_pdev);
 
-	if (data->reg_vbus)
-		regulator_disable(data->reg_vbus);
-
 	if (data->phy) {
 		usb_phy_shutdown(data->phy);
 		module_put(data->phy->dev->driver->owner);
diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c
index ebff9f4..e091147 100644
--- a/drivers/usb/chipidea/host.c
+++ b/drivers/usb/chipidea/host.c
@@ -106,6 +106,12 @@ static int host_start(struct ci13xxx *ci)
 	if (usb_disabled())
 		return -ENODEV;
 
+	if (ci->platdata->set_vbus_power) {
+		ret = ci->platdata->set_vbus_power(ci, 1);
+		if (ret)
+			return ret;
+	}
+
 	hcd = usb_create_hcd(&ci_ehci_hc_driver, ci->dev, dev_name(ci->dev));
 	if (!hcd)
 		return -ENOMEM;
@@ -138,6 +144,8 @@ static void host_stop(struct ci13xxx *ci)
 
 	usb_remove_hcd(hcd);
 	usb_put_hcd(hcd);
+	if (ci->platdata->set_vbus_power)
+		ci->platdata->set_vbus_power(ci, 0);
 }
 
 int ci_hdrc_host_init(struct ci13xxx *ci)
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h
index 544825d..080f479 100644
--- a/include/linux/usb/chipidea.h
+++ b/include/linux/usb/chipidea.h
@@ -23,6 +23,8 @@ struct ci13xxx_platform_data {
 #define CI13XXX_CONTROLLER_RESET_EVENT		0
 #define CI13XXX_CONTROLLER_STOPPED_EVENT	1
 	void	(*notify_event) (struct ci13xxx *ci, unsigned event);
+	/* set vbus power, it must be called in non-atomic context */
+	int	(*set_vbus_power) (struct ci13xxx *ci, int enable);
 };
 
 /* Default offset of capability registers */
-- 
1.7.9.5




From richard.zhao at freescale.com  Tue Aug 28 03:03:17 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 15:03:17 +0800
Subject: [PATCH v2 11/11] USB: chipidea: re-order irq handling to avoid
 unhandled irq
In-Reply-To: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
Message-ID: <1346137397-32374-12-git-send-email-richard.zhao@freescale.com>

- let role driver handle irq before ID change check. It give the
  role driver a chance to handle disconnect.
- disable irq during switch role. No role driver to handle irq in
  the period.

Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
---
 drivers/usb/chipidea/core.c |   21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 7485c84..0942b9b 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -279,6 +279,7 @@ static void ci_role_work(struct work_struct *work)
 
 		ci_role_stop(ci);
 		ci_role_start(ci, role);
+		enable_irq(ci->irq);
 	}
 }
 
@@ -318,18 +319,22 @@ static irqreturn_t ci_irq(int irq, void *data)
 {
 	struct ci13xxx *ci = data;
 	irqreturn_t ret = IRQ_NONE;
+	u32 otgsc = 0;
 
-	if (ci->is_otg) {
-		u32 sts = hw_read(ci, OP_OTGSC, ~0);
+	if (ci->is_otg)
+		otgsc = hw_read(ci, OP_OTGSC, ~0);
 
-		if (sts & OTGSC_IDIS) {
-			hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
-			queue_work(ci->wq, &ci->work);
-			ret = IRQ_HANDLED;
-		}
+	if (ci->role != CI_ROLE_END)
+		ret = ci_role(ci)->irq(ci);
+
+	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
+		hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
+		disable_irq_nosync(ci->irq);
+		queue_work(ci->wq, &ci->work);
+		ret = IRQ_HANDLED;
 	}
 
-	return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci);
+	return ret;
 }
 
 static DEFINE_IDA(ci_ida);
-- 
1.7.9.5




From swarren at wwwdotorg.org  Tue Aug 28 03:10:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 00:10:00 -0700
Subject: [PATCH 2/2] ARM: dt: tegra: harmony: add regulators
In-Reply-To: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
References: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1346137800-7448-2-git-send-email-swarren@wwwdotorg.org>

From: Laxman Dewangan <ldewangan at nvidia.com>

Harmony uses a TPS6586x regulator. Instantiate this, and hook up a
couple of fixed GPIO-controlled regulators too.

Based on Ventana regulator patch by Stephen Warren <swarren at nvidia.com>
and converted to Harmony.

[swarren: Remove board-harmony{-power.c,.h} now that they're unused.
 Fixed board-harmony-pcie.c to control the 1V5 GPIO using the regulator
 introduced in the .dts file rather than directly]

Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
Note that this depends on a TPS6586x driver patch that I believe Mark
Brown will be placing into a branch for the Tegra tree to merge. Also,
I haven't boot-tested this, but I hope that Laxman will. If not, I will
once I get back from the conference.

 arch/arm/boot/dts/tegra20-harmony.dts     |  210 +++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Makefile              |    1 -
 arch/arm/mach-tegra/board-dt-tegra20.c    |    9 +-
 arch/arm/mach-tegra/board-harmony-pcie.c  |   28 ++--
 arch/arm/mach-tegra/board-harmony-power.c |  144 --------------------
 arch/arm/mach-tegra/board-harmony.h       |   28 ----
 6 files changed, 227 insertions(+), 193 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/board-harmony-power.c
 delete mode 100644 arch/arm/mach-tegra/board-harmony.h

diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index f146dbf..0add02b 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -275,6 +275,152 @@
 	i2c at 7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;
+
+		pmic: tps6586x at 34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sys_reg: regulator at 0 {
+					reg = <0>;
+					regulator-compatible = "sys";
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				regulator at 1 {
+					reg = <1>;
+					regulator-compatible = "sm0";
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				regulator at 2 {
+					reg = <2>;
+					regulator-compatible = "sm1";
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: regulator at 3 {
+					reg = <3>;
+					regulator-compatible = "sm2";
+					regulator-name = "vdd_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				regulator at 5 {
+					reg = <5>;
+					regulator-compatible = "ldo1";
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				regulator at 6 {
+					reg = <6>;
+					regulator-compatible = "ldo2";
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				regulator at 7 {
+					reg = <7>;
+					regulator-compatible = "ldo3";
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				regulator at 8 {
+					reg = <8>;
+					regulator-compatible = "ldo4";
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				regulator at 9 {
+					reg = <9>;
+					regulator-compatible = "ldo5";
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 10 {
+					reg = <10>;
+					regulator-compatible = "ldo6";
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 11 {
+					reg = <11>;
+					regulator-compatible = "ldo7";
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				regulator at 12 {
+					reg = <12>;
+					regulator-compatible = "ldo8";
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				regulator at 13 {
+					reg = <13>;
+					regulator-compatible = "ldo9";
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				regulator at 14 {
+					reg = <14>;
+					regulator-compatible = "ldo_rtc";
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
 	};
 
 	pmc {
@@ -310,6 +456,70 @@
 		bus-width = <8>;
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "vdd_1v5";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			gpio = <&pmic 0 0>;
+		};
+
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "vdd_1v2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&pmic 1 0>;
+			enable-active-high;
+		};
+
+		regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vdd_1v05";
+			regulator-min-microvolt = <10500000>;
+			regulator-max-microvolt = <10500000>;
+			gpio = <&pmic 2 0>;
+			enable-active-high;
+		};
+
+		regulator at 4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vdd_pnl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio 22 0>; /* gpio PC6 */
+			enable-active-high;
+		};
+
+		regulator at 5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "vdd_bl";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio 176 0>; /* gpio PW0 */
+			enable-active-high;
+		};
+	};
+
 	sound {
 		compatible = "nvidia,tegra-audio-wm8903-harmony",
 			     "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 90a40c3..0e04bc4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -29,6 +29,5 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-pcie.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-harmony-power.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-paz00.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 30f8036..adc6b98 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -44,7 +44,6 @@
 #include <mach/usb_phy.h>
 
 #include "board.h"
-#include "board-harmony.h"
 #include "clock.h"
 
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -134,15 +133,9 @@ static void __init trimslice_init(void)
 
 static void __init harmony_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
 	int ret;
 
-	ret = harmony_regulator_init();
-	if (ret) {
-		pr_err("harmony_regulator_init() failed: %d\n", ret);
-		return;
-	}
-
-#ifdef CONFIG_TEGRA_PCI
 	ret = harmony_pcie_init();
 	if (ret)
 		pr_err("harmony_pcie_init() failed: %d\n", ret);
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index e8c3fda..662fb20 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -23,26 +23,29 @@
 #include <asm/mach-types.h>
 
 #include "board.h"
-#include "board-harmony.h"
 
 #ifdef CONFIG_TEGRA_PCI
 
 int __init harmony_pcie_init(void)
 {
-	struct regulator *regulator = NULL;
+	struct regulator *regulator_1v5, *regulator_pex;
 	int err;
 
-	err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
-	if (err)
-		return err;
+	regulator_1v5 = regulator_get(NULL, "vdd_1v5");
+	if (IS_ERR_OR_NULL(regulator_1v5)) {
+		err = PTR_ERR(regulator_1v5);
+		goto err_reg;
+	}
 
-	gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
+	regulator_enable(regulator_1v5);
 
-	regulator = regulator_get(NULL, "pex_clk");
-	if (IS_ERR_OR_NULL(regulator))
+	regulator_pex = regulator_get(NULL, "pex_clk");
+	if (IS_ERR_OR_NULL(regulator_pex)) {
+		err = PTR_ERR(regulator_pex);
 		goto err_reg;
+	}
 
-	regulator_enable(regulator);
+	regulator_enable(regulator_pex);
 
 	err = tegra_pcie_init(true, true);
 	if (err)
@@ -51,10 +54,11 @@ int __init harmony_pcie_init(void)
 	return 0;
 
 err_pcie:
-	regulator_disable(regulator);
-	regulator_put(regulator);
+	regulator_disable(regulator_pex);
+	regulator_put(regulator_pex);
 err_reg:
-	gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
+	regulator_disable(regulator_1v5);
+	regulator_put(regulator_1v5);
 
 	return err;
 }
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
deleted file mode 100644
index 8f9cf77..0000000
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
- */
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of.h>
-#include <linux/of_i2c.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-#include "board-harmony.h"
-
-static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
-	REGULATOR_SUPPLY("pex_clk", NULL),
-};
-
-static struct regulator_init_data ldo0_data = {
-	.supply_regulator = "vdd_sm2",
-	.constraints = {
-		.name = "vdd_ldo0",
-		.min_uV = 3300 * 1000,
-		.max_uV = 3300 * 1000,
-		.valid_modes_mask = (REGULATOR_MODE_NORMAL |
-				     REGULATOR_MODE_STANDBY),
-		.valid_ops_mask = (REGULATOR_CHANGE_MODE |
-				   REGULATOR_CHANGE_STATUS |
-				   REGULATOR_CHANGE_VOLTAGE),
-		.apply_uV = 1,
-	},
-	.num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
-	.consumer_supplies = tps658621_ldo0_supply,
-};
-
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
-	static struct regulator_init_data _id##_data = {		\
-		.supply_regulator = _supply,				\
-		.constraints = {					\
-			.name = _name,					\
-			.min_uV = (_minmv)*1000,			\
-			.max_uV = (_maxmv)*1000,			\
-			.valid_modes_mask = (REGULATOR_MODE_NORMAL |	\
-					     REGULATOR_MODE_STANDBY),	\
-			.valid_ops_mask = (REGULATOR_CHANGE_MODE |	\
-					   REGULATOR_CHANGE_STATUS |	\
-					   REGULATOR_CHANGE_VOLTAGE),	\
-			.always_on = _on,				\
-		},							\
-	}
-
-HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,	    1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
-
-#define TPS_REG(_id, _data)			\
-	{					\
-		.id = TPS6586X_ID_##_id,	\
-		.name = "tps6586x-regulator",	\
-		.platform_data = _data,		\
-	}
-
-static struct tps6586x_subdev_info tps_devs[] = {
-	TPS_REG(SM_0, &sm0_data),
-	TPS_REG(SM_1, &sm1_data),
-	TPS_REG(SM_2, &sm2_data),
-	TPS_REG(LDO_0, &ldo0_data),
-	TPS_REG(LDO_1, &ldo1_data),
-	TPS_REG(LDO_2, &ldo2_data),
-	TPS_REG(LDO_3, &ldo3_data),
-	TPS_REG(LDO_4, &ldo4_data),
-	TPS_REG(LDO_5, &ldo5_data),
-	TPS_REG(LDO_6, &ldo6_data),
-	TPS_REG(LDO_7, &ldo7_data),
-	TPS_REG(LDO_8, &ldo8_data),
-	TPS_REG(LDO_9, &ldo9_data),
-};
-
-static struct tps6586x_platform_data tps_platform = {
-	.irq_base	= TEGRA_NR_IRQS,
-	.num_subdevs	= ARRAY_SIZE(tps_devs),
-	.subdevs	= tps_devs,
-	.gpio_base	= HARMONY_GPIO_TPS6586X(0),
-};
-
-static struct i2c_board_info __initdata harmony_regulators[] = {
-	{
-		I2C_BOARD_INFO("tps6586x", 0x34),
-		.irq		= INT_EXTERNAL_PMU,
-		.platform_data	= &tps_platform,
-	},
-};
-
-int __init harmony_regulator_init(void)
-{
-	struct device_node *np;
-	struct i2c_adapter *adapter;
-
-	regulator_register_always_on(0, "vdd_sys",
-		NULL, 0, 5000000);
-
-	np = of_find_node_by_path("/i2c at 7000d000");
-	if (np == NULL) {
-		pr_err("Could not find device_node for DVC I2C\n");
-		return -ENODEV;
-	}
-
-	adapter = of_find_i2c_adapter_by_node(np);
-	if (!adapter) {
-		pr_err("Could not find i2c_adapter for DVC I2C\n");
-		return -ENODEV;
-	}
-
-	i2c_new_device(adapter, harmony_regulators);
-
-	return 0;
-}
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
deleted file mode 100644
index 7ae87088..0000000
--- a/arch/arm/mach-tegra/board-harmony.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_HARMONY_H
-#define _MACH_TEGRA_BOARD_HARMONY_H
-
-#include <mach/gpio-tegra.h>
-
-#define HARMONY_GPIO_TPS6586X(_x_)	(TEGRA_NR_GPIOS + (_x_))
-
-#define TEGRA_GPIO_EN_VDD_1V05_GPIO	HARMONY_GPIO_TPS6586X(2)
-
-int harmony_regulator_init(void);
-
-#endif
-- 
1.7.9.5



From swarren at wwwdotorg.org  Tue Aug 28 03:09:59 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 00:09:59 -0700
Subject: [PATCH 1/2] ARM: tegra: remove dead code
Message-ID: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Now that all boards are converted to device tree, devices.[ch] and
board-pinmux.[ch] are no longer used. So, remove them.

The only exception is the EHCI platform data in devices.h. Move that
data to board-dt-tegra20.c - the only places it's used.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
These patches are both destined for Tegra's for-3.7/board-removal branch.

 arch/arm/mach-tegra/Makefile           |    2 -
 arch/arm/mach-tegra/board-dt-tegra20.c |   27 +-
 arch/arm/mach-tegra/board-pinmux.c     |   87 ----
 arch/arm/mach-tegra/board-pinmux.h     |   54 ---
 arch/arm/mach-tegra/devices.c          |  701 --------------------------------
 arch/arm/mach-tegra/devices.h          |   60 ---
 6 files changed, 26 insertions(+), 905 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/board-pinmux.c
 delete mode 100644 arch/arm/mach-tegra/board-pinmux.h
 delete mode 100644 arch/arm/mach-tegra/devices.c
 delete mode 100644 arch/arm/mach-tegra/devices.h

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b94858f..90a40c3 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,4 @@
-obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
-obj-y                                   += devices.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index d9eeae6..30f8036 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -28,6 +28,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pda_power.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
@@ -40,11 +41,35 @@
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
+#include <mach/usb_phy.h>
 
 #include "board.h"
 #include "board-harmony.h"
 #include "clock.h"
-#include "devices.h"
+
+struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+	.operating_mode = TEGRA_USB_OTG,
+	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
+};
+
+struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+	.reset_gpio = -1,
+	.clk = "cdev2",
+};
+
+struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+	.phy_config = &tegra_ehci2_ulpi_phy_config,
+	.operating_mode = TEGRA_USB_HOST,
+	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
+};
+
+struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+	.operating_mode = TEGRA_USB_HOST,
+	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
+};
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
deleted file mode 100644
index a5574c7..0000000
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/notifier.h>
-#include <linux/string.h>
-
-#include "board-pinmux.h"
-#include "devices.h"
-
-unsigned long tegra_pincfg_pullnone_driven[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullnone_tristate[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pullnone_na[1] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-};
-
-unsigned long tegra_pincfg_pullup_driven[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullup_tristate[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pullup_na[1] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-};
-
-unsigned long tegra_pincfg_pulldown_driven[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pulldown_tristate[2] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-unsigned long tegra_pincfg_pulldown_na[1] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-};
-
-unsigned long tegra_pincfg_pullna_driven[1] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-};
-
-unsigned long tegra_pincfg_pullna_tristate[1] = {
-	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-};
-
-static struct platform_device *devices[] = {
-	&tegra_gpio_device,
-	&tegra_pinmux_device,
-};
-
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-			     struct tegra_board_pinmux_conf *conf_b)
-{
-	if (conf_a)
-		pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
-	if (conf_b)
-		pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
deleted file mode 100644
index c5f3f33..0000000
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_BOARD_PINMUX_H
-#define __MACH_TEGRA_BOARD_PINMUX_H
-
-#include <linux/pinctrl/machine.h>
-
-#include <mach/pinconf-tegra.h>
-
-#define PINMUX_DEV "tegra20-pinctrl"
-
-#define TEGRA_MAP_MUX(_group_, _function_) \
-	PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
-
-#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
-	PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
-
-#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
-	TEGRA_MAP_MUX(_group_, _function_), \
-	TEGRA_MAP_CONF(_group_, _pull_, _drive_)
-
-extern unsigned long tegra_pincfg_pullnone_driven[2];
-extern unsigned long tegra_pincfg_pullnone_tristate[2];
-extern unsigned long tegra_pincfg_pullnone_na[1];
-extern unsigned long tegra_pincfg_pullup_driven[2];
-extern unsigned long tegra_pincfg_pullup_tristate[2];
-extern unsigned long tegra_pincfg_pullup_na[1];
-extern unsigned long tegra_pincfg_pulldown_driven[2];
-extern unsigned long tegra_pincfg_pulldown_tristate[2];
-extern unsigned long tegra_pincfg_pulldown_na[1];
-extern unsigned long tegra_pincfg_pullna_driven[1];
-extern unsigned long tegra_pincfg_pullna_tristate[1];
-
-struct tegra_board_pinmux_conf {
-	struct pinctrl_map *maps;
-	int map_count;
-};
-
-void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
-			     struct tegra_board_pinmux_conf *conf_b);
-
-#endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
deleted file mode 100644
index 61e9603..0000000
--- a/arch/arm/mach-tegra/devices.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *	Colin Cross <ccross at android.com>
- *	Erik Gilling <ccross at android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-
-#include <linux/resource.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/fsl_devices.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c-tegra.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/dma.h>
-#include <mach/usb_phy.h>
-
-#include "gpio-names.h"
-#include "devices.h"
-
-static struct resource gpio_resource[] = {
-	[0] = {
-		.start	= TEGRA_GPIO_BASE,
-		.end	= TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_GPIO1,
-		.end	= INT_GPIO1,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= INT_GPIO2,
-		.end	= INT_GPIO2,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[3] = {
-		.start	= INT_GPIO3,
-		.end	= INT_GPIO3,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[4] = {
-		.start	= INT_GPIO4,
-		.end	= INT_GPIO4,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[5] = {
-		.start	= INT_GPIO5,
-		.end	= INT_GPIO5,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[6] = {
-		.start	= INT_GPIO6,
-		.end	= INT_GPIO6,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[7] = {
-		.start	= INT_GPIO7,
-		.end	= INT_GPIO7,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device tegra_gpio_device = {
-	.name		= "tegra-gpio",
-	.id		= -1,
-	.resource	= gpio_resource,
-	.num_resources	= ARRAY_SIZE(gpio_resource),
-};
-
-static struct resource pinmux_resource[] = {
-	[0] = {
-		/* Tri-state registers */
-		.start	= TEGRA_APB_MISC_BASE + 0x14,
-		.end	= TEGRA_APB_MISC_BASE + 0x20 + 3,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		/* Mux registers */
-		.start	= TEGRA_APB_MISC_BASE + 0x80,
-		.end	= TEGRA_APB_MISC_BASE + 0x9c + 3,
-		.flags	= IORESOURCE_MEM,
-	},
-	[2] = {
-		/* Pull-up/down registers */
-		.start	= TEGRA_APB_MISC_BASE + 0xa0,
-		.end	= TEGRA_APB_MISC_BASE + 0xb0 + 3,
-		.flags	= IORESOURCE_MEM,
-	},
-	[3] = {
-		/* Pad control registers */
-		.start	= TEGRA_APB_MISC_BASE + 0x868,
-		.end	= TEGRA_APB_MISC_BASE + 0x90c + 3,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-struct platform_device tegra_pinmux_device = {
-	.name		= "tegra20-pinctrl",
-	.id		= -1,
-	.resource	= pinmux_resource,
-	.num_resources	= ARRAY_SIZE(pinmux_resource),
-};
-
-static struct resource i2c_resource1[] = {
-	[0] = {
-		.start	= INT_I2C,
-		.end	= INT_I2C,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_I2C_BASE,
-		.end	= TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource i2c_resource2[] = {
-	[0] = {
-		.start	= INT_I2C2,
-		.end	= INT_I2C2,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_I2C2_BASE,
-		.end	= TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource i2c_resource3[] = {
-	[0] = {
-		.start	= INT_I2C3,
-		.end	= INT_I2C3,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_I2C3_BASE,
-		.end	= TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource i2c_resource4[] = {
-	[0] = {
-		.start	= INT_DVC,
-		.end	= INT_DVC,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_DVC_BASE,
-		.end	= TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
-	.bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
-	.bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
-	.bus_clk_rate   = 400000,
-};
-
-static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
-	.bus_clk_rate   = 400000,
-};
-
-struct platform_device tegra_i2c_device1 = {
-	.name		= "tegra-i2c",
-	.id		= 0,
-	.resource	= i2c_resource1,
-	.num_resources	= ARRAY_SIZE(i2c_resource1),
-	.dev = {
-		.platform_data = &tegra_i2c1_platform_data,
-	},
-};
-
-struct platform_device tegra_i2c_device2 = {
-	.name		= "tegra-i2c",
-	.id		= 1,
-	.resource	= i2c_resource2,
-	.num_resources	= ARRAY_SIZE(i2c_resource2),
-	.dev = {
-		.platform_data = &tegra_i2c2_platform_data,
-	},
-};
-
-struct platform_device tegra_i2c_device3 = {
-	.name		= "tegra-i2c",
-	.id		= 2,
-	.resource	= i2c_resource3,
-	.num_resources	= ARRAY_SIZE(i2c_resource3),
-	.dev = {
-		.platform_data = &tegra_i2c3_platform_data,
-	},
-};
-
-struct platform_device tegra_i2c_device4 = {
-	.name		= "tegra-i2c",
-	.id		= 3,
-	.resource	= i2c_resource4,
-	.num_resources	= ARRAY_SIZE(i2c_resource4),
-	.dev = {
-		.platform_data = &tegra_dvc_platform_data,
-	},
-};
-
-static struct resource spi_resource1[] = {
-	[0] = {
-		.start	= INT_S_LINK1,
-		.end	= INT_S_LINK1,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SPI1_BASE,
-		.end	= TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource spi_resource2[] = {
-	[0] = {
-		.start	= INT_SPI_2,
-		.end	= INT_SPI_2,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SPI2_BASE,
-		.end	= TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource spi_resource3[] = {
-	[0] = {
-		.start	= INT_SPI_3,
-		.end	= INT_SPI_3,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SPI3_BASE,
-		.end	= TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource spi_resource4[] = {
-	[0] = {
-		.start	= INT_SPI_4,
-		.end	= INT_SPI_4,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SPI4_BASE,
-		.end	= TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-struct platform_device tegra_spi_device1 = {
-	.name		= "spi_tegra",
-	.id		= 0,
-	.resource	= spi_resource1,
-	.num_resources	= ARRAY_SIZE(spi_resource1),
-	.dev		= {
-		.coherent_dma_mask	= 0xffffffff,
-	},
-};
-
-struct platform_device tegra_spi_device2 = {
-	.name		= "spi_tegra",
-	.id		= 1,
-	.resource	= spi_resource2,
-	.num_resources	= ARRAY_SIZE(spi_resource2),
-	.dev		= {
-		.coherent_dma_mask	= 0xffffffff,
-	},
-};
-
-struct platform_device tegra_spi_device3 = {
-	.name		= "spi_tegra",
-	.id		= 2,
-	.resource	= spi_resource3,
-	.num_resources	= ARRAY_SIZE(spi_resource3),
-	.dev		= {
-		.coherent_dma_mask	= 0xffffffff,
-	},
-};
-
-struct platform_device tegra_spi_device4 = {
-	.name		= "spi_tegra",
-	.id		= 3,
-	.resource	= spi_resource4,
-	.num_resources	= ARRAY_SIZE(spi_resource4),
-	.dev		= {
-		.coherent_dma_mask	= 0xffffffff,
-	},
-};
-
-
-static struct resource sdhci_resource1[] = {
-	[0] = {
-		.start	= INT_SDMMC1,
-		.end	= INT_SDMMC1,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SDMMC1_BASE,
-		.end	= TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource sdhci_resource2[] = {
-	[0] = {
-		.start	= INT_SDMMC2,
-		.end	= INT_SDMMC2,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SDMMC2_BASE,
-		.end	= TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource sdhci_resource3[] = {
-	[0] = {
-		.start	= INT_SDMMC3,
-		.end	= INT_SDMMC3,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SDMMC3_BASE,
-		.end	= TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct resource sdhci_resource4[] = {
-	[0] = {
-		.start	= INT_SDMMC4,
-		.end	= INT_SDMMC4,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= TEGRA_SDMMC4_BASE,
-		.end	= TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-/* board files should fill in platform_data register the devices themselvs.
- * See board-harmony.c for an example
- */
-struct platform_device tegra_sdhci_device1 = {
-	.name		= "sdhci-tegra",
-	.id		= 0,
-	.resource	= sdhci_resource1,
-	.num_resources	= ARRAY_SIZE(sdhci_resource1),
-};
-
-struct platform_device tegra_sdhci_device2 = {
-	.name		= "sdhci-tegra",
-	.id		= 1,
-	.resource	= sdhci_resource2,
-	.num_resources	= ARRAY_SIZE(sdhci_resource2),
-};
-
-struct platform_device tegra_sdhci_device3 = {
-	.name		= "sdhci-tegra",
-	.id		= 2,
-	.resource	= sdhci_resource3,
-	.num_resources	= ARRAY_SIZE(sdhci_resource3),
-};
-
-struct platform_device tegra_sdhci_device4 = {
-	.name		= "sdhci-tegra",
-	.id		= 3,
-	.resource	= sdhci_resource4,
-	.num_resources	= ARRAY_SIZE(sdhci_resource4),
-};
-
-static struct resource tegra_usb1_resources[] = {
-	[0] = {
-		.start	= TEGRA_USB_BASE,
-		.end	= TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_USB,
-		.end	= INT_USB,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_usb2_resources[] = {
-	[0] = {
-		.start	= TEGRA_USB2_BASE,
-		.end	= TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_USB2,
-		.end	= INT_USB2,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_usb3_resources[] = {
-	[0] = {
-		.start	= TEGRA_USB3_BASE,
-		.end	= TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_USB3,
-		.end	= INT_USB3,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-	.reset_gpio = -1,
-	.clk = "cdev2",
-};
-
-struct tegra_ehci_platform_data tegra_ehci1_pdata = {
-	.operating_mode = TEGRA_USB_OTG,
-	.power_down_on_bus_suspend = 1,
-	.vbus_gpio = -1,
-};
-
-struct tegra_ehci_platform_data tegra_ehci2_pdata = {
-	.phy_config = &tegra_ehci2_ulpi_phy_config,
-	.operating_mode = TEGRA_USB_HOST,
-	.power_down_on_bus_suspend = 1,
-	.vbus_gpio = -1,
-};
-
-struct tegra_ehci_platform_data tegra_ehci3_pdata = {
-	.operating_mode = TEGRA_USB_HOST,
-	.power_down_on_bus_suspend = 1,
-	.vbus_gpio = -1,
-};
-
-static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device tegra_ehci1_device = {
-	.name	= "tegra-ehci",
-	.id	= 0,
-	.dev	= {
-		.dma_mask	= &tegra_ehci_dmamask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci1_pdata,
-	},
-	.resource = tegra_usb1_resources,
-	.num_resources = ARRAY_SIZE(tegra_usb1_resources),
-};
-
-struct platform_device tegra_ehci2_device = {
-	.name	= "tegra-ehci",
-	.id	= 1,
-	.dev	= {
-		.dma_mask	= &tegra_ehci_dmamask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci2_pdata,
-	},
-	.resource = tegra_usb2_resources,
-	.num_resources = ARRAY_SIZE(tegra_usb2_resources),
-};
-
-struct platform_device tegra_ehci3_device = {
-	.name	= "tegra-ehci",
-	.id	= 2,
-	.dev	= {
-		.dma_mask	= &tegra_ehci_dmamask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-		.platform_data = &tegra_ehci3_pdata,
-	},
-	.resource = tegra_usb3_resources,
-	.num_resources = ARRAY_SIZE(tegra_usb3_resources),
-};
-
-static struct resource tegra_pmu_resources[] = {
-	[0] = {
-		.start	= INT_CPU0_PMU_INTR,
-		.end	= INT_CPU0_PMU_INTR,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[1] = {
-		.start	= INT_CPU1_PMU_INTR,
-		.end	= INT_CPU1_PMU_INTR,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device tegra_pmu_device = {
-	.name		= "arm-pmu",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(tegra_pmu_resources),
-	.resource	= tegra_pmu_resources,
-};
-
-static struct resource tegra_uarta_resources[] = {
-	[0] = {
-		.start	= TEGRA_UARTA_BASE,
-		.end	= TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_UARTA,
-		.end	= INT_UARTA,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_uartb_resources[] = {
-	[0] = {
-		.start	= TEGRA_UARTB_BASE,
-		.end	= TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_UARTB,
-		.end	= INT_UARTB,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_uartc_resources[] = {
-	[0] = {
-		.start	= TEGRA_UARTC_BASE,
-		.end	= TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_UARTC,
-		.end	= INT_UARTC,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_uartd_resources[] = {
-	[0] = {
-		.start	= TEGRA_UARTD_BASE,
-		.end	= TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_UARTD,
-		.end	= INT_UARTD,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct resource tegra_uarte_resources[] = {
-	[0] = {
-		.start	= TEGRA_UARTE_BASE,
-		.end	= TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= INT_UARTE,
-		.end	= INT_UARTE,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device tegra_uarta_device = {
-	.name	= "tegra_uart",
-	.id	= 0,
-	.num_resources	= ARRAY_SIZE(tegra_uarta_resources),
-	.resource	= tegra_uarta_resources,
-	.dev	= {
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device tegra_uartb_device = {
-	.name	= "tegra_uart",
-	.id	= 1,
-	.num_resources	= ARRAY_SIZE(tegra_uartb_resources),
-	.resource	= tegra_uartb_resources,
-	.dev	= {
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device tegra_uartc_device = {
-	.name	= "tegra_uart",
-	.id	= 2,
-	.num_resources	= ARRAY_SIZE(tegra_uartc_resources),
-	.resource	= tegra_uartc_resources,
-	.dev	= {
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device tegra_uartd_device = {
-	.name	= "tegra_uart",
-	.id	= 3,
-	.num_resources	= ARRAY_SIZE(tegra_uartd_resources),
-	.resource	= tegra_uartd_resources,
-	.dev	= {
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-struct platform_device tegra_uarte_device = {
-	.name	= "tegra_uart",
-	.id	= 4,
-	.num_resources	= ARRAY_SIZE(tegra_uarte_resources),
-	.resource	= tegra_uarte_resources,
-	.dev	= {
-		.coherent_dma_mask	= DMA_BIT_MASK(32),
-	},
-};
-
-static struct resource i2s_resource1[] = {
-	[0] = {
-		.start	= INT_I2S1,
-		.end	= INT_I2S1,
-		.flags	= IORESOURCE_IRQ
-	},
-	[1] = {
-		.start	= TEGRA_DMA_REQ_SEL_I2S_1,
-		.end	= TEGRA_DMA_REQ_SEL_I2S_1,
-		.flags	= IORESOURCE_DMA
-	},
-	[2] = {
-		.start	= TEGRA_I2S1_BASE,
-		.end	= TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
-		.flags	= IORESOURCE_MEM
-	}
-};
-
-static struct resource i2s_resource2[] = {
-	[0] = {
-		.start	= INT_I2S2,
-		.end	= INT_I2S2,
-		.flags	= IORESOURCE_IRQ
-	},
-	[1] = {
-		.start	= TEGRA_DMA_REQ_SEL_I2S2_1,
-		.end	= TEGRA_DMA_REQ_SEL_I2S2_1,
-		.flags	= IORESOURCE_DMA
-	},
-	[2] = {
-		.start	= TEGRA_I2S2_BASE,
-		.end	= TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
-		.flags	= IORESOURCE_MEM
-	}
-};
-
-struct platform_device tegra_i2s_device1 = {
-	.name		= "tegra20-i2s",
-	.id		= 0,
-	.resource	= i2s_resource1,
-	.num_resources	= ARRAY_SIZE(i2s_resource1),
-};
-
-struct platform_device tegra_i2s_device2 = {
-	.name		= "tegra20-i2s",
-	.id		= 1,
-	.resource	= i2s_resource2,
-	.num_resources	= ARRAY_SIZE(i2s_resource2),
-};
-
-static struct resource tegra_das_resources[] = {
-	[0] = {
-		.start = TEGRA_APB_MISC_DAS_BASE,
-		.end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-struct platform_device tegra_das_device = {
-	.name		= "tegra20-das",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(tegra_das_resources),
-	.resource	= tegra_das_resources,
-};
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
deleted file mode 100644
index 4f50527..0000000
--- a/arch/arm/mach-tegra/devices.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2010,2011 Google, Inc.
- *
- * Author:
- *	Colin Cross <ccross at android.com>
- *	Erik Gilling <ccross at android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_DEVICES_H
-#define __MACH_TEGRA_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <mach/usb_phy.h>
-
-extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
-
-extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
-extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
-
-extern struct platform_device tegra_gpio_device;
-extern struct platform_device tegra_pinmux_device;
-extern struct platform_device tegra_sdhci_device1;
-extern struct platform_device tegra_sdhci_device2;
-extern struct platform_device tegra_sdhci_device3;
-extern struct platform_device tegra_sdhci_device4;
-extern struct platform_device tegra_i2c_device1;
-extern struct platform_device tegra_i2c_device2;
-extern struct platform_device tegra_i2c_device3;
-extern struct platform_device tegra_i2c_device4;
-extern struct platform_device tegra_spi_device1;
-extern struct platform_device tegra_spi_device2;
-extern struct platform_device tegra_spi_device3;
-extern struct platform_device tegra_spi_device4;
-extern struct platform_device tegra_ehci1_device;
-extern struct platform_device tegra_ehci2_device;
-extern struct platform_device tegra_ehci3_device;
-extern struct platform_device tegra_uarta_device;
-extern struct platform_device tegra_uartb_device;
-extern struct platform_device tegra_uartc_device;
-extern struct platform_device tegra_uartd_device;
-extern struct platform_device tegra_uarte_device;
-extern struct platform_device tegra_pmu_device;
-extern struct platform_device tegra_i2s_device1;
-extern struct platform_device tegra_i2s_device2;
-extern struct platform_device tegra_das_device;
-
-#endif
-- 
1.7.9.5



From s.hauer at pengutronix.de  Tue Aug 28 03:37:44 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 09:37:44 +0200
Subject: [PATCH] pwm-imx: Fix config / enable / disable
In-Reply-To: <1305545087.2775440.1345755837651.JavaMail.root@advansee.com>
References: <20120823191108.GB8127@avionic-0098.mockup.avionic-design.de>
 <1305545087.2775440.1345755837651.JavaMail.root@advansee.com>
Message-ID: <20120828073744.GU26594@pengutronix.de>

On Thu, Aug 23, 2012 at 11:03:57PM +0200, Beno?t Th?baudeau wrote:
> imx_pwm_config() did not enable the PWM IP clock while accessing the registers.
> Hence, a call to pwm_config() had no effect before pwm_enable() had been called,
> which does not comply to the PWM API.
> 
> Moreover, calling pwm_disable() then pwm_enable() must be a transparent
> operation.
> 
> This fixes the first setting of brightness through sysfs that had no effect with
> leds-pwm.

I don't really like this patch. I'd like to have this one first, it
makes further cleanups easier:

https://lkml.org/lkml/2012/8/28/24

Simililarly, we should probably introduce a imx_pwm_[en|dis]able_v[12]

Then, the pwm core already makes sure that pwm_enable/disable are called
only once, so the if (imx->clk_enabled) in pwm_enable/disable is
unnecessary.

Sascha

> 
> Cc: Thierry Reding <thierry.reding at avionic-design.de>
> Cc: <linux-kernel at vger.kernel.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: <linux-arm-kernel at lists.infradead.org>
> Cc: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau at advansee.com>
> ---
>  .../drivers/pwm/pwm-imx.c                          |   55 +++++++++++++++-----
>  1 file changed, 43 insertions(+), 12 deletions(-)
> 
> diff --git linux-next-c94456b.orig/drivers/pwm/pwm-imx.c linux-next-c94456b/drivers/pwm/pwm-imx.c
> index 2a0b353..0519bf2 100644
> --- linux-next-c94456b.orig/drivers/pwm/pwm-imx.c
> +++ linux-next-c94456b/drivers/pwm/pwm-imx.c
> @@ -55,6 +55,16 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  {
>  	struct imx_chip *imx = to_imx_chip(chip);
>  
> +	/*
> +	 * If the PWM is disabled, make sure to turn on the clock before
> +	 * accessing the registers.
> +	 */
> +	if (!imx->clk_enabled) {
> +		int rc = clk_prepare_enable(imx->clk);
> +		if (rc)
> +			return rc;
> +	}
> +
>  	if (!(cpu_is_mx1() || cpu_is_mx21())) {
>  		unsigned long long c;
>  		unsigned long period_cycles, duty_cycles, prescale;
> @@ -85,8 +95,11 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
>  
>  		cr = MX3_PWMCR_PRESCALER(prescale) |
> -			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
> -			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
> +			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN;
> +
> +		/* If the PWM is enabled, keep it so. */
> +		if (imx->clk_enabled)
> +			cr |= MX3_PWMCR_EN;
>  
>  		if (cpu_is_mx25())
>  			cr |= MX3_PWMCR_CLKSRC_IPG;
> @@ -118,32 +131,50 @@ static int imx_pwm_config(struct pwm_chip *chip,
>  		BUG();
>  	}
>  
> +	/* If the PWM is disabled, turn the clock off again to save power. */
> +	if (!imx->clk_enabled)
> +		clk_disable_unprepare(imx->clk);
> +
>  	return 0;
>  }
>  
>  static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
>  	struct imx_chip *imx = to_imx_chip(chip);
> -	int rc = 0;
> +	int rc;
>  
> -	if (!imx->clk_enabled) {
> -		rc = clk_prepare_enable(imx->clk);
> -		if (!rc)
> -			imx->clk_enabled = 1;
> +	if (imx->clk_enabled)
> +		return 0;
> +
> +	rc = clk_prepare_enable(imx->clk);
> +	if (rc)
> +		return rc;
> +
> +	if (!(cpu_is_mx1() || cpu_is_mx21())) {
> +		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
> +		cr |= MX3_PWMCR_EN;
> +		writel(cr, imx->mmio_base + MX3_PWMCR);
>  	}
> -	return rc;
> +
> +	imx->clk_enabled = 1;
> +	return 0;
>  }
>  
>  static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
>  	struct imx_chip *imx = to_imx_chip(chip);
>  
> -	writel(0, imx->mmio_base + MX3_PWMCR);
> +	if (!imx->clk_enabled)
> +		return;
>  
> -	if (imx->clk_enabled) {
> -		clk_disable_unprepare(imx->clk);
> -		imx->clk_enabled = 0;
> +	if (!(cpu_is_mx1() || cpu_is_mx21())) {
> +		u32 cr = readl(imx->mmio_base + MX3_PWMCR);
> +		cr &= ~MX3_PWMCR_EN;
> +		writel(cr, imx->mmio_base + MX3_PWMCR);
>  	}
> +
> +	clk_disable_unprepare(imx->clk);
> +	imx->clk_enabled = 0;
>  }
>  
>  static struct pwm_ops imx_pwm_ops = {
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 03:45:33 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 09:45:33 +0200
Subject: [PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <1345385346-25412-1-git-send-email-festevam@gmail.com>
References: <1345385346-25412-1-git-send-email-festevam@gmail.com>
Message-ID: <20120828074533.GV26594@pengutronix.de>

On Sun, Aug 19, 2012 at 11:09:05AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied and added stable tag (I assume this should go to stable, right?)

Sascha

> ---
>  arch/arm/mach-imx/clk-imx35.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index c6422fb..f7910df 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -230,10 +230,8 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.1");
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 03:45:51 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 09:45:51 +0200
Subject: [PATCH v2 2/2] ARM: clk-imx25: Fix SSI clock registration
In-Reply-To: <1345395959-26978-1-git-send-email-festevam@gmail.com>
References: <1345395959-26978-1-git-send-email-festevam@gmail.com>
Message-ID: <20120828074551.GW26594@pengutronix.de>

On Sun, Aug 19, 2012 at 02:05:59PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied and also added stable tag.

Sascha

> ---
> Changes since v1:
> - Use imx-ssi.1 for ssi2_ipg
> 
>  arch/arm/mach-imx/clk-imx25.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
> index fdd8cc8..5ff9534 100644
> --- a/arch/arm/mach-imx/clk-imx25.c
> +++ b/arch/arm/mach-imx/clk-imx25.c
> @@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
>  	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
>  	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
>  	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
> -	clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
>  	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
>  	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
>  	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 03:47:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 09:47:10 +0200
Subject: [PATCH v3] Visstrim SM10: Use mo_version to decide board video
 mode.
In-Reply-To: <1345457581-13837-1-git-send-email-javier.martin@vista-silicon.com>
References: <1345457581-13837-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120828074710.GX26594@pengutronix.de>

On Mon, Aug 20, 2012 at 12:13:01PM +0200, Javier Martin wrote:
> If the mother board version number is odd, emmaprp() for
> format conversion + UVC camera will be used.
> 
> Otherwise mx2_camera and m2m-deinterlacer will be registered.
> 
> For both cases Coda video codec is registered.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

> ---
> This patch should go through the media-tree because it depends on the following
> patches that have already made through it:
> 
>  [PATCH v2 3/3] Visstrim M10: Add support for Coda. 
>  [PATCH 2/2] i.MX27: Visstrim_M10: Add support for deinterlacing driver. 
> 
> For this reason I've added Mauro to CC and I will need Sascha's ACK.
> 
> Changes since v2:
> - Remove redundant 'return' pointed out by Baruch.
> ---
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   52 ++++++++++++++++++++++++---
>  1 file changed, 47 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index 176533e..1d6830f 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -49,6 +49,10 @@
>  #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
>  #define SDHC1_IRQ IRQ_GPIOB(25)
>  
> +#define VERSION_MASK		0x7
> +#define MOTHERBOARD_SHIFT	4
> +#define EXPBOARD_SHIFT		0
> +
>  #define MOTHERBOARD_BIT2	(GPIO_PORTD + 31)
>  #define MOTHERBOARD_BIT1	(GPIO_PORTD + 30)
>  #define MOTHERBOARD_BIT0	(GPIO_PORTD + 29)
> @@ -205,7 +209,7 @@ static struct mx2_camera_platform_data visstrim_camera = {
>  static phys_addr_t mx2_camera_base __initdata;
>  #define MX2_CAMERA_BUF_SIZE SZ_8M
>  
> -static void __init visstrim_camera_init(void)
> +static void __init visstrim_analog_camera_init(void)
>  {
>  	struct platform_device *pdev;
>  	int dma;
> @@ -442,6 +446,27 @@ static void __init visstrim_deinterlace_init(void)
>  		return;
>  }
>  
> +/* Emma-PrP for format conversion */
> +static void __init visstrim_emmaprp_init(void)
> +{
> +	struct platform_device *pdev;
> +	int dma;
> +
> +	pdev = imx27_add_mx2_emmaprp();
> +	if (IS_ERR(pdev))
> +		return;
> +
> +	/*
> +	 * Use the same memory area as the analog camera since both
> +	 * devices are, by nature, exclusive.
> +	 */
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +				mx2_camera_base, mx2_camera_base,
> +				MX2_CAMERA_BUF_SIZE,
> +				DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +	if (!(dma & DMA_MEMORY_MAP))
> +		pr_err("Failed to declare memory for emmaprp\n");
> +}
>  
>  static void __init visstrim_m10_revision(void)
>  {
> @@ -467,13 +492,14 @@ static void __init visstrim_m10_revision(void)
>  	mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
>  
>  	system_rev = 0x27000;
> -	system_rev |= (mo_version << 4);
> -	system_rev |= exp_version;
> +	system_rev |= (mo_version << MOTHERBOARD_SHIFT);
> +	system_rev |= (exp_version << EXPBOARD_SHIFT);
>  }
>  
>  static void __init visstrim_m10_board_init(void)
>  {
>  	int ret;
> +	int mo_version;
>  
>  	imx27_soc_init();
>  	visstrim_m10_revision();
> @@ -505,8 +531,24 @@ static void __init visstrim_m10_board_init(void)
>  	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
>  				      &iclink_tvp5150, sizeof(iclink_tvp5150));
>  	gpio_led_register_device(0, &visstrim_m10_led_data);
> -	visstrim_deinterlace_init();
> -	visstrim_camera_init();
> +
> +	/* Use mother board version to decide what video devices we shall use */
> +	mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
> +	if (mo_version & 0x1) {
> +		visstrim_emmaprp_init();
> +
> +		/*
> +		 * Despite not being used, tvp5150 must be
> +		 * powered on to avoid I2C problems. To minimize
> +		 * power consupmtion keep reset enabled.
> +		 */
> +		gpio_set_value(TVP5150_PWDN, 1);
> +		ndelay(1);
> +		gpio_set_value(TVP5150_RSTN, 0);
> +	} else {
> +		visstrim_deinterlace_init();
> +		visstrim_analog_camera_init();
> +	}
>  	visstrim_coda_init();
>  }
>  
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From lee.jones at linaro.org  Tue Aug 28 03:48:19 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 Aug 2012 08:48:19 +0100
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <CACRpkdZRJ1yX-o8-NUuMzXMz5ebbp=H21Xa6JMy1y56Chq-T9g@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
 <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>
 <20120820080632.GD8450@gmail.com>
 <CACRpkdZRJ1yX-o8-NUuMzXMz5ebbp=H21Xa6JMy1y56Chq-T9g@mail.gmail.com>
Message-ID: <20120828074812.GA12957@gmail.com>

On Mon, Aug 27, 2012 at 04:07:58PM -0700, Linus Walleij wrote:
> On Mon, Aug 20, 2012 at 1:06 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Tue, Aug 14, 2012 at 01:13:49PM +0200, Linus Walleij wrote:
> >> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
> >>
> >> > We've done this before and it worked well last time. Here we're
> >> > duplicating a complex registration function to ease the process
> >> > of enabling it for Device Tree. As there are quite a few steps
> >> > taken during the registration process, it makes sense to break
> >> > them up into more manageable chunks. This patch will aid us.
> >> >
> >> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >>
> >> I understand you have used this approach before so:
> >> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> >
> > Does this comment take back your previous one:
> >
> > NOTE: it seems this patch set contains some churn. First you
> > add in the forked device init, put in a big chunk of code and
> > then in the *same* patch set delete it again. It's not like
> > we're dying to see all the development history... can this
> > be squashed down a bit?
> >
> > ... hence leave the patch-set as it is?
> 
> No. I just meant leave it like that for the devices outside of this
> set.
> 
> If you're adding and then removing *all* of them in this set,
> why add them in the first place?

So that there's no breakage during bisection.

You should be able to roll the kernel back in between each of these
patches and there to be full compatibility at each point. At least
that was the intention. Is that wrong?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From s.hauer at pengutronix.de  Tue Aug 28 03:49:57 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 09:49:57 +0200
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
References: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120828074957.GY26594@pengutronix.de>

On Mon, Aug 20, 2012 at 09:39:22AM -0300, Fabio Estevam wrote:
> SSI block has two types of clock:
> 
> ipg: bus clock, the clock needed for accessing registers.
> per: peripheral clock, the clock needed for generating the bit rate.
> 
> Currently SSI driver only supports slave mode and only need to handle
> the ipg clock, because the peripheral clock comes from the master codec.
> 
> Only register the ipg clock and do not register the peripheral clock for ssi.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Ok, used this version instead.

Sascha

> ---
> Changes since v1:
> - Use ssi2_gate for imx-ssi.1
> 
>  arch/arm/mach-imx/clk-imx35.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index c6422fb..f7910df 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -230,10 +230,8 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
> -	clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> -- 
> 1.7.9.5
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Aug 28 04:06:45 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 10:06:45 +0200
Subject: [PATCH] ARM: imx: fix imx51 babbage SD2 CD/WP
In-Reply-To: <1345779227-3700-1-git-send-email-shawn.guo@linaro.org>
References: <1345779227-3700-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120828080645.GA26594@pengutronix.de>

On Fri, Aug 24, 2012 at 11:33:47AM +0800, Shawn Guo wrote:
> Pads GPIO1_6 and GPIO1_5 are used as SD2 CD/WP on imx51 babbage board.
> Before commit 5d23b39 (ARM: i.MX51 iomux: add missed definitions for
> SION-bit and mode for some pads) gets in, we use the pad settings
> configured by bootloader with NO_PAD_CTRL and SD2 CD/WP just works.
> The commit changes the pad settings and causes SD2 CD/WP stop working.
> 
> Set up pads GPIO1_6 and GPIO1_5 in the configuation that bootloader
> uses on imx51 babbage board to fix the SD2 CD/WP regression.
> 
> Cc: <stable at vger.kernel.org>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

> ---
>  arch/arm/mach-imx/mach-mx51_babbage.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
> index 7b31cbd..83f49c4 100644
> --- a/arch/arm/mach-imx/mach-mx51_babbage.c
> +++ b/arch/arm/mach-imx/mach-mx51_babbage.c
> @@ -154,8 +154,8 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
>  	MX51_PAD_SD2_DATA2__SD2_DATA2,
>  	MX51_PAD_SD2_DATA3__SD2_DATA3,
>  	/* CD/WP gpio */
> -	MX51_PAD_GPIO1_6__GPIO1_6,
> -	MX51_PAD_GPIO1_5__GPIO1_5,
> +	NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
> +	NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
>  
>  	/* eCSPI1 */
>  	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
> -- 
> 1.7.5.4
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From lauri.hintsala at bluegiga.com  Tue Aug 28 04:08:24 2012
From: lauri.hintsala at bluegiga.com (Lauri Hintsala)
Date: Tue, 28 Aug 2012 11:08:24 +0300
Subject: [PATCH 0/2] mmc: mxs-mmc: fix deadlocks
In-Reply-To: <1342534570-8293-1-git-send-email-lauri.hintsala@bluegiga.com>
References: <1342534570-8293-1-git-send-email-lauri.hintsala@bluegiga.com>
Message-ID: <503C7C78.7080700@bluegiga.com>

On 07/17/2012 05:16 PM, Lauri Hintsala wrote:
> Two different deadlock fixes in cases with SDIO IRQs
> generated by SDIO device.

Any comments? Could they be applied?

BR,
Lauri


> Lauri Hintsala (2):
>    mmc: mxs-mmc: fix deadlock in SDIO IRQ case
>    mmc: mxs-mmc: fix deadlock caused by recursion loop
>
>   drivers/mmc/host/mxs-mmc.c |   14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
>


From 21cnbao at gmail.com  Tue Aug 28 04:08:38 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 Aug 2012 16:08:38 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4x4DdHsNgh7ArkD1fCHT22rxRs18vcobHtpSXJ-cq3o4Q@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210757.32852.arnd@arndb.de>
 <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
 <201208210920.52816.arnd@arndb.de>
 <CAGsJ_4x4DdHsNgh7ArkD1fCHT22rxRs18vcobHtpSXJ-cq3o4Q@mail.gmail.com>
Message-ID: <CAGsJ_4y3Snvf-2DLSrpU5+zmytkARtNxJN_nPdiOngd+BK-aDA@mail.gmail.com>

2012/8/28 Barry Song <21cnbao at gmail.com>:
> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
>> On Tuesday 21 August 2012, Barry Song wrote:
>>> then i add these to Kconfig.debug as it is a common way
>>>
>>>         config DEBUG_PRIMA2_UART1
>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
>>>                 depends on ARCH_PRIMA2
>>>                 help
>>>                   Say Y here if you want the debug print routines to direct
>>>                   their output to UART1 serial port on SiRFprimaII devices.
>>>
>>>         config DEBUG_MARCO_UART1
>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
>>>                 depends on ARCH_MARCO
>>>                 help
>>>                   Say Y here if you want the debug print routines to direct
>>>                   their output to UART1 serial port on SiRFmarco devices.
>>>
>>> and these in mach-prima2/include/mach/uart.h
>>>
>>>   #ifdef CONFIG_DEBUG_PRIMA2_UART1
>>>   #define SIRFSOC_UART1_PA_BASE          0xb0060000
>>>   #elif defined(CONFIG_DEBUG_MARCO_UART1)
>>>   #define SIRFSOC_UART1_PA_BASE          0xcc060000
>>>   #endif
>>>
>>> the above codes seem still ugly ?
>>>
>>
>> No, that's fine, about as a good as it gets with today's kernel
>> capabilities. Just fix the description to have the correct
>> SoC name instead of "DaVinci DA8XX" ;-)
>
> except the DEBUG_LL uart base address, i missed the zreladdr-y. for
> primaii, it is 0x00008000, for marco, it is 0x40008000 as marco's
> memory space begins from 0x4000000.
> i would to have AUTO_ZRELADDR for the whole SiRF series.
> but for uImage load address difference in uImage header, which blocks
> multiple SoCs from using same uImage, is "KERNEL_NOLOAD" uImage type
> the current generic solution?

also add Stephen Warren.

i have two verified ways to resolve this problem:

1. use "kernel noload", build uImage by:

make uImage UIMAGE_TYPE=kernel_noload
and add the following patch in kernel:

diff --git a/arch/arm/mach-prima2/Makefile.boot
b/arch/arm/mach-prima2/Makefile.boot
index 53c5225..059bcd7 100644
--- a/arch/arm/mach-prima2/Makefile.boot
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -1,12 +1,4 @@

-zreladdr-y             += 0x00008000
-params_phys-y          := 0x00000100
-initrd_phys-y          := 0x00800000
#we use kernel_noload uImage and AUTO_ZRELADDR
+zreladdr-y             += 0x0

2. don't use kernel's uImage target, mkimage uImage out of kernel by
giving mkimage the "-a 0x40008000" and keep kernel unchanged.

anyway, i think arm SoC needs a generic way to handle this kind of problem.

if we move to 1, i think almost all ARM SoCs don't need Makefile.boot again.

>
>>
>>         Arnd
>
> -barry

-barry


From anilkumar at ti.com  Tue Aug 28 04:10:52 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 28 Aug 2012 13:40:52 +0530
Subject: [PATCH RESEND v4 1/3] arm/dts: AM33XX: Add basic pinctrl device tree
 data
In-Reply-To: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346141454-18786-2-git-send-email-anilkumar@ti.com>

Adds basic pinctrl device tree data for AM33XX family of devices.
This patch is based on the pinctrl-single driver.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dde76f7..dfe9c559 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -40,6 +40,15 @@
 		};
 	};
 
+	am3358_pinmux: pinmux at 44E10800 {
+		compatible = "pinctrl-single";
+		reg = <0x44E10800 0x0238>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7F>;
+	};
+
 	/*
 	 * XXX: Use a flat representation of the AM33XX interconnect.
 	 * The real AM33XX interconnect network is quite complex.Since
-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 28 04:10:51 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 28 Aug 2012 13:40:51 +0530
Subject: [PATCH v4 0/3] Add device tree data for AM33XX devices
Message-ID: <1346141454-18786-1-git-send-email-anilkumar@ti.com>

Add pinctrl and d_can device tree data to AM33XX family of devices.
First two patches add support for pinctrl DT data and third one
adds dcan DT data.

Reason behind combining these patches is to apply cleanly on
linux-omap tree, because these are sequential patches.

These patches were tested on AM335x-Bone and AM335x-EVM apply
on linux-omap:master

d_can:
  Changes from v3:
	- Removed d_can1 node from am335x-evm.dts file. Instance
	  one of CAN (d_can1) is available on AM335x-EVM only under
	  a specific CPLD mode selection. am335x-evm.dts does not
          support this mode so remove the d_can1 node.
	- Dropped d_can pinmux settings patch, above comment
	  applies here as well.

  Changes from v2:
	- Incorporated Vaibhav H's comments on v2
	  * Added dcan0 instances to am33xx.dtsi file

  Changes from v1:
	- These two patches separated from c_can DT support
	  patch series.

pinctrl:
  Changes from v3:
	- Updated the reg length based on latest AM335x TRM.

  Changes from v2:
	- user led pinmux comments updated according to Tony's
	  comment.

  Changes from v1:
	- Rebased the patches based on latest pinctrl-single driver

AnilKumar Ch (3):
  arm/dts: AM33XX: Add basic pinctrl device tree data
  arm/dts: AM33XX: Configure pinmuxs for user leds control on Bone
  arm/dts: AM33XX: Add D_CAN device tree data

 arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi     |   27 +++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 28 04:10:54 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 28 Aug 2012 13:40:54 +0530
Subject: [PATCH v4 3/3] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346141454-18786-4-git-send-email-anilkumar@ti.com>

Add Bosch D_CAN controller device tree data to AM33XX dtsi
file by adding d_can device nodes with all the necessary
parameters.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index dfe9c559..d965137 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -177,5 +177,23 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		dcan0: d_can at 481CC000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			reg = <0x481CC000 0x2000>;
+			interrupts = <52>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		dcan1: d_can at 481D0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			reg = <0x481D0000 0x2000>;
+			interrupts = <55>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.7.9.5



From anilkumar at ti.com  Tue Aug 28 04:10:53 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Tue, 28 Aug 2012 13:40:53 +0530
Subject: [PATCH RESEND v4 2/3] arm/dts: AM33XX: Configure pinmuxs for user
 leds control on Bone
In-Reply-To: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346141454-18786-3-git-send-email-anilkumar@ti.com>

Adds GPIO pinctrl nodes to am3358_pinmux master node to control
user leds (USR0, USR1, USR2 and USR3) present on BeagleBone.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a7906cb..58f5042 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -18,6 +18,20 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
+	am3358_pinmux: pinmux at 44E10800 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&userled_pins>;
+
+		userled_pins: pinmux_userled_pins {
+			pinctrl-single,pins = <
+				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+				0x5C 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+			>;
+		};
+	};
+
 	ocp {
 		uart1: serial at 44E09000 {
 			status = "okay";
-- 
1.7.9.5



From thomas.abraham at linaro.org  Tue Aug 28 04:15:47 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 13:45:47 +0530
Subject: [PATCH] ARM: Exynos4: Turn off clocks for NAND,
 OneNAND and TSI controllers
In-Reply-To: <1345819936-6503-1-git-send-email-chander.kashyap@linaro.org>
References: <1345819936-6503-1-git-send-email-chander.kashyap@linaro.org>
Message-ID: <CAJuYYwSFMR1cJm7SB-eF_aYM9SPMaopvw3K9stiPvabCfjH=QA@mail.gmail.com>

On 24 August 2012 20:22, Chander Kashyap <chander.kashyap at linaro.org> wrote:
> The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
> controllers could be either enabled or disabled at boot. To ensure
> that these are turned off until used, add them to the list of clocks
> to be turned off during boot.
>
> Signed-off-by: Chander Kashyap <chander.kashyap at linaro.org>
> ---
>  arch/arm/mach-exynos/clock-exynos4.c |   12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
> index 2f51293..7cc5491 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
>                 .enable         = exynos4_clk_ip_cam_ctrl,
>                 .ctrlbit        = (1 << 3),
>         }, {
> +               .name           = "tsi",
> +               .enable         = exynos4_clk_ip_fsys_ctrl,
> +               .ctrlbit        = (1 << 4),
> +       }, {
>                 .name           = "hsmmc",
>                 .devname        = "exynos4-sdhci.0",
>                 .parent         = &exynos4_clk_aclk_133.clk,
> @@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
>                 .enable         = exynos4_clk_ip_fsys_ctrl,
>                 .ctrlbit        = (1 << 9),
>         }, {
> +               .name           = "onenand",
> +               .enable         = exynos4_clk_ip_fsys_ctrl,
> +               .ctrlbit        = (1 << 15),
> +       }, {
> +               .name           = "nfcon",
> +               .enable         = exynos4_clk_ip_fsys_ctrl,
> +               .ctrlbit        = (1 << 16),
> +       }, {
>                 .name           = "dac",
>                 .devname        = "s5p-sdo",
>                 .enable         = exynos4_clk_ip_tv_ctrl,
> --
> 1.7.9.5

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From alexander.shishkin at linux.intel.com  Tue Aug 28 04:29:35 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Tue, 28 Aug 2012 11:29:35 +0300
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
Message-ID: <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> States in gadget are not needed any more, set it to zero.

It's generally a good practice to mention in the commit message what is
it that you are fixing with this patch.

> Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> ---
>  drivers/usb/chipidea/udc.c |    1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index c7a032a..9fb6394 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -1746,6 +1746,7 @@ free_pools:
>  	dma_pool_destroy(ci->td_pool);
>  free_qh_pool:
>  	dma_pool_destroy(ci->qh_pool);
> +	memset(&ci->gadget, 0, sizeof(ci->gadget));

I understand that you're probably hitting "kobject already initialized"
warning here, but I think the real problem is that this function gets
called twice and fails the first time. Why does that happen?

In any case, please elaborate on the problem.

Regards,
--
Alex


From alexander.shishkin at linux.intel.com  Tue Aug 28 04:38:23 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Tue, 28 Aug 2012 11:38:23 +0300
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
Message-ID: <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> One role failed, but the other role will possiblly still work.
> For example, when udc start failed, if plug in a host device,
> it works.

If you're a host device, ci->role should be HOST at this point and
ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
role detection must be fixed. If ci_role_start() fails for host, but it
still works when it's called again after the id pin change is detected,
again, the problem is elsewhere.

>
> Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> ---
>  drivers/usb/chipidea/core.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index 19ef324..8fd390a 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
>  	ret = ci_role_start(ci, ci->role);
>  	if (ret) {
>  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
> -		ret = -ENODEV;
> -		goto rm_wq;
> +		ci->role = CI_ROLE_END;

So are you relying on id pin interrupt for initializing the role after
this? Can you provide more details?

Regards,
--
Alex


From kmpark at infradead.org  Tue Aug 28 04:39:39 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Tue, 28 Aug 2012 17:39:39 +0900
Subject: [PATCH v5 2/2] ARM: EXYNOS: SMC instruction (aka firmware) support
In-Reply-To: <20120827221030.GC7431@lumpy>
References: <20120824083357.GA25384@july>
	<20120827221030.GC7431@lumpy>
Message-ID: <CAH9JG2V5Xt1H5siBKT=LBr76YdSBRqyM92pTNFVo9K4WRWxcyA@mail.gmail.com>

On 8/28/12, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> See below.
>
> On Fri, Aug 24, 2012 at 05:33:57PM +0900, Kyungmin Park wrote:
>
>> diff --git a/arch/arm/mach-exynos/Makefile
>> b/arch/arm/mach-exynos/Makefile
>> index 9b58024..8ee779c 100644
>> --- a/arch/arm/mach-exynos/Makefile
>> +++ b/arch/arm/mach-exynos/Makefile
>> @@ -30,6 +30,11 @@ obj-$(CONFIG_EXYNOS4_MCT)	+= mct.o
>>
>>  obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
>>
>> +obj-$(CONFIG_ARM_FIRMWARE)	+= exynos-smc.o firmware.o
>> +
>> +plus_sec := $(call as-instr,.arch_extension sec,+sec)
>> +AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
>
> Again, no need for a config option here.
checked, I just did as others, omap3, highbank.
BTW, does it be required for older toolchain?
>
>> diff --git a/arch/arm/mach-exynos/firmware.c
>> b/arch/arm/mach-exynos/firmware.c
>> new file mode 100644
>> index 0000000..a144593
>> --- /dev/null
>> +++ b/arch/arm/mach-exynos/firmware.c
>> @@ -0,0 +1,37 @@
>> +/*
>> + *  Copyright (C) 2012 Samsung Electronics.
>> + *  Kyungmin Park <kyungmin.park at samsung.com>
>> + *
>> + * This program is free software,you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +
>> +#include <asm/firmware.h>
>> +
>> +#include "smc.h"
>> +
>> +static int exynos_do_idle(void)
>> +{
>> +        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
>> +        return 0;
>> +}
>> +
>> +static void exynos_cpu_boot(int cpu)
>> +{
>> +	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>> +}
>> +
>> +static struct firmware_ops exynos_firmware_ops __initdata = {
>> +	.do_idle	= exynos_do_idle,
>> +	.cpu_boot	= exynos_cpu_boot,
>> +};
>> +
>> +int __init exynos_firmware_init(void)
>> +{
>> +	firmware_ops = exynos_firmware_ops;
>> +	return 0;
>> +}
>
> If you add a check for SMC presence/execution mode here, then you can
> make this a runtime instead of boot time option, thus making it possible
> to build a kernel that boots and runs both with and without SMC support.
In the previous time, it's hard to detect at runtime, so I add this function.
I think it's board specfic instead of SOC one.
Can you check it again, does it possbiel to know smc firmware is
support at this board?

Thank you,
Kyungmin Park


From sangsu4u.park at samsung.com  Tue Aug 28 04:55:49 2012
From: sangsu4u.park at samsung.com (Sangsu Park)
Date: Tue, 28 Aug 2012 17:55:49 +0900
Subject: [RESUBMIT PATCH] ASoC: SAMSUNG: Change Kconfig to support all SAMSUNG
 ASoC
Message-ID: <003301cd84fa$eb8a6b20$c29f4160$@samsung.com>

All SAMSUNG ASoC needs SND_SOC_SAMSUNG configuration.
This patch change Kconfig to support all SAMSUNG ASoC.

Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>
---
 sound/soc/samsung/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index f17dd25..e7b8317 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,6 +1,6 @@
 config SND_SOC_SAMSUNG
 	tristate "ASoC support for Samsung"
-	depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_EXYNOS4
+	depends on PLAT_SAMSUNG
 	select S3C64XX_DMA if ARCH_S3C64XX
 	select S3C2410_DMA if ARCH_S3C24XX
 	help
-- 
1.7.1

On 08/28/12 8:00, Kukjin Kim wrote:
> On 08/27/12 11:08, Mark Brown wrote:
> > On Mon, Aug 27, 2012 at 11:06:47AM -0700, Kukjin Kim wrote:
> >
> >> Hmm, all of Samsung stuff is available...so how about?
> >>
> >> +	depends on PLAT_SAMSUNG
> >
> > Yes, that's a very good idea!
> 
> Mark, thanks.
> 
> Sangsu, could you please re-submit as per my suggestion?
> 
> Thanks.
> 

Kukjin, thanks. 
This is re-submit patch. In fact, I'd wanted to submit your idea :)
Thanks.

> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer, SW Solution Development Team, Samsung
> Electronics Co., Ltd.



From richard.zhao at freescale.com  Tue Aug 28 05:09:43 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 17:09:43 +0800
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
 <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120828090942.GX4011@b20223-02.ap.freescale.net>

On Tue, Aug 28, 2012 at 11:29:35AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > States in gadget are not needed any more, set it to zero.
> 
> It's generally a good practice to mention in the commit message what is
> it that you are fixing with this patch.
It fixes the following dump if udc_start register gadget->dev but fail
the start process:
kobject (bf8330a0): tried to init an initialized object, something is seriously wrong.
[<80011d90>] (dump_backtrace+0x0/0x10c) from [<804b65ac>] (dump_stack+0x18/0x1c)
[<804b6594>] (dump_stack+0x0/0x1c) from [<80247d98>] (kobject_init+0x7c/0x9c)
[<80247d1c>] (kobject_init+0x0/0x9c) from [<802a3870>] (device_initialize+0x28/0x70)
[<802a3848>] (device_initialize+0x0/0x70) from [<802a4798>] (device_register+0x14/0x20)
[<802a4784>] (device_register+0x0/0x20) from [<80359a70>] (udc_start+0x180/0x2c8)
[<803598f0>] (udc_start+0x0/0x2c8) from [<80356e9c>] (ci_role_work+0xc8/0xec)
[<80356dd4>] (ci_role_work+0x0/0xec) from [<8003a8a0>] (process_one_work+0x158/0x474)
[<8003a748>] (process_one_work+0x0/0x474) from [<8003af6c>] (worker_thread+0x140/0x3b4)
[<8003ae2c>] (worker_thread+0x0/0x3b4) from [<8003fe60>] (kthread+0x90/0x9c)
[<8003fdd0>] (kthread+0x0/0x9c) from [<8002774c>] (do_exit+0x0/0x350)
> 
> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> > ---
> >  drivers/usb/chipidea/udc.c |    1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > index c7a032a..9fb6394 100644
> > --- a/drivers/usb/chipidea/udc.c
> > +++ b/drivers/usb/chipidea/udc.c
> > @@ -1746,6 +1746,7 @@ free_pools:
> >  	dma_pool_destroy(ci->td_pool);
> >  free_qh_pool:
> >  	dma_pool_destroy(ci->qh_pool);
> > +	memset(&ci->gadget, 0, sizeof(ci->gadget));
> 
> I understand that you're probably hitting "kobject already initialized"
> warning here, but I think the real problem is that this function gets
> called twice and fails the first time. Why does that happen?
I saw the dump at early stage of adding imx otg support, when there's
things not ready. I think it's less important why udc_start fail,
because no one enable imx otg before.  It's important when it fails,
the dump shows up.

Thanks
Richard
> 
> In any case, please elaborate on the problem.
> 
> Regards,
> --
> Alex
> 



From andrew at lunn.ch  Tue Aug 28 05:11:39 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 28 Aug 2012 11:11:39 +0200
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120828091139.GC31704@lunn.ch>

On Tue, Aug 28, 2012 at 01:35:28AM +0200, Thomas Petazzoni wrote:
> Commit c085d965fb63ac3b4cc7379d45588c0b39e2bdb0 made the ARCH_MVEBU
> platform select PLAT_ORION, which means that now all Orion drivers can
> be enabled on ARCH_MVEBU. This works fine for most drivers, except for
> orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
> not have a mach/hardware.h header (it is considered as a deprecated
> practice).
> 
> It turns out that the <mach/hardware.h> include in orion_nand is not
> necessary: the driver builds perfectly fine without it, so we simply
> get rid of it.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: David Woodhouse <dwmw2 at infradead.org>
> Cc: linux-mtd at lists.infradead.org
> Cc: Artem Bityutskiy <dedekind1 at gmail.com>
> ---
>  drivers/mtd/nand/orion_nand.c |    1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
> index fc5a868..9ee436d 100644
> --- a/drivers/mtd/nand/orion_nand.c
> +++ b/drivers/mtd/nand/orion_nand.c
> @@ -21,7 +21,6 @@
>  #include <linux/err.h>
>  #include <asm/io.h>
>  #include <asm/sizes.h>
> -#include <mach/hardware.h>
>  #include <plat/orion_nand.h>
>  
>  static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
> -- 
> 1.7.9.5
> 

Hi Thomas

I compiled tested on Dove, Kirkwood, Orion5x and mv78xx0.

Tested-by: Andrew Lunn <andrew at lunn.ch>

One other driver you might want to look at is:

drivers/watchdog/orion_wdt.c

It uses <mach/bridge-regs.h>

   Andrew


From den at openvz.org  Tue Aug 28 05:12:04 2012
From: den at openvz.org (Denis V. Lunev)
Date: Tue, 28 Aug 2012 13:12:04 +0400
Subject: [PATCH 1/1] arm: KGDB support for PXA
Message-ID: <1346145124-23384-1-git-send-email-den@openvz.org>

From: "Denis V. Lunev" <den at openvz.org>

Actually, in order to support KGDB over serial console one must
implement two callbacks for character polling. Clone them from
8250 driver with a bit of tuning.

Signed-off-by: Denis V. Lunev <den at openvz.org>
Signed-off-by: Marko Katic <dromede at gmail.com>
CC: Eric Miao <eric.y.miao at gmail.com>
CC: Russell King <linux at arm.linux.org.uk>
CC: Haojian Zhuang <haojian.zhuang at gmail.com>
CC: <linux-arm-kernel at lists.infradead.org>
---
This patch has been originally posted by me to LKML in 2009 and postponed.
I was contacted last week by Marko who has kindly ported the patch to the
latest v3.6 kernel and asked to re-send it.

Here it is :)

 drivers/tty/serial/pxa.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5847a4b..54cbb02 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -691,6 +691,57 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
 	clk_disable_unprepare(up->clk);
 }
 
+#ifdef CONFIG_CONSOLE_POLL
+/*
+ * Console polling routines for writing and reading from the uart while
+ * in an interrupt or debug context.
+ */
+
+static int serial_pxa_get_poll_char(struct uart_port *port)
+{
+	struct uart_pxa_port *up = (struct uart_pxa_port *)port;
+	unsigned char lsr = serial_in(up, UART_LSR);
+
+	while (!(lsr & UART_LSR_DR))
+		lsr = serial_in(up, UART_LSR);
+
+	return serial_in(up, UART_RX);
+}
+
+
+static void serial_pxa_put_poll_char(struct uart_port *port,
+			 unsigned char c)
+{
+	unsigned int ier;
+	struct uart_pxa_port *up = (struct uart_pxa_port *)port;
+
+	/*
+	 *	First save the IER then disable the interrupts
+	 */
+	ier = serial_in(up, UART_IER);
+	serial_out(up, UART_IER, UART_IER_UUE);
+
+	wait_for_xmitr(up);
+	/*
+	 *	Send the character out.
+	 *	If a LF, also do CR...
+	 */
+	serial_out(up, UART_TX, c);
+	if (c == 10) {
+		wait_for_xmitr(up);
+		serial_out(up, UART_TX, 13);
+	}
+
+	/*
+	 *	Finally, wait for transmitter to become empty
+	 *	and restore the IER
+	 */
+	wait_for_xmitr(up);
+	serial_out(up, UART_IER, ier);
+}
+
+#endif /* CONFIG_CONSOLE_POLL */
+
 static int __init
 serial_pxa_console_setup(struct console *co, char *options)
 {
@@ -745,6 +796,10 @@ struct uart_ops serial_pxa_pops = {
 	.request_port	= serial_pxa_request_port,
 	.config_port	= serial_pxa_config_port,
 	.verify_port	= serial_pxa_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_get_char = serial_pxa_get_poll_char,
+	.poll_put_char = serial_pxa_put_poll_char,
+#endif
 };
 
 static struct uart_driver serial_pxa_reg = {
-- 
1.7.7.6



From richard.zhao at freescale.com  Tue Aug 28 05:27:31 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 17:27:31 +0800
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
 <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120828092730.GY4011@b20223-02.ap.freescale.net>

On Tue, Aug 28, 2012 at 11:38:23AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > One role failed, but the other role will possiblly still work.
> > For example, when udc start failed, if plug in a host device,
> > it works.
> 
> If you're a host device, ci->role should be HOST at this point and
> ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
> role detection must be fixed. If ci_role_start() fails for host, but it
> still works when it's called again after the id pin change is detected,
> again, the problem is elsewhere.
The check is only for OTG device. For single role device, it just fail
if it start the role failed.
> 
> >
> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> > ---
> >  drivers/usb/chipidea/core.c |    7 +++++--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> > index 19ef324..8fd390a 100644
> > --- a/drivers/usb/chipidea/core.c
> > +++ b/drivers/usb/chipidea/core.c
> > @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
> >  	ret = ci_role_start(ci, ci->role);
> >  	if (ret) {
> >  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
> > -		ret = -ENODEV;
> > -		goto rm_wq;
> > +		ci->role = CI_ROLE_END;
> 
> So are you relying on id pin interrupt for initializing the role after
> this? Can you provide more details?
Yes. The ID pin detect still works. My case is, gadget role failed,
host role works. I was trying not to ruin host function.

Thanks
Richard
> 
> Regards,
> --
> Alex
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From b29396 at freescale.com  Tue Aug 28 05:09:58 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:09:58 +0800
Subject: [PATCH v3 0/7] add syscon driver based on regmap for general
 registers access
Message-ID: <1346145005-17961-1-git-send-email-b29396@freescale.com>

This patch series mainly adds an syscon driver which is used to access
general system controller registers like FSL IOMUXC GPR and ANATOP,
after that, we convert all the exist private access general registers code to use
standard API from regmap to access registers.
Finally we remove the old mfd anatop driver which is only for anatop register
access.

The patch series is based on linus's tree 3.6-rc3 since commit 9160338.

Dong Aisheng (7):
  mfd: add syscon driver based on regmap
  ARM: imx6q: add iomuxc gpr support into syscon
  ARM: imx6q: add anatop support into syscon
  regulator: anatop-regulator: convert to use syscon to access anatop
    register
  ARM: imx6q: convert to use syscon to access anatop registers
  ARM: dts: imx6q: add simple-bus compatible string for anatop
  mfd: anatop-mfd: remove anatop driver

 Documentation/devicetree/bindings/mfd/syscon.txt |   11 +
 arch/arm/boot/dts/imx6q.dtsi                     |    9 +-
 arch/arm/mach-imx/Kconfig                        |    2 +-
 arch/arm/mach-imx/mach-imx6q.c                   |   47 ++--
 drivers/mfd/Kconfig                              |   13 +-
 drivers/mfd/Makefile                             |    2 +-
 drivers/mfd/anatop-mfd.c                         |  124 ---------
 drivers/mfd/syscon.c                             |  172 ++++++++++++
 drivers/regulator/Kconfig                        |    2 +-
 drivers/regulator/anatop-regulator.c             |   30 ++-
 include/linux/fsl/imx6q-iomuxc-gpr.h             |  319 ++++++++++++++++++++++
 include/linux/mfd/anatop.h                       |   40 ---
 include/linux/mfd/syscon.h                       |   23 ++
 13 files changed, 579 insertions(+), 215 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/syscon.txt
 delete mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 drivers/mfd/syscon.c
 create mode 100644 include/linux/fsl/imx6q-iomuxc-gpr.h
 delete mode 100644 include/linux/mfd/anatop.h
 create mode 100644 include/linux/mfd/syscon.h




From b29396 at freescale.com  Tue Aug 28 05:09:59 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:09:59 +0800
Subject: [PATCH v3 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-2-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Add regmap based syscon driver.
This is usually used for access misc bits in registers which does not belong
to a specific module, for example, IMX IOMUXC GPR and ANATOP.
With this driver, client can use generic regmap API to access registers
which are registered into syscon.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog:
v2->v3:
 * export regmap lookup APIs including syscon_node_to_regmap
 * fix a few typo
v1->v2:
 * provide a way of retrieving the regmap, suggested by Mark Brown.
 * delete imx-syscon io accessors and using generic regmap API for client drivers.
 * change to a more generic name for other SoCs to use.
---
 Documentation/devicetree/bindings/mfd/syscon.txt |   11 ++
 drivers/mfd/Kconfig                              |    7 +
 drivers/mfd/Makefile                             |    1 +
 drivers/mfd/syscon.c                             |  172 ++++++++++++++++++++++
 include/linux/mfd/syscon.h                       |   23 +++
 5 files changed, 214 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
new file mode 100644
index 0000000..0f0d26d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -0,0 +1,11 @@
+* System Controller Registers R/W driver
+
+Required properties:
+- compatible: Should contain "syscon".
+- reg: the register range can be access from syscon
+
+Examples:
+gpr: iomuxc-gpr at 020e0000 {
+	compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+	reg = <0x020e0000 0x38>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b1a1462..4a6c48e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -993,6 +993,13 @@ config MFD_ANATOP
 	  MFD controller. This controller embeds regulator and
 	  thermal devices for Freescale i.MX platforms.
 
+config MFD_SYSCON
+        bool "System Controller Register R/W Based on Regmap"
+        select REGMAP_MMIO
+        help
+          Select this option to enable accessing system control registers
+	  via regmap.
+
 config MFD_PALMAS
 	bool "Support for the TI Palmas series chips"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..8384bc9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
+obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
new file mode 100644
index 0000000..e6e5b7a
--- /dev/null
+++ b/drivers/mfd/syscon.c
@@ -0,0 +1,172 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct platform_driver syscon_driver;
+
+struct syscon {
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *regmap;
+};
+
+static int syscon_match(struct device *dev, void *data)
+{
+	struct syscon *syscon = dev_get_drvdata(dev);
+	struct device_node *dn = data;
+
+	return (syscon->dev->of_node == dn) ? 1 : 0;
+}
+
+struct regmap *syscon_node_to_regmap(struct device_node *np)
+{
+	struct syscon *syscon;
+	struct device *dev;
+
+	dev = driver_find_device(&syscon_driver.driver, NULL, np,
+				 syscon_match);
+	of_node_put(np);
+
+	if (!dev)
+		return ERR_PTR(-EPROBE_DEFER);
+
+	syscon = dev_get_drvdata(dev);
+
+	return syscon->regmap;
+}
+EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
+
+struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_find_compatible_node(NULL, NULL, s);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
+
+struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
+					const char *property)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_parse_phandle(np, property, 0);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle);
+
+static const struct of_device_id of_syscon_match[] = {
+	{ .compatible = "syscon", },
+	{ },
+};
+
+static struct regmap_config syscon_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int __devinit syscon_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct syscon *syscon;
+	struct resource res;
+	int ret;
+
+	if (!np)
+		return -ENOENT;
+
+	syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
+			    GFP_KERNEL);
+	if (!syscon)
+		return -ENOMEM;
+
+	syscon->base = of_iomap(np, 0);
+	if (!syscon->base)
+		return -EADDRNOTAVAIL;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	syscon_regmap_config.max_register = res.end - res.start - 3;
+	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
+					&syscon_regmap_config);
+	if (IS_ERR(syscon->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(syscon->regmap);
+	}
+
+	regcache_cache_only(syscon->regmap, false);
+
+	syscon->dev = &pdev->dev;
+	platform_set_drvdata(pdev, syscon);
+
+	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
+		res.start, res.end);
+
+	return 0;
+}
+
+static int __devexit syscon_remove(struct platform_device *pdev)
+{
+	struct syscon *syscon;
+
+	syscon = platform_get_drvdata(pdev);
+	iounmap(syscon->base);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver syscon_driver = {
+	.driver = {
+		.name = "syscon",
+		.owner = THIS_MODULE,
+		.of_match_table = of_syscon_match,
+	},
+	.probe		= syscon_probe,
+	.remove		= __devexit_p(syscon_remove),
+};
+
+static int __init syscon_init(void)
+{
+	return platform_driver_register(&syscon_driver);
+}
+postcore_initcall(syscon_init);
+
+static void __exit syscon_exit(void)
+{
+	platform_driver_unregister(&syscon_driver);
+}
+module_exit(syscon_exit);
+
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("System Control driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
new file mode 100644
index 0000000..6aeb6b8
--- /dev/null
+++ b/include/linux/mfd/syscon.h
@@ -0,0 +1,23 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_MFD_SYSCON_H__
+#define __LINUX_MFD_SYSCON_H__
+
+extern struct regmap *syscon_node_to_regmap(struct device_node *np);
+extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
+extern struct regmap *syscon_regmap_lookup_by_phandle(
+					struct device_node *np,
+					const char *property);
+#endif /* __LINUX_MFD_SYSCON_H__ */
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:02 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:02 +0800
Subject: [PATCH v3 4/7] regulator: anatop-regulator: convert to use syscon to
 access anatop register
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-5-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop register.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * update to use syscon_node_to_regmap and use of_get_parent to get anatop node.
ChangeLog v1-v2:
 * update to use generic regmap api
---
 drivers/regulator/Kconfig            |    2 +-
 drivers/regulator/anatop-regulator.c |   30 ++++++++++++++++++++----------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 4e932cc..2ae1d97 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -112,7 +112,7 @@ config REGULATOR_DA9052
 
 config REGULATOR_ANATOP
 	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
-	depends on MFD_ANATOP
+	depends on MFD_SYSCON
 	help
 	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
 	  regulators. It is recommended that this option be
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index ce0fe72..346e5f6 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -21,19 +21,20 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 #include <linux/module.h>
+#include <linux/mfd/syscon.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
+#include <linux/regmap.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/of_regulator.h>
 
 struct anatop_regulator {
 	const char *name;
 	u32 control_reg;
-	struct anatop *mfd;
+	struct regmap *anatop;
 	int vol_bit_shift;
 	int vol_bit_width;
 	int min_bit_val;
@@ -43,7 +44,8 @@ struct anatop_regulator {
 	struct regulator_init_data *initdata;
 };
 
-static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
+static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
+					unsigned selector)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -56,12 +58,13 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val <<= anatop_reg->vol_bit_shift;
-	anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
+	regmap_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
+				mask, val);
 
 	return 0;
 }
 
-static int anatop_get_voltage_sel(struct regulator_dev *reg)
+static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -69,7 +72,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 	if (!anatop_reg->control_reg)
 		return -ENOTSUPP;
 
-	val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
+	regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val = (val & mask) >> anatop_reg->vol_bit_shift;
@@ -78,8 +81,8 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 }
 
 static struct regulator_ops anatop_rops = {
-	.set_voltage_sel = anatop_set_voltage_sel,
-	.get_voltage_sel = anatop_get_voltage_sel,
+	.set_voltage_sel = anatop_regmap_set_voltage_sel,
+	.get_voltage_sel = anatop_regmap_get_voltage_sel,
 	.list_voltage = regulator_list_voltage_linear,
 	.map_voltage = regulator_map_voltage_linear,
 };
@@ -88,11 +91,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
+	struct device_node *anatop_np;
 	struct regulator_desc *rdesc;
 	struct regulator_dev *rdev;
 	struct anatop_regulator *sreg;
 	struct regulator_init_data *initdata;
-	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
 	struct regulator_config config = { };
 	int ret = 0;
 
@@ -109,7 +112,14 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	rdesc->ops = &anatop_rops;
 	rdesc->type = REGULATOR_VOLTAGE;
 	rdesc->owner = THIS_MODULE;
-	sreg->mfd = anatopmfd;
+
+	anatop_np = of_get_parent(np);
+	if (!anatop_np)
+		return -ENODEV;
+	sreg->anatop = syscon_node_to_regmap(anatop_np);
+	if (IS_ERR(sreg->anatop))
+		return PTR_ERR(sreg->anatop);
+
 	ret = of_property_read_u32(np, "anatop-reg-offset",
 				   &sreg->control_reg);
 	if (ret) {
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:01 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:01 +0800
Subject: [PATCH v3 3/7] ARM: imx6q: add anatop support into syscon
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-4-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

There're a few anatop registers need to be accessed by different modules.
Add anatop registers into syscon support for easy access.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bea21bc..db3fa15 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -378,8 +378,8 @@
 				interrupts = <0 87 0x04 0 88 0x04>;
 			};
 
-			anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop";
+			anatop: anatop at 020c8000 {
+				compatible = "fsl,imx6q-anatop", "syscon";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:00 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:00 +0800
Subject: [PATCH v3 2/7] ARM: imx6q: add iomuxc gpr support into syscon
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-3-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Include headfile for easy using.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi         |    5 +
 include/linux/fsl/imx6q-iomuxc-gpr.h |  319 ++++++++++++++++++++++++++++++++++
 2 files changed, 324 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..bea21bc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -507,6 +507,11 @@
 				interrupts = <0 89 0x04 0 90 0x04>;
 			};
 
+			gpr: iomuxc-gpr at 020e0000 {
+				compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+				reg = <0x020e0000 0x38>;
+			};
+
 			iomuxc at 020e0000 {
 				compatible = "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
diff --git a/include/linux/fsl/imx6q-iomuxc-gpr.h b/include/linux/fsl/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..2c44573
--- /dev/null
+++ b/include/linux/fsl/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0	0x00
+#define IOMUXC_GPR1	0x04
+#define IOMUXC_GPR2	0x08
+#define IOMUXC_GPR3	0x0c
+#define IOMUXC_GPR4	0x10
+#define IOMUXC_GPR5	0x14
+#define IOMUXC_GPR6	0x18
+#define IOMUXC_GPR7	0x1c
+#define IOMUXC_GPR8	0x20
+#define IOMUXC_GPR9	0x24
+#define IOMUXC_GPR10	0x28
+#define IOMUXC_GPR11	0x2c
+#define IOMUXC_GPR12	0x30
+#define IOMUXC_GPR13	0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7	(0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED	(0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR	(0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED	(0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7	(0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED	(0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2	(0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED	(0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2	(0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED	(0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1	(0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED	(0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1	(0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1	(0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2	(0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK		BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX	BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK		BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2	BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK		BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1			BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23			BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IMX6Q_GPR1_DPI_OFF			BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY			0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE			BIT(15)
+#define IMX6Q_GPR1_PCIE_INT			BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK		BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER	0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1	BIT(13)
+#define IMX6Q_GPR1_GINT				BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3			BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2			BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1			BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0			BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK	(0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5		(0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3		(0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4		(0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6		(0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK		(0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0		(0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1		(0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2		(0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3		(0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4		(0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5		(0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6		(0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7		(0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK		BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR	0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR	BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK		BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L	BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK		BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L	BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK		BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA	BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK		BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT		BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK		BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA	BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK		BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT		BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN		BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK		(0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE		(0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0	(0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1	(0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK		(0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE		(0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0	(0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK			(0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D		(0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D		(0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG		(0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL		BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL		BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL		BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL		BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK		(0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK		(0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN		BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN		BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN		BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN		BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK		BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK		BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK		BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK		(0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0	(0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1	(0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0	(0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1	(0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK		(0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0	(0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1	(0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0	(0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1	(0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0	(0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1	(0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0	(0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1	(0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL		BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL		BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL		BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL		BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL		BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL		BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL		BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL		BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK		BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK		BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK		BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK		BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK		(0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF		0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL		BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL		BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL		BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK	BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL		BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL		BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN			BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN		BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP		BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR		(0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN		BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK		(0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK		(0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN			BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN			BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK		BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY		0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE		BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK		(0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK		BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1	(0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK		(0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0	(0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1	(0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0	(0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ		BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ		BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB		(0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB		(0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB		(0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB		(0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB		(0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB		(0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB		(0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK		(0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK		(0x7 << 16)
+#define IMX6Q_GPR13_SATA_SPEED_MASK		BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G		0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G		BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5			BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK		(0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16		(0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16		(0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16		(0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16		(0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16		(0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16		(0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK		(0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF		0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF		0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK		(0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST		(0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
+
+#endif /* !__LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:03 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:03 +0800
Subject: [PATCH v3 5/7] ARM: imx6q: convert to use syscon to access anatop
 registers
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-6-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop registers.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * remove a few unneed codes
ChangeLog v1->v2:
 * update to use generic regmap api
---
 arch/arm/mach-imx/Kconfig      |    2 +-
 arch/arm/mach-imx/mach-imx6q.c |   47 +++++++++++++++------------------------
 2 files changed, 19 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..7bba253 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -839,7 +839,7 @@ config SOC_IMX6Q
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC
 	select HAVE_SMP
-	select MFD_ANATOP
+	select MFD_SYSCON
 	select PINCTRL
 	select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6..eaf56b4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,8 +24,9 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -120,20 +121,7 @@ static void __init imx6q_sabrelite_init(void)
 
 static void __init imx6q_usb_init(void)
 {
-	struct device_node *np;
-	struct platform_device *pdev = NULL;
-	struct anatop *adata = NULL;
-
-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-	if (np)
-		pdev = of_find_device_by_node(np);
-	if (pdev)
-		adata = platform_get_drvdata(pdev);
-	if (!adata) {
-		if (np)
-			of_node_put(np);
-		return;
-	}
+	struct regmap *anatop;
 
 #define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT		0x00000210
@@ -141,20 +129,21 @@ static void __init imx6q_usb_init(void)
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000
 
-	/*
-	 * The external charger detector needs to be disabled,
-	 * or the signal at DP will be poor
-	 */
-	anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B
-			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-	anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B |
-			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-
-	of_node_put(np);
+	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+	if (!IS_ERR(anatop)) {
+		/*
+		 * The external charger detector needs to be disabled,
+		 * or the signal at DP will be poor
+		 */
+		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B
+				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B |
+				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+	} else {
+		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+	}
 }
 
 static void __init imx6q_init_machine(void)
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:04 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:04 +0800
Subject: [PATCH v3 6/7] ARM: dts: imx6q: add simple-bus compatible string for
 anatop
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-7-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Originally the anatop regulator devices are populated by mfd anatop driver.
Since mfd anatop driver will be deleted later, we change to populate the
regulator devices by devicetree automatically.
This will cause some warning messages as follows during boot due to device
recreation: "vdd1p1: Failed to create debugfs directory"
But it does not break any function.
Later, we will remove mfd anatop driver which can get rid of this
error message.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index db3fa15..52ed4d1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -379,7 +379,7 @@
 			};
 
 			anatop: anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop", "syscon";
+				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Tue Aug 28 05:10:05 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 28 Aug 2012 17:10:05 +0800
Subject: [PATCH v3 7/7] mfd: anatop-mfd: remove anatop driver
In-Reply-To: <1346145005-17961-1-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
Message-ID: <1346145005-17961-8-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

The anatop registers are accessed via syscon now, no one will use
mfd anatop driver anymore, remove it.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 drivers/mfd/Kconfig        |    8 ---
 drivers/mfd/Makefile       |    1 -
 drivers/mfd/anatop-mfd.c   |  124 --------------------------------------------
 include/linux/mfd/anatop.h |   40 --------------
 4 files changed, 0 insertions(+), 173 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4a6c48e..4fb3f49 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -985,14 +985,6 @@ config MFD_STA2X11
 	depends on STA2X11
 	select MFD_CORE
 
-config MFD_ANATOP
-	bool "Support for Freescale i.MX on-chip ANATOP controller"
-	depends on SOC_IMX6Q
-	help
-	  Select this option to enable Freescale i.MX on-chip ANATOP
-	  MFD controller. This controller embeds regulator and
-	  thermal devices for Freescale i.MX platforms.
-
 config MFD_SYSCON
         bool "System Controller Register R/W Based on Regmap"
         select REGMAP_MMIO
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8384bc9..0f10a95 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -130,6 +130,5 @@ obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
-obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
 obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
deleted file mode 100644
index 5576e07..0000000
--- a/drivers/mfd/anatop-mfd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- * Copyright (C) 2012 Linaro
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
-
-u32 anatop_read_reg(struct anatop *adata, u32 addr)
-{
-	return readl(adata->ioreg + addr);
-}
-EXPORT_SYMBOL_GPL(anatop_read_reg);
-
-void anatop_write_reg(struct anatop *adata, u32 addr, u32 data, u32 mask)
-{
-	u32 val;
-
-	data &= mask;
-
-	spin_lock(&adata->reglock);
-	val = readl(adata->ioreg + addr);
-	val &= ~mask;
-	val |= data;
-	writel(val, adata->ioreg + addr);
-	spin_unlock(&adata->reglock);
-}
-EXPORT_SYMBOL_GPL(anatop_write_reg);
-
-static const struct of_device_id of_anatop_match[] = {
-	{ .compatible = "fsl,imx6q-anatop", },
-	{ },
-};
-
-static int __devinit of_anatop_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	void *ioreg;
-	struct anatop *drvdata;
-
-	ioreg = of_iomap(np, 0);
-	if (!ioreg)
-		return -EADDRNOTAVAIL;
-	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-	if (!drvdata)
-		return -ENOMEM;
-	drvdata->ioreg = ioreg;
-	spin_lock_init(&drvdata->reglock);
-	platform_set_drvdata(pdev, drvdata);
-	of_platform_populate(np, NULL, NULL, dev);
-
-	return 0;
-}
-
-static int __devexit of_anatop_remove(struct platform_device *pdev)
-{
-	struct anatop *drvdata;
-	drvdata = platform_get_drvdata(pdev);
-	iounmap(drvdata->ioreg);
-
-	return 0;
-}
-
-static struct platform_driver anatop_of_driver = {
-	.driver = {
-		.name = "anatop-mfd",
-		.owner = THIS_MODULE,
-		.of_match_table = of_anatop_match,
-	},
-	.probe		= of_anatop_probe,
-	.remove		= of_anatop_remove,
-};
-
-static int __init anatop_init(void)
-{
-	return platform_driver_register(&anatop_of_driver);
-}
-postcore_initcall(anatop_init);
-
-static void __exit anatop_exit(void)
-{
-	platform_driver_unregister(&anatop_of_driver);
-}
-module_exit(anatop_exit);
-
-MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
-MODULE_DESCRIPTION("ANATOP MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf..0000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * anatop.h - Anatop MFD driver
- *
- *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- *  Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_ANATOP_H
-#define __LINUX_MFD_ANATOP_H
-
-#include <linux/spinlock.h>
-
-/**
- * anatop - MFD data
- * @ioreg: ioremap register
- * @reglock: spinlock for register read/write
- */
-struct anatop {
-	void *ioreg;
-	spinlock_t reglock;
-};
-
-extern u32 anatop_read_reg(struct anatop *, u32);
-extern void anatop_write_reg(struct anatop *, u32, u32, u32);
-
-#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.0.4




From sebastian.hesselbarth at gmail.com  Tue Aug 28 05:31:37 2012
From: sebastian.hesselbarth at gmail.com (Sebastian Hesselbarth)
Date: Tue, 28 Aug 2012 11:31:37 +0200
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <20120828091139.GC31704@lunn.ch>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120828091139.GC31704@lunn.ch>
Message-ID: <CABJ1b_QgJU_xLL2Z=-r_hs51O+d4W+oLZPPf9-6UmeO5B+chPg@mail.gmail.com>

On 8/28/12, Andrew Lunn <andrew at lunn.ch> wrote:
> One other driver you might want to look at is:
>
> drivers/watchdog/orion_wdt.c
> It uses <mach/bridge-regs.h>

Andrew, Thomas,

both current watchdog and timer are using the bridge-regs to clear the
interrupt cause. On orion the cause register is located in bridge-regs.
>From the work on timer together with Gregory, I expect Armada 370/XP
to have the watchdog cause bit also within timer registers.

Sebastian


From s.hauer at pengutronix.de  Tue Aug 28 05:35:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 11:35:17 +0200
Subject: [PATCH] media: mx2_camera: Remove MX2_CAMERA_SWAP16 and
 MX2_CAMERA_PACK_DIR_MSB flags.
In-Reply-To: <CACKLOr3OmRUACO8QaJnYA6E=YZMCrrOq1pAXb1wTv4Udg+u8bQ@mail.gmail.com>
References: <1342083809-19921-1-git-send-email-javier.martin@vista-silicon.com>
 <Pine.LNX.4.64.1207201330240.27906@axis700.grange>
 <CACKLOr2sKVWCk3we_cP5MvnR6-WsaFwA9AC=fgp3iLm8B6mfEA@mail.gmail.com>
 <Pine.LNX.4.64.1207301718510.28003@axis700.grange>
 <CACKLOr3OmRUACO8QaJnYA6E=YZMCrrOq1pAXb1wTv4Udg+u8bQ@mail.gmail.com>
Message-ID: <20120828093517.GH26594@pengutronix.de>

On Mon, Aug 20, 2012 at 10:08:39AM +0200, javier Martin wrote:
> Hi,
> 
> On 30 July 2012 17:33, Guennadi Liakhovetski <g.liakhovetski at gmx.de> wrote:
> > Hi Javier
> >
> > On Mon, 30 Jul 2012, javier Martin wrote:
> >
> >> Hi,
> >> thank you for yor ACKs.
> >>
> >> On 20 July 2012 13:31, Guennadi Liakhovetski <g.liakhovetski at gmx.de> wrote:
> >> > On Thu, 12 Jul 2012, Javier Martin wrote:
> >> >
> >> >> These flags are not used any longer and can be safely removed
> >> >> since the following patch:
> >> >> http://www.spinics.net/lists/linux-media/msg50165.html
> >> >>
> >> >> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> >> >
> >> > For the ARM tree:
> >> >
> >> > Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
> >>
> >> forgive my ignorance on the matter. Could you please point me to the
> >> git repository this patch should be merged?
> >
> > Sorry, my "for the ARM tree" comment was probably not clear enough. This
> > patch should certainly go via the ARM (SoC) tree, since it only touches
> > arch/arm. So, the maintainer (Sascha - added to CC), that will be
> > forwarding this patch to Linus can thereby add my "acked-by" to this
> > patch, if he feels like it.
> >
> 
> Sascha, do you have any comments on this one? I can't find it in
> arm-soc, did you already merge it?

Applied, thanks. I have rewritten the commit message as follows:

Author: Javier Martin <javier.martin at vista-silicon.com>
Date:   Thu Jul 12 11:03:29 2012 +0200

    ARM i.MX mx2_camera: Remove MX2_CAMERA_SWAP16 and MX2_CAMERA_PACK_DIR_MSB flags.
    
    These flags are not used any longer and can be safely removed
    since:
    
    | commit 8a76e5383fb5f58868fdd3a2fe1f4b95988f10a8
    | Author: Javier Martin <javier.martin at vista-silicon.com>
    | Date:   Wed Jul 11 17:34:54 2012 +0200
    |
    |    media: mx2_camera: Fix mbus format handling
    
    Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
    Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
    Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
    Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From 21cnbao at gmail.com  Tue Aug 28 05:35:42 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 Aug 2012 17:35:42 +0800
Subject: [GIT PULL] CSR SiRFmarco preparing patches
Message-ID: <CAGsJ_4xY17w96vVs1966KJBC5Tt24qyR=YAPbQWMTFrDRs+xog@mail.gmail.com>

Hi Olof, Arnd,

Please pull the following patches which are making mach-prima2 common
for prima2 and coming new marco SoC.
Note the 3/5 patches depend on 2/5:
ARM: PRIMA2: convert to common clk and finish full clk tree
clk: prima2: move from arch/arm/mach to drivers/clk
which have been in Mike's clk-next, you might see:
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;h=refs/heads/clk-next

so i rebase other 3 patches on top of commit
bc0e489eb07f4aa2fb5cb9b7ff1fdf4b6ba3bda5.

i guess Mike will not rebase prima2 clk patches any more, so there
will not be merge conflict.

anyway, if i have let prima2-clk go through arm-soc tree but not clk
tree, things should be better.

Regards,
Barry

The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:
  git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel.git marco-prepare

Barry Song (4):
      clk: prima2: move from arch/arm/mach to drivers/clk
      ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
      ARM: PRIMA2: adjust Kconfig to support select SoC features
      ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GIC

Binghua Duan (1):
      ARM: PRIMA2: convert to common clk and finish full clk tree

 arch/arm/Kconfig                            |   12 +-
 arch/arm/configs/prima2_defconfig           |    7 +-
 arch/arm/mach-prima2/Kconfig                |   19 +
 arch/arm/mach-prima2/Makefile               |    5 +-
 arch/arm/mach-prima2/clock.c                |  510 ------------
 arch/arm/mach-prima2/{prima2.c => common.c} |   12 +-
 arch/arm/mach-prima2/irq.c                  |    2 +-
 arch/arm/mach-prima2/timer.c                |    8 +-
 drivers/clk/Makefile                        |    1 +
 drivers/clk/clk-prima2.c                    | 1171 +++++++++++++++++++++++++++
 10 files changed, 1216 insertions(+), 531 deletions(-)
 create mode 100644 arch/arm/mach-prima2/Kconfig
 delete mode 100644 arch/arm/mach-prima2/clock.c
 rename arch/arm/mach-prima2/{prima2.c => common.c} (81%)
 create mode 100644 drivers/clk/clk-prima2.c


From vbyravarasu at nvidia.com  Tue Aug 28 05:32:18 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Tue, 28 Aug 2012 15:02:18 +0530
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
Message-ID: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>

In order to keep up with the USB driver files organization,
moving USB phy driver from mach-tegra to drivers/USB directory.

Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
---
 arch/arm/mach-tegra/Makefile                       |    1 -
 arch/arm/mach-tegra/devices.c                      |    8 +-------
 arch/arm/mach-tegra/devices.h                      |    2 --
 drivers/usb/host/ehci-tegra.c                      |    2 +-
 drivers/usb/phy/Makefile                           |    1 +
 .../usb_phy.c => drivers/usb/phy/tegra_usb_phy.c   |    4 +---
 .../usb_phy.h => drivers/usb/phy/tegra_usb_phy.h   |    2 --
 7 files changed, 4 insertions(+), 16 deletions(-)
 rename arch/arm/mach-tegra/usb_phy.c => drivers/usb/phy/tegra_usb_phy.c (99%)
 rename arch/arm/mach-tegra/include/mach/usb_phy.h => drivers/usb/phy/tegra_usb_phy.h (97%)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b94858f..b542dac 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
-obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 61e9603..232d7e1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -26,7 +26,6 @@
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
-#include <mach/usb_phy.h>
 
 #include "gpio-names.h"
 #include "devices.h"
@@ -438,11 +437,6 @@ static struct resource tegra_usb3_resources[] = {
 	},
 };
 
-struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
-	.reset_gpio = -1,
-	.clk = "cdev2",
-};
-
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
 	.operating_mode = TEGRA_USB_OTG,
 	.power_down_on_bus_suspend = 1,
@@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata = {
 };
 
 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
-	.phy_config = &tegra_ehci2_ulpi_phy_config,
+	.phy_config = NULL,
 	.operating_mode = TEGRA_USB_HOST,
 	.power_down_on_bus_suspend = 1,
 	.vbus_gpio = -1,
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 4f50527..6bac5e6 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -22,8 +22,6 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_usb.h>
 
-#include <mach/usb_phy.h>
-
 extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
 
 extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 75eca42..a03e279 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -27,7 +27,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 
-#include <mach/usb_phy.h>
+#include "../phy/tegra_usb_phy.h"
 #include <mach/iomap.h>
 
 #define TEGRA_USB_DMA_ALIGN 32
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..663164f 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_USB_EHCI_TEGRA)		+= tegra_usb_phy.o
diff --git a/arch/arm/mach-tegra/usb_phy.c b/drivers/usb/phy/tegra_usb_phy.c
similarity index 99%
rename from arch/arm/mach-tegra/usb_phy.c
rename to drivers/usb/phy/tegra_usb_phy.c
index 022b33a..c856716 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/drivers/usb/phy/tegra_usb_phy.c
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/usb_phy.c
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
@@ -31,7 +29,7 @@
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <mach/gpio-tegra.h>
-#include <mach/usb_phy.h>
+#include "tegra_usb_phy.h"
 #include <mach/iomap.h>
 
 #define ULPI_VIEWPORT		0x170
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/drivers/usb/phy/tegra_usb_phy.h
similarity index 97%
rename from arch/arm/mach-tegra/include/mach/usb_phy.h
rename to drivers/usb/phy/tegra_usb_phy.h
index 935ce9f..516c724 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/drivers/usb/phy/tegra_usb_phy.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/include/mach/usb_phy.h
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
-- 
1.7.1.1



From t-kristo at ti.com  Tue Aug 28 05:50:10 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 28 Aug 2012 12:50:10 +0300
Subject: [PATCH v2 02/14] MFD: twl4030-audio: Convert to use devm_kzalloc
In-Reply-To: <1344954162-7985-3-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
 <1344954162-7985-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346147410.2182.96.camel@sokoban>

On Tue, 2012-08-14 at 17:22 +0300, Peter Ujfalusi wrote:
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>

I think this one could use a short commit message, also about why
kfree():s are dropped (handled internally by devm_* etc.)

-Tero



From t-kristo at ti.com  Tue Aug 28 05:51:50 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 28 Aug 2012 12:51:50 +0300
Subject: [PATCH v2 00/14] MFD/ASoC/Input: twl4030-audio submodule DT
 support
In-Reply-To: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346147510.2182.98.camel@sokoban>

Hi Peter,

The MFD patches in this set look good to me except for the minor comment
on patch 2 I just sent. That is with my limited knowledge of DT
though...

-Tero




From balbi at ti.com  Tue Aug 28 05:49:26 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 28 Aug 2012 12:49:26 +0300
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
Message-ID: <20120828094924.GT27166@arwen.pp.htv.fi>

Hi,

On Tue, Aug 28, 2012 at 03:02:18PM +0530, Venu Byravarasu wrote:
> In order to keep up with the USB driver files organization,
> moving USB phy driver from mach-tegra to drivers/USB directory.
> 
> Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
> ---
>  arch/arm/mach-tegra/Makefile                       |    1 -
>  arch/arm/mach-tegra/devices.c                      |    8 +-------
>  arch/arm/mach-tegra/devices.h                      |    2 --
>  drivers/usb/host/ehci-tegra.c                      |    2 +-
>  drivers/usb/phy/Makefile                           |    1 +
>  .../usb_phy.c => drivers/usb/phy/tegra_usb_phy.c   |    4 +---
>  .../usb_phy.h => drivers/usb/phy/tegra_usb_phy.h   |    2 --
>  7 files changed, 4 insertions(+), 16 deletions(-)
>  rename arch/arm/mach-tegra/usb_phy.c => drivers/usb/phy/tegra_usb_phy.c (99%)
>  rename arch/arm/mach-tegra/include/mach/usb_phy.h => drivers/usb/phy/tegra_usb_phy.h (97%)
> 
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index b94858f..b542dac 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -25,7 +25,6 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
>  obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
>  obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
>  obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
> -obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
>  
>  obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
>  obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
> diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
> index 61e9603..232d7e1 100644
> --- a/arch/arm/mach-tegra/devices.c
> +++ b/arch/arm/mach-tegra/devices.c
> @@ -26,7 +26,6 @@
>  #include <mach/irqs.h>
>  #include <mach/iomap.h>
>  #include <mach/dma.h>
> -#include <mach/usb_phy.h>
>  
>  #include "gpio-names.h"
>  #include "devices.h"
> @@ -438,11 +437,6 @@ static struct resource tegra_usb3_resources[] = {
>  	},
>  };
>  
> -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
> -	.reset_gpio = -1,
> -	.clk = "cdev2",
> -};
> -
>  struct tegra_ehci_platform_data tegra_ehci1_pdata = {
>  	.operating_mode = TEGRA_USB_OTG,
>  	.power_down_on_bus_suspend = 1,
> @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata = {
>  };
>  
>  struct tegra_ehci_platform_data tegra_ehci2_pdata = {
> -	.phy_config = &tegra_ehci2_ulpi_phy_config,
> +	.phy_config = NULL,
>  	.operating_mode = TEGRA_USB_HOST,
>  	.power_down_on_bus_suspend = 1,
>  	.vbus_gpio = -1,
> diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
> index 4f50527..6bac5e6 100644
> --- a/arch/arm/mach-tegra/devices.h
> +++ b/arch/arm/mach-tegra/devices.h
> @@ -22,8 +22,6 @@
>  #include <linux/platform_device.h>
>  #include <linux/platform_data/tegra_usb.h>
>  
> -#include <mach/usb_phy.h>
> -
>  extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
>  
>  extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> index 75eca42..a03e279 100644
> --- a/drivers/usb/host/ehci-tegra.c
> +++ b/drivers/usb/host/ehci-tegra.c
> @@ -27,7 +27,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pm_runtime.h>
>  
> -#include <mach/usb_phy.h>
> +#include "../phy/tegra_usb_phy.h"
>  #include <mach/iomap.h>
>  
>  #define TEGRA_USB_DMA_ALIGN 32
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index eca095b..663164f 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -5,3 +5,4 @@
>  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
>  
>  obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
> +obj-$(CONFIG_USB_EHCI_TEGRA)		+= tegra_usb_phy.o
> diff --git a/arch/arm/mach-tegra/usb_phy.c b/drivers/usb/phy/tegra_usb_phy.c
> similarity index 99%
> rename from arch/arm/mach-tegra/usb_phy.c
> rename to drivers/usb/phy/tegra_usb_phy.c
> index 022b33a..c856716 100644
> --- a/arch/arm/mach-tegra/usb_phy.c
> +++ b/drivers/usb/phy/tegra_usb_phy.c
> @@ -1,6 +1,4 @@
>  /*
> - * arch/arm/mach-tegra/usb_phy.c
> - *
>   * Copyright (C) 2010 Google, Inc.
>   *
>   * Author:
> @@ -31,7 +29,7 @@
>  #include <linux/usb/ulpi.h>
>  #include <asm/mach-types.h>
>  #include <mach/gpio-tegra.h>
> -#include <mach/usb_phy.h>
> +#include "tegra_usb_phy.h"
>  #include <mach/iomap.h>
>  
>  #define ULPI_VIEWPORT		0x170

NAK, needs to be converted to proper PHY driver (misnamed as
include/linux/usb/otg.h). You will need proper phy->init, phy->suspend,
phy->resume, etc callbacks.

-- 
balbi
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From sbkim73 at samsung.com  Tue Aug 28 05:54:47 2012
From: sbkim73 at samsung.com (Sangbeom Kim)
Date: Tue, 28 Aug 2012 18:54:47 +0900
Subject: [alsa-devel] [RESUBMIT PATCH] ASoC: SAMSUNG: Change Kconfig to
 support all SAMSUNG ASoC
In-Reply-To: <003301cd84fa$eb8a6b20$c29f4160$@samsung.com>
References: <003301cd84fa$eb8a6b20$c29f4160$@samsung.com>
Message-ID: <019801cd8503$28e031f0$7aa095d0$@com>

On Mon, Aug 28, 2012 at 05:56PM, Sangsu Park wrote:
> All SAMSUNG ASoC needs SND_SOC_SAMSUNG configuration.
> This patch change Kconfig to support all SAMSUNG ASoC.
> 
> Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>

Acked-by: Sangbeom Kim <sbkim73 at samsung.com>



From t.figa at samsung.com  Tue Aug 28 06:01:05 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 12:01:05 +0200
Subject: [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
Message-ID: <4648723.rWnut7F0uJ@amdc1227>

This patch series makes necessary preparations and adds support for GPIO on 
Exynos4x12 SoCs.

Tomasz Figa (3):
  ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
  gpio: samsung: Add support for Exynos4x12 SoCs
  ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12

 arch/arm/mach-exynos/include/mach/gpio.h   |   58 ++++--
 arch/arm/mach-exynos/include/mach/irqs.h   |    6 -
 arch/arm/mach-exynos/mach-nuri.c           |   16 +-
 arch/arm/mach-exynos/mach-origen.c         |    6 +-
 arch/arm/mach-exynos/mach-trats.c          |    4 +-
 arch/arm/mach-exynos/mach-universal_c210.c |   32 ++--
 arch/arm/mach-exynos/setup-fimc.c          |   21 ++-
 drivers/gpio/gpio-samsung.c                |  351 
++++++++++++++++++++++++----
 8 files changed, 399 insertions(+), 95 deletions(-)

-- 
1.7.8.6




From t.figa at samsung.com  Tue Aug 28 06:06:19 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 12:06:19 +0200
Subject: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
In-Reply-To: <4648723.rWnut7F0uJ@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
Message-ID: <14029212.D3MKvQZpbq@amdc1227>

The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
Redefine them to use the exact SoC name.

Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
Joonyoung Shim, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
---
 arch/arm/mach-exynos/include/mach/gpio.h   | 32 +++++++++++++++---------------
 arch/arm/mach-exynos/mach-nuri.c           | 16 +++++++--------
 arch/arm/mach-exynos/mach-origen.c         |  6 +++---
 arch/arm/mach-exynos/mach-trats.c          |  4 ++--
 arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
 arch/arm/mach-exynos/setup-fimc.c          |  4 ++--
 drivers/gpio/gpio-samsung.c                | 20 +++++++++----------
 7 files changed, 57 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index eb24f1e..21c9bf1 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,11 @@
 #define EXYNOS4_GPIO_C1_NR	(5)
 #define EXYNOS4_GPIO_D0_NR	(4)
 #define EXYNOS4_GPIO_D1_NR	(4)
-#define EXYNOS4_GPIO_E0_NR	(5)
-#define EXYNOS4_GPIO_E1_NR	(8)
-#define EXYNOS4_GPIO_E2_NR	(6)
-#define EXYNOS4_GPIO_E3_NR	(8)
-#define EXYNOS4_GPIO_E4_NR	(8)
+#define EXYNOS4210_GPIO_E0_NR	(5)
+#define EXYNOS4210_GPIO_E1_NR	(8)
+#define EXYNOS4210_GPIO_E2_NR	(6)
+#define EXYNOS4210_GPIO_E3_NR	(8)
+#define EXYNOS4210_GPIO_E4_NR	(8)
 #define EXYNOS4_GPIO_F0_NR	(8)
 #define EXYNOS4_GPIO_F1_NR	(8)
 #define EXYNOS4_GPIO_F2_NR	(8)
@@ -67,12 +67,12 @@ enum exynos4_gpio_number {
 	EXYNOS4_GPIO_C1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
 	EXYNOS4_GPIO_D0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
 	EXYNOS4_GPIO_D1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
-	EXYNOS4_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
-	EXYNOS4_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
-	EXYNOS4_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
-	EXYNOS4_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
-	EXYNOS4_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
-	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
+	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+	EXYNOS4210_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
+	EXYNOS4210_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
+	EXYNOS4210_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
+	EXYNOS4210_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
+	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
 	EXYNOS4_GPIO_F1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
 	EXYNOS4_GPIO_F2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
 	EXYNOS4_GPIO_F3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +108,11 @@ enum exynos4_gpio_number {
 #define EXYNOS4_GPC1(_nr)	(EXYNOS4_GPIO_C1_START + (_nr))
 #define EXYNOS4_GPD0(_nr)	(EXYNOS4_GPIO_D0_START + (_nr))
 #define EXYNOS4_GPD1(_nr)	(EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr)	(EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr)	(EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr)	(EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr)	(EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr)	(EXYNOS4_GPIO_E4_START + (_nr))
+#define EXYNOS4210_GPE0(_nr)	(EXYNOS4210_GPIO_E0_START + (_nr))
+#define EXYNOS4210_GPE1(_nr)	(EXYNOS4210_GPIO_E1_START + (_nr))
+#define EXYNOS4210_GPE2(_nr)	(EXYNOS4210_GPIO_E2_START + (_nr))
+#define EXYNOS4210_GPE3(_nr)	(EXYNOS4210_GPIO_E3_START + (_nr))
+#define EXYNOS4210_GPE4(_nr)	(EXYNOS4210_GPIO_E4_START + (_nr))
 #define EXYNOS4_GPF0(_nr)	(EXYNOS4_GPIO_F0_START + (_nr))
 #define EXYNOS4_GPF1(_nr)	(EXYNOS4_GPIO_F1_START + (_nr))
 #define EXYNOS4_GPF2(_nr)	(EXYNOS4_GPIO_F2_START + (_nr))
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index ea785fc..426bb79 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -268,7 +268,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
 
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
-	int gpio = EXYNOS4_GPE1(5);
+	int gpio = EXYNOS4210_GPE1(5);
 
 	gpio_request(gpio, "LVDS_nSHDN");
 	gpio_direction_output(gpio, power);
@@ -277,7 +277,7 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 
 static int nuri_bl_init(struct device *dev)
 {
-	return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
+	return gpio_request_one(EXYNOS4210_GPE2(3), GPIOF_OUT_INIT_LOW,
 				"LCD_LD0_EN");
 }
 
@@ -286,14 +286,14 @@ static int nuri_bl_notify(struct device *dev, int brightness)
 	if (brightness < 1)
 		brightness = 0;
 
-	gpio_set_value(EXYNOS4_GPE2(3), 1);
+	gpio_set_value(EXYNOS4210_GPE2(3), 1);
 
 	return brightness;
 }
 
 static void nuri_bl_exit(struct device *dev)
 {
-	gpio_free(EXYNOS4_GPE2(3));
+	gpio_free(EXYNOS4210_GPE2(3));
 }
 
 /* nuri pwm backlight */
@@ -1048,7 +1048,7 @@ static struct max8903_pdata nuri_max8903 = {
 	 */
 	.dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
 	/* uok, usus: not connected */
-	.chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+	.chg = EXYNOS4210_GPE2(0), /* TA_nCHG */
 	/* flt: vcc_1.8V_pda */
 	.dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
 
@@ -1119,7 +1119,7 @@ static struct regulator_init_data cam_vt_cam15_reg_init_data = {
 static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
 	.supply_name	= "VT_CAM_1.5V",
 	.microvolts	= 1500000,
-	.gpio		= EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
+	.gpio		= EXYNOS4210_GPE2(2), /* VT_CAM_1.5V_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_vt_cam15_reg_init_data,
 };
@@ -1143,7 +1143,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {
 static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
 	.supply_name	= "CAM_IO_EN",
 	.microvolts	= 2800000,
-	.gpio		= EXYNOS4_GPE2(1), /* CAM_IO_EN */
+	.gpio		= EXYNOS4210_GPE2(1), /* CAM_IO_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_vdda_reg_init_data,
 };
@@ -1167,7 +1167,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {
 static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
 	.supply_name	= "8M_1.2V",
 	.microvolts	= 1200000,
-	.gpio		= EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+	.gpio		= EXYNOS4210_GPE2(5), /* 8M_1.2V_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_8m_12v_reg_init_data,
 };
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5ca8030..13424fc 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -591,13 +591,13 @@ static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
 	int ret;
 
 	if (power)
-		ret = gpio_request_one(EXYNOS4_GPE3(4),
+		ret = gpio_request_one(EXYNOS4210_GPE3(4),
 					GPIOF_OUT_INIT_HIGH, "GPE3_4");
 	else
-		ret = gpio_request_one(EXYNOS4_GPE3(4),
+		ret = gpio_request_one(EXYNOS4210_GPE3(4),
 					GPIOF_OUT_INIT_LOW, "GPE3_4");
 
-	gpio_free(EXYNOS4_GPE3(4));
+	gpio_free(EXYNOS4210_GPE3(4));
 
 	if (ret)
 		pr_err("failed to request gpio for LCD power: %d\n", ret);
diff --git a/arch/arm/mach-exynos/mach-trats.c b/arch/arm/mach-exynos/mach-trats.c
index fdcbcbd..d2c9787 100644
--- a/arch/arm/mach-exynos/mach-trats.c
+++ b/arch/arm/mach-exynos/mach-trats.c
@@ -770,7 +770,7 @@ static struct regulator_init_data cam_vdda_reg_init_data = {
 static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
 	.supply_name	= "CAM_IO_EN",
 	.microvolts	= 2800000,
-	.gpio		= EXYNOS4_GPE2(1), /* CAM_IO_EN */
+	.gpio		= EXYNOS4210_GPE2(1), /* CAM_IO_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_vdda_reg_init_data,
 };
@@ -794,7 +794,7 @@ static struct regulator_init_data cam_8m_12v_reg_init_data = {
 static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
 	.supply_name	= "8M_1.2V_EN",
 	.microvolts	= 1200000,
-	.gpio		= EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+	.gpio		= EXYNOS4210_GPE2(5), /* 8M_1.2V_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_8m_12v_reg_init_data,
 };
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 8951bcc..9c60e66 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -552,7 +552,7 @@ static struct max8998_platform_data universal_lp3974_pdata = {
 	.buck2_voltage1		= 1200000,	/* G3D */
 	.buck2_voltage2		= 1100000,
 	.buck1_default_idx	= 0,
-	.buck2_set3		= EXYNOS4_GPE2(0),
+	.buck2_set3		= EXYNOS4210_GPE2(0),
 	.buck2_default_idx	= 0,
 	.wakeup			= true,
 };
@@ -581,7 +581,7 @@ static struct regulator_init_data hdmi_fixed_voltage_init_data = {
 static struct fixed_voltage_config hdmi_fixed_voltage_config = {
 	.supply_name		= "HDMI_EN1",
 	.microvolts		= 5000000,
-	.gpio			= EXYNOS4_GPE0(1),
+	.gpio			= EXYNOS4210_GPE0(1),
 	.enable_high		= true,
 	.init_data		= &hdmi_fixed_voltage_init_data,
 };
@@ -630,12 +630,12 @@ static void __init universal_tsp_init(void)
 	int gpio;
 
 	/* TSP_LDO_ON: XMDMADDR_11 */
-	gpio = EXYNOS4_GPE2(3);
+	gpio = EXYNOS4210_GPE2(3);
 	gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
 	gpio_export(gpio, 0);
 
 	/* TSP_INT: XMDMADDR_7 */
-	gpio = EXYNOS4_GPE1(7);
+	gpio = EXYNOS4210_GPE1(7);
 	gpio_request(gpio, "TSP_INT");
 
 	s5p_register_gpio_interrupt(gpio);
@@ -661,8 +661,8 @@ static struct mcs_platform_data touchkey_data = {
 /* GPIO I2C 3_TOUCH 2.8V */
 #define I2C_GPIO_BUS_12		12
 static struct i2c_gpio_platform_data i2c_gpio12_data = {
-	.sda_pin	= EXYNOS4_GPE4(0),	/* XMDMDATA_8 */
-	.scl_pin	= EXYNOS4_GPE4(1),	/* XMDMDATA_9 */
+	.sda_pin	= EXYNOS4210_GPE4(0),	/* XMDMDATA_8 */
+	.scl_pin	= EXYNOS4210_GPE4(1),	/* XMDMDATA_9 */
 };
 
 static struct platform_device i2c_gpio12 = {
@@ -684,13 +684,13 @@ static void __init universal_touchkey_init(void)
 {
 	int gpio;
 
-	gpio = EXYNOS4_GPE3(7);			/* XMDMDATA_7 */
+	gpio = EXYNOS4210_GPE3(7);			/* XMDMDATA_7 */
 	gpio_request(gpio, "3_TOUCH_INT");
 	s5p_register_gpio_interrupt(gpio);
 	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
 	i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
 
-	gpio = EXYNOS4_GPE3(3);			/* XMDMDATA_3 */
+	gpio = EXYNOS4210_GPE3(3);			/* XMDMDATA_3 */
 	gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
 }
 
@@ -776,7 +776,7 @@ static struct regulator_init_data mmc0_fixed_voltage_init_data = {
 static struct fixed_voltage_config mmc0_fixed_voltage_config = {
 	.supply_name		= "MASSMEMORY_EN",
 	.microvolts		= 2800000,
-	.gpio			= EXYNOS4_GPE1(3),
+	.gpio			= EXYNOS4210_GPE1(3),
 	.enable_high		= true,
 	.init_data		= &mmc0_fixed_voltage_init_data,
 };
@@ -887,7 +887,7 @@ static struct regulator_init_data cam_vt_dio_reg_init_data = {
 static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
 	.supply_name	= "CAM_VT_D_IO",
 	.microvolts	= 2800000,
-	.gpio		= EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
+	.gpio		= EXYNOS4210_GPE2(1), /* CAM_PWR_EN2 */
 	.enable_high	= 1,
 	.init_data	= &cam_vt_dio_reg_init_data,
 };
@@ -909,7 +909,7 @@ static struct regulator_init_data cam_i_core_reg_init_data = {
 static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
 	.supply_name	= "CAM_I_CORE_1.2V",
 	.microvolts	= 1200000,
-	.gpio		= EXYNOS4_GPE2(2),	/* CAM_8M_CORE_EN */
+	.gpio		= EXYNOS4210_GPE2(2),	/* CAM_8M_CORE_EN */
 	.enable_high	= 1,
 	.init_data	= &cam_i_core_reg_init_data,
 };
@@ -931,7 +931,7 @@ static struct regulator_init_data cam_s_if_reg_init_data = {
 static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
 	.supply_name	= "CAM_S_IF_1.8V",
 	.microvolts	= 1800000,
-	.gpio		= EXYNOS4_GPE3(0),	/* CAM_PWR_EN1 */
+	.gpio		= EXYNOS4210_GPE3(0),	/* CAM_PWR_EN1 */
 	.enable_high	= 1,
 	.init_data	= &cam_s_if_reg_init_data,
 };
@@ -949,11 +949,11 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
 	.phy_enable	= s5p_csis_phy_enable,
 };
 
-#define GPIO_CAM_LEVEL_EN(n)	EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_LEVEL_EN(n)	EXYNOS4210_GPE4(n + 3)
 #define GPIO_CAM_8M_ISP_INT	EXYNOS4_GPX1(5)	/* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST	EXYNOS4_GPE2(5)
-#define GPIO_CAM_VGA_NRST	EXYNOS4_GPE4(7)
-#define GPIO_CAM_VGA_NSTBY	EXYNOS4_GPE4(6)
+#define GPIO_CAM_MEGA_nRST	EXYNOS4210_GPE2(5)
+#define GPIO_CAM_VGA_NRST	EXYNOS4210_GPE4(7)
+#define GPIO_CAM_VGA_NSTBY	EXYNOS4210_GPE4(6)
 
 static int s5k6aa_set_power(int on)
 {
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
index 6a45078..d74843e 100644
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -26,8 +26,8 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
 		break;
 
 	case S5P_CAMPORT_B:
-		gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
-		gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
+		gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
+		gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
 		sfn = S3C_GPIO_SFN(3);
 		break;
 
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..c996440 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2171,32 +2171,32 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
 		},
 	}, {
 		.chip	= {
-			.base	= EXYNOS4_GPE0(0),
-			.ngpio	= EXYNOS4_GPIO_E0_NR,
+			.base	= EXYNOS4210_GPE0(0),
+			.ngpio	= EXYNOS4210_GPIO_E0_NR,
 			.label	= "GPE0",
 		},
 	}, {
 		.chip	= {
-			.base	= EXYNOS4_GPE1(0),
-			.ngpio	= EXYNOS4_GPIO_E1_NR,
+			.base	= EXYNOS4210_GPE1(0),
+			.ngpio	= EXYNOS4210_GPIO_E1_NR,
 			.label	= "GPE1",
 		},
 	}, {
 		.chip	= {
-			.base	= EXYNOS4_GPE2(0),
-			.ngpio	= EXYNOS4_GPIO_E2_NR,
+			.base	= EXYNOS4210_GPE2(0),
+			.ngpio	= EXYNOS4210_GPIO_E2_NR,
 			.label	= "GPE2",
 		},
 	}, {
 		.chip	= {
-			.base	= EXYNOS4_GPE3(0),
-			.ngpio	= EXYNOS4_GPIO_E3_NR,
+			.base	= EXYNOS4210_GPE3(0),
+			.ngpio	= EXYNOS4210_GPIO_E3_NR,
 			.label	= "GPE3",
 		},
 	}, {
 		.chip	= {
-			.base	= EXYNOS4_GPE4(0),
-			.ngpio	= EXYNOS4_GPIO_E4_NR,
+			.base	= EXYNOS4210_GPE4(0),
+			.ngpio	= EXYNOS4210_GPIO_E4_NR,
 			.label	= "GPE4",
 		},
 	}, {
-- 
1.7.12




From t.figa at samsung.com  Tue Aug 28 06:06:55 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 12:06:55 +0200
Subject: [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
In-Reply-To: <4648723.rWnut7F0uJ@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
Message-ID: <2265472.2J2KAQrYg1@amdc1227>

Based on patch "gpio/exynos: Add support for Exynos4x12 SoC" by Joonyoung Shim.
See: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html

Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
so the initialization code has to be modified to support Exynos4x12 SoC.
GPVx Exynos4x12 GPIO part4 is not supported yet.

In the Exynos4x12 GPIO part1 and part2, the interval of base register
offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.

- Exynos4x12 GPIO Part1
GPIO    Base offset     Interrupt reg offset
GPA0    0x000           0x00
GPA1    0x020           0x04
GPB     0x040           0x08
GPC0    0x060           0x0C
GPC1    0x080           0x10
GPD0    0x0A0           0x14
GPD1    0x0C0           0x18
        ...
GPF0    0x180           0x30
GPF1    0x1A0           0x34
GPF2    0x1C0           0x38
GPF3    0x1E0           0x3C
        ...
GPJ0    0x240           0x40
GPJ1    0x260           0x44

- Exynos4x12 GPIO Part2
        ...
GPK0    0x040           0x08
GPK1    0x060           0x0C
GPK2    0x080           0x10
GPK3    0x0A0           0x14
GPL0    0x0C0           0x18
GPL1    0x0E0           0x1C
GPL2    0x100           0x20
GPY0    0x120           x
GPY1    0x140           x
GPY2    0x160           x
GPY3    0x180           x
GPY4    0x1A0           x
GPY5    0x1C0           x
GPY6    0x1E0           x
        ...
GPM0    0x260           0x24
GPM1    0x280           0x28
GPM2    0x2A0           0x2C
GPM3    0x2C0           0x30
GPM4    0x2E0           0x34
GPX0    0xC00           x
GPX1    0xC20           x
GPX2    0xC40           x
GPX3    0xC60           x

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
---
 arch/arm/mach-exynos/include/mach/gpio.h |  28 ++-
 arch/arm/mach-exynos/include/mach/irqs.h |   6 -
 drivers/gpio/gpio-samsung.c              | 330 ++++++++++++++++++++++++++++---
 3 files changed, 326 insertions(+), 38 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 21c9bf1..2103d14 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -26,11 +26,13 @@
 #define EXYNOS4_GPIO_C1_NR	(5)
 #define EXYNOS4_GPIO_D0_NR	(4)
 #define EXYNOS4_GPIO_D1_NR	(4)
+
 #define EXYNOS4210_GPIO_E0_NR	(5)
 #define EXYNOS4210_GPIO_E1_NR	(8)
 #define EXYNOS4210_GPIO_E2_NR	(6)
 #define EXYNOS4210_GPIO_E3_NR	(8)
 #define EXYNOS4210_GPIO_E4_NR	(8)
+
 #define EXYNOS4_GPIO_F0_NR	(8)
 #define EXYNOS4_GPIO_F1_NR	(8)
 #define EXYNOS4_GPIO_F2_NR	(8)
@@ -44,6 +46,13 @@
 #define EXYNOS4_GPIO_L0_NR	(8)
 #define EXYNOS4_GPIO_L1_NR	(3)
 #define EXYNOS4_GPIO_L2_NR	(8)
+
+#define EXYNOS4X12_GPIO_M0_NR	(8)
+#define EXYNOS4X12_GPIO_M1_NR	(7)
+#define EXYNOS4X12_GPIO_M2_NR	(5)
+#define EXYNOS4X12_GPIO_M3_NR	(8)
+#define EXYNOS4X12_GPIO_M4_NR	(8)
+
 #define EXYNOS4_GPIO_X0_NR	(8)
 #define EXYNOS4_GPIO_X1_NR	(8)
 #define EXYNOS4_GPIO_X2_NR	(8)
@@ -67,12 +76,20 @@ enum exynos4_gpio_number {
 	EXYNOS4_GPIO_C1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
 	EXYNOS4_GPIO_D0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
 	EXYNOS4_GPIO_D1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
+
 	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
 	EXYNOS4210_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
 	EXYNOS4210_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
 	EXYNOS4210_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
 	EXYNOS4210_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
-	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
+
+	EXYNOS4X12_GPIO_M0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
+	EXYNOS4X12_GPIO_M1_START	= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
+	EXYNOS4X12_GPIO_M2_START	= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
+	EXYNOS4X12_GPIO_M3_START	= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
+	EXYNOS4X12_GPIO_M4_START	= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
+
+	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
 	EXYNOS4_GPIO_F1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
 	EXYNOS4_GPIO_F2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
 	EXYNOS4_GPIO_F3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
@@ -108,11 +125,13 @@ enum exynos4_gpio_number {
 #define EXYNOS4_GPC1(_nr)	(EXYNOS4_GPIO_C1_START + (_nr))
 #define EXYNOS4_GPD0(_nr)	(EXYNOS4_GPIO_D0_START + (_nr))
 #define EXYNOS4_GPD1(_nr)	(EXYNOS4_GPIO_D1_START + (_nr))
+
 #define EXYNOS4210_GPE0(_nr)	(EXYNOS4210_GPIO_E0_START + (_nr))
 #define EXYNOS4210_GPE1(_nr)	(EXYNOS4210_GPIO_E1_START + (_nr))
 #define EXYNOS4210_GPE2(_nr)	(EXYNOS4210_GPIO_E2_START + (_nr))
 #define EXYNOS4210_GPE3(_nr)	(EXYNOS4210_GPIO_E3_START + (_nr))
 #define EXYNOS4210_GPE4(_nr)	(EXYNOS4210_GPIO_E4_START + (_nr))
+
 #define EXYNOS4_GPF0(_nr)	(EXYNOS4_GPIO_F0_START + (_nr))
 #define EXYNOS4_GPF1(_nr)	(EXYNOS4_GPIO_F1_START + (_nr))
 #define EXYNOS4_GPF2(_nr)	(EXYNOS4_GPIO_F2_START + (_nr))
@@ -126,6 +145,13 @@ enum exynos4_gpio_number {
 #define EXYNOS4_GPL0(_nr)	(EXYNOS4_GPIO_L0_START + (_nr))
 #define EXYNOS4_GPL1(_nr)	(EXYNOS4_GPIO_L1_START + (_nr))
 #define EXYNOS4_GPL2(_nr)	(EXYNOS4_GPIO_L2_START + (_nr))
+
+#define EXYNOS4X12_GPM0(_nr)	(EXYNOS4X12_GPIO_M0_START + (_nr))
+#define EXYNOS4X12_GPM1(_nr)	(EXYNOS4X12_GPIO_M1_START + (_nr))
+#define EXYNOS4X12_GPM2(_nr)	(EXYNOS4X12_GPIO_M2_START + (_nr))
+#define EXYNOS4X12_GPM3(_nr)	(EXYNOS4X12_GPIO_M3_START + (_nr))
+#define EXYNOS4X12_GPM4(_nr)	(EXYNOS4X12_GPIO_M4_START + (_nr))
+
 #define EXYNOS4_GPX0(_nr)	(EXYNOS4_GPIO_X0_START + (_nr))
 #define EXYNOS4_GPX1(_nr)	(EXYNOS4_GPIO_X1_START + (_nr))
 #define EXYNOS4_GPX2(_nr)	(EXYNOS4_GPIO_X2_START + (_nr))
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 315aa14..c2ad2be 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -168,9 +168,6 @@
 
 #define EXYNOS4_MAX_COMBINER_NR		16
 
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
-
 /*
  * For Compatibility:
  * the default is for EXYNOS4, and
@@ -238,9 +235,6 @@
 #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
 #define IRQ_FIMD0_SYSTEM		EXYNOS4_IRQ_FIMD0_SYSTEM
 
-#define IRQ_GPIO1_NR_GROUPS		EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS		EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
 /* For EXYNOS5 SoCs */
 
 #define EXYNOS5_IRQ_MDMA0		IRQ_SPI(33)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index c996440..b5048f5 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2126,7 +2126,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
  */
 
 #ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_1[] = {
+static struct samsung_gpio_chip exynos4210_gpios_1[] = {
 	{
 		.chip	= {
 			.base	= EXYNOS4_GPA0(0),
@@ -2225,10 +2225,93 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
 		},
 	},
 };
-#endif
 
-#ifdef CONFIG_ARCH_EXYNOS4
-static struct samsung_gpio_chip exynos4_gpios_2[] = {
+static struct samsung_gpio_chip exynos4x12_gpios_1[] = {
+	{
+		.chip	= {
+			.base	= EXYNOS4_GPA0(0),
+			.ngpio	= EXYNOS4_GPIO_A0_NR,
+			.label	= "GPA0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPA1(0),
+			.ngpio	= EXYNOS4_GPIO_A1_NR,
+			.label	= "GPA1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPB(0),
+			.ngpio	= EXYNOS4_GPIO_B_NR,
+			.label	= "GPB",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPC0(0),
+			.ngpio	= EXYNOS4_GPIO_C0_NR,
+			.label	= "GPC0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPC1(0),
+			.ngpio	= EXYNOS4_GPIO_C1_NR,
+			.label	= "GPC1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPD0(0),
+			.ngpio	= EXYNOS4_GPIO_D0_NR,
+			.label	= "GPD0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPD1(0),
+			.ngpio	= EXYNOS4_GPIO_D1_NR,
+			.label	= "GPD1",
+		},
+	}, {
+		.base	= (void *)0x180,
+		.group	= 12,
+		.chip	= {
+			.base	= EXYNOS4_GPF0(0),
+			.ngpio	= EXYNOS4_GPIO_F0_NR,
+			.label	= "GPF0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPF1(0),
+			.ngpio	= EXYNOS4_GPIO_F1_NR,
+			.label	= "GPF1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPF2(0),
+			.ngpio	= EXYNOS4_GPIO_F2_NR,
+			.label	= "GPF2",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPF3(0),
+			.ngpio	= EXYNOS4_GPIO_F3_NR,
+			.label	= "GPF3",
+		},
+	}, {
+		.base	= (void *)0x240,
+		.chip	= {
+			.base	= EXYNOS4_GPJ0(0),
+			.ngpio	= EXYNOS4_GPIO_J0_NR,
+			.label	= "GPJ0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPJ1(0),
+			.ngpio	= EXYNOS4_GPIO_J1_NR,
+			.label	= "GPJ1",
+		},
+	},
+};
+
+static struct samsung_gpio_chip exynos4210_gpios_2[] = {
 	{
 		.chip	= {
 			.base	= EXYNOS4_GPJ0(0),
@@ -2333,6 +2416,172 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
 			.label	= "GPY6",
 		},
 	}, {
+		.base	= (void *)0xC00,
+		.config	= &samsung_gpio_cfgs[9],
+		.irq_base = IRQ_EINT(0),
+		.chip	= {
+			.base	= EXYNOS4_GPX0(0),
+			.ngpio	= EXYNOS4_GPIO_X0_NR,
+			.label	= "GPX0",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[9],
+		.irq_base = IRQ_EINT(8),
+		.chip	= {
+			.base	= EXYNOS4_GPX1(0),
+			.ngpio	= EXYNOS4_GPIO_X1_NR,
+			.label	= "GPX1",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[9],
+		.irq_base = IRQ_EINT(16),
+		.chip	= {
+			.base	= EXYNOS4_GPX2(0),
+			.ngpio	= EXYNOS4_GPIO_X2_NR,
+			.label	= "GPX2",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[9],
+		.irq_base = IRQ_EINT(24),
+		.chip	= {
+			.base	= EXYNOS4_GPX3(0),
+			.ngpio	= EXYNOS4_GPIO_X3_NR,
+			.label	= "GPX3",
+			.to_irq	= samsung_gpiolib_to_irq,
+		},
+	},
+};
+
+static struct samsung_gpio_chip exynos4x12_gpios_2[] = {
+	{
+		.base	= (void *)0x040,
+		.group	= 20,
+		.chip	= {
+			.base	= EXYNOS4_GPK0(0),
+			.ngpio	= EXYNOS4_GPIO_K0_NR,
+			.label	= "GPK0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPK1(0),
+			.ngpio	= EXYNOS4_GPIO_K1_NR,
+			.label	= "GPK1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPK2(0),
+			.ngpio	= EXYNOS4_GPIO_K2_NR,
+			.label	= "GPK2",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPK3(0),
+			.ngpio	= EXYNOS4_GPIO_K3_NR,
+			.label	= "GPK3",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPL0(0),
+			.ngpio	= EXYNOS4_GPIO_L0_NR,
+			.label	= "GPL0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPL1(0),
+			.ngpio	= EXYNOS4_GPIO_L1_NR,
+			.label	= "GPL1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4_GPL2(0),
+			.ngpio	= EXYNOS4_GPIO_L2_NR,
+			.label	= "GPL2",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY0(0),
+			.ngpio	= EXYNOS4_GPIO_Y0_NR,
+			.label	= "GPY0",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY1(0),
+			.ngpio	= EXYNOS4_GPIO_Y1_NR,
+			.label	= "GPY1",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY2(0),
+			.ngpio	= EXYNOS4_GPIO_Y2_NR,
+			.label	= "GPY2",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY3(0),
+			.ngpio	= EXYNOS4_GPIO_Y3_NR,
+			.label	= "GPY3",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY4(0),
+			.ngpio	= EXYNOS4_GPIO_Y4_NR,
+			.label	= "GPY4",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY5(0),
+			.ngpio	= EXYNOS4_GPIO_Y5_NR,
+			.label	= "GPY5",
+		},
+	}, {
+		.config	= &samsung_gpio_cfgs[8],
+		.chip	= {
+			.base	= EXYNOS4_GPY6(0),
+			.ngpio	= EXYNOS4_GPIO_Y6_NR,
+			.label	= "GPY6",
+		},
+	}, {
+		.base	= (void *)0x260,
+		.chip	= {
+			.base	= EXYNOS4X12_GPM0(0),
+			.ngpio	= EXYNOS4X12_GPIO_M0_NR,
+			.label	= "GPM0",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4X12_GPM1(0),
+			.ngpio	= EXYNOS4X12_GPIO_M1_NR,
+			.label	= "GPM1",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4X12_GPM2(0),
+			.ngpio	= EXYNOS4X12_GPIO_M2_NR,
+			.label	= "GPM2",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4X12_GPM3(0),
+			.ngpio	= EXYNOS4X12_GPIO_M3_NR,
+			.label	= "GPM3",
+		},
+	}, {
+		.chip	= {
+			.base	= EXYNOS4X12_GPM4(0),
+			.ngpio	= EXYNOS4X12_GPIO_M4_NR,
+			.label	= "GPM4",
+		},
+	}, {
+		.base	= (void *)0xC00,
 		.config	= &samsung_gpio_cfgs[9],
 		.irq_base = IRQ_EINT(0),
 		.chip	= {
@@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
 		},
 	},
 };
-#endif
 
-#ifdef CONFIG_ARCH_EXYNOS4
 static struct samsung_gpio_chip exynos4_gpios_3[] = {
 	{
 		.chip	= {
@@ -2727,12 +2974,15 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
 
 static __init void exynos4_gpiolib_init(void)
 {
-#ifdef CONFIG_CPU_EXYNOS4210
+#ifdef CONFIG_ARCH_EXYNOS4
 	struct samsung_gpio_chip *chip;
 	int i, nr_chips;
 	void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
 	int group = 0;
 	void __iomem *gpx_base;
+	struct samsung_gpio_chip *chip_p;
+	int offset = 0;
+	int group1 = 0;
 
 	/* gpio part1 */
 	gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
@@ -2741,19 +2991,31 @@ static __init void exynos4_gpiolib_init(void)
 		goto err_ioremap1;
 	}
 
-	chip = exynos4_gpios_1;
-	nr_chips = ARRAY_SIZE(exynos4_gpios_1);
+	if (soc_is_exynos4210()) {
+		chip = chip_p = exynos4210_gpios_1;
+		nr_chips = ARRAY_SIZE(exynos4210_gpios_1);
+	} else {
+		chip = chip_p = exynos4x12_gpios_1;
+		nr_chips = ARRAY_SIZE(exynos4x12_gpios_1);
+	}
 
 	for (i = 0; i < nr_chips; i++, chip++) {
 		if (!chip->config) {
 			chip->config = &exynos_gpio_cfg;
+			if (chip->group)
+				group = chip->group;
 			chip->group = group++;
 		}
-		exynos_gpiolib_attach_ofnode(chip,
-				EXYNOS4_PA_GPIO1, i * 0x20);
+
+		if (chip->base)
+			offset = (u32)chip->base;
+		chip->base = gpio_base1 + offset;
+		offset += 0x20;
+
+		exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO1, 0);
 	}
-	samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
-				       nr_chips, gpio_base1);
+	samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base1);
+	group1 = group;
 
 	/* gpio part2 */
 	gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
@@ -2762,25 +3024,32 @@ static __init void exynos4_gpiolib_init(void)
 		goto err_ioremap2;
 	}
 
-	/* need to set base address for gpx */
-	chip = &exynos4_gpios_2[16];
-	gpx_base = gpio_base2 + 0xC00;
-	for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
-		chip->base = gpx_base;
+	if (soc_is_exynos4210()) {
+		chip = chip_p = exynos4210_gpios_2;
+		nr_chips = ARRAY_SIZE(exynos4210_gpios_2);
+	} else {
+		chip = chip_p = exynos4x12_gpios_2;
+		nr_chips = ARRAY_SIZE(exynos4x12_gpios_2);
+	}
 
-	chip = exynos4_gpios_2;
-	nr_chips = ARRAY_SIZE(exynos4_gpios_2);
+	offset = 0;
 
 	for (i = 0; i < nr_chips; i++, chip++) {
 		if (!chip->config) {
 			chip->config = &exynos_gpio_cfg;
+			if (chip->group)
+				group = chip->group;
 			chip->group = group++;
 		}
-		exynos_gpiolib_attach_ofnode(chip,
-				EXYNOS4_PA_GPIO2, i * 0x20);
+
+		if (chip->base)
+			offset = (u32)chip->base;
+		chip->base = gpio_base2 + offset;
+		offset += 0x20;
+
+		exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO2, 0);
 	}
-	samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
-				       nr_chips, gpio_base2);
+	samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base2);
 
 	/* gpio part3 */
 	gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
@@ -2801,12 +3070,10 @@ static __init void exynos4_gpiolib_init(void)
 				EXYNOS4_PA_GPIO3, i * 0x20);
 	}
 	samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
-				       nr_chips, gpio_base3);
+					nr_chips, gpio_base3);
 
-#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
-	s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
-	s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
-#endif
+	s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, group1);
+	s5p_register_gpioint_bank(IRQ_GPIO_XB, group1, group - group1);
 
 	return;
 
@@ -2816,7 +3083,7 @@ err_ioremap2:
 	iounmap(gpio_base1);
 err_ioremap1:
 	return;
-#endif	/* CONFIG_CPU_EXYNOS4210 */
+#endif	/* CONFIG_ARCH_EXYNOS4 */
 }
 
 static __init void exynos5_gpiolib_init(void)
@@ -3010,7 +3277,8 @@ static __init int samsung_gpiolib_init(void)
 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
 		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
 #endif
-	} else if (soc_is_exynos4210()) {
+	} else if (soc_is_exynos4210() || soc_is_exynos4212() ||
+			soc_is_exynos4412()) {
 		exynos4_gpiolib_init();
 	} else if (soc_is_exynos5250()) {
 		exynos5_gpiolib_init();
-- 
1.7.12




From t.figa at samsung.com  Tue Aug 28 06:07:32 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 12:07:32 +0200
Subject: [PATCH 3/3] ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on
 Exynos4x12
In-Reply-To: <4648723.rWnut7F0uJ@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
Message-ID: <2273077.MFzyvUNijr@amdc1227>

Exynos4x12 SoCs use different GPIO pins for FIMC cam port B and this patch
modifies the setup code to take it into account.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
---
 arch/arm/mach-exynos/setup-fimc.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
index d74843e..4b0cce5 100644
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ b/arch/arm/mach-exynos/setup-fimc.c
@@ -11,6 +11,7 @@
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/camport.h>
+#include <plat/cpu.h>
 
 int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
 {
@@ -26,6 +27,22 @@ int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
 		break;
 
 	case S5P_CAMPORT_B:
+		if (soc_is_exynos4212() || soc_is_exynos4412()) {
+			sfn = S3C_GPIO_SFN(3);
+
+			/* PCLK, DATA[0-6] */
+			ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM0(0), 8, sfn);
+			/* FIELD, DATA[7]*/
+			if (!ret)
+				ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM1(0),
+							       2, sfn);
+			/* VSYNC, HREF, CLKOUT*/
+			if (!ret)
+				ret = s3c_gpio_cfgrange_nopull(EXYNOS4X12_GPM2(0),
+							       3, sfn);
+			return ret;
+		}
+
 		gpio8 = EXYNOS4210_GPE0(0); /* DATA[0:7] */
 		gpio5 = EXYNOS4210_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
 		sfn = S3C_GPIO_SFN(3);
-- 
1.7.12




From gururaja.hebbar at ti.com  Tue Aug 28 06:19:56 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 28 Aug 2012 10:19:56 +0000
Subject: [PATCH V2 5/6] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <20120827181939.GX4339@opensource.wolfsonmicro.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-6-git-send-email-gururaja.hebbar@ti.com>
 <20120827181939.GX4339@opensource.wolfsonmicro.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA6C7AF@DBDE01.ent.ti.com>

On Mon, Aug 27, 2012 at 23:49:40, Mark Brown wrote:
> On Mon, Aug 27, 2012 at 06:56:43PM +0530, Hebbar, Gururaja wrote:
> > Device tree support for tlv320aic3x CODEC driver
> 
> Not really for the CODEC - this is a machine driver.
> 
> > +- dai-data		: A list of DAI data used by SOC code to register
> > +			  DAI, Codecs platform.
> > +			  The string index "should" be as shown below.
> > +dai-data =
> > +"<DAI Name>", 		"<DAI Stream Name>",
> > +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> > +"<evm ops required (evm_ops or evm_spdif_ops)>";
> 
> What do these different ops do - how would the user figure it out or if
> they're needed at all?


Ok. I will correct and send.

Since other patches are accepted. I will send only this patch.
> 


Regards, 
Gururaja


From gururaja.hebbar at ti.com  Tue Aug 28 06:13:50 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Tue, 28 Aug 2012 15:43:50 +0530
Subject: [PATCH V3] ASoC: Davinci: machine: Add device tree binding
Message-ID: <1346148830-2965-1-git-send-email-gururaja.hebbar@ti.com>

Device tree support for Davinci Machine driver

When the board boots with device tree, the driver will receive card,
codec, dai interface details (like the card name, DAPM routing map,
phandle for the audio components described in the dts file, codec mclk
speed).
The card will be set up based on this information.
Since the routing is provided via DT we can mark the card fully routed
so core can take care of disconnecting the unused pins.

When here, code indentation and comment style is also fixed

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
Changes from V1:
	- Change DT parameter from "ti,codec-clock" to "ti,codec-clock-rate"
	- add more explanation to DT parameters

Changes from V2:
	- Update Documentation details
	- Remove irrelevant commit message

:000000 100644 0000000... b248014... A	Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
:100644 100644 ab0ad45... ca2a547... M	sound/soc/davinci/davinci-evm.c
 .../bindings/sound/davinci-evm-audio.txt           |   66 +++++++
 sound/soc/davinci/davinci-evm.c                    |  185 +++++++++++++++++--
 2 files changed, 231 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
new file mode 100644
index 0000000..b248014
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -0,0 +1,66 @@
+* Texas Instruments SoC audio setups with TLV320AIC3X Codec
+
+Required properties:
+- compatible : "ti,davinci-evm-audio"
+- ti,model : The user-visible name of this sound complex.
+- ti,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the codec's pins, and the jacks on the board:
+
+  Codec pins:
+
+  * MIC3L
+  * MIC3R
+  * LINE1L
+  * LINE2L
+  * LINE1R
+  * LINE2R
+
+  Board connectors:
+
+  * Headphone Jack
+  * Line Out
+  * Mic Jack
+
+- ti,mcasp-controller : The phandle of the McASP controller
+- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
+- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
+
+- dai-data		: A list of DAI data used by SOC code to register
+			  DAI, Codecs platform.
+			  The string index "should" be as shown below.
+dai-data =
+"<DAI Name>", 		"<DAI Stream Name>",
+"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
+"<evm ops required (evm_ops or evm_spdif_ops)>";
+
+Here fields
+"<DAI Name>"		: used to indicate the DAI Name
+"<DAI Stream Name>"	: used to indicate the Stream Name
+"<CODEC DAI Name>"	: used to bind the link between Codec DAI and ASOC DAI
+
+Machine related options
+"<true/false>"		: Whether the machine specific initialization
+			: evm_aic3x_init() is required
+
+"<evm ops required>"	: Which hardware ops function is to be used.
+			: (evm_ops or evm_spdif_ops)
+			: use evm-spdif-ops if DAI is working in DIT mode
+			: else use evm-ops. These ops setup hw param callbacks
+			: which are used to setup CODEC/cpu DAI configuration
+			: and codec system clock.
+
+Example:
+
+sound {
+	compatible = "ti,davinci-evm-audio";
+	ti,model = "DA830 EVM";
+	ti,audio-codec = <&tlv320aic3x>;
+	ti,mcasp-controller = <&mcasp1>;
+	ti,codec-clock-rate = <12000000>;
+	dai-data =
+		"TLV320AIC3X", 		"AIC3X",
+		"tlv320aic3x-hifi",	"true",
+		"evm-ops";
+};
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index ab0ad45..ca2a547 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -34,27 +34,38 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_card *soc_card = codec->card;
+	struct device_node *np = soc_card->dev->of_node;
 	int ret = 0;
 	unsigned sysclk;
 
-	/* ASP1 on DM355 EVM is clocked by an external oscillator */
-	if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
-	    machine_is_davinci_dm365_evm())
-		sysclk = 27000000;
-
-	/* ASP0 in DM6446 EVM is clocked by U55, as configured by
-	 * board-dm644x-evm.c using GPIOs from U18.  There are six
-	 * options; here we "know" we use a 48 KHz sample rate.
-	 */
-	else if (machine_is_davinci_evm())
-		sysclk = 12288000;
-
-	else if (machine_is_davinci_da830_evm() ||
-				machine_is_davinci_da850_evm())
-		sysclk = 24576000;
-
-	else
-		return -EINVAL;
+	if (np) {
+		ret = of_property_read_u32(np, "ti,codec-clock-rate", &sysclk);
+		if (ret < 0)
+			return ret;
+	} else {
+		/* ASP1 on DM355 EVM is clocked by an external oscillator */
+		if (machine_is_davinci_dm355_evm() ||
+			machine_is_davinci_dm6467_evm() ||
+			machine_is_davinci_dm365_evm())
+			sysclk = 27000000;
+
+		/*
+		 * ASP0 in DM6446 EVM is clocked by U55, as configured by
+		 * board-dm644x-evm.c using GPIOs from U18.  There are six
+		 * options; here we "know" we use a 48 KHz sample rate.
+		 */
+		else if (machine_is_davinci_evm())
+			sysclk = 12288000;
+
+		else if (machine_is_davinci_da830_evm() ||
+					machine_is_davinci_da850_evm())
+			sysclk = 24576000;
+
+		else
+			return -EINVAL;
+	}
 
 	/* set codec DAI configuration */
 	ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
@@ -127,13 +138,22 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_codec *codec = rtd->codec;
 	struct snd_soc_dapm_context *dapm = &codec->dapm;
+	struct device_node *np = codec->card->dev->of_node;
+	int ret;
 
 	/* Add davinci-evm specific widgets */
 	snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
 				  ARRAY_SIZE(aic3x_dapm_widgets));
 
-	/* Set up davinci-evm specific audio path audio_map */
-	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	if (np) {
+		ret = snd_soc_of_parse_audio_routing(codec->card,
+							"ti,audio-routing");
+		if (ret)
+			return ret;
+	} else {
+		/* Set up davinci-evm specific audio path audio_map */
+		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
+	}
 
 	/* not connected */
 	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
@@ -282,6 +302,113 @@ static struct snd_soc_card da850_snd_soc_card = {
 	.num_links = 1,
 };
 
+#if defined(CONFIG_OF)
+/*
+ * This struct is just used as place holder. It will be filled with
+ * data from dt node
+ */
+static struct snd_soc_dai_link evm_dai = {
+};
+
+/* davinci evm audio machine driver */
+static struct snd_soc_card evm_soc_card = {
+	.owner = THIS_MODULE,
+	.dai_link = &evm_dai,
+	.num_links = 1,
+};
+
+static int davinci_evm_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const char *stringPtr, *propname;
+	u32 val;
+	int ret = 0;
+
+	propname = "dai-data";
+	val = of_property_count_strings(np, propname);
+	if (val < 0)
+		return val;
+
+	ret = of_property_read_string_index(np, propname, 0, &evm_dai.name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 1,
+						&evm_dai.stream_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 2,
+						&evm_dai.codec_dai_name);
+	if (ret < 0)
+		return ret;
+
+	ret = of_property_read_string_index(np, propname, 3, &stringPtr);
+	if (ret < 0)
+		return ret;
+	else
+		if (strcasecmp(stringPtr, "true") == 0)
+			evm_dai.init = evm_aic3x_init;
+
+	ret = of_property_read_string_index(np, propname, 4, &stringPtr);
+	if (ret < 0) {
+		return ret;
+	} else {
+		if (strcasecmp(stringPtr, "evm-ops") == 0)
+			evm_dai.ops = &evm_ops;
+		else if (strcasecmp(stringPtr, "evm-spdif-ops") == 0)
+			evm_dai.ops = &evm_spdif_ops;
+	}
+
+	evm_dai.codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
+	if (!evm_dai.codec_of_node)
+		return -EINVAL;
+
+	evm_dai.cpu_dai_of_node = of_parse_phandle(np,
+						"ti,mcasp-controller", 0);
+	if (!evm_dai.cpu_dai_of_node)
+		return -EINVAL;
+
+	evm_dai.platform_of_node = evm_dai.cpu_dai_of_node;
+
+	evm_soc_card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
+	if (ret)
+		return ret;
+
+	ret = snd_soc_register_card(&evm_soc_card);
+	if (ret)
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+
+	return ret;
+}
+
+static int __devexit davinci_evm_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(card);
+
+	return 0;
+}
+
+static const struct of_device_id davinci_evm_dt_ids[] = {
+	{ .compatible = "ti,davinci-evm-audio", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, davinci_mcasp_dt_ids);
+
+static struct platform_driver davinci_evm_driver = {
+	.probe		= davinci_evm_probe,
+	.remove		= __devexit_p(davinci_evm_remove),
+	.driver		= {
+		.name	= "davinci_evm",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(davinci_evm_dt_ids),
+	},
+};
+#endif
+
 static struct platform_device *evm_snd_device;
 
 static int __init evm_init(void)
@@ -289,6 +416,14 @@ static int __init evm_init(void)
 	struct snd_soc_card *evm_snd_dev_data;
 	int index;
 	int ret;
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		return platform_driver_register(&davinci_evm_driver);
+	}
+#endif
 
 	if (machine_is_davinci_evm()) {
 		evm_snd_dev_data = &dm6446_snd_soc_card_evm;
@@ -325,6 +460,16 @@ static int __init evm_init(void)
 
 static void __exit evm_exit(void)
 {
+#if defined(CONFIG_OF)
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
+	if (np) {
+		platform_driver_unregister(&davinci_evm_driver);
+		return;
+	}
+#endif
+
 	platform_device_unregister(evm_snd_device);
 }
 
-- 
1.7.1



From mkl at pengutronix.de  Tue Aug 28 06:31:25 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Tue, 28 Aug 2012 12:31:25 +0200
Subject: [PATCH] usb: chipidea: cleanup dma_pool if udc_start() fails
Message-ID: <1346149885-3084-1-git-send-email-mkl@pengutronix.de>

If udc_start() fails the qh_pool dma-pool cannot be closed because
it's still in use. This patch factors out the dma_pool_free() loop
into destroy_eps() and calls it in the error path of udc_start(),
too.

Cc: Richard Zhao <richard.zhao at freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
---
Hello,

Richard, can you please include this patch in your stack. IIRC I think it once
was, but now it's not anymore.

regards, Marc

 drivers/usb/chipidea/udc.c |   23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 2cb4498..0b18191 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1507,6 +1507,17 @@ static int init_eps(struct ci13xxx *ci)
 	return retval;
 }
 
+static void destroy_eps(struct ci13xxx *ci)
+{
+	int i;
+
+	for (i = 0; i < ci->hw_ep_max; i++) {
+		struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
+
+		dma_pool_free(ci->qh_pool, mEp->qh.ptr, mEp->qh.dma);
+	}
+}
+
 /**
  * ci13xxx_start: register a gadget driver
  * @gadget: our gadget
@@ -1723,7 +1734,7 @@ static int udc_start(struct ci13xxx *ci)
 	if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
 		if (ci->transceiver == NULL) {
 			retval = -ENODEV;
-			goto free_pools;
+			goto destroy_eps;
 		}
 	}
 
@@ -1775,6 +1786,8 @@ unreg_device:
 put_transceiver:
 	if (!IS_ERR_OR_NULL(ci->transceiver) && ci->global_phy)
 		usb_put_phy(ci->transceiver);
+destroy_eps:
+	destroy_eps(ci);
 free_pools:
 	dma_pool_destroy(ci->td_pool);
 free_qh_pool:
@@ -1790,8 +1803,6 @@ free_qh_pool:
  */
 static void udc_stop(struct ci13xxx *ci)
 {
-	int i;
-
 	if (ci == NULL)
 		return;
 
@@ -1800,11 +1811,7 @@ static void udc_stop(struct ci13xxx *ci)
 
 	usb_del_gadget_udc(&ci->gadget);
 
-	for (i = 0; i < ci->hw_ep_max; i++) {
-		struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
-
-		dma_pool_free(ci->qh_pool, mEp->qh.ptr, mEp->qh.dma);
-	}
+	destroy_eps(ci);
 
 	dma_pool_destroy(ci->td_pool);
 	dma_pool_destroy(ci->qh_pool);
-- 
1.7.10.4



From gcembed at gmail.com  Tue Aug 28 06:33:30 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Tue, 28 Aug 2012 12:33:30 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <1345825064-9147-1-git-send-email-gcembed@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
Message-ID: <503C9E7A.7060401@gmail.com>

Hi,
Any comments for this patch ?
Regards,
Ga?tan Carlier.

On 08/24/2012 06:17 PM, Ga?tan Carlier wrote:
> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> Warning: The same solution needs to be applied to the boot loader and the
> flash programmer.
>
> This is a modified version of patch sent by J?rgen Lambrecht :
> [PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block Indicator,
> and use for imx27pdk nand support.
>
>   v3: - use accessor function for I/O memory accesses as suggested by Artem
>         Bityutskiy
>       - rename function name as suggested by Artem Bityutskiy
>
>   v2: - Use a flag in a mxc_nand_platform structure instead of adding option
>         in Kconfig
>
>   v1: - Original patch "Add 'config IMX_NFC_V1_BISWAP'" by J?rgen Lambrecht
>
> Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
> ---
>   arch/arm/plat-mxc/include/mach/mxc_nand.h |    2 ++
>   drivers/mtd/nand/mxc_nand.c               |   26 ++++++++++++++++++++++++++
>   2 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
> index 6bb96ef..7c04437 100644
> --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
> +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
> @@ -26,6 +26,8 @@ struct mxc_nand_platform_data {
>   	unsigned int width;	/* data bus width in bytes */
>   	unsigned int hw_ecc:1;	/* 0 if suppress hardware ECC */
>   	unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
> +	unsigned int biswap:1;	/* set to 1 to swap the Bad Block Indicator
> +				   NFC v1 workaround */
>   	struct mtd_partition *parts;	/* partition table */
>   	int nr_parts;			/* size of parts */
>   };
> diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
> index 3f94e1f..24fc9e1 100644
> --- a/drivers/mtd/nand/mxc_nand.c
> +++ b/drivers/mtd/nand/mxc_nand.c
> @@ -682,6 +682,26 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
>   	return 0;
>   }
>
> +/*
> + * Swap the BI-byte on position 0x7D0 with a data byte at 0x835.
> + * To fix a bug in NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> + * Warning: The same solution needs to be applied to the boot loader and the
> + * flash programmer.
> + */
> +static void nfcv1_bi_swap_quirk(struct mtd_info *mtd)
> +{
> +	struct nand_chip *nand_chip = mtd->priv;
> +	struct mxc_nand_host *host = nand_chip->priv;
> +	unsigned short temp1, temp2, new_temp1;
> +
> +	temp1 = ioread16(host->main_area0 + 0x7D0);
> +	temp2 = ioread16(host->main_area0 + 0x834);
> +	new_temp1 = (temp1 & 0xFF00) | (temp2 >> 8);
> +	temp2 = (temp2 & 0x00FF) | (temp1 << 8);
> +	iowrite16(new_temp1, host->main_area0 + 0x7D0);
> +	iowrite16(temp2, host->main_area0 + 0x834);
> +}
> +
>   static u_char mxc_nand_read_byte(struct mtd_info *mtd)
>   {
>   	struct nand_chip *nand_chip = mtd->priv;
> @@ -1093,6 +1113,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
>
>   		host->devtype_data->send_page(mtd, NFC_OUTPUT);
>
> +		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
> +			nfcv1_bi_swap_quirk(mtd);
> +
>   		memcpy32_fromio(host->data_buf, host->main_area0,
>   				mtd->writesize);
>   		copy_spare(mtd, true);
> @@ -1112,6 +1135,9 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
>   	case NAND_CMD_PAGEPROG:
>   		memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
>   		copy_spare(mtd, false);
> +		if ((mtd->writesize > 512) && nfc_is_v1() && host->pdata.biswap)
> +			nfcv1_bi_swap_quirk(mtd);
> +
>   		host->devtype_data->send_page(mtd, NFC_INPUT);
>   		host->devtype_data->send_cmd(host, command, true);
>   		mxc_do_addr_cycle(mtd, column, page_addr);
>



From richard.zhao at freescale.com  Tue Aug 28 06:46:18 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 18:46:18 +0800
Subject: [PATCH] usb: chipidea: cleanup dma_pool if udc_start() fails
In-Reply-To: <1346149885-3084-1-git-send-email-mkl@pengutronix.de>
References: <1346149885-3084-1-git-send-email-mkl@pengutronix.de>
Message-ID: <20120828104617.GZ4011@b20223-02.ap.freescale.net>

On Tue, Aug 28, 2012 at 12:31:25PM +0200, Marc Kleine-Budde wrote:
> If udc_start() fails the qh_pool dma-pool cannot be closed because
> it's still in use. This patch factors out the dma_pool_free() loop
> into destroy_eps() and calls it in the error path of udc_start(),
> too.
> 
> Cc: Richard Zhao <richard.zhao at freescale.com>
> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
> ---
> Hello,
> 
> Richard, can you please include this patch in your stack. IIRC I think it once
> was, but now it's not anymore.
Sorry for that. I just push it to my topics/usb-driver branch.
Of course, it's better, if Alex can give a ACK and Greg could pick up.

Thanks
Richard
> 
> regards, Marc
> 
>  drivers/usb/chipidea/udc.c |   23 +++++++++++++++--------
>  1 file changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 2cb4498..0b18191 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -1507,6 +1507,17 @@ static int init_eps(struct ci13xxx *ci)
>  	return retval;
>  }
>  
> +static void destroy_eps(struct ci13xxx *ci)
> +{
> +	int i;
> +
> +	for (i = 0; i < ci->hw_ep_max; i++) {
> +		struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
> +
> +		dma_pool_free(ci->qh_pool, mEp->qh.ptr, mEp->qh.dma);
> +	}
> +}
> +
>  /**
>   * ci13xxx_start: register a gadget driver
>   * @gadget: our gadget
> @@ -1723,7 +1734,7 @@ static int udc_start(struct ci13xxx *ci)
>  	if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
>  		if (ci->transceiver == NULL) {
>  			retval = -ENODEV;
> -			goto free_pools;
> +			goto destroy_eps;
>  		}
>  	}
>  
> @@ -1775,6 +1786,8 @@ unreg_device:
>  put_transceiver:
>  	if (!IS_ERR_OR_NULL(ci->transceiver) && ci->global_phy)
>  		usb_put_phy(ci->transceiver);
> +destroy_eps:
> +	destroy_eps(ci);
>  free_pools:
>  	dma_pool_destroy(ci->td_pool);
>  free_qh_pool:
> @@ -1790,8 +1803,6 @@ free_qh_pool:
>   */
>  static void udc_stop(struct ci13xxx *ci)
>  {
> -	int i;
> -
>  	if (ci == NULL)
>  		return;
>  
> @@ -1800,11 +1811,7 @@ static void udc_stop(struct ci13xxx *ci)
>  
>  	usb_del_gadget_udc(&ci->gadget);
>  
> -	for (i = 0; i < ci->hw_ep_max; i++) {
> -		struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
> -
> -		dma_pool_free(ci->qh_pool, mEp->qh.ptr, mEp->qh.dma);
> -	}
> +	destroy_eps(ci);
>  
>  	dma_pool_destroy(ci->td_pool);
>  	dma_pool_destroy(ci->qh_pool);
> -- 
> 1.7.10.4
> 
> 



From dirk.behme at de.bosch.com  Tue Aug 28 06:46:27 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Tue, 28 Aug 2012 12:46:27 +0200
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled
 console
In-Reply-To: <503BBA5A.8040609@boundarydevices.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>
 <503BBA5A.8040609@boundarydevices.com>
Message-ID: <503CA183.70704@de.bosch.com>

On 27.08.2012 20:20, Troy Kisky wrote:
> On 8/27/2012 12:36 AM, Dirk Behme wrote:
>> From: Xinyu Chen <xinyu.chen at freescale.com>
>>
>> Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
>> as this will cause clock reinit, and output garbage.
>>
>> This patch is a port from Freescale's Android kernel.
>>
>> Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
>> Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
>> CC: Shawn Guo <shawn.guo at linaro.org>
>> CC: Sascha Hauer <s.hauer at pengutronix.de>
>> ---
>>   drivers/tty/serial/imx.c |    2 ++
>>   1 files changed, 2 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
>> index 908178f..31ce414 100644
>> --- a/drivers/tty/serial/imx.c
>> +++ b/drivers/tty/serial/imx.c
>> @@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
>>   	int retval;
>>   	unsigned long flags, temp;
>>   
>> +#ifndef CONFIG_SERIAL_CORE_CONSOLE
>>   	imx_setup_ufcr(sport, 0);
>> +#endif
>>   
>>   	/* disable the DREN bit (Data Ready interrupt enable) before
>>   	 * requesting IRQs
> 
> 
> I'd rather do something like this
> 
> static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
> {
>          unsigned int val;
> 
>          /* set receiver / transmitter trigger level. */
>          val = readl(sport->port.membase + UFCR) & UFCR_RFDIV;

Shouldn't it be

... & (UFCR_RFDIV | UFCR_DCEDTE);

then? My i.MX6 manual has DCEDTE as bit 6, which we don't want to touch, 
too? We only want to touch TXTL and RXTL?

>          val |= TXTL << 10 | RXTL;
>          writel(val, sport->port.membase + UFCR);
>          return 0;
> }
> 
> There is no need for imx_setup_ufcr to change divisor.

Ok

Thanks

Dirk


From mkl at pengutronix.de  Tue Aug 28 06:52:19 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Tue, 28 Aug 2012 12:52:19 +0200
Subject: [PATCH] usb: chipidea: cleanup dma_pool if udc_start() fails
In-Reply-To: <20120828104617.GZ4011@b20223-02.ap.freescale.net>
References: <1346149885-3084-1-git-send-email-mkl@pengutronix.de>
 <20120828104617.GZ4011@b20223-02.ap.freescale.net>
Message-ID: <503CA2E3.6010707@pengutronix.de>

On 08/28/2012 12:46 PM, Richard Zhao wrote:
> On Tue, Aug 28, 2012 at 12:31:25PM +0200, Marc Kleine-Budde wrote:
>> If udc_start() fails the qh_pool dma-pool cannot be closed because
>> it's still in use. This patch factors out the dma_pool_free() loop
>> into destroy_eps() and calls it in the error path of udc_start(),
>> too.
>>
>> Cc: Richard Zhao <richard.zhao at freescale.com>
>> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
>> ---
>> Hello,
>>
>> Richard, can you please include this patch in your stack. IIRC I think it once
>> was, but now it's not anymore.
> Sorry for that. I just push it to my topics/usb-driver branch.
> Of course, it's better, if Alex can give a ACK and Greg could pick up.

I'm not sure, if this [1] is the latest thread on this patch, but Greg
asked to queue this patch into your tree.

Marc

[1] http://comments.gmane.org/gmane.linux.usb.general/66440
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From t.figa at samsung.com  Tue Aug 28 07:08:28 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 13:08:28 +0200
Subject: [PATCH] ARM: EXYNOS: Use non-secure MDMA1
Message-ID: <5886686.Vz6SVkoRWm@amdc1227>

Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
so use non-secure instead.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/dma.c              | 2 +-
 arch/arm/mach-exynos/include/mach/map.h | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66d..8858df5 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata = {
 };
 
 static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
-	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
+	EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
 
 static int __init exynos_dma_init(void)
 {
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
exynos/include/mach/map.h
index 51943f2..5df5910 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,8 @@
 #define EXYNOS4_PA_L2CC			0x10502000
 
 #define EXYNOS4_PA_MDMA0		0x10810000
-#define EXYNOS4_PA_MDMA1		0x12840000
+#define EXYNOS4_PA_S_MDMA1		0x12840000
+#define EXYNOS4_PA_NS_MDMA1		0x12850000
 #define EXYNOS4_PA_PDMA0		0x12680000
 #define EXYNOS4_PA_PDMA1		0x12690000
 #define EXYNOS5_PA_MDMA0		0x10800000
-- 
1.7.12




From gcembed at gmail.com  Tue Aug 28 07:09:10 2012
From: gcembed at gmail.com (=?UTF-8?q?Ga=C3=ABtan=20Carlier?=)
Date: Tue, 28 Aug 2012 13:09:10 +0200
Subject: [PATCH] MFD : MC13783 : add regulators sw1x and sw2x
Message-ID: <1346152150-21669-1-git-send-email-gcembed@gmail.com>


Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>
---
 drivers/regulator/mc13783-regulator.c |   66 +++++++++++++++++++++++++++++++++
 1 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/drivers/regulator/mc13783-regulator.c b/drivers/regulator/mc13783-regulator.c
index 4977b19..0801a6d 100644
--- a/drivers/regulator/mc13783-regulator.c
+++ b/drivers/regulator/mc13783-regulator.c
@@ -21,6 +21,30 @@
 #include <linux/module.h>
 #include "mc13xxx.h"
 
+#define MC13783_REG_SWITCHERS0			24
+/* Enable does not exist for SW1A */
+#define MC13783_REG_SWITCHERS0_SW1AEN			0
+#define MC13783_REG_SWITCHERS0_SW1AVSEL			0
+#define MC13783_REG_SWITCHERS0_SW1AVSEL_M		(63 << 0)
+
+#define MC13783_REG_SWITCHERS1			25
+/* Enable does not exist for SW1B */
+#define MC13783_REG_SWITCHERS1_SW1BEN			0
+#define MC13783_REG_SWITCHERS1_SW1BVSEL			0
+#define MC13783_REG_SWITCHERS1_SW1BVSEL_M		(63 << 0)
+
+#define MC13783_REG_SWITCHERS2			26
+/* Enable does not exist for SW2A */
+#define MC13783_REG_SWITCHERS2_SW2AEN			0
+#define MC13783_REG_SWITCHERS2_SW2AVSEL			0
+#define MC13783_REG_SWITCHERS2_SW2AVSEL_M		(63 << 0)
+
+#define MC13783_REG_SWITCHERS3			27
+/* Enable does not exist for SW2B */
+#define MC13783_REG_SWITCHERS3_SW2BEN			0
+#define MC13783_REG_SWITCHERS3_SW2BVSEL			0
+#define MC13783_REG_SWITCHERS3_SW2BVSEL_M		(63 << 0)
+
 #define MC13783_REG_SWITCHERS5			29
 #define MC13783_REG_SWITCHERS5_SW3EN			(1 << 20)
 #define MC13783_REG_SWITCHERS5_SW3VSEL			18
@@ -93,6 +117,44 @@
 
 
 /* Voltage Values */
+static const int mc13783_sw1x_val[] = {
+	900000, 925000, 950000, 975000,
+	1000000, 1025000, 1050000, 1075000,
+	1100000, 1125000, 1150000, 1175000,
+	1200000, 1225000, 1250000, 1275000,
+	1300000, 1325000, 1350000, 1375000,
+	1400000, 1425000, 1450000, 1475000,
+	1500000, 1525000, 1550000, 1575000,
+	1600000, 1625000, 1650000, 1675000,
+	1700000, 1700000, 1700000, 1700000,
+	1800000, 1800000, 1800000, 1800000,
+	1850000, 1850000, 1850000, 1850000,
+	2000000, 2000000, 2000000, 2000000,
+	2100000, 2100000, 2100000, 2100000,
+	2200000, 2200000, 2200000, 2200000,
+	2200000, 2200000, 2200000, 2200000,
+	2200000, 2200000, 2200000, 2200000,
+};
+
+static const int mc13783_sw2x_val[] = {
+	900000, 925000, 950000, 975000,
+	1000000, 1025000, 1050000, 1075000,
+	1100000, 1125000, 1150000, 1175000,
+	1200000, 1225000, 1250000, 1275000,
+	1300000, 1325000, 1350000, 1375000,
+	1400000, 1425000, 1450000, 1475000,
+	1500000, 1525000, 1550000, 1575000,
+	1600000, 1625000, 1650000, 1675000,
+	1700000, 1700000, 1700000, 1700000,
+	1800000, 1800000, 1800000, 1800000,
+	1900000, 1900000, 1900000, 1900000,
+	2000000, 2000000, 2000000, 2000000,
+	2100000, 2100000, 2100000, 2100000,
+	2200000, 2200000, 2200000, 2200000,
+	2200000, 2200000, 2200000, 2200000,
+	2200000, 2200000, 2200000, 2200000,
+};
+
 static const unsigned int mc13783_sw3_val[] = {
 	5000000, 5000000, 5000000, 5500000,
 };
@@ -188,6 +250,10 @@ static struct regulator_ops mc13783_gpo_regulator_ops;
 	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
 
 static struct mc13xxx_regulator mc13783_regulators[] = {
+	MC13783_DEFINE_SW(SW1A, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
+	MC13783_DEFINE_SW(SW1B, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
+	MC13783_DEFINE_SW(SW2A, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
+	MC13783_DEFINE_SW(SW2B, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
 	MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
 
 	MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
-- 
1.7.7.4



From t.figa at samsung.com  Tue Aug 28 07:13:40 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 13:13:40 +0200
Subject: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on
 Exynos4412
Message-ID: <1422318.SfZfh0XoVo@amdc1227>

Exynos4412 uses different information register for each core. This patch
adjusts the bring-up code to take that into account.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/platsmp.c | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..1114ced 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline volatile void *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline volatile void *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*
  * control for which core is the next to come out of the secondary
@@ -138,7 +149,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+							cpu_boot_reg(cpu));
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
@@ -186,6 +197,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int i;
+
 	if (!soc_is_exynos5250())
 		scu_enable(scu_base_addr());
 
@@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i) {
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+							cpu_boot_reg(i));
+	}
 }
-- 
1.7.12




From wni at nvidia.com  Tue Aug 28 07:13:33 2012
From: wni at nvidia.com (Wei Ni)
Date: Tue, 28 Aug 2012 19:13:33 +0800
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly
 for non-OOB
In-Reply-To: <503BD345.6030501@wwwdotorg.org>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com>  <503BD345.6030501@wwwdotorg.org>
Message-ID: <1346152413.3516.211.camel@tegra-chromium-2>

On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
> > On 08/27/2012 12:25 PM, Wei Ni wrote:
> >> In case of inband interrupts, if we handle the interrupt in dpc thread,
> >> two level of thread switching takes place to process wifi interrupts.
> >> One in SDHCI driver and the other in Wifi driver. This may cause the
> >> system
> >> instability.
> > 
> > Looking into the sdhci/mmc code indeed shows that the brcmfmac irq
> > handler is not called in true IRQ context. So the dpc thread may add
> > unnecessary complexity, but to me there is not indication that there is
> > a stability issue.

The brcmfmac irq handler is called in the thread sdio_irq_thread(), this
thread indeed is driven by the sdhci irq, although it's not the true IRQ
context. If the brcmfmac doesn't clear the IRQ condition ASAP, the
sdio_irq_thread will be triggered again and again, and in this condition
it's too difficult to run the brcmfmac dpc thread, more and more
interrupt can't be handled.

> > 
> >> Because the SDHCI calls sdio_irq_thread() to handle the irq, this
> >> thread locks
> >> mmc host and calls wifi handler. It expects WiFi handler to be quick and
> >> enables sdio interrupt from card at end. If wifi handler defers this
> >> work for
> >> a different thread, sdio_irq_thread() will be stuck on next wifi
> >> interrupt
> >> since mmc lock is not freed.
> > 
> > Not sure if I can follow this explanation. The isr is called with host
> > claimed (by sdio_irq_thread) and all it does is at a linked list member
> > and signal the dpc thread. After doing this the host is released.
> 
> Is the issue something like the ISR handler or first level of threading
> does:
> 
> * Trigger DPC
> * Re-enable interrupt
> 
> So that the interrupt then fires again before the triggered DPC can run
> to handle/clear it, thus causing an interrupt storm?
> 
> Whereas handling the interrupt directly prevents this race condition?

Above is my understanding.




From lee.jones at linaro.org  Tue Aug 28 07:26:07 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Tue, 28 Aug 2012 12:26:07 +0100
Subject: [PATCH RESEND 1/4] ARM: OMAP2+: AM33XX: Add tps65910 device tree
 data
In-Reply-To: <20120723133400.GU4435@opensource.wolfsonmicro.com>
References: <1342766789-28148-1-git-send-email-anilkumar@ti.com>
 <1342766789-28148-2-git-send-email-anilkumar@ti.com>
 <20120720095935.GQ4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13E9FA91E@DBDE01.ent.ti.com>
 <20120720113806.GW4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA01F1E@DBDE01.ent.ti.com>
 <20120723133400.GU4435@opensource.wolfsonmicro.com>
Message-ID: <20120828112603.GC25786@gmail.com>

Hi Mark,

> > arch/arm/boot/dts/db8500.dtsi
> 
> I'm not actually seeing anything terribly problematic here, though the
> regulator-name properties should really be removed as they're fairly
> useless and seem to be missing the point of having the property.

Just looking at this now. 

The regulator-name property is used to populate constrains->name. Are
you sure you still want them all removed?

Kind regards,
Lee

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From richard.zhao at freescale.com  Tue Aug 28 07:42:36 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Tue, 28 Aug 2012 19:42:36 +0800
Subject: [PATCH] usb: chipidea: cleanup dma_pool if udc_start() fails
In-Reply-To: <503CA2E3.6010707@pengutronix.de>
References: <1346149885-3084-1-git-send-email-mkl@pengutronix.de>
 <20120828104617.GZ4011@b20223-02.ap.freescale.net>
 <503CA2E3.6010707@pengutronix.de>
Message-ID: <20120828114235.GA4011@b20223-02.ap.freescale.net>

On Tue, Aug 28, 2012 at 12:52:19PM +0200, Marc Kleine-Budde wrote:
> On 08/28/2012 12:46 PM, Richard Zhao wrote:
> > On Tue, Aug 28, 2012 at 12:31:25PM +0200, Marc Kleine-Budde wrote:
> >> If udc_start() fails the qh_pool dma-pool cannot be closed because
> >> it's still in use. This patch factors out the dma_pool_free() loop
> >> into destroy_eps() and calls it in the error path of udc_start(),
> >> too.
> >>
> >> Cc: Richard Zhao <richard.zhao at freescale.com>
> >> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
> >> ---
> >> Hello,
> >>
> >> Richard, can you please include this patch in your stack. IIRC I think it once
> >> was, but now it's not anymore.
> > Sorry for that. I just push it to my topics/usb-driver branch.
> > Of course, it's better, if Alex can give a ACK and Greg could pick up.
> 
> I'm not sure, if this [1] is the latest thread on this patch, but Greg
> asked to queue this patch into your tree.
It does not depends on my tree any more. It can be applied directly on
Greg's tree.

Thanks
Richard
> 
> Marc
> 
> [1] http://comments.gmane.org/gmane.linux.usb.general/66440
> -- 
> Pengutronix e.K.                  | Marc Kleine-Budde           |
> Industrial Linux Solutions        | Phone: +49-231-2826-924     |
> Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
> Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |
> 





From hdoyu at nvidia.com  Tue Aug 28 07:43:51 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 14:43:51 +0300
Subject: [PATCH 3/4] ARM: dma-mapping: Refrain noisy console message
In-Reply-To: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
References: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346154232-13299-3-git-send-email-hdoyu@nvidia.com>

With many IOMMU'able devices, console gets noisy.

Tegra30 has a few dozen of IOMMU'able devices.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 8cb9542..2621282 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1747,7 +1747,7 @@ int arm_iommu_attach_device(struct device *dev,
 	dev->archdata.mapping = mapping;
 	set_dma_ops(dev, &iommu_ops);
 
-	pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev));
+	pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
 	return 0;
 }
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Tue Aug 28 07:43:49 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 14:43:49 +0300
Subject: [PATCH 1/4] ARM: dma-mapping: Small logical clean up
Message-ID: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>

Skip unnecessary operations if order == 0. A little bit easier to
read.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 70a6275..aaea5e4 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1032,11 +1032,12 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
 		if (!pages[i])
 			goto error;
 
-		if (order)
+		if (order) {
 			split_page(pages[i], order);
-		j = 1 << order;
-		while (--j)
-			pages[i + j] = pages[i] + j;
+			j = 1 << order;
+			while (--j)
+				pages[i + j] = pages[i] + j;
+		}
 
 		__dma_clear_buffer(pages[i], PAGE_SIZE << order);
 		i += 1 << order;
-- 
1.7.5.4



From hdoyu at nvidia.com  Tue Aug 28 07:43:50 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 14:43:50 +0300
Subject: [PATCH 2/4] ARM: dma-mapping: Remove unsed var at
 arm_coherent_iommu_unmap_page
In-Reply-To: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
References: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346154232-13299-2-git-send-email-hdoyu@nvidia.com>

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index aaea5e4..8cb9542 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1557,7 +1557,6 @@ static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 {
 	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
 	dma_addr_t iova = handle & PAGE_MASK;
-	struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
 	int offset = handle & ~PAGE_MASK;
 	int len = PAGE_ALIGN(size + offset);
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Tue Aug 28 07:43:52 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 14:43:52 +0300
Subject: [PATCH 4/4] ARM: dma-mapping: Skip cache maint for invalid page
In-Reply-To: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
References: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346154232-13299-4-git-send-email-hdoyu@nvidia.com>

Skip cache maint for invalid page but warn it.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 2621282..0368702 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1589,6 +1589,9 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 	if (!iova)
 		return;
 
+	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
+		return;
+
 	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
 		__dma_page_dev_to_cpu(page, offset, size, dir);
 
@@ -1607,6 +1610,9 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
 	if (!iova)
 		return;
 
+	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
+		return;
+
 	__dma_page_dev_to_cpu(page, offset, size, dir);
 }
 
@@ -1621,6 +1627,9 @@ static void arm_iommu_sync_single_for_device(struct device *dev,
 	if (!iova)
 		return;
 
+	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
+		return;
+
 	__dma_page_cpu_to_dev(page, offset, size, dir);
 }
 
-- 
1.7.5.4



From festevam at gmail.com  Tue Aug 28 07:47:10 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 28 Aug 2012 08:47:10 -0300
Subject: [PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <20120828074533.GV26594@pengutronix.de>
References: <1345385346-25412-1-git-send-email-festevam@gmail.com>
 <20120828074533.GV26594@pengutronix.de>
Message-ID: <CAOMZO5AGCf_9Hzj=6F_u9oK7RAR_ppdm0QhYxht5PPHZ7_-GfQ@mail.gmail.com>

On 8/28/12, Sascha Hauer <s.hauer at pengutronix.de> wrote:


> Applied and added stable tag (I assume this should go to stable, right?)

Yes, please apply v2 version and you can add the stable tag (only
applies to 3.5 stable branch though).

Thanks,

Fabio Estevam


From s.hauer at pengutronix.de  Tue Aug 28 07:48:15 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:15 +0200
Subject: i.MX pwm patches
Message-ID: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>

Hi All,

The following patches are an overdue work on the i.MX pwm driver.

- introduce SoC specific functions to make the driver easier to maintain
- use peripheral clock for pwm output unconditionally
- separate the two clocks this module has
- enable ipg clock for register accesses, peripheral clock for enabling
  the pwm
- make the driver safe for calling pwm_config before pwm_enable
- Add devicetree support for i.MX53

The platform device support is still implemented using cpu_is_*, I think
this can be dropped completely soon as this driver has no in kernel users
currently, so there should be no need to keep compatibility for platform
based boards.

Hopefully this series fixes the issues mentioned by Beno?t. It has been
tested on an i.MX53 only.

Sascha

----------------------------------------------------------------
Philipp Zabel (3):
      pwm i.MX: add devicetree support
      pwm i.MX: fix clock lookup
      pwm i.MX: add devicetree support

Sascha Hauer (6):
      pwm i.MX: factor out SoC specific functions
      pwm i.MX: remove unnecessary if in pwm_[en|dis]able
      pwm i.MX: add functions to enable/disable pwm.
      pwm i.MX: Use module_platform_driver
      pwm i.MX: use per clock unconditionally
      ARM i.MX53: Add pwms to dtsi

 arch/arm/boot/dts/imx53.dtsi        |   14 ++
 arch/arm/mach-imx/clk-imx51-imx53.c |    4 +
 drivers/pwm/pwm-imx.c               |  278 +++++++++++++++++++++++------------
 3 files changed, 202 insertions(+), 94 deletions(-)


From s.hauer at pengutronix.de  Tue Aug 28 07:48:24 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:24 +0200
Subject: [PATCH 9/9] pwm i.MX: add devicetree support
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-10-git-send-email-s.hauer@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 308ab51..dce2acb 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -206,9 +206,25 @@ static struct pwm_ops imx_pwm_ops = {
 	.owner = THIS_MODULE,
 };
 
+struct imx_pwm_data {
+	int (*config)(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns);
+	void (*set_enable)(struct pwm_chip *chip, bool enable);
+};
+
+static struct imx_pwm_data imx_pwm_data_v1 = {
+	.config = imx_pwm_config_v1,
+	.set_enable = imx_pwm_set_enable_v1,
+};
+
+static struct imx_pwm_data imx_pwm_data_v2 = {
+	.config = imx_pwm_config_v2,
+	.set_enable = imx_pwm_set_enable_v2,
+};
+
 static const struct of_device_id imx_pwm_dt_ids[] = {
-	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_config_v1, },
-	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_config_v2, },
+	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
+	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, imx_pwm_of_match);
@@ -257,7 +273,9 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 		return -EADDRNOTAVAIL;
 
 	if (of_id) {
-		imx->config = of_id->data;
+		struct imx_pwm_data *data = of_id->data;
+		imx->config = data->config;
+		imx->set_enable = data->set_enable;
 	} else {
 		if (cpu_is_mx1() || cpu_is_mx21()) {
 			imx->config = imx_pwm_config_v1;
@@ -290,6 +308,7 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
 static struct platform_driver imx_pwm_driver = {
 	.driver		= {
 		.name	= "mxc_pwm",
+		.of_match_table = of_match_ptr(imx_pwm_dt_ids),
 	},
 	.probe		= imx_pwm_probe,
 	.remove		= __devexit_p(imx_pwm_remove),
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:17 +0200
Subject: [PATCH 2/9] pwm i.MX: remove unnecessary if in pwm_[en|dis]able
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-3-git-send-email-s.hauer@pengutronix.de>

The pwm core makes sure that pwm_enable/disable are called only
once. Still keep the enabled state since we will need it in
pwm_config.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 38270f4..0f244e6 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -42,7 +42,7 @@
 struct imx_chip {
 	struct clk	*clk;
 
-	int		clk_enabled;
+	int		enabled;
 	void __iomem	*mmio_base;
 
 	struct pwm_chip	chip;
@@ -138,14 +138,15 @@ static int imx_pwm_config(struct pwm_chip *chip,
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
-	int rc = 0;
+	int rc;
 
-	if (!imx->clk_enabled) {
-		rc = clk_prepare_enable(imx->clk);
-		if (!rc)
-			imx->clk_enabled = 1;
-	}
-	return rc;
+	rc = clk_prepare_enable(imx->clk);
+	if (rc)
+		return rc;
+
+	imx->enabled = 1;
+
+	return 0;
 }
 
 static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
@@ -154,10 +155,8 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 
 	writel(0, imx->mmio_base + MX3_PWMCR);
 
-	if (imx->clk_enabled) {
-		clk_disable_unprepare(imx->clk);
-		imx->clk_enabled = 0;
-	}
+	clk_disable_unprepare(imx->clk);
+	imx->enabled = 0;
 }
 
 static struct pwm_ops imx_pwm_ops = {
@@ -189,8 +188,6 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	imx->chip.base = -1;
 	imx->chip.npwm = 1;
 
-	imx->clk_enabled = 0;
-
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
 		dev_err(&pdev->dev, "no memory resource defined\n");
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:23 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:23 +0200
Subject: [PATCH 8/9] ARM i.MX53: Add pwms to dtsi
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-9-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Conflicts:
	arch/arm/mach-imx/clk-imx51-imx53.c
---
 arch/arm/boot/dts/imx53.dtsi        |   14 ++++++++++++++
 arch/arm/mach-imx/clk-imx51-imx53.c |    4 ++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165..7ec17e4 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -189,6 +189,20 @@
 				status = "disabled";
 			};
 
+			pwm1: pwm at 53fb4000 {
+				#pwm-cells = <3>;
+				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+				reg = <0x53fb4000 0x4000>;
+				interrupts = <61>;
+			};
+
+			pwm2: pwm at 53fb8000 {
+				#pwm-cells = <3>;
+				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+				reg = <0x53fb8000 0x4000>;
+				interrupts = <94>;
+			};
+
 			uart1: serial at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..b522411 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -455,6 +455,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+	clk_register_clkdev(clk[pwm1_ipg_gate], "ipg", "53fb4000.pwm");
+	clk_register_clkdev(clk[pwm1_hf_gate], "per", "53fb4000.pwm");
+	clk_register_clkdev(clk[pwm2_ipg_gate], "ipg", "53fb8000.pwm");
+	clk_register_clkdev(clk[pwm2_hf_gate], "per", "53fb8000.pwm");
 
 	/* set SDHC root clock to 200MHZ*/
 	clk_set_rate(clk[esdhc_a_podf], 200000000);
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:22 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:22 +0200
Subject: [PATCH 7/9] pwm i.MX: fix clock lookup
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-8-git-send-email-s.hauer@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

The i.MX pwm core has two clocks: The ipg clock and the ipg highfreq
(peripheral) clock. The ipg clock has to be enabled for this hardware
to work. The actual pwm output can either be driven by the ipg clock
or the ipg highfreq. The ipg highfreq has the advantage that it runs
even when the SoC is in low power modes.
This patch requests both clocks and enables the ipg clock for accessing
registers and the peripheral clock to actually turn on the pwm.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   33 +++++++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 3834f475..308ab51 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -41,7 +41,8 @@
 #define MX3_PWMCR_EN              (1 << 0)
 
 struct imx_chip {
-	struct clk	*clk;
+	struct clk	*clk_per;
+	struct clk	*clk_ipg;
 
 	int		enabled;
 	void __iomem	*mmio_base;
@@ -106,7 +107,7 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
 	unsigned long period_cycles, duty_cycles, prescale;
 	u32 cr;
 
-	c = clk_get_rate(imx->clk);
+	c = clk_get_rate(imx->clk_per);
 	c = c * period_ns;
 	do_div(c, 1000000000);
 	period_cycles = c;
@@ -161,8 +162,15 @@ static int imx_pwm_config(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
+	int ret;
 
-	return imx->config(chip, pwm, duty_ns, period_ns);
+	clk_prepare_enable(imx->clk_ipg);
+
+	ret = imx->config(chip, pwm, duty_ns, period_ns);
+
+	clk_disable_unprepare(imx->clk_ipg);
+
+	return ret;
 }
 
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
@@ -170,7 +178,7 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	struct imx_chip *imx = to_imx_chip(chip);
 	int rc;
 
-	rc = clk_prepare_enable(imx->clk);
+	rc = clk_prepare_enable(imx->clk_per);
 	if (rc)
 		return rc;
 
@@ -187,7 +195,7 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 
 	imx->set_enable(chip, false);
 
-	clk_disable_unprepare(imx->clk);
+	clk_disable_unprepare(imx->clk_per);
 	imx->enabled = 0;
 }
 
@@ -219,10 +227,19 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	imx->clk = devm_clk_get(&pdev->dev, "pwm");
+	imx->clk_per = devm_clk_get(&pdev->dev, "per");
+	if (IS_ERR(imx->clk_per)) {
+		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
+				PTR_ERR(imx->clk_per));
+		return PTR_ERR(imx->clk_per);
+	}
 
-	if (IS_ERR(imx->clk))
-		return PTR_ERR(imx->clk);
+	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+	if (IS_ERR(imx->clk_ipg)) {
+		dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
+				PTR_ERR(imx->clk_ipg));
+		return PTR_ERR(imx->clk_ipg);
+	}
 
 	imx->chip.ops = &imx_pwm_ops;
 	imx->chip.dev = &pdev->dev;
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:18 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:18 +0200
Subject: [PATCH 3/9] pwm i.MX: add functions to enable/disable pwm.
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-4-git-send-email-s.hauer@pengutronix.de>

We used to enable/disable the pwm only by switching the
clock on or off. Instead, use the dedicated register bits.
These differ on different SoCs, so introduce a SoC specific
function for this.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   48 ++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 44 insertions(+), 4 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 0f244e6..3fc4ae8 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -25,6 +25,7 @@
 #define MX1_PWMS    0x04   /* PWM Sample Register */
 #define MX1_PWMP    0x08   /* PWM Period Register */
 
+#define MX1_PWMC_EN		(1 << 4)
 
 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
 
@@ -49,6 +50,7 @@ struct imx_chip {
 
 	int (*config)(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns);
+	void (*set_enable)(struct pwm_chip *chip, bool enable);
 };
 
 #define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
@@ -81,6 +83,21 @@ static int imx_pwm_config_v1(struct pwm_chip *chip,
 	return 0;
 }
 
+static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+	u32 val;
+
+	val = readl(imx->mmio_base + MX1_PWMC);
+
+	if (enable)
+		val |= MX1_PWMC_EN;
+	else
+		val &= ~MX1_PWMC_EN;
+
+	writel(val, imx->mmio_base + MX1_PWMC);
+}
+
 static int imx_pwm_config_v2(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
@@ -115,7 +132,10 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
 
 	cr = MX3_PWMCR_PRESCALER(prescale) |
 		MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-		MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
+		MX3_PWMCR_DBGEN;
+
+	if (imx->enabled)
+		cr |= MX3_PWMCR_EN;
 
 	if (cpu_is_mx25())
 		cr |= MX3_PWMCR_CLKSRC_IPG;
@@ -127,6 +147,21 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
 	return 0;
 }
 
+static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+	u32 val;
+
+	val = readl(imx->mmio_base + MX3_PWMCR);
+
+	if (enable)
+		val |= MX3_PWMCR_EN;
+	else
+		val &= ~MX3_PWMCR_EN;
+
+	writel(val, imx->mmio_base + MX3_PWMCR);
+}
+
 static int imx_pwm_config(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
@@ -144,6 +179,8 @@ static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	if (rc)
 		return rc;
 
+	imx->set_enable(chip, true);
+
 	imx->enabled = 1;
 
 	return 0;
@@ -153,7 +190,7 @@ static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
 
-	writel(0, imx->mmio_base + MX3_PWMCR);
+	imx->set_enable(chip, false);
 
 	clk_disable_unprepare(imx->clk);
 	imx->enabled = 0;
@@ -198,10 +235,13 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	if (imx->mmio_base == NULL)
 		return -EADDRNOTAVAIL;
 
-	if (cpu_is_mx1() || cpu_is_mx21())
+	if (cpu_is_mx1() || cpu_is_mx21()) {
 		imx->config = imx_pwm_config_v1;
-	else
+		imx->set_enable = imx_pwm_set_enable_v1;
+	} else {
 		imx->config = imx_pwm_config_v2;
+		imx->set_enable = imx_pwm_set_enable_v2;
+	}
 
 	ret = pwmchip_add(&imx->chip);
 	if (ret < 0)
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:19 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:19 +0200
Subject: [PATCH 4/9] pwm i.MX: Use module_platform_driver
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-5-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 3fc4ae8..a689144 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -270,17 +270,7 @@ static struct platform_driver imx_pwm_driver = {
 	.remove		= __devexit_p(imx_pwm_remove),
 };
 
-static int __init imx_pwm_init(void)
-{
-	return platform_driver_register(&imx_pwm_driver);
-}
-arch_initcall(imx_pwm_init);
-
-static void __exit imx_pwm_exit(void)
-{
-	platform_driver_unregister(&imx_pwm_driver);
-}
-module_exit(imx_pwm_exit);
+module_platform_driver(imx_pwm_driver);
 
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:21 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:21 +0200
Subject: [PATCH 6/9] pwm i.MX: use per clock unconditionally
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-7-git-send-email-s.hauer@pengutronix.de>

The i.MX pwm core has two clocks: The ipg clock and the ipg highfreq
(peripheral) clock. The ipg clock has to be enabled for this hardware
to work. The actual pwm output can either be driven by the ipg clock
or the ipg highfreq. The ipg highfreq has the advantage that it runs
even when the SoC is in low power modes.
Use the always running clock also on i.MX25.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index dfc1bae..3834f475 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -132,16 +132,11 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
 
 	cr = MX3_PWMCR_PRESCALER(prescale) |
 		MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-		MX3_PWMCR_DBGEN;
+		MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
 
 	if (imx->enabled)
 		cr |= MX3_PWMCR_EN;
 
-	if (cpu_is_mx25())
-		cr |= MX3_PWMCR_CLKSRC_IPG;
-	else
-		cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
-
 	writel(cr, imx->mmio_base + MX3_PWMCR);
 
 	return 0;
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:20 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:20 +0200
Subject: [PATCH 5/9] pwm i.MX: add devicetree support
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-6-git-send-email-s.hauer@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |   25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index a689144..dfc1bae 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -16,9 +16,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pwm.h>
+#include <linux/of_device.h>
 #include <mach/hardware.h>
 
-
 /* i.MX1 and i.MX21 share the same PWM function block: */
 
 #define MX1_PWMC    0x00   /* PWM Control Register */
@@ -203,8 +203,17 @@ static struct pwm_ops imx_pwm_ops = {
 	.owner = THIS_MODULE,
 };
 
+static const struct of_device_id imx_pwm_dt_ids[] = {
+	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_config_v1, },
+	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_config_v2, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_pwm_of_match);
+
 static int __devinit imx_pwm_probe(struct platform_device *pdev)
 {
+	const struct of_device_id *of_id =
+			of_match_device(imx_pwm_dt_ids, &pdev->dev);
 	struct imx_chip *imx;
 	struct resource *r;
 	int ret = 0;
@@ -235,12 +244,16 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	if (imx->mmio_base == NULL)
 		return -EADDRNOTAVAIL;
 
-	if (cpu_is_mx1() || cpu_is_mx21()) {
-		imx->config = imx_pwm_config_v1;
-		imx->set_enable = imx_pwm_set_enable_v1;
+	if (of_id) {
+		imx->config = of_id->data;
 	} else {
-		imx->config = imx_pwm_config_v2;
-		imx->set_enable = imx_pwm_set_enable_v2;
+		if (cpu_is_mx1() || cpu_is_mx21()) {
+			imx->config = imx_pwm_config_v1;
+			imx->set_enable = imx_pwm_set_enable_v1;
+		} else {
+			imx->config = imx_pwm_config_v2;
+			imx->set_enable = imx_pwm_set_enable_v2;
+		}
 	}
 
 	ret = pwmchip_add(&imx->chip);
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:48:16 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:48:16 +0200
Subject: [PATCH 1/9] pwm i.MX: factor out SoC specific functions
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346154504-5623-2-git-send-email-s.hauer@pengutronix.de>

To make the code more flexible.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/pwm/pwm-imx.c |  145 ++++++++++++++++++++++++++++---------------------
 1 file changed, 82 insertions(+), 63 deletions(-)

diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..38270f4 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -46,81 +46,95 @@ struct imx_chip {
 	void __iomem	*mmio_base;
 
 	struct pwm_chip	chip;
+
+	int (*config)(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns);
 };
 
 #define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
 
-static int imx_pwm_config(struct pwm_chip *chip,
+static int imx_pwm_config_v1(struct pwm_chip *chip,
 		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
 
-	if (!(cpu_is_mx1() || cpu_is_mx21())) {
-		unsigned long long c;
-		unsigned long period_cycles, duty_cycles, prescale;
-		u32 cr;
-
-		c = clk_get_rate(imx->clk);
-		c = c * period_ns;
-		do_div(c, 1000000000);
-		period_cycles = c;
-
-		prescale = period_cycles / 0x10000 + 1;
-
-		period_cycles /= prescale;
-		c = (unsigned long long)period_cycles * duty_ns;
-		do_div(c, period_ns);
-		duty_cycles = c;
-
-		/*
-		 * according to imx pwm RM, the real period value should be
-		 * PERIOD value in PWMPR plus 2.
-		 */
-		if (period_cycles > 2)
-			period_cycles -= 2;
-		else
-			period_cycles = 0;
-
-		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
-		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
-
-		cr = MX3_PWMCR_PRESCALER(prescale) |
-			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-			MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
-
-		if (cpu_is_mx25())
-			cr |= MX3_PWMCR_CLKSRC_IPG;
-		else
-			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
-
-		writel(cr, imx->mmio_base + MX3_PWMCR);
-	} else if (cpu_is_mx1() || cpu_is_mx21()) {
-		/* The PWM subsystem allows for exact frequencies. However,
-		 * I cannot connect a scope on my device to the PWM line and
-		 * thus cannot provide the program the PWM controller
-		 * exactly. Instead, I'm relying on the fact that the
-		 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
-		 * function group already. So I'll just modify the PWM sample
-		 * register to follow the ratio of duty_ns vs. period_ns
-		 * accordingly.
-		 *
-		 * This is good enough for programming the brightness of
-		 * the LCD backlight.
-		 *
-		 * The real implementation would divide PERCLK[0] first by
-		 * both the prescaler (/1 .. /128) and then by CLKSEL
-		 * (/2 .. /16).
-		 */
-		u32 max = readl(imx->mmio_base + MX1_PWMP);
-		u32 p = max * duty_ns / period_ns;
-		writel(max - p, imx->mmio_base + MX1_PWMS);
-	} else {
-		BUG();
-	}
+	/* The PWM subsystem allows for exact frequencies. However,
+	 * I cannot connect a scope on my device to the PWM line and
+	 * thus cannot provide the program the PWM controller
+	 * exactly. Instead, I'm relying on the fact that the
+	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
+	 * function group already. So I'll just modify the PWM sample
+	 * register to follow the ratio of duty_ns vs. period_ns
+	 * accordingly.
+	 *
+	 * This is good enough for programming the brightness of
+	 * the LCD backlight.
+	 *
+	 * The real implementation would divide PERCLK[0] first by
+	 * both the prescaler (/1 .. /128) and then by CLKSEL
+	 * (/2 .. /16).
+	 */
+	u32 max = readl(imx->mmio_base + MX1_PWMP);
+	u32 p = max * duty_ns / period_ns;
+	writel(max - p, imx->mmio_base + MX1_PWMS);
+
+	return 0;
+}
+
+static int imx_pwm_config_v2(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+	unsigned long long c;
+	unsigned long period_cycles, duty_cycles, prescale;
+	u32 cr;
+
+	c = clk_get_rate(imx->clk);
+	c = c * period_ns;
+	do_div(c, 1000000000);
+	period_cycles = c;
+
+	prescale = period_cycles / 0x10000 + 1;
+
+	period_cycles /= prescale;
+	c = (unsigned long long)period_cycles * duty_ns;
+	do_div(c, period_ns);
+	duty_cycles = c;
+
+	/*
+	 * according to imx pwm RM, the real period value should be
+	 * PERIOD value in PWMPR plus 2.
+	 */
+	if (period_cycles > 2)
+		period_cycles -= 2;
+	else
+		period_cycles = 0;
+
+	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
+	writel(period_cycles, imx->mmio_base + MX3_PWMPR);
+
+	cr = MX3_PWMCR_PRESCALER(prescale) |
+		MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+		MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
+
+	if (cpu_is_mx25())
+		cr |= MX3_PWMCR_CLKSRC_IPG;
+	else
+		cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
+
+	writel(cr, imx->mmio_base + MX3_PWMCR);
 
 	return 0;
 }
 
+static int imx_pwm_config(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	struct imx_chip *imx = to_imx_chip(chip);
+
+	return imx->config(chip, pwm, duty_ns, period_ns);
+}
+
 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
 	struct imx_chip *imx = to_imx_chip(chip);
@@ -187,6 +201,11 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
 	if (imx->mmio_base == NULL)
 		return -EADDRNOTAVAIL;
 
+	if (cpu_is_mx1() || cpu_is_mx21())
+		imx->config = imx_pwm_config_v1;
+	else
+		imx->config = imx_pwm_config_v2;
+
 	ret = pwmchip_add(&imx->chip);
 	if (ret < 0)
 		return ret;
-- 
1.7.10.4



From s.hauer at pengutronix.de  Tue Aug 28 07:49:32 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 28 Aug 2012 13:49:32 +0200
Subject: [PATCH 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <CAOMZO5AGCf_9Hzj=6F_u9oK7RAR_ppdm0QhYxht5PPHZ7_-GfQ@mail.gmail.com>
References: <1345385346-25412-1-git-send-email-festevam@gmail.com>
 <20120828074533.GV26594@pengutronix.de>
 <CAOMZO5AGCf_9Hzj=6F_u9oK7RAR_ppdm0QhYxht5PPHZ7_-GfQ@mail.gmail.com>
Message-ID: <20120828114932.GI26594@pengutronix.de>

On Tue, Aug 28, 2012 at 08:47:10AM -0300, Fabio Estevam wrote:
> On 8/28/12, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> 
> > Applied and added stable tag (I assume this should go to stable, right?)
> 
> Yes, please apply v2 version and you can add the stable tag (only
> applies to 3.5 stable branch though).

Yes I applied v2 (found it a bit later after writing the email)

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From valentin.longchamp at keymile.com  Tue Aug 28 07:56:16 2012
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Tue, 28 Aug 2012 13:56:16 +0200
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
Message-ID: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>

This is a first attempt to support the km_kirkwood reference design with
a device tree. This km_kirkwood design is present in many Keymile
products. It is based on the Marvell Bobcat SOC which integrates a
Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
is very similar to the "normal" one, but there are a few differences.

This initial support is minimal: the kernel can boot with network
(ge0), serial port and NAND functional.

Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
Cc: Holger Brunck <holger.brunck at keymile.com>
---
 arch/arm/boot/dts/kirkwood-km_kirkwood.dts |   29 +++++++++++
 arch/arm/mach-kirkwood/Kconfig             |    7 +++
 arch/arm/mach-kirkwood/Makefile            |    1 +
 arch/arm/mach-kirkwood/Makefile.boot       |    1 +
 arch/arm/mach-kirkwood/board-dt.c          |    4 ++
 arch/arm/mach-kirkwood/board-km_kirkwood.c |   75 ++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.h            |    6 ++
 7 files changed, 123 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-km_kirkwood.dts
 create mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c

diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 0000000..60118d5
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Keymile Kirkwood Reference Design";
+	compatible = "keymile,km_kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x08000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+
+		nand at 3000000 {
+			status = "ok";
+			chip-delay = <25>;
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..a2a99a1 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -109,6 +109,13 @@ config MACH_LSXL_DT
 	  Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
 	  Flattened Device Tree.
 
+config MACH_KM_KIRKWOOD_DT
+	bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a..f23ed81 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_MACH_IB62X0_DT)		+= board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)		+= board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)		+= board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)		+= board-lsxl.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)	+= board-km_kirkwood.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a571755..4f1dc3c 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -11,3 +11,4 @@ dtb-$(CONFIG_MACH_TS219_DT)	+= kirkwood-qnap-ts219.dtb
 dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
 dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+dtb-$(CONFIG_MACH_KM_KIRKWOOD_DT) += kirkwood-km_kirkwood.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450..9decc97 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,9 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("buffalo,lsxl"))
 		lsxl_init();
 
+	if (of_machine_is_compatible("keymile,km_kirkwood"))
+		km_kirkwood_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table,
 			     kirkwood_auxdata_lookup, NULL);
 }
@@ -100,6 +103,7 @@ static const char *kirkwood_dt_board_compat[] = {
 	"qnap,ts219",
 	"seagate,goflexnet",
 	"buffalo,lsxl",
+	"keymile,km_kirkwood",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
new file mode 100644
index 0000000..7a103db
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp at keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+	MPP8_GPIO,	/* I2C SDA */
+	MPP9_GPIO,	/* I2C SCL */
+	0
+};
+
+void __init km_kirkwood_init(void)
+{
+	struct clk *sata_clk;
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+
+	kirkwood_mpp_conf(km_kirkwood_mpp_config);
+
+	/*
+	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
+	 * devices are also not present in this variant, their clocks get
+	 * disabled because unused when clk_disable_unused() gets called.
+	 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+	 */
+	sata_clk = clk_get_sys("sata_mv.0", "0");
+	if (!IS_ERR(sata_clk))
+		sata_clk->flags |= CLK_IGNORE_UNUSED;
+	sata_clk = clk_get_sys("sata_mv.0", "1");
+	if (!IS_ERR(sata_clk))
+		sata_clk->flags |= CLK_IGNORE_UNUSED;
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1a..219eecc 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -94,6 +94,12 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.1



From andrew at lunn.ch  Tue Aug 28 08:20:54 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 28 Aug 2012 14:20:54 +0200
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
In-Reply-To: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
References: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20120828122054.GG31704@lunn.ch>

Hi Valentin

> This is a first attempt to support the km_kirkwood reference design with
> a device tree. This km_kirkwood design is present in many Keymile
> products. It is based on the Marvell Bobcat SOC which integrates a
> Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
> is very similar to the "normal" one, but there are a few differences.

Is there a public datasheet for this device?

> diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
> new file mode 100644
> index 0000000..7a103db
> --- /dev/null
> +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
> + * Valentin Longchamp <valentin.longchamp at keymile.com>
> + *
> + * arch/arm/mach-kirkwood/board-km_kirkwood.c
> + *
> + * Keymile km_kirkwood Reference Desing Init for drivers not converted to
> + * flattened device tree yet.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/ata_platform.h>
> +#include <linux/mv643xx_eth.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_fdt.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/gpio.h>
> +#include <linux/mtd/physmap.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/spi.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <mach/kirkwood.h>
> +#include <mach/bridge-regs.h>
> +#include <plat/mvsdio.h>
> +#include "common.h"
> +#include "mpp.h"

Please remove all the header files you don't need.

> +
> +static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
> +};
> +
> +static unsigned int km_kirkwood_mpp_config[] __initdata = {
> +	MPP8_GPIO,	/* I2C SDA */
> +	MPP9_GPIO,	/* I2C SCL */
> +	0
> +};
> +
> +void __init km_kirkwood_init(void)
> +{
> +	struct clk *sata_clk;
> +	/*
> +	 * Basic setup. Needs to be called early.
> +	 */
> +
> +	kirkwood_mpp_conf(km_kirkwood_mpp_config);
> +
> +	/*
> +	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
> +	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
> +	 * devices are also not present in this variant, their clocks get
> +	 * disabled because unused when clk_disable_unused() gets called.

So there is no SATA at all on this SoC? Anything else missing which a
'normal' kirkwood has?

If there a way to identify the chipset? e.g. what does 

kirkwood_pcie_id(&dev, &rev);

give? It would be better to not create the clocks at all, if we could
determine at runtime the hardware was not there.

Apart from these comments, the patch looks good.

      Andrew


From afzal at ti.com  Tue Aug 28 08:21:01 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 28 Aug 2012 12:21:01 +0000
Subject: [PATCH v6 07/10] ARM: OMAP2+: gpmc: generic timing calculation
In-Reply-To: <503BD8D5.5060400@ti.com>
References: <cover.1345524670.git.afzal@ti.com>
 <83b963e4ebcc1009a26a8c6419c785ac6d742c0b.1345524670.git.afzal@ti.com>
 <50359C64.40603@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9BA63D@DBDE01.ent.ti.com>
 <503BD8D5.5060400@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9DA81D@DBDE01.ent.ti.com>

Hi Jon,

On Tue, Aug 28, 2012 at 02:00:13, Hunter, Jon wrote:
> On 08/27/2012 05:37 AM, Mohammed, Afzal wrote:

> > And at least for initial users, they are expected to have
> > some grasp on how to calculate timings, such a user will
> > not be much worried about your 3 concerns above, anyway as
> > of now they need to have a good grasp on it.
> 
> I would consider myself to be an initial user and I am concerned,
> doesn't that count?

Yes sir, what I meant was new users who want to have runtime
calculation using the generic timing routine. For the
peripherals already making use of custom timing routine,
I am into that role too, hence the patches 8-10.

And if you have any board that makes use of existing custom
timing calculation routines (OneNAND, tusb6010 or smc91x),
can you please give this series a try.

Regards
Afzal


From aaro.koskinen at iki.fi  Tue Aug 28 08:20:49 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Tue, 28 Aug 2012 15:20:49 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
Message-ID: <20120828122042.GC783@harshnoise.musicnaut.iki.fi>

Hi,

On Mon, Aug 27, 2012 at 05:17:30PM -0700, Shilimkar, Santosh wrote:
> On Mon, Aug 27, 2012 at 4:26 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> > I tried bypassing the whole SRAM init, but the device does not seem to
> > boot up at all.
> >
> > If I comment out the memset alone, then it boots and the issue is gone:
> >
> > +#if 0
> >         memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
> >                   omap_sram_size - SRAM_BOOTLOADER_SZ);
> > +#endif
> >
> Good. So the issue is indeed direct or indirect access to the secure SRAM.
> As security can dynamically resize the secure RAM size it is even harder
> to fix this issue properly. One easier way to deal with the issue is map only
> needed SRAM and leave rest for security.
> 
> For now, Can you check if reducing the size of the SRAM in init is helping you
> to get way with the issue. Sorry it might need few iterations for you to get
> a working SRAM size.

The problem is triggered by writing to the beginning of the SRAM area,
not to the end. I need to skip the first 16k (0x4000) to get rid of
the errors. Maybe the base address calculation is wrong? This could
also explain why it's still possible to use the device - it seems the
allocator starts from the end, and moves towards the base...

A.


From thomas.petazzoni at free-electrons.com  Tue Aug 28 08:22:36 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 14:22:36 +0200
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <20120828091139.GC31704@lunn.ch>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120828091139.GC31704@lunn.ch>
Message-ID: <20120828142236.2c7e9bd3@skate>

Le Tue, 28 Aug 2012 11:11:39 +0200,
Andrew Lunn <andrew at lunn.ch> a ?crit :

> I compiled tested on Dove, Kirkwood, Orion5x and mv78xx0.
> 
> Tested-by: Andrew Lunn <andrew at lunn.ch>

Thanks! Will Jason take care of merging this on top of the previous
address decoding patches? Note that if you want to keep build
bisectability, it should be merged before my "arm: plat-orion: introduce
PLAT_ORION_LEGACY hidden config option" patch.

> One other driver you might want to look at is:
> 
> drivers/watchdog/orion_wdt.c
> 
> It uses <mach/bridge-regs.h>

This driver is:

config ORION_WATCHDOG
        tristate "Orion watchdog"
        depends on ARCH_ORION5X || ARCH_KIRKWOOD

so it isn't selectable with ARCH_MVEBU, so it will not cause problems
for now. Of course, at some point, we'll have a look at the watchdog
driver but for now, it's fine.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From vbyravarasu at nvidia.com  Tue Aug 28 08:36:14 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Tue, 28 Aug 2012 18:06:14 +0530
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <20120828094924.GT27166@arwen.pp.htv.fi>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
 <20120828094924.GT27166@arwen.pp.htv.fi>
Message-ID: <D958900912E20642BCBC71664EFECE3E6DDE14DCF5@BGMAIL02.nvidia.com>


> -----Original Message-----
> From: Felipe Balbi [mailto:balbi at ti.com]
> Sent: Tuesday, August 28, 2012 3:19 PM
> To: Venu Byravarasu
> Cc: ccross at android.com; olof at lixom.net; swarren at wwwdotorg.org;
> linux at arm.linux.org.uk; stern at rowland.harvard.edu;
> gregkh at linuxfoundation.org; balbi at ti.com; linux-kernel at vger.kernel.org;
> linux-tegra at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> usb at vger.kernel.org
> Subject: Re: [PATCH] usb: tegra: moving phy driver into drivers directory
> 
> * PGP Signed by an unknown key
> 
> Hi,
> 
> On Tue, Aug 28, 2012 at 03:02:18PM +0530, Venu Byravarasu wrote:
> > In order to keep up with the USB driver files organization,
> > moving USB phy driver from mach-tegra to drivers/USB directory.
> >
> > Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
> > ---
> >  arch/arm/mach-tegra/Makefile                       |    1 -
> >  arch/arm/mach-tegra/devices.c                      |    8 +-------
> >  arch/arm/mach-tegra/devices.h                      |    2 --
> >  drivers/usb/host/ehci-tegra.c                      |    2 +-
> >  drivers/usb/phy/Makefile                           |    1 +
> >  .../usb_phy.c => drivers/usb/phy/tegra_usb_phy.c   |    4 +---
> >  .../usb_phy.h => drivers/usb/phy/tegra_usb_phy.h   |    2 --
> >  7 files changed, 4 insertions(+), 16 deletions(-)
> >  rename arch/arm/mach-tegra/usb_phy.c =>
> drivers/usb/phy/tegra_usb_phy.c (99%)
> >  rename arch/arm/mach-tegra/include/mach/usb_phy.h =>
> drivers/usb/phy/tegra_usb_phy.h (97%)
> >
> > diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-
> tegra/Makefile
> > index b94858f..b542dac 100644
> > --- a/arch/arm/mach-tegra/Makefile
> > +++ b/arch/arm/mach-tegra/Makefile
> > @@ -25,7 +25,6 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
> >  obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
> >  obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
> >  obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
> > -obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
> >
> >  obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-
> tegra20.o
> >  obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-
> tegra30.o
> > diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-
> tegra/devices.c
> > index 61e9603..232d7e1 100644
> > --- a/arch/arm/mach-tegra/devices.c
> > +++ b/arch/arm/mach-tegra/devices.c
> > @@ -26,7 +26,6 @@
> >  #include <mach/irqs.h>
> >  #include <mach/iomap.h>
> >  #include <mach/dma.h>
> > -#include <mach/usb_phy.h>
> >
> >  #include "gpio-names.h"
> >  #include "devices.h"
> > @@ -438,11 +437,6 @@ static struct resource tegra_usb3_resources[] = {
> >  	},
> >  };
> >
> > -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
> > -	.reset_gpio = -1,
> > -	.clk = "cdev2",
> > -};
> > -
> >  struct tegra_ehci_platform_data tegra_ehci1_pdata = {
> >  	.operating_mode = TEGRA_USB_OTG,
> >  	.power_down_on_bus_suspend = 1,
> > @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata
> = {
> >  };
> >
> >  struct tegra_ehci_platform_data tegra_ehci2_pdata = {
> > -	.phy_config = &tegra_ehci2_ulpi_phy_config,
> > +	.phy_config = NULL,
> >  	.operating_mode = TEGRA_USB_HOST,
> >  	.power_down_on_bus_suspend = 1,
> >  	.vbus_gpio = -1,
> > diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-
> tegra/devices.h
> > index 4f50527..6bac5e6 100644
> > --- a/arch/arm/mach-tegra/devices.h
> > +++ b/arch/arm/mach-tegra/devices.h
> > @@ -22,8 +22,6 @@
> >  #include <linux/platform_device.h>
> >  #include <linux/platform_data/tegra_usb.h>
> >
> > -#include <mach/usb_phy.h>
> > -
> >  extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
> >
> >  extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
> > diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> > index 75eca42..a03e279 100644
> > --- a/drivers/usb/host/ehci-tegra.c
> > +++ b/drivers/usb/host/ehci-tegra.c
> > @@ -27,7 +27,7 @@
> >  #include <linux/of_gpio.h>
> >  #include <linux/pm_runtime.h>
> >
> > -#include <mach/usb_phy.h>
> > +#include "../phy/tegra_usb_phy.h"
> >  #include <mach/iomap.h>
> >
> >  #define TEGRA_USB_DMA_ALIGN 32
> > diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> > index eca095b..663164f 100644
> > --- a/drivers/usb/phy/Makefile
> > +++ b/drivers/usb/phy/Makefile
> > @@ -5,3 +5,4 @@
> >  ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
> >
> >  obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
> > +obj-$(CONFIG_USB_EHCI_TEGRA)		+= tegra_usb_phy.o
> > diff --git a/arch/arm/mach-tegra/usb_phy.c
> b/drivers/usb/phy/tegra_usb_phy.c
> > similarity index 99%
> > rename from arch/arm/mach-tegra/usb_phy.c
> > rename to drivers/usb/phy/tegra_usb_phy.c
> > index 022b33a..c856716 100644
> > --- a/arch/arm/mach-tegra/usb_phy.c
> > +++ b/drivers/usb/phy/tegra_usb_phy.c
> > @@ -1,6 +1,4 @@
> >  /*
> > - * arch/arm/mach-tegra/usb_phy.c
> > - *
> >   * Copyright (C) 2010 Google, Inc.
> >   *
> >   * Author:
> > @@ -31,7 +29,7 @@
> >  #include <linux/usb/ulpi.h>
> >  #include <asm/mach-types.h>
> >  #include <mach/gpio-tegra.h>
> > -#include <mach/usb_phy.h>
> > +#include "tegra_usb_phy.h"
> >  #include <mach/iomap.h>
> >
> >  #define ULPI_VIEWPORT		0x170
> 
> NAK, needs to be converted to proper PHY driver (misnamed as
> include/linux/usb/otg.h). You will need proper phy->init, phy->suspend,
> phy->resume, etc callbacks.
> 

Thanks Felipe for your comments.
Created a patch to separate out phy related stuff to phy.h with you as a reviewer.
Plz let me know your comments. 

Thanks,
Venu

> --
> balbi
> 
> * Unknown Key
> * 0x35CAA444


From ludovic.desroches at atmel.com  Tue Aug 28 09:14:58 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Tue, 28 Aug 2012 15:14:58 +0200
Subject: [PATCH 2/2] mmc: atmel-mci: AP700x PDC is not connected to MCI
In-Reply-To: <503A856A.9020303@yahoo.es>
References: <503A856A.9020303@yahoo.es>
Message-ID: <503CC452.7090607@atmel.com>

Hi Hein,

Le 08/26/2012 10:22 PM, Hein Tibosch a ?crit :
> Earlier, atmel-mci was adapter to make use of the peripheral DMA
> controller (PDC), in case normal DMA wouldn't work.
> ( http://comments.gmane.org/gmane.linux.kernel.mmc/9403 )
> This works OK on ARM platforms (AT91), but it broke the driver
> for AVR32, the AP700x.
> This patch makes the use of PDC depend on CONFIG_AVR32

I think you should explain explicitly that even if the MCI has PDC 
support, the connection is not done for AVR chips.

Otherwise you can add

Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Thanks for the patch.

Regards

Ludovic

>
> Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>
>
> ---
>   drivers/mmc/host/atmel-mci-regs.h |    7 +++++++
>   drivers/mmc/host/atmel-mci.c      |    2 +-
>   2 files changed, 8 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index ab56f7d..c97001e 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -140,6 +140,13 @@
>   #define atmci_writel(port,reg,value)			\
>   	__raw_writel((value), (port)->regs + reg)
>
> +/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
> +#ifdef CONFIG_AVR32
> +#	define ATMCI_PDC_CONNECTED	0
> +#else
> +#	define ATMCI_PDC_CONNECTED	1
> +#endif
> +
>   /*
>    * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
>    * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index 66e9fdc..702ab5c 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -2205,7 +2205,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
>   			"version: 0x%x\n", version);
>
>   	host->caps.has_dma_conf_reg = 0;
> -	host->caps.has_pdc = 1;
> +	host->caps.has_pdc = ATMCI_PDC_CONNECTED;
>   	host->caps.has_cfg_reg = 0;
>   	host->caps.has_cstor_reg = 0;
>   	host->caps.has_highspeed = 0;
>



From ludovic.desroches at atmel.com  Tue Aug 28 09:25:58 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Tue, 28 Aug 2012 15:25:58 +0200
Subject: [PATCH 1/2] mmc: atmel-mci: DMA can be used with other controller
In-Reply-To: <503A852B.8010902@yahoo.es>
References: <503A852B.8010902@yahoo.es>
Message-ID: <503CC6E6.1020403@atmel.com>

Hi Hein,

Thanks for your investigation about the MCI issue with AVR chips.

Le 08/26/2012 10:20 PM, Hein Tibosch a ?crit :
> After the latest changes to atmel-mci, it could not be used with
> DMA on the AVR32 platform. This patch will allow to use DMA again
> and it will avoid access to MCI register ATMCI_DMA.
>

I think you should add more details about the issue:
Even if the IP version is lower than v3xx and doesn't have the DMA
configuration register, DMA transfers can be used with a different
controller than the Atmel AHB DMA one. For instance, some AVR chips use 
the Synopsys DesignWare AHB DMA controller.

> Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>
>

Some comments below...

> ---
>   drivers/mmc/host/atmel-mci.c |   21 +++++++++------------
>   1 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index f2c115e..66e9fdc 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -71,7 +71,7 @@ enum atmci_pdc_buf {
>   };
>
>   struct atmel_mci_caps {
> -	bool    has_dma;
> +	bool    has_dma_conf_reg;
>   	bool    has_pdc;
>   	bool    has_cfg_reg;
>   	bool    has_cstor_reg;
> @@ -411,7 +411,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
>   	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
>   	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
>
> -	if (host->caps.has_dma) {
> +	if (host->caps.has_dma_conf_reg) {
>   		u32 val;
>
>   		val = buf[ATMCI_DMA / 4];
> @@ -767,7 +767,7 @@ static void atmci_dma_complete(void *arg)
>
>   	dev_vdbg(&host->pdev->dev, "DMA complete\n");
>
> -	if (host->caps.has_dma)
> +	if (host->caps.has_dma_conf_reg)
>   		/* Disable DMA hardware handshaking on MCI */
>   		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
>
> @@ -954,7 +954,9 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
>   		maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
>   	}
>
> -	atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | ATMCI_DMAEN);
> +	if (host->caps.has_dma_conf_reg)
> +		atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
> +			ATMCI_DMAEN);
>
>   	sglen = dma_map_sg(chan->device->dev, data->sg,
>   			data->sg_len, direction);
> @@ -2202,7 +2204,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
>   	dev_info(&host->pdev->dev,
>   			"version: 0x%x\n", version);
>
> -	host->caps.has_dma = 0;
> +	host->caps.has_dma_conf_reg = 0;
>   	host->caps.has_pdc = 1;
>   	host->caps.has_cfg_reg = 0;
>   	host->caps.has_cstor_reg = 0;
> @@ -2219,12 +2221,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
>   		host->caps.has_odd_clk_div = 1;
>   	case 0x400:
>   	case 0x300:
> -#ifdef CONFIG_AT_HDMAC
> -		host->caps.has_dma = 1;
> -#else
> -		dev_info(&host->pdev->dev,
> -			"has dma capability but dma engine is not selected, then use pio\n");
> -#endif
> +		host->caps.has_dma_conf_reg = 1;
>   		host->caps.has_pdc = 0;
>   		host->caps.has_cfg_reg = 1;
>   		host->caps.has_cstor_reg = 1;
> @@ -2298,7 +2295,7 @@ static int __init atmci_probe(struct platform_device *pdev)
>
>   	/* Get MCI capabilities and set operations according to it */
>   	atmci_get_cap(host);
> -	if (host->caps.has_dma && atmci_configure_dma(host)) {
> +	if (atmci_configure_dma(host)) {
>   		host->prepare_data = &atmci_prepare_data_dma;
>   		host->submit_data = &atmci_submit_data_dma;
>   		host->stop_transfer = &atmci_stop_transfer_dma;
>

I have tested this patch on at91sam9m10g45, at91sam9g10 and at91sam9261. 
For chips without MCI support for Atmel AHB DMA, removing the 
host->caps.has_dma test involves to use pdata->dma_slave with more 
caution to avoid some NULL pointer dereferences

@@ -2168,16 +2168,21 @@ static bool atmci_configure_dma(struct atmel_mci 
*host)
                 return false;

         pdata = host->pdev->dev.platform_data;
+       if (!pdata)
+               return false;

-       if (pdata && find_slave_dev(pdata->dma_slave)) {
+       if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
                 dma_cap_mask_t mask;


Regards

Ludovic


From swarren at wwwdotorg.org  Tue Aug 28 10:07:28 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 07:07:28 -0700
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
Message-ID: <503CD0A0.7080300@wwwdotorg.org>

On 08/28/2012 02:32 AM, Venu Byravarasu wrote:
> In order to keep up with the USB driver files organization,
> moving USB phy driver from mach-tegra to drivers/USB directory.
> 
> Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>

> diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c

> -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
> -	.reset_gpio = -1,
> -	.clk = "cdev2",
> -};
> -
>  struct tegra_ehci_platform_data tegra_ehci1_pdata = {
>  	.operating_mode = TEGRA_USB_OTG,
>  	.power_down_on_bus_suspend = 1,
> @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata = {
>  };
>  
>  struct tegra_ehci_platform_data tegra_ehci2_pdata = {
> -	.phy_config = &tegra_ehci2_ulpi_phy_config,
> +	.phy_config = NULL,

The PHY driver checks that field isn't NULL, and fails if it is:

> struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
>         void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
> {
...
>         phy->config = config;
>         phy->mode = phy_mode;
> 
>         if (!phy->config) {
>                 if (phy_is_ulpi(phy)) {
>                         pr_err("%s: ulpi phy configuration missing", __func__);
>                         err = -EINVAL;
>                         goto err0;

So, this change will completely break ULPI support, which currently
works fine. So, NAK.

I also plan on deleting devices.[ch] in kernel 3.7, and moving the USB
platform data into board-dt-tegra20.c, since that's the only place it's
used right now. So, this patch would conflict with that rather badly. I
just posted the patches for that to the linux-tegra mailing list last
night. Do you have better proposals for that? Perhaps usb_phy.c should
set phy->config to &ulpi_default in a similar fashion to how it works
for UTMI; that would remove some of the coupling between the changes.

BTW, in your response to Felipe, you said...

> Thanks Felipe for your comments.
> Created a patch to separate out phy related stuff to phy.h with you as a reviewer.
> Plz let me know your comments. 

... where is that patch?


From robherring2 at gmail.com  Tue Aug 28 10:19:42 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 28 Aug 2012 09:19:42 -0500
Subject: [PATCH] ARM: highbank: add a defconfig
Message-ID: <1346163582-13627-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/configs/highbank_defconfig |   39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 arch/arm/configs/highbank_defconfig

diff --git a/arch/arm/configs/highbank_defconfig b/arch/arm/configs/highbank_defconfig
new file mode 100644
index 0000000..38154be
--- /dev/null
+++ b/arch/arm/configs/highbank_defconfig
@@ -0,0 +1,39 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_CMDLINE="console=ttyAMA0"
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_SI=y
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_PL061=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_HIGHBANK_MC=y
+CONFIG_EDAC_HIGHBANK_L2=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Tue Aug 28 10:19:38 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 28 Aug 2012 07:19:38 -0700
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <20120828122042.GC783@harshnoise.musicnaut.iki.fi>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
 <20120828122042.GC783@harshnoise.musicnaut.iki.fi>
Message-ID: <CAMQu2gwMk68_BNc4O0M52OACUVLLGzRCQe+5mGH_40DrwAQ4KA@mail.gmail.com>

On Tue, Aug 28, 2012 at 5:20 AM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> Hi,
>
> On Mon, Aug 27, 2012 at 05:17:30PM -0700, Shilimkar, Santosh wrote:
>> On Mon, Aug 27, 2012 at 4:26 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
>> > I tried bypassing the whole SRAM init, but the device does not seem to
>> > boot up at all.
>> >
>> > If I comment out the memset alone, then it boots and the issue is gone:
>> >
>> > +#if 0
>> >         memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
>> >                   omap_sram_size - SRAM_BOOTLOADER_SZ);
>> > +#endif
>> >
>> Good. So the issue is indeed direct or indirect access to the secure SRAM.
>> As security can dynamically resize the secure RAM size it is even harder
>> to fix this issue properly. One easier way to deal with the issue is map only
>> needed SRAM and leave rest for security.
>>
>> For now, Can you check if reducing the size of the SRAM in init is helping you
>> to get way with the issue. Sorry it might need few iterations for you to get
>> a working SRAM size.
>
> The problem is triggered by writing to the beginning of the SRAM area,
> not to the end. I need to skip the first 16k (0x4000) to get rid of
> the errors. Maybe the base address calculation is wrong? This could
> also explain why it's still possible to use the device - it seems the
> allocator starts from the end, and moves towards the base...
>
Or the PPA has resized the secure area of 16K. As you have seen the issue
on one OMAP3 device, it makes sense to takeout that 16K from the public
SRAM map.

Can you send the patch with fixed base address fir PUB SRAM ?

Regards
Santosh


From swarren at wwwdotorg.org  Tue Aug 28 10:28:28 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 07:28:28 -0700
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <CAGsJ_4y3Snvf-2DLSrpU5+zmytkARtNxJN_nPdiOngd+BK-aDA@mail.gmail.com>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210757.32852.arnd@arndb.de>
 <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
 <201208210920.52816.arnd@arndb.de>
 <CAGsJ_4x4DdHsNgh7ArkD1fCHT22rxRs18vcobHtpSXJ-cq3o4Q@mail.gmail.com>
 <CAGsJ_4y3Snvf-2DLSrpU5+zmytkARtNxJN_nPdiOngd+BK-aDA@mail.gmail.com>
Message-ID: <503CD58C.1010703@wwwdotorg.org>

On 08/28/2012 01:08 AM, Barry Song wrote:
> 2012/8/28 Barry Song <21cnbao at gmail.com>:
>> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
>>> On Tuesday 21 August 2012, Barry Song wrote:
>>>> then i add these to Kconfig.debug as it is a common way
>>>>
>>>>         config DEBUG_PRIMA2_UART1
>>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
>>>>                 depends on ARCH_PRIMA2
>>>>                 help
>>>>                   Say Y here if you want the debug print routines to direct
>>>>                   their output to UART1 serial port on SiRFprimaII devices.
>>>>
>>>>         config DEBUG_MARCO_UART1
>>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
>>>>                 depends on ARCH_MARCO
>>>>                 help
>>>>                   Say Y here if you want the debug print routines to direct
>>>>                   their output to UART1 serial port on SiRFmarco devices.
>>>>
>>>> and these in mach-prima2/include/mach/uart.h
>>>>
>>>>   #ifdef CONFIG_DEBUG_PRIMA2_UART1
>>>>   #define SIRFSOC_UART1_PA_BASE          0xb0060000
>>>>   #elif defined(CONFIG_DEBUG_MARCO_UART1)
>>>>   #define SIRFSOC_UART1_PA_BASE          0xcc060000
>>>>   #endif
>>>>
>>>> the above codes seem still ugly ?
>>>>
>>>
>>> No, that's fine, about as a good as it gets with today's kernel
>>> capabilities. Just fix the description to have the correct
>>> SoC name instead of "DaVinci DA8XX" ;-)
>>
>> except the DEBUG_LL uart base address, i missed the zreladdr-y. for
>> primaii, it is 0x00008000, for marco, it is 0x40008000 as marco's
>> memory space begins from 0x4000000.
>> i would to have AUTO_ZRELADDR for the whole SiRF series.
>> but for uImage load address difference in uImage header, which blocks
>> multiple SoCs from using same uImage, is "KERNEL_NOLOAD" uImage type
>> the current generic solution?
> 
> also add Stephen Warren.
> 
> i have two verified ways to resolve this problem:
> 
> 1. use "kernel noload", build uImage by:
> 
> make uImage UIMAGE_TYPE=kernel_noload
> and add the following patch in kernel:

Very recent U-Boot have a bootz command, which acts just like bootm, but
allows use of a raw zImage or the kernel, rather than a
uImage-wrapped-zImage. This was implemented by Marek Vasut.


From thomas.abraham at linaro.org  Tue Aug 28 10:48:50 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 20:18:50 +0530
Subject: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
In-Reply-To: <14029212.D3MKvQZpbq@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
	<14029212.D3MKvQZpbq@amdc1227>
Message-ID: <CAJuYYwQWzUaAhBqzf--kVN39GnhsYJMzH6ew6yDf-JCFaA--cQ@mail.gmail.com>

On 28 August 2012 15:36, Tomasz Figa <t.figa at samsung.com> wrote:
> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
> Redefine them to use the exact SoC name.
>
> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
> Joonyoung Shim, see:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/gpio.h   | 32 +++++++++++++++---------------
>  arch/arm/mach-exynos/mach-nuri.c           | 16 +++++++--------
>  arch/arm/mach-exynos/mach-origen.c         |  6 +++---
>  arch/arm/mach-exynos/mach-trats.c          |  4 ++--
>  arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
>  arch/arm/mach-exynos/setup-fimc.c          |  4 ++--
>  drivers/gpio/gpio-samsung.c                | 20 +++++++++----------
>  7 files changed, 57 insertions(+), 57 deletions(-)

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>

[...]


From mgr at pengutronix.de  Tue Aug 28 10:51:51 2012
From: mgr at pengutronix.de (Michael Grzeschik)
Date: Tue, 28 Aug 2012 16:51:51 +0200
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
Message-ID: <20120828145151.GJ10429@pengutronix.de>

Hi,

On Tue, Aug 28, 2012 at 02:58:27PM +0800, Richard Zhao wrote:
> i.MX usb controllers shares non-core registers, which may include
> SoC specific controls. We take it as a usbmisc device and usbmisc
> driver set operations needed by ci13xxx_imx driver.
> 
> For example, Sabrelite board has bad over-current design, we can
> usbmisc to disable over-current detect.
> 
> Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
>  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
>  drivers/usb/chipidea/Makefile                      |    2 +-
>  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
>  drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
>  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
>  6 files changed, 274 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
>  create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
>  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
> 
> diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> index 2c29041..5778b9c 100644
> --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> @@ -7,7 +7,10 @@ Required properties:
>  
>  Optional properties:
>  - fsl,usbphy: phandler of usb phy that connects to the only one port
> +- fsl,usbmisc: phandler of non-core register device, with one argument
> +  that indicate usb controller index
>  - vbus-supply: regulator for vbus
> +- disable-over-current: disable over current detect
>  
>  Examples:
>  usb at 02184000 { /* USB OTG */
> @@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
>  	reg = <0x02184000 0x200>;
>  	interrupts = <0 43 0x04>;
>  	fsl,usbphy = <&usbphy1>;
> +	fsl,usbmisc = <&usbmisc 0>;
> +	disable-over-current;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> new file mode 100644
> index 0000000..97ce94e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> @@ -0,0 +1,14 @@
> +* Freescale i.MX non-core registers
> +
> +Required properties:
> +- #index-cells: Cells used to descibe usb controller index. Should be <1>
> +- compatible: Should be one of below:
> +	"fsl,imx6q-usbmisc" for imx6q
> +- reg: Should contain registers location and length
> +
> +Examples:
> +usbmisc at 02184800 {
> +	#index-cells = <1>;
> +	compatible = "fsl,imx6q-usbmisc";
> +	reg = <0x02184800 0x200>;
> +};

i think we should have the devicetree-discuss Mailinglist in Cc: for
that.

Thanks,
Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.abraham at linaro.org  Tue Aug 28 10:55:34 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 20:25:34 +0530
Subject: [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
In-Reply-To: <2265472.2J2KAQrYg1@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
	<2265472.2J2KAQrYg1@amdc1227>
Message-ID: <CAJuYYwR3tPhk=DHJVgk1E_MqWrwT+7_YdJOSjrYX=pF7_RFjpw@mail.gmail.com>

On 28 August 2012 15:36, Tomasz Figa <t.figa at samsung.com> wrote:
> Based on patch "gpio/exynos: Add support for Exynos4x12 SoC" by Joonyoung Shim.
> See: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100737.html
>
> Exynos4x12 GPIO part1 and part2 have different layout than Exynos4210,
> so the initialization code has to be modified to support Exynos4x12 SoC.
> GPVx Exynos4x12 GPIO part4 is not supported yet.
>
> In the Exynos4x12 GPIO part1 and part2, the interval of base register
> offset is 0x20 but GPF0, GPJ0, GPK0 and GPM0 have different offsets. Same goes
> for the interrupt reg offset of GPF0 and GPK0. Refer to the layout below.
>
> - Exynos4x12 GPIO Part1
> GPIO    Base offset     Interrupt reg offset
> GPA0    0x000           0x00
> GPA1    0x020           0x04
> GPB     0x040           0x08
> GPC0    0x060           0x0C
> GPC1    0x080           0x10
> GPD0    0x0A0           0x14
> GPD1    0x0C0           0x18
>         ...
> GPF0    0x180           0x30
> GPF1    0x1A0           0x34
> GPF2    0x1C0           0x38
> GPF3    0x1E0           0x3C
>         ...
> GPJ0    0x240           0x40
> GPJ1    0x260           0x44
>
> - Exynos4x12 GPIO Part2
>         ...
> GPK0    0x040           0x08
> GPK1    0x060           0x0C
> GPK2    0x080           0x10
> GPK3    0x0A0           0x14
> GPL0    0x0C0           0x18
> GPL1    0x0E0           0x1C
> GPL2    0x100           0x20
> GPY0    0x120           x
> GPY1    0x140           x
> GPY2    0x160           x
> GPY3    0x180           x
> GPY4    0x1A0           x
> GPY5    0x1C0           x
> GPY6    0x1E0           x
>         ...
> GPM0    0x260           0x24
> GPM1    0x280           0x28
> GPM2    0x2A0           0x2C
> GPM3    0x2C0           0x30
> GPM4    0x2E0           0x34
> GPX0    0xC00           x
> GPX1    0xC20           x
> GPX2    0xC40           x
> GPX3    0xC60           x
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> ---
>  arch/arm/mach-exynos/include/mach/gpio.h |  28 ++-
>  arch/arm/mach-exynos/include/mach/irqs.h |   6 -
>  drivers/gpio/gpio-samsung.c              | 330 ++++++++++++++++++++++++++++---
>  3 files changed, 326 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index 21c9bf1..2103d14 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -26,11 +26,13 @@
>  #define EXYNOS4_GPIO_C1_NR     (5)
>  #define EXYNOS4_GPIO_D0_NR     (4)
>  #define EXYNOS4_GPIO_D1_NR     (4)
> +
>  #define EXYNOS4210_GPIO_E0_NR  (5)
>  #define EXYNOS4210_GPIO_E1_NR  (8)
>  #define EXYNOS4210_GPIO_E2_NR  (6)
>  #define EXYNOS4210_GPIO_E3_NR  (8)
>  #define EXYNOS4210_GPIO_E4_NR  (8)
> +
>  #define EXYNOS4_GPIO_F0_NR     (8)
>  #define EXYNOS4_GPIO_F1_NR     (8)
>  #define EXYNOS4_GPIO_F2_NR     (8)
> @@ -44,6 +46,13 @@
>  #define EXYNOS4_GPIO_L0_NR     (8)
>  #define EXYNOS4_GPIO_L1_NR     (3)
>  #define EXYNOS4_GPIO_L2_NR     (8)
> +
> +#define EXYNOS4X12_GPIO_M0_NR  (8)
> +#define EXYNOS4X12_GPIO_M1_NR  (7)
> +#define EXYNOS4X12_GPIO_M2_NR  (5)
> +#define EXYNOS4X12_GPIO_M3_NR  (8)
> +#define EXYNOS4X12_GPIO_M4_NR  (8)
> +
>  #define EXYNOS4_GPIO_X0_NR     (8)
>  #define EXYNOS4_GPIO_X1_NR     (8)
>  #define EXYNOS4_GPIO_X2_NR     (8)
> @@ -67,12 +76,20 @@ enum exynos4_gpio_number {
>         EXYNOS4_GPIO_C1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
>         EXYNOS4_GPIO_D0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
>         EXYNOS4_GPIO_D1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
> +
>         EXYNOS4210_GPIO_E0_START        = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
>         EXYNOS4210_GPIO_E1_START        = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E0),
>         EXYNOS4210_GPIO_E2_START        = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E1),
>         EXYNOS4210_GPIO_E3_START        = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E2),
>         EXYNOS4210_GPIO_E4_START        = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E3),
> -       EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4210_GPIO_E4),
> +
> +       EXYNOS4X12_GPIO_M0_START        = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
> +       EXYNOS4X12_GPIO_M1_START        = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M0),
> +       EXYNOS4X12_GPIO_M2_START        = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M1),
> +       EXYNOS4X12_GPIO_M3_START        = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M2),
> +       EXYNOS4X12_GPIO_M4_START        = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M3),
> +
> +       EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4X12_GPIO_M4),
>         EXYNOS4_GPIO_F1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
>         EXYNOS4_GPIO_F2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
>         EXYNOS4_GPIO_F3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
> @@ -108,11 +125,13 @@ enum exynos4_gpio_number {
>  #define EXYNOS4_GPC1(_nr)      (EXYNOS4_GPIO_C1_START + (_nr))
>  #define EXYNOS4_GPD0(_nr)      (EXYNOS4_GPIO_D0_START + (_nr))
>  #define EXYNOS4_GPD1(_nr)      (EXYNOS4_GPIO_D1_START + (_nr))
> +
>  #define EXYNOS4210_GPE0(_nr)   (EXYNOS4210_GPIO_E0_START + (_nr))
>  #define EXYNOS4210_GPE1(_nr)   (EXYNOS4210_GPIO_E1_START + (_nr))
>  #define EXYNOS4210_GPE2(_nr)   (EXYNOS4210_GPIO_E2_START + (_nr))
>  #define EXYNOS4210_GPE3(_nr)   (EXYNOS4210_GPIO_E3_START + (_nr))
>  #define EXYNOS4210_GPE4(_nr)   (EXYNOS4210_GPIO_E4_START + (_nr))
> +
>  #define EXYNOS4_GPF0(_nr)      (EXYNOS4_GPIO_F0_START + (_nr))
>  #define EXYNOS4_GPF1(_nr)      (EXYNOS4_GPIO_F1_START + (_nr))
>  #define EXYNOS4_GPF2(_nr)      (EXYNOS4_GPIO_F2_START + (_nr))
> @@ -126,6 +145,13 @@ enum exynos4_gpio_number {
>  #define EXYNOS4_GPL0(_nr)      (EXYNOS4_GPIO_L0_START + (_nr))
>  #define EXYNOS4_GPL1(_nr)      (EXYNOS4_GPIO_L1_START + (_nr))
>  #define EXYNOS4_GPL2(_nr)      (EXYNOS4_GPIO_L2_START + (_nr))
> +
> +#define EXYNOS4X12_GPM0(_nr)   (EXYNOS4X12_GPIO_M0_START + (_nr))
> +#define EXYNOS4X12_GPM1(_nr)   (EXYNOS4X12_GPIO_M1_START + (_nr))
> +#define EXYNOS4X12_GPM2(_nr)   (EXYNOS4X12_GPIO_M2_START + (_nr))
> +#define EXYNOS4X12_GPM3(_nr)   (EXYNOS4X12_GPIO_M3_START + (_nr))
> +#define EXYNOS4X12_GPM4(_nr)   (EXYNOS4X12_GPIO_M4_START + (_nr))
> +
>  #define EXYNOS4_GPX0(_nr)      (EXYNOS4_GPIO_X0_START + (_nr))
>  #define EXYNOS4_GPX1(_nr)      (EXYNOS4_GPIO_X1_START + (_nr))
>  #define EXYNOS4_GPX2(_nr)      (EXYNOS4_GPIO_X2_START + (_nr))
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 315aa14..c2ad2be 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -168,9 +168,6 @@
>
>  #define EXYNOS4_MAX_COMBINER_NR                16
>
> -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
> -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
> -
>  /*
>   * For Compatibility:
>   * the default is for EXYNOS4, and
> @@ -238,9 +235,6 @@
>  #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
>  #define IRQ_FIMD0_SYSTEM               EXYNOS4_IRQ_FIMD0_SYSTEM
>
> -#define IRQ_GPIO1_NR_GROUPS            EXYNOS4_IRQ_GPIO1_NR_GROUPS
> -#define IRQ_GPIO2_NR_GROUPS            EXYNOS4_IRQ_GPIO2_NR_GROUPS
> -
>  /* For EXYNOS5 SoCs */
>
>  #define EXYNOS5_IRQ_MDMA0              IRQ_SPI(33)
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index c996440..b5048f5 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -2126,7 +2126,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
>   */
>
>  #ifdef CONFIG_ARCH_EXYNOS4
> -static struct samsung_gpio_chip exynos4_gpios_1[] = {
> +static struct samsung_gpio_chip exynos4210_gpios_1[] = {
>         {
>                 .chip   = {
>                         .base   = EXYNOS4_GPA0(0),
> @@ -2225,10 +2225,93 @@ static struct samsung_gpio_chip exynos4_gpios_1[] = {
>                 },
>         },
>  };
> -#endif
>
> -#ifdef CONFIG_ARCH_EXYNOS4
> -static struct samsung_gpio_chip exynos4_gpios_2[] = {
> +static struct samsung_gpio_chip exynos4x12_gpios_1[] = {
> +       {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPA0(0),
> +                       .ngpio  = EXYNOS4_GPIO_A0_NR,
> +                       .label  = "GPA0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPA1(0),
> +                       .ngpio  = EXYNOS4_GPIO_A1_NR,
> +                       .label  = "GPA1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPB(0),
> +                       .ngpio  = EXYNOS4_GPIO_B_NR,
> +                       .label  = "GPB",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPC0(0),
> +                       .ngpio  = EXYNOS4_GPIO_C0_NR,
> +                       .label  = "GPC0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPC1(0),
> +                       .ngpio  = EXYNOS4_GPIO_C1_NR,
> +                       .label  = "GPC1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPD0(0),
> +                       .ngpio  = EXYNOS4_GPIO_D0_NR,
> +                       .label  = "GPD0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPD1(0),
> +                       .ngpio  = EXYNOS4_GPIO_D1_NR,
> +                       .label  = "GPD1",
> +               },
> +       }, {
> +               .base   = (void *)0x180,
> +               .group  = 12,
> +               .chip   = {
> +                       .base   = EXYNOS4_GPF0(0),
> +                       .ngpio  = EXYNOS4_GPIO_F0_NR,
> +                       .label  = "GPF0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPF1(0),
> +                       .ngpio  = EXYNOS4_GPIO_F1_NR,
> +                       .label  = "GPF1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPF2(0),
> +                       .ngpio  = EXYNOS4_GPIO_F2_NR,
> +                       .label  = "GPF2",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPF3(0),
> +                       .ngpio  = EXYNOS4_GPIO_F3_NR,
> +                       .label  = "GPF3",
> +               },
> +       }, {
> +               .base   = (void *)0x240,
> +               .chip   = {
> +                       .base   = EXYNOS4_GPJ0(0),
> +                       .ngpio  = EXYNOS4_GPIO_J0_NR,
> +                       .label  = "GPJ0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPJ1(0),
> +                       .ngpio  = EXYNOS4_GPIO_J1_NR,
> +                       .label  = "GPJ1",
> +               },
> +       },
> +};
> +
> +static struct samsung_gpio_chip exynos4210_gpios_2[] = {
>         {
>                 .chip   = {
>                         .base   = EXYNOS4_GPJ0(0),
> @@ -2333,6 +2416,172 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>                         .label  = "GPY6",
>                 },
>         }, {
> +               .base   = (void *)0xC00,
> +               .config = &samsung_gpio_cfgs[9],
> +               .irq_base = IRQ_EINT(0),
> +               .chip   = {
> +                       .base   = EXYNOS4_GPX0(0),
> +                       .ngpio  = EXYNOS4_GPIO_X0_NR,
> +                       .label  = "GPX0",
> +                       .to_irq = samsung_gpiolib_to_irq,
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[9],
> +               .irq_base = IRQ_EINT(8),
> +               .chip   = {
> +                       .base   = EXYNOS4_GPX1(0),
> +                       .ngpio  = EXYNOS4_GPIO_X1_NR,
> +                       .label  = "GPX1",
> +                       .to_irq = samsung_gpiolib_to_irq,
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[9],
> +               .irq_base = IRQ_EINT(16),
> +               .chip   = {
> +                       .base   = EXYNOS4_GPX2(0),
> +                       .ngpio  = EXYNOS4_GPIO_X2_NR,
> +                       .label  = "GPX2",
> +                       .to_irq = samsung_gpiolib_to_irq,
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[9],
> +               .irq_base = IRQ_EINT(24),
> +               .chip   = {
> +                       .base   = EXYNOS4_GPX3(0),
> +                       .ngpio  = EXYNOS4_GPIO_X3_NR,
> +                       .label  = "GPX3",
> +                       .to_irq = samsung_gpiolib_to_irq,
> +               },
> +       },
> +};

I see that GPX0, GPX1, GPX2 and GPX3 bank instances are already part
of mainline kernel. How is that this is being added here.

> +
> +static struct samsung_gpio_chip exynos4x12_gpios_2[] = {
> +       {
> +               .base   = (void *)0x040,
> +               .group  = 20,
> +               .chip   = {
> +                       .base   = EXYNOS4_GPK0(0),
> +                       .ngpio  = EXYNOS4_GPIO_K0_NR,
> +                       .label  = "GPK0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPK1(0),
> +                       .ngpio  = EXYNOS4_GPIO_K1_NR,
> +                       .label  = "GPK1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPK2(0),
> +                       .ngpio  = EXYNOS4_GPIO_K2_NR,
> +                       .label  = "GPK2",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPK3(0),
> +                       .ngpio  = EXYNOS4_GPIO_K3_NR,
> +                       .label  = "GPK3",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPL0(0),
> +                       .ngpio  = EXYNOS4_GPIO_L0_NR,
> +                       .label  = "GPL0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPL1(0),
> +                       .ngpio  = EXYNOS4_GPIO_L1_NR,
> +                       .label  = "GPL1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4_GPL2(0),
> +                       .ngpio  = EXYNOS4_GPIO_L2_NR,
> +                       .label  = "GPL2",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY0(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y0_NR,
> +                       .label  = "GPY0",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY1(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y1_NR,
> +                       .label  = "GPY1",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY2(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y2_NR,
> +                       .label  = "GPY2",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY3(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y3_NR,
> +                       .label  = "GPY3",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY4(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y4_NR,
> +                       .label  = "GPY4",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY5(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y5_NR,
> +                       .label  = "GPY5",
> +               },
> +       }, {
> +               .config = &samsung_gpio_cfgs[8],
> +               .chip   = {
> +                       .base   = EXYNOS4_GPY6(0),
> +                       .ngpio  = EXYNOS4_GPIO_Y6_NR,
> +                       .label  = "GPY6",
> +               },
> +       }, {
> +               .base   = (void *)0x260,
> +               .chip   = {
> +                       .base   = EXYNOS4X12_GPM0(0),
> +                       .ngpio  = EXYNOS4X12_GPIO_M0_NR,
> +                       .label  = "GPM0",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4X12_GPM1(0),
> +                       .ngpio  = EXYNOS4X12_GPIO_M1_NR,
> +                       .label  = "GPM1",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4X12_GPM2(0),
> +                       .ngpio  = EXYNOS4X12_GPIO_M2_NR,
> +                       .label  = "GPM2",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4X12_GPM3(0),
> +                       .ngpio  = EXYNOS4X12_GPIO_M3_NR,
> +                       .label  = "GPM3",
> +               },
> +       }, {
> +               .chip   = {
> +                       .base   = EXYNOS4X12_GPM4(0),
> +                       .ngpio  = EXYNOS4X12_GPIO_M4_NR,
> +                       .label  = "GPM4",
> +               },
> +       }, {
> +               .base   = (void *)0xC00,
>                 .config = &samsung_gpio_cfgs[9],
>                 .irq_base = IRQ_EINT(0),
>                 .chip   = {
> @@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>                 },
>         },
>  };

There are no GPX banks instantiated here for 4x12. What is the reason for that?

> -#endif
>
> -#ifdef CONFIG_ARCH_EXYNOS4
>  static struct samsung_gpio_chip exynos4_gpios_3[] = {
>         {
>                 .chip   = {
> @@ -2727,12 +2974,15 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,

What is the limitation in adding support for GPVx as well for 4x12 ?

>
>  static __init void exynos4_gpiolib_init(void)
>  {
> -#ifdef CONFIG_CPU_EXYNOS4210
> +#ifdef CONFIG_ARCH_EXYNOS4
>         struct samsung_gpio_chip *chip;
>         int i, nr_chips;
>         void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
>         int group = 0;
>         void __iomem *gpx_base;
> +       struct samsung_gpio_chip *chip_p;
> +       int offset = 0;
> +       int group1 = 0;
>
>         /* gpio part1 */
>         gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
> @@ -2741,19 +2991,31 @@ static __init void exynos4_gpiolib_init(void)
>                 goto err_ioremap1;
>         }
>
> -       chip = exynos4_gpios_1;
> -       nr_chips = ARRAY_SIZE(exynos4_gpios_1);
> +       if (soc_is_exynos4210()) {
> +               chip = chip_p = exynos4210_gpios_1;
> +               nr_chips = ARRAY_SIZE(exynos4210_gpios_1);
> +       } else {
> +               chip = chip_p = exynos4x12_gpios_1;
> +               nr_chips = ARRAY_SIZE(exynos4x12_gpios_1);
> +       }
>
>         for (i = 0; i < nr_chips; i++, chip++) {
>                 if (!chip->config) {
>                         chip->config = &exynos_gpio_cfg;
> +                       if (chip->group)
> +                               group = chip->group;
>                         chip->group = group++;
>                 }
> -               exynos_gpiolib_attach_ofnode(chip,
> -                               EXYNOS4_PA_GPIO1, i * 0x20);
> +
> +               if (chip->base)
> +                       offset = (u32)chip->base;
> +               chip->base = gpio_base1 + offset;
> +               offset += 0x20;
> +
> +               exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO1, 0);
>         }
> -       samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
> -                                      nr_chips, gpio_base1);
> +       samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base1);
> +       group1 = group;
>
>         /* gpio part2 */
>         gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
> @@ -2762,25 +3024,32 @@ static __init void exynos4_gpiolib_init(void)
>                 goto err_ioremap2;
>         }
>
> -       /* need to set base address for gpx */
> -       chip = &exynos4_gpios_2[16];
> -       gpx_base = gpio_base2 + 0xC00;
> -       for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
> -               chip->base = gpx_base;
> +       if (soc_is_exynos4210()) {
> +               chip = chip_p = exynos4210_gpios_2;
> +               nr_chips = ARRAY_SIZE(exynos4210_gpios_2);
> +       } else {
> +               chip = chip_p = exynos4x12_gpios_2;
> +               nr_chips = ARRAY_SIZE(exynos4x12_gpios_2);
> +       }
>
> -       chip = exynos4_gpios_2;
> -       nr_chips = ARRAY_SIZE(exynos4_gpios_2);
> +       offset = 0;
>
>         for (i = 0; i < nr_chips; i++, chip++) {
>                 if (!chip->config) {
>                         chip->config = &exynos_gpio_cfg;
> +                       if (chip->group)
> +                               group = chip->group;
>                         chip->group = group++;
>                 }
> -               exynos_gpiolib_attach_ofnode(chip,
> -                               EXYNOS4_PA_GPIO2, i * 0x20);
> +
> +               if (chip->base)
> +                       offset = (u32)chip->base;
> +               chip->base = gpio_base2 + offset;
> +               offset += 0x20;
> +
> +               exynos_gpiolib_attach_ofnode(chip, EXYNOS4_PA_GPIO2, 0);
>         }
> -       samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
> -                                      nr_chips, gpio_base2);
> +       samsung_gpiolib_add_4bit_chips(chip_p, nr_chips, gpio_base2);
>
>         /* gpio part3 */
>         gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
> @@ -2801,12 +3070,10 @@ static __init void exynos4_gpiolib_init(void)
>                                 EXYNOS4_PA_GPIO3, i * 0x20);
>         }
>         samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
> -                                      nr_chips, gpio_base3);
> +                                       nr_chips, gpio_base3);
>
> -#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
> -       s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
> -       s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
> -#endif
> +       s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, group1);
> +       s5p_register_gpioint_bank(IRQ_GPIO_XB, group1, group - group1);
>
>         return;
>
> @@ -2816,7 +3083,7 @@ err_ioremap2:
>         iounmap(gpio_base1);
>  err_ioremap1:
>         return;
> -#endif /* CONFIG_CPU_EXYNOS4210 */
> +#endif /* CONFIG_ARCH_EXYNOS4 */
>  }
>
>  static __init void exynos5_gpiolib_init(void)
> @@ -3010,7 +3277,8 @@ static __init int samsung_gpiolib_init(void)
>  #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
>                 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
>  #endif
> -       } else if (soc_is_exynos4210()) {
> +       } else if (soc_is_exynos4210() || soc_is_exynos4212() ||
> +                       soc_is_exynos4412()) {
>                 exynos4_gpiolib_init();
>         } else if (soc_is_exynos5250()) {
>                 exynos5_gpiolib_init();
> --
> 1.7.12
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From 21cnbao at gmail.com  Tue Aug 28 10:57:59 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 28 Aug 2012 22:57:59 +0800
Subject: [PATCH 2/3] ARM: PRIMA2: make mach-prima2 common for all SiRF
 series SoC
In-Reply-To: <503CD58C.1010703@wwwdotorg.org>
References: <1345450787-17246-1-git-send-email-Barry.Song@csr.com>
 <201208210757.32852.arnd@arndb.de>
 <CAGsJ_4yRbFrH8NPJZ6-gU1BebqVkQEBz_GLr4owQz+XpOyejug@mail.gmail.com>
 <201208210920.52816.arnd@arndb.de>
 <CAGsJ_4x4DdHsNgh7ArkD1fCHT22rxRs18vcobHtpSXJ-cq3o4Q@mail.gmail.com>
 <CAGsJ_4y3Snvf-2DLSrpU5+zmytkARtNxJN_nPdiOngd+BK-aDA@mail.gmail.com>
 <503CD58C.1010703@wwwdotorg.org>
Message-ID: <CAGsJ_4zgdsGE=Htuvg7+OGh8+2efUBMNyWBYmq5MhnBOgG+MLg@mail.gmail.com>

2012/8/28 Stephen Warren <swarren at wwwdotorg.org>:
> On 08/28/2012 01:08 AM, Barry Song wrote:
>> 2012/8/28 Barry Song <21cnbao at gmail.com>:
>>> 2012/8/21 Arnd Bergmann <arnd at arndb.de>:
>>>> On Tuesday 21 August 2012, Barry Song wrote:
>>>>> then i add these to Kconfig.debug as it is a common way
>>>>>
>>>>>         config DEBUG_PRIMA2_UART1
>>>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
>>>>>                 depends on ARCH_PRIMA2
>>>>>                 help
>>>>>                   Say Y here if you want the debug print routines to direct
>>>>>                   their output to UART1 serial port on SiRFprimaII devices.
>>>>>
>>>>>         config DEBUG_MARCO_UART1
>>>>>                 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
>>>>>                 depends on ARCH_MARCO
>>>>>                 help
>>>>>                   Say Y here if you want the debug print routines to direct
>>>>>                   their output to UART1 serial port on SiRFmarco devices.
>>>>>
>>>>> and these in mach-prima2/include/mach/uart.h
>>>>>
>>>>>   #ifdef CONFIG_DEBUG_PRIMA2_UART1
>>>>>   #define SIRFSOC_UART1_PA_BASE          0xb0060000
>>>>>   #elif defined(CONFIG_DEBUG_MARCO_UART1)
>>>>>   #define SIRFSOC_UART1_PA_BASE          0xcc060000
>>>>>   #endif
>>>>>
>>>>> the above codes seem still ugly ?
>>>>>
>>>>
>>>> No, that's fine, about as a good as it gets with today's kernel
>>>> capabilities. Just fix the description to have the correct
>>>> SoC name instead of "DaVinci DA8XX" ;-)
>>>
>>> except the DEBUG_LL uart base address, i missed the zreladdr-y. for
>>> primaii, it is 0x00008000, for marco, it is 0x40008000 as marco's
>>> memory space begins from 0x4000000.
>>> i would to have AUTO_ZRELADDR for the whole SiRF series.
>>> but for uImage load address difference in uImage header, which blocks
>>> multiple SoCs from using same uImage, is "KERNEL_NOLOAD" uImage type
>>> the current generic solution?
>>
>> also add Stephen Warren.
>>
>> i have two verified ways to resolve this problem:
>>
>> 1. use "kernel noload", build uImage by:
>>
>> make uImage UIMAGE_TYPE=kernel_noload
>> and add the following patch in kernel:
>
> Very recent U-Boot have a bootz command, which acts just like bootm, but
> allows use of a raw zImage or the kernel, rather than a
> uImage-wrapped-zImage. This was implemented by Marek Vasut.

Thanks, Stephen. i guess xianglong will try bootz on SiRFmarco and try
to move from uImage to raw zImage.

Based on your past "kernel_noload" support patch, we actually can
compile an uImage by:
make uImage UIMAGE_TYPE=kernel_noload UIMAGE_ENTRYADDR=0x0
and it gets a cross-SoCs uImage which doesn't care about zreladdr-y in
Makefile.boot.
actually it just jumps to (loaded uImage dram address + 0x40).

anyway, we don't need to modify mach-prima2/Makefile.boot for marco any more.

do people think we have a chance to delete mach-xxx/Makefile.boot for
some platforms if  zreladdr-y and related address don't make many
senses again?

-barry


From thomas.abraham at linaro.org  Tue Aug 28 10:58:30 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 28 Aug 2012 20:28:30 +0530
Subject: [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
In-Reply-To: <4648723.rWnut7F0uJ@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227>
Message-ID: <CAJuYYwTBeCczF7M=9pJzYUgGB3Xg1md2kRDKbYEU-ji-C1_hug@mail.gmail.com>

On 28 August 2012 15:31, Tomasz Figa <t.figa at samsung.com> wrote:
> This patch series makes necessary preparations and adds support for GPIO on
> Exynos4x12 SoCs.
>
> Tomasz Figa (3):
>   ARM: EXYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx
>   gpio: samsung: Add support for Exynos4x12 SoCs
>   ARM: EXYNOS: Add support for FIMC cam port B GPIO setup on Exynos4x12
>
>  arch/arm/mach-exynos/include/mach/gpio.h   |   58 ++++--
>  arch/arm/mach-exynos/include/mach/irqs.h   |    6 -
>  arch/arm/mach-exynos/mach-nuri.c           |   16 +-
>  arch/arm/mach-exynos/mach-origen.c         |    6 +-
>  arch/arm/mach-exynos/mach-trats.c          |    4 +-
>  arch/arm/mach-exynos/mach-universal_c210.c |   32 ++--
>  arch/arm/mach-exynos/setup-fimc.c          |   21 ++-
>  drivers/gpio/gpio-samsung.c                |  351
> ++++++++++++++++++++++++----
>  8 files changed, 399 insertions(+), 95 deletions(-)
>
> --
> 1.7.8.6

Hopefully, we can get device tree support merged for Exynos4412 soon
and then switch over to using pinctrl driver. That can simplfy the
gpio/pinmux support for Exynos4 SoC's.

Thanks,
Thomas.


From ludovic.desroches at atmel.com  Tue Aug 28 11:10:00 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Tue, 28 Aug 2012 17:10:00 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>
Message-ID: <503CDF48.5080201@atmel.com>

Hi Nikolaus,

I forgot one correction I did in your patch:

Le 11/08/2011 11:49 AM, Nikolaus Voss a ?crit :
[...]

> diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
> index 9295e90..27fddc1 100644
> --- a/arch/arm/mach-at91/at91sam9261_devices.c
> +++ b/arch/arm/mach-at91/at91sam9261_devices.c
> @@ -283,9 +283,18 @@ static struct i2c_gpio_platform_data pdata = {
>   	.udelay			= 2,		/* ~100 kHz */
>   };
>
> +static const struct platform_device_id twi_ip_type = {
> +	/*
> +	 * driver_data is 2 for SAM9261 compatible ip, see enum twi_ip_id in
> +	 * drivers/i2c/busses/i2c-at91.c
> +	 */
> +	.driver_data	= 2,
> +};
> +
>   static struct platform_device at91sam9261_twi_device = {
>   	.name			= "i2c-gpio",
>   	.id			= -1,
> +	.id_entry		= &twi_ip_type,
>   	.dev.platform_data	= &pdata,
>   };
>

[...]

You add the id_entry to the i2c-gpio device instead of at91_i2c device.

Regards

Ludovic


From ldewangan at nvidia.com  Tue Aug 28 10:49:45 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Tue, 28 Aug 2012 20:19:45 +0530
Subject: [PATCH 1/2] ARM: tegra: remove dead code
In-Reply-To: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
References: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <503CDA89.2020403@nvidia.com>

On Tuesday 28 August 2012 12:39 PM, Stephen Warren wrote:
> From: Stephen Warren<swarren at nvidia.com>
>
> Now that all boards are converted to device tree, devices.[ch] and
> board-pinmux.[ch] are no longer used. So, remove them.
>
> The only exception is the EHCI platform data in devices.h. Move that
> data to board-dt-tegra20.c - the only places it's used.
>
> Signed-off-by: Stephen Warren<swarren at nvidia.com>
> ---
> These patches are both destined for Tegra's for-3.7/board-removal branch.


I applied both patches and it crash on with following log:
[    1.652934] VFP support v0.3: implementor 41 architecture 3 part 30 
variant 9
  rev 1
[    1.661661] Unable to handle kernel paging request at virtual address 
fffffe0
7
[    1.670980] pgd = c0004000
[    1.673711] [fffffe07] *pgd=2f7fe821, *pte=00000000, *ppte=00000000
[    1.679988] Internal error: Oops: 17 [#1] PREEMPT SMP ARM
[    1.685369] Modules linked in:
[    1.688419] CPU: 0    Not tainted  (3.6.0-rc3-next-20120824-dirty #2)
[    1.694852] PC is at regulator_disable+0x4/0x60
[    1.699378] LR is at harmony_pcie_init+0x50/0xa0
[    1.703983] pc : [<c01f71f0>]    lr : [<c05e3810>]    psr: 20000013
[    1.703983] sp : ef04bf38  ip : 22222222  fp : 00000000
[    1.715434] r10: c05dd690  r9 : c0602eb0  r8 : c05db26c
[    1.720642] r7 : 00000000  r6 : fffffdfb  r5 : c0459004  r4 : fffffdfb
[    1.727151] r3 : 00000000  r2 : 00000000  r1 : 00000000  r0 : fffffdfb
[    1.733663] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  
Segment kern
el
[    1.740953] Control: 10c5387d  Table: 0000404a  DAC: 00000015
[    1.746682] Process swapper/0 (pid: 1, stack limit = 0xef04a2f0)
[    1.752672] Stack: (0xef04bf38 to 0xef04c000)
[    1.757015] 
bf20:                                                       fffff
dfb c0459004
[    1.765174] bf40: fffffdfb c05e3810 00000002 c0459004 c045900c 
c05e3718 c05e3
710 c05e36f8
[    1.773333] bf60: c05fd8ec ef04a000 c06595c0 c05dd6ac 00000000 c00085c8


From ldewangan at nvidia.com  Tue Aug 28 11:04:11 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Tue, 28 Aug 2012 20:34:11 +0530
Subject: [PATCH 2/2] ARM: dt: tegra: harmony: add regulators
In-Reply-To: <1346137800-7448-2-git-send-email-swarren@wwwdotorg.org>
References: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
 <1346137800-7448-2-git-send-email-swarren@wwwdotorg.org>
Message-ID: <503CDDEB.1050201@nvidia.com>

On Tuesday 28 August 2012 12:40 PM, Stephen Warren wrote:
>   #include "board.h"
> -#include "board-harmony.h"
>
>   #ifdef CONFIG_TEGRA_PCI
>
>   int __init harmony_pcie_init(void)
>   {
> -       struct regulator *regulator = NULL;
> +       struct regulator *regulator_1v5, *regulator_pex;
>          int err;
>
> -       err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
> -       if (err)
> -               return err;
> +       regulator_1v5 = regulator_get(NULL, "vdd_1v5");
> +       if (IS_ERR_OR_NULL(regulator_1v5)) {
> +               err = PTR_ERR(regulator_1v5);
> +               goto err_reg;
> +       }

You need to return in case of err otherwise it will cause the crash in 
regulator_disable() with NULL argument.




From N.Voss at weinmann.de  Tue Aug 28 11:32:52 2012
From: N.Voss at weinmann.de (Voss, Nikolaus)
Date: Tue, 28 Aug 2012 17:32:52 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <503CDF48.5080201@atmel.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>
 <503CDF48.5080201@atmel.com>
Message-ID: <EF2E73589CA71846A15D0B2CDF79505D090EC3DB91@wm021.weinmann.com>

Hi Ludovic,

ludovic.desroches wrote on Tuesday, August 28, 2012 5:10 PM:
> > +static const struct platform_device_id twi_ip_type = {
> > +	/*
> > +	 * driver_data is 2 for SAM9261 compatible ip, see enum twi_ip_id in
> > +	 * drivers/i2c/busses/i2c-at91.c
> > +	 */
> > +	.driver_data	= 2,
> > +};
> > +
> >   static struct platform_device at91sam9261_twi_device = {
> >   	.name			= "i2c-gpio",
> >   	.id			= -1,
> > +	.id_entry		= &twi_ip_type,
> >   	.dev.platform_data	= &pdata,
> >   };
> >
> 
> [...]
> 
> You add the id_entry to the i2c-gpio device instead of at91_i2c device.

Oh! I'll post the complete series tomorrow.

Regards,
Niko



From matthew.leach at arm.com  Tue Aug 28 11:41:28 2012
From: matthew.leach at arm.com (Matthew Leach)
Date: Tue, 28 Aug 2012 16:41:28 +0100
Subject: [PATCH v3] serial: pl011: honour serial aliases in device tree
Message-ID: <1346168488-9309-1-git-send-email-matthew.leach@arm.com>

If the order of UART nodes is changed in the device tree, then tty dev
devices are attached to different serial ports causing the console to
be directed to a different physical serial port. The "serial" aliases
in the device tree should prevent this.

This patch ensures that the UART driver creates tty devices that
honour these aliases if a device tree is present.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Reviewed-by: Will Deacon <will.deacon at arm.com>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Matthew Leach <matthew.leach at arm.com>
---
v3: minor consistency correction
v2: use IS_ENABLED instead of ifdefs
 drivers/tty/serial/amba-pl011.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index d3553b5..dc05dd1 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,8 @@
 #include <linux/scatterlist.h>
 #include <linux/delay.h>
 #include <linux/types.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/sizes.h>
 
@@ -1869,6 +1871,38 @@ static struct uart_driver amba_reg = {
 	.cons			= AMBA_CONSOLE,
 };
 
+static int pl011_probe_dt_alias(int index, struct device *dev)
+{
+	struct device_node *np;
+	static bool seen_dev_with_alias = false;
+	static bool seen_dev_without_alias = false;
+	int ret = index;
+
+	if (!IS_ENABLED(CONFIG_OF))
+		return ret;
+
+	np = dev->of_node;
+	if (!np)
+		return ret;
+
+	ret = of_alias_get_id(np, "serial");
+	if (IS_ERR_VALUE(ret)) {
+		seen_dev_without_alias = true;
+		ret = index;
+	} else {
+		seen_dev_with_alias = true;
+		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
+			dev_warn(dev, "requested serial port %d  not available.\n", ret);
+			ret = index;
+		}
+	}
+
+	if (seen_dev_with_alias && seen_dev_without_alias)
+		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
+
+	return ret;
+}
+
 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 {
 	struct uart_amba_port *uap;
@@ -1891,6 +1925,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto out;
 	}
 
+	i = pl011_probe_dt_alias(i, &dev->dev);
+
 	base = ioremap(dev->res.start, resource_size(&dev->res));
 	if (!base) {
 		ret = -ENOMEM;
-- 
1.7.0.4



From maxime.ripard at free-electrons.com  Tue Aug 28 12:02:24 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Tue, 28 Aug 2012 18:02:24 +0200
Subject: [PATCH] ARM: dts: mxs: Add the second I2C adapter to the CFA10049
 expansion board
Message-ID: <1346169744-24674-1-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/imx28-cfa10049.dts |   31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx28-cfa10049.dts

diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 0000000..e0e4b8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+	model = "Crystalfontz CFA-10049 Board";
+	compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+
+	apb at 80000000 {
+		apbx at 80040000 {
+			i2c1: i2c at 8005a000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c1_pins_a>;
+				status = "okay";
+			};
+		};
+	};
+};
-- 
1.7.9.5



From jason at lakedaemon.net  Tue Aug 28 11:30:50 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 11:30:50 -0400
Subject: dreamplug spi partitions
In-Reply-To: <1345566505.6821.115.camel@zakaz.uk.xensource.com>
References: <1344498477.11783.38.camel@dagon.hellion.org.uk>
 <20120816142005.GS22226@titan.lakedaemon.net>
 <1345566505.6821.115.camel@zakaz.uk.xensource.com>
Message-ID: <20120828153050.GD19437@titan.lakedaemon.net>

On Tue, Aug 21, 2012 at 05:28:25PM +0100, Ian Campbell wrote:
> On Thu, 2012-08-16 at 10:20 -0400, Jason Cooper wrote:
> > On Thu, Aug 09, 2012 at 08:47:57AM +0100, Ian Campbell wrote:
> > > Hi all,
> > > 
> > > I've been using "fw_printenv" and "fw_setenv" from the u-boot-tools
> > > package on my DreamPlug which work fine with this /etc/fw_env.config:
> > >         # Configuration file for fw_(printenv/saveenv) utility.
> > >         # Up to two entries are valid, in this case the redundant
> > >         # environment sector is assumed present.
> > >         # MTD device name       Device offset   Env. size       Flash sector size
> > >         /dev/mtd1               0x00000000      0x00001000      0x00001000
> > >         
> > > This corresponds roughly, but not exactly, with:
> > >         # cat /proc/mtd 
> > >         dev:    size   erasesize  name
> > >         mtd0: 00080000 00001000 "u-boot"
> > >         mtd1: 00010000 00001000 "u-boot env"
> > >         mtd2: 00010000 00001000 "dtb"
> > > 
> > > But notice how "Env. size" and mtd1's size don't match -- if I use
> > > 0x10000 in fw_env.cfg then the tools don't work (checksums don't match).
> > 
> > I've always seen the u-boot environment set to 4k.
> 
> Right, so it seems like that is the right size for the kernel to report
> then?
> 
> >   The kernel
> > partitions came out of my head.  When I added support for the dreamplug
> > to u-boot, I found out there was a bug in the factory supplied u-boot
> > which only allowed it to see the first 1MB of the 2MB flash.  Also, the
> > factory supplied kernel didn't even have support for the flash.
> > 
> > So, I fixed u-boot, and figured the extra 1MB was too small for a
> > kernel, wasn't used by anybody else, and imho, the factory location of
> > the environment didn't leave much room for new u-boots.
> > 
> > I decided to move the environment and make a place for the dtb.  As I
> > didn't want to constrain either one, I split the extra space between the
> > two.
> > 
> > Was that the best decision?  Well, no one yelled at me and I was new to
> > the whole process, so that's how it went down.
> 
> ;-)
> 
> I'm not saying the partitioning scheme is wrong or trying to criticize,
> I just noticed that upstream u-boot and the kernel are inconsistent.
> 
> I haven't looked at the factory u-boot, I wouldn't be too torn up if it
> matched neither of the other two though.
> 
> > As it is right now, if you configure your own u-boot to have, say
> > 0x10000 bytes for the environment, you don't need to change your kernel
> > to support it.  Just set the size and write it.
> > 
> > I'm open to suggestions and patches...
> 
> I think upstream u-boot and the kernel should match, but I'm not really
> sure which one should be changed to match the other.
> 
> At this point I suppose it is generally easier for people to change
> their kernel so that should be the one to change?

Before we go changing anything, what is the maximum size a uboot
environment or a dtb can be?  Until we can nail that down, I'm inclined
to leave the partitions at their current locations and only adjust the
size of the environment down to 4k in the kernel.

This way, a user foolishly attempting to write more than 4k will get an
error.

If a user changes out their uboot to get a larger environment, they can
adjust the dts as well.  No kernel rebuilding necessary.

thx,

Jason.


From sboyd at codeaurora.org  Tue Aug 28 12:21:40 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Tue, 28 Aug 2012 09:21:40 -0700
Subject: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on
 Exynos4412
In-Reply-To: <1422318.SfZfh0XoVo@amdc1227>
References: <1422318.SfZfh0XoVo@amdc1227>
Message-ID: <503CF014.8010503@codeaurora.org>

On 8/28/2012 4:13 AM, Tomasz Figa wrote:
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 36c3984..1114ced 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -34,8 +34,19 @@
>  
>  extern void exynos4_secondary_startup(void);
>  
> -#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
> -				S5P_INFORM5 : S5P_VA_SYSRAM)
> +static inline volatile void *cpu_boot_reg_base(void)

__iomem?

> +{
> +	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> +		return S5P_INFORM5;
> +	return S5P_VA_SYSRAM;
> +}
> +
> +static inline volatile void *cpu_boot_reg(int cpu)

__iomem? And why volatile?

> +{
> +	if (soc_is_exynos4412())
> +		return cpu_boot_reg_base() + 4*cpu;
> +	return cpu_boot_reg_base();
> +}
>  
>  /*
>   * control for which core is the next to come out of the secondary
> @@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
>  	 * until it receives a soft interrupt, and then the
>  	 * secondary CPU branches to this address.
>  	 */
> -	__raw_writel(virt_to_phys(exynos4_secondary_startup),
> -			CPU1_BOOT_REG);
> +	for (i = 1; i < max_cpus; ++i) {
> +		__raw_writel(virt_to_phys(exynos4_secondary_startup),
> +							cpu_boot_reg(i));

Do you need to use cpu_logical_map()?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From frankyl at broadcom.com  Tue Aug 28 12:45:39 2012
From: frankyl at broadcom.com (Franky Lin)
Date: Tue, 28 Aug 2012 09:45:39 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR
 directly for non-OOB
In-Reply-To: <1346152413.3516.211.camel@tegra-chromium-2>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com> <503BD345.6030501@wwwdotorg.org>
 <1346152413.3516.211.camel@tegra-chromium-2>
Message-ID: <503CF5B3.8040201@broadcom.com>

On 08/28/2012 04:13 AM, Wei Ni wrote:
> On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
>> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
>>> On 08/27/2012 12:25 PM, Wei Ni wrote:
>>>> In case of inband interrupts, if we handle the interrupt in dpc thread,
>>>> two level of thread switching takes place to process wifi interrupts.
>>>> One in SDHCI driver and the other in Wifi driver. This may cause the
>>>> system
>>>> instability.
>>>
>>> Looking into the sdhci/mmc code indeed shows that the brcmfmac irq
>>> handler is not called in true IRQ context. So the dpc thread may add
>>> unnecessary complexity, but to me there is not indication that there is
>>> a stability issue.
>
> The brcmfmac irq handler is called in the thread sdio_irq_thread(), this
> thread indeed is driven by the sdhci irq, although it's not the true IRQ
> context. If the brcmfmac doesn't clear the IRQ condition ASAP, the
> sdio_irq_thread will be triggered again and again, and in this condition
> it's too difficult to run the brcmfmac dpc thread, more and more
> interrupt can't be handled.
>
>>>
>>>> Because the SDHCI calls sdio_irq_thread() to handle the irq, this
>>>> thread locks
>>>> mmc host and calls wifi handler. It expects WiFi handler to be quick and
>>>> enables sdio interrupt from card at end. If wifi handler defers this
>>>> work for
>>>> a different thread, sdio_irq_thread() will be stuck on next wifi
>>>> interrupt
>>>> since mmc lock is not freed.
>>>
>>> Not sure if I can follow this explanation. The isr is called with host
>>> claimed (by sdio_irq_thread) and all it does is at a linked list member
>>> and signal the dpc thread. After doing this the host is released.
>>
>> Is the issue something like the ISR handler or first level of threading
>> does:
>>
>> * Trigger DPC
>> * Re-enable interrupt
>>
>> So that the interrupt then fires again before the triggered DPC can run
>> to handle/clear it, thus causing an interrupt storm?
>>
>> Whereas handling the interrupt directly prevents this race condition?
>
> Above is my understanding.
>

Hi Wei,

I understand the issue here and totally agree that we should treat 
in-band and out-band interrupts differently. But my concern is that the 
behavior of releasing the host before calling brcmf_sdbrcm_isr and grab 
it after is likely error prone. Also we are restructuring the dpc 
routine internally and it's almost done. I will find a better solution 
for in-band interrupt and get it the queue as well. So I suggest 
dropping this patch.

Thanks,
Franky



From broonie at opensource.wolfsonmicro.com  Tue Aug 28 12:48:26 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 09:48:26 -0700
Subject: [PATCH v2 02/14] MFD: twl4030-audio: Convert to use devm_kzalloc
In-Reply-To: <1346147410.2182.96.camel@sokoban>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
 <1344954162-7985-3-git-send-email-peter.ujfalusi@ti.com>
 <1346147410.2182.96.camel@sokoban>
Message-ID: <20120828164825.GA4534@opensource.wolfsonmicro.com>

On Tue, Aug 28, 2012 at 12:50:10PM +0300, Tero Kristo wrote:
> On Tue, 2012-08-14 at 17:22 +0300, Peter Ujfalusi wrote:
> > Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>

> I think this one could use a short commit message, also about why
> kfree():s are dropped (handled internally by devm_* etc.)

Honestly I think people should be able to figure this out, it's not like
it's an obscure API nobody ever used before.


From m.szyprowski at samsung.com  Tue Aug 28 12:51:00 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 28 Aug 2012 18:51:00 +0200
Subject: [v4 0/4] ARM: dma-mapping: IOMMU atomic allocation
In-Reply-To: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
References: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <503CF6F4.7060702@samsung.com>

Hello,

On 8/28/2012 7:13 AM, Hiroshi Doyu wrote:
> The commit e9da6e9 "ARM: dma-mapping: remove custom consistent dma
> region" breaks the compatibility with existing drivers. This causes
> the following kernel oops(*1). That driver has called dma_pool_alloc()
> to allocate memory from the interrupt context, and it hits
> BUG_ON(in_interrpt()) in "get_vm_area_caller()". This patch seris
> fixes this problem with making use of the pre-allocate atomic memory
> pool which DMA is using in the same way as DMA does now.
>
> Any comment would be really appreciated.

Looks fine now. I will do some tests and apply them to my fixes-for-3.6
branch. Thanks for Your contribution!

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From davidb at codeaurora.org  Tue Aug 28 12:55:32 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 28 Aug 2012 09:55:32 -0700
Subject: [GIT PULL] msm fixes for v3.6
Message-ID: <20120828165532.GA20947@codeaurora.org>

The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:

  Linux 3.5 (2012-07-21 13:58:29 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git tags/msm-fix-for3.6

for you to fetch changes up to e7501de53aa1a551526872f6c95901a00705f942:

  ARM: msm: Remove call to missing FPGA init on 8660 (2012-08-28 09:39:28 -0700)

----------------------------------------------------------------
Fixes for two problems with MSM:

  - Mapping issue on 7x00 targets.
  - Compilation problems with devicetree on 8660.

----------------------------------------------------------------
David Brown (1):
      ARM: msm: Remove call to missing FPGA init on 8660

Rohit Vaswani (2):
      ARM: msm: io: Remove 7x30 iomap region from 7x00
      ARM: msm: io: Change the default static iomappings to be shared

Stephen Boyd (2):
      ARM: msm: Add handle_irq handler for 8660 DT machine
      ARM: msm: Add msm8660-surf.dts to Makefile.boot

 arch/arm/mach-msm/Makefile.boot   |  2 ++
 arch/arm/mach-msm/board-msm8x60.c |  6 +-----
 arch/arm/mach-msm/io.c            | 28 +++++++++++++++++-----------
 3 files changed, 20 insertions(+), 16 deletions(-)

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From broonie at opensource.wolfsonmicro.com  Tue Aug 28 13:06:25 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 10:06:25 -0700
Subject: [PATCH] MFD : MC13783 : add regulators sw1x and sw2x
In-Reply-To: <1346152150-21669-1-git-send-email-gcembed@gmail.com>
References: <1346152150-21669-1-git-send-email-gcembed@gmail.com>
Message-ID: <20120828170625.GC4534@opensource.wolfsonmicro.com>

On Tue, Aug 28, 2012 at 01:09:10PM +0200, Ga?tan Carlier wrote:
> 
> Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Tue Aug 28 13:13:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 10:13:20 -0700
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <CAOMZO5B2feJzbqEQgJm_gKDcZPSKuckXWj=s+b+5R39Tnv7-kw@mail.gmail.com>
References: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
 <20120822192723.GS7995@opensource.wolfsonmicro.com>
 <CAOMZO5B2feJzbqEQgJm_gKDcZPSKuckXWj=s+b+5R39Tnv7-kw@mail.gmail.com>
Message-ID: <20120828171320.GE4534@opensource.wolfsonmicro.com>

On Wed, Aug 22, 2012 at 04:38:26PM -0300, Fabio Estevam wrote:
> On Wed, Aug 22, 2012 at 4:27 PM, Mark Brown

> > in that it stops boot hanging on the board, though it still doesn't make
> > AC'97 come out of reset happily.  That's probably some separate issue
> > (pinmux perhaps?) though.

> Yes, looks like a separate issue.

> Did imx_ssi_probe go successfully? What is the error log you are getting?

The controller probes but there's no perceptible activity on the pins
when we try to reset the CODEC so no register I/O.


From broonie at opensource.wolfsonmicro.com  Tue Aug 28 13:17:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 10:17:16 -0700
Subject: [RESUBMIT PATCH] ASoC: SAMSUNG: Change Kconfig to support all
 SAMSUNG ASoC
In-Reply-To: <003301cd84fa$eb8a6b20$c29f4160$@samsung.com>
References: <003301cd84fa$eb8a6b20$c29f4160$@samsung.com>
Message-ID: <20120828171716.GG4534@opensource.wolfsonmicro.com>

On Tue, Aug 28, 2012 at 05:55:49PM +0900, Sangsu Park wrote:
> All SAMSUNG ASoC needs SND_SOC_SAMSUNG configuration.
> This patch change Kconfig to support all SAMSUNG ASoC.

Applied, thanks.


From broonie at opensource.wolfsonmicro.com  Tue Aug 28 13:21:33 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 10:21:33 -0700
Subject: [PATCH RESEND 1/4] ARM: OMAP2+: AM33XX: Add tps65910 device tree
 data
In-Reply-To: <20120828112603.GC25786@gmail.com>
References: <1342766789-28148-1-git-send-email-anilkumar@ti.com>
 <1342766789-28148-2-git-send-email-anilkumar@ti.com>
 <20120720095935.GQ4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13E9FA91E@DBDE01.ent.ti.com>
 <20120720113806.GW4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA01F1E@DBDE01.ent.ti.com>
 <20120723133400.GU4435@opensource.wolfsonmicro.com>
 <20120828112603.GC25786@gmail.com>
Message-ID: <20120828172133.GH4534@opensource.wolfsonmicro.com>

On Tue, Aug 28, 2012 at 12:26:07PM +0100, Lee Jones wrote:

> > > arch/arm/boot/dts/db8500.dtsi

> > I'm not actually seeing anything terribly problematic here, though the
> > regulator-name properties should really be removed as they're fairly
> > useless and seem to be missing the point of having the property.

> Just looking at this now. 

> The regulator-name property is used to populate constrains->name. Are
> you sure you still want them all removed?

Yes, of course.  There's no way that a generic .dtsi used for any
possible board could come up with a sensible value.


From festevam at gmail.com  Tue Aug 28 13:22:41 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 28 Aug 2012 14:22:41 -0300
Subject: [PATCH v2 1/2] ARM: clk-imx35: Fix SSI clock registration
In-Reply-To: <20120828171320.GE4534@opensource.wolfsonmicro.com>
References: <1345466362-2576-1-git-send-email-fabio.estevam@freescale.com>
 <20120822192723.GS7995@opensource.wolfsonmicro.com>
 <CAOMZO5B2feJzbqEQgJm_gKDcZPSKuckXWj=s+b+5R39Tnv7-kw@mail.gmail.com>
 <20120828171320.GE4534@opensource.wolfsonmicro.com>
Message-ID: <CAOMZO5CnEFHfw5iCW0vqwLHOwqdyuWzb_dtVqF5QLD3rjFAShQ@mail.gmail.com>

On Tue, Aug 28, 2012 at 2:13 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:

>> Did imx_ssi_probe go successfully? What is the error log you are getting?
>
> The controller probes but there's no perceptible activity on the pins
> when we try to reset the CODEC so no register I/O.

Take a look at pcm043_ac97_cold_reset/pcm043_ac97_warm_reset at
arch/arm/mach-imx/mach-pcm043.c
to see how GPIO pins are handled for resetting ac97 codec on this platform.

Regards,

Fabio Estevam


From jason at lakedaemon.net  Tue Aug 28 13:23:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 13:23:44 -0400
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
In-Reply-To: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
References: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
Message-ID: <20120828172344.GE19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 01:56:16PM +0200, Valentin Longchamp wrote:
> This is a first attempt to support the km_kirkwood reference design with
> a device tree. This km_kirkwood design is present in many Keymile
> products. It is based on the Marvell Bobcat SOC which integrates a
> Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
> is very similar to the "normal" one, but there are a few differences.
> 
> This initial support is minimal: the kernel can boot with network
> (ge0), serial port and NAND functional.
> 
> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
> Cc: Holger Brunck <holger.brunck at keymile.com>
> ---
>  arch/arm/boot/dts/kirkwood-km_kirkwood.dts |   29 +++++++++++
>  arch/arm/mach-kirkwood/Kconfig             |    7 +++
>  arch/arm/mach-kirkwood/Makefile            |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot       |    1 +
>  arch/arm/mach-kirkwood/board-dt.c          |    4 ++
>  arch/arm/mach-kirkwood/board-km_kirkwood.c |   75 ++++++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/common.h            |    6 ++
>  7 files changed, 123 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-km_kirkwood.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
> 
> diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
> new file mode 100644
> index 0000000..60118d5
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
> @@ -0,0 +1,29 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "Keymile Kirkwood Reference Design";
> +	compatible = "keymile,km_kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x08000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	ocp at f1000000 {
> +		serial at 12000 {
> +			clock-frequency = <200000000>;
> +			status = "ok";
> +		};
> +
> +		nand at 3000000 {
> +			status = "ok";
> +			chip-delay = <25>;
> +		};

Is there a partition layout for this board?

thx,

Jason.


From tomasz.figa at gmail.com  Tue Aug 28 13:27:30 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 19:27:30 +0200
Subject: [PATCH 2/3] gpio: samsung: Add support for Exynos4x12 SoCs
In-Reply-To: <CAJuYYwR3tPhk=DHJVgk1E_MqWrwT+7_YdJOSjrYX=pF7_RFjpw@mail.gmail.com>
References: <4648723.rWnut7F0uJ@amdc1227> <2265472.2J2KAQrYg1@amdc1227>
 <CAJuYYwR3tPhk=DHJVgk1E_MqWrwT+7_YdJOSjrYX=pF7_RFjpw@mail.gmail.com>
Message-ID: <42072476.sfX69hco6r@flatron>

Hi,

Thanks for reviewing the patch.

On Tuesday 28 of August 2012 20:25:34 Thomas Abraham wrote:
> > +       }, {
> > +               .config = &samsung_gpio_cfgs[9],
> > +               .irq_base = IRQ_EINT(24),
> > +               .chip   = {
> > +                       .base   = EXYNOS4_GPX3(0),
> > +                       .ngpio  = EXYNOS4_GPIO_X3_NR,
> > +                       .label  = "GPX3",
> > +                       .to_irq = samsung_gpiolib_to_irq,
> > +               },
> > +       },
> > +};
> 
> I see that GPX0, GPX1, GPX2 and GPX3 bank instances are already part
> of mainline kernel. How is that this is being added here.

It seems like somehow GPXx are added to exynos4210_gpios_2 again and the 
already present part is used for exynos4x12_gpios_2. I guess that it's 
because of adding ".base   = (void *)0xC00" to GPX0, which might be an 
accidental mistake. I will recheck that.

> > +       }, {
> > +               .base   = (void *)0xC00,
> > 
> >                 .config = &samsung_gpio_cfgs[9],
> >                 .irq_base = IRQ_EINT(0),
> >                 .chip   = {
> > 
> > @@ -2370,9 +2619,7 @@ static struct samsung_gpio_chip exynos4_gpios_2[]
> > = {> 
> >                 },
> >         
> >         },
> >  
> >  };
> 
> There are no GPX banks instantiated here for 4x12. What is the reason for
> that?

See previous point. GPXx which have been part of exynos4_gpios_2 become 
part of exynos4210_gpios_2.

> > -#endif
> > 
> > -#ifdef CONFIG_ARCH_EXYNOS4
> > 
> >  static struct samsung_gpio_chip exynos4_gpios_3[] = {
> >  
> >         {
> >         
> >                 .chip   = {
> > 
> > @@ -2727,12 +2974,15 @@ static __init void
> > exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> What is the limitation in adding support for GPVx as well for 4x12 ?

I'm not sure, I might have simply overlooked GPVx. I will recheck that 
tomorrow.

Best regards,
--
Tomasz Figa



From tomasz.figa at gmail.com  Tue Aug 28 13:43:30 2012
From: tomasz.figa at gmail.com (Tomasz Figa)
Date: Tue, 28 Aug 2012 19:43:30 +0200
Subject: [PATCH] ARM: EXYNOS: Add support for secondary CPU bring-up on
 Exynos4412
In-Reply-To: <503CF014.8010503@codeaurora.org>
References: <1422318.SfZfh0XoVo@amdc1227> <503CF014.8010503@codeaurora.org>
Message-ID: <2038010.NUtf96WSJU@flatron>

Hi,

Thanks for reviewing the patch.

On Tuesday 28 of August 2012 09:21:40 Stephen Boyd wrote:
> On 8/28/2012 4:13 AM, Tomasz Figa wrote:
> > diff --git a/arch/arm/mach-exynos/platsmp.c
> > b/arch/arm/mach-exynos/platsmp.c index 36c3984..1114ced 100644
> > --- a/arch/arm/mach-exynos/platsmp.c
> > +++ b/arch/arm/mach-exynos/platsmp.c
> > @@ -34,8 +34,19 @@
> > 
> >  extern void exynos4_secondary_startup(void);
> > 
> > -#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
> > -				S5P_INFORM5 : S5P_VA_SYSRAM)
> > +static inline volatile void *cpu_boot_reg_base(void)
> 
> __iomem?

Sorry, bad habit. I will fix it. 
 
> > +{
> > +	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> > +		return S5P_INFORM5;
> > +	return S5P_VA_SYSRAM;
> > +}
> > +
> > +static inline volatile void *cpu_boot_reg(int cpu)
> 
> __iomem? And why volatile?

Ditto.

> > +{
> > +	if (soc_is_exynos4412())
> > +		return cpu_boot_reg_base() + 4*cpu;
> > +	return cpu_boot_reg_base();
> > +}
> > 
> >  /*
> >  
> >   * control for which core is the next to come out of the secondary
> > 
> > @@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int
> > max_cpus)> 
> >  	 * until it receives a soft interrupt, and then the
> >  	 * secondary CPU branches to this address.
> >  	 */
> > 
> > -	__raw_writel(virt_to_phys(exynos4_secondary_startup),
> > -			CPU1_BOOT_REG);
> > +	for (i = 1; i < max_cpus; ++i) {
> > +		__raw_writel(virt_to_phys(exynos4_secondary_startup),
> > +							cpu_boot_reg(i));
> 
> Do you need to use cpu_logical_map()?

Correct me if I am wrong, but physical to logical CPU mapping will not be 
1:1 only if booted on physical CPU other than 0. I have not seen yet an 
Exynos-based board which does it.

However it might be wiser to use cpu_logical_map() just to be safe indeed. 
I will add it in next version of the patch.

--
Best regards,
Tomasz Figa



From jason at lakedaemon.net  Tue Aug 28 14:10:08 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 14:10:08 -0400
Subject: [PATCH] ARM: Kirkwood: Iomega ix2-200 DT support
In-Reply-To: <2b8d12ce68911cc12c96dcdd60c3345b72d25780.1345472556.git.alanbutty12@gmail.com>
References: <cover.1345472556.git.alanbutty12@gmail.com>
 <2b8d12ce68911cc12c96dcdd60c3345b72d25780.1345472556.git.alanbutty12@gmail.com>
Message-ID: <20120828181008.GG19437@titan.lakedaemon.net>

On Mon, Aug 20, 2012 at 03:29:07PM +0100, Alan M Butler wrote:
> Patch version 5.
> Add support for the Iomega ix2-200.
> Led's and buttons working as of kernel 3.6-rc2
> 
> the 3 lines in the network interface do seem to be required as
> removing either causes the network card to not be able to reach
> the network (at least on my device).
> 
> Product page:
> http://go.iomega.com/en/products/network-storage-desktop/storcenter-network-storage-solution/network-hard-drive-ix2-200-cloud/?partner=4735#tech_specsItem_tab
> 
> Signed-off-by: Alan M Butler <alanbutty12 at gmail.com>

Alan,

Great work!

Applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7-v2

I'll wait for the mv_sata fix and the gpio-keys fix before I send a pull
request to the arm-soc maintainers.

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 28 14:12:47 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 14:12:47 -0400
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120828181247.GH19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 01:35:28AM +0200, Thomas Petazzoni wrote:
> Commit c085d965fb63ac3b4cc7379d45588c0b39e2bdb0 made the ARCH_MVEBU
> platform select PLAT_ORION, which means that now all Orion drivers can
> be enabled on ARCH_MVEBU. This works fine for most drivers, except for
> orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
> not have a mach/hardware.h header (it is considered as a deprecated
> practice).
> 
> It turns out that the <mach/hardware.h> include in orion_nand is not
> necessary: the driver builds perfectly fine without it, so we simply
> get rid of it.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: David Woodhouse <dwmw2 at infradead.org>
> Cc: linux-mtd at lists.infradead.org
> Cc: Artem Bityutskiy <dedekind1 at gmail.com>

Applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7-v2

thx,

Jason.


From jason at lakedaemon.net  Tue Aug 28 14:25:23 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 14:25:23 -0400
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120828182523.GI19437@titan.lakedaemon.net>

On Mon, Aug 20, 2012 at 12:47:28PM +0200, Marek Szyprowski wrote:
> The default 256 KiB coherent pool may be too small for some of the Kirkwood
> devices, so increase it to make sure that devices will be able to allocate
> their buffers with GFP_ATOMIC flag.
> 
> Suggested-by: Josh Coombs <josh.coombs at gmail.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>

Acked-by: Jason Cooper <jason at lakedaemon.net>

I assume this will go through the dma tree.  Or, if they want to Ack it,
I'll take it through mine since I have boards depending on this.

thx,

Jason.

> ---
>  arch/arm/mach-kirkwood/common.c |    7 +++++++
>  1 files changed, 7 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index c4b64ad..d748f50 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -517,6 +517,13 @@ void __init kirkwood_wdt_init(void)
>  void __init kirkwood_init_early(void)
>  {
>  	orion_time_set_base(TIMER_VIRT_BASE);
> +
> +	/*
> +	 * Some Kirkwood devices allocate their coherent buffers from atomic
> +	 * context. Increase size of atomic coherent pool to make sure such
> +	 * the allocations won't fail.
> +	 */
> +	init_dma_coherent_pool_size(SZ_1M);
>  }
>  
>  int kirkwood_tclk;
> -- 
> 1.7.1.569.g6f426
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From troy.kisky at boundarydevices.com  Tue Aug 28 14:27:08 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Tue, 28 Aug 2012 11:27:08 -0700
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled
 console
In-Reply-To: <503CA183.70704@de.bosch.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>
 <503BBA5A.8040609@boundarydevices.com> <503CA183.70704@de.bosch.com>
Message-ID: <503D0D7C.2070509@boundarydevices.com>

On 8/28/2012 3:46 AM, Dirk Behme wrote:
> On 27.08.2012 20:20, Troy Kisky wrote:
>> On 8/27/2012 12:36 AM, Dirk Behme wrote:
>>> From: Xinyu Chen <xinyu.chen at freescale.com>
>>>
>>> Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
>>> as this will cause clock reinit, and output garbage.
>>>
>>> This patch is a port from Freescale's Android kernel.
>>>
>>> Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
>>> Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
>>> CC: Shawn Guo <shawn.guo at linaro.org>
>>> CC: Sascha Hauer <s.hauer at pengutronix.de>
>>> ---
>>>   drivers/tty/serial/imx.c |    2 ++
>>>   1 files changed, 2 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
>>> index 908178f..31ce414 100644
>>> --- a/drivers/tty/serial/imx.c
>>> +++ b/drivers/tty/serial/imx.c
>>> @@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
>>>       int retval;
>>>       unsigned long flags, temp;
>>>   +#ifndef CONFIG_SERIAL_CORE_CONSOLE
>>>       imx_setup_ufcr(sport, 0);
>>> +#endif
>>>         /* disable the DREN bit (Data Ready interrupt enable) before
>>>        * requesting IRQs
>>
>>
>> I'd rather do something like this
>>
>> static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
>> {
>>          unsigned int val;
>>
>>          /* set receiver / transmitter trigger level. */
>>          val = readl(sport->port.membase + UFCR) & UFCR_RFDIV;
>
> Shouldn't it be
>
> ... & (UFCR_RFDIV | UFCR_DCEDTE);
>
> then? My i.MX6 manual has DCEDTE as bit 6, which we don't want to 
> touch, too? We only want to touch TXTL and RXTL?
>

If you do that, you should also change imx_set_termios
to possibly clear the bit

new_ufcr = (old_ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);

to

new_ufcr = (old_ufcr & (~(UFCR_RFDIV | UFCR_DCEDTE))) | UFCR_RFDIV_REG(div);

>>          val |= TXTL << 10 | RXTL;
>>          writel(val, sport->port.membase + UFCR);
>>          return 0;
>> }
>>
>> There is no need for imx_setup_ufcr to change divisor.
>
> Ok
>
> Thanks
>
> Dirk
>



From jkosina at suse.cz  Tue Aug 28 14:28:11 2012
From: jkosina at suse.cz (Jiri Kosina)
Date: Tue, 28 Aug 2012 11:28:11 -0700 (PDT)
Subject: PER_LINUX32, Was: [PATCH v2 21/31] arm64: 32-bit (compat)
 applications support
In-Reply-To: <201208230646.31276.arnd@arndb.de>
References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com>
 <201208151434.05145.arnd@arndb.de>
 <20120816102808.GH31784@mudshark.cambridge.arm.com>
 <201208230646.31276.arnd@arndb.de>
Message-ID: <alpine.LNX.2.00.1208281124520.22447@pobox.suse.cz>

On Thu, 23 Aug 2012, Arnd Bergmann wrote:

> > > > +asmlinkage int compat_sys_personality(compat_ulong_t personality)
> > > > +{
> > > > +	int ret;
> > > > +
> > > > +	if (personality(current->personality) == PER_LINUX32 &&
> > > > +		personality == PER_LINUX)
> > > > +		personality = PER_LINUX32;
> > > > +	ret = sys_personality(personality);
> > > > +	if (ret == PER_LINUX32)
> > > > +		ret = PER_LINUX;
> > > > +	return ret;
> > > > +}
> > > 
> > > Where did you get this from?
> > > 
> > > You should not need compat_sys_personality, just call the native function.
> > 
> > Hmm, but in that case an aarch32 application doing a personality(PER_LINUX)
> > syscall will start seeing the wrong uname.
> 
> Coming back at this topic, I noticed another issue. Jiri Kosina
> has recently posted patches to fix this function in the other architectures

Yeah, there were quite a few broken ones, some of them since the beginning 
of time.

> in order to mask out the other personality bits, which is a correct fix,
> but the above function is odd for other reasons.
> 
> * On MIPS, it is used only for compat tasks, like you have it above.
> * On PA-RISC, it is used for native 32 bit tasks and for compat 32 bit tasks,
>   but not for native 64 bit ones.
> * On IA64, it was used for compat tasks (support for which has since
>   been removed from the kernel), plus all 32 bit tasks would start with
>   PER_LINUX32.
> * On PowerPC, Sparc and s390, it is used for native 64 bit tasks and for
>   compat 32 bit tasks, but not for native 32 bit ones.
> * On Tile, it was never used.
> * On x86_64, it used to be defined (copied from ia64) but not used
>   throughout the git history.
> 
> The semantics of the function are also interesting: The intention seems
> to be that to a compat task, PER_LINUX32 would appear as PER_LINUX.
> The effect is that any process can set PER_LINUX32 but it can never
> be unset except by a 64 bit MIPS or PA-RISC task.
> 
> Since x86_64 does not implement this behavior at all, I suspect that
> there are now lots of things depending on not having it, while all
> the other architectures might also have some (even predating the
> x86_64 port) use cases that depend on depend on not being able to
> observe PER_LINUX32 in 32 bit compat tasks.
> 
> I think we should try to agree on how this is all supposed to work
> and use common code, either put the ppc/sparc/s390 version into
> sys_personality, or remove all of them and just do what x86 and tile
> do, using the regular sys_personality for all tasks.

How about rather introducing common compat_sys_personality() and switching 
the archs that are using it to it? Unifying the behavior (PER_LINUX / 
PER_LINUX32 masquerading) should be painless.

Thanks,

-- 
Jiri Kosina
SUSE Labs


From haojian.zhuang at gmail.com  Tue Aug 28 14:31:34 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 29 Aug 2012 02:31:34 +0800
Subject: [PATCH 1/1] arm: KGDB support for PXA
In-Reply-To: <1346145124-23384-1-git-send-email-den@openvz.org>
References: <1346145124-23384-1-git-send-email-den@openvz.org>
Message-ID: <CAN1soZwXSrpJCCCok=weJwRtWJHXz5zPQ6jB88UTr1HePU84gw@mail.gmail.com>

On Tue, Aug 28, 2012 at 5:12 PM, Denis V. Lunev <den at openvz.org> wrote:
> From: "Denis V. Lunev" <den at openvz.org>
>
> Actually, in order to support KGDB over serial console one must
> implement two callbacks for character polling. Clone them from
> 8250 driver with a bit of tuning.
>
> Signed-off-by: Denis V. Lunev <den at openvz.org>
> Signed-off-by: Marko Katic <dromede at gmail.com>
> CC: Eric Miao <eric.y.miao at gmail.com>
> CC: Russell King <linux at arm.linux.org.uk>
> CC: Haojian Zhuang <haojian.zhuang at gmail.com>
> CC: <linux-arm-kernel at lists.infradead.org>
> ---
> This patch has been originally posted by me to LKML in 2009 and postponed.
> I was contacted last week by Marko who has kindly ported the patch to the
> latest v3.6 kernel and asked to re-send it.
>
> Here it is :)
>
>  drivers/tty/serial/pxa.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 55 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
> index 5847a4b..54cbb02 100644
> --- a/drivers/tty/serial/pxa.c
> +++ b/drivers/tty/serial/pxa.c
> @@ -691,6 +691,57 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
>         clk_disable_unprepare(up->clk);
>  }
>
> +#ifdef CONFIG_CONSOLE_POLL
> +/*
> + * Console polling routines for writing and reading from the uart while
> + * in an interrupt or debug context.
> + */
> +
> +static int serial_pxa_get_poll_char(struct uart_port *port)
> +{
> +       struct uart_pxa_port *up = (struct uart_pxa_port *)port;
> +       unsigned char lsr = serial_in(up, UART_LSR);
> +
> +       while (!(lsr & UART_LSR_DR))
> +               lsr = serial_in(up, UART_LSR);
> +
> +       return serial_in(up, UART_RX);
> +}
> +
> +
> +static void serial_pxa_put_poll_char(struct uart_port *port,
> +                        unsigned char c)
> +{
> +       unsigned int ier;
> +       struct uart_pxa_port *up = (struct uart_pxa_port *)port;
> +
> +       /*
> +        *      First save the IER then disable the interrupts
> +        */
> +       ier = serial_in(up, UART_IER);
> +       serial_out(up, UART_IER, UART_IER_UUE);
> +
> +       wait_for_xmitr(up);
> +       /*
> +        *      Send the character out.
> +        *      If a LF, also do CR...
> +        */
> +       serial_out(up, UART_TX, c);
> +       if (c == 10) {
> +               wait_for_xmitr(up);
> +               serial_out(up, UART_TX, 13);
> +       }
> +
> +       /*
> +        *      Finally, wait for transmitter to become empty
> +        *      and restore the IER
> +        */
> +       wait_for_xmitr(up);
> +       serial_out(up, UART_IER, ier);
> +}
> +
> +#endif /* CONFIG_CONSOLE_POLL */
> +
>  static int __init
>  serial_pxa_console_setup(struct console *co, char *options)
>  {
> @@ -745,6 +796,10 @@ struct uart_ops serial_pxa_pops = {
>         .request_port   = serial_pxa_request_port,
>         .config_port    = serial_pxa_config_port,
>         .verify_port    = serial_pxa_verify_port,
> +#ifdef CONFIG_CONSOLE_POLL
> +       .poll_get_char = serial_pxa_get_poll_char,
> +       .poll_put_char = serial_pxa_put_poll_char,
> +#endif
>  };
>
>  static struct uart_driver serial_pxa_reg = {
> --
> 1.7.7.6
>

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Greg,

Will you merge this patch into tty.git? or I merge it into arch-pxa tree?

Regards
Haojian


From m.szyprowski at samsung.com  Tue Aug 28 14:37:57 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 28 Aug 2012 20:37:57 +0200
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <20120828182523.GI19437@titan.lakedaemon.net>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
 <20120828182523.GI19437@titan.lakedaemon.net>
Message-ID: <503D1005.209@samsung.com>

Hello Jason,

On 8/28/2012 8:25 PM, Jason Cooper wrote:
> On Mon, Aug 20, 2012 at 12:47:28PM +0200, Marek Szyprowski wrote:
>> The default 256 KiB coherent pool may be too small for some of the Kirkwood
>> devices, so increase it to make sure that devices will be able to allocate
>> their buffers with GFP_ATOMIC flag.
>>
>> Suggested-by: Josh Coombs <josh.coombs at gmail.com>
>> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
>
> Acked-by: Jason Cooper <jason at lakedaemon.net>
>
> I assume this will go through the dma tree.  Or, if they want to Ack it,
> I'll take it through mine since I have boards depending on this.

Thanks for the ack, I would like to push it via my dma-mapping tree
together with the patches which add init_dma_coherent_pool_size()
function. I've already added it to fixes-for-3.6 branch.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From jason at lakedaemon.net  Tue Aug 28 14:40:59 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 14:40:59 -0400
Subject: [PATCH 3/3] ARM: Kirkwood: increase atomic coherent pool size
In-Reply-To: <503D1005.209@samsung.com>
References: <1345459648-24263-1-git-send-email-m.szyprowski@samsung.com>
 <1345459648-24263-4-git-send-email-m.szyprowski@samsung.com>
 <20120828182523.GI19437@titan.lakedaemon.net>
 <503D1005.209@samsung.com>
Message-ID: <20120828184059.GJ19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 08:37:57PM +0200, Marek Szyprowski wrote:
> Hello Jason,
> 
> On 8/28/2012 8:25 PM, Jason Cooper wrote:
> >On Mon, Aug 20, 2012 at 12:47:28PM +0200, Marek Szyprowski wrote:
> >>The default 256 KiB coherent pool may be too small for some of the Kirkwood
> >>devices, so increase it to make sure that devices will be able to allocate
> >>their buffers with GFP_ATOMIC flag.
> >>
> >>Suggested-by: Josh Coombs <josh.coombs at gmail.com>
> >>Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> >
> >Acked-by: Jason Cooper <jason at lakedaemon.net>
> >
> >I assume this will go through the dma tree.  Or, if they want to Ack it,
> >I'll take it through mine since I have boards depending on this.
> 
> Thanks for the ack, I would like to push it via my dma-mapping tree
> together with the patches which add init_dma_coherent_pool_size()
> function. I've already added it to fixes-for-3.6 branch.

Great!

thx,

Jason.


From troy.kisky at boundarydevices.com  Tue Aug 28 14:45:24 2012
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Tue, 28 Aug 2012 11:45:24 -0700
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled
 console
In-Reply-To: <503D0D7C.2070509@boundarydevices.com>
References: <1346053012-25686-1-git-send-email-dirk.behme@de.bosch.com>
 <1346053012-25686-3-git-send-email-dirk.behme@de.bosch.com>
 <503BBA5A.8040609@boundarydevices.com> <503CA183.70704@de.bosch.com>
 <503D0D7C.2070509@boundarydevices.com>
Message-ID: <503D11C4.9060508@boundarydevices.com>

On 8/28/2012 11:27 AM, Troy Kisky wrote:
> On 8/28/2012 3:46 AM, Dirk Behme wrote:
>> On 27.08.2012 20:20, Troy Kisky wrote:
>>> On 8/27/2012 12:36 AM, Dirk Behme wrote:
>>>> From: Xinyu Chen <xinyu.chen at freescale.com>
>>>>
>>>> Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
>>>> as this will cause clock reinit, and output garbage.
>>>>
>>>> This patch is a port from Freescale's Android kernel.
>>>>
>>>> Signed-off-by: Xinyu Chen <xinyu.chen at freescale.com>
>>>> Tested-by: Dirk Behme <dirk.behme at de.bosch.com>
>>>> CC: Shawn Guo <shawn.guo at linaro.org>
>>>> CC: Sascha Hauer <s.hauer at pengutronix.de>
>>>> ---
>>>>   drivers/tty/serial/imx.c |    2 ++
>>>>   1 files changed, 2 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
>>>> index 908178f..31ce414 100644
>>>> --- a/drivers/tty/serial/imx.c
>>>> +++ b/drivers/tty/serial/imx.c
>>>> @@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
>>>>       int retval;
>>>>       unsigned long flags, temp;
>>>>   +#ifndef CONFIG_SERIAL_CORE_CONSOLE
>>>>       imx_setup_ufcr(sport, 0);
>>>> +#endif
>>>>         /* disable the DREN bit (Data Ready interrupt enable) before
>>>>        * requesting IRQs
>>>
>>>
>>> I'd rather do something like this
>>>
>>> static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
>>> {
>>>          unsigned int val;
>>>
>>>          /* set receiver / transmitter trigger level. */
>>>          val = readl(sport->port.membase + UFCR) & UFCR_RFDIV;
>>
>> Shouldn't it be
>>
>> ... & (UFCR_RFDIV | UFCR_DCEDTE);
>>
>> then? My i.MX6 manual has DCEDTE as bit 6, which we don't want to 
>> touch, too? We only want to touch TXTL and RXTL?
>>
>
> If you do that, you should also change imx_set_termios
> to possibly clear the bit
>
> new_ufcr = (old_ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
>
> to
>
> new_ufcr = (old_ufcr & (~(UFCR_RFDIV | UFCR_DCEDTE))) | 
> UFCR_RFDIV_REG(div);
>

Sorry, I was looking at the wrong tree. Mainline does not have

sport->use_dcedte. I'm fine either way.






From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:01 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:01 +0200
Subject: arm: move plat-orion platform_data headers to the right place
Message-ID: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>

Hello,

plat-orion/include/plat contains a bunch of headers with platform_data
structure definitions. Those headers should now be in
<linux/platform_data/...>, so this patch series is moving them
here. This impacts the MTD, USB EHCI, sound, MMC, DMA XOR drivers.

Moreover, this series takes this opportunity to move two other
platform_data headers that were in <linux/...>. This impacts the I2C
and Ethernet drivers.

This series has been built tested for orion5x_defconfig,
dove_defconfig, kirkwood_defconfig and mv78x00_defconfig.

Thanks,

Thomas



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:02 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:02 +0200
Subject: [PATCH 1/8] sound: kirkwood: remove useless <plat/audio.h> include
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-2-git-send-email-thomas.petazzoni@free-electrons.com>

kirkwood-openrd.c and kirkwood-t5325.c are not using the platform_data
structure defined in <plat/audio.h>, so there's no point in including
this header file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 sound/soc/kirkwood/kirkwood-openrd.c |    1 -
 sound/soc/kirkwood/kirkwood-t5325.c  |    1 -
 2 files changed, 2 deletions(-)

diff --git a/sound/soc/kirkwood/kirkwood-openrd.c b/sound/soc/kirkwood/kirkwood-openrd.c
index 80bd59c..98a9157 100644
--- a/sound/soc/kirkwood/kirkwood-openrd.c
+++ b/sound/soc/kirkwood/kirkwood-openrd.c
@@ -17,7 +17,6 @@
 #include <linux/slab.h>
 #include <sound/soc.h>
 #include <mach/kirkwood.h>
-#include <plat/audio.h>
 #include <asm/mach-types.h>
 #include "../codecs/cs42l51.h"
 
diff --git a/sound/soc/kirkwood/kirkwood-t5325.c b/sound/soc/kirkwood/kirkwood-t5325.c
index f898363..5213ee9 100644
--- a/sound/soc/kirkwood/kirkwood-t5325.c
+++ b/sound/soc/kirkwood/kirkwood-t5325.c
@@ -16,7 +16,6 @@
 #include <linux/slab.h>
 #include <sound/soc.h>
 #include <mach/kirkwood.h>
-#include <plat/audio.h>
 #include <asm/mach-types.h>
 #include "../codecs/alc5623.h"
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:03 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:03 +0200
Subject: [PATCH 2/8] sound: kirkwood: move <plat/audio.h> to
 <linux/platform_data/kirkwood-audio.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-3-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/common.c              |    2 +-
 arch/arm/plat-orion/include/plat/audio.h     |    7 -------
 include/linux/platform_data/kirkwood-audio.h |    7 +++++++
 sound/soc/kirkwood/kirkwood-i2s.c            |    2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)
 delete mode 100644 arch/arm/plat-orion/include/plat/audio.h
 create mode 100644 include/linux/platform_data/kirkwood-audio.h

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c4b64ad..138ba47 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -18,6 +18,7 @@
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/platform_data/kirkwood-audio.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -26,7 +27,6 @@
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/audio.h>
 #include <plat/cache-feroceon-l2.h>
 #include <plat/mvsdio.h>
 #include <plat/orion_nand.h>
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
deleted file mode 100644
index d6a55bd..0000000
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __PLAT_AUDIO_H
-#define __PLAT_AUDIO_H
-
-struct kirkwood_asoc_platform_data {
-	int burst;
-};
-#endif
diff --git a/include/linux/platform_data/kirkwood-audio.h b/include/linux/platform_data/kirkwood-audio.h
new file mode 100644
index 0000000..a2c25da
--- /dev/null
+++ b/include/linux/platform_data/kirkwood-audio.h
@@ -0,0 +1,7 @@
+#ifndef __KIRKWOOD_AUDIO_PDATA_H
+#define __KIRKWOOD_AUDIO_PDATA_H
+
+struct kirkwood_asoc_platform_data {
+	int burst;
+};
+#endif
diff --git a/sound/soc/kirkwood/kirkwood-i2s.c b/sound/soc/kirkwood/kirkwood-i2s.c
index 7646dd7..c4dd2f1 100644
--- a/sound/soc/kirkwood/kirkwood-i2s.c
+++ b/sound/soc/kirkwood/kirkwood-i2s.c
@@ -21,7 +21,7 @@
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
-#include <plat/audio.h>
+#include <linux/platform_data/kirkwood-audio.h>
 #include "kirkwood.h"
 
 #define DRV_NAME	"kirkwood-i2s"
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:04 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:04 +0200
Subject: [PATCH 3/8] usb: ehci-orion: move <plat/ehci-orion.h> to
 <linux/platform_data/ehci-orion.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-4-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-kirkwood/common.c                    |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |    2 +-
 arch/arm/mach-orion5x/common.c                     |    2 +-
 arch/arm/plat-orion/common.c                       |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 .../linux/platform_data}/ehci-orion.h              |    6 ++----
 7 files changed, 8 insertions(+), 10 deletions(-)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/ehci-orion.h (78%)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 4db5de5..c8e657b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,7 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/ehci-orion.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -28,7 +29,6 @@
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
-#include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
 #include "common.h"
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 138ba47..833fe07 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -19,6 +19,7 @@
 #include <linux/spinlock.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/platform_data/kirkwood-audio.h>
+#include <linux/platform_data/ehci-orion.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -30,7 +31,6 @@
 #include <plat/cache-feroceon-l2.h>
 #include <plat/mvsdio.h>
 #include <plat/orion_nand.h>
-#include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index b4c53b8..7413c35 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -15,12 +15,12 @@
 #include <linux/ata_platform.h>
 #include <linux/clk-provider.h>
 #include <linux/ethtool.h>
+#include <linux/platform_data/ehci-orion.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 9148b22..7228eaa 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -19,6 +19,7 @@
 #include <linux/ata_platform.h>
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
+#include <linux/platform_data/ehci-orion.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -31,7 +32,6 @@
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
 #include <plat/orion_nand.h>
-#include <plat/ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index d245a87..ebcf727 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -18,9 +18,9 @@
 #include <linux/clkdev.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/platform_data/ehci-orion.h>
 #include <net/dsa.h>
 #include <plat/mv_xor.h>
-#include <plat/ehci-orion.h>
 #include <mach/bridge-regs.h>
 
 /* Create a clkdev entry for a given device/clk */
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 8892d36..b34b928 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/mbus.h>
 #include <linux/clk.h>
-#include <plat/ehci-orion.h>
+#include <linux/platform_data/ehci-orion.h>
 
 #define rdl(off)	__raw_readl(hcd->regs + (off))
 #define wrl(off, val)	__raw_writel((val), hcd->regs + (off))
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/include/linux/platform_data/ehci-orion.h
similarity index 78%
rename from arch/arm/plat-orion/include/plat/ehci-orion.h
rename to include/linux/platform_data/ehci-orion.h
index 6fc78e4..f01933d 100644
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ b/include/linux/platform_data/ehci-orion.h
@@ -1,13 +1,11 @@
 /*
- * arch/arm/plat-orion/include/plat/ehci-orion.h
- *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __PLAT_EHCI_ORION_H
-#define __PLAT_EHCI_ORION_H
+#ifndef __EHCI_ORION_PDATA_H
+#define __EHCI_ORION_PDATA_H
 
 #include <linux/mbus.h>
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:06 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:06 +0200
Subject: [PATCH 5/8] dma: mv_xor: move <plat/mv_xor.h> to
 <linux/platform_data/mv_xor.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-6-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/common.c                    |    2 +-
 arch/arm/plat-orion/common.c                       |    2 +-
 drivers/dma/mv_xor.c                               |    2 +-
 .../plat => include/linux/platform_data}/mv_xor.h  |    6 ++----
 4 files changed, 5 insertions(+), 7 deletions(-)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/mv_xor.h (77%)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index e04bd6f..a3d8836 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -21,6 +21,7 @@
 #include <linux/platform_data/kirkwood-audio.h>
 #include <linux/platform_data/ehci-orion.h>
 #include <linux/platform_data/mvsdio.h>
+#include <linux/platform_data/mv_xor.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -34,7 +35,6 @@
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
-#include <plat/mv_xor.h>
 #include "common.h"
 
 /*****************************************************************************
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index ebcf727..88dac08 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/platform_data/ehci-orion.h>
+#include <linux/platform_data/mv_xor.h>
 #include <net/dsa.h>
-#include <plat/mv_xor.h>
 #include <mach/bridge-regs.h>
 
 /* Create a clkdev entry for a given device/clk */
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 0b12e68..ec9c570 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <linux/clk.h>
-#include <plat/mv_xor.h>
+#include <linux/platform_data/mv_xor.h>
 
 #include "dmaengine.h"
 #include "mv_xor.h"
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/include/linux/platform_data/mv_xor.h
similarity index 77%
rename from arch/arm/plat-orion/include/plat/mv_xor.h
rename to include/linux/platform_data/mv_xor.h
index 2ba1f7d..cbfc6e1 100644
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ b/include/linux/platform_data/mv_xor.h
@@ -1,11 +1,9 @@
 /*
- * arch/arm/plat-orion/include/plat/mv_xor.h
- *
  * Marvell XOR platform device data definition file.
  */
 
-#ifndef __PLAT_MV_XOR_H
-#define __PLAT_MV_XOR_H
+#ifndef __MV_XOR_PDATA_H
+#define __MV_XOR_PDATA_H
 
 #include <linux/dmaengine.h>
 #include <linux/mbus.h>
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:05 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:05 +0200
Subject: [PATCH 4/8] mmc: mvsdio: move <plat/mvsdio.h> to
 <linux/platform_data/mvsdio.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-5-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/board-dreamplug.c           |    2 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    2 +-
 arch/arm/mach-kirkwood/common.c                    |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    2 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    2 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    2 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    2 +-
 drivers/mmc/host/mvsdio.c                          |    2 +-
 .../plat => include/linux/platform_data}/mvsdio.h  |    6 ++----
 11 files changed, 12 insertions(+), 14 deletions(-)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/mvsdio.h (77%)

diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index aeb234d..5256c1f 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -25,12 +25,12 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 413e2c8..3d4ba64 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -27,12 +27,12 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 833fe07..e04bd6f 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <linux/mv643xx_i2c.h>
 #include <linux/platform_data/kirkwood-audio.h>
 #include <linux/platform_data/ehci-orion.h>
+#include <linux/platform_data/mvsdio.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -29,7 +30,6 @@
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/mvsdio.h>
 #include <plat/orion_nand.h>
 #include <plat/common.h>
 #include <plat/time.h>
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index d933593..c0a367b 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -14,10 +14,10 @@
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 61d9a55..819cad1 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -16,10 +16,10 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index bdaed38..be2b8fe 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -16,10 +16,10 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 7e99c3f..3b36ae7 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -17,10 +17,10 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index ef92207..78e1541 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -16,11 +16,11 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
+#include <linux/platform_data/mvsdio.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 4ea70e5..006dc69 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -16,10 +16,10 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c
index a61cb5f..0ae0a53 100644
--- a/drivers/mmc/host/mvsdio.c
+++ b/drivers/mmc/host/mvsdio.c
@@ -22,10 +22,10 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/mvsdio.h>
 
 #include <asm/sizes.h>
 #include <asm/unaligned.h>
-#include <plat/mvsdio.h>
 
 #include "mvsdio.h"
 
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/include/linux/platform_data/mvsdio.h
similarity index 77%
rename from arch/arm/plat-orion/include/plat/mvsdio.h
rename to include/linux/platform_data/mvsdio.h
index 1190efe..a44eb86 100644
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ b/include/linux/platform_data/mvsdio.h
@@ -1,13 +1,11 @@
 /*
- * arch/arm/plat-orion/include/plat/mvsdio.h
- *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __MACH_MVSDIO_H
-#define __MACH_MVSDIO_H
+#ifndef __MVSDIO_PDATA_H
+#define __MVSDIO_PDATA_H
 
 #include <linux/mbus.h>
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:07 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:07 +0200
Subject: [PATCH 6/8] mtd: orion_nand: move <plat/orion_nand.h> to
 <linux/platform_data/orion_nand.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-7-git-send-email-thomas.petazzoni@free-electrons.com>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/common.c                    |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |    2 +-
 arch/arm/mach-orion5x/common.c                     |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    2 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    2 +-
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 .../linux/platform_data}/orion_nand.h              |    6 ++----
 7 files changed, 8 insertions(+), 10 deletions(-)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/orion_nand.h (82%)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a3d8836..3e14dfc 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -22,6 +22,7 @@
 #include <linux/platform_data/ehci-orion.h>
 #include <linux/platform_data/mvsdio.h>
 #include <linux/platform_data/mv_xor.h>
+#include <linux/platform_data/orion_nand.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -31,7 +32,6 @@
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/orion_nand.h>
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 7413c35..acc0791 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -16,12 +16,12 @@
 #include <linux/clk-provider.h>
 #include <linux/ethtool.h>
 #include <linux/platform_data/ehci-orion.h>
+#include <linux/platform_data/orion_nand.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 7228eaa..e0db313 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -20,6 +20,7 @@
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/platform_data/ehci-orion.h>
+#include <linux/platform_data/orion_nand.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -31,7 +32,6 @@
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 49a3fd6..be3080e 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -20,11 +20,11 @@
 #include <linux/timer.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/i2c.h>
+#include <linux/platform_data/orion_nand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 1e458ef..82cf706 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -20,11 +20,11 @@
 #include <linux/i2c.h>
 #include <linux/serial_reg.h>
 #include <linux/ata_platform.h>
+#include <linux/platform_data/orion_nand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index fc5a868..eaf8fc7 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -19,10 +19,10 @@
 #include <linux/mtd/partitions.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/platform_data/orion_nand.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <mach/hardware.h>
-#include <plat/orion_nand.h>
 
 static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
diff --git a/arch/arm/plat-orion/include/plat/orion_nand.h b/include/linux/platform_data/orion_nand.h
similarity index 82%
rename from arch/arm/plat-orion/include/plat/orion_nand.h
rename to include/linux/platform_data/orion_nand.h
index 9f3c180..baa1860 100644
--- a/arch/arm/plat-orion/include/plat/orion_nand.h
+++ b/include/linux/platform_data/orion_nand.h
@@ -1,13 +1,11 @@
 /*
- * arch/arm/plat-orion/include/plat/orion_nand.h
- *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __PLAT_ORION_NAND_H
-#define __PLAT_ORION_NAND_H
+#ifndef __ORION_NAND_PDATA_H
+#define __ORION_NAND_PDATA_H
 
 /*
  * Device bus NAND private data
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:08 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:08 +0200
Subject: [PATCH 7/8] i2c: mv643xx: move <linux/mv643xx_i2c.h> to
 <linux/platform_data/mv643xx_i2c.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-8-git-send-email-thomas.petazzoni@free-electrons.com>

Even though this platform_data header was already in <linux/...> and
not in <plat/...>, it makes sense to move it as well to
<linux/platform_data/...>.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-kirkwood/common.c                 |    2 +-
 arch/arm/mach-orion5x/common.c                  |    2 +-
 arch/arm/plat-orion/common.c                    |    2 +-
 drivers/i2c/busses/i2c-mv64xxx.c                |    2 +-
 include/linux/mv643xx.h                         |    2 +-
 include/linux/{ => platform_data}/mv643xx_i2c.h |    4 ++--
 6 files changed, 7 insertions(+), 7 deletions(-)
 rename include/linux/{ => platform_data}/mv643xx_i2c.h (89%)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 3e14dfc..7981012 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -17,11 +17,11 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/platform_data/kirkwood-audio.h>
 #include <linux/platform_data/ehci-orion.h>
 #include <linux/platform_data/mvsdio.h>
 #include <linux/platform_data/mv_xor.h>
+#include <linux/platform_data/mv643xx_i2c.h>
 #include <linux/platform_data/orion_nand.h>
 #include <net/dsa.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index e0db313..43ae1b7 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -15,11 +15,11 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/platform_data/ehci-orion.h>
+#include <linux/platform_data/mv643xx_i2c.h>
 #include <linux/platform_data/orion_nand.h>
 #include <net/dsa.h>
 #include <asm/page.h>
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 88dac08..3aeb28f 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/platform_data/ehci-orion.h>
 #include <linux/platform_data/mv_xor.h>
+#include <linux/platform_data/mv643xx_i2c.h>
 #include <net/dsa.h>
 #include <mach/bridge-regs.h>
 
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 2e9d567..c5e6993 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -15,7 +15,6 @@
 #include <linux/spinlock.h>
 #include <linux/i2c.h>
 #include <linux/interrupt.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/of.h>
@@ -23,6 +22,7 @@
 #include <linux/of_i2c.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/platform_data/mv643xx_i2c.h>
 
 /* Register defines */
 #define	MV64XXX_I2C_REG_SLAVE_ADDR			0x00
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index 69327b7..7e293ce 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -15,7 +15,7 @@
 
 #include <asm/types.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
+#include <linux/platform_data/mv643xx_i2c.h>
 
 /****************************************/
 /* Processor Address Space              */
diff --git a/include/linux/mv643xx_i2c.h b/include/linux/platform_data/mv643xx_i2c.h
similarity index 89%
rename from include/linux/mv643xx_i2c.h
rename to include/linux/platform_data/mv643xx_i2c.h
index 5db5152..a00c687 100644
--- a/include/linux/mv643xx_i2c.h
+++ b/include/linux/platform_data/mv643xx_i2c.h
@@ -5,8 +5,8 @@
  * option) any later version.
  */
 
-#ifndef _MV64XXX_I2C_H_
-#define _MV64XXX_I2C_H_
+#ifndef _MV64XXX_I2C_PDATA_H_
+#define _MV64XXX_I2C_PDATA_H_
 
 #include <linux/types.h>
 
-- 
1.7.9.5



From thomas.petazzoni at free-electrons.com  Tue Aug 28 14:59:09 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 20:59:09 +0200
Subject: [PATCH 8/8] net: mv643xx_eth: move <linux/mv643xx_eth.h> to
 <linux/platform_data/mv643xx_eth.h>
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346180349-25123-9-git-send-email-thomas.petazzoni@free-electrons.com>

Even though this platform_data header was already in <linux/...> and
not in <plat/...>, it makes sense to move it as well to
<linux/platform_data/...>.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 arch/arm/mach-dove/cm-a510.c                    |    2 +-
 arch/arm/mach-dove/dove-db-setup.c              |    2 +-
 arch/arm/mach-kirkwood/board-dnskw.c            |    2 +-
 arch/arm/mach-kirkwood/board-dreamplug.c        |    2 +-
 arch/arm/mach-kirkwood/board-goflexnet.c        |    2 +-
 arch/arm/mach-kirkwood/board-ib62x0.c           |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c         |    2 +-
 arch/arm/mach-kirkwood/board-lsxl.c             |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c            |    2 +-
 arch/arm/mach-kirkwood/d2net_v2-setup.c         |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c     |    2 +-
 arch/arm/mach-kirkwood/dockstar-setup.c         |    2 +-
 arch/arm/mach-kirkwood/guruplug-setup.c         |    2 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c  |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c      |    2 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c       |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c           |    2 +-
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c    |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c        |    2 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c       |    2 +-
 arch/arm/mach-kirkwood/t5325-setup.c            |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c            |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c            |    2 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c       |    2 +-
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c        |    2 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c      |    2 +-
 arch/arm/mach-orion5x/d2net-setup.c             |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c         |    2 +-
 arch/arm/mach-orion5x/dns323-setup.c            |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c         |    2 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c       |    2 +-
 arch/arm/mach-orion5x/ls-chl-setup.c            |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c            |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c            |    2 +-
 arch/arm/mach-orion5x/mss2-setup.c              |    2 +-
 arch/arm/mach-orion5x/mv2120-setup.c            |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c           |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c    |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c     |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c         |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c    |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c  |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c             |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c             |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c            |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c            |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c           |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c        |    2 +-
 arch/arm/plat-orion/common.c                    |    2 +-
 arch/arm/plat-orion/include/plat/common.h       |    2 +-
 drivers/net/ethernet/marvell/mv643xx_eth.c      |    2 +-
 include/linux/mv643xx.h                         |    2 +-
 include/linux/{ => platform_data}/mv643xx_eth.h |    4 ++--
 53 files changed, 54 insertions(+), 54 deletions(-)
 rename include/linux/{ => platform_data}/mv643xx_eth.h (96%)

diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 792b4e2..bb887b8 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index bc2867f..60cac4d 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/timer.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/pci.h>
 #include <linux/spi/spi.h>
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab3506..8103961 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 5256c1f..b5a4922 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
index 3d4ba64..52cde7c 100644
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -20,7 +20,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index cfc47f8..4304a44 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -16,7 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198..108bfc5 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -17,7 +17,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/mtd/partitions.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 83d8975..bf247f0 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -18,7 +18,7 @@
 #include <linux/ata_platform.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/gpio-fan.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 1750e68..304ba38 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -18,7 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 6e1bac9..d8f615c 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -24,7 +24,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index c0a367b..fdfe211 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/platform_data/mvsdio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 819cad1..0f4c340 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/partitions.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/platform_data/mvsdio.h>
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index be2b8fe..4de18b8 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/platform_data/mvsdio.h>
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 6d8364a..faf50bf 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/timer.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index e6bba01..1f307e7 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -25,7 +25,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 31ae8de..a970001 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -24,7 +24,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 3b36ae7..a967c32 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -14,7 +14,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/mvsdio.h>
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index f742a66..f757ab0 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 78e1541..81cdc0c 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -14,7 +14,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/platform_data/mvsdio.h>
 #include <net/dsa.h>
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 006dc69..c80b660 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/partitions.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/platform_data/mvsdio.h>
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index bad738e..d3dda63 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -17,7 +17,7 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 73e2b6c..3cf2266 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca26..0ce35ed 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index ee74ec9..1fce054 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/i2c.h>
 #include <mach/mv78xx0.h>
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 4d6d48b..c2ffbb3 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/i2c.h>
 #include <mach/mv78xx0.h>
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 9a88270..2423f74 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <mach/mv78xx0.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index d75dcfa..9f31bbe 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -16,7 +16,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index be3080e..051bd16 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -18,7 +18,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/timer.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/orion_nand.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index d470864..cdc34e5 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -21,7 +21,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 355e962..cf47458 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -24,7 +24,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 82cf706..bac1f57 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -16,7 +16,7 @@
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/serial_reg.h>
 #include <linux/ata_platform.h>
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 0c9e413..e24835f 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio-fan.h>
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index c1b5d8a..97ba200 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 949eaa8..f73c9d7 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 1c16d04..10eb517 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -15,7 +15,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c87fde4..4c1d86f 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 0180c39..d10fa5a 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 78a6a11..c1e874b 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -14,7 +14,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 2f5dc54..6551cd5 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -14,7 +14,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/i2c.h>
 #include <net/dsa.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 399130f..22d423e 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -16,7 +16,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 92df49c..a8cbd4e 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -14,7 +14,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/ethtool.h>
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 90e571d..33f1fd5 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -16,7 +16,7 @@
 #include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/i2c.h>
 #include <linux/serial_reg.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index b184f68..55b59f0 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -16,7 +16,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index a5c2e64..a4b5be0 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -18,7 +18,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index b420327..28e2fe0 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/sysfs.h>
 #include <linux/platform_device.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/m48t86.h>
 #include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
index 7189827..9e917bd 100644
--- a/arch/arm/mach-orion5x/tsx09-common.c
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -12,7 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/timex.h>
 #include <linux/serial_reg.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 754c12b..f815dac 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -13,7 +13,7 @@
 #include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 45c2125..61dec34 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -13,7 +13,7 @@
 #include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 3aeb28f..4585815 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -16,7 +16,7 @@
 #include <linux/ata_platform.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/platform_data/ehci-orion.h>
 #include <linux/platform_data/mv_xor.h>
 #include <linux/platform_data/mv643xx_i2c.h>
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index e00fdb2..2a57984 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -9,7 +9,7 @@
  */
 
 #ifndef __PLAT_COMMON_H
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 
 struct dsa_platform_data;
 
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 087b9e0..9e5c179 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -52,12 +52,12 @@
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
 #include <linux/phy.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/io.h>
 #include <linux/types.h>
 #include <linux/inet_lro.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/platform_data/mv643xx_eth.h>
 
 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
 static char mv643xx_eth_driver_version[] = "1.4";
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index 7e293ce..21a1a74 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -14,7 +14,7 @@
 #define __ASM_MV643XX_H
 
 #include <asm/types.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/platform_data/mv643xx_eth.h>
 #include <linux/platform_data/mv643xx_i2c.h>
 
 /****************************************/
diff --git a/include/linux/mv643xx_eth.h b/include/linux/platform_data/mv643xx_eth.h
similarity index 96%
rename from include/linux/mv643xx_eth.h
rename to include/linux/platform_data/mv643xx_eth.h
index 51bf8ad..6c6cfe6 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/platform_data/mv643xx_eth.h
@@ -2,8 +2,8 @@
  * MV-643XX ethernet platform device data definition file.
  */
 
-#ifndef __LINUX_MV643XX_ETH_H
-#define __LINUX_MV643XX_ETH_H
+#ifndef __MV643XX_ETH_PDATA_H
+#define __MV643XX_ETH_PDATA_H
 
 #include <linux/mbus.h>
 
-- 
1.7.9.5



From davidb at codeaurora.org  Tue Aug 28 14:59:58 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 28 Aug 2012 11:59:58 -0700
Subject: [PATCH] ARM: Make sure dtc is built before running it
Message-ID: <1346180398-8079-1-git-send-email-davidb@codeaurora.org>

'make dtbs' in a clean tree will try running the dtc before actually
building it.  Make these rules depend upon the scripts to build it.
---
 arch/arm/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00..926d840 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -279,10 +279,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-%.dtb:
+%.dtb: scripts
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
-dtbs:
+dtbs: scripts
 	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
 # We use MRPROPER_FILES and CLEAN_FILES now
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From andrew at lunn.ch  Tue Aug 28 16:11:34 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 28 Aug 2012 22:11:34 +0200
Subject: arm: move plat-orion platform_data headers to the right place
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120828201134.GM9886@lunn.ch>

> This series has been built tested for orion5x_defconfig,
> dove_defconfig, kirkwood_defconfig and mv78x00_defconfig.

Hi Thomas

It would be nice if you could also build test the affected powerpc
platforms.

	Thanks
		Andrew


From sylvester.nawrocki at gmail.com  Tue Aug 28 16:13:46 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Tue, 28 Aug 2012 22:13:46 +0200
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
In-Reply-To: <503C03D7.5050801@samsung.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
 <503C03D7.5050801@samsung.com>
Message-ID: <503D267A.2090406@gmail.com>

On 08/28/2012 01:33 AM, Kukjin Kim wrote:
> On 08/25/12 05:20, Sylwester Nawrocki wrote:
>> This short patch series converts remaining users of the s3c24xx SoC
>> specific gpiolib functions to the gpiolib API and finally removes
>> all s3c2410_* functions from drivers/gpio/gpio-samsung.c.
>>
>> Sylwester Nawrocki (3):
>> ARM: S3C24XX: Convert users of s3c2410_gpio_setpin to gpiolib API
>> ARM: S3C24XX: Remove obsolete GPIO API declarations
>> gpio-samsung: Remove now unused s3c2410_gpio* API
>>
>> arch/arm/mach-s3c24xx/mach-anubis.c | 3 +-
>> arch/arm/mach-s3c24xx/mach-jive.c | 12 ++--
>> arch/arm/mach-s3c24xx/mach-mini2440.c | 4 +-
>> arch/arm/mach-s3c24xx/mach-nexcoder.c | 22 +++---
>> arch/arm/mach-s3c24xx/mach-osiris.c | 7 +-
>> arch/arm/plat-samsung/include/plat/gpio-fns.h | 97 
>> -------------------------
>> drivers/gpio/gpio-samsung.c | 40 ----------
>> 7 files changed, 25 insertions(+), 160 deletions(-)
>>
> 
> Nice cleanup.

Thanks for taking care of this whole series. 

I thought it needs to be done as we go adding more and more new 
code.. For time being it is my last GPIO cleanup patch series ;)

> Accordingly, we need to sort out the 
> 'Documentation/arm/Samsung-S3C24XX/GPIO.txt' later?

Indeed, I let this out for a moment. Let me tidy this up as well, when 
I find some time.


Thanks,
Sylwester

> Linus, this series should be sent to upstream via both trees, samsung 
> and gpio to avoid useless merge conflicts. How do you think?
> 
> Thanks.
> 
> Best regards,
> Kgene.
> -- 
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.


From jason at lakedaemon.net  Tue Aug 28 16:25:34 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 16:25:34 -0400
Subject: arm: move plat-orion platform_data headers to the right place
In-Reply-To: <20120828201134.GM9886@lunn.ch>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120828201134.GM9886@lunn.ch>
Message-ID: <20120828202534.GK19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 10:11:34PM +0200, Andrew Lunn wrote:
> > This series has been built tested for orion5x_defconfig,
> > dove_defconfig, kirkwood_defconfig and mv78x00_defconfig.
> 
> Hi Thomas
> 
> It would be nice if you could also build test the affected powerpc
> platforms.

If my toolchain builds, I'll test it.

thx,

Jason.


From broonie at opensource.wolfsonmicro.com  Tue Aug 28 16:35:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 28 Aug 2012 13:35:04 -0700
Subject: [PATCH] clk: Make the generic clock API available by default
Message-ID: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>

Rather than requiring platforms to select the generic clock API to make
it available make the API available as a user selectable option unless the
user either selects HAVE_CUSTOM_CLK (if they have their own implementation)
or selects COMMON_CLK (if they depend on the generic implementation).

All current architectures that HAVE_CLK but don't use the common clock
framework have selects of HAVE_CUSTOM_CLK added.

This allows drivers to use the generic API on platforms which have no need
for the clock API at platform level.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---

This depends on having one of the patches I've sent adding a generic
clkdev.h added merged - Arnd was expecting to merge one of those, there
was just the lack of clarity about the most practical Kbuild hookup.

 arch/arm/Kconfig            |   12 ++++++++++++
 arch/avr32/Kconfig          |    1 +
 arch/mips/Kconfig           |    4 ++++
 arch/mips/loongson/Kconfig  |    1 +
 arch/mips/loongson1/Kconfig |    1 +
 arch/mips/txx9/Kconfig      |    1 +
 arch/powerpc/Kconfig        |    1 +
 arch/unicore32/Kconfig      |    1 +
 drivers/clk/Kconfig         |   13 ++++++++++---
 9 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d4471d4..2a5633b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,6 +330,7 @@ config ARCH_VEXPRESS
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select HAVE_PATA_PLATFORM
 	select ICST
 	select NO_IOPORT
@@ -343,6 +344,7 @@ config ARCH_AT91
 	bool "Atmel AT91"
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select IRQ_DOMAIN
 	select NEED_MACH_IO_H if PCCARD
@@ -674,6 +676,7 @@ config ARCH_TEGRA
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	select ARCH_HAS_CPUFREQ
@@ -732,6 +735,7 @@ config ARCH_PXA
 config ARCH_MSM
 	bool "Qualcomm MSM"
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select CLKDEV_LOOKUP
@@ -745,6 +749,7 @@ config ARCH_MSM
 config ARCH_SHMOBILE
 	bool "Renesas SH-Mobile / R-Mobile"
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select HAVE_MACH_CLKDEV
 	select HAVE_SMP
@@ -798,6 +803,7 @@ config ARCH_S3C24XX
 	select GENERIC_GPIO
 	select ARCH_HAS_CPUFREQ
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select ARCH_USES_GETTIMEOFFSET
 	select HAVE_S3C2410_I2C if I2C
@@ -816,6 +822,7 @@ config ARCH_S3C64XX
 	select CPU_V6
 	select ARM_VIC
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select HAVE_TCM
 	select CLKDEV_LOOKUP
 	select NO_IOPORT
@@ -838,6 +845,7 @@ config ARCH_S5P64X0
 	select CPU_V6
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -852,6 +860,7 @@ config ARCH_S5PC100
 	bool "Samsung S5PC100"
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select CPU_V7
 	select ARCH_USES_GETTIMEOFFSET
@@ -868,6 +877,7 @@ config ARCH_S5PV210
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 	select ARCH_HAS_CPUFREQ
@@ -886,6 +896,7 @@ config ARCH_EXYNOS
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select CLKDEV_LOOKUP
 	select ARCH_HAS_CPUFREQ
 	select GENERIC_CLOCKEVENTS
@@ -972,6 +983,7 @@ config ARCH_OMAP
 	bool "TI OMAP"
 	depends on MMU
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_HAS_CPUFREQ
 	select CLKSRC_MMIO
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 06e73bf..bfeb9cc 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -4,6 +4,7 @@ config AVR32
 	# that we usually don't need on AVR32.
 	select EXPERT
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select HAVE_OPROFILE
 	select HAVE_KPROBES
 	select HAVE_GENERIC_HARDIRQS
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 641d067..27dfc99 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -84,6 +84,7 @@ config AR7
 	select ARCH_REQUIRE_GPIOLIB
 	select VLYNQ
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	help
 	  Support for the Texas Instruments AR7 System-on-a-Chip
 	  family: TNETD7100, 7200 and 7300.
@@ -96,6 +97,7 @@ config ATH79
 	select CSRC_R4K
 	select DMA_NONCOHERENT
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select IRQ_CPU
 	select MIPS_MACHINE
 	select SYS_HAS_CPU_MIPS32_R2
@@ -133,6 +135,7 @@ config BCM63XX
 	select SWAP_IO_SPACE
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	help
 	 Support for BCM63XX based boards
 
@@ -228,6 +231,7 @@ config MACH_JZ4740
 	select SYS_HAS_EARLY_PRINTK
 	select HAVE_PWM
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select GENERIC_IRQ_CHIP
 
 config LANTIQ
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index 263beb9..ed42be1 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -42,6 +42,7 @@ config LEMOTE_MACH2F
 	select DMA_NONCOHERENT
 	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select HW_HAS_PCI
 	select I8259
 	select IRQ_CPU
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
index a9a14d6..ddaa7d0 100644
--- a/arch/mips/loongson1/Kconfig
+++ b/arch/mips/loongson1/Kconfig
@@ -16,6 +16,7 @@ config LOONGSON1_LS1B
 	select SYS_SUPPORTS_HIGHMEM
 	select SYS_HAS_EARLY_PRINTK
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 
 endchoice
 
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 6d40bc7..04e3cdb 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -21,6 +21,7 @@ config MACH_TXX9
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 
 config TOSHIBA_JMR3927
 	bool "Toshiba JMR-TX3927 board"
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 58088dd..b7a611b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -1013,6 +1013,7 @@ config PPC_CLOCK
 	bool
 	default n
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 
 config PPC_LIB_RHEAP
 	bool
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 5d53ffd..fe30bb1 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -89,6 +89,7 @@ config ARCH_PUV3
 	select CPU_UCV2
 	select GENERIC_CLOCKEVENTS
 	select HAVE_CLK
+	select HAVE_CUSTOM_CLK
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_HAS_CPUFREQ
 
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7f0b5ca..e94fd06 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -9,16 +9,23 @@ config HAVE_CLK_PREPARE
 config HAVE_MACH_CLKDEV
 	bool
 
-config COMMON_CLK
+config HAVE_CUSTOM_CLK
 	bool
+	---help---
+	  Architectures which provide a custom clk API should select
+	  this to disable the common clock API.
+
+config COMMON_CLK
+	bool "Common clock framework"
+	depends on !HAVE_CUSTOM_CLK
 	select HAVE_CLK_PREPARE
 	select CLKDEV_LOOKUP
 	---help---
 	  The common clock framework is a single definition of struct
 	  clk, useful across many platforms, as well as an
 	  implementation of the clock API in include/linux/clk.h.
-	  Architectures utilizing the common struct clk should select
-	  this option.
+	  This provides a generic way for drivers to provide and use
+	  clocks without hard coded relationships in the drivers.
 
 menu "Common Clock Framework"
 	depends on COMMON_CLK
-- 
1.7.10.4



From olof at lixom.net  Tue Aug 28 16:41:53 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 Aug 2012 13:41:53 -0700
Subject: [PATCH RESEND 2/2] msm: io: Change the default static iomappings
 to be shared
In-Reply-To: <1344633496-1873-1-git-send-email-rvaswani@codeaurora.org>
References: <1344633496-1873-1-git-send-email-rvaswani@codeaurora.org>
Message-ID: <CAOesGMgC2OxEs-wGRQku-GeoiaO2Wa_dZ2AuwnKd3Nze4gknqQ@mail.gmail.com>

Hi,

On Fri, Aug 10, 2012 at 2:18 PM, Rohit Vaswani <rvaswani at codeaurora.org> wrote:
> With 3.4 kernel the static iomappings can be shared with the ioremap
> mappings. If ioremap is called with an address for which a static
> mapping already exists, then that mapping should be used instead
> of creating a new one.
> However, the MT_DEVICE_NONSHARED flag prevents this. Hence, get rid
> of this flag. Some targets (7X00) that require the static iomappings
> to be NONSHARED use the MSM_DEVICE_TYPE and MSM_CHIP_DEVICE_TYPE macros.
>
> Signed-off-by: Rohit Vaswani <rvaswani at codeaurora.org>
> ---
>  arch/arm/mach-msm/io.c |   25 +++++++++++++++++--------
>  1 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
> index 2409c0b..5fc2e48 100644
> --- a/arch/arm/mach-msm/io.c
> +++ b/arch/arm/mach-msm/io.c
> @@ -33,23 +33,32 @@
>                 .virtual = (unsigned long) MSM_##name##_BASE, \
>                 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
>                 .length = chip##_##name##_SIZE, \
> -               .type = MT_DEVICE_NONSHARED, \
> +               .type = MT_DEVICE, \
> +        }
> +
> +#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                         \
> +               .virtual = (unsigned long) MSM_##name##_BASE, \
> +               .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
> +               .length = chip##_##name##_SIZE, \
> +               .type = mem_type, \
>          }

The above is partially hidden by lack of context in the diff, but now
you have two defines that do nearly the same thing. It's better to
move to a

#define MSM_CHIP_DEVICE(name, chip)  MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)

for the exising one, instead of duplicating the open coded macros.


-Olof


From olof at lixom.net  Tue Aug 28 16:45:02 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 28 Aug 2012 13:45:02 -0700
Subject: [GIT PULL] msm fixes for v3.6
In-Reply-To: <20120828165532.GA20947@codeaurora.org>
References: <20120828165532.GA20947@codeaurora.org>
Message-ID: <20120828204502.GA24149@quad.lixom.net>

Hi,

On Tue, Aug 28, 2012 at 09:55:32AM -0700, David Brown wrote:
> The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:
> 
>   Linux 3.5 (2012-07-21 13:58:29 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git tags/msm-fix-for3.6
> 
> for you to fetch changes up to e7501de53aa1a551526872f6c95901a00705f942:
> 
>   ARM: msm: Remove call to missing FPGA init on 8660 (2012-08-28 09:39:28 -0700)
> 
> ----------------------------------------------------------------
> Fixes for two problems with MSM:
> 
>   - Mapping issue on 7x00 targets.
>   - Compilation problems with devicetree on 8660.

Thanks for using a tag with a description of the pull request contents,
but it seems like you're missing a bit here -- it has a patch for the dtbs
target, and the handle_irq fix isn't technically breaking compilation,
I believe?

> ----------------------------------------------------------------
> David Brown (1):
>       ARM: msm: Remove call to missing FPGA init on 8660

So, this seems to be breaking builds, seems appropriate as a fix.

> Rohit Vaswani (2):
>       ARM: msm: io: Remove 7x30 iomap region from 7x00
>       ARM: msm: io: Change the default static iomappings to be shared

These two patches lack your Signed-off-by, even though you seem to have been
the committer. Please add it.

But also, it's not clear to me if the second of the two patches actually causes
problems, or if it's just that the mapping won't be reused from the static
range. If it's the latter, then I'd say it's 3.7 material instead. Also see my
separate comment on the posted patch about the format of it.

> Stephen Boyd (2):
>       ARM: msm: Add handle_irq handler for 8660 DT machine

Clearly a bug fix, no problem.

>       ARM: msm: Add msm8660-surf.dts to Makefile.boot

This one looks like 3.7 material.


-Olof


From mturquette at linaro.org  Tue Aug 28 16:52:42 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Tue, 28 Aug 2012 13:52:42 -0700
Subject: [PATCH 1/5] arm: mmp: make private clock definition exclude from
 common clock
In-Reply-To: <CADApbegJwd3jQr+rKd-54AxhZG=On0LSEG5ioX-jnq9S0xY=ug@mail.gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
 <CAN1soZy54UcoQ_qrN2Wh4ZWVMCXj3gpHZas57GqQeT988dnkQQ@mail.gmail.com>
 <CADApbegJwd3jQr+rKd-54AxhZG=On0LSEG5ioX-jnq9S0xY=ug@mail.gmail.com>
Message-ID: <20120828205242.30660.26162@nucleus>

Quoting Chao Xie (2012-08-27 18:40:07)
> On Tue, Aug 28, 2012 at 6:42 AM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
> > On Mon, Aug 27, 2012 at 10:53 AM, Chao Xie <xiechao.mail at gmail.com> wrote:
> >> From: Chao Xie <chao.xie at marvell.com>
> >>
> >> the clock.c is mmp private implementation, make it excluded
> >> from common clock framework
> >>
> >> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
> >> ---
> >>  arch/arm/mach-mmp/Makefile |    5 ++++-
> >>  1 files changed, 4 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
> >> index b786f7e..815c3e7 100644
> >> --- a/arch/arm/mach-mmp/Makefile
> >> +++ b/arch/arm/mach-mmp/Makefile
> >> @@ -2,13 +2,16 @@
> >>  # Makefile for Marvell's PXA168 processors line
> >>  #
> >>
> >> -obj-y                          += common.o clock.o devices.o time.o irq.o
> >> +obj-y                          += common.o devices.o time.o irq.o
> >>
> >>  # SoC support
> >>  obj-$(CONFIG_CPU_PXA168)       += pxa168.o
> >>  obj-$(CONFIG_CPU_PXA910)       += pxa910.o
> >>  obj-$(CONFIG_CPU_MMP2)         += mmp2.o sram.o
> >>
> >> +ifeq ($(CONFIG_COMMON_CLK), )
> >> +obj-y                          += clock.o
> >> +endif
> >
> > Why not to discard all private clock code? Maybe you can use common
> > clk in arch-mmp directly.
> Our dvfs and devfreq are set up based on private clock code. The
> migration of dvfs and devfreq is on going. Checking in common clock
> framework code will help us mirgarate the dvfs and devfreq, but i do
> not want to block the our product development, so I would like to keep
> the private clock code untile we have settle down all the problems.

I am OK with the general approach.  It would be nice to remove all of
the old stuff at the same time to have a better diffstat, but I also
understand needing to balance out the needs of product teams.

Since DVFS is a concern for you I would ask you look in on my
dvfs/reentrancy rfc [1] and provide feedback on whether you think it
will work well for your platform.

Regards,
Mike

[1] http://marc.info/?l=linux-arm-kernel&m=134507427602446&w=2


From sylvester.nawrocki at gmail.com  Tue Aug 28 16:58:48 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Tue, 28 Aug 2012 22:58:48 +0200
Subject: [PATCH] ARM: S3C24XX: Add .get_rate callback for "camif-upll"
 clock
In-Reply-To: <503BFB86.20607@samsung.com>
References: <1346098329-32059-1-git-send-email-sylvester.nawrocki@gmail.com>
 <503BFB86.20607@samsung.com>
Message-ID: <503D3108.1030804@gmail.com>

On 08/28/2012 12:58 AM, Kukjin Kim wrote:
> On 08/27/12 13:12, Sylwester Nawrocki wrote:
>> Add missing get_rate callback for the "camif-upll" clock, so frequency
>> of this clock is properly reported with clk_get_rate().
>>
>> Signed-off-by: Sylwester Nawrocki<sylvester.nawrocki at gmail.com>
>> ---
>> arch/arm/mach-s3c24xx/clock-s3c2440.c | 14 ++++++++++++++
>> 1 files changed, 14 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c 
>> b/arch/arm/mach-s3c24xx/clock-s3c2440.c
>> index cb2883d..749220f 100644
>> --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
>> +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
>> @@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk 
>> *clk, unsigned long rate)
>> return 0;
>> }
>>
>> +static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
>> +{
>> + unsigned long parent_rate = clk_get_rate(clk->parent);
>> + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
>> +
>> + if (!(camdivn& S3C2440_CAMDIVN_CAMCLK_SEL))
>> + return parent_rate;
>> +
>> + camdivn&= S3C2440_CAMDIVN_CAMCLK_MASK;
>> +
>> + return parent_rate / (camdivn + 1) / 2;
> 
> Well, why do we need '/ 2' here?

I simply followed documentation of the camera clock divider register
(CAMDIVN). This is how CAMCLK_SEL and CAMCLK_DIV bit fields are described
there:

CAMDIVN      |  Bit  |       Description
--------------------------------------------------------------------------
CAMCLK_SEL   | [4]   | 0 : Use CAMCLK with UPLL output(CAMCLK=UPLL output)
             |       | 1 : CAMCLK is divided by CAMCLK_DIV value
-------------+-------+----------------------------------------------------
CAMCLK_DIV   | [3:0] | CAMCLK divide factor setting register(0 ? 15).
             |       | Camera clock = UPLL / [(CAMCLK_DIV +1)x2].
             |       | This bit is valid when CAMCLK_SEL=1.

So, camera clock frequency = parent_rate / ((camdivn + 1) * 2).
This is exactly same as 'parent_rate / ( camdivn + 1) / 2'.

To be 1000% sure I compared frequency values reported from clk_get_rate()
in the driver with values measured with an oscilloscope at the CAMCLKOUT
pin. Everything was as expected (UPLL - 48 MHz, CAMCLKOUT - 12 MHz).

Also, it's easy to confirm correctness of this code by inversing equations
found in function s3c2440_camif_upll_setrate(), i.e.

 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
 if (rate != parent_rate) {
 	camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
 	camdivn |= (((parent_rate / rate) / 2) - 1);
 }

 __raw_writel(camdivn, S3C2440_CAMDIVN);

--
Regards,
Sylwester


From haojian.zhuang at gmail.com  Tue Aug 28 17:03:46 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 29 Aug 2012 05:03:46 +0800
Subject: [PATCH 1/5] arm: mmp: make private clock definition exclude from
 common clock
In-Reply-To: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
References: <1346036043-20115-1-git-send-email-xiechao.mail@gmail.com>
Message-ID: <CAN1soZy5-TsuquOAnZSD34aO1HV1EpsgmbQpv_yBP8PZGfskuA@mail.gmail.com>

On Mon, Aug 27, 2012 at 10:53 AM, Chao Xie <xiechao.mail at gmail.com> wrote:
> From: Chao Xie <chao.xie at marvell.com>
>
> the clock.c is mmp private implementation, make it excluded
> from common clock framework
>
> Signed-off-by: Chao Xie <xiechao.mail at gmail.com>
> ---

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>

Acked for this patch series.


From jason at lakedaemon.net  Tue Aug 28 17:15:03 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 17:15:03 -0400
Subject: arm: move plat-orion platform_data headers to the right place
In-Reply-To: <20120828202534.GK19437@titan.lakedaemon.net>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120828201134.GM9886@lunn.ch>
 <20120828202534.GK19437@titan.lakedaemon.net>
Message-ID: <20120828211503.GM19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 04:25:34PM -0400, Jason Cooper wrote:
> On Tue, Aug 28, 2012 at 10:11:34PM +0200, Andrew Lunn wrote:
> > > This series has been built tested for orion5x_defconfig,
> > > dove_defconfig, kirkwood_defconfig and mv78x00_defconfig.
> > 
> > It would be nice if you could also build test the affected powerpc
> > platforms.
> 
> If my toolchain builds, I'll test it.

Ok, built the following defconfigs with a generic powerpc toolchain:

c2k_defconfig
chrp32_defconfig
prpmc2800_defconfig

This exercises I2C_MV64XXX and MV643XX_ETH.  The others don't appear to
be used in powerpc.  But I don't use powerpc so take it for what it's
worth.

thx,

Jason.


From heiko at sntech.de  Tue Aug 28 17:55:43 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Tue, 28 Aug 2012 23:55:43 +0200
Subject: [PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
Message-ID: <201208282355.44268.heiko@sntech.de>

Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
via the device tree. This patch implements dt-support for the
s3c24xx arches.

The controllers contain only 3 cells, as the underlying gpio controller
does not support controlling the drive strength on a gpio level.

Tested with the gpio-keys driver on a s3c2416 based machine.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>
---
changes since v1:
update bindings documentation to address SoC specific issues

 .../devicetree/bindings/gpio/gpio-samsung.txt      |   43 +++++++++++++
 drivers/gpio/gpio-samsung.c                        |   63 ++++++++++++++++++++
 2 files changed, 106 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625..f1e5dfe 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
 		#gpio-cells = <4>;
 		gpio-controller;
 	};
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [flags and pull up/down]
+
+  Values for gpio specifier:
+  - Pin number: depending on the controller a number from 0 up to 15.
+  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
+                  as input, output or a special function
+  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
+                    example S3C2416/S3C2450:
+                            0 - Pull Up/Down Disabled.
+                            1 - Pull Down Enabled.
+                            2 - Pull Up Enabled.
+          Bit 16 (0x00010000) - Input is active low.
+  Consult the user manual for the correct values of Mux and Pull Up/Down.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+	gpa: gpio-controller at 56000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "samsung,s3c24xx-gpio";
+		reg = <0x56000000 0x10>;
+		#gpio-cells = <3>;
+		gpio-controller;
+	};
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc..54f6663 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
 		s3c_gpiolib_track(chip);
 }
 
+#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+			const struct of_phandle_args *gpiospec, u32 *flags)
+{
+	unsigned int pin;
+
+	if (WARN_ON(gc->of_gpio_n_cells < 3))
+		return -EINVAL;
+
+	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+		return -EINVAL;
+
+	if (gpiospec->args[0] > gc->ngpio)
+		return -EINVAL;
+
+	pin = gc->base + gpiospec->args[0];
+
+	if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
+		pr_warn("gpio_xlate: failed to set pin function\n");
+	if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
+		pr_warn("gpio_xlate: failed to set pin pull up/down\n");
+
+	if (flags)
+		*flags = gpiospec->args[2] >> 16;
+
+	return gpiospec->args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+	{ .compatible = "samsung,s3c24xx-gpio", },
+	{}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+						 u64 base, u64 offset)
+{
+	struct gpio_chip *gc =  &chip->chip;
+	u64 address;
+
+	if (!of_have_populated_dt())
+		return;
+
+	address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
+	gc->of_node = of_find_matching_node_by_address(NULL,
+			s3c24xx_gpio_dt_match, address);
+	if (!gc->of_node) {
+		pr_info("gpio: device tree node not found for gpio controller"
+			" with base address %08llx\n", address);
+		return;
+	}
+	gc->of_gpio_n_cells = 3;
+	gc->of_xlate = s3c24xx_gpio_xlate;
+}
+#elif defined(CONFIG_PLAT_S3C24XX)
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+						 u64 base, u64 offset)
+{
+	return;
+}
+#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
+
 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
 					     int nr_chips, void __iomem *base)
 {
@@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
 			gc->direction_output = samsung_gpiolib_2bit_output;
 
 		samsung_gpiolib_add(chip);
+
+		s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
 	}
 }
 
-- 
1.7.2.3



From thomas.petazzoni at free-electrons.com  Tue Aug 28 17:57:29 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 23:57:29 +0200
Subject: arm: move plat-orion platform_data headers to the right place
In-Reply-To: <20120828211503.GM19437@titan.lakedaemon.net>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <20120828201134.GM9886@lunn.ch>
 <20120828202534.GK19437@titan.lakedaemon.net>
 <20120828211503.GM19437@titan.lakedaemon.net>
Message-ID: <20120828235729.0f4e792f@skate>

Le Tue, 28 Aug 2012 17:15:03 -0400,
Jason Cooper <jason at lakedaemon.net> a ?crit :

> Ok, built the following defconfigs with a generic powerpc toolchain:
> 
> c2k_defconfig
> chrp32_defconfig
> prpmc2800_defconfig

I also built the following PowerPW defconfigs, which had either the I2C
or the Ethernet Marvell drivers enabled, or both:

 c2k
 chroma
 chrp32
 mpc7448_hpc2
 pasemi
 ppc6xx
 prpmc2800

All of them built, except mpc7448_hpc2, but the build failure was
completely unrelated.

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From m.szyprowski at samsung.com  Tue Aug 28 17:58:48 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 28 Aug 2012 23:58:48 +0200
Subject: [PATCH 4/4] ARM: dma-mapping: Skip cache maint for invalid page
In-Reply-To: <1346154232-13299-4-git-send-email-hdoyu@nvidia.com>
References: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com>
 <1346154232-13299-4-git-send-email-hdoyu@nvidia.com>
Message-ID: <503D3F18.7070507@samsung.com>

Hello,

On 8/28/2012 1:43 PM, Hiroshi Doyu wrote:

> Skip cache maint for invalid page but warn it.
>
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>   arch/arm/mm/dma-mapping.c |    9 +++++++++
>   1 files changed, 9 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 2621282..0368702 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1589,6 +1589,9 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
>   	if (!iova)
>   		return;
>
> +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> +		return;
> +
>   	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
>   		__dma_page_dev_to_cpu(page, offset, size, dir);
>
> @@ -1607,6 +1610,9 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
>   	if (!iova)
>   		return;
>
> +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> +		return;
> +
>   	__dma_page_dev_to_cpu(page, offset, size, dir);
>   }
>
> @@ -1621,6 +1627,9 @@ static void arm_iommu_sync_single_for_device(struct device *dev,
>   	if (!iova)
>   		return;
>
> +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> +		return;
> +
>   	__dma_page_cpu_to_dev(page, offset, size, dir);
>   }

I really wonder what has happened in your system that you require
such paranoid checks. All of the above functions are called on the
scatter-list which has been first passed to dma_map_sg(). IMHO it
makes much more sense to add a pfn_valid() check in dma_map_sg()
and return error if the provided scatter list is not valid instead
of these WARN_ONs.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From swarren at wwwdotorg.org  Tue Aug 28 18:39:40 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 15:39:40 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly
 for non-OOB
In-Reply-To: <503CF5B3.8040201@broadcom.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com> <503BD345.6030501@wwwdotorg.org>
 <1346152413.3516.211.camel@tegra-chromium-2> <503CF5B3.8040201@broadcom.com>
Message-ID: <503D48AC.5040509@wwwdotorg.org>

On 08/28/2012 09:45 AM, Franky Lin wrote:
> On 08/28/2012 04:13 AM, Wei Ni wrote:
>> On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
>>> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
>>>> On 08/27/2012 12:25 PM, Wei Ni wrote:
>>>>> In case of inband interrupts, if we handle the interrupt in dpc
>>>>> thread,
>>>>> two level of thread switching takes place to process wifi interrupts.
>>>>> One in SDHCI driver and the other in Wifi driver. This may cause the
>>>>> system
>>>>> instability.
...
>>>> Not sure if I can follow this explanation. The isr is called with host
>>>> claimed (by sdio_irq_thread) and all it does is at a linked list member
>>>> and signal the dpc thread. After doing this the host is released.
>>>
>>> Is the issue something like the ISR handler or first level of threading
>>> does:
>>>
>>> * Trigger DPC
>>> * Re-enable interrupt
>>>
>>> So that the interrupt then fires again before the triggered DPC can run
>>> to handle/clear it, thus causing an interrupt storm?
>>>
>>> Whereas handling the interrupt directly prevents this race condition?
>>
>> Above is my understanding.
> 
> I understand the issue here and totally agree that we should treat
> in-band and out-band interrupts differently. But my concern is that the
> behavior of releasing the host before calling brcmf_sdbrcm_isr and grab
> it after is likely error prone. Also we are restructuring the dpc
> routine internally and it's almost done. I will find a better solution
> for in-band interrupt and get it the queue as well. So I suggest
> dropping this patch.

Franky, do you know which kernel release the DPC restructuring will make
it into? I ask because I can't apply the rest of the patches in this
series without first resolving the stability issues with the Broadcom
WiFi enabled, since that'd de-stabilize the Tegra platform
significantly, and I'd like to plan when we can apply these patches to
Tegra. Thanks!


From gregory.clement at free-electrons.com  Tue Aug 28 18:53:01 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 Aug 2012 00:53:01 +0200
Subject: [PATCH 0/1] clk: add DT fixed-factor-clock binding support
Message-ID: <1346194382-11405-1-git-send-email-gregory.clement@free-electrons.com>

Hi,

During the port of the clock common framework for the armada 370/XP, I
need to get "fixed-factor-clock" using the device tree. For this need
I add support DT for "fixed-factor-clock" in the same way that the
existing support for "fixed-rate-clock". It turned out that finally I
didn't need it anymore, but as the code was written and tested, here
it is.

Gregory Clement



From gregory.clement at free-electrons.com  Tue Aug 28 18:53:02 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 29 Aug 2012 00:53:02 +0200
Subject: [PATCH] clk: add DT fixed-factor-clock binding support
In-Reply-To: <1346194382-11405-1-git-send-email-gregory.clement@free-electrons.com>
References: <1346194382-11405-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1346194382-11405-2-git-send-email-gregory.clement@free-electrons.com>

Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mike Turquette <mturquette at ti.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
---
 .../bindings/clock/fixed-factor-clock.txt          |   24 ++++++++++++++
 drivers/clk/clk-fixed-factor.c                     |   34 ++++++++++++++++++++
 include/linux/clk-provider.h                       |    2 ++
 3 files changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/fixed-factor-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
new file mode 100644
index 0000000..7ed236f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
@@ -0,0 +1,24 @@
+Binding for simple fixed factor rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- div: fixed divider.
+- mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+	clock {
+		compatible = "fixed-factor-clock";
+		clocks = <&parentclk>;
+		#clock-cells = <0>;
+		div = <2>;
+		mult = <1>;
+	};
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index a489985..8fdf5e9 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -11,6 +11,7 @@
 #include <linux/clk-provider.h>
 #include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/of.h>
 
 /*
  * DOC: basic fixed multiplier and divider clock that cannot gate
@@ -93,3 +94,36 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 
 	return clk;
 }
+#ifdef CONFIG_OF
+/**
+ * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
+ */
+void __init of_fixed_factor_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	u32 div, mult;
+
+	if (of_property_read_u32(node, "div", &div)) {
+		pr_err("%s Fixed factor clock <%s> must have a div property\n",
+			__func__, node->name);
+		return;
+	}
+
+	if (of_property_read_u32(node, "mult", &mult)) {
+		pr_err("%s Fixed factor clock <%s> must have a mult property\n",
+			__func__, node->name);
+		return;
+	}
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+					mult, div);
+	if (clk)
+		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup);
+#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fa..796e68b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -314,6 +314,8 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
 
+void of_fixed_factor_clk_setup(struct device_node *node);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
-- 
1.7.9.5



From swarren at wwwdotorg.org  Tue Aug 28 18:54:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 15:54:00 -0700
Subject: [PATCH v3 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346145005-17961-2-git-send-email-b29396@freescale.com>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
 <1346145005-17961-2-git-send-email-b29396@freescale.com>
Message-ID: <503D4C08.8040605@wwwdotorg.org>

On 08/28/2012 02:09 AM, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Add regmap based syscon driver.
> This is usually used for access misc bits in registers which does not belong
> to a specific module, for example, IMX IOMUXC GPR and ANATOP.
> With this driver, client can use generic regmap API to access registers
> which are registered into syscon.

> diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt

> +* System Controller Registers R/W driver

I think the binding document could use some information about what a
"syscon" actually is, especially since the compatible value is something
generic like "syscon" rather than something with a vendor-specific
prefix. How about:

A system controller node represents a register region containing a set
of miscellaneous registers. The registers are not cohesive enough to
represent as any specific type of device. The typical use-case is for
some other node's driver, or platform-specific code, to acquire a
reference to the syscon node (e.g. by phandle, node path, or search
using a specific compatible value), interrogate the node (or associated
OS driver) to determine the location of the registers, and access the
registers directly.

> +Required properties:
> +- compatible: Should contain "syscon".
> +- reg: the register range can be access from syscon
> +
> +Examples:
> +gpr: iomuxc-gpr at 020e0000 {
> +	compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
> +	reg = <0x020e0000 0x38>;
> +};

> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig

> +config MFD_SYSCON
> +        bool "System Controller Register R/W Based on Regmap"
> +        select REGMAP_MMIO
> +        help
> +          Select this option to enable accessing system control registers
> +	  via regmap.

I think the indentation is off there.

> +static int __devinit syscon_probe(struct platform_device *pdev)
...
> +	regcache_cache_only(syscon->regmap, false);

Isn't that the default?

Aside from that, I don't have any particular comments on this series, so
please consider it,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From frankyl at broadcom.com  Tue Aug 28 19:01:45 2012
From: frankyl at broadcom.com (Franky Lin)
Date: Tue, 28 Aug 2012 16:01:45 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR
 directly for non-OOB
In-Reply-To: <503D48AC.5040509@wwwdotorg.org>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com> <503BD345.6030501@wwwdotorg.org>
 <1346152413.3516.211.camel@tegra-chromium-2>
 <503CF5B3.8040201@broadcom.com> <503D48AC.5040509@wwwdotorg.org>
Message-ID: <503D4DD9.2060808@broadcom.com>

On 08/28/2012 03:39 PM, Stephen Warren wrote:
> On 08/28/2012 09:45 AM, Franky Lin wrote:
>> On 08/28/2012 04:13 AM, Wei Ni wrote:
>>> On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
>>>> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
>>>>> On 08/27/2012 12:25 PM, Wei Ni wrote:
>>>>>> In case of inband interrupts, if we handle the interrupt in dpc
>>>>>> thread,
>>>>>> two level of thread switching takes place to process wifi interrupts.
>>>>>> One in SDHCI driver and the other in Wifi driver. This may cause the
>>>>>> system
>>>>>> instability.
> ...
>>>>> Not sure if I can follow this explanation. The isr is called with host
>>>>> claimed (by sdio_irq_thread) and all it does is at a linked list member
>>>>> and signal the dpc thread. After doing this the host is released.
>>>>
>>>> Is the issue something like the ISR handler or first level of threading
>>>> does:
>>>>
>>>> * Trigger DPC
>>>> * Re-enable interrupt
>>>>
>>>> So that the interrupt then fires again before the triggered DPC can run
>>>> to handle/clear it, thus causing an interrupt storm?
>>>>
>>>> Whereas handling the interrupt directly prevents this race condition?
>>>
>>> Above is my understanding.
>>
>> I understand the issue here and totally agree that we should treat
>> in-band and out-band interrupts differently. But my concern is that the
>> behavior of releasing the host before calling brcmf_sdbrcm_isr and grab
>> it after is likely error prone. Also we are restructuring the dpc
>> routine internally and it's almost done. I will find a better solution
>> for in-band interrupt and get it the queue as well. So I suggest
>> dropping this patch.
>
> Franky, do you know which kernel release the DPC restructuring will make
> it into? I ask because I can't apply the rest of the patches in this
> series without first resolving the stability issues with the Broadcom
> WiFi enabled, since that'd de-stabilize the Tegra platform
> significantly, and I'd like to plan when we can apply these patches to
> Tegra. Thanks!
>

Hi Stephen,

Since we submit patches through linux-wireless tree, you may only be 
able to pick it up at 3.7-rc1. It's quite a big change so I don't think 
it will qualify as a bug fix to get into 3.6-rcX.

Regards,
Franky



From swarren at wwwdotorg.org  Tue Aug 28 19:04:31 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 16:04:31 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR directly
 for non-OOB
In-Reply-To: <503D4DD9.2060808@broadcom.com>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com> <503BD345.6030501@wwwdotorg.org>
 <1346152413.3516.211.camel@tegra-chromium-2> <503CF5B3.8040201@broadcom.com>
 <503D48AC.5040509@wwwdotorg.org> <503D4DD9.2060808@broadcom.com>
Message-ID: <503D4E7F.9010205@wwwdotorg.org>

On 08/28/2012 04:01 PM, Franky Lin wrote:
> On 08/28/2012 03:39 PM, Stephen Warren wrote:
>> On 08/28/2012 09:45 AM, Franky Lin wrote:
>>> On 08/28/2012 04:13 AM, Wei Ni wrote:
>>>> On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
>>>>> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
>>>>>> On 08/27/2012 12:25 PM, Wei Ni wrote:
>>>>>>> In case of inband interrupts, if we handle the interrupt in dpc
>>>>>>> thread,
>>>>>>> two level of thread switching takes place to process wifi
>>>>>>> interrupts.
>>>>>>> One in SDHCI driver and the other in Wifi driver. This may cause the
>>>>>>> system
>>>>>>> instability.
>> ...
>>>>>> Not sure if I can follow this explanation. The isr is called with
>>>>>> host
>>>>>> claimed (by sdio_irq_thread) and all it does is at a linked list
>>>>>> member
>>>>>> and signal the dpc thread. After doing this the host is released.
>>>>>
>>>>> Is the issue something like the ISR handler or first level of
>>>>> threading
>>>>> does:
>>>>>
>>>>> * Trigger DPC
>>>>> * Re-enable interrupt
>>>>>
>>>>> So that the interrupt then fires again before the triggered DPC can
>>>>> run
>>>>> to handle/clear it, thus causing an interrupt storm?
>>>>>
>>>>> Whereas handling the interrupt directly prevents this race condition?
>>>>
>>>> Above is my understanding.
>>>
>>> I understand the issue here and totally agree that we should treat
>>> in-band and out-band interrupts differently. But my concern is that the
>>> behavior of releasing the host before calling brcmf_sdbrcm_isr and grab
>>> it after is likely error prone. Also we are restructuring the dpc
>>> routine internally and it's almost done. I will find a better solution
>>> for in-band interrupt and get it the queue as well. So I suggest
>>> dropping this patch.
>>
>> Franky, do you know which kernel release the DPC restructuring will make
>> it into? I ask because I can't apply the rest of the patches in this
>> series without first resolving the stability issues with the Broadcom
>> WiFi enabled, since that'd de-stabilize the Tegra platform
>> significantly, and I'd like to plan when we can apply these patches to
>> Tegra. Thanks!
>>
> 
> Hi Stephen,
> 
> Since we submit patches through linux-wireless tree, you may only be
> able to pick it up at 3.7-rc1. It's quite a big change so I don't think
> it will qualify as a bug fix to get into 3.6-rcX.

That's as quick as I expected it to show up, so that's great. I don't
suppose you could mail Wei and myself once the patch gets into the
linux-wireless tree, so we can test it out on Tegra. If the patch could
possibly go into a topic branch in the wireless tree so it can be merged
into the Tegra tree before this series, that would be awesome. Thanks.


From swarren at wwwdotorg.org  Tue Aug 28 19:06:11 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 28 Aug 2012 16:06:11 -0700
Subject: [PATCH 2/2] ARM: dt: tegra: harmony: add regulators
In-Reply-To: <503CDDEB.1050201@nvidia.com>
References: <1346137800-7448-1-git-send-email-swarren@wwwdotorg.org>
 <1346137800-7448-2-git-send-email-swarren@wwwdotorg.org>
 <503CDDEB.1050201@nvidia.com>
Message-ID: <503D4EE3.1000603@wwwdotorg.org>

On 08/28/2012 08:04 AM, Laxman Dewangan wrote:
> On Tuesday 28 August 2012 12:40 PM, Stephen Warren wrote:
>>   #include "board.h"
>> -#include "board-harmony.h"
>>
>>   #ifdef CONFIG_TEGRA_PCI
>>
>>   int __init harmony_pcie_init(void)
>>   {
>> -       struct regulator *regulator = NULL;
>> +       struct regulator *regulator_1v5, *regulator_pex;
>>          int err;
>>
>> -       err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
>> -       if (err)
>> -               return err;
>> +       regulator_1v5 = regulator_get(NULL, "vdd_1v5");
>> +       if (IS_ERR_OR_NULL(regulator_1v5)) {
>> +               err = PTR_ERR(regulator_1v5);
>> +               goto err_reg;
>> +       }
> 
> You need to return in case of err otherwise it will cause the crash in
> regulator_disable() with NULL argument.

OK, I think I've fixed this and the crash, and re-pushed my personal
linux-next_common. I don't suppose you could retest this. Thanks very much!


From kgene.kim at samsung.com  Tue Aug 28 19:09:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:09:37 -0700
Subject: [PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208282355.44268.heiko@sntech.de>
References: <201208282355.44268.heiko@sntech.de>
Message-ID: <503D4FB1.1020206@samsung.com>

On 08/28/12 14:55, Heiko St?bner wrote:
> Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
> via the device tree. This patch implements dt-support for the
> s3c24xx arches.
>
> The controllers contain only 3 cells, as the underlying gpio controller
> does not support controlling the drive strength on a gpio level.
>
> Tested with the gpio-keys driver on a s3c2416 based machine.
>
> Signed-off-by: Heiko Stuebner<heiko at sntech.de>
> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>

Yeah, looks good to me...

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

BTW, I'm not sure when we can support device tree for S3C24XX :-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> ---
> changes since v1:
> update bindings documentation to address SoC specific issues
>
>   .../devicetree/bindings/gpio/gpio-samsung.txt      |   43 +++++++++++++
>   drivers/gpio/gpio-samsung.c                        |   63 ++++++++++++++++++++
>   2 files changed, 106 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> index 5375625..f1e5dfe 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> @@ -39,3 +39,46 @@ Example:
>   		#gpio-cells =<4>;
>   		gpio-controller;
>   	};
> +
> +
> +Samsung S3C24XX GPIO Controller
> +
> +Required properties:
> +- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
> +
> +- reg: Physical base address of the controller and length of memory mapped
> +  region.
> +
> +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
> +  should be the following with values derived from the SoC user manual.
> +<[phandle of the gpio controller node]
> +      [pin number within the gpio controller]
> +      [mux function]
> +      [flags and pull up/down]
> +
> +  Values for gpio specifier:
> +  - Pin number: depending on the controller a number from 0 up to 15.
> +  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
> +                  as input, output or a special function
> +  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
> +                    example S3C2416/S3C2450:
> +                            0 - Pull Up/Down Disabled.
> +                            1 - Pull Down Enabled.
> +                            2 - Pull Up Enabled.
> +          Bit 16 (0x00010000) - Input is active low.
> +  Consult the user manual for the correct values of Mux and Pull Up/Down.
> +
> +- gpio-controller: Specifies that the node is a gpio controller.
> +- #address-cells: should be 1.
> +- #size-cells: should be 1.
> +
> +Example:
> +
> +	gpa: gpio-controller at 56000000 {
> +		#address-cells =<1>;
> +		#size-cells =<1>;
> +		compatible = "samsung,s3c24xx-gpio";
> +		reg =<0x56000000 0x10>;
> +		#gpio-cells =<3>;
> +		gpio-controller;
> +	};
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index ba126cc..54f6663 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
>   		s3c_gpiolib_track(chip);
>   }
>
> +#if defined(CONFIG_PLAT_S3C24XX)&&  defined(CONFIG_OF)
> +static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
> +			const struct of_phandle_args *gpiospec, u32 *flags)
> +{
> +	unsigned int pin;
> +
> +	if (WARN_ON(gc->of_gpio_n_cells<  3))
> +		return -EINVAL;
> +
> +	if (WARN_ON(gpiospec->args_count<  gc->of_gpio_n_cells))
> +		return -EINVAL;
> +
> +	if (gpiospec->args[0]>  gc->ngpio)
> +		return -EINVAL;
> +
> +	pin = gc->base + gpiospec->args[0];
> +
> +	if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
> +		pr_warn("gpio_xlate: failed to set pin function\n");
> +	if (s3c_gpio_setpull(pin, gpiospec->args[2]&  0xffff))
> +		pr_warn("gpio_xlate: failed to set pin pull up/down\n");
> +
> +	if (flags)
> +		*flags = gpiospec->args[2]>>  16;
> +
> +	return gpiospec->args[0];
> +}
> +
> +static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
> +	{ .compatible = "samsung,s3c24xx-gpio", },
> +	{}
> +};
> +
> +static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> +						 u64 base, u64 offset)
> +{
> +	struct gpio_chip *gc =&chip->chip;
> +	u64 address;
> +
> +	if (!of_have_populated_dt())
> +		return;
> +
> +	address = chip->base ? base + ((u32)chip->base&  0xfff) : base + offset;
> +	gc->of_node = of_find_matching_node_by_address(NULL,
> +			s3c24xx_gpio_dt_match, address);
> +	if (!gc->of_node) {
> +		pr_info("gpio: device tree node not found for gpio controller"
> +			" with base address %08llx\n", address);
> +		return;
> +	}
> +	gc->of_gpio_n_cells = 3;
> +	gc->of_xlate = s3c24xx_gpio_xlate;
> +}
> +#elif defined(CONFIG_PLAT_S3C24XX)
> +static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
> +						 u64 base, u64 offset)
> +{
> +	return;
> +}
> +#endif /* defined(CONFIG_PLAT_S3C24XX)&&  defined(CONFIG_OF) */
> +
>   static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
>   					     int nr_chips, void __iomem *base)
>   {
> @@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
>   			gc->direction_output = samsung_gpiolib_2bit_output;
>
>   		samsung_gpiolib_add(chip);
> +
> +		s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
>   	}
>   }
>


From aaro.koskinen at iki.fi  Tue Aug 28 19:09:17 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed, 29 Aug 2012 02:09:17 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <CAMQu2gwMk68_BNc4O0M52OACUVLLGzRCQe+5mGH_40DrwAQ4KA@mail.gmail.com>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
 <20120828122042.GC783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwMk68_BNc4O0M52OACUVLLGzRCQe+5mGH_40DrwAQ4KA@mail.gmail.com>
Message-ID: <20120828230917.GD783@harshnoise.musicnaut.iki.fi>

Hi,

On Tue, Aug 28, 2012 at 07:19:38AM -0700, Shilimkar, Santosh wrote:
> Or the PPA has resized the secure area of 16K. As you have seen the issue
> on one OMAP3 device, it makes sense to takeout that 16K from the public
> SRAM map.
> 
> Can you send the patch with fixed base address fir PUB SRAM ?

Maybe I'm missing something, but I tried the following and now something
else got broken:

	save_secure_sram() returns 0000ff02

(and it hangs there).

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181c..242ea5b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -38,7 +38,7 @@
 
 #define OMAP1_SRAM_PA		0x20000000
 #define OMAP2_SRAM_PUB_PA	(OMAP2_SRAM_PA + 0xf800)
-#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0xc000)
 #ifdef CONFIG_OMAP4_ERRATA_I688
 #define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
 #else
@@ -112,9 +112,9 @@ static void __init omap_detect_sram(void)
 				omap_sram_start = OMAP3_SRAM_PUB_PA;
 				if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 				    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
-					omap_sram_size = 0x7000; /* 28K */
+					omap_sram_size = 0x3000; /* 12K */
 				} else {
-					omap_sram_size = 0x8000; /* 32K */
+					omap_sram_size = SZ_16K; /* 16K */
 				}
 			} else if (cpu_is_omap44xx()) {
 				omap_sram_start = OMAP4_SRAM_PUB_PA;


From frankyl at broadcom.com  Tue Aug 28 19:10:07 2012
From: frankyl at broadcom.com (Franky Lin)
Date: Tue, 28 Aug 2012 16:10:07 -0700
Subject: [PATCH 2/6] brcmfmac: Handling the interrupt in ISR
 directly for non-OOB
In-Reply-To: <503D4E7F.9010205@wwwdotorg.org>
References: <1346063114-30361-1-git-send-email-wni@nvidia.com>
 <1346063114-30361-3-git-send-email-wni@nvidia.com>
 <503B9F31.5050502@broadcom.com> <503BD345.6030501@wwwdotorg.org>
 <1346152413.3516.211.camel@tegra-chromium-2>
 <503CF5B3.8040201@broadcom.com> <503D48AC.5040509@wwwdotorg.org>
 <503D4DD9.2060808@broadcom.com> <503D4E7F.9010205@wwwdotorg.org>
Message-ID: <503D4FCF.7030109@broadcom.com>

On 08/28/2012 04:04 PM, Stephen Warren wrote:
> On 08/28/2012 04:01 PM, Franky Lin wrote:
>> On 08/28/2012 03:39 PM, Stephen Warren wrote:
>>> On 08/28/2012 09:45 AM, Franky Lin wrote:
>>>> On 08/28/2012 04:13 AM, Wei Ni wrote:
>>>>> On Tue, 2012-08-28 at 04:06 +0800, Stephen Warren wrote:
>>>>>> On 08/27/2012 09:24 AM, Arend van Spriel wrote:
>>>>>>> On 08/27/2012 12:25 PM, Wei Ni wrote:
>>>>>>>> In case of inband interrupts, if we handle the interrupt in dpc
>>>>>>>> thread,
>>>>>>>> two level of thread switching takes place to process wifi
>>>>>>>> interrupts.
>>>>>>>> One in SDHCI driver and the other in Wifi driver. This may cause the
>>>>>>>> system
>>>>>>>> instability.
>>> ...
>>>>>>> Not sure if I can follow this explanation. The isr is called with
>>>>>>> host
>>>>>>> claimed (by sdio_irq_thread) and all it does is at a linked list
>>>>>>> member
>>>>>>> and signal the dpc thread. After doing this the host is released.
>>>>>>
>>>>>> Is the issue something like the ISR handler or first level of
>>>>>> threading
>>>>>> does:
>>>>>>
>>>>>> * Trigger DPC
>>>>>> * Re-enable interrupt
>>>>>>
>>>>>> So that the interrupt then fires again before the triggered DPC can
>>>>>> run
>>>>>> to handle/clear it, thus causing an interrupt storm?
>>>>>>
>>>>>> Whereas handling the interrupt directly prevents this race condition?
>>>>>
>>>>> Above is my understanding.
>>>>
>>>> I understand the issue here and totally agree that we should treat
>>>> in-band and out-band interrupts differently. But my concern is that the
>>>> behavior of releasing the host before calling brcmf_sdbrcm_isr and grab
>>>> it after is likely error prone. Also we are restructuring the dpc
>>>> routine internally and it's almost done. I will find a better solution
>>>> for in-band interrupt and get it the queue as well. So I suggest
>>>> dropping this patch.
>>>
>>> Franky, do you know which kernel release the DPC restructuring will make
>>> it into? I ask because I can't apply the rest of the patches in this
>>> series without first resolving the stability issues with the Broadcom
>>> WiFi enabled, since that'd de-stabilize the Tegra platform
>>> significantly, and I'd like to plan when we can apply these patches to
>>> Tegra. Thanks!
>>>
>>
>> Hi Stephen,
>>
>> Since we submit patches through linux-wireless tree, you may only be
>> able to pick it up at 3.7-rc1. It's quite a big change so I don't think
>> it will qualify as a bug fix to get into 3.6-rcX.
>
> That's as quick as I expected it to show up, so that's great. I don't
> suppose you could mail Wei and myself once the patch gets into the
> linux-wireless tree, so we can test it out on Tegra. If the patch could
> possibly go into a topic branch in the wireless tree so it can be merged
> into the Tegra tree before this series, that would be awesome. Thanks.
>

Will keep you posted.

Franky



From kgene.kim at samsung.com  Tue Aug 28 19:10:52 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:10:52 -0700
Subject: [PATCH] ARM: S3C24XX: Add .get_rate callback for "camif-upll"
 clock
In-Reply-To: <503D3108.1030804@gmail.com>
References: <1346098329-32059-1-git-send-email-sylvester.nawrocki@gmail.com>
 <503BFB86.20607@samsung.com> <503D3108.1030804@gmail.com>
Message-ID: <503D4FFC.9010706@samsung.com>

On 08/28/12 13:58, Sylwester Nawrocki wrote:
> On 08/28/2012 12:58 AM, Kukjin Kim wrote:
>> On 08/27/12 13:12, Sylwester Nawrocki wrote:
>>> Add missing get_rate callback for the "camif-upll" clock, so frequency
>>> of this clock is properly reported with clk_get_rate().
>>>
>>> Signed-off-by: Sylwester Nawrocki<sylvester.nawrocki at gmail.com>
>>> ---
>>> arch/arm/mach-s3c24xx/clock-s3c2440.c | 14 ++++++++++++++
>>> 1 files changed, 14 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c
>>> b/arch/arm/mach-s3c24xx/clock-s3c2440.c
>>> index cb2883d..749220f 100644
>>> --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
>>> +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
>>> @@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk
>>> *clk, unsigned long rate)
>>> return 0;
>>> }
>>>
>>> +static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
>>> +{
>>> + unsigned long parent_rate = clk_get_rate(clk->parent);
>>> + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
>>> +
>>> + if (!(camdivn&  S3C2440_CAMDIVN_CAMCLK_SEL))
>>> + return parent_rate;
>>> +
>>> + camdivn&= S3C2440_CAMDIVN_CAMCLK_MASK;
>>> +
>>> + return parent_rate / (camdivn + 1) / 2;
>>
>> Well, why do we need '/ 2' here?
>
> I simply followed documentation of the camera clock divider register
> (CAMDIVN). This is how CAMCLK_SEL and CAMCLK_DIV bit fields are described
> there:
>
> CAMDIVN      |  Bit  |       Description
> --------------------------------------------------------------------------
> CAMCLK_SEL   | [4]   | 0 : Use CAMCLK with UPLL output(CAMCLK=UPLL output)
>               |       | 1 : CAMCLK is divided by CAMCLK_DIV value
> -------------+-------+----------------------------------------------------
> CAMCLK_DIV   | [3:0] | CAMCLK divide factor setting register(0 ? 15).
>               |       | Camera clock = UPLL / [(CAMCLK_DIV +1)x2].
>               |       | This bit is valid when CAMCLK_SEL=1.
>
> So, camera clock frequency = parent_rate / ((camdivn + 1) * 2).
> This is exactly same as 'parent_rate / ( camdivn + 1) / 2'.
>
> To be 1000% sure I compared frequency values reported from clk_get_rate()
> in the driver with values measured with an oscilloscope at the CAMCLKOUT
> pin. Everything was as expected (UPLL - 48 MHz, CAMCLKOUT - 12 MHz).
>
> Also, it's easy to confirm correctness of this code by inversing equations
> found in function s3c2440_camif_upll_setrate(), i.e.
>
>   camdivn&= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
>   if (rate != parent_rate) {
>   	camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
>   	camdivn |= (((parent_rate / rate) / 2) - 1);
>   }
>
>   __raw_writel(camdivn, S3C2440_CAMDIVN);
>
> --

Looks OK, thanks for your reply :-)

Applied.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Tue Aug 28 19:12:45 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:12:45 -0700
Subject: [PATCH 0/3] Removal of obsolete s3c2410_* GPIO API
In-Reply-To: <CACRpkdaspHBDUjwf_bPtZoFeYK7q97oX4Jat=pmX810RtGJOpA@mail.gmail.com>
References: <1345897243-15619-1-git-send-email-sylvester.nawrocki@gmail.com>
 <CACRpkdaspHBDUjwf_bPtZoFeYK7q97oX4Jat=pmX810RtGJOpA@mail.gmail.com>
Message-ID: <503D506D.9090201@samsung.com>

On 08/27/12 17:13, Linus Walleij wrote:
> On Sat, Aug 25, 2012 at 5:20 AM, Sylwester Nawrocki
> <sylvester.nawrocki at gmail.com>  wrote:
>
>> This short patch series converts remaining users of the s3c24xx SoC
>> specific gpiolib functions to the gpiolib API and finally removes
>> all s3c2410_* functions from drivers/gpio/gpio-samsung.c.
>
> I'm fine with this as long as the Samsung maintainer is, so
> Acked-by: Linus Walleij<linus.walleij at linaro.org>
>
Thanks, applied this series with your ack.

> But I suspect this will be merged through the Samsung SoC tree?
>
Yes, then will be sent to upstream via arm-soc. If any problems, please 
let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From grinberg at compulab.co.il  Tue Aug 28 19:18:48 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:48 +0300
Subject: [PATCH 0/9] ARM: OMAP: cleanup plat/board.h file
Message-ID: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>

This patch series cleans up the plat/board.h and related files.

Remove confusingly empty struct omap_board_config_kernel structures
and unused omap_get_nr_config() macro along with
unused omap_get_var_config() function.
Those apparently were never used in upstream kernels.

Move OMAP3EVM revision bits to the board file as those are not used
(and never have been used) outside of the board file in upstream kernels.

Remove the tags part of the sti console workaround on OMAP2.
Also remove the crystal type tag parsing code on OMAP1.
Since the tags were never used upstream, the sti console workaround
and the crystal type tag parsing code have never fired.

OMAP custom tags code is not used - remove it.
Finally, move all leftovers from the plat/board.h to include/linux/*
and delete the plat/board.h file.

The series are based on Linus' v3.6-rc3, checkpatch clean,
and have been compile tested with omap1|2plus_defconfig(s).

Igor Grinberg (9):
  ARM: OMAP: cleanup struct omap_board_config_kernel
  ARM: OMAP: omap3evm: cleanup revision bits
  ARM: OMAP: remove the sti console workaround
  ARM: OMAP1: remove the crystal type tag parsing
  ARM: OMAP: remove the omap custom tags
  ARM: OMAP1: move omap1_bl pdata out of arch/arm/*
  ARM: OMAP1: move lcd pdata out of arch/arm/*
  ARM: OMAP: move debug_card_init() function
  ARM: OMAP: remove plat/board.h file

 arch/arm/mach-omap1/board-ams-delta.c           |    1 -
 arch/arm/mach-omap1/board-fsample.c             |    1 -
 arch/arm/mach-omap1/board-generic.c             |    6 -
 arch/arm/mach-omap1/board-htcherald.c           |    1 -
 arch/arm/mach-omap1/board-nokia770.c            |    1 -
 arch/arm/mach-omap1/board-osk.c                 |    1 +
 arch/arm/mach-omap1/board-palmte.c              |    2 +-
 arch/arm/mach-omap1/board-palmtt.c              |    2 +-
 arch/arm/mach-omap1/board-palmz71.c             |    2 +-
 arch/arm/mach-omap1/board-perseus2.c            |    1 -
 arch/arm/mach-omap1/board-sx1.c                 |    1 -
 arch/arm/mach-omap1/board-voiceblue.c           |    6 -
 arch/arm/mach-omap1/clock_data.c                |    8 --
 arch/arm/mach-omap1/devices.c                   |    1 -
 arch/arm/mach-omap1/serial.c                    |    1 -
 arch/arm/mach-omap2/board-2430sdp.c             |    1 -
 arch/arm/mach-omap2/board-3430sdp.c             |    6 -
 arch/arm/mach-omap2/board-3630sdp.c             |    6 -
 arch/arm/mach-omap2/board-4430sdp.c             |    1 -
 arch/arm/mach-omap2/board-am3517crane.c         |    9 --
 arch/arm/mach-omap2/board-am3517evm.c           |    6 -
 arch/arm/mach-omap2/board-apollon.c             |    1 -
 arch/arm/mach-omap2/board-cm-t35.c              |    6 -
 arch/arm/mach-omap2/board-cm-t3517.c            |    6 -
 arch/arm/mach-omap2/board-devkit8000.c          |    1 -
 arch/arm/mach-omap2/board-generic.c             |    1 -
 arch/arm/mach-omap2/board-h4.c                  |    2 +-
 arch/arm/mach-omap2/board-igep0020.c            |    1 -
 arch/arm/mach-omap2/board-ldp.c                 |    1 -
 arch/arm/mach-omap2/board-n8x0.c                |    1 -
 arch/arm/mach-omap2/board-omap3beagle.c         |    1 -
 arch/arm/mach-omap2/board-omap3evm.c            |   19 ++-
 arch/arm/mach-omap2/board-omap3logic.c          |    1 -
 arch/arm/mach-omap2/board-omap3pandora.c        |    1 -
 arch/arm/mach-omap2/board-omap3stalker.c        |    6 -
 arch/arm/mach-omap2/board-omap3touchbook.c      |    1 -
 arch/arm/mach-omap2/board-omap4panda.c          |    1 -
 arch/arm/mach-omap2/board-overo.c               |    1 -
 arch/arm/mach-omap2/board-rx51-peripherals.c    |    1 -
 arch/arm/mach-omap2/board-rx51.c                |    1 -
 arch/arm/mach-omap2/board-ti8168evm.c           |    6 -
 arch/arm/mach-omap2/board-zoom.c                |    1 -
 arch/arm/mach-omap2/common.c                    |    1 -
 arch/arm/mach-omap2/devices.c                   |    1 -
 arch/arm/mach-omap2/gpmc-nand.c                 |    1 -
 arch/arm/mach-omap2/gpmc-onenand.c              |    1 -
 arch/arm/mach-omap2/gpmc-smc91x.c               |    1 -
 arch/arm/mach-omap2/gpmc-smsc911x.c             |    1 -
 arch/arm/mach-omap2/pm-debug.c                  |    1 -
 arch/arm/mach-omap2/pm24xx.c                    |   11 --
 arch/arm/mach-omap2/serial.c                    |    1 -
 arch/arm/plat-omap/common.c                     |   40 -------
 arch/arm/plat-omap/counter_32k.c                |    1 -
 arch/arm/plat-omap/debug-devices.c              |    3 -
 arch/arm/plat-omap/devices.c                    |    1 -
 arch/arm/plat-omap/fb.c                         |    2 -
 arch/arm/plat-omap/include/plat/board.h         |  138 -----------------------
 arch/arm/plat-omap/include/plat/debug-devices.h |    9 ++
 arch/arm/plat-omap/include/plat/mmc.h           |    1 -
 arch/arm/plat-omap/include/plat/usb.h           |    1 -
 arch/arm/plat-omap/sram.c                       |    1 -
 drivers/mmc/host/omap.c                         |    1 -
 drivers/mmc/host/omap_hsmmc.c                   |    1 -
 drivers/mtd/onenand/omap2.c                     |    2 -
 drivers/video/backlight/omap1_bl.c              |    2 +-
 include/linux/omapfb.h                          |    7 +-
 include/linux/platform_data/omap1_bl.h          |   11 ++
 67 files changed, 44 insertions(+), 320 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/board.h
 create mode 100644 arch/arm/plat-omap/include/plat/debug-devices.h
 create mode 100644 include/linux/platform_data/omap1_bl.h

-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:50 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:50 +0300
Subject: [PATCH 2/9] ARM: OMAP: omap3evm: cleanup revision bits
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-3-git-send-email-grinberg@compulab.co.il>

The omap3evm has its revision information bits inside the plat/board.h
file. Those bits are not used anywhere in the upstream tree besides the
board-omap3evm.c file.
Move the OMAP3EVM_BOARD_GEN_* bits to the board file and remove the
get_omap3_evm_rev() function declaration.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/board-omap3evm.c    |   12 ++++++++++++
 arch/arm/plat-omap/include/plat/board.h |   18 ------------------
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5be082b..8477137 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -73,6 +73,18 @@
 #define OMAP3EVM_GEN1_ETHR_GPIO_RST	64
 #define OMAP3EVM_GEN2_ETHR_GPIO_RST	7
 
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *	GEN_1	= 0x01150000
+ *	GEN_2	= 0x92200000
+ */
+enum {
+	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
+	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
+};
+
 static u8 omap3_evm_version;
 
 u8 get_omap3_evm_rev(void)
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index e6a8d79..db3bdc1 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -14,18 +14,6 @@
 
 #include <plat/gpio-switch.h>
 
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- *	GEN_1	= 0x01150000
- *	GEN_2	= 0x92200000
- */
-enum {
-	OMAP3EVM_BOARD_GEN_1 = 0,	/* EVM Rev between  A - D */
-	OMAP3EVM_BOARD_GEN_2,		/* EVM Rev >= Rev E */
-};
-
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK		0x4f01
 #define OMAP_TAG_GPIO_SWITCH	0x4f06
@@ -125,10 +113,4 @@ extern int omap_board_config_size;
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
-/* OMAP3EVM revision */
-#if defined(CONFIG_MACH_OMAP3EVM)
-u8 get_omap3_evm_rev(void);
-#else
-#define get_omap3_evm_rev() (-EINVAL)
-#endif
 #endif
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:51 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:51 +0300
Subject: [PATCH 3/9] ARM: OMAP: remove the sti console workaround
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-4-git-send-email-grinberg@compulab.co.il>

The sti console workaround uses the OMAP custom tags.
Those tags are not used in upstream kernel and therefore the workaround
never fires on upstream kernels.
Remove the sti console workaround tags part.
This leaves the workaround functional part intact so can be reused if
needed.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/pm24xx.c |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc..9e54dc9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -352,16 +352,6 @@ int __init omap2_pm_init(void)
 
 	prcm_setup_regs();
 
-	/* Hack to prevent MPU retention when STI console is enabled. */
-	{
-		const struct omap_sti_console_config *sti;
-
-		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
-				      struct omap_sti_console_config);
-		if (sti != NULL && sti->enable)
-			sti_console_enabled = 1;
-	}
-
 	/*
 	 * We copy the assembler sleep/wakeup routines to SRAM.
 	 * These routines need to be in SRAM as that's the only
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:49 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:49 +0300
Subject: [PATCH 1/9] ARM: OMAP: cleanup struct omap_board_config_kernel
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-2-git-send-email-grinberg@compulab.co.il>

struct omap_board_config_kernel defined in the board files
is always empty and does not bring any added value.
Remove the struct omap_board_config_kernel instances from the board
files.
Also remove the omap_get_nr_config() macro and the omap_get_var_config()
function as both are not used for quite a long time (if ever).

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap1/board-generic.c      |    5 -----
 arch/arm/mach-omap1/board-voiceblue.c    |    5 -----
 arch/arm/mach-omap2/board-3430sdp.c      |    6 ------
 arch/arm/mach-omap2/board-3630sdp.c      |    6 ------
 arch/arm/mach-omap2/board-am3517crane.c  |    9 ---------
 arch/arm/mach-omap2/board-am3517evm.c    |    6 ------
 arch/arm/mach-omap2/board-cm-t35.c       |    6 ------
 arch/arm/mach-omap2/board-cm-t3517.c     |    6 ------
 arch/arm/mach-omap2/board-omap3evm.c     |    7 -------
 arch/arm/mach-omap2/board-omap3stalker.c |    6 ------
 arch/arm/mach-omap2/board-ti8168evm.c    |    6 ------
 arch/arm/plat-omap/common.c              |    5 -----
 arch/arm/plat-omap/include/plat/board.h  |    4 ----
 13 files changed, 0 insertions(+), 77 deletions(-)

diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 6ec385e..d032734 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -52,9 +52,6 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
 };
 #endif
 
-static struct omap_board_config_kernel generic_config[] __initdata = {
-};
-
 static void __init omap_generic_init(void)
 {
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -76,8 +73,6 @@ static void __init omap_generic_init(void)
 	}
 #endif
 
-	omap_board_config = generic_config;
-	omap_board_config_size = ARRAY_SIZE(generic_config);
 	omap_serial_init();
 	omap_register_i2c_bus(1, 100, NULL, 0);
 }
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 3497769..11e1ff3 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -155,9 +155,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
 	.pins[2]	= 6,
 };
 
-static struct omap_board_config_kernel voiceblue_config[] = {
-};
-
 #define MACHINE_PANICED		1
 #define MACHINE_REBOOTING	2
 #define MACHINE_REBOOT		4
@@ -275,8 +272,6 @@ static void __init voiceblue_init(void)
 	voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
 	voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
-	omap_board_config = voiceblue_config;
-	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
 	omap_serial_init();
 	omap1_usb_init(&voiceblue_usb_config);
 	omap_register_i2c_bus(1, 100, NULL, 0);
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index a98c688..0f78cdb 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -31,7 +31,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
 #include <plat/dma.h>
@@ -191,9 +190,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
 	.default_device	= &sdp3430_lcd_device,
 };
 
-static struct omap_board_config_kernel sdp3430_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
@@ -576,8 +572,6 @@ static void __init omap_3430sdp_init(void)
 	int gpio_pendown;
 
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-	omap_board_config = sdp3430_config;
-	omap_board_config_size = ARRAY_SIZE(sdp3430_config);
 	omap_hsmmc_init(mmc);
 	omap3430_i2c_init();
 	omap_display_init(&sdp3430_dss_data);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 2dc9ba5..8518b13 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -17,7 +17,6 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
 #include <plat/gpmc-smc91x.h>
 #include <plat/usb.h>
 
@@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 	.reset_gpio_port[2]  = -EINVAL
 };
 
-static struct omap_board_config_kernel sdp_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
 	{ .reg_offset = OMAP_MUX_TERMINATOR },
@@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-	omap_board_config = sdp_config;
-	omap_board_config_size = ARRAY_SIZE(sdp_config);
 	zoom_peripherals_init();
 	omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
 				  h8mbx00u0mer0em_sdrc_params);
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 92432c2..de92b08 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -26,7 +26,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
@@ -37,11 +36,6 @@
 #define GPIO_USB_POWER		35
 #define GPIO_USB_NRESET		38
 
-
-/* Board initialization */
-static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
 	{ .reg_offset = OMAP_MUX_TERMINATOR },
@@ -67,9 +61,6 @@ static void __init am3517_crane_init(void)
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
 
-	omap_board_config = am3517_crane_config;
-	omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
-
 	/* Configure GPIO for EHCI port */
 	if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
 		pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 18f6010..00abda1 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -32,7 +32,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -324,9 +323,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
 	platform_device_register(&am3517_hecc_device);
 }
 
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
@@ -346,8 +342,6 @@ static struct omap2_hsmmc_info mmc[] = {
 
 static void __init am3517_evm_init(void)
 {
-	omap_board_config = am3517_evm_config;
-	omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
 	am3517_evm_i2c_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 97d7190..d94a640 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -37,7 +37,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/nand.h>
 #include <plat/gpmc.h>
@@ -714,13 +713,8 @@ static inline void cm_t35_init_mux(void) {}
 static inline void cm_t3730_init_mux(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
-
 static void __init cm_t3x_common_init(void)
 {
-	omap_board_config = cm_t35_config;
-	omap_board_config_size = ARRAY_SIZE(cm_t35_config);
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
 	omap_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a33ad46..57204f8 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -38,7 +38,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/nand.h>
@@ -249,9 +248,6 @@ static void __init cm_t3517_init_nand(void)
 static inline void cm_t3517_init_nand(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
 	/* GPIO186 - Green LED */
@@ -285,8 +281,6 @@ static void __init cm_t3517_init(void)
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
-	omap_board_config = cm_t3517_config;
-	omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
 	cm_t3517_init_leds();
 	cm_t3517_init_nand();
 	cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0..5be082b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -45,7 +45,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include <plat/usb.h>
 #include <plat/nand.h>
 #include "common.h"
@@ -525,9 +524,6 @@ static int __init omap3_evm_i2c_init(void)
 	return 0;
 }
 
-static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
-};
-
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 
 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -687,9 +683,6 @@ static void __init omap3_evm_init(void)
 	obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
 	omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
-	omap_board_config = omap3_evm_config;
-	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-
 	omap_mux_init_gpio(63, OMAP_PIN_INPUT);
 	omap_hsmmc_init(mmc);
 
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index b318f56..421fb8e 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -35,7 +35,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
@@ -362,9 +361,6 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO	175
 
-static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
-};
-
 static struct platform_device *omap3_stalker_devices[] __initdata = {
 	&keys_gpio,
 };
@@ -399,8 +395,6 @@ static void __init omap3_stalker_init(void)
 {
 	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-	omap_board_config = omap3_stalker_config;
-	omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
 	omap_mux_init_gpio(23, OMAP_PIN_INPUT);
 	omap_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index d4c8392..da4679d 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -21,7 +21,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/irqs.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
@@ -32,15 +31,10 @@ static struct omap_musb_board_data musb_board_data = {
 	.power		= 500,
 };
 
-static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
-};
-
 static void __init ti81xx_evm_init(void)
 {
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
-	omap_board_config = ti81xx_evm_config;
-	omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
 	usb_musb_init(&musb_board_data);
 }
 
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 89a3723..af98971 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -58,11 +58,6 @@ const void *__init __omap_get_config(u16 tag, size_t len, int nr)
         return get_config(tag, len, nr, NULL);
 }
 
-const void *__init omap_get_var_config(u16 tag, size_t *len)
-{
-        return get_config(tag, NO_LENGTH_CHECK, 0, len);
-}
-
 void __init omap_reserve(void)
 {
 	omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index e62f20a..e6a8d79 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -117,10 +117,6 @@ extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
 
 #define omap_get_config(tag, type) \
 	((const type *) __omap_get_config((tag), sizeof(type), 0))
-#define omap_get_nr_config(tag, type, nr) \
-	((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-
-extern const void *__init omap_get_var_config(u16 tag, size_t *len);
 
 extern struct omap_board_config_kernel *omap_board_config;
 extern int omap_board_config_size;
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:52 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:52 +0300
Subject: [PATCH 4/9] ARM: OMAP1: remove the crystal type tag parsing
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-5-git-send-email-grinberg@compulab.co.il>

The omap1 crystal setting uses the OMAP custom tags.
Those tags are not used in upstream kernel and therefore the crystal
type is never set by the tag parsing code on upstream kernels.
Remove the crystal tag parsing code.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap1/clock_data.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c007d80..6a32b9b 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,7 +25,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
-#include <plat/board.h>
 #include <plat/sram.h>	/* for omap_sram_reprogram_clock() */
 
 #include <mach/hardware.h>
@@ -788,7 +787,6 @@ u32 cpu_mask;
 int __init omap1_clk_init(void)
 {
 	struct omap_clk *c;
-	const struct omap_clock_config *info;
 	int crystal_type = 0; /* Default 12 MHz */
 	u32 reg;
 
@@ -837,12 +835,6 @@ int __init omap1_clk_init(void)
 	ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 	ck_ref_p = clk_get(NULL, "ck_ref");
 
-	info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-	if (info != NULL) {
-		if (!cpu_is_omap15xx())
-			crystal_type = info->system_clock_type;
-	}
-
 	if (cpu_is_omap7xx())
 		ck_ref.rate = 13000000;
 	if (cpu_is_omap16xx() && crystal_type == 2)
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:54 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:54 +0300
Subject: [PATCH 6/9] ARM: OMAP1: move omap1_bl pdata out of arch/arm/*
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-7-git-send-email-grinberg@compulab.co.il>

omap1 backlight platform data resides inside plat/board.h while it
should be inside include/linux/...
Move the omap1 backlight platform data to
include/linux/platform_data/.

Cc: Richard Purdie <rpurdie at rpsys.net>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
Cc: linux-fbdev at vger.kernel.org
Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap1/board-osk.c         |    1 +
 arch/arm/mach-omap1/board-palmte.c      |    1 +
 arch/arm/mach-omap1/board-palmtt.c      |    1 +
 arch/arm/mach-omap1/board-palmz71.c     |    1 +
 arch/arm/plat-omap/include/plat/board.h |    7 -------
 drivers/video/backlight/omap1_bl.c      |    2 +-
 include/linux/platform_data/omap1_bl.h  |   11 +++++++++++
 7 files changed, 16 insertions(+), 8 deletions(-)
 create mode 100644 include/linux/platform_data/omap1_bl.h

diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 8784705..569b687 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -39,6 +39,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 26bcb9d..7bf00ba 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -28,6 +28,7 @@
 #include <linux/interrupt.h>
 #include <linux/apm-emulation.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 4d09944..2cce505 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -27,6 +27,7 @@
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 3559803..45ab9f0 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -30,6 +30,7 @@
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 5938c72..d0bc46e 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -19,13 +19,6 @@ struct omap_lcd_config {
 	u8   data_lines;
 };
 
-struct device;
-struct fb_info;
-struct omap_backlight_config {
-	int default_intensity;
-	int (*set_power)(struct device *dev, int state);
-};
-
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index bfdc5fb..92257ef 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -27,9 +27,9 @@
 #include <linux/fb.h>
 #include <linux/backlight.h>
 #include <linux/slab.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <mach/hardware.h>
-#include <plat/board.h>
 #include <plat/mux.h>
 
 #define OMAPBL_MAX_INTENSITY		0xff
diff --git a/include/linux/platform_data/omap1_bl.h b/include/linux/platform_data/omap1_bl.h
new file mode 100644
index 0000000..881a8e9
--- /dev/null
+++ b/include/linux/platform_data/omap1_bl.h
@@ -0,0 +1,11 @@
+#ifndef __OMAP1_BL_H__
+#define __OMAP1_BL_H__
+
+#include <linux/device.h>
+
+struct omap_backlight_config {
+	int default_intensity;
+	int (*set_power)(struct device *dev, int state);
+};
+
+#endif
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:56 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:56 +0300
Subject: [PATCH 8/9] ARM: OMAP: move debug_card_init() function
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-9-git-send-email-grinberg@compulab.co.il>

debug_card_init() function resides in the plat/board.h file.
Move it to a separate header file under plat/ so the board.h file can be
removed.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/board-h4.c                  |    2 +-
 arch/arm/plat-omap/include/plat/board.h         |    5 -----
 arch/arm/plat-omap/include/plat/debug-devices.h |    9 +++++++++
 3 files changed, 10 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/debug-devices.h

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index ace2048..5be30e6 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,11 +32,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include <plat/debug-devices.h>
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 2ddc198..d92f1b5 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -10,9 +10,4 @@
 #ifndef _OMAP_BOARD_H
 #define _OMAP_BOARD_H
 
-#include <linux/types.h>
-
-/* for TI reference platforms sharing the same debug card */
-extern int debug_card_init(u32 addr, unsigned gpio);
-
 #endif
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
new file mode 100644
index 0000000..a4edbd2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -0,0 +1,9 @@
+#ifndef _OMAP_DEBUG_DEVICES_H
+#define _OMAP_DEBUG_DEVICES_H
+
+#include <linux/types.h>
+
+/* for TI reference platforms sharing the same debug card */
+extern int debug_card_init(u32 addr, unsigned gpio);
+
+#endif
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:55 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:55 +0300
Subject: [PATCH 7/9] ARM: OMAP1: move lcd pdata out of arch/arm/*
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-8-git-send-email-grinberg@compulab.co.il>

omap1 lcd platform data resides inside plat/board.h while it
should be inside include/linux/...
Move the omap1 lcd platform data to include/linux/omapfb.h.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap1/board-ams-delta.c   |    1 -
 arch/arm/mach-omap1/board-fsample.c     |    1 -
 arch/arm/mach-omap1/board-htcherald.c   |    1 -
 arch/arm/mach-omap1/board-nokia770.c    |    1 -
 arch/arm/mach-omap1/board-palmte.c      |    1 -
 arch/arm/mach-omap1/board-palmtt.c      |    1 -
 arch/arm/mach-omap1/board-palmz71.c     |    1 -
 arch/arm/mach-omap1/board-perseus2.c    |    1 -
 arch/arm/mach-omap1/board-sx1.c         |    1 -
 arch/arm/plat-omap/fb.c                 |    2 --
 arch/arm/plat-omap/include/plat/board.h |    7 -------
 include/linux/omapfb.h                  |    7 ++++++-
 12 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c534698..c162369 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -37,7 +37,6 @@
 #include <plat/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <plat/mux.h>
-#include <plat/board.h>
 
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 6872f3f..6d98552 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -32,7 +32,6 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/keypad.h>
-#include <plat/board.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index b3f6e94..b9771b5 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -42,7 +42,6 @@
 #include <asm/mach/arch.h>
 
 #include <plat/omap7xx.h>
-#include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/mmc.h>
 
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 2c0ca8f..ec01f03 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 7bf00ba..49f8d74 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -38,7 +38,6 @@
 #include <plat/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
-#include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 2cce505..01523cd 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -38,7 +38,6 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
 
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 45ab9f0..a7abce6 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -40,7 +40,6 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
 
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 703d55e..277e0bc 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -32,7 +32,6 @@
 #include <plat/fpga.h>
 #include <plat/flash.h>
 #include <plat/keypad.h>
-#include <plat/board.h>
 
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 8c665bd..2e1fff2 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -38,7 +38,6 @@
 #include <plat/dma.h>
 #include <plat/irda.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
 
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index dd6f92c..bcbb9d5 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,8 +33,6 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
-
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
 static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index d0bc46e..2ddc198 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,13 +12,6 @@
 
 #include <linux/types.h>
 
-struct omap_lcd_config {
-	char panel_name[16];
-	char ctrl_name[16];
-	s16  nreset_gpio;
-	u8   data_lines;
-};
-
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
diff --git a/include/linux/omapfb.h b/include/linux/omapfb.h
index 4ff57e8..85af818 100644
--- a/include/linux/omapfb.h
+++ b/include/linux/omapfb.h
@@ -220,7 +220,12 @@ struct omapfb_display_info {
 
 #ifdef __KERNEL__
 
-#include <plat/board.h>
+struct omap_lcd_config {
+	char panel_name[16];
+	char ctrl_name[16];
+	s16  nreset_gpio;
+	u8   data_lines;
+};
 
 struct omapfb_platform_data {
 	struct omap_lcd_config		lcd;
-- 
1.7.8.6



From grinberg at compulab.co.il  Tue Aug 28 19:18:53 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:53 +0300
Subject: [PATCH 5/9] ARM: OMAP: remove the omap custom tags
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-6-git-send-email-grinberg@compulab.co.il>

The omap custom initialization tags are not used anymore (if ever)
by the mainline kernel.
Thus remove the omap custom initialization tags.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/plat-omap/common.c             |   34 ------------
 arch/arm/plat-omap/include/plat/board.h |   84 -------------------------------
 2 files changed, 0 insertions(+), 118 deletions(-)

diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index af98971..7c04748 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -24,40 +24,6 @@
 
 #include <plat/omap-secure.h>
 
-
-#define NO_LENGTH_CHECK 0xffffffff
-
-struct omap_board_config_kernel *omap_board_config __initdata;
-int omap_board_config_size;
-
-static const void *__init get_config(u16 tag, size_t len,
-		int skip, size_t *len_out)
-{
-	struct omap_board_config_kernel *kinfo = NULL;
-	int i;
-
-	/* Try to find the config from the board-specific structures
-	 * in the kernel. */
-	for (i = 0; i < omap_board_config_size; i++) {
-		if (omap_board_config[i].tag == tag) {
-			if (skip == 0) {
-				kinfo = &omap_board_config[i];
-				break;
-			} else {
-				skip--;
-			}
-		}
-	}
-	if (kinfo == NULL)
-		return NULL;
-	return kinfo->data;
-}
-
-const void *__init __omap_get_config(u16 tag, size_t len, int nr)
-{
-        return get_config(tag, len, nr, NULL);
-}
-
 void __init omap_reserve(void)
 {
 	omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index db3bdc1..5938c72 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -12,39 +12,6 @@
 
 #include <linux/types.h>
 
-#include <plat/gpio-switch.h>
-
-/* Different peripheral ids */
-#define OMAP_TAG_CLOCK		0x4f01
-#define OMAP_TAG_GPIO_SWITCH	0x4f06
-#define OMAP_TAG_STI_CONSOLE	0x4f09
-#define OMAP_TAG_CAMERA_SENSOR	0x4f0a
-
-#define OMAP_TAG_BOOT_REASON    0x4f80
-#define OMAP_TAG_FLASH_PART	0x4f81
-#define OMAP_TAG_VERSION_STR	0x4f82
-
-struct omap_clock_config {
-	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
-	u8 system_clock_type;
-};
-
-struct omap_serial_console_config {
-	u8 console_uart;
-	u32 console_speed;
-};
-
-struct omap_sti_console_config {
-	unsigned enable:1;
-	u8 channel;
-};
-
-struct omap_camera_sensor_config {
-	u16 reset_gpio;
-	int (*power_on)(void * data);
-	int (*power_off)(void * data);
-};
-
 struct omap_lcd_config {
 	char panel_name[16];
 	char ctrl_name[16];
@@ -59,57 +26,6 @@ struct omap_backlight_config {
 	int (*set_power)(struct device *dev, int state);
 };
 
-struct omap_fbmem_config {
-	u32 start;
-	u32 size;
-};
-
-struct omap_pwm_led_platform_data {
-	const char *name;
-	int intensity_timer;
-	int blink_timer;
-	void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
-};
-
-struct omap_uart_config {
-	/* Bit field of UARTs present; bit 0 --> UART1 */
-	unsigned int enabled_uarts;
-};
-
-
-struct omap_flash_part_config {
-	char part_table[0];
-};
-
-struct omap_boot_reason_config {
-	char reason_str[12];
-};
-
-struct omap_version_config {
-	char component[12];
-	char version[12];
-};
-
-struct omap_board_config_entry {
-	u16 tag;
-	u16 len;
-	u8  data[0];
-};
-
-struct omap_board_config_kernel {
-	u16 tag;
-	const void *data;
-};
-
-extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-
-#define omap_get_config(tag, type) \
-	((const type *) __omap_get_config((tag), sizeof(type), 0))
-
-extern struct omap_board_config_kernel *omap_board_config;
-extern int omap_board_config_size;
-
-
 /* for TI reference platforms sharing the same debug card */
 extern int debug_card_init(u32 addr, unsigned gpio);
 
-- 
1.7.8.6



From kgene.kim at samsung.com  Tue Aug 28 19:20:18 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:20:18 -0700
Subject: [PATCH] ARM: Exynos4: Turn off clocks for NAND, OneNAND and TSI
 controllers
In-Reply-To: <CAJuYYwSFMR1cJm7SB-eF_aYM9SPMaopvw3K9stiPvabCfjH=QA@mail.gmail.com>
References: <1345819936-6503-1-git-send-email-chander.kashyap@linaro.org>
 <CAJuYYwSFMR1cJm7SB-eF_aYM9SPMaopvw3K9stiPvabCfjH=QA@mail.gmail.com>
Message-ID: <503D5232.5040101@samsung.com>

On 08/28/12 01:15, Thomas Abraham wrote:
> On 24 August 2012 20:22, Chander Kashyap<chander.kashyap at linaro.org>  wrote:
>> The clocks for NAND, OneNAND and Transport Stream Interface(TSI)
>> controllers could be either enabled or disabled at boot. To ensure
>> that these are turned off until used, add them to the list of clocks
>> to be turned off during boot.
>>
>> Signed-off-by: Chander Kashyap<chander.kashyap at linaro.org>
>> ---
>>   arch/arm/mach-exynos/clock-exynos4.c |   12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
>> index 2f51293..7cc5491 100644
>> --- a/arch/arm/mach-exynos/clock-exynos4.c
>> +++ b/arch/arm/mach-exynos/clock-exynos4.c
>> @@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
>>                  .enable         = exynos4_clk_ip_cam_ctrl,
>>                  .ctrlbit        = (1<<  3),
>>          }, {
>> +               .name           = "tsi",
>> +               .enable         = exynos4_clk_ip_fsys_ctrl,
>> +               .ctrlbit        = (1<<  4),
>> +       }, {
>>                  .name           = "hsmmc",
>>                  .devname        = "exynos4-sdhci.0",
>>                  .parent         =&exynos4_clk_aclk_133.clk,
>> @@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
>>                  .enable         = exynos4_clk_ip_fsys_ctrl,
>>                  .ctrlbit        = (1<<  9),
>>          }, {
>> +               .name           = "onenand",
>> +               .enable         = exynos4_clk_ip_fsys_ctrl,
>> +               .ctrlbit        = (1<<  15),
>> +       }, {
>> +               .name           = "nfcon",
>> +               .enable         = exynos4_clk_ip_fsys_ctrl,
>> +               .ctrlbit        = (1<<  16),
>> +       }, {
>>                  .name           = "dac",
>>                  .devname        = "s5p-sdo",
>>                  .enable         = exynos4_clk_ip_tv_ctrl,
>> --
>> 1.7.9.5
>
> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>

Applied, thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From grinberg at compulab.co.il  Tue Aug 28 19:18:57 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 29 Aug 2012 02:18:57 +0300
Subject: =?UTF-8?q?=5BPATCH=209/9=5D=20ARM=3A=20OMAP=3A=20remove=20plat/board=2Eh=20file?=
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346195937-6383-10-git-send-email-grinberg@compulab.co.il>

plat/board.h file is now empty - remove it.

Cc: Jarkko Lavinen <jarkko.lavinen at nokia.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: linux-mmc at vger.kernel.org
Cc: linux-mtd at lists.infradead.org
Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap1/board-generic.c          |    1 -
 arch/arm/mach-omap1/board-voiceblue.c        |    1 -
 arch/arm/mach-omap1/devices.c                |    1 -
 arch/arm/mach-omap1/serial.c                 |    1 -
 arch/arm/mach-omap2/board-2430sdp.c          |    1 -
 arch/arm/mach-omap2/board-4430sdp.c          |    1 -
 arch/arm/mach-omap2/board-apollon.c          |    1 -
 arch/arm/mach-omap2/board-devkit8000.c       |    1 -
 arch/arm/mach-omap2/board-generic.c          |    1 -
 arch/arm/mach-omap2/board-igep0020.c         |    1 -
 arch/arm/mach-omap2/board-ldp.c              |    1 -
 arch/arm/mach-omap2/board-n8x0.c             |    1 -
 arch/arm/mach-omap2/board-omap3beagle.c      |    1 -
 arch/arm/mach-omap2/board-omap3logic.c       |    1 -
 arch/arm/mach-omap2/board-omap3pandora.c     |    1 -
 arch/arm/mach-omap2/board-omap3touchbook.c   |    1 -
 arch/arm/mach-omap2/board-omap4panda.c       |    1 -
 arch/arm/mach-omap2/board-overo.c            |    1 -
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 -
 arch/arm/mach-omap2/board-rx51.c             |    1 -
 arch/arm/mach-omap2/board-zoom.c             |    1 -
 arch/arm/mach-omap2/common.c                 |    1 -
 arch/arm/mach-omap2/devices.c                |    1 -
 arch/arm/mach-omap2/gpmc-nand.c              |    1 -
 arch/arm/mach-omap2/gpmc-onenand.c           |    1 -
 arch/arm/mach-omap2/gpmc-smc91x.c            |    1 -
 arch/arm/mach-omap2/gpmc-smsc911x.c          |    1 -
 arch/arm/mach-omap2/pm-debug.c               |    1 -
 arch/arm/mach-omap2/pm24xx.c                 |    1 -
 arch/arm/mach-omap2/serial.c                 |    1 -
 arch/arm/plat-omap/common.c                  |    1 -
 arch/arm/plat-omap/counter_32k.c             |    1 -
 arch/arm/plat-omap/debug-devices.c           |    3 ---
 arch/arm/plat-omap/devices.c                 |    1 -
 arch/arm/plat-omap/include/plat/board.h      |   13 -------------
 arch/arm/plat-omap/include/plat/mmc.h        |    1 -
 arch/arm/plat-omap/include/plat/usb.h        |    1 -
 arch/arm/plat-omap/sram.c                    |    1 -
 drivers/mmc/host/omap.c                      |    1 -
 drivers/mmc/host/omap_hsmmc.c                |    1 -
 drivers/mtd/onenand/omap2.c                  |    2 --
 41 files changed, 0 insertions(+), 56 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/board.h

diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index d032734..04b5fda 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -23,7 +23,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/board.h>
 
 #include <mach/usb.h>
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 11e1ff3..1668af3 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -35,7 +35,6 @@
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index fa1fa4d..1feca35 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -20,7 +20,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 6809c9e..0d1709b 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -22,7 +22,6 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
 
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9511584..36eee4b 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index ad8a7d9..04e8574 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -34,7 +34,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index e5fa46b..a6a1b48 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 6567c1c..870a2a5 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -40,7 +40,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 6f93a20..38024a5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,7 +20,6 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include "common-board-devices.h"
 
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 7491529..c4f17bb 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -29,7 +29,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ef9e829..c37c2a1 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -35,7 +35,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 677357f..5397209 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -25,7 +25,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 6202fc7..293e3b2 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -39,7 +39,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index fca93d1..a63a49d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -41,7 +41,6 @@
 #include "common-board-devices.h"
 
 #include <plat/mux.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 57aebee..633c445 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,7 +40,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 485d14d..d3556c9 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,7 +44,6 @@
 #include <asm/mach/flash.h>
 #include <asm/system_info.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 70f6d1d..3911c13 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -39,7 +39,6 @@
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 779734d..193d160 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -42,7 +42,6 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index df2534d..3b9fc61 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -28,7 +28,6 @@
 #include <asm/system_info.h>
 
 #include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd93..92924eb 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -24,7 +24,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4e7e561..4994438 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -22,7 +22,6 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 069f972..6c2ff4f 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 
 #include <plat/hardware.h>
-#include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/clock.h>
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c00c689..56dfa2d 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -26,7 +26,6 @@
 #include <asm/pmu.h>
 
 #include "iomap.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 386dec8..513ed9e 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -18,7 +18,6 @@
 
 #include <plat/cpu.h>
 #include <plat/nand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
 static struct resource gpmc_nand_resource = {
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index a0fa9bb..c5f005e 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -20,7 +20,6 @@
 
 #include <plat/cpu.h>
 #include <plat/onenand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
 static struct omap_onenand_platform_data *gpmc_onenand_data;
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index ba10c24..3f75ff0 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,7 +17,6 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
 #include <plat/gpmc-smc91x.h>
 
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index b6c77be..a3a2887 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -20,7 +20,6 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
 #include <plat/gpmc-smsc911x.h>
 
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd9..3e1345f 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -28,7 +28,6 @@
 #include <linux/slab.h>
 
 #include <plat/clock.h>
-#include <plat/board.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/dmtimer.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 9e54dc9..de1caf1 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -38,7 +38,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
-#include <plat/board.h>
 
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index c1b93c7..10f7f02 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -29,7 +29,6 @@
 
 #include <plat/omap-serial.h>
 #include "common.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 7c04748..e5778ed 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -17,7 +17,6 @@
 #include <linux/dma-mapping.h>
 
 #include <plat/common.h>
-#include <plat/board.h>
 #include <plat/vram.h>
 #include <plat/dsp.h>
 #include <plat/dma.h>
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index dbf1e03..902d2ff 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -24,7 +24,6 @@
 
 #include <plat/hardware.h>
 #include <plat/common.h>
-#include <plat/board.h>
 
 #include <plat/clock.h>
 
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index caa1f7b..c7a4c09 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -17,9 +17,6 @@
 
 #include <mach/hardware.h>
 
-#include <plat/board.h>
-
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.
  */
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1cba927..287ac37 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -23,7 +23,6 @@
 #include <asm/memblock.h>
 
 #include <plat/tc.h>
-#include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/menelaus.h>
 #include <plat/omap44xx.h>
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644
index d92f1b5..0000000
--- a/arch/arm/plat-omap/include/plat/board.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/board.h
- *
- *  Information structures for board-specific data
- *
- *  Copyright (C) 2004	Nokia Corporation
- *  Written by Juha Yrj?l? <juha.yrjola at nokia.com>
- */
-
-#ifndef _OMAP_BOARD_H
-#define _OMAP_BOARD_H
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d5..8b4e4f2 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,6 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
 
-#include <plat/board.h>
 #include <plat/omap_hwmod.h>
 
 #define OMAP15XX_NR_MMC		1
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 548a4c8..bd20588 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -5,7 +5,6 @@
 
 #include <linux/io.h>
 #include <linux/usb/musb.h>
-#include <plat/board.h>
 
 #define OMAP3_HS_USB_PORTS	3
 
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181c..d861aa7 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/sram.h>
-#include <plat/board.h>
 #include <plat/cpu.h>
 
 #include "sram.h"
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 50e08f0..5b7d420 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -33,7 +33,6 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <plat/board.h>
 #include <plat/mmc.h>
 #include <asm/gpio.h>
 #include <plat/dma.h>
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 3a09f93..f871b31 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -40,7 +40,6 @@
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
 #include <mach/hardware.h>
-#include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/cpu.h>
 
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 398a827..10ed992 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -44,8 +44,6 @@
 
 #include <plat/dma.h>
 
-#include <plat/board.h>
-
 #define DRIVER_NAME "omap2-onenand"
 
 #define ONENAND_IO_SIZE		SZ_128K
-- 
1.7.8.6



From festevam at gmail.com  Tue Aug 28 19:22:45 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 28 Aug 2012 20:22:45 -0300
Subject: [PATCH] ARM: imx27-phytec-phycore: Fix I2C EEPROM address
Message-ID: <1346196165-5024-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Fix I2C EEPROM address as per 24c32 datasheet.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boot/dts/imx27-phytec-phycore.dts |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60..2acc86c 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -49,7 +49,7 @@
 			i2c at 1001d000 {
 				clock-frequency = <400000>;
 				status = "okay";
-				at24 at 4c {
+				at24 at 52 {
 					compatible = "at,24c32";
 					pagesize = <32>;
 					reg = <0x52>;
-- 
1.7.9.5



From kgene.kim at samsung.com  Tue Aug 28 19:30:45 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:30:45 -0700
Subject: [PATCH 1/2] ARM: S3C64XX: Update configuration for WM5102 module
 on Cragganmore
In-Reply-To: <20120823152031.GH7995@opensource.wolfsonmicro.com>
References: <1344535549-4371-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <0db901cd76b4$7daf1730$790d4590$%kim@samsung.com>
 <20120810100713.GH24328@opensource.wolfsonmicro.com>
 <0eff01cd777f$4c9d1f90$e5d75eb0$%kim@samsung.com>
 <20120813122359.GA13446@opensource.wolfsonmicro.com>
 <1d5901cd8114$023550f0$069ff2d0$%kim@samsung.com>
 <20120823152031.GH7995@opensource.wolfsonmicro.com>
Message-ID: <503D54A5.8010003@samsung.com>

On 08/23/12 08:20, Mark Brown wrote:
> On Thu, Aug 23, 2012 at 06:45:19PM +0900, Kukjin Kim wrote:
>
>> Yeah, actually SoC defconfig in mainline doesn't cover _real_ requirements
>> for (mass) product. But I think, it's time we need to sort out the
>> defconfigs so that we could use them efficiently on product. BTW, if
>> enabling board in defconfig, at least, unexpected build breakages could be
>> detected by testing defconfig before merge for mainline...
>
> Right, sure.  I guess the main thing I'm saying here is that I don't
> mind what happens here, it's certainly no problem for me turn them on in
> the build if that's what people wants.
>
Hmm...I want? :)

--->

From: Kukjin Kim <kgene.kim at samsung.com>
Subject: [PATCH] ARM: s3c6400_defconfig: enable more boards in defconfig

This enables all of s3c64xx boards in the s3c6400_defconfig.
In this time, MINI6410, REAL6410, and WLF_CRAGG_6410 are
added in the defconfig.

Cc: Darius Augulis <augulis.darius at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
  arch/arm/configs/s3c6400_defconfig |    3 +++
  1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/s3c6400_defconfig 
b/arch/arm/configs/s3c6400_defconfig
index ba6a515..3a186d6 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -9,11 +9,14 @@ CONFIG_ARCH_S3C64XX=y
  CONFIG_S3C_BOOT_ERROR_RESET=y
  CONFIG_MACH_SMDK6400=y
  CONFIG_MACH_ANW6410=y
+CONFIG_MACH_MINI6410=y
+CONFIG_MACH_REAL6410=y
  CONFIG_MACH_SMDK6410=y
  CONFIG_MACH_NCP=y
  CONFIG_MACH_HMT=y
  CONFIG_MACH_SMARTQ5=y
  CONFIG_MACH_SMARTQ7=y
+CONFIG_MACH_WLF_CRAGG_6410=y
  CONFIG_CPU_32v6K=y
  CONFIG_AEABI=y
  CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc 
initrd=0x51000000,6M ramdisk_size=6144"
-- 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From santosh.shilimkar at ti.com  Tue Aug 28 19:38:24 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 28 Aug 2012 16:38:24 -0700
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <20120828230917.GD783@harshnoise.musicnaut.iki.fi>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
 <20120828122042.GC783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwMk68_BNc4O0M52OACUVLLGzRCQe+5mGH_40DrwAQ4KA@mail.gmail.com>
 <20120828230917.GD783@harshnoise.musicnaut.iki.fi>
Message-ID: <CAMQu2gxdXXa27yAYL4yEkBci7pAKH+FNjDWp8-Y86zxdqndO0Q@mail.gmail.com>

On Tue, Aug 28, 2012 at 4:09 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> Hi,
>
> On Tue, Aug 28, 2012 at 07:19:38AM -0700, Shilimkar, Santosh wrote:
>> Or the PPA has resized the secure area of 16K. As you have seen the issue
>> on one OMAP3 device, it makes sense to takeout that 16K from the public
>> SRAM map.
>>
>> Can you send the patch with fixed base address fir PUB SRAM ?
>
> Maybe I'm missing something, but I tried the following and now something
> else got broken:
>
>         save_secure_sram() returns 0000ff02
>
Damn. Looks like, you are running short of memory now for sram_push stuff.

Regards
Santosh


From kgene.kim at samsung.com  Tue Aug 28 19:44:47 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:44:47 -0700
Subject: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
In-Reply-To: <14029212.D3MKvQZpbq@amdc1227>
References: <4648723.rWnut7F0uJ@amdc1227> <14029212.D3MKvQZpbq@amdc1227>
Message-ID: <503D57EF.2090402@samsung.com>

On 08/28/12 03:06, Tomasz Figa wrote:
> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
> Redefine them to use the exact SoC name.
>
> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
> Joonyoung Shim, see:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>
> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
> ---
>   arch/arm/mach-exynos/include/mach/gpio.h   | 32 +++++++++++++++---------------
>   arch/arm/mach-exynos/mach-nuri.c           | 16 +++++++--------
>   arch/arm/mach-exynos/mach-origen.c         |  6 +++---
>   arch/arm/mach-exynos/mach-trats.c          |  4 ++--
>   arch/arm/mach-exynos/mach-universal_c210.c | 32 +++++++++++++++---------------
>   arch/arm/mach-exynos/setup-fimc.c          |  4 ++--
>   drivers/gpio/gpio-samsung.c                | 20 +++++++++----------
>   7 files changed, 57 insertions(+), 57 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index eb24f1e..21c9bf1 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -26,11 +26,11 @@
>   #define EXYNOS4_GPIO_C1_NR	(5)
>   #define EXYNOS4_GPIO_D0_NR	(4)
>   #define EXYNOS4_GPIO_D1_NR	(4)
> -#define EXYNOS4_GPIO_E0_NR	(5)
> -#define EXYNOS4_GPIO_E1_NR	(8)
> -#define EXYNOS4_GPIO_E2_NR	(6)
> -#define EXYNOS4_GPIO_E3_NR	(8)
> -#define EXYNOS4_GPIO_E4_NR	(8)
> +#define EXYNOS4210_GPIO_E0_NR	(5)
> +#define EXYNOS4210_GPIO_E1_NR	(8)
> +#define EXYNOS4210_GPIO_E2_NR	(6)
> +#define EXYNOS4210_GPIO_E3_NR	(8)
> +#define EXYNOS4210_GPIO_E4_NR	(8)

Please see my comments on Joonyoung Shim's previous patch...
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Tue Aug 28 19:56:45 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 28 Aug 2012 16:56:45 -0700
Subject: [PATCH] ARM: EXYNOS: Use non-secure MDMA1
In-Reply-To: <5886686.Vz6SVkoRWm@amdc1227>
References: <5886686.Vz6SVkoRWm@amdc1227>
Message-ID: <503D5ABD.9040801@samsung.com>

On 08/28/12 04:08, Tomasz Figa wrote:
> Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
> so use non-secure instead.
>
> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> ---
>   arch/arm/mach-exynos/dma.c              | 2 +-
>   arch/arm/mach-exynos/include/mach/map.h | 3 ++-
>   2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
> index f60b66d..8858df5 100644
> --- a/arch/arm/mach-exynos/dma.c
> +++ b/arch/arm/mach-exynos/dma.c
> @@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata = {
>   };
>
>   static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
> -	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1},&exynos_mdma1_pdata);
> +	EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1},&exynos_mdma1_pdata);
>
>   static int __init exynos_dma_init(void)
>   {
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
> exynos/include/mach/map.h
> index 51943f2..5df5910 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -89,7 +89,8 @@
>   #define EXYNOS4_PA_L2CC			0x10502000
>
>   #define EXYNOS4_PA_MDMA0		0x10810000
> -#define EXYNOS4_PA_MDMA1		0x12840000
> +#define EXYNOS4_PA_S_MDMA1		0x12840000
> +#define EXYNOS4_PA_NS_MDMA1		0x12850000
>   #define EXYNOS4_PA_PDMA0		0x12680000
>   #define EXYNOS4_PA_PDMA1		0x12690000
>   #define EXYNOS5_PA_MDMA0		0x10800000

Cc'ed Boojin Kim.

Well, just fix the address is enough like exynos5 stuff? I don't have 
any idea why we need secure mdma and non-secure mdma both here...

diff --git a/arch/arm/mach-exynos/include/mach/map.h 
b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..c941053 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,7 +89,7 @@
  #define EXYNOS4_PA_L2CC                        0x10502000

  #define EXYNOS4_PA_MDMA0		0x10810000
-#define EXYNOS4_PA_MDMA1		0x12840000
+#define EXYNOS4_PA_MDMA1		0x12850000
  #define EXYNOS4_PA_PDMA0		0x12680000
  #define EXYNOS4_PA_PDMA1		0x12690000
  #define EXYNOS5_PA_MDMA0		0x10800000
--

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From cjb at laptop.org  Tue Aug 28 19:58:51 2012
From: cjb at laptop.org (Chris Ball)
Date: Tue, 28 Aug 2012 19:58:51 -0400
Subject: [PATCH 9/9] ARM: OMAP: remove plat/board.h file
In-Reply-To: <1346195937-6383-10-git-send-email-grinberg@compulab.co.il> (Igor
 Grinberg's message of "Wed, 29 Aug 2012 02:18:57 +0300")
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
 <1346195937-6383-10-git-send-email-grinberg@compulab.co.il>
Message-ID: <877gsiwouc.fsf@octavius.laptop.org>

Hi,

On Tue, Aug 28 2012, Igor Grinberg wrote:
>  drivers/mmc/host/omap.c                      |    1 -
>  drivers/mmc/host/omap_hsmmc.c                |    1 -

Acked-by: Chris Ball <cjb at laptop.org>

-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From jason at lakedaemon.net  Tue Aug 28 20:02:24 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 20:02:24 -0400
Subject: arm: move plat-orion platform_data headers to the right place
In-Reply-To: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
References: <1346180349-25123-1-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <20120829000224.GN19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 08:59:01PM +0200, Thomas Petazzoni wrote:
> Hello,
> 
> plat-orion/include/plat contains a bunch of headers with platform_data
> structure definitions. Those headers should now be in
> <linux/platform_data/...>, so this patch series is moving them
> here. This impacts the MTD, USB EHCI, sound, MMC, DMA XOR drivers.
> 
> Moreover, this series takes this opportunity to move two other
> platform_data headers that were in <linux/...>. This impacts the I2C
> and Ethernet drivers.
> 
> This series has been built tested for orion5x_defconfig,
> dove_defconfig, kirkwood_defconfig and mv78x00_defconfig.
> 
> Thanks,
> 
> Thomas

Entire series applied to:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7-v2

thx,

Jason.


From kyungmin.park at samsung.com  Tue Aug 28 20:03:12 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Wed, 29 Aug 2012 09:03:12 +0900
Subject: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
In-Reply-To: <503D57EF.2090402@samsung.com>
References: <4648723.rWnut7F0uJ@amdc1227> <14029212.D3MKvQZpbq@amdc1227>
 <503D57EF.2090402@samsung.com>
Message-ID: <CAH9JG2UF6cqPcX4idYLRBHwLvs27ErtbwsjEFvMZbyfz_KNsZw@mail.gmail.com>

On 8/29/12, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/28/12 03:06, Tomasz Figa wrote:
>> The GPEx gpios are specific to Exynos4210 and do not exist on Exynos4x12.
>> Redefine them to use the exact SoC name.
>>
>> Based on "ARM: EXYYNOS: Use EXYNOS4210_GPEx instead of EXYNOS4_GPEx" by
>> Joonyoung Shim, see:
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100738.html
>>
>> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
>> ---
>>   arch/arm/mach-exynos/include/mach/gpio.h   | 32
>> +++++++++++++++---------------
>>   arch/arm/mach-exynos/mach-nuri.c           | 16 +++++++--------
>>   arch/arm/mach-exynos/mach-origen.c         |  6 +++---
>>   arch/arm/mach-exynos/mach-trats.c          |  4 ++--
>>   arch/arm/mach-exynos/mach-universal_c210.c | 32
>> +++++++++++++++---------------
>>   arch/arm/mach-exynos/setup-fimc.c          |  4 ++--
>>   drivers/gpio/gpio-samsung.c                | 20 +++++++++----------
>>   7 files changed, 57 insertions(+), 57 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h
>> b/arch/arm/mach-exynos/include/mach/gpio.h
>> index eb24f1e..21c9bf1 100644
>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>> @@ -26,11 +26,11 @@
>>   #define EXYNOS4_GPIO_C1_NR	(5)
>>   #define EXYNOS4_GPIO_D0_NR	(4)
>>   #define EXYNOS4_GPIO_D1_NR	(4)
>> -#define EXYNOS4_GPIO_E0_NR	(5)
>> -#define EXYNOS4_GPIO_E1_NR	(8)
>> -#define EXYNOS4_GPIO_E2_NR	(6)
>> -#define EXYNOS4_GPIO_E3_NR	(8)
>> -#define EXYNOS4_GPIO_E4_NR	(8)
>> +#define EXYNOS4210_GPIO_E0_NR	(5)
>> +#define EXYNOS4210_GPIO_E1_NR	(8)
>> +#define EXYNOS4210_GPIO_E2_NR	(6)
>> +#define EXYNOS4210_GPIO_E3_NR	(8)
>> +#define EXYNOS4210_GPIO_E4_NR	(8)
>
> Please see my comments on Joonyoung Shim's previous patch...
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.html

It's perference issue. some person like this style. others doesn't.
Moreever vender, System LSI, provided codes have whole different style.
It lists up whole gpios for each SoCs.

EXYNOS4210_{A0, .... Z}
EXYNOS4412_{A0, .... V4}
EXYNOS5250_{A0, .... Z}

anyway, just remain it as broken, and try to use pinctl as Thomas mentioned.

Thank you,
Kyungmin Park

>
> [...]
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From kyungmin.park at samsung.com  Tue Aug 28 20:06:05 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Wed, 29 Aug 2012 09:06:05 +0900
Subject: [PATCH] ARM: EXYNOS: Use non-secure MDMA1
In-Reply-To: <503D5ABD.9040801@samsung.com>
References: <5886686.Vz6SVkoRWm@amdc1227>
	<503D5ABD.9040801@samsung.com>
Message-ID: <CAH9JG2WSPyWMV3pUZANkQT9dbZOb83KsWzuh-x5YyibOvAh2oQ@mail.gmail.com>

On 8/29/12, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/28/12 04:08, Tomasz Figa wrote:
>> Using secure MDMA1 on TrustZone-enabled boards causes early boot crash,
>> so use non-secure instead.
>>
>> Signed-off-by: Tomasz Figa<t.figa at samsung.com>
>> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
>> ---
>>   arch/arm/mach-exynos/dma.c              | 2 +-
>>   arch/arm/mach-exynos/include/mach/map.h | 3 ++-
>>   2 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
>> index f60b66d..8858df5 100644
>> --- a/arch/arm/mach-exynos/dma.c
>> +++ b/arch/arm/mach-exynos/dma.c
>> @@ -261,7 +261,7 @@ static struct dma_pl330_platdata exynos_mdma1_pdata =
>> {
>>   };
>>
>>   static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
>> -	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1},&exynos_mdma1_pdata);
>> +	EXYNOS4_PA_NS_MDMA1, {EXYNOS4_IRQ_MDMA1},&exynos_mdma1_pdata);
>>
>>   static int __init exynos_dma_init(void)
>>   {
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-
>> exynos/include/mach/map.h
>> index 51943f2..5df5910 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -89,7 +89,8 @@
>>   #define EXYNOS4_PA_L2CC			0x10502000
>>
>>   #define EXYNOS4_PA_MDMA0		0x10810000
>> -#define EXYNOS4_PA_MDMA1		0x12840000
>> +#define EXYNOS4_PA_S_MDMA1		0x12840000
>> +#define EXYNOS4_PA_NS_MDMA1		0x12850000
>>   #define EXYNOS4_PA_PDMA0		0x12680000
>>   #define EXYNOS4_PA_PDMA1		0x12690000
>>   #define EXYNOS5_PA_MDMA0		0x10800000
>
> Cc'ed Boojin Kim.
>
> Well, just fix the address is enough like exynos5 stuff? I don't have
> any idea why we need secure mdma and non-secure mdma both here...

Did you see the datasheet and your team codes?
>
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index c72b675..c941053 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -89,7 +89,7 @@
>   #define EXYNOS4_PA_L2CC                        0x10502000
>
>   #define EXYNOS4_PA_MDMA0		0x10810000
> -#define EXYNOS4_PA_MDMA1		0x12840000
> +#define EXYNOS4_PA_MDMA1		0x12850000
>   #define EXYNOS4_PA_PDMA0		0x12680000
>   #define EXYNOS4_PA_PDMA1		0x12690000
>   #define EXYNOS5_PA_MDMA0		0x10800000
> --
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From jason at lakedaemon.net  Tue Aug 28 20:11:29 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 28 Aug 2012 20:11:29 -0400
Subject: [GIT PULL] Kirkwood: board changes for v3.7
Message-ID: <20120829001129.GO19437@titan.lakedaemon.net>

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7-v2

Alan M Butler (1):
      ARM: Kirkwood: Iomega ix2-200 DT support

Arnaud Patard (3):
      ARM: Kirkwood: Describe iconnect keys in DT.
      ARM: Kirkwood: Describe iconnect nand in DT.
      ARM: Kirkwood: fix Makefile.boot

Jason Cooper (5):
      ARM: Kirkwood: board-dockstar: use linux/platform_data/mvsdio.h instead of plat/mvsdio.h   
      ARM: Kirkwood: use linux/platform_data/mv643xx.h instead of linux/mv643xx.h
      ARM: Kirkwood: Kconfig: keep DT boards together
      ARM: Kirkwood: update defconfig
      ARM: Kirkwood: add DT boards to defconfig

Sebastian Hesselbarth (2):
      ARM: kirkwood: DT board setup for Seagate FreeAgent Dockstar
      ARM: kirkwood: DT descriptor for Seagate FreeAgent Dockstar

Thomas Petazzoni (15):
      arm: add documentation describing Marvell families of SoC
      mtd: orion_nand: remove <mach/hardware.h> include
      arm: plat-orion: use 'void __iomem *' in addr-map code
      arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option
      arm: plat-orion: make bridge_virt_base non-const to support DT use case
      arm: mvebu: add basic address decoding support to Armada 370/XP
      arm: mvebu: add address decoding controller to the DT
      sound: kirkwood: remove useless <plat/audio.h> include
      sound: kirkwood: move <plat/audio.h> to <linux/platform_data/kirkwood-audio.h>  
      usb: ehci-orion: move <plat/ehci-orion.h> to <linux/platform_data/ehci-orion.h> 
      mmc: mvsdio: move <plat/mvsdio.h> to <linux/platform_data/mvsdio.h>
      dma: mv_xor: move <plat/mv_xor.h> to <linux/platform_data/mv_xor.h>
      mtd: orion_nand: move <plat/orion_nand.h> to <linux/platform_data/orion_nand.h>
      i2c: mv643xx: move <linux/mv643xx_i2c.h> to <linux/platform_data/mv643xx_i2c.h>
      net: mv643xx_eth: move <linux/mv643xx_eth.h> to <linux/platform_data/mv643xx_eth.h>

 Documentation/arm/Marvell/README                   |  232 ++++++++++++++++++++
 arch/arm/Kconfig                                   |   13 +-
 arch/arm/boot/dts/armada-370-xp.dtsi               |    5 +
 arch/arm/boot/dts/kirkwood-dockstar.dts            |   57 +++++
 arch/arm/boot/dts/kirkwood-iconnect.dts            |   50 ++++-
 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts      |  105 +++++++++
 arch/arm/configs/kirkwood_defconfig                |   37 ++--
 arch/arm/mach-dove/addr-map.c                      |    2 +-
 arch/arm/mach-dove/cm-a510.c                       |    2 +-
 arch/arm/mach-dove/common.c                        |    2 +-
 arch/arm/mach-dove/dove-db-setup.c                 |    2 +-
 arch/arm/mach-kirkwood/Kconfig                     |   14 ++
 arch/arm/mach-kirkwood/Makefile                    |    2 +
 arch/arm/mach-kirkwood/Makefile.boot               |    5 +-
 arch/arm/mach-kirkwood/addr-map.c                  |    5 +-
 arch/arm/mach-kirkwood/board-dnskw.c               |    2 +-
 arch/arm/mach-kirkwood/board-dockstar.c            |   61 +++++
 arch/arm/mach-kirkwood/board-dreamplug.c           |    4 +-
 arch/arm/mach-kirkwood/board-dt.c                  |    8 +
 arch/arm/mach-kirkwood/board-goflexnet.c           |    4 +-
 arch/arm/mach-kirkwood/board-ib62x0.c              |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c            |   49 +----
 arch/arm/mach-kirkwood/board-iomega_ix2_200.c      |   57 +++++
 arch/arm/mach-kirkwood/board-lsxl.c                |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c               |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   12 +-
 arch/arm/mach-kirkwood/common.h                    |   12 +
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    4 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    4 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    4 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c     |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    2 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    4 +-
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c       |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    4 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    4 +-
 arch/arm/mach-kirkwood/t5325-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c               |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    4 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |    4 +-
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |    2 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |    2 +-
 arch/arm/mach-mvebu/Makefile                       |    2 +-
 arch/arm/mach-mvebu/addr-map.c                     |  134 +++++++++++
 arch/arm/mach-orion5x/addr-map.c                   |    5 +-
 arch/arm/mach-orion5x/common.c                     |    6 +-
 arch/arm/mach-orion5x/d2net-setup.c                |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    4 +-
 arch/arm/mach-orion5x/dns323-setup.c               |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |    2 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    4 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |    2 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |    2 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c              |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c               |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c               |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |    2 +-
 arch/arm/plat-orion/Makefile                       |    9 +-
 arch/arm/plat-orion/addr-map.c                     |   11 +-
 arch/arm/plat-orion/common.c                       |    8 +-
 arch/arm/plat-orion/include/plat/addr-map.h        |    4 +-
 arch/arm/plat-orion/include/plat/audio.h           |    7 -
 arch/arm/plat-orion/include/plat/common.h          |    2 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/i2c/busses/i2c-mv64xxx.c                   |    2 +-
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/net/ethernet/marvell/mv643xx_eth.c         |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 include/linux/mv643xx.h                            |    4 +-
 .../linux/platform_data}/ehci-orion.h              |    6 +-
 include/linux/platform_data/kirkwood-audio.h       |    7 +
 include/linux/{ => platform_data}/mv643xx_eth.h    |    4 +-
 include/linux/{ => platform_data}/mv643xx_i2c.h    |    4 +-
 .../plat => include/linux/platform_data}/mv_xor.h  |    6 +-
 .../plat => include/linux/platform_data}/mvsdio.h  |    6 +-
 .../linux/platform_data}/orion_nand.h              |    6 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    1 -
 sound/soc/kirkwood/kirkwood-t5325.c                |    1 -
 95 files changed, 890 insertions(+), 207 deletions(-)
 create mode 100644 Documentation/arm/Marvell/README
 create mode 100644 arch/arm/boot/dts/kirkwood-dockstar.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
 create mode 100644 arch/arm/mach-kirkwood/board-dockstar.c
 create mode 100644 arch/arm/mach-kirkwood/board-iomega_ix2_200.c
 create mode 100644 arch/arm/mach-mvebu/addr-map.c
 delete mode 100644 arch/arm/plat-orion/include/plat/audio.h
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/ehci-orion.h (78%)
 create mode 100644 include/linux/platform_data/kirkwood-audio.h
 rename include/linux/{ => platform_data}/mv643xx_eth.h (96%)
 rename include/linux/{ => platform_data}/mv643xx_i2c.h (89%)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/mv_xor.h (77%)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/mvsdio.h (77%)
 rename {arch/arm/plat-orion/include/plat => include/linux/platform_data}/orion_nand.h (82%)



From aaro.koskinen at iki.fi  Tue Aug 28 20:23:03 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Wed, 29 Aug 2012 03:23:03 +0300
Subject: [PATCH] arm: omap: ratelimit omap_l3_smx error log spam
In-Reply-To: <CAMQu2gxdXXa27yAYL4yEkBci7pAKH+FNjDWp8-Y86zxdqndO0Q@mail.gmail.com>
References: <1346101403-5882-1-git-send-email-aaro.koskinen@iki.fi>
 <CAMQu2gyEctrq_3K8W6VahMW-ODOiv7TjrBfPTkZqNGJ+0m9ozw@mail.gmail.com>
 <20120827220254.GA783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gz9HE0xEoW7gu257rpLWdCUpt7N6GQNQzWVhFb-A+69hg@mail.gmail.com>
 <20120827232613.GB783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwHp3PgB-TqPTNWcbRuXRT0wjfvF99nYqfDyWr1GiUvCg@mail.gmail.com>
 <20120828122042.GC783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gwMk68_BNc4O0M52OACUVLLGzRCQe+5mGH_40DrwAQ4KA@mail.gmail.com>
 <20120828230917.GD783@harshnoise.musicnaut.iki.fi>
 <CAMQu2gxdXXa27yAYL4yEkBci7pAKH+FNjDWp8-Y86zxdqndO0Q@mail.gmail.com>
Message-ID: <20120829002256.GE783@harshnoise.musicnaut.iki.fi>

On Tue, Aug 28, 2012 at 04:38:24PM -0700, Shilimkar, Santosh wrote:
> On Tue, Aug 28, 2012 at 4:09 PM, Aaro Koskinen <aaro.koskinen at iki.fi> wrote:
> > On Tue, Aug 28, 2012 at 07:19:38AM -0700, Shilimkar, Santosh wrote:
> >> Or the PPA has resized the secure area of 16K. As you have seen the issue
> >> on one OMAP3 device, it makes sense to takeout that 16K from the public
> >> SRAM map.
> >>
> >> Can you send the patch with fixed base address fir PUB SRAM ?
> >
> > Maybe I'm missing something, but I tried the following and now something
> > else got broken:
> >
> >         save_secure_sram() returns 0000ff02
> >
> Damn. Looks like, you are running short of memory now for sram_push stuff.

No, it's not that, because the below version works and that leaves as
little memory for the sram_push code:

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 766181c..a91e7ad 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -47,7 +47,7 @@
 #define OMAP5_SRAM_PA		0x40300000
 
 #if defined(CONFIG_ARCH_OMAP2PLUS)
-#define SRAM_BOOTLOADER_SZ	0x00
+#define SRAM_BOOTLOADER_SZ	(cpu_is_omap34xx() ? SZ_16K : 0)
 #else
 #define SRAM_BOOTLOADER_SZ	0x80
 #endif

A.


From chanho61.park at samsung.com  Tue Aug 28 21:14:53 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 10:14:53 +0900
Subject: [PATCH v3 0/4] Add support to enable ARM PMU for EXYNOS
Message-ID: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>

This patchset fixes irq numbers of ARM Performance Monitoring unit and enable it
for Perf(Performance Counter) on the exynos 4 and 5. The exynos4 and 5 use 2
more cpu cores which has its own pmu.
The exynos uses combiner-irq type for arm-pmu. Especially, the exynos4412 has 4
extra combined irq groups. So, we need to change a max combiner number.
To enable perf, we need also to implement a set_irq_affinity function about the
combiner-irq. After applying this patch, we can use the perf for the exynos
machine.

Changes from v2:
 - Convert to dt binding of exynos5250

Changes from v1:
 - Split arm-pmu init of exynos from plat-samsung
 - Correct combined irqs of exynos4412
 - Use soc_is_xxx function instead of CONFIG_XXX to identify dynamically

Chanho Park (4):
  ARM: EXYNOS: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: Correct combined IRQs for exynos4412
  ARM: EXYNOS: Enable PMUs for exynos4
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

 arch/arm/boot/dts/exynos5250.dtsi        |    6 ++
 arch/arm/mach-exynos/common.c            |  106 ++++++++++++++++++++++++++----
 arch/arm/mach-exynos/include/mach/irqs.h |   10 ++-
 arch/arm/plat-samsung/devs.c             |    2 +-
 4 files changed, 109 insertions(+), 15 deletions(-)

-- 
1.7.9.5



From chanho61.park at samsung.com  Tue Aug 28 21:14:55 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 10:14:55 +0900
Subject: [PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412
In-Reply-To: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
Message-ID: <1346202897-27306-3-git-send-email-chanho61.park@samsung.com>

This patch corrects combined IRQs for exynos4412 platform. The exynos4412 has
four extra combined irq group. Each irq is mapped to IRQ_SPI(xx). Unfortunately,
extra combined IRQs isn't sequential. So, we need to map the irq manually.

Signed-off-by: Chanho Park <chanho61.park at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/common.c            |   31 ++++++++++++++++++++++++------
 arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f194bbc..be61564 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -560,23 +560,39 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
 	.map	= combiner_irq_domain_map,
 };
 
+static unsigned int get_combiner_extra_irq(int group)
+{
+	switch (group) {
+	case 16:
+		return IRQ_SPI(107);
+	case 17:
+		return IRQ_SPI(108);
+	case 18:
+		return IRQ_SPI(48);
+	case 19:
+		return IRQ_SPI(42);
+	default:
+		return 0;
+	}
+}
+
 static void __init combiner_init(void __iomem *combiner_base,
 				 struct device_node *np)
 {
 	int i, irq, irq_base;
 	unsigned int max_nr, nr_irq;
 
+	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+					EXYNOS4_MAX_COMBINER_NR;
+
 	if (np) {
 		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 			pr_warning("%s: number of combiners not specified, "
 				"setting default as %d.\n",
-				__func__, EXYNOS4_MAX_COMBINER_NR);
-			max_nr = EXYNOS4_MAX_COMBINER_NR;
+				__func__, max_nr);
 		}
-	} else {
-		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-						EXYNOS4_MAX_COMBINER_NR;
 	}
+
 	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
 	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		irq = IRQ_SPI(i);
+		if (i < 16 || soc_is_exynos5250())
+			irq = IRQ_SPI(i);
+		else
+			irq = get_combiner_extra_irq(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..357ed7f 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -165,7 +165,7 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR		16
+#define EXYNOS4_MAX_COMBINER_NR		20
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
-- 
1.7.9.5



From chanho61.park at samsung.com  Tue Aug 28 21:14:54 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 10:14:54 +0900
Subject: [PATCH v3 1/4] ARM: EXYNOS: Add set_irq_affinity function for
 combiner_irq
In-Reply-To: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
Message-ID: <1346202897-27306-2-git-send-email-chanho61.park@samsung.com>

This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type irqs.

Signed-off-by: Chanho Park <chanho61.park at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..f194bbc 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -405,6 +405,7 @@ struct combiner_chip_data {
 	unsigned int irq_offset;
 	unsigned int irq_mask;
 	void __iomem *base;
+	unsigned int parent_irq;
 };
 
 static struct irq_domain *combiner_irq_domain;
@@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+				 const struct cpumask *mask_val, bool force)
+{
+	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
+	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
+
+	if (chip && chip->irq_set_affinity)
+		return chip->irq_set_affinity(data, mask_val, force);
+	else
+		return -EINVAL;
+}
+#endif
+
 static struct irq_chip combiner_chip = {
-	.name		= "COMBINER",
-	.irq_mask	= combiner_mask_irq,
-	.irq_unmask	= combiner_unmask_irq,
+	.name			= "COMBINER",
+	.irq_mask		= combiner_mask_irq,
+	.irq_unmask		= combiner_unmask_irq,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= combiner_set_affinity,
+#endif
 };
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 }
 
 static void __init combiner_init_one(unsigned int combiner_nr,
-				     void __iomem *base)
+				     void __iomem *base, unsigned int irq)
 {
 	combiner_data[combiner_nr].base = base;
 	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+	combiner_data[combiner_nr].parent_irq = irq;
 
 	/* Disable all interrupts */
 	__raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 		irq = IRQ_SPI(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
 #endif
+		combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
 		combiner_cascade_irq(i, irq);
 	}
 }
-- 
1.7.9.5



From chanho61.park at samsung.com  Tue Aug 28 21:14:56 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 10:14:56 +0900
Subject: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
In-Reply-To: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
Message-ID: <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>

This patch define irq numbers of ARM performance monitoring unit for exynos4.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So we need to identify each soc type using soc_is_xxx function and define the
pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.

Signed-off-by: Chanho Park <chanho61.park at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
 arch/arm/plat-samsung/devs.c             |    2 +-
 3 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index be61564..24b78bd 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -30,11 +30,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/pmu.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
 #include <mach/pmu.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
 	return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+static struct resource exynos42xx_pmu_resource[] = {
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+};
+
+static struct platform_device exynos42xx_device_pmu = {
+	.name		= "arm-pmu",
+	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
+	.resource	= exynos42xx_pmu_resource,
+};
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+static struct resource exynos44xx_pmu_resource[] = {
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+};
+
+static struct platform_device exynos44xx_device_pmu = {
+	.name		= "arm-pmu",
+	.num_resources	= ARRAY_SIZE(exynos44xx_pmu_resource),
+	.resource	= exynos44xx_pmu_resource,
+};
+#endif
+
+static int __init exynos_armpmu_init(void)
+{
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+	if (soc_is_exynos4210() || soc_is_exynos4212())
+		platform_device_register(&exynos42xx_device_pmu);
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+	if (soc_is_exynos4412())
+		platform_device_register(&exynos44xx_device_pmu);
+#endif
+
+	return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 357ed7f..5e75b19 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
 #define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU		IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
@@ -136,6 +136,11 @@
 #define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU			COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1		COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2		COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3		COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
 #define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
 #define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
 #define IRQ_TC				EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU				EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..3b44dad 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
 	DEFINE_RES_IRQ(IRQ_PMU)
 };
-- 
1.7.9.5



From chanho61.park at samsung.com  Tue Aug 28 21:14:57 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 10:14:57 +0900
Subject: [PATCH v3 4/4] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
In-Reply-To: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
Message-ID: <1346202897-27306-5-git-send-email-chanho61.park@samsung.com>

This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.

Signed-off-by: Chanho Park <chanho61.park at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..45746cbf 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -52,6 +52,12 @@
 			     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupt-parent = <&combiner>;
+		interrupts = <1 2>, <22 4>;
+	};
+
 	watchdog {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x101D0000 0x100>;
-- 
1.7.9.5



From b29396 at freescale.com  Tue Aug 28 22:00:50 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 10:00:50 +0800
Subject: [PATCH v3 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <503D4C08.8040605@wwwdotorg.org>
References: <1346145005-17961-1-git-send-email-b29396@freescale.com>
 <1346145005-17961-2-git-send-email-b29396@freescale.com>
 <503D4C08.8040605@wwwdotorg.org>
Message-ID: <20120829020049.GA29464@shlinux2.ap.freescale.net>

On Wed, Aug 29, 2012 at 06:54:00AM +0800, Stephen Warren wrote:
> On 08/28/2012 02:09 AM, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Add regmap based syscon driver.
> > This is usually used for access misc bits in registers which does not belong
> > to a specific module, for example, IMX IOMUXC GPR and ANATOP.
> > With this driver, client can use generic regmap API to access registers
> > which are registered into syscon.
> 
> > diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
> 
> > +* System Controller Registers R/W driver
> 
> I think the binding document could use some information about what a
> "syscon" actually is, especially since the compatible value is something
> generic like "syscon" rather than something with a vendor-specific
> prefix.
Yes, we'd better have it.

> How about:
> 
> A system controller node represents a register region containing a set
> of miscellaneous registers. The registers are not cohesive enough to
> represent as any specific type of device. The typical use-case is for
> some other node's driver, or platform-specific code, to acquire a
> reference to the syscon node (e.g. by phandle, node path, or search
> using a specific compatible value), interrogate the node (or associated
> OS driver) to determine the location of the registers, and access the
> registers directly.
> 
It looks very good to me.
Thanks for the help.

> > +Required properties:
> > +- compatible: Should contain "syscon".
> > +- reg: the register range can be access from syscon
> > +
> > +Examples:
> > +gpr: iomuxc-gpr at 020e0000 {
> > +	compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
> > +	reg = <0x020e0000 0x38>;
> > +};
> 
> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> 
> > +config MFD_SYSCON
> > +        bool "System Controller Register R/W Based on Regmap"
> > +        select REGMAP_MMIO
> > +        help
> > +          Select this option to enable accessing system control registers
> > +	  via regmap.
> 
> I think the indentation is off there.
> 
You're right.
Will fix it.

> > +static int __devinit syscon_probe(struct platform_device *pdev)
> ...
> > +	regcache_cache_only(syscon->regmap, false);
> 
> Isn't that the default?
> 
Correct, will remove.

> Aside from that, I don't have any particular comments on this series, so
> please consider it,
> 
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> 
Thanks a lot.

Regards
Dong Aisheng



From richard.zhao at freescale.com  Tue Aug 28 22:55:14 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 10:55:14 +0800
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <20120828145151.GJ10429@pengutronix.de>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <20120828145151.GJ10429@pengutronix.de>
Message-ID: <20120829025513.GB4011@b20223-02.ap.freescale.net>

On Tue, Aug 28, 2012 at 04:51:51PM +0200, Michael Grzeschik wrote:
> Hi,
> 
> On Tue, Aug 28, 2012 at 02:58:27PM +0800, Richard Zhao wrote:
> > i.MX usb controllers shares non-core registers, which may include
> > SoC specific controls. We take it as a usbmisc device and usbmisc
> > driver set operations needed by ci13xxx_imx driver.
> > 
> > For example, Sabrelite board has bad over-current design, we can
> > usbmisc to disable over-current detect.
> > 
> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
> >  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
> >  drivers/usb/chipidea/Makefile                      |    2 +-
> >  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
> >  drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
> >  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
> >  6 files changed, 274 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> >  create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
> >  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > index 2c29041..5778b9c 100644
> > --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > @@ -7,7 +7,10 @@ Required properties:
> >  
> >  Optional properties:
> >  - fsl,usbphy: phandler of usb phy that connects to the only one port
> > +- fsl,usbmisc: phandler of non-core register device, with one argument
> > +  that indicate usb controller index
> >  - vbus-supply: regulator for vbus
> > +- disable-over-current: disable over current detect
> >  
> >  Examples:
> >  usb at 02184000 { /* USB OTG */
> > @@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
> >  	reg = <0x02184000 0x200>;
> >  	interrupts = <0 43 0x04>;
> >  	fsl,usbphy = <&usbphy1>;
> > +	fsl,usbmisc = <&usbmisc 0>;
> > +	disable-over-current;
> >  };
> > diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> > new file mode 100644
> > index 0000000..97ce94e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> > @@ -0,0 +1,14 @@
> > +* Freescale i.MX non-core registers
> > +
> > +Required properties:
> > +- #index-cells: Cells used to descibe usb controller index. Should be <1>
> > +- compatible: Should be one of below:
> > +	"fsl,imx6q-usbmisc" for imx6q
> > +- reg: Should contain registers location and length
> > +
> > +Examples:
> > +usbmisc at 02184800 {
> > +	#index-cells = <1>;
> > +	compatible = "fsl,imx6q-usbmisc";
> > +	reg = <0x02184800 0x200>;
> > +};
> 
> i think we should have the devicetree-discuss Mailinglist in Cc: for
> that.
ccing devicetree-discuss ...

Thanks
Richard
> 
> Thanks,
> Michael
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From zhenkun44 at vip.163.com  Tue Aug 28 22:27:07 2012
From: zhenkun44 at vip.163.com (zhenkun44)
Date: Wed, 29 Aug 2012 10:27:07 +0800 (CST)
Subject: =?GBK?Q?=B1=A8=BC=DB=B1=ED(CIF=BB=F2FOB)?=
Message-ID: <4f7098d9.3006.13970341d99.Coremail.zhenkun44@vip.163.com>

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From sachin.kamat at linaro.org  Tue Aug 28 23:38:32 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed, 29 Aug 2012 09:08:32 +0530
Subject: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
In-Reply-To: <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
Message-ID: <CAK9yfHz2mQeTCY8+TopWd+KPfSDUCfsn-kSncU_Wr8_r97pJgA@mail.gmail.com>

Hi Chanho,

On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com> wrote:
> This patch define irq numbers of ARM performance monitoring unit for exynos4.
> The number of CPU cores and PMU irq numbers are vary according to soc types.
> So we need to identify each soc type using soc_is_xxx function and define the
> pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
>
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
>  arch/arm/plat-samsung/devs.c             |    2 +-
>  3 files changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index be61564..24b78bd 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -30,11 +30,13 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  #include <asm/cacheflush.h>
> +#include <asm/pmu.h>
>
>  #include <mach/regs-irq.h>
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-gpio.h>
>  #include <mach/pmu.h>
> +#include <mach/irqs.h>
>
>  #include <plat/cpu.h>
>  #include <plat/clock.h>
> @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
>         return 0;
>  }
>  arch_initcall(exynos_init_irq_eint);
> +
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +static struct resource exynos42xx_pmu_resource[] = {
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +};
> +
> +static struct platform_device exynos42xx_device_pmu = {
> +       .name           = "arm-pmu",
> +       .num_resources  = ARRAY_SIZE(exynos42xx_pmu_resource),
> +       .resource       = exynos42xx_pmu_resource,
> +};
> +#endif
> +
> +#if defined(CONFIG_SOC_EXYNOS4412)
> +static struct resource exynos44xx_pmu_resource[] = {
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
> +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
> +};
> +
> +static struct platform_device exynos44xx_device_pmu = {
> +       .name           = "arm-pmu",
> +       .num_resources  = ARRAY_SIZE(exynos44xx_pmu_resource),
> +       .resource       = exynos44xx_pmu_resource,
> +};
> +#endif
> +
> +static int __init exynos_armpmu_init(void)
> +{
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +       if (soc_is_exynos4210() || soc_is_exynos4212())
> +               platform_device_register(&exynos42xx_device_pmu);
> +#endif
> +#if defined(CONFIG_SOC_EXYNOS4412)
> +       if (soc_is_exynos4412())
> +               platform_device_register(&exynos44xx_device_pmu);
> +#endif

Do we need both compile time and run-time checks here?


> +
> +       return 0;
> +}
> +arch_initcall(exynos_armpmu_init);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 357ed7f..5e75b19 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -128,7 +128,7 @@
>  #define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
>  #define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
>  #define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
> -#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
> +#define EXYNOS4_IRQ_POWER_PMU          IRQ_SPI(110)
>  #define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
>  #define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
>  #define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
> @@ -136,6 +136,11 @@
>  #define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
>  #define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
>
> +#define EXYNOS4_IRQ_PMU                        COMBINER_IRQ(2, 2)
> +#define EXYNOS4_IRQ_PMU_CPU1           COMBINER_IRQ(3, 2)
> +#define EXYNOS4_IRQ_PMU_CPU2           COMBINER_IRQ(18, 2)
> +#define EXYNOS4_IRQ_PMU_CPU3           COMBINER_IRQ(19, 2)
> +
>  #define EXYNOS4_IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
>  #define EXYNOS4_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
>  #define EXYNOS4_IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
> @@ -230,7 +235,6 @@
>  #define IRQ_TC                         EXYNOS4_IRQ_PEN0
>
>  #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
> -#define IRQ_PMU                                EXYNOS4_IRQ_PMU
>
>  #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
>  #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index fc49f3d..3b44dad 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
>
>  /* PMU */
>
> -#ifdef CONFIG_PLAT_S5P
> +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
>  static struct resource s5p_pmu_resource[] = {
>         DEFINE_RES_IRQ(IRQ_PMU)
>  };
> --
> 1.7.9.5
>



-- 
With warm regards,
Sachin


From chanho61.park at samsung.com  Tue Aug 28 23:51:17 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Wed, 29 Aug 2012 12:51:17 +0900
Subject: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
In-Reply-To: <CAK9yfHz2mQeTCY8+TopWd+KPfSDUCfsn-kSncU_Wr8_r97pJgA@mail.gmail.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
 <CAK9yfHz2mQeTCY8+TopWd+KPfSDUCfsn-kSncU_Wr8_r97pJgA@mail.gmail.com>
Message-ID: <002501cd8599$8b67ab50$a23701f0$@samsung.com>

> -----Original Message-----
> From: Sachin Kamat [mailto:sachin.kamat at linaro.org]
> Sent: Wednesday, August 29, 2012 12:39 PM
> To: Chanho Park
> Cc: kgene.kim at samsung.com; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> will.deacon at arm.com; thomas.abraham at linaro.org; Kyungmin Park
> Subject: Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
> 
> Hi Chanho,
> 
> On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com>
> wrote:
> > This patch define irq numbers of ARM performance monitoring unit for
> exynos4.
> > The number of CPU cores and PMU irq numbers are vary according to soc
> types.
> > So we need to identify each soc type using soc_is_xxx function and
> > define the pmu irqs dynamically. In case of exynos4412, there are 4 cpu
> cores and pmus.
> >
> > Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   45
> ++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
> >  arch/arm/plat-samsung/devs.c             |    2 +-
> >  3 files changed, 52 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index be61564..24b78bd 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -30,11 +30,13 @@
> >  #include <asm/mach/map.h>
> >  #include <asm/mach/irq.h>
> >  #include <asm/cacheflush.h>
> > +#include <asm/pmu.h>
> >
> >  #include <mach/regs-irq.h>
> >  #include <mach/regs-pmu.h>
> >  #include <mach/regs-gpio.h>
> >  #include <mach/pmu.h>
> > +#include <mach/irqs.h>
> >
> >  #include <plat/cpu.h>
> >  #include <plat/clock.h>
> > @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
> >         return 0;
> >  }
> >  arch_initcall(exynos_init_irq_eint);
> > +
> > +#if defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +static struct resource exynos42xx_pmu_resource[] = {
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +};
> > +
> > +static struct platform_device exynos42xx_device_pmu = {
> > +       .name           = "arm-pmu",
> > +       .num_resources  = ARRAY_SIZE(exynos42xx_pmu_resource),
> > +       .resource       = exynos42xx_pmu_resource,
> > +};
> > +#endif
> > +
> > +#if defined(CONFIG_SOC_EXYNOS4412)
> > +static struct resource exynos44xx_pmu_resource[] = {
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
> > +       DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
> > +};
> > +
> > +static struct platform_device exynos44xx_device_pmu = {
> > +       .name           = "arm-pmu",
> > +       .num_resources  = ARRAY_SIZE(exynos44xx_pmu_resource),
> > +       .resource       = exynos44xx_pmu_resource,
> > +};
> > +#endif
> > +
> > +static int __init exynos_armpmu_init(void) { #if
> > +defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +       if (soc_is_exynos4210() || soc_is_exynos4212())
> > +               platform_device_register(&exynos42xx_device_pmu);
> > +#endif
> > +#if defined(CONFIG_SOC_EXYNOS4412)
> > +       if (soc_is_exynos4412())
> > +               platform_device_register(&exynos44xx_device_pmu);
> > +#endif
> 
> Do we need both compile time and run-time checks here?

I think we can reduce code size and avoid unnecessary comparison using compile time check if 
turn off these kernel configurations.
And runtime check is helpful when turned on all SoC types in the kernel configurations.

Best regards,
Chanho Park

> 
> 
> > +
> > +       return 0;
> > +}
> > +arch_initcall(exynos_armpmu_init);
> > diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
> > b/arch/arm/mach-exynos/include/mach/irqs.h
> > index 357ed7f..5e75b19 100644
> > --- a/arch/arm/mach-exynos/include/mach/irqs.h
> > +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> > @@ -128,7 +128,7 @@
> >  #define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
> >  #define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
> >  #define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
> > -#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
> > +#define EXYNOS4_IRQ_POWER_PMU          IRQ_SPI(110)
> >  #define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
> >  #define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
> >  #define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
> > @@ -136,6 +136,11 @@
> >  #define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
> >  #define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
> >
> > +#define EXYNOS4_IRQ_PMU                        COMBINER_IRQ(2, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU1           COMBINER_IRQ(3, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU2           COMBINER_IRQ(18, 2)
> > +#define EXYNOS4_IRQ_PMU_CPU3           COMBINER_IRQ(19, 2)
> > +
> >  #define EXYNOS4_IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
> >  #define EXYNOS4_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
> >  #define EXYNOS4_IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
> > @@ -230,7 +235,6 @@
> >  #define IRQ_TC                         EXYNOS4_IRQ_PEN0
> >
> >  #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
> > -#define IRQ_PMU                                EXYNOS4_IRQ_PMU
> >
> >  #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
> >  #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
> > diff --git a/arch/arm/plat-samsung/devs.c
> > b/arch/arm/plat-samsung/devs.c index fc49f3d..3b44dad 100644
> > --- a/arch/arm/plat-samsung/devs.c
> > +++ b/arch/arm/plat-samsung/devs.c
> > @@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
> >
> >  /* PMU */
> >
> > -#ifdef CONFIG_PLAT_S5P
> > +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
> >  static struct resource s5p_pmu_resource[] = {
> >         DEFINE_RES_IRQ(IRQ_PMU)
> >  };
> > --
> > 1.7.9.5
> >
> 
> 
> 
> --
> With warm regards,
> Sachin



From tushar.behera at linaro.org  Wed Aug 29 00:46:23 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 Aug 2012 10:16:23 +0530
Subject: [PATCH 0/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as
 DMA_PRIVATE
Message-ID: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>

DMA clients pdma0 and pdma1 are internal to the SoC and are used only
by dedicated peripherals. Since they cannot be used for generic
purpose, their capability should be set as DMA_PRIVATE.

The patches are rebased on top of v3.6-rc3.

Tushar Behera (2):
  ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
  DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE

 arch/arm/mach-exynos/dma.c |    2 ++
 drivers/dma/pl330.c        |    1 +
 2 files changed, 3 insertions(+), 0 deletions(-)

-- 
1.7.4.1



From tushar.behera at linaro.org  Wed Aug 29 00:46:24 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 Aug 2012 10:16:24 +0530
Subject: [PATCH 1/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as
 DMA_PRIVATE
In-Reply-To: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
References: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1346215585-31023-2-git-send-email-tushar.behera@linaro.org>

DMA clients pdma0 and pdma1 are internal to the SoC and are used only
by dedicated peripherals. Since they cannot be used for generic
purpose, their capability should be set as DMA_PRIVATE.

CC: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/dma.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index f60b66d..21d568b 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -303,10 +303,12 @@ static int __init exynos_dma_init(void)
 
 	dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
 	dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
+	dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
 	amba_device_register(&exynos_pdma0_device, &iomem_resource);
 
 	dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
 	dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
+	dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
 	amba_device_register(&exynos_pdma1_device, &iomem_resource);
 
 	dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
-- 
1.7.4.1



From tushar.behera at linaro.org  Wed Aug 29 00:46:25 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 Aug 2012 10:16:25 +0530
Subject: [PATCH 2/2] DMA: PL330: Set the capability of pdm0 and pdm1 as
 DMA_PRIVATE
In-Reply-To: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
References: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1346215585-31023-3-git-send-email-tushar.behera@linaro.org>

DMA clients pdma0 and pdma1 are internal to the SoC and are used only
by dedicated peripherals. Since they cannot be used for generic
purpose, their capability should be set as DMA_PRIVATE.

CC: Vinod Koul <vinod.koul at intel.com>
Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 drivers/dma/pl330.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index e4feba6..600ea5e 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2954,6 +2954,7 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
 		if (pi->pcfg.num_peri) {
 			dma_cap_set(DMA_SLAVE, pd->cap_mask);
 			dma_cap_set(DMA_CYCLIC, pd->cap_mask);
+			dma_cap_set(DMA_PRIVATE, pd->cap_mask);
 		}
 	}
 
-- 
1.7.4.1



From hdoyu at nvidia.com  Wed Aug 29 00:49:43 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 06:49:43 +0200
Subject: [PATCH 4/4] ARM: dma-mapping: Skip cache maint for invalid page
In-Reply-To: <503D3F18.7070507@samsung.com>
References: <1346154232-13299-1-git-send-email-hdoyu@nvidia.com><1346154232-13299-4-git-send-email-hdoyu@nvidia.com><503D3F18.7070507@samsung.com>
Message-ID: <20120829.074943.1208694903968924153.hdoyu@nvidia.com>

Hi Marek,

Marek Szyprowski <m.szyprowski at samsung.com> wrote @ Tue, 28 Aug 2012 23:58:48 +0200:

> Hello,
> 
> On 8/28/2012 1:43 PM, Hiroshi Doyu wrote:
> 
> > Skip cache maint for invalid page but warn it.
> >
> > Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> > ---
> >   arch/arm/mm/dma-mapping.c |    9 +++++++++
> >   1 files changed, 9 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> > index 2621282..0368702 100644
> > --- a/arch/arm/mm/dma-mapping.c
> > +++ b/arch/arm/mm/dma-mapping.c
> > @@ -1589,6 +1589,9 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
> >   	if (!iova)
> >   		return;
> >
> > +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> > +		return;
> > +
> >   	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
> >   		__dma_page_dev_to_cpu(page, offset, size, dir);
> >
> > @@ -1607,6 +1610,9 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
> >   	if (!iova)
> >   		return;
> >
> > +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> > +		return;
> > +
> >   	__dma_page_dev_to_cpu(page, offset, size, dir);
> >   }
> >
> > @@ -1621,6 +1627,9 @@ static void arm_iommu_sync_single_for_device(struct device *dev,
> >   	if (!iova)
> >   		return;
> >
> > +	if (WARN_ON(!pfn_valid(page_to_pfn(page))))
> > +		return;
> > +
> >   	__dma_page_cpu_to_dev(page, offset, size, dir);
> >   }
> 
> I really wonder what has happened in your system that you require
> such paranoid checks. All of the above functions are called on the
> scatter-list which has been first passed to dma_map_sg(). IMHO it
> makes much more sense to add a pfn_valid() check in dma_map_sg()
> and return error if the provided scatter list is not valid instead
> of these WARN_ONs.

Actually one device driver hit Oops at unmap_page() since this
function could be called directly from device drivers, and
WARN_ON(dump_stack) helped to find out which device driver did
something wrong. IIRC, the following functions can be called directly
from device drivers?

static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
				  size_t size, enum dma_data_direction dir);
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
					   size_t size,
					   enum dma_data_direction dir);
static inline void dma_sync_single_for_device(struct device *dev,
					      dma_addr_t addr, size_t size,
					      enum dma_data_direction dir);


From vbyravarasu at nvidia.com  Wed Aug 29 01:17:51 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Wed, 29 Aug 2012 10:47:51 +0530
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <503CD0A0.7080300@wwwdotorg.org>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
 <503CD0A0.7080300@wwwdotorg.org>
Message-ID: <D958900912E20642BCBC71664EFECE3E6DDE14DD7C@BGMAIL02.nvidia.com>


> -----Original Message-----
> From: Stephen Warren [mailto:swarren at wwwdotorg.org]
> Sent: Tuesday, August 28, 2012 7:37 PM
> To: Venu Byravarasu
> Cc: ccross at android.com; olof at lixom.net; linux at arm.linux.org.uk;
> stern at rowland.harvard.edu; gregkh at linuxfoundation.org; balbi at ti.com;
> linux-kernel at vger.kernel.org; linux-tegra at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-usb at vger.kernel.org
> Subject: Re: [PATCH] usb: tegra: moving phy driver into drivers directory
> 
> On 08/28/2012 02:32 AM, Venu Byravarasu wrote:
> > In order to keep up with the USB driver files organization,
> > moving USB phy driver from mach-tegra to drivers/USB directory.
> >
> > Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
> 
> > diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-
> tegra/devices.c
> 
> > -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
> > -	.reset_gpio = -1,
> > -	.clk = "cdev2",
> > -};
> > -
> >  struct tegra_ehci_platform_data tegra_ehci1_pdata = {
> >  	.operating_mode = TEGRA_USB_OTG,
> >  	.power_down_on_bus_suspend = 1,
> > @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata
> = {
> >  };
> >
> >  struct tegra_ehci_platform_data tegra_ehci2_pdata = {
> > -	.phy_config = &tegra_ehci2_ulpi_phy_config,
> > +	.phy_config = NULL,
> 
> The PHY driver checks that field isn't NULL, and fails if it is:
> 
> > struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int
> instance,
> >         void __iomem *regs, void *config, enum tegra_usb_phy_mode
> phy_mode)
> > {
> ...
> >         phy->config = config;
> >         phy->mode = phy_mode;
> >
> >         if (!phy->config) {
> >                 if (phy_is_ulpi(phy)) {
> >                         pr_err("%s: ulpi phy configuration missing", __func__);
> >                         err = -EINVAL;
> >                         goto err0;
> 
> So, this change will completely break ULPI support, which currently
> works fine. So, NAK.

My initial plan was to add support for phy interfaces one by one.
As part of that thought of UTMI only support at first and then add
ULPI and HSIC in next patches.
However as you were mentioning that it is not correct way, will
push ULPI & UTMI support at once in next patches.

> 
> I also plan on deleting devices.[ch] in kernel 3.7, and moving the USB
> platform data into board-dt-tegra20.c, since that's the only place it's
> used right now. So, this patch would conflict with that rather badly. I
> just posted the patches for that to the linux-tegra mailing list last
> night. Do you have better proposals for that? Perhaps usb_phy.c should
> set phy->config to &ulpi_default in a similar fashion to how it works
> for UTMI; that would remove some of the coupling between the changes.
> 
> BTW, in your response to Felipe, you said...
> 
> > Thanks Felipe for your comments.
> > Created a patch to separate out phy related stuff to phy.h with you as a
> reviewer.
> > Plz let me know your comments.
> 
> ... where is that patch?

Plz see https://lkml.org/lkml/2012/8/28/58 
 



From andrew at lunn.ch  Wed Aug 29 01:35:23 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 29 Aug 2012 07:35:23 +0200
Subject: [PATCH] ARM: Build dtb files in all target
Message-ID: <1346218523-15958-1-git-send-email-andrew@lunn.ch>

Tools like kisskb are good at finding build regressions in the kernel
sources. However, regressions in the DT desscriptions are not found,
because generally these build systems don't build the DT binary blobs.

Extend the ARM all target to build all enabled DTB files.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/Makefile |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..aee2b1e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -268,7 +268,7 @@ else
 KBUILD_IMAGE := zImage
 endif
 
-all:	$(KBUILD_IMAGE)
+all:	$(KBUILD_IMAGE) dtbs
 
 boot := arch/arm/boot
 
-- 
1.7.10.4



From egtvedt at samfundet.no  Wed Aug 29 01:56:25 2012
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Wed, 29 Aug 2012 07:56:25 +0200
Subject: [PATCH] clk: Make the generic clock API available by default
In-Reply-To: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <20120829055625.GA17753@samfundet.no>

Around Tue 28 Aug 2012 13:35:04 -0700 or thereabout, Mark Brown wrote:
> Rather than requiring platforms to select the generic clock API to make
> it available make the API available as a user selectable option unless the
> user either selects HAVE_CUSTOM_CLK (if they have their own implementation)
> or selects COMMON_CLK (if they depend on the generic implementation).
> 
> All current architectures that HAVE_CLK but don't use the common clock
> framework have selects of HAVE_CUSTOM_CLK added.
> 
> This allows drivers to use the generic API on platforms which have no need
> for the clock API at platform level.
> 
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
> 
> This depends on having one of the patches I've sent adding a generic
> clkdev.h added merged - Arnd was expecting to merge one of those, there
> was just the lack of clarity about the most practical Kbuild hookup.
> 
>  arch/arm/Kconfig            |   12 ++++++++++++
>  arch/avr32/Kconfig          |    1 +

For the AVR32 related changes

Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

<snipp>

-- 
mvh
Hans-Christian Egtvedt


From vsu at altlinux.ru  Wed Aug 29 02:25:34 2012
From: vsu at altlinux.ru (Sergey Vlasov)
Date: Wed, 29 Aug 2012 10:25:34 +0400
Subject: [alsa-devel] [PATCH V2 1/6] ASoC: davinci: davinci-pcm does not
 need to be a plaform_driver
In-Reply-To: <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120829062534.GB11919@newmaster.mivlgu.local>

On Mon, Aug 27, 2012 at 06:56:39PM +0530, Hebbar, Gururaja wrote:
> Same as the commit 518de86 (ASoC: tegra: register 'platform' from DAIs,
> get rid of pdev). It makes davinci-pcm not a platform_driver but helper
> to register "platform", so that the platform_device for davinci-pcm can
> be saved completely.
> 
> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> ---
> Changes from V1:
> 	- New Commit. Instanciate seudo-device (davinci-pcm) directly from DAI
> 	  driver rather than having a separate virtual-device registered
> 
> :100644 100644 c80c20a... 4b37e2a... M	sound/soc/davinci/davinci-evm.c
> :100644 100644 0a74b95... 407df72... M	sound/soc/davinci/davinci-i2s.c
> :100644 100644 6a2c54c... 34ee2f1... M	sound/soc/davinci/davinci-mcasp.c
> :100644 100644 97d77b2... 4b70828... M	sound/soc/davinci/davinci-pcm.c
> :100644 100644 c0d6c9b... 5e55164... M	sound/soc/davinci/davinci-pcm.h
> :100644 100644 f71175b... 5be65aa... M	sound/soc/davinci/davinci-sffsdr.c
> :100644 100644 da030ff... 07bde2e... M	sound/soc/davinci/davinci-vcif.c
>  sound/soc/davinci/davinci-evm.c    |   15 ++++++++-------
>  sound/soc/davinci/davinci-i2s.c    |   10 ++++++++++
>  sound/soc/davinci/davinci-mcasp.c  |   10 ++++++++++
>  sound/soc/davinci/davinci-pcm.c    |   23 ++++++-----------------
>  sound/soc/davinci/davinci-pcm.h    |    3 +++
>  sound/soc/davinci/davinci-sffsdr.c |    2 +-
>  sound/soc/davinci/davinci-vcif.c   |    8 ++++++++
>  7 files changed, 46 insertions(+), 25 deletions(-)
> 
> diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
> index c80c20a..4b37e2a 100644
> --- a/sound/soc/davinci/davinci-evm.c
> +++ b/sound/soc/davinci/davinci-evm.c
> @@ -159,7 +159,7 @@ static struct snd_soc_dai_link dm6446_evm_dai = {
>  	.cpu_dai_name = "davinci-mcbsp",
>  	.codec_dai_name = "tlv320aic3x-hifi",
>  	.codec_name = "tlv320aic3x-codec.1-001b",
> -	.platform_name = "davinci-pcm-audio",
> +	.platform_name = "davinci-mcbsp",
>  	.init = evm_aic3x_init,
>  	.ops = &evm_ops,
>  };
> @@ -170,7 +170,7 @@ static struct snd_soc_dai_link dm355_evm_dai = {
>  	.cpu_dai_name = "davinci-mcbsp.1",
>  	.codec_dai_name = "tlv320aic3x-hifi",
>  	.codec_name = "tlv320aic3x-codec.1-001b",
> -	.platform_name = "davinci-pcm-audio",
> +	.platform_name = "davinci-mcbsp.1",
>  	.init = evm_aic3x_init,
>  	.ops = &evm_ops,
>  };
> @@ -184,14 +184,15 @@ static struct snd_soc_dai_link dm365_evm_dai = {
>  	.init = evm_aic3x_init,
>  	.codec_name = "tlv320aic3x-codec.1-0018",
>  	.ops = &evm_ops,
> +	.platform_name = "davinci-mcbsp",
>  #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
>  	.name = "Voice Codec - CQ93VC",
>  	.stream_name = "CQ93",
>  	.cpu_dai_name = "davinci-vcif",
>  	.codec_dai_name = "cq93vc-hifi",
>  	.codec_name = "cq93vc-codec",
> +	.platform_name = "avinci-vcif",

Typo?
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From gururaja.hebbar at ti.com  Wed Aug 29 02:29:19 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Wed, 29 Aug 2012 06:29:19 +0000
Subject: [alsa-devel] [PATCH V2 1/6] ASoC: davinci: davinci-pcm does not
 need to be a plaform_driver
In-Reply-To: <20120829062534.GB11919@newmaster.mivlgu.local>
References: <1346074004-22172-1-git-send-email-gururaja.hebbar@ti.com>
 <1346074004-22172-2-git-send-email-gururaja.hebbar@ti.com>
 <20120829062534.GB11919@newmaster.mivlgu.local>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA6D3D0@DBDE01.ent.ti.com>

On Wed, Aug 29, 2012 at 11:55:34, Sergey Vlasov wrote:
> On Mon, Aug 27, 2012 at 06:56:39PM +0530, Hebbar, Gururaja wrote:
> > Same as the commit 518de86 (ASoC: tegra: register 'platform' from DAIs,
> > get rid of pdev). It makes davinci-pcm not a platform_driver but helper
> > to register "platform", so that the platform_device for davinci-pcm can
> > be saved completely.
> > 
> > Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> > ---
> > Changes from V1:
> > 	- New Commit. Instanciate seudo-device (davinci-pcm) directly from DAI
> > 	  driver rather than having a separate virtual-device registered
> > 
> > :100644 100644 c80c20a... 4b37e2a... M	sound/soc/davinci/davinci-evm.c
> > :100644 100644 0a74b95... 407df72... M	sound/soc/davinci/davinci-i2s.c
> > :100644 100644 6a2c54c... 34ee2f1... M	sound/soc/davinci/davinci-mcasp.c

...snip...
...snip...

> >  	.name = "Voice Codec - CQ93VC",
> >  	.stream_name = "CQ93",
> >  	.cpu_dai_name = "davinci-vcif",
> >  	.codec_dai_name = "cq93vc-hifi",
> >  	.codec_name = "cq93vc-codec",
> > +	.platform_name = "avinci-vcif",
> 
> Typo?
> 

Oops. Sorry. Will send back a corrected patch ASAP

Regards, 
Gururaja


From hdoyu at nvidia.com  Wed Aug 29 02:55:30 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:30 +0300
Subject: [RFC 0/5] ARM: dma-mapping: New dma_map_ops to control IOVA more
 precisely
Message-ID: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>

Hi,

The following APIs are needed for us to support the legacy Tegra
memory manager for devices("NvMap") with *DMA mapping API*.

New API:

 ->iova_alloc(): To allocate IOVA area.
 ->iova_alloc_at(): To allocate IOVA area at specific address.
 ->iova_free():  To free IOVA area.

 ->map_page_at(): To map page at specific IOVA.

misc:
 ->iova_get_free_total(): To return how much IOVA is available totally.
 ->iova_get_free_max():   To return the size of biggest IOVA area.

Although  NvMap itself will be replaced soon, there are cases for the
above API where we need to specify IOVA explicitly.

(1) HWAs may require the address for special purpose, like reset vector.
(2) IOVA linear mapping: ex: [RFC 5/5] ARM: dma-mapping: Introduce
    dma_map_linear_attrs() for IOVA linear map
(3) To support different heaps. To have allocation and mapping
    independently.

Some of them could be supported with creating different mappings, but
currently a device can have a single contiguous mapping, and we cannot
specifiy any address inside of a map since all IOVA alloction is done
implicitly now.

This is the revised version of:

 http://lists.linaro.org/pipermail/linaro-mm-sig/2012-May/001947.html
 http://lists.linaro.org/pipermail/linaro-mm-sig/2012-May/001948.html
 http://lists.linaro.org/pipermail/linaro-mm-sig/2012-May/001949.html

Any comment would be really appreciated.

Hiroshi Doyu (5):
  ARM: dma-mapping: New dma_map_ops->iova_get_free_{total,max}
    functions
  ARM: dma-mapping: New dma_map_ops->iova_{alloc,free}() functions
  ARM: dma-mapping: New dma_map_ops->iova_alloc*_at* function
  ARM: dma-mapping: New dma_map_ops->map_page*_at* function
  ARM: dma-mapping: Introduce dma_map_linear_attrs() for IOVA linear
    map

 arch/arm/include/asm/dma-mapping.h       |   55 +++++++++++++
 arch/arm/mm/dma-mapping.c                |  124 ++++++++++++++++++++++++++++++
 include/asm-generic/dma-mapping-common.h |   20 +++++
 include/linux/dma-mapping.h              |   14 ++++
 4 files changed, 213 insertions(+), 0 deletions(-)

-- 
1.7.5.4



From s.hauer at pengutronix.de  Wed Aug 29 03:14:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:14:58 +0200
Subject: [PATCH] ARM: imx27-phytec-phycore: Fix I2C EEPROM address
In-Reply-To: <1346196165-5024-1-git-send-email-festevam@gmail.com>
References: <1346196165-5024-1-git-send-email-festevam@gmail.com>
Message-ID: <20120829071458.GU26594@pengutronix.de>

On Tue, Aug 28, 2012 at 08:22:45PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Fix I2C EEPROM address as per 24c32 datasheet.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks

Sascha

> ---
>  arch/arm/boot/dts/imx27-phytec-phycore.dts |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> index 2b0ff60..2acc86c 100644
> --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
> +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
> @@ -49,7 +49,7 @@
>  			i2c at 1001d000 {
>  				clock-frequency = <400000>;
>  				status = "okay";
> -				at24 at 4c {
> +				at24 at 52 {
>  					compatible = "at,24c32";
>  					pagesize = <32>;
>  					reg = <0x52>;
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sboyd at codeaurora.org  Wed Aug 29 03:20:55 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 29 Aug 2012 00:20:55 -0700
Subject: [PATCH] ARM: Build dtb files in all target
In-Reply-To: <1346218523-15958-1-git-send-email-andrew@lunn.ch>
References: <1346218523-15958-1-git-send-email-andrew@lunn.ch>
Message-ID: <503DC2D7.2080107@codeaurora.org>

On 8/28/2012 10:35 PM, Andrew Lunn wrote:
> Tools like kisskb are good at finding build regressions in the kernel
> sources. However, regressions in the DT desscriptions are not found,
> because generally these build systems don't build the DT binary blobs.
>
> Extend the ARM all target to build all enabled DTB files.
>
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

You should probably put a star (*) next to the dtbs info in the help
text too.

Have you tried this in a clean tree? Also, should this only be default
true if USE_OF is true?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 29 03:21:37 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 29 Aug 2012 00:21:37 -0700
Subject: [PATCH] ARM: formalize an IPI for CPU wake-ups
In-Reply-To: <50352D82.2050509@codeaurora.org>
References: <alpine.LFD.2.02.1206111152190.23555@xanadu.home>
 <20120611155716.GA18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111241470.23555@xanadu.home>
 <20120611165115.GB18267@n2100.arm.linux.org.uk>
 <alpine.LFD.2.02.1206111307550.23555@xanadu.home>
 <4FD62DBB.8070407@codeaurora.org>
 <20120611192519.GF18267@n2100.arm.linux.org.uk>
 <4FE1FB15.3090305@codeaurora.org>
 <0e0201cd5f2f$2c2f6e60$848e4b20$%kim@samsung.com>
 <5016D03D.8010607@codeaurora.org>
 <CANqRtoQ9BCPhQPi38vK__61G2yAY=g9s17NG3LhSnrxdOYnkDg@mail.gmail.com>
 <50297B34.5090504@codeaurora.org> <50352D82.2050509@codeaurora.org>
Message-ID: <503DC301.3010705@codeaurora.org>


On 8/22/2012 12:05 PM, Stephen Boyd wrote:
> Ok, I've put it in the patch tracker.
>

Russell, what's involved in getting rid of the printk now? Can we just
shift everything down by 1 and then formalize 0 as the wakeup ipi? Or do
you want to completely remove that ipi from the stats? It's not clear to
me what we should do. Something like the following untested patch would
be a possibility.

----8<------->8------

diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 436e60b..2740c2a2 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,7 +5,7 @@
 #include <linux/threads.h>
 #include <asm/irq.h>

-#define NR_IPI 5
+#define NR_IPI 6

 typedef struct {
        unsigned int __softirq_pending;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebd8ad2..d98c37e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -51,7 +51,8 @@
 struct secondary_data secondary_data;

 enum ipi_msg_type {
-       IPI_TIMER = 2,
+       IPI_WAKEUP,
+       IPI_TIMER,
        IPI_RESCHEDULE,
        IPI_CALL_FUNC,
        IPI_CALL_FUNC_SINGLE,
@@ -347,7 +348,8 @@ void arch_send_call_function_single_ipi(int cpu)
 }

 static const char *ipi_types[NR_IPI] = {
-#define S(x,s) [x - IPI_TIMER] = s
+#define S(x,s) [x] = s
+       S(IPI_WAKEUP, "CPU wakeup interrupts"),
        S(IPI_TIMER, "Timer broadcast interrupts"),
        S(IPI_RESCHEDULE, "Rescheduling interrupts"),
        S(IPI_CALL_FUNC, "Function call interrupts"),
@@ -500,10 +502,13 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
        unsigned int cpu = smp_processor_id();
        struct pt_regs *old_regs = set_irq_regs(regs);

-       if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
-               __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
+       if (ipinr < NR_IPI)
+               __inc_irq_stat(cpu, ipi_irqs[ipinr]);

        switch (ipinr) {
+       case IPI_WAKEUP:
+               break;
+
        case IPI_TIMER:
                irq_enter();
                ipi_timer();

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Wed Aug 29 03:24:02 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 29 Aug 2012 00:24:02 -0700
Subject: [RFC/PATCH] ARM: smp: Fix cpu_up() racing with sys_reboot
In-Reply-To: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>
References: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <503DC392.4070904@codeaurora.org>

On 8/21/2012 9:03 PM, Stephen Boyd wrote:
> Nothing stops a process from hotplugging in a CPU concurrently
> with a sys_reboot() call. In such a situation we could have
> ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
> fact that the CPU is not really offline and call the
> CPU_UP_PREPARE notifier. When this happens stop_machine code will
> complain that the cpu thread already exists and BUG_ON().
>
> CPU0                      CPU1
>
> sys_reboot()
>  kernel_restart()
>   machine_restart()
>    machine_shutdown()
>     smp_send_stop()
>     ...                   ipi_cpu_stop()
>                            set_cpu_online(1, false)
>                             local_irq_disable()
>                              while(1)
>     <PREEMPT>
> cpu_up()
>  _cpu_up()
>    if (!cpu_online(1))
>     __cpu_notify(CPU_UP_PREPARE...)
>
> cpu_stop_cpu_callback()
>   BUG_ON(stopper->thread)
>
> This is easily reproducible by hotplugging in and out in a tight
> loop while also rebooting.
>
> Since the CPU is not really offline and hasn't gone through the
> proper steps to be marked as such, let's mark the CPU as inactive.
> This is just as easily testable as online and avoids any possibility
> of _cpu_up() trying to bring the CPU back online when it never was
> offline to begin with.
>
> Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
> ---
>
> Perhaps we can take the hotplug lock in the sys_reboot() case but I
> don't think that actually fixes everything. For example, in cases
> where machine_shutdown() is called from emergency_restart() we would
> have to take the hotplug lock which doesn't really seem feasible.

Any comments on this patch?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From s.hauer at pengutronix.de  Wed Aug 29 03:40:16 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:40:16 +0200
Subject: [PATCH 1/4] mtd nand mxc_nand: Use managed resources
In-Reply-To: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346226019-23560-2-git-send-email-s.hauer@pengutronix.de>

To make the error path simpler and to make subsequent patches
easier.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   70 ++++++++++++++-----------------------------
 1 file changed, 23 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 6acc790..268c0dc 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1344,8 +1344,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	int err = 0;
 
 	/* Allocate memory for MTD device structure and private data */
-	host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
-			NAND_MAX_OOBSIZE, GFP_KERNEL);
+	host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
+			NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
 	if (!host)
 		return -ENOMEM;
 
@@ -1372,26 +1372,17 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	this->read_buf = mxc_nand_read_buf;
 	this->verify_buf = mxc_nand_verify_buf;
 
-	host->clk = clk_get(&pdev->dev, "nfc");
-	if (IS_ERR(host->clk)) {
-		err = PTR_ERR(host->clk);
-		goto eclk;
-	}
-
-	clk_prepare_enable(host->clk);
-	host->clk_act = 1;
+	host->clk = devm_clk_get(&pdev->dev, "nfc");
+	if (IS_ERR(host->clk))
+		return PTR_ERR(host->clk);
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		err = -ENODEV;
-		goto eres;
-	}
+	if (!res)
+		return -ENODEV;
 
-	host->base = ioremap(res->start, resource_size(res));
-	if (!host->base) {
-		err = -ENOMEM;
-		goto eres;
-	}
+	host->base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!host->base)
+		return -ENOMEM;
 
 	host->main_area0 = host->base;
 
@@ -1399,7 +1390,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	if (err > 0)
 		err = mxcnd_probe_pdata(host);
 	if (err < 0)
-		goto eirq;
+		return err;
 
 	if (host->devtype_data->regs_offset)
 		host->regs = host->base + host->devtype_data->regs_offset;
@@ -1416,15 +1407,11 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 
 	if (host->devtype_data->needs_ip) {
 		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-		if (!res) {
-			err = -ENODEV;
-			goto eirq;
-		}
-		host->regs_ip = ioremap(res->start, resource_size(res));
-		if (!host->regs_ip) {
-			err = -ENOMEM;
-			goto eirq;
-		}
+		if (!res)
+			return -ENODEV;
+		host->regs_ip = devm_request_and_ioremap(&pdev->dev, res);
+		if (!host->regs_ip)
+			return -ENOMEM;
 	}
 
 	if (host->pdata.hw_ecc) {
@@ -1458,9 +1445,13 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	 */
 	host->devtype_data->irq_control(host, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
+			IRQF_DISABLED, DRIVER_NAME, host);
 	if (err)
-		goto eirq;
+		return err;
+
+	clk_prepare_enable(host->clk);
+	host->clk_act = 1;
 
 	/*
 	 * Now that we "own" the interrupt make sure the interrupt mask bit is
@@ -1512,15 +1503,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	return 0;
 
 escan:
-	free_irq(host->irq, host);
-eirq:
-	if (host->regs_ip)
-		iounmap(host->regs_ip);
-	iounmap(host->base);
-eres:
-	clk_put(host->clk);
-eclk:
-	kfree(host);
+	clk_disable_unprepare(host->clk);
 
 	return err;
 }
@@ -1529,16 +1512,9 @@ static int __devexit mxcnd_remove(struct platform_device *pdev)
 {
 	struct mxc_nand_host *host = platform_get_drvdata(pdev);
 
-	clk_put(host->clk);
-
 	platform_set_drvdata(pdev, NULL);
 
 	nand_release(&host->mtd);
-	free_irq(host->irq, host);
-	if (host->regs_ip)
-		iounmap(host->regs_ip);
-	iounmap(host->base);
-	kfree(host);
 
 	return 0;
 }
-- 
1.7.10.4



From s.hauer at pengutronix.de  Wed Aug 29 03:40:15 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:40:15 +0200
Subject: [PATCH resend] i.MX53 Nand support
Message-ID: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>

Hi All,

The following patches add i.MX53 and dt support to mxc_nand. This
is only a resent based on v3.6-rc3 as it seems this series slipped
through the cracks last time I posted it.

So Artem, if there are no objections, please consider applying up to
3/4, I would then take 4/4 through my tree.

Sascha

The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git tags/mtd-imx53-nand

for you to fetch changes up to 587450da74aa7db28fe0e9a9ee2a3816140fa8f4:

  ARM i.MX5: Add nand oftree support (2012-08-29 09:33:47 +0200)

----------------------------------------------------------------
Add i.MX53 and dt support to the mxc_nand driver

----------------------------------------------------------------
Sascha Hauer (4):
      mtd nand mxc_nand: Use managed resources
      mtd nand mxc_nand: swap iomem resource order
      mtd nand mxc_nand: add i.MX53 support
      ARM i.MX5: Add nand oftree support

 arch/arm/boot/dts/imx51.dtsi                  |    7 ++
 arch/arm/boot/dts/imx53.dtsi                  |    7 ++
 arch/arm/mach-imx/clk-imx51-imx53.c           |    2 +
 arch/arm/plat-mxc/devices/platform-mxc_nand.c |   11 +-
 drivers/mtd/nand/mxc_nand.c                   |  137 ++++++++++++++-----------
 5 files changed, 97 insertions(+), 67 deletions(-)


From s.hauer at pengutronix.de  Wed Aug 29 03:40:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:40:17 +0200
Subject: [PATCH 2/4] mtd nand mxc_nand: swap iomem resource order
In-Reply-To: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346226019-23560-3-git-send-email-s.hauer@pengutronix.de>

The i.MX v3 nand controller (i.MX5) needs two memory resources.
Traditionally we have the AXI resource first. For sorting in this
driver into the devicetree it feels much more natural to have the
IP resource first. This patch swaps the ordering of these two
resources.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/plat-mxc/devices/platform-mxc_nand.c |   11 ++++----
 drivers/mtd/nand/mxc_nand.c                   |   35 ++++++++++++++-----------
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 1568f39..95b75cc 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -63,10 +63,6 @@ struct platform_device *__init imx_add_mxc_nand(
 	/* AXI has to come first, that's how the mxc_nand driver expect it */
 	struct resource res[] = {
 		{
-			.start = data->axibase,
-			.end = data->axibase + SZ_16K - 1,
-			.flags = IORESOURCE_MEM,
-		}, {
 			.start = data->iobase,
 			.end = data->iobase + data->iosize - 1,
 			.flags = IORESOURCE_MEM,
@@ -74,10 +70,13 @@ struct platform_device *__init imx_add_mxc_nand(
 			.start = data->irq,
 			.end = data->irq,
 			.flags = IORESOURCE_IRQ,
+		}, {
+			.start = data->axibase,
+			.end = data->axibase + SZ_16K - 1,
+			.flags = IORESOURCE_MEM,
 		},
 	};
 	return imx_add_platform_device("mxc_nand", data->id,
-			res + !data->axibase,
-			ARRAY_SIZE(res) - !data->axibase,
+			res, ARRAY_SIZE(res) - !data->axibase,
 			pdata, sizeof(*pdata));
 }
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 268c0dc..efbc72c 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1376,7 +1376,25 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	if (IS_ERR(host->clk))
 		return PTR_ERR(host->clk);
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	err = mxcnd_probe_dt(host);
+	if (err > 0)
+		err = mxcnd_probe_pdata(host);
+	if (err < 0)
+		return err;
+
+	if (host->devtype_data->needs_ip) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (!res)
+			return -ENODEV;
+		host->regs_ip = devm_request_and_ioremap(&pdev->dev, res);
+		if (!host->regs_ip)
+			return -ENOMEM;
+
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	} else {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	}
+
 	if (!res)
 		return -ENODEV;
 
@@ -1386,12 +1404,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 
 	host->main_area0 = host->base;
 
-	err = mxcnd_probe_dt(host);
-	if (err > 0)
-		err = mxcnd_probe_pdata(host);
-	if (err < 0)
-		return err;
-
 	if (host->devtype_data->regs_offset)
 		host->regs = host->base + host->devtype_data->regs_offset;
 	host->spare0 = host->base + host->devtype_data->spare0_offset;
@@ -1405,15 +1417,6 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	this->ecc.size = 512;
 	this->ecc.layout = host->devtype_data->ecclayout_512;
 
-	if (host->devtype_data->needs_ip) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-		if (!res)
-			return -ENODEV;
-		host->regs_ip = devm_request_and_ioremap(&pdev->dev, res);
-		if (!host->regs_ip)
-			return -ENOMEM;
-	}
-
 	if (host->pdata.hw_ecc) {
 		this->ecc.calculate = mxc_nand_calculate_ecc;
 		this->ecc.hwctl = mxc_nand_enable_hwecc;
-- 
1.7.10.4



From s.hauer at pengutronix.de  Wed Aug 29 03:40:18 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:40:18 +0200
Subject: [PATCH 3/4] mtd nand mxc_nand: add i.MX53 support
In-Reply-To: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346226019-23560-4-git-send-email-s.hauer@pengutronix.de>

The only relevant change between i.MX51 and i.MX53 is that
a bitfield is shifted one bit to the left.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   48 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index efbc72c..49557c8 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -43,8 +43,8 @@
 
 #define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
 #define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
-#define nfc_is_v3_2()		(cpu_is_mx51() || cpu_is_mx53())
-#define nfc_is_v3()		nfc_is_v3_2()
+#define nfc_is_v3_2a()		cpu_is_mx51()
+#define nfc_is_v3_2b()		cpu_is_mx53()
 
 /* Addresses for NFC registers */
 #define NFC_V1_V2_BUF_SIZE		(host->regs + 0x00)
@@ -122,7 +122,7 @@
 #define NFC_V3_CONFIG2_2CMD_PHASES		(1 << 4)
 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0		(1 << 5)
 #define NFC_V3_CONFIG2_ECC_MODE_8		(1 << 6)
-#define NFC_V3_CONFIG2_PPB(x)			(((x) & 0x3) << 7)
+#define NFC_V3_CONFIG2_PPB(x, shift)		(((x) & 0x3) << shift)
 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)	(((x) & 0x3) << 12)
 #define NFC_V3_CONFIG2_INT_MSK			(1 << 15)
 #define NFC_V3_CONFIG2_ST_CMD(x)		(((x) & 0xff) << 24)
@@ -174,6 +174,7 @@ struct mxc_nand_devtype_data {
 	int spare_len;
 	int eccbytes;
 	int eccsize;
+	int ppb_shift;
 };
 
 struct mxc_nand_host {
@@ -1021,7 +1022,9 @@ static void preset_v3(struct mtd_info *mtd)
 	}
 
 	if (mtd->writesize) {
-		config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
+		config2 |= NFC_V3_CONFIG2_PPB(
+				ffs(mtd->erasesize / mtd->writesize) - 6,
+				host->devtype_data->ppb_shift);
 		host->eccsize = get_eccsize(mtd);
 		if (host->eccsize == 8)
 			config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
@@ -1234,7 +1237,7 @@ static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
 	.eccsize = 0,
 };
 
-/* v3: i.MX51, i.MX53 */
+/* v3.2a: i.MX51 */
 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
 	.preset = preset_v3,
 	.send_cmd = send_cmd_v3,
@@ -1258,6 +1261,34 @@ static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
 	.spare_len = 64,
 	.eccbytes = 0,
 	.eccsize = 0,
+	.ppb_shift = 7,
+};
+
+/* v3.2b: i.MX53 */
+static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
+	.preset = preset_v3,
+	.send_cmd = send_cmd_v3,
+	.send_addr = send_addr_v3,
+	.send_page = send_page_v3,
+	.send_read_id = send_read_id_v3,
+	.get_dev_status = get_dev_status_v3,
+	.check_int = check_int_v3,
+	.irq_control = irq_control_v3,
+	.get_ecc_status = get_ecc_status_v3,
+	.ecclayout_512 = &nandv2_hw_eccoob_smallpage,
+	.ecclayout_2k = &nandv2_hw_eccoob_largepage,
+	.ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
+	.select_chip = mxc_nand_select_chip_v1_v3,
+	.correct_data = mxc_nand_correct_data_v2_v3,
+	.irqpending_quirk = 0,
+	.needs_ip = 1,
+	.regs_offset = 0,
+	.spare0_offset = 0x1000,
+	.axi_offset = 0x1e00,
+	.spare_len = 64,
+	.eccbytes = 0,
+	.eccsize = 0,
+	.ppb_shift = 8,
 };
 
 #ifdef CONFIG_OF_MTD
@@ -1274,6 +1305,9 @@ static const struct of_device_id mxcnd_dt_ids[] = {
 	}, {
 		.compatible = "fsl,imx51-nand",
 		.data = &imx51_nand_devtype_data,
+	}, {
+		.compatible = "fsl,imx53-nand",
+		.data = &imx53_nand_devtype_data,
 	},
 	{ /* sentinel */ }
 };
@@ -1327,8 +1361,10 @@ static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
 			host->devtype_data = &imx27_nand_devtype_data;
 	} else if (nfc_is_v21()) {
 		host->devtype_data = &imx25_nand_devtype_data;
-	} else if (nfc_is_v3_2()) {
+	} else if (nfc_is_v3_2a()) {
 		host->devtype_data = &imx51_nand_devtype_data;
+	} else if (nfc_is_v3_2b()) {
+		host->devtype_data = &imx53_nand_devtype_data;
 	} else
 		BUG();
 
-- 
1.7.10.4



From heiko at sntech.de  Wed Aug 29 03:41:31 2012
From: heiko at sntech.de (Heiko =?utf-8?q?St=C3=BCbner?=)
Date: Wed, 29 Aug 2012 09:41:31 +0200
Subject: [PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <503D4FB1.1020206@samsung.com>
References: <201208282355.44268.heiko@sntech.de> <503D4FB1.1020206@samsung.com>
Message-ID: <201208290941.32071.heiko@sntech.de>

Am Mittwoch, 29. August 2012, 01:09:37 schrieb Kukjin Kim:
> On 08/28/12 14:55, Heiko St?bner wrote:
> > Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
> > via the device tree. This patch implements dt-support for the
> > s3c24xx arches.
> > 
> > The controllers contain only 3 cells, as the underlying gpio controller
> > does not support controlling the drive strength on a gpio level.
> > 
> > Tested with the gpio-keys driver on a s3c2416 based machine.
> > 
> > Signed-off-by: Heiko Stuebner<heiko at sntech.de>
> > Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>
> 
> Yeah, looks good to me...
> 
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> BTW, I'm not sure when we can support device tree for S3C24XX :-)

As you might've guessed, I'm working on it :-) .

Thanks to some engineers of yours at least the s3c2416/s3c2450 SoCs share a 
lot of components with all the newer ones and their drivers already contain 
the dt bindings - mostly thanks to Thomas I think.

So the only real hard part I need to figure out for now is, how to implement 
the interrupt bindings. Then I'll already have sdhci, rtc, watchdog, serial 
and i2c available.

And if I also manage to get the dma into dt, I'll also have the s3c64xx-spi 
available.

So, all in all, this does sound solvable :-)


Heiko


> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> > ---
> > changes since v1:
> > update bindings documentation to address SoC specific issues
> > 
> >   .../devicetree/bindings/gpio/gpio-samsung.txt      |   43 +++++++++++++
> >   drivers/gpio/gpio-samsung.c                        |   63
> >   ++++++++++++++++++++ 2 files changed, 106 insertions(+), 0
> >   deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt index
> > 5375625..f1e5dfe 100644
> > --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > +++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
> > 
> > @@ -39,3 +39,46 @@ Example:
> >   		#gpio-cells =<4>;
> >   		gpio-controller;
> >   	
> >   	};
> > 
> > +
> > +
> > +Samsung S3C24XX GPIO Controller
> > +
> > +Required properties:
> > +- compatible: Compatible property value should be
> > "samsung,s3c24xx-gpio". +
> > +- reg: Physical base address of the controller and length of memory
> > mapped +  region.
> > +
> > +- #gpio-cells: Should be 3. The syntax of the gpio specifier used by
> > client nodes +  should be the following with values derived from the SoC
> > user manual. +<[phandle of the gpio controller node]
> > +      [pin number within the gpio controller]
> > +      [mux function]
> > +      [flags and pull up/down]
> > +
> > +  Values for gpio specifier:
> > +  - Pin number: depending on the controller a number from 0 up to 15.
> > +  - Mux function: Depending on the SoC and the gpio bank the gpio can be
> > set +                  as input, output or a special function
> > +  - Flags and Pull Up/Down: the values to use differ for the individual
> > SoCs +                    example S3C2416/S3C2450:
> > +                            0 - Pull Up/Down Disabled.
> > +                            1 - Pull Down Enabled.
> > +                            2 - Pull Up Enabled.
> > +          Bit 16 (0x00010000) - Input is active low.
> > +  Consult the user manual for the correct values of Mux and Pull
> > Up/Down. +
> > +- gpio-controller: Specifies that the node is a gpio controller.
> > +- #address-cells: should be 1.
> > +- #size-cells: should be 1.
> > +
> > +Example:
> > +
> > +	gpa: gpio-controller at 56000000 {
> > +		#address-cells =<1>;
> > +		#size-cells =<1>;
> > +		compatible = "samsung,s3c24xx-gpio";
> > +		reg =<0x56000000 0x10>;
> > +		#gpio-cells =<3>;
> > +		gpio-controller;
> > +	};
> > diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> > index ba126cc..54f6663 100644
> > --- a/drivers/gpio/gpio-samsung.c
> > +++ b/drivers/gpio/gpio-samsung.c
> > @@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct
> > samsung_gpio_chip *chip)
> > 
> >   		s3c_gpiolib_track(chip);
> >   
> >   }
> > 
> > +#if defined(CONFIG_PLAT_S3C24XX)&&  defined(CONFIG_OF)
> > +static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
> > +			const struct of_phandle_args *gpiospec, u32 *flags)
> > +{
> > +	unsigned int pin;
> > +
> > +	if (WARN_ON(gc->of_gpio_n_cells<  3))
> > +		return -EINVAL;
> > +
> > +	if (WARN_ON(gpiospec->args_count<  gc->of_gpio_n_cells))
> > +		return -EINVAL;
> > +
> > +	if (gpiospec->args[0]>  gc->ngpio)
> > +		return -EINVAL;
> > +
> > +	pin = gc->base + gpiospec->args[0];
> > +
> > +	if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
> > +		pr_warn("gpio_xlate: failed to set pin function\n");
> > +	if (s3c_gpio_setpull(pin, gpiospec->args[2]&  0xffff))
> > +		pr_warn("gpio_xlate: failed to set pin pull up/down\n");
> > +
> > +	if (flags)
> > +		*flags = gpiospec->args[2]>>  16;
> > +
> > +	return gpiospec->args[0];
> > +}
> > +
> > +static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
> > +	{ .compatible = "samsung,s3c24xx-gpio", },
> > +	{}
> > +};
> > +
> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
> > samsung_gpio_chip *chip, +						 u64 base, u64 offset)
> > +{
> > +	struct gpio_chip *gc =&chip->chip;
> > +	u64 address;
> > +
> > +	if (!of_have_populated_dt())
> > +		return;
> > +
> > +	address = chip->base ? base + ((u32)chip->base&  0xfff) : base +
> > offset; +	gc->of_node = of_find_matching_node_by_address(NULL,
> > +			s3c24xx_gpio_dt_match, address);
> > +	if (!gc->of_node) {
> > +		pr_info("gpio: device tree node not found for gpio controller"
> > +			" with base address %08llx\n", address);
> > +		return;
> > +	}
> > +	gc->of_gpio_n_cells = 3;
> > +	gc->of_xlate = s3c24xx_gpio_xlate;
> > +}
> > +#elif defined(CONFIG_PLAT_S3C24XX)
> > +static __init void s3c24xx_gpiolib_attach_ofnode(struct
> > samsung_gpio_chip *chip, +						 u64 base, u64 offset)
> > +{
> > +	return;
> > +}
> > +#endif /* defined(CONFIG_PLAT_S3C24XX)&&  defined(CONFIG_OF) */
> > +
> > 
> >   static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip
> >   *chip,
> >   
> >   					     int nr_chips, void __iomem *base)
> >   
> >   {
> > 
> > @@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct
> > samsung_gpio_chip *chip,
> > 
> >   			gc->direction_output = samsung_gpiolib_2bit_output;
> >   		
> >   		samsung_gpiolib_add(chip);
> > 
> > +
> > +		s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
> > 
> >   	}
> >   
> >   }



From alexander.shishkin at linux.intel.com  Wed Aug 29 04:03:48 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 11:03:48 +0300
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <20120828090942.GX4011@b20223-02.ap.freescale.net>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
 <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828090942.GX4011@b20223-02.ap.freescale.net>
Message-ID: <87y5kyjfa3.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> On Tue, Aug 28, 2012 at 11:29:35AM +0300, Alexander Shishkin wrote:
>> Richard Zhao <richard.zhao at freescale.com> writes:
>> 
>> > States in gadget are not needed any more, set it to zero.
>> 
>> It's generally a good practice to mention in the commit message what is
>> it that you are fixing with this patch.
> It fixes the following dump if udc_start register gadget->dev but fail
> the start process:
> kobject (bf8330a0): tried to init an initialized object, something is seriously wrong.
> [<80011d90>] (dump_backtrace+0x0/0x10c) from [<804b65ac>] (dump_stack+0x18/0x1c)
> [<804b6594>] (dump_stack+0x0/0x1c) from [<80247d98>] (kobject_init+0x7c/0x9c)
> [<80247d1c>] (kobject_init+0x0/0x9c) from [<802a3870>] (device_initialize+0x28/0x70)
> [<802a3848>] (device_initialize+0x0/0x70) from [<802a4798>] (device_register+0x14/0x20)
> [<802a4784>] (device_register+0x0/0x20) from [<80359a70>] (udc_start+0x180/0x2c8)
> [<803598f0>] (udc_start+0x0/0x2c8) from [<80356e9c>] (ci_role_work+0xc8/0xec)
> [<80356dd4>] (ci_role_work+0x0/0xec) from [<8003a8a0>] (process_one_work+0x158/0x474)
> [<8003a748>] (process_one_work+0x0/0x474) from [<8003af6c>] (worker_thread+0x140/0x3b4)
> [<8003ae2c>] (worker_thread+0x0/0x3b4) from [<8003fe60>] (kthread+0x90/0x9c)
> [<8003fdd0>] (kthread+0x0/0x9c) from [<8002774c>] (do_exit+0x0/0x350)
>> 
>> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
>> > ---
>> >  drivers/usb/chipidea/udc.c |    1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
>> > index c7a032a..9fb6394 100644
>> > --- a/drivers/usb/chipidea/udc.c
>> > +++ b/drivers/usb/chipidea/udc.c
>> > @@ -1746,6 +1746,7 @@ free_pools:
>> >  	dma_pool_destroy(ci->td_pool);
>> >  free_qh_pool:
>> >  	dma_pool_destroy(ci->qh_pool);
>> > +	memset(&ci->gadget, 0, sizeof(ci->gadget));
>> 
>> I understand that you're probably hitting "kobject already initialized"
>> warning here, but I think the real problem is that this function gets
>> called twice and fails the first time. Why does that happen?
> I saw the dump at early stage of adding imx otg support, when there's
> things not ready. I think it's less important why udc_start fail,
> because no one enable imx otg before.  It's important when it fails,
> the dump shows up.

I'd prefer that whenever udc_start() fails it doesn't go unnoticed,
except probably for the cases when it fails due to transceiver not being
ready at the probe time, which needs to be handled separately.

Regards,
--
Alex


From valentin.longchamp at keymile.com  Wed Aug 29 04:04:21 2012
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Wed, 29 Aug 2012 10:04:21 +0200
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
In-Reply-To: <20120828122054.GG31704@lunn.ch>
References: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
 <20120828122054.GG31704@lunn.ch>
Message-ID: <503DCD05.5040500@keymile.com>

Hi Andrew,

On 08/28/2012 02:20 PM, Andrew Lunn wrote:
> Hi Valentin
> 
>> This is a first attempt to support the km_kirkwood reference design with
>> a device tree. This km_kirkwood design is present in many Keymile
>> products. It is based on the Marvell Bobcat SOC which integrates a
>> Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
>> is very similar to the "normal" one, but there are a few differences.
> 
> Is there a public datasheet for this device?

Unfortunately I am not aware of such a document. I have just checked on
Marvell's website and I haven't found anything. All the documents we have are
under NDA.

> 
>> diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
>> new file mode 100644
>> index 0000000..7a103db
>> --- /dev/null
>> +++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
>> @@ -0,0 +1,75 @@
>> +/*
>> + * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
>> + * Valentin Longchamp <valentin.longchamp at keymile.com>
>> + *
>> + * arch/arm/mach-kirkwood/board-km_kirkwood.c
>> + *
>> + * Keymile km_kirkwood Reference Desing Init for drivers not converted to
>> + * flattened device tree yet.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/ata_platform.h>
>> +#include <linux/mv643xx_eth.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_fdt.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/gpio.h>
>> +#include <linux/mtd/physmap.h>
>> +#include <linux/spi/flash.h>
>> +#include <linux/spi/spi.h>
>> +#include <linux/clk.h>
>> +#include <linux/clk-private.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <asm/mach/map.h>
>> +#include <mach/kirkwood.h>
>> +#include <mach/bridge-regs.h>
>> +#include <plat/mvsdio.h>
>> +#include "common.h"
>> +#include "mpp.h"
> 
> Please remove all the header files you don't need.

OK.

> 
>> +
>> +static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
>> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
>> +};
>> +
>> +static unsigned int km_kirkwood_mpp_config[] __initdata = {
>> +	MPP8_GPIO,	/* I2C SDA */
>> +	MPP9_GPIO,	/* I2C SCL */
>> +	0
>> +};
>> +
>> +void __init km_kirkwood_init(void)
>> +{
>> +	struct clk *sata_clk;
>> +	/*
>> +	 * Basic setup. Needs to be called early.
>> +	 */
>> +
>> +	kirkwood_mpp_conf(km_kirkwood_mpp_config);
>> +
>> +	/*
>> +	 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
>> +	 * SATA bits (14-15) of the Clock Gating Control Register. Since these
>> +	 * devices are also not present in this variant, their clocks get
>> +	 * disabled because unused when clk_disable_unused() gets called.
> 
> So there is no SATA at all on this SoC? Anything else missing which a
> 'normal' kirkwood has?

No SATA at all. Yes, other missing peripherals are RTC, SDIO, I2S (Audio), TDM,
TS (MPEG-2 Transport Stream).

> 
> If there a way to identify the chipset? e.g. what does 
> 
> kirkwood_pcie_id(&dev, &rev);
> 
> give? It would be better to not create the clocks at all, if we could
> determine at runtime the hardware was not there.
> 

Yeah I agree, it would be much better. However here is what is returned from the
kirkwood_pcie_id call in kirkwood_dt_init() (kirkwood_id())

> Kirkwood: MV88F6281-A0, TCLK=200000000.

To me it looks like this is the exact same ID as the usual kirkwood version so
we cannot determine this at runtime (at least not with that ID).

Valentin


From alexander.shishkin at linux.intel.com  Wed Aug 29 04:10:33 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 11:10:33 +0300
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <20120828092730.GY4011@b20223-02.ap.freescale.net>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
 <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828092730.GY4011@b20223-02.ap.freescale.net>
Message-ID: <87vcg2jeyu.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> On Tue, Aug 28, 2012 at 11:38:23AM +0300, Alexander Shishkin wrote:
>> Richard Zhao <richard.zhao at freescale.com> writes:
>> 
>> > One role failed, but the other role will possiblly still work.
>> > For example, when udc start failed, if plug in a host device,
>> > it works.
>> 
>> If you're a host device, ci->role should be HOST at this point and
>> ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
>> role detection must be fixed. If ci_role_start() fails for host, but it
>> still works when it's called again after the id pin change is detected,
>> again, the problem is elsewhere.
> The check is only for OTG device. For single role device, it just fail
> if it start the role failed.

Sorry, can you rephrase?

>> 
>> >
>> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
>> > ---
>> >  drivers/usb/chipidea/core.c |    7 +++++--
>> >  1 file changed, 5 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
>> > index 19ef324..8fd390a 100644
>> > --- a/drivers/usb/chipidea/core.c
>> > +++ b/drivers/usb/chipidea/core.c
>> > @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
>> >  	ret = ci_role_start(ci, ci->role);
>> >  	if (ret) {
>> >  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
>> > -		ret = -ENODEV;
>> > -		goto rm_wq;
>> > +		ci->role = CI_ROLE_END;
>> 
>> So are you relying on id pin interrupt for initializing the role after
>> this? Can you provide more details?
> Yes. The ID pin detect still works. My case is, gadget role failed,
> host role works. I was trying not to ruin host function.

But it shouldn't even try to start the gadget, because ci_otg_role()
should set ci->role to HOST before ci_role_start() happens.

Another question is, why does gadget start fail?

Regards,
--
Alex


From s.hauer at pengutronix.de  Wed Aug 29 04:10:20 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 10:10:20 +0200
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829081020.GX26594@pengutronix.de>

On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > i.MX usb controllers shares non-core registers, which may include
> > SoC specific controls. We take it as a usbmisc device and usbmisc
> > driver set operations needed by ci13xxx_imx driver.
> >
> > For example, Sabrelite board has bad over-current design, we can
> > usbmisc to disable over-current detect.
> 
> Why does this have to be part of the usb driver instead of SoC specific
> code? It looks like you've created a whole new device/driver
> infrastructure just to disable overcurrent for a specific board.

Richards code indeed only handles overcurrent for a specific board, but
there are more bits to configure in the longer run: power pin
polarities, ULPI/serial mode select and some more.

> 
> And the infrastructure boils down to a complex way of passing a callback
> from imx driver to another imx driver, that only works if they are
> probed in the right order. I don't see any point in doing it like this
> other than inflating the device tree tables even further.
> 
> Why can't this be part of the SoC code like it is done, for example in
> arch/arm/mach-omap2/control.c?

The settings are board specific, so there must be some way to configure
them in the devicetree.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From richard.zhao at freescale.com  Wed Aug 29 04:13:40 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 16:13:40 +0800
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829081339.GG4011@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > i.MX usb controllers shares non-core registers, which may include
> > SoC specific controls. We take it as a usbmisc device and usbmisc
> > driver set operations needed by ci13xxx_imx driver.
> >
> > For example, Sabrelite board has bad over-current design, we can
> > usbmisc to disable over-current detect.
> 
> Why does this have to be part of the usb driver instead of SoC specific
> code? It looks like you've created a whole new device/driver
> infrastructure just to disable overcurrent for a specific board.
> 
> And the infrastructure boils down to a complex way of passing a callback
> from imx driver to another imx driver, that only works if they are
> probed in the right order. I don't see any point in doing it like this
> other than inflating the device tree tables even further.
The goal is to let ci13xxx_imx can call usbmisc function at runtime.
The disable over current can be set once at boot time, but there's other
callbacks which is not yet in the mainline have to be called dynamically.

Thanks
Richard
> 
> Why can't this be part of the SoC code like it is done, for example in
> arch/arm/mach-omap2/control.c?
> 
> Regards,
> --
> Alex
> 
> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
> >  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
> >  drivers/usb/chipidea/Makefile                      |    2 +-
> >  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
> >  drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
> >  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
> >  6 files changed, 274 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> >  create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
> >  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
> >
> > diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > index 2c29041..5778b9c 100644
> > --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> > @@ -7,7 +7,10 @@ Required properties:
> >  
> >  Optional properties:
> >  - fsl,usbphy: phandler of usb phy that connects to the only one port
> > +- fsl,usbmisc: phandler of non-core register device, with one argument
> > +  that indicate usb controller index
> >  - vbus-supply: regulator for vbus
> > +- disable-over-current: disable over current detect
> >  
> >  Examples:
> >  usb at 02184000 { /* USB OTG */
> > @@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
> >  	reg = <0x02184000 0x200>;
> >  	interrupts = <0 43 0x04>;
> >  	fsl,usbphy = <&usbphy1>;
> > +	fsl,usbmisc = <&usbmisc 0>;
> > +	disable-over-current;
> >  };
> > diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> > new file mode 100644
> > index 0000000..97ce94e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> > @@ -0,0 +1,14 @@
> > +* Freescale i.MX non-core registers
> > +
> > +Required properties:
> > +- #index-cells: Cells used to descibe usb controller index. Should be <1>
> > +- compatible: Should be one of below:
> > +	"fsl,imx6q-usbmisc" for imx6q
> > +- reg: Should contain registers location and length
> > +
> > +Examples:
> > +usbmisc at 02184800 {
> > +	#index-cells = <1>;
> > +	compatible = "fsl,imx6q-usbmisc";
> > +	reg = <0x02184800 0x200>;
> > +};
> > diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
> > index 5c66d9c..57e510f 100644
> > --- a/drivers/usb/chipidea/Makefile
> > +++ b/drivers/usb/chipidea/Makefile
> > @@ -15,5 +15,5 @@ ifneq ($(CONFIG_PCI),)
> >  endif
> >  
> >  ifneq ($(CONFIG_OF_DEVICE),)
> > -	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o
> > +	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o usbmisc_imx6q.o
> >  endif
> > diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
> > index ef60d06..96ac67b 100644
> > --- a/drivers/usb/chipidea/ci13xxx_imx.c
> > +++ b/drivers/usb/chipidea/ci13xxx_imx.c
> > @@ -22,6 +22,7 @@
> >  #include <linux/regulator/consumer.h>
> >  
> >  #include "ci.h"
> > +#include "ci13xxx_imx.h"
> >  
> >  #define pdev_to_phy(pdev) \
> >  	((struct usb_phy *)platform_get_drvdata(pdev))
> > @@ -34,6 +35,55 @@ struct ci13xxx_imx_data {
> >  	struct regulator *reg_vbus;
> >  };
> >  
> > +static const struct usbmisc_ops *usbmisc_ops;
> > +
> > +/* Common functions shared by usbmisc drivers */
> > +
> > +int usbmisc_set_ops(const struct usbmisc_ops *ops)
> > +{
> > +	if (usbmisc_ops)
> > +		return -EBUSY;
> > +
> > +	usbmisc_ops = ops;
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(usbmisc_set_ops);
> > +
> > +void usbmisc_unset_ops(const struct usbmisc_ops *ops)
> > +{
> > +	usbmisc_ops = NULL;
> > +}
> > +EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
> > +
> > +int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
> > +{
> > +	struct device_node *np = dev->of_node;
> > +	struct of_phandle_args args;
> > +	int ret;
> > +
> > +	usbdev->dev = dev;
> > +
> > +	ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
> > +					0, &args);
> > +	if (ret) {
> > +		dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
> > +			ret);
> > +		memset(usbdev, 0, sizeof(*usbdev));
> > +		return ret;
> > +	}
> > +	usbdev->index = args.args[0];
> > +	of_node_put(args.np);
> > +
> > +	if (of_find_property(np, "disable-over-current", NULL))
> > +		usbdev->disable_oc = 1;
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
> > +
> > +/* End of common functions shared by usbmisc drivers*/
> > +
> >  static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
> >  	.name			= "ci13xxx_imx",
> >  	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
> > @@ -51,6 +101,10 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
> >  	struct regulator *reg_vbus;
> >  	int ret;
> >  
> > +	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
> > +		&& !usbmisc_ops)
> > +		return -EPROBE_DEFER;
> > +
> >  	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> >  	if (!data) {
> >  		dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
> > @@ -120,6 +174,16 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
> >  		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
> >  		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
> >  	}
> > +
> > +	if (usbmisc_ops && usbmisc_ops->init) {
> > +		ret = usbmisc_ops->init(&pdev->dev);
> > +		if (ret) {
> > +			dev_err(&pdev->dev,
> > +				"usbmisc init failed, ret=%d\n", ret);
> > +			goto err;
> > +		}
> > +	}
> > +
> >  	plat_ci = ci13xxx_add_device(&pdev->dev,
> >  				pdev->resource, pdev->num_resources,
> >  				&ci13xxx_imx_platdata);
> > diff --git a/drivers/usb/chipidea/ci13xxx_imx.h b/drivers/usb/chipidea/ci13xxx_imx.h
> > new file mode 100644
> > index 0000000..2e88acc
> > --- /dev/null
> > +++ b/drivers/usb/chipidea/ci13xxx_imx.h
> > @@ -0,0 +1,28 @@
> > +/*
> > + * Copyright 2012 Freescale Semiconductor, Inc.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/* Used to set SoC specific callbacks */
> > +struct usbmisc_ops {
> > +	/* It's called once when probe a usb device */
> > +	int (*init)(struct device *dev);
> > +};
> > +
> > +struct usbmisc_usb_device {
> > +	struct device *dev; /* usb controller device */
> > +	int index;
> > +
> > +	int disable_oc:1; /* over current detect disabled */
> > +};
> > +
> > +int usbmisc_set_ops(const struct usbmisc_ops *ops);
> > +void usbmisc_unset_ops(const struct usbmisc_ops *ops);
> > +int
> > +usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev);
> > diff --git a/drivers/usb/chipidea/usbmisc_imx6q.c b/drivers/usb/chipidea/usbmisc_imx6q.c
> > new file mode 100644
> > index 0000000..416e3fc
> > --- /dev/null
> > +++ b/drivers/usb/chipidea/usbmisc_imx6q.c
> > @@ -0,0 +1,162 @@
> > +/*
> > + * Copyright 2012 Freescale Semiconductor, Inc.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +
> > +#include "ci13xxx_imx.h"
> > +
> > +#define USB_DEV_MAX 4
> > +
> > +#define BM_OVER_CUR_DIS		BIT(7)
> > +
> > +struct imx6q_usbmisc {
> > +	void __iomem *base;
> > +	spinlock_t lock;
> > +	struct clk *clk;
> > +	struct usbmisc_usb_device usbdev[USB_DEV_MAX];
> > +};
> > +
> > +static struct imx6q_usbmisc *usbmisc;
> > +
> > +static struct usbmisc_usb_device *get_usbdev(struct device *dev)
> > +{
> > +	int i, ret;
> > +
> > +	for (i = 0; i < USB_DEV_MAX; i++) {
> > +		if (usbmisc->usbdev[i].dev == dev)
> > +			return &usbmisc->usbdev[i];
> > +		else if (!usbmisc->usbdev[i].dev)
> > +			break;
> > +	}
> > +
> > +	if (i >= USB_DEV_MAX)
> > +		return ERR_PTR(-EBUSY);
> > +
> > +	ret = usbmisc_get_init_data(dev, &usbmisc->usbdev[i]);
> > +	if (ret)
> > +		return ERR_PTR(ret);
> > +
> > +	return &usbmisc->usbdev[i];
> > +}
> > +
> > +static int usbmisc_imx6q_init(struct device *dev)
> > +{
> > +
> > +	struct usbmisc_usb_device *usbdev;
> > +	unsigned long flags;
> > +	u32 reg;
> > +
> > +	usbdev = get_usbdev(dev);
> > +	if (IS_ERR(usbdev))
> > +		return PTR_ERR(usbdev);
> > +
> > +	if (usbdev->disable_oc) {
> > +		spin_lock_irqsave(&usbmisc->lock, flags);
> > +		reg = readl(usbmisc->base + usbdev->index * 4);
> > +		writel(reg | BM_OVER_CUR_DIS,
> > +			usbmisc->base + usbdev->index * 4);
> > +		spin_unlock_irqrestore(&usbmisc->lock, flags);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct usbmisc_ops imx6q_usbmisc_ops = {
> > +	.init = usbmisc_imx6q_init,
> > +};
> > +
> > +static const struct of_device_id usbmisc_imx6q_dt_ids[] = {
> > +	{ .compatible = "fsl,imx6q-usbmisc"},
> > +	{ /* sentinel */ }
> > +};
> > +
> > +static int __devinit usbmisc_imx6q_probe(struct platform_device *pdev)
> > +{
> > +	struct resource	*res;
> > +	struct imx6q_usbmisc *data;
> > +	int ret;
> > +
> > +	if (usbmisc)
> > +		return -EBUSY;
> > +
> > +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> > +	if (!data)
> > +		return -ENOMEM;
> > +
> > +	spin_lock_init(&data->lock);
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	data->base = devm_request_and_ioremap(&pdev->dev, res);
> > +	if (!data->base)
> > +		return -EADDRNOTAVAIL;
> > +
> > +	data->clk = devm_clk_get(&pdev->dev, NULL);
> > +	if (IS_ERR(data->clk)) {
> > +		dev_err(&pdev->dev,
> > +			"failed to get clock, err=%ld\n", PTR_ERR(data->clk));
> > +		return PTR_ERR(data->clk);
> > +	}
> > +
> > +	ret = clk_prepare_enable(data->clk);
> > +	if (ret) {
> > +		dev_err(&pdev->dev,
> > +			"clk_prepare_enable failed, err=%d\n", ret);
> > +		return ret;
> > +	}
> > +
> > +	ret = usbmisc_set_ops(&imx6q_usbmisc_ops);
> > +	if (ret) {
> > +		clk_disable_unprepare(data->clk);
> > +		return ret;
> > +	}
> > +
> > +	usbmisc = data;
> > +
> > +	return 0;
> > +}
> > +
> > +static int __devexit usbmisc_imx6q_remove(struct platform_device *pdev)
> > +{
> > +	usbmisc_unset_ops(&imx6q_usbmisc_ops);
> > +	clk_disable_unprepare(usbmisc->clk);
> > +	return 0;
> > +}
> > +
> > +static struct platform_driver usbmisc_imx6q_driver = {
> > +	.probe = usbmisc_imx6q_probe,
> > +	.remove = __devexit_p(usbmisc_imx6q_remove),
> > +	.driver = {
> > +		.name = "usbmisc_imx6q",
> > +		.owner = THIS_MODULE,
> > +		.of_match_table = usbmisc_imx6q_dt_ids,
> > +	 },
> > +};
> > +
> > +int __init usbmisc_imx6q_drv_init(void)
> > +{
> > +	return platform_driver_register(&usbmisc_imx6q_driver);
> > +}
> > +subsys_initcall(usbmisc_imx6q_drv_init);
> > +
> > +void __exit usbmisc_imx6q_drv_exit(void)
> > +{
> > +	platform_driver_unregister(&usbmisc_imx6q_driver);
> > +}
> > +module_exit(usbmisc_imx6q_drv_exit);
> > +
> > +MODULE_ALIAS("platform:usbmisc-imx6q");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DESCRIPTION("driver for imx6q usb non-core registers");
> > +MODULE_AUTHOR("Richard Zhao <richard.zhao at freescale.com>");
> > -- 
> > 1.7.9.5
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From alexander.shishkin at linux.intel.com  Wed Aug 29 03:50:08 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 10:50:08 +0300
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
Message-ID: <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> i.MX usb controllers shares non-core registers, which may include
> SoC specific controls. We take it as a usbmisc device and usbmisc
> driver set operations needed by ci13xxx_imx driver.
>
> For example, Sabrelite board has bad over-current design, we can
> usbmisc to disable over-current detect.

Why does this have to be part of the usb driver instead of SoC specific
code? It looks like you've created a whole new device/driver
infrastructure just to disable overcurrent for a specific board.

And the infrastructure boils down to a complex way of passing a callback
from imx driver to another imx driver, that only works if they are
probed in the right order. I don't see any point in doing it like this
other than inflating the device tree tables even further.

Why can't this be part of the SoC code like it is done, for example in
arch/arm/mach-omap2/control.c?

Regards,
--
Alex

> Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  .../devicetree/bindings/usb/ci13xxx-imx.txt        |    5 +
>  .../devicetree/bindings/usb/usbmisc-imx.txt        |   14 ++
>  drivers/usb/chipidea/Makefile                      |    2 +-
>  drivers/usb/chipidea/ci13xxx_imx.c                 |   64 ++++++++
>  drivers/usb/chipidea/ci13xxx_imx.h                 |   28 ++++
>  drivers/usb/chipidea/usbmisc_imx6q.c               |  162 ++++++++++++++++++++
>  6 files changed, 274 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/usb/usbmisc-imx.txt
>  create mode 100644 drivers/usb/chipidea/ci13xxx_imx.h
>  create mode 100644 drivers/usb/chipidea/usbmisc_imx6q.c
>
> diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> index 2c29041..5778b9c 100644
> --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> +++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
> @@ -7,7 +7,10 @@ Required properties:
>  
>  Optional properties:
>  - fsl,usbphy: phandler of usb phy that connects to the only one port
> +- fsl,usbmisc: phandler of non-core register device, with one argument
> +  that indicate usb controller index
>  - vbus-supply: regulator for vbus
> +- disable-over-current: disable over current detect
>  
>  Examples:
>  usb at 02184000 { /* USB OTG */
> @@ -15,4 +18,6 @@ usb at 02184000 { /* USB OTG */
>  	reg = <0x02184000 0x200>;
>  	interrupts = <0 43 0x04>;
>  	fsl,usbphy = <&usbphy1>;
> +	fsl,usbmisc = <&usbmisc 0>;
> +	disable-over-current;
>  };
> diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> new file mode 100644
> index 0000000..97ce94e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
> @@ -0,0 +1,14 @@
> +* Freescale i.MX non-core registers
> +
> +Required properties:
> +- #index-cells: Cells used to descibe usb controller index. Should be <1>
> +- compatible: Should be one of below:
> +	"fsl,imx6q-usbmisc" for imx6q
> +- reg: Should contain registers location and length
> +
> +Examples:
> +usbmisc at 02184800 {
> +	#index-cells = <1>;
> +	compatible = "fsl,imx6q-usbmisc";
> +	reg = <0x02184800 0x200>;
> +};
> diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile
> index 5c66d9c..57e510f 100644
> --- a/drivers/usb/chipidea/Makefile
> +++ b/drivers/usb/chipidea/Makefile
> @@ -15,5 +15,5 @@ ifneq ($(CONFIG_PCI),)
>  endif
>  
>  ifneq ($(CONFIG_OF_DEVICE),)
> -	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o
> +	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_imx.o usbmisc_imx6q.o
>  endif
> diff --git a/drivers/usb/chipidea/ci13xxx_imx.c b/drivers/usb/chipidea/ci13xxx_imx.c
> index ef60d06..96ac67b 100644
> --- a/drivers/usb/chipidea/ci13xxx_imx.c
> +++ b/drivers/usb/chipidea/ci13xxx_imx.c
> @@ -22,6 +22,7 @@
>  #include <linux/regulator/consumer.h>
>  
>  #include "ci.h"
> +#include "ci13xxx_imx.h"
>  
>  #define pdev_to_phy(pdev) \
>  	((struct usb_phy *)platform_get_drvdata(pdev))
> @@ -34,6 +35,55 @@ struct ci13xxx_imx_data {
>  	struct regulator *reg_vbus;
>  };
>  
> +static const struct usbmisc_ops *usbmisc_ops;
> +
> +/* Common functions shared by usbmisc drivers */
> +
> +int usbmisc_set_ops(const struct usbmisc_ops *ops)
> +{
> +	if (usbmisc_ops)
> +		return -EBUSY;
> +
> +	usbmisc_ops = ops;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_set_ops);
> +
> +void usbmisc_unset_ops(const struct usbmisc_ops *ops)
> +{
> +	usbmisc_ops = NULL;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
> +
> +int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct of_phandle_args args;
> +	int ret;
> +
> +	usbdev->dev = dev;
> +
> +	ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
> +					0, &args);
> +	if (ret) {
> +		dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
> +			ret);
> +		memset(usbdev, 0, sizeof(*usbdev));
> +		return ret;
> +	}
> +	usbdev->index = args.args[0];
> +	of_node_put(args.np);
> +
> +	if (of_find_property(np, "disable-over-current", NULL))
> +		usbdev->disable_oc = 1;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
> +
> +/* End of common functions shared by usbmisc drivers*/
> +
>  static struct ci13xxx_platform_data ci13xxx_imx_platdata __devinitdata  = {
>  	.name			= "ci13xxx_imx",
>  	.flags			= CI13XXX_REQUIRE_TRANSCEIVER |
> @@ -51,6 +101,10 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
>  	struct regulator *reg_vbus;
>  	int ret;
>  
> +	if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
> +		&& !usbmisc_ops)
> +		return -EPROBE_DEFER;
> +
>  	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
>  	if (!data) {
>  		dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
> @@ -120,6 +174,16 @@ static int __devinit ci13xxx_imx_probe(struct platform_device *pdev)
>  		*pdev->dev.dma_mask = DMA_BIT_MASK(32);
>  		dma_set_coherent_mask(&pdev->dev, *pdev->dev.dma_mask);
>  	}
> +
> +	if (usbmisc_ops && usbmisc_ops->init) {
> +		ret = usbmisc_ops->init(&pdev->dev);
> +		if (ret) {
> +			dev_err(&pdev->dev,
> +				"usbmisc init failed, ret=%d\n", ret);
> +			goto err;
> +		}
> +	}
> +
>  	plat_ci = ci13xxx_add_device(&pdev->dev,
>  				pdev->resource, pdev->num_resources,
>  				&ci13xxx_imx_platdata);
> diff --git a/drivers/usb/chipidea/ci13xxx_imx.h b/drivers/usb/chipidea/ci13xxx_imx.h
> new file mode 100644
> index 0000000..2e88acc
> --- /dev/null
> +++ b/drivers/usb/chipidea/ci13xxx_imx.h
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/* Used to set SoC specific callbacks */
> +struct usbmisc_ops {
> +	/* It's called once when probe a usb device */
> +	int (*init)(struct device *dev);
> +};
> +
> +struct usbmisc_usb_device {
> +	struct device *dev; /* usb controller device */
> +	int index;
> +
> +	int disable_oc:1; /* over current detect disabled */
> +};
> +
> +int usbmisc_set_ops(const struct usbmisc_ops *ops);
> +void usbmisc_unset_ops(const struct usbmisc_ops *ops);
> +int
> +usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev);
> diff --git a/drivers/usb/chipidea/usbmisc_imx6q.c b/drivers/usb/chipidea/usbmisc_imx6q.c
> new file mode 100644
> index 0000000..416e3fc
> --- /dev/null
> +++ b/drivers/usb/chipidea/usbmisc_imx6q.c
> @@ -0,0 +1,162 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +
> +#include "ci13xxx_imx.h"
> +
> +#define USB_DEV_MAX 4
> +
> +#define BM_OVER_CUR_DIS		BIT(7)
> +
> +struct imx6q_usbmisc {
> +	void __iomem *base;
> +	spinlock_t lock;
> +	struct clk *clk;
> +	struct usbmisc_usb_device usbdev[USB_DEV_MAX];
> +};
> +
> +static struct imx6q_usbmisc *usbmisc;
> +
> +static struct usbmisc_usb_device *get_usbdev(struct device *dev)
> +{
> +	int i, ret;
> +
> +	for (i = 0; i < USB_DEV_MAX; i++) {
> +		if (usbmisc->usbdev[i].dev == dev)
> +			return &usbmisc->usbdev[i];
> +		else if (!usbmisc->usbdev[i].dev)
> +			break;
> +	}
> +
> +	if (i >= USB_DEV_MAX)
> +		return ERR_PTR(-EBUSY);
> +
> +	ret = usbmisc_get_init_data(dev, &usbmisc->usbdev[i]);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	return &usbmisc->usbdev[i];
> +}
> +
> +static int usbmisc_imx6q_init(struct device *dev)
> +{
> +
> +	struct usbmisc_usb_device *usbdev;
> +	unsigned long flags;
> +	u32 reg;
> +
> +	usbdev = get_usbdev(dev);
> +	if (IS_ERR(usbdev))
> +		return PTR_ERR(usbdev);
> +
> +	if (usbdev->disable_oc) {
> +		spin_lock_irqsave(&usbmisc->lock, flags);
> +		reg = readl(usbmisc->base + usbdev->index * 4);
> +		writel(reg | BM_OVER_CUR_DIS,
> +			usbmisc->base + usbdev->index * 4);
> +		spin_unlock_irqrestore(&usbmisc->lock, flags);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct usbmisc_ops imx6q_usbmisc_ops = {
> +	.init = usbmisc_imx6q_init,
> +};
> +
> +static const struct of_device_id usbmisc_imx6q_dt_ids[] = {
> +	{ .compatible = "fsl,imx6q-usbmisc"},
> +	{ /* sentinel */ }
> +};
> +
> +static int __devinit usbmisc_imx6q_probe(struct platform_device *pdev)
> +{
> +	struct resource	*res;
> +	struct imx6q_usbmisc *data;
> +	int ret;
> +
> +	if (usbmisc)
> +		return -EBUSY;
> +
> +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&data->lock);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	data->base = devm_request_and_ioremap(&pdev->dev, res);
> +	if (!data->base)
> +		return -EADDRNOTAVAIL;
> +
> +	data->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(data->clk)) {
> +		dev_err(&pdev->dev,
> +			"failed to get clock, err=%ld\n", PTR_ERR(data->clk));
> +		return PTR_ERR(data->clk);
> +	}
> +
> +	ret = clk_prepare_enable(data->clk);
> +	if (ret) {
> +		dev_err(&pdev->dev,
> +			"clk_prepare_enable failed, err=%d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = usbmisc_set_ops(&imx6q_usbmisc_ops);
> +	if (ret) {
> +		clk_disable_unprepare(data->clk);
> +		return ret;
> +	}
> +
> +	usbmisc = data;
> +
> +	return 0;
> +}
> +
> +static int __devexit usbmisc_imx6q_remove(struct platform_device *pdev)
> +{
> +	usbmisc_unset_ops(&imx6q_usbmisc_ops);
> +	clk_disable_unprepare(usbmisc->clk);
> +	return 0;
> +}
> +
> +static struct platform_driver usbmisc_imx6q_driver = {
> +	.probe = usbmisc_imx6q_probe,
> +	.remove = __devexit_p(usbmisc_imx6q_remove),
> +	.driver = {
> +		.name = "usbmisc_imx6q",
> +		.owner = THIS_MODULE,
> +		.of_match_table = usbmisc_imx6q_dt_ids,
> +	 },
> +};
> +
> +int __init usbmisc_imx6q_drv_init(void)
> +{
> +	return platform_driver_register(&usbmisc_imx6q_driver);
> +}
> +subsys_initcall(usbmisc_imx6q_drv_init);
> +
> +void __exit usbmisc_imx6q_drv_exit(void)
> +{
> +	platform_driver_unregister(&usbmisc_imx6q_driver);
> +}
> +module_exit(usbmisc_imx6q_drv_exit);
> +
> +MODULE_ALIAS("platform:usbmisc-imx6q");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("driver for imx6q usb non-core registers");
> +MODULE_AUTHOR("Richard Zhao <richard.zhao at freescale.com>");
> -- 
> 1.7.9.5


From s.hauer at pengutronix.de  Wed Aug 29 03:41:22 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:41:22 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <5035F84E.3000901@antcom.de>
References: <5035F84E.3000901@antcom.de>
Message-ID: <20120829074122.GV26594@pengutronix.de>

Hi Roland,

On Thu, Aug 23, 2012 at 11:30:54AM +0200, Roland Stigge wrote:
> Hi,
> 
> I'd like to know about the current state of mxc_nand.c on imx53, because
> I got an error on probe() because the clock that mxc_nand is requesting
> is "nfc" but imx53 only defines the clock "mxc_nand".

The driver generally works on i.MX53, only some pieces are missing. I
just resent the corresponding series and put you on Cc.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Aug 29 03:40:19 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 09:40:19 +0200
Subject: [PATCH 4/4] ARM i.MX5: Add nand oftree support
In-Reply-To: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346226019-23560-5-git-send-email-s.hauer@pengutronix.de>

This adds snippets to the i.MX51/53 devicetrees for the nand
flash controller.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx51.dtsi        |    7 +++++++
 arch/arm/boot/dts/imx53.dtsi        |    7 +++++++
 arch/arm/mach-imx/clk-imx51-imx53.c |    2 ++
 3 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc..aaa0c0a 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -263,6 +263,13 @@
 				status = "disabled";
 			};
 
+			nand at 83fdb000 {
+				compatible = "fsl,imx51-nand";
+				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
 			ssi3: ssi at 83fe8000 {
 				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 				reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165..dc00c62 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -321,6 +321,13 @@
 				status = "disabled";
 			};
 
+			nand at 63fdb000 {
+				compatible = "fsl,imx53-nand";
+				reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
 			ssi3: ssi at 63fe8000 {
 				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 				reg = <0x63fe8000 0x4000>;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..e81f17a 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -367,6 +367,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
+	clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
 	/* set the usboh3 parent to pll2_sw */
 	clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -455,6 +456,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+	clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
 
 	/* set SDHC root clock to 200MHZ*/
 	clk_set_rate(clk[esdhc_a_podf], 200000000);
-- 
1.7.10.4



From valentin.longchamp at keymile.com  Wed Aug 29 04:15:51 2012
From: valentin.longchamp at keymile.com (Valentin Longchamp)
Date: Wed, 29 Aug 2012 10:15:51 +0200
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
In-Reply-To: <20120828172344.GE19437@titan.lakedaemon.net>
References: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
 <20120828172344.GE19437@titan.lakedaemon.net>
Message-ID: <503DCFB7.4080804@keymile.com>

On 08/28/2012 07:23 PM, Jason Cooper wrote:
> On Tue, Aug 28, 2012 at 01:56:16PM +0200, Valentin Longchamp wrote:
>> This is a first attempt to support the km_kirkwood reference design with
>> a device tree. This km_kirkwood design is present in many Keymile
>> products. It is based on the Marvell Bobcat SOC which integrates a
>> Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC
>> is very similar to the "normal" one, but there are a few differences.
>>
>> This initial support is minimal: the kernel can boot with network
>> (ge0), serial port and NAND functional.
>>
>> Signed-off-by: Valentin Longchamp <valentin.longchamp at keymile.com>
>> Cc: Holger Brunck <holger.brunck at keymile.com>
>> ---
>>  arch/arm/boot/dts/kirkwood-km_kirkwood.dts |   29 +++++++++++
>>  arch/arm/mach-kirkwood/Kconfig             |    7 +++
>>  arch/arm/mach-kirkwood/Makefile            |    1 +
>>  arch/arm/mach-kirkwood/Makefile.boot       |    1 +
>>  arch/arm/mach-kirkwood/board-dt.c          |    4 ++
>>  arch/arm/mach-kirkwood/board-km_kirkwood.c |   75 ++++++++++++++++++++++++++++
>>  arch/arm/mach-kirkwood/common.h            |    6 ++
>>  7 files changed, 123 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/kirkwood-km_kirkwood.dts
>>  create mode 100644 arch/arm/mach-kirkwood/board-km_kirkwood.c
>>
>> diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
>> new file mode 100644
>> index 0000000..60118d5
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
>> @@ -0,0 +1,29 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +	model = "Keymile Kirkwood Reference Design";
>> +	compatible = "keymile,km_kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x00000000 0x08000000>;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +	};
>> +
>> +	ocp at f1000000 {
>> +		serial at 12000 {
>> +			clock-frequency = <200000000>;
>> +			status = "ok";
>> +		};
>> +
>> +		nand at 3000000 {
>> +			status = "ok";
>> +			chip-delay = <25>;
>> +		};
> 
> Is there a partition layout for this board?
>

Well, there is one: one big UBI partition on the whole NAND chip (we then create
UBI volumes when building the initial system and dynamically create additional
ones when neeeded). But this UBI partition gets detected perfecly well without
this partition layout so I left it out.

Valentin


From dedekind1 at gmail.com  Wed Aug 29 03:56:01 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 29 Aug 2012 10:56:01 +0300
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <1345825064-9147-1-git-send-email-gcembed@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
Message-ID: <1346226961.2848.424.camel@sauron.fi.intel.com>

On Fri, 2012-08-24 at 18:17 +0200, Ga?tan Carlier wrote:
> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> Warning: The same solution needs to be applied to the boot loader and the
> flash programmer.
> 
> This is a modified version of patch sent by J?rgen Lambrecht :
> [PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block Indicator,
> and use for imx27pdk nand support.

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From richard.zhao at freescale.com  Wed Aug 29 04:22:55 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 16:22:55 +0800
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <87y5kyjfa3.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
 <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828090942.GX4011@b20223-02.ap.freescale.net>
 <87y5kyjfa3.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829082254.GH4011@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 11:03:48AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > On Tue, Aug 28, 2012 at 11:29:35AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > States in gadget are not needed any more, set it to zero.
> >> 
> >> It's generally a good practice to mention in the commit message what is
> >> it that you are fixing with this patch.
> > It fixes the following dump if udc_start register gadget->dev but fail
> > the start process:
> > kobject (bf8330a0): tried to init an initialized object, something is seriously wrong.
> > [<80011d90>] (dump_backtrace+0x0/0x10c) from [<804b65ac>] (dump_stack+0x18/0x1c)
> > [<804b6594>] (dump_stack+0x0/0x1c) from [<80247d98>] (kobject_init+0x7c/0x9c)
> > [<80247d1c>] (kobject_init+0x0/0x9c) from [<802a3870>] (device_initialize+0x28/0x70)
> > [<802a3848>] (device_initialize+0x0/0x70) from [<802a4798>] (device_register+0x14/0x20)
> > [<802a4784>] (device_register+0x0/0x20) from [<80359a70>] (udc_start+0x180/0x2c8)
> > [<803598f0>] (udc_start+0x0/0x2c8) from [<80356e9c>] (ci_role_work+0xc8/0xec)
> > [<80356dd4>] (ci_role_work+0x0/0xec) from [<8003a8a0>] (process_one_work+0x158/0x474)
> > [<8003a748>] (process_one_work+0x0/0x474) from [<8003af6c>] (worker_thread+0x140/0x3b4)
> > [<8003ae2c>] (worker_thread+0x0/0x3b4) from [<8003fe60>] (kthread+0x90/0x9c)
> > [<8003fdd0>] (kthread+0x0/0x9c) from [<8002774c>] (do_exit+0x0/0x350)
> >> 
> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> >> > ---
> >> >  drivers/usb/chipidea/udc.c |    1 +
> >> >  1 file changed, 1 insertion(+)
> >> >
> >> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> >> > index c7a032a..9fb6394 100644
> >> > --- a/drivers/usb/chipidea/udc.c
> >> > +++ b/drivers/usb/chipidea/udc.c
> >> > @@ -1746,6 +1746,7 @@ free_pools:
> >> >  	dma_pool_destroy(ci->td_pool);
> >> >  free_qh_pool:
> >> >  	dma_pool_destroy(ci->qh_pool);
> >> > +	memset(&ci->gadget, 0, sizeof(ci->gadget));
> >> 
> >> I understand that you're probably hitting "kobject already initialized"
> >> warning here, but I think the real problem is that this function gets
> >> called twice and fails the first time. Why does that happen?
> > I saw the dump at early stage of adding imx otg support, when there's
> > things not ready. I think it's less important why udc_start fail,
> > because no one enable imx otg before.  It's important when it fails,
> > the dump shows up.
> 
> I'd prefer that whenever udc_start() fails it doesn't go unnoticed,
> except probably for the cases when it fails due to transceiver not being
> ready at the probe time, which needs to be handled separately.
Is it related to the patch? The patch is logically right that reset the
status, agree?

Thanks
Richard
> 
> Regards,
> --
> Alex
> 



From lee.jones at linaro.org  Wed Aug 29 04:31:31 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 29 Aug 2012 09:31:31 +0100
Subject: [PATCH RESEND 1/4] ARM: OMAP2+: AM33XX: Add tps65910 device tree
 data
In-Reply-To: <20120828172133.GH4534@opensource.wolfsonmicro.com>
References: <1342766789-28148-1-git-send-email-anilkumar@ti.com>
 <1342766789-28148-2-git-send-email-anilkumar@ti.com>
 <20120720095935.GQ4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13E9FA91E@DBDE01.ent.ti.com>
 <20120720113806.GW4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA01F1E@DBDE01.ent.ti.com>
 <20120723133400.GU4435@opensource.wolfsonmicro.com>
 <20120828112603.GC25786@gmail.com>
 <20120828172133.GH4534@opensource.wolfsonmicro.com>
Message-ID: <20120829083129.GB3439@gmail.com>

On Tue, Aug 28, 2012 at 10:21:33AM -0700, Mark Brown wrote:
> On Tue, Aug 28, 2012 at 12:26:07PM +0100, Lee Jones wrote:
> 
> > > > arch/arm/boot/dts/db8500.dtsi
> 
> > > I'm not actually seeing anything terribly problematic here, though the
> > > regulator-name properties should really be removed as they're fairly
> > > useless and seem to be missing the point of having the property.
> 
> > Just looking at this now. 
> 
> > The regulator-name property is used to populate constrains->name. Are
> > you sure you still want them all removed?
> 
> Yes, of course.  There's no way that a generic .dtsi used for any
> possible board could come up with a sensible value.

So how should constrains->name be populated then? Would you prefer
regulator-names moved to the .dts file(s), or something else?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From richard.zhao at freescale.com  Wed Aug 29 04:33:38 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 16:33:38 +0800
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <87vcg2jeyu.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
 <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828092730.GY4011@b20223-02.ap.freescale.net>
 <87vcg2jeyu.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829083337.GI4011@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 11:10:33AM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > On Tue, Aug 28, 2012 at 11:38:23AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > One role failed, but the other role will possiblly still work.
> >> > For example, when udc start failed, if plug in a host device,
> >> > it works.
> >> 
> >> If you're a host device, ci->role should be HOST at this point and
> >> ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
> >> role detection must be fixed. If ci_role_start() fails for host, but it
> >> still works when it's called again after the id pin change is detected,
> >> again, the problem is elsewhere.
> > The check is only for OTG device. For single role device, it just fail
> > if it start the role failed.
> 
> Sorry, can you rephrase?
> 
> >> 
> >> >
> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> >> > ---
> >> >  drivers/usb/chipidea/core.c |    7 +++++--
> >> >  1 file changed, 5 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> >> > index 19ef324..8fd390a 100644
> >> > --- a/drivers/usb/chipidea/core.c
> >> > +++ b/drivers/usb/chipidea/core.c
> >> > @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
> >> >  	ret = ci_role_start(ci, ci->role);
> >> >  	if (ret) {
> >> >  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
> >> > -		ret = -ENODEV;
> >> > -		goto rm_wq;
> >> > +		ci->role = CI_ROLE_END;
> >> 
> >> So are you relying on id pin interrupt for initializing the role after
> >> this? Can you provide more details?
> > Yes. The ID pin detect still works. My case is, gadget role failed,
> > host role works. I was trying not to ruin host function.
> 
> But it shouldn't even try to start the gadget, because ci_otg_role()
> should set ci->role to HOST before ci_role_start() happens.
It depends on ID pin. If ID pin is gadget and gadget is not support well,
ci_role_start will fail. See below example.
> 
> Another question is, why does gadget start fail?
There's one example:
If usb phy don't support otg yet, otg_set_peripheral will fail, and
then cause udc_start fail.

Thanks
Richard
> 
> Regards,
> --
> Alex
> 



From rnayak at ti.com  Wed Aug 29 04:56:13 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 29 Aug 2012 14:26:13 +0530
Subject: [PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk
Message-ID: <1346230576-20004-1-git-send-email-rnayak@ti.com>

Changes in v4:
* Added *hack* comments around clk_prepare usage in hwmod
rebased on 3.6-rc

Changes in v3:
* Fixed various checkpatch warning/errors as reported by Paul W.

Changes in v2:
* Dropped all driver clk_prepare/clk_unprepare changes, will be
  sent seperately to respective lists

This is a preparatory series for the OMAP Common Clk
conversion. They mostly add clk_prepare/clk_unprepare
in OMAP platform code. Also gets rid of omap_clk_get_by_name
and uses clk_get, and removes all direct 'struct clk'
dereferrencing and uses helpers similar to what is provided
by Common Clk.

Patches are boot tested on OMAP2430sdp, 3630 Beagle-Xm
and 4430/4460 Panda and suspend tested on 3630 Beagle-Xm
and 4430 Panda. Patches apply on 3.6-rc3.

Rajendra Nayak (3):
  ARM: omap: clk: add clk_prepare and clk_unprepare
  ARM: omap: hwmod: get rid of all omap_clk_get_by_name usage
  ARM: OMAP2+: clock: Remove all direct dereferencing of struct clk

 arch/arm/mach-omap2/board-apollon.c          |    4 +-
 arch/arm/mach-omap2/board-h4.c               |    6 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/clkt2xxx_apll.c          |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   10 ++-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c       |   20 +++---
 arch/arm/mach-omap2/clkt_clksel.c            |   91 ++++++++++++++++----------
 arch/arm/mach-omap2/clkt_dpll.c              |   26 ++++----
 arch/arm/mach-omap2/clock.c                  |   11 ++--
 arch/arm/mach-omap2/clock2420_data.c         |   17 +++++
 arch/arm/mach-omap2/clock2430_data.c         |   21 ++++++
 arch/arm/mach-omap2/clock3xxx.c              |    8 +--
 arch/arm/mach-omap2/clock3xxx_data.c         |   23 +++++++
 arch/arm/mach-omap2/clock44xx_data.c         |    6 ++
 arch/arm/mach-omap2/display.c                |    4 +-
 arch/arm/mach-omap2/dpll3xxx.c               |   48 ++++++++------
 arch/arm/mach-omap2/gpmc.c                   |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c             |   45 ++++++++++---
 arch/arm/mach-omap2/pm.c                     |    2 +-
 arch/arm/plat-omap/clock.c                   |   27 --------
 arch/arm/plat-omap/include/plat/clock.h      |    5 ++
 arch/arm/plat-omap/omap_device.c             |    6 +-
 22 files changed, 251 insertions(+), 135 deletions(-)

-- 
1.7.9.5



From rnayak at ti.com  Wed Aug 29 04:56:15 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 29 Aug 2012 14:26:15 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all omap_clk_get_by_name
 usage
In-Reply-To: <1346230576-20004-1-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
Message-ID: <1346230576-20004-3-git-send-email-rnayak@ti.com>

Moving to Common clk framework for OMAP would mean we no longer use
internal lookup mechanism like omap_clk_get_by_name().
get rid of all its usage mostly from hwmod and omap_device
code.

Also use IS_ERR_OR_NULL() for error checking.

Moving to clk_get() also means the respective platforms
need the clkdev tables updated with an entry for all clocks
used by hwmod to have clock name same as the alias.

Based on original changes from Mike Turquette.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/clock2420_data.c |   17 +++++++++++++++++
 arch/arm/mach-omap2/clock2430_data.c |   21 +++++++++++++++++++++
 arch/arm/mach-omap2/clock3xxx_data.c |   23 +++++++++++++++++++++++
 arch/arm/mach-omap2/clock44xx_data.c |    6 ++++++
 arch/arm/mach-omap2/omap_hwmod.c     |   12 ++++++------
 arch/arm/plat-omap/clock.c           |   27 ---------------------------
 arch/arm/plat-omap/omap_device.c     |    6 +++---
 7 files changed, 76 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 0027451..49da781 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"gfx_ick",	&gfx_ick,	CK_242X),
 	/* DSS domain clocks */
 	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_242X),
+	CLK(NULL,	"dss_ick",		&dss_ick,	CK_242X),
 	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_242X),
 	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_242X),
 	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_242X),
 	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_242X),
 	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_242X),
+	CLK(NULL,	"mcbsp1_ick",	&mcbsp1_ick,	CK_242X),
 	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_242X),
 	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_242X),
+	CLK(NULL,	"mcbsp2_ick",	&mcbsp2_ick,	CK_242X),
 	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_242X),
 	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_242X),
+	CLK(NULL,	"mcspi1_ick",	&mcspi1_ick,	CK_242X),
 	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_242X),
 	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_242X),
+	CLK(NULL,	"mcspi2_ick",	&mcspi2_ick,	CK_242X),
 	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_242X),
 	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_242X),
 	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_242X),
 	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_242X),
 	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_242X),
+	CLK(NULL,	"mpu_wdt_ick",		&mpu_wdt_ick,	CK_242X),
 	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_242X),
 	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_242X),
 	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_242X),
 	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_242X),
 	CLK("omap24xxcam", "fck",	&cam_fck,	CK_242X),
+	CLK(NULL,	"cam_fck",	&cam_fck,	CK_242X),
 	CLK("omap24xxcam", "ick",	&cam_ick,	CK_242X),
+	CLK(NULL,	"cam_ick",	&cam_ick,	CK_242X),
 	CLK(NULL,	"mailboxes_ick", &mailboxes_ick,	CK_242X),
 	CLK(NULL,	"wdt4_ick",	&wdt4_ick,	CK_242X),
 	CLK(NULL,	"wdt4_fck",	&wdt4_fck,	CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_242X),
 	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_242X),
 	CLK("mmci-omap.0", "ick",	&mmc_ick,	CK_242X),
+	CLK(NULL,	"mmc_ick",	&mmc_ick,	CK_242X),
 	CLK("mmci-omap.0", "fck",	&mmc_fck,	CK_242X),
+	CLK(NULL,	"mmc_fck",	&mmc_fck,	CK_242X),
 	CLK(NULL,	"fac_ick",	&fac_ick,	CK_242X),
 	CLK(NULL,	"fac_fck",	&fac_fck,	CK_242X),
 	CLK(NULL,	"eac_ick",	&eac_ick,	CK_242X),
 	CLK(NULL,	"eac_fck",	&eac_fck,	CK_242X),
 	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_242X),
+	CLK(NULL,	"hdq_ick",	&hdq_ick,	CK_242X),
 	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_242X),
+	CLK(NULL,	"hdq_fck",	&hdq_fck,	CK_242X),
 	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_242X),
+	CLK(NULL,	"i2c1_ick",	&i2c1_ick,	CK_242X),
 	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_242X),
 	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_242X),
+	CLK(NULL,	"i2c2_ick",	&i2c2_ick,	CK_242X),
 	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_242X),
 	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),
 	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),
@@ -1892,8 +1906,11 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"vlynq_fck",	&vlynq_fck,	CK_242X),
 	CLK(NULL,	"des_ick",	&des_ick,	CK_242X),
 	CLK("omap-sham",	"ick",	&sha_ick,	CK_242X),
+	CLK(NULL,	"sha_ick",	&sha_ick,	CK_242X),
 	CLK("omap_rng",	"ick",		&rng_ick,	CK_242X),
+	CLK(NULL,	"rng_ick",		&rng_ick,	CK_242X),
 	CLK("omap-aes",	"ick",	&aes_ick,	CK_242X),
+	CLK(NULL,	"aes_ick",	&aes_ick,	CK_242X),
 	CLK(NULL,	"pka_ick",	&pka_ick,	CK_242X),
 	CLK(NULL,	"usb_fck",	&usb_fck,	CK_242X),
 	CLK("musb-hdrc",	"fck",	&osc_ck,	CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index cacabb0..bcf86a7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1887,6 +1887,7 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"mdm_osc_ck",	&mdm_osc_ck,	CK_243X),
 	/* DSS domain clocks */
 	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_243X),
+	CLK(NULL,	"dss_ick",		&dss_ick,	CK_243X),
 	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_243X),
 	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_243X),
 	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_243X),
@@ -1926,20 +1927,28 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_243X),
 	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_243X),
 	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_243X),
+	CLK(NULL,	"mcbsp1_ick",	&mcbsp1_ick,	CK_243X),
 	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_243X),
 	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_243X),
+	CLK(NULL,	"mcbsp2_ick",	&mcbsp2_ick,	CK_243X),
 	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_243X),
 	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_243X),
+	CLK(NULL,	"mcbsp3_ick",	&mcbsp3_ick,	CK_243X),
 	CLK(NULL,	"mcbsp3_fck",	&mcbsp3_fck,	CK_243X),
 	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_243X),
+	CLK(NULL,	"mcbsp4_ick",	&mcbsp4_ick,	CK_243X),
 	CLK(NULL,	"mcbsp4_fck",	&mcbsp4_fck,	CK_243X),
 	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_243X),
+	CLK(NULL,	"mcbsp5_ick",	&mcbsp5_ick,	CK_243X),
 	CLK(NULL,	"mcbsp5_fck",	&mcbsp5_fck,	CK_243X),
 	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_243X),
+	CLK(NULL,	"mcspi1_ick",	&mcspi1_ick,	CK_243X),
 	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_243X),
 	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_243X),
+	CLK(NULL,	"mcspi2_ick",	&mcspi2_ick,	CK_243X),
 	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_243X),
 	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_243X),
+	CLK(NULL,	"mcspi3_ick",	&mcspi3_ick,	CK_243X),
 	CLK(NULL,	"mcspi3_fck",	&mcspi3_fck,	CK_243X),
 	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_243X),
 	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_243X),
@@ -1950,13 +1959,16 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_243X),
 	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_243X),
 	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_243X),
+	CLK(NULL,	"mpu_wdt_ick",	&mpu_wdt_ick,	CK_243X),
 	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_243X),
 	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_243X),
 	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_243X),
 	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_243X),
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_243X),
 	CLK("omap24xxcam", "fck",	&cam_fck,	CK_243X),
+	CLK(NULL,	"cam_fck",	&cam_fck,	CK_243X),
 	CLK("omap24xxcam", "ick",	&cam_ick,	CK_243X),
+	CLK(NULL,	"cam_ick",	&cam_ick,	CK_243X),
 	CLK(NULL,	"mailboxes_ick", &mailboxes_ick,	CK_243X),
 	CLK(NULL,	"wdt4_ick",	&wdt4_ick,	CK_243X),
 	CLK(NULL,	"wdt4_fck",	&wdt4_fck,	CK_243X),
@@ -1965,10 +1977,14 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"fac_ick",	&fac_ick,	CK_243X),
 	CLK(NULL,	"fac_fck",	&fac_fck,	CK_243X),
 	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_243X),
+	CLK(NULL,	"hdq_ick",	&hdq_ick,	CK_243X),
 	CLK("omap_hdq.1", "fck",	&hdq_fck,	CK_243X),
+	CLK(NULL,	"hdq_fck",	&hdq_fck,	CK_243X),
 	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_243X),
+	CLK(NULL,	"i2c1_ick",	&i2c1_ick,	CK_243X),
 	CLK(NULL,	"i2chs1_fck",	&i2chs1_fck,	CK_243X),
 	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_243X),
+	CLK(NULL,	"i2c2_ick",	&i2c2_ick,	CK_243X),
 	CLK(NULL,	"i2chs2_fck",	&i2chs2_fck,	CK_243X),
 	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_243X),
 	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_243X),
@@ -1981,15 +1997,20 @@ static struct omap_clk omap2430_clks[] = {
 	CLK(NULL,	"pka_ick",	&pka_ick,	CK_243X),
 	CLK(NULL,	"usb_fck",	&usb_fck,	CK_243X),
 	CLK("musb-omap2430",	"ick",	&usbhs_ick,	CK_243X),
+	CLK(NULL,	"usbhs_ick",	&usbhs_ick,	CK_243X),
 	CLK("omap_hsmmc.0", "ick",	&mmchs1_ick,	CK_243X),
+	CLK(NULL,	"mmchs1_ick",	&mmchs1_ick,	CK_243X),
 	CLK(NULL,	"mmchs1_fck",	&mmchs1_fck,	CK_243X),
 	CLK("omap_hsmmc.1", "ick",	&mmchs2_ick,	CK_243X),
+	CLK(NULL,	"mmchs2_ick",	&mmchs2_ick,	CK_243X),
 	CLK(NULL,	"mmchs2_fck",	&mmchs2_fck,	CK_243X),
 	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_243X),
 	CLK(NULL,	"gpio5_fck",	&gpio5_fck,	CK_243X),
 	CLK(NULL,	"mdm_intc_ick",	&mdm_intc_ick,	CK_243X),
 	CLK("omap_hsmmc.0", "mmchsdb_fck",	&mmchsdb1_fck,	CK_243X),
+	CLK(NULL,	"mmchsdb1_fck",		&mmchsdb1_fck,	CK_243X),
 	CLK("omap_hsmmc.1", "mmchsdb_fck",	&mmchsdb2_fck,	CK_243X),
+	CLK(NULL,	"mmchsdb2_fck",		&mmchsdb2_fck,	CK_243X),
 	CLK(NULL,	"timer_32k_ck",  &func_32k_ck,   CK_243X),
 	CLK(NULL,	"timer_sys_ck",	&sys_ck,	CK_243X),
 	CLK(NULL,	"timer_ext_ck",	&alt_ck,	CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9a..405f4b6 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3247,6 +3247,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"dpll4_x2_ck",	&dpll4_x2_ck,	CK_3XXX),
 	CLK(NULL,	"omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
 	CLK(NULL,	"omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+	CLK(NULL,	"omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_3XXX),
 	CLK(NULL,	"omap_96m_fck",	&omap_96m_fck,	CK_3XXX),
 	CLK(NULL,	"cm_96m_fck",	&cm_96m_fck,	CK_3XXX),
 	CLK(NULL,	"omap_54m_fck",	&omap_54m_fck,	CK_3XXX),
@@ -3314,6 +3315,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"fshostusb_fck", &fshostusb_fck, CK_3430ES1),
 	CLK(NULL,	"core_12m_fck",	&core_12m_fck,	CK_3XXX),
 	CLK("omap_hdq.0",	"fck",	&hdq_fck,	CK_3XXX),
+	CLK(NULL,	"hdq_fck",	&hdq_fck,	CK_3XXX),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es1,	CK_3430ES1),
 	CLK(NULL,	"ssi_ssr_fck",	&ssi_ssr_fck_3430es2,	CK_3430ES2PLUS | CK_36XX),
 	CLK(NULL,	"ssi_sst_fck",	&ssi_sst_fck_3430es1,	CK_3430ES1),
@@ -3321,6 +3323,8 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"core_l3_ick",	&core_l3_ick,	CK_3XXX),
 	CLK("musb-omap2430",	"ick",	&hsotgusb_ick_3430es1,	CK_3430ES1),
 	CLK("musb-omap2430",	"ick",	&hsotgusb_ick_3430es2,	CK_3430ES2PLUS | CK_36XX),
+	CLK(NULL,	"hsotgusb_ick",	&hsotgusb_ick_3430es1,	CK_3430ES1),
+	CLK(NULL,	"hsotgusb_ick",	&hsotgusb_ick_3430es2,	CK_3430ES2PLUS | CK_36XX),
 	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_3XXX),
 	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_3XXX),
 	CLK(NULL,	"security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3329,27 +3333,40 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK("usbhs_omap",	"usbtll_ick",	&usbtll_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK("omap_hsmmc.2",	"ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+	CLK(NULL,	"mmchs3_ick",	&mmchs3_ick,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"icr_ick",	&icr_ick,	CK_34XX | CK_36XX),
 	CLK("omap-aes",	"ick",	&aes2_ick,	CK_34XX | CK_36XX),
 	CLK("omap-sham",	"ick",	&sha12_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"des2_ick",	&des2_ick,	CK_34XX | CK_36XX),
 	CLK("omap_hsmmc.1",	"ick",	&mmchs2_ick,	CK_3XXX),
 	CLK("omap_hsmmc.0",	"ick",	&mmchs1_ick,	CK_3XXX),
+	CLK(NULL,	"mmchs2_ick",	&mmchs2_ick,	CK_3XXX),
+	CLK(NULL,	"mmchs1_ick",	&mmchs1_ick,	CK_3XXX),
 	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_34XX | CK_36XX),
 	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_3XXX),
+	CLK(NULL,	"hdq_ick",	&hdq_ick,	CK_3XXX),
 	CLK("omap2_mcspi.4", "ick",	&mcspi4_ick,	CK_3XXX),
 	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_3XXX),
 	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_3XXX),
 	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_3XXX),
+	CLK(NULL,	"mcspi4_ick",	&mcspi4_ick,	CK_3XXX),
+	CLK(NULL,	"mcspi3_ick",	&mcspi3_ick,	CK_3XXX),
+	CLK(NULL,	"mcspi2_ick",	&mcspi2_ick,	CK_3XXX),
+	CLK(NULL,	"mcspi1_ick",	&mcspi1_ick,	CK_3XXX),
 	CLK("omap_i2c.3", "ick",	&i2c3_ick,	CK_3XXX),
 	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_3XXX),
 	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_3XXX),
+	CLK(NULL,	"i2c3_ick",	&i2c3_ick,	CK_3XXX),
+	CLK(NULL,	"i2c2_ick",	&i2c2_ick,	CK_3XXX),
+	CLK(NULL,	"i2c1_ick",	&i2c1_ick,	CK_3XXX),
 	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_3XXX),
 	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_3XXX),
 	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_3XXX),
 	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_3XXX),
 	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_3XXX),
 	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_3XXX),
+	CLK(NULL,	"mcbsp5_ick",	&mcbsp5_ick,	CK_3XXX),
+	CLK(NULL,	"mcbsp1_ick",	&mcbsp1_ick,	CK_3XXX),
 	CLK(NULL,	"fac_ick",	&fac_ick,	CK_3430ES1),
 	CLK(NULL,	"mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
 	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_3XXX),
@@ -3368,7 +3385,9 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"dss_96m_fck",	&dss_96m_fck,	CK_3XXX),
 	CLK(NULL,	"dss2_alwon_fck",	&dss2_alwon_fck, CK_3XXX),
 	CLK("omapdss_dss",	"ick",		&dss_ick_3430es1,	CK_3430ES1),
+	CLK(NULL,	"dss_ick",		&dss_ick_3430es1,	CK_3430ES1),
 	CLK("omapdss_dss",	"ick",		&dss_ick_3430es2,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+	CLK(NULL,	"dss_ick",		&dss_ick_3430es2,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
 	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_34XX | CK_36XX),
 	CLK(NULL,	"cam_ick",	&cam_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"csi2_96m_fck",	&csi2_96m_fck,	CK_34XX | CK_36XX),
@@ -3393,6 +3412,7 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_34XX | CK_36XX),
 	CLK(NULL,	"usim_ick",	&usim_ick,	CK_3430ES2PLUS | CK_36XX),
 	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_3XXX),
+	CLK(NULL,	"wdt2_ick",	&wdt2_ick,	CK_3XXX),
 	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_3XXX),
 	CLK(NULL,	"gpio1_ick",	&gpio1_ick,	CK_3XXX),
 	CLK(NULL,	"omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3438,6 +3458,9 @@ static struct omap_clk omap3xxx_clks[] = {
 	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_3XXX),
 	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_3XXX),
 	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_3XXX),
+	CLK(NULL,	"mcbsp4_ick",	&mcbsp2_ick,	CK_3XXX),
+	CLK(NULL,	"mcbsp3_ick",	&mcbsp3_ick,	CK_3XXX),
+	CLK(NULL,	"mcbsp2_ick",	&mcbsp4_ick,	CK_3XXX),
 	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_3XXX),
 	CLK(NULL,	"mcbsp3_fck",	&mcbsp3_fck,	CK_3XXX),
 	CLK(NULL,	"mcbsp4_fck",	&mcbsp4_fck,	CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e4..a3831a2 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk,	CK_443X),
 	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk,	CK_443X),
 	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk,	CK_443X),
+	CLK(NULL,	"dss_fck",			&dss_fck,	CK_443X),
 	CLK("omapdss_dss",	"ick",				&dss_fck,	CK_443X),
 	CLK(NULL,	"efuse_ctrl_cust_fck",		&efuse_ctrl_cust_fck,	CK_443X),
 	CLK(NULL,	"emif1_fck",			&emif1_fck,	CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m,	CK_443X),
 	CLK(NULL,	"ocp2scp_usb_phy_ick",		&ocp2scp_usb_phy_ick,	CK_443X),
 	CLK(NULL,	"ocp_wp_noc_ick",		&ocp_wp_noc_ick,	CK_443X),
+	CLK(NULL,	"rng_ick",			&rng_ick,	CK_443X),
 	CLK("omap_rng",	"ick",				&rng_ick,	CK_443X),
 	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck,	CK_443X),
 	CLK(NULL,	"sl2if_ick",			&sl2if_ick,	CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"uart3_fck",			&uart3_fck,	CK_443X),
 	CLK(NULL,	"uart4_fck",			&uart4_fck,	CK_443X),
 	CLK("usbhs_omap",	"fs_fck",		&usb_host_fs_fck,	CK_443X),
+	CLK(NULL,	"usb_host_fs_fck",		&usb_host_fs_fck,	CK_443X),
 	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk,	CK_443X),
 	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk,	CK_443X),
 	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk,	CK_443X),
@@ -3253,14 +3256,17 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk,	CK_443X),
 	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk,	CK_443X),
 	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk,	CK_443X),
+	CLK(NULL,	"usb_host_hs_fck",		&usb_host_hs_fck,	CK_443X),
 	CLK("usbhs_omap",	"hs_fck",		&usb_host_hs_fck,	CK_443X),
 	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk,	CK_443X),
 	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk,	CK_443X),
+	CLK(NULL,	"usb_otg_hs_ick",		&usb_otg_hs_ick,	CK_443X),
 	CLK("musb-omap2430",	"ick",				&usb_otg_hs_ick,	CK_443X),
 	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k,	CK_443X),
 	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk,	CK_443X),
 	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk,	CK_443X),
 	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk,	CK_443X),
+	CLK(NULL,	"usb_tll_hs_ick",		&usb_tll_hs_ick,	CK_443X),
 	CLK("usbhs_omap",	"usbtll_ick",		&usb_tll_hs_ick,	CK_443X),
 	CLK(NULL,	"usim_ck",			&usim_ck,	CK_443X),
 	CLK(NULL,	"usim_fclk",			&usim_fclk,	CK_443X),
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index fb3e110..c77ab5b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -677,8 +677,8 @@ static int _init_main_clk(struct omap_hwmod *oh)
 	if (!oh->main_clk)
 		return 0;
 
-	oh->_clk = omap_clk_get_by_name(oh->main_clk);
-	if (!oh->_clk) {
+	oh->_clk = clk_get(NULL, oh->main_clk);
+	if (IS_ERR_OR_NULL(oh->_clk)) {
 		pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
 			   oh->name, oh->main_clk);
 		return -EINVAL;
@@ -722,8 +722,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)
 		if (!os->clk)
 			continue;
 
-		c = omap_clk_get_by_name(os->clk);
-		if (!c) {
+		c = clk_get(NULL, os->clk);
+		if (IS_ERR_OR_NULL(c)) {
 			pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
 				   oh->name, os->clk);
 			ret = -EINVAL;
@@ -758,8 +758,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 	int ret = 0;
 
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
-		c = omap_clk_get_by_name(oc->clk);
-		if (!c) {
+		c = clk_get(NULL, oc->clk);
+		if (IS_ERR_OR_NULL(c)) {
 			pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
 				   oh->name, oc->clk);
 			ret = -EINVAL;
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 706b7e2..9d7ac20 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void)
 	}
 }
 
-/**
- * omap_clk_get_by_name - locate OMAP struct clk by its name
- * @name: name of the struct clk to locate
- *
- * Locate an OMAP struct clk by its name.  Assumes that struct clk
- * names are unique.  Returns NULL if not found or a pointer to the
- * struct clk if found.
- */
-struct clk *omap_clk_get_by_name(const char *name)
-{
-	struct clk *c;
-	struct clk *ret = NULL;
-
-	mutex_lock(&clocks_mutex);
-
-	list_for_each_entry(c, &clocks, node) {
-		if (!strcmp(c->name, name)) {
-			ret = c;
-			break;
-		}
-	}
-
-	mutex_unlock(&clocks_mutex);
-
-	return ret;
-}
-
 int omap_clk_enable_autoidle_all(void)
 {
 	struct clk *c;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..af822d5 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -266,10 +266,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
 		return;
 	}
 
-	r = omap_clk_get_by_name(clk_name);
-	if (IS_ERR(r)) {
+	r = clk_get(NULL, clk_name);
+	if (IS_ERR_OR_NULL(r)) {
 		dev_err(&od->pdev->dev,
-			"omap_clk_get_by_name for %s failed\n", clk_name);
+			"clk_get for %s failed\n", clk_name);
 		return;
 	}
 
-- 
1.7.9.5



From rnayak at ti.com  Wed Aug 29 04:56:14 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 29 Aug 2012 14:26:14 +0530
Subject: [PATCH v4 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
In-Reply-To: <1346230576-20004-1-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
Message-ID: <1346230576-20004-2-git-send-email-rnayak@ti.com>

As part of Common Clk Framework (CCF) the clk_enable() operation
was split into a clk_prepare() which could sleep, and a clk_enable()
which should never sleep. Similarly the clk_disable() was
split into clk_disable() and clk_unprepare(). This was
needed to handle complex cases where in a clk gate/ungate
would require a slow and a fast part to be implemented.
None of the clocks below seem to be in the 'complex' clocks
category and are just simple clocks which are enabled/disabled
through simple register writes.
Most of the instances also seem to be called in non-atomic
context which means its safe to move all of those from
using a clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare().

For some others, mainly the ones handled through the hwmod framework
there is a possibility that they get called in either an atomic
or a non-atomic context.

The way these get handled below work only as long as clk_prepare
is implemented as a no-op (which is the case today) since this gets
called very early at boot while most subsystems are unavailable.
Hence these are marked with a *HACK* comment, which says we need
to re-visit these once we start doing something meaningful with
clk_prepare/clk_unprepare like doing voltage scaling or something
that involves i2c.

This is in preparation of OMAP moving to CCF.

Based on initial changes from Mike turquette.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/board-apollon.c    |    4 ++--
 arch/arm/mach-omap2/board-h4.c         |    6 +++---
 arch/arm/mach-omap2/board-omap4panda.c |    2 +-
 arch/arm/mach-omap2/clock3xxx.c        |    8 ++++----
 arch/arm/mach-omap2/display.c          |    4 ++--
 arch/arm/mach-omap2/gpmc.c             |    2 +-
 arch/arm/mach-omap2/omap_hwmod.c       |   27 +++++++++++++++++++++++++++
 7 files changed, 40 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index e5fa46b..25e8f2f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -204,7 +204,7 @@ static inline void __init apollon_init_smc91x(void)
 		return;
 	}
 
-	clk_enable(gpmc_fck);
+	clk_prepare_enable(gpmc_fck);
 	rate = clk_get_rate(gpmc_fck);
 
 	eth_cs = APOLLON_ETH_CS;
@@ -248,7 +248,7 @@ static inline void __init apollon_init_smc91x(void)
 		gpmc_cs_free(APOLLON_ETH_CS);
 	}
 out:
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index ace2048..bd08bef 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -266,9 +266,9 @@ static inline void __init h4_init_debug(void)
 		return;
 	}
 
-	clk_enable(gpmc_fck);
+	clk_prepare_enable(gpmc_fck);
 	rate = clk_get_rate(gpmc_fck);
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 
 	if (is_gpmc_muxed())
@@ -312,7 +312,7 @@ static inline void __init h4_init_debug(void)
 		gpmc_cs_free(eth_cs);
 
 out:
-	clk_disable(gpmc_fck);
+	clk_disable_unprepare(gpmc_fck);
 	clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 70f6d1d..86c2201 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -172,7 +172,7 @@ static void __init omap4_ehci_init(void)
 		return;
 	}
 	clk_set_rate(phy_ref_clk, 19200000);
-	clk_enable(phy_ref_clk);
+	clk_prepare_enable(phy_ref_clk);
 
 	/* disable the power to the usb hub prior to init and reset phy+hub */
 	ret = gpio_request_array(panda_ehci_gpios,
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d827..4c1591a 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void)
 
 	dpll5_clk = clk_get(NULL, "dpll5_ck");
 	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-	clk_enable(dpll5_clk);
+	clk_prepare_enable(dpll5_clk);
 
 	/* Program dpll5_m2_clk divider for no division */
 	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-	clk_enable(dpll5_m2_clk);
+	clk_prepare_enable(dpll5_m2_clk);
 	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 
-	clk_disable(dpll5_m2_clk);
-	clk_disable(dpll5_clk);
+	clk_disable_unprepare(dpll5_m2_clk);
+	clk_disable_unprepare(dpll5_clk);
 	return;
 }
 
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d..5a3afd2 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 		if (oc->_clk)
-			clk_enable(oc->_clk);
+			clk_prepare_enable(oc->_clk);
 
 	dispc_disable_outputs();
 
@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 		if (oc->_clk)
-			clk_disable(oc->_clk);
+			clk_disable_unprepare(oc->_clk);
 
 	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index b2b5759..a14d650c 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -750,7 +750,7 @@ static int __init gpmc_init(void)
 		BUG();
 	}
 
-	clk_enable(gpmc_l3_clk);
+	clk_prepare_enable(gpmc_l3_clk);
 
 	l = gpmc_read_reg(GPMC_REVISION);
 	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..fb3e110 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -683,6 +683,15 @@ static int _init_main_clk(struct omap_hwmod *oh)
 			   oh->name, oh->main_clk);
 		return -EINVAL;
 	}
+	/*
+	 * HACK: This needs a re-visit once clk_prepare() is implemented
+	 * to do something meaningful. Today its just a no-op.
+	 * If clk_prepare() is used at some point to do things like
+	 * voltage scaling etc, then this would have to be moved to
+	 * some point where subsystems like i2c and pmic become
+	 * available.
+	 */
+	clk_prepare(oh->_clk);
 
 	if (!oh->_clk->clkdm)
 		pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
@@ -720,6 +729,15 @@ static int _init_interface_clks(struct omap_hwmod *oh)
 			ret = -EINVAL;
 		}
 		os->_clk = c;
+		/*
+		 * HACK: This needs a re-visit once clk_prepare() is implemented
+		 * to do something meaningful. Today its just a no-op.
+		 * If clk_prepare() is used at some point to do things like
+		 * voltage scaling etc, then this would have to be moved to
+		 * some point where subsystems like i2c and pmic become
+		 * available.
+		 */
+		clk_prepare(os->_clk);
 	}
 
 	return ret;
@@ -747,6 +765,15 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 			ret = -EINVAL;
 		}
 		oc->_clk = c;
+		/*
+		 * HACK: This needs a re-visit once clk_prepare() is implemented
+		 * to do something meaningful. Today its just a no-op.
+		 * If clk_prepare() is used at some point to do things like
+		 * voltage scaling etc, then this would have to be moved to
+		 * some point where subsystems like i2c and pmic become
+		 * available.
+		 */
+		clk_prepare(oc->_clk);
 	}
 
 	return ret;
-- 
1.7.9.5



From rnayak at ti.com  Wed Aug 29 04:56:16 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 29 Aug 2012 14:26:16 +0530
Subject: [PATCH v4 3/3] ARM: OMAP2+: clock: Remove all direct dereferencing of
 struct clk
In-Reply-To: <1346230576-20004-1-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
Message-ID: <1346230576-20004-4-git-send-email-rnayak@ti.com>

While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.

While here also concatenate some strings split across multiple lines
which seem to be needed anyway.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
[paul at pwsan.com: simplified some compound expressions; reformatted some
 messages]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Mike Turquette <mturquette at linaro.org>
---
 arch/arm/mach-omap2/clkt2xxx_apll.c          |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   10 ++-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c       |   20 +++---
 arch/arm/mach-omap2/clkt_clksel.c            |   91 ++++++++++++++++----------
 arch/arm/mach-omap2/clkt_dpll.c              |   26 ++++----
 arch/arm/mach-omap2/clock.c                  |   11 ++--
 arch/arm/mach-omap2/dpll3xxx.c               |   48 ++++++++------
 arch/arm/mach-omap2/omap_hwmod.c             |    6 +-
 arch/arm/mach-omap2/pm.c                     |    2 +-
 arch/arm/plat-omap/include/plat/clock.h      |    5 ++
 10 files changed, 135 insertions(+), 86 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7..c2d1521 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
 	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
 	omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-			     OMAP24XX_CM_IDLEST_VAL, clk->name);
+			     OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
 
 	/*
 	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746..da03fa4 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
 	const struct prcm_config *ptr;
-	long highest_rate;
+	long highest_rate, sys_clk_rate;
 
 	highest_rate = -EINVAL;
+	sys_clk_rate = __clk_get_rate(sclk);
 
 	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 		if (!(ptr->flags & cpu_mask))
 			continue;
-		if (ptr->xtal_speed != sclk->rate)
+		if (ptr->xtal_speed != sys_clk_rate)
 			continue;
 
 		highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 	const struct prcm_config *prcm;
 	unsigned long found_speed = 0;
 	unsigned long flags;
+	long sys_clk_rate;
+
+	sys_clk_rate = __clk_get_rate(sclk);
 
 	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 		if (!(prcm->flags & cpu_mask))
 			continue;
 
-		if (prcm->xtal_speed != sclk->rate)
+		if (prcm->xtal_speed != sys_clk_rate)
 			continue;
 
 		if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..0fd8b70 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	struct omap_sdrc_params *sdrc_cs0;
 	struct omap_sdrc_params *sdrc_cs1;
 	int ret;
+	unsigned long clkrate;
 
 	if (!clk || !rate)
 		return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	if (validrate != rate)
 		return -EINVAL;
 
-	sdrcrate = sdrc_ick_p->rate;
-	if (rate > clk->rate)
-		sdrcrate <<= ((rate / clk->rate) >> 1);
+	sdrcrate = __clk_get_rate(sdrc_ick_p);
+	clkrate = __clk_get_rate(clk);
+	if (rate > clkrate)
+		sdrcrate <<= ((rate / clkrate) >> 1);
 	else
-		sdrcrate >>= ((clk->rate / rate) >> 1);
+		sdrcrate >>= ((clkrate / rate) >> 1);
 
 	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
 	if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	/*
 	 * XXX This only needs to be done when the CPU frequency changes
 	 */
-	_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+	_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
 	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
 	c += 1;  /* for safety */
 	c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 	if (c == 0)
 		c = 1;
 
-	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-		 validrate);
+	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+		 clkrate, validrate);
 	pr_debug("clock: SDRC CS0 timing params used:"
 		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
@@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
 	if (sdrc_cs1)
 		omap3_configure_core_dpll(
-				  new_div, unlock_dll, c, rate > clk->rate,
+				  new_div, unlock_dll, c, rate > clkrate,
 				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 	else
 		omap3_configure_core_dpll(
-				  new_div, unlock_dll, c, rate > clk->rate,
+				  new_div, unlock_dll, c, rate > clkrate,
 				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 				  0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..33382fb 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 
 	if (!clks->parent) {
 		/* This indicates a data problem */
-		WARN(1, "clock: Could not find parent clock %s in clksel array "
-		     "of clock %s\n", src_clk->name, clk->name);
+		WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+		     __clk_get_name(clk), __clk_get_name(src_clk));
 		return NULL;
 	}
 
@@ -126,8 +126,9 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
 
 	if (max_div == 0) {
 		/* This indicates an error in the clksel data */
-		WARN(1, "clock: Could not find divisor for clock %s parent %s"
-		     "\n", clk->name, src_clk->parent->name);
+		WARN(1, "clock: %s: could not find divisor for parent %s\n",
+		     __clk_get_name(clk),
+		     __clk_get_name(__clk_get_parent(src_clk)));
 		return 0;
 	}
 
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
+	struct clk *parent;
 
-	clks = _get_clksel_by_parent(clk, clk->parent);
+	parent = __clk_get_parent(clk);
+	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
 		return 0;
 
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
 	if (!clkr->div) {
 		/* This indicates a data error */
-		WARN(1, "clock: Could not find fieldval %d for clock %s parent "
-		     "%s\n", field_val, clk->name, clk->parent->name);
+		WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+		     __clk_get_name(clk), field_val, __clk_get_name(parent));
 		return 0;
 	}
 
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
+	struct clk *parent;
 
 	/* should never happen */
 	WARN_ON(div == 0);
 
-	clks = _get_clksel_by_parent(clk, clk->parent);
+	parent = __clk_get_parent(clk);
+	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
 		return ~0;
 
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 	}
 
 	if (!clkr->div) {
-		pr_err("clock: Could not find divisor %d for clock %s parent "
-		       "%s\n", div, clk->name, clk->parent->name);
+		pr_err("clock: %s: could not find divisor %d for parent %s\n",
+		       __clk_get_name(clk), div, __clk_get_name(parent));
 		return ~0;
 	}
 
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
 	u32 last_div = 0;
+	struct clk *parent;
+	unsigned long parent_rate;
+	const char *clk_name;
+
+	parent = __clk_get_parent(clk);
+	parent_rate = __clk_get_rate(parent);
+	clk_name = __clk_get_name(clk);
 
 	if (!clk->clksel || !clk->clksel_mask)
 		return ~0;
 
 	pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-		 clk->name, target_rate);
+		 clk_name, target_rate);
 
 	*new_div = 1;
 
-	clks = _get_clksel_by_parent(clk, clk->parent);
+	clks = _get_clksel_by_parent(clk, parent);
 	if (!clks)
 		return ~0;
 
@@ -300,30 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
 		/* Sanity check */
 		if (clkr->div <= last_div)
-			pr_err("clock: clksel_rate table not sorted "
-			       "for clock %s", clk->name);
+			pr_err("clock: %s: clksel_rate table not sorted\n",
+			       clk_name);
 
 		last_div = clkr->div;
 
-		test_rate = clk->parent->rate / clkr->div;
+		test_rate = parent_rate / clkr->div;
 
 		if (test_rate <= target_rate)
 			break; /* found it */
 	}
 
 	if (!clkr->div) {
-		pr_err("clock: Could not find divisor for target "
-		       "rate %ld for clock %s parent %s\n", target_rate,
-		       clk->name, clk->parent->name);
+		pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+		       clk_name, target_rate, __clk_get_name(parent));
 		return ~0;
 	}
 
 	*new_div = clkr->div;
 
 	pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-		 (clk->parent->rate / clkr->div));
+		 (parent_rate / clkr->div));
 
-	return clk->parent->rate / clkr->div;
+	return parent_rate / clkr->div;
 }
 
 /*
@@ -345,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
 	const struct clksel *clks;
 	const struct clksel_rate *clkr;
 	u32 r, found = 0;
+	struct clk *parent;
+	const char *clk_name;
 
 	if (!clk->clksel || !clk->clksel_mask)
 		return;
 
+	parent = __clk_get_parent(clk);
+	clk_name = __clk_get_name(clk);
+
 	r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
 	r >>= __ffs(clk->clksel_mask);
 
@@ -358,12 +374,14 @@ void omap2_init_clksel_parent(struct clk *clk)
 				continue;
 
 			if (clkr->val == r) {
-				if (clk->parent != clks->parent) {
+				if (parent != clks->parent) {
 					pr_debug("clock: inited %s parent "
 						 "to %s (was %s)\n",
-						 clk->name, clks->parent->name,
-						 ((clk->parent) ?
-						  clk->parent->name : "NULL"));
+						 clk_name,
+						 __clk_get_name(clks->parent),
+						 ((parent) ?
+						  __clk_get_name(parent) :
+						 "NULL"));
 					clk_reparent(clk, clks->parent);
 				};
 				found = 1;
@@ -373,7 +391,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
 	/* This indicates a data error */
 	WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-	     clk->name, r);
+	     clk_name, r);
 
 	return;
 }
@@ -391,15 +409,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 {
 	unsigned long rate;
 	u32 div = 0;
+	struct clk *parent;
 
 	div = _read_divisor(clk);
 	if (div == 0)
-		return clk->rate;
+		return __clk_get_rate(clk);
 
-	rate = clk->parent->rate / div;
+	parent = __clk_get_parent(clk);
+	rate = __clk_get_rate(parent) / div;
 
-	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
-		 rate, div);
+	pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+		 __clk_get_name(clk), rate, div);
 
 	return rate;
 }
@@ -454,9 +474,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
 	_write_clksel_reg(clk, field_val);
 
-	clk->rate = clk->parent->rate / new_div;
+	clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
 
-	pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+	pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+		 __clk_get_rate(clk));
 
 	return 0;
 }
@@ -498,13 +519,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
 	clk_reparent(clk, new_parent);
 
 	/* CLKSEL clocks follow their parents' rates, divided by a divisor */
-	clk->rate = new_parent->rate;
+	clk->rate = __clk_get_rate(new_parent);
 
 	if (parent_div > 0)
-		clk->rate /= parent_div;
+		__clk_get_rate(clk) /= parent_div;
 
 	pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-		 clk->name, clk->parent->name, clk->rate);
+		 __clk_get_name(clk),
+		 __clk_get_name(__clk_get_parent(clk)),
+		 __clk_get_rate(clk));
 
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..8c3349e 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
 	dd = clk->dpll_data;
 
 	/* DPLL divider must result in a valid jitter correction val */
-	fint = clk->parent->rate / n;
+	fint = __clk_get_rate(__clk_get_parent(clk)) / n;
 
 	if (cpu_is_omap24xx()) {
 		/* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 	if (cpu_is_omap24xx()) {
 		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-			return dd->clk_bypass->rate;
+			return __clk_get_rate(dd->clk_bypass);
 	} else if (cpu_is_omap34xx()) {
 		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-			return dd->clk_bypass->rate;
+			return __clk_get_rate(dd->clk_bypass);
 	} else if (cpu_is_omap44xx()) {
 		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
 		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-			return dd->clk_bypass->rate;
+			return __clk_get_rate(dd->clk_bypass);
 	}
 
 	v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 	dpll_div = v & dd->div1_mask;
 	dpll_div >>= __ffs(dd->div1_mask);
 
-	dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+	dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
 	do_div(dpll_clk, dpll_div + 1);
 
 	return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 	unsigned long scaled_rt_rp;
 	unsigned long new_rate = 0;
 	struct dpll_data *dd;
+	unsigned long ref_rate;
+	const char *clk_name;
 
 	if (!clk || !clk->dpll_data)
 		return ~0;
 
 	dd = clk->dpll_data;
 
+	ref_rate = __clk_get_rate(dd->clk_ref);
+	clk_name = __clk_get_name(clk);
 	pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-		 clk->name, target_rate);
+		 clk_name, target_rate);
 
-	scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
 	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
 	dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 			break;
 
 		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-				    dd->clk_ref->rate);
+				    ref_rate);
 
 		/* m can't be set low enough for this n - try with a larger n */
 		if (r == DPLL_MULT_UNDERFLOW)
 			continue;
 
 		pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-			 clk->name, m, n, new_rate);
+			 clk_name, m, n, new_rate);
 
 		if (target_rate == new_rate) {
 			dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 	}
 
 	if (target_rate != new_rate) {
-		pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
-			 target_rate);
+		pr_debug("clock: %s: cannot round to rate %ld\n",
+			 clk_name, target_rate);
 		return ~0;
 	}
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..5083d72 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -76,7 +76,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
 	clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
 
 	omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
-			     clk->name);
+			     __clk_get_name(clk));
 }
 
 /* Public functions */
@@ -92,18 +92,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
 void omap2_init_clk_clkdm(struct clk *clk)
 {
 	struct clockdomain *clkdm;
+	const char *clk_name;
 
 	if (!clk->clkdm_name)
 		return;
 
+	clk_name = __clk_get_name(clk);
+
 	clkdm = clkdm_lookup(clk->clkdm_name);
 	if (clkdm) {
 		pr_debug("clock: associated clk %s to clkdm %s\n",
-			 clk->name, clk->clkdm_name);
+			 clk_name, clk->clkdm_name);
 		clk->clkdm = clkdm;
 	} else {
-		pr_debug("clock: could not associate clk %s to "
-			 "clkdm %s\n", clk->name, clk->clkdm_name);
+		pr_debug("clock: could not associate clk %s to clkdm %s\n",
+			 clk_name, clk->clkdm_name);
 	}
 }
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..47c2bf7 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 	const struct dpll_data *dd;
 	int i = 0;
 	int ret = -EINVAL;
+	const char *clk_name;
 
 	dd = clk->dpll_data;
+	clk_name = __clk_get_name(clk);
 
 	state <<= __ffs(dd->idlest_mask);
 
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 
 	if (i == MAX_DPLL_WAIT_TRIES) {
 		printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-		       clk->name, (state) ? "locked" : "bypassed");
+		       clk_name, (state) ? "locked" : "bypassed");
 	} else {
 		pr_debug("clock: %s transition to '%s' in %d loops\n",
-			 clk->name, (state) ? "locked" : "bypassed", i);
+			 clk_name, (state) ? "locked" : "bypassed", i);
 
 		ret = 0;
 	}
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
 	unsigned long fint;
 	u16 f = 0;
 
-	fint = clk->dpll_data->clk_ref->rate / n;
+	fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
 
 	pr_debug("clock: fint is %lu\n", fint);
 
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
 	u8 state = 1;
 	int r = 0;
 
-	pr_debug("clock: locking DPLL %s\n", clk->name);
+	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
 
 	dd = clk->dpll_data;
 	state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
 		return -EINVAL;
 
 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-		 clk->name);
+		 __clk_get_name(clk));
 
 	ai = omap3_dpll_autoidle_read(clk);
 
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 		return -EINVAL;
 
-	pr_debug("clock: stopping DPLL %s\n", clk->name);
+	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
 
 	ai = omap3_dpll_autoidle_read(clk);
 
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
 	unsigned long fint, clkinp; /* watch out for overflow */
 
-	clkinp = clk->parent->rate;
+	clkinp = __clk_get_rate(__clk_get_parent(clk));
 	fint = (clkinp / n) * m;
 
 	if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
 	unsigned long clkinp, sd; /* watch out for overflow */
 	int mod1, mod2;
 
-	clkinp = clk->parent->rate;
+	clkinp = __clk_get_rate(__clk_get_parent(clk));
 
 	/*
 	 * target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 {
 	int r;
 	struct dpll_data *dd;
+	struct clk *parent;
 
 	dd = clk->dpll_data;
 	if (!dd)
 		return -EINVAL;
 
-	if (clk->rate == dd->clk_bypass->rate) {
-		WARN_ON(clk->parent != dd->clk_bypass);
+	parent = __clk_get_parent(clk);
+
+	if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+		WARN_ON(parent != dd->clk_bypass);
 		r = _omap3_noncore_dpll_bypass(clk);
 	} else {
-		WARN_ON(clk->parent != dd->clk_ref);
+		WARN_ON(parent != dd->clk_ref);
 		r = _omap3_noncore_dpll_lock(clk);
 	}
 	/*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
 	struct clk *new_parent = NULL;
-	unsigned long hw_rate;
+	unsigned long hw_rate, bypass_rate;
 	u16 freqsel = 0;
 	struct dpll_data *dd;
 	int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 	omap2_clk_enable(dd->clk_bypass);
 	omap2_clk_enable(dd->clk_ref);
 
-	if (dd->clk_bypass->rate == rate &&
+	bypass_rate = __clk_get_rate(dd->clk_bypass);
+	if (bypass_rate == rate &&
 	    (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
 		pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 		}
 
 		pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-			 clk->name, rate);
+			 __clk_get_name(clk), rate);
 
 		ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
 						 dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
 	if (!dd->autoidle_reg) {
 		pr_debug("clock: DPLL %s: autoidle not supported\n",
-			clk->name);
+			__clk_get_name(clk));
 		return;
 	}
 
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
 	if (!dd->autoidle_reg) {
 		pr_debug("clock: DPLL %s: autoidle not supported\n",
-			clk->name);
+			__clk_get_name(clk));
 		return;
 	}
 
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 	unsigned long rate;
 	u32 v;
 	struct clk *pclk;
+	unsigned long parent_rate;
 
 	/* Walk up the parents of clk, looking for a DPLL */
-	pclk = clk->parent;
+	pclk = __clk_get_parent(clk);
 	while (pclk && !pclk->dpll_data)
-		pclk = pclk->parent;
+		pclk = __clk_get_parent(pclk);
 
 	/* clk does not have a DPLL as a parent? */
 	WARN_ON(!pclk);
@@ -630,12 +637,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 
 	WARN_ON(!dd->enable_mask);
 
+	parent_rate = __clk_get_rate(__clk_get_parent(clk));
 	v = __raw_readl(dd->control_reg) & dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
-		rate = clk->parent->rate;
+		rate = parent_rate;
 	else
-		rate = clk->parent->rate * 2;
+		rate = parent_rate * 2;
 	return rate;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c77ab5b..8b614eb 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -695,7 +695,7 @@ static int _init_main_clk(struct omap_hwmod *oh)
 
 	if (!oh->_clk->clkdm)
 		pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
-			   oh->main_clk, oh->_clk->name);
+			   oh->name, oh->main_clk);
 
 	return ret;
 }
@@ -852,7 +852,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 		if (oc->_clk) {
 			pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
-				 oc->_clk->name);
+				 __clk_get_name(oc->_clk));
 			clk_enable(oc->_clk);
 		}
 }
@@ -867,7 +867,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 		if (oc->_clk) {
 			pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
-				 oc->_clk->name);
+				 __clk_get_name(oc->_clk));
 			clk_disable(oc->_clk);
 		}
 }
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5ced..40012e3 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
 		goto exit;
 	}
 
-	freq = clk->rate;
+	freq = clk_get_rate(clk);
 	clk_put(clk);
 
 	rcu_read_lock();
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b986..e2e2d04 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
 struct clk;
 struct clockdomain;
 
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)	(clk->name)
+#define __clk_get_parent(clk)	(clk->parent)
+#define __clk_get_rate(clk)	(clk->rate)
+
 /**
  * struct clkops - some clock function pointers
  * @enable: fn ptr that enables the current clock in hardware
-- 
1.7.9.5



From u.kleine-koenig at pengutronix.de  Wed Aug 29 05:00:00 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 29 Aug 2012 11:00:00 +0200
Subject: [PATCH] ARM: tegra_defconfig: enable APB DMA support
Message-ID: <1346230800-3167-1-git-send-email-u.kleine-koenig@pengutronix.de>

Additionally DMADEVICES needs to be enabled as TEGRA20_APB_DMA depends
on that.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/configs/tegra_defconfig |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db22453..0d6bb73 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-- 
1.7.10.4



From ijc at hellion.org.uk  Wed Aug 29 05:04:13 2012
From: ijc at hellion.org.uk (Ian Campbell)
Date: Wed, 29 Aug 2012 10:04:13 +0100
Subject: dreamplug spi partitions
In-Reply-To: <20120828153050.GD19437@titan.lakedaemon.net>
References: <1344498477.11783.38.camel@dagon.hellion.org.uk>
 <20120816142005.GS22226@titan.lakedaemon.net>
 <1345566505.6821.115.camel@zakaz.uk.xensource.com>
 <20120828153050.GD19437@titan.lakedaemon.net>
Message-ID: <1346231053.9975.43.camel@zakaz.uk.xensource.com>

(lets add the u-boot list, like I should have done in the first place. 
For u-boot@ folks the thread starts at
http://www.spinics.net/lists/arm-kernel/msg188462.html and concerns the
discrepancy between the size of u-boot's environment defined by u-boot
and the kernel)

On Tue, 2012-08-28 at 11:30 -0400, Jason Cooper wrote:
> Before we go changing anything, what is the maximum size a uboot
> environment

grepping for CONFIG_ENV_SIZE in the u-boot source shows examples of
basically every conceivable size. The biggest I could see was 256K. That
seems pretty huge compared to the sorts of things stored in here though
(I expect it happens to be the underlying sector size)

BTW, I see that in u-boot CONFIG_ENV_SECT_SIZE is 64K while
CONFIG_ENV_SIZE is only 4K. Looking at README this would be discouraged
(it's intended to be used to allow u-boot and the env to share a sector,
which is dangerous) but the layout we use doesn't actually overlap
anything.

I've not had much luck googling for the spec of the actual SPI part in
the dreamplug and my one is at home so I can't look for part numbers.

>  or a dtb can be?

Single digit numbers of K seems to be the norm (at least for vexpress
platforms). Allowing for a pretty huge factor for expansion even just 4K
would be enormous (although that strikes me as the sort of statement
which comes back to haunt people ;-)).

>   Until we can nail that down, I'm inclined
> to leave the partitions at their current locations and only adjust the
> size of the environment down to 4k in the kernel.

That sounds sensible.

> This way, a user foolishly attempting to write more than 4k will get an
> error.
> 
> If a user changes out their uboot to get a larger environment, they can
> adjust the dts as well.  No kernel rebuilding necessary.

I hadn't spotted that this was in DTS now (although I should have
guessed). Either way this sounds reasonable to me.

Ian.
-- 
Ian Campbell

How sharper than a hound's tooth it is to have a thankless serpent.



From u.kleine-koenig at pengutronix.de  Wed Aug 29 05:05:26 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 29 Aug 2012 11:05:26 +0200
Subject: [PATCH] MAINTAINERS: add defconfig file to IMX section
Message-ID: <1346231126-11286-1-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 MAINTAINERS |    1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 39d8a59..6bfd2df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -777,6 +777,7 @@ S:	Maintained
 T:	git git://git.pengutronix.de/git/imx/linux-2.6.git
 F:	arch/arm/mach-imx/
 F:	arch/arm/plat-mxc/
+F:	arch/arm/configs/imx*_defconfig
 
 ARM/FREESCALE IMX6
 M:	Shawn Guo <shawn.guo at linaro.org>
-- 
1.7.10.4



From ldewangan at nvidia.com  Wed Aug 29 05:19:36 2012
From: ldewangan at nvidia.com (Laxman Dewangan)
Date: Wed, 29 Aug 2012 14:49:36 +0530
Subject: [PATCH] ARM: tegra_defconfig: enable APB DMA support
In-Reply-To: <1346230800-3167-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1346230800-3167-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <503DDEA8.1000405@nvidia.com>

On Wednesday 29 August 2012 02:30 PM, Uwe Kleine-K?nig wrote:
> Additionally DMADEVICES needs to be enabled as TEGRA20_APB_DMA depends
> on that.
>
> Signed-off-by: Uwe Kleine-K?nig<u.kleine-koenig at pengutronix.de>
> ---
>   arch/arm/configs/tegra_defconfig |    2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
> index db22453..0d6bb73 100644
> --- a/arch/arm/configs/tegra_defconfig
> +++ b/arch/arm/configs/tegra_defconfig
> @@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
>   CONFIG_RTC_CLASS=y
>   CONFIG_RTC_DRV_EM3027=y
>   CONFIG_RTC_DRV_TEGRA=y
> +CONFIG_DMADEVICES=y
> +CONFIG_TEGRA20_APB_DMA=y
>   CONFIG_STAGING=y
>   CONFIG_SENSORS_ISL29018=y
>   CONFIG_SENSORS_ISL29028=y

Hi Uwe,
Tegra team is working on to enable the new dma drivr which is dmaengine 
based. We have dma legacy driver as of now in mach-tegra. Some of the 
tests are failing with new dmadriver and so we are not able to enable it.
The patch series which is posted against this is:

[PATCH 0/5] ARM: tegra: move all APB DMA client to dmaengine based driver

Thanks,
Laxman





From alexander.shishkin at linux.intel.com  Wed Aug 29 05:44:40 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 12:44:40 +0300
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <20120829082254.GH4011@b20223-02.ap.freescale.net>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
 <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828090942.GX4011@b20223-02.ap.freescale.net>
 <87y5kyjfa3.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829082254.GH4011@b20223-02.ap.freescale.net>
Message-ID: <87pq6ajalz.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> On Wed, Aug 29, 2012 at 11:03:48AM +0300, Alexander Shishkin wrote:
>> Richard Zhao <richard.zhao at freescale.com> writes:
>> 
>> > On Tue, Aug 28, 2012 at 11:29:35AM +0300, Alexander Shishkin wrote:
>> >> Richard Zhao <richard.zhao at freescale.com> writes:
>> >> 
>> >> > States in gadget are not needed any more, set it to zero.
>> >> 
>> >> It's generally a good practice to mention in the commit message what is
>> >> it that you are fixing with this patch.
>> > It fixes the following dump if udc_start register gadget->dev but fail
>> > the start process:
>> > kobject (bf8330a0): tried to init an initialized object, something is seriously wrong.
>> > [<80011d90>] (dump_backtrace+0x0/0x10c) from [<804b65ac>] (dump_stack+0x18/0x1c)
>> > [<804b6594>] (dump_stack+0x0/0x1c) from [<80247d98>] (kobject_init+0x7c/0x9c)
>> > [<80247d1c>] (kobject_init+0x0/0x9c) from [<802a3870>] (device_initialize+0x28/0x70)
>> > [<802a3848>] (device_initialize+0x0/0x70) from [<802a4798>] (device_register+0x14/0x20)
>> > [<802a4784>] (device_register+0x0/0x20) from [<80359a70>] (udc_start+0x180/0x2c8)
>> > [<803598f0>] (udc_start+0x0/0x2c8) from [<80356e9c>] (ci_role_work+0xc8/0xec)
>> > [<80356dd4>] (ci_role_work+0x0/0xec) from [<8003a8a0>] (process_one_work+0x158/0x474)
>> > [<8003a748>] (process_one_work+0x0/0x474) from [<8003af6c>] (worker_thread+0x140/0x3b4)
>> > [<8003ae2c>] (worker_thread+0x0/0x3b4) from [<8003fe60>] (kthread+0x90/0x9c)
>> > [<8003fdd0>] (kthread+0x0/0x9c) from [<8002774c>] (do_exit+0x0/0x350)
>> >> 
>> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
>> >> > ---
>> >> >  drivers/usb/chipidea/udc.c |    1 +
>> >> >  1 file changed, 1 insertion(+)
>> >> >
>> >> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
>> >> > index c7a032a..9fb6394 100644
>> >> > --- a/drivers/usb/chipidea/udc.c
>> >> > +++ b/drivers/usb/chipidea/udc.c
>> >> > @@ -1746,6 +1746,7 @@ free_pools:
>> >> >  	dma_pool_destroy(ci->td_pool);
>> >> >  free_qh_pool:
>> >> >  	dma_pool_destroy(ci->qh_pool);
>> >> > +	memset(&ci->gadget, 0, sizeof(ci->gadget));
>> >> 
>> >> I understand that you're probably hitting "kobject already initialized"
>> >> warning here, but I think the real problem is that this function gets
>> >> called twice and fails the first time. Why does that happen?
>> > I saw the dump at early stage of adding imx otg support, when there's
>> > things not ready. I think it's less important why udc_start fail,
>> > because no one enable imx otg before.  It's important when it fails,
>> > the dump shows up.
>> 
>> I'd prefer that whenever udc_start() fails it doesn't go unnoticed,
>> except probably for the cases when it fails due to transceiver not being
>> ready at the probe time, which needs to be handled separately.
> Is it related to the patch? The patch is logically right that reset the
> status, agree?

No. This warning means that we have called udc_start() once, failed
(thus didn't call udc_stop()) due to some unknown reason, and called it
again at a later point in time. This -- failing for unknown reason --
should not happen. If it does, we should fix the reason, not paper over
the warning that is telling us that something is wrong.

If we decide that we want to allow udc_start to fail for *certain*
reasons, we should do it explicitly, not by shutting up all warnings for
good.

Regards,
--
Alex


From alexander.shishkin at linux.intel.com  Wed Aug 29 05:48:15 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 12:48:15 +0300
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <20120829083337.GI4011@b20223-02.ap.freescale.net>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
 <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828092730.GY4011@b20223-02.ap.freescale.net>
 <87vcg2jeyu.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829083337.GI4011@b20223-02.ap.freescale.net>
Message-ID: <87mx1ejag0.fsf@ashishki-desk.ger.corp.intel.com>

Richard Zhao <richard.zhao at freescale.com> writes:

> On Wed, Aug 29, 2012 at 11:10:33AM +0300, Alexander Shishkin wrote:
>> Richard Zhao <richard.zhao at freescale.com> writes:
>> 
>> > On Tue, Aug 28, 2012 at 11:38:23AM +0300, Alexander Shishkin wrote:
>> >> Richard Zhao <richard.zhao at freescale.com> writes:
>> >> 
>> >> > One role failed, but the other role will possiblly still work.
>> >> > For example, when udc start failed, if plug in a host device,
>> >> > it works.
>> >> 
>> >> If you're a host device, ci->role should be HOST at this point and
>> >> ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
>> >> role detection must be fixed. If ci_role_start() fails for host, but it
>> >> still works when it's called again after the id pin change is detected,
>> >> again, the problem is elsewhere.
>> > The check is only for OTG device. For single role device, it just fail
>> > if it start the role failed.
>> 
>> Sorry, can you rephrase?
>> 
>> >> 
>> >> >
>> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
>> >> > ---
>> >> >  drivers/usb/chipidea/core.c |    7 +++++--
>> >> >  1 file changed, 5 insertions(+), 2 deletions(-)
>> >> >
>> >> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
>> >> > index 19ef324..8fd390a 100644
>> >> > --- a/drivers/usb/chipidea/core.c
>> >> > +++ b/drivers/usb/chipidea/core.c
>> >> > @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
>> >> >  	ret = ci_role_start(ci, ci->role);
>> >> >  	if (ret) {
>> >> >  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
>> >> > -		ret = -ENODEV;
>> >> > -		goto rm_wq;
>> >> > +		ci->role = CI_ROLE_END;
>> >> 
>> >> So are you relying on id pin interrupt for initializing the role after
>> >> this? Can you provide more details?
>> > Yes. The ID pin detect still works. My case is, gadget role failed,
>> > host role works. I was trying not to ruin host function.
>> 
>> But it shouldn't even try to start the gadget, because ci_otg_role()
>> should set ci->role to HOST before ci_role_start() happens.
> It depends on ID pin. If ID pin is gadget and gadget is not support well,
> ci_role_start will fail. See below example.
>> 
>> Another question is, why does gadget start fail?
> There's one example:
> If usb phy don't support otg yet, otg_set_peripheral will fail, and
> then cause udc_start fail.

So you should drop the CI13XXX_REQUIRE_TRANSCEIVER flag from imx
platform data till the phy is fully implemented.

Regards,
--
Alex


From hvaibhav at ti.com  Wed Aug 29 05:48:11 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 29 Aug 2012 15:18:11 +0530
Subject: [RFC PATCH] ARM: OMAP2+: omap-device: Do not overwrite resources
 allocated by OF layer
Message-ID: <1346233691-10294-1-git-send-email-hvaibhav@ti.com>

With the new devices (like, AM33XX and OMAP5) we now only support
DT boot mode of operation and now it is the time to start killing
slowly the dependency on hwmod, so with this patch, we are starting
with device resources.
The idea here is implemented considering to both boot modes -
  - DT boot mode
    OF framework will construct the resource structure (currently
    does for MEM & IRQ resource) and we should respect/use these
    resources, killing hwmod dependency.
    If pdev->num_resources > 0, we assume that MEM & IRQ resources
    have been allocated by OF layer already (through DTB).

    Once DMA resource is available from OF layer, we should
    kill filling any resources from hwmod.

  - Non-DT boot mode
    Here, pdev->num_resources = 0, and we should get all the
    resources from hwmod (following existing steps)

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Kevin Hilman <khilman at ti.com>
---
This patch is tested on BeagleBone and AM37xEVM.

Why RFC?
Still we have function duplication omap_device_fill_resources() and
omap_device_fill_dma_resources(), we can actually split the function
into 3 resources and avoid duplication -
  - omap_device_fill_dma_resources()
  - omap_device_fill_mem_resources()
  - omap_device_fill_irq_resources()

Actually I wanted to clean it further but thought of getting
feedback first and then proceed further.

 arch/arm/mach-omap2/omap_hwmod.c             |   27 ++++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    1 +
 arch/arm/plat-omap/omap_device.c             |   72 +++++++++++++++++++++----
 3 files changed, 88 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 31ec283..edabfb3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3330,6 +3330,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }

 /**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+	int i, sdma_reqs_cnt;
+	int r = 0;
+
+	sdma_reqs_cnt = _count_sdma_reqs(oh);
+	for (i = 0; i < sdma_reqs_cnt; i++) {
+		(res + r)->name = (oh->sdma_reqs + i)->name;
+		(res + r)->start = (oh->sdma_reqs + i)->dma_req;
+		(res + r)->end = (oh->sdma_reqs + i)->dma_req;
+		(res + r)->flags = IORESOURCE_DMA;
+		r++;
+	}
+
+	return r;
+}
+
+/**
  * omap_hwmod_get_resource_byname - fetch IP block integration data by name
  * @oh: struct omap_hwmod * to operate on
  * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 9b9646c..0533073 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);

 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
 				   const char *name, struct resource *res);

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..fd15a3a 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -486,6 +486,33 @@ static int omap_device_fill_resources(struct omap_device *od,
 }

 /**
+ * omap_device_fill_dma_resources - fill in array of struct resource with dma resources
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the dma resource data for this omap_device @od.  Used by
+ * omap_device_alloc() after calling omap_device_count_resources().
+ *
+ * Ideally this function would not be needed at all.  If we have
+ * mechanism to get dma resources from DT.
+ *
+ * Returns 0.
+ */
+static int omap_device_fill_dma_resources(struct omap_device *od,
+				      struct resource *res)
+{
+	int i, r;
+
+	for (i = 0; i < od->hwmods_cnt; i++) {
+		r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
+		res += r;
+	}
+
+	return 0;
+}
+
+/**
  * omap_device_alloc - allocate an omap_device
  * @pdev: platform_device that will be included in this omap_device
  * @oh: ptr to the single omap_hwmod that backs this omap_device
@@ -524,24 +551,45 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
 	od->hwmods = hwmods;
 	od->pdev = pdev;

+	res_count = omap_device_count_resources(od);
 	/*
-	 * HACK: Ideally the resources from DT should match, and hwmod
-	 * should just add the missing ones. Since the name is not
-	 * properly populated by DT, stick to hwmod resources only.
+	 * DT Boot:
+	 *   OF framework will construct the resource structure (currently
+	 *   does for MEM & IRQ resource) and we should respect/use these
+	 *   resources, killing hwmod dependency.
+	 *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
+	 *   have been allocated by OF layer already (through DTB).
+	 *
+	 * Non-DT Boot:
+	 *   Here, pdev->num_resources = 0, and we should get all the
+	 *   resources from hwmod.
+	 *
+	 * TODO: Once DMA resource is available from OF layer, we should
+	 *   kill filling any resources from hwmod.
 	 */
-	if (pdev->num_resources && pdev->resource)
-		dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
-			__func__, pdev->num_resources);
-
-	res_count = omap_device_count_resources(od);
-	if (res_count > 0) {
-		dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
-			__func__, res_count);
+	if (res_count > pdev->num_resources) {
+		/* Allocate resources memory to account for new resources */
 		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
 		if (!res)
 			goto oda_exit3;

-		omap_device_fill_resources(od, res);
+		/*
+		 * If pdev->num_resources > 0, then assume that,
+		 * MEM and IRQ resources will only come from DT and only
+		 * fill DMA resource from hwmod layer.
+		 */
+		if (pdev->num_resources && pdev->resource) {
+			dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
+					__func__, res_count);
+			memcpy(res, pdev->resource,
+				sizeof(struct resource) * pdev->num_resources);
+			omap_device_fill_dma_resources(od,
+					&res[pdev->num_resources]);
+		} else {
+			dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
+					__func__, res_count);
+			omap_device_fill_resources(od, res);
+		}

 		ret = platform_device_add_resources(pdev, res, res_count);
 		kfree(res);
--
1.7.0.4



From nicolas.ferre at atmel.com  Wed Aug 29 05:49:18 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 29 Aug 2012 11:49:18 +0200
Subject: [PATCH] USB: ohci-at91: fix PIO handling in relation with number of
 ports
Message-ID: <1346233758-27009-1-git-send-email-nicolas.ferre@atmel.com>

If the number of ports present on the SoC/board is not the maximum
and that the platform data is not filled with all data, there is
an easy way to mess the PIO setup for this interface.
This quick fix addresses mis-configuration in USB host platform data
that is common in at91 boards since commit 0ee6d1e (USB: ohci-at91:
change maximum number of ports) that did not modified the associatd
board files.

Reported-by: Klaus Falkner <klaus.falkner at solectrix.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: linux-usb at vger.kernel.org
Cc: Stable <stable at vger.kernel.org> [3.4+]
---
 drivers/usb/host/ohci-at91.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a665b3e..aaa8d2b 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -570,6 +570,16 @@ static int __devinit ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 
 	if (pdata) {
 		at91_for_each_port(i) {
+			/*
+			 * do not configure PIO if not in relation with
+			 * real USB port on board
+			 */
+			if (i >= pdata->ports) {
+				pdata->vbus_pin[i] = -EINVAL;
+				pdata->overcurrent_pin[i] = -EINVAL;
+				break;
+			}
+
 			if (!gpio_is_valid(pdata->vbus_pin[i]))
 				continue;
 			gpio = pdata->vbus_pin[i];
-- 
1.7.10



From u.kleine-koenig at pengutronix.de  Wed Aug 29 05:49:57 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 29 Aug 2012 11:49:57 +0200
Subject: [PATCH] ARM: tegra_defconfig: enable APB DMA support
In-Reply-To: <503DDEA8.1000405@nvidia.com>
References: <1346230800-3167-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <503DDEA8.1000405@nvidia.com>
Message-ID: <20120829094957.GF28643@pengutronix.de>

On Wed, Aug 29, 2012 at 02:49:36PM +0530, Laxman Dewangan wrote:
> On Wednesday 29 August 2012 02:30 PM, Uwe Kleine-K?nig wrote:
> >Additionally DMADEVICES needs to be enabled as TEGRA20_APB_DMA depends
> >on that.
> >
> >Signed-off-by: Uwe Kleine-K?nig<u.kleine-koenig at pengutronix.de>
> >---
> >  arch/arm/configs/tegra_defconfig |    2 ++
> >  1 file changed, 2 insertions(+)
> >
> >diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
> >index db22453..0d6bb73 100644
> >--- a/arch/arm/configs/tegra_defconfig
> >+++ b/arch/arm/configs/tegra_defconfig
> >@@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
> >  CONFIG_RTC_CLASS=y
> >  CONFIG_RTC_DRV_EM3027=y
> >  CONFIG_RTC_DRV_TEGRA=y
> >+CONFIG_DMADEVICES=y
> >+CONFIG_TEGRA20_APB_DMA=y
> >  CONFIG_STAGING=y
> >  CONFIG_SENSORS_ISL29018=y
> >  CONFIG_SENSORS_ISL29028=y
> 
> Hi Uwe,
> Tegra team is working on to enable the new dma drivr which is
> dmaengine based. We have dma legacy driver as of now in mach-tegra.
> Some of the tests are failing with new dmadriver and so we are not
> able to enable it.
So it depends on what you wanna do with the defconfig. There are two
purposes for them:

 a) compile coverage
 b) starting point for machine support

So it all depends on what you consider to be more important.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From josh.wu at atmel.com  Wed Aug 29 06:11:33 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Wed, 29 Aug 2012 18:11:33 +0800
Subject: [PATCH] [media] atmel_isi: allocate memory to store the isi platform
 data.
Message-ID: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>

This patch fix the bug: ISI driver's platform data became invalid when isi platform data's attribution is __initdata.

If the isi platform data is passed as __initdata. Then we need store it in driver allocated memory. otherwise when we use it out of the probe() function, then the isi platform data is invalid.

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
 drivers/media/platform/soc_camera/atmel-isi.c |   12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
index ec3f6a0..dc0fdec 100644
--- a/drivers/media/platform/soc_camera/atmel-isi.c
+++ b/drivers/media/platform/soc_camera/atmel-isi.c
@@ -926,6 +926,7 @@ static int __devexit atmel_isi_remove(struct platform_device *pdev)
 	clk_put(isi->mck);
 	clk_unprepare(isi->pclk);
 	clk_put(isi->pclk);
+	kfree(isi->pdata);
 	kfree(isi);
 
 	return 0;
@@ -968,8 +969,15 @@ static int __devinit atmel_isi_probe(struct platform_device *pdev)
 		goto err_alloc_isi;
 	}
 
+	isi->pdata = kzalloc(sizeof(struct isi_platform_data), GFP_KERNEL);
+	if (!isi->pdata) {
+		ret = -ENOMEM;
+		dev_err(&pdev->dev, "Can't allocate isi platform data!\n");
+		goto err_alloc_isi_pdata;
+	}
+	memcpy(isi->pdata, pdata, sizeof(struct isi_platform_data));
+
 	isi->pclk = pclk;
-	isi->pdata = pdata;
 	isi->active = NULL;
 	spin_lock_init(&isi->lock);
 	init_waitqueue_head(&isi->vsync_wq);
@@ -1073,6 +1081,8 @@ err_set_mck_rate:
 err_clk_prepare_mck:
 	clk_put(isi->mck);
 err_clk_get:
+	kfree(isi->pdata);
+err_alloc_isi_pdata:
 	kfree(isi);
 err_alloc_isi:
 	clk_unprepare(pclk);
-- 
1.7.9.5



From alexander.shishkin at linux.intel.com  Wed Aug 29 06:18:10 2012
From: alexander.shishkin at linux.intel.com (Alexander Shishkin)
Date: Wed, 29 Aug 2012 13:18:10 +0300
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <20120829081020.GX26594@pengutronix.de>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829081020.GX26594@pengutronix.de>
Message-ID: <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>

Sascha Hauer <s.hauer at pengutronix.de> writes:

> On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
>> Richard Zhao <richard.zhao at freescale.com> writes:
>> 
>> > i.MX usb controllers shares non-core registers, which may include
>> > SoC specific controls. We take it as a usbmisc device and usbmisc
>> > driver set operations needed by ci13xxx_imx driver.
>> >
>> > For example, Sabrelite board has bad over-current design, we can
>> > usbmisc to disable over-current detect.
>> 
>> Why does this have to be part of the usb driver instead of SoC specific
>> code? It looks like you've created a whole new device/driver
>> infrastructure just to disable overcurrent for a specific board.
>
> Richards code indeed only handles overcurrent for a specific board, but
> there are more bits to configure in the longer run: power pin
> polarities, ULPI/serial mode select and some more.

Sounds to me like these things that should be taken care of by the phy
driver, which will likely be simpler from both driver's and devicetree's
perspective.

>
>> 
>> And the infrastructure boils down to a complex way of passing a callback
>> from imx driver to another imx driver, that only works if they are
>> probed in the right order. I don't see any point in doing it like this
>> other than inflating the device tree tables even further.
>> 
>> Why can't this be part of the SoC code like it is done, for example in
>> arch/arm/mach-omap2/control.c?
>
> The settings are board specific, so there must be some way to configure
> them in the devicetree.

But I'm sure there's a way to control board-specific settings/kludges
from devicetree?

Regards,
--
Alex


From richard.zhao at freescale.com  Wed Aug 29 06:37:28 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 18:37:28 +0800
Subject: [PATCH v2 04/11] USB: chipidea: clear gadget struct at udc_start
 fail path
In-Reply-To: <87pq6ajalz.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-5-git-send-email-richard.zhao@freescale.com>
 <87oblv2zdc.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828090942.GX4011@b20223-02.ap.freescale.net>
 <87y5kyjfa3.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829082254.GH4011@b20223-02.ap.freescale.net>
 <87pq6ajalz.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829103728.GA25433@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 12:44:40PM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > On Wed, Aug 29, 2012 at 11:03:48AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > On Tue, Aug 28, 2012 at 11:29:35AM +0300, Alexander Shishkin wrote:
> >> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> >> 
> >> >> > States in gadget are not needed any more, set it to zero.
> >> >> 
> >> >> It's generally a good practice to mention in the commit message what is
> >> >> it that you are fixing with this patch.
> >> > It fixes the following dump if udc_start register gadget->dev but fail
> >> > the start process:
> >> > kobject (bf8330a0): tried to init an initialized object, something is seriously wrong.
> >> > [<80011d90>] (dump_backtrace+0x0/0x10c) from [<804b65ac>] (dump_stack+0x18/0x1c)
> >> > [<804b6594>] (dump_stack+0x0/0x1c) from [<80247d98>] (kobject_init+0x7c/0x9c)
> >> > [<80247d1c>] (kobject_init+0x0/0x9c) from [<802a3870>] (device_initialize+0x28/0x70)
> >> > [<802a3848>] (device_initialize+0x0/0x70) from [<802a4798>] (device_register+0x14/0x20)
> >> > [<802a4784>] (device_register+0x0/0x20) from [<80359a70>] (udc_start+0x180/0x2c8)
> >> > [<803598f0>] (udc_start+0x0/0x2c8) from [<80356e9c>] (ci_role_work+0xc8/0xec)
> >> > [<80356dd4>] (ci_role_work+0x0/0xec) from [<8003a8a0>] (process_one_work+0x158/0x474)
> >> > [<8003a748>] (process_one_work+0x0/0x474) from [<8003af6c>] (worker_thread+0x140/0x3b4)
> >> > [<8003ae2c>] (worker_thread+0x0/0x3b4) from [<8003fe60>] (kthread+0x90/0x9c)
> >> > [<8003fdd0>] (kthread+0x0/0x9c) from [<8002774c>] (do_exit+0x0/0x350)
> >> >> 
> >> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> >> >> > ---
> >> >> >  drivers/usb/chipidea/udc.c |    1 +
> >> >> >  1 file changed, 1 insertion(+)
> >> >> >
> >> >> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> >> >> > index c7a032a..9fb6394 100644
> >> >> > --- a/drivers/usb/chipidea/udc.c
> >> >> > +++ b/drivers/usb/chipidea/udc.c
> >> >> > @@ -1746,6 +1746,7 @@ free_pools:
> >> >> >  	dma_pool_destroy(ci->td_pool);
> >> >> >  free_qh_pool:
> >> >> >  	dma_pool_destroy(ci->qh_pool);
> >> >> > +	memset(&ci->gadget, 0, sizeof(ci->gadget));
> >> >> 
> >> >> I understand that you're probably hitting "kobject already initialized"
> >> >> warning here, but I think the real problem is that this function gets
> >> >> called twice and fails the first time. Why does that happen?
> >> > I saw the dump at early stage of adding imx otg support, when there's
> >> > things not ready. I think it's less important why udc_start fail,
> >> > because no one enable imx otg before.  It's important when it fails,
> >> > the dump shows up.
> >> 
> >> I'd prefer that whenever udc_start() fails it doesn't go unnoticed,
> >> except probably for the cases when it fails due to transceiver not being
> >> ready at the probe time, which needs to be handled separately.
> > Is it related to the patch? The patch is logically right that reset the
> > status, agree?
> 
> No. This warning means that we have called udc_start() once, failed
> (thus didn't call udc_stop()) due to some unknown reason, and called it
> again at a later point in time.
If role start failed, it may have its own error message. Why do we use
such dump message to tell something wrong? And once the role start failed,
it also prevent re-trying if ID pin switch to the role again. If you
think we don't need the retrying, it's ok to drop this patch.

Thanks
Richard
> This -- failing for unknown reason --
> should not happen. If it does, we should fix the reason, not paper over
> the warning that is telling us that something is wrong.
> 
> If we decide that we want to allow udc_start to fail for *certain*
> reasons, we should do it explicitly, not by shutting up all warnings for
> good.
> 
> Regards,
> --
> Alex
> 



From thomas.abraham at linaro.org  Wed Aug 29 07:01:09 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:31:09 +0530
Subject: [PATCH v4 0/3] ARM: Exynos: Add support for MSHC controller
Message-ID: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>

This patch series adds Exynos5250 platform support for MSHC controllers.

Thomas Abraham (3):
  ARM: Samsung: Add support for MSHC controller clocks
  ARM: Exynos5: Add AUXDATA support for MSHC controllers
  ARM: dts: Add nodes for dw_mmc controllers for Samsung Exynos5250 platforms

 arch/arm/boot/dts/exynos5250-smdk5250.dts |   55 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   32 +++++++++++++++++
 arch/arm/mach-exynos/clock-exynos5.c      |   45 ++++++++---------------
 arch/arm/mach-exynos/include/mach/map.h   |    4 ++
 arch/arm/mach-exynos/mach-exynos5-dt.c    |    8 ++++
 5 files changed, 115 insertions(+), 29 deletions(-)



From thomas.abraham at linaro.org  Wed Aug 29 07:01:10 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:31:10 +0530
Subject: [PATCH v4 1/3] ARM: Samsung: Add support for MSHC controller clocks
In-Reply-To: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
References: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1346238072-7324-2-git-send-email-thomas.abraham@linaro.org>

Add clock instances for bus interface unit clock and card interface unit
clock of the all four MSHC controller instances.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/clock-exynos5.c |   45 ++++++++++++----------------------
 1 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e29..16d8bef 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 19),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "biu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "biu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 13),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "biu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "hsmmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "biu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_aclk_200.clk,
 		.enable		= exynos5_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 15),
 	}, {
-		.name		= "dwmci",
-		.parent		= &exynos5_clk_aclk_200.clk,
-		.enable		= exynos5_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 16),
-	}, {
 		.name		= "sata",
 		.devname	= "ahci",
 		.enable		= exynos5_clk_ip_fsys_ctrl,
@@ -1006,8 +1001,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.0",
+		.name		= "ciu",
+		.devname	= "dw_mmc.0",
 		.parent		= &exynos5_clk_dout_mmc0.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 0),
@@ -1017,8 +1012,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.1",
+		.name		= "ciu",
+		.devname	= "dw_mmc.1",
 		.parent		= &exynos5_clk_dout_mmc1.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 4),
@@ -1028,8 +1023,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.2",
+		.name		= "ciu",
+		.devname	= "dw_mmc.2",
 		.parent		= &exynos5_clk_dout_mmc2.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
@@ -1039,8 +1034,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
 	.clk	= {
-		.name		= "sclk_mmc",
-		.devname	= "exynos4-sdhci.3",
+		.name		= "ciu",
+		.devname	= "dw_mmc.3",
 		.parent		= &exynos5_clk_dout_mmc3.clk,
 		.enable		= exynos5_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
@@ -1114,14 +1109,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
 static struct clksrc_clk exynos5_clksrcs[] = {
 	{
 		.clk	= {
-			.name		= "sclk_dwmci",
-			.parent		= &exynos5_clk_dout_mmc4.clk,
-			.enable		= exynos5_clksrc_mask_fsys_ctrl,
-			.ctrlbit	= (1 << 16),
-		},
-		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-	}, {
-		.clk	= {
 			.name		= "sclk_fimd",
 			.devname	= "s3cfb.1",
 			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 29 07:01:11 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:31:11 +0530
Subject: [PATCH v4 2/3] ARM: Exynos5: Add AUXDATA support for MSHC controllers
In-Reply-To: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
References: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1346238072-7324-3-git-send-email-thomas.abraham@linaro.org>

Add entries if MSHC controllers in AUXDATA table for correct device name
initialization.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/include/mach/map.h |    4 ++++
 arch/arm/mach-exynos/mach-exynos5-dt.c  |    8 ++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9d1f3ac..7cf6738 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -172,6 +172,10 @@
 
 #define EXYNOS4_PA_HSMMC(x)		(0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI		0x12550000
+#define EXYNOS5_PA_DWMCI0		0x12200000
+#define EXYNOS5_PA_DWMCI1		0x12210000
+#define EXYNOS5_PA_DWMCI2		0x12220000
+#define EXYNOS5_PA_DWMCI3		0x12230000
 
 #define EXYNOS4_PA_HSOTG		0x12480000
 #define EXYNOS4_PA_USB_HSPHY		0x125B0000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc..ce82f30 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"s3c2440-i2c.0", NULL),
 	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
 				"s3c2440-i2c.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
+				"dw_mmc.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
+				"dw_mmc.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
+				"dw_mmc.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
+				"dw_mmc.3", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
 				"exynos4210-spi.0", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Wed Aug 29 07:01:12 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:31:12 +0530
Subject: [PATCH v4 3/3] ARM: dts: Add nodes for dw_mmc controllers for Samsung
 Exynos5250 platforms
In-Reply-To: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
References: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1346238072-7324-4-git-send-email-thomas.abraham@linaro.org>

Add device nodes for the four instances of dw_mmc controllers in Exynos5250
and enable instance 0 and 2 for the smdk5250 board.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   55 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   32 +++++++++++++++++
 2 files changed, 87 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..d57e8e0 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -16,6 +16,13 @@
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
 	compatible = "samsung,smdk5250", "samsung,exynos5250";
 
+	aliases {
+		mshc0 = &dwmmc_0;
+		mshc1 = &dwmmc_1;
+		mshc2 = &dwmmc_2;
+		mshc3 = &dwmmc_3;
+	};
+
 	memory {
 		reg = <0x40000000 0x80000000>;
 	};
@@ -72,6 +79,54 @@
 		status = "disabled";
 	};
 
+	dwmmc_0: dwmmc0 at 12200000 {
+		num-slots = <1>;
+		supports-highspeed;
+		broken-cd;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <8>;
+			gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+				<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+				<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
+				<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+				<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
+		};
+	};
+
+	dwmmc_1: dwmmc1 at 12210000 {
+		status = "disabled";
+	};
+
+	dwmmc_2: dwmmc2 at 12220000 {
+		num-slots = <1>;
+		supports-highspeed;
+		fifo-depth = <0x80>;
+		card-detect-delay = <200>;
+		samsung,dw-mshc-sdr-timing = <2 3 3>;
+		samsung,dw-mshc-ddr-timing = <1 2 3>;
+
+		slot at 0 {
+			reg = <0>;
+			bus-width = <4>;
+			samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+			gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+				<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+				<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
+				<&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
+				<&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
+		};
+	};
+
+	dwmmc_3: dwmmc3 at 12230000 {
+		status = "disabled";
+	};
+
 	spi_0: spi at 12d20000 {
 		status = "disabled";
 	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8..f69e389 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -182,6 +182,38 @@
 		#size-cells = <0>;
 	};
 
+	dwmmc0 at 12200000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc1 at 12210000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc2 at 12220000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	dwmmc3 at 12230000 {
+		compatible = "samsung,exynos5250-dw-mshc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.6.6.rc2



From richard.zhao at freescale.com  Wed Aug 29 06:46:00 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 18:46:00 +0800
Subject: [PATCH v2 05/11] USB: chipidea: don't let probe fail if otg
 controller start one role failed
In-Reply-To: <87mx1ejag0.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137397-32374-1-git-send-email-richard.zhao@freescale.com>
 <1346137397-32374-6-git-send-email-richard.zhao@freescale.com>
 <87ligz2yyo.fsf@ashishki-desk.ger.corp.intel.com>
 <20120828092730.GY4011@b20223-02.ap.freescale.net>
 <87vcg2jeyu.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829083337.GI4011@b20223-02.ap.freescale.net>
 <87mx1ejag0.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829104559.GB25433@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 12:48:15PM +0300, Alexander Shishkin wrote:
> Richard Zhao <richard.zhao at freescale.com> writes:
> 
> > On Wed, Aug 29, 2012 at 11:10:33AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > On Tue, Aug 28, 2012 at 11:38:23AM +0300, Alexander Shishkin wrote:
> >> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> >> 
> >> >> > One role failed, but the other role will possiblly still work.
> >> >> > For example, when udc start failed, if plug in a host device,
> >> >> > it works.
> >> >> 
> >> >> If you're a host device, ci->role should be HOST at this point and
> >> >> ci_role_start() shouldn't fail. If ci->role is detected wrongly, the
> >> >> role detection must be fixed. If ci_role_start() fails for host, but it
> >> >> still works when it's called again after the id pin change is detected,
> >> >> again, the problem is elsewhere.
> >> > The check is only for OTG device. For single role device, it just fail
> >> > if it start the role failed.
> >> 
> >> Sorry, can you rephrase?
> >> 
> >> >> 
> >> >> >
> >> >> > Signed-off-by: Richard Zhao <richard.zhao at freescale.com>
> >> >> > ---
> >> >> >  drivers/usb/chipidea/core.c |    7 +++++--
> >> >> >  1 file changed, 5 insertions(+), 2 deletions(-)
> >> >> >
> >> >> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> >> >> > index 19ef324..8fd390a 100644
> >> >> > --- a/drivers/usb/chipidea/core.c
> >> >> > +++ b/drivers/usb/chipidea/core.c
> >> >> > @@ -473,8 +473,11 @@ static int __devinit ci_hdrc_probe(struct platform_device *pdev)
> >> >> >  	ret = ci_role_start(ci, ci->role);
> >> >> >  	if (ret) {
> >> >> >  		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
> >> >> > -		ret = -ENODEV;
> >> >> > -		goto rm_wq;
> >> >> > +		ci->role = CI_ROLE_END;
> >> >> 
> >> >> So are you relying on id pin interrupt for initializing the role after
> >> >> this? Can you provide more details?
> >> > Yes. The ID pin detect still works. My case is, gadget role failed,
> >> > host role works. I was trying not to ruin host function.
> >> 
> >> But it shouldn't even try to start the gadget, because ci_otg_role()
> >> should set ci->role to HOST before ci_role_start() happens.
> > It depends on ID pin. If ID pin is gadget and gadget is not support well,
> > ci_role_start will fail. See below example.
> >> 
> >> Another question is, why does gadget start fail?
> > There's one example:
> > If usb phy don't support otg yet, otg_set_peripheral will fail, and
> > then cause udc_start fail.
> 
> So you should drop the CI13XXX_REQUIRE_TRANSCEIVER flag from imx
> platform data till the phy is fully implemented.
It's just an example. We can not assume udc_start always success. If it
fails, isn't it better to continue support of host than say game over?

Thanks
Richard
> 
> Regards,
> --
> Alex
> 



From richard.zhao at freescale.com  Wed Aug 29 06:57:21 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 29 Aug 2012 18:57:21 +0800
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829081020.GX26594@pengutronix.de>
 <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829105720.GC25433@b20223-02.ap.freescale.net>

On Wed, Aug 29, 2012 at 01:18:10PM +0300, Alexander Shishkin wrote:
> Sascha Hauer <s.hauer at pengutronix.de> writes:
> 
> > On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > i.MX usb controllers shares non-core registers, which may include
> >> > SoC specific controls. We take it as a usbmisc device and usbmisc
> >> > driver set operations needed by ci13xxx_imx driver.
> >> >
> >> > For example, Sabrelite board has bad over-current design, we can
> >> > usbmisc to disable over-current detect.
> >> 
> >> Why does this have to be part of the usb driver instead of SoC specific
> >> code? It looks like you've created a whole new device/driver
> >> infrastructure just to disable overcurrent for a specific board.
> >
> > Richards code indeed only handles overcurrent for a specific board, but
> > there are more bits to configure in the longer run: power pin
> > polarities, ULPI/serial mode select and some more.
> 
> Sounds to me like these things that should be taken care of by the phy
> driver, which will likely be simpler from both driver's and devicetree's
> perspective.
No, it's controlled by a set of usb misc registers, which is not in phy
IP or usb controller IP.

Thanks
Richard
> 
> >
> >> 
> >> And the infrastructure boils down to a complex way of passing a callback
> >> from imx driver to another imx driver, that only works if they are
> >> probed in the right order. I don't see any point in doing it like this
> >> other than inflating the device tree tables even further.
> >> 
> >> Why can't this be part of the SoC code like it is done, for example in
> >> arch/arm/mach-omap2/control.c?
> >
> > The settings are board specific, so there must be some way to configure
> > them in the devicetree.
> 
> But I'm sure there's a way to control board-specific settings/kludges
> from devicetree?
> 
> Regards,
> --
> Alex
> 



From thomas.abraham at linaro.org  Wed Aug 29 07:01:18 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:31:18 +0530
Subject: [PATCH v3 1/4] ARM: EXYNOS: Add set_irq_affinity function for
 combiner_irq
In-Reply-To: <1346202897-27306-2-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-2-git-send-email-chanho61.park@samsung.com>
Message-ID: <CAJuYYwRab+BvZhE+vcUGtsrfpxHW_LfhtHGYj3W6eX6TjEFbvA@mail.gmail.com>

On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com> wrote:
> This patch adds set_irq_affinity function for combiner_irq. We need this
> function to enable a arm-pmu because the pmu of exynos has combined type irqs.
>
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>

>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 4eb39cd..f194bbc 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -405,6 +405,7 @@ struct combiner_chip_data {
>         unsigned int irq_offset;
>         unsigned int irq_mask;
>         void __iomem *base;
> +       unsigned int parent_irq;
>  };
>
>  static struct irq_domain *combiner_irq_domain;
> @@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
>         chained_irq_exit(chip, desc);
>  }
>
> +#ifdef CONFIG_SMP
> +static int combiner_set_affinity(struct irq_data *d,
> +                                const struct cpumask *mask_val, bool force)
> +{
> +       struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
> +       struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
> +       struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
> +
> +       if (chip && chip->irq_set_affinity)
> +               return chip->irq_set_affinity(data, mask_val, force);
> +       else
> +               return -EINVAL;
> +}
> +#endif
> +
>  static struct irq_chip combiner_chip = {
> -       .name           = "COMBINER",
> -       .irq_mask       = combiner_mask_irq,
> -       .irq_unmask     = combiner_unmask_irq,
> +       .name                   = "COMBINER",
> +       .irq_mask               = combiner_mask_irq,
> +       .irq_unmask             = combiner_unmask_irq,
> +#ifdef CONFIG_SMP
> +       .irq_set_affinity       = combiner_set_affinity,
> +#endif
>  };
>
>  static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
> @@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
>  }
>
>  static void __init combiner_init_one(unsigned int combiner_nr,
> -                                    void __iomem *base)
> +                                    void __iomem *base, unsigned int irq)
>  {
>         combiner_data[combiner_nr].base = base;
>         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
>                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
>         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
> +       combiner_data[combiner_nr].parent_irq = irq;
>
>         /* Disable all interrupts */
>         __raw_writel(combiner_data[combiner_nr].irq_mask,
> @@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem *combiner_base,
>         }
>
>         for (i = 0; i < max_nr; i++) {
> -               combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
>                 irq = IRQ_SPI(i);
>  #ifdef CONFIG_OF
>                 if (np)
>                         irq = irq_of_parse_and_map(np, i);
>  #endif
> +               combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
>                 combiner_cascade_irq(i, irq);
>         }
>  }
> --
> 1.7.9.5
>


From s.hauer at pengutronix.de  Wed Aug 29 07:01:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 29 Aug 2012 13:01:37 +0200
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829081020.GX26594@pengutronix.de>
 <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>
Message-ID: <20120829110137.GA26594@pengutronix.de>

On Wed, Aug 29, 2012 at 01:18:10PM +0300, Alexander Shishkin wrote:
> Sascha Hauer <s.hauer at pengutronix.de> writes:
> 
> > On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
> >> Richard Zhao <richard.zhao at freescale.com> writes:
> >> 
> >> > i.MX usb controllers shares non-core registers, which may include
> >> > SoC specific controls. We take it as a usbmisc device and usbmisc
> >> > driver set operations needed by ci13xxx_imx driver.
> >> >
> >> > For example, Sabrelite board has bad over-current design, we can
> >> > usbmisc to disable over-current detect.
> >> 
> >> Why does this have to be part of the usb driver instead of SoC specific
> >> code? It looks like you've created a whole new device/driver
> >> infrastructure just to disable overcurrent for a specific board.
> >
> > Richards code indeed only handles overcurrent for a specific board, but
> > there are more bits to configure in the longer run: power pin
> > polarities, ULPI/serial mode select and some more.
> 
> Sounds to me like these things that should be taken care of by the phy
> driver, which will likely be simpler from both driver's and devicetree's
> perspective.

Most i.MX SoCs have three instances of the chipidea core. These cores
share a single register space for controlling the mentioned bits (the
usbmisc register space). The usbmisc looks different on the different
SoCs.
Indeed they control some phy specific aspects, but the phy itself may
also be an external ULPI or UTMI phy with a separate driver. So if we
integrate the usbmisc into the phy wouldn't that mean that it has to
be integrated into all possible phy drivers?

>From a devicetrees perspective it makes sense to integrate the flags
into the chipidea nodes, because there is one node per chipidea core,
but only one usbmisc unit for all ports on the SoC. So we can do a:

	chipidea at ofs {
		disable-overcurrent = <1>;
	};

instead of

	usbmisc at ofs {
		disable-overcurrent-port0 = <1>;
		disable-overcurrent-port1 = <0>;
		...
	};

> 
> >
> >> 
> >> And the infrastructure boils down to a complex way of passing a callback
> >> from imx driver to another imx driver, that only works if they are
> >> probed in the right order. I don't see any point in doing it like this
> >> other than inflating the device tree tables even further.
> >> 
> >> Why can't this be part of the SoC code like it is done, for example in
> >> arch/arm/mach-omap2/control.c?
> >
> > The settings are board specific, so there must be some way to configure
> > them in the devicetree.
> 
> But I'm sure there's a way to control board-specific settings/kludges
> from devicetree?

Hm, yes. That's what Richard does, right? I may be misunderstanding you
here.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sangsu4u.park at samsung.com  Wed Aug 29 07:06:32 2012
From: sangsu4u.park at samsung.com (Sangsu Park)
Date: Wed, 29 Aug 2012 20:06:32 +0900
Subject: [PATCH] ASoC: SAMSUNG: Add SND_SOC_DAIFMT_CONT option for
 snd_soc_set_fmt()
In-Reply-To: <20120827204550.GA4400@opensource.wolfsonmicro.com>
References: <003101cd8367$3476e650$9d64b2f0$@samsung.com>
 <20120827204550.GA4400@opensource.wolfsonmicro.com>
Message-ID: <001d01cd85d6$59298040$0b7c80c0$@samsung.com>

On Sun, Aug 26, 2012 at 05:45:54PM +0900, Mark Brown wrote:
> On Sun, Aug 26, 2012 at 05:45:54PM +0900,  ?    wrote:
> > SND_SOC_DAIFMT_CONT option is now needed because of below commit:
> >
> > ASoC: Allow DAI formats to be specified in the dai_link
> 
> Clearly it's not a direct consequence of this commit, that just introduces a new optional facility
> which...
OK, I'll change it.
> 
> >  	/* Set the cpu DAI configuration */
> >  	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B
> > +				| SND_SOC_DAIFMT_CONT
> >  				| SND_SOC_DAIFMT_IB_NF
> >  				| SND_SOC_DAIFMT_CBS_CFS);
> 
> ...isn't being used by the driver.
> 
> Looking at the above it looks like the PCM driver is doing something very odd - _CONT doesn't make
> a whole lot of sense on the slave side, it's related to the clock generation so should have no
> effect at all on the slave side.  The driver code looks reasonably sensible though.
You mean cpu side is slave? 
And I think that pcm driver can be changed to solve this issue.
> 
> What specifically is going wrong here?
SND_SOC_DAIFMT_CONT is used sound/soc/Samsung/pcm.c (s3c_pcm_set_fmt()) like below.

switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
        case SND_SOC_DAIFMT_CONT:
                pcm->idleclk = 1;
                break;
        case SND_SOC_DAIFMT_GATED:
                pcm->idleclk = 0;
                break;
        default:
                dev_err(pcm->dev, "Invalid Clock gating request!\n");
                ret = -EINVAL;
                goto exit;
        }

If fmt argument has no SND_SOC_DAIFMT_ option, s3c_pcm_set_fmt() return -EINVAL.

> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From thomas.abraham at linaro.org  Wed Aug 29 07:09:35 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:39:35 +0530
Subject: [PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412
In-Reply-To: <1346202897-27306-3-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-3-git-send-email-chanho61.park@samsung.com>
Message-ID: <CAJuYYwSH19-GmNo7jZyXd9TC4VeKGxVCd=N0Vi4=kUNZPZNx6g@mail.gmail.com>

On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com> wrote:
> This patch corrects combined IRQs for exynos4412 platform. The exynos4412 has
> four extra combined irq group. Each irq is mapped to IRQ_SPI(xx). Unfortunately,
> extra combined IRQs isn't sequential. So, we need to map the irq manually.
>
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   31 ++++++++++++++++++++++++------
>  arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
>  2 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index f194bbc..be61564 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -560,23 +560,39 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
>         .map    = combiner_irq_domain_map,
>  };
>
> +static unsigned int get_combiner_extra_irq(int group)
> +{
> +       switch (group) {
> +       case 16:
> +               return IRQ_SPI(107);
> +       case 17:
> +               return IRQ_SPI(108);
> +       case 18:
> +               return IRQ_SPI(48);
> +       case 19:
> +               return IRQ_SPI(42);
> +       default:
> +               return 0;
> +       }
> +}
> +
>  static void __init combiner_init(void __iomem *combiner_base,
>                                  struct device_node *np)
>  {
>         int i, irq, irq_base;
>         unsigned int max_nr, nr_irq;
>
> +       max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> +                                       EXYNOS4_MAX_COMBINER_NR;
> +
>         if (np) {
>                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
>                         pr_warning("%s: number of combiners not specified, "
>                                 "setting default as %d.\n",
> -                               __func__, EXYNOS4_MAX_COMBINER_NR);
> -                       max_nr = EXYNOS4_MAX_COMBINER_NR;
> +                               __func__, max_nr);
>                 }
> -       } else {
> -               max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> -                                               EXYNOS4_MAX_COMBINER_NR;
>         }
> +
>         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;

Along with this change, this patch should update the default value
"samsung,combiner-nr" binding in device tree binding documentation for
combiner. It should state that is Exynos5 will use 32 and Exynos4 will
use 20 as the default value.

>
>         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
> @@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem *combiner_base,
>         }
>
>         for (i = 0; i < max_nr; i++) {
> -               irq = IRQ_SPI(i);
> +               if (i < 16 || soc_is_exynos5250())
> +                       irq = IRQ_SPI(i);
> +               else
> +                       irq = get_combiner_extra_irq(i);
>  #ifdef CONFIG_OF
>                 if (np)
>                         irq = irq_of_parse_and_map(np, i);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 35bced6..357ed7f 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -165,7 +165,7 @@
>  #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
>  #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
>
> -#define EXYNOS4_MAX_COMBINER_NR                16
> +#define EXYNOS4_MAX_COMBINER_NR                20

Will this not break Exynos4210 which has only 16 combiners? This is
fine in case max-combiner values is listed in dt mode, but in non-dt
mode or if max-combiner is not specified in dt, this will not be
correct.

>
>  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
>  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
> --
> 1.7.9.5
>


From b29396 at freescale.com  Wed Aug 29 06:56:51 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:51 +0800
Subject: [PATCH v4 0/7] add syscon driver based on regmap for general
 registers access
Message-ID: <1346237818-9498-1-git-send-email-b29396@freescale.com>

This patch series mainly adds an syscon driver which is used to access
general system controller registers like FSL IOMUXC GPR and ANATOP,
after that, we convert all the exist private access general registers code to use
standard API from regmap to access registers.
Finally we remove the old mfd anatop driver which is only for anatop register
access.

The patch series is based on linus's tree 3.6-rc3 since commit 9160338.

ChangeLog v3->v4:
Only '[PATCH v4 1/7] mfd: add syscon driver based on regmap' is changed.

Dong Aisheng (7):
  mfd: add syscon driver based on regmap
  ARM: imx6q: add iomuxc gpr support into syscon
  ARM: imx6q: add anatop support into syscon
  regulator: anatop-regulator: convert to use syscon to access anatop
    register
  ARM: imx6q: convert to use syscon to access anatop registers
  ARM: dts: imx6q: add simple-bus compatible string for anatop
  mfd: anatop-mfd: remove anatop driver

 Documentation/devicetree/bindings/mfd/syscon.txt |   20 ++
 arch/arm/boot/dts/imx6q.dtsi                     |    9 +-
 arch/arm/mach-imx/Kconfig                        |    2 +-
 arch/arm/mach-imx/mach-imx6q.c                   |   47 ++--
 drivers/mfd/Kconfig                              |   13 +-
 drivers/mfd/Makefile                             |    2 +-
 drivers/mfd/anatop-mfd.c                         |  124 ---------
 drivers/mfd/syscon.c                             |  170 ++++++++++++
 drivers/regulator/Kconfig                        |    2 +-
 drivers/regulator/anatop-regulator.c             |   30 ++-
 include/linux/fsl/imx6q-iomuxc-gpr.h             |  319 ++++++++++++++++++++++
 include/linux/mfd/anatop.h                       |   40 ---
 include/linux/mfd/syscon.h                       |   23 ++
 13 files changed, 586 insertions(+), 215 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/syscon.txt
 delete mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 drivers/mfd/syscon.c
 create mode 100644 include/linux/fsl/imx6q-iomuxc-gpr.h
 delete mode 100644 include/linux/mfd/anatop.h
 create mode 100644 include/linux/mfd/syscon.h




From b29396 at freescale.com  Wed Aug 29 06:56:52 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:52 +0800
Subject: [PATCH v4 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-2-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Add regmap based syscon driver.
This is usually used for access misc bits in registers which does not belong
to a specific module, for example, IMX IOMUXC GPR and ANATOP.
With this driver, client can use generic regmap API to access registers
which are registered into syscon.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog:
v3->v4:
 * add more description about syscon(provided by Stephen Warren) in binding doc.
 * fix a minor code indent error and remove set cache type code since the cache
   is disabled by default.
v2->v3:
 * export regmap lookup APIs including syscon_node_to_regmap
 * fix a few typo
v1->v2:
 * provide a way of retrieving the regmap, suggested by Mark Brown.
 * delete imx-syscon io accessors and using generic regmap API for client drivers.
 * change to a more generic name for other SoCs to use.
---
 Documentation/devicetree/bindings/mfd/syscon.txt |   20 +++
 drivers/mfd/Kconfig                              |    7 +
 drivers/mfd/Makefile                             |    1 +
 drivers/mfd/syscon.c                             |  170 ++++++++++++++++++++++
 include/linux/mfd/syscon.h                       |   23 +++
 5 files changed, 221 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
new file mode 100644
index 0000000..fe8150b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -0,0 +1,20 @@
+* System Controller Registers R/W driver
+
+System controller node represents a register region containing a set
+of miscellaneous registers. The registers are not cohesive enough to
+represent as any specific type of device. The typical use-case is for
+some other node's driver, or platform-specific code, to acquire a
+reference to the syscon node (e.g. by phandle, node path, or search
+using a specific compatible value), interrogate the node (or associated
+OS driver) to determine the location of the registers, and access the
+registers directly.
+
+Required properties:
+- compatible: Should contain "syscon".
+- reg: the register region can be accessed from syscon
+
+Examples:
+gpr: iomuxc-gpr at 020e0000 {
+	compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+	reg = <0x020e0000 0x38>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b1a1462..2b53ed8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -993,6 +993,13 @@ config MFD_ANATOP
 	  MFD controller. This controller embeds regulator and
 	  thermal devices for Freescale i.MX platforms.
 
+config MFD_SYSCON
+        bool "System Controller Register R/W Based on Regmap"
+        select REGMAP_MMIO
+        help
+	  Select this option to enable accessing system control registers
+	  via regmap.
+
 config MFD_PALMAS
 	bool "Support for the TI Palmas series chips"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..8384bc9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
 obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
+obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
new file mode 100644
index 0000000..561c2ae
--- /dev/null
+++ b/drivers/mfd/syscon.c
@@ -0,0 +1,170 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct platform_driver syscon_driver;
+
+struct syscon {
+	struct device *dev;
+	void __iomem *base;
+	struct regmap *regmap;
+};
+
+static int syscon_match(struct device *dev, void *data)
+{
+	struct syscon *syscon = dev_get_drvdata(dev);
+	struct device_node *dn = data;
+
+	return (syscon->dev->of_node == dn) ? 1 : 0;
+}
+
+struct regmap *syscon_node_to_regmap(struct device_node *np)
+{
+	struct syscon *syscon;
+	struct device *dev;
+
+	dev = driver_find_device(&syscon_driver.driver, NULL, np,
+				 syscon_match);
+	of_node_put(np);
+
+	if (!dev)
+		return ERR_PTR(-EPROBE_DEFER);
+
+	syscon = dev_get_drvdata(dev);
+
+	return syscon->regmap;
+}
+EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
+
+struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_find_compatible_node(NULL, NULL, s);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
+
+struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
+					const char *property)
+{
+	struct device_node *syscon_np;
+
+	syscon_np = of_parse_phandle(np, property, 0);
+	if (!syscon_np)
+		return ERR_PTR(-ENODEV);
+
+	return syscon_node_to_regmap(syscon_np);
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle);
+
+static const struct of_device_id of_syscon_match[] = {
+	{ .compatible = "syscon", },
+	{ },
+};
+
+static struct regmap_config syscon_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int __devinit syscon_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct syscon *syscon;
+	struct resource res;
+	int ret;
+
+	if (!np)
+		return -ENOENT;
+
+	syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
+			    GFP_KERNEL);
+	if (!syscon)
+		return -ENOMEM;
+
+	syscon->base = of_iomap(np, 0);
+	if (!syscon->base)
+		return -EADDRNOTAVAIL;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	syscon_regmap_config.max_register = res.end - res.start - 3;
+	syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
+					&syscon_regmap_config);
+	if (IS_ERR(syscon->regmap)) {
+		dev_err(&pdev->dev, "regmap init failed\n");
+		return PTR_ERR(syscon->regmap);
+	}
+
+	syscon->dev = &pdev->dev;
+	platform_set_drvdata(pdev, syscon);
+
+	dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
+		res.start, res.end);
+
+	return 0;
+}
+
+static int __devexit syscon_remove(struct platform_device *pdev)
+{
+	struct syscon *syscon;
+
+	syscon = platform_get_drvdata(pdev);
+	iounmap(syscon->base);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver syscon_driver = {
+	.driver = {
+		.name = "syscon",
+		.owner = THIS_MODULE,
+		.of_match_table = of_syscon_match,
+	},
+	.probe		= syscon_probe,
+	.remove		= __devexit_p(syscon_remove),
+};
+
+static int __init syscon_init(void)
+{
+	return platform_driver_register(&syscon_driver);
+}
+postcore_initcall(syscon_init);
+
+static void __exit syscon_exit(void)
+{
+	platform_driver_unregister(&syscon_driver);
+}
+module_exit(syscon_exit);
+
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("System Control driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
new file mode 100644
index 0000000..6aeb6b8
--- /dev/null
+++ b/include/linux/mfd/syscon.h
@@ -0,0 +1,23 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_MFD_SYSCON_H__
+#define __LINUX_MFD_SYSCON_H__
+
+extern struct regmap *syscon_node_to_regmap(struct device_node *np);
+extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
+extern struct regmap *syscon_regmap_lookup_by_phandle(
+					struct device_node *np,
+					const char *property);
+#endif /* __LINUX_MFD_SYSCON_H__ */
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:54 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:54 +0800
Subject: [PATCH v4 3/7] ARM: imx6q: add anatop support into syscon
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-4-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

There're a few anatop registers need to be accessed by different modules.
Add anatop registers into syscon support for easy access.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bea21bc..db3fa15 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -378,8 +378,8 @@
 				interrupts = <0 87 0x04 0 88 0x04>;
 			};
 
-			anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop";
+			anatop: anatop at 020c8000 {
+				compatible = "fsl,imx6q-anatop", "syscon";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:53 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:53 +0800
Subject: [PATCH v4 2/7] ARM: imx6q: add iomuxc gpr support into syscon
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-3-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Include headfile for easy using.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi         |    5 +
 include/linux/fsl/imx6q-iomuxc-gpr.h |  319 ++++++++++++++++++++++++++++++++++
 2 files changed, 324 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..bea21bc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -507,6 +507,11 @@
 				interrupts = <0 89 0x04 0 90 0x04>;
 			};
 
+			gpr: iomuxc-gpr at 020e0000 {
+				compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+				reg = <0x020e0000 0x38>;
+			};
+
 			iomuxc at 020e0000 {
 				compatible = "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
diff --git a/include/linux/fsl/imx6q-iomuxc-gpr.h b/include/linux/fsl/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..2c44573
--- /dev/null
+++ b/include/linux/fsl/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0	0x00
+#define IOMUXC_GPR1	0x04
+#define IOMUXC_GPR2	0x08
+#define IOMUXC_GPR3	0x0c
+#define IOMUXC_GPR4	0x10
+#define IOMUXC_GPR5	0x14
+#define IOMUXC_GPR6	0x18
+#define IOMUXC_GPR7	0x1c
+#define IOMUXC_GPR8	0x20
+#define IOMUXC_GPR9	0x24
+#define IOMUXC_GPR10	0x28
+#define IOMUXC_GPR11	0x2c
+#define IOMUXC_GPR12	0x30
+#define IOMUXC_GPR13	0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7	(0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED	(0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR	(0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED	(0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7	(0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED	(0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2	(0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED	(0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2	(0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED	(0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1	(0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED	(0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1	(0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1	(0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2	(0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK		BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX	BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3		BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK		BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2	BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1		BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2		BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1	0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3		BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK		BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1		0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1			BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23			BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IMX6Q_GPR1_DPI_OFF			BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY			0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE			BIT(15)
+#define IMX6Q_GPR1_PCIE_INT			BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK		BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER	0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1	BIT(13)
+#define IMX6Q_GPR1_GINT				BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3			BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2			BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1			BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0			BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK	(0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5		(0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3		(0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4		(0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6		(0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK		(0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0		(0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1		(0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2		(0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3		(0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4		(0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5		(0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6		(0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7		(0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK		BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR	0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR	BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK		BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L	BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK		BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H	0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L	BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK		BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA	BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK		BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT		BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK		BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG		0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA	BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK		BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT		0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT		BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN		BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK		(0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE		(0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0	(0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1	(0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK		(0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE		(0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0	(0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK			(0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D		(0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D		(0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG		(0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL		BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL		BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL		BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL		BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK		(0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK		(0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN		BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN		BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN		BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN		BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK		BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK		BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK		BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK		(0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0	(0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1	(0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0	(0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1	(0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK		(0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0	(0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1	(0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0	(0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1	(0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0	(0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1	(0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0	(0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1	(0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL		BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL		BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL		BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL		BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL		BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL		BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL		BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL		BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK		BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK		BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK		BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK		BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK		(0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF		0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL		BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL		BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL		BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK	BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL		BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL		BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN			BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN		BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP		BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR		(0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN		BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK		(0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK		(0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN			BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN			BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK		BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY		0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE		BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK		(0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK		BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK		(0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0	(0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1	(0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0	(0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1	(0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK		(0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0	(0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1	(0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0	(0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1	(0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ		BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ		BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB		(0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB		(0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB		(0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB		(0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB		(0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB		(0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB		(0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB		(0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK		(0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M		(0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M		(0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X		(0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK		(0x7 << 16)
+#define IMX6Q_GPR13_SATA_SPEED_MASK		BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G		0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G		BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5			BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK		(0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16		(0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16		(0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16		(0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16		(0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16		(0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16		(0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK		(0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF		0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK		(0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF		0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK		(0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST		(0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
+
+#endif /* !__LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:55 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:55 +0800
Subject: [PATCH v4 4/7] regulator: anatop-regulator: convert to use syscon to
 access anatop register
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-5-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop register.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * update to use syscon_node_to_regmap and use of_get_parent to get anatop node.
ChangeLog v1-v2:
 * update to use generic regmap api
---
 drivers/regulator/Kconfig            |    2 +-
 drivers/regulator/anatop-regulator.c |   30 ++++++++++++++++++++----------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 4e932cc..2ae1d97 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -112,7 +112,7 @@ config REGULATOR_DA9052
 
 config REGULATOR_ANATOP
 	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
-	depends on MFD_ANATOP
+	depends on MFD_SYSCON
 	help
 	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
 	  regulators. It is recommended that this option be
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index ce0fe72..346e5f6 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -21,19 +21,20 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 #include <linux/module.h>
+#include <linux/mfd/syscon.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
+#include <linux/regmap.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/of_regulator.h>
 
 struct anatop_regulator {
 	const char *name;
 	u32 control_reg;
-	struct anatop *mfd;
+	struct regmap *anatop;
 	int vol_bit_shift;
 	int vol_bit_width;
 	int min_bit_val;
@@ -43,7 +44,8 @@ struct anatop_regulator {
 	struct regulator_init_data *initdata;
 };
 
-static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
+static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
+					unsigned selector)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -56,12 +58,13 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val <<= anatop_reg->vol_bit_shift;
-	anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
+	regmap_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
+				mask, val);
 
 	return 0;
 }
 
-static int anatop_get_voltage_sel(struct regulator_dev *reg)
+static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
 {
 	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
 	u32 val, mask;
@@ -69,7 +72,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 	if (!anatop_reg->control_reg)
 		return -ENOTSUPP;
 
-	val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
+	regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
 	mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
 		anatop_reg->vol_bit_shift;
 	val = (val & mask) >> anatop_reg->vol_bit_shift;
@@ -78,8 +81,8 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
 }
 
 static struct regulator_ops anatop_rops = {
-	.set_voltage_sel = anatop_set_voltage_sel,
-	.get_voltage_sel = anatop_get_voltage_sel,
+	.set_voltage_sel = anatop_regmap_set_voltage_sel,
+	.get_voltage_sel = anatop_regmap_get_voltage_sel,
 	.list_voltage = regulator_list_voltage_linear,
 	.map_voltage = regulator_map_voltage_linear,
 };
@@ -88,11 +91,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
+	struct device_node *anatop_np;
 	struct regulator_desc *rdesc;
 	struct regulator_dev *rdev;
 	struct anatop_regulator *sreg;
 	struct regulator_init_data *initdata;
-	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
 	struct regulator_config config = { };
 	int ret = 0;
 
@@ -109,7 +112,14 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	rdesc->ops = &anatop_rops;
 	rdesc->type = REGULATOR_VOLTAGE;
 	rdesc->owner = THIS_MODULE;
-	sreg->mfd = anatopmfd;
+
+	anatop_np = of_get_parent(np);
+	if (!anatop_np)
+		return -ENODEV;
+	sreg->anatop = syscon_node_to_regmap(anatop_np);
+	if (IS_ERR(sreg->anatop))
+		return PTR_ERR(sreg->anatop);
+
 	ret = of_property_read_u32(np, "anatop-reg-offset",
 				   &sreg->control_reg);
 	if (ret) {
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:56 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:56 +0800
Subject: [PATCH v4 5/7] ARM: imx6q: convert to use syscon to access anatop
 registers
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-6-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Using syscon to access anatop registers.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * remove a few unneed codes
ChangeLog v1->v2:
 * update to use generic regmap api
---
 arch/arm/mach-imx/Kconfig      |    2 +-
 arch/arm/mach-imx/mach-imx6q.c |   47 +++++++++++++++------------------------
 2 files changed, 19 insertions(+), 30 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..7bba253 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -839,7 +839,7 @@ config SOC_IMX6Q
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC
 	select HAVE_SMP
-	select MFD_ANATOP
+	select MFD_SYSCON
 	select PINCTRL
 	select PINCTRL_IMX6Q
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6..eaf56b4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,8 +24,9 @@
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
+#include <linux/regmap.h>
 #include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
 #include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -120,20 +121,7 @@ static void __init imx6q_sabrelite_init(void)
 
 static void __init imx6q_usb_init(void)
 {
-	struct device_node *np;
-	struct platform_device *pdev = NULL;
-	struct anatop *adata = NULL;
-
-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
-	if (np)
-		pdev = of_find_device_by_node(np);
-	if (pdev)
-		adata = platform_get_drvdata(pdev);
-	if (!adata) {
-		if (np)
-			of_node_put(np);
-		return;
-	}
+	struct regmap *anatop;
 
 #define HW_ANADIG_USB1_CHRG_DETECT		0x000001b0
 #define HW_ANADIG_USB2_CHRG_DETECT		0x00000210
@@ -141,20 +129,21 @@ static void __init imx6q_usb_init(void)
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x00100000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x00080000
 
-	/*
-	 * The external charger detector needs to be disabled,
-	 * or the signal at DP will be poor
-	 */
-	anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B
-			| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-	anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
-			BM_ANADIG_USB_CHRG_DETECT_EN_B |
-			BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
-			~0);
-
-	of_node_put(np);
+	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+	if (!IS_ERR(anatop)) {
+		/*
+		 * The external charger detector needs to be disabled,
+		 * or the signal at DP will be poor
+		 */
+		regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B
+				| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+		regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+				BM_ANADIG_USB_CHRG_DETECT_EN_B |
+				BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+	} else {
+		pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+	}
 }
 
 static void __init imx6q_init_machine(void)
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:58 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:58 +0800
Subject: [PATCH v4 7/7] mfd: anatop-mfd: remove anatop driver
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-8-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

The anatop registers are accessed via syscon now, no one will use
mfd anatop driver anymore, remove it.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 drivers/mfd/Kconfig        |    8 ---
 drivers/mfd/Makefile       |    1 -
 drivers/mfd/anatop-mfd.c   |  124 --------------------------------------------
 include/linux/mfd/anatop.h |   40 --------------
 4 files changed, 0 insertions(+), 173 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2b53ed8..d260e1e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -985,14 +985,6 @@ config MFD_STA2X11
 	depends on STA2X11
 	select MFD_CORE
 
-config MFD_ANATOP
-	bool "Support for Freescale i.MX on-chip ANATOP controller"
-	depends on SOC_IMX6Q
-	help
-	  Select this option to enable Freescale i.MX on-chip ANATOP
-	  MFD controller. This controller embeds regulator and
-	  thermal devices for Freescale i.MX platforms.
-
 config MFD_SYSCON
         bool "System Controller Register R/W Based on Regmap"
         select REGMAP_MMIO
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8384bc9..0f10a95 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -130,6 +130,5 @@ obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
 obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
-obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
 obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
deleted file mode 100644
index 5576e07..0000000
--- a/drivers/mfd/anatop-mfd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- * Copyright (C) 2012 Linaro
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
-
-u32 anatop_read_reg(struct anatop *adata, u32 addr)
-{
-	return readl(adata->ioreg + addr);
-}
-EXPORT_SYMBOL_GPL(anatop_read_reg);
-
-void anatop_write_reg(struct anatop *adata, u32 addr, u32 data, u32 mask)
-{
-	u32 val;
-
-	data &= mask;
-
-	spin_lock(&adata->reglock);
-	val = readl(adata->ioreg + addr);
-	val &= ~mask;
-	val |= data;
-	writel(val, adata->ioreg + addr);
-	spin_unlock(&adata->reglock);
-}
-EXPORT_SYMBOL_GPL(anatop_write_reg);
-
-static const struct of_device_id of_anatop_match[] = {
-	{ .compatible = "fsl,imx6q-anatop", },
-	{ },
-};
-
-static int __devinit of_anatop_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	void *ioreg;
-	struct anatop *drvdata;
-
-	ioreg = of_iomap(np, 0);
-	if (!ioreg)
-		return -EADDRNOTAVAIL;
-	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-	if (!drvdata)
-		return -ENOMEM;
-	drvdata->ioreg = ioreg;
-	spin_lock_init(&drvdata->reglock);
-	platform_set_drvdata(pdev, drvdata);
-	of_platform_populate(np, NULL, NULL, dev);
-
-	return 0;
-}
-
-static int __devexit of_anatop_remove(struct platform_device *pdev)
-{
-	struct anatop *drvdata;
-	drvdata = platform_get_drvdata(pdev);
-	iounmap(drvdata->ioreg);
-
-	return 0;
-}
-
-static struct platform_driver anatop_of_driver = {
-	.driver = {
-		.name = "anatop-mfd",
-		.owner = THIS_MODULE,
-		.of_match_table = of_anatop_match,
-	},
-	.probe		= of_anatop_probe,
-	.remove		= of_anatop_remove,
-};
-
-static int __init anatop_init(void)
-{
-	return platform_driver_register(&anatop_of_driver);
-}
-postcore_initcall(anatop_init);
-
-static void __exit anatop_exit(void)
-{
-	platform_driver_unregister(&anatop_of_driver);
-}
-module_exit(anatop_exit);
-
-MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
-MODULE_DESCRIPTION("ANATOP MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf..0000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * anatop.h - Anatop MFD driver
- *
- *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
- *  Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __LINUX_MFD_ANATOP_H
-#define __LINUX_MFD_ANATOP_H
-
-#include <linux/spinlock.h>
-
-/**
- * anatop - MFD data
- * @ioreg: ioremap register
- * @reglock: spinlock for register read/write
- */
-struct anatop {
-	void *ioreg;
-	spinlock_t reglock;
-};
-
-extern u32 anatop_read_reg(struct anatop *, u32);
-extern void anatop_write_reg(struct anatop *, u32, u32, u32);
-
-#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.0.4




From b29396 at freescale.com  Wed Aug 29 06:56:57 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Wed, 29 Aug 2012 18:56:57 +0800
Subject: [PATCH v4 6/7] ARM: dts: imx6q: add simple-bus compatible string for
 anatop
In-Reply-To: <1346237818-9498-1-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
Message-ID: <1346237818-9498-7-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Originally the anatop regulator devices are populated by mfd anatop driver.
Since mfd anatop driver will be deleted later, we change to populate the
regulator devices by devicetree automatically.
This will cause some warning messages as follows during boot due to device
recreation: "vdd1p1: Failed to create debugfs directory"
But it does not break any function.
Later, we will remove mfd anatop driver which can get rid of this
error message.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index db3fa15..52ed4d1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -379,7 +379,7 @@
 			};
 
 			anatop: anatop at 020c8000 {
-				compatible = "fsl,imx6q-anatop", "syscon";
+				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
-- 
1.7.0.4




From thomas.abraham at linaro.org  Wed Aug 29 07:25:09 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 29 Aug 2012 16:55:09 +0530
Subject: [PATCH v3 4/4] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
In-Reply-To: <1346202897-27306-5-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-5-git-send-email-chanho61.park@samsung.com>
Message-ID: <CAJuYYwTs=9Wx6+v46Dt+peEe3w3ytJqxXgkxBwKLq7zF5ynjnw@mail.gmail.com>

On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com> wrote:
> This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
> has two pmus which have combiner irq type.
>
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 004aaa8..45746cbf 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -52,6 +52,12 @@
>                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
>         };
>
> +       pmu {
> +               compatible = "arm,cortex-a15-pmu";
> +               interrupt-parent = <&combiner>;
> +               interrupts = <1 2>, <22 4>;
> +       };
> +
>         watchdog {
>                 compatible = "samsung,s3c2410-wdt";
>                 reg = <0x101D0000 0x100>;
> --
> 1.7.9.5
>

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>

Probably, this should be doable for Exynos4 as well.


From ludovic.desroches at atmel.com  Wed Aug 29 08:06:10 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Wed, 29 Aug 2012 14:06:10 +0200
Subject: [PATCH v11 0/4] AT91: replace old i2c-at91.c TWI driver
In-Reply-To: <cover.1346225321.git.n.voss@weinmann.de>
References: <cover.1346225321.git.n.voss@weinmann.de>
Message-ID: <503E05B2.2020204@atmel.com>

Hi Nikolaus,

Le 08/29/2012 09:28 AM, Nikolaus Voss a ?crit :
> The old driver has two main deficencies:
> i)  No repeated start (Sr) condiction is possible, this makes it unusable
>      e.g. for most SMBus transfers.
> ii) I/O was done with polling/busy waiting what caused over-/underruns
>      even at light system loads and clock speeds.
>
> The new driver overcomes these deficencies and in addition allows for
> more than one TWI interface.
>
> A remaining limitation is the fact, that only one repeated start is
> possible (two concatenated messages). This limitation is imposed by
> the hardware. However, this should not be a problem as all common
> i2c-client communication does not rely on more than one repeated start.
>
> Changes since v11:
> - corrected wrong id_entry on sam9261 twi gpio pdev
>

Thanks for this new version, you can add
Tested-By: Ludovic Desroches <ludovic.desroches at atmel.com>
for the whole series.

Concerning the open drain issue, even if I don't have it on my board 
your patch is correct it is needed also for chips. Once I'll have the 
complete list, I'll send an additional patch.

Regards

Ludovic


> Nikolaus Voss (4):
>    drivers/i2c/busses/i2c-at91.c: remove old polling driver
>    Replace clk_lookup.con_id with clk_lookup.dev_id entries for twi clk
>    drivers/i2c/busses/i2c-at91.c: add new driver
>    G45 TWI: remove open drain setting for twi function gpios
>
>   arch/arm/mach-at91/at91rm9200.c            |    1 +
>   arch/arm/mach-at91/at91rm9200_devices.c    |    9 +
>   arch/arm/mach-at91/at91sam9260.c           |    1 +
>   arch/arm/mach-at91/at91sam9261.c           |    1 +
>   arch/arm/mach-at91/at91sam9261_devices.c   |    9 +
>   arch/arm/mach-at91/at91sam9263.c           |    1 +
>   arch/arm/mach-at91/at91sam9g45.c           |    2 +
>   arch/arm/mach-at91/at91sam9g45_devices.c   |    6 -
>   arch/arm/mach-at91/at91sam9rl.c            |    2 +
>   arch/arm/mach-at91/at91sam9x5.c            |    3 +
>   arch/arm/mach-at91/include/mach/at91_twi.h |   68 ----
>   drivers/i2c/busses/Kconfig                 |   11 +-
>   drivers/i2c/busses/i2c-at91.c              |  591 ++++++++++++++++++----------
>   13 files changed, 418 insertions(+), 287 deletions(-)
>   delete mode 100644 arch/arm/mach-at91/include/mach/at91_twi.h
>



From tushar.behera at linaro.org  Wed Aug 29 08:07:13 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Wed, 29 Aug 2012 17:37:13 +0530
Subject: [PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
In-Reply-To: <CAAgF-Bdp817_RD3n6Sdo9zi=OrB4-Uiu5PDt4UB1BL-f0M4aJg@mail.gmail.com>
References: <1343218056-30432-1-git-send-email-padma.v@samsung.com>
 <031501cd6f98$dd67c550$98374ff0$%kim@samsung.com>
 <CAAgF-Bdp817_RD3n6Sdo9zi=OrB4-Uiu5PDt4UB1BL-f0M4aJg@mail.gmail.com>
Message-ID: <503E05F1.8050903@linaro.org>

On 08/01/2012 06:39 PM, Padma Venkat wrote:
> Hi,
> 
> On Wed, Aug 1, 2012 at 9:21 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> Padmavathi Venna wrote:
>>>
>>> Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
>>> board specific. So this patch adds a function to set the required
>>> audio codec clk frequency from machine file.
>>>
>>> This patch also adds all the required clock instances for audio
>>> subsystem and adds the clock alias names for i2sclk and busclk.
>>>
>>> Signed-off-by: Taylor Hutt <thutt at chromium.org>
>>> Signed-off-by: sangsu4u.park <sangsu4u.park at samsung.com>
>>> Signed-off-by: Padmavathi Venna <padma.v at samsung.com>
>>> ---
>>>  arch/arm/mach-exynos/clock-exynos5.c           |  129
>>> ++++++++++++++++++++++++
>>>  arch/arm/mach-exynos/common.h                  |    1 +
>>>  arch/arm/mach-exynos/include/mach/regs-audss.h |   12 ++
>>>  arch/arm/mach-exynos/mach-exynos5-dt.c         |    1 +
>>>  4 files changed, 143 insertions(+), 0 deletions(-)
>>>

[...]

>>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>>> @@ -69,6 +69,7 @@ static void __init exynos5250_dt_machine_init(void)
>>>  {
>>>       of_platform_populate(NULL, of_default_bus_match_table,
>>>                               exynos5250_auxdata_lookup, NULL);
>>> +     exynos5_set_audiocdclk_rate(16934400);
>>
>> As you commented, the value of clock can be changed according to the board,
>> and this file, mach-exynos5-dt.c is not only for smdk5250, now there is no
>> board for exynos5250 though.
> Please suggest me some file where I can call this function then.
>>

Will it be a good idea to split this into two patches, one adding basic
audio subsystem defines and another one adding specific support for EXYNOS5?


>> [...]
>>
>> Thanks.
>>
>> Best regards,
>> Kgene.
> 
> Thanks for your review.
> 
> Best Regards
> Padma
>> --
>> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
>> SW Solution Development Team, Samsung Electronics Co., Ltd.
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


-- 
Tushar Behera


From anilkumar at ti.com  Wed Aug 29 08:33:26 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Wed, 29 Aug 2012 12:33:26 +0000
Subject: [PATCH v4 2/4] mfd: omap: control: core system control driver
In-Reply-To: <500FD2EC.7060208@dev.rtsoft.ru>
References: <500FD2EC.7060208@dev.rtsoft.ru>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA21C6C@DBDE01.ent.ti.com>

Hi Konstantin,

On Wed, Jul 25, 2012 at 16:35:16, Konstantin Baydarov wrote:
> This patch introduces a MFD core device driver for
> OMAP system control module.
> 
> The control module allows software control of
> various static modes supported by the device. It is
> composed of two control submodules: general control
> module and device (padconfiguration) control
> module.
> 
> Device driver is probed with postcore_initcall.
> Control module register CONTROL_STATUS that is needed
> by omap_type() is early mapped by postcore_initcall_sync.
> 
> Signed-off-by: J Keerthy <j-keerthy at ti.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin at ti.com>
> Signed-off-by: Konstantin Baydarov <kbaidarov at dev.rtsoft.ru>
> ---
>  .../devicetree/bindings/mfd/omap_control.txt       |   32 ++++
>  arch/arm/mach-omap2/Kconfig                        |    1 +
>  arch/arm/plat-omap/Kconfig                         |    4 +
>  drivers/mfd/Kconfig                                |    6 +
>  drivers/mfd/Makefile                               |    1 +
>  drivers/mfd/omap-control-core.c                    |  162 ++++++++++++++++++++
>  include/linux/mfd/omap_control.h                   |   35 +++++
>  7 files changed, 241 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mfd/omap_control.txt
>  create mode 100644 drivers/mfd/omap-control-core.c
>  create mode 100644 include/linux/mfd/omap_control.h
> 
> diff --git a/Documentation/devicetree/bindings/mfd/omap_control.txt b/Documentation/devicetree/bindings/mfd/omap_control.txt
> new file mode 100644
> index 0000000..a9dca9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/omap_control.txt
> @@ -0,0 +1,32 @@
> +* Texas Instrument OMAP System Control Module (SCM) bindings
> +
> +The control module allows software control of various static modes supported by
> +the device. The control module controls the settings of various device  modules
> +through register configuration and internal signals. It also controls  the  pad
> +configuration, pin functional multiplexing, and the routing of internal signals
> +(such as PRCM  signals or DMA requests)  to output pins configured for hardware
> +observability.
> +
> +Required properties:
> +- compatible : Should be:
> +  - "ti,omap3-control" for OMAP3 support
> +  - "ti,omap4-control" for OMAP4 support
> +  - "ti,omap5-control" for OMAP5 support
> +
> +OMAP specific properties:
> +- ti,hwmods: Name of the hwmod associated to the control module:
> +  Should be "ctrl_module_core";
> +
> +OMAP CONTROL_STATUS register:
> +reg = <0x4A0022C4 0x4>; /* CONTROL_STATUS register */
> +
> +Examples:
> +ctrl_module_core: ctrl_module_core at 4A0022C4 {
> +	compatible = "ti,omap4-control";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	/* ranges; */
> +	ti,hwmods = "ctrl_module_core";
> +	reg = <0x4A0022C4 0x4>; /* CONTROL_STATUS register */
> +};
> +
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index dd0fbf7..1235576 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -59,6 +59,7 @@ config ARCH_OMAP4
>  	select ARM_ERRATA_720789
>  	select ARCH_HAS_OPP
>  	select PM_RUNTIME if CPU_IDLE
> +	select ARCH_HAS_CONTROL_MODULE
>  	select PM_OPP if PM
>  	select USB_ARCH_HAS_EHCI if USB_SUPPORT
>  	select ARM_CPU_SUSPEND if PM
> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> index dd36eba..2b2c9d8 100644
> --- a/arch/arm/plat-omap/Kconfig
> +++ b/arch/arm/plat-omap/Kconfig
> @@ -5,6 +5,10 @@ menu "TI OMAP Common Features"
>  config ARCH_OMAP_OTG
>  	bool
>  
> +config ARCH_HAS_CONTROL_MODULE
> +	bool
> +	select MFD_OMAP_CONTROL
> +
>  choice
>  	prompt "OMAP System Type"
>  	default ARCH_OMAP2PLUS
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 92144ed..530ac60 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -823,6 +823,12 @@ config MFD_WL1273_CORE
>  	  driver connects the radio-wl1273 V4L2 module and the wl1273
>  	  audio codec.
>  
> +config MFD_OMAP_CONTROL
> +	bool "Texas Instruments OMAP System control module"
> +	depends on ARCH_HAS_CONTROL_MODULE
> +	help
> +	  This is the core driver for system control module.
> +
>  config MFD_OMAP_USB_HOST
>  	bool "Support OMAP USBHS core driver"
>  	depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 75f6ed6..b037443 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -107,6 +107,7 @@ obj-$(CONFIG_MFD_TPS6586X)	+= tps6586x.o
>  obj-$(CONFIG_MFD_VX855)		+= vx855.o
>  obj-$(CONFIG_MFD_WL1273_CORE)	+= wl1273-core.o
>  obj-$(CONFIG_MFD_CS5535)	+= cs5535-mfd.o
> +obj-$(CONFIG_MFD_OMAP_CONTROL)	+= omap-control-core.o
>  obj-$(CONFIG_MFD_OMAP_USB_HOST)	+= omap-usb-host.o
>  obj-$(CONFIG_MFD_PM8921_CORE) 	+= pm8921-core.o
>  obj-$(CONFIG_MFD_PM8XXX_IRQ) 	+= pm8xxx-irq.o
> diff --git a/drivers/mfd/omap-control-core.c b/drivers/mfd/omap-control-core.c
> new file mode 100644
> index 0000000..cefbc5a
> --- /dev/null
> +++ b/drivers/mfd/omap-control-core.c
> @@ -0,0 +1,162 @@
> +/*
> + * OMAP system control module driver file
> + *
> + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Contacts:
> + * Based on original code written by:
> + *    J Keerthy <j-keerthy at ti.com>
> + *    Moiz Sonasath <m-sonasath at ti.com>
> + * MFD clean up and re-factoring:
> + *    Eduardo Valentin <eduardo.valentin at ti.com>
> + *    Konstantin Baydarov <kbaidarov at dev.rtsoft.ru>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/export.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/core.h>
> +#include <linux/mfd/omap_control.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +void __iomem *omap_control_base;
> +unsigned long omap_control_phys_base;
> +size_t omap_control_mapsize;
> +
> +u32 omap_control_status_read(void)
> +{
> +	return __raw_readl(omap_control_base);
> +}

In AM335X, D_CAN IP uses single CONTROL module register to
initialize D_CAN ram (D_CAN_RAMINIT). In order to enable
D_CAN RAM we have to write to that register in sync with
clock enable/disable.

How can I use this driver to handle this usecase? Similar to
above API?

Currently this is handled using platform call back (example below)

In arch/arm/mach-omap2/devices.c:
static void d_can_hw_raminit(unsigned int instance, unsigned int enable)
{
        u32 val;

        /* Read the value */
        val = readl(AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
        if (enable) {
                /* Set to "1" */
                val &= ~AM33XX_DCAN_RAMINIT_START(instance);
                val |= AM33XX_DCAN_RAMINIT_START(instance);
                writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
        } else {
                /* Set to "0" */
                val &= ~AM33XX_DCAN_RAMINIT_START(instance);
                writel(val, AM33XX_CTRL_REGADDR(AM33XX_DCAN_RAMINIT_OFFSET));
        }
}

In drivers/net/can/c_can/c_can.c:
void d_can_reset_ram(struct d_can_priv *d_can, unsigned int instance,
                                        unsigned int enable)
{
        if (d_can->ram_init)
                d_can->ram_init(instance, enable);
}

Thanks
AnilKumar


From peter.ujfalusi at ti.com  Wed Aug 29 09:31:00 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:00 +0300
Subject: [PATCH v2 1/8] ARM/dts: OMAP2: Add McBSP entries for OMAP2420 and
 OMAP2430 SoC
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-2-git-send-email-peter.ujfalusi@ti.com>

The McBSP IP within OMAP2420 and 2430 is different we need to create separate
dtsi files for them.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap2420.dtsi |   39 ++++++++++++++++++
 arch/arm/boot/dts/omap2430.dtsi |   83 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 122 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap2420.dtsi
 create mode 100644 arch/arm/boot/dts/omap2430.dtsi

diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 0000000..f375c68
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+	compatible = "ti,omap2420", "ti,omap2";
+
+	ocp {
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap2420-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>; /* RX interrupt */
+			interrupt-names = "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 48076000 {
+			compatible = "ti,omap2420-mcbsp";
+			reg = <0x48076000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>; /* RX interrupt */
+			interrupt-names = "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,hwmods = "mcbsp2";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 0000000..531e346
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+	compatible = "ti,omap2430", "ti,omap2";
+
+	ocp {
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 64 0x4>, /* OCP compliant interrupt */
+				     <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>, /* RX interrupt */
+				     <0 61 0x4>; /* RX overflow interrupt */
+			interrupt-names = "common", "tx", "rx", "rx_overflow";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 48076000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48076000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>, /* OCP compliant interrupt */
+				     <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 4808c000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x4808c000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+				     <0 89 0x4>, /* TX interrupt */
+				     <0 90 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 4808e000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x4808e000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 18 0x4>, /* OCP compliant interrupt */
+				     <0 54 0x4>, /* TX interrupt */
+				     <0 55 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
+
+		mcbsp5: mcbsp at 48096000 {
+			compatible = "ti,omap2430-mcbsp";
+			reg = <0x48096000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 19 0x4>, /* OCP compliant interrupt */
+				     <0 81 0x4>, /* TX interrupt */
+				     <0 82 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp5";
+		};
+	};
+};
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:01 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:01 +0300
Subject: [PATCH v2 2/8] ARM/dts: omap2420-h4: Include omap2420.dtsi file
 instead the common omap2
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-3-git-send-email-peter.ujfalusi@ti.com>

Since the board is based on OMAP2420 we should include the dedicated dtsi
file (which includes the common omap2 dtsi).

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap2420-h4.dts |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b7..77b84e1 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
 
 / {
 	model = "TI OMAP2420 H4 board";
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:02 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:02 +0300
Subject: [PATCH v2 3/8] ARM/dts: OMAP3: Add McBSP entries
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-4-git-send-email-peter.ujfalusi@ti.com>

Create the needed sections to be able to probe McBSP ports via DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap3.dtsi |   69 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 8109471..5c14b00 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -220,5 +220,74 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		mcbsp1: mcbsp at 48074000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x48074000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>, /* OCP compliant interrupt */
+				     <0 59 0x4>, /* TX interrupt */
+				     <0 60 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 49022000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49022000 0xff>,
+			      <0x49028000 0xff>;
+			reg-names = "mpu", "sidetone";
+			interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+				     <0 62 0x4>, /* TX interrupt */
+				     <0 63 0x4>, /* RX interrupt */
+				     <0 4 0x4>;  /* Sidetone */
+			interrupt-names = "common", "tx", "rx", "sidetone";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <1280>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 49024000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49024000 0xff>,
+			      <0x4902a000 0xff>;
+			reg-names = "mpu", "sidetone";
+			interrupts = <0 22 0x4>, /* OCP compliant interrupt */
+				     <0 89 0x4>, /* TX interrupt */
+				     <0 90 0x4>, /* RX interrupt */
+				     <0 5 0x4>;  /* Sidetone */
+			interrupt-names = "common", "tx", "rx", "sidetone";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 49026000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x49026000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 23 0x4>, /* OCP compliant interrupt */
+				     <0 54 0x4>, /* TX interrupt */
+				     <0 55 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
+
+		mcbsp5: mcbsp at 48096000 {
+			compatible = "ti,omap3-mcbsp";
+			reg = <0x48096000 0xff>;
+			reg-names = "mpu";
+			interrupts = <0 27 0x4>, /* OCP compliant interrupt */
+				     <0 81 0x4>, /* TX interrupt */
+				     <0 82 0x4>; /* RX interrupt */
+			interrupt-names = "common", "tx", "rx";
+			interrupt-parent = <&intc>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp5";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:03 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:03 +0300
Subject: [PATCH v2 4/8] ARM/dts: OMAP4: Add McBSP entries
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-5-git-send-email-peter.ujfalusi@ti.com>

Create the sections describing the McBSP ports to be able to use them via
DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |   47 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..258435f 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -295,5 +295,52 @@
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
 		};
+
+		mcbsp1: mcbsp at 40122000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40122000 0xff>, /* MPU private access */
+			      <0x49022000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 17 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 40124000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40124000 0xff>, /* MPU private access */
+			      <0x49024000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 22 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 40126000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40126000 0xff>, /* MPU private access */
+			      <0x49026000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 23 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
+
+		mcbsp4: mcbsp at 48096000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x48096000 0xff>; /* L4 Interconnect */
+			reg-names = "mpu";
+			interrupts = <0 16 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp4";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:04 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:04 +0300
Subject: [PATCH v2 5/8] ARM/dts: OMAP5: Add McBSP entries
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-6-git-send-email-peter.ujfalusi@ti.com>

Create the sections describing the McBSP ports to be able to use them via
DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 881d60c..57ca7c1 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -211,5 +211,41 @@
 			ti,hwmods = "mmc5";
 			ti,needs-special-reset;
 		};
+
+		mcbsp1: mcbsp at 40122000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40122000 0xff>, /* MPU private access */
+			      <0x49022000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 17 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp1";
+		};
+
+		mcbsp2: mcbsp at 40124000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40124000 0xff>, /* MPU private access */
+			      <0x49024000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 22 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp2";
+		};
+
+		mcbsp3: mcbsp at 40126000 {
+			compatible = "ti,omap4-mcbsp";
+			reg = <0x40126000 0xff>, /* MPU private access */
+			      <0x49026000 0xff>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 23 0x4>;
+			interrupt-names = "common";
+			interrupt-parent = <&gic>;
+			ti,buffer-size = <128>;
+			ti,hwmods = "mcbsp3";
+		};
 	};
 };
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:30:59 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:30:59 +0300
Subject: [PATCH v2 0/8] ARM/dts: OMAP audio related updates for OMAP2/3/4/5
Message-ID: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

I have extended and rebased the previous set:
'ARM/dts: omap McBSP and audio support for BeagleBoard'

Changes since v1:
- Rebased on current l-o:devel-dt branch
- Two new patch, one for OMAP4 to add reg-names for the mem areas, one for OMAP5
  to add McPDM and DMIC section

The rest of the series remaind the same: adds the McBSP sections to OMAP2/3/4/5
and also enable the audio support for BeagleBoard when booting with DT.

Regards,
Peter
---
Peter Ujfalusi (8):
  ARM/dts: OMAP2: Add McBSP entries for OMAP2420 and OMAP2430 SoC
  ARM/dts: omap2420-h4: Include omap2420.dtsi file instead the common
    omap2
  ARM/dts: OMAP3: Add McBSP entries
  ARM/dts: OMAP4: Add McBSP entries
  ARM/dts: OMAP5: Add McBSP entries
  ARM/dts: omap3-beagle: Enable audio support
  ARM/dts: omap4: Add reg-names for McPDM and DMIC
  ARM/dts: omap5: Add McPDM and DMIC section to the dtsi file

 arch/arm/boot/dts/omap2420-h4.dts  |    2 +-
 arch/arm/boot/dts/omap2420.dtsi    |   39 +++++++++++++++++
 arch/arm/boot/dts/omap2430.dtsi    |   83 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-beagle.dts |   14 ++++++
 arch/arm/boot/dts/omap3.dtsi       |   69 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi       |   49 +++++++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi       |   56 ++++++++++++++++++++++++
 7 files changed, 311 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap2420.dtsi
 create mode 100644 arch/arm/boot/dts/omap2430.dtsi

-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:05 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:05 +0300
Subject: [PATCH v2 6/8] ARM/dts: omap3-beagle: Enable audio support
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-7-git-send-email-peter.ujfalusi@ti.com>

Add the needed sections to enable audio support on BeagleBoard when booted
with DT blob.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap3-beagle.dts |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index cdcb98c..28cf180 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -17,6 +17,14 @@
 		device_type = "memory";
 		reg = <0x80000000 0x20000000>; /* 512 MB */
 	};
+
+	sound {
+		compatible = "ti,omap-twl4030";
+		ti,model = "omap3beagle";
+
+		ti,mcbsp = <&mcbsp2>;
+		ti,codec = <&twl_audio>;
+	};
 };
 
 &i2c1 {
@@ -32,6 +40,12 @@
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <3000000>;
 		};
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			codec {
+			};
+		};
 	};
 };
 
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:06 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:06 +0300
Subject: [PATCH v2 7/8] ARM/dts: omap4: Add reg-names for McPDM and DMIC
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-8-git-send-email-peter.ujfalusi@ti.com>

In order to get the memory areas by name when booted with DT.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap4.dtsi |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 258435f..115a502 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -282,6 +282,7 @@
 			compatible = "ti,omap4-mcpdm";
 			reg = <0x40132000 0x7f>, /* MPU private access */
 			      <0x49032000 0x7f>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
 			interrupts = <0 112 0x4>;
 			interrupt-parent = <&gic>;
 			ti,hwmods = "mcpdm";
@@ -291,6 +292,7 @@
 			compatible = "ti,omap4-dmic";
 			reg = <0x4012e000 0x7f>, /* MPU private access */
 			      <0x4902e000 0x7f>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
 			interrupts = <0 114 0x4>;
 			interrupt-parent = <&gic>;
 			ti,hwmods = "dmic";
-- 
1.7.8.6



From peter.ujfalusi at ti.com  Wed Aug 29 09:31:07 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 29 Aug 2012 16:31:07 +0300
Subject: [PATCH v2 8/8] ARM/dts: omap5: Add McPDM and DMIC section to the dtsi
 file
In-Reply-To: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
References: <1346247067-9632-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1346247067-9632-9-git-send-email-peter.ujfalusi@ti.com>

To be able to load the McPDM and DMIC driver when booted with device tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/boot/dts/omap5.dtsi |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57ca7c1..5ab1a36 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -212,6 +212,26 @@
 			ti,needs-special-reset;
 		};
 
+		mcpdm: mcpdm at 40132000 {
+			compatible = "ti,omap4-mcpdm";
+			reg = <0x40132000 0x7f>, /* MPU private access */
+			      <0x49032000 0x7f>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 112 0x4>;
+			interrupt-parent = <&gic>;
+			ti,hwmods = "mcpdm";
+		};
+
+		dmic: dmic at 4012e000 {
+			compatible = "ti,omap4-dmic";
+			reg = <0x4012e000 0x7f>, /* MPU private access */
+			      <0x4902e000 0x7f>; /* L3 Interconnect */
+			reg-names = "mpu", "dma";
+			interrupts = <0 114 0x4>;
+			interrupt-parent = <&gic>;
+			ti,hwmods = "dmic";
+		};
+
 		mcbsp1: mcbsp at 40122000 {
 			compatible = "ti,omap4-mcbsp";
 			reg = <0x40122000 0xff>, /* MPU private access */
-- 
1.7.8.6



From maxime.ripard at free-electrons.com  Wed Aug 29 09:40:24 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Wed, 29 Aug 2012 15:40:24 +0200
Subject: [PATCH 4/4] ARM: dts: mxs: add oled support for the cfa-10036
In-Reply-To: <20120823144541.GL24242@S2101-09.ap.freescale.net>
References: <1345711351-16367-1-git-send-email-maxime.ripard@free-electrons.com>
 <1345711351-16367-5-git-send-email-maxime.ripard@free-electrons.com>
 <20120823144541.GL24242@S2101-09.ap.freescale.net>
Message-ID: <503E1BC8.8060500@free-electrons.com>

Hi,

Le 23/08/2012 16:45, Shawn Guo a ?crit :
> On Thu, Aug 23, 2012 at 10:42:31AM +0200, Maxime Ripard wrote:
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> Cc: Brian Lilly <brian at crystalfontz.com>
>> ---
>>  arch/arm/boot/dts/imx28-cfa10036.dts |   20 ++++++++++++++++++++
>>  1 file changed, 20 insertions(+)
>>
> Looks mostly good, but I have to postpone it until driver part gets
> accepted.

Yes, I totally understand that.

Florian, are you ok with merging the fb driver in the first patch?

> Some minor comments below.

Ok, I'll send an update with the next version of the patchset if there
is comments on the driver, or alone if the driver is merged as is.

Maxime

-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From t.figa at samsung.com  Wed Aug 29 09:52:23 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 29 Aug 2012 15:52:23 +0200
Subject: [PATCH 1/3] ARM: EXYNOS: Use EXYNOS4210_GPEx instead of
 EXYNOS4_GPEx
In-Reply-To: <CAH9JG2UF6cqPcX4idYLRBHwLvs27ErtbwsjEFvMZbyfz_KNsZw@mail.gmail.com>
References: <4648723.rWnut7F0uJ@amdc1227> <503D57EF.2090402@samsung.com>
 <CAH9JG2UF6cqPcX4idYLRBHwLvs27ErtbwsjEFvMZbyfz_KNsZw@mail.gmail.com>
Message-ID: <3351890.rVcxVBV0WB@amdc1227>

Hi,

On Wednesday 29 of August 2012 09:03:12 Kyungmin Park wrote:
> On 8/29/12, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Please see my comments on Joonyoung Shim's previous patch...
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/101522.h
> > tml
> It's perference issue. some person like this style. others doesn't.
> Moreever vender, System LSI, provided codes have whole different style.
> It lists up whole gpios for each SoCs.
> 
> EXYNOS4210_{A0, .... Z}
> EXYNOS4412_{A0, .... V4}
> EXYNOS5250_{A0, .... Z}
> 
> anyway, just remain it as broken, and try to use pinctl as Thomas
> mentioned.

OK, I will drop this patchset for the time being. Let's get the pinctrl 
driver merged first and then investigate Exynos4x12 support in it.

Best regards,
-- 
Tomasz Figa
Samsung Poland R&D Center



From t.figa at samsung.com  Wed Aug 29 10:08:53 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Wed, 29 Aug 2012 16:08:53 +0200
Subject: [PATCH v2] ARM: EXYNOS: Add support for secondary CPU bring-up on
 Exynos4412
Message-ID: <1393767.3tjq8gL245@amdc1227>

Exynos4412 uses different information register for each core. This patch
adjusts the bring-up code to take that into account.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/platsmp.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..816a27d 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*
  * control for which core is the next to come out of the secondary
@@ -89,6 +100,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
+	unsigned long phys_cpu = cpu_logical_map(cpu);
 
 	/*
 	 * Set synchronisation state between this boot processor
@@ -104,7 +116,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
-	write_pen_release(cpu_logical_map(cpu));
+	write_pen_release(phys_cpu);
 
 	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 		__raw_writel(S5P_CORE_LOCAL_PWR_EN,
@@ -138,7 +150,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+							cpu_boot_reg(phys_cpu));
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
@@ -186,6 +198,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int i;
+
 	if (!soc_is_exynos5250())
 		scu_enable(scu_base_addr());
 
@@ -195,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i)
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+					cpu_boot_reg(cpu_logical_map(i)));
 }
-- 
1.7.12




From nicolas.thery at st.com  Wed Aug 29 10:55:32 2012
From: nicolas.thery at st.com (Nicolas THERY)
Date: Wed, 29 Aug 2012 16:55:32 +0200
Subject: [PATCH] [media] atmel_isi: allocate memory to store the isi
 platform data.
In-Reply-To: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
References: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
Message-ID: <503E2D64.1020303@st.com>

Hello,

On 2012-08-29 12:11, Josh Wu wrote:
> This patch fix the bug: ISI driver's platform data became invalid when isi platform data's attribution is __initdata.
> 
> If the isi platform data is passed as __initdata. Then we need store it in driver allocated memory. otherwise when we use it out of the probe() function, then the isi platform data is invalid.
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
>  drivers/media/platform/soc_camera/atmel-isi.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
> index ec3f6a0..dc0fdec 100644
> --- a/drivers/media/platform/soc_camera/atmel-isi.c
> +++ b/drivers/media/platform/soc_camera/atmel-isi.c
> @@ -926,6 +926,7 @@ static int __devexit atmel_isi_remove(struct platform_device *pdev)
>  	clk_put(isi->mck);
>  	clk_unprepare(isi->pclk);
>  	clk_put(isi->pclk);
> +	kfree(isi->pdata);

Not needed if you use devm_kzalloc().  See below.

>  	kfree(isi);
>  
>  	return 0;
> @@ -968,8 +969,15 @@ static int __devinit atmel_isi_probe(struct platform_device *pdev)
>  		goto err_alloc_isi;
>  	}
>  
> +	isi->pdata = kzalloc(sizeof(struct isi_platform_data), GFP_KERNEL);
> +	if (!isi->pdata) {
> +		ret = -ENOMEM;
> +		dev_err(&pdev->dev, "Can't allocate isi platform data!\n");
> +		goto err_alloc_isi_pdata;
> +	}
> +	memcpy(isi->pdata, pdata, sizeof(struct isi_platform_data));
> +

It is more idiomatic to use sizeof(*isi->pdata) in kzalloc() and memcpy() calls
to be resilient to future type changes.

You may also want to use dev_kzalloc() which frees memory automagically on
driver detach.

>  	isi->pclk = pclk;
> -	isi->pdata = pdata;
>  	isi->active = NULL;
>  	spin_lock_init(&isi->lock);
>  	init_waitqueue_head(&isi->vsync_wq);
> @@ -1073,6 +1081,8 @@ err_set_mck_rate:
>  err_clk_prepare_mck:
>  	clk_put(isi->mck);
>  err_clk_get:
> +	kfree(isi->pdata);
> +err_alloc_isi_pdata:
>  	kfree(isi);
>  err_alloc_isi:
>  	clk_unprepare(pclk);
> 

Best regards,
Nicolas

From tomi.valkeinen at ti.com  Wed Aug 29 11:04:24 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 29 Aug 2012 18:04:24 +0300
Subject: [PATCH 6/9] ARM: OMAP1: move omap1_bl pdata out of arch/arm/*
In-Reply-To: <1346195937-6383-7-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
 <1346195937-6383-7-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346252664.12380.0.camel@deskari>

On Wed, 2012-08-29 at 02:18 +0300, Igor Grinberg wrote:
> omap1 backlight platform data resides inside plat/board.h while it
> should be inside include/linux/...
> Move the omap1 backlight platform data to
> include/linux/platform_data/.
> 
> Cc: Richard Purdie <rpurdie at rpsys.net>
> Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
> Cc: linux-fbdev at vger.kernel.org
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
>  arch/arm/mach-omap1/board-osk.c         |    1 +
>  arch/arm/mach-omap1/board-palmte.c      |    1 +
>  arch/arm/mach-omap1/board-palmtt.c      |    1 +
>  arch/arm/mach-omap1/board-palmz71.c     |    1 +
>  arch/arm/plat-omap/include/plat/board.h |    7 -------
>  drivers/video/backlight/omap1_bl.c      |    2 +-
>  include/linux/platform_data/omap1_bl.h  |   11 +++++++++++
>  7 files changed, 16 insertions(+), 8 deletions(-)
>  create mode 100644 include/linux/platform_data/omap1_bl.h
> 
> diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
> index 8784705..569b687 100644
> --- a/arch/arm/mach-omap1/board-osk.c
> +++ b/arch/arm/mach-omap1/board-osk.c
> @@ -39,6 +39,7 @@
>  #include <linux/mtd/partitions.h>
>  #include <linux/mtd/physmap.h>
>  #include <linux/i2c/tps65010.h>
> +#include <linux/platform_data/omap1_bl.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
> index 26bcb9d..7bf00ba 100644
> --- a/arch/arm/mach-omap1/board-palmte.c
> +++ b/arch/arm/mach-omap1/board-palmte.c
> @@ -28,6 +28,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/apm-emulation.h>
>  #include <linux/omapfb.h>
> +#include <linux/platform_data/omap1_bl.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
> index 4d09944..2cce505 100644
> --- a/arch/arm/mach-omap1/board-palmtt.c
> +++ b/arch/arm/mach-omap1/board-palmtt.c
> @@ -27,6 +27,7 @@
>  #include <linux/omapfb.h>
>  #include <linux/spi/spi.h>
>  #include <linux/spi/ads7846.h>
> +#include <linux/platform_data/omap1_bl.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
> index 3559803..45ab9f0 100644
> --- a/arch/arm/mach-omap1/board-palmz71.c
> +++ b/arch/arm/mach-omap1/board-palmz71.c
> @@ -30,6 +30,7 @@
>  #include <linux/omapfb.h>
>  #include <linux/spi/spi.h>
>  #include <linux/spi/ads7846.h>
> +#include <linux/platform_data/omap1_bl.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
> index 5938c72..d0bc46e 100644
> --- a/arch/arm/plat-omap/include/plat/board.h
> +++ b/arch/arm/plat-omap/include/plat/board.h
> @@ -19,13 +19,6 @@ struct omap_lcd_config {
>  	u8   data_lines;
>  };
>  
> -struct device;
> -struct fb_info;
> -struct omap_backlight_config {
> -	int default_intensity;
> -	int (*set_power)(struct device *dev, int state);
> -};
> -
>  /* for TI reference platforms sharing the same debug card */
>  extern int debug_card_init(u32 addr, unsigned gpio);
>  
> diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
> index bfdc5fb..92257ef 100644
> --- a/drivers/video/backlight/omap1_bl.c
> +++ b/drivers/video/backlight/omap1_bl.c
> @@ -27,9 +27,9 @@
>  #include <linux/fb.h>
>  #include <linux/backlight.h>
>  #include <linux/slab.h>
> +#include <linux/platform_data/omap1_bl.h>
>  
>  #include <mach/hardware.h>
> -#include <plat/board.h>
>  #include <plat/mux.h>
>  
>  #define OMAPBL_MAX_INTENSITY		0xff
> diff --git a/include/linux/platform_data/omap1_bl.h b/include/linux/platform_data/omap1_bl.h
> new file mode 100644
> index 0000000..881a8e9
> --- /dev/null
> +++ b/include/linux/platform_data/omap1_bl.h
> @@ -0,0 +1,11 @@
> +#ifndef __OMAP1_BL_H__
> +#define __OMAP1_BL_H__
> +
> +#include <linux/device.h>

You could use struct device; here.

> +
> +struct omap_backlight_config {
> +	int default_intensity;
> +	int (*set_power)(struct device *dev, int state);
> +};
> +
> +#endif

Acked-by: Tomi Valkeinen <tomi.valkeinen at ti.com>

 Tomi

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From tomi.valkeinen at ti.com  Wed Aug 29 11:06:05 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 29 Aug 2012 18:06:05 +0300
Subject: [PATCH 7/9] ARM: OMAP1: move lcd pdata out of arch/arm/*
In-Reply-To: <1346195937-6383-8-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
 <1346195937-6383-8-git-send-email-grinberg@compulab.co.il>
Message-ID: <1346252765.12380.1.camel@deskari>

On Wed, 2012-08-29 at 02:18 +0300, Igor Grinberg wrote:
> omap1 lcd platform data resides inside plat/board.h while it
> should be inside include/linux/...
> Move the omap1 lcd platform data to include/linux/omapfb.h.
> 
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
>  arch/arm/mach-omap1/board-ams-delta.c   |    1 -
>  arch/arm/mach-omap1/board-fsample.c     |    1 -
>  arch/arm/mach-omap1/board-htcherald.c   |    1 -
>  arch/arm/mach-omap1/board-nokia770.c    |    1 -
>  arch/arm/mach-omap1/board-palmte.c      |    1 -
>  arch/arm/mach-omap1/board-palmtt.c      |    1 -
>  arch/arm/mach-omap1/board-palmz71.c     |    1 -
>  arch/arm/mach-omap1/board-perseus2.c    |    1 -
>  arch/arm/mach-omap1/board-sx1.c         |    1 -
>  arch/arm/plat-omap/fb.c                 |    2 --
>  arch/arm/plat-omap/include/plat/board.h |    7 -------
>  include/linux/omapfb.h                  |    7 ++++++-
>  12 files changed, 6 insertions(+), 19 deletions(-)
> 

Acked-by: Tomi Valkeinen <tomi.valkeinen at ti.com>

 Tomi

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From dromede at gmail.com  Wed Aug 29 11:06:43 2012
From: dromede at gmail.com (dromede at gmail.com)
Date: Wed, 29 Aug 2012 17:06:43 +0200
Subject: [RFC][PATCH] pxamci: defining CONFIG_REGULATOR_DUMMY may break PXA
 MMC controller driver.
Message-ID: <1346252803-7817-1-git-send-email-dromede@gmail.com>

From: Marko Katic <dromede.gmail.com>

Here's an interesting scenario. The spitz machine has an
Intersil 6271A voltage regulator and an ADS7846 touchscreen
controller. The ADS7846 driver requires the use of the voltage regulator
or if not present, CONFIG_REGULATOR_DUMMY should be used for proper operation.
So to support both devices, CONFIG_REGULATOR and CONFIG REGULATOR_DUMMY have
to be defined.

However, enabling CONFIG_REGULATOR_DUMMY breaks pxamci in pxamci_init_ocr().
and pxamci_set_power() in the case when no vmmc regulator is present.

These functions don't handle the presence of a dummy regulator very well
since they expect a proper regulator when CONFIG_REGULATOR is defined or
no regulator at all. I've modified both to do more checking and to always
fall back to platform data if such data is present.

I should probably add some dev_warns somewhere, i would like some input
on that.

Signed-off-by: Marko Katic <dromede.gmail.com>
---
 drivers/mmc/host/pxamci.c |   36 ++++++++++++++++++++++--------------
 1 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e..ffbf177 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -80,18 +80,24 @@ struct pxamci_host {
 static inline void pxamci_init_ocr(struct pxamci_host *host)
 {
 #ifdef CONFIG_REGULATOR
+	int ocr_mask;
 	host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
 
 	if (IS_ERR(host->vcc))
 		host->vcc = NULL;
 	else {
-		host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
-		if (host->pdata && host->pdata->ocr_mask)
+		ocr_mask = mmc_regulator_get_ocrmask(host->vcc);
+		if (ocr_mask <= 0)
+			host->mmc->ocr_avail = 0;
+		else	
+			host->mmc->ocr_avail = ocr_mask;
+				
+		if (host->pdata && host->pdata->ocr_mask && host->mmc->ocr_avail)
 			dev_warn(mmc_dev(host->mmc),
 				"ocr_mask/setpower will not be used\n");
 	}
 #endif
-	if (host->vcc == NULL) {
+	if (host->vcc == NULL || host->mmc->ocr_avail == 0) {
 		/* fall-back to platform data */
 		host->mmc->ocr_avail = host->pdata ?
 			host->pdata->ocr_mask :
@@ -104,27 +110,29 @@ static inline int pxamci_set_power(struct pxamci_host *host,
 				    unsigned int vdd)
 {
 	int on;
-
+	
+#ifdef CONFIG_REGULATOR
 	if (host->vcc) {
-		int ret;
+		int ret = 0;
 
-		if (power_mode == MMC_POWER_UP) {
+		if (power_mode == MMC_POWER_UP)
 			ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
-			if (ret)
-				return ret;
-		} else if (power_mode == MMC_POWER_OFF) {
+
+		if (power_mode == MMC_POWER_OFF)
 			ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
-			if (ret)
-				return ret;
-		}
+		
+		if (ret == 0)
+			return ret;
 	}
-	if (!host->vcc && host->pdata &&
+#endif
+	
+	if (host->pdata &&
 	    gpio_is_valid(host->pdata->gpio_power)) {
 		on = ((1 << vdd) & host->pdata->ocr_mask);
 		gpio_set_value(host->pdata->gpio_power,
 			       !!on ^ host->pdata->gpio_power_invert);
 	}
-	if (!host->vcc && host->pdata && host->pdata->setpower)
+	if (host->pdata && host->pdata->setpower)
 		host->pdata->setpower(mmc_dev(host->mmc), vdd);
 
 	return 0;
-- 
1.7.4.1



From s.nawrocki at samsung.com  Wed Aug 29 11:16:10 2012
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 29 Aug 2012 17:16:10 +0200
Subject: [PATCH] [media] atmel_isi: allocate memory to store the isi
 platform data.
In-Reply-To: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
References: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
Message-ID: <503E323A.8060409@samsung.com>

Hi,

On 08/29/2012 12:11 PM, Josh Wu wrote:
> This patch fix the bug: ISI driver's platform data became invalid 
> when isi platform data's attribution is __initdata.
> 
> If the isi platform data is passed as __initdata. Then we need store
> it in driver allocated memory. otherwise when we use it out of the 
> probe() function, then the isi platform data is invalid.
> 
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
>  drivers/media/platform/soc_camera/atmel-isi.c |   12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
> index ec3f6a0..dc0fdec 100644
> --- a/drivers/media/platform/soc_camera/atmel-isi.c
> +++ b/drivers/media/platform/soc_camera/atmel-isi.c
> @@ -926,6 +926,7 @@ static int __devexit atmel_isi_remove(struct platform_device *pdev)
>  	clk_put(isi->mck);
>  	clk_unprepare(isi->pclk);
>  	clk_put(isi->pclk);
> +	kfree(isi->pdata);
>  	kfree(isi);
>  
>  	return 0;
> @@ -968,8 +969,15 @@ static int __devinit atmel_isi_probe(struct platform_device *pdev)
>  		goto err_alloc_isi;
>  	}
>  
> +	isi->pdata = kzalloc(sizeof(struct isi_platform_data), GFP_KERNEL);
> +	if (!isi->pdata) {
> +		ret = -ENOMEM;
> +		dev_err(&pdev->dev, "Can't allocate isi platform data!\n");
> +		goto err_alloc_isi_pdata;
> +	}
> +	memcpy(isi->pdata, pdata, sizeof(struct isi_platform_data));
> +

Why not just embed struct isi_platform_data in struct atmel_isi and drop this
another kzalloc() ?
Then you could simply do isi->pdata = *pdata.

Also, is this going to work when this driver is build and as a module
and its loading is deferred past system booting ? At that time the driver's
platform data may be well discarded. You may wan't to duplicate it on the
running boards in board code with kmemdup() or something.

--

Regards,
Sylwester


From stigge at antcom.de  Wed Aug 29 11:20:17 2012
From: stigge at antcom.de (Roland Stigge)
Date: Wed, 29 Aug 2012 17:20:17 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <20120829074122.GV26594@pengutronix.de>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de>
Message-ID: <503E3331.8050203@antcom.de>

Hi Sascha,

On 08/29/2012 09:41 AM, Sascha Hauer wrote:
> On Thu, Aug 23, 2012 at 11:30:54AM +0200, Roland Stigge wrote:
>> Hi,
>>
>> I'd like to know about the current state of mxc_nand.c on imx53, because
>> I got an error on probe() because the clock that mxc_nand is requesting
>> is "nfc" but imx53 only defines the clock "mxc_nand".
> 
> The driver generally works on i.MX53, only some pieces are missing. I
> just resent the corresponding series and put you on Cc.

Good - thank you for the patches, didn't know about them.

Now, my flash is detected:

NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND 512MiB
3,3V 8-bit), page size: 4096, OOB size: 128

However, when I read a partition, kernel (mxc_nand_correct_data_v2_v3())
says:

...
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
...

I'm using the following dt (on an Emtrion DIMM-MX53 board):

                        nand at 63fdb000 {
                                status = "okay";
                                #address-cells = <1>;
                                #size-cells = <1>;
                                nand-bus-width = <8>;
                                nand-ecc-mode = "hw";

                                mtd0 at 00000000 {
                                        label = "bootstrap";
                                        reg = <0x00000000 0x80000>;
                                        read-only;
                                };
                                mtd1 at 00080000 {
                                        label = "uboot";
                                        reg = <0x00080000 0x80000>;
                                        read-only;
                                };
                                mtd2 at 00100000 {
                                        label = "NVRAM";
                                        reg = <0x00100000 0x100000>;
                                };
                                mtd3 at 00200000 {
                                        label = "bootlogo";
                                        reg = <0x00200000 0x80000>;
                                };
                                mtd4 at 00280000 {
                                        label = "linux";
                                        reg = <0x00280000 0x400000>;
                                };
                                mtd5 at 00680000 {
                                        label = "rootfs";
                                        reg = <0x00680000 0x8000000>;
                                };
                                mtd6 at 08680000 {
                                        label = "appfs";
                                        reg = <0x08680000 0x17980000>;
                                };
                        };

NAND info from u-boot:

NAND:  512 MiB
Manufacturer      : Micron (0x2c)
Device Code       : 0xdc
Cell Technology   : SLC
Chip Size         : 512 MiB
Pages per Block   : 64
Page Geometry     : 4096+218
ECC Strength      : 8 bits
ECC Size          : 512 B
Data Setup Time   : 20 ns
Data Hold Time    : 10 ns
Address Setup Time: 10 ns
GPMI Sample Delay : 6 ns
tREA              : Unknown
tRLOH             : Unknown
tRHOH             : Unknown
Description       : MT29F4G08ABAEA

I guess I hit a documented open issue:

/* v3.2b: i.MX53 */
static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
        .preset = preset_v3,
        .send_cmd = send_cmd_v3,
        .send_addr = send_addr_v3,
        .send_page = send_page_v3,
        .send_read_id = send_read_id_v3,
        .get_dev_status = get_dev_status_v3,
        .check_int = check_int_v3,
        .irq_control = irq_control_v3,
        .get_ecc_status = get_ecc_status_v3,
        .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
        .ecclayout_2k = &nandv2_hw_eccoob_largepage,
        .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */

Using  ".ecclayout_4k = &nandv2_hw_eccoob_4k" also doesn't work. So is
there any hint how I can proceed from here? Any plans or hint regarding
the "XXX"?

Thanks in advance,

Roland


From eric at eukrea.com  Wed Aug 29 11:28:20 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Wed, 29 Aug 2012 17:28:20 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <503E3331.8050203@antcom.de>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de>
 <503E3331.8050203@antcom.de>
Message-ID: <20120829172820.43bbe68e@eb-e6520>

Hi Roland,

Le Wed, 29 Aug 2012 17:20:17 +0200,
Roland Stigge <stigge at antcom.de> a ?crit :
> Using  ".ecclayout_4k = &nandv2_hw_eccoob_4k" also doesn't work. So is
> there any hint how I can proceed from here? Any plans or hint regarding
> the "XXX"?
> 
you may need something like this patch from barebox :
http://git.pengutronix.de/?p=barebox.git;a=commit;h=632c45795065e6a7471ab82be38e808eb6204341

I may have time to adapt this next week but if you have time before feel
free to do it ;-)

Eric


From dedekind1 at gmail.com  Wed Aug 29 11:46:01 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 29 Aug 2012 18:46:01 +0300
Subject: [PATCH] mtd: orion_nand: remove <mach/hardware.h> include
In-Reply-To: <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
References: <20120816183708.GT22226@titan.lakedaemon.net>
 <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>
 <1346110528-30858-2-git-send-email-thomas.petazzoni@free-electrons.com>
Message-ID: <1346255161.2848.515.camel@sauron.fi.intel.com>

On Tue, 2012-08-28 at 01:35 +0200, Thomas Petazzoni wrote:
> Commit c085d965fb63ac3b4cc7379d45588c0b39e2bdb0 made the ARCH_MVEBU
> platform select PLAT_ORION, which means that now all Orion drivers can
> be enabled on ARCH_MVEBU. This works fine for most drivers, except for
> orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
> not have a mach/hardware.h header (it is considered as a deprecated
> practice).
> 
> It turns out that the <mach/hardware.h> include in orion_nand is not
> necessary: the driver builds perfectly fine without it, so we simply
> get rid of it.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From g.liakhovetski at gmx.de  Wed Aug 29 12:02:18 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 29 Aug 2012 18:02:18 +0200 (CEST)
Subject: [PATCH] [media] atmel_isi: allocate memory to store the isi
 platform data.
In-Reply-To: <503E323A.8060409@samsung.com>
References: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
 <503E323A.8060409@samsung.com>
Message-ID: <alpine.DEB.2.00.1208291755220.3095@axis700.grange>

On Wed, 29 Aug 2012, Sylwester Nawrocki wrote:

> Hi,
> 
> On 08/29/2012 12:11 PM, Josh Wu wrote:
> > This patch fix the bug: ISI driver's platform data became invalid 
> > when isi platform data's attribution is __initdata.
> > 
> > If the isi platform data is passed as __initdata. Then we need store
> > it in driver allocated memory. otherwise when we use it out of the 
> > probe() function, then the isi platform data is invalid.
> > 
> > Signed-off-by: Josh Wu <josh.wu at atmel.com>
> > ---
> >  drivers/media/platform/soc_camera/atmel-isi.c |   12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
> > index ec3f6a0..dc0fdec 100644
> > --- a/drivers/media/platform/soc_camera/atmel-isi.c
> > +++ b/drivers/media/platform/soc_camera/atmel-isi.c
> > @@ -926,6 +926,7 @@ static int __devexit atmel_isi_remove(struct platform_device *pdev)
> >  	clk_put(isi->mck);
> >  	clk_unprepare(isi->pclk);
> >  	clk_put(isi->pclk);
> > +	kfree(isi->pdata);
> >  	kfree(isi);
> >  
> >  	return 0;
> > @@ -968,8 +969,15 @@ static int __devinit atmel_isi_probe(struct platform_device *pdev)
> >  		goto err_alloc_isi;
> >  	}
> >  
> > +	isi->pdata = kzalloc(sizeof(struct isi_platform_data), GFP_KERNEL);
> > +	if (!isi->pdata) {
> > +		ret = -ENOMEM;
> > +		dev_err(&pdev->dev, "Can't allocate isi platform data!\n");
> > +		goto err_alloc_isi_pdata;
> > +	}
> > +	memcpy(isi->pdata, pdata, sizeof(struct isi_platform_data));
> > +
> 
> Why not just embed struct isi_platform_data in struct atmel_isi and drop this
> another kzalloc() ?
> Then you could simply do isi->pdata = *pdata.
> 
> Also, is this going to work when this driver is build and as a module
> and its loading is deferred past system booting ? At that time the driver's
> platform data may be well discarded.

Right, it will be gone, I think.

> You may wan't to duplicate it on the
> running boards in board code with kmemdup() or something.

How about removing __initdata from board code?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From jason at lakedaemon.net  Wed Aug 29 13:14:51 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 29 Aug 2012 13:14:51 -0400
Subject: [RFC PATCH] ARM: initial DTS support for km_kirkwood
In-Reply-To: <503DCFB7.4080804@keymile.com>
References: <1346154976-16916-1-git-send-email-valentin.longchamp@keymile.com>
 <20120828172344.GE19437@titan.lakedaemon.net>
 <503DCFB7.4080804@keymile.com>
Message-ID: <20120829171451.GP19437@titan.lakedaemon.net>

On Wed, Aug 29, 2012 at 10:15:51AM +0200, Valentin Longchamp wrote:
> On 08/28/2012 07:23 PM, Jason Cooper wrote:
> > On Tue, Aug 28, 2012 at 01:56:16PM +0200, Valentin Longchamp wrote:
> >> +	ocp at f1000000 {
> >> +		serial at 12000 {
> >> +			clock-frequency = <200000000>;
> >> +			status = "ok";
> >> +		};
> >> +
> >> +		nand at 3000000 {
> >> +			status = "ok";
> >> +			chip-delay = <25>;
> >> +		};
> > 
> > Is there a partition layout for this board?
> 
> Well, there is one: one big UBI partition on the whole NAND chip (we then create
> UBI volumes when building the initial system and dynamically create additional
> ones when neeeded). But this UBI partition gets detected perfecly well without
> this partition layout so I left it out.

ok, just wanted to make sure it wasn't left out.  I look forward to v2
with Andrew's suggestions.

thx,

Jason.


From swarren at wwwdotorg.org  Wed Aug 29 13:30:49 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 Aug 2012 10:30:49 -0700
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <D958900912E20642BCBC71664EFECE3E6DDE14DD7C@BGMAIL02.nvidia.com>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
 <503CD0A0.7080300@wwwdotorg.org>
 <D958900912E20642BCBC71664EFECE3E6DDE14DD7C@BGMAIL02.nvidia.com>
Message-ID: <503E51C9.7000606@wwwdotorg.org>

On 08/28/12 22:17, Venu Byravarasu wrote:
> Stephen Warren wrote at Tuesday, August 28, 2012 7:37 PM:
>> On 08/28/2012 02:32 AM, Venu Byravarasu wrote:
>>> In order to keep up with the USB driver files organization,
>>> moving USB phy driver from mach-tegra to drivers/USB directory.
>>>
>>> Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
>>
>>> diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-
>> tegra/devices.c
>>
>>> -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
>>> -	.reset_gpio = -1,
>>> -	.clk = "cdev2",
>>> -};
>>> -
>>>   struct tegra_ehci_platform_data tegra_ehci1_pdata = {
>>>   	.operating_mode = TEGRA_USB_OTG,
>>>   	.power_down_on_bus_suspend = 1,
>>> @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data tegra_ehci1_pdata
>> = {
>>>   };
>>>
>>>   struct tegra_ehci_platform_data tegra_ehci2_pdata = {
>>> -	.phy_config = &tegra_ehci2_ulpi_phy_config,
>>> +	.phy_config = NULL,
>>
>> The PHY driver checks that field isn't NULL, and fails if it is:
>>
>>> struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int
>> instance,
>>>          void __iomem *regs, void *config, enum tegra_usb_phy_mode
>> phy_mode)
>>> {
>> ...
>>>          phy->config = config;
>>>          phy->mode = phy_mode;
>>>
>>>          if (!phy->config) {
>>>                  if (phy_is_ulpi(phy)) {
>>>                          pr_err("%s: ulpi phy configuration missing", __func__);
>>>                          err = -EINVAL;
>>>                          goto err0;
>>
>> So, this change will completely break ULPI support, which currently
>> works fine. So, NAK.
>
> My initial plan was to add support for phy interfaces one by one.
> As part of that thought of UTMI only support at first and then add
> ULPI and HSIC in next patches.
> However as you were mentioning that it is not correct way, will
> push ULPI & UTMI support at once in next patches.

But with the existing code, both ULPI and UTMI work. This patch breaks 
something that already works.

>> I also plan on deleting devices.[ch] in kernel 3.7, and moving the USB
>> platform data into board-dt-tegra20.c, since that's the only place it's
>> used right now. So, this patch would conflict with that rather badly. I
>> just posted the patches for that to the linux-tegra mailing list last
>> night. Do you have better proposals for that? Perhaps usb_phy.c should
>> set phy->config to &ulpi_default in a similar fashion to how it works
>> for UTMI; that would remove some of the coupling between the changes.
>>
>> BTW, in your response to Felipe, you said...
>>
>>> Thanks Felipe for your comments.
>>> Created a patch to separate out phy related stuff to phy.h with you as a
>> reviewer.
>>> Plz let me know your comments.
>>
>> ... where is that patch?
>
> Plz see https://lkml.org/lkml/2012/8/28/58

Doesn't that link point at the patch I replied to?



From swarren at wwwdotorg.org  Wed Aug 29 13:34:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 Aug 2012 10:34:00 -0700
Subject: [PATCH] ARM: tegra_defconfig: enable APB DMA support
In-Reply-To: <20120829094957.GF28643@pengutronix.de>
References: <1346230800-3167-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <503DDEA8.1000405@nvidia.com> <20120829094957.GF28643@pengutronix.de>
Message-ID: <503E5288.90602@wwwdotorg.org>

On 08/29/12 02:49, Uwe Kleine-K?nig wrote:
> On Wed, Aug 29, 2012 at 02:49:36PM +0530, Laxman Dewangan wrote:
>> On Wednesday 29 August 2012 02:30 PM, Uwe Kleine-K?nig wrote:
>>> Additionally DMADEVICES needs to be enabled as TEGRA20_APB_DMA depends
>>> on that.
>>>
>>> Signed-off-by: Uwe Kleine-K?nig<u.kleine-koenig at pengutronix.de>
>>> ---
>>>   arch/arm/configs/tegra_defconfig |    2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
>>> index db22453..0d6bb73 100644
>>> --- a/arch/arm/configs/tegra_defconfig
>>> +++ b/arch/arm/configs/tegra_defconfig
>>> @@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
>>>   CONFIG_RTC_CLASS=y
>>>   CONFIG_RTC_DRV_EM3027=y
>>>   CONFIG_RTC_DRV_TEGRA=y
>>> +CONFIG_DMADEVICES=y
>>> +CONFIG_TEGRA20_APB_DMA=y
>>>   CONFIG_STAGING=y
>>>   CONFIG_SENSORS_ISL29018=y
>>>   CONFIG_SENSORS_ISL29028=y
>>
>> Hi Uwe,
>> Tegra team is working on to enable the new dma drivr which is
>> dmaengine based. We have dma legacy driver as of now in mach-tegra.
>> Some of the tests are failing with new dmadriver and so we are not
>> able to enable it.
> So it depends on what you wanna do with the defconfig. There are two
> purposes for them:
>
>   a) compile coverage
>   b) starting point for machine support
>
> So it all depends on what you consider to be more important.

I'd prefer tegra_defconfig to produce a useful working system. I believe 
that enabling both DMA drivers at the same time will cause conflicts. 
Hopefully the switch to the new DMA driver is coming very soon, and this 
patch (or equivalent) will be part of that.



From mturquette at linaro.org  Wed Aug 29 14:26:39 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 Aug 2012 11:26:39 -0700
Subject: [PATCH V5 0/5] clk: mmp: add clock framework for mmp
In-Reply-To: <CADApbehotHB7JSCHdo_eoTb08C5Pe6ewh7whwckQTyuCcMM=BQ@mail.gmail.com>
References: <1345431315-8037-1-git-send-email-xiechao.mail@gmail.com>
 <20120825002151.18366.99434@nucleus>
 <CADApbehotHB7JSCHdo_eoTb08C5Pe6ewh7whwckQTyuCcMM=BQ@mail.gmail.com>
Message-ID: <20120829182639.4450.99900@nucleus>

Quoting Chao Xie (2012-08-26 18:19:02)
> On Sat, Aug 25, 2012 at 8:21 AM, Mike Turquette <mturquette at linaro.org> wrote:
> > Quoting Chao Xie (2012-08-19 19:55:10)
> >> From: Chao Xie <chao.xie at marvell.com>
> >>  arch/arm/mach-mmp/Kconfig    |    3 +
> >>  drivers/clk/Makefile         |    3 +
> >>  drivers/clk/mmp/Makefile     |    9 +
> >>  drivers/clk/mmp/clk-apbc.c   |  152 ++++++++++++++
> >>  drivers/clk/mmp/clk-apmu.c   |   97 +++++++++
> >>  drivers/clk/mmp/clk-frac.c   |  153 ++++++++++++++
> >>  drivers/clk/mmp/clk-mmp2.c   |  449 ++++++++++++++++++++++++++++++++++++++++++
> >>  drivers/clk/mmp/clk-pxa168.c |  346 ++++++++++++++++++++++++++++++++
> >>  drivers/clk/mmp/clk-pxa910.c |  320 ++++++++++++++++++++++++++++++
> >>  drivers/clk/mmp/clk.h        |   35 ++++
> >
> > Looks like you are not removing your arch/arm/mach-mmp/clock.c.  Is that
> > intentional?
> >
> > When I apply your series against v3.6-rc3 I find that compilation breaks
> > with mmp2_defconfig due to conflicting definitions for the clk api
> > (clk_enable, clk_set_rate, etc).  This is not surprising since your
> > legacy clock code is neither deleted nor removed from compilation
> > conditionally by checking for CONFIG_COMMON_CLK.
> >
> > Did I somehow manage to misapply your patches or should your patches
> > have removed the arch-specific clock framework as well?
> >
> hi, Mike
> Yes. There are some patches for seperate the original clock code in arch.
> I had sent these patches before, but it seems that too many patches
> sent, and haojian missed it.
> I will sent out the patches for arch today. Thanks.
> 

I pulled in the dependency series and the build goes through nicely now.
I'm happy to take these five patches into clk-next but of course mmp
will have problems building clk-next without the dependencies, which I
assume are going through arm-soc.

Regards,
Mike

> > Regards,
> > Mike
> >
> >>  10 files changed, 1567 insertions(+), 0 deletions(-)
> >>  create mode 100644 drivers/clk/mmp/Makefile
> >>  create mode 100644 drivers/clk/mmp/clk-apbc.c
> >>  create mode 100644 drivers/clk/mmp/clk-apmu.c
> >>  create mode 100644 drivers/clk/mmp/clk-frac.c
> >>  create mode 100644 drivers/clk/mmp/clk-mmp2.c
> >>  create mode 100644 drivers/clk/mmp/clk-pxa168.c
> >>  create mode 100644 drivers/clk/mmp/clk-pxa910.c
> >>  create mode 100644 drivers/clk/mmp/clk.h


From paul at pwsan.com  Wed Aug 29 14:41:12 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 29 Aug 2012 18:41:12 +0000 (UTC)
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
Message-ID: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>


Hi,

for everyone at Linux Plumbers Conference/LinuxCon, we'll be having a 
Linux on TI SoCs BoF on Thursday, August 30 in Nautilus 1.  



- Paul


From linus.walleij at linaro.org  Wed Aug 29 14:26:42 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 Aug 2012 20:26:42 +0200
Subject: [PATCH 1/4] ARM: ks-8695: merge the timer header into the timer driver
Message-ID: <1346264802-20306-1-git-send-email-linus.walleij@linaro.org>

This <mach/regs-timer.h> is broadcasted in the entire kernel for
no good reason, since it's only used by the timer driver. Merge
it into the driver.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ks8695/include/mach/regs-timer.h |   40 ------------------------
 arch/arm/mach-ks8695/time.c                    |   21 ++++++++++++-
 2 files changed, 20 insertions(+), 41 deletions(-)
 delete mode 100644 arch/arm/mach-ks8695/include/mach/regs-timer.h

diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
deleted file mode 100644
index e620cda..0000000
--- a/arch/arm/mach-ks8695/include/mach/regs-timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben at simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-
-#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)
-#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)
-
-
-/*
- * Timer registers
- */
-#define KS8695_TMCON		(0x00)		/* Timer Control Register */
-#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */
-#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */
-#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */
-#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */
-
-
-/* Timer Control Register */
-#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */
-#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */
-
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
-
-
-#endif
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index ec783a3..6427b7c 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -29,11 +29,30 @@
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
-#include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
 
 #include "generic.h"
 
+#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)
+#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON		(0x00)		/* Timer Control Register */
+#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */
+#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */
+#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */
+#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */
+
+/* Timer Control Register */
+#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */
+#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
+
 /*
  * Returns number of ms since last clock interrupt.  Note that interrupts
  * will have been disabled by do_gettimeoffset()
-- 
1.7.7.6



From linus.walleij at linaro.org  Wed Aug 29 14:27:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 Aug 2012 20:27:22 +0200
Subject: [PATCH 4/4] ARM: ks8695: convert to generic time and clocksource
Message-ID: <1346264842-20411-1-git-send-email-linus.walleij@linaro.org>

Old platforms using ancient gettimeoffset() and other arcane
APIs are standing in the way of cleaning up the ARM kernel.

This is an attempt at blind-coding a generic time and clocksource
driver for the platform by way of a datasheet and looking at the
old code, it'd be great if someone who is actually using this
machine could test it.

If noone volunteers to do this I will instead propose a patch
deleting the machine altogether.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig            |    3 +-
 arch/arm/mach-ks8695/time.c |  123 ++++++++++++++++++++++++++++++-------------
 2 files changed, 88 insertions(+), 38 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5..181b697 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,8 +652,9 @@ config ARCH_KS8695
 	bool "Micrel/Kendin KS8695"
 	select CPU_ARM922T
 	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_USES_GETTIMEOFFSET
 	select NEED_MACH_MEMORY_H
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
 	help
 	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 	  System-on-Chip devices.
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 6974c23..1a933f1 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -25,6 +25,8 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -53,44 +55,68 @@
 /* Timer0 Timeout Counter Register */
 #define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
 
-/*
- * Returns number of ms since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long ks8695_gettimeoffset (void)
+static void ks8695_set_mode(enum clock_event_mode mode,
+			    struct clock_event_device *evt)
 {
-	unsigned long elapsed, tick2, intpending;
+	if (mode == CLOCK_EVT_FEAT_PERIODIC) {
+		u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
+		u32 half = DIV_ROUND_CLOSEST(rate, 2);
+		u32 tmcon;
+
+		/* Disable timer 1 */
+		tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+		tmcon &= TMCON_T1EN;
+		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+		/* Both registers need to count down */
+		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+		/* Re-enable timer1 */
+		tmcon |= TMCON_T1EN;
+		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+	}
+}
 
-	/*
-	 * Get the current number of ticks.  Note that there is a race
-	 * condition between us reading the timer and checking for an
-	 * interrupt.  We solve this by ensuring that the counter has not
-	 * reloaded between our two reads.
-	 */
-	elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
-	do {
-		tick2 = elapsed;
-		intpending = readl_relaxed(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
-		elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
-	} while (elapsed > tick2);
-
-	/* Convert to number of ticks expired (not remaining) */
-	elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
-
-	/* Is interrupt pending?  If so, then timer has been reloaded already. */
-	if (intpending)
-		elapsed += (CLOCK_TICK_RATE / HZ);
-
-	/* Convert ticks to usecs */
-	return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+static int ks8695_set_next_event(unsigned long cycles,
+				 struct clock_event_device *evt)
+
+{
+	u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+	u32 tmcon;
+
+	/* Disable timer 1 */
+	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+	tmcon &= TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+	/* Both registers need to count down */
+	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+	/* Re-enable timer1 */
+	tmcon |= TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+	return 0;
 }
 
+static struct clock_event_device clockevent_ks8695 = {
+	.name		= "ks8695_t1tc",
+	.rating		= 300, /* Reasonably fast and accurate clock event */
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.set_next_event	= ks8695_set_next_event,
+	.set_mode	= ks8695_set_mode,
+};
+
 /*
  * IRQ handler for the timer.
  */
 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 {
-	timer_tick();
+	struct clock_event_device *evt = &clockevent_ks8695;
+
+	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 
@@ -102,18 +128,42 @@ static struct irqaction ks8695_timer_irq = {
 
 static void ks8695_timer_setup(void)
 {
-	unsigned long tmout = CLOCK_TICK_RATE / HZ;
 	unsigned long tmcon;
 
-	/* disable timer1 */
+	/* Disable timer 0 and 1 */
 	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
-	writel_relaxed(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	tmcon &= TMCON_T0EN;
+	tmcon &= TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
 
-	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
-	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+	/*
+	 * Set up timer 0 to loop indefinately, count 32 bits with TOUT0
+	 * set to zero, then 1 bit with TOUT0 set to 1. The reason we are doing
+	 * this is that it's not allowed to set either register to 0, then the
+	 * behaviour is "unpredictable". This injects a faulty pulse every
+	 * 2^32-1 cycles but we can surely live with that rather than
+	 * complicating the code.
+	 */
+	writel_relaxed(0xFFFFFFFFU, KS8695_TMR_VA + KS8695_T0TC);
+	writel_relaxed(1, KS8695_TMR_VA + KS8695_T0PD);
+	/* Start timer 0 */
+	tmcon |= TMCON_T0EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+	/* Use timer 0 as clocksource */
+	if (clocksource_mmio_init((void *) KS8695_TMR_VA + KS8695_T0TC,
+			"ks8695_t0tc", KS8695_CLOCK_RATE, 300, 32,
+			clocksource_mmio_readl_up))
+		pr_err("timer: failed to initialize KS8695 clock source\n");
 
-	/* re-enable timer1 */
-	writel_relaxed(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	/*
+	 * Use timer 1 to fire IRQs on the timeline, only support one-shot
+	 * mode and the system will take care of the rest. Minimum 2 cycles
+	 * (one on each counter) maximum 2*2^32, but the API will only
+	 * accept up to a 32bit full word (0xFFFFFFFFU).
+	 */
+	clockevents_config_and_register(&clockevent_ks8695,
+					KS8695_CLOCK_RATE, 2,
+					0xFFFFFFFFU);
 }
 
 static void __init ks8695_timer_init (void)
@@ -126,7 +176,6 @@ static void __init ks8695_timer_init (void)
 
 struct sys_timer ks8695_timer = {
 	.init		= ks8695_timer_init,
-	.offset		= ks8695_gettimeoffset,
 };
 
 void ks8695_restart(char mode, const char *cmd)
-- 
1.7.7.6



From linus.walleij at linaro.org  Wed Aug 29 14:27:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 Aug 2012 20:27:02 +0200
Subject: [PATCH 2/4] ARM: ks8695: use [readl|writel]_relaxed()
Message-ID: <1346264822-20347-1-git-send-email-linus.walleij@linaro.org>

I have no clue why __raw* macros are used here, but I strongly
suspect there is no good reason at all for this, so removing
another bad example.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ks8695/time.c |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 6427b7c..ae9dacc 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -67,11 +67,11 @@ static unsigned long ks8695_gettimeoffset (void)
 	 * interrupt.  We solve this by ensuring that the counter has not
 	 * reloaded between our two reads.
 	 */
-	elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+	elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
 	do {
 		tick2 = elapsed;
-		intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
-		elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
+		intpending = readl_relaxed(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
+		elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
 	} while (elapsed > tick2);
 
 	/* Convert to number of ticks expired (not remaining) */
@@ -106,14 +106,14 @@ static void ks8695_timer_setup(void)
 	unsigned long tmcon;
 
 	/* disable timer1 */
-	tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-	__raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+	writel_relaxed(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
 
-	__raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
-	__raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
+	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
 
 	/* re-enable timer1 */
-	__raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	writel_relaxed(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
 }
 
 static void __init ks8695_timer_init (void)
@@ -138,12 +138,12 @@ void ks8695_restart(char mode, const char *cmd)
 		soft_restart(0);
 
 	/* disable timer0 */
-	reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-	__raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+	reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+	writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 
 	/* enable watchdog mode */
-	__raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+	writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
 
 	/* re-enable timer0 */
-	__raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+	writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 }
-- 
1.7.7.6



From mkl at pengutronix.de  Wed Aug 29 16:00:32 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Wed, 29 Aug 2012 22:00:32 +0200
Subject: [PATCH v6 1/3] USB: chipidea: add imx usbmisc support
In-Reply-To: <20120829110137.GA26594@pengutronix.de>
References: <1346137109-32247-1-git-send-email-richard.zhao@freescale.com>
 <1346137109-32247-2-git-send-email-richard.zhao@freescale.com>
 <871uiqkuhb.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829081020.GX26594@pengutronix.de>
 <87ehmqj925.fsf@ashishki-desk.ger.corp.intel.com>
 <20120829110137.GA26594@pengutronix.de>
Message-ID: <503E74E0.6040503@pengutronix.de>

On 08/29/2012 01:01 PM, Sascha Hauer wrote:
> On Wed, Aug 29, 2012 at 01:18:10PM +0300, Alexander Shishkin wrote:
>> Sascha Hauer <s.hauer at pengutronix.de> writes:
>>
>>> On Wed, Aug 29, 2012 at 10:50:08AM +0300, Alexander Shishkin wrote:
>>>> Richard Zhao <richard.zhao at freescale.com> writes:
>>>>
>>>>> i.MX usb controllers shares non-core registers, which may include
>>>>> SoC specific controls. We take it as a usbmisc device and usbmisc
>>>>> driver set operations needed by ci13xxx_imx driver.
>>>>>
>>>>> For example, Sabrelite board has bad over-current design, we can
>>>>> usbmisc to disable over-current detect.
>>>>
>>>> Why does this have to be part of the usb driver instead of SoC specific
>>>> code? It looks like you've created a whole new device/driver
>>>> infrastructure just to disable overcurrent for a specific board.
>>>
>>> Richards code indeed only handles overcurrent for a specific board, but
>>> there are more bits to configure in the longer run: power pin
>>> polarities, ULPI/serial mode select and some more.

We already have a patch adding a usbmisc_imx53_init() function to that
driver.

>> Sounds to me like these things that should be taken care of by the phy
>> driver, which will likely be simpler from both driver's and devicetree's
>> perspective.
> 
> Most i.MX SoCs have three instances of the chipidea core. These cores
> share a single register space for controlling the mentioned bits (the
> usbmisc register space). The usbmisc looks different on the different
> SoCs.
> Indeed they control some phy specific aspects, but the phy itself may
> also be an external ULPI or UTMI phy with a separate driver. So if we
> integrate the usbmisc into the phy wouldn't that mean that it has to
> be integrated into all possible phy drivers?
> 
> From a devicetrees perspective it makes sense to integrate the flags
> into the chipidea nodes, because there is one node per chipidea core,
> but only one usbmisc unit for all ports on the SoC. So we can do a:
> 
> 	chipidea at ofs {
> 		disable-overcurrent = <1>;
> 	};
> 
> instead of
> 
> 	usbmisc at ofs {
> 		disable-overcurrent-port0 = <1>;
> 		disable-overcurrent-port1 = <0>;
> 		...
> 	};

+1

IMHO looks much cleaner.

>>>> And the infrastructure boils down to a complex way of passing a callback
>>>> from imx driver to another imx driver, that only works if they are
>>>> probed in the right order. I don't see any point in doing it like this
>>>> other than inflating the device tree tables even further.
>>>>
>>>> Why can't this be part of the SoC code like it is done, for example in
>>>> arch/arm/mach-omap2/control.c?
>>>
>>> The settings are board specific, so there must be some way to configure
>>> them in the devicetree.
>>
>> But I'm sure there's a way to control board-specific settings/kludges
>> from devicetree?
> 
> Hm, yes. That's what Richard does, right? I may be misunderstanding you
> here.
> 
> Sascha

Marc


-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From j-pihet at ti.com  Wed Aug 29 16:48:25 2012
From: j-pihet at ti.com (Pihet-XID, Jean)
Date: Wed, 29 Aug 2012 13:48:25 -0700
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
In-Reply-To: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
References: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
Message-ID: <CAN5iSWp9LJjC9B3fiAJhuYVkfNzC98WkvQKPiVt8+tqxr==COg@mail.gmail.com>

On Wed, Aug 29, 2012 at 11:41 AM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Hi,
>
> for everyone at Linux Plumbers Conference/LinuxCon, we'll be having a
> Linux on TI SoCs BoF on Thursday, August 30 in Nautilus 1.
Great! Is there a schedule already?

Thanks!
Jean

>
>
>
> - Paul


From linus.walleij at linaro.org  Wed Aug 29 14:27:12 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 29 Aug 2012 20:27:12 +0200
Subject: [PATCH 3/4] ARM: ks8695: delete resume hook from timer
Message-ID: <1346264832-20379-1-git-send-email-linus.walleij@linaro.org>

This system does not support suspend/resume so let's skip this
hook altogether.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ks8695/time.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index ae9dacc..6974c23 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -127,7 +127,6 @@ static void __init ks8695_timer_init (void)
 struct sys_timer ks8695_timer = {
 	.init		= ks8695_timer_init,
 	.offset		= ks8695_gettimeoffset,
-	.resume		= ks8695_timer_setup,
 };
 
 void ks8695_restart(char mode, const char *cmd)
-- 
1.7.7.6



From will.deacon at arm.com  Wed Aug 29 17:10:34 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 Aug 2012 22:10:34 +0100
Subject: [GIT PULL] ARM perf updates for 3.7
Message-ID: <20120829211034.GA13222@mudshark.cambridge.arm.com>

Hi Arnd, Olof,

I appreciate that perf changes don't usually go via arm-soc, but in this
case I'm touching a bunch of platforms (albeit in a fairly mechanical way)
so it would be great if you could pull this into a branch for 3.7. Jon can
then use it as a base for his OMAP PMU patches and I think that ST and
Samsung may also have patches that depend on this lot.

The changes outside of platform code are restricted to perf files and the
whole series has been in -next since -rc1.

Cheers,

Will

---

The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git tags/arm-perf-3.7

for you to fetch changes up to 051f1b13144dd8553d5a5104dde94c7263ae3ba7:

  ARM: perf: move irq registration into pmu implementation (2012-08-23 11:35:52 +0100)

----------------------------------------------------------------
Bunch of perf updates for the ARM backend that pave the way for
big.LITTLE support in the future. The separation of CPU and PMU code
is also the start of being able to move some of this stuff under
drivers/.

----------------------------------------------------------------
Jon Hunter (1):
      ARM: PMU: Add runtime PM Support

Sudeep KarkadaNagesha (2):
      ARM: pmu: remove arm_pmu_type enumeration
      ARM: perf: move irq registration into pmu implementation

Will Deacon (6):
      ARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs
      ARM: pmu: remove unused reservation mechanism
      ARM: perf: remove mysterious compiler barrier
      ARM: perf: probe devicetree in preference to current CPU
      ARM: perf: prepare for moving CPU PMU code into separate file
      ARM: perf: move CPU-specific PMU handling code into separate file

 Documentation/devicetree/bindings/arm/pmu.txt |   4 +
 MAINTAINERS                                   |   1 -
 arch/arm/Kconfig                              |   8 +-
 arch/arm/include/asm/perf_event.h             |   9 +-
 arch/arm/include/asm/pmu.h                    |  77 ++----
 arch/arm/kernel/Makefile                      |   3 +-
 arch/arm/kernel/perf_event.c                  | 347 ++++----------------------
 arch/arm/kernel/perf_event_cpu.c              | 295 ++++++++++++++++++++++
 arch/arm/kernel/perf_event_v6.c               |  12 +-
 arch/arm/kernel/perf_event_v7.c               |  32 +--
 arch/arm/kernel/perf_event_xscale.c           |  10 +-
 arch/arm/kernel/pmu.c                         |  36 ---
 arch/arm/mach-bcmring/arch.c                  |   3 +-
 arch/arm/mach-omap2/devices.c                 |   3 +-
 arch/arm/mach-pxa/devices.c                   |   3 +-
 arch/arm/mach-realview/realview_eb.c          |   3 +-
 arch/arm/mach-realview/realview_pb1176.c      |   3 +-
 arch/arm/mach-realview/realview_pb11mp.c      |   3 +-
 arch/arm/mach-realview/realview_pba8.c        |   3 +-
 arch/arm/mach-realview/realview_pbx.c         |   3 +-
 arch/arm/mach-tegra/devices.c                 |   3 +-
 arch/arm/mach-ux500/cpu-db8500.c              |   3 +-
 arch/arm/mach-vexpress/ct-ca9x4.c             |   3 +-
 arch/arm/plat-iop/pmu.c                       |   3 +-
 arch/arm/plat-samsung/devs.c                  |   3 +-
 25 files changed, 424 insertions(+), 449 deletions(-)
 create mode 100644 arch/arm/kernel/perf_event_cpu.c
 delete mode 100644 arch/arm/kernel/pmu.c


From will.deacon at arm.com  Wed Aug 29 17:25:23 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 Aug 2012 22:25:23 +0100
Subject: [PATCH v2 1/2] ARM: delay: set loops_per_jiffy when moving to
 timer-based loop
Message-ID: <1346275524-13817-1-git-send-email-will.deacon@arm.com>

The delay functions may be called by some platforms between switching to
the timer-based delay loop but before calibration. In this case, the
initial loops_per_jiffy may not be suitable for the timer (although a
compromise may be achievable) and delay times may be considered too
inaccurate.

This patch updates loops_per_jiffy when switching to the timer-based
delay loop so that delays are consistent prior to calibration.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/lib/delay.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index d6dacc6..395d5fb 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq)
 {
 	pr_info("Switching to timer-based delay loop\n");
 	lpj_fine			= freq / HZ;
+	loops_per_jiffy			= lpj_fine;
 	arm_delay_ops.delay		= __timer_delay;
 	arm_delay_ops.const_udelay	= __timer_const_udelay;
 	arm_delay_ops.udelay		= __timer_udelay;
-- 
1.7.4.1



From will.deacon at arm.com  Wed Aug 29 17:25:24 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 Aug 2012 22:25:24 +0100
Subject: [PATCH v2 2/2] ARM: delay: add registration mechanism for delay timer
 sources
In-Reply-To: <1346275524-13817-1-git-send-email-will.deacon@arm.com>
References: <1346275524-13817-1-git-send-email-will.deacon@arm.com>
Message-ID: <1346275524-13817-2-git-send-email-will.deacon@arm.com>

From: Jonathan Austin <Jonathan.Austin at arm.com>

The current timer-based delay loop relies on the architected timer to
initiate the switch away from the polling-based implementation. This is
unfortunate for platforms without the architected timers but with a
suitable delay source (that is, constant frequency, always powered-up
and ticking as long as the CPUs are online).

This patch introduces a registration mechanism for the delay timer
(which provides an unconditional read_current_timer implementation) and
updates the architected timer code to use the new interface.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

v2: Changed prototype for low-level read_current_timer to return the
    timer value directly.

 arch/arm/include/asm/arch_timer.h |    1 -
 arch/arm/include/asm/delay.h      |    9 +++++++++
 arch/arm/include/asm/timex.h      |    6 ------
 arch/arm/kernel/arch_timer.c      |   17 ++++++++---------
 arch/arm/lib/delay.c              |   31 ++++++++++++++++++++++---------
 5 files changed, 39 insertions(+), 25 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 62e7547..88401c2 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -4,7 +4,6 @@
 #include <asm/errno.h>
 
 #ifdef CONFIG_ARM_ARCH_TIMER
-#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
 #else
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index dc61451..50928e8 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -15,6 +15,11 @@
 
 #ifndef __ASSEMBLY__
 
+struct delay_timer {
+	unsigned long (*read_current_timer)(void);
+	unsigned long freq;
+};
+
 extern struct arm_delay_ops {
 	void (*delay)(unsigned long);
 	void (*const_udelay)(unsigned long);
@@ -56,6 +61,10 @@ extern void __loop_delay(unsigned long loops);
 extern void __loop_udelay(unsigned long usecs);
 extern void __loop_const_udelay(unsigned long);
 
+/* Delay-loop timer registration. */
+#define ARCH_HAS_READ_CURRENT_TIMER
+extern void register_current_timer_delay(struct delay_timer *timer);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* defined(_ARM_DELAY_H) */
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce11944..9acc135 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,15 +12,9 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
-#include <asm/arch_timer.h>
 #include <mach/timex.h>
 
 typedef unsigned long cycles_t;
-
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
 #define get_cycles()	({ cycles_t c; read_current_timer(&c) ? 0 : c; })
-#else
-#define get_cycles()	(0)
-#endif
 
 #endif
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index cf25880..700917a 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 
 #include <asm/cputype.h>
+#include <asm/delay.h>
 #include <asm/localtimer.h>
 #include <asm/arch_timer.h>
 #include <asm/system_info.h>
@@ -31,8 +32,7 @@ static int arch_timer_ppi;
 static int arch_timer_ppi2;
 
 static struct clock_event_device __percpu **arch_timer_evt;
-
-extern void init_current_timer_delay(unsigned long freq);
+static struct delay_timer arch_delay_timer;
 
 /*
  * Architected system timer support.
@@ -225,12 +225,9 @@ static cycle_t arch_counter_read(struct clocksource *cs)
 	return arch_counter_get_cntpct();
 }
 
-int read_current_timer(unsigned long *timer_val)
+static unsigned long arch_timer_read_current_timer(void)
 {
-	if (!arch_timer_rate)
-		return -ENXIO;
-	*timer_val = arch_counter_get_cntpct();
-	return 0;
+	return arch_counter_get_cntpct();
 }
 
 static struct clocksource clocksource_counter = {
@@ -302,11 +299,13 @@ static int __init arch_timer_register(void)
 		arch_timer_global_evt.cpumask = cpumask_of(0);
 		err = arch_timer_setup(&arch_timer_global_evt);
 	}
-
 	if (err)
 		goto out_free_irq;
 
-	init_current_timer_delay(arch_timer_rate);
+	/* Use the architected timer for the delay loop. */
+	arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
+	arch_delay_timer.freq = arch_timer_rate;
+	register_current_timer_delay(&arch_delay_timer);
 	return 0;
 
 out_free_irq:
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 395d5fb..fe6f4fb 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -34,7 +34,14 @@ struct arm_delay_ops arm_delay_ops = {
 	.udelay		= __loop_udelay,
 };
 
-#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static struct delay_timer *delay_timer;
+static bool delay_calibrated;
+
+int read_current_timer(unsigned long *timer_val)
+{
+	return delay_timer ? delay_timer->read_current_timer() : -ENXIO;
+}
+
 static void __timer_delay(unsigned long cycles)
 {
 	cycles_t start = get_cycles();
@@ -55,18 +62,24 @@ static void __timer_udelay(unsigned long usecs)
 	__timer_const_udelay(usecs * UDELAY_MULT);
 }
 
-void __init init_current_timer_delay(unsigned long freq)
+void __init register_current_timer_delay(struct delay_timer *timer)
 {
-	pr_info("Switching to timer-based delay loop\n");
-	lpj_fine			= freq / HZ;
-	loops_per_jiffy			= lpj_fine;
-	arm_delay_ops.delay		= __timer_delay;
-	arm_delay_ops.const_udelay	= __timer_const_udelay;
-	arm_delay_ops.udelay		= __timer_udelay;
+	if (!delay_calibrated) {
+		pr_info("Switching to timer-based delay loop\n");
+		delay_timer			= timer;
+		lpj_fine			= timer->freq / HZ;
+		loops_per_jiffy			= lpj_fine;
+		arm_delay_ops.delay		= __timer_delay;
+		arm_delay_ops.const_udelay	= __timer_const_udelay;
+		arm_delay_ops.udelay		= __timer_udelay;
+		delay_calibrated		= true;
+	} else {
+		pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
+	}
 }
 
 unsigned long __cpuinit calibrate_delay_is_known(void)
 {
+	delay_calibrated = true;
 	return lpj_fine;
 }
-#endif
-- 
1.7.4.1



From will.deacon at arm.com  Wed Aug 29 17:34:05 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 29 Aug 2012 22:34:05 +0100
Subject: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
In-Reply-To: <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
Message-ID: <20120829213405.GC13868@mudshark.cambridge.arm.com>

On Wed, Aug 29, 2012 at 02:14:56AM +0100, Chanho Park wrote:
> This patch define irq numbers of ARM performance monitoring unit for exynos4.
> The number of CPU cores and PMU irq numbers are vary according to soc types.
> So we need to identify each soc type using soc_is_xxx function and define the
> pmu irqs dynamically. In case of exynos4412, there are 4 cpu cores and pmus.
> 
> Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   45 ++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
>  arch/arm/plat-samsung/devs.c             |    2 +-
>  3 files changed, 52 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index be61564..24b78bd 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -30,11 +30,13 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  #include <asm/cacheflush.h>
> +#include <asm/pmu.h>

Why do you need this header file?

>  #include <mach/regs-irq.h>
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-gpio.h>
>  #include <mach/pmu.h>
> +#include <mach/irqs.h>
>  
>  #include <plat/cpu.h>
>  #include <plat/clock.h>
> @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
>  	return 0;
>  }
>  arch_initcall(exynos_init_irq_eint);
> +
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +static struct resource exynos42xx_pmu_resource[] = {
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +};
> +
> +static struct platform_device exynos42xx_device_pmu = {
> +	.name		= "arm-pmu",
> +	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
> +	.resource	= exynos42xx_pmu_resource,
> +};
> +#endif

Given that you don't pass an id and your device-tree binding is that for
Cortex A15, I assume this patch series is based on my perf/updates branch?

That's good because it reduces the potential for conflicts, but you should
make sure that whoever you send this to is aware of the dependency.

Cheers,

Will


From mturquette at linaro.org  Wed Aug 29 17:41:02 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Wed, 29 Aug 2012 14:41:02 -0700
Subject: [PATCH v2 1/4] [RFC] clk: new locking scheme for reentrancy
In-Reply-To: <CADTbHxob_pkYN_73AD4YL_Ki5i40iLTJuN0rPuFzYcyyhfoMAQ@mail.gmail.com>
References: <1345074214-17531-1-git-send-email-mturquette@linaro.org>
 <1345074214-17531-2-git-send-email-mturquette@linaro.org>
 <CADTbHxob_pkYN_73AD4YL_Ki5i40iLTJuN0rPuFzYcyyhfoMAQ@mail.gmail.com>
Message-ID: <20120829214102.4450.35547@nucleus>

Quoting Pankaj Jangra (2012-08-27 10:05:29)
> Hi Mike,
> 
> On Thu, Aug 16, 2012 at 5:13 AM, Mike Turquette <mturquette at linaro.org> wrote:
> > +}
> > +
> > +void __clk_unprepare(struct clk *clk, struct clk *top)
> 
> Why do you need to change the signature of __clk_prepare and
> __clk_unprepare functions ?
> I mean i did not understand the use of passing struct clk *top? As i
> understand, it tells when you reach at the last
> clk struct in the tree which needs to be prepared/unprepared. Do we
> have extra benefit of this or if i am missing something?
> 

This series breaks compatibility with the internal clk functions.  So if
you were using __clk_prepare in your code somewhere then this will no
longer work.  It is likely you could just call clk_prepare in the same
place since there is some reentrancy introduced in this series.

Your understanding of top is correct: I want to avoid walking to the
root of the clock tree every time.  We determine the top based on
finding a positive clk->enable_count value.  There is no "extra
benefit", but locking to the root of the tree would destroy the goal of
reentrancy since there would be locking collisions at the top of the
tree.

<snip>
> > +               if (IS_ERR(top)) {
> > +                       pr_debug("%s: %s failed with %ld on attempt %d\n",
> > +                                       __func__, clk->name, PTR_ERR(top),
> > +                                       tries);
> > +                       wait_for_completion(&clk_completion);
> > +                       if (WAIT_TRIES == ++tries)
> > +                               break;
> > +               } else
> > +                       break;
> 
> Braces around else part please.
> 

OK.

> > +       }
> > +
> > +       if (WAIT_TRIES == tries) {
> > +               pr_warning("%s: failed to lock clocks; cyclical dependency?\n",
> > +                               __func__);
> > +               return;
> > +       }
> > +
> > +       /* unprepare the list of clocks from clk to top */
> > +       __clk_unprepare(clk, top);
> > +
> 
> > +       /* unprepare the list of clocks from clk to top */
> > +       __clk_prepare(clk, top);
> 
> You mean prepare right ? :)
> 

Right.  Will fix in next version of RFC.

Thanks much for the review,
Mike

> 
> 
> Regards,
> Pankaj Kumar


From grinberg at compulab.co.il  Wed Aug 29 17:42:40 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 30 Aug 2012 00:42:40 +0300
Subject: [PATCH 6/9] ARM: OMAP1: move omap1_bl pdata out of arch/arm/*
In-Reply-To: <1346252664.12380.0.camel@deskari>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
 <1346195937-6383-7-git-send-email-grinberg@compulab.co.il>
 <1346252664.12380.0.camel@deskari>
Message-ID: <503E8CD0.2090608@compulab.co.il>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 08/29/12 18:04, Tomi Valkeinen wrote:
> On Wed, 2012-08-29 at 02:18 +0300, Igor Grinberg wrote:
>> omap1 backlight platform data resides inside plat/board.h while it
>> should be inside include/linux/...
>> Move the omap1 backlight platform data to
>> include/linux/platform_data/.
>>
>> Cc: Richard Purdie <rpurdie at rpsys.net>
>> Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
>> Cc: linux-fbdev at vger.kernel.org
>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>> ---
>>  arch/arm/mach-omap1/board-osk.c         |    1 +
>>  arch/arm/mach-omap1/board-palmte.c      |    1 +
>>  arch/arm/mach-omap1/board-palmtt.c      |    1 +
>>  arch/arm/mach-omap1/board-palmz71.c     |    1 +
>>  arch/arm/plat-omap/include/plat/board.h |    7 -------
>>  drivers/video/backlight/omap1_bl.c      |    2 +-
>>  include/linux/platform_data/omap1_bl.h  |   11 +++++++++++
>>  7 files changed, 16 insertions(+), 8 deletions(-)
>>  create mode 100644 include/linux/platform_data/omap1_bl.h

[...]

>> diff --git a/include/linux/platform_data/omap1_bl.h b/include/linux/platform_data/omap1_bl.h
>> new file mode 100644
>> index 0000000..881a8e9
>> --- /dev/null
>> +++ b/include/linux/platform_data/omap1_bl.h
>> @@ -0,0 +1,11 @@
>> +#ifndef __OMAP1_BL_H__
>> +#define __OMAP1_BL_H__
>> +
>> +#include <linux/device.h>
> 
> You could use struct device; here.

Yes I know, but I don't think it is any better.

> 
>> +
>> +struct omap_backlight_config {
>> +	int default_intensity;
>> +	int (*set_power)(struct device *dev, int state);
>> +};
>> +
>> +#endif
> 
> Acked-by: Tomi Valkeinen <tomi.valkeinen at ti.com>

Thanks!


- -- 
Regards,
Igor.
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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/


ycdLeCP+C7ZcsaNApWMS
=kElj
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From swarren at wwwdotorg.org  Wed Aug 29 17:49:34 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 29 Aug 2012 14:49:34 -0700
Subject: [PATCH] clk: Make the generic clock API available by default
In-Reply-To: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <503E8E6E.1010101@wwwdotorg.org>

On 08/28/12 13:35, Mark Brown wrote:
> Rather than requiring platforms to select the generic clock API to make
> it available make the API available as a user selectable option unless the
> user either selects HAVE_CUSTOM_CLK (if they have their own implementation)
> or selects COMMON_CLK (if they depend on the generic implementation).
>
> All current architectures that HAVE_CLK but don't use the common clock
> framework have selects of HAVE_CUSTOM_CLK added.
>
> This allows drivers to use the generic API on platforms which have no need
> for the clock API at platform level.

> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig

> @@ -674,6 +676,7 @@ config ARCH_TEGRA
>   	select GENERIC_CLOCKEVENTS
>   	select GENERIC_GPIO
>   	select HAVE_CLK
> +	select HAVE_CUSTOM_CLK

For 3.7, Tegra will switch to the common clock framework. I think this 
patch would then disable that. How should we resolve this - rebase the 
Tegra common-clk tree on top of any branch containing this patch in 
order to remove that select statement?


From grinberg at compulab.co.il  Wed Aug 29 18:01:13 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 30 Aug 2012 01:01:13 +0300
Subject: [PATCH] ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
In-Reply-To: <CAMQu2gxZBq0wMw4rgbFpDT2pmA83ULKAJ-Mwv+VKvQQZMRQ4Dw@mail.gmail.com>
References: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>
 <CAMQu2gxZBq0wMw4rgbFpDT2pmA83ULKAJ-Mwv+VKvQQZMRQ4Dw@mail.gmail.com>
Message-ID: <503E9129.9060408@compulab.co.il>

On 08/28/12 01:43, Shilimkar, Santosh wrote:
> On Mon, Aug 27, 2012 at 3:26 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>> Currently, omap2_sync32k_clocksource_init() function initializes the 32K
>> timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
>> setting.
>> Fix this by providing a default implementation for
>> !CONFIG_OMAP_32K_TIMER case.
>>
>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>> Reviewed-by: Paul Walmsley <paul at pwsan.com>
>> ---
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Thanks Santosh!

Tony, apparently, this bug has been there for a while,
so probably I should have added:
Cc: stable at vger.kernel.org

Thanks!

-- 
Regards,
Igor.


From eduardo.valentin at ti.com  Wed Aug 29 18:02:32 2012
From: eduardo.valentin at ti.com (Valentin, Eduardo)
Date: Thu, 30 Aug 2012 01:02:32 +0300
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
In-Reply-To: <CAGF5oy_-3g3A8Eadn7uRm5srPCsuufFZ42estfRuAWy4JiqQ-w@mail.gmail.com>
References: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
 <CAN5iSWp9LJjC9B3fiAJhuYVkfNzC98WkvQKPiVt8+tqxr==COg@mail.gmail.com>
 <CAGF5oy_-3g3A8Eadn7uRm5srPCsuufFZ42estfRuAWy4JiqQ-w@mail.gmail.com>
Message-ID: <CAGF5oy9hf8ys=Cqvhto8tPnW=iuf2V3sRmJW+aoAmZS4Sdroyg@mail.gmail.com>

Cool! Which time is it?

On Thu, Aug 30, 2012 at 1:01 AM, Valentin, Eduardo
<eduardo.valentin at ti.com> wrote:
>
> Cool! Which time is it?
>
>
> On Wed, Aug 29, 2012 at 11:48 PM, Pihet-XID, Jean <j-pihet at ti.com> wrote:
>>
>> On Wed, Aug 29, 2012 at 11:41 AM, Paul Walmsley <paul at pwsan.com> wrote:
>> >
>> > Hi,
>> >
>> > for everyone at Linux Plumbers Conference/LinuxCon, we'll be having a
>> > Linux on TI SoCs BoF on Thursday, August 30 in Nautilus 1.
>> Great! Is there a schedule already?
>>
>> Thanks!
>> Jean
>>
>> >
>> >
>> >
>> > - Paul
>
>
>
>
> --
>
> Eduardo Valentin




--

Eduardo Valentin


From mlocke at ti.com  Wed Aug 29 18:07:49 2012
From: mlocke at ti.com (Locke, Matthew)
Date: Wed, 29 Aug 2012 22:07:49 +0000
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
In-Reply-To: <CAGF5oy9hf8ys=Cqvhto8tPnW=iuf2V3sRmJW+aoAmZS4Sdroyg@mail.gmail.com>
References: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
 <CAN5iSWp9LJjC9B3fiAJhuYVkfNzC98WkvQKPiVt8+tqxr==COg@mail.gmail.com>
 <CAGF5oy_-3g3A8Eadn7uRm5srPCsuufFZ42estfRuAWy4JiqQ-w@mail.gmail.com>,
 <CAGF5oy9hf8ys=Cqvhto8tPnW=iuf2V3sRmJW+aoAmZS4Sdroyg@mail.gmail.com>
Message-ID: <B1BA3B0F-098D-4AC8-A514-6862D0F98EC6@ti.com>

During lunch

On Aug 29, 2012, at 3:02 PM, "Valentin, Eduardo" <eduardo.valentin at ti.com> wrote:

> Cool! Which time is it?
> 
> On Thu, Aug 30, 2012 at 1:01 AM, Valentin, Eduardo
> <eduardo.valentin at ti.com> wrote:
>> 
>> Cool! Which time is it?
>> 
>> 
>> On Wed, Aug 29, 2012 at 11:48 PM, Pihet-XID, Jean <j-pihet at ti.com> wrote:
>>> 
>>> On Wed, Aug 29, 2012 at 11:41 AM, Paul Walmsley <paul at pwsan.com> wrote:
>>>> 
>>>> Hi,
>>>> 
>>>> for everyone at Linux Plumbers Conference/LinuxCon, we'll be having a
>>>> Linux on TI SoCs BoF on Thursday, August 30 in Nautilus 1.
>>> Great! Is there a schedule already?
>>> 
>>> Thanks!
>>> Jean
>>> 
>>>> 
>>>> 
>>>> 
>>>> - Paul
>> 
>> 
>> 
>> 
>> --
>> 
>> Eduardo Valentin
> 
> 
> 
> 
> --
> 
> Eduardo Valentin


From robherring2 at gmail.com  Wed Aug 29 18:31:26 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:26 -0500
Subject: [PATCH 00/10] Make mach/gpio.h optional
Message-ID: <1346279496-26286-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This series makes mach/gpio.h optional like we have done for other mach
headers in preparation for multi-platform kernel images. Unfortunately,
it adds more mach includes to drivers/, but really they are just now
explicitly included and easily found.

A few platforms like Samsung were such a mess I didn't convert them and
they still require a gpio.h.

This is build tested on all ARM defconfigs. There may be a few lingering
failures, but I've iterated thru builds several times.

The series plus multi-platform support is available here:

git://sources.calxeda.com/kernel/linux.git multi-plat

Rob

Rob Herring (10):
  usb: pxa27x_udc: remove IRQ_USB define
  gpio: pxa: add explicit includes for cpu_is_X macros
  serial: atmel: add explict mach/gpio.h include
  net: pxaficp_ir: add explicit mach/gpio.h includes
  ARM: at91: explicitly include mach/gpio.h
  ARM: shmobile: explicitly include mach/gpio.h
  ARM: orion: add explict mach/gpio.h includes
  ARM: omap2: add explict mach/gpio.h includes
  ARM: omap1: add explict mach/gpio.h includes
  ARM: make mach/gpio.h headers optional

 arch/arm/Kconfig                               |   17 +++++++++++++
 arch/arm/include/asm/gpio.h                    |    2 ++
 arch/arm/mach-at91/at91rm9200_devices.c        |    1 +
 arch/arm/mach-at91/at91sam9260_devices.c       |    1 +
 arch/arm/mach-at91/at91sam9261_devices.c       |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c       |    1 +
 arch/arm/mach-at91/at91sam9g45_devices.c       |    1 +
 arch/arm/mach-at91/at91sam9rl_devices.c        |    1 +
 arch/arm/mach-at91/board-1arm.c                |    1 +
 arch/arm/mach-at91/board-afeb-9260v1.c         |    1 +
 arch/arm/mach-at91/board-cam60.c               |    1 +
 arch/arm/mach-at91/board-carmeva.c             |    1 +
 arch/arm/mach-at91/board-cpu9krea.c            |    1 +
 arch/arm/mach-at91/board-cpuat91.c             |    1 +
 arch/arm/mach-at91/board-csb337.c              |    1 +
 arch/arm/mach-at91/board-csb637.c              |    1 +
 arch/arm/mach-at91/board-eb9200.c              |    1 +
 arch/arm/mach-at91/board-ecbat91.c             |    1 +
 arch/arm/mach-at91/board-eco920.c              |    1 +
 arch/arm/mach-at91/board-flexibity.c           |    1 +
 arch/arm/mach-at91/board-foxg20.c              |    1 +
 arch/arm/mach-at91/board-gsia18s.c             |    1 +
 arch/arm/mach-at91/board-kafa.c                |    1 +
 arch/arm/mach-at91/board-kb9202.c              |    1 +
 arch/arm/mach-at91/board-neocore926.c          |    1 +
 arch/arm/mach-at91/board-pcontrol-g20.c        |    1 +
 arch/arm/mach-at91/board-picotux200.c          |    1 +
 arch/arm/mach-at91/board-qil-a9260.c           |    1 +
 arch/arm/mach-at91/board-rm9200dk.c            |    1 +
 arch/arm/mach-at91/board-rm9200ek.c            |    1 +
 arch/arm/mach-at91/board-rsi-ews.c             |    1 +
 arch/arm/mach-at91/board-sam9-l9260.c          |    1 +
 arch/arm/mach-at91/board-sam9260ek.c           |    1 +
 arch/arm/mach-at91/board-sam9261ek.c           |    1 +
 arch/arm/mach-at91/board-sam9263ek.c           |    1 +
 arch/arm/mach-at91/board-sam9g20ek.c           |    1 +
 arch/arm/mach-at91/board-sam9m10g45ek.c        |    1 +
 arch/arm/mach-at91/board-sam9rlek.c            |    1 +
 arch/arm/mach-at91/board-snapper9260.c         |    1 +
 arch/arm/mach-at91/board-stamp9g20.c           |    1 +
 arch/arm/mach-at91/board-usb-a926x.c           |    1 +
 arch/arm/mach-at91/board-yl-9200.c             |    1 +
 arch/arm/mach-at91/gpio.c                      |    1 +
 arch/arm/mach-at91/leds.c                      |    1 +
 arch/arm/mach-at91/pm.c                        |    1 +
 arch/arm/mach-dove/irq.c                       |    1 +
 arch/arm/mach-dove/mpp.c                       |    1 +
 arch/arm/mach-ep93xx/include/mach/gpio.h       |    1 -
 arch/arm/mach-highbank/include/mach/gpio.h     |    1 -
 arch/arm/mach-ixp4xx/include/mach/gpio.h       |    2 --
 arch/arm/mach-kirkwood/irq.c                   |    1 +
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c   |    1 +
 arch/arm/mach-mmp/include/mach/gpio.h          |    8 ------
 arch/arm/mach-msm/include/mach/gpio.h          |    1 -
 arch/arm/mach-mv78xx0/irq.c                    |    1 +
 arch/arm/mach-mxs/include/mach/gpio.h          |    1 -
 arch/arm/mach-nomadik/include/mach/gpio.h      |    4 ---
 arch/arm/mach-omap1/board-ams-delta.c          |    1 +
 arch/arm/mach-omap1/board-osk.c                |    1 +
 arch/arm/mach-omap1/gpio15xx.c                 |    1 +
 arch/arm/mach-omap1/gpio16xx.c                 |    1 +
 arch/arm/mach-omap1/gpio7xx.c                  |    1 +
 arch/arm/mach-omap1/leds-h2p2-debug.c          |    1 +
 arch/arm/mach-omap1/leds.c                     |    1 +
 arch/arm/mach-omap2/board-zoom-display.c       |    1 +
 arch/arm/mach-omap2/gpio.c                     |    1 +
 arch/arm/mach-omap2/pm24xx.c                   |    1 +
 arch/arm/mach-omap2/pm34xx.c                   |    1 +
 arch/arm/mach-orion5x/d2net-setup.c            |    1 +
 arch/arm/mach-orion5x/dns323-setup.c           |    1 +
 arch/arm/mach-orion5x/irq.c                    |    1 +
 arch/arm/mach-orion5x/net2big-setup.c          |    1 +
 arch/arm/mach-picoxcell/include/mach/gpio.h    |    1 -
 arch/arm/mach-pxa/include/mach/gpio.h          |   32 ------------------------
 arch/arm/mach-realview/include/mach/gpio.h     |    1 -
 arch/arm/mach-shmobile/board-ap4evb.c          |    1 +
 arch/arm/mach-shmobile/board-armadillo800eva.c |    1 +
 arch/arm/mach-shmobile/board-g4evm.c           |    1 +
 arch/arm/mach-shmobile/board-mackerel.c        |    1 +
 arch/arm/mach-shmobile/include/mach/gpio.h     |   14 -----------
 arch/arm/mach-shmobile/pfc-r8a7740.c           |    2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c           |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh7377.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c            |    2 +-
 arch/arm/mach-spear13xx/include/mach/gpio.h    |   19 --------------
 arch/arm/mach-spear3xx/include/mach/gpio.h     |   19 --------------
 arch/arm/mach-spear6xx/include/mach/gpio.h     |   19 --------------
 arch/arm/mach-tegra/include/mach/gpio.h        |    1 -
 arch/arm/mach-u300/include/mach/gpio.h         |    1 -
 arch/arm/mach-ux500/include/mach/gpio.h        |    5 ----
 arch/arm/mach-versatile/include/mach/gpio.h    |    1 -
 arch/arm/mach-vexpress/include/mach/gpio.h     |    1 -
 arch/arm/mach-vt8500/include/mach/gpio.h       |    1 -
 arch/arm/plat-mxc/include/mach/gpio.h          |    1 -
 arch/arm/plat-orion/mpp.c                      |    1 +
 arch/arm/plat-spear/include/plat/gpio.h        |    1 -
 drivers/gpio/gpio-omap.c                       |    2 +-
 drivers/gpio/gpio-pxa.c                        |    4 +++
 drivers/net/irda/pxaficp_ir.c                  |    3 ++-
 drivers/sh/pfc/gpio.c                          |    1 +
 drivers/tty/serial/atmel_serial.c              |    2 +-
 drivers/usb/gadget/pxa27x_udc.c                |    2 +-
 104 files changed, 103 insertions(+), 145 deletions(-)
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-highbank/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-msm/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-realview/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-u300/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-vexpress/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/gpio.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/gpio.h
 delete mode 100644 arch/arm/plat-spear/include/plat/gpio.h

-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:27 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:27 -0500
Subject: [PATCH 01/10] usb: pxa27x_udc: remove IRQ_USB define
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

IRQ_USB was implicitly included by gpio.h. Use the existing variable
instead of IRQ_USB.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
---
 drivers/usb/gadget/pxa27x_udc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 644b430..7a8713c 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -2508,7 +2508,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev)
 			IRQF_SHARED, driver_name, udc);
 	if (retval != 0) {
 		dev_err(udc->dev, "%s: can't get irq %i, err %d\n",
-			driver_name, IRQ_USB, retval);
+			driver_name, udc->irq, retval);
 		goto err_irq;
 	}
 	retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:28 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:28 -0500
Subject: [PATCH 02/10] gpio: pxa: add explicit includes for cpu_is_X macros
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add the
necessary includes for cpu_is_X macros.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/gpio/gpio-pxa.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9cac88a..4d44e2f 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -27,6 +27,10 @@
 #include <linux/slab.h>
 
 #include <mach/irqs.h>
+#include <mach/hardware.h>
+#ifdef CONFIG_ARCH_MMP
+#include <mach/cputype.h>
+#endif
 
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:29 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:29 -0500
Subject: [PATCH 03/10] serial: atmel: add explict mach/gpio.h include
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explicit
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Alan Cox <alan at linux.intel.com>
---
 drivers/tty/serial/atmel_serial.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee..c799001 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -48,7 +48,7 @@
 
 #ifdef CONFIG_ARM
 #include <mach/cpu.h>
-#include <asm/gpio.h>
+#include <mach/gpio.h>
 #endif
 
 #define PDC_BUFFER_SIZE		512
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:30 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:30 -0500
Subject: [PATCH 04/10] net: pxaficp_ir: add explicit mach/gpio.h includes
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Samuel Ortiz <samuel at sortiz.org>
---
 drivers/net/irda/pxaficp_ir.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8d54767..e7e3e79 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -29,8 +29,9 @@
 
 #include <mach/dma.h>
 #include <mach/irda.h>
-#include <mach/regs-uart.h>
+#include <mach/irqs.h>
 #include <mach/regs-ost.h>
+#include <mach/regs-uart.h>
 
 #define FICP		__REG(0x40800000)  /* Start of FICP area */
 #define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:31 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:31 -0500
Subject: [PATCH 05/10] ARM: at91: explicitly include mach/gpio.h
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Andrew Victor <linux at maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/at91rm9200_devices.c  |    1 +
 arch/arm/mach-at91/at91sam9260_devices.c |    1 +
 arch/arm/mach-at91/at91sam9261_devices.c |    1 +
 arch/arm/mach-at91/at91sam9263_devices.c |    1 +
 arch/arm/mach-at91/at91sam9g45_devices.c |    1 +
 arch/arm/mach-at91/at91sam9rl_devices.c  |    1 +
 arch/arm/mach-at91/board-1arm.c          |    1 +
 arch/arm/mach-at91/board-afeb-9260v1.c   |    1 +
 arch/arm/mach-at91/board-cam60.c         |    1 +
 arch/arm/mach-at91/board-carmeva.c       |    1 +
 arch/arm/mach-at91/board-cpu9krea.c      |    1 +
 arch/arm/mach-at91/board-cpuat91.c       |    1 +
 arch/arm/mach-at91/board-csb337.c        |    1 +
 arch/arm/mach-at91/board-csb637.c        |    1 +
 arch/arm/mach-at91/board-eb9200.c        |    1 +
 arch/arm/mach-at91/board-ecbat91.c       |    1 +
 arch/arm/mach-at91/board-eco920.c        |    1 +
 arch/arm/mach-at91/board-flexibity.c     |    1 +
 arch/arm/mach-at91/board-foxg20.c        |    1 +
 arch/arm/mach-at91/board-gsia18s.c       |    1 +
 arch/arm/mach-at91/board-kafa.c          |    1 +
 arch/arm/mach-at91/board-kb9202.c        |    1 +
 arch/arm/mach-at91/board-neocore926.c    |    1 +
 arch/arm/mach-at91/board-pcontrol-g20.c  |    1 +
 arch/arm/mach-at91/board-picotux200.c    |    1 +
 arch/arm/mach-at91/board-qil-a9260.c     |    1 +
 arch/arm/mach-at91/board-rm9200dk.c      |    1 +
 arch/arm/mach-at91/board-rm9200ek.c      |    1 +
 arch/arm/mach-at91/board-rsi-ews.c       |    1 +
 arch/arm/mach-at91/board-sam9-l9260.c    |    1 +
 arch/arm/mach-at91/board-sam9260ek.c     |    1 +
 arch/arm/mach-at91/board-sam9261ek.c     |    1 +
 arch/arm/mach-at91/board-sam9263ek.c     |    1 +
 arch/arm/mach-at91/board-sam9g20ek.c     |    1 +
 arch/arm/mach-at91/board-sam9m10g45ek.c  |    1 +
 arch/arm/mach-at91/board-sam9rlek.c      |    1 +
 arch/arm/mach-at91/board-snapper9260.c   |    1 +
 arch/arm/mach-at91/board-stamp9g20.c     |    1 +
 arch/arm/mach-at91/board-usb-a926x.c     |    1 +
 arch/arm/mach-at91/board-yl-9200.c       |    1 +
 arch/arm/mach-at91/gpio.c                |    1 +
 arch/arm/mach-at91/leds.c                |    1 +
 arch/arm/mach-at91/pm.c                  |    1 +
 43 files changed, 43 insertions(+)

diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb732..8b15739 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -22,6 +22,7 @@
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..2b6caf3 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -26,6 +26,7 @@
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_adc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8df5c1b..e79d7b4 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -26,6 +26,7 @@
 #include <mach/at91sam9261_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..4a58359 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -25,6 +25,7 @@
 #include <mach/at91sam9263_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 0607399..799861f 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -33,6 +33,7 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
+#include <mach/gpio.h>
 
 #include <media/atmel-isi.h>
 
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..ca6abdd 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -23,6 +23,7 @@
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 22d8856..bbd9f05 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -37,6 +37,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be19..4d09924 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -45,6 +45,7 @@
 
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 477e708..bec435c 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -41,6 +41,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f..685a170 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -37,6 +37,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b..1d05046 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -45,6 +45,7 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043..cfa39e9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -41,6 +41,7 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc31..59741c1 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -40,6 +40,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 872871a..e36c63c 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -37,6 +37,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3f..8816928 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -37,6 +37,7 @@
 
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb2..90af119 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -40,6 +40,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde..8f4ba07 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -29,6 +29,7 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a8..790791a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -35,6 +35,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab124..1f7bc1f 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -44,6 +44,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index a9d5e78..8bf7046 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -35,6 +35,7 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/gsia18s.h>
 #include <mach/stamp9g20.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf..5945808 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -37,6 +37,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb8..3a88688 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -40,6 +40,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d..5deb106 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -47,6 +47,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 9ca3e32..d622a07 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -33,6 +33,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/stamp9g20.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 1270655..a33a6b5 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -41,6 +41,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e2..655b1f3 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -44,6 +44,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf97..0e42db0 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -43,6 +43,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e6..b1d0d36 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -43,6 +43,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43ae..f2b4d26 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -27,6 +27,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91_aic.h>
+#include <mach/gpio.h>
 
 #include <linux/gpio.h>
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da7..0a7e7e2 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -40,6 +40,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf..232a9f6 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -45,6 +45,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 #include <mach/system_rev.h>
 
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5..13cb9b4 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -49,6 +49,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 #include <mach/system_rev.h>
 
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf58..d1ce5cb 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -48,6 +48,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 #include <mach/system_rev.h>
 
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee0..4aecb95 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -46,6 +46,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 #include <mach/system_rev.h>
 
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 3d48ec1..74a7101 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -46,6 +46,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 #include <mach/system_rev.h>
 
 #include "sam9_smc.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ea..2a03138 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -34,6 +34,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index a4e031a..4eeae73 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -35,6 +35,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae16..836d25c 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -28,6 +28,7 @@
 #include <mach/board.h>
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9..76b5271 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -45,6 +45,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/gpio.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340..d98ae49 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -48,6 +48,7 @@
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..f498461 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -28,6 +28,7 @@
 
 #include <asm/mach/irq.h>
 
+#include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..042ba65 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 
 #include <mach/board.h>
+#include <mach/gpio.h>
 
 
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d865..363c40e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -28,6 +28,7 @@
 #include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include <mach/gpio.h>
 
 #include "generic.h"
 #include "pm.h"
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:32 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:32 -0500
Subject: [PATCH 06/10] ARM: shmobile: explicitly include mach/gpio.h
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-7-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
includes of necessary headers.

shmobile always uses gpiolib, so we can remove some of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Paul Mundt <lethal at linux-sh.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
---
 arch/arm/mach-shmobile/board-ap4evb.c          |    1 +
 arch/arm/mach-shmobile/board-armadillo800eva.c |    1 +
 arch/arm/mach-shmobile/board-g4evm.c           |    1 +
 arch/arm/mach-shmobile/board-mackerel.c        |    1 +
 arch/arm/mach-shmobile/include/mach/gpio.h     |   14 --------------
 arch/arm/mach-shmobile/pfc-r8a7740.c           |    2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c           |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh7377.c            |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c            |    2 +-
 drivers/sh/pfc/gpio.c                          |    1 +
 12 files changed, 11 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f172ca8..65a959a 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,6 +61,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
+#include <mach/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index cf10f92..2e647d8 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -38,6 +38,7 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <mach/common.h>
+#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include <mach/r8a7740.h>
 #include <media/mt9t112.h>
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index fa5dfc5..b8688c1 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -36,6 +36,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <mach/gpio.h>
 #include <mach/irqs.h>
 #include <mach/sh7377.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7ea2b31..86e72a0 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -60,6 +60,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
+#include <mach/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index 844507d..7ba1877 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -12,22 +12,8 @@
 
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#include <linux/sh_pfc.h>
 #include <linux/io.h>
 
-#ifdef CONFIG_GPIOLIB
-
-static inline int irq_to_gpio(unsigned int irq)
-{
-	return -ENOSYS;
-}
-
-#else
-
-#define __ARM_GPIOLIB_COMPLEX
-
-#endif /* CONFIG_GPIOLIB */
-
 /*
  * FIXME !!
  *
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index ce9e7fa..134d1b9 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -20,7 +20,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index d14c9b0..cbc26ba 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -19,7 +19,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <linux/ioport.h>
 #include <mach/r8a7779.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
index e6e5246..c0c137f 100644
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ b/arch/arm/mach-shmobile/pfc-sh7367.c
@@ -18,7 +18,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7367.h>
 
 #define CPU_ALL_PORT(fn, pfx, sfx)				\
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 336093f9..7a1525f 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -22,7 +22,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
index 2f10511..f3117f6 100644
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ b/arch/arm/mach-shmobile/pfc-sh7377.c
@@ -19,7 +19,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh7377.h>
 
 #define CPU_ALL_PORT(fn, pfx, sfx)				\
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 4a547b8..b442f9d 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -20,7 +20,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/sh_pfc.h>
 #include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
diff --git a/drivers/sh/pfc/gpio.c b/drivers/sh/pfc/gpio.c
index 62bca98..038fa07 100644
--- a/drivers/sh/pfc/gpio.c
+++ b/drivers/sh/pfc/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/sh_pfc.h>
 
 struct sh_pfc_chip {
 	struct sh_pfc		*pfc;
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:33 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:33 -0500
Subject: [PATCH 07/10] ARM: orion: add explict mach/gpio.h includes
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-8-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/mach-dove/irq.c                     |    1 +
 arch/arm/mach-dove/mpp.c                     |    1 +
 arch/arm/mach-kirkwood/irq.c                 |    1 +
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c |    1 +
 arch/arm/mach-mv78xx0/irq.c                  |    1 +
 arch/arm/mach-orion5x/d2net-setup.c          |    1 +
 arch/arm/mach-orion5x/dns323-setup.c         |    1 +
 arch/arm/mach-orion5x/irq.c                  |    1 +
 arch/arm/mach-orion5x/net2big-setup.c        |    1 +
 arch/arm/plat-orion/mpp.c                    |    1 +
 10 files changed, 10 insertions(+)

diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9bc97a5..6b30d76 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -18,6 +18,7 @@
 #include <asm/mach/irq.h>
 #include <mach/pm.h>
 #include <mach/bridge-regs.h>
+#include <mach/gpio.h>
 #include "common.h"
 
 static void pmu_irq_mask(struct irq_data *d)
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 7f70afc..f5851da 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/dove.h>
+#include <mach/gpio.h>
 #include "mpp.h"
 
 struct dove_mpp_grp {
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 720063f..5dadebd 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <mach/bridge-regs.h>
+#include <mach/gpio.h>
 #include <plat/irq.h>
 
 static int __initdata gpio0_irqs[4] = {
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index f742a66..8e5d470 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -18,6 +18,7 @@
 #include <linux/spi/spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/gpio.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index eff9a75..2b33bd7 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <mach/bridge-regs.h>
+#include <mach/gpio.h>
 #include <plat/irq.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index d75dcfa..39aecc8 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -26,6 +26,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
+#include <mach/gpio.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index d470864..b720804 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -33,6 +33,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <asm/system_info.h>
+#include <mach/gpio.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 17da709..bfdeab1 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <mach/bridge-regs.h>
+#include <mach/gpio.h>
 #include <plat/irq.h>
 
 static int __initdata gpio0_irqs[4] = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 0180c39..472e9c6 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/gpio.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 3b1e17b..c140c2f 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <plat/gpio.h>
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:34 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:34 -0500
Subject: [PATCH 08/10] ARM: omap2: add explict mach/gpio.h includes
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-9-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-omap2/board-zoom-display.c |    1 +
 arch/arm/mach-omap2/gpio.c               |    1 +
 arch/arm/mach-omap2/pm24xx.c             |    1 +
 arch/arm/mach-omap2/pm34xx.c             |    1 +
 drivers/gpio/gpio-omap.c                 |    2 +-
 5 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 28187f1..c1a27b8 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -17,6 +17,7 @@
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
+#include <plat/cpu.h>
 
 #define LCD_PANEL_RESET_GPIO_PROD	96
 #define LCD_PANEL_RESET_GPIO_PILOT	55
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d48..c090e9e 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -25,6 +25,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/gpio.h>
 
 #include "powerdomain.h"
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2edeffc..95f37e9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -39,6 +39,7 @@
 #include <plat/sram.h>
 #include <plat/dma.h>
 #include <plat/board.h>
+#include <plat/gpio.h>
 
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..6373400 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -40,6 +40,7 @@
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
+#include <plat/gpio.h>
 
 #include "common.h"
 #include "cm2xxx_3xxx.h"
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..06dceba 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
-#include <asm/gpio.h>
+#include <mach/gpio.h>
 #include <asm/mach/irq.h>
 
 #define OFF_MODE	1
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:35 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:35 -0500
Subject: [PATCH 09/10] ARM: omap1: add explict mach/gpio.h includes
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-10-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove implicit inclusion of mach/gpio.h, add explict
include of mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/board-ams-delta.c |    1 +
 arch/arm/mach-omap1/board-osk.c       |    1 +
 arch/arm/mach-omap1/gpio15xx.c        |    1 +
 arch/arm/mach-omap1/gpio16xx.c        |    1 +
 arch/arm/mach-omap1/gpio7xx.c         |    1 +
 arch/arm/mach-omap1/leds-h2p2-debug.c |    1 +
 arch/arm/mach-omap1/leds.c            |    1 +
 7 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c534698..ad80fd0 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -39,6 +39,7 @@
 #include <plat/mux.h>
 #include <plat/board.h>
 
+#include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
 #include <mach/camera.h>
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 8784705..5cbb780 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -48,6 +48,7 @@
 #include <plat/mux.h>
 #include <plat/tc.h>
 
+#include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index ebef15e..c54efb4 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <mach/gpio.h>
 
 #define OMAP1_MPUIO_VBASE		OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE		0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 2a48cd2..fd934bf 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <mach/gpio.h>
 
 #define OMAP1610_GPIO1_BASE		0xfffbe400
 #define OMAP1610_GPIO2_BASE		0xfffbec00
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index acf12b7..20d33c0 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <mach/gpio.h>
 
 #define OMAP7XX_GPIO1_BASE		0xfffbc000
 #define OMAP7XX_GPIO2_BASE		0xfffbc800
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index f6b14a1..c7e16db 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -15,6 +15,7 @@
 #include <linux/sched.h>
 #include <linux/io.h>
 
+#include <mach/gpio.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index ae6dd93..de155dc 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -10,6 +10,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
+#include <mach/gpio.h>
 #include <plat/mux.h>
 
 #include "leds.h"
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:31:36 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:31:36 -0500
Subject: [PATCH 10/10] ARM: make mach/gpio.h headers optional
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346279496-26286-11-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Most platforms don't need mach/gpio.h and it prevents multi-platform
kernel images. Add CONFIG_NEED_MACH_GPIO_H and make platforns select it
if they need gpio.h. This is platforms that define __GPIOLIB_COMPLEX
or have lots of implicit includes pulled in by mach/gpio.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                            |   17 ++++++++++++++
 arch/arm/include/asm/gpio.h                 |    2 ++
 arch/arm/mach-ep93xx/include/mach/gpio.h    |    1 -
 arch/arm/mach-highbank/include/mach/gpio.h  |    1 -
 arch/arm/mach-ixp4xx/include/mach/gpio.h    |    2 --
 arch/arm/mach-mmp/include/mach/gpio.h       |    8 -------
 arch/arm/mach-msm/include/mach/gpio.h       |    1 -
 arch/arm/mach-mxs/include/mach/gpio.h       |    1 -
 arch/arm/mach-nomadik/include/mach/gpio.h   |    4 ----
 arch/arm/mach-picoxcell/include/mach/gpio.h |    1 -
 arch/arm/mach-pxa/include/mach/gpio.h       |   32 ---------------------------
 arch/arm/mach-realview/include/mach/gpio.h  |    1 -
 arch/arm/mach-spear13xx/include/mach/gpio.h |   19 ----------------
 arch/arm/mach-spear3xx/include/mach/gpio.h  |   19 ----------------
 arch/arm/mach-spear6xx/include/mach/gpio.h  |   19 ----------------
 arch/arm/mach-tegra/include/mach/gpio.h     |    1 -
 arch/arm/mach-u300/include/mach/gpio.h      |    1 -
 arch/arm/mach-ux500/include/mach/gpio.h     |    5 -----
 arch/arm/mach-versatile/include/mach/gpio.h |    1 -
 arch/arm/mach-vexpress/include/mach/gpio.h  |    1 -
 arch/arm/mach-vt8500/include/mach/gpio.h    |    1 -
 arch/arm/plat-mxc/include/mach/gpio.h       |    1 -
 arch/arm/plat-spear/include/plat/gpio.h     |    1 -
 23 files changed, 19 insertions(+), 121 deletions(-)
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-highbank/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-msm/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-realview/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-u300/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-vexpress/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/gpio.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/gpio.h
 delete mode 100644 arch/arm/plat-spear/include/plat/gpio.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..3557f12 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -202,6 +202,13 @@ config ARM_PATCH_PHYS_VIRT
 	  this feature (eg, building a kernel for a single machine) and
 	  you need to shrink the kernel to the minimal size.
 
+config NEED_MACH_GPIO_H
+	bool
+	help
+	  Select this when mach/gpio.h is required to provide special
+	  definitions for this platform. The need for mach/gpio.h should
+	  be avoided when possible.
+
 config NEED_MACH_IO_H
 	bool
 	help
@@ -523,6 +530,7 @@ config ARCH_IOP32X
 	bool "IOP32x-based"
 	depends on MMU
 	select CPU_XSCALE
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_IO_H
 	select NEED_RET_TO_USER
 	select PLAT_IOP
@@ -536,6 +544,7 @@ config ARCH_IOP33X
 	bool "IOP33x-based"
 	depends on MMU
 	select CPU_XSCALE
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_IO_H
 	select NEED_RET_TO_USER
 	select PLAT_IOP
@@ -795,6 +804,7 @@ config ARCH_SA1100
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_IDE
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_MEMORY_H
 	select SPARSE_IRQ
 	help
@@ -810,6 +820,7 @@ config ARCH_S3C24XX
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_IO_H
 	help
 	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
@@ -837,6 +848,7 @@ config ARCH_S3C64XX
 	select SAMSUNG_GPIOLIB_4BIT
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
 	help
 	  Samsung S3C64XX series based systems
 
@@ -851,6 +863,7 @@ config ARCH_S5P64X0
 	select GENERIC_CLOCKEVENTS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C_RTC if RTC_CLASS
+	select NEED_MACH_GPIO_H
 	help
 	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 	  SMDK6450.
@@ -865,6 +878,7 @@ config ARCH_S5PC100
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
 	help
 	  Samsung S5PC100 series based systems
 
@@ -882,6 +896,7 @@ config ARCH_S5PV210
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Samsung S5PV210/S5PC110 series based systems
@@ -899,6 +914,7 @@ config ARCH_EXYNOS
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
@@ -971,6 +987,7 @@ config ARCH_DAVINCI
 	select GENERIC_ALLOCATOR
 	select GENERIC_IRQ_CHIP
 	select ARCH_HAS_HOLES_MEMORYMODEL
+	select NEED_MACH_GPIO_H
 	help
 	  Support for TI's DaVinci platform.
 
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index c402e9b..477e020 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -6,7 +6,9 @@
 #endif
 
 /* not all ARM platforms necessarily support this API ... */
+#ifdef CONFIG_NEED_MACH_GPIO_H
 #include <mach/gpio.h>
+#endif
 
 #ifndef __ARM_GPIOLIB_COMPLEX
 /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-ep93xx/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-highbank/include/mach/gpio.h b/arch/arm/mach-highbank/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-highbank/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
deleted file mode 100644
index ef37f26..0000000
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* empty */
-
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
deleted file mode 100644
index 13219eb..0000000
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_MACH_GPIO_H
-#define __ASM_MACH_GPIO_H
-
-#include <asm-generic/gpio.h>
-
-#include <mach/cputype.h>
-
-#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-mxs/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
deleted file mode 100644
index efdde0a..0000000
--- a/arch/arm/mach-nomadik/include/mach/gpio.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-picoxcell/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
deleted file mode 100644
index 0248e43..0000000
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/gpio.h
- *
- * PXA GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Philipp Zabel <philipp.zabel at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_PXA_GPIO_H
-#define __ASM_ARCH_PXA_GPIO_H
-
-#include <asm-generic/gpio.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#endif
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-realview/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h
deleted file mode 100644
index 85f1763..0000000
--- a/arch/arm/mach-spear13xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux at gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
deleted file mode 100644
index 2ac74c6..0000000
--- a/arch/arm/mach-spear3xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux at gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
deleted file mode 100644
index d42cefc..0000000
--- a/arch/arm/mach-spear6xx/include/mach/gpio.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/gpio.h
- *
- * GPIO macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux at gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GPIO_H
-#define __MACH_GPIO_H
-
-#include <plat/gpio.h>
-
-#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-tegra/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
deleted file mode 100644
index c01ef66..0000000
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-versatile/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vexpress/include/mach/gpio.h b/arch/arm/mach-vexpress/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-vexpress/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-vt8500/include/mach/gpio.h b/arch/arm/mach-vt8500/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/mach-vt8500/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
deleted file mode 100644
index 40a8c17..0000000
--- a/arch/arm/plat-spear/include/plat/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:54 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:54 -0500
Subject: [PATCH 0/6] Initial multi-platform support
Message-ID: <1346280600-29395-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This series enables initial multi-platform support for highbank, mvebu,
socfpga, picoxcell, and vexpress.

There's a couple of issues which I'm aware of:

- DEBUG_LL does not work (even for 1 platform).
- make dtbs does not work. It needs to be changes such that the build
  will iterate over mach-dirs instead of using MACHINE

This series is dependent on gpio.h clean-up and is available here:

git://sources.calxeda.com/kernel/linux.git multi-plat

Rob

Arnd Bergmann (1):
  ARM: vexpress: remove dependency on mach/* headers

Rob Herring (5):
  ARM: move ARCH config definitions into mach dirs
  ARM: introduce Kconfig.mach
  ARM: picoxcell: header fixes for multi-platform
  ARM: initial multiplatform support
  ARM: update defconfigs

 arch/arm/Kconfig                                   |  923 +-------------------
 arch/arm/Kconfig.mach                              |  585 +++++++++++++
 arch/arm/Makefile                                  |  155 ++--
 arch/arm/boot/compressed/misc.c                    |    6 +
 arch/arm/configs/acs5k_defconfig                   |    2 +-
 arch/arm/configs/acs5k_tiny_defconfig              |    2 +-
 arch/arm/configs/afeb9260_defconfig                |    2 +-
 arch/arm/configs/ag5evm_defconfig                  |    2 +-
 arch/arm/configs/am200epdkit_defconfig             |    2 +-
 arch/arm/configs/ap4evb_defconfig                  |    2 +-
 arch/arm/configs/armadillo800eva_defconfig         |    2 +-
 arch/arm/configs/assabet_defconfig                 |    2 +-
 arch/arm/configs/at91_dt_defconfig                 |    2 +-
 arch/arm/configs/at91rm9200_defconfig              |    2 +-
 arch/arm/configs/at91sam9260_defconfig             |    2 +-
 arch/arm/configs/at91sam9261_defconfig             |    2 +-
 arch/arm/configs/at91sam9263_defconfig             |    2 +-
 arch/arm/configs/at91sam9g20_defconfig             |    2 +-
 arch/arm/configs/at91sam9g45_defconfig             |    2 +-
 arch/arm/configs/at91sam9rl_defconfig              |    2 +-
 arch/arm/configs/at91x40_defconfig                 |    2 +-
 arch/arm/configs/badge4_defconfig                  |    2 +-
 arch/arm/configs/bcmring_defconfig                 |    2 +-
 arch/arm/configs/bonito_defconfig                  |    2 +-
 arch/arm/configs/cam60_defconfig                   |    2 +-
 arch/arm/configs/cerfcube_defconfig                |    2 +-
 arch/arm/configs/cm_x2xx_defconfig                 |    2 +-
 arch/arm/configs/cm_x300_defconfig                 |    2 +-
 arch/arm/configs/cns3420vb_defconfig               |    2 +-
 arch/arm/configs/colibri_pxa270_defconfig          |    2 +-
 arch/arm/configs/colibri_pxa300_defconfig          |    2 +-
 arch/arm/configs/collie_defconfig                  |    2 +-
 arch/arm/configs/corgi_defconfig                   |    2 +-
 arch/arm/configs/cpu9260_defconfig                 |    2 +-
 arch/arm/configs/cpu9g20_defconfig                 |    2 +-
 arch/arm/configs/da8xx_omapl_defconfig             |    2 +-
 arch/arm/configs/davinci_all_defconfig             |    2 +-
 arch/arm/configs/dove_defconfig                    |    2 +-
 arch/arm/configs/ebsa110_defconfig                 |    2 +-
 arch/arm/configs/edb7211_defconfig                 |    2 +-
 arch/arm/configs/em_x270_defconfig                 |    2 +-
 arch/arm/configs/ep93xx_defconfig                  |    2 +-
 arch/arm/configs/eseries_pxa_defconfig             |    2 +-
 arch/arm/configs/exynos4_defconfig                 |    2 +-
 arch/arm/configs/exynos_defconfig                  |    4 +-
 arch/arm/configs/ezx_defconfig                     |    2 +-
 arch/arm/configs/footbridge_defconfig              |    2 +-
 arch/arm/configs/fortunet_defconfig                |    2 +-
 arch/arm/configs/g3evm_defconfig                   |    2 +-
 arch/arm/configs/g4evm_defconfig                   |    2 +-
 arch/arm/configs/h3600_defconfig                   |    2 +-
 arch/arm/configs/h5000_defconfig                   |    2 +-
 arch/arm/configs/h7201_defconfig                   |    2 +-
 arch/arm/configs/h7202_defconfig                   |    2 +-
 arch/arm/configs/hackkit_defconfig                 |    2 +-
 arch/arm/configs/imote2_defconfig                  |    2 +-
 arch/arm/configs/imx_v4_v5_defconfig               |    2 +-
 arch/arm/configs/imx_v6_v7_defconfig               |    2 +-
 arch/arm/configs/integrator_defconfig              |    2 +-
 arch/arm/configs/iop13xx_defconfig                 |    2 +-
 arch/arm/configs/iop32x_defconfig                  |    2 +-
 arch/arm/configs/iop33x_defconfig                  |    2 +-
 arch/arm/configs/ixp4xx_defconfig                  |    2 +-
 arch/arm/configs/jornada720_defconfig              |    2 +-
 arch/arm/configs/kirkwood_defconfig                |    2 +-
 arch/arm/configs/kota2_defconfig                   |    2 +-
 arch/arm/configs/ks8695_defconfig                  |    2 +-
 arch/arm/configs/kzm9d_defconfig                   |    2 +-
 arch/arm/configs/kzm9g_defconfig                   |    2 +-
 arch/arm/configs/lart_defconfig                    |    2 +-
 arch/arm/configs/lpc32xx_defconfig                 |    2 +-
 arch/arm/configs/lpd270_defconfig                  |    2 +-
 arch/arm/configs/lubbock_defconfig                 |    2 +-
 arch/arm/configs/mackerel_defconfig                |    2 +-
 arch/arm/configs/magician_defconfig                |    2 +-
 arch/arm/configs/mainstone_defconfig               |    2 +-
 arch/arm/configs/marzen_defconfig                  |    2 +-
 arch/arm/configs/mini2440_defconfig                |    2 +-
 arch/arm/configs/mmp2_defconfig                    |    2 +-
 arch/arm/configs/msm_defconfig                     |    2 +-
 arch/arm/configs/mv78xx0_defconfig                 |    2 +-
 arch/arm/configs/mvebu_defconfig                   |    2 +-
 arch/arm/configs/mxs_defconfig                     |    2 +-
 arch/arm/configs/neponset_defconfig                |    2 +-
 arch/arm/configs/netwinder_defconfig               |    2 +-
 arch/arm/configs/netx_defconfig                    |    2 +-
 arch/arm/configs/nhk8815_defconfig                 |    2 +-
 arch/arm/configs/nuc910_defconfig                  |    2 +-
 arch/arm/configs/nuc950_defconfig                  |    2 +-
 arch/arm/configs/nuc960_defconfig                  |    2 +-
 arch/arm/configs/omap1_defconfig                   |    2 +-
 arch/arm/configs/omap2plus_defconfig               |    2 +-
 arch/arm/configs/orion5x_defconfig                 |    2 +-
 arch/arm/configs/palmz72_defconfig                 |    2 +-
 arch/arm/configs/pcm027_defconfig                  |    2 +-
 arch/arm/configs/pleb_defconfig                    |    2 +-
 arch/arm/configs/pnx4008_defconfig                 |    2 +-
 arch/arm/configs/prima2_defconfig                  |    2 +-
 arch/arm/configs/pxa168_defconfig                  |    2 +-
 arch/arm/configs/pxa255-idp_defconfig              |    2 +-
 arch/arm/configs/pxa3xx_defconfig                  |    2 +-
 arch/arm/configs/pxa910_defconfig                  |    2 +-
 arch/arm/configs/qil-a9260_defconfig               |    2 +-
 arch/arm/configs/raumfeld_defconfig                |    2 +-
 arch/arm/configs/realview-smp_defconfig            |    2 +-
 arch/arm/configs/realview_defconfig                |    2 +-
 arch/arm/configs/rpc_defconfig                     |    2 +-
 arch/arm/configs/s3c2410_defconfig                 |    2 +-
 arch/arm/configs/s3c6400_defconfig                 |    2 +-
 arch/arm/configs/s5p64x0_defconfig                 |    2 +-
 arch/arm/configs/s5pc100_defconfig                 |    2 +-
 arch/arm/configs/s5pv210_defconfig                 |    2 +-
 arch/arm/configs/sam9_l9260_defconfig              |    2 +-
 arch/arm/configs/shannon_defconfig                 |    2 +-
 arch/arm/configs/shark_defconfig                   |    2 +-
 arch/arm/configs/simpad_defconfig                  |    2 +-
 arch/arm/configs/socfpga_defconfig                 |    2 +-
 arch/arm/configs/spear13xx_defconfig               |    2 +-
 arch/arm/configs/spear6xx_defconfig                |    2 +-
 arch/arm/configs/spitz_defconfig                   |    2 +-
 arch/arm/configs/stamp9g20_defconfig               |    2 +-
 arch/arm/configs/tct_hammer_defconfig              |    2 +-
 arch/arm/configs/tegra_defconfig                   |    2 +-
 arch/arm/configs/trizeps4_defconfig                |    2 +-
 arch/arm/configs/u300_defconfig                    |    2 +-
 arch/arm/configs/u8500_defconfig                   |    2 +-
 arch/arm/configs/usb-a9260_defconfig               |    2 +-
 arch/arm/configs/vexpress_defconfig                |    2 +-
 arch/arm/configs/viper_defconfig                   |    2 +-
 arch/arm/configs/xcep_defconfig                    |    2 +-
 arch/arm/configs/zeus_defconfig                    |    2 +-
 arch/arm/include/asm/timex.h                       |    4 +
 arch/arm/mach-at91/Kconfig                         |    8 +
 arch/arm/mach-bcmring/Kconfig                      |    9 +
 arch/arm/mach-clps711x/Kconfig                     |    6 +
 arch/arm/mach-cns3xxx/Kconfig                      |    9 +
 arch/arm/mach-davinci/Kconfig                      |   12 +
 arch/arm/mach-dove/Kconfig                         |    9 +
 arch/arm/mach-ebsa110/Kconfig                      |    9 +
 arch/arm/mach-ep93xx/Kconfig                       |   11 +
 arch/arm/mach-exynos/Kconfig                       |   16 +
 arch/arm/mach-footbridge/Kconfig                   |    9 +
 arch/arm/mach-gemini/Kconfig                       |    6 +
 arch/arm/mach-h720x/Kconfig                        |    6 +
 arch/arm/mach-highbank/Kconfig                     |   15 +
 arch/arm/mach-integrator/Kconfig                   |   16 +
 arch/arm/mach-iop13xx/Kconfig                      |   11 +
 arch/arm/mach-iop32x/Kconfig                       |   10 +
 arch/arm/mach-iop33x/Kconfig                       |   10 +
 arch/arm/mach-ixp4xx/Kconfig                       |   11 +
 arch/arm/mach-kirkwood/Kconfig                     |    9 +
 arch/arm/mach-ks8695/Kconfig                       |    7 +
 arch/arm/mach-lpc32xx/Kconfig                      |   12 +
 arch/arm/mach-mmp/Kconfig                          |   12 +
 arch/arm/mach-msm/Kconfig                          |    7 +
 arch/arm/mach-mv78xx0/Kconfig                      |    9 +
 arch/arm/mach-mvebu/Kconfig                        |   10 +
 arch/arm/mach-mvebu/Makefile                       |    2 +
 arch/arm/mach-mxs/Kconfig                          |   11 +
 arch/arm/mach-netx/Kconfig                         |    7 +
 arch/arm/mach-nomadik/Kconfig                      |   11 +
 arch/arm/mach-orion5x/Kconfig                      |    9 +
 arch/arm/mach-picoxcell/Kconfig                    |   14 +
 arch/arm/mach-picoxcell/common.c                   |    6 +-
 arch/arm/mach-picoxcell/include/mach/map.h         |   25 -
 .../mach-picoxcell/include/mach/picoxcell_soc.h    |   25 -
 arch/arm/mach-picoxcell/picoxcell_soc.h            |   25 +
 arch/arm/mach-pnx4008/Kconfig                      |    5 +
 arch/arm/mach-pxa/Kconfig                          |   16 +
 arch/arm/mach-realview/Kconfig                     |   15 +
 arch/arm/mach-rpc/Kconfig                          |   13 +
 arch/arm/mach-s3c24xx/Kconfig                      |   13 +
 arch/arm/mach-s3c64xx/Kconfig                      |   26 +
 arch/arm/mach-s5p64x0/Kconfig                      |   13 +
 arch/arm/mach-s5pc100/Kconfig                      |   12 +
 arch/arm/mach-s5pv210/Kconfig                      |   17 +
 arch/arm/mach-sa1100/Kconfig                       |   17 +
 arch/arm/mach-shark/Kconfig                        |   11 +
 arch/arm/mach-shmobile/Kconfig                     |   14 +
 arch/arm/mach-socfpga/Kconfig                      |   16 +
 arch/arm/mach-tegra/Kconfig                        |   13 +
 arch/arm/mach-u300/Kconfig                         |   14 +
 arch/arm/mach-ux500/Kconfig                        |   11 +
 arch/arm/mach-versatile/Kconfig                    |   16 +
 arch/arm/mach-vexpress/Kconfig                     |   16 +
 arch/arm/mach-vexpress/Makefile                    |    2 +
 arch/arm/mach-vexpress/ct-ca9x4.c                  |    1 +
 arch/arm/mach-vexpress/include/mach/irqs.h         |    2 +
 arch/arm/mach-vt8500/Kconfig                       |    8 +
 arch/arm/mach-w90x900/Kconfig                      |    8 +
 arch/arm/mach-zynq/Kconfig                         |   10 +
 arch/arm/plat-mxc/Kconfig                          |   11 +
 arch/arm/plat-omap/Kconfig                         |    9 +
 arch/arm/plat-spear/Kconfig                        |    9 +
 arch/arm/plat-versatile/Makefile                   |    2 +
 195 files changed, 1455 insertions(+), 1178 deletions(-)
 create mode 100644 arch/arm/Kconfig.mach
 create mode 100644 arch/arm/mach-ebsa110/Kconfig
 create mode 100644 arch/arm/mach-highbank/Kconfig
 create mode 100644 arch/arm/mach-lpc32xx/Kconfig
 create mode 100644 arch/arm/mach-picoxcell/Kconfig
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/map.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
 create mode 100644 arch/arm/mach-picoxcell/picoxcell_soc.h
 create mode 100644 arch/arm/mach-pnx4008/Kconfig
 create mode 100644 arch/arm/mach-rpc/Kconfig
 create mode 100644 arch/arm/mach-shark/Kconfig
 create mode 100644 arch/arm/mach-socfpga/Kconfig
 create mode 100644 arch/arm/mach-zynq/Kconfig

-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:55 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:55 -0500
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation for mulit-platform support, convert all platforms' ARCH_
definition to a hidden option and create a new choice option.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                 |  650 ++++++++------------------------------
 arch/arm/mach-at91/Kconfig       |    8 +
 arch/arm/mach-bcmring/Kconfig    |    9 +
 arch/arm/mach-clps711x/Kconfig   |    6 +
 arch/arm/mach-cns3xxx/Kconfig    |    9 +
 arch/arm/mach-davinci/Kconfig    |   12 +
 arch/arm/mach-dove/Kconfig       |    9 +
 arch/arm/mach-ebsa110/Kconfig    |    9 +
 arch/arm/mach-ep93xx/Kconfig     |   11 +
 arch/arm/mach-exynos/Kconfig     |   16 +
 arch/arm/mach-footbridge/Kconfig |    9 +
 arch/arm/mach-gemini/Kconfig     |    6 +
 arch/arm/mach-h720x/Kconfig      |    6 +
 arch/arm/mach-highbank/Kconfig   |   15 +
 arch/arm/mach-integrator/Kconfig |   16 +
 arch/arm/mach-iop13xx/Kconfig    |   11 +
 arch/arm/mach-iop32x/Kconfig     |   10 +
 arch/arm/mach-iop33x/Kconfig     |   10 +
 arch/arm/mach-ixp4xx/Kconfig     |   11 +
 arch/arm/mach-kirkwood/Kconfig   |    9 +
 arch/arm/mach-ks8695/Kconfig     |    7 +
 arch/arm/mach-lpc32xx/Kconfig    |   12 +
 arch/arm/mach-mmp/Kconfig        |   12 +
 arch/arm/mach-msm/Kconfig        |    7 +
 arch/arm/mach-mv78xx0/Kconfig    |    9 +
 arch/arm/mach-mvebu/Kconfig      |   10 +
 arch/arm/mach-mxs/Kconfig        |   11 +
 arch/arm/mach-netx/Kconfig       |    7 +
 arch/arm/mach-nomadik/Kconfig    |   11 +
 arch/arm/mach-orion5x/Kconfig    |    9 +
 arch/arm/mach-picoxcell/Kconfig  |   14 +
 arch/arm/mach-pnx4008/Kconfig    |    5 +
 arch/arm/mach-pxa/Kconfig        |   16 +
 arch/arm/mach-realview/Kconfig   |   15 +
 arch/arm/mach-rpc/Kconfig        |   13 +
 arch/arm/mach-s3c24xx/Kconfig    |   13 +
 arch/arm/mach-s3c64xx/Kconfig    |   26 ++
 arch/arm/mach-s5p64x0/Kconfig    |   13 +
 arch/arm/mach-s5pc100/Kconfig    |   12 +
 arch/arm/mach-s5pv210/Kconfig    |   17 +
 arch/arm/mach-sa1100/Kconfig     |   17 +
 arch/arm/mach-shark/Kconfig      |   11 +
 arch/arm/mach-shmobile/Kconfig   |   14 +
 arch/arm/mach-socfpga/Kconfig    |   16 +
 arch/arm/mach-tegra/Kconfig      |   13 +
 arch/arm/mach-u300/Kconfig       |   14 +
 arch/arm/mach-ux500/Kconfig      |   11 +
 arch/arm/mach-versatile/Kconfig  |   16 +
 arch/arm/mach-vexpress/Kconfig   |   16 +
 arch/arm/mach-vt8500/Kconfig     |    8 +
 arch/arm/mach-w90x900/Kconfig    |    8 +
 arch/arm/mach-zynq/Kconfig       |   10 +
 arch/arm/plat-mxc/Kconfig        |   11 +
 arch/arm/plat-omap/Kconfig       |    9 +
 arch/arm/plat-spear/Kconfig      |    9 +
 55 files changed, 742 insertions(+), 522 deletions(-)
 create mode 100644 arch/arm/mach-ebsa110/Kconfig
 create mode 100644 arch/arm/mach-highbank/Kconfig
 create mode 100644 arch/arm/mach-lpc32xx/Kconfig
 create mode 100644 arch/arm/mach-picoxcell/Kconfig
 create mode 100644 arch/arm/mach-pnx4008/Kconfig
 create mode 100644 arch/arm/mach-rpc/Kconfig
 create mode 100644 arch/arm/mach-shark/Kconfig
 create mode 100644 arch/arm/mach-socfpga/Kconfig
 create mode 100644 arch/arm/mach-zynq/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3557f12..3ad82c6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -256,424 +256,213 @@ choice
 	prompt "ARM system type"
 	default ARCH_VERSATILE
 
-config ARCH_SOCFPGA
+config ARCH_SOCFPGA_CHOICE
 	bool "Altera SOCFPGA family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CPU_V7
-	select DW_APB_TIMER
-	select DW_APB_TIMER_OF
-	select GENERIC_CLOCKEVENTS
-	select GPIO_PL061 if GPIOLIB
-	select HAVE_ARM_SCU
-	select SPARSE_IRQ
-	select USE_OF
+	select ARCH_SOCFPGA
 	help
 	  This enables support for Altera SOCFPGA Cyclone V platform
 
-config ARCH_INTEGRATOR
+config ARCH_INTEGRATOR_CHOICE
 	bool "ARM Ltd. Integrator family"
-	select ARM_AMBA
-	select ARCH_HAS_CPUFREQ
-	select COMMON_CLK
-	select CLK_VERSATILE
-	select HAVE_TCM
-	select ICST
-	select GENERIC_CLOCKEVENTS
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_FPGA_IRQ
-	select NEED_MACH_IO_H
-	select NEED_MACH_MEMORY_H
-	select SPARSE_IRQ
-	select MULTI_IRQ_HANDLER
+	select ARCH_INTEGRATOR
 	help
 	  Support for ARM's Integrator platform.
 
-config ARCH_REALVIEW
+config ARCH_REALVIEW_CHOICE
 	bool "ARM Ltd. RealView family"
-	select ARM_AMBA
-	select CLKDEV_LOOKUP
-	select HAVE_MACH_CLKDEV
-	select ICST
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLOCK
-	select PLAT_VERSATILE_CLCD
-	select ARM_TIMER_SP804
-	select GPIO_PL061 if GPIOLIB
-	select NEED_MACH_MEMORY_H
+	select ARCH_REALVIEW
 	help
 	  This enables support for ARM Ltd RealView boards.
 
-config ARCH_VERSATILE
+config ARCH_VERSATILE_CHOICE
 	bool "ARM Ltd. Versatile family"
-	select ARM_AMBA
-	select ARM_VIC
-	select CLKDEV_LOOKUP
-	select HAVE_MACH_CLKDEV
-	select ICST
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select NEED_MACH_IO_H if PCI
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLOCK
-	select PLAT_VERSATILE_CLCD
-	select PLAT_VERSATILE_FPGA_IRQ
-	select ARM_TIMER_SP804
+	select ARCH_VERSATILE
 	help
 	  This enables support for ARM Ltd Versatile board.
 
-config ARCH_VEXPRESS
+config ARCH_VEXPRESS_CHOICE
 	bool "ARM Ltd. Versatile Express family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select GENERIC_CLOCKEVENTS
-	select HAVE_CLK
-	select HAVE_PATA_PLATFORM
-	select ICST
-	select NO_IOPORT
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLCD
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select ARCH_VEXPRESS
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
 
-config ARCH_AT91
+config ARCH_AT91_CHOICE
 	bool "Atmel AT91"
-	select ARCH_REQUIRE_GPIOLIB
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select IRQ_DOMAIN
-	select NEED_MACH_IO_H if PCCARD
+	select ARCH_AT91
 	help
 	  This enables support for systems based on Atmel
 	  AT91RM9200 and AT91SAM9* processors.
 
-config ARCH_BCMRING
+config ARCH_BCMRING_CHOICE
 	bool "Broadcom BCMRING"
 	depends on MMU
-	select CPU_V6
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
-config ARCH_HIGHBANK
+config ARCH_HIGHBANK_CHOICE
 	bool "Calxeda Highbank-based"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select ARM_TIMER_SP804
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select HAVE_ARM_SCU
-	select HAVE_SMP
-	select SPARSE_IRQ
-	select USE_OF
+	select ARCH_HIGHBANK
 	help
 	  Support for the Calxeda Highbank SoC based boards.
 
-config ARCH_CLPS711X
+config ARCH_CLPS711X_CHOICE
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
-	select CPU_ARM720T
-	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_MEMORY_H
+	select ARCH_CLPS711X
 	help
 	  Support for Cirrus Logic 711x/721x/731x based boards.
 
-config ARCH_CNS3XXX
+config ARCH_CNS3XXX_CHOICE
 	bool "Cavium Networks CNS3XXX family"
-	select CPU_V6K
-	select GENERIC_CLOCKEVENTS
-	select ARM_GIC
-	select MIGHT_HAVE_CACHE_L2X0
-	select MIGHT_HAVE_PCI
-	select PCI_DOMAINS if PCI
+	select ARCH_CNS3XXX
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 
-config ARCH_GEMINI
+config ARCH_GEMINI_CHOICE
 	bool "Cortina Systems Gemini"
-	select CPU_FA526
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_GEMINI
 	help
 	  Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_PRIMA2
+config ARCH_PRIMA2_CHOICE
 	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-	select CPU_V7
-	select NO_IOPORT
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select GENERIC_IRQ_CHIP
-	select MIGHT_HAVE_CACHE_L2X0
-	select PINCTRL
-	select PINCTRL_SIRF
-	select USE_OF
-	select ZONE_DMA
+	select ARCH_PRIMA2
 	help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
-config ARCH_EBSA110
+config ARCH_EBSA110_CHOICE
 	bool "EBSA-110"
-	select CPU_SA110
-	select ISA
-	select NO_IOPORT
-	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_IO_H
-	select NEED_MACH_MEMORY_H
+	select ARCH_EBSA110
 	help
 	  This is an evaluation board for the StrongARM processor available
 	  from Digital. It has limited hardware on-board, including an
 	  Ethernet interface, two PCMCIA sockets, two serial ports and a
 	  parallel port.
 
-config ARCH_EP93XX
+config ARCH_EP93XX_CHOICE
 	bool "EP93xx-based"
-	select CPU_ARM920T
-	select ARM_AMBA
-	select ARM_VIC
-	select CLKDEV_LOOKUP
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_MEMORY_H
+	select ARCH_EP93XX
 	help
 	  This enables support for the Cirrus EP93xx series of CPUs.
 
-config ARCH_FOOTBRIDGE
+config ARCH_FOOTBRIDGE_CHOICE
 	bool "FootBridge"
-	select CPU_SA110
-	select FOOTBRIDGE
-	select GENERIC_CLOCKEVENTS
-	select HAVE_IDE
-	select NEED_MACH_IO_H
-	select NEED_MACH_MEMORY_H
+	select ARCH_FOOTBRIDGE
 	help
 	  Support for systems based on the DC21285 companion chip
 	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 
-config ARCH_MXC
+config ARCH_MXC_CHOICE
 	bool "Freescale MXC/iMX-based"
-	select GENERIC_CLOCKEVENTS
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select GENERIC_IRQ_CHIP
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
-	select USE_OF
+	select ARCH_MXC
 	help
 	  Support for Freescale MXC/iMX-based family of processors
 
-config ARCH_MXS
+config ARCH_MXS_CHOICE
 	bool "Freescale MXS-based"
-	select GENERIC_CLOCKEVENTS
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select COMMON_CLK
-	select HAVE_CLK_PREPARE
-	select PINCTRL
-	select USE_OF
+	select ARCH_MXS
 	help
 	  Support for Freescale MXS-based family of processors
 
-config ARCH_NETX
+config ARCH_NETX_CHOICE
 	bool "Hilscher NetX based"
-	select CLKSRC_MMIO
-	select CPU_ARM926T
-	select ARM_VIC
-	select GENERIC_CLOCKEVENTS
+	select ARCH_NETX
 	help
 	  This enables support for systems based on the Hilscher NetX Soc
 
-config ARCH_H720X
+config ARCH_H720X_CHOICE
 	bool "Hynix HMS720x-based"
-	select CPU_ARM720T
-	select ISA_DMA_API
-	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_H720X
 	help
 	  This enables support for systems based on the Hynix HMS720x
 
-config ARCH_IOP13XX
+config ARCH_IOP13XX_CHOICE
 	bool "IOP13xx-based"
 	depends on MMU
-	select CPU_XSC3
-	select PLAT_IOP
-	select PCI
-	select ARCH_SUPPORTS_MSI
-	select VMSPLIT_1G
-	select NEED_MACH_IO_H
-	select NEED_MACH_MEMORY_H
-	select NEED_RET_TO_USER
+	select ARCH_IOP13XX
 	help
 	  Support for Intel's IOP13XX (XScale) family of processors.
 
-config ARCH_IOP32X
+config ARCH_IOP32X_CHOICE
 	bool "IOP32x-based"
 	depends on MMU
-	select CPU_XSCALE
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_IO_H
-	select NEED_RET_TO_USER
-	select PLAT_IOP
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_IOP32X
 	help
 	  Support for Intel's 80219 and IOP32X (XScale) family of
 	  processors.
 
-config ARCH_IOP33X
+config ARCH_IOP33X_CHOICE
 	bool "IOP33x-based"
 	depends on MMU
-	select CPU_XSCALE
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_IO_H
-	select NEED_RET_TO_USER
-	select PLAT_IOP
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_IOP33X
 	help
 	  Support for Intel's IOP33X (XScale) family of processors.
 
-config ARCH_IXP4XX
+config ARCH_IXP4XX_CHOICE
 	bool "IXP4xx-based"
 	depends on MMU
-	select ARCH_HAS_DMA_SET_COHERENT_MASK
-	select CLKSRC_MMIO
-	select CPU_XSCALE
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select MIGHT_HAVE_PCI
-	select NEED_MACH_IO_H
-	select DMABOUNCE if PCI
+	select ARCH_IXP4XX
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_MVEBU
+config ARCH_MVEBU_CHOICE
 	bool "Marvell SOCs with Device Tree support"
-	select GENERIC_CLOCKEVENTS
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
-	select CLKSRC_MMIO
-	select GENERIC_IRQ_CHIP
-	select IRQ_DOMAIN
-	select COMMON_CLK
+	select ARCH_MVEBU
 	help
 	  Support for the Marvell SoC Family with device tree support
 
-config ARCH_DOVE
+config ARCH_DOVE_CHOICE
 	bool "Marvell Dove"
-	select CPU_V7
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select ARCH_DOVE
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
-config ARCH_KIRKWOOD
+config ARCH_KIRKWOOD_CHOICE
 	bool "Marvell Kirkwood"
-	select CPU_FEROCEON
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select ARCH_KIRKWOOD
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.
 
-config ARCH_LPC32XX
+config ARCH_LPC32XX_CHOICE
 	bool "NXP LPC32XX"
-	select CLKSRC_MMIO
-	select CPU_ARM926T
-	select ARCH_REQUIRE_GPIOLIB
-	select HAVE_IDE
-	select ARM_AMBA
-	select USB_ARCH_HAS_OHCI
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select USE_OF
-	select HAVE_PWM
+	select ARCH_LPC32XX
 	help
 	  Support for the NXP LPC32XX family of processors
 
-config ARCH_MV78XX0
+config ARCH_MV78XX0_CHOICE
 	bool "Marvell MV78xx0"
-	select CPU_FEROCEON
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select ARCH_MV78XX0
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.
 
-config ARCH_ORION5X
+config ARCH_ORION5X_CHOICE
 	bool "Marvell Orion"
 	depends on MMU
-	select CPU_FEROCEON
-	select PCI
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select ARCH_ORION5X
 	help
 	  Support for the following Marvell Orion 5x series SoCs:
 	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 	  Orion-2 (5281), Orion-1-90 (6183).
 
-config ARCH_MMP
+config ARCH_MMP_CHOICE
 	bool "Marvell PXA168/910/MMP2"
 	depends on MMU
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select GPIO_PXA
-	select IRQ_DOMAIN
-	select PLAT_PXA
-	select SPARSE_IRQ
-	select GENERIC_ALLOCATOR
+	select ARCH_MMP
 	help
 	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
-config ARCH_KS8695
+config ARCH_KS8695_CHOICE
 	bool "Micrel/Kendin KS8695"
-	select CPU_ARM922T
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_MEMORY_H
+	select ARCH_KS8695
 	help
 	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 	  System-on-Chip devices.
 
-config ARCH_W90X900
+config ARCH_W90X900_CHOICE
 	bool "Nuvoton W90X900 CPU"
-	select CPU_ARM926T
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select GENERIC_CLOCKEVENTS
+	select ARCH_W90X900
 	help
 	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 	  At present, the w90x900 has been renamed nuc900, regarding
@@ -683,74 +472,37 @@ config ARCH_W90X900
 	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 
-config ARCH_TEGRA
+config ARCH_TEGRA_CHOICE
 	bool "NVIDIA Tegra"
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select GENERIC_CLOCKEVENTS
-	select GENERIC_GPIO
-	select HAVE_CLK
-	select HAVE_SMP
-	select MIGHT_HAVE_CACHE_L2X0
-	select NEED_MACH_IO_H if PCI
-	select ARCH_HAS_CPUFREQ
-	select USE_OF
+	select ARCH_TEGRA
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
 	  Tegra 6xx and Tegra 2 series).
 
-config ARCH_PICOXCELL
+config ARCH_PICOXCELL_CHOICE
 	bool "Picochip picoXcell"
-	select ARCH_REQUIRE_GPIOLIB
-	select ARM_PATCH_PHYS_VIRT
-	select ARM_VIC
-	select CPU_V6K
-	select DW_APB_TIMER
-	select DW_APB_TIMER_OF
-	select GENERIC_CLOCKEVENTS
-	select GENERIC_GPIO
-	select HAVE_TCM
-	select NO_IOPORT
-	select SPARSE_IRQ
-	select USE_OF
+	select ARCH_PICOXCELL
 	help
 	  This enables support for systems based on the Picochip picoXcell
 	  family of Femtocell devices.  The picoxcell support requires device tree
 	  for all boards.
 
-config ARCH_PNX4008
+config ARCH_PNX4008_CHOICE
 	bool "Philips Nexperia PNX4008 Mobile"
-	select CPU_ARM926T
-	select CLKDEV_LOOKUP
-	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_PNX4008
 	help
 	  This enables support for Philips PNX4008 mobile platform.
 
-config ARCH_PXA
+config ARCH_PXA_CHOICE
 	bool "PXA2xx/PXA3xx-based"
 	depends on MMU
-	select ARCH_MTD_XIP
-	select ARCH_HAS_CPUFREQ
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select ARCH_REQUIRE_GPIOLIB
-	select GENERIC_CLOCKEVENTS
-	select GPIO_PXA
-	select PLAT_PXA
-	select SPARSE_IRQ
-	select AUTO_ZRELADDR
-	select MULTI_IRQ_HANDLER
-	select ARM_CPU_SUSPEND if PM
-	select HAVE_IDE
+	select ARCH_PXA
 	help
 	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
-config ARCH_MSM
+config ARCH_MSM_CHOICE
 	bool "Qualcomm MSM"
-	select HAVE_CLK
-	select GENERIC_CLOCKEVENTS
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
+	select ARCH_MSM
 	help
 	  Support for Qualcomm MSM/QSD based systems.  This runs on the
 	  apps processor of the MSM/QSD and depends on a shared memory
@@ -758,283 +510,121 @@ config ARCH_MSM
 	  stack and controls some vital subsystems
 	  (clock and power control, etc).
 
-config ARCH_SHMOBILE
+config ARCH_SHMOBILE_CHOICE
 	bool "Renesas SH-Mobile / R-Mobile"
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select HAVE_MACH_CLKDEV
-	select HAVE_SMP
-	select GENERIC_CLOCKEVENTS
-	select MIGHT_HAVE_CACHE_L2X0
-	select NO_IOPORT
-	select SPARSE_IRQ
-	select MULTI_IRQ_HANDLER
-	select PM_GENERIC_DOMAINS if PM
-	select NEED_MACH_MEMORY_H
+	select ARCH_SHMOBILE
 	help
 	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 
-config ARCH_RPC
+config ARCH_RPC_CHOICE
 	bool "RiscPC"
-	select ARCH_ACORN
-	select FIQ
-	select ARCH_MAY_HAVE_PC_FDC
-	select HAVE_PATA_PLATFORM
-	select ISA_DMA_API
-	select NO_IOPORT
-	select ARCH_SPARSEMEM_ENABLE
-	select ARCH_USES_GETTIMEOFFSET
-	select HAVE_IDE
-	select NEED_MACH_IO_H
-	select NEED_MACH_MEMORY_H
+	select ARCH_RPC
 	help
 	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
 	  CD-ROM interface, serial and parallel port, and the floppy drive.
 
-config ARCH_SA1100
+config ARCH_SA1100_CHOICE
 	bool "SA1100-based"
-	select CLKSRC_MMIO
-	select CPU_SA1100
-	select ISA
-	select ARCH_SPARSEMEM_ENABLE
-	select ARCH_MTD_XIP
-	select ARCH_HAS_CPUFREQ
-	select CPU_FREQ
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select ARCH_REQUIRE_GPIOLIB
-	select HAVE_IDE
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_MEMORY_H
-	select SPARSE_IRQ
+	select ARCH_SA1100
 	help
 	  Support for StrongARM 11x0 based boards.
 
-config ARCH_S3C24XX
+config ARCH_S3C24XX_CHOICE
 	bool "Samsung S3C24XX SoCs"
-	select GENERIC_GPIO
-	select ARCH_HAS_CPUFREQ
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select ARCH_USES_GETTIMEOFFSET
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_IO_H
+	select ARCH_S3C24XX
 	help
 	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 	  Samsung SMDK2410 development board (and derivatives).
 
-config ARCH_S3C64XX
+config ARCH_S3C64XX_CHOICE
 	bool "Samsung S3C64XX"
-	select PLAT_SAMSUNG
-	select CPU_V6
-	select ARM_VIC
-	select HAVE_CLK
-	select HAVE_TCM
-	select CLKDEV_LOOKUP
-	select NO_IOPORT
-	select ARCH_USES_GETTIMEOFFSET
-	select ARCH_HAS_CPUFREQ
-	select ARCH_REQUIRE_GPIOLIB
-	select SAMSUNG_CLKSRC
-	select SAMSUNG_IRQ_VIC_TIMER
-	select S3C_GPIO_TRACK
-	select S3C_DEV_NAND
-	select USB_ARCH_HAS_OHCI
-	select SAMSUNG_GPIOLIB_4BIT
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select NEED_MACH_GPIO_H
+	select ARCH_S3C64XX
 	help
 	  Samsung S3C64XX series based systems
 
-config ARCH_S5P64X0
+config ARCH_S5P64X0_CHOICE
 	bool "Samsung S5P6440 S5P6450"
-	select CPU_V6
-	select GENERIC_GPIO
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select GENERIC_CLOCKEVENTS
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C_RTC if RTC_CLASS
-	select NEED_MACH_GPIO_H
+	select ARCH_S5P64X0
 	help
 	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 	  SMDK6450.
 
-config ARCH_S5PC100
+config ARCH_S5PC100_CHOICE
 	bool "Samsung S5PC100"
-	select GENERIC_GPIO
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select CPU_V7
-	select ARCH_USES_GETTIMEOFFSET
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select NEED_MACH_GPIO_H
+	select ARCH_S5PC100
 	help
 	  Samsung S5PC100 series based systems
 
-config ARCH_S5PV210
+config ARCH_S5PV210_CHOICE
 	bool "Samsung S5PV210/S5PC110"
-	select CPU_V7
-	select ARCH_SPARSEMEM_ENABLE
-	select ARCH_HAS_HOLES_MEMORYMODEL
-	select GENERIC_GPIO
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select CLKSRC_MMIO
-	select ARCH_HAS_CPUFREQ
-	select GENERIC_CLOCKEVENTS
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_MEMORY_H
+	select ARCH_S5PV210
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_EXYNOS
+config ARCH_EXYNOS_CHOICE
 	bool "SAMSUNG EXYNOS"
-	select CPU_V7
-	select ARCH_SPARSEMEM_ENABLE
-	select ARCH_HAS_HOLES_MEMORYMODEL
-	select GENERIC_GPIO
-	select HAVE_CLK
-	select CLKDEV_LOOKUP
-	select ARCH_HAS_CPUFREQ
-	select GENERIC_CLOCKEVENTS
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select NEED_MACH_GPIO_H
-	select NEED_MACH_MEMORY_H
+	select ARCH_EXYNOS
 	help
 	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 
-config ARCH_SHARK
+config ARCH_SHARK_CHOICE
 	bool "Shark"
-	select CPU_SA110
-	select ISA
-	select ISA_DMA
-	select ZONE_DMA
-	select PCI
-	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_MEMORY_H
-	select NEED_MACH_IO_H
+	select ARCH_SHARK
 	help
 	  Support for the StrongARM based Digital DNARD machine, also known
 	  as "Shark" (<http://www.shark-linux.de/shark.html>).
 
-config ARCH_U300
+config ARCH_U300_CHOICE
 	bool "ST-Ericsson U300 Series"
 	depends on MMU
-	select CLKSRC_MMIO
-	select CPU_ARM926T
-	select HAVE_TCM
-	select ARM_AMBA
-	select ARM_PATCH_PHYS_VIRT
-	select ARM_VIC
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select GENERIC_GPIO
-	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_U300
 	help
 	  Support for ST-Ericsson U300 series mobile platforms.
 
-config ARCH_U8500
+config ARCH_U8500_CHOICE
 	bool "ST-Ericsson U8500 Series"
 	depends on MMU
-	select CPU_V7
-	select ARM_AMBA
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_HAS_CPUFREQ
-	select HAVE_SMP
-	select MIGHT_HAVE_CACHE_L2X0
+	select ARCH_U8500
 	help
 	  Support for ST-Ericsson's Ux500 architecture
 
-config ARCH_NOMADIK
+config ARCH_NOMADIK_CHOICE
 	bool "STMicroelectronics Nomadik"
-	select ARM_AMBA
-	select ARM_VIC
-	select CPU_ARM926T
-	select COMMON_CLK
-	select GENERIC_CLOCKEVENTS
-	select PINCTRL
-	select MIGHT_HAVE_CACHE_L2X0
-	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_NOMADIK
 	help
 	  Support for the Nomadik platform by ST-Ericsson
 
-config ARCH_DAVINCI
+config ARCH_DAVINCI_CHOICE
 	bool "TI DaVinci"
-	select GENERIC_CLOCKEVENTS
-	select ARCH_REQUIRE_GPIOLIB
-	select ZONE_DMA
-	select HAVE_IDE
-	select CLKDEV_LOOKUP
-	select GENERIC_ALLOCATOR
-	select GENERIC_IRQ_CHIP
-	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_DAVINCI
 	select NEED_MACH_GPIO_H
 	help
 	  Support for TI's DaVinci platform.
 
-config ARCH_OMAP
+config ARCH_OMAP_CHOICE
 	bool "TI OMAP"
 	depends on MMU
-	select HAVE_CLK
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_HAS_CPUFREQ
-	select CLKSRC_MMIO
-	select GENERIC_CLOCKEVENTS
-	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_OMAP
 	help
 	  Support for TI's OMAP platform (OMAP1/2/3/4).
 
-config PLAT_SPEAR
+config PLAT_SPEAR_CHOICE
 	bool "ST SPEAr"
-	select ARM_AMBA
-	select ARCH_REQUIRE_GPIOLIB
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CLKSRC_MMIO
-	select GENERIC_CLOCKEVENTS
-	select HAVE_CLK
+	select PLAT_SPEAR
 	help
 	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 
-config ARCH_VT8500
+config ARCH_VT8500_CHOICE
 	bool "VIA/WonderMedia 85xx"
-	select CPU_ARM926T
-	select GENERIC_GPIO
-	select ARCH_HAS_CPUFREQ
-	select GENERIC_CLOCKEVENTS
-	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_VT8500
 	help
 	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
-config ARCH_ZYNQ
+config ARCH_ZYNQ_CHOICE
 	bool "Xilinx Zynq ARM Cortex A9 Platform"
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select ARM_GIC
-	select ARM_AMBA
-	select ICST
-	select MIGHT_HAVE_CACHE_L2X0
-	select USE_OF
+	select ARCH_ZYNQ
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
@@ -1058,6 +648,8 @@ source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-dove/Kconfig"
 
+source "arch/arm/mach-ebsa110/Kconfig"
+
 source "arch/arm/mach-ep93xx/Kconfig"
 
 source "arch/arm/mach-footbridge/Kconfig"
@@ -1066,6 +658,8 @@ source "arch/arm/mach-gemini/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
 
+source "arch/arm/mach-highbank/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -1080,6 +674,8 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
 
+source "arch/arm/mach-lpc32xx/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1101,6 +697,10 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
+source "arch/arm/mach-picoxcell/Kconfig"
+
+source "arch/arm/mach-pnx4008/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/plat-pxa/Kconfig"
 
@@ -1108,11 +708,17 @@ source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-realview/Kconfig"
 
+source "arch/arm/mach-rpc/Kconfig"
+
 source "arch/arm/mach-sa1100/Kconfig"
 
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 
+source "arch/arm/mach-shark/Kconfig"
+
+source "arch/arm/mach-socfpga/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
@@ -1121,9 +727,7 @@ source "arch/arm/mach-s3c2412/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
 endif
 
-if ARCH_S3C64XX
 source "arch/arm/mach-s3c64xx/Kconfig"
-endif
 
 source "arch/arm/mach-s5p64x0/Kconfig"
 
@@ -1150,6 +754,8 @@ source "arch/arm/mach-vt8500/Kconfig"
 
 source "arch/arm/mach-w90x900/Kconfig"
 
+source "arch/arm/mach-zynq/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8050b1..835886a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,3 +1,11 @@
+config ARCH_AT91
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select HAVE_CLK
+	select IRQ_DOMAIN
+	select NEED_MACH_IO_H if PCCARD
+
 if ARCH_AT91
 
 config HAVE_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
index 9170d16..7a8c869 100644
--- a/arch/arm/mach-bcmring/Kconfig
+++ b/arch/arm/mach-bcmring/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_BCMRING
+	bool
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select CLKDEV_LOOKUP
+	select CPU_V6
+	select GENERIC_CLOCKEVENTS
+
 choice
 	prompt "Processor selection in BCMRING family of devices"
 	depends on ARCH_BCMRING
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index ea036d6..2d3dba9 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -1,3 +1,9 @@
+config ARCH_CLPS711X
+	bool
+	select ARCH_USES_GETTIMEOFFSET
+	select CPU_ARM720T
+	select NEED_MACH_MEMORY_H
+
 if ARCH_CLPS711X
 
 menu "CLPS711X/EP721X/EP731X Implementations"
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 29b13f2..0dab723 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_CNS3XXX
+	bool
+	select CPU_V6K
+	select GENERIC_CLOCKEVENTS
+	select ARM_GIC
+	select MIGHT_HAVE_CACHE_L2X0
+	select MIGHT_HAVE_PCI
+	select PCI_DOMAINS if PCI
+
 menu "CNS3XXX platform type"
 	depends on ARCH_CNS3XXX
 
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index ab99c3c..3e0102b 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,3 +1,15 @@
+config ARCH_DAVINCI
+	bool
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select GENERIC_ALLOCATOR
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_IRQ_CHIP
+	select HAVE_IDE
+	select NEED_MACH_GPIO_H
+	select ZONE_DMA
+
 if ARCH_DAVINCI
 
 config AINTC
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c5..34b7bdb 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_DOVE
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
+	select PCI
+	select PLAT_ORION
+
 if ARCH_DOVE
 
 menu "Marvell Dove Implementations"
diff --git a/arch/arm/mach-ebsa110/Kconfig b/arch/arm/mach-ebsa110/Kconfig
new file mode 100644
index 0000000..3ca0f58
--- /dev/null
+++ b/arch/arm/mach-ebsa110/Kconfig
@@ -0,0 +1,9 @@
+config ARCH_EBSA110
+	bool
+	select CPU_SA110
+	select ISA
+	select NO_IOPORT
+	select ARCH_USES_GETTIMEOFFSET
+	select NEED_MACH_IO_H
+	select NEED_MACH_MEMORY_H
+
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index fe3c1fa..4cf770c 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_EP93XX
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_USES_GETTIMEOFFSET
+	select ARM_AMBA
+	select ARM_VIC
+	select CLKDEV_LOOKUP
+	select CPU_ARM920T
+	select NEED_MACH_MEMORY_H
+
 if ARCH_EP93XX
 
 menu "Cirrus EP93xx Implementation Options"
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..4e78a4a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -7,6 +7,22 @@
 
 # Configuration options for the EXYNOS4
 
+config ARCH_EXYNOS
+	bool
+	select ARCH_SPARSEMEM_ENABLE
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select CLKDEV_LOOKUP
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_MEMORY_H
+
 if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index f643ef8..6690953 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_FOOTBRIDGE
+	bool
+	select CPU_SA110
+	select FOOTBRIDGE
+	select GENERIC_CLOCKEVENTS
+	select HAVE_IDE
+	select NEED_MACH_IO_H
+	select NEED_MACH_MEMORY_H
+
 if ARCH_FOOTBRIDGE
 
 menu "Footbridge Implementations"
diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig
index 6f066ee..54d4cee 100644
--- a/arch/arm/mach-gemini/Kconfig
+++ b/arch/arm/mach-gemini/Kconfig
@@ -1,3 +1,9 @@
+config ARCH_GEMINI
+	bool
+	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_FA526
+
 if ARCH_GEMINI
 
 menu "Cortina Systems Gemini Implementations"
diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig
index abf356c..566a4ed 100644
--- a/arch/arm/mach-h720x/Kconfig
+++ b/arch/arm/mach-h720x/Kconfig
@@ -1,3 +1,9 @@
+config ARCH_H720X
+	bool
+	select CPU_ARM720T
+	select ISA_DMA_API
+	select ARCH_USES_GETTIMEOFFSET
+
 if ARCH_H720X
 
 menu "h720x Implementations"
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
new file mode 100644
index 0000000..d4f1b23
--- /dev/null
+++ b/arch/arm/mach-highbank/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_HIGHBANK
+	bool
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_TIMER_SP804
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU
+	select HAVE_SMP
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 350e266..88afd42 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_INTEGRATOR
+	bool
+	select ARM_AMBA
+	select ARCH_HAS_CPUFREQ
+	select COMMON_CLK
+	select CLK_VERSATILE
+	select HAVE_TCM
+	select ICST
+	select GENERIC_CLOCKEVENTS
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_FPGA_IRQ
+	select NEED_MACH_IO_H
+	select NEED_MACH_MEMORY_H
+	select SPARSE_IRQ
+	select MULTI_IRQ_HANDLER
+
 if ARCH_INTEGRATOR
 
 menu "Integrator Options"
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
index 40c2d68..d004752 100644
--- a/arch/arm/mach-iop13xx/Kconfig
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_IOP13XX
+	bool
+	select CPU_XSC3
+	select PLAT_IOP
+	select PCI
+	select ARCH_SUPPORTS_MSI
+	select VMSPLIT_1G
+	select NEED_MACH_IO_H
+	select NEED_MACH_MEMORY_H
+	select NEED_RET_TO_USER
+
 if ARCH_IOP13XX
 
 menu "IOP13XX Implementation Options"
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index 5e8c6f7..f438f73 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -1,3 +1,13 @@
+config ARCH_IOP32X
+	bool
+	select CPU_XSCALE
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_IO_H
+	select NEED_RET_TO_USER
+	select PLAT_IOP
+	select PCI
+	select ARCH_REQUIRE_GPIOLIB
+
 if ARCH_IOP32X
 
 menu "IOP32x Implementation Options"
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
index 9aa016b..20b3dbe 100644
--- a/arch/arm/mach-iop33x/Kconfig
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -1,3 +1,13 @@
+config ARCH_IOP33X
+	bool
+	select CPU_XSCALE
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_IO_H
+	select NEED_RET_TO_USER
+	select PLAT_IOP
+	select PCI
+	select ARCH_REQUIRE_GPIOLIB
+
 if ARCH_IOP33X
 
 menu "IOP33x Implementation Options"
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index fd5e7b6..48f9978 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_IXP4XX
+	bool
+	select ARCH_HAS_DMA_SET_COHERENT_MASK
+	select CLKSRC_MMIO
+	select CPU_XSCALE
+	select ARCH_REQUIRE_GPIOLIB
+	select GENERIC_CLOCKEVENTS
+	select MIGHT_HAVE_PCI
+	select NEED_MACH_IO_H
+	select DMABOUNCE if PCI
+
 if ARCH_IXP4XX
 
 config ARCH_SUPPORTS_BIG_ENDIAN
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a..2fedc99 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_KIRKWOOD
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_FEROCEON
+	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
+	select PCI
+	select PLAT_ORION
+
 if ARCH_KIRKWOOD
 
 menu "Marvell Kirkwood Implementations"
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
index f5c39a8..f73a02f 100644
--- a/arch/arm/mach-ks8695/Kconfig
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -1,3 +1,10 @@
+config ARCH_KS8695
+	bool
+	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_ARM922T
+	select NEED_MACH_MEMORY_H
+
 if ARCH_KS8695
 
 menu "Kendin/Micrel KS8695 Implementations"
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 0000000..7975c48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,12 @@
+config ARCH_LPC32XX
+	bool
+	select CLKSRC_MMIO
+	select CPU_ARM926T
+	select ARCH_REQUIRE_GPIOLIB
+	select HAVE_IDE
+	select ARM_AMBA
+	select USB_ARCH_HAS_OHCI
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select USE_OF
+	select HAVE_PWM
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 7fddd01..2c586fd 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -1,3 +1,15 @@
+config ARCH_MMP
+	bool
+	depends on MMU
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PXA
+	select IRQ_DOMAIN
+	select PLAT_PXA
+	select SPARSE_IRQ
+	select GENERIC_ALLOCATOR
+
 if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1cd40ad..8b6994e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,3 +1,10 @@
+config ARCH_MSM
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK
+
 if ARCH_MSM
 
 choice
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
index f2d309d..6c09349 100644
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_MV78XX0
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_FEROCEON
+	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
+	select PCI
+	select PLAT_ORION
+
 if ARCH_MV78XX0
 
 menu "Marvell MV78xx0 Implementations"
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..1ed7d15 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,3 +1,13 @@
+config ARCH_MVEBU
+	bool
+	select CLKSRC_MMIO
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+
 if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 9a8bbda..cea9703 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_MXS
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK_PREPARE
+	select PINCTRL
+	select USE_OF
+
 if ARCH_MXS
 
 source "arch/arm/mach-mxs/devices/Kconfig"
diff --git a/arch/arm/mach-netx/Kconfig b/arch/arm/mach-netx/Kconfig
index 3d90ef1..29b1d56 100644
--- a/arch/arm/mach-netx/Kconfig
+++ b/arch/arm/mach-netx/Kconfig
@@ -1,3 +1,10 @@
+config ARCH_NETX
+	bool
+	select ARM_VIC
+	select CLKSRC_MMIO
+	select CPU_ARM926T
+	select GENERIC_CLOCKEVENTS
+
 menu "NetX Implementations"
 	depends on ARCH_NETX
 
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 365879b..af0821d 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_NOMADIK
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select ARM_VIC
+	select COMMON_CLK
+	select CPU_ARM926T
+	select GENERIC_CLOCKEVENTS
+	select MIGHT_HAVE_CACHE_L2X0
+	select PINCTRL
+
 if ARCH_NOMADIK
 
 menu "Nomadik boards"
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 0673f0c..c8470c7 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_ORION5X
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select CPU_FEROCEON
+	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
+	select PCI
+	select PLAT_ORION
+
 if ARCH_ORION5X
 
 menu "Orion Implementations"
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 0000000..b0fd5a1
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,14 @@
+config ARCH_PICOXCELL
+	bool
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_VIC
+	select CPU_V6K
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_TCM
+	select NO_IOPORT
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-pnx4008/Kconfig b/arch/arm/mach-pnx4008/Kconfig
new file mode 100644
index 0000000..b654cff
--- /dev/null
+++ b/arch/arm/mach-pnx4008/Kconfig
@@ -0,0 +1,5 @@
+config ARCH_PNX4008
+	bool
+	select CPU_ARM926T
+	select CLKDEV_LOOKUP
+	select ARCH_USES_GETTIMEOFFSET
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f8..1c89e24 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_PXA
+	bool
+	select ARCH_HAS_CPUFREQ
+	select ARCH_MTD_XIP
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_CPU_SUSPEND if PM
+	select AUTO_ZRELADDR
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PXA
+	select HAVE_IDE
+	select MULTI_IRQ_HANDLER
+	select PLAT_PXA
+	select SPARSE_IRQ
+
 if ARCH_PXA
 
 menu "Intel PXA2xx/PXA3xx Implementations"
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index c593be4..2018527 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -1,3 +1,18 @@
+config ARCH_REALVIEW
+	bool
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_MACH_CLKDEV
+	select ICST
+	select NEED_MACH_MEMORY_H
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
+	select PLAT_VERSATILE_CLCD
+
 menu "RealView platform type"
 	depends on ARCH_REALVIEW
 
diff --git a/arch/arm/mach-rpc/Kconfig b/arch/arm/mach-rpc/Kconfig
new file mode 100644
index 0000000..478d213
--- /dev/null
+++ b/arch/arm/mach-rpc/Kconfig
@@ -0,0 +1,13 @@
+config ARCH_RPC
+	bool
+	select ARCH_ACORN
+	select FIQ
+	select ARCH_MAY_HAVE_PC_FDC
+	select HAVE_PATA_PLATFORM
+	select ISA_DMA_API
+	select NO_IOPORT
+	select ARCH_SPARSEMEM_ENABLE
+	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_IDE
+	select NEED_MACH_IO_H
+	select NEED_MACH_MEMORY_H
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d56b0f7..21dd369 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -7,6 +7,19 @@
 #
 # Licensed under GPLv2
 
+config ARCH_S3C24XX
+	bool
+	select ARCH_HAS_CPUFREQ
+	select ARCH_USES_GETTIMEOFFSET
+	select CLKDEV_LOOKUP
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_IO_H
+
 if ARCH_S3C24XX
 
 menu "SAMSUNG S3C24XX SoCs Support"
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 06ca1cd..4a0cdbb 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -3,6 +3,30 @@
 #
 # Licensed under GPLv2
 
+config ARCH_S3C64XX
+	bool
+	select PLAT_SAMSUNG
+	select CPU_V6
+	select ARM_VIC
+	select HAVE_CLK
+	select HAVE_TCM
+	select CLKDEV_LOOKUP
+	select NO_IOPORT
+	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_HAS_CPUFREQ
+	select ARCH_REQUIRE_GPIOLIB
+	select SAMSUNG_CLKSRC
+	select SAMSUNG_IRQ_VIC_TIMER
+	select S3C_GPIO_TRACK
+	select S3C_DEV_NAND
+	select USB_ARCH_HAS_OHCI
+	select SAMSUNG_GPIOLIB_4BIT
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
+
+if ARCH_S3C64XX
+
 # temporary until we can eliminate all drivers using it.
 config PLAT_S3C64XX
 	bool
@@ -307,3 +331,5 @@ config MACH_WLF_CRAGG_6410
 	select LEDS_GPIO_REGISTER
 	help
 	  Machine support for the Wolfson Cragganmore S3C6410 variant.
+
+endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index c87f610..8215c54 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -5,6 +5,19 @@
 #
 # Licensed under GPLv2
 
+config ARCH_S5P64X0
+	bool
+	select CPU_V6
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select GENERIC_CLOCKEVENTS
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C_RTC if RTC_CLASS
+	select NEED_MACH_GPIO_H
+
 if ARCH_S5P64X0
 
 config CPU_S5P6440
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 75a26ea..8114a81 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,6 +5,18 @@
 
 # Configuration options for the S5PC100 CPU
 
+config ARCH_S5PC100
+	bool
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
+	select CPU_V7
+	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
+
 if ARCH_S5PC100
 
 config CPU_S5PC100
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 77185c3..5633743 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -7,6 +7,23 @@
 
 # Configuration options for the S5PV210/S5PC110
 
+config ARCH_S5PV210
+	bool
+	select CPU_V7
+	select ARCH_SPARSEMEM_ENABLE
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select ARCH_HAS_CPUFREQ
+	select GENERIC_CLOCKEVENTS
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_MEMORY_H
+
 if ARCH_S5PV210
 
 config CPU_S5PV210
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 42625e4..37c31a3 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -1,3 +1,20 @@
+config ARCH_SA1100
+	bool
+	select CLKSRC_MMIO
+	select CPU_SA1100
+	select ISA
+	select ARCH_SPARSEMEM_ENABLE
+	select ARCH_MTD_XIP
+	select ARCH_HAS_CPUFREQ
+	select CPU_FREQ
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select ARCH_REQUIRE_GPIOLIB
+	select HAVE_IDE
+	select NEED_MACH_GPIO_H
+	select NEED_MACH_MEMORY_H
+	select SPARSE_IRQ
+
 if ARCH_SA1100
 
 menu "SA11x0 Implementations"
diff --git a/arch/arm/mach-shark/Kconfig b/arch/arm/mach-shark/Kconfig
new file mode 100644
index 0000000..93d03db
--- /dev/null
+++ b/arch/arm/mach-shark/Kconfig
@@ -0,0 +1,11 @@
+config ARCH_SHARK
+	bool
+	select CPU_SA110
+	select ISA
+	select ISA_DMA
+	select ZONE_DMA
+	select PCI
+	select ARCH_USES_GETTIMEOFFSET
+	select NEED_MACH_MEMORY_H
+	select NEED_MACH_IO_H
+
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4cacc2d..ee807ad 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,3 +1,17 @@
+config ARCH_SHMOBILE
+	bool
+	select HAVE_CLK
+	select CLKDEV_LOOKUP
+	select HAVE_MACH_CLKDEV
+	select HAVE_SMP
+	select GENERIC_CLOCKEVENTS
+	select MIGHT_HAVE_CACHE_L2X0
+	select NO_IOPORT
+	select SPARSE_IRQ
+	select MULTI_IRQ_HANDLER
+	select PM_GENERIC_DOMAINS if PM
+	select NEED_MACH_MEMORY_H
+
 if ARCH_SHMOBILE
 
 comment "SH-Mobile System Type"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 0000000..51b04ba
--- /dev/null
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_SOCFPGA
+	bool
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9077aaa..d6ee9f5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,3 +1,16 @@
+config ARCH_TEGRA
+	bool
+	select ARCH_HAS_CPUFREQ
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select HAVE_SMP
+	select MIGHT_HAVE_CACHE_L2X0
+	select NEED_MACH_IO_H if PCI
+	select USE_OF
+
 if ARCH_TEGRA
 
 comment "NVIDIA Tegra options"
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34..bd442a0 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,3 +1,17 @@
+config ARCH_U300
+	bool
+	select CLKSRC_MMIO
+	select CPU_ARM926T
+	select HAVE_TCM
+	select ARM_AMBA
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_VIC
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select GENERIC_GPIO
+	select ARCH_REQUIRE_GPIOLIB
+
 if ARCH_U300
 
 menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf..6b40959 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_U8500
+	bool
+	select CPU_V7
+	select ARM_AMBA
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_CPUFREQ
+	select HAVE_SMP
+	select MIGHT_HAVE_CACHE_L2X0
+
 if ARCH_U8500
 
 config UX500_SOC_COMMON
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index c1f38f6..cd63ea6 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_VERSATILE
+	bool
+	select ARM_AMBA
+	select ARM_VIC
+	select CLKDEV_LOOKUP
+	select HAVE_MACH_CLKDEV
+	select ICST
+	select GENERIC_CLOCKEVENTS
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select NEED_MACH_IO_H if PCI
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLOCK
+	select PLAT_VERSATILE_CLCD
+	select PLAT_VERSATILE_FPGA_IRQ
+	select ARM_TIMER_SP804
+
 menu "Versatile platform type"
 	depends on ARCH_VERSATILE
 
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index fc3730f..8ce13a7 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_VEXPRESS
+	bool
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK
+	select HAVE_PATA_PLATFORM
+	select ICST
+	select NO_IOPORT
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLCD
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 menu "Versatile Express platform type"
 	depends on ARCH_VEXPRESS
 
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 2c20a34..fa22d24 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -1,3 +1,11 @@
+config ARCH_VT8500
+	bool
+	select CPU_ARM926T
+	select GENERIC_GPIO
+	select ARCH_HAS_CPUFREQ
+	select GENERIC_CLOCKEVENTS
+	select ARCH_REQUIRE_GPIOLIB
+
 if ARCH_VT8500
 
 config VTWM_VERSION_VT8500
diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
index 69bab32..ab4b2fc 100644
--- a/arch/arm/mach-w90x900/Kconfig
+++ b/arch/arm/mach-w90x900/Kconfig
@@ -1,3 +1,11 @@
+config ARCH_W90X900
+	bool
+	select CPU_ARM926T
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+
 if ARCH_W90X900
 
 config CPU_W90P910
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
new file mode 100644
index 0000000..1560167
--- /dev/null
+++ b/arch/arm/mach-zynq/Kconfig
@@ -0,0 +1,10 @@
+config ARCH_ZYNQ
+	bool
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select CLKDEV_LOOKUP
+	select ARM_GIC
+	select ARM_AMBA
+	select ICST
+	select MIGHT_HAVE_CACHE_L2X0
+	select USE_OF
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index baf9064..84af663 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,3 +1,14 @@
+config ARCH_MXC
+	bool
+	select GENERIC_CLOCKEVENTS
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select CLKSRC_MMIO
+	select GENERIC_IRQ_CHIP
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+	select USE_OF
+
 if ARCH_MXC
 
 source "arch/arm/plat-mxc/devices/Kconfig"
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba..8b86fca 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -1,3 +1,12 @@
+config ARCH_OMAP
+	bool
+	select HAVE_CLK
+	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_CPUFREQ
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+	select ARCH_HAS_HOLES_MEMORYMODEL
+
 if ARCH_OMAP
 
 menu "TI OMAP Common Features"
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 4404f82..50088bb 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -1,6 +1,15 @@
 #
 # SPEAr Platform configuration file
 #
+config PLAT_SPEAR
+	bool
+	select ARM_AMBA
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK
 
 if PLAT_SPEAR
 
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:58 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:58 -0500
Subject: [PATCH 4/6] ARM: vexpress: remove dependency on mach/* headers
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-5-git-send-email-robherring2@gmail.com>

From: Arnd Bergmann <arnd at arndb.de>

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-vexpress/ct-ca9x4.c          |    1 +
 arch/arm/mach-vexpress/include/mach/irqs.h |    2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c4924..0e770e8 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -27,6 +27,7 @@
 #include "core.h"
 
 #include <mach/motherboard.h>
+#include <mach/irqs.h>
 
 #include <plat/clcd.h>
 
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 4b10ee7..f8f7f78 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,6 @@
 #define IRQ_LOCALTIMER		29
 #define IRQ_LOCALWDOG		30
 
+#ifndef CONFIG_SPARSE_IRQ
 #define NR_IRQS	256
+#endif
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:57 -0500
Subject: [PATCH 3/6] ARM: picoxcell: header fixes for multi-platform
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-picoxcell/common.c                   |    6 ++---
 arch/arm/mach-picoxcell/include/mach/map.h         |   25 --------------------
 .../mach-picoxcell/include/mach/picoxcell_soc.h    |   25 --------------------
 arch/arm/mach-picoxcell/picoxcell_soc.h            |   25 ++++++++++++++++++++
 4 files changed, 28 insertions(+), 53 deletions(-)
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/map.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
 create mode 100644 arch/arm/mach-picoxcell/picoxcell_soc.h

diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 8f9a0b4..a8b70b5 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -20,11 +20,11 @@
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
 
-#include <mach/map.h>
-#include <mach/picoxcell_soc.h>
-
+#include "picoxcell_soc.h"
 #include "common.h"
 
+#define PHYS_TO_IO(x)		(((x) & 0x00ffffff) | 0xfe000000)
+
 #define WDT_CTRL_REG_EN_MASK	(1 << 0)
 #define WDT_CTRL_REG_OFFS	(0x00)
 #define WDT_TIMEOUT_REG_OFFS	(0x04)
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-picoxcell/include/mach/map.h
deleted file mode 100644
index c06afad..0000000
--- a/arch/arm/mach-picoxcell/include/mach/map.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __PICOXCELL_MAP_H__
-#define __PICOXCELL_MAP_H__
-
-#define PHYS_TO_IO(x)		(((x) & 0x00ffffff) | 0xfe000000)
-
-#ifdef __ASSEMBLY__
-#define IO_ADDRESS(x)		PHYS_TO_IO((x))
-#else
-#define IO_ADDRESS(x)		(void __iomem __force *)(PHYS_TO_IO((x)))
-#endif
-
-#endif /* __PICOXCELL_MAP_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
deleted file mode 100644
index 5566fc8..0000000
--- a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This file contains the hardware definitions of the picoXcell SoC devices.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __PICOXCELL_SOC_H__
-#define __PICOXCELL_SOC_H__
-
-#define PICOXCELL_UART1_BASE		0x80230000
-#define PICOXCELL_PERIPH_BASE		0x80000000
-#define PICOXCELL_PERIPH_LENGTH		SZ_4M
-#define PICOXCELL_VIC0_BASE		0x80060000
-#define PICOXCELL_VIC1_BASE		0x80064000
-
-#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/picoxcell_soc.h b/arch/arm/mach-picoxcell/picoxcell_soc.h
new file mode 100644
index 0000000..5566fc8
--- /dev/null
+++ b/arch/arm/mach-picoxcell/picoxcell_soc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __PICOXCELL_SOC_H__
+#define __PICOXCELL_SOC_H__
+
+#define PICOXCELL_UART1_BASE		0x80230000
+#define PICOXCELL_PERIPH_BASE		0x80000000
+#define PICOXCELL_PERIPH_LENGTH		SZ_4M
+#define PICOXCELL_VIC0_BASE		0x80060000
+#define PICOXCELL_VIC1_BASE		0x80064000
+
+#endif /* __PICOXCELL_SOC_H__ */
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:56 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:56 -0500
Subject: [PATCH 2/6] ARM: introduce Kconfig.mach
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move all the mach related config options into separate Kconfig.mach file.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig      |  529 +------------------------------------------------
 arch/arm/Kconfig.mach |  528 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 529 insertions(+), 528 deletions(-)
 create mode 100644 arch/arm/Kconfig.mach

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3ad82c6..fa34df2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -248,534 +248,7 @@ config MMU
 	  Select if you want MMU-based virtualised addressing space
 	  support by paged memory management. If unsure, say 'Y'.
 
-#
-# The "ARM system type" choice list is ordered alphabetically by option
-# text.  Please add new entries in the option alphabetic order.
-#
-choice
-	prompt "ARM system type"
-	default ARCH_VERSATILE
-
-config ARCH_SOCFPGA_CHOICE
-	bool "Altera SOCFPGA family"
-	select ARCH_SOCFPGA
-	help
-	  This enables support for Altera SOCFPGA Cyclone V platform
-
-config ARCH_INTEGRATOR_CHOICE
-	bool "ARM Ltd. Integrator family"
-	select ARCH_INTEGRATOR
-	help
-	  Support for ARM's Integrator platform.
-
-config ARCH_REALVIEW_CHOICE
-	bool "ARM Ltd. RealView family"
-	select ARCH_REALVIEW
-	help
-	  This enables support for ARM Ltd RealView boards.
-
-config ARCH_VERSATILE_CHOICE
-	bool "ARM Ltd. Versatile family"
-	select ARCH_VERSATILE
-	help
-	  This enables support for ARM Ltd Versatile board.
-
-config ARCH_VEXPRESS_CHOICE
-	bool "ARM Ltd. Versatile Express family"
-	select ARCH_VEXPRESS
-	help
-	  This enables support for the ARM Ltd Versatile Express boards.
-
-config ARCH_AT91_CHOICE
-	bool "Atmel AT91"
-	select ARCH_AT91
-	help
-	  This enables support for systems based on Atmel
-	  AT91RM9200 and AT91SAM9* processors.
-
-config ARCH_BCMRING_CHOICE
-	bool "Broadcom BCMRING"
-	depends on MMU
-	select ARCH_BCMRING
-	help
-	  Support for Broadcom's BCMRing platform.
-
-config ARCH_HIGHBANK_CHOICE
-	bool "Calxeda Highbank-based"
-	select ARCH_HIGHBANK
-	help
-	  Support for the Calxeda Highbank SoC based boards.
-
-config ARCH_CLPS711X_CHOICE
-	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
-	select ARCH_CLPS711X
-	help
-	  Support for Cirrus Logic 711x/721x/731x based boards.
-
-config ARCH_CNS3XXX_CHOICE
-	bool "Cavium Networks CNS3XXX family"
-	select ARCH_CNS3XXX
-	help
-	  Support for Cavium Networks CNS3XXX platform.
-
-config ARCH_GEMINI_CHOICE
-	bool "Cortina Systems Gemini"
-	select ARCH_GEMINI
-	help
-	  Support for the Cortina Systems Gemini family SoCs
-
-config ARCH_PRIMA2_CHOICE
-	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-	select ARCH_PRIMA2
-	help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
-
-config ARCH_EBSA110_CHOICE
-	bool "EBSA-110"
-	select ARCH_EBSA110
-	help
-	  This is an evaluation board for the StrongARM processor available
-	  from Digital. It has limited hardware on-board, including an
-	  Ethernet interface, two PCMCIA sockets, two serial ports and a
-	  parallel port.
-
-config ARCH_EP93XX_CHOICE
-	bool "EP93xx-based"
-	select ARCH_EP93XX
-	help
-	  This enables support for the Cirrus EP93xx series of CPUs.
-
-config ARCH_FOOTBRIDGE_CHOICE
-	bool "FootBridge"
-	select ARCH_FOOTBRIDGE
-	help
-	  Support for systems based on the DC21285 companion chip
-	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-
-config ARCH_MXC_CHOICE
-	bool "Freescale MXC/iMX-based"
-	select ARCH_MXC
-	help
-	  Support for Freescale MXC/iMX-based family of processors
-
-config ARCH_MXS_CHOICE
-	bool "Freescale MXS-based"
-	select ARCH_MXS
-	help
-	  Support for Freescale MXS-based family of processors
-
-config ARCH_NETX_CHOICE
-	bool "Hilscher NetX based"
-	select ARCH_NETX
-	help
-	  This enables support for systems based on the Hilscher NetX Soc
-
-config ARCH_H720X_CHOICE
-	bool "Hynix HMS720x-based"
-	select ARCH_H720X
-	help
-	  This enables support for systems based on the Hynix HMS720x
-
-config ARCH_IOP13XX_CHOICE
-	bool "IOP13xx-based"
-	depends on MMU
-	select ARCH_IOP13XX
-	help
-	  Support for Intel's IOP13XX (XScale) family of processors.
-
-config ARCH_IOP32X_CHOICE
-	bool "IOP32x-based"
-	depends on MMU
-	select ARCH_IOP32X
-	help
-	  Support for Intel's 80219 and IOP32X (XScale) family of
-	  processors.
-
-config ARCH_IOP33X_CHOICE
-	bool "IOP33x-based"
-	depends on MMU
-	select ARCH_IOP33X
-	help
-	  Support for Intel's IOP33X (XScale) family of processors.
-
-config ARCH_IXP4XX_CHOICE
-	bool "IXP4xx-based"
-	depends on MMU
-	select ARCH_IXP4XX
-	help
-	  Support for Intel's IXP4XX (XScale) family of processors.
-
-config ARCH_MVEBU_CHOICE
-	bool "Marvell SOCs with Device Tree support"
-	select ARCH_MVEBU
-	help
-	  Support for the Marvell SoC Family with device tree support
-
-config ARCH_DOVE_CHOICE
-	bool "Marvell Dove"
-	select ARCH_DOVE
-	help
-	  Support for the Marvell Dove SoC 88AP510
-
-config ARCH_KIRKWOOD_CHOICE
-	bool "Marvell Kirkwood"
-	select ARCH_KIRKWOOD
-	help
-	  Support for the following Marvell Kirkwood series SoCs:
-	  88F6180, 88F6192 and 88F6281.
-
-config ARCH_LPC32XX_CHOICE
-	bool "NXP LPC32XX"
-	select ARCH_LPC32XX
-	help
-	  Support for the NXP LPC32XX family of processors
-
-config ARCH_MV78XX0_CHOICE
-	bool "Marvell MV78xx0"
-	select ARCH_MV78XX0
-	help
-	  Support for the following Marvell MV78xx0 series SoCs:
-	  MV781x0, MV782x0.
-
-config ARCH_ORION5X_CHOICE
-	bool "Marvell Orion"
-	depends on MMU
-	select ARCH_ORION5X
-	help
-	  Support for the following Marvell Orion 5x series SoCs:
-	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
-	  Orion-2 (5281), Orion-1-90 (6183).
-
-config ARCH_MMP_CHOICE
-	bool "Marvell PXA168/910/MMP2"
-	depends on MMU
-	select ARCH_MMP
-	help
-	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
-
-config ARCH_KS8695_CHOICE
-	bool "Micrel/Kendin KS8695"
-	select ARCH_KS8695
-	help
-	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
-	  System-on-Chip devices.
-
-config ARCH_W90X900_CHOICE
-	bool "Nuvoton W90X900 CPU"
-	select ARCH_W90X900
-	help
-	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
-	  At present, the w90x900 has been renamed nuc900, regarding
-	  the ARM series product line, you can login the following
-	  link address to know more.
-
-	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
-		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
-
-config ARCH_TEGRA_CHOICE
-	bool "NVIDIA Tegra"
-	select ARCH_TEGRA
-	help
-	  This enables support for NVIDIA Tegra based systems (Tegra APX,
-	  Tegra 6xx and Tegra 2 series).
-
-config ARCH_PICOXCELL_CHOICE
-	bool "Picochip picoXcell"
-	select ARCH_PICOXCELL
-	help
-	  This enables support for systems based on the Picochip picoXcell
-	  family of Femtocell devices.  The picoxcell support requires device tree
-	  for all boards.
-
-config ARCH_PNX4008_CHOICE
-	bool "Philips Nexperia PNX4008 Mobile"
-	select ARCH_PNX4008
-	help
-	  This enables support for Philips PNX4008 mobile platform.
-
-config ARCH_PXA_CHOICE
-	bool "PXA2xx/PXA3xx-based"
-	depends on MMU
-	select ARCH_PXA
-	help
-	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-
-config ARCH_MSM_CHOICE
-	bool "Qualcomm MSM"
-	select ARCH_MSM
-	help
-	  Support for Qualcomm MSM/QSD based systems.  This runs on the
-	  apps processor of the MSM/QSD and depends on a shared memory
-	  interface to the modem processor which runs the baseband
-	  stack and controls some vital subsystems
-	  (clock and power control, etc).
-
-config ARCH_SHMOBILE_CHOICE
-	bool "Renesas SH-Mobile / R-Mobile"
-	select ARCH_SHMOBILE
-	help
-	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
-
-config ARCH_RPC_CHOICE
-	bool "RiscPC"
-	select ARCH_RPC
-	help
-	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
-	  CD-ROM interface, serial and parallel port, and the floppy drive.
-
-config ARCH_SA1100_CHOICE
-	bool "SA1100-based"
-	select ARCH_SA1100
-	help
-	  Support for StrongARM 11x0 based boards.
-
-config ARCH_S3C24XX_CHOICE
-	bool "Samsung S3C24XX SoCs"
-	select ARCH_S3C24XX
-	help
-	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
-	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
-	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
-	  Samsung SMDK2410 development board (and derivatives).
-
-config ARCH_S3C64XX_CHOICE
-	bool "Samsung S3C64XX"
-	select ARCH_S3C64XX
-	help
-	  Samsung S3C64XX series based systems
-
-config ARCH_S5P64X0_CHOICE
-	bool "Samsung S5P6440 S5P6450"
-	select ARCH_S5P64X0
-	help
-	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
-	  SMDK6450.
-
-config ARCH_S5PC100_CHOICE
-	bool "Samsung S5PC100"
-	select ARCH_S5PC100
-	help
-	  Samsung S5PC100 series based systems
-
-config ARCH_S5PV210_CHOICE
-	bool "Samsung S5PV210/S5PC110"
-	select ARCH_S5PV210
-	help
-	  Samsung S5PV210/S5PC110 series based systems
-
-config ARCH_EXYNOS_CHOICE
-	bool "SAMSUNG EXYNOS"
-	select ARCH_EXYNOS
-	help
-	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
-
-config ARCH_SHARK_CHOICE
-	bool "Shark"
-	select ARCH_SHARK
-	help
-	  Support for the StrongARM based Digital DNARD machine, also known
-	  as "Shark" (<http://www.shark-linux.de/shark.html>).
-
-config ARCH_U300_CHOICE
-	bool "ST-Ericsson U300 Series"
-	depends on MMU
-	select ARCH_U300
-	help
-	  Support for ST-Ericsson U300 series mobile platforms.
-
-config ARCH_U8500_CHOICE
-	bool "ST-Ericsson U8500 Series"
-	depends on MMU
-	select ARCH_U8500
-	help
-	  Support for ST-Ericsson's Ux500 architecture
-
-config ARCH_NOMADIK_CHOICE
-	bool "STMicroelectronics Nomadik"
-	select ARCH_NOMADIK
-	help
-	  Support for the Nomadik platform by ST-Ericsson
-
-config ARCH_DAVINCI_CHOICE
-	bool "TI DaVinci"
-	select ARCH_DAVINCI
-	select NEED_MACH_GPIO_H
-	help
-	  Support for TI's DaVinci platform.
-
-config ARCH_OMAP_CHOICE
-	bool "TI OMAP"
-	depends on MMU
-	select ARCH_OMAP
-	help
-	  Support for TI's OMAP platform (OMAP1/2/3/4).
-
-config PLAT_SPEAR_CHOICE
-	bool "ST SPEAr"
-	select PLAT_SPEAR
-	help
-	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-
-config ARCH_VT8500_CHOICE
-	bool "VIA/WonderMedia 85xx"
-	select ARCH_VT8500
-	help
-	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
-
-config ARCH_ZYNQ_CHOICE
-	bool "Xilinx Zynq ARM Cortex A9 Platform"
-	select ARCH_ZYNQ
-	help
-	  Support for Xilinx Zynq ARM Cortex A9 Platform
-endchoice
-
-#
-# This is sorted alphabetically by mach-* pathname.  However, plat-*
-# Kconfigs may be included either alphabetically (according to the
-# plat- suffix) or along side the corresponding mach-* source.
-#
-source "arch/arm/mach-mvebu/Kconfig"
-
-source "arch/arm/mach-at91/Kconfig"
-
-source "arch/arm/mach-bcmring/Kconfig"
-
-source "arch/arm/mach-clps711x/Kconfig"
-
-source "arch/arm/mach-cns3xxx/Kconfig"
-
-source "arch/arm/mach-davinci/Kconfig"
-
-source "arch/arm/mach-dove/Kconfig"
-
-source "arch/arm/mach-ebsa110/Kconfig"
-
-source "arch/arm/mach-ep93xx/Kconfig"
-
-source "arch/arm/mach-footbridge/Kconfig"
-
-source "arch/arm/mach-gemini/Kconfig"
-
-source "arch/arm/mach-h720x/Kconfig"
-
-source "arch/arm/mach-highbank/Kconfig"
-
-source "arch/arm/mach-integrator/Kconfig"
-
-source "arch/arm/mach-iop32x/Kconfig"
-
-source "arch/arm/mach-iop33x/Kconfig"
-
-source "arch/arm/mach-iop13xx/Kconfig"
-
-source "arch/arm/mach-ixp4xx/Kconfig"
-
-source "arch/arm/mach-kirkwood/Kconfig"
-
-source "arch/arm/mach-ks8695/Kconfig"
-
-source "arch/arm/mach-lpc32xx/Kconfig"
-
-source "arch/arm/mach-msm/Kconfig"
-
-source "arch/arm/mach-mv78xx0/Kconfig"
-
-source "arch/arm/plat-mxc/Kconfig"
-
-source "arch/arm/mach-mxs/Kconfig"
-
-source "arch/arm/mach-netx/Kconfig"
-
-source "arch/arm/mach-nomadik/Kconfig"
-source "arch/arm/plat-nomadik/Kconfig"
-
-source "arch/arm/plat-omap/Kconfig"
-
-source "arch/arm/mach-omap1/Kconfig"
-
-source "arch/arm/mach-omap2/Kconfig"
-
-source "arch/arm/mach-orion5x/Kconfig"
-
-source "arch/arm/mach-picoxcell/Kconfig"
-
-source "arch/arm/mach-pnx4008/Kconfig"
-
-source "arch/arm/mach-pxa/Kconfig"
-source "arch/arm/plat-pxa/Kconfig"
-
-source "arch/arm/mach-mmp/Kconfig"
-
-source "arch/arm/mach-realview/Kconfig"
-
-source "arch/arm/mach-rpc/Kconfig"
-
-source "arch/arm/mach-sa1100/Kconfig"
-
-source "arch/arm/plat-samsung/Kconfig"
-source "arch/arm/plat-s3c24xx/Kconfig"
-
-source "arch/arm/mach-shark/Kconfig"
-
-source "arch/arm/mach-socfpga/Kconfig"
-
-source "arch/arm/plat-spear/Kconfig"
-
-source "arch/arm/mach-s3c24xx/Kconfig"
-if ARCH_S3C24XX
-source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2440/Kconfig"
-endif
-
-source "arch/arm/mach-s3c64xx/Kconfig"
-
-source "arch/arm/mach-s5p64x0/Kconfig"
-
-source "arch/arm/mach-s5pc100/Kconfig"
-
-source "arch/arm/mach-s5pv210/Kconfig"
-
-source "arch/arm/mach-exynos/Kconfig"
-
-source "arch/arm/mach-shmobile/Kconfig"
-
-source "arch/arm/mach-tegra/Kconfig"
-
-source "arch/arm/mach-u300/Kconfig"
-
-source "arch/arm/mach-ux500/Kconfig"
-
-source "arch/arm/mach-versatile/Kconfig"
-
-source "arch/arm/mach-vexpress/Kconfig"
-source "arch/arm/plat-versatile/Kconfig"
-
-source "arch/arm/mach-vt8500/Kconfig"
-
-source "arch/arm/mach-w90x900/Kconfig"
-
-source "arch/arm/mach-zynq/Kconfig"
-
-# Definitions to make life easier
-config ARCH_ACORN
-	bool
-
-config PLAT_IOP
-	bool
-	select GENERIC_CLOCKEVENTS
-
-config PLAT_ORION
-	bool
-	select CLKSRC_MMIO
-	select GENERIC_IRQ_CHIP
-	select IRQ_DOMAIN
-	select COMMON_CLK
-
-config PLAT_PXA
-	bool
-
-config PLAT_VERSATILE
-	bool
+source "arch/arm/Kconfig.mach"
 
 config ARM_TIMER_SP804
 	bool
diff --git a/arch/arm/Kconfig.mach b/arch/arm/Kconfig.mach
new file mode 100644
index 0000000..60f0386
--- /dev/null
+++ b/arch/arm/Kconfig.mach
@@ -0,0 +1,528 @@
+#
+# The "ARM system type" choice list is ordered alphabetically by option
+# text.  Please add new entries in the option alphabetic order.
+#
+choice
+	prompt "ARM system type"
+	default ARCH_VERSATILE
+
+config ARCH_SOCFPGA_CHOICE
+	bool "Altera SOCFPGA family"
+	select ARCH_SOCFPGA
+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform
+
+config ARCH_INTEGRATOR_CHOICE
+	bool "ARM Ltd. Integrator family"
+	select ARCH_INTEGRATOR
+	help
+	  Support for ARM's Integrator platform.
+
+config ARCH_REALVIEW_CHOICE
+	bool "ARM Ltd. RealView family"
+	select ARCH_REALVIEW
+	help
+	  This enables support for ARM Ltd RealView boards.
+
+config ARCH_VERSATILE_CHOICE
+	bool "ARM Ltd. Versatile family"
+	select ARCH_VERSATILE
+	help
+	  This enables support for ARM Ltd Versatile board.
+
+config ARCH_VEXPRESS_CHOICE
+	bool "ARM Ltd. Versatile Express family"
+	select ARCH_VEXPRESS
+	help
+	  This enables support for the ARM Ltd Versatile Express boards.
+
+config ARCH_AT91_CHOICE
+	bool "Atmel AT91"
+	select ARCH_AT91
+	help
+	  This enables support for systems based on Atmel
+	  AT91RM9200 and AT91SAM9* processors.
+
+config ARCH_BCMRING_CHOICE
+	bool "Broadcom BCMRING"
+	depends on MMU
+	select ARCH_BCMRING
+	help
+	  Support for Broadcom's BCMRing platform.
+
+config ARCH_HIGHBANK_CHOICE
+	bool "Calxeda Highbank-based"
+	select ARCH_HIGHBANK
+	help
+	  Support for the Calxeda Highbank SoC based boards.
+
+config ARCH_CLPS711X_CHOICE
+	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
+	select ARCH_CLPS711X
+	help
+	  Support for Cirrus Logic 711x/721x/731x based boards.
+
+config ARCH_CNS3XXX_CHOICE
+	bool "Cavium Networks CNS3XXX family"
+	select ARCH_CNS3XXX
+	help
+	  Support for Cavium Networks CNS3XXX platform.
+
+config ARCH_GEMINI_CHOICE
+	bool "Cortina Systems Gemini"
+	select ARCH_GEMINI
+	help
+	  Support for the Cortina Systems Gemini family SoCs
+
+config ARCH_PRIMA2_CHOICE
+	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+	select ARCH_PRIMA2
+	help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+config ARCH_EBSA110_CHOICE
+	bool "EBSA-110"
+	select ARCH_EBSA110
+	help
+	  This is an evaluation board for the StrongARM processor available
+	  from Digital. It has limited hardware on-board, including an
+	  Ethernet interface, two PCMCIA sockets, two serial ports and a
+	  parallel port.
+
+config ARCH_EP93XX_CHOICE
+	bool "EP93xx-based"
+	select ARCH_EP93XX
+	help
+	  This enables support for the Cirrus EP93xx series of CPUs.
+
+config ARCH_FOOTBRIDGE_CHOICE
+	bool "FootBridge"
+	select ARCH_FOOTBRIDGE
+	help
+	  Support for systems based on the DC21285 companion chip
+	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
+
+config ARCH_MXC_CHOICE
+	bool "Freescale MXC/iMX-based"
+	select ARCH_MXC
+	help
+	  Support for Freescale MXC/iMX-based family of processors
+
+config ARCH_MXS_CHOICE
+	bool "Freescale MXS-based"
+	select ARCH_MXS
+	help
+	  Support for Freescale MXS-based family of processors
+
+config ARCH_NETX_CHOICE
+	bool "Hilscher NetX based"
+	select ARCH_NETX
+	help
+	  This enables support for systems based on the Hilscher NetX Soc
+
+config ARCH_H720X_CHOICE
+	bool "Hynix HMS720x-based"
+	select ARCH_H720X
+	help
+	  This enables support for systems based on the Hynix HMS720x
+
+config ARCH_IOP13XX_CHOICE
+	bool "IOP13xx-based"
+	depends on MMU
+	select ARCH_IOP13XX
+	help
+	  Support for Intel's IOP13XX (XScale) family of processors.
+
+config ARCH_IOP32X_CHOICE
+	bool "IOP32x-based"
+	depends on MMU
+	select ARCH_IOP32X
+	help
+	  Support for Intel's 80219 and IOP32X (XScale) family of
+	  processors.
+
+config ARCH_IOP33X_CHOICE
+	bool "IOP33x-based"
+	depends on MMU
+	select ARCH_IOP33X
+	help
+	  Support for Intel's IOP33X (XScale) family of processors.
+
+config ARCH_IXP4XX_CHOICE
+	bool "IXP4xx-based"
+	depends on MMU
+	select ARCH_IXP4XX
+	help
+	  Support for Intel's IXP4XX (XScale) family of processors.
+
+config ARCH_MVEBU_CHOICE
+	bool "Marvell SOCs with Device Tree support"
+	select ARCH_MVEBU
+	help
+	  Support for the Marvell SoC Family with device tree support
+
+config ARCH_DOVE_CHOICE
+	bool "Marvell Dove"
+	select ARCH_DOVE
+	help
+	  Support for the Marvell Dove SoC 88AP510
+
+config ARCH_KIRKWOOD_CHOICE
+	bool "Marvell Kirkwood"
+	select ARCH_KIRKWOOD
+	help
+	  Support for the following Marvell Kirkwood series SoCs:
+	  88F6180, 88F6192 and 88F6281.
+
+config ARCH_LPC32XX_CHOICE
+	bool "NXP LPC32XX"
+	select ARCH_LPC32XX
+	help
+	  Support for the NXP LPC32XX family of processors
+
+config ARCH_MV78XX0_CHOICE
+	bool "Marvell MV78xx0"
+	select ARCH_MV78XX0
+	help
+	  Support for the following Marvell MV78xx0 series SoCs:
+	  MV781x0, MV782x0.
+
+config ARCH_ORION5X_CHOICE
+	bool "Marvell Orion"
+	depends on MMU
+	select ARCH_ORION5X
+	help
+	  Support for the following Marvell Orion 5x series SoCs:
+	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
+	  Orion-2 (5281), Orion-1-90 (6183).
+
+config ARCH_MMP_CHOICE
+	bool "Marvell PXA168/910/MMP2"
+	depends on MMU
+	select ARCH_MMP
+	help
+	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
+
+config ARCH_KS8695_CHOICE
+	bool "Micrel/Kendin KS8695"
+	select ARCH_KS8695
+	help
+	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
+	  System-on-Chip devices.
+
+config ARCH_W90X900_CHOICE
+	bool "Nuvoton W90X900 CPU"
+	select ARCH_W90X900
+	help
+	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
+	  At present, the w90x900 has been renamed nuc900, regarding
+	  the ARM series product line, you can login the following
+	  link address to know more.
+
+	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
+		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
+
+config ARCH_TEGRA_CHOICE
+	bool "NVIDIA Tegra"
+	select ARCH_TEGRA
+	help
+	  This enables support for NVIDIA Tegra based systems (Tegra APX,
+	  Tegra 6xx and Tegra 2 series).
+
+config ARCH_PICOXCELL_CHOICE
+	bool "Picochip picoXcell"
+	select ARCH_PICOXCELL
+	help
+	  This enables support for systems based on the Picochip picoXcell
+	  family of Femtocell devices.  The picoxcell support requires device tree
+	  for all boards.
+
+config ARCH_PNX4008_CHOICE
+	bool "Philips Nexperia PNX4008 Mobile"
+	select ARCH_PNX4008
+	help
+	  This enables support for Philips PNX4008 mobile platform.
+
+config ARCH_PXA_CHOICE
+	bool "PXA2xx/PXA3xx-based"
+	depends on MMU
+	select ARCH_PXA
+	help
+	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
+
+config ARCH_MSM_CHOICE
+	bool "Qualcomm MSM"
+	select ARCH_MSM
+	help
+	  Support for Qualcomm MSM/QSD based systems.  This runs on the
+	  apps processor of the MSM/QSD and depends on a shared memory
+	  interface to the modem processor which runs the baseband
+	  stack and controls some vital subsystems
+	  (clock and power control, etc).
+
+config ARCH_SHMOBILE_CHOICE
+	bool "Renesas SH-Mobile / R-Mobile"
+	select ARCH_SHMOBILE
+	help
+	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
+
+config ARCH_RPC_CHOICE
+	bool "RiscPC"
+	select ARCH_RPC
+	help
+	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
+	  CD-ROM interface, serial and parallel port, and the floppy drive.
+
+config ARCH_SA1100_CHOICE
+	bool "SA1100-based"
+	select ARCH_SA1100
+	help
+	  Support for StrongARM 11x0 based boards.
+
+config ARCH_S3C24XX_CHOICE
+	bool "Samsung S3C24XX SoCs"
+	select ARCH_S3C24XX
+	help
+	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
+	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
+	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
+	  Samsung SMDK2410 development board (and derivatives).
+
+config ARCH_S3C64XX_CHOICE
+	bool "Samsung S3C64XX"
+	select ARCH_S3C64XX
+	help
+	  Samsung S3C64XX series based systems
+
+config ARCH_S5P64X0_CHOICE
+	bool "Samsung S5P6440 S5P6450"
+	select ARCH_S5P64X0
+	help
+	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
+	  SMDK6450.
+
+config ARCH_S5PC100_CHOICE
+	bool "Samsung S5PC100"
+	select ARCH_S5PC100
+	help
+	  Samsung S5PC100 series based systems
+
+config ARCH_S5PV210_CHOICE
+	bool "Samsung S5PV210/S5PC110"
+	select ARCH_S5PV210
+	help
+	  Samsung S5PV210/S5PC110 series based systems
+
+config ARCH_EXYNOS_CHOICE
+	bool "SAMSUNG EXYNOS"
+	select ARCH_EXYNOS
+	help
+	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
+
+config ARCH_SHARK_CHOICE
+	bool "Shark"
+	select ARCH_SHARK
+	help
+	  Support for the StrongARM based Digital DNARD machine, also known
+	  as "Shark" (<http://www.shark-linux.de/shark.html>).
+
+config ARCH_U300_CHOICE
+	bool "ST-Ericsson U300 Series"
+	depends on MMU
+	select ARCH_U300
+	help
+	  Support for ST-Ericsson U300 series mobile platforms.
+
+config ARCH_U8500_CHOICE
+	bool "ST-Ericsson U8500 Series"
+	depends on MMU
+	select ARCH_U8500
+	help
+	  Support for ST-Ericsson's Ux500 architecture
+
+config ARCH_NOMADIK_CHOICE
+	bool "STMicroelectronics Nomadik"
+	select ARCH_NOMADIK
+	help
+	  Support for the Nomadik platform by ST-Ericsson
+
+config ARCH_DAVINCI_CHOICE
+	bool "TI DaVinci"
+	select ARCH_DAVINCI
+	help
+	  Support for TI's DaVinci platform.
+
+config ARCH_OMAP_CHOICE
+	bool "TI OMAP"
+	depends on MMU
+	select ARCH_OMAP
+	help
+	  Support for TI's OMAP platform (OMAP1/2/3/4).
+
+config PLAT_SPEAR_CHOICE
+	bool "ST SPEAr"
+	select PLAT_SPEAR
+	help
+	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
+
+config ARCH_VT8500_CHOICE
+	bool "VIA/WonderMedia 85xx"
+	select ARCH_VT8500
+	help
+	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+
+config ARCH_ZYNQ_CHOICE
+	bool "Xilinx Zynq ARM Cortex A9 Platform"
+	select ARCH_ZYNQ
+	help
+	  Support for Xilinx Zynq ARM Cortex A9 Platform
+endchoice
+
+#
+# This is sorted alphabetically by mach-* pathname.  However, plat-*
+# Kconfigs may be included either alphabetically (according to the
+# plat- suffix) or along side the corresponding mach-* source.
+#
+source "arch/arm/mach-mvebu/Kconfig"
+
+source "arch/arm/mach-at91/Kconfig"
+
+source "arch/arm/mach-bcmring/Kconfig"
+
+source "arch/arm/mach-clps711x/Kconfig"
+
+source "arch/arm/mach-cns3xxx/Kconfig"
+
+source "arch/arm/mach-davinci/Kconfig"
+
+source "arch/arm/mach-dove/Kconfig"
+
+source "arch/arm/mach-ebsa110/Kconfig"
+
+source "arch/arm/mach-ep93xx/Kconfig"
+
+source "arch/arm/mach-footbridge/Kconfig"
+
+source "arch/arm/mach-gemini/Kconfig"
+
+source "arch/arm/mach-h720x/Kconfig"
+
+source "arch/arm/mach-highbank/Kconfig"
+
+source "arch/arm/mach-integrator/Kconfig"
+
+source "arch/arm/mach-iop32x/Kconfig"
+
+source "arch/arm/mach-iop33x/Kconfig"
+
+source "arch/arm/mach-iop13xx/Kconfig"
+
+source "arch/arm/mach-ixp4xx/Kconfig"
+
+source "arch/arm/mach-kirkwood/Kconfig"
+
+source "arch/arm/mach-ks8695/Kconfig"
+
+source "arch/arm/mach-lpc32xx/Kconfig"
+
+source "arch/arm/mach-msm/Kconfig"
+
+source "arch/arm/mach-mv78xx0/Kconfig"
+
+source "arch/arm/plat-mxc/Kconfig"
+
+source "arch/arm/mach-mxs/Kconfig"
+
+source "arch/arm/mach-netx/Kconfig"
+
+source "arch/arm/mach-nomadik/Kconfig"
+source "arch/arm/plat-nomadik/Kconfig"
+
+source "arch/arm/plat-omap/Kconfig"
+
+source "arch/arm/mach-omap1/Kconfig"
+
+source "arch/arm/mach-omap2/Kconfig"
+
+source "arch/arm/mach-orion5x/Kconfig"
+
+source "arch/arm/mach-picoxcell/Kconfig"
+
+source "arch/arm/mach-pnx4008/Kconfig"
+
+source "arch/arm/mach-pxa/Kconfig"
+source "arch/arm/plat-pxa/Kconfig"
+
+source "arch/arm/mach-mmp/Kconfig"
+
+source "arch/arm/mach-realview/Kconfig"
+
+source "arch/arm/mach-rpc/Kconfig"
+
+source "arch/arm/mach-sa1100/Kconfig"
+
+source "arch/arm/plat-samsung/Kconfig"
+source "arch/arm/plat-s3c24xx/Kconfig"
+
+source "arch/arm/mach-shark/Kconfig"
+
+source "arch/arm/mach-socfpga/Kconfig"
+
+source "arch/arm/plat-spear/Kconfig"
+
+source "arch/arm/mach-s3c24xx/Kconfig"
+if ARCH_S3C24XX
+source "arch/arm/mach-s3c2412/Kconfig"
+source "arch/arm/mach-s3c2440/Kconfig"
+endif
+
+source "arch/arm/mach-s3c64xx/Kconfig"
+
+source "arch/arm/mach-s5p64x0/Kconfig"
+
+source "arch/arm/mach-s5pc100/Kconfig"
+
+source "arch/arm/mach-s5pv210/Kconfig"
+
+source "arch/arm/mach-exynos/Kconfig"
+
+source "arch/arm/mach-shmobile/Kconfig"
+
+source "arch/arm/mach-tegra/Kconfig"
+
+source "arch/arm/mach-u300/Kconfig"
+
+source "arch/arm/mach-ux500/Kconfig"
+
+source "arch/arm/mach-versatile/Kconfig"
+
+source "arch/arm/mach-vexpress/Kconfig"
+source "arch/arm/plat-versatile/Kconfig"
+
+source "arch/arm/mach-vt8500/Kconfig"
+
+source "arch/arm/mach-w90x900/Kconfig"
+
+source "arch/arm/mach-zynq/Kconfig"
+
+# Definitions to make life easier
+config ARCH_ACORN
+	bool
+
+config PLAT_IOP
+	bool
+	select GENERIC_CLOCKEVENTS
+
+config PLAT_ORION
+	bool
+	select CLKSRC_MMIO
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select COMMON_CLK
+
+config PLAT_PXA
+	bool
+
+config PLAT_VERSATILE
+	bool
+
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:49:59 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:49:59 -0500
Subject: [PATCH 5/6] ARM: initial multiplatform support
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This lets us build a multiplatform kernel for experimental purposes.
However, it will not be useful for any real work, because it relies
on a number of useful things to be disabled for now:

* SMP support must be turned off because of conflicting symbols.
  Marc Zyngier has proposed a solution by adding a new SOC
  operations structure to hold indirect function pointers
  for these, but that work is currently stalled

* We turn on SPARSE_IRQ unconditionally, which is not supported
  on most platforms. Each of them is currently in a different
  state, but most are being worked on.

* A common clock framework is in place since v3.4 but not yet
  being used. Work on this is on its way.

* DEBUG_LL for early debugging is currently disabled.

* THUMB2_KERNEL does not work with allyesconfig because the
  kernel gets too big

[Rob Herring]: Rebased to not be dependent on the mass mach header rename.
As a result, omap2plus, imx, mxs and ux500 are not converted. Highbank,
picoxcell, mvebu, socfpga, and vexpress are converted.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig.mach            |   57 ++++++++++++++
 arch/arm/Makefile                |  155 ++++++++++++++++++++------------------
 arch/arm/boot/compressed/misc.c  |    6 ++
 arch/arm/include/asm/timex.h     |    4 +
 arch/arm/mach-highbank/Kconfig   |    2 +-
 arch/arm/mach-mvebu/Kconfig      |    2 +-
 arch/arm/mach-mvebu/Makefile     |    2 +
 arch/arm/mach-picoxcell/Kconfig  |    2 +-
 arch/arm/mach-socfpga/Kconfig    |    2 +-
 arch/arm/mach-vexpress/Kconfig   |    2 +-
 arch/arm/mach-vexpress/Makefile  |    2 +
 arch/arm/plat-versatile/Makefile |    2 +
 12 files changed, 158 insertions(+), 80 deletions(-)

diff --git a/arch/arm/Kconfig.mach b/arch/arm/Kconfig.mach
index 60f0386..7a21abb 100644
--- a/arch/arm/Kconfig.mach
+++ b/arch/arm/Kconfig.mach
@@ -4,6 +4,7 @@
 #
 choice
 	prompt "ARM system type"
+	depends on !ARCH_MULTIPLATFORM
 	default ARCH_VERSATILE
 
 config ARCH_SOCFPGA_CHOICE
@@ -378,6 +379,62 @@ config ARCH_ZYNQ_CHOICE
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
 
+menuconfig ARCH_MULTIPLATFORM
+	bool "Multiple platform selection"
+	select USE_OF
+	select COMMON_CLK
+	select SPARSE_IRQ
+	select MULTI_IRQ_HANDLER
+	select AUTO_ZRELADDR
+	depends on MMU
+
+if ARCH_MULTIPLATFORM
+
+comment "CPU Core family selection"
+
+config ARCH_MULTI_V4
+	bool "ARMv4 based platforms (FA526, StrongARM)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4T
+	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V5
+	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4_V5
+	bool
+
+config ARCH_MULTI_V6
+	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+	select CPU_V6
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V7
+	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+	select CPU_V7
+	select ARCH_VEXPRESS
+	default y
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V6_V7
+	bool
+
+config ARCH_MULTI_CPU_AUTO
+	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
+	select ARCH_MULTI_V5
+
+endif
+
+if ARCH_MULTIPLATFORM
+comment "SoC family selection"
+endif
+
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..fe6e05e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -135,84 +135,84 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
-machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
-machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
-machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
-machine-$(CONFIG_ARCH_DOVE)		:= dove
-machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
-machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
-machine-$(CONFIG_ARCH_GEMINI)		:= gemini
-machine-$(CONFIG_ARCH_H720X)		:= h720x
-machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
-machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
-machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
-machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
-machine-$(CONFIG_ARCH_IOP33X)		:= iop33x
-machine-$(CONFIG_ARCH_IXP4XX)		:= ixp4xx
-machine-$(CONFIG_ARCH_KIRKWOOD)		:= kirkwood
-machine-$(CONFIG_ARCH_KS8695)		:= ks8695
-machine-$(CONFIG_ARCH_LPC32XX)		:= lpc32xx
-machine-$(CONFIG_ARCH_MMP)		:= mmp
-machine-$(CONFIG_ARCH_MSM)		:= msm
-machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
-machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
-machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
-machine-$(CONFIG_ARCH_MXS)		:= mxs
-machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
-machine-$(CONFIG_ARCH_NETX)		:= netx
-machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
-machine-$(CONFIG_ARCH_OMAP1)		:= omap1
-machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
-machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
-machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
-machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
-machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
-machine-$(CONFIG_ARCH_PXA)		:= pxa
-machine-$(CONFIG_ARCH_REALVIEW)		:= realview
-machine-$(CONFIG_ARCH_RPC)		:= rpc
-machine-$(CONFIG_ARCH_S3C24XX)		:= s3c24xx s3c2412 s3c2440
-machine-$(CONFIG_ARCH_S3C64XX)		:= s3c64xx
-machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
-machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
-machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
-machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
-machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
-machine-$(CONFIG_ARCH_SA1100)		:= sa1100
-machine-$(CONFIG_ARCH_SHARK)		:= shark
-machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
-machine-$(CONFIG_ARCH_TEGRA)		:= tegra
-machine-$(CONFIG_ARCH_U300)		:= u300
-machine-$(CONFIG_ARCH_U8500)		:= ux500
-machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
-machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
-machine-$(CONFIG_ARCH_VT8500)		:= vt8500
-machine-$(CONFIG_ARCH_W90X900)		:= w90x900
-machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
-machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
-machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
-machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
-machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
-machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
+machine-$(CONFIG_ARCH_AT91)		+= at91
+machine-$(CONFIG_ARCH_BCMRING)		+= bcmring
+machine-$(CONFIG_ARCH_CLPS711X)		+= clps711x
+machine-$(CONFIG_ARCH_CNS3XXX)		+= cns3xxx
+machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
+machine-$(CONFIG_ARCH_DOVE)		+= dove
+machine-$(CONFIG_ARCH_EBSA110)		+= ebsa110
+machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
+machine-$(CONFIG_ARCH_GEMINI)		+= gemini
+machine-$(CONFIG_ARCH_H720X)		+= h720x
+machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
+machine-$(CONFIG_ARCH_INTEGRATOR)	+= integrator
+machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx
+machine-$(CONFIG_ARCH_IOP32X)		+= iop32x
+machine-$(CONFIG_ARCH_IOP33X)		+= iop33x
+machine-$(CONFIG_ARCH_IXP4XX)		+= ixp4xx
+machine-$(CONFIG_ARCH_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARCH_KS8695)		+= ks8695
+machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
+machine-$(CONFIG_ARCH_MMP)		+= mmp
+machine-$(CONFIG_ARCH_MSM)		+= msm
+machine-$(CONFIG_ARCH_MV78XX0)		+= mv78xx0
+machine-$(CONFIG_ARCH_IMX_V4_V5)	+= imx
+machine-$(CONFIG_ARCH_IMX_V6_V7)	+= imx
+machine-$(CONFIG_ARCH_MXS)		+= mxs
+machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
+machine-$(CONFIG_ARCH_NETX)		+= netx
+machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_OMAP1)		+= omap1
+machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
+machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
+machine-$(CONFIG_ARCH_PICOXCELL)	+= picoxcell
+machine-$(CONFIG_ARCH_PNX4008)		+= pnx4008
+machine-$(CONFIG_ARCH_PRIMA2)		+= prima2
+machine-$(CONFIG_ARCH_PXA)		+= pxa
+machine-$(CONFIG_ARCH_REALVIEW)		+= realview
+machine-$(CONFIG_ARCH_RPC)		+= rpc
+machine-$(CONFIG_ARCH_S3C24XX)		+= s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S3C64XX)		+= s3c64xx
+machine-$(CONFIG_ARCH_S5P64X0)		+= s5p64x0
+machine-$(CONFIG_ARCH_S5PC100)		+= s5pc100
+machine-$(CONFIG_ARCH_S5PV210)		+= s5pv210
+machine-$(CONFIG_ARCH_EXYNOS4)		+= exynos
+machine-$(CONFIG_ARCH_EXYNOS5)		+= exynos
+machine-$(CONFIG_ARCH_SA1100)		+= sa1100
+machine-$(CONFIG_ARCH_SHARK)		+= shark
+machine-$(CONFIG_ARCH_SHMOBILE) 	+= shmobile
+machine-$(CONFIG_ARCH_TEGRA)		+= tegra
+machine-$(CONFIG_ARCH_U300)		+= u300
+machine-$(CONFIG_ARCH_U8500)		+= ux500
+machine-$(CONFIG_ARCH_VERSATILE)	+= versatile
+machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
+machine-$(CONFIG_ARCH_VT8500)		+= vt8500
+machine-$(CONFIG_ARCH_W90X900)		+= w90x900
+machine-$(CONFIG_FOOTBRIDGE)		+= footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
+machine-$(CONFIG_MACH_SPEAR1310)	+= spear13xx
+machine-$(CONFIG_MACH_SPEAR1340)	+= spear13xx
+machine-$(CONFIG_MACH_SPEAR300)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR310)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR320)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR600)		+= spear6xx
+machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_MXC)		:= mxc
-plat-$(CONFIG_ARCH_OMAP)	:= omap
-plat-$(CONFIG_ARCH_S3C64XX)	:= samsung
-plat-$(CONFIG_ARCH_ZYNQ)	:= versatile
-plat-$(CONFIG_PLAT_IOP)		:= iop
-plat-$(CONFIG_PLAT_NOMADIK)	:= nomadik
-plat-$(CONFIG_PLAT_ORION)	:= orion
-plat-$(CONFIG_PLAT_PXA)		:= pxa
-plat-$(CONFIG_PLAT_S3C24XX)	:= s3c24xx samsung
-plat-$(CONFIG_PLAT_S5P)		:= samsung
-plat-$(CONFIG_PLAT_SPEAR)	:= spear
-plat-$(CONFIG_PLAT_VERSATILE)	:= versatile
+plat-$(CONFIG_ARCH_MXC)		+= mxc
+plat-$(CONFIG_ARCH_OMAP)	+= omap
+plat-$(CONFIG_ARCH_S3C64XX)	+= samsung
+plat-$(CONFIG_ARCH_ZYNQ)	+= versatile
+plat-$(CONFIG_PLAT_IOP)		+= iop
+plat-$(CONFIG_PLAT_NOMADIK)	+= nomadik
+plat-$(CONFIG_PLAT_ORION)	+= orion
+plat-$(CONFIG_PLAT_PXA)		+= pxa
+plat-$(CONFIG_PLAT_S3C24XX)	+= s3c24xx samsung
+plat-$(CONFIG_PLAT_S5P)		+= samsung
+plat-$(CONFIG_PLAT_SPEAR)	+= spear
+plat-$(CONFIG_PLAT_VERSATILE)	+= versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -230,15 +230,20 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
+ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+MACHINE  :=
+endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 
+ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
+endif
 
 export	TEXT_OFFSET GZFLAGS MMUEXT
 
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 8e2a8fc..df89983 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 extern void error(char *x);
 
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+#else
 #include <mach/uncompress.h>
+#endif
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce11944..963342a 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -13,7 +13,11 @@
 #define _ASMARM_TIMEX_H
 
 #include <asm/arch_timer.h>
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define CLOCK_TICK_RATE 1000000
+#else
 #include <mach/timex.h>
+#endif
 
 typedef unsigned long cycles_t;
 
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index d4f1b23..0e1d0a4 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_HIGHBANK
-	bool
+	bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 1ed7d15..7b27035 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_MVEBU
-	bool
+	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
 	select CLKSRC_MMIO
 	select COMMON_CLK
 	select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8..6ea8998 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,4 @@
+ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
 obj-y += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index b0fd5a1..868796f 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_PICOXCELL
-	bool
+	bool "Picochip PicoXcell" if ARCH_MULTI_V6
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_PATCH_PHYS_VIRT
 	select ARM_VIC
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 51b04ba..803a328 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_SOCFPGA
-	bool
+	bool "Altera SOCFPGA family" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 8ce13a7..498ea15 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,5 +1,5 @@
 config ARCH_VEXPRESS
-	bool
+	bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_TIMER_SP804
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9..42703e8 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,6 +1,8 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+	-I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 272769a8..74cfd94 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,3 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
-- 
1.7.9.5



From robherring2 at gmail.com  Wed Aug 29 18:50:00 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 29 Aug 2012 17:50:00 -0500
Subject: [PATCH 6/6] ARM: update defconfigs
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346280600-29395-7-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Converted with this script:

sed -i -e 's/\(CONFIG_ARCH_.*\)=/\1_CHOICE=/' -- arch/arm/configs/*

and then fixup all the duplicates.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/configs/acs5k_defconfig           |    2 +-
 arch/arm/configs/acs5k_tiny_defconfig      |    2 +-
 arch/arm/configs/afeb9260_defconfig        |    2 +-
 arch/arm/configs/ag5evm_defconfig          |    2 +-
 arch/arm/configs/am200epdkit_defconfig     |    2 +-
 arch/arm/configs/ap4evb_defconfig          |    2 +-
 arch/arm/configs/armadillo800eva_defconfig |    2 +-
 arch/arm/configs/assabet_defconfig         |    2 +-
 arch/arm/configs/at91_dt_defconfig         |    2 +-
 arch/arm/configs/at91rm9200_defconfig      |    2 +-
 arch/arm/configs/at91sam9260_defconfig     |    2 +-
 arch/arm/configs/at91sam9261_defconfig     |    2 +-
 arch/arm/configs/at91sam9263_defconfig     |    2 +-
 arch/arm/configs/at91sam9g20_defconfig     |    2 +-
 arch/arm/configs/at91sam9g45_defconfig     |    2 +-
 arch/arm/configs/at91sam9rl_defconfig      |    2 +-
 arch/arm/configs/at91x40_defconfig         |    2 +-
 arch/arm/configs/badge4_defconfig          |    2 +-
 arch/arm/configs/bcmring_defconfig         |    2 +-
 arch/arm/configs/bonito_defconfig          |    2 +-
 arch/arm/configs/cam60_defconfig           |    2 +-
 arch/arm/configs/cerfcube_defconfig        |    2 +-
 arch/arm/configs/cm_x2xx_defconfig         |    2 +-
 arch/arm/configs/cm_x300_defconfig         |    2 +-
 arch/arm/configs/cns3420vb_defconfig       |    2 +-
 arch/arm/configs/colibri_pxa270_defconfig  |    2 +-
 arch/arm/configs/colibri_pxa300_defconfig  |    2 +-
 arch/arm/configs/collie_defconfig          |    2 +-
 arch/arm/configs/corgi_defconfig           |    2 +-
 arch/arm/configs/cpu9260_defconfig         |    2 +-
 arch/arm/configs/cpu9g20_defconfig         |    2 +-
 arch/arm/configs/da8xx_omapl_defconfig     |    2 +-
 arch/arm/configs/davinci_all_defconfig     |    2 +-
 arch/arm/configs/dove_defconfig            |    2 +-
 arch/arm/configs/ebsa110_defconfig         |    2 +-
 arch/arm/configs/edb7211_defconfig         |    2 +-
 arch/arm/configs/em_x270_defconfig         |    2 +-
 arch/arm/configs/ep93xx_defconfig          |    2 +-
 arch/arm/configs/eseries_pxa_defconfig     |    2 +-
 arch/arm/configs/exynos4_defconfig         |    2 +-
 arch/arm/configs/exynos_defconfig          |    4 ++--
 arch/arm/configs/ezx_defconfig             |    2 +-
 arch/arm/configs/footbridge_defconfig      |    2 +-
 arch/arm/configs/fortunet_defconfig        |    2 +-
 arch/arm/configs/g3evm_defconfig           |    2 +-
 arch/arm/configs/g4evm_defconfig           |    2 +-
 arch/arm/configs/h3600_defconfig           |    2 +-
 arch/arm/configs/h5000_defconfig           |    2 +-
 arch/arm/configs/h7201_defconfig           |    2 +-
 arch/arm/configs/h7202_defconfig           |    2 +-
 arch/arm/configs/hackkit_defconfig         |    2 +-
 arch/arm/configs/imote2_defconfig          |    2 +-
 arch/arm/configs/imx_v4_v5_defconfig       |    2 +-
 arch/arm/configs/imx_v6_v7_defconfig       |    2 +-
 arch/arm/configs/integrator_defconfig      |    2 +-
 arch/arm/configs/iop13xx_defconfig         |    2 +-
 arch/arm/configs/iop32x_defconfig          |    2 +-
 arch/arm/configs/iop33x_defconfig          |    2 +-
 arch/arm/configs/ixp4xx_defconfig          |    2 +-
 arch/arm/configs/jornada720_defconfig      |    2 +-
 arch/arm/configs/kirkwood_defconfig        |    2 +-
 arch/arm/configs/kota2_defconfig           |    2 +-
 arch/arm/configs/ks8695_defconfig          |    2 +-
 arch/arm/configs/kzm9d_defconfig           |    2 +-
 arch/arm/configs/kzm9g_defconfig           |    2 +-
 arch/arm/configs/lart_defconfig            |    2 +-
 arch/arm/configs/lpc32xx_defconfig         |    2 +-
 arch/arm/configs/lpd270_defconfig          |    2 +-
 arch/arm/configs/lubbock_defconfig         |    2 +-
 arch/arm/configs/mackerel_defconfig        |    2 +-
 arch/arm/configs/magician_defconfig        |    2 +-
 arch/arm/configs/mainstone_defconfig       |    2 +-
 arch/arm/configs/marzen_defconfig          |    2 +-
 arch/arm/configs/mini2440_defconfig        |    2 +-
 arch/arm/configs/mmp2_defconfig            |    2 +-
 arch/arm/configs/msm_defconfig             |    2 +-
 arch/arm/configs/mv78xx0_defconfig         |    2 +-
 arch/arm/configs/mvebu_defconfig           |    2 +-
 arch/arm/configs/mxs_defconfig             |    2 +-
 arch/arm/configs/neponset_defconfig        |    2 +-
 arch/arm/configs/netwinder_defconfig       |    2 +-
 arch/arm/configs/netx_defconfig            |    2 +-
 arch/arm/configs/nhk8815_defconfig         |    2 +-
 arch/arm/configs/nuc910_defconfig          |    2 +-
 arch/arm/configs/nuc950_defconfig          |    2 +-
 arch/arm/configs/nuc960_defconfig          |    2 +-
 arch/arm/configs/omap1_defconfig           |    2 +-
 arch/arm/configs/omap2plus_defconfig       |    2 +-
 arch/arm/configs/orion5x_defconfig         |    2 +-
 arch/arm/configs/palmz72_defconfig         |    2 +-
 arch/arm/configs/pcm027_defconfig          |    2 +-
 arch/arm/configs/pleb_defconfig            |    2 +-
 arch/arm/configs/pnx4008_defconfig         |    2 +-
 arch/arm/configs/prima2_defconfig          |    2 +-
 arch/arm/configs/pxa168_defconfig          |    2 +-
 arch/arm/configs/pxa255-idp_defconfig      |    2 +-
 arch/arm/configs/pxa3xx_defconfig          |    2 +-
 arch/arm/configs/pxa910_defconfig          |    2 +-
 arch/arm/configs/qil-a9260_defconfig       |    2 +-
 arch/arm/configs/raumfeld_defconfig        |    2 +-
 arch/arm/configs/realview-smp_defconfig    |    2 +-
 arch/arm/configs/realview_defconfig        |    2 +-
 arch/arm/configs/rpc_defconfig             |    2 +-
 arch/arm/configs/s3c2410_defconfig         |    2 +-
 arch/arm/configs/s3c6400_defconfig         |    2 +-
 arch/arm/configs/s5p64x0_defconfig         |    2 +-
 arch/arm/configs/s5pc100_defconfig         |    2 +-
 arch/arm/configs/s5pv210_defconfig         |    2 +-
 arch/arm/configs/sam9_l9260_defconfig      |    2 +-
 arch/arm/configs/shannon_defconfig         |    2 +-
 arch/arm/configs/shark_defconfig           |    2 +-
 arch/arm/configs/simpad_defconfig          |    2 +-
 arch/arm/configs/socfpga_defconfig         |    2 +-
 arch/arm/configs/spear13xx_defconfig       |    2 +-
 arch/arm/configs/spear6xx_defconfig        |    2 +-
 arch/arm/configs/spitz_defconfig           |    2 +-
 arch/arm/configs/stamp9g20_defconfig       |    2 +-
 arch/arm/configs/tct_hammer_defconfig      |    2 +-
 arch/arm/configs/tegra_defconfig           |    2 +-
 arch/arm/configs/trizeps4_defconfig        |    2 +-
 arch/arm/configs/u300_defconfig            |    2 +-
 arch/arm/configs/u8500_defconfig           |    2 +-
 arch/arm/configs/usb-a9260_defconfig       |    2 +-
 arch/arm/configs/vexpress_defconfig        |    2 +-
 arch/arm/configs/viper_defconfig           |    2 +-
 arch/arm/configs/xcep_defconfig            |    2 +-
 arch/arm/configs/zeus_defconfig            |    2 +-
 127 files changed, 128 insertions(+), 128 deletions(-)

diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig
index 92b0f90..7543bef 100644
--- a/arch/arm/configs/acs5k_defconfig
+++ b/arch/arm/configs/acs5k_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_KS8695=y
+CONFIG_ARCH_KS8695_CHOICE=y
 CONFIG_MACH_KS8695=y
 CONFIG_MACH_DSM320=y
 CONFIG_MACH_ACS5K=y
diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig
index 2a27a14..89de2f2 100644
--- a/arch/arm/configs/acs5k_tiny_defconfig
+++ b/arch/arm/configs/acs5k_tiny_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_KS8695=y
+CONFIG_ARCH_KS8695_CHOICE=y
 CONFIG_MACH_ACS5K=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
index 2afdf67..0f0389c 100644
--- a/arch/arm/configs/afeb9260_defconfig
+++ b/arch/arm/configs/afeb9260_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_AFEB9260=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig
index 212ead3..afe2f08 100644
--- a/arch/arm/configs/ag5evm_defconfig
+++ b/arch/arm/configs/ag5evm_defconfig
@@ -15,7 +15,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_AG5EVM=y
 CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
index f0dea52..7069340 100644
--- a/arch/arm/configs/am200epdkit_defconfig
+++ b/arch/arm/configs/am200epdkit_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_GUMSTIX=y
 CONFIG_PCCARD=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
index 2eef85e..8b82ed3 100644
--- a/arch/arm/configs/ap4evb_defconfig
+++ b/arch/arm/configs/ap4evb_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_SH7372=y
 CONFIG_MACH_AP4EVB=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 7d87184..46072fd 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
index 558ecd8..b2deaf9 100644
--- a/arch/arm/configs/assabet_defconfig
+++ b/arch/arm/configs/assabet_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_ASSABET=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_SA1100=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 67bc571..fb42cd3 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_SOC_AT91SAM9260=y
 CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index d54e2ac..cfde6c2 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91RM9200=y
 CONFIG_MACH_ONEARM=y
 CONFIG_ARCH_AT91RM9200DK=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 505b376..8206d1c 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_ARCH_AT91SAM9260_SAM9XE=y
 CONFIG_MACH_AT91SAM9260EK=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_defconfig
index ade6b2f..2e2e559 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 1cf9626..287de20 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
 CONFIG_MACH_USB_A9263=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 994d331..fbe6f40 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_AT91SAM9G20EK=y
 CONFIG_MACH_AT91SAM9G20EK_2MMC=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 606d48f..85f2743 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
 CONFIG_MACH_AT91SAM_DT=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index ad562ee..0f8f9b3 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9RL=y
 CONFIG_MACH_AT91SAM9RLEK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
index c55e921..42acdab 100644
--- a/arch/arm/configs/at91x40_defconfig
+++ b/arch/arm/configs/at91x40_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 # CONFIG_MMU is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91X40=y
 CONFIG_MACH_AT91EB01=y
 CONFIG_AT91_EARLY_USART0=y
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 5b54abb..e657c9e 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -3,7 +3,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
 CONFIG_MODVERSIONS=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_BADGE4=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
index 9e6a8fe..7fabe55 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -20,7 +20,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
+CONFIG_ARCH_BCMRING_CHOICE=y
 CONFIG_BCM_ZRELADDR=0x8000
 CONFIG_CPU_32v6K=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
index 5457108..c1bf7ba 100644
--- a/arch/arm/configs/bonito_defconfig
+++ b/arch/arm/configs/bonito_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_BONITO=y
 # CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
index cedc92e..f692e00 100644
--- a/arch/arm/configs/cam60_defconfig
+++ b/arch/arm/configs/cam60_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_CAM60=y
 CONFIG_ZBOOT_ROM_BSS=0x20004000
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index dce912d..f728b36 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -5,7 +5,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_CERF=y
 CONFIG_SA1100_CERF_FLASH_16MB=y
 CONFIG_PCCARD=m
diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
index a93ff8d..069fe65 100644
--- a/arch/arm/configs/cm_x2xx_defconfig
+++ b/arch/arm/configs/cm_x2xx_defconfig
@@ -13,7 +13,7 @@ CONFIG_EXPERT=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_ARMCORE=y
 CONFIG_PCI=y
 CONFIG_PCCARD=m
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index f4b7672..65be1f6 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_MACH_CM_X300=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index 313627a..eeefbdd 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -19,7 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_IOSCHED_CFQ=m
-CONFIG_ARCH_CNS3XXX=y
+CONFIG_ARCH_CNS3XXX_CHOICE=y
 CONFIG_MACH_CNS3420VB=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
index 2ef2c5e..7e543e1 100644
--- a/arch/arm/configs/colibri_pxa270_defconfig
+++ b/arch/arm/configs/colibri_pxa270_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_COLIBRI=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
index b985334..44b61a595 100644
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ b/arch/arm/configs/colibri_pxa300_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_COLIBRI300=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttyS0,115200 rw"
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 6c56ad0..2efaad1 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -10,7 +10,7 @@ CONFIG_EXPERT=y
 CONFIG_SLOB=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_COLLIE=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_SA1100=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e53c475..9a925e8 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_PXA_SHARPSL=y
 CONFIG_MACH_POODLE=y
 CONFIG_MACH_CORGI=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
index bbf729e..93b387d 100644
--- a/arch/arm/configs/cpu9260_defconfig
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_CPU9260=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
index e7d7942..544b25d 100644
--- a/arch/arm/configs/cpu9g20_defconfig
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_CPU9G20=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 88ccde0..f546dba 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_DAVINCI=y
+CONFIG_ARCH_DAVINCI_CHOICE=y
 CONFIG_ARCH_DAVINCI_DA830=y
 CONFIG_ARCH_DAVINCI_DA850=y
 CONFIG_MACH_MITYOMAPL138=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 67b5abb6..aeed63e 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_DAVINCI=y
+CONFIG_ARCH_DAVINCI_CHOICE=y
 CONFIG_ARCH_DAVINCI_DM644x=y
 CONFIG_ARCH_DAVINCI_DM355=y
 CONFIG_ARCH_DAVINCI_DM646x=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 40db34c..24988f7 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -6,7 +6,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_DOVE=y
+CONFIG_ARCH_DOVE_CHOICE=y
 CONFIG_MACH_DOVE_DB=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/ebsa110_defconfig b/arch/arm/configs/ebsa110_defconfig
index 14559db..016261c 100644
--- a/arch/arm/configs/ebsa110_defconfig
+++ b/arch/arm/configs/ebsa110_defconfig
@@ -4,7 +4,7 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
-CONFIG_ARCH_EBSA110=y
+CONFIG_ARCH_EBSA110_CHOICE=y
 CONFIG_PCCARD=m
 CONFIG_I82365=m
 CONFIG_LEDS=y
diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig
index d52ded35..5dc3398 100644
--- a/arch/arm/configs/edb7211_defconfig
+++ b/arch/arm/configs/edb7211_defconfig
@@ -4,7 +4,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_CLPS711X_CHOICE=y
 CONFIG_ARCH_EDB7211=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
index 60a21e0..1ae64d2 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/em_x270_defconfig
@@ -13,7 +13,7 @@ CONFIG_EXPERT=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_EM_X270=y
 CONFIG_MACH_EXEDA=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 8e97b2f..2e74fae 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_EP93XX=y
+CONFIG_ARCH_EP93XX_CHOICE=y
 CONFIG_CRUNCH=y
 CONFIG_MACH_ADSSPHERE=y
 CONFIG_MACH_EDB9301=y
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index d68ac67..ded7fd6 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -12,7 +12,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_PXA_ESERIES=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_IWMMXT=y
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
index bffe68e..dd1d584 100644
--- a/arch/arm/configs/exynos4_defconfig
+++ b/arch/arm/configs/exynos4_defconfig
@@ -4,7 +4,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS_CHOICE=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDKC210=y
 CONFIG_MACH_ARMLEX4210=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index e40b435..cd76c19 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -8,10 +8,10 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_EFI_PARTITION=y
-CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS_CHOICE=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_S3C24XX_PWM=y
-CONFIG_ARCH_EXYNOS5=y
+CONFIG_ARCH_EXYNOS5_CHOICE=y
 CONFIG_MACH_EXYNOS4_DT=y
 CONFIG_MACH_EXYNOS5_DT=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index d95763d..c33b4d0 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_PXA_EZX=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
index 038518a..557867a 100644
--- a/arch/arm/configs/footbridge_defconfig
+++ b/arch/arm/configs/footbridge_defconfig
@@ -6,7 +6,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_HOTPLUG is not set
 CONFIG_MODULES=y
-CONFIG_ARCH_FOOTBRIDGE=y
+CONFIG_ARCH_FOOTBRIDGE_CHOICE=y
 CONFIG_ARCH_CATS=y
 CONFIG_ARCH_PERSONAL_SERVER=y
 CONFIG_ARCH_EBSA285_HOST=y
diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig
index 840fced..aa5652b 100644
--- a/arch/arm/configs/fortunet_defconfig
+++ b/arch/arm/configs/fortunet_defconfig
@@ -4,7 +4,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_HOTPLUG is not set
-CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_CLPS711X_CHOICE=y
 CONFIG_ARCH_FORTUNET=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/g3evm_defconfig b/arch/arm/configs/g3evm_defconfig
index 4a336ab..4299600 100644
--- a/arch/arm/configs/g3evm_defconfig
+++ b/arch/arm/configs/g3evm_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_SH7367=y
 CONFIG_MACH_G3EVM=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/g4evm_defconfig b/arch/arm/configs/g4evm_defconfig
index 21c6d03..e5fa444 100644
--- a/arch/arm/configs/g4evm_defconfig
+++ b/arch/arm/configs/g4evm_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_SH7377=y
 CONFIG_MACH_G4EVM=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index 317960f..65009de 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_H3600=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_SA1100=y
diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
index 37903e3..94cc67d 100644
--- a/arch/arm/configs/h5000_defconfig
+++ b/arch/arm/configs/h5000_defconfig
@@ -12,7 +12,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_H5000=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/h7201_defconfig b/arch/arm/configs/h7201_defconfig
index bee94d2..8404e5e 100644
--- a/arch/arm/configs/h7201_defconfig
+++ b/arch/arm/configs/h7201_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
+CONFIG_ARCH_H720X_CHOICE=y
 CONFIG_ARCH_H7201=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index 69405a7..768f654 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
+CONFIG_ARCH_H720X_CHOICE=y
 CONFIG_ARCH_H7202=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index bed8047..7d2c376 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_HACKKIT=y
 CONFIG_LEDS=y
 CONFIG_LEDS_CPU=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index fd996bb..6b574fd 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -16,7 +16,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_INTELMOTE2=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 78ed575..21fdab3 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MXC_CHOICE=y
 CONFIG_ARCH_IMX_V4_V5=y
 CONFIG_ARCH_MX1ADS=y
 CONFIG_MACH_SCB9328=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3c9f32f..cf959d2 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -16,7 +16,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MXC_CHOICE=y
 CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_PCM037=y
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index a8314c3..c3cfc4b 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -7,7 +7,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_INTEGRATOR=y
+CONFIG_ARCH_INTEGRATOR_CHOICE=y
 CONFIG_ARCH_INTEGRATOR_AP=y
 CONFIG_ARCH_INTEGRATOR_CP=y
 CONFIG_CPU_ARM720T=y
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
index 4fa94a1..5c0b6ec 100644
--- a/arch/arm/configs/iop13xx_defconfig
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_IOP13XX=y
+CONFIG_ARCH_IOP13XX_CHOICE=y
 CONFIG_MACH_IQ81340SC=y
 CONFIG_MACH_IQ81340MC=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 4f2ec3a..92ba2c7 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_IOP32X=y
+CONFIG_ARCH_IOP32X_CHOICE=y
 CONFIG_MACH_GLANTANK=y
 CONFIG_ARCH_IQ80321=y
 CONFIG_ARCH_IQ31244=y
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index aa36128..ea381ec 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_IOP33X=y
+CONFIG_ARCH_IOP33X_CHOICE=y
 CONFIG_ARCH_IQ80331=y
 CONFIG_MACH_IQ80332=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index 063e2ab..663f522 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -7,7 +7,7 @@ CONFIG_EXPERT=y
 CONFIG_MODULES=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_IXP4XX=y
+CONFIG_ARCH_IXP4XX_CHOICE=y
 CONFIG_MACH_NSLU2=y
 CONFIG_MACH_AVILA=y
 CONFIG_MACH_LOFT=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index ea80e7e..83e38b1 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -4,7 +4,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_JORNADA720=y
 CONFIG_SA1100_JORNADA720_SSP=y
 CONFIG_PCCARD=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af5..accc8db 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -7,7 +7,7 @@ CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_KIRKWOOD=y
+CONFIG_ARCH_KIRKWOOD_CHOICE=y
 CONFIG_MACH_DB88F6281_BP=y
 CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
index b7735d6..3b73777 100644
--- a/arch/arm/configs/kota2_defconfig
+++ b/arch/arm/configs/kota2_defconfig
@@ -17,7 +17,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KOTA2=y
diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig
index 47c4883..f795954 100644
--- a/arch/arm/configs/ks8695_defconfig
+++ b/arch/arm/configs/ks8695_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_KS8695=y
+CONFIG_ARCH_KS8695_CHOICE=y
 CONFIG_MACH_KS8695=y
 CONFIG_MACH_DSM320=y
 # CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 26146ff..5ce2ba4 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -12,7 +12,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_MACH_KZM9D=y
 CONFIG_MEMORY_START=0x40000000
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c86..5490470 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -21,7 +21,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KZM9G=y
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig
index faa2865..68e03f9 100644
--- a/arch/arm/configs/lart_defconfig
+++ b/arch/arm/configs/lart_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_LART=y
 CONFIG_LEDS=y
 CONFIG_LEDS_CPU=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index e42a0e3..d219a20 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -17,7 +17,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_ARCH_LPC32XX=y
+CONFIG_ARCH_LPC32XX_CHOICE=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index 1c8c9ee..12ee552 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SLAB=y
 CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_LOGICPD_PXA270=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index c4ba274..617271e 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_LUBBOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 306a2e2..7ca4ffa 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_SH7372=y
 CONFIG_MACH_MACKEREL=y
 CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index a691ef4..2e402f4 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -12,7 +12,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_H4700=y
 CONFIG_MACH_MAGICIAN=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index 04efa1b..e90b18e 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_MAINSTONE=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_LEDS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 864f9a5..46c2a50 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 # CONFIG_BLOCK is not set
-CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SHMOBILE_CHOICE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
 CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 082175c..828a920 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_ARCH_S3C24XX=y
+CONFIG_ARCH_S3C24XX_CHOICE=y
 # CONFIG_CPU_S3C2410 is not set
 CONFIG_CPU_S3C2440=y
 CONFIG_S3C_ADC=y
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 5a58452..c5e0355 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MMP=y
+CONFIG_ARCH_MMP_CHOICE=y
 CONFIG_MACH_BROWNSTONE=y
 CONFIG_MACH_FLINT=y
 CONFIG_MACH_MARVELL_JASPER=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index 2b8f7af..77218bd 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -6,7 +6,7 @@ CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MSM=y
+CONFIG_ARCH_MSM_CHOICE=y
 CONFIG_MACH_HALIBUT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 7305ebd..f2200bc 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -11,7 +11,7 @@ CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MV78XX0=y
+CONFIG_ARCH_MV78XX0_CHOICE=y
 CONFIG_MACH_DB78X00_BP=y
 CONFIG_MACH_RD78X00_MASA=y
 CONFIG_MACH_TERASTATION_WXL=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31..76f2486 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -8,7 +8,7 @@ CONFIG_EXPERT=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_MVEBU_CHOICE=y
 CONFIG_MACH_ARMADA_370_XP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4edcfb4..a64a406 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -21,7 +21,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXS=y
+CONFIG_ARCH_MXS_CHOICE=y
 CONFIG_MACH_MXS_DT=y
 CONFIG_MACH_MX23EVK=y
 CONFIG_MACH_MX28EVK=y
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index d7dc992..ee6b316 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -4,7 +4,7 @@ CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_ASSABET=y
 CONFIG_ASSABET_NEPONSET=y
 CONFIG_PCCARD=y
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index 25ed772..e9bcdc3 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -1,7 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_ARCH_FOOTBRIDGE=y
+CONFIG_ARCH_FOOTBRIDGE_CHOICE=y
 CONFIG_ARCH_NETWINDER=y
 CONFIG_LEDS=y
 CONFIG_LEDS_CPU=y
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 9c0ad79..4d036c9 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -8,7 +8,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_NETX=y
+CONFIG_ARCH_NETX_CHOICE=y
 CONFIG_MACH_NXDKN=y
 CONFIG_MACH_NXDB500=y
 CONFIG_MACH_NXEB500HMI=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index bf123c5..2e327e0 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_NOMADIK=y
+CONFIG_ARCH_NOMADIK_CHOICE=y
 CONFIG_MACH_NOMADIK_8815NHK=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig
index 10180cf..4d05295 100644
--- a/arch/arm/configs/nuc910_defconfig
+++ b/arch/arm/configs/nuc910_defconfig
@@ -8,7 +8,7 @@ CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_SLAB=y
-CONFIG_ARCH_W90X900=y
+CONFIG_ARCH_W90X900_CHOICE=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig
index 27aa873..846fd11 100644
--- a/arch/arm/configs/nuc950_defconfig
+++ b/arch/arm/configs/nuc950_defconfig
@@ -8,7 +8,7 @@ CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_SLAB=y
-CONFIG_ARCH_W90X900=y
+CONFIG_ARCH_W90X900_CHOICE=y
 # CONFIG_MACH_W90P910EVB is not set
 CONFIG_MACH_W90P950EVB=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig
index 56fd7ad..3ec4197 100644
--- a/arch/arm/configs/nuc960_defconfig
+++ b/arch/arm/configs/nuc960_defconfig
@@ -8,7 +8,7 @@ CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_SLAB=y
-CONFIG_ARCH_W90X900=y
+CONFIG_ARCH_W90X900_CHOICE=y
 # CONFIG_MACH_W90P910EVB is not set
 CONFIG_MACH_W90N960EVB=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index dde2a1a..43e9487 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -22,7 +22,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_CHOICE=y
 CONFIG_ARCH_OMAP1=y
 CONFIG_OMAP_RESET_CLOCKS=y
 # CONFIG_OMAP_MUX is not set
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index e58edc3..7d959cd 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -20,7 +20,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP_CHOICE=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
 CONFIG_ARM_THUMBEE=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index a288d70..cad9bd5 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -10,7 +10,7 @@ CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_ORION5X=y
+CONFIG_ARCH_ORION5X_CHOICE=y
 CONFIG_MACH_DB88F5281=y
 CONFIG_MACH_RD88F5182=y
 CONFIG_MACH_KUROBOX_PRO=y
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
index 4baa83c..67cff48 100644
--- a/arch/arm/configs/palmz72_defconfig
+++ b/arch/arm/configs/palmz72_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_PXA_PALM=y
 # CONFIG_MACH_PALMTX is not set
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
index 2f136c3..521caef 100644
--- a/arch/arm/configs/pcm027_defconfig
+++ b/arch/arm/configs/pcm027_defconfig
@@ -16,7 +16,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_PCM027=y
 CONFIG_MACH_PCM990_BASEBOARD=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index cb08cc5..703751e 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -9,7 +9,7 @@ CONFIG_EXPERT=y
 CONFIG_MODULES=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_PLEB=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index 35a31cc..87e705d 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -12,7 +12,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
+CONFIG_ARCH_PNX4008_CHOICE=y
 CONFIG_PREEMPT=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index c328ac6..e23ebd2 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
+CONFIG_ARCH_PRIMA2_CHOICE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
index 74d7e01..f479d22 100644
--- a/arch/arm/configs/pxa168_defconfig
+++ b/arch/arm/configs/pxa168_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MMP=y
+CONFIG_ARCH_MMP_CHOICE=y
 CONFIG_MACH_ASPENITE=y
 CONFIG_MACH_ZYLONITE2=y
 CONFIG_MACH_AVENGERS_LITE=y
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
index 917a070..e836371 100644
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ b/arch/arm/configs/pxa255-idp_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_MODULES=y
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_PXA_IDP=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_LEDS=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 1677a06..0da136d 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -7,7 +7,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_LITTLETON=y
 CONFIG_MACH_TAVOREVB=y
 CONFIG_MACH_SAAR=y
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
index 1cd381e..73a3c23 100644
--- a/arch/arm/configs/pxa910_defconfig
+++ b/arch/arm/configs/pxa910_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MMP=y
+CONFIG_ARCH_MMP_CHOICE=y
 CONFIG_MACH_TAVOREVB=y
 CONFIG_MACH_TTC_DKB=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index 9160f3b..446403b 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_QIL_A9260=y
 CONFIG_AT91_SLOW_CLOCK=y
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig
index f7caa90..062fbcd 100644
--- a/arch/arm/configs/raumfeld_defconfig
+++ b/arch/arm/configs/raumfeld_defconfig
@@ -5,7 +5,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_RAUMFELD_RC=y
 CONFIG_MACH_RAUMFELD_CONNECTOR=y
 CONFIG_MACH_RAUMFELD_SPEAKER=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index abe61bf..8080936 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_REALVIEW=y
+CONFIG_ARCH_REALVIEW_CHOICE=y
 CONFIG_MACH_REALVIEW_EB=y
 CONFIG_REALVIEW_EB_ARM11MP=y
 CONFIG_MACH_REALVIEW_PB11MP=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 7079cbe..4114be5 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_REALVIEW=y
+CONFIG_ARCH_REALVIEW_CHOICE=y
 CONFIG_MACH_REALVIEW_EB=y
 CONFIG_REALVIEW_EB_ARM11MP=y
 CONFIG_MACH_REALVIEW_PB11MP=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 00515ef..e57d7af 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -7,7 +7,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_RPC=y
+CONFIG_ARCH_RPC_CHOICE=y
 CONFIG_CPU_SA110=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 193448f..80b7757 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_S3C24XX=y
+CONFIG_ARCH_S3C24XX_CHOICE=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index ba6a515..72cd97a 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -5,7 +5,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C64XX=y
+CONFIG_ARCH_S3C64XX_CHOICE=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_MACH_SMDK6400=y
 CONFIG_MACH_ANW6410=y
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
index ad6b61b..32edf95 100644
--- a/arch/arm/configs/s5p64x0_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -5,7 +5,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5P64X0=y
+CONFIG_ARCH_S5P64X0_CHOICE=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDK6440=y
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
index 41bafc9..eb6dbd7 100644
--- a/arch/arm/configs/s5pc100_defconfig
+++ b/arch/arm/configs/s5pc100_defconfig
@@ -5,7 +5,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5PC100=y
+CONFIG_ARCH_S5PC100_CHOICE=y
 CONFIG_MACH_SMDKC100=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index fa98990..5176dac59 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -5,7 +5,7 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5PV210=y
+CONFIG_ARCH_S5PV210_CHOICE=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_S3C_DEV_FB=y
 CONFIG_S5PV210_SETUP_FB_24BPP=y
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index ecf2531..18d831b 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -9,7 +9,7 @@ CONFIG_LOG_BUF_SHIFT=15
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_SAM9_L9260=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig
index b0b9694..b64afb0 100644
--- a/arch/arm/configs/shannon_defconfig
+++ b/arch/arm/configs/shannon_defconfig
@@ -3,7 +3,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_SHANNON=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_SA1100=y
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index caa07db..6579d28 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -8,7 +8,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_SHARK=y
+CONFIG_ARCH_SHARK_CHOICE=y
 CONFIG_LEDS=y
 CONFIG_LEDS_TIMER=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index d335815..e3bbdf9 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -6,7 +6,7 @@ CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
-CONFIG_ARCH_SA1100=y
+CONFIG_ARCH_SA1100_CHOICE=y
 CONFIG_SA1100_SIMPAD=y
 CONFIG_PCCARD=y
 CONFIG_PCMCIA_SA1100=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0ac1293..89023b6 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SOCFPGA=y
+CONFIG_ARCH_SOCFPGA_CHOICE=y
 CONFIG_MACH_SOCFPGA_CYCLONE5=y
 CONFIG_ARM_THUMBEE=y
 # CONFIG_CACHE_L2X0 is not set
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 1fdb826..ea4069c 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR13XX=y
+CONFIG_ARCH_SPEAR13XX_CHOICE=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 # CONFIG_SWP_EMULATE is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index a2a1265..a82ba96 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR6XX=y
+CONFIG_ARCH_SPEAR6XX_CHOICE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index 7015827..35667a0 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_PXA_SHARPSL=y
 CONFIG_MACH_AKITA=y
 CONFIG_MACH_BORZOI=y
diff --git a/arch/arm/configs/stamp9g20_defconfig b/arch/arm/configs/stamp9g20_defconfig
index d5e260b..23da280 100644
--- a/arch/arm/configs/stamp9g20_defconfig
+++ b/arch/arm/configs/stamp9g20_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9G20=y
 CONFIG_MACH_PORTUXG20=y
 CONFIG_MACH_STAMP9G20=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 71277a1..d618ae2 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -14,7 +14,7 @@ CONFIG_SLOB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C24XX=y
+CONFIG_ARCH_S3C24XX_CHOICE=y
 CONFIG_MACH_TCT_HAMMER=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db22453..24c16fa 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -23,7 +23,7 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_CHOICE=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_HARMONY=y
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
index 3162173..7433db3 100644
--- a/arch/arm/configs/trizeps4_defconfig
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_TRIZEPS_PXA=y
 CONFIG_MACH_TRIZEPS4=y
 CONFIG_PCCARD=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000e..2a0b97d 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_U300=y
+CONFIG_ARCH_U300_CHOICE=y
 CONFIG_MACH_U300=y
 CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d4f661..35aa6dc 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -7,7 +7,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_U8500=y
+CONFIG_ARCH_U8500_CHOICE=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
index 2e39f38..d2c5d90 100644
--- a/arch/arm/configs/usb-a9260_defconfig
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91_CHOICE=y
 CONFIG_ARCH_AT91SAM9260=y
 CONFIG_MACH_USB_A9260=y
 CONFIG_AT91_SLOW_CLOCK=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index f2de51f..75c85ad 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -21,7 +21,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CHOICE=y
 CONFIG_ARCH_VEXPRESS_CA9X4=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_SMP=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index 1d01ddd..2e9d898 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -11,7 +11,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_ARCH_VIPER=y
 CONFIG_IWMMXT=y
 CONFIG_PCCARD=m
diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig
index 721832f..3136636 100644
--- a/arch/arm/configs/xcep_defconfig
+++ b/arch/arm/configs/xcep_defconfig
@@ -20,7 +20,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLOCK is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_XCEP=y
 CONFIG_IWMMXT=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index 547a3c1..4a1b536 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -6,7 +6,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_PXA=y
+CONFIG_ARCH_PXA_CHOICE=y
 CONFIG_MACH_ARCOM_ZEUS=y
 CONFIG_PCCARD=m
 CONFIG_PCMCIA_PXA2XX=m
-- 
1.7.9.5



From hartleys at visionengravers.com  Wed Aug 29 19:14:08 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 29 Aug 2012 18:14:08 -0500
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <1346280600-29395-2-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F00206B1D9F2E4@AUSP01VMBX24.collaborationhost.net>

On Wednesday, August 29, 2012 3:50 PM, Rob Herring wrote:
>
> In preparation for mulit-platform support, convert all platforms' ARCH_
> definition to a hidden option and create a new choice option.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> ---
>  arch/arm/Kconfig                 |  650 ++++++++------------------------------

<snip>

> arch/arm/mach-ep93xx/Kconfig     |   11 +

<snip>

>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig

<snip>

> -config ARCH_EP93XX
> +config ARCH_EP93XX_CHOICE
>  	bool "EP93xx-based"
> -	select CPU_ARM920T
> -	select ARM_AMBA
> -	select ARM_VIC
> -	select CLKDEV_LOOKUP
> -	select ARCH_REQUIRE_GPIOLIB
> -	select ARCH_HAS_HOLES_MEMORYMODEL
> -	select ARCH_USES_GETTIMEOFFSET
> -	select NEED_MACH_MEMORY_H
> +	select ARCH_EP93XX
>  	help
>  	  This enables support for the Cirrus EP93xx series of CPUs.

<snip>

> diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
> index fe3c1fa..4cf770c 100644
> --- a/arch/arm/mach-ep93xx/Kconfig
> +++ b/arch/arm/mach-ep93xx/Kconfig
> @@ -1,3 +1,14 @@
> +config ARCH_EP93XX
> +	bool
> +	select ARCH_REQUIRE_GPIOLIB
> +	select ARCH_HAS_HOLES_MEMORYMODEL
> +	select ARCH_USES_GETTIMEOFFSET
> +	select ARM_AMBA
> +	select ARM_VIC
> +	select CLKDEV_LOOKUP
> +	select CPU_ARM920T
> +	select NEED_MACH_MEMORY_H
> +
>  if ARCH_EP93XX
 >
>  menu "Cirrus EP93xx Implementation Options"

Curious... Why did you rearrange the select's? There "almost"
alphabetic now, but not quite...

But, FWIW, for the EP93xx part:

Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>

Thanks


From hartleys at visionengravers.com  Wed Aug 29 19:18:04 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 29 Aug 2012 18:18:04 -0500
Subject: [PATCH 2/6] ARM: introduce Kconfig.mach
In-Reply-To: <1346280600-29395-3-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-3-git-send-email-robherring2@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F00206B1D9F2E7@AUSP01VMBX24.collaborationhost.net>

On Wednesday, August 29, 2012 3:50 PM, Rob Herring wrote:
>
> Move all the mach related config options into separate Kconfig.mach file.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> ---
>  arch/arm/Kconfig      |  529 +------------------------------------------------
>  arch/arm/Kconfig.mach |  528 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 529 insertions(+), 528 deletions(-)
>  create mode 100644 arch/arm/Kconfig.mach

FWIW as far as ep93xx goes..

Reviewed-by: H Hartley Sweeten <hsweeten at visionengravers.com>

Thanks


From linux at arm.linux.org.uk  Wed Aug 29 19:31:59 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 00:31:59 +0100
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <1346280600-29395-2-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
Message-ID: <20120829233159.GS18957@n2100.arm.linux.org.uk>

On Wed, Aug 29, 2012 at 05:49:55PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation for mulit-platform support, convert all platforms' ARCH_
> definition to a hidden option and create a new choice option.

This is churn and annoyance.  It's definitely annoyance for the
autobuilder because it's going to have to have symbols changed in the
seed configs. It's annoyance for people because they're going to have
to manually reselect their SoC types in every build they do.

I think also that Kconfig will end up on 'make oldconfig' selecting
one of the platforms, deselecting all the dependencies on that platform,
which then means you'll have thousands of Kconfig options to answer.

I've been there with x86 configs, and spent something like an hour
piecing together a configuration for my laptop, answering one question
every couple of seconds.  That is not a nice experience to inflict on
people.


From linux at arm.linux.org.uk  Wed Aug 29 19:37:05 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 00:37:05 +0100
Subject: [PATCH 03/10] serial: atmel: add explict mach/gpio.h include
In-Reply-To: <1346279496-26286-4-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-4-git-send-email-robherring2@gmail.com>
Message-ID: <20120829233705.GT18957@n2100.arm.linux.org.uk>

On Wed, Aug 29, 2012 at 05:31:29PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove implicit inclusion of mach/gpio.h, add explicit
> include of mach/gpio.h.

Definitely NAK.

What is in the Atmel mach/gpio.h has hardly anything to do with the
gpio subsystem (it's more a private gpio implementation).  It should
be renamed as such to make it clear (and so it doesn't trigger my
sanity filtering.)


From linux at arm.linux.org.uk  Wed Aug 29 19:38:41 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 00:38:41 +0100
Subject: [PATCH 06/10] ARM: shmobile: explicitly include mach/gpio.h
In-Reply-To: <1346279496-26286-7-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-7-git-send-email-robherring2@gmail.com>
Message-ID: <20120829233841.GU18957@n2100.arm.linux.org.uk>

On Wed, Aug 29, 2012 at 05:31:32PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove implicit inclusion of mach/gpio.h, add explict
> includes of necessary headers.
> 
> shmobile always uses gpiolib, so we can remove some of mach/gpio.h.

Given that I spent a long time getting rid of all explicit mach/gpio.h
includes to fix the madness with what definitions drivers picked up from
where, NAK.


From linux at arm.linux.org.uk  Wed Aug 29 19:40:30 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 00:40:30 +0100
Subject: [PATCH 00/10] Make mach/gpio.h optional
In-Reply-To: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
Message-ID: <20120829234030.GV18957@n2100.arm.linux.org.uk>

On Wed, Aug 29, 2012 at 05:31:26PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> This series makes mach/gpio.h optional like we have done for other mach
> headers in preparation for multi-platform kernel images. Unfortunately,
> it adds more mach includes to drivers/, but really they are just now
> explicitly included and easily found.

This in general looks like a complete backwards step rather than a forwards
step for multi-platform kernels.  All these drivers are not going to be
usable in multi-platform kernel images, because with mach/ includes they're
not going to be picking up the correct set of headers.

So all these SoC types might as well not be part of the multi-platform
project until they get their act together with their headers.


From linux at arm.linux.org.uk  Wed Aug 29 19:53:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 00:53:53 +0100
Subject: [RFC/PATCH] ARM: smp: Fix cpu_up() racing with sys_reboot
In-Reply-To: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>
References: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>
Message-ID: <20120829235353.GW18957@n2100.arm.linux.org.uk>

On Tue, Aug 21, 2012 at 09:03:49PM -0700, Stephen Boyd wrote:
> Nothing stops a process from hotplugging in a CPU concurrently
> with a sys_reboot() call. In such a situation we could have
> ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
> fact that the CPU is not really offline and call the
> CPU_UP_PREPARE notifier. When this happens stop_machine code will
> complain that the cpu thread already exists and BUG_ON().

This puts us at odds with x86, which is a bad thing without first
investigating whether a generic solution which fixes all arches would
be more appropriate.

A better solution may be to mark those CPUs as being not-present,
which will prevent them being hot-plugged back.


From mturquette at ti.com  Wed Aug 29 20:03:49 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 29 Aug 2012 17:03:49 -0700
Subject: [PATCH v4 1/3] ARM: omap: clk: add clk_prepare and clk_unprepare
In-Reply-To: <1346230576-20004-2-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-2-git-send-email-rnayak@ti.com>
Message-ID: <CAJOA=zMXK51UzrREj4mWsJVchV0N+21bbz-GV=7yGqZg+K5voQ@mail.gmail.com>

On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak <rnayak at ti.com> wrote:
> As part of Common Clk Framework (CCF) the clk_enable() operation
> was split into a clk_prepare() which could sleep, and a clk_enable()
> which should never sleep. Similarly the clk_disable() was
> split into clk_disable() and clk_unprepare(). This was
> needed to handle complex cases where in a clk gate/ungate
> would require a slow and a fast part to be implemented.
> None of the clocks below seem to be in the 'complex' clocks
> category and are just simple clocks which are enabled/disabled
> through simple register writes.
> Most of the instances also seem to be called in non-atomic
> context which means its safe to move all of those from
> using a clk_enable() to clk_prepare_enable() and clk_disable() to
> clk_disable_unprepare().
>
> For some others, mainly the ones handled through the hwmod framework
> there is a possibility that they get called in either an atomic
> or a non-atomic context.
>
> The way these get handled below work only as long as clk_prepare
> is implemented as a no-op (which is the case today) since this gets
> called very early at boot while most subsystems are unavailable.
> Hence these are marked with a *HACK* comment, which says we need
> to re-visit these once we start doing something meaningful with
> clk_prepare/clk_unprepare like doing voltage scaling or something
> that involves i2c.
>
> This is in preparation of OMAP moving to CCF.
>
> Based on initial changes from Mike turquette.
>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>

Looks good to me.

Reviewed-by: Mike Turquette <mturquette at linaro.org>

> ---
>  arch/arm/mach-omap2/board-apollon.c    |    4 ++--
>  arch/arm/mach-omap2/board-h4.c         |    6 +++---
>  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
>  arch/arm/mach-omap2/clock3xxx.c        |    8 ++++----
>  arch/arm/mach-omap2/display.c          |    4 ++--
>  arch/arm/mach-omap2/gpmc.c             |    2 +-
>  arch/arm/mach-omap2/omap_hwmod.c       |   27 +++++++++++++++++++++++++++
>  7 files changed, 40 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
> index e5fa46b..25e8f2f 100644
> --- a/arch/arm/mach-omap2/board-apollon.c
> +++ b/arch/arm/mach-omap2/board-apollon.c
> @@ -204,7 +204,7 @@ static inline void __init apollon_init_smc91x(void)
>                 return;
>         }
>
> -       clk_enable(gpmc_fck);
> +       clk_prepare_enable(gpmc_fck);
>         rate = clk_get_rate(gpmc_fck);
>
>         eth_cs = APOLLON_ETH_CS;
> @@ -248,7 +248,7 @@ static inline void __init apollon_init_smc91x(void)
>                 gpmc_cs_free(APOLLON_ETH_CS);
>         }
>  out:
> -       clk_disable(gpmc_fck);
> +       clk_disable_unprepare(gpmc_fck);
>         clk_put(gpmc_fck);
>  }
>
> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
> index ace2048..bd08bef 100644
> --- a/arch/arm/mach-omap2/board-h4.c
> +++ b/arch/arm/mach-omap2/board-h4.c
> @@ -266,9 +266,9 @@ static inline void __init h4_init_debug(void)
>                 return;
>         }
>
> -       clk_enable(gpmc_fck);
> +       clk_prepare_enable(gpmc_fck);
>         rate = clk_get_rate(gpmc_fck);
> -       clk_disable(gpmc_fck);
> +       clk_disable_unprepare(gpmc_fck);
>         clk_put(gpmc_fck);
>
>         if (is_gpmc_muxed())
> @@ -312,7 +312,7 @@ static inline void __init h4_init_debug(void)
>                 gpmc_cs_free(eth_cs);
>
>  out:
> -       clk_disable(gpmc_fck);
> +       clk_disable_unprepare(gpmc_fck);
>         clk_put(gpmc_fck);
>  }
>
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index 70f6d1d..86c2201 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -172,7 +172,7 @@ static void __init omap4_ehci_init(void)
>                 return;
>         }
>         clk_set_rate(phy_ref_clk, 19200000);
> -       clk_enable(phy_ref_clk);
> +       clk_prepare_enable(phy_ref_clk);
>
>         /* disable the power to the usb hub prior to init and reset phy+hub */
>         ret = gpio_request_array(panda_ehci_gpios,
> diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
> index 794d827..4c1591a 100644
> --- a/arch/arm/mach-omap2/clock3xxx.c
> +++ b/arch/arm/mach-omap2/clock3xxx.c
> @@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void)
>
>         dpll5_clk = clk_get(NULL, "dpll5_ck");
>         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
> -       clk_enable(dpll5_clk);
> +       clk_prepare_enable(dpll5_clk);
>
>         /* Program dpll5_m2_clk divider for no division */
>         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
> -       clk_enable(dpll5_m2_clk);
> +       clk_prepare_enable(dpll5_m2_clk);
>         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
>
> -       clk_disable(dpll5_m2_clk);
> -       clk_disable(dpll5_clk);
> +       clk_disable_unprepare(dpll5_m2_clk);
> +       clk_disable_unprepare(dpll5_clk);
>         return;
>  }
>
> diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
> index af1ed7d..5a3afd2 100644
> --- a/arch/arm/mach-omap2/display.c
> +++ b/arch/arm/mach-omap2/display.c
> @@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
>
>         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
>                 if (oc->_clk)
> -                       clk_enable(oc->_clk);
> +                       clk_prepare_enable(oc->_clk);
>
>         dispc_disable_outputs();
>
> @@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
>
>         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
>                 if (oc->_clk)
> -                       clk_disable(oc->_clk);
> +                       clk_disable_unprepare(oc->_clk);
>
>         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
>
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index b2b5759..a14d650c 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -750,7 +750,7 @@ static int __init gpmc_init(void)
>                 BUG();
>         }
>
> -       clk_enable(gpmc_l3_clk);
> +       clk_prepare_enable(gpmc_l3_clk);
>
>         l = gpmc_read_reg(GPMC_REVISION);
>         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 6ca8e51..fb3e110 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -683,6 +683,15 @@ static int _init_main_clk(struct omap_hwmod *oh)
>                            oh->name, oh->main_clk);
>                 return -EINVAL;
>         }
> +       /*
> +        * HACK: This needs a re-visit once clk_prepare() is implemented
> +        * to do something meaningful. Today its just a no-op.
> +        * If clk_prepare() is used at some point to do things like
> +        * voltage scaling etc, then this would have to be moved to
> +        * some point where subsystems like i2c and pmic become
> +        * available.
> +        */
> +       clk_prepare(oh->_clk);
>
>         if (!oh->_clk->clkdm)
>                 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
> @@ -720,6 +729,15 @@ static int _init_interface_clks(struct omap_hwmod *oh)
>                         ret = -EINVAL;
>                 }
>                 os->_clk = c;
> +               /*
> +                * HACK: This needs a re-visit once clk_prepare() is implemented
> +                * to do something meaningful. Today its just a no-op.
> +                * If clk_prepare() is used at some point to do things like
> +                * voltage scaling etc, then this would have to be moved to
> +                * some point where subsystems like i2c and pmic become
> +                * available.
> +                */
> +               clk_prepare(os->_clk);
>         }
>
>         return ret;
> @@ -747,6 +765,15 @@ static int _init_opt_clks(struct omap_hwmod *oh)
>                         ret = -EINVAL;
>                 }
>                 oc->_clk = c;
> +               /*
> +                * HACK: This needs a re-visit once clk_prepare() is implemented
> +                * to do something meaningful. Today its just a no-op.
> +                * If clk_prepare() is used at some point to do things like
> +                * voltage scaling etc, then this would have to be moved to
> +                * some point where subsystems like i2c and pmic become
> +                * available.
> +                */
> +               clk_prepare(oc->_clk);
>         }
>
>         return ret;
> --
> 1.7.9.5
>


From linux at arm.linux.org.uk  Wed Aug 29 20:08:49 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 01:08:49 +0100
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <1346230576-20004-3-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
Message-ID: <20120830000849.GD25765@n2100.arm.linux.org.uk>

On Wed, Aug 29, 2012 at 02:26:15PM +0530, Rajendra Nayak wrote:
> Moving to Common clk framework for OMAP would mean we no longer use
> internal lookup mechanism like omap_clk_get_by_name().
> get rid of all its usage mostly from hwmod and omap_device
> code.
> 
> Also use IS_ERR_OR_NULL() for error checking.

This is wrong.  IS_ERR() is the only check you should ever use with clk_get().


From mturquette at ti.com  Wed Aug 29 20:15:02 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 29 Aug 2012 17:15:02 -0700
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <1346230576-20004-3-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
Message-ID: <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>

On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak <rnayak at ti.com> wrote:
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index d7f55e4..a3831a2 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
>         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
>         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
>         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
> +       CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
>         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),

Is it right to re-use dss_fck for the "ick" here?  I think it is due
to omap4 modulemode stuff but I don't have DM in front of me and
wanted a double-check...

Regards,
Mike


From tony at atomide.com  Wed Aug 29 19:20:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 29 Aug 2012 16:20:27 -0700
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
In-Reply-To: <B1BA3B0F-098D-4AC8-A514-6862D0F98EC6@ti.com>
References: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
 <CAN5iSWp9LJjC9B3fiAJhuYVkfNzC98WkvQKPiVt8+tqxr==COg@mail.gmail.com>
 <CAGF5oy_-3g3A8Eadn7uRm5srPCsuufFZ42estfRuAWy4JiqQ-w@mail.gmail.com>
 <CAGF5oy9hf8ys=Cqvhto8tPnW=iuf2V3sRmJW+aoAmZS4Sdroyg@mail.gmail.com>
 <B1BA3B0F-098D-4AC8-A514-6862D0F98EC6@ti.com>
Message-ID: <20120829232026.GD1303@atomide.com>

* Locke, Matthew <mlocke at ti.com> [120829 15:08]:
> During lunch

Oops I'm already heading back home today. But you guys have
a fun BoF!

Tony


From fernando.lugo at ti.com  Wed Aug 29 20:24:52 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Wed, 29 Aug 2012 19:24:52 -0500
Subject: [PATCH] rpmsg: use right device paramter when calling
 dma_free_coherent function
Message-ID: <1346286292-21773-1-git-send-email-fernando.lugo@ti.com>

dma_alloc/free_coherent APIs requires the platform specific remoteproc
device as the device parameter. We are passing vdev->dev.parent to the
dma_free_coherent function which is the generic rproc device and it is
wrong, it has to be vdev->dev.parent->parent instead, same as when we
call dma_alloc_coherent function.

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 drivers/rpmsg/virtio_rpmsg_bus.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/rpmsg/virtio_rpmsg_bus.c b/drivers/rpmsg/virtio_rpmsg_bus.c
index 590cfaf..1859f71 100644
--- a/drivers/rpmsg/virtio_rpmsg_bus.c
+++ b/drivers/rpmsg/virtio_rpmsg_bus.c
@@ -1008,8 +1008,8 @@ static int rpmsg_probe(struct virtio_device *vdev)
 	return 0;
 
 free_coherent:
-	dma_free_coherent(vdev->dev.parent, RPMSG_TOTAL_BUF_SPACE, bufs_va,
-					vrp->bufs_dma);
+	dma_free_coherent(vdev->dev.parent->parent, RPMSG_TOTAL_BUF_SPACE,
+					bufs_va, vrp->bufs_dma);
 vqs_del:
 	vdev->config->del_vqs(vrp->vdev);
 free_vrp:
@@ -1043,7 +1043,7 @@ static void __devexit rpmsg_remove(struct virtio_device *vdev)
 
 	vdev->config->del_vqs(vrp->vdev);
 
-	dma_free_coherent(vdev->dev.parent, RPMSG_TOTAL_BUF_SPACE,
+	dma_free_coherent(vdev->dev.parent->parent, RPMSG_TOTAL_BUF_SPACE,
 					vrp->rbufs, vrp->bufs_dma);
 
 	kfree(vrp);
-- 
1.7.1



From kyungmin.park at samsung.com  Wed Aug 29 20:54:01 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Thu, 30 Aug 2012 09:54:01 +0900
Subject: [PATCH 0/6] ARM: EXYNOS: Add support for Trats board using device
 tree
In-Reply-To: <1346245980-2658-1-git-send-email-t.figa@samsung.com>
References: <1346245980-2658-1-git-send-email-t.figa@samsung.com>
Message-ID: <040101cd8649$f1dab7f0$d59027d0$%park@samsung.com>

+ Thomas Abraham,

> -----Original Message-----
> From: Tomasz Figa [mailto:t.figa at samsung.com]
> Sent: Wednesday, August 29, 2012 10:13 PM
> To: linux-samsung-soc at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; kyungmin.park at samsung.com;
> kgene.kim at samsung.com; jy0922.shim at samsung.com; Tomasz Figa
> Subject: [PATCH 0/6] ARM: EXYNOS: Add support for Trats board using device
> tree
> 
> This patch series adds basic device tree support for Samsung Trats board
> along with any necessary prerequisites.
> 
> In addition it refactors Exynos4 dts include files to split parts common
> to
> the whole Exynos4 part from parts specific to Exynos4210 to allow further
> extension of Exynos4210 dts include file and addition of include files for
> other SoCs from Exynos4 line.
> 
> Dependencies:
> -> [PATCH v5] mmc: sdhci-s3c: Add device tree support
> http://www.spinics.net/lists/linux-samsung-soc/msg12056.html
> -> [PATCH v5 2/2] regulator: add device tree support for max8997
> http://www.spinics.net/lists/kernel/msg1328117.html
> 
> Tomasz Figa (6):
>   ARM: dts: Move parts common to Exynos4 from Exynos4210.dtsi to
>     Exynos4.dtsi
>   ARM: EXYNOS: exynos4-dt: Use exynos4 prefix instead of exynos4210
>   ARM: Exynos4: dts: Specify address and size cells for i2c controllers
>   ARM: Exynos4: Add OF compatibility lookups for Exynos4 i2c adapters
>   ARM: EXYNOS: Increase maximum possible memory bank size to 512MiB
>   ARM: Exynos: Add basic dts file for Samsung Trats board
> 
>  arch/arm/boot/dts/exynos4.dtsi             | 418
> +++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210-trats.dts     | 287 ++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi          | 377
+-------------------------
>  arch/arm/mach-exynos/Makefile.boot         |   2 +-
>  arch/arm/mach-exynos/include/mach/memory.h |   4 +-
>  arch/arm/mach-exynos/mach-exynos4-dt.c     |  34 ++-
>  6 files changed, 734 insertions(+), 388 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos4.dtsi
>  create mode 100644 arch/arm/boot/dts/exynos4210-trats.dts
> 
> --
> 1.7.12



From lauraa at codeaurora.org  Wed Aug 29 21:03:18 2012
From: lauraa at codeaurora.org (Laura Abbott)
Date: Wed, 29 Aug 2012 18:03:18 -0700
Subject: CMA page migration failure due to buffers on bh_lru
Message-ID: <503EBBD6.5080504@codeaurora.org>

Hi,

I've been observing a high rate of failures with CMA allocations on my
ARM system. I've set up a test case set up with a 56MB CMA region that
essentially does the following:

	total_failures = 0;
	loop forever:
		loop_failure = 0;
		for (i = 0; i < 56; i++)
			chunk[i] = dma_allocate(&cma_dev, 1MB)
			if (!chunk[i])
				loop_failure = 0

		if (loop_failure)
			total_failures++
			loop_failure = 0

		for (i = 0; i < 56; i++)
			dma_free(&cma_dev, chunk[i], 1MB)

In the background, I also have a process doing some amount of filesystem
activity (adb push/pull since this is an android system). During the 
course of my investigations I generally get ~8500 loops total and ~450 
total failures (i.e. one or more buffers could not be allocated). This 
is unacceptably high for our use cases.

In every case the allocation failure was ultimately due to a migration
failure; the pages contained buffers which could not be dropped because 
the buffers were busy (move_to_new_page -> fallback_migrate_page ->
try_to_release_page -> try_to_free_buffers -> drop_buffers -> 
buffer_busy). In every case, the b_count on the buffer head was always 1.

The problem arises because of the LRU lists for buffer heads:

__getblk
     __getblk_slow
         grow_buffers
             grow_dev_page
                 find_or_create_page -- create a possibly movable page
         __find_get_block
	    __find_get_block_slow
                 find_get_page -- return the movable page
             bh_lru_install
                 get_bh -- buffer head now has a reference

The reference taken in bh_lru_install won't be dropped until the bh is 
evicted from the lru. This means the page cannot be migrated as long as 
the buffer exists on an LRU list. The real issue is that unless the 
buffer gets evicted quickly the page can remain non-migratible for long 
periods of time. This makes CMA regions unusable for long periods of 
time given that we generally don't want to size CMA regions any larger 
than necessary ergo any failure will cause a problem.

My quick and dirty workaround for testing is to remove the GFP_MOVABLE 
flag from find_or_create_page but this seems significantly less than 
optimal. Ideally, it seems like the buffers should be evicted from the 
LRU when trying to drop (expand on invalid_bh_lru?) but I'm not familiar 
enough with the code path to know if this is a good approach.

Any suggestions/feedback is appreciated. Thanks.

Laura
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From dhobsong at igel.co.jp  Wed Aug 29 22:03:43 2012
From: dhobsong at igel.co.jp (Damian Hobson-Garcia)
Date: Thu, 30 Aug 2012 11:03:43 +0900
Subject: [PATCH 0/2] Renesas IPMMU driver for sh7372
In-Reply-To: <20120825071344.GI29755@verge.net.au>
References: <1343197742-13630-1-git-send-email-hdk@igel.co.jp>
 <20120825071344.GI29755@verge.net.au>
Message-ID: <503EC9FF.1090100@igel.co.jp>

Hi Simon,

On 2012/08/25 16:13, Simon Horman wrote:
> On Wed, Jul 25, 2012 at 03:29:00PM +0900, Hideki EIRAKU wrote:
>> This is the Renesas IPMMU driver, IOMMU API implementation and IPMMU
>> device support for sh7372 (AP4EVB and Mackerel).
>>
>> The IPMMU module supports the MMU function and the PMB function.  The
>> MMU function provides address translation by pagetable compatible with
>> ARMv6.  The PMB function provides address translation including
>> tile-linear translation.  This is implementation of the MMU function.
> 
> Hi,
> 
> I am wondering if anyone has had a chance to review this short series.
> It seems reasonable to me with the minor exception that I would
> be happier the second patch to update the relevant defconfigs
> to either enable or disable the driver.
> 
> I am also curious to know how this driver may be tested.

Since this patch series configures the LCDC, and CEU to use the IPMMU,
checking the memory addresses that those blocks are using are properly
registered in the IPMMU, and verifying that they actually function seems
like the best way to test this driver. I'll take a look at doing that.

That said, there currently isn't any way to use this with UIO devices,
since enabling the IPMMU with break direct accesses to physical memory
from all of the IP blocks on the ICB (LCDC, CEU, VPU, VEU, etc.)
For these devices, memory allocated with the dma-mapping API *must* be
used with IPMMU enabled.  The current uio_pdrv_genirq driver isn't set
up to deal with this right now.

Damian


From chanho61.park at samsung.com  Wed Aug 29 22:13:44 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Thu, 30 Aug 2012 11:13:44 +0900
Subject: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
In-Reply-To: <20120829213405.GC13868@mudshark.cambridge.arm.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-4-git-send-email-chanho61.park@samsung.com>
 <20120829213405.GC13868@mudshark.cambridge.arm.com>
Message-ID: <003501cd8655$15317f80$3f947e80$@samsung.com>

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Will Deacon
> Sent: Thursday, August 30, 2012 6:34 AM
> To: Chanho Park
> Cc: linux-samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> sachin.kamat at linaro.org; Kyungmin Park; kgene.kim at samsung.com;
> thomas.abraham at linaro.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v3 3/4] ARM: EXYNOS: Enable PMUs for exynos4
> 
> On Wed, Aug 29, 2012 at 02:14:56AM +0100, Chanho Park wrote:
> > This patch define irq numbers of ARM performance monitoring unit for
> exynos4.
> > The number of CPU cores and PMU irq numbers are vary according to soc
> types.
> > So we need to identify each soc type using soc_is_xxx function and
> > define the pmu irqs dynamically. In case of exynos4412, there are 4 cpu
> cores and pmus.
> >
> > Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   45
> ++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++--
> >  arch/arm/plat-samsung/devs.c             |    2 +-
> >  3 files changed, 52 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index be61564..24b78bd 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -30,11 +30,13 @@
> >  #include <asm/mach/map.h>
> >  #include <asm/mach/irq.h>
> >  #include <asm/cacheflush.h>
> > +#include <asm/pmu.h>
> 
> Why do you need this header file?

Oh, I'll remove  it. Thanks.

> 
> >  #include <mach/regs-irq.h>
> >  #include <mach/regs-pmu.h>
> >  #include <mach/regs-gpio.h>
> >  #include <mach/pmu.h>
> > +#include <mach/irqs.h>
> >
> >  #include <plat/cpu.h>
> >  #include <plat/clock.h>
> > @@ -1056,3 +1058,46 @@ static int __init exynos_init_irq_eint(void)
> >  	return 0;
> >  }
> >  arch_initcall(exynos_init_irq_eint);
> > +
> > +#if defined(CONFIG_CPU_EXYNOS4210) ||
> defined(CONFIG_SOC_EXYNOS4212)
> > +static struct resource exynos42xx_pmu_resource[] = {
> > +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> > +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> > +};
> > +
> > +static struct platform_device exynos42xx_device_pmu = {
> > +	.name		= "arm-pmu",
> > +	.num_resources	= ARRAY_SIZE(exynos42xx_pmu_resource),
> > +	.resource	= exynos42xx_pmu_resource,
> > +};
> > +#endif
> 
> Given that you don't pass an id and your device-tree binding is that for
> Cortex A15, I assume this patch series is based on my perf/updates branch?
> 
> That's good because it reduces the potential for conflicts, but you should
> make sure that whoever you send this to is aware of the dependency.

Yes. This patch is based on your latest patchset to avoid conflict because I saw Kukjin had acked your patch.
I think he'll resolve the dependency. If not, I'll re-submit this patch after applied your patch.

Best regards,
Chanho Park

> 
> Cheers,
> 
> Will
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From chanho61.park at samsung.com  Wed Aug 29 22:53:51 2012
From: chanho61.park at samsung.com (Chanho Park)
Date: Thu, 30 Aug 2012 11:53:51 +0900
Subject: [PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for exynos4412
In-Reply-To: <CAJuYYwSH19-GmNo7jZyXd9TC4VeKGxVCd=N0Vi4=kUNZPZNx6g@mail.gmail.com>
References: <1346202897-27306-1-git-send-email-chanho61.park@samsung.com>
 <1346202897-27306-3-git-send-email-chanho61.park@samsung.com>
 <CAJuYYwSH19-GmNo7jZyXd9TC4VeKGxVCd=N0Vi4=kUNZPZNx6g@mail.gmail.com>
Message-ID: <003701cd865a$af73c170$0e5b4450$@samsung.com>

> -----Original Message-----
> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> Sent: Wednesday, August 29, 2012 8:10 PM
> To: Chanho Park
> Cc: kgene.kim at samsung.com; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; linux at arm.linux.org.uk;
> sachin.kamat at linaro.org; will.deacon at arm.com; Kyungmin Park
> Subject: Re: [PATCH v3 2/4] ARM: EXYNOS: Correct combined IRQs for
> exynos4412
> 
> On 29 August 2012 06:44, Chanho Park <chanho61.park at samsung.com>
> wrote:
> > This patch corrects combined IRQs for exynos4412 platform. The
> > exynos4412 has four extra combined irq group. Each irq is mapped to
> > IRQ_SPI(xx). Unfortunately, extra combined IRQs isn't sequential. So, we
> need to map the irq manually.
> >
> > Signed-off-by: Chanho Park <chanho61.park at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   31
> ++++++++++++++++++++++++------
> >  arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
> >  2 files changed, 26 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index f194bbc..be61564 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -560,23 +560,39 @@ static struct irq_domain_ops
> combiner_irq_domain_ops = {
> >         .map    = combiner_irq_domain_map,
> >  };
> >
> > +static unsigned int get_combiner_extra_irq(int group) {
> > +       switch (group) {
> > +       case 16:
> > +               return IRQ_SPI(107);
> > +       case 17:
> > +               return IRQ_SPI(108);
> > +       case 18:
> > +               return IRQ_SPI(48);
> > +       case 19:
> > +               return IRQ_SPI(42);
> > +       default:
> > +               return 0;
> > +       }
> > +}
> > +
> >  static void __init combiner_init(void __iomem *combiner_base,
> >                                  struct device_node *np)  {
> >         int i, irq, irq_base;
> >         unsigned int max_nr, nr_irq;
> >
> > +       max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> > +                                       EXYNOS4_MAX_COMBINER_NR;
> > +
> >         if (np) {
> >                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr))
> {
> >                         pr_warning("%s: number of combiners not specified, "
> >                                 "setting default as %d.\n",
> > -                               __func__, EXYNOS4_MAX_COMBINER_NR);
> > -                       max_nr = EXYNOS4_MAX_COMBINER_NR;
> > +                               __func__, max_nr);
> >                 }
> > -       } else {
> > -               max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> > -                                               EXYNOS4_MAX_COMBINER_NR;
> >         }
> > +
> >         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
> 
> Along with this change, this patch should update the default value
> "samsung,combiner-nr" binding in device tree binding documentation for
> combiner. It should state that is Exynos5 will use 32 and Exynos4 will use 20 as
> the default value.
> 
> >
> >         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
> > @@ -593,7 +609,10 @@ static void __init combiner_init(void __iomem
> *combiner_base,
> >         }
> >
> >         for (i = 0; i < max_nr; i++) {
> > -               irq = IRQ_SPI(i);
> > +               if (i < 16 || soc_is_exynos5250())
> > +                       irq = IRQ_SPI(i);
> > +               else
> > +                       irq = get_combiner_extra_irq(i);
> >  #ifdef CONFIG_OF
> >                 if (np)
> >                         irq = irq_of_parse_and_map(np, i); diff --git
> > a/arch/arm/mach-exynos/include/mach/irqs.h
> > b/arch/arm/mach-exynos/include/mach/irqs.h
> > index 35bced6..357ed7f 100644
> > --- a/arch/arm/mach-exynos/include/mach/irqs.h
> > +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> > @@ -165,7 +165,7 @@
> >  #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
> >  #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
> >
> > -#define EXYNOS4_MAX_COMBINER_NR                16
> > +#define EXYNOS4_MAX_COMBINER_NR                20
> 
> Will this not break Exynos4210 which has only 16 combiners? This is fine in
> case max-combiner values is listed in dt mode, but in non-dt mode or if max-
> combiner is not specified in dt, this will not be correct.

I didn't have test about exynos4210 because I don't have the 4210 board.
However, there is no problem of exynos4212 which has 18 combiner.
On second thought, it might break by accessing undefined area.
Ok, I'll resolve it and resubmit patch.

Best regards,
Chanho Park

> 
> >
> >  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
> >  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
> > --
> > 1.7.9.5
> >



From gururaja.hebbar at ti.com  Thu Aug 30 00:01:00 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Thu, 30 Aug 2012 04:01:00 +0000
Subject: [PATCH V3] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1346148830-2965-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346148830-2965-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA6DDAD@DBDE01.ent.ti.com>


Hi,

Gentle Ping.


On Tue, Aug 28, 2012 at 15:43:50, Hebbar, Gururaja wrote:
> Device tree support for Davinci Machine driver
> 
> When the board boots with device tree, the driver will receive card,
> codec, dai interface details (like the card name, DAPM routing map,
> phandle for the audio components described in the dts file, codec mclk
> speed).
> The card will be set up based on this information.
> Since the routing is provided via DT we can mark the card fully routed
> so core can take care of disconnecting the unused pins.
> 
> When here, code indentation and comment style is also fixed
> 
> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> ---
> Changes from V1:
> 	- Change DT parameter from "ti,codec-clock" to "ti,codec-clock-rate"
> 	- add more explanation to DT parameters
> 
> Changes from V2:
> 	- Update Documentation details
> 	- Remove irrelevant commit message
> 
> :000000 100644 0000000... b248014... A	Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> :100644 100644 ab0ad45... ca2a547... M	sound/soc/davinci/davinci-evm.c
>  .../bindings/sound/davinci-evm-audio.txt           |   66 +++++++
>  sound/soc/davinci/davinci-evm.c                    |  185 +++++++++++++++++--
>  2 files changed, 231 insertions(+), 20 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> new file mode 100644
> index 0000000..b248014
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> @@ -0,0 +1,66 @@
> +* Texas Instruments SoC audio setups with TLV320AIC3X Codec
> +
> +Required properties:
> +- compatible : "ti,davinci-evm-audio"
> +- ti,model : The user-visible name of this sound complex.
> +- ti,audio-routing : A list of the connections between audio components.
> +  Each entry is a pair of strings, the first being the connection's sink,
> +  the second being the connection's source. Valid names for sources and
> +  sinks are the codec's pins, and the jacks on the board:
> +
> +  Codec pins:
> +
> +  * MIC3L
> +  * MIC3R
> +  * LINE1L
> +  * LINE2L
> +  * LINE1R
> +  * LINE2R
> +
> +  Board connectors:
> +
> +  * Headphone Jack
> +  * Line Out
> +  * Mic Jack
> +
> +- ti,mcasp-controller : The phandle of the McASP controller
> +- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
> +- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
> +
> +- dai-data		: A list of DAI data used by SOC code to register
> +			  DAI, Codecs platform.
> +			  The string index "should" be as shown below.
> +dai-data =
> +"<DAI Name>", 		"<DAI Stream Name>",
> +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> +"<evm ops required (evm_ops or evm_spdif_ops)>";
> +
> +Here fields
> +"<DAI Name>"		: used to indicate the DAI Name
> +"<DAI Stream Name>"	: used to indicate the Stream Name
> +"<CODEC DAI Name>"	: used to bind the link between Codec DAI and ASOC DAI
> +
> +Machine related options
> +"<true/false>"		: Whether the machine specific initialization
> +			: evm_aic3x_init() is required
> +
> +"<evm ops required>"	: Which hardware ops function is to be used.
> +			: (evm_ops or evm_spdif_ops)
> +			: use evm-spdif-ops if DAI is working in DIT mode
> +			: else use evm-ops. These ops setup hw param callbacks
> +			: which are used to setup CODEC/cpu DAI configuration
> +			: and codec system clock.
> +
> +Example:
> +
> +sound {
> +	compatible = "ti,davinci-evm-audio";
> +	ti,model = "DA830 EVM";
> +	ti,audio-codec = <&tlv320aic3x>;
> +	ti,mcasp-controller = <&mcasp1>;
> +	ti,codec-clock-rate = <12000000>;
> +	dai-data =
> +		"TLV320AIC3X", 		"AIC3X",
> +		"tlv320aic3x-hifi",	"true",
> +		"evm-ops";
> +};
> diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
> index ab0ad45..ca2a547 100644
> --- a/sound/soc/davinci/davinci-evm.c
> +++ b/sound/soc/davinci/davinci-evm.c
> @@ -34,27 +34,38 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
>  	struct snd_soc_pcm_runtime *rtd = substream->private_data;
>  	struct snd_soc_dai *codec_dai = rtd->codec_dai;
>  	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
> +	struct snd_soc_codec *codec = rtd->codec;
> +	struct snd_soc_card *soc_card = codec->card;
> +	struct device_node *np = soc_card->dev->of_node;
>  	int ret = 0;
>  	unsigned sysclk;
>  
> -	/* ASP1 on DM355 EVM is clocked by an external oscillator */
> -	if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
> -	    machine_is_davinci_dm365_evm())
> -		sysclk = 27000000;
> -
> -	/* ASP0 in DM6446 EVM is clocked by U55, as configured by
> -	 * board-dm644x-evm.c using GPIOs from U18.  There are six
> -	 * options; here we "know" we use a 48 KHz sample rate.
> -	 */
> -	else if (machine_is_davinci_evm())
> -		sysclk = 12288000;
> -
> -	else if (machine_is_davinci_da830_evm() ||
> -				machine_is_davinci_da850_evm())
> -		sysclk = 24576000;
> -
> -	else
> -		return -EINVAL;
> +	if (np) {
> +		ret = of_property_read_u32(np, "ti,codec-clock-rate", &sysclk);
> +		if (ret < 0)
> +			return ret;
> +	} else {
> +		/* ASP1 on DM355 EVM is clocked by an external oscillator */
> +		if (machine_is_davinci_dm355_evm() ||
> +			machine_is_davinci_dm6467_evm() ||
> +			machine_is_davinci_dm365_evm())
> +			sysclk = 27000000;
> +
> +		/*
> +		 * ASP0 in DM6446 EVM is clocked by U55, as configured by
> +		 * board-dm644x-evm.c using GPIOs from U18.  There are six
> +		 * options; here we "know" we use a 48 KHz sample rate.
> +		 */
> +		else if (machine_is_davinci_evm())
> +			sysclk = 12288000;
> +
> +		else if (machine_is_davinci_da830_evm() ||
> +					machine_is_davinci_da850_evm())
> +			sysclk = 24576000;
> +
> +		else
> +			return -EINVAL;
> +	}
>  
>  	/* set codec DAI configuration */
>  	ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
> @@ -127,13 +138,22 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
>  {
>  	struct snd_soc_codec *codec = rtd->codec;
>  	struct snd_soc_dapm_context *dapm = &codec->dapm;
> +	struct device_node *np = codec->card->dev->of_node;
> +	int ret;
>  
>  	/* Add davinci-evm specific widgets */
>  	snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
>  				  ARRAY_SIZE(aic3x_dapm_widgets));
>  
> -	/* Set up davinci-evm specific audio path audio_map */
> -	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
> +	if (np) {
> +		ret = snd_soc_of_parse_audio_routing(codec->card,
> +							"ti,audio-routing");
> +		if (ret)
> +			return ret;
> +	} else {
> +		/* Set up davinci-evm specific audio path audio_map */
> +		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
> +	}
>  
>  	/* not connected */
>  	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
> @@ -282,6 +302,113 @@ static struct snd_soc_card da850_snd_soc_card = {
>  	.num_links = 1,
>  };
>  
> +#if defined(CONFIG_OF)
> +/*
> + * This struct is just used as place holder. It will be filled with
> + * data from dt node
> + */
> +static struct snd_soc_dai_link evm_dai = {
> +};
> +
> +/* davinci evm audio machine driver */
> +static struct snd_soc_card evm_soc_card = {
> +	.owner = THIS_MODULE,
> +	.dai_link = &evm_dai,
> +	.num_links = 1,
> +};
> +
> +static int davinci_evm_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	const char *stringPtr, *propname;
> +	u32 val;
> +	int ret = 0;
> +
> +	propname = "dai-data";
> +	val = of_property_count_strings(np, propname);
> +	if (val < 0)
> +		return val;
> +
> +	ret = of_property_read_string_index(np, propname, 0, &evm_dai.name);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = of_property_read_string_index(np, propname, 1,
> +						&evm_dai.stream_name);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = of_property_read_string_index(np, propname, 2,
> +						&evm_dai.codec_dai_name);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = of_property_read_string_index(np, propname, 3, &stringPtr);
> +	if (ret < 0)
> +		return ret;
> +	else
> +		if (strcasecmp(stringPtr, "true") == 0)
> +			evm_dai.init = evm_aic3x_init;
> +
> +	ret = of_property_read_string_index(np, propname, 4, &stringPtr);
> +	if (ret < 0) {
> +		return ret;
> +	} else {
> +		if (strcasecmp(stringPtr, "evm-ops") == 0)
> +			evm_dai.ops = &evm_ops;
> +		else if (strcasecmp(stringPtr, "evm-spdif-ops") == 0)
> +			evm_dai.ops = &evm_spdif_ops;
> +	}
> +
> +	evm_dai.codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
> +	if (!evm_dai.codec_of_node)
> +		return -EINVAL;
> +
> +	evm_dai.cpu_dai_of_node = of_parse_phandle(np,
> +						"ti,mcasp-controller", 0);
> +	if (!evm_dai.cpu_dai_of_node)
> +		return -EINVAL;
> +
> +	evm_dai.platform_of_node = evm_dai.cpu_dai_of_node;
> +
> +	evm_soc_card.dev = &pdev->dev;
> +	ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
> +	if (ret)
> +		return ret;
> +
> +	ret = snd_soc_register_card(&evm_soc_card);
> +	if (ret)
> +		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
> +
> +	return ret;
> +}
> +
> +static int __devexit davinci_evm_remove(struct platform_device *pdev)
> +{
> +	struct snd_soc_card *card = platform_get_drvdata(pdev);
> +
> +	snd_soc_unregister_card(card);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id davinci_evm_dt_ids[] = {
> +	{ .compatible = "ti,davinci-evm-audio", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, davinci_mcasp_dt_ids);
> +
> +static struct platform_driver davinci_evm_driver = {
> +	.probe		= davinci_evm_probe,
> +	.remove		= __devexit_p(davinci_evm_remove),
> +	.driver		= {
> +		.name	= "davinci_evm",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(davinci_evm_dt_ids),
> +	},
> +};
> +#endif
> +
>  static struct platform_device *evm_snd_device;
>  
>  static int __init evm_init(void)
> @@ -289,6 +416,14 @@ static int __init evm_init(void)
>  	struct snd_soc_card *evm_snd_dev_data;
>  	int index;
>  	int ret;
> +#if defined(CONFIG_OF)
> +	struct device_node *np;
> +
> +	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
> +	if (np) {
> +		return platform_driver_register(&davinci_evm_driver);
> +	}
> +#endif
>  
>  	if (machine_is_davinci_evm()) {
>  		evm_snd_dev_data = &dm6446_snd_soc_card_evm;
> @@ -325,6 +460,16 @@ static int __init evm_init(void)
>  
>  static void __exit evm_exit(void)
>  {
> +#if defined(CONFIG_OF)
> +	struct device_node *np;
> +
> +	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
> +	if (np) {
> +		platform_driver_unregister(&davinci_evm_driver);
> +		return;
> +	}
> +#endif
> +
>  	platform_device_unregister(evm_snd_device);
>  }
>  
> -- 
> 1.7.1
> 
> 


Regards, 
Gururaja


From andrew at lunn.ch  Thu Aug 30 01:11:42 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 30 Aug 2012 07:11:42 +0200
Subject: [PATCH] ARM: Build dtb files in all target
In-Reply-To: <503DC2D7.2080107@codeaurora.org>
References: <1346218523-15958-1-git-send-email-andrew@lunn.ch>
 <503DC2D7.2080107@codeaurora.org>
Message-ID: <20120830051142.GO9886@lunn.ch>

On Wed, Aug 29, 2012 at 12:20:55AM -0700, Stephen Boyd wrote:
> On 8/28/2012 10:35 PM, Andrew Lunn wrote:
> > Tools like kisskb are good at finding build regressions in the kernel
> > sources. However, regressions in the DT desscriptions are not found,
> > because generally these build systems don't build the DT binary blobs.
> >
> > Extend the ARM all target to build all enabled DTB files.
> >
> > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> 
> You should probably put a star (*) next to the dtbs info in the help
> text too.

Will do. Version 2 to be posted soon.

> 
> Have you tried this in a clean tree?

I tested with
make distclean
make kirkwood_defconfig
make

Any other permutations you would like me to test?

> Also, should this only be default true if USE_OF is true?

Also in v2.

     Thanks
          Andrew


From andrew at lunn.ch  Thu Aug 30 01:14:47 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 30 Aug 2012 07:14:47 +0200
Subject: [PATCH v2] ARM: Build dtb files in all target
Message-ID: <1346303687-7795-1-git-send-email-andrew@lunn.ch>

Tools like kisskb are good at finding build regressions in the kernel
sources. However, regressions in the DT desscriptions are not found,
because generally these build systems don't build the DT binary blobs.

Extend the ARM all target to build all enabled DTB files.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
v2: * in the help test
    Only invoke dtbs if CONFIGUSE_OF=y

 arch/arm/Makefile |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..0457ef4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -268,7 +268,12 @@ else
 KBUILD_IMAGE := zImage
 endif
 
-all:	$(KBUILD_IMAGE)
+# Build the DT binary blobs if we have OF configured
+ifeq ($(CONFIG_USE_OF),y)
+KBUILD_DTBS := dtbs
+endif
+
+all:	$(KBUILD_IMAGE) $(KBUILD_DTBS)
 
 boot := arch/arm/boot
 
@@ -306,7 +311,7 @@ define archhelp
   echo  '  uImage        - U-Boot wrapped zImage'
   echo  '  bootpImage    - Combined zImage and initial RAM disk' 
   echo  '                  (supply initrd image via make variable INITRD=<path>)'
-  echo  '  dtbs          - Build device tree blobs for enabled boards'
+  echo  '* dtbs          - Build device tree blobs for enabled boards'
   echo  '  install       - Install uncompressed kernel'
   echo  '  zinstall      - Install compressed kernel'
   echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
-- 
1.7.10.4



From vbyravarasu at nvidia.com  Thu Aug 30 01:16:35 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Thu, 30 Aug 2012 10:46:35 +0530
Subject: [PATCH] usb: tegra: moving phy driver into drivers directory
In-Reply-To: <503E51C9.7000606@wwwdotorg.org>
References: <1346146338-4996-1-git-send-email-vbyravarasu@nvidia.com>
 <503CD0A0.7080300@wwwdotorg.org>
 <D958900912E20642BCBC71664EFECE3E6DDE14DD7C@BGMAIL02.nvidia.com>
 <503E51C9.7000606@wwwdotorg.org>
Message-ID: <D958900912E20642BCBC71664EFECE3E6DDE14DF54@BGMAIL02.nvidia.com>

> -----Original Message-----
> From: linux-tegra-owner at vger.kernel.org [mailto:linux-tegra-
> owner at vger.kernel.org] On Behalf Of Stephen Warren
> Sent: Wednesday, August 29, 2012 11:01 PM
> To: Venu Byravarasu
> Cc: ccross at android.com; olof at lixom.net; linux at arm.linux.org.uk;
> stern at rowland.harvard.edu; gregkh at linuxfoundation.org; balbi at ti.com;
> linux-kernel at vger.kernel.org; linux-tegra at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; linux-usb at vger.kernel.org
> Subject: Re: [PATCH] usb: tegra: moving phy driver into drivers directory
> 
> On 08/28/12 22:17, Venu Byravarasu wrote:
> > Stephen Warren wrote at Tuesday, August 28, 2012 7:37 PM:
> >> On 08/28/2012 02:32 AM, Venu Byravarasu wrote:
> >>> In order to keep up with the USB driver files organization,
> >>> moving USB phy driver from mach-tegra to drivers/USB directory.
> >>>
> >>> Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
> >>
> >>> diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-
> >> tegra/devices.c
> >>
> >>> -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
> >>> -	.reset_gpio = -1,
> >>> -	.clk = "cdev2",
> >>> -};
> >>> -
> >>>   struct tegra_ehci_platform_data tegra_ehci1_pdata = {
> >>>   	.operating_mode = TEGRA_USB_OTG,
> >>>   	.power_down_on_bus_suspend = 1,
> >>> @@ -450,7 +444,7 @@ struct tegra_ehci_platform_data
> tegra_ehci1_pdata
> >> = {
> >>>   };
> >>>
> >>>   struct tegra_ehci_platform_data tegra_ehci2_pdata = {
> >>> -	.phy_config = &tegra_ehci2_ulpi_phy_config,
> >>> +	.phy_config = NULL,
> >>
> >> The PHY driver checks that field isn't NULL, and fails if it is:
> >>
> >>> struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int
> >> instance,
> >>>          void __iomem *regs, void *config, enum tegra_usb_phy_mode
> >> phy_mode)
> >>> {
> >> ...
> >>>          phy->config = config;
> >>>          phy->mode = phy_mode;
> >>>
> >>>          if (!phy->config) {
> >>>                  if (phy_is_ulpi(phy)) {
> >>>                          pr_err("%s: ulpi phy configuration missing", __func__);
> >>>                          err = -EINVAL;
> >>>                          goto err0;
> >>
> >> So, this change will completely break ULPI support, which currently
> >> works fine. So, NAK.
> >
> > My initial plan was to add support for phy interfaces one by one.
> > As part of that thought of UTMI only support at first and then add
> > ULPI and HSIC in next patches.
> > However as you were mentioning that it is not correct way, will
> > push ULPI & UTMI support at once in next patches.
> 
> But with the existing code, both ULPI and UTMI work. This patch breaks
> something that already works.
> 
> >> I also plan on deleting devices.[ch] in kernel 3.7, and moving the USB
> >> platform data into board-dt-tegra20.c, since that's the only place it's
> >> used right now. So, this patch would conflict with that rather badly. I
> >> just posted the patches for that to the linux-tegra mailing list last
> >> night. Do you have better proposals for that? Perhaps usb_phy.c should
> >> set phy->config to &ulpi_default in a similar fashion to how it works
> >> for UTMI; that would remove some of the coupling between the changes.
> >>
> >> BTW, in your response to Felipe, you said...
> >>
> >>> Thanks Felipe for your comments.
> >>> Created a patch to separate out phy related stuff to phy.h with you as a
> >> reviewer.
> >>> Plz let me know your comments.
> >>
> >> ... where is that patch?
> >
> > Plz see https://lkml.org/lkml/2012/8/28/58
> 
> Doesn't that link point at the patch I replied to?

Sorry, by mistake I sent the wrong one.
Here is the correct one: https://lkml.org/lkml/2012/8/29/40  

> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From horms at verge.net.au  Thu Aug 30 01:36:03 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:36:03 +0900
Subject: [PATCH] ARM: mach-shmobile: Add compilation support for dtbs using
 'make dtbs'
In-Reply-To: <1346304963-23457-1-git-send-email-horms@verge.net.au>
References: <1346304963-23457-1-git-send-email-horms@verge.net.au>
Message-ID: <1346304963-23457-2-git-send-email-horms@verge.net.au>

From: Tetsuyuki Kobayashi <koba at kmckk.co.jp>

Add compilation support for dtbs using 'make dtbs'

Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Cc: Simon Horman <horms at verge.net.au>
Signed-off-by: Tetsuyuki Kobayashi <koba at kmckk.co.jp>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/Makefile.boot | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd9..5e41019 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,3 +7,7 @@ __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
 #
 #params_phys-y (Instead: Pass atags pointer in r2)
 #initrd_phys-y (Instead: Use compiled-in initramfs)
+
+dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb
+dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb
+dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 01:36:02 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:36:02 +0900
Subject: [GIT PULL v2] Renesas ARM-based SoC: Core for 3.7
Message-ID: <1346304963-23457-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following enhancement for the Renesas ARM-based SoC
Core from Kobayashi-san for inclusion in 3.7.

This replaces v1 of this pull request which included an
old and incorrect version of Kobayashi-san's patch.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git soc-core

for you to fetch changes up to c88a79a7789b2909ad1cf69ea2c9142030bbd6f4:

  ARM: mach-shmobile: Add compilation support for dtbs using 'make dtbs' (2012-08-30 14:21:54 +0900)

----------------------------------------------------------------
Tetsuyuki Kobayashi (1):
      ARM: mach-shmobile: Add compilation support for dtbs using 'make dtbs'

 arch/arm/mach-shmobile/Makefile.boot | 4 ++++
 1 file changed, 4 insertions(+)


From horms at verge.net.au  Thu Aug 30 01:38:58 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:38:58 +0900
Subject: [GIT PULL] Renesas ARM-based SoC fix for v3.6
Message-ID: <1346305139-24337-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following boot-failure fix for the Marzen board from
Morimoto-san for inclusion in 3.6.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git fixes

for you to fetch changes up to 497dcf6fc355f0734faf851662b6957386715d24:

  ARM: shmobile: marzen: fixup smsc911x id for regulator (2012-08-30 14:10:08 +0900)

----------------------------------------------------------------
Kuninori Morimoto (1):
      ARM: shmobile: marzen: fixup smsc911x id for regulator

 arch/arm/mach-shmobile/board-marzen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


From horms at verge.net.au  Thu Aug 30 01:38:59 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:38:59 +0900
Subject: [PATCH] ARM: shmobile: marzen: fixup smsc911x id for regulator
In-Reply-To: <1346305139-24337-1-git-send-email-horms@verge.net.au>
References: <1346305139-24337-1-git-send-email-horms@verge.net.au>
Message-ID: <1346305139-24337-2-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

dummy_supplies for smsc911x are registered as "smsc911x".
smsc911x driver needs id = -1

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 3a528cf..fcf5a47 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -67,7 +67,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
 
 static struct platform_device eth_device = {
 	.name		= "smsc911x",
-	.id		= 0,
+	.id		= -1,
 	.dev  = {
 		.platform_data = &smsc911x_platdata,
 	},
-- 
1.7.10.2.484.gcd07cc5



From andrew at lunn.ch  Thu Aug 30 01:39:12 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 30 Aug 2012 07:39:12 +0200
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
Message-ID: <1346305152-14618-1-git-send-email-andrew@lunn.ch>

Linux-next has failed to compile for kirkwood since 23 August with:

arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)

Add missing <linux/sizes.h>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index d933593..be90b7d 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/sizes.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
-- 
1.7.10.4



From horms at verge.net.au  Thu Aug 30 01:43:13 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:43:13 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: KZM-9A-GT for 3.7
In-Reply-To: <503C1B97.3070004@kmckk.co.jp>
References: <1346113116-20252-1-git-send-email-horms@verge.net.au>
 <503C1B97.3070004@kmckk.co.jp>
Message-ID: <20120830054313.GA25362@verge.net.au>

On Tue, Aug 28, 2012 at 10:15:03AM +0900, Tetsuyuki Kobayashi wrote:
> (2012/08/28 9:18), Simon Horman wrote:
> > Hi Olaf, Hi Arnd,
> > 
> > please consider the following enhancement for the KZM-9A-GT board
> 
> Just a minor correction :)
> The board name is KZM-A9-GT.

Thanks, sorry about that.


From horms at verge.net.au  Thu Aug 30 01:47:27 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:47:27 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: KZM-A9-GT for 3.7 #2
Message-ID: <1346305648-25263-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following enhancement to the KZM-A9-GT board by
from Morimoto-san for inclusion in 3.7.

* This pull request is based on the devel branch of
  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
  which is based on v3.6-rc2.

  This is to satisfy compile-time dependencies.
  Please let me know if you would like this handled a different way.

* This and a previous pull request,
  "Renesas ARM-based SoC: KZM-9A-GT for 3.7", both touch board-kzm9g.c
  but I do not believe there is a conflict.

  Please let me know if you would like this handled a different way.

----------------------------------------------------------------
The following changes since commit f24a9172233cfc205ef7a999370412ab577783b1:

  gpio/mxs: adopt irq_domain support for mxs gpio driver (2012-08-23 23:49:17 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git kzm9g-gpio

for you to fetch changes up to af26b952cca1a87f31b09015fb3f7c77232036e1:

  ARM: shmobile: kzm9g: use gpio-keys instead of gpio-keys-polled (2012-08-30 13:59:31 +0900)

----------------------------------------------------------------
Kuninori Morimoto (1):
      ARM: shmobile: kzm9g: use gpio-keys instead of gpio-keys-polled

 arch/arm/configs/kzm9g_defconfig     | 2 +-
 arch/arm/mach-shmobile/board-kzm9g.c | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)


From horms at verge.net.au  Thu Aug 30 01:47:28 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:47:28 +0900
Subject: [PATCH] ARM: shmobile: kzm9g: use gpio-keys instead of
 gpio-keys-polled
In-Reply-To: <1346305648-25263-1-git-send-email-horms@verge.net.au>
References: <1346305648-25263-1-git-send-email-horms@verge.net.au>
Message-ID: <1346305648-25263-2-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

6e20a0a429bd4dc07d6de16d9c247270e04e4aa0
(gpio: pcf857x: enable gpio_to_irq() support) supports
gpio_to_irq() on pcf857x driver.
Now, we can use gpio-keys driver instead of gpio-keys-polled.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/kzm9g_defconfig     | 2 +-
 arch/arm/mach-shmobile/board-kzm9g.c | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c86..175804e 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -22,7 +22,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_ARCH_SH73A0=y
 CONFIG_MACH_KZM9G=y
 CONFIG_MEMORY_START=0x41000000
@@ -70,6 +69,7 @@ CONFIG_INPUT_SPARSEKMAP=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ST1232=y
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 53b7ea9..4d1348e 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -482,12 +482,10 @@ static struct gpio_keys_button gpio_buttons[] = {
 static struct gpio_keys_platform_data gpio_key_info = {
 	.buttons	= gpio_buttons,
 	.nbuttons	= ARRAY_SIZE(gpio_buttons),
-	.poll_interval	= 250, /* poling at this point */
 };
 
 static struct platform_device gpio_keys_device = {
-	/* gpio-pcf857x.c driver doesn't support gpio_to_irq() */
-	.name	= "gpio-keys-polled",
+	.name	= "gpio-keys",
 	.dev	= {
 		.platform_data  = &gpio_key_info,
 	},
@@ -550,6 +548,7 @@ static struct platform_device fsi_ak4648_device = {
 /* I2C */
 static struct pcf857x_platform_data pcf8575_pdata = {
 	.gpio_base	= GPIO_PCF8575_BASE,
+	.irq		= intcs_evt2irq(0x3260), /* IRQ19 */
 };
 
 static struct i2c_board_info i2c0_devices[] = {
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 01:52:48 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:52:48 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: r8a7740 SoC for 3.7
Message-ID: <1346305969-27110-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following documentation enhancement for the
r8a7740 SoC from Morimoto-san for inclusion in 3.7.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git r8a7740

for you to fetch changes up to a6e7c110f972d7ca5c6eb288f5e64d5659b44dc0:

  ARM: shmobile: r8a7740: add USB24 clock explain and sample code (2012-08-27 17:43:22 +0900)

----------------------------------------------------------------
Kuninori Morimoto (1):
      ARM: shmobile: r8a7740: add USB24 clock explain and sample code

 arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)


From horms at verge.net.au  Thu Aug 30 01:52:49 2012
From: horms at verge.net.au (Simon Horman)
Date: Thu, 30 Aug 2012 14:52:49 +0900
Subject: [PATCH] ARM: shmobile: r8a7740: add USB24 clock explain and sample
 code
In-Reply-To: <1346305969-27110-1-git-send-email-horms@verge.net.au>
References: <1346305969-27110-1-git-send-email-horms@verge.net.au>
Message-ID: <1346305969-27110-2-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

USBCKCR is controlling USB parent clock and divide rate.
This parent clock is used as a "usb24s" from other devices,
but the "divide rate" is not used.
Further, this clock itself is known as "usb24".
So, to set this clock is a little confusable.
This patch adds quick explain and sample code for this clock.

Cc: Damian Hobson-Garcia <dhobsong at igel.co.jp>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index ad5fccc..a6a7583 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -188,6 +188,22 @@ static struct clk pllc1_div2_clk = {
 };
 
 /* USB clock */
+/*
+ * USBCKCR is controlling usb24 clock
+ * bit[7] : parent clock
+ * bit[6] : clock divide rate
+ * And this bit[7] is used as a "usb24s" from other devices.
+ * (Video clock / Sub clock / SPU clock)
+ * You can controll this clock as a below.
+ *
+ * struct clk *usb24	= clk_get(dev,  "usb24");
+ * struct clk *usb24s	= clk_get(NULL, "usb24s");
+ * struct clk *system	= clk_get(NULL, "system_clk");
+ * int rate = clk_get_rate(system);
+ *
+ * clk_set_parent(usb24s, system);  // for bit[7]
+ * clk_set_rate(usb24, rate / 2);   // for bit[6]
+ */
 static struct clk *usb24s_parents[] = {
 	[0] = &system_clk,
 	[1] = &extal2_clk
-- 
1.7.10.2.484.gcd07cc5



From dedekind1 at gmail.com  Thu Aug 30 02:29:05 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 30 Aug 2012 09:29:05 +0300
Subject: [PATCH resend] i.MX53 Nand support
In-Reply-To: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1346308145.2848.529.camel@sauron.fi.intel.com>

On Wed, 2012-08-29 at 09:40 +0200, Sascha Hauer wrote:
> Hi All,
> 
> The following patches add i.MX53 and dt support to mxc_nand. This
> is only a resent based on v3.6-rc3 as it seems this series slipped
> through the cracks last time I posted it.
> 
> So Artem, if there are no objections, please consider applying up to
> 3/4, I would then take 4/4 through my tree.

Please, take a look at the l2-mtd.git tree, I already have all these
patches. Actually, they are already in dwmw2's tree, the and were
supposed to be merged already, but unfortunately the merge window was
missed because (a) dwmw2 did not send a pull request early enough and
(b) Linus decided to punish late pull-request senders and closed the
merge window 2 days earlier than usually.

-- 
Best Regards,
Artem Bityutskiy
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From s.hauer at pengutronix.de  Thu Aug 30 02:31:07 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 30 Aug 2012 08:31:07 +0200
Subject: [PATCH resend] i.MX53 Nand support
In-Reply-To: <1346308145.2848.529.camel@sauron.fi.intel.com>
References: <1346226019-23560-1-git-send-email-s.hauer@pengutronix.de>
 <1346308145.2848.529.camel@sauron.fi.intel.com>
Message-ID: <20120830063107.GD26594@pengutronix.de>

On Thu, Aug 30, 2012 at 09:29:05AM +0300, Artem Bityutskiy wrote:
> On Wed, 2012-08-29 at 09:40 +0200, Sascha Hauer wrote:
> > Hi All,
> > 
> > The following patches add i.MX53 and dt support to mxc_nand. This
> > is only a resent based on v3.6-rc3 as it seems this series slipped
> > through the cracks last time I posted it.
> > 
> > So Artem, if there are no objections, please consider applying up to
> > 3/4, I would then take 4/4 through my tree.
> 
> Please, take a look at the l2-mtd.git tree, I already have all these
> patches. Actually, they are already in dwmw2's tree, the and were
> supposed to be merged already, but unfortunately the merge window was
> missed because (a) dwmw2 did not send a pull request early enough and
> (b) Linus decided to punish late pull-request senders and closed the
> merge window 2 days earlier than usually.

Ah, I missed to check the tree. Sorry for the noise then.

Thanks
 Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From josh.wu at atmel.com  Thu Aug 30 02:27:57 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 30 Aug 2012 14:27:57 +0800
Subject: [PATCH] [media] atmel_isi: allocate memory to store the isi
 platform data.
In-Reply-To: <alpine.DEB.2.00.1208291755220.3095@axis700.grange>
References: <1346235093-28613-1-git-send-email-josh.wu@atmel.com>
 <503E323A.8060409@samsung.com>
 <alpine.DEB.2.00.1208291755220.3095@axis700.grange>
Message-ID: <503F07ED.6080802@atmel.com>

Hi, all

Sorry, My mistake here. After checking the code, this ISI bug doesn't 
exist in current mainline code. So I will *cancel* this patch.

Since current mainline will copy this __initdata isi platform data to 
one static structure in function at91_add_device_isi(...). Then pass 
this static structure to the driver.

So the ISI driver has no bug that isi platform became invalid. I meet 
this is because I'm not call the at91_add_device_isi(...) since I try in 
the DT support board.

At last, even no above bug in the code, This isi_platform_data is still 
need to stored in ISI driver. Since if we support DT then we need this 
isi platform data and the function at91_add_device_isi(...) will not to 
be called (it is in device file).

So I think after soc-camera DT support is merged. Then I will send a DT 
support patch for ISI driver which will embed the isi_platform_data into 
atmel_isi.

Thank you all for the replies. That helps a lot even in this small 
patch.  :)

On 8/30/2012 12:02 AM, Guennadi Liakhovetski wrote:
> On Wed, 29 Aug 2012, Sylwester Nawrocki wrote:
>
>> Hi,
>>
>> On 08/29/2012 12:11 PM, Josh Wu wrote:
>>> This patch fix the bug: ISI driver's platform data became invalid
>>> when isi platform data's attribution is __initdata.
>>>
>>> If the isi platform data is passed as __initdata. Then we need store
>>> it in driver allocated memory. otherwise when we use it out of the
>>> probe() function, then the isi platform data is invalid.
>>>
>>> Signed-off-by: Josh Wu <josh.wu at atmel.com>
>>> ---
>>>   drivers/media/platform/soc_camera/atmel-isi.c |   12 +++++++++++-
>>>   1 file changed, 11 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/media/platform/soc_camera/atmel-isi.c b/drivers/media/platform/soc_camera/atmel-isi.c
>>> index ec3f6a0..dc0fdec 100644
>>> --- a/drivers/media/platform/soc_camera/atmel-isi.c
>>> +++ b/drivers/media/platform/soc_camera/atmel-isi.c
>>> @@ -926,6 +926,7 @@ static int __devexit atmel_isi_remove(struct platform_device *pdev)
>>>   	clk_put(isi->mck);
>>>   	clk_unprepare(isi->pclk);
>>>   	clk_put(isi->pclk);
>>> +	kfree(isi->pdata);
>>>   	kfree(isi);
>>>   
>>>   	return 0;
>>> @@ -968,8 +969,15 @@ static int __devinit atmel_isi_probe(struct platform_device *pdev)
>>>   		goto err_alloc_isi;
>>>   	}
>>>   
>>> +	isi->pdata = kzalloc(sizeof(struct isi_platform_data), GFP_KERNEL);
>>> +	if (!isi->pdata) {
>>> +		ret = -ENOMEM;
>>> +		dev_err(&pdev->dev, "Can't allocate isi platform data!\n");
>>> +		goto err_alloc_isi_pdata;
>>> +	}
>>> +	memcpy(isi->pdata, pdata, sizeof(struct isi_platform_data));
>>> +
>> Why not just embed struct isi_platform_data in struct atmel_isi and drop this
>> another kzalloc() ?
>> Then you could simply do isi->pdata = *pdata.
>>
>> Also, is this going to work when this driver is build and as a module
>> and its loading is deferred past system booting ? At that time the driver's
>> platform data may be well discarded.
> Right, it will be gone, I think.
>
>> You may wan't to duplicate it on the
>> running boards in board code with kmemdup() or something.
> How about removing __initdata from board code?
>
> Thanks
> Guennadi
> ---
> Guennadi Liakhovetski, Ph.D.
> Freelance Open-Source Software Developer
> http://www.open-technology.de/
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Best Regards,
Josh Wu


From jg1.han at samsung.com  Thu Aug 30 03:10:11 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 30 Aug 2012 16:10:11 +0900
Subject: [PATCH] pwm: Call pwm_enable() before pwm_config()
In-Reply-To: <50364FA4.7000401@metafoo.de>
References: <217877237.2758643.1345731587941.JavaMail.root@advansee.com>
 <50364FA4.7000401@metafoo.de>
Message-ID: <002001cd867e$7e964130$7bc2c390$%han@samsung.com>

On Friday, August 24, 2012 12:44 AM, Lars-Peter Clausen wrote:
> 
> On 08/23/2012 04:19 PM, Beno?t Th?baudeau wrote:
> > Some PWM drivers enable the clock of the PWM peripheral in pwm_enable(). Hence,
> > for these drivers, a call to pwm_config() does not have any effect before
> > pwm_enable() has been called.
> >
> > This patch fixes the PWM users to make sure that they call pwm_enable() before
> > pwm_config().
> >
> > This fixes the first setting of brightness through sysfs that had no effect with
> > leds-pwm and the i.MX PWM driver.
> 
> But isn't this a bug in the PWM peripheral driver? With this change the PWM
> will start with the old settings first. While this is not so much of a problem
> for a backlight (although it might cause a short flickering) it might cause
> problems for other applications, like using the PWM pin as a timing generator.
> In my opinion it's better to fix the PWM peripheral drivers which have this
> problem instead of trying to work around it in every user of the PWM API.

Hi Lars-Peter Clausen,

I think so.
It would be better to fix the PWM peripheral drivers.


Best regards,
Jingoo Han

> 
> - Lars
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From t.figa at samsung.com  Thu Aug 30 03:31:37 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:37 +0200
Subject: [PATCH RESEND 0/6] ARM: EXYNOS: Add support for Trats board using
 device tree
Message-ID: <1346311903-15920-1-git-send-email-t.figa@samsung.com>

This patch series adds basic device tree support for Samsung Trats board
along with any necessary prerequisites.

In addition it refactors Exynos4 dts include files to split parts common to
the whole Exynos4 part from parts specific to Exynos4210 to allow further
extension of Exynos4210 dts include file and addition of include files for
other SoCs from Exynos4 line.

Dependencies:
-> [PATCH v5] mmc: sdhci-s3c: Add device tree support
http://www.spinics.net/lists/linux-samsung-soc/msg12056.html
-> [PATCH v5 2/2] regulator: add device tree support for max8997
http://www.spinics.net/lists/kernel/msg1328117.html

This is a resend, because previous messages somehow did not get to the mailing
lists.

Tomasz Figa (6):
  ARM: dts: Move parts common to Exynos4 from Exynos4210.dtsi to
    Exynos4.dtsi
  ARM: EXYNOS: exynos4-dt: Use exynos4 prefix instead of exynos4210
  ARM: Exynos4: dts: Specify address and size cells for i2c controllers
  ARM: Exynos4: Add OF compatibility lookups for Exynos4 i2c adapters
  ARM: EXYNOS: Increase maximum possible memory bank size to 512MiB
  ARM: Exynos: Add basic dts file for Samsung Trats board

 arch/arm/boot/dts/exynos4.dtsi             | 418 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210-trats.dts     | 287 ++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi          | 377 +-------------------------
 arch/arm/mach-exynos/Makefile.boot         |   2 +-
 arch/arm/mach-exynos/include/mach/memory.h |   4 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c     |  34 ++-
 6 files changed, 734 insertions(+), 388 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4.dtsi
 create mode 100644 arch/arm/boot/dts/exynos4210-trats.dts

-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:39 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:39 +0200
Subject: [PATCH 2/6] ARM: EXYNOS: exynos4-dt: Use exynos4 prefix instead of
 exynos4210
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-3-git-send-email-t.figa@samsung.com>

Since mach-exynos4-dt.c is also going to be used for other SoCs from Exynos4
line, rename internal structures and functions to use exynos4_ prefix, instead
of exynos4210_.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/mach-exynos4-dt.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b2b5d5f..8dad4ec 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -1,5 +1,5 @@
 /*
- * Samsung's Exynos4210 flattened device tree enabled machine
+ * Samsung's Exynos4 flattened device tree enabled machine
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
@@ -36,7 +36,7 @@
  * at some point, the drivers should be capable of parsing all the platform
  * data from the device tree.
  */
-static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
+static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
 				"exynos4210-uart.0", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
@@ -66,19 +66,19 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 	{},
 };
 
-static void __init exynos4210_dt_map_io(void)
+static void __init exynos4_dt_map_io(void)
 {
 	exynos_init_io(NULL, 0);
 	s3c24xx_init_clocks(24000000);
 }
 
-static void __init exynos4210_dt_machine_init(void)
+static void __init exynos4_dt_machine_init(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table,
-				exynos4210_auxdata_lookup, NULL);
+				exynos4_auxdata_lookup, NULL);
 }
 
-static char const *exynos4210_dt_compat[] __initdata = {
+static char const *exynos4_dt_compat[] __initdata = {
 	"samsung,exynos4210",
 	NULL
 };
@@ -86,11 +86,11 @@ static char const *exynos4210_dt_compat[] __initdata = {
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
 	/* Maintainer: Thomas Abraham <thomas.abraham at linaro.org> */
 	.init_irq	= exynos4_init_irq,
-	.map_io		= exynos4210_dt_map_io,
+	.map_io		= exynos4_dt_map_io,
 	.handle_irq	= gic_handle_irq,
-	.init_machine	= exynos4210_dt_machine_init,
+	.init_machine	= exynos4_dt_machine_init,
 	.init_late	= exynos_init_late,
 	.timer		= &exynos4_timer,
-	.dt_compat	= exynos4210_dt_compat,
+	.dt_compat	= exynos4_dt_compat,
 	.restart        = exynos4_restart,
 MACHINE_END
-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:41 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:41 +0200
Subject: [PATCH 4/6] ARM: Exynos4: Add OF compatibility lookups for Exynos4 i2c
 adapters
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-5-git-send-email-t.figa@samsung.com>

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/mach-exynos4-dt.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8dad4ec..0391c84 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -61,6 +61,22 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
 				"exynos4210-spi.1", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
 				"exynos4210-spi.2", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
+				"s3c2440-i2c.0", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
+				"s3c2440-i2c.1", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
+				"s3c2440-i2c.2", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
+				"s3c2440-i2c.3", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
+				"s3c2440-i2c.4", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
+				"s3c2440-i2c.5", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
+				"s3c2440-i2c.6", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
+				"s3c2440-i2c.7", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
 	{},
-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:38 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:38 +0200
Subject: [PATCH 1/6] ARM: dts: Move parts common to Exynos4 from
 Exynos4210.dtsi to Exynos4.dtsi
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-2-git-send-email-t.figa@samsung.com>

Most definitions from Exynos4210.dtsi can be applied for other SoCs from
Exynos4 line as well, so move the common part into separate file that
can be included by dtsi files of other Exynos4 SoCs (as well as current
Exynos4210.dtsi).

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/boot/dts/exynos4.dtsi    | 402 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4210.dtsi | 377 +----------------------------------
 2 files changed, 403 insertions(+), 376 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4.dtsi

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
new file mode 100644
index 0000000..5e99503
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -0,0 +1,402 @@
+/*
+ * Samsung's Exynos4 SoC series common device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *		www.linaro.org
+ *
+ * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos4 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		spi0 = &spi_0;
+		spi1 = &spi_1;
+		spi2 = &spi_2;
+	};
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		cpu-offset = <0x8000>;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x1000>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+	};
+
+	watchdog at 10060000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x10060000 0x100>;
+		interrupts = <0 43 0>;
+	};
+
+	rtc at 10070000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x10070000 0x100>;
+		interrupts = <0 44 0>, <0 45 0>;
+	};
+
+	keypad at 100A0000 {
+		compatible = "samsung,s5pv210-keypad";
+		reg = <0x100A0000 0x100>;
+		interrupts = <0 109 0>;
+	};
+
+	sdhci at 12510000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12510000 0x100>;
+		interrupts = <0 73 0>;
+	};
+
+	sdhci at 12520000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12520000 0x100>;
+		interrupts = <0 74 0>;
+	};
+
+	sdhci at 12530000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12530000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12540000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12540000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	serial at 13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 13820000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13820000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	serial at 13830000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13830000 0x100>;
+		interrupts = <0 55 0>;
+	};
+
+	i2c at 13860000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13860000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 13870000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13870000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 13880000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13880000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 13890000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x13890000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 138A0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138A0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 138B0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138B0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c at 138C0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138C0000 0x100>;
+		interrupts = <0 64 0>;
+	};
+
+	i2c at 138D0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x138D0000 0x100>;
+		interrupts = <0 65 0>;
+	};
+
+	spi_0: spi at 13920000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13920000 0x100>;
+		interrupts = <0 66 0>;
+		tx-dma-channel = <&pdma0 7>; /* preliminary */
+		rx-dma-channel = <&pdma0 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_1: spi at 13930000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13930000 0x100>;
+		interrupts = <0 67 0>;
+		tx-dma-channel = <&pdma1 7>; /* preliminary */
+		rx-dma-channel = <&pdma1 6>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	spi_2: spi at 13940000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x13940000 0x100>;
+		interrupts = <0 68 0>;
+		tx-dma-channel = <&pdma0 9>; /* preliminary */
+		rx-dma-channel = <&pdma0 8>; /* preliminary */
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 12680000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12680000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		pdma1: pdma at 12690000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x12690000 0x1000>;
+			interrupts = <0 36 0>;
+		};
+	};
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf2: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf3: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk0: gpio-controller at 11000040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk1: gpio-controller at 11000060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk2: gpio-controller at 11000080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpk3: gpio-controller at 110000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl0: gpio-controller at 110000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl1: gpio-controller at 110000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpl2: gpio-controller at 11000100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 11000120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 11000140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 11000160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11000180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 110001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 110001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 110001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x110001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11000C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11000C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11000C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11000C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11000C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 02891fe..4672367 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,249 +19,12 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
-	interrupt-parent = <&gic>;
-
-	aliases {
-		spi0 = &spi_0;
-		spi1 = &spi_1;
-		spi2 = &spi_2;
-	};
-
-	gic:interrupt-controller at 10490000 {
-		compatible = "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		cpu-offset = <0x8000>;
-		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
-	};
-
-	combiner:interrupt-controller at 10440000 {
-		compatible = "samsung,exynos4210-combiner";
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		reg = <0x10440000 0x1000>;
-		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
-	};
-
-	watchdog at 10060000 {
-		compatible = "samsung,s3c2410-wdt";
-		reg = <0x10060000 0x100>;
-		interrupts = <0 43 0>;
-	};
-
-	rtc at 10070000 {
-		compatible = "samsung,s3c6410-rtc";
-		reg = <0x10070000 0x100>;
-		interrupts = <0 44 0>, <0 45 0>;
-	};
-
-	keypad at 100A0000 {
-		compatible = "samsung,s5pv210-keypad";
-		reg = <0x100A0000 0x100>;
-		interrupts = <0 109 0>;
-	};
-
-	sdhci at 12510000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12510000 0x100>;
-		interrupts = <0 73 0>;
-	};
-
-	sdhci at 12520000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12520000 0x100>;
-		interrupts = <0 74 0>;
-	};
-
-	sdhci at 12530000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12530000 0x100>;
-		interrupts = <0 75 0>;
-	};
-
-	sdhci at 12540000 {
-		compatible = "samsung,exynos4210-sdhci";
-		reg = <0x12540000 0x100>;
-		interrupts = <0 76 0>;
-	};
-
-	serial at 13800000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13800000 0x100>;
-		interrupts = <0 52 0>;
-	};
-
-	serial at 13810000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13810000 0x100>;
-		interrupts = <0 53 0>;
-	};
-
-	serial at 13820000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13820000 0x100>;
-		interrupts = <0 54 0>;
-	};
-
-	serial at 13830000 {
-		compatible = "samsung,exynos4210-uart";
-		reg = <0x13830000 0x100>;
-		interrupts = <0 55 0>;
-	};
-
-	i2c at 13860000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13860000 0x100>;
-		interrupts = <0 58 0>;
-	};
-
-	i2c at 13870000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13870000 0x100>;
-		interrupts = <0 59 0>;
-	};
-
-	i2c at 13880000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13880000 0x100>;
-		interrupts = <0 60 0>;
-	};
-
-	i2c at 13890000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x13890000 0x100>;
-		interrupts = <0 61 0>;
-	};
-
-	i2c at 138A0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138A0000 0x100>;
-		interrupts = <0 62 0>;
-	};
-
-	i2c at 138B0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138B0000 0x100>;
-		interrupts = <0 63 0>;
-	};
-
-	i2c at 138C0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138C0000 0x100>;
-		interrupts = <0 64 0>;
-	};
-
-	i2c at 138D0000 {
-		compatible = "samsung,s3c2440-i2c";
-		reg = <0x138D0000 0x100>;
-		interrupts = <0 65 0>;
-	};
-
-	spi_0: spi at 13920000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13920000 0x100>;
-		interrupts = <0 66 0>;
-		tx-dma-channel = <&pdma0 7>; /* preliminary */
-		rx-dma-channel = <&pdma0 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_1: spi at 13930000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13930000 0x100>;
-		interrupts = <0 67 0>;
-		tx-dma-channel = <&pdma1 7>; /* preliminary */
-		rx-dma-channel = <&pdma1 6>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi_2: spi at 13940000 {
-		compatible = "samsung,exynos4210-spi";
-		reg = <0x13940000 0x100>;
-		interrupts = <0 68 0>;
-		tx-dma-channel = <&pdma0 9>; /* preliminary */
-		rx-dma-channel = <&pdma0 8>; /* preliminary */
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	amba {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "arm,amba-bus";
-		interrupt-parent = <&gic>;
-		ranges;
-
-		pdma0: pdma at 12680000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12680000 0x1000>;
-			interrupts = <0 35 0>;
-		};
-
-		pdma1: pdma at 12690000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x12690000 0x1000>;
-			interrupts = <0 36 0>;
-		};
-	};
 
 	gpio-controllers {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		gpio-controller;
-		ranges;
-
-		gpa0: gpio-controller at 11400000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400000 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpa1: gpio-controller at 11400020 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400020 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpb: gpio-controller at 11400040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc0: gpio-controller at 11400060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpc1: gpio-controller at 11400080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd0: gpio-controller at 114000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpd1: gpio-controller at 114000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpe0: gpio-controller at 114000E0 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x114000E0 0x20>;
@@ -292,30 +55,6 @@
 			#gpio-cells = <4>;
 		};
 
-		gpf0: gpio-controller at 11400180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11400180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf1: gpio-controller at 114001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf2: gpio-controller at 114001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpf3: gpio-controller at 114001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x114001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
 		gpj0: gpio-controller at 11000000 {
 			compatible = "samsung,exynos4-gpio";
 			reg = <0x11000000 0x20>;
@@ -327,119 +66,5 @@
 			reg = <0x11000020 0x20>;
 			#gpio-cells = <4>;
 		};
-
-		gpk0: gpio-controller at 11000040 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000040 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk1: gpio-controller at 11000060 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000060 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk2: gpio-controller at 11000080 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000080 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpk3: gpio-controller at 110000A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl0: gpio-controller at 110000C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl1: gpio-controller at 110000E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110000E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpl2: gpio-controller at 11000100 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000100 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy0: gpio-controller at 11000120 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000120 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy1: gpio-controller at 11000140 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000140 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy2: gpio-controller at 11000160 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000160 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy3: gpio-controller at 11000180 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000180 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy4: gpio-controller at 110001A0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001A0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy5: gpio-controller at 110001C0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001C0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpy6: gpio-controller at 110001E0 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x110001E0 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx0: gpio-controller at 11000C00 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C00 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx1: gpio-controller at 11000C20 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C20 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx2: gpio-controller at 11000C40 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C40 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpx3: gpio-controller at 11000C60 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x11000C60 0x20>;
-			#gpio-cells = <4>;
-		};
-
-		gpz: gpio-controller at 03860000 {
-			compatible = "samsung,exynos4-gpio";
-			reg = <0x03860000 0x20>;
-			#gpio-cells = <4>;
-		};
 	};
 };
-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:40 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:40 +0200
Subject: [PATCH 3/6] ARM: Exynos4: dts: Specify address and size cells for i2c
 controllers
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-4-git-send-email-t.figa@samsung.com>

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/boot/dts/exynos4.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 5e99503..5935588 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -116,48 +116,64 @@
 	};
 
 	i2c at 13860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13860000 0x100>;
 		interrupts = <0 58 0>;
 	};
 
 	i2c at 13870000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13870000 0x100>;
 		interrupts = <0 59 0>;
 	};
 
 	i2c at 13880000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13880000 0x100>;
 		interrupts = <0 60 0>;
 	};
 
 	i2c at 13890000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13890000 0x100>;
 		interrupts = <0 61 0>;
 	};
 
 	i2c at 138A0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138A0000 0x100>;
 		interrupts = <0 62 0>;
 	};
 
 	i2c at 138B0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138B0000 0x100>;
 		interrupts = <0 63 0>;
 	};
 
 	i2c at 138C0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138C0000 0x100>;
 		interrupts = <0 64 0>;
 	};
 
 	i2c at 138D0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138D0000 0x100>;
 		interrupts = <0 65 0>;
-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:42 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:42 +0200
Subject: [PATCH 5/6] ARM: EXYNOS: Increase maximum possible memory bank size to
 512MiB
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-6-git-send-email-t.figa@samsung.com>

Some boards have larger memory banks than 256MiB. This patch increses
maximum bank size for Exynos-based boards to 512MiB.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/include/mach/memory.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
index 374ef2c..d4db508 100644
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ b/arch/arm/mach-exynos/include/mach/memory.h
@@ -15,8 +15,8 @@
 
 #define PLAT_PHYS_OFFSET		UL(0x40000000)
 
-/* Maximum of 256MiB in one bank */
+/* Maximum of 512MiB in one bank */
 #define MAX_PHYSMEM_BITS	32
-#define SECTION_SIZE_BITS	28
+#define SECTION_SIZE_BITS	29
 
 #endif /* __ASM_ARCH_MEMORY_H */
-- 
1.7.12



From t.figa at samsung.com  Thu Aug 30 03:31:43 2012
From: t.figa at samsung.com (Tomasz Figa)
Date: Thu, 30 Aug 2012 09:31:43 +0200
Subject: [PATCH 6/6] ARM: Exynos: Add basic dts file for Samsung Trats board
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <1346311903-15920-7-git-send-email-t.figa@samsung.com>

This commit adds basic device tree for Exynos4210-based Trats board.

Currently it provides support for eMMC over sdhci and MAX8997 PMIC.

Signed-off-by: Tomasz Figa <t.figa at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/boot/dts/exynos4210-trats.dts | 287 +++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/Makefile.boot     |   2 +-
 2 files changed, 288 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-trats.dts

diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
new file mode 100644
index 0000000..a9cd2d0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -0,0 +1,287 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+
+/ {
+	model = "Samsung Trats based on Exynos4210";
+	compatible = "samsung,trats", "samsung,exynos4210";
+
+	memory {
+		reg =  <0x40000000 0x20000000
+			0x60000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
+	};
+
+	wakeup_eint: interrupt-controller-wakeup-eint {
+		compatible = "samsung,exynos4210-wakeup-eint";
+		reg = <0x11000000 0x1000>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts =	<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+				<0 32 0>;
+	};
+
+	vemmc_reg: voltage-regulator at 0 {
+	        compatible = "regulator-fixed";
+		regulator-name = "VMEM_VDD_2.8V";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpk0 2 1 0 0>;
+	};
+
+	sdhci_emmc: sdhci at 12510000 {
+		bus-width = <8>;
+		non-removable;
+		gpios = <&gpk0 0 2 0 3>,
+			<&gpk0 1 2 0 3>,
+			<&gpk0 3 2 2 3>,
+			<&gpk0 4 2 2 3>,
+			<&gpk0 5 2 2 3>,
+			<&gpk0 6 2 2 3>,
+			<&gpk1 3 3 3 3>,
+			<&gpk1 4 3 3 3>,
+			<&gpk1 5 3 3 3>,
+			<&gpk1 6 3 3 3>;
+		vmmc-supply = &vemmc_reg;
+	};
+
+	i2c at 138B0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <100000>;
+		gpios = <&gpb 6 3 3 0>,
+			<&gpb 7 3 3 0>;
+
+		max8997_pmic at 66 {
+			compatible = "maxim,max8997-pmic";
+			interrupt-parent = <&wakeup_eint>;
+
+			reg = <0x66>;
+			interrupts = <4 0>, <3 0>;
+
+			max8997,pmic-buck1-uses-gpio-dvs;
+			max8997,pmic-buck2-uses-gpio-dvs;
+			max8997,pmic-buck5-uses-gpio-dvs;
+
+			max8997,pmic-ignore-gpiodvs-side-effect;
+			max8997,pmic-buck125-default-dvs-idx = <0>;
+
+			max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
+						         <&gpx0 6 1 0 0>,
+							 <&gpl0 0 1 0 0>;
+
+			max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+							 <1250000>, <1200000>,
+							 <1150000>, <1100000>,
+							 <1000000>, <950000>;
+
+			max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
+							 <950000>,  <900000>,
+							 <1100000>, <1000000>,
+							 <950000>,  <900000>;
+
+			max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+							 <1200000>, <1200000>,
+							 <1200000>, <1200000>,
+							 <1200000>, <1200000>;
+
+			regulators {
+				valive_reg: LDO2 {
+				     regulator-name = "VALIVE_1.1V_C210";
+				     regulator-min-microvolt = <1100000>;
+				     regulator-max-microvolt = <1100000>;
+				     regulator-always-on;
+				};
+
+				vusb_reg: LDO3 {
+				     regulator-name = "VUSB_1.1V_C210";
+				     regulator-min-microvolt = <1100000>;
+				     regulator-max-microvolt = <1100000>;
+				};
+
+				vmipi_reg: LDO4 {
+				     regulator-name = "VMIPI_1.8V";
+				     regulator-min-microvolt = <1800000>;
+				     regulator-max-microvolt = <1800000>;
+				};
+
+				vpda_reg: LDO6 {
+				     regulator-name = "VCC_1.8V_PDA";
+				     regulator-min-microvolt = <1800000>;
+				     regulator-max-microvolt = <1800000>;
+				     regulator-always-on;
+				};
+
+				vcam_reg: LDO7 {
+				     regulator-name = "CAM_ISP_1.8V";
+				     regulator-min-microvolt = <1800000>;
+				     regulator-max-microvolt = <1800000>;
+				};
+
+				vusbdac_reg: LDO8 {
+				     regulator-name = "VUSB/VDAC_3.3V_C210";
+				     regulator-min-microvolt = <3300000>;
+				     regulator-max-microvolt = <3300000>;
+				};
+
+				vccpda_reg: LDO9 {
+				     regulator-name = "VCC_2.8V_PDA";
+				     regulator-min-microvolt = <2800000>;
+				     regulator-max-microvolt = <2800000>;
+				     regulator-always-on;
+				};
+
+				vpll_reg: LDO10 {
+				     regulator-name = "VPLL_1.1V_C210";
+				     regulator-min-microvolt = <1100000>;
+				     regulator-max-microvolt = <1100000>;
+				     regulator-always-on;
+				};
+
+				vcclcd_reg: LDO13 {
+				     regulator-name = "VCC_3.3V_LCD";
+				     regulator-min-microvolt = <3300000>;
+				     regulator-max-microvolt = <3300000>;
+				};
+
+				vlcd_reg: LDO15 {
+				     regulator-name = "VLCD_2.2V";
+				     regulator-min-microvolt = <2200000>;
+				     regulator-max-microvolt = <2200000>;
+				};
+
+				camsensor_reg: LDO16 {
+				     regulator-name = "CAM_SENSOR_IO_1.8V";
+				     regulator-min-microvolt = <1800000>;
+				     regulator-max-microvolt = <1800000>;
+				};
+
+				vddq_reg: LDO21 {
+				     regulator-name = "VDDQ_M1M2_1.2V";
+				     regulator-min-microvolt = <1200000>;
+				     regulator-max-microvolt = <1200000>;
+				     regulator-always-on;
+				};
+
+				varm_breg: BUCK1 {
+				     regulator-name = "VARM_1.2V_C210";
+				     regulator-min-microvolt = <900000>;
+				     regulator-max-microvolt = <1350000>;
+				     regulator-always-on;
+				};
+
+				vint_breg: BUCK2 {
+				     regulator-name = "VINT_1.1V_C210";
+				     regulator-min-microvolt = <900000>;
+				     regulator-max-microvolt = <1100000>;
+				     regulator-always-on;
+				};
+
+				camisp_breg: BUCK4 {
+				     regulator-name = "CAM_ISP_CORE_1.2V";
+				     regulator-min-microvolt = <1200000>;
+				     regulator-max-microvolt = <1200000>;
+				};
+
+				vmem_breg: BUCK5 {
+				     regulator-name = "VMEM_1.2V_C210";
+				     regulator-min-microvolt = <1200000>;
+				     regulator-max-microvolt = <1200000>;
+				     regulator-always-on;
+				};
+
+				vccsub_breg: BUCK7 {
+				     regulator-name = "VCC_SUB_2.0V";
+				     regulator-min-microvolt = <2000000>;
+				     regulator-max-microvolt = <2000000>;
+				     regulator-always-on;
+				};
+
+				safe1_sreg: ESAFEOUT1 {
+				     regulator-name = "SAFEOUT1";
+				     regulator-always-on;
+				};
+
+				safe2_sreg: ESAFEOUT2 {
+				     regulator-name = "SAFEOUT2";
+				     regulator-boot-on;
+				};
+			};
+		};
+	};
+
+	keypad at 100A0000 {
+		status = "disabled";
+	};
+
+	sdhci at 12520000 {
+		status = "disabled";
+	};
+
+	sdhci at 12530000 {
+		status = "disabled";
+	};
+
+	sdhci at 12540000 {
+		status = "disabled";
+	};
+
+	i2c at 13860000 {
+		status = "disabled";
+	};
+
+	i2c at 13870000 {
+		status = "disabled";
+	};
+
+	i2c at 13880000 {
+		status = "disabled";
+	};
+
+	i2c at 13890000 {
+		status = "disabled";
+	};
+
+	i2c at 138A0000 {
+		status = "disabled";
+	};
+
+	i2c at 138C0000 {
+		status = "disabled";
+	};
+
+	i2c at 138D0000 {
+		status = "disabled";
+	};
+
+	spi_0: spi at 13920000 {
+		status = "disabled";
+	};
+
+	spi_1: spi at 13930000 {
+		status = "disabled";
+	};
+
+	spi_2: spi at 13940000 {
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
index 31bd181..a79d999 100644
--- a/arch/arm/mach-exynos/Makefile.boot
+++ b/arch/arm/mach-exynos/Makefile.boot
@@ -1,5 +1,5 @@
    zreladdr-y	+= 0x40008000
 params_phys-y	:= 0x40000100
 
-dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
+dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb exynos4210-trats.dtb
 dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
-- 
1.7.12



From ludovic.desroches at atmel.com  Thu Aug 30 03:35:35 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Thu, 30 Aug 2012 09:35:35 +0200
Subject: [PATCH v11 3/4] drivers/i2c/busses/i2c-at91.c: add new driver
In-Reply-To: <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>
References: <cover.1345618760.git.n.voss@weinmann.de>
 <4f3dcfbf1e8eab3e251ab3558e9e1e9123643928.1345618760.git.n.voss@weinmann.de>,
 <503B4919.6080306@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECC330@EXMDB06.org.aalto.fi>,
 <503B623C.4030304@atmel.com>
 <BC0F374A1C27184AB96177CDFEC2F54225ECD36E@EXMDB06.org.aalto.fi>
 <EF2E73589CA71846A15D0B2CDF79505D090EC3D6F6@wm021.weinmann.com>
Message-ID: <503F17C7.5010807@atmel.com>

Le 08/27/2012 03:32 PM, Voss, Nikolaus a ?crit :
> Hi Adian,
>
> Yanes Martinez Adrian wrote on Monday, August 27, 2012 2:46 PM:
>> Le 08/27/2012 12:40 PM, Yanes Martinez Adrian a ?crit :
>>> Hi Ludovic,
>>>
>>>> Tested on at91rm9200, at91sam9261, at91sam9g20 and at91sam9m10 with
>>>> eeprom, temperature sensor and rtc devices (and wolfson chip for
>>>> sam9g20).
>>>
>>> concerning the at91rm9200, what was the amount of bytes you
>> transmitted?
>>>
>>
>>> I have only checked that I can communicate with i2c devices so the
>>> amount is very low (1-4 bytes).
>>
>> IIRC it was from >7 bytes when the issues appeared.
>>
>>> Some months ago I performed some testing[1] with the previous version of
>>> the patch and the main conclusion was that the absence of PDC in the
>>> AT91RM9200 made this driver unusable in such platform.
>
> I didn't get your last post  in that thread. In my opinion RM9200 should really
> be excluded from being configured with this driver, what's your opinion
> Ludovic?
>

After investigation, the transmission issue may concern rm9200, 9261, 
9260 and 9263. The main cause of this issue is we do not have clock 
stretching.
Using a low clock frequency should reduce the underrun issue so this 
driver can be used on those chips but a warning have to be added to 
indicate this potential issue. I'll do it when I'll resend patches for 
DT support.


Regards

Ludovic

> Regards,
> Niko
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>



From w.sang at pengutronix.de  Thu Aug 30 04:25:18 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 30 Aug 2012 10:25:18 +0200
Subject: MX28 & finding out boot mode
Message-ID: <20120830082518.GA27306@pengutronix.de>

Hi,

is there a way to find out how the MX28 was booted? I could read out the
bootmode-pins for indication. Still, either by button or by empty NAND,
the CPU could have been booted via USB recovery mode. And going through
the docs and the bootlets code, I can't find a way to determine if USB
recovery was used.

So, can USB recovery mode be detected somehow? Then, this and reading
pins should be sufficent, no?

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From b29396 at freescale.com  Thu Aug 30 04:12:16 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Thu, 30 Aug 2012 16:12:16 +0800
Subject: MX28 & finding out boot mode
In-Reply-To: <20120830082518.GA27306@pengutronix.de>
References: <20120830082518.GA27306@pengutronix.de>
Message-ID: <20120830081215.GA1198@shlinux2.ap.freescale.net>

On Thu, Aug 30, 2012 at 04:25:18PM +0800, Wolfram Sang wrote:
> Hi,
> 
> is there a way to find out how the MX28 was booted? I could read out the
> bootmode-pins for indication. Still, either by button or by empty NAND,
> the CPU could have been booted via USB recovery mode. And going through
> the docs and the bootlets code, I can't find a way to determine if USB
> recovery was used.
> 
> So, can USB recovery mode be detected somehow? Then, this and reading
> pins should be sufficent, no?
> 
Add Frank&Peter who may know it.

Regards
Dong Aisheng



From rnayak at ti.com  Thu Aug 30 04:37:37 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 30 Aug 2012 14:07:37 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <20120830000849.GD25765@n2100.arm.linux.org.uk>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <20120830000849.GD25765@n2100.arm.linux.org.uk>
Message-ID: <503F2651.50609@ti.com>

On Thursday 30 August 2012 05:38 AM, Russell King - ARM Linux wrote:
> On Wed, Aug 29, 2012 at 02:26:15PM +0530, Rajendra Nayak wrote:
>> Moving to Common clk framework for OMAP would mean we no longer use
>> internal lookup mechanism like omap_clk_get_by_name().
>> get rid of all its usage mostly from hwmod and omap_device
>> code.
>>
>> Also use IS_ERR_OR_NULL() for error checking.
>
> This is wrong.  IS_ERR() is the only check you should ever use with clk_get().

okay, thanks, will fix.




From rnayak at ti.com  Thu Aug 30 04:39:00 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 30 Aug 2012 14:09:00 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
Message-ID: <503F26A4.3050902@ti.com>

On Thursday 30 August 2012 05:45 AM, Turquette, Mike wrote:
> On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak<rnayak at ti.com>  wrote:
>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
>> index d7f55e4..a3831a2 100644
>> --- a/arch/arm/mach-omap2/clock44xx_data.c
>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
>> @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
>>          CLK(NULL,       "dss_tv_clk",&dss_tv_clk,    CK_443X),
>>          CLK(NULL,       "dss_48mhz_clk",&dss_48mhz_clk, CK_443X),
>>          CLK(NULL,       "dss_dss_clk",&dss_dss_clk,   CK_443X),
>> +       CLK(NULL,       "dss_fck",&dss_fck,       CK_443X),
>>          CLK("omapdss_dss",      "ick",&dss_fck,       CK_443X),
>
> Is it right to re-use dss_fck for the "ick" here?  I think it is due
> to omap4 modulemode stuff but I don't have DM in front of me and
> wanted a double-check...

yes, its because of the wierdness of DSS clocks where a so-called
optional clock is actually a function clock.

>
> Regards,
> Mike



From B29397 at freescale.com  Thu Aug 30 04:47:21 2012
From: B29397 at freescale.com (Chen Peter-B29397)
Date: Thu, 30 Aug 2012 08:47:21 +0000
Subject: MX28 & finding out boot mode
In-Reply-To: <20120830081215.GA1198@shlinux2.ap.freescale.net>
References: <20120830082518.GA27306@pengutronix.de>
 <20120830081215.GA1198@shlinux2.ap.freescale.net>
Message-ID: <F281D0F91ED19E4D8E63A7504E8A649803C63005@039-SN2MPN1-023.039d.mgd.msft.net>

 
> > is there a way to find out how the MX28 was booted? I could read out
> the
> > bootmode-pins for indication. Still, either by button or by empty NAND,
> > the CPU could have been booted via USB recovery mode. And going through
> > the docs and the bootlets code, I can't find a way to determine if USB
> > recovery was used.
> >
> > So, can USB recovery mode be detected somehow? Then, this and reading
> > pins should be sufficent, no?
> >
> Add Frank&Peter who may know it.
As far as I know, the romcode decides which mode is used, I haven't read
romcode, so don't know priority of below booting selection.

OTP, button, boot media (if no boot media, will go to USB recovery mode)

Why do you need to know USB recovery mode at your code? 

Peter



From keguang.zhang at gmail.com  Thu Aug 30 04:51:34 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Thu, 30 Aug 2012 16:51:34 +0800
Subject: [PATCH v3] clk: add Loongson1B clock support
Message-ID: <1346316694-5270-1-git-send-email-keguang.zhang@gmail.com>

This adds clock support to Loongson1B SoC using the common clock
infrastructure.

Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
---
 drivers/clk/Makefile   |    1 +
 drivers/clk/clk-ls1x.c |  111 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-ls1x.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..018ec57 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)	+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/
 obj-$(CONFIG_ARCH_U300)		+= clk-u300.o
 obj-$(CONFIG_ARCH_INTEGRATOR)	+= versatile/
+obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 0000000..f20b750
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <loongson1.h>
+
+#define OSC	33
+
+static DEFINE_SPINLOCK(_lock);
+
+static int ls1x_pll_clk_enable(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static void ls1x_pll_clk_disable(struct clk_hw *hw)
+{
+}
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 pll, rate;
+
+	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+	rate = ((12 + (pll & 0x3f)) * 1000000) +
+		((((pll >> 8) & 0x3ff) * 1000000) >> 10);
+	rate *= OSC;
+	rate >>= 1;
+
+	return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+	.enable = ls1x_pll_clk_enable,
+	.disable = ls1x_pll_clk_disable,
+	.recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static struct clk * __init clk_register_pll(struct device *dev,
+	 const char *name, const char *parent_name, unsigned long flags)
+{
+	struct clk_hw *hw;
+	struct clk *clk;
+	struct clk_init_data init;
+
+	/* allocate the divider */
+	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
+	if (!hw) {
+		pr_err("%s: could not allocate clk_hw\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	init.name = name;
+	init.ops = &ls1x_pll_clk_ops;
+	init.flags = flags | CLK_IS_BASIC;
+	init.parent_names = (parent_name ? &parent_name : NULL);
+	init.num_parents = (parent_name ? 1 : 0);
+	hw->init = &init;
+
+	/* register the clock */
+	clk = clk_register(dev, hw);
+
+	if (IS_ERR(clk))
+		kfree(hw);
+
+	return clk;
+}
+
+void __init ls1x_clk_init(void)
+{
+	struct clk *clk;
+
+	clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
+	clk_prepare_enable(clk);
+
+	clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
+			DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "cpu", NULL);
+
+	clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+			DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "dc", NULL);
+
+	clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
+			CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
+			DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "ahb", NULL);
+	clk_register_clkdev(clk, "stmmaceth", NULL);
+
+	clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
+	clk_prepare_enable(clk);
+	clk_register_clkdev(clk, "apb", NULL);
+	clk_register_clkdev(clk, "serial8250", NULL);
+}
-- 
1.7.1



From w.sang at pengutronix.de  Thu Aug 30 05:13:18 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 30 Aug 2012 11:13:18 +0200
Subject: MX28 & finding out boot mode
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A649803C63005@039-SN2MPN1-023.039d.mgd.msft.net>
References: <20120830082518.GA27306@pengutronix.de>
 <20120830081215.GA1198@shlinux2.ap.freescale.net>
 <F281D0F91ED19E4D8E63A7504E8A649803C63005@039-SN2MPN1-023.039d.mgd.msft.net>
Message-ID: <20120830091318.GC27306@pengutronix.de>

On Thu, Aug 30, 2012 at 08:47:21AM +0000, Chen Peter-B29397 wrote:
>  
> > > is there a way to find out how the MX28 was booted? I could read out
> > the
> > > bootmode-pins for indication. Still, either by button or by empty NAND,
> > > the CPU could have been booted via USB recovery mode. And going through
> > > the docs and the bootlets code, I can't find a way to determine if USB
> > > recovery was used.
> > >
> > > So, can USB recovery mode be detected somehow? Then, this and reading
> > > pins should be sufficent, no?
> > >
> > Add Frank&Peter who may know it.

Thanks.

> As far as I know, the romcode decides which mode is used, I haven't read
> romcode, so don't know priority of below booting selection.

For me, this is not about priorities, I just want to know which mode was
really used in the end :)

> Why do you need to know USB recovery mode at your code? 

Some customers want this to handle the recovery case differently than
the standard case.

Thanks for the help!

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From peter.ujfalusi at ti.com  Thu Aug 30 05:16:11 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 30 Aug 2012 12:16:11 +0300
Subject: [PATCH v2 0/3] MFD/GPIO: Add twl6040 GPO driver
In-Reply-To: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
References: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <503F2F5B.6020304@ti.com>

Hi Samuel, Linus,

On 08/16/2012 03:13 PM, Peter Ujfalusi wrote:
> Hello,
> 
> Changes since v1:
> - Removed the ti,use-gpo property from DT bindings
> - Register the GPO driver if we booted with DT blob or in legacy if the pdata
>   for the GPO driver is present
> - DT binding Documentation update
> 
> The Documentation update has reference to the twl6040.dtsi file which will be
> created to hold the common/static properties for the twl6040.
> To avoid cross tree merge issues later I have only included the Documentation
> update to this series and I will send the actual .dtsi/.dts changes via
> linux-omap. If this is not a problem.

Did you had time to look at this series? Do you want me to resend it?

Thank you,
P?ter

> 
> The dependencies for this series are in mainline and I think this series can
> go via GPIO if Samuel agrees with the changes.
> 
> Intro mail from v1:
> 
> The following series adds support for the GPO (General Purpose Output) on the
> twl6040/41 audio chip.
> The series has been tested on SDP4430, compile tested for x86_64 and x86_32 bit
> to be sure it does not introduce build breakage.
> 
> Regards,
> Peter
> ---
> Peter Ujfalusi (3):
>   mfd: twl6040: Fix GPO mask
>   mfd: twl6040: Add twl6040-gpio child
>   gpio: Add basic support for TWL6040 GPOs
> 
>  Documentation/devicetree/bindings/mfd/twl6040.txt |    9 +-
>  drivers/gpio/Kconfig                              |    7 +
>  drivers/gpio/Makefile                             |    1 +
>  drivers/gpio/gpio-twl6040.c                       |  137 +++++++++++++++++++++
>  drivers/mfd/twl6040-core.c                        |   15 +++
>  include/linux/mfd/twl6040.h                       |   11 ++-
>  6 files changed, 175 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/gpio/gpio-twl6040.c
> 




From peter.ujfalusi at ti.com  Thu Aug 30 05:19:22 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 30 Aug 2012 12:19:22 +0300
Subject: [PATCH v2 02/14] MFD: twl4030-audio: Convert to use devm_kzalloc
In-Reply-To: <1346147410.2182.96.camel@sokoban>
References: <1344954162-7985-1-git-send-email-peter.ujfalusi@ti.com>
 <1344954162-7985-3-git-send-email-peter.ujfalusi@ti.com>
 <1346147410.2182.96.camel@sokoban>
Message-ID: <503F301A.1090200@ti.com>

Hi Tero,

On 08/28/2012 12:50 PM, Tero Kristo wrote:
> On Tue, 2012-08-14 at 17:22 +0300, Peter Ujfalusi wrote:
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> 
> I think this one could use a short commit message, also about why
> kfree():s are dropped (handled internally by devm_* etc.)

I don't like empty commit messages either but this patch is self explaining I
would think that the commit title explains it.

-- 
P?ter


From B29397 at freescale.com  Thu Aug 30 05:40:05 2012
From: B29397 at freescale.com (Chen Peter-B29397)
Date: Thu, 30 Aug 2012 09:40:05 +0000
Subject: MX28 & finding out boot mode
In-Reply-To: <20120830091318.GC27306@pengutronix.de>
References: <20120830082518.GA27306@pengutronix.de>
 <20120830081215.GA1198@shlinux2.ap.freescale.net>
 <F281D0F91ED19E4D8E63A7504E8A649803C63005@039-SN2MPN1-023.039d.mgd.msft.net>
 <20120830091318.GC27306@pengutronix.de>
Message-ID: <F281D0F91ED19E4D8E63A7504E8A649803C630EF@039-SN2MPN1-023.039d.mgd.msft.net>

 
> 
> Some customers want this to handle the recovery case differently than
> the standard case.
> 

If you can't find method at datasheet (like reading some registers), a workaround
is according to usb register, usually, usbcmd.rs (pull-up DP) stands for usb is using
or not.

1. Make sure usbcmd.rs = 0 is the default value.
2. Before the usb code is running, the usbcmd.rs should be 0 at normal mode
So, get a flag before usb code is running

if (usbcmd.rs == 0)
	usb_recover_mode = 0;
else
	usb_recover_mode = 1;


Peter

> Thanks for the help!
> 
>    Wolfram
> 
> --
> Pengutronix e.K.                           | Wolfram Sang
> |
> Industrial Linux Solutions                 | http://www.pengutronix.de/
> |



From w.sang at pengutronix.de  Thu Aug 30 05:55:55 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 30 Aug 2012 11:55:55 +0200
Subject: MX28 & finding out boot mode
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A649803C630EF@039-SN2MPN1-023.039d.mgd.msft.net>
References: <20120830082518.GA27306@pengutronix.de>
 <20120830081215.GA1198@shlinux2.ap.freescale.net>
 <F281D0F91ED19E4D8E63A7504E8A649803C63005@039-SN2MPN1-023.039d.mgd.msft.net>
 <20120830091318.GC27306@pengutronix.de>
 <F281D0F91ED19E4D8E63A7504E8A649803C630EF@039-SN2MPN1-023.039d.mgd.msft.net>
Message-ID: <20120830095555.GE27306@pengutronix.de>

On Thu, Aug 30, 2012 at 09:40:05AM +0000, Chen Peter-B29397 wrote:
>  
> > 
> > Some customers want this to handle the recovery case differently than
> > the standard case.
> > 
> 
> If you can't find method at datasheet (like reading some registers), a workaround

I hoped there was one bit in the persistent registers where the ROM
code stores such stuff. Sadly, those are usually not documented, so I
asked.

> is according to usb register, usually, usbcmd.rs (pull-up DP) stands for usb is using
> or not.

I think this is too much of a workaround for me :)

Thanks anyway!

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From b-cousson at ti.com  Thu Aug 30 07:57:11 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Thu, 30 Aug 2012 13:57:11 +0200
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <503F26A4.3050902@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com>
Message-ID: <503F5517.4010100@ti.com>

On 08/30/2012 10:39 AM, Rajendra Nayak wrote:
> On Thursday 30 August 2012 05:45 AM, Turquette, Mike wrote:
>> On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak<rnayak at ti.com>  wrote:
>>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c
>>> b/arch/arm/mach-omap2/clock44xx_data.c
>>> index d7f55e4..a3831a2 100644
>>> --- a/arch/arm/mach-omap2/clock44xx_data.c
>>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
>>> @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
>>>          CLK(NULL,       "dss_tv_clk",&dss_tv_clk,    CK_443X),
>>>          CLK(NULL,       "dss_48mhz_clk",&dss_48mhz_clk, CK_443X),
>>>          CLK(NULL,       "dss_dss_clk",&dss_dss_clk,   CK_443X),
>>> +       CLK(NULL,       "dss_fck",&dss_fck,       CK_443X),
>>>          CLK("omapdss_dss",      "ick",&dss_fck,       CK_443X),
>>
>> Is it right to re-use dss_fck for the "ick" here?  I think it is due
>> to omap4 modulemode stuff but I don't have DM in front of me and
>> wanted a double-check...
> 
> yes, its because of the wierdness of DSS clocks where a so-called
> optional clock is actually a function clock.

Not only, it is a hack to allow the DSS to be enabled whenever a DSS
submodule has to be enabled. Since they are sharing the ick, it will
enable the modulemode when the DISPC will be enabled.

That hack should disappear as soon as the DSS will be able to handle the
PM dependency between DSS submodules and the DSS itself using pm_runtime
parent/child link.
And then we will have to remove this fake ick modulemode clock node and
let hwmod handle that properly.

Tomi already cleaned the DSS part, I guess it should be upstreamed soon,
if this is not already the case.

Regards,
Benoit



From lee.jones at linaro.org  Thu Aug 30 08:31:48 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 Aug 2012 13:31:48 +0100
Subject: [PATCH 18/22] ARM: ux500: Rename MSP board file to something
 more meaningful
In-Reply-To: <CACRpkdaJcfLNzZ4s4NOyBLROjNbNfP8m0EewFkwe6tTrCS-Hog@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-19-git-send-email-lee.jones@linaro.org>
 <CACRpkdaJcfLNzZ4s4NOyBLROjNbNfP8m0EewFkwe6tTrCS-Hog@mail.gmail.com>
Message-ID: <20120830123146.GF14145@gmail.com>

On Tue, Aug 14, 2012 at 01:20:32PM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:47 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > The 'msp' board file does more than just register MSP devices. It
> > also registers some other components necessary to get audio working
> > on ux500 based platforms; such as the PCM and Machine Drivers. For
> > that reason we're changing the filename to be more encompassing -
> > 'audio'.
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Ideally I want Ola to confirm this but it looks OK to me.
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Poke for Ola.

I'm guessing it's okay, as Ola told me to rename the file 'msp' -> 'audio'.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From pawel.moll at arm.com  Thu Aug 30 08:33:47 2012
From: pawel.moll at arm.com (Pawel Moll)
Date: Thu, 30 Aug 2012 13:33:47 +0100
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <1346330027.2623.4.camel@hornet>

Hi Linus,

I'm working on moving the VE clocking into driver/clk on top of your
Realview change, and just spotted one minor issue...

On Mon, 2012-08-06 at 17:32 +0100, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This converts the ARM RealView machine over to using the common
> clock. The approach is similar to the one used for the Integrator,
> and we're reusing the ICST wrapper code.
[...]
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 7f0b5ca..89b726d 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -40,4 +40,11 @@ config COMMON_CLK_WM831X
>            Supports the clocking subsystem of the WM831x/2x series of
>           PMICs from Wolfson Microlectronics.
> 
> +config COMMON_CLK_VERSATILE
> +       tristate "Clock driver for ARM Reference designs"

It can't really be a "tristate", can it? To my mind there is no way of
making it a module, so a "bool" seems more appropriate?

> +       depends on ARCH_INTEGRATOR || ARCH_REALVIEW
> +       ---help---
> +          Supports clocking on ARM Reference designs Integrator/AP,
> +         Integrator/CP, RealView PB1176, EB, PB11MP and PBX.
> +
>  endmenu

Cheers!

Pawe?




From lee.jones at linaro.org  Thu Aug 30 09:12:04 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 Aug 2012 14:12:04 +0100
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120821164244.GA4672@core.coreip.homeip.net>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
 <20120821164244.GA4672@core.coreip.homeip.net>
Message-ID: <20120830131202.GG14145@gmail.com>

> Sorry for the delay. Yes, this shoudl be fine, but since it is
> essentially a revert of the original patch it should be pushed in as
> such.

How's this?

Author: Lee Jones <lee.jones at linaro.org>
Date:   Thu Aug 30 14:08:19 2012 +0100

    Revert "input: ab8500-ponkey: Create AB8500 domain IRQ mapping"
    
    This reverts commit ca3b3faf9bee4dc5df4f10eae2d1e48f7de0a8ad.
    
    There was a plan to place ab8500_irq_get_virq() calls in each AB8500
    child device prior to requesting an IRQ, but as we're no longer using
    Device Tree to collect our IRQ numbers, it's actually better to allow
    the core to do this during device registration time. So the IRQ number
    we pull from its resource has already been converted to a virtual IRQ.
    
    CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
    CC: linux-input at vger.kernel.org
    Acked-by: Linus Walleij <linus.walleij at linaro.org>
    Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
index f06231b..84ec691 100644
--- a/drivers/input/misc/ab8500-ponkey.c
+++ b/drivers/input/misc/ab8500-ponkey.c
@@ -74,8 +74,8 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
 
        ponkey->idev = input;
        ponkey->ab8500 = ab8500;
-       ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
-       ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
+       ponkey->irq_dbf = irq_dbf;
+       ponkey->irq_dbr = irq_dbr;
 
        input->name = "AB8500 POn(PowerOn) Key";
        input->dev.parent = &pdev->dev;


From lee.jones at linaro.org  Thu Aug 30 09:18:08 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 30 Aug 2012 14:18:08 +0100
Subject: [PATCH 04/22] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <CACRpkdZse9Nq1acoAujV8ojhRKxykNX0ymcr51QAoanUbDW14g@mail.gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-5-git-send-email-lee.jones@linaro.org>
 <CACRpkda_xOyu9BFGRK4xTsXOO9RCJu7BbU-kPGpttVkR6mDMZg@mail.gmail.com>
 <20120820115914.GP8450@gmail.com>
 <CACRpkdZse9Nq1acoAujV8ojhRKxykNX0ymcr51QAoanUbDW14g@mail.gmail.com>
Message-ID: <20120830131807.GI14145@gmail.com>

On Mon, Aug 27, 2012 at 04:09:46PM -0700, Linus Walleij wrote:
> On Mon, Aug 20, 2012 at 4:59 AM, Lee Jones <lee.jones at linaro.org> wrote:
> > On Tue, Aug 14, 2012 at 10:51:02AM +0200, Linus Walleij wrote:
> 
> >> But wait. These are just local statics. Surelty you can put these into
> >> struct ux500_msp instead? Here it looks like these will be used for
> >> all ports, so MSP2 will enable the pins requested by MSP1 etc
> >> completely broken. So put it into the struct ux500_msp state
> >> container from ux500_msp_i2s.h where it belongs.
> >>
> >> Refer to drivers/tty/serial/amba-pl011.c when in trouble. This
> >> one is a good pinctrl example.
> >
> > How do you see the MSP1 and MSP3 usage protection working if I hide it
> > all away in MSP specific structs?
> 
> Usage protection? Sorry not following. Please elaborate...

Don't worry about it, I think I sorted it.

Please see the lastest version of the patch (sent on 24th Aug).

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From festevam at gmail.com  Thu Aug 30 10:09:49 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 30 Aug 2012 11:09:49 -0300
Subject: [PATCH] clk: mxs: Register USB clocks for mx23
In-Reply-To: <CAOMZO5AME0NXarMF_rarYJeQ4-rGc+DpV7nvL4OeQj+LfkLLQw@mail.gmail.com>
References: <1340148392-9847-1-git-send-email-festevam@gmail.com>
 <20120620143830.GF2253@S2101-09.ap.freescale.net>
 <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>
 <20120806030014.GB22302@S2101-09.ap.freescale.net>
 <CAOMZO5AME0NXarMF_rarYJeQ4-rGc+DpV7nvL4OeQj+LfkLLQw@mail.gmail.com>
Message-ID: <CAOMZO5CZjOopAy1EhWOOCszgJQNW52Z-UPjzVwU6MAp_HtDCzw@mail.gmail.com>

Shawn,

On Mon, Aug 13, 2012 at 12:06 AM, Fabio Estevam <festevam at gmail.com> wrote:
> Shawn,
>
> On Mon, Aug 6, 2012 at 12:00 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>
>> Probably, no, as I plan to freeze the addition to clkdev lookup table
>> and replace it with DT clock lookup.
>
> Could you please suggest how can I register the USB clocks for mx23?
> Any example I can refer to implement a "DT clock lookup"?

Ping?

I saw some patches from you that changes the way dt clocks are
registered for mx23/mx28, but not sure if these were applied or not.

Please let me know how should I proceed regarding mx23 usb clocks registration.

Regards,

Fabio Estevam


From nsekhar at ti.com  Thu Aug 30 10:16:32 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Thu, 30 Aug 2012 19:46:32 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1345684176-21472-4-git-send-email-mporter@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
Message-ID: <503F75C0.1050507@ti.com>

Hi Matt,

On 8/23/2012 6:39 AM, Matt Porter wrote:
> Removes use of the DaVinci EDMA private DMA API and replaces
> it with use of the DMA engine API.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>

I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
initialize after applying the patch.

root at arago:~# dmesg | grep -i spi                                               
spi_davinci spi_davinci.1: request RX DMA channel failed                        

without these 3 patches, SPI flash is detected fine (same kernel 
configuration):

root at arago:~# dmesg | grep spi                                                  
spi_davinci spi_davinci.1: DMA: supported                                       
spi_davinci spi_davinci.1: DMA: RX channel: 18, TX channel: 19, event queue: 0  
spi_davinci spi_davinci.1: master is unqueued, this is deprecated               
m25p80 spi1.0: m25p64 (8192 Kbytes)                                             
spi_davinci spi_davinci.1: Controller at 0xfef0e000                             

Any idea what could be wrong? This is v3.6-rc3 kernel. I can provide 
full bootlogs or any other debug information if that helps.

Thanks,
Sekhar


From mporter at ti.com  Thu Aug 30 10:43:07 2012
From: mporter at ti.com (Matt Porter)
Date: Thu, 30 Aug 2012 10:43:07 -0400
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <503F75C0.1050507@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
 <503F75C0.1050507@ti.com>
Message-ID: <20120830144307.GA26737@beef>

On Thu, Aug 30, 2012 at 07:46:32PM +0530, Sekhar Nori wrote:
> Hi Matt,
> 
> On 8/23/2012 6:39 AM, Matt Porter wrote:
> > Removes use of the DaVinci EDMA private DMA API and replaces
> > it with use of the DMA engine API.
> > 
> > Signed-off-by: Matt Porter <mporter at ti.com>
> 
> I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
> initialize after applying the patch.
> 
> root at arago:~# dmesg | grep -i spi                                               
> spi_davinci spi_davinci.1: request RX DMA channel failed                        

Hi Sekhar,

Most likely CONFIG_TI_EDMA is off as it defaults to off in the v3
series. Try enabling this and if it's the problem then this error
path can be fixed to properly fallback to PIO only or fail to
initialize as needed.

-Matt


From robherring2 at gmail.com  Thu Aug 30 11:18:52 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 30 Aug 2012 10:18:52 -0500
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120829233159.GS18957@n2100.arm.linux.org.uk>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk>
Message-ID: <503F845C.10406@gmail.com>

On 08/29/2012 06:31 PM, Russell King - ARM Linux wrote:
> On Wed, Aug 29, 2012 at 05:49:55PM -0500, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> In preparation for mulit-platform support, convert all platforms' ARCH_
>> definition to a hidden option and create a new choice option.
> 
> This is churn and annoyance.  It's definitely annoyance for the
> autobuilder because it's going to have to have symbols changed in the
> seed configs. It's annoyance for people because they're going to have
> to manually reselect their SoC types in every build they do.
> 
> I think also that Kconfig will end up on 'make oldconfig' selecting
> one of the platforms, deselecting all the dependencies on that platform,
> which then means you'll have thousands of Kconfig options to answer.
> 
> I've been there with x86 configs, and spent something like an hour
> piecing together a configuration for my laptop, answering one question
> every couple of seconds.  That is not a nice experience to inflict on
> people.

Then what do you suggest? I can think of a few alternatives.

Leave the current name and make the hidden option a new name like
ARCH_xx_OPTIONS. This would require renaming ARCH_xxx for each platform
all over the tree. I don't care to sign up for that task...

Move platforms one by one out of the choice as they are converted. I
can't think of a reason for a platform to be in both places except we
would have to figure out something for getting DEBUG_LL to work.

Rob


From robherring2 at gmail.com  Thu Aug 30 11:27:15 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 30 Aug 2012 10:27:15 -0500
Subject: [PATCH 00/10] Make mach/gpio.h optional
In-Reply-To: <20120829234030.GV18957@n2100.arm.linux.org.uk>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <20120829234030.GV18957@n2100.arm.linux.org.uk>
Message-ID: <503F8653.40908@gmail.com>

On 08/29/2012 06:40 PM, Russell King - ARM Linux wrote:
> On Wed, Aug 29, 2012 at 05:31:26PM -0500, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> This series makes mach/gpio.h optional like we have done for other mach
>> headers in preparation for multi-platform kernel images. Unfortunately,
>> it adds more mach includes to drivers/, but really they are just now
>> explicitly included and easily found.
> 
> This in general looks like a complete backwards step rather than a forwards
> step for multi-platform kernels.  All these drivers are not going to be
> usable in multi-platform kernel images, because with mach/ includes they're
> not going to be picking up the correct set of headers.

These drivers are already not usable. I'm just making that obvious.

> So all these SoC types might as well not be part of the multi-platform
> project until they get their act together with their headers.

Precisely the point. It is pushing the problem to the sub-arches so they
can clean-up their stuff if they want to get into a multi-plat image. I
expect we will see some clean starting in parallel with this. The omap
folks are working omap headers and there were some clean-ups for Marvell
parts posted. Arnd has platform_data header series he is working on.

Rob



From nicolas.pitre at linaro.org  Thu Aug 30 11:59:14 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 30 Aug 2012 11:59:14 -0400 (EDT)
Subject: [PATCH - 2/2] arm: disable caches based on config option
In-Reply-To: <1346337826-27232-2-git-send-email-m-karicheri2@ti.com>
References: <1346337826-27232-1-git-send-email-m-karicheri2@ti.com>
 <1346337826-27232-2-git-send-email-m-karicheri2@ti.com>
Message-ID: <alpine.LFD.2.02.1208301156390.1784@xanadu.home>

On Thu, 30 Aug 2012, Murali Karicheri wrote:

> CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE are available
> to allow disabling of D-Cache and I-Cache. However the compressed version
> of head.S currently doesn't check these variables. This patch will fix
> this issue and is written similar to the uncompressed version of head.S
> 
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>

Acked-by: nicolas Pitre <nico at linaro.org>

You may submit your patch to http://www.arm.linux.org.uk/developer/patches/.


> ---
>  arch/arm/boot/compressed/head.S |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index b8c64b8..e1d2124 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -659,6 +659,12 @@ __armv7_mmu_cache_on:
>  #ifdef CONFIG_CPU_ENDIAN_BE8
>  		orr	r0, r0, #1 << 25	@ big-endian page tables
>  #endif
> +#ifdef CONFIG_CPU_DCACHE_DISABLE
> +		bic	r0, r0, #1 << 2
> +#endif
> +#ifdef CONFIG_CPU_ICACHE_DISABLE
> +		bic	r0, r0, #1 << 12
> +#endif
>  		orrne	r0, r0, #1		@ MMU enabled
>  		movne	r1, #0xfffffffd		@ domain 0 = client
>  		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
> -- 
> 1.7.9.5
> 


From m-karicheri2 at ti.com  Thu Aug 30 12:17:14 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Thu, 30 Aug 2012 16:17:14 +0000
Subject: [PATCH] arm:davinci: clk - migrate to new common clock API
In-Reply-To: <5029F079.8010901@ti.com>
References: <1343926428-5210-1-git-send-email-m-karicheri2@ti.com>
 <5029F079.8010901@ti.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041AD30F@DFLE12.ent.ti.com>

Agreed. So I am not re-sending this patch.

Murali Karicheri
Software Design Engineer


>> -----Original Message-----
>> From: Nori, Sekhar
>> Sent: Tuesday, August 14, 2012 2:30 AM
>> To: Karicheri, Muralidharan
>> Cc: linux-arm-kernel at lists.infradead.org; davinci-linux-open-
>> source at linux.davincidsp.com; linux-keystone at list.ti.com - Linux developers for Keystone
>> family of devices (May contain non-TIers); Turquette, Mike; Chemparathy, Cyril;
>> linux at arm.linux.org.uk
>> Subject: Re: [PATCH] arm:davinci: clk - migrate to new common clock API
>> 
>> 
>> Hi Murali,
>> 
>> On 8/2/2012 10:23 PM, Murali Karicheri wrote:
>> > As a first step towards migrating davinci platforms to use common clock
>> > framework, replace all instances of clk_enable() with clk_prepare_enable()
>> > and clk_disable() with clk_disable_unprepare(). Until the platform is
>> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> > adds a might_sleep() call and would work without any issues.
>> >
>> > This will make it easy later to switch to common clk based implementation
>> > of clk driver from DaVinci specific driver.
>> >
>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> 
>> Queuing this patch for v3.7. The subject line should have ARM in
>> capitals for consistency. Also, you are not really migrating to new API
>> in this patch - just preparing for migration so I prefer:
>> 
>> "ARM: davinci: convert platform code to use clk_prepare/clk_unprepare"
>> 
>> I will make this change while committing.
>> 
>> Thanks,
>> Sekhar

From paul at pwsan.com  Thu Aug 30 12:19:14 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 30 Aug 2012 16:19:14 +0000 (UTC)
Subject: TI SoC Linux BoF @ Linux Plumbers Conference: tomorrow
In-Reply-To: <B1BA3B0F-098D-4AC8-A514-6862D0F98EC6@ti.com>
References: <alpine.DEB.2.00.1208291837040.1619@utopia.booyaka.com>
 <CAN5iSWp9LJjC9B3fiAJhuYVkfNzC98WkvQKPiVt8+tqxr==COg@mail.gmail.com>
 <CAGF5oy_-3g3A8Eadn7uRm5srPCsuufFZ42estfRuAWy4JiqQ-w@mail.gmail.com>,
 <CAGF5oy9hf8ys=Cqvhto8tPnW=iuf2V3sRmJW+aoAmZS4Sdroyg@mail.gmail.com>
 <B1BA3B0F-098D-4AC8-A514-6862D0F98EC6@ti.com>
Message-ID: <alpine.DEB.2.00.1208301615430.8816@utopia.booyaka.com>

On Wed, 29 Aug 2012, Locke, Matthew wrote:

> During lunch

On the schedule[1], the TI Linux BoF is from 12:35pm to 13:20pm.  So it 
looks like people can get a quick lunch outside from 12:05pm to 12:30pm, 
then head to Nautilus 1 for the BoF.

It's all informal, so please drop in and say hello if you're using 
OMAP/AM/DM/C6x/whatever chips.


- Paul

1. http://summit.linuxplumbersconf.org/lpc-2012/2012-08-30/display?


From tomi.valkeinen at ti.com  Thu Aug 30 12:42:13 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Thu, 30 Aug 2012 19:42:13 +0300
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <503F5517.4010100@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
Message-ID: <1346344933.2327.43.camel@deskari>

On Thu, 2012-08-30 at 13:57 +0200, Benoit Cousson wrote:
> On 08/30/2012 10:39 AM, Rajendra Nayak wrote:
> > On Thursday 30 August 2012 05:45 AM, Turquette, Mike wrote:
> >> On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak<rnayak at ti.com>  wrote:
> >>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c
> >>> b/arch/arm/mach-omap2/clock44xx_data.c
> >>> index d7f55e4..a3831a2 100644
> >>> --- a/arch/arm/mach-omap2/clock44xx_data.c
> >>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> >>> @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
> >>>          CLK(NULL,       "dss_tv_clk",&dss_tv_clk,    CK_443X),
> >>>          CLK(NULL,       "dss_48mhz_clk",&dss_48mhz_clk, CK_443X),
> >>>          CLK(NULL,       "dss_dss_clk",&dss_dss_clk,   CK_443X),
> >>> +       CLK(NULL,       "dss_fck",&dss_fck,       CK_443X),
> >>>          CLK("omapdss_dss",      "ick",&dss_fck,       CK_443X),
> >>
> >> Is it right to re-use dss_fck for the "ick" here?  I think it is due
> >> to omap4 modulemode stuff but I don't have DM in front of me and
> >> wanted a double-check...
> > 
> > yes, its because of the wierdness of DSS clocks where a so-called
> > optional clock is actually a function clock.
> 
> Not only, it is a hack to allow the DSS to be enabled whenever a DSS
> submodule has to be enabled. Since they are sharing the ick, it will
> enable the modulemode when the DISPC will be enabled.
> 
> That hack should disappear as soon as the DSS will be able to handle the
> PM dependency between DSS submodules and the DSS itself using pm_runtime
> parent/child link.
> And then we will have to remove this fake ick modulemode clock node and
> let hwmod handle that properly.
> 
> Tomi already cleaned the DSS part, I guess it should be upstreamed soon,
> if this is not already the case.

This is in 3.5. omapdss_dss is now the parent for the rest of the dss
submodules, and runtime PM is being used.

I think we should now revisit this dss clock handling to see if there
are any other changes required in the omapdss side, but I hope they are
already according to our discussions and correct.

 Tomi

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From linus.walleij at linaro.org  Thu Aug 30 12:37:58 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 18:37:58 +0200
Subject: [PATCH] ARM: clps711x: convert to clocksource/clockevents
Message-ID: <1346344678-18248-1-git-send-email-linus.walleij@linaro.org>

This converts the ageing clps711x timer driver to the modern
clocksource/clockevent API.

This was blind-coded using the datasheet, it'd be great if someone
who has this machine could test it.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/Kconfig                |    3 +-
 arch/arm/mach-clps711x/common.c |   59 +++++++++++++++++++++++++++++---------
 2 files changed, 47 insertions(+), 15 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 181b697..8a3da9e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -383,8 +383,9 @@ config ARCH_HIGHBANK
 config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 	select CPU_ARM720T
-	select ARCH_USES_GETTIMEOFFSET
 	select NEED_MACH_MEMORY_H
+	select GENERIC_CLOCKEVENTS
+	select CLKSRC_MMIO
 	help
 	  Support for Cirrus Logic 711x/721x/731x based boards.
 
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293b..850697f 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -26,6 +26,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
 
 #include <asm/sizes.h>
 #include <mach/hardware.h>
@@ -157,25 +159,42 @@ void __init clps711x_init_irq(void)
 	clps_writel(0, KBDEOI);
 }
 
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
+static void clps711x_set_mode(enum clock_event_mode mode,
+			  struct clock_event_device *evt)
 {
-	unsigned long hwticks;
-	hwticks = LATCH - (clps_readl(TC2D) & 0xffff);	/* since last underflow */
-	return (hwticks * (tick_nsec / 1000)) / LATCH;
+	u32 syscon;
+	u32 period = DIV_ROUND_CLOSEST(512000, HZ);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+	case CLOCK_EVT_MODE_RESUME:
+		/* Go into prescaler mode, program frequency */
+		syscon = clps_readl(SYSCON1);
+		syscon |= SYSCON1_TC2M;
+		clps_writel(syscon, SYSCON1);
+		clps_writel(period, TC2D);
+		break;
+	default:
+		break;
+	}
 }
 
+static struct clock_event_device clockevent_clps711x = {
+	.name		= "clps711x_tc2d",
+	.rating		= 300,
+	/* Only support periodic mode */
+	.features	= CLOCK_EVT_FEAT_PERIODIC,
+	.set_mode	= clps711x_set_mode,
+};
+
 /*
  * IRQ handler for the timer
  */
 static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
 {
-	timer_tick();
+	struct clock_event_device *evt = &clockevent_clps711x;
+
+	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 
@@ -190,17 +209,29 @@ static void __init clps711x_timer_init(void)
 	unsigned int syscon;
 
 	syscon = clps_readl(SYSCON1);
-	syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+	/* Timer 1 in free running mode */
+	syscon &= ~(SYSCON1_TC1M);
+	/* Timer 2 in prescale mode */
+	syscon |= SYSCON1_TC2M;
+	/* Set both timers to 512 kHz */
+	syscon |= (SYSCON1_TC1S | SYSCON1_TC2S);
 	clps_writel(syscon, SYSCON1);
 
-	clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+	/* Start timer 1 in free running mode */
+	clps_writel(0xFFFFU, TC1D);
+	if (clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+			"clps711x_tc1d", 512000, 300, 16,
+			clocksource_mmio_readl_down))
+		pr_err("timer: failed to initialize clps711x clock source\n");
 
+	/* Configure and register the clockevent */
+	clockevents_config_and_register(&clockevent_clps711x, 512000,
+					1, 0xFFFFU);
 	setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
 
 struct sys_timer clps711x_timer = {
 	.init		= clps711x_timer_init,
-	.offset		= clps711x_gettimeoffset,
 };
 
 void clps711x_restart(char mode, const char *cmd)
-- 
1.7.7.6



From linux at arm.linux.org.uk  Thu Aug 30 12:45:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 17:45:51 +0100
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <503F845C.10406@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk> <503F845C.10406@gmail.com>
Message-ID: <20120830164551.GY18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 10:18:52AM -0500, Rob Herring wrote:
> Then what do you suggest? I can think of a few alternatives.
> 
> Leave the current name and make the hidden option a new name like
> ARCH_xx_OPTIONS. This would require renaming ARCH_xxx for each platform
> all over the tree. I don't care to sign up for that task...

Well, requiring everyone to spend hours redoing their configuration also
isn't practical either.

> Move platforms one by one out of the choice as they are converted. I
> can't think of a reason for a platform to be in both places except we
> would have to figure out something for getting DEBUG_LL to work.

No you don't.  We've already decided how we're going to deal with
DEBUG_LL, and we are _not_ going to make that multi-platform.  You
select one of the output options, and that is it.  We've already
been moving in that direction, albiet slowly.  Again, anyone who wants
to be part of a multiplatform kernel better use the provided choice
or they will get no DEBUG_LL facility - simples.

That also means we can start to think about moving the mach/debug-macros.S
header elsewhere, remembering that this facility is shared between the
decompressor for debugging and the kernel.

Remember that DEBUG_LL is the low-level *debug* facility.  It is not
the early console, even if it ended up being used as such (which is
not something I really care for.)  Read the previous discussions on
this subject if you disagree, but I'm not changing my position over
DEBUG_LL because that will just require me to re-invent the facility
yet again (which is what DEBUG_LL is there to stop.)  It was _never_
intended to be an early console facility.


From santosh.shilimkar at ti.com  Thu Aug 30 12:49:54 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 30 Aug 2012 09:49:54 -0700
Subject: [PATCH - 2/2] arm: disable caches based on config option
In-Reply-To: <1346337826-27232-2-git-send-email-m-karicheri2@ti.com>
References: <1346337826-27232-1-git-send-email-m-karicheri2@ti.com>
 <1346337826-27232-2-git-send-email-m-karicheri2@ti.com>
Message-ID: <CAMQu2gyuVHEz-gUK3Tzqy4DPRwP+NWWjJTCYS=-RzFuszHw9Wg@mail.gmail.com>

On Thu, Aug 30, 2012 at 7:43 AM, Murali Karicheri <m-karicheri2 at ti.com> wrote:
> CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE are available
> to allow disabling of D-Cache and I-Cache. However the compressed version
> of head.S currently doesn't check these variables. This patch will fix
> this issue and is written similar to the uncompressed version of head.S
>
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From jason at lakedaemon.net  Thu Aug 30 12:52:24 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 12:52:24 -0400
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
Message-ID: <20120830165224.GR19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 07:14:47AM +0200, Andrew Lunn wrote:
> Tools like kisskb are good at finding build regressions in the kernel
> sources. However, regressions in the DT desscriptions are not found,
> because generally these build systems don't build the DT binary blobs.
> 
> Extend the ARM all target to build all enabled DTB files.
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

Acked-by: Jason Cooper <jason at lakedaemon.net>

I've CC'd stable to see if they want to pick this up.  It does depend on
having dtc built.  A patch already exists to build dtc on demand, but
I'm not sure if it has made it into mainline yet.  It may be in
Russell's queue.

thx,

Jason.

> ---
> v2: * in the help test
>     Only invoke dtbs if CONFIGUSE_OF=y
> 
>  arch/arm/Makefile |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 30eae87..0457ef4 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -268,7 +268,12 @@ else
>  KBUILD_IMAGE := zImage
>  endif
>  
> -all:	$(KBUILD_IMAGE)
> +# Build the DT binary blobs if we have OF configured
> +ifeq ($(CONFIG_USE_OF),y)
> +KBUILD_DTBS := dtbs
> +endif
> +
> +all:	$(KBUILD_IMAGE) $(KBUILD_DTBS)
>  
>  boot := arch/arm/boot
>  
> @@ -306,7 +311,7 @@ define archhelp
>    echo  '  uImage        - U-Boot wrapped zImage'
>    echo  '  bootpImage    - Combined zImage and initial RAM disk' 
>    echo  '                  (supply initrd image via make variable INITRD=<path>)'
> -  echo  '  dtbs          - Build device tree blobs for enabled boards'
> +  echo  '* dtbs          - Build device tree blobs for enabled boards'
>    echo  '  install       - Install uncompressed kernel'
>    echo  '  zinstall      - Install compressed kernel'
>    echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From linux at arm.linux.org.uk  Thu Aug 30 12:52:33 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 17:52:33 +0100
Subject: [PATCH 00/10] Make mach/gpio.h optional
In-Reply-To: <503F8653.40908@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <20120829234030.GV18957@n2100.arm.linux.org.uk> <503F8653.40908@gmail.com>
Message-ID: <20120830165233.GZ18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 10:27:15AM -0500, Rob Herring wrote:
> On 08/29/2012 06:40 PM, Russell King - ARM Linux wrote:
> > On Wed, Aug 29, 2012 at 05:31:26PM -0500, Rob Herring wrote:
> >> From: Rob Herring <rob.herring at calxeda.com>
> >>
> >> This series makes mach/gpio.h optional like we have done for other mach
> >> headers in preparation for multi-platform kernel images. Unfortunately,
> >> it adds more mach includes to drivers/, but really they are just now
> >> explicitly included and easily found.
> > 
> > This in general looks like a complete backwards step rather than a forwards
> > step for multi-platform kernels.  All these drivers are not going to be
> > usable in multi-platform kernel images, because with mach/ includes they're
> > not going to be picking up the correct set of headers.
> 
> These drivers are already not usable. I'm just making that obvious.

Yes, by undoing all the work I did cleaning up the gpio shite, which I
object to.

> > So all these SoC types might as well not be part of the multi-platform
> > project until they get their act together with their headers.
> 
> Precisely the point. It is pushing the problem to the sub-arches so they
> can clean-up their stuff if they want to get into a multi-plat image. I
> expect we will see some clean starting in parallel with this. The omap
> folks are working omap headers and there were some clean-ups for Marvell
> parts posted. Arnd has platform_data header series he is working on.

No, it is undoing the work I did getting rid of mach/gpio.h includes, and
tidying up the asm/gpio.h & mach/gpio.h crap, ensuring that stuff won't
work properly with mach/gpio.h includes, and encouraging everyone to move
to the right include - linux/gpio.h.  You're undoing all that work by
effectively saying "we want you to start using mach/gpio.h because this
patch is re-introducing it".

So, a very strong NAK against that from me.

If they're not able to be part of a multi-platform kernel as they stand,
and they're still not able after your patch series, you've not achieved
anything material, and the changes you propose are just pure churn.

If you're thinking that your patch series will spark cleanup work, then
you're mistaken - no one cares about gpio header files, if they did then
my cleanup to make stuff use asm/gpio.h or linux/gpio.h would have also
sparked cleanup, which it didn't.  So please stop daydreaming that patches
spark other people to do cleanups.

What sparks people into life is when you tell them that their favourite
arch can't be part of new feature Y because Z is incompatible.  They'll
then fix Z if they want feature Y.

Sure, no problem with getting rid of the empty gpio.h headers, and
ifdef'ing the mach/gpio.h include - but don't then go around changing
all those asm/gpio.h's into mach/gpio.h's.


From broonie at opensource.wolfsonmicro.com  Thu Aug 30 12:59:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 30 Aug 2012 09:59:08 -0700
Subject: [PATCH RESEND 1/4] ARM: OMAP2+: AM33XX: Add tps65910 device tree
 data
In-Reply-To: <20120829083129.GB3439@gmail.com>
References: <1342766789-28148-1-git-send-email-anilkumar@ti.com>
 <1342766789-28148-2-git-send-email-anilkumar@ti.com>
 <20120720095935.GQ4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13E9FA91E@DBDE01.ent.ti.com>
 <20120720113806.GW4495@opensource.wolfsonmicro.com>
 <331ABD5ECB02734CA317220B2BBEABC13EA01F1E@DBDE01.ent.ti.com>
 <20120723133400.GU4435@opensource.wolfsonmicro.com>
 <20120828112603.GC25786@gmail.com>
 <20120828172133.GH4534@opensource.wolfsonmicro.com>
 <20120829083129.GB3439@gmail.com>
Message-ID: <20120830165907.GC4356@opensource.wolfsonmicro.com>

On Wed, Aug 29, 2012 at 09:31:31AM +0100, Lee Jones wrote:
> On Tue, Aug 28, 2012 at 10:21:33AM -0700, Mark Brown wrote:

> > > The regulator-name property is used to populate constrains->name. Are
> > > you sure you still want them all removed?

> > Yes, of course.  There's no way that a generic .dtsi used for any
> > possible board could come up with a sensible value.

> So how should constrains->name be populated then? Would you prefer
> regulator-names moved to the .dts file(s), or something else?

Of course, yes.  The sole purpose of that field is to give a board
specific name to the supply.  It can't usefully be set by anything
except the board.


From shc_work at mail.ru  Thu Aug 30 13:02:10 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Thu, 30 Aug 2012 21:02:10 +0400
Subject: [PATCH] ARM: clps711x: convert to clocksource/clockevents
In-Reply-To: <1346344678-18248-1-git-send-email-linus.walleij@linaro.org>
References: <1346344678-18248-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <20120830210210.55e0899d.shc_work@mail.ru>

On Thu, 30 Aug 2012 18:37:58 +0200
Linus Walleij <linus.walleij at linaro.org> wrote:

> This converts the ageing clps711x timer driver to the modern
> clocksource/clockevent API.
The patch does not account for the changes that I sent to the mailing list
recently, where I did support different clock frequencies for the processor.

> This was blind-coded using the datasheet, it'd be great if someone
> who has this machine could test it.
...
> +	/* Set both timers to 512 kHz */
The patch uses a second timer, which does not allow its use for other purposes,
I can not test the functionality of the device in this case, unfortunately.

I have also tried to do something like this without using additional processor
resources, but not yet brought to the finish line yet.

-- 
Alexander Shiyan <shc_work at mail.ru>


From jason at lakedaemon.net  Thu Aug 30 13:12:36 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 13:12:36 -0400
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
Message-ID: <20120830171236.GS19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 07:39:12AM +0200, Andrew Lunn wrote:
> Linux-next has failed to compile for kirkwood since 23 August with:
> 
> arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
> arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)
> 
> Add missing <linux/sizes.h>
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

Applied to: fixes-for-v3.6

Also, I added a CC for stable so greg can pick it up.

thx,

Jason.

> ---
>  arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> index d933593..be90b7d 100644
> --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> @@ -10,6 +10,7 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/sizes.h>
>  #include <linux/platform_device.h>
>  #include <linux/mtd/partitions.h>
>  #include <linux/ata_platform.h>
> -- 
> 1.7.10.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jason at lakedaemon.net  Thu Aug 30 13:14:28 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 13:14:28 -0400
Subject: [GIT PULL] kirkwood fix for v3.6
Message-ID: <20120830171428.GT19437@titan.lakedaemon.net>

The following changes since commit b74ffd85e32d44e8ed405a2a0a175ef4cd39cf67:

  ARM: Kirkwood: fix Makefile.boot (2012-08-15 13:58:52 +0000)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6

Andrew Lunn (1):
      ARM: Kirkwood: Fix 'SZ_1M' undeclared here for db88f6281-bp-setup.c

 arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)


From plagnioj at jcrosoft.com  Thu Aug 30 13:14:46 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 30 Aug 2012 19:14:46 +0200
Subject: [PATCH 05/10] ARM: at91: explicitly include mach/gpio.h
In-Reply-To: <1346279496-26286-6-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-6-git-send-email-robherring2@gmail.com>
Message-ID: <20120830171446.GC7629@game.jcrosoft.org>

On 17:31 Wed 29 Aug     , Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove implicit inclusion of mach/gpio.h, add explict
> include of mach/gpio.h.
I'm going to drop it for 3.7 too

the attached patch will do the same but in a more simpler way

Best Regards,
J.
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From broonie at opensource.wolfsonmicro.com  Thu Aug 30 13:19:19 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 30 Aug 2012 10:19:19 -0700
Subject: [PATCH] clk: Make the generic clock API available by default
In-Reply-To: <503E8E6E.1010101@wwwdotorg.org>
References: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <503E8E6E.1010101@wwwdotorg.org>
Message-ID: <20120830171918.GE4356@opensource.wolfsonmicro.com>

On Wed, Aug 29, 2012 at 02:49:34PM -0700, Stephen Warren wrote:
> On 08/28/12 13:35, Mark Brown wrote:

> >@@ -674,6 +676,7 @@ config ARCH_TEGRA
> >  	select GENERIC_CLOCKEVENTS
> >  	select GENERIC_GPIO
> >  	select HAVE_CLK
> >+	select HAVE_CUSTOM_CLK

> For 3.7, Tegra will switch to the common clock framework. I think
> this patch would then disable that. How should we resolve this -
> rebase the Tegra common-clk tree on top of any branch containing
> this patch in order to remove that select statement?

I'd expect this to be applied on a separate branch so you should be able
to rebase your conversion on top of it or merge it into your branch
which should deal with things well enough I think?


From linus.walleij at linaro.org  Thu Aug 30 13:21:44 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 10:21:44 -0700
Subject: [PATCH] ARM: clps711x: convert to clocksource/clockevents
In-Reply-To: <20120830210210.55e0899d.shc_work@mail.ru>
References: <1346344678-18248-1-git-send-email-linus.walleij@linaro.org>
 <20120830210210.55e0899d.shc_work@mail.ru>
Message-ID: <CACRpkdYHenkDYnZ5W8xzR58ioK8=8-rfSQFrtpTqfGYy28-cSA@mail.gmail.com>

On Thu, Aug 30, 2012 at 10:02 AM, Alexander Shiyan <shc_work at mail.ru> wrote:
> On Thu, 30 Aug 2012 18:37:58 +0200
> Linus Walleij <linus.walleij at linaro.org> wrote:
>
>> This converts the ageing clps711x timer driver to the modern
>> clocksource/clockevent API.
>
> The patch does not account for the changes that I sent to the mailing list
> recently, where I did support different clock frequencies for the processor.

No problem, I can rebase on top of your patches as soon as you
submit them to ARM SoC so I can see them in linux-next.

>> This was blind-coded using the datasheet, it'd be great if someone
>> who has this machine could test it.
> ...
>> +     /* Set both timers to 512 kHz */
>
> The patch uses a second timer, which does not allow its use for other purposes,

What does this mean? Reading the datasheet it didn't say anything about
this timer being dedicated to something else.

I am using TC1D as clocksource and TC2D as clockevent, repurposing
it from the previous use as singe time source.

Doing "git grep TC1D" I cannot see any code in the kernel making use
of this timer?

I could think of things like the boot loader or firmware setting it up
to run in free-running mode ... in that case we use
it as clocksource without initialization as long as we know what
frequency it's running on.

As far as I could understand from the datasheet there is really
no way to actually disable these timers, so they always run
anyway?

> I have also tried to do something like this without using additional processor
> resources, but not yet brought to the finish line yet.

OK do you think you can switch the clps71x over to generic time and
clockevents inspired by this patch or so?

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Thu Aug 30 13:23:04 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 18:23:04 +0100
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830165224.GR19437@titan.lakedaemon.net>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
Message-ID: <20120830172304.GA18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> On Thu, Aug 30, 2012 at 07:14:47AM +0200, Andrew Lunn wrote:
> > Tools like kisskb are good at finding build regressions in the kernel
> > sources. However, regressions in the DT desscriptions are not found,
> > because generally these build systems don't build the DT binary blobs.
> > 
> > Extend the ARM all target to build all enabled DTB files.
> > 
> > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> 
> Acked-by: Jason Cooper <jason at lakedaemon.net>
> 
> I've CC'd stable to see if they want to pick this up.

That's not how stable works - and you'll probably receive a standard form
whinge from them about that.  Please read up on the submission requirements
to the stable kernel trees.

> It does depend on
> having dtc built.  A patch already exists to build dtc on demand, but
> I'm not sure if it has made it into mainline yet.  It may be in
> Russell's queue.

At the moment, the only stuff I have outstanding for -rc is:

36418c5 ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEM
df547e0 ARM: 7503/1: mm: only flush both pmd entries for classic MMU
ae3790b ARM: 7502/1: contextidr: avoid using bfi instruction during notifier
dbece45 ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores
d968d2b ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all addressbf88011 ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint accessa849088 ARM: Fix ioremap() of address zero

I have nothing queued for dtc building, and there's no sign of anything
new in the patch system.


From linus.walleij at linaro.org  Thu Aug 30 13:24:28 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 10:24:28 -0700
Subject: [PATCH] clk: convert ARM RealView to common clk
In-Reply-To: <1346330027.2623.4.camel@hornet>
References: <1344270728-7550-1-git-send-email-linus.walleij@stericsson.com>
 <1346330027.2623.4.camel@hornet>
Message-ID: <CACRpkdbEU6zWd6-SK+pAxSUd8Vow+3JP5ZkxdijZwYraekEW8g@mail.gmail.com>

On Thu, Aug 30, 2012 at 5:33 AM, Pawel Moll <pawel.moll at arm.com> wrote:
[Me]
>> +config COMMON_CLK_VERSATILE
>> +       tristate "Clock driver for ARM Reference designs"
>
> It can't really be a "tristate", can it? To my mind there is no way of
> making it a module, so a "bool" seems more appropriate?

You're right, I'll send a small fixup patch to Mike.

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Thu Aug 30 13:24:52 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 18:24:52 +0100
Subject: [PATCH 05/10] ARM: at91: explicitly include mach/gpio.h
In-Reply-To: <20120830171446.GC7629@game.jcrosoft.org>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-6-git-send-email-robherring2@gmail.com>
 <20120830171446.GC7629@game.jcrosoft.org>
Message-ID: <20120830172452.GB18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 07:14:46PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:31 Wed 29 Aug     , Rob Herring wrote:
> > From: Rob Herring <rob.herring at calxeda.com>
> > 
> > In preparation to remove implicit inclusion of mach/gpio.h, add explict
> > include of mach/gpio.h.
> I'm going to drop it for 3.7 too
> 
> the attached patch will do the same but in a more simpler way

I wonder whether you read your patches before you send them... it's
sometimes quite a good idea to review your own patches. :)

> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> index c5d7e1e..6803baa 100644
> --- a/arch/arm/mach-at91/gpio.c
> +++ b/arch/arm/mach-at91/gpio.c
> @@ -30,6 +30,7 @@
>  #include <mach/at91_pio.h>
>  
>  #include "generic.h"
> +#include "generic.h"

That's fairly obviously wrong.


From linus.walleij at linaro.org  Thu Aug 30 13:22:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 19:22:36 +0200
Subject: [PATCH] ARM: gemini: fix the gemini build
Message-ID: <1346347356-18786-1-git-send-email-linus.walleij@linaro.org>

Test-compiling obscure machines I notice that the gemini (which
by the way lacks a defconfig) is broken since some time back.
Adding a simple missing include makes it build again.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ARM SoC guys: please apply this patch directly to the -rc:s
unless there is some obvious problem with it.
---
 arch/arm/mach-gemini/irq.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index ca70e5f..020852d 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -17,6 +17,7 @@
 #include <linux/sched.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 #include <mach/hardware.h>
 
 #define IRQ_SOURCE(base_addr)	(base_addr + 0x00)
-- 
1.7.7.6



From linus.walleij at linaro.org  Thu Aug 30 13:39:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 19:39:00 +0200
Subject: [PATCH] clk: versatile: make config option boolean
Message-ID: <1346348340-19020-1-git-send-email-linus.walleij@linaro.org>

There is no choice to have the RealView clocks as module for sure,
so turn this config option into a boolean.

Reported-by: Pawel Moll <pawel.moll at arm.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/clk/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 89b726d..df33b8e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -41,7 +41,7 @@ config COMMON_CLK_WM831X
 	  PMICs from Wolfson Microlectronics.
 
 config COMMON_CLK_VERSATILE
-	tristate "Clock driver for ARM Reference designs"
+	bool "Clock driver for ARM Reference designs"
 	depends on ARCH_INTEGRATOR || ARCH_REALVIEW
 	---help---
           Supports clocking on ARM Reference designs Integrator/AP,
-- 
1.7.7.6



From broonie at opensource.wolfsonmicro.com  Thu Aug 30 13:43:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 30 Aug 2012 10:43:18 -0700
Subject: [PATCH] ASoC: SAMSUNG: Add SND_SOC_DAIFMT_CONT option for
 snd_soc_set_fmt()
In-Reply-To: <001d01cd85d6$59298040$0b7c80c0$@samsung.com>
References: <003101cd8367$3476e650$9d64b2f0$@samsung.com>
 <20120827204550.GA4400@opensource.wolfsonmicro.com>
 <001d01cd85d6$59298040$0b7c80c0$@samsung.com>
Message-ID: <20120830174317.GG4356@opensource.wolfsonmicro.com>

On Wed, Aug 29, 2012 at 08:06:32PM +0900, Sangsu Park wrote:

Please check your mailer configuration, it looks like it's reformatting
all the text with much longer line widths.

> On Sun, Aug 26, 2012 at 05:45:54PM +0900, Mark Brown wrote:

> > a whole lot of sense on the slave side, it's related to the clock generation so should have no
> > effect at all on the slave side.  The driver code looks reasonably sensible though.

> You mean cpu side is slave? 

Yes.


> > What specifically is going wrong here?

> SND_SOC_DAIFMT_CONT is used sound/soc/Samsung/pcm.c (s3c_pcm_set_fmt()) like below.

> switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
>         case SND_SOC_DAIFMT_CONT:
>                 pcm->idleclk = 1;
>                 break;
>         case SND_SOC_DAIFMT_GATED:
>                 pcm->idleclk = 0;
>                 break;
>         default:
>                 dev_err(pcm->dev, "Invalid Clock gating request!\n");
>                 ret = -EINVAL;
>                 goto exit;
>         }

> If fmt argument has no SND_SOC_DAIFMT_ option, s3c_pcm_set_fmt() return -EINVAL.

So, clearly this is unrelated to the change you mentioned in your commit
message - it looks like this is just a plain issue in the machine
driver.  That said the above code should be changed to at least ignore
the setting in slave mode (since the clock shouldn't be being driven and
it doesn't matter).


From hein_tibosch at yahoo.es  Thu Aug 30 12:34:27 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Fri, 31 Aug 2012 00:34:27 +0800
Subject: [PATCH v2 2/2] mmc: atmel-mci: AP700x PDC is not connected to MCI
Message-ID: <503F9613.5060007@yahoo.es>

Earlier, atmel-mci was adapted to make use of the peripheral DMA
controller (PDC), in case normal DMA wouldn't work.
( http://comments.gmane.org/gmane.linux.kernel.mmc/9403 )
This works OK on ARM platforms (AT91), but it broke the driver
for AVR32, the AP700x.
Although the MCI has PDC support, the connection is not done for
AVR chips

This patch makes the use of PDC depend on CONFIG_AVR32

Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>

---
 drivers/mmc/host/atmel-mci-regs.h |    7 +++++++
 drivers/mmc/host/atmel-mci.c      |    2 +-
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index ab56f7d..c97001e 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -140,6 +140,13 @@
 #define atmci_writel(port,reg,value)			\
 	__raw_writel((value), (port)->regs + reg)
 
+/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
+#ifdef CONFIG_AVR32
+#	define ATMCI_PDC_CONNECTED	0
+#else
+#	define ATMCI_PDC_CONNECTED	1
+#endif
+
 /*
  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index a6a5593..b8de891 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2208,7 +2208,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 			"version: 0x%x\n", version);
 
 	host->caps.has_dma_conf_reg = 0;
-	host->caps.has_pdc = 1;
+	host->caps.has_pdc = ATMCI_PDC_CONNECTED;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
 	host->caps.has_highspeed = 0;
-- 
1.7.8.0



From hein_tibosch at yahoo.es  Thu Aug 30 12:34:38 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Fri, 31 Aug 2012 00:34:38 +0800
Subject: [PATCH v2 1/2] mmc: atmel-mci: DMA can be used with other controller
Message-ID: <503F961E.5010905@yahoo.es>

After the latest changes to atmel-mci, it could not be used with
DMA on the AVR32 platform. This patch will allow to use DMA again
and it will avoid access to MCI register ATMCI_DMA.

v2:
Even if the IP version is lower than v3xx and doesn't have the DMA
configuration register, DMA transfers can be used with a different
controller than the Atmel AHB DMA one. For instance, some AVR chips use 
the Synopsys DesignWare AHB DMA controller.

v2: in atmci_configure_dma: check both pdata and pdata->dma_slave


Signed-off-by: Hein Tibosch <hein_tibosch at yahoo.es>
Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/mmc/host/atmel-mci.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index f2c115e..a6a5593 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -71,7 +71,7 @@ enum atmci_pdc_buf {
 };
 
 struct atmel_mci_caps {
-	bool    has_dma;
+	bool    has_dma_conf_reg;
 	bool    has_pdc;
 	bool    has_cfg_reg;
 	bool    has_cstor_reg;
@@ -411,7 +411,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
 	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 
-	if (host->caps.has_dma) {
+	if (host->caps.has_dma_conf_reg) {
 		u32 val;
 
 		val = buf[ATMCI_DMA / 4];
@@ -767,7 +767,7 @@ static void atmci_dma_complete(void *arg)
 
 	dev_vdbg(&host->pdev->dev, "DMA complete\n");
 
-	if (host->caps.has_dma)
+	if (host->caps.has_dma_conf_reg)
 		/* Disable DMA hardware handshaking on MCI */
 		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 
@@ -954,7 +954,9 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 		maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
 	}
 
-	atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | ATMCI_DMAEN);
+	if (host->caps.has_dma_conf_reg)
+		atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
+			ATMCI_DMAEN);
 
 	sglen = dma_map_sg(chan->device->dev, data->sg,
 			data->sg_len, direction);
@@ -2161,7 +2163,10 @@ static bool atmci_configure_dma(struct atmel_mci *host)
 
 	pdata = host->pdev->dev.platform_data;
 
-	if (pdata && find_slave_dev(pdata->dma_slave)) {
+	if (!pdata)
+		return false;
+
+	if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
 		dma_cap_mask_t mask;
 
 		/* Try to grab a DMA channel */
@@ -2202,7 +2207,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 	dev_info(&host->pdev->dev,
 			"version: 0x%x\n", version);
 
-	host->caps.has_dma = 0;
+	host->caps.has_dma_conf_reg = 0;
 	host->caps.has_pdc = 1;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
@@ -2219,12 +2224,7 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 		host->caps.has_odd_clk_div = 1;
 	case 0x400:
 	case 0x300:
-#ifdef CONFIG_AT_HDMAC
-		host->caps.has_dma = 1;
-#else
-		dev_info(&host->pdev->dev,
-			"has dma capability but dma engine is not selected, then use pio\n");
-#endif
+		host->caps.has_dma_conf_reg = 1;
 		host->caps.has_pdc = 0;
 		host->caps.has_cfg_reg = 1;
 		host->caps.has_cstor_reg = 1;
@@ -2298,7 +2298,7 @@ static int __init atmci_probe(struct platform_device *pdev)
 
 	/* Get MCI capabilities and set operations according to it */
 	atmci_get_cap(host);
-	if (host->caps.has_dma && atmci_configure_dma(host)) {
+	if (atmci_configure_dma(host)) {
 		host->prepare_data = &atmci_prepare_data_dma;
 		host->submit_data = &atmci_submit_data_dma;
 		host->stop_transfer = &atmci_stop_transfer_dma;
-- 
1.7.8.0



From hein_tibosch at yahoo.es  Thu Aug 30 12:48:53 2012
From: hein_tibosch at yahoo.es (Hein Tibosch)
Date: Fri, 31 Aug 2012 00:48:53 +0800
Subject: [PATCH v2 0/2] mmc: atmel-mci: repair driver for use with AVR32
 (AP7000)
Message-ID: <503F9975.4060001@yahoo.es>

Due to changes after 2.6.38, the drivers atmel-mci and dw_dmac got broken
for the AVR32 platform: the AP7000.

These two patches repair the atmel-mci driver

Thanks to Ludovic and Hans-Christian for their comments

Hein Tibosch (2):

  mmc: atmel-mci: DMA can be used with other controller
  mmc: atmel-mci: AP700x PDC is not connected to MCI

 drivers/mmc/host/atmel-mci-regs.h |    7 +++++++
 drivers/mmc/host/atmel-mci.c      |   28 ++++++++++++++--------------
 2 files changed, 21 insertions(+), 14 deletions(-)

-- 



From shc_work at mail.ru  Thu Aug 30 13:57:48 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Thu, 30 Aug 2012 21:57:48 +0400
Subject: [PATCH] ARM: clps711x: convert to clocksource/clockevents
In-Reply-To: <CACRpkdYHenkDYnZ5W8xzR58ioK8=8-rfSQFrtpTqfGYy28-cSA@mail.gmail.com>
References: <1346344678-18248-1-git-send-email-linus.walleij@linaro.org>
 <20120830210210.55e0899d.shc_work@mail.ru>
 <CACRpkdYHenkDYnZ5W8xzR58ioK8=8-rfSQFrtpTqfGYy28-cSA@mail.gmail.com>
Message-ID: <20120830215748.492ce5e3.shc_work@mail.ru>

On Thu, 30 Aug 2012 10:21:44 -0700
Linus Walleij <linus.walleij at linaro.org> wrote:

> >> This converts the ageing clps711x timer driver to the modern
> >> clocksource/clockevent API.
> > The patch does not account for the changes that I sent to the mailing list
> > recently, where I did support different clock frequencies for the processor.
> No problem, I can rebase on top of your patches as soon as you
> submit them to ARM SoC so I can see them in linux-next.
Patches have already been sent to the mailing list, and as far I understand,
these patches are awaiting approval from Arnd.

...
> > The patch uses a second timer, which does not allow its use for other purposes, 
> What does this mean? Reading the datasheet it didn't say anything about
> this timer being dedicated to something else.
> I am using TC1D as clocksource and TC2D as clockevent, repurposing
> it from the previous use as singe time source.
> Doing "git grep TC1D" I cannot see any code in the kernel making use
> of this timer?
These timers are only two in the processor and I just want to say that the second
timer CAN be used for other purposes, such as I use. In the kernel of the second
timer is really not used.

> I could think of things like the boot loader or firmware setting it up
> to run in free-running mode ... in that case we use
> it as clocksource without initialization as long as we know what
> frequency it's running on.
Not understand this...

> As far as I could understand from the datasheet there is really
> no way to actually disable these timers, so they always run
> anyway?
Yes. We can only enable/disable IRQ for the timers, switch clock source and mode.

> > I have also tried to do something like this without using additional processor
> > resources, but not yet brought to the finish line yet.
> OK do you think you can switch the clps71x over to generic time and
> clockevents inspired by this patch or so?
Unfortunately, I'm leaving tomorrow for a little while so I can not check anything
or try to do better, but the idea of ??switching to a new API I like. Upon arrival back,
I'll try to make a similar using only one timer or use the CLOCKSOURCE/CLOCKEVENTS
resources to generate intervals necessary for me.

-- 
Alexander Shiyan <shc_work at mail.ru>


From gregkh at linuxfoundation.org  Thu Aug 30 14:03:57 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 30 Aug 2012 11:03:57 -0700
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830165224.GR19437@titan.lakedaemon.net>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
Message-ID: <20120830180357.GA2459@kroah.com>

On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> On Thu, Aug 30, 2012 at 07:14:47AM +0200, Andrew Lunn wrote:
> > Tools like kisskb are good at finding build regressions in the kernel
> > sources. However, regressions in the DT desscriptions are not found,
> > because generally these build systems don't build the DT binary blobs.
> > 
> > Extend the ARM all target to build all enabled DTB files.
> > 
> > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> 
> Acked-by: Jason Cooper <jason at lakedaemon.net>
> 
> I've CC'd stable to see if they want to pick this up.  It does depend on
> having dtc built.  A patch already exists to build dtc on demand, but
> I'm not sure if it has made it into mainline yet.  It may be in
> Russell's queue.

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read Documentation/stable_kernel_rules.txt
for how to do this properly.

</formletter>


From andrew at lunn.ch  Thu Aug 30 14:08:53 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 30 Aug 2012 20:08:53 +0200
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <20120830171236.GS19437@titan.lakedaemon.net>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
 <20120830171236.GS19437@titan.lakedaemon.net>
Message-ID: <20120830180853.GP9886@lunn.ch>

On Thu, Aug 30, 2012 at 01:12:36PM -0400, Jason Cooper wrote:
> On Thu, Aug 30, 2012 at 07:39:12AM +0200, Andrew Lunn wrote:
> > Linux-next has failed to compile for kirkwood since 23 August with:
> > 
> > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
> > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)
> > 
> > Add missing <linux/sizes.h>
> > 
> > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> 
> Applied to: fixes-for-v3.6
> 
> Also, I added a CC for stable so greg can pick it up.

Hi Jason

Stable does not need it. As i said, it only broke 23 August with
linux-next. So this is needed for only 3.7.

	    Andrew


From fernando.lugo at ti.com  Thu Aug 30 14:26:11 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Thu, 30 Aug 2012 13:26:11 -0500
Subject: [PATCHv2 0/3] remoteproc: introduce rproc recovery
Message-ID: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>

These set of patches make possible the remoteproc recover after a crash.
This is a hard recovery, that means the remoteproc is reset and it will
start from the beginning. When a crash happen all the virtio devices are
destroyed. Therefore, both rpmsg drivers and devices are gracefully
removed which also cause rproc users become 0 and the remoteproc is turned
off. After the virtio devices are destroyed the crash handler function
will read the virtio information from the firmware in order to recreate
the virtio devices that will boot the remoteproc and everything will be
functional again.

-Version 2
* Wait untill there is no more rproc users before realoding the FW again
  in order to make sure the recovery will work fine. As suggested by
  Sjur BRENDELAND

Fernando Guzman Lugo (3):
  remoteproc: add rproc_report_crash function to notify rproc crashes
  remoteproc: recover a remoteproc when it has crashed
  remoteproc: create debugfs entry to disable/enable recovery
    dynamically

 Documentation/remoteproc.txt             |    7 ++
 drivers/remoteproc/remoteproc_core.c     |  116 ++++++++++++++++++++++++++++--
 drivers/remoteproc/remoteproc_debugfs.c  |   83 +++++++++++++++++++++
 drivers/remoteproc/remoteproc_internal.h |    1 +
 include/linux/remoteproc.h               |   22 ++++++
 5 files changed, 222 insertions(+), 7 deletions(-)



From fernando.lugo at ti.com  Thu Aug 30 14:26:12 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Thu, 30 Aug 2012 13:26:12 -0500
Subject: [PATCHv2 1/3] remoteproc: add rproc_report_crash function to notify
 rproc crashes
In-Reply-To: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
References: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1346351174-28441-2-git-send-email-fernando.lugo@ti.com>

This patch is exporting the rproc_report_crash function which can be used
to report a rproc crash to the remoteproc core. This function is specially
thought to be called by low-level remoteproc driver code in case of
detecting a crash (remoteproc is not functional anymore). Using this
function from another driver (non rproc driver) should be analyzed very
carefully most of the time that will be considered wrong.

rproc_report_crash function can be called from any context, that means,
it can be called from atomic context without any problem. The reporter
function is creating a new thread (workqueue work) in charge of handling
the crash (if possible).

Creating this new thread is done for two main reasons. First reason is
to be able to call it from atomic context, due to the fact that many
crashes trigger an interrupt, so this function can be called directly
from ISR context. Second reason is avoid any deadlock condition which
could happen if the rproc_report_crash function is called from a
function which is indirectly holding a rproc lock.

The reporter function is scheduling the crash handler task. This task
is thought to have some features like:

-remoteproc register dump
-remoteproc stack dump
-remoteproc core dump
-Saving of the remoteproc traces in order to be visible after the crash
-Reseting the remoteproc in order to make it functional again (hard recovery)

Right now, it is only printing the crash type which was detected. The
types of crashes are represented by an enum. I have only added mmufault
crash type. Remoteproc low-level drivers can add more types when needed.

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 Documentation/remoteproc.txt         |    7 +++
 drivers/remoteproc/remoteproc_core.c |   80 +++++++++++++++++++++++++++++++---
 include/linux/remoteproc.h           |   18 ++++++++
 3 files changed, 98 insertions(+), 7 deletions(-)

diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt
index 23a09b8..e6469fd 100644
--- a/Documentation/remoteproc.txt
+++ b/Documentation/remoteproc.txt
@@ -129,6 +129,13 @@ int dummy_rproc_example(struct rproc *my_rproc)
 
       Returns 0 on success and -EINVAL if @rproc isn't valid.
 
+  void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type)
+    - Report a crash in a remoteproc
+      This function must be called every time a crash is detected by the
+      platform specific rproc implementation. This should not be called from a
+      non-remoteproc driver. This function can be called from atomic/interrupt
+      context.
+
 5. Implementation callbacks
 
 These callbacks should be provided by platform-specific remoteproc
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index d5c2dbf..3a6f1a1 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -50,6 +50,18 @@ typedef int (*rproc_handle_resource_t)(struct rproc *rproc, void *, int avail);
 /* Unique indices for remoteproc devices */
 static DEFINE_IDA(rproc_dev_index);
 
+static const char * const rproc_crash_names[] = {
+	[RPROC_MMUFAULT]	= "mmufault",
+};
+
+/* translate rproc_crash_type to string */
+static const char *rproc_crash_to_string(enum rproc_crash_type type)
+{
+	if (type < ARRAY_SIZE(rproc_crash_names))
+		return rproc_crash_names[type];
+	return "unkown";
+}
+
 /*
  * This is the IOMMU fault handler we register with the IOMMU API
  * (when relevant; not all remote processors access memory through
@@ -57,19 +69,17 @@ static DEFINE_IDA(rproc_dev_index);
  *
  * IOMMU core will invoke this handler whenever the remote processor
  * will try to access an unmapped device address.
- *
- * Currently this is mostly a stub, but it will be later used to trigger
- * the recovery of the remote processor.
  */
 static int rproc_iommu_fault(struct iommu_domain *domain, struct device *dev,
 		unsigned long iova, int flags, void *token)
 {
+	struct rproc *rproc = token;
+
 	dev_err(dev, "iommu fault: da 0x%lx flags 0x%x\n", iova, flags);
 
-	/*
-	 * Let the iommu core know we're not really handling this fault;
-	 * we just plan to use this as a recovery trigger.
-	 */
+	rproc_report_crash(rproc, RPROC_MMUFAULT);
+
+	/* Let the iommu core know we're not really handling this fault; */
 	return -ENOSYS;
 }
 
@@ -872,6 +882,34 @@ out:
 }
 
 /**
+ * rproc_crash_handler_work() - handle a crash
+ *
+ * This function needs to handle everything related to a crash, like cpu
+ * registers and stack dump, information to help to debug the fatal error, etc.
+ */
+static void rproc_crash_handler_work(struct work_struct *work)
+{
+	struct rproc *rproc = container_of(work, struct rproc, crash_handler);
+	struct device *dev = &rproc->dev;
+
+	dev_dbg(dev, "enter %s\n", __func__);
+
+	mutex_lock(&rproc->lock);
+	if (rproc->state == RPROC_CRASHED || rproc->state == RPROC_OFFLINE) {
+		/* handle only the first crash detected */
+		mutex_unlock(&rproc->lock);
+		return;
+	}
+
+	rproc->state = RPROC_CRASHED;
+	dev_err(&rproc->dev, "handling crash #%u in %s\n",
+		++rproc->crash_cnt, rproc->name);
+	mutex_unlock(&rproc->lock);
+
+	/* TODO: handle crash */
+}
+
+/**
  * rproc_boot() - boot a remote processor
  * @rproc: handle of a remote processor
  *
@@ -1165,6 +1203,8 @@ struct rproc *rproc_alloc(struct device *dev, const char *name,
 	INIT_LIST_HEAD(&rproc->traces);
 	INIT_LIST_HEAD(&rproc->rvdevs);
 
+	INIT_WORK(&rproc->crash_handler, rproc_crash_handler_work);
+
 	rproc->state = RPROC_OFFLINE;
 
 	return rproc;
@@ -1221,6 +1261,32 @@ int rproc_del(struct rproc *rproc)
 }
 EXPORT_SYMBOL(rproc_del);
 
+/**
+ * rproc_report_crash() - rproc crash reporter function
+ * @rproc: remote processor
+ * @type: crash type
+ *
+ * This function must be called every time a crash is detected by the low-level
+ * drivers implementing a specific remoteproc. This should not be called from a
+ * non-remoteproc driver.
+ *
+ * This function can be called from atomic/interrupt context.
+ */
+void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type)
+{
+	if (!rproc) {
+		pr_err("NULL rproc pointer\n");
+		return;
+	}
+
+	dev_err(&rproc->dev, "crash detected in %s: type %s\n",
+		rproc->name, rproc_crash_to_string(type));
+
+	/* create a new task to handle the error */
+	schedule_work(&rproc->crash_handler);
+}
+EXPORT_SYMBOL(rproc_report_crash);
+
 static int __init remoteproc_init(void)
 {
 	rproc_init_debugfs();
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 131b539..a46ed27 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -361,6 +361,19 @@ enum rproc_state {
 };
 
 /**
+ * enum rproc_crash_type - remote processor crash types
+ * @RPROC_MMUFAULT:	iommu fault
+ *
+ * Each element of the enum is used as an array index. So that, the value of
+ * the elements should be always something sane.
+ *
+ * Feel free to add more types when needed.
+ */
+enum rproc_crash_type {
+	RPROC_MMUFAULT,
+};
+
+/**
  * struct rproc - represents a physical remote processor device
  * @node: klist node of this rproc object
  * @domain: iommu domain
@@ -383,6 +396,8 @@ enum rproc_state {
  * @rvdevs: list of remote virtio devices
  * @notifyids: idr for dynamically assigning rproc-wide unique notify ids
  * @index: index of this rproc device
+ * @crash_handler: workqueue for handling a crash
+ * @crash_cnt: crash counter
  */
 struct rproc {
 	struct klist_node node;
@@ -406,6 +421,8 @@ struct rproc {
 	struct list_head rvdevs;
 	struct idr notifyids;
 	int index;
+	struct work_struct crash_handler;
+	unsigned crash_cnt;
 };
 
 /* we currently support only two vrings per rvdev */
@@ -460,6 +477,7 @@ int rproc_del(struct rproc *rproc);
 
 int rproc_boot(struct rproc *rproc);
 void rproc_shutdown(struct rproc *rproc);
+void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type);
 
 static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
 {
-- 
1.7.1



From fernando.lugo at ti.com  Thu Aug 30 14:26:13 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Thu, 30 Aug 2012 13:26:13 -0500
Subject: [PATCHv2 2/3] remoteproc: recover a remoteproc when it has crashed
In-Reply-To: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
References: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1346351174-28441-3-git-send-email-fernando.lugo@ti.com>

This patch is introducing rproc_trigger_recover function which is in
charge of recovering the rproc. One way to recover the rproc after a crash
is resetting all its virtio devices. Doing that, all rpmsg drivers are
restored along with the rpmsg devices and that also causes the reset of
the remoteproc making the rpmsg communication with the remoteproc
functional again. So far, rproc_trigger_recover function is only resetting
all virtio devices, if in the future other rproc features are introduced
and need to be reset too, rproc_trigger_recover function should take care
of that.

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 drivers/remoteproc/remoteproc_core.c     |   37 +++++++++++++++++++++++++++++-
 drivers/remoteproc/remoteproc_internal.h |    1 +
 include/linux/remoteproc.h               |    2 +
 3 files changed, 39 insertions(+), 1 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 3a6f1a1..9fbd364 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -882,6 +882,36 @@ out:
 }
 
 /**
+ * rproc_trigger_recover() - recover a remoteproc
+ * @rproc: the remote processor
+ *
+ * The recovery is done by reseting all the virtio devices, that way all the
+ * rpmsg drivers will be reseted along with the remote processor making the
+ * remoteproc functional again.
+ *
+ * This function can sleep, so that it cannot be called from atomic context.
+ */
+int rproc_trigger_recover(struct rproc *rproc)
+{
+	struct rproc_vdev *rvdev, *rvtmp;
+
+	dev_err(&rproc->dev, "recovering %s\n", rproc->name);
+
+	init_completion(&rproc->crash_comp);
+	/* clean up remote vdev entries */
+	list_for_each_entry_safe(rvdev, rvtmp, &rproc->rvdevs, node)
+		rproc_remove_virtio_dev(rvdev);
+
+	/* wait until there is no more rproc users */
+	wait_for_completion(&rproc->crash_comp);
+
+	/* run rproc_fw_config_virtio to create vdevs again */
+	return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
+			rproc->firmware, &rproc->dev, GFP_KERNEL,
+			rproc, rproc_fw_config_virtio);
+}
+
+/**
  * rproc_crash_handler_work() - handle a crash
  *
  * This function needs to handle everything related to a crash, like cpu
@@ -906,7 +936,7 @@ static void rproc_crash_handler_work(struct work_struct *work)
 		++rproc->crash_cnt, rproc->name);
 	mutex_unlock(&rproc->lock);
 
-	/* TODO: handle crash */
+	rproc_trigger_recover(rproc);
 }
 
 /**
@@ -1030,6 +1060,10 @@ void rproc_shutdown(struct rproc *rproc)
 
 	rproc_disable_iommu(rproc);
 
+	/* if in crash state, unlock crash handler */
+	if (rproc->state == RPROC_CRASHED)
+		complete_all(&rproc->crash_comp);
+
 	rproc->state = RPROC_OFFLINE;
 
 	dev_info(dev, "stopped remote processor %s\n", rproc->name);
@@ -1204,6 +1238,7 @@ struct rproc *rproc_alloc(struct device *dev, const char *name,
 	INIT_LIST_HEAD(&rproc->rvdevs);
 
 	INIT_WORK(&rproc->crash_handler, rproc_crash_handler_work);
+	init_completion(&rproc->crash_comp);
 
 	rproc->state = RPROC_OFFLINE;
 
diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h
index a690ebe..d9c0730 100644
--- a/drivers/remoteproc/remoteproc_internal.h
+++ b/drivers/remoteproc/remoteproc_internal.h
@@ -63,6 +63,7 @@ void rproc_free_vring(struct rproc_vring *rvring);
 int rproc_alloc_vring(struct rproc_vdev *rvdev, int i);
 
 void *rproc_da_to_va(struct rproc *rproc, u64 da, int len);
+int rproc_trigger_recover(struct rproc *rproc);
 
 static inline
 int rproc_fw_sanity_check(struct rproc *rproc, const struct firmware *fw)
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index a46ed27..0c1a2f9 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -398,6 +398,7 @@ enum rproc_crash_type {
  * @index: index of this rproc device
  * @crash_handler: workqueue for handling a crash
  * @crash_cnt: crash counter
+ * @crash_comp: completion used to sync crash handler and the rproc reload
  */
 struct rproc {
 	struct klist_node node;
@@ -423,6 +424,7 @@ struct rproc {
 	int index;
 	struct work_struct crash_handler;
 	unsigned crash_cnt;
+	struct completion crash_comp;
 };
 
 /* we currently support only two vrings per rvdev */
-- 
1.7.1



From fernando.lugo at ti.com  Thu Aug 30 14:26:14 2012
From: fernando.lugo at ti.com (Fernando Guzman Lugo)
Date: Thu, 30 Aug 2012 13:26:14 -0500
Subject: [PATCHv2 3/3] remoteproc: create debugfs entry to disable/enable
 recovery dynamically
In-Reply-To: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
References: <1346351174-28441-1-git-send-email-fernando.lugo@ti.com>
Message-ID: <1346351174-28441-4-git-send-email-fernando.lugo@ti.com>

Add a debugfs entry (named recovery) so that recovery can be disabled
dynamically at runtime. This entry is very useful when you are trying to
debug a rproc crash. Without this a recovery will take place making
impossible to debug the issue.

Original idea from Ohad Ben-Cohen and contributions from
Subramaniam Chanderashekarapuram

Example:
-disabling recovery:
$ echo disabled > <debugfs>/remoteproc/remoteproc0/recovery

-enabling recovery:
$ echo enabled > <debugfs>/remoteproc/remoteproc0/recovery

-in case you have disabled recovery and you want to continue
 debugging you can recover the remoteproc once using recover.
 This will not change the state of the recovery entry, it will
 only recovery the rproc if its state is RPROC_CRASHED
$ echo recover > <debugfs>/remoteproc/remoteproc0/recovery

Signed-off-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
---
 drivers/remoteproc/remoteproc_core.c    |    3 +-
 drivers/remoteproc/remoteproc_debugfs.c |   83 +++++++++++++++++++++++++++++++
 include/linux/remoteproc.h              |    2 +
 3 files changed, 87 insertions(+), 1 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 9fbd364..16e20f7 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -936,7 +936,8 @@ static void rproc_crash_handler_work(struct work_struct *work)
 		++rproc->crash_cnt, rproc->name);
 	mutex_unlock(&rproc->lock);
 
-	rproc_trigger_recover(rproc);
+	if (!rproc->recovery_disabled)
+		rproc_trigger_recover(rproc);
 }
 
 /**
diff --git a/drivers/remoteproc/remoteproc_debugfs.c b/drivers/remoteproc/remoteproc_debugfs.c
index 0383385..aa95cde 100644
--- a/drivers/remoteproc/remoteproc_debugfs.c
+++ b/drivers/remoteproc/remoteproc_debugfs.c
@@ -28,6 +28,9 @@
 #include <linux/debugfs.h>
 #include <linux/remoteproc.h>
 #include <linux/device.h>
+#include <linux/uaccess.h>
+
+#include "remoteproc_internal.h"
 
 /* remoteproc debugfs parent dir */
 static struct dentry *rproc_dbg;
@@ -111,6 +114,84 @@ static const struct file_operations rproc_name_ops = {
 	.llseek	= generic_file_llseek,
 };
 
+/* expose recovery flag via debugfs */
+static ssize_t rproc_recovery_read(struct file *filp, char __user *userbuf,
+		size_t count, loff_t *ppos)
+{
+	struct rproc *rproc = filp->private_data;
+	char *buf = rproc->recovery_disabled ? "disabled\n" : "enabled\n";
+
+	return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
+}
+
+
+/*
+ * Writing to the recovey debugfs entry we can change the behavior of the
+ * recovery dynamically. The default value of this entry is "enabled".
+ *
+ * There are 3 possible options you can write to the recovery debug entry:
+ * "enabled", "disabled" and "recover"
+ *
+ * enabled:	In this case recovery will be enabled, every time there is a
+ *		rproc crashed the rproc will be recovered. If recovery has been
+ *		disabled and it crashed and you enable recovery it will be
+ *		recover as soon as you enable recovery.
+ * disabled:	In this case recovery will be disabled, that means if a rproc
+ *		crashes it will remain in crashed state. Therefore the rproc
+ *		won't be functional any more. But this option is used for
+ *		debugging purposes. Otherwise, debugging a crash would not be
+ *		possible.
+ * recover:	This function will trigger a recovery without taking care of
+ *		the recovery state (enabled/disabled) and without changing it.
+ *		This useful for the cases when you are debugging a crash and
+ *		after enabling recovery you get another crash immediately. As
+ *		the recovery state will be enabled it will recover the rproc
+ *		without let you debug the new crash. So, it is recommended to
+ *		disabled recovery, then starting debugging and use "recovery"
+ *		command while still debugging and when you are done then you
+ *		case use enabled command.
+ */
+static ssize_t rproc_recovery_write(struct file *filp,
+		const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	struct rproc *rproc = filp->private_data;
+	char buf[10];
+	int ret;
+
+	if (count > sizeof(buf))
+		return count;
+
+	ret = copy_from_user(buf, user_buf, count);
+	if (ret)
+		return ret;
+
+	/* remove end of line */
+	if (buf[count - 1] == '\n')
+		buf[count - 1] = '\0';
+
+	if (!strncmp(buf, "enabled", count)) {
+		rproc->recovery_disabled = false;
+		/* if rproc has crashed trigger recovery */
+		if (rproc->state == RPROC_CRASHED)
+			rproc_trigger_recover(rproc);
+	} else if (!strncmp(buf, "disabled", count)) {
+		rproc->recovery_disabled = true;
+	} else if (!strncmp(buf, "recover", count)) {
+		/* if rproc has crashed trigger recovery */
+		if (rproc->state == RPROC_CRASHED)
+			rproc_trigger_recover(rproc);
+	}
+
+	return count;
+}
+
+static const struct file_operations rproc_recovery_ops = {
+	.read = rproc_recovery_read,
+	.write = rproc_recovery_write,
+	.open = simple_open,
+	.llseek = generic_file_llseek,
+};
+
 void rproc_remove_trace_file(struct dentry *tfile)
 {
 	debugfs_remove(tfile);
@@ -154,6 +235,8 @@ void rproc_create_debug_dir(struct rproc *rproc)
 					rproc, &rproc_name_ops);
 	debugfs_create_file("state", 0400, rproc->dbg_dir,
 					rproc, &rproc_state_ops);
+	debugfs_create_file("recovery", 0400, rproc->dbg_dir,
+					rproc, &rproc_recovery_ops);
 }
 
 void __init rproc_init_debugfs(void)
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 0c1a2f9..2ccc3fe 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -399,6 +399,7 @@ enum rproc_crash_type {
  * @crash_handler: workqueue for handling a crash
  * @crash_cnt: crash counter
  * @crash_comp: completion used to sync crash handler and the rproc reload
+ * @recovery_disabled: flag that state if recovery was disabled
  */
 struct rproc {
 	struct klist_node node;
@@ -425,6 +426,7 @@ struct rproc {
 	struct work_struct crash_handler;
 	unsigned crash_cnt;
 	struct completion crash_comp;
+	bool recovery_disabled;
 };
 
 /* we currently support only two vrings per rvdev */
-- 
1.7.1



From cyril at ti.com  Thu Aug 30 14:28:17 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Thu, 30 Aug 2012 14:28:17 -0400
Subject: [PATCH v3 1/2] ARM: arch_timers: enable the use of the virtual
 timer
In-Reply-To: <1345819976-6339-2-git-send-email-marc.zyngier@arm.com>
References: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
 <1345819976-6339-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <503FB0C1.5040309@ti.com>

Hi Marc,

On 8/24/2012 10:52 AM, Marc Zyngier wrote:
> At the moment, the arch_timer driver only uses the physical timer,
> which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
> which is likely in a virtualized environment. Instead, the virtual
> timer is always available.
>
> This patch enables the use of the virtual timer, unless no
> interrupt is provided in the DT for it, in which case it falls
> back to the physical timer.
>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>

Looks very nice...  Minor comments below.

> ---
>   arch/arm/kernel/arch_timer.c | 337 ++++++++++++++++++++++++++++++-------------
>   1 file changed, 233 insertions(+), 104 deletions(-)
>
> diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> index cf25880..3f63b90 100644
> --- a/arch/arm/kernel/arch_timer.c
> +++ b/arch/arm/kernel/arch_timer.c
> @@ -27,13 +27,23 @@
>   #include <asm/sched_clock.h>
>
>   static unsigned long arch_timer_rate;
> -static int arch_timer_ppi;
> -static int arch_timer_ppi2;
> +
> +enum ppi_nr {
> +	PHYS_SECURE_PPI,
> +	PHYS_NONSECURE_PPI,
> +	VIRT_PPI,
> +	HYP_PPI,
> +	MAX_TIMER_PPI
> +};
> +
> +static int arch_timer_ppi[MAX_TIMER_PPI];
>
>   static struct clock_event_device __percpu **arch_timer_evt;
>
>   extern void init_current_timer_delay(unsigned long freq);
>
> +static bool arch_timer_use_virtual = true;
> +
>   /*
>    * Architected system timer support.
>    */
> @@ -43,53 +53,98 @@ extern void init_current_timer_delay(unsigned long freq);
>   #define ARCH_TIMER_CTRL_IT_STAT		(1 << 2)
>
>   #define ARCH_TIMER_REG_CTRL		0
> -#define ARCH_TIMER_REG_FREQ		1
> -#define ARCH_TIMER_REG_TVAL		2
> +#define ARCH_TIMER_REG_TVAL		1
>
> -static void arch_timer_reg_write(int reg, u32 val)
> +#define ARCH_TIMER_PHYS_ACCESS		0
> +#define ARCH_TIMER_VIRT_ACCESS		1
> +
> +/*
> + * These register accessors are marked inline so the compiler can
> + * nicely work out which register we want, and chuck away the rest of
> + * the code. At least it does so with a recent GCC (4.6.3).
> + */
> +static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
>   {
> -	switch (reg) {
> -	case ARCH_TIMER_REG_CTRL:
> -		asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> -		break;
> -	case ARCH_TIMER_REG_TVAL:
> -		asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
> -		break;
> +	if (access == ARCH_TIMER_PHYS_ACCESS) {
> +		switch (reg) {
> +		case ARCH_TIMER_REG_CTRL:
> +			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> +			break;
> +		case ARCH_TIMER_REG_TVAL:
> +			asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
> +			break;
> +		}
> +	}
> +
> +	if (access == ARCH_TIMER_VIRT_ACCESS) {
> +		switch (reg) {
> +		case ARCH_TIMER_REG_CTRL:
> +			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
> +			break;
> +		case ARCH_TIMER_REG_TVAL:
> +			asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
> +			break;
> +		}
>   	}
>
>   	isb();
>   }
>
> -static u32 arch_timer_reg_read(int reg)
> +static inline u32 arch_timer_reg_read(const int access, const int reg)
>   {
> -	u32 val;
> +	u32 val = 0;
> +
> +	if (access == ARCH_TIMER_PHYS_ACCESS) {
> +		switch (reg) {
> +		case ARCH_TIMER_REG_CTRL:
> +			asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
> +			break;
> +		case ARCH_TIMER_REG_TVAL:
> +			asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
> +			break;
> +		}
> +	}
>
> -	switch (reg) {
> -	case ARCH_TIMER_REG_CTRL:
> -		asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
> -		break;
> -	case ARCH_TIMER_REG_FREQ:
> -		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
> -		break;
> -	case ARCH_TIMER_REG_TVAL:
> -		asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
> -		break;
> -	default:
> -		BUG();
> +	if (access == ARCH_TIMER_VIRT_ACCESS) {
> +		switch (reg) {
> +		case ARCH_TIMER_REG_CTRL:
> +			asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
> +			break;
> +		case ARCH_TIMER_REG_TVAL:
> +			asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
> +			break;
> +		}
>   	}
>
>   	return val;
>   }
>
> -static irqreturn_t arch_timer_handler(int irq, void *dev_id)
> +static inline cycle_t arch_counter_get_cntpct(void)
>   {
> -	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> -	unsigned long ctrl;
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}
> +
> +static inline cycle_t arch_counter_get_cntvct(void)
> +{
> +	u32 cvall, cvalh;
> +
> +	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> +
> +	return ((cycle_t) cvalh << 32) | cvall;
> +}

We should use the Q and R qualifiers to avoid compiler misbehavior:
	u64 cval;
	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cvall));

The compiler generates sad looking code when constructing 64-bit 
quantities with shifts and ORs.  We found this while implementing the 
phys-virt patching for 64-bit phys_addr_t.

Is there value in unifying the physical and virtual counter read 
functions using the access specifier as you've done for the register 
read and write functions?

>
> -	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
> +static irqreturn_t inline timer_handler(const int access,
> +					struct clock_event_device *evt)
> +{
> +	unsigned long ctrl;
> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
>   	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
>   		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
> -		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
> +		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
>   		evt->event_handler(evt);
>   		return IRQ_HANDLED;
>   	}
> @@ -97,63 +152,100 @@ static irqreturn_t arch_timer_handler(int irq, void *dev_id)
>   	return IRQ_NONE;
>   }
>
> -static void arch_timer_disable(void)
> +static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
>   {
> -	unsigned long ctrl;
> +	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
>
> -	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
> -	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
> -	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
> +	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
>   }
>
> -static void arch_timer_set_mode(enum clock_event_mode mode,
> -				struct clock_event_device *clk)
> +static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
>   {
> +	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
> +
> +	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
> +}
> +
> +static inline void timer_set_mode(const int access, int mode)
> +{
> +	unsigned long ctrl;
>   	switch (mode) {
>   	case CLOCK_EVT_MODE_UNUSED:
>   	case CLOCK_EVT_MODE_SHUTDOWN:
> -		arch_timer_disable();
> +		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
> +		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
> +		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
>   		break;
>   	default:
>   		break;
>   	}
>   }
>
> -static int arch_timer_set_next_event(unsigned long evt,
> -				     struct clock_event_device *unused)
> +static void arch_timer_set_mode_virt(enum clock_event_mode mode,
> +				     struct clock_event_device *clk)
>   {
> -	unsigned long ctrl;
> +	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
> +}
> +
> +static void arch_timer_set_mode_phys(enum clock_event_mode mode,
> +				     struct clock_event_device *clk)
> +{
> +	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
> +}
>
> -	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
> +static inline void set_next_event(const int access, unsigned long evt)
> +{
> +	unsigned long ctrl;
> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
>   	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>   	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
> +	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
> +}
>
> -	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
> -	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
> +static int arch_timer_set_next_event_virt(unsigned long evt,
> +					  struct clock_event_device *unused)
> +{
> +	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
> +	return 0;
> +}
>
> +static int arch_timer_set_next_event_phys(unsigned long evt,
> +					  struct clock_event_device *unused)
> +{
> +	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
>   	return 0;
>   }
>
>   static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
>   {
> -	/* Be safe... */
> -	arch_timer_disable();
> -
>   	clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
>   	clk->name = "arch_sys_timer";
>   	clk->rating = 450;
> -	clk->set_mode = arch_timer_set_mode;
> -	clk->set_next_event = arch_timer_set_next_event;
> -	clk->irq = arch_timer_ppi;
> +	if (arch_timer_use_virtual) {
> +		arch_timer_set_mode_virt(CLOCK_EVT_MODE_SHUTDOWN, NULL);
> +		clk->set_mode = arch_timer_set_mode_virt;
> +		clk->set_next_event = arch_timer_set_next_event_virt;
> +	} else {
> +		arch_timer_set_mode_phys(CLOCK_EVT_MODE_SHUTDOWN, NULL);
> +		clk->set_mode = arch_timer_set_mode_phys;
> +		clk->set_next_event = arch_timer_set_next_event_phys;
> +	}
> +		
> +	clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
>
>   	clockevents_config_and_register(clk, arch_timer_rate,
>   					0xf, 0x7fffffff);
>
>   	*__this_cpu_ptr(arch_timer_evt) = clk;
>
> -	enable_percpu_irq(clk->irq, 0);
> -	if (arch_timer_ppi2)
> -		enable_percpu_irq(arch_timer_ppi2, 0);
> +	if (arch_timer_use_virtual)
> +		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
> +	else {
> +		enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
> +		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
> +			enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
> +	}
>
>   	return 0;
>   }
> @@ -173,8 +265,7 @@ static int arch_timer_available(void)
>   		return -ENXIO;
>
>   	if (arch_timer_rate == 0) {
> -		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
> -		freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
> +		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
>
>   		/* Check the timer frequency. */
>   		if (freq == 0) {
> @@ -185,43 +276,42 @@ static int arch_timer_available(void)
>   		arch_timer_rate = freq;
>   	}
>
> -	pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
> -		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
> +	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
> +		     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100,
> +		     arch_timer_use_virtual ? "virt" : "phys");
>   	return 0;
>   }
>
> -static inline cycle_t arch_counter_get_cntpct(void)
> +static u32 notrace arch_counter_get_cntpct32(void)
>   {
> -	u32 cvall, cvalh;
> +	cycle_t cnt = arch_counter_get_cntpct();
>
> -	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> -}
> -
> -static inline cycle_t arch_counter_get_cntvct(void)
> -{
> -	u32 cvall, cvalh;
> -
> -	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
> -
> -	return ((cycle_t) cvalh << 32) | cvall;
> +	/*
> +	 * The sched_clock infrastructure only knows about counters
> +	 * with at most 32bits. Forget about the upper 24 bits for the
> +	 * time being...
> +	 */
> +	return (u32)(cnt & (u32)~0);

Wouldn't a return (u32)cnt be sufficient here?

>   }
>
>   static u32 notrace arch_counter_get_cntvct32(void)
>   {
> -	cycle_t cntvct = arch_counter_get_cntvct();
> +	cycle_t cnt = arch_counter_get_cntvct();
>
>   	/*
>   	 * The sched_clock infrastructure only knows about counters
>   	 * with at most 32bits. Forget about the upper 24 bits for the
>   	 * time being...
>   	 */
> -	return (u32)(cntvct & (u32)~0);
> +	return (u32)(cnt & (u32)~0);
>   }
>
>   static cycle_t arch_counter_read(struct clocksource *cs)
>   {
> +	/*
> +	 * Always use the physical counter for the clocksource.
> +	 * CNTHCTL.PL1PCTEN must be set to 1.
> +	 */
>   	return arch_counter_get_cntpct();
>   }
>
> @@ -245,10 +335,16 @@ static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
>   {
>   	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
>   		 clk->irq, smp_processor_id());
> -	disable_percpu_irq(clk->irq);
> -	if (arch_timer_ppi2)
> -		disable_percpu_irq(arch_timer_ppi2);
> -	arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
> +
> +	if (arch_timer_use_virtual) {
> +		disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
> +		arch_timer_set_mode_virt(CLOCK_EVT_MODE_UNUSED, clk);
> +	} else {
> +		disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
> +		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
> +			disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
> +		arch_timer_set_mode_phys(CLOCK_EVT_MODE_UNUSED, clk);
> +	}
>   }
>
>   static struct local_timer_ops arch_timer_ops __cpuinitdata = {
> @@ -261,36 +357,44 @@ static struct clock_event_device arch_timer_global_evt;
>   static int __init arch_timer_register(void)
>   {
>   	int err;
> +	int ppi;
>
>   	err = arch_timer_available();
>   	if (err)
> -		return err;
> +		goto out;
>
>   	arch_timer_evt = alloc_percpu(struct clock_event_device *);
> -	if (!arch_timer_evt)
> -		return -ENOMEM;
> +	if (!arch_timer_evt) {
> +		err = -ENOMEM;
> +		goto out;
> +	}
>
>   	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
>
> -	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
> -				 "arch_timer", arch_timer_evt);
> +	if (arch_timer_use_virtual) {
> +		ppi = arch_timer_ppi[VIRT_PPI];
> +		err = request_percpu_irq(ppi, arch_timer_handler_virt,
> +					 "arch_timer", arch_timer_evt);
> +	} else {
> +		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
> +		err = request_percpu_irq(ppi, arch_timer_handler_phys,
> +					 "arch_timer", arch_timer_evt);
> +		if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
> +			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
> +			err = request_percpu_irq(ppi, arch_timer_handler_phys,
> +						 "arch_timer", arch_timer_evt);
> +			if (err)
> +				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
> +						arch_timer_evt);
> +		}
> +	}
> +
>   	if (err) {
>   		pr_err("arch_timer: can't register interrupt %d (%d)\n",
> -		       arch_timer_ppi, err);
> +		       ppi, err);
>   		goto out_free;
>   	}
>
> -	if (arch_timer_ppi2) {
> -		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
> -					 "arch_timer", arch_timer_evt);
> -		if (err) {
> -			pr_err("arch_timer: can't register interrupt %d (%d)\n",
> -			       arch_timer_ppi2, err);
> -			arch_timer_ppi2 = 0;
> -			goto out_free_irq;
> -		}
> -	}
> -
>   	err = local_timer_register(&arch_timer_ops);
>   	if (err) {
>   		/*
> @@ -310,13 +414,19 @@ static int __init arch_timer_register(void)
>   	return 0;
>
>   out_free_irq:
> -	free_percpu_irq(arch_timer_ppi, arch_timer_evt);
> -	if (arch_timer_ppi2)
> -		free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
> +	if (arch_timer_use_virtual)
> +		free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
> +	else {
> +		free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
> +				arch_timer_evt);
> +		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
> +			free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
> +					arch_timer_evt);
> +	}
>
>   out_free:
>   	free_percpu(arch_timer_evt);
> -
> +out:
>   	return err;
>   }
>
> @@ -329,6 +439,7 @@ int __init arch_timer_of_register(void)
>   {
>   	struct device_node *np;
>   	u32 freq;
> +	int i;
>
>   	np = of_find_matching_node(NULL, arch_timer_of_match);
>   	if (!np) {
> @@ -340,22 +451,40 @@ int __init arch_timer_of_register(void)
>   	if (!of_property_read_u32(np, "clock-frequency", &freq))
>   		arch_timer_rate = freq;
>
> -	arch_timer_ppi = irq_of_parse_and_map(np, 0);
> -	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
> -	pr_info("arch_timer: found %s irqs %d %d\n",
> -		np->name, arch_timer_ppi, arch_timer_ppi2);
> +	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
> +		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
> +
> +	/*
> +	 * If no interrupt provided for virtual timer, we'll have to
> +	 * stick to the physical timer. It'd better be accessible...
> +	 */
> +	if (!arch_timer_ppi[VIRT_PPI]) {
> +		arch_timer_use_virtual = false;
> +
> +		if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
> +		    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
> +			pr_warn("arch_timer: No interrupt available, giving up\n");
> +			return -EINVAL;
> +		}
> +	}
>
>   	return arch_timer_register();
>   }
>
>   int __init arch_timer_sched_clock_init(void)
>   {
> +	u32 (*cnt32)(void);
>   	int err;
>
>   	err = arch_timer_available();
>   	if (err)
>   		return err;
>
> -	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
> +	if (arch_timer_use_virtual)
> +		cnt32 = arch_counter_get_cntvct32;
> +	else
> +		cnt32 = arch_counter_get_cntpct32;
> +
> +	setup_sched_clock(cnt32, 32, arch_timer_rate);
>   	return 0;
>   }
>

-- 
Thanks
- Cyril


From jason at lakedaemon.net  Thu Aug 30 14:37:11 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 14:37:11 -0400
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830172304.GA18957@n2100.arm.linux.org.uk>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
 <20120830172304.GA18957@n2100.arm.linux.org.uk>
Message-ID: <20120830183711.GY19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 06:23:04PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> > I've CC'd stable to see if they want to pick this up.
> 
> That's not how stable works - and you'll probably receive a standard form
> whinge from them about that.  Please read up on the submission requirements
> to the stable kernel trees.

Ah, thanks.  usually, I just add the Cc: line for fixes I send to
arm-soc.  Since this patch affects more than just kirkwood/marvell, I
didn't feel it was appropriate to pull it in through my tree.

> > It does depend on having dtc built.  A patch already exists to build
> > dtc on demand, but I'm not sure if it has made it into mainline yet.
> > It may be in Russell's queue.
> 
> At the moment, the only stuff I have outstanding for -rc is:
> 
> 36418c5 ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEM
> df547e0 ARM: 7503/1: mm: only flush both pmd entries for classic MMU
> ae3790b ARM: 7502/1: contextidr: avoid using bfi instruction during notifier
> dbece45 ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores
> d968d2b ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all address
> bf88011 ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access
> a849088 ARM: Fix ioremap() of address zero
> 
> I have nothing queued for dtc building, and there's no sign of anything
> new in the patch system.

What I'm referring to is here:

http://lkml.org/lkml/2012/8/28/257

I submitted a patch six months ago for the exact same thing and was
informed that others already had a pending patch in your queue for it.
However, I can't for the life of me locate the thread atm.  I remember
it because it was the first patch I did that needed to go into your
queue instead of through arm-soc.  Obviously, I did something horribly
wrong.  ;-)

thx,

Jason.


From jason at lakedaemon.net  Thu Aug 30 14:50:50 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 14:50:50 -0400
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <20120830180853.GP9886@lunn.ch>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
 <20120830171236.GS19437@titan.lakedaemon.net>
 <20120830180853.GP9886@lunn.ch>
Message-ID: <20120830185050.GZ19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 08:08:53PM +0200, Andrew Lunn wrote:
> On Thu, Aug 30, 2012 at 01:12:36PM -0400, Jason Cooper wrote:
> > On Thu, Aug 30, 2012 at 07:39:12AM +0200, Andrew Lunn wrote:
> > > Linux-next has failed to compile for kirkwood since 23 August with:
> > > 
> > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
> > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)
> > > 
> > > Add missing <linux/sizes.h>
> > > 
> > > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> > 
> > Applied to: fixes-for-v3.6
> > 
> > Also, I added a CC for stable so greg can pick it up.
> 
> Stable does not need it. As i said, it only broke 23 August with
> linux-next. So this is needed for only 3.7.

Do we know caused the break?  Is it a fix destined for -stable?

thx,

Jason.


From tony at atomide.com  Thu Aug 30 14:55:56 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 11:55:56 -0700
Subject: [PATCH 0/9] ARM: OMAP: cleanup plat/board.h file
In-Reply-To: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
References: <1346195937-6383-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <20120830185556.GT1303@atomide.com>

* Igor Grinberg <grinberg at compulab.co.il> [120828 16:19]:
> This patch series cleans up the plat/board.h and related files.

Great, thanks for doing this! Nice that we can finally remove
all of that. I've also tested that 770 boots after this, so
looks like we've already fixed up whatever it was depending on.

I'll be applying this into the cleanup branch as soon as I'll
have an immutable commit for Arnd's treewide changes to move
the obvious things into include/linux/platform_data.

Regards,

Tony


From andrew at lunn.ch  Thu Aug 30 14:59:18 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 30 Aug 2012 20:59:18 +0200
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <20120830185050.GZ19437@titan.lakedaemon.net>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
 <20120830171236.GS19437@titan.lakedaemon.net>
 <20120830180853.GP9886@lunn.ch>
 <20120830185050.GZ19437@titan.lakedaemon.net>
Message-ID: <20120830185918.GR9886@lunn.ch>

> > Stable does not need it. As i said, it only broke 23 August with
> > linux-next. So this is needed for only 3.7.
> 
> Do we know caused the break?  Is it a fix destined for -stable?

I've not bisected it.

     Andrew


From sboyd at codeaurora.org  Thu Aug 30 15:00:06 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 30 Aug 2012 12:00:06 -0700
Subject: [RFC/PATCH] ARM: smp: Fix cpu_up() racing with sys_reboot
In-Reply-To: <20120829235353.GW18957@n2100.arm.linux.org.uk>
References: <1345608229-5707-1-git-send-email-sboyd@codeaurora.org>
 <20120829235353.GW18957@n2100.arm.linux.org.uk>
Message-ID: <503FB836.2060000@codeaurora.org>

On 8/29/2012 4:53 PM, Russell King - ARM Linux wrote:
> On Tue, Aug 21, 2012 at 09:03:49PM -0700, Stephen Boyd wrote:
>> Nothing stops a process from hotplugging in a CPU concurrently
>> with a sys_reboot() call. In such a situation we could have
>> ipi_cpu_stop() mark a cpu as 'offline' and _cpu_up() ignore the
>> fact that the CPU is not really offline and call the
>> CPU_UP_PREPARE notifier. When this happens stop_machine code will
>> complain that the cpu thread already exists and BUG_ON().
> This puts us at odds with x86, which is a bad thing without first
> investigating whether a generic solution which fixes all arches would
> be more appropriate.

I went this way because it seems that we stop CPUs in architecture
specific code instead of doing it generically (although we have
smp_send_stop()?). It would be nice if we could generalize the cpu
stopping code so that reboot at the architectual level doesn't have to
do this.

>
> A better solution may be to mark those CPUs as being not-present,
> which will prevent them being hot-plugged back.

That sounds fine to me. I can s/active/present/ for v2 if we can get
some kind of consensus. I was also thinking we could stop using these
functions entirely and have some private stopped CPUs map that we check
instead.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From tony at atomide.com  Thu Aug 30 15:04:32 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 12:04:32 -0700
Subject: [PATCH 4/4] [RFC] ARM: treewide: manually change more
 mach-*/*.h includes
In-Reply-To: <20120824203622.GB1303@atomide.com>
References: <201208221253.07278.arnd@arndb.de>
 <20120822214323.GA12255@n2100.arm.linux.org.uk>
 <201208231135.11688.arnd@arndb.de>
 <201208231726.11293.arnd@arndb.de>
 <20120824203622.GB1303@atomide.com>
Message-ID: <20120830190431.GU1303@atomide.com>

* Tony Lindgren <tony at atomide.com> [120824 13:37]:
> * Arnd Bergmann <arnd at arndb.de> [120823 10:27]:
> > On Thursday 23 August 2012, Arnd Bergmann wrote:
> > > On Wednesday 22 August 2012, Russell King - ARM Linux wrote:
> > > > In any case, what we should be doing here as well is moving the headers
> > > > included by drivers for platform data out of the arch/arm/mach/ subtrees
> > > > and into include/linux/platform_data.  That will substantially reduce the
> > > > amount of mach/ headers to deal with.
> > > 
> > > I've just looked at the {mach,plat}/*.h files that get included in ARM
> > > specific drivers. Out of the 342 header files that get used in this way,
> > > I found 93 that are practically just platform data, and a few that
> > > are platform_data mixed with something else.
> > > 
> > > How about I move all the pure platform data definition files now and
> > > rebase the other patches on top of that. Here is a list of suggested
> > > file names in include/linux/platform_data/:
> > 
> > I've just scripted this and am running my build testsuite over it now.
> > 
> > Please let me know what you think about it.
> > 
> > 	Arnd
> > 
> > The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
> > 
> >   Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git 
> 
> I'd like to run some checks on this, but branch name missing here for
> pulling a branch in for testing..

FYI, after talking with Arnd this is the testing/platform-data branch
in the arm soc tree. Seems to build and work fine on omaps:

Tested-by: Tony Lindgren <tony at atomide.com>

Arnd, can you please provide a stable branch to use as a base of
other related header changes?

Regards,

Tony


From robherring2 at gmail.com  Thu Aug 30 15:07:18 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 30 Aug 2012 14:07:18 -0500
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120830164551.GY18957@n2100.arm.linux.org.uk>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk> <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk>
Message-ID: <503FB9E6.7020102@gmail.com>

On 08/30/2012 11:45 AM, Russell King - ARM Linux wrote:
> On Thu, Aug 30, 2012 at 10:18:52AM -0500, Rob Herring wrote:
>> Then what do you suggest? I can think of a few alternatives.
>>
>> Leave the current name and make the hidden option a new name like
>> ARCH_xx_OPTIONS. This would require renaming ARCH_xxx for each platform
>> all over the tree. I don't care to sign up for that task...
> 
> Well, requiring everyone to spend hours redoing their configuration also
> isn't practical either.
> 
>> Move platforms one by one out of the choice as they are converted. I
>> can't think of a reason for a platform to be in both places except we
>> would have to figure out something for getting DEBUG_LL to work.
> 
> No you don't.  We've already decided how we're going to deal with
> DEBUG_LL, and we are _not_ going to make that multi-platform.  You
> select one of the output options, and that is it.  We've already
> been moving in that direction, albiet slowly.  Again, anyone who wants
> to be part of a multiplatform kernel better use the provided choice
> or they will get no DEBUG_LL facility - simples.

Right. The problem is with current patches (and Arnd's version) you
cannot select even 1 DEBUG_LL choice as mach/debug-macro.S is not in the
include path any more when multi-plat is enabled. If we move platforms
out of the choice, then we need some way to enable DEBUG_LL.

> 
> That also means we can start to think about moving the mach/debug-macros.S
> header elsewhere, remembering that this facility is shared between the
> decompressor for debugging and the kernel.

I was thinking we could convert the phys and virt addresses to config
values and then the DEBUG_LL choices could just be "Use PL01x uart" and
"Use 8250 uart". This would cut down the number of debug-macro.S files
and choices.

Using a fixed virtual address for all platforms might also help simplify
DEBUG_LL.

But I'd like to find a more simple solution to get past enabling
multi-platform and deal with a more complex change later.

Rob

> Remember that DEBUG_LL is the low-level *debug* facility.  It is not
> the early console, even if it ended up being used as such (which is
> not something I really care for.)  Read the previous discussions on
> this subject if you disagree, but I'm not changing my position over
> DEBUG_LL because that will just require me to re-invent the facility
> yet again (which is what DEBUG_LL is there to stop.)  It was _never_
> intended to be an early console facility.
> 



From linux at arm.linux.org.uk  Thu Aug 30 15:14:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 20:14:12 +0100
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830183711.GY19437@titan.lakedaemon.net>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
 <20120830172304.GA18957@n2100.arm.linux.org.uk>
 <20120830183711.GY19437@titan.lakedaemon.net>
Message-ID: <20120830191412.GC18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 02:37:11PM -0400, Jason Cooper wrote:
> On Thu, Aug 30, 2012 at 06:23:04PM +0100, Russell King - ARM Linux wrote:
> > On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> > > I've CC'd stable to see if they want to pick this up.
> > 
> > That's not how stable works - and you'll probably receive a standard form
> > whinge from them about that.  Please read up on the submission requirements
> > to the stable kernel trees.
> 
> Ah, thanks.  usually, I just add the Cc: line for fixes I send to
> arm-soc.  Since this patch affects more than just kirkwood/marvell, I
> didn't feel it was appropriate to pull it in through my tree.

Yes, you put the Cc: line in the commit, but you don't actually send it
to that address.  The only time that you do mail that address is when
the commit is _in_ mainline and it doesn't have the Cc: tag or the stable
team haven't picked it up.

> I submitted a patch six months ago for the exact same thing and was
> informed that others already had a pending patch in your queue for it.
> However, I can't for the life of me locate the thread atm.  I remember
> it because it was the first patch I did that needed to go into your
> queue instead of through arm-soc.  Obviously, I did something horribly
> wrong.  ;-)

I don't see anything in there for it - I tried searching for patches
containing 'dtbs' and the latest one it found was 7152/1 on 8th
November.  I also see no notifications from the patch system for a
patch from you...


From linux at arm.linux.org.uk  Thu Aug 30 15:28:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 30 Aug 2012 20:28:31 +0100
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <503FB9E6.7020102@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk> <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk> <503FB9E6.7020102@gmail.com>
Message-ID: <20120830192831.GD18957@n2100.arm.linux.org.uk>

On Thu, Aug 30, 2012 at 02:07:18PM -0500, Rob Herring wrote:
> On 08/30/2012 11:45 AM, Russell King - ARM Linux wrote:
> > That also means we can start to think about moving the mach/debug-macros.S
> > header elsewhere, remembering that this facility is shared between the
> > decompressor for debugging and the kernel.
> 
> I was thinking we could convert the phys and virt addresses to config
> values and then the DEBUG_LL choices could just be "Use PL01x uart" and
> "Use 8250 uart". This would cut down the number of debug-macro.S files
> and choices.
> 
> Using a fixed virtual address for all platforms might also help simplify
> DEBUG_LL.

No it won't, that comment says you totally don't understand the feature
you're playing with to me.

It's not only about virtual addresses, it's about physical addresses too,
and we can't dictate that all hardware exposes a UART at any particular
physical address.

Remember that the code provided by DEBUG_LL is used in the early kernel
bring up to set up the phys:virt mapping for the UART, it's also used by
the early kernel code to access the UART at the physical address, and by
the decompressor to also access the UART at the physical address.

So playing around with fixing it at a specific virtual address is total
poppycock, and is completely worthless.

I think what we need is arch/arm/include/debug, move the platform specific
debug-macros headers into there, named using platform specific file names.
Then we have the config system define a string-based config:

config DEBUG_LL_INCLUDE
	string
	default "<debug/icedcc.S>" if DEBUG_ICEDCC
	default "<debug/msm.S>" if DEBUG_MSM_UART1 || DEBUG_MSM_UART2 || DEBUG_MSM_UART3
... etc ...
	default "mach/debug-macros.S"

And then we can have the various assembly codes do:

#include CONFIG_DEBUG_LL_INCLUDE

Not only does this give a migration path, but it also gives folk a reason
to move to the 'new way' if they want to be part of a multi-platform
kernel - and it's a trivial thing to do.  Just move the include file,
add an entry to the DEBUG_LL_INCLUDE entry and the "Kernel low-level
debugging port" choice statement, and job done for both non-multi-platform
and multi-platform kernels.

What's even nicer about this approach is it doesn't require everyone to
change simultaneously - it can be done progressively as required.


From jason at lakedaemon.net  Thu Aug 30 15:40:43 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 15:40:43 -0400
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830191412.GC18957@n2100.arm.linux.org.uk>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
 <20120830172304.GA18957@n2100.arm.linux.org.uk>
 <20120830183711.GY19437@titan.lakedaemon.net>
 <20120830191412.GC18957@n2100.arm.linux.org.uk>
Message-ID: <20120830194043.GA19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 08:14:12PM +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 30, 2012 at 02:37:11PM -0400, Jason Cooper wrote:
> > On Thu, Aug 30, 2012 at 06:23:04PM +0100, Russell King - ARM Linux wrote:
> > > On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
...
> > I submitted a patch six months ago for the exact same thing and was
> > informed that others already had a pending patch in your queue for it.
> > However, I can't for the life of me locate the thread atm.  I remember
> > it because it was the first patch I did that needed to go into your
> > queue instead of through arm-soc.  Obviously, I did something horribly
> > wrong.  ;-)
> 
> I don't see anything in there for it - I tried searching for patches
> containing 'dtbs' and the latest one it found was 7152/1 on 8th
> November.  I also see no notifications from the patch system for a
> patch from you...

I should have been more clear, I sent it to lakml, was told to send it
to your queue, and then I was told there was already a patch by someone
else in your queue.  So, I dropped mine from the next version of my
dreamplug series.  Sorry to generate unnecessary searching on your part.

Since it still hasn't made it in, I'll ask David Brown to feed his
version into your queue.

thx,

Jason.


From jason at lakedaemon.net  Thu Aug 30 15:47:06 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 30 Aug 2012 15:47:06 -0400
Subject: [PATCH] ARM: Make sure dtc is built before running it
In-Reply-To: <1346180398-8079-1-git-send-email-davidb@codeaurora.org>
References: <1346180398-8079-1-git-send-email-davidb@codeaurora.org>
Message-ID: <20120830194706.GB19437@titan.lakedaemon.net>

On Tue, Aug 28, 2012 at 11:59:58AM -0700, David Brown wrote:
> 'make dtbs' in a clean tree will try running the dtc before actually
> building it.  Make these rules depend upon the scripts to build it.

David,

Could you please send this into rmk's queue? [1]  This fix has been
cropping up by various submitters for the past 6 months or so, it would
be nice to finally get it in.

thx,

Jason.

[1] http://www.arm.linux.org.uk/developer/patches/

> ---
>  arch/arm/Makefile | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 0298b00..926d840 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -279,10 +279,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
>  zinstall uinstall install: vmlinux
>  	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
>  
> -%.dtb:
> +%.dtb: scripts
>  	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
>  
> -dtbs:
> +dtbs: scripts
>  	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
>  
>  # We use MRPROPER_FILES and CLEAN_FILES now
> -- 
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tony at atomide.com  Thu Aug 30 16:14:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:14:16 -0700
Subject: [RFC RESEND 1/4] arm/dts: OMAP: Add timer nodes
In-Reply-To: <502D0BEE.3010609@ti.com>
References: <1342218413-30116-1-git-send-email-jon-hunter@ti.com>
 <1342218413-30116-2-git-send-email-jon-hunter@ti.com>
 <5000D647.4090200@gmail.com> <500439A8.1050705@ti.com>
 <500D6CAB.4030504@ti.com> <502B67DD.6050904@ti.com>
 <502D0BEE.3010609@ti.com>
Message-ID: <20120830201415.GX1303@atomide.com>

* Jon Hunter <jon-hunter at ti.com> [120816 08:05]:
> On 08/15/2012 04:11 AM, Vaibhav Hiremath wrote:
> > 
> > Did we get conclude on this? I haven't got anything further on this
> > thread, this may block baseport support for the new devices in omap2
> > family, like AM33xx and OMAP5.
> 
> Sorry I have been out of the office. However, no update on this so far.
> I need to check with Tony if he has any preference for handling this. I
> will follow-up with him and keep you posted.

Jon please repost these without the RFC in the subject line
assuming the pending comments have been addressed so people
can ack them.

Regards,

Tony


From m-karicheri2 at ti.com  Thu Aug 30 16:18:49 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Thu, 30 Aug 2012 20:18:49 +0000
Subject: [PATCH - 2/2] arm: disable caches based on config option
In-Reply-To: <alpine.LFD.2.02.1208301156390.1784@xanadu.home>
References: <1346337826-27232-1-git-send-email-m-karicheri2@ti.com>
 <1346337826-27232-2-git-send-email-m-karicheri2@ti.com>
 <alpine.LFD.2.02.1208301156390.1784@xanadu.home>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041AD7AD@DFLE12.ent.ti.com>

Submitted. Thanks.

Murali Karicheri
Software Design Engineer


>> -----Original Message-----
>> From: Nicolas Pitre [mailto:nicolas.pitre at linaro.org]
>> Sent: Thursday, August 30, 2012 11:59 AM
>> To: Karicheri, Muralidharan
>> Cc: Russell King - ARM Linux; tony at atomide.com; Shilimkar, Santosh; wim at iguana.be;
>> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
>> Subject: Re: [PATCH - 2/2] arm: disable caches based on config option
>> 
>> On Thu, 30 Aug 2012, Murali Karicheri wrote:
>> 
>> > CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE are available
>> > to allow disabling of D-Cache and I-Cache. However the compressed version
>> > of head.S currently doesn't check these variables. This patch will fix
>> > this issue and is written similar to the uncompressed version of head.S
>> >
>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> 
>> Acked-by: nicolas Pitre <nico at linaro.org>
>> 
>> You may submit your patch to http://www.arm.linux.org.uk/developer/patches/.
>> 
>> 
>> > ---
>> >  arch/arm/boot/compressed/head.S |    6 ++++++
>> >  1 file changed, 6 insertions(+)
>> >
>> > diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
>> > index b8c64b8..e1d2124 100644
>> > --- a/arch/arm/boot/compressed/head.S
>> > +++ b/arch/arm/boot/compressed/head.S
>> > @@ -659,6 +659,12 @@ __armv7_mmu_cache_on:
>> >  #ifdef CONFIG_CPU_ENDIAN_BE8
>> >  		orr	r0, r0, #1 << 25	@ big-endian page tables
>> >  #endif
>> > +#ifdef CONFIG_CPU_DCACHE_DISABLE
>> > +		bic	r0, r0, #1 << 2
>> > +#endif
>> > +#ifdef CONFIG_CPU_ICACHE_DISABLE
>> > +		bic	r0, r0, #1 << 12
>> > +#endif
>> >  		orrne	r0, r0, #1		@ MMU enabled
>> >  		movne	r1, #0xfffffffd		@ domain 0 = client
>> >  		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
>> > --
>> > 1.7.9.5
>> >


From tony at atomide.com  Thu Aug 30 16:20:58 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:20:58 -0700
Subject: [PATCH] ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
In-Reply-To: <503E9129.9060408@compulab.co.il>
References: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>
 <CAMQu2gxZBq0wMw4rgbFpDT2pmA83ULKAJ-Mwv+VKvQQZMRQ4Dw@mail.gmail.com>
 <503E9129.9060408@compulab.co.il>
Message-ID: <20120830202057.GY1303@atomide.com>

* Igor Grinberg <grinberg at compulab.co.il> [120829 15:02]:
> On 08/28/12 01:43, Shilimkar, Santosh wrote:
> > On Mon, Aug 27, 2012 at 3:26 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> >> Currently, omap2_sync32k_clocksource_init() function initializes the 32K
> >> timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
> >> setting.
> >> Fix this by providing a default implementation for
> >> !CONFIG_OMAP_32K_TIMER case.
> >>
> >> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> >> Reviewed-by: Paul Walmsley <paul at pwsan.com>
> >> ---
> > Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> 
> Thanks Santosh!
> 
> Tony, apparently, this bug has been there for a while,
> so probably I should have added:
> Cc: stable at vger.kernel.org

Thanks I'll apply this into fixes with Cc: stable. Note that
Cc: stable is usually added at commit time, or at least you're
not supposed to send the patch for review there.

Regards,

Tony


From tony at atomide.com  Thu Aug 30 16:27:08 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:27:08 -0700
Subject: [PATCH 0/5] hwrng/ARM: OMAP: convert to use runtime PM
In-Reply-To: <20120827232922.15045.56522.stgit@dusk.lan>
References: <20120827232922.15045.56522.stgit@dusk.lan>
Message-ID: <20120830202708.GZ1303@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120827 16:39]:
> This series converts the OMAP hardware random number generator driver
> to use runtime PM.  Hardware integration data is added for OMAP2xxx
> systems.  I'm pretty sure this device is available on other OMAP chips
> too, but may require some experimentation with the integration details.

Good to hear. I believe that at some point this got moved to be
only accessible in the secure mode on later omaps?
 
> There are still a few rough edges with this series.  Something is
> still not right with the reset behavior on OMAP2430, at least.  But it
> would be good to get acks from the hwrng folks for the three patches that
> touch files in that directory.  Will continue with the testing process
> here.

Yes Matt & Herbert, care to ack the drivers/char/hw_random related changes?

This series will conflict with the planned ARM common zImage changes
that we have planned so I'd like to merge them via the ARM soc tree.

Regards,

Tony
 
> - Paul
> 
> ---
> 
> Paul Walmsley (5):
>       ARM: OMAP2/3: hwmod: add RNG integration data
>       hwrng: OMAP: store per-device data in per-device variables, not file statics
>       hwrng: OMAP: convert to use runtime PM
>       ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
>       hwrng: OMAP: remove SoC restrictions from driver registration
> 
> 
>  arch/arm/mach-omap1/devices.c                      |   28 +++++
>  arch/arm/mach-omap2/devices.c                      |   18 +++
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    1 
>  .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |   17 +++
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   37 ++++++
>  arch/arm/mach-omap2/omap_hwmod_common_data.h       |    5 -
>  arch/arm/plat-omap/Makefile                        |    3 
>  arch/arm/plat-omap/devices.c                       |   92 ---------------
>  drivers/char/hw_random/omap-rng.c                  |  121 ++++++++++++--------
>  10 files changed, 176 insertions(+), 147 deletions(-)
>  delete mode 100644 arch/arm/plat-omap/devices.c
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From herbert at gondor.apana.org.au  Thu Aug 30 16:29:25 2012
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Thu, 30 Aug 2012 13:29:25 -0700
Subject: [PATCH 0/5] hwrng/ARM: OMAP: convert to use runtime PM
In-Reply-To: <20120830202708.GZ1303@atomide.com>
References: <20120827232922.15045.56522.stgit@dusk.lan>
 <20120830202708.GZ1303@atomide.com>
Message-ID: <20120830202925.GA32300@gondor.apana.org.au>

On Thu, Aug 30, 2012 at 01:27:08PM -0700, Tony Lindgren wrote:
> * Paul Walmsley <paul at pwsan.com> [120827 16:39]:
> > This series converts the OMAP hardware random number generator driver
> > to use runtime PM.  Hardware integration data is added for OMAP2xxx
> > systems.  I'm pretty sure this device is available on other OMAP chips
> > too, but may require some experimentation with the integration details.
> 
> Good to hear. I believe that at some point this got moved to be
> only accessible in the secure mode on later omaps?
>  
> > There are still a few rough edges with this series.  Something is
> > still not right with the reset behavior on OMAP2430, at least.  But it
> > would be good to get acks from the hwrng folks for the three patches that
> > touch files in that directory.  Will continue with the testing process
> > here.
> 
> Yes Matt & Herbert, care to ack the drivers/char/hw_random related changes?

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>

> This series will conflict with the planned ARM common zImage changes
> that we have planned so I'd like to merge them via the ARM soc tree.

Thanks,
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From tony at atomide.com  Thu Aug 30 16:32:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:32:35 -0700
Subject: [PATCH RESEND v4 1/3] arm/dts: AM33XX: Add basic pinctrl
 device tree data
In-Reply-To: <1346141454-18786-2-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
 <1346141454-18786-2-git-send-email-anilkumar@ti.com>
Message-ID: <20120830203234.GA1303@atomide.com>

* AnilKumar Ch <anilkumar at ti.com> [120828 01:11]:
> Adds basic pinctrl device tree data for AM33XX family of devices.
> This patch is based on the pinctrl-single driver.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index dde76f7..dfe9c559 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -40,6 +40,15 @@
>  		};
>  	};
>  
> +	am3358_pinmux: pinmux at 44E10800 {
> +		compatible = "pinctrl-single";
> +		reg = <0x44E10800 0x0238>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		pinctrl-single,register-width = <32>;
> +		pinctrl-single,function-mask = <0x7F>;
> +	};
> +

Nit: Please use lower case for the hex numbers as that's the
standard in Linux kernel.

Tony


From tony at atomide.com  Thu Aug 30 16:35:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:35:06 -0700
Subject: [PATCH RESEND v4 2/3] arm/dts: AM33XX: Configure pinmuxs for
 user leds control on Bone
In-Reply-To: <1346141454-18786-3-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
 <1346141454-18786-3-git-send-email-anilkumar@ti.com>
Message-ID: <20120830203505.GB1303@atomide.com>

* AnilKumar Ch <anilkumar at ti.com> [120828 01:11]:
> Adds GPIO pinctrl nodes to am3358_pinmux master node to control
> user leds (USR0, USR1, USR2 and USR3) present on BeagleBone.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
> index a7906cb..58f5042 100644
> --- a/arch/arm/boot/dts/am335x-bone.dts
> +++ b/arch/arm/boot/dts/am335x-bone.dts
> @@ -18,6 +18,20 @@
>  		reg = <0x80000000 0x10000000>; /* 256 MB */
>  	};
>  
> +	am3358_pinmux: pinmux at 44E10800 {
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&userled_pins>;
> +
> +		userled_pins: pinmux_userled_pins {
> +			pinctrl-single,pins = <
> +				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
> +				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
> +				0x5C 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
> +				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
> +			>;
> +		};
> +	};
> +

Looks like this patch should also claim these pins by the led driver.
Then the led driver should just do pinctrl_get_select_default(&pdev->dev)
in it's probe function to set the pins.

Tony



From tony at atomide.com  Thu Aug 30 16:35:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:35:59 -0700
Subject: [PATCH v4 3/3] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <1346141454-18786-4-git-send-email-anilkumar@ti.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
 <1346141454-18786-4-git-send-email-anilkumar@ti.com>
Message-ID: <20120830203558.GC1303@atomide.com>

* AnilKumar Ch <anilkumar at ti.com> [120828 01:11]:
> Add Bosch D_CAN controller device tree data to AM33XX dtsi
> file by adding d_can device nodes with all the necessary
> parameters.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  arch/arm/boot/dts/am33xx.dtsi |   18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index dfe9c559..d965137 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -177,5 +177,23 @@
>  			compatible = "ti,omap3-wdt";
>  			ti,hwmods = "wd_timer2";
>  		};
> +
> +		dcan0: d_can at 481CC000 {
> +			compatible = "bosch,d_can";
> +			ti,hwmods = "d_can0";
> +			reg = <0x481CC000 0x2000>;
> +			interrupts = <52>;
> +			interrupt-parent = <&intc>;
> +			status = "disabled";
> +		};
> +
> +		dcan1: d_can at 481D0000 {
> +			compatible = "bosch,d_can";
> +			ti,hwmods = "d_can1";
> +			reg = <0x481D0000 0x2000>;
> +			interrupts = <55>;
> +			interrupt-parent = <&intc>;
> +			status = "disabled";
> +		};
>  	};
>  };

Use lower case for hex numbers here too and add support to claim the pins
in the dcan driver.

Tony


From tony at atomide.com  Thu Aug 30 16:48:26 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 13:48:26 -0700
Subject: [PATCH 2/2] arm/dts: Cleanup regulator naming and remove @0,1..
In-Reply-To: <503C6380.4090107@ti.com>
References: <1343653940-16614-1-git-send-email-rnayak@ti.com>
 <1343653940-16614-3-git-send-email-rnayak@ti.com>
 <20120824202725.GA1303@atomide.com> <503C6380.4090107@ti.com>
Message-ID: <20120830204825.GE1303@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120827 23:22]:
> Hi Tony,
> 
> >* Rajendra Nayak<rnayak at ti.com>  [120730 06:17]:
> >>regulators do not have a 'reg' property, hence the regulator at 0,
> >>regulator at 1 do not make sense. get rid of it.
> >
> >Looks like this needs to be refreshed to apply. Care to
> >refresh against current devel-dt branch in case other
> >places need the same change?
> 
> Looks like devel-dt is missing the PATCH 1/2 from this series,
> which you have already pushed in the -rc for merge.
> With that applied, this ones applies cleanly too.

Oh OK thanks :) I'll apply it on top of the fix and merge
into devel-dt.

Tony


From paul at pwsan.com  Thu Aug 30 16:56:14 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 30 Aug 2012 20:56:14 +0000 (UTC)
Subject: [PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk
In-Reply-To: <1346230576-20004-1-git-send-email-rnayak@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
Message-ID: <alpine.DEB.2.00.1208302052210.29754@utopia.booyaka.com>

Hi Rajendra

On Wed, 29 Aug 2012, Rajendra Nayak wrote:

> Changes in v4:
> * Added *hack* comments around clk_prepare usage in hwmod
> rebased on 3.6-rc

Assuming this is so (haven't looked closely at this series yet), and after 
the existing comments are taken into consideration and a new version 
reposted, will queue this series for 3.7.

Care to respin your series that converts the data also, on top of your new 
version of this series?  We should try to get that into 3.7 also.
BTW are you still waiting for something from Vaibhav Hiremath for this?  
Or can the scripts convert the existing clock33xx_data.c also?


- Paul


From paul at pwsan.com  Thu Aug 30 16:57:30 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 30 Aug 2012 20:57:30 +0000 (UTC)
Subject: [PATCH 0/5] hwrng/ARM: OMAP: convert to use runtime PM
In-Reply-To: <20120830202925.GA32300@gondor.apana.org.au>
References: <20120827232922.15045.56522.stgit@dusk.lan>
 <20120830202708.GZ1303@atomide.com>
 <20120830202925.GA32300@gondor.apana.org.au>
Message-ID: <alpine.DEB.2.00.1208302056330.29754@utopia.booyaka.com>

On Thu, 30 Aug 2012, Herbert Xu wrote:

> Acked-by: Herbert Xu <herbert at gondor.apana.org.au>

Great, thanks Herbert.

At some point in the next month or so, there should be similar series for 
the OMAP crypto IP blocks too, which will need some acks - just as a 
heads-up.


- Paul


From tony at atomide.com  Thu Aug 30 17:01:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 14:01:10 -0700
Subject: [PATCH v3 0/4] Add AM33XX regulators device tree data
In-Reply-To: <20120821135738.GJ7995@opensource.wolfsonmicro.com>
References: <1345547850-29761-1-git-send-email-anilkumar@ti.com>
 <20120821135738.GJ7995@opensource.wolfsonmicro.com>
Message-ID: <20120830210109.GG1303@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120821 06:58]:
> On Tue, Aug 21, 2012 at 04:47:26PM +0530, AnilKumar Ch wrote:
> > This patch series add AM33XX regulators (tps65910/tps65217) device
> > tree data to am335x-evm and am335x-bone dts files. These patches
> > are based on Tony L "devel-dt" tree with these patches
> > http://www.mail-archive.com/linux-omap at vger.kernel.org/msg73843.html
> > and these patches has been tested on AM335x EVM and Bone devices.
> 
> Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

Applying these into omap devel-dt branch.

Tony


From nicolas.pitre at linaro.org  Thu Aug 30 17:01:18 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 30 Aug 2012 17:01:18 -0400 (EDT)
Subject: [PATCH 0/6] Integrator devicetree support
In-Reply-To: <alpine.LFD.2.02.1208191148520.1754@xanadu.home>
References: <1345119317-22600-1-git-send-email-linus.walleij@linaro.org>
 <201208161344.55723.arnd@arndb.de>
 <CACRpkdYYgdzAU=nyL7dQbdMLx3z3G+K7ba0uJe1=aX=BLeF_sg@mail.gmail.com>
 <alpine.LFD.2.02.1208191148520.1754@xanadu.home>
Message-ID: <alpine.LFD.2.02.1208301659070.1784@xanadu.home>

On Sun, 19 Aug 2012, Nicolas Pitre wrote:

> On Sun, 19 Aug 2012, Linus Walleij wrote:
> 
> > But then we hit #ifdeffing and compiling out a lot of dangerous stuff
> > in arch/arm/kernel and then I get the creeps. I can try, but I think
> > this is typical Nico territory for example...
> 
> I did post a patch moving all the ATAG stuff to a separate source file a 
> while ago, exactly for that purpose.  I should try to dig it out and 
> refresh it.

OK... In this case "a while ago" = 2 years!

Please see the 2 patches to follow.


Nicolas


From nicolas.pitre at linaro.org  Thu Aug 30 17:10:07 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 30 Aug 2012 17:10:07 -0400
Subject: [PATCH 1/2] ARM: split out ATAGS parsing
Message-ID: <1346361008-7320-1-git-send-email-nicolas.pitre@linaro.org>

Make ATAGS parsing into a source file of its own, namely atags_parse.c.
Also rename compat.c to atags_compat.c to make it clearer what it is
about.  Same for atags.c which is now atags_proc.c. Gather all the atags
function declarations into a common atags.h.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/kernel/Makefile                     |   6 +-
 arch/arm/kernel/atags.h                      |   3 +
 arch/arm/kernel/{compat.c => atags_compat.c} |   4 +-
 arch/arm/kernel/atags_parse.c                | 238 +++++++++++++++++++++++++++
 arch/arm/kernel/{atags.c => atags_proc.c}    |   0
 arch/arm/kernel/compat.h                     |  11 --
 arch/arm/kernel/setup.c                      | 236 +-------------------------
 7 files changed, 247 insertions(+), 251 deletions(-)
 rename arch/arm/kernel/{compat.c => atags_compat.c} (99%)
 create mode 100644 arch/arm/kernel/atags_parse.c
 rename arch/arm/kernel/{atags.c => atags_proc.c} (100%)
 delete mode 100644 arch/arm/kernel/compat.h

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5cf70..086c9d3bc3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,11 +15,11 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y		:= atags_parse.o elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 		   process.o ptrace.o return_address.o sched_clock.o \
 		   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
-obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
 obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)		+= etm.o
@@ -52,7 +52,7 @@ test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs		+= kprobes-test-arm.o
 endif
-obj-$(CONFIG_ATAGS_PROC)	+= atags.o
+obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
index e5f028d214..a888fdd381 100644
--- a/arch/arm/kernel/atags.h
+++ b/arch/arm/kernel/atags.h
@@ -3,3 +3,6 @@ extern void save_atags(struct tag *tags);
 #else
 static inline void save_atags(struct tag *tags) { }
 #endif
+
+void convert_to_tag_list(struct tag *tags);
+struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr);
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/atags_compat.c
similarity index 99%
rename from arch/arm/kernel/compat.c
rename to arch/arm/kernel/atags_compat.c
index 925652318b..5236ad38f4 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/atags_compat.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/kernel/compat.c
+ *  linux/arch/arm/kernel/atags_compat.c
  *
  *  Copyright (C) 2001 Russell King
  *
@@ -26,7 +26,7 @@
 
 #include <asm/mach/arch.h>
 
-#include "compat.h"
+#include "atags.h"
 
 /*
  * Usage:
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
new file mode 100644
index 0000000000..18f13be99e
--- /dev/null
+++ b/arch/arm/kernel/atags_parse.c
@@ -0,0 +1,238 @@
+/*
+ * Tag parsing.
+ *
+ * Copyright (C) 1995-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This is the traditional way of passing data to the kernel at boot time.  Rather
+ * than passing a fixed inflexible structure to the kernel, we pass a list
+ * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
+ * tag for the list to be recognised (to distinguish the tagged list from
+ * a param_struct).  The list is terminated with a zero-length tag (this tag
+ * is not parsed in any way).
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/screen_info.h>
+
+#include <asm/setup.h>
+#include <asm/system_info.h>
+#include <asm/page.h>
+#include <asm/mach/arch.h>
+
+#include "atags.h"
+
+static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
+
+#ifndef MEM_SIZE
+#define MEM_SIZE	(16*1024*1024)
+#endif
+
+static struct {
+	struct tag_header hdr1;
+	struct tag_core   core;
+	struct tag_header hdr2;
+	struct tag_mem32  mem;
+	struct tag_header hdr3;
+} default_tags __initdata = {
+	{ tag_size(tag_core), ATAG_CORE },
+	{ 1, PAGE_SIZE, 0xff },
+	{ tag_size(tag_mem32), ATAG_MEM },
+	{ MEM_SIZE },
+	{ 0, ATAG_NONE }
+};
+
+static int __init parse_tag_core(const struct tag *tag)
+{
+	if (tag->hdr.size > 2) {
+		if ((tag->u.core.flags & 1) == 0)
+			root_mountflags &= ~MS_RDONLY;
+		ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
+	}
+	return 0;
+}
+
+__tagtable(ATAG_CORE, parse_tag_core);
+
+static int __init parse_tag_mem32(const struct tag *tag)
+{
+	return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
+}
+
+__tagtable(ATAG_MEM, parse_tag_mem32);
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
+static int __init parse_tag_videotext(const struct tag *tag)
+{
+	screen_info.orig_x            = tag->u.videotext.x;
+	screen_info.orig_y            = tag->u.videotext.y;
+	screen_info.orig_video_page   = tag->u.videotext.video_page;
+	screen_info.orig_video_mode   = tag->u.videotext.video_mode;
+	screen_info.orig_video_cols   = tag->u.videotext.video_cols;
+	screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
+	screen_info.orig_video_lines  = tag->u.videotext.video_lines;
+	screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
+	screen_info.orig_video_points = tag->u.videotext.video_points;
+	return 0;
+}
+
+__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
+#endif
+
+#ifdef CONFIG_BLK_DEV_RAM
+static int __init parse_tag_ramdisk(const struct tag *tag)
+{
+	extern int rd_size, rd_image_start, rd_prompt, rd_doload;
+
+	rd_image_start = tag->u.ramdisk.start;
+	rd_doload = (tag->u.ramdisk.flags & 1) == 0;
+	rd_prompt = (tag->u.ramdisk.flags & 2) == 0;
+
+	if (tag->u.ramdisk.size)
+		rd_size = tag->u.ramdisk.size;
+
+	return 0;
+}
+
+__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
+#endif
+
+static int __init parse_tag_serialnr(const struct tag *tag)
+{
+	system_serial_low = tag->u.serialnr.low;
+	system_serial_high = tag->u.serialnr.high;
+	return 0;
+}
+
+__tagtable(ATAG_SERIAL, parse_tag_serialnr);
+
+static int __init parse_tag_revision(const struct tag *tag)
+{
+	system_rev = tag->u.revision.rev;
+	return 0;
+}
+
+__tagtable(ATAG_REVISION, parse_tag_revision);
+
+static int __init parse_tag_cmdline(const struct tag *tag)
+{
+#if defined(CONFIG_CMDLINE_EXTEND)
+	strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
+	strlcat(default_command_line, tag->u.cmdline.cmdline,
+		COMMAND_LINE_SIZE);
+#elif defined(CONFIG_CMDLINE_FORCE)
+	pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
+#else
+	strlcpy(default_command_line, tag->u.cmdline.cmdline,
+		COMMAND_LINE_SIZE);
+#endif
+	return 0;
+}
+
+__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
+
+/*
+ * Scan the tag table for this tag, and call its parse function.
+ * The tag table is built by the linker from all the __tagtable
+ * declarations.
+ */
+static int __init parse_tag(const struct tag *tag)
+{
+	extern struct tagtable __tagtable_begin, __tagtable_end;
+	struct tagtable *t;
+
+	for (t = &__tagtable_begin; t < &__tagtable_end; t++)
+		if (tag->hdr.tag == t->tag) {
+			t->parse(tag);
+			break;
+		}
+
+	return t < &__tagtable_end;
+}
+
+/*
+ * Parse all tags in the list, checking both the global and architecture
+ * specific tag tables.
+ */
+static void __init parse_tags(const struct tag *t)
+{
+	for (; t->hdr.size; t = tag_next(t))
+		if (!parse_tag(t))
+			printk(KERN_WARNING
+				"Ignoring unrecognised tag 0x%08x\n",
+				t->hdr.tag);
+}
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+	for (; tag->hdr.size; tag = tag_next(tag))
+		if (tag->hdr.tag == ATAG_MEM)
+			tag->hdr.tag = ATAG_NONE;
+}
+
+struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer,
+						unsigned int machine_nr)
+{
+	struct tag *tags = (struct tag *)&default_tags;
+	struct machine_desc *mdesc = NULL, *p;
+	char *from = default_command_line;
+
+	default_tags.mem.start = PHYS_OFFSET;
+
+	/*
+	 * locate machine in the list of supported machines.
+	 */
+	for_each_machine_desc(p)
+		if (machine_nr == p->nr) {
+			printk("Machine: %s\n", p->name);
+			mdesc = p;
+			break;
+		}
+
+	if (!mdesc) {
+		early_print("\nError: unrecognized/unsupported machine ID"
+			    " (r1 = 0x%08x).\n\n", machine_nr);
+		dump_machine_table(); /* does not return */
+	}
+	
+	if (__atags_pointer)
+		tags = phys_to_virt(__atags_pointer);
+	else if (mdesc->atag_offset)
+		tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
+
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
+	/*
+	 * If we have the old style parameters, convert them to
+	 * a tag list.
+	 */
+	if (tags->hdr.tag != ATAG_CORE)
+		convert_to_tag_list(tags);
+#endif
+	if (tags->hdr.tag != ATAG_CORE) {
+		early_print("Warning: Neither atags nor dtb found\n");
+		tags = (struct tag *)&default_tags;
+	}
+
+	if (mdesc->fixup)
+		mdesc->fixup(tags, &from, &meminfo);
+
+	if (tags->hdr.tag == ATAG_CORE) {
+		if (meminfo.nr_banks != 0)
+			squash_mem_tags(tags);
+		save_atags(tags);
+		parse_tags(tags);
+	}
+
+	/* parse_early_param needs a boot_command_line */
+	strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+	return mdesc;
+}
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags_proc.c
similarity index 100%
rename from arch/arm/kernel/atags.c
rename to arch/arm/kernel/atags_proc.c
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
deleted file mode 100644
index 39264ab1b9..0000000000
--- a/arch/arm/kernel/compat.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  linux/arch/arm/kernel/compat.h
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void convert_to_tag_list(struct tag *tags);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a81dcecc73..0785472460 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,11 +21,9 @@
 #include <linux/init.h>
 #include <linux/kexec.h>
 #include <linux/of_fdt.h>
-#include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
-#include <linux/fs.h>
 #include <linux/proc_fs.h>
 #include <linux/memblock.h>
 #include <linux/bug.h>
@@ -56,15 +54,9 @@
 #include <asm/unwind.h>
 #include <asm/memblock.h>
 
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-#include "compat.h"
-#endif
 #include "atags.h"
 #include "tcm.h"
 
-#ifndef MEM_SIZE
-#define MEM_SIZE	(16*1024*1024)
-#endif
 
 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
 char fpe_type[8];
@@ -145,7 +137,6 @@ static const char *machine_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
 struct machine_desc *machine_desc __initdata;
 
-static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
 #define ENDIANNESS ((char)endian_test.l)
 
@@ -583,21 +574,6 @@ static int __init early_mem(char *p)
 }
 early_param("mem", early_mem);
 
-static void __init
-setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
-{
-#ifdef CONFIG_BLK_DEV_RAM
-	extern int rd_size, rd_image_start, rd_prompt, rd_doload;
-
-	rd_image_start = image_start;
-	rd_prompt = prompt;
-	rd_doload = doload;
-
-	if (rd_sz)
-		rd_size = rd_sz;
-#endif
-}
-
 static void __init request_standard_resources(struct machine_desc *mdesc)
 {
 	struct memblock_region *region;
@@ -643,35 +619,6 @@ static void __init request_standard_resources(struct machine_desc *mdesc)
 		request_resource(&ioport_resource, &lp2);
 }
 
-/*
- *  Tag parsing.
- *
- * This is the new way of passing data to the kernel at boot time.  Rather
- * than passing a fixed inflexible structure to the kernel, we pass a list
- * of variable-sized tags to the kernel.  The first tag must be a ATAG_CORE
- * tag for the list to be recognised (to distinguish the tagged list from
- * a param_struct).  The list is terminated with a zero-length tag (this tag
- * is not parsed in any way).
- */
-static int __init parse_tag_core(const struct tag *tag)
-{
-	if (tag->hdr.size > 2) {
-		if ((tag->u.core.flags & 1) == 0)
-			root_mountflags &= ~MS_RDONLY;
-		ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
-	}
-	return 0;
-}
-
-__tagtable(ATAG_CORE, parse_tag_core);
-
-static int __init parse_tag_mem32(const struct tag *tag)
-{
-	return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
-}
-
-__tagtable(ATAG_MEM, parse_tag_mem32);
-
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
 struct screen_info screen_info = {
  .orig_video_lines	= 30,
@@ -681,117 +628,8 @@ struct screen_info screen_info = {
  .orig_video_isVGA	= 1,
  .orig_video_points	= 8
 };
-
-static int __init parse_tag_videotext(const struct tag *tag)
-{
-	screen_info.orig_x            = tag->u.videotext.x;
-	screen_info.orig_y            = tag->u.videotext.y;
-	screen_info.orig_video_page   = tag->u.videotext.video_page;
-	screen_info.orig_video_mode   = tag->u.videotext.video_mode;
-	screen_info.orig_video_cols   = tag->u.videotext.video_cols;
-	screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
-	screen_info.orig_video_lines  = tag->u.videotext.video_lines;
-	screen_info.orig_video_isVGA  = tag->u.videotext.video_isvga;
-	screen_info.orig_video_points = tag->u.videotext.video_points;
-	return 0;
-}
-
-__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
 #endif
 
-static int __init parse_tag_ramdisk(const struct tag *tag)
-{
-	setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
-		      (tag->u.ramdisk.flags & 2) == 0,
-		      tag->u.ramdisk.start, tag->u.ramdisk.size);
-	return 0;
-}
-
-__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
-
-static int __init parse_tag_serialnr(const struct tag *tag)
-{
-	system_serial_low = tag->u.serialnr.low;
-	system_serial_high = tag->u.serialnr.high;
-	return 0;
-}
-
-__tagtable(ATAG_SERIAL, parse_tag_serialnr);
-
-static int __init parse_tag_revision(const struct tag *tag)
-{
-	system_rev = tag->u.revision.rev;
-	return 0;
-}
-
-__tagtable(ATAG_REVISION, parse_tag_revision);
-
-static int __init parse_tag_cmdline(const struct tag *tag)
-{
-#if defined(CONFIG_CMDLINE_EXTEND)
-	strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
-	strlcat(default_command_line, tag->u.cmdline.cmdline,
-		COMMAND_LINE_SIZE);
-#elif defined(CONFIG_CMDLINE_FORCE)
-	pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
-#else
-	strlcpy(default_command_line, tag->u.cmdline.cmdline,
-		COMMAND_LINE_SIZE);
-#endif
-	return 0;
-}
-
-__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
-
-/*
- * Scan the tag table for this tag, and call its parse function.
- * The tag table is built by the linker from all the __tagtable
- * declarations.
- */
-static int __init parse_tag(const struct tag *tag)
-{
-	extern struct tagtable __tagtable_begin, __tagtable_end;
-	struct tagtable *t;
-
-	for (t = &__tagtable_begin; t < &__tagtable_end; t++)
-		if (tag->hdr.tag == t->tag) {
-			t->parse(tag);
-			break;
-		}
-
-	return t < &__tagtable_end;
-}
-
-/*
- * Parse all tags in the list, checking both the global and architecture
- * specific tag tables.
- */
-static void __init parse_tags(const struct tag *t)
-{
-	for (; t->hdr.size; t = tag_next(t))
-		if (!parse_tag(t))
-			printk(KERN_WARNING
-				"Ignoring unrecognised tag 0x%08x\n",
-				t->hdr.tag);
-}
-
-/*
- * This holds our defaults.
- */
-static struct init_tags {
-	struct tag_header hdr1;
-	struct tag_core   core;
-	struct tag_header hdr2;
-	struct tag_mem32  mem;
-	struct tag_header hdr3;
-} init_tags __initdata = {
-	{ tag_size(tag_core), ATAG_CORE },
-	{ 1, PAGE_SIZE, 0xff },
-	{ tag_size(tag_mem32), ATAG_MEM },
-	{ MEM_SIZE },
-	{ 0, ATAG_NONE }
-};
-
 static int __init customize_machine(void)
 {
 	/* customizes platform devices, or adds new ones */
@@ -858,78 +696,6 @@ static void __init reserve_crashkernel(void)
 static inline void reserve_crashkernel(void) {}
 #endif /* CONFIG_KEXEC */
 
-static void __init squash_mem_tags(struct tag *tag)
-{
-	for (; tag->hdr.size; tag = tag_next(tag))
-		if (tag->hdr.tag == ATAG_MEM)
-			tag->hdr.tag = ATAG_NONE;
-}
-
-static struct machine_desc * __init setup_machine_tags(unsigned int nr)
-{
-	struct tag *tags = (struct tag *)&init_tags;
-	struct machine_desc *mdesc = NULL, *p;
-	char *from = default_command_line;
-
-	init_tags.mem.start = PHYS_OFFSET;
-
-	/*
-	 * locate machine in the list of supported machines.
-	 */
-	for_each_machine_desc(p)
-		if (nr == p->nr) {
-			printk("Machine: %s\n", p->name);
-			mdesc = p;
-			break;
-		}
-
-	if (!mdesc) {
-		early_print("\nError: unrecognized/unsupported machine ID"
-			" (r1 = 0x%08x).\n\n", nr);
-		dump_machine_table(); /* does not return */
-	}
-
-	if (__atags_pointer)
-		tags = phys_to_virt(__atags_pointer);
-	else if (mdesc->atag_offset)
-		tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
-
-#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
-	/*
-	 * If we have the old style parameters, convert them to
-	 * a tag list.
-	 */
-	if (tags->hdr.tag != ATAG_CORE)
-		convert_to_tag_list(tags);
-#endif
-
-	if (tags->hdr.tag != ATAG_CORE) {
-#if defined(CONFIG_OF)
-		/*
-		 * If CONFIG_OF is set, then assume this is a reasonably
-		 * modern system that should pass boot parameters
-		 */
-		early_print("Warning: Neither atags nor dtb found\n");
-#endif
-		tags = (struct tag *)&init_tags;
-	}
-
-	if (mdesc->fixup)
-		mdesc->fixup(tags, &from, &meminfo);
-
-	if (tags->hdr.tag == ATAG_CORE) {
-		if (meminfo.nr_banks != 0)
-			squash_mem_tags(tags);
-		save_atags(tags);
-		parse_tags(tags);
-	}
-
-	/* parse_early_param needs a boot_command_line */
-	strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-
-	return mdesc;
-}
-
 static int __init meminfo_cmp(const void *_a, const void *_b)
 {
 	const struct membank *a = _a, *b = _b;
@@ -944,7 +710,7 @@ void __init setup_arch(char **cmdline_p)
 	setup_processor();
 	mdesc = setup_machine_fdt(__atags_pointer);
 	if (!mdesc)
-		mdesc = setup_machine_tags(machine_arch_type);
+		mdesc = setup_machine_tags(__atags_pointer, machine_arch_type);
 	machine_desc = mdesc;
 	machine_name = mdesc->name;
 
-- 
1.7.12.84.gefa6462



From nicolas.pitre at linaro.org  Thu Aug 30 17:10:08 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 30 Aug 2012 17:10:08 -0400
Subject: [PATCH 2/2] ARM: allow for ATAGS to be configured out when DT support
 is selected
In-Reply-To: <1346361008-7320-1-git-send-email-nicolas.pitre@linaro.org>
References: <1346361008-7320-1-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <1346361008-7320-2-git-send-email-nicolas.pitre@linaro.org>

Now that ATAGS support is well contained, we can easily remove it from
the kernel build if so desired.  It has to explicitly be disabled, and
only when DT support is selected.

Note: disabling kernel ATAGS support does not prevent the usage of
CONFIG_ARM_ATAG_DTB_COMPAT.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/Kconfig         | 26 +++++++++++++++++++-------
 arch/arm/kernel/Makefile |  5 +++--
 arch/arm/kernel/atags.h  | 11 +++++++++++
 3 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5dbd..5c7302e208 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1891,12 +1891,6 @@ config CC_STACKPROTECTOR
 	  neutralized via a kernel panic.
 	  This feature requires gcc version 4.2 or above.
 
-config DEPRECATED_PARAM_STRUCT
-	bool "Provide old way to pass kernel parameters"
-	help
-	  This was deprecated in 2001 and announced to live on for 5 years.
-	  Some old boot loaders still use this way.
-
 endmenu
 
 menu "Boot options"
@@ -1909,6 +1903,23 @@ config USE_OF
 	help
 	  Include support for flattened device tree machine descriptions.
 
+config ATAGS
+	bool "Support for the traditional ATAGS boot data passing" if USE_OF
+	default y
+	help
+	  This is the traditional way of passing data to the kernel at boot
+	  time. If you are solely relying on the flattened device tree (or
+	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
+	  to remove ATAGS support from your kernel binary.  If unsure,
+	  leave this to y.
+
+config DEPRECATED_PARAM_STRUCT
+	bool "Provide old way to pass kernel parameters"
+	depends on ATAGS
+	help
+	  This was deprecated in 2001 and announced to live on for 5 years.
+	  Some old boot loaders still use this way.
+
 # Compressed boot loader in ROM.  Yes, we really want to ask about
 # TEXT and BSS so we preserve their values in the config files.
 config ZBOOT_ROM_TEXT
@@ -2035,6 +2046,7 @@ config CMDLINE
 choice
 	prompt "Kernel command line type" if CMDLINE != ""
 	default CMDLINE_FROM_BOOTLOADER
+	depends on ATAGS
 
 config CMDLINE_FROM_BOOTLOADER
 	bool "Use bootloader kernel arguments if available"
@@ -2104,7 +2116,7 @@ config KEXEC
 
 config ATAGS_PROC
 	bool "Export atags in procfs"
-	depends on KEXEC
+	depends on ATAGS && KEXEC
 	default y
 	help
 	  Should the atags used to boot the kernel be exported in an "atags"
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 086c9d3bc3..79e346a5d7 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,10 +15,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y		:= atags_parse.o elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 		   process.o ptrace.o return_address.o sched_clock.o \
 		   setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
+obj-$(CONFIG_ATAGS)		+= atags_parse.o
+obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
 obj-$(CONFIG_LEDS)		+= leds.o
@@ -52,7 +54,6 @@ test-kprobes-objs		+= kprobes-test-thumb.o
 else
 test-kprobes-objs		+= kprobes-test-arm.o
 endif
-obj-$(CONFIG_ATAGS_PROC)	+= atags_proc.o
 obj-$(CONFIG_OABI_COMPAT)	+= sys_oabi-compat.o
 obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
index a888fdd381..9edc969233 100644
--- a/arch/arm/kernel/atags.h
+++ b/arch/arm/kernel/atags.h
@@ -5,4 +5,15 @@ static inline void save_atags(struct tag *tags) { }
 #endif
 
 void convert_to_tag_list(struct tag *tags);
+
+#ifdef CONFIG_ATAGS
 struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr);
+#else
+static inline struct machine_desc *
+setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr)
+{
+	early_print("no ATAGS support: can't continue\n");
+	while (true);
+	unreachable();
+}
+#endif
-- 
1.7.12.84.gefa6462



From vkoul at infradead.org  Thu Aug 30 18:14:00 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 03:44:00 +0530
Subject: [PATCH v4 0/2] dmaengine: add support mmp-pdma
In-Reply-To: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
References: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
Message-ID: <1346364840.15463.1.camel@vkoul-mobl4>

On Thu, 2012-08-16 at 10:23 +0800, Zhangfei Gao wrote:

What tree is this based on? I do not find
Documentation/devicetree/bindings/dma/mmp-dma.txt in my tree or linus's
tree??

-- 
~Vinod Koul
Intel Corp.



From linus.walleij at linaro.org  Thu Aug 30 18:17:39 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 15:17:39 -0700
Subject: [PATCH 02/10] gpio: pxa: add explicit includes for cpu_is_X macros
In-Reply-To: <1346279496-26286-3-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-3-git-send-email-robherring2@gmail.com>
Message-ID: <CACRpkdasWv8toA1eBzpYo4QactNhkpzhuBk-D8kJbbM03WZN2Q@mail.gmail.com>

On Wed, Aug 29, 2012 at 3:31 PM, Rob Herring <robherring2 at gmail.com> wrote:

> From: Rob Herring <rob.herring at calxeda.com>
>
> In preparation to remove implicit inclusion of mach/gpio.h, add the
> necessary includes for cpu_is_X macros.

The commit message talks about gpio.h, but...

>  #include <mach/irqs.h>
> +#include <mach/hardware.h>
> +#ifdef CONFIG_ARCH_MMP
> +#include <mach/cputype.h>
> +#endif

This seems completely unrelated, but correct in the sense that every driver
should include its resources.

But isn't the proper fix to move arch/arm/mach-pxa/include/mach/cputype.h to
include/linux/*/pxa-cputype.h or something (note: no clue what "*" should be!),
or even better, modify this one driver to take a flag from platform data and/or
DT?

Anyway, we need the PXA maintainers to look at this.

Yours,
Linus Walleij


From grinberg at compulab.co.il  Thu Aug 30 18:26:51 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 31 Aug 2012 01:26:51 +0300
Subject: [PATCH] ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
In-Reply-To: <20120830202057.GY1303@atomide.com>
References: <1346106374-3283-1-git-send-email-grinberg@compulab.co.il>
 <CAMQu2gxZBq0wMw4rgbFpDT2pmA83ULKAJ-Mwv+VKvQQZMRQ4Dw@mail.gmail.com>
 <503E9129.9060408@compulab.co.il> <20120830202057.GY1303@atomide.com>
Message-ID: <503FE8AB.9010801@compulab.co.il>

On 08/30/12 23:20, Tony Lindgren wrote:
> * Igor Grinberg <grinberg at compulab.co.il> [120829 15:02]:
>> On 08/28/12 01:43, Shilimkar, Santosh wrote:
>>> On Mon, Aug 27, 2012 at 3:26 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>>>> Currently, omap2_sync32k_clocksource_init() function initializes the 32K
>>>> timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
>>>> setting.
>>>> Fix this by providing a default implementation for
>>>> !CONFIG_OMAP_32K_TIMER case.
>>>>
>>>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>>>> Reviewed-by: Paul Walmsley <paul at pwsan.com>
>>>> ---
>>> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>
>> Thanks Santosh!
>>
>> Tony, apparently, this bug has been there for a while,
>> so probably I should have added:
>> Cc: stable at vger.kernel.org
> 
> Thanks I'll apply this into fixes with Cc: stable. Note that
> Cc: stable is usually added at commit time, or at least you're
> not supposed to send the patch for review there.

Yeah yeah, I know, I just forgot to add it while committing.

Thanks!

-- 
Regards,
Igor.


From dmitry.torokhov at gmail.com  Thu Aug 30 19:02:21 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 30 Aug 2012 16:02:21 -0700
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120830131202.GG14145@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
 <20120821164244.GA4672@core.coreip.homeip.net>
 <20120830131202.GG14145@gmail.com>
Message-ID: <20120830230221.GD21501@core.coreip.homeip.net>

On Thu, Aug 30, 2012 at 02:12:04PM +0100, Lee Jones wrote:
> > Sorry for the delay. Yes, this shoudl be fine, but since it is
> > essentially a revert of the original patch it should be pushed in as
> > such.
> 
> How's this?
> 

Excellent.

> Author: Lee Jones <lee.jones at linaro.org>
> Date:   Thu Aug 30 14:08:19 2012 +0100
> 
>     Revert "input: ab8500-ponkey: Create AB8500 domain IRQ mapping"
>     
>     This reverts commit ca3b3faf9bee4dc5df4f10eae2d1e48f7de0a8ad.
>     
>     There was a plan to place ab8500_irq_get_virq() calls in each AB8500
>     child device prior to requesting an IRQ, but as we're no longer using
>     Device Tree to collect our IRQ numbers, it's actually better to allow
>     the core to do this during device registration time. So the IRQ number
>     we pull from its resource has already been converted to a virtual IRQ.
>     
>     CC: Dmitry Torokhov <dmitry.torokhov at gmail.com>
>     CC: linux-input at vger.kernel.org
>     Acked-by: Linus Walleij <linus.walleij at linaro.org>

Acked-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>

>     Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> diff --git a/drivers/input/misc/ab8500-ponkey.c b/drivers/input/misc/ab8500-ponkey.c
> index f06231b..84ec691 100644
> --- a/drivers/input/misc/ab8500-ponkey.c
> +++ b/drivers/input/misc/ab8500-ponkey.c
> @@ -74,8 +74,8 @@ static int __devinit ab8500_ponkey_probe(struct platform_device *pdev)
>  
>         ponkey->idev = input;
>         ponkey->ab8500 = ab8500;
> -       ponkey->irq_dbf = ab8500_irq_get_virq(ab8500, irq_dbf);
> -       ponkey->irq_dbr = ab8500_irq_get_virq(ab8500, irq_dbr);
> +       ponkey->irq_dbf = irq_dbf;
> +       ponkey->irq_dbr = irq_dbr;
>  
>         input->name = "AB8500 POn(PowerOn) Key";
>         input->dev.parent = &pdev->dev;

-- 
Dmitry


From dmitry.torokhov at gmail.com  Thu Aug 30 19:03:23 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 30 Aug 2012 16:03:23 -0700
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120830230221.GD21501@core.coreip.homeip.net>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
 <20120821164244.GA4672@core.coreip.homeip.net>
 <20120830131202.GG14145@gmail.com>
 <20120830230221.GD21501@core.coreip.homeip.net>
Message-ID: <20120830230323.GE21501@core.coreip.homeip.net>

On Thu, Aug 30, 2012 at 04:02:21PM -0700, Dmitry Torokhov wrote:
> On Thu, Aug 30, 2012 at 02:12:04PM +0100, Lee Jones wrote:
> > > Sorry for the delay. Yes, this shoudl be fine, but since it is
> > > essentially a revert of the original patch it should be pushed in as
> > > such.
> > 
> > How's this?
> > 
> 
> Excellent.

I assume you will be merging it with the rest of AB8500 patches, right?

-- 
Dmitry


From sboyd at codeaurora.org  Thu Aug 30 19:28:08 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 30 Aug 2012 16:28:08 -0700
Subject: [PATCH v3 1/2] ARM: arch_timers: enable the use of the virtual
 timer
In-Reply-To: <1345819976-6339-2-git-send-email-marc.zyngier@arm.com>
References: <1345819976-6339-1-git-send-email-marc.zyngier@arm.com>
 <1345819976-6339-2-git-send-email-marc.zyngier@arm.com>
Message-ID: <503FF708.10603@codeaurora.org>

On 8/24/2012 7:52 AM, Marc Zyngier wrote:
> At the moment, the arch_timer driver only uses the physical timer,
> which can cause problem if PL2 hasn't enabled PL1 access in CNTHCTL,
> which is likely in a virtualized environment. Instead, the virtual
> timer is always available.
>
> This patch enables the use of the virtual timer, unless no
> interrupt is provided in the DT for it, in which case it falls
> back to the physical timer.

Is this a good candidate for static keys? It looks like we make the
decision fairly early and then we're done and have a bunch of if
statements. Maybe its premature optimization though...

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From linus.walleij at linaro.org  Thu Aug 30 19:30:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 16:30:55 -0700
Subject: [PATCH 5/6] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <20120820080210.GF7439@game.jcrosoft.org>
References: <1345119373-22774-1-git-send-email-linus.walleij@linaro.org>
 <20120816124002.GB7439@game.jcrosoft.org>
 <CACRpkdZDMxk30YTkrumRveR3OuWptSpzNevrAvC2FxYShOZp-A@mail.gmail.com>
 <20120820080210.GF7439@game.jcrosoft.org>
Message-ID: <CACRpkdYkfgY-dYD1L3_HkhFJL49d9GaSWd8ax2Rqm3BGFFHhdQ@mail.gmail.com>

On Mon, Aug 20, 2012 at 1:02 AM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> On 00:42 Sun 19 Aug     , Linus Walleij wrote:

> no I mean why
>> >> +     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
>> >> +             "rtc", NULL),
>> >> +     OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
>> >> +             "kmi0", NULL),
>> >> +     OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
>> >> +             "kmi1", NULL),
>
> no platform data why do you use the AUXDATA?
>
> as the OF_DEV_AUXDATA is deprecated now

OK this is to get the right bus names of the devices.

As I support boot from both device tree and without device tree, I cannot
change all the names that e.g. the clock framework is tied to.

Once we switch to pure device tree this can be changed at the user
sites and all auxdata be removed.

Yours,
Linus Walleij


From swarren at wwwdotorg.org  Thu Aug 30 19:40:25 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 30 Aug 2012 16:40:25 -0700
Subject: [PATCH] clk: Make the generic clock API available by default
In-Reply-To: <20120830171918.GE4356@opensource.wolfsonmicro.com>
References: <1346186104-4083-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <503E8E6E.1010101@wwwdotorg.org>
 <20120830171918.GE4356@opensource.wolfsonmicro.com>
Message-ID: <503FF9E9.4020701@wwwdotorg.org>

On 08/30/12 10:19, Mark Brown wrote:
> On Wed, Aug 29, 2012 at 02:49:34PM -0700, Stephen Warren wrote:
>> On 08/28/12 13:35, Mark Brown wrote:
>
>>> @@ -674,6 +676,7 @@ config ARCH_TEGRA
>>>   	select GENERIC_CLOCKEVENTS
>>>   	select GENERIC_GPIO
>>>   	select HAVE_CLK
>>> +	select HAVE_CUSTOM_CLK
>
>> For 3.7, Tegra will switch to the common clock framework. I think
>> this patch would then disable that. How should we resolve this -
>> rebase the Tegra common-clk tree on top of any branch containing
>> this patch in order to remove that select statement?
>
> I'd expect this to be applied on a separate branch so you should be able
> to rebase your conversion on top of it or merge it into your branch
> which should deal with things well enough I think?

That should work.



From linus.walleij at linaro.org  Thu Aug 30 19:46:17 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 16:46:17 -0700
Subject: [PATCH 01/17] ASoC: Ux500: Move MSP pinctrl setup into the MSP
 driver
In-Reply-To: <1345816913-4113-2-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdai+RObHsq7xe0+Fk24K7r-Wzoc8o3RbvHT78=EeHkjSQ@mail.gmail.com>

On Fri, Aug 24, 2012 at 7:01 AM, Lee Jones <lee.jones at linaro.org> wrote:

> In the initial submission of the MSP driver msp1 and msp3's associated
> pinctrl mechanism was passed back to platform code using a plat_init()
> call-back routine, but it has no place in platform code. The MSP driver
> should set this up for the appropriate ports. Instead we use a use_pinctrl
> identifier which is passed from platform_data/Device Tree which indicates
> which ports should use pinctrl.
>
> CC: alsa-devel at alsa-project.org
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Looks good to me, so Acked-by: Linus Walleij <linus.walleij at linaro.org>
for the ux500 mach part.

However I'd request Ola/Roger to ACK it too on the ALSA side.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu Aug 30 19:50:38 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 16:50:38 -0700
Subject: [PATCH 09/17] ARM: ux500: Add AB8500 CODEC node to DB8500 Device
 Tree
In-Reply-To: <1345816913-4113-10-git-send-email-lee.jones@linaro.org>
References: <1345816913-4113-1-git-send-email-lee.jones@linaro.org>
 <1345816913-4113-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdY057+e=Hc2r-EkTP4pneNfPKWVaz80DjaUcG-gGyJRxg@mail.gmail.com>

On Fri, Aug 24, 2012 at 7:01 AM, Lee Jones <lee.jones at linaro.org> wrote:

> Ensure correct probing and pass though important configuration
> options to the AB8500 CODEC driver when DT is enabled
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From sboyd at codeaurora.org  Thu Aug 30 19:51:13 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 30 Aug 2012 16:51:13 -0700
Subject: [PATCH v2 1/2] ARM: delay: set loops_per_jiffy when moving to
 timer-based loop
In-Reply-To: <1346275524-13817-1-git-send-email-will.deacon@arm.com>
References: <1346275524-13817-1-git-send-email-will.deacon@arm.com>
Message-ID: <503FFC71.1070506@codeaurora.org>

On 8/29/2012 2:25 PM, Will Deacon wrote:
> The delay functions may be called by some platforms between switching to
> the timer-based delay loop but before calibration. In this case, the
> initial loops_per_jiffy may not be suitable for the timer (although a
> compromise may be achievable) and delay times may be considered too
> inaccurate.
>
> This patch updates loops_per_jiffy when switching to the timer-based
> delay loop so that delays are consistent prior to calibration.
>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From sboyd at codeaurora.org  Thu Aug 30 19:51:25 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 30 Aug 2012 16:51:25 -0700
Subject: [PATCH v2 2/2] ARM: delay: add registration mechanism for delay
 timer sources
In-Reply-To: <1346275524-13817-2-git-send-email-will.deacon@arm.com>
References: <1346275524-13817-1-git-send-email-will.deacon@arm.com>
 <1346275524-13817-2-git-send-email-will.deacon@arm.com>
Message-ID: <503FFC7D.9050704@codeaurora.org>

On 8/29/2012 2:25 PM, Will Deacon wrote:
> From: Jonathan Austin <Jonathan.Austin at arm.com>
>
> The current timer-based delay loop relies on the architected timer to
> initiate the switch away from the polling-based implementation. This is
> unfortunate for platforms without the architected timers but with a
> suitable delay source (that is, constant frequency, always powered-up
> and ticking as long as the CPUs are online).
>
> This patch introduces a registration mechanism for the delay timer
> (which provides an unconditional read_current_timer implementation) and
> updates the architected timer code to use the new interface.
>
> Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>

Reviewed-by: Stephen Boyd <sboyd at codeaurora.org>

> diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> index 62e7547..88401c2 100644
> --- a/arch/arm/include/asm/arch_timer.h
> +++ b/arch/arm/include/asm/arch_timer.h
> @@ -4,7 +4,6 @@
>  #include <asm/errno.h>
>  
>  #ifdef CONFIG_ARM_ARCH_TIMER
> -#define ARCH_HAS_READ_CURRENT_TIMER
>  int arch_timer_of_register(void);
>  int arch_timer_sched_clock_init(void);
>  #else
> diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
> index dc61451..50928e8 100644
> --- a/arch/arm/include/asm/delay.h
> +++ b/arch/arm/include/asm/delay.h
> @@ -15,6 +15,11 @@
>  
>  #ifndef __ASSEMBLY__
>  
> +struct delay_timer {
> +	unsigned long (*read_current_timer)(void);
> +	unsigned long freq;

I wonder if we should print a warning and not actually switch to the
timer based udelay if the frequency is not fast enough (< 1Mhz). Or
people just wouldn't do that?

> @@ -55,18 +62,24 @@ static void __timer_udelay(unsigned long usecs)
>  	__timer_const_udelay(usecs * UDELAY_MULT);
>  }
>  
> -void __init init_current_timer_delay(unsigned long freq)
> +void __init register_current_timer_delay(struct delay_timer *timer)

const?

>  {
> -	pr_info("Switching to timer-based delay loop\n");
> -	lpj_fine			= freq / HZ;
> -	loops_per_jiffy			= lpj_fine;
> -	arm_delay_ops.delay		= __timer_delay;
> -	arm_delay_ops.const_udelay	= __timer_const_udelay;
> -	arm_delay_ops.udelay		= __timer_udelay;
> +	if (!delay_calibrated) {
> +		pr_info("Switching to timer-based delay loop\n");
> +		delay_timer			= timer;
> +		lpj_fine			= timer->freq / HZ;
> +		loops_per_jiffy			= lpj_fine;
> +		arm_delay_ops.delay		= __timer_delay;
> +		arm_delay_ops.const_udelay	= __timer_const_udelay;
> +		arm_delay_ops.udelay		= __timer_udelay;
> +		delay_calibrated		= true;
> +	} else {
> +		pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");

warn?

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From linus.walleij at linaro.org  Thu Aug 30 19:56:03 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 30 Aug 2012 16:56:03 -0700
Subject: [PATCH 13/22] ARM: ux500: Fork MSP platform registration for
 step-by-step DT enablement
In-Reply-To: <20120828074812.GA12957@gmail.com>
References: <1344527268-5964-1-git-send-email-lee.jones@linaro.org>
 <1344527268-5964-14-git-send-email-lee.jones@linaro.org>
 <CACRpkdaem6t3mvy-_9e=GEgwWoeBQSoX3Hf1L=hjWsvLJdsVAQ@mail.gmail.com>
 <20120820080632.GD8450@gmail.com>
 <CACRpkdZRJ1yX-o8-NUuMzXMz5ebbp=H21Xa6JMy1y56Chq-T9g@mail.gmail.com>
 <20120828074812.GA12957@gmail.com>
Message-ID: <CACRpkdY0jwV7MOOGbFOcFhujMzanRyxx6TofA72ZwLi_D4HhHw@mail.gmail.com>

On Tue, Aug 28, 2012 at 12:48 AM, Lee Jones <lee.jones at linaro.org> wrote:
> On Mon, Aug 27, 2012 at 04:07:58PM -0700, Linus Walleij wrote:

>> If you're adding and then removing *all* of them in this set,
>> why add them in the first place?
>
> So that there's no breakage during bisection.
>
> You should be able to roll the kernel back in between each of these
> patches and there to be full compatibility at each point. At least
> that was the intention. Is that wrong?

No it's correct, the only way to do what I'm thinking on may be
to squash them all into one gigantic patch, which is not good either.

So go ahead with this scheme, it's the lesser of two evils.
Acked-by etc.

Yours,
Linus Walleij


From sboyd at codeaurora.org  Thu Aug 30 20:00:22 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 30 Aug 2012 17:00:22 -0700
Subject: [PATCHv2] ARM: msm: Implement read_current_timer for msm timers
Message-ID: <1346371222-7450-1-git-send-email-sboyd@codeaurora.org>

Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.

Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---

Changes since v1:
 * Updated for new function signature

 arch/arm/mach-msm/timer.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index ce6b008..6e3b91b 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -28,6 +28,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
+#include <asm/delay.h>
 
 #include "common.h"
 
@@ -173,6 +174,15 @@ static notrace u32 msm_sched_clock_read(void)
 	return msm_clocksource.read(&msm_clocksource);
 }
 
+static unsigned long msm_read_current_timer(void)
+{
+	return msm_clocksource.read(&msm_clocksource);
+}
+
+static struct delay_timer msm_delay_timer = {
+	.read_current_timer = msm_read_current_timer,
+};
+
 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
 				  bool percpu)
 {
@@ -217,6 +227,8 @@ err:
 	if (res)
 		pr_err("clocksource_register failed\n");
 	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
+	msm_delay_timer.freq = dgt_hz;
+	register_current_timer_delay(&msm_delay_timer);
 }
 
 #ifdef CONFIG_OF
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From horms at verge.net.au  Thu Aug 30 20:34:35 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:35 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7
Message-ID: <1346373285-19588-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following enhancements to the Marzen board
and r8a7779 SoC by Phil Edworthy, Morimoto-san and myself for 3.7.

* This pull request is based on the usb-next branch of Greg KH's USB tree,
  git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git,
  which is based on v3.6-rc3.

  This is to satisfy compile-time dependencies.
  Please let me know if you would like this handled a different way.

----------------------------------------------------------------
The following changes since commit a7bdf7fa33127bf08eb0810698bca607a9462df4:

  Merge v3.6-rc3 into usb-next (2012-08-27 07:15:30 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git marzen

for you to fetch changes up to 922bdac2247841fff1ace215b45eb165f6346a6f:

  ARM: shmobile: marzen: enable thermal sensor (2012-08-31 09:24:15 +0900)

----------------------------------------------------------------
Kuninori Morimoto (7):
      ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx
      ARM: shmobile: r8a7779: add USB common phy initializer
      ARM: shmobile: r8a7779: add USB EHCI clock support
      ARM: shmobile: r8a7779: add USB OHCI clock support
      ARM: shmobile: marzen: add USB EHCI driver support
      ARM: shmobile: marzen: fixup regulator id for smsc911x
      ARM: shmobile: marzen: enable thermal sensor

Phil Edworthy (2):
      r8a7779: add SDHI clock support
      marzen: add SDHI0 support

Simon Horman (1):
      ARM: mach-shmobile: marzen: defconfig update

 arch/arm/configs/marzen_defconfig             |  25 +++--
 arch/arm/mach-shmobile/Kconfig                |   1 +
 arch/arm/mach-shmobile/board-marzen.c         | 156 +++++++++++++++++++++++++-
 arch/arm/mach-shmobile/clock-r8a7779.c        |  18 ++-
 arch/arm/mach-shmobile/include/mach/common.h  |   1 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h |   2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c          |  16 +--
 arch/arm/mach-shmobile/setup-r8a7779.c        |  93 +++++++++++++++
 8 files changed, 294 insertions(+), 18 deletions(-)


From horms at verge.net.au  Thu Aug 30 20:34:38 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:38 +0900
Subject: [PATCH 03/10] ARM: mach-shmobile: marzen: defconfig update
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-4-git-send-email-horms@verge.net.au>

Update marzen defconfig
* Enable MMC Block device as SDHI hw is now supported.
* Default to NFS root, this is consistent with many other
  shmobile boards
* Enable UNIX which is required by udevd

Other changes are noise due to using make savedefconfig
to create the new defconfig.

Cc: Phil Edworthy <phil.edworthy at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index bf42ad2..cd2dc21 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -1,13 +1,14 @@
 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
 CONFIG_EXPERIMENTAL=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
@@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_NO_HZ=y
 CONFIG_SMP=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
 CONFIG_AEABI=y
@@ -29,13 +29,16 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -69,16 +72,16 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_SSB=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_REDUCED=y
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:36 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:36 +0900
Subject: [PATCH 01/10] r8a7779: add SDHI clock support
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-2-git-send-email-horms@verge.net.au>

From: Phil Edworthy <phil.edworthy at renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c..3cafb6a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = {
 				      0x0300, CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015, MSTP014,
 	MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
 };
 
 void __init r8a7779_clock_init(void)
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:39 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:39 +0900
Subject: [PATCH 04/10] ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-5-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

PENCx is Power Enable Control pin for USB.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c          | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b07ad31..7597a37 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
 	GPIO_FN_A19,
 
 	/* IPSR0 */
-	GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+	GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
 	GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
 	GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
 	GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index d14c9b0..9fac32e4 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
 	FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
 	FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
 	FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-	FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+	FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 	FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 
 	/* GPSR5 */
@@ -176,7 +176,7 @@ enum {
 	FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 	FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 	FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-	FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+	FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 	FN_SCIF_CLK, FN_TCLK0_C,
 
 	/* IPSR1 */
@@ -447,7 +447,7 @@ enum {
 	A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 	BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 	ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-	PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+	USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 	SCIF_CLK_MARK, TCLK0_C_MARK,
 
 	EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(A18_MARK, FN_A18),
 	PINMUX_DATA(A19_MARK, FN_A19),
 
-	PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+	PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 	PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
 	GPIO_FN(A19),
 
 	/* IPSR0 */
-	GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+	GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
 	GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
 	GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
 	GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		GP_4_30_FN, FN_IP8_18,
 		GP_4_29_FN, FN_IP8_17_16,
 		GP_4_28_FN, FN_IP0_2_0,
-		GP_4_27_FN, FN_PENC1,
-		GP_4_26_FN, FN_PENC0,
+		GP_4_27_FN, FN_USB_PENC1,
+		GP_4_26_FN, FN_USB_PENC0,
 		GP_4_25_FN, FN_IP8_15_12,
 		GP_4_24_FN, FN_IP8_11_8,
 		GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 		FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 		/* IP0_2_0 [3] */
-		FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+		FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 		FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
 	},
 	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:37 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:37 +0900
Subject: [PATCH 02/10] marzen: add SDHI0 support
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-3-git-send-email-horms@verge.net.au>

From: Phil Edworthy <phil.edworthy at renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  4 +--
 arch/arm/mach-shmobile/board-marzen.c | 52 ++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 864f9a5..bf42ad2 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -71,12 +71,12 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_SSB=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 3a528cf..dec3ffc 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,6 +30,8 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -39,6 +41,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
 	REGULATOR_SUPPLY("vddvario", "smsc911x"),
@@ -75,13 +83,45 @@ static struct platform_device eth_device = {
 	.num_resources	= ARRAY_SIZE(smsc911x_resources),
 };
 
+static struct resource sdhi0_resources[] = {
+	[0] = {
+		.name	= "sdhi0",
+		.start	= 0xffe4c000,
+		.end	= 0xffe4c0ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(104),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct sh_mobile_sdhi_info sdhi0_platform_data = {
+	.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
+	.tmio_caps = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct platform_device sdhi0_device = {
+	.name = "sh_mobile_sdhi",
+	.num_resources = ARRAY_SIZE(sdhi0_resources),
+	.resource = sdhi0_resources,
+	.id = 0,
+	.dev = {
+		.platform_data = &sdhi0_platform_data,
+	}
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
+	&sdhi0_device,
 };
 
 static void __init marzen_init(void)
 {
-	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+				ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+	regulator_register_fixed(0, dummy_supplies,
+				ARRAY_SIZE(dummy_supplies));
 
 	r8a7779_pinmux_init();
 
@@ -97,6 +137,16 @@ static void __init marzen_init(void)
 	gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
 	gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
 
+	/* SD0 (CN20) */
+	gpio_request(GPIO_FN_SD0_CLK, NULL);
+	gpio_request(GPIO_FN_SD0_CMD, NULL);
+	gpio_request(GPIO_FN_SD0_DAT0, NULL);
+	gpio_request(GPIO_FN_SD0_DAT1, NULL);
+	gpio_request(GPIO_FN_SD0_DAT2, NULL);
+	gpio_request(GPIO_FN_SD0_DAT3, NULL);
+	gpio_request(GPIO_FN_SD0_CD, NULL);
+	gpio_request(GPIO_FN_SD0_WP, NULL);
+
 	r8a7779_add_standard_devices();
 	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:42 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:42 +0900
Subject: [PATCH 07/10] ARM: shmobile: r8a7779: add USB OHCI clock support
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-8-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

ohci-platform driver require these clocks

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1d8842b..7c62e3d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -158,7 +158,9 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
 	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+	CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
 	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+	CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:41 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:41 +0900
Subject: [PATCH 06/10] ARM: shmobile: r8a7779: add USB EHCI clock support
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-7-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

ehci-platform driver require these clocks

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 3cafb6a..1d8842b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
+	MSTP101, MSTP100,
 	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015, MSTP014,
 	MSTP_NR };
@@ -96,6 +97,8 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+	[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
+	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -154,6 +157,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:44 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:44 +0900
Subject: [PATCH 09/10] ARM: shmobile: marzen: fixup regulator id for smsc911x
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-10-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

regulator id = 0 is used for sh_mobile_sdhi.
smsc911x's regulator can use id = 1

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 0249c0e..91e81e9 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -196,7 +196,7 @@ static void __init marzen_init(void)
 {
 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 				ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-	regulator_register_fixed(0, dummy_supplies,
+	regulator_register_fixed(1, dummy_supplies,
 				ARRAY_SIZE(dummy_supplies));
 
 	r8a7779_pinmux_init();
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:45 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:45 +0900
Subject: [PATCH 10/10] ARM: shmobile: marzen: enable thermal sensor
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-11-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Marzen board can measure its thermal by this patch.
	cat /sys/class/thermal/thermal_zoneX/temp

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  2 ++
 arch/arm/mach-shmobile/board-marzen.c | 16 ++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 61d1c55..c30ea5e 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -73,6 +73,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 91e81e9..eb0a05a 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -113,9 +113,25 @@ static struct platform_device sdhi0_device = {
 	}
 };
 
+/* Thermal */
+static struct resource thermal_resources[] = {
+	[0] = {
+		.start		= 0xFFC48000,
+		.end		= 0xFFC48038 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device thermal_device = {
+	.name		= "rcar_thermal",
+	.resource	= thermal_resources,
+	.num_resources	= ARRAY_SIZE(thermal_resources),
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
 	&sdhi0_device,
+	&thermal_device,
 };
 
 /* USB */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:43 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:43 +0900
Subject: [PATCH 08/10] ARM: shmobile: marzen: add USB EHCI driver support
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-9-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch supports CN21/CN22 USB 2.0 (port 0/1/2),
and enable USB momery on defconfig

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  6 +++
 arch/arm/mach-shmobile/Kconfig        |  1 +
 arch/arm/mach-shmobile/board-marzen.c | 88 +++++++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index cd2dc21..61d1c55 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -75,6 +77,10 @@ CONFIG_SSB=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4cacc2d..8937d69 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,7 @@ config ARCH_R8A7779
 	select SH_CLK_CPG
 	select ARM_GIC
 	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select USB_ARCH_HAS_EHCI
 
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index dec3ffc..0249c0e 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -32,6 +32,8 @@
 #include <linux/smsc911x.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -116,6 +118,80 @@ static struct platform_device *marzen_devices[] __initdata = {
 	&sdhi0_device,
 };
 
+/* USB */
+static int xhci_power_on(struct platform_device *pdev)
+{
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_get_sync(&pdev->dev);
+
+	return 0;
+}
+
+static void xhci_power_off(struct platform_device *pdev)
+{
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static struct usb_ehci_pdata ehcix_pdata = {
+	.power_on	= xhci_power_on,
+	.power_off	= xhci_power_off,
+	.power_suspend	= xhci_power_off,
+};
+
+static struct resource ehci0_resources[] = {
+	[0] = {
+		.start	= 0xffe70000,
+		.end	= 0xffe70400 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(44),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ehci0_device = {
+	.name	= "ehci-platform",
+	.id	= 0,
+	.dev	= {
+		.dma_mask		= &ehci0_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ehcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ehci0_resources),
+	.resource	= ehci0_resources,
+};
+
+static struct resource ehci1_resources[] = {
+	[0] = {
+		.start	= 0xfff70000,
+		.end	= 0xfff70400 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(45),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ehci1_device = {
+	.name	= "ehci-platform",
+	.id	= 1,
+	.dev	= {
+		.dma_mask		= &ehci1_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ehcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ehci1_resources),
+	.resource	= ehci1_resources,
+};
+
+static struct platform_device *marzen_usb_devices[] __initdata = {
+	&ehci0_device,
+	&ehci1_device,
+};
+
 static void __init marzen_init(void)
 {
 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -147,8 +223,20 @@ static void __init marzen_init(void)
 	gpio_request(GPIO_FN_SD0_CD, NULL);
 	gpio_request(GPIO_FN_SD0_WP, NULL);
 
+	/* USB (CN21) */
+	gpio_request(GPIO_FN_USB_OVC0, NULL);
+	gpio_request(GPIO_FN_USB_OVC1, NULL);
+	gpio_request(GPIO_FN_USB_OVC2, NULL);
+
+	/* USB (CN22) */
+	gpio_request(GPIO_FN_USB_PENC2, NULL);
+
 	r8a7779_add_standard_devices();
 	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
+
+	if (0 == r8a7779_usb_phy_init(0))
+		platform_add_devices(marzen_usb_devices,
+				     ARRAY_SIZE(marzen_usb_devices));
 }
 
 MACHINE_START(MARZEN, "marzen")
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:34:40 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:34:40 +0900
Subject: [PATCH 05/10] ARM: shmobile: r8a7779: add USB common phy initializer
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <1346373285-19588-6-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch adds common USB phy ports initializer for r8a7779.

The note is that each USB IP have own MSTP clock bit,
and common USB phy port doesn't have MSTP clock,
but this USB phy needs USB clock.
Each USB driver / platform should keep USB MSTP clock somehow.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/common.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c       | 93 ++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)

diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 45e61da..00b2eb5 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -78,6 +78,7 @@ extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7740_meram_workaround(void);
+extern int r8a7779_usb_phy_init(u32 usbpctrl0);
 
 extern unsigned int r8a7779_get_core_count(void);
 extern int r8a7779_platform_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index e98e46f..17fdd1f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
+#include <linux/pm_runtime.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
@@ -243,6 +244,98 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
 static struct platform_device *r8a7779_late_devices[] __initdata = {
 };
 
+/* USBH common register */
+#define USBPCTRL0	0x0800
+#define USBPCTRL1	0x0804
+#define USBST		0x0808
+#define USBEH0		0x080C
+#define USBOH0		0x081C
+#define USBCTL0		0x0858
+#define EIIBC1		0x0094
+#define EIIBC2		0x009C
+
+#ifdef CONFIG_ARCH_SUPPORTS_BIG_ENDIAN
+# define xHCI_ENDIAN "BIG"
+# define xHCI_NO_SWAP 0x00000003
+#else
+# define xHCI_ENDIAN "LITTLE"
+# define xHCI_NO_SWAP 0x00000000
+#endif
+
+/*
+ * USB initial/install operation.
+ *
+ * This function setup USB phy.
+ * The used value and setting order came from
+ * [USB :: Initial setting] on datasheet.
+ */
+int __init r8a7779_usb_phy_init(u32 usbpctrl0)
+{
+	void __iomem *reg0, *reg1;
+	int i;
+	u32 val;
+
+	reg0 = ioremap_nocache(0xffe70000, 0x900);
+	reg1 = ioremap_nocache(0xfff70000, 0x900);
+
+	/*----------------------------------------*
+	 * USB phy start-up
+	 *----------------------------------------*/
+
+	/* (1) USB-PHY standby release */
+	iowrite32(0x00000001, (reg0 + USBPCTRL1));
+
+	/* (2) start USB-PHY internal PLL */
+	iowrite32(0x00000003, (reg0 + USBPCTRL1));
+
+	/* (3) USB module status check */
+	for (i = 0; i < 1024; i++) {
+		udelay(10);
+		val = ioread32(reg0 + USBST);
+		if (0xc0000000 == val)
+			goto usb_module_is_working;
+	}
+	pr_err("USB module not ready\n");
+	return -EIO;
+
+usb_module_is_working:
+	/* (4) USB-PHY reset clear */
+	iowrite32(0x00000007, (reg0 + USBPCTRL1));
+
+	/* set platform specific port settings */
+	iowrite32(usbpctrl0, (reg0 + USBPCTRL0));
+
+	/*----------------------------------------*
+	 * EHCI IP Internal Buffer Setting
+	 *----------------------------------------*/
+
+	/* (1) EHCI IP internal buffer setting */
+	iowrite32(0x00ff0040, (reg0 + EIIBC1));
+	iowrite32(0x00ff0040, (reg1 + EIIBC1));
+
+	/* (2) EHCI IP internal buffer enable */
+	iowrite32(0x00000001, (reg0 + EIIBC2));
+	iowrite32(0x00000001, (reg1 + EIIBC2));
+
+	/*----------------------------------------*
+	 * Bus alignment settings
+	 *----------------------------------------*/
+
+	/* (1) EHCI bus alignment */
+	iowrite32(xHCI_NO_SWAP, (reg0 + USBEH0));
+
+	/* (1) OHCI bus alignment */
+	iowrite32(xHCI_NO_SWAP, (reg0 + USBOH0));
+
+	pr_info("USB xHCI alignment was initialized as %s endian no swap\n",
+		xHCI_ENDIAN);
+
+	iounmap(reg0);
+	iounmap(reg1);
+
+	return 0;
+}
+
 void __init r8a7779_add_standard_devices(void)
 {
 #ifdef CONFIG_CACHE_L2X0
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 20:41:08 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 09:41:08 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7
In-Reply-To: <1346373285-19588-1-git-send-email-horms@verge.net.au>
References: <1346373285-19588-1-git-send-email-horms@verge.net.au>
Message-ID: <20120831004108.GA22207@verge.net.au>

On Fri, Aug 31, 2012 at 09:34:35AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
> 
> please consider the following enhancements to the Marzen board
> and r8a7779 SoC by Phil Edworthy, Morimoto-san and myself for 3.7.

Sorry, it seems that I missed one patch. I will repost shortly.


From vkoul at infradead.org  Thu Aug 30 20:52:10 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 06:22:10 +0530
Subject: [PATCH 0/2] ARM: EXYNOS: Set the capability of pdm0 and pdm1 as
 DMA_PRIVATE
In-Reply-To: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
References: <1346215585-31023-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1346374330.15463.5.camel@vkoul-mobl4>

On Wed, 2012-08-29 at 10:16 +0530, Tushar Behera wrote:
> DMA clients pdma0 and pdma1 are internal to the SoC and are used only
> by dedicated peripherals. Since they cannot be used for generic
> purpose, their capability should be set as DMA_PRIVATE.
> 
> The patches are rebased on top of v3.6-rc3.
Kukjin, if you ack them I can take thru my tree, other way round is fine
with me too.
> 
> Tushar Behera (2):
>   ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
>   DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE
> 
>  arch/arm/mach-exynos/dma.c |    2 ++
>  drivers/dma/pl330.c        |    1 +
>  2 files changed, 3 insertions(+), 0 deletions(-)
> 

-- 
~Vinod Koul
Intel Corp.



From vkoul at infradead.org  Thu Aug 30 20:55:54 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 06:25:54 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <20120830144307.GA26737@beef>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
 <503F75C0.1050507@ti.com> <20120830144307.GA26737@beef>
Message-ID: <1346374554.15463.6.camel@vkoul-mobl4>

On Thu, 2012-08-30 at 10:43 -0400, Matt Porter wrote:
> On Thu, Aug 30, 2012 at 07:46:32PM +0530, Sekhar Nori wrote:
> > Hi Matt,
> > 
> > On 8/23/2012 6:39 AM, Matt Porter wrote:
> > > Removes use of the DaVinci EDMA private DMA API and replaces
> > > it with use of the DMA engine API.
> > > 
> > > Signed-off-by: Matt Porter <mporter at ti.com>
> > 
> > I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
> > initialize after applying the patch.
> > 
> > root at arago:~# dmesg | grep -i spi                                               
> > spi_davinci spi_davinci.1: request RX DMA channel failed                        
> 
> Hi Sekhar,
> 
> Most likely CONFIG_TI_EDMA is off as it defaults to off in the v3
> series. Try enabling this and if it's the problem then this error
> path can be fixed to properly fallback to PIO only or fail to
> initialize as needed.
I didnt see any update on this one, is it okay, if so care to send a
tested-by?

-- 
~Vinod Koul
Intel Corp.



From tony at atomide.com  Thu Aug 30 20:52:19 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:19 -0700
Subject: [PATCH 0/9] Clean up hardcoded IRQs for mach-omap2,
 enable SPARSE_IRQ, plaform_data/gpio-omap.h
Message-ID: <20120831004828.28732.902.stgit@muffinssi.local>

Hi all,

Here's the first set of omap header clean-up patches needed for single
zImage support. This series is based v3.6-rc3 and the following patches
to avoid merge conflicts with the includes:

- Arnd's patch "ARM: omap: move platform_data definitions"
- Igor's series "ARM: OMAP: cleanup plat/board.h file"
- Afzal's series "Prepare for GPMC driver conversion (w.r.t MTD)"

Regards,

Tony

---

Tony Lindgren (9):
      ARM: OMAP1: Move define of OMAP_LCD_DMA to dma.h
      ARM: OMAP1: Define OMAP1_INT_I2C locally
      ARM: OMAP2+: Make INTCPS_NR_IRQS local for mach-omap2/irq.c
      ARM: OMAP2+: Remove unused nand_irq for GPMC
      ARM: OMAP2+: Remove hardcoded twl4030 gpio_base, irq_base and irq_end
      ARM: OMAP: Move gpio.h to include/linux/platform_data
      ARM: OMAP2+: Prepare for irqs.h removal
      ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ
      ARM: OMAP1: Move plat/irqs.h to mach/irqs.h


 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    1 
 arch/arm/mach-omap1/board-ams-delta.c              |    3 
 arch/arm/mach-omap1/board-osk.c                    |    1 
 arch/arm/mach-omap1/dma.c                          |    3 
 arch/arm/mach-omap1/gpio15xx.c                     |    1 
 arch/arm/mach-omap1/gpio16xx.c                     |    1 
 arch/arm/mach-omap1/gpio7xx.c                      |    1 
 arch/arm/mach-omap1/include/mach/ams-delta-fiq.h   |    2 
 arch/arm/mach-omap1/include/mach/gpio.h            |    2 
 arch/arm/mach-omap1/include/mach/irqs.h            |  267 ++++++++++++
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 
 arch/arm/mach-omap1/leds.c                         |    1 
 arch/arm/mach-omap2/board-2430sdp.c                |   10 
 arch/arm/mach-omap2/board-3430sdp.c                |    3 
 arch/arm/mach-omap2/board-4430sdp.c                |    3 
 arch/arm/mach-omap2/board-am3517evm.c              |   12 -
 arch/arm/mach-omap2/board-cm-t35.c                 |   15 -
 arch/arm/mach-omap2/board-cm-t3517.c               |    6 
 arch/arm/mach-omap2/board-devkit8000.c             |    3 
 arch/arm/mach-omap2/board-flash.c                  |    3 
 arch/arm/mach-omap2/board-igep0020.c               |   10 
 arch/arm/mach-omap2/board-ldp.c                    |    3 
 arch/arm/mach-omap2/board-n8x0.c                   |    3 
 arch/arm/mach-omap2/board-omap3beagle.c            |    3 
 arch/arm/mach-omap2/board-omap3evm.c               |    3 
 arch/arm/mach-omap2/board-omap3logic.c             |    3 
 arch/arm/mach-omap2/board-omap3pandora.c           |    3 
 arch/arm/mach-omap2/board-omap3stalker.c           |    3 
 arch/arm/mach-omap2/board-omap3touchbook.c         |    3 
 arch/arm/mach-omap2/board-omap4panda.c             |    3 
 arch/arm/mach-omap2/board-overo.c                  |    3 
 arch/arm/mach-omap2/board-rm680.c                  |    9 
 arch/arm/mach-omap2/board-rx51-peripherals.c       |    5 
 arch/arm/mach-omap2/board-ti8168evm.c              |    3 
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    1 
 arch/arm/mach-omap2/board-zoom-display.c           |    6 
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    9 
 arch/arm/mach-omap2/cpuidle34xx.c                  |    1 
 arch/arm/mach-omap2/devices.c                      |    7 
 arch/arm/mach-omap2/gpio.c                         |    1 
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    1 
 arch/arm/mach-omap2/gpmc.c                         |   11 
 arch/arm/mach-omap2/hsmmc.c                        |    5 
 arch/arm/mach-omap2/include/mach/gpio.h            |    2 
 arch/arm/mach-omap2/include/mach/irqs.h            |    2 
 arch/arm/mach-omap2/io.c                           |    2 
 arch/arm/mach-omap2/irq.c                          |    2 
 arch/arm/mach-omap2/mailbox.c                      |    3 
 arch/arm/mach-omap2/mcbsp.c                        |    1 
 arch/arm/mach-omap2/msdi.c                         |    1 
 arch/arm/mach-omap2/omap-iommu.c                   |    1 
 arch/arm/mach-omap2/omap-wakeupgen.c               |    1 
 arch/arm/mach-omap2/omap4-common.c                 |    7 
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    2 
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    9 
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 -
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    4 
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   33 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 
 arch/arm/mach-omap2/omap_l3_noc.c                  |    6 
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 
 arch/arm/mach-omap2/pm24xx.c                       |    3 
 arch/arm/mach-omap2/pm34xx.c                       |    2 
 arch/arm/mach-omap2/prcm.c                         |    1 
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    3 
 arch/arm/mach-omap2/prm44xx.c                      |    4 
 arch/arm/mach-omap2/prm_common.c                   |    1 
 arch/arm/mach-omap2/serial.c                       |    1 
 arch/arm/mach-omap2/timer.c                        |   10 
 arch/arm/mach-omap2/twl-common.c                   |    3 
 arch/arm/mach-omap2/twl-common.h                   |    6 
 arch/arm/mach-omap2/usb-host.c                     |    1 
 arch/arm/mach-omap2/usb-musb.c                     |    1 
 arch/arm/plat-omap/Kconfig                         |    1 
 arch/arm/plat-omap/i2c.c                           |    3 
 arch/arm/plat-omap/include/plat/dma.h              |    2 
 arch/arm/plat-omap/include/plat/irqs-44xx.h        |  144 ------
 arch/arm/plat-omap/include/plat/irqs.h             |  453 --------------------
 arch/arm/plat-omap/include/plat/omap44xx.h         |    1 
 drivers/dma/omap-dma.c                             |    2 
 drivers/gpio/gpio-omap.c                           |   15 -
 drivers/gpio/gpio-twl4030.c                        |   15 -
 drivers/mfd/twl-core.c                             |    2 
 drivers/mtd/nand/ams-delta.c                       |    8 
 drivers/mtd/onenand/omap2.c                        |    8 
 drivers/tty/serial/8250/8250.c                     |    4 
 drivers/video/omap2/dss/dispc.c                    |    1 
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 
 include/linux/i2c/twl.h                            |    3 
 include/linux/mfd/twl6040.h                        |    2 
 include/linux/platform_data/gpio-omap.h            |   15 -
 include/linux/platform_data/mtd-nand-omap2.h       |    1 
 sound/soc/omap/mcbsp.c                             |    3 
 sound/soc/omap/omap-mcbsp.c                        |    1 
 sound/soc/omap/omap-pcm.c                          |    1 
 sound/soc/omap/sdp3430.c                           |    1 
 96 files changed, 455 insertions(+), 808 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/irqs-44xx.h
 delete mode 100644 arch/arm/plat-omap/include/plat/irqs.h
 rename arch/arm/plat-omap/include/plat/gpio.h => include/linux/platform_data/gpio-omap.h (94%)

-- 
Signature


From tony at atomide.com  Thu Aug 30 20:52:21 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:21 -0700
Subject: [PATCH 1/9] ARM: OMAP1: Move define of OMAP_LCD_DMA to dma.h
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005221.28732.16339.stgit@muffinssi.local>

This is needed to start removing hardcoded IRQs on omap2+.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/include/plat/dma.h  |    2 ++
 arch/arm/plat-omap/include/plat/irqs.h |    1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index c5811d4..0a87b05 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -31,6 +31,8 @@
 /* Move omap4 specific defines to dma-44xx.h */
 #include "dma-44xx.h"
 
+#define INT_DMA_LCD			25
+
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE		0
 #define OMAP_DMA_MCSI1_TX		1
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 37bbbbb..15f497c 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -53,7 +53,6 @@
 #define INT_DMA_CH3		22
 #define INT_DMA_CH4		23
 #define INT_DMA_CH5		24
-#define INT_DMA_LCD		25
 #define INT_TIMER1		26
 #define INT_WD_TIMER		27
 #define INT_BRIDGE_PUB		28



From tony at atomide.com  Thu Aug 30 20:52:24 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:24 -0700
Subject: [PATCH 2/9] ARM: OMAP1: Define OMAP1_INT_I2C locally
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005224.28732.88615.stgit@muffinssi.local>

This is needed to start removing hardcoded IRQs for omap2+.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/i2c.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc..40bc06a 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -39,6 +39,7 @@
 
 #define OMAP_I2C_SIZE		0x3f
 #define OMAP1_I2C_BASE		0xfffb3800
+#define OMAP1_INT_I2C		(32 + 4)
 
 static const char name[] = "omap_i2c";
 
@@ -105,7 +106,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
 	res = pdev->resource;
 	res[0].start = OMAP1_I2C_BASE;
 	res[0].end = res[0].start + OMAP_I2C_SIZE;
-	res[1].start = INT_I2C;
+	res[1].start = OMAP1_INT_I2C;
 	pdata = &i2c_pdata[bus_id - 1];
 
 	/* all OMAP1 have IP version 1 register set */



From tony at atomide.com  Thu Aug 30 20:52:26 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:26 -0700
Subject: [PATCH 3/9] ARM: OMAP2+: Make INTCPS_NR_IRQS local for
 mach-omap2/irq.c
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005226.28732.37930.stgit@muffinssi.local>

Make INTCPS_NR_IRQS local for mach-omap2/irq.c

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/irq.c              |    2 ++
 arch/arm/plat-omap/include/plat/irqs.h |    3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bcd83db..ac59f96 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -49,6 +49,8 @@
 #define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
 #define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
 #define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+#define INTCPS_NR_MIR_REGS	3
+#define INTCPS_NR_IRQS		96
 
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 15f497c..fc3959c 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -440,9 +440,6 @@
 
 #define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
 
-#define INTCPS_NR_MIR_REGS	3
-#define INTCPS_NR_IRQS		96
-
 #include <mach/hardware.h>
 
 #ifdef CONFIG_FIQ



From tony at atomide.com  Thu Aug 30 20:52:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:28 -0700
Subject: [PATCH 4/9] ARM: OMAP2+: Remove unused nand_irq for GPMC
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005228.28732.90454.stgit@muffinssi.local>

This is no longer needed and assumes a fixed IRQ number
that won't work with SPARSE_IRQ.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-flash.c            |    1 -
 include/linux/platform_data/mtd-nand-omap2.h |    1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index a1ef5f0..c8d4382 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -140,7 +140,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
 	board_nand_data.devsize		= nand_type;
 
 	board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-	board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
 	gpmc_nand_init(&board_nand_data);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h
index 290cef5..1a68c1e 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -24,7 +24,6 @@ struct omap_nand_platform_data {
 	struct gpmc_timings	*gpmc_t;
 	int			nr_parts;
 	bool			dev_ready;
-	int			gpmc_irq;
 	enum nand_io		xfer_type;
 	int			devsize;
 	enum omap_ecc           ecc_opt;



From tony at atomide.com  Thu Aug 30 20:52:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:30 -0700
Subject: [PATCH 5/9] ARM: OMAP2+: Remove hardcoded twl4030 gpio_base,
 irq_base and irq_end
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005230.28732.1131.stgit@muffinssi.local>

We can't use hardcoded interrupts for SPARSE_IRQ, and can replace
the hardcoded gpio_base with twl_gpiochip.base after it's been
allocated.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-2430sdp.c          |    3 ---
 arch/arm/mach-omap2/board-3430sdp.c          |    3 ---
 arch/arm/mach-omap2/board-4430sdp.c          |    1 -
 arch/arm/mach-omap2/board-cm-t35.c           |    3 ---
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ---
 arch/arm/mach-omap2/board-igep0020.c         |    3 ---
 arch/arm/mach-omap2/board-ldp.c              |    3 ---
 arch/arm/mach-omap2/board-omap3beagle.c      |    3 ---
 arch/arm/mach-omap2/board-omap3evm.c         |    3 ---
 arch/arm/mach-omap2/board-omap3logic.c       |    3 ---
 arch/arm/mach-omap2/board-omap3pandora.c     |    3 ---
 arch/arm/mach-omap2/board-omap3stalker.c     |    3 ---
 arch/arm/mach-omap2/board-omap3touchbook.c   |    3 ---
 arch/arm/mach-omap2/board-omap4panda.c       |    1 -
 arch/arm/mach-omap2/board-overo.c            |    3 ---
 arch/arm/mach-omap2/board-rm680.c            |    3 ---
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ---
 arch/arm/mach-omap2/board-zoom-peripherals.c |    3 ---
 drivers/gpio/gpio-twl4030.c                  |   15 ++++++++++-----
 include/linux/i2c/twl.h                      |    3 ---
 include/linux/mfd/twl6040.h                  |    2 --
 21 files changed, 10 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 36eee4b..cacc498 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -211,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index dac5cdf..5fd3934 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -229,9 +229,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.pulldowns	= BIT(2) | BIT(6) | BIT(8) | BIT(13)
 				| BIT(16) | BIT(17),
 	.setup		= sdp3430_twl_gpio_setup,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 04e8574..ee82604 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -543,7 +543,6 @@ static struct twl6040_platform_data twl6040_data = {
 	.codec		= &twl6040_codec,
 	.vibra		= &twl6040_vibra,
 	.audpwron_gpio	= 127,
-	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 6e20b82..ad83654 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -469,9 +469,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 }
 
 static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.setup          = cm_t35_twl_gpio_setup,
 };
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 214be52..d96eab5 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -235,9 +235,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.pulldowns	= BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
 				| BIT(15) | BIT(16) | BIT(17),
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 7a3e536..0b9677b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -424,9 +424,6 @@ static int igep_twl_gpio_setup(struct device *dev,
 };
 
 static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.setup		= igep_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index dc41435..e85323c86 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -274,9 +274,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 }
 
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.setup		= ldp_twl_gpio_setup,
 };
 
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d74eb37..b259713 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -296,9 +296,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data beagle_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.pullups	= BIT(1),
 	.pulldowns	= BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 64245bf..0470d44 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -387,9 +387,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.setup		= omap3evm_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index a63a49d..8fe7f0c 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -77,9 +77,6 @@ static struct regulator_init_data omap3logic_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.pullups	= BIT(1),
 	.pulldowns	= BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index d14b0cd..93c6109 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -320,9 +320,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.setup		= omap3pandora_twl_gpio_setup,
 };
 
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 2ec4802..465ee22 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -278,9 +278,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.setup		= omap3stalker_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index b0516ec..ba657cd 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -138,9 +138,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data touchbook_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.pullups	= BIT(1),
 	.pulldowns	= BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 3911c13..e37ee67 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -262,7 +262,6 @@ static struct twl6040_codec_data twl6040_codec = {
 static struct twl6040_platform_data twl6040_data = {
 	.codec		= &twl6040_codec,
 	.audpwron_gpio	= 127,
-	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
 /* Panda board uses the common PMIC configuration */
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 3aaf4af..ec42d6c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -398,9 +398,6 @@ static int overo_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data overo_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.use_leds	= true,
 	.setup		= overo_twl_gpio_setup,
 };
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index bbfbe56..4c45109 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -72,9 +72,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = {
 
 /* TWL */
 static struct twl4030_gpio_platform_data rm680_gpio_data = {
-	.gpio_base		= OMAP_MAX_GPIO_LINES,
-	.irq_base		= TWL4030_GPIO_IRQ_BASE,
-	.irq_end		= TWL4030_GPIO_IRQ_END,
 	.pullups		= BIT(0),
 	.pulldowns		= BIT(1) | BIT(2) | BIT(8) | BIT(15),
 };
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 4be0552..06e44e4 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -773,9 +773,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 }
 
 static struct twl4030_gpio_platform_data rx51_gpio_data = {
-	.gpio_base		= OMAP_MAX_GPIO_LINES,
-	.irq_base		= TWL4030_GPIO_IRQ_BASE,
-	.irq_end		= TWL4030_GPIO_IRQ_END,
 	.pulldowns		= BIT(0) | BIT(1) | BIT(2) | BIT(3)
 				| BIT(4) | BIT(5)
 				| BIT(8) | BIT(9) | BIT(10) | BIT(11)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index b797cb2..00f73b7 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -251,9 +251,6 @@ static void zoom2_set_hs_extmute(int mute)
 }
 
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
-	.gpio_base	= OMAP_MAX_GPIO_LINES,
-	.irq_base	= TWL4030_GPIO_IRQ_BASE,
-	.irq_end	= TWL4030_GPIO_IRQ_END,
 	.setup		= zoom_twl_gpio_setup,
 };
 
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 94256fe..f030880 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -51,6 +51,7 @@
 
 
 static struct gpio_chip twl_gpiochip;
+static int twl4030_gpio_base;
 static int twl4030_gpio_irq_base;
 
 /* genirq interfaces are not available to modules */
@@ -428,8 +429,6 @@ no_irqs:
 	twl_gpiochip.dev = &pdev->dev;
 
 	if (pdata) {
-		twl_gpiochip.base = pdata->gpio_base;
-
 		/*
 		 * NOTE:  boards may waste power if they don't set pullups
 		 * and pulldowns correctly ... default for non-ULPI pins is
@@ -461,15 +460,21 @@ no_irqs:
 		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
 		twl_gpiochip.ngpio = 0;
 		gpio_twl4030_remove(pdev);
-	} else if (pdata && pdata->setup) {
+		goto out;
+	}
+
+	twl4030_gpio_base = twl_gpiochip.base;
+
+	if (pdata && pdata->setup) {
 		int status;
 
 		status = pdata->setup(&pdev->dev,
-				pdata->gpio_base, TWL4030_GPIO_MAX);
+				twl4030_gpio_base, TWL4030_GPIO_MAX);
 		if (status)
 			dev_dbg(&pdev->dev, "setup --> %d\n", status);
 	}
 
+out:
 	return ret;
 }
 
@@ -481,7 +486,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
 
 	if (pdata && pdata->teardown) {
 		status = pdata->teardown(&pdev->dev,
-				pdata->gpio_base, TWL4030_GPIO_MAX);
+				twl4030_gpio_base, TWL4030_GPIO_MAX);
 		if (status) {
 			dev_dbg(&pdev->dev, "teardown --> %d\n", status);
 			return status;
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 7ea898c..a12a381 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -561,9 +561,6 @@ struct twl4030_bci_platform_data {
 
 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
 struct twl4030_gpio_platform_data {
-	int		gpio_base;
-	unsigned	irq_base, irq_end;
-
 	/* package the two LED signals as output-only GPIOs? */
 	bool		use_leds;
 
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index eaad49f..55b77b3 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -194,7 +194,6 @@ struct twl6040_vibra_data {
 
 struct twl6040_platform_data {
 	int audpwron_gpio;	/* audio power-on gpio */
-	unsigned int irq_base;
 
 	struct twl6040_codec_data *codec;
 	struct twl6040_vibra_data *vibra;
@@ -222,7 +221,6 @@ struct twl6040 {
 	unsigned int mclk;
 
 	unsigned int irq;
-	unsigned int irq_base;
 	u8 irq_masks_cur;
 	u8 irq_masks_cache;
 };



From tony at atomide.com  Thu Aug 30 20:52:34 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:34 -0700
Subject: [PATCH 6/9] ARM: OMAP: Move gpio.h to include/linux/platform_data
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005234.28732.10624.stgit@muffinssi.local>

This way we can remove includes of plat/gpio.h which won't work
with the single zImage support.

Note that we also remove the cpu_class_is_omap2() check
in gpio-omap.c as the drivers should not call it as we need to
make it local to arch/arm/mach-omap2 for single zImage support.

While at it, arrange the related includes in the standard way.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at linaro.org>
Cc: linux-mtd at lists.infradead.org
Cc: alsa-devel at alsa-project.org
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/board-ams-delta.c              |    3 ++-
 arch/arm/mach-omap1/board-osk.c                    |    1 +
 arch/arm/mach-omap1/gpio15xx.c                     |    1 +
 arch/arm/mach-omap1/gpio16xx.c                     |    1 +
 arch/arm/mach-omap1/gpio7xx.c                      |    1 +
 arch/arm/mach-omap1/include/mach/gpio.h            |    2 --
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 +++-
 arch/arm/mach-omap1/leds.c                         |    1 +
 arch/arm/mach-omap2/board-am3517evm.c              |    9 ++++++---
 arch/arm/mach-omap2/board-cm-t35.c                 |   12 +++++++-----
 arch/arm/mach-omap2/board-zoom-display.c           |    6 +++++-
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    1 +
 arch/arm/mach-omap2/gpio.c                         |    1 +
 arch/arm/mach-omap2/hsmmc.c                        |    5 ++++-
 arch/arm/mach-omap2/include/mach/gpio.h            |    2 --
 arch/arm/mach-omap2/msdi.c                         |    1 +
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 -
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    6 +++---
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    6 +++---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 +++---
 arch/arm/mach-omap2/pm24xx.c                       |    1 +
 arch/arm/mach-omap2/pm34xx.c                       |    2 ++
 drivers/gpio/gpio-omap.c                           |   15 ++++++++-------
 drivers/mtd/nand/ams-delta.c                       |    8 ++++++--
 include/linux/platform_data/gpio-omap.h            |   15 ++-------------
 sound/soc/omap/sdp3430.c                           |    1 +
 27 files changed, 65 insertions(+), 49 deletions(-)
 rename arch/arm/plat-omap/include/plat/gpio.h => include/linux/platform_data/gpio-omap.h (94%)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 147d665..4b5578b 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -26,6 +26,8 @@
 #include <linux/export.h>
 #include <linux/omapfb.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <media/soc_camera.h>
 
@@ -35,7 +37,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/board-ams-delta.h>
-#include <linux/platform_data/keypad-omap.h>
 #include <plat/mux.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 9413fd3..c780a1b 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -39,6 +39,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index ebef15e..98e6f39 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1_MPUIO_VBASE		OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE		0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 2a48cd2..33f4192 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1610_GPIO1_BASE		0xfffbe400
 #define OMAP1610_GPIO2_BASE		0xfffbec00
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index acf12b7..958ce9a 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP7XX_GPIO1_BASE		0xfffbc000
 #define OMAP7XX_GPIO2_BASE		0xfffbc800
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
index e737706..ebf86c0 100644
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ b/arch/arm/mach-omap1/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap1/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index f6b14a1..3ea12c7 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -14,13 +14,15 @@
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
 
+#include <mach/hardware.h>
+
 #include "leds.h"
 
 
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index ae6dd93..7b1a383 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -6,6 +6,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 00abda1..c6d63d7 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,19 +25,22 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <mach/am35xx.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/usb.h>
+
+#include <mach/hardware.h>
+#include <mach/am35xx.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "common.h"
 #include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ad83654..c2b2371 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -23,6 +23,9 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
@@ -37,17 +40,16 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
+
+#include <mach/hardware.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-
-#include <mach/hardware.h>
 
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 660a2932..0e48a51 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -15,9 +15,13 @@
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
-#include <video/omapdss.h>
+
+#include <plat/cpu.h>
+
 #include <mach/board-zoom.h>
 
+#include <video/omapdss.h>
+
 #define LCD_PANEL_RESET_GPIO_PROD	96
 #define LCD_PANEL_RESET_GPIO_PILOT	55
 #define LCD_PANEL_QVGA_GPIO		56
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 00f73b7..ae5d36b 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d48..7b52bdf 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9675d8..4b0e166 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,12 +14,15 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
-#include <mach/hardware.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
 #include <plat/mux.h>
 #include <plat/omap_device.h>
 
+#include <mach/hardware.h>
+
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
index be4d290..5621cc5 100644
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index fb5bc6c..9e57b4a 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -23,6 +23,7 @@
 
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 558c300..b305d7f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,7 +18,6 @@
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d662766..79ac236 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,15 +12,15 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/dsp-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <linux/platform_data/dsp-mcbsp.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/mmc.h>
 #include <plat/l3_2xxx.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 161ae0a..44e4764 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,9 +10,9 @@
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 656bb7f..15f617e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -15,6 +15,9 @@
  * XXX these should be marked initdata for multi-OMAP kernels
  */
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/dsp-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <plat/omap_hwmod.h>
 #include <mach/irqs.h>
@@ -24,10 +27,7 @@
 #include <plat/l3_3xxx.h>
 #include <plat/l4_3xxx.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mmc.h>
-#include <linux/platform_data/dsp-mcbsp.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3a06e7d..c9edaf2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,15 +19,15 @@
  */
 
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/dsp-mcbsp.h>
 #include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/dsp-mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index de1caf1..2708a8b 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c..2a08978 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..64fbce3 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,9 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
 #define OFF_MODE	1
@@ -385,13 +383,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
 static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned gpio;
+	unsigned gpio = 0;
 	int retval;
 	unsigned long flags;
 
-	if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
+#ifdef CONFIG_ARCH_OMAP1
+	if (d->irq > IH_MPUIO_BASE)
 		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-	else
+#endif
+
+	if (!gpio)
 		gpio = irq_to_gpio(bank, d->irq);
 
 	if (type & ~IRQ_TYPE_SENSE_MASK)
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 861ca8f..78a524b 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -23,12 +23,16 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <asm/io.h>
-#include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <linux/gpio.h>
+
 #include <plat/board-ams-delta.h>
 
+#include <mach/hardware.h>
+
 /*
  * MTD structure for E3 (Delta)
  */
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/include/linux/platform_data/gpio-omap.h
similarity index 94%
rename from arch/arm/plat-omap/include/plat/gpio.h
rename to include/linux/platform_data/gpio-omap.h
index 50fb7cc..e8741c2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/include/linux/platform_data/gpio-omap.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/gpio.h
- *
  * OMAP GPIO handling defines and functions
  *
  * Copyright (C) 2003-2005 Nokia Corporation
@@ -155,6 +153,8 @@
 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
 #define OMAP4_GPIO_SETDATAOUT		0x0194
 
+#define OMAP_MAX_GPIO_LINES		192
+
 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
 
@@ -213,16 +213,5 @@ extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-/*-------------------------------------------------------------------------*/
-
-/*
- * Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- *
- * The original OMAP-specific calls should eventually be removed.
- */
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
 
 #endif
diff --git a/sound/soc/omap/sdp3430.c b/sound/soc/omap/sdp3430.c
index 33f4ac2..da45b51 100644
--- a/sound/soc/omap/sdp3430.c
+++ b/sound/soc/omap/sdp3430.c
@@ -33,6 +33,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/dsp-mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */



From tony at atomide.com  Thu Aug 30 20:52:39 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:39 -0700
Subject: [PATCH 8/9] ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005239.28732.47333.stgit@muffinssi.local>

Remove hardcoded IRQs in irqs.h and related files as these
are no longer needed.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/include/mach/irqs.h     |    2 
 arch/arm/plat-omap/Kconfig                  |    1 
 arch/arm/plat-omap/include/plat/irqs-44xx.h |  144 ---------------------
 arch/arm/plat-omap/include/plat/irqs.h      |  183 ---------------------------
 4 files changed, 2 insertions(+), 328 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/irqs-44xx.h

diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
index 44dab77..ba5282c 100644
--- a/arch/arm/mach-omap2/include/mach/irqs.h
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/irqs.h
  */
-
-#include <plat/irqs.h>
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba..d15a4a6 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
 	bool "TI OMAP2/3/4"
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
+	select SPARSE_IRQ
 	select OMAP_DM_TIMER
 	select USE_OF
 	select PROC_DEVICETREE if PROC_FS
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c..0000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * OMAP4 Interrupt lines definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Santosh Shilimkar (santosh.shilimkar at ti.com)
- * Benoit Cousson (b-cousson at ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap at vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-
-/* OMAP44XX IRQs numbers definitions */
-#define OMAP44XX_IRQ_LOCALTIMER			29
-#define OMAP44XX_IRQ_LOCALWDT			30
-
-#define OMAP44XX_IRQ_GIC_START			32
-
-#define OMAP44XX_IRQ_PL310			(0 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI0			(1 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI1			(2 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ELM			(4 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_1N			(7 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SECURITY_EVENTS		(8 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_DBG			(9 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_APP			(10 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PRCM			(11 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_0			(12 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_1			(13 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_2			(14 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_3			(15 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP4			(16 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP1			(17 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_MCU			(18 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_CORE			(19 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPMC			(20 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GFX			(21 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP2			(22 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP3			(23 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ISS_5			(24 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DISPC			(25 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MAIL_U0			(26 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_0			(27 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TESLA_MMU			(28 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO1			(29 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO2			(30 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO3			(31 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO4			(32 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO5			(33 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO6			(34 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_USIM			(35 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT3			(36 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT1			(37 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT2			(38 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT3			(39 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT4			(40 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT5			(41 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT6			(42 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT7			(43 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT8			(44 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT9			(45 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT10			(46 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT11			(47 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI4			(48 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_S			(49 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S		(50 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_P			(51 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_RNG			(52 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI1			(53 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C1			(56 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C2			(57 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HDQ			(58 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC5			(59 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C3			(61 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C4			(62 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_S			(63 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_P			(64 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI1			(65 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI2			(66 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P1			(67 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P2			(68 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FDIF_3			(69 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART4			(70 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_DMA			(71 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART1			(72 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART2			(73 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART3			(74 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PBIAS			(75 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_OHCI			(76 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EHCI			(77 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TLL			(78 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_S			(79 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT2			(80 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_S			(81 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_P			(82 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC1			(83 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI2			(84 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_P			(85 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC2			(86 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MPU_ICR			(87 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_1			(88 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB			(89 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB_SMI			(90 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI3			(91 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_MC_N		(92 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_DMA_N		(93 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC3			(94 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT12			(95 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC4			(96 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS1			(97 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS2			(98 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ABE			(99 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DUCATI_MMU			(100 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_HDMI			(101 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_IVA			(102 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1	(103 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0	(104 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0	(107 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AR			(108 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AX			(109 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_1			(110 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_2			(111 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCPDM			(112 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMM			(113 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMIC			(114 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_0			(115 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_1			(116 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_2			(117 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_3			(118 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_2N			(119 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_KBD_CTL			(120 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UNIPRO1			(124 + OMAP44XX_IRQ_GIC_START)
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index fc3959c..729992d 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,9 +28,6 @@
 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
 #define __ASM_ARCH_OMAP15XX_IRQS_H
 
-/* All OMAP4 specific defines are moved to irqs-44xx.h */
-#include "irqs-44xx.h"
-
 /*
  * IRQ numbers for interrupt handler 1
  *
@@ -242,125 +239,6 @@
 #define INT_7XX_DMA_CH15	(62 + IH2_BASE)
 #define INT_7XX_NAND		(63 + IH2_BASE)
 
-#define INT_24XX_SYS_NIRQ	7
-#define INT_24XX_SDMA_IRQ0	12
-#define INT_24XX_SDMA_IRQ1	13
-#define INT_24XX_SDMA_IRQ2	14
-#define INT_24XX_SDMA_IRQ3	15
-#define INT_24XX_CAM_IRQ	24
-#define INT_24XX_DSS_IRQ	25
-#define INT_24XX_MAIL_U0_MPU	26
-#define INT_24XX_DSP_UMA	27
-#define INT_24XX_DSP_MMU	28
-#define INT_24XX_GPIO_BANK1	29
-#define INT_24XX_GPIO_BANK2	30
-#define INT_24XX_GPIO_BANK3	31
-#define INT_24XX_GPIO_BANK4	32
-#define INT_24XX_GPIO_BANK5	33
-#define INT_24XX_MAIL_U3_MPU	34
-#define INT_24XX_GPTIMER1	37
-#define INT_24XX_GPTIMER2	38
-#define INT_24XX_GPTIMER3	39
-#define INT_24XX_GPTIMER4	40
-#define INT_24XX_GPTIMER5	41
-#define INT_24XX_GPTIMER6	42
-#define INT_24XX_GPTIMER7	43
-#define INT_24XX_GPTIMER8	44
-#define INT_24XX_GPTIMER9	45
-#define INT_24XX_GPTIMER10	46
-#define INT_24XX_GPTIMER11	47
-#define INT_24XX_GPTIMER12	48
-#define INT_24XX_SHA1MD5	51
-#define INT_24XX_MCBSP4_IRQ_TX	54
-#define INT_24XX_MCBSP4_IRQ_RX	55
-#define INT_24XX_I2C1_IRQ	56
-#define INT_24XX_I2C2_IRQ	57
-#define INT_24XX_HDQ_IRQ	58
-#define INT_24XX_MCBSP1_IRQ_TX	59
-#define INT_24XX_MCBSP1_IRQ_RX	60
-#define INT_24XX_MCBSP2_IRQ_TX	62
-#define INT_24XX_MCBSP2_IRQ_RX	63
-#define INT_24XX_SPI1_IRQ	65
-#define INT_24XX_SPI2_IRQ	66
-#define INT_24XX_UART1_IRQ	72
-#define INT_24XX_UART2_IRQ	73
-#define INT_24XX_UART3_IRQ	74
-#define INT_24XX_USB_IRQ_GEN	75
-#define INT_24XX_USB_IRQ_NISO	76
-#define INT_24XX_USB_IRQ_ISO	77
-#define INT_24XX_USB_IRQ_HGEN	78
-#define INT_24XX_USB_IRQ_HSOF	79
-#define INT_24XX_USB_IRQ_OTG	80
-#define INT_24XX_MCBSP5_IRQ_TX	81
-#define INT_24XX_MCBSP5_IRQ_RX	82
-#define INT_24XX_MMC_IRQ	83
-#define INT_24XX_MMC2_IRQ	86
-#define INT_24XX_MCBSP3_IRQ_TX	89
-#define INT_24XX_MCBSP3_IRQ_RX	90
-#define INT_24XX_SPI3_IRQ	91
-
-#define INT_243X_MCBSP2_IRQ	16
-#define INT_243X_MCBSP3_IRQ	17
-#define INT_243X_MCBSP4_IRQ	18
-#define INT_243X_MCBSP5_IRQ	19
-#define INT_243X_MCBSP1_IRQ	64
-#define INT_243X_HS_USB_MC	92
-#define INT_243X_HS_USB_DMA	93
-#define INT_243X_CARKIT_IRQ	94
-
-#define INT_34XX_BENCH_MPU_EMUL	3
-#define INT_34XX_ST_MCBSP2_IRQ	4
-#define INT_34XX_ST_MCBSP3_IRQ	5
-#define INT_34XX_SSM_ABORT_IRQ	6
-#define INT_34XX_SYS_NIRQ	7
-#define INT_34XX_D2D_FW_IRQ	8
-#define INT_34XX_L3_DBG_IRQ     9
-#define INT_34XX_L3_APP_IRQ     10
-#define INT_34XX_PRCM_MPU_IRQ	11
-#define INT_34XX_MCBSP1_IRQ	16
-#define INT_34XX_MCBSP2_IRQ	17
-#define INT_34XX_GPMC_IRQ	20
-#define INT_34XX_MCBSP3_IRQ	22
-#define INT_34XX_MCBSP4_IRQ	23
-#define INT_34XX_CAM_IRQ	24
-#define INT_34XX_MCBSP5_IRQ	27
-#define INT_34XX_GPIO_BANK1	29
-#define INT_34XX_GPIO_BANK2	30
-#define INT_34XX_GPIO_BANK3	31
-#define INT_34XX_GPIO_BANK4	32
-#define INT_34XX_GPIO_BANK5	33
-#define INT_34XX_GPIO_BANK6	34
-#define INT_34XX_USIM_IRQ	35
-#define INT_34XX_WDT3_IRQ	36
-#define INT_34XX_SPI4_IRQ	48
-#define INT_34XX_SHA1MD52_IRQ	49
-#define INT_34XX_FPKA_READY_IRQ	50
-#define INT_34XX_SHA1MD51_IRQ	51
-#define INT_34XX_RNG_IRQ	52
-#define INT_34XX_I2C3_IRQ	61
-#define INT_34XX_FPKA_ERROR_IRQ	64
-#define INT_34XX_PBIAS_IRQ	75
-#define INT_34XX_OHCI_IRQ	76
-#define INT_34XX_EHCI_IRQ	77
-#define INT_34XX_TLL_IRQ	78
-#define INT_34XX_PARTHASH_IRQ	79
-#define INT_34XX_MMC3_IRQ	94
-#define INT_34XX_GPT12_IRQ	95
-
-#define INT_36XX_UART4_IRQ	80
-
-#define INT_35XX_HECC0_IRQ		24
-#define INT_35XX_HECC1_IRQ		28
-#define INT_35XX_EMAC_C0_RXTHRESH_IRQ	67
-#define INT_35XX_EMAC_C0_RX_PULSE_IRQ	68
-#define INT_35XX_EMAC_C0_TX_PULSE_IRQ	69
-#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ	70
-#define INT_35XX_USBOTG_IRQ		71
-#define INT_35XX_UART4_IRQ		84
-#define INT_35XX_CCDC_VD0_IRQ		88
-#define INT_35XX_CCDC_VD1_IRQ		92
-#define INT_35XX_CCDC_VD2_IRQ		93
-
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES	192
@@ -377,66 +255,7 @@
 #endif
 #define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
 
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define	TWL4030_IRQ_BASE	(OMAP_FPGA_IRQ_END)
-#ifdef	CONFIG_TWL4030_CORE
-#define	TWL4030_BASE_NR_IRQS	8
-#define	TWL4030_PWR_NR_IRQS	8
-#else
-#define	TWL4030_BASE_NR_IRQS	0
-#define	TWL4030_PWR_NR_IRQS	0
-#endif
-#define TWL4030_IRQ_END		(TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE	TWL4030_IRQ_END
-#define	TWL4030_PWR_IRQ_END	(TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE	TWL4030_PWR_IRQ_END
-#ifdef	CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS	18
-#else
-#define	TWL4030_GPIO_NR_IRQS	0
-#endif
-#define TWL4030_GPIO_IRQ_END	(TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-#define	TWL6030_IRQ_BASE	(OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define	TWL6030_BASE_NR_IRQS	20
-#else
-#define	TWL6030_BASE_NR_IRQS	0
-#endif
-#define TWL6030_IRQ_END		(TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
-
-#define TWL6040_CODEC_IRQ_BASE	TWL6030_IRQ_END
-#ifdef CONFIG_TWL6040_CODEC
-#define TWL6040_CODEC_NR_IRQS	6
-#else
-#define TWL6040_CODEC_NR_IRQS	0
-#endif
-#define TWL6040_CODEC_IRQ_END	(TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
-#define TWL_IRQ_END 		TWL4030_GPIO_IRQ_END
-#else
-#define TWL_IRQ_END		TWL6040_CODEC_IRQ_END
-#endif
-
-/* GPMC related */
-#define OMAP_GPMC_IRQ_BASE	(TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS	8
-#define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
-
-/* PRCM IRQ handler */
-#ifdef CONFIG_ARCH_OMAP2PLUS
-#define OMAP_PRCM_IRQ_BASE	(OMAP_GPMC_IRQ_END)
-#define OMAP_PRCM_NR_IRQS	64
-#define OMAP_PRCM_IRQ_END	(OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
-#else
-#define OMAP_PRCM_IRQ_END	OMAP_GPMC_IRQ_END
-#endif
-
-#define NR_IRQS			OMAP_PRCM_IRQ_END
+#define NR_IRQS			OMAP_FPGA_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
 



From tony at atomide.com  Thu Aug 30 20:52:37 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:37 -0700
Subject: [PATCH 7/9] ARM: OMAP2+: Prepare for irqs.h removal
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005237.28732.96766.stgit@muffinssi.local>

As the interrupts should only be defined in the platform_data, and
eventually coming from device tree, there's no need to define them
in header files.

Let's remove the hardcoded references to irqs.h and fix up the includes
so we don't rely on headers included in irqs.h. While at it, sort
the includes the standard way.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-2430sdp.c                |    7 +++--
 arch/arm/mach-omap2/board-4430sdp.c                |    2 +
 arch/arm/mach-omap2/board-am3517evm.c              |    3 +-
 arch/arm/mach-omap2/board-cm-t3517.c               |    6 ++--
 arch/arm/mach-omap2/board-flash.c                  |    2 +
 arch/arm/mach-omap2/board-igep0020.c               |    7 +++--
 arch/arm/mach-omap2/board-n8x0.c                   |    3 +-
 arch/arm/mach-omap2/board-omap4panda.c             |    2 +
 arch/arm/mach-omap2/board-rm680.c                  |    6 +++-
 arch/arm/mach-omap2/board-rx51-peripherals.c       |    2 +
 arch/arm/mach-omap2/board-ti8168evm.c              |    3 +-
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    1 +
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    5 ++--
 arch/arm/mach-omap2/cpuidle34xx.c                  |    1 -
 arch/arm/mach-omap2/devices.c                      |    7 +----
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    1 +
 arch/arm/mach-omap2/gpmc.c                         |   11 +++++---
 arch/arm/mach-omap2/io.c                           |    2 +
 arch/arm/mach-omap2/mailbox.c                      |    3 +-
 arch/arm/mach-omap2/mcbsp.c                        |    1 -
 arch/arm/mach-omap2/omap-iommu.c                   |    1 -
 arch/arm/mach-omap2/omap-wakeupgen.c               |    1 +
 arch/arm/mach-omap2/omap4-common.c                 |    7 ++---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 -
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    3 +-
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 ++++-----
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    2 -
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   27 ++++++++++----------
 arch/arm/mach-omap2/omap_l3_noc.c                  |    6 +++-
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 +
 arch/arm/mach-omap2/pm24xx.c                       |    2 -
 arch/arm/mach-omap2/prcm.c                         |    1 -
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    3 +-
 arch/arm/mach-omap2/prm44xx.c                      |    4 +--
 arch/arm/mach-omap2/prm_common.c                   |    1 -
 arch/arm/mach-omap2/serial.c                       |    1 +
 arch/arm/mach-omap2/timer.c                        |   10 ++++---
 arch/arm/mach-omap2/twl-common.c                   |    3 +-
 arch/arm/mach-omap2/twl-common.h                   |    6 +---
 arch/arm/mach-omap2/usb-host.c                     |    1 -
 arch/arm/mach-omap2/usb-musb.c                     |    1 -
 arch/arm/plat-omap/include/plat/omap44xx.h         |    1 +
 drivers/dma/omap-dma.c                             |    2 +
 drivers/mfd/twl-core.c                             |    2 +
 drivers/mtd/onenand/omap2.c                        |    8 ++++--
 drivers/tty/serial/8250/8250.c                     |    4 +--
 drivers/video/omap2/dss/dispc.c                    |    1 +
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 ++-
 sound/soc/omap/mcbsp.c                             |    3 +-
 sound/soc/omap/omap-mcbsp.c                        |    1 +
 sound/soc/omap/omap-pcm.c                          |    1 +
 51 files changed, 105 insertions(+), 92 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index cacc498..3a587d0 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -28,19 +28,20 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
 
+#include <mach/hardware.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -231,7 +232,7 @@ static int __init omap2430_i2c_init(void)
 	sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
 	omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
 			ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-	omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
+	omap_pmic_init(2, 100, "twl4030", 7,
 			&sdp2430_twldata);
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index ee82604..31456ea 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -579,7 +579,7 @@ static int __init omap4_i2c_init(void)
 			TWL_COMMON_REGULATOR_V1V8 |
 			TWL_COMMON_REGULATOR_V2V1);
 	omap4_pmic_init("twl6030", &sdp4430_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+			&twl6040_data, 119 + OMAP44XX_IRQ_GIC_START);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
 				ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index c6d63d7..818f664 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -298,8 +298,7 @@ static struct resource am3517_hecc_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start	= INT_35XX_HECC0_IRQ,
-		.end	= INT_35XX_HECC0_IRQ,
+		.start	= 24,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 30b7b01..d1c59d3 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -38,13 +38,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/usb.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
+#include <plat/serial.h>
 
 #include <mach/am35xx.h>
 
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 #include "common-board-devices.h"
@@ -89,8 +90,7 @@ static struct resource cm_t3517_hecc_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start	= INT_35XX_HECC0_IRQ,
-		.end	= INT_35XX_HECC0_IRQ,
+		.start	= 24,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c8d4382..bd67c4c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -16,8 +16,8 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-#include <plat/irqs.h>
 
+#include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0b9677b..0dfed5a 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -23,19 +23,20 @@
 #include <linux/regulator/fixed.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
-
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
+#include <plat/serial.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index edf6559..eed16d6 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include <plat/menelaus.h>
-#include <mach/irqs.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/mmc.h>
@@ -599,7 +598,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
 static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
 	{
 		I2C_BOARD_INFO("menelaus", 0x72),
-		.irq = INT_24XX_SYS_NIRQ,
+		.irq = 7,
 		.platform_data = &n8x0_menelaus_platform_data,
 	},
 };
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e37ee67..cbf6fd5 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -292,7 +292,7 @@ static int __init omap4_panda_i2c_init(void)
 			TWL_COMMON_REGULATOR_V1V8 |
 			TWL_COMMON_REGULATOR_V2V1);
 	omap4_pmic_init("twl6030", &omap4_panda_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+			&twl6040_data, 119 + OMAP44XX_IRQ_GIC_START);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	/*
 	 * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 4c45109..abdb057 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -25,9 +25,11 @@
 #include <plat/mmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc.h>
-#include "common.h"
+#include <plat/serial.h>
+
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-nokia.h"
@@ -84,7 +86,7 @@ static struct twl4030_platform_data rm680_twl_data = {
 static void __init rm680_i2c_init(void)
 {
 	omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
-	omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+	omap_pmic_init(1, 2900, "twl5031", 7, &rm680_twl_data);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	omap_register_i2c_bus(3, 400, NULL, 0);
 }
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 06e44e4..93710b3 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -1047,7 +1047,7 @@ static int __init rx51_i2c_init(void)
 	rx51_twldata.vdac->constraints.apply_uV = true;
 	rx51_twldata.vdac->constraints.name = "VDAC";
 
-	omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+	omap_pmic_init(1, 2200, "twl5030", 7, &rx51_twldata);
 	omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
 			      ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index da4679d..5387cb8 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -20,9 +20,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/irqs.h>
-#include "common.h"
 #include <plat/usb.h>
+#include "common.h"
 
 static struct omap_musb_board_data musb_board_data = {
 	.set_phy_power	= ti81xx_musb_phy_power,
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index f64f441..f1100c2 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -19,6 +19,7 @@
 
 #include <plat/gpmc.h>
 #include <plat/gpmc-smsc911x.h>
+#include <plat/serial.h>
 
 #include <mach/board-zoom.h>
 
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index ae5d36b..406303d 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -25,11 +25,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/usb.h>
+#include <plat/serial.h>
 
 #include <mach/board-zoom.h>
 
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -279,7 +280,7 @@ static int __init omap_i2c_init(void)
 		codec_data->hs_extmute = 1;
 		codec_data->set_hs_extmute = zoom2_set_hs_extmute;
 	}
-	omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
+	omap_pmic_init(1, 2400, "twl5030", 7, &zoom_twldata);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	omap_register_i2c_bus(3, 400, NULL, 0);
 	return 0;
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f2a49a4..bc27569 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -28,7 +28,6 @@
 #include <linux/cpu_pm.h>
 
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b80073f..a4f5ce6 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,17 +20,16 @@
 #include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include "iomap.h"
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap4-keypad.h>
 
+#include "iomap.h"
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
@@ -435,13 +434,11 @@ static inline void omap_init_mcspi(void) {}
 
 static struct resource omap2_pmu_resource = {
 	.start	= 3,
-	.end	= 3,
 	.flags	= IORESOURCE_IRQ,
 };
 
 static struct resource omap3_pmu_resource = {
-	.start	= INT_34XX_BENCH_MPU_EMUL,
-	.end	= INT_34XX_BENCH_MPU_EMUL,
+	.start	= 3,
 	.flags	= IORESOURCE_IRQ,
 };
 
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 3f75ff0..e8ff2da 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
+#include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <plat/gpmc-smc91x.h>
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 39c30d9..bea55a2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,10 +26,13 @@
 #include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
-#include <plat/gpmc.h>
 
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
 #include <plat/sdrc.h>
 
+#include <mach/hardware.h>
+
 /* GPMC register offsets */
 #define GPMC_REVISION		0x00
 #define GPMC_SYSCONFIG		0x10
@@ -846,16 +849,16 @@ static int __init gpmc_init(void)
 			l = OMAP2420_GPMC_BASE;
 		else
 			l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
+		gpmc_irq = 20;
 	} else if (cpu_is_omap34xx()) {
 		ck = "gpmc_fck";
 		l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
+		gpmc_irq = 20;
 	} else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
 		/* Base address and irq number are same for OMAP4/5 */
 		ck = "gpmc_ck";
 		l = OMAP44XX_GPMC_BASE;
-		gpmc_irq = OMAP44XX_IRQ_GPMC;
+		gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
 	}
 
 	if (WARN_ON(!ck))
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4d2d981..ff6fc5b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,6 +33,8 @@
 #include <plat/multi.h>
 #include <plat/dma.h>
 
+#include <mach/hardware.h>
+
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6875be8..e032a73 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -16,8 +16,9 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+
+#include <plat/cpu.h>
 #include <plat/mailbox.h>
-#include <mach/irqs.h>
 
 #define MAILBOX_REVISION		0x000
 #define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 4ee08c6..4576708 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -18,7 +18,6 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
 #include <plat/dma.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/dsp-mcbsp.h>
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 1be8bcb..a8d957a 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -14,7 +14,6 @@
 #include <linux/platform_device.h>
 
 #include <plat/iommu.h>
-#include <plat/irqs.h>
 
 struct iommu_device {
 	resource_size_t base;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 05fdebf..95ee7dd 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -27,6 +27,7 @@
 
 #include <asm/hardware/gic.h>
 
+#include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
 #include <mach/omap-secure.h>
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c29dee9..c886325 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -16,15 +16,15 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/export.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 
-#include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
@@ -35,7 +35,6 @@
 #include "common.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
-#include <linux/export.h>
 
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b305d7f..8fdc676 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -13,7 +13,6 @@
  * XXX these should be marked initdata for multi-OMAP kernels
  */
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 79ac236..4a6bbfd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,7 +16,6 @@
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
@@ -25,6 +24,8 @@
 #include <plat/mmc.h>
 #include <plat/l3_2xxx.h>
 
+#include <plat/hardware.h>
+
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 102d76e..f19540a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -15,8 +15,6 @@
 #include <plat/common.h>
 #include <plat/hdq1w.h>
 
-#include <mach/irqs.h>
-
 #include "omap_hwmod_common_data.h"
 
 /* UART */
@@ -237,17 +235,17 @@ struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
 };
 
 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
-	{ .irq = INT_24XX_UART1_IRQ, },
+	{ .irq = 72, },
 	{ .irq = -1 }
 };
 
 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
-	{ .irq = INT_24XX_UART2_IRQ, },
+	{ .irq = 73, },
 	{ .irq = -1 }
 };
 
 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
-	{ .irq = INT_24XX_UART3_IRQ, },
+	{ .irq = 74, },
 	{ .irq = -1 }
 };
 
@@ -257,12 +255,12 @@ struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
 };
 
 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
-	{ .irq = INT_24XX_I2C1_IRQ, },
+	{ .irq = 56, },
 	{ .irq = -1 }
 };
 
 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
-	{ .irq = INT_24XX_I2C2_IRQ, },
+	{ .irq = 57, },
 	{ .irq = -1 }
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 44e4764..85c1259 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -15,8 +15,6 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/irqs.h>
-
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 15f617e..b9525d2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -20,7 +20,6 @@
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
@@ -30,11 +29,13 @@
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 
+#include <mach/hardware.h>
+#include <mach/am35xx.h>
+
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
-#include <mach/am35xx.h>
 
 /*
  * OMAP3xxx hardware module integration data
@@ -51,8 +52,8 @@
 
 /* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
-	{ .irq = INT_34XX_L3_DBG_IRQ },
-	{ .irq = INT_34XX_L3_APP_IRQ },
+	{ .irq = 9 },
+	{ .irq = 10 },
 	{ .irq = -1 }
 };
 
@@ -490,7 +491,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 
 /* UART4 */
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
-	{ .irq = INT_36XX_UART4_IRQ, },
+	{ .irq = 80, },
 	{ .irq = -1 }
 };
 
@@ -518,7 +519,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 };
 
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
-	{ .irq = INT_35XX_UART4_IRQ, },
+	{ .irq = 84, },
 	{ .irq = -1 }
 };
 
@@ -804,7 +805,7 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-	{ .irq = INT_34XX_I2C3_IRQ, },
+	{ .irq = 61, },
 	{ .irq = -1 }
 };
 
@@ -1585,7 +1586,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
 
 /* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
-	{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+	{ .name = "irq", .irq = 48 },
 	{ .irq = -1 }
 };
 
@@ -1773,7 +1774,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
 /* MMC/SD/SDIO2 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
-	{ .irq = INT_24XX_MMC2_IRQ, },
+	{ .irq = 86, },
 	{ .irq = -1 }
 };
 
@@ -3214,10 +3215,10 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
 };
 
 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
-	{ .name = "rxthresh",	.irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
-	{ .name = "rx_pulse",	.irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
-	{ .name = "tx_pulse",	.irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
-	{ .name = "misc_pulse",	.irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
+	{ .name = "rxthresh",	.irq = 67 },
+	{ .name = "rx_pulse",	.irq = 68 },
+	{ .name = "tx_pulse",	.irq = 69 },
+	{ .name = "misc_pulse",	.irq = 70 },
 	{ .irq = -1 }
 };
 
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index d15225f..f0992fd 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -28,6 +28,8 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 
+#include <plat/hardware.h>
+
 #include "omap_l3_noc.h"
 
 /*
@@ -190,7 +192,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev)
 			IRQF_DISABLED, "l3-dbg-irq", l3);
 	if (ret) {
 		pr_crit("L3: request_irq failed to register for 0x%x\n",
-						OMAP44XX_IRQ_L3_DBG);
+						9 + OMAP44XX_IRQ_GIC_START);
 		goto err3;
 	}
 
@@ -200,7 +202,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev)
 			IRQF_DISABLED, "l3-app-irq", l3);
 	if (ret) {
 		pr_crit("L3: request_irq failed to register for 0x%x\n",
-						OMAP44XX_IRQ_L3_APP);
+						10 + OMAP44XX_IRQ_GIC_START);
 		goto err4;
 	}
 
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d52651a..d0b4dc7 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -28,7 +28,9 @@
 #include <linux/err.h>
 #include <linux/usb.h>
 
+#include <plat/hardware.h>
 #include <plat/usb.h>
+
 #include "control.h"
 
 /* OMAP control module register for UTMI PHY */
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 2708a8b..8af6cd6 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -40,8 +40,6 @@
 #include <plat/sram.h>
 #include <plat/dma.h>
 
-#include <mach/irqs.h>
-
 #include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 053e24e..9c9d23c 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a0309de..9052383 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -20,7 +20,6 @@
 #include "common.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "vp.h"
 
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
 	.nr_regs		= 1,
 	.irqs			= omap3_prcm_irqs,
 	.nr_irqs		= ARRAY_SIZE(omap3_prcm_irqs),
-	.irq			= INT_34XX_PRCM_MPU_IRQ,
+	.irq			= 11,
 	.read_pending_irqs	= &omap3xxx_prm_read_pending_irqs,
 	.ocp_barrier		= &omap3xxx_prm_ocp_barrier,
 	.save_and_clear_irqen	= &omap3xxx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index bb727c2..df2cfe1 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -18,8 +18,8 @@
 #include <linux/io.h>
 
 #include <plat/cpu.h>
-#include <plat/irqs.h>
 #include <plat/prcm.h>
+#include <plat/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
@@ -40,7 +40,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
 	.nr_regs		= 2,
 	.irqs			= omap4_prcm_irqs,
 	.nr_irqs		= ARRAY_SIZE(omap4_prcm_irqs),
-	.irq			= OMAP44XX_IRQ_PRCM,
+	.irq			= 11 + OMAP44XX_IRQ_GIC_START,
 	.read_pending_irqs	= &omap44xx_prm_read_pending_irqs,
 	.ocp_barrier		= &omap44xx_prm_ocp_barrier,
 	.save_and_clear_irqen	= &omap44xx_prm_save_and_clear_irqen,
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 03b126d..6b4d332 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -26,7 +26,6 @@
 
 #include <plat/common.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 10f7f02..7345267 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -33,6 +33,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/serial.h>
 
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2ff6d41..e1f1d09 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -38,14 +38,17 @@
 #include <linux/slab.h>
 
 #include <asm/mach/time.h>
-#include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
-#include "common.h"
+
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
 #include "powerdomain.h"
 
 /* Parent clocks, eventually these will come from the clock framework */
@@ -373,8 +376,7 @@ OMAP_SYS_TIMER(3_am33xx)
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
-			      OMAP44XX_LOCAL_TWD_BASE,
-			      OMAP44XX_IRQ_LOCALTIMER);
+			      OMAP44XX_LOCAL_TWD_BASE, 29);
 #endif
 
 static void __init omap4_timer_init(void)
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index de47f17..81f9956 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -26,6 +26,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 
+#include <plat/hardware.h>
 #include <plat/i2c.h>
 #include <plat/usb.h>
 
@@ -83,7 +84,7 @@ void __init omap4_pmic_init(const char *pmic_type,
 	omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
 	strncpy(omap4_i2c1_board_info[0].type, pmic_type,
 		sizeof(omap4_i2c1_board_info[0].type));
-	omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
+	omap4_i2c1_board_info[0].irq = 7 + OMAP44XX_IRQ_GIC_START;
 	omap4_i2c1_board_info[0].platform_data = pmic_data;
 
 	/* TWL6040 audio IC part */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 8fe71cf..1ddea9f 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -1,8 +1,6 @@
 #ifndef __OMAP_PMIC_COMMON__
 #define __OMAP_PMIC_COMMON__
 
-#include <plat/irqs.h>
-
 #define TWL_COMMON_PDATA_USB		(1 << 0)
 #define TWL_COMMON_PDATA_BCI		(1 << 1)
 #define TWL_COMMON_PDATA_MADC		(1 << 2)
@@ -40,13 +38,13 @@ void omap_pmic_late_init(void);
 static inline void omap2_pmic_init(const char *pmic_type,
 				   struct twl4030_platform_data *pmic_data)
 {
-	omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+	omap_pmic_init(2, 2600, pmic_type, 7, pmic_data);
 }
 
 static inline void omap3_pmic_init(const char *pmic_type,
 				   struct twl4030_platform_data *pmic_data)
 {
-	omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+	omap_pmic_init(1, 2600, pmic_type, 7, pmic_data);
 }
 
 void omap4_pmic_init(const char *pmic_type,
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index dde8a11..14368c3 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -26,7 +26,6 @@
 #include <asm/io.h>
 
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index c4a5768..3f35e6c 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -27,7 +27,6 @@
 #include <linux/usb/musb.h>
 
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <mach/am35xx.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index c0d478e..5da9735 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -39,6 +39,7 @@
 #define IRQ_SIR_IRQ			0x0040
 #define OMAP44XX_GIC_DIST_BASE		0x48241000
 #define OMAP44XX_GIC_CPU_BASE		0x48240100
+#define OMAP44XX_IRQ_GIC_START		32
 #define OMAP44XX_SCU_BASE		0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE		0x48240600
 #define OMAP44XX_L2CACHE_BASE		0x48242000
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index ae05618..2e16627 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -18,6 +18,8 @@
 #include <linux/spinlock.h>
 
 #include "virt-dma.h"
+
+#include <plat/cpu.h>
 #include <plat/dma.h>
 
 struct omap_dmadev {
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 1c32afe..f462ff2 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -46,6 +46,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 
+#include <plat/cpu.h>
+
 #include "twl-core.h"
 
 /*
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 1b4725b..06134c9 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -37,13 +37,15 @@
 #include <linux/slab.h>
 #include <linux/regulator/consumer.h>
 
-#include <asm/mach/flash.h>
-#include <plat/gpmc.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/gpio.h>
+#include <asm/mach/flash.h>
 
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
 #include <plat/dma.h>
 
+#include <linux/platform_data/mtd-onenand-omap2.h>
+
 #define DRIVER_NAME "omap2-onenand"
 
 #define ONENAND_BUFRAM_SIZE	(1024 * 5)
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
index 8123f78..5b3f2fe 100644
--- a/drivers/tty/serial/8250/8250.c
+++ b/drivers/tty/serial/8250/8250.c
@@ -2336,7 +2336,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 			serial_port_out(port, UART_EFR, efr);
 	}
 
-#ifdef CONFIG_ARCH_OMAP
+#ifdef CONFIG_ARCH_OMAP1
 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
 	if (cpu_is_omap1510() && is_omap_port(up)) {
 		if (baud == 115200) {
@@ -2426,7 +2426,7 @@ static unsigned int serial8250_port_size(struct uart_8250_port *pt)
 {
 	if (pt->port.iotype == UPIO_AU)
 		return 0x1000;
-#ifdef CONFIG_ARCH_OMAP
+#ifdef CONFIG_ARCH_OMAP1
 	if (is_omap_port(pt))
 		return 0x16 << pt->port.regshift;
 #endif
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 5b289c5..ee9e296 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -37,6 +37,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 
 #include <video/omapdss.h>
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 08ec1a7..9e6ee5c 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -30,10 +30,12 @@
 #include <linux/platform_device.h>
 #include <linux/omapfb.h>
 
-#include <video/omapdss.h>
+#include <plat/cpu.h>
 #include <plat/vram.h>
 #include <plat/vrfb.h>
 
+#include <video/omapdss.h>
+
 #include "omapfb.h"
 
 #define MODULE_NAME     "omapfb"
diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index 4bc029d..bfdf7e0 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -24,9 +24,10 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-
 #include <linux/platform_data/dsp-mcbsp.h>
 
+#include <plat/cpu.h>
+
 #include "mcbsp.h"
 
 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index deeda47..ecee212b 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -32,6 +32,7 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <linux/platform_data/dsp-mcbsp.h>
 #include "mcbsp.h"
diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index f0feb06..b309941 100644
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -30,6 +30,7 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include "omap-pcm.h"
 



From tony at atomide.com  Thu Aug 30 20:52:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 30 Aug 2012 17:52:41 -0700
Subject: [PATCH 9/9] ARM: OMAP1: Move plat/irqs.h to mach/irqs.h
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <20120831005241.28732.63942.stgit@muffinssi.local>

This is now omap1 specific files.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/ams-delta-fiq-handler.S      |    1 
 arch/arm/mach-omap1/dma.c                        |    3 
 arch/arm/mach-omap1/include/mach/ams-delta-fiq.h |    2 
 arch/arm/mach-omap1/include/mach/irqs.h          |  267 ++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h           |  268 ----------------------
 5 files changed, 268 insertions(+), 273 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/irqs.h

diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index a051cb8..d2b6acc 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -18,6 +18,7 @@
 
 #include <plat/board-ams-delta.h>
 
+#include <mach/irqs.h>
 #include <mach/ams-delta-fiq.h>
 
 #include "iomap.h"
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 3ef7d52..b0b0f0f 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -27,7 +27,8 @@
 
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irqs.h>
+
+#include <mach/irqs.h>
 
 #define OMAP1_DMA_BASE			(0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT	17
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
index 23eed00..adb5e76 100644
--- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -14,8 +14,6 @@
 #ifndef __AMS_DELTA_FIQ_H
 #define __AMS_DELTA_FIQ_H
 
-#include <plat/irqs.h>
-
 /*
  * Interrupt number used for passing control from FIQ to IRQ.
  * IRQ12, described as reserved, has been selected.
diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/include/mach/irqs.h
index 9292fdc..729992d 100644
--- a/arch/arm/mach-omap1/include/mach/irqs.h
+++ b/arch/arm/mach-omap1/include/mach/irqs.h
@@ -1,5 +1,268 @@
 /*
- * arch/arm/mach-omap1/include/mach/irqs.h
+ *  arch/arm/plat-omap/include/mach/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony at atomide.com>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *	 are different.
  */
 
-#include <plat/irqs.h>
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_CAMERA		1
+#define INT_FIQ			3
+#define INT_RTDX		6
+#define INT_DSP_MMU_ABORT	7
+#define INT_HOST		8
+#define INT_ABORT		9
+#define INT_BRIDGE_PRIV		13
+#define INT_GPIO_BANK1		14
+#define INT_UART3		15
+#define INT_TIMER3		16
+#define INT_DMA_CH0_6		19
+#define INT_DMA_CH1_7		20
+#define INT_DMA_CH2_8		21
+#define INT_DMA_CH3		22
+#define INT_DMA_CH4		23
+#define INT_DMA_CH5		24
+#define INT_TIMER1		26
+#define INT_WD_TIMER		27
+#define INT_BRIDGE_PUB		28
+#define INT_TIMER2		30
+#define INT_LCD_CTRL		31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_IH2_IRQ	0
+#define INT_1510_RES2		2
+#define INT_1510_SPI_TX		4
+#define INT_1510_SPI_RX		5
+#define INT_1510_DSP_MAILBOX1	10
+#define INT_1510_DSP_MAILBOX2	11
+#define INT_1510_RES12		12
+#define INT_1510_LB_MMU		17
+#define INT_1510_RES18		18
+#define INT_1510_LOCAL_BUS	29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
+#define INT_1610_IH2_FIQ	2
+#define INT_1610_McBSP2_TX	4
+#define INT_1610_McBSP2_RX	5
+#define INT_1610_DSP_MAILBOX1	10
+#define INT_1610_DSP_MAILBOX2	11
+#define INT_1610_LCD_LINE	12
+#define INT_1610_GPTIMER1	17
+#define INT_1610_GPTIMER2	18
+#define INT_1610_SSR_FIFO_0	29
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
+ */
+#define INT_7XX_IH2_FIQ		0
+#define INT_7XX_IH2_IRQ		1
+#define INT_7XX_USB_NON_ISO	2
+#define INT_7XX_USB_ISO		3
+#define INT_7XX_ICR		4
+#define INT_7XX_EAC		5
+#define INT_7XX_GPIO_BANK1	6
+#define INT_7XX_GPIO_BANK2	7
+#define INT_7XX_GPIO_BANK3	8
+#define INT_7XX_McBSP2TX	10
+#define INT_7XX_McBSP2RX	11
+#define INT_7XX_McBSP2RX_OVF	12
+#define INT_7XX_LCD_LINE	14
+#define INT_7XX_GSM_PROTECT	15
+#define INT_7XX_TIMER3		16
+#define INT_7XX_GPIO_BANK5	17
+#define INT_7XX_GPIO_BANK6	18
+#define INT_7XX_SPGIO_WR	29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE		32
+
+#define INT_KEYBOARD		(1 + IH2_BASE)
+#define INT_uWireTX		(2 + IH2_BASE)
+#define INT_uWireRX		(3 + IH2_BASE)
+#define INT_I2C			(4 + IH2_BASE)
+#define INT_MPUIO		(5 + IH2_BASE)
+#define INT_USB_HHC_1		(6 + IH2_BASE)
+#define INT_McBSP3TX		(10 + IH2_BASE)
+#define INT_McBSP3RX		(11 + IH2_BASE)
+#define INT_McBSP1TX		(12 + IH2_BASE)
+#define INT_McBSP1RX		(13 + IH2_BASE)
+#define INT_UART1		(14 + IH2_BASE)
+#define INT_UART2		(15 + IH2_BASE)
+#define INT_BT_MCSI1TX		(16 + IH2_BASE)
+#define INT_BT_MCSI1RX		(17 + IH2_BASE)
+#define INT_SOSSI_MATCH		(19 + IH2_BASE)
+#define INT_USB_W2FC		(20 + IH2_BASE)
+#define INT_1WIRE		(21 + IH2_BASE)
+#define INT_OS_TIMER		(22 + IH2_BASE)
+#define INT_MMC			(23 + IH2_BASE)
+#define INT_GAUGE_32K		(24 + IH2_BASE)
+#define INT_RTC_TIMER		(25 + IH2_BASE)
+#define INT_RTC_ALARM		(26 + IH2_BASE)
+#define INT_MEM_STICK		(27 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_DSP_MMU	(28 + IH2_BASE)
+#define INT_1510_COM_SPI_RO	(31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC		(0 + IH2_BASE)
+#define INT_1610_USB_HHC_2	(7 + IH2_BASE)
+#define INT_1610_USB_OTG	(8 + IH2_BASE)
+#define INT_1610_SoSSI		(9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH	(19 + IH2_BASE)
+#define INT_1610_DSP_MMU	(28 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF	(31 + IH2_BASE)
+#define INT_1610_STI		(32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP	(33 + IH2_BASE)
+#define INT_1610_GPTIMER3	(34 + IH2_BASE)
+#define INT_1610_GPTIMER4	(35 + IH2_BASE)
+#define INT_1610_GPTIMER5	(36 + IH2_BASE)
+#define INT_1610_GPTIMER6	(37 + IH2_BASE)
+#define INT_1610_GPTIMER7	(38 + IH2_BASE)
+#define INT_1610_GPTIMER8	(39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2	(40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3	(41 + IH2_BASE)
+#define INT_1610_MMC2		(42 + IH2_BASE)
+#define INT_1610_CF		(43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ	(46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4	(48 + IH2_BASE)
+#define INT_1610_SPI		(49 + IH2_BASE)
+#define INT_1610_DMA_CH6	(53 + IH2_BASE)
+#define INT_1610_DMA_CH7	(54 + IH2_BASE)
+#define INT_1610_DMA_CH8	(55 + IH2_BASE)
+#define INT_1610_DMA_CH9	(56 + IH2_BASE)
+#define INT_1610_DMA_CH10	(57 + IH2_BASE)
+#define INT_1610_DMA_CH11	(58 + IH2_BASE)
+#define INT_1610_DMA_CH12	(59 + IH2_BASE)
+#define INT_1610_DMA_CH13	(60 + IH2_BASE)
+#define INT_1610_DMA_CH14	(61 + IH2_BASE)
+#define INT_1610_DMA_CH15	(62 + IH2_BASE)
+#define INT_1610_NAND		(63 + IH2_BASE)
+#define INT_1610_SHA1MD5	(91 + IH2_BASE)
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
+ */
+#define INT_7XX_HW_ERRORS	(0 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL	(1 + IH2_BASE)
+#define INT_7XX_CFCD		(2 + IH2_BASE)
+#define INT_7XX_CFIREQ		(3 + IH2_BASE)
+#define INT_7XX_I2C		(4 + IH2_BASE)
+#define INT_7XX_PCC		(5 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ	(6 + IH2_BASE)
+#define INT_7XX_SPI_100K_1	(7 + IH2_BASE)
+#define INT_7XX_SYREN_SPI	(8 + IH2_BASE)
+#define INT_7XX_VLYNQ		(9 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4	(10 + IH2_BASE)
+#define INT_7XX_McBSP1TX	(11 + IH2_BASE)
+#define INT_7XX_McBSP1RX	(12 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF	(13 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1	(15 + IH2_BASE)
+#define INT_7XX_MCSI		(16 + IH2_BASE)
+#define INT_7XX_uWireTX		(17 + IH2_BASE)
+#define INT_7XX_uWireRX		(18 + IH2_BASE)
+#define INT_7XX_SMC_CD		(19 + IH2_BASE)
+#define INT_7XX_SMC_IREQ	(20 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE	(21 + IH2_BASE)
+#define INT_7XX_TIMER32K	(22 + IH2_BASE)
+#define INT_7XX_MMC_SDIO	(23 + IH2_BASE)
+#define INT_7XX_UPLD		(24 + IH2_BASE)
+#define INT_7XX_USB_HHC_1	(27 + IH2_BASE)
+#define INT_7XX_USB_HHC_2	(28 + IH2_BASE)
+#define INT_7XX_USB_GENI	(29 + IH2_BASE)
+#define INT_7XX_USB_OTG		(30 + IH2_BASE)
+#define INT_7XX_CAMERA_IF	(31 + IH2_BASE)
+#define INT_7XX_RNG		(32 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN	(34 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD	(35 + IH2_BASE)
+#define INT_7XX_SHA1_MD5	(36 + IH2_BASE)
+#define INT_7XX_SPI_100K_2	(37 + IH2_BASE)
+#define INT_7XX_RNG_IDLE	(38 + IH2_BASE)
+#define INT_7XX_MPUIO		(39 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF	(40 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING	(42 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC	(43 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ	(46 + IH2_BASE)
+#define INT_7XX_DMA_CH6		(53 + IH2_BASE)
+#define INT_7XX_DMA_CH7		(54 + IH2_BASE)
+#define INT_7XX_DMA_CH8		(55 + IH2_BASE)
+#define INT_7XX_DMA_CH9		(56 + IH2_BASE)
+#define INT_7XX_DMA_CH10	(57 + IH2_BASE)
+#define INT_7XX_DMA_CH11	(58 + IH2_BASE)
+#define INT_7XX_DMA_CH12	(59 + IH2_BASE)
+#define INT_7XX_DMA_CH13	(60 + IH2_BASE)
+#define INT_7XX_DMA_CH14	(61 + IH2_BASE)
+#define INT_7XX_DMA_CH15	(62 + IH2_BASE)
+#define INT_7XX_NAND		(63 + IH2_BASE)
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES	192
+#define IH_GPIO_BASE		(128 + IH2_BASE)
+#define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define OMAP_IRQ_END		(IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define	OMAP_FPGA_IRQ_BASE	(OMAP_IRQ_END)
+#ifdef	CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS	24
+#else
+#define OMAP_FPGA_NR_IRQS	0
+#endif
+#define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+#define NR_IRQS			OMAP_FPGA_IRQ_END
+
+#define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
+
+#include <mach/hardware.h>
+
+#ifdef CONFIG_FIQ
+#define FIQ_START		1024
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644
index 729992d..0000000
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irqs.h
- *
- *  Copyright (C) Greg Lonnon 2001
- *  Updated for OMAP-1610 by Tony Lindgren <tony at atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- *	 are different.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA		1
-#define INT_FIQ			3
-#define INT_RTDX		6
-#define INT_DSP_MMU_ABORT	7
-#define INT_HOST		8
-#define INT_ABORT		9
-#define INT_BRIDGE_PRIV		13
-#define INT_GPIO_BANK1		14
-#define INT_UART3		15
-#define INT_TIMER3		16
-#define INT_DMA_CH0_6		19
-#define INT_DMA_CH1_7		20
-#define INT_DMA_CH2_8		21
-#define INT_DMA_CH3		22
-#define INT_DMA_CH4		23
-#define INT_DMA_CH5		24
-#define INT_TIMER1		26
-#define INT_WD_TIMER		27
-#define INT_BRIDGE_PUB		28
-#define INT_TIMER2		30
-#define INT_LCD_CTRL		31
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ	0
-#define INT_1510_RES2		2
-#define INT_1510_SPI_TX		4
-#define INT_1510_SPI_RX		5
-#define INT_1510_DSP_MAILBOX1	10
-#define INT_1510_DSP_MAILBOX2	11
-#define INT_1510_RES12		12
-#define INT_1510_LB_MMU		17
-#define INT_1510_RES18		18
-#define INT_1510_LOCAL_BUS	29
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
-#define INT_1610_IH2_FIQ	2
-#define INT_1610_McBSP2_TX	4
-#define INT_1610_McBSP2_RX	5
-#define INT_1610_DSP_MAILBOX1	10
-#define INT_1610_DSP_MAILBOX2	11
-#define INT_1610_LCD_LINE	12
-#define INT_1610_GPTIMER1	17
-#define INT_1610_GPTIMER2	18
-#define INT_1610_SSR_FIFO_0	29
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 1
- */
-#define INT_7XX_IH2_FIQ		0
-#define INT_7XX_IH2_IRQ		1
-#define INT_7XX_USB_NON_ISO	2
-#define INT_7XX_USB_ISO		3
-#define INT_7XX_ICR		4
-#define INT_7XX_EAC		5
-#define INT_7XX_GPIO_BANK1	6
-#define INT_7XX_GPIO_BANK2	7
-#define INT_7XX_GPIO_BANK3	8
-#define INT_7XX_McBSP2TX	10
-#define INT_7XX_McBSP2RX	11
-#define INT_7XX_McBSP2RX_OVF	12
-#define INT_7XX_LCD_LINE	14
-#define INT_7XX_GSM_PROTECT	15
-#define INT_7XX_TIMER3		16
-#define INT_7XX_GPIO_BANK5	17
-#define INT_7XX_GPIO_BANK6	18
-#define INT_7XX_SPGIO_WR	29
-
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE		32
-
-#define INT_KEYBOARD		(1 + IH2_BASE)
-#define INT_uWireTX		(2 + IH2_BASE)
-#define INT_uWireRX		(3 + IH2_BASE)
-#define INT_I2C			(4 + IH2_BASE)
-#define INT_MPUIO		(5 + IH2_BASE)
-#define INT_USB_HHC_1		(6 + IH2_BASE)
-#define INT_McBSP3TX		(10 + IH2_BASE)
-#define INT_McBSP3RX		(11 + IH2_BASE)
-#define INT_McBSP1TX		(12 + IH2_BASE)
-#define INT_McBSP1RX		(13 + IH2_BASE)
-#define INT_UART1		(14 + IH2_BASE)
-#define INT_UART2		(15 + IH2_BASE)
-#define INT_BT_MCSI1TX		(16 + IH2_BASE)
-#define INT_BT_MCSI1RX		(17 + IH2_BASE)
-#define INT_SOSSI_MATCH		(19 + IH2_BASE)
-#define INT_USB_W2FC		(20 + IH2_BASE)
-#define INT_1WIRE		(21 + IH2_BASE)
-#define INT_OS_TIMER		(22 + IH2_BASE)
-#define INT_MMC			(23 + IH2_BASE)
-#define INT_GAUGE_32K		(24 + IH2_BASE)
-#define INT_RTC_TIMER		(25 + IH2_BASE)
-#define INT_RTC_ALARM		(26 + IH2_BASE)
-#define INT_MEM_STICK		(27 + IH2_BASE)
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU	(28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO	(31 + IH2_BASE)
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC		(0 + IH2_BASE)
-#define INT_1610_USB_HHC_2	(7 + IH2_BASE)
-#define INT_1610_USB_OTG	(8 + IH2_BASE)
-#define INT_1610_SoSSI		(9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH	(19 + IH2_BASE)
-#define INT_1610_DSP_MMU	(28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF	(31 + IH2_BASE)
-#define INT_1610_STI		(32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP	(33 + IH2_BASE)
-#define INT_1610_GPTIMER3	(34 + IH2_BASE)
-#define INT_1610_GPTIMER4	(35 + IH2_BASE)
-#define INT_1610_GPTIMER5	(36 + IH2_BASE)
-#define INT_1610_GPTIMER6	(37 + IH2_BASE)
-#define INT_1610_GPTIMER7	(38 + IH2_BASE)
-#define INT_1610_GPTIMER8	(39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2	(40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3	(41 + IH2_BASE)
-#define INT_1610_MMC2		(42 + IH2_BASE)
-#define INT_1610_CF		(43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ	(46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4	(48 + IH2_BASE)
-#define INT_1610_SPI		(49 + IH2_BASE)
-#define INT_1610_DMA_CH6	(53 + IH2_BASE)
-#define INT_1610_DMA_CH7	(54 + IH2_BASE)
-#define INT_1610_DMA_CH8	(55 + IH2_BASE)
-#define INT_1610_DMA_CH9	(56 + IH2_BASE)
-#define INT_1610_DMA_CH10	(57 + IH2_BASE)
-#define INT_1610_DMA_CH11	(58 + IH2_BASE)
-#define INT_1610_DMA_CH12	(59 + IH2_BASE)
-#define INT_1610_DMA_CH13	(60 + IH2_BASE)
-#define INT_1610_DMA_CH14	(61 + IH2_BASE)
-#define INT_1610_DMA_CH15	(62 + IH2_BASE)
-#define INT_1610_NAND		(63 + IH2_BASE)
-#define INT_1610_SHA1MD5	(91 + IH2_BASE)
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 2
- */
-#define INT_7XX_HW_ERRORS	(0 + IH2_BASE)
-#define INT_7XX_NFIQ_PWR_FAIL	(1 + IH2_BASE)
-#define INT_7XX_CFCD		(2 + IH2_BASE)
-#define INT_7XX_CFIREQ		(3 + IH2_BASE)
-#define INT_7XX_I2C		(4 + IH2_BASE)
-#define INT_7XX_PCC		(5 + IH2_BASE)
-#define INT_7XX_MPU_EXT_NIRQ	(6 + IH2_BASE)
-#define INT_7XX_SPI_100K_1	(7 + IH2_BASE)
-#define INT_7XX_SYREN_SPI	(8 + IH2_BASE)
-#define INT_7XX_VLYNQ		(9 + IH2_BASE)
-#define INT_7XX_GPIO_BANK4	(10 + IH2_BASE)
-#define INT_7XX_McBSP1TX	(11 + IH2_BASE)
-#define INT_7XX_McBSP1RX	(12 + IH2_BASE)
-#define INT_7XX_McBSP1RX_OF	(13 + IH2_BASE)
-#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_7XX_UART_MODEM_1	(15 + IH2_BASE)
-#define INT_7XX_MCSI		(16 + IH2_BASE)
-#define INT_7XX_uWireTX		(17 + IH2_BASE)
-#define INT_7XX_uWireRX		(18 + IH2_BASE)
-#define INT_7XX_SMC_CD		(19 + IH2_BASE)
-#define INT_7XX_SMC_IREQ	(20 + IH2_BASE)
-#define INT_7XX_HDQ_1WIRE	(21 + IH2_BASE)
-#define INT_7XX_TIMER32K	(22 + IH2_BASE)
-#define INT_7XX_MMC_SDIO	(23 + IH2_BASE)
-#define INT_7XX_UPLD		(24 + IH2_BASE)
-#define INT_7XX_USB_HHC_1	(27 + IH2_BASE)
-#define INT_7XX_USB_HHC_2	(28 + IH2_BASE)
-#define INT_7XX_USB_GENI	(29 + IH2_BASE)
-#define INT_7XX_USB_OTG		(30 + IH2_BASE)
-#define INT_7XX_CAMERA_IF	(31 + IH2_BASE)
-#define INT_7XX_RNG		(32 + IH2_BASE)
-#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_7XX_DBB_RF_EN	(34 + IH2_BASE)
-#define INT_7XX_MPUIO_KEYPAD	(35 + IH2_BASE)
-#define INT_7XX_SHA1_MD5	(36 + IH2_BASE)
-#define INT_7XX_SPI_100K_2	(37 + IH2_BASE)
-#define INT_7XX_RNG_IDLE	(38 + IH2_BASE)
-#define INT_7XX_MPUIO		(39 + IH2_BASE)
-#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF	(40 + IH2_BASE)
-#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_7XX_LLPC_OE_RISING	(42 + IH2_BASE)
-#define INT_7XX_LLPC_VSYNC	(43 + IH2_BASE)
-#define INT_7XX_WAKE_UP_REQ	(46 + IH2_BASE)
-#define INT_7XX_DMA_CH6		(53 + IH2_BASE)
-#define INT_7XX_DMA_CH7		(54 + IH2_BASE)
-#define INT_7XX_DMA_CH8		(55 + IH2_BASE)
-#define INT_7XX_DMA_CH9		(56 + IH2_BASE)
-#define INT_7XX_DMA_CH10	(57 + IH2_BASE)
-#define INT_7XX_DMA_CH11	(58 + IH2_BASE)
-#define INT_7XX_DMA_CH12	(59 + IH2_BASE)
-#define INT_7XX_DMA_CH13	(60 + IH2_BASE)
-#define INT_7XX_DMA_CH14	(61 + IH2_BASE)
-#define INT_7XX_DMA_CH15	(62 + IH2_BASE)
-#define INT_7XX_NAND		(63 + IH2_BASE)
-
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES	192
-#define IH_GPIO_BASE		(128 + IH2_BASE)
-#define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END		(IH_MPUIO_BASE + 16)
-
-/* External FPGA handles interrupts on Innovator boards */
-#define	OMAP_FPGA_IRQ_BASE	(OMAP_IRQ_END)
-#ifdef	CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS	24
-#else
-#define OMAP_FPGA_NR_IRQS	0
-#endif
-#define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
-#define NR_IRQS			OMAP_FPGA_IRQ_END
-
-#define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))
-
-#include <mach/hardware.h>
-
-#ifdef CONFIG_FIQ
-#define FIQ_START		1024
-#endif
-
-#endif



From zhangfei.gao at gmail.com  Thu Aug 30 21:10:17 2012
From: zhangfei.gao at gmail.com (zhangfei gao)
Date: Fri, 31 Aug 2012 09:10:17 +0800
Subject: [PATCH v4 0/2] dmaengine: add support mmp-pdma
In-Reply-To: <1346364840.15463.1.camel@vkoul-mobl4>
References: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
 <1346364840.15463.1.camel@vkoul-mobl4>
Message-ID: <CAMj5BkiF6NGwfbHBgS52EHwTzb+z6x60hSDaqLtQXgk7bB8jUg@mail.gmail.com>

On Fri, Aug 31, 2012 at 6:14 AM, Vinod Koul <vkoul at infradead.org> wrote:
> On Thu, 2012-08-16 at 10:23 +0800, Zhangfei Gao wrote:
>
> What tree is this based on? I do not find
> Documentation/devicetree/bindings/dma/mmp-dma.txt in my tree or linus's
> tree??
>

The mmp-dma.txt is created by [PATCH v3 1/4] dmaengine: mmp-pdma support.
The patch set based on linux-next, July 13.

Thanks


From horms at verge.net.au  Thu Aug 30 21:28:15 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:15 +0900
Subject: [PATCH 04/11] ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-5-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

PENCx is Power Enable Control pin for USB.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c          | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b07ad31..7597a37 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
 	GPIO_FN_A19,
 
 	/* IPSR0 */
-	GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+	GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
 	GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
 	GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
 	GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index d14c9b0..9fac32e4 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
 	FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
 	FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
 	FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
-	FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+	FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 	FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 
 	/* GPSR5 */
@@ -176,7 +176,7 @@ enum {
 	FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 	FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 	FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
-	FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+	FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 	FN_SCIF_CLK, FN_TCLK0_C,
 
 	/* IPSR1 */
@@ -447,7 +447,7 @@ enum {
 	A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 	BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 	ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-	PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+	USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 	SCIF_CLK_MARK, TCLK0_C_MARK,
 
 	EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(A18_MARK, FN_A18),
 	PINMUX_DATA(A19_MARK, FN_A19),
 
-	PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+	PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 	PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
 	GPIO_FN(A19),
 
 	/* IPSR0 */
-	GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+	GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
 	GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
 	GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
 	GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		GP_4_30_FN, FN_IP8_18,
 		GP_4_29_FN, FN_IP8_17_16,
 		GP_4_28_FN, FN_IP0_2_0,
-		GP_4_27_FN, FN_PENC1,
-		GP_4_26_FN, FN_PENC0,
+		GP_4_27_FN, FN_USB_PENC1,
+		GP_4_26_FN, FN_USB_PENC0,
 		GP_4_25_FN, FN_IP8_15_12,
 		GP_4_24_FN, FN_IP8_11_8,
 		GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 		FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 		/* IP0_2_0 [3] */
-		FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+		FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 		FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
 	},
 	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:13 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:13 +0900
Subject: [PATCH 02/11] marzen: add SDHI0 support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-3-git-send-email-horms@verge.net.au>

From: Phil Edworthy <phil.edworthy at renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  4 +--
 arch/arm/mach-shmobile/board-marzen.c | 52 ++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 864f9a5..bf42ad2 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -71,12 +71,12 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_SSB=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 3a528cf..dec3ffc 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,6 +30,8 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -39,6 +41,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
 	REGULATOR_SUPPLY("vddvario", "smsc911x"),
@@ -75,13 +83,45 @@ static struct platform_device eth_device = {
 	.num_resources	= ARRAY_SIZE(smsc911x_resources),
 };
 
+static struct resource sdhi0_resources[] = {
+	[0] = {
+		.name	= "sdhi0",
+		.start	= 0xffe4c000,
+		.end	= 0xffe4c0ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(104),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct sh_mobile_sdhi_info sdhi0_platform_data = {
+	.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
+	.tmio_caps = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct platform_device sdhi0_device = {
+	.name = "sh_mobile_sdhi",
+	.num_resources = ARRAY_SIZE(sdhi0_resources),
+	.resource = sdhi0_resources,
+	.id = 0,
+	.dev = {
+		.platform_data = &sdhi0_platform_data,
+	}
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
+	&sdhi0_device,
 };
 
 static void __init marzen_init(void)
 {
-	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+				ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+	regulator_register_fixed(0, dummy_supplies,
+				ARRAY_SIZE(dummy_supplies));
 
 	r8a7779_pinmux_init();
 
@@ -97,6 +137,16 @@ static void __init marzen_init(void)
 	gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
 	gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
 
+	/* SD0 (CN20) */
+	gpio_request(GPIO_FN_SD0_CLK, NULL);
+	gpio_request(GPIO_FN_SD0_CMD, NULL);
+	gpio_request(GPIO_FN_SD0_DAT0, NULL);
+	gpio_request(GPIO_FN_SD0_DAT1, NULL);
+	gpio_request(GPIO_FN_SD0_DAT2, NULL);
+	gpio_request(GPIO_FN_SD0_DAT3, NULL);
+	gpio_request(GPIO_FN_SD0_CD, NULL);
+	gpio_request(GPIO_FN_SD0_WP, NULL);
+
 	r8a7779_add_standard_devices();
 	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:12 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:12 +0900
Subject: [PATCH 01/11] r8a7779: add SDHI clock support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-2-git-send-email-horms@verge.net.au>

From: Phil Edworthy <phil.edworthy at renesas.com>

Signed-off-by: Phil Edworthy <phil.edworthy at renesas.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c..3cafb6a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = {
 				      0x0300, CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015, MSTP014,
 	MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+	CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
 };
 
 void __init r8a7779_clock_init(void)
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:11 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:11 +0900
Subject: [GIT PULL v2] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7
Message-ID: <1346376502-12114-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following enhancements to the Marzen board
and r8a7779 SoC by Phil Edworthy, Morimoto-san and myself for 3.7.

* This pull requests superceedes the previous request,
  "[GIT PULL v2] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7"
  which I made earlier today. The difference to that request is that
  I have pushed one more patch. There was no rebase.

* This pull request is based on the usb-next branch of Greg KH's USB tree,
  git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git,
  which is based on v3.6-rc3.

  This is to satisfy compile-time dependencies.
  Please let me know if you would like this handled a different way.

----------------------------------------------------------------
The following changes since commit a7bdf7fa33127bf08eb0810698bca607a9462df4:

  Merge v3.6-rc3 into usb-next (2012-08-27 07:15:30 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git marzen

for you to fetch changes up to 3553395437f2ac42a73255a0ffac09efc9acf5c4:

  ARM: shmobile: marzen: add USB OHCI driver support (2012-08-31 09:41:44 +0900)

----------------------------------------------------------------
Kuninori Morimoto (8):
      ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx
      ARM: shmobile: r8a7779: add USB common phy initializer
      ARM: shmobile: r8a7779: add USB EHCI clock support
      ARM: shmobile: r8a7779: add USB OHCI clock support
      ARM: shmobile: marzen: add USB EHCI driver support
      ARM: shmobile: marzen: fixup regulator id for smsc911x
      ARM: shmobile: marzen: enable thermal sensor
      ARM: shmobile: marzen: add USB OHCI driver support

Phil Edworthy (2):
      r8a7779: add SDHI clock support
      marzen: add SDHI0 support

Simon Horman (1):
      ARM: mach-shmobile: marzen: defconfig update

 arch/arm/configs/marzen_defconfig             |  30 ++--
 arch/arm/mach-shmobile/Kconfig                |   2 +
 arch/arm/mach-shmobile/board-marzen.c         | 213 +++++++++++++++++++++++++-
 arch/arm/mach-shmobile/clock-r8a7779.c        |  18 ++-
 arch/arm/mach-shmobile/include/mach/common.h  |   1 +
 arch/arm/mach-shmobile/include/mach/r8a7779.h |   2 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c          |  16 +-
 arch/arm/mach-shmobile/setup-r8a7779.c        |  93 +++++++++++
 8 files changed, 355 insertions(+), 20 deletions(-)


From horms at verge.net.au  Thu Aug 30 21:28:14 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:14 +0900
Subject: [PATCH 03/11] ARM: mach-shmobile: marzen: defconfig update
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-4-git-send-email-horms@verge.net.au>

Update marzen defconfig
* Enable MMC Block device as SDHI hw is now supported.
* Default to NFS root, this is consistent with many other
  shmobile boards
* Enable UNIX which is required by udevd

Other changes are noise due to using make savedefconfig
to create the new defconfig.

Cc: Phil Edworthy <phil.edworthy at renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index bf42ad2..cd2dc21 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -1,13 +1,14 @@
 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
 CONFIG_EXPERIMENTAL=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_MACH_MARZEN=y
@@ -21,7 +22,6 @@ CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_NO_HZ=y
 CONFIG_SMP=y
 # CONFIG_ARM_CPU_TOPOLOGY is not set
 CONFIG_AEABI=y
@@ -29,13 +29,16 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
+CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -69,16 +72,16 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_SSB=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_INFO_REDUCED=y
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:18 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:18 +0900
Subject: [PATCH 07/11] ARM: shmobile: r8a7779: add USB OHCI clock support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-8-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

ohci-platform driver require these clocks

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1d8842b..7c62e3d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -158,7 +158,9 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
 	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+	CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
 	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+	CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:17 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:17 +0900
Subject: [PATCH 06/11] ARM: shmobile: r8a7779: add USB EHCI clock support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-7-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

ehci-platform driver require these clocks

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 3cafb6a..1d8842b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,6 +87,7 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
+	MSTP101, MSTP100,
 	MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 	MSTP016, MSTP015, MSTP014,
 	MSTP_NR };
@@ -96,6 +97,8 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
 	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
 	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+	[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
+	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -154,6 +157,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
 	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+	CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
+	CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:20 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:20 +0900
Subject: [PATCH 09/11] ARM: shmobile: marzen: fixup regulator id for smsc911x
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-10-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

regulator id = 0 is used for sh_mobile_sdhi.
smsc911x's regulator can use id = 1

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 0249c0e..91e81e9 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -196,7 +196,7 @@ static void __init marzen_init(void)
 {
 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 				ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-	regulator_register_fixed(0, dummy_supplies,
+	regulator_register_fixed(1, dummy_supplies,
 				ARRAY_SIZE(dummy_supplies));
 
 	r8a7779_pinmux_init();
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:21 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:21 +0900
Subject: [PATCH 10/11] ARM: shmobile: marzen: enable thermal sensor
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-11-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Marzen board can measure its thermal by this patch.
	cat /sys/class/thermal/thermal_zoneX/temp

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  2 ++
 arch/arm/mach-shmobile/board-marzen.c | 16 ++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 61d1c55..c30ea5e 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -73,6 +73,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
 CONFIG_SSB=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 91e81e9..eb0a05a 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -113,9 +113,25 @@ static struct platform_device sdhi0_device = {
 	}
 };
 
+/* Thermal */
+static struct resource thermal_resources[] = {
+	[0] = {
+		.start		= 0xFFC48000,
+		.end		= 0xFFC48038 - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device thermal_device = {
+	.name		= "rcar_thermal",
+	.resource	= thermal_resources,
+	.num_resources	= ARRAY_SIZE(thermal_resources),
+};
+
 static struct platform_device *marzen_devices[] __initdata = {
 	&eth_device,
 	&sdhi0_device,
+	&thermal_device,
 };
 
 /* USB */
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:22 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:22 +0900
Subject: [PATCH 11/11] ARM: shmobile: marzen: add USB OHCI driver support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-12-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch supports CN21/CN22 USB 1.x (port 0/1/2),
and enable input event on defconfig

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  5 +--
 arch/arm/mach-shmobile/Kconfig        |  1 +
 arch/arm/mach-shmobile/board-marzen.c | 57 +++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index c30ea5e..30f2714 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -61,9 +61,8 @@ CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -81,6 +80,8 @@ CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_UIO=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8937d69..66befbc 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -42,6 +42,7 @@ config ARCH_R8A7779
 	select ARM_GIC
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select USB_ARCH_HAS_EHCI
+	select USB_ARCH_HAS_OHCI
 
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index eb0a05a..30c794b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -33,6 +33,7 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
 #include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
@@ -203,9 +204,65 @@ static struct platform_device ehci1_device = {
 	.resource	= ehci1_resources,
 };
 
+static struct usb_ohci_pdata ohcix_pdata = {
+	.power_on	= xhci_power_on,
+	.power_off	= xhci_power_off,
+	.power_suspend	= xhci_power_off,
+};
+
+static struct resource ohci0_resources[] = {
+	[0] = {
+		.start	= 0xffe70400,
+		.end	= 0xffe70800 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(44),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ohci0_device = {
+	.name	= "ohci-platform",
+	.id	= 0,
+	.dev	= {
+		.dma_mask		= &ohci0_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ohcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ohci0_resources),
+	.resource	= ohci0_resources,
+};
+
+static struct resource ohci1_resources[] = {
+	[0] = {
+		.start	= 0xfff70400,
+		.end	= 0xfff70800 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(45),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ohci1_device = {
+	.name	= "ohci-platform",
+	.id	= 1,
+	.dev	= {
+		.dma_mask		= &ohci1_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ohcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ohci1_resources),
+	.resource	= ohci1_resources,
+};
+
 static struct platform_device *marzen_usb_devices[] __initdata = {
 	&ehci0_device,
 	&ehci1_device,
+	&ohci0_device,
+	&ohci1_device,
 };
 
 static void __init marzen_init(void)
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:19 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:19 +0900
Subject: [PATCH 08/11] ARM: shmobile: marzen: add USB EHCI driver support
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-9-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch supports CN21/CN22 USB 2.0 (port 0/1/2),
and enable USB momery on defconfig

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/configs/marzen_defconfig     |  6 +++
 arch/arm/mach-shmobile/Kconfig        |  1 +
 arch/arm/mach-shmobile/board-marzen.c | 88 +++++++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+)

diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index cd2dc21..61d1c55 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -75,6 +77,10 @@ CONFIG_SSB=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4cacc2d..8937d69 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,7 @@ config ARCH_R8A7779
 	select SH_CLK_CPG
 	select ARM_GIC
 	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select USB_ARCH_HAS_EHCI
 
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index dec3ffc..0249c0e 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -32,6 +32,8 @@
 #include <linux/smsc911x.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -116,6 +118,80 @@ static struct platform_device *marzen_devices[] __initdata = {
 	&sdhi0_device,
 };
 
+/* USB */
+static int xhci_power_on(struct platform_device *pdev)
+{
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_get_sync(&pdev->dev);
+
+	return 0;
+}
+
+static void xhci_power_off(struct platform_device *pdev)
+{
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static struct usb_ehci_pdata ehcix_pdata = {
+	.power_on	= xhci_power_on,
+	.power_off	= xhci_power_off,
+	.power_suspend	= xhci_power_off,
+};
+
+static struct resource ehci0_resources[] = {
+	[0] = {
+		.start	= 0xffe70000,
+		.end	= 0xffe70400 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(44),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ehci0_device = {
+	.name	= "ehci-platform",
+	.id	= 0,
+	.dev	= {
+		.dma_mask		= &ehci0_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ehcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ehci0_resources),
+	.resource	= ehci0_resources,
+};
+
+static struct resource ehci1_resources[] = {
+	[0] = {
+		.start	= 0xfff70000,
+		.end	= 0xfff70400 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= gic_spi(45),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ehci1_device = {
+	.name	= "ehci-platform",
+	.id	= 1,
+	.dev	= {
+		.dma_mask		= &ehci1_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &ehcix_pdata,
+	},
+	.num_resources	= ARRAY_SIZE(ehci1_resources),
+	.resource	= ehci1_resources,
+};
+
+static struct platform_device *marzen_usb_devices[] __initdata = {
+	&ehci0_device,
+	&ehci1_device,
+};
+
 static void __init marzen_init(void)
 {
 	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -147,8 +223,20 @@ static void __init marzen_init(void)
 	gpio_request(GPIO_FN_SD0_CD, NULL);
 	gpio_request(GPIO_FN_SD0_WP, NULL);
 
+	/* USB (CN21) */
+	gpio_request(GPIO_FN_USB_OVC0, NULL);
+	gpio_request(GPIO_FN_USB_OVC1, NULL);
+	gpio_request(GPIO_FN_USB_OVC2, NULL);
+
+	/* USB (CN22) */
+	gpio_request(GPIO_FN_USB_PENC2, NULL);
+
 	r8a7779_add_standard_devices();
 	platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
+
+	if (0 == r8a7779_usb_phy_init(0))
+		platform_add_devices(marzen_usb_devices,
+				     ARRAY_SIZE(marzen_usb_devices));
 }
 
 MACHINE_START(MARZEN, "marzen")
-- 
1.7.10.2.484.gcd07cc5



From horms at verge.net.au  Thu Aug 30 21:28:16 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 10:28:16 +0900
Subject: [PATCH 05/11] ARM: shmobile: r8a7779: add USB common phy initializer
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <1346376502-12114-6-git-send-email-horms@verge.net.au>

From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

This patch adds common USB phy ports initializer for r8a7779.

The note is that each USB IP have own MSTP clock bit,
and common USB phy port doesn't have MSTP clock,
but this USB phy needs USB clock.
Each USB driver / platform should keep USB MSTP clock somehow.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/common.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c       | 93 ++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)

diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 45e61da..00b2eb5 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -78,6 +78,7 @@ extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7740_meram_workaround(void);
+extern int r8a7779_usb_phy_init(u32 usbpctrl0);
 
 extern unsigned int r8a7779_get_core_count(void);
 extern int r8a7779_platform_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index e98e46f..17fdd1f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
+#include <linux/pm_runtime.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
@@ -243,6 +244,98 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
 static struct platform_device *r8a7779_late_devices[] __initdata = {
 };
 
+/* USBH common register */
+#define USBPCTRL0	0x0800
+#define USBPCTRL1	0x0804
+#define USBST		0x0808
+#define USBEH0		0x080C
+#define USBOH0		0x081C
+#define USBCTL0		0x0858
+#define EIIBC1		0x0094
+#define EIIBC2		0x009C
+
+#ifdef CONFIG_ARCH_SUPPORTS_BIG_ENDIAN
+# define xHCI_ENDIAN "BIG"
+# define xHCI_NO_SWAP 0x00000003
+#else
+# define xHCI_ENDIAN "LITTLE"
+# define xHCI_NO_SWAP 0x00000000
+#endif
+
+/*
+ * USB initial/install operation.
+ *
+ * This function setup USB phy.
+ * The used value and setting order came from
+ * [USB :: Initial setting] on datasheet.
+ */
+int __init r8a7779_usb_phy_init(u32 usbpctrl0)
+{
+	void __iomem *reg0, *reg1;
+	int i;
+	u32 val;
+
+	reg0 = ioremap_nocache(0xffe70000, 0x900);
+	reg1 = ioremap_nocache(0xfff70000, 0x900);
+
+	/*----------------------------------------*
+	 * USB phy start-up
+	 *----------------------------------------*/
+
+	/* (1) USB-PHY standby release */
+	iowrite32(0x00000001, (reg0 + USBPCTRL1));
+
+	/* (2) start USB-PHY internal PLL */
+	iowrite32(0x00000003, (reg0 + USBPCTRL1));
+
+	/* (3) USB module status check */
+	for (i = 0; i < 1024; i++) {
+		udelay(10);
+		val = ioread32(reg0 + USBST);
+		if (0xc0000000 == val)
+			goto usb_module_is_working;
+	}
+	pr_err("USB module not ready\n");
+	return -EIO;
+
+usb_module_is_working:
+	/* (4) USB-PHY reset clear */
+	iowrite32(0x00000007, (reg0 + USBPCTRL1));
+
+	/* set platform specific port settings */
+	iowrite32(usbpctrl0, (reg0 + USBPCTRL0));
+
+	/*----------------------------------------*
+	 * EHCI IP Internal Buffer Setting
+	 *----------------------------------------*/
+
+	/* (1) EHCI IP internal buffer setting */
+	iowrite32(0x00ff0040, (reg0 + EIIBC1));
+	iowrite32(0x00ff0040, (reg1 + EIIBC1));
+
+	/* (2) EHCI IP internal buffer enable */
+	iowrite32(0x00000001, (reg0 + EIIBC2));
+	iowrite32(0x00000001, (reg1 + EIIBC2));
+
+	/*----------------------------------------*
+	 * Bus alignment settings
+	 *----------------------------------------*/
+
+	/* (1) EHCI bus alignment */
+	iowrite32(xHCI_NO_SWAP, (reg0 + USBEH0));
+
+	/* (1) OHCI bus alignment */
+	iowrite32(xHCI_NO_SWAP, (reg0 + USBOH0));
+
+	pr_info("USB xHCI alignment was initialized as %s endian no swap\n",
+		xHCI_ENDIAN);
+
+	iounmap(reg0);
+	iounmap(reg1);
+
+	return 0;
+}
+
 void __init r8a7779_add_standard_devices(void)
 {
 #ifdef CONFIG_CACHE_L2X0
-- 
1.7.10.2.484.gcd07cc5



From robherring2 at gmail.com  Thu Aug 30 23:00:28 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 30 Aug 2012 22:00:28 -0500
Subject: [PATCH 03/10] serial: atmel: add explict mach/gpio.h include
In-Reply-To: <20120829233705.GT18957@n2100.arm.linux.org.uk>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-4-git-send-email-robherring2@gmail.com>
 <20120829233705.GT18957@n2100.arm.linux.org.uk>
Message-ID: <504028CC.9020202@gmail.com>

On 08/29/2012 06:37 PM, Russell King - ARM Linux wrote:
> On Wed, Aug 29, 2012 at 05:31:29PM -0500, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> In preparation to remove implicit inclusion of mach/gpio.h, add explicit
>> include of mach/gpio.h.
> 
> Definitely NAK.
> 
> What is in the Atmel mach/gpio.h has hardly anything to do with the
> gpio subsystem (it's more a private gpio implementation).  It should
> be renamed as such to make it clear (and so it doesn't trigger my
> sanity filtering.)

Jean-Christophe, Does your gpio clean-up address this?

Rob



From thomas.abraham at linaro.org  Thu Aug 30 23:48:26 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 09:18:26 +0530
Subject: [PATCH 1/6] ARM: dts: Move parts common to Exynos4 from
 Exynos4210.dtsi to Exynos4.dtsi
In-Reply-To: <1346311903-15920-2-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
 <1346311903-15920-2-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwSC4USH0XLU9vfchEux_ncDf-iudPY3g4SXRp_mF9Ub8w@mail.gmail.com>

Hi Tomasz,

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> Most definitions from Exynos4210.dtsi can be applied for other SoCs from
> Exynos4 line as well, so move the common part into separate file that
> can be included by dtsi files of other Exynos4 SoCs (as well as current
> Exynos4210.dtsi).
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/boot/dts/exynos4.dtsi    | 402 ++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4210.dtsi | 377 +----------------------------------
>  2 files changed, 403 insertions(+), 376 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos4.dtsi

A similar patch was submitted by Dongjin Kim
<dongjin.kim at agreeyamobility.net> as well.
[PATCH v2] arm/dts: exynos4: Add DTS files derived from common Exynos4

Few comments are inlined below.

>
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> new file mode 100644
> index 0000000..5e99503
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -0,0 +1,402 @@
> +/*
> + * Samsung's Exynos4 SoC series common device tree source
> + *
> + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + * Copyright (c) 2010-2011 Linaro Ltd.
> + *             www.linaro.org
> + *
> + * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
> + * SoCs from Exynos4 series can include this file and provide values for SoCs
> + * specfic bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
> + * nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +       interrupt-parent = <&gic>;
> +
> +       aliases {
> +               spi0 = &spi_0;
> +               spi1 = &spi_1;
> +               spi2 = &spi_2;
> +       };
> +
> +       gic:interrupt-controller at 10490000 {
> +               compatible = "arm,cortex-a9-gic";
> +               #interrupt-cells = <3>;
> +               interrupt-controller;
> +               cpu-offset = <0x8000>;

The value of cpu-offset is different for Exynos4210 and Exynos4412
(not sure if it is different on Exynos4212 as well). Since
exynos4.dtsi will be included in the other Exynos4 specific dtsi
files, cpu-offset property can be removed from here and included in
SoC specific dtsi files.

> +               reg = <0x10490000 0x1000>, <0x10480000 0x100>;
> +       };
> +
> +       combiner:interrupt-controller at 10440000 {
> +               compatible = "samsung,exynos4210-combiner";
> +               #interrupt-cells = <2>;
> +               interrupt-controller;
> +               reg = <0x10440000 0x1000>;
> +               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> +                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> +                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> +                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
> +       };

Similarly, the number of interrupts generated by the combiner is also
specific to the Exynos4 SoC. So the interrupts property could also be
moved into SoC specific dtsi files.

> +
> +       watchdog at 10060000 {
> +               compatible = "samsung,s3c2410-wdt";
> +               reg = <0x10060000 0x100>;
> +               interrupts = <0 43 0>;
> +       };
> +
> +       rtc at 10070000 {
> +               compatible = "samsung,s3c6410-rtc";
> +               reg = <0x10070000 0x100>;
> +               interrupts = <0 44 0>, <0 45 0>;
> +       };
> +
> +       keypad at 100A0000 {
> +               compatible = "samsung,s5pv210-keypad";
> +               reg = <0x100A0000 0x100>;
> +               interrupts = <0 109 0>;
> +       };
> +
> +       sdhci at 12510000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12510000 0x100>;
> +               interrupts = <0 73 0>;
> +       };
> +
> +       sdhci at 12520000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12520000 0x100>;
> +               interrupts = <0 74 0>;
> +       };
> +
> +       sdhci at 12530000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12530000 0x100>;
> +               interrupts = <0 75 0>;
> +       };
> +
> +       sdhci at 12540000 {
> +               compatible = "samsung,exynos4210-sdhci";
> +               reg = <0x12540000 0x100>;
> +               interrupts = <0 76 0>;
> +       };
> +
> +       serial at 13800000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13800000 0x100>;
> +               interrupts = <0 52 0>;
> +       };
> +
> +       serial at 13810000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13810000 0x100>;
> +               interrupts = <0 53 0>;
> +       };
> +
> +       serial at 13820000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13820000 0x100>;
> +               interrupts = <0 54 0>;
> +       };
> +
> +       serial at 13830000 {
> +               compatible = "samsung,exynos4210-uart";
> +               reg = <0x13830000 0x100>;
> +               interrupts = <0 55 0>;
> +       };
> +
> +       i2c at 13860000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13860000 0x100>;
> +               interrupts = <0 58 0>;
> +       };
> +
> +       i2c at 13870000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13870000 0x100>;
> +               interrupts = <0 59 0>;
> +       };
> +
> +       i2c at 13880000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13880000 0x100>;
> +               interrupts = <0 60 0>;
> +       };
> +
> +       i2c at 13890000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x13890000 0x100>;
> +               interrupts = <0 61 0>;
> +       };
> +
> +       i2c at 138A0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138A0000 0x100>;
> +               interrupts = <0 62 0>;
> +       };
> +
> +       i2c at 138B0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138B0000 0x100>;
> +               interrupts = <0 63 0>;
> +       };
> +
> +       i2c at 138C0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138C0000 0x100>;
> +               interrupts = <0 64 0>;
> +       };
> +
> +       i2c at 138D0000 {
> +               compatible = "samsung,s3c2440-i2c";
> +               reg = <0x138D0000 0x100>;
> +               interrupts = <0 65 0>;
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13920000 0x100>;
> +               interrupts = <0 66 0>;
> +               tx-dma-channel = <&pdma0 7>; /* preliminary */
> +               rx-dma-channel = <&pdma0 6>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13930000 0x100>;
> +               interrupts = <0 67 0>;
> +               tx-dma-channel = <&pdma1 7>; /* preliminary */
> +               rx-dma-channel = <&pdma1 6>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               compatible = "samsung,exynos4210-spi";
> +               reg = <0x13940000 0x100>;
> +               interrupts = <0 68 0>;
> +               tx-dma-channel = <&pdma0 9>; /* preliminary */
> +               rx-dma-channel = <&pdma0 8>; /* preliminary */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
> +
> +       amba {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "arm,amba-bus";
> +               interrupt-parent = <&gic>;
> +               ranges;
> +
> +               pdma0: pdma at 12680000 {
> +                       compatible = "arm,pl330", "arm,primecell";
> +                       reg = <0x12680000 0x1000>;
> +                       interrupts = <0 35 0>;
> +               };
> +
> +               pdma1: pdma at 12690000 {
> +                       compatible = "arm,pl330", "arm,primecell";
> +                       reg = <0x12690000 0x1000>;
> +                       interrupts = <0 36 0>;
> +               };
> +       };
> +
> +       gpio-controllers {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               gpio-controller;
> +               ranges;

Should we just retain the gpio nodes in exynos4210.dtsi file itself
for now. If we manage to get the pinctrl driver support for exynos4210
and exynos4412 merged, these gpio nodes would anyway be removed. And
since there are differences in gpio banks in Exynos4 SoC's, maybe we
could just leave these in exynos4210.dtsi file for now.

> +
> +               gpa0: gpio-controller at 11400000 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400000 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpa1: gpio-controller at 11400020 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400020 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpb: gpio-controller at 11400040 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400040 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpc0: gpio-controller at 11400060 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400060 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpc1: gpio-controller at 11400080 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400080 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpd0: gpio-controller at 114000A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114000A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpd1: gpio-controller at 114000C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114000C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf0: gpio-controller at 11400180 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11400180 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf1: gpio-controller at 114001A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf2: gpio-controller at 114001C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpf3: gpio-controller at 114001E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x114001E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk0: gpio-controller at 11000040 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000040 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk1: gpio-controller at 11000060 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000060 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk2: gpio-controller at 11000080 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000080 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpk3: gpio-controller at 110000A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl0: gpio-controller at 110000C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl1: gpio-controller at 110000E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110000E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpl2: gpio-controller at 11000100 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000100 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy0: gpio-controller at 11000120 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000120 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy1: gpio-controller at 11000140 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000140 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy2: gpio-controller at 11000160 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000160 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy3: gpio-controller at 11000180 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000180 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy4: gpio-controller at 110001A0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001A0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy5: gpio-controller at 110001C0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001C0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpy6: gpio-controller at 110001E0 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x110001E0 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx0: gpio-controller at 11000C00 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C00 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx1: gpio-controller at 11000C20 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C20 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx2: gpio-controller at 11000C40 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C40 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpx3: gpio-controller at 11000C60 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x11000C60 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +
> +               gpz: gpio-controller at 03860000 {
> +                       compatible = "samsung,exynos4-gpio";
> +                       reg = <0x03860000 0x20>;
> +                       #gpio-cells = <4>;
> +               };
> +       };
> +};
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
> index 02891fe..4672367 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -19,249 +19,12 @@
>   * published by the Free Software Foundation.
>  */
>
> -/include/ "skeleton.dtsi"
> +/include/ "exynos4.dtsi"
>
>  / {
>         compatible = "samsung,exynos4210";
> -       interrupt-parent = <&gic>;
> -
> -       aliases {
> -               spi0 = &spi_0;
> -               spi1 = &spi_1;
> -               spi2 = &spi_2;
> -       };
> -
> -       gic:interrupt-controller at 10490000 {
> -               compatible = "arm,cortex-a9-gic";
> -               #interrupt-cells = <3>;
> -               interrupt-controller;
> -               cpu-offset = <0x8000>;
> -               reg = <0x10490000 0x1000>, <0x10480000 0x100>;
> -       };
> -
> -       combiner:interrupt-controller at 10440000 {
> -               compatible = "samsung,exynos4210-combiner";
> -               #interrupt-cells = <2>;
> -               interrupt-controller;
> -               reg = <0x10440000 0x1000>;
> -               interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
> -                            <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
> -                            <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
> -                            <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
> -       };
> -
> -       watchdog at 10060000 {
> -               compatible = "samsung,s3c2410-wdt";
> -               reg = <0x10060000 0x100>;
> -               interrupts = <0 43 0>;
> -       };
> -
> -       rtc at 10070000 {
> -               compatible = "samsung,s3c6410-rtc";
> -               reg = <0x10070000 0x100>;
> -               interrupts = <0 44 0>, <0 45 0>;
> -       };
> -
> -       keypad at 100A0000 {
> -               compatible = "samsung,s5pv210-keypad";
> -               reg = <0x100A0000 0x100>;
> -               interrupts = <0 109 0>;
> -       };
> -
> -       sdhci at 12510000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12510000 0x100>;
> -               interrupts = <0 73 0>;
> -       };
> -
> -       sdhci at 12520000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12520000 0x100>;
> -               interrupts = <0 74 0>;
> -       };
> -
> -       sdhci at 12530000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12530000 0x100>;
> -               interrupts = <0 75 0>;
> -       };
> -
> -       sdhci at 12540000 {
> -               compatible = "samsung,exynos4210-sdhci";
> -               reg = <0x12540000 0x100>;
> -               interrupts = <0 76 0>;
> -       };
> -
> -       serial at 13800000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13800000 0x100>;
> -               interrupts = <0 52 0>;
> -       };
> -
> -       serial at 13810000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13810000 0x100>;
> -               interrupts = <0 53 0>;
> -       };
> -
> -       serial at 13820000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13820000 0x100>;
> -               interrupts = <0 54 0>;
> -       };
> -
> -       serial at 13830000 {
> -               compatible = "samsung,exynos4210-uart";
> -               reg = <0x13830000 0x100>;
> -               interrupts = <0 55 0>;
> -       };
> -
> -       i2c at 13860000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13860000 0x100>;
> -               interrupts = <0 58 0>;
> -       };
> -
> -       i2c at 13870000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13870000 0x100>;
> -               interrupts = <0 59 0>;
> -       };
> -
> -       i2c at 13880000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13880000 0x100>;
> -               interrupts = <0 60 0>;
> -       };
> -
> -       i2c at 13890000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x13890000 0x100>;
> -               interrupts = <0 61 0>;
> -       };
> -
> -       i2c at 138A0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138A0000 0x100>;
> -               interrupts = <0 62 0>;
> -       };
> -
> -       i2c at 138B0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138B0000 0x100>;
> -               interrupts = <0 63 0>;
> -       };
> -
> -       i2c at 138C0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138C0000 0x100>;
> -               interrupts = <0 64 0>;
> -       };
> -
> -       i2c at 138D0000 {
> -               compatible = "samsung,s3c2440-i2c";
> -               reg = <0x138D0000 0x100>;
> -               interrupts = <0 65 0>;
> -       };
> -
> -       spi_0: spi at 13920000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13920000 0x100>;
> -               interrupts = <0 66 0>;
> -               tx-dma-channel = <&pdma0 7>; /* preliminary */
> -               rx-dma-channel = <&pdma0 6>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       spi_1: spi at 13930000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13930000 0x100>;
> -               interrupts = <0 67 0>;
> -               tx-dma-channel = <&pdma1 7>; /* preliminary */
> -               rx-dma-channel = <&pdma1 6>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       spi_2: spi at 13940000 {
> -               compatible = "samsung,exynos4210-spi";
> -               reg = <0x13940000 0x100>;
> -               interrupts = <0 68 0>;
> -               tx-dma-channel = <&pdma0 9>; /* preliminary */
> -               rx-dma-channel = <&pdma0 8>; /* preliminary */
> -               #address-cells = <1>;
> -               #size-cells = <0>;
> -       };
> -
> -       amba {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               compatible = "arm,amba-bus";
> -               interrupt-parent = <&gic>;
> -               ranges;
> -
> -               pdma0: pdma at 12680000 {
> -                       compatible = "arm,pl330", "arm,primecell";
> -                       reg = <0x12680000 0x1000>;
> -                       interrupts = <0 35 0>;
> -               };
> -
> -               pdma1: pdma at 12690000 {
> -                       compatible = "arm,pl330", "arm,primecell";
> -                       reg = <0x12690000 0x1000>;
> -                       interrupts = <0 36 0>;
> -               };
> -       };
>
>         gpio-controllers {
> -               #address-cells = <1>;
> -               #size-cells = <1>;
> -               gpio-controller;
> -               ranges;
> -
> -               gpa0: gpio-controller at 11400000 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400000 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpa1: gpio-controller at 11400020 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400020 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpb: gpio-controller at 11400040 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400040 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpc0: gpio-controller at 11400060 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400060 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpc1: gpio-controller at 11400080 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400080 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpd0: gpio-controller at 114000A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114000A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpd1: gpio-controller at 114000C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114000C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
>                 gpe0: gpio-controller at 114000E0 {
>                         compatible = "samsung,exynos4-gpio";
>                         reg = <0x114000E0 0x20>;
> @@ -292,30 +55,6 @@
>                         #gpio-cells = <4>;
>                 };
>
> -               gpf0: gpio-controller at 11400180 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11400180 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf1: gpio-controller at 114001A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf2: gpio-controller at 114001C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpf3: gpio-controller at 114001E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x114001E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
>                 gpj0: gpio-controller at 11000000 {
>                         compatible = "samsung,exynos4-gpio";
>                         reg = <0x11000000 0x20>;
> @@ -327,119 +66,5 @@
>                         reg = <0x11000020 0x20>;
>                         #gpio-cells = <4>;
>                 };
> -
> -               gpk0: gpio-controller at 11000040 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000040 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk1: gpio-controller at 11000060 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000060 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk2: gpio-controller at 11000080 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000080 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpk3: gpio-controller at 110000A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl0: gpio-controller at 110000C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl1: gpio-controller at 110000E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110000E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpl2: gpio-controller at 11000100 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000100 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy0: gpio-controller at 11000120 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000120 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy1: gpio-controller at 11000140 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000140 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy2: gpio-controller at 11000160 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000160 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy3: gpio-controller at 11000180 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000180 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy4: gpio-controller at 110001A0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001A0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy5: gpio-controller at 110001C0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001C0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpy6: gpio-controller at 110001E0 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x110001E0 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx0: gpio-controller at 11000C00 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C00 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx1: gpio-controller at 11000C20 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C20 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx2: gpio-controller at 11000C40 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C40 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpx3: gpio-controller at 11000C60 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x11000C60 0x20>;
> -                       #gpio-cells = <4>;
> -               };
> -
> -               gpz: gpio-controller at 03860000 {
> -                       compatible = "samsung,exynos4-gpio";
> -                       reg = <0x03860000 0x20>;
> -                       #gpio-cells = <4>;
> -               };
>         };
>  };
> --
> 1.7.12
>

While we are at it, should we mark the nodes in exynos4.dtsi and
exynos4210.dtsi as "disabled". The board dts files will have to
explicitly "enable" those nodes which it uses.

Apart from these minor comments, the rest of the changes looks fine.

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From thomas.abraham at linaro.org  Thu Aug 30 23:51:05 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 09:21:05 +0530
Subject: [PATCH 2/6] ARM: EXYNOS: exynos4-dt: Use exynos4 prefix instead
 of exynos4210
In-Reply-To: <1346311903-15920-3-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
 <1346311903-15920-3-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwTcAjgqLgp0tLSu-Tms1JEAk0WMjYC-Gx3YK1JVOm4VFQ@mail.gmail.com>

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> Since mach-exynos4-dt.c is also going to be used for other SoCs from Exynos4
> line, rename internal structures and functions to use exynos4_ prefix, instead
> of exynos4210_.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/mach-exynos4-dt.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From thomas.abraham at linaro.org  Thu Aug 30 23:53:40 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 09:23:40 +0530
Subject: [PATCH 3/6] ARM: Exynos4: dts: Specify address and size cells for
 i2c controllers
In-Reply-To: <1346311903-15920-4-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
 <1346311903-15920-4-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwT7RQrQhqw1GXcFxnucLa1OZzEdHX2GWZ92=-3D6_Rr0g@mail.gmail.com>

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/boot/dts/exynos4.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>

[...]


From thomas.abraham at linaro.org  Thu Aug 30 23:59:42 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 09:29:42 +0530
Subject: [PATCH 4/6] ARM: Exynos4: Add OF compatibility lookups for
 Exynos4 i2c adapters
In-Reply-To: <1346311903-15920-5-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
 <1346311903-15920-5-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwT+diyXX0O2WOJ3=yFMJwEXLbb30rmcYfbomjaFEQmOuQ@mail.gmail.com>

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/mach-exynos4-dt.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
> index 8dad4ec..0391c84 100644
> --- a/arch/arm/mach-exynos/mach-exynos4-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
> @@ -61,6 +61,22 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
>                                 "exynos4210-spi.1", NULL),
>         OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
>                                 "exynos4210-spi.2", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
> +                               "s3c2440-i2c.0", NULL),

i2c0 lookup information is already in this list. So the above line
should not be included in this patch.

> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
> +                               "s3c2440-i2c.1", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
> +                               "s3c2440-i2c.2", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
> +                               "s3c2440-i2c.3", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
> +                               "s3c2440-i2c.4", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
> +                               "s3c2440-i2c.5", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
> +                               "s3c2440-i2c.6", NULL),
> +       OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
> +                               "s3c2440-i2c.7", NULL),
>         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
>         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
>         {},
> --
> 1.7.12
>

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From plagnioj at jcrosoft.com  Fri Aug 31 00:12:09 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 Aug 2012 06:12:09 +0200
Subject: [PATCH 03/10] serial: atmel: add explict mach/gpio.h include
In-Reply-To: <1346279496-26286-4-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-4-git-send-email-robherring2@gmail.com>
Message-ID: <20120831041209.GD7629@game.jcrosoft.org>

On 17:31 Wed 29 Aug     , Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove implicit inclusion of mach/gpio.h, add explicit
> include of mach/gpio.h.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Alan Cox <alan at linux.intel.com>
no you do not fix the right way

we need to use the gpio lig in this driver

Best Regards,
J.


From thomas.abraham at linaro.org  Fri Aug 31 00:24:20 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 09:54:20 +0530
Subject: [PATCH 6/6] ARM: Exynos: Add basic dts file for Samsung Trats
 board
In-Reply-To: <1346311903-15920-7-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
 <1346311903-15920-7-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwSPfEk7fkcR=vP0GmSe924BJPNwoO=1CaSXX3zUFWwBoQ@mail.gmail.com>

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> This commit adds basic device tree for Exynos4210-based Trats board.
>
> Currently it provides support for eMMC over sdhci and MAX8997 PMIC.
>
> Signed-off-by: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/boot/dts/exynos4210-trats.dts | 287 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/Makefile.boot     |   2 +-
>  2 files changed, 288 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/exynos4210-trats.dts
>
> diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
> new file mode 100644
> index 0000000..a9cd2d0
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos4210-trats.dts
> @@ -0,0 +1,287 @@
> +/*
> + * Samsung's Exynos4210 based Trats board device tree source
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com
> + *
> + * Device tree source file for Samsung's Trats board which is based on
> + * Samsung's Exynos4210 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos4210.dtsi"
> +
> +/ {
> +       model = "Samsung Trats based on Exynos4210";
> +       compatible = "samsung,trats", "samsung,exynos4210";
> +
> +       memory {
> +               reg =  <0x40000000 0x20000000
> +                       0x60000000 0x20000000>;
> +       };
> +
> +       chosen {
> +               bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
> +       };
> +
> +       wakeup_eint: interrupt-controller-wakeup-eint {
> +               compatible = "samsung,exynos4210-wakeup-eint";
> +               reg = <0x11000000 0x1000>;
> +               #interrupt-cells = <2>;
> +               interrupt-controller;
> +               interrupts =    <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
> +                               <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
> +                               <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
> +                               <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
> +                               <0 32 0>;
> +       };

The external wakeup node should be in the exynos4.dtsi file since this
is common across all Exynos4 SoC's. Besides, the device tree support
patches for wakeup-interrupts is not being pursed anymore, since it is
now handled in pinctrl driver itself. So it would be better not to
include this node.

> +
> +       vemmc_reg: voltage-regulator at 0 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "VMEM_VDD_2.8V";
> +               regulator-min-microvolt = <2800000>;
> +               regulator-max-microvolt = <2800000>;
> +               gpio = <&gpk0 2 1 0 0>;
> +       };
> +
> +       sdhci_emmc: sdhci at 12510000 {
> +               bus-width = <8>;
> +               non-removable;
> +               gpios = <&gpk0 0 2 0 3>,
> +                       <&gpk0 1 2 0 3>,
> +                       <&gpk0 3 2 2 3>,
> +                       <&gpk0 4 2 2 3>,
> +                       <&gpk0 5 2 2 3>,
> +                       <&gpk0 6 2 2 3>,
> +                       <&gpk1 3 3 3 3>,
> +                       <&gpk1 4 3 3 3>,
> +                       <&gpk1 5 3 3 3>,
> +                       <&gpk1 6 3 3 3>;
> +               vmmc-supply = &vemmc_reg;
> +       };
> +
> +       i2c at 138B0000 {
> +               samsung,i2c-sda-delay = <100>;
> +               samsung,i2c-slave-addr = <0x10>;
> +               samsung,i2c-max-bus-freq = <100000>;
> +               gpios = <&gpb 6 3 3 0>,
> +                       <&gpb 7 3 3 0>;
> +
> +               max8997_pmic at 66 {
> +                       compatible = "maxim,max8997-pmic";
> +                       interrupt-parent = <&wakeup_eint>;
> +
> +                       reg = <0x66>;
> +                       interrupts = <4 0>, <3 0>;
> +
> +                       max8997,pmic-buck1-uses-gpio-dvs;
> +                       max8997,pmic-buck2-uses-gpio-dvs;
> +                       max8997,pmic-buck5-uses-gpio-dvs;
> +
> +                       max8997,pmic-ignore-gpiodvs-side-effect;
> +                       max8997,pmic-buck125-default-dvs-idx = <0>;
> +
> +                       max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>,
> +                                                        <&gpx0 6 1 0 0>,
> +                                                        <&gpl0 0 1 0 0>;
> +
> +                       max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
> +                                                        <1250000>, <1200000>,
> +                                                        <1150000>, <1100000>,
> +                                                        <1000000>, <950000>;
> +
> +                       max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
> +                                                        <950000>,  <900000>,
> +                                                        <1100000>, <1000000>,
> +                                                        <950000>,  <900000>;
> +
> +                       max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
> +                                                        <1200000>, <1200000>,
> +                                                        <1200000>, <1200000>,
> +                                                        <1200000>, <1200000>;
> +
> +                       regulators {
> +                               valive_reg: LDO2 {
> +                                    regulator-name = "VALIVE_1.1V_C210";
> +                                    regulator-min-microvolt = <1100000>;
> +                                    regulator-max-microvolt = <1100000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vusb_reg: LDO3 {
> +                                    regulator-name = "VUSB_1.1V_C210";
> +                                    regulator-min-microvolt = <1100000>;
> +                                    regulator-max-microvolt = <1100000>;
> +                               };
> +
> +                               vmipi_reg: LDO4 {
> +                                    regulator-name = "VMIPI_1.8V";
> +                                    regulator-min-microvolt = <1800000>;
> +                                    regulator-max-microvolt = <1800000>;
> +                               };
> +
> +                               vpda_reg: LDO6 {
> +                                    regulator-name = "VCC_1.8V_PDA";
> +                                    regulator-min-microvolt = <1800000>;
> +                                    regulator-max-microvolt = <1800000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vcam_reg: LDO7 {
> +                                    regulator-name = "CAM_ISP_1.8V";
> +                                    regulator-min-microvolt = <1800000>;
> +                                    regulator-max-microvolt = <1800000>;
> +                               };
> +
> +                               vusbdac_reg: LDO8 {
> +                                    regulator-name = "VUSB/VDAC_3.3V_C210";
> +                                    regulator-min-microvolt = <3300000>;
> +                                    regulator-max-microvolt = <3300000>;
> +                               };
> +
> +                               vccpda_reg: LDO9 {
> +                                    regulator-name = "VCC_2.8V_PDA";
> +                                    regulator-min-microvolt = <2800000>;
> +                                    regulator-max-microvolt = <2800000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vpll_reg: LDO10 {
> +                                    regulator-name = "VPLL_1.1V_C210";
> +                                    regulator-min-microvolt = <1100000>;
> +                                    regulator-max-microvolt = <1100000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vcclcd_reg: LDO13 {
> +                                    regulator-name = "VCC_3.3V_LCD";
> +                                    regulator-min-microvolt = <3300000>;
> +                                    regulator-max-microvolt = <3300000>;
> +                               };
> +
> +                               vlcd_reg: LDO15 {
> +                                    regulator-name = "VLCD_2.2V";
> +                                    regulator-min-microvolt = <2200000>;
> +                                    regulator-max-microvolt = <2200000>;
> +                               };
> +
> +                               camsensor_reg: LDO16 {
> +                                    regulator-name = "CAM_SENSOR_IO_1.8V";
> +                                    regulator-min-microvolt = <1800000>;
> +                                    regulator-max-microvolt = <1800000>;
> +                               };
> +
> +                               vddq_reg: LDO21 {
> +                                    regulator-name = "VDDQ_M1M2_1.2V";
> +                                    regulator-min-microvolt = <1200000>;
> +                                    regulator-max-microvolt = <1200000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               varm_breg: BUCK1 {
> +                                    regulator-name = "VARM_1.2V_C210";
> +                                    regulator-min-microvolt = <900000>;
> +                                    regulator-max-microvolt = <1350000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vint_breg: BUCK2 {
> +                                    regulator-name = "VINT_1.1V_C210";
> +                                    regulator-min-microvolt = <900000>;
> +                                    regulator-max-microvolt = <1100000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               camisp_breg: BUCK4 {
> +                                    regulator-name = "CAM_ISP_CORE_1.2V";
> +                                    regulator-min-microvolt = <1200000>;
> +                                    regulator-max-microvolt = <1200000>;
> +                               };
> +
> +                               vmem_breg: BUCK5 {
> +                                    regulator-name = "VMEM_1.2V_C210";
> +                                    regulator-min-microvolt = <1200000>;
> +                                    regulator-max-microvolt = <1200000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               vccsub_breg: BUCK7 {
> +                                    regulator-name = "VCC_SUB_2.0V";
> +                                    regulator-min-microvolt = <2000000>;
> +                                    regulator-max-microvolt = <2000000>;
> +                                    regulator-always-on;
> +                               };
> +
> +                               safe1_sreg: ESAFEOUT1 {
> +                                    regulator-name = "SAFEOUT1";
> +                                    regulator-always-on;
> +                               };
> +
> +                               safe2_sreg: ESAFEOUT2 {
> +                                    regulator-name = "SAFEOUT2";
> +                                    regulator-boot-on;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       keypad at 100A0000 {
> +               status = "disabled";
> +       };
> +
> +       sdhci at 12520000 {
> +               status = "disabled";
> +       };
> +
> +       sdhci at 12530000 {
> +               status = "disabled";
> +       };
> +
> +       sdhci at 12540000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 13860000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 13870000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 13880000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 13890000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 138A0000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 138C0000 {
> +               status = "disabled";
> +       };
> +
> +       i2c at 138D0000 {
> +               status = "disabled";
> +       };
> +
> +       spi_0: spi at 13920000 {
> +               status = "disabled";
> +       };
> +
> +       spi_1: spi at 13930000 {
> +               status = "disabled";
> +       };
> +
> +       spi_2: spi at 13940000 {
> +               status = "disabled";
> +       };
> +};

If we choose to mark the nodes in dtsi files as "disabled" then we can
avoid these here.

> diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
> index 31bd181..a79d999 100644
> --- a/arch/arm/mach-exynos/Makefile.boot
> +++ b/arch/arm/mach-exynos/Makefile.boot
> @@ -1,5 +1,5 @@
>     zreladdr-y  += 0x40008000
>  params_phys-y  := 0x40000100
>
> -dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb
> +dtb-$(CONFIG_MACH_EXYNOS4_DT) += exynos4210-origen.dtb exynos4210-smdkv310.dtb exynos4210-trats.dtb
>  dtb-$(CONFIG_MACH_EXYNOS5_DT) += exynos5250-smdk5250.dtb
> --
> 1.7.12
>

The rest of the additions looks fine.

Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>


From dgreid at chromium.org  Fri Aug 31 00:37:34 2012
From: dgreid at chromium.org (Dylan Reid)
Date: Thu, 30 Aug 2012 21:37:34 -0700
Subject: [PATCH] ASoC: samsung dma - Don't indicate support for pause/resume.
Message-ID: <1346387854-22222-1-git-send-email-dgreid@chromium.org>

The pause and resume operations indicate that the stream can be
un-paused/resumed from the exact location they were paused/suspended.
This is not true for this driver, the pause and suspend triggers share
the same code path with stop, they flush all pending DMA transfers.
This drops all pending samples.  The pause_release/resume triggers are
the same as start, except that prepare won't be called beforehand,
nothing will be enqueued to the DMA engine and nothing will happen (no
audio).  Removing the pause flag will let apps know that it isn't
supported.  Removing the resume flag will cause user space to call
prepare and start instead of resume, so audio will continue playing when
the system wakes up.

Before removing the pause and resume flags, I tested this on an exynos
5250, using 'aplay -i'. Pause/un-pause leads to silence followed by a
write error.  Suspend/resume testing led to the same result.  Removing
the two flags fixes suspend/resume (since snd_pcm_prepare is called
again). And leads to a proper reporting of pause not supported.

Signed-off-by: Dylan Reid <dgreid at chromium.org>
---
 sound/soc/samsung/dma.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index f3ebc38..56a507a 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -34,9 +34,7 @@ static const struct snd_pcm_hardware dma_hardware = {
 	.info			= SNDRV_PCM_INFO_INTERLEAVED |
 				    SNDRV_PCM_INFO_BLOCK_TRANSFER |
 				    SNDRV_PCM_INFO_MMAP |
-				    SNDRV_PCM_INFO_MMAP_VALID |
-				    SNDRV_PCM_INFO_PAUSE |
-				    SNDRV_PCM_INFO_RESUME,
+				    SNDRV_PCM_INFO_MMAP_VALID,
 	.formats		= SNDRV_PCM_FMTBIT_S16_LE |
 				    SNDRV_PCM_FMTBIT_U16_LE |
 				    SNDRV_PCM_FMTBIT_U8 |
-- 
1.7.12.146.g16d26b1



From hvaibhav at ti.com  Fri Aug 31 01:03:39 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 31 Aug 2012 10:33:39 +0530
Subject: [PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk
In-Reply-To: <alpine.DEB.2.00.1208302052210.29754@utopia.booyaka.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <alpine.DEB.2.00.1208302052210.29754@utopia.booyaka.com>
Message-ID: <504045AB.5010302@ti.com>



On 8/31/2012 2:26 AM, Paul Walmsley wrote:
> Hi Rajendra
> 
> On Wed, 29 Aug 2012, Rajendra Nayak wrote:
> 
>> Changes in v4:
>> * Added *hack* comments around clk_prepare usage in hwmod
>> rebased on 3.6-rc
> 
> Assuming this is so (haven't looked closely at this series yet), and after 
> the existing comments are taken into consideration and a new version 
> reposted, will queue this series for 3.7.
> 
> Care to respin your series that converts the data also, on top of your new 
> version of this series?  We should try to get that into 3.7 also.
> BTW are you still waiting for something from Vaibhav Hiremath for this?  
> Or can the scripts convert the existing clock33xx_data.c also?
> 

I believe I have already shared all the patches with Rajendra, so please
let me know if anything is pending on me.

Thanks,
Vaibhav

> 
> - Paul
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From thomas.abraham at linaro.org  Fri Aug 31 01:32:54 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 31 Aug 2012 11:02:54 +0530
Subject: [PATCH RESEND 0/6] ARM: EXYNOS: Add support for Trats board using
 device tree
In-Reply-To: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
References: <1346311903-15920-1-git-send-email-t.figa@samsung.com>
Message-ID: <CAJuYYwSUCNdfMXbMVVULPgTVC=zh=4qQR1YiA29JXvUCj6meGA@mail.gmail.com>

On 30 August 2012 13:01, Tomasz Figa <t.figa at samsung.com> wrote:
> This patch series adds basic device tree support for Samsung Trats board
> along with any necessary prerequisites.
>
> In addition it refactors Exynos4 dts include files to split parts common to
> the whole Exynos4 part from parts specific to Exynos4210 to allow further
> extension of Exynos4210 dts include file and addition of include files for
> other SoCs from Exynos4 line.
>
> Dependencies:
> -> [PATCH v5] mmc: sdhci-s3c: Add device tree support
> http://www.spinics.net/lists/linux-samsung-soc/msg12056.html
> -> [PATCH v5 2/2] regulator: add device tree support for max8997
> http://www.spinics.net/lists/kernel/msg1328117.html

I will follow up on this patch and resubmit it.

Thanks,
Thomas.

[...]


From andrew at lunn.ch  Fri Aug 31 01:47:34 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 31 Aug 2012 07:47:34 +0200
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <20120830185050.GZ19437@titan.lakedaemon.net>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
 <20120830171236.GS19437@titan.lakedaemon.net>
 <20120830180853.GP9886@lunn.ch>
 <20120830185050.GZ19437@titan.lakedaemon.net>
Message-ID: <20120831054734.GA30111@lunn.ch>

On Thu, Aug 30, 2012 at 02:50:50PM -0400, Jason Cooper wrote:
> On Thu, Aug 30, 2012 at 08:08:53PM +0200, Andrew Lunn wrote:
> > On Thu, Aug 30, 2012 at 01:12:36PM -0400, Jason Cooper wrote:
> > > On Thu, Aug 30, 2012 at 07:39:12AM +0200, Andrew Lunn wrote:
> > > > Linux-next has failed to compile for kirkwood since 23 August with:
> > > > 
> > > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
> > > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)
> > > > 
> > > > Add missing <linux/sizes.h>
> > > > 
> > > > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> > > 
> > > Applied to: fixes-for-v3.6
> > > 
> > > Also, I added a CC for stable so greg can pick it up.
> > 
> > Stable does not need it. As i said, it only broke 23 August with
> > linux-next. So this is needed for only 3.7.
> 
> Do we know caused the break?  Is it a fix destined for -stable?

Hi Jason

If im groking the output from gcc -E correctly, it was this change:

http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=commitdiff;h=8f039ba3191e67bf48e560f5737d0c285720d4d8

The #include <asm/memory.h> has been dropped, and its from there that
it was getting <linux/sizes.h>.

This does not look like a change that will get backported to anything
earlier than 3.7.

	Andrew


From robherring2 at gmail.com  Fri Aug 31 01:58:38 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 00:58:38 -0500
Subject: [PATCH 0/9] Clean up hardcoded IRQs for mach-omap2,
 enable SPARSE_IRQ, plaform_data/gpio-omap.h
In-Reply-To: <20120831004828.28732.902.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
Message-ID: <5040528E.80509@gmail.com>

On 08/30/2012 07:52 PM, Tony Lindgren wrote:
> Hi all,
> 
> Here's the first set of omap header clean-up patches needed for single
> zImage support. This series is based v3.6-rc3 and the following patches
> to avoid merge conflicts with the includes:
> 
> - Arnd's patch "ARM: omap: move platform_data definitions"
> - Igor's series "ARM: OMAP: cleanup plat/board.h file"
> - Afzal's series "Prepare for GPMC driver conversion (w.r.t MTD)"
> 

Looks like I can drop my omap gpio changes with this. Do you have a git
tree with this?

Rob

> Regards,
> 
> Tony
> 
> ---
> 
> Tony Lindgren (9):
>       ARM: OMAP1: Move define of OMAP_LCD_DMA to dma.h
>       ARM: OMAP1: Define OMAP1_INT_I2C locally
>       ARM: OMAP2+: Make INTCPS_NR_IRQS local for mach-omap2/irq.c
>       ARM: OMAP2+: Remove unused nand_irq for GPMC
>       ARM: OMAP2+: Remove hardcoded twl4030 gpio_base, irq_base and irq_end
>       ARM: OMAP: Move gpio.h to include/linux/platform_data
>       ARM: OMAP2+: Prepare for irqs.h removal
>       ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ
>       ARM: OMAP1: Move plat/irqs.h to mach/irqs.h
> 
> 
>  arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    1 
>  arch/arm/mach-omap1/board-ams-delta.c              |    3 
>  arch/arm/mach-omap1/board-osk.c                    |    1 
>  arch/arm/mach-omap1/dma.c                          |    3 
>  arch/arm/mach-omap1/gpio15xx.c                     |    1 
>  arch/arm/mach-omap1/gpio16xx.c                     |    1 
>  arch/arm/mach-omap1/gpio7xx.c                      |    1 
>  arch/arm/mach-omap1/include/mach/ams-delta-fiq.h   |    2 
>  arch/arm/mach-omap1/include/mach/gpio.h            |    2 
>  arch/arm/mach-omap1/include/mach/irqs.h            |  267 ++++++++++++
>  arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 
>  arch/arm/mach-omap1/leds.c                         |    1 
>  arch/arm/mach-omap2/board-2430sdp.c                |   10 
>  arch/arm/mach-omap2/board-3430sdp.c                |    3 
>  arch/arm/mach-omap2/board-4430sdp.c                |    3 
>  arch/arm/mach-omap2/board-am3517evm.c              |   12 -
>  arch/arm/mach-omap2/board-cm-t35.c                 |   15 -
>  arch/arm/mach-omap2/board-cm-t3517.c               |    6 
>  arch/arm/mach-omap2/board-devkit8000.c             |    3 
>  arch/arm/mach-omap2/board-flash.c                  |    3 
>  arch/arm/mach-omap2/board-igep0020.c               |   10 
>  arch/arm/mach-omap2/board-ldp.c                    |    3 
>  arch/arm/mach-omap2/board-n8x0.c                   |    3 
>  arch/arm/mach-omap2/board-omap3beagle.c            |    3 
>  arch/arm/mach-omap2/board-omap3evm.c               |    3 
>  arch/arm/mach-omap2/board-omap3logic.c             |    3 
>  arch/arm/mach-omap2/board-omap3pandora.c           |    3 
>  arch/arm/mach-omap2/board-omap3stalker.c           |    3 
>  arch/arm/mach-omap2/board-omap3touchbook.c         |    3 
>  arch/arm/mach-omap2/board-omap4panda.c             |    3 
>  arch/arm/mach-omap2/board-overo.c                  |    3 
>  arch/arm/mach-omap2/board-rm680.c                  |    9 
>  arch/arm/mach-omap2/board-rx51-peripherals.c       |    5 
>  arch/arm/mach-omap2/board-ti8168evm.c              |    3 
>  arch/arm/mach-omap2/board-zoom-debugboard.c        |    1 
>  arch/arm/mach-omap2/board-zoom-display.c           |    6 
>  arch/arm/mach-omap2/board-zoom-peripherals.c       |    9 
>  arch/arm/mach-omap2/cpuidle34xx.c                  |    1 
>  arch/arm/mach-omap2/devices.c                      |    7 
>  arch/arm/mach-omap2/gpio.c                         |    1 
>  arch/arm/mach-omap2/gpmc-smc91x.c                  |    1 
>  arch/arm/mach-omap2/gpmc.c                         |   11 
>  arch/arm/mach-omap2/hsmmc.c                        |    5 
>  arch/arm/mach-omap2/include/mach/gpio.h            |    2 
>  arch/arm/mach-omap2/include/mach/irqs.h            |    2 
>  arch/arm/mach-omap2/io.c                           |    2 
>  arch/arm/mach-omap2/irq.c                          |    2 
>  arch/arm/mach-omap2/mailbox.c                      |    3 
>  arch/arm/mach-omap2/mcbsp.c                        |    1 
>  arch/arm/mach-omap2/msdi.c                         |    1 
>  arch/arm/mach-omap2/omap-iommu.c                   |    1 
>  arch/arm/mach-omap2/omap-wakeupgen.c               |    1 
>  arch/arm/mach-omap2/omap4-common.c                 |    7 
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    2 
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    9 
>  .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 -
>  arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    4 
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   33 +
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    6 
>  arch/arm/mach-omap2/omap_l3_noc.c                  |    6 
>  arch/arm/mach-omap2/omap_phy_internal.c            |    2 
>  arch/arm/mach-omap2/pm24xx.c                       |    3 
>  arch/arm/mach-omap2/pm34xx.c                       |    2 
>  arch/arm/mach-omap2/prcm.c                         |    1 
>  arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    3 
>  arch/arm/mach-omap2/prm44xx.c                      |    4 
>  arch/arm/mach-omap2/prm_common.c                   |    1 
>  arch/arm/mach-omap2/serial.c                       |    1 
>  arch/arm/mach-omap2/timer.c                        |   10 
>  arch/arm/mach-omap2/twl-common.c                   |    3 
>  arch/arm/mach-omap2/twl-common.h                   |    6 
>  arch/arm/mach-omap2/usb-host.c                     |    1 
>  arch/arm/mach-omap2/usb-musb.c                     |    1 
>  arch/arm/plat-omap/Kconfig                         |    1 
>  arch/arm/plat-omap/i2c.c                           |    3 
>  arch/arm/plat-omap/include/plat/dma.h              |    2 
>  arch/arm/plat-omap/include/plat/irqs-44xx.h        |  144 ------
>  arch/arm/plat-omap/include/plat/irqs.h             |  453 --------------------
>  arch/arm/plat-omap/include/plat/omap44xx.h         |    1 
>  drivers/dma/omap-dma.c                             |    2 
>  drivers/gpio/gpio-omap.c                           |   15 -
>  drivers/gpio/gpio-twl4030.c                        |   15 -
>  drivers/mfd/twl-core.c                             |    2 
>  drivers/mtd/nand/ams-delta.c                       |    8 
>  drivers/mtd/onenand/omap2.c                        |    8 
>  drivers/tty/serial/8250/8250.c                     |    4 
>  drivers/video/omap2/dss/dispc.c                    |    1 
>  drivers/video/omap2/omapfb/omapfb-main.c           |    4 
>  include/linux/i2c/twl.h                            |    3 
>  include/linux/mfd/twl6040.h                        |    2 
>  include/linux/platform_data/gpio-omap.h            |   15 -
>  include/linux/platform_data/mtd-nand-omap2.h       |    1 
>  sound/soc/omap/mcbsp.c                             |    3 
>  sound/soc/omap/omap-mcbsp.c                        |    1 
>  sound/soc/omap/omap-pcm.c                          |    1 
>  sound/soc/omap/sdp3430.c                           |    1 
>  96 files changed, 455 insertions(+), 808 deletions(-)
>  delete mode 100644 arch/arm/plat-omap/include/plat/irqs-44xx.h
>  delete mode 100644 arch/arm/plat-omap/include/plat/irqs.h
>  rename arch/arm/plat-omap/include/plat/gpio.h => include/linux/platform_data/gpio-omap.h (94%)
> 



From horms at verge.net.au  Fri Aug 31 02:05:15 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 15:05:15 +0900
Subject: [PATCH] ARM: mach-shmobile: remove duplicated include from
 board-ag5evm.c
In-Reply-To: <CAPgLHd_LaGpVqgWa-5EfYbkmjuM_rhT47y2-z6E3ExZ8Rmw4vw@mail.gmail.com>
References: <CAPgLHd_LaGpVqgWa-5EfYbkmjuM_rhT47y2-z6E3ExZ8Rmw4vw@mail.gmail.com>
Message-ID: <20120831060515.GA7014@verge.net.au>

On Sun, Aug 26, 2012 at 09:49:58AM +0800, Wei Yongjun wrote:
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
> 
> Remove duplicated include.

Thanks, applied to the ag5evm branch of
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git



From hvaibhav at ti.com  Fri Aug 31 02:17:19 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 31 Aug 2012 11:47:19 +0530
Subject: [PATCH RESEND v4 1/3] arm/dts: AM33XX: Add basic pinctrl device
 tree data
In-Reply-To: <20120830203234.GA1303@atomide.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
 <1346141454-18786-2-git-send-email-anilkumar@ti.com>
 <20120830203234.GA1303@atomide.com>
Message-ID: <504056EF.8010205@ti.com>



On 8/31/2012 2:02 AM, Tony Lindgren wrote:
> * AnilKumar Ch <anilkumar at ti.com> [120828 01:11]:
>> Adds basic pinctrl device tree data for AM33XX family of devices.
>> This patch is based on the pinctrl-single driver.
>>
>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>> ---
>>  arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
>> index dde76f7..dfe9c559 100644
>> --- a/arch/arm/boot/dts/am33xx.dtsi
>> +++ b/arch/arm/boot/dts/am33xx.dtsi
>> @@ -40,6 +40,15 @@
>>  		};
>>  	};
>>  
>> +	am3358_pinmux: pinmux at 44E10800 {
>> +		compatible = "pinctrl-single";
>> +		reg = <0x44E10800 0x0238>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		pinctrl-single,register-width = <32>;
>> +		pinctrl-single,function-mask = <0x7F>;
>> +	};
>> +
> 
> Nit: Please use lower case for the hex numbers as that's the
> standard in Linux kernel.
> 

Tony,

I could see that you have already merged the patch from Anil for
regulator support in bone & evm dts file, which has uppper-case hex numbers.
Request you to merge the patch which I submitted to convert all hex
numbers to lower-case and then merge all dts changes only with
lower-case presentation.

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg74393.html

Thanks,
Vaibhav
> Tony
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
> 


From gerg at snapgear.com  Fri Aug 31 02:20:24 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Fri, 31 Aug 2012 16:20:24 +1000
Subject: [PATCH 4/4] ARM: ks8695: convert to generic time and clocksource
In-Reply-To: <1346264842-20411-1-git-send-email-linus.walleij@linaro.org>
References: <1346264842-20411-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <504057A8.7030302@snapgear.com>

Hi Linus,

On 08/30/2012 04:27 AM, Linus Walleij wrote:
> Old platforms using ancient gettimeoffset() and other arcane
> APIs are standing in the way of cleaning up the ARM kernel.
>
> This is an attempt at blind-coding a generic time and clocksource
> driver for the platform by way of a datasheet and looking at the
> old code, it'd be great if someone who is actually using this
> machine could test it.

Ok, tested on a KS8695 based machine. Boots and runs, obviously
clock is basically working. But 'date' never shows the time
increasing:

   # date
   Thu Jan  1 00:00:00 UTC 1970
   # date
   Thu Jan  1 00:00:00 UTC 1970
   # date
   Thu Jan  1 00:00:00 UTC 1970
   #

And yes, that did work before applying this patch :-)

Regards
Greg



> If noone volunteers to do this I will instead propose a patch
> deleting the machine altogether.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>   arch/arm/Kconfig            |    3 +-
>   arch/arm/mach-ks8695/time.c |  123 ++++++++++++++++++++++++++++++-------------
>   2 files changed, 88 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c5f9ae5..181b697 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -652,8 +652,9 @@ config ARCH_KS8695
>   	bool "Micrel/Kendin KS8695"
>   	select CPU_ARM922T
>   	select ARCH_REQUIRE_GPIOLIB
> -	select ARCH_USES_GETTIMEOFFSET
>   	select NEED_MACH_MEMORY_H
> +	select CLKSRC_MMIO
> +	select GENERIC_CLOCKEVENTS
>   	help
>   	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
>   	  System-on-Chip devices.
> diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
> index 6974c23..1a933f1 100644
> --- a/arch/arm/mach-ks8695/time.c
> +++ b/arch/arm/mach-ks8695/time.c
> @@ -25,6 +25,8 @@
>   #include <linux/kernel.h>
>   #include <linux/sched.h>
>   #include <linux/io.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
>
>   #include <asm/mach/time.h>
>   #include <asm/system_misc.h>
> @@ -53,44 +55,68 @@
>   /* Timer0 Timeout Counter Register */
>   #define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
>
> -/*
> - * Returns number of ms since last clock interrupt.  Note that interrupts
> - * will have been disabled by do_gettimeoffset()
> - */
> -static unsigned long ks8695_gettimeoffset (void)
> +static void ks8695_set_mode(enum clock_event_mode mode,
> +			    struct clock_event_device *evt)
>   {
> -	unsigned long elapsed, tick2, intpending;
> +	if (mode == CLOCK_EVT_FEAT_PERIODIC) {
> +		u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
> +		u32 half = DIV_ROUND_CLOSEST(rate, 2);
> +		u32 tmcon;
> +
> +		/* Disable timer 1 */
> +		tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
> +		tmcon &= TMCON_T1EN;
> +		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
> +
> +		/* Both registers need to count down */
> +		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
> +		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
> +
> +		/* Re-enable timer1 */
> +		tmcon |= TMCON_T1EN;
> +		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
> +	}
> +}
>
> -	/*
> -	 * Get the current number of ticks.  Note that there is a race
> -	 * condition between us reading the timer and checking for an
> -	 * interrupt.  We solve this by ensuring that the counter has not
> -	 * reloaded between our two reads.
> -	 */
> -	elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
> -	do {
> -		tick2 = elapsed;
> -		intpending = readl_relaxed(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
> -		elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
> -	} while (elapsed > tick2);
> -
> -	/* Convert to number of ticks expired (not remaining) */
> -	elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
> -
> -	/* Is interrupt pending?  If so, then timer has been reloaded already. */
> -	if (intpending)
> -		elapsed += (CLOCK_TICK_RATE / HZ);
> -
> -	/* Convert ticks to usecs */
> -	return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
> +static int ks8695_set_next_event(unsigned long cycles,
> +				 struct clock_event_device *evt)
> +
> +{
> +	u32 half = DIV_ROUND_CLOSEST(cycles, 2);
> +	u32 tmcon;
> +
> +	/* Disable timer 1 */
> +	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
> +	tmcon &= TMCON_T1EN;
> +	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
> +
> +	/* Both registers need to count down */
> +	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
> +	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
> +
> +	/* Re-enable timer1 */
> +	tmcon |= TMCON_T1EN;
> +	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
> +
> +	return 0;
>   }
>
> +static struct clock_event_device clockevent_ks8695 = {
> +	.name		= "ks8695_t1tc",
> +	.rating		= 300, /* Reasonably fast and accurate clock event */
> +	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
> +	.set_next_event	= ks8695_set_next_event,
> +	.set_mode	= ks8695_set_mode,
> +};
> +
>   /*
>    * IRQ handler for the timer.
>    */
>   static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
>   {
> -	timer_tick();
> +	struct clock_event_device *evt = &clockevent_ks8695;
> +
> +	evt->event_handler(evt);
>   	return IRQ_HANDLED;
>   }
>
> @@ -102,18 +128,42 @@ static struct irqaction ks8695_timer_irq = {
>
>   static void ks8695_timer_setup(void)
>   {
> -	unsigned long tmout = CLOCK_TICK_RATE / HZ;
>   	unsigned long tmcon;
>
> -	/* disable timer1 */
> +	/* Disable timer 0 and 1 */
>   	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
> -	writel_relaxed(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
> +	tmcon &= TMCON_T0EN;
> +	tmcon &= TMCON_T1EN;
> +	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
>
> -	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
> -	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
> +	/*
> +	 * Set up timer 0 to loop indefinately, count 32 bits with TOUT0
> +	 * set to zero, then 1 bit with TOUT0 set to 1. The reason we are doing
> +	 * this is that it's not allowed to set either register to 0, then the
> +	 * behaviour is "unpredictable". This injects a faulty pulse every
> +	 * 2^32-1 cycles but we can surely live with that rather than
> +	 * complicating the code.
> +	 */
> +	writel_relaxed(0xFFFFFFFFU, KS8695_TMR_VA + KS8695_T0TC);
> +	writel_relaxed(1, KS8695_TMR_VA + KS8695_T0PD);
> +	/* Start timer 0 */
> +	tmcon |= TMCON_T0EN;
> +	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
> +	/* Use timer 0 as clocksource */
> +	if (clocksource_mmio_init((void *) KS8695_TMR_VA + KS8695_T0TC,
> +			"ks8695_t0tc", KS8695_CLOCK_RATE, 300, 32,
> +			clocksource_mmio_readl_up))
> +		pr_err("timer: failed to initialize KS8695 clock source\n");
>
> -	/* re-enable timer1 */
> -	writel_relaxed(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
> +	/*
> +	 * Use timer 1 to fire IRQs on the timeline, only support one-shot
> +	 * mode and the system will take care of the rest. Minimum 2 cycles
> +	 * (one on each counter) maximum 2*2^32, but the API will only
> +	 * accept up to a 32bit full word (0xFFFFFFFFU).
> +	 */
> +	clockevents_config_and_register(&clockevent_ks8695,
> +					KS8695_CLOCK_RATE, 2,
> +					0xFFFFFFFFU);
>   }
>
>   static void __init ks8695_timer_init (void)
> @@ -126,7 +176,6 @@ static void __init ks8695_timer_init (void)
>
>   struct sys_timer ks8695_timer = {
>   	.init		= ks8695_timer_init,
> -	.offset		= ks8695_gettimeoffset,
>   };
>
>   void ks8695_restart(char mode, const char *cmd)
>


-- 
------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close,                            FAX:         +61 7 3891 3630
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From horms at verge.net.au  Fri Aug 31 02:24:38 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 15:24:38 +0900
Subject: [GIT PULL v2] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7
In-Reply-To: <1346376502-12114-1-git-send-email-horms@verge.net.au>
References: <1346376502-12114-1-git-send-email-horms@verge.net.au>
Message-ID: <20120831062438.GB7014@verge.net.au>

On Fri, Aug 31, 2012 at 10:28:11AM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
> 
> please consider the following enhancements to the Marzen board
> and r8a7779 SoC by Phil Edworthy, Morimoto-san and myself for 3.7.
> 
> * This pull requests superceedes the previous request,
>   "[GIT PULL v2] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7"

    The line above should be:

    "[GIT PULL] Renesas ARM-based SoC: Marzen and r8a7779 for 3.7"

>   which I made earlier today. The difference to that request is that
>   I have pushed one more patch. There was no rebase.
> 
> * This pull request is based on the usb-next branch of Greg KH's USB tree,
>   git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git,
>   which is based on v3.6-rc3.
> 
>   This is to satisfy compile-time dependencies.
>   Please let me know if you would like this handled a different way.
> 
> ----------------------------------------------------------------
> The following changes since commit a7bdf7fa33127bf08eb0810698bca607a9462df4:
> 
>   Merge v3.6-rc3 into usb-next (2012-08-27 07:15:30 -0700)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git marzen
> 
> for you to fetch changes up to 3553395437f2ac42a73255a0ffac09efc9acf5c4:
> 
>   ARM: shmobile: marzen: add USB OHCI driver support (2012-08-31 09:41:44 +0900)
> 
> ----------------------------------------------------------------
> Kuninori Morimoto (8):
>       ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx
>       ARM: shmobile: r8a7779: add USB common phy initializer
>       ARM: shmobile: r8a7779: add USB EHCI clock support
>       ARM: shmobile: r8a7779: add USB OHCI clock support
>       ARM: shmobile: marzen: add USB EHCI driver support
>       ARM: shmobile: marzen: fixup regulator id for smsc911x
>       ARM: shmobile: marzen: enable thermal sensor
>       ARM: shmobile: marzen: add USB OHCI driver support
> 
> Phil Edworthy (2):
>       r8a7779: add SDHI clock support
>       marzen: add SDHI0 support
> 
> Simon Horman (1):
>       ARM: mach-shmobile: marzen: defconfig update
> 
>  arch/arm/configs/marzen_defconfig             |  30 ++--
>  arch/arm/mach-shmobile/Kconfig                |   2 +
>  arch/arm/mach-shmobile/board-marzen.c         | 213 +++++++++++++++++++++++++-
>  arch/arm/mach-shmobile/clock-r8a7779.c        |  18 ++-
>  arch/arm/mach-shmobile/include/mach/common.h  |   1 +
>  arch/arm/mach-shmobile/include/mach/r8a7779.h |   2 +-
>  arch/arm/mach-shmobile/pfc-r8a7779.c          |  16 +-
>  arch/arm/mach-shmobile/setup-r8a7779.c        |  93 +++++++++++
>  8 files changed, 355 insertions(+), 20 deletions(-)
> 


From a0393947 at ti.com  Fri Aug 31 02:23:41 2012
From: a0393947 at ti.com (Archit Taneja)
Date: Fri, 31 Aug 2012 11:53:41 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <1346344933.2327.43.camel@deskari>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
 <1346344933.2327.43.camel@deskari>
Message-ID: <5040586D.2020406@ti.com>

On Thursday 30 August 2012 10:12 PM, Tomi Valkeinen wrote:
> On Thu, 2012-08-30 at 13:57 +0200, Benoit Cousson wrote:
>> On 08/30/2012 10:39 AM, Rajendra Nayak wrote:
>>> On Thursday 30 August 2012 05:45 AM, Turquette, Mike wrote:
>>>> On Wed, Aug 29, 2012 at 1:56 AM, Rajendra Nayak<rnayak at ti.com>  wrote:
>>>>> diff --git a/arch/arm/mach-omap2/clock44xx_data.c
>>>>> b/arch/arm/mach-omap2/clock44xx_data.c
>>>>> index d7f55e4..a3831a2 100644
>>>>> --- a/arch/arm/mach-omap2/clock44xx_data.c
>>>>> +++ b/arch/arm/mach-omap2/clock44xx_data.c
>>>>> @@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
>>>>>           CLK(NULL,       "dss_tv_clk",&dss_tv_clk,    CK_443X),
>>>>>           CLK(NULL,       "dss_48mhz_clk",&dss_48mhz_clk, CK_443X),
>>>>>           CLK(NULL,       "dss_dss_clk",&dss_dss_clk,   CK_443X),
>>>>> +       CLK(NULL,       "dss_fck",&dss_fck,       CK_443X),
>>>>>           CLK("omapdss_dss",      "ick",&dss_fck,       CK_443X),
>>>>
>>>> Is it right to re-use dss_fck for the "ick" here?  I think it is due
>>>> to omap4 modulemode stuff but I don't have DM in front of me and
>>>> wanted a double-check...
>>>
>>> yes, its because of the wierdness of DSS clocks where a so-called
>>> optional clock is actually a function clock.
>>
>> Not only, it is a hack to allow the DSS to be enabled whenever a DSS
>> submodule has to be enabled. Since they are sharing the ick, it will
>> enable the modulemode when the DISPC will be enabled.
>>
>> That hack should disappear as soon as the DSS will be able to handle the
>> PM dependency between DSS submodules and the DSS itself using pm_runtime
>> parent/child link.
>> And then we will have to remove this fake ick modulemode clock node and
>> let hwmod handle that properly.
>>
>> Tomi already cleaned the DSS part, I guess it should be upstreamed soon,
>> if this is not already the case.
>
> This is in 3.5. omapdss_dss is now the parent for the rest of the dss
> submodules, and runtime PM is being used.
>
> I think we should now revisit this dss clock handling to see if there
> are any other changes required in the omapdss side, but I hope they are
> already according to our discussions and correct.

The only little problem was that during bootup, when hwmods are setup, 
only the 'parent' hwmod was able to get reset properly, all the other 
'child' hwmods don't have modulemode bits tied to them, and hence 
weren't able to reset. So we got some error prints.

Once DSS driver kicks in, the driver ensures the parent is enabled for 
any child to be enabled, so we don't face the issue again.

So, if DSS driver is not built in, and if the bootloader left DSS in a 
bad state, the DSS clocks might remain messed up all the time since 
hwmod fwk wasn't able to reset them.

I think this is why we didn't proceed with remove "dss_fck" as a slave 
clock. If this issue is minor, we could go ahead and remove it.

Archit



From horms at verge.net.au  Fri Aug 31 02:26:15 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 15:26:15 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: AG5EVM for 3.7
Message-ID: <1346394376-11951-1-git-send-email-horms@verge.net.au>

Hi Olof, Hi Arnd,

please consider the following enhancement to the AG5EVM board
by Wei Yongjun for inclusion in 3.7.

----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git ag5evm

for you to fetch changes up to aa9c1ba4412d2f9348b6e700aa4831569a25a7ca:

  ARM: mach-shmobile: remove duplicated include from board-ag5evm.c (2012-08-31 15:02:02 +0900)

----------------------------------------------------------------
Wei Yongjun (1):
      ARM: mach-shmobile: remove duplicated include from board-ag5evm.c

 arch/arm/mach-shmobile/board-ag5evm.c | 1 -
 1 file changed, 1 deletion(-)


From horms at verge.net.au  Fri Aug 31 02:26:16 2012
From: horms at verge.net.au (Simon Horman)
Date: Fri, 31 Aug 2012 15:26:16 +0900
Subject: [PATCH] ARM: mach-shmobile: remove duplicated include from
 board-ag5evm.c
In-Reply-To: <1346394376-11951-1-git-send-email-horms@verge.net.au>
References: <1346394376-11951-1-git-send-email-horms@verge.net.au>
Message-ID: <1346394376-11951-2-git-send-email-horms@verge.net.au>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn>

Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn>
Signed-off-by: Simon Horman <horms at verge.net.au>
---
 arch/arm/mach-shmobile/board-ag5evm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d82c010..cfc3b5c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,7 +40,6 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
-#include <linux/videodev2.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
-- 
1.7.10.2.484.gcd07cc5



From gerg at snapgear.com  Fri Aug 31 02:25:52 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Fri, 31 Aug 2012 16:25:52 +1000
Subject: [PATCH 1/4] ARM: ks-8695: merge the timer header into the timer
 driver
In-Reply-To: <1346264802-20306-1-git-send-email-linus.walleij@linaro.org>
References: <1346264802-20306-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <504058F0.9060705@snapgear.com>

On 08/30/2012 04:26 AM, Linus Walleij wrote:
> This <mach/regs-timer.h> is broadcasted in the entire kernel for
> no good reason, since it's only used by the timer driver. Merge
> it into the driver.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Tested-by: Greg Ungerer <gerg at snapgear.com>


> ---
>   arch/arm/mach-ks8695/include/mach/regs-timer.h |   40 ------------------------
>   arch/arm/mach-ks8695/time.c                    |   21 ++++++++++++-
>   2 files changed, 20 insertions(+), 41 deletions(-)
>   delete mode 100644 arch/arm/mach-ks8695/include/mach/regs-timer.h
>
> diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
> deleted file mode 100644
> index e620cda..0000000
> --- a/arch/arm/mach-ks8695/include/mach/regs-timer.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/*
> - * arch/arm/mach-ks8695/include/mach/regs-timer.h
> - *
> - * Copyright (C) 2006 Ben Dooks <ben at simtec.co.uk>
> - * Copyright (C) 2006 Simtec Electronics
> - *
> - * KS8695 - Timer registers and bit definitions.
> - *
> - * This file is licensed under  the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef KS8695_TIMER_H
> -#define KS8695_TIMER_H
> -
> -#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)
> -#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)
> -#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)
> -
> -
> -/*
> - * Timer registers
> - */
> -#define KS8695_TMCON		(0x00)		/* Timer Control Register */
> -#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */
> -#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */
> -#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */
> -#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */
> -
> -
> -/* Timer Control Register */
> -#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */
> -#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */
> -
> -/* Timer0 Timeout Counter Register */
> -#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
> -
> -
> -#endif
> diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
> index ec783a3..6427b7c 100644
> --- a/arch/arm/mach-ks8695/time.c
> +++ b/arch/arm/mach-ks8695/time.c
> @@ -29,11 +29,30 @@
>   #include <asm/mach/time.h>
>   #include <asm/system_misc.h>
>
> -#include <mach/regs-timer.h>
>   #include <mach/regs-irq.h>
>
>   #include "generic.h"
>
> +#define KS8695_TMR_OFFSET	(0xF0000 + 0xE400)
> +#define KS8695_TMR_VA		(KS8695_IO_VA + KS8695_TMR_OFFSET)
> +#define KS8695_TMR_PA		(KS8695_IO_PA + KS8695_TMR_OFFSET)
> +
> +/*
> + * Timer registers
> + */
> +#define KS8695_TMCON		(0x00)		/* Timer Control Register */
> +#define KS8695_T1TC		(0x04)		/* Timer 1 Timeout Count Register */
> +#define KS8695_T0TC		(0x08)		/* Timer 0 Timeout Count Register */
> +#define KS8695_T1PD		(0x0C)		/* Timer 1 Pulse Count Register */
> +#define KS8695_T0PD		(0x10)		/* Timer 0 Pulse Count Register */
> +
> +/* Timer Control Register */
> +#define TMCON_T1EN		(1 << 1)	/* Timer 1 Enable */
> +#define TMCON_T0EN		(1 << 0)	/* Timer 0 Enable */
> +
> +/* Timer0 Timeout Counter Register */
> +#define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
> +
>   /*
>    * Returns number of ms since last clock interrupt.  Note that interrupts
>    * will have been disabled by do_gettimeoffset()
>


-- 
------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close,                            FAX:         +61 7 3891 3630
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From gerg at snapgear.com  Fri Aug 31 02:30:01 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Fri, 31 Aug 2012 16:30:01 +1000
Subject: [PATCH 3/4] ARM: ks8695: delete resume hook from timer
In-Reply-To: <1346264832-20379-1-git-send-email-linus.walleij@linaro.org>
References: <1346264832-20379-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <504059E9.9090606@snapgear.com>

On 08/30/2012 04:27 AM, Linus Walleij wrote:
> This system does not support suspend/resume so let's skip this
> hook altogether.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Tested-by: Greg Ungerer <gerg at snapgear.com>


> ---
>   arch/arm/mach-ks8695/time.c |    1 -
>   1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
> index ae9dacc..6974c23 100644
> --- a/arch/arm/mach-ks8695/time.c
> +++ b/arch/arm/mach-ks8695/time.c
> @@ -127,7 +127,6 @@ static void __init ks8695_timer_init (void)
>   struct sys_timer ks8695_timer = {
>   	.init		= ks8695_timer_init,
>   	.offset		= ks8695_gettimeoffset,
> -	.resume		= ks8695_timer_setup,
>   };
>
>   void ks8695_restart(char mode, const char *cmd)
>


-- 
------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close,                            FAX:         +61 7 3891 3630
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From vbyravarasu at nvidia.com  Fri Aug 31 02:45:26 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Fri, 31 Aug 2012 12:15:26 +0530
Subject: [PATCH v2] usb: move phy driver from mach-tegra to drivers/usb
Message-ID: <1346395526-18219-1-git-send-email-vbyravarasu@nvidia.com>

As part of this patch:
	1. Moved existing tegra phy driver to drivers/USB directory.
	2. Added standard USB phy driver APIs to tegra phy driver.

Signed-off-by: Venu Byravarasu <vbyravarasu at nvidia.com>
---
delta from v1:

1. Used standard USB phy driver APIs
2. Restored ULPI phy support, which was removed in patch v1, while moving
tegra usb phy driver from mach-tegra to drivers/usb/phy directory.


 arch/arm/mach-tegra/Makefile                       |    1 -
 arch/arm/mach-tegra/devices.c                      |    2 +-
 arch/arm/mach-tegra/devices.h                      |    2 +-
 drivers/usb/host/ehci-tegra.c                      |   14 +-
 drivers/usb/phy/Makefile                           |    1 +
 .../usb_phy.c => drivers/usb/phy/tegra_usb_phy.c   |  152 +++++++++++---------
 .../usb_phy.h => include/linux/usb/tegra_usb_phy.h |   16 +--
 7 files changed, 103 insertions(+), 85 deletions(-)
 rename arch/arm/mach-tegra/usb_phy.c => drivers/usb/phy/tegra_usb_phy.c (94%)
 rename arch/arm/mach-tegra/include/mach/usb_phy.h => include/linux/usb/tegra_usb_phy.h (86%)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b94858f..b542dac 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
-obj-$(CONFIG_USB_SUPPORT)		+= usb_phy.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 61e9603..63cc280 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -26,7 +26,7 @@
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
-#include <mach/usb_phy.h>
+#include <linux/usb/tegra_usb_phy.h>
 
 #include "gpio-names.h"
 #include "devices.h"
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 4f50527..906a61f 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -22,7 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/tegra_usb.h>
 
-#include <mach/usb_phy.h>
+#include <linux/usb/tegra_usb_phy.h>
 
 extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
 
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 75eca42..bd20dba 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -27,7 +27,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 
-#include <mach/usb_phy.h>
+#include <linux/usb/tegra_usb_phy.h>
 #include <mach/iomap.h>
 
 #define TEGRA_USB_DMA_ALIGN 32
@@ -49,7 +49,7 @@ static void tegra_ehci_power_up(struct usb_hcd *hcd)
 
 	clk_prepare_enable(tegra->emc_clk);
 	clk_prepare_enable(tegra->clk);
-	tegra_usb_phy_power_on(tegra->phy);
+	usb_phy_set_suspend(&tegra->phy->u_phy, 0);
 	tegra->host_resumed = 1;
 }
 
@@ -58,7 +58,7 @@ static void tegra_ehci_power_down(struct usb_hcd *hcd)
 	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 
 	tegra->host_resumed = 0;
-	tegra_usb_phy_power_off(tegra->phy);
+	usb_phy_set_suspend(&tegra->phy->u_phy, 1);
 	clk_disable_unprepare(tegra->clk);
 	clk_disable_unprepare(tegra->emc_clk);
 }
@@ -715,7 +715,9 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		goto fail_io;
 	}
 
-	err = tegra_usb_phy_power_on(tegra->phy);
+	usb_phy_init(&tegra->phy->u_phy);
+
+	err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to power on the phy\n");
 		goto fail;
@@ -761,7 +763,7 @@ fail:
 	if (!IS_ERR_OR_NULL(tegra->transceiver))
 		otg_set_host(tegra->transceiver->otg, NULL);
 #endif
-	tegra_usb_phy_close(tegra->phy);
+	usb_phy_shutdown(&tegra->phy->u_phy);
 fail_io:
 	clk_disable_unprepare(tegra->emc_clk);
 fail_emc_clk:
@@ -790,7 +792,7 @@ static int tegra_ehci_remove(struct platform_device *pdev)
 
 	usb_remove_hcd(hcd);
 
-	tegra_usb_phy_close(tegra->phy);
+	usb_phy_shutdown(&tegra->phy->u_phy);
 
 	usb_put_hcd(hcd);
 
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index eca095b..d2c9546 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -5,3 +5,4 @@
 ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
 
 obj-$(CONFIG_USB_ISP1301)		+= isp1301.o
+obj-$(CONFIG_USB_EHCI_TEGRA)	+= tegra_usb_phy.o
diff --git a/arch/arm/mach-tegra/usb_phy.c b/drivers/usb/phy/tegra_usb_phy.c
similarity index 94%
rename from arch/arm/mach-tegra/usb_phy.c
rename to drivers/usb/phy/tegra_usb_phy.c
index 022b33a..4739903 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/drivers/usb/phy/tegra_usb_phy.c
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/usb_phy.c
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
@@ -31,7 +29,7 @@
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <mach/gpio-tegra.h>
-#include <mach/usb_phy.h>
+#include <linux/usb/tegra_usb_phy.h>
 #include <mach/iomap.h>
 
 #define ULPI_VIEWPORT		0x170
@@ -482,7 +480,7 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 	return 0;
 }
 
-static void utmi_phy_power_off(struct tegra_usb_phy *phy)
+static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
@@ -514,7 +512,7 @@ static void utmi_phy_power_off(struct tegra_usb_phy *phy)
 	       UTMIP_FORCE_PDDR_POWERDOWN;
 	writel(val, base + UTMIP_XCVR_CFG1);
 
-	utmip_pad_power_off(phy);
+	return utmip_pad_power_off(phy);
 }
 
 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
@@ -638,7 +636,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 	return 0;
 }
 
-static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
+static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
@@ -651,15 +649,92 @@ static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
 	val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
 	writel(val, base + USB_PORTSC1);
 
-	gpio_direction_output(config->reset_gpio, 0);
 	clk_disable(phy->clk);
+	return gpio_direction_output(config->reset_gpio, 0);
+}
+
+static int	tegra_phy_init(struct usb_phy *x)
+{
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
+	struct tegra_ulpi_config *ulpi_config;
+	int err;
+
+	if (phy_is_ulpi(phy)) {
+		ulpi_config = phy->config;
+		phy->clk = clk_get_sys(NULL, ulpi_config->clk);
+		if (IS_ERR(phy->clk)) {
+			pr_err("%s: can't get ulpi clock\n", __func__);
+			err = -ENXIO;
+			goto err1;
+		}
+		if (!gpio_is_valid(ulpi_config->reset_gpio))
+			ulpi_config->reset_gpio =
+				of_get_named_gpio(phy->dev->of_node,
+						  "nvidia,phy-reset-gpio", 0);
+		if (!gpio_is_valid(ulpi_config->reset_gpio)) {
+			pr_err("%s: invalid reset gpio: %d\n", __func__,
+			       ulpi_config->reset_gpio);
+			err = -EINVAL;
+			goto err1;
+		}
+		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
+		gpio_direction_output(ulpi_config->reset_gpio, 0);
+		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
+		phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
+	} else {
+		err = utmip_pad_open(phy);
+		if (err < 0)
+			goto err1;
+	}
+	return 0;
+err1:
+	clk_disable_unprepare(phy->pll_u);
+	clk_put(phy->pll_u);
+	return err;
+}
+
+static void tegra_usb_phy_close(struct usb_phy *x)
+{
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
+
+	if (phy_is_ulpi(phy))
+		clk_put(phy->clk);
+	else
+		utmip_pad_close(phy);
+	clk_disable_unprepare(phy->pll_u);
+	clk_put(phy->pll_u);
+	kfree(phy);
+}
+
+static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
+{
+	if (phy_is_ulpi(phy))
+		return ulpi_phy_power_on(phy);
+	else
+		return utmi_phy_power_on(phy);
+}
+
+static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
+{
+	if (phy_is_ulpi(phy))
+		return ulpi_phy_power_off(phy);
+	else
+		return utmi_phy_power_off(phy);
+}
+
+static int	tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
+{
+	struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
+	if (suspend)
+		return tegra_usb_phy_power_off(phy);
+	else
+		return tegra_usb_phy_power_on(phy);
 }
 
 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
 {
 	struct tegra_usb_phy *phy;
-	struct tegra_ulpi_config *ulpi_config;
 	unsigned long parent_rate;
 	int i;
 	int err;
@@ -672,6 +747,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 	phy->regs = regs;
 	phy->config = config;
 	phy->mode = phy_mode;
+	phy->dev = dev;
 
 	if (!phy->config) {
 		if (phy_is_ulpi(phy)) {
@@ -704,33 +780,9 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 		goto err1;
 	}
 
-	if (phy_is_ulpi(phy)) {
-		ulpi_config = config;
-		phy->clk = clk_get_sys(NULL, ulpi_config->clk);
-		if (IS_ERR(phy->clk)) {
-			pr_err("%s: can't get ulpi clock\n", __func__);
-			err = -ENXIO;
-			goto err1;
-		}
-		if (!gpio_is_valid(ulpi_config->reset_gpio))
-			ulpi_config->reset_gpio =
-				of_get_named_gpio(dev->of_node,
-						  "nvidia,phy-reset-gpio", 0);
-		if (!gpio_is_valid(ulpi_config->reset_gpio)) {
-			pr_err("%s: invalid reset gpio: %d\n", __func__,
-			       ulpi_config->reset_gpio);
-			err = -EINVAL;
-			goto err1;
-		}
-		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
-		gpio_direction_output(ulpi_config->reset_gpio, 0);
-		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
-		phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
-	} else {
-		err = utmip_pad_open(phy);
-		if (err < 0)
-			goto err1;
-	}
+	phy->u_phy.init = tegra_phy_init;
+	phy->u_phy.shutdown = tegra_usb_phy_close;
+	phy->u_phy.set_suspend = tegra_usb_phy_suspend;
 
 	return phy;
 
@@ -743,24 +795,6 @@ err0:
 }
 EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
-{
-	if (phy_is_ulpi(phy))
-		return ulpi_phy_power_on(phy);
-	else
-		return utmi_phy_power_on(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
-
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
-{
-	if (phy_is_ulpi(phy))
-		ulpi_phy_power_off(phy);
-	else
-		utmi_phy_power_off(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
-
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
@@ -803,15 +837,3 @@ void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 		utmi_phy_clk_enable(phy);
 }
 EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
-
-void tegra_usb_phy_close(struct tegra_usb_phy *phy)
-{
-	if (phy_is_ulpi(phy))
-		clk_put(phy->clk);
-	else
-		utmip_pad_close(phy);
-	clk_disable_unprepare(phy->pll_u);
-	clk_put(phy->pll_u);
-	kfree(phy);
-}
-EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/include/linux/usb/tegra_usb_phy.h
similarity index 86%
rename from arch/arm/mach-tegra/include/mach/usb_phy.h
rename to include/linux/usb/tegra_usb_phy.h
index 935ce9f..176b1ca 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/include/linux/usb/tegra_usb_phy.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/include/mach/usb_phy.h
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
@@ -14,8 +12,8 @@
  *
  */
 
-#ifndef __MACH_USB_PHY_H
-#define __MACH_USB_PHY_H
+#ifndef __TEGRA_USB_PHY_H
+#define __TEGRA_USB_PHY_H
 
 #include <linux/clk.h>
 #include <linux/usb/otg.h>
@@ -59,19 +57,17 @@ struct tegra_usb_phy {
 	enum tegra_usb_phy_mode mode;
 	void *config;
 	struct usb_phy *ulpi;
+	struct usb_phy u_phy;
+	struct device *dev;
 };
 
 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 	void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
 
-int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
-
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
 
-void tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
-
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy);
@@ -81,6 +77,4 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
 
-void tegra_usb_phy_close(struct tegra_usb_phy *phy);
-
-#endif /* __MACH_USB_PHY_H */
+#endif /* __TEGRA_USB_PHY_H */
-- 
1.7.1.1



From tomi.valkeinen at ti.com  Fri Aug 31 03:15:09 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 Aug 2012 10:15:09 +0300
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <5040586D.2020406@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
 <1346344933.2327.43.camel@deskari> <5040586D.2020406@ti.com>
Message-ID: <1346397309.18766.5.camel@lappyti>

On Fri, 2012-08-31 at 11:53 +0530, Archit Taneja wrote:

> The only little problem was that during bootup, when hwmods are setup, 
> only the 'parent' hwmod was able to get reset properly, all the other 
> 'child' hwmods don't have modulemode bits tied to them, and hence 
> weren't able to reset. So we got some error prints.
> 
> Once DSS driver kicks in, the driver ensures the parent is enabled for 
> any child to be enabled, so we don't face the issue again.
> 
> So, if DSS driver is not built in, and if the bootloader left DSS in a 
> bad state, the DSS clocks might remain messed up all the time since 
> hwmod fwk wasn't able to reset them.
> 
> I think this is why we didn't proceed with remove "dss_fck" as a slave 
> clock. If this issue is minor, we could go ahead and remove it.

I wonder if we could handle this with a custom reset function. We
already have a reset func for dss core. If I remember right, the main
point for that is the fact that omap4 doesn't have a softreset for dss
core, so we manually write the default values to registers.

For omap2/3 this would be simple: skip the resets for all other dss
submodules, and dss core's reset would enable all the clocks and set the
softreset bit. This would reset all the submodules also.

Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
manually dss core's registers, and then set softreset bits in all the
submodules. So in this case dss core would need to have information
about the other submodules.

 Tomi

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From lee.jones at linaro.org  Fri Aug 31 03:31:33 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 08:31:33 +0100
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120830230323.GE21501@core.coreip.homeip.net>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
 <20120821164244.GA4672@core.coreip.homeip.net>
 <20120830131202.GG14145@gmail.com>
 <20120830230221.GD21501@core.coreip.homeip.net>
 <20120830230323.GE21501@core.coreip.homeip.net>
Message-ID: <20120831073123.GA13298@gmail.com>

On Thu, Aug 30, 2012 at 04:03:23PM -0700, Dmitry Torokhov wrote:
> On Thu, Aug 30, 2012 at 04:02:21PM -0700, Dmitry Torokhov wrote:
> > On Thu, Aug 30, 2012 at 02:12:04PM +0100, Lee Jones wrote:
> > > > Sorry for the delay. Yes, this shoudl be fine, but since it is
> > > > essentially a revert of the original patch it should be pushed in as
> > > > such.
> > > 
> > > How's this?
> > > 
> > 
> > Excellent.
> 
> I assume you will be merging it with the rest of AB8500 patches, right?

Yes, if that's okay with you of course?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From florian.vaussard at epfl.ch  Fri Aug 31 03:52:53 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 09:52:53 +0200
Subject: [PATCH 0/2] dts for i2c-omap: fix incorrect adapter id
Message-ID: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>

Hello,

This patchset fixes the i2c adapter id on OMAP3 and OMAP4/AM33xx when booting
from a device tree.

Currently, pdev->id is used, regardless of the boot method. The first patch
checks for of_node, and get the id from the alias if a device tree is found.
The boot message is updated accordingly.

The second patch add the necessary aliases for OMAP3, OMAP4 and AM33xx.

This patchset applies on 3.6-rc3 and has been tested on OMAP3 (Gumstix Overo).

Regards,

Florian


Florian Vaussard (2):
  i2c-omap: Fix incorrect adapter id when booting from a device tree
  arm/dts: Add i2c aliases for OMAP3 and OMAP4/AM33xx

 arch/arm/boot/dts/am33xx.dtsi |    3 +++
 arch/arm/boot/dts/omap3.dtsi  |    3 +++
 arch/arm/boot/dts/omap4.dtsi  |    4 ++++
 drivers/i2c/busses/i2c-omap.c |   19 +++++++++++++++----
 4 files changed, 25 insertions(+), 4 deletions(-)

-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri Aug 31 03:52:54 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 09:52:54 +0200
Subject: [PATCH 1/2] i2c-omap: Fix incorrect adapter id when booting from a
 device tree
In-Reply-To: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
References: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1346399575-7285-2-git-send-email-florian.vaussard@epfl.ch>

When booting from a device tree, the omap driver is using pdev->id,
which is incorrect. The proposed patch uses aliases, as done in
omap-serial.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 drivers/i2c/busses/i2c-omap.c |   19 +++++++++++++++----
 1 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 5d19a49..9445d1f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1064,9 +1064,6 @@ omap_i2c_probe(struct platform_device *pdev)
 		goto err_unuse_clocks;
 	}
 
-	dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
-		 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
-
 	adap = &dev->adapter;
 	i2c_set_adapdata(adap, dev);
 	adap->owner = THIS_MODULE;
@@ -1076,8 +1073,22 @@ omap_i2c_probe(struct platform_device *pdev)
 	adap->dev.parent = &pdev->dev;
 	adap->dev.of_node = pdev->dev.of_node;
 
+	if (adap->dev.of_node)
+		adap->nr = of_alias_get_id(adap->dev.of_node, "i2c");
+	else
+		adap->nr = pdev->id;
+
+	if (adap->nr < 0) {
+		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
+				adap->nr);
+		r = -ENODEV;
+		goto err_free_irq;
+	}
+
+	dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
+		 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
+
 	/* i2c device drivers may be active on return from add_adapter() */
-	adap->nr = pdev->id;
 	r = i2c_add_numbered_adapter(adap);
 	if (r) {
 		dev_err(dev->dev, "failure adding adapter\n");
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri Aug 31 03:52:55 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 09:52:55 +0200
Subject: [PATCH 2/2] arm/dts: Add i2c aliases for OMAP3 and OMAP4/AM33xx
In-Reply-To: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
References: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1346399575-7285-3-git-send-email-florian.vaussard@epfl.ch>

I2C aliases need to be set, for the omap-i2c driver to get a correct adapter id.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/am33xx.dtsi |    3 +++
 arch/arm/boot/dts/omap3.dtsi  |    3 +++
 arch/arm/boot/dts/omap4.dtsi  |    4 ++++
 3 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c4..ff2d879 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -20,6 +20,9 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
 	};
 
 	cpus {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 8109471..a7d2f83 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -18,6 +18,9 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
 	};
 
 	cpus {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb..496c7ce 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -25,6 +25,10 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
 	};
 
 	cpus {
-- 
1.7.5.4



From dirk.behme at de.bosch.com  Fri Aug 31 04:02:47 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 31 Aug 2012 10:02:47 +0200
Subject: [PATCH v2 2/2] tty: serial: imx: don't reinit clock in
 imx_setup_ufcr()
Message-ID: <1346400167-24669-1-git-send-email-dirk.behme@de.bosch.com>

Remove the clock configuration from imx_setup_ufcr(). This
isn't needed here and will cause garbage output if done.

To be be sure that we only touch the bits we want (TXTL and RXTL)
we have to mask out all other bits of the UFCR register. Add
one non-existing bit macro for this, too (bit 6, DCEDTE on i.MX6).

Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>
CC: Shawn Guo <shawn.guo at linaro.org>
CC: Sascha Hauer <s.hauer at pengutronix.de>
CC: Troy Kisky <troy.kisky at boundarydevices.com>
CC: Xinyu Chen <xinyu.chen at freescale.com>
CC: <stable at vger.kernel.org>
---
Changes in v2: Instead of disabling imx_setup_ufcr() with an
ifndef CONFIG_SERIAL_CORE_CONSOLE, remove the unneeded clock 
configuration from imx_setup_ufcr() itself as proposed by Troy Kisky.

Note: If this patch is accepted, it should go to the same stable
kernels as patch #1 of this series. So most probably 3.4 and 3.5.

 drivers/tty/serial/imx.c |   18 ++++--------------
 1 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 908178f..e309e8b 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -132,6 +132,7 @@
 #define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
 #define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
+#define  UFCR_DCEDTE	 (1<<6)  /* DCE/DTE mode select */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UFCR_RFDIV_REG(x)	(((x) < 7 ? 6 - (x) : 6) << 7)
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
@@ -667,22 +668,11 @@ static void imx_break_ctl(struct uart_port *port, int break_state)
 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
 {
 	unsigned int val;
-	unsigned int ufcr_rfdiv;
-
-	/* set receiver / transmitter trigger level.
-	 * RFDIV is set such way to satisfy requested uartclk value
-	 */
-	val = TXTL << 10 | RXTL;
-	ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2)
-			/ sport->port.uartclk;
-
-	if(!ufcr_rfdiv)
-		ufcr_rfdiv = 1;
-
-	val |= UFCR_RFDIV_REG(ufcr_rfdiv);
 
+	/* set receiver / transmitter trigger level */
+	val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
+	val |= TXTL << UFCR_TXTL_SHF | RXTL;
 	writel(val, sport->port.membase + UFCR);
-
 	return 0;
 }
 
-- 
1.7.0.4



From a0393947 at ti.com  Fri Aug 31 04:20:31 2012
From: a0393947 at ti.com (Archit Taneja)
Date: Fri, 31 Aug 2012 13:50:31 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <1346397309.18766.5.camel@lappyti>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
 <1346344933.2327.43.camel@deskari> <5040586D.2020406@ti.com>
 <1346397309.18766.5.camel@lappyti>
Message-ID: <504073CF.6010804@ti.com>

On Friday 31 August 2012 12:45 PM, Tomi Valkeinen wrote:
> On Fri, 2012-08-31 at 11:53 +0530, Archit Taneja wrote:
>
>> The only little problem was that during bootup, when hwmods are setup,
>> only the 'parent' hwmod was able to get reset properly, all the other
>> 'child' hwmods don't have modulemode bits tied to them, and hence
>> weren't able to reset. So we got some error prints.
>>
>> Once DSS driver kicks in, the driver ensures the parent is enabled for
>> any child to be enabled, so we don't face the issue again.
>>
>> So, if DSS driver is not built in, and if the bootloader left DSS in a
>> bad state, the DSS clocks might remain messed up all the time since
>> hwmod fwk wasn't able to reset them.
>>
>> I think this is why we didn't proceed with remove "dss_fck" as a slave
>> clock. If this issue is minor, we could go ahead and remove it.
>
> I wonder if we could handle this with a custom reset function. We
> already have a reset func for dss core. If I remember right, the main
> point for that is the fact that omap4 doesn't have a softreset for dss
> core, so we manually write the default values to registers.
>
> For omap2/3 this would be simple: skip the resets for all other dss
> submodules, and dss core's reset would enable all the clocks and set the
> softreset bit. This would reset all the submodules also.
>
> Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
> manually dss core's registers, and then set softreset bits in all the
> submodules. So in this case dss core would need to have information
> about the other submodules.

The is a good idea. I don't clearly understand your approach though. Are 
you saying we have a custom reset function for only dss core? And reset 
the submodules in it manually?

An alternative approach would be to implement custom reset functions for 
each submodule(or each hwmod), and in the beginning of every reset 
function, add a hack to enable MODULEMODE bits(since we don't want hwmod 
fwk to touch MODULEMODE for the DSS submodules), and then set the soft 
reset bits.

Your approach would ensure that we get a clean reset of DSS, but it 
would still give the annoying prints when each of the submodule tries to 
reset itself.

Archit


From tomi.valkeinen at ti.com  Fri Aug 31 04:27:23 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 Aug 2012 11:27:23 +0300
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <504073CF.6010804@ti.com>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
 <1346344933.2327.43.camel@deskari> <5040586D.2020406@ti.com>
 <1346397309.18766.5.camel@lappyti> <504073CF.6010804@ti.com>
Message-ID: <1346401643.32389.4.camel@deskari>

On Fri, 2012-08-31 at 13:50 +0530, Archit Taneja wrote:
> On Friday 31 August 2012 12:45 PM, Tomi Valkeinen wrote:
> > On Fri, 2012-08-31 at 11:53 +0530, Archit Taneja wrote:
> >
> >> The only little problem was that during bootup, when hwmods are setup,
> >> only the 'parent' hwmod was able to get reset properly, all the other
> >> 'child' hwmods don't have modulemode bits tied to them, and hence
> >> weren't able to reset. So we got some error prints.
> >>
> >> Once DSS driver kicks in, the driver ensures the parent is enabled for
> >> any child to be enabled, so we don't face the issue again.
> >>
> >> So, if DSS driver is not built in, and if the bootloader left DSS in a
> >> bad state, the DSS clocks might remain messed up all the time since
> >> hwmod fwk wasn't able to reset them.
> >>
> >> I think this is why we didn't proceed with remove "dss_fck" as a slave
> >> clock. If this issue is minor, we could go ahead and remove it.
> >
> > I wonder if we could handle this with a custom reset function. We
> > already have a reset func for dss core. If I remember right, the main
> > point for that is the fact that omap4 doesn't have a softreset for dss
> > core, so we manually write the default values to registers.
> >
> > For omap2/3 this would be simple: skip the resets for all other dss
> > submodules, and dss core's reset would enable all the clocks and set the
> > softreset bit. This would reset all the submodules also.
> >
> > Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
> > manually dss core's registers, and then set softreset bits in all the
> > submodules. So in this case dss core would need to have information
> > about the other submodules.
> 
> The is a good idea. I don't clearly understand your approach though. Are 
> you saying we have a custom reset function for only dss core? And reset 
> the submodules in it manually?

Yes.

> An alternative approach would be to implement custom reset functions for 
> each submodule(or each hwmod), and in the beginning of every reset 
> function, add a hack to enable MODULEMODE bits(since we don't want hwmod 
> fwk to touch MODULEMODE for the DSS submodules), and then set the soft 
> reset bits.

I thought about that also. We'd need reset functions for all of them,
and for omap2/3 we'd just reset the submodules again as they have
already been reset with the dss core reset.

The dss submodule resets are a bit linked. For omap2/3 the connection is
obvious as dss core reset resets also the submodules, and for omap4 we
have this requirement for the modulemode. That's why I though it'd be
perhaps cleaner to handle the reset of the DSS block as a whole, in one
place.

> Your approach would ensure that we get a clean reset of DSS, but it 
> would still give the annoying prints when each of the submodule tries to 
> reset itself.

The other submodules would not be reset by the hwmod framework at all,
so there wouldn't be prints. I think there's a flag for that.

 Tomi

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From a0393947 at ti.com  Fri Aug 31 04:28:16 2012
From: a0393947 at ti.com (Archit Taneja)
Date: Fri, 31 Aug 2012 13:58:16 +0530
Subject: [PATCH v4 2/3] ARM: omap: hwmod: get rid of all
 omap_clk_get_by_name usage
In-Reply-To: <1346401643.32389.4.camel@deskari>
References: <1346230576-20004-1-git-send-email-rnayak@ti.com>
 <1346230576-20004-3-git-send-email-rnayak@ti.com>
 <CAJOA=zM2sFsrdohooKp1+zsV_AK6dKnoN37+Gs2oskBUK4J00w@mail.gmail.com>
 <503F26A4.3050902@ti.com> <503F5517.4010100@ti.com>
 <1346344933.2327.43.camel@deskari> <5040586D.2020406@ti.com>
 <1346397309.18766.5.camel@lappyti> <504073CF.6010804@ti.com>
 <1346401643.32389.4.camel@deskari>
Message-ID: <504075A0.7010708@ti.com>

On Friday 31 August 2012 01:57 PM, Tomi Valkeinen wrote:
> On Fri, 2012-08-31 at 13:50 +0530, Archit Taneja wrote:
>> On Friday 31 August 2012 12:45 PM, Tomi Valkeinen wrote:
>>> On Fri, 2012-08-31 at 11:53 +0530, Archit Taneja wrote:
>>>
>>>> The only little problem was that during bootup, when hwmods are setup,
>>>> only the 'parent' hwmod was able to get reset properly, all the other
>>>> 'child' hwmods don't have modulemode bits tied to them, and hence
>>>> weren't able to reset. So we got some error prints.
>>>>
>>>> Once DSS driver kicks in, the driver ensures the parent is enabled for
>>>> any child to be enabled, so we don't face the issue again.
>>>>
>>>> So, if DSS driver is not built in, and if the bootloader left DSS in a
>>>> bad state, the DSS clocks might remain messed up all the time since
>>>> hwmod fwk wasn't able to reset them.
>>>>
>>>> I think this is why we didn't proceed with remove "dss_fck" as a slave
>>>> clock. If this issue is minor, we could go ahead and remove it.
>>>
>>> I wonder if we could handle this with a custom reset function. We
>>> already have a reset func for dss core. If I remember right, the main
>>> point for that is the fact that omap4 doesn't have a softreset for dss
>>> core, so we manually write the default values to registers.
>>>
>>> For omap2/3 this would be simple: skip the resets for all other dss
>>> submodules, and dss core's reset would enable all the clocks and set the
>>> softreset bit. This would reset all the submodules also.
>>>
>>> Omap4 is more tricky. I guess we'd need to enable all the clocks, clear
>>> manually dss core's registers, and then set softreset bits in all the
>>> submodules. So in this case dss core would need to have information
>>> about the other submodules.
>>
>> The is a good idea. I don't clearly understand your approach though. Are
>> you saying we have a custom reset function for only dss core? And reset
>> the submodules in it manually?
>
> Yes.
>
>> An alternative approach would be to implement custom reset functions for
>> each submodule(or each hwmod), and in the beginning of every reset
>> function, add a hack to enable MODULEMODE bits(since we don't want hwmod
>> fwk to touch MODULEMODE for the DSS submodules), and then set the soft
>> reset bits.
>
> I thought about that also. We'd need reset functions for all of them,
> and for omap2/3 we'd just reset the submodules again as they have
> already been reset with the dss core reset.
>
> The dss submodule resets are a bit linked. For omap2/3 the connection is
> obvious as dss core reset resets also the submodules, and for omap4 we
> have this requirement for the modulemode. That's why I though it'd be
> perhaps cleaner to handle the reset of the DSS block as a whole, in one
> place.
>
>> Your approach would ensure that we get a clean reset of DSS, but it
>> would still give the annoying prints when each of the submodule tries to
>> reset itself.
>
> The other submodules would not be reset by the hwmod framework at all,
> so there wouldn't be prints. I think there's a flag for that.

Oh, yeah. I didn't think of it that way, we could just 'not reset' the 
DSS submodule hwmod using this flag.

If we do that, then your approach sounds good.

Archit



From tomi.valkeinen at ti.com  Fri Aug 31 04:30:46 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 31 Aug 2012 11:30:46 +0300
Subject: [PATCH 0/3] ARM: OMAP2/3: DSS HWMOD fixes
In-Reply-To: <alpine.DEB.2.00.1207040610310.6760@utopia.booyaka.com>
References: <1336645264-909-1-git-send-email-tomi.valkeinen@ti.com>
 <alpine.DEB.2.00.1206271416420.27496@utopia.booyaka.com>
 <alpine.DEB.2.00.1207040610310.6760@utopia.booyaka.com>
Message-ID: <1346401846.32389.7.camel@deskari>

On Wed, 2012-07-04 at 06:11 -0600, Paul Walmsley wrote:
> Hi Tomi
> 
> On Wed, 27 Jun 2012, Paul Walmsley wrote:
> 
> > On Thu, 10 May 2012, Tomi Valkeinen wrote:
> > 
> > > These patches fix DSS hwmod data related to sysc flags. I haven't seen any
> > > problem produced by these missing bits, but by looking at the TRM it's clear
> > > that they should be defined.
> > > 
> > > However, applying these will cause additional warnings to show during boot:
> > > 
> > > omap_hwmod: dss_dispc: softreset failed (waited 10000 usec)
> > > omap_hwmod: dss_rfbi: softreset failed (waited 10000 usec)
> > > 
> > > Most likely the softreset fails even now, but as there's no check to verify it,
> > > no warnings are visible.
> > > 
> > > I think the reason for the failing softreset is the same problem as we have on
> > > OMAP4: dss_core hwmod should be enabled before other dss hwmods can be enabled
> > > (and reset).
> > 
> > Thanks, queued for 3.6.
> > 
> > Not sure what to do about the softreset issues at the moment, due to 
> > competing priorities.  But for sure the data should match the hardware.
> 
> I've dropped these for 3.6 since they cause a PM regression during a 
> system suspend test:
> 
> [   39.721282] Powerdomain (dss_pwrdm) didn't enter target state 1
> 
> Probably before we can pull these in, we need to figure out what's going 
> on there.

Just tested with current mainline
(155e36d40cf31c17f2b629fc2f2f5527e4cfc324) on omap3 overo, with DSS,
USB, MMC disabled in the kernel config:

# echo mem > /sys/power/state 
[   14.140472] PM: Syncing filesystems ... done.
[   14.154205] Freezing user space processes ... (elapsed 0.02 seconds)
done.
[   14.184173] Freezing remaining freezable tasks ... (elapsed 0.02
seconds) done.
[   14.234283] PM: suspend of devices complete after 13.977 msecs
[   14.244567] PM: late suspend of devices complete after 4.028 msecs
[   14.257110] PM: noirq suspend of devices complete after 6.011 msecs
[   14.263885] Disabling non-boot CPUs ...
[   15.986541] Powerdomain (iva2_pwrdm) didn't enter target state 1
[   15.992858] Powerdomain (dss_pwrdm) didn't enter target state 1
[   15.999084] Powerdomain (per_pwrdm) didn't enter target state 1
[   16.005310] Powerdomain (core_pwrdm) didn't enter target state 1
[   16.011627] Powerdomain (usbhost_pwrdm) didn't enter target state 1
[   16.018188] Could not enter target state in pm_suspend
[   16.026580] PM: noirq resume of devices complete after 2.807 msecs
[   16.037597] PM: early resume of devices complete after 2.655 msecs

[   16.054870] PM: resume of devices complete after 10.620 msecs
[   16.065643] Restarting tasks ... done.

So things don't look correct even without my patches. Does the suspend
work for you?

 Tomi

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From dirk.behme at de.bosch.com  Fri Aug 31 04:55:11 2012
From: dirk.behme at de.bosch.com (Dirk Behme)
Date: Fri, 31 Aug 2012 10:55:11 +0200
Subject: [PATCH] spi/imx: set the inactive state of the clock according to the
 clock polarity
Message-ID: <1346403311-25080-1-git-send-email-dirk.behme@de.bosch.com>

From: Knut Wohlrab <knut.wohlrab at de.bosch.com>

There are SPI devices which need a SPI clock with active low polarity and
high inactive state.

Add the setting of the inactive state ECSPIx_CONFIGREG:SCLK CTL
according to the clock polarity ECSPIx_CONFIGREG:SCLK POL:

DT without "spi-cpol" = 0 = clock active high polarity = inactive state low
DT with    "spi-cpol" = 1 = clock active low  polarity = inactive state high

Signed-off-by: Knut Wohlrab <knut.wohlrab at de.bosch.com>
---

Question: Are there real world examples for a need of an individual setting of
clock polarity/inactive state?

 drivers/spi/spi-imx.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e834ff8..d64655b 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -197,6 +197,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
 #define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
+#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
 
 #define MX51_ECSPI_INT		0x10
 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
@@ -287,9 +288,10 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
 	if (config->mode & SPI_CPHA)
 		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
 
-	if (config->mode & SPI_CPOL)
+	if (config->mode & SPI_CPOL) {
 		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
-
+		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
+	}
 	if (config->mode & SPI_CS_HIGH)
 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
 
-- 
1.7.0.4



From gururaja.hebbar at ti.com  Fri Aug 31 04:55:39 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 Aug 2012 08:55:39 +0000
Subject: [PATCH V3] ASoC: Davinci: machine: Add device tree binding
References: <1346148830-2965-1-git-send-email-gururaja.hebbar@ti.com> 
Message-ID: <1BAFE6F6C881BF42822005164F1491C33EA70165@DBDE01.ent.ti.com>


Gentle Ping. Any updates about this version or can it be pulled into the tree.

On Thu, Aug 30, 2012 at 09:29:55, Hebbar, Gururaja wrote:
> 
> Hi,
> 
> Gentle Ping.
> 
> 
> On Tue, Aug 28, 2012 at 15:43:50, Hebbar, Gururaja wrote:
> > Device tree support for Davinci Machine driver
> > 
> > When the board boots with device tree, the driver will receive card,
> > codec, dai interface details (like the card name, DAPM routing map,
> > phandle for the audio components described in the dts file, codec mclk
> > speed).
> > The card will be set up based on this information.
> > Since the routing is provided via DT we can mark the card fully routed
> > so core can take care of disconnecting the unused pins.
> > 
> > When here, code indentation and comment style is also fixed
> > 
> > Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
> > ---
> > Changes from V1:
> > 	- Change DT parameter from "ti,codec-clock" to "ti,codec-clock-rate"
> > 	- add more explanation to DT parameters
> > 
> > Changes from V2:
> > 	- Update Documentation details
> > 	- Remove irrelevant commit message
> > 
> > :000000 100644 0000000... b248014... A	Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> > :100644 100644 ab0ad45... ca2a547... M	sound/soc/davinci/davinci-evm.c
> >  .../bindings/sound/davinci-evm-audio.txt           |   66 +++++++
> >  sound/soc/davinci/davinci-evm.c                    |  185 +++++++++++++++++--
> >  2 files changed, 231 insertions(+), 20 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> > new file mode 100644
> > index 0000000..b248014
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
> > @@ -0,0 +1,66 @@
> > +* Texas Instruments SoC audio setups with TLV320AIC3X Codec
> > +
> > +Required properties:
> > +- compatible : "ti,davinci-evm-audio"
> > +- ti,model : The user-visible name of this sound complex.
> > +- ti,audio-routing : A list of the connections between audio components.
> > +  Each entry is a pair of strings, the first being the connection's sink,
> > +  the second being the connection's source. Valid names for sources and
> > +  sinks are the codec's pins, and the jacks on the board:
> > +
> > +  Codec pins:
> > +
> > +  * MIC3L
> > +  * MIC3R
> > +  * LINE1L
> > +  * LINE2L
> > +  * LINE1R
> > +  * LINE2R
> > +
> > +  Board connectors:
> > +
> > +  * Headphone Jack
> > +  * Line Out
> > +  * Mic Jack
> > +
> > +- ti,mcasp-controller : The phandle of the McASP controller
> > +- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
> > +- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
> > +
> > +- dai-data		: A list of DAI data used by SOC code to register
> > +			  DAI, Codecs platform.
> > +			  The string index "should" be as shown below.
> > +dai-data =
> > +"<DAI Name>", 		"<DAI Stream Name>",
> > +"<CODEC DAI Name>",	"<true if evm_aic3x_init is required, else false>",
> > +"<evm ops required (evm_ops or evm_spdif_ops)>";
> > +
> > +Here fields
> > +"<DAI Name>"		: used to indicate the DAI Name
> > +"<DAI Stream Name>"	: used to indicate the Stream Name
> > +"<CODEC DAI Name>"	: used to bind the link between Codec DAI and ASOC DAI
> > +
> > +Machine related options
> > +"<true/false>"		: Whether the machine specific initialization
> > +			: evm_aic3x_init() is required
> > +
> > +"<evm ops required>"	: Which hardware ops function is to be used.
> > +			: (evm_ops or evm_spdif_ops)
> > +			: use evm-spdif-ops if DAI is working in DIT mode
> > +			: else use evm-ops. These ops setup hw param callbacks
> > +			: which are used to setup CODEC/cpu DAI configuration
> > +			: and codec system clock.
> > +
> > +Example:
> > +
> > +sound {
> > +	compatible = "ti,davinci-evm-audio";
> > +	ti,model = "DA830 EVM";
> > +	ti,audio-codec = <&tlv320aic3x>;
> > +	ti,mcasp-controller = <&mcasp1>;
> > +	ti,codec-clock-rate = <12000000>;
> > +	dai-data =
> > +		"TLV320AIC3X", 		"AIC3X",
> > +		"tlv320aic3x-hifi",	"true",
> > +		"evm-ops";
> > +};
> > diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
> > index ab0ad45..ca2a547 100644
> > --- a/sound/soc/davinci/davinci-evm.c
> > +++ b/sound/soc/davinci/davinci-evm.c
> > @@ -34,27 +34,38 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
> >  	struct snd_soc_pcm_runtime *rtd = substream->private_data;
> >  	struct snd_soc_dai *codec_dai = rtd->codec_dai;
> >  	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
> > +	struct snd_soc_codec *codec = rtd->codec;
> > +	struct snd_soc_card *soc_card = codec->card;
> > +	struct device_node *np = soc_card->dev->of_node;
> >  	int ret = 0;
> >  	unsigned sysclk;
> >  
> > -	/* ASP1 on DM355 EVM is clocked by an external oscillator */
> > -	if (machine_is_davinci_dm355_evm() || machine_is_davinci_dm6467_evm() ||
> > -	    machine_is_davinci_dm365_evm())
> > -		sysclk = 27000000;
> > -
> > -	/* ASP0 in DM6446 EVM is clocked by U55, as configured by
> > -	 * board-dm644x-evm.c using GPIOs from U18.  There are six
> > -	 * options; here we "know" we use a 48 KHz sample rate.
> > -	 */
> > -	else if (machine_is_davinci_evm())
> > -		sysclk = 12288000;
> > -
> > -	else if (machine_is_davinci_da830_evm() ||
> > -				machine_is_davinci_da850_evm())
> > -		sysclk = 24576000;
> > -
> > -	else
> > -		return -EINVAL;
> > +	if (np) {
> > +		ret = of_property_read_u32(np, "ti,codec-clock-rate", &sysclk);
> > +		if (ret < 0)
> > +			return ret;
> > +	} else {
> > +		/* ASP1 on DM355 EVM is clocked by an external oscillator */
> > +		if (machine_is_davinci_dm355_evm() ||
> > +			machine_is_davinci_dm6467_evm() ||
> > +			machine_is_davinci_dm365_evm())
> > +			sysclk = 27000000;
> > +
> > +		/*
> > +		 * ASP0 in DM6446 EVM is clocked by U55, as configured by
> > +		 * board-dm644x-evm.c using GPIOs from U18.  There are six
> > +		 * options; here we "know" we use a 48 KHz sample rate.
> > +		 */
> > +		else if (machine_is_davinci_evm())
> > +			sysclk = 12288000;
> > +
> > +		else if (machine_is_davinci_da830_evm() ||
> > +					machine_is_davinci_da850_evm())
> > +			sysclk = 24576000;
> > +
> > +		else
> > +			return -EINVAL;
> > +	}
> >  
> >  	/* set codec DAI configuration */
> >  	ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
> > @@ -127,13 +138,22 @@ static int evm_aic3x_init(struct snd_soc_pcm_runtime *rtd)
> >  {
> >  	struct snd_soc_codec *codec = rtd->codec;
> >  	struct snd_soc_dapm_context *dapm = &codec->dapm;
> > +	struct device_node *np = codec->card->dev->of_node;
> > +	int ret;
> >  
> >  	/* Add davinci-evm specific widgets */
> >  	snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
> >  				  ARRAY_SIZE(aic3x_dapm_widgets));
> >  
> > -	/* Set up davinci-evm specific audio path audio_map */
> > -	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
> > +	if (np) {
> > +		ret = snd_soc_of_parse_audio_routing(codec->card,
> > +							"ti,audio-routing");
> > +		if (ret)
> > +			return ret;
> > +	} else {
> > +		/* Set up davinci-evm specific audio path audio_map */
> > +		snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
> > +	}
> >  
> >  	/* not connected */
> >  	snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
> > @@ -282,6 +302,113 @@ static struct snd_soc_card da850_snd_soc_card = {
> >  	.num_links = 1,
> >  };
> >  
> > +#if defined(CONFIG_OF)
> > +/*
> > + * This struct is just used as place holder. It will be filled with
> > + * data from dt node
> > + */
> > +static struct snd_soc_dai_link evm_dai = {
> > +};
> > +
> > +/* davinci evm audio machine driver */
> > +static struct snd_soc_card evm_soc_card = {
> > +	.owner = THIS_MODULE,
> > +	.dai_link = &evm_dai,
> > +	.num_links = 1,
> > +};
> > +
> > +static int davinci_evm_probe(struct platform_device *pdev)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	const char *stringPtr, *propname;
> > +	u32 val;
> > +	int ret = 0;
> > +
> > +	propname = "dai-data";
> > +	val = of_property_count_strings(np, propname);
> > +	if (val < 0)
> > +		return val;
> > +
> > +	ret = of_property_read_string_index(np, propname, 0, &evm_dai.name);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = of_property_read_string_index(np, propname, 1,
> > +						&evm_dai.stream_name);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = of_property_read_string_index(np, propname, 2,
> > +						&evm_dai.codec_dai_name);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = of_property_read_string_index(np, propname, 3, &stringPtr);
> > +	if (ret < 0)
> > +		return ret;
> > +	else
> > +		if (strcasecmp(stringPtr, "true") == 0)
> > +			evm_dai.init = evm_aic3x_init;
> > +
> > +	ret = of_property_read_string_index(np, propname, 4, &stringPtr);
> > +	if (ret < 0) {
> > +		return ret;
> > +	} else {
> > +		if (strcasecmp(stringPtr, "evm-ops") == 0)
> > +			evm_dai.ops = &evm_ops;
> > +		else if (strcasecmp(stringPtr, "evm-spdif-ops") == 0)
> > +			evm_dai.ops = &evm_spdif_ops;
> > +	}
> > +
> > +	evm_dai.codec_of_node = of_parse_phandle(np, "ti,audio-codec", 0);
> > +	if (!evm_dai.codec_of_node)
> > +		return -EINVAL;
> > +
> > +	evm_dai.cpu_dai_of_node = of_parse_phandle(np,
> > +						"ti,mcasp-controller", 0);
> > +	if (!evm_dai.cpu_dai_of_node)
> > +		return -EINVAL;
> > +
> > +	evm_dai.platform_of_node = evm_dai.cpu_dai_of_node;
> > +
> > +	evm_soc_card.dev = &pdev->dev;
> > +	ret = snd_soc_of_parse_card_name(&evm_soc_card, "ti,model");
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = snd_soc_register_card(&evm_soc_card);
> > +	if (ret)
> > +		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
> > +
> > +	return ret;
> > +}
> > +
> > +static int __devexit davinci_evm_remove(struct platform_device *pdev)
> > +{
> > +	struct snd_soc_card *card = platform_get_drvdata(pdev);
> > +
> > +	snd_soc_unregister_card(card);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id davinci_evm_dt_ids[] = {
> > +	{ .compatible = "ti,davinci-evm-audio", },
> > +	{ /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, davinci_mcasp_dt_ids);
> > +
> > +static struct platform_driver davinci_evm_driver = {
> > +	.probe		= davinci_evm_probe,
> > +	.remove		= __devexit_p(davinci_evm_remove),
> > +	.driver		= {
> > +		.name	= "davinci_evm",
> > +		.owner	= THIS_MODULE,
> > +		.of_match_table = of_match_ptr(davinci_evm_dt_ids),
> > +	},
> > +};
> > +#endif
> > +
> >  static struct platform_device *evm_snd_device;
> >  
> >  static int __init evm_init(void)
> > @@ -289,6 +416,14 @@ static int __init evm_init(void)
> >  	struct snd_soc_card *evm_snd_dev_data;
> >  	int index;
> >  	int ret;
> > +#if defined(CONFIG_OF)
> > +	struct device_node *np;
> > +
> > +	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
> > +	if (np) {
> > +		return platform_driver_register(&davinci_evm_driver);
> > +	}
> > +#endif
> >  
> >  	if (machine_is_davinci_evm()) {
> >  		evm_snd_dev_data = &dm6446_snd_soc_card_evm;
> > @@ -325,6 +460,16 @@ static int __init evm_init(void)
> >  
> >  static void __exit evm_exit(void)
> >  {
> > +#if defined(CONFIG_OF)
> > +	struct device_node *np;
> > +
> > +	np = of_find_compatible_node(NULL, NULL, "ti,davinci-evm-audio");
> > +	if (np) {
> > +		platform_driver_unregister(&davinci_evm_driver);
> > +		return;
> > +	}
> > +#endif
> > +
> >  	platform_device_unregister(evm_snd_device);
> >  }
> >  
> > -- 
> > 1.7.1
> > 
> > 
> 
> 
> Regards, 
> Gururaja
> 


Regards, 
Gururaja


From stigge at antcom.de  Fri Aug 31 05:05:08 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 31 Aug 2012 11:05:08 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <20120829172820.43bbe68e@eb-e6520>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de> <503E3331.8050203@antcom.de>
 <20120829172820.43bbe68e@eb-e6520>
Message-ID: <50407E44.5080408@antcom.de>

Hi Eric,

On 08/29/2012 05:28 PM, Eric B?nard wrote:
> Le Wed, 29 Aug 2012 17:20:17 +0200,
> Roland Stigge <stigge at antcom.de> a ?crit :
>> Using  ".ecclayout_4k = &nandv2_hw_eccoob_4k" also doesn't work. So is
>> there any hint how I can proceed from here? Any plans or hint regarding
>> the "XXX"?
>>
> you may need something like this patch from barebox :
> http://git.pengutronix.de/?p=barebox.git;a=commit;h=632c45795065e6a7471ab82be38e808eb6204341

Thank you for the link!

I tried to port this on top of Sascha's patches for imx53, only for mxc v3 for now, as below.

Unfortunately, I still get:

...
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
UnCorrectable RS-ECC Error
...

from mxc_nand.c's mxc_nand_correct_data_v2_v3(). Maybe there's still sth. missing in the
error correction code?

Tracing reveals that in mxc_nand_command()'s switch statement, NAND_CMD_READID is handled,
but the NAND_CMD_PARAM case never gets triggered. (Under which circumstances is this
supposed to happen?) Further, I still wonder why the bootloader identifies the NAND as:

NAND:  512 MiB
Manufacturer      : Micron (0x2c)
Device Code       : 0xdc
Cell Technology   : SLC
Chip Size         : 512 MiB
Pages per Block   : 64
Page Geometry     : 4096+218
ECC Strength      : 8 bits
ECC Size          : 512 B
Data Setup Time   : 20 ns
Data Hold Time    : 10 ns
Address Setup Time: 10 ns
GPMI Sample Delay : 6 ns
tREA              : Unknown
tRLOH             : Unknown
tRHOH             : Unknown
Description       : MT29F4G08ABAEA

But Linux says:

NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron NAND 512MiB 3,3V 8-bit), page size: 4096, OOB size: 128

(See OOB size 128 vs. 218).

Thanks in advance,

Roland


---
 drivers/mtd/nand/mxc_nand.c |   36 ++++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

--- linux-2.6.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-2.6/drivers/mtd/nand/mxc_nand.c
@@ -150,6 +150,7 @@ struct mxc_nand_devtype_data {
        void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
        void (*send_page)(struct mtd_info *, unsigned int);
        void (*send_read_id)(struct mxc_nand_host *);
+       void (*send_read_param)(struct mxc_nand_host *);
        uint16_t (*get_dev_status)(struct mxc_nand_host *);
        int (*check_int)(struct mxc_nand_host *);
        void (*irq_control)(struct mxc_nand_host *, int);
@@ -543,6 +544,16 @@ static void send_read_id_v3(struct mxc_n
        memcpy32_fromio(host->data_buf, host->main_area0, 16);
 }
 
+static void send_read_param_v3(struct mxc_nand_host *host)
+{
+       /* Read param into main buffer */
+       writel(NFC_OUTPUT, NFC_V3_LAUNCH);
+
+       wait_op_done(host, true);
+
+       memcpy32_fromio(host->data_buf, host->main_area0, 1024);
+}
+
 /* Request the NANDFC to perform a read of the NAND device ID. */
 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 {
@@ -741,6 +752,10 @@ static void mxc_nand_read_buf(struct mtd
 
        n = min(n, len);
 
+       /* handle the read param special case */
+       if ((mtd->writesize == 0) && (len != 0))
+               n = len;
+
        memcpy(buf, host->data_buf + col, n);
 
        host->buf_start += n;
@@ -842,9 +857,12 @@ static void mxc_do_addr_cycle(struct mtd
                 * MXC NANDFC can only perform full page+spare or
                 * spare-only read/write.  When the upper layers
                 * perform a read/write buf operation, the saved column
-                 * address is used to index into the full page.
+                * address is used to index into the full page.
+                *
+                * The colum address must be sent to the flash in
+                * order to get the ONFI header (0x20)
                 */
-               host->devtype_data->send_addr(host, 0, page_addr == -1);
+               host->devtype_data->send_addr(host, column, page_addr == -1);
                if (mtd->writesize > 512)
                        /* another col addr cycle for 2k page */
                        host->devtype_data->send_addr(host, 0, false);
@@ -998,9 +1016,11 @@ static void preset_v3(struct mtd_info *m
 
        writel(0, NFC_V3_IPC);
 
+       /* if the flash has a 224 oob, the NFC must be configured to 218 */
        config2 = NFC_V3_CONFIG2_ONE_CYCLE |
                NFC_V3_CONFIG2_2CMD_PHASES |
-               NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
+               NFC_V3_CONFIG2_SPAS(((mtd->oobsize > 218) ?
+                                    218 : mtd->oobsize) >> 1) |
                NFC_V3_CONFIG2_ST_CMD(0x70) |
                NFC_V3_CONFIG2_INT_MSK |
                NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
@@ -1124,6 +1144,13 @@ static void mxc_nand_command(struct mtd_
                host->buf_start = column;
                break;
 
+       case NAND_CMD_PARAM:
+               host->devtype_data->send_cmd(host, command, true);
+               mxc_do_addr_cycle(mtd, column, page_addr);
+               host->devtype_data->send_read_param(host);
+               host->buf_start = column;
+               break;
+
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
                host->devtype_data->send_cmd(host, command, false);
@@ -1271,13 +1298,14 @@ static const struct mxc_nand_devtype_dat
        .send_addr = send_addr_v3,
        .send_page = send_page_v3,
        .send_read_id = send_read_id_v3,
+       .send_read_param = send_read_param_v3,
        .get_dev_status = get_dev_status_v3,
        .check_int = check_int_v3,
        .irq_control = irq_control_v3,
        .get_ecc_status = get_ecc_status_v3,
        .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
        .ecclayout_2k = &nandv2_hw_eccoob_largepage,
-       .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
+       .ecclayout_4k = &nandv2_hw_eccoob_4k,
        .select_chip = mxc_nand_select_chip_v1_v3,
        .correct_data = mxc_nand_correct_data_v2_v3,
        .irqpending_quirk = 0,


From b-cousson at ti.com  Fri Aug 31 05:14:20 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 Aug 2012 11:14:20 +0200
Subject: [PATCH 1/2] i2c-omap: Fix incorrect adapter id when booting from
 a device tree
In-Reply-To: <1346399575-7285-2-git-send-email-florian.vaussard@epfl.ch>
References: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
 <1346399575-7285-2-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <5040806C.9080003@ti.com>

Hi Florian,

On 08/31/2012 09:52 AM, Florian Vaussard wrote:
> When booting from a device tree, the omap driver is using pdev->id,
> which is incorrect. 

Not really, see below...

> The proposed patch uses aliases, as done in omap-serial.

Mmm, but is it really needed?
In the case of serial the id is important because of the tty number used
as device interface.
In the case of I2C, the id is mostly irrelevant.

In fact, using the pdev->id = -1 was used on purpose to have a dynamic
assignment:

int i2c_add_numbered_adapter(struct i2c_adapter *adap)
...
        if (adap->nr == -1) /* -1 means dynamically assign bus id */
                return i2c_add_adapter(adap);

> Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
> ---
>  drivers/i2c/busses/i2c-omap.c |   19 +++++++++++++++----
>  1 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 5d19a49..9445d1f 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -1064,9 +1064,6 @@ omap_i2c_probe(struct platform_device *pdev)
>  		goto err_unuse_clocks;
>  	}
>  
> -	dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
> -		 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
> -

[    0.658843] omap_i2c i2c.15: bus -1 rev2.4.0 at 400 kHz
[    0.760192] omap_i2c i2c.16: bus -1 rev2.4.0 at 400 kHz
[    0.775817] omap_i2c i2c.17: bus -1 rev2.4.0 at 400 kHz
[    0.791442] omap_i2c i2c.18: bus -1 rev2.4.0 at 400 kHz

OK, it is true that the current log is not that nice with bus -1, but
maybe we should just remove that.

Or we can potentially retrieve the i2c adapter number assign later, and
delay the log.

>  	r = i2c_add_numbered_adapter(adap);
>  	if (r) {
>  		dev_err(dev->dev, "failure adding adapter\n");


Regards,
Benoit


>  	adap = &dev->adapter;
>  	i2c_set_adapdata(adap, dev);
>  	adap->owner = THIS_MODULE;
> @@ -1076,8 +1073,22 @@ omap_i2c_probe(struct platform_device *pdev)
>  	adap->dev.parent = &pdev->dev;
>  	adap->dev.of_node = pdev->dev.of_node;
>  
> +	if (adap->dev.of_node)
> +		adap->nr = of_alias_get_id(adap->dev.of_node, "i2c");
> +	else
> +		adap->nr = pdev->id;
> +
> +	if (adap->nr < 0) {
> +		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
> +				adap->nr);
> +		r = -ENODEV;
> +		goto err_free_irq;
> +	}
> +
> +	dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
> +		 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
> +
>  	/* i2c device drivers may be active on return from add_adapter() */
> -	adap->nr = pdev->id;
>  	r = i2c_add_numbered_adapter(adap);
>  	if (r) {
>  		dev_err(dev->dev, "failure adding adapter\n");
> 



From castet.matthieu at free.fr  Fri Aug 31 05:21:56 2012
From: castet.matthieu at free.fr (Matthieu CASTET)
Date: Fri, 31 Aug 2012 11:21:56 +0200
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
Message-ID: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>

Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
---
 drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/tty/hvc/hvc_dcc.c b/drivers/tty/hvc/hvc_dcc.c
index 44fbeba..489e9e5 100644
--- a/drivers/tty/hvc/hvc_dcc.c
+++ b/drivers/tty/hvc/hvc_dcc.c
@@ -26,6 +26,7 @@
 
 #include "hvc_console.h"
 
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
 /* DCC Status Bits */
 #define DCC_STATUS_RX		(1 << 30)
 #define DCC_STATUS_TX		(1 << 29)
@@ -58,6 +59,39 @@ static inline void __dcc_putchar(char c)
 		: "r" (c));
 	isb();
 }
+#else
+/* DCC Status Bits */
+#define DCC_STATUS_RX		(1 << 0)
+#define DCC_STATUS_TX		(1 << 1)
+
+/* primitive JTAG1 protocol utilities */
+static inline u32 __dcc_getstatus(void)
+{
+	u32 ret;
+
+	asm __volatile__ ("mrc p14, 0, %0, c0, c0	@ read comms ctrl reg"
+		: "=r" (ret));
+
+	return ret;
+}
+
+static inline char __dcc_getchar(void)
+{
+	char c;
+
+	asm __volatile__ ("mrc p14, 0, %0, c1, c0	@ read comms data reg"
+		: "=r" (c));
+
+	return c;
+}
+
+static inline void __dcc_putchar(unsigned char c)
+{
+	asm __volatile__ ("mcr p14, 0, %0, c1, c0	@ write a char"
+		: /* no output register */
+		: "r" (c));
+}
+#endif
 
 static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
 {
-- 
1.7.10.4



From ludovic.desroches at atmel.com  Fri Aug 31 05:21:16 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:21:16 +0200
Subject: [PATCH 0/8] i2c: at91: cleanup and dt support
Message-ID: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Hi,

This set of patches is based on Nikolaus at91_i2c driver.

Ludovic Desroches (8):
  i2c: at91: use managed resources
  i2c: at91: add warning about transmission issues for some devices
  i2c: at91: use an id table for SoC dependent parameters
  ARM: at91: do not configure at91sam9g10 twi pio as open-drain
  i2c: at91: add dt support to i2c-at91
  ARM: at91: add clocks for I2C DT entries
  ARM: dts: add twi nodes for atmel SOCs
  ARM: dts: add twi nodes for atmel boards

 .../devicetree/bindings/i2c/atmel-i2c.txt          |  30 +++
 arch/arm/boot/dts/at91sam9260.dtsi                 |  23 +--
 arch/arm/boot/dts/at91sam9263.dtsi                 |  23 +--
 arch/arm/boot/dts/at91sam9263ek.dts                |  20 +-
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   4 +
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi        |  28 +--
 arch/arm/boot/dts/at91sam9g25ek.dts                |  12 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |  33 ++--
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   8 +
 arch/arm/boot/dts/at91sam9n12.dtsi                 |  33 ++--
 arch/arm/boot/dts/at91sam9n12ek.dts                |   8 +
 arch/arm/boot/dts/at91sam9x5.dtsi                  |  69 +++----
 arch/arm/mach-at91/at91rm9200.c                    |   2 +-
 arch/arm/mach-at91/at91rm9200_devices.c            |  11 +-
 arch/arm/mach-at91/at91sam9260.c                   |   4 +-
 arch/arm/mach-at91/at91sam9260_devices.c           |   8 +-
 arch/arm/mach-at91/at91sam9261.c                   |   3 +-
 arch/arm/mach-at91/at91sam9261_devices.c           |  31 ++-
 arch/arm/mach-at91/at91sam9263.c                   |   3 +-
 arch/arm/mach-at91/at91sam9263_devices.c           |   2 +-
 arch/arm/mach-at91/at91sam9g45.c                   |   6 +-
 arch/arm/mach-at91/at91sam9g45_devices.c           |   4 +-
 arch/arm/mach-at91/at91sam9n12.c                   |   2 +
 arch/arm/mach-at91/at91sam9rl.c                    |   4 +-
 arch/arm/mach-at91/at91sam9rl_devices.c            |   2 +-
 arch/arm/mach-at91/at91sam9x5.c                    |   6 +-
 drivers/i2c/busses/Kconfig                         |   6 +
 drivers/i2c/busses/i2c-at91.c                      | 217 +++++++++++++--------
 28 files changed, 367 insertions(+), 235 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/i2c/atmel-i2c.txt

-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:21:17 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:21:17 +0200
Subject: [PATCH 1/8] i2c: at91: use managed resources
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346404884-18451-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Use managed resources to ease the cleanup.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/i2c/busses/i2c-at91.c | 85 +++++++++++++------------------------------
 1 file changed, 25 insertions(+), 60 deletions(-)

diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 2b8b2c2..08aaee7 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -326,61 +326,49 @@ static struct i2c_algorithm at91_twi_algorithm = {
 static int __devinit at91_twi_probe(struct platform_device *pdev)
 {
 	struct at91_twi_dev *dev;
-	struct resource *mem, *ioarea;
-	int irq, rc;
+	struct resource *mem;
+	int rc;
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+	init_completion(&dev->cmd_complete);
+	dev->dev = &pdev->dev;
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem)
 		return -ENODEV;
 
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
-	ioarea = request_mem_region(mem->start, resource_size(mem), pdev->name);
-	if (!ioarea)
+	dev->base = devm_request_and_ioremap(&pdev->dev, mem);
+	if (!dev->base)
 		return -EBUSY;
 
-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-	if (!dev) {
-		rc = -ENOMEM;
-		goto err_release_region;
+	dev->irq = platform_get_irq(pdev, 0);
+	if (dev->irq < 0)
+		return dev->irq;
+
+	rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
+			 dev_name(dev->dev), dev);
+	if (rc) {
+		dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
+		return rc;
 	}
 
 	if (pdev->id_entry)
 		dev->ip_id = pdev->id_entry->driver_data;
 
-	init_completion(&dev->cmd_complete);
-
-	dev->dev = &pdev->dev;
-	dev->irq = irq;
 	platform_set_drvdata(pdev, dev);
 
-	dev->clk = clk_get(dev->dev, NULL);
+	dev->clk = devm_clk_get(dev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
 		dev_err(dev->dev, "no clock defined\n");
-		rc = -ENODEV;
-		goto err_free_mem;
-	}
-	clk_prepare(dev->clk);
-	clk_enable(dev->clk);
-
-	dev->base = ioremap(mem->start, resource_size(mem));
-	if (!dev->base) {
-		rc = -EBUSY;
-		goto err_mem_ioremap;
+		return -ENODEV;
 	}
+	clk_prepare_enable(dev->clk);
 
 	at91_calc_twi_clock(dev, TWI_CLK_HZ);
 	at91_init_twi_bus(dev);
 
-	rc = request_irq(dev->irq, atmel_twi_interrupt, 0,
-			 dev_name(dev->dev), dev);
-	if (rc) {
-		dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
-		goto err_unuse_clocks;
-	}
-
 	snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
 	i2c_set_adapdata(&dev->adapter, dev);
 	dev->adapter.owner = THIS_MODULE;
@@ -394,44 +382,21 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 	if (rc) {
 		dev_err(dev->dev, "Adapter %s registration failed\n",
 			dev->adapter.name);
-		goto err_free_irq;
+		clk_disable_unprepare(dev->clk);
+		return rc;
 	}
 
 	dev_info(dev->dev, "AT91 i2c bus driver.\n");
 	return 0;
-
-err_free_irq:
-	free_irq(dev->irq, dev);
-err_unuse_clocks:
-	iounmap(dev->base);
-err_mem_ioremap:
-	clk_disable(dev->clk);
-	clk_unprepare(dev->clk);
-	clk_put(dev->clk);
-err_free_mem:
-	kfree(dev);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
-
-	return rc;
 }
 
 static int __devexit at91_twi_remove(struct platform_device *pdev)
 {
 	struct at91_twi_dev *dev = platform_get_drvdata(pdev);
-	struct resource *mem;
 	int rc;
 
 	rc = i2c_del_adapter(&dev->adapter);
-	clk_disable(dev->clk);
-	clk_unprepare(dev->clk);
-	clk_put(dev->clk);
-	free_irq(dev->irq, dev);
-	iounmap(dev->base);
-	kfree(dev);
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
+	clk_disable_unprepare(dev->clk);
 
 	return rc;
 }
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:21:18 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:21:18 +0200
Subject: [PATCH 2/8] i2c: at91: add warning about transmission issues for some
 devices
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346404884-18451-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Some devices don't have clock streching in transmission mode. It can
lead to premature stop sendings if the latency to write data in the
transmission register is too long. In this case, prefer the i2c-gpio
driver.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/i2c/busses/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index d9c4918..da77c37 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -300,6 +300,12 @@ config I2C_AT91
 	  to support combined I2C messages.  Use the i2c-gpio driver
 	  unless your system can cope with this limitation.
 
+	  Caution! at91rm9200, at91sam9261, at91sam9260, at91sam9263 devices
+	  don't have clock stretching in transmission mode. For that reason,
+	  you can encounter underrun issues causing premature stop sendings if
+	  the latency to fill the transmission register is too long. If you
+	  are facing this situation, use the i2c-gpio driver.
+
 config I2C_AU1550
 	tristate "Au1550/Au1200/Au1300 SMBus interface"
 	depends on MIPS_ALCHEMY
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:21:19 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:21:19 +0200
Subject: [PATCH 3/8] i2c: at91: use an id table for SoC dependent parameters
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346404884-18451-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Use the id_table to store configuration structures which are depending on
SoC.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91rm9200.c          |  2 +-
 arch/arm/mach-at91/at91rm9200_devices.c  | 11 +----
 arch/arm/mach-at91/at91sam9260.c         |  3 +-
 arch/arm/mach-at91/at91sam9260_devices.c |  8 ++-
 arch/arm/mach-at91/at91sam9261.c         |  3 +-
 arch/arm/mach-at91/at91sam9261_devices.c | 17 +++----
 arch/arm/mach-at91/at91sam9263.c         |  2 +-
 arch/arm/mach-at91/at91sam9263_devices.c |  2 +-
 arch/arm/mach-at91/at91sam9g45.c         |  4 +-
 arch/arm/mach-at91/at91sam9g45_devices.c |  4 +-
 arch/arm/mach-at91/at91sam9rl.c          |  4 +-
 arch/arm/mach-at91/at91sam9rl_devices.c  |  2 +-
 drivers/i2c/busses/i2c-at91.c            | 85 +++++++++++++++++++++++++-------
 13 files changed, 95 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index f2112f9..0bc91e5 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91rm9200_i2c", &twi_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 71e7387..cddfe02 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -494,18 +494,9 @@ static struct resource twi_resources[] = {
 	},
 };
 
-static const struct platform_device_id twi_ip_type = {
-	/*
-	 * driver_data is 1 for RM9200 compatible ip, see enum twi_ip_id in
-	 * drivers/i2c/busses/i2c-at91.c
-	 */
-	.driver_data	= 1,
-};
-
 static struct platform_device at91rm9200_twi_device = {
-	.name		= "at91_i2c",
+	.name		= "at91rm9200_i2c",
 	.id		= -1,
-	.id_entry	= &twi_ip_type,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
 };
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 57c79ee..5f86e71 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -211,7 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9260_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g20_i2c", &twi_clk),
 	/* more usart lookup table for DT entries */
 	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..ed02171 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -503,7 +503,6 @@ static struct resource twi_resources[] = {
 };
 
 static struct platform_device at91sam9260_twi_device = {
-	.name		= "at91_i2c",
 	.id		= -1,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
@@ -511,6 +510,13 @@ static struct platform_device at91sam9260_twi_device = {
 
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
+	/* IP version is not the same on 9260 and g20 */
+	if (cpu_is_at91sam9g20()) {
+		at91sam9260_twi_device.name = "at91sam9g20_i2c";
+	} else {
+		at91sam9260_twi_device.name = "at91sam9260_i2c";
+	}
+
 	/* pins used for TWI interface */
 	at91_set_A_periph(AT91_PIN_PA23, 0);		/* TWD */
 	at91_set_multi_drive(AT91_PIN_PA23, 1);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 71ca1e0..0ccf63c 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -178,7 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9261_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g10_i2c", &twi_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
 	CLKDEV_CON_ID("pioB", &pioB_clk),
 	CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index d830724..c94495d 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -316,24 +316,21 @@ static struct resource twi_resources[] = {
 	},
 };
 
-static const struct platform_device_id twi_ip_type = {
-	/*
-	 * driver_data is 2 for SAM9261 compatible ip, see enum twi_ip_id in
-	 * drivers/i2c/busses/i2c-at91.c
-	 */
-	.driver_data	= 2,
-};
-
 static struct platform_device at91sam9261_twi_device = {
-	.name		= "at91_i2c",
 	.id		= -1,
-	.id_entry	= &twi_ip_type,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
 };
 
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
+	/* IP version is not the same on 9261 and g10 */
+	if (cpu_is_at91sam9g10()) {
+		at91sam9261_twi_device.name = "at91sam9g10_i2c";
+	} else {
+		at91sam9261_twi_device.name = "at91sam9261_i2c";
+	}
+
 	/* pins used for TWI interface */
 	at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
 	at91_set_multi_drive(AT91_PIN_PA7, 1);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 2a08305..a4d760c 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -193,7 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9260_i2c", &twi_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..7cff86c 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -574,7 +574,7 @@ static struct resource twi_resources[] = {
 };
 
 static struct platform_device at91sam9263_twi_device = {
-	.name		= "at91_i2c",
+	.name		= "at91sam9260_i2c",
 	.id		= -1,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ddf3d37..15e62b9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -237,8 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.0", &twi0_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.1", &twi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g10_i2c.0", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g10_i2c.1", &twi1_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 	CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index f001305..a61c7ec 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -653,7 +653,7 @@ static struct resource twi0_resources[] = {
 };
 
 static struct platform_device at91sam9g45_twi0_device = {
-	.name		= "at91_i2c",
+	.name		= "at91sam9g10_i2c",
 	.id		= 0,
 	.resource	= twi0_resources,
 	.num_resources	= ARRAY_SIZE(twi0_resources),
@@ -673,7 +673,7 @@ static struct resource twi1_resources[] = {
 };
 
 static struct platform_device at91sam9g45_twi1_device = {
-	.name		= "at91_i2c",
+	.name		= "at91sam9g10_i2c",
 	.id		= 1,
 	.resource	= twi1_resources,
 	.num_resources	= ARRAY_SIZE(twi1_resources),
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index bf79c1f..d708dfa 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -186,8 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.0", &twi0_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.1", &twi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g20_i2c.0", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "at91sam9g20_i2c.1", &twi1_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
 	CLKDEV_CON_ID("pioB", &pioB_clk),
 	CLKDEV_CON_ID("pioC", &pioC_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..2df7411 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -346,7 +346,7 @@ static struct resource twi_resources[] = {
 };
 
 static struct platform_device at91sam9rl_twi_device = {
-	.name		= "at91_i2c",
+	.name		= "at91sam9g20_i2c",
 	.id		= -1,
 	.resource	= twi_resources,
 	.num_resources	= ARRAY_SIZE(twi_resources),
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 08aaee7..bcf9a5c 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -61,10 +61,10 @@
 #define	AT91_TWI_RHR		0x0030	/* Receive Holding Register */
 #define	AT91_TWI_THR		0x0034	/* Transmit Holding Register */
 
-enum twi_ip_id {
-	DEFAULT		= 0, /* default ip, no known limitations */
-	RM9200		= 1,
-	SAM9261		= 2,
+struct at91_twi_pdata {
+	unsigned	clk_max_div;
+	unsigned	clk_offset;
+	bool		has_unre_flag;
 };
 
 struct at91_twi_dev {
@@ -78,8 +78,8 @@ struct at91_twi_dev {
 	int			irq;
 	unsigned		transfer_status;
 	struct i2c_adapter	adapter;
-	enum twi_ip_id		ip_id;
 	unsigned		twi_cwgr_reg;
+	struct at91_twi_pdata	*pdata;
 };
 
 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
@@ -114,16 +114,9 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
 static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 {
 	int ckdiv, cdiv, div;
-	int offset = 4;
-	int max_ckdiv = 7;
-
-	if (dev->ip_id == RM9200) {
-		offset = 3;
-		max_ckdiv = 5;
-	} else if (dev->ip_id == SAM9261) {
-		offset = 4;
-		max_ckdiv = 5;
-	}
+	struct at91_twi_pdata *pdata = dev->pdata;
+	int offset = pdata->clk_offset;
+	int max_ckdiv = pdata->clk_max_div;
 
 	div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
 				       2 * twi_clk) - offset);
@@ -209,6 +202,7 @@ static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
 {
 	int ret;
+	bool has_unre_flag = dev->pdata->has_unre_flag;
 
 	dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
 		(dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
@@ -250,7 +244,7 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
 		dev_err(dev->dev, "overrun while reading\n");
 		return -EIO;
 	}
-	if (dev->transfer_status & AT91_TWI_UNRE && dev->ip_id == RM9200) {
+	if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
 		dev_err(dev->dev, "underrun while writing\n");
 		return -EIO;
 	}
@@ -323,6 +317,57 @@ static struct i2c_algorithm at91_twi_algorithm = {
 	.functionality	= at91_twi_func,
 };
 
+static struct at91_twi_pdata at91rm9200_config = {
+	.clk_max_div = 5,
+	.clk_offset = 3,
+	.has_unre_flag = true,
+};
+
+static struct at91_twi_pdata at91sam9261_config = {
+	.clk_max_div = 5,
+	.clk_offset = 4,
+	.has_unre_flag = false,
+};
+
+static struct at91_twi_pdata at91sam9260_config = {
+	.clk_max_div = 7,
+	.clk_offset = 4,
+	.has_unre_flag = false,
+};
+
+static struct at91_twi_pdata at91sam9g20_config = {
+	.clk_max_div = 7,
+	.clk_offset = 4,
+	.has_unre_flag = false,
+};
+
+static struct at91_twi_pdata at91sam9g10_config = {
+	.clk_max_div = 7,
+	.clk_offset = 4,
+	.has_unre_flag = false,
+};
+
+static const struct platform_device_id at91_twi_devtypes[] = {
+	{
+		.name = "at91rm9200_i2c",
+		.driver_data = (unsigned long) &at91rm9200_config,
+	}, {
+		.name = "at91sam9261_i2c",
+		.driver_data = (unsigned long) &at91sam9261_config,
+	}, {
+		.name = "at91sam9260_i2c",
+		.driver_data = (unsigned long) &at91sam9260_config,
+	}, {
+		.name = "at91sam9g20_i2c",
+		.driver_data = (unsigned long) &at91sam9g20_config,
+	}, {
+		.name = "at91sam9g10_i2c",
+		.driver_data = (unsigned long) &at91sam9g10_config,
+	}, {
+		/* sentinel */
+	}
+};
+
 static int __devinit at91_twi_probe(struct platform_device *pdev)
 {
 	struct at91_twi_dev *dev;
@@ -339,6 +384,10 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 	if (!mem)
 		return -ENODEV;
 
+	dev->pdata = at91_twi_get_driver_data(pdev);
+	if (!dev->pdata)
+		return -ENODEV;
+
 	dev->base = devm_request_and_ioremap(&pdev->dev, mem);
 	if (!dev->base)
 		return -EBUSY;
@@ -354,9 +403,6 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 		return rc;
 	}
 
-	if (pdev->id_entry)
-		dev->ip_id = pdev->id_entry->driver_data;
-
 	platform_set_drvdata(pdev, dev);
 
 	dev->clk = devm_clk_get(dev->dev, NULL);
@@ -432,6 +478,7 @@ static const struct dev_pm_ops at91_twi_pm = {
 static struct platform_driver at91_twi_driver = {
 	.probe		= at91_twi_probe,
 	.remove		= __devexit_p(at91_twi_remove),
+	.id_table	= at91_twi_devtypes,
 	.driver		= {
 		.name	= "at91_i2c",
 		.owner	= THIS_MODULE,
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:21:20 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:21:20 +0200
Subject: [PATCH 4/8] ARM: at91: do not configure at91sam9g10 twi pio as
 open-drain
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346404884-18451-5-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

As indicated in the datasheet, TWD and TWCK must not be programmed as
open-drain.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9261_devices.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index c94495d..405f603 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -324,20 +324,22 @@ static struct platform_device at91sam9261_twi_device = {
 
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
-	/* IP version is not the same on 9261 and g10 */
+	/*
+	 * IP version is not the same on 9261 and g10 and only 9261 one
+	 * requires to configure PIO as open-drain.
+	 */
 	if (cpu_is_at91sam9g10()) {
 		at91sam9261_twi_device.name = "at91sam9g10_i2c";
+		at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
+		at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
 	} else {
 		at91sam9261_twi_device.name = "at91sam9261_i2c";
+		at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
+		at91_set_multi_drive(AT91_PIN_PA7, 1);
+		at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
+		at91_set_multi_drive(AT91_PIN_PA8, 1);
 	}
 
-	/* pins used for TWI interface */
-	at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
-	at91_set_multi_drive(AT91_PIN_PA7, 1);
-
-	at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
-	at91_set_multi_drive(AT91_PIN_PA8, 1);
-
 	i2c_register_board_info(0, devices, nr_devices);
 	platform_device_register(&at91sam9261_twi_device);
 }
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:23:30 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:23:30 +0200
Subject: [PATCH 4/8] ARM: at91: do not configure at91sam9g10 twi pio as
 open-drain
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346405010-18499-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

As indicated in the datasheet, TWD and TWCK must not be programmed as
open-drain.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9261_devices.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index c94495d..405f603 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -324,20 +324,22 @@ static struct platform_device at91sam9261_twi_device = {
 
 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
 {
-	/* IP version is not the same on 9261 and g10 */
+	/*
+	 * IP version is not the same on 9261 and g10 and only 9261 one
+	 * requires to configure PIO as open-drain.
+	 */
 	if (cpu_is_at91sam9g10()) {
 		at91sam9261_twi_device.name = "at91sam9g10_i2c";
+		at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
+		at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
 	} else {
 		at91sam9261_twi_device.name = "at91sam9261_i2c";
+		at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
+		at91_set_multi_drive(AT91_PIN_PA7, 1);
+		at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
+		at91_set_multi_drive(AT91_PIN_PA8, 1);
 	}
 
-	/* pins used for TWI interface */
-	at91_set_A_periph(AT91_PIN_PA7, 0);		/* TWD */
-	at91_set_multi_drive(AT91_PIN_PA7, 1);
-
-	at91_set_A_periph(AT91_PIN_PA8, 0);		/* TWCK */
-	at91_set_multi_drive(AT91_PIN_PA8, 1);
-
 	i2c_register_board_info(0, devices, nr_devices);
 	platform_device_register(&at91sam9261_twi_device);
 }
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:23:49 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:23:49 +0200
Subject: [PATCH 5/8] i2c: at91: add dt support to i2c-at91
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346405029-18539-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 .../devicetree/bindings/i2c/atmel-i2c.txt          | 30 +++++++++++++
 drivers/i2c/busses/i2c-at91.c                      | 49 ++++++++++++++++++++++
 2 files changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/atmel-i2c.txt

diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
new file mode 100644
index 0000000..b689a0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
@@ -0,0 +1,30 @@
+I2C for Atmel platforms
+
+Required properties :
+- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
+     "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c"
+     or "atmel,at91sam9x5-i2c"
+- reg: physical base address of the controller and length of memory mapped
+     region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- Child nodes conforming to i2c bus binding
+
+Examples :
+
+i2c0: i2c at fff84000 {
+	compatible = "atmel,at91sam9g20-i2c";
+	reg = <0xfff84000 0x100>;
+	interrupts = <12 4 6>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	24c512 at 50 {
+		compatible = "24c512";
+		reg = <0x50>;
+		pagesize = <128>;
+	}
+}
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index bcf9a5c..7a80982 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -24,6 +24,9 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_i2c.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -347,6 +350,12 @@ static struct at91_twi_pdata at91sam9g10_config = {
 	.has_unre_flag = false,
 };
 
+static struct at91_twi_pdata at91sam9x5_config = {
+	.clk_max_div = 7,
+	.clk_offset = 4,
+	.has_unre_flag = false,
+};
+
 static const struct platform_device_id at91_twi_devtypes[] = {
 	{
 		.name = "at91rm9200_i2c",
@@ -368,6 +377,42 @@ static const struct platform_device_id at91_twi_devtypes[] = {
 	}
 };
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_twi_dt_ids[] = {
+	{
+		.compatible = "atmel,at91sam9260-i2c",
+		.data = &at91sam9260_config,
+	} , {
+		.compatible = "atmel,at91sam9g20-i2c",
+		.data = &at91sam9g20_config,
+	} , {
+		.compatible = "atmel,at91sam9g10-i2c",
+		.data = &at91sam9g10_config,
+	}, {
+		.compatible = "atmel,at91sam9x5-i2c",
+		.data = &at91sam9x5_config,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
+#else
+#define atmel_twi_dt_ids NULL
+#endif
+
+static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
+					struct platform_device *pdev)
+{
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
+		if (!match)
+			return NULL;
+		return match->data;
+	}
+	return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
+}
+
 static int __devinit at91_twi_probe(struct platform_device *pdev)
 {
 	struct at91_twi_dev *dev;
@@ -423,6 +468,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 	dev->adapter.dev.parent = dev->dev;
 	dev->adapter.nr = pdev->id;
 	dev->adapter.timeout = AT91_I2C_TIMEOUT;
+	dev->adapter.dev.of_node = pdev->dev.of_node;
 
 	rc = i2c_add_numbered_adapter(&dev->adapter);
 	if (rc) {
@@ -432,6 +478,8 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
 		return rc;
 	}
 
+	of_i2c_register_devices(&dev->adapter);
+
 	dev_info(dev->dev, "AT91 i2c bus driver.\n");
 	return 0;
 }
@@ -482,6 +530,7 @@ static struct platform_driver at91_twi_driver = {
 	.driver		= {
 		.name	= "at91_i2c",
 		.owner	= THIS_MODULE,
+		.of_match_table = atmel_twi_dt_ids,
 		.pm	= at91_twi_pm_ops,
 	},
 };
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:24:18 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:24:18 +0200
Subject: [PATCH 6/8] ARM: at91: add clocks for I2C DT entries
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346405058-18580-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9260.c | 1 +
 arch/arm/mach-at91/at91sam9263.c | 1 +
 arch/arm/mach-at91/at91sam9g45.c | 2 ++
 arch/arm/mach-at91/at91sam9n12.c | 2 ++
 arch/arm/mach-at91/at91sam9x5.c  | 6 +++---
 5 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5f86e71..43f529a 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -221,6 +221,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 	CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 	CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 	/* more tc lookup table for DT entries */
 	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index a4d760c..514757e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -211,6 +211,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
 	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 15e62b9..9f3beba 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -256,6 +256,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..732d3d3 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 4bad4a2..e503538 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,9 +231,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.0", &twi0_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.1", &twi1_clk),
-	CLKDEV_CON_DEV_ID(NULL, "at91_i2c.2", &twi2_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:24:37 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:24:37 +0200
Subject: [PATCH 7/8] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346405077-18620-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Add twi nodes for atmel SOCs and remove i2c-gpio ones.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9260.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9263.dtsi | 23 ++++++-------
 arch/arm/boot/dts/at91sam9g20.dtsi |  4 +++
 arch/arm/boot/dts/at91sam9g45.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9n12.dtsi | 33 +++++++++++-------
 arch/arm/boot/dts/at91sam9x5.dtsi  | 69 +++++++++++++++++---------------------
 6 files changed, 94 insertions(+), 91 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 66389c1..8128963 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -28,6 +28,7 @@
 		gpio2 = &pioC;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -199,6 +200,15 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fffac000 {
+				compatible = "atmel,at91sam9260-i2c";
+				reg = <0xfffac000 0x100>;
+				interrupts = <11 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
@@ -258,17 +268,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 23 0 /* sda */
-			 &pioA 24 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index b460d6c..34dd4f5 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -24,6 +24,7 @@
 		gpio3 = &pioD;
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
+		i2c0 = &i2c0;
 	};
 	cpus {
 		cpu at 0 {
@@ -180,6 +181,15 @@
 				interrupts = <24 4 2>;
 				status = "disabled";
 			};
+
+			i2c0: i2c at fff88000 {
+				compatible = "atmel,at91sam9263-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -205,17 +215,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 2a1d1ca..75ce6e7 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -18,6 +18,10 @@
 
 	ahb {
 		apb {
+			i2c0: i2c at fffac000 {
+				compatible = "atmel,at91sam9g20-i2c";
+			};
+
 			adc0: adc at fffe0000 {
 				atmel,adc-startup-time = <40>;
 			};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bafa880..e06cb8a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -29,6 +29,8 @@
 		gpio4 = &pioE;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -201,6 +203,24 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at fff84000 {
+				compatible = "atmel,at91sam9g10-i2c";
+				reg = <0xfff84000 0x100>;
+				interrupts = <12 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at fff88000 {
+				compatible = "atmel,at91sam9g10-i2c";
+				reg = <0xfff88000 0x100>;
+				interrupts = <13 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at fffb0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffb0000 0x100>;
@@ -269,17 +289,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 20 0 /* sda */
-			 &pioA 21 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bfac0df..0c05bb9 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -26,6 +26,8 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 	};
 	cpus {
 		cpu at 0 {
@@ -178,6 +180,24 @@
 				atmel,use-dma-tx;
 				status = "disabled";
 			};
+
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9x5-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9x5-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -205,17 +225,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 4a18c39..907b89e 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -27,6 +27,9 @@
 		gpio3 = &pioD;
 		tcb0 = &tcb0;
 		tcb1 = &tcb1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
 	};
 	cpus {
 		cpu at 0 {
@@ -192,6 +195,33 @@
 				status = "disabled";
 			};
 
+			i2c0: i2c at f8010000 {
+				compatible = "atmel,at91sam9x5-i2c";
+				reg = <0xf8010000 0x100>;
+				interrupts = <9 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at f8014000 {
+				compatible = "atmel,at91sam9x5-i2c";
+				reg = <0xf8014000 0x100>;
+				interrupts = <10 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at f8018000 {
+				compatible = "atmel,at91sam9x5-i2c";
+				reg = <0xf8018000 0x100>;
+				interrupts = <11 4 6>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			adc0: adc at f804c000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xf804c000 0x100>;
@@ -260,43 +290,4 @@
 			status = "disabled";
 		};
 	};
-
-	i2c at 0 {
-		compatible = "i2c-gpio";
-		gpios = <&pioA 30 0 /* sda */
-			 &pioA 31 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 1 {
-		compatible = "i2c-gpio";
-		gpios = <&pioC 0 0 /* sda */
-			 &pioC 1 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c at 2 {
-		compatible = "i2c-gpio";
-		gpios = <&pioB 4 0 /* sda */
-			 &pioB 5 0 /* scl */
-			>;
-		i2c-gpio,sda-open-drain;
-		i2c-gpio,scl-open-drain;
-		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
 };
-- 
1.7.11.3



From ludovic.desroches at atmel.com  Fri Aug 31 05:24:56 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Fri, 31 Aug 2012 11:24:56 +0200
Subject: [PATCH 8/8] ARM: dts: add twi nodes for atmel boards
In-Reply-To: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1346405096-18660-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Use the atmel twi instead of gpio for i2c stuff.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9263ek.dts         | 20 ++++++++++----------
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 28 ++++++++++++++--------------
 arch/arm/boot/dts/at91sam9g25ek.dts         | 12 ++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |  8 ++++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |  8 ++++++++
 5 files changed, 52 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index f86ac4b..772ab75 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -50,6 +50,16 @@
 				atmel,vbus-gpio = <&pioA 25 0>;
 				status = "okay";
 			};
+
+			i2c0: i2c at fff88000 {
+				status = "okay";
+
+				24c512 at 50 {
+					compatible = "24c512";
+					reg = <0x50>;
+					pagesize = <128>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -143,14 +153,4 @@
 			gpio-key,wakeup;
 		};
 	};
-
-	i2c at 0 {
-		status = "okay";
-
-		24c512 at 50 {
-			compatible = "24c512";
-			reg = <0x50>;
-			pagesize = <128>;
-		};
-	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index b06c0db..712106b 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -51,6 +51,20 @@
 				atmel,vbus-gpio = <&pioC 5 0>;
 				status = "okay";
 			};
+
+			i2c0: i2c at fffac000 {
+				status = "okay";
+
+				24c512 at 50 {
+					compatible = "24c512";
+					reg = <0x50>;
+				};
+
+				wm8731 at 1b {
+					compatible = "wm8731";
+					reg = <0x1b>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
@@ -106,20 +120,6 @@
 		};
 	};
 
-	i2c at 0 {
-		status = "okay";
-
-		24c512 at 50 {
-			compatible = "24c512";
-			reg = <0x50>;
-		};
-
-		wm8731 at 1b {
-			compatible = "wm8731";
-			reg = <0x1b>;
-		};
-	};
-
 	gpio_keys {
 		compatible = "gpio-keys";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7829a4d..3b0adbc 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,18 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			i2c0: i2c at f8010000 {
+				status = "okay";
+			};
+
+			i2c1: i2c at f8014000 {
+				status = "okay";
+			};
+
+			i2c2: i2c at f8018000 {
+				status = "okay";
+			};
 		};
 
 		usb0: ohci at 00600000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a3633bd..15e1dd4 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -46,6 +46,14 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			i2c0: i2c at fff84000 {
+				status = "okay";
+			};
+
+			i2c1: i2c at fff88000 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index f4e43e3..912b2c2 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -37,6 +37,14 @@
 			dbgu: serial at fffff200 {
 				status = "okay";
 			};
+
+			i2c0: i2c at f8010000 {
+				status = "okay";
+			};
+
+			i2c1: i2c at f8014000 {
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.11.3



From p.zabel at pengutronix.de  Fri Aug 31 05:26:55 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:26:55 +0200
Subject: [PATCH v2 0/9] Add device tree support for on-chip SRAM 
Message-ID: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>

These patches add support to configure on-chip SRAM via device-tree
node and to obtain the resulting genalloc pool from a phandle pointing
at the node.
This allows drivers to allocate SRAM with the genalloc API without
hard-coding the genalloc pool address.

The on-chip SRAM on i.MX53 and i.MX6q is registered via device tree and
changed to use the simple generic SRAM driver:

		ocram: ocram at 00900000 {
			compatible = "fsl,imx-ocram", "sram";
			reg = <0x00900000 0x3f000>;
 		};

A driver that needs to allocate SRAM buffers, like the video processing
unit on i.MX53, can retrieve the genalloc pool from a phandle in the
device tree using of_get_named_gen_pool(node, "iram", 0) from patch 5:

		vpu at 63ff4000 {
			/* ... */
			iram = <&ocram>;
 		};

Changes since v1:
 - Added a generic SRAM driver in drivers/misc that does nothing but
   request/ioremap its given memory region and serve it via the genalloc
   API.
 - Renamed the i.MX device tree nodes from "iram" to "ocram".

regards
Philipp

---
 arch/arm/boot/dts/imx53.dtsi          |    5 ++
 arch/arm/boot/dts/imx6q.dtsi          |    5 ++
 arch/arm/plat-mxc/Kconfig             |    4 --
 arch/arm/plat-mxc/Makefile            |    1 -
 arch/arm/plat-mxc/include/mach/iram.h |   41 -------------
 arch/arm/plat-mxc/iram_alloc.c        |   73 -----------------------
 drivers/misc/Kconfig                  |    8 +++
 drivers/misc/Makefile                 |    1 +
 drivers/misc/sram.c                   |  105 +++++++++++++++++++++++++++++++++
 include/linux/genalloc.h              |   14 +++++
 lib/genalloc.c                        |   77 ++++++++++++++++++++++++
 11 files changed, 215 insertions(+), 119 deletions(-)



From p.zabel at pengutronix.de  Fri Aug 31 05:26:58 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:26:58 +0200
Subject: [PATCH v2 3/9] ARM i.MX6: Add OCRAM to device tree
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-4-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
Changes since v1:
 - Renamed "iram" to "ocram" as it appears in the processor
   reference manuals.
---
 arch/arm/boot/dts/imx6q.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..9cb0b50 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -111,6 +111,11 @@
 		       status = "disabled";
 		};
 
+		ocram at 00900000 {
+			compatible = "fsl,imx-ocram";
+			reg = <0x00900000 0x3f000>;
+		};
+
 		timer at 00a00600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x00a00600 0x20>;
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:26:57 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:26:57 +0200
Subject: [PATCH v2 2/9] ARM i.MX53: Add OCRAM to device tree
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-3-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 - Renamed "iram" to "ocram" as it appears in the processor
   reference manuals.
---
 arch/arm/boot/dts/imx53.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165..5da342a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -337,5 +337,10 @@
 				status = "disabled";
 			};
 		};
+
+		ocram at f8000000 {
+			compatible = "fsl,imx-ocram";
+			reg = <0xf8000000 0x20000>;
+		};
 	};
 };
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:27:00 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:27:00 +0200
Subject: [PATCH v2 5/9] genalloc: add a global pool list,
 allow to find pools by phys address
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-6-git-send-email-p.zabel@pengutronix.de>

This patch keeps all created pools in a global list and adds two
functions that allow to retrieve the gen_pool pointer from a known
physical address and from a device tree node.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 include/linux/genalloc.h |   14 +++++++++
 lib/genalloc.c           |   77 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+)

diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h
index 5e98eeb..46ff435 100644
--- a/include/linux/genalloc.h
+++ b/include/linux/genalloc.h
@@ -33,6 +33,7 @@
  *  General purpose special memory pool descriptor.
  */
 struct gen_pool {
+	struct list_head next_pool;	/* pool in global list */
 	spinlock_t lock;
 	struct list_head chunks;	/* list of chunks in this pool */
 	int min_alloc_order;		/* minimum allocation order */
@@ -78,4 +79,17 @@ extern void gen_pool_for_each_chunk(struct gen_pool *,
 	void (*)(struct gen_pool *, struct gen_pool_chunk *, void *), void *);
 extern size_t gen_pool_avail(struct gen_pool *);
 extern size_t gen_pool_size(struct gen_pool *);
+extern struct gen_pool *gen_pool_find_by_phys(phys_addr_t phys);
+
+#ifdef CONFIG_OF
+struct device_node;
+extern struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index);
+#else
+inline struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index)
+{
+	return NULL;
+}
+#endif
 #endif /* __GENALLOC_H__ */
diff --git a/lib/genalloc.c b/lib/genalloc.c
index 6bc04aa..df2d8f9 100644
--- a/lib/genalloc.c
+++ b/lib/genalloc.c
@@ -34,6 +34,11 @@
 #include <linux/rculist.h>
 #include <linux/interrupt.h>
 #include <linux/genalloc.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+
+static LIST_HEAD(pools);
+static DEFINE_SPINLOCK(list_lock);
 
 static int set_bits_ll(unsigned long *addr, unsigned long mask_to_set)
 {
@@ -152,6 +157,9 @@ struct gen_pool *gen_pool_create(int min_alloc_order, int nid)
 		spin_lock_init(&pool->lock);
 		INIT_LIST_HEAD(&pool->chunks);
 		pool->min_alloc_order = min_alloc_order;
+		spin_lock(&list_lock);
+		list_add_rcu(&pool->next_pool, &pools);
+		spin_unlock(&list_lock);
 	}
 	return pool;
 }
@@ -234,6 +242,9 @@ void gen_pool_destroy(struct gen_pool *pool)
 	int order = pool->min_alloc_order;
 	int bit, end_bit;
 
+	spin_lock(&list_lock);
+	list_del_rcu(&pool->next_pool);
+	spin_unlock(&list_lock);
 	list_for_each_safe(_chunk, _next_chunk, &pool->chunks) {
 		chunk = list_entry(_chunk, struct gen_pool_chunk, next_chunk);
 		list_del(&chunk->next_chunk);
@@ -400,3 +411,69 @@ size_t gen_pool_size(struct gen_pool *pool)
 	return size;
 }
 EXPORT_SYMBOL_GPL(gen_pool_size);
+
+/**
+ * gen_pool_find_by_phys - find a pool by physical start address
+ * @phys: physical address as added with gen_pool_add_virt
+ *
+ * Returns the pool that contains the chunk starting at phys,
+ * or NULL if not found.
+ */
+struct gen_pool *gen_pool_find_by_phys(phys_addr_t phys)
+{
+	struct gen_pool *pool, *found = NULL;
+	struct gen_pool_chunk *chunk;
+
+	rcu_read_lock();
+	list_for_each_entry_rcu(pool, &pools, next_pool) {
+		list_for_each_entry_rcu(chunk, &pool->chunks, next_chunk) {
+			if (phys == chunk->phys_addr) {
+				found = pool;
+				break;
+			}
+		}
+	}
+	rcu_read_unlock();
+
+	return found;
+}
+EXPORT_SYMBOL_GPL(gen_pool_find_by_phys);
+
+#ifdef CONFIG_OF
+/**
+ * of_get_named_gen_pool - find a pool by the physical address in
+ * @np: device node
+ *
+ * Returns the pool that contains the chunk starting at the physical
+ * address of the np device node, or NULL if not found.
+ */
+struct gen_pool *of_get_named_gen_pool(struct device_node *np,
+	const char *propname, int index)
+{
+	struct property *prop;
+	const __be32 *list;
+	int size;
+	phandle phandle;
+	struct device_node *np_pool;
+	const u32 *reg;
+	u64 addr;
+
+	prop = of_find_property(np, propname, &size);
+	if (!prop)
+		return NULL;
+	list = prop->value;
+	size /= sizeof(*list);
+	phandle = be32_to_cpup(list);
+	np_pool = of_find_node_by_phandle(phandle);
+	if (!np_pool)
+		return NULL;
+	reg = of_get_property(np_pool, "reg", NULL);
+	if (!reg)
+		return NULL;
+	addr = of_translate_address(np_pool, reg);
+	if (addr == OF_BAD_ADDR)
+		return NULL;
+	return gen_pool_find_by_phys((phys_addr_t) addr);
+}
+EXPORT_SYMBOL_GPL(of_get_named_gen_pool);
+#endif /* CONFIG_OF */
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:27:03 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:27:03 +0200
Subject: [PATCH v2 8/9] ARM: i.MX6: use generic on-chip SRAM allocator driver
 for OCRAM
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-9-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/boot/dts/imx6q.dtsi |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 9cb0b50..1e463c4 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -111,8 +111,8 @@
 		       status = "disabled";
 		};
 
-		ocram at 00900000 {
-			compatible = "fsl,imx-ocram";
+		ocram: ocram at 00900000 {
+			compatible = "fsl,imx-ocram", "sram";
 			reg = <0x00900000 0x3f000>;
 		};
 
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:27:01 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:27:01 +0200
Subject: [PATCH v2 6/9] misc: Generic on-chip SRAM allocation driver
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-7-git-send-email-p.zabel@pengutronix.de>

This driver requests and remaps a memory region as configured in the
device tree. It serves memory from this region via the genalloc API.

Other drivers can retrieve the genalloc pool from a phandle pointing
to this drivers' device node in the device tree.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 drivers/misc/Kconfig  |    8 ++++
 drivers/misc/Makefile |    1 +
 drivers/misc/sram.c   |  105 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 114 insertions(+)
 create mode 100644 drivers/misc/sram.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 98a442d..8a55284 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -509,6 +509,14 @@ config USB_SWITCH_FSA9480
 	  stereo and mono audio, video, microphone and UART data to use
 	  a common connector port.
 
+config SRAM
+	bool "Generic on-chip SRAM driver\n"
+	select GENERIC_ALLOCATOR
+	help
+	  This driver allows to declare a memory region to be managed
+	  by the genalloc API. It is supposed to be used for small
+	  on-chip SRAM areas found on many ARM SoCs.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b88df7a..ccc759a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -50,3 +50,4 @@ obj-y				+= carma/
 obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
 obj-$(CONFIG_ALTERA_STAPL)	+=altera-stapl/
 obj-$(CONFIG_INTEL_MEI)		+= mei/
+obj-$(CONFIG_SRAM)		+= sram.o
diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c
new file mode 100644
index 0000000..c5cf67e
--- /dev/null
+++ b/drivers/misc/sram.c
@@ -0,0 +1,105 @@
+/*
+ * Generic on-chip SRAM allocation driver
+ *
+ * Copyright (C) 2012 Philipp Zabel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/genalloc.h>
+
+struct sram_dev {
+	struct gen_pool *pool;
+};
+
+static int __devinit sram_probe(struct platform_device *pdev)
+{
+	void __iomem *virt_base;
+	struct sram_dev *sram;
+	struct resource *res;
+	unsigned long size;
+	int ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -EINVAL;
+
+	size = resource_size(res);
+
+	virt_base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!virt_base)
+		return -ENOMEM;
+
+	sram = devm_kzalloc(&pdev->dev, sizeof(*sram), GFP_KERNEL);
+	if (!sram)
+		return -ENOMEM;
+
+	sram->pool = gen_pool_create(PAGE_SHIFT, -1);
+	if (!sram->pool)
+		return -ENOMEM;
+
+	ret = gen_pool_add_virt(sram->pool, (unsigned long)virt_base,
+				res->start, size, -1);
+	if (ret < 0) {
+		gen_pool_destroy(sram->pool);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, sram);
+
+	dev_dbg(&pdev->dev, "SRAM pool: %ld KiB @ 0x%p\n", size / 1024, virt_base);
+
+	return 0;
+}
+
+static int __devexit sram_remove(struct platform_device *pdev)
+{
+	struct sram_dev *sram = platform_get_drvdata(pdev);
+
+	if (gen_pool_avail(sram->pool) < gen_pool_size(sram->pool))
+		dev_dbg(&pdev->dev, "removed while SRAM allocated\n");
+
+	gen_pool_destroy(sram->pool);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static struct of_device_id sram_dt_ids[] = {
+	{ .compatible = "sram" },
+	{ /* sentinel */ }
+};
+#endif
+
+static struct platform_driver sram_driver = {
+	.driver = {
+		.name = "sram",
+		.of_match_table = of_match_ptr(sram_dt_ids),
+	},
+	.probe = sram_probe,
+	.remove = __devexit_p(sram_remove),
+};
+
+module_platform_driver(sram_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Philipp Zabel, Pengutronix");
+MODULE_DESCRIPTION("Generic SRAM allocator driver");
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:27:02 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:27:02 +0200
Subject: [PATCH v2 7/9] ARM: i.MX53: use generic on-chip SRAM allocator driver
 for OCRAM
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-8-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/boot/dts/imx53.dtsi |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 5da342a..2767a92 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -338,8 +338,8 @@
 			};
 		};
 
-		ocram at f8000000 {
-			compatible = "fsl,imx-ocram";
+		ocram: ocram at f8000000 {
+			compatible = "fsl,imx-ocram", "sram";
 			reg = <0xf8000000 0x20000>;
 		};
 	};
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:26:59 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:26:59 +0200
Subject: [PATCH v2 4/9] iram_alloc: store the virt and phys mem address in
 gen_pool chunks
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-5-git-send-email-p.zabel@pengutronix.de>

This improves the symmetry of iram_alloc and iram_free in that
iram_free has to be called with the virtual address now.
Also, gen_pool_virt_to_phys is now functional.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/iram_alloc.c |   39 ++++++++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
index 673deb4..343e96d 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -26,25 +26,22 @@
 #include <linux/platform_device.h>
 #include <mach/iram.h>
 
-static unsigned long iram_phys_base;
-static void __iomem *iram_virt_base;
 static struct gen_pool *iram_pool;
 
-static inline void __iomem *iram_phys_to_virt(unsigned long p)
-{
-	return iram_virt_base + (p - iram_phys_base);
-}
-
 void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
 {
+	unsigned long virt;
+
 	if (!iram_pool)
 		return NULL;
 
-	*dma_addr = gen_pool_alloc(iram_pool, size);
+	virt = gen_pool_alloc(iram_pool, size);
 	pr_debug("iram alloc - %dB at 0x%lX\n", size, *dma_addr);
-	if (!*dma_addr)
+	if (!virt)
 		return NULL;
-	return iram_phys_to_virt(*dma_addr);
+
+	*dma_addr = gen_pool_virt_to_phys(iram_pool, virt);
+	return (void __iomem *)virt;
 }
 EXPORT_SYMBOL(iram_alloc);
 
@@ -59,29 +56,37 @@ EXPORT_SYMBOL(iram_free);
 
 static int __devinit iram_probe(struct platform_device *pdev)
 {
+	void __iomem *virt_base;
 	struct resource *res;
 	unsigned long size;
+	int ret;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
 		return -EINVAL;
 
-	if (iram_phys_base)
+	if (iram_pool)
 		return -EBUSY;
 
-	iram_phys_base = res->start;
 	size = resource_size(res);
 
+	virt_base = devm_ioremap(&pdev->dev, res->start, size);
+	if (!virt_base)
+		return -ENOMEM;
+
 	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
 	if (!iram_pool)
 		return -ENOMEM;
 
-	gen_pool_add(iram_pool, res->start, size, -1);
-	iram_virt_base = ioremap(iram_phys_base, size);
-	if (!iram_virt_base)
-		return -EIO;
+	ret = gen_pool_add_virt(iram_pool, (unsigned long)virt_base,
+				res->start, size, -1);
+	if (ret < 0) {
+		gen_pool_destroy(iram_pool);
+		iram_pool = NULL;
+		return ret;
+	}
 
-	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, iram_virt_base);
+	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, virt_base);
 	return 0;
 }
 
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:27:04 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:27:04 +0200
Subject: [PATCH v2 9/9] ARM i.MX: remove IRAM_ALLOC facility
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-10-git-send-email-p.zabel@pengutronix.de>

A generic on-chip SRAM allocator driver can be used instead.
Users of the iram_alloc/free API should convert to the genalloc API:

-	virt = iram_alloc(SIZE, &phys);
+	gen_pool_alloc(iram_pool, SIZE);
+	phys = gen_pool_virt_to_phys(iram_pool, virt);
 	/* ... */
-	iram_free(virt, SIZE);
+	gen_pool_free(iram_pool, virt, SIZE);

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/Kconfig             |    4 --
 arch/arm/plat-mxc/Makefile            |    1 -
 arch/arm/plat-mxc/include/mach/iram.h |   35 ----------
 arch/arm/plat-mxc/iram_alloc.c        |  116 ---------------------------------
 4 files changed, 156 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/iram.h
 delete mode 100644 arch/arm/plat-mxc/iram_alloc.c

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index baf9064..8e63f10 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -82,8 +82,4 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config IRAM_ALLOC
-	bool
-	select GENERIC_ALLOCATOR
-
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 6ac7200..bdf370f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
-obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
deleted file mode 100644
index d5c863f..0000000
--- a/arch/arm/plat-mxc/include/mach/iram.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/errno.h>
-
-#ifdef CONFIG_IRAM_ALLOC
-
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
-void iram_free(unsigned long dma_addr, unsigned int size);
-
-#else
-
-static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	return NULL;
-}
-
-static inline void iram_free(unsigned long base, unsigned long size) {}
-
-#endif
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
deleted file mode 100644
index 343e96d..0000000
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/genalloc.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <mach/iram.h>
-
-static struct gen_pool *iram_pool;
-
-void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
-{
-	unsigned long virt;
-
-	if (!iram_pool)
-		return NULL;
-
-	virt = gen_pool_alloc(iram_pool, size);
-	pr_debug("iram alloc - %dB at 0x%lX\n", size, *dma_addr);
-	if (!virt)
-		return NULL;
-
-	*dma_addr = gen_pool_virt_to_phys(iram_pool, virt);
-	return (void __iomem *)virt;
-}
-EXPORT_SYMBOL(iram_alloc);
-
-void iram_free(unsigned long addr, unsigned int size)
-{
-	if (!iram_pool)
-		return;
-
-	gen_pool_free(iram_pool, addr, size);
-}
-EXPORT_SYMBOL(iram_free);
-
-static int __devinit iram_probe(struct platform_device *pdev)
-{
-	void __iomem *virt_base;
-	struct resource *res;
-	unsigned long size;
-	int ret;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -EINVAL;
-
-	if (iram_pool)
-		return -EBUSY;
-
-	size = resource_size(res);
-
-	virt_base = devm_ioremap(&pdev->dev, res->start, size);
-	if (!virt_base)
-		return -ENOMEM;
-
-	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
-	if (!iram_pool)
-		return -ENOMEM;
-
-	ret = gen_pool_add_virt(iram_pool, (unsigned long)virt_base,
-				res->start, size, -1);
-	if (ret < 0) {
-		gen_pool_destroy(iram_pool);
-		iram_pool = NULL;
-		return ret;
-	}
-
-	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, virt_base);
-	return 0;
-}
-
-static int __devexit iram_remove(struct platform_device *pdev)
-{
-	gen_pool_destroy(iram_pool);
-	iram_pool = NULL;
-	return 0;
-}
-
-#ifdef CONFIG_OF
-static struct of_device_id iram_dt_ids[] = {
-	{ .compatible = "fsl,imx-iram" },
-	{ /* sentinel */ }
-};
-#endif
-
-static struct platform_driver iram_driver = {
-	.driver = {
-		.name = "imx-iram",
-		.of_match_table = of_match_ptr(iram_dt_ids),
-	},
-	.probe = iram_probe,
-	.remove = __devexit_p(iram_remove),
-};
-
-module_platform_driver(iram_driver);
-- 
1.7.10.4



From p.zabel at pengutronix.de  Fri Aug 31 05:26:56 2012
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Fri, 31 Aug 2012 11:26:56 +0200
Subject: [PATCH v2 1/9] ARM i.MX: Switch IRAM allocator to device tree
 initialization
In-Reply-To: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405224-20399-2-git-send-email-p.zabel@pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/iram.h |    6 -----
 arch/arm/plat-mxc/iram_alloc.c        |   44 ++++++++++++++++++++++++++++++---
 2 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
index 022690c..d5c863f 100644
--- a/arch/arm/plat-mxc/include/mach/iram.h
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -20,17 +20,11 @@
 
 #ifdef CONFIG_IRAM_ALLOC
 
-int __init iram_init(unsigned long base, unsigned long size);
 void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
 void iram_free(unsigned long dma_addr, unsigned int size);
 
 #else
 
-static inline int __init iram_init(unsigned long base, unsigned long size)
-{
-	return -ENOMEM;
-}
-
 static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
 {
 	return NULL;
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
index 074c386..673deb4 100644
--- a/arch/arm/plat-mxc/iram_alloc.c
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -22,6 +22,8 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/genalloc.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
 #include <mach/iram.h>
 
 static unsigned long iram_phys_base;
@@ -55,15 +57,26 @@ void iram_free(unsigned long addr, unsigned int size)
 }
 EXPORT_SYMBOL(iram_free);
 
-int __init iram_init(unsigned long base, unsigned long size)
+static int __devinit iram_probe(struct platform_device *pdev)
 {
-	iram_phys_base = base;
+	struct resource *res;
+	unsigned long size;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -EINVAL;
+
+	if (iram_phys_base)
+		return -EBUSY;
+
+	iram_phys_base = res->start;
+	size = resource_size(res);
 
 	iram_pool = gen_pool_create(PAGE_SHIFT, -1);
 	if (!iram_pool)
 		return -ENOMEM;
 
-	gen_pool_add(iram_pool, base, size, -1);
+	gen_pool_add(iram_pool, res->start, size, -1);
 	iram_virt_base = ioremap(iram_phys_base, size);
 	if (!iram_virt_base)
 		return -EIO;
@@ -71,3 +84,28 @@ int __init iram_init(unsigned long base, unsigned long size)
 	pr_debug("i.MX IRAM pool: %ld KB at 0x%p\n", size / 1024, iram_virt_base);
 	return 0;
 }
+
+static int __devexit iram_remove(struct platform_device *pdev)
+{
+	gen_pool_destroy(iram_pool);
+	iram_pool = NULL;
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static struct of_device_id iram_dt_ids[] = {
+	{ .compatible = "fsl,imx-iram" },
+	{ /* sentinel */ }
+};
+#endif
+
+static struct platform_driver iram_driver = {
+	.driver = {
+		.name = "imx-iram",
+		.of_match_table = of_match_ptr(iram_dt_ids),
+	},
+	.probe = iram_probe,
+	.remove = __devexit_p(iram_remove),
+};
+
+module_platform_driver(iram_driver);
-- 
1.7.10.4



From anilkumar at ti.com  Fri Aug 31 05:29:17 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:17 +0530
Subject: [PATCH v5 1/5] arm/dts: AM33XX: Add basic pinctrl device tree data
In-Reply-To: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405361-29711-2-git-send-email-anilkumar@ti.com>

Adds basic pinctrl device tree data for AM33XX family of devices.
This patch is based on the pinctrl-single driver.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index be43511..bf5f713 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -40,6 +40,15 @@
 		};
 	};
 
+	am3358_pinmux: pinmux at 44e10800 {
+		compatible = "pinctrl-single";
+		reg = <0x44e10800 0x0238>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7f>;
+	};
+
 	/*
 	 * XXX: Use a flat representation of the AM33XX interconnect.
 	 * The real AM33XX interconnect network is quite complex.Since
-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:29:19 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:19 +0530
Subject: [PATCH v5 3/5] arm/dts: AM33XX: Add D_CAN device tree data
In-Reply-To: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405361-29711-4-git-send-email-anilkumar@ti.com>

Add Bosch D_CAN controller device tree data to AM33XX dtsi
file by adding d_can device nodes with all the necessary
parameters.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am33xx.dtsi |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bf5f713..ab744d6 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -177,5 +177,23 @@
 			compatible = "ti,omap3-wdt";
 			ti,hwmods = "wd_timer2";
 		};
+
+		dcan0: d_can at 481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			reg = <0x481cc000 0x2000>;
+			interrupts = <52>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		dcan1: d_can at 481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			reg = <0x481d0000 0x2000>;
+			interrupts = <55>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
 	};
 };
-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:29:18 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:18 +0530
Subject: [PATCH v5 2/5] arm/dts: AM33XX: Configure pinmuxs for user leds
 control on Bone
In-Reply-To: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405361-29711-3-git-send-email-anilkumar@ti.com>

Adds GPIO pinctrl nodes to am3358_pinmux master node to control
user leds (USR0, USR1, USR2 and USR3) present on BeagleBone.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |   41 +++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87..ce486fc 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -18,11 +18,52 @@
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 
+	am3358_pinmux: pinmux at 44e10800 {
+		userled_pins: pinmux_userled_pins {
+			pinctrl-single,pins = <
+				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+				0x5c 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+			>;
+		};
+	};
+
 	ocp {
 		uart1: serial at 44e09000 {
 			status = "okay";
 		};
 
+		gpio-leds {
+			compatible = "gpio-leds";
+			pinctrl-names = "default";
+			pinctrl-0 = <&userled_pins>;
+
+			led0 {
+				label = "status:green:user0";
+				gpios = <&gpio2 21 0>;
+				default-state = "off";
+			};
+
+			led1 {
+				label = "status:green:user1";
+				gpios = <&gpio2 22 0>;
+				default-state = "off";
+			};
+
+			led2 {
+				label = "status:green:user2";
+				gpios = <&gpio2 23 0>;
+				default-state = "off";
+			};
+
+			led3 {
+				label = "status:green:user3";
+				gpios = <&gpio2 24 0>;
+				default-state = "off";
+			};
+		};
+
 		i2c1: i2c at 44e0b000 {
 			status = "okay";
 			clock-frequency = <400000>;
-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:29:20 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:20 +0530
Subject: [PATCH 4/5] leds: leds-gpio: adopt pinctrl support
In-Reply-To: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405361-29711-5-git-send-email-anilkumar@ti.com>

Adopt pinctrl support to leds-gpio driver, based on the device
pointer (leds-gpio) pinctrl driver configure SoC pins to GPIO
mode.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 drivers/leds/leds-gpio.c |   31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
index c032b21..d98dfb9 100644
--- a/drivers/leds/leds-gpio.c
+++ b/drivers/leds/leds-gpio.c
@@ -20,6 +20,7 @@
 #include <linux/slab.h>
 #include <linux/workqueue.h>
 #include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
 
 struct gpio_led_data {
 	struct led_classdev cdev;
@@ -236,14 +237,23 @@ static int __devinit gpio_led_probe(struct platform_device *pdev)
 {
 	struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
 	struct gpio_leds_priv *priv;
-	int i, ret = 0;
+	struct pinctrl *pinctrl;
+	int i = 0;
+	int ret = 0;
+
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl)) {
+		return PTR_ERR(pinctrl);
+	}
 
 	if (pdata && pdata->num_leds) {
 		priv = devm_kzalloc(&pdev->dev,
 				sizeof_gpio_leds_priv(pdata->num_leds),
 					GFP_KERNEL);
-		if (!priv)
-			return -ENOMEM;
+		if (!priv) {
+			ret = -ENOMEM;
+			goto err_pctrl_put;
+		}
 
 		priv->num_leds = pdata->num_leds;
 		for (i = 0; i < priv->num_leds; i++) {
@@ -254,18 +264,25 @@ static int __devinit gpio_led_probe(struct platform_device *pdev)
 				/* On failure: unwind the led creations */
 				for (i = i - 1; i >= 0; i--)
 					delete_gpio_led(&priv->leds[i]);
-				return ret;
+				goto err_pctrl_put;
 			}
 		}
 	} else {
 		priv = gpio_leds_create_of(pdev);
-		if (!priv)
-			return -ENODEV;
+		if (!priv) {
+			ret = -ENODEV;
+			goto err_del_gpio_led;
+		}
 	}
 
 	platform_set_drvdata(pdev, priv);
 
-	return 0;
+err_pctrl_put:
+	pinctrl_put(pinctrl);
+err_del_gpio_led:
+	while (--i >= 0)
+		delete_gpio_led(&priv->leds[i]);
+	return ret;
 }
 
 static int __devexit gpio_led_remove(struct platform_device *pdev)
-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:29:16 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:16 +0530
Subject: [PATCH v5 0/5] Add device tree data for AM33XX devices
Message-ID: <1346405361-29711-1-git-send-email-anilkumar@ti.com>

Add pinctrl and d_can device tree data to AM33XX family of devices.
First two patches add support for pinctrl DT data and third one
adds dcan DT data.

Reason behind combining these patches is to apply cleanly on
linux-omap tree, because these are sequential patches.

These patches were tested on AM335x-Bone, AM335x-EVM and based
on linux-omap:master with this patch
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg74393.html

d_can:
  Changes from v4:
	- Incorporated Tony's comments on v4
	  * Converted all hex numbers to lower-case.
	- Updated C_CAN bindings documentation according to recent
	  changes.

  Changes from v3:
	- Removed d_can1 node from am335x-evm.dts file. Instance
	  one of CAN (d_can1) is available on AM335x-EVM only under
	  a specific CPLD mode selection. am335x-evm.dts does not
          support this mode so remove the d_can1 node.
	- Dropped d_can pinmux settings patch, above comment
	  applies here as well.

  Changes from v2:
	- Incorporated Vaibhav H's comments on v2
	  * Added dcan0 instances to am33xx.dtsi file

  Changes from v1:
	- These two patches separated from c_can DT support
	  patch series.

pinctrl:
  Changes from v4:
	- Incorporated Tony's comments on v4
	  * Converted all hex numbers to lower-case.
	- Added pinctrl api to leds-gpio driver to configure led
	  pins to GPIO mode.

  Changes from v3:
	- Updated the reg length based on latest AM335x TRM.

  Changes from v2:
	- user led pinmux comments updated according to Tony's
	  comment.

  Changes from v1:
	- Rebased the patches based on latest pinctrl-single driver

AnilKumar Ch (5):
  arm/dts: AM33XX: Add basic pinctrl device tree data
  arm/dts: AM33XX: Configure pinmuxs for user leds control on Bone
  arm/dts: AM33XX: Add D_CAN device tree data
  leds: leds-gpio: adopt pinctrl support
  of: Modify c_can binding documentation

 .../devicetree/bindings/net/can/c_can.txt          |   25 +++++++++---
 arch/arm/boot/dts/am335x-bone.dts                  |   41 ++++++++++++++++++++
 arch/arm/boot/dts/am33xx.dtsi                      |   27 +++++++++++++
 drivers/leds/leds-gpio.c                           |   31 +++++++++++----
 4 files changed, 112 insertions(+), 12 deletions(-)

-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:29:21 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 14:59:21 +0530
Subject: [PATCH 5/5] of: Modify c_can binding documentation
In-Reply-To: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405361-29711-6-git-send-email-anilkumar@ti.com>

Modify c_can binding documentation according to recent review comments
on device tree data addition patches.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 .../devicetree/bindings/net/can/c_can.txt          |   25 ++++++++++++++++----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index a43f083..90a70be 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -8,6 +8,8 @@ Required properties:
 			  registers map
 - interrupts		: property with a value describing the interrupt
 			  number
+- status		: describes the node status either "disabled" or
+			  "okay"
 
 Optional properties:
 - interrupt-parent	: The parent interrupt controller
@@ -20,18 +22,31 @@ Future plan is to migrate hwmod data base contents into device tree
 blob so that, all the required data will be used from device tree dts
 file.
 
-Examples:
+Example:
 
-	d_can at 481D0000 {
+Step1: SoC common .dtsi file
+
+	d_can1: d_can at 481d0000 {
 		compatible = "bosch,d_can";
-		reg = <0x481D0000 0x1000>;
-		interrupts = <55 0x4>;
+		reg = <0x481d0000 0x2000>;
+		interrupts = <55>;
 		interrupt-parent = <&intc>;
+		status = "disabled";
 	};
 
 (or)
 
-	d_can at 481D0000 {
+	d_can1: d_can at 481d0000 {
 		compatible = "bosch,d_can";
 		ti,hwmods = "d_can1";
+		reg = <0x481d0000 0x2000>;
+		interrupts = <55>;
+		interrupt-parent = <&intc>;
+		status = "disabled";
+	};
+
+Step 2: board specific .dts file
+
+	&dcan1 {
+		status = "okay";
 	};
-- 
1.7.9.5



From b-cousson at ti.com  Fri Aug 31 05:32:41 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 Aug 2012 11:32:41 +0200
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
 <503229F5.4030405@ti.com>
 <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>
Message-ID: <504084B9.3000701@ti.com>

Hi Sourav,

While rebasing your series on top of Tony's lo/devel-dt, I realized that the keypad nodes are not located at the correct place :-(

At the moment they are just floating at the top level of the dts while they belong to the ocp bus and thus should be put there.

I fixed that since it was trivial and cleaned as well the changelog and the comments to aligned then properly. I added as well the physical address to the node name and a label for easy reference at board level.

I did some basic test on my OMAP4 sdp, but that all I can do so far.

Could you just check if this is still fine for OMAP5 before I ask Tony to pull that.

I based that on top of Tony's DT patches due to conflict with the existing MMC patch in it.



The following changes since commit 85d7ff9b907685b6469058888f1d961b3e8d47ad:
  Olof Johansson (1):
        ARM: omap: add dtb targets

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.7/dts

Sourav Poddar (6):
      arm/dts: omap5-evm: Add I2C support
      arm/dts: omap5-evm: Add tmp102 sensor support
      arm/dts: omap5-evm: Add keypad data
      arm/dts: omap5-evm: Add bmp085 sensor support
      arm/dts: omap4-sdp: Add keypad data
      Documentation: dt: i2c: trivial-devices: Update for tmp102

 .../devicetree/bindings/i2c/trivial-devices.txt    |    1 +
 arch/arm/boot/dts/omap4-sdp.dts                    |   70 ++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi                       |    5 ++
 arch/arm/boot/dts/omap5-evm.dts                    |   33 +++++++++
 arch/arm/boot/dts/omap5.dtsi                       |   40 +++++++++++
 5 files changed, 149 insertions(+), 0 deletions(-)

Regards,
Benoit



From jlu at pengutronix.de  Fri Aug 31 05:37:28 2012
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Fri, 31 Aug 2012 11:37:28 +0200
Subject: [PATCH v2 6/9] misc: Generic on-chip SRAM allocation driver
In-Reply-To: <1346405224-20399-7-git-send-email-p.zabel@pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
 <1346405224-20399-7-git-send-email-p.zabel@pengutronix.de>
Message-ID: <1346405848.5316.11.camel@coredoba.hi.pengutronix.de>

On Fri, 2012-08-31 at 11:27 +0200, Philipp Zabel wrote:
> This driver requests and remaps a memory region as configured in the
> device tree. It serves memory from this region via the genalloc API.
> 
> Other drivers can retrieve the genalloc pool from a phandle pointing
> to this drivers' device node in the device tree.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> ---
>  drivers/misc/Kconfig  |    8 ++++
>  drivers/misc/Makefile |    1 +
>  drivers/misc/sram.c   |  105 +++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 114 insertions(+)
>  create mode 100644 drivers/misc/sram.c

We now have drivers/memory, which seems to be a good place for this.

Regards,
Jan
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From anilkumar at ti.com  Fri Aug 31 05:37:20 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 15:07:20 +0530
Subject: [PATCH 2/2] arm/dts: AM33XX: Add device tree OPP table
In-Reply-To: <1346405840-31058-1-git-send-email-anilkumar@ti.com>
References: <1346405840-31058-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405840-31058-3-git-send-email-anilkumar@ti.com>

Add DT OPP table for AM33XX family of devices. This data is
decoded by OF with of_init_opp_table() helper function.

Also adds cpu0 supply name to the corresponding dts files.
cpu0-supply name is used by cpufreq-cpu0 driver to get the
regulator pointer for voltage modifications.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |    6 ++++++
 arch/arm/boot/dts/am335x-evm.dts  |    6 ++++++
 arch/arm/boot/dts/am33xx.dtsi     |   15 +++++++++++++++
 3 files changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index ce486fc..2767b5f 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -13,6 +13,12 @@
 	model = "TI AM335x BeagleBone";
 	compatible = "ti,am335x-bone", "ti,am33xx";
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&dcdc2_reg>;
+		};
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index baa3276..54d972c 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -13,6 +13,12 @@
 	model = "TI AM335x EVM";
 	compatible = "ti,am335x-evm", "ti,am33xx";
 
+	cpus {
+		cpu at 0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index ab744d6..2043b53 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -25,6 +25,21 @@
 	cpus {
 		cpu at 0 {
 			compatible = "arm,cortex-a8";
+
+			/*
+			 * To consider voltage drop between PMIC and SoC,
+			 * tolerance value is reduced to 2% from 4% and
+			 * voltage value is increased as a precaution.
+			 */
+			operating-points = <
+				/* kHz    uV */
+				720000  1285000
+				600000  1225000
+				500000  1125000
+				275000  1125000
+			>;
+			voltage-tolerance = <2>; /* 2 percentage */
+			clock-latency = <300000>; /* From omap-cpufreq driver */
 		};
 	};
 
-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:37:18 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 15:07:18 +0530
Subject: [PATCH 0/2] ARM: OMAP2: AM33XX: Add cpufreq support
Message-ID: <1346405840-31058-1-git-send-email-anilkumar@ti.com>

Add cpufreq support to AM33XX family of devices by adding OPP
information, clock entry with cpu0 name and voltage supplies
to cpu0.

These patches have been tested on AM335x-EVM, AM335x-Bone and
these patches are based on cpufreq-cpu0 driver
http://marc.info/?l=linux-arm-kernel&m=134457735413293&w=2

AnilKumar Ch (2):
  ARM: OMAP2+: AM33XX: Add clock entries to omap_clk data
  arm/dts: AM33XX: Add device tree OPP table

 arch/arm/boot/dts/am335x-bone.dts    |    6 ++++++
 arch/arm/boot/dts/am335x-evm.dts     |    6 ++++++
 arch/arm/boot/dts/am33xx.dtsi        |   15 +++++++++++++++
 arch/arm/mach-omap2/clock33xx_data.c |    1 +
 4 files changed, 28 insertions(+)

-- 
1.7.9.5



From anilkumar at ti.com  Fri Aug 31 05:37:19 2012
From: anilkumar at ti.com (AnilKumar Ch)
Date: Fri, 31 Aug 2012 15:07:19 +0530
Subject: [PATCH 1/2] ARM: OMAP2+: AM33XX: Add clock entries to omap_clk data
In-Reply-To: <1346405840-31058-1-git-send-email-anilkumar@ti.com>
References: <1346405840-31058-1-git-send-email-anilkumar@ti.com>
Message-ID: <1346405840-31058-2-git-send-email-anilkumar@ti.com>

Add AM335x cpu0 clock entry to the corresponding clock data
file. This is useful in getting the correct mpu clock pointer
to change the cpu frequency in cpufreq driver.

Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
---
 arch/arm/mach-omap2/clock33xx_data.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 23251fa..7afefe8 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"dpll_core_m5_ck",	&dpll_core_m5_ck,	CK_AM33XX),
 	CLK(NULL,	"dpll_core_m6_ck",	&dpll_core_m6_ck,	CK_AM33XX),
 	CLK(NULL,	"dpll_mpu_ck",		&dpll_mpu_ck,	CK_AM33XX),
+	CLK("cpu0",	NULL,			&dpll_mpu_ck,		CK_AM33XX),
 	CLK(NULL,	"dpll_mpu_m2_ck",	&dpll_mpu_m2_ck,	CK_AM33XX),
 	CLK(NULL,	"dpll_ddr_ck",		&dpll_ddr_ck,	CK_AM33XX),
 	CLK(NULL,	"dpll_ddr_m2_ck",	&dpll_ddr_m2_ck,	CK_AM33XX),
-- 
1.7.9.5



From santosh.shilimkar at ti.com  Fri Aug 31 05:40:50 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 31 Aug 2012 02:40:50 -0700
Subject: [PATCH v2 6/9] misc: Generic on-chip SRAM allocation driver
In-Reply-To: <1346405848.5316.11.camel@coredoba.hi.pengutronix.de>
References: <1346405224-20399-1-git-send-email-p.zabel@pengutronix.de>
 <1346405224-20399-7-git-send-email-p.zabel@pengutronix.de>
 <1346405848.5316.11.camel@coredoba.hi.pengutronix.de>
Message-ID: <CAMQu2gxsdeX4z2Zrnb2NW7-gnh2Tyjcxkd2pOMOagkdkHGsgWQ@mail.gmail.com>

On Fri, Aug 31, 2012 at 2:37 AM, Jan L?bbe <jlu at pengutronix.de> wrote:
>
> On Fri, 2012-08-31 at 11:27 +0200, Philipp Zabel wrote:
> > This driver requests and remaps a memory region as configured in the
> > device tree. It serves memory from this region via the genalloc API.
> >
> > Other drivers can retrieve the genalloc pool from a phandle pointing
> > to this drivers' device node in the device tree.
> >
> > Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> > ---
> >  drivers/misc/Kconfig  |    8 ++++
> >  drivers/misc/Makefile |    1 +
> >  drivers/misc/sram.c   |  105
> > +++++++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 114 insertions(+)
> >  create mode 100644 drivers/misc/sram.c
>
> We now have drivers/memory, which seems to be a good place for this.
>
drivers/memory is created for Memory controller device drivers. SRAM is
just pool of memory and should belong to some other place.

Regards
Santosh


From lee.jones at linaro.org  Fri Aug 31 05:44:38 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 10:44:38 +0100
Subject: [PATCH 2/8] irqdomain: Take interrupt-parent property into
 account if specified
In-Reply-To: <CACRpkdZMoisfUD_NSkVy2w-jZVUDGn0E8LmvKSWnJ0YRGZO-tQ@mail.gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdZMoisfUD_NSkVy2w-jZVUDGn0E8LmvKSWnJ0YRGZO-tQ@mail.gmail.com>
Message-ID: <20120831094434.GF13298@gmail.com>

On Tue, Aug 14, 2012 at 10:19:08AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > irq_find_host() currently ignores the 'interrupt-parent' property
> > even if it's specified in the Device Tree. Meaning that a node can
> > match to a domain in its hierarchy even if it doesn't belong to it.
> > By searching for the parent first using of_irq_find_parent() we
> > insist that the 'interrupt-parent' property is taken into account
> > ensuring a greater chance of returning the correct domain.
> >
> > CC: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> > CC: Grant Likely <grant.likely at secretlab.ca>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> This (with 1/8) is the right solution. Thanks, and I think
> Mark may want to look at this too since I recognize he asked
> you to work in this direction.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Rob, did this get your Ack too?

Ben, Grant, Mark, would you like to take a look also?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From Barry.Song at csr.com  Fri Aug 31 05:44:55 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 31 Aug 2012 17:44:55 +0800
Subject: [PATCH 1/2] ARM: exynos: delete redundant HAVE_SCHED_CLOCK option in
 Kconfig
Message-ID: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/mach-exynos/Kconfig |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c..3fd4ab3 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -243,7 +243,6 @@ config MACH_UNIVERSAL_C210
 	select CPU_EXYNOS4210
 	select S5P_HRT
 	select CLKSRC_MMIO
-	select HAVE_SCHED_CLOCK
 	select S5P_GPIO_INT
 	select S5P_DEV_FIMC0
 	select S5P_DEV_FIMC1
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From Barry.Song at csr.com  Fri Aug 31 05:44:56 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 31 Aug 2012 17:44:56 +0800
Subject: [PATCH 2/2] ARM: timer_sp804: delete redundant HAVE_SCHED_CLOCK
 option in Kconfig
In-Reply-To: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
References: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
Message-ID: <1346406296-16223-2-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/Kconfig |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2c1ca9f..00ef0e0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1157,7 +1157,6 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
 	bool
 	select CLKSRC_MMIO
-	select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
 
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From kmpark at infradead.org  Fri Aug 31 05:52:19 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 31 Aug 2012 18:52:19 +0900
Subject: [PATCH 1/2] ARM: exynos: delete redundant HAVE_SCHED_CLOCK option
 in Kconfig
In-Reply-To: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
References: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
Message-ID: <CAH9JG2W8xZrkmGkVw_JDY3qSsqHnaTi8-BNoW99V3FUyvWBXng@mail.gmail.com>

Hi,

then where select it HAVE_SCHED_CLOCK? apart from other exynos board,
universal have to use another clock.

Thank you,
Kyungmin Park

On 8/31/12, Barry Song <Barry.Song at csr.com> wrote:
> From: Barry Song <Baohua.Song at csr.com>
>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  arch/arm/mach-exynos/Kconfig |    1 -
>  1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index b5b4c8c..3fd4ab3 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -243,7 +243,6 @@ config MACH_UNIVERSAL_C210
>  	select CPU_EXYNOS4210
>  	select S5P_HRT
>  	select CLKSRC_MMIO
> -	select HAVE_SCHED_CLOCK
>  	select S5P_GPIO_INT
>  	select S5P_DEV_FIMC0
>  	select S5P_DEV_FIMC1
> --
> 1.7.0.4
>
>
>
> Member of the CSR plc group of companies. CSR plc registered in England and
> Wales, registered number 4187346, registered office Churchill House,
> Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
> More information can be found at www.csr.com. Follow CSR on Twitter at
> http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From florian.vaussard at epfl.ch  Fri Aug 31 05:53:37 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 11:53:37 +0200
Subject: [PATCH 1/2] i2c-omap: Fix incorrect adapter id when booting from
 a device tree
In-Reply-To: <5040806C.9080003@ti.com>
References: <1346399575-7285-1-git-send-email-florian.vaussard@epfl.ch>
 <1346399575-7285-2-git-send-email-florian.vaussard@epfl.ch>
 <5040806C.9080003@ti.com>
Message-ID: <504089A1.3030000@epfl.ch>

Hi Benoit,

> [    0.658843] omap_i2c i2c.15: bus -1 rev2.4.0 at 400 kHz
> [    0.760192] omap_i2c i2c.16: bus -1 rev2.4.0 at 400 kHz
> [    0.775817] omap_i2c i2c.17: bus -1 rev2.4.0 at 400 kHz
> [    0.791442] omap_i2c i2c.18: bus -1 rev2.4.0 at 400 kHz
>
> OK, it is true that the current log is not that nice with bus -1, but
> maybe we should just remove that.
>
> Or we can potentially retrieve the i2c adapter number assign later, and
> delay the log.
>
>>   	r = i2c_add_numbered_adapter(adap);
>>   	if (r) {
>>   		dev_err(dev->dev, "failure adding adapter\n");
I agree, we should defer the log if we want a nice print. I will send a 
new patch.

Regards,
Florian


From alan at lxorguk.ukuu.org.uk  Fri Aug 31 06:04:44 2012
From: alan at lxorguk.ukuu.org.uk (Alan Cox)
Date: Fri, 31 Aug 2012 11:04:44 +0100
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
Message-ID: <20120831110444.25d9b9fe@pyramind.ukuu.org.uk>

On Fri, 31 Aug 2012 11:21:56 +0200
Matthieu CASTET <castet.matthieu at free.fr> wrote:

> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
> ---
>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)

This is a step in the wrong direction. This should all be runtime handled

NAK.


From shawn.guo at linaro.org  Thu Aug 30 17:01:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 05:01:55 +0800
Subject: [PATCH] clk: mxs: Register USB clocks for mx23
In-Reply-To: <CAOMZO5CZjOopAy1EhWOOCszgJQNW52Z-UPjzVwU6MAp_HtDCzw@mail.gmail.com>
References: <1340148392-9847-1-git-send-email-festevam@gmail.com>
 <20120620143830.GF2253@S2101-09.ap.freescale.net>
 <CAOMZO5AaLKN9bhuPRLJkA8ytiwVi_yrpwzL0mJAzf6VS4PSRLQ@mail.gmail.com>
 <20120806030014.GB22302@S2101-09.ap.freescale.net>
 <CAOMZO5AME0NXarMF_rarYJeQ4-rGc+DpV7nvL4OeQj+LfkLLQw@mail.gmail.com>
 <CAOMZO5CZjOopAy1EhWOOCszgJQNW52Z-UPjzVwU6MAp_HtDCzw@mail.gmail.com>
Message-ID: <20120830210155.GA3617@r65073-Latitude-D630>

On Thu, Aug 30, 2012 at 11:09:49AM -0300, Fabio Estevam wrote:
> Shawn,
> 
> On Mon, Aug 13, 2012 at 12:06 AM, Fabio Estevam <festevam at gmail.com> wrote:
> > Shawn,
> >
> > On Mon, Aug 6, 2012 at 12:00 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> >
> >> Probably, no, as I plan to freeze the addition to clkdev lookup table
> >> and replace it with DT clock lookup.
> >
> > Could you please suggest how can I register the USB clocks for mx23?
> > Any example I can refer to implement a "DT clock lookup"?
> 
> Ping?
> 
> I saw some patches from you that changes the way dt clocks are
> registered for mx23/mx28, but not sure if these were applied or not.
> 
The v2 patch solving Russell's comment has been acked by Rob.  I'm
waiting for Mike to apply it, and then I can publish a mxs branch
based on that.

> Please let me know how should I proceed regarding mx23 usb clocks registration.
> 
> Regards,
> 
> Fabio Estevam

-- 
Regards,
Shawn


From 21cnbao at gmail.com  Fri Aug 31 06:05:17 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 31 Aug 2012 18:05:17 +0800
Subject: [PATCH 1/2] ARM: exynos: delete redundant HAVE_SCHED_CLOCK option
 in Kconfig
In-Reply-To: <CAH9JG2W8xZrkmGkVw_JDY3qSsqHnaTi8-BNoW99V3FUyvWBXng@mail.gmail.com>
References: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
 <CAH9JG2W8xZrkmGkVw_JDY3qSsqHnaTi8-BNoW99V3FUyvWBXng@mail.gmail.com>
Message-ID: <CAGsJ_4xUBDGn1hDdWvUX68MfC98936v-_vLfPrisLNL7RY6nEw@mail.gmail.com>

2012/8/31 Kyungmin Park <kmpark at infradead.org>:
> Hi,
>
> then where select it HAVE_SCHED_CLOCK? apart from other exynos board,
> universal have to use another clock.

The old arch/arm/kernel/Makefile:
obj-$(CONFIG_HAVE_SCHED_CLOCK)  += sched_clock.o
has become:
obj-y += sched_clock.o

>
> Thank you,
> Kyungmin Park
>
> On 8/31/12, Barry Song <Barry.Song at csr.com> wrote:
>> From: Barry Song <Baohua.Song at csr.com>
>>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> ---
>>  arch/arm/mach-exynos/Kconfig |    1 -
>>  1 files changed, 0 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index b5b4c8c..3fd4ab3 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -243,7 +243,6 @@ config MACH_UNIVERSAL_C210
>>       select CPU_EXYNOS4210
>>       select S5P_HRT
>>       select CLKSRC_MMIO
>> -     select HAVE_SCHED_CLOCK
>>       select S5P_GPIO_INT
>>       select S5P_DEV_FIMC0
>>       select S5P_DEV_FIMC1
>> --
>> 1.7.0.4
>>
-barry


From shawn.guo at linaro.org  Thu Aug 30 17:05:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 05:05:43 +0800
Subject: [PATCH 0/2] mmc: mxs-mmc: fix deadlocks
In-Reply-To: <503C7C78.7080700@bluegiga.com>
References: <1342534570-8293-1-git-send-email-lauri.hintsala@bluegiga.com>
 <503C7C78.7080700@bluegiga.com>
Message-ID: <20120830210540.GA3613@r65073-Latitude-D630>

On Tue, Aug 28, 2012 at 11:08:24AM +0300, Lauri Hintsala wrote:
> On 07/17/2012 05:16 PM, Lauri Hintsala wrote:
> >Two different deadlock fixes in cases with SDIO IRQs
> >generated by SDIO device.
> 
> Any comments? Could they be applied?
> 
Chris, can you please send these two fixes for 3.6?  Also, stable
should be Cc-ed.

-- 
Regards,
Shawn


From cjb at laptop.org  Fri Aug 31 06:11:16 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 31 Aug 2012 06:11:16 -0400
Subject: [PATCH 1/2] mmc: mxs-mmc: fix deadlock in SDIO IRQ case
In-Reply-To: <1342534570-8293-2-git-send-email-lauri.hintsala@bluegiga.com>
 (Lauri Hintsala's message of "Tue, 17 Jul 2012 17:16:09 +0300")
References: <1342534570-8293-1-git-send-email-lauri.hintsala@bluegiga.com>
 <1342534570-8293-2-git-send-email-lauri.hintsala@bluegiga.com>
Message-ID: <87y5kvnzgb.fsf@octavius.laptop.org>

Hi,

On Tue, Jul 17 2012, Lauri Hintsala wrote:
> Release the lock before mmc_signal_sdio_irq is called by mxs_mmc_irq_handler.
>
> Backtrace:
> [   79.660000] =============================================
> [   79.660000] [ INFO: possible recursive locking detected ]
> [   79.660000] 3.4.0-00009-g3e96082-dirty #11 Not tainted
> [   79.660000] ---------------------------------------------
> [   79.660000] swapper/0 is trying to acquire lock:
> [   79.660000]  (&(&host->lock)->rlock#2){-.....}, at: [<c026ea3c>] mxs_mmc_enable_sdio_irq+0x18/0xd4
> [   79.660000]
> [   79.660000] but task is already holding lock:
> [   79.660000]  (&(&host->lock)->rlock#2){-.....}, at: [<c026f744>] mxs_mmc_irq_handler+0x1c/0xe8
> [   79.660000]
> [   79.660000] other info that might help us debug this:
> [   79.660000]  Possible unsafe locking scenario:
> [   79.660000]
> [   79.660000]        CPU0
> [   79.660000]        ----
> [   79.660000]   lock(&(&host->lock)->rlock#2);
> [   79.660000]   lock(&(&host->lock)->rlock#2);
> [   79.660000]
> [   79.660000]  *** DEADLOCK ***
> [   79.660000]
> [   79.660000]  May be due to missing lock nesting notation
> [   79.660000]
> [   79.660000] 1 lock held by swapper/0:
> [   79.660000]  #0:  (&(&host->lock)->rlock#2){-.....}, at: [<c026f744>] mxs_mmc_irq_handler+0x1c/0xe8
> [   79.660000]
> [   79.660000] stack backtrace:
> [   79.660000] [<c0014bd0>] (unwind_backtrace+0x0/0xf4) from [<c005f9c0>] (__lock_acquire+0x1948/0x1d48)
> [   79.660000] [<c005f9c0>] (__lock_acquire+0x1948/0x1d48) from [<c005fea0>] (lock_acquire+0xe0/0xf8)
> [   79.660000] [<c005fea0>] (lock_acquire+0xe0/0xf8) from [<c03a8460>] (_raw_spin_lock_irqsave+0x44/0x58)
> [   79.660000] [<c03a8460>] (_raw_spin_lock_irqsave+0x44/0x58) from [<c026ea3c>] (mxs_mmc_enable_sdio_irq+0x18/0xd4)
> [   79.660000] [<c026ea3c>] (mxs_mmc_enable_sdio_irq+0x18/0xd4) from [<c026f7fc>] (mxs_mmc_irq_handler+0xd4/0xe8)
> [   79.660000] [<c026f7fc>] (mxs_mmc_irq_handler+0xd4/0xe8) from [<c006bdd8>] (handle_irq_event_percpu+0x70/0x254)
> [   79.660000] [<c006bdd8>] (handle_irq_event_percpu+0x70/0x254) from [<c006bff8>] (handle_irq_event+0x3c/0x5c)
> [   79.660000] [<c006bff8>] (handle_irq_event+0x3c/0x5c) from [<c006e6d0>] (handle_level_irq+0x90/0x110)
> [   79.660000] [<c006e6d0>] (handle_level_irq+0x90/0x110) from [<c006b930>] (generic_handle_irq+0x38/0x50)
> [   79.660000] [<c006b930>] (generic_handle_irq+0x38/0x50) from [<c00102fc>] (handle_IRQ+0x30/0x84)
> [   79.660000] [<c00102fc>] (handle_IRQ+0x30/0x84) from [<c000f058>] (__irq_svc+0x38/0x60)
> [   79.660000] [<c000f058>] (__irq_svc+0x38/0x60) from [<c0010520>] (default_idle+0x2c/0x40)
> [   79.660000] [<c0010520>] (default_idle+0x2c/0x40) from [<c0010a90>] (cpu_idle+0x64/0xcc)
> [   79.660000] [<c0010a90>] (cpu_idle+0x64/0xcc) from [<c04ff858>] (start_kernel+0x244/0x2c8)
> [   79.660000] BUG: spinlock lockup on CPU#0, swapper/0
> [   79.660000]  lock: c398cb2c, .magic: dead4ead, .owner: swapper/0, .owner_cpu: 0
> [   79.660000] [<c0014bd0>] (unwind_backtrace+0x0/0xf4) from [<c01ddb1c>] (do_raw_spin_lock+0xf0/0x144)
> [   79.660000] [<c01ddb1c>] (do_raw_spin_lock+0xf0/0x144) from [<c03a8468>] (_raw_spin_lock_irqsave+0x4c/0x58)
> [   79.660000] [<c03a8468>] (_raw_spin_lock_irqsave+0x4c/0x58) from [<c026ea3c>] (mxs_mmc_enable_sdio_irq+0x18/0xd4)
> [   79.660000] [<c026ea3c>] (mxs_mmc_enable_sdio_irq+0x18/0xd4) from [<c026f7fc>] (mxs_mmc_irq_handler+0xd4/0xe8)
> [   79.660000] [<c026f7fc>] (mxs_mmc_irq_handler+0xd4/0xe8) from [<c006bdd8>] (handle_irq_event_percpu+0x70/0x254)
> [   79.660000] [<c006bdd8>] (handle_irq_event_percpu+0x70/0x254) from [<c006bff8>] (handle_irq_event+0x3c/0x5c)
> [   79.660000] [<c006bff8>] (handle_irq_event+0x3c/0x5c) from [<c006e6d0>] (handle_level_irq+0x90/0x110)
> [   79.660000] [<c006e6d0>] (handle_level_irq+0x90/0x110) from [<c006b930>] (generic_handle_irq+0x38/0x50)
> [   79.660000] [<c006b930>] (generic_handle_irq+0x38/0x50) from [<c00102fc>] (handle_IRQ+0x30/0x84)
> [   79.660000] [<c00102fc>] (handle_IRQ+0x30/0x84) from [<c000f058>] (__irq_svc+0x38/0x60)
> [   79.660000] [<c000f058>] (__irq_svc+0x38/0x60) from [<c0010520>] (default_idle+0x2c/0x40)
> [   79.660000] [<c0010520>] (default_idle+0x2c/0x40) from [<c0010a90>] (cpu_idle+0x64/0xcc)
> [   79.660000] [<c0010a90>] (cpu_idle+0x64/0xcc) from [<c04ff858>] (start_kernel+0x244/0x2c8)
>
> Signed-off-by: Lauri Hintsala <lauri.hintsala at bluegiga.com>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/mmc/host/mxs-mmc.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> index 277161d..20a0550 100644
> --- a/drivers/mmc/host/mxs-mmc.c
> +++ b/drivers/mmc/host/mxs-mmc.c
> @@ -278,11 +278,11 @@ static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
>  	writel(stat & MXS_MMC_IRQ_BITS,
>  	       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
>  
> +	spin_unlock(&host->lock);
> +
>  	if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
>  		mmc_signal_sdio_irq(host->mmc);
>  
> -	spin_unlock(&host->lock);
> -
>  	if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
>  		cmd->error = -ETIMEDOUT;
>  	else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)

Thanks, pushed to mmc-next for 3.6 with a stable@ tag.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From cjb at laptop.org  Fri Aug 31 06:12:13 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 31 Aug 2012 06:12:13 -0400
Subject: [PATCH 2/2] mmc: mxs-mmc: fix deadlock caused by recursion loop
In-Reply-To: <1342534570-8293-3-git-send-email-lauri.hintsala@bluegiga.com>
 (Lauri Hintsala's message of "Tue, 17 Jul 2012 17:16:10 +0300")
References: <1342534570-8293-1-git-send-email-lauri.hintsala@bluegiga.com>
 <1342534570-8293-3-git-send-email-lauri.hintsala@bluegiga.com>
Message-ID: <87txvjnzeq.fsf@octavius.laptop.org>

Hi,

On Tue, Jul 17 2012, Lauri Hintsala wrote:
> Release the lock before mmc_signal_sdio_irq is called by
> mxs_mmc_enable_sdio_irq.
>
> Backtrace:
> [   65.470000] =============================================
> [   65.470000] [ INFO: possible recursive locking detected ]
> [   65.470000] 3.5.0-rc5 #2 Not tainted
> [   65.470000] ---------------------------------------------
> [   65.470000] ksdioirqd/mmc0/73 is trying to acquire lock:
> [   65.470000]  (&(&host->lock)->rlock#2){-.-...}, at: [<bf054120>] mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc]
> [   65.470000]
> [   65.470000] but task is already holding lock:
> [   65.470000]  (&(&host->lock)->rlock#2){-.-...}, at: [<bf054120>] mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc]
> [   65.470000]
> [   65.470000] other info that might help us debug this:
> [   65.470000]  Possible unsafe locking scenario:
> [   65.470000]
> [   65.470000]        CPU0
> [   65.470000]        ----
> [   65.470000]   lock(&(&host->lock)->rlock#2);
> [   65.470000]   lock(&(&host->lock)->rlock#2);
> [   65.470000]
> [   65.470000]  *** DEADLOCK ***
> [   65.470000]
> [   65.470000]  May be due to missing lock nesting notation
> [   65.470000]
> [   65.470000] 1 lock held by ksdioirqd/mmc0/73:
> [   65.470000]  #0:  (&(&host->lock)->rlock#2){-.-...}, at: [<bf054120>] mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc]
> [   65.470000]
> [   65.470000] stack backtrace:
> [   65.470000] [<c0014990>] (unwind_backtrace+0x0/0xf4) from [<c005ccb8>] (__lock_acquire+0x14f8/0x1b98)
> [   65.470000] [<c005ccb8>] (__lock_acquire+0x14f8/0x1b98) from [<c005d3f8>] (lock_acquire+0xa0/0x108)
> [   65.470000] [<c005d3f8>] (lock_acquire+0xa0/0x108) from [<c02f671c>] (_raw_spin_lock_irqsave+0x48/0x5c)
> [   65.470000] [<c02f671c>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<bf054120>] (mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc])
> [   65.470000] [<bf054120>] (mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc]) from [<bf0541d0>] (mxs_mmc_enable_sdio_irq+0xc8/0xdc [mxs_mmc])
> [   65.470000] [<bf0541d0>] (mxs_mmc_enable_sdio_irq+0xc8/0xdc [mxs_mmc]) from [<c0219b38>] (sdio_irq_thread+0x1bc/0x274)
> [   65.470000] [<c0219b38>] (sdio_irq_thread+0x1bc/0x274) from [<c003c324>] (kthread+0x8c/0x98)
> [   65.470000] [<c003c324>] (kthread+0x8c/0x98) from [<c00101ac>] (kernel_thread_exit+0x0/0x8)
> [   65.470000] BUG: spinlock lockup suspected on CPU#0, ksdioirqd/mmc0/73
> [   65.470000]  lock: 0xc3358724, .magic: dead4ead, .owner: ksdioirqd/mmc0/73, .owner_cpu: 0
> [   65.470000] [<c0014990>] (unwind_backtrace+0x0/0xf4) from [<c01b46b0>] (do_raw_spin_lock+0x100/0x144)
> [   65.470000] [<c01b46b0>] (do_raw_spin_lock+0x100/0x144) from [<c02f6724>] (_raw_spin_lock_irqsave+0x50/0x5c)
> [   65.470000] [<c02f6724>] (_raw_spin_lock_irqsave+0x50/0x5c) from [<bf054120>] (mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc])
> [   65.470000] [<bf054120>] (mxs_mmc_enable_sdio_irq+0x18/0xdc [mxs_mmc]) from [<bf0541d0>] (mxs_mmc_enable_sdio_irq+0xc8/0xdc [mxs_mmc])
> [   65.470000] [<bf0541d0>] (mxs_mmc_enable_sdio_irq+0xc8/0xdc [mxs_mmc]) from [<c0219b38>] (sdio_irq_thread+0x1bc/0x274)
> [   65.470000] [<c0219b38>] (sdio_irq_thread+0x1bc/0x274) from [<c003c324>] (kthread+0x8c/0x98)
> [   65.470000] [<c003c324>] (kthread+0x8c/0x98) from [<c00101ac>] (kernel_thread_exit+0x0/0x8)
>
> Reported-by: Attila Kinali <attila at kinali.ch>
> Signed-off-by: Lauri Hintsala <lauri.hintsala at bluegiga.com>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/mmc/host/mxs-mmc.c |   10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> index 20a0550..e1fd2c8 100644
> --- a/drivers/mmc/host/mxs-mmc.c
> +++ b/drivers/mmc/host/mxs-mmc.c
> @@ -637,11 +637,6 @@ static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
>  		writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
>  		       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
> -
> -		if (readl(host->base + HW_SSP_STATUS(host)) &
> -				BM_SSP_STATUS_SDIO_IRQ)
> -			mmc_signal_sdio_irq(host->mmc);
> -
>  	} else {
>  		writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
>  		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> @@ -650,6 +645,11 @@ static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  	}
>  
>  	spin_unlock_irqrestore(&host->lock, flags);
> +
> +	if (enable && readl(host->base + HW_SSP_STATUS(host)) &
> +			BM_SSP_STATUS_SDIO_IRQ)
> +		mmc_signal_sdio_irq(host->mmc);
> +
>  }
>  
>  static const struct mmc_host_ops mxs_mmc_ops = {

Thanks, pushed to mmc-next for 3.6 with a stable@ tag.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From sourav.poddar at ti.com  Fri Aug 31 06:21:20 2012
From: sourav.poddar at ti.com (Poddar, Sourav)
Date: Fri, 31 Aug 2012 15:51:20 +0530
Subject: [PATCHv3 0/4] Add device tree data for omap5
In-Reply-To: <504084B9.3000701@ti.com>
References: <1344961473-13675-1-git-send-email-sourav.poddar@ti.com>
 <CAKdam57L8txFtE9ahy3u3vLW0XRP5z4QaNQKVFj9KaEFZE1qvg@mail.gmail.com>
 <503229F5.4030405@ti.com>
 <CAKdam543ATO96rbhgCWKtGUGRQ_+=KSyAk-nGBknjC+BvJSmOw@mail.gmail.com>
 <504084B9.3000701@ti.com>
Message-ID: <CAKdam573NqiCd2=CQ2kg1g+VqjS6z8g=QbPfMZZbm8P98yDP_A@mail.gmail.com>

Hi Benoit,

On Fri, Aug 31, 2012 at 3:02 PM, Benoit Cousson <b-cousson at ti.com> wrote:
> Hi Sourav,
>
> While rebasing your series on top of Tony's lo/devel-dt, I realized that the keypad nodes are not located at the correct place :-(
>
> At the moment they are just floating at the top level of the dts while they belong to the ocp bus and thus should be put there.
>
My bad, never realised always used it at the top level. Sorry for the
inconvenience.
> I fixed that since it was trivial and cleaned as well the changelog and the comments to aligned then properly. I added as well the physical address to the node name and a label for easy reference at board level.
>
Thanks for fixing it up.
> I did some basic test on my OMAP4 sdp, but that all I can do so far.
>
> Could you just check if this is still fine for OMAP5 before I ask Tony to pull that.
>
I just booted the below mentioned branch and its booting fine on omap5. Did
some keypad functionality test also and keypad seems to be working
fine on omap5.
> I based that on top of Tony's DT patches due to conflict with the existing MMC patch in it.
>
>
>
> The following changes since commit 85d7ff9b907685b6469058888f1d961b3e8d47ad:
>   Olof Johansson (1):
>         ARM: omap: add dtb targets
>
> are available in the git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.7/dts
>
> Sourav Poddar (6):
>       arm/dts: omap5-evm: Add I2C support
>       arm/dts: omap5-evm: Add tmp102 sensor support
>       arm/dts: omap5-evm: Add keypad data
>       arm/dts: omap5-evm: Add bmp085 sensor support
>       arm/dts: omap4-sdp: Add keypad data
>       Documentation: dt: i2c: trivial-devices: Update for tmp102
>
>  .../devicetree/bindings/i2c/trivial-devices.txt    |    1 +
>  arch/arm/boot/dts/omap4-sdp.dts                    |   70 ++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi                       |    5 ++
>  arch/arm/boot/dts/omap5-evm.dts                    |   33 +++++++++
>  arch/arm/boot/dts/omap5.dtsi                       |   40 +++++++++++
>  5 files changed, 149 insertions(+), 0 deletions(-)
>
> Regards,
> Benoit
>

Thanks,
Sourav


From matthieu.castet at parrot.com  Fri Aug 31 06:29:04 2012
From: matthieu.castet at parrot.com (Matthieu CASTET)
Date: Fri, 31 Aug 2012 12:29:04 +0200
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <20120831110444.25d9b9fe@pyramind.ukuu.org.uk>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
 <20120831110444.25d9b9fe@pyramind.ukuu.org.uk>
Message-ID: <504091F0.1090703@parrot.com>

Alan Cox a ?crit :
> On Fri, 31 Aug 2012 11:21:56 +0200
> Matthieu CASTET <castet.matthieu at free.fr> wrote:
> 
>> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
>> ---
>>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
> 
> This is a step in the wrong direction. This should all be runtime handled
> 
> NAK.
> 

AFAIK you can't build a arm kernel that support arm6/armv7 and armv5.
And I am not sure it will be possible one day.




From linux at arm.linux.org.uk  Fri Aug 31 06:33:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 31 Aug 2012 11:33:51 +0100
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <504091F0.1090703@parrot.com>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
 <20120831110444.25d9b9fe@pyramind.ukuu.org.uk> <504091F0.1090703@parrot.com>
Message-ID: <20120831103351.GE18957@n2100.arm.linux.org.uk>

On Fri, Aug 31, 2012 at 12:29:04PM +0200, Matthieu CASTET wrote:
> Alan Cox a ?crit :
> > On Fri, 31 Aug 2012 11:21:56 +0200
> > Matthieu CASTET <castet.matthieu at free.fr> wrote:
> > 
> >> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
> >> ---
> >>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
> >>  1 file changed, 34 insertions(+)
> > 
> > This is a step in the wrong direction. This should all be runtime handled
> > 
> > NAK.
> > 
> 
> AFAIK you can't build a arm kernel that support arm6/armv7 and armv5.
> And I am not sure it will be possible one day.

There are no plans to ever make it possible; there are too many significant
differences between ARMv4, v5 architectures and ARMv6,v7 architectures
to warrant making this runtime selectable.


From shawn.guo at linaro.org  Thu Aug 30 17:34:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 05:34:19 +0800
Subject: [PATCH] ARM: dts: mxs: Add the second I2C adapter to the
 CFA10049 expansion board
In-Reply-To: <1346169744-24674-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1346169744-24674-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <20120830213417.GB3613@r65073-Latitude-D630>

On Tue, Aug 28, 2012 at 06:02:24PM +0200, Maxime Ripard wrote:
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
> ---
>  arch/arm/boot/dts/imx28-cfa10049.dts |   31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx28-cfa10049.dts

Please add the dtb target into arch/arm/mach-mxs/Makefile.boot.

Regards,
Shawn

> 
> diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
> new file mode 100644
> index 0000000..e0e4b8c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-cfa10049.dts
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright 2012 Free Electrons
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/*
> + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
> + * need to include the CFA-10036 DTS.
> + */
> +/include/ "imx28-cfa10036.dts"
> +
> +/ {
> +	model = "Crystalfontz CFA-10049 Board";
> +	compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
> +
> +	apb at 80000000 {
> +		apbx at 80040000 {
> +			i2c1: i2c at 8005a000 {
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&i2c1_pins_a>;
> +				status = "okay";
> +			};
> +		};
> +	};
> +};
> -- 
> 1.7.9.5
> 


From lee.jones at linaro.org  Fri Aug 31 06:36:36 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 11:36:36 +0100
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the Nomadik
 I2C driver
In-Reply-To: <CACRpkdapY3JvZmLxK7dX917O-E+aDgVE9ELnysjqAyETXMZHNw@mail.gmail.com>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
 <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdapY3JvZmLxK7dX917O-E+aDgVE9ELnysjqAyETXMZHNw@mail.gmail.com>
Message-ID: <20120831103633.GA5569@gmail.com>

On Mon, Aug 27, 2012 at 04:42:49PM -0700, Linus Walleij wrote:
> On Thu, Aug 23, 2012 at 8:01 AM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > Here we apply the bindings required for successful Device Tree
> > probing of the i2c-nomadik driver.
> >
> > Cc: linux-i2c at vger.kernel.org
> > Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

I'm assuming I still need Wolfram's Ack on this?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From Barry.Song at csr.com  Fri Aug 31 06:35:12 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 31 Aug 2012 18:35:12 +0800
Subject: [RFC/PATCH] ARM: PRIMA2: initial support for SiRFmarco dual-core SoC
Message-ID: <1346409312-16778-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

SiRFmarco is a dual-core cortex-A9 SoC. This patch adds initial support for it.
It is only a RFC for early review from community. I'd like to split it into
multiple patches later.
change list:
1. Marco has different OS timer hardware with Prima2, so add a new timer-marco
2. add platsmp.c, headsmp.S and hotplug.c for MPcore support
3. some hardwares have changed, like rstc, so use of_compatible to branch Prima2 and Marco
4. add initial .dtsi for Marco SoC and initial .dts for the EVB
5. some hardware support both Prima2 and Marco, add marco stuff to of_match tables
6. use GIC for Marco instead of Prima2's IRQ controller
7. add DEBUG_LL uart ports for Prima2 and Marco debug ports

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 arch/arm/Kconfig                                 |    3 +-
 arch/arm/Kconfig.debug                           |   14 +
 arch/arm/Makefile                                |    2 +-
 arch/arm/boot/dts/marco-evb.dts                  |   20 +
 arch/arm/boot/dts/marco.dtsi                     |  497 ++++++++++++++++++++++
 arch/arm/configs/marcocb_defconfig               |   86 ++++
 arch/arm/mach-prima2/Kconfig                     |   14 +
 arch/arm/mach-prima2/Makefile                    |    5 +-
 arch/arm/mach-prima2/common.c                    |   44 ++-
 arch/arm/mach-prima2/common.h                    |    6 +-
 arch/arm/mach-prima2/headsmp.S                   |   79 ++++
 arch/arm/mach-prima2/hotplug.c                   |   57 +++
 arch/arm/mach-prima2/include/mach/uart.h         |    4 +
 arch/arm/mach-prima2/l2x0.c                      |   19 +-
 arch/arm/mach-prima2/platsmp.c                   |  154 +++++++
 arch/arm/mach-prima2/pm.c                        |    1 +
 arch/arm/mach-prima2/rstc.c                      |   47 ++-
 arch/arm/mach-prima2/rtciobrg.c                  |    1 +
 arch/arm/mach-prima2/timer-marco.c               |  295 +++++++++++++
 arch/arm/mach-prima2/{timer.c => timer-prima2.c} |    4 +-
 drivers/pinctrl/Kconfig                          |    2 +-
 21 files changed, 1326 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/boot/dts/marco-evb.dts
 create mode 100644 arch/arm/boot/dts/marco.dtsi
 create mode 100644 arch/arm/configs/marcocb_defconfig
 create mode 100644 arch/arm/mach-prima2/headsmp.S
 create mode 100644 arch/arm/mach-prima2/hotplug.c
 create mode 100644 arch/arm/mach-prima2/platsmp.c
 create mode 100644 arch/arm/mach-prima2/timer-marco.c
 rename arch/arm/mach-prima2/{timer.c => timer-prima2.c} (98%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 00ef0e0..8f2fe64 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -418,8 +418,9 @@ config ARCH_SIRF
 	select PINCTRL
 	select PINCTRL_SIRF
 	select USE_OF
+	select AUTO_ZRELADDR
 	help
-	  Support for CSR SiRFprimaII/Marco/Polo platforms
+	 Support for CSR SiRFprimaII/Marco/Polo platforms
 
 config ARCH_EBSA110
 	bool "EBSA-110"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f15f82b..2e63c78 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,20 @@ choice
 		  The uncompressor code port configuration is now handled
 		  by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+	config DEBUG_SIRFPRIMA2_UART1
+		bool "Kernel low-level debugging messages via SiRFprimaII UART1"
+		depends on ARCH_PRIMA2
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the uart1 port on SiRFprimaII devices.
+
+	config DEBUG_SIRFMARCO_UART1
+		bool "Kernel low-level debugging messages via SiRFmarco UART1"
+		depends on ARCH_MARCO
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the uart1 port on SiRFmarco devices.
+
 	config DEBUG_VEXPRESS_UART0_DETECT
 		bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
 		depends on ARCH_VEXPRESS && CPU_CP15_MMU
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..6fbec07 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -168,7 +168,6 @@ machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
 machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
 machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
-machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
 machine-$(CONFIG_ARCH_RPC)		:= rpc
@@ -182,6 +181,7 @@ machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
+machine-$(CONFIG_ARCH_SIRF)		:= prima2
 machine-$(CONFIG_ARCH_TEGRA)		:= tegra
 machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)		:= ux500
diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts
new file mode 100644
index 0000000..8b2dc61
--- /dev/null
+++ b/arch/arm/boot/dts/marco-evb.dts
@@ -0,0 +1,20 @@
+/*
+ * DTS file for CSR SiRFmarco Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "marco.dtsi"
+
+/ {
+	model = "CSR SiRFmarco Evaluation Board";
+	compatible = "sirf,marco", "sirf,marco-cb";
+
+	memory {
+		reg = <0x40000000 0x60000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
new file mode 100644
index 0000000..34aad72
--- /dev/null
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -0,0 +1,497 @@
+/*
+ * DTS file for CSR SiRFmarco SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+	compatible = "sirf,marco";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+		};
+	};
+
+	axi {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x40000000 0x40000000 0xa0000000>;
+
+		l2-cache-controller at c0030000 {
+			compatible = "arm,pl310-cache", "sirf,marco-pl310-cache";
+			reg = <0xc0030000 0x1000>;
+			interrupts = <0 59 0>;
+			arm,tag-latency = <1 1 1>;
+			arm,data-latency = <1 1 1>;
+			arm,filter-ranges = <0x40000000 0xc0000000>;
+		};
+
+                gic: interrupt-controller at c0011000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0xc0011000 0x1000>,
+                              <0xc0010100 0x0100>;
+                };
+
+		 rstc-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc2000000 0xc2000000 0x10000>;
+
+			reset-controller at c2000000 {
+				compatible = "sirf,marco-rstc";
+				reg = <0xc2000000 0x10000>;
+			};
+		};
+
+		sys-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc3000000 0xc3000000 0x30000>;
+
+			clock-controller at c3000000 {
+				compatible = "sirf,marco-clkc";
+				reg = <0xc3000000 0x1000>;
+				interrupts = <0 3 0>;
+			};
+
+			rsc-controller at c3010000 {
+				compatible = "sirf,marco-rsc";
+				reg = <0xc3010000 0x1000>;
+			};
+		};
+
+		mem-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc4000000 0xc4000000 0x10000>;
+
+			memory-controller at c4000000 {
+				compatible = "sirf,marco-memc";
+				reg = <0xc4000000 0x10000>;
+				interrupts = <0 27 0>;
+			};
+		};
+
+		disp-iobg0 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc5000000 0xc5000000 0x20000>;
+
+			display0 at c5000000 {
+				compatible = "sirf,marco-lcd";
+				reg = <0xc5000000 0x10000>;
+				interrupts = <0 30 0>;
+			};
+
+			vpp0 at c5010000 {
+				compatible = "sirf,marco-vpp";
+				reg = <0xc5010000 0x10000>;
+				interrupts = <0 31 0>;
+			};
+		};
+
+		disp-iobg1 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc6000000 0xc6000000 0x20000>;
+
+			display1 at c6000000 {
+				compatible = "sirf,marco-lcd";
+				reg = <0xc6000000 0x10000>;
+				interrupts = <0 62 0>;
+			};
+
+			vpp1 at c6010000 {
+				compatible = "sirf,marco-vpp";
+				reg = <0xc6010000 0x10000>;
+				interrupts = <0 63 0>;
+			};
+		};
+
+		graphics-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc8000000 0xc8000000 0x1000000>;
+
+			graphics at c8000000 {
+				compatible = "powervr,sgx540";
+				reg = <0xc8000000 0x1000000>;
+				interrupts = <0 6 0>;
+			};
+		};
+
+		multimedia-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc9000000 0xc9000000 0x1000000>;
+
+			multimedia at a0000000 {
+				compatible = "sirf,marco-video-codec";
+				reg = <0xc9000000 0x1000000>;
+				interrupts = <0 5 0>;
+			};
+		};
+
+		dsp-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xca000000 0xca000000 0x2000000>;
+
+			dspif at ca000000 {
+				compatible = "sirf,marco-dspif";
+				reg = <0xca000000 0x10000>;
+				interrupts = <0 9 0>;
+			};
+
+			gps at ca010000 {
+				compatible = "sirf,marco-gps";
+				reg = <0xca010000 0x10000>;
+				interrupts = <0 7 0>;
+			};
+
+			dsp at cb000000 {
+				compatible = "sirf,marco-dsp";
+				reg = <0xcb000000 0x1000000>;
+				interrupts = <0 8 0>;
+			};
+		};
+
+		peri-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xcc000000 0xcc000000 0x1b0000>;
+
+			timer at cc020000 {
+				compatible = "sirf,marco-tick";
+				reg = <0xcc020000 0x1000>;
+				interrupts = <0 0 0>;
+			};
+
+			nand at cc030000 {
+				compatible = "sirf,marco-nand";
+				reg = <0xcc030000 0x10000>;
+				interrupts = <0 41 0>;
+			};
+
+			audio at cc040000 {
+				compatible = "sirf,marco-audio";
+				reg = <0xcc040000 0x10000>;
+				interrupts = <0 35 0>;
+			};
+
+			uart0: uart at cc050000 {
+				cell-index = <0>;
+				compatible = "sirf,marco-uart";
+				reg = <0xcc050000 0x1000>;
+				interrupts = <0 17 0>;
+				fifosize = <128>;
+			};
+
+			uart1: uart at cc060000 {
+				cell-index = <1>;
+				compatible = "sirf,marco-uart";
+				reg = <0xcc060000 0x1000>;
+				interrupts = <0 18 0>;
+				fifosize = <32>;
+			};
+
+			uart2: uart at cc070000 {
+				cell-index = <2>;
+				compatible = "sirf,marco-uart";
+				reg = <0xcc070000 0x1000>;
+				interrupts = <0 19 0>;
+				fifosize = <128>;
+			};
+
+			uart3: uart at cc190000 {
+				cell-index = <3>;
+				compatible = "sirf,marco-uart";
+				reg = <0xcc190000 0x1000>;
+				interrupts = <0 66 0>;
+				fifosize = <128>;
+			};
+
+			uart4: uart at cc1a0000 {
+				cell-index = <4>;
+				compatible = "sirf,marco-uart";
+				reg = <0xcc1a0000 0x1000>;
+				interrupts = <0 69 0>;
+				fifosize = <128>;
+			};
+
+			usp0: usp at cc080000 {
+				cell-index = <0>;
+				compatible = "sirf,marco-usp";
+				reg = <0xcc080000 0x10000>;
+				interrupts = <0 20 0>;
+			};
+
+			usp1: usp at cc090000 {
+				cell-index = <1>;
+				compatible = "sirf,marco-usp";
+				reg = <0xcc090000 0x10000>;
+				interrupts = <0 21 0>;
+			};
+
+			usp2: usp at cc0a0000 {
+				cell-index = <2>;
+				compatible = "sirf,marco-usp";
+				reg = <0xcc0a0000 0x10000>;
+				interrupts = <0 22 0>;
+			};
+
+			dmac0: dma-controller at cc0b0000 {
+				cell-index = <0>;
+				compatible = "sirf,marco-dmac";
+				reg = <0xcc0b0000 0x10000>;
+				interrupts = <0 12 0>;
+			};
+
+			dmac1: dma-controller at cc160000 {
+				cell-index = <1>;
+				compatible = "sirf,marco-dmac";
+				reg = <0xcc160000 0x10000>;
+				interrupts = <0 13 0>;
+			};
+
+			vip at cc0c0000 {
+				compatible = "sirf,marco-vip";
+				reg = <0xcc0c0000 0x10000>;
+			};
+
+			spi0: spi at cc0D0000 {
+				cell-index = <0>;
+				compatible = "sirf,marco-spi";
+				reg = <0xcc0D0000 0x10000>;
+				interrupts = <0 15 0>;
+				sirf,spi-num-chipselects = <1>;
+				cs-gpios = <&gpio 0 0>;
+			};
+
+			spi1: spi at cc170000 {
+				cell-index = <1>;
+				compatible = "sirf,marco-spi";
+				reg = <0xcc170000 0x10000>;
+				interrupts = <0 16 0>;
+				sirf,spi-num-chipselects = <1>;
+				cs-gpios = <&gpio 0 0>;
+			};
+
+			i2c0: i2c at cc0e0000 {
+				cell-index = <0>;
+				compatible = "sirf,marco-i2c";
+				reg = <0xcc0e0000 0x10000>;
+				interrupts = <0 24 0>;
+			};
+
+			i2c1: i2c at cc0f0000 {
+				cell-index = <1>;
+				compatible = "sirf,marco-i2c";
+				reg = <0xcc0f0000 0x10000>;
+				interrupts = <0 25 0>;
+			};
+
+			tsc at cc110000 {
+				compatible = "sirf,marco-tsc";
+				reg = <0xcc110000 0x10000>;
+				interrupts = <0 33 0>;
+			};
+
+			gpio: gpio-controller at cc120000 {
+				#gpio-cells = <2>;
+				#interrupt-cells = <2>;
+				compatible = "sirf,marco-gpio-pinmux";
+				reg = <0xcc120000 0x10000>;
+				interrupts = <0 43 0>,
+					   <0 44 0>,
+					   <0 45 0>,
+					   <0 46 0>,
+					   <0 47 0>;
+				gpio-controller;
+				interrupt-controller;
+			};
+
+			pwm at cc130000 {
+				compatible = "sirf,marco-pwm";
+				reg = <0xcc130000 0x10000>;
+			};
+
+			efusesys at cc140000 {
+				compatible = "sirf,marco-efuse";
+				reg = <0xcc140000 0x10000>;
+			};
+
+			pulsec at cc150000 {
+				compatible = "sirf,marco-pulsec";
+				reg = <0xcc150000 0x10000>;
+				interrupts = <0 48 0>;
+			};
+
+			pci-iobg {
+				compatible = "sirf,marco-pciiobg", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0xcD000000 0xcD000000 0x1000000>;
+
+				sd0: sdhci at cD000000 {
+					cell-index = <0>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD000000 0x100000>;
+					interrupts = <0 38 0>;
+				};
+
+				sd1: sdhci at cD100000 {
+					cell-index = <1>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD100000 0x100000>;
+					interrupts = <0 38 0>;
+				};
+
+				sd2: sdhci at cD200000 {
+					cell-index = <2>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD200000 0x100000>;
+					interrupts = <0 23 0>;
+				};
+
+				sd3: sdhci at cD300000 {
+					cell-index = <3>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD300000 0x100000>;
+					interrupts = <0 23 0>;
+				};
+
+				sd4: sdhci at cD400000 {
+					cell-index = <4>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD400000 0x100000>;
+					interrupts = <0 39 0>;
+				};
+
+				sd5: sdhci at cD500000 {
+					cell-index = <5>;
+					compatible = "sirf,marco-sdhc";
+					reg = <0xcD500000 0x100000>;
+					interrupts = <0 39 0>;
+				};
+
+				pci-copy at cD900000 {
+					compatible = "sirf,marco-pcicp";
+					reg = <0xcD900000 0x100000>;
+					interrupts = <0 40 0>;
+				};
+
+				rom-interface at cDa00000 {
+					compatible = "sirf,marco-romif";
+					reg = <0xcDa00000 0x100000>;
+				};
+			};
+		};
+
+		rtc-iobg {
+			compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xc1000000 0x10000>;
+
+			gpsrtc at 1000 {
+				compatible = "sirf,marco-gpsrtc";
+				reg = <0x1000 0x1000>;
+				interrupts = <0 55 0>,
+					   <0 56 0>,
+					   <0 57 0>;
+			};
+
+			sysrtc at 2000 {
+				compatible = "sirf,marco-sysrtc";
+				reg = <0x2000 0x1000>;
+				interrupts = <0 52 0>,
+					   <0 53 0>,
+					   <0 54 0>;
+			};
+
+			pwrc at 3000 {
+				compatible = "sirf,marco-pwrc";
+				reg = <0x3000 0x1000>;
+				interrupts = <0 32 0>;
+			};
+		};
+
+		uus-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xce000000 0xce000000 0x40000>;
+
+			usb0: usb at ce000000 {
+				compatible = "chipidea,ci13611a-marco";
+				reg = <0xce000000 0x10000>;
+				interrupts = <0 10 0>;
+			};
+
+			usb1: usb at ce010000 {
+				compatible = "chipidea,ci13611a-marco";
+				reg = <0xce010000 0x10000>;
+				interrupts = <0 11 0>;
+			};
+
+			security at ce020000 {
+				compatible = "sirf,marco-security";
+				reg = <0xce020000 0x10000>;
+				interrupts = <0 42 0>;
+			};
+		};
+
+		can-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xD0000000 0xD0000000 0x20000>;
+
+			can0: can at D0000000 {
+				compatible = "sirf,marco-can";
+				reg = <0xD0000000 0x10000>;
+			};
+
+			can1: can at D0010000 {
+				compatible = "sirf,marco-can";
+				reg = <0xD0010000 0x10000>;
+			};
+		};
+
+		lvds-iobg {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xD1000000 0xD1000000 0x10000>;
+
+			lvds at D1000000 {
+				compatible = "sirf,marco-lvds";
+				reg = <0xD1000000 0x10000>;
+				interrupts = <0 64 0>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/configs/marcocb_defconfig b/arch/arm/configs/marcocb_defconfig
new file mode 100644
index 0000000..1a9829d
--- /dev/null
+++ b/arch/arm/configs/marcocb_defconfig
@@ -0,0 +1,86 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_ARCH_SIRF=y
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+# CONFIG_LOCAL_TIMERS is not set
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_KEXEC=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_DMADEVICES=y
+CONFIG_DMADEVICES_DEBUG=y
+CONFIG_DMADEVICES_VDEBUG=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 41fc853..1ad4dd3 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -11,9 +11,23 @@ config ARCH_PRIMA2
 	help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
+config ARCH_MARCO
+	bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
+	default y
+	select CPU_V7
+	select HAVE_SMP
+	select SMP_ON_UP
+	select ARM_GIC
+	select SIRFMARCO_FPGA
+	help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
 endmenu
 
 config SIRF_IRQ
 	bool
 
+config SIRFMARCO_FPGA
+	bool "CSR SiRFmarco FPGA with 26Mhz io clock"
+
 endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index fc9ce22..bfe360c 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,4 +1,3 @@
-obj-y := timer.o
 obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
@@ -6,3 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SIRF_IRQ) += irq.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
+obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
+obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index f25a541..3ee1457 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -8,9 +8,11 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include "common.h"
@@ -32,15 +34,15 @@ void __init sirfsoc_init_late(void)
 
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
-       "sirf,prima2",
-       NULL
+	"sirf,prima2",
+	NULL
 };
 
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <baohua.song at csr.com> */
 	.map_io         = sirfsoc_map_lluart,
 	.init_irq	= sirfsoc_of_irq_init,
-	.timer		= &sirfsoc_timer,
+	.timer		= &sirfsoc_prima2_timer,
 	.dma_zone_size	= SZ_256M,
 	.init_machine	= sirfsoc_mach_init,
 	.init_late	= sirfsoc_init_late,
@@ -48,3 +50,39 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	.restart	= sirfsoc_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_ARCH_MARCO
+static __init void sirfsoc_map_io(void)
+{
+	sirfsoc_map_lluart();
+	sirfsoc_map_scu();
+}
+
+static const struct of_device_id marco_irq_match[] __initconst = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ /* sentinel */ }
+};
+
+static void __init marco_init_irq(void)
+{
+	of_irq_init(marco_irq_match);
+}
+
+static const char *marco_dt_match[] __initdata = {
+	"sirf,marco",
+	NULL
+};
+
+DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
+	/* Maintainer: Barry Song <baohua.song at csr.com> */
+	.map_io         = sirfsoc_map_io,
+	.init_irq	= marco_init_irq,
+	.handle_irq     = gic_handle_irq,
+	.timer		= &sirfsoc_marco_timer,
+	.init_machine	= sirfsoc_mach_init,
+	.init_late	= sirfsoc_init_late,
+	.dt_compat      = marco_dt_match,
+	.restart	= sirfsoc_restart,
+MACHINE_END
+#endif
+
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 60d826f..2e82e41 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -12,11 +12,13 @@
 #include <linux/init.h>
 #include <asm/mach/time.h>
 
-extern struct sys_timer sirfsoc_timer;
+extern struct sys_timer sirfsoc_prima2_timer;
+extern struct sys_timer sirfsoc_marco_timer;
 
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
 extern void sirfsoc_restart(char, const char *);
+extern void sirfsoc_secondary_startup(void);
 
 #ifndef CONFIG_DEBUG_LL
 static inline void sirfsoc_map_lluart(void)  {}
@@ -24,6 +26,8 @@ static inline void sirfsoc_map_lluart(void)  {}
 extern void __init sirfsoc_map_lluart(void);
 #endif
 
+extern void sirfsoc_map_scu(void);
+
 #ifdef CONFIG_SUSPEND
 extern int sirfsoc_pm_init(void);
 #else
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
new file mode 100644
index 0000000..6ec19d5
--- /dev/null
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -0,0 +1,79 @@
+/*
+ * Entry of the second core for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+/*
+ * Cold boot and hardware reset show different behaviour,
+ * system will be always panic if we warm-reset the board
+ * Here we invalidate L1 of CPU1 to make sure there isn't
+ * uninitialized data written into memory later
+ */
+ENTRY(v7_invalidate_l1)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache
+	mcr	p15, 2, r0, c0, c0, 0
+	mrc	p15, 1, r0, c0, c0, 0
+
+	ldr	r1, =0x7fff
+	and	r2, r1, r0, lsr #13
+
+	ldr	r1, =0x3ff
+
+	and	r3, r1, r0, lsr #3	@ NumWays - 1
+	add	r2, r2, #1		@ NumSets
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4	@ SetShift
+
+	clz	r1, r3		@ WayShift
+	add	r4, r3, #1	@ NumWays
+1:	sub	r2, r2, #1	@ NumSets--
+	mov	r3, r4		@ Temp = NumWays
+2:	subs	r3, r3, #1	@ Temp--
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+	mcr	p15, 0, r5, c7, c6, 2
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7_invalidate_l1)
+
+/*
+ * SIRFSOC specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sirfsoc_secondary_startup)
+	bl v7_invalidate_l1
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+ENDPROC(sirfsoc_secondary_startup)
+
+        .align
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
new file mode 100644
index 0000000..7d5febe
--- /dev/null
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -0,0 +1,57 @@
+/*
+ * CPU hotplug support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+extern volatile int pen_release;
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+	flush_cache_all();
+
+	/* we put the platform to just WFI */
+	for (;;) {
+		__asm__ __volatile__("dsb\n\t" "wfi\n\t"
+			: : : "memory");
+		if (pen_release == cpu_logical_map(cpu)) {
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		}
+	}
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+	platform_do_lowpower(cpu);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
index c98b4d5..e5953d2 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -10,7 +10,11 @@
 #define __MACH_PRIMA2_SIRFSOC_UART_H
 
 /* UART-1: used as serial debug port */
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
 #define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#endif
 #define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
 #define SIRFSOC_UART1_SIZE		SZ_4K
 
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index c998377..35a2973 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -11,21 +11,38 @@
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 
+/*
+ * fixme: make aux_val and aux_mask the private data
+ * of of_device_id after we get right aux_val/mask
+ */
 static struct of_device_id prima2_l2x0_ids[]  = {
 	{ .compatible = "sirf,prima2-pl310-cache" },
 	{},
 };
 
+static struct of_device_id marco_l2x0_ids[]  = {
+	{ .compatible = "sirf,marco-pl310-cache" },
+	{},
+};
+
 static int __init sirfsoc_l2x0_init(void)
 {
 	struct device_node *np;
-
 	np = of_find_matching_node(NULL, prima2_l2x0_ids);
 	if (np) {
 		pr_info("Initializing prima2 L2 cache\n");
 		return l2x0_of_init(0x40000, 0);
 	}
 
+	np = of_find_matching_node(NULL, marco_l2x0_ids);
+	if (np) {
+		pr_info("Initializing marco L2 cache\n");
+		/*
+		 * fixme: set the right aux_val and aux_mask
+		 * return l2x0_of_init(0x10000, 0);
+		 */
+	}
+
 	return 0;
 }
 early_initcall(sirfsoc_l2x0_init);
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
new file mode 100644
index 0000000..e990a79
--- /dev/null
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -0,0 +1,154 @@
+/*
+ * plat smp support for CSR Marco dual-core SMP SoCs
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/delay.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include "common.h"
+
+static void __iomem *scu_base;
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen".
+ */
+volatile int pen_release = -1;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static struct map_desc scu_io_desc __initdata = {
+	.length		= SZ_4K,
+	.type		= MT_DEVICE,
+};
+
+void __init sirfsoc_map_scu(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	scu_io_desc.virtual = SIRFSOC_VA(base);
+	scu_io_desc.pfn = __phys_to_pfn(base);
+	iotable_init(&scu_io_desc, 1);
+
+	scu_base = (void __iomem *)SIRFSOC_VA(base);
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_secondary_init(0);
+
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	pen_release = -1;
+	smp_wmb();
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+	static void __iomem *sram_base;
+
+	/* for the moment in FPGA we use DSP SRAM */
+#define SIRFSOC_DSP_SRAM_BASE 0xCA008000UL
+	sram_base = ioremap_nocache(SIRFSOC_DSP_SRAM_BASE, SZ_4K);
+
+	/*
+	 * write the address of secondary startup into the sram register
+	 * at offset 0x34, then write the magic number 0x12345678 to the
+	 * sram register at offset 0x30, which is what boot rom code is
+	 * waiting for. This would wake up the secondary core from WFI
+	 */
+#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x34
+	__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
+		sram_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
+
+#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x30
+	__raw_writel(0x12345678,
+		sram_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
+
+	/* make sure write buffer is drained */
+	mb();
+
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	pen_release = cpu_logical_map(cpu);
+	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+
+	/*
+	 * Send the secondary CPU a soft interrupt ID15, thereby causing
+	 * the boot monitor to read the JUMPADDR and WAKEMAGIC, and branch
+	 * to the address found there.
+	 */
+	gic_raise_softirq(cpumask_of(cpu), 15);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -ENOSYS : 0;
+}
+
+void __init smp_init_cpus(void)
+{
+	int i, ncores;
+
+	ncores = scu_get_core_count(scu_base);
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+	scu_enable(scu_base);
+}
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index fb5a791..a16dec7 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -93,6 +93,7 @@ int __init sirfsoc_pm_init(void)
 
 static const struct of_device_id pwrc_ids[] = {
 	{ .compatible = "sirf,prima2-pwrc" },
+	{ .compatible = "sirf,marco-pwrc" },
 	{}
 };
 
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 762adb7..b8b002a 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
 
 static struct of_device_id rstc_ids[]  = {
 	{ .compatible = "sirf,prima2-rstc" },
+	{ .compatible = "sirf,marco-rstc" },
 	{},
 };
 
@@ -42,27 +43,39 @@ early_initcall(sirfsoc_of_rstc_init);
 
 int sirfsoc_reset_device(struct device *dev)
 {
-	const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
-	unsigned int reset_bit;
+	u32 reset_bit;
 
-	if (!prop)
-		return -ENODEV;
-
-	reset_bit = be32_to_cpup(prop);
+	if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+		return -EINVAL;
 
 	mutex_lock(&rstc_lock);
 
-	/*
-	 * Writing 1 to this bit resets corresponding block. Writing 0 to this
-	 * bit de-asserts reset signal of the corresponding block.
-	 * datasheet doesn't require explicit delay between the set and clear
-	 * of reset bit. it could be shorter if tests pass.
-	 */
-	writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
-		sirfsoc_rstc_base + (reset_bit / 32) * 4);
-	msleep(10);
-	writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
-		sirfsoc_rstc_base + (reset_bit / 32) * 4);
+	if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
+		/*
+		 * Writing 1 to this bit resets corresponding block. Writing 0 to this
+		 * bit de-asserts reset signal of the corresponding block.
+		 * datasheet doesn't require explicit delay between the set and clear
+		 * of reset bit. it could be shorter if tests pass.
+		 */
+		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+			sirfsoc_rstc_base + (reset_bit / 32) * 4);
+		msleep(10);
+		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+			sirfsoc_rstc_base + (reset_bit / 32) * 4);
+	} else {
+		/*
+		 * For MARCO and POLO
+		 * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
+		 * register de-asserts reset signal of the corresponding block.
+		 * datasheet doesn't require explicit delay between the set and clear
+		 * of reset bit. it could be shorter if tests pass.
+		 */
+		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 8) | reset_bit,
+			sirfsoc_rstc_base + (reset_bit / 32) * 8);
+		msleep(10);
+		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 8) | reset_bit,
+			sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+	}
 
 	mutex_unlock(&rstc_lock);
 
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
index 9d80f1e..fc6c4ab 100644
--- a/arch/arm/mach-prima2/rtciobrg.c
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -104,6 +104,7 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
 
 static const struct of_device_id rtciobrg_ids[] = {
 	{ .compatible = "sirf,prima2-rtciobg" },
+	{ .compatible = "sirf,marco-rtciobg" },
 	{}
 };
 
diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
new file mode 100644
index 0000000..eb5adad
--- /dev/null
+++ b/arch/arm/mach-prima2/timer-marco.c
@@ -0,0 +1,295 @@
+/*
+ * System timer for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <mach/map.h>
+#include <asm/sched_clock.h>
+#include <asm/mach/time.h>
+
+#include "common.h"
+
+#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
+#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
+#define SIRFSOC_TIMER_32COUNTER_2_CTRL			0x0008
+#define SIRFSOC_TIMER_32COUNTER_3_CTRL			0x000c
+#define SIRFSOC_TIMER_32COUNTER_4_CTRL			0x0010
+#define SIRFSOC_TIMER_32COUNTER_5_CTRL			0x0014
+#define SIRFSOC_TIMER_MATCH_0				0x0018
+#define SIRFSOC_TIMER_MATCH_1				0x001c
+#define SIRFSOC_TIMER_MATCH_2				0x0020
+#define SIRFSOC_TIMER_MATCH_3				0x0024
+#define SIRFSOC_TIMER_MATCH_4				0x0028
+#define SIRFSOC_TIMER_MATCH_5				0x002c
+#define SIRFSOC_TIMER_32COUNTER_0_MATCH_NUM		0x0030
+#define SIRFSOC_TIMER_32COUNTER_1_MATCH_NUM		0x0034
+#define SIRFSOC_TIMER_32COUNTER_2_MATCH_NUM		0x0038
+#define SIRFSOC_TIMER_32COUNTER_3_MATCH_NUM		0x003c
+#define SIRFSOC_TIMER_32COUNTER_4_MATCH_NUM		0x0040
+#define SIRFSOC_TIMER_32COUNTER_5_MATCH_NUM		0x0044
+#define SIRFSOC_TIMER_COUNTER_0				0x0048
+#define SIRFSOC_TIMER_COUNTER_1				0x004c
+#define SIRFSOC_TIMER_COUNTER_2				0x0050
+#define SIRFSOC_TIMER_COUNTER_3				0x0054
+#define SIRFSOC_TIMER_COUNTER_4				0x0058
+#define SIRFSOC_TIMER_COUNTER_5				0x005c
+#define SIRFSOC_TIMER_INTR_STATUS			0x0060
+#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
+#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
+#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
+#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
+#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
+#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080
+
+#define SIRFSOC_TIMER_REG_CNT 5
+
+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
+	SIRFSOC_TIMER_WATCHDOG_EN,
+	SIRFSOC_TIMER_32COUNTER_0_CTRL,
+	SIRFSOC_TIMER_64COUNTER_CTRL,
+	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
+	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
+};
+
+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
+
+static void __iomem *sirfsoc_timer_base;
+static void __init sirfsoc_of_timer_map(void);
+
+/* timer0 interrupt handler */
+static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *ce = dev_id;
+	u32 val;
+
+	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS) & BIT(0)));
+
+	/* Stop the timer tick */
+	val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+	val &= ~(BIT(0) | BIT(1) | BIT(2));
+	writel_relaxed(val, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+
+	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+
+	/* clear timer0 interrupt */
+	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+
+	ce->event_handler(ce);
+
+	return IRQ_HANDLED;
+}
+
+/* read 64-bit timer counter */
+static cycle_t sirfsoc_timer_read(struct clocksource *cs)
+{
+	u64 cycles;
+
+	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+
+	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
+	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
+
+	return cycles;
+}
+
+static int sirfsoc_timer_set_next_event(unsigned long delta,
+	struct clock_event_device *ce)
+{
+	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+	val |= BIT(0) | BIT(1) | BIT(2);
+
+	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+#if 0
+	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
+#else
+	/* Fix FPGA: divider of 32counter_0 doesn't work */
+	writel_relaxed(delta * 13, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
+#endif
+
+	/* enable the tick */
+	writel_relaxed(val, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+	return 0;
+}
+
+static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
+	struct clock_event_device *ce)
+{
+	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+	val &= ~(BIT(0) | BIT(1) | BIT(2));
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		WARN_ON(1);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		/* enable in set_next_event */
+		break;
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+
+	writel_relaxed(val, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+}
+
+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
+{
+	int i;
+
+	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+}
+
+static void sirfsoc_clocksource_resume(struct clocksource *cs)
+{
+	int i;
+
+	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
+		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+
+	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
+		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
+		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+
+	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+}
+
+static struct clock_event_device sirfsoc_clockevent = {
+	.name = "sirfsoc_clockevent",
+	.rating = 200,
+	.features = CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode = sirfsoc_timer_set_mode,
+	.set_next_event = sirfsoc_timer_set_next_event,
+};
+
+static struct clocksource sirfsoc_clocksource = {
+	.name = "sirfsoc_clocksource",
+	.rating = 200,
+	.mask = CLOCKSOURCE_MASK(64),
+	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
+	.read = sirfsoc_timer_read,
+	.suspend = sirfsoc_clocksource_suspend,
+	.resume = sirfsoc_clocksource_resume,
+};
+
+static struct irqaction sirfsoc_timer_irq = {
+	.name = "sirfsoc_timer0",
+	.flags = IRQF_TIMER,
+	.handler = sirfsoc_timer_interrupt,
+	.dev_id = &sirfsoc_clockevent,
+};
+
+static void __init sirfsoc_clockevent_init(void)
+{
+	clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
+
+	sirfsoc_clockevent.max_delta_ns =
+		clockevent_delta2ns(-2, &sirfsoc_clockevent);
+	sirfsoc_clockevent.min_delta_ns =
+		clockevent_delta2ns(2, &sirfsoc_clockevent);
+
+	sirfsoc_clockevent.cpumask = cpumask_of(0);
+	clockevents_register_device(&sirfsoc_clockevent);
+}
+
+/* initialize the kernel jiffy timer source */
+static void __init sirfsoc_timer_init(void)
+{
+	unsigned long rate;
+	u32 timer_div;
+	struct clk *clk;
+
+	/* initialize clocking early, we want to set the OS timer */
+	sirfsoc_of_clk_init();
+
+	/* timer's input clock is io clock */
+	clk = clk_get_sys("io", NULL);
+
+	BUG_ON(IS_ERR(clk));
+#if defined(CONFIG_SIRFMARCO_FPGA)
+	/* For FPGA, the io clk is fixed to 26Mhz */
+	rate = 26000000;
+#else
+	rate = clk_get_rate(clk);
+#endif
+
+	BUG_ON(rate < CLOCK_TICK_RATE);
+	BUG_ON(rate % CLOCK_TICK_RATE);
+
+	sirfsoc_of_timer_map();
+
+	/* Initialize the timer divider */
+	timer_div = rate / CLOCK_TICK_RATE / 2 - 1;
+	writel_relaxed((timer_div << 16) | readl_relaxed(sirfsoc_timer_base +
+				SIRFSOC_TIMER_64COUNTER_CTRL),
+			sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+
+	writel_relaxed((timer_div << 16) | readl_relaxed(sirfsoc_timer_base +
+				SIRFSOC_TIMER_32COUNTER_0_CTRL) | BIT(0),
+			sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
+
+	/* Initialize the timer counter to 0 */
+
+	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
+	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
+	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
+		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
+	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
+
+	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
+
+	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+
+	BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
+
+	sirfsoc_clockevent_init();
+}
+
+static struct of_device_id timer_ids[] = {
+	{ .compatible = "sirf,marco-tick" },
+	{},
+};
+
+static void __init sirfsoc_of_timer_map(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, timer_ids);
+	if (!np)
+		return;
+	sirfsoc_timer_base = of_iomap(np, 0);
+	if (!sirfsoc_timer_base)
+		panic("unable to map timer cpu registers\n");
+
+	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
+	if (!sirfsoc_timer_irq.irq)
+		panic("No irq passed for timer via DT\n");
+
+	of_node_put(np);
+}
+
+struct sys_timer sirfsoc_marco_timer = {
+	.init = sirfsoc_timer_init,
+};
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer-prima2.c
similarity index 98%
rename from arch/arm/mach-prima2/timer.c
rename to arch/arm/mach-prima2/timer-prima2.c
index d95bf25..305cbcc 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer-prima2.c
@@ -233,7 +233,7 @@ static void __init sirfsoc_of_timer_map(void)
 
 	np = of_find_matching_node(NULL, timer_ids);
 	if (!np)
-		panic("unable to find compatible timer node in dtb\n");
+		return;
 	sirfsoc_timer_base = of_iomap(np, 0);
 	if (!sirfsoc_timer_base)
 		panic("unable to map timer cpu registers\n");
@@ -246,6 +246,6 @@ static void __init sirfsoc_of_timer_map(void)
 	of_node_put(np);
 }
 
-struct sys_timer sirfsoc_timer = {
+struct sys_timer sirfsoc_prima2_timer = {
 	.init = sirfsoc_timer_init,
 };
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..e5db829 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -112,7 +112,7 @@ config PINCTRL_SINGLE
 
 config PINCTRL_SIRF
 	bool "CSR SiRFprimaII pin controller driver"
-	depends on ARCH_PRIMA2
+	depends on ARCH_SIRF
 	select PINMUX
 
 config PINCTRL_TEGRA
-- 
1.7.0.4



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From shawn.guo at linaro.org  Thu Aug 30 17:45:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 05:45:49 +0800
Subject: i.MX pwm patches
In-Reply-To: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120830214547.GC3613@r65073-Latitude-D630>

On Tue, Aug 28, 2012 at 01:48:15PM +0200, Sascha Hauer wrote:
> Hi All,
> 
> The following patches are an overdue work on the i.MX pwm driver.
> 
> - introduce SoC specific functions to make the driver easier to maintain
> - use peripheral clock for pwm output unconditionally
> - separate the two clocks this module has
> - enable ipg clock for register accesses, peripheral clock for enabling
>   the pwm
> - make the driver safe for calling pwm_config before pwm_enable
> - Add devicetree support for i.MX53
> 
> The platform device support is still implemented using cpu_is_*, I think
> this can be dropped completely soon

Anything stops us from doing this right now?  The bonus point of
cleaning this is that we can remove the #include <mach/hardware.h>
from the driver, which is helpful for single-kernel project.

Regards,
Shawn

> as this driver has no in kernel users
> currently, so there should be no need to keep compatibility for platform
> based boards.
> 
> Hopefully this series fixes the issues mentioned by Beno?t. It has been
> tested on an i.MX53 only.
> 
> Sascha
> 
> ----------------------------------------------------------------
> Philipp Zabel (3):
>       pwm i.MX: add devicetree support
>       pwm i.MX: fix clock lookup
>       pwm i.MX: add devicetree support
> 
> Sascha Hauer (6):
>       pwm i.MX: factor out SoC specific functions
>       pwm i.MX: remove unnecessary if in pwm_[en|dis]able
>       pwm i.MX: add functions to enable/disable pwm.
>       pwm i.MX: Use module_platform_driver
>       pwm i.MX: use per clock unconditionally
>       ARM i.MX53: Add pwms to dtsi
> 
>  arch/arm/boot/dts/imx53.dtsi        |   14 ++
>  arch/arm/mach-imx/clk-imx51-imx53.c |    4 +
>  drivers/pwm/pwm-imx.c               |  278 +++++++++++++++++++++++------------
>  3 files changed, 202 insertions(+), 94 deletions(-)


From alan at lxorguk.ukuu.org.uk  Fri Aug 31 06:59:39 2012
From: alan at lxorguk.ukuu.org.uk (Alan Cox)
Date: Fri, 31 Aug 2012 11:59:39 +0100
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <20120831103351.GE18957@n2100.arm.linux.org.uk>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
 <20120831110444.25d9b9fe@pyramind.ukuu.org.uk>
 <504091F0.1090703@parrot.com>
 <20120831103351.GE18957@n2100.arm.linux.org.uk>
Message-ID: <20120831115939.23fd4a08@pyramind.ukuu.org.uk>

On Fri, 31 Aug 2012 11:33:51 +0100
Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:

> On Fri, Aug 31, 2012 at 12:29:04PM +0200, Matthieu CASTET wrote:
> > Alan Cox a ?crit :
> > > On Fri, 31 Aug 2012 11:21:56 +0200
> > > Matthieu CASTET <castet.matthieu at free.fr> wrote:
> > > 
> > >> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
> > >> ---
> > >>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
> > >>  1 file changed, 34 insertions(+)
> > > 
> > > This is a step in the wrong direction. This should all be runtime handled
> > > 
> > > NAK.
> > > 
> > 
> > AFAIK you can't build a arm kernel that support arm6/armv7 and armv5.
> > And I am not sure it will be possible one day.
> 
> There are no plans to ever make it possible; there are too many significant
> differences between ARMv4, v5 architectures and ARMv6,v7 architectures
> to warrant making this runtime selectable.

Then bury this crap in platform files please not in the drivers/tty layer
code. Make it a platform driver provided callback or something.

Alan


From stigge at antcom.de  Fri Aug 31 06:57:37 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 31 Aug 2012 12:57:37 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <50407E44.5080408@antcom.de>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de> <503E3331.8050203@antcom.de>
 <20120829172820.43bbe68e@eb-e6520> <50407E44.5080408@antcom.de>
Message-ID: <504098A1.4050208@antcom.de>

On 08/31/2012 11:05 AM, Roland Stigge wrote:
> I tried to port this on top of Sascha's patches for imx53, only for mxc v3 for now, as below.
> 
> Unfortunately, I still get:
> 
> ...
> UnCorrectable RS-ECC Error
> UnCorrectable RS-ECC Error
> UnCorrectable RS-ECC Error
> UnCorrectable RS-ECC Error
> UnCorrectable RS-ECC Error
> ...
> 
> from mxc_nand.c's mxc_nand_correct_data_v2_v3(). Maybe there's still sth. missing in the
> error correction code?

With the below incremental fix, it works. :-)

Thanks,

Roland

PS: Will you prepare a patch for l2-mtd.git? I only have an imx53, can't test the v1/v2 etc.
configs.


--- linux-2.6.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-2.6/drivers/mtd/nand/mxc_nand.c
@@ -1141,14 +1141,14 @@ static void mxc_nand_command(struct mtd_
                host->devtype_data->send_cmd(host, command, true);
                mxc_do_addr_cycle(mtd, column, page_addr);
                host->devtype_data->send_read_id(host);
-               host->buf_start = column;
+               host->buf_start = 0;
                break;
 
        case NAND_CMD_PARAM:
                host->devtype_data->send_cmd(host, command, true);
                mxc_do_addr_cycle(mtd, column, page_addr);
                host->devtype_data->send_read_param(host);
-               host->buf_start = column;
+               host->buf_start = 0;
                break;
 
        case NAND_CMD_ERASE1:


From kmpark at infradead.org  Fri Aug 31 06:58:18 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 31 Aug 2012 19:58:18 +0900
Subject: [PATCH 1/2] ARM: exynos: delete redundant HAVE_SCHED_CLOCK option
 in Kconfig
In-Reply-To: <CAGsJ_4xUBDGn1hDdWvUX68MfC98936v-_vLfPrisLNL7RY6nEw@mail.gmail.com>
References: <1346406296-16223-1-git-send-email-Barry.Song@csr.com>
 <CAH9JG2W8xZrkmGkVw_JDY3qSsqHnaTi8-BNoW99V3FUyvWBXng@mail.gmail.com>
 <CAGsJ_4xUBDGn1hDdWvUX68MfC98936v-_vLfPrisLNL7RY6nEw@mail.gmail.com>
Message-ID: <CAH9JG2W3KL=K7MHDsF4_NScjY01X56JLc=nBy+wvh3EFQefQmw@mail.gmail.com>

Acked-by: Kyungmin Park <kyungmin.park at samsung.com>

# git grep HAVE_SCHED_CLOCK arch/arm/
arch/arm/Kconfig:       select HAVE_SCHED_CLOCK
arch/arm/mach-exynos/Kconfig:   select HAVE_SCHED_CLOCK

On 8/31/12, Barry Song <21cnbao at gmail.com> wrote:
> 2012/8/31 Kyungmin Park <kmpark at infradead.org>:
>> Hi,
>>
>> then where select it HAVE_SCHED_CLOCK? apart from other exynos board,
>> universal have to use another clock.
>
> The old arch/arm/kernel/Makefile:
> obj-$(CONFIG_HAVE_SCHED_CLOCK)  += sched_clock.o
> has become:
> obj-y += sched_clock.o
>
>>
>> Thank you,
>> Kyungmin Park
>>
>> On 8/31/12, Barry Song <Barry.Song at csr.com> wrote:
>>> From: Barry Song <Baohua.Song at csr.com>
>>>
>>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>>> ---
>>>  arch/arm/mach-exynos/Kconfig |    1 -
>>>  1 files changed, 0 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>> index b5b4c8c..3fd4ab3 100644
>>> --- a/arch/arm/mach-exynos/Kconfig
>>> +++ b/arch/arm/mach-exynos/Kconfig
>>> @@ -243,7 +243,6 @@ config MACH_UNIVERSAL_C210
>>>       select CPU_EXYNOS4210
>>>       select S5P_HRT
>>>       select CLKSRC_MMIO
>>> -     select HAVE_SCHED_CLOCK
>>>       select S5P_GPIO_INT
>>>       select S5P_DEV_FIMC0
>>>       select S5P_DEV_FIMC1
>>> --
>>> 1.7.0.4
>>>
> -barry
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From linux at arm.linux.org.uk  Fri Aug 31 06:59:01 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 31 Aug 2012 11:59:01 +0100
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <20120831115939.23fd4a08@pyramind.ukuu.org.uk>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
 <20120831110444.25d9b9fe@pyramind.ukuu.org.uk> <504091F0.1090703@parrot.com>
 <20120831103351.GE18957@n2100.arm.linux.org.uk>
 <20120831115939.23fd4a08@pyramind.ukuu.org.uk>
Message-ID: <20120831105901.GF18957@n2100.arm.linux.org.uk>

On Fri, Aug 31, 2012 at 11:59:39AM +0100, Alan Cox wrote:
> On Fri, 31 Aug 2012 11:33:51 +0100
> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> 
> > On Fri, Aug 31, 2012 at 12:29:04PM +0200, Matthieu CASTET wrote:
> > > Alan Cox a ?crit :
> > > > On Fri, 31 Aug 2012 11:21:56 +0200
> > > > Matthieu CASTET <castet.matthieu at free.fr> wrote:
> > > > 
> > > >> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
> > > >> ---
> > > >>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
> > > >>  1 file changed, 34 insertions(+)
> > > > 
> > > > This is a step in the wrong direction. This should all be runtime handled
> > > > 
> > > > NAK.
> > > > 
> > > 
> > > AFAIK you can't build a arm kernel that support arm6/armv7 and armv5.
> > > And I am not sure it will be possible one day.
> > 
> > There are no plans to ever make it possible; there are too many significant
> > differences between ARMv4, v5 architectures and ARMv6,v7 architectures
> > to warrant making this runtime selectable.
> 
> Then bury this crap in platform files please not in the drivers/tty layer
> code. Make it a platform driver provided callback or something.

Platform driver callbacks via platform data are incompatible with DT,
which is where folk elsewhere in the kernel community have kicked ARM
towards, away from the platform driver/device with platform data model.


From cavokz at gmail.com  Fri Aug 31 07:05:12 2012
From: cavokz at gmail.com (Domenico Andreoli)
Date: Fri, 31 Aug 2012 13:05:12 +0200
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120830192831.GD18957@n2100.arm.linux.org.uk>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk>
 <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk>
 <503FB9E6.7020102@gmail.com>
 <20120830192831.GD18957@n2100.arm.linux.org.uk>
Message-ID: <20120831110512.GA24490@glitch>

On Thu, Aug 30, 2012 at 08:28:31PM +0100, Russell King - ARM Linux wrote:
> 
> I think what we need is arch/arm/include/debug, move the platform specific
> debug-macros headers into there, named using platform specific file names.
> Then we have the config system define a string-based config:
> 
> config DEBUG_LL_INCLUDE
> 	string
> 	default "<debug/icedcc.S>" if DEBUG_ICEDCC
> 	default "<debug/msm.S>" if DEBUG_MSM_UART1 || DEBUG_MSM_UART2 || DEBUG_MSM_UART3
> ... etc ...
> 	default "mach/debug-macros.S"
> 
> And then we can have the various assembly codes do:
> 
> #include CONFIG_DEBUG_LL_INCLUDE
> 
> Not only does this give a migration path, but it also gives folk a reason
> to move to the 'new way' if they want to be part of a multi-platform
> kernel - and it's a trivial thing to do.  Just move the include file,
> add an entry to the DEBUG_LL_INCLUDE entry and the "Kernel low-level
> debugging port" choice statement, and job done for both non-multi-platform
> and multi-platform kernels.
> 
> What's even nicer about this approach is it doesn't require everyone to
> change simultaneously - it can be done progressively as required.

This means that:

  1) DEBUG_LL console is specified statically (it's a debug option so you
     are supposed to be already building the kernel, right?)

  2) It's not portable across incompatible SoCs so it must really stay
     disabled on production multi-platform kernels.

Regards,
Domenico


From lee.jones at linaro.org  Fri Aug 31 07:08:22 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 12:08:22 +0100
Subject: [rtc-linux] [PATCH 1/1] drivers/rtc/rtc-ab8500.c: Revoke Device
 Tree enablement
In-Reply-To: <CACRpkdZa-72QogrZ-P5jbDHTTX64babZo3ydjzfgC-4LWUBfMg@mail.gmail.com>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
 <1344527828-6283-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdZa-72QogrZ-P5jbDHTTX64babZo3ydjzfgC-4LWUBfMg@mail.gmail.com>
Message-ID: <20120831110818.GA5962@gmail.com>

On Tue, Aug 14, 2012 at 10:32:02AM +0200, Linus Walleij wrote:
> On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > All AB8500 devices are now registered via MFD core, so Device Tree
> > capability is no longer required for probing. Here we pull the DT
> > match table to ensure we're no longer probed during Device Tree
> > start-up.
> >
> > CC: Alessandro Zummo <a.zummo at towertech.it>
> > CC: rtc-linux at googlegroups.com
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

I'm guessing we still need Alessandro's Ack?

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linux at arm.linux.org.uk  Fri Aug 31 07:11:38 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 31 Aug 2012 12:11:38 +0100
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120831110512.GA24490@glitch>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk> <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk> <503FB9E6.7020102@gmail.com>
 <20120830192831.GD18957@n2100.arm.linux.org.uk>
 <20120831110512.GA24490@glitch>
Message-ID: <20120831111138.GG18957@n2100.arm.linux.org.uk>

On Fri, Aug 31, 2012 at 01:05:12PM +0200, Domenico Andreoli wrote:
> On Thu, Aug 30, 2012 at 08:28:31PM +0100, Russell King - ARM Linux wrote:
> > 
> > I think what we need is arch/arm/include/debug, move the platform specific
> > debug-macros headers into there, named using platform specific file names.
> > Then we have the config system define a string-based config:
> > 
> > config DEBUG_LL_INCLUDE
> > 	string
> > 	default "<debug/icedcc.S>" if DEBUG_ICEDCC
> > 	default "<debug/msm.S>" if DEBUG_MSM_UART1 || DEBUG_MSM_UART2 || DEBUG_MSM_UART3
> > ... etc ...
> > 	default "mach/debug-macros.S"
> > 
> > And then we can have the various assembly codes do:
> > 
> > #include CONFIG_DEBUG_LL_INCLUDE
> > 
> > Not only does this give a migration path, but it also gives folk a reason
> > to move to the 'new way' if they want to be part of a multi-platform
> > kernel - and it's a trivial thing to do.  Just move the include file,
> > add an entry to the DEBUG_LL_INCLUDE entry and the "Kernel low-level
> > debugging port" choice statement, and job done for both non-multi-platform
> > and multi-platform kernels.
> > 
> > What's even nicer about this approach is it doesn't require everyone to
> > change simultaneously - it can be done progressively as required.
> 
> This means that:

I'm not about to re-open the debate again.  Please go back and read the
previous discussions during the last year about this where eventually
agreement on this way forward was reached.  Thanks.


From w.sang at pengutronix.de  Fri Aug 31 07:22:58 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Fri, 31 Aug 2012 13:22:58 +0200
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the
 Nomadik I2C driver
In-Reply-To: <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
 <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20120831112258.GA2624@pengutronix.de>

On Thu, Aug 23, 2012 at 04:01:27PM +0100, Lee Jones wrote:
> Here we apply the bindings required for successful Device Tree
> probing of the i2c-nomadik driver.
> 
> Cc: linux-i2c at vger.kernel.org
> Acked-by: srinidhi kasagar <srinidhi.kasagar at stericsson.com>

Two acks? I'd think this cannot work for multiple reasons.

BTW, patch 2 and 3 should be merged. It is a lot easier to review the
code with the binding description together.

Is there some dependency other than updating the dts files? If not, I'd
like to pick up the patch via I2C.

> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/i2c/busses/i2c-nomadik.c |   28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
> index 61b00ed..8168389 100644
> --- a/drivers/i2c/busses/i2c-nomadik.c
> +++ b/drivers/i2c/busses/i2c-nomadik.c
> @@ -25,6 +25,7 @@
>  #include <linux/regulator/consumer.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/platform_data/i2c-nomadik.h>
> +#include <linux/of.h>
>  
>  #define DRIVER_NAME "nmk-i2c"
>  
> @@ -920,15 +921,42 @@ static struct nmk_i2c_controller u8500_i2c = {
>  	.sm             = I2C_FREQ_MODE_FAST,
>  };
>  
> +static void nmk_i2c_of_probe(struct device_node *np,
> +			struct nmk_i2c_controller *pdata)
> +{
> +	/* Provide the default configuration as a base. */
> +	pdata = &u8500_i2c;

?????? I wonder how that could work... have you tested the patch?

> +
> +	of_property_read_u32(np, "clock-frequency", (u32*)&pdata->clk_freq);

Might be worth changing clk_freq to u32?

> +
> +	/* This driver only supports 'standard' and 'fast' modes of operation. */
> +	if (pdata->clk_freq <= 100000)
> +		pdata->sm = I2C_FREQ_MODE_STANDARD;

Is standard == 100000 Hz?


> +	else
> +		pdata->sm = I2C_FREQ_MODE_FAST;

If those two are fixed frequencies, you should omit a warning if the
devicetree has a different frequency set and report which one is going
to be used actually.


> +}
> +
>  static atomic_t adapter_id = ATOMIC_INIT(0);
>  
>  static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
>  {
>  	int ret = 0;
>  	struct nmk_i2c_controller *pdata = adev->dev.platform_data;
> +	struct device_node *np = adev->dev.of_node;
>  	struct nmk_i2c_dev	*dev;
>  	struct i2c_adapter *adap;
>  
> +	if (np) {
> +		if (!pdata) {
> +			pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
> +			if (!pdata) {
> +				ret = -ENOMEM;
> +				goto err_no_mem;
> +			}
> +		}
> +		nmk_i2c_of_probe(np, pdata);
> +	}
> +
>  	if (!pdata)
>  		/* No i2c configuration found, using the default. */
>  		pdata = &u8500_i2c;
> -- 
> 1.7.9.5
> 

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From shawn.guo at linaro.org  Thu Aug 30 18:26:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 06:26:53 +0800
Subject: [PATCH 5/9] pwm i.MX: add devicetree support
In-Reply-To: <1346154504-5623-6-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <1346154504-5623-6-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120830222650.GD3613@r65073-Latitude-D630>

On Tue, Aug 28, 2012 at 01:48:20PM +0200, Sascha Hauer wrote:
> From: Philipp Zabel <p.zabel at pengutronix.de>
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  drivers/pwm/pwm-imx.c |   25 +++++++++++++++++++------
>  1 file changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index a689144..dfc1bae 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -16,9 +16,9 @@
>  #include <linux/clk.h>
>  #include <linux/io.h>
>  #include <linux/pwm.h>
> +#include <linux/of_device.h>
>  #include <mach/hardware.h>
>  
> -
>  /* i.MX1 and i.MX21 share the same PWM function block: */
>  
>  #define MX1_PWMC    0x00   /* PWM Control Register */
> @@ -203,8 +203,17 @@ static struct pwm_ops imx_pwm_ops = {
>  	.owner = THIS_MODULE,
>  };
>  
> +static const struct of_device_id imx_pwm_dt_ids[] = {
> +	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_config_v1, },
> +	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_config_v2, },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx_pwm_of_match);

s/imx_pwm_of_match/imx_pwm_dt_ids

Regards,
Shawn

> +
>  static int __devinit imx_pwm_probe(struct platform_device *pdev)
>  {
> +	const struct of_device_id *of_id =
> +			of_match_device(imx_pwm_dt_ids, &pdev->dev);
>  	struct imx_chip *imx;
>  	struct resource *r;
>  	int ret = 0;
> @@ -235,12 +244,16 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
>  	if (imx->mmio_base == NULL)
>  		return -EADDRNOTAVAIL;
>  
> -	if (cpu_is_mx1() || cpu_is_mx21()) {
> -		imx->config = imx_pwm_config_v1;
> -		imx->set_enable = imx_pwm_set_enable_v1;
> +	if (of_id) {
> +		imx->config = of_id->data;
>  	} else {
> -		imx->config = imx_pwm_config_v2;
> -		imx->set_enable = imx_pwm_set_enable_v2;
> +		if (cpu_is_mx1() || cpu_is_mx21()) {
> +			imx->config = imx_pwm_config_v1;
> +			imx->set_enable = imx_pwm_set_enable_v1;
> +		} else {
> +			imx->config = imx_pwm_config_v2;
> +			imx->set_enable = imx_pwm_set_enable_v2;
> +		}
>  	}
>  
>  	ret = pwmchip_add(&imx->chip);
> -- 
> 1.7.10.4
> 


From shawn.guo at linaro.org  Thu Aug 30 18:28:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 06:28:45 +0800
Subject: [PATCH 9/9] pwm i.MX: add devicetree support
In-Reply-To: <1346154504-5623-10-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <1346154504-5623-10-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120830222843.GE3613@r65073-Latitude-D630>

Shouldn't this patch be merged into #5?  Also, a binding doc should
be added.

Regards,
Shawn

On Tue, Aug 28, 2012 at 01:48:24PM +0200, Sascha Hauer wrote:
> From: Philipp Zabel <p.zabel at pengutronix.de>
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  drivers/pwm/pwm-imx.c |   25 ++++++++++++++++++++++---
>  1 file changed, 22 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index 308ab51..dce2acb 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -206,9 +206,25 @@ static struct pwm_ops imx_pwm_ops = {
>  	.owner = THIS_MODULE,
>  };
>  
> +struct imx_pwm_data {
> +	int (*config)(struct pwm_chip *chip,
> +		struct pwm_device *pwm, int duty_ns, int period_ns);
> +	void (*set_enable)(struct pwm_chip *chip, bool enable);
> +};
> +
> +static struct imx_pwm_data imx_pwm_data_v1 = {
> +	.config = imx_pwm_config_v1,
> +	.set_enable = imx_pwm_set_enable_v1,
> +};
> +
> +static struct imx_pwm_data imx_pwm_data_v2 = {
> +	.config = imx_pwm_config_v2,
> +	.set_enable = imx_pwm_set_enable_v2,
> +};
> +
>  static const struct of_device_id imx_pwm_dt_ids[] = {
> -	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_config_v1, },
> -	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_config_v2, },
> +	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
> +	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, imx_pwm_of_match);
> @@ -257,7 +273,9 @@ static int __devinit imx_pwm_probe(struct platform_device *pdev)
>  		return -EADDRNOTAVAIL;
>  
>  	if (of_id) {
> -		imx->config = of_id->data;
> +		struct imx_pwm_data *data = of_id->data;
> +		imx->config = data->config;
> +		imx->set_enable = data->set_enable;
>  	} else {
>  		if (cpu_is_mx1() || cpu_is_mx21()) {
>  			imx->config = imx_pwm_config_v1;
> @@ -290,6 +308,7 @@ static int __devexit imx_pwm_remove(struct platform_device *pdev)
>  static struct platform_driver imx_pwm_driver = {
>  	.driver		= {
>  		.name	= "mxc_pwm",
> +		.of_match_table = of_match_ptr(imx_pwm_dt_ids),
>  	},
>  	.probe		= imx_pwm_probe,
>  	.remove		= __devexit_p(imx_pwm_remove),
> -- 
> 1.7.10.4
> 


From shawn.guo at linaro.org  Thu Aug 30 18:32:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 06:32:20 +0800
Subject: [PATCH 8/9] ARM i.MX53: Add pwms to dtsi
In-Reply-To: <1346154504-5623-9-git-send-email-s.hauer@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <1346154504-5623-9-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120830223219.GF3613@r65073-Latitude-D630>

On Tue, Aug 28, 2012 at 01:48:23PM +0200, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> Conflicts:
> 	arch/arm/mach-imx/clk-imx51-imx53.c

Yeah, I know you have sorted out conflicts :)

> ---
>  arch/arm/boot/dts/imx53.dtsi        |   14 ++++++++++++++
>  arch/arm/mach-imx/clk-imx51-imx53.c |    4 ++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index cd37165..7ec17e4 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -189,6 +189,20 @@
>  				status = "disabled";
>  			};
>  
> +			pwm1: pwm at 53fb4000 {
> +				#pwm-cells = <3>;

pwm-cells should be 2?

> +				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> +				reg = <0x53fb4000 0x4000>;
> +				interrupts = <61>;
> +			};
> +
> +			pwm2: pwm at 53fb8000 {
> +				#pwm-cells = <3>;
> +				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
> +				reg = <0x53fb8000 0x4000>;
> +				interrupts = <94>;
> +			};
> +
>  			uart1: serial at 53fbc000 {
>  				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
>  				reg = <0x53fbc000 0x4000>;
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index 4bdcaa9..b522411 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -455,6 +455,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
>  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
>  	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
> +	clk_register_clkdev(clk[pwm1_ipg_gate], "ipg", "53fb4000.pwm");
> +	clk_register_clkdev(clk[pwm1_hf_gate], "per", "53fb4000.pwm");
> +	clk_register_clkdev(clk[pwm2_ipg_gate], "ipg", "53fb8000.pwm");
> +	clk_register_clkdev(clk[pwm2_hf_gate], "per", "53fb8000.pwm");

It should be in a separate patch?

>  
>  	/* set SDHC root clock to 200MHZ*/
>  	clk_set_rate(clk[esdhc_a_podf], 200000000);
> -- 
> 1.7.10.4
> 

-- 
Regards,
Shawn


From cavokz at gmail.com  Fri Aug 31 07:46:29 2012
From: cavokz at gmail.com (Domenico Andreoli)
Date: Fri, 31 Aug 2012 13:46:29 +0200
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120831111138.GG18957@n2100.arm.linux.org.uk>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk>
 <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk>
 <503FB9E6.7020102@gmail.com>
 <20120830192831.GD18957@n2100.arm.linux.org.uk>
 <20120831110512.GA24490@glitch>
 <20120831111138.GG18957@n2100.arm.linux.org.uk>
Message-ID: <20120831114629.GB24490@glitch>

On Fri, Aug 31, 2012 at 12:11:38PM +0100, Russell King - ARM Linux wrote:
> On Fri, Aug 31, 2012 at 01:05:12PM +0200, Domenico Andreoli wrote:
> > On Thu, Aug 30, 2012 at 08:28:31PM +0100, Russell King - ARM Linux wrote:
> > > 
> > > I think what we need is arch/arm/include/debug, move the platform specific
> > > debug-macros headers into there, named using platform specific file names.
> > > Then we have the config system define a string-based config:
> > > 
> > > config DEBUG_LL_INCLUDE
> > > 	string
> > > 	default "<debug/icedcc.S>" if DEBUG_ICEDCC
> > > 	default "<debug/msm.S>" if DEBUG_MSM_UART1 || DEBUG_MSM_UART2 || DEBUG_MSM_UART3
> > > ... etc ...
> > > 	default "mach/debug-macros.S"
> > > 
> > > And then we can have the various assembly codes do:
> > > 
> > > #include CONFIG_DEBUG_LL_INCLUDE
> > > 
> > > Not only does this give a migration path, but it also gives folk a reason
> > > to move to the 'new way' if they want to be part of a multi-platform
> > > kernel - and it's a trivial thing to do.  Just move the include file,
> > > add an entry to the DEBUG_LL_INCLUDE entry and the "Kernel low-level
> > > debugging port" choice statement, and job done for both non-multi-platform
> > > and multi-platform kernels.
> > > 
> > > What's even nicer about this approach is it doesn't require everyone to
> > > change simultaneously - it can be done progressively as required.
> > 
> > This means that:
> 
> I'm not about to re-open the debate again.  Please go back and read the
> previous discussions during the last year about this where eventually
> agreement on this way forward was reached.  Thanks.

I don't want to reopen anything, it's only that I've clearly missed the
discussion (*) as also my patches in the area may show (**). So I really
wanted to understand if, for once, I've understood the thing correctly.

cheers,
Domenico

(*) I would have appreciated if you had pointed it to me in the only
comment you made on those patches but that's ok, it has been fun anyway

(**) http://lists.infradead.org/pipermail/linux-arm-kernel/2012-July/109457.html


From castet.matthieu at free.fr  Fri Aug 31 07:47:25 2012
From: castet.matthieu at free.fr (Matthieu CASTET)
Date: Fri, 31 Aug 2012 13:47:25 +0200
Subject: [PATCH v2] hvc_dcc : add support to armv4 and armv5 core
Message-ID: <1346413645-4593-1-git-send-email-castet.matthieu@free.fr>

Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
---
 drivers/tty/hvc/hvc_dcc.c |   83 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 76 insertions(+), 7 deletions(-)

diff --git a/drivers/tty/hvc/hvc_dcc.c b/drivers/tty/hvc/hvc_dcc.c
index 44fbeba..5f8827f 100644
--- a/drivers/tty/hvc/hvc_dcc.c
+++ b/drivers/tty/hvc/hvc_dcc.c
@@ -27,10 +27,10 @@
 #include "hvc_console.h"
 
 /* DCC Status Bits */
-#define DCC_STATUS_RX		(1 << 30)
-#define DCC_STATUS_TX		(1 << 29)
+#define DCC_STATUS_RX_V6		(1 << 30)
+#define DCC_STATUS_TX_V6		(1 << 29)
 
-static inline u32 __dcc_getstatus(void)
+static inline u32 __dcc_getstatus_v6(void)
 {
 	u32 __ret;
 	asm volatile("mrc p14, 0, %0, c0, c1, 0	@ read comms ctrl reg"
@@ -40,7 +40,7 @@ static inline u32 __dcc_getstatus(void)
 }
 
 
-static inline char __dcc_getchar(void)
+static inline char __dcc_getchar_v6(void)
 {
 	char __c;
 
@@ -51,7 +51,7 @@ static inline char __dcc_getchar(void)
 	return __c;
 }
 
-static inline void __dcc_putchar(char c)
+static inline void __dcc_putchar_v6(char c)
 {
 	asm volatile("mcr p14, 0, %0, c0, c5, 0	@ write a char"
 		: /* no output register */
@@ -59,6 +59,69 @@ static inline void __dcc_putchar(char c)
 	isb();
 }
 
+static int hvc_dcc_put_chars_v6(uint32_t vt, const char *buf, int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		while (__dcc_getstatus_v6() & DCC_STATUS_TX_V6)
+			cpu_relax();
+
+		__dcc_putchar_v6(buf[i]);
+	}
+
+	return count;
+}
+
+static int hvc_dcc_get_chars_v6(uint32_t vt, char *buf, int count)
+{
+	int i;
+
+	for (i = 0; i < count; ++i)
+		if (__dcc_getstatus_v6() & DCC_STATUS_RX_V6)
+			buf[i] = __dcc_getchar_v6();
+		else
+			break;
+
+	return i;
+}
+
+static const struct hv_ops hvc_dcc_get_put_ops_v6 = {
+	.get_chars = hvc_dcc_get_chars_v6,
+	.put_chars = hvc_dcc_put_chars_v6,
+};
+
+#define DCC_STATUS_RX		(1 << 0)
+#define DCC_STATUS_TX		(1 << 1)
+
+/* primitive JTAG1 protocol utilities */
+static inline u32 __dcc_getstatus(void)
+{
+	u32 ret;
+
+	asm __volatile__ ("mrc p14, 0, %0, c0, c0	@ read comms ctrl reg"
+		: "=r" (ret));
+
+	return ret;
+}
+
+static inline char __dcc_getchar(void)
+{
+	char c;
+
+	asm __volatile__ ("mrc p14, 0, %0, c1, c0	@ read comms data reg"
+		: "=r" (c));
+
+	return c;
+}
+
+static inline void __dcc_putchar(unsigned char c)
+{
+	asm __volatile__ ("mcr p14, 0, %0, c1, c0	@ write a char"
+		: /* no output register */
+		: "r" (c));
+}
+
 static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
 {
 	int i;
@@ -93,14 +156,20 @@ static const struct hv_ops hvc_dcc_get_put_ops = {
 
 static int __init hvc_dcc_console_init(void)
 {
-	hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);
+	if (cpu_architecture() >= CPU_ARCH_ARMv6)
+		hvc_instantiate(0, 0, &hvc_dcc_get_put_ops_v6);
+	else
+		hvc_instantiate(0, 0, &hvc_dcc_get_put_ops);
 	return 0;
 }
 console_initcall(hvc_dcc_console_init);
 
 static int __init hvc_dcc_init(void)
 {
-	hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
+	if (cpu_architecture() >= CPU_ARCH_ARMv6)
+		hvc_alloc(0, 0, &hvc_dcc_get_put_ops_v6, 128);
+	else
+		hvc_alloc(0, 0, &hvc_dcc_get_put_ops, 128);
 	return 0;
 }
 device_initcall(hvc_dcc_init);
-- 
1.7.10.4



From matthieu.castet at parrot.com  Fri Aug 31 07:48:17 2012
From: matthieu.castet at parrot.com (Matthieu CASTET)
Date: Fri, 31 Aug 2012 13:48:17 +0200
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <20120831115939.23fd4a08@pyramind.ukuu.org.uk>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>	<20120831110444.25d9b9fe@pyramind.ukuu.org.uk>	<504091F0.1090703@parrot.com>	<20120831103351.GE18957@n2100.arm.linux.org.uk>
 <20120831115939.23fd4a08@pyramind.ukuu.org.uk>
Message-ID: <5040A481.7020403@parrot.com>

Alan Cox a ?crit :
> On Fri, 31 Aug 2012 11:33:51 +0100
> Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> 
>> On Fri, Aug 31, 2012 at 12:29:04PM +0200, Matthieu CASTET wrote:
>>> Alan Cox a ?crit :
>>>> On Fri, 31 Aug 2012 11:21:56 +0200
>>>> Matthieu CASTET <castet.matthieu at free.fr> wrote:
>>>>
>>>>> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>
>>>>> ---
>>>>>  drivers/tty/hvc/hvc_dcc.c |   34 ++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 34 insertions(+)
>>>> This is a step in the wrong direction. This should all be runtime handled
>>>>
>>>> NAK.
>>>>
>>> AFAIK you can't build a arm kernel that support arm6/armv7 and armv5.
>>> And I am not sure it will be possible one day.
>> There are no plans to ever make it possible; there are too many significant
>> differences between ARMv4, v5 architectures and ARMv6,v7 architectures
>> to warrant making this runtime selectable.
> 
> Then bury this crap in platform files please not in the drivers/tty layer
> code. Make it a platform driver provided callback or something.
> 
I posted a new v2 patch that make the selection dynamic.


Matthieu


From lee.jones at linaro.org  Fri Aug 31 08:04:15 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 13:04:15 +0100
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the Nomadik
 I2C driver
In-Reply-To: <20120831112258.GA2624@pengutronix.de>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
 <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
 <20120831112258.GA2624@pengutronix.de>
Message-ID: <20120831120411.GB5962@gmail.com>

> Is there some dependency other than updating the dts files? If not, I'd
> like to pick up the patch via I2C.

There's no other dependency. Feel free to take them into your tree.

> > +static void nmk_i2c_of_probe(struct device_node *np,
> > +			struct nmk_i2c_controller *pdata)
> > +{
> > +	/* Provide the default configuration as a base. */
> > +	pdata = &u8500_i2c;
> 
> ?????? I wonder how that could work... have you tested the patch?

Wow, that's a great spot!

I have tested the patch, but I don't have any i2c devices, so can't
test full functionality. I, wrongly it seems, assumed there would be
a complaint from the I2C subsystem if any of the values seemed wrong.
What I will do before next submission is print out the entire pdata
structure to ensure it's populated in the correct way.

> > +
> > +	of_property_read_u32(np, "clock-frequency", (u32*)&pdata->clk_freq);
> 
> Might be worth changing clk_freq to u32?

Yes, makes sense. 

> > +
> > +	/* This driver only supports 'standard' and 'fast' modes of operation. */
> > +	if (pdata->clk_freq <= 100000)
> > +		pdata->sm = I2C_FREQ_MODE_STANDARD;
> 
> Is standard == 100000 Hz?

Well it depends on how you interpret the comments in:
     include/linux/platform_data/i2c-nomadik.h

enum i2c_freq_mode {
        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
        I2C_FREQ_MODE_HIGH_SPEED,       /* up to 3.4 Mb/s */
        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
};

I guess your guess would be better than mine.

> > +	else
> > +		pdata->sm = I2C_FREQ_MODE_FAST;
> 
> If those two are fixed frequencies, you should omit a warning if the
> devicetree has a different frequency set and report which one is going
> to be used actually.

Well, again by the comments above I would say that in between values
were valid, but I'm willing to bow down to your knowledge if you think
they are fixed values?

Thanks for reviewing.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From alan at lxorguk.ukuu.org.uk  Fri Aug 31 08:25:19 2012
From: alan at lxorguk.ukuu.org.uk (Alan Cox)
Date: Fri, 31 Aug 2012 13:25:19 +0100
Subject: [PATCH] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <5040A481.7020403@parrot.com>
References: <1346404916-27616-1-git-send-email-castet.matthieu@free.fr>
 <20120831110444.25d9b9fe@pyramind.ukuu.org.uk>
 <504091F0.1090703@parrot.com>
 <20120831103351.GE18957@n2100.arm.linux.org.uk>
 <20120831115939.23fd4a08@pyramind.ukuu.org.uk>
 <5040A481.7020403@parrot.com>
Message-ID: <20120831132519.7c33f648@pyramind.ukuu.org.uk>

> > Then bury this crap in platform files please not in the drivers/tty layer
> > code. Make it a platform driver provided callback or something.
> > 
> I posted a new v2 patch that make the selection dynamic.

Thanks - fine with that one - or with burying it in headers etc in the arm
subdirs.

Greg's email address btw has changed - you want his current one as
suse.de bounces.

Alan


From ulf.hansson at stericsson.com  Fri Aug 31 08:21:27 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 31 Aug 2012 14:21:27 +0200
Subject: [PATCH 0/4] clk: Support for smp_twd clock for ux500
Message-ID: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

To implement support for the smp_twd clock for ux500 several steps
was needed. This patchseries has also proposed some new changes in the
common clock core, which the ux500 smp_twd clock definition are
relying on.

Moreover some crossdepency exist to the ux500 prcmu mfd driver.
My idea is that the corresponding maintainers may be able to ack these
changes, if they like them of course, so we can merge this through
Mike Turquette's clk git tree. Otherwise I can happily set up some other
way forward, if that suits better.

Patches is based upon Linux 3.6 rc2. The clock patches specific for ux500,
is based upon the series [PATCH V2 0/4] clk: Convert ARM ux500 to common
clock.

Michel Jaouen (1):
  mfd: dbx500: Provide a more accurate smp_twd clock

Ulf Hansson (3):
  clk: Provide option for clk_get_rate to issue hw for new rate
  clk: ux500: Support for prmcu_rate clock
  clk: ux500: Define smp_twd clock for u8500

 drivers/clk/clk.c                |   43 +++++++++++++++++++++-----------------
 drivers/clk/ux500/clk-prcmu.c    |   14 +++++++++++++
 drivers/clk/ux500/clk.h          |    5 +++++
 drivers/clk/ux500/u8500_clk.c    |   12 +++++++----
 drivers/mfd/db8500-prcmu.c       |   42 +++++++++++++++++++++++++++++++++++++
 drivers/mfd/dbx500-prcmu-regs.h  |    4 +++-
 include/linux/clk-provider.h     |    1 +
 include/linux/mfd/dbx500-prcmu.h |    1 +
 8 files changed, 98 insertions(+), 24 deletions(-)

-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 31 08:21:28 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 31 Aug 2012 14:21:28 +0200
Subject: [PATCH 1/4] clk: Provide option for clk_get_rate to issue hw for new
 rate
In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346415691-13371-2-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

By using CLK_GET_RATE_NOCACHE flag, we tell the clk_get_rate API to
issue the hw for an updated clock rate. This can be used for a clock
which rate may be updated without a client necessary modifying it.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/clk.c            |   43 +++++++++++++++++++++++-------------------
 include/linux/clk-provider.h |    1 +
 2 files changed, 25 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index efdfd00..d9cbae0 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -558,25 +558,6 @@ int clk_enable(struct clk *clk)
 EXPORT_SYMBOL_GPL(clk_enable);
 
 /**
- * clk_get_rate - return the rate of clk
- * @clk: the clk whose rate is being returned
- *
- * Simply returns the cached rate of the clk.  Does not query the hardware.  If
- * clk is NULL then returns 0.
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long rate;
-
-	mutex_lock(&prepare_lock);
-	rate = __clk_get_rate(clk);
-	mutex_unlock(&prepare_lock);
-
-	return rate;
-}
-EXPORT_SYMBOL_GPL(clk_get_rate);
-
-/**
  * __clk_round_rate - round the given rate for a clk
  * @clk: round the rate of this clock
  *
@@ -702,6 +683,30 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
 }
 
 /**
+ * clk_get_rate - return the rate of clk
+ * @clk: the clk whose rate is being returned
+ *
+ * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
+ * is set, which means a recalc_rate will be issued.
+ * If clk is NULL then returns 0.
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+
+	mutex_lock(&prepare_lock);
+
+	if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
+		__clk_recalc_rates(clk, 0);
+
+	rate = __clk_get_rate(clk);
+	mutex_unlock(&prepare_lock);
+
+	return rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/**
  * __clk_speculate_rates
  * @clk: first clk in the subtree
  * @parent_rate: the "future" rate of clk's parent
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 77335fa..1b15307 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -26,6 +26,7 @@
 #define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
 #define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
 #define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
 
 struct clk_hw;
 
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 31 08:21:29 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 31 Aug 2012 14:21:29 +0200
Subject: [PATCH 2/4] clk: ux500: Support for prmcu_rate clock
In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346415691-13371-3-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

The prmcu_rate clock is not gateable and has a rate which
only can be fetched.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/clk-prcmu.c |   14 ++++++++++++++
 drivers/clk/ux500/clk.h       |    5 +++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 1d779ad..930cdfe 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -153,6 +153,11 @@ static struct clk_ops clk_prcmu_gate_ops = {
 	.recalc_rate = clk_prcmu_recalc_rate,
 };
 
+static struct clk_ops clk_prcmu_rate_ops = {
+	.is_enabled = clk_prcmu_is_enabled,
+	.recalc_rate = clk_prcmu_recalc_rate,
+};
+
 static struct clk_ops clk_prcmu_opp_gate_ops = {
 	.prepare = clk_prcmu_opp_prepare,
 	.unprepare = clk_prcmu_opp_unprepare,
@@ -228,6 +233,15 @@ struct clk *clk_reg_prcmu_gate(const char *name,
 			&clk_prcmu_gate_ops);
 }
 
+struct clk *clk_reg_prcmu_rate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags)
+{
+	return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
+			&clk_prcmu_rate_ops);
+}
+
 struct clk *clk_reg_prcmu_opp_gate(const char *name,
 				   const char *parent_name,
 				   u8 cg_sel,
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
index 32085aa..836d7d1 100644
--- a/drivers/clk/ux500/clk.h
+++ b/drivers/clk/ux500/clk.h
@@ -35,6 +35,11 @@ struct clk *clk_reg_prcmu_gate(const char *name,
 			       u8 cg_sel,
 			       unsigned long flags);
 
+struct clk *clk_reg_prcmu_rate(const char *name,
+			       const char *parent_name,
+			       u8 cg_sel,
+			       unsigned long flags);
+
 struct clk *clk_reg_prcmu_opp_gate(const char *name,
 				   const char *parent_name,
 				   u8 cg_sel,
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 31 08:21:30 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 31 Aug 2012 14:21:30 +0200
Subject: [PATCH 3/4] mfd: dbx500: Provide a more accurate smp_twd clock
In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346415691-13371-4-git-send-email-ulf.hansson@stericsson.com>

From: Michel Jaouen <michel.jaouen at stericsson.com>

The local timer clock is based on ARM subsystem clock. This patch
obtains a more exact value of that clock by reading PRCMU registers.
Using this increases the accuracy of the local timer events.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
Signed-off-by: Rickard Andersson <rickard.andersson at stericsson.com>
Signed-off-by: Michel Jaouen <michel.jaouen at stericsson.com>
---
 drivers/mfd/db8500-prcmu.c       |   42 ++++++++++++++++++++++++++++++++++++++
 drivers/mfd/dbx500-prcmu-regs.h  |    4 +++-
 include/linux/mfd/dbx500-prcmu.h |    1 +
 3 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 4f74529..e7f9539 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -418,6 +418,9 @@ static struct {
 
 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 
+/* Functions definition */
+static void compute_armss_rate(void);
+
 /* Spinlocks */
 static DEFINE_SPINLOCK(prcmu_lock);
 static DEFINE_SPINLOCK(clkout_lock);
@@ -517,6 +520,7 @@ static struct dsiescclk dsiescclk[3] = {
 	}
 };
 
+
 /*
 * Used by MCDE to setup all necessary PRCMU registers
 */
@@ -1013,6 +1017,7 @@ int db8500_prcmu_set_arm_opp(u8 opp)
 		(mb1_transfer.ack.arm_opp != opp))
 		r = -EIO;
 
+	compute_armss_rate();
 	mutex_unlock(&mb1_transfer.lock);
 
 	return r;
@@ -1612,6 +1617,7 @@ static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
 	if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
 		(val & PRCM_PLL_FREQ_DIV2EN) &&
 		((reg == PRCM_PLLSOC0_FREQ) ||
+		 (reg == PRCM_PLLARM_FREQ) ||
 		 (reg == PRCM_PLLDDR_FREQ))))
 		div *= 2;
 
@@ -1661,6 +1667,39 @@ static unsigned long clock_rate(u8 clock)
 	else
 		return 0;
 }
+static unsigned long latest_armss_rate;
+static unsigned long armss_rate(void)
+{
+	return latest_armss_rate;
+}
+
+static void compute_armss_rate(void)
+{
+	u32 r;
+	unsigned long rate;
+
+	r = readl(PRCM_ARM_CHGCLKREQ);
+
+	if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
+		/* External ARMCLKFIX clock */
+
+		rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
+
+		/* Check PRCM_ARM_CHGCLKREQ divider */
+		if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
+			rate /= 2;
+
+		/* Check PRCM_ARMCLKFIX_MGT divider */
+		r = readl(PRCM_ARMCLKFIX_MGT);
+		r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
+		rate /= r;
+
+	} else {/* ARM PLL */
+		rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
+	}
+
+	latest_armss_rate = rate;
+}
 
 static unsigned long dsiclk_rate(u8 n)
 {
@@ -1707,6 +1746,8 @@ unsigned long prcmu_clock_rate(u8 clock)
 		return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
 	else if (clock == PRCMU_PLLSOC1)
 		return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
+	else if (clock == PRCMU_ARMSS)
+		return armss_rate();
 	else if (clock == PRCMU_PLLDDR)
 		return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
 	else if (clock == PRCMU_PLLDSI)
@@ -2693,6 +2734,7 @@ void __init db8500_prcmu_early_init(void)
 					 handle_simple_irq);
 		set_irq_flags(irq, IRQF_VALID);
 	}
+	compute_armss_rate();
 }
 
 static void __init init_prcm_registers(void)
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6..79c76eb 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -61,7 +61,8 @@
 #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3	0x2
 
 #define PRCM_ARM_CHGCLKREQ	(_PRCMU_BASE + 0x114)
-#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ	0x1
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ	BIT(0)
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL	BIT(16)
 
 #define PRCM_PLLARM_ENABLE	(_PRCMU_BASE + 0x98)
 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE	0x1
@@ -140,6 +141,7 @@
 /* PRCMU clock/PLL/reset registers */
 #define PRCM_PLLSOC0_FREQ	   (_PRCMU_BASE + 0x080)
 #define PRCM_PLLSOC1_FREQ	   (_PRCMU_BASE + 0x084)
+#define PRCM_PLLARM_FREQ	   (_PRCMU_BASE + 0x088)
 #define PRCM_PLLDDR_FREQ	   (_PRCMU_BASE + 0x08C)
 #define PRCM_PLL_FREQ_D_SHIFT	0
 #define PRCM_PLL_FREQ_D_MASK	BITS(0, 7)
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 5b90e94..c410d99 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -136,6 +136,7 @@ enum prcmu_clock {
 	PRCMU_TIMCLK,
 	PRCMU_PLLSOC0,
 	PRCMU_PLLSOC1,
+	PRCMU_ARMSS,
 	PRCMU_PLLDDR,
 	PRCMU_PLLDSI,
 	PRCMU_DSI0CLK,
-- 
1.7.10



From ulf.hansson at stericsson.com  Fri Aug 31 08:21:31 2012
From: ulf.hansson at stericsson.com (Ulf Hansson)
Date: Fri, 31 Aug 2012 14:21:31 +0200
Subject: [PATCH 4/4] clk: ux500: Define smp_twd clock for u8500
In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <1346415691-13371-5-git-send-email-ulf.hansson@stericsson.com>

From: Ulf Hansson <ulf.hansson at linaro.org>

The smp_twd clock is based upon a prcmu_rate clock type
for the PRCMU_ARMSS clock.

Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
---
 drivers/clk/ux500/u8500_clk.c |   12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 5c1fca1..ca4a25e 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -205,12 +205,16 @@ void u8500_clk_init(void)
 	clk_register_clkdev(clk, "dsilp2", "dsilink.2");
 	clk_register_clkdev(clk, "dsilp2", "mcde");
 
+	clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
+				CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
+				CLK_IGNORE_UNUSED);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
 	/*
 	 * FIXME: Add special handled PRCMU clocks here:
-	 * 1. smp_twd, use PRCMU_ARMSS.
-	 * 2. clk_arm, use PRCMU_ARMCLK.
-	 * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
-	 * 4. ab9540_clkout1yuv, see clkout0yuv
+	 * 1. clk_arm, use PRCMU_ARMCLK.
+	 * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
+	 * 3. ab9540_clkout1yuv, see clkout0yuv
 	 */
 
 	/* PRCC P-clocks */
-- 
1.7.10



From lee.jones at linaro.org  Fri Aug 31 08:23:27 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Fri, 31 Aug 2012 13:23:27 +0100
Subject: [PATCH 3/3] i2c: nomadik: Add Device Tree support to the Nomadik
 I2C driver
In-Reply-To: <20120831112258.GA2624@pengutronix.de>
References: <1345734087-21803-1-git-send-email-lee.jones@linaro.org>
 <1345734087-21803-3-git-send-email-lee.jones@linaro.org>
 <20120831112258.GA2624@pengutronix.de>
Message-ID: <20120831122323.GC5962@gmail.com>

Hopefully this is more to your liking:

Author: Lee Jones <lee.jones at linaro.org>
Date:   Mon Aug 6 11:09:57 2012 +0100

    i2c: nomadik: Add Device Tree support to the Nomadik I2C driver
    
    Here we apply the bindings required for successful Device Tree
    probing of the i2c-nomadik driver.
    
    Cc: linux-i2c at vger.kernel.org
    Signed-off-by: Lee Jones <lee.jones at linaro.org>

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 61b00ed..2c85de1 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -25,6 +25,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
 #include <linux/platform_data/i2c-nomadik.h>
+#include <linux/of.h>
 
 #define DRIVER_NAME "nmk-i2c"
 
@@ -920,15 +921,41 @@ static struct nmk_i2c_controller u8500_i2c = {
        .sm             = I2C_FREQ_MODE_FAST,
 };
 
+static void nmk_i2c_of_probe(struct device_node *np,
+                       struct nmk_i2c_controller *pdata)
+{
+       of_property_read_u32(np, "clock-frequency", &pdata->clk_freq);
+
+       /* This driver only supports 'standard' and 'fast' modes of operation. */
+       if (pdata->clk_freq <= 100000)
+               pdata->sm = I2C_FREQ_MODE_STANDARD;
+       else
+               pdata->sm = I2C_FREQ_MODE_FAST;
+}
+
 static atomic_t adapter_id = ATOMIC_INIT(0);
 
 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
 {
        int ret = 0;
        struct nmk_i2c_controller *pdata = adev->dev.platform_data;
+       struct device_node *np = adev->dev.of_node;
        struct nmk_i2c_dev      *dev;
        struct i2c_adapter *adap;
 
+       if (np) {
+               if (!pdata) {
+                       pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL);
+                       if (!pdata) {
+                               ret = -ENOMEM;
+                               goto err_no_mem;
+                       }
+               }
+               /* Provide the default configuration as a base. */
+               pdata = &u8500_i2c;
+               nmk_i2c_of_probe(np, pdata);
+       }
+
        if (!pdata)
                /* No i2c configuration found, using the default. */
                pdata = &u8500_i2c;
diff --git a/include/linux/platform_data/i2c-nomadik.h b/include/linux/platform_data/i2c-nomadik.h
index c2303c3..3a8be9c 100644
--- a/include/linux/platform_data/i2c-nomadik.h
+++ b/include/linux/platform_data/i2c-nomadik.h
@@ -28,7 +28,7 @@ enum i2c_freq_mode {
  * @sm:                speed mode
  */
 struct nmk_i2c_controller {
-       unsigned long   clk_freq;
+       u32             clk_freq;
        unsigned short  slsu;
        unsigned char   tft;
        unsigned char   rft;


From s.hauer at pengutronix.de  Fri Aug 31 09:05:02 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 31 Aug 2012 15:05:02 +0200
Subject: i.MX pwm patches
In-Reply-To: <20120830214547.GC3613@r65073-Latitude-D630>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <20120830214547.GC3613@r65073-Latitude-D630>
Message-ID: <20120831130502.GR26594@pengutronix.de>

On Fri, Aug 31, 2012 at 05:45:49AM +0800, Shawn Guo wrote:
> On Tue, Aug 28, 2012 at 01:48:15PM +0200, Sascha Hauer wrote:
> > Hi All,
> > 
> > The following patches are an overdue work on the i.MX pwm driver.
> > 
> > - introduce SoC specific functions to make the driver easier to maintain
> > - use peripheral clock for pwm output unconditionally
> > - separate the two clocks this module has
> > - enable ipg clock for register accesses, peripheral clock for enabling
> >   the pwm
> > - make the driver safe for calling pwm_config before pwm_enable
> > - Add devicetree support for i.MX53
> > 
> > The platform device support is still implemented using cpu_is_*, I think
> > this can be dropped completely soon
> 
> Anything stops us from doing this right now?  The bonus point of
> cleaning this is that we can remove the #include <mach/hardware.h>
> from the driver, which is helpful for single-kernel project.

The pwm driver currently has no in kernel user, so I'd say yes.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Aug 31 09:07:23 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 31 Aug 2012 15:07:23 +0200
Subject: [PATCH 8/9] ARM i.MX53: Add pwms to dtsi
In-Reply-To: <20120830223219.GF3613@r65073-Latitude-D630>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <1346154504-5623-9-git-send-email-s.hauer@pengutronix.de>
 <20120830223219.GF3613@r65073-Latitude-D630>
Message-ID: <20120831130723.GS26594@pengutronix.de>

On Fri, Aug 31, 2012 at 06:32:20AM +0800, Shawn Guo wrote:
> On Tue, Aug 28, 2012 at 01:48:23PM +0200, Sascha Hauer wrote:
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > 
> > Conflicts:
> > 	arch/arm/mach-imx/clk-imx51-imx53.c
> 
> Yeah, I know you have sorted out conflicts :)

:)

> 
> > ---
> >  arch/arm/boot/dts/imx53.dtsi        |   14 ++++++++++++++
> >  arch/arm/mach-imx/clk-imx51-imx53.c |    4 ++++
> >  2 files changed, 18 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> > index cd37165..7ec17e4 100644
> > --- a/arch/arm/boot/dts/imx53.dtsi
> > +++ b/arch/arm/boot/dts/imx53.dtsi
> > @@ -189,6 +189,20 @@
> >  				status = "disabled";
> >  			};
> >  
> > +			pwm1: pwm at 53fb4000 {
> > +				#pwm-cells = <3>;
> 
> pwm-cells should be 2?

Yes, right. We have a patch internally that allows us to pass a
'inverted' flag to the pwm, hence I accidently have 3 here.

> >  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
> >  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
> >  	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
> > +	clk_register_clkdev(clk[pwm1_ipg_gate], "ipg", "53fb4000.pwm");
> > +	clk_register_clkdev(clk[pwm1_hf_gate], "per", "53fb4000.pwm");
> > +	clk_register_clkdev(clk[pwm2_ipg_gate], "ipg", "53fb8000.pwm");
> > +	clk_register_clkdev(clk[pwm2_hf_gate], "per", "53fb8000.pwm");
> 
> It should be in a separate patch?

Should it? Surely I can do this, I had the feeling though that it
belongs together.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From gururaja.hebbar at ti.com  Fri Aug 31 08:50:58 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 Aug 2012 18:20:58 +0530
Subject: [PATCH 2/3] ASoC: Davinci: pcm: add support for sram-support-less
 platforms
In-Reply-To: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346417459-30042-3-git-send-email-gururaja.hebbar@ti.com>

OMAP2+ platforms (like TI81xx, AM33xx) uses davinci-pcm driver. SRAM is
not needed/used in EDMA transfers for audio on such platforms. However
they do not provide generic SRAM APIs (sram_alloc() and sram_free()). In
such cases the pcm driver cannot be used directly as it results in
compilation failure on OMAP2 platforms.

Fix this by providing a config option to indicate missing SRAM API
support. This config is enabled by default on Davinci platform so as to
not break existing platforms. For OMAP2+ platforms, the config is
disabled.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:100644 100644 9e11a14... 328b463... M	sound/soc/davinci/Kconfig
:100644 100644 93ea3bf... 7ac5a19... M	sound/soc/davinci/davinci-pcm.c
 sound/soc/davinci/Kconfig       |    5 +++++
 sound/soc/davinci/davinci-pcm.c |    8 ++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/sound/soc/davinci/Kconfig b/sound/soc/davinci/Kconfig
index 9e11a14..328b463 100644
--- a/sound/soc/davinci/Kconfig
+++ b/sound/soc/davinci/Kconfig
@@ -15,6 +15,11 @@ config SND_DAVINCI_SOC_MCASP
 config SND_DAVINCI_SOC_VCIF
 	tristate
 
+config SND_DAVINCI_HAVE_SRAM
+	bool
+	default y if ARCH_DAVINCI=y
+	default n if ARCH_OMAP=y
+
 config SND_DAVINCI_SOC_EVM
 	tristate "SoC Audio support for DaVinci DM6446, DM355 or DM365 EVM"
 	depends on SND_DAVINCI_SOC
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index 93ea3bf..7ac5a19 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -23,7 +23,9 @@
 #include <sound/soc.h>
 
 #include <asm/dma.h>
+#if defined(CONFIG_SND_DAVINCI_HAVE_SRAM)
 #include <mach/sram.h>
+#endif
 
 #include "davinci-pcm.h"
 
@@ -259,6 +261,7 @@ static void davinci_pcm_dma_irq(unsigned link, u16 ch_status, void *data)
 	}
 }
 
+#if defined(CONFIG_SND_DAVINCI_HAVE_SRAM)
 static int allocate_sram(struct snd_pcm_substream *substream, unsigned size,
 		struct snd_pcm_hardware *ppcm)
 {
@@ -289,6 +292,7 @@ exit2:
 exit1:
 	return -ENOMEM;
 }
+#endif
 
 /*
  * Only used with ping/pong.
@@ -676,7 +680,9 @@ static int davinci_pcm_open(struct snd_pcm_substream *substream)
 
 	ppcm = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
 			&pcm_hardware_playback : &pcm_hardware_capture;
+#if defined(CONFIG_SND_DAVINCI_HAVE_SRAM)
 	allocate_sram(substream, params->sram_size, ppcm);
+#endif
 	snd_soc_set_runtime_hwparams(substream, ppcm);
 	/* ensure that buffer size is a multiple of period size */
 	ret = snd_pcm_hw_constraint_integer(runtime,
@@ -817,11 +823,13 @@ static void davinci_pcm_free(struct snd_pcm *pcm)
 		dma_free_writecombine(pcm->card->dev, buf->bytes,
 				      buf->area, buf->addr);
 		buf->area = NULL;
+#if defined(CONFIG_SND_DAVINCI_HAVE_SRAM)
 		iram_dma = buf->private_data;
 		if (iram_dma) {
 			sram_free(iram_dma->area, iram_dma->bytes);
 			kfree(iram_dma);
 		}
+#endif
 	}
 }
 
-- 
1.7.1



From gururaja.hebbar at ti.com  Fri Aug 31 08:50:56 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 Aug 2012 18:20:56 +0530
Subject: [PATCH 0/3] ASoC: Davinci: McASP: add support new McASP IP Variant
Message-ID: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>

The OMAP2+ variant of McASP is different from Davinci variant w.r.to some
register offset and missing generic SRAM APIs support

Changes
- Add new MCASP_VERSION_3 to identify new variant. New DT compatible
  "ti,omap2-mcasp-audio" to identify version 3 controller.
- The register offsets are handled depending on the version.
- Provide a config option to indicate missing SRAM API support.

While here, fix a typo caused by recent commit (cf53756 - ASoC: davinci: 
davinci-pcm does not need to be a plaform_driver)

Note:
   DMA parameters (dma fifo offset) are not updated and will be done later.

Hebbar, Gururaja (3):
  ASoC: Davinci: McASP: add support new McASP IP Variant
  ASoC: Davinci: pcm: add support for sram-support-less platforms
  ASoC: Davinci: evm: Fix typo in cpu dai name

 .../bindings/sound/davinci-mcasp-audio.txt         |    1 +
 include/linux/platform_data/davinci_asp.h          |    1 +
 sound/soc/davinci/Kconfig                          |    5 ++
 sound/soc/davinci/davinci-evm.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.c                  |   71 ++++++++++++++++----
 sound/soc/davinci/davinci-pcm.c                    |    8 ++
 6 files changed, 74 insertions(+), 14 deletions(-)



From gururaja.hebbar at ti.com  Fri Aug 31 08:50:59 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 Aug 2012 18:20:59 +0530
Subject: [PATCH 3/3] ASoC: Davinci: evm: Fix typo in cpu dai name
In-Reply-To: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346417459-30042-4-git-send-email-gururaja.hebbar@ti.com>

Fix typo caused by recent commit (cf53756 - ASoC: davinci: davinci-pcm
does not need to be a plaform_driver)

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:100644 100644 ca2a547... 2864f24... M	sound/soc/davinci/davinci-evm.c
 sound/soc/davinci/davinci-evm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index ca2a547..2864f24 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -208,7 +208,7 @@ static struct snd_soc_dai_link dm365_evm_dai = {
 	.cpu_dai_name = "davinci-vcif",
 	.codec_dai_name = "cq93vc-hifi",
 	.codec_name = "cq93vc-codec",
-	.platform_name = "avinci-vcif",
+	.platform_name = "davinci-vcif",
 #endif
 };
 
-- 
1.7.1



From gururaja.hebbar at ti.com  Fri Aug 31 08:50:57 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Fri, 31 Aug 2012 18:20:57 +0530
Subject: [PATCH 1/3] ASoC: Davinci: McASP: add support new McASP IP Variant
In-Reply-To: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
References: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <1346417459-30042-2-git-send-email-gururaja.hebbar@ti.com>

The OMAP2+ variant of McASP is different from Davinci variant w.r.to
some register offset.

Changes
- Add new MCASP_VERSION_3 to identify new variant. New DT compatible
  "ti,omap2-mcasp-audio" to identify version 3 controller.
- The register offsets are handled depending on the version.

Note:
    DMA parameters (dma fifo offset) are not updated and will be done later.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar at ti.com>
---
:100644 100644 e6148ec... 374e145... M	Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
:100644 100644 79c26aa... d0c5825... M	include/linux/platform_data/davinci_asp.h
:100644 100644 c3eae1d... bb6ae9d... M	sound/soc/davinci/davinci-mcasp.c
 .../bindings/sound/davinci-mcasp-audio.txt         |    1 +
 include/linux/platform_data/davinci_asp.h          |    1 +
 sound/soc/davinci/davinci-mcasp.c                  |   71 ++++++++++++++++----
 3 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
index e6148ec..374e145 100644
--- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible :
 	"ti,dm646x-mcasp-audio"	: for DM646x platforms
 	"ti,da830-mcasp-audio"	: for both DA830 & DA850 platforms
+	"ti,omap2-mcasp-audio"	: for OMAP2 platforms (TI81xx, AM33xx)
 
 - reg : Should contain McASP registers offset and length
 - interrupts : Interrupt number for McASP
diff --git a/include/linux/platform_data/davinci_asp.h b/include/linux/platform_data/davinci_asp.h
index 79c26aa..d0c5825 100644
--- a/include/linux/platform_data/davinci_asp.h
+++ b/include/linux/platform_data/davinci_asp.h
@@ -87,6 +87,7 @@ struct snd_platform_data {
 enum {
 	MCASP_VERSION_1 = 0,	/* DM646x */
 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
+	MCASP_VERSION_3,        /* TI81xx/AM33xx */
 };
 
 enum mcbsp_clk_input_pin {
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index c3eae1d..bb6ae9d 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -111,6 +111,10 @@
 #define DAVINCI_MCASP_WFIFOSTS		(0x1014)
 #define DAVINCI_MCASP_RFIFOCTL		(0x1018)
 #define DAVINCI_MCASP_RFIFOSTS		(0x101C)
+#define MCASP_VER3_WFIFOCTL		(0x1000)
+#define MCASP_VER3_WFIFOSTS		(0x1004)
+#define MCASP_VER3_RFIFOCTL		(0x1008)
+#define MCASP_VER3_RFIFOSTS		(0x100C)
 
 /*
  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
@@ -384,18 +388,32 @@ static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
 {
 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		if (dev->txnumevt) {	/* enable FIFO */
-			mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+			if (dev->version == MCASP_VERSION_3) {
+				mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
 								FIFO_ENABLE);
-			mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+				mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
 								FIFO_ENABLE);
+			} else {
+				mcasp_clr_bits(dev->base +
+					DAVINCI_MCASP_WFIFOCTL,	FIFO_ENABLE);
+				mcasp_set_bits(dev->base +
+					DAVINCI_MCASP_WFIFOCTL,	FIFO_ENABLE);
+			}
 		}
 		mcasp_start_tx(dev);
 	} else {
 		if (dev->rxnumevt) {	/* enable FIFO */
-			mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+			if (dev->version == MCASP_VERSION_3) {
+				mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
 								FIFO_ENABLE);
-			mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+				mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
 								FIFO_ENABLE);
+			} else {
+				mcasp_clr_bits(dev->base +
+					DAVINCI_MCASP_RFIFOCTL,	FIFO_ENABLE);
+				mcasp_set_bits(dev->base +
+					DAVINCI_MCASP_RFIFOCTL,	FIFO_ENABLE);
+			}
 		}
 		mcasp_start_rx(dev);
 	}
@@ -416,14 +434,24 @@ static void mcasp_stop_tx(struct davinci_audio_dev *dev)
 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
 {
 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		if (dev->txnumevt)	/* disable FIFO */
-			mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+		if (dev->txnumevt) {	/* disable FIFO */
+			if (dev->version == MCASP_VERSION_3)
+				mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
 								FIFO_ENABLE);
+			else
+				mcasp_clr_bits(dev->base +
+					DAVINCI_MCASP_WFIFOCTL,	FIFO_ENABLE);
+		}
 		mcasp_stop_tx(dev);
 	} else {
-		if (dev->rxnumevt)	/* disable FIFO */
-			mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+		if (dev->rxnumevt) {	/* disable FIFO */
+			if (dev->version == MCASP_VERSION_3)
+				mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
 								FIFO_ENABLE);
+			else
+				mcasp_clr_bits(dev->base +
+					DAVINCI_MCASP_RFIFOCTL,	FIFO_ENABLE);
+		}
 		mcasp_stop_rx(dev);
 	}
 }
@@ -622,20 +650,33 @@ static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
 		if (dev->txnumevt * tx_ser > 64)
 			dev->txnumevt = 1;
 
-		mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
+		if (dev->version == MCASP_VERSION_3) {
+			mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
 								NUMDMA_MASK);
-		mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+			mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
+				((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
+		} else {
+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+							tx_ser,	NUMDMA_MASK);
+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
 				((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
+		}
 	}
 
 	if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
 		if (dev->rxnumevt * rx_ser > 64)
 			dev->rxnumevt = 1;
-
-		mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
+		if (dev->version == MCASP_VERSION_3) {
+			mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
 								NUMDMA_MASK);
-		mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+			mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
 				((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
+		} else {
+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+							rx_ser,	NUMDMA_MASK);
+			mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+				((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
+		}
 	}
 }
 
@@ -874,6 +915,10 @@ static const struct of_device_id mcasp_dt_ids[] = {
 		.compatible = "ti,da830-mcasp-audio",
 		.data = (void *)MCASP_VERSION_2,
 	},
+	{
+		.compatible = "ti,omap2-mcasp-audio",
+		.data = (void *)MCASP_VERSION_3,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
-- 
1.7.1



From shawn.guo at linaro.org  Thu Aug 30 20:16:06 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 08:16:06 +0800
Subject: [PATCH 8/9] ARM i.MX53: Add pwms to dtsi
In-Reply-To: <20120831130723.GS26594@pengutronix.de>
References: <1346154504-5623-1-git-send-email-s.hauer@pengutronix.de>
 <1346154504-5623-9-git-send-email-s.hauer@pengutronix.de>
 <20120830223219.GF3613@r65073-Latitude-D630>
 <20120831130723.GS26594@pengutronix.de>
Message-ID: <20120831001604.GG3613@r65073-Latitude-D630>

On Fri, Aug 31, 2012 at 03:07:23PM +0200, Sascha Hauer wrote:
> > >  	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
> > >  	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
> > >  	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
> > > +	clk_register_clkdev(clk[pwm1_ipg_gate], "ipg", "53fb4000.pwm");
> > > +	clk_register_clkdev(clk[pwm1_hf_gate], "per", "53fb4000.pwm");
> > > +	clk_register_clkdev(clk[pwm2_ipg_gate], "ipg", "53fb8000.pwm");
> > > +	clk_register_clkdev(clk[pwm2_hf_gate], "per", "53fb8000.pwm");
> > 
> > It should be in a separate patch?
> 
> Should it? Surely I can do this, I had the feeling though that it
> belongs together.
> 
>From patch subject, I do not expect these changes in the patch.  It's
okay to have it but we need a more proper patch subject then.  

-- 
Regards,
Shawn


From robherring2 at gmail.com  Fri Aug 31 09:58:49 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 08:58:49 -0500
Subject: [PATCH 2/8] irqdomain: Take interrupt-parent property into account
 if specified
In-Reply-To: <20120831094434.GF13298@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdZMoisfUD_NSkVy2w-jZVUDGn0E8LmvKSWnJ0YRGZO-tQ@mail.gmail.com>
 <20120831094434.GF13298@gmail.com>
Message-ID: <5040C319.5080704@gmail.com>

On 08/31/2012 04:44 AM, Lee Jones wrote:
> On Tue, Aug 14, 2012 at 10:19:08AM +0200, Linus Walleij wrote:
>> On Thu, Aug 9, 2012 at 5:53 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>>> irq_find_host() currently ignores the 'interrupt-parent' property
>>> even if it's specified in the Device Tree. Meaning that a node can
>>> match to a domain in its hierarchy even if it doesn't belong to it.
>>> By searching for the parent first using of_irq_find_parent() we
>>> insist that the 'interrupt-parent' property is taken into account
>>> ensuring a greater chance of returning the correct domain.
>>>
>>> CC: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>>> CC: Grant Likely <grant.likely at secretlab.ca>
>>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> This (with 1/8) is the right solution. Thanks, and I think
>> Mark may want to look at this too since I recognize he asked
>> you to work in this direction.
>>
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Rob, did this get your Ack too?

Acked-by: Rob Herring <rob.herring at calxeda.com>

Rob

> 
> Ben, Grant, Mark, would you like to take a look also?
> 



From maxime.ripard at free-electrons.com  Fri Aug 31 10:00:40 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 31 Aug 2012 16:00:40 +0200
Subject: [PATCH 1/2] ARM: dts: mxs: Add alternative I2C muxing options for
 imx28
In-Reply-To: <1346421641-3765-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1346421641-3765-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1346421641-3765-2-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/imx28.dtsi |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 60d10d7..7d156ee 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -421,6 +421,17 @@
 					fsl,pull-up = <1>;
 				};
 
+				i2c1_pins_a: i2c1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <
+						0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+						0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+					>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
 				saif0_pins_a: saif0 at 0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
-- 
1.7.9.5



From maxime.ripard at free-electrons.com  Fri Aug 31 10:00:39 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 31 Aug 2012 16:00:39 +0200
Subject: [PATCHv2] Introduce the CFA-10049 expansion board
Message-ID: <1346421641-3765-1-git-send-email-maxime.ripard@free-electrons.com>

Hi everyone,

Here is a patchset to introduce the CFA-10049 expansion board to the CFA-10036
module.

This expansion board has a number of ADCs and DACs, stepper drivers, GPIO
expanders, a LCD touchscreen and fans. Support for those will come eventually.

We only support the I2C bus for now, that is used for ADCs behind a i2c muxer
and a GPIO expander.


Thanks,
Maxime



From maxime.ripard at free-electrons.com  Fri Aug 31 10:00:41 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 31 Aug 2012 16:00:41 +0200
Subject: [PATCH 2/2] ARM: dts: mxs: Add the second I2C adapter to the CFA10049
 expansion board
In-Reply-To: <1346421641-3765-1-git-send-email-maxime.ripard@free-electrons.com>
References: <1346421641-3765-1-git-send-email-maxime.ripard@free-electrons.com>
Message-ID: <1346421641-3765-3-git-send-email-maxime.ripard@free-electrons.com>

Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
---
 arch/arm/boot/dts/imx28-cfa10049.dts |   31 +++++++++++++++++++++++++++++++
 arch/arm/mach-mxs/Makefile.boot      |    1 +
 2 files changed, 32 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx28-cfa10049.dts

diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 0000000..e0e4b8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+	model = "Crystalfontz CFA-10049 Board";
+	compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+
+	apb at 80000000 {
+		apbx at 80040000 {
+			i2c1: i2c at 8005a000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c1_pins_a>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 4582999..8bd23a8 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -5,6 +5,7 @@ dtb-y += imx23-evk.dtb \
 	 imx23-stmp378x_devb.dtb \
 	 imx28-apx4devkit.dtb \
 	 imx28-cfa10036.dtb \
+	 imx28-cfa10049.dtb \
 	 imx28-evk.dtb \
 	 imx28-m28evk.dtb \
 	 imx28-tx28.dtb \
-- 
1.7.9.5



From shawn.guo at linaro.org  Thu Aug 30 21:26:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 09:26:29 +0800
Subject: [PATCH v4 1/7] mfd: add syscon driver based on regmap
In-Reply-To: <1346237818-9498-2-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
 <1346237818-9498-2-git-send-email-b29396@freescale.com>
Message-ID: <20120831012626.GA7726@r65073-Latitude-D630>

On Wed, Aug 29, 2012 at 06:56:52PM +0800, Dong Aisheng wrote:
> +config MFD_SYSCON
> +        bool "System Controller Register R/W Based on Regmap"

If the driver only compiles and works for device tree probe, we should
have the following?

	depends on OF

> +        select REGMAP_MMIO
> +        help
> +	  Select this option to enable accessing system control registers
> +	  via regmap.
> +

<snip>

> +struct regmap *syscon_node_to_regmap(struct device_node *np)
> +{
> +	struct syscon *syscon;
> +	struct device *dev;
> +
> +	dev = driver_find_device(&syscon_driver.driver, NULL, np,
> +				 syscon_match);
> +	of_node_put(np);

This looks a little unnatural to me.  Function syscon_node_to_regmap
becomes an API visible to clients, who might never know that np will
be put inside the API.  I'm saying the client may also call of_node_put
to put the node they get.

I think of_node_put should be moved out from here and put into
syscon_node_to_regmap and syscon_regmap_lookup_by_compatible.

Regards,
Shawn

> +
> +	if (!dev)
> +		return ERR_PTR(-EPROBE_DEFER);
> +
> +	syscon = dev_get_drvdata(dev);
> +
> +	return syscon->regmap;
> +}
> +EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
> +
> +struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
> +{
> +	struct device_node *syscon_np;
> +
> +	syscon_np = of_find_compatible_node(NULL, NULL, s);
> +	if (!syscon_np)
> +		return ERR_PTR(-ENODEV);
> +
> +	return syscon_node_to_regmap(syscon_np);
> +}
> +EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
> +
> +struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
> +					const char *property)
> +{
> +	struct device_node *syscon_np;
> +
> +	syscon_np = of_parse_phandle(np, property, 0);
> +	if (!syscon_np)
> +		return ERR_PTR(-ENODEV);
> +
> +	return syscon_node_to_regmap(syscon_np);
> +}
> +EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle);



From plagnioj at jcrosoft.com  Fri Aug 31 10:29:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 Aug 2012 16:29:44 +0200
Subject: [PATCH 3/8] i2c: at91: use an id table for SoC dependent
 parameters
In-Reply-To: <1346404884-18451-4-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346404884-18451-4-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120831142944.GA23867@game.jcrosoft.org>

On 11:21 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Use the id_table to store configuration structures which are depending on
> SoC.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
>  arch/arm/mach-at91/at91rm9200.c          |  2 +-
>  arch/arm/mach-at91/at91rm9200_devices.c  | 11 +----
>  arch/arm/mach-at91/at91sam9260.c         |  3 +-
>  arch/arm/mach-at91/at91sam9260_devices.c |  8 ++-
>  arch/arm/mach-at91/at91sam9261.c         |  3 +-
>  arch/arm/mach-at91/at91sam9261_devices.c | 17 +++----
>  arch/arm/mach-at91/at91sam9263.c         |  2 +-
>  arch/arm/mach-at91/at91sam9263_devices.c |  2 +-
>  arch/arm/mach-at91/at91sam9g45.c         |  4 +-
>  arch/arm/mach-at91/at91sam9g45_devices.c |  4 +-
>  arch/arm/mach-at91/at91sam9rl.c          |  4 +-
>  arch/arm/mach-at91/at91sam9rl_devices.c  |  2 +-
>  drivers/i2c/busses/i2c-at91.c            | 85 +++++++++++++++++++++++++-------
>  13 files changed, 95 insertions(+), 52 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index f2112f9..0bc91e5 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
>  	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
>  	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
> -	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
> +	CLKDEV_CON_DEV_ID(NULL, "at91rm9200_i2c", &twi_clk),
use i2c-xxx as on other drivers

and I do not like to have platform_device_id

as we need to touch the driver to add a new soc

please use platform data

Best Regards,
J.


From shawn.guo at linaro.org  Thu Aug 30 21:39:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 09:39:26 +0800
Subject: [PATCH v4 7/7] mfd: anatop-mfd: remove anatop driver
In-Reply-To: <1346237818-9498-8-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
 <1346237818-9498-8-git-send-email-b29396@freescale.com>
Message-ID: <20120831013924.GB7726@r65073-Latitude-D630>

On Wed, Aug 29, 2012 at 06:56:58PM +0800, Dong Aisheng wrote:
> -config MFD_ANATOP
> -	bool "Support for Freescale i.MX on-chip ANATOP controller"
> -	depends on SOC_IMX6Q
> -	help
> -	  Select this option to enable Freescale i.MX on-chip ANATOP
> -	  MFD controller. This controller embeds regulator and
> -	  thermal devices for Freescale i.MX platforms.
> -

All the occurrences of MFD_ANATOP should be removed too.  I know there
is one in arch/arm/mach-imx/Kconfig.

Regards,
Shawn



From plagnioj at jcrosoft.com  Fri Aug 31 10:41:05 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 Aug 2012 16:41:05 +0200
Subject: [PATCH 7/8] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <1346405077-18620-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346405077-18620-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120831144105.GB23867@game.jcrosoft.org>

On 11:24 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Add twi nodes for atmel SOCs and remove i2c-gpio ones.
Only drop the i2c-gpio on the soc that are kn own to have no issue on the hw
IP. For hte onther one keep both in the dtsi

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri Aug 31 10:42:28 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 Aug 2012 16:42:28 +0200
Subject: [PATCH 8/8] ARM: dts: add twi nodes for atmel boards
In-Reply-To: <1346405096-18660-1-git-send-email-ludovic.desroches@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346405096-18660-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <20120831144228.GC23867@game.jcrosoft.org>

On 11:24 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Use the atmel twi instead of gpio for i2c stuff.
NACK as you do not update al the platform at the same time and break the Calao

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri Aug 31 10:45:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 31 Aug 2012 16:45:06 +0200
Subject: [PATCH 03/10] serial: atmel: add explict mach/gpio.h include
In-Reply-To: <504028CC.9020202@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-4-git-send-email-robherring2@gmail.com>
 <20120829233705.GT18957@n2100.arm.linux.org.uk>
 <504028CC.9020202@gmail.com>
Message-ID: <20120831144506.GD23867@game.jcrosoft.org>

On 22:00 Thu 30 Aug     , Rob Herring wrote:
> On 08/29/2012 06:37 PM, Russell King - ARM Linux wrote:
> > On Wed, Aug 29, 2012 at 05:31:29PM -0500, Rob Herring wrote:
> >> From: Rob Herring <rob.herring at calxeda.com>
> >>
> >> In preparation to remove implicit inclusion of mach/gpio.h, add explicit
> >> include of mach/gpio.h.
> > 
> > Definitely NAK.
> > 
> > What is in the Atmel mach/gpio.h has hardly anything to do with the
> > gpio subsystem (it's more a private gpio implementation).  It should
> > be renamed as such to make it clear (and so it doesn't trigger my
> > sanity filtering.)
> 
> Jean-Christophe, Does your gpio clean-up address this?
yes I've a patch series on my local tree that cleanup this

on at91 we do not need the include/mach/gpio.h

and I do plan to drop most of the stuff in it

Best Regards,
J.


From vkoul at infradead.org  Fri Aug 31 10:53:27 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 20:23:27 +0530
Subject: [PATCH v4 0/2] dmaengine: add support mmp-pdma
In-Reply-To: <CAMj5BkiF6NGwfbHBgS52EHwTzb+z6x60hSDaqLtQXgk7bB8jUg@mail.gmail.com>
References: <1345083806-24588-1-git-send-email-zhangfei.gao@marvell.com>
 <1346364840.15463.1.camel@vkoul-mobl4>
 <CAMj5BkiF6NGwfbHBgS52EHwTzb+z6x60hSDaqLtQXgk7bB8jUg@mail.gmail.com>
Message-ID: <1346424807.15463.11.camel@vkoul-mobl4>

On Fri, 2012-08-31 at 09:10 +0800, zhangfei gao wrote:
> On Fri, Aug 31, 2012 at 6:14 AM, Vinod Koul <vkoul at infradead.org> wrote:
> > On Thu, 2012-08-16 at 10:23 +0800, Zhangfei Gao wrote:
> >
> > What tree is this based on? I do not find
> > Documentation/devicetree/bindings/dma/mmp-dma.txt in my tree or linus's
> > tree??
> >
> 
> The mmp-dma.txt is created by [PATCH v3 1/4] dmaengine: mmp-pdma support.
> The patch set based on linux-next, July 13.
And I cant apply this!!! 

It needs to be based on either dmaengine-next or linus master.

Otherwise this should be sent to tree where this file exists, or drop
the binding and rest can be merged while binding get merged separately,
I would prefer the last approach

-- 
~Vinod Koul
Intel Corp.



From ludovic.desroches at atmel.com  Fri Aug 31 10:46:34 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Fri, 31 Aug 2012 16:46:34 +0200
Subject: [PATCH 7/8] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <20120831144105.GB23867@game.jcrosoft.org>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346405077-18620-1-git-send-email-ludovic.desroches@atmel.com>
 <20120831144105.GB23867@game.jcrosoft.org>
Message-ID: <5040CE4A.7070005@atmel.com>

Le 08/31/2012 04:41 PM, Jean-Christophe PLAGNIOL-VILLARD a ?crit :
> On 11:24 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Add twi nodes for atmel SOCs and remove i2c-gpio ones.
> Only drop the i2c-gpio on the soc that are kn own to have no issue on the hw
> IP. For hte onther one keep both in the dtsi
>

Ok I'll keep it.

Regards

Ludovic

> Best Regards,
> J.
>
>



From dmitry.torokhov at gmail.com  Fri Aug 31 10:50:13 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 31 Aug 2012 07:50:13 -0700
Subject: [PATCH 8/8] input: ab8500-ponkey: Rely on MFD core to convert
 IRQs to virtual
In-Reply-To: <20120831073123.GA13298@gmail.com>
References: <1344527635-6163-1-git-send-email-lee.jones@linaro.org>
 <1344527635-6163-9-git-send-email-lee.jones@linaro.org>
 <CACRpkdZ-HOGy_sdsCQSNOdYTDzHFszk0OySM88TjO-neSJUz0A@mail.gmail.com>
 <20120821092328.GC26899@gmail.com>
 <20120821164244.GA4672@core.coreip.homeip.net>
 <20120830131202.GG14145@gmail.com>
 <20120830230221.GD21501@core.coreip.homeip.net>
 <20120830230323.GE21501@core.coreip.homeip.net>
 <20120831073123.GA13298@gmail.com>
Message-ID: <20120831145012.GA26858@core.coreip.homeip.net>

On Fri, Aug 31, 2012 at 08:31:33AM +0100, Lee Jones wrote:
> On Thu, Aug 30, 2012 at 04:03:23PM -0700, Dmitry Torokhov wrote:
> > On Thu, Aug 30, 2012 at 04:02:21PM -0700, Dmitry Torokhov wrote:
> > > On Thu, Aug 30, 2012 at 02:12:04PM +0100, Lee Jones wrote:
> > > > > Sorry for the delay. Yes, this shoudl be fine, but since it is
> > > > > essentially a revert of the original patch it should be pushed in as
> > > > > such.
> > > > 
> > > > How's this?
> > > > 
> > > 
> > > Excellent.
> > 
> > I assume you will be merging it with the rest of AB8500 patches, right?
> 
> Yes, if that's okay with you of course?

Sure, please go ahead,

Thanks.

-- 
Dmitry


From nicolas.ferre at atmel.com  Fri Aug 31 10:51:44 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 Aug 2012 16:51:44 +0200
Subject: [PATCH 3/8] i2c: at91: use an id table for SoC dependent
 parameters
In-Reply-To: <20120831142944.GA23867@game.jcrosoft.org>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346404884-18451-4-git-send-email-ludovic.desroches@atmel.com>
 <20120831142944.GA23867@game.jcrosoft.org>
Message-ID: <5040CF80.8060201@atmel.com>

On 08/31/2012 04:29 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On 11:21 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Use the id_table to store configuration structures which are depending on
>> SoC.
>>
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>> ---
>>  arch/arm/mach-at91/at91rm9200.c          |  2 +-
>>  arch/arm/mach-at91/at91rm9200_devices.c  | 11 +----
>>  arch/arm/mach-at91/at91sam9260.c         |  3 +-
>>  arch/arm/mach-at91/at91sam9260_devices.c |  8 ++-
>>  arch/arm/mach-at91/at91sam9261.c         |  3 +-
>>  arch/arm/mach-at91/at91sam9261_devices.c | 17 +++----
>>  arch/arm/mach-at91/at91sam9263.c         |  2 +-
>>  arch/arm/mach-at91/at91sam9263_devices.c |  2 +-
>>  arch/arm/mach-at91/at91sam9g45.c         |  4 +-
>>  arch/arm/mach-at91/at91sam9g45_devices.c |  4 +-
>>  arch/arm/mach-at91/at91sam9rl.c          |  4 +-
>>  arch/arm/mach-at91/at91sam9rl_devices.c  |  2 +-
>>  drivers/i2c/busses/i2c-at91.c            | 85 +++++++++++++++++++++++++-------
>>  13 files changed, 95 insertions(+), 52 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
>> index f2112f9..0bc91e5 100644
>> --- a/arch/arm/mach-at91/at91rm9200.c
>> +++ b/arch/arm/mach-at91/at91rm9200.c
>> @@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
>>  	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
>>  	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
>>  	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
>> -	CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk),
>> +	CLKDEV_CON_DEV_ID(NULL, "at91rm9200_i2c", &twi_clk),
> use i2c-xxx as on other drivers
> 
> and I do not like to have platform_device_id

Me, I like it and find this implementation very elegant.

> as we need to touch the driver to add a new soc

So what? We still keep the compatibility if the new SoC has it
compatibility assured with previous revision: there is nothing to modify.

> please use platform data

No, it does not have to be exposed to the user: these data are highly
dependent on the actual hardware (IP revision in fact). So, no need to
mess with platform data.

So I will acknowledge Ludo's patches.

Bye,
-- 
Nicolas Ferre


From hvaibhav at ti.com  Fri Aug 31 10:54:51 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 31 Aug 2012 20:24:51 +0530
Subject: Without MACH_ option Early printk (DEBUG_LL)
Message-ID: <5040D03B.2050304@ti.com>

Hi Russell & Tony,

AM335X EVM (based on AM33XX device) only supports DT boot mode and
doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
baseport submission we had aligned that, we won't create separate EVM
options, killing the board file all-together.

Having said that, the early printk option (DEBUG_LL) is broken, the
auto-generated file "./include/generated/mach-types.h" still refers to
CONFIG_MACH_AM335XEVM option,

#ifdef CONFIG_MACH_AM335XEVM
# ifdef machine_arch_type
#  undef machine_arch_type
#  define machine_arch_type     __machine_arch_type
# else
#  define machine_arch_type     MACH_TYPE_AM335XEVM
# endif
# define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
#else
# define machine_is_am335xevm() (0)
#endif


So I am thinking of changing the config_xxx option to SOC_AM33XX or
ARCH_OMAP2PLUS, something like below,

am335xevm        SOC_AM33XX          AM335XEVM         3589

OR

am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589


Can you comment on this? Based on that I will submit the patch.

Thanks,
Vaibhav


From nicolas.ferre at atmel.com  Fri Aug 31 10:56:20 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 Aug 2012 16:56:20 +0200
Subject: [PATCH 7/8] ARM: dts: add twi nodes for atmel SOCs
In-Reply-To: <20120831144105.GB23867@game.jcrosoft.org>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346405077-18620-1-git-send-email-ludovic.desroches@atmel.com>
 <20120831144105.GB23867@game.jcrosoft.org>
Message-ID: <5040D094.3060306@atmel.com>

On 08/31/2012 04:41 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On 11:24 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Add twi nodes for atmel SOCs and remove i2c-gpio ones.
> Only drop the i2c-gpio on the soc that are kn own to have no issue on the hw
> IP. For hte onther one keep both in the dtsi

Yes, I agree with this.

Bye,
-- 
Nicolas Ferre


From shawn.guo at linaro.org  Thu Aug 30 22:02:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 10:02:48 +0800
Subject: [PATCH v4 2/7] ARM: imx6q: add iomuxc gpr support into syscon
In-Reply-To: <1346237818-9498-3-git-send-email-b29396@freescale.com>
References: <1346237818-9498-1-git-send-email-b29396@freescale.com>
 <1346237818-9498-3-git-send-email-b29396@freescale.com>
Message-ID: <20120831020247.GC7726@r65073-Latitude-D630>

On Wed, Aug 29, 2012 at 06:56:53PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Include headfile for easy using.
> 
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  arch/arm/boot/dts/imx6q.dtsi         |    5 +
>  include/linux/fsl/imx6q-iomuxc-gpr.h |  319 ++++++++++++++++++++++++++++++++++

I assume that all the users of this header file are imx6q syscon
clients.  In that case, this header belongs to mfd/syscon subsystem.

I have been told by people that it was a mistake to create
include/linux/fsl.  Each header in include/linux should go to
respective subsystem sub-directory.  For this particular case,
it should be include/linux/mfd or include/linux/mfd/syscon even
better, IMO.

<snip>

> +#define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
> +#define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
> +
> +#endif /* !__LINUX_IMX6Q_IOMUXC_GPR_H */

Nit: why do we have a "!" there?

-- 
Regards,
Shawn



From nicolas.ferre at atmel.com  Fri Aug 31 11:07:10 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 31 Aug 2012 17:07:10 +0200
Subject: [PATCH 8/8] ARM: dts: add twi nodes for atmel boards
In-Reply-To: <20120831144228.GC23867@game.jcrosoft.org>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346405096-18660-1-git-send-email-ludovic.desroches@atmel.com>
 <20120831144228.GC23867@game.jcrosoft.org>
Message-ID: <5040D31E.8040306@atmel.com>

On 08/31/2012 04:42 PM, Jean-Christophe PLAGNIOL-VILLARD :
> On 11:24 Fri 31 Aug     , ludovic.desroches at atmel.com wrote:
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>>
>> Use the atmel twi instead of gpio for i2c stuff.
> NACK as you do not update al the platform at the same time and break the Calao

Yes, Ludovic shall keep i2c-gpio at the side of the new twi driver.

But for the platform, the platform maintainer will have to choose the
one or the other.

Bye,
-- 
Nicolas Ferre


From shawn.guo at linaro.org  Thu Aug 30 22:14:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 10:14:24 +0800
Subject: [PATCH v2 2/2] tty: serial: imx: don't reinit clock in
 imx_setup_ufcr()
In-Reply-To: <1346400167-24669-1-git-send-email-dirk.behme@de.bosch.com>
References: <1346400167-24669-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20120831021422.GD7726@r65073-Latitude-D630>

On Fri, Aug 31, 2012 at 10:02:47AM +0200, Dirk Behme wrote:
> Remove the clock configuration from imx_setup_ufcr(). This
> isn't needed here and will cause garbage output if done.
> 
> To be be sure that we only touch the bits we want (TXTL and RXTL)
> we have to mask out all other bits of the UFCR register. Add
> one non-existing bit macro for this, too (bit 6, DCEDTE on i.MX6).
> 
> Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>
> CC: Shawn Guo <shawn.guo at linaro.org>
> CC: Sascha Hauer <s.hauer at pengutronix.de>
> CC: Troy Kisky <troy.kisky at boundarydevices.com>
> CC: Xinyu Chen <xinyu.chen at freescale.com>
> CC: <stable at vger.kernel.org>

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> ---
> Changes in v2: Instead of disabling imx_setup_ufcr() with an
> ifndef CONFIG_SERIAL_CORE_CONSOLE, remove the unneeded clock 
> configuration from imx_setup_ufcr() itself as proposed by Troy Kisky.
> 
> Note: If this patch is accepted, it should go to the same stable
> kernels as patch #1 of this series. So most probably 3.4 and 3.5.

In such cases, you should repost the series instead of this patch only,
so that maintainer can apply them a little easier.  Let's see if
Greg is fine to apply patch #1 from the early post and #2 from here.

-- 
Regards,
Shawn



From b-cousson at ti.com  Fri Aug 31 11:24:53 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 Aug 2012 17:24:53 +0200
Subject: [RFC PATCH] ARM: OMAP2+: omap-device: Do not overwrite resources
 allocated by OF layer
In-Reply-To: <1346233691-10294-1-git-send-email-hvaibhav@ti.com>
References: <1346233691-10294-1-git-send-email-hvaibhav@ti.com>
Message-ID: <5040D745.5010909@ti.com>

Hi Vaibhav,

On 08/29/2012 11:48 AM, Vaibhav Hiremath wrote:
> With the new devices (like, AM33XX and OMAP5) we now only support
> DT boot mode of operation and now it is the time to start killing
> slowly the dependency on hwmod, so with this patch, we are starting
> with device resources.

Thanks for working on that.

> The idea here is implemented considering to both boot modes -
>   - DT boot mode
>     OF framework will construct the resource structure (currently
>     does for MEM & IRQ resource) and we should respect/use these
>     resources, killing hwmod dependency.
>     If pdev->num_resources > 0, we assume that MEM & IRQ resources
>     have been allocated by OF layer already (through DTB).
> 
>     Once DMA resource is available from OF layer, we should
>     kill filling any resources from hwmod.

Yeap, I did a similar patch some months ago and decided to drop it
because I was expected the DMA binding to be there and wanted to avoid
adding more code that we are going to remove later.

The other potential issue is that when the binding will be there, we
will have to update all the drivers and DTS first before being able to
change the hwmod code from hwmod DMA to DTS DMA.
I was thinking of something smoother that will check if DMA is in DTS
and fall back to hwmod if not to avoid that.
But again, I'm not sure it worth the effort.

>   - Non-DT boot mode
>     Here, pdev->num_resources = 0, and we should get all the
>     resources from hwmod (following existing steps)
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Kevin Hilman <khilman at ti.com>
> ---
> This patch is tested on BeagleBone and AM37xEVM.

I'll try to do more testing on Panda next week.

> Why RFC?
> Still we have function duplication omap_device_fill_resources() and
> omap_device_fill_dma_resources(), we can actually split the function
> into 3 resources and avoid duplication -
>   - omap_device_fill_dma_resources()
>   - omap_device_fill_mem_resources()
>   - omap_device_fill_irq_resources()
> 
> Actually I wanted to clean it further but thought of getting
> feedback first and then proceed further.

Well, that's anyway temporary code that should be gone in 6 months from
now (ideally). So that looks pretty good to me.

>  arch/arm/mach-omap2/omap_hwmod.c             |   27 ++++++++++
>  arch/arm/plat-omap/include/plat/omap_hwmod.h |    1 +
>  arch/arm/plat-omap/omap_device.c             |   72 +++++++++++++++++++++----
>  3 files changed, 88 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 31ec283..edabfb3 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -3330,6 +3330,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
>  }
> 
>  /**
> + * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
> + * @oh: struct omap_hwmod *
> + * @res: pointer to the array of struct resource to fill
> + *
> + * Fill the struct resource array @res with dma resource data from the
> + * omap_hwmod @oh.  Intended to be called by code that registers
> + * omap_devices.  See also omap_hwmod_count_resources().  Returns the
> + * number of array elements filled.
> + */
> +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
> +{
> +	int i, sdma_reqs_cnt;
> +	int r = 0;
> +
> +	sdma_reqs_cnt = _count_sdma_reqs(oh);
> +	for (i = 0; i < sdma_reqs_cnt; i++) {
> +		(res + r)->name = (oh->sdma_reqs + i)->name;
> +		(res + r)->start = (oh->sdma_reqs + i)->dma_req;
> +		(res + r)->end = (oh->sdma_reqs + i)->dma_req;
> +		(res + r)->flags = IORESOURCE_DMA;
> +		r++;
> +	}
> +
> +	return r;
> +}
> +
> +/**
>   * omap_hwmod_get_resource_byname - fetch IP block integration data by name
>   * @oh: struct omap_hwmod * to operate on
>   * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
> diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> index 9b9646c..0533073 100644
> --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
> +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> @@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
> 
>  int omap_hwmod_count_resources(struct omap_hwmod *oh);
>  int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
> +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
>  int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
>  				   const char *name, struct resource *res);
> 
> diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
> index c490240..fd15a3a 100644
> --- a/arch/arm/plat-omap/omap_device.c
> +++ b/arch/arm/plat-omap/omap_device.c
> @@ -486,6 +486,33 @@ static int omap_device_fill_resources(struct omap_device *od,
>  }
> 
>  /**
> + * omap_device_fill_dma_resources - fill in array of struct resource with dma resources
> + * @od: struct omap_device *
> + * @res: pointer to an array of struct resource to be filled in
> + *
> + * Populate one or more empty struct resource pointed to by @res with
> + * the dma resource data for this omap_device @od.  Used by
> + * omap_device_alloc() after calling omap_device_count_resources().
> + *
> + * Ideally this function would not be needed at all.  If we have
> + * mechanism to get dma resources from DT.
> + *
> + * Returns 0.
> + */
> +static int omap_device_fill_dma_resources(struct omap_device *od,
> +				      struct resource *res)
> +{
> +	int i, r;
> +
> +	for (i = 0; i < od->hwmods_cnt; i++) {
> +		r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
> +		res += r;
> +	}
> +
> +	return 0;
> +}
> +
> +/**
>   * omap_device_alloc - allocate an omap_device
>   * @pdev: platform_device that will be included in this omap_device
>   * @oh: ptr to the single omap_hwmod that backs this omap_device
> @@ -524,24 +551,45 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
>  	od->hwmods = hwmods;
>  	od->pdev = pdev;
> 
> +	res_count = omap_device_count_resources(od);
>  	/*
> -	 * HACK: Ideally the resources from DT should match, and hwmod
> -	 * should just add the missing ones. Since the name is not
> -	 * properly populated by DT, stick to hwmod resources only.
> +	 * DT Boot:
> +	 *   OF framework will construct the resource structure (currently
> +	 *   does for MEM & IRQ resource) and we should respect/use these
> +	 *   resources, killing hwmod dependency.
> +	 *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
> +	 *   have been allocated by OF layer already (through DTB).
> +	 *
> +	 * Non-DT Boot:
> +	 *   Here, pdev->num_resources = 0, and we should get all the
> +	 *   resources from hwmod.
> +	 *
> +	 * TODO: Once DMA resource is available from OF layer, we should
> +	 *   kill filling any resources from hwmod.
>  	 */
> -	if (pdev->num_resources && pdev->resource)
> -		dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
> -			__func__, pdev->num_resources);
> -
> -	res_count = omap_device_count_resources(od);
> -	if (res_count > 0) {
> -		dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
> -			__func__, res_count);
> +	if (res_count > pdev->num_resources) {
> +		/* Allocate resources memory to account for new resources */
>  		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
>  		if (!res)
>  			goto oda_exit3;
> 
> -		omap_device_fill_resources(od, res);
> +		/*
> +		 * If pdev->num_resources > 0, then assume that,
> +		 * MEM and IRQ resources will only come from DT and only
> +		 * fill DMA resource from hwmod layer.
> +		 */
> +		if (pdev->num_resources && pdev->resource) {
> +			dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
> +					__func__, res_count);
> +			memcpy(res, pdev->resource,
> +				sizeof(struct resource) * pdev->num_resources);
> +			omap_device_fill_dma_resources(od,
> +					&res[pdev->num_resources]);
> +		} else {
> +			dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
> +					__func__, res_count);
> +			omap_device_fill_resources(od, res);
> +		}

Considering the temporary aspect of that, I'm more than fine with that
approach.

BTW, did you attend the discussion about the DMA binding during PLC?
Is this going to be finalized soon?

Thanks,
Benoit


From shawn.guo at linaro.org  Thu Aug 30 22:35:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 10:35:20 +0800
Subject: [PATCH] spi/imx: set the inactive state of the clock according
 to the clock polarity
In-Reply-To: <1346403311-25080-1-git-send-email-dirk.behme@de.bosch.com>
References: <1346403311-25080-1-git-send-email-dirk.behme@de.bosch.com>
Message-ID: <20120831023518.GE7726@r65073-Latitude-D630>

Copy Uwe ...

On Fri, Aug 31, 2012 at 10:55:11AM +0200, Dirk Behme wrote:
> From: Knut Wohlrab <knut.wohlrab at de.bosch.com>
> 
> There are SPI devices which need a SPI clock with active low polarity and
> high inactive state.
> 
> Add the setting of the inactive state ECSPIx_CONFIGREG:SCLK CTL
> according to the clock polarity ECSPIx_CONFIGREG:SCLK POL:
> 
> DT without "spi-cpol" = 0 = clock active high polarity = inactive state low
> DT with    "spi-cpol" = 1 = clock active low  polarity = inactive state high
> 
> Signed-off-by: Knut Wohlrab <knut.wohlrab at de.bosch.com>
> ---
> 
> Question: Are there real world examples for a need of an individual setting of
> clock polarity/inactive state?

I'm less concerned about that.  We can always patch the driver when
the real world example occurs?

Regards,
Shawn

> 
>  drivers/spi/spi-imx.c |    6 ++++--
>  1 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
> index e834ff8..d64655b 100644
> --- a/drivers/spi/spi-imx.c
> +++ b/drivers/spi/spi-imx.c
> @@ -197,6 +197,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
>  #define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
>  #define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
>  #define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
> +#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
>  
>  #define MX51_ECSPI_INT		0x10
>  #define MX51_ECSPI_INT_TEEN		(1 <<  0)
> @@ -287,9 +288,10 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
>  	if (config->mode & SPI_CPHA)
>  		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
>  
> -	if (config->mode & SPI_CPOL)
> +	if (config->mode & SPI_CPOL) {
>  		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
> -
> +		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
> +	}
>  	if (config->mode & SPI_CS_HIGH)
>  		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
>  
> -- 
> 1.7.0.4
> 



From hvaibhav at ti.com  Fri Aug 31 11:36:00 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 31 Aug 2012 15:36:00 +0000
Subject: [RFC PATCH] ARM: OMAP2+: omap-device: Do not overwrite
 resources allocated by OF layer
In-Reply-To: <5040D745.5010909@ti.com>
References: <1346233691-10294-1-git-send-email-hvaibhav@ti.com>
 <5040D745.5010909@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9EA8E@DBDE01.ent.ti.com>

On Fri, Aug 31, 2012 at 20:54:53, Cousson, Benoit wrote:
> Hi Vaibhav,
> 
> On 08/29/2012 11:48 AM, Vaibhav Hiremath wrote:
> > With the new devices (like, AM33XX and OMAP5) we now only support
> > DT boot mode of operation and now it is the time to start killing
> > slowly the dependency on hwmod, so with this patch, we are starting
> > with device resources.
> 
> Thanks for working on that.
> 
> > The idea here is implemented considering to both boot modes -
> >   - DT boot mode
> >     OF framework will construct the resource structure (currently
> >     does for MEM & IRQ resource) and we should respect/use these
> >     resources, killing hwmod dependency.
> >     If pdev->num_resources > 0, we assume that MEM & IRQ resources
> >     have been allocated by OF layer already (through DTB).
> > 
> >     Once DMA resource is available from OF layer, we should
> >     kill filling any resources from hwmod.
> 
> Yeap, I did a similar patch some months ago and decided to drop it
> because I was expected the DMA binding to be there and wanted to avoid
> adding more code that we are going to remove later.
> 
> The other potential issue is that when the binding will be there, we
> will have to update all the drivers and DTS first before being able to
> change the hwmod code from hwmod DMA to DTS DMA.
> I was thinking of something smoother that will check if DMA is in DTS
> and fall back to hwmod if not to avoid that.
> But again, I'm not sure it worth the effort.
> 
> >   - Non-DT boot mode
> >     Here, pdev->num_resources = 0, and we should get all the
> >     resources from hwmod (following existing steps)
> > 
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Paul Walmsley <paul at pwsan.com>
> > Cc: Kevin Hilman <khilman at ti.com>
> > ---
> > This patch is tested on BeagleBone and AM37xEVM.
> 
> I'll try to do more testing on Panda next week.
> 

Thanks a lot.

> > Why RFC?
> > Still we have function duplication omap_device_fill_resources() and
> > omap_device_fill_dma_resources(), we can actually split the function
> > into 3 resources and avoid duplication -
> >   - omap_device_fill_dma_resources()
> >   - omap_device_fill_mem_resources()
> >   - omap_device_fill_irq_resources()
> > 
> > Actually I wanted to clean it further but thought of getting
> > feedback first and then proceed further.
> 
> Well, that's anyway temporary code that should be gone in 6 months from
> now (ideally). So that looks pretty good to me.
> 
> >  arch/arm/mach-omap2/omap_hwmod.c             |   27 ++++++++++
> >  arch/arm/plat-omap/include/plat/omap_hwmod.h |    1 +
> >  arch/arm/plat-omap/omap_device.c             |   72 +++++++++++++++++++++----
> >  3 files changed, 88 insertions(+), 12 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> > index 31ec283..edabfb3 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod.c
> > @@ -3330,6 +3330,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
> >  }
> > 
> >  /**
> > + * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
> > + * @oh: struct omap_hwmod *
> > + * @res: pointer to the array of struct resource to fill
> > + *
> > + * Fill the struct resource array @res with dma resource data from the
> > + * omap_hwmod @oh.  Intended to be called by code that registers
> > + * omap_devices.  See also omap_hwmod_count_resources().  Returns the
> > + * number of array elements filled.
> > + */
> > +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
> > +{
> > +	int i, sdma_reqs_cnt;
> > +	int r = 0;
> > +
> > +	sdma_reqs_cnt = _count_sdma_reqs(oh);
> > +	for (i = 0; i < sdma_reqs_cnt; i++) {
> > +		(res + r)->name = (oh->sdma_reqs + i)->name;
> > +		(res + r)->start = (oh->sdma_reqs + i)->dma_req;
> > +		(res + r)->end = (oh->sdma_reqs + i)->dma_req;
> > +		(res + r)->flags = IORESOURCE_DMA;
> > +		r++;
> > +	}
> > +
> > +	return r;
> > +}
> > +
> > +/**
> >   * omap_hwmod_get_resource_byname - fetch IP block integration data by name
> >   * @oh: struct omap_hwmod * to operate on
> >   * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
> > diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > index 9b9646c..0533073 100644
> > --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > @@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
> > 
> >  int omap_hwmod_count_resources(struct omap_hwmod *oh);
> >  int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
> > +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
> >  int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
> >  				   const char *name, struct resource *res);
> > 
> > diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
> > index c490240..fd15a3a 100644
> > --- a/arch/arm/plat-omap/omap_device.c
> > +++ b/arch/arm/plat-omap/omap_device.c
> > @@ -486,6 +486,33 @@ static int omap_device_fill_resources(struct omap_device *od,
> >  }
> > 
> >  /**
> > + * omap_device_fill_dma_resources - fill in array of struct resource with dma resources
> > + * @od: struct omap_device *
> > + * @res: pointer to an array of struct resource to be filled in
> > + *
> > + * Populate one or more empty struct resource pointed to by @res with
> > + * the dma resource data for this omap_device @od.  Used by
> > + * omap_device_alloc() after calling omap_device_count_resources().
> > + *
> > + * Ideally this function would not be needed at all.  If we have
> > + * mechanism to get dma resources from DT.
> > + *
> > + * Returns 0.
> > + */
> > +static int omap_device_fill_dma_resources(struct omap_device *od,
> > +				      struct resource *res)
> > +{
> > +	int i, r;
> > +
> > +	for (i = 0; i < od->hwmods_cnt; i++) {
> > +		r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
> > +		res += r;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> >   * omap_device_alloc - allocate an omap_device
> >   * @pdev: platform_device that will be included in this omap_device
> >   * @oh: ptr to the single omap_hwmod that backs this omap_device
> > @@ -524,24 +551,45 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
> >  	od->hwmods = hwmods;
> >  	od->pdev = pdev;
> > 
> > +	res_count = omap_device_count_resources(od);
> >  	/*
> > -	 * HACK: Ideally the resources from DT should match, and hwmod
> > -	 * should just add the missing ones. Since the name is not
> > -	 * properly populated by DT, stick to hwmod resources only.
> > +	 * DT Boot:
> > +	 *   OF framework will construct the resource structure (currently
> > +	 *   does for MEM & IRQ resource) and we should respect/use these
> > +	 *   resources, killing hwmod dependency.
> > +	 *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
> > +	 *   have been allocated by OF layer already (through DTB).
> > +	 *
> > +	 * Non-DT Boot:
> > +	 *   Here, pdev->num_resources = 0, and we should get all the
> > +	 *   resources from hwmod.
> > +	 *
> > +	 * TODO: Once DMA resource is available from OF layer, we should
> > +	 *   kill filling any resources from hwmod.
> >  	 */
> > -	if (pdev->num_resources && pdev->resource)
> > -		dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
> > -			__func__, pdev->num_resources);
> > -
> > -	res_count = omap_device_count_resources(od);
> > -	if (res_count > 0) {
> > -		dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
> > -			__func__, res_count);
> > +	if (res_count > pdev->num_resources) {
> > +		/* Allocate resources memory to account for new resources */
> >  		res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
> >  		if (!res)
> >  			goto oda_exit3;
> > 
> > -		omap_device_fill_resources(od, res);
> > +		/*
> > +		 * If pdev->num_resources > 0, then assume that,
> > +		 * MEM and IRQ resources will only come from DT and only
> > +		 * fill DMA resource from hwmod layer.
> > +		 */
> > +		if (pdev->num_resources && pdev->resource) {
> > +			dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
> > +					__func__, res_count);
> > +			memcpy(res, pdev->resource,
> > +				sizeof(struct resource) * pdev->num_resources);
> > +			omap_device_fill_dma_resources(od,
> > +					&res[pdev->num_resources]);
> > +		} else {
> > +			dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
> > +					__func__, res_count);
> > +			omap_device_fill_resources(od, res);
> > +		}
> 
> Considering the temporary aspect of that, I'm more than fine with that
> approach.
> 

Thanks, once you test it on other platforms and based on observation we can 
merge this patch.

> BTW, did you attend the discussion about the DMA binding during PLC?
> Is this going to be finalized soon?
> 

I think you are getting confused between Vaibhav B and Vaibhav H :)
We have two Vaibhav's roaming around here ;-)


I was not there during LPC this time, it was Vaibhav B who attended it.
I will sync up with him and try to get more info on it.

Thanks,
Vaibhav



From tony at atomide.com  Fri Aug 31 11:36:02 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 08:36:02 -0700
Subject: [PATCH 0/9] Clean up hardcoded IRQs for mach-omap2, enable
 SPARSE_IRQ, plaform_data/gpio-omap.h
In-Reply-To: <5040528E.80509@gmail.com>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <5040528E.80509@gmail.com>
Message-ID: <20120831153601.GJ1303@atomide.com>

* Rob Herring <robherring2 at gmail.com> [120830 22:59]:
> On 08/30/2012 07:52 PM, Tony Lindgren wrote:
> > Hi all,
> > 
> > Here's the first set of omap header clean-up patches needed for single
> > zImage support. This series is based v3.6-rc3 and the following patches
> > to avoid merge conflicts with the includes:
> > 
> > - Arnd's patch "ARM: omap: move platform_data definitions"
> > - Igor's series "ARM: OMAP: cleanup plat/board.h file"
> > - Afzal's series "Prepare for GPMC driver conversion (w.r.t MTD)"
> > 
> 
> Looks like I can drop my omap gpio changes with this. Do you have a git
> tree with this?

Yes no need for those changes for omap :) I have not pushed out any
branch yet, I'm waiting on the scripted platform data move Arnd announced
later on in the "[PATCH 4/4] [RFC] ARM: treewide: manually change more"
thread that are now in the arm-soc tree testing/platform-data branch.

Regards,

Tony


From jason at lakedaemon.net  Fri Aug 31 11:38:52 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 Aug 2012 11:38:52 -0400
Subject: [PATCH] ARM: Kirkwood: Fix 'SZ_1M' undeclared here for
 db88f6281-bp-setup.c
In-Reply-To: <20120831054734.GA30111@lunn.ch>
References: <1346305152-14618-1-git-send-email-andrew@lunn.ch>
 <20120830171236.GS19437@titan.lakedaemon.net>
 <20120830180853.GP9886@lunn.ch>
 <20120830185050.GZ19437@titan.lakedaemon.net>
 <20120831054734.GA30111@lunn.ch>
Message-ID: <20120831153852.GG19437@titan.lakedaemon.net>

On Fri, Aug 31, 2012 at 07:47:34AM +0200, Andrew Lunn wrote:
> On Thu, Aug 30, 2012 at 02:50:50PM -0400, Jason Cooper wrote:
> > On Thu, Aug 30, 2012 at 08:08:53PM +0200, Andrew Lunn wrote:
> > > On Thu, Aug 30, 2012 at 01:12:36PM -0400, Jason Cooper wrote:
> > > > On Thu, Aug 30, 2012 at 07:39:12AM +0200, Andrew Lunn wrote:
> > > > > Linux-next has failed to compile for kirkwood since 23 August with:
> > > > > 
> > > > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function)
> > > > > arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function)
> > > > > 
> > > > > Add missing <linux/sizes.h>
> > > > > 
> > > > > Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> > > > 
> > > > Applied to: fixes-for-v3.6
> > > > 
> > > > Also, I added a CC for stable so greg can pick it up.
> > > 
> > > Stable does not need it. As i said, it only broke 23 August with
> > > linux-next. So this is needed for only 3.7.
> > 
> > Do we know caused the break?  Is it a fix destined for -stable?
> 
> Hi Jason
> 
> If im groking the output from gcc -E correctly, it was this change:
> 
> http://git.kernel.org/?p=linux/kernel/git/next/linux-next.git;a=commitdiff;h=8f039ba3191e67bf48e560f5737d0c285720d4d8
> 
> The #include <asm/memory.h> has been dropped, and its from there that
> it was getting <linux/sizes.h>.
> 
> This does not look like a change that will get backported to anything
> earlier than 3.7.

Ok, Arnd and Olof haven't pulled yet, so I'll issue a new request
without the Cc -stable.

thx,

Jason.


From tony at atomide.com  Fri Aug 31 11:39:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 08:39:22 -0700
Subject: [PATCH 08/10] ARM: omap2: add explict mach/gpio.h includes
In-Reply-To: <1346279496-26286-9-git-send-email-robherring2@gmail.com>
References: <1346279496-26286-1-git-send-email-robherring2@gmail.com>
 <1346279496-26286-9-git-send-email-robherring2@gmail.com>
Message-ID: <20120831153921.GK1303@atomide.com>

* Rob Herring <robherring2 at gmail.com> [120829 15:32]:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove implicit inclusion of mach/gpio.h, add explict
> include of mach/gpio.h.

Just for reference, as Rob already mentioned, these should no longer be
needed for omaps after the "Clean up hardcoded IRQs for mach-omap2,
enable SPARSE_IRQ, plaform_data/gpio-omap.h" series I posted yesterday.

Regards,

Tony


From b-cousson at ti.com  Fri Aug 31 11:42:01 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 31 Aug 2012 17:42:01 +0200
Subject: [RFC PATCH] ARM: OMAP2+: omap-device: Do not overwrite resources
 allocated by OF layer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9EA8E@DBDE01.ent.ti.com>
References: <1346233691-10294-1-git-send-email-hvaibhav@ti.com>
 <5040D745.5010909@ti.com>
 <79CD15C6BA57404B839C016229A409A83EA9EA8E@DBDE01.ent.ti.com>
Message-ID: <5040DB49.9000403@ti.com>

On 08/31/2012 05:36 PM, Hiremath, Vaibhav wrote:
> On Fri, Aug 31, 2012 at 20:54:53, Cousson, Benoit wrote:
...
> I think you are getting confused between Vaibhav B and Vaibhav H :)
> We have two Vaibhav's roaming around here ;-)

Oops, sorry, this is the very first time I realized that two different
Vaibhav were sending patches on very similar topic...
That's why you were so good generating a lot of patches :-) You have a
dual channel of patches :-)

> I was not there during LPC this time, it was Vaibhav B who attended it.
> I will sync up with him and try to get more info on it.

Sorry again for the confusion.

Thanks,
Benoit


From jason at lakedaemon.net  Fri Aug 31 11:43:18 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 Aug 2012 11:43:18 -0400
Subject: [GIT PULL] kirkwood fix for v3.6
In-Reply-To: <20120830171428.GT19437@titan.lakedaemon.net>
References: <20120830171428.GT19437@titan.lakedaemon.net>
Message-ID: <20120831154318.GH19437@titan.lakedaemon.net>

On Thu, Aug 30, 2012 at 01:14:28PM -0400, Jason Cooper wrote:
> The following changes since commit b74ffd85e32d44e8ed405a2a0a175ef4cd39cf67:
> 
>   ARM: Kirkwood: fix Makefile.boot (2012-08-15 13:58:52 +0000)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6
> 
> Andrew Lunn (1):
>       ARM: Kirkwood: Fix 'SZ_1M' undeclared here for db88f6281-bp-setup.c
> 
>  arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)

Arnd, Olof,

I'm going to issue a v2 for this.  Andrew has determined that this
does not need to go to stable.

thx,

Jason.


From jason at lakedaemon.net  Fri Aug 31 11:50:40 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 31 Aug 2012 11:50:40 -0400
Subject: [GIT PULL V2] kirkwood fix for v3.6
In-Reply-To: <20120830171428.GT19437@titan.lakedaemon.net>
References: <20120830171428.GT19437@titan.lakedaemon.net>
Message-ID: <20120831155039.GI19437@titan.lakedaemon.net>

The following changes since commit b74ffd85e32d44e8ed405a2a0a175ef4cd39cf67:

  ARM: Kirkwood: fix Makefile.boot (2012-08-15 13:58:52 +0000)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux.git fixes-for-v3.6-v2

Andrew Lunn (1):
      ARM: Kirkwood: Fix 'SZ_1M' undeclared here for db88f6281-bp-setup.c

 arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)


From tony at atomide.com  Fri Aug 31 11:52:26 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 08:52:26 -0700
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <5040D03B.2050304@ti.com>
References: <5040D03B.2050304@ti.com>
Message-ID: <20120831155226.GL1303@atomide.com>

* Vaibhav Hiremath <hvaibhav at ti.com> [120831 07:55]:
> Hi Russell & Tony,
> 
> AM335X EVM (based on AM33XX device) only supports DT boot mode and
> doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> baseport submission we had aligned that, we won't create separate EVM
> options, killing the board file all-together.
> 
> Having said that, the early printk option (DEBUG_LL) is broken, the
> auto-generated file "./include/generated/mach-types.h" still refers to
> CONFIG_MACH_AM335XEVM option,

The way we're heading is that the DEBUG_LL options will only work for
one hardcoded machine where you need to select the uart type and address
in Kconfig. Or just patch it in.
 
> #ifdef CONFIG_MACH_AM335XEVM
> # ifdef machine_arch_type
> #  undef machine_arch_type
> #  define machine_arch_type     __machine_arch_type
> # else
> #  define machine_arch_type     MACH_TYPE_AM335XEVM
> # endif
> # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> #else
> # define machine_is_am335xevm() (0)
> #endif
> 
> 
> So I am thinking of changing the config_xxx option to SOC_AM33XX or
> ARCH_OMAP2PLUS, something like below,
> 
> am335xevm        SOC_AM33XX          AM335XEVM         3589
> 
> OR
> 
> am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589
> 
> 
> Can you comment on this? Based on that I will submit the patch.

I think that would at minimum break things for autogenerated
mach-types.h where if only some other non-am335xevm machine is
selected (like omap-generic) things don't get optimized out any
longer as they currently do.

Regards,

Tony


From koen at dominion.thruhere.net  Fri Aug 31 11:53:18 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Fri, 31 Aug 2012 17:53:18 +0200
Subject: [PATCH RESEND v4 2/3] arm/dts: AM33XX: Configure pinmuxs for user
 leds control on Bone
In-Reply-To: <20120830203505.GB1303@atomide.com>
References: <1346141454-18786-1-git-send-email-anilkumar@ti.com>
 <1346141454-18786-3-git-send-email-anilkumar@ti.com>
 <20120830203505.GB1303@atomide.com>
Message-ID: <C1D7B7D4-D576-4256-83F3-09689B4087C3@dominion.thruhere.net>


Op 30 aug. 2012, om 22:35 heeft Tony Lindgren <tony at atomide.com> het volgende geschreven:

> * AnilKumar Ch <anilkumar at ti.com> [120828 01:11]:
>> Adds GPIO pinctrl nodes to am3358_pinmux master node to control
>> user leds (USR0, USR1, USR2 and USR3) present on BeagleBone.
>> 
>> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
>> ---
>> arch/arm/boot/dts/am335x-bone.dts |   14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>> 
>> diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
>> index a7906cb..58f5042 100644
>> --- a/arch/arm/boot/dts/am335x-bone.dts
>> +++ b/arch/arm/boot/dts/am335x-bone.dts
>> @@ -18,6 +18,20 @@
>> 		reg = <0x80000000 0x10000000>; /* 256 MB */
>> 	};
>> 
>> +	am3358_pinmux: pinmux at 44E10800 {
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&userled_pins>;
>> +
>> +		userled_pins: pinmux_userled_pins {
>> +			pinctrl-single,pins = <
>> +				0x54 0x7	/* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
>> +				0x58 0x17	/* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
>> +				0x5C 0x7	/* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
>> +				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
>> +			>;
>> +		};
>> +	};
>> +
> 
> Looks like this patch should also claim these pins by the led driver.
> Then the led driver should just do pinctrl_get_select_default(&pdev->dev)
> in it's probe function to set the pins.

FWIW, I've been using this for a while now:

+       leds {
+               compatible = "gpio-leds";
+               heartbeat {
+                       label = "beaglebone::usr0";
+                       gpios = <&gpio2 21 0>;
+                       linux,default-trigger = "heartbeat";
+               };
+
+               mmc {
+                       label = "beaglebone:usr1";
+                       gpios = <&gpio2 22 0>;
+                       linux,default-trigger = "mmc0";
+               };

From nsekhar at ti.com  Fri Aug 31 12:02:18 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 31 Aug 2012 21:32:18 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <20120830144307.GA26737@beef>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com> <503F75C0.1050507@ti.com>
 <20120830144307.GA26737@beef>
Message-ID: <5040E00A.3080600@ti.com>

Hi Matt,

On 8/30/2012 8:13 PM, Matt Porter wrote:
> On Thu, Aug 30, 2012 at 07:46:32PM +0530, Sekhar Nori wrote:
>> Hi Matt,
>>
>> On 8/23/2012 6:39 AM, Matt Porter wrote:
>>> Removes use of the DaVinci EDMA private DMA API and replaces
>>> it with use of the DMA engine API.
>>>
>>> Signed-off-by: Matt Porter <mporter at ti.com>
>>
>> I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
>> initialize after applying the patch.
>>
>> root at arago:~# dmesg | grep -i spi                                               
>> spi_davinci spi_davinci.1: request RX DMA channel failed                        
> 
> Hi Sekhar,
> 
> Most likely CONFIG_TI_EDMA is off as it defaults to off in the v3
> series. Try enabling this and if it's the problem then this error
> path can be fixed to properly fallback to PIO only or fail to
> initialize as needed.

Yes, this was the problem. Since the SPI driver now depends on
CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
Kconfig if SPI is enabled? That should do until the fallback to PIO is
implemented.

With that fixed, I tested SPI on OMAP-L138 EVM and it works great.
Tested a JFFS2 mount as well as some raw chardev read/write tests.

Tested-by: Sekhar Nori <nsekhar at ti.com>

Thanks,
Sekhar


From tony at atomide.com  Fri Aug 31 12:04:04 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 09:04:04 -0700
Subject: [PATCH 4/5] leds: leds-gpio: adopt pinctrl support
In-Reply-To: <1346405361-29711-5-git-send-email-anilkumar@ti.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
 <1346405361-29711-5-git-send-email-anilkumar@ti.com>
Message-ID: <20120831160402.GN1303@atomide.com>

* AnilKumar Ch <anilkumar at ti.com> [120831 02:30]:
> Adopt pinctrl support to leds-gpio driver, based on the device
> pointer (leds-gpio) pinctrl driver configure SoC pins to GPIO
> mode.
> 
> Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> ---
>  drivers/leds/leds-gpio.c |   31 ++++++++++++++++++++++++-------
>  1 file changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
> index c032b21..d98dfb9 100644
> --- a/drivers/leds/leds-gpio.c
> +++ b/drivers/leds/leds-gpio.c
> @@ -20,6 +20,7 @@
>  #include <linux/slab.h>
>  #include <linux/workqueue.h>
>  #include <linux/module.h>
> +#include <linux/pinctrl/consumer.h>
>  
>  struct gpio_led_data {
>  	struct led_classdev cdev;
> @@ -236,14 +237,23 @@ static int __devinit gpio_led_probe(struct platform_device *pdev)
>  {
>  	struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
>  	struct gpio_leds_priv *priv;
> -	int i, ret = 0;
> +	struct pinctrl *pinctrl;
> +	int i = 0;
> +	int ret = 0;
> +
> +	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
> +	if (IS_ERR(pinctrl)) {
> +		return PTR_ERR(pinctrl);
> +	}

I think you need to just print out a warning here as most systems don't
have the pinctrl implemented. And some people just do static pinmuxing
in the bootloader.

Regards,

Tony


From hvaibhav at ti.com  Fri Aug 31 12:06:11 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 31 Aug 2012 16:06:11 +0000
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <20120831155226.GL1303@atomide.com>
References: <5040D03B.2050304@ti.com> <20120831155226.GL1303@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>

On Fri, Aug 31, 2012 at 21:22:26, Tony Lindgren wrote:
> * Vaibhav Hiremath <hvaibhav at ti.com> [120831 07:55]:
> > Hi Russell & Tony,
> > 
> > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > baseport submission we had aligned that, we won't create separate EVM
> > options, killing the board file all-together.
> > 
> > Having said that, the early printk option (DEBUG_LL) is broken, the
> > auto-generated file "./include/generated/mach-types.h" still refers to
> > CONFIG_MACH_AM335XEVM option,
> 
> The way we're heading is that the DEBUG_LL options will only work for
> one hardcoded machine where you need to select the uart type and address
> in Kconfig. Or just patch it in.
>  
> > #ifdef CONFIG_MACH_AM335XEVM
> > # ifdef machine_arch_type
> > #  undef machine_arch_type
> > #  define machine_arch_type     __machine_arch_type
> > # else
> > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > # endif
> > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > #else
> > # define machine_is_am335xevm() (0)
> > #endif
> > 
> > 
> > So I am thinking of changing the config_xxx option to SOC_AM33XX or
> > ARCH_OMAP2PLUS, something like below,
> > 
> > am335xevm        SOC_AM33XX          AM335XEVM         3589
> > 
> > OR
> > 
> > am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589
> > 
> > 
> > Can you comment on this? Based on that I will submit the patch.
> 
> I think that would at minimum break things for autogenerated
> mach-types.h where if only some other non-am335xevm machine is
> selected (like omap-generic) things don't get optimized out any
> longer as they currently do.
> 

Agreed. In that case the first option should work here, right?

Thanks,
Vaibhav


From florian.vaussard at epfl.ch  Fri Aug 31 12:06:12 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 18:06:12 +0200
Subject: [PATCH 2/2] ARM: omap/dts: update the documentation
In-Reply-To: <1346429172-5902-1-git-send-email-florian.vaussard@epfl.ch>
References: <1346429172-5902-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1346429172-5902-3-git-send-email-florian.vaussard@epfl.ch>

Add the Tobi/Overo board to the list of supported platforms.

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 .../devicetree/bindings/arm/omap/omap.txt          |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index ccdd0e5..d0051a7 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -36,6 +36,9 @@ Boards:
 - OMAP3 BeagleBoard : Low cost community board
   compatible = "ti,omap3-beagle", "ti,omap3"
 
+- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
+  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
+
 - OMAP4 SDP : Software Developement Board
   compatible = "ti,omap4-sdp", "ti,omap4430"
 
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri Aug 31 12:06:11 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 18:06:11 +0200
Subject: [PATCH 1/2] ARM: omap/dts: Add support for Gumstix Overo with Tobi
 expansion board
In-Reply-To: <1346429172-5902-1-git-send-email-florian.vaussard@epfl.ch>
References: <1346429172-5902-1-git-send-email-florian.vaussard@epfl.ch>
Message-ID: <1346429172-5902-2-git-send-email-florian.vaussard@epfl.ch>

The Gumstix Overo is a computer on module using an OMAP3 processor.
This module must be plugged into an expansion board.

This patch adds a first device tree support for the Overo, using the
Tobi expansion board. The current support is able to boot and mount
the rootfs from MMC.

This patche also updates the omap3 dtb build target.

Currently working:
- mmc0 (on board microSD)
- i2c0 and i2c2 (i2c1 not used)
- led on GPIO

Signed-off-by: Florian Vaussard <florian.vaussard at epfl.ch>
---
 arch/arm/boot/dts/omap3-overo.dtsi |   42 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-tobi.dts   |   35 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/Makefile.boot  |    2 +-
 3 files changed, 78 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-overo.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-tobi.dts

diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 0000000..d6cc5e2
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl at 48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+	};
+};
+
+/include/ "twl4030.dtsi"
+
+/* i2c2 pins are used for gpio */
+&i2c2 {
+	status = "disabled";
+};
+
+/* on board microSD slot */
+&mmc1 {
+	vmmc-supply = <&vmmc1>;
+	bus-width = <4>;
+};
+
+/* optional on board WiFi */
+&mmc2 {
+	bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 0000000..a13d12d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/include/ "omap3-overo.dtsi"
+
+/ {
+	model = "TI OMAP3 Gumstix Overo on Tobi";
+	compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+
+	leds {
+		compatible = "gpio-leds";
+		heartbeat {
+			label = "overo:red:gpio21";
+			gpios = <&gpio1 21 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+};
+
+&mmc3 {
+	status = "disabled";
+};
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
index 6cf1c2d..18813ab 100644
--- a/arch/arm/mach-omap2/Makefile.boot
+++ b/arch/arm/mach-omap2/Makefile.boot
@@ -3,7 +3,7 @@ params_phys-y		:= 0x80000100
 initrd_phys-y		:= 0x80800000
 
 dtb-$(CONFIG_SOC_OMAP2420)	+= omap2420-h4.dtb
-dtb-$(CONFIG_ARCH_OMAP3)	+= omap3-beagle.dtb omap3-evm.dtb
+dtb-$(CONFIG_ARCH_OMAP3)	+= omap3-beagle.dtb omap3-evm.dtb omap3-tobi.dtb
 dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-panda.dtb omap4-pandaES.dtb
 dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-var_som.dtb omap4-sdp.dtb
 dtb-$(CONFIG_SOC_OMAP5)		+= omap5-evm.dtb
-- 
1.7.5.4



From florian.vaussard at epfl.ch  Fri Aug 31 12:06:10 2012
From: florian.vaussard at epfl.ch (Florian Vaussard)
Date: Fri, 31 Aug 2012 18:06:10 +0200
Subject: [PATCH 0/2] ARM: omap/dts: Add support for Gumstix Overo with Tobi
 expansion
Message-ID: <1346429172-5902-1-git-send-email-florian.vaussard@epfl.ch>

The Gumstix Overo is a computer on module using an OMAP3 processor.
This module must be plugged into an expansion board.

This patchset adds a first device tree support for the Overo, using the
Tobi expansion board. The current support is able to boot and mount
the rootfs from MMC, with a few extra features.

The first patch creates the device tree for both the Overo and the
Tobi expansion board, and updates the dtb build target.

The second patch updates the omap/dts documentation.

This patchset applies on tony's tree [1], devel-dt branch.

Regards,

Florian

[1] http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap.git;a=summary


Florian Vaussard (2):
  ARM: omap/dts: Add support for Gumstix Overo with Tobi expansion
    board
  ARM: omap/dts: update the documentation

 .../devicetree/bindings/arm/omap/omap.txt          |    3 +
 arch/arm/boot/dts/omap3-overo.dtsi                 |   42 ++++++++++++++++++++
 arch/arm/boot/dts/omap3-tobi.dts                   |   35 ++++++++++++++++
 arch/arm/mach-omap2/Makefile.boot                  |    2 +-
 4 files changed, 81 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-overo.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-tobi.dts

-- 
1.7.5.4



From tony at atomide.com  Fri Aug 31 12:11:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 09:11:22 -0700
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>
References: <5040D03B.2050304@ti.com> <20120831155226.GL1303@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>
Message-ID: <20120831161122.GO1303@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120831 09:06]:
> On Fri, Aug 31, 2012 at 21:22:26, Tony Lindgren wrote:
> > * Vaibhav Hiremath <hvaibhav at ti.com> [120831 07:55]:
> > > Hi Russell & Tony,
> > > 
> > > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > > baseport submission we had aligned that, we won't create separate EVM
> > > options, killing the board file all-together.
> > > 
> > > Having said that, the early printk option (DEBUG_LL) is broken, the
> > > auto-generated file "./include/generated/mach-types.h" still refers to
> > > CONFIG_MACH_AM335XEVM option,
> > 
> > The way we're heading is that the DEBUG_LL options will only work for
> > one hardcoded machine where you need to select the uart type and address
> > in Kconfig. Or just patch it in.
> >  
> > > #ifdef CONFIG_MACH_AM335XEVM
> > > # ifdef machine_arch_type
> > > #  undef machine_arch_type
> > > #  define machine_arch_type     __machine_arch_type
> > > # else
> > > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > > # endif
> > > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > > #else
> > > # define machine_is_am335xevm() (0)
> > > #endif
> > > 
> > > 
> > > So I am thinking of changing the config_xxx option to SOC_AM33XX or
> > > ARCH_OMAP2PLUS, something like below,
> > > 
> > > am335xevm        SOC_AM33XX          AM335XEVM         3589
> > > 
> > > OR
> > > 
> > > am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589
> > > 
> > > 
> > > Can you comment on this? Based on that I will submit the patch.
> > 
> > I think that would at minimum break things for autogenerated
> > mach-types.h where if only some other non-am335xevm machine is
> > selected (like omap-generic) things don't get optimized out any
> > longer as they currently do.
> > 
> 
> Agreed. In that case the first option should work here, right?

It gets messy if we start mixing mach and soc defines there..

How about just add a hidden Kconfig option to mach-omap2/Kconfig 
that always selects MACH_TYPE_AM335XEVM if SOC_AM33XX is set?
Or does that require that MACHINE_START is there as well?

Regards,

Tony


From vkoul at infradead.org  Fri Aug 31 12:31:49 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 22:01:49 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <5040E00A.3080600@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
 <503F75C0.1050507@ti.com> <20120830144307.GA26737@beef>
 <5040E00A.3080600@ti.com>
Message-ID: <1346430709.15463.15.camel@vkoul-mobl4>

On Fri, 2012-08-31 at 21:32 +0530, Sekhar Nori wrote:
> Hi Matt,
> 
> On 8/30/2012 8:13 PM, Matt Porter wrote:
> > On Thu, Aug 30, 2012 at 07:46:32PM +0530, Sekhar Nori wrote:
> >> Hi Matt,
> >>
> >> On 8/23/2012 6:39 AM, Matt Porter wrote:
> >>> Removes use of the DaVinci EDMA private DMA API and replaces
> >>> it with use of the DMA engine API.
> >>>
> >>> Signed-off-by: Matt Porter <mporter at ti.com>
> >>
> >> I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
> >> initialize after applying the patch.
> >>
> >> root at arago:~# dmesg | grep -i spi                                               
> >> spi_davinci spi_davinci.1: request RX DMA channel failed                        
> > 
> > Hi Sekhar,
> > 
> > Most likely CONFIG_TI_EDMA is off as it defaults to off in the v3
> > series. Try enabling this and if it's the problem then this error
> > path can be fixed to properly fallback to PIO only or fail to
> > initialize as needed.
> 
> Yes, this was the problem. Since the SPI driver now depends on
> CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
> Kconfig if SPI is enabled? That should do until the fallback to PIO is
> implemented.
Then this should be enabled for SPI. Care to send a patch
> 
> With that fixed, I tested SPI on OMAP-L138 EVM and it works great.
> Tested a JFFS2 mount as well as some raw chardev read/write tests.
> 
> Tested-by: Sekhar Nori <nsekhar at ti.com>
> 
> Thanks,
> Sekhar
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

-- 
~Vinod Koul
Intel Corp.



From nsekhar at ti.com  Fri Aug 31 12:31:03 2012
From: nsekhar at ti.com (Sekhar Nori)
Date: Fri, 31 Aug 2012 22:01:03 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1346430709.15463.15.camel@vkoul-mobl4>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com> <503F75C0.1050507@ti.com>
 <20120830144307.GA26737@beef> <5040E00A.3080600@ti.com>
 <1346430709.15463.15.camel@vkoul-mobl4>
Message-ID: <5040E6C7.6030106@ti.com>

On 8/31/2012 10:01 PM, Vinod Koul wrote:
> On Fri, 2012-08-31 at 21:32 +0530, Sekhar Nori wrote:
>> Hi Matt,
>>
>> On 8/30/2012 8:13 PM, Matt Porter wrote:
>>> On Thu, Aug 30, 2012 at 07:46:32PM +0530, Sekhar Nori wrote:
>>>> Hi Matt,
>>>>
>>>> On 8/23/2012 6:39 AM, Matt Porter wrote:
>>>>> Removes use of the DaVinci EDMA private DMA API and replaces
>>>>> it with use of the DMA engine API.
>>>>>
>>>>> Signed-off-by: Matt Porter <mporter at ti.com>
>>>>
>>>> I tried testing this patch on my OMAP-L138 EVM, but SPI fails to 
>>>> initialize after applying the patch.
>>>>
>>>> root at arago:~# dmesg | grep -i spi                                               
>>>> spi_davinci spi_davinci.1: request RX DMA channel failed                        
>>>
>>> Hi Sekhar,
>>>
>>> Most likely CONFIG_TI_EDMA is off as it defaults to off in the v3
>>> series. Try enabling this and if it's the problem then this error
>>> path can be fixed to properly fallback to PIO only or fail to
>>> initialize as needed.
>>
>> Yes, this was the problem. Since the SPI driver now depends on
>> CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
>> Kconfig if SPI is enabled? That should do until the fallback to PIO is
>> implemented.
> Then this should be enabled for SPI. Care to send a patch

By 'this' you mean the Kconfig select? Then there should be no need of a
new patch for this. It can be part of this patch itself, no?

Thanks,
Sekhar


From hvaibhav at ti.com  Fri Aug 31 12:37:37 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 31 Aug 2012 16:37:37 +0000
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <20120831161122.GO1303@atomide.com>
References: <5040D03B.2050304@ti.com> <20120831155226.GL1303@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>
 <20120831161122.GO1303@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9EB6D@DBDE01.ent.ti.com>

On Fri, Aug 31, 2012 at 21:41:22, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120831 09:06]:
> > On Fri, Aug 31, 2012 at 21:22:26, Tony Lindgren wrote:
> > > * Vaibhav Hiremath <hvaibhav at ti.com> [120831 07:55]:
> > > > Hi Russell & Tony,
> > > > 
> > > > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > > > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > > > baseport submission we had aligned that, we won't create separate EVM
> > > > options, killing the board file all-together.
> > > > 
> > > > Having said that, the early printk option (DEBUG_LL) is broken, the
> > > > auto-generated file "./include/generated/mach-types.h" still refers to
> > > > CONFIG_MACH_AM335XEVM option,
> > > 
> > > The way we're heading is that the DEBUG_LL options will only work for
> > > one hardcoded machine where you need to select the uart type and address
> > > in Kconfig. Or just patch it in.
> > >  
> > > > #ifdef CONFIG_MACH_AM335XEVM
> > > > # ifdef machine_arch_type
> > > > #  undef machine_arch_type
> > > > #  define machine_arch_type     __machine_arch_type
> > > > # else
> > > > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > > > # endif
> > > > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > > > #else
> > > > # define machine_is_am335xevm() (0)
> > > > #endif
> > > > 
> > > > 
> > > > So I am thinking of changing the config_xxx option to SOC_AM33XX or
> > > > ARCH_OMAP2PLUS, something like below,
> > > > 
> > > > am335xevm        SOC_AM33XX          AM335XEVM         3589
> > > > 
> > > > OR
> > > > 
> > > > am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589
> > > > 
> > > > 
> > > > Can you comment on this? Based on that I will submit the patch.
> > > 
> > > I think that would at minimum break things for autogenerated
> > > mach-types.h where if only some other non-am335xevm machine is
> > > selected (like omap-generic) things don't get optimized out any
> > > longer as they currently do.
> > > 
> > 
> > Agreed. In that case the first option should work here, right?
> 
> It gets messy if we start mixing mach and soc defines there..
> 
> How about just add a hidden Kconfig option to mach-omap2/Kconfig 
> that always selects MACH_TYPE_AM335XEVM if SOC_AM33XX is set?

Great, this is what I had in my mind but since it is hidden option I thought 
may not be right thing to do.
I was just thinking in the direction that, it should be logical and fine if 
SOC_AM33XX is used for all AM33xx based machines, isn't it?

Anyway, I think we are on same page here, I will add it and submit the patch 
ASAP.

> Or does that require that MACHINE_START is there as well?
> 

I do not think so, they are not related to each other, this option is 
required only during decompression.
I have tested it on BeagleBone and it is working.

Thanks,
Vaibhav


> Regards,
> 
> Tony
> 



From hvaibhav at ti.com  Fri Aug 31 12:47:12 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 31 Aug 2012 16:47:12 +0000
Subject: Without MACH_ option Early printk (DEBUG_LL)
References: <5040D03B.2050304@ti.com> <20120831155226.GL1303@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>
 <20120831161122.GO1303@atomide.com> 
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9EBD1@DBDE01.ent.ti.com>

On Fri, Aug 31, 2012 at 22:07:37, Hiremath, Vaibhav wrote:
> On Fri, Aug 31, 2012 at 21:41:22, Tony Lindgren wrote:
> > * Hiremath, Vaibhav <hvaibhav at ti.com> [120831 09:06]:
> > > On Fri, Aug 31, 2012 at 21:22:26, Tony Lindgren wrote:
> > > > * Vaibhav Hiremath <hvaibhav at ti.com> [120831 07:55]:
> > > > > Hi Russell & Tony,
> > > > > 
> > > > > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > > > > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > > > > baseport submission we had aligned that, we won't create separate EVM
> > > > > options, killing the board file all-together.
> > > > > 
> > > > > Having said that, the early printk option (DEBUG_LL) is broken, the
> > > > > auto-generated file "./include/generated/mach-types.h" still refers to
> > > > > CONFIG_MACH_AM335XEVM option,
> > > > 
> > > > The way we're heading is that the DEBUG_LL options will only work for
> > > > one hardcoded machine where you need to select the uart type and address
> > > > in Kconfig. Or just patch it in.
> > > >  
> > > > > #ifdef CONFIG_MACH_AM335XEVM
> > > > > # ifdef machine_arch_type
> > > > > #  undef machine_arch_type
> > > > > #  define machine_arch_type     __machine_arch_type
> > > > > # else
> > > > > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > > > > # endif
> > > > > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > > > > #else
> > > > > # define machine_is_am335xevm() (0)
> > > > > #endif
> > > > > 
> > > > > 
> > > > > So I am thinking of changing the config_xxx option to SOC_AM33XX or
> > > > > ARCH_OMAP2PLUS, something like below,
> > > > > 
> > > > > am335xevm        SOC_AM33XX          AM335XEVM         3589
> > > > > 
> > > > > OR
> > > > > 
> > > > > am335xevm        ARCH_OMAP2PLUS      AM335XEVM         3589
> > > > > 
> > > > > 
> > > > > Can you comment on this? Based on that I will submit the patch.
> > > > 
> > > > I think that would at minimum break things for autogenerated
> > > > mach-types.h where if only some other non-am335xevm machine is
> > > > selected (like omap-generic) things don't get optimized out any
> > > > longer as they currently do.
> > > > 
> > > 
> > > Agreed. In that case the first option should work here, right?
> > 
> > It gets messy if we start mixing mach and soc defines there..
> > 
> > How about just add a hidden Kconfig option to mach-omap2/Kconfig 
> > that always selects MACH_TYPE_AM335XEVM if SOC_AM33XX is set?
> 
> Great, this is what I had in my mind but since it is hidden option I thought 
> may not be right thing to do.
> I was just thinking in the direction that, it should be logical and fine if 
> SOC_AM33XX is used for all AM33xx based machines, isn't it?
> 
> Anyway, I think we are on same page here, I will add it and submit the patch 
> ASAP.
> 
> > Or does that require that MACHINE_START is there as well?
> > 
> 
> I do not think so, they are not related to each other, this option is 
> required only during decompression.
> I have tested it on BeagleBone and it is working.
> 

Can you please review below patch? If you think its ok, I will send the 
patch -


diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fccbdf0..eccafb4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -104,6 +104,9 @@ config SOC_AM33XX
        select CPU_V7
        select ARM_CPU_SUSPEND if PM
        select MULTI_IRQ_HANDLER
+       select MACH_AM335XEVM
+       select MACH_AM335XIAEVM
+       select MACH_TAM335X

 config OMAP_PACKAGE_ZAF
        bool
@@ -140,6 +143,15 @@ config MACH_OMAP_GENERIC
          Support for generic TI OMAP2+ boards using Flattened Device Tree.
          More information at Documentation/devicetree

+config MACH_AM335XEVM
+       bool
+
+config MACH_AM335XIAEVM
+       bool
+
+config MACH_TAM335X
+       bool
+
 config MACH_OMAP2_TUSB6010
        bool
        depends on ARCH_OMAP2 && SOC_OMAP2420

Thanks,
Vaibhav


From sboyd at codeaurora.org  Fri Aug 31 12:48:55 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Fri, 31 Aug 2012 09:48:55 -0700
Subject: [PATCH v2] hvc_dcc : add support to armv4 and armv5 core
In-Reply-To: <1346413645-4593-1-git-send-email-castet.matthieu@free.fr>
References: <1346413645-4593-1-git-send-email-castet.matthieu@free.fr>
Message-ID: <5040EAF7.9010003@codeaurora.org>

On 8/31/2012 4:47 AM, Matthieu CASTET wrote:
> Signed-off-by: Matthieu Castet <matthieu.castet at parrot.com>

Please consider adding some sort of commit text. Does this add some new
feature I may want on some downstream distro kernel?

> @@ -51,7 +51,7 @@ static inline char __dcc_getchar(void)
>  	return __c;
>  }
>  
> -static inline void __dcc_putchar(char c)
> +static inline void __dcc_putchar_v6(char c)
>  {
>  	asm volatile("mcr p14, 0, %0, c0, c5, 0	@ write a char"
>  		: /* no output register */
> @@ -59,6 +59,69 @@ static inline void __dcc_putchar(char c)
>  	isb();
>  }
>  
> +static int hvc_dcc_put_chars_v6(uint32_t vt, const char *buf, int count)
> +{
> +	int i;
> +
> +	for (i = 0; i < count; i++) {
> +		while (__dcc_getstatus_v6() & DCC_STATUS_TX_V6)
> +			cpu_relax();
> +
> +		__dcc_putchar_v6(buf[i]);
> +	}
> +
> +	return count;
> +}

It's unfortunate that the main logic is duplicated. I wonder if we could
push the runtime decision slightly lower into the accessor functions
instead and make some new functions dcc_tx_busy() and dcc_rx_busy() or
something. Then these loops stay the same.

> +
> +static int hvc_dcc_get_chars_v6(uint32_t vt, char *buf, int count)
> +{
> +	int i;
> +
> +	for (i = 0; i < count; ++i)
> +		if (__dcc_getstatus_v6() & DCC_STATUS_RX_V6)
> +			buf[i] = __dcc_getchar_v6();
> +		else
> +			break;
> +
> +	return i;
> +}
> +
> +static const struct hv_ops hvc_dcc_get_put_ops_v6 = {
> +	.get_chars = hvc_dcc_get_chars_v6,
> +	.put_chars = hvc_dcc_put_chars_v6,
> +};
> +
> +#define DCC_STATUS_RX		(1 << 0)
> +#define DCC_STATUS_TX		(1 << 1)
> +
> +/* primitive JTAG1 protocol utilities */

This comment doesn't tell me much. Remove it?

> +static inline u32 __dcc_getstatus(void)
> +{
> +	u32 ret;
> +
> +	asm __volatile__ ("mrc p14, 0, %0, c0, c0	@ read comms ctrl reg"
> +		: "=r" (ret));

Can you use volatile instead of __volatile__ so that the file is consistent?

> +
> +	return ret;
> +}
> +
> +static inline char __dcc_getchar(void)
> +{
> +	char c;
> +
> +	asm __volatile__ ("mrc p14, 0, %0, c1, c0	@ read comms data reg"
> +		: "=r" (c));
> +

Do you see any multiple character inputs? I think you may need an isb
here similar to the v6/7 code and in the putchar as well.

> +	return c;
> +}
> +
> +static inline void __dcc_putchar(unsigned char c)
> +{
> +	asm __volatile__ ("mcr p14, 0, %0, c1, c0	@ write a char"
> +		: /* no output register */
> +		: "r" (c));
> +}
> +
>  static int hvc_dcc_put_chars(uint32_t vt, const char *buf, int count)
>  {
>  	int i;
>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From vkoul at infradead.org  Fri Aug 31 13:02:57 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Fri, 31 Aug 2012 22:32:57 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <5040E6C7.6030106@ti.com>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
 <503F75C0.1050507@ti.com> <20120830144307.GA26737@beef>
 <5040E00A.3080600@ti.com> <1346430709.15463.15.camel@vkoul-mobl4>
 <5040E6C7.6030106@ti.com>
Message-ID: <1346432577.15463.16.camel@vkoul-mobl4>

On Fri, 2012-08-31 at 22:01 +0530, Sekhar Nori wrote:
> >> Yes, this was the problem. Since the SPI driver now depends on
> >> CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
> >> Kconfig if SPI is enabled? That should do until the fallback to PIO
> is
> >> implemented.
> > Then this should be enabled for SPI. Care to send a patch
> 
> By 'this' you mean the Kconfig select? Then there should be no need of
> a
> new patch for this. It can be part of this patch itself, no? 
Either way is okay for me.

-- 
~Vinod Koul
Intel Corp.



From tony at atomide.com  Fri Aug 31 13:06:14 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 10:06:14 -0700
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9EBD1@DBDE01.ent.ti.com>
References: <5040D03B.2050304@ti.com> <20120831155226.GL1303@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9EB0F@DBDE01.ent.ti.com>
 <20120831161122.GO1303@atomide.com>
 <79CD15C6BA57404B839C016229A409A83EA9EBD1@DBDE01.ent.ti.com>
Message-ID: <20120831170614.GP1303@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120831 09:47]:
> > On Fri, Aug 31, 2012 at 21:41:22, Tony Lindgren wrote:
> 
> Can you please review below patch? If you think its ok, I will send the 
> patch -

Yeah thanks looks OK to me, at least I can't think of better options for now.

Regards,

Tony
 
 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index fccbdf0..eccafb4 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -104,6 +104,9 @@ config SOC_AM33XX
>         select CPU_V7
>         select ARM_CPU_SUSPEND if PM
>         select MULTI_IRQ_HANDLER
> +       select MACH_AM335XEVM
> +       select MACH_AM335XIAEVM
> +       select MACH_TAM335X
> 
>  config OMAP_PACKAGE_ZAF
>         bool
> @@ -140,6 +143,15 @@ config MACH_OMAP_GENERIC
>           Support for generic TI OMAP2+ boards using Flattened Device Tree.
>           More information at Documentation/devicetree
> 
> +config MACH_AM335XEVM
> +       bool
> +
> +config MACH_AM335XIAEVM
> +       bool
> +
> +config MACH_TAM335X
> +       bool
> +
>  config MACH_OMAP2_TUSB6010
>         bool
>         depends on ARCH_OMAP2 && SOC_OMAP2420
> 
> Thanks,
> Vaibhav


From linux at arm.linux.org.uk  Fri Aug 31 13:13:36 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 31 Aug 2012 18:13:36 +0100
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <5040D03B.2050304@ti.com>
References: <5040D03B.2050304@ti.com>
Message-ID: <20120831171336.GA6978@n2100.arm.linux.org.uk>

On Fri, Aug 31, 2012 at 08:24:51PM +0530, Vaibhav Hiremath wrote:
> Hi Russell & Tony,
> 
> AM335X EVM (based on AM33XX device) only supports DT boot mode and
> doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> baseport submission we had aligned that, we won't create separate EVM
> options, killing the board file all-together.
> 
> Having said that, the early printk option (DEBUG_LL) is broken, the
> auto-generated file "./include/generated/mach-types.h" still refers to
> CONFIG_MACH_AM335XEVM option,
> 
> #ifdef CONFIG_MACH_AM335XEVM
> # ifdef machine_arch_type
> #  undef machine_arch_type
> #  define machine_arch_type     __machine_arch_type
> # else
> #  define machine_arch_type     MACH_TYPE_AM335XEVM
> # endif
> # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> #else
> # define machine_is_am335xevm() (0)
> #endif

machine types are entirely meaningless for DT based systems.

> Can you comment on this? Based on that I will submit the patch.

Pointless.  You can't use machine_is_am335xevm() when you're using DT.


From hvaibhav at ti.com  Fri Aug 31 13:23:12 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 31 Aug 2012 17:23:12 +0000
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <20120831171336.GA6978@n2100.arm.linux.org.uk>
References: <5040D03B.2050304@ti.com>
 <20120831171336.GA6978@n2100.arm.linux.org.uk>
Message-ID: <79CD15C6BA57404B839C016229A409A83EA9EC8B@DBDE01.ent.ti.com>

On Fri, Aug 31, 2012 at 22:43:36, Russell King - ARM Linux wrote:
> On Fri, Aug 31, 2012 at 08:24:51PM +0530, Vaibhav Hiremath wrote:
> > Hi Russell & Tony,
> > 
> > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > baseport submission we had aligned that, we won't create separate EVM
> > options, killing the board file all-together.
> > 
> > Having said that, the early printk option (DEBUG_LL) is broken, the
> > auto-generated file "./include/generated/mach-types.h" still refers to
> > CONFIG_MACH_AM335XEVM option,
> > 
> > #ifdef CONFIG_MACH_AM335XEVM
> > # ifdef machine_arch_type
> > #  undef machine_arch_type
> > #  define machine_arch_type     __machine_arch_type
> > # else
> > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > # endif
> > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > #else
> > # define machine_is_am335xevm() (0)
> > #endif
> 
> machine types are entirely meaningless for DT based systems.
> 
> > Can you comment on this? Based on that I will submit the patch.
> 
> Pointless.  You can't use machine_is_am335xevm() when you're using DT.
> 

They how do you recommend to resolve early prink issue (required during 
decompression)?

Thanks,
Vaibhav



From broonie at opensource.wolfsonmicro.com  Fri Aug 31 13:27:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 31 Aug 2012 10:27:30 -0700
Subject: [PATCH V3] ASoC: Davinci: machine: Add device tree binding
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EA70165@DBDE01.ent.ti.com>
References: <1346148830-2965-1-git-send-email-gururaja.hebbar@ti.com>
 <1BAFE6F6C881BF42822005164F1491C33EA70165@DBDE01.ent.ti.com>
Message-ID: <20120831172729.GE25575@opensource.wolfsonmicro.com>

On Fri, Aug 31, 2012 at 08:55:39AM +0000, Hebbar, Gururaja wrote:
> 
> Gentle Ping. Any updates about this version or can it be pulled into the tree.
> 
> On Thu, Aug 30, 2012 at 09:29:55, Hebbar, Gururaja wrote:

Please don't do this:

 - Never top post.
 - If the patch genuinely has been forgotten you need to resend it.
 - You've allowed less than 24 hours for a reply, this is unreasonable.
   Unless there's a critical bug fix you should only be worrying after a
   few weeks or so.


From broonie at opensource.wolfsonmicro.com  Fri Aug 31 13:41:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 31 Aug 2012 10:41:36 -0700
Subject: [PATCH] ASoC: samsung dma - Don't indicate support for
 pause/resume.
In-Reply-To: <1346387854-22222-1-git-send-email-dgreid@chromium.org>
References: <1346387854-22222-1-git-send-email-dgreid@chromium.org>
Message-ID: <20120831174135.GF25575@opensource.wolfsonmicro.com>

On Thu, Aug 30, 2012 at 09:37:34PM -0700, Dylan Reid wrote:

> index f3ebc38..56a507a 100644
> --- a/sound/soc/samsung/dma.c
> +++ b/sound/soc/samsung/dma.c
> @@ -34,9 +34,7 @@ static const struct snd_pcm_hardware dma_hardware = {
>  	.info			= SNDRV_PCM_INFO_INTERLEAVED |
>  				    SNDRV_PCM_INFO_BLOCK_TRANSFER |
>  				    SNDRV_PCM_INFO_MMAP |
> -				    SNDRV_PCM_INFO_MMAP_VALID |
> -				    SNDRV_PCM_INFO_PAUSE |
> -				    SNDRV_PCM_INFO_RESUME,
> +				    SNDRV_PCM_INFO_MMAP_VALID,

I'd expect to also see an update to the trigger function to not accept
the suspend and resume triggers?


From anilkumar at ti.com  Fri Aug 31 13:54:18 2012
From: anilkumar at ti.com (AnilKumar, Chimata)
Date: Fri, 31 Aug 2012 17:54:18 +0000
Subject: [PATCH 4/5] leds: leds-gpio: adopt pinctrl support
In-Reply-To: <20120831160402.GN1303@atomide.com>
References: <1346405361-29711-1-git-send-email-anilkumar@ti.com>
 <1346405361-29711-5-git-send-email-anilkumar@ti.com>
 <20120831160402.GN1303@atomide.com>
Message-ID: <331ABD5ECB02734CA317220B2BBEABC13EA2329D@DBDE01.ent.ti.com>

Hi Tony,

Thanks for the review,

On Fri, Aug 31, 2012 at 21:34:04, Tony Lindgren wrote:
> * AnilKumar Ch <anilkumar at ti.com> [120831 02:30]:
> > Adopt pinctrl support to leds-gpio driver, based on the device
> > pointer (leds-gpio) pinctrl driver configure SoC pins to GPIO
> > mode.
> > 
> > Signed-off-by: AnilKumar Ch <anilkumar at ti.com>
> > ---
> >  drivers/leds/leds-gpio.c |   31 ++++++++++++++++++++++++-------
> >  1 file changed, 24 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
> > index c032b21..d98dfb9 100644
> > --- a/drivers/leds/leds-gpio.c
> > +++ b/drivers/leds/leds-gpio.c
> > @@ -20,6 +20,7 @@
> >  #include <linux/slab.h>
> >  #include <linux/workqueue.h>
> >  #include <linux/module.h>
> > +#include <linux/pinctrl/consumer.h>
> >  
> >  struct gpio_led_data {
> >  	struct led_classdev cdev;
> > @@ -236,14 +237,23 @@ static int __devinit gpio_led_probe(struct platform_device *pdev)
> >  {
> >  	struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
> >  	struct gpio_leds_priv *priv;
> > -	int i, ret = 0;
> > +	struct pinctrl *pinctrl;
> > +	int i = 0;
> > +	int ret = 0;
> > +
> > +	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
> > +	if (IS_ERR(pinctrl)) {
> > +		return PTR_ERR(pinctrl);
> > +	}
> 
> I think you need to just print out a warning here as most systems don't
> have the pinctrl implemented. And some people just do static pinmuxing
> in the bootloader.
> 

Yes, that is better approach I will fix this in my next version.
I will separate out this patch from the series because these changes are
leds-gpio driver specific which are different from DT data (pinctrl and
d_can).

Thanks
AnilKumar


From hvaibhav at ti.com  Fri Aug 31 13:54:34 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 31 Aug 2012 23:24:34 +0530
Subject: [PATCH] ARM: OMAP2+: Makefile.boot: Add am335x evm and bone targets
Message-ID: <1346435674-6207-1-git-send-email-hvaibhav@ti.com>

This adds am335x-evm and am335x-bone dtb targets to
'make dtbs', just like other platforms.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Makefile.boot |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
index 6cf1c2d..1136072 100644
--- a/arch/arm/mach-omap2/Makefile.boot
+++ b/arch/arm/mach-omap2/Makefile.boot
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_OMAP3)	+= omap3-beagle.dtb omap3-evm.dtb
 dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-panda.dtb omap4-pandaES.dtb
 dtb-$(CONFIG_ARCH_OMAP4)	+= omap4-var_som.dtb omap4-sdp.dtb
 dtb-$(CONFIG_SOC_OMAP5)		+= omap5-evm.dtb
+dtb-$(CONFIG_SOC_AM33XX)	+= am335x-evm.dtb am335x-bone.dtb
-- 
1.7.0.4



From robherring2 at gmail.com  Fri Aug 31 14:12:45 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 13:12:45 -0500
Subject: [PATCH v2] ARM: initial multiplatform support
In-Reply-To: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346436765-9709-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This lets us build a multiplatform kernel for experimental purposes.
However, it will not be useful for any real work, because it relies
on a number of useful things to be disabled for now:

* SMP support must be turned off because of conflicting symbols.
  Marc Zyngier has proposed a solution by adding a new SOC
  operations structure to hold indirect function pointers
  for these, but that work is currently stalled

* We turn on SPARSE_IRQ unconditionally, which is not supported
  on most platforms. Each of them is currently in a different
  state, but most are being worked on.

* Only platforms using common clock framework or no clocks at all can
  be converted to multi-platform.

* THUMB2_KERNEL does not work with allyesconfig because the
  kernel gets too big

[Rob Herring]: Rebased to not be dependent on the mass mach header rename.
As a result, omap2plus, imx, mxs and ux500 are not converted. Highbank,
picoxcell, mvebu, socfpga, and vexpress are converted.

v2: This version avoids the kconfig symbol name changes and simply moves
multi-platform enabled platform kconfig option out of the choice option
and into the platform's mach directory. A separate series fixes DEBUG_LL
for multi-platform.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                 |  145 +++++++++++++++--------------------
 arch/arm/Makefile                |  155 ++++++++++++++++++++------------------
 arch/arm/boot/compressed/misc.c  |    6 ++
 arch/arm/include/asm/timex.h     |    4 +
 arch/arm/mach-highbank/Kconfig   |   15 ++++
 arch/arm/mach-mvebu/Kconfig      |   10 +++
 arch/arm/mach-mvebu/Makefile     |    2 +
 arch/arm/mach-picoxcell/Kconfig  |   14 ++++
 arch/arm/mach-socfpga/Kconfig    |   16 ++++
 arch/arm/mach-vexpress/Kconfig   |   16 ++++
 arch/arm/mach-vexpress/Makefile  |    2 +
 arch/arm/plat-versatile/Makefile |    2 +
 12 files changed, 226 insertions(+), 161 deletions(-)
 create mode 100644 arch/arm/mach-highbank/Kconfig
 create mode 100644 arch/arm/mach-picoxcell/Kconfig
 create mode 100644 arch/arm/mach-socfpga/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3557f12..4c9f2fc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -254,27 +254,9 @@ config MMU
 #
 choice
 	prompt "ARM system type"
+	depends on !ARCH_MULTIPLATFORM
 	default ARCH_VERSATILE
 
-config ARCH_SOCFPGA
-	bool "Altera SOCFPGA family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CPU_V7
-	select DW_APB_TIMER
-	select DW_APB_TIMER_OF
-	select GENERIC_CLOCKEVENTS
-	select GPIO_PL061 if GPIOLIB
-	select HAVE_ARM_SCU
-	select SPARSE_IRQ
-	select USE_OF
-	help
-	  This enables support for Altera SOCFPGA Cyclone V platform
-
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select ARM_AMBA
@@ -328,24 +310,6 @@ config ARCH_VERSATILE
 	help
 	  This enables support for ARM Ltd Versatile board.
 
-config ARCH_VEXPRESS
-	bool "ARM Ltd. Versatile Express family"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select GENERIC_CLOCKEVENTS
-	select HAVE_CLK
-	select HAVE_PATA_PLATFORM
-	select ICST
-	select NO_IOPORT
-	select PLAT_VERSATILE
-	select PLAT_VERSATILE_CLCD
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-	help
-	  This enables support for the ARM Ltd Versatile Express boards.
-
 config ARCH_AT91
 	bool "Atmel AT91"
 	select ARCH_REQUIRE_GPIOLIB
@@ -369,24 +333,6 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
-config ARCH_HIGHBANK
-	bool "Calxeda Highbank-based"
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	select ARM_AMBA
-	select ARM_GIC
-	select ARM_TIMER_SP804
-	select CACHE_L2X0
-	select CLKDEV_LOOKUP
-	select COMMON_CLK
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select HAVE_ARM_SCU
-	select HAVE_SMP
-	select SPARSE_IRQ
-	select USE_OF
-	help
-	  Support for the Calxeda Highbank SoC based boards.
-
 config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 	select CPU_ARM720T
@@ -567,18 +513,6 @@ config ARCH_IXP4XX
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_MVEBU
-	bool "Marvell SOCs with Device Tree support"
-	select GENERIC_CLOCKEVENTS
-	select MULTI_IRQ_HANDLER
-	select SPARSE_IRQ
-	select CLKSRC_MMIO
-	select GENERIC_IRQ_CHIP
-	select IRQ_DOMAIN
-	select COMMON_CLK
-	help
-	  Support for the Marvell SoC Family with device tree support
-
 config ARCH_DOVE
 	bool "Marvell Dove"
 	select CPU_V7
@@ -699,25 +633,6 @@ config ARCH_TEGRA
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
 	  Tegra 6xx and Tegra 2 series).
 
-config ARCH_PICOXCELL
-	bool "Picochip picoXcell"
-	select ARCH_REQUIRE_GPIOLIB
-	select ARM_PATCH_PHYS_VIRT
-	select ARM_VIC
-	select CPU_V6K
-	select DW_APB_TIMER
-	select DW_APB_TIMER_OF
-	select GENERIC_CLOCKEVENTS
-	select GENERIC_GPIO
-	select HAVE_TCM
-	select NO_IOPORT
-	select SPARSE_IRQ
-	select USE_OF
-	help
-	  This enables support for systems based on the Picochip picoXcell
-	  family of Femtocell devices.  The picoxcell support requires device tree
-	  for all boards.
-
 config ARCH_PNX4008
 	bool "Philips Nexperia PNX4008 Mobile"
 	select CPU_ARM926T
@@ -1039,6 +954,58 @@ config ARCH_ZYNQ
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
 
+menuconfig ARCH_MULTIPLATFORM
+	bool "Multiple platform selection"
+	select USE_OF
+	select COMMON_CLK
+	select SPARSE_IRQ
+	select MULTI_IRQ_HANDLER
+	select AUTO_ZRELADDR
+	depends on MMU
+
+if ARCH_MULTIPLATFORM
+
+comment "CPU Core family selection"
+
+config ARCH_MULTI_V4
+	bool "ARMv4 based platforms (FA526, StrongARM)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4T
+	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V5
+	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
+	select ARCH_MULTI_V4_V5
+	depends on !ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V4_V5
+	bool
+
+config ARCH_MULTI_V6
+	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
+	select CPU_V6
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V7
+	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
+	select CPU_V7
+	select ARCH_VEXPRESS
+	default y
+	select ARCH_MULTI_V6_V7
+
+config ARCH_MULTI_V6_V7
+	bool
+
+config ARCH_MULTI_CPU_AUTO
+	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
+	select ARCH_MULTI_V5
+
+endif
+
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -1066,6 +1033,8 @@ source "arch/arm/mach-gemini/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
 
+source "arch/arm/mach-highbank/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -1101,6 +1070,8 @@ source "arch/arm/mach-omap2/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
+source "arch/arm/mach-picoxcell/Kconfig"
+
 source "arch/arm/mach-pxa/Kconfig"
 source "arch/arm/plat-pxa/Kconfig"
 
@@ -1113,6 +1084,8 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 
+source "arch/arm/mach-socfpga/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..fe6e05e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -135,84 +135,84 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
-machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
-machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
-machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
-machine-$(CONFIG_ARCH_DOVE)		:= dove
-machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
-machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
-machine-$(CONFIG_ARCH_GEMINI)		:= gemini
-machine-$(CONFIG_ARCH_H720X)		:= h720x
-machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
-machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
-machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
-machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
-machine-$(CONFIG_ARCH_IOP33X)		:= iop33x
-machine-$(CONFIG_ARCH_IXP4XX)		:= ixp4xx
-machine-$(CONFIG_ARCH_KIRKWOOD)		:= kirkwood
-machine-$(CONFIG_ARCH_KS8695)		:= ks8695
-machine-$(CONFIG_ARCH_LPC32XX)		:= lpc32xx
-machine-$(CONFIG_ARCH_MMP)		:= mmp
-machine-$(CONFIG_ARCH_MSM)		:= msm
-machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
-machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
-machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
-machine-$(CONFIG_ARCH_MXS)		:= mxs
-machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
-machine-$(CONFIG_ARCH_NETX)		:= netx
-machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
-machine-$(CONFIG_ARCH_OMAP1)		:= omap1
-machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
-machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
-machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
-machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
-machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
-machine-$(CONFIG_ARCH_PXA)		:= pxa
-machine-$(CONFIG_ARCH_REALVIEW)		:= realview
-machine-$(CONFIG_ARCH_RPC)		:= rpc
-machine-$(CONFIG_ARCH_S3C24XX)		:= s3c24xx s3c2412 s3c2440
-machine-$(CONFIG_ARCH_S3C64XX)		:= s3c64xx
-machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
-machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
-machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
-machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
-machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
-machine-$(CONFIG_ARCH_SA1100)		:= sa1100
-machine-$(CONFIG_ARCH_SHARK)		:= shark
-machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
-machine-$(CONFIG_ARCH_TEGRA)		:= tegra
-machine-$(CONFIG_ARCH_U300)		:= u300
-machine-$(CONFIG_ARCH_U8500)		:= ux500
-machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
-machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
-machine-$(CONFIG_ARCH_VT8500)		:= vt8500
-machine-$(CONFIG_ARCH_W90X900)		:= w90x900
-machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
-machine-$(CONFIG_ARCH_SOCFPGA)		:= socfpga
-machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
-machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
-machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
-machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
+machine-$(CONFIG_ARCH_AT91)		+= at91
+machine-$(CONFIG_ARCH_BCMRING)		+= bcmring
+machine-$(CONFIG_ARCH_CLPS711X)		+= clps711x
+machine-$(CONFIG_ARCH_CNS3XXX)		+= cns3xxx
+machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
+machine-$(CONFIG_ARCH_DOVE)		+= dove
+machine-$(CONFIG_ARCH_EBSA110)		+= ebsa110
+machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
+machine-$(CONFIG_ARCH_GEMINI)		+= gemini
+machine-$(CONFIG_ARCH_H720X)		+= h720x
+machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
+machine-$(CONFIG_ARCH_INTEGRATOR)	+= integrator
+machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx
+machine-$(CONFIG_ARCH_IOP32X)		+= iop32x
+machine-$(CONFIG_ARCH_IOP33X)		+= iop33x
+machine-$(CONFIG_ARCH_IXP4XX)		+= ixp4xx
+machine-$(CONFIG_ARCH_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARCH_KS8695)		+= ks8695
+machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
+machine-$(CONFIG_ARCH_MMP)		+= mmp
+machine-$(CONFIG_ARCH_MSM)		+= msm
+machine-$(CONFIG_ARCH_MV78XX0)		+= mv78xx0
+machine-$(CONFIG_ARCH_IMX_V4_V5)	+= imx
+machine-$(CONFIG_ARCH_IMX_V6_V7)	+= imx
+machine-$(CONFIG_ARCH_MXS)		+= mxs
+machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
+machine-$(CONFIG_ARCH_NETX)		+= netx
+machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_OMAP1)		+= omap1
+machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
+machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
+machine-$(CONFIG_ARCH_PICOXCELL)	+= picoxcell
+machine-$(CONFIG_ARCH_PNX4008)		+= pnx4008
+machine-$(CONFIG_ARCH_PRIMA2)		+= prima2
+machine-$(CONFIG_ARCH_PXA)		+= pxa
+machine-$(CONFIG_ARCH_REALVIEW)		+= realview
+machine-$(CONFIG_ARCH_RPC)		+= rpc
+machine-$(CONFIG_ARCH_S3C24XX)		+= s3c24xx s3c2412 s3c2440
+machine-$(CONFIG_ARCH_S3C64XX)		+= s3c64xx
+machine-$(CONFIG_ARCH_S5P64X0)		+= s5p64x0
+machine-$(CONFIG_ARCH_S5PC100)		+= s5pc100
+machine-$(CONFIG_ARCH_S5PV210)		+= s5pv210
+machine-$(CONFIG_ARCH_EXYNOS4)		+= exynos
+machine-$(CONFIG_ARCH_EXYNOS5)		+= exynos
+machine-$(CONFIG_ARCH_SA1100)		+= sa1100
+machine-$(CONFIG_ARCH_SHARK)		+= shark
+machine-$(CONFIG_ARCH_SHMOBILE) 	+= shmobile
+machine-$(CONFIG_ARCH_TEGRA)		+= tegra
+machine-$(CONFIG_ARCH_U300)		+= u300
+machine-$(CONFIG_ARCH_U8500)		+= ux500
+machine-$(CONFIG_ARCH_VERSATILE)	+= versatile
+machine-$(CONFIG_ARCH_VEXPRESS)		+= vexpress
+machine-$(CONFIG_ARCH_VT8500)		+= vt8500
+machine-$(CONFIG_ARCH_W90X900)		+= w90x900
+machine-$(CONFIG_FOOTBRIDGE)		+= footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
+machine-$(CONFIG_MACH_SPEAR1310)	+= spear13xx
+machine-$(CONFIG_MACH_SPEAR1340)	+= spear13xx
+machine-$(CONFIG_MACH_SPEAR300)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR310)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR320)		+= spear3xx
+machine-$(CONFIG_MACH_SPEAR600)		+= spear6xx
+machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_MXC)		:= mxc
-plat-$(CONFIG_ARCH_OMAP)	:= omap
-plat-$(CONFIG_ARCH_S3C64XX)	:= samsung
-plat-$(CONFIG_ARCH_ZYNQ)	:= versatile
-plat-$(CONFIG_PLAT_IOP)		:= iop
-plat-$(CONFIG_PLAT_NOMADIK)	:= nomadik
-plat-$(CONFIG_PLAT_ORION)	:= orion
-plat-$(CONFIG_PLAT_PXA)		:= pxa
-plat-$(CONFIG_PLAT_S3C24XX)	:= s3c24xx samsung
-plat-$(CONFIG_PLAT_S5P)		:= samsung
-plat-$(CONFIG_PLAT_SPEAR)	:= spear
-plat-$(CONFIG_PLAT_VERSATILE)	:= versatile
+plat-$(CONFIG_ARCH_MXC)		+= mxc
+plat-$(CONFIG_ARCH_OMAP)	+= omap
+plat-$(CONFIG_ARCH_S3C64XX)	+= samsung
+plat-$(CONFIG_ARCH_ZYNQ)	+= versatile
+plat-$(CONFIG_PLAT_IOP)		+= iop
+plat-$(CONFIG_PLAT_NOMADIK)	+= nomadik
+plat-$(CONFIG_PLAT_ORION)	+= orion
+plat-$(CONFIG_PLAT_PXA)		+= pxa
+plat-$(CONFIG_PLAT_S3C24XX)	+= s3c24xx samsung
+plat-$(CONFIG_PLAT_S5P)		+= samsung
+plat-$(CONFIG_PLAT_SPEAR)	+= spear
+plat-$(CONFIG_PLAT_VERSATILE)	+= versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
@@ -230,15 +230,20 @@ MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
 else
 MACHINE  :=
 endif
+ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+MACHINE  :=
+endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
 
+ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
 KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
 else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
+endif
 
 export	TEXT_OFFSET GZFLAGS MMUEXT
 
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 8e2a8fc..df89983 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 extern void error(char *x);
 
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+#else
 #include <mach/uncompress.h>
+#endif
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index ce11944..963342a 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -13,7 +13,11 @@
 #define _ASMARM_TIMEX_H
 
 #include <asm/arch_timer.h>
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+#define CLOCK_TICK_RATE 1000000
+#else
 #include <mach/timex.h>
+#endif
 
 typedef unsigned long cycles_t;
 
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
new file mode 100644
index 0000000..0e1d0a4
--- /dev/null
+++ b/arch/arm/mach-highbank/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_HIGHBANK
+	bool "Calxeda ECX-1000 (Highbank)" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_TIMER_SP804
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU
+	select HAVE_SMP
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..7b27035 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,3 +1,13 @@
+config ARCH_MVEBU
+	bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+	select CLKSRC_MMIO
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+
 if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8..6ea8998 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,4 @@
+ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
 obj-y += system-controller.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
new file mode 100644
index 0000000..868796f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -0,0 +1,14 @@
+config ARCH_PICOXCELL
+	bool "Picochip PicoXcell" if ARCH_MULTI_V6
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_VIC
+	select CPU_V6K
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_TCM
+	select NO_IOPORT
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 0000000..803a328
--- /dev/null
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CACHE_L2X0
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CPU_V7
+	select DW_APB_TIMER
+	select DW_APB_TIMER_OF
+	select GENERIC_CLOCKEVENTS
+	select GPIO_PL061 if GPIOLIB
+	select HAVE_ARM_SCU
+	select SPARSE_IRQ
+	select USE_OF
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index fc3730f..498ea15 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_VEXPRESS
+	bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_CLK
+	select HAVE_PATA_PLATFORM
+	select ICST
+	select NO_IOPORT
+	select PLAT_VERSATILE
+	select PLAT_VERSATILE_CLCD
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 menu "Versatile Express platform type"
 	depends on ARCH_VEXPRESS
 
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 90551b9..42703e8 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,6 +1,8 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+	-I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 272769a8..74cfd94 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,3 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
-- 
1.7.9.5



From mturquette at linaro.org  Fri Aug 31 14:24:37 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 31 Aug 2012 11:24:37 -0700
Subject: [PATCH v3] clk: add Loongson1B clock support
In-Reply-To: <1345457135-12737-1-git-send-email-keguang.zhang@gmail.com>
References: <1345457135-12737-1-git-send-email-keguang.zhang@gmail.com>
Message-ID: <20120831182437.26807.56140@nucleus>

Quoting Kelvin Cheung (2012-08-20 03:05:35)
> This adds clock support to Loongson1B SoC using the common clock
> infrastructure.
> 
> Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>

Looks good.  I've taken this into clk-next.

Thanks,
Mike

> ---
>  drivers/clk/Makefile   |    1 +
>  drivers/clk/clk-ls1x.c |  111 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 112 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/clk-ls1x.c
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 5869ea3..018ec57 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)    += socfpga/
>  obj-$(CONFIG_PLAT_SPEAR)       += spear/
>  obj-$(CONFIG_ARCH_U300)                += clk-u300.o
>  obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
> +obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
>  
>  # Chip specific
>  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
> new file mode 100644
> index 0000000..f20b750
> --- /dev/null
> +++ b/drivers/clk/clk-ls1x.c
> @@ -0,0 +1,111 @@
> +/*
> + * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include <loongson1.h>
> +
> +#define OSC    33
> +
> +static DEFINE_SPINLOCK(_lock);
> +
> +static int ls1x_pll_clk_enable(struct clk_hw *hw)
> +{
> +       return 0;
> +}
> +
> +static void ls1x_pll_clk_disable(struct clk_hw *hw)
> +{
> +}
> +
> +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
> +                                            unsigned long parent_rate)
> +{
> +       u32 pll, rate;
> +
> +       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
> +       rate = ((12 + (pll & 0x3f)) * 1000000) +
> +               ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
> +       rate *= OSC;
> +       rate >>= 1;
> +
> +       return rate;
> +}
> +
> +static const struct clk_ops ls1x_pll_clk_ops = {
> +       .enable = ls1x_pll_clk_enable,
> +       .disable = ls1x_pll_clk_disable,
> +       .recalc_rate = ls1x_pll_recalc_rate,
> +};
> +
> +static struct clk * __init clk_register_pll(struct device *dev,
> +        const char *name, const char *parent_name, unsigned long flags)
> +{
> +       struct clk_hw *hw;
> +       struct clk *clk;
> +       struct clk_init_data init;
> +
> +       /* allocate the divider */
> +       hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
> +       if (!hw) {
> +               pr_err("%s: could not allocate clk_hw\n", __func__);
> +               return ERR_PTR(-ENOMEM);
> +       }
> +
> +       init.name = name;
> +       init.ops = &ls1x_pll_clk_ops;
> +       init.flags = flags | CLK_IS_BASIC;
> +       init.parent_names = (parent_name ? &parent_name : NULL);
> +       init.num_parents = (parent_name ? 1 : 0);
> +       hw->init = &init;
> +
> +       /* register the clock */
> +       clk = clk_register(dev, hw);
> +
> +       if (IS_ERR(clk))
> +               kfree(hw);
> +
> +       return clk;
> +}
> +
> +void __init ls1x_clk_init(void)
> +{
> +       struct clk *clk;
> +
> +       clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
> +       clk_prepare_enable(clk);
> +
> +       clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
> +                       DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "cpu", NULL);
> +
> +       clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
> +                       DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "dc", NULL);
> +
> +       clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
> +                       DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "ahb", NULL);
> +       clk_register_clkdev(clk, "stmmaceth", NULL);
> +
> +       clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "apb", NULL);
> +       clk_register_clkdev(clk, "serial8250", NULL);
> +}
> -- 
> 1.7.1


From robherring2 at gmail.com  Fri Aug 31 14:29:19 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 13:29:19 -0500
Subject: [PATCH 1/3] ARM: move debug macros to common location
Message-ID: <1346437761-17039-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Based on suggestion by Russell King, create a common location for debug
macros and select the included debug macro file using config option.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig.debug          |    5 +++
 arch/arm/include/debug/icedcc.S |   90 +++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/debug.S         |   87 ++-----------------------------------
 arch/arm/kernel/head.S          |    4 +-
 4 files changed, 100 insertions(+), 86 deletions(-)
 create mode 100644 arch/arm/include/debug/icedcc.S

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f15f82b..71bbda2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -373,6 +373,11 @@ choice
 
 endchoice
 
+config DEBUG_LL_INCLUDE
+	string
+	default "debug/icedcc.S" if DEBUG_ICEDCC
+	default "mach/debug-macros.S"
+
 config EARLY_PRINTK
 	bool "Early printk"
 	depends on DEBUG_LL
diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S
new file mode 100644
index 0000000..43afcb0
--- /dev/null
+++ b/arch/arm/include/debug/icedcc.S
@@ -0,0 +1,90 @@
+/*
+ *  arch/arm/include/debug/icedcc.S
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+		@@ debug using ARM EmbeddedICE DCC channel
+
+		.macro	addruart, rp, rv, tmp
+		.endm
+
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
+
+		.macro	senduart, rd, rx
+		mcr	p14, 0, \rd, c0, c5, 0
+		.endm
+
+		.macro	busyuart, rd, rx
+1001:
+		mrc	p14, 0, \rx, c0, c1, 0
+		tst	\rx, #0x20000000
+		beq	1001b
+		.endm
+
+		.macro	waituart, rd, rx
+		mov	\rd, #0x2000000
+1001:
+		subs	\rd, \rd, #1
+		bmi	1002f
+		mrc	p14, 0, \rx, c0, c1, 0
+		tst	\rx, #0x20000000
+		bne	1001b
+1002:
+		.endm
+
+#elif defined(CONFIG_CPU_XSCALE)
+
+		.macro	senduart, rd, rx
+		mcr	p14, 0, \rd, c8, c0, 0
+		.endm
+
+		.macro	busyuart, rd, rx
+1001:
+		mrc	p14, 0, \rx, c14, c0, 0
+		tst	\rx, #0x10000000
+		beq	1001b
+		.endm
+
+		.macro	waituart, rd, rx
+		mov	\rd, #0x10000000
+1001:
+		subs	\rd, \rd, #1
+		bmi	1002f
+		mrc	p14, 0, \rx, c14, c0, 0
+		tst	\rx, #0x10000000
+		bne	1001b
+1002:
+		.endm
+
+#else
+
+		.macro	senduart, rd, rx
+		mcr	p14, 0, \rd, c1, c0, 0
+		.endm
+
+		.macro	busyuart, rd, rx
+1001:
+		mrc	p14, 0, \rx, c0, c0, 0
+		tst	\rx, #2
+		beq	1001b
+
+		.endm
+
+		.macro	waituart, rd, rx
+		mov	\rd, #0x2000000
+1001:
+		subs	\rd, \rd, #1
+		bmi	1002f
+		mrc	p14, 0, \rx, c0, c0, 0
+		tst	\rx, #2
+		bne	1001b
+1002:
+		.endm
+
+#endif	/* CONFIG_CPU_V6 */
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index c45522c..66f711b 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -20,90 +20,9 @@
  * references to these in a production kernel!
  */
 
-#if defined(CONFIG_DEBUG_ICEDCC)
-		@@ debug using ARM EmbeddedICE DCC channel
-
-		.macro	addruart, rp, rv, tmp
-		.endm
-
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
-
-		.macro	senduart, rd, rx
-		mcr	p14, 0, \rd, c0, c5, 0
-		.endm
-
-		.macro	busyuart, rd, rx
-1001:
-		mrc	p14, 0, \rx, c0, c1, 0
-		tst	\rx, #0x20000000
-		beq	1001b
-		.endm
-
-		.macro	waituart, rd, rx
-		mov	\rd, #0x2000000
-1001:
-		subs	\rd, \rd, #1
-		bmi	1002f
-		mrc	p14, 0, \rx, c0, c1, 0
-		tst	\rx, #0x20000000
-		bne	1001b
-1002:
-		.endm
-
-#elif defined(CONFIG_CPU_XSCALE)
-
-		.macro	senduart, rd, rx
-		mcr	p14, 0, \rd, c8, c0, 0
-		.endm
-
-		.macro	busyuart, rd, rx
-1001:
-		mrc	p14, 0, \rx, c14, c0, 0
-		tst	\rx, #0x10000000
-		beq	1001b
-		.endm
-
-		.macro	waituart, rd, rx
-		mov	\rd, #0x10000000
-1001:
-		subs	\rd, \rd, #1
-		bmi	1002f
-		mrc	p14, 0, \rx, c14, c0, 0
-		tst	\rx, #0x10000000
-		bne	1001b
-1002:
-		.endm
-
-#else
-
-		.macro	senduart, rd, rx
-		mcr	p14, 0, \rd, c1, c0, 0
-		.endm
-
-		.macro	busyuart, rd, rx
-1001:
-		mrc	p14, 0, \rx, c0, c0, 0
-		tst	\rx, #2
-		beq	1001b
-
-		.endm
-
-		.macro	waituart, rd, rx
-		mov	\rd, #0x2000000
-1001:
-		subs	\rd, \rd, #1
-		bmi	1002f
-		mrc	p14, 0, \rx, c0, c0, 0
-		tst	\rx, #2
-		bne	1001b
-1002:
-		.endm
-
-#endif	/* CONFIG_CPU_V6 */
-
-#elif !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include <mach/debug-macro.S>
-#endif	/* CONFIG_DEBUG_ICEDCC */
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
 
 #ifdef CONFIG_MMU
 		.macro	addruart_current, rx, tmp1, tmp2
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3db960e..9874d07 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -23,8 +23,8 @@
 #include <asm/thread_info.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_DEBUG_LL
-#include <mach/debug-macro.S>
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
 #endif
 
 /*
-- 
1.7.9.5



From robherring2 at gmail.com  Fri Aug 31 14:29:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 13:29:20 -0500
Subject: [PATCH 2/3] ARM: highbank: move debug macros to include/debug
In-Reply-To: <1346437761-17039-1-git-send-email-robherring2@gmail.com>
References: <1346437761-17039-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346437761-17039-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move highbank debug-macro.S over to common debug macro directory.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig.debug                             |    1 +
 .../debug-macro.S => include/debug/highbank.S}     |    0
 2 files changed, 1 insertion(+)
 rename arch/arm/{mach-highbank/include/mach/debug-macro.S => include/debug/highbank.S} (100%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 71bbda2..71214ab 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -376,6 +376,7 @@ endchoice
 config DEBUG_LL_INCLUDE
 	string
 	default "debug/icedcc.S" if DEBUG_ICEDCC
+	default "debug/highbank.S" if DEBUG_HIGHBANK_UART
 	default "mach/debug-macros.S"
 
 config EARLY_PRINTK
diff --git a/arch/arm/mach-highbank/include/mach/debug-macro.S b/arch/arm/include/debug/highbank.S
similarity index 100%
rename from arch/arm/mach-highbank/include/mach/debug-macro.S
rename to arch/arm/include/debug/highbank.S
-- 
1.7.9.5



From robherring2 at gmail.com  Fri Aug 31 14:29:21 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 13:29:21 -0500
Subject: [PATCH 3/3] ARM: vexpress: move debug macros to include/debug
In-Reply-To: <1346437761-17039-1-git-send-email-robherring2@gmail.com>
References: <1346437761-17039-1-git-send-email-robherring2@gmail.com>
Message-ID: <1346437761-17039-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move vexpress debug-macro.S over to common debug macro directory.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig.debug                             |    1 +
 .../debug-macro.S => include/debug/vexpress.S}     |    0
 2 files changed, 1 insertion(+)
 rename arch/arm/{mach-vexpress/include/mach/debug-macro.S => include/debug/vexpress.S} (100%)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 71214ab..2256944 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -377,6 +377,7 @@ config DEBUG_LL_INCLUDE
 	string
 	default "debug/icedcc.S" if DEBUG_ICEDCC
 	default "debug/highbank.S" if DEBUG_HIGHBANK_UART
+	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
 	default "mach/debug-macros.S"
 
 config EARLY_PRINTK
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/include/debug/vexpress.S
similarity index 100%
rename from arch/arm/mach-vexpress/include/mach/debug-macro.S
rename to arch/arm/include/debug/vexpress.S
-- 
1.7.9.5



From nico at fluxnic.net  Fri Aug 31 14:23:32 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 31 Aug 2012 14:23:32 -0400 (EDT)
Subject: Without MACH_ option Early printk (DEBUG_LL)
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EA9EC8B@DBDE01.ent.ti.com>
References: <5040D03B.2050304@ti.com>
 <20120831171336.GA6978@n2100.arm.linux.org.uk>
 <79CD15C6BA57404B839C016229A409A83EA9EC8B@DBDE01.ent.ti.com>
Message-ID: <alpine.LFD.2.02.1208311422450.1784@xanadu.home>

On Fri, 31 Aug 2012, Hiremath, Vaibhav wrote:

> On Fri, Aug 31, 2012 at 22:43:36, Russell King - ARM Linux wrote:
> > On Fri, Aug 31, 2012 at 08:24:51PM +0530, Vaibhav Hiremath wrote:
> > > Hi Russell & Tony,
> > > 
> > > AM335X EVM (based on AM33XX device) only supports DT boot mode and
> > > doesn't have CONFIG_MACH_AM335XEVM option defined. Some time back during
> > > baseport submission we had aligned that, we won't create separate EVM
> > > options, killing the board file all-together.
> > > 
> > > Having said that, the early printk option (DEBUG_LL) is broken, the
> > > auto-generated file "./include/generated/mach-types.h" still refers to
> > > CONFIG_MACH_AM335XEVM option,
> > > 
> > > #ifdef CONFIG_MACH_AM335XEVM
> > > # ifdef machine_arch_type
> > > #  undef machine_arch_type
> > > #  define machine_arch_type     __machine_arch_type
> > > # else
> > > #  define machine_arch_type     MACH_TYPE_AM335XEVM
> > > # endif
> > > # define machine_is_am335xevm() (machine_arch_type == MACH_TYPE_AM335XEVM)
> > > #else
> > > # define machine_is_am335xevm() (0)
> > > #endif
> > 
> > machine types are entirely meaningless for DT based systems.
> > 
> > > Can you comment on this? Based on that I will submit the patch.
> > 
> > Pointless.  You can't use machine_is_am335xevm() when you're using DT.
> > 
> 
> They how do you recommend to resolve early prink issue (required during 
> decompression)?

Right now the best you can do is to have empty stubs that display 
nothing.


Nicolas


From mturquette at ti.com  Fri Aug 31 15:29:06 2012
From: mturquette at ti.com (Mike Turquette)
Date: Fri, 31 Aug 2012 12:29:06 -0700
Subject: [PATCH 1/4] clk: Provide option for clk_get_rate to issue hw for
 new rate
In-Reply-To: <1346415691-13371-2-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
 <1346415691-13371-2-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <20120831192906.31162.97714@nucleus>

Quoting Ulf Hansson (2012-08-31 05:21:28)
> From: Ulf Hansson <ulf.hansson at linaro.org>
> 
> By using CLK_GET_RATE_NOCACHE flag, we tell the clk_get_rate API to
> issue the hw for an updated clock rate. This can be used for a clock
> which rate may be updated without a client necessary modifying it.
> 

I'm glad to see this.  We discussed whether the default behavior should
be cached or from the hardware at length some time back, so having a
flag to support the non-default is great.

> Signed-off-by: Ulf Hansson <ulf.hansson at linaro.org>
> ---
>  drivers/clk/clk.c            |   43 +++++++++++++++++++++++-------------------
>  include/linux/clk-provider.h |    1 +
>  2 files changed, 25 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index efdfd00..d9cbae0 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -558,25 +558,6 @@ int clk_enable(struct clk *clk)
>  EXPORT_SYMBOL_GPL(clk_enable);
>  
>  /**
> - * clk_get_rate - return the rate of clk
> - * @clk: the clk whose rate is being returned
> - *
> - * Simply returns the cached rate of the clk.  Does not query the hardware.  If
> - * clk is NULL then returns 0.
> - */
> -unsigned long clk_get_rate(struct clk *clk)
> -{
> -       unsigned long rate;
> -
> -       mutex_lock(&prepare_lock);
> -       rate = __clk_get_rate(clk);
> -       mutex_unlock(&prepare_lock);
> -
> -       return rate;
> -}
> -EXPORT_SYMBOL_GPL(clk_get_rate);
> -
> -/**
>   * __clk_round_rate - round the given rate for a clk
>   * @clk: round the rate of this clock
>   *
> @@ -702,6 +683,30 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
>  }
>  
>  /**
> + * clk_get_rate - return the rate of clk
> + * @clk: the clk whose rate is being returned
> + *
> + * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
> + * is set, which means a recalc_rate will be issued.
> + * If clk is NULL then returns 0.
> + */
> +unsigned long clk_get_rate(struct clk *clk)
> +{
> +       unsigned long rate;
> +
> +       mutex_lock(&prepare_lock);
> +
> +       if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
> +               __clk_recalc_rates(clk, 0);

This is a bit subtle.  Calling __clk_recalc_rates will walk the subtree
of children recalculating rates as well as firing off notifiers.  Is
this what you want?  If your clock changes rates behind your back AND
has chilren then this is probably the right thing to do.  However you
might be better off with:

	if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
		rate = clk->ops->recalc_rate(clk->hw, clk->parent->rate);

This doesn't update children or fire off notifiers.  What is best for
your platform?

Regards,
Mike

> +
> +       rate = __clk_get_rate(clk);
> +       mutex_unlock(&prepare_lock);
> +
> +       return rate;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_rate);
> +
> +/**
>   * __clk_speculate_rates
>   * @clk: first clk in the subtree
>   * @parent_rate: the "future" rate of clk's parent
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 77335fa..1b15307 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -26,6 +26,7 @@
>  #define CLK_IGNORE_UNUSED      BIT(3) /* do not gate even if unused */
>  #define CLK_IS_ROOT            BIT(4) /* root clk, has no parent */
>  #define CLK_IS_BASIC           BIT(5) /* Basic clk, can't do a to_clk_foo() */
> +#define CLK_GET_RATE_NOCACHE   BIT(6) /* do not use the cached clk rate */
>  
>  struct clk_hw;
>  
> -- 
> 1.7.10


From shawn.guo at linaro.org  Fri Aug 31 02:41:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 14:41:27 +0800
Subject: [PATCH v2 1/4] clk: add of_clk_src_onecell_get() support
In-Reply-To: <1345642590-29905-2-git-send-email-shawn.guo@linaro.org>
References: <1345642590-29905-1-git-send-email-shawn.guo@linaro.org>
 <1345642590-29905-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120831064125.GA3271@r65073-Latitude-D630>

Ping, Mike.

Regards,
Shawn

On Wed, Aug 22, 2012 at 09:36:27PM +0800, Shawn Guo wrote:
> For those SoCs that have hundreds of clock outputs, their clock
> DT bindings could reasonably define #clock-cells as 1 and require
> the client device specify the index of the clock it consumes in the
> cell of its "clocks" phandle.
> 
> Add a generic of_clk_src_onecell_get() function for this purpose.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/clk/clk.c            |   14 ++++++++++++++
>  include/linux/clk-provider.h |    5 +++++
>  2 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index efdfd00..308f058 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1582,6 +1582,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
>  }
>  EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
>  
> +struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
> +{
> +	struct clk_onecell_data *clk_data = data;
> +	unsigned int idx = clkspec->args[0];
> +
> +	if (idx >= clk_data->clk_num) {
> +		pr_err("%s: invalid clock index %d\n", __func__, idx);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return clk_data->clks[idx];
> +}
> +EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
> +
>  /**
>   * of_clk_add_provider() - Register a clock provider for a node
>   * @np: Device node pointer associated with clock provider
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 77335fa..8fe6ec7 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -360,6 +360,11 @@ int of_clk_add_provider(struct device_node *np,
>  void of_clk_del_provider(struct device_node *np);
>  struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
>  				  void *data);
> +struct clk_onecell_data {
> +	struct clk **clks;
> +	unsigned int clk_num;
> +};
> +struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
>  const char *of_clk_get_parent_name(struct device_node *np, int index);
>  void of_clk_init(const struct of_device_id *matches);
>  
> -- 
> 1.7.5.4
> 



From shawn.guo at linaro.org  Fri Aug 31 02:42:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 31 Aug 2012 14:42:38 +0800
Subject: [PATCH v3 0/3] Add a generic cpufreq-cpu0 driver
In-Reply-To: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
References: <1344577046-14847-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120831064236.GB3271@r65073-Latitude-D630>

Ping, Rafael.

Regards,
Shawn

On Fri, Aug 10, 2012 at 01:37:22PM +0800, Shawn Guo wrote:
> Patch "cpufreq: Add a generic cpufreq-cpu0 driver" has a dependency
> on following branch.
> 
>  git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git topic/tol
> 
> Changes since v2:
> * Drop patch "regulator: add a new API regulator_set_voltage_tol()",
>   which has been applied on regulator tree as above.
> * Rewrite function of_init_opp_table to make it concise.
>   
> Regards,
> Shawn
> 
> Richard Zhao (1):
>   ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp
> 
> Shawn Guo (2):
>   PM / OPP: Initialize OPP table from device tree
>   cpufreq: Add a generic cpufreq-cpu0 driver
> 
>  .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt   |   55 ++++
>  Documentation/devicetree/bindings/power/opp.txt    |   25 ++
>  arch/arm/kernel/smp.c                              |   54 ++++
>  drivers/base/power/opp.c                           |   47 ++++
>  drivers/cpufreq/Kconfig                            |   11 +
>  drivers/cpufreq/Makefile                           |    2 +
>  drivers/cpufreq/cpufreq-cpu0.c                     |  271 ++++++++++++++++++++
>  include/linux/opp.h                                |    8 +
>  8 files changed, 473 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
>  create mode 100644 Documentation/devicetree/bindings/power/opp.txt
>  create mode 100644 drivers/cpufreq/cpufreq-cpu0.c
> 
> -- 
> 1.7.5.4
> 
> 



From davem at davemloft.net  Fri Aug 31 15:49:31 2012
From: davem at davemloft.net (David Miller)
Date: Fri, 31 Aug 2012 15:49:31 -0400 (EDT)
Subject: [PATCH v2] cs89x0 : packet reception not working
In-Reply-To: <1346104431-3784-1-git-send-email-jaccon.bastiaansen@gmail.com>
References: <1346104431-3784-1-git-send-email-jaccon.bastiaansen@gmail.com>
Message-ID: <20120831.154931.1463711821590835826.davem@davemloft.net>

From: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>
Date: Mon, 27 Aug 2012 23:53:51 +0200

> The RxCFG register of the CS89x0 could be configured incorrectly
> (because of misplaced parentheses), resulting in the disabling
> of packet reception.
> 
> Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen at gmail.com>

Applied and queued up for -stable, thanks.


From lauraa at codeaurora.org  Fri Aug 31 16:46:54 2012
From: lauraa at codeaurora.org (Laura Abbott)
Date: Fri, 31 Aug 2012 13:46:54 -0700
Subject: CMA page migration failure due to buffers on bh_lru
In-Reply-To: <503EBBD6.5080504@codeaurora.org>
References: <503EBBD6.5080504@codeaurora.org>
Message-ID: <504122BE.8080706@codeaurora.org>

On 8/29/2012 6:03 PM, Laura Abbott wrote:

> My quick and dirty workaround for testing is to remove the GFP_MOVABLE
> flag from find_or_create_page but this seems significantly less than
> optimal. Ideally, it seems like the buffers should be evicted from the
> LRU when trying to drop (expand on invalid_bh_lru?) but I'm not familiar
> enough with the code path to know if this is a good approach.
>
> Any suggestions/feedback is appreciated. Thanks.
>
> Laura

I came up with what I think is a reasonable fix to this. Feedback is 
appreciated. Thanks.

Laura


8<---

diff --git a/fs/buffer.c b/fs/buffer.c
index ad5938c..daa0c3d 100644
--- a/fs/buffer.c
+++ b/fs/buffer.c
@@ -1399,12 +1399,49 @@ static bool has_bh_in_lru(int cpu, void *dummy)
  	return 0;
  }

+static void __evict_bh_lru(void *arg)
+{
+	struct bh_lru *b = &get_cpu_var(bh_lrus);
+	struct buffer_head *bh = arg;
+	int i;
+
+	for (i = 0; i < BH_LRU_SIZE; i++) {
+		if (b->bhs[i] == bh) {
+			brelse(b->bhs[i]);
+			b->bhs[i] = NULL;
+			goto out;
+		}
+	}
+out:
+	put_cpu_var(bh_lrus);
+}
+
+static bool bh_exists_in_lru(int cpu, void *arg)
+{
+	struct bh_lru *b = per_cpu_ptr(&bh_lrus, cpu);
+	struct buffer_head *bh = arg;
+	int i;
+
+	for (i = 0; i < BH_LRU_SIZE; i++) {
+		if (b->bhs[i] == bh)
+			return 1;
+	}
+
+	return 0;
+
+}
  void invalidate_bh_lrus(void)
  {
  	on_each_cpu_cond(has_bh_in_lru, invalidate_bh_lru, NULL, 1, GFP_KERNEL);
  }
  EXPORT_SYMBOL_GPL(invalidate_bh_lrus);

+void evict_bh_lrus(struct buffer_head *bh)
+{
+	on_each_cpu_cond(bh_exists_in_lru, __evict_bh_lru, bh, 1, GFP_ATOMIC);
+}
+EXPORT_SYMBOL_GPL(evict_bh_lrus);
+
  void set_bh_page(struct buffer_head *bh,
  		struct page *page, unsigned long offset)
  {
@@ -3052,6 +3089,7 @@ drop_buffers(struct page *page, struct buffer_head 
**buffers_to_free)

  	bh = head;
  	do {
+		evict_bh_lrus(bh);
  		if (buffer_write_io_error(bh) && page->mapping)
  			set_bit(AS_EIO, &page->mapping->flags);
  		if (buffer_busy(bh))
-- 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation


From sylvester.nawrocki at gmail.com  Fri Aug 31 16:47:15 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Fri, 31 Aug 2012 22:47:15 +0200
Subject: [PATCH 3/8] i2c: at91: use an id table for SoC dependent
 parameters
In-Reply-To: <5040CF80.8060201@atmel.com>
References: <1346404884-18451-1-git-send-email-ludovic.desroches@atmel.com>
 <1346404884-18451-4-git-send-email-ludovic.desroches@atmel.com>
 <20120831142944.GA23867@game.jcrosoft.org> <5040CF80.8060201@atmel.com>
Message-ID: <504122D3.70507@gmail.com>

On 08/31/2012 04:51 PM, Nicolas Ferre wrote:
>>> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
>>> index f2112f9..0bc91e5 100644
>>> --- a/arch/arm/mach-at91/at91rm9200.c
>>> +++ b/arch/arm/mach-at91/at91rm9200.c
>>> @@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
>>>   	CLKDEV_CON_DEV_ID("pclk", "ssc.0",&ssc0_clk),
>>>   	CLKDEV_CON_DEV_ID("pclk", "ssc.1",&ssc1_clk),
>>>   	CLKDEV_CON_DEV_ID("pclk", "ssc.2",&ssc2_clk),
>>> -	CLKDEV_CON_DEV_ID(NULL, "at91_i2c",&twi_clk),
>>> +	CLKDEV_CON_DEV_ID(NULL, "at91rm9200_i2c",&twi_clk),
>> use i2c-xxx as on other drivers
>>
>> and I do not like to have platform_device_id
> 
> Me, I like it and find this implementation very elegant.
> 
>> as we need to touch the driver to add a new soc
> 
> So what? We still keep the compatibility if the new SoC has it
> compatibility assured with previous revision: there is nothing to modify.

I agree. The driver would need to be touched to support new SoC only if
the IP there have had some differences, which would have needed to be 
resolved anyway.

>> please use platform data

Using platform data for the dt platforms would have been more troublesome,
wouldn't it ? I like Ludovic's approach which handles both: dt and non-dt 
cases in uniform way from the driver's POV.

> No, it does not have to be exposed to the user: these data are highly
> dependent on the actual hardware (IP revision in fact). So, no need to
> mess with platform data.

Agreed.
 
> So I will acknowledge Ludo's patches.
> 
> Bye,

--

Regards,
Sylwester


From ben at decadent.org.uk  Fri Aug 31 17:11:55 2012
From: ben at decadent.org.uk (Ben Hutchings)
Date: Fri, 31 Aug 2012 14:11:55 -0700
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <20120830191412.GC18957@n2100.arm.linux.org.uk>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
 <20120830172304.GA18957@n2100.arm.linux.org.uk>
 <20120830183711.GY19437@titan.lakedaemon.net>
 <20120830191412.GC18957@n2100.arm.linux.org.uk>
Message-ID: <1346447515.13980.19.camel@deadeye.wl.decadent.org.uk>

On Thu, 2012-08-30 at 20:14 +0100, Russell King - ARM Linux wrote:
> On Thu, Aug 30, 2012 at 02:37:11PM -0400, Jason Cooper wrote:
> > On Thu, Aug 30, 2012 at 06:23:04PM +0100, Russell King - ARM Linux wrote:
> > > On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> > > > I've CC'd stable to see if they want to pick this up.
> > > 
> > > That's not how stable works - and you'll probably receive a standard form
> > > whinge from them about that.  Please read up on the submission requirements
> > > to the stable kernel trees.
> > 
> > Ah, thanks.  usually, I just add the Cc: line for fixes I send to
> > arm-soc.  Since this patch affects more than just kirkwood/marvell, I
> > didn't feel it was appropriate to pull it in through my tree.
> 
> Yes, you put the Cc: line in the commit, but you don't actually send it
> to that address.
[...]

It's OK to cc the stable address when submitting to the relevant
subsystem maintainer *as well as* including the cc: line in the commit
message.  It just can't be used as a substitute for the commit line.

Ben.

-- 
Ben Hutchings
Theory and practice are closer in theory than in practice.
                                - John Levine, moderator of comp.compilers
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From linus.walleij at linaro.org  Fri Aug 31 18:28:29 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 00:28:29 +0200
Subject: [PATCH 1/6] gpio/mxs: adopt irq_domain support for mxs gpio driver
In-Reply-To: <20120824010904.GN24242@S2101-09.ap.freescale.net>
References: <1345472400-31262-1-git-send-email-shawn.guo@linaro.org>
 <1345472400-31262-2-git-send-email-shawn.guo@linaro.org>
 <CACRpkdbSaa6ZOZYB1Cm7WjW0O51kvwsTAxhjefEKd-7XaBB3dw@mail.gmail.com>
 <20120824010904.GN24242@S2101-09.ap.freescale.net>
Message-ID: <CACRpkdYhxxPw5Chw0U6gqc0cuSTpC5aMYV==dqbqBT=xnOO9Hg@mail.gmail.com>

On Fri, Aug 24, 2012 at 3:09 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Thu, Aug 23, 2012 at 11:49:50PM +0200, Linus Walleij wrote:
>> On Mon, Aug 20, 2012 at 4:19 PM, Shawn Guo <shawn.guo at linaro.org> wrote:
>>
>> > Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio
>> > driver adopt irqdomain support, so that we can have the mapping
>> > between gpio and irq number available without using virtual_irq_start
>> > and MXS_GPIO_IRQ_START.
>> >
>> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>> > Cc: Linus Walleij <linus.walleij at linaro.org>
>>
>> OK patch applied, thanks!
>>
> I was planning to have the patch to go via arm-soc tree with your ACK.
> But it also works to have it on gpio tree and I ask arm-soc people to
> pull gpio tree into arm-soc, but you need to ensure the branch is
> stable (no rebase).

OK sorry (and sorry for the delay) I took the patch out again, please take
this through your tree as needed.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours.
Linus Walleij


From linux at arm.linux.org.uk  Fri Aug 31 18:32:19 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 31 Aug 2012 23:32:19 +0100
Subject: [PATCH v2] ARM: Build dtb files in all target
In-Reply-To: <1346447515.13980.19.camel@deadeye.wl.decadent.org.uk>
References: <1346303687-7795-1-git-send-email-andrew@lunn.ch>
 <20120830165224.GR19437@titan.lakedaemon.net>
 <20120830172304.GA18957@n2100.arm.linux.org.uk>
 <20120830183711.GY19437@titan.lakedaemon.net>
 <20120830191412.GC18957@n2100.arm.linux.org.uk>
 <1346447515.13980.19.camel@deadeye.wl.decadent.org.uk>
Message-ID: <20120831223219.GA6906@n2100.arm.linux.org.uk>

On Fri, Aug 31, 2012 at 02:11:55PM -0700, Ben Hutchings wrote:
> On Thu, 2012-08-30 at 20:14 +0100, Russell King - ARM Linux wrote:
> > On Thu, Aug 30, 2012 at 02:37:11PM -0400, Jason Cooper wrote:
> > > On Thu, Aug 30, 2012 at 06:23:04PM +0100, Russell King - ARM Linux wrote:
> > > > On Thu, Aug 30, 2012 at 12:52:24PM -0400, Jason Cooper wrote:
> > > > > I've CC'd stable to see if they want to pick this up.
> > > > 
> > > > That's not how stable works - and you'll probably receive a standard form
> > > > whinge from them about that.  Please read up on the submission requirements
> > > > to the stable kernel trees.
> > > 
> > > Ah, thanks.  usually, I just add the Cc: line for fixes I send to
> > > arm-soc.  Since this patch affects more than just kirkwood/marvell, I
> > > didn't feel it was appropriate to pull it in through my tree.
> > 
> > Yes, you put the Cc: line in the commit, but you don't actually send it
> > to that address.
> [...]
> 
> It's OK to cc the stable address when submitting to the relevant
> subsystem maintainer *as well as* including the cc: line in the commit
> message.  It just can't be used as a substitute for the commit line.

No it is not.  It seems you also need to read
Documentation/stable_kernel_rules.txt

There are two ways to submit patches to the stable team:

1. send the patch to stable at vger.kernel.org _with_ the upstream commit
   ID _included_ in the message.

You can't get that until it's been merged into the upstream tree, so you
can't send it to stable at vger.kernel.org _until_ a maintainer has taken it
and given you the ID.

2. Add the Cc: tag to the commit and let it be picked up automatically
   by the stable team when it hits mainline kernels.

There are no other options.  Definitely Cc'ing the stable address upon
initial submission to the subsystem maintainer is _out_ of the question.


From linus.walleij at linaro.org  Fri Aug 31 18:44:10 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 00:44:10 +0200
Subject: [PATCH] GPIO: Add support for GPIO on CLPS711X-target platform
In-Reply-To: <20120824074552.97d32478.shc_work@mail.ru>
References: <1345635383-12224-1-git-send-email-shc_work@mail.ru>
 <CACRpkdZrcBLz+sg-AwWnBD0SA697uWQzocUYnbC1nPYG14LYyA@mail.gmail.com>
 <20120824074552.97d32478.shc_work@mail.ru>
Message-ID: <CACRpkdZEh1sg5h5-uzpsYwxYM5W47q-1hk4sS3=dQQLaVUC1Vw@mail.gmail.com>

On Fri, Aug 24, 2012 at 5:45 AM, Alexander Shiyan <shc_work at mail.ru> wrote:
> On Fri, 24 Aug 2012 00:08:45 +0200
> Linus Walleij <linus.walleij at linaro.org> wrote:
>
> ...
>> > +static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
>> > +{
>> > +       int ret;
>> > +       struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
>> > +
>> > +       mutex_lock(&gpio->lock);
>> > +       ret = clps_readb(gpio_clps711x_port_dataaddr(chip)) & (1 << offset);
>> > +       mutex_unlock(&gpio->lock);
>> > +
>> > +       return !!ret;
>> > +}
>>
>> Please get rid of this clps_readb() business. I can see it's just this:
>> #define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
>>
>> This makes stuff hard to understand, please pass the virtual base as
>> a memory resource to the platform device, store it in the state holder
>> and just use readb() in the driver from that offset.
>
> This will break the whole concept of this platform. All the CPU registers
> are in one particular area, and therefore access to the registers of all
> the drivers performed using the macro.
> Maybe just add a short comment?

It does not break if you pass the offset CLPS711X_VIRT_BASE as
a memory resource and reference from that, e.g.:

Add a base:

struct clps711x_gpio {
       struct gpio_chip       chip[CLPS711X_GPIO_PORTS];
       struct mutex            lock;
+     void __iomem         *base;
};

Fish out the base from the platform device (provided it's added to
the platform device) in .probe:

res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!res) {
        ret = -ENOENT;
        goto out;
}
gpio->base = res->start;

The access registers like this:

foo = readb(gpio->base + gpio_clps711x_port_diraddr(chip));

It's no big change, just that the offset is included in every
access instead of using custom accessor functions which
are in an obscure <mach/*> header, and we want to get rid
of all such headers.

If you do this, you should no longer need to include
<mach/hardware.h> (or something more is wrong...)

BTW I cannot see where this patch adds the platform device
named "gpio-clps711x"? Are you intending to do this later?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 18:46:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 00:46:50 +0200
Subject: [PATCH 0/3] ARM: EXYNOS: Add support for GPIO on Exynos4x12
In-Reply-To: <CAJuYYwTBeCczF7M=9pJzYUgGB3Xg1md2kRDKbYEU-ji-C1_hug@mail.gmail.com>
References: <4648723.rWnut7F0uJ@amdc1227>
 <CAJuYYwTBeCczF7M=9pJzYUgGB3Xg1md2kRDKbYEU-ji-C1_hug@mail.gmail.com>
Message-ID: <CACRpkdaMqvQOUETPKFuzBw1bW+GciHLE1uvtdkPV5FoxrowftQ@mail.gmail.com>

On Tue, Aug 28, 2012 at 4:58 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> On 28 August 2012 15:31, Tomasz Figa <t.figa at samsung.com> wrote:

>> This patch series makes necessary preparations and adds support for GPIO on
>> Exynos4x12 SoCs.
>
> Hopefully, we can get device tree support merged for Exynos4412 soon
> and then switch over to using pinctrl driver. That can simplfy the
> gpio/pinmux support for Exynos4 SoC's.

This sounds like a NACK.

I will not merge these patches until Ben or Kukjin (the Samsung
maintainers listed in MAINTAINERS) ACK it.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 18:52:11 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 00:52:11 +0200
Subject: [PATCH] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <201208252353.59345.heiko@sntech.de>
References: <201208252353.59345.heiko@sntech.de>
Message-ID: <CACRpkdZws9ifr3WLKGJ-Mz0uYY5=itcd0GmnZYXBOTN7AkU=nQ@mail.gmail.com>

On Sat, Aug 25, 2012 at 11:53 PM, Heiko St?bner <heiko at sntech.de> wrote:

> Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
> via the device tree. This patch implements dt-support for the
> s3c24xx arches.
>
> The controllers contain only 3 cells, as the underlying gpio controller
> does not support controlling the drive strength on a gpio level.
>
> Tested with the gpio-keys driver on a s3c2416 based machine.
>
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>

I cannot figure out if you guys have reached consensus on this
patch or not.

I guess this will go through the Samsung tree in any case, I have no
objections from a GPIO subsystem point of view.

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:07:50 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:07:50 +0200
Subject: [PATCH v2] gpio: samsung: add devicetree init for s3c24xx arches
In-Reply-To: <503D4FB1.1020206@samsung.com>
References: <201208282355.44268.heiko@sntech.de> <503D4FB1.1020206@samsung.com>
Message-ID: <CACRpkdYqYhtHHVw8C5HhDr96V6diV-0M+55xCHnoATOiyDp3Jg@mail.gmail.com>

On Wed, Aug 29, 2012 at 1:09 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 08/28/12 14:55, Heiko St?bner wrote:
>>
>> Until now the Exynos-SoC was the only Samsung-SoC supporting the GPIOs
>> via the device tree. This patch implements dt-support for the
>> s3c24xx arches.
>>
>> The controllers contain only 3 cells, as the underlying gpio controller
>> does not support controlling the drive strength on a gpio level.
>>
>> Tested with the gpio-keys driver on a s3c2416 based machine.
>>
>> Signed-off-by: Heiko Stuebner<heiko at sntech.de>
>> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>
>
>
> Yeah, looks good to me...
>
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>

OK are you taking this into the Samsung tree or shall I take care of it?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:10:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:10:23 +0200
Subject: [PATCH v2 0/3] MFD/GPIO: Add twl6040 GPO driver
In-Reply-To: <503F2F5B.6020304@ti.com>
References: <1345119195-7490-1-git-send-email-peter.ujfalusi@ti.com>
 <503F2F5B.6020304@ti.com>
Message-ID: <CACRpkdakhoM1-+muCy2F73dEy4Ta4DBsag49cNy16EDRQ5csUw@mail.gmail.com>

On Thu, Aug 30, 2012 at 11:16 AM, Peter Ujfalusi <peter.ujfalusi at ti.com> wrote:

> Hi Samuel, Linus,
(...)
> Did you had time to look at this series? Do you want me to resend it?

I have provided my ACK on the GPIO part assuming you're taking this
series through the MFD tree. There is not more I can do...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:16:26 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:16:26 +0200
Subject: [PATCH 5/9] ARM: OMAP2+: Remove hardcoded twl4030 gpio_base,
 irq_base and irq_end
In-Reply-To: <20120831005230.28732.1131.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <20120831005230.28732.1131.stgit@muffinssi.local>
Message-ID: <CACRpkdZdvK+fB8rJFU6sLALjVx1SMBRH9pvg8shkmuzbZGt8xg@mail.gmail.com>

On Fri, Aug 31, 2012 at 2:52 AM, Tony Lindgren <tony at atomide.com> wrote:

> We can't use hardcoded interrupts for SPARSE_IRQ, and can replace
> the hardcoded gpio_base with twl_gpiochip.base after it's been
> allocated.
>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Oh, cool.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:17:20 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:17:20 +0200
Subject: [PATCH 6/9] ARM: OMAP: Move gpio.h to include/linux/platform_data
In-Reply-To: <20120831005234.28732.10624.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <20120831005234.28732.10624.stgit@muffinssi.local>
Message-ID: <CACRpkdb7ozr8uxTDudVPMF5Lcr3FMtDLo9RUm-hvqbVUCHji6w@mail.gmail.com>

On Fri, Aug 31, 2012 at 2:52 AM, Tony Lindgren <tony at atomide.com> wrote:

> This way we can remove includes of plat/gpio.h which won't work
> with the single zImage support.
>
> Note that we also remove the cpu_class_is_omap2() check
> in gpio-omap.c as the drivers should not call it as we need to
> make it local to arch/arm/mach-omap2 for single zImage support.
>
> While at it, arrange the related includes in the standard way.
>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: linux-mtd at lists.infradead.org
> Cc: alsa-devel at alsa-project.org
> Acked-by: Tony Lindgren <tony at atomide.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:27:28 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:27:28 +0200
Subject: [rtc-linux] [PATCH 1/1] drivers/rtc/rtc-ab8500.c: Revoke Device
 Tree enablement
In-Reply-To: <20120831110818.GA5962@gmail.com>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
 <1344527828-6283-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdZa-72QogrZ-P5jbDHTTX64babZo3ydjzfgC-4LWUBfMg@mail.gmail.com>
 <20120831110818.GA5962@gmail.com>
Message-ID: <CACRpkdat3zj_47r7ENz7Qv3N8cNOSKDV+k5em9DjOhkNycy9gQ@mail.gmail.com>

On Fri, Aug 31, 2012 at 1:08 PM, Lee Jones <lee.jones at linaro.org> wrote:
> On Tue, Aug 14, 2012 at 10:32:02AM +0200, Linus Walleij wrote:
>> On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>
>> > All AB8500 devices are now registered via MFD core, so Device Tree
>> > capability is no longer required for probing. Here we pull the DT
>> > match table to ensure we're no longer probed during Device Tree
>> > start-up.
>> >
>> > CC: Alessandro Zummo <a.zummo at towertech.it>
>> > CC: rtc-linux at googlegroups.com
>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>
> I'm guessing we still need Alessandro's Ack?

Well, usually we have Andrew Morton merging patches for RTC, so
put him on CC.

If I was the MFD maintainer I'd just merge this though, it's quite
obvious.

Sam: do you agree?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:28:34 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:28:34 +0200
Subject: [rtc-linux] [PATCH 1/1] drivers/rtc/rtc-ab8500.c: Revoke Device
 Tree enablement
In-Reply-To: <CACRpkdat3zj_47r7ENz7Qv3N8cNOSKDV+k5em9DjOhkNycy9gQ@mail.gmail.com>
References: <1344527828-6283-1-git-send-email-lee.jones@linaro.org>
 <1344527828-6283-3-git-send-email-lee.jones@linaro.org>
 <CACRpkdZa-72QogrZ-P5jbDHTTX64babZo3ydjzfgC-4LWUBfMg@mail.gmail.com>
 <20120831110818.GA5962@gmail.com>
 <CACRpkdat3zj_47r7ENz7Qv3N8cNOSKDV+k5em9DjOhkNycy9gQ@mail.gmail.com>
Message-ID: <CACRpkdbXwLXoWL+PS-wJ9cbztC-jWhyc=vr+98ffg70f6coaiQ@mail.gmail.com>

On Sat, Sep 1, 2012 at 1:27 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Fri, Aug 31, 2012 at 1:08 PM, Lee Jones <lee.jones at linaro.org> wrote:
>> On Tue, Aug 14, 2012 at 10:32:02AM +0200, Linus Walleij wrote:
>>> On Thu, Aug 9, 2012 at 5:57 PM, Lee Jones <lee.jones at linaro.org> wrote:
>>>
>>> > All AB8500 devices are now registered via MFD core, so Device Tree
>>> > capability is no longer required for probing. Here we pull the DT
>>> > match table to ensure we're no longer probed during Device Tree
>>> > start-up.
>>> >
>>> > CC: Alessandro Zummo <a.zummo at towertech.it>
>>> > CC: rtc-linux at googlegroups.com
>>> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
>>>
>>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>>
>> I'm guessing we still need Alessandro's Ack?
>
> Well, usually we have Andrew Morton merging patches for RTC, so
> put him on CC.
>
> If I was the MFD maintainer I'd just merge this though, it's quite
> obvious.
>
> Sam: do you agree?

Or wait, Sam was not on the To: line...

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:32:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:32:55 +0200
Subject: [PATCH 0/4] clk: Support for smp_twd clock for ux500
In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com>
Message-ID: <CACRpkdbymhVyWrvRpoZHYp9FanO1As0dnEVJ5tSQm9AGE6-gBQ@mail.gmail.com>

On Fri, Aug 31, 2012 at 2:21 PM, Ulf Hansson <ulf.hansson at stericsson.com> wrote:

> From: Ulf Hansson <ulf.hansson at linaro.org>
>
> To implement support for the smp_twd clock for ux500 several steps
> was needed. This patchseries has also proposed some new changes in the
> common clock core, which the ux500 smp_twd clock definition are
> relying on.

This is a great series,
Acked-by: Linus Walleij <linus.walleij at linaro.org>
For the ux500 parts.

Mike it'd be great if you could merge this once you have the semantics
of [1/4] sorted out with Ulf.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:43:46 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 01:43:46 +0200
Subject: [PATCH 4/4] ARM: ks8695: convert to generic time and clocksource
In-Reply-To: <504057A8.7030302@snapgear.com>
References: <1346264842-20411-1-git-send-email-linus.walleij@linaro.org>
 <504057A8.7030302@snapgear.com>
Message-ID: <CACRpkdZ0Gw5H_yRcN2CmC+F8NtUcySTrLehuzZdWrbDwL4HHWw@mail.gmail.com>

On Fri, Aug 31, 2012 at 8:20 AM, Greg Ungerer <gerg at snapgear.com> wrote:

> Ok, tested on a KS8695 based machine. Boots and runs, obviously
> clock is basically working. But 'date' never shows the time
> increasing:
>
>   # date
>   Thu Jan  1 00:00:00 UTC 1970
>   # date
>   Thu Jan  1 00:00:00 UTC 1970
>   # date
>   Thu Jan  1 00:00:00 UTC 1970
>   #
>
> And yes, that did work before applying this patch :-)

That mean clockevent is running but not clocksource.

And I think that is because I forgot a ~ in the mask for disabling
the T1 timer, so setting up the clockevent disables the clocksource ...

I'll send out a fixed version, plese test!

(BTW I had not clue the 68K maintainer had a platform like
this, fun!)

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 19:49:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 01:49:55 +0200
Subject: [PATCH v2] ARM: ks8695: convert to generic time and clocksource
Message-ID: <1346456995-21572-1-git-send-email-linus.walleij@linaro.org>

Old platforms using ancient gettimeoffset() and other arcane
APIs are standing in the way of cleaning up the ARM kernel.

This is an attempt at blind-coding a generic time and clocksource
driver for the platform by way of a datasheet and looking at the
old code, it'd be great if someone who is actually using this
machine could test it.

If noone volunteers to do this I will instead propose a patch
deleting the machine altogether.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Corrected the mask when setting clockevents from & TMCON_T1EN
  to & ~TMCON_T1EN so it doesn't shut down the clock source.
---
 arch/arm/Kconfig            |   3 +-
 arch/arm/mach-ks8695/time.c | 123 +++++++++++++++++++++++++++++++-------------
 2 files changed, 88 insertions(+), 38 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6d6e18f..e9ce038 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,8 +652,9 @@ config ARCH_KS8695
 	bool "Micrel/Kendin KS8695"
 	select CPU_ARM922T
 	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_USES_GETTIMEOFFSET
 	select NEED_MACH_MEMORY_H
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
 	help
 	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 	  System-on-Chip devices.
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 6974c23..1ba0182 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -25,6 +25,8 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -53,44 +55,68 @@
 /* Timer0 Timeout Counter Register */
 #define T0TC_WATCHDOG		(0xff)		/* Enable watchdog mode */
 
-/*
- * Returns number of ms since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long ks8695_gettimeoffset (void)
+static void ks8695_set_mode(enum clock_event_mode mode,
+			    struct clock_event_device *evt)
 {
-	unsigned long elapsed, tick2, intpending;
+	if (mode == CLOCK_EVT_FEAT_PERIODIC) {
+		u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
+		u32 half = DIV_ROUND_CLOSEST(rate, 2);
+		u32 tmcon;
+
+		/* Disable timer 1 */
+		tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+		tmcon &= ~TMCON_T1EN;
+		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+		/* Both registers need to count down */
+		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+		writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+		/* Re-enable timer1 */
+		tmcon |= TMCON_T1EN;
+		writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+	}
+}
 
-	/*
-	 * Get the current number of ticks.  Note that there is a race
-	 * condition between us reading the timer and checking for an
-	 * interrupt.  We solve this by ensuring that the counter has not
-	 * reloaded between our two reads.
-	 */
-	elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
-	do {
-		tick2 = elapsed;
-		intpending = readl_relaxed(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
-		elapsed = readl_relaxed(KS8695_TMR_VA + KS8695_T1TC) + readl_relaxed(KS8695_TMR_VA + KS8695_T1PD);
-	} while (elapsed > tick2);
-
-	/* Convert to number of ticks expired (not remaining) */
-	elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
-
-	/* Is interrupt pending?  If so, then timer has been reloaded already. */
-	if (intpending)
-		elapsed += (CLOCK_TICK_RATE / HZ);
-
-	/* Convert ticks to usecs */
-	return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+static int ks8695_set_next_event(unsigned long cycles,
+				 struct clock_event_device *evt)
+
+{
+	u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+	u32 tmcon;
+
+	/* Disable timer 1 */
+	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+	tmcon &= ~TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+	/* Both registers need to count down */
+	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+	writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+	/* Re-enable timer1 */
+	tmcon |= TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+	return 0;
 }
 
+static struct clock_event_device clockevent_ks8695 = {
+	.name		= "ks8695_t1tc",
+	.rating		= 300, /* Reasonably fast and accurate clock event */
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.set_next_event	= ks8695_set_next_event,
+	.set_mode	= ks8695_set_mode,
+};
+
 /*
  * IRQ handler for the timer.
  */
 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 {
-	timer_tick();
+	struct clock_event_device *evt = &clockevent_ks8695;
+
+	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 
@@ -102,18 +128,42 @@ static struct irqaction ks8695_timer_irq = {
 
 static void ks8695_timer_setup(void)
 {
-	unsigned long tmout = CLOCK_TICK_RATE / HZ;
 	unsigned long tmcon;
 
-	/* disable timer1 */
+	/* Disable timer 0 and 1 */
 	tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
-	writel_relaxed(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	tmcon &= ~TMCON_T0EN;
+	tmcon &= ~TMCON_T1EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
 
-	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
-	writel_relaxed(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+	/*
+	 * Set up timer 0 to loop indefinately, count 32 bits with TOUT0
+	 * set to zero, then 1 bit with TOUT0 set to 1. The reason we are doing
+	 * this is that it's not allowed to set either register to 0, then the
+	 * behaviour is "unpredictable". This injects a faulty pulse every
+	 * 2^32-1 cycles but we can surely live with that rather than
+	 * complicating the code.
+	 */
+	writel_relaxed(0xFFFFFFFFU, KS8695_TMR_VA + KS8695_T0TC);
+	writel_relaxed(1, KS8695_TMR_VA + KS8695_T0PD);
+	/* Start timer 0 */
+	tmcon |= TMCON_T0EN;
+	writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+	/* Use timer 0 as clocksource */
+	if (clocksource_mmio_init((void *) KS8695_TMR_VA + KS8695_T0TC,
+			"ks8695_t0tc", KS8695_CLOCK_RATE, 300, 32,
+			clocksource_mmio_readl_up))
+		pr_err("timer: failed to initialize KS8695 clock source\n");
 
-	/* re-enable timer1 */
-	writel_relaxed(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+	/*
+	 * Use timer 1 to fire IRQs on the timeline, only support one-shot
+	 * mode and the system will take care of the rest. Minimum 2 cycles
+	 * (one on each counter) maximum 2*2^32, but the API will only
+	 * accept up to a 32bit full word (0xFFFFFFFFU).
+	 */
+	clockevents_config_and_register(&clockevent_ks8695,
+					KS8695_CLOCK_RATE, 2,
+					0xFFFFFFFFU);
 }
 
 static void __init ks8695_timer_init (void)
@@ -126,7 +176,6 @@ static void __init ks8695_timer_init (void)
 
 struct sys_timer ks8695_timer = {
 	.init		= ks8695_timer_init,
-	.offset		= ks8695_gettimeoffset,
 };
 
 void ks8695_restart(char mode, const char *cmd)
-- 
1.7.11.4



From tony at atomide.com  Fri Aug 31 19:52:12 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 16:52:12 -0700
Subject: [PATCH 5/9] ARM: OMAP2+: Remove hardcoded twl4030 gpio_base,
 irq_base and irq_end
In-Reply-To: <20120831005230.28732.1131.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <20120831005230.28732.1131.stgit@muffinssi.local>
Message-ID: <20120831235212.GS1303@atomide.com>

* Tony Lindgren <tony at atomide.com> [120830 17:53]:
> We can't use hardcoded interrupts for SPARSE_IRQ, and can replace
> the hardcoded gpio_base with twl_gpiochip.base after it's been
> allocated.
...

> --- a/include/linux/mfd/twl6040.h
> +++ b/include/linux/mfd/twl6040.h
> @@ -194,7 +194,6 @@ struct twl6040_vibra_data {
>  
>  struct twl6040_platform_data {
>  	int audpwron_gpio;	/* audio power-on gpio */
> -	unsigned int irq_base;
>  
>  	struct twl6040_codec_data *codec;
>  	struct twl6040_vibra_data *vibra;

The platform_data irq_base is not being used it seems..

> @@ -222,7 +221,6 @@ struct twl6040 {
>  	unsigned int mclk;
>  
>  	unsigned int irq;
> -	unsigned int irq_base;
>  	u8 irq_masks_cur;
>  	u8 irq_masks_cache;
>  };

..but irq_base here is still in use as that's where the value from
irq_alloc_descs() is being stored to. So I'll drop the changes to
struct twl6040 from this patch as otherwise twl6040 code won't compile.

Turns out I did not have twl6040 selected in any of the testconfigs
that I ran.

Regards,

Tony


From linus.walleij at linaro.org  Fri Aug 31 20:14:07 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 02:14:07 +0200
Subject: [PATCH v2] ARM: ks8695: convert to generic time and clocksource
In-Reply-To: <1346456995-21572-1-git-send-email-linus.walleij@linaro.org>
References: <1346456995-21572-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CACRpkdY0i77U5kGoNzWj2KwtyJ=ayptNGTE_7=95tJ0v4Tv5xw@mail.gmail.com>

On Sat, Sep 1, 2012 at 1:49 AM, Linus Walleij <linus.walleij at linaro.org> wrote:

> Old platforms using ancient gettimeoffset() and other arcane
> APIs are standing in the way of cleaning up the ARM kernel.
>
> This is an attempt at blind-coding a generic time and clocksource
> driver for the platform by way of a datasheet and looking at the
> old code, it'd be great if someone who is actually using this
> machine could test it.
>
> If noone volunteers to do this I will instead propose a patch
> deleting the machine altogether.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> ChangeLog v1->v2:
> - Corrected the mask when setting clockevents from & TMCON_T1EN
>   to & ~TMCON_T1EN so it doesn't shut down the clock source.

BTW: Greg if this would happen to work - could you try to enable
CONFIG_TICK_ONESHOT and CONFIG_NO_HZ as well to see
if we can work fine in oneshot mode as well?

Yours,
Linus Walleij


From linus.walleij at linaro.org  Fri Aug 31 20:23:48 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 02:23:48 +0200
Subject: [PATCH 2/2] ARM: allow for ATAGS to be configured out when DT
 support is selected
In-Reply-To: <1346361008-7320-2-git-send-email-nicolas.pitre@linaro.org>
References: <1346361008-7320-1-git-send-email-nicolas.pitre@linaro.org>
 <1346361008-7320-2-git-send-email-nicolas.pitre@linaro.org>
Message-ID: <CACRpkdZqgjkOOfR7b9Fs8uixkDAnjj-VFmSfYQ_eN1-GuZtb+Q@mail.gmail.com>

On Thu, Aug 30, 2012 at 11:10 PM, Nicolas Pitre
<nicolas.pitre at linaro.org> wrote:

> Now that ATAGS support is well contained, we can easily remove it from
> the kernel build if so desired.  It has to explicitly be disabled, and
> only when DT support is selected.

I patched this on top of my Integrator patch stack and disabled
the ATAGS, it just works.

Tested-by: Linus Walleij <linus.walleij at linaro.org>

I'd suggest you to put this into Russells tracker then?

Yours,
Linus Walleij


From tony at atomide.com  Fri Aug 31 20:26:20 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 17:26:20 -0700
Subject: [PATCH 1/4] ARM: OMAP: Remove unused old gpio-switch.h
In-Reply-To: <20120901002534.23715.28654.stgit@muffinssi.local>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
Message-ID: <20120901002620.23715.3322.stgit@muffinssi.local>

This is no longer used anywhere.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/include/plat/gpio-switch.h |   54 -------------------------
 1 file changed, 54 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/gpio-switch.h

diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644
index 10da0e0..0000000
--- a/arch/arm/plat-omap/include/plat/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * GPIO switch definitions
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
-#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
-
-#include <linux/types.h>
-
-/* Cover:
- *	high -> closed
- *	low  -> open
- * Connection:
- *	high -> connected
- *	low  -> disconnected
- * Activity:
- *	high -> active
- *	low  -> inactive
- *
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER		0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION	0x0001
-#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY		0x0002
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED		0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT		0x0002
-
-struct omap_gpio_switch {
-	const char *name;
-	s16 gpio;
-	unsigned flags:4;
-	unsigned type:4;
-
-	/* Time in ms to debounce when transitioning from
-	 * inactive state to active state. */
-	u16 debounce_rising;
-	/* Same for transition from active to inactive state. */
-	u16 debounce_falling;
-
-	/* notify board-specific code about state changes */
-	void (* notify)(void *data, int state);
-	void *notify_data;
-};
-
-/* Call at init time only */
-extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
-					int count);
-
-#endif



From tony at atomide.com  Fri Aug 31 20:26:18 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 17:26:18 -0700
Subject: [PATCH 0/4] Series short description
Message-ID: <20120901002534.23715.28654.stgit@muffinssi.local>

Hi all,

Here are the changes needed to make hardware.h local for mach-omap2.
These patches are based on v3.6-rc3 and the following patches:

- Arnd's patch "ARM: omap: move platform_data definitions"
- Igor's series "ARM: OMAP: cleanup plat/board.h file"
- Afzal's series "Prepare for GPMC driver conversion (w.r.t MTD)"
- My series "Clean up hardcoded IRQs for mach-omap2, enable SPARSE_IRQ,
  plaform_data/gpio-omap.h"

Regards,

Tony

---

Tony Lindgren (4):
      ARM: OMAP: Remove unused old gpio-switch.h
      ARM: OMAP: Split plat/hardware.h, introduce local hardware.h and soc.h for omap2+
      ARM: OMAP2+ Move SoC specific headers to be local to mach-omap2
      ARM: OMAP1: Move SoC specific headers from plat to mach for omap1


 arch/arm/mach-omap1/board-htcherald.c          |    4 
 arch/arm/mach-omap1/devices.c                  |    2 
 arch/arm/mach-omap1/include/mach/hardware.h    |  285 +++++++++++++++++++++++
 arch/arm/mach-omap1/include/mach/omap1510.h    |    3 
 arch/arm/mach-omap1/include/mach/omap16xx.h    |    3 
 arch/arm/mach-omap1/include/mach/omap7xx.h     |    3 
 arch/arm/mach-omap2/am33xx.h                   |    0 
 arch/arm/mach-omap2/board-2430sdp.c            |    2 
 arch/arm/mach-omap2/board-3430sdp.c            |    9 -
 arch/arm/mach-omap2/board-4430sdp.c            |    9 -
 arch/arm/mach-omap2/board-am3517crane.c        |    1 
 arch/arm/mach-omap2/board-am3517evm.c          |    1 
 arch/arm/mach-omap2/board-apollon.c            |    3 
 arch/arm/mach-omap2/board-cm-t35.c             |    2 
 arch/arm/mach-omap2/board-cm-t3517.c           |    3 
 arch/arm/mach-omap2/board-devkit8000.c         |   22 +-
 arch/arm/mach-omap2/board-flash.c              |    6 
 arch/arm/mach-omap2/board-generic.c            |    1 
 arch/arm/mach-omap2/board-h4.c                 |    3 
 arch/arm/mach-omap2/board-igep0020.c           |    1 
 arch/arm/mach-omap2/board-ldp.c                |   10 -
 arch/arm/mach-omap2/board-n8x0.c               |   10 -
 arch/arm/mach-omap2/board-omap3beagle.c        |   12 -
 arch/arm/mach-omap2/board-omap3evm.c           |   11 -
 arch/arm/mach-omap2/board-omap3logic.c         |   16 -
 arch/arm/mach-omap2/board-omap3pandora.c       |    9 -
 arch/arm/mach-omap2/board-omap3stalker.c       |   20 +-
 arch/arm/mach-omap2/board-omap3touchbook.c     |    9 -
 arch/arm/mach-omap2/board-omap4panda.c         |    7 -
 arch/arm/mach-omap2/board-overo.c              |   14 -
 arch/arm/mach-omap2/board-rm680.c              |    1 
 arch/arm/mach-omap2/board-rx51.c               |    5 
 arch/arm/mach-omap2/board-ti8168evm.c          |    2 
 arch/arm/mach-omap2/board-zoom-debugboard.c    |    4 
 arch/arm/mach-omap2/board-zoom-display.c       |    4 
 arch/arm/mach-omap2/board-zoom-peripherals.c   |    1 
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c   |    2 
 arch/arm/mach-omap2/clkt_dpll.c                |    2 
 arch/arm/mach-omap2/clock.c                    |    8 -
 arch/arm/mach-omap2/clock2420_data.c           |    2 
 arch/arm/mach-omap2/clock2430.c                |    2 
 arch/arm/mach-omap2/clock2430_data.c           |    2 
 arch/arm/mach-omap2/clock2xxx.c                |    2 
 arch/arm/mach-omap2/clock33xx_data.c           |    2 
 arch/arm/mach-omap2/clock3xxx.c                |    2 
 arch/arm/mach-omap2/clock3xxx_data.c           |    3 
 arch/arm/mach-omap2/clock44xx_data.c           |    3 
 arch/arm/mach-omap2/cm2xxx_3xxx.c              |    3 
 arch/arm/mach-omap2/common.c                   |    2 
 arch/arm/mach-omap2/common.h                   |    6 
 arch/arm/mach-omap2/control.c                  |    2 
 arch/arm/mach-omap2/control.h                  |    2 
 arch/arm/mach-omap2/devices.c                  |    1 
 arch/arm/mach-omap2/dpll3xxx.c                 |    2 
 arch/arm/mach-omap2/dpll44xx.c                 |    2 
 arch/arm/mach-omap2/emu.c                      |    2 
 arch/arm/mach-omap2/gpmc-nand.c                |    5 
 arch/arm/mach-omap2/gpmc-onenand.c             |    5 
 arch/arm/mach-omap2/gpmc-smc91x.c              |    3 
 arch/arm/mach-omap2/gpmc.c                     |    4 
 arch/arm/mach-omap2/hardware.h                 |    6 
 arch/arm/mach-omap2/hsmmc.c                    |    2 
 arch/arm/mach-omap2/i2c.c                      |    1 
 arch/arm/mach-omap2/id.c                       |    2 
 arch/arm/mach-omap2/include/mach/hardware.h    |    2 
 arch/arm/mach-omap2/io.c                       |    3 
 arch/arm/mach-omap2/irq.c                      |    3 
 arch/arm/mach-omap2/mailbox.c                  |    3 
 arch/arm/mach-omap2/mcbsp.c                    |    5 
 arch/arm/mach-omap2/omap-mpuss-lowpower.c      |    3 
 arch/arm/mach-omap2/omap-smp.c                 |    2 
 arch/arm/mach-omap2/omap-wakeupgen.c           |    2 
 arch/arm/mach-omap2/omap24xx.h                 |    2 
 arch/arm/mach-omap2/omap34xx.h                 |    2 
 arch/arm/mach-omap2/omap4-common.c             |    2 
 arch/arm/mach-omap2/omap44xx.h                 |    1 
 arch/arm/mach-omap2/omap54xx.h                 |    0 
 arch/arm/mach-omap2/omap_hwmod.c               |    8 -
 arch/arm/mach-omap2/omap_hwmod_2420_data.c     |    5 
 arch/arm/mach-omap2/omap_hwmod_2430_data.c     |    5 
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c     |    3 
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c     |    1 
 arch/arm/mach-omap2/omap_l3_noc.c              |    3 
 arch/arm/mach-omap2/omap_phy_internal.c        |    3 
 arch/arm/mach-omap2/opp2420_data.c             |    2 
 arch/arm/mach-omap2/opp2430_data.c             |    2 
 arch/arm/mach-omap2/opp3xxx_data.c             |    2 
 arch/arm/mach-omap2/opp4xxx_data.c             |    3 
 arch/arm/mach-omap2/powerdomain.c              |    6 
 arch/arm/mach-omap2/powerdomains3xxx_data.c    |    4 
 arch/arm/mach-omap2/prm2xxx_3xxx.c             |    4 
 arch/arm/mach-omap2/prm44xx.c                  |    4 
 arch/arm/mach-omap2/sdrc2xxx.c                 |    2 
 arch/arm/mach-omap2/sleep24xx.S                |    3 
 arch/arm/mach-omap2/sleep34xx.S                |    2 
 arch/arm/mach-omap2/sleep44xx.S                |    2 
 arch/arm/mach-omap2/soc.h                      |    1 
 arch/arm/mach-omap2/sram242x.S                 |    3 
 arch/arm/mach-omap2/sram243x.S                 |    3 
 arch/arm/mach-omap2/sram34xx.S                 |    3 
 arch/arm/mach-omap2/ti81xx.h                   |    0 
 arch/arm/mach-omap2/timer.c                    |    3 
 arch/arm/mach-omap2/twl-common.c               |    2 
 arch/arm/mach-omap2/usb-host.c                 |    1 
 arch/arm/mach-omap2/usb-musb.c                 |    6 
 arch/arm/mach-omap2/vc.c                       |    3 
 arch/arm/mach-omap2/voltagedomains3xxx_data.c  |    3 
 arch/arm/plat-omap/Makefile                    |    3 
 arch/arm/plat-omap/counter_32k.c               |    2 
 arch/arm/plat-omap/devices.c                   |   91 -------
 arch/arm/plat-omap/dma.c                       |    3 
 arch/arm/plat-omap/include/plat/gpio-switch.h  |   54 ----
 arch/arm/plat-omap/include/plat/hardware.h     |  293 ------------------------
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    2 
 drivers/spi/spi-omap-uwire.c                   |    3 
 drivers/watchdog/omap_wdt.c                    |    5 
 sound/soc/omap/omap-abe-twl6040.c              |    4 
 sound/soc/omap/omap-mcpdm.c                    |    2 
 118 files changed, 475 insertions(+), 687 deletions(-)
 rename arch/arm/{plat-omap/include/plat/omap1510.h => mach-omap1/include/mach/omap1510.h} (97%)
 rename arch/arm/{plat-omap/include/plat/omap16xx.h => mach-omap1/include/mach/omap16xx.h} (99%)
 rename arch/arm/{plat-omap/include/plat/omap7xx.h => mach-omap1/include/mach/omap7xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/am33xx.h => mach-omap2/am33xx.h} (100%)
 create mode 100644 arch/arm/mach-omap2/hardware.h
 rename arch/arm/{plat-omap/include/plat/omap24xx.h => mach-omap2/omap24xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/omap34xx.h => mach-omap2/omap34xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/omap44xx.h => mach-omap2/omap44xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/omap54xx.h => mach-omap2/omap54xx.h} (100%)
 create mode 100644 arch/arm/mach-omap2/soc.h
 rename arch/arm/{plat-omap/include/plat/ti81xx.h => mach-omap2/ti81xx.h} (100%)
 delete mode 100644 arch/arm/plat-omap/devices.c
 delete mode 100644 arch/arm/plat-omap/include/plat/gpio-switch.h
 delete mode 100644 arch/arm/plat-omap/include/plat/hardware.h

-- 
Signature


From tony at atomide.com  Fri Aug 31 20:26:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 17:26:27 -0700
Subject: [PATCH 3/4] ARM: OMAP2+ Move SoC specific headers to be local to
 mach-omap2
In-Reply-To: <20120901002534.23715.28654.stgit@muffinssi.local>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
Message-ID: <20120901002627.23715.85527.stgit@muffinssi.local>

These can now be moved to be local headers in mach-omap2.

Note that this patch removes arch/arm/plat-omap/devices.c as it
will get removed anyways with Paul Walmsley's patch
"ARM: OMAP: split OMAP1, OMAP2+ RNG device registration".

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/am33xx.h               |    0 
 arch/arm/mach-omap2/clock33xx_data.c       |    2 -
 arch/arm/mach-omap2/control.h              |    2 -
 arch/arm/mach-omap2/hardware.h             |   12 ++--
 arch/arm/mach-omap2/omap-mpuss-lowpower.c  |    3 -
 arch/arm/mach-omap2/omap24xx.h             |    2 -
 arch/arm/mach-omap2/omap34xx.h             |    2 -
 arch/arm/mach-omap2/omap44xx.h             |    0 
 arch/arm/mach-omap2/omap54xx.h             |    0 
 arch/arm/mach-omap2/sleep24xx.S            |    3 -
 arch/arm/mach-omap2/sleep34xx.S            |    2 -
 arch/arm/mach-omap2/sleep44xx.S            |    2 -
 arch/arm/mach-omap2/ti81xx.h               |    0 
 arch/arm/plat-omap/Makefile                |    3 -
 arch/arm/plat-omap/devices.c               |   91 ----------------------------
 15 files changed, 13 insertions(+), 111 deletions(-)
 rename arch/arm/{plat-omap/include/plat/am33xx.h => mach-omap2/am33xx.h} (100%)
 rename arch/arm/{plat-omap/include/plat/omap24xx.h => mach-omap2/omap24xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/omap34xx.h => mach-omap2/omap34xx.h} (98%)
 rename arch/arm/{plat-omap/include/plat/omap44xx.h => mach-omap2/omap44xx.h} (100%)
 rename arch/arm/{plat-omap/include/plat/omap54xx.h => mach-omap2/omap54xx.h} (100%)
 rename arch/arm/{plat-omap/include/plat/ti81xx.h => mach-omap2/ti81xx.h} (100%)
 delete mode 100644 arch/arm/plat-omap/devices.c

diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/mach-omap2/am33xx.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/am33xx.h
rename to arch/arm/mach-omap2/am33xx.h
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 25bbcc7..7aa5eca 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -18,8 +18,8 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <plat/clkdev_omap.h>
-#include <plat/am33xx.h>
 
+#include "am33xx.h"
 #include "iomap.h"
 #include "control.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8cdc85..c1a5cab 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,7 +21,7 @@
 #include <mach/ctrl_module_pad_core_44xx.h>
 #include <mach/ctrl_module_pad_wkup_44xx.h>
 
-#include <plat/am33xx.h>
+#include "am33xx.h"
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)					\
diff --git a/arch/arm/mach-omap2/hardware.h b/arch/arm/mach-omap2/hardware.h
index 3c190f9..78f59ec 100644
--- a/arch/arm/mach-omap2/hardware.h
+++ b/arch/arm/mach-omap2/hardware.h
@@ -1,6 +1,6 @@
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/ti81xx.h>
-#include <plat/am33xx.h>
-#include <plat/omap54xx.h>
+#include "omap24xx.h"
+#include "omap34xx.h"
+#include "omap44xx.h"
+#include "ti81xx.h"
+#include "am33xx.h"
+#include "omap54xx.h"
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 637a1bd..ff4e6a0 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -50,9 +50,8 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
-
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap24xx.h
rename to arch/arm/mach-omap2/omap24xx.h
index 92df9e2..641a2c8 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/mach-omap2/omap24xx.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap24xx.h
- *
  * This file contains the processor specific definitions
  * of the TI OMAP24XX.
  *
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap34xx.h
rename to arch/arm/mach-omap2/omap34xx.h
index 0d818ac..c0d1b4b 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/mach-omap2/omap34xx.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap34xx.h
- *
  * This file contains the processor specific definitions of the TI OMAP34XX.
  *
  * Copyright (C) 2007 Texas Instruments.
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/omap44xx.h
rename to arch/arm/mach-omap2/omap44xx.h
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/omap54xx.h
rename to arch/arm/mach-omap2/omap54xx.h
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index d4bf904..ce0ccd2 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -28,8 +28,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/omap24xx.h>
-
+#include "omap24xx.h"
 #include "sdrc.h"
 
 /* First address of reserved address space?  apparently valid for OMAP2 & 3 */
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 3fbe496..5069879 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,9 +26,9 @@
 
 #include <asm/assembler.h>
 
-#include <plat/omap34xx.h>
 #include <plat/sram.h>
 
+#include "omap34xx.h"
 #include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9f6b83d..df7f840 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -14,10 +14,10 @@
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
 #include <mach/omap-secure.h>
 
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/ti81xx.h
rename to arch/arm/mach-omap2/ti81xx.h
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf85..a017e99 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-	 fb.o counter_32k.o
+obj-y := common.o sram.o clock.o dma.o mux.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 287ac37..0000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/devices.c
- *
- * Common platform device setup/initialization for OMAP1 and OMAP2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/memblock.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-
-#include <plat/tc.h>
-#include <plat/mmc.h>
-#include <plat/menelaus.h>
-#include <plat/omap44xx.h>
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-#define	OMAP_RNG_BASE		0x480A0000
-#else
-#define	OMAP_RNG_BASE		0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-	{
-		.start		= OMAP_RNG_BASE,
-		.end		= OMAP_RNG_BASE + 0x4f,
-		.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap_rng_device = {
-	.name		= "omap_rng",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(rng_resources),
-	.resource	= rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-	(void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
-/*
- * This gets called after board-specific INIT_MACHINE, and initializes most
- * on-chip peripherals accessible on this board (except for few like USB):
- *
- *  (a) Does any "standard config" pin muxing needed.  Board-specific
- *	code will have muxed GPIO pins and done "nonstandard" setup;
- *	that code could live in the boot loader.
- *  (b) Populating board-specific platform_data with the data drivers
- *	rely on to handle wiring variations.
- *  (c) Creating platform devices as meaningful on this board and
- *	with this kernel configuration.
- *
- * Claiming GPIOs, and setting their direction and initial values, is the
- * responsibility of the device drivers.  So is responding to probe().
- *
- * Board-specific knowledge like creating devices or pin setup is to be
- * kept out of drivers as much as possible.  In particular, pin setup
- * may be handled by the boot loader, and drivers should expect it will
- * normally have been done by the time they're probed.
- */
-static int __init omap_init_devices(void)
-{
-	/* please keep these calls, and their implementations above,
-	 * in alphabetical order so they're easier to sort through.
-	 */
-	omap_init_rng();
-	return 0;
-}
-arch_initcall(omap_init_devices);



From tony at atomide.com  Fri Aug 31 20:26:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 17:26:30 -0700
Subject: [PATCH 4/4] ARM: OMAP1: Move SoC specific headers from plat to mach
 for omap1
In-Reply-To: <20120901002534.23715.28654.stgit@muffinssi.local>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
Message-ID: <20120901002630.23715.39417.stgit@muffinssi.local>

There's no need to have these in plat-omap any longer. Note that these
could eventually be made local to mach-omap1 instead of being in mach.

But to do that, at least various driver access using omap7xxx.h registers
needs to be fixed first.

Cc: spi-devel-general at lists.sourceforge.net
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/board-htcherald.c       |    4 ++--
 arch/arm/mach-omap1/devices.c               |    2 +-
 arch/arm/mach-omap1/include/mach/hardware.h |    6 +++---
 arch/arm/mach-omap1/include/mach/omap1510.h |    3 +--
 arch/arm/mach-omap1/include/mach/omap16xx.h |    3 +--
 arch/arm/mach-omap1/include/mach/omap7xx.h  |    3 +--
 drivers/spi/spi-omap-uwire.c                |    3 ++-
 7 files changed, 11 insertions(+), 13 deletions(-)
 rename arch/arm/{plat-omap/include/plat/omap1510.h => mach-omap1/include/mach/omap1510.h} (97%)
 rename arch/arm/{plat-omap/include/plat/omap16xx.h => mach-omap1/include/mach/omap16xx.h} (99%)
 rename arch/arm/{plat-omap/include/plat/omap7xx.h => mach-omap1/include/mach/omap7xx.h} (98%)

diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index bdb94fe..4fe4884 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -37,14 +37,14 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/omap7xx.h>
-#include <linux/platform_data/keypad-omap.h>
 #include <plat/mmc.h>
 
+#include <mach/omap7xx.h>
 #include <mach/irqs.h>
 #include <mach/usb.h>
 
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 1feca35..05fdbd9 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -23,8 +23,8 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
-#include <plat/omap7xx.h>
 
+#include <mach/omap7xx.h>
 #include <mach/camera.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index bd3b95e..84248d2 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -311,8 +311,8 @@ static inline u32 omap_cs3_phys(void)
  * ---------------------------------------------------------------------------
  */
 
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
+#include "omap7xx.h"
+#include "omap1510.h"
+#include "omap16xx.h"
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h
similarity index 97%
rename from arch/arm/plat-omap/include/plat/omap1510.h
rename to arch/arm/mach-omap1/include/mach/omap1510.h
index d240046..8fe05d6 100644
--- a/arch/arm/plat-omap/include/plat/omap1510.h
+++ b/arch/arm/mach-omap1/include/mach/omap1510.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap1510.h
- *
+/*
  * Hardware definitions for TI OMAP1510 processor.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme at de.bosch.com>
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/mach-omap1/include/mach/omap16xx.h
similarity index 99%
rename from arch/arm/plat-omap/include/plat/omap16xx.h
rename to arch/arm/mach-omap1/include/mach/omap16xx.h
index e69e1d8..cd1c724 100644
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ b/arch/arm/mach-omap1/include/mach/omap16xx.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap16xx.h
- *
+/*
  * Hardware definitions for TI OMAP1610/5912/1710 processors.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme at de.bosch.com>
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/mach-omap1/include/mach/omap7xx.h
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap7xx.h
rename to arch/arm/mach-omap1/include/mach/omap7xx.h
index 48e4757..63da994 100644
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ b/arch/arm/mach-omap1/include/mach/omap7xx.h
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap7xx.h
- *
+/*
  * Hardware definitions for TI OMAP7XX processor.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme at de.bosch.com>
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 9b0d716..a3996a1 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -53,7 +53,8 @@
 #include <asm/mach-types.h>
 
 #include <plat/mux.h>
-#include <plat/omap7xx.h>	/* OMAP7XX_IO_CONF registers */
+
+#include <mach/omap7xx.h>	/* OMAP7XX_IO_CONF registers */
 
 
 /* FIXME address is now a platform device resource,



From tony at atomide.com  Fri Aug 31 20:26:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 17:26:22 -0700
Subject: [PATCH 2/4] ARM: OMAP: Split plat/hardware.h,
 introduce local hardware.h and soc.h for omap2+
In-Reply-To: <20120901002534.23715.28654.stgit@muffinssi.local>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
Message-ID: <20120901002622.23715.68557.stgit@muffinssi.local>

As the plat and mach includes need to disappear for single zImage work,
we need to remove plat/hardware.h.

Do this by splitting plat/hardware.h into omap1 and omap2+ specific files.

The old plat/hardware.h already has omap1 only defines, so it gets moved
to mach/hardware.h for omap1. For omap2+, we add a new local hardware.h
that for now just includes the related SoC headers to keep this patch more
readable.

To avoid churn in the omap2+ specific files, let's also introduce local
soc.h that includes plat/cpu.h for the revision check. Let's also include
plat/serial.h from common.h for all the board-*.c files. This allows
making the include files local later on without patching these files again.

Note that only minimal changes are done in this patch for the
drivers/watchdog/omap_wdt.c driver to keep things compiling. Further
patches are needed to eventually remove cpu_is_omap usage in the drivers.

Also only minimal changes are done to sound/soc/omap/* to remove the
unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's
no need to include omap44xx.h.

While at it, also sort the includes in the standard way.

Cc: linux-watchdog at vger.kernel.org
Cc: Wim Van Sebroeck <wim at iguana.be>
Cc: alsa-devel at alsa-project.org
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Jarkko Nikula <jarkko.nikula at bitmer.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/include/mach/hardware.h    |  285 +++++++++++++++++++++++
 arch/arm/mach-omap2/board-2430sdp.c            |    2 
 arch/arm/mach-omap2/board-3430sdp.c            |    9 -
 arch/arm/mach-omap2/board-4430sdp.c            |    9 -
 arch/arm/mach-omap2/board-am3517crane.c        |    1 
 arch/arm/mach-omap2/board-am3517evm.c          |    1 
 arch/arm/mach-omap2/board-apollon.c            |    3 
 arch/arm/mach-omap2/board-cm-t35.c             |    2 
 arch/arm/mach-omap2/board-cm-t3517.c           |    3 
 arch/arm/mach-omap2/board-devkit8000.c         |   22 +-
 arch/arm/mach-omap2/board-flash.c              |    6 
 arch/arm/mach-omap2/board-generic.c            |    1 
 arch/arm/mach-omap2/board-h4.c                 |    3 
 arch/arm/mach-omap2/board-igep0020.c           |    1 
 arch/arm/mach-omap2/board-ldp.c                |   10 -
 arch/arm/mach-omap2/board-n8x0.c               |   10 -
 arch/arm/mach-omap2/board-omap3beagle.c        |   12 -
 arch/arm/mach-omap2/board-omap3evm.c           |   11 -
 arch/arm/mach-omap2/board-omap3logic.c         |   16 -
 arch/arm/mach-omap2/board-omap3pandora.c       |    9 -
 arch/arm/mach-omap2/board-omap3stalker.c       |   20 +-
 arch/arm/mach-omap2/board-omap3touchbook.c     |    9 -
 arch/arm/mach-omap2/board-omap4panda.c         |    7 -
 arch/arm/mach-omap2/board-overo.c              |   14 -
 arch/arm/mach-omap2/board-rm680.c              |    1 
 arch/arm/mach-omap2/board-rx51.c               |    5 
 arch/arm/mach-omap2/board-ti8168evm.c          |    2 
 arch/arm/mach-omap2/board-zoom-debugboard.c    |    4 
 arch/arm/mach-omap2/board-zoom-display.c       |    4 
 arch/arm/mach-omap2/board-zoom-peripherals.c   |    1 
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c   |    2 
 arch/arm/mach-omap2/clkt_dpll.c                |    2 
 arch/arm/mach-omap2/clock.c                    |    8 -
 arch/arm/mach-omap2/clock2420_data.c           |    2 
 arch/arm/mach-omap2/clock2430.c                |    2 
 arch/arm/mach-omap2/clock2430_data.c           |    2 
 arch/arm/mach-omap2/clock2xxx.c                |    2 
 arch/arm/mach-omap2/clock3xxx.c                |    2 
 arch/arm/mach-omap2/clock3xxx_data.c           |    3 
 arch/arm/mach-omap2/clock44xx_data.c           |    3 
 arch/arm/mach-omap2/cm2xxx_3xxx.c              |    3 
 arch/arm/mach-omap2/common.c                   |    2 
 arch/arm/mach-omap2/common.h                   |    6 
 arch/arm/mach-omap2/control.c                  |    2 
 arch/arm/mach-omap2/devices.c                  |    1 
 arch/arm/mach-omap2/dpll3xxx.c                 |    2 
 arch/arm/mach-omap2/dpll44xx.c                 |    2 
 arch/arm/mach-omap2/emu.c                      |    2 
 arch/arm/mach-omap2/gpmc-nand.c                |    5 
 arch/arm/mach-omap2/gpmc-onenand.c             |    5 
 arch/arm/mach-omap2/gpmc-smc91x.c              |    3 
 arch/arm/mach-omap2/gpmc.c                     |    4 
 arch/arm/mach-omap2/hardware.h                 |    6 
 arch/arm/mach-omap2/hsmmc.c                    |    2 
 arch/arm/mach-omap2/i2c.c                      |    1 
 arch/arm/mach-omap2/id.c                       |    2 
 arch/arm/mach-omap2/include/mach/hardware.h    |    2 
 arch/arm/mach-omap2/io.c                       |    3 
 arch/arm/mach-omap2/irq.c                      |    3 
 arch/arm/mach-omap2/mailbox.c                  |    3 
 arch/arm/mach-omap2/mcbsp.c                    |    5 
 arch/arm/mach-omap2/omap-smp.c                 |    2 
 arch/arm/mach-omap2/omap-wakeupgen.c           |    2 
 arch/arm/mach-omap2/omap4-common.c             |    2 
 arch/arm/mach-omap2/omap_hwmod.c               |    8 -
 arch/arm/mach-omap2/omap_hwmod_2420_data.c     |    5 
 arch/arm/mach-omap2/omap_hwmod_2430_data.c     |    5 
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c     |    3 
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c     |    1 
 arch/arm/mach-omap2/omap_l3_noc.c              |    3 
 arch/arm/mach-omap2/omap_phy_internal.c        |    3 
 arch/arm/mach-omap2/opp2420_data.c             |    2 
 arch/arm/mach-omap2/opp2430_data.c             |    2 
 arch/arm/mach-omap2/opp3xxx_data.c             |    2 
 arch/arm/mach-omap2/opp4xxx_data.c             |    3 
 arch/arm/mach-omap2/powerdomain.c              |    6 
 arch/arm/mach-omap2/powerdomains3xxx_data.c    |    4 
 arch/arm/mach-omap2/prm2xxx_3xxx.c             |    4 
 arch/arm/mach-omap2/prm44xx.c                  |    4 
 arch/arm/mach-omap2/sdrc2xxx.c                 |    2 
 arch/arm/mach-omap2/sleep34xx.S                |    2 
 arch/arm/mach-omap2/soc.h                      |    1 
 arch/arm/mach-omap2/sram242x.S                 |    3 
 arch/arm/mach-omap2/sram243x.S                 |    3 
 arch/arm/mach-omap2/sram34xx.S                 |    3 
 arch/arm/mach-omap2/timer.c                    |    3 
 arch/arm/mach-omap2/twl-common.c               |    2 
 arch/arm/mach-omap2/usb-host.c                 |    1 
 arch/arm/mach-omap2/usb-musb.c                 |    6 
 arch/arm/mach-omap2/vc.c                       |    3 
 arch/arm/mach-omap2/voltagedomains3xxx_data.c  |    3 
 arch/arm/plat-omap/counter_32k.c               |    2 
 arch/arm/plat-omap/dma.c                       |    3 
 arch/arm/plat-omap/include/plat/hardware.h     |  293 ------------------------
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    2 
 arch/arm/plat-omap/include/plat/omap44xx.h     |    1 
 drivers/watchdog/omap_wdt.c                    |    5 
 sound/soc/omap/omap-abe-twl6040.c              |    4 
 sound/soc/omap/omap-mcpdm.c                    |    2 
 99 files changed, 461 insertions(+), 519 deletions(-)
 create mode 100644 arch/arm/mach-omap2/hardware.h
 create mode 100644 arch/arm/mach-omap2/soc.h
 delete mode 100644 arch/arm/plat-omap/include/plat/hardware.h

diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index 01e35fa..bd3b95e 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -1,11 +1,46 @@
 /*
  * arch/arm/mach-omap1/include/mach/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *	 file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon at ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony at atomide.com>
+ *                          and Dirk Behme <dirk.behme at de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
 
+#include <asm/sizes.h>
 #ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <plat/cpu.h>
+
 /*
  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
  */
@@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void)
 			? 0 : OMAP_CS3_PHYS;
 }
 
+#endif	/* ifndef __ASSEMBLER__ */
+
+#include <plat/serial.h>
+
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *	 files.
+ * ---------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE	(0xfffec500)
+#define OMAP_MPU_TIMER2_BASE	(0xfffec600)
+#define OMAP_MPU_TIMER3_BASE	(0xfffec700)
+#define MPU_TIMER_FREE		(1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE	(1 << 5)
+#define MPU_TIMER_AR		(1 << 1)
+#define MPU_TIMER_ST		(1 << 0)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE		(0xfffece00)
+#define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)
+
+#define CK_RATEF		1
+#define CK_IDLEF		2
+#define CK_ENABLEF		4
+#define CK_SELECTF		8
+#define SETARM_IDLE_SHIFT
+
+/* DPLL control registers */
+#define DPLL_CTL		(0xfffecf00)
+
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
+#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
+#define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
+#define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)
+
+/*
+ * ---------------------------------------------------------------------------
+ * UPLD
+ * ---------------------------------------------------------------------------
+ */
+#define ULPD_REG_BASE		(0xfffe0800)
+#define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
+#	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
+#	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
+#define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
+#	define SOFT_UDC_REQ		(1 << 4)
+#	define SOFT_USB_CLK_REQ		(1 << 3)
+#	define SOFT_DPLL_REQ		(1 << 0)
+#define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
+#	define DIS_MMC2_DPLL_REQ	(1 << 11)
+#	define DIS_MMC1_DPLL_REQ	(1 << 10)
+#	define DIS_UART3_DPLL_REQ	(1 << 9)
+#	define DIS_UART2_DPLL_REQ	(1 << 8)
+#	define DIS_UART1_DPLL_REQ	(1 << 7)
+#	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* Watchdog timer within the OMAP3.2 gigacell */
+#define OMAP_MPU_WATCHDOG_BASE	(0xfffec800)
+#define OMAP_WDT_TIMER		(OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE	(OMAP_MPU_WATCHDOG_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_ARCH_OMAP1
+
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
+
+#define OMAP_IH1_BASE		0xfffecb00
+#define OMAP_IH2_BASE		0xfffe0000
+
+#define OMAP_IH1_ITR		(OMAP_IH1_BASE + 0x00)
+#define OMAP_IH1_MIR		(OMAP_IH1_BASE + 0x04)
+#define OMAP_IH1_SIR_IRQ	(OMAP_IH1_BASE + 0x10)
+#define OMAP_IH1_SIR_FIQ	(OMAP_IH1_BASE + 0x14)
+#define OMAP_IH1_CONTROL	(OMAP_IH1_BASE + 0x18)
+#define OMAP_IH1_ILR0		(OMAP_IH1_BASE + 0x1c)
+#define OMAP_IH1_ISR		(OMAP_IH1_BASE + 0x9c)
+
+#define OMAP_IH2_ITR		(OMAP_IH2_BASE + 0x00)
+#define OMAP_IH2_MIR		(OMAP_IH2_BASE + 0x04)
+#define OMAP_IH2_SIR_IRQ	(OMAP_IH2_BASE + 0x10)
+#define OMAP_IH2_SIR_FIQ	(OMAP_IH2_BASE + 0x14)
+#define OMAP_IH2_CONTROL	(OMAP_IH2_BASE + 0x18)
+#define OMAP_IH2_ILR0		(OMAP_IH2_BASE + 0x1c)
+#define OMAP_IH2_ISR		(OMAP_IH2_BASE + 0x9c)
+
+#define IRQ_ITR_REG_OFFSET	0x00
+#define IRQ_MIR_REG_OFFSET	0x04
+#define IRQ_SIR_IRQ_REG_OFFSET	0x10
+#define IRQ_SIR_FIQ_REG_OFFSET	0x14
+#define IRQ_CONTROL_REG_OFFSET	0x18
+#define IRQ_ISR_REG_OFFSET	0x9c
+#define IRQ_ILR0_REG_OFFSET	0x1c
+#define IRQ_GMR_REG_OFFSET	0xa0
+
 #endif
-#endif
 
-#include <plat/hardware.h>
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0		0xfffe1080
+#define MOD_CONF_CTRL_1		0xfffe1110
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0		0xfffe1000
+#define FUNC_MUX_CTRL_1		0xfffe1004
+#define FUNC_MUX_CTRL_2		0xfffe1008
+#define COMP_MODE_CTRL_0	0xfffe100c
+#define FUNC_MUX_CTRL_3		0xfffe1010
+#define FUNC_MUX_CTRL_4		0xfffe1014
+#define FUNC_MUX_CTRL_5		0xfffe1018
+#define FUNC_MUX_CTRL_6		0xfffe101C
+#define FUNC_MUX_CTRL_7		0xfffe1020
+#define FUNC_MUX_CTRL_8		0xfffe1024
+#define FUNC_MUX_CTRL_9		0xfffe1028
+#define FUNC_MUX_CTRL_A		0xfffe102C
+#define FUNC_MUX_CTRL_B		0xfffe1030
+#define FUNC_MUX_CTRL_C		0xfffe1034
+#define FUNC_MUX_CTRL_D		0xfffe1038
+#define PULL_DWN_CTRL_0		0xfffe1040
+#define PULL_DWN_CTRL_1		0xfffe1044
+#define PULL_DWN_CTRL_2		0xfffe1048
+#define PULL_DWN_CTRL_3		0xfffe104c
+#define PULL_DWN_CTRL_4		0xfffe10ac
+
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E		0xfffe1090
+#define FUNC_MUX_CTRL_F		0xfffe1094
+#define FUNC_MUX_CTRL_10	0xfffe1098
+#define FUNC_MUX_CTRL_11	0xfffe109c
+#define FUNC_MUX_CTRL_12	0xfffe10a0
+#define PU_PD_SEL_0		0xfffe10b4
+#define PU_PD_SEL_1		0xfffe10b8
+#define PU_PD_SEL_2		0xfffe10bc
+#define PU_PD_SEL_3		0xfffe10c0
+#define PU_PD_SEL_4		0xfffe10c4
+
+/* Timer32K for 1610 and 1710*/
+#define OMAP_TIMER32K_BASE	0xFFFBC400
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL		(TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL		(TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * MPUI interface
+ * ----------------------------------------------------------------------------
+ */
+#define MPUI_BASE			(0xfffec900)
+#define MPUI_CTRL			(MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR			(MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA			(MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG			(MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG			(MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS			(MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG		(MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG		(MPUI_BASE + 0x1c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * LED Pulse Generator
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_LPG1_BASE			0xfffbd000
+#define OMAP_LPG2_BASE			0xfffbd800
+#define OMAP_LPG1_LCR			(OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR			(OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR			(OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR			(OMAP_LPG2_BASE + 0x04)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE			0xfffb5800
+#define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor specific defines
+ * ---------------------------------------------------------------------------
+ */
+
+#include <plat/omap7xx.h>
+#include <plat/omap1510.h>
+#include <plat/omap16xx.h>
+
+#endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 3a587d0..3092134 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -36,8 +36,6 @@
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
 
-#include <mach/hardware.h>
-
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5fd3934..d139fd6 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,22 +24,21 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/usb.h>
-#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include <plat/gpmc-smc91x.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/gpmc-smc91x.h>
-
+#include "common.h"
 #include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 31456ea..c98cad3 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -27,23 +27,24 @@
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
+#include <linux/platform_data/omap-abe-twl6040.h>
+#include <linux/wl12xx.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
-#include <linux/wl12xx.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
 
+#include "hardware.h"
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index de92b08..318fead 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -21,7 +21,6 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 818f664..4da1ee0 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -33,7 +33,6 @@
 
 #include <plat/usb.h>
 
-#include <mach/hardware.h>
 #include <mach/am35xx.h>
 
 #include <video/omapdss.h>
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index a6a1b48..0a8d3df 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -29,18 +29,17 @@
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include "common.h"
 #include <plat/gpmc.h>
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index c2b2371..d10974e 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -43,8 +43,6 @@
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
-#include <mach/hardware.h>
-
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index d1c59d3..63c38dc 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -33,15 +33,14 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/can/platform/ti_hecc.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/usb.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
-#include <plat/serial.h>
 
 #include <mach/am35xx.h>
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index d96eab5..cf7e894 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -24,38 +24,34 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
-
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/dm9000.h>
 
-#include <mach/hardware.h>
-#include <mach/id.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include "common.h"
 #include <plat/gpmc.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
+
+#include <mach/id.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/dm9000.h>
-#include <linux/interrupt.h>
-
 #include "sdram-micron-mt46h32m32lf-6.h"
-
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index bd67c4c..22c6b30 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -16,13 +16,13 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-
-#include <plat/cpu.h>
-#include <plat/gpmc.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
+
+#include <plat/gpmc.h>
 #include <plat/tc.h>
 
+#include "common.h"
 #include "board-flash.h"
 
 #define REG_FPGA_REV			0x10
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 38024a5..2ea7c57 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -16,7 +16,6 @@
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 5be30e6..12569cb 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -27,12 +27,10 @@
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
@@ -41,6 +39,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0dfed5a..c2d0c14 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,7 +31,6 @@
 
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/serial.h>
 
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index e85323c86..19381a9 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -28,24 +28,22 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include "common.h"
 #include <plat/gpmc.h>
-#include <mach/board-zoom.h>
-
-#include <asm/delay.h>
 #include <plat/usb.h>
 #include <plat/gpmc-smsc911x.h>
 
+#include <mach/board-zoom.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "board-flash.h"
 #include "mux.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index eed16d6..931affb 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,18 +20,18 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
-#include <sound/tlv320aic3x.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include "common.h"
 #include <plat/menelaus.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/mmc.h>
-#include <plat/serial.h>
 
+#include <sound/tlv320aic3x.h>
+
+#include "common.h"
 #include "mux.h"
 
 #define TUSB6010_ASYNC_CS	1
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index b259713..0fd3677 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -24,29 +24,27 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/opp.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
-
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include "common.h"
-#include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
+#include <video/omapdss.h>
+#include <video/omap-panel-tfp410.h>
+
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 0470d44..6f390f0 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -23,35 +23,32 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/leds.h>
 #include <linux/interrupt.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
-
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
-
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/wl12xx.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/usb.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include "common.h"
-#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 8fe7f0c..b2efdfb 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -23,30 +23,26 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
-
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
-
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "mux.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "common-board-devices.h"
-
-#include <plat/mux.h>
-#include "common.h"
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
 #include <plat/usb.h>
 
+#include "common.h"
+#include "mux.h"
+#include "hsmmc.h"
+#include "control.h"
+#include "common-board-devices.h"
+
 #define OMAP3LOGIC_SMSC911X_CS			1
 
 #define OMAP3530_LV_SOM_MMC_GPIO_CD		110
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 93c6109..0aa1cce 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -20,7 +20,6 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
-
 #include <linux/spi/spi.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -35,18 +34,18 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-#include <mach/hardware.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/usb.h>
+
 #include <video/omapdss.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 465ee22..7a72e7b 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -23,33 +23,31 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
-
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/i2c/at24.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include "common.h"
 #include <plat/gpmc.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/interrupt.h>
-#include <linux/smsc911x.h>
-#include <linux/i2c/at24.h>
-
+#include "common.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index ba657cd..4e5576d 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -23,32 +23,27 @@
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
-
 #include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <linux/spi/spi.h>
-
 #include <linux/spi/ads7846.h>
-
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/system_info.h>
 
-#include "common.h"
 #include <plat/gpmc.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index cbf6fd5..848e567 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -32,18 +32,19 @@
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <video/omapdss.h>
 
-#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
+
+#include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "hardware.h"
+#include "common.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index ec42d6c..cb5f7f0 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -31,28 +31,26 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/spi/spi.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
+#include <plat/gpmc.h>
+#include <plat/usb.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/gpmc.h>
-#include <mach/hardware.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/mux.h>
-#include <plat/usb.h>
 
+#include "common.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index abdb057..dfbbda2 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -25,7 +25,6 @@
 #include <plat/mmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc.h>
-#include <plat/serial.h>
 
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 3b236ba..398990b 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -17,18 +17,17 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <linux/platform_data/spi-omap2-mcspi.h>
-#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
+#include "common.h"
 #include "mux.h"
 #include "pm.h"
 #include "sdram-nokia.h"
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 5387cb8..d6db794 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -15,12 +15,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/usb.h>
+
 #include "common.h"
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index f1100c2..254e12f 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -19,10 +19,12 @@
 
 #include <plat/gpmc.h>
 #include <plat/gpmc-smsc911x.h>
-#include <plat/serial.h>
 
 #include <mach/board-zoom.h>
 
+#include "hardware.h"
+#include "common.h"
+
 #define ZOOM_SMSC911X_CS	7
 #define ZOOM_SMSC911X_GPIO	158
 #define ZOOM_QUADUART_CS	3
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 0e48a51..1f8648b 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,12 +16,12 @@
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <plat/cpu.h>
-
 #include <mach/board-zoom.h>
 
 #include <video/omapdss.h>
 
+#include "common.h"
+
 #define LCD_PANEL_RESET_GPIO_PROD	96
 #define LCD_PANEL_RESET_GPIO_PILOT	55
 #define LCD_PANEL_QVGA_GPIO		56
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 406303d..41eae75 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/usb.h>
-#include <plat/serial.h>
 
 #include <mach/board-zoom.h>
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3d9d746..cabcfdb 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,11 +33,11 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f..ae624c3 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -22,8 +22,8 @@
 #include <asm/div64.h>
 
 #include <plat/clock.h>
-#include <plat/cpu.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ea3f565..1a1f97f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,14 +22,16 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <trace/events/power.h>
 
 #include <asm/cpu.h>
+
 #include <plat/clock.h>
-#include "clockdomain.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
 
+#include <trace/events/power.h>
+
+#include "soc.h"
+#include "clockdomain.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 0027451..3c33e39 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -18,9 +18,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index dfda9a3..b9852fc 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index cacabb0..62fec64 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 1250009..e92be1f 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,9 +22,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 794d827..fc2765b 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 83bed9a..cc74e74 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -21,9 +21,10 @@
 #include <linux/list.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
+#include "hardware.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index d7f55e4..d1535d9 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -28,9 +28,10 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
+#include "hardware.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 389f9f8..6ffdc86 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,8 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 6c2ff4f..d6048e6 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,10 +17,10 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/mux.h>
 #include <plat/clock.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 1f65b18..f679248 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -28,9 +28,13 @@
 
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
-#include <plat/common.h>
+
 #include <asm/proc-fns.h>
 
+#include <plat/cpu.h>
+#include <plat/serial.h>
+#include <plat/common.h>
+
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 3223b81..da768f1 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,9 +15,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/sdrc.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index a4f5ce6..dcb79a4 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,7 +19,6 @@
 #include <linux/of.h>
 #include <linux/platform_data/omap4-keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b9c8d2f..d8318dc 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -28,9 +28,9 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 9c6a296..09d0ccc 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -15,9 +15,9 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index e28e761..7c9beba 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -21,8 +21,6 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <mach/hardware.h>
-
 #include "iomap.h"
 
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index f0f5918..4acf497 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -13,13 +13,14 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 
+#include "soc.h"
+
 static struct resource gpmc_nand_resource[] = {
 	{
 		.flags		= IORESOURCE_MEM,
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index afb9de8..916716e 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,13 +15,14 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/gpmc.h>
 
+#include "soc.h"
+
 #define	ONENAND_IO_SIZE	SZ_128K
 
 static struct omap_onenand_platform_data *gpmc_onenand_data;
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index e8ff2da..245839d 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,10 +17,11 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "soc.h"
+
 static struct omap_smc91x_platform_data *gpmc_cfg;
 
 static struct resource gpmc_smc91x_resources[] = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bea55a2..bf9a4f0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -27,11 +27,11 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
+#include "soc.h"
 
 /* GPMC register offsets */
 #define GPMC_REVISION		0x00
diff --git a/arch/arm/mach-omap2/hardware.h b/arch/arm/mach-omap2/hardware.h
new file mode 100644
index 0000000..3c190f9
--- /dev/null
+++ b/arch/arm/mach-omap2/hardware.h
@@ -0,0 +1,6 @@
+#include <plat/omap24xx.h>
+#include <plat/omap34xx.h>
+#include <plat/omap44xx.h>
+#include <plat/ti81xx.h>
+#include <plat/am33xx.h>
+#include <plat/omap54xx.h>
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 4b0e166..b7251a2 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -21,8 +21,6 @@
 #include <plat/mux.h>
 #include <plat/omap_device.h>
 
-#include <mach/hardware.h>
-
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index a12e224..fc57e67 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -19,7 +19,6 @@
  *
  */
 
-#include <plat/cpu.h>
 #include <plat/i2c.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 40373db..7219df0 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,10 +22,10 @@
 #include <asm/cputype.h>
 
 #include "common.h"
-#include <plat/cpu.h>
 
 #include <mach/id.h>
 
+#include "soc.h"
 #include "control.h"
 
 static unsigned int omap_revision;
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
index 78edf9d..54492db 100644
--- a/arch/arm/mach-omap2/include/mach/hardware.h
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/hardware.h
  */
-
-#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index ff6fc5b..8d675dd 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,8 +33,7 @@
 #include <plat/multi.h>
 #include <plat/dma.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index ac59f96..25f2baa 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -23,8 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index e032a73..0d97456 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -17,9 +17,10 @@
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
 
-#include <plat/cpu.h>
 #include <plat/mailbox.h>
 
+#include "soc.h"
+
 #define MAILBOX_REVISION		0x000
 #define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
 #define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 4576708..d887642 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -17,12 +17,11 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_data/dsp-mcbsp.h>
 
 #include <plat/dma.h>
-#include <plat/cpu.h>
-#include <linux/platform_data/dsp-mcbsp.h>
 #include <plat/omap_device.h>
-#include <linux/pm_runtime.h>
 
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9a35adf..bdf34b6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,11 +24,11 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 
-#include <mach/hardware.h>
 #include <mach/omap-secure.h>
 #include <mach/omap-wakeupgen.h>
 #include <asm/cputype.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 95ee7dd..2e4bd9a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -27,10 +27,10 @@
 
 #include <asm/hardware/gic.h>
 
-#include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
 #include <mach/omap-secure.h>
 
+#include "hardware.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c886325..48708f0 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -29,9 +29,9 @@
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
 
-#include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
 
+#include "hardware.h"
 #include "common.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6ca8e51..9db1684 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,14 +139,14 @@
 #include <linux/slab.h>
 #include <linux/bootmem.h>
 
-#include "common.h"
-#include <plat/cpu.h>
-#include "clockdomain.h"
-#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
+#include "common.h"
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 8fdc676..95da81a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -12,12 +12,13 @@
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
 #include <plat/l4_2xxx.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4a6bbfd..f0c3fc7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,7 +16,6 @@
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
@@ -24,10 +23,8 @@
 #include <plat/mmc.h>
 #include <plat/l3_2xxx.h>
 
-#include <plat/hardware.h>
-
+#include "hardware.h"
 #include "omap_hwmod_common_data.h"
-
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "wd_timer.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b9525d2..c8b8ee3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -20,7 +20,6 @@
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/l3_3xxx.h>
@@ -29,9 +28,9 @@
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 
-#include <mach/hardware.h>
 #include <mach/am35xx.h>
 
+#include "hardware.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c9edaf2..0c2e71c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -25,7 +25,6 @@
 #include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/i2c.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index f0992fd..1699d53 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -28,8 +28,7 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 
-#include <plat/hardware.h>
-
+#include "hardware.h"
 #include "omap_l3_noc.h"
 
 /*
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d0b4dc7..d60cc9b 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -28,9 +28,10 @@
 #include <linux/err.h>
 #include <linux/usb.h>
 
-#include <plat/hardware.h>
 #include <plat/usb.h>
 
+#include "soc.h"
+#include "hardware.h"
 #include "control.h"
 
 /* OMAP control module register for UTMI PHY */
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index 5037e76..a9e8cf2 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -28,7 +28,7 @@
  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 750805c..0e75ec3 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -26,7 +26,7 @@
  * This is technically part of the OMAP2xxx clock code.
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index d95f3f9..75cef5f 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,8 +19,6 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba2..798754e 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -20,8 +20,7 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 69b36e1..ca5be83 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -28,11 +28,13 @@
 #include "prm44xx.h"
 
 #include <asm/cpu.h>
-#include <plat/cpu.h>
+
+#include <plat/prcm.h>
+
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/prcm.h>
 
+#include "soc.h"
 #include "pm.h"
 
 #define PWRDM_TRACE_STATES_FLAG	(1<<31)
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index bb883e4..8b23d23 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -15,11 +15,9 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
-
 #include "prcm-common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9052383..b86d905 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -17,10 +17,10 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "common.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
+#include "common.h"
 #include "vp.h"
 
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index df2cfe1..aeaf5e7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,10 +17,10 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <plat/hardware.h>
 
+#include "soc.h"
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "vp.h"
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 1133bb2..974e5b0 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,11 +24,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "hardware.h"
 #include "iomap.h"
 #include "common.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 1f62f23..3fbe496 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,7 +26,7 @@
 
 #include <asm/assembler.h>
 
-#include <plat/hardware.h>
+#include <plat/omap34xx.h>
 #include <plat/sram.h>
 
 #include "iomap.h"
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
new file mode 100644
index 0000000..40195f1
--- /dev/null
+++ b/arch/arm/mach-omap2/soc.h
@@ -0,0 +1 @@
+#include <plat/cpu.h>
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index ee0bfcc..5f13780 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index d4d39ef..9a8d401 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index df5a213..8252b19 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -29,8 +29,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index e1f1d09..b030874 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -46,8 +46,7 @@
 #include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
 
-#include <mach/hardware.h>
-
+#include "hardware.h"
 #include "common.h"
 #include "powerdomain.h"
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 81f9956..db9db2e 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -26,10 +26,10 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 
-#include <plat/hardware.h>
 #include <plat/i2c.h>
 #include <plat/usb.h>
 
+#include "hardware.h"
 #include "twl-common.h"
 #include "pm.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 14368c3..ac95daa 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -25,7 +25,6 @@
 
 #include <asm/io.h>
 
-#include <mach/hardware.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3f35e6c..89150b2 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -23,13 +23,13 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
-
 #include <linux/usb/musb.h>
 
-#include <mach/hardware.h>
-#include <mach/am35xx.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
+
+#include <mach/am35xx.h>
+
 #include "mux.h"
 
 static struct musb_hdrc_config musb_config = {
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 84da34f..b451f3c 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -12,8 +12,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "voltage.h"
 #include "vc.h"
 #include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index d0103c8..63afbfe 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -18,9 +18,8 @@
 #include <linux/err.h>
 #include <linux/init.h>
 
+#include "soc.h"
 #include "common.h"
-#include <plat/cpu.h>
-
 #include "prm-regbits-34xx.h"
 #include "omap_opp_data.h"
 #include "voltage.h"
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 902d2ff..2e826f1 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,9 +22,7 @@
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 
-#include <plat/hardware.h>
 #include <plat/common.h>
-
 #include <plat/clock.h>
 
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe6267..6dcad58 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,8 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
+#include <plat/cpu.h>
 #include <plat/dma.h>
-
 #include <plat/tc.h>
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644
index ddbde38..0000000
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/hardware.h
- *
- * Hardware definitions for TI OMAP processors and boards
- *
- * NOTE: Please put device driver specific defines into a separate header
- *	 file for each driver.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc. Greg Lonnon <glonnon at ridgerun.com>
- *
- * Reorganized for Linux-2.6 by Tony Lindgren <tony at atomide.com>
- *                          and Dirk Behme <dirk.behme at de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __ASM_ARCH_OMAP_HARDWARE_H
-
-#include <asm/sizes.h>
-#ifndef __ASSEMBLER__
-#include <asm/types.h>
-#include <plat/cpu.h>
-#endif
-#include <plat/serial.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Common definitions for all OMAP processors
- * NOTE: Put all processor or board specific parts to the special header
- *	 files.
- * ---------------------------------------------------------------------------
- */
-
-/*
- * ----------------------------------------------------------------------------
- * Timers
- * ----------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE	(0xfffec500)
-#define OMAP_MPU_TIMER2_BASE	(0xfffec600)
-#define OMAP_MPU_TIMER3_BASE	(0xfffec700)
-#define MPU_TIMER_FREE		(1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE	(1 << 5)
-#define MPU_TIMER_AR		(1 << 1)
-#define MPU_TIMER_ST		(1 << 0)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_BASE		(0xfffece00)
-#define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)
-
-#define CK_RATEF		1
-#define CK_IDLEF		2
-#define CK_ENABLEF		4
-#define CK_SELECTF		8
-#define SETARM_IDLE_SHIFT
-
-/* DPLL control registers */
-#define DPLL_CTL		(0xfffecf00)
-
-/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
-#define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)
-
-/*
- * ---------------------------------------------------------------------------
- * UPLD
- * ---------------------------------------------------------------------------
- */
-#define ULPD_REG_BASE		(0xfffe0800)
-#define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
-#define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
-#define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
-#	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
-#	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
-#	define SOFT_UDC_REQ		(1 << 4)
-#	define SOFT_USB_CLK_REQ		(1 << 3)
-#	define SOFT_DPLL_REQ		(1 << 0)
-#define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
-#define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
-#	define DIS_MMC2_DPLL_REQ	(1 << 11)
-#	define DIS_MMC1_DPLL_REQ	(1 << 10)
-#	define DIS_UART3_DPLL_REQ	(1 << 9)
-#	define DIS_UART2_DPLL_REQ	(1 << 8)
-#	define DIS_UART1_DPLL_REQ	(1 << 7)
-#	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
-#define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
-#define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* Watchdog timer within the OMAP3.2 gigacell */
-#define OMAP_MPU_WATCHDOG_BASE	(0xfffec800)
-#define OMAP_WDT_TIMER		(OMAP_MPU_WATCHDOG_BASE + 0x0)
-#define OMAP_WDT_LOAD_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_READ_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_TIMER_MODE	(OMAP_MPU_WATCHDOG_BASE + 0x8)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_ARCH_OMAP1
-
-/*
- * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
- * or something similar.. -- PFM.
- */
-
-#define OMAP_IH1_BASE		0xfffecb00
-#define OMAP_IH2_BASE		0xfffe0000
-
-#define OMAP_IH1_ITR		(OMAP_IH1_BASE + 0x00)
-#define OMAP_IH1_MIR		(OMAP_IH1_BASE + 0x04)
-#define OMAP_IH1_SIR_IRQ	(OMAP_IH1_BASE + 0x10)
-#define OMAP_IH1_SIR_FIQ	(OMAP_IH1_BASE + 0x14)
-#define OMAP_IH1_CONTROL	(OMAP_IH1_BASE + 0x18)
-#define OMAP_IH1_ILR0		(OMAP_IH1_BASE + 0x1c)
-#define OMAP_IH1_ISR		(OMAP_IH1_BASE + 0x9c)
-
-#define OMAP_IH2_ITR		(OMAP_IH2_BASE + 0x00)
-#define OMAP_IH2_MIR		(OMAP_IH2_BASE + 0x04)
-#define OMAP_IH2_SIR_IRQ	(OMAP_IH2_BASE + 0x10)
-#define OMAP_IH2_SIR_FIQ	(OMAP_IH2_BASE + 0x14)
-#define OMAP_IH2_CONTROL	(OMAP_IH2_BASE + 0x18)
-#define OMAP_IH2_ILR0		(OMAP_IH2_BASE + 0x1c)
-#define OMAP_IH2_ISR		(OMAP_IH2_BASE + 0x9c)
-
-#define IRQ_ITR_REG_OFFSET	0x00
-#define IRQ_MIR_REG_OFFSET	0x04
-#define IRQ_SIR_IRQ_REG_OFFSET	0x10
-#define IRQ_SIR_FIQ_REG_OFFSET	0x14
-#define IRQ_CONTROL_REG_OFFSET	0x18
-#define IRQ_ISR_REG_OFFSET	0x9c
-#define IRQ_ILR0_REG_OFFSET	0x1c
-#define IRQ_GMR_REG_OFFSET	0xa0
-
-#endif
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define MOD_CONF_CTRL_0		0xfffe1080
-#define MOD_CONF_CTRL_1		0xfffe1110
-
-/*
- * ----------------------------------------------------------------------------
- * Pin multiplexing registers
- * ----------------------------------------------------------------------------
- */
-#define FUNC_MUX_CTRL_0		0xfffe1000
-#define FUNC_MUX_CTRL_1		0xfffe1004
-#define FUNC_MUX_CTRL_2		0xfffe1008
-#define COMP_MODE_CTRL_0	0xfffe100c
-#define FUNC_MUX_CTRL_3		0xfffe1010
-#define FUNC_MUX_CTRL_4		0xfffe1014
-#define FUNC_MUX_CTRL_5		0xfffe1018
-#define FUNC_MUX_CTRL_6		0xfffe101C
-#define FUNC_MUX_CTRL_7		0xfffe1020
-#define FUNC_MUX_CTRL_8		0xfffe1024
-#define FUNC_MUX_CTRL_9		0xfffe1028
-#define FUNC_MUX_CTRL_A		0xfffe102C
-#define FUNC_MUX_CTRL_B		0xfffe1030
-#define FUNC_MUX_CTRL_C		0xfffe1034
-#define FUNC_MUX_CTRL_D		0xfffe1038
-#define PULL_DWN_CTRL_0		0xfffe1040
-#define PULL_DWN_CTRL_1		0xfffe1044
-#define PULL_DWN_CTRL_2		0xfffe1048
-#define PULL_DWN_CTRL_3		0xfffe104c
-#define PULL_DWN_CTRL_4		0xfffe10ac
-
-/* OMAP-1610 specific multiplexing registers */
-#define FUNC_MUX_CTRL_E		0xfffe1090
-#define FUNC_MUX_CTRL_F		0xfffe1094
-#define FUNC_MUX_CTRL_10	0xfffe1098
-#define FUNC_MUX_CTRL_11	0xfffe109c
-#define FUNC_MUX_CTRL_12	0xfffe10a0
-#define PU_PD_SEL_0		0xfffe10b4
-#define PU_PD_SEL_1		0xfffe10b8
-#define PU_PD_SEL_2		0xfffe10bc
-#define PU_PD_SEL_3		0xfffe10c0
-#define PU_PD_SEL_4		0xfffe10c4
-
-/* Timer32K for 1610 and 1710*/
-#define OMAP_TIMER32K_BASE	0xFFFBC400
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL		(TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL		(TIPB_PRIVATE_CNTL_BASE + 0x8)
-
-/*
- * ----------------------------------------------------------------------------
- * MPUI interface
- * ----------------------------------------------------------------------------
- */
-#define MPUI_BASE			(0xfffec900)
-#define MPUI_CTRL			(MPUI_BASE + 0x0)
-#define MPUI_DEBUG_ADDR			(MPUI_BASE + 0x4)
-#define MPUI_DEBUG_DATA			(MPUI_BASE + 0x8)
-#define MPUI_DEBUG_FLAG			(MPUI_BASE + 0xc)
-#define MPUI_STATUS_REG			(MPUI_BASE + 0x10)
-#define MPUI_DSP_STATUS			(MPUI_BASE + 0x14)
-#define MPUI_DSP_BOOT_CONFIG		(MPUI_BASE + 0x18)
-#define MPUI_DSP_API_CONFIG		(MPUI_BASE + 0x1c)
-
-/*
- * ----------------------------------------------------------------------------
- * LED Pulse Generator
- * ----------------------------------------------------------------------------
- */
-#define OMAP_LPG1_BASE			0xfffbd000
-#define OMAP_LPG2_BASE			0xfffbd800
-#define OMAP_LPG1_LCR			(OMAP_LPG1_BASE + 0x00)
-#define OMAP_LPG1_PMR			(OMAP_LPG1_BASE + 0x04)
-#define OMAP_LPG2_LCR			(OMAP_LPG2_BASE + 0x00)
-#define OMAP_LPG2_PMR			(OMAP_LPG2_BASE + 0x04)
-
-/*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP_PWL_BASE			0xfffb5800
-#define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
-#define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)
-
-/*
- * ---------------------------------------------------------------------------
- * Processor specific defines
- * ---------------------------------------------------------------------------
- */
-
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/ti81xx.h>
-#include <plat/am33xx.h>
-#include <plat/omap54xx.h>
-
-#endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 8ad0a37..20de0d5 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,6 +1,8 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 
+struct omap_board_data;
+
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
 				struct omap_board_data *);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 5da9735..43b927b 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -45,7 +45,6 @@
 #define OMAP44XX_L2CACHE_BASE		0x48242000
 #define OMAP44XX_WKUPGEN_BASE		0x48281000
 #define OMAP44XX_MCPDM_BASE		0x40132000
-#define OMAP44XX_MCPDM_L3_BASE		0x49032000
 #define OMAP44XX_SAR_RAM_BASE		0x4a326000
 
 #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index fceec4f..f5db18db 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -46,6 +46,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <mach/hardware.h>
+#include <plat/cpu.h>
 #include <plat/prcm.h>
 
 #include "omap_wdt.h"
@@ -218,12 +219,16 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
 	case WDIOC_GETSTATUS:
 		return put_user(0, (int __user *)arg);
 	case WDIOC_GETBOOTSTATUS:
+#ifdef CONFIG_ARCH_OMAP1
 		if (cpu_is_omap16xx())
 			return put_user(__raw_readw(ARM_SYSST),
 					(int __user *)arg);
+#endif
+#ifdef CONFIG_ARCH_OMAP2PLUS
 		if (cpu_is_omap24xx())
 			return put_user(omap_prcm_get_reset_sources(),
 					(int __user *)arg);
+#endif
 		return put_user(0, (int __user *)arg);
 	case WDIOC_KEEPALIVE:
 		spin_lock(&wdt_lock);
diff --git a/sound/soc/omap/omap-abe-twl6040.c b/sound/soc/omap/omap-abe-twl6040.c
index 9d93793..45909ca 100644
--- a/sound/soc/omap/omap-abe-twl6040.c
+++ b/sound/soc/omap/omap-abe-twl6040.c
@@ -31,10 +31,6 @@
 #include <sound/soc.h>
 #include <sound/jack.h>
 
-#include <asm/mach-types.h>
-#include <plat/hardware.h>
-#include <plat/mux.h>
-
 #include "omap-dmic.h"
 #include "omap-mcpdm.h"
 #include "omap-pcm.h"
diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c
index 2c66e24..ea053c3 100644
--- a/sound/soc/omap/omap-mcpdm.c
+++ b/sound/soc/omap/omap-mcpdm.c
@@ -45,6 +45,8 @@
 #include "omap-mcpdm.h"
 #include "omap-pcm.h"
 
+#define OMAP44XX_MCPDM_L3_BASE		0x49032000
+
 struct omap_mcpdm {
 	struct device *dev;
 	unsigned long phys_base;



From broonie at opensource.wolfsonmicro.com  Fri Aug 31 20:27:54 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 31 Aug 2012 17:27:54 -0700
Subject: [PATCH 2/4] ARM: OMAP: Split plat/hardware.h, introduce local
 hardware.h and soc.h for omap2+
In-Reply-To: <20120901002622.23715.68557.stgit@muffinssi.local>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
 <20120901002622.23715.68557.stgit@muffinssi.local>
Message-ID: <20120901002753.GA21451@opensource.wolfsonmicro.com>

On Fri, Aug 31, 2012 at 05:26:22PM -0700, Tony Lindgren wrote:
> As the plat and mach includes need to disappear for single zImage work,
> we need to remove plat/hardware.h.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

There's a topic/omap branch in ASoC which you can pull in to help reduce
conflicts, or I could merge this there if that's sensible.


From broonie at opensource.wolfsonmicro.com  Fri Aug 31 20:44:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 31 Aug 2012 17:44:44 -0700
Subject: [PATCH 1/3] ASoC: Davinci: McASP: add support new McASP IP Variant
In-Reply-To: <1346417459-30042-2-git-send-email-gururaja.hebbar@ti.com>
References: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
 <1346417459-30042-2-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120901004443.GB21451@opensource.wolfsonmicro.com>

On Fri, Aug 31, 2012 at 06:20:57PM +0530, Hebbar, Gururaja wrote:

> +			if (dev->version == MCASP_VERSION_3) {
> +				mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
>  								FIFO_ENABLE);
> -			mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
> +				mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
>  								FIFO_ENABLE);
> +			} else {
> +				mcasp_clr_bits(dev->base +
> +					DAVINCI_MCASP_RFIFOCTL,	FIFO_ENABLE);
> +				mcasp_set_bits(dev->base +
> +					DAVINCI_MCASP_RFIFOCTL,	FIFO_ENABLE);
> +			}

This is all basically OK but it seems like it'd be better if all these
dev->version checks were switch statements.  That way when the hardware
designers get bored and add version 4 of the register map it'll slot in
naturally, and it'll be more clear what the code currently handles.


From broonie at opensource.wolfsonmicro.com  Fri Aug 31 20:47:25 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 31 Aug 2012 17:47:25 -0700
Subject: [PATCH 3/3] ASoC: Davinci: evm: Fix typo in cpu dai name
In-Reply-To: <1346417459-30042-4-git-send-email-gururaja.hebbar@ti.com>
References: <1346417459-30042-1-git-send-email-gururaja.hebbar@ti.com>
 <1346417459-30042-4-git-send-email-gururaja.hebbar@ti.com>
Message-ID: <20120901004724.GC21451@opensource.wolfsonmicro.com>

On Fri, Aug 31, 2012 at 06:20:59PM +0530, Hebbar, Gururaja wrote:
> Fix typo caused by recent commit (cf53756 - ASoC: davinci: davinci-pcm
> does not need to be a plaform_driver)

Applied, thanks.


From vkoul at infradead.org  Fri Aug 31 21:02:29 2012
From: vkoul at infradead.org (Vinod Koul)
Date: Sat, 01 Sep 2012 06:32:29 +0530
Subject: [PATCH v3 3/3] spi: spi-davinci: convert to DMA engine API
In-Reply-To: <1346432577.15463.16.camel@vkoul-mobl4>
References: <1345684176-21472-1-git-send-email-mporter@ti.com>
 <1345684176-21472-4-git-send-email-mporter@ti.com>
 <503F75C0.1050507@ti.com> <20120830144307.GA26737@beef>
 <5040E00A.3080600@ti.com> <1346430709.15463.15.camel@vkoul-mobl4>
 <5040E6C7.6030106@ti.com> <1346432577.15463.16.camel@vkoul-mobl4>
Message-ID: <1346461349.2806.4.camel@vkoul-mobl4>

On Fri, 2012-08-31 at 22:32 +0530, Vinod Koul wrote:
> On Fri, 2012-08-31 at 22:01 +0530, Sekhar Nori wrote:
> > >> Yes, this was the problem. Since the SPI driver now depends on
> > >> CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
> > >> Kconfig if SPI is enabled? That should do until the fallback to PIO
> > is
> > >> implemented.
> > > Then this should be enabled for SPI. Care to send a patch
> > 
> > By 'this' you mean the Kconfig select? Then there should be no need of
> > a
> > new patch for this. It can be part of this patch itself, no? 
> Either way is okay for me.
And am in good mood :)

Applied all with this as well

>From b5f14330590118e6a0659255476c0f24ab681e05 Mon Sep 17 00:00:00 2001
From: Vinod Koul <vinod.koul at linux.intel.com>
Date: Sat, 1 Sep 2012 06:29:22 +0530
Subject: [PATCH] spi: davici - make davinci select edma

Reported-by: Sekhar Nori <nsekhar at ti.com>
Signed-off-by: Vinod Koul <vinod.koul at linux.intel.com>
---
 drivers/spi/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b55..b9fb9a1 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -134,6 +134,7 @@ config SPI_DAVINCI
 	tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI
controller"
 	depends on ARCH_DAVINCI
 	select SPI_BITBANG
+	select TI_EDMA
 	help
 	  SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
 
-- 
1.7.9.5



-- 
~Vinod Koul
Intel Corp.



From linus.walleij at linaro.org  Fri Aug 31 21:14:15 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat, 1 Sep 2012 03:14:15 +0200
Subject: [PATCH 3/6] ARM: plat-versatile: add DT support to FPGA IRQ
 controller
In-Reply-To: <201208161350.49063.arnd@arndb.de>
References: <1345119357-22702-1-git-send-email-linus.walleij@linaro.org>
 <201208161350.49063.arnd@arndb.de>
Message-ID: <CACRpkdamVhbW_nizDODTu2wg7wX+4ENnLMGH=RoHkG4hwn3Yfg@mail.gmail.com>

On Thu, Aug 16, 2012 at 3:50 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 16 August 2012, Linus Walleij wrote:
>> +- irq-start: the u32 hardware IRQ number of the first interrupt handled by
>> +  this FPGA IRQ instance - since there may be many FPGA IRQ controller
>> +  instances, each will have its unique hardware offset number.
>
> The irq-start value is a Linux specific invention, the hardware doesn't
> know anything about these. As long as you depend on specific IRQ numbers
> to get assigned, I would use something like auxdata to find the
> start number.

Sorry that does not work. Auxdata is not used with IRQ controllers,
only with devices.

of_irq_init() will dereference the .data field of struct of_device_id
and use as a callback function to initialize the IRQ controller, no
chance to pass any other data that way.

> When all devices get their IRQ numbers from the device
> tree, you can move to linear IRQ domains instead of legacy, and let
> the irq domain code pick the numbers.

It seems I have no other choice here than to move directly to
linear numbers or atleast dynamically allocated descriptors.

Yours,
Linus Walleij


From nicolas.pitre at linaro.org  Fri Aug 31 21:48:30 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 31 Aug 2012 21:48:30 -0400 (EDT)
Subject: [PATCH 2/2] ARM: allow for ATAGS to be configured out when DT
 support is selected
In-Reply-To: <CACRpkdZqgjkOOfR7b9Fs8uixkDAnjj-VFmSfYQ_eN1-GuZtb+Q@mail.gmail.com>
References: <1346361008-7320-1-git-send-email-nicolas.pitre@linaro.org>
 <1346361008-7320-2-git-send-email-nicolas.pitre@linaro.org>
 <CACRpkdZqgjkOOfR7b9Fs8uixkDAnjj-VFmSfYQ_eN1-GuZtb+Q@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1208312145520.1784@xanadu.home>

On Sat, 1 Sep 2012, Linus Walleij wrote:

> On Thu, Aug 30, 2012 at 11:10 PM, Nicolas Pitre
> <nicolas.pitre at linaro.org> wrote:
> 
> > Now that ATAGS support is well contained, we can easily remove it from
> > the kernel build if so desired.  It has to explicitly be disabled, and
> > only when DT support is selected.
> 
> I patched this on top of my Integrator patch stack and disabled
> the ATAGS, it just works.
> 
> Tested-by: Linus Walleij <linus.walleij at linaro.org>

Thanks.

> I'd suggest you to put this into Russells tracker then?

Certainly.  I just wanted someone else than myself to test it / look at it 
before I do so.


Nicolas


From tony at atomide.com  Fri Aug 31 22:06:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 31 Aug 2012 19:06:54 -0700
Subject: [PATCH 2/4] ARM: OMAP: Split plat/hardware.h, introduce local
 hardware.h and soc.h for omap2+
In-Reply-To: <20120901002753.GA21451@opensource.wolfsonmicro.com>
References: <20120901002534.23715.28654.stgit@muffinssi.local>
 <20120901002622.23715.68557.stgit@muffinssi.local>
 <20120901002753.GA21451@opensource.wolfsonmicro.com>
Message-ID: <20120901020654.GT1303@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120831 17:28]:
> On Fri, Aug 31, 2012 at 05:26:22PM -0700, Tony Lindgren wrote:
> > As the plat and mach includes need to disappear for single zImage work,
> > we need to remove plat/hardware.h.
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
> There's a topic/omap branch in ASoC which you can pull in to help reduce
> conflicts, or I could merge this there if that's sensible.

Thanks. Did not see it yet at git://opensource.wolfsonmicro.com/linux-2.6-asoc,
maybe it's not yet pushed out?

Tony


From linus.walleij at linaro.org  Fri Aug 31 23:55:53 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:53 +0200
Subject: [PATCH 1/6 v2] ARM: integrator: call common init function from machine
Message-ID: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>

There is currently a common integrator_init() function set up
to be called from an arch_initcall(). The problem is that it is
using machine_is_integrator() which is not working with device
tree, let's call this from respective machine initilization
function and add a parameter to tell whether it's the
Integrator/AP or Integrator/CP instead.

There are still machine_is*() calls in the Integrator
machines directory, but this one needs to be fixed lest we
don't even get a UART console on the Integrator/AP after a
Device Tree boot.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-integrator/common.h        | 1 +
 arch/arm/mach-integrator/core.c          | 6 ++----
 arch/arm/mach-integrator/integrator_ap.c | 2 ++
 arch/arm/mach-integrator/integrator_cp.c | 1 +
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index 899561d..c4338e2 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,4 @@
 void integrator_init_early(void);
+int integrator_init(bool is_cp);
 void integrator_reserve(void);
 void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 3fa6c51..5ba4bc8 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -61,7 +61,7 @@ static struct amba_device *amba_devs[] __initdata = {
 	&kmi1_device,
 };
 
-static int __init integrator_init(void)
+int __init integrator_init(bool is_cp)
 {
 	int i;
 
@@ -70,7 +70,7 @@ static int __init integrator_init(void)
 	 * hard-code them. The Integator/CP and forward have proper cell IDs.
 	 * Else we leave them undefined to the bus driver can autoprobe them.
 	 */
-	if (machine_is_integrator()) {
+	if (!is_cp) {
 		rtc_device.periphid	= 0x00041030;
 		uart0_device.periphid	= 0x00041010;
 		uart1_device.periphid	= 0x00041010;
@@ -86,8 +86,6 @@ static int __init integrator_init(void)
 	return 0;
 }
 
-arch_initcall(integrator_init);
-
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
  * bits in the following SC_CTRLS register bits:
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3b22675..ff966d8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -312,6 +312,8 @@ static void __init ap_init(void)
 
 		lm_device_register(lmdev);
 	}
+
+	integrator_init(false);
 }
 
 /*
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 82d5c83..2b40bc1 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -366,6 +366,7 @@ static void __init intcp_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
+	integrator_init(true);
 }
 
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
-- 
1.7.11.4



From linus.walleij at linaro.org  Fri Aug 31 23:55:54 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:54 +0200
Subject: [PATCH 2/6 v2] ARM: integrator: check PL010 device name rather than
 base address
In-Reply-To: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>

In the PL010 UART callback a comparison against the base address is
done to figure out which UART is doing the callback. This does not
play well with device tree, so let's check the dev_name() of the
device instead.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-integrator/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 5ba4bc8..67ea181 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -100,7 +100,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
 {
 	unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 
-	if (dev == &uart0_device) {
+	if (!strcmp(dev_name(&dev->dev), "uart0")) {
 		rts_mask = 1 << 4;
 		dtr_mask = 1 << 5;
 	} else {
-- 
1.7.11.4



From linus.walleij at linaro.org  Fri Aug 31 23:55:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:55 +0200
Subject: [PATCH 3/6 v2] ARM: plat-versatile: add DT support to FPGA IRQ
 controller
In-Reply-To: <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>
References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>
Message-ID: <1346471760-23993-3-git-send-email-linus.walleij@linaro.org>

This adds Device Tree probing support to the Versatile FPGA
IRQ controller.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Stop passing the Linux IRQ number in the DT node, bad idea.
  Register descriptors dynamically, and use whatever IRQ number
  base we get. Assume we will switch everything using this over to
  DT and live with it.
---
 .../devicetree/bindings/arm/versatile-fpga-irq.txt | 31 ++++++++++++++
 arch/arm/plat-versatile/fpga-irq.c                 | 47 ++++++++++++++++++++++
 arch/arm/plat-versatile/include/plat/fpga-irq.h    |  2 +
 3 files changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt

diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
new file mode 100644
index 0000000..9989eda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt
@@ -0,0 +1,31 @@
+* ARM Versatile FPGA interrupt controller
+
+One or more FPGA IRQ controllers can be synthesized in an ARM reference board
+such as the Integrator or Versatile family. The output of these different
+controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
+instance can handle up to 32 interrupts.
+
+Required properties:
+- compatible: "arm,versatile-fpga-irq"
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
+  as the FPGA IRQ controller has no configuration options for interrupt
+  sources.  The cell is a u32 and defines the interrupt number.
+- reg: The register bank for the FPGA interrupt controller.
+- clear-mask: a u32 number representing the mask written to clear all IRQs
+  on the controller at boot for example.
+- valid-mask: a u32 number representing a bit mask determining which of
+  the interrupts are valid. Unconnected/unused lines are set to 0, and
+  the system till not make it possible for devices to request these
+  interrupts.
+
+Example:
+
+pic: pic at 14000000 {
+        compatible = "arm,versatile-fpga-irq";
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        reg = <0x14000000 0x100>;
+        clear-mask = <0xffffffff>;
+        valid-mask = <0x003fffff>;
+};
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 6e70d03..1ca595c 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -5,6 +5,8 @@
 #include <linux/io.h>
 #include <linux/irqdomain.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -14,6 +16,13 @@
 #define IRQ_RAW_STATUS		0x04
 #define IRQ_ENABLE_SET		0x08
 #define IRQ_ENABLE_CLEAR	0x0c
+#define INT_SOFT_SET		0x10
+#define INT_SOFT_CLEAR		0x14
+#define FIQ_STATUS		0x20
+#define FIQ_RAW_STATUS		0x24
+#define FIQ_ENABLE		0x28
+#define FIQ_ENABLE_SET		0x28
+#define FIQ_ENABLE_CLEAR	0x2C
 
 /**
  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
@@ -156,3 +165,41 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
 
 	fpga_irq_id++;
 }
+
+#ifdef CONFIG_OF
+int __init fpga_irq_of_init(struct device_node *node,
+			    struct device_node *parent)
+{
+	void __iomem *base;
+	u32 irq_start;
+	u32 clear_mask;
+	u32 valid_mask;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	base = of_iomap(node, 0);
+	WARN(!base, "unable to map fpga irq registers\n");
+
+	if (of_property_read_u32(node, "clear-mask", &clear_mask))
+		clear_mask = 0;
+
+	if (of_property_read_u32(node, "valid-mask", &valid_mask))
+		valid_mask = 0;
+
+	irq_start = irq_alloc_descs(-1, 0, fls(valid_mask), numa_node_id());
+	if (WARN_ON(irq_start < 0))
+		goto out_unmap;
+
+	writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+	writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+
+	fpga_irq_init(base, node->name, irq_start, -1, valid_mask, node);
+
+	return 0;
+
+out_unmap:
+	iounmap(base);
+	return -EIO;
+}
+#endif
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 91bcfb6..1fac965 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -7,5 +7,7 @@ struct pt_regs;
 void fpga_handle_irq(struct pt_regs *regs);
 void fpga_irq_init(void __iomem *, const char *, int, int, u32,
 		struct device_node *node);
+int fpga_irq_of_init(struct device_node *node,
+		     struct device_node *parent);
 
 #endif
-- 
1.7.11.4



From linus.walleij at linaro.org  Fri Aug 31 23:55:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:56 +0200
Subject: [PATCH 4/6 v2] ARM: integrator: initial device tree support
In-Reply-To: <1346471760-23993-3-git-send-email-linus.walleij@linaro.org>
References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-3-git-send-email-linus.walleij@linaro.org>
Message-ID: <1346471760-23993-4-git-send-email-linus.walleij@linaro.org>

This is initial device tree support for the ARM Integrator family,
we create a very basic device tree, #ifdef out the non-DT machines
when compiling for device tree.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Also switch over clocksource and clockevent to device tree.
  Else the IRQ mapping goes bananas.
---
 Documentation/devicetree/bindings/arm/arm-boards |  12 ++
 arch/arm/boot/dts/integratorap.dts               |  51 ++++++++
 arch/arm/boot/dts/integratorcp.dts               |  69 ++++++++++
 arch/arm/mach-integrator/integrator_ap.c         | 137 ++++++++++++++++----
 arch/arm/mach-integrator/integrator_cp.c         | 152 ++++++++++++++++-------
 5 files changed, 353 insertions(+), 68 deletions(-)
 create mode 100644 arch/arm/boot/dts/integratorap.dts
 create mode 100644 arch/arm/boot/dts/integratorcp.dts

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 91f2614..fc81a7d 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -1,3 +1,15 @@
+ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
+-----------------------------------------------------------------------------
+ARM's oldest Linux-supported platform with connectors for different core
+tiles of ARMv4, ARMv5 and ARMv6 type.
+
+Required properties (in root node):
+	compatible = "arm,integrator-ap";  /* Application Platform */
+	compatible = "arm,integrator-cp";  /* Compact Platform */
+
+FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
+
+
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
 ARM's development hardware platform with connectors for customizable
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
new file mode 100644
index 0000000..928a7be
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -0,0 +1,51 @@
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "ARM Integrator/AP";
+	compatible = "arm,integrator-ap";
+	ranges;
+
+	aliases {
+		arm,integrator-clocksource = &timer2;
+		arm,integrator-clockevent = &timer1;
+	};
+
+	chosen {
+		bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
+	};
+
+	timer0: timer at 13000000 {
+		compatible = "arm,integrator-timer";
+		reg = <0x13000000 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <5>;
+	};
+
+	timer1: timer at 13000100 {
+		compatible = "arm,integrator-timer";
+		reg = <0x13000100 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <6>;
+	};
+
+	timer2: timer at 13000200 {
+		compatible = "arm,integrator-timer";
+		reg = <0x13000200 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <7>;
+	};
+
+	pic: pic at 14000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x14000000 0x100>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x003fffff>;
+	};
+};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
new file mode 100644
index 0000000..8fad5a1
--- /dev/null
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -0,0 +1,69 @@
+/*
+ * Device Tree for the ARM Integrator/CP platform
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "ARM Integrator/CP";
+	compatible = "arm,integrator-cp";
+	ranges;
+
+	aliases {
+		arm,integrator-clocksource = &timer2;
+		arm,integrator-clockevent = &timer1;
+	};
+
+	chosen {
+		bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
+	};
+
+	timer0: timer at 13000000 {
+		compatible = "arm,sp804", "arm,primecell";
+		reg = <0x13000000 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <5>;
+	};
+
+	timer1: timer at 13000100 {
+		compatible = "arm,sp804", "arm,primecell";
+		reg = <0x13000100 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <6>;
+	};
+
+	timer2: timer at 13000200 {
+		compatible = "arm,sp804", "arm,primecell";
+		reg = <0x13000200 0x100>;
+		interrupt-parent = <&pic>;
+		interrupts = <7>;
+	};
+
+	pic: pic at 14000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x14000000 0x100>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x1fc003ff>;
+	};
+
+	cic: cic at 10000040 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0x10000040 0x100>;
+		clear-mask = <0xffffffff>;
+		valid-mask = <0x00000007>;
+	};
+
+	sic: sic at ca000000 {
+		compatible = "arm,versatile-fpga-irq";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		reg = <0xca000000 0x100>;
+		clear-mask = <0x00000fff>;
+		valid-mask = <0x00000fff>;
+	};
+};
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index ff966d8..26d4d8c 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -34,6 +34,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -161,23 +163,6 @@ static void __init ap_map_io(void)
 	vga_base = PCI_MEMORY_VADDR;
 }
 
-#define INTEGRATOR_SC_VALID_INT	0x003fffff
-
-static void __init ap_init_irq(void)
-{
-	/* Disable all interrupts initially. */
-	/* Do the core module ones */
-	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-	/* do the header card stuff next */
-	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-		-1, INTEGRATOR_SC_VALID_INT, NULL);
-	integrator_clk_init(false);
-}
-
 #ifdef CONFIG_PM
 static unsigned long ic_irq_enable;
 
@@ -330,9 +315,9 @@ static u32 notrace integrator_read_sched_clock(void)
 	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
 
-static void integrator_clocksource_init(unsigned long inrate)
+static void integrator_clocksource_init(unsigned long inrate,
+					void __iomem *base)
 {
-	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 	unsigned long rate = inrate;
 
@@ -349,7 +334,7 @@ static void integrator_clocksource_init(unsigned long inrate)
 	setup_sched_clock(integrator_read_sched_clock, 16, rate);
 }
 
-static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
+static void __iomem * clkevt_base;
 
 /*
  * IRQ handler for the timer
@@ -421,11 +406,13 @@ static struct irqaction integrator_timer_irq = {
 	.dev_id		= &integrator_clockevent,
 };
 
-static void integrator_clockevent_init(unsigned long inrate)
+static void integrator_clockevent_init(unsigned long inrate,
+				void __iomem *base, int irq)
 {
 	unsigned long rate = inrate;
 	unsigned int ctrl = 0;
 
+	clkevt_base = base;
 	/* Calculate and program a divisor */
 	if (rate > 0x100000 * HZ) {
 		rate /= 256;
@@ -437,7 +424,7 @@ static void integrator_clockevent_init(unsigned long inrate)
 	timer_reload = rate / HZ;
 	writel(ctrl, clkevt_base + TIMER_CTRL);
 
-	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
+	setup_irq(irq, &integrator_timer_irq);
 	clockevents_config_and_register(&integrator_clockevent,
 					rate,
 					1,
@@ -448,9 +435,89 @@ void __init ap_init_early(void)
 {
 }
 
+#ifdef CONFIG_OF
+
+static void __init ap_init_timer_of(void)
+{
+	struct device_node *node;
+	const char *path;
+	void __iomem *base;
+	int err;
+	int irq;
+	struct clk *clk;
+	unsigned long rate;
+
+	clk = clk_get_sys("ap_timer", NULL);
+	BUG_ON(IS_ERR(clk));
+	clk_prepare_enable(clk);
+	rate = clk_get_rate(clk);
+
+	err = of_property_read_string(of_aliases,
+				"arm,integrator-clocksource", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	writel(0, base + TIMER_CTRL);
+	integrator_clocksource_init(rate, base);
+
+	err = of_property_read_string(of_aliases,
+				"arm,integrator-clockevent", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	irq = irq_of_parse_and_map(node, 0);
+	writel(0, base + TIMER_CTRL);
+	integrator_clockevent_init(rate, base, irq);
+}
+
+static struct sys_timer ap_of_timer = {
+	.init		= ap_init_timer_of,
+};
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init ap_init_irq_of(void)
+{
+	/* disable core module IRQs */
+	writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(false);
+}
+
+static const char * ap_dt_board_compat[] = {
+	"arm,integrator-ap",
+	NULL,
+};
+
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= ap_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
+	.init_early	= ap_init_early,
+	.init_irq	= ap_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &ap_of_timer,
+	.init_machine	= ap_init,
+	.restart	= integrator_restart,
+	.dt_compat      = ap_dt_board_compat,
+MACHINE_END
+
+#else
+
 /*
- * Set up timer(s).
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
  */
+
 static void __init ap_init_timer(void)
 {
 	struct clk *clk;
@@ -465,14 +532,32 @@ static void __init ap_init_timer(void)
 	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 
-	integrator_clocksource_init(rate);
-	integrator_clockevent_init(rate);
+	integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
+	integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
+				IRQ_TIMERINT1);
 }
 
 static struct sys_timer ap_timer = {
 	.init		= ap_init_timer,
 };
 
+#define INTEGRATOR_SC_VALID_INT	0x003fffff
+
+static void __init ap_init_irq(void)
+{
+	/* Disable all interrupts initially. */
+	/* Do the core module ones */
+	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+
+	/* do the header card stuff next */
+	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+		-1, INTEGRATOR_SC_VALID_INT, NULL);
+	integrator_clk_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
@@ -486,3 +571,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	.init_machine	= ap_init,
 	.restart	= integrator_restart,
 MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 2b40bc1..e7f2fb6 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,6 +23,8 @@
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -53,10 +55,6 @@
 
 #define INTCP_PA_CLCD_BASE		0xc0000000
 
-#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
-
 #define INTCP_ETH_SIZE			0x10
 
 #define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
@@ -143,37 +141,6 @@ static void __init intcp_map_io(void)
 	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
 
-static void __init intcp_init_irq(void)
-{
-	u32 pic_mask, cic_mask, sic_mask;
-
-	/* These masks are for the HW IRQ registers */
-	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-	pic_mask |= (~((~0u) << (29 - 22))) << 22;
-	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-
-	/*
-	 * Disable all interrupt sources
-	 */
-	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-
-	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-		      -1, pic_mask, NULL);
-
-	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-		      -1, cic_mask, NULL);
-
-	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-		      IRQ_CP_CPPLDINT, sic_mask, NULL);
-	integrator_clk_init(true);
-}
-
 /*
  * Flash handling.
  */
@@ -356,17 +323,114 @@ static void __init intcp_init_early(void)
 #endif
 }
 
-static void __init intcp_init(void)
+static void __init intcp_timer_init_of(void)
+{
+	struct device_node *node;
+	const char *path;
+	void __iomem *base;
+	int err;
+	int irq;
+
+	err = of_property_read_string(of_aliases,
+				"arm,integrator-clocksource", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	writel(0, base + TIMER_CTRL);
+	sp804_clocksource_init(base, node->name);
+
+	err = of_property_read_string(of_aliases,
+				"arm,integrator-clockevent", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	irq = irq_of_parse_and_map(node, 0);
+	writel(0, base + TIMER_CTRL);
+	sp804_clockevents_init(base, irq, node->name);
+}
+
+static struct sys_timer cp_of_timer = {
+	.init		= intcp_timer_init_of,
+};
+
+#ifdef CONFIG_OF
+
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init intcp_init_irq_of(void)
 {
-	int i;
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(true);
+}
 
-	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+static const char * intcp_dt_board_compat[] = {
+	"arm,integrator-cp",
+	NULL,
+};
 
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-	integrator_init(true);
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= intcp_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
+	.init_early	= intcp_init_early,
+	.init_irq	= intcp_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &cp_of_timer,
+	.init_machine	= intcp_init,
+	.restart	= integrator_restart,
+	.dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+
+#else
+
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+
+#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
+
+static void __init intcp_init_irq(void)
+{
+	u32 pic_mask, cic_mask, sic_mask;
+
+	/* These masks are for the HW IRQ registers */
+	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+	pic_mask |= (~((~0u) << (29 - 22))) << 22;
+	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+
+	/*
+	 * Disable all interrupt sources
+	 */
+	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+
+	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+		      -1, pic_mask, NULL);
+
+	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+		      -1, cic_mask, NULL);
+
+	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+		      IRQ_CP_CPPLDINT, sic_mask, NULL);
+
+	integrator_clk_init(true);
 }
 
 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
@@ -400,3 +464,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 	.init_machine	= intcp_init,
 	.restart	= integrator_restart,
 MACHINE_END
+
+#endif
-- 
1.7.11.4



From linus.walleij at linaro.org  Fri Aug 31 23:55:57 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:57 +0200
Subject: [PATCH 5/6 v2] ARM: integrator: convert AMBA devices to device tree
In-Reply-To: <1346471760-23993-4-git-send-email-linus.walleij@linaro.org>
References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-3-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-4-git-send-email-linus.walleij@linaro.org>
Message-ID: <1346471760-23993-5-git-send-email-linus.walleij@linaro.org>

This converts the AMBA (PrimeCell) devices on the Integrator/AP
and Integrator/CP over to probing from the Device Tree if the
kernel is compiled for Device Tree support.

We continue to #ifdef out all non-DT code and vice versa on
respective boot type to get a clean cut.

We need to add a bunch of auxdata (compare to the Versatile)
to handle bus names and callbacks alike.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Move interrupt-parent up one step to the fpga bus for the
  PrimeCell devices. (Suggestion from Arnd Bergmann)
---
 arch/arm/boot/dts/integratorap.dts       |  43 ++++++++++++
 arch/arm/boot/dts/integratorcp.dts       |  57 ++++++++++++++++
 arch/arm/mach-integrator/common.h        |   2 +
 arch/arm/mach-integrator/core.c          |   8 ++-
 arch/arm/mach-integrator/integrator_ap.c | 109 ++++++++++++++++++++++---------
 arch/arm/mach-integrator/integrator_cp.c |  84 ++++++++++++++++++------
 6 files changed, 250 insertions(+), 53 deletions(-)

diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 928a7be..de51bcf 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -48,4 +48,47 @@
 		clear-mask = <0xffffffff>;
 		valid-mask = <0x003fffff>;
 	};
+
+	fpga {
+		compatible = "arm,amba-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&pic>;
+
+		rtc: rtc at 15000000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x15000000 0x1000>;
+			interrupts = <8>;
+			arm,primecell-periphid = <0x00041030>;
+		};
+
+		uart0: uart at 16000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x16000000 0x1000>;
+			interrupts = <1>;
+			arm,primecell-periphid = <0x00041010>;
+		};
+
+		uart1: uart at 17000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x17000000 0x1000>;
+			interrupts = <2>;
+			arm,primecell-periphid = <0x00041010>;
+		};
+
+		kmi0: kmi at 18000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x18000000 0x1000>;
+			interrupts = <3>;
+			arm,primecell-periphid = <0x00041050>;
+		};
+
+		kmi1: kmi at 19000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x19000000 0x1000>;
+			interrupts = <4>;
+			arm,primecell-periphid = <0x00041050>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 8fad5a1..3265b25 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -66,4 +66,61 @@
 		clear-mask = <0x00000fff>;
 		valid-mask = <0x00000fff>;
 	};
+
+	fpga {
+		compatible = "arm,amba-bus", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		interrupt-parent = <&pic>;
+
+		rtc: rtc at 15000000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x15000000 0x1000>;
+			interrupts = <8>;
+		};
+
+		uart0: uart at 16000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x16000000 0x1000>;
+			interrupts = <1>;
+		};
+
+		uart1: uart at 17000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x17000000 0x1000>;
+			interrupts = <2>;
+		};
+
+		kmi0: kmi at 18000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x18000000 0x1000>;
+			interrupts = <3>;
+		};
+
+		kmi1: kmi at 19000000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x19000000 0x1000>;
+			interrupts = <4>;
+		};
+
+		mmci: mmc at 1C000000 {
+			compatible = "arm,pl180", "arm,primecell";
+			reg = <0x1C000000 0x1000>;
+			interrupts = <23 24>;
+			max-frequency = <515633>;
+		};
+
+		aaci: aaci at 1D000000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x1D000000 0x1000>;
+			interrupts = <25>;
+		};
+
+		clcd: clcd at c0000000 {
+			compatible = "arm,pl110", "arm,primecell";
+			reg = <0xC0000000 0x1000>;
+			interrupts = <22>;
+		};
+	};
 };
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index c4338e2..c3ff21b 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,3 +1,5 @@
+#include <linux/amba/serial.h>
+extern struct amba_pl010_data integrator_uart_data;
 void integrator_init_early(void);
 int integrator_init(bool is_cp);
 void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 67ea181..42890c8 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -33,7 +33,9 @@
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
 
-static struct amba_pl010_data integrator_uart_data;
+#include "common.h"
+
+#ifndef CONFIG_OF
 
 #define INTEGRATOR_RTC_IRQ	{ IRQ_RTCINT }
 #define INTEGRATOR_UART0_IRQ	{ IRQ_UARTINT0 }
@@ -86,6 +88,8 @@ int __init integrator_init(bool is_cp)
 	return 0;
 }
 
+#endif
+
 /*
  * On the Integrator platform, the port RTS and DTR are provided by
  * bits in the following SC_CTRLS register bits:
@@ -122,7 +126,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *bas
 	__raw_writel(ctrlc, SC_CTRLC);
 }
 
-static struct amba_pl010_data integrator_uart_data = {
+struct amba_pl010_data integrator_uart_data = {
 	.set_mctrl = integrator_uart_set_mctrl,
 };
 
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 26d4d8c..990ce85 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -36,6 +36,7 @@
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -271,36 +272,6 @@ static struct platform_device cfi_flash_device = {
 	.resource	= &cfi_flash_resource,
 };
 
-static void __init ap_init(void)
-{
-	unsigned long sc_dec;
-	int i;
-
-	platform_device_register(&cfi_flash_device);
-
-	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-	for (i = 0; i < 4; i++) {
-		struct lm_device *lmdev;
-
-		if ((sc_dec & (16 << i)) == 0)
-			continue;
-
-		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
-		if (!lmdev)
-			continue;
-
-		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-		lmdev->resource.flags = IORESOURCE_MEM;
-		lmdev->irq = IRQ_AP_EXPINT0 + i;
-		lmdev->id = i;
-
-		lm_device_register(lmdev);
-	}
-
-	integrator_init(false);
-}
-
 /*
  * Where is the timer (VA)?
  */
@@ -493,6 +464,52 @@ static void __init ap_init_irq_of(void)
 	integrator_clk_init(false);
 }
 
+/* For the Device Tree, add in the UART callbacks as AUXDATA */
+static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+		"rtc", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+		"uart0", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+		"uart1", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+		"kmi0", NULL),
+	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+		"kmi1", NULL),
+	{ /* sentinel */ },
+};
+
+static void __init ap_init_of(void)
+{
+	unsigned long sc_dec;
+	int i;
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			ap_auxdata_lookup, NULL);
+
+	platform_device_register(&cfi_flash_device);
+
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_AP_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+}
+
 static const char * ap_dt_board_compat[] = {
 	"arm,integrator-ap",
 	NULL,
@@ -506,7 +523,7 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 	.init_irq	= ap_init_irq_of,
 	.handle_irq	= fpga_handle_irq,
 	.timer		= &ap_of_timer,
-	.init_machine	= ap_init,
+	.init_machine	= ap_init_of,
 	.restart	= integrator_restart,
 	.dt_compat      = ap_dt_board_compat,
 MACHINE_END
@@ -558,6 +575,36 @@ static void __init ap_init_irq(void)
 	integrator_clk_init(false);
 }
 
+static void __init ap_init(void)
+{
+	unsigned long sc_dec;
+	int i;
+
+	platform_device_register(&cfi_flash_device);
+
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_AP_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+
+	integrator_init(false);
+}
+
 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index e7f2fb6..1b07aa6 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -25,6 +25,7 @@
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
+#include <linux/of_platform.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -245,16 +246,6 @@ static struct mmci_platform_data mmc_data = {
 	.gpio_cd	= -1,
 };
 
-#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
-#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }
-
-static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
-	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
-
-static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
-	INTEGRATOR_CP_AACI_IRQS, NULL);
-
-
 /*
  * CLCD support
  */
@@ -305,15 +296,6 @@ static struct clcd_board clcd_data = {
 	.remove		= versatile_clcd_remove_dma,
 };
 
-static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
-	{ IRQ_CP_CLCDCINT }, &clcd_data);
-
-static struct amba_device *amba_devs[] __initdata = {
-	&mmc_device,
-	&aaci_device,
-	&clcd_device,
-};
-
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 
 static void __init intcp_init_early(void)
@@ -372,6 +354,37 @@ static void __init intcp_init_irq_of(void)
 	integrator_clk_init(true);
 }
 
+/*
+ * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
+ * and enforce the bus names since these are used for clock lookups.
+ */
+static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
+		"rtc", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
+		"uart0", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
+		"uart1", &integrator_uart_data),
+	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
+		"kmi0", NULL),
+	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
+		"kmi1", NULL),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
+		"mmci", &mmc_data),
+	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
+		"aaci", &mmc_data),
+	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
+		"clcd", &clcd_data),
+	{ /* sentinel */ },
+};
+
+static void __init intcp_init_of(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			intcp_auxdata_lookup, NULL);
+	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+}
+
 static const char * intcp_dt_board_compat[] = {
 	"arm,integrator-cp",
 	NULL,
@@ -385,7 +398,7 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
 	.init_irq	= intcp_init_irq_of,
 	.handle_irq	= fpga_handle_irq,
 	.timer		= &cp_of_timer,
-	.init_machine	= intcp_init,
+	.init_machine	= intcp_init_of,
 	.restart	= integrator_restart,
 	.dt_compat      = intcp_dt_board_compat,
 MACHINE_END
@@ -451,6 +464,37 @@ static struct sys_timer cp_timer = {
 	.init		= intcp_timer_init,
 };
 
+#define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }
+
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
+	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
+	INTEGRATOR_CP_AACI_IRQS, NULL);
+
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
+	{ IRQ_CP_CLCDCINT }, &clcd_data);
+
+static struct amba_device *amba_devs[] __initdata = {
+	&mmc_device,
+	&aaci_device,
+	&clcd_device,
+};
+
+static void __init intcp_init(void)
+{
+	int i;
+
+	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+
+	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+		struct amba_device *d = amba_devs[i];
+		amba_device_register(d, &iomem_resource);
+	}
+	integrator_init(true);
+}
+
 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 	.atag_offset	= 0x100,
-- 
1.7.11.4



From linus.walleij at linaro.org  Fri Aug 31 23:55:58 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Sat,  1 Sep 2012 05:55:58 +0200
Subject: [PATCH 6/6 v2] ARM: integrator: convert platform devices to Device
 Tree
In-Reply-To: <1346471760-23993-5-git-send-email-linus.walleij@linaro.org>
References: <1346471760-23993-1-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-2-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-3-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-4-git-send-email-linus.walleij@linaro.org>
 <1346471760-23993-5-git-send-email-linus.walleij@linaro.org>
Message-ID: <1346471760-23993-6-git-send-email-linus.walleij@linaro.org>

This moves the physmap flash and SMSC91x ethernet devices
over to the device tree, moving the static board code down
into the #ifndef CONFIG_OF section.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/integratorap.dts       |  5 ++
 arch/arm/boot/dts/integratorcp.dts       | 12 +++++
 arch/arm/mach-integrator/integrator_ap.c | 36 ++++++-------
 arch/arm/mach-integrator/integrator_cp.c | 92 ++++++++++++++++----------------
 4 files changed, 82 insertions(+), 63 deletions(-)

diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index de51bcf..044c72b 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -49,6 +49,11 @@
 		valid-mask = <0x003fffff>;
 	};
 
+	flash: flash at 24000000 {
+		compatible = "cfi-flash";
+		reg = <0x24000000 0x02000000>;
+	};
+
 	fpga {
 		compatible = "arm,amba-bus", "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 3265b25..8584241 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -67,6 +67,18 @@
 		valid-mask = <0x00000fff>;
 	};
 
+	flash: flash at 24000000 {
+		compatible = "cfi-flash";
+		reg = <0x24000000 0x02000000>;
+	};
+
+	ethernet: ethernet at c8000000 {
+		compatible = "smsc,lan91c111";
+		reg = <0xc8000000 0x10>;
+		interrupt-parent = <&pic>;
+		interrupts = <27>;
+	};
+
 	fpga {
 		compatible = "arm,amba-bus", "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 990ce85..aaa6b01 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -256,22 +256,6 @@ static struct physmap_flash_data ap_flash_data = {
 	.set_vpp	= ap_flash_set_vpp,
 };
 
-static struct resource cfi_flash_resource = {
-	.start		= INTEGRATOR_FLASH_BASE,
-	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device cfi_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &ap_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &cfi_flash_resource,
-};
-
 /*
  * Where is the timer (VA)?
  */
@@ -476,6 +460,8 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 		"kmi0", NULL),
 	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
 		"kmi1", NULL),
+	OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
+		"physmap-flash", &ap_flash_data),
 	{ /* sentinel */ },
 };
 
@@ -487,8 +473,6 @@ static void __init ap_init_of(void)
 	of_platform_populate(NULL, of_default_bus_match_table,
 			ap_auxdata_lookup, NULL);
 
-	platform_device_register(&cfi_flash_device);
-
 	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 	for (i = 0; i < 4; i++) {
 		struct lm_device *lmdev;
@@ -535,6 +519,22 @@ MACHINE_END
  * for eventual deletion.
  */
 
+static struct resource cfi_flash_resource = {
+	.start		= INTEGRATOR_FLASH_BASE,
+	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device cfi_flash_device = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &ap_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &cfi_flash_resource,
+};
+
 static void __init ap_init_timer(void)
 {
 	struct clk *clk;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 1b07aa6..1f4a7be 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -52,12 +52,9 @@
 #include "common.h"
 
 #define INTCP_PA_FLASH_BASE		0x24000000
-#define INTCP_FLASH_SIZE		SZ_32M
 
 #define INTCP_PA_CLCD_BASE		0xc0000000
 
-#define INTCP_ETH_SIZE			0x10
-
 #define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG			0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
@@ -184,47 +181,6 @@ static struct physmap_flash_data intcp_flash_data = {
 	.set_vpp	= intcp_flash_set_vpp,
 };
 
-static struct resource intcp_flash_resource = {
-	.start		= INTCP_PA_FLASH_BASE,
-	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device intcp_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &intcp_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &intcp_flash_resource,
-};
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= INTEGRATOR_CP_ETH_BASE,
-		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_CP_ETHINT,
-		.end	= IRQ_CP_ETHINT,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *intcp_devs[] __initdata = {
-	&intcp_flash_device,
-	&smc91x_device,
-};
-
 /*
  * It seems that the card insertion interrupt remains active after
  * we've acknowledged it.  We therefore ignore the interrupt, and
@@ -375,6 +331,8 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
 		"aaci", &mmc_data),
 	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
 		"clcd", &clcd_data),
+	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
+		"physmap-flash", &intcp_flash_data),
 	{ /* sentinel */ },
 };
 
@@ -382,7 +340,6 @@ static void __init intcp_init_of(void)
 {
 	of_platform_populate(NULL, of_default_bus_match_table,
 			intcp_auxdata_lookup, NULL);
-	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 }
 
 static const char * intcp_dt_board_compat[] = {
@@ -410,6 +367,51 @@ MACHINE_END
  * for eventual deletion.
  */
 
+#define INTCP_FLASH_SIZE		SZ_32M
+
+static struct resource intcp_flash_resource = {
+	.start		= INTCP_PA_FLASH_BASE,
+	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device intcp_flash_device = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &intcp_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &intcp_flash_resource,
+};
+
+#define INTCP_ETH_SIZE			0x10
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	= INTEGRATOR_CP_ETH_BASE,
+		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_CP_ETHINT,
+		.end	= IRQ_CP_ETHINT,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *intcp_devs[] __initdata = {
+	&intcp_flash_device,
+	&smc91x_device,
+};
+
 #define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
 #define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
 #define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
-- 
1.7.11.4



From robherring2 at gmail.com  Fri Aug 31 20:48:42 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 31 Aug 2012 19:48:42 -0500
Subject: [PATCH 1/6] ARM: move ARCH config definitions into mach dirs
In-Reply-To: <20120830192831.GD18957@n2100.arm.linux.org.uk>
References: <1346280600-29395-1-git-send-email-robherring2@gmail.com>
 <1346280600-29395-2-git-send-email-robherring2@gmail.com>
 <20120829233159.GS18957@n2100.arm.linux.org.uk> <503F845C.10406@gmail.com>
 <20120830164551.GY18957@n2100.arm.linux.org.uk> <503FB9E6.7020102@gmail.com>
 <20120830192831.GD18957@n2100.arm.linux.org.uk>
Message-ID: <50415B6A.5060601@gmail.com>

On 08/30/2012 02:28 PM, Russell King - ARM Linux wrote:
> On Thu, Aug 30, 2012 at 02:07:18PM -0500, Rob Herring wrote:
>> On 08/30/2012 11:45 AM, Russell King - ARM Linux wrote:
>>> That also means we can start to think about moving the mach/debug-macros.S
>>> header elsewhere, remembering that this facility is shared between the
>>> decompressor for debugging and the kernel.
>>
>> I was thinking we could convert the phys and virt addresses to config
>> values and then the DEBUG_LL choices could just be "Use PL01x uart" and
>> "Use 8250 uart". This would cut down the number of debug-macro.S files
>> and choices.
>>
>> Using a fixed virtual address for all platforms might also help simplify
>> DEBUG_LL.
> 
> No it won't, that comment says you totally don't understand the feature
> you're playing with to me.

Or you don't understand what I meant.

> It's not only about virtual addresses, it's about physical addresses too,
> and we can't dictate that all hardware exposes a UART at any particular
> physical address.

We have 3 things to track for each platform: the type of uart, the
uart's phys address, and the virtual address we map it to. Obviously, we
can't get rid of the first 2, but we can align the virtual address to
the same 1MB section for DEBUG_LL on all platforms. Then we only have 2
differences to deal with. If we make the physical address a config
value, then we could unify all the addruart implementations (except
perhaps for the crazy stuff omap does). So something like this:

		.macro	addruart,rp,rv,tmp
		mov	\rv, #0xfe000000
		orr	\rv, \rv, #0x00d00000
		ldr	\rp, =CONFIG_DEBUG_LL_UART_ADDR
		lsl	\tmp, \rp, #12
		lsr	\tmp, \tmp, #12
		orr	\rv, \rv, \tmp
		.endm

Of course we'd have to shift around static mappings to free up whatever
address we use. I don't know if 0xfed00000 would be the best choice, but
that is just below were I put the PCI i/o mapping.

Rob




From sandro.viti at gmail.com  Wed Aug  1 04:06:40 2012
From: sandro.viti at gmail.com (Sandro Viti)
Date: Wed, 01 Aug 2012 08:06:40 -0000
Subject: Kernel relocate on beaglebone
Message-ID: <18095ED2-616B-46FB-8404-2E5D344185F2@gmail.com>

Dear All,

i'm trying to relocate kernel to load on a different address than the usual 0x80008000 that is the start of my 256M ddr. The platform is a beaglebone. Kernel is 3.2.21 Debian Squeeze based on Robert CNelson work (http://eewiki.net/display/linuxonarm/BeagleBone).


This is needed for me because i need to reserve 16M at the start of ddr to be used as a special buffer for data to be sent.


This is my output from "cat /proc/iomem" of the standard build:
80000000-8fffffff : System RAM
   80008000-806a6fff : Kernel text
   806e6000-8076fb1b : Kernel data

I tried to change the address where the kernel is loaded, thus the ZRELADDRESS option in the build_kernel.sh to something bigger than 0x80008000, let's say 0x8A008000, but the u-boot loader hangs just after extracting the kernel.
This is the output:
Hit any key to stop autoboot:  0 
SD/MMC found on device 0
reading uEnv.txt

316 bytes read
Loaded environment from uEnv.txt
Importing environment from mmc ...
reading uImage

2658120 bytes read
## Booting kernel from Legacy Image at 80300000 ...
   Image Name:   VISALINUX
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2658056 Bytes = 2.5 MiB
   Load Address: 8a008000
   Entry Point:  8a008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

Then it hangs..

I also then tried to tweak values on arch/arm/mach-omap2/Makefile.boot to:

zreladdr-y +: 0x8a008000

params_phys-y := 0x82000100

Initrd_phys-y := 0x82800000

But nothing change

Any of you have some info to share to understand why this is happening and what is the best way to do this shift in kernel loading?

Thanks

Alex Viti
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From arnd at arndb.de  Wed Aug  1 13:20:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 01 Aug 2012 17:20:44 -0000
Subject: [RFC 20/22] ARM: keystone: introducing TI Keystone platform
In-Reply-To: <50194E14.4070301@ti.com>
References: <1343775898-28345-1-git-send-email-cyril@ti.com>
 <201207312316.19592.arnd@arndb.de> <50194E14.4070301@ti.com>
Message-ID: <3021860.0mUoOFAv0G@wuerfel>

On Wednesday 01 August 2012 11:41:08 Cyril Chemparathy wrote:
> On 7/31/2012 7:16 PM, Arnd Bergmann wrote:
> > On Tuesday 31 July 2012, Cyril Chemparathy wrote:
> >> Texas Instruments Keystone family of multicore devices now includes an
> >> upcoming slew of Cortex A15 based devices.  This patch adds basic definitions
> >> for a new Keystone sub-architecture in ARM.
> >>
> >> Subsequent patches in this series will extend support to include SMP and take
> >> advantage of the large physical memory addressing capabilities via LPAE.
> >>
> >> Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
> >> Signed-off-by: Cyril Chemparathy <cyril at ti.com>
> >
> > Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> >
> 
> Thanks for taking a look, Arnd.
> 
> Any inputs on the other patches in this series?

I briefly looked over them and they largely looked ok, but I'm not really
qualified to comment on most of them.

	Arnd
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From luffy.sun at ymail.com  Thu Aug  2 02:00:25 2012
From: luffy.sun at ymail.com (Luffy Sun)
Date: Thu, 02 Aug 2012 06:00:25 -0000
Subject: Vector Modified
Message-ID: <1343887222.77573.YahooMailNeo@web121605.mail.ne1.yahoo.com>

Hi,? All,



I have tested crashme on Marvell PXA920 processor with kernel 3.5-rc6.? System will hang 
during testing. 
Sometimes, the board could be connected by JTAG.? I found the?vector_dabt(address 0xFFFF0010) have been
modified. The instruction 
should be a jump instruction. But it have been modified to "BKPT 0x1"? or "Undefined".
The Vector modification doesn't? happen every time when testing.? 


Have anyone encountered with this status ?? Why arm vector is modified?
Thanks in advance.

BR,
Luffy
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From u.kleine-koenig at pengutronix.de  Thu Aug  2 11:39:19 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 02 Aug 2012 15:39:19 -0000
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
Message-ID: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>

This is mostly cut'n'paste from the imx51 pinctrl driver.

Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Stephen Warren <swarren at wwwdotorg.org>
Cc: Dong Aisheng <dong.aisheng at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 .../bindings/pinctrl/fsl,imx35-pinctrl.txt         |  985 ++++++++++++
 drivers/pinctrl/Kconfig                            |    8 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-imx35.c                    | 1598 ++++++++++++++++++++
 4 files changed, 2592 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-imx35.c

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
new file mode 100644
index 0000000..8cc07c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
@@ -0,0 +1,985 @@
+* Freescale IMX35 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx35-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_DRIVE_VOLAGAGE_18	(1 << 13)
+PAD_CTL_DRIVE_VOLAGAGE_33	(0 << 13)
+PAD_CTL_HYS			(1 << 8)
+PAD_CTL_PKE			(1 << 7)
+PAD_CTL_PUE			(1 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_ODE_CMOS		(0 << 3)
+PAD_CTL_ODE_OPENDRAIN		(1 << 3)
+PAD_CTL_DSE_NOMINAL		(0 << 1)
+PAD_CTL_DSE_HIGH		(1 << 1)
+PAD_CTL_DSE_MAX			(2 << 1)
+PAD_CTL_SRE_FAST		(1 << 0)
+PAD_CTL_SRE_SLOW		(0 << 0)
+
+See below for available PIN_FUNC_ID for imx35:
+# grep '   IMX_PIN_REG' drivers/pinctrl/pinctrl-imx35.c | awk '{ print NR-1 " " $8 }'
+0 MX35_PAD_CAPTURE__GPT_CAPIN1
+1 MX35_PAD_CAPTURE__GPT_CMPOUT2
+2 MX35_PAD_CAPTURE__CSPI2_SS1
+3 MX35_PAD_CAPTURE__EPIT1_EPITO
+4 MX35_PAD_CAPTURE__CCM_CLK32K
+5 MX35_PAD_CAPTURE__GPIO1_4
+6 MX35_PAD_COMPARE__GPT_CMPOUT1
+7 MX35_PAD_COMPARE__GPT_CAPIN2
+8 MX35_PAD_COMPARE__GPT_CMPOUT3
+9 MX35_PAD_COMPARE__EPIT2_EPITO
+10 MX35_PAD_COMPARE__GPIO1_5
+11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
+12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
+13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
+14 MX35_PAD_WDOG_RST__GPIO1_6
+15 MX35_PAD_GPIO1_0__GPIO1_0
+16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
+17 MX35_PAD_GPIO1_0__OWIRE_LINE
+18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
+19 MX35_PAD_GPIO1_1__GPIO1_1
+20 MX35_PAD_GPIO1_1__PWM_PWMO
+21 MX35_PAD_GPIO1_1__CSPI1_SS2
+22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
+23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
+24 MX35_PAD_GPIO2_0__GPIO2_0
+25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
+26 MX35_PAD_GPIO3_0__GPIO3_0
+27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
+28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
+29 MX35_PAD_POR_B__CCM_POR_B
+30 MX35_PAD_CLKO__CCM_CLKO
+31 MX35_PAD_CLKO__GPIO1_8
+32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
+33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
+34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
+35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
+36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
+37 MX35_PAD_VSTBY__CCM_VSTBY
+38 MX35_PAD_VSTBY__GPIO1_7
+39 MX35_PAD_A0__EMI_EIM_DA_L_0
+40 MX35_PAD_A1__EMI_EIM_DA_L_1
+41 MX35_PAD_A2__EMI_EIM_DA_L_2
+42 MX35_PAD_A3__EMI_EIM_DA_L_3
+43 MX35_PAD_A4__EMI_EIM_DA_L_4
+44 MX35_PAD_A5__EMI_EIM_DA_L_5
+45 MX35_PAD_A6__EMI_EIM_DA_L_6
+46 MX35_PAD_A7__EMI_EIM_DA_L_7
+47 MX35_PAD_A8__EMI_EIM_DA_H_8
+48 MX35_PAD_A9__EMI_EIM_DA_H_9
+49 MX35_PAD_A10__EMI_EIM_DA_H_10
+50 MX35_PAD_MA10__EMI_MA10
+51 MX35_PAD_A11__EMI_EIM_DA_H_11
+52 MX35_PAD_A12__EMI_EIM_DA_H_12
+53 MX35_PAD_A13__EMI_EIM_DA_H_13
+54 MX35_PAD_A14__EMI_EIM_DA_H2_14
+55 MX35_PAD_A15__EMI_EIM_DA_H2_15
+56 MX35_PAD_A16__EMI_EIM_A_16
+57 MX35_PAD_A17__EMI_EIM_A_17
+58 MX35_PAD_A18__EMI_EIM_A_18
+59 MX35_PAD_A19__EMI_EIM_A_19
+60 MX35_PAD_A20__EMI_EIM_A_20
+61 MX35_PAD_A21__EMI_EIM_A_21
+62 MX35_PAD_A22__EMI_EIM_A_22
+63 MX35_PAD_A23__EMI_EIM_A_23
+64 MX35_PAD_A24__EMI_EIM_A_24
+65 MX35_PAD_A25__EMI_EIM_A_25
+66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
+67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
+68 MX35_PAD_SD0__EMI_DRAM_D_0
+69 MX35_PAD_SD1__EMI_DRAM_D_1
+70 MX35_PAD_SD2__EMI_DRAM_D_2
+71 MX35_PAD_SD3__EMI_DRAM_D_3
+72 MX35_PAD_SD4__EMI_DRAM_D_4
+73 MX35_PAD_SD5__EMI_DRAM_D_5
+74 MX35_PAD_SD6__EMI_DRAM_D_6
+75 MX35_PAD_SD7__EMI_DRAM_D_7
+76 MX35_PAD_SD8__EMI_DRAM_D_8
+77 MX35_PAD_SD9__EMI_DRAM_D_9
+78 MX35_PAD_SD10__EMI_DRAM_D_10
+79 MX35_PAD_SD11__EMI_DRAM_D_11
+80 MX35_PAD_SD12__EMI_DRAM_D_12
+81 MX35_PAD_SD13__EMI_DRAM_D_13
+82 MX35_PAD_SD14__EMI_DRAM_D_14
+83 MX35_PAD_SD15__EMI_DRAM_D_15
+84 MX35_PAD_SD16__EMI_DRAM_D_16
+85 MX35_PAD_SD17__EMI_DRAM_D_17
+86 MX35_PAD_SD18__EMI_DRAM_D_18
+87 MX35_PAD_SD19__EMI_DRAM_D_19
+88 MX35_PAD_SD20__EMI_DRAM_D_20
+89 MX35_PAD_SD21__EMI_DRAM_D_21
+90 MX35_PAD_SD22__EMI_DRAM_D_22
+91 MX35_PAD_SD23__EMI_DRAM_D_23
+92 MX35_PAD_SD24__EMI_DRAM_D_24
+93 MX35_PAD_SD25__EMI_DRAM_D_25
+94 MX35_PAD_SD26__EMI_DRAM_D_26
+95 MX35_PAD_SD27__EMI_DRAM_D_27
+96 MX35_PAD_SD28__EMI_DRAM_D_28
+97 MX35_PAD_SD29__EMI_DRAM_D_29
+98 MX35_PAD_SD30__EMI_DRAM_D_30
+99 MX35_PAD_SD31__EMI_DRAM_D_31
+100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
+101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
+102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
+103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
+104 MX35_PAD_EB0__EMI_EIM_EB0_B
+105 MX35_PAD_EB1__EMI_EIM_EB1_B
+106 MX35_PAD_OE__EMI_EIM_OE
+107 MX35_PAD_CS0__EMI_EIM_CS0
+108 MX35_PAD_CS1__EMI_EIM_CS1
+109 MX35_PAD_CS1__EMI_NANDF_CE3
+110 MX35_PAD_CS2__EMI_EIM_CS2
+111 MX35_PAD_CS3__EMI_EIM_CS3
+112 MX35_PAD_CS4__EMI_EIM_CS4
+113 MX35_PAD_CS4__EMI_DTACK_B
+114 MX35_PAD_CS4__EMI_NANDF_CE1
+115 MX35_PAD_CS4__GPIO1_20
+116 MX35_PAD_CS5__EMI_EIM_CS5
+117 MX35_PAD_CS5__CSPI2_SS2
+118 MX35_PAD_CS5__CSPI1_SS2
+119 MX35_PAD_CS5__EMI_NANDF_CE2
+120 MX35_PAD_CS5__GPIO1_21
+121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
+122 MX35_PAD_NF_CE0__GPIO1_22
+123 MX35_PAD_ECB__EMI_EIM_ECB
+124 MX35_PAD_LBA__EMI_EIM_LBA
+125 MX35_PAD_BCLK__EMI_EIM_BCLK
+126 MX35_PAD_RW__EMI_EIM_RW
+127 MX35_PAD_RAS__EMI_DRAM_RAS
+128 MX35_PAD_CAS__EMI_DRAM_CAS
+129 MX35_PAD_SDWE__EMI_DRAM_SDWE
+130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
+131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
+132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
+133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
+134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
+135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
+136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
+137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
+138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
+139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
+140 MX35_PAD_NFWE_B__GPIO2_18
+141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
+142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
+143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
+144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
+145 MX35_PAD_NFRE_B__GPIO2_19
+146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
+147 MX35_PAD_NFALE__EMI_NANDF_ALE
+148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
+149 MX35_PAD_NFALE__IPU_DISPB_CS0
+150 MX35_PAD_NFALE__GPIO2_20
+151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
+152 MX35_PAD_NFCLE__EMI_NANDF_CLE
+153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
+154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
+155 MX35_PAD_NFCLE__GPIO2_21
+156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
+157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
+158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
+159 MX35_PAD_NFWP_B__IPU_DISPB_WR
+160 MX35_PAD_NFWP_B__GPIO2_22
+161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
+162 MX35_PAD_NFRB__EMI_NANDF_RB
+163 MX35_PAD_NFRB__IPU_DISPB_RD
+164 MX35_PAD_NFRB__GPIO2_23
+165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
+166 MX35_PAD_D15__EMI_EIM_D_15
+167 MX35_PAD_D14__EMI_EIM_D_14
+168 MX35_PAD_D13__EMI_EIM_D_13
+169 MX35_PAD_D12__EMI_EIM_D_12
+170 MX35_PAD_D11__EMI_EIM_D_11
+171 MX35_PAD_D10__EMI_EIM_D_10
+172 MX35_PAD_D9__EMI_EIM_D_9
+173 MX35_PAD_D8__EMI_EIM_D_8
+174 MX35_PAD_D7__EMI_EIM_D_7
+175 MX35_PAD_D6__EMI_EIM_D_6
+176 MX35_PAD_D5__EMI_EIM_D_5
+177 MX35_PAD_D4__EMI_EIM_D_4
+178 MX35_PAD_D3__EMI_EIM_D_3
+179 MX35_PAD_D2__EMI_EIM_D_2
+180 MX35_PAD_D1__EMI_EIM_D_1
+181 MX35_PAD_D0__EMI_EIM_D_0
+182 MX35_PAD_CSI_D8__IPU_CSI_D_8
+183 MX35_PAD_CSI_D8__KPP_COL_0
+184 MX35_PAD_CSI_D8__GPIO1_20
+185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
+186 MX35_PAD_CSI_D9__IPU_CSI_D_9
+187 MX35_PAD_CSI_D9__KPP_COL_1
+188 MX35_PAD_CSI_D9__GPIO1_21
+189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
+190 MX35_PAD_CSI_D10__IPU_CSI_D_10
+191 MX35_PAD_CSI_D10__KPP_COL_2
+192 MX35_PAD_CSI_D10__GPIO1_22
+193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
+194 MX35_PAD_CSI_D11__IPU_CSI_D_11
+195 MX35_PAD_CSI_D11__KPP_COL_3
+196 MX35_PAD_CSI_D11__GPIO1_23
+197 MX35_PAD_CSI_D12__IPU_CSI_D_12
+198 MX35_PAD_CSI_D12__KPP_ROW_0
+199 MX35_PAD_CSI_D12__GPIO1_24
+200 MX35_PAD_CSI_D13__IPU_CSI_D_13
+201 MX35_PAD_CSI_D13__KPP_ROW_1
+202 MX35_PAD_CSI_D13__GPIO1_25
+203 MX35_PAD_CSI_D14__IPU_CSI_D_14
+204 MX35_PAD_CSI_D14__KPP_ROW_2
+205 MX35_PAD_CSI_D14__GPIO1_26
+206 MX35_PAD_CSI_D15__IPU_CSI_D_15
+207 MX35_PAD_CSI_D15__KPP_ROW_3
+208 MX35_PAD_CSI_D15__GPIO1_27
+209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
+210 MX35_PAD_CSI_MCLK__GPIO1_28
+211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
+212 MX35_PAD_CSI_VSYNC__GPIO1_29
+213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
+214 MX35_PAD_CSI_HSYNC__GPIO1_30
+215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
+216 MX35_PAD_CSI_PIXCLK__GPIO1_31
+217 MX35_PAD_I2C1_CLK__I2C1_SCL
+218 MX35_PAD_I2C1_CLK__GPIO2_24
+219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
+220 MX35_PAD_I2C1_DAT__I2C1_SDA
+221 MX35_PAD_I2C1_DAT__GPIO2_25
+222 MX35_PAD_I2C2_CLK__I2C2_SCL
+223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
+224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
+225 MX35_PAD_I2C2_CLK__GPIO2_26
+226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
+227 MX35_PAD_I2C2_DAT__I2C2_SDA
+228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
+229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
+230 MX35_PAD_I2C2_DAT__GPIO2_27
+231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
+232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
+233 MX35_PAD_STXD4__GPIO2_28
+234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
+235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
+236 MX35_PAD_SRXD4__GPIO2_29
+237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
+238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
+239 MX35_PAD_SCK4__GPIO2_30
+240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
+241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
+242 MX35_PAD_STXFS4__GPIO2_31
+243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
+244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
+245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
+246 MX35_PAD_STXD5__CSPI2_MOSI
+247 MX35_PAD_STXD5__GPIO1_0
+248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
+249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
+250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
+251 MX35_PAD_SRXD5__CSPI2_MISO
+252 MX35_PAD_SRXD5__GPIO1_1
+253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
+254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
+255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
+256 MX35_PAD_SCK5__CSPI2_SCLK
+257 MX35_PAD_SCK5__GPIO1_2
+258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
+259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
+260 MX35_PAD_STXFS5__CSPI2_RDY
+261 MX35_PAD_STXFS5__GPIO1_3
+262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
+263 MX35_PAD_SCKR__ESAI_SCKR
+264 MX35_PAD_SCKR__GPIO1_4
+265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
+266 MX35_PAD_FSR__ESAI_FSR
+267 MX35_PAD_FSR__GPIO1_5
+268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
+269 MX35_PAD_HCKR__ESAI_HCKR
+270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
+271 MX35_PAD_HCKR__CSPI2_SS0
+272 MX35_PAD_HCKR__IPU_FLASH_STROBE
+273 MX35_PAD_HCKR__GPIO1_6
+274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
+275 MX35_PAD_SCKT__ESAI_SCKT
+276 MX35_PAD_SCKT__GPIO1_7
+277 MX35_PAD_SCKT__IPU_CSI_D_0
+278 MX35_PAD_SCKT__KPP_ROW_2
+279 MX35_PAD_FST__ESAI_FST
+280 MX35_PAD_FST__GPIO1_8
+281 MX35_PAD_FST__IPU_CSI_D_1
+282 MX35_PAD_FST__KPP_ROW_3
+283 MX35_PAD_HCKT__ESAI_HCKT
+284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
+285 MX35_PAD_HCKT__GPIO1_9
+286 MX35_PAD_HCKT__IPU_CSI_D_2
+287 MX35_PAD_HCKT__KPP_COL_3
+288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
+289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
+290 MX35_PAD_TX5_RX0__CSPI2_SS2
+291 MX35_PAD_TX5_RX0__CAN2_TXCAN
+292 MX35_PAD_TX5_RX0__UART2_DTR
+293 MX35_PAD_TX5_RX0__GPIO1_10
+294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
+295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
+296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
+297 MX35_PAD_TX4_RX1__CSPI2_SS3
+298 MX35_PAD_TX4_RX1__CAN2_RXCAN
+299 MX35_PAD_TX4_RX1__UART2_DSR
+300 MX35_PAD_TX4_RX1__GPIO1_11
+301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
+302 MX35_PAD_TX4_RX1__KPP_ROW_0
+303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
+304 MX35_PAD_TX3_RX2__I2C3_SCL
+305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
+306 MX35_PAD_TX3_RX2__GPIO1_12
+307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
+308 MX35_PAD_TX3_RX2__KPP_ROW_1
+309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
+310 MX35_PAD_TX2_RX3__I2C3_SDA
+311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
+312 MX35_PAD_TX2_RX3__GPIO1_13
+313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
+314 MX35_PAD_TX2_RX3__KPP_COL_0
+315 MX35_PAD_TX1__ESAI_TX1
+316 MX35_PAD_TX1__CCM_PMIC_RDY
+317 MX35_PAD_TX1__CSPI1_SS2
+318 MX35_PAD_TX1__EMI_NANDF_CE3
+319 MX35_PAD_TX1__UART2_RI
+320 MX35_PAD_TX1__GPIO1_14
+321 MX35_PAD_TX1__IPU_CSI_D_6
+322 MX35_PAD_TX1__KPP_COL_1
+323 MX35_PAD_TX0__ESAI_TX0
+324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
+325 MX35_PAD_TX0__CSPI1_SS3
+326 MX35_PAD_TX0__EMI_DTACK_B
+327 MX35_PAD_TX0__UART2_DCD
+328 MX35_PAD_TX0__GPIO1_15
+329 MX35_PAD_TX0__IPU_CSI_D_7
+330 MX35_PAD_TX0__KPP_COL_2
+331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
+332 MX35_PAD_CSPI1_MOSI__GPIO1_16
+333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
+334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
+335 MX35_PAD_CSPI1_MISO__GPIO1_17
+336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
+337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
+338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
+339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
+340 MX35_PAD_CSPI1_SS0__GPIO1_18
+341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
+342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
+343 MX35_PAD_CSPI1_SS1__PWM_PWMO
+344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
+345 MX35_PAD_CSPI1_SS1__GPIO1_19
+346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
+347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
+348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
+349 MX35_PAD_CSPI1_SCLK__GPIO3_4
+350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
+351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
+352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
+353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
+354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
+355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
+356 MX35_PAD_RXD1__UART1_RXD_MUX
+357 MX35_PAD_RXD1__CSPI2_MOSI
+358 MX35_PAD_RXD1__KPP_COL_4
+359 MX35_PAD_RXD1__GPIO3_6
+360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
+361 MX35_PAD_TXD1__UART1_TXD_MUX
+362 MX35_PAD_TXD1__CSPI2_MISO
+363 MX35_PAD_TXD1__KPP_COL_5
+364 MX35_PAD_TXD1__GPIO3_7
+365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
+366 MX35_PAD_RTS1__UART1_RTS
+367 MX35_PAD_RTS1__CSPI2_SCLK
+368 MX35_PAD_RTS1__I2C3_SCL
+369 MX35_PAD_RTS1__IPU_CSI_D_0
+370 MX35_PAD_RTS1__KPP_COL_6
+371 MX35_PAD_RTS1__GPIO3_8
+372 MX35_PAD_RTS1__EMI_NANDF_CE1
+373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
+374 MX35_PAD_CTS1__UART1_CTS
+375 MX35_PAD_CTS1__CSPI2_RDY
+376 MX35_PAD_CTS1__I2C3_SDA
+377 MX35_PAD_CTS1__IPU_CSI_D_1
+378 MX35_PAD_CTS1__KPP_COL_7
+379 MX35_PAD_CTS1__GPIO3_9
+380 MX35_PAD_CTS1__EMI_NANDF_CE2
+381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
+382 MX35_PAD_RXD2__UART2_RXD_MUX
+383 MX35_PAD_RXD2__KPP_ROW_4
+384 MX35_PAD_RXD2__GPIO3_10
+385 MX35_PAD_TXD2__UART2_TXD_MUX
+386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
+387 MX35_PAD_TXD2__KPP_ROW_5
+388 MX35_PAD_TXD2__GPIO3_11
+389 MX35_PAD_RTS2__UART2_RTS
+390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
+391 MX35_PAD_RTS2__CAN2_RXCAN
+392 MX35_PAD_RTS2__IPU_CSI_D_2
+393 MX35_PAD_RTS2__KPP_ROW_6
+394 MX35_PAD_RTS2__GPIO3_12
+395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
+396 MX35_PAD_RTS2__UART3_RXD_MUX
+397 MX35_PAD_CTS2__UART2_CTS
+398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
+399 MX35_PAD_CTS2__CAN2_TXCAN
+400 MX35_PAD_CTS2__IPU_CSI_D_3
+401 MX35_PAD_CTS2__KPP_ROW_7
+402 MX35_PAD_CTS2__GPIO3_13
+403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
+404 MX35_PAD_CTS2__UART3_TXD_MUX
+405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
+406 MX35_PAD_TCK__SJC_TCK
+407 MX35_PAD_TMS__SJC_TMS
+408 MX35_PAD_TDI__SJC_TDI
+409 MX35_PAD_TDO__SJC_TDO
+410 MX35_PAD_TRSTB__SJC_TRSTB
+411 MX35_PAD_DE_B__SJC_DE_B
+412 MX35_PAD_SJC_MOD__SJC_MOD
+413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
+414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
+415 MX35_PAD_USBOTG_PWR__GPIO3_14
+416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
+417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
+418 MX35_PAD_USBOTG_OC__GPIO3_15
+419 MX35_PAD_LD0__IPU_DISPB_DAT_0
+420 MX35_PAD_LD0__GPIO2_0
+421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
+422 MX35_PAD_LD1__IPU_DISPB_DAT_1
+423 MX35_PAD_LD1__GPIO2_1
+424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
+425 MX35_PAD_LD2__IPU_DISPB_DAT_2
+426 MX35_PAD_LD2__GPIO2_2
+427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
+428 MX35_PAD_LD3__IPU_DISPB_DAT_3
+429 MX35_PAD_LD3__GPIO2_3
+430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
+431 MX35_PAD_LD4__IPU_DISPB_DAT_4
+432 MX35_PAD_LD4__GPIO2_4
+433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
+434 MX35_PAD_LD5__IPU_DISPB_DAT_5
+435 MX35_PAD_LD5__GPIO2_5
+436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
+437 MX35_PAD_LD6__IPU_DISPB_DAT_6
+438 MX35_PAD_LD6__GPIO2_6
+439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
+440 MX35_PAD_LD7__IPU_DISPB_DAT_7
+441 MX35_PAD_LD7__GPIO2_7
+442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
+443 MX35_PAD_LD8__IPU_DISPB_DAT_8
+444 MX35_PAD_LD8__GPIO2_8
+445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
+446 MX35_PAD_LD9__IPU_DISPB_DAT_9
+447 MX35_PAD_LD9__GPIO2_9
+448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
+449 MX35_PAD_LD10__IPU_DISPB_DAT_10
+450 MX35_PAD_LD10__GPIO2_10
+451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
+452 MX35_PAD_LD11__IPU_DISPB_DAT_11
+453 MX35_PAD_LD11__GPIO2_11
+454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
+455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
+456 MX35_PAD_LD12__IPU_DISPB_DAT_12
+457 MX35_PAD_LD12__GPIO2_12
+458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
+459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
+460 MX35_PAD_LD13__IPU_DISPB_DAT_13
+461 MX35_PAD_LD13__GPIO2_13
+462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
+463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
+464 MX35_PAD_LD14__IPU_DISPB_DAT_14
+465 MX35_PAD_LD14__GPIO2_14
+466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
+467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
+468 MX35_PAD_LD15__IPU_DISPB_DAT_15
+469 MX35_PAD_LD15__GPIO2_15
+470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
+471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
+472 MX35_PAD_LD16__IPU_DISPB_DAT_16
+473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
+474 MX35_PAD_LD16__GPIO2_16
+475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
+476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
+477 MX35_PAD_LD17__IPU_DISPB_DAT_17
+478 MX35_PAD_LD17__IPU_DISPB_CS2
+479 MX35_PAD_LD17__GPIO2_17
+480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
+481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
+482 MX35_PAD_LD18__IPU_DISPB_DAT_18
+483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
+484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
+485 MX35_PAD_LD18__ESDHC3_CMD
+486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
+487 MX35_PAD_LD18__GPIO3_24
+488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
+489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
+490 MX35_PAD_LD19__IPU_DISPB_DAT_19
+491 MX35_PAD_LD19__IPU_DISPB_BCLK
+492 MX35_PAD_LD19__IPU_DISPB_CS1
+493 MX35_PAD_LD19__ESDHC3_CLK
+494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
+495 MX35_PAD_LD19__GPIO3_25
+496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
+497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
+498 MX35_PAD_LD20__IPU_DISPB_DAT_20
+499 MX35_PAD_LD20__IPU_DISPB_CS0
+500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
+501 MX35_PAD_LD20__ESDHC3_DAT0
+502 MX35_PAD_LD20__GPIO3_26
+503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
+504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
+505 MX35_PAD_LD21__IPU_DISPB_DAT_21
+506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
+507 MX35_PAD_LD21__IPU_DISPB_SER_RS
+508 MX35_PAD_LD21__ESDHC3_DAT1
+509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
+510 MX35_PAD_LD21__GPIO3_27
+511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
+512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
+513 MX35_PAD_LD22__IPU_DISPB_DAT_22
+514 MX35_PAD_LD22__IPU_DISPB_WR
+515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
+516 MX35_PAD_LD22__ESDHC3_DAT2
+517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
+518 MX35_PAD_LD22__GPIO3_28
+519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
+520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
+521 MX35_PAD_LD23__IPU_DISPB_DAT_23
+522 MX35_PAD_LD23__IPU_DISPB_RD
+523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
+524 MX35_PAD_LD23__ESDHC3_DAT3
+525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
+526 MX35_PAD_LD23__GPIO3_29
+527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
+528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
+529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
+530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
+531 MX35_PAD_D3_HSYNC__GPIO3_30
+532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
+533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
+534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
+535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
+536 MX35_PAD_D3_FPSHIFT__GPIO3_31
+537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
+538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
+539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
+540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
+541 MX35_PAD_D3_DRDY__GPIO1_0
+542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
+543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
+544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
+545 MX35_PAD_CONTRAST__GPIO1_1
+546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
+547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
+548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
+549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
+550 MX35_PAD_D3_VSYNC__GPIO1_2
+551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
+552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
+553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
+554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
+555 MX35_PAD_D3_REV__GPIO1_3
+556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
+557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
+558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
+559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
+560 MX35_PAD_D3_CLS__GPIO1_4
+561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
+562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
+563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
+565 MX35_PAD_D3_SPL__GPIO1_5
+566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
+567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
+568 MX35_PAD_SD1_CMD__ESDHC1_CMD
+569 MX35_PAD_SD1_CMD__MSHC_SCLK
+570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
+571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
+572 MX35_PAD_SD1_CMD__GPIO1_6
+573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
+574 MX35_PAD_SD1_CLK__ESDHC1_CLK
+575 MX35_PAD_SD1_CLK__MSHC_BS
+576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
+577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
+578 MX35_PAD_SD1_CLK__GPIO1_7
+579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
+580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
+581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
+582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
+583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
+584 MX35_PAD_SD1_DATA0__GPIO1_8
+585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
+586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
+587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
+588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
+589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
+590 MX35_PAD_SD1_DATA1__GPIO1_9
+591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
+592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
+593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
+594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
+595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
+596 MX35_PAD_SD1_DATA2__GPIO1_10
+597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
+598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
+599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
+600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
+601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
+602 MX35_PAD_SD1_DATA3__GPIO1_11
+603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
+604 MX35_PAD_SD2_CMD__ESDHC2_CMD
+605 MX35_PAD_SD2_CMD__I2C3_SCL
+606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
+607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
+608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
+609 MX35_PAD_SD2_CMD__GPIO2_0
+610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
+611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
+612 MX35_PAD_SD2_CLK__ESDHC2_CLK
+613 MX35_PAD_SD2_CLK__I2C3_SDA
+614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
+615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
+616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
+617 MX35_PAD_SD2_CLK__GPIO2_1
+618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
+619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
+620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
+621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
+622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
+623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
+624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
+625 MX35_PAD_SD2_DATA0__GPIO2_2
+626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
+627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
+628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
+629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
+630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
+631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
+632 MX35_PAD_SD2_DATA1__GPIO2_3
+633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
+634 MX35_PAD_SD2_DATA2__UART3_RTS
+635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
+636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
+637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
+638 MX35_PAD_SD2_DATA2__GPIO2_4
+639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
+640 MX35_PAD_SD2_DATA3__UART3_CTS
+641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
+642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
+643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
+644 MX35_PAD_SD2_DATA3__GPIO2_5
+645 MX35_PAD_ATA_CS0__ATA_CS0
+646 MX35_PAD_ATA_CS0__CSPI1_SS3
+647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
+648 MX35_PAD_ATA_CS0__GPIO2_6
+649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
+650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
+651 MX35_PAD_ATA_CS1__ATA_CS1
+652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
+653 MX35_PAD_ATA_CS1__CSPI2_SS0
+654 MX35_PAD_ATA_CS1__GPIO2_7
+655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
+656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
+657 MX35_PAD_ATA_DIOR__ATA_DIOR
+658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
+659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
+660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
+661 MX35_PAD_ATA_DIOR__CSPI2_SS1
+662 MX35_PAD_ATA_DIOR__GPIO2_8
+663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
+664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
+665 MX35_PAD_ATA_DIOW__ATA_DIOW
+666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
+667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
+668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
+669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
+670 MX35_PAD_ATA_DIOW__GPIO2_9
+671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
+672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
+673 MX35_PAD_ATA_DMACK__ATA_DMACK
+674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
+675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
+676 MX35_PAD_ATA_DMACK__CSPI2_MISO
+677 MX35_PAD_ATA_DMACK__GPIO2_10
+678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
+679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
+680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
+681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
+682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
+683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
+684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
+685 MX35_PAD_ATA_RESET_B__GPIO2_11
+686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
+687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
+688 MX35_PAD_ATA_IORDY__ATA_IORDY
+689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
+690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
+691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
+692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
+693 MX35_PAD_ATA_IORDY__GPIO2_12
+694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
+695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
+696 MX35_PAD_ATA_DATA0__ATA_DATA_0
+697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
+698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
+699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
+700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
+701 MX35_PAD_ATA_DATA0__GPIO2_13
+702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
+703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
+704 MX35_PAD_ATA_DATA1__ATA_DATA_1
+705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
+706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
+707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
+708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
+709 MX35_PAD_ATA_DATA1__GPIO2_14
+710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
+711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
+712 MX35_PAD_ATA_DATA2__ATA_DATA_2
+713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
+714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
+715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
+716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
+717 MX35_PAD_ATA_DATA2__GPIO2_15
+718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
+719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
+720 MX35_PAD_ATA_DATA3__ATA_DATA_3
+721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
+722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
+723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
+724 MX35_PAD_ATA_DATA3__GPIO2_16
+725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
+726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
+727 MX35_PAD_ATA_DATA4__ATA_DATA_4
+728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
+729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
+730 MX35_PAD_ATA_DATA4__GPIO2_17
+731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
+732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
+733 MX35_PAD_ATA_DATA5__ATA_DATA_5
+734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
+735 MX35_PAD_ATA_DATA5__GPIO2_18
+736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
+737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
+738 MX35_PAD_ATA_DATA6__ATA_DATA_6
+739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
+740 MX35_PAD_ATA_DATA6__UART1_DTR
+741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
+742 MX35_PAD_ATA_DATA6__GPIO2_19
+743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
+744 MX35_PAD_ATA_DATA7__ATA_DATA_7
+745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
+746 MX35_PAD_ATA_DATA7__UART1_DSR
+747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
+748 MX35_PAD_ATA_DATA7__GPIO2_20
+749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
+750 MX35_PAD_ATA_DATA8__ATA_DATA_8
+751 MX35_PAD_ATA_DATA8__UART3_RTS
+752 MX35_PAD_ATA_DATA8__UART1_RI
+753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
+754 MX35_PAD_ATA_DATA8__GPIO2_21
+755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
+756 MX35_PAD_ATA_DATA9__ATA_DATA_9
+757 MX35_PAD_ATA_DATA9__UART3_CTS
+758 MX35_PAD_ATA_DATA9__UART1_DCD
+759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
+760 MX35_PAD_ATA_DATA9__GPIO2_22
+761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
+762 MX35_PAD_ATA_DATA10__ATA_DATA_10
+763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
+764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
+765 MX35_PAD_ATA_DATA10__GPIO2_23
+766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
+767 MX35_PAD_ATA_DATA11__ATA_DATA_11
+768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
+769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
+770 MX35_PAD_ATA_DATA11__GPIO2_24
+771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
+772 MX35_PAD_ATA_DATA12__ATA_DATA_12
+773 MX35_PAD_ATA_DATA12__I2C3_SCL
+774 MX35_PAD_ATA_DATA12__GPIO2_25
+775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
+776 MX35_PAD_ATA_DATA13__ATA_DATA_13
+777 MX35_PAD_ATA_DATA13__I2C3_SDA
+778 MX35_PAD_ATA_DATA13__GPIO2_26
+779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
+780 MX35_PAD_ATA_DATA14__ATA_DATA_14
+781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
+782 MX35_PAD_ATA_DATA14__KPP_ROW_0
+783 MX35_PAD_ATA_DATA14__GPIO2_27
+784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
+785 MX35_PAD_ATA_DATA15__ATA_DATA_15
+786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
+787 MX35_PAD_ATA_DATA15__KPP_ROW_1
+788 MX35_PAD_ATA_DATA15__GPIO2_28
+789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
+790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
+791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
+792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
+793 MX35_PAD_ATA_INTRQ__GPIO2_29
+794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
+795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
+796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
+797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
+798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
+799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
+800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
+801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
+802 MX35_PAD_ATA_DMARQ__KPP_COL_0
+803 MX35_PAD_ATA_DMARQ__GPIO2_31
+804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
+805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
+806 MX35_PAD_ATA_DA0__ATA_DA_0
+807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
+808 MX35_PAD_ATA_DA0__KPP_COL_1
+809 MX35_PAD_ATA_DA0__GPIO3_0
+810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
+811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
+812 MX35_PAD_ATA_DA1__ATA_DA_1
+813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
+814 MX35_PAD_ATA_DA1__KPP_COL_2
+815 MX35_PAD_ATA_DA1__GPIO3_1
+816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
+817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
+818 MX35_PAD_ATA_DA2__ATA_DA_2
+819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
+820 MX35_PAD_ATA_DA2__KPP_COL_3
+821 MX35_PAD_ATA_DA2__GPIO3_2
+822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
+823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
+824 MX35_PAD_MLB_CLK__MLB_MLBCLK
+825 MX35_PAD_MLB_CLK__GPIO3_3
+826 MX35_PAD_MLB_DAT__MLB_MLBDAT
+827 MX35_PAD_MLB_DAT__GPIO3_4
+828 MX35_PAD_MLB_SIG__MLB_MLBSIG
+829 MX35_PAD_MLB_SIG__GPIO3_5
+830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
+831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
+832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
+833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
+834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
+835 MX35_PAD_FEC_TX_CLK__GPIO3_6
+836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
+837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
+838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
+839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
+840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
+841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
+842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
+843 MX35_PAD_FEC_RX_CLK__GPIO3_7
+844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
+845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
+846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
+847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
+848 MX35_PAD_FEC_RX_DV__UART3_RTS
+849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
+850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
+851 MX35_PAD_FEC_RX_DV__GPIO3_8
+852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
+853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
+854 MX35_PAD_FEC_COL__FEC_COL
+855 MX35_PAD_FEC_COL__ESDHC1_DAT7
+856 MX35_PAD_FEC_COL__UART3_CTS
+857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
+858 MX35_PAD_FEC_COL__CSPI2_RDY
+859 MX35_PAD_FEC_COL__GPIO3_9
+860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
+861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
+862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
+863 MX35_PAD_FEC_RDATA0__PWM_PWMO
+864 MX35_PAD_FEC_RDATA0__UART3_DTR
+865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
+866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
+867 MX35_PAD_FEC_RDATA0__GPIO3_10
+868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
+869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
+870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
+871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
+872 MX35_PAD_FEC_TDATA0__UART3_DSR
+873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
+874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
+875 MX35_PAD_FEC_TDATA0__GPIO3_11
+876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
+877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
+878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
+879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
+880 MX35_PAD_FEC_TX_EN__UART3_RI
+881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
+882 MX35_PAD_FEC_TX_EN__GPIO3_12
+883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
+884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
+885 MX35_PAD_FEC_MDC__FEC_MDC
+886 MX35_PAD_FEC_MDC__CAN2_TXCAN
+887 MX35_PAD_FEC_MDC__UART3_DCD
+888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
+889 MX35_PAD_FEC_MDC__GPIO3_13
+890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
+891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
+892 MX35_PAD_FEC_MDIO__FEC_MDIO
+893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
+894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
+895 MX35_PAD_FEC_MDIO__GPIO3_14
+896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
+897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
+898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
+899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
+900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
+901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
+902 MX35_PAD_FEC_TX_ERR__GPIO3_15
+903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
+904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
+905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
+906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
+907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
+908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
+909 MX35_PAD_FEC_RX_ERR__GPIO3_16
+910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
+911 MX35_PAD_FEC_CRS__FEC_CRS
+912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
+913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
+914 MX35_PAD_FEC_CRS__KPP_COL_5
+915 MX35_PAD_FEC_CRS__GPIO3_17
+916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
+917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
+918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
+919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
+920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
+921 MX35_PAD_FEC_RDATA1__KPP_COL_6
+922 MX35_PAD_FEC_RDATA1__GPIO3_18
+923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
+924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
+925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
+926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
+927 MX35_PAD_FEC_TDATA1__KPP_COL_7
+928 MX35_PAD_FEC_TDATA1__GPIO3_19
+929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
+930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
+931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
+932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
+933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
+934 MX35_PAD_FEC_RDATA2__GPIO3_20
+935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
+936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
+937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
+938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
+939 MX35_PAD_FEC_TDATA2__GPIO3_21
+940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
+941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
+942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
+943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
+944 MX35_PAD_FEC_RDATA3__GPIO3_22
+945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
+946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
+947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
+948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
+949 MX35_PAD_FEC_TDATA3__GPIO3_23
+950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
+951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6e6ae0..350cc9b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_IMX
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_IMX35
+	bool "IMX35 pinctrl driver"
+	depends on OF
+	depends on SOC_IMX35
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx35 pinctrl driver
+
 config PINCTRL_IMX51
 	bool "IMX51 pinctrl driver"
 	depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 8c07437..8e1020d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL)		+= devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
 obj-$(CONFIG_PINCTRL_IMX)	+= pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX35)	+= pinctrl-imx35.o
 obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6q.o
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
new file mode 100644
index 0000000..9bf3139
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -0,0 +1,1598 @@
+/*
+ * imx35 pinctrl driver.
+ *
+ * This driver was mostly copied from the imx51 pinctrl driver which has:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx35_pads {
+	/* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tMX35_PAD_\1, at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
+	MX35_PAD_CAPTURE,
+	MX35_PAD_COMPARE,
+	MX35_PAD_WDOG_RST,
+	MX35_PAD_GPIO1_0,
+	MX35_PAD_GPIO1_1,
+	MX35_PAD_GPIO2_0,
+	MX35_PAD_GPIO3_0,
+	MX35_PAD_RESET_IN_B,
+	MX35_PAD_POR_B,
+	MX35_PAD_CLKO,
+	MX35_PAD_BOOT_MODE0,
+	MX35_PAD_BOOT_MODE1,
+	MX35_PAD_CLK_MODE0,
+	MX35_PAD_CLK_MODE1,
+	MX35_PAD_POWER_FAIL,
+	MX35_PAD_VSTBY,
+	MX35_PAD_A0,
+	MX35_PAD_A1,
+	MX35_PAD_A2,
+	MX35_PAD_A3,
+	MX35_PAD_A4,
+	MX35_PAD_A5,
+	MX35_PAD_A6,
+	MX35_PAD_A7,
+	MX35_PAD_A8,
+	MX35_PAD_A9,
+	MX35_PAD_A10,
+	MX35_PAD_MA10,
+	MX35_PAD_A11,
+	MX35_PAD_A12,
+	MX35_PAD_A13,
+	MX35_PAD_A14,
+	MX35_PAD_A15,
+	MX35_PAD_A16,
+	MX35_PAD_A17,
+	MX35_PAD_A18,
+	MX35_PAD_A19,
+	MX35_PAD_A20,
+	MX35_PAD_A21,
+	MX35_PAD_A22,
+	MX35_PAD_A23,
+	MX35_PAD_A24,
+	MX35_PAD_A25,
+	MX35_PAD_SDBA1,
+	MX35_PAD_SDBA0,
+	MX35_PAD_SD0,
+	MX35_PAD_SD1,
+	MX35_PAD_SD2,
+	MX35_PAD_SD3,
+	MX35_PAD_SD4,
+	MX35_PAD_SD5,
+	MX35_PAD_SD6,
+	MX35_PAD_SD7,
+	MX35_PAD_SD8,
+	MX35_PAD_SD9,
+	MX35_PAD_SD10,
+	MX35_PAD_SD11,
+	MX35_PAD_SD12,
+	MX35_PAD_SD13,
+	MX35_PAD_SD14,
+	MX35_PAD_SD15,
+	MX35_PAD_SD16,
+	MX35_PAD_SD17,
+	MX35_PAD_SD18,
+	MX35_PAD_SD19,
+	MX35_PAD_SD20,
+	MX35_PAD_SD21,
+	MX35_PAD_SD22,
+	MX35_PAD_SD23,
+	MX35_PAD_SD24,
+	MX35_PAD_SD25,
+	MX35_PAD_SD26,
+	MX35_PAD_SD27,
+	MX35_PAD_SD28,
+	MX35_PAD_SD29,
+	MX35_PAD_SD30,
+	MX35_PAD_SD31,
+	MX35_PAD_DQM0,
+	MX35_PAD_DQM1,
+	MX35_PAD_DQM2,
+	MX35_PAD_DQM3,
+	MX35_PAD_EB0,
+	MX35_PAD_EB1,
+	MX35_PAD_OE,
+	MX35_PAD_CS0,
+	MX35_PAD_CS1,
+	MX35_PAD_CS2,
+	MX35_PAD_CS3,
+	MX35_PAD_CS4,
+	MX35_PAD_CS5,
+	MX35_PAD_NF_CE0,
+	MX35_PAD_ECB,
+	MX35_PAD_LBA,
+	MX35_PAD_BCLK,
+	MX35_PAD_RW,
+	MX35_PAD_RAS,
+	MX35_PAD_CAS,
+	MX35_PAD_SDWE,
+	MX35_PAD_SDCKE0,
+	MX35_PAD_SDCKE1,
+	MX35_PAD_SDCLK,
+	MX35_PAD_SDQS0,
+	MX35_PAD_SDQS1,
+	MX35_PAD_SDQS2,
+	MX35_PAD_SDQS3,
+	MX35_PAD_NFWE_B,
+	MX35_PAD_NFRE_B,
+	MX35_PAD_NFALE,
+	MX35_PAD_NFCLE,
+	MX35_PAD_NFWP_B,
+	MX35_PAD_NFRB,
+	MX35_PAD_D15,
+	MX35_PAD_D14,
+	MX35_PAD_D13,
+	MX35_PAD_D12,
+	MX35_PAD_D11,
+	MX35_PAD_D10,
+	MX35_PAD_D9,
+	MX35_PAD_D8,
+	MX35_PAD_D7,
+	MX35_PAD_D6,
+	MX35_PAD_D5,
+	MX35_PAD_D4,
+	MX35_PAD_D3,
+	MX35_PAD_D2,
+	MX35_PAD_D1,
+	MX35_PAD_D0,
+	MX35_PAD_CSI_D8,
+	MX35_PAD_CSI_D9,
+	MX35_PAD_CSI_D10,
+	MX35_PAD_CSI_D11,
+	MX35_PAD_CSI_D12,
+	MX35_PAD_CSI_D13,
+	MX35_PAD_CSI_D14,
+	MX35_PAD_CSI_D15,
+	MX35_PAD_CSI_MCLK,
+	MX35_PAD_CSI_VSYNC,
+	MX35_PAD_CSI_HSYNC,
+	MX35_PAD_CSI_PIXCLK,
+	MX35_PAD_I2C1_CLK,
+	MX35_PAD_I2C1_DAT,
+	MX35_PAD_I2C2_CLK,
+	MX35_PAD_I2C2_DAT,
+	MX35_PAD_STXD4,
+	MX35_PAD_SRXD4,
+	MX35_PAD_SCK4,
+	MX35_PAD_STXFS4,
+	MX35_PAD_STXD5,
+	MX35_PAD_SRXD5,
+	MX35_PAD_SCK5,
+	MX35_PAD_STXFS5,
+	MX35_PAD_SCKR,
+	MX35_PAD_FSR,
+	MX35_PAD_HCKR,
+	MX35_PAD_SCKT,
+	MX35_PAD_FST,
+	MX35_PAD_HCKT,
+	MX35_PAD_TX5_RX0,
+	MX35_PAD_TX4_RX1,
+	MX35_PAD_TX3_RX2,
+	MX35_PAD_TX2_RX3,
+	MX35_PAD_TX1,
+	MX35_PAD_TX0,
+	MX35_PAD_CSPI1_MOSI,
+	MX35_PAD_CSPI1_MISO,
+	MX35_PAD_CSPI1_SS0,
+	MX35_PAD_CSPI1_SS1,
+	MX35_PAD_CSPI1_SCLK,
+	MX35_PAD_CSPI1_SPI_RDY,
+	MX35_PAD_RXD1,
+	MX35_PAD_TXD1,
+	MX35_PAD_RTS1,
+	MX35_PAD_CTS1,
+	MX35_PAD_RXD2,
+	MX35_PAD_TXD2,
+	MX35_PAD_RTS2,
+	MX35_PAD_CTS2,
+	MX35_PAD_RTCK,
+	MX35_PAD_TCK,
+	MX35_PAD_TMS,
+	MX35_PAD_TDI,
+	MX35_PAD_TDO,
+	MX35_PAD_TRSTB,
+	MX35_PAD_DE_B,
+	MX35_PAD_SJC_MOD,
+	MX35_PAD_USBOTG_PWR,
+	MX35_PAD_USBOTG_OC,
+	MX35_PAD_LD0,
+	MX35_PAD_LD1,
+	MX35_PAD_LD2,
+	MX35_PAD_LD3,
+	MX35_PAD_LD4,
+	MX35_PAD_LD5,
+	MX35_PAD_LD6,
+	MX35_PAD_LD7,
+	MX35_PAD_LD8,
+	MX35_PAD_LD9,
+	MX35_PAD_LD10,
+	MX35_PAD_LD11,
+	MX35_PAD_LD12,
+	MX35_PAD_LD13,
+	MX35_PAD_LD14,
+	MX35_PAD_LD15,
+	MX35_PAD_LD16,
+	MX35_PAD_LD17,
+	MX35_PAD_LD18,
+	MX35_PAD_LD19,
+	MX35_PAD_LD20,
+	MX35_PAD_LD21,
+	MX35_PAD_LD22,
+	MX35_PAD_LD23,
+	MX35_PAD_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT,
+	MX35_PAD_D3_DRDY,
+	MX35_PAD_CONTRAST,
+	MX35_PAD_D3_VSYNC,
+	MX35_PAD_D3_REV,
+	MX35_PAD_D3_CLS,
+	MX35_PAD_D3_SPL,
+	MX35_PAD_SD1_CMD,
+	MX35_PAD_SD1_CLK,
+	MX35_PAD_SD1_DATA0,
+	MX35_PAD_SD1_DATA1,
+	MX35_PAD_SD1_DATA2,
+	MX35_PAD_SD1_DATA3,
+	MX35_PAD_SD2_CMD,
+	MX35_PAD_SD2_CLK,
+	MX35_PAD_SD2_DATA0,
+	MX35_PAD_SD2_DATA1,
+	MX35_PAD_SD2_DATA2,
+	MX35_PAD_SD2_DATA3,
+	MX35_PAD_ATA_CS0,
+	MX35_PAD_ATA_CS1,
+	MX35_PAD_ATA_DIOR,
+	MX35_PAD_ATA_DIOW,
+	MX35_PAD_ATA_DMACK,
+	MX35_PAD_ATA_RESET_B,
+	MX35_PAD_ATA_IORDY,
+	MX35_PAD_ATA_DATA0,
+	MX35_PAD_ATA_DATA1,
+	MX35_PAD_ATA_DATA2,
+	MX35_PAD_ATA_DATA3,
+	MX35_PAD_ATA_DATA4,
+	MX35_PAD_ATA_DATA5,
+	MX35_PAD_ATA_DATA6,
+	MX35_PAD_ATA_DATA7,
+	MX35_PAD_ATA_DATA8,
+	MX35_PAD_ATA_DATA9,
+	MX35_PAD_ATA_DATA10,
+	MX35_PAD_ATA_DATA11,
+	MX35_PAD_ATA_DATA12,
+	MX35_PAD_ATA_DATA13,
+	MX35_PAD_ATA_DATA14,
+	MX35_PAD_ATA_DATA15,
+	MX35_PAD_ATA_INTRQ,
+	MX35_PAD_ATA_BUFF_EN,
+	MX35_PAD_ATA_DMARQ,
+	MX35_PAD_ATA_DA0,
+	MX35_PAD_ATA_DA1,
+	MX35_PAD_ATA_DA2,
+	MX35_PAD_MLB_CLK,
+	MX35_PAD_MLB_DAT,
+	MX35_PAD_MLB_SIG,
+	MX35_PAD_FEC_TX_CLK,
+	MX35_PAD_FEC_RX_CLK,
+	MX35_PAD_FEC_RX_DV,
+	MX35_PAD_FEC_COL,
+	MX35_PAD_FEC_RDATA0,
+	MX35_PAD_FEC_TDATA0,
+	MX35_PAD_FEC_TX_EN,
+	MX35_PAD_FEC_MDC,
+	MX35_PAD_FEC_MDIO,
+	MX35_PAD_FEC_TX_ERR,
+	MX35_PAD_FEC_RX_ERR,
+	MX35_PAD_FEC_CRS,
+	MX35_PAD_FEC_RDATA1,
+	MX35_PAD_FEC_TDATA1,
+	MX35_PAD_FEC_RDATA2,
+	MX35_PAD_FEC_TDATA2,
+	MX35_PAD_FEC_RDATA3,
+	MX35_PAD_FEC_TDATA3,
+	MX35_PAD_EXT_ARMCLK,
+	MX35_PAD_TEST_MODE,
+};
+
+/* imx35 register maps */
+static struct imx_pin_reg imx35_pin_regs[] = {
+	/* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tIMX_PIN_REG(MX35_PAD_\1, \3, \4, \5, \6, \7), /\* MX35_PAD_\1__\2 *\/@p' arch/arm/plat-mxc/include/mach/iomux-mx35.h */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */
+	IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */
+	IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */
+	IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */
+	IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */
+	IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */
+	IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */
+	IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */
+	IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */
+	IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */
+	IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */
+	IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */
+	IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */
+	IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */
+	IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */
+	IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */
+	IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */
+	IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */
+	IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */
+	IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */
+	IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */
+	IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */
+	IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */
+	IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */
+	IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */
+	IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */
+	IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */
+	IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */
+	IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */
+	IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */
+	IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */
+	IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */
+	IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */
+	IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */
+	IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */
+	IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */
+	IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */
+	IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */
+	IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */
+	IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */
+	IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */
+	IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */
+	IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */
+	IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */
+	IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */
+	IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */
+	IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */
+	IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */
+	IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */
+	IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */
+	IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */
+	IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */
+	IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */
+	IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */
+	IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */
+	IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */
+	IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */
+	IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */
+	IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */
+	IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */
+	IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */
+	IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */
+	IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */
+	IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */
+	IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */
+	IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */
+	IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */
+	IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */
+	IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */
+	IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */
+	IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */
+	IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */
+	IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */
+	IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */
+	IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */
+	IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */
+	IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */
+	IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */
+	IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */
+	IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */
+	IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */
+	IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */
+	IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */
+	IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */
+	IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */
+	IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */
+	IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */
+	IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */
+	IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */
+	IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */
+	IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */
+	IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */
+	IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */
+	IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */
+	IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */
+	IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */
+	IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */
+	IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */
+	IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */
+	IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */
+	IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */
+	IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */
+	IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */
+	IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */
+	IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */
+	IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */
+	IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */
+	IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */
+	IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */
+	IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */
+	IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */
+	IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */
+	IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */
+	IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */
+	IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */
+	IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */
+	IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */
+	IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */
+	IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */
+	IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */
+	IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */
+	IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */
+	IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */
+	IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */
+	IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */
+	IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */
+	IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */
+	IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */
+	IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */
+	IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */
+	IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */
+	IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */
+	IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */
+	IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */
+	IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */
+	IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */
+	IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */
+	IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */
+	IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */
+	IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */
+	IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */
+	IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */
+	IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */
+	IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */
+	IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */
+	IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */
+	IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */
+	IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */
+	IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */
+	IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */
+	IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */
+	IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */
+	IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */
+	IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */
+	IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */
+	IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */
+	IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */
+	IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */
+	IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */
+	IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */
+	IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */
+	IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */
+	IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */
+	IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */
+	IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */
+	IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */
+	IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */
+	IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */
+	IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */
+	IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */
+	IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */
+	IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */
+	IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */
+	IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */
+	IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */
+	IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */
+	IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */
+	IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */
+	IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */
+	IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */
+	IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */
+	IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */
+	IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */
+	IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */
+	IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */
+	IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */
+	IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */
+	IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */
+	IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */
+	IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */
+	IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */
+	IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */
+	IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */
+	IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */
+	IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */
+	IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */
+	IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */
+	IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */
+	IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */
+	IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */
+	IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */
+	IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */
+	IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */
+	IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */
+	IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */
+	IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */
+	IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */
+	IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */
+	IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */
+	IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */
+	IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */
+	IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */
+	IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */
+	IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
+	IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */
+	IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */
+	IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */
+	IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */
+	IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
+	IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */
+	IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */
+	IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */
+	IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */
+	IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */
+	IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */
+	IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */
+	IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */
+	IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */
+	IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */
+	IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */
+	IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */
+	IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */
+	IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */
+	IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */
+	IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */
+	IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */
+	IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */
+	IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */
+	IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */
+	IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */
+	IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */
+	IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */
+	IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */
+	IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */
+	IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */
+	IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */
+	IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */
+	IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */
+	IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */
+	IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */
+	IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */
+	IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */
+	IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */
+	IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */
+	IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */
+	IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */
+	IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */
+	IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */
+	IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */
+	IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */
+	IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */
+	IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */
+	IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */
+	IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */
+	IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */
+	IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */
+	IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */
+	IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */
+	IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */
+	IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */
+	IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */
+	IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */
+	IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */
+	IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */
+	IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */
+	IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */
+	IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */
+	IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */
+	IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */
+	IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */
+	IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */
+	IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */
+	IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */
+	IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */
+	IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */
+	IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */
+	IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */
+	IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */
+	IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */
+	IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */
+	IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */
+	IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */
+	IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */
+	IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */
+	IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */
+	IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */
+	IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */
+	IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */
+	IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */
+	IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */
+	IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */
+	IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */
+	IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */
+	IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */
+	IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */
+	IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */
+	IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */
+	IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */
+	IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */
+	IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */
+	IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */
+	IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */
+	IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */
+	IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */
+	IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */
+	IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */
+	IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */
+	IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */
+	IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */
+	IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */
+	IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */
+	IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */
+	IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */
+	IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */
+	IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */
+	IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */
+	IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */
+	IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */
+	IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */
+	IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */
+	IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */
+	IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */
+	IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */
+	IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */
+	IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */
+	IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */
+	IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */
+	IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */
+	IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */
+	IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */
+	IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */
+	IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */
+	IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */
+	IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */
+	IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */
+	IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */
+	IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */
+	IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */
+	IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */
+	IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */
+	IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */
+	IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */
+	IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */
+	IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */
+	IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */
+	IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */
+	IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */
+	IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */
+	IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */
+	IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */
+	IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */
+	IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */
+	IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */
+	IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */
+	IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */
+	IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */
+	IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */
+	IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */
+	IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */
+	IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */
+	IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */
+	IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */
+	IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */
+	IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */
+	IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */
+	IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */
+	IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */
+	IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */
+	IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */
+	IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */
+	IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */
+	IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */
+	IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */
+	IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */
+	IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */
+	IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */
+	IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */
+	IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */
+	IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */
+	IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */
+	IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */
+	IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */
+	IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */
+	IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */
+	IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */
+	IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */
+	IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */
+	IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */
+	IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */
+	IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */
+	IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */
+	IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */
+	IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */
+	IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */
+	IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */
+	IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */
+	IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */
+	IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */
+	IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */
+	IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */
+	IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */
+	IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */
+	IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */
+	IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */
+	IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */
+	IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */
+	IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */
+	IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */
+	IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */
+	IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */
+	IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */
+	IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */
+	IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */
+	IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */
+	IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */
+	IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */
+	IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */
+	IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */
+	IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */
+	IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */
+	IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */
+	IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */
+	IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */
+	IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */
+	IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */
+	IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */
+	IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */
+	IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */
+	IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */
+	IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */
+	IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */
+	IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */
+	IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */
+	IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */
+	IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */
+	IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
+	/* sed -r -n 's@^#define MX35_PAD_([0-9A-Z_]*)__([0-9A-Z_]*)\s+IOMUX_PAD\(\s*([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9a-fx]*),\s+([0-9]*),\s*NO_PAD_CTRL\)@\tIMX_PINCTRL_PIN(MX35_PAD_\1), at p' arch/arm/plat-mxc/include/mach/iomux-mx35.h | uniq */
+	IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
+	IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
+	IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
+	IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
+	IMX_PINCTRL_PIN(MX35_PAD_POR_B),
+	IMX_PINCTRL_PIN(MX35_PAD_CLKO),
+	IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
+	IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
+	IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
+	IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
+	IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
+	IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
+	IMX_PINCTRL_PIN(MX35_PAD_A0),
+	IMX_PINCTRL_PIN(MX35_PAD_A1),
+	IMX_PINCTRL_PIN(MX35_PAD_A2),
+	IMX_PINCTRL_PIN(MX35_PAD_A3),
+	IMX_PINCTRL_PIN(MX35_PAD_A4),
+	IMX_PINCTRL_PIN(MX35_PAD_A5),
+	IMX_PINCTRL_PIN(MX35_PAD_A6),
+	IMX_PINCTRL_PIN(MX35_PAD_A7),
+	IMX_PINCTRL_PIN(MX35_PAD_A8),
+	IMX_PINCTRL_PIN(MX35_PAD_A9),
+	IMX_PINCTRL_PIN(MX35_PAD_A10),
+	IMX_PINCTRL_PIN(MX35_PAD_MA10),
+	IMX_PINCTRL_PIN(MX35_PAD_A11),
+	IMX_PINCTRL_PIN(MX35_PAD_A12),
+	IMX_PINCTRL_PIN(MX35_PAD_A13),
+	IMX_PINCTRL_PIN(MX35_PAD_A14),
+	IMX_PINCTRL_PIN(MX35_PAD_A15),
+	IMX_PINCTRL_PIN(MX35_PAD_A16),
+	IMX_PINCTRL_PIN(MX35_PAD_A17),
+	IMX_PINCTRL_PIN(MX35_PAD_A18),
+	IMX_PINCTRL_PIN(MX35_PAD_A19),
+	IMX_PINCTRL_PIN(MX35_PAD_A20),
+	IMX_PINCTRL_PIN(MX35_PAD_A21),
+	IMX_PINCTRL_PIN(MX35_PAD_A22),
+	IMX_PINCTRL_PIN(MX35_PAD_A23),
+	IMX_PINCTRL_PIN(MX35_PAD_A24),
+	IMX_PINCTRL_PIN(MX35_PAD_A25),
+	IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD3),
+	IMX_PINCTRL_PIN(MX35_PAD_SD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SD6),
+	IMX_PINCTRL_PIN(MX35_PAD_SD7),
+	IMX_PINCTRL_PIN(MX35_PAD_SD8),
+	IMX_PINCTRL_PIN(MX35_PAD_SD9),
+	IMX_PINCTRL_PIN(MX35_PAD_SD10),
+	IMX_PINCTRL_PIN(MX35_PAD_SD11),
+	IMX_PINCTRL_PIN(MX35_PAD_SD12),
+	IMX_PINCTRL_PIN(MX35_PAD_SD13),
+	IMX_PINCTRL_PIN(MX35_PAD_SD14),
+	IMX_PINCTRL_PIN(MX35_PAD_SD15),
+	IMX_PINCTRL_PIN(MX35_PAD_SD16),
+	IMX_PINCTRL_PIN(MX35_PAD_SD17),
+	IMX_PINCTRL_PIN(MX35_PAD_SD18),
+	IMX_PINCTRL_PIN(MX35_PAD_SD19),
+	IMX_PINCTRL_PIN(MX35_PAD_SD20),
+	IMX_PINCTRL_PIN(MX35_PAD_SD21),
+	IMX_PINCTRL_PIN(MX35_PAD_SD22),
+	IMX_PINCTRL_PIN(MX35_PAD_SD23),
+	IMX_PINCTRL_PIN(MX35_PAD_SD24),
+	IMX_PINCTRL_PIN(MX35_PAD_SD25),
+	IMX_PINCTRL_PIN(MX35_PAD_SD26),
+	IMX_PINCTRL_PIN(MX35_PAD_SD27),
+	IMX_PINCTRL_PIN(MX35_PAD_SD28),
+	IMX_PINCTRL_PIN(MX35_PAD_SD29),
+	IMX_PINCTRL_PIN(MX35_PAD_SD30),
+	IMX_PINCTRL_PIN(MX35_PAD_SD31),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM0),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM1),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM2),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM3),
+	IMX_PINCTRL_PIN(MX35_PAD_EB0),
+	IMX_PINCTRL_PIN(MX35_PAD_EB1),
+	IMX_PINCTRL_PIN(MX35_PAD_OE),
+	IMX_PINCTRL_PIN(MX35_PAD_CS0),
+	IMX_PINCTRL_PIN(MX35_PAD_CS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CS2),
+	IMX_PINCTRL_PIN(MX35_PAD_CS3),
+	IMX_PINCTRL_PIN(MX35_PAD_CS4),
+	IMX_PINCTRL_PIN(MX35_PAD_CS5),
+	IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
+	IMX_PINCTRL_PIN(MX35_PAD_ECB),
+	IMX_PINCTRL_PIN(MX35_PAD_LBA),
+	IMX_PINCTRL_PIN(MX35_PAD_BCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_RW),
+	IMX_PINCTRL_PIN(MX35_PAD_RAS),
+	IMX_PINCTRL_PIN(MX35_PAD_CAS),
+	IMX_PINCTRL_PIN(MX35_PAD_SDWE),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
+	IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFALE),
+	IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
+	IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFRB),
+	IMX_PINCTRL_PIN(MX35_PAD_D15),
+	IMX_PINCTRL_PIN(MX35_PAD_D14),
+	IMX_PINCTRL_PIN(MX35_PAD_D13),
+	IMX_PINCTRL_PIN(MX35_PAD_D12),
+	IMX_PINCTRL_PIN(MX35_PAD_D11),
+	IMX_PINCTRL_PIN(MX35_PAD_D10),
+	IMX_PINCTRL_PIN(MX35_PAD_D9),
+	IMX_PINCTRL_PIN(MX35_PAD_D8),
+	IMX_PINCTRL_PIN(MX35_PAD_D7),
+	IMX_PINCTRL_PIN(MX35_PAD_D6),
+	IMX_PINCTRL_PIN(MX35_PAD_D5),
+	IMX_PINCTRL_PIN(MX35_PAD_D4),
+	IMX_PINCTRL_PIN(MX35_PAD_D3),
+	IMX_PINCTRL_PIN(MX35_PAD_D2),
+	IMX_PINCTRL_PIN(MX35_PAD_D1),
+	IMX_PINCTRL_PIN(MX35_PAD_D0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_STXD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SCK4),
+	IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
+	IMX_PINCTRL_PIN(MX35_PAD_STXD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SCK5),
+	IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
+	IMX_PINCTRL_PIN(MX35_PAD_SCKR),
+	IMX_PINCTRL_PIN(MX35_PAD_FSR),
+	IMX_PINCTRL_PIN(MX35_PAD_HCKR),
+	IMX_PINCTRL_PIN(MX35_PAD_SCKT),
+	IMX_PINCTRL_PIN(MX35_PAD_FST),
+	IMX_PINCTRL_PIN(MX35_PAD_HCKT),
+	IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
+	IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
+	IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
+	IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
+	IMX_PINCTRL_PIN(MX35_PAD_TX1),
+	IMX_PINCTRL_PIN(MX35_PAD_TX0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
+	IMX_PINCTRL_PIN(MX35_PAD_RXD1),
+	IMX_PINCTRL_PIN(MX35_PAD_TXD1),
+	IMX_PINCTRL_PIN(MX35_PAD_RTS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CTS1),
+	IMX_PINCTRL_PIN(MX35_PAD_RXD2),
+	IMX_PINCTRL_PIN(MX35_PAD_TXD2),
+	IMX_PINCTRL_PIN(MX35_PAD_RTS2),
+	IMX_PINCTRL_PIN(MX35_PAD_CTS2),
+	IMX_PINCTRL_PIN(MX35_PAD_RTCK),
+	IMX_PINCTRL_PIN(MX35_PAD_TCK),
+	IMX_PINCTRL_PIN(MX35_PAD_TMS),
+	IMX_PINCTRL_PIN(MX35_PAD_TDI),
+	IMX_PINCTRL_PIN(MX35_PAD_TDO),
+	IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
+	IMX_PINCTRL_PIN(MX35_PAD_DE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
+	IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
+	IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
+	IMX_PINCTRL_PIN(MX35_PAD_LD0),
+	IMX_PINCTRL_PIN(MX35_PAD_LD1),
+	IMX_PINCTRL_PIN(MX35_PAD_LD2),
+	IMX_PINCTRL_PIN(MX35_PAD_LD3),
+	IMX_PINCTRL_PIN(MX35_PAD_LD4),
+	IMX_PINCTRL_PIN(MX35_PAD_LD5),
+	IMX_PINCTRL_PIN(MX35_PAD_LD6),
+	IMX_PINCTRL_PIN(MX35_PAD_LD7),
+	IMX_PINCTRL_PIN(MX35_PAD_LD8),
+	IMX_PINCTRL_PIN(MX35_PAD_LD9),
+	IMX_PINCTRL_PIN(MX35_PAD_LD10),
+	IMX_PINCTRL_PIN(MX35_PAD_LD11),
+	IMX_PINCTRL_PIN(MX35_PAD_LD12),
+	IMX_PINCTRL_PIN(MX35_PAD_LD13),
+	IMX_PINCTRL_PIN(MX35_PAD_LD14),
+	IMX_PINCTRL_PIN(MX35_PAD_LD15),
+	IMX_PINCTRL_PIN(MX35_PAD_LD16),
+	IMX_PINCTRL_PIN(MX35_PAD_LD17),
+	IMX_PINCTRL_PIN(MX35_PAD_LD18),
+	IMX_PINCTRL_PIN(MX35_PAD_LD19),
+	IMX_PINCTRL_PIN(MX35_PAD_LD20),
+	IMX_PINCTRL_PIN(MX35_PAD_LD21),
+	IMX_PINCTRL_PIN(MX35_PAD_LD22),
+	IMX_PINCTRL_PIN(MX35_PAD_LD23),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
+	IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
+};
+
+static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+	.pins = imx35_pinctrl_pads,
+	.npins = ARRAY_SIZE(imx35_pinctrl_pads),
+	.pin_regs = imx35_pin_regs,
+	.npin_regs = ARRAY_SIZE(imx35_pin_regs),
+};
+
+static struct of_device_id imx35_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "fsl,imx35-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int __devinit imx35_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
+}
+
+static struct platform_driver imx35_pinctrl_driver = {
+	.driver = {
+		.name = "imx35-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(imx35_pinctrl_of_match),
+	},
+	.probe = imx35_pinctrl_probe,
+	.remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx35_pinctrl_init(void)
+{
+	return platform_driver_register(&imx35_pinctrl_driver);
+}
+arch_initcall(imx35_pinctrl_init);
+
+static void __exit imx35_pinctrl_exit(void)
+{
+	platform_driver_unregister(&imx35_pinctrl_driver);
+}
+module_exit(imx35_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From luffy.sun at ymail.com  Thu Aug  2 21:51:37 2012
From: luffy.sun at ymail.com (Luffy Sun)
Date: Fri, 03 Aug 2012 01:51:37 -0000
Subject: Crashme test cause arm data abort vector modified
Message-ID: <1343958694.1286.YahooMailNeo@web121603.mail.ne1.yahoo.com>

Hi,? All,


I have tested crashme on Marvell PXA920 processor with kernel 3.5-rc6.? System will hang 
during testing. 
Sometimes, the board could be connected by JTAG.? I found the?vector_dabt(address 0xFFFF0010) have been
modified. The instruction 
should be a jump instruction. But it have been modified to "BKPT 0x1"? or "Undefined".
The Vector modification doesn't? happen every time when testing.? 


Have anyone encountered with this status ?? Why arm vector is modified?
Thanks in advance.

BR,
Luffy
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From briefsun at gmail.com  Fri Aug  3 03:18:53 2012
From: briefsun at gmail.com (=?GB2312?B?y+/D99a+?=)
Date: Fri, 03 Aug 2012 07:18:53 -0000
Subject: Crashme test causes arm data abort vector modified
Message-ID: <CAHTtT8-bZJr5t5hZipCROpTRr89bfaG3uCBne0EhHj6RnX=UgA@mail.gmail.com>

Hi,  All,

I have tested crashme on Marvell PXA920 processor with kernel 3.5-rc6.
System will
hang during testing. Sometimes, the board could be connected by JTAG. I
found the
vector_dabt(address 0xFFFF0010) have been modified.

The instruction should be a jump instruction. But it have been modified to
"BKPT
0x1" or "Undefined". The Vector modification doesn't  happen every time when
testing.

Have anyone encountered with this status ?  Why arm vector is modified?
Thanks in advance.

BR,
Luffy
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From pgaikwad at nvidia.com  Mon Aug  6 02:28:59 2012
From: pgaikwad at nvidia.com (Prashant Gaikwad)
Date: Mon, 06 Aug 2012 06:28:59 -0000
Subject: [PATCH v4 5/6] ARM: tegra: Port tegra to generic clock framework
In-Reply-To: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
References: <1344234464-23901-1-git-send-email-pgaikwad@nvidia.com>
Message-ID: <1344234464-23901-6-git-send-email-pgaikwad@nvidia.com>

This patch converts tegra clock code to generic clock framework in following way:
 - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c)
 - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk.
 - Initialize all clock data statically. (tegraXX_clocks_data.c)

Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions.
Removed init function. It's functionality is splitted into recalc_rate and is_enabled.

Static initialization is used since slab is not up in .init_early and clock
is needed to be initialized before clockevent/clocksource initialization.
Macros redefined for clk_tegra.

Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This
is to move quickly to generic common clock framework so that other dependent features will
not be blocked (such as DT binding).

Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20
and Tegra30.

Signed-off-by: Prashant Gaikwad <pgaikwad at nvidia.com>
---
 arch/arm/Kconfig                          |    1 +
 arch/arm/mach-tegra/clock.h               |    1 +
 arch/arm/mach-tegra/tegra20_clocks.c      | 1062 ++++++++++---------
 arch/arm/mach-tegra/tegra20_clocks.h      |    4 +
 arch/arm/mach-tegra/tegra20_clocks_data.c | 1300 +++++++++++++----------
 arch/arm/mach-tegra/tegra30_clocks.c      | 1416 ++++++++++++++----------
 arch/arm/mach-tegra/tegra30_clocks.h      |   14 +-
 arch/arm/mach-tegra/tegra30_clocks_data.c | 1688 ++++++++++++++++-------------
 8 files changed, 3099 insertions(+), 2387 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cd..35a0e5f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -692,6 +692,7 @@ config ARCH_TEGRA
 	select NEED_MACH_IO_H if PCI
 	select ARCH_HAS_CPUFREQ
 	select USE_OF
+	select COMMON_CLK
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
 	  Tegra 6xx and Tegra 2 series).
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index f4d32ba..be69ae1 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -233,6 +233,7 @@ int clk_set_rate_locked(struct clk *c, unsigned long rate);
 int clk_reparent(struct clk *c, struct clk *parent);
 #endif /* !CONFIG_COMMON_CLK */
 
+void tegra_clk_add(struct clk *c);
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
 struct clk *tegra_get_clock_by_name(const char *name);
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 4a32030..a1e0f8a 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -1,7 +1,8 @@
 /*
- * arch/arm/mach-tegra/tegra2_clocks.c
+ * arch/arm/mach-tegra/tegra20_clocks.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Colin Cross <ccross at google.com>
@@ -98,7 +99,7 @@
 #define PLL_OUT_CLKEN			(1<<1)
 #define PLL_OUT_RESET_DISABLE		(1<<0)
 
-#define PLL_MISC(c)			(((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
 
 #define PLL_MISC_DCCON_SHIFT		20
 #define PLL_MISC_CPCON_SHIFT		8
@@ -191,7 +192,8 @@ static unsigned long clk_measure_input_freq(void)
 	} else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
 		return 26000000;
 	} else {
-		pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
+		pr_err("%s: Unexpected clock autodetect value %d",
+						__func__, clock_autodetect);
 		BUG();
 		return 0;
 	}
@@ -230,12 +232,21 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
 }
 
 /* clk_m functions */
-static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
-	u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
+	if (!to_clk_tegra(hw)->fixed_rate)
+		to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+	return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra20_clk_m_init(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 osc_ctrl = clk_readl(OSC_CTRL);
+	u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
 
-	c->rate = clk_measure_input_freq();
-	switch (c->rate) {
+	switch (c->fixed_rate) {
 	case 12000000:
 		auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
 		break;
@@ -249,35 +260,14 @@ static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
 		auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
 		break;
 	default:
-		pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
 		BUG();
 	}
 	clk_writel(auto_clock_control, OSC_CTRL);
-	return c->rate;
-}
-
-static void tegra2_clk_m_init(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	tegra2_clk_m_autodetect_rate(c);
-}
-
-static int tegra2_clk_m_enable(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	return 0;
-}
-
-static void tegra2_clk_m_disable(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	BUG();
 }
 
 struct clk_ops tegra_clk_m_ops = {
-	.init		= tegra2_clk_m_init,
-	.enable		= tegra2_clk_m_enable,
-	.disable	= tegra2_clk_m_disable,
+	.init = tegra20_clk_m_init,
+	.recalc_rate = tegra20_clk_m_recalc_rate,
 };
 
 /* super clock functions */
@@ -286,161 +276,108 @@ struct clk_ops tegra_clk_m_ops = {
  * can't lower the voltage when using the clock skip, but we can if we
  * lower the PLL frequency.
  */
-static void tegra2_super_clk_init(struct clk *c)
+static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	int source;
-	int shift;
-	const struct clk_mux_sel *sel;
+
 	val = clk_readl(c->reg + SUPER_CLK_MUX);
-	c->state = ON;
 	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
 		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-	source = (val >> shift) & SUPER_SOURCE_MASK;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->value == source)
-			break;
-	}
-	BUG_ON(sel->input == NULL);
-	c->parent = sel->input;
+	c->state = ON;
+	return c->state;
 }
 
-static int tegra2_super_clk_enable(struct clk *c)
+static int tegra20_super_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
 	return 0;
 }
 
-static void tegra2_super_clk_disable(struct clk *c)
+static void tegra20_super_clk_disable(struct clk_hw *hw)
 {
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	/* oops - don't disable the CPU clock! */
 	BUG();
 }
 
-static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
+static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
 {
-	u32 val;
-	const struct clk_mux_sel *sel;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	int val = clk_readl(c->reg + SUPER_CLK_MUX);
+	int source;
 	int shift;
 
-	val = clk_readl(c->reg + SUPER_CLK_MUX);
 	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
 		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
 	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
 		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			val &= ~(SUPER_SOURCE_MASK << shift);
-			val |= sel->value << shift;
+	source = (val >> shift) & SUPER_SOURCE_MASK;
+	return source;
+}
 
-			if (c->refcnt)
-				clk_enable(p);
+static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
+	int shift;
 
-			clk_writel(val, c->reg);
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	val &= ~(SUPER_SOURCE_MASK << shift);
+	val |= index << shift;
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+	clk_writel(val, c->reg);
 
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
-	return -EINVAL;
+	return 0;
 }
 
-/*
- * Super clocks have "clock skippers" instead of dividers.  Dividing using
- * a clock skipper does not allow the voltage to be scaled down, so instead
- * adjust the rate of the parent clock.  This requires that the parent of a
- * super clock have no other children, otherwise the rate will change
- * underneath the other children.
- */
-static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
+/* FIX ME: Need to switch parents to change the source PLL rate */
+static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
-	return clk_set_rate(c->parent, rate);
+	return prate;
 }
 
-struct clk_ops tegra_super_ops = {
-	.init			= tegra2_super_clk_init,
-	.enable			= tegra2_super_clk_enable,
-	.disable		= tegra2_super_clk_disable,
-	.set_parent		= tegra2_super_clk_set_parent,
-	.set_rate		= tegra2_super_clk_set_rate,
-};
-
-/* virtual cpu clock functions */
-/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
-   To change the frequency of these clocks, the parent pll may need to be
-   reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
-   and then the clock moved back to the pll.  To hide this sequence, a virtual
-   clock handles it.
- */
-static void tegra2_cpu_clk_init(struct clk *c)
+static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
+	return *prate;
 }
 
-static int tegra2_cpu_clk_enable(struct clk *c)
+static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
 	return 0;
 }
 
-static void tegra2_cpu_clk_disable(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-
-	/* oops - don't disable the CPU clock! */
-	BUG();
-}
+struct clk_ops tegra_super_ops = {
+	.is_enabled = tegra20_super_clk_is_enabled,
+	.enable = tegra20_super_clk_enable,
+	.disable = tegra20_super_clk_disable,
+	.set_parent = tegra20_super_clk_set_parent,
+	.get_parent = tegra20_super_clk_get_parent,
+	.set_rate = tegra20_super_clk_set_rate,
+	.round_rate = tegra20_super_clk_round_rate,
+	.recalc_rate = tegra20_super_clk_recalc_rate,
+};
 
-static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
+static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
 {
-	int ret;
-	/*
-	 * Take an extra reference to the main pll so it doesn't turn
-	 * off when we move the cpu off of it
-	 */
-	clk_enable(c->u.cpu.main);
-
-	ret = clk_set_parent(c->parent, c->u.cpu.backup);
-	if (ret) {
-		pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
-		goto out;
-	}
-
-	if (rate == clk_get_rate(c->u.cpu.backup))
-		goto out;
-
-	ret = clk_set_rate(c->u.cpu.main, rate);
-	if (ret) {
-		pr_err("Failed to change cpu pll to %lu\n", rate);
-		goto out;
-	}
-
-	ret = clk_set_parent(c->parent, c->u.cpu.main);
-	if (ret) {
-		pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
-		goto out;
-	}
-
-out:
-	clk_disable(c->u.cpu.main);
-	return ret;
+	return 0;
 }
 
-struct clk_ops tegra_cpu_ops = {
-	.init     = tegra2_cpu_clk_init,
-	.enable   = tegra2_cpu_clk_enable,
-	.disable  = tegra2_cpu_clk_disable,
-	.set_rate = tegra2_cpu_clk_set_rate,
+struct clk_ops tegra_cop_ops = {
+	.get_parent = tegra20_cop_clk_get_parent,
 };
 
 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
  * reset the COP block (i.e. AVP) */
-static void tegra2_cop_clk_reset(struct clk *c, bool assert)
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
 {
 	unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
 
@@ -448,23 +385,21 @@ static void tegra2_cop_clk_reset(struct clk *c, bool assert)
 	clk_writel(1 << 1, reg);
 }
 
-struct clk_ops tegra_cop_ops = {
-	.reset    = tegra2_cop_clk_reset,
-};
-
 /* bus clock functions */
-static void tegra2_bus_clk_init(struct clk *c)
+static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
+
 	c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-	c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-	c->mul = 1;
+	return c->state;
 }
 
-static int tegra2_bus_clk_enable(struct clk *c)
+static int tegra20_bus_clk_enable(struct clk_hw *hw)
 {
-	u32 val;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
+	u32 val;
 
 	spin_lock_irqsave(&clock_register_lock, flags);
 
@@ -477,10 +412,11 @@ static int tegra2_bus_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra2_bus_clk_disable(struct clk *c)
+static void tegra20_bus_clk_disable(struct clk_hw *hw)
 {
-	u32 val;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
+	u32 val;
 
 	spin_lock_irqsave(&clock_register_lock, flags);
 
@@ -491,12 +427,31 @@ static void tegra2_bus_clk_disable(struct clk *c)
 	spin_unlock_irqrestore(&clock_register_lock, flags);
 }
 
-static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
-	u32 val;
-	unsigned long parent_rate = clk_get_rate(c->parent);
-	unsigned long flags;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg);
+	u64 rate = prate;
+
+	c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+	c->mul = 1;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+	return rate;
+}
+
+static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
 	int ret = -EINVAL;
+	unsigned long flags;
+	u32 val;
 	int i;
 
 	spin_lock_irqsave(&clock_register_lock, flags);
@@ -519,21 +474,56 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
 	return ret;
 }
 
+static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	unsigned long parent_rate = *prate;
+	s64 divider;
+
+	if (rate >= parent_rate)
+		return rate;
+
+	divider = parent_rate;
+	divider += rate - 1;
+	do_div(divider, rate);
+
+	if (divider < 0)
+		return divider;
+
+	if (divider > 4)
+		divider = 4;
+	do_div(parent_rate, divider);
+
+	return parent_rate;
+}
+
 struct clk_ops tegra_bus_ops = {
-	.init			= tegra2_bus_clk_init,
-	.enable			= tegra2_bus_clk_enable,
-	.disable		= tegra2_bus_clk_disable,
-	.set_rate		= tegra2_bus_clk_set_rate,
+	.is_enabled = tegra20_bus_clk_is_enabled,
+	.enable = tegra20_bus_clk_enable,
+	.disable = tegra20_bus_clk_disable,
+	.set_rate = tegra20_bus_clk_set_rate,
+	.round_rate = tegra20_bus_clk_round_rate,
+	.recalc_rate = tegra20_bus_clk_recalc_rate,
 };
 
 /* Blink output functions */
-
-static void tegra2_blink_clk_init(struct clk *c)
+static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 
 	val = pmc_readl(PMC_CTRL);
 	c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+	return c->state;
+}
+
+static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = prate;
+	u32 val;
+
 	c->mul = 1;
 	val = pmc_readl(c->reg);
 
@@ -550,9 +540,16 @@ static void tegra2_blink_clk_init(struct clk *c)
 	} else {
 		c->div = 1;
 	}
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+	return rate;
 }
 
-static int tegra2_blink_clk_enable(struct clk *c)
+static int tegra20_blink_clk_enable(struct clk_hw *hw)
 {
 	u32 val;
 
@@ -565,7 +562,7 @@ static int tegra2_blink_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra2_blink_clk_disable(struct clk *c)
+static void tegra20_blink_clk_disable(struct clk_hw *hw)
 {
 	u32 val;
 
@@ -576,9 +573,11 @@ static void tegra2_blink_clk_disable(struct clk *c)
 	pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
 }
 
-static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	unsigned long parent_rate = clk_get_rate(c->parent);
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (rate >= parent_rate) {
 		c->div = 1;
 		pmc_writel(0, c->reg);
@@ -601,31 +600,74 @@ static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
+static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	int div;
+	int mul;
+	long round_rate = *prate;
+
+	mul = 1;
+
+	if (rate >= *prate) {
+		div = 1;
+	} else {
+		div = DIV_ROUND_UP(*prate / 8, rate);
+		div *= 8;
+	}
+
+	round_rate *= mul;
+	round_rate += div - 1;
+	do_div(round_rate, div);
+
+	return round_rate;
+}
+
 struct clk_ops tegra_blink_clk_ops = {
-	.init			= &tegra2_blink_clk_init,
-	.enable			= &tegra2_blink_clk_enable,
-	.disable		= &tegra2_blink_clk_disable,
-	.set_rate		= &tegra2_blink_clk_set_rate,
+	.is_enabled = tegra20_blink_clk_is_enabled,
+	.enable = tegra20_blink_clk_enable,
+	.disable = tegra20_blink_clk_disable,
+	.set_rate = tegra20_blink_clk_set_rate,
+	.round_rate = tegra20_blink_clk_round_rate,
+	.recalc_rate = tegra20_blink_clk_recalc_rate,
 };
 
 /* PLL Functions */
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
+static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
 {
 	udelay(c->u.pll.lock_delay);
-
 	return 0;
 }
 
-static void tegra2_pll_clk_init(struct clk *c)
+static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg + PLL_BASE);
 
 	c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+	return c->state;
+}
+
+static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
+				unsigned long prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg + PLL_BASE);
+	u64 rate = prate;
 
 	if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-		pr_warning("Clock %s has unknown fixed frequency\n", c->name);
-		c->mul = 1;
-		c->div = 1;
+		const struct clk_pll_freq_table *sel;
+		for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+			if (sel->input_rate == prate &&
+				sel->output_rate == c->u.pll.fixed_rate) {
+				c->mul = sel->n;
+				c->div = sel->m * sel->p;
+				break;
+			}
+		}
+		pr_err("Clock %s has unknown fixed frequency\n",
+			__clk_get_name(hw->clk));
+		BUG();
 	} else if (val & PLL_BASE_BYPASS) {
 		c->mul = 1;
 		c->div = 1;
@@ -637,42 +679,63 @@ static void tegra2_pll_clk_init(struct clk *c)
 		else
 			c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
 	}
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+	return rate;
 }
 
-static int tegra2_pll_clk_enable(struct clk *c)
+static int tegra20_pll_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	val = clk_readl(c->reg + PLL_BASE);
 	val &= ~PLL_BASE_BYPASS;
 	val |= PLL_BASE_ENABLE;
 	clk_writel(val, c->reg + PLL_BASE);
 
-	tegra2_pll_clk_wait_for_lock(c);
+	tegra20_pll_clk_wait_for_lock(c);
 
 	return 0;
 }
 
-static void tegra2_pll_clk_disable(struct clk *c)
+static void tegra20_pll_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	val = clk_readl(c->reg);
 	val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 	clk_writel(val, c->reg);
 }
 
-static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	u32 val;
-	unsigned long input_rate;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long input_rate = parent_rate;
 	const struct clk_pll_freq_table *sel;
+	u32 val;
 
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+	pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+	if (c->flags & PLL_FIXED) {
+		int ret = 0;
+		if (rate != c->u.pll.fixed_rate) {
+			pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+				__func__, __clk_get_name(hw->clk),
+				c->u.pll.fixed_rate, rate);
+			ret = -EINVAL;
+		}
+		return ret;
+	}
 
-	input_rate = clk_get_rate(c->parent);
 	for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
 		if (sel->input_rate == input_rate && sel->output_rate == rate) {
 			c->mul = sel->n;
@@ -703,41 +766,76 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
 			}
 
 			if (c->state == ON)
-				tegra2_pll_clk_enable(c);
-
+				tegra20_pll_clk_enable(hw);
 			return 0;
 		}
 	}
 	return -EINVAL;
 }
 
+static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	const struct clk_pll_freq_table *sel;
+	unsigned long input_rate = *prate;
+	unsigned long output_rate = *prate;
+	int mul;
+	int div;
+
+	if (c->flags & PLL_FIXED)
+		return c->u.pll.fixed_rate;
+
+	for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
+		if (sel->input_rate == input_rate && sel->output_rate == rate) {
+			mul = sel->n;
+			div = sel->m * sel->p;
+			break;
+		}
+
+	if (sel->input_rate == 0)
+		return -EINVAL;
+
+	output_rate *= mul;
+	output_rate += div - 1; /* round up */
+	do_div(output_rate, div);
+
+	return output_rate;
+}
+
 struct clk_ops tegra_pll_ops = {
-	.init			= tegra2_pll_clk_init,
-	.enable			= tegra2_pll_clk_enable,
-	.disable		= tegra2_pll_clk_disable,
-	.set_rate		= tegra2_pll_clk_set_rate,
+	.is_enabled = tegra20_pll_clk_is_enabled,
+	.enable = tegra20_pll_clk_enable,
+	.disable = tegra20_pll_clk_disable,
+	.set_rate = tegra20_pll_clk_set_rate,
+	.recalc_rate = tegra20_pll_clk_recalc_rate,
+	.round_rate = tegra20_pll_clk_round_rate,
 };
 
-static void tegra2_pllx_clk_init(struct clk *c)
+static void tegra20_pllx_clk_init(struct clk_hw *hw)
 {
-	tegra2_pll_clk_init(c);
+	struct clk_tegra *c = to_clk_tegra(hw);
 
 	if (tegra_sku_id == 7)
 		c->max_rate = 750000000;
 }
 
 struct clk_ops tegra_pllx_ops = {
-	.init     = tegra2_pllx_clk_init,
-	.enable   = tegra2_pll_clk_enable,
-	.disable  = tegra2_pll_clk_disable,
-	.set_rate = tegra2_pll_clk_set_rate,
+	.init = tegra20_pllx_clk_init,
+	.is_enabled = tegra20_pll_clk_is_enabled,
+	.enable = tegra20_pll_clk_enable,
+	.disable = tegra20_pll_clk_disable,
+	.set_rate = tegra20_pll_clk_set_rate,
+	.recalc_rate = tegra20_pll_clk_recalc_rate,
+	.round_rate = tegra20_pll_clk_round_rate,
 };
 
-static int tegra2_plle_clk_enable(struct clk *c)
+static int tegra20_plle_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	mdelay(1);
 
@@ -753,20 +851,35 @@ static int tegra2_plle_clk_enable(struct clk *c)
 }
 
 struct clk_ops tegra_plle_ops = {
-	.init       = tegra2_pll_clk_init,
-	.enable     = tegra2_plle_clk_enable,
-	.set_rate   = tegra2_pll_clk_set_rate,
+	.is_enabled = tegra20_pll_clk_is_enabled,
+	.enable = tegra20_plle_clk_enable,
+	.set_rate = tegra20_pll_clk_set_rate,
+	.recalc_rate = tegra20_pll_clk_recalc_rate,
+	.round_rate = tegra20_pll_clk_round_rate,
 };
 
 /* Clock divider ops */
-static void tegra2_pll_div_clk_init(struct clk *c)
+static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
-	u32 divu71;
+
 	val >>= c->reg_shift;
 	c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
 	if (!(val & PLL_OUT_RESET_DISABLE))
 		c->state = OFF;
+	return c->state;
+}
+
+static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = prate;
+	u32 val = clk_readl(c->reg);
+	u32 divu71;
+
+	val >>= c->reg_shift;
 
 	if (c->flags & DIV_U71) {
 		divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
@@ -779,15 +892,23 @@ static void tegra2_pll_div_clk_init(struct clk *c)
 		c->div = 1;
 		c->mul = 1;
 	}
+
+	rate *= c->mul;
+	rate += c->div - 1; /* round up */
+	do_div(rate, c->div);
+
+	return rate;
 }
 
-static int tegra2_pll_div_clk_enable(struct clk *c)
+static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
 {
-	u32 val;
-	u32 new_val;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
+	u32 new_val;
+	u32 val;
+
+	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
 
-	pr_debug("%s: %s\n", __func__, c->name);
 	if (c->flags & DIV_U71) {
 		spin_lock_irqsave(&clock_register_lock, flags);
 		val = clk_readl(c->reg);
@@ -813,13 +934,15 @@ static int tegra2_pll_div_clk_enable(struct clk *c)
 	return -EINVAL;
 }
 
-static void tegra2_pll_div_clk_disable(struct clk *c)
+static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
 {
-	u32 val;
-	u32 new_val;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
+	u32 new_val;
+	u32 val;
+
+	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
 
-	pr_debug("%s: %s\n", __func__, c->name);
 	if (c->flags & DIV_U71) {
 		spin_lock_irqsave(&clock_register_lock, flags);
 		val = clk_readl(c->reg);
@@ -842,15 +965,17 @@ static void tegra2_pll_div_clk_disable(struct clk *c)
 	}
 }
 
-static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	u32 val;
-	u32 new_val;
-	int divider_u71;
-	unsigned long parent_rate = clk_get_rate(c->parent);
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
+	int divider_u71;
+	u32 new_val;
+	u32 val;
+
+	pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
 
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
 	if (c->flags & DIV_U71) {
 		divider_u71 = clk_div71_get_divider(parent_rate, rate);
 		if (divider_u71 >= 0) {
@@ -878,11 +1003,14 @@ static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long parent_rate = *prate;
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+	pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(parent_rate, rate);
@@ -896,60 +1024,24 @@ static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
 }
 
 struct clk_ops tegra_pll_div_ops = {
-	.init			= tegra2_pll_div_clk_init,
-	.enable			= tegra2_pll_div_clk_enable,
-	.disable		= tegra2_pll_div_clk_disable,
-	.set_rate		= tegra2_pll_div_clk_set_rate,
-	.round_rate		= tegra2_pll_div_clk_round_rate,
+	.is_enabled = tegra20_pll_div_clk_is_enabled,
+	.enable = tegra20_pll_div_clk_enable,
+	.disable = tegra20_pll_div_clk_disable,
+	.set_rate = tegra20_pll_div_clk_set_rate,
+	.round_rate = tegra20_pll_div_clk_round_rate,
+	.recalc_rate = tegra20_pll_div_clk_recalc_rate,
 };
 
 /* Periph clk ops */
 
-static void tegra2_periph_clk_init(struct clk *c)
+static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
 {
-	u32 val = clk_readl(c->reg);
-	const struct clk_mux_sel *mux = NULL;
-	const struct clk_mux_sel *sel;
-	u32 shift;
-	u32 mask;
-
-	if (c->flags & MUX_PWM) {
-		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-		mask = PERIPH_CLK_SOURCE_PWM_MASK;
-	} else {
-		shift = PERIPH_CLK_SOURCE_SHIFT;
-		mask = PERIPH_CLK_SOURCE_MASK;
-	}
-
-	if (c->flags & MUX) {
-		for (sel = c->inputs; sel->input != NULL; sel++) {
-			if ((val & mask) >> shift == sel->value)
-				mux = sel;
-		}
-		BUG_ON(!mux);
-
-		c->parent = mux->input;
-	} else {
-		c->parent = c->inputs[0].input;
-	}
-
-	if (c->flags & DIV_U71) {
-		u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-		c->div = divu71 + 2;
-		c->mul = 2;
-	} else if (c->flags & DIV_U16) {
-		u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-		c->div = divu16 + 1;
-		c->mul = 1;
-	} else {
-		c->div = 1;
-		c->mul = 1;
-	}
+	struct clk_tegra *c = to_clk_tegra(hw);
 
 	c->state = ON;
 
 	if (!c->u.periph.clk_num)
-		return;
+		goto out;
 
 	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
 			PERIPH_CLK_TO_ENB_BIT(c)))
@@ -959,24 +1051,27 @@ static void tegra2_periph_clk_init(struct clk *c)
 		if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
 				PERIPH_CLK_TO_ENB_BIT(c))
 			c->state = OFF;
+
+out:
+	return c->state;
 }
 
-static int tegra2_periph_clk_enable(struct clk *c)
+static int tegra20_periph_clk_enable(struct clk_hw *hw)
 {
-	u32 val;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
-	int refcount;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	u32 val;
+
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	if (!c->u.periph.clk_num)
 		return 0;
 
-	spin_lock_irqsave(&clock_register_lock, flags);
-
-	refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+	tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+		return 0;
 
-	if (refcount > 1)
-		goto out;
+	spin_lock_irqsave(&clock_register_lock, flags);
 
 	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
 		CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
@@ -991,39 +1086,41 @@ static int tegra2_periph_clk_enable(struct clk *c)
 		clk_writel(val, c->reg);
 	}
 
-out:
 	spin_unlock_irqrestore(&clock_register_lock, flags);
 
 	return 0;
 }
 
-static void tegra2_periph_clk_disable(struct clk *c)
+static void tegra20_periph_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long flags;
 
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	if (!c->u.periph.clk_num)
 		return;
 
-	spin_lock_irqsave(&clock_register_lock, flags);
+	tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
 
-	if (c->refcnt)
-		tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+		return;
 
-	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
-		clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-			CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+	spin_lock_irqsave(&clock_register_lock, flags);
+
+	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+		CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
 
 	spin_unlock_irqrestore(&clock_register_lock, flags);
 }
 
-static void tegra2_periph_clk_reset(struct clk *c, bool assert)
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
 
 	pr_debug("%s %s on clock %s\n", __func__,
-		 assert ? "assert" : "deassert", c->name);
+		assert ? "assert" : "deassert", __clk_get_name(hw->clk));
 
 	BUG_ON(!c->u.periph.clk_num);
 
@@ -1032,13 +1129,14 @@ static void tegra2_periph_clk_reset(struct clk *c, bool assert)
 			   base + PERIPH_CLK_TO_ENB_SET_REG(c));
 }
 
-static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	const struct clk_mux_sel *sel;
-	u32 mask, shift;
+	u32 mask;
+	u32 shift;
 
-	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+	pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
 
 	if (c->flags & MUX_PWM) {
 		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
@@ -1048,36 +1146,78 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 		mask = PERIPH_CLK_SOURCE_MASK;
 	}
 
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			val = clk_readl(c->reg);
-			val &= ~mask;
-			val |= (sel->value) << shift;
+	val = clk_readl(c->reg);
+	val &= ~mask;
+	val |= (index) << shift;
 
-			if (c->refcnt)
-				clk_enable(p);
+	clk_writel(val, c->reg);
 
-			clk_writel(val, c->reg);
+	return 0;
+}
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg);
+	u32 mask;
+	u32 shift;
 
-			clk_reparent(c, p);
-			return 0;
-		}
+	if (c->flags & MUX_PWM) {
+		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+		mask = PERIPH_CLK_SOURCE_PWM_MASK;
+	} else {
+		shift = PERIPH_CLK_SOURCE_SHIFT;
+		mask = PERIPH_CLK_SOURCE_MASK;
 	}
 
-	return -EINVAL;
+	if (c->flags & MUX)
+		return (val & mask) >> shift;
+	else
+		return 0;
 }
 
-static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long rate = prate;
+	u32 val = clk_readl(c->reg);
+
+	if (c->flags & DIV_U71) {
+		u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+		c->div = divu71 + 2;
+		c->mul = 2;
+	} else if (c->flags & DIV_U16) {
+		u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+		c->div = divu16 + 1;
+		c->mul = 1;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+		return rate;
+	}
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
+}
+
+static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
+
+	val = clk_readl(c->reg);
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(parent_rate, rate);
+
 		if (divider >= 0) {
 			val = clk_readl(c->reg);
 			val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
@@ -1103,15 +1243,21 @@ static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
 		c->mul = 1;
 		return 0;
 	}
+
 	return -EINVAL;
 }
 
-static long tegra2_periph_clk_round_rate(struct clk *c,
-	unsigned long rate)
+static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
+	unsigned long rate, unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+	pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+	if (prate)
+		parent_rate = *prate;
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(parent_rate, rate);
@@ -1129,44 +1275,27 @@ static long tegra2_periph_clk_round_rate(struct clk *c,
 }
 
 struct clk_ops tegra_periph_clk_ops = {
-	.init			= &tegra2_periph_clk_init,
-	.enable			= &tegra2_periph_clk_enable,
-	.disable		= &tegra2_periph_clk_disable,
-	.set_parent		= &tegra2_periph_clk_set_parent,
-	.set_rate		= &tegra2_periph_clk_set_rate,
-	.round_rate		= &tegra2_periph_clk_round_rate,
-	.reset			= &tegra2_periph_clk_reset,
+	.is_enabled = tegra20_periph_clk_is_enabled,
+	.enable = tegra20_periph_clk_enable,
+	.disable = tegra20_periph_clk_disable,
+	.set_parent = tegra20_periph_clk_set_parent,
+	.get_parent = tegra20_periph_clk_get_parent,
+	.set_rate = tegra20_periph_clk_set_rate,
+	.round_rate = tegra20_periph_clk_round_rate,
+	.recalc_rate = tegra20_periph_clk_recalc_rate,
 };
 
-/* The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB. */
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
-{
-	u32 reg;
-	unsigned long flags;
-
-	spin_lock_irqsave(&c->spinlock, flags);
-
-	delay = clamp(delay, 0, 15);
-	reg = clk_readl(c->reg);
-	reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
-	reg |= SDMMC_CLK_INT_FB_SEL;
-	reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
-	clk_writel(reg, c->reg);
-
-	spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
 /* External memory controller clock ops */
-static void tegra2_emc_clk_init(struct clk *c)
+static void tegra20_emc_clk_init(struct clk_hw *hw)
 {
-	tegra2_periph_clk_init(c);
-	c->max_rate = clk_get_rate_locked(c);
+	struct clk_tegra *c = to_clk_tegra(hw);
+	c->max_rate = __clk_get_rate(hw->clk);
 }
 
-static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	long emc_rate;
 	long clk_rate;
 
@@ -1182,7 +1311,7 @@ static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
 	 * The fastest rate the PLL will generate that is at most the
 	 * requested rate.
 	 */
-	clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
+	clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
 
 	/*
 	 * If this fails, and emc_rate > clk_rate, it's because the maximum
@@ -1198,9 +1327,11 @@ static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
 	return emc_rate;
 }
 
-static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
 	int ret;
+
 	/*
 	 * The Tegra2 memory controller has an interlock with the clock
 	 * block that allows memory shadowed registers to be updated,
@@ -1211,116 +1342,145 @@ static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
 	if (ret < 0)
 		return ret;
 
-	ret = tegra2_periph_clk_set_rate(c, rate);
+	ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
 	udelay(1);
 
 	return ret;
 }
 
 struct clk_ops tegra_emc_clk_ops = {
-	.init			= &tegra2_emc_clk_init,
-	.enable			= &tegra2_periph_clk_enable,
-	.disable		= &tegra2_periph_clk_disable,
-	.set_parent		= &tegra2_periph_clk_set_parent,
-	.set_rate		= &tegra2_emc_clk_set_rate,
-	.round_rate		= &tegra2_emc_clk_round_rate,
-	.reset			= &tegra2_periph_clk_reset,
+	.init = tegra20_emc_clk_init,
+	.is_enabled = tegra20_periph_clk_is_enabled,
+	.enable = tegra20_periph_clk_enable,
+	.disable = tegra20_periph_clk_disable,
+	.set_parent = tegra20_periph_clk_set_parent,
+	.get_parent = tegra20_periph_clk_get_parent,
+	.set_rate = tegra20_emc_clk_set_rate,
+	.round_rate = tegra20_emc_clk_round_rate,
+	.recalc_rate = tegra20_periph_clk_recalc_rate,
 };
 
 /* Clock doubler ops */
-static void tegra2_clk_double_init(struct clk *c)
+static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
 {
-	c->mul = 2;
-	c->div = 1;
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	c->state = ON;
 
 	if (!c->u.periph.clk_num)
-		return;
+		goto out;
 
 	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
 			PERIPH_CLK_TO_ENB_BIT(c)))
 		c->state = OFF;
+
+out:
+	return c->state;
 };
 
-static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
-	if (rate != 2 * clk_get_rate(c->parent))
-		return -EINVAL;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = prate;
+
 	c->mul = 2;
 	c->div = 1;
+
+	rate *= c->mul;
+	rate += c->div - 1; /* round up */
+	do_div(rate, c->div);
+
+	return rate;
+}
+
+static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	unsigned long output_rate = *prate;
+
+	do_div(output_rate, 2);
+	return output_rate;
+}
+
+static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
+{
+	if (rate != 2 * parent_rate)
+		return -EINVAL;
 	return 0;
 }
 
 struct clk_ops tegra_clk_double_ops = {
-	.init			= &tegra2_clk_double_init,
-	.enable			= &tegra2_periph_clk_enable,
-	.disable		= &tegra2_periph_clk_disable,
-	.set_rate		= &tegra2_clk_double_set_rate,
+	.is_enabled = tegra20_clk_double_is_enabled,
+	.enable = tegra20_periph_clk_enable,
+	.disable = tegra20_periph_clk_disable,
+	.set_rate = tegra20_clk_double_set_rate,
+	.recalc_rate = tegra20_clk_double_recalc_rate,
+	.round_rate = tegra20_clk_double_round_rate,
 };
 
 /* Audio sync clock ops */
-static void tegra2_audio_sync_clk_init(struct clk *c)
+static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
 {
-	int source;
-	const struct clk_mux_sel *sel;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
+
 	c->state = (val & (1<<4)) ? OFF : ON;
-	source = val & 0xf;
-	for (sel = c->inputs; sel->input != NULL; sel++)
-		if (sel->value == source)
-			break;
-	BUG_ON(sel->input == NULL);
-	c->parent = sel->input;
+	return c->state;
 }
 
-static int tegra2_audio_sync_clk_enable(struct clk *c)
+static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	clk_writel(0, c->reg);
 	return 0;
 }
 
-static void tegra2_audio_sync_clk_disable(struct clk *c)
+static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	clk_writel(1, c->reg);
 }
 
-static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
 {
-	u32 val;
-	const struct clk_mux_sel *sel;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			val = clk_readl(c->reg);
-			val &= ~0xf;
-			val |= sel->value;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg);
+	int source;
 
-			if (c->refcnt)
-				clk_enable(p);
+	source = val & 0xf;
+	return source;
+}
 
-			clk_writel(val, c->reg);
+static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val;
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+	val = clk_readl(c->reg);
+	val &= ~0xf;
+	val |= index;
 
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
+	clk_writel(val, c->reg);
 
-	return -EINVAL;
+	return 0;
 }
 
 struct clk_ops tegra_audio_sync_clk_ops = {
-	.init       = tegra2_audio_sync_clk_init,
-	.enable     = tegra2_audio_sync_clk_enable,
-	.disable    = tegra2_audio_sync_clk_disable,
-	.set_parent = tegra2_audio_sync_clk_set_parent,
+	.is_enabled = tegra20_audio_sync_clk_is_enabled,
+	.enable = tegra20_audio_sync_clk_enable,
+	.disable = tegra20_audio_sync_clk_disable,
+	.set_parent = tegra20_audio_sync_clk_set_parent,
+	.get_parent = tegra20_audio_sync_clk_get_parent,
 };
 
 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
 
-static void tegra2_cdev_clk_init(struct clk *c)
+static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	/* We could un-tristate the cdev1 or cdev2 pingroup here; this is
 	 * currently done in the pinmux code. */
 	c->state = ON;
@@ -1330,10 +1490,12 @@ static void tegra2_cdev_clk_init(struct clk *c)
 	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
 			PERIPH_CLK_TO_ENB_BIT(c)))
 		c->state = OFF;
+	return c->state;
 }
 
-static int tegra2_cdev_clk_enable(struct clk *c)
+static int tegra20_cdev_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	BUG_ON(!c->u.periph.clk_num);
 
 	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
@@ -1341,118 +1503,24 @@ static int tegra2_cdev_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra2_cdev_clk_disable(struct clk *c)
+static void tegra20_cdev_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	BUG_ON(!c->u.periph.clk_num);
 
 	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
 		CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
 }
 
-struct clk_ops tegra_cdev_clk_ops = {
-	.init			= &tegra2_cdev_clk_init,
-	.enable			= &tegra2_cdev_clk_enable,
-	.disable		= &tegra2_cdev_clk_disable,
-};
-
-/* shared bus ops */
-/*
- * Some clocks may have multiple downstream users that need to request a
- * higher clock rate.  Shared bus clocks provide a unique shared_bus_user
- * clock to each user.  The frequency of the bus is set to the highest
- * enabled shared_bus_user clock, with a minimum value set by the
- * shared bus.
- */
-static int tegra_clk_shared_bus_update(struct clk *bus)
-{
-	struct clk *c;
-	unsigned long rate = bus->min_rate;
-
-	list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
-		if (c->u.shared_bus_user.enabled)
-			rate = max(c->u.shared_bus_user.rate, rate);
-
-	if (rate == clk_get_rate_locked(bus))
-		return 0;
-
-	return clk_set_rate_locked(bus, rate);
-};
-
-static void tegra_clk_shared_bus_init(struct clk *c)
-{
-	unsigned long flags;
-
-	c->max_rate = c->parent->max_rate;
-	c->u.shared_bus_user.rate = c->parent->max_rate;
-	c->state = OFF;
-	c->set = true;
-
-	spin_lock_irqsave(&c->parent->spinlock, flags);
-
-	list_add_tail(&c->u.shared_bus_user.node,
-		&c->parent->shared_bus_list);
-
-	spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
+			unsigned long prate)
 {
-	unsigned long flags;
-	int ret;
-	long new_rate = rate;
-
-	new_rate = clk_round_rate(c->parent, new_rate);
-	if (new_rate < 0)
-		return new_rate;
-
-	spin_lock_irqsave(&c->parent->spinlock, flags);
-
-	c->u.shared_bus_user.rate = new_rate;
-	ret = tegra_clk_shared_bus_update(c->parent);
-
-	spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-	return ret;
-}
-
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
-{
-	return clk_round_rate(c->parent, rate);
+	return to_clk_tegra(hw)->fixed_rate;
 }
 
-static int tegra_clk_shared_bus_enable(struct clk *c)
-{
-	unsigned long flags;
-	int ret;
-
-	spin_lock_irqsave(&c->parent->spinlock, flags);
-
-	c->u.shared_bus_user.enabled = true;
-	ret = tegra_clk_shared_bus_update(c->parent);
-
-	spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-	return ret;
-}
-
-static void tegra_clk_shared_bus_disable(struct clk *c)
-{
-	unsigned long flags;
-	int ret;
-
-	spin_lock_irqsave(&c->parent->spinlock, flags);
-
-	c->u.shared_bus_user.enabled = false;
-	ret = tegra_clk_shared_bus_update(c->parent);
-	WARN_ON_ONCE(ret);
-
-	spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-struct clk_ops tegra_clk_shared_bus_ops = {
-	.init = tegra_clk_shared_bus_init,
-	.enable = tegra_clk_shared_bus_enable,
-	.disable = tegra_clk_shared_bus_disable,
-	.set_rate = tegra_clk_shared_bus_set_rate,
-	.round_rate = tegra_clk_shared_bus_round_rate,
+struct clk_ops tegra_cdev_clk_ops = {
+	.is_enabled = tegra20_cdev_clk_is_enabled,
+	.enable = tegra20_cdev_clk_enable,
+	.disable = tegra20_cdev_clk_disable,
+	.recalc_rate = tegra20_cdev_recalc_rate,
 };
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
index 167058c..0e42ec0 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -17,6 +17,7 @@
 #ifndef __MACH_TEGRA20_CLOCK_H
 #define __MACH_TEGRA20_CLOCK_H
 
+extern struct clk_ops tegra_clk_32k_ops;
 extern struct clk_ops tegra_pll_ops;
 extern struct clk_ops tegra_clk_m_ops;
 extern struct clk_ops tegra_pll_div_ops;
@@ -34,4 +35,7 @@ extern struct clk_ops tegra_emc_clk_ops;
 extern struct clk_ops tegra_periph_clk_ops;
 extern struct clk_ops tegra_clk_shared_bus_ops;
 
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
+
 #endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 24f45ff..b5c518e 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/tegra2_clocks.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Colin Cross <ccross at google.com>
@@ -17,13 +18,13 @@
  *
  */
 
+#include <linux/clk-private.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/clkdev.h>
 #include <linux/clk.h>
 
 #include <mach/iomap.h>
@@ -35,13 +36,126 @@
 #include "tegra20_clocks.h"
 
 /* Clock definitions */
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,		\
+		   _parent_names, _parents, _parent)		\
+	static struct clk tegra_##_name = {			\
+		.hw = &tegra_##_name##_hw.hw,			\
+		.name = #_name,					\
+		.rate = _rate,					\
+		.ops = _ops,					\
+		.flags = _flags,				\
+		.parent_names = _parent_names,			\
+		.parents = _parents,				\
+		.num_parents = ARRAY_SIZE(_parent_names),	\
+		.parent = _parent,				\
+	};
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+	.hw = {
+		.clk = &tegra_clk_32k,
+	},
+	.fixed_rate = 32768,
+};
+
 static struct clk tegra_clk_32k = {
 	.name = "clk_32k",
 	.rate = 32768,
-	.ops  = NULL,
-	.max_rate = 32768,
+	.ops = &tegra_clk_32k_ops,
+	.hw = &tegra_clk_32k_hw.hw,
+	.flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+	.hw = {
+		.clk = &tegra_clk_m,
+	},
+	.flags = ENABLE_ON_INIT,
+	.reg = 0x1fc,
+	.reg_shift = 28,
+	.max_rate = 26000000,
+	.fixed_rate = 0,
+};
+
+static struct clk tegra_clk_m = {
+	.name = "clk_m",
+	.ops = &tegra_clk_m_ops,
+	.hw = &tegra_clk_m_hw.hw,
+	.flags = CLK_IS_ROOT,
 };
 
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,	\
+		   _input_max, _cf_min, _cf_max, _vco_min,	\
+		   _vco_max, _freq_table, _lock_delay, _ops,	\
+		   _fixed_rate, _parent)			\
+	static const char *tegra_##_name##_parent_names[] = {	\
+		#_parent,					\
+	};							\
+	static struct clk *tegra_##_name##_parents[] = {	\
+		&tegra_##_parent,				\
+	};							\
+	static struct clk tegra_##_name;			\
+	static struct clk_tegra tegra_##_name##_hw = {		\
+		.hw = {						\
+			.clk = &tegra_##_name,			\
+		},						\
+		.flags = _flags,				\
+		.reg = _reg,					\
+		.max_rate = _max_rate,				\
+		.u.pll = {					\
+			.input_min = _input_min,		\
+			.input_max = _input_max,		\
+			.cf_min = _cf_min,			\
+			.cf_max = _cf_max,			\
+			.vco_min = _vco_min,			\
+			.vco_max = _vco_max,			\
+			.freq_table = _freq_table,		\
+			.lock_delay = _lock_delay,		\
+			.fixed_rate = _fixed_rate,		\
+		},						\
+	};							\
+	static struct clk tegra_##_name = {			\
+		.name = #_name,					\
+		.ops = &_ops,					\
+		.hw = &tegra_##_name##_hw.hw,			\
+		.parent = &tegra_##_parent,			\
+		.parent_names = tegra_##_name##_parent_names,	\
+		.parents = tegra_##_name##_parents,		\
+		.num_parents = 1,				\
+	};
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,		\
+		_max_rate, _ops, _parent, _clk_flags)		\
+	static const char *tegra_##_name##_parent_names[] = {	\
+		#_parent,					\
+	};							\
+	static struct clk *tegra_##_name##_parents[] = {	\
+		&tegra_##_parent,				\
+	};							\
+	static struct clk tegra_##_name;			\
+	static struct clk_tegra tegra_##_name##_hw = {		\
+		.hw = {						\
+			.clk = &tegra_##_name,			\
+		},						\
+		.flags = _flags,				\
+		.reg = _reg,					\
+		.max_rate = _max_rate,				\
+		.reg_shift = _reg_shift,			\
+	};							\
+	static struct clk tegra_##_name = {			\
+		.name = #_name,					\
+		.ops = &tegra_pll_div_ops,			\
+		.hw = &tegra_##_name##_hw.hw,			\
+		.parent = &tegra_##_parent,			\
+		.parent_names = tegra_##_name##_parent_names,	\
+		.parents = tegra_##_name##_parents,		\
+		.num_parents = 1,				\
+		.flags = _clk_flags,				\
+	};
+
+
 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
 	{32768, 12000000, 366, 1, 1, 0},
 	{32768, 13000000, 397, 1, 1, 0},
@@ -50,40 +164,9 @@ static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
 	{0, 0, 0, 0, 0, 0},
 };
 
-static struct clk tegra_pll_s = {
-	.name      = "pll_s",
-	.flags     = PLL_ALT_MISC_REG,
-	.ops       = &tegra_pll_ops,
-	.parent    = &tegra_clk_32k,
-	.max_rate  = 26000000,
-	.reg       = 0xf0,
-	.u.pll = {
-		.input_min = 32768,
-		.input_max = 32768,
-		.cf_min    = 0, /* FIXME */
-		.cf_max    = 0, /* FIXME */
-		.vco_min   = 12000000,
-		.vco_max   = 26000000,
-		.freq_table = tegra_pll_s_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk_mux_sel tegra_clk_m_sel[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ .input = &tegra_pll_s,  .value = 1},
-	{ NULL , 0},
-};
-
-static struct clk tegra_clk_m = {
-	.name      = "clk_m",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra_clk_m_ops,
-	.inputs    = tegra_clk_m_sel,
-	.reg       = 0x1fc,
-	.reg_shift = 28,
-	.max_rate  = 26000000,
-};
+DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
+		0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
+		tegra_pll_ops, 0, clk_32k);
 
 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
 	{ 12000000, 600000000, 600, 12, 1, 8 },
@@ -93,34 +176,12 @@ static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_c = {
-	.name      = "pll_c",
-	.flags	   = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x80,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 600000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_c_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
+		6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+		tegra_pll_ops, 0, clk_m);
 
-static struct clk tegra_pll_c_out1 = {
-	.name      = "pll_c_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_c,
-	.reg       = 0x84,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
+		tegra_pll_div_ops, pll_c, 0);
 
 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
 	{ 12000000, 666000000, 666, 12, 1, 8},
@@ -134,34 +195,12 @@ static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_m = {
-	.name      = "pll_m",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0x90,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 800000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_m_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
+		6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
+		tegra_pll_ops, 0, clk_m);
 
-static struct clk tegra_pll_m_out1 = {
-	.name      = "pll_m_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_m,
-	.reg       = 0x94,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+		tegra_pll_div_ops, pll_m, 0);
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
 	{ 12000000, 216000000, 432, 12, 2, 8},
@@ -175,64 +214,19 @@ static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_p = {
-	.name      = "pll_p",
-	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xa0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 432000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_p_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_p_out1 = {
-	.name      = "pll_p_out1",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-	.name      = "pll_p_out2",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
 
-static struct clk tegra_pll_p_out3 = {
-	.name      = "pll_p_out3",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+		2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+		tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
 
-static struct clk tegra_pll_p_out4 = {
-	.name      = "pll_p_out4",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
+		432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
+		432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
+		432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
+		432000000, tegra_pll_div_ops, pll_p, 0);
 
 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
 	{ 28800000, 56448000, 49, 25, 1, 1},
@@ -241,34 +235,12 @@ static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_a = {
-	.name      = "pll_a",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xb0,
-	.parent    = &tegra_pll_p_out1,
-	.max_rate  = 73728000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_a_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
+		6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
+		tegra_pll_ops, 0, pll_p_out1);
 
-static struct clk tegra_pll_a_out0 = {
-	.name      = "pll_a_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_a,
-	.reg       = 0xb4,
-	.reg_shift = 0,
-	.max_rate  = 73728000,
-};
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
+		tegra_pll_div_ops, pll_a, 0);
 
 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 	{ 12000000, 216000000, 216, 12, 1, 4},
@@ -289,32 +261,12 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_d = {
-	.name      = "pll_d",
-	.flags     = PLL_HAS_CPCON | PLLD,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xd0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+		1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+		1000, tegra_pll_ops, 0, clk_m);
 
-static struct clk tegra_pll_d_out0 = {
-	.name      = "pll_d_out0",
-	.ops       = &tegra_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d,
-	.max_rate  = 500000000,
-};
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
+		tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
 
 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
 	{ 12000000, 480000000, 960, 12, 2, 0},
@@ -324,24 +276,9 @@ static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_u = {
-	.name      = "pll_u",
-	.flags     = PLLU,
-	.ops       = &tegra_pll_ops,
-	.reg       = 0xc0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 480000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 480000000,
-		.vco_max   = 960000000,
-		.freq_table = tegra_pll_u_freq_table,
-		.lock_delay = 1000,
-	},
-};
+DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
+		48000000, 960000000, tegra_pll_u_freq_table, 1000,
+		tegra_pll_ops, 0, clk_m);
 
 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 	/* 1 GHz */
@@ -395,78 +332,84 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_x = {
-	.name      = "pll_x",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-	.ops       = &tegra_pllx_ops,
-	.reg       = 0xe0,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_x_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
+		31000000, 1000000, 6000000, 20000000, 1200000000,
+		tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
 
 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
 	{ 12000000, 100000000,  200,  24, 1, 0 },
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_e = {
-	.name      = "pll_e",
-	.flags	   = PLL_ALT_MISC_REG,
-	.ops       = &tegra_plle_ops,
-	.parent    = &tegra_clk_m,
-	.reg       = 0xe8,
-	.max_rate  = 100000000,
-	.u.pll = {
-		.input_min = 12000000,
-		.input_max = 12000000,
-		.freq_table = tegra_pll_e_freq_table,
-	},
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
+		0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
+
+static const char *tegra_common_parent_names[] = {
+	"clk_m",
 };
 
-static struct clk tegra_clk_d = {
-	.name      = "clk_d",
-	.flags     = PERIPH_NO_RESET,
-	.ops       = &tegra_clk_double_ops,
-	.reg       = 0x34,
+static struct clk *tegra_common_parents[] = {
+	&tegra_clk_m,
+};
+
+static struct clk tegra_clk_d;
+static struct clk_tegra tegra_clk_d_hw = {
+	.hw = {
+		.clk = &tegra_clk_d,
+	},
+	.flags = PERIPH_NO_RESET,
+	.reg = 0x34,
 	.reg_shift = 12,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 52000000,
-	.u.periph  = {
+	.max_rate = 52000000,
+	.u.periph = {
 		.clk_num = 90,
 	},
 };
 
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
-	.name      = "cdev1",
-	.ops       = &tegra_cdev_clk_ops,
-	.rate      = 26000000,
-	.max_rate  = 26000000,
-	.u.periph  = {
+static struct clk tegra_clk_d = {
+	.name = "clk_d",
+	.hw = &tegra_clk_d_hw.hw,
+	.ops = &tegra_clk_double_ops,
+	.parent = &tegra_clk_m,
+	.parent_names = tegra_common_parent_names,
+	.parents = tegra_common_parents,
+	.num_parents = ARRAY_SIZE(tegra_common_parent_names),
+};
+
+static struct clk tegra_cdev1;
+static struct clk_tegra tegra_cdev1_hw = {
+	.hw = {
+		.clk = &tegra_cdev1,
+	},
+	.fixed_rate = 26000000,
+	.u.periph = {
 		.clk_num = 94,
 	},
 };
+static struct clk tegra_cdev1 = {
+	.name = "cdev1",
+	.hw = &tegra_cdev1_hw.hw,
+	.ops = &tegra_cdev_clk_ops,
+	.flags = CLK_IS_ROOT,
+};
 
 /* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
-	.name      = "cdev2",
-	.ops       = &tegra_cdev_clk_ops,
-	.rate      = 26000000,
-	.max_rate  = 26000000,
-	.u.periph  = {
-		.clk_num   = 93,
+static struct clk tegra_cdev2;
+static struct clk_tegra tegra_cdev2_hw = {
+	.hw = {
+		.clk = &tegra_cdev2,
+	},
+	.fixed_rate = 26000000,
+	.u.periph = {
+		.clk_num  = 93,
 	},
 };
+static struct clk tegra_cdev2 = {
+	.name = "cdev2",
+	.hw = &tegra_cdev2_hw.hw,
+	.ops = &tegra_cdev_clk_ops,
+	.flags = CLK_IS_ROOT,
+};
 
 /* initialized before peripheral clocks */
 static struct clk_mux_sel mux_audio_sync_clk[8+1];
@@ -487,30 +430,66 @@ static const struct audio_sources {
 	{ NULL, 0 }
 };
 
-static struct clk tegra_clk_audio = {
-	.name      = "audio",
-	.inputs    = mux_audio_sync_clk,
-	.reg       = 0x38,
-	.max_rate  = 73728000,
-	.ops       = &tegra_audio_sync_clk_ops
+static const char *audio_parent_names[] = {
+	"spdif_in",
+	"i2s1",
+	"i2s2",
+	"dummy",
+	"pll_a_out0",
+	"dummy",
+	"dummy",
+	"dummy",
+};
+
+static struct clk *audio_parents[] = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+};
+
+static struct clk tegra_audio;
+static struct clk_tegra tegra_audio_hw = {
+	.hw = {
+		.clk = &tegra_audio,
+	},
+	.reg = 0x38,
+	.max_rate = 73728000,
+};
+DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
+		audio_parents, NULL);
+
+static const char *audio_2x_parent_names[] = {
+	"audio",
 };
 
-static struct clk tegra_clk_audio_2x = {
-	.name      = "audio_2x",
-	.flags     = PERIPH_NO_RESET,
-	.max_rate  = 48000000,
-	.ops       = &tegra_clk_double_ops,
-	.reg       = 0x34,
+static struct clk *audio_2x_parents[] = {
+	&tegra_audio,
+};
+
+static struct clk tegra_audio_2x;
+static struct clk_tegra tegra_audio_2x_hw = {
+	.hw = {
+		.clk = &tegra_audio_2x,
+	},
+	.flags = PERIPH_NO_RESET,
+	.max_rate = 48000000,
+	.reg = 0x34,
 	.reg_shift = 8,
-	.parent    = &tegra_clk_audio,
 	.u.periph = {
 		.clk_num = 89,
 	},
 };
+DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
+		audio_2x_parents, &tegra_audio);
 
 static struct clk_lookup tegra_audio_clk_lookups[] = {
-	{ .con_id = "audio", .clk = &tegra_clk_audio },
-	{ .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
+	{ .con_id = "audio", .clk = &tegra_audio },
+	{ .con_id = "audio_2x", .clk = &tegra_audio_2x }
 };
 
 /* This is called after peripheral clocks are initialized, as the
@@ -529,315 +508,501 @@ static void init_audio_sync_clock_mux(void)
 		if (!sel->input)
 			pr_err("%s: could not find clk %s\n", __func__,
 				src->name);
+		audio_parents[src->value] = sel->input;
 		sel->value = src->value;
 	}
 
 	lookup = tegra_audio_clk_lookups;
 	for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-		clk_init(lookup->clk);
-		clkdev_add(lookup);
+		struct clk *c = lookup->clk;
+		struct clk_tegra *clk = to_clk_tegra(c->hw);
+		__clk_init(NULL, c);
+		INIT_LIST_HEAD(&clk->shared_bus_list);
+		clk->lookup.con_id = lookup->con_id;
+		clk->lookup.clk = c;
+		clkdev_add(&clk->lookup);
+		tegra_clk_add(c);
 	}
 }
 
-static struct clk_mux_sel mux_cclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c,	.value = 1},
-	{ .input = &tegra_clk_32k,	.value = 2},
-	{ .input = &tegra_pll_m,	.value = 3},
-	{ .input = &tegra_pll_p,	.value = 4},
-	{ .input = &tegra_pll_p_out4,	.value = 5},
-	{ .input = &tegra_pll_p_out3,	.value = 6},
-	{ .input = &tegra_clk_d,	.value = 7},
-	{ .input = &tegra_pll_x,	.value = 8},
-	{ NULL, 0},
-};
-
-static struct clk_mux_sel mux_sclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c_out1,	.value = 1},
-	{ .input = &tegra_pll_p_out4,	.value = 2},
-	{ .input = &tegra_pll_p_out3,	.value = 3},
-	{ .input = &tegra_pll_p_out2,	.value = 4},
-	{ .input = &tegra_clk_d,	.value = 5},
-	{ .input = &tegra_clk_32k,	.value = 6},
-	{ .input = &tegra_pll_m_out1,	.value = 7},
-	{ NULL, 0},
-};
-
-static struct clk tegra_clk_cclk = {
-	.name	= "cclk",
-	.inputs	= mux_cclk,
-	.reg	= 0x20,
-	.ops	= &tegra_super_ops,
+static const char *mux_cclk[] = {
+	"clk_m",
+	"pll_c",
+	"clk_32k",
+	"pll_m",
+	"pll_p",
+	"pll_p_out4",
+	"pll_p_out3",
+	"clk_d",
+	"pll_x",
+};
+
+
+static struct clk *mux_cclk_p[] = {
+	&tegra_clk_m,
+	&tegra_pll_c,
+	&tegra_clk_32k,
+	&tegra_pll_m,
+	&tegra_pll_p,
+	&tegra_pll_p_out4,
+	&tegra_pll_p_out3,
+	&tegra_clk_d,
+	&tegra_pll_x,
+};
+
+static const char *mux_sclk[] = {
+	"clk_m",
+	"pll_c_out1",
+	"pll_p_out4",
+	"pllp_p_out3",
+	"pll_p_out2",
+	"clk_d",
+	"clk_32k",
+	"pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+	&tegra_clk_m,
+	&tegra_pll_c_out1,
+	&tegra_pll_p_out4,
+	&tegra_pll_p_out3,
+	&tegra_pll_p_out2,
+	&tegra_clk_d,
+	&tegra_clk_32k,
+	&tegra_pll_m_out1,
+};
+
+static struct clk tegra_cclk;
+static struct clk_tegra tegra_cclk_hw = {
+	.hw = {
+		.clk = &tegra_cclk,
+	},
+	.reg = 0x20,
 	.max_rate = 1000000000,
 };
+DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
+		mux_cclk_p, NULL);
 
-static struct clk tegra_clk_sclk = {
-	.name	= "sclk",
-	.inputs	= mux_sclk,
-	.reg	= 0x28,
-	.ops	= &tegra_super_ops,
+static struct clk tegra_sclk;
+static struct clk_tegra tegra_sclk_hw = {
+	.hw = {
+		.clk = &tegra_sclk,
+	},
+	.reg = 0x28,
 	.max_rate = 240000000,
 	.min_rate = 120000000,
 };
+DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
+		mux_sclk_p, NULL);
 
-static struct clk tegra_clk_virtual_cpu = {
-	.name      = "cpu",
-	.parent    = &tegra_clk_cclk,
-	.ops       = &tegra_cpu_ops,
-	.max_rate  = 1000000000,
-	.u.cpu = {
-		.main      = &tegra_pll_x,
-		.backup    = &tegra_pll_p,
-	},
+static const char *tegra_cop_parent_names[] = {
+	"tegra_sclk",
+};
+
+static struct clk *tegra_cop_parents[] = {
+	&tegra_sclk,
 };
 
-static struct clk tegra_clk_cop = {
-	.name      = "cop",
-	.parent    = &tegra_clk_sclk,
-	.ops       = &tegra_cop_ops,
+static struct clk tegra_cop;
+static struct clk_tegra tegra_cop_hw = {
+	.hw = {
+		.clk = &tegra_cop,
+	},
 	.max_rate  = 240000000,
+	.reset = &tegra2_cop_clk_reset,
+};
+DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
+		tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
+
+static const char *tegra_hclk_parent_names[] = {
+	"tegra_sclk",
+};
+
+static struct clk *tegra_hclk_parents[] = {
+	&tegra_sclk,
 };
 
-static struct clk tegra_clk_hclk = {
-	.name		= "hclk",
-	.flags		= DIV_BUS,
-	.parent		= &tegra_clk_sclk,
-	.reg		= 0x30,
-	.reg_shift	= 4,
-	.ops		= &tegra_bus_ops,
-	.max_rate       = 240000000,
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+	.hw = {
+		.clk = &tegra_hclk,
+	},
+	.flags = DIV_BUS,
+	.reg = 0x30,
+	.reg_shift = 4,
+	.max_rate = 240000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
+		tegra_hclk_parents, &tegra_sclk);
+
+static const char *tegra_pclk_parent_names[] = {
+	"tegra_hclk",
 };
 
-static struct clk tegra_clk_pclk = {
-	.name		= "pclk",
-	.flags		= DIV_BUS,
-	.parent		= &tegra_clk_hclk,
-	.reg		= 0x30,
-	.reg_shift	= 0,
-	.ops		= &tegra_bus_ops,
-	.max_rate       = 120000000,
+static struct clk *tegra_pclk_parents[] = {
+	&tegra_hclk,
 };
 
-static struct clk tegra_clk_blink = {
-	.name		= "blink",
-	.parent		= &tegra_clk_32k,
-	.reg		= 0x40,
-	.ops		= &tegra_blink_clk_ops,
-	.max_rate	= 32768,
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+	.hw = {
+		.clk = &tegra_pclk,
+	},
+	.flags = DIV_BUS,
+	.reg = 0x30,
+	.reg_shift = 0,
+	.max_rate = 120000000,
 };
+DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
+		tegra_pclk_parents, &tegra_hclk);
 
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_pll_a_out0, .value = 3},
-	{ NULL, 0},
+static const char *tegra_blink_parent_names[] = {
+	"clk_32k",
 };
 
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
+static struct clk *tegra_blink_parents[] = {
+	&tegra_clk_32k,
 };
 
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_m, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
+static struct clk tegra_blink;
+static struct clk_tegra tegra_blink_hw = {
+	.hw = {
+		.clk = &tegra_blink,
+	},
+	.reg = 0x40,
+	.max_rate = 32768,
+};
+DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
+		tegra_blink_parents, &tegra_clk_32k);
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+	"pll_m",
+	"pll_c",
+	"pll_p",
+	"pll_a_out0",
 };
 
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
-	{.input = &tegra_pll_a_out0, .value = 0},
-	{.input = &tegra_clk_audio_2x, .value = 1},
-	{.input = &tegra_pll_p, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+	&tegra_pll_m,
+	&tegra_pll_c,
+	&tegra_pll_p,
+	&tegra_pll_a_out0,
 };
 
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_d_out0, .value = 1},
-	{.input = &tegra_pll_c, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ NULL, 0},
+static const char *mux_pllm_pllc_pllp_clkm[] = {
+	"pll_m",
+	"pll_c",
+	"pll_p",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_audio,     .value = 2},
-	{.input = &tegra_clk_m,     .value = 3},
-	{.input = &tegra_clk_32k,   .value = 4},
-	{ NULL, 0},
+static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
+	&tegra_pll_m,
+	&tegra_pll_c,
+	&tegra_pll_p,
+	&tegra_clk_m,
 };
 
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_pll_m,     .value = 2},
-	{ NULL, 0},
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+	"pll_p",
+	"pll_c",
+	"pll_m",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_clk_m[] = {
-	{ .input = &tegra_clk_m, .value = 0},
-	{ NULL, 0},
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_pll_m,
+	&tegra_clk_m,
 };
 
-static struct clk_mux_sel mux_pllp_out3[] = {
-	{ .input = &tegra_pll_p_out3, .value = 0},
-	{ NULL, 0},
+static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
+	"pll_a_out0",
+	"audio_2x",
+	"pll_p",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_plld[] = {
-	{ .input = &tegra_pll_d, .value = 0},
-	{ NULL, 0},
+static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
+	&tegra_pll_a_out0,
+	&tegra_audio_2x,
+	&tegra_pll_p,
+	&tegra_clk_m,
 };
 
-static struct clk_mux_sel mux_clk_32k[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ NULL, 0},
+static const char *mux_pllp_plld_pllc_clkm[] = {
+	"pllp",
+	"pll_d_out0",
+	"pll_c",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pclk[] = {
-	{ .input = &tegra_clk_pclk, .value = 0},
-	{ NULL, 0},
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_d_out0,
+	&tegra_pll_c,
+	&tegra_clk_m,
 };
 
-static struct clk tegra_clk_emc = {
-	.name = "emc",
-	.ops = &tegra_emc_clk_ops,
+static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
+	"pll_p",
+	"pll_c",
+	"audio",
+	"clk_m",
+	"clk_32k",
+};
+
+static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_audio,
+	&tegra_clk_m,
+	&tegra_clk_32k,
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+	"pll_p",
+	"pll_c",
+	"pll_m"
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_pll_m,
+};
+
+static const char *mux_clk_m[] = {
+	"clk_m",
+};
+
+static struct clk *mux_clk_m_p[] = {
+	&tegra_clk_m,
+};
+
+static const char *mux_pllp_out3[] = {
+	"pll_p_out3",
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+	&tegra_pll_p_out3,
+};
+
+static const char *mux_plld[] = {
+	"pll_d",
+};
+
+static struct clk *mux_plld_p[] = {
+	&tegra_pll_d,
+};
+
+static const char *mux_clk_32k[] = {
+	"clk_32k",
+};
+
+static struct clk *mux_clk_32k_p[] = {
+	&tegra_clk_32k,
+};
+
+static const char *mux_pclk[] = {
+	"pclk",
+};
+
+static struct clk *mux_pclk_p[] = {
+	&tegra_pclk,
+};
+
+static struct clk tegra_emc;
+static struct clk_tegra tegra_emc_hw = {
+	.hw = {
+		.clk = &tegra_emc,
+	},
 	.reg = 0x19c,
 	.max_rate = 800000000,
-	.inputs = mux_pllm_pllc_pllp_clkm,
 	.flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+	.reset = &tegra2_periph_clk_reset,
 	.u.periph = {
 		.clk_num = 57,
 	},
 };
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
+DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
+		mux_pllm_pllc_pllp_clkm_p, NULL);
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,	\
+		_max, _inputs, _flags) 			\
+	static struct clk tegra_##_name;		\
+	static struct clk_tegra tegra_##_name##_hw = {	\
+		.hw = {					\
+			.clk = &tegra_##_name,		\
 		},					\
-		.ops       = &tegra_periph_clk_ops,	\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
+		.lookup = {				\
+			.dev_id = _dev,			\
+			.con_id = _con,			\
 		},					\
-	}
-
-#define SHARED_CLK(_name, _dev, _con, _parent)		\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id    = _con,		\
+		.reg = _reg,				\
+		.flags = _flags,			\
+		.max_rate = _max,			\
+		.u.periph = {				\
+			.clk_num = _clk_num,		\
 		},					\
-		.ops       = &tegra_clk_shared_bus_ops,	\
-		.parent = _parent,			\
-	}
+		.reset = tegra2_periph_clk_reset,	\
+	};						\
+	static struct clk tegra_##_name = {		\
+		.name = #_name,				\
+		.ops = &tegra_periph_clk_ops,		\
+		.hw = &tegra_##_name##_hw.hw,		\
+		.parent_names = _inputs,		\
+		.parents = _inputs##_p,			\
+		.num_parents = ARRAY_SIZE(_inputs),	\
+	};
+
+PERIPH_CLK(apbdma,	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0);
+PERIPH_CLK(rtc,		"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET);
+PERIPH_CLK(timer,	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(i2s1,	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(i2s2,	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(spdif_out,	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(spdif_in,	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71);
+PERIPH_CLK(pwm,		"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM);
+PERIPH_CLK(spi,		"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(xio,		"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(twc,		"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sbc1,	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sbc2,	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sbc3,	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sbc4,	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(ide,		"ide",			NULL,	25,	0x144,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(ndflash,	"tegra_nand",		NULL,	13,	0x160,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vfir,	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sdmmc1,	"sdhci-tegra.0",	NULL,	14,	0x150,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,		"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(bsea,	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(bsev,	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(vde,		"tegra-avp",		"vde",	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(csite,	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* max rate ??? */
+/* FIXME: what is la? */
+PERIPH_CLK(la,		"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(owr,		"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(nor,		"nor",			NULL,	42,	0x1d0,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(i2c1,	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16);
+PERIPH_CLK(i2c2,	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16);
+PERIPH_CLK(i2c3,	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16);
+PERIPH_CLK(dvc,		"tegra-i2c.3",		NULL,	47,	0x128,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16);
+PERIPH_CLK(i2c1_i2c,	"tegra-i2c.0",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0);
+PERIPH_CLK(i2c2_i2c,	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0);
+PERIPH_CLK(i2c3_i2c,	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0);
+PERIPH_CLK(dvc_i2c,	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0);
+PERIPH_CLK(uarta,	"tegra-uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX);
+PERIPH_CLK(uartb,	"tegra-uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX);
+PERIPH_CLK(uartc,	"tegra-uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX);
+PERIPH_CLK(uartd,	"tegra-uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX);
+PERIPH_CLK(uarte,	"tegra-uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX);
+PERIPH_CLK(3d,		"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(2d,		"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi,		"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi_sensor,	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(epp,		"epp",			NULL,	19,	0x16c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(mpe,		"mpe",			NULL,	60,	0x170,	250000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(host1x,	"host1x",		NULL,	28,	0x180,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(cve,		"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,		"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(hdmi,	"hdmi",			NULL,	51,	0x18c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvdac,	"tvdac",		NULL,	53,	0x194,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_plld_pllc_clkm,	MUX); /* scales with voltage and process_id */
+PERIPH_CLK(disp2,	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_plld_pllc_clkm,	MUX); /* scales with voltage and process_id */
+PERIPH_CLK(usbd,	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(usb2,	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(usb3,	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(dsi,		"dsi",			NULL,	48,	0,	500000000, mux_plld,			0); /* scales with voltage */
+PERIPH_CLK(csi,		"tegra_camera",		"csi",	52,	0,	72000000,  mux_pllp_out3,		0);
+PERIPH_CLK(isp,		"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0); /* same frequency as VI */
+PERIPH_CLK(csus,	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET);
+PERIPH_CLK(pex,		NULL,			"pex",  70,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET);
+PERIPH_CLK(afi,		NULL,			"afi",  72,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET);
+PERIPH_CLK(pcie_xclk,	NULL,		  "pcie_xclk",  74,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET);
+
+static struct clk *tegra_list_clks[] = {
+	&tegra_apbdma,
+	&tegra_rtc,
+	&tegra_timer,
+	&tegra_i2s1,
+	&tegra_i2s2,
+	&tegra_spdif_out,
+	&tegra_spdif_in,
+	&tegra_pwm,
+	&tegra_spi,
+	&tegra_xio,
+	&tegra_twc,
+	&tegra_sbc1,
+	&tegra_sbc2,
+	&tegra_sbc3,
+	&tegra_sbc4,
+	&tegra_ide,
+	&tegra_ndflash,
+	&tegra_vfir,
+	&tegra_sdmmc1,
+	&tegra_sdmmc2,
+	&tegra_sdmmc3,
+	&tegra_sdmmc4,
+	&tegra_vcp,
+	&tegra_bsea,
+	&tegra_bsev,
+	&tegra_vde,
+	&tegra_csite,
+	&tegra_la,
+	&tegra_owr,
+	&tegra_nor,
+	&tegra_mipi,
+	&tegra_i2c1,
+	&tegra_i2c2,
+	&tegra_i2c3,
+	&tegra_dvc,
+	&tegra_i2c1_i2c,
+	&tegra_i2c2_i2c,
+	&tegra_i2c3_i2c,
+	&tegra_dvc_i2c,
+	&tegra_uarta,
+	&tegra_uartb,
+	&tegra_uartc,
+	&tegra_uartd,
+	&tegra_uarte,
+	&tegra_3d,
+	&tegra_2d,
+	&tegra_vi,
+	&tegra_vi_sensor,
+	&tegra_epp,
+	&tegra_mpe,
+	&tegra_host1x,
+	&tegra_cve,
+	&tegra_tvo,
+	&tegra_hdmi,
+	&tegra_tvdac,
+	&tegra_disp1,
+	&tegra_disp2,
+	&tegra_usbd,
+	&tegra_usb2,
+	&tegra_usb3,
+	&tegra_dsi,
+	&tegra_csi,
+	&tegra_isp,
+	&tegra_csus,
+	&tegra_pex,
+	&tegra_afi,
+	&tegra_pcie_xclk,
+};
 
-static struct clk tegra_list_clks[] = {
-	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0),
-	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET),
-	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("i2s1",	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("i2s2",	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
-	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("vde",	"tegra-avp",		"vde",	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
-	/* FIXME: what is la? */
-	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	250000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
-	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_plld_pllc_clkm,	MUX), /* scales with voltage and process_id */
-	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	500000000, mux_plld,			0), /* scales with voltage */
-	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	72000000,  mux_pllp_out3,		0),
-	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
-	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
-	PERIPH_CLK("pex",       NULL,			"pex",  70,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-	PERIPH_CLK("afi",       NULL,			"afi",  72,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-	PERIPH_CLK("pcie_xclk", NULL,		  "pcie_xclk",  74,     0,	26000000,  mux_clk_m,			PERIPH_MANUAL_RESET),
-
-	SHARED_CLK("avp.sclk",	"tegra-avp",		"sclk",	&tegra_clk_sclk),
-	SHARED_CLK("avp.emc",	"tegra-avp",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("cpu.emc",	"cpu",			"emc",	&tegra_clk_emc),
-	SHARED_CLK("disp1.emc",	"tegradc.0",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("disp2.emc",	"tegradc.1",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("hdmi.emc",	"hdmi",			"emc",	&tegra_clk_emc),
-	SHARED_CLK("host.emc",	"tegra_grhost",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usbd.emc",	"fsl-tegra-udc",	"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb1.emc",	"tegra-ehci.0",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb2.emc",	"tegra-ehci.1",		"emc",	&tegra_clk_emc),
-	SHARED_CLK("usb3.emc",	"tegra-ehci.2",		"emc",	&tegra_clk_emc),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)		\
-	{						\
-		.name	= _name,			\
-		.lookup	= {				\
-			.dev_id	= _dev,			\
-			.con_id		= _con,		\
-		},					\
+#define CLK_DUPLICATE(_name, _dev, _con)	\
+	{					\
+		.name	= _name,		\
+		.lookup	= {			\
+			.dev_id	= _dev,		\
+			.con_id	= _con,		\
+		},				\
 	}
 
 /* Some clocks may be used by different drivers depending on the board
@@ -850,25 +1015,26 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("uartc",	"serial8250.2",	NULL),
 	CLK_DUPLICATE("uartd",	"serial8250.3",	NULL),
 	CLK_DUPLICATE("uarte",	"serial8250.4",	NULL),
-	CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
-	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
-	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-	CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
-	CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
-	CLK_DUPLICATE("cop", "tegra-avp", "cop"),
-	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
+	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
+	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
+	CLK_DUPLICATE("hdmi",	"tegradc.0",	"hdmi"),
+	CLK_DUPLICATE("hdmi",	"tegradc.1",	"hdmi"),
+	CLK_DUPLICATE("host1x",	"tegra_grhost",	"host1x"),
+	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
+	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
+	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
+	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
+	CLK_DUPLICATE("cop",	"tegra-avp",	"cop"),
+	CLK_DUPLICATE("vde",	"tegra-aes",	"vde"),
+	CLK_DUPLICATE("cclk",	NULL,		"cpu"),
 };
 
 #define CLK(dev, con, ck)	\
 	{			\
-		.dev_id = dev,	\
-		.con_id = con,	\
-		.clk = ck,	\
+		.dev_id	= dev,	\
+		.con_id	= con,	\
+		.clk	= ck,	\
 	}
 
 static struct clk *tegra_ptr_clks[] = {
@@ -891,27 +1057,33 @@ static struct clk *tegra_ptr_clks[] = {
 	&tegra_pll_u,
 	&tegra_pll_x,
 	&tegra_pll_e,
-	&tegra_clk_cclk,
-	&tegra_clk_sclk,
-	&tegra_clk_hclk,
-	&tegra_clk_pclk,
+	&tegra_cclk,
+	&tegra_sclk,
+	&tegra_hclk,
+	&tegra_pclk,
 	&tegra_clk_d,
-	&tegra_clk_cdev1,
-	&tegra_clk_cdev2,
-	&tegra_clk_virtual_cpu,
-	&tegra_clk_blink,
-	&tegra_clk_cop,
-	&tegra_clk_emc,
+	&tegra_cdev1,
+	&tegra_cdev2,
+	&tegra_blink,
+	&tegra_cop,
+	&tegra_emc,
 };
 
 static void tegra2_init_one_clock(struct clk *c)
 {
-	clk_init(c);
-	INIT_LIST_HEAD(&c->shared_bus_list);
-	if (!c->lookup.dev_id && !c->lookup.con_id)
-		c->lookup.con_id = c->name;
-	c->lookup.clk = c;
-	clkdev_add(&c->lookup);
+	struct clk_tegra *clk = to_clk_tegra(c->hw);
+	int ret;
+
+	ret = __clk_init(NULL, c);
+	if (ret)
+		pr_err("clk init failed %s\n", __clk_get_name(c));
+
+	INIT_LIST_HEAD(&clk->shared_bus_list);
+	if (!clk->lookup.dev_id && !clk->lookup.con_id)
+		clk->lookup.con_id = c->name;
+	clk->lookup.clk = c;
+	clkdev_add(&clk->lookup);
+	tegra_clk_add(c);
 }
 
 void __init tegra2_init_clocks(void)
@@ -923,7 +1095,7 @@ void __init tegra2_init_clocks(void)
 		tegra2_init_one_clock(tegra_ptr_clks[i]);
 
 	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-		tegra2_init_one_clock(&tegra_list_clks[i]);
+		tegra2_init_one_clock(tegra_list_clks[i]);
 
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
 		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 645ef69..a9fa8ea 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -381,14 +381,16 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 		udelay(2);						\
 	} while (0)
 
-
-static inline int clk_set_div(struct clk *c, u32 n)
+static inline int clk_set_div(struct clk_tegra *c, u32 n)
 {
-	return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+	struct clk *clk = c->hw.clk;
+
+	return clk_set_rate(clk,
+			(__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
 }
 
 static inline u32 periph_clk_to_reg(
-	struct clk *c, u32 reg_L, u32 reg_V, int offs)
+	struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
 {
 	u32 reg = c->u.periph.clk_num / 32;
 	BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +472,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
 	return divider_u16 - 1;
 }
 
+static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
 /* clk_m functions */
-static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	if (!to_clk_tegra(hw)->fixed_rate)
+		to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+	return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra30_clk_m_init(struct clk_hw *hw)
 {
 	u32 osc_ctrl = clk_readl(OSC_CTRL);
 	u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
 	u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 
-	c->rate = clk_measure_input_freq();
-	switch (c->rate) {
+	switch (to_clk_tegra(hw)->fixed_rate) {
 	case 12000000:
 		auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +527,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
 		break;
 	default:
-		pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+		pr_err("%s: Unexpected clock rate %ld", __func__,
+				to_clk_tegra(hw)->fixed_rate);
 		BUG();
 	}
 	clk_writel(auto_clock_control, OSC_CTRL);
-	return c->rate;
 }
 
-static void tegra30_clk_m_init(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	tegra30_clk_m_autodetect_rate(c);
-}
+struct clk_ops tegra30_clk_m_ops = {
+	.init = tegra30_clk_m_init,
+	.recalc_rate = tegra30_clk_m_recalc_rate,
+};
 
-static int tegra30_clk_m_enable(struct clk *c)
+static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
 {
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	return 0;
-}
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
 
-static void tegra30_clk_m_disable(struct clk *c)
-{
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	WARN(1, "Attempting to disable main SoC clock\n");
-}
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
 
-struct clk_ops tegra30_clk_m_ops = {
-	.init		= tegra30_clk_m_init,
-	.enable		= tegra30_clk_m_enable,
-	.disable	= tegra30_clk_m_disable,
-};
+	return rate;
+}
 
 struct clk_ops tegra_clk_m_div_ops = {
-	.enable		= tegra30_clk_m_enable,
+	.recalc_rate = tegra30_clk_m_div_recalc_rate,
 };
 
 /* PLL reference divider functions */
-static void tegra30_pll_ref_init(struct clk *c)
+static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
+			unsigned long parent_rate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long rate = parent_rate;
 	u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
-	pr_debug("%s on clock %s\n", __func__, c->name);
 
 	switch (pll_ref_div) {
 	case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +581,18 @@ static void tegra30_pll_ref_init(struct clk *c)
 		BUG();
 	}
 	c->mul = 1;
-	c->state = ON;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
 }
 
 struct clk_ops tegra_pll_ref_ops = {
-	.init		= tegra30_pll_ref_init,
-	.enable		= tegra30_clk_m_enable,
-	.disable	= tegra30_clk_m_disable,
+	.recalc_rate = tegra30_pll_ref_recalc_rate,
 };
 
 /* super clock functions */
@@ -581,56 +603,50 @@ struct clk_ops tegra_pll_ref_ops = {
  * only when its parent is a fixed rate PLL, since we can't change PLL rate
  * in this case.
  */
-static void tegra30_super_clk_init(struct clk *c)
+static void tegra30_super_clk_init(struct clk_hw *hw)
 {
-	u32 val;
-	int source;
-	int shift;
-	const struct clk_mux_sel *sel;
-	val = clk_readl(c->reg + SUPER_CLK_MUX);
-	c->state = ON;
-	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-	source = (val >> shift) & SUPER_SOURCE_MASK;
-	if (c->flags & DIV_2)
-		source |= val & SUPER_LP_DIV2_BYPASS;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->value == source)
-			break;
-	}
-	BUG_ON(sel->input == NULL);
-	c->parent = sel->input;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	struct clk_tegra *p =
+			to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
 
+	c->state = ON;
 	if (c->flags & DIV_U71) {
 		/* Init safe 7.1 divider value (does not affect PLLX path) */
 		clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
 			   c->reg + SUPER_CLK_DIVIDER);
 		c->mul = 2;
 		c->div = 2;
-		if (!(c->parent->flags & PLLX))
+		if (!(p->flags & PLLX))
 			c->div += SUPER_CLOCK_DIV_U71_MIN;
 	} else
 		clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
 }
 
-static int tegra30_super_clk_enable(struct clk *c)
+static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
 {
-	return 0;
-}
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val;
+	int source;
+	int shift;
 
-static void tegra30_super_clk_disable(struct clk *c)
-{
-	/* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
-	   geared up g-mode super clock - mode switch may request to disable
-	   either of them; accept request with no affect on h/w */
+	val = clk_readl(c->reg + SUPER_CLK_MUX);
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	source = (val >> shift) & SUPER_SOURCE_MASK;
+	if (c->flags & DIV_2)
+		source |= val & SUPER_LP_DIV2_BYPASS;
+
+	return source;
 }
 
-static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	struct clk_tegra *p =
+			to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
 	u32 val;
-	const struct clk_mux_sel *sel;
 	int shift;
 
 	val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +654,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
 		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
 	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
 		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			/* For LP mode super-clock switch between PLLX direct
-			   and divided-by-2 outputs is allowed only when other
-			   than PLLX clock source is current parent */
-			if ((c->flags & DIV_2) && (p->flags & PLLX) &&
-			    ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
-				if (c->parent->flags & PLLX)
-					return -EINVAL;
-				val ^= SUPER_LP_DIV2_BYPASS;
-				clk_writel_delay(val, c->reg);
-			}
-			val &= ~(SUPER_SOURCE_MASK << shift);
-			val |= (sel->value & SUPER_SOURCE_MASK) << shift;
-
-			/* 7.1 divider for CPU super-clock does not affect
-			   PLLX path */
-			if (c->flags & DIV_U71) {
-				u32 div = 0;
-				if (!(p->flags & PLLX)) {
-					div = clk_readl(c->reg +
-							SUPER_CLK_DIVIDER);
-					div &= SUPER_CLOCK_DIV_U71_MASK;
-					div >>= SUPER_CLOCK_DIV_U71_SHIFT;
-				}
-				c->div = div + 2;
-				c->mul = 2;
-			}
-
-			if (c->refcnt)
-				clk_enable(p);
-
-			clk_writel_delay(val, c->reg);
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+	/* For LP mode super-clock switch between PLLX direct
+	   and divided-by-2 outputs is allowed only when other
+	   than PLLX clock source is current parent */
+	if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+	    ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
+		if (p->flags & PLLX)
+			return -EINVAL;
+		val ^= SUPER_LP_DIV2_BYPASS;
+		clk_writel_delay(val, c->reg);
+	}
+	val &= ~(SUPER_SOURCE_MASK << shift);
+	val |= (index & SUPER_SOURCE_MASK) << shift;
 
-			clk_reparent(c, p);
-			return 0;
+	/* 7.1 divider for CPU super-clock does not affect
+	   PLLX path */
+	if (c->flags & DIV_U71) {
+		u32 div = 0;
+		if (!(p->flags & PLLX)) {
+			div = clk_readl(c->reg +
+					SUPER_CLK_DIVIDER);
+			div &= SUPER_CLOCK_DIV_U71_MASK;
+			div >>= SUPER_CLOCK_DIV_U71_SHIFT;
 		}
+		c->div = div + 2;
+		c->mul = 2;
 	}
-	return -EINVAL;
+	clk_writel_delay(val, c->reg);
+
+	return 0;
 }
 
 /*
@@ -691,10 +695,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
  * rate of this PLL can't be changed, and it has many other children. In
  * this case use 7.1 fractional divider to adjust the super clock rate.
  */
-static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
-		int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+	struct clk_tegra *c = to_clk_tegra(hw);
+	struct clk *parent = __clk_get_parent(hw->clk);
+	struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+
+	if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+		int div = clk_div71_get_divider(parent_rate,
 					rate, c->flags, ROUND_DIVIDER_DOWN);
 		div = max(div, SUPER_CLOCK_DIV_U71_MIN);
 
@@ -704,55 +713,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
 		c->mul = 2;
 		return 0;
 	}
-	return clk_set_rate(c->parent, rate);
+	return 0;
+}
+
+static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
+}
+
+static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	struct clk *parent = __clk_get_parent(hw->clk);
+	struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+	int mul = 2;
+	int div;
+
+	if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+		div = clk_div71_get_divider(*prate,
+				rate, c->flags, ROUND_DIVIDER_DOWN);
+		div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
+		rate = *prate * mul;
+		rate += div - 1; /* round up */
+		do_div(rate, c->div);
+
+		return rate;
+	}
+	return *prate;
 }
 
 struct clk_ops tegra30_super_ops = {
-	.init			= tegra30_super_clk_init,
-	.enable			= tegra30_super_clk_enable,
-	.disable		= tegra30_super_clk_disable,
-	.set_parent		= tegra30_super_clk_set_parent,
-	.set_rate		= tegra30_super_clk_set_rate,
+	.init = tegra30_super_clk_init,
+	.set_parent = tegra30_super_clk_set_parent,
+	.get_parent = tegra30_super_clk_get_parent,
+	.recalc_rate = tegra30_super_clk_recalc_rate,
+	.round_rate = tegra30_super_clk_round_rate,
+	.set_rate = tegra30_super_clk_set_rate,
 };
 
-static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
 {
-	/* The input value 'rate' is the clock rate of the CPU complex. */
-	c->rate = (rate * c->mul) / c->div;
-	return 0;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
 }
 
 struct clk_ops tegra30_twd_ops = {
-	.set_rate	= tegra30_twd_clk_set_rate,
+	.recalc_rate = tegra30_twd_clk_recalc_rate,
 };
 
 /* Blink output functions */
-
-static void tegra30_blink_clk_init(struct clk *c)
+static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 
 	val = pmc_readl(PMC_CTRL);
 	c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-	c->mul = 1;
-	val = pmc_readl(c->reg);
-
-	if (val & PMC_BLINK_TIMER_ENB) {
-		unsigned int on_off;
-
-		on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-			PMC_BLINK_TIMER_DATA_ON_MASK;
-		val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-		val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-		on_off += val;
-		/* each tick in the blink timer is 4 32KHz clocks */
-		c->div = on_off * 4;
-	} else {
-		c->div = 1;
-	}
+	return c->state;
 }
 
-static int tegra30_blink_clk_enable(struct clk *c)
+static int tegra30_blink_clk_enable(struct clk_hw *hw)
 {
 	u32 val;
 
@@ -765,7 +805,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra30_blink_clk_disable(struct clk *c)
+static void tegra30_blink_clk_disable(struct clk_hw *hw)
 {
 	u32 val;
 
@@ -776,9 +816,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
 	pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
 }
 
-static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
-	unsigned long parent_rate = clk_get_rate(c->parent);
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (rate >= parent_rate) {
 		c->div = 1;
 		pmc_writel(0, c->reg);
@@ -801,40 +843,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
 	return 0;
 }
 
-struct clk_ops tegra30_blink_clk_ops = {
-	.init			= &tegra30_blink_clk_init,
-	.enable			= &tegra30_blink_clk_enable,
-	.disable		= &tegra30_blink_clk_disable,
-	.set_rate		= &tegra30_blink_clk_set_rate,
-};
+static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+	u32 val;
+	u32 mul;
+	u32 div;
+	u32 on_off;
 
-/* PLL Functions */
-static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
-					 u32 lock_bit)
+	mul = 1;
+	val = pmc_readl(c->reg);
+
+	if (val & PMC_BLINK_TIMER_ENB) {
+		on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+			PMC_BLINK_TIMER_DATA_ON_MASK;
+		val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+		val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+		on_off += val;
+		/* each tick in the blink timer is 4 32KHz clocks */
+		div = on_off * 4;
+	} else {
+		div = 1;
+	}
+
+	if (mul != 0 && div != 0) {
+		rate *= mul;
+		rate += div - 1; /* round up */
+		do_div(rate, div);
+	}
+	return rate;
+}
+
+static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
-#if USE_PLL_LOCK_BITS
-	int i;
-	for (i = 0; i < c->u.pll.lock_delay; i++) {
-		if (clk_readl(lock_reg) & lock_bit) {
-			udelay(PLL_POST_LOCK_DELAY);
-			return 0;
-		}
-		udelay(2);		/* timeout = 2 * lock time */
+	int div;
+	int mul;
+	long round_rate = *prate;
+
+	mul = 1;
+
+	if (rate >= *prate) {
+		div = 1;
+	} else {
+		div = DIV_ROUND_UP(*prate / 8, rate);
+		div *= 8;
 	}
-	pr_err("Timed out waiting for lock bit on pll %s", c->name);
-	return -1;
-#endif
-	udelay(c->u.pll.lock_delay);
 
-	return 0;
+	round_rate *= mul;
+	round_rate += div - 1;
+	do_div(round_rate, div);
+
+	return round_rate;
 }
 
-static void tegra30_utmi_param_configure(struct clk *c)
+struct clk_ops tegra30_blink_clk_ops = {
+	.is_enabled = tegra30_blink_clk_is_enabled,
+	.enable = tegra30_blink_clk_enable,
+	.disable = tegra30_blink_clk_disable,
+	.recalc_rate = tegra30_blink_clk_recalc_rate,
+	.round_rate = tegra30_blink_clk_round_rate,
+	.set_rate = tegra30_blink_clk_set_rate,
+};
+
+static void tegra30_utmi_param_configure(struct clk_hw *hw)
 {
+	unsigned long main_rate =
+		__clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
 	u32 reg;
 	int i;
-	unsigned long main_rate =
-		clk_get_rate(c->parent->parent);
 
 	for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
 		if (main_rate == utmi_parameters[i].osc_frequency)
@@ -885,50 +964,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
 	clk_writel(reg, UTMIP_PLL_CFG1);
 }
 
-static void tegra30_pll_clk_init(struct clk *c)
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
+					 u32 lock_bit)
+{
+	int ret = 0;
+
+#if USE_PLL_LOCK_BITS
+	int i;
+	for (i = 0; i < c->u.pll.lock_delay; i++) {
+		if (clk_readl(lock_reg) & lock_bit) {
+			udelay(PLL_POST_LOCK_DELAY);
+			return 0;
+		}
+		udelay(2);	/* timeout = 2 * lock time */
+	}
+	pr_err("Timed out waiting for lock bit on pll %s",
+					__clk_get_name(hw->clk));
+	ret = -1;
+#else
+	udelay(c->u.pll.lock_delay);
+#endif
+	return ret;
+}
+
+static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg + PLL_BASE);
 
 	c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+	return c->state;
+}
 
-	if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-		const struct clk_pll_freq_table *sel;
-		unsigned long input_rate = clk_get_rate(c->parent);
-		for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-			if (sel->input_rate == input_rate &&
-				sel->output_rate == c->u.pll.fixed_rate) {
-				c->mul = sel->n;
-				c->div = sel->m * sel->p;
-				return;
-			}
-		}
-		pr_err("Clock %s has unknown fixed frequency\n", c->name);
-		BUG();
-	} else if (val & PLL_BASE_BYPASS) {
-		c->mul = 1;
-		c->div = 1;
-	} else {
-		c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-		c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-		if (c->flags & PLLU)
-			c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-		else
-			c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
-					PLL_BASE_DIVP_SHIFT));
-		if (c->flags & PLL_FIXED) {
-			unsigned long rate = clk_get_rate_locked(c);
-			BUG_ON(rate != c->u.pll.fixed_rate);
-		}
-	}
+static void tegra30_pll_clk_init(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
 
 	if (c->flags & PLLU)
-		tegra30_utmi_param_configure(c);
+		tegra30_utmi_param_configure(hw);
 }
 
-static int tegra30_pll_clk_enable(struct clk *c)
+static int tegra30_pll_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 #if USE_PLL_LOCK_BITS
 	val = clk_readl(c->reg + PLL_MISC(c));
@@ -951,10 +1032,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra30_pll_clk_disable(struct clk *c)
+static void tegra30_pll_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 	val = clk_readl(c->reg);
 	val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -967,36 +1049,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
 	}
 }
 
-static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val, p_div, old_base;
 	unsigned long input_rate;
 	const struct clk_pll_freq_table *sel;
 	struct clk_pll_freq_table cfg;
 
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
 	if (c->flags & PLL_FIXED) {
 		int ret = 0;
 		if (rate != c->u.pll.fixed_rate) {
 			pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-			       __func__, c->name, c->u.pll.fixed_rate, rate);
+			       __func__, __clk_get_name(hw->clk),
+				c->u.pll.fixed_rate, rate);
 			ret = -EINVAL;
 		}
 		return ret;
 	}
 
 	if (c->flags & PLLM) {
-		if (rate != clk_get_rate_locked(c)) {
+		if (rate != __clk_get_rate(hw->clk)) {
 			pr_err("%s: Can not change memory %s rate in flight\n",
-			       __func__, c->name);
+				__func__, __clk_get_name(hw->clk));
 			return -EINVAL;
 		}
-		return 0;
 	}
 
 	p_div = 0;
-	input_rate = clk_get_rate(c->parent);
+	input_rate = parent_rate;
 
 	/* Check if the target rate is tabulated */
 	for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1054,7 +1136,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
 		    (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
 		    (cfg.output_rate > c->u.pll.vco_max)) {
 			pr_err("%s: Failed to set %s out-of-table rate %lu\n",
-			       __func__, c->name, rate);
+			       __func__, __clk_get_name(hw->clk), rate);
 			return -EINVAL;
 		}
 		p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1072,7 +1154,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
 		return 0;
 
 	if (c->state == ON) {
-		tegra30_pll_clk_disable(c);
+		tegra30_pll_clk_disable(hw);
 		val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 	}
 	clk_writel(val, c->reg + PLL_BASE);
@@ -1094,87 +1176,201 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
 	}
 
 	if (c->state == ON)
-		tegra30_pll_clk_enable(c);
-
-	return 0;
-}
+		tegra30_pll_clk_enable(hw);
 
-struct clk_ops tegra30_pll_ops = {
-	.init			= tegra30_pll_clk_init,
-	.enable			= tegra30_pll_clk_enable,
-	.disable		= tegra30_pll_clk_disable,
-	.set_rate		= tegra30_pll_clk_set_rate,
-};
-
-static int
-tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
-{
-	u32 val, mask, reg;
-
-	switch (p) {
-	case TEGRA_CLK_PLLD_CSI_OUT_ENB:
-		mask = PLLD_BASE_CSI_CLKENABLE;
-		reg = c->reg + PLL_BASE;
-		break;
-	case TEGRA_CLK_PLLD_DSI_OUT_ENB:
-		mask = PLLD_MISC_DSI_CLKENABLE;
-		reg = c->reg + PLL_MISC(c);
-		break;
-	case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
-		if (!(c->flags & PLL_ALT_MISC_REG)) {
-			mask = PLLD_BASE_DSIB_MUX_MASK;
-			reg = c->reg + PLL_BASE;
-			break;
-		}
-	/* fall through - error since PLLD2 does not have MUX_SEL control */
-	default:
-		return -EINVAL;
-	}
+	c->u.pll.fixed_rate = rate;
 
-	val = clk_readl(reg);
-	if (setting)
-		val |= mask;
-	else
-		val &= ~mask;
-	clk_writel(val, reg);
 	return 0;
 }
 
-struct clk_ops tegra_plld_ops = {
-	.init			= tegra30_pll_clk_init,
-	.enable			= tegra30_pll_clk_enable,
-	.disable		= tegra30_pll_clk_disable,
-	.set_rate		= tegra30_pll_clk_set_rate,
-	.clk_cfg_ex		= tegra30_plld_clk_cfg_ex,
-};
-
-static void tegra30_plle_clk_init(struct clk *c)
+static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long input_rate = *prate;
+	unsigned long output_rate = *prate;
+	const struct clk_pll_freq_table *sel;
+	struct clk_pll_freq_table cfg;
+	int mul;
+	int div;
+	u32 p_div;
 	u32 val;
 
-	val = clk_readl(PLLE_AUX);
-	c->parent = (val & PLLE_AUX_PLLP_SEL) ?
-		tegra_get_clock_by_name("pll_p") :
-		tegra_get_clock_by_name("pll_ref");
+	if (c->flags & PLL_FIXED)
+		return c->u.pll.fixed_rate;
 
-	val = clk_readl(c->reg + PLL_BASE);
-	c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
-	c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
-	c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
-	c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
-}
+	if (c->flags & PLLM)
+		return __clk_get_rate(hw->clk);
 
-static void tegra30_plle_clk_disable(struct clk *c)
-{
-	u32 val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	p_div = 0;
+	/* Check if the target rate is tabulated */
+	for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+		if (sel->input_rate == input_rate && sel->output_rate == rate) {
+			if (c->flags & PLLU) {
+				BUG_ON(sel->p < 1 || sel->p > 2);
+				if (sel->p == 1)
+					p_div = PLLU_BASE_POST_DIV;
+			} else {
+				BUG_ON(sel->p < 1);
+				for (val = sel->p; val > 1; val >>= 1)
+					p_div++;
+				p_div <<= PLL_BASE_DIVP_SHIFT;
+			}
+			break;
+		}
+	}
 
-	val = clk_readl(c->reg + PLL_BASE);
-	val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
-	clk_writel(val, c->reg + PLL_BASE);
-}
+	if (sel->input_rate == 0) {
+		unsigned long cfreq;
+		BUG_ON(c->flags & PLLU);
+		sel = &cfg;
+
+		switch (input_rate) {
+		case 12000000:
+		case 26000000:
+			cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+			break;
+		case 13000000:
+			cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+			break;
+		case 16800000:
+		case 19200000:
+			cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+			break;
+		default:
+			pr_err("%s: Unexpected reference rate %lu\n",
+			       __func__, input_rate);
+			BUG();
+		}
+
+		/* Raise VCO to guarantee 0.5% accuracy */
+		for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+		      cfg.output_rate <<= 1)
+			p_div++;
+
+		cfg.p = 0x1 << p_div;
+		cfg.m = input_rate / cfreq;
+		cfg.n = cfg.output_rate / cfreq;
+	}
+
+	mul = sel->n;
+	div = sel->m * sel->p;
+
+	output_rate *= mul;
+	output_rate += div - 1; /* round up */
+	do_div(output_rate, div);
+
+	return output_rate;
+}
+
+static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+	u32 val = clk_readl(c->reg + PLL_BASE);
+
+	if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+		const struct clk_pll_freq_table *sel;
+		for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+			if (sel->input_rate == parent_rate &&
+				sel->output_rate == c->u.pll.fixed_rate) {
+				c->mul = sel->n;
+				c->div = sel->m * sel->p;
+				break;
+			}
+		}
+		pr_err("Clock %s has unknown fixed frequency\n",
+						__clk_get_name(hw->clk));
+		BUG();
+	} else if (val & PLL_BASE_BYPASS) {
+		c->mul = 1;
+		c->div = 1;
+	} else {
+		c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+		c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+		if (c->flags & PLLU)
+			c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+		else
+			c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+					PLL_BASE_DIVP_SHIFT));
+	}
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
+}
+
+struct clk_ops tegra30_pll_ops = {
+	.is_enabled = tegra30_pll_clk_is_enabled,
+	.init = tegra30_pll_clk_init,
+	.enable = tegra30_pll_clk_enable,
+	.disable = tegra30_pll_clk_disable,
+	.recalc_rate = tegra30_pll_recalc_rate,
+	.round_rate = tegra30_pll_round_rate,
+	.set_rate = tegra30_pll_clk_set_rate,
+};
+
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val, mask, reg;
+
+	switch (p) {
+	case TEGRA_CLK_PLLD_CSI_OUT_ENB:
+		mask = PLLD_BASE_CSI_CLKENABLE;
+		reg = c->reg + PLL_BASE;
+		break;
+	case TEGRA_CLK_PLLD_DSI_OUT_ENB:
+		mask = PLLD_MISC_DSI_CLKENABLE;
+		reg = c->reg + PLL_MISC(c);
+		break;
+	case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
+		if (!(c->flags & PLL_ALT_MISC_REG)) {
+			mask = PLLD_BASE_DSIB_MUX_MASK;
+			reg = c->reg + PLL_BASE;
+			break;
+		}
+	/* fall through - error since PLLD2 does not have MUX_SEL control */
+	default:
+		return -EINVAL;
+	}
+
+	val = clk_readl(reg);
+	if (setting)
+		val |= mask;
+	else
+		val &= ~mask;
+	clk_writel(val, reg);
+	return 0;
+}
+
+static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val;
+
+	val = clk_readl(c->reg + PLL_BASE);
+	c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
+	return c->state;
+}
+
+static void tegra30_plle_clk_disable(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val;
+
+	val = clk_readl(c->reg + PLL_BASE);
+	val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+	clk_writel(val, c->reg + PLL_BASE);
+}
 
-static void tegra30_plle_training(struct clk *c)
+static void tegra30_plle_training(struct clk_tegra *c)
 {
 	u32 val;
 
@@ -1197,12 +1393,15 @@ static void tegra30_plle_training(struct clk *c)
 	} while (!(val & PLLE_MISC_READY));
 }
 
-static int tegra30_plle_configure(struct clk *c, bool force_training)
+static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
 {
-	u32 val;
+	struct clk_tegra *c = to_clk_tegra(hw);
+	struct clk *parent = __clk_get_parent(hw->clk);
 	const struct clk_pll_freq_table *sel;
+	u32 val;
+
 	unsigned long rate = c->u.pll.fixed_rate;
-	unsigned long input_rate = clk_get_rate(c->parent);
+	unsigned long input_rate = __clk_get_rate(parent);
 
 	for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
 		if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1213,7 +1412,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
 		return -ENOSYS;
 
 	/* disable PLLE, clear setup fiels */
-	tegra30_plle_clk_disable(c);
+	tegra30_plle_clk_disable(hw);
 
 	val = clk_readl(c->reg + PLL_MISC(c));
 	val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1251,52 +1450,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
 	return 0;
 }
 
-static int tegra30_plle_clk_enable(struct clk *c)
+static int tegra30_plle_clk_enable(struct clk_hw *hw)
 {
-	pr_debug("%s on clock %s\n", __func__, c->name);
-	return tegra30_plle_configure(c, !c->set);
+	struct clk_tegra *c = to_clk_tegra(hw);
+
+	return tegra30_plle_configure(hw, !c->set);
+}
+
+static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
+			unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long rate = parent_rate;
+	u32 val;
+
+	val = clk_readl(c->reg + PLL_BASE);
+	c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+	c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+	c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+	return rate;
 }
 
 struct clk_ops tegra30_plle_ops = {
-	.init			= tegra30_plle_clk_init,
-	.enable			= tegra30_plle_clk_enable,
-	.disable		= tegra30_plle_clk_disable,
+	.is_enabled = tegra30_plle_clk_is_enabled,
+	.enable = tegra30_plle_clk_enable,
+	.disable = tegra30_plle_clk_disable,
+	.recalc_rate = tegra30_plle_clk_recalc_rate,
 };
 
 /* Clock divider ops */
-static void tegra30_pll_div_clk_init(struct clk *c)
+static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (c->flags & DIV_U71) {
-		u32 divu71;
 		u32 val = clk_readl(c->reg);
 		val >>= c->reg_shift;
 		c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
 		if (!(val & PLL_OUT_RESET_DISABLE))
 			c->state = OFF;
-
-		divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-		c->div = (divu71 + 2);
-		c->mul = 2;
-	} else if (c->flags & DIV_2) {
-		c->state = ON;
-		if (c->flags & (PLLD | PLLX)) {
-			c->div = 2;
-			c->mul = 1;
-		} else
-			BUG();
 	} else {
 		c->state = ON;
-		c->div = 1;
-		c->mul = 1;
 	}
+	return c->state;
 }
 
-static int tegra30_pll_div_clk_enable(struct clk *c)
+static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	u32 new_val;
 
-	pr_debug("%s: %s\n", __func__, c->name);
+	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
 	if (c->flags & DIV_U71) {
 		val = clk_readl(c->reg);
 		new_val = val >> c->reg_shift;
@@ -1314,12 +1525,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
 	return -EINVAL;
 }
 
-static void tegra30_pll_div_clk_disable(struct clk *c)
+static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	u32 new_val;
 
-	pr_debug("%s: %s\n", __func__, c->name);
+	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
 	if (c->flags & DIV_U71) {
 		val = clk_readl(c->reg);
 		new_val = val >> c->reg_shift;
@@ -1333,14 +1545,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
 	}
 }
 
-static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	u32 new_val;
 	int divider_u71;
-	unsigned long parent_rate = clk_get_rate(c->parent);
 
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
 	if (c->flags & DIV_U71) {
 		divider_u71 = clk_div71_get_divider(
 			parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1358,19 +1570,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
 			clk_writel_delay(val, c->reg);
 			c->div = divider_u71 + 2;
 			c->mul = 2;
+			c->fixed_rate = rate;
 			return 0;
 		}
-	} else if (c->flags & DIV_2)
-		return clk_set_rate(c->parent, rate * 2);
+	} else if (c->flags & DIV_2) {
+		c->fixed_rate = rate;
+		return 0;
+	}
 
 	return -EINVAL;
 }
 
-static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+
+	if (c->flags & DIV_U71) {
+		u32 divu71;
+		u32 val = clk_readl(c->reg);
+		val >>= c->reg_shift;
+
+		divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+		c->div = (divu71 + 2);
+		c->mul = 2;
+	} else if (c->flags & DIV_2) {
+		if (c->flags & (PLLD | PLLX)) {
+			c->div = 2;
+			c->mul = 1;
+		} else
+			BUG();
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
+				unsigned long rate, unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+	if (prate)
+		parent_rate = *prate;
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(
@@ -1378,23 +1630,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
 		if (divider < 0)
 			return divider;
 		return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-	} else if (c->flags & DIV_2)
-		/* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+	} else if (c->flags & DIV_2) {
+		*prate = rate * 2;
 		return rate;
+	}
 
 	return -EINVAL;
 }
 
 struct clk_ops tegra30_pll_div_ops = {
-	.init			= tegra30_pll_div_clk_init,
-	.enable			= tegra30_pll_div_clk_enable,
-	.disable		= tegra30_pll_div_clk_disable,
-	.set_rate		= tegra30_pll_div_clk_set_rate,
-	.round_rate		= tegra30_pll_div_clk_round_rate,
+	.is_enabled = tegra30_pll_div_clk_is_enabled,
+	.enable = tegra30_pll_div_clk_enable,
+	.disable = tegra30_pll_div_clk_disable,
+	.set_rate = tegra30_pll_div_clk_set_rate,
+	.recalc_rate = tegra30_pll_div_clk_recalc_rate,
+	.round_rate = tegra30_pll_div_clk_round_rate,
 };
 
 /* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk *c)
+static inline u32 periph_clk_source_mask(struct clk_tegra *c)
 {
 	if (c->flags & MUX8)
 		return 7 << 29;
@@ -1408,7 +1662,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
 		return 3 << 30;
 }
 
-static inline u32 periph_clk_source_shift(struct clk *c)
+static inline u32 periph_clk_source_shift(struct clk_tegra *c)
 {
 	if (c->flags & MUX8)
 		return 29;
@@ -1422,47 +1676,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
 		return 30;
 }
 
-static void tegra30_periph_clk_init(struct clk *c)
+static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
 {
-	u32 val = clk_readl(c->reg);
-	const struct clk_mux_sel *mux = 0;
-	const struct clk_mux_sel *sel;
-	if (c->flags & MUX) {
-		for (sel = c->inputs; sel->input != NULL; sel++) {
-			if (((val & periph_clk_source_mask(c)) >>
-			    periph_clk_source_shift(c)) == sel->value)
-				mux = sel;
-		}
-		BUG_ON(!mux);
-
-		c->parent = mux->input;
-	} else {
-		c->parent = c->inputs[0].input;
-	}
-
-	if (c->flags & DIV_U71) {
-		u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-		if ((c->flags & DIV_U71_UART) &&
-		    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
-			divu71 = 0;
-		}
-		if (c->flags & DIV_U71_IDLE) {
-			val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
-				PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-			val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
-				PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-			clk_writel(val, c->reg);
-		}
-		c->div = divu71 + 2;
-		c->mul = 2;
-	} else if (c->flags & DIV_U16) {
-		u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-		c->div = divu16 + 1;
-		c->mul = 1;
-	} else {
-		c->div = 1;
-		c->mul = 1;
-	}
+	struct clk_tegra *c = to_clk_tegra(hw);
 
 	c->state = ON;
 	if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1470,11 +1686,12 @@ static void tegra30_periph_clk_init(struct clk *c)
 	if (!(c->flags & PERIPH_NO_RESET))
 		if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
 			c->state = OFF;
+	return c->state;
 }
 
-static int tegra30_periph_clk_enable(struct clk *c)
+static int tegra30_periph_clk_enable(struct clk_hw *hw)
 {
-	pr_debug("%s on clock %s\n", __func__, c->name);
+	struct clk_tegra *c = to_clk_tegra(hw);
 
 	tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
 	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1493,31 +1710,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra30_periph_clk_disable(struct clk *c)
+static void tegra30_periph_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long val;
-	pr_debug("%s on clock %s\n", __func__, c->name);
 
-	if (c->refcnt)
-		tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+	tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
 
-	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
-		/* If peripheral is in the APB bus then read the APB bus to
-		 * flush the write operation in apb bus. This will avoid the
-		 * peripheral access after disabling clock*/
-		if (c->flags & PERIPH_ON_APB)
-			val = chipid_readl();
+	if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+		return;
 
-		clk_writel_delay(
-			PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-	}
+	/* If peripheral is in the APB bus then read the APB bus to
+	 * flush the write operation in apb bus. This will avoid the
+	 * peripheral access after disabling clock*/
+	if (c->flags & PERIPH_ON_APB)
+		val = chipid_readl();
+
+	clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
 }
 
-static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	unsigned long val;
-	pr_debug("%s %s on clock %s\n", __func__,
-		 assert ? "assert" : "deassert", c->name);
 
 	if (!(c->flags & PERIPH_NO_RESET)) {
 		if (assert) {
@@ -1536,42 +1751,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
 	}
 }
 
-static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	const struct clk_mux_sel *sel;
-	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
 
 	if (!(c->flags & MUX))
-		return (p == c->parent) ? 0 : (-EINVAL);
-
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			val = clk_readl(c->reg);
-			val &= ~periph_clk_source_mask(c);
-			val |= (sel->value << periph_clk_source_shift(c));
-
-			if (c->refcnt)
-				clk_enable(p);
+		return (index == 0) ? 0 : (-EINVAL);
 
-			clk_writel_delay(val, c->reg);
+	val = clk_readl(c->reg);
+	val &= ~periph_clk_source_mask(c);
+	val |= (index << periph_clk_source_shift(c));
+	clk_writel_delay(val, c->reg);
+	return 0;
+}
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg);
+	int source  = (val & periph_clk_source_mask(c)) >>
+					periph_clk_source_shift(c);
 
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
+	if (!(c->flags & MUX))
+		return 0;
 
-	return -EINVAL;
+	return source;
 }
 
-static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(
@@ -1610,12 +1823,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-static long tegra30_periph_clk_round_rate(struct clk *c,
-	unsigned long rate)
+static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
 	int divider;
-	unsigned long parent_rate = clk_get_rate(c->parent);
-	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+	if (prate)
+		parent_rate = *prate;
 
 	if (c->flags & DIV_U71) {
 		divider = clk_div71_get_divider(
@@ -1633,20 +1849,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
 	return -EINVAL;
 }
 
+static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
+	u32 val = clk_readl(c->reg);
+
+	if (c->flags & DIV_U71) {
+		u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+		if ((c->flags & DIV_U71_UART) &&
+		    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+			divu71 = 0;
+		}
+		if (c->flags & DIV_U71_IDLE) {
+			val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+				PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+			val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+				PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+			clk_writel(val, c->reg);
+		}
+		c->div = divu71 + 2;
+		c->mul = 2;
+	} else if (c->flags & DIV_U16) {
+		u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+		c->div = divu16 + 1;
+		c->mul = 1;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+	return rate;
+}
+
 struct clk_ops tegra30_periph_clk_ops = {
-	.init			= &tegra30_periph_clk_init,
+	.is_enabled = tegra30_periph_clk_is_enabled,
+	.enable = tegra30_periph_clk_enable,
+	.disable = tegra30_periph_clk_disable,
+	.set_parent = tegra30_periph_clk_set_parent,
+	.get_parent = tegra30_periph_clk_get_parent,
+	.set_rate = tegra30_periph_clk_set_rate,
+	.round_rate = tegra30_periph_clk_round_rate,
+	.recalc_rate = tegra30_periph_clk_recalc_rate,
+};
+
+static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk *d = clk_get_sys(NULL, "pll_d");
+	/* The DSIB parent selection bit is in PLLD base
+	   register - can not do direct r-m-w, must be
+	   protected by PLLD lock */
+	tegra_clk_cfg_ex(
+		d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
+
+	return 0;
+}
+
+struct clk_ops tegra30_dsib_clk_ops = {
+	.is_enabled = tegra30_periph_clk_is_enabled,
 	.enable			= &tegra30_periph_clk_enable,
 	.disable		= &tegra30_periph_clk_disable,
-	.set_parent		= &tegra30_periph_clk_set_parent,
+	.set_parent		= &tegra30_dsib_clk_set_parent,
+	.get_parent		= &tegra30_periph_clk_get_parent,
 	.set_rate		= &tegra30_periph_clk_set_rate,
 	.round_rate		= &tegra30_periph_clk_round_rate,
-	.reset			= &tegra30_periph_clk_reset,
+	.recalc_rate		= &tegra30_periph_clk_recalc_rate,
 };
 
 /* Periph extended clock configuration ops */
-static int
-tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (p == TEGRA_CLK_VI_INP_SEL) {
 		u32 val = clk_readl(c->reg);
 		val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1658,20 +1939,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-struct clk_ops tegra_vi_clk_ops = {
-	.init			= &tegra30_periph_clk_init,
-	.enable			= &tegra30_periph_clk_enable,
-	.disable		= &tegra30_periph_clk_disable,
-	.set_parent		= &tegra30_periph_clk_set_parent,
-	.set_rate		= &tegra30_periph_clk_set_rate,
-	.round_rate		= &tegra30_periph_clk_round_rate,
-	.clk_cfg_ex		= &tegra30_vi_clk_cfg_ex,
-	.reset			= &tegra30_periph_clk_reset,
-};
-
-static int
-tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
 		u32 val = clk_readl(c->reg);
 		if (setting)
@@ -1684,20 +1956,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-struct clk_ops tegra_nand_clk_ops = {
-	.init			= &tegra30_periph_clk_init,
-	.enable			= &tegra30_periph_clk_enable,
-	.disable		= &tegra30_periph_clk_disable,
-	.set_parent		= &tegra30_periph_clk_set_parent,
-	.set_rate		= &tegra30_periph_clk_set_rate,
-	.round_rate		= &tegra30_periph_clk_round_rate,
-	.clk_cfg_ex		= &tegra30_nand_clk_cfg_ex,
-	.reset			= &tegra30_periph_clk_reset,
-};
-
-static int
-tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	if (p == TEGRA_CLK_DTV_INVERT) {
 		u32 val = clk_readl(c->reg);
 		if (setting)
@@ -1710,91 +1973,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 	return -EINVAL;
 }
 
-struct clk_ops tegra_dtv_clk_ops = {
-	.init			= &tegra30_periph_clk_init,
-	.enable			= &tegra30_periph_clk_enable,
-	.disable		= &tegra30_periph_clk_disable,
-	.set_parent		= &tegra30_periph_clk_set_parent,
-	.set_rate		= &tegra30_periph_clk_set_rate,
-	.round_rate		= &tegra30_periph_clk_round_rate,
-	.clk_cfg_ex		= &tegra30_dtv_clk_cfg_ex,
-	.reset			= &tegra30_periph_clk_reset,
-};
-
-static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
-{
-	const struct clk_mux_sel *sel;
-	struct clk *d = tegra_get_clock_by_name("pll_d");
-
-	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			if (c->refcnt)
-				clk_enable(p);
-
-			/* The DSIB parent selection bit is in PLLD base
-			   register - can not do direct r-m-w, must be
-			   protected by PLLD lock */
-			tegra_clk_cfg_ex(
-				d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
-
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
-
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
-
-	return -EINVAL;
-}
-
-struct clk_ops tegra_dsib_clk_ops = {
-	.init			= &tegra30_periph_clk_init,
-	.enable			= &tegra30_periph_clk_enable,
-	.disable		= &tegra30_periph_clk_disable,
-	.set_parent		= &tegra30_dsib_clk_set_parent,
-	.set_rate		= &tegra30_periph_clk_set_rate,
-	.round_rate		= &tegra30_periph_clk_round_rate,
-	.reset			= &tegra30_periph_clk_reset,
-};
-
-/* pciex clock support only reset function */
-struct clk_ops tegra_pciex_clk_ops = {
-	.reset    = tegra30_periph_clk_reset,
-};
-
 /* Output clock ops */
 
 static DEFINE_SPINLOCK(clk_out_lock);
 
-static void tegra30_clk_out_init(struct clk *c)
+static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
 {
-	const struct clk_mux_sel *mux = 0;
-	const struct clk_mux_sel *sel;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = pmc_readl(c->reg);
 
 	c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
 	c->mul = 1;
 	c->div = 1;
-
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (((val & periph_clk_source_mask(c)) >>
-		     periph_clk_source_shift(c)) == sel->value)
-			mux = sel;
-	}
-	BUG_ON(!mux);
-	c->parent = mux->input;
+	return c->state;
 }
 
-static int tegra30_clk_out_enable(struct clk *c)
+static int tegra30_clk_out_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	unsigned long flags;
 
-	pr_debug("%s on clock %s\n", __func__, c->name);
-
 	spin_lock_irqsave(&clk_out_lock, flags);
 	val = pmc_readl(c->reg);
 	val |= (0x1 << c->u.periph.clk_num);
@@ -1804,13 +2003,12 @@ static int tegra30_clk_out_enable(struct clk *c)
 	return 0;
 }
 
-static void tegra30_clk_out_disable(struct clk *c)
+static void tegra30_clk_out_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	unsigned long flags;
 
-	pr_debug("%s on clock %s\n", __func__, c->name);
-
 	spin_lock_irqsave(&clk_out_lock, flags);
 	val = pmc_readl(c->reg);
 	val &= ~(0x1 << c->u.periph.clk_num);
@@ -1818,58 +2016,59 @@ static void tegra30_clk_out_disable(struct clk *c)
 	spin_unlock_irqrestore(&clk_out_lock, flags);
 }
 
-static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
 	unsigned long flags;
-	const struct clk_mux_sel *sel;
 
-	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			if (c->refcnt)
-				clk_enable(p);
+	spin_lock_irqsave(&clk_out_lock, flags);
+	val = pmc_readl(c->reg);
+	val &= ~periph_clk_source_mask(c);
+	val |= (index << periph_clk_source_shift(c));
+	pmc_writel(val, c->reg);
+	spin_unlock_irqrestore(&clk_out_lock, flags);
 
-			spin_lock_irqsave(&clk_out_lock, flags);
-			val = pmc_readl(c->reg);
-			val &= ~periph_clk_source_mask(c);
-			val |= (sel->value << periph_clk_source_shift(c));
-			pmc_writel(val, c->reg);
-			spin_unlock_irqrestore(&clk_out_lock, flags);
+	return 0;
+}
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = pmc_readl(c->reg);
+	int source;
 
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
-	return -EINVAL;
+	source = (val & periph_clk_source_mask(c)) >>
+				periph_clk_source_shift(c);
+	return source;
 }
 
 struct clk_ops tegra_clk_out_ops = {
-	.init			= &tegra30_clk_out_init,
-	.enable			= &tegra30_clk_out_enable,
-	.disable		= &tegra30_clk_out_disable,
-	.set_parent		= &tegra30_clk_out_set_parent,
+	.is_enabled = tegra30_clk_out_is_enabled,
+	.enable = tegra30_clk_out_enable,
+	.disable = tegra30_clk_out_disable,
+	.set_parent = tegra30_clk_out_set_parent,
+	.get_parent = tegra30_clk_out_get_parent,
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
 /* Clock doubler ops */
-static void tegra30_clk_double_init(struct clk *c)
+static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
 {
-	u32 val = clk_readl(c->reg);
-	c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
-	c->div = 1;
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	c->state = ON;
 	if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
 		c->state = OFF;
+	return c->state;
 };
 
-static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	unsigned long parent_rate = clk_get_rate(c->parent);
+
 	if (rate == parent_rate) {
 		val = clk_readl(c->reg) | (0x1 << c->reg_shift);
 		clk_writel(val, c->reg);
@@ -1886,108 +2085,139 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
 	return -EINVAL;
 }
 
-struct clk_ops tegra30_clk_double_ops = {
-	.init			= &tegra30_clk_double_init,
-	.enable			= &tegra30_periph_clk_enable,
-	.disable		= &tegra30_periph_clk_disable,
-	.set_rate		= &tegra30_clk_double_set_rate,
-};
+static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u64 rate = parent_rate;
 
-/* Audio sync clock ops */
-static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+	u32 val = clk_readl(c->reg);
+	c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+	c->div = 1;
+
+	if (c->mul != 0 && c->div != 0) {
+		rate *= c->mul;
+		rate += c->div - 1; /* round up */
+		do_div(rate, c->div);
+	}
+
+	return rate;
+}
+
+static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
 {
-	c->rate = rate;
-	return 0;
+	unsigned long output_rate = *prate;
+
+	do_div(output_rate, 2);
+	return output_rate;
 }
 
+struct clk_ops tegra30_clk_double_ops = {
+	.is_enabled = tegra30_clk_double_is_enabled,
+	.enable = tegra30_periph_clk_enable,
+	.disable = tegra30_periph_clk_disable,
+	.recalc_rate = tegra30_clk_double_recalc_rate,
+	.round_rate = tegra30_clk_double_round_rate,
+	.set_rate = tegra30_clk_double_set_rate,
+};
+
+/* Audio sync clock ops */
 struct clk_ops tegra_sync_source_ops = {
-	.set_rate		= &tegra30_sync_source_set_rate,
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-static void tegra30_audio_sync_clk_init(struct clk *c)
+static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
 {
-	int source;
-	const struct clk_mux_sel *sel;
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
 	c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
-	source = val & AUDIO_SYNC_SOURCE_MASK;
-	for (sel = c->inputs; sel->input != NULL; sel++)
-		if (sel->value == source)
-			break;
-	BUG_ON(sel->input == NULL);
-	c->parent = sel->input;
+	return c->state;
 }
 
-static int tegra30_audio_sync_clk_enable(struct clk *c)
+static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
 	clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
 	return 0;
 }
 
-static void tegra30_audio_sync_clk_disable(struct clk *c)
+static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
 	clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
 }
 
-static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val;
-	const struct clk_mux_sel *sel;
-	for (sel = c->inputs; sel->input != NULL; sel++) {
-		if (sel->input == p) {
-			val = clk_readl(c->reg);
-			val &= ~AUDIO_SYNC_SOURCE_MASK;
-			val |= sel->value;
 
-			if (c->refcnt)
-				clk_enable(p);
-
-			clk_writel(val, c->reg);
+	val = clk_readl(c->reg);
+	val &= ~AUDIO_SYNC_SOURCE_MASK;
+	val |= index;
 
-			if (c->refcnt && c->parent)
-				clk_disable(c->parent);
+	clk_writel(val, c->reg);
+	return 0;
+}
 
-			clk_reparent(c, p);
-			return 0;
-		}
-	}
+static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	u32 val = clk_readl(c->reg);
+	int source;
 
-	return -EINVAL;
+	source = val & AUDIO_SYNC_SOURCE_MASK;
+	return source;
 }
 
 struct clk_ops tegra30_audio_sync_clk_ops = {
-	.init       = tegra30_audio_sync_clk_init,
-	.enable     = tegra30_audio_sync_clk_enable,
-	.disable    = tegra30_audio_sync_clk_disable,
+	.is_enabled = tegra30_audio_sync_clk_is_enabled,
+	.enable = tegra30_audio_sync_clk_enable,
+	.disable = tegra30_audio_sync_clk_disable,
 	.set_parent = tegra30_audio_sync_clk_set_parent,
+	.get_parent = tegra30_audio_sync_clk_get_parent,
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
 /* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra30_cml_clk_init(struct clk *c)
+static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
 	u32 val = clk_readl(c->reg);
 	c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+	return c->state;
 }
 
-static int tegra30_cml_clk_enable(struct clk *c)
+static int tegra30_cml_clk_enable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	u32 val = clk_readl(c->reg);
 	val |= (0x1 << c->u.periph.clk_num);
 	clk_writel(val, c->reg);
+
 	return 0;
 }
 
-static void tegra30_cml_clk_disable(struct clk *c)
+static void tegra30_cml_clk_disable(struct clk_hw *hw)
 {
+	struct clk_tegra *c = to_clk_tegra(hw);
+
 	u32 val = clk_readl(c->reg);
 	val &= ~(0x1 << c->u.periph.clk_num);
 	clk_writel(val, c->reg);
 }
 
 struct clk_ops tegra_cml_clk_ops = {
-	.init			= &tegra30_cml_clk_init,
-	.enable			= &tegra30_cml_clk_enable,
-	.disable		= &tegra30_cml_clk_disable,
+	.is_enabled = tegra30_cml_clk_is_enabled,
+	.enable = tegra30_cml_clk_enable,
+	.disable = tegra30_cml_clk_disable,
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
+struct clk_ops tegra_pciex_clk_ops = {
+	.recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
index f8c4df5..aeb4e96 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -17,6 +17,7 @@
 #ifndef __MACH_TEGRA30_CLOCK_H
 #define __MACH_TEGRA30_CLOCK_H
 
+extern struct clk_ops tegra_clk_32k_ops;
 extern struct clk_ops tegra30_clk_m_ops;
 extern struct clk_ops tegra_clk_m_div_ops;
 extern struct clk_ops tegra_pll_ref_ops;
@@ -27,17 +28,26 @@ extern struct clk_ops tegra30_plle_ops;
 extern struct clk_ops tegra_cml_clk_ops;
 extern struct clk_ops tegra_pciex_clk_ops;
 extern struct clk_ops tegra_sync_source_ops;
-extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
 extern struct clk_ops tegra30_clk_double_ops;
 extern struct clk_ops tegra_clk_out_ops;
 extern struct clk_ops tegra30_super_ops;
 extern struct clk_ops tegra30_blink_clk_ops;
 extern struct clk_ops tegra30_twd_ops;
 extern struct clk_ops tegra30_periph_clk_ops;
-extern struct clk_ops tegra_dsib_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
 extern struct clk_ops tegra_nand_clk_ops;
 extern struct clk_ops tegra_vi_clk_ops;
 extern struct clk_ops tegra_dtv_clk_ops;
 extern struct clk_ops tegra_clk_shared_bus_ops;
 
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+				enum tegra_clk_ex_param p, u32 setting);
 #endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index b1243c9..c924240 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-tegra/tegra30_clocks_data.c
+ * arch/arm/mach-tegra/tegra30_clocks.c
  *
- * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
  *
  */
 
+#include <linux/clk-private.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -28,69 +29,165 @@
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 
-#include <asm/clkdev.h>
-
-#include <mach/iomap.h>
-
 #include "clock.h"
 #include "fuse.h"
 #include "tegra30_clocks.h"
 
-/* Clock definitions */
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,		\
+		   _parent_names, _parents, _parent)		\
+	static struct clk tegra_##_name = {			\
+		.hw = &tegra_##_name##_hw.hw,			\
+		.name = #_name,					\
+		.rate = _rate,					\
+		.ops = _ops,					\
+		.flags = _flags,				\
+		.parent_names = _parent_names,			\
+		.parents = _parents,				\
+		.num_parents = ARRAY_SIZE(_parent_names),	\
+		.parent	= _parent,				\
+	};
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+	.hw = {
+		.clk = &tegra_clk_32k,
+	},
+	.fixed_rate = 32768,
+};
 static struct clk tegra_clk_32k = {
 	.name = "clk_32k",
-	.rate = 32768,
-	.ops  = NULL,
-	.max_rate = 32768,
+	.hw = &tegra_clk_32k_hw.hw,
+	.ops = &tegra_clk_32k_ops,
+	.flags = CLK_IS_ROOT,
 };
 
-static struct clk tegra_clk_m = {
-	.name      = "clk_m",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra30_clk_m_ops,
-	.reg       = 0x1fc,
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+	.hw = {
+		.clk = &tegra_clk_m,
+	},
+	.flags = ENABLE_ON_INIT,
+	.reg = 0x1fc,
 	.reg_shift = 28,
-	.max_rate  = 48000000,
+	.max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+	.name = "clk_m",
+	.hw = &tegra_clk_m_hw.hw,
+	.ops = &tegra30_clk_m_ops,
+	.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
 };
 
-static struct clk tegra_clk_m_div2 = {
-	.name      = "clk_m_div2",
-	.ops       = &tegra_clk_m_div_ops,
-	.parent    = &tegra_clk_m,
-	.mul       = 1,
-	.div       = 2,
-	.state     = ON,
-	.max_rate  = 24000000,
+static const char *clk_m_div_parent_names[] = {
+	"clk_m",
 };
 
-static struct clk tegra_clk_m_div4 = {
-	.name      = "clk_m_div4",
-	.ops       = &tegra_clk_m_div_ops,
-	.parent    = &tegra_clk_m,
-	.mul       = 1,
-	.div       = 4,
-	.state     = ON,
-	.max_rate  = 12000000,
+static struct clk *clk_m_div_parents[] = {
+	&tegra_clk_m,
 };
 
-static struct clk tegra_pll_ref = {
-	.name      = "pll_ref",
-	.flags     = ENABLE_ON_INIT,
-	.ops       = &tegra_pll_ref_ops,
-	.parent    = &tegra_clk_m,
-	.max_rate  = 26000000,
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+	.hw = {
+		.clk = &tegra_clk_m_div2,
+	},
+	.mul = 1,
+	.div = 2,
+	.max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+		clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+	.hw = {
+		.clk = &tegra_clk_m_div4,
+	},
+	.mul = 1,
+	.div = 4,
+	.max_rate = 12000000,
 };
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+		clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+	.hw = {
+		.clk = &tegra_pll_ref,
+	},
+	.flags = ENABLE_ON_INIT,
+	.max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+		clk_m_div_parents, &tegra_clk_m);
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,	\
+		   _input_max, _cf_min, _cf_max, _vco_min,	\
+		   _vco_max, _freq_table, _lock_delay, _ops,	\
+		   _fixed_rate, _clk_cfg_ex, _parent)		\
+	static struct clk tegra_##_name;			\
+	static const char *_name##_parent_names[] = {		\
+		#_parent,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		&tegra_##_parent,				\
+	};							\
+	static struct clk_tegra tegra_##_name##_hw = {		\
+		.hw = {						\
+			.clk = &tegra_##_name,			\
+		},						\
+		.flags = _flags,				\
+		.reg = _reg,					\
+		.max_rate = _max_rate,				\
+		.u.pll = {					\
+			.input_min = _input_min,		\
+			.input_max = _input_max,		\
+			.cf_min = _cf_min,			\
+			.cf_max = _cf_max,			\
+			.vco_min = _vco_min,			\
+			.vco_max = _vco_max,			\
+			.freq_table = _freq_table,		\
+			.lock_delay = _lock_delay,		\
+			.fixed_rate = _fixed_rate,		\
+		},						\
+		.clk_cfg_ex = _clk_cfg_ex,			\
+	};							\
+	DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,	\
+			 _name##_parent_names, _name##_parents,	\
+			&tegra_##_parent);
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,		\
+		_max_rate, _ops, _parent, _clk_flags)		\
+	static const char *_name##_parent_names[] = {		\
+		#_parent,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		&tegra_##_parent,				\
+	};							\
+	static struct clk tegra_##_name;			\
+	static struct clk_tegra tegra_##_name##_hw = {		\
+		.hw = {						\
+			.clk = &tegra_##_name,			\
+		},						\
+		.flags = _flags,				\
+		.reg = _reg,					\
+		.max_rate = _max_rate,				\
+		.reg_shift = _reg_shift,			\
+	};							\
+	DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,	\
+		_clk_flags,  _name##_parent_names,		\
+		_name##_parents, &tegra_##_parent);
 
 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
 	{ 12000000, 1040000000, 520,  6, 1, 8},
 	{ 13000000, 1040000000, 480,  6, 1, 8},
-	{ 16800000, 1040000000, 495,  8, 1, 8},		/* actual: 1039.5 MHz */
+	{ 16800000, 1040000000, 495,  8, 1, 8},	/* actual: 1039.5 MHz */
 	{ 19200000, 1040000000, 325,  6, 1, 6},
 	{ 26000000, 1040000000, 520, 13, 1, 8},
 
 	{ 12000000, 832000000, 416,  6, 1, 8},
 	{ 13000000, 832000000, 832, 13, 1, 8},
-	{ 16800000, 832000000, 396,  8, 1, 8},		/* actual: 831.6 MHz */
+	{ 16800000, 832000000, 396,  8, 1, 8},	/* actual: 831.6 MHz */
 	{ 19200000, 832000000, 260,  6, 1, 8},
 	{ 26000000, 832000000, 416, 13, 1, 8},
 
@@ -108,46 +205,24 @@ static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
 
 	{ 12000000, 520000000, 520, 12, 1, 8},
 	{ 13000000, 520000000, 520, 13, 1, 8},
-	{ 16800000, 520000000, 495, 16, 1, 8},		/* actual: 519.75 MHz */
+	{ 16800000, 520000000, 495, 16, 1, 8},	/* actual: 519.75 MHz */
 	{ 19200000, 520000000, 325, 12, 1, 6},
 	{ 26000000, 520000000, 520, 26, 1, 8},
 
 	{ 12000000, 416000000, 416, 12, 1, 8},
 	{ 13000000, 416000000, 416, 13, 1, 8},
-	{ 16800000, 416000000, 396, 16, 1, 8},		/* actual: 415.8 MHz */
+	{ 16800000, 416000000, 396, 16, 1, 8},	/* actual: 415.8 MHz */
 	{ 19200000, 416000000, 260, 12, 1, 6},
 	{ 26000000, 416000000, 416, 26, 1, 8},
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_c = {
-	.name      = "pll_c",
-	.flags	   = PLL_HAS_CPCON,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0x80,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1400000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_c_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+		6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+		tegra30_pll_ops, 0, NULL, pll_ref);
 
-static struct clk tegra_pll_c_out1 = {
-	.name      = "pll_c_out1",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_c,
-	.reg       = 0x84,
-	.reg_shift = 0,
-	.max_rate  = 700000000,
-};
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+		tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
 	{ 12000000, 666000000, 666, 12, 1, 8},
@@ -163,34 +238,12 @@ static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_m = {
-	.name      = "pll_m",
-	.flags     = PLL_HAS_CPCON | PLLM,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0x90,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 800000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1200000000,
-		.freq_table = tegra_pll_m_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+		1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+		300, tegra30_pll_ops, 0, NULL, pll_ref);
 
-static struct clk tegra_pll_m_out1 = {
-	.name      = "pll_m_out1",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_m,
-	.reg       = 0x94,
-	.reg_shift = 0,
-	.max_rate  = 600000000,
-};
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+		tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
 	{ 12000000, 216000000, 432, 12, 2, 8},
@@ -201,65 +254,19 @@ static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_p = {
-	.name      = "pll_p",
-	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0xa0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 432000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_p_freq_table,
-		.lock_delay = 300,
-		.fixed_rate = 408000000,
-	},
-};
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+		2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+		tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+		pll_ref);
 
-static struct clk tegra_pll_p_out1 = {
-	.name      = "pll_p_out1",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-	.name      = "pll_p_out2",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa4,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-	.name      = "pll_p_out3",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 0,
-	.max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-	.name      = "pll_p_out4",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-	.parent    = &tegra_pll_p,
-	.reg       = 0xa8,
-	.reg_shift = 16,
-	.max_rate  = 432000000,
-};
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+		0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+		16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+		0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+		16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
 	{ 9600000, 564480000, 294, 5, 1, 4},
@@ -272,34 +279,12 @@ static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_a = {
-	.name      = "pll_a",
-	.flags     = PLL_HAS_CPCON,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0xb0,
-	.parent    = &tegra_pll_p_out1,
-	.max_rate  = 700000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1400000000,
-		.freq_table = tegra_pll_a_freq_table,
-		.lock_delay = 300,
-	},
-};
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+		6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+		300, tegra30_pll_ops, 0, NULL, pll_p_out1);
 
-static struct clk tegra_pll_a_out0 = {
-	.name      = "pll_a_out0",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_U71,
-	.parent    = &tegra_pll_a,
-	.reg       = 0xb4,
-	.reg_shift = 0,
-	.max_rate  = 100000000,
-};
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+		pll_a, CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 	{ 12000000, 216000000, 216, 12, 1, 4},
@@ -322,59 +307,20 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_d = {
-	.name      = "pll_d",
-	.flags     = PLL_HAS_CPCON | PLLD,
-	.ops       = &tegra_plld_ops,
-	.reg       = 0xd0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+		1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+		1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
 
-static struct clk tegra_pll_d_out0 = {
-	.name      = "pll_d_out0",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d,
-	.max_rate  = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
-	.name      = "pll_d2",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
-	.ops       = &tegra_plld_ops,
-	.reg       = 0x4b8,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1000000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 40000000,
-		.vco_max   = 1000000000,
-		.freq_table = tegra_pll_d_freq_table,
-		.lock_delay = 1000,
-	},
-};
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+		pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 
-static struct clk tegra_pll_d2_out0 = {
-	.name      = "pll_d2_out0",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_2 | PLLD,
-	.parent    = &tegra_pll_d2,
-	.max_rate  = 500000000,
-};
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+		2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+		tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+		pll_ref);
+
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+		pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
 	{ 12000000, 480000000, 960, 12, 2, 12},
@@ -385,24 +331,9 @@ static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_u = {
-	.name      = "pll_u",
-	.flags     = PLL_HAS_CPCON | PLLU,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0xc0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 480000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 40000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 480000000,
-		.vco_max   = 960000000,
-		.freq_table = tegra_pll_u_freq_table,
-		.lock_delay = 1000,
-	},
-};
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+		1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+		1000, tegra30_pll_ops, 0, NULL, pll_ref);
 
 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 	/* 1.7 GHz */
@@ -464,33 +395,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_x = {
-	.name      = "pll_x",
-	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
-	.ops       = &tegra30_pll_ops,
-	.reg       = 0xe0,
-	.parent    = &tegra_pll_ref,
-	.max_rate  = 1700000000,
-	.u.pll = {
-		.input_min = 2000000,
-		.input_max = 31000000,
-		.cf_min    = 1000000,
-		.cf_max    = 6000000,
-		.vco_min   = 20000000,
-		.vco_max   = 1700000000,
-		.freq_table = tegra_pll_x_freq_table,
-		.lock_delay = 300,
-	},
-};
-
-static struct clk tegra_pll_x_out0 = {
-	.name      = "pll_x_out0",
-	.ops       = &tegra30_pll_div_ops,
-	.flags     = DIV_2 | PLLX,
-	.parent    = &tegra_pll_x,
-	.max_rate  = 850000000,
-};
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+		2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+		tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
 
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+		pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 
 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
 	/* PLLE special case: use cpcon field to store cml divider value */
@@ -499,518 +409,835 @@ static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
 	{ 0, 0, 0, 0, 0, 0 },
 };
 
-static struct clk tegra_pll_e = {
-	.name      = "pll_e",
-	.flags     = PLL_ALT_MISC_REG,
-	.ops       = &tegra30_plle_ops,
-	.reg       = 0xe8,
-	.max_rate  = 100000000,
-	.u.pll = {
-		.input_min = 12000000,
-		.input_max = 216000000,
-		.cf_min    = 12000000,
-		.cf_max    = 12000000,
-		.vco_min   = 1200000000,
-		.vco_max   = 2400000000U,
-		.freq_table = tegra_pll_e_freq_table,
-		.lock_delay = 300,
-		.fixed_rate = 100000000,
-	},
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+		12000000, 12000000, 1200000000, 2400000000U,
+		tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+		pll_ref);
+
+static const char *mux_plle[] = {
+	"pll_e",
+};
+
+static struct clk *mux_plle_p[] = {
+	&tegra_pll_e,
 };
 
-static struct clk tegra_cml0_clk = {
-	.name      = "cml0",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_cml_clk_ops,
-	.reg       = 0x48c,
-	.max_rate  = 100000000,
-	.u.periph  = {
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+	.hw = {
+		.clk = &tegra_cml0,
+	},
+	.reg = 0x48c,
+	.fixed_rate = 100000000,
+	.u.periph = {
 		.clk_num = 0,
 	},
 };
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+		mux_plle_p, &tegra_pll_e);
 
-static struct clk tegra_cml1_clk = {
-	.name      = "cml1",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_cml_clk_ops,
-	.reg       = 0x48c,
-	.max_rate  = 100000000,
-	.u.periph  = {
-		.clk_num   = 1,
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+	.hw = {
+		.clk = &tegra_cml1,
+	},
+	.reg = 0x48c,
+	.fixed_rate = 100000000,
+	.u.periph = {
+		.clk_num = 1,
 	},
 };
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+		mux_plle_p, &tegra_pll_e);
 
-static struct clk tegra_pciex_clk = {
-	.name      = "pciex",
-	.parent    = &tegra_pll_e,
-	.ops       = &tegra_pciex_clk_ops,
-	.max_rate  = 100000000,
-	.u.periph  = {
-		.clk_num   = 74,
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+	.hw = {
+		.clk = &tegra_pciex,
+	},
+	.reg = 0x48c,
+	.fixed_rate = 100000000,
+	.reset = tegra30_periph_clk_reset,
+	.u.periph = {
+		.clk_num = 74,
 	},
 };
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+		mux_plle_p, &tegra_pll_e);
 
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id)				\
-	{						\
-		.name      = #_id "_sync",		\
-		.rate      = 24000000,			\
-		.max_rate  = 24000000,			\
-		.ops       = &tegra_sync_source_ops	\
-	}
-static struct clk tegra_sync_source_list[] = {
-	SYNC_SOURCE(spdif_in),
-	SYNC_SOURCE(i2s0),
-	SYNC_SOURCE(i2s1),
-	SYNC_SOURCE(i2s2),
-	SYNC_SOURCE(i2s3),
-	SYNC_SOURCE(i2s4),
-	SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
-	{ .input = &tegra_sync_source_list[0],	.value = 0},
-	{ .input = &tegra_sync_source_list[1],	.value = 1},
-	{ .input = &tegra_sync_source_list[2],	.value = 2},
-	{ .input = &tegra_sync_source_list[3],	.value = 3},
-	{ .input = &tegra_sync_source_list[4],	.value = 4},
-	{ .input = &tegra_sync_source_list[5],	.value = 5},
-	{ .input = &tegra_pll_a_out0,		.value = 6},
-	{ .input = &tegra_sync_source_list[6],	.value = 7},
-	{ 0, 0 }
-};
-
-#define AUDIO_SYNC_CLK(_id, _index)			\
-	{						\
-		.name      = #_id,			\
-		.inputs    = mux_audio_sync_clk,	\
-		.reg       = 0x4A0 + (_index) * 4,	\
-		.max_rate  = 24000000,			\
-		.ops       = &tegra30_audio_sync_clk_ops	\
-	}
-static struct clk tegra_clk_audio_list[] = {
-	AUDIO_SYNC_CLK(audio0, 0),
-	AUDIO_SYNC_CLK(audio1, 1),
-	AUDIO_SYNC_CLK(audio2, 2),
-	AUDIO_SYNC_CLK(audio3, 3),
-	AUDIO_SYNC_CLK(audio4, 4),
-	AUDIO_SYNC_CLK(audio, 5),	/* SPDIF */
-};
-
-#define AUDIO_SYNC_2X_CLK(_id, _index)				\
-	{							\
-		.name      = #_id "_2x",			\
-		.flags     = PERIPH_NO_RESET,			\
-		.max_rate  = 48000000,				\
-		.ops       = &tegra30_clk_double_ops,		\
-		.reg       = 0x49C,				\
+#define SYNC_SOURCE(_name)					\
+	static struct clk tegra_##_name##_sync;			\
+	static struct clk_tegra tegra_##_name##_sync_hw = {	\
+		.hw = {						\
+			.clk = &tegra_##_name##_sync,		\
+		},						\
+		.max_rate = 24000000,				\
+		.fixed_rate = 24000000,				\
+	};							\
+	static struct clk tegra_##_name##_sync = {		\
+		.name = #_name "_sync",				\
+		.hw = &tegra_##_name##_sync_hw.hw,		\
+		.ops = &tegra_sync_source_ops,			\
+		.flags = CLK_IS_ROOT,				\
+	};
+
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+
+static struct clk *tegra_sync_source_list[] = {
+	&tegra_spdif_in_sync,
+	&tegra_i2s0_sync,
+	&tegra_i2s1_sync,
+	&tegra_i2s2_sync,
+	&tegra_i2s3_sync,
+	&tegra_i2s4_sync,
+	&tegra_vimclk_sync,
+};
+
+static const char *mux_audio_sync_clk[] = {
+	"spdif_in_sync",
+	"i2s0_sync",
+	"i2s1_sync",
+	"i2s2_sync",
+	"i2s3_sync",
+	"i2s4_sync",
+	"vimclk_sync",
+};
+
+#define AUDIO_SYNC_CLK(_name, _index)				\
+	static struct clk tegra_##_name;			\
+	static struct clk_tegra tegra_##_name##_hw = {		\
+		.hw = {						\
+			.clk = &tegra_##_name,			\
+		},						\
+		.max_rate = 24000000,				\
+		.reg = 0x4A0 + (_index) * 4,			\
+	};							\
+	static struct clk tegra_##_name = {			\
+		.name = #_name,					\
+		.ops = &tegra_audio_sync_clk_ops,		\
+		.hw = &tegra_##_name##_hw.hw,			\
+		.parent_names = mux_audio_sync_clk,		\
+		.parents = tegra_sync_source_list,		\
+		.num_parents = ARRAY_SIZE(mux_audio_sync_clk),	\
+	};
+
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+
+static struct clk *tegra_clk_audio_list[] = {
+	&tegra_audio0,
+	&tegra_audio1,
+	&tegra_audio2,
+	&tegra_audio3,
+	&tegra_audio4,
+	&tegra_audio5,	/* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_name, _index)			\
+	static const char *_name##_parent_names[] = {		\
+		"tegra_" #_name,				\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		&tegra_##_name,					\
+	};							\
+	static struct clk tegra_##_name##_2x;			\
+	static struct clk_tegra tegra_##_name##_2x_hw = {	\
+		.hw = {						\
+			.clk = &tegra_##_name##_2x,		\
+		},						\
+		.flags = PERIPH_NO_RESET,			\
+		.max_rate = 48000000,				\
+		.reg = 0x49C,					\
 		.reg_shift = 24 + (_index),			\
-		.parent    = &tegra_clk_audio_list[(_index)],	\
 		.u.periph = {					\
 			.clk_num = 113 + (_index),		\
 		},						\
-	}
-static struct clk tegra_clk_audio_2x_list[] = {
-	AUDIO_SYNC_2X_CLK(audio0, 0),
-	AUDIO_SYNC_2X_CLK(audio1, 1),
-	AUDIO_SYNC_2X_CLK(audio2, 2),
-	AUDIO_SYNC_2X_CLK(audio3, 3),
-	AUDIO_SYNC_2X_CLK(audio4, 4),
-	AUDIO_SYNC_2X_CLK(audio, 5),	/* SPDIF */
-};
-
-#define MUX_I2S_SPDIF(_id, _index)					\
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {	\
-	{.input = &tegra_pll_a_out0, .value = 0},			\
-	{.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},	\
-	{.input = &tegra_pll_p, .value = 2},				\
-	{.input = &tegra_clk_m, .value = 3},				\
-	{ 0, 0},							\
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5);		/* SPDIF */
+	};							\
+	static struct clk tegra_##_name##_2x = {		\
+		.name = #_name "_2x",				\
+		.ops = &tegra30_clk_double_ops,			\
+		.hw = &tegra_##_name##_2x_hw.hw,		\
+		.parent_names = _name##_parent_names,		\
+		.parents = _name##_parents,			\
+		.parent = &tegra_##_name,			\
+		.num_parents = 1,				\
+	};
+
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5);	/* SPDIF */
+
+static struct clk *tegra_clk_audio_2x_list[] = {
+	&tegra_audio0_2x,
+	&tegra_audio1_2x,
+	&tegra_audio2_2x,
+	&tegra_audio3_2x,
+	&tegra_audio4_2x,
+	&tegra_audio5_2x,	/* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id)					\
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {	\
+	"pll_a_out0",						\
+	#_id "_2x",						\
+	"pll_p",						\
+	"clk_m",						\
+};								\
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {	\
+	&tegra_pll_a_out0,					\
+	&tegra_##_id##_2x,					\
+	&tegra_pll_p,						\
+	&tegra_clk_m,						\
+};
+
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5);		/* SPDIF */
+
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
 
 /* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)						\
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {	\
-	{.input = &tegra_clk_m,		.value = 0},			\
-	{.input = &tegra_clk_m_div2,	.value = 1},			\
-	{.input = &tegra_clk_m_div4,	.value = 2},			\
-	{.input = NULL,			.value = 3}, /* placeholder */	\
-	{ 0, 0},							\
-}
+#define MUX_EXTERN_OUT(_id)					\
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {	\
+	"clk_m",						\
+	"clk_m_div2",						\
+	"clk_m_div4",						\
+	"extern" #_id,						\
+};								\
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {	\
+	&tegra_clk_m,						\
+	&tegra_clk_m_div2,					\
+	&tegra_clk_m_div4,					\
+	&tegra_extern##_id,					\
+};
+
 MUX_EXTERN_OUT(1);
 MUX_EXTERN_OUT(2);
 MUX_EXTERN_OUT(3);
 
-static struct clk_mux_sel *mux_extern_out_list[] = {
-	mux_clkm_clkm2_clkm4_extern1,
-	mux_clkm_clkm2_clkm4_extern2,
-	mux_clkm_clkm2_clkm4_extern3,
+#define CLK_OUT_CLK(_name, _index)					\
+	static struct clk tegra_##_name;				\
+	static struct clk_tegra tegra_##_name##_hw = {			\
+		.hw = {							\
+			.clk = &tegra_##_name,				\
+		},							\
+		.lookup = {						\
+			.dev_id	= #_name,				\
+			.con_id	= "extern" #_index,			\
+		},							\
+		.flags = MUX_CLK_OUT,					\
+		.fixed_rate = 216000000,					\
+		.reg = 0x1a8,						\
+		.u.periph = {						\
+			.clk_num = (_index - 1) * 8 + 2,		\
+		},							\
+	};								\
+	static struct clk tegra_##_name = {				\
+		.name = #_name,						\
+		.ops = &tegra_clk_out_ops,				\
+		.hw = &tegra_##_name##_hw.hw,				\
+		.parent_names = mux_clkm_clkm2_clkm4_extern##_index,	\
+		.parents = mux_clkm_clkm2_clkm4_extern##_index##_p,	\
+		.num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+	};
+
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+
+static struct clk *tegra_clk_out_list[] = {
+	&tegra_clk_out_1,
+	&tegra_clk_out_2,
+	&tegra_clk_out_3,
+};
+
+static const char *mux_sclk[] = {
+	"clk_m",
+	"pll_c_out1",
+	"pll_p_out4",
+	"pll_p_out3",
+	"pll_p_out2",
+	"dummy",
+	"clk_32k",
+	"pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+	&tegra_clk_m,
+	&tegra_pll_c_out1,
+	&tegra_pll_p_out4,
+	&tegra_pll_p_out3,
+	&tegra_pll_p_out2,
+	NULL,
+	&tegra_clk_32k,
+	&tegra_pll_m_out1,
 };
 
-#define CLK_OUT_CLK(_id)					\
-	{							\
-		.name      = "clk_out_" #_id,			\
-		.lookup    = {					\
-			.dev_id    = "clk_out_" #_id,		\
-			.con_id	   = "extern" #_id,		\
-		},						\
-		.ops       = &tegra_clk_out_ops,		\
-		.reg       = 0x1a8,				\
-		.inputs    = mux_clkm_clkm2_clkm4_extern##_id,	\
-		.flags     = MUX_CLK_OUT,			\
-		.max_rate  = 216000000,				\
-		.u.periph = {					\
-			.clk_num   = (_id - 1) * 8 + 2,		\
-		},						\
-	}
-static struct clk tegra_clk_out_list[] = {
-	CLK_OUT_CLK(1),
-	CLK_OUT_CLK(2),
-	CLK_OUT_CLK(3),
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+	.hw = {
+		.clk = &tegra_clk_sclk,
+	},
+	.reg = 0x28,
+	.max_rate = 334000000,
+	.min_rate = 40000000,
 };
 
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
-{
-	int i;
-	struct clk *c;
-
-	/* output clock con_id is the name of peripheral
-	   external clock connected to input 3 of the output mux */
-	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
-		c = tegra_get_clock_by_name(
-			tegra_clk_out_list[i].lookup.con_id);
-		if (!c)
-			pr_err("%s: could not find clk %s\n", __func__,
-			       tegra_clk_out_list[i].lookup.con_id);
-		mux_extern_out_list[i][3].input = c;
-	}
-}
+static struct clk tegra_clk_sclk = {
+	.name = "sclk",
+	.ops = &tegra30_super_ops,
+	.hw = &tegra_clk_sclk_hw.hw,
+	.parent_names = mux_sclk,
+	.parents = mux_sclk_p,
+	.num_parents = ARRAY_SIZE(mux_sclk),
+};
 
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
-	{ .input = &tegra_clk_m,	.value = 0},
-	{ .input = &tegra_pll_c_out1,	.value = 1},
-	{ .input = &tegra_pll_p_out4,	.value = 2},
-	{ .input = &tegra_pll_p_out3,	.value = 3},
-	{ .input = &tegra_pll_p_out2,	.value = 4},
-	/* { .input = &tegra_clk_d,	.value = 5}, - no use on tegra30 */
-	{ .input = &tegra_clk_32k,	.value = 6},
-	{ .input = &tegra_pll_m_out1,	.value = 7},
-	{ 0, 0},
+static const char *mux_blink[] = {
+	"clk_32k",
 };
 
-static struct clk tegra_clk_sclk = {
-	.name	= "sclk",
-	.inputs	= mux_sclk,
-	.reg	= 0x28,
-	.ops	= &tegra30_super_ops,
-	.max_rate = 334000000,
-	.min_rate = 40000000,
+static struct clk *mux_blink_p[] = {
+	&tegra_clk_32k,
 };
 
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+	.hw = {
+		.clk = &tegra_clk_blink,
+	},
+	.reg = 0x40,
+	.max_rate = 32768,
+};
 static struct clk tegra_clk_blink = {
-	.name		= "blink",
-	.parent		= &tegra_clk_32k,
-	.reg		= 0x40,
-	.ops		= &tegra30_blink_clk_ops,
-	.max_rate	= 32768,
+	.name = "blink",
+	.ops = &tegra30_blink_clk_ops,
+	.hw = &tegra_clk_blink_hw.hw,
+	.parent = &tegra_clk_32k,
+	.parent_names = mux_blink,
+	.parents = mux_blink_p,
+	.num_parents = ARRAY_SIZE(mux_blink),
 };
 
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-	{ .input = &tegra_pll_m, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_pll_a_out0, .value = 3},
-	{ 0, 0},
+static const char *mux_pllm_pllc_pllp_plla[] = {
+	"pll_m",
+	"pll_c",
+	"pll_p",
+	"pll_a_out0",
 };
 
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_pll_c, .value = 1},
-	{ .input = &tegra_pll_m, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+	"pll_p",
+	"pll_c",
+	"pll_m",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_clkm[] = {
-	{ .input = &tegra_pll_p, .value = 0},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
+static const char *mux_pllp_clkm[] = {
+	"pll_p",
+	"dummy",
+	"dummy",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_d_out0, .value = 1},
-	{.input = &tegra_pll_c, .value = 2},
-	{.input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
+static const char *mux_pllp_plld_pllc_clkm[] = {
+	"pll_p",
+	"pll_d_out0",
+	"pll_c",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-	{.input = &tegra_pll_p, .value = 0},
-	{.input = &tegra_pll_m, .value = 1},
-	{.input = &tegra_pll_d_out0, .value = 2},
-	{.input = &tegra_pll_a_out0, .value = 3},
-	{.input = &tegra_pll_c, .value = 4},
-	{.input = &tegra_pll_d2_out0, .value = 5},
-	{.input = &tegra_clk_m, .value = 6},
-	{ 0, 0},
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+	"pll_p",
+	"pll_m",
+	"pll_d_out0",
+	"pll_a_out0",
+	"pll_c",
+	"pll_d2_out0",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
-	{ .input = &tegra_pll_a_out0, .value = 0},
-	/* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
-	{ .input = &tegra_pll_p, .value = 2},
-	{ .input = &tegra_clk_m, .value = 3},
-	{ 0, 0},
+static const char *mux_plla_pllc_pllp_clkm[] = {
+	"pll_a_out0",
+	"dummy",
+	"pll_p",
+	"clk_m"
 };
 
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_32k,   .value = 2},
-	{.input = &tegra_clk_m,     .value = 3},
-	{ 0, 0},
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+	"pll_p",
+	"pll_c",
+	"clk_32k",
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_clk_m,     .value = 2},
-	{.input = &tegra_clk_32k,   .value = 3},
-	{ 0, 0},
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+	"pll_p",
+	"pll_c",
+	"clk_m",
+	"clk_32k",
 };
 
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-	{.input = &tegra_pll_p,     .value = 0},
-	{.input = &tegra_pll_c,     .value = 1},
-	{.input = &tegra_pll_m,     .value = 2},
-	{ 0, 0},
+static const char *mux_pllp_pllc_pllm[] = {
+	"pll_p",
+	"pll_c",
+	"pll_m",
 };
 
-static struct clk_mux_sel mux_clk_m[] = {
-	{ .input = &tegra_clk_m, .value = 0},
-	{ 0, 0},
+static const char *mux_clk_m[] = {
+	"clk_m",
 };
 
-static struct clk_mux_sel mux_pllp_out3[] = {
-	{ .input = &tegra_pll_p_out3, .value = 0},
-	{ 0, 0},
+static const char *mux_pllp_out3[] = {
+	"pll_p_out3",
 };
 
-static struct clk_mux_sel mux_plld_out0[] = {
-	{ .input = &tegra_pll_d_out0, .value = 0},
-	{ 0, 0},
+static const char *mux_plld_out0[] = {
+	"pll_d_out0",
 };
 
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
-	{ .input = &tegra_pll_d_out0,  .value = 0},
-	{ .input = &tegra_pll_d2_out0, .value = 1},
-	{ 0, 0},
+static const char *mux_plld_out0_plld2_out0[] = {
+	"pll_d_out0",
+	"pll_d2_out0",
 };
 
-static struct clk_mux_sel mux_clk_32k[] = {
-	{ .input = &tegra_clk_32k, .value = 0},
-	{ 0, 0},
+static const char *mux_clk_32k[] = {
+	"clk_32k",
 };
 
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
-	{ .input = &tegra_pll_a_out0, .value = 0},
-	{ .input = &tegra_clk_32k,    .value = 1},
-	{ .input = &tegra_pll_p,      .value = 2},
-	{ .input = &tegra_clk_m,      .value = 3},
-	{ .input = &tegra_pll_e,      .value = 4},
-	{ 0, 0},
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+	"pll_a_out0",
+	"clk_32k",
+	"pll_p",
+	"clk_m",
+	"pll_e",
 };
 
-static struct clk_mux_sel mux_cclk_g[] = {
-	{ .input = &tegra_clk_m,        .value = 0},
-	{ .input = &tegra_pll_c,        .value = 1},
-	{ .input = &tegra_clk_32k,      .value = 2},
-	{ .input = &tegra_pll_m,        .value = 3},
-	{ .input = &tegra_pll_p,        .value = 4},
-	{ .input = &tegra_pll_p_out4,   .value = 5},
-	{ .input = &tegra_pll_p_out3,   .value = 6},
-	{ .input = &tegra_pll_x,        .value = 8},
-	{ 0, 0},
+static const char *mux_cclk_g[] = {
+	"clk_m",
+	"pll_c",
+	"clk_32k",
+	"pll_m",
+	"pll_p",
+	"pll_p_out4",
+	"pll_p_out3",
+	"dummy",
+	"pll_x",
 };
 
-static struct clk tegra_clk_cclk_g = {
-	.name	= "cclk_g",
-	.flags	= DIV_U71 | DIV_U71_INT,
-	.inputs = mux_cclk_g,
-	.reg	= 0x368,
-	.ops	= &tegra30_super_ops,
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+	&tegra_pll_m,
+	&tegra_pll_c,
+	&tegra_pll_p,
+	&tegra_pll_a_out0,
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_pll_m,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_clkm_p[] = {
+	&tegra_pll_p,
+	NULL,
+	NULL,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_d_out0,
+	&tegra_pll_c,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_m,
+	&tegra_pll_d_out0,
+	&tegra_pll_a_out0,
+	&tegra_pll_c,
+	&tegra_pll_d2_out0,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+	&tegra_pll_a_out0,
+	NULL,
+	&tegra_pll_p,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_clk_32k,
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_clk_m,
+	&tegra_clk_32k,
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+	&tegra_pll_p,
+	&tegra_pll_c,
+	&tegra_pll_m,
+};
+
+static struct clk *mux_clk_m_p[] = {
+	&tegra_clk_m,
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+	&tegra_pll_p_out3,
+};
+
+static struct clk *mux_plld_out0_p[] = {
+	&tegra_pll_d_out0,
+};
+
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+	&tegra_pll_d_out0,
+	&tegra_pll_d2_out0,
+};
+
+static struct clk *mux_clk_32k_p[] = {
+	&tegra_clk_32k,
+};
+
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+	&tegra_pll_a_out0,
+	&tegra_clk_32k,
+	&tegra_pll_p,
+	&tegra_clk_m,
+	&tegra_pll_e,
+};
+
+static struct clk *mux_cclk_g_p[] = {
+	&tegra_clk_m,
+	&tegra_pll_c,
+	&tegra_clk_32k,
+	&tegra_pll_m,
+	&tegra_pll_p,
+	&tegra_pll_p_out4,
+	&tegra_pll_p_out3,
+	NULL,
+	&tegra_pll_x,
+};
+
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+	.hw = {
+		.clk = &tegra_clk_cclk_g,
+	},
+	.flags = DIV_U71 | DIV_U71_INT,
+	.reg = 0x368,
 	.max_rate = 1700000000,
 };
+static struct clk tegra_clk_cclk_g = {
+	.name = "cclk_g",
+	.ops = &tegra30_super_ops,
+	.hw = &tegra_clk_cclk_g_hw.hw,
+	.parent_names = mux_cclk_g,
+	.parents = mux_cclk_g_p,
+	.num_parents = ARRAY_SIZE(mux_cclk_g),
+};
 
-static struct clk tegra30_clk_twd = {
-	.parent	  = &tegra_clk_cclk_g,
-	.name     = "twd",
-	.ops      = &tegra30_twd_ops,
-	.max_rate = 1400000000,	/* Same as tegra_clk_cpu_cmplx.max_rate */
-	.mul      = 1,
-	.div      = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
-		},					\
-		.ops       = &tegra30_periph_clk_ops,	\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
-		},					\
-	}
+static const char *mux_twd[] = {
+	"cclk_g",
+};
 
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs,	\
-			_flags, _ops)					\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id	   = _con,		\
-		},					\
-		.ops       = _ops,			\
-		.reg       = _reg,			\
-		.inputs    = _inputs,			\
-		.flags     = _flags,			\
-		.max_rate  = _max,			\
-		.u.periph = {				\
-			.clk_num   = _clk_num,		\
-		},					\
-	}
+static struct clk *mux_twd_p[] = {
+	&tegra_clk_cclk_g,
+};
 
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
-	{						\
-		.name      = _name,			\
-		.lookup    = {				\
-			.dev_id    = _dev,		\
-			.con_id    = _con,		\
-		},					\
-		.ops       = &tegra_clk_shared_bus_ops,	\
-		.parent = _parent,			\
-		.u.shared_bus_user = {			\
-			.client_id = _id,		\
-			.client_div = _div,		\
-			.mode = _mode,			\
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+	.hw = {
+		.clk = &tegra30_clk_twd,
+	},
+	.max_rate = 1400000000,
+	.mul = 1,
+	.div = 2,
+};
+
+static struct clk tegra30_clk_twd = {
+	.name = "twd",
+	.ops = &tegra30_twd_ops,
+	.hw = &tegra30_clk_twd_hw.hw,
+	.parent = &tegra_clk_cclk_g,
+	.parent_names = mux_twd,
+	.parents = mux_twd_p,
+	.num_parents = ARRAY_SIZE(mux_twd),
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,	\
+		_max, _inputs, _flags)	 		\
+	static struct clk tegra_##_name;		\
+	static struct clk_tegra tegra_##_name##_hw = {	\
+		.hw = {					\
+			.clk = &tegra_##_name,		\
 		},					\
-	}
-struct clk tegra_list_clks[] = {
-	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
-	PERIPH_CLK("kbc",	"tegra-kbc",		NULL,	36,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB),
-	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("kfuse",	"kfuse-tegra",		NULL,	40,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("fuse",	"fuse-tegra",		"fuse",	39,	0,	26000000,  mux_clk_m,			PERIPH_ON_APB),
-	PERIPH_CLK("fuse_burn",	"fuse-tegra",		"fuse_burn",	39,	0,	26000000,  mux_clk_m,		PERIPH_ON_APB),
-	PERIPH_CLK("apbif",	"tegra30-ahub",		"apbif", 107,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("i2s0",	"tegra30-i2s.0",	NULL,	30,	0x1d8,	26000000,  mux_pllaout0_audio0_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s1",	"tegra30-i2s.1",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio1_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s2",	"tegra30-i2s.2",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s3",	"tegra30-i2s.3",	NULL,	101,	0x3bc,	26000000,  mux_pllaout0_audio3_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("i2s4",	"tegra30-i2s.4",	NULL,	102,	0x3c0,	26000000,  mux_pllaout0_audio4_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("spdif_out",	"tegra30-spdif",	"spdif_out",	10,	0x108,	100000000, mux_pllaout0_audio_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("spdif_in",	"tegra30-spdif",	"spdif_in",	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("d_audio",	"tegra30-ahub",		"d_audio", 106,	0x3d0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam0",	"tegra30-dam.0",	NULL,   108,	0x3d8,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam1",	"tegra30-dam.1",	NULL,   109,	0x3dc,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("dam2",	"tegra30-dam.2",	NULL,   110,	0x3e0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda",	"tegra30-hda",		"hda",   125,	0x428,	108000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda2codec_2x",	"tegra30-hda",	"hda2codec",   111,	0x3e4,	48000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("hda2hdmi",	"tegra30-hda",		"hda2hdmi",	128,	0,	48000000,  mux_clk_m,			0),
-	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc5",	"spi_tegra.4",		NULL,	104,	0x3c8,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sbc6",	"spi_tegra.5",		NULL,	105,	0x3cc,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sata_oob",	"tegra_sata_oob",	NULL,	123,	0x420,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sata",	"tegra_sata",		NULL,	124,	0x424,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sata_cold",	"tegra_sata_cold",	NULL,	129,	0,	48000000,  mux_clk_m,			0),
-	PERIPH_CLK_EX("ndflash", "tegra_nand",		NULL,	13,	0x160,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71,	&tegra_nand_clk_ops),
-	PERIPH_CLK("ndspeed",	"tegra_nand_speed",	NULL,	80,	0x3f8,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("vde",	"vde",			NULL,	61,	0x1c8,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
-	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	127000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
-	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c4",	"tegra-i2c.3",		NULL,	103,	0x3c4,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("i2c5",	"tegra-i2c.4",		NULL,	47,	0x128,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB),
-	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-	PERIPH_CLK_EX("vi",	"tegra_camera",		"vi",	20,	0x148,	425000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT,	&tegra_vi_clk_ops),
-	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-	PERIPH_CLK("3d2",       "3d2",			NULL,	98,	0x3b0,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET),
-	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	260000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT),
-	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK_EX("dtv",	"dtv",			NULL,	79,	0x1dc,	250000000, mux_clk_m,			0,		&tegra_dtv_clk_ops),
-	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	220000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
-	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8),
-	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("dsia",	"tegradc.0",		"dsia",	48,	0,	500000000, mux_plld_out0,		0),
-	PERIPH_CLK_EX("dsib",	"tegradc.1",		"dsib",	82,	0xd0,	500000000, mux_plld_out0_plld2_out0,	MUX | PLLD,	&tegra_dsib_clk_ops),
-	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	102000000, mux_pllp_out3,		0),
-	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
-	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
-
-	PERIPH_CLK("tsensor",	"tegra-tsensor",	NULL,	100,	0x3b8,	216000000, mux_pllp_pllc_clkm_clk32,	MUX | DIV_U71),
-	PERIPH_CLK("actmon",	"actmon",		NULL,	119,	0x3e8,	216000000, mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("extern1",	"extern1",		NULL,	120,	0x3ec,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("extern2",	"extern2",		NULL,	121,	0x3f0,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("extern3",	"extern3",		NULL,	122,	0x3f4,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71),
-	PERIPH_CLK("i2cslow",	"i2cslow",		NULL,	81,	0x3fc,	26000000,  mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("pcie",	"tegra-pcie",		"pcie",	70,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("afi",	"tegra-pcie",		"afi",	72,	0,	250000000, mux_clk_m,			0),
-	PERIPH_CLK("se",	"se",			NULL,	127,	0x42c,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)		\
-	{						\
-		.name	= _name,			\
-		.lookup	= {				\
+		.lookup = {				\
 			.dev_id	= _dev,			\
-			.con_id		= _con,		\
+			.con_id	= _con,			\
 		},					\
+		.reg = _reg,				\
+		.flags = _flags,			\
+		.max_rate = _max,			\
+		.u.periph = {				\
+			.clk_num = _clk_num,		\
+		},					\
+		.reset = &tegra30_periph_clk_reset,	\
+	};						\
+	static struct clk tegra_##_name = {		\
+		.name = #_name,				\
+		.ops = &tegra30_periph_clk_ops,		\
+		.hw = &tegra_##_name##_hw.hw,		\
+		.parent_names = _inputs,		\
+		.parents = _inputs##_p,			\
+		.num_parents = ARRAY_SIZE(_inputs),	\
+	};
+
+PERIPH_CLK(apbdma,	"tegra-apbdma",		NULL,	34,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(rtc,		"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc,		"tegra-kbc",		NULL,	36,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer,	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(kfuse,	"kfuse-tegra",		NULL,	40,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(fuse,	"fuse-tegra",		"fuse",	39,	0,	26000000,  mux_clk_m,			PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn,	"fuse-tegra",		"fuse_burn",	39,	0,	26000000,  mux_clk_m,		PERIPH_ON_APB);
+PERIPH_CLK(apbif,	"tegra30-ahub",		"apbif", 107,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(i2s0,	"tegra30-i2s.0",	NULL,	30,	0x1d8,	26000000,  mux_pllaout0_audio0_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1,	"tegra30-i2s.1",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio1_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2,	"tegra30-i2s.2",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3,	"tegra30-i2s.3",	NULL,	101,	0x3bc,	26000000,  mux_pllaout0_audio3_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4,	"tegra30-i2s.4",	NULL,	102,	0x3c0,	26000000,  mux_pllaout0_audio4_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out,	"tegra30-spdif",	"spdif_out",	10,	0x108,	100000000, mux_pllaout0_audio5_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in,	"tegra30-spdif",	"spdif_in",	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm,		"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio,	"tegra30-ahub",		"d_audio", 106,	0x3d0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(dam0,	"tegra30-dam.0",	NULL,	108,	0x3d8,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(dam1,	"tegra30-dam.1",	NULL,	109,	0x3dc,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(dam2,	"tegra30-dam.2",	NULL,	110,	0x3e0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71);
+PERIPH_CLK(hda,		"tegra30-hda",		"hda",	125,	0x428,	108000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x,	"tegra30-hda",	"hda2codec",	111,	0x3e4,	48000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi,	"tegra30-hda",		"hda2hdmi",	128,	0,	48000000,  mux_clk_m,			0);
+PERIPH_CLK(sbc1,	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2,	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3,	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4,	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5,	"spi_tegra.4",		NULL,	104,	0x3c8,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6,	"spi_tegra.5",		NULL,	105,	0x3cc,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob,	"tegra_sata_oob",	NULL,	123,	0x420,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sata,	"tegra_sata",		NULL,	124,	0x424,	216000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(sata_cold,	"tegra_sata_cold",	NULL,	129,	0,	48000000,  mux_clk_m,			0);
+PERIPH_CLK(ndflash,	"tegra_nand",		NULL,	13,	0x160,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(ndspeed,	"tegra_nand_speed",	NULL,	80,	0x3f8,	240000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(vfir,	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1,	"sdhci-tegra.0",	NULL,	14,	0x150,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,	"sdhci-tegra.1",	NULL,	9,	0x154,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,	"sdhci-tegra.2",	NULL,	69,	0x1bc,	208000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,	"sdhci-tegra.3",	NULL,	15,	0x164,	104000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,		"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(bsea,	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(bsev,	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(vde,		"vde",			NULL,	61,	0x1c8,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite,	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la,		"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71);
+PERIPH_CLK(owr,		"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor,		"nor",			NULL,	42,	0x1d0,	127000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1,	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2,	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3,	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4,	"tegra-i2c.3",		NULL,	103,	0x3c4,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5,	"tegra-i2c.4",		NULL,	47,	0x128,	26000000,  mux_pllp_clkm,		MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta,	"tegra-uart.0",		NULL,	6,	0x178,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb,	"tegra-uart.1",		NULL,	7,	0x17c,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc,	"tegra-uart.2",		NULL,	55,	0x1a0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd,	"tegra-uart.3",		NULL,	65,	0x1c0,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte,	"tegra-uart.4",		NULL,	66,	0x1c4,	800000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi,		"tegra_camera",		"vi",	20,	0x148,	425000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d,		"3d",			NULL,	24,	0x158,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2,		"3d2",			NULL,	98,	0x3b0,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d,		"2d",			NULL,	21,	0x15c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor,	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp,		"epp",			NULL,	19,	0x16c,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe,		"mpe",			NULL,	60,	0x170,	520000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x,	"host1x",		NULL,	28,	0x180,	260000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve,		"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,		"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv,		"dtv",			NULL,	79,	0x1dc,	250000000, mux_clk_m,			0);
+PERIPH_CLK(hdmi,	"hdmi",			NULL,	51,	0x18c,	148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac,	"tvdac",		NULL,	53,	0x194,	220000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8);
+PERIPH_CLK(disp2,	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,	MUX | MUX8);
+PERIPH_CLK(usbd,	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(usb2,	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(usb3,	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0); /* requires min voltage */
+PERIPH_CLK(dsia,	"tegradc.0",		"dsia",	48,	0,	500000000, mux_plld_out0,		0);
+PERIPH_CLK(csi,		"tegra_camera",		"csi",	52,	0,	102000000, mux_pllp_out3,		0);
+PERIPH_CLK(isp,		"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0); /* same frequency as VI */
+PERIPH_CLK(csus,	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET);
+PERIPH_CLK(tsensor,	"tegra-tsensor",	NULL,	100,	0x3b8,	216000000, mux_pllp_pllc_clkm_clk32,	MUX | DIV_U71);
+PERIPH_CLK(actmon,	"actmon",		NULL,	119,	0x3e8,	216000000, mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71);
+PERIPH_CLK(extern1,	"extern1",		NULL,	120,	0x3ec,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2,	"extern2",		NULL,	121,	0x3f0,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3,	"extern3",		NULL,	122,	0x3f4,	216000000, mux_plla_clk32_pllp_clkm_plle,	MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow,	"i2cslow",		NULL,	81,	0x3fc,	26000000,  mux_pllp_pllc_clk32_clkm,	MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie,	"tegra-pcie",		"pcie",	70,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(afi,		"tegra-pcie",		"afi",	72,	0,	250000000, mux_clk_m,			0);
+PERIPH_CLK(se,		"se",			NULL,	127,	0x42c,	520000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71 | DIV_U71_INT);
+
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+	.hw = {
+		.clk = &tegra_dsib,
+	},
+	.lookup = {
+		.dev_id	= "tegradc.1",
+		.con_id	= "dsib",
+	},
+	.reg = 0xd0,
+	.flags = MUX | PLLD,
+	.max_rate = 500000000,
+	.u.periph = {
+		.clk_num = 82,
+	},
+	.reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+	.name = "dsib",
+	.ops = &tegra30_dsib_clk_ops,
+	.hw = &tegra_dsib_hw.hw,
+	.parent_names = mux_plld_out0_plld2_out0,
+	.parents = mux_plld_out0_plld2_out0_p,
+	.num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+
+struct clk *tegra_list_clks[] = {
+	&tegra_apbdma,
+	&tegra_rtc,
+	&tegra_kbc,
+	&tegra_timer,
+	&tegra_kfuse,
+	&tegra_fuse,
+	&tegra_fuse_burn,
+	&tegra_apbif,
+	&tegra_i2s0,
+	&tegra_i2s1,
+	&tegra_i2s2,
+	&tegra_i2s3,
+	&tegra_i2s4,
+	&tegra_spdif_out,
+	&tegra_spdif_in,
+	&tegra_pwm,
+	&tegra_d_audio,
+	&tegra_dam0,
+	&tegra_dam1,
+	&tegra_dam2,
+	&tegra_hda,
+	&tegra_hda2codec_2x,
+	&tegra_hda2hdmi,
+	&tegra_sbc1,
+	&tegra_sbc2,
+	&tegra_sbc3,
+	&tegra_sbc4,
+	&tegra_sbc5,
+	&tegra_sbc6,
+	&tegra_sata_oob,
+	&tegra_sata,
+	&tegra_sata_cold,
+	&tegra_ndflash,
+	&tegra_ndspeed,
+	&tegra_vfir,
+	&tegra_sdmmc1,
+	&tegra_sdmmc2,
+	&tegra_sdmmc3,
+	&tegra_sdmmc4,
+	&tegra_vcp,
+	&tegra_bsea,
+	&tegra_bsev,
+	&tegra_vde,
+	&tegra_csite,
+	&tegra_la,
+	&tegra_owr,
+	&tegra_nor,
+	&tegra_mipi,
+	&tegra_i2c1,
+	&tegra_i2c2,
+	&tegra_i2c3,
+	&tegra_i2c4,
+	&tegra_i2c5,
+	&tegra_uarta,
+	&tegra_uartb,
+	&tegra_uartc,
+	&tegra_uartd,
+	&tegra_uarte,
+	&tegra_vi,
+	&tegra_3d,
+	&tegra_3d2,
+	&tegra_2d,
+	&tegra_vi_sensor,
+	&tegra_epp,
+	&tegra_mpe,
+	&tegra_host1x,
+	&tegra_cve,
+	&tegra_tvo,
+	&tegra_dtv,
+	&tegra_hdmi,
+	&tegra_tvdac,
+	&tegra_disp1,
+	&tegra_disp2,
+	&tegra_usbd,
+	&tegra_usb2,
+	&tegra_usb3,
+	&tegra_dsia,
+	&tegra_dsib,
+	&tegra_csi,
+	&tegra_isp,
+	&tegra_csus,
+	&tegra_tsensor,
+	&tegra_actmon,
+	&tegra_extern1,
+	&tegra_extern2,
+	&tegra_extern3,
+	&tegra_i2cslow,
+	&tegra_pcie,
+	&tegra_afi,
+	&tegra_se,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)	\
+	{					\
+		.name	= _name,		\
+		.lookup	= {			\
+			.dev_id	= _dev,		\
+			.con_id	= _con,		\
+		},				\
 	}
 
 /* Some clocks may be used by different drivers depending on the board
@@ -1088,23 +1315,24 @@ struct clk *tegra_ptr_clks[] = {
 	&tegra_pll_x_out0,
 	&tegra_pll_e,
 	&tegra_clk_cclk_g,
-	&tegra_cml0_clk,
-	&tegra_cml1_clk,
-	&tegra_pciex_clk,
+	&tegra_cml0,
+	&tegra_cml1,
+	&tegra_pciex,
 	&tegra_clk_sclk,
 	&tegra_clk_blink,
 	&tegra30_clk_twd,
 };
 
-
 static void tegra30_init_one_clock(struct clk *c)
 {
-	clk_init(c);
-	INIT_LIST_HEAD(&c->shared_bus_list);
-	if (!c->lookup.dev_id && !c->lookup.con_id)
-		c->lookup.con_id = c->name;
-	c->lookup.clk = c;
-	clkdev_add(&c->lookup);
+	struct clk_tegra *clk = to_clk_tegra(c->hw);
+	__clk_init(NULL, c);
+	INIT_LIST_HEAD(&clk->shared_bus_list);
+	if (!clk->lookup.dev_id && !clk->lookup.con_id)
+		clk->lookup.con_id = c->name;
+	clk->lookup.clk = c;
+	clkdev_add(&clk->lookup);
+	tegra_clk_add(c);
 }
 
 void __init tegra30_init_clocks(void)
@@ -1116,7 +1344,7 @@ void __init tegra30_init_clocks(void)
 		tegra30_init_one_clock(tegra_ptr_clks[i]);
 
 	for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-		tegra30_init_one_clock(&tegra_list_clks[i]);
+		tegra30_init_one_clock(tegra_list_clks[i]);
 
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
 		c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
@@ -1131,14 +1359,12 @@ void __init tegra30_init_clocks(void)
 	}
 
 	for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
-		tegra30_init_one_clock(&tegra_sync_source_list[i]);
+		tegra30_init_one_clock(tegra_sync_source_list[i]);
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
-		tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+		tegra30_init_one_clock(tegra_clk_audio_list[i]);
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-		tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+		tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
 
-	init_clk_out_mux();
 	for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
-		tegra30_init_one_clock(&tegra_clk_out_list[i]);
-
+		tegra30_init_one_clock(tegra_clk_out_list[i]);
 }
-- 
1.7.4.1



From gregory.clement at free-electrons.com  Wed Aug  8 11:05:47 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:05:47 -0000
Subject: [RFC 1/6] arm: cache-l2x0: make outer_cache_fns a field of
 l2x0_of_data
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-2-git-send-email-gregory.clement@free-electrons.com>

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mm/cache-l2x0.c |   38 ++++++++++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2a8e380..3591940 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -39,7 +39,7 @@ struct l2x0_regs l2x0_saved_regs;
 struct l2x0_of_data {
 	void (*setup)(const struct device_node *, u32 *, u32 *);
 	void (*save)(void);
-	void (*resume)(void);
+	struct outer_cache_fns outer_cache;
 };
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
@@ -376,6 +376,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		writel_relaxed(1, l2x0_base + L2X0_CTRL);
 	}
 
+#ifndef CONFIG_OF
 	outer_cache.inv_range = l2x0_inv_range;
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
@@ -383,6 +384,7 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	outer_cache.flush_all = l2x0_flush_all;
 	outer_cache.inv_all = l2x0_inv_all;
 	outer_cache.disable = l2x0_disable;
+#endif
 
 	printk(KERN_INFO "%s cache controller enabled\n", type);
 	printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
@@ -533,15 +535,34 @@ static void pl310_resume(void)
 }
 
 static const struct l2x0_of_data pl310_data = {
-	pl310_of_setup,
-	pl310_save,
-	pl310_resume,
+	.setup = pl310_of_setup,
+	.save  = pl310_save,
+	.outer_cache = {
+		.resume      = pl310_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+		.set_debug   = pl310_set_debug,
+	},
 };
 
 static const struct l2x0_of_data l2x0_data = {
-	l2x0_of_setup,
-	NULL,
-	l2x0_resume,
+	.setup = l2x0_of_setup,
+	.save  = NULL,
+	.outer_cache = {
+		.resume      = l2x0_resume,
+		.inv_range   = l2x0_inv_range,
+		.clean_range = l2x0_clean_range,
+		.flush_range = l2x0_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
 };
 
 static const struct of_device_id l2x0_ids[] __initconst = {
@@ -583,7 +604,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 
 	l2x0_init(l2x0_base, aux_val, aux_mask);
 
-	outer_cache.resume = data->resume;
+	memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+
 	return 0;
 }
 #endif
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Wed Aug  8 11:05:52 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:05:52 -0000
Subject: [RFC 2/6] arm: cache-l2x0: add an optional register to save/restore
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-3-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c4c87bc..5f2c7b4 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -126,6 +126,7 @@ struct l2x0_regs {
 	unsigned long filter_end;
 	unsigned long prefetch_ctrl;
 	unsigned long pwr_ctrl;
+	unsigned long ctrl;
 };
 
 extern struct l2x0_regs l2x0_saved_regs;
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Wed Aug  8 11:05:55 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:05:55 -0000
Subject: [RFC 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-6-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/boot/dts/armada-370.dtsi |    6 ++++++
 arch/arm/boot/dts/armada-xp.dtsi  |    7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc..43fa832 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,6 +20,12 @@
 / {
 	model = "Marvell Armada 370 family SoC";
 	compatible = "marvell,armada370", "marvell,armada-370-xp";
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-with-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
 
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 71d6b5d..f045a63 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,13 @@
 	model = "Marvell Armada XP family SoC";
 	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+	L2: l2-cache {
+		compatible = "marvell,aurora-cache-no-outer";
+		reg = <0xd0008000 0x1000>;
+		cache-id-part = <0x100>;
+		wt-override;
+	};
+
 	mpic: interrupt-controller at d0020000 {
 	      reg = <0xd0020a00 0x1d0>,
 		    <0xd0021870 0x58>;
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Wed Aug  8 11:06:00 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:06:00 -0000
Subject: [RFC 4/6] arm: mvebu: add L2 cache support
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-5-git-send-email-gregory.clement@free-electrons.com>

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Jason Cooper <jason at lakedaemon.net>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-mvebu/Kconfig             |    1 +
 arch/arm/mach-mvebu/irq-armada-370-xp.c |    4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e..e20c5e9 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,7 @@ config MACH_ARMADA_370_XP
 	bool "Marvell Armada 370 and Aramada XP boards"
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+	select CACHE_L2X0
 	help
 
 	  Say 'Y' here if you want your kernel to support boards based on
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..570be84 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /* Interrupt Controller Registers Map */
 #define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
@@ -130,4 +131,7 @@ static const struct of_device_id mpic_of_match[] __initconst = {
 void __init armada_370_xp_init_irq(void)
 {
 	of_irq_init(mpic_of_match);
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
 }
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Wed Aug  8 11:06:06 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:06:06 -0000
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-4-git-send-email-gregory.clement@free-electrons.com>

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 +++++
 arch/arm/mm/cache-l2x0.c                        |  259 ++++++++++++++++++++++-
 2 files changed, 304 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/hardware/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
new file mode 100644
index 0000000..65dad20
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -0,0 +1,51 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3591940..25a41df 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,6 +25,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-aurora-l2.h>
 
 #define CACHE_LINE_SIZE		32
 
@@ -33,6 +34,11 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -275,6 +281,130 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static unsigned long calc_range_end(unsigned long start, unsigned long end)
+{
+	unsigned long range_end;
+
+	BUG_ON(start & (CACHE_LINE_SIZE - 1));
+	BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+	/*
+	 * Try to process all cache lines between 'start' and 'end'.
+	 */
+	range_end = end;
+
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (range_end > start + MAX_RANGE_SIZE)
+		range_end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+		range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+	return range_end;
+}
+
+static void aurora_pa_range(unsigned long start, unsigned long end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	/*
+	 * Make sure 'start' and 'end' reference the same page, as
+	 * L2 is PIPT and range operations only do a TLB lookup on
+	 * the start address.
+	 */
+	BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+	writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel(end, l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * Clean and invalidate partial first cache line.
+	 */
+	if (start & (CACHE_LINE_SIZE - 1)) {
+		writel((start & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+	}
+
+	/*
+	 * Clean and invalidate partial last cache line.
+	 */
+	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
+		writel((end & ~(CACHE_LINE_SIZE - 1)) & ~0x1f,
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		end &= ~(CACHE_LINE_SIZE - 1);
+	}
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		unsigned long range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+
+	dsb();
+}
+
+static void aurora_clean_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+
+	dsb();
+}
+
+static void aurora_flush_range(unsigned long start, unsigned long end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			unsigned long range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+	dsb();
+}
+
+
 
 static void l2x0_disable(void)
 {
@@ -292,11 +422,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +449,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = 3;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -340,6 +481,30 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+
+		switch ((aux >> 13) & 0xf) {
+		case 3:
+			ways = 4;
+			break;
+		case 7:
+			ways = 8;
+			break;
+		case 11:
+			ways = 16;
+			break;
+		case 15:
+			ways = 32;
+			break;
+		default:
+			ways = 8;
+			break;
+		}
+		way_size_shift = 2;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -353,7 +518,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -489,6 +655,12 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
@@ -534,6 +706,48 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	u32 u;
+
+	u = readl(l2x0_base + L2X0_CTRL);
+	if (!(u & 1)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands()
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= 0x100;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -565,10 +779,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-cache-no-outer",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-cache-with-outer",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -597,6 +838,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5



From gregory.clement at free-electrons.com  Thu Aug  9 12:49:15 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Thu, 09 Aug 2012 16:49:15 -0000
Subject: [RFC 2 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
In-Reply-To: <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
References: <20120808151946.GE4579@mudshark.cambridge.arm.com>
 <1344530925-25857-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344530925-25857-2-git-send-email-gregory.clement@free-electrons.com>

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/include/asm/hardware/cache-aurora-l2.h |   51 +++++
 arch/arm/mm/cache-l2x0.c                        |  274 ++++++++++++++++++++++-
 2 files changed, 319 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/include/asm/hardware/cache-aurora-l2.h

diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h
new file mode 100644
index 0000000..65dad20
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h
@@ -0,0 +1,51 @@
+/*
+ * AURORA shared L2 cache controller support
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
+#define __ASM_ARM_HARDWARE_AURORA_L2_H
+
+#define AURORA_SYNC_REG		    0x700
+#define AURORA_RANGE_BASE_ADDR_REG  0x720
+#define AURORA_FLUSH_PHY_ADDR_REG   0x7f0
+#define AURORA_INVAL_RANGE_REG	    0x774
+#define AURORA_CLEAN_RANGE_REG	    0x7b4
+#define AURORA_FLUSH_RANGE_REG	    0x7f4
+
+#define AURORA_ACR_REPLACEMENT_OFFSET	    27
+#define AURORA_ACR_REPLACEMENT_MASK	     \
+	(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR    \
+	(0 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_LFSR     \
+	(1 << AURORA_ACR_REPLACEMENT_OFFSET)
+#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
+	(3 << AURORA_ACR_REPLACEMENT_OFFSET)
+
+#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET	0
+#define AURORA_ACR_FORCE_WRITE_POLICY_MASK	\
+	(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_POLICY_DIS	\
+	(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_BACK_POLICY	\
+	(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+#define AURORA_ACR_FORCE_WRITE_THRO_POLICY	\
+	(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
+
+#define MAX_RANGE_SIZE		1024
+
+/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
+ * the distinction between a number coming from hardware and a number
+ * coming from the device tree */
+#define AURORA_CACHE_ID	       0x100
+
+#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3591940..036ad71 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -25,14 +25,33 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-aurora-l2.h>
 
 #define CACHE_LINE_SIZE		32
 
+#ifdef CONFIG_ARM_LPAE
+/*
+ * On Aurora if LPAE is activated then when writting in a 32bits
+ * adress in regsiter actual physical address is
+ * {bits[3:0],bits[31:5],00000}. And if not bits[4:0] must be set to
+ * 0x0.
+ */
+
+#define AURORA_LPAE(addr)   ((((addr)>>32)&0xf)|((addr)&~0xf))
+#else
+#define AURORA_LPAE(addr)   (addr)
+#endif
+
 static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+static int l2_wt_override;
+
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32  cache_id_part_number_from_dt;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -275,6 +294,132 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
+/*
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive, while the hardware cache range operations use
+ * inclusive start and end addresses.
+ */
+static phys_addr_t calc_range_end(phys_addr_t start, phys_addr_t end)
+{
+	phys_addr_t range_end;
+
+	BUG_ON(start & (CACHE_LINE_SIZE - 1));
+	BUG_ON(end & (CACHE_LINE_SIZE - 1));
+
+	/*
+	 * Try to process all cache lines between 'start' and 'end'.
+	 */
+	range_end = end;
+
+	/*
+	 * Limit the number of cache lines processed at once,
+	 * since cache range operations stall the CPU pipeline
+	 * until completion.
+	 */
+	if (range_end > start + MAX_RANGE_SIZE)
+		range_end = start + MAX_RANGE_SIZE;
+
+	/*
+	 * Cache range operations can't straddle a page boundary.
+	 */
+	if (range_end > (start | (PAGE_SIZE - 1)) + 1)
+		range_end = (start | (PAGE_SIZE - 1)) + 1;
+
+	return range_end;
+}
+
+static void aurora_pa_range(phys_addr_t start, phys_addr_t end,
+			unsigned long offset)
+{
+	unsigned long flags;
+
+	/*
+	 * Make sure 'start' and 'end' reference the same page, as
+	 * L2 is PIPT and range operations only do a TLB lookup on
+	 * the start address.
+	 */
+	BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+	raw_spin_lock_irqsave(&l2x0_lock, flags);
+
+
+	writel_relaxed(AURORA_LPAE(start), l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
+	writel_relaxed(AURORA_LPAE(end), l2x0_base + offset);
+	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+
+	cache_sync();
+}
+
+static void aurora_inv_range(phys_addr_t start, phys_addr_t end)
+{
+	/*
+	 * Clean and invalidate partial first cache line.
+	 */
+	if (start & (CACHE_LINE_SIZE - 1)) {
+		writel_relaxed(AURORA_LPAE((start & ~(CACHE_LINE_SIZE - 1)) & ~0x1f),
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+	}
+
+	/*
+	 * Clean and invalidate partial last cache line.
+	 */
+	if (start < end && end & (CACHE_LINE_SIZE - 1)) {
+		writel_relaxed(AURORA_LPAE((end & ~(CACHE_LINE_SIZE - 1)) & ~0x1f),
+			l2x0_base + AURORA_FLUSH_PHY_ADDR_REG);
+		cache_sync();
+		end &= ~(CACHE_LINE_SIZE - 1);
+	}
+
+	/*
+	 * Invalidate all full cache lines between 'start' and 'end'.
+	 */
+	while (start < end) {
+		phys_addr_t range_end = calc_range_end(start, end);
+		aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+				AURORA_INVAL_RANGE_REG);
+		start = range_end;
+	}
+
+	dsb();
+}
+
+static void aurora_clean_range(phys_addr_t start, phys_addr_t end)
+{
+	/*
+	 * If L2 is forced to WT, the L2 will always be clean and we
+	 * don't need to do anything here.
+	 */
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			phys_addr_t range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_CLEAN_RANGE_REG);
+			start = range_end;
+		}
+	}
+
+	dsb();
+}
+
+static void aurora_flush_range(phys_addr_t start, phys_addr_t end)
+{
+	if (!l2_wt_override) {
+		start &= ~(CACHE_LINE_SIZE - 1);
+		end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
+		while (start != end) {
+			phys_addr_t range_end = calc_range_end(start, end);
+			aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
+					AURORA_FLUSH_RANGE_REG);
+			start = range_end;
+		}
+	}
+	dsb();
+}
+
+
 
 static void l2x0_disable(void)
 {
@@ -292,11 +437,18 @@ static void l2x0_unlock(u32 cache_id)
 	int lockregs;
 	int i;
 
-	if (cache_id == L2X0_CACHE_ID_PART_L310)
+	switch (cache_id) {
+	case L2X0_CACHE_ID_PART_L310:
 		lockregs = 8;
-	else
+		break;
+	case AURORA_CACHE_ID:
+		lockregs = 4;
+		break;
+	default:
 		/* L210 and unknown types */
 		lockregs = 1;
+		break;
+	}
 
 	for (i = 0; i < lockregs; i++) {
 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
@@ -312,18 +464,22 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	u32 cache_id;
 	u32 way_size = 0;
 	int ways;
+	int way_size_shift = 3;
 	const char *type;
 
 	l2x0_base = base;
-
-	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+	if (cache_id_part_number_from_dt)
+		cache_id = cache_id_part_number_from_dt;
+	else
+		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
+			& L2X0_CACHE_ID_PART_MASK;
 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
 	aux &= aux_mask;
 	aux |= aux_val;
 
 	/* Determine the number of ways */
-	switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+	switch (cache_id) {
 	case L2X0_CACHE_ID_PART_L310:
 		if (aux & (1 << 16))
 			ways = 16;
@@ -340,6 +496,30 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		ways = (aux >> 13) & 0xf;
 		type = "L210";
 		break;
+
+	case AURORA_CACHE_ID:
+		sync_reg_offset = AURORA_SYNC_REG;
+
+		switch ((aux >> 13) & 0xf) {
+		case 3:
+			ways = 4;
+			break;
+		case 7:
+			ways = 8;
+			break;
+		case 11:
+			ways = 16;
+			break;
+		case 15:
+			ways = 32;
+			break;
+		default:
+			ways = 8;
+			break;
+		}
+		way_size_shift = 2;
+		type = "Aurora";
+		break;
 	default:
 		/* Assume unknown chips have 8 ways */
 		ways = 8;
@@ -353,7 +533,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 	 * L2 cache Size =  Way size * Number of ways
 	 */
 	way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-	way_size = 1 << (way_size + 3);
+	way_size = 1 << (way_size + way_size_shift);
+
 	l2x0_size = ways * way_size * SZ_1K;
 
 	/*
@@ -489,6 +670,12 @@ static void __init pl310_save(void)
 	}
 }
 
+static void aurora_save(void)
+{
+	l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
 static void l2x0_resume(void)
 {
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
@@ -534,6 +721,48 @@ static void pl310_resume(void)
 	l2x0_resume();
 }
 
+static void aurora_resume(void)
+{
+	u32 u;
+
+	u = readl(l2x0_base + L2X0_CTRL);
+	if (!(u & 1)) {
+		writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
+		writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+	}
+}
+
+static void __init aurora_broadcast_l2_commands(void)
+{
+	__u32 u;
+	/* Enable Broadcasting of cache commands to L2*/
+	__asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+	u |= 0x100;		/* Set the FW bit */
+	__asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+}
+
+static void __init aurora_of_setup(const struct device_node *np,
+				u32 *aux_val, u32 *aux_mask)
+{
+	u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+	u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+
+	of_property_read_u32(np, "cache-id-part",
+			&cache_id_part_number_from_dt);
+
+	/* Determine and save the write policy */
+	l2_wt_override = of_property_read_bool(np, "wt-override");
+
+	if (l2_wt_override) {
+		val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+	}
+
+	*aux_val &= ~mask;
+	*aux_val |= val;
+	*aux_mask &= ~mask;
+}
+
 static const struct l2x0_of_data pl310_data = {
 	.setup = pl310_of_setup,
 	.save  = pl310_save,
@@ -565,10 +794,37 @@ static const struct l2x0_of_data l2x0_data = {
 	},
 };
 
+static const struct l2x0_of_data aurora_with_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+		.inv_range   = aurora_inv_range,
+		.clean_range = aurora_clean_range,
+		.flush_range = aurora_flush_range,
+		.sync        = l2x0_cache_sync,
+		.flush_all   = l2x0_flush_all,
+		.inv_all     = l2x0_inv_all,
+		.disable     = l2x0_disable,
+	},
+};
+
+static const struct l2x0_of_data aurora_no_outer_data = {
+	.setup = aurora_of_setup,
+	.save  = aurora_save,
+	.outer_cache = {
+		.resume      = aurora_resume,
+	},
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
 	{ .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
 	{ .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
 	{ .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+	{ .compatible = "marvell,aurora-cache-no-outer",
+	  .data = (void *)&aurora_no_outer_data},
+	{ .compatible = "marvell,aurora-cache-with-outer",
+	  .data = (void *)&aurora_with_outer_data},
 	{}
 };
 
@@ -597,6 +853,12 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 		if (data->setup)
 			data->setup(np, &aux_val, &aux_mask);
+
+
+		/* For aurora cache in no outer mode select the
+		 * correct mode using the coprocessor*/
+		if (data == &aurora_no_outer_data)
+			aurora_broadcast_l2_commands();
 	}
 
 	if (data->save)
-- 
1.7.9.5



From u.kleine-koenig at pengutronix.de  Thu Aug  9 13:22:03 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 09 Aug 2012 17:22:03 -0000
Subject: [PATCH] pinctrl: pinctrl-imx: add imx35 pinctrl driver
In-Reply-To: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1343921942-22079-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1344529412-18053-1-git-send-email-u.kleine-koenig@pengutronix.de>

This is mostly cut'n'paste from the imx51 pinctrl driver. The data was
generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx35.h.

Cc: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Acked-by: Dong Aisheng <dong.aisheng at linaro.org>
Cc: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
--
Changes since (implicit) v1,
id:1343921942-22079-1-git-send-email-u.kleine-koenig at pengutronix.de

 - remove references to file names in binding documentation
 - remove sed commands from comments in driver
 - add explicit numbers for pins and functions

@Stephen and Dong: I assumed your ack even though we didn't talk about
adding numbers for the functions. If you don't like these please scream
before the patch makes it in :-)
---
 .../bindings/pinctrl/fsl,imx35-pinctrl.txt         |  984 ++++++++++++
 drivers/pinctrl/Kconfig                            |    8 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-imx35.c                    | 1595 ++++++++++++++++++++
 4 files changed, 2588 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-imx35.c

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
new file mode 100644
index 0000000..84a549b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
@@ -0,0 +1,984 @@
+* Freescale IMX35 IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx35-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_DRIVE_VOLAGAGE_18	(1 << 13)
+PAD_CTL_DRIVE_VOLAGAGE_33	(0 << 13)
+PAD_CTL_HYS			(1 << 8)
+PAD_CTL_PKE			(1 << 7)
+PAD_CTL_PUE			(1 << 6)
+PAD_CTL_PUS_100K_DOWN		(0 << 4)
+PAD_CTL_PUS_47K_UP		(1 << 4)
+PAD_CTL_PUS_100K_UP		(2 << 4)
+PAD_CTL_PUS_22K_UP		(3 << 4)
+PAD_CTL_ODE_CMOS		(0 << 3)
+PAD_CTL_ODE_OPENDRAIN		(1 << 3)
+PAD_CTL_DSE_NOMINAL		(0 << 1)
+PAD_CTL_DSE_HIGH		(1 << 1)
+PAD_CTL_DSE_MAX			(2 << 1)
+PAD_CTL_SRE_FAST		(1 << 0)
+PAD_CTL_SRE_SLOW		(0 << 0)
+
+See below for available PIN_FUNC_ID for imx35:
+0 MX35_PAD_CAPTURE__GPT_CAPIN1
+1 MX35_PAD_CAPTURE__GPT_CMPOUT2
+2 MX35_PAD_CAPTURE__CSPI2_SS1
+3 MX35_PAD_CAPTURE__EPIT1_EPITO
+4 MX35_PAD_CAPTURE__CCM_CLK32K
+5 MX35_PAD_CAPTURE__GPIO1_4
+6 MX35_PAD_COMPARE__GPT_CMPOUT1
+7 MX35_PAD_COMPARE__GPT_CAPIN2
+8 MX35_PAD_COMPARE__GPT_CMPOUT3
+9 MX35_PAD_COMPARE__EPIT2_EPITO
+10 MX35_PAD_COMPARE__GPIO1_5
+11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
+12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
+13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
+14 MX35_PAD_WDOG_RST__GPIO1_6
+15 MX35_PAD_GPIO1_0__GPIO1_0
+16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
+17 MX35_PAD_GPIO1_0__OWIRE_LINE
+18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
+19 MX35_PAD_GPIO1_1__GPIO1_1
+20 MX35_PAD_GPIO1_1__PWM_PWMO
+21 MX35_PAD_GPIO1_1__CSPI1_SS2
+22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
+23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
+24 MX35_PAD_GPIO2_0__GPIO2_0
+25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
+26 MX35_PAD_GPIO3_0__GPIO3_0
+27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
+28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
+29 MX35_PAD_POR_B__CCM_POR_B
+30 MX35_PAD_CLKO__CCM_CLKO
+31 MX35_PAD_CLKO__GPIO1_8
+32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
+33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
+34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
+35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
+36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
+37 MX35_PAD_VSTBY__CCM_VSTBY
+38 MX35_PAD_VSTBY__GPIO1_7
+39 MX35_PAD_A0__EMI_EIM_DA_L_0
+40 MX35_PAD_A1__EMI_EIM_DA_L_1
+41 MX35_PAD_A2__EMI_EIM_DA_L_2
+42 MX35_PAD_A3__EMI_EIM_DA_L_3
+43 MX35_PAD_A4__EMI_EIM_DA_L_4
+44 MX35_PAD_A5__EMI_EIM_DA_L_5
+45 MX35_PAD_A6__EMI_EIM_DA_L_6
+46 MX35_PAD_A7__EMI_EIM_DA_L_7
+47 MX35_PAD_A8__EMI_EIM_DA_H_8
+48 MX35_PAD_A9__EMI_EIM_DA_H_9
+49 MX35_PAD_A10__EMI_EIM_DA_H_10
+50 MX35_PAD_MA10__EMI_MA10
+51 MX35_PAD_A11__EMI_EIM_DA_H_11
+52 MX35_PAD_A12__EMI_EIM_DA_H_12
+53 MX35_PAD_A13__EMI_EIM_DA_H_13
+54 MX35_PAD_A14__EMI_EIM_DA_H2_14
+55 MX35_PAD_A15__EMI_EIM_DA_H2_15
+56 MX35_PAD_A16__EMI_EIM_A_16
+57 MX35_PAD_A17__EMI_EIM_A_17
+58 MX35_PAD_A18__EMI_EIM_A_18
+59 MX35_PAD_A19__EMI_EIM_A_19
+60 MX35_PAD_A20__EMI_EIM_A_20
+61 MX35_PAD_A21__EMI_EIM_A_21
+62 MX35_PAD_A22__EMI_EIM_A_22
+63 MX35_PAD_A23__EMI_EIM_A_23
+64 MX35_PAD_A24__EMI_EIM_A_24
+65 MX35_PAD_A25__EMI_EIM_A_25
+66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
+67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
+68 MX35_PAD_SD0__EMI_DRAM_D_0
+69 MX35_PAD_SD1__EMI_DRAM_D_1
+70 MX35_PAD_SD2__EMI_DRAM_D_2
+71 MX35_PAD_SD3__EMI_DRAM_D_3
+72 MX35_PAD_SD4__EMI_DRAM_D_4
+73 MX35_PAD_SD5__EMI_DRAM_D_5
+74 MX35_PAD_SD6__EMI_DRAM_D_6
+75 MX35_PAD_SD7__EMI_DRAM_D_7
+76 MX35_PAD_SD8__EMI_DRAM_D_8
+77 MX35_PAD_SD9__EMI_DRAM_D_9
+78 MX35_PAD_SD10__EMI_DRAM_D_10
+79 MX35_PAD_SD11__EMI_DRAM_D_11
+80 MX35_PAD_SD12__EMI_DRAM_D_12
+81 MX35_PAD_SD13__EMI_DRAM_D_13
+82 MX35_PAD_SD14__EMI_DRAM_D_14
+83 MX35_PAD_SD15__EMI_DRAM_D_15
+84 MX35_PAD_SD16__EMI_DRAM_D_16
+85 MX35_PAD_SD17__EMI_DRAM_D_17
+86 MX35_PAD_SD18__EMI_DRAM_D_18
+87 MX35_PAD_SD19__EMI_DRAM_D_19
+88 MX35_PAD_SD20__EMI_DRAM_D_20
+89 MX35_PAD_SD21__EMI_DRAM_D_21
+90 MX35_PAD_SD22__EMI_DRAM_D_22
+91 MX35_PAD_SD23__EMI_DRAM_D_23
+92 MX35_PAD_SD24__EMI_DRAM_D_24
+93 MX35_PAD_SD25__EMI_DRAM_D_25
+94 MX35_PAD_SD26__EMI_DRAM_D_26
+95 MX35_PAD_SD27__EMI_DRAM_D_27
+96 MX35_PAD_SD28__EMI_DRAM_D_28
+97 MX35_PAD_SD29__EMI_DRAM_D_29
+98 MX35_PAD_SD30__EMI_DRAM_D_30
+99 MX35_PAD_SD31__EMI_DRAM_D_31
+100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
+101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
+102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
+103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
+104 MX35_PAD_EB0__EMI_EIM_EB0_B
+105 MX35_PAD_EB1__EMI_EIM_EB1_B
+106 MX35_PAD_OE__EMI_EIM_OE
+107 MX35_PAD_CS0__EMI_EIM_CS0
+108 MX35_PAD_CS1__EMI_EIM_CS1
+109 MX35_PAD_CS1__EMI_NANDF_CE3
+110 MX35_PAD_CS2__EMI_EIM_CS2
+111 MX35_PAD_CS3__EMI_EIM_CS3
+112 MX35_PAD_CS4__EMI_EIM_CS4
+113 MX35_PAD_CS4__EMI_DTACK_B
+114 MX35_PAD_CS4__EMI_NANDF_CE1
+115 MX35_PAD_CS4__GPIO1_20
+116 MX35_PAD_CS5__EMI_EIM_CS5
+117 MX35_PAD_CS5__CSPI2_SS2
+118 MX35_PAD_CS5__CSPI1_SS2
+119 MX35_PAD_CS5__EMI_NANDF_CE2
+120 MX35_PAD_CS5__GPIO1_21
+121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
+122 MX35_PAD_NF_CE0__GPIO1_22
+123 MX35_PAD_ECB__EMI_EIM_ECB
+124 MX35_PAD_LBA__EMI_EIM_LBA
+125 MX35_PAD_BCLK__EMI_EIM_BCLK
+126 MX35_PAD_RW__EMI_EIM_RW
+127 MX35_PAD_RAS__EMI_DRAM_RAS
+128 MX35_PAD_CAS__EMI_DRAM_CAS
+129 MX35_PAD_SDWE__EMI_DRAM_SDWE
+130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
+131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
+132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
+133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
+134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
+135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
+136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
+137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
+138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
+139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
+140 MX35_PAD_NFWE_B__GPIO2_18
+141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
+142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
+143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
+144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
+145 MX35_PAD_NFRE_B__GPIO2_19
+146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
+147 MX35_PAD_NFALE__EMI_NANDF_ALE
+148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
+149 MX35_PAD_NFALE__IPU_DISPB_CS0
+150 MX35_PAD_NFALE__GPIO2_20
+151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
+152 MX35_PAD_NFCLE__EMI_NANDF_CLE
+153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
+154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
+155 MX35_PAD_NFCLE__GPIO2_21
+156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
+157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
+158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
+159 MX35_PAD_NFWP_B__IPU_DISPB_WR
+160 MX35_PAD_NFWP_B__GPIO2_22
+161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
+162 MX35_PAD_NFRB__EMI_NANDF_RB
+163 MX35_PAD_NFRB__IPU_DISPB_RD
+164 MX35_PAD_NFRB__GPIO2_23
+165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
+166 MX35_PAD_D15__EMI_EIM_D_15
+167 MX35_PAD_D14__EMI_EIM_D_14
+168 MX35_PAD_D13__EMI_EIM_D_13
+169 MX35_PAD_D12__EMI_EIM_D_12
+170 MX35_PAD_D11__EMI_EIM_D_11
+171 MX35_PAD_D10__EMI_EIM_D_10
+172 MX35_PAD_D9__EMI_EIM_D_9
+173 MX35_PAD_D8__EMI_EIM_D_8
+174 MX35_PAD_D7__EMI_EIM_D_7
+175 MX35_PAD_D6__EMI_EIM_D_6
+176 MX35_PAD_D5__EMI_EIM_D_5
+177 MX35_PAD_D4__EMI_EIM_D_4
+178 MX35_PAD_D3__EMI_EIM_D_3
+179 MX35_PAD_D2__EMI_EIM_D_2
+180 MX35_PAD_D1__EMI_EIM_D_1
+181 MX35_PAD_D0__EMI_EIM_D_0
+182 MX35_PAD_CSI_D8__IPU_CSI_D_8
+183 MX35_PAD_CSI_D8__KPP_COL_0
+184 MX35_PAD_CSI_D8__GPIO1_20
+185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
+186 MX35_PAD_CSI_D9__IPU_CSI_D_9
+187 MX35_PAD_CSI_D9__KPP_COL_1
+188 MX35_PAD_CSI_D9__GPIO1_21
+189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
+190 MX35_PAD_CSI_D10__IPU_CSI_D_10
+191 MX35_PAD_CSI_D10__KPP_COL_2
+192 MX35_PAD_CSI_D10__GPIO1_22
+193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
+194 MX35_PAD_CSI_D11__IPU_CSI_D_11
+195 MX35_PAD_CSI_D11__KPP_COL_3
+196 MX35_PAD_CSI_D11__GPIO1_23
+197 MX35_PAD_CSI_D12__IPU_CSI_D_12
+198 MX35_PAD_CSI_D12__KPP_ROW_0
+199 MX35_PAD_CSI_D12__GPIO1_24
+200 MX35_PAD_CSI_D13__IPU_CSI_D_13
+201 MX35_PAD_CSI_D13__KPP_ROW_1
+202 MX35_PAD_CSI_D13__GPIO1_25
+203 MX35_PAD_CSI_D14__IPU_CSI_D_14
+204 MX35_PAD_CSI_D14__KPP_ROW_2
+205 MX35_PAD_CSI_D14__GPIO1_26
+206 MX35_PAD_CSI_D15__IPU_CSI_D_15
+207 MX35_PAD_CSI_D15__KPP_ROW_3
+208 MX35_PAD_CSI_D15__GPIO1_27
+209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
+210 MX35_PAD_CSI_MCLK__GPIO1_28
+211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
+212 MX35_PAD_CSI_VSYNC__GPIO1_29
+213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
+214 MX35_PAD_CSI_HSYNC__GPIO1_30
+215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
+216 MX35_PAD_CSI_PIXCLK__GPIO1_31
+217 MX35_PAD_I2C1_CLK__I2C1_SCL
+218 MX35_PAD_I2C1_CLK__GPIO2_24
+219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
+220 MX35_PAD_I2C1_DAT__I2C1_SDA
+221 MX35_PAD_I2C1_DAT__GPIO2_25
+222 MX35_PAD_I2C2_CLK__I2C2_SCL
+223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
+224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
+225 MX35_PAD_I2C2_CLK__GPIO2_26
+226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
+227 MX35_PAD_I2C2_DAT__I2C2_SDA
+228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
+229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
+230 MX35_PAD_I2C2_DAT__GPIO2_27
+231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
+232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
+233 MX35_PAD_STXD4__GPIO2_28
+234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
+235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
+236 MX35_PAD_SRXD4__GPIO2_29
+237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
+238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
+239 MX35_PAD_SCK4__GPIO2_30
+240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
+241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
+242 MX35_PAD_STXFS4__GPIO2_31
+243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
+244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
+245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
+246 MX35_PAD_STXD5__CSPI2_MOSI
+247 MX35_PAD_STXD5__GPIO1_0
+248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
+249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
+250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
+251 MX35_PAD_SRXD5__CSPI2_MISO
+252 MX35_PAD_SRXD5__GPIO1_1
+253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
+254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
+255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
+256 MX35_PAD_SCK5__CSPI2_SCLK
+257 MX35_PAD_SCK5__GPIO1_2
+258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
+259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
+260 MX35_PAD_STXFS5__CSPI2_RDY
+261 MX35_PAD_STXFS5__GPIO1_3
+262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
+263 MX35_PAD_SCKR__ESAI_SCKR
+264 MX35_PAD_SCKR__GPIO1_4
+265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
+266 MX35_PAD_FSR__ESAI_FSR
+267 MX35_PAD_FSR__GPIO1_5
+268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
+269 MX35_PAD_HCKR__ESAI_HCKR
+270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
+271 MX35_PAD_HCKR__CSPI2_SS0
+272 MX35_PAD_HCKR__IPU_FLASH_STROBE
+273 MX35_PAD_HCKR__GPIO1_6
+274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
+275 MX35_PAD_SCKT__ESAI_SCKT
+276 MX35_PAD_SCKT__GPIO1_7
+277 MX35_PAD_SCKT__IPU_CSI_D_0
+278 MX35_PAD_SCKT__KPP_ROW_2
+279 MX35_PAD_FST__ESAI_FST
+280 MX35_PAD_FST__GPIO1_8
+281 MX35_PAD_FST__IPU_CSI_D_1
+282 MX35_PAD_FST__KPP_ROW_3
+283 MX35_PAD_HCKT__ESAI_HCKT
+284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
+285 MX35_PAD_HCKT__GPIO1_9
+286 MX35_PAD_HCKT__IPU_CSI_D_2
+287 MX35_PAD_HCKT__KPP_COL_3
+288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
+289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
+290 MX35_PAD_TX5_RX0__CSPI2_SS2
+291 MX35_PAD_TX5_RX0__CAN2_TXCAN
+292 MX35_PAD_TX5_RX0__UART2_DTR
+293 MX35_PAD_TX5_RX0__GPIO1_10
+294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
+295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
+296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
+297 MX35_PAD_TX4_RX1__CSPI2_SS3
+298 MX35_PAD_TX4_RX1__CAN2_RXCAN
+299 MX35_PAD_TX4_RX1__UART2_DSR
+300 MX35_PAD_TX4_RX1__GPIO1_11
+301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
+302 MX35_PAD_TX4_RX1__KPP_ROW_0
+303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
+304 MX35_PAD_TX3_RX2__I2C3_SCL
+305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
+306 MX35_PAD_TX3_RX2__GPIO1_12
+307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
+308 MX35_PAD_TX3_RX2__KPP_ROW_1
+309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
+310 MX35_PAD_TX2_RX3__I2C3_SDA
+311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
+312 MX35_PAD_TX2_RX3__GPIO1_13
+313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
+314 MX35_PAD_TX2_RX3__KPP_COL_0
+315 MX35_PAD_TX1__ESAI_TX1
+316 MX35_PAD_TX1__CCM_PMIC_RDY
+317 MX35_PAD_TX1__CSPI1_SS2
+318 MX35_PAD_TX1__EMI_NANDF_CE3
+319 MX35_PAD_TX1__UART2_RI
+320 MX35_PAD_TX1__GPIO1_14
+321 MX35_PAD_TX1__IPU_CSI_D_6
+322 MX35_PAD_TX1__KPP_COL_1
+323 MX35_PAD_TX0__ESAI_TX0
+324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
+325 MX35_PAD_TX0__CSPI1_SS3
+326 MX35_PAD_TX0__EMI_DTACK_B
+327 MX35_PAD_TX0__UART2_DCD
+328 MX35_PAD_TX0__GPIO1_15
+329 MX35_PAD_TX0__IPU_CSI_D_7
+330 MX35_PAD_TX0__KPP_COL_2
+331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
+332 MX35_PAD_CSPI1_MOSI__GPIO1_16
+333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
+334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
+335 MX35_PAD_CSPI1_MISO__GPIO1_17
+336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
+337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
+338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
+339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
+340 MX35_PAD_CSPI1_SS0__GPIO1_18
+341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
+342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
+343 MX35_PAD_CSPI1_SS1__PWM_PWMO
+344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
+345 MX35_PAD_CSPI1_SS1__GPIO1_19
+346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
+347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
+348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
+349 MX35_PAD_CSPI1_SCLK__GPIO3_4
+350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
+351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
+352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
+353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
+354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
+355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
+356 MX35_PAD_RXD1__UART1_RXD_MUX
+357 MX35_PAD_RXD1__CSPI2_MOSI
+358 MX35_PAD_RXD1__KPP_COL_4
+359 MX35_PAD_RXD1__GPIO3_6
+360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
+361 MX35_PAD_TXD1__UART1_TXD_MUX
+362 MX35_PAD_TXD1__CSPI2_MISO
+363 MX35_PAD_TXD1__KPP_COL_5
+364 MX35_PAD_TXD1__GPIO3_7
+365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
+366 MX35_PAD_RTS1__UART1_RTS
+367 MX35_PAD_RTS1__CSPI2_SCLK
+368 MX35_PAD_RTS1__I2C3_SCL
+369 MX35_PAD_RTS1__IPU_CSI_D_0
+370 MX35_PAD_RTS1__KPP_COL_6
+371 MX35_PAD_RTS1__GPIO3_8
+372 MX35_PAD_RTS1__EMI_NANDF_CE1
+373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
+374 MX35_PAD_CTS1__UART1_CTS
+375 MX35_PAD_CTS1__CSPI2_RDY
+376 MX35_PAD_CTS1__I2C3_SDA
+377 MX35_PAD_CTS1__IPU_CSI_D_1
+378 MX35_PAD_CTS1__KPP_COL_7
+379 MX35_PAD_CTS1__GPIO3_9
+380 MX35_PAD_CTS1__EMI_NANDF_CE2
+381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
+382 MX35_PAD_RXD2__UART2_RXD_MUX
+383 MX35_PAD_RXD2__KPP_ROW_4
+384 MX35_PAD_RXD2__GPIO3_10
+385 MX35_PAD_TXD2__UART2_TXD_MUX
+386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
+387 MX35_PAD_TXD2__KPP_ROW_5
+388 MX35_PAD_TXD2__GPIO3_11
+389 MX35_PAD_RTS2__UART2_RTS
+390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
+391 MX35_PAD_RTS2__CAN2_RXCAN
+392 MX35_PAD_RTS2__IPU_CSI_D_2
+393 MX35_PAD_RTS2__KPP_ROW_6
+394 MX35_PAD_RTS2__GPIO3_12
+395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
+396 MX35_PAD_RTS2__UART3_RXD_MUX
+397 MX35_PAD_CTS2__UART2_CTS
+398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
+399 MX35_PAD_CTS2__CAN2_TXCAN
+400 MX35_PAD_CTS2__IPU_CSI_D_3
+401 MX35_PAD_CTS2__KPP_ROW_7
+402 MX35_PAD_CTS2__GPIO3_13
+403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
+404 MX35_PAD_CTS2__UART3_TXD_MUX
+405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
+406 MX35_PAD_TCK__SJC_TCK
+407 MX35_PAD_TMS__SJC_TMS
+408 MX35_PAD_TDI__SJC_TDI
+409 MX35_PAD_TDO__SJC_TDO
+410 MX35_PAD_TRSTB__SJC_TRSTB
+411 MX35_PAD_DE_B__SJC_DE_B
+412 MX35_PAD_SJC_MOD__SJC_MOD
+413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
+414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
+415 MX35_PAD_USBOTG_PWR__GPIO3_14
+416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
+417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
+418 MX35_PAD_USBOTG_OC__GPIO3_15
+419 MX35_PAD_LD0__IPU_DISPB_DAT_0
+420 MX35_PAD_LD0__GPIO2_0
+421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
+422 MX35_PAD_LD1__IPU_DISPB_DAT_1
+423 MX35_PAD_LD1__GPIO2_1
+424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
+425 MX35_PAD_LD2__IPU_DISPB_DAT_2
+426 MX35_PAD_LD2__GPIO2_2
+427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
+428 MX35_PAD_LD3__IPU_DISPB_DAT_3
+429 MX35_PAD_LD3__GPIO2_3
+430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
+431 MX35_PAD_LD4__IPU_DISPB_DAT_4
+432 MX35_PAD_LD4__GPIO2_4
+433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
+434 MX35_PAD_LD5__IPU_DISPB_DAT_5
+435 MX35_PAD_LD5__GPIO2_5
+436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
+437 MX35_PAD_LD6__IPU_DISPB_DAT_6
+438 MX35_PAD_LD6__GPIO2_6
+439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
+440 MX35_PAD_LD7__IPU_DISPB_DAT_7
+441 MX35_PAD_LD7__GPIO2_7
+442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
+443 MX35_PAD_LD8__IPU_DISPB_DAT_8
+444 MX35_PAD_LD8__GPIO2_8
+445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
+446 MX35_PAD_LD9__IPU_DISPB_DAT_9
+447 MX35_PAD_LD9__GPIO2_9
+448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
+449 MX35_PAD_LD10__IPU_DISPB_DAT_10
+450 MX35_PAD_LD10__GPIO2_10
+451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
+452 MX35_PAD_LD11__IPU_DISPB_DAT_11
+453 MX35_PAD_LD11__GPIO2_11
+454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
+455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
+456 MX35_PAD_LD12__IPU_DISPB_DAT_12
+457 MX35_PAD_LD12__GPIO2_12
+458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
+459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
+460 MX35_PAD_LD13__IPU_DISPB_DAT_13
+461 MX35_PAD_LD13__GPIO2_13
+462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
+463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
+464 MX35_PAD_LD14__IPU_DISPB_DAT_14
+465 MX35_PAD_LD14__GPIO2_14
+466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
+467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
+468 MX35_PAD_LD15__IPU_DISPB_DAT_15
+469 MX35_PAD_LD15__GPIO2_15
+470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
+471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
+472 MX35_PAD_LD16__IPU_DISPB_DAT_16
+473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
+474 MX35_PAD_LD16__GPIO2_16
+475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
+476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
+477 MX35_PAD_LD17__IPU_DISPB_DAT_17
+478 MX35_PAD_LD17__IPU_DISPB_CS2
+479 MX35_PAD_LD17__GPIO2_17
+480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
+481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
+482 MX35_PAD_LD18__IPU_DISPB_DAT_18
+483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
+484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
+485 MX35_PAD_LD18__ESDHC3_CMD
+486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
+487 MX35_PAD_LD18__GPIO3_24
+488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
+489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
+490 MX35_PAD_LD19__IPU_DISPB_DAT_19
+491 MX35_PAD_LD19__IPU_DISPB_BCLK
+492 MX35_PAD_LD19__IPU_DISPB_CS1
+493 MX35_PAD_LD19__ESDHC3_CLK
+494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
+495 MX35_PAD_LD19__GPIO3_25
+496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
+497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
+498 MX35_PAD_LD20__IPU_DISPB_DAT_20
+499 MX35_PAD_LD20__IPU_DISPB_CS0
+500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
+501 MX35_PAD_LD20__ESDHC3_DAT0
+502 MX35_PAD_LD20__GPIO3_26
+503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
+504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
+505 MX35_PAD_LD21__IPU_DISPB_DAT_21
+506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
+507 MX35_PAD_LD21__IPU_DISPB_SER_RS
+508 MX35_PAD_LD21__ESDHC3_DAT1
+509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
+510 MX35_PAD_LD21__GPIO3_27
+511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
+512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
+513 MX35_PAD_LD22__IPU_DISPB_DAT_22
+514 MX35_PAD_LD22__IPU_DISPB_WR
+515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
+516 MX35_PAD_LD22__ESDHC3_DAT2
+517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
+518 MX35_PAD_LD22__GPIO3_28
+519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
+520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
+521 MX35_PAD_LD23__IPU_DISPB_DAT_23
+522 MX35_PAD_LD23__IPU_DISPB_RD
+523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
+524 MX35_PAD_LD23__ESDHC3_DAT3
+525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
+526 MX35_PAD_LD23__GPIO3_29
+527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
+528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
+529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
+530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
+531 MX35_PAD_D3_HSYNC__GPIO3_30
+532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
+533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
+534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
+535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
+536 MX35_PAD_D3_FPSHIFT__GPIO3_31
+537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
+538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
+539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
+540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
+541 MX35_PAD_D3_DRDY__GPIO1_0
+542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
+543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
+544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
+545 MX35_PAD_CONTRAST__GPIO1_1
+546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
+547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
+548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
+549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
+550 MX35_PAD_D3_VSYNC__GPIO1_2
+551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
+552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
+553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
+554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
+555 MX35_PAD_D3_REV__GPIO1_3
+556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
+557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
+558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
+559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
+560 MX35_PAD_D3_CLS__GPIO1_4
+561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
+562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
+563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
+565 MX35_PAD_D3_SPL__GPIO1_5
+566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
+567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
+568 MX35_PAD_SD1_CMD__ESDHC1_CMD
+569 MX35_PAD_SD1_CMD__MSHC_SCLK
+570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
+571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
+572 MX35_PAD_SD1_CMD__GPIO1_6
+573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
+574 MX35_PAD_SD1_CLK__ESDHC1_CLK
+575 MX35_PAD_SD1_CLK__MSHC_BS
+576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
+577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
+578 MX35_PAD_SD1_CLK__GPIO1_7
+579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
+580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
+581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
+582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
+583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
+584 MX35_PAD_SD1_DATA0__GPIO1_8
+585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
+586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
+587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
+588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
+589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
+590 MX35_PAD_SD1_DATA1__GPIO1_9
+591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
+592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
+593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
+594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
+595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
+596 MX35_PAD_SD1_DATA2__GPIO1_10
+597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
+598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
+599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
+600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
+601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
+602 MX35_PAD_SD1_DATA3__GPIO1_11
+603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
+604 MX35_PAD_SD2_CMD__ESDHC2_CMD
+605 MX35_PAD_SD2_CMD__I2C3_SCL
+606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
+607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
+608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
+609 MX35_PAD_SD2_CMD__GPIO2_0
+610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
+611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
+612 MX35_PAD_SD2_CLK__ESDHC2_CLK
+613 MX35_PAD_SD2_CLK__I2C3_SDA
+614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
+615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
+616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
+617 MX35_PAD_SD2_CLK__GPIO2_1
+618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
+619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
+620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
+621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
+622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
+623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
+624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
+625 MX35_PAD_SD2_DATA0__GPIO2_2
+626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
+627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
+628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
+629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
+630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
+631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
+632 MX35_PAD_SD2_DATA1__GPIO2_3
+633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
+634 MX35_PAD_SD2_DATA2__UART3_RTS
+635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
+636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
+637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
+638 MX35_PAD_SD2_DATA2__GPIO2_4
+639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
+640 MX35_PAD_SD2_DATA3__UART3_CTS
+641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
+642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
+643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
+644 MX35_PAD_SD2_DATA3__GPIO2_5
+645 MX35_PAD_ATA_CS0__ATA_CS0
+646 MX35_PAD_ATA_CS0__CSPI1_SS3
+647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
+648 MX35_PAD_ATA_CS0__GPIO2_6
+649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
+650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
+651 MX35_PAD_ATA_CS1__ATA_CS1
+652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
+653 MX35_PAD_ATA_CS1__CSPI2_SS0
+654 MX35_PAD_ATA_CS1__GPIO2_7
+655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
+656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
+657 MX35_PAD_ATA_DIOR__ATA_DIOR
+658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
+659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
+660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
+661 MX35_PAD_ATA_DIOR__CSPI2_SS1
+662 MX35_PAD_ATA_DIOR__GPIO2_8
+663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
+664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
+665 MX35_PAD_ATA_DIOW__ATA_DIOW
+666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
+667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
+668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
+669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
+670 MX35_PAD_ATA_DIOW__GPIO2_9
+671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
+672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
+673 MX35_PAD_ATA_DMACK__ATA_DMACK
+674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
+675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
+676 MX35_PAD_ATA_DMACK__CSPI2_MISO
+677 MX35_PAD_ATA_DMACK__GPIO2_10
+678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
+679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
+680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
+681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
+682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
+683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
+684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
+685 MX35_PAD_ATA_RESET_B__GPIO2_11
+686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
+687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
+688 MX35_PAD_ATA_IORDY__ATA_IORDY
+689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
+690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
+691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
+692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
+693 MX35_PAD_ATA_IORDY__GPIO2_12
+694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
+695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
+696 MX35_PAD_ATA_DATA0__ATA_DATA_0
+697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
+698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
+699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
+700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
+701 MX35_PAD_ATA_DATA0__GPIO2_13
+702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
+703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
+704 MX35_PAD_ATA_DATA1__ATA_DATA_1
+705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
+706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
+707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
+708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
+709 MX35_PAD_ATA_DATA1__GPIO2_14
+710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
+711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
+712 MX35_PAD_ATA_DATA2__ATA_DATA_2
+713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
+714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
+715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
+716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
+717 MX35_PAD_ATA_DATA2__GPIO2_15
+718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
+719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
+720 MX35_PAD_ATA_DATA3__ATA_DATA_3
+721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
+722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
+723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
+724 MX35_PAD_ATA_DATA3__GPIO2_16
+725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
+726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
+727 MX35_PAD_ATA_DATA4__ATA_DATA_4
+728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
+729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
+730 MX35_PAD_ATA_DATA4__GPIO2_17
+731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
+732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
+733 MX35_PAD_ATA_DATA5__ATA_DATA_5
+734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
+735 MX35_PAD_ATA_DATA5__GPIO2_18
+736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
+737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
+738 MX35_PAD_ATA_DATA6__ATA_DATA_6
+739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
+740 MX35_PAD_ATA_DATA6__UART1_DTR
+741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
+742 MX35_PAD_ATA_DATA6__GPIO2_19
+743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
+744 MX35_PAD_ATA_DATA7__ATA_DATA_7
+745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
+746 MX35_PAD_ATA_DATA7__UART1_DSR
+747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
+748 MX35_PAD_ATA_DATA7__GPIO2_20
+749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
+750 MX35_PAD_ATA_DATA8__ATA_DATA_8
+751 MX35_PAD_ATA_DATA8__UART3_RTS
+752 MX35_PAD_ATA_DATA8__UART1_RI
+753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
+754 MX35_PAD_ATA_DATA8__GPIO2_21
+755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
+756 MX35_PAD_ATA_DATA9__ATA_DATA_9
+757 MX35_PAD_ATA_DATA9__UART3_CTS
+758 MX35_PAD_ATA_DATA9__UART1_DCD
+759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
+760 MX35_PAD_ATA_DATA9__GPIO2_22
+761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
+762 MX35_PAD_ATA_DATA10__ATA_DATA_10
+763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
+764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
+765 MX35_PAD_ATA_DATA10__GPIO2_23
+766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
+767 MX35_PAD_ATA_DATA11__ATA_DATA_11
+768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
+769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
+770 MX35_PAD_ATA_DATA11__GPIO2_24
+771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
+772 MX35_PAD_ATA_DATA12__ATA_DATA_12
+773 MX35_PAD_ATA_DATA12__I2C3_SCL
+774 MX35_PAD_ATA_DATA12__GPIO2_25
+775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
+776 MX35_PAD_ATA_DATA13__ATA_DATA_13
+777 MX35_PAD_ATA_DATA13__I2C3_SDA
+778 MX35_PAD_ATA_DATA13__GPIO2_26
+779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
+780 MX35_PAD_ATA_DATA14__ATA_DATA_14
+781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
+782 MX35_PAD_ATA_DATA14__KPP_ROW_0
+783 MX35_PAD_ATA_DATA14__GPIO2_27
+784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
+785 MX35_PAD_ATA_DATA15__ATA_DATA_15
+786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
+787 MX35_PAD_ATA_DATA15__KPP_ROW_1
+788 MX35_PAD_ATA_DATA15__GPIO2_28
+789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
+790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
+791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
+792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
+793 MX35_PAD_ATA_INTRQ__GPIO2_29
+794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
+795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
+796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
+797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
+798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
+799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
+800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
+801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
+802 MX35_PAD_ATA_DMARQ__KPP_COL_0
+803 MX35_PAD_ATA_DMARQ__GPIO2_31
+804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
+805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
+806 MX35_PAD_ATA_DA0__ATA_DA_0
+807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
+808 MX35_PAD_ATA_DA0__KPP_COL_1
+809 MX35_PAD_ATA_DA0__GPIO3_0
+810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
+811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
+812 MX35_PAD_ATA_DA1__ATA_DA_1
+813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
+814 MX35_PAD_ATA_DA1__KPP_COL_2
+815 MX35_PAD_ATA_DA1__GPIO3_1
+816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
+817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
+818 MX35_PAD_ATA_DA2__ATA_DA_2
+819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
+820 MX35_PAD_ATA_DA2__KPP_COL_3
+821 MX35_PAD_ATA_DA2__GPIO3_2
+822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
+823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
+824 MX35_PAD_MLB_CLK__MLB_MLBCLK
+825 MX35_PAD_MLB_CLK__GPIO3_3
+826 MX35_PAD_MLB_DAT__MLB_MLBDAT
+827 MX35_PAD_MLB_DAT__GPIO3_4
+828 MX35_PAD_MLB_SIG__MLB_MLBSIG
+829 MX35_PAD_MLB_SIG__GPIO3_5
+830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
+831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
+832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
+833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
+834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
+835 MX35_PAD_FEC_TX_CLK__GPIO3_6
+836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
+837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
+838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
+839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
+840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
+841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
+842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
+843 MX35_PAD_FEC_RX_CLK__GPIO3_7
+844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
+845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
+846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
+847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
+848 MX35_PAD_FEC_RX_DV__UART3_RTS
+849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
+850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
+851 MX35_PAD_FEC_RX_DV__GPIO3_8
+852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
+853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
+854 MX35_PAD_FEC_COL__FEC_COL
+855 MX35_PAD_FEC_COL__ESDHC1_DAT7
+856 MX35_PAD_FEC_COL__UART3_CTS
+857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
+858 MX35_PAD_FEC_COL__CSPI2_RDY
+859 MX35_PAD_FEC_COL__GPIO3_9
+860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
+861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
+862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
+863 MX35_PAD_FEC_RDATA0__PWM_PWMO
+864 MX35_PAD_FEC_RDATA0__UART3_DTR
+865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
+866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
+867 MX35_PAD_FEC_RDATA0__GPIO3_10
+868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
+869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
+870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
+871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
+872 MX35_PAD_FEC_TDATA0__UART3_DSR
+873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
+874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
+875 MX35_PAD_FEC_TDATA0__GPIO3_11
+876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
+877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
+878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
+879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
+880 MX35_PAD_FEC_TX_EN__UART3_RI
+881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
+882 MX35_PAD_FEC_TX_EN__GPIO3_12
+883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
+884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
+885 MX35_PAD_FEC_MDC__FEC_MDC
+886 MX35_PAD_FEC_MDC__CAN2_TXCAN
+887 MX35_PAD_FEC_MDC__UART3_DCD
+888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
+889 MX35_PAD_FEC_MDC__GPIO3_13
+890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
+891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
+892 MX35_PAD_FEC_MDIO__FEC_MDIO
+893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
+894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
+895 MX35_PAD_FEC_MDIO__GPIO3_14
+896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
+897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
+898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
+899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
+900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
+901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
+902 MX35_PAD_FEC_TX_ERR__GPIO3_15
+903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
+904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
+905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
+906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
+907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
+908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
+909 MX35_PAD_FEC_RX_ERR__GPIO3_16
+910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
+911 MX35_PAD_FEC_CRS__FEC_CRS
+912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
+913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
+914 MX35_PAD_FEC_CRS__KPP_COL_5
+915 MX35_PAD_FEC_CRS__GPIO3_17
+916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
+917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
+918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
+919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
+920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
+921 MX35_PAD_FEC_RDATA1__KPP_COL_6
+922 MX35_PAD_FEC_RDATA1__GPIO3_18
+923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
+924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
+925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
+926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
+927 MX35_PAD_FEC_TDATA1__KPP_COL_7
+928 MX35_PAD_FEC_TDATA1__GPIO3_19
+929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
+930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
+931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
+932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
+933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
+934 MX35_PAD_FEC_RDATA2__GPIO3_20
+935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
+936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
+937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
+938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
+939 MX35_PAD_FEC_TDATA2__GPIO3_21
+940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
+941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
+942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
+943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
+944 MX35_PAD_FEC_RDATA3__GPIO3_22
+945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
+946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
+947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
+948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
+949 MX35_PAD_FEC_TDATA3__GPIO3_23
+950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
+951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 54e3588..85e714d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -31,6 +31,14 @@ config PINCTRL_IMX
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_IMX35
+	bool "IMX35 pinctrl driver"
+	depends on OF
+	depends on SOC_IMX35
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx35 pinctrl driver
+
 config PINCTRL_IMX51
 	bool "IMX51 pinctrl driver"
 	depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f40b1f8..4ae7a3f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL)		+= devicetree.o
 endif
 obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
 obj-$(CONFIG_PINCTRL_IMX)	+= pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX35)	+= pinctrl-imx35.o
 obj-$(CONFIG_PINCTRL_IMX51)	+= pinctrl-imx51.o
 obj-$(CONFIG_PINCTRL_IMX53)	+= pinctrl-imx53.o
 obj-$(CONFIG_PINCTRL_IMX6Q)	+= pinctrl-imx6q.o
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
new file mode 100644
index 0000000..82f109e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -0,0 +1,1595 @@
+/*
+ * imx35 pinctrl driver.
+ *
+ * This driver was mostly copied from the imx51 pinctrl driver which has:
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx35_pads {
+	MX35_PAD_CAPTURE = 0,
+	MX35_PAD_COMPARE = 1,
+	MX35_PAD_WDOG_RST = 2,
+	MX35_PAD_GPIO1_0 = 3,
+	MX35_PAD_GPIO1_1 = 4,
+	MX35_PAD_GPIO2_0 = 5,
+	MX35_PAD_GPIO3_0 = 6,
+	MX35_PAD_RESET_IN_B = 7,
+	MX35_PAD_POR_B = 8,
+	MX35_PAD_CLKO = 9,
+	MX35_PAD_BOOT_MODE0 = 10,
+	MX35_PAD_BOOT_MODE1 = 11,
+	MX35_PAD_CLK_MODE0 = 12,
+	MX35_PAD_CLK_MODE1 = 13,
+	MX35_PAD_POWER_FAIL = 14,
+	MX35_PAD_VSTBY = 15,
+	MX35_PAD_A0 = 16,
+	MX35_PAD_A1 = 17,
+	MX35_PAD_A2 = 18,
+	MX35_PAD_A3 = 19,
+	MX35_PAD_A4 = 20,
+	MX35_PAD_A5 = 21,
+	MX35_PAD_A6 = 22,
+	MX35_PAD_A7 = 23,
+	MX35_PAD_A8 = 24,
+	MX35_PAD_A9 = 25,
+	MX35_PAD_A10 = 26,
+	MX35_PAD_MA10 = 27,
+	MX35_PAD_A11 = 28,
+	MX35_PAD_A12 = 29,
+	MX35_PAD_A13 = 30,
+	MX35_PAD_A14 = 31,
+	MX35_PAD_A15 = 32,
+	MX35_PAD_A16 = 33,
+	MX35_PAD_A17 = 34,
+	MX35_PAD_A18 = 35,
+	MX35_PAD_A19 = 36,
+	MX35_PAD_A20 = 37,
+	MX35_PAD_A21 = 38,
+	MX35_PAD_A22 = 39,
+	MX35_PAD_A23 = 40,
+	MX35_PAD_A24 = 41,
+	MX35_PAD_A25 = 42,
+	MX35_PAD_SDBA1 = 43,
+	MX35_PAD_SDBA0 = 44,
+	MX35_PAD_SD0 = 45,
+	MX35_PAD_SD1 = 46,
+	MX35_PAD_SD2 = 47,
+	MX35_PAD_SD3 = 48,
+	MX35_PAD_SD4 = 49,
+	MX35_PAD_SD5 = 50,
+	MX35_PAD_SD6 = 51,
+	MX35_PAD_SD7 = 52,
+	MX35_PAD_SD8 = 53,
+	MX35_PAD_SD9 = 54,
+	MX35_PAD_SD10 = 55,
+	MX35_PAD_SD11 = 56,
+	MX35_PAD_SD12 = 57,
+	MX35_PAD_SD13 = 58,
+	MX35_PAD_SD14 = 59,
+	MX35_PAD_SD15 = 60,
+	MX35_PAD_SD16 = 61,
+	MX35_PAD_SD17 = 62,
+	MX35_PAD_SD18 = 63,
+	MX35_PAD_SD19 = 64,
+	MX35_PAD_SD20 = 65,
+	MX35_PAD_SD21 = 66,
+	MX35_PAD_SD22 = 67,
+	MX35_PAD_SD23 = 68,
+	MX35_PAD_SD24 = 69,
+	MX35_PAD_SD25 = 70,
+	MX35_PAD_SD26 = 71,
+	MX35_PAD_SD27 = 72,
+	MX35_PAD_SD28 = 73,
+	MX35_PAD_SD29 = 74,
+	MX35_PAD_SD30 = 75,
+	MX35_PAD_SD31 = 76,
+	MX35_PAD_DQM0 = 77,
+	MX35_PAD_DQM1 = 78,
+	MX35_PAD_DQM2 = 79,
+	MX35_PAD_DQM3 = 80,
+	MX35_PAD_EB0 = 81,
+	MX35_PAD_EB1 = 82,
+	MX35_PAD_OE = 83,
+	MX35_PAD_CS0 = 84,
+	MX35_PAD_CS1 = 85,
+	MX35_PAD_CS2 = 86,
+	MX35_PAD_CS3 = 87,
+	MX35_PAD_CS4 = 88,
+	MX35_PAD_CS5 = 89,
+	MX35_PAD_NF_CE0 = 90,
+	MX35_PAD_ECB = 91,
+	MX35_PAD_LBA = 92,
+	MX35_PAD_BCLK = 93,
+	MX35_PAD_RW = 94,
+	MX35_PAD_RAS = 95,
+	MX35_PAD_CAS = 96,
+	MX35_PAD_SDWE = 97,
+	MX35_PAD_SDCKE0 = 98,
+	MX35_PAD_SDCKE1 = 99,
+	MX35_PAD_SDCLK = 100,
+	MX35_PAD_SDQS0 = 101,
+	MX35_PAD_SDQS1 = 102,
+	MX35_PAD_SDQS2 = 103,
+	MX35_PAD_SDQS3 = 104,
+	MX35_PAD_NFWE_B = 105,
+	MX35_PAD_NFRE_B = 106,
+	MX35_PAD_NFALE = 107,
+	MX35_PAD_NFCLE = 108,
+	MX35_PAD_NFWP_B = 109,
+	MX35_PAD_NFRB = 110,
+	MX35_PAD_D15 = 111,
+	MX35_PAD_D14 = 112,
+	MX35_PAD_D13 = 113,
+	MX35_PAD_D12 = 114,
+	MX35_PAD_D11 = 115,
+	MX35_PAD_D10 = 116,
+	MX35_PAD_D9 = 117,
+	MX35_PAD_D8 = 118,
+	MX35_PAD_D7 = 119,
+	MX35_PAD_D6 = 120,
+	MX35_PAD_D5 = 121,
+	MX35_PAD_D4 = 122,
+	MX35_PAD_D3 = 123,
+	MX35_PAD_D2 = 124,
+	MX35_PAD_D1 = 125,
+	MX35_PAD_D0 = 126,
+	MX35_PAD_CSI_D8 = 127,
+	MX35_PAD_CSI_D9 = 128,
+	MX35_PAD_CSI_D10 = 129,
+	MX35_PAD_CSI_D11 = 130,
+	MX35_PAD_CSI_D12 = 131,
+	MX35_PAD_CSI_D13 = 132,
+	MX35_PAD_CSI_D14 = 133,
+	MX35_PAD_CSI_D15 = 134,
+	MX35_PAD_CSI_MCLK = 135,
+	MX35_PAD_CSI_VSYNC = 136,
+	MX35_PAD_CSI_HSYNC = 137,
+	MX35_PAD_CSI_PIXCLK = 138,
+	MX35_PAD_I2C1_CLK = 139,
+	MX35_PAD_I2C1_DAT = 140,
+	MX35_PAD_I2C2_CLK = 141,
+	MX35_PAD_I2C2_DAT = 142,
+	MX35_PAD_STXD4 = 143,
+	MX35_PAD_SRXD4 = 144,
+	MX35_PAD_SCK4 = 145,
+	MX35_PAD_STXFS4 = 146,
+	MX35_PAD_STXD5 = 147,
+	MX35_PAD_SRXD5 = 148,
+	MX35_PAD_SCK5 = 149,
+	MX35_PAD_STXFS5 = 150,
+	MX35_PAD_SCKR = 151,
+	MX35_PAD_FSR = 152,
+	MX35_PAD_HCKR = 153,
+	MX35_PAD_SCKT = 154,
+	MX35_PAD_FST = 155,
+	MX35_PAD_HCKT = 156,
+	MX35_PAD_TX5_RX0 = 157,
+	MX35_PAD_TX4_RX1 = 158,
+	MX35_PAD_TX3_RX2 = 159,
+	MX35_PAD_TX2_RX3 = 160,
+	MX35_PAD_TX1 = 161,
+	MX35_PAD_TX0 = 162,
+	MX35_PAD_CSPI1_MOSI = 163,
+	MX35_PAD_CSPI1_MISO = 164,
+	MX35_PAD_CSPI1_SS0 = 165,
+	MX35_PAD_CSPI1_SS1 = 166,
+	MX35_PAD_CSPI1_SCLK = 167,
+	MX35_PAD_CSPI1_SPI_RDY = 168,
+	MX35_PAD_RXD1 = 169,
+	MX35_PAD_TXD1 = 170,
+	MX35_PAD_RTS1 = 171,
+	MX35_PAD_CTS1 = 172,
+	MX35_PAD_RXD2 = 173,
+	MX35_PAD_TXD2 = 174,
+	MX35_PAD_RTS2 = 175,
+	MX35_PAD_CTS2 = 176,
+	MX35_PAD_RTCK = 177,
+	MX35_PAD_TCK = 178,
+	MX35_PAD_TMS = 179,
+	MX35_PAD_TDI = 180,
+	MX35_PAD_TDO = 181,
+	MX35_PAD_TRSTB = 182,
+	MX35_PAD_DE_B = 183,
+	MX35_PAD_SJC_MOD = 184,
+	MX35_PAD_USBOTG_PWR = 185,
+	MX35_PAD_USBOTG_OC = 186,
+	MX35_PAD_LD0 = 187,
+	MX35_PAD_LD1 = 188,
+	MX35_PAD_LD2 = 189,
+	MX35_PAD_LD3 = 190,
+	MX35_PAD_LD4 = 191,
+	MX35_PAD_LD5 = 192,
+	MX35_PAD_LD6 = 193,
+	MX35_PAD_LD7 = 194,
+	MX35_PAD_LD8 = 195,
+	MX35_PAD_LD9 = 196,
+	MX35_PAD_LD10 = 197,
+	MX35_PAD_LD11 = 198,
+	MX35_PAD_LD12 = 199,
+	MX35_PAD_LD13 = 200,
+	MX35_PAD_LD14 = 201,
+	MX35_PAD_LD15 = 202,
+	MX35_PAD_LD16 = 203,
+	MX35_PAD_LD17 = 204,
+	MX35_PAD_LD18 = 205,
+	MX35_PAD_LD19 = 206,
+	MX35_PAD_LD20 = 207,
+	MX35_PAD_LD21 = 208,
+	MX35_PAD_LD22 = 209,
+	MX35_PAD_LD23 = 210,
+	MX35_PAD_D3_HSYNC = 211,
+	MX35_PAD_D3_FPSHIFT = 212,
+	MX35_PAD_D3_DRDY = 213,
+	MX35_PAD_CONTRAST = 214,
+	MX35_PAD_D3_VSYNC = 215,
+	MX35_PAD_D3_REV = 216,
+	MX35_PAD_D3_CLS = 217,
+	MX35_PAD_D3_SPL = 218,
+	MX35_PAD_SD1_CMD = 219,
+	MX35_PAD_SD1_CLK = 220,
+	MX35_PAD_SD1_DATA0 = 221,
+	MX35_PAD_SD1_DATA1 = 222,
+	MX35_PAD_SD1_DATA2 = 223,
+	MX35_PAD_SD1_DATA3 = 224,
+	MX35_PAD_SD2_CMD = 225,
+	MX35_PAD_SD2_CLK = 226,
+	MX35_PAD_SD2_DATA0 = 227,
+	MX35_PAD_SD2_DATA1 = 228,
+	MX35_PAD_SD2_DATA2 = 229,
+	MX35_PAD_SD2_DATA3 = 230,
+	MX35_PAD_ATA_CS0 = 231,
+	MX35_PAD_ATA_CS1 = 232,
+	MX35_PAD_ATA_DIOR = 233,
+	MX35_PAD_ATA_DIOW = 234,
+	MX35_PAD_ATA_DMACK = 235,
+	MX35_PAD_ATA_RESET_B = 236,
+	MX35_PAD_ATA_IORDY = 237,
+	MX35_PAD_ATA_DATA0 = 238,
+	MX35_PAD_ATA_DATA1 = 239,
+	MX35_PAD_ATA_DATA2 = 240,
+	MX35_PAD_ATA_DATA3 = 241,
+	MX35_PAD_ATA_DATA4 = 242,
+	MX35_PAD_ATA_DATA5 = 243,
+	MX35_PAD_ATA_DATA6 = 244,
+	MX35_PAD_ATA_DATA7 = 245,
+	MX35_PAD_ATA_DATA8 = 246,
+	MX35_PAD_ATA_DATA9 = 247,
+	MX35_PAD_ATA_DATA10 = 248,
+	MX35_PAD_ATA_DATA11 = 249,
+	MX35_PAD_ATA_DATA12 = 250,
+	MX35_PAD_ATA_DATA13 = 251,
+	MX35_PAD_ATA_DATA14 = 252,
+	MX35_PAD_ATA_DATA15 = 253,
+	MX35_PAD_ATA_INTRQ = 254,
+	MX35_PAD_ATA_BUFF_EN = 255,
+	MX35_PAD_ATA_DMARQ = 256,
+	MX35_PAD_ATA_DA0 = 257,
+	MX35_PAD_ATA_DA1 = 258,
+	MX35_PAD_ATA_DA2 = 259,
+	MX35_PAD_MLB_CLK = 260,
+	MX35_PAD_MLB_DAT = 261,
+	MX35_PAD_MLB_SIG = 262,
+	MX35_PAD_FEC_TX_CLK = 263,
+	MX35_PAD_FEC_RX_CLK = 264,
+	MX35_PAD_FEC_RX_DV = 265,
+	MX35_PAD_FEC_COL = 266,
+	MX35_PAD_FEC_RDATA0 = 267,
+	MX35_PAD_FEC_TDATA0 = 268,
+	MX35_PAD_FEC_TX_EN = 269,
+	MX35_PAD_FEC_MDC = 270,
+	MX35_PAD_FEC_MDIO = 271,
+	MX35_PAD_FEC_TX_ERR = 272,
+	MX35_PAD_FEC_RX_ERR = 273,
+	MX35_PAD_FEC_CRS = 274,
+	MX35_PAD_FEC_RDATA1 = 275,
+	MX35_PAD_FEC_TDATA1 = 276,
+	MX35_PAD_FEC_RDATA2 = 277,
+	MX35_PAD_FEC_TDATA2 = 278,
+	MX35_PAD_FEC_RDATA3 = 279,
+	MX35_PAD_FEC_TDATA3 = 280,
+	MX35_PAD_EXT_ARMCLK = 281,
+	MX35_PAD_TEST_MODE = 282,
+};
+
+/* imx35 register maps */
+static struct imx_pin_reg imx35_pin_regs[] = {
+	[0] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 0, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CAPIN1 */
+	[1] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 1, 0x0, 0), /* MX35_PAD_CAPTURE__GPT_CMPOUT2 */
+	[2] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 2, 0x7f4, 0), /* MX35_PAD_CAPTURE__CSPI2_SS1 */
+	[3] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 3, 0x0, 0), /* MX35_PAD_CAPTURE__EPIT1_EPITO */
+	[4] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 4, 0x7d0, 0), /* MX35_PAD_CAPTURE__CCM_CLK32K */
+	[5] = IMX_PIN_REG(MX35_PAD_CAPTURE, 0x328, 0x004, 5, 0x850, 0), /* MX35_PAD_CAPTURE__GPIO1_4 */
+	[6] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 0, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT1 */
+	[7] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 1, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CAPIN2 */
+	[8] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 2, 0x0, 0), /* MX35_PAD_COMPARE__GPT_CMPOUT3 */
+	[9] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 3, 0x0, 0), /* MX35_PAD_COMPARE__EPIT2_EPITO */
+	[10] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 5, 0x854, 0), /* MX35_PAD_COMPARE__GPIO1_5 */
+	[11] = IMX_PIN_REG(MX35_PAD_COMPARE, 0x32c, 0x008, 7, 0x0, 0), /* MX35_PAD_COMPARE__SDMA_EXTDMA_2 */
+	[12] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 0, 0x0, 0), /* MX35_PAD_WDOG_RST__WDOG_WDOG_B */
+	[13] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 3, 0x0, 0), /* MX35_PAD_WDOG_RST__IPU_FLASH_STROBE */
+	[14] = IMX_PIN_REG(MX35_PAD_WDOG_RST, 0x330, 0x00c, 5, 0x858, 0), /* MX35_PAD_WDOG_RST__GPIO1_6 */
+	[15] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 0, 0x82c, 0), /* MX35_PAD_GPIO1_0__GPIO1_0 */
+	[16] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 1, 0x7d4, 0), /* MX35_PAD_GPIO1_0__CCM_PMIC_RDY */
+	[17] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 2, 0x990, 0), /* MX35_PAD_GPIO1_0__OWIRE_LINE */
+	[18] = IMX_PIN_REG(MX35_PAD_GPIO1_0, 0x334, 0x010, 7, 0x0, 0), /* MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 */
+	[19] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 0, 0x838, 0), /* MX35_PAD_GPIO1_1__GPIO1_1 */
+	[20] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 2, 0x0, 0), /* MX35_PAD_GPIO1_1__PWM_PWMO */
+	[21] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 3, 0x7d8, 0), /* MX35_PAD_GPIO1_1__CSPI1_SS2 */
+	[22] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 6, 0x0, 0), /* MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT */
+	[23] = IMX_PIN_REG(MX35_PAD_GPIO1_1, 0x338, 0x014, 7, 0x0, 0), /* MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 */
+	[24] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 0, 0x868, 0), /* MX35_PAD_GPIO2_0__GPIO2_0 */
+	[25] = IMX_PIN_REG(MX35_PAD_GPIO2_0, 0x33c, 0x018, 1, 0x0, 0), /* MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK */
+	[26] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 0, 0x8e8, 0), /* MX35_PAD_GPIO3_0__GPIO3_0 */
+	[27] = IMX_PIN_REG(MX35_PAD_GPIO3_0, 0x340, 0x01c, 1, 0x0, 0), /* MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK */
+	[28] = IMX_PIN_REG(MX35_PAD_RESET_IN_B, 0x344, 0x0, 0, 0x0, 0), /* MX35_PAD_RESET_IN_B__CCM_RESET_IN_B */
+	[29] = IMX_PIN_REG(MX35_PAD_POR_B, 0x348, 0x0, 0, 0x0, 0), /* MX35_PAD_POR_B__CCM_POR_B */
+	[30] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 0, 0x0, 0), /* MX35_PAD_CLKO__CCM_CLKO */
+	[31] = IMX_PIN_REG(MX35_PAD_CLKO, 0x34c, 0x020, 5, 0x860, 0), /* MX35_PAD_CLKO__GPIO1_8 */
+	[32] = IMX_PIN_REG(MX35_PAD_BOOT_MODE0, 0x350, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 */
+	[33] = IMX_PIN_REG(MX35_PAD_BOOT_MODE1, 0x354, 0x0, 0, 0x0, 0), /* MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 */
+	[34] = IMX_PIN_REG(MX35_PAD_CLK_MODE0, 0x358, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 */
+	[35] = IMX_PIN_REG(MX35_PAD_CLK_MODE1, 0x35c, 0x0, 0, 0x0, 0), /* MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 */
+	[36] = IMX_PIN_REG(MX35_PAD_POWER_FAIL, 0x360, 0x0, 0, 0x0, 0), /* MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 */
+	[37] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 0, 0x0, 0), /* MX35_PAD_VSTBY__CCM_VSTBY */
+	[38] = IMX_PIN_REG(MX35_PAD_VSTBY, 0x364, 0x024, 5, 0x85c, 0), /* MX35_PAD_VSTBY__GPIO1_7 */
+	[39] = IMX_PIN_REG(MX35_PAD_A0, 0x368, 0x028, 0, 0x0, 0), /* MX35_PAD_A0__EMI_EIM_DA_L_0 */
+	[40] = IMX_PIN_REG(MX35_PAD_A1, 0x36c, 0x02c, 0, 0x0, 0), /* MX35_PAD_A1__EMI_EIM_DA_L_1 */
+	[41] = IMX_PIN_REG(MX35_PAD_A2, 0x370, 0x030, 0, 0x0, 0), /* MX35_PAD_A2__EMI_EIM_DA_L_2 */
+	[42] = IMX_PIN_REG(MX35_PAD_A3, 0x374, 0x034, 0, 0x0, 0), /* MX35_PAD_A3__EMI_EIM_DA_L_3 */
+	[43] = IMX_PIN_REG(MX35_PAD_A4, 0x378, 0x038, 0, 0x0, 0), /* MX35_PAD_A4__EMI_EIM_DA_L_4 */
+	[44] = IMX_PIN_REG(MX35_PAD_A5, 0x37c, 0x03c, 0, 0x0, 0), /* MX35_PAD_A5__EMI_EIM_DA_L_5 */
+	[45] = IMX_PIN_REG(MX35_PAD_A6, 0x380, 0x040, 0, 0x0, 0), /* MX35_PAD_A6__EMI_EIM_DA_L_6 */
+	[46] = IMX_PIN_REG(MX35_PAD_A7, 0x384, 0x044, 0, 0x0, 0), /* MX35_PAD_A7__EMI_EIM_DA_L_7 */
+	[47] = IMX_PIN_REG(MX35_PAD_A8, 0x388, 0x048, 0, 0x0, 0), /* MX35_PAD_A8__EMI_EIM_DA_H_8 */
+	[48] = IMX_PIN_REG(MX35_PAD_A9, 0x38c, 0x04c, 0, 0x0, 0), /* MX35_PAD_A9__EMI_EIM_DA_H_9 */
+	[49] = IMX_PIN_REG(MX35_PAD_A10, 0x390, 0x050, 0, 0x0, 0), /* MX35_PAD_A10__EMI_EIM_DA_H_10 */
+	[50] = IMX_PIN_REG(MX35_PAD_MA10, 0x394, 0x054, 0, 0x0, 0), /* MX35_PAD_MA10__EMI_MA10 */
+	[51] = IMX_PIN_REG(MX35_PAD_A11, 0x398, 0x058, 0, 0x0, 0), /* MX35_PAD_A11__EMI_EIM_DA_H_11 */
+	[52] = IMX_PIN_REG(MX35_PAD_A12, 0x39c, 0x05c, 0, 0x0, 0), /* MX35_PAD_A12__EMI_EIM_DA_H_12 */
+	[53] = IMX_PIN_REG(MX35_PAD_A13, 0x3a0, 0x060, 0, 0x0, 0), /* MX35_PAD_A13__EMI_EIM_DA_H_13 */
+	[54] = IMX_PIN_REG(MX35_PAD_A14, 0x3a4, 0x064, 0, 0x0, 0), /* MX35_PAD_A14__EMI_EIM_DA_H2_14 */
+	[55] = IMX_PIN_REG(MX35_PAD_A15, 0x3a8, 0x068, 0, 0x0, 0), /* MX35_PAD_A15__EMI_EIM_DA_H2_15 */
+	[56] = IMX_PIN_REG(MX35_PAD_A16, 0x3ac, 0x06c, 0, 0x0, 0), /* MX35_PAD_A16__EMI_EIM_A_16 */
+	[57] = IMX_PIN_REG(MX35_PAD_A17, 0x3b0, 0x070, 0, 0x0, 0), /* MX35_PAD_A17__EMI_EIM_A_17 */
+	[58] = IMX_PIN_REG(MX35_PAD_A18, 0x3b4, 0x074, 0, 0x0, 0), /* MX35_PAD_A18__EMI_EIM_A_18 */
+	[59] = IMX_PIN_REG(MX35_PAD_A19, 0x3b8, 0x078, 0, 0x0, 0), /* MX35_PAD_A19__EMI_EIM_A_19 */
+	[60] = IMX_PIN_REG(MX35_PAD_A20, 0x3bc, 0x07c, 0, 0x0, 0), /* MX35_PAD_A20__EMI_EIM_A_20 */
+	[61] = IMX_PIN_REG(MX35_PAD_A21, 0x3c0, 0x080, 0, 0x0, 0), /* MX35_PAD_A21__EMI_EIM_A_21 */
+	[62] = IMX_PIN_REG(MX35_PAD_A22, 0x3c4, 0x084, 0, 0x0, 0), /* MX35_PAD_A22__EMI_EIM_A_22 */
+	[63] = IMX_PIN_REG(MX35_PAD_A23, 0x3c8, 0x088, 0, 0x0, 0), /* MX35_PAD_A23__EMI_EIM_A_23 */
+	[64] = IMX_PIN_REG(MX35_PAD_A24, 0x3cc, 0x08c, 0, 0x0, 0), /* MX35_PAD_A24__EMI_EIM_A_24 */
+	[65] = IMX_PIN_REG(MX35_PAD_A25, 0x3d0, 0x090, 0, 0x0, 0), /* MX35_PAD_A25__EMI_EIM_A_25 */
+	[66] = IMX_PIN_REG(MX35_PAD_SDBA1, 0x3d4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA1__EMI_EIM_SDBA1 */
+	[67] = IMX_PIN_REG(MX35_PAD_SDBA0, 0x3d8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDBA0__EMI_EIM_SDBA0 */
+	[68] = IMX_PIN_REG(MX35_PAD_SD0, 0x3dc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD0__EMI_DRAM_D_0 */
+	[69] = IMX_PIN_REG(MX35_PAD_SD1, 0x3e0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD1__EMI_DRAM_D_1 */
+	[70] = IMX_PIN_REG(MX35_PAD_SD2, 0x3e4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD2__EMI_DRAM_D_2 */
+	[71] = IMX_PIN_REG(MX35_PAD_SD3, 0x3e8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD3__EMI_DRAM_D_3 */
+	[72] = IMX_PIN_REG(MX35_PAD_SD4, 0x3ec, 0x0, 0, 0x0, 0), /* MX35_PAD_SD4__EMI_DRAM_D_4 */
+	[73] = IMX_PIN_REG(MX35_PAD_SD5, 0x3f0, 0x0, 0, 0x0, 0), /* MX35_PAD_SD5__EMI_DRAM_D_5 */
+	[74] = IMX_PIN_REG(MX35_PAD_SD6, 0x3f4, 0x0, 0, 0x0, 0), /* MX35_PAD_SD6__EMI_DRAM_D_6 */
+	[75] = IMX_PIN_REG(MX35_PAD_SD7, 0x3f8, 0x0, 0, 0x0, 0), /* MX35_PAD_SD7__EMI_DRAM_D_7 */
+	[76] = IMX_PIN_REG(MX35_PAD_SD8, 0x3fc, 0x0, 0, 0x0, 0), /* MX35_PAD_SD8__EMI_DRAM_D_8 */
+	[77] = IMX_PIN_REG(MX35_PAD_SD9, 0x400, 0x0, 0, 0x0, 0), /* MX35_PAD_SD9__EMI_DRAM_D_9 */
+	[78] = IMX_PIN_REG(MX35_PAD_SD10, 0x404, 0x0, 0, 0x0, 0), /* MX35_PAD_SD10__EMI_DRAM_D_10 */
+	[79] = IMX_PIN_REG(MX35_PAD_SD11, 0x408, 0x0, 0, 0x0, 0), /* MX35_PAD_SD11__EMI_DRAM_D_11 */
+	[80] = IMX_PIN_REG(MX35_PAD_SD12, 0x40c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD12__EMI_DRAM_D_12 */
+	[81] = IMX_PIN_REG(MX35_PAD_SD13, 0x410, 0x0, 0, 0x0, 0), /* MX35_PAD_SD13__EMI_DRAM_D_13 */
+	[82] = IMX_PIN_REG(MX35_PAD_SD14, 0x414, 0x0, 0, 0x0, 0), /* MX35_PAD_SD14__EMI_DRAM_D_14 */
+	[83] = IMX_PIN_REG(MX35_PAD_SD15, 0x418, 0x0, 0, 0x0, 0), /* MX35_PAD_SD15__EMI_DRAM_D_15 */
+	[84] = IMX_PIN_REG(MX35_PAD_SD16, 0x41c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD16__EMI_DRAM_D_16 */
+	[85] = IMX_PIN_REG(MX35_PAD_SD17, 0x420, 0x0, 0, 0x0, 0), /* MX35_PAD_SD17__EMI_DRAM_D_17 */
+	[86] = IMX_PIN_REG(MX35_PAD_SD18, 0x424, 0x0, 0, 0x0, 0), /* MX35_PAD_SD18__EMI_DRAM_D_18 */
+	[87] = IMX_PIN_REG(MX35_PAD_SD19, 0x428, 0x0, 0, 0x0, 0), /* MX35_PAD_SD19__EMI_DRAM_D_19 */
+	[88] = IMX_PIN_REG(MX35_PAD_SD20, 0x42c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD20__EMI_DRAM_D_20 */
+	[89] = IMX_PIN_REG(MX35_PAD_SD21, 0x430, 0x0, 0, 0x0, 0), /* MX35_PAD_SD21__EMI_DRAM_D_21 */
+	[90] = IMX_PIN_REG(MX35_PAD_SD22, 0x434, 0x0, 0, 0x0, 0), /* MX35_PAD_SD22__EMI_DRAM_D_22 */
+	[91] = IMX_PIN_REG(MX35_PAD_SD23, 0x438, 0x0, 0, 0x0, 0), /* MX35_PAD_SD23__EMI_DRAM_D_23 */
+	[92] = IMX_PIN_REG(MX35_PAD_SD24, 0x43c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD24__EMI_DRAM_D_24 */
+	[93] = IMX_PIN_REG(MX35_PAD_SD25, 0x440, 0x0, 0, 0x0, 0), /* MX35_PAD_SD25__EMI_DRAM_D_25 */
+	[94] = IMX_PIN_REG(MX35_PAD_SD26, 0x444, 0x0, 0, 0x0, 0), /* MX35_PAD_SD26__EMI_DRAM_D_26 */
+	[95] = IMX_PIN_REG(MX35_PAD_SD27, 0x448, 0x0, 0, 0x0, 0), /* MX35_PAD_SD27__EMI_DRAM_D_27 */
+	[96] = IMX_PIN_REG(MX35_PAD_SD28, 0x44c, 0x0, 0, 0x0, 0), /* MX35_PAD_SD28__EMI_DRAM_D_28 */
+	[97] = IMX_PIN_REG(MX35_PAD_SD29, 0x450, 0x0, 0, 0x0, 0), /* MX35_PAD_SD29__EMI_DRAM_D_29 */
+	[98] = IMX_PIN_REG(MX35_PAD_SD30, 0x454, 0x0, 0, 0x0, 0), /* MX35_PAD_SD30__EMI_DRAM_D_30 */
+	[99] = IMX_PIN_REG(MX35_PAD_SD31, 0x458, 0x0, 0, 0x0, 0), /* MX35_PAD_SD31__EMI_DRAM_D_31 */
+	[100] = IMX_PIN_REG(MX35_PAD_DQM0, 0x45c, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM0__EMI_DRAM_DQM_0 */
+	[101] = IMX_PIN_REG(MX35_PAD_DQM1, 0x460, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM1__EMI_DRAM_DQM_1 */
+	[102] = IMX_PIN_REG(MX35_PAD_DQM2, 0x464, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM2__EMI_DRAM_DQM_2 */
+	[103] = IMX_PIN_REG(MX35_PAD_DQM3, 0x468, 0x0, 0, 0x0, 0), /* MX35_PAD_DQM3__EMI_DRAM_DQM_3 */
+	[104] = IMX_PIN_REG(MX35_PAD_EB0, 0x46c, 0x094, 0, 0x0, 0), /* MX35_PAD_EB0__EMI_EIM_EB0_B */
+	[105] = IMX_PIN_REG(MX35_PAD_EB1, 0x470, 0x098, 0, 0x0, 0), /* MX35_PAD_EB1__EMI_EIM_EB1_B */
+	[106] = IMX_PIN_REG(MX35_PAD_OE, 0x474, 0x09c, 0, 0x0, 0), /* MX35_PAD_OE__EMI_EIM_OE */
+	[107] = IMX_PIN_REG(MX35_PAD_CS0, 0x478, 0x0a0, 0, 0x0, 0), /* MX35_PAD_CS0__EMI_EIM_CS0 */
+	[108] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 0, 0x0, 0), /* MX35_PAD_CS1__EMI_EIM_CS1 */
+	[109] = IMX_PIN_REG(MX35_PAD_CS1, 0x47c, 0x0a4, 3, 0x0, 0), /* MX35_PAD_CS1__EMI_NANDF_CE3 */
+	[110] = IMX_PIN_REG(MX35_PAD_CS2, 0x480, 0x0a8, 0, 0x0, 0), /* MX35_PAD_CS2__EMI_EIM_CS2 */
+	[111] = IMX_PIN_REG(MX35_PAD_CS3, 0x484, 0x0ac, 0, 0x0, 0), /* MX35_PAD_CS3__EMI_EIM_CS3 */
+	[112] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 0, 0x0, 0), /* MX35_PAD_CS4__EMI_EIM_CS4 */
+	[113] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 1, 0x800, 0), /* MX35_PAD_CS4__EMI_DTACK_B */
+	[114] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 3, 0x0, 0), /* MX35_PAD_CS4__EMI_NANDF_CE1 */
+	[115] = IMX_PIN_REG(MX35_PAD_CS4, 0x488, 0x0b0, 5, 0x83c, 0), /* MX35_PAD_CS4__GPIO1_20 */
+	[116] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 0, 0x0, 0), /* MX35_PAD_CS5__EMI_EIM_CS5 */
+	[117] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 1, 0x7f8, 0), /* MX35_PAD_CS5__CSPI2_SS2 */
+	[118] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 2, 0x7d8, 1), /* MX35_PAD_CS5__CSPI1_SS2 */
+	[119] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 3, 0x0, 0), /* MX35_PAD_CS5__EMI_NANDF_CE2 */
+	[120] = IMX_PIN_REG(MX35_PAD_CS5, 0x48c, 0x0b4, 5, 0x840, 0), /* MX35_PAD_CS5__GPIO1_21 */
+	[121] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 0, 0x0, 0), /* MX35_PAD_NF_CE0__EMI_NANDF_CE0 */
+	[122] = IMX_PIN_REG(MX35_PAD_NF_CE0, 0x490, 0x0b8, 5, 0x844, 0), /* MX35_PAD_NF_CE0__GPIO1_22 */
+	[123] = IMX_PIN_REG(MX35_PAD_ECB, 0x494, 0x0, 0, 0x0, 0), /* MX35_PAD_ECB__EMI_EIM_ECB */
+	[124] = IMX_PIN_REG(MX35_PAD_LBA, 0x498, 0x0bc, 0, 0x0, 0), /* MX35_PAD_LBA__EMI_EIM_LBA */
+	[125] = IMX_PIN_REG(MX35_PAD_BCLK, 0x49c, 0x0c0, 0, 0x0, 0), /* MX35_PAD_BCLK__EMI_EIM_BCLK */
+	[126] = IMX_PIN_REG(MX35_PAD_RW, 0x4a0, 0x0c4, 0, 0x0, 0), /* MX35_PAD_RW__EMI_EIM_RW */
+	[127] = IMX_PIN_REG(MX35_PAD_RAS, 0x4a4, 0x0, 0, 0x0, 0), /* MX35_PAD_RAS__EMI_DRAM_RAS */
+	[128] = IMX_PIN_REG(MX35_PAD_CAS, 0x4a8, 0x0, 0, 0x0, 0), /* MX35_PAD_CAS__EMI_DRAM_CAS */
+	[129] = IMX_PIN_REG(MX35_PAD_SDWE, 0x4ac, 0x0, 0, 0x0, 0), /* MX35_PAD_SDWE__EMI_DRAM_SDWE */
+	[130] = IMX_PIN_REG(MX35_PAD_SDCKE0, 0x4b0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 */
+	[131] = IMX_PIN_REG(MX35_PAD_SDCKE1, 0x4b4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 */
+	[132] = IMX_PIN_REG(MX35_PAD_SDCLK, 0x4b8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDCLK__EMI_DRAM_SDCLK */
+	[133] = IMX_PIN_REG(MX35_PAD_SDQS0, 0x4bc, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 */
+	[134] = IMX_PIN_REG(MX35_PAD_SDQS1, 0x4c0, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 */
+	[135] = IMX_PIN_REG(MX35_PAD_SDQS2, 0x4c4, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 */
+	[136] = IMX_PIN_REG(MX35_PAD_SDQS3, 0x4c8, 0x0, 0, 0x0, 0), /* MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 */
+	[137] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 0, 0x0, 0), /* MX35_PAD_NFWE_B__EMI_NANDF_WE_B */
+	[138] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 1, 0x9d8, 0), /* MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 */
+	[139] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 2, 0x924, 0), /* MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC */
+	[140] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 5, 0x88c, 0), /* MX35_PAD_NFWE_B__GPIO2_18 */
+	[141] = IMX_PIN_REG(MX35_PAD_NFWE_B, 0x4cc, 0x0c8, 7, 0x0, 0), /* MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 */
+	[142] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 0, 0x0, 0), /* MX35_PAD_NFRE_B__EMI_NANDF_RE_B */
+	[143] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 1, 0x9ec, 0), /* MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR */
+	[144] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 2, 0x0, 0), /* MX35_PAD_NFRE_B__IPU_DISPB_BCLK */
+	[145] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 5, 0x890, 0), /* MX35_PAD_NFRE_B__GPIO2_19 */
+	[146] = IMX_PIN_REG(MX35_PAD_NFRE_B, 0x4d0, 0x0cc, 7, 0x0, 0), /* MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 */
+	[147] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 0, 0x0, 0), /* MX35_PAD_NFALE__EMI_NANDF_ALE */
+	[148] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 1, 0x0, 0), /* MX35_PAD_NFALE__USB_TOP_USBH2_STP */
+	[149] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 2, 0x0, 0), /* MX35_PAD_NFALE__IPU_DISPB_CS0 */
+	[150] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 5, 0x898, 0), /* MX35_PAD_NFALE__GPIO2_20 */
+	[151] = IMX_PIN_REG(MX35_PAD_NFALE, 0x4d4, 0x0d0, 7, 0x0, 0), /* MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 */
+	[152] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 0, 0x0, 0), /* MX35_PAD_NFCLE__EMI_NANDF_CLE */
+	[153] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 1, 0x9f0, 0), /* MX35_PAD_NFCLE__USB_TOP_USBH2_NXT */
+	[154] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 2, 0x0, 0), /* MX35_PAD_NFCLE__IPU_DISPB_PAR_RS */
+	[155] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 5, 0x89c, 0), /* MX35_PAD_NFCLE__GPIO2_21 */
+	[156] = IMX_PIN_REG(MX35_PAD_NFCLE, 0x4d8, 0x0d4, 7, 0x0, 0), /* MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 */
+	[157] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 0, 0x0, 0), /* MX35_PAD_NFWP_B__EMI_NANDF_WP_B */
+	[158] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 1, 0x9e8, 0), /* MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 */
+	[159] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 2, 0x0, 0), /* MX35_PAD_NFWP_B__IPU_DISPB_WR */
+	[160] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 5, 0x8a0, 0), /* MX35_PAD_NFWP_B__GPIO2_22 */
+	[161] = IMX_PIN_REG(MX35_PAD_NFWP_B, 0x4dc, 0x0d8, 7, 0x0, 0), /* MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL */
+	[162] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 0, 0x0, 0), /* MX35_PAD_NFRB__EMI_NANDF_RB */
+	[163] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 2, 0x0, 0), /* MX35_PAD_NFRB__IPU_DISPB_RD */
+	[164] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 5, 0x8a4, 0), /* MX35_PAD_NFRB__GPIO2_23 */
+	[165] = IMX_PIN_REG(MX35_PAD_NFRB, 0x4e0, 0x0dc, 7, 0x0, 0), /* MX35_PAD_NFRB__ARM11P_TOP_TRCLK */
+	[166] = IMX_PIN_REG(MX35_PAD_D15, 0x4e4, 0x0, 0, 0x0, 0), /* MX35_PAD_D15__EMI_EIM_D_15 */
+	[167] = IMX_PIN_REG(MX35_PAD_D14, 0x4e8, 0x0, 0, 0x0, 0), /* MX35_PAD_D14__EMI_EIM_D_14 */
+	[168] = IMX_PIN_REG(MX35_PAD_D13, 0x4ec, 0x0, 0, 0x0, 0), /* MX35_PAD_D13__EMI_EIM_D_13 */
+	[169] = IMX_PIN_REG(MX35_PAD_D12, 0x4f0, 0x0, 0, 0x0, 0), /* MX35_PAD_D12__EMI_EIM_D_12 */
+	[170] = IMX_PIN_REG(MX35_PAD_D11, 0x4f4, 0x0, 0, 0x0, 0), /* MX35_PAD_D11__EMI_EIM_D_11 */
+	[171] = IMX_PIN_REG(MX35_PAD_D10, 0x4f8, 0x0, 0, 0x0, 0), /* MX35_PAD_D10__EMI_EIM_D_10 */
+	[172] = IMX_PIN_REG(MX35_PAD_D9, 0x4fc, 0x0, 0, 0x0, 0), /* MX35_PAD_D9__EMI_EIM_D_9 */
+	[173] = IMX_PIN_REG(MX35_PAD_D8, 0x500, 0x0, 0, 0x0, 0), /* MX35_PAD_D8__EMI_EIM_D_8 */
+	[174] = IMX_PIN_REG(MX35_PAD_D7, 0x504, 0x0, 0, 0x0, 0), /* MX35_PAD_D7__EMI_EIM_D_7 */
+	[175] = IMX_PIN_REG(MX35_PAD_D6, 0x508, 0x0, 0, 0x0, 0), /* MX35_PAD_D6__EMI_EIM_D_6 */
+	[176] = IMX_PIN_REG(MX35_PAD_D5, 0x50c, 0x0, 0, 0x0, 0), /* MX35_PAD_D5__EMI_EIM_D_5 */
+	[177] = IMX_PIN_REG(MX35_PAD_D4, 0x510, 0x0, 0, 0x0, 0), /* MX35_PAD_D4__EMI_EIM_D_4 */
+	[178] = IMX_PIN_REG(MX35_PAD_D3, 0x514, 0x0, 0, 0x0, 0), /* MX35_PAD_D3__EMI_EIM_D_3 */
+	[179] = IMX_PIN_REG(MX35_PAD_D2, 0x518, 0x0, 0, 0x0, 0), /* MX35_PAD_D2__EMI_EIM_D_2 */
+	[180] = IMX_PIN_REG(MX35_PAD_D1, 0x51c, 0x0, 0, 0x0, 0), /* MX35_PAD_D1__EMI_EIM_D_1 */
+	[181] = IMX_PIN_REG(MX35_PAD_D0, 0x520, 0x0, 0, 0x0, 0), /* MX35_PAD_D0__EMI_EIM_D_0 */
+	[182] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 0, 0x0, 0), /* MX35_PAD_CSI_D8__IPU_CSI_D_8 */
+	[183] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 1, 0x950, 0), /* MX35_PAD_CSI_D8__KPP_COL_0 */
+	[184] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 5, 0x83c, 1), /* MX35_PAD_CSI_D8__GPIO1_20 */
+	[185] = IMX_PIN_REG(MX35_PAD_CSI_D8, 0x524, 0x0e0, 7, 0x0, 0), /* MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 */
+	[186] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 0, 0x0, 0), /* MX35_PAD_CSI_D9__IPU_CSI_D_9 */
+	[187] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 1, 0x954, 0), /* MX35_PAD_CSI_D9__KPP_COL_1 */
+	[188] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 5, 0x840, 1), /* MX35_PAD_CSI_D9__GPIO1_21 */
+	[189] = IMX_PIN_REG(MX35_PAD_CSI_D9, 0x528, 0x0e4, 7, 0x0, 0), /* MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 */
+	[190] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 0, 0x0, 0), /* MX35_PAD_CSI_D10__IPU_CSI_D_10 */
+	[191] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 1, 0x958, 0), /* MX35_PAD_CSI_D10__KPP_COL_2 */
+	[192] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 5, 0x844, 1), /* MX35_PAD_CSI_D10__GPIO1_22 */
+	[193] = IMX_PIN_REG(MX35_PAD_CSI_D10, 0x52c, 0x0e8, 7, 0x0, 0), /* MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 */
+	[194] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 0, 0x0, 0), /* MX35_PAD_CSI_D11__IPU_CSI_D_11 */
+	[195] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 1, 0x95c, 0), /* MX35_PAD_CSI_D11__KPP_COL_3 */
+	[196] = IMX_PIN_REG(MX35_PAD_CSI_D11, 0x530, 0x0ec, 5, 0x0, 0), /* MX35_PAD_CSI_D11__GPIO1_23 */
+	[197] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 0, 0x0, 0), /* MX35_PAD_CSI_D12__IPU_CSI_D_12 */
+	[198] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 1, 0x970, 0), /* MX35_PAD_CSI_D12__KPP_ROW_0 */
+	[199] = IMX_PIN_REG(MX35_PAD_CSI_D12, 0x534, 0x0f0, 5, 0x0, 0), /* MX35_PAD_CSI_D12__GPIO1_24 */
+	[200] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 0, 0x0, 0), /* MX35_PAD_CSI_D13__IPU_CSI_D_13 */
+	[201] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 1, 0x974, 0), /* MX35_PAD_CSI_D13__KPP_ROW_1 */
+	[202] = IMX_PIN_REG(MX35_PAD_CSI_D13, 0x538, 0x0f4, 5, 0x0, 0), /* MX35_PAD_CSI_D13__GPIO1_25 */
+	[203] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 0, 0x0, 0), /* MX35_PAD_CSI_D14__IPU_CSI_D_14 */
+	[204] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 1, 0x978, 0), /* MX35_PAD_CSI_D14__KPP_ROW_2 */
+	[205] = IMX_PIN_REG(MX35_PAD_CSI_D14, 0x53c, 0x0f8, 5, 0x0, 0), /* MX35_PAD_CSI_D14__GPIO1_26 */
+	[206] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 0, 0x97c, 0), /* MX35_PAD_CSI_D15__IPU_CSI_D_15 */
+	[207] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 1, 0x0, 0), /* MX35_PAD_CSI_D15__KPP_ROW_3 */
+	[208] = IMX_PIN_REG(MX35_PAD_CSI_D15, 0x540, 0x0fc, 5, 0x0, 0), /* MX35_PAD_CSI_D15__GPIO1_27 */
+	[209] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 0, 0x0, 0), /* MX35_PAD_CSI_MCLK__IPU_CSI_MCLK */
+	[210] = IMX_PIN_REG(MX35_PAD_CSI_MCLK, 0x544, 0x100, 5, 0x0, 0), /* MX35_PAD_CSI_MCLK__GPIO1_28 */
+	[211] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 0, 0x0, 0), /* MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC */
+	[212] = IMX_PIN_REG(MX35_PAD_CSI_VSYNC, 0x548, 0x104, 5, 0x0, 0), /* MX35_PAD_CSI_VSYNC__GPIO1_29 */
+	[213] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 0, 0x0, 0), /* MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC */
+	[214] = IMX_PIN_REG(MX35_PAD_CSI_HSYNC, 0x54c, 0x108, 5, 0x0, 0), /* MX35_PAD_CSI_HSYNC__GPIO1_30 */
+	[215] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 0, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK */
+	[216] = IMX_PIN_REG(MX35_PAD_CSI_PIXCLK, 0x550, 0x10c, 5, 0x0, 0), /* MX35_PAD_CSI_PIXCLK__GPIO1_31 */
+	[217] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 0, 0x0, 0), /* MX35_PAD_I2C1_CLK__I2C1_SCL */
+	[218] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 5, 0x8a8, 0), /* MX35_PAD_I2C1_CLK__GPIO2_24 */
+	[219] = IMX_PIN_REG(MX35_PAD_I2C1_CLK, 0x554, 0x110, 6, 0x0, 0), /* MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK */
+	[220] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 0, 0x0, 0), /* MX35_PAD_I2C1_DAT__I2C1_SDA */
+	[221] = IMX_PIN_REG(MX35_PAD_I2C1_DAT, 0x558, 0x114, 5, 0x8ac, 0), /* MX35_PAD_I2C1_DAT__GPIO2_25 */
+	[222] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 0, 0x0, 0), /* MX35_PAD_I2C2_CLK__I2C2_SCL */
+	[223] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 1, 0x0, 0), /* MX35_PAD_I2C2_CLK__CAN1_TXCAN */
+	[224] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 2, 0x0, 0), /* MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR */
+	[225] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 5, 0x8b0, 0), /* MX35_PAD_I2C2_CLK__GPIO2_26 */
+	[226] = IMX_PIN_REG(MX35_PAD_I2C2_CLK, 0x55c, 0x118, 6, 0x0, 0), /* MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 */
+	[227] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 0, 0x0, 0), /* MX35_PAD_I2C2_DAT__I2C2_SDA */
+	[228] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 1, 0x7c8, 0), /* MX35_PAD_I2C2_DAT__CAN1_RXCAN */
+	[229] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 2, 0x9f4, 0), /* MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC */
+	[230] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 5, 0x8b4, 0), /* MX35_PAD_I2C2_DAT__GPIO2_27 */
+	[231] = IMX_PIN_REG(MX35_PAD_I2C2_DAT, 0x560, 0x11c, 6, 0x0, 0), /* MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 */
+	[232] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 0, 0x0, 0), /* MX35_PAD_STXD4__AUDMUX_AUD4_TXD */
+	[233] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 5, 0x8b8, 0), /* MX35_PAD_STXD4__GPIO2_28 */
+	[234] = IMX_PIN_REG(MX35_PAD_STXD4, 0x564, 0x120, 7, 0x0, 0), /* MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 */
+	[235] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 0, 0x0, 0), /* MX35_PAD_SRXD4__AUDMUX_AUD4_RXD */
+	[236] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 5, 0x8bc, 0), /* MX35_PAD_SRXD4__GPIO2_29 */
+	[237] = IMX_PIN_REG(MX35_PAD_SRXD4, 0x568, 0x124, 7, 0x0, 0), /* MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 */
+	[238] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 0, 0x0, 0), /* MX35_PAD_SCK4__AUDMUX_AUD4_TXC */
+	[239] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 5, 0x8c4, 0), /* MX35_PAD_SCK4__GPIO2_30 */
+	[240] = IMX_PIN_REG(MX35_PAD_SCK4, 0x56c, 0x128, 7, 0x0, 0), /* MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 */
+	[241] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 0, 0x0, 0), /* MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS */
+	[242] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 5, 0x8c8, 0), /* MX35_PAD_STXFS4__GPIO2_31 */
+	[243] = IMX_PIN_REG(MX35_PAD_STXFS4, 0x570, 0x12c, 7, 0x0, 0), /* MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 */
+	[244] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 0, 0x0, 0), /* MX35_PAD_STXD5__AUDMUX_AUD5_TXD */
+	[245] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 1, 0x0, 0), /* MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 */
+	[246] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 2, 0x7ec, 0), /* MX35_PAD_STXD5__CSPI2_MOSI */
+	[247] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 5, 0x82c, 1), /* MX35_PAD_STXD5__GPIO1_0 */
+	[248] = IMX_PIN_REG(MX35_PAD_STXD5, 0x574, 0x130, 7, 0x0, 0), /* MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 */
+	[249] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 0, 0x0, 0), /* MX35_PAD_SRXD5__AUDMUX_AUD5_RXD */
+	[250] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 1, 0x998, 0), /* MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 */
+	[251] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 2, 0x7e8, 0), /* MX35_PAD_SRXD5__CSPI2_MISO */
+	[252] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 5, 0x838, 1), /* MX35_PAD_SRXD5__GPIO1_1 */
+	[253] = IMX_PIN_REG(MX35_PAD_SRXD5, 0x578, 0x134, 7, 0x0, 0), /* MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 */
+	[254] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 0, 0x0, 0), /* MX35_PAD_SCK5__AUDMUX_AUD5_TXC */
+	[255] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 1, 0x994, 0), /* MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK */
+	[256] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 2, 0x7e0, 0), /* MX35_PAD_SCK5__CSPI2_SCLK */
+	[257] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 5, 0x848, 0), /* MX35_PAD_SCK5__GPIO1_2 */
+	[258] = IMX_PIN_REG(MX35_PAD_SCK5, 0x57c, 0x138, 7, 0x0, 0), /* MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 */
+	[259] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 0, 0x0, 0), /* MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS */
+	[260] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 2, 0x7e4, 0), /* MX35_PAD_STXFS5__CSPI2_RDY */
+	[261] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 5, 0x84c, 0), /* MX35_PAD_STXFS5__GPIO1_3 */
+	[262] = IMX_PIN_REG(MX35_PAD_STXFS5, 0x580, 0x13c, 7, 0x0, 0), /* MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 */
+	[263] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 0, 0x0, 0), /* MX35_PAD_SCKR__ESAI_SCKR */
+	[264] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 5, 0x850, 1), /* MX35_PAD_SCKR__GPIO1_4 */
+	[265] = IMX_PIN_REG(MX35_PAD_SCKR, 0x584, 0x140, 7, 0x0, 0), /* MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 */
+	[266] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 0, 0x0, 0), /* MX35_PAD_FSR__ESAI_FSR */
+	[267] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 5, 0x854, 1), /* MX35_PAD_FSR__GPIO1_5 */
+	[268] = IMX_PIN_REG(MX35_PAD_FSR, 0x588, 0x144, 7, 0x0, 0), /* MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 */
+	[269] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 0, 0x0, 0), /* MX35_PAD_HCKR__ESAI_HCKR */
+	[270] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 1, 0x0, 0), /* MX35_PAD_HCKR__AUDMUX_AUD5_RXFS */
+	[271] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 2, 0x7f0, 0), /* MX35_PAD_HCKR__CSPI2_SS0 */
+	[272] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 3, 0x0, 0), /* MX35_PAD_HCKR__IPU_FLASH_STROBE */
+	[273] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 5, 0x858, 1), /* MX35_PAD_HCKR__GPIO1_6 */
+	[274] = IMX_PIN_REG(MX35_PAD_HCKR, 0x58c, 0x148, 7, 0x0, 0), /* MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 */
+	[275] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 0, 0x0, 0), /* MX35_PAD_SCKT__ESAI_SCKT */
+	[276] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 5, 0x85c, 1), /* MX35_PAD_SCKT__GPIO1_7 */
+	[277] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 6, 0x930, 0), /* MX35_PAD_SCKT__IPU_CSI_D_0 */
+	[278] = IMX_PIN_REG(MX35_PAD_SCKT, 0x590, 0x14c, 7, 0x978, 1), /* MX35_PAD_SCKT__KPP_ROW_2 */
+	[279] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 0, 0x0, 0), /* MX35_PAD_FST__ESAI_FST */
+	[280] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 5, 0x860, 1), /* MX35_PAD_FST__GPIO1_8 */
+	[281] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 6, 0x934, 0), /* MX35_PAD_FST__IPU_CSI_D_1 */
+	[282] = IMX_PIN_REG(MX35_PAD_FST, 0x594, 0x150, 7, 0x97c, 1), /* MX35_PAD_FST__KPP_ROW_3 */
+	[283] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 0, 0x0, 0), /* MX35_PAD_HCKT__ESAI_HCKT */
+	[284] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 1, 0x7a8, 0), /* MX35_PAD_HCKT__AUDMUX_AUD5_RXC */
+	[285] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 5, 0x864, 0), /* MX35_PAD_HCKT__GPIO1_9 */
+	[286] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 6, 0x938, 0), /* MX35_PAD_HCKT__IPU_CSI_D_2 */
+	[287] = IMX_PIN_REG(MX35_PAD_HCKT, 0x598, 0x154, 7, 0x95c, 1), /* MX35_PAD_HCKT__KPP_COL_3 */
+	[288] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 0, 0x0, 0), /* MX35_PAD_TX5_RX0__ESAI_TX5_RX0 */
+	[289] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 1, 0x0, 0), /* MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC */
+	[290] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 2, 0x7f8, 1), /* MX35_PAD_TX5_RX0__CSPI2_SS2 */
+	[291] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 3, 0x0, 0), /* MX35_PAD_TX5_RX0__CAN2_TXCAN */
+	[292] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 4, 0x0, 0), /* MX35_PAD_TX5_RX0__UART2_DTR */
+	[293] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 5, 0x830, 0), /* MX35_PAD_TX5_RX0__GPIO1_10 */
+	[294] = IMX_PIN_REG(MX35_PAD_TX5_RX0, 0x59c, 0x158, 7, 0x0, 0), /* MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 */
+	[295] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 0, 0x0, 0), /* MX35_PAD_TX4_RX1__ESAI_TX4_RX1 */
+	[296] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 1, 0x0, 0), /* MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS */
+	[297] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 2, 0x7fc, 0), /* MX35_PAD_TX4_RX1__CSPI2_SS3 */
+	[298] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 3, 0x7cc, 0), /* MX35_PAD_TX4_RX1__CAN2_RXCAN */
+	[299] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 4, 0x0, 0), /* MX35_PAD_TX4_RX1__UART2_DSR */
+	[300] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 5, 0x834, 0), /* MX35_PAD_TX4_RX1__GPIO1_11 */
+	[301] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 6, 0x93c, 0), /* MX35_PAD_TX4_RX1__IPU_CSI_D_3 */
+	[302] = IMX_PIN_REG(MX35_PAD_TX4_RX1, 0x5a0, 0x15c, 7, 0x970, 1), /* MX35_PAD_TX4_RX1__KPP_ROW_0 */
+	[303] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 0, 0x0, 0), /* MX35_PAD_TX3_RX2__ESAI_TX3_RX2 */
+	[304] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 1, 0x91c, 0), /* MX35_PAD_TX3_RX2__I2C3_SCL */
+	[305] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 3, 0x0, 0), /* MX35_PAD_TX3_RX2__EMI_NANDF_CE1 */
+	[306] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 5, 0x0, 0), /* MX35_PAD_TX3_RX2__GPIO1_12 */
+	[307] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 6, 0x940, 0), /* MX35_PAD_TX3_RX2__IPU_CSI_D_4 */
+	[308] = IMX_PIN_REG(MX35_PAD_TX3_RX2, 0x5a4, 0x160, 7, 0x974, 1), /* MX35_PAD_TX3_RX2__KPP_ROW_1 */
+	[309] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 0, 0x0, 0), /* MX35_PAD_TX2_RX3__ESAI_TX2_RX3 */
+	[310] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 1, 0x920, 0), /* MX35_PAD_TX2_RX3__I2C3_SDA */
+	[311] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 3, 0x0, 0), /* MX35_PAD_TX2_RX3__EMI_NANDF_CE2 */
+	[312] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 5, 0x0, 0), /* MX35_PAD_TX2_RX3__GPIO1_13 */
+	[313] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 6, 0x944, 0), /* MX35_PAD_TX2_RX3__IPU_CSI_D_5 */
+	[314] = IMX_PIN_REG(MX35_PAD_TX2_RX3, 0x5a8, 0x164, 7, 0x950, 1), /* MX35_PAD_TX2_RX3__KPP_COL_0 */
+	[315] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 0, 0x0, 0), /* MX35_PAD_TX1__ESAI_TX1 */
+	[316] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 1, 0x7d4, 1), /* MX35_PAD_TX1__CCM_PMIC_RDY */
+	[317] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 2, 0x7d8, 2), /* MX35_PAD_TX1__CSPI1_SS2 */
+	[318] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 3, 0x0, 0), /* MX35_PAD_TX1__EMI_NANDF_CE3 */
+	[319] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 4, 0x0, 0), /* MX35_PAD_TX1__UART2_RI */
+	[320] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 5, 0x0, 0), /* MX35_PAD_TX1__GPIO1_14 */
+	[321] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 6, 0x948, 0), /* MX35_PAD_TX1__IPU_CSI_D_6 */
+	[322] = IMX_PIN_REG(MX35_PAD_TX1, 0x5ac, 0x168, 7, 0x954, 1), /* MX35_PAD_TX1__KPP_COL_1 */
+	[323] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 0, 0x0, 0), /* MX35_PAD_TX0__ESAI_TX0 */
+	[324] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 1, 0x994, 1), /* MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK */
+	[325] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 2, 0x7dc, 0), /* MX35_PAD_TX0__CSPI1_SS3 */
+	[326] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 3, 0x800, 1), /* MX35_PAD_TX0__EMI_DTACK_B */
+	[327] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 4, 0x0, 0), /* MX35_PAD_TX0__UART2_DCD */
+	[328] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 5, 0x0, 0), /* MX35_PAD_TX0__GPIO1_15 */
+	[329] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 6, 0x94c, 0), /* MX35_PAD_TX0__IPU_CSI_D_7 */
+	[330] = IMX_PIN_REG(MX35_PAD_TX0, 0x5b0, 0x16c, 7, 0x958, 1), /* MX35_PAD_TX0__KPP_COL_2 */
+	[331] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 0, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__CSPI1_MOSI */
+	[332] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 5, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__GPIO1_16 */
+	[333] = IMX_PIN_REG(MX35_PAD_CSPI1_MOSI, 0x5b4, 0x170, 7, 0x0, 0), /* MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 */
+	[334] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 0, 0x0, 0), /* MX35_PAD_CSPI1_MISO__CSPI1_MISO */
+	[335] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 5, 0x0, 0), /* MX35_PAD_CSPI1_MISO__GPIO1_17 */
+	[336] = IMX_PIN_REG(MX35_PAD_CSPI1_MISO, 0x5b8, 0x174, 7, 0x0, 0), /* MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 */
+	[337] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS0__CSPI1_SS0 */
+	[338] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 1, 0x990, 1), /* MX35_PAD_CSPI1_SS0__OWIRE_LINE */
+	[339] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 2, 0x7fc, 1), /* MX35_PAD_CSPI1_SS0__CSPI2_SS3 */
+	[340] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS0__GPIO1_18 */
+	[341] = IMX_PIN_REG(MX35_PAD_CSPI1_SS0, 0x5bc, 0x178, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 */
+	[342] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 0, 0x0, 0), /* MX35_PAD_CSPI1_SS1__CSPI1_SS1 */
+	[343] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 1, 0x0, 0), /* MX35_PAD_CSPI1_SS1__PWM_PWMO */
+	[344] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 2, 0x7d0, 1), /* MX35_PAD_CSPI1_SS1__CCM_CLK32K */
+	[345] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 5, 0x0, 0), /* MX35_PAD_CSPI1_SS1__GPIO1_19 */
+	[346] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 6, 0x0, 0), /* MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 */
+	[347] = IMX_PIN_REG(MX35_PAD_CSPI1_SS1, 0x5c0, 0x17c, 7, 0x0, 0), /* MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 */
+	[348] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 0, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__CSPI1_SCLK */
+	[349] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 5, 0x904, 0), /* MX35_PAD_CSPI1_SCLK__GPIO3_4 */
+	[350] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 6, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 */
+	[351] = IMX_PIN_REG(MX35_PAD_CSPI1_SCLK, 0x5c4, 0x180, 7, 0x0, 0), /* MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 */
+	[352] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 0, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY */
+	[353] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 5, 0x908, 0), /* MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 */
+	[354] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 6, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 */
+	[355] = IMX_PIN_REG(MX35_PAD_CSPI1_SPI_RDY, 0x5c8, 0x184, 7, 0x0, 0), /* MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 */
+	[356] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 0, 0x0, 0), /* MX35_PAD_RXD1__UART1_RXD_MUX */
+	[357] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 1, 0x7ec, 1), /* MX35_PAD_RXD1__CSPI2_MOSI */
+	[358] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 4, 0x960, 0), /* MX35_PAD_RXD1__KPP_COL_4 */
+	[359] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 5, 0x90c, 0), /* MX35_PAD_RXD1__GPIO3_6 */
+	[360] = IMX_PIN_REG(MX35_PAD_RXD1, 0x5cc, 0x188, 7, 0x0, 0), /* MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 */
+	[361] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 0, 0x0, 0), /* MX35_PAD_TXD1__UART1_TXD_MUX */
+	[362] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 1, 0x7e8, 1), /* MX35_PAD_TXD1__CSPI2_MISO */
+	[363] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 4, 0x964, 0), /* MX35_PAD_TXD1__KPP_COL_5 */
+	[364] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 5, 0x910, 0), /* MX35_PAD_TXD1__GPIO3_7 */
+	[365] = IMX_PIN_REG(MX35_PAD_TXD1, 0x5d0, 0x18c, 7, 0x0, 0), /* MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 */
+	[366] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 0, 0x0, 0), /* MX35_PAD_RTS1__UART1_RTS */
+	[367] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 1, 0x7e0, 1), /* MX35_PAD_RTS1__CSPI2_SCLK */
+	[368] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 2, 0x91c, 1), /* MX35_PAD_RTS1__I2C3_SCL */
+	[369] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 3, 0x930, 1), /* MX35_PAD_RTS1__IPU_CSI_D_0 */
+	[370] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 4, 0x968, 0), /* MX35_PAD_RTS1__KPP_COL_6 */
+	[371] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 5, 0x914, 0), /* MX35_PAD_RTS1__GPIO3_8 */
+	[372] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 6, 0x0, 0), /* MX35_PAD_RTS1__EMI_NANDF_CE1 */
+	[373] = IMX_PIN_REG(MX35_PAD_RTS1, 0x5d4, 0x190, 7, 0x0, 0), /* MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 */
+	[374] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 0, 0x0, 0), /* MX35_PAD_CTS1__UART1_CTS */
+	[375] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 1, 0x7e4, 1), /* MX35_PAD_CTS1__CSPI2_RDY */
+	[376] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 2, 0x920, 1), /* MX35_PAD_CTS1__I2C3_SDA */
+	[377] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 3, 0x934, 1), /* MX35_PAD_CTS1__IPU_CSI_D_1 */
+	[378] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 4, 0x96c, 0), /* MX35_PAD_CTS1__KPP_COL_7 */
+	[379] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 5, 0x918, 0), /* MX35_PAD_CTS1__GPIO3_9 */
+	[380] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 6, 0x0, 0), /* MX35_PAD_CTS1__EMI_NANDF_CE2 */
+	[381] = IMX_PIN_REG(MX35_PAD_CTS1, 0x5d8, 0x194, 7, 0x0, 0), /* MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 */
+	[382] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 0, 0x0, 0), /* MX35_PAD_RXD2__UART2_RXD_MUX */
+	[383] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 4, 0x980, 0), /* MX35_PAD_RXD2__KPP_ROW_4 */
+	[384] = IMX_PIN_REG(MX35_PAD_RXD2, 0x5dc, 0x198, 5, 0x8ec, 0), /* MX35_PAD_RXD2__GPIO3_10 */
+	[385] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 0, 0x0, 0), /* MX35_PAD_TXD2__UART2_TXD_MUX */
+	[386] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 1, 0x994, 2), /* MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK */
+	[387] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 4, 0x984, 0), /* MX35_PAD_TXD2__KPP_ROW_5 */
+	[388] = IMX_PIN_REG(MX35_PAD_TXD2, 0x5e0, 0x19c, 5, 0x8f0, 0), /* MX35_PAD_TXD2__GPIO3_11 */
+	[389] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 0, 0x0, 0), /* MX35_PAD_RTS2__UART2_RTS */
+	[390] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 1, 0x998, 1), /* MX35_PAD_RTS2__SPDIF_SPDIF_IN1 */
+	[391] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 2, 0x7cc, 1), /* MX35_PAD_RTS2__CAN2_RXCAN */
+	[392] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 3, 0x938, 1), /* MX35_PAD_RTS2__IPU_CSI_D_2 */
+	[393] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 4, 0x988, 0), /* MX35_PAD_RTS2__KPP_ROW_6 */
+	[394] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 5, 0x8f4, 0), /* MX35_PAD_RTS2__GPIO3_12 */
+	[395] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 6, 0x0, 0), /* MX35_PAD_RTS2__AUDMUX_AUD5_RXC */
+	[396] = IMX_PIN_REG(MX35_PAD_RTS2, 0x5e4, 0x1a0, 7, 0x9a0, 0), /* MX35_PAD_RTS2__UART3_RXD_MUX */
+	[397] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 0, 0x0, 0), /* MX35_PAD_CTS2__UART2_CTS */
+	[398] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 1, 0x0, 0), /* MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 */
+	[399] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 2, 0x0, 0), /* MX35_PAD_CTS2__CAN2_TXCAN */
+	[400] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 3, 0x93c, 1), /* MX35_PAD_CTS2__IPU_CSI_D_3 */
+	[401] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 4, 0x98c, 0), /* MX35_PAD_CTS2__KPP_ROW_7 */
+	[402] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 5, 0x8f8, 0), /* MX35_PAD_CTS2__GPIO3_13 */
+	[403] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 6, 0x0, 0), /* MX35_PAD_CTS2__AUDMUX_AUD5_RXFS */
+	[404] = IMX_PIN_REG(MX35_PAD_CTS2, 0x5e8, 0x1a4, 7, 0x0, 0), /* MX35_PAD_CTS2__UART3_TXD_MUX */
+	[405] = IMX_PIN_REG(MX35_PAD_RTCK, 0x5ec, 0x0, 0, 0x0, 0), /* MX35_PAD_RTCK__ARM11P_TOP_RTCK */
+	[406] = IMX_PIN_REG(MX35_PAD_TCK, 0x5f0, 0x0, 0, 0x0, 0), /* MX35_PAD_TCK__SJC_TCK */
+	[407] = IMX_PIN_REG(MX35_PAD_TMS, 0x5f4, 0x0, 0, 0x0, 0), /* MX35_PAD_TMS__SJC_TMS */
+	[408] = IMX_PIN_REG(MX35_PAD_TDI, 0x5f8, 0x0, 0, 0x0, 0), /* MX35_PAD_TDI__SJC_TDI */
+	[409] = IMX_PIN_REG(MX35_PAD_TDO, 0x5fc, 0x0, 0, 0x0, 0), /* MX35_PAD_TDO__SJC_TDO */
+	[410] = IMX_PIN_REG(MX35_PAD_TRSTB, 0x600, 0x0, 0, 0x0, 0), /* MX35_PAD_TRSTB__SJC_TRSTB */
+	[411] = IMX_PIN_REG(MX35_PAD_DE_B, 0x604, 0x0, 0, 0x0, 0), /* MX35_PAD_DE_B__SJC_DE_B */
+	[412] = IMX_PIN_REG(MX35_PAD_SJC_MOD, 0x608, 0x0, 0, 0x0, 0), /* MX35_PAD_SJC_MOD__SJC_MOD */
+	[413] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 0, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR */
+	[414] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 1, 0x0, 0), /* MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR */
+	[415] = IMX_PIN_REG(MX35_PAD_USBOTG_PWR, 0x60c, 0x1a8, 5, 0x8fc, 0), /* MX35_PAD_USBOTG_PWR__GPIO3_14 */
+	[416] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 0, 0x0, 0), /* MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC */
+	[417] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 1, 0x9f4, 1), /* MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC */
+	[418] = IMX_PIN_REG(MX35_PAD_USBOTG_OC, 0x610, 0x1ac, 5, 0x900, 0), /* MX35_PAD_USBOTG_OC__GPIO3_15 */
+	[419] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 0, 0x0, 0), /* MX35_PAD_LD0__IPU_DISPB_DAT_0 */
+	[420] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 5, 0x868, 1), /* MX35_PAD_LD0__GPIO2_0 */
+	[421] = IMX_PIN_REG(MX35_PAD_LD0, 0x614, 0x1b0, 6, 0x0, 0), /* MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 */
+	[422] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 0, 0x0, 0), /* MX35_PAD_LD1__IPU_DISPB_DAT_1 */
+	[423] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 5, 0x894, 0), /* MX35_PAD_LD1__GPIO2_1 */
+	[424] = IMX_PIN_REG(MX35_PAD_LD1, 0x618, 0x1b4, 6, 0x0, 0), /* MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 */
+	[425] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 0, 0x0, 0), /* MX35_PAD_LD2__IPU_DISPB_DAT_2 */
+	[426] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 5, 0x8c0, 0), /* MX35_PAD_LD2__GPIO2_2 */
+	[427] = IMX_PIN_REG(MX35_PAD_LD2, 0x61c, 0x1b8, 6, 0x0, 0), /* MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 */
+	[428] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 0, 0x0, 0), /* MX35_PAD_LD3__IPU_DISPB_DAT_3 */
+	[429] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 5, 0x8cc, 0), /* MX35_PAD_LD3__GPIO2_3 */
+	[430] = IMX_PIN_REG(MX35_PAD_LD3, 0x620, 0x1bc, 6, 0x0, 0), /* MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 */
+	[431] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 0, 0x0, 0), /* MX35_PAD_LD4__IPU_DISPB_DAT_4 */
+	[432] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 5, 0x8d0, 0), /* MX35_PAD_LD4__GPIO2_4 */
+	[433] = IMX_PIN_REG(MX35_PAD_LD4, 0x624, 0x1c0, 6, 0x0, 0), /* MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 */
+	[434] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 0, 0x0, 0), /* MX35_PAD_LD5__IPU_DISPB_DAT_5 */
+	[435] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 5, 0x8d4, 0), /* MX35_PAD_LD5__GPIO2_5 */
+	[436] = IMX_PIN_REG(MX35_PAD_LD5, 0x628, 0x1c4, 6, 0x0, 0), /* MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 */
+	[437] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 0, 0x0, 0), /* MX35_PAD_LD6__IPU_DISPB_DAT_6 */
+	[438] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 5, 0x8d8, 0), /* MX35_PAD_LD6__GPIO2_6 */
+	[439] = IMX_PIN_REG(MX35_PAD_LD6, 0x62c, 0x1c8, 6, 0x0, 0), /* MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 */
+	[440] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 0, 0x0, 0), /* MX35_PAD_LD7__IPU_DISPB_DAT_7 */
+	[441] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 5, 0x8dc, 0), /* MX35_PAD_LD7__GPIO2_7 */
+	[442] = IMX_PIN_REG(MX35_PAD_LD7, 0x630, 0x1cc, 6, 0x0, 0), /* MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 */
+	[443] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 0, 0x0, 0), /* MX35_PAD_LD8__IPU_DISPB_DAT_8 */
+	[444] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 5, 0x8e0, 0), /* MX35_PAD_LD8__GPIO2_8 */
+	[445] = IMX_PIN_REG(MX35_PAD_LD8, 0x634, 0x1d0, 6, 0x0, 0), /* MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 */
+	[446] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 0, 0x0, 0), /* MX35_PAD_LD9__IPU_DISPB_DAT_9 */
+	[447] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 5, 0x8e4, 0), /* MX35_PAD_LD9__GPIO2_9 */
+	[448] = IMX_PIN_REG(MX35_PAD_LD9, 0x638, 0x1d4, 6, 0x0, 0), /* MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 */
+	[449] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 0, 0x0, 0), /* MX35_PAD_LD10__IPU_DISPB_DAT_10 */
+	[450] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 5, 0x86c, 0), /* MX35_PAD_LD10__GPIO2_10 */
+	[451] = IMX_PIN_REG(MX35_PAD_LD10, 0x63c, 0x1d8, 6, 0x0, 0), /* MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 */
+	[452] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 0, 0x0, 0), /* MX35_PAD_LD11__IPU_DISPB_DAT_11 */
+	[453] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 5, 0x870, 0), /* MX35_PAD_LD11__GPIO2_11 */
+	[454] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 6, 0x0, 0), /* MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 */
+	[455] = IMX_PIN_REG(MX35_PAD_LD11, 0x640, 0x1dc, 7, 0x0, 0), /* MX35_PAD_LD11__ARM11P_TOP_TRACE_4 */
+	[456] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 0, 0x0, 0), /* MX35_PAD_LD12__IPU_DISPB_DAT_12 */
+	[457] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 5, 0x874, 0), /* MX35_PAD_LD12__GPIO2_12 */
+	[458] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 6, 0x0, 0), /* MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 */
+	[459] = IMX_PIN_REG(MX35_PAD_LD12, 0x644, 0x1e0, 7, 0x0, 0), /* MX35_PAD_LD12__ARM11P_TOP_TRACE_5 */
+	[460] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 0, 0x0, 0), /* MX35_PAD_LD13__IPU_DISPB_DAT_13 */
+	[461] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 5, 0x878, 0), /* MX35_PAD_LD13__GPIO2_13 */
+	[462] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 6, 0x0, 0), /* MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 */
+	[463] = IMX_PIN_REG(MX35_PAD_LD13, 0x648, 0x1e4, 7, 0x0, 0), /* MX35_PAD_LD13__ARM11P_TOP_TRACE_6 */
+	[464] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 0, 0x0, 0), /* MX35_PAD_LD14__IPU_DISPB_DAT_14 */
+	[465] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 5, 0x87c, 0), /* MX35_PAD_LD14__GPIO2_14 */
+	[466] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 6, 0x0, 0), /* MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 */
+	[467] = IMX_PIN_REG(MX35_PAD_LD14, 0x64c, 0x1e8, 7, 0x0, 0), /* MX35_PAD_LD14__ARM11P_TOP_TRACE_7 */
+	[468] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 0, 0x0, 0), /* MX35_PAD_LD15__IPU_DISPB_DAT_15 */
+	[469] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 5, 0x880, 0), /* MX35_PAD_LD15__GPIO2_15 */
+	[470] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 6, 0x0, 0), /* MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 */
+	[471] = IMX_PIN_REG(MX35_PAD_LD15, 0x650, 0x1ec, 7, 0x0, 0), /* MX35_PAD_LD15__ARM11P_TOP_TRACE_8 */
+	[472] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 0, 0x0, 0), /* MX35_PAD_LD16__IPU_DISPB_DAT_16 */
+	[473] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 2, 0x928, 0), /* MX35_PAD_LD16__IPU_DISPB_D12_VSYNC */
+	[474] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 5, 0x884, 0), /* MX35_PAD_LD16__GPIO2_16 */
+	[475] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 6, 0x0, 0), /* MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 */
+	[476] = IMX_PIN_REG(MX35_PAD_LD16, 0x654, 0x1f0, 7, 0x0, 0), /* MX35_PAD_LD16__ARM11P_TOP_TRACE_9 */
+	[477] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 0, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_DAT_17 */
+	[478] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 2, 0x0, 0), /* MX35_PAD_LD17__IPU_DISPB_CS2 */
+	[479] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 5, 0x888, 0), /* MX35_PAD_LD17__GPIO2_17 */
+	[480] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 6, 0x0, 0), /* MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 */
+	[481] = IMX_PIN_REG(MX35_PAD_LD17, 0x658, 0x1f4, 7, 0x0, 0), /* MX35_PAD_LD17__ARM11P_TOP_TRACE_10 */
+	[482] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 0, 0x0, 0), /* MX35_PAD_LD18__IPU_DISPB_DAT_18 */
+	[483] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 1, 0x924, 1), /* MX35_PAD_LD18__IPU_DISPB_D0_VSYNC */
+	[484] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 2, 0x928, 1), /* MX35_PAD_LD18__IPU_DISPB_D12_VSYNC */
+	[485] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 3, 0x818, 0), /* MX35_PAD_LD18__ESDHC3_CMD */
+	[486] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 4, 0x9b0, 0), /* MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 */
+	[487] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 5, 0x0, 0), /* MX35_PAD_LD18__GPIO3_24 */
+	[488] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 6, 0x0, 0), /* MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 */
+	[489] = IMX_PIN_REG(MX35_PAD_LD18, 0x65c, 0x1f8, 7, 0x0, 0), /* MX35_PAD_LD18__ARM11P_TOP_TRACE_11 */
+	[490] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 0, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_DAT_19 */
+	[491] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 1, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_BCLK */
+	[492] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 2, 0x0, 0), /* MX35_PAD_LD19__IPU_DISPB_CS1 */
+	[493] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 3, 0x814, 0), /* MX35_PAD_LD19__ESDHC3_CLK */
+	[494] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 4, 0x9c4, 0), /* MX35_PAD_LD19__USB_TOP_USBOTG_DIR */
+	[495] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 5, 0x0, 0), /* MX35_PAD_LD19__GPIO3_25 */
+	[496] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 6, 0x0, 0), /* MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 */
+	[497] = IMX_PIN_REG(MX35_PAD_LD19, 0x660, 0x1fc, 7, 0x0, 0), /* MX35_PAD_LD19__ARM11P_TOP_TRACE_12 */
+	[498] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 0, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_DAT_20 */
+	[499] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 1, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_CS0 */
+	[500] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 2, 0x0, 0), /* MX35_PAD_LD20__IPU_DISPB_SD_CLK */
+	[501] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 3, 0x81c, 0), /* MX35_PAD_LD20__ESDHC3_DAT0 */
+	[502] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 5, 0x0, 0), /* MX35_PAD_LD20__GPIO3_26 */
+	[503] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 6, 0x0, 0), /* MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 */
+	[504] = IMX_PIN_REG(MX35_PAD_LD20, 0x664, 0x200, 7, 0x0, 0), /* MX35_PAD_LD20__ARM11P_TOP_TRACE_13 */
+	[505] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 0, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_DAT_21 */
+	[506] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 1, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_PAR_RS */
+	[507] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 2, 0x0, 0), /* MX35_PAD_LD21__IPU_DISPB_SER_RS */
+	[508] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 3, 0x820, 0), /* MX35_PAD_LD21__ESDHC3_DAT1 */
+	[509] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 4, 0x0, 0), /* MX35_PAD_LD21__USB_TOP_USBOTG_STP */
+	[510] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 5, 0x0, 0), /* MX35_PAD_LD21__GPIO3_27 */
+	[511] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 6, 0x0, 0), /* MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL */
+	[512] = IMX_PIN_REG(MX35_PAD_LD21, 0x668, 0x204, 7, 0x0, 0), /* MX35_PAD_LD21__ARM11P_TOP_TRACE_14 */
+	[513] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 0, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_DAT_22 */
+	[514] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 1, 0x0, 0), /* MX35_PAD_LD22__IPU_DISPB_WR */
+	[515] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 2, 0x92c, 0), /* MX35_PAD_LD22__IPU_DISPB_SD_D_I */
+	[516] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 3, 0x824, 0), /* MX35_PAD_LD22__ESDHC3_DAT2 */
+	[517] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 4, 0x9c8, 0), /* MX35_PAD_LD22__USB_TOP_USBOTG_NXT */
+	[518] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 5, 0x0, 0), /* MX35_PAD_LD22__GPIO3_28 */
+	[519] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 6, 0x0, 0), /* MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR */
+	[520] = IMX_PIN_REG(MX35_PAD_LD22, 0x66c, 0x208, 7, 0x0, 0), /* MX35_PAD_LD22__ARM11P_TOP_TRCTL */
+	[521] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 0, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_DAT_23 */
+	[522] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 1, 0x0, 0), /* MX35_PAD_LD23__IPU_DISPB_RD */
+	[523] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 2, 0x92c, 1), /* MX35_PAD_LD23__IPU_DISPB_SD_D_IO */
+	[524] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 3, 0x828, 0), /* MX35_PAD_LD23__ESDHC3_DAT3 */
+	[525] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 4, 0x9c0, 0), /* MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 */
+	[526] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 5, 0x0, 0), /* MX35_PAD_LD23__GPIO3_29 */
+	[527] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 6, 0x0, 0), /* MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS */
+	[528] = IMX_PIN_REG(MX35_PAD_LD23, 0x670, 0x20c, 7, 0x0, 0), /* MX35_PAD_LD23__ARM11P_TOP_TRCLK */
+	[529] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 0, 0x0, 0), /* MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC */
+	[530] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 2, 0x92c, 2), /* MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO */
+	[531] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 5, 0x0, 0), /* MX35_PAD_D3_HSYNC__GPIO3_30 */
+	[532] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 6, 0x0, 0), /* MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE */
+	[533] = IMX_PIN_REG(MX35_PAD_D3_HSYNC, 0x674, 0x210, 7, 0x0, 0), /* MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 */
+	[534] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 0, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK */
+	[535] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 2, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK */
+	[536] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 5, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__GPIO3_31 */
+	[537] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 6, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 */
+	[538] = IMX_PIN_REG(MX35_PAD_D3_FPSHIFT, 0x678, 0x214, 7, 0x0, 0), /* MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 */
+	[539] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 0, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY */
+	[540] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 2, 0x0, 0), /* MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O */
+	[541] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 5, 0x82c, 2), /* MX35_PAD_D3_DRDY__GPIO1_0 */
+	[542] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 6, 0x0, 0), /* MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 */
+	[543] = IMX_PIN_REG(MX35_PAD_D3_DRDY, 0x67c, 0x218, 7, 0x0, 0), /* MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 */
+	[544] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 0, 0x0, 0), /* MX35_PAD_CONTRAST__IPU_DISPB_CONTR */
+	[545] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 5, 0x838, 2), /* MX35_PAD_CONTRAST__GPIO1_1 */
+	[546] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 6, 0x0, 0), /* MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 */
+	[547] = IMX_PIN_REG(MX35_PAD_CONTRAST, 0x680, 0x21c, 7, 0x0, 0), /* MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 */
+	[548] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 0, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC */
+	[549] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 2, 0x0, 0), /* MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 */
+	[550] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 5, 0x848, 1), /* MX35_PAD_D3_VSYNC__GPIO1_2 */
+	[551] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 6, 0x0, 0), /* MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD */
+	[552] = IMX_PIN_REG(MX35_PAD_D3_VSYNC, 0x684, 0x220, 7, 0x0, 0), /* MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 */
+	[553] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 0, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_D3_REV */
+	[554] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 2, 0x0, 0), /* MX35_PAD_D3_REV__IPU_DISPB_SER_RS */
+	[555] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 5, 0x84c, 1), /* MX35_PAD_D3_REV__GPIO1_3 */
+	[556] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 6, 0x0, 0), /* MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB */
+	[557] = IMX_PIN_REG(MX35_PAD_D3_REV, 0x688, 0x224, 7, 0x0, 0), /* MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 */
+	[558] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 0, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS */
+	[559] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 2, 0x0, 0), /* MX35_PAD_D3_CLS__IPU_DISPB_CS2 */
+	[560] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 5, 0x850, 2), /* MX35_PAD_D3_CLS__GPIO1_4 */
+	[561] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 6, 0x0, 0), /* MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 */
+	[562] = IMX_PIN_REG(MX35_PAD_D3_CLS, 0x68c, 0x228, 7, 0x0, 0), /* MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 */
+	[563] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 0, 0x0, 0), /* MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL */
+	[564] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 2, 0x928, 2), /* MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC */
+	[565] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 5, 0x854, 2), /* MX35_PAD_D3_SPL__GPIO1_5 */
+	[566] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 6, 0x0, 0), /* MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 */
+	[567] = IMX_PIN_REG(MX35_PAD_D3_SPL, 0x690, 0x22c, 7, 0x0, 0), /* MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 */
+	[568] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 0, 0x0, 0), /* MX35_PAD_SD1_CMD__ESDHC1_CMD */
+	[569] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 1, 0x0, 0), /* MX35_PAD_SD1_CMD__MSHC_SCLK */
+	[570] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 3, 0x924, 2), /* MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC */
+	[571] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 4, 0x9b4, 0), /* MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 */
+	[572] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 5, 0x858, 2), /* MX35_PAD_SD1_CMD__GPIO1_6 */
+	[573] = IMX_PIN_REG(MX35_PAD_SD1_CMD, 0x694, 0x230, 7, 0x0, 0), /* MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL */
+	[574] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 0, 0x0, 0), /* MX35_PAD_SD1_CLK__ESDHC1_CLK */
+	[575] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 1, 0x0, 0), /* MX35_PAD_SD1_CLK__MSHC_BS */
+	[576] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 3, 0x0, 0), /* MX35_PAD_SD1_CLK__IPU_DISPB_BCLK */
+	[577] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 4, 0x9b8, 0), /* MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 */
+	[578] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 5, 0x85c, 2), /* MX35_PAD_SD1_CLK__GPIO1_7 */
+	[579] = IMX_PIN_REG(MX35_PAD_SD1_CLK, 0x698, 0x234, 7, 0x0, 0), /* MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK */
+	[580] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 0, 0x0, 0), /* MX35_PAD_SD1_DATA0__ESDHC1_DAT0 */
+	[581] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 1, 0x0, 0), /* MX35_PAD_SD1_DATA0__MSHC_DATA_0 */
+	[582] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 3, 0x0, 0), /* MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 */
+	[583] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 4, 0x9bc, 0), /* MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 */
+	[584] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 5, 0x860, 2), /* MX35_PAD_SD1_DATA0__GPIO1_8 */
+	[585] = IMX_PIN_REG(MX35_PAD_SD1_DATA0, 0x69c, 0x238, 7, 0x0, 0), /* MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 */
+	[586] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 0, 0x0, 0), /* MX35_PAD_SD1_DATA1__ESDHC1_DAT1 */
+	[587] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 1, 0x0, 0), /* MX35_PAD_SD1_DATA1__MSHC_DATA_1 */
+	[588] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 3, 0x0, 0), /* MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS */
+	[589] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 4, 0x9a4, 0), /* MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 */
+	[590] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 5, 0x864, 1), /* MX35_PAD_SD1_DATA1__GPIO1_9 */
+	[591] = IMX_PIN_REG(MX35_PAD_SD1_DATA1, 0x6a0, 0x23c, 7, 0x0, 0), /* MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 */
+	[592] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 0, 0x0, 0), /* MX35_PAD_SD1_DATA2__ESDHC1_DAT2 */
+	[593] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 1, 0x0, 0), /* MX35_PAD_SD1_DATA2__MSHC_DATA_2 */
+	[594] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 3, 0x0, 0), /* MX35_PAD_SD1_DATA2__IPU_DISPB_WR */
+	[595] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 4, 0x9a8, 0), /* MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 */
+	[596] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 5, 0x830, 1), /* MX35_PAD_SD1_DATA2__GPIO1_10 */
+	[597] = IMX_PIN_REG(MX35_PAD_SD1_DATA2, 0x6a4, 0x240, 7, 0x0, 0), /* MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 */
+	[598] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 0, 0x0, 0), /* MX35_PAD_SD1_DATA3__ESDHC1_DAT3 */
+	[599] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 1, 0x0, 0), /* MX35_PAD_SD1_DATA3__MSHC_DATA_3 */
+	[600] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 3, 0x0, 0), /* MX35_PAD_SD1_DATA3__IPU_DISPB_RD */
+	[601] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 4, 0x9ac, 0), /* MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 */
+	[602] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 5, 0x834, 1), /* MX35_PAD_SD1_DATA3__GPIO1_11 */
+	[603] = IMX_PIN_REG(MX35_PAD_SD1_DATA3, 0x6a8, 0x244, 7, 0x0, 0), /* MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 */
+	[604] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 0, 0x0, 0), /* MX35_PAD_SD2_CMD__ESDHC2_CMD */
+	[605] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 1, 0x91c, 2), /* MX35_PAD_SD2_CMD__I2C3_SCL */
+	[606] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 2, 0x804, 0), /* MX35_PAD_SD2_CMD__ESDHC1_DAT4 */
+	[607] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 3, 0x938, 2), /* MX35_PAD_SD2_CMD__IPU_CSI_D_2 */
+	[608] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 4, 0x9dc, 0), /* MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 */
+	[609] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 5, 0x868, 2), /* MX35_PAD_SD2_CMD__GPIO2_0 */
+	[610] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 6, 0x0, 0), /* MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 */
+	[611] = IMX_PIN_REG(MX35_PAD_SD2_CMD, 0x6ac, 0x248, 7, 0x928, 3), /* MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC */
+	[612] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 0, 0x0, 0), /* MX35_PAD_SD2_CLK__ESDHC2_CLK */
+	[613] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 1, 0x920, 2), /* MX35_PAD_SD2_CLK__I2C3_SDA */
+	[614] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 2, 0x808, 0), /* MX35_PAD_SD2_CLK__ESDHC1_DAT5 */
+	[615] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 3, 0x93c, 2), /* MX35_PAD_SD2_CLK__IPU_CSI_D_3 */
+	[616] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 4, 0x9e0, 0), /* MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 */
+	[617] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 5, 0x894, 1), /* MX35_PAD_SD2_CLK__GPIO2_1 */
+	[618] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 6, 0x998, 2), /* MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 */
+	[619] = IMX_PIN_REG(MX35_PAD_SD2_CLK, 0x6b0, 0x24c, 7, 0x0, 0), /* MX35_PAD_SD2_CLK__IPU_DISPB_CS2 */
+	[620] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 0, 0x0, 0), /* MX35_PAD_SD2_DATA0__ESDHC2_DAT0 */
+	[621] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 1, 0x9a0, 1), /* MX35_PAD_SD2_DATA0__UART3_RXD_MUX */
+	[622] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 2, 0x80c, 0), /* MX35_PAD_SD2_DATA0__ESDHC1_DAT6 */
+	[623] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 3, 0x940, 1), /* MX35_PAD_SD2_DATA0__IPU_CSI_D_4 */
+	[624] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 4, 0x9e4, 0), /* MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 */
+	[625] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 5, 0x8c0, 1), /* MX35_PAD_SD2_DATA0__GPIO2_2 */
+	[626] = IMX_PIN_REG(MX35_PAD_SD2_DATA0, 0x6b4, 0x250, 6, 0x994, 3), /* MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK */
+	[627] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 0, 0x0, 0), /* MX35_PAD_SD2_DATA1__ESDHC2_DAT1 */
+	[628] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 1, 0x0, 0), /* MX35_PAD_SD2_DATA1__UART3_TXD_MUX */
+	[629] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 2, 0x810, 0), /* MX35_PAD_SD2_DATA1__ESDHC1_DAT7 */
+	[630] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 3, 0x944, 1), /* MX35_PAD_SD2_DATA1__IPU_CSI_D_5 */
+	[631] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 4, 0x9cc, 0), /* MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 */
+	[632] = IMX_PIN_REG(MX35_PAD_SD2_DATA1, 0x6b8, 0x254, 5, 0x8cc, 1), /* MX35_PAD_SD2_DATA1__GPIO2_3 */
+	[633] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 0, 0x0, 0), /* MX35_PAD_SD2_DATA2__ESDHC2_DAT2 */
+	[634] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 1, 0x99c, 0), /* MX35_PAD_SD2_DATA2__UART3_RTS */
+	[635] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 2, 0x7c8, 1), /* MX35_PAD_SD2_DATA2__CAN1_RXCAN */
+	[636] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 3, 0x948, 1), /* MX35_PAD_SD2_DATA2__IPU_CSI_D_6 */
+	[637] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 4, 0x9d0, 0), /* MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 */
+	[638] = IMX_PIN_REG(MX35_PAD_SD2_DATA2, 0x6bc, 0x258, 5, 0x8d0, 1), /* MX35_PAD_SD2_DATA2__GPIO2_4 */
+	[639] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 0, 0x0, 0), /* MX35_PAD_SD2_DATA3__ESDHC2_DAT3 */
+	[640] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 1, 0x0, 0), /* MX35_PAD_SD2_DATA3__UART3_CTS */
+	[641] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 2, 0x0, 0), /* MX35_PAD_SD2_DATA3__CAN1_TXCAN */
+	[642] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 3, 0x94c, 1), /* MX35_PAD_SD2_DATA3__IPU_CSI_D_7 */
+	[643] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 4, 0x9d4, 0), /* MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 */
+	[644] = IMX_PIN_REG(MX35_PAD_SD2_DATA3, 0x6c0, 0x25c, 5, 0x8d4, 1), /* MX35_PAD_SD2_DATA3__GPIO2_5 */
+	[645] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 0, 0x0, 0), /* MX35_PAD_ATA_CS0__ATA_CS0 */
+	[646] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 1, 0x7dc, 1), /* MX35_PAD_ATA_CS0__CSPI1_SS3 */
+	[647] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 3, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DISPB_CS1 */
+	[648] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 5, 0x8d8, 1), /* MX35_PAD_ATA_CS0__GPIO2_6 */
+	[649] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 6, 0x0, 0), /* MX35_PAD_ATA_CS0__IPU_DIAGB_0 */
+	[650] = IMX_PIN_REG(MX35_PAD_ATA_CS0, 0x6c4, 0x260, 7, 0x0, 0), /* MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 */
+	[651] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 0, 0x0, 0), /* MX35_PAD_ATA_CS1__ATA_CS1 */
+	[652] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 3, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DISPB_CS2 */
+	[653] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 4, 0x7f0, 1), /* MX35_PAD_ATA_CS1__CSPI2_SS0 */
+	[654] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 5, 0x8dc, 1), /* MX35_PAD_ATA_CS1__GPIO2_7 */
+	[655] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 6, 0x0, 0), /* MX35_PAD_ATA_CS1__IPU_DIAGB_1 */
+	[656] = IMX_PIN_REG(MX35_PAD_ATA_CS1, 0x6c8, 0x264, 7, 0x0, 0), /* MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 */
+	[657] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 0, 0x0, 0), /* MX35_PAD_ATA_DIOR__ATA_DIOR */
+	[658] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 1, 0x81c, 1), /* MX35_PAD_ATA_DIOR__ESDHC3_DAT0 */
+	[659] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 2, 0x9c4, 1), /* MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR */
+	[660] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 3, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 */
+	[661] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 4, 0x7f4, 1), /* MX35_PAD_ATA_DIOR__CSPI2_SS1 */
+	[662] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 5, 0x8e0, 1), /* MX35_PAD_ATA_DIOR__GPIO2_8 */
+	[663] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 6, 0x0, 0), /* MX35_PAD_ATA_DIOR__IPU_DIAGB_2 */
+	[664] = IMX_PIN_REG(MX35_PAD_ATA_DIOR, 0x6cc, 0x268, 7, 0x0, 0), /* MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 */
+	[665] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 0, 0x0, 0), /* MX35_PAD_ATA_DIOW__ATA_DIOW */
+	[666] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 1, 0x820, 1), /* MX35_PAD_ATA_DIOW__ESDHC3_DAT1 */
+	[667] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 2, 0x0, 0), /* MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP */
+	[668] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 3, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 */
+	[669] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 4, 0x7ec, 2), /* MX35_PAD_ATA_DIOW__CSPI2_MOSI */
+	[670] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 5, 0x8e4, 1), /* MX35_PAD_ATA_DIOW__GPIO2_9 */
+	[671] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 6, 0x0, 0), /* MX35_PAD_ATA_DIOW__IPU_DIAGB_3 */
+	[672] = IMX_PIN_REG(MX35_PAD_ATA_DIOW, 0x6d0, 0x26c, 7, 0x0, 0), /* MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 */
+	[673] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 0, 0x0, 0), /* MX35_PAD_ATA_DMACK__ATA_DMACK */
+	[674] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 1, 0x824, 1), /* MX35_PAD_ATA_DMACK__ESDHC3_DAT2 */
+	[675] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 2, 0x9c8, 1), /* MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT */
+	[676] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 4, 0x7e8, 2), /* MX35_PAD_ATA_DMACK__CSPI2_MISO */
+	[677] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 5, 0x86c, 1), /* MX35_PAD_ATA_DMACK__GPIO2_10 */
+	[678] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 6, 0x0, 0), /* MX35_PAD_ATA_DMACK__IPU_DIAGB_4 */
+	[679] = IMX_PIN_REG(MX35_PAD_ATA_DMACK, 0x6d4, 0x270, 7, 0x0, 0), /* MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 */
+	[680] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 0, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ATA_RESET_B */
+	[681] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 1, 0x828, 1), /* MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 */
+	[682] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 2, 0x9a4, 1), /* MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 */
+	[683] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 3, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O */
+	[684] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 4, 0x7e4, 2), /* MX35_PAD_ATA_RESET_B__CSPI2_RDY */
+	[685] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 5, 0x870, 1), /* MX35_PAD_ATA_RESET_B__GPIO2_11 */
+	[686] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 6, 0x0, 0), /* MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 */
+	[687] = IMX_PIN_REG(MX35_PAD_ATA_RESET_B, 0x6d8, 0x274, 7, 0x0, 0), /* MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 */
+	[688] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 0, 0x0, 0), /* MX35_PAD_ATA_IORDY__ATA_IORDY */
+	[689] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 1, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC3_DAT4 */
+	[690] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 2, 0x9a8, 1), /* MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 */
+	[691] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 3, 0x92c, 3), /* MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO */
+	[692] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 4, 0x0, 0), /* MX35_PAD_ATA_IORDY__ESDHC2_DAT4 */
+	[693] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 5, 0x874, 1), /* MX35_PAD_ATA_IORDY__GPIO2_12 */
+	[694] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 6, 0x0, 0), /* MX35_PAD_ATA_IORDY__IPU_DIAGB_6 */
+	[695] = IMX_PIN_REG(MX35_PAD_ATA_IORDY, 0x6dc, 0x278, 7, 0x0, 0), /* MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 */
+	[696] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA0__ATA_DATA_0 */
+	[697] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 1, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC3_DAT5 */
+	[698] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 2, 0x9ac, 1), /* MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 */
+	[699] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 3, 0x928, 4), /* MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC */
+	[700] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 4, 0x0, 0), /* MX35_PAD_ATA_DATA0__ESDHC2_DAT5 */
+	[701] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 5, 0x878, 1), /* MX35_PAD_ATA_DATA0__GPIO2_13 */
+	[702] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA0__IPU_DIAGB_7 */
+	[703] = IMX_PIN_REG(MX35_PAD_ATA_DATA0, 0x6e0, 0x27c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 */
+	[704] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 0, 0x0, 0), /* MX35_PAD_ATA_DATA1__ATA_DATA_1 */
+	[705] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 1, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC3_DAT6 */
+	[706] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 2, 0x9b0, 1), /* MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 */
+	[707] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 3, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK */
+	[708] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 4, 0x0, 0), /* MX35_PAD_ATA_DATA1__ESDHC2_DAT6 */
+	[709] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 5, 0x87c, 1), /* MX35_PAD_ATA_DATA1__GPIO2_14 */
+	[710] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 6, 0x0, 0), /* MX35_PAD_ATA_DATA1__IPU_DIAGB_8 */
+	[711] = IMX_PIN_REG(MX35_PAD_ATA_DATA1, 0x6e4, 0x280, 7, 0x0, 0), /* MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 */
+	[712] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 0, 0x0, 0), /* MX35_PAD_ATA_DATA2__ATA_DATA_2 */
+	[713] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 1, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC3_DAT7 */
+	[714] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 2, 0x9b4, 1), /* MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 */
+	[715] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 3, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS */
+	[716] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 4, 0x0, 0), /* MX35_PAD_ATA_DATA2__ESDHC2_DAT7 */
+	[717] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 5, 0x880, 1), /* MX35_PAD_ATA_DATA2__GPIO2_15 */
+	[718] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 6, 0x0, 0), /* MX35_PAD_ATA_DATA2__IPU_DIAGB_9 */
+	[719] = IMX_PIN_REG(MX35_PAD_ATA_DATA2, 0x6e8, 0x284, 7, 0x0, 0), /* MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 */
+	[720] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 0, 0x0, 0), /* MX35_PAD_ATA_DATA3__ATA_DATA_3 */
+	[721] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 1, 0x814, 1), /* MX35_PAD_ATA_DATA3__ESDHC3_CLK */
+	[722] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 2, 0x9b8, 1), /* MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 */
+	[723] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 4, 0x7e0, 2), /* MX35_PAD_ATA_DATA3__CSPI2_SCLK */
+	[724] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 5, 0x884, 1), /* MX35_PAD_ATA_DATA3__GPIO2_16 */
+	[725] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 6, 0x0, 0), /* MX35_PAD_ATA_DATA3__IPU_DIAGB_10 */
+	[726] = IMX_PIN_REG(MX35_PAD_ATA_DATA3, 0x6ec, 0x288, 7, 0x0, 0), /* MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 */
+	[727] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA4__ATA_DATA_4 */
+	[728] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 1, 0x818, 1), /* MX35_PAD_ATA_DATA4__ESDHC3_CMD */
+	[729] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 2, 0x9bc, 1), /* MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 */
+	[730] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 5, 0x888, 1), /* MX35_PAD_ATA_DATA4__GPIO2_17 */
+	[731] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA4__IPU_DIAGB_11 */
+	[732] = IMX_PIN_REG(MX35_PAD_ATA_DATA4, 0x6f0, 0x28c, 7, 0x0, 0), /* MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 */
+	[733] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 0, 0x0, 0), /* MX35_PAD_ATA_DATA5__ATA_DATA_5 */
+	[734] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 2, 0x9c0, 1), /* MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 */
+	[735] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 5, 0x88c, 1), /* MX35_PAD_ATA_DATA5__GPIO2_18 */
+	[736] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 6, 0x0, 0), /* MX35_PAD_ATA_DATA5__IPU_DIAGB_12 */
+	[737] = IMX_PIN_REG(MX35_PAD_ATA_DATA5, 0x6f4, 0x290, 7, 0x0, 0), /* MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 */
+	[738] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 0, 0x0, 0), /* MX35_PAD_ATA_DATA6__ATA_DATA_6 */
+	[739] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 1, 0x0, 0), /* MX35_PAD_ATA_DATA6__CAN1_TXCAN */
+	[740] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 2, 0x0, 0), /* MX35_PAD_ATA_DATA6__UART1_DTR */
+	[741] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 3, 0x7b4, 0), /* MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD */
+	[742] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 5, 0x890, 1), /* MX35_PAD_ATA_DATA6__GPIO2_19 */
+	[743] = IMX_PIN_REG(MX35_PAD_ATA_DATA6, 0x6f8, 0x294, 6, 0x0, 0), /* MX35_PAD_ATA_DATA6__IPU_DIAGB_13 */
+	[744] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 0, 0x0, 0), /* MX35_PAD_ATA_DATA7__ATA_DATA_7 */
+	[745] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 1, 0x7c8, 2), /* MX35_PAD_ATA_DATA7__CAN1_RXCAN */
+	[746] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 2, 0x0, 0), /* MX35_PAD_ATA_DATA7__UART1_DSR */
+	[747] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 3, 0x7b0, 0), /* MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD */
+	[748] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 5, 0x898, 1), /* MX35_PAD_ATA_DATA7__GPIO2_20 */
+	[749] = IMX_PIN_REG(MX35_PAD_ATA_DATA7, 0x6fc, 0x298, 6, 0x0, 0), /* MX35_PAD_ATA_DATA7__IPU_DIAGB_14 */
+	[750] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 0, 0x0, 0), /* MX35_PAD_ATA_DATA8__ATA_DATA_8 */
+	[751] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 1, 0x99c, 1), /* MX35_PAD_ATA_DATA8__UART3_RTS */
+	[752] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 2, 0x0, 0), /* MX35_PAD_ATA_DATA8__UART1_RI */
+	[753] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 3, 0x7c0, 0), /* MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC */
+	[754] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 5, 0x89c, 1), /* MX35_PAD_ATA_DATA8__GPIO2_21 */
+	[755] = IMX_PIN_REG(MX35_PAD_ATA_DATA8, 0x700, 0x29c, 6, 0x0, 0), /* MX35_PAD_ATA_DATA8__IPU_DIAGB_15 */
+	[756] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA9__ATA_DATA_9 */
+	[757] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 1, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART3_CTS */
+	[758] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 2, 0x0, 0), /* MX35_PAD_ATA_DATA9__UART1_DCD */
+	[759] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 3, 0x7c4, 0), /* MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS */
+	[760] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 5, 0x8a0, 1), /* MX35_PAD_ATA_DATA9__GPIO2_22 */
+	[761] = IMX_PIN_REG(MX35_PAD_ATA_DATA9, 0x704, 0x2a0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA9__IPU_DIAGB_16 */
+	[762] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA10__ATA_DATA_10 */
+	[763] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 1, 0x9a0, 2), /* MX35_PAD_ATA_DATA10__UART3_RXD_MUX */
+	[764] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 3, 0x7b8, 0), /* MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC */
+	[765] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 5, 0x8a4, 1), /* MX35_PAD_ATA_DATA10__GPIO2_23 */
+	[766] = IMX_PIN_REG(MX35_PAD_ATA_DATA10, 0x708, 0x2a4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA10__IPU_DIAGB_17 */
+	[767] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA11__ATA_DATA_11 */
+	[768] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 1, 0x0, 0), /* MX35_PAD_ATA_DATA11__UART3_TXD_MUX */
+	[769] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 3, 0x7bc, 0), /* MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS */
+	[770] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 5, 0x8a8, 1), /* MX35_PAD_ATA_DATA11__GPIO2_24 */
+	[771] = IMX_PIN_REG(MX35_PAD_ATA_DATA11, 0x70c, 0x2a8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA11__IPU_DIAGB_18 */
+	[772] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 0, 0x0, 0), /* MX35_PAD_ATA_DATA12__ATA_DATA_12 */
+	[773] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 1, 0x91c, 3), /* MX35_PAD_ATA_DATA12__I2C3_SCL */
+	[774] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 5, 0x8ac, 1), /* MX35_PAD_ATA_DATA12__GPIO2_25 */
+	[775] = IMX_PIN_REG(MX35_PAD_ATA_DATA12, 0x710, 0x2ac, 6, 0x0, 0), /* MX35_PAD_ATA_DATA12__IPU_DIAGB_19 */
+	[776] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 0, 0x0, 0), /* MX35_PAD_ATA_DATA13__ATA_DATA_13 */
+	[777] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 1, 0x920, 3), /* MX35_PAD_ATA_DATA13__I2C3_SDA */
+	[778] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 5, 0x8b0, 1), /* MX35_PAD_ATA_DATA13__GPIO2_26 */
+	[779] = IMX_PIN_REG(MX35_PAD_ATA_DATA13, 0x714, 0x2b0, 6, 0x0, 0), /* MX35_PAD_ATA_DATA13__IPU_DIAGB_20 */
+	[780] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 0, 0x0, 0), /* MX35_PAD_ATA_DATA14__ATA_DATA_14 */
+	[781] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 1, 0x930, 2), /* MX35_PAD_ATA_DATA14__IPU_CSI_D_0 */
+	[782] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 3, 0x970, 2), /* MX35_PAD_ATA_DATA14__KPP_ROW_0 */
+	[783] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 5, 0x8b4, 1), /* MX35_PAD_ATA_DATA14__GPIO2_27 */
+	[784] = IMX_PIN_REG(MX35_PAD_ATA_DATA14, 0x718, 0x2b4, 6, 0x0, 0), /* MX35_PAD_ATA_DATA14__IPU_DIAGB_21 */
+	[785] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 0, 0x0, 0), /* MX35_PAD_ATA_DATA15__ATA_DATA_15 */
+	[786] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 1, 0x934, 2), /* MX35_PAD_ATA_DATA15__IPU_CSI_D_1 */
+	[787] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 3, 0x974, 2), /* MX35_PAD_ATA_DATA15__KPP_ROW_1 */
+	[788] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 5, 0x8b8, 1), /* MX35_PAD_ATA_DATA15__GPIO2_28 */
+	[789] = IMX_PIN_REG(MX35_PAD_ATA_DATA15, 0x71c, 0x2b8, 6, 0x0, 0), /* MX35_PAD_ATA_DATA15__IPU_DIAGB_22 */
+	[790] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 0, 0x0, 0), /* MX35_PAD_ATA_INTRQ__ATA_INTRQ */
+	[791] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 1, 0x938, 3), /* MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 */
+	[792] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 3, 0x978, 2), /* MX35_PAD_ATA_INTRQ__KPP_ROW_2 */
+	[793] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 5, 0x8bc, 1), /* MX35_PAD_ATA_INTRQ__GPIO2_29 */
+	[794] = IMX_PIN_REG(MX35_PAD_ATA_INTRQ, 0x720, 0x2bc, 6, 0x0, 0), /* MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 */
+	[795] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 0, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN */
+	[796] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 1, 0x93c, 3), /* MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 */
+	[797] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 3, 0x97c, 2), /* MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 */
+	[798] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 5, 0x8c4, 1), /* MX35_PAD_ATA_BUFF_EN__GPIO2_30 */
+	[799] = IMX_PIN_REG(MX35_PAD_ATA_BUFF_EN, 0x724, 0x2c0, 6, 0x0, 0), /* MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 */
+	[800] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 0, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ATA_DMARQ */
+	[801] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 1, 0x940, 2), /* MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 */
+	[802] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 3, 0x950, 2), /* MX35_PAD_ATA_DMARQ__KPP_COL_0 */
+	[803] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 5, 0x8c8, 1), /* MX35_PAD_ATA_DMARQ__GPIO2_31 */
+	[804] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 6, 0x0, 0), /* MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 */
+	[805] = IMX_PIN_REG(MX35_PAD_ATA_DMARQ, 0x728, 0x2c4, 7, 0x0, 0), /* MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 */
+	[806] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 0, 0x0, 0), /* MX35_PAD_ATA_DA0__ATA_DA_0 */
+	[807] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 1, 0x944, 2), /* MX35_PAD_ATA_DA0__IPU_CSI_D_5 */
+	[808] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 3, 0x954, 2), /* MX35_PAD_ATA_DA0__KPP_COL_1 */
+	[809] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 5, 0x8e8, 1), /* MX35_PAD_ATA_DA0__GPIO3_0 */
+	[810] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 6, 0x0, 0), /* MX35_PAD_ATA_DA0__IPU_DIAGB_26 */
+	[811] = IMX_PIN_REG(MX35_PAD_ATA_DA0, 0x72c, 0x2c8, 7, 0x0, 0), /* MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 */
+	[812] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 0, 0x0, 0), /* MX35_PAD_ATA_DA1__ATA_DA_1 */
+	[813] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 1, 0x948, 2), /* MX35_PAD_ATA_DA1__IPU_CSI_D_6 */
+	[814] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 3, 0x958, 2), /* MX35_PAD_ATA_DA1__KPP_COL_2 */
+	[815] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 5, 0x0, 0), /* MX35_PAD_ATA_DA1__GPIO3_1 */
+	[816] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 6, 0x0, 0), /* MX35_PAD_ATA_DA1__IPU_DIAGB_27 */
+	[817] = IMX_PIN_REG(MX35_PAD_ATA_DA1, 0x730, 0x2cc, 7, 0x0, 0), /* MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 */
+	[818] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 0, 0x0, 0), /* MX35_PAD_ATA_DA2__ATA_DA_2 */
+	[819] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 1, 0x94c, 2), /* MX35_PAD_ATA_DA2__IPU_CSI_D_7 */
+	[820] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 3, 0x95c, 2), /* MX35_PAD_ATA_DA2__KPP_COL_3 */
+	[821] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 5, 0x0, 0), /* MX35_PAD_ATA_DA2__GPIO3_2 */
+	[822] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 6, 0x0, 0), /* MX35_PAD_ATA_DA2__IPU_DIAGB_28 */
+	[823] = IMX_PIN_REG(MX35_PAD_ATA_DA2, 0x734, 0x2d0, 7, 0x0, 0), /* MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 */
+	[824] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 0, 0x0, 0), /* MX35_PAD_MLB_CLK__MLB_MLBCLK */
+	[825] = IMX_PIN_REG(MX35_PAD_MLB_CLK, 0x738, 0x2d4, 5, 0x0, 0), /* MX35_PAD_MLB_CLK__GPIO3_3 */
+	[826] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 0, 0x0, 0), /* MX35_PAD_MLB_DAT__MLB_MLBDAT */
+	[827] = IMX_PIN_REG(MX35_PAD_MLB_DAT, 0x73c, 0x2d8, 5, 0x904, 1), /* MX35_PAD_MLB_DAT__GPIO3_4 */
+	[828] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 0, 0x0, 0), /* MX35_PAD_MLB_SIG__MLB_MLBSIG */
+	[829] = IMX_PIN_REG(MX35_PAD_MLB_SIG, 0x740, 0x2dc, 5, 0x908, 1), /* MX35_PAD_MLB_SIG__GPIO3_5 */
+	[830] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 0, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__FEC_TX_CLK */
+	[831] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 1, 0x804, 1), /* MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 */
+	[832] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 2, 0x9a0, 3), /* MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX */
+	[833] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 3, 0x9ec, 1), /* MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR */
+	[834] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 4, 0x7ec, 3), /* MX35_PAD_FEC_TX_CLK__CSPI2_MOSI */
+	[835] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 5, 0x90c, 1), /* MX35_PAD_FEC_TX_CLK__GPIO3_6 */
+	[836] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 6, 0x928, 5), /* MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC */
+	[837] = IMX_PIN_REG(MX35_PAD_FEC_TX_CLK, 0x744, 0x2e0, 7, 0x0, 0), /* MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 */
+	[838] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 0, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__FEC_RX_CLK */
+	[839] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 1, 0x808, 1), /* MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 */
+	[840] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 2, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX */
+	[841] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 3, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP */
+	[842] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 4, 0x7e8, 3), /* MX35_PAD_FEC_RX_CLK__CSPI2_MISO */
+	[843] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 5, 0x910, 1), /* MX35_PAD_FEC_RX_CLK__GPIO3_7 */
+	[844] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 6, 0x92c, 4), /* MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I */
+	[845] = IMX_PIN_REG(MX35_PAD_FEC_RX_CLK, 0x748, 0x2e4, 7, 0x0, 0), /* MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 */
+	[846] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 0, 0x0, 0), /* MX35_PAD_FEC_RX_DV__FEC_RX_DV */
+	[847] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 1, 0x80c, 1), /* MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 */
+	[848] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 2, 0x99c, 2), /* MX35_PAD_FEC_RX_DV__UART3_RTS */
+	[849] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 3, 0x9f0, 1), /* MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT */
+	[850] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 4, 0x7e0, 3), /* MX35_PAD_FEC_RX_DV__CSPI2_SCLK */
+	[851] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 5, 0x914, 1), /* MX35_PAD_FEC_RX_DV__GPIO3_8 */
+	[852] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 6, 0x0, 0), /* MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK */
+	[853] = IMX_PIN_REG(MX35_PAD_FEC_RX_DV, 0x74c, 0x2e8, 7, 0x0, 0), /* MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 */
+	[854] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 0, 0x0, 0), /* MX35_PAD_FEC_COL__FEC_COL */
+	[855] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 1, 0x810, 1), /* MX35_PAD_FEC_COL__ESDHC1_DAT7 */
+	[856] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 2, 0x0, 0), /* MX35_PAD_FEC_COL__UART3_CTS */
+	[857] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 3, 0x9cc, 1), /* MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 */
+	[858] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 4, 0x7e4, 3), /* MX35_PAD_FEC_COL__CSPI2_RDY */
+	[859] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 5, 0x918, 1), /* MX35_PAD_FEC_COL__GPIO3_9 */
+	[860] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 6, 0x0, 0), /* MX35_PAD_FEC_COL__IPU_DISPB_SER_RS */
+	[861] = IMX_PIN_REG(MX35_PAD_FEC_COL, 0x750, 0x2ec, 7, 0x0, 0), /* MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 */
+	[862] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA0__FEC_RDATA_0 */
+	[863] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 1, 0x0, 0), /* MX35_PAD_FEC_RDATA0__PWM_PWMO */
+	[864] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA0__UART3_DTR */
+	[865] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 3, 0x9d0, 1), /* MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 */
+	[866] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 4, 0x7f0, 2), /* MX35_PAD_FEC_RDATA0__CSPI2_SS0 */
+	[867] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 5, 0x8ec, 1), /* MX35_PAD_FEC_RDATA0__GPIO3_10 */
+	[868] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 */
+	[869] = IMX_PIN_REG(MX35_PAD_FEC_RDATA0, 0x754, 0x2f0, 7, 0x0, 0), /* MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 */
+	[870] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA0__FEC_TDATA_0 */
+	[871] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 1, 0x0, 0), /* MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 */
+	[872] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 2, 0x0, 0), /* MX35_PAD_FEC_TDATA0__UART3_DSR */
+	[873] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 3, 0x9d4, 1), /* MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 */
+	[874] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 4, 0x7f4, 2), /* MX35_PAD_FEC_TDATA0__CSPI2_SS1 */
+	[875] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 5, 0x8f0, 1), /* MX35_PAD_FEC_TDATA0__GPIO3_11 */
+	[876] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 */
+	[877] = IMX_PIN_REG(MX35_PAD_FEC_TDATA0, 0x758, 0x2f4, 7, 0x0, 0), /* MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 */
+	[878] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 0, 0x0, 0), /* MX35_PAD_FEC_TX_EN__FEC_TX_EN */
+	[879] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 1, 0x998, 3), /* MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 */
+	[880] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 2, 0x0, 0), /* MX35_PAD_FEC_TX_EN__UART3_RI */
+	[881] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 3, 0x9d8, 1), /* MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 */
+	[882] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 5, 0x8f4, 1), /* MX35_PAD_FEC_TX_EN__GPIO3_12 */
+	[883] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 6, 0x0, 0), /* MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS */
+	[884] = IMX_PIN_REG(MX35_PAD_FEC_TX_EN, 0x75c, 0x2f8, 7, 0x0, 0), /* MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 */
+	[885] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 0, 0x0, 0), /* MX35_PAD_FEC_MDC__FEC_MDC */
+	[886] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 1, 0x0, 0), /* MX35_PAD_FEC_MDC__CAN2_TXCAN */
+	[887] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 2, 0x0, 0), /* MX35_PAD_FEC_MDC__UART3_DCD */
+	[888] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 3, 0x9dc, 1), /* MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 */
+	[889] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 5, 0x8f8, 1), /* MX35_PAD_FEC_MDC__GPIO3_13 */
+	[890] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 6, 0x0, 0), /* MX35_PAD_FEC_MDC__IPU_DISPB_WR */
+	[891] = IMX_PIN_REG(MX35_PAD_FEC_MDC, 0x760, 0x2fc, 7, 0x0, 0), /* MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 */
+	[892] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 0, 0x0, 0), /* MX35_PAD_FEC_MDIO__FEC_MDIO */
+	[893] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 1, 0x7cc, 2), /* MX35_PAD_FEC_MDIO__CAN2_RXCAN */
+	[894] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 3, 0x9e0, 1), /* MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 */
+	[895] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 5, 0x8fc, 1), /* MX35_PAD_FEC_MDIO__GPIO3_14 */
+	[896] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 6, 0x0, 0), /* MX35_PAD_FEC_MDIO__IPU_DISPB_RD */
+	[897] = IMX_PIN_REG(MX35_PAD_FEC_MDIO, 0x764, 0x300, 7, 0x0, 0), /* MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 */
+	[898] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 0, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__FEC_TX_ERR */
+	[899] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 1, 0x990, 2), /* MX35_PAD_FEC_TX_ERR__OWIRE_LINE */
+	[900] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 2, 0x994, 4), /* MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK */
+	[901] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 3, 0x9e4, 1), /* MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 */
+	[902] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 5, 0x900, 1), /* MX35_PAD_FEC_TX_ERR__GPIO3_15 */
+	[903] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 6, 0x924, 3), /* MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC */
+	[904] = IMX_PIN_REG(MX35_PAD_FEC_TX_ERR, 0x768, 0x304, 7, 0x0, 0), /* MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 */
+	[905] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 0, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__FEC_RX_ERR */
+	[906] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 1, 0x930, 3), /* MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 */
+	[907] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 3, 0x9e8, 1), /* MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 */
+	[908] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 4, 0x960, 1), /* MX35_PAD_FEC_RX_ERR__KPP_COL_4 */
+	[909] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 5, 0x0, 0), /* MX35_PAD_FEC_RX_ERR__GPIO3_16 */
+	[910] = IMX_PIN_REG(MX35_PAD_FEC_RX_ERR, 0x76c, 0x308, 6, 0x92c, 5), /* MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO */
+	[911] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 0, 0x0, 0), /* MX35_PAD_FEC_CRS__FEC_CRS */
+	[912] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 1, 0x934, 3), /* MX35_PAD_FEC_CRS__IPU_CSI_D_1 */
+	[913] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 3, 0x0, 0), /* MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR */
+	[914] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 4, 0x964, 1), /* MX35_PAD_FEC_CRS__KPP_COL_5 */
+	[915] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 5, 0x0, 0), /* MX35_PAD_FEC_CRS__GPIO3_17 */
+	[916] = IMX_PIN_REG(MX35_PAD_FEC_CRS, 0x770, 0x30c, 6, 0x0, 0), /* MX35_PAD_FEC_CRS__IPU_FLASH_STROBE */
+	[917] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA1__FEC_RDATA_1 */
+	[918] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 1, 0x938, 4), /* MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 */
+	[919] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 2, 0x0, 0), /* MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC */
+	[920] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 3, 0x9f4, 2), /* MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC */
+	[921] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 4, 0x968, 1), /* MX35_PAD_FEC_RDATA1__KPP_COL_6 */
+	[922] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA1__GPIO3_18 */
+	[923] = IMX_PIN_REG(MX35_PAD_FEC_RDATA1, 0x774, 0x310, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 */
+	[924] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA1__FEC_TDATA_1 */
+	[925] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 1, 0x93c, 4), /* MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 */
+	[926] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 2, 0x7bc, 1), /* MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS */
+	[927] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 4, 0x96c, 1), /* MX35_PAD_FEC_TDATA1__KPP_COL_7 */
+	[928] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA1__GPIO3_19 */
+	[929] = IMX_PIN_REG(MX35_PAD_FEC_TDATA1, 0x778, 0x314, 6, 0x0, 0), /* MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 */
+	[930] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA2__FEC_RDATA_2 */
+	[931] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 1, 0x940, 3), /* MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 */
+	[932] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 2, 0x7b4, 1), /* MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD */
+	[933] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 4, 0x980, 1), /* MX35_PAD_FEC_RDATA2__KPP_ROW_4 */
+	[934] = IMX_PIN_REG(MX35_PAD_FEC_RDATA2, 0x77c, 0x318, 5, 0x0, 0), /* MX35_PAD_FEC_RDATA2__GPIO3_20 */
+	[935] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA2__FEC_TDATA_2 */
+	[936] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 1, 0x944, 3), /* MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 */
+	[937] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 2, 0x7b0, 1), /* MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD */
+	[938] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 4, 0x984, 1), /* MX35_PAD_FEC_TDATA2__KPP_ROW_5 */
+	[939] = IMX_PIN_REG(MX35_PAD_FEC_TDATA2, 0x780, 0x31c, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA2__GPIO3_21 */
+	[940] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 0, 0x0, 0), /* MX35_PAD_FEC_RDATA3__FEC_RDATA_3 */
+	[941] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 1, 0x948, 3), /* MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 */
+	[942] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 2, 0x7c0, 1), /* MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC */
+	[943] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 4, 0x988, 1), /* MX35_PAD_FEC_RDATA3__KPP_ROW_6 */
+	[944] = IMX_PIN_REG(MX35_PAD_FEC_RDATA3, 0x784, 0x320, 6, 0x0, 0), /* MX35_PAD_FEC_RDATA3__GPIO3_22 */
+	[945] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 0, 0x0, 0), /* MX35_PAD_FEC_TDATA3__FEC_TDATA_3 */
+	[946] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 1, 0x94c, 3), /* MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 */
+	[947] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 2, 0x7c4, 1), /* MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS */
+	[948] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 4, 0x98c, 1), /* MX35_PAD_FEC_TDATA3__KPP_ROW_7 */
+	[949] = IMX_PIN_REG(MX35_PAD_FEC_TDATA3, 0x788, 0x324, 5, 0x0, 0), /* MX35_PAD_FEC_TDATA3__GPIO3_23 */
+	[950] = IMX_PIN_REG(MX35_PAD_EXT_ARMCLK, 0x78c, 0x0, 0, 0x0, 0), /* MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK */
+	[951] = IMX_PIN_REG(MX35_PAD_TEST_MODE, 0x790, 0x0, 0, 0x0, 0), /* MX35_PAD_TEST_MODE__TCU_TEST_MODE */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
+	IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
+	IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
+	IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
+	IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
+	IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
+	IMX_PINCTRL_PIN(MX35_PAD_POR_B),
+	IMX_PINCTRL_PIN(MX35_PAD_CLKO),
+	IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
+	IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
+	IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
+	IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
+	IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
+	IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
+	IMX_PINCTRL_PIN(MX35_PAD_A0),
+	IMX_PINCTRL_PIN(MX35_PAD_A1),
+	IMX_PINCTRL_PIN(MX35_PAD_A2),
+	IMX_PINCTRL_PIN(MX35_PAD_A3),
+	IMX_PINCTRL_PIN(MX35_PAD_A4),
+	IMX_PINCTRL_PIN(MX35_PAD_A5),
+	IMX_PINCTRL_PIN(MX35_PAD_A6),
+	IMX_PINCTRL_PIN(MX35_PAD_A7),
+	IMX_PINCTRL_PIN(MX35_PAD_A8),
+	IMX_PINCTRL_PIN(MX35_PAD_A9),
+	IMX_PINCTRL_PIN(MX35_PAD_A10),
+	IMX_PINCTRL_PIN(MX35_PAD_MA10),
+	IMX_PINCTRL_PIN(MX35_PAD_A11),
+	IMX_PINCTRL_PIN(MX35_PAD_A12),
+	IMX_PINCTRL_PIN(MX35_PAD_A13),
+	IMX_PINCTRL_PIN(MX35_PAD_A14),
+	IMX_PINCTRL_PIN(MX35_PAD_A15),
+	IMX_PINCTRL_PIN(MX35_PAD_A16),
+	IMX_PINCTRL_PIN(MX35_PAD_A17),
+	IMX_PINCTRL_PIN(MX35_PAD_A18),
+	IMX_PINCTRL_PIN(MX35_PAD_A19),
+	IMX_PINCTRL_PIN(MX35_PAD_A20),
+	IMX_PINCTRL_PIN(MX35_PAD_A21),
+	IMX_PINCTRL_PIN(MX35_PAD_A22),
+	IMX_PINCTRL_PIN(MX35_PAD_A23),
+	IMX_PINCTRL_PIN(MX35_PAD_A24),
+	IMX_PINCTRL_PIN(MX35_PAD_A25),
+	IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD3),
+	IMX_PINCTRL_PIN(MX35_PAD_SD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SD6),
+	IMX_PINCTRL_PIN(MX35_PAD_SD7),
+	IMX_PINCTRL_PIN(MX35_PAD_SD8),
+	IMX_PINCTRL_PIN(MX35_PAD_SD9),
+	IMX_PINCTRL_PIN(MX35_PAD_SD10),
+	IMX_PINCTRL_PIN(MX35_PAD_SD11),
+	IMX_PINCTRL_PIN(MX35_PAD_SD12),
+	IMX_PINCTRL_PIN(MX35_PAD_SD13),
+	IMX_PINCTRL_PIN(MX35_PAD_SD14),
+	IMX_PINCTRL_PIN(MX35_PAD_SD15),
+	IMX_PINCTRL_PIN(MX35_PAD_SD16),
+	IMX_PINCTRL_PIN(MX35_PAD_SD17),
+	IMX_PINCTRL_PIN(MX35_PAD_SD18),
+	IMX_PINCTRL_PIN(MX35_PAD_SD19),
+	IMX_PINCTRL_PIN(MX35_PAD_SD20),
+	IMX_PINCTRL_PIN(MX35_PAD_SD21),
+	IMX_PINCTRL_PIN(MX35_PAD_SD22),
+	IMX_PINCTRL_PIN(MX35_PAD_SD23),
+	IMX_PINCTRL_PIN(MX35_PAD_SD24),
+	IMX_PINCTRL_PIN(MX35_PAD_SD25),
+	IMX_PINCTRL_PIN(MX35_PAD_SD26),
+	IMX_PINCTRL_PIN(MX35_PAD_SD27),
+	IMX_PINCTRL_PIN(MX35_PAD_SD28),
+	IMX_PINCTRL_PIN(MX35_PAD_SD29),
+	IMX_PINCTRL_PIN(MX35_PAD_SD30),
+	IMX_PINCTRL_PIN(MX35_PAD_SD31),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM0),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM1),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM2),
+	IMX_PINCTRL_PIN(MX35_PAD_DQM3),
+	IMX_PINCTRL_PIN(MX35_PAD_EB0),
+	IMX_PINCTRL_PIN(MX35_PAD_EB1),
+	IMX_PINCTRL_PIN(MX35_PAD_OE),
+	IMX_PINCTRL_PIN(MX35_PAD_CS0),
+	IMX_PINCTRL_PIN(MX35_PAD_CS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CS2),
+	IMX_PINCTRL_PIN(MX35_PAD_CS3),
+	IMX_PINCTRL_PIN(MX35_PAD_CS4),
+	IMX_PINCTRL_PIN(MX35_PAD_CS5),
+	IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
+	IMX_PINCTRL_PIN(MX35_PAD_ECB),
+	IMX_PINCTRL_PIN(MX35_PAD_LBA),
+	IMX_PINCTRL_PIN(MX35_PAD_BCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_RW),
+	IMX_PINCTRL_PIN(MX35_PAD_RAS),
+	IMX_PINCTRL_PIN(MX35_PAD_CAS),
+	IMX_PINCTRL_PIN(MX35_PAD_SDWE),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
+	IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
+	IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFALE),
+	IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
+	IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
+	IMX_PINCTRL_PIN(MX35_PAD_NFRB),
+	IMX_PINCTRL_PIN(MX35_PAD_D15),
+	IMX_PINCTRL_PIN(MX35_PAD_D14),
+	IMX_PINCTRL_PIN(MX35_PAD_D13),
+	IMX_PINCTRL_PIN(MX35_PAD_D12),
+	IMX_PINCTRL_PIN(MX35_PAD_D11),
+	IMX_PINCTRL_PIN(MX35_PAD_D10),
+	IMX_PINCTRL_PIN(MX35_PAD_D9),
+	IMX_PINCTRL_PIN(MX35_PAD_D8),
+	IMX_PINCTRL_PIN(MX35_PAD_D7),
+	IMX_PINCTRL_PIN(MX35_PAD_D6),
+	IMX_PINCTRL_PIN(MX35_PAD_D5),
+	IMX_PINCTRL_PIN(MX35_PAD_D4),
+	IMX_PINCTRL_PIN(MX35_PAD_D3),
+	IMX_PINCTRL_PIN(MX35_PAD_D2),
+	IMX_PINCTRL_PIN(MX35_PAD_D1),
+	IMX_PINCTRL_PIN(MX35_PAD_D0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_STXD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
+	IMX_PINCTRL_PIN(MX35_PAD_SCK4),
+	IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
+	IMX_PINCTRL_PIN(MX35_PAD_STXD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
+	IMX_PINCTRL_PIN(MX35_PAD_SCK5),
+	IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
+	IMX_PINCTRL_PIN(MX35_PAD_SCKR),
+	IMX_PINCTRL_PIN(MX35_PAD_FSR),
+	IMX_PINCTRL_PIN(MX35_PAD_HCKR),
+	IMX_PINCTRL_PIN(MX35_PAD_SCKT),
+	IMX_PINCTRL_PIN(MX35_PAD_FST),
+	IMX_PINCTRL_PIN(MX35_PAD_HCKT),
+	IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
+	IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
+	IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
+	IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
+	IMX_PINCTRL_PIN(MX35_PAD_TX1),
+	IMX_PINCTRL_PIN(MX35_PAD_TX0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
+	IMX_PINCTRL_PIN(MX35_PAD_RXD1),
+	IMX_PINCTRL_PIN(MX35_PAD_TXD1),
+	IMX_PINCTRL_PIN(MX35_PAD_RTS1),
+	IMX_PINCTRL_PIN(MX35_PAD_CTS1),
+	IMX_PINCTRL_PIN(MX35_PAD_RXD2),
+	IMX_PINCTRL_PIN(MX35_PAD_TXD2),
+	IMX_PINCTRL_PIN(MX35_PAD_RTS2),
+	IMX_PINCTRL_PIN(MX35_PAD_CTS2),
+	IMX_PINCTRL_PIN(MX35_PAD_RTCK),
+	IMX_PINCTRL_PIN(MX35_PAD_TCK),
+	IMX_PINCTRL_PIN(MX35_PAD_TMS),
+	IMX_PINCTRL_PIN(MX35_PAD_TDI),
+	IMX_PINCTRL_PIN(MX35_PAD_TDO),
+	IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
+	IMX_PINCTRL_PIN(MX35_PAD_DE_B),
+	IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
+	IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
+	IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
+	IMX_PINCTRL_PIN(MX35_PAD_LD0),
+	IMX_PINCTRL_PIN(MX35_PAD_LD1),
+	IMX_PINCTRL_PIN(MX35_PAD_LD2),
+	IMX_PINCTRL_PIN(MX35_PAD_LD3),
+	IMX_PINCTRL_PIN(MX35_PAD_LD4),
+	IMX_PINCTRL_PIN(MX35_PAD_LD5),
+	IMX_PINCTRL_PIN(MX35_PAD_LD6),
+	IMX_PINCTRL_PIN(MX35_PAD_LD7),
+	IMX_PINCTRL_PIN(MX35_PAD_LD8),
+	IMX_PINCTRL_PIN(MX35_PAD_LD9),
+	IMX_PINCTRL_PIN(MX35_PAD_LD10),
+	IMX_PINCTRL_PIN(MX35_PAD_LD11),
+	IMX_PINCTRL_PIN(MX35_PAD_LD12),
+	IMX_PINCTRL_PIN(MX35_PAD_LD13),
+	IMX_PINCTRL_PIN(MX35_PAD_LD14),
+	IMX_PINCTRL_PIN(MX35_PAD_LD15),
+	IMX_PINCTRL_PIN(MX35_PAD_LD16),
+	IMX_PINCTRL_PIN(MX35_PAD_LD17),
+	IMX_PINCTRL_PIN(MX35_PAD_LD18),
+	IMX_PINCTRL_PIN(MX35_PAD_LD19),
+	IMX_PINCTRL_PIN(MX35_PAD_LD20),
+	IMX_PINCTRL_PIN(MX35_PAD_LD21),
+	IMX_PINCTRL_PIN(MX35_PAD_LD22),
+	IMX_PINCTRL_PIN(MX35_PAD_LD23),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
+	IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
+	IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
+	IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
+	IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
+	IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
+	IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
+};
+
+static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+	.pins = imx35_pinctrl_pads,
+	.npins = ARRAY_SIZE(imx35_pinctrl_pads),
+	.pin_regs = imx35_pin_regs,
+	.npin_regs = ARRAY_SIZE(imx35_pin_regs),
+};
+
+static struct of_device_id imx35_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "fsl,imx35-iomuxc", },
+	{ /* sentinel */ }
+};
+
+static int __devinit imx35_pinctrl_probe(struct platform_device *pdev)
+{
+	return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
+}
+
+static struct platform_driver imx35_pinctrl_driver = {
+	.driver = {
+		.name = "imx35-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(imx35_pinctrl_of_match),
+	},
+	.probe = imx35_pinctrl_probe,
+	.remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx35_pinctrl_init(void)
+{
+	return platform_driver_register(&imx35_pinctrl_driver);
+}
+arch_initcall(imx35_pinctrl_init);
+
+static void __exit imx35_pinctrl_exit(void)
+{
+	platform_driver_unregister(&imx35_pinctrl_driver);
+}
+module_exit(imx35_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng at linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.10.4



From alanbutty12 at gmail.com  Fri Aug 10 08:46:28 2012
From: alanbutty12 at gmail.com (alan butler)
Date: Fri, 10 Aug 2012 12:46:28 -0000
Subject: DTS support for the Iomega ix2-200
Message-ID: <CADhrpJ4p4U2f6uj+uDQg0f0yGaOodAyBTLhBJQeWKCn-vSkY3w@mail.gmail.com>

I am currently working on a dts for the iomega ix2-200 and have run into a
bit of a wall
and was wondering if i could get help here and as i am new here i am unsure
how to
start one of these threads and what information is required.

I have created a dts file and a board config and made the appropriate
changes to build
the support into the kernel but when i try to boot the kernel it just stops
at the following
line:

turn off boot console earlycon0

please let me know what other information is required to help me get this
working.

thank you
-------------- next part --------------
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From arnd at arndb.de  Fri Aug 10 15:06:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 19:06:35 -0000
Subject: [GIT PULL 2/3] arm-soc: late at91 changes
In-Reply-To: <1344625575-27560-1-git-send-email-arnd@arndb.de>
References: <1344625575-27560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344625575-27560-3-git-send-email-arnd@arndb.de>

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/late-at91-mci

for you to fetch changes up to b3ce167791c02da98f6e527be7d19213b3abddf0:

  Merge tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91 into at91/mci (2012-08-10 12:34:18 +0200)

----------------------------------------------------------------

arm-soc: late at91 changes

This series was originally sent for inclusion in v3.5 but missed out
twice, first time because it was late for v3.5 and we decided not to
push it then, and this time because the maintainer was on a long
vacation before the merge window and nobody noticed that it was missing
from the v3.6 list.

The main purpose of this series is to move over the at91 board files
to use the atmel-mci driver instead of the old at91_mci that is
scheduled for removal in v3.7.

Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Ludovic Desroches <ludovic.desroches at atmel.com>
----------------------------------------------------------------
Arnd Bergmann (1):
      Merge tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91 into at91/mci

Ludovic Desroches (1):
      ARM: at91: add atmel-mci support for chips and boards which can use it

Nicolas Ferre (1):
      ARM: at91/defconfig: change the MCI driver to use in defconfigs

Paul Bolle (1):
      ARM: at91: set i2c_board_info.type to "ds1339" directly

Richard Genoud (1):
      ARM: at91/defconfig: Remove unaffected config option

 arch/arm/configs/afeb9260_defconfig      |    1 -
 arch/arm/configs/at91rm9200_defconfig    |    2 +-
 arch/arm/configs/at91sam9261_defconfig   |    2 +-
 arch/arm/configs/at91sam9263_defconfig   |    3 +-
 arch/arm/configs/at91sam9g20_defconfig   |    2 +-
 arch/arm/configs/at91sam9rl_defconfig    |    2 +-
 arch/arm/configs/cpu9260_defconfig       |    2 +-
 arch/arm/configs/cpu9g20_defconfig       |    2 +-
 arch/arm/configs/qil-a9260_defconfig     |    3 +-
 arch/arm/configs/stamp9g20_defconfig     |    1 -
 arch/arm/configs/usb-a9260_defconfig     |    1 -
 arch/arm/mach-at91/at91rm9200_devices.c  |   92 ++++++++++-------
 arch/arm/mach-at91/at91sam9260_devices.c |   84 +---------------
 arch/arm/mach-at91/at91sam9261_devices.c |   60 +++++------
 arch/arm/mach-at91/at91sam9263.c         |    4 +-
 arch/arm/mach-at91/at91sam9263_devices.c |  161 +++++++++++++++++-------------
 arch/arm/mach-at91/at91sam9rl_devices.c  |   60 +++++------
 arch/arm/mach-at91/board-afeb-9260v1.c   |   14 +--
 arch/arm/mach-at91/board-carmeva.c       |   14 +--
 arch/arm/mach-at91/board-cpu9krea.c      |   17 ++--
 arch/arm/mach-at91/board-cpuat91.c       |   13 +--
 arch/arm/mach-at91/board-csb337.c        |   14 +--
 arch/arm/mach-at91/board-eb9200.c        |   14 +--
 arch/arm/mach-at91/board-ecbat91.c       |   14 +--
 arch/arm/mach-at91/board-eco920.c        |   14 +--
 arch/arm/mach-at91/board-flexibity.c     |   14 +--
 arch/arm/mach-at91/board-foxg20.c        |   16 +--
 arch/arm/mach-at91/board-kb9202.c        |   14 +--
 arch/arm/mach-at91/board-neocore926.c    |   13 +--
 arch/arm/mach-at91/board-picotux200.c    |   14 +--
 arch/arm/mach-at91/board-qil-a9260.c     |   14 +--
 arch/arm/mach-at91/board-rm9200dk.c      |   14 +--
 arch/arm/mach-at91/board-rm9200ek.c      |   14 +--
 arch/arm/mach-at91/board-rsi-ews.c       |   13 +--
 arch/arm/mach-at91/board-sam9-l9260.c    |   16 +--
 arch/arm/mach-at91/board-sam9260ek.c     |   16 +--
 arch/arm/mach-at91/board-sam9261ek.c     |   13 +--
 arch/arm/mach-at91/board-sam9263ek.c     |   13 +--
 arch/arm/mach-at91/board-sam9g20ek.c     |   16 +--
 arch/arm/mach-at91/board-sam9rlek.c      |   13 +--
 arch/arm/mach-at91/board-stamp9g20.c     |   14 ---
 arch/arm/mach-at91/board-usb-a926x.c     |    2 -
 arch/arm/mach-at91/board-yl-9200.c       |   13 +--
 drivers/mtd/nand/Kconfig                 |   40 --------
 44 files changed, 384 insertions(+), 494 deletions(-)


From arnd at arndb.de  Fri Aug 10 15:06:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 19:06:36 -0000
Subject: [GIT PULL 1/3] arm-soc: bug fixes for v3.6-rc2
In-Reply-To: <1344625575-27560-1-git-send-email-arnd@arndb.de>
References: <1344625575-27560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344625575-27560-2-git-send-email-arnd@arndb.de>

The following changes since commit 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee:

  Linux 3.6-rc1 (2012-08-02 16:38:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-for-linus

for you to fetch changes up to de9234306bb28fe6c8c3bb908e3f9956f5276a02:

  ARM: davinci: remove broken ntosd2_init_i2c (2012-08-10 13:14:36 +0200)

----------------------------------------------------------------
arm-soc: bug fixes for v3.6-rc2

These are a bunch of bug fixes that came in after the merge window and
one update for the MAINTAINERS file. The largest part of the fixes
are patches that address bugs found by building all the ARM defconfig
files. There are a lot more warnings that we have patches for, but
the others are either still under discussion or are harmless and
do not cause actual problems besides making the build slightly noisy.

----------------------------------------------------------------
Arnd Bergmann (19):
      Merge branch 'imx/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
      Merge branch 'mxs/fixes-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
      Merge tag 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes
      mfd/asic3: fix asic3_mfd_probe return value
      usb/ohci-omap: remove unused variable
      ARM: pxa: remove irq_to_gpio from ezx-pcap driver
      Input: eeti_ts: pass gpio value instead of IRQ
      ARM: sa1100: include linux/io.h in hackkit leds code
      ARM: s3c24xx: use new PWM driver
      ARM: integrator: include <linux/export.h>
      ARM: imx: gpmi-nand depends on mxs-dma
      ARM: exynos: exynos_pm_add_dev_to_genpd may be unused
      gpio: em: do not discard em_gio_irq_domain_cleanup
      mtd/omap2: fix dmaengine_slave_config error handling
      spi/s3c64xx: improve error handling
      omap-rng: fix use of SIMPLE_DEV_PM_OPS
      Merge branch 'testing/new-warnings' into fixes
      ARM: s3c24xx: enable CONFIG_BUG for tct_hammer
      ARM: davinci: remove broken ntosd2_init_i2c

Fabio Estevam (5):
      ARM: dts: imx27-3ds.dts: Fix serial console node
      ARM: imx6q-sabrelite: Setup CLKO IOMUX
      ARM: mx23: Fix registers range
      ARM: mx28: Fix registers range
      ARM: clk-imx31: Fix the keypad clock name

Javier Martin (1):
      i.MX27: Fix emma-prp and csi clocks.

Linus Walleij (2):
      MAINTAINERS: update entry for Linus Walleij
      ARM: integrator: use clk_prepare_enable() for timer

Marc Kleine-Budde (1):
      ARM: mxs: always build ocotp

Marek Vasut (1):
      ARM: mxs: Remove MMAP_MIN_ADDR setting from mxs_defconfig

Sebastian Hesselbarth (1):
      ARM: kirkwood: fix typo in Makefile.boot

Shawn Guo (3):
      ARM: imx: enable emi_slow_gate clock for imx5
      ARM: dts: imx53-ard: add regulators for lan9220
      ARM: dts: imx: fix gpio interrupts property

Stephen Warren (1):
      ARM: tegra: more regulator fixes for Harmony

 MAINTAINERS                               |   17 ++++---
 arch/arm/boot/dts/imx23.dtsi              |   52 ++++++++++----------
 arch/arm/boot/dts/imx27-3ds.dts           |    2 +-
 arch/arm/boot/dts/imx28.dtsi              |   74 ++++++++++++++---------------
 arch/arm/boot/dts/imx51-babbage.dts       |    2 +-
 arch/arm/boot/dts/imx53-ard.dts           |   22 ++++++++-
 arch/arm/boot/dts/imx6q-sabrelite.dts     |    1 +
 arch/arm/configs/imx_v6_v7_defconfig      |    1 +
 arch/arm/configs/mxs_defconfig            |    1 -
 arch/arm/configs/tct_hammer_defconfig     |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c |   39 ---------------
 arch/arm/mach-exynos/pm_domains.c         |    2 +-
 arch/arm/mach-imx/clk-imx27.c             |    8 ++--
 arch/arm/mach-imx/clk-imx31.c             |    2 +-
 arch/arm/mach-imx/clk-imx51-imx53.c       |    1 +
 arch/arm/mach-integrator/core.c           |    1 +
 arch/arm/mach-integrator/integrator_ap.c  |    2 +-
 arch/arm/mach-kirkwood/Makefile.boot      |    4 +-
 arch/arm/mach-mxs/Kconfig                 |    6 ---
 arch/arm/mach-mxs/Makefile                |    3 +-
 arch/arm/mach-pxa/raumfeld.c              |    2 +-
 arch/arm/mach-s3c24xx/Kconfig             |    4 +-
 arch/arm/mach-sa1100/leds-hackkit.c       |    1 +
 arch/arm/mach-tegra/board-harmony-power.c |   32 +++++++------
 arch/arm/plat-samsung/Kconfig             |    3 +-
 drivers/char/hw_random/omap-rng.c         |    2 +-
 drivers/gpio/gpio-em.c                    |    2 +-
 drivers/input/touchscreen/eeti_ts.c       |   21 ++++----
 drivers/mfd/asic3.c                       |    1 +
 drivers/mfd/ezx-pcap.c                    |    2 +-
 drivers/mtd/nand/Kconfig                  |    2 +-
 drivers/mtd/nand/omap2.c                  |    7 ++-
 drivers/spi/spi-s3c64xx.c                 |    2 +-
 drivers/usb/host/ohci-omap.c              |    2 -
 include/linux/input/eeti_ts.h             |    1 +
 include/linux/mfd/ezx-pcap.h              |    1 +
 36 files changed, 160 insertions(+), 167 deletions(-)


From arnd at arndb.de  Fri Aug 10 15:06:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 10 Aug 2012 19:06:48 -0000
Subject: =?UTF-8?q?=5BGIT=20PULL=203/3=5D=20arm-soc=3A=20make=20of=5Fdevice=5Fid-=3Edata=20constant?=
In-Reply-To: <1344625575-27560-1-git-send-email-arnd@arndb.de>
References: <1344625575-27560-1-git-send-email-arnd@arndb.de>
Message-ID: <1344625575-27560-4-git-send-email-arnd@arndb.de>

The following changes since commit 28a33cbc24e4256c143dce96c7d93bf423229f92:

  Linux 3.5 (2012-07-21 13:58:29 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/late-warnings

for you to fetch changes up to 100e8f5fda756fe71d21c0ea68d67e56f5f05167:

  Merge branch 'ofdeviceiddata' of git://git.pengutronix.de/git/ukl/linux into late/warnings (2012-07-24 16:58:51 +0200)

----------------------------------------------------------------

arm-soc: make of_device_id->data constant

This patch series from Uwe Kleine-K?nigwas meant to go into
the v3.6 merge window, but got lost in a small miscommunication
between Olof and me. It gets rid of a (harmless) gcc warning
by making the of_device_id->data pointer constant, which is
generally considered to be a good idea.

Cc: "Uwe Kleine-K?nig" <u.kleine-koenig at pengutronix.de>
----------------------------------------------------------------
Arnd Bergmann (7):
      watchdog/mpc8xxx: add a const qualifier
      powerpc/fsl_msi: drop unneeded cast to non-const pointer
      mfd/da9052: make i2c_device_id array const
      i2c/mpc: make data used as *of_device_id.data const
      macintosh/mediabay: make data used as *of_device_id.data const
      can: mpc5xxx_can: make data used as *of_device_id.data const
      Merge branch 'ofdeviceiddata' of git://git.pengutronix.de/git/ukl/linux into late/warnings

Marc Kleine-Budde (1):
      can: mpc5xxx_can: make data in mpc5xxx_can_probe const

Uwe Kleine-K?nig (18):
      spi/imx: make spi_imx_data.devtype_data member point to const data
      spi/spi-omap2-mcspi: add a const qualifier
      serial/imx: make imx_port.devdata member point to const data
      serial/mpc52xx_uart: add a const qualifier
      ARM: cache-l2x0: add a const qualifier
      misc/atmel_tc: make atmel_tc.tcb_config member point to const data
      gpio/gpio-omap.c: add a const qualifier
      gpio/mpc8xxx: add a const qualifier
      i2c/i2c-omap: add a const qualifier
      i2c/mpc: add a const qualifier
      dmaengine: at_hdmac: add a few const qualifiers
      mmc/omap_hsmmc: add a const qualifier
      macintosh/mediabay: add a const qualifier
      powerpc/83xx: add a const qualifier
      powerpc/fsl_msi: add a const qualifier
      powerpc/celleb_pci: add a const qualifier
      of: add const to struct *of_device_id.data
      gpio/gpio-omap: make platformdata used as *of_device_id.data const

 arch/arm/mm/cache-l2x0.c                 |    2 +-
 arch/powerpc/platforms/83xx/suspend.c    |    2 +-
 arch/powerpc/platforms/cell/celleb_pci.c |    2 +-
 arch/powerpc/sysdev/fsl_msi.c            |    8 ++++----
 drivers/dma/at_hdmac.c                   |    4 ++--
 drivers/gpio/gpio-mpc8xxx.c              |    2 +-
 drivers/gpio/gpio-omap.c                 |    8 ++++----
 drivers/i2c/busses/i2c-mpc.c             |   12 ++++++------
 drivers/i2c/busses/i2c-omap.c            |    3 ++-
 drivers/macintosh/mediabay.c             |    8 ++++----
 drivers/mfd/da9052-i2c.c                 |    4 ++--
 drivers/mmc/host/omap_hsmmc.c            |    2 +-
 drivers/net/can/mscan/mpc5xxx_can.c      |    6 +++---
 drivers/spi/spi-imx.c                    |    2 +-
 drivers/spi/spi-omap2-mcspi.c            |    2 +-
 drivers/tty/serial/imx.c                 |    2 +-
 drivers/tty/serial/mpc52xx_uart.c        |    2 +-
 drivers/watchdog/mpc8xxx_wdt.c           |    2 +-
 include/linux/atmel_tc.h                 |    2 +-
 include/linux/mod_devicetable.h          |    2 +-
 20 files changed, 39 insertions(+), 38 deletions(-)


From cyril at ti.com  Fri Aug 10 21:25:40 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 11 Aug 2012 01:25:40 -0000
Subject: [RFC v2 21/22] ARM: keystone: enable SMP on Keystone machines
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-22-git-send-email-cyril@ti.com>

This patch adds basic SMP support for Keystone machines.  Nothing very fancy
here, just enough to get 4 CPUs booted up.  This does not include support for
hotplug, etc.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/Kconfig                    |    1 +
 arch/arm/configs/keystone_defconfig |    2 +
 arch/arm/mach-keystone/Makefile     |    1 +
 arch/arm/mach-keystone/keystone.c   |    3 ++
 arch/arm/mach-keystone/keystone.h   |   23 +++++++++++
 arch/arm/mach-keystone/platsmp.c    |   74 +++++++++++++++++++++++++++++++++++
 6 files changed, 104 insertions(+)
 create mode 100644 arch/arm/mach-keystone/keystone.h
 create mode 100644 arch/arm/mach-keystone/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f1b8aa0..37b4e9c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -416,6 +416,7 @@ config ARCH_KEYSTONE
 	select SPARSE_IRQ
 	select NEED_MACH_MEMORY_H
 	select HAVE_SCHED_CLOCK
+	select HAVE_SMP
 	help
 	  Support for boards based on the Texas Instruments Keystone family of
 	  SoCs.
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 7f2a04b..5f71e66 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -1,7 +1,9 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
+CONFIG_NR_CPUS=4
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_VFP=y
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index d4671d5..3f6b8ab 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -1 +1,2 @@
 obj-y					:= keystone.o
+obj-$(CONFIG_SMP)			+= platsmp.o
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 702c184..6a8ece9 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -26,6 +26,8 @@
 #include <asm/arch_timer.h>
 #include <asm/hardware/gic.h>
 
+#include "keystone.h"
+
 static struct map_desc io_desc[] = {
 	{
 		.virtual        = 0xfe800000UL,
@@ -73,6 +75,7 @@ static const char *keystone_match[] __initconst = {
 };
 
 DT_MACHINE_START(KEYSTONE, "Keystone")
+	smp_ops(keystone_smp_ops)
 	.map_io		= keystone_map_io,
 	.init_irq	= keystone_init_irq,
 	.timer		= &keystone_timer,
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
new file mode 100644
index 0000000..71bd0f4
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __KEYSTONE_H__
+#define __KEYSTONE_H__
+
+extern struct smp_ops keystone_smp_ops;
+extern void secondary_startup(void);
+
+#endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
new file mode 100644
index 0000000..dbe7601
--- /dev/null
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2012 Texas Instruments, Inc.
+ *
+ * Based on platsmp.c, Copyright 2010-2011 Calxeda, Inc.
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/smp_plat.h>
+#include <asm/smp_ops.h>
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+#include <asm/memory.h>
+
+#include "keystone.h"
+
+static void __init keystone_smp_init_cpus(void)
+{
+	unsigned int i, ncores;
+
+	ncores = 4;
+
+	/* sanity check */
+	if (ncores > NR_CPUS) {
+		pr_warn("restricted to %d cpus\n", NR_CPUS);
+		ncores = NR_CPUS;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init keystone_smp_prepare_cpus(unsigned int max_cpus)
+{
+	/* nothing for now */
+}
+
+static void __cpuinit keystone_secondary_init(unsigned int cpu)
+{
+	gic_secondary_init(0);
+}
+
+static int __cpuinit
+keystone_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long *ptr;
+	
+	ptr = phys_to_virt(0x800001f0);
+	ptr[cpu] = virt_to_idmap(&secondary_startup);
+	__cpuc_flush_dcache_area(ptr, sizeof(ptr) * 4);
+
+	return 0;
+}
+
+struct smp_ops keystone_smp_ops __initdata = {
+	smp_init_ops(keystone)
+	smp_secondary_ops(keystone)
+};
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:25:55 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 11 Aug 2012 01:25:55 -0000
Subject: [RFC v2 22/22] ARM: keystone: add switch over to high physical
 address range
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-23-git-send-email-cyril@ti.com>

Keystone platforms have their physical memory mapped at an address outside the
32-bit physical range.  A Keystone machine with 16G of RAM would find its
memory at 0x0800000000 - 0x0bffffffff.

For boot purposes, the interconnect supports a limited alias of some of this
memory within the 32-bit addressable space (0x80000000 - 0xffffffff).  This
aliasing is implemented in hardware, and is not intended to be used much
beyond boot.  For instance, DMA coherence does not work when running out of
this aliased address space.

Therefore, we've taken the approach of booting out of the low physical address
range, and subsequently we switch over to the high range once we're safely
inside machine specific territory.  This patch implements this switch over
mechanism, which involves rewiring the TTBRs and page tables to point to the
new physical address space.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 arch/arm/Kconfig                             |    1 +
 arch/arm/boot/dts/keystone-sim.dts           |    8 +++---
 arch/arm/configs/keystone_defconfig          |    1 +
 arch/arm/mach-keystone/include/mach/memory.h |   25 +++++++++++++++++
 arch/arm/mach-keystone/keystone.c            |   39 ++++++++++++++++++++++++++
 arch/arm/mach-keystone/platsmp.c             |   16 +++++++++--
 6 files changed, 83 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 37b4e9c..18ffff7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -417,6 +417,7 @@ config ARCH_KEYSTONE
 	select NEED_MACH_MEMORY_H
 	select HAVE_SCHED_CLOCK
 	select HAVE_SMP
+	select ZONE_DMA if ARM_LPAE
 	help
 	  Support for boards based on the Texas Instruments Keystone family of
 	  SoCs.
diff --git a/arch/arm/boot/dts/keystone-sim.dts b/arch/arm/boot/dts/keystone-sim.dts
index acec30f8..17ee473 100644
--- a/arch/arm/boot/dts/keystone-sim.dts
+++ b/arch/arm/boot/dts/keystone-sim.dts
@@ -4,8 +4,8 @@
 / {
 	model = "Texas Instruments Keystone 2 SoC";
 	compatible = "ti,keystone-evm";
-	#address-cells = <1>;
-	#size-cells = <1>;
+	#address-cells = <2>;
+	#size-cells = <2>;
 	interrupt-parent = <&gic>;
 
 	aliases {
@@ -13,11 +13,11 @@
 	};
 
 	chosen {
-		bootargs = "console=ttyS0,115200n8 debug earlyprintk lpj=50000 rdinit=/bin/ash rw root=/dev/ram0 initrd=0x85000000,2M";
+		bootargs = "console=ttyS0,115200n8 debug earlyprintk lpj=50000 rdinit=/bin/ash rw root=/dev/ram0 initrd=0x805000000,2M";
 	};
 
 	memory {
-		reg = <0x80000000 0x8000000>;
+		reg = <0x00000008 0x00000000 0x00000000 0x8000000>;
 	};
 
 	cpus {
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 5f71e66..8ea3b96 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -1,6 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARM_LPAE=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_NR_CPUS=4
diff --git a/arch/arm/mach-keystone/include/mach/memory.h b/arch/arm/mach-keystone/include/mach/memory.h
index 7c78b1e..a5f7a1a 100644
--- a/arch/arm/mach-keystone/include/mach/memory.h
+++ b/arch/arm/mach-keystone/include/mach/memory.h
@@ -19,4 +19,29 @@
 #define MAX_PHYSMEM_BITS	36
 #define SECTION_SIZE_BITS	34
 
+#define KEYSTONE_LOW_PHYS_START		0x80000000ULL
+#define KEYSTONE_LOW_PHYS_SIZE		0x80000000ULL /* 2G */
+#define KEYSTONE_LOW_PHYS_END		(KEYSTONE_LOW_PHYS_START + \
+					 KEYSTONE_LOW_PHYS_SIZE - 1)
+
+#define KEYSTONE_HIGH_PHYS_START	0x800000000ULL
+#define KEYSTONE_HIGH_PHYS_SIZE		0x400000000ULL	/* 16G */
+#define KEYSTONE_HIGH_PHYS_END		(KEYSTONE_HIGH_PHYS_START + \
+					 KEYSTONE_HIGH_PHYS_SIZE - 1)
+#ifdef CONFIG_ARM_LPAE
+
+#ifndef __ASSEMBLY__
+
+static inline phys_addr_t __virt_to_idmap(unsigned long x)
+{
+	return (phys_addr_t)(x) - CONFIG_PAGE_OFFSET +
+		KEYSTONE_LOW_PHYS_START;
+}
+
+#define virt_to_idmap(x)	__virt_to_idmap((unsigned long)(x))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_LPAE */
+
 #endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 6a8ece9..c4be7a7 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -74,6 +74,41 @@ static const char *keystone_match[] __initconst = {
 	NULL,
 };
 
+static void __init keystone_init_meminfo(void)
+{
+	bool lpae = IS_ENABLED(CONFIG_ARM_LPAE);
+	bool pvpatch = IS_ENABLED(CONFIG_ARM_PATCH_PHYS_VIRT);
+	phys_addr_t offset = PHYS_OFFSET - KEYSTONE_LOW_PHYS_START;
+	phys_addr_t mem_start, mem_end;
+
+	BUG_ON(meminfo.nr_banks < 1);
+	mem_start = meminfo.bank[0].start;
+	mem_end = mem_start + meminfo.bank[0].size - 1;
+
+	/* nothing to do if we are running out of the <32-bit space */
+	if (mem_start >= KEYSTONE_LOW_PHYS_START &&
+	    mem_end   <= KEYSTONE_LOW_PHYS_END)
+		return;
+
+	if (!lpae || !pvpatch) {
+		panic("Enable %s%s%s to run outside 32-bit space\n",
+		      !lpae ? __stringify(CONFIG_ARM_LPAE) : "",
+		      (!lpae && !pvpatch) ? " and " : "",
+		      !pvpatch ? __stringify(CONFIG_ARM_PATCH_PHYS_VIRT) : "");
+	}
+
+	if (mem_start < KEYSTONE_HIGH_PHYS_START ||
+	    mem_end   > KEYSTONE_HIGH_PHYS_END) {
+		panic("Invalid address space for memory (%08llx-%08llx)\n",
+		      mem_start, mem_end);
+	}
+
+	offset += KEYSTONE_HIGH_PHYS_START;
+	pr_info("switching to high address space at 0x%llx\n", offset);
+	__pv_phys_offset = offset;
+	__pv_offset      = offset - PAGE_OFFSET;
+}
+
 DT_MACHINE_START(KEYSTONE, "Keystone")
 	smp_ops(keystone_smp_ops)
 	.map_io		= keystone_map_io,
@@ -82,4 +117,8 @@ DT_MACHINE_START(KEYSTONE, "Keystone")
 	.handle_irq	= gic_handle_irq,
 	.init_machine	= keystone_init,
 	.dt_compat	= keystone_match,
+	.init_meminfo	= keystone_init_meminfo,
+#ifdef CONFIG_ZONE_DMA
+	.dma_zone_size	= SZ_2G,
+#endif
 MACHINE_END
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
index dbe7601..0151906 100644
--- a/arch/arm/mach-keystone/platsmp.c
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -24,6 +24,7 @@
 #include <asm/smp_ops.h>
 #include <asm/hardware/gic.h>
 #include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
 #include <asm/memory.h>
 
 #include "keystone.h"
@@ -51,17 +52,26 @@ static void __init keystone_smp_prepare_cpus(unsigned int max_cpus)
 	/* nothing for now */
 }
 
+static void __cpuinit keystone_secondary_initmem(void)
+{
+#ifdef CONFIG_ARM_LPAE
+	pgd_t *pgd0 = pgd_offset_k(0);
+	cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
+	local_flush_tlb_all();
+#endif
+}
+
 static void __cpuinit keystone_secondary_init(unsigned int cpu)
 {
 	gic_secondary_init(0);
+	keystone_secondary_initmem();
 }
 
 static int __cpuinit
 keystone_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned long *ptr;
-	
-	ptr = phys_to_virt(0x800001f0);
+	unsigned long *ptr = (unsigned long *)(PAGE_OFFSET + 0x1f0);
+
 	ptr[cpu] = virt_to_idmap(&secondary_startup);
 	__cpuc_flush_dcache_area(ptr, sizeof(ptr) * 4);
 
-- 
1.7.9.5



From cyril at ti.com  Fri Aug 10 21:26:01 2012
From: cyril at ti.com (Cyril Chemparathy)
Date: Sat, 11 Aug 2012 01:26:01 -0000
Subject: [RFC v2 20/22] ARM: keystone: introducing TI Keystone platform
In-Reply-To: <1344648306-15619-1-git-send-email-cyril@ti.com>
References: <1344648306-15619-1-git-send-email-cyril@ti.com>
Message-ID: <1344648306-15619-21-git-send-email-cyril@ti.com>

Texas Instruments Keystone family of multicore devices now includes an
upcoming slew of Cortex A15 based devices.  This patch adds basic definitions
for a new Keystone sub-architecture in ARM.

Subsequent patches in this series will extend support to include SMP and take
advantage of the large physical memory addressing capabilities via LPAE.

Signed-off-by: Vitaly Andrianov <vitalya at ti.com>
Signed-off-by: Cyril Chemparathy <cyril at ti.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Kconfig                                  |   18 +++++
 arch/arm/Makefile                                 |    1 +
 arch/arm/boot/dts/keystone-sim.dts                |   77 +++++++++++++++++++
 arch/arm/configs/keystone_defconfig               |   20 +++++
 arch/arm/mach-keystone/Makefile                   |    1 +
 arch/arm/mach-keystone/Makefile.boot              |    1 +
 arch/arm/mach-keystone/include/mach/debug-macro.S |   44 +++++++++++
 arch/arm/mach-keystone/include/mach/memory.h      |   22 ++++++
 arch/arm/mach-keystone/include/mach/timex.h       |   21 ++++++
 arch/arm/mach-keystone/include/mach/uncompress.h  |   24 ++++++
 arch/arm/mach-keystone/keystone.c                 |   82 +++++++++++++++++++++
 11 files changed, 311 insertions(+)
 create mode 100644 arch/arm/boot/dts/keystone-sim.dts
 create mode 100644 arch/arm/configs/keystone_defconfig
 create mode 100644 arch/arm/mach-keystone/Makefile
 create mode 100644 arch/arm/mach-keystone/Makefile.boot
 create mode 100644 arch/arm/mach-keystone/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-keystone/include/mach/memory.h
 create mode 100644 arch/arm/mach-keystone/include/mach/timex.h
 create mode 100644 arch/arm/mach-keystone/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-keystone/keystone.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9ac86ea..f1b8aa0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -402,6 +402,24 @@ config ARCH_HIGHBANK
 	help
 	  Support for the Calxeda Highbank SoC based boards.
 
+config ARCH_KEYSTONE
+	bool "Texas Instruments Keystone Devices"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select ARM_GIC
+	select MULTI_IRQ_HANDLER
+	select CLKDEV_LOOKUP
+	select COMMON_CLK
+	select CLKSRC_MMIO
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select USE_OF
+	select SPARSE_IRQ
+	select NEED_MACH_MEMORY_H
+	select HAVE_SCHED_CLOCK
+	help
+	  Support for boards based on the Texas Instruments Keystone family of
+	  SoCs.
+
 config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 	select CPU_ARM720T
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..75b5b79 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
 machine-$(CONFIG_ARCH_H720X)		:= h720x
 machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
+machine-$(CONFIG_ARCH_KEYSTONE)		:= keystone
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x
diff --git a/arch/arm/boot/dts/keystone-sim.dts b/arch/arm/boot/dts/keystone-sim.dts
new file mode 100644
index 0000000..acec30f8
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-sim.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Texas Instruments Keystone 2 SoC";
+	compatible = "ti,keystone-evm";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0	= &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 debug earlyprintk lpj=50000 rdinit=/bin/ash rw root=/dev/ram0 initrd=0x85000000,2M";
+	};
+
+	memory {
+		reg = <0x80000000 0x8000000>;
+	};
+
+	cpus {
+		interrupt-parent = <&gic>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a15";
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a15";
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a15";
+		};
+
+		cpu at 3 {
+			compatible = "arm,cortex-a15";
+		};
+
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "ti,keystone","simple-bus";
+		interrupt-parent = <&gic>;
+
+		gic:	interrupt-controller at 02560000 {
+			compatible = "arm,cortex-a15-gic";
+			#interrupt-cells = <3>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0x02561000 0x1000>,
+			      <0x02562000 0x2000>;
+		};
+
+		timer {
+			compatible = "arm,armv7-timer";
+			interrupts = <1 13 0xf08 1 14 0xf08>;
+			clock-frequency = <10000000>; /* Freq in Hz - optional */
+		};
+
+		uart0:	serial at 02530c00 {
+			compatible	= "ns16550a";
+			current-speed	= <115200>;
+			reg-shift	= <2>;
+			reg-io-width	= <4>;
+			reg		= <0x02530c00 0x100>;
+			clock-frequency = <48000000>;
+			interrupts	= <0 277 0xf01>;
+		};
+	};
+};
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
new file mode 100644
index 0000000..7f2a04b
--- /dev/null
+++ b/arch/arm/configs/keystone_defconfig
@@ -0,0 +1,20 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
new file mode 100644
index 0000000..d4671d5
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile
@@ -0,0 +1 @@
+obj-y					:= keystone.o
diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot
new file mode 100644
index 0000000..dae9661
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y	:= 0x00008000
diff --git a/arch/arm/mach-keystone/include/mach/debug-macro.S b/arch/arm/mach-keystone/include/mach/debug-macro.S
new file mode 100644
index 0000000..1108210
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/debug-macro.S
@@ -0,0 +1,44 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/serial_reg.h>
+
+#define UART_SHIFT	2
+
+	.macro	addruart,rp,rv,tmp
+	movw	\rv, #0x0c00
+	movt	\rv, #0xfed3
+	movw	\rp, #0x0c00
+	movt	\rp, #0x0253
+	.endm
+
+
+	.macro	senduart,rd,rx
+	str	\rd, [\rx, #UART_TX << UART_SHIFT]
+	.endm
+
+	.macro	busyuart,rd,rx
+1002:	ldr	\rd, [\rx, #UART_LSR << UART_SHIFT]
+	and	\rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+	teq	\rd, #UART_LSR_TEMT | UART_LSR_THRE
+	bne	1002b
+	.endm
+
+	.macro	waituart,rd,rx
+	.endm
diff --git a/arch/arm/mach-keystone/include/mach/memory.h b/arch/arm/mach-keystone/include/mach/memory.h
new file mode 100644
index 0000000..7c78b1e
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/memory.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_MACH_MEMORY_H
+#define __ASM_MACH_MEMORY_H
+
+#define MAX_PHYSMEM_BITS	36
+#define SECTION_SIZE_BITS	34
+
+#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-keystone/include/mach/timex.h b/arch/arm/mach-keystone/include/mach/timex.h
new file mode 100644
index 0000000..f355ecb
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/timex.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE		1000000
+
+#endif
diff --git a/arch/arm/mach-keystone/include/mach/uncompress.h b/arch/arm/mach-keystone/include/mach/uncompress.h
new file mode 100644
index 0000000..1071761
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/uncompress.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
new file mode 100644
index 0000000..702c184
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2010-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/arch_timer.h>
+#include <asm/hardware/gic.h>
+
+static struct map_desc io_desc[] = {
+	{
+		.virtual        = 0xfe800000UL,
+		.pfn            = __phys_to_pfn(0x02000000UL),
+		.length         = 0x800000UL,
+		.type           = MT_DEVICE
+	},
+};
+
+static void __init keystone_map_io(void)
+{
+	iotable_init(io_desc, ARRAY_SIZE(io_desc));
+}
+
+static const struct of_device_id irq_match[] = {
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+	{}
+};
+
+static void __init keystone_init_irq(void)
+{
+	of_irq_init(irq_match);
+}
+
+
+static void __init keystone_timer_init(void)
+{
+	arch_timer_of_register();
+	arch_timer_sched_clock_init();
+}
+
+static struct sys_timer keystone_timer = {
+	.init = keystone_timer_init,
+};
+
+
+static void __init keystone_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *keystone_match[] __initconst = {
+	"ti,keystone-evm",
+	NULL,
+};
+
+DT_MACHINE_START(KEYSTONE, "Keystone")
+	.map_io		= keystone_map_io,
+	.init_irq	= keystone_init_irq,
+	.timer		= &keystone_timer,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= keystone_init,
+	.dt_compat	= keystone_match,
+MACHINE_END
-- 
1.7.9.5



From shawn.guo at linaro.org  Mon Aug 13 09:06:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 13 Aug 2012 13:06:16 -0000
Subject: [PATCH 15/17] ARM: imx53: remove unneeded files and functions
In-Reply-To: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
References: <1344863137-6112-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1344863137-6112-16-git-send-email-shawn.guo@linaro.org>

Now imx53 is a device tree only platform, so the files and functions
used only by non-DT kernel can be removed.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/devices-imx53.h           |   48 --
 arch/arm/mach-imx/mm-imx5.c                 |   47 -
 arch/arm/plat-mxc/include/mach/common.h     |    1 -
 arch/arm/plat-mxc/include/mach/iomux-mx53.h | 1219 ---------------------------
 4 files changed, 0 insertions(+), 1315 deletions(-)
 delete mode 100644 arch/arm/mach-imx/devices-imx53.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h

diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db9..0000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010 Yong Shen. <Yong.Shen at linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx53.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx53_fec_data;
-#define imx53_add_fec(pdata)   \
-	imx_add_fec(&imx53_fec_data, pdata)
-
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
-#define imx53_add_imx_uart(id, pdata)	\
-	imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-
-
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
-#define imx53_add_imx_i2c(id, pdata)	\
-	imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
-#define imx53_add_sdhci_esdhc_imx(id, pdata)	\
-	imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx53_ecspi_data[];
-#define imx53_add_ecspi(id, pdata)	\
-	imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id)	\
-	imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
-
-extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
-#define imx53_add_imx_ssi(id, pdata)	\
-	imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
-#define imx53_add_imx_keypad(pdata)	\
-	imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx53_pata_imx_data;
-#define imx53_add_pata_imx() \
-	imx_add_pata_imx(&imx53_pata_imx_data)
-
-extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f53..acb0aad 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
 	.script_addrs = &imx51_sdma_script,
 };
 
-static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
-	.ap_2_ap_addr = 642,
-	.app_2_mcu_addr = 683,
-	.mcu_2_app_addr = 747,
-	.uart_2_mcu_addr = 817,
-	.shp_2_mcu_addr = 891,
-	.mcu_2_shp_addr = 960,
-	.uartsh_2_mcu_addr = 1032,
-	.spdif_2_mcu_addr = 1100,
-	.mcu_2_spdif_addr = 1134,
-	.firi_2_mcu_addr = 1193,
-	.mcu_2_firi_addr = 1290,
-};
-
-static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-	.fw_name = "sdma-imx53.bin",
-	.script_addrs = &imx53_sdma_script,
-};
-
 static const struct resource imx50_audmux_res[] __initconst = {
 	DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 };
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
 	DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 };
 
-static const struct resource imx53_audmux_res[] __initconst = {
-	DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
 void __init imx50_soc_init(void)
 {
 	/* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
 					ARRAY_SIZE(imx51_audmux_res));
 }
 
-void __init imx53_soc_init(void)
-{
-	/* i.mx53 has the i.mx35 type gpio */
-	mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-	mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-	mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-	mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-	mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-	mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-	mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
-
-	pinctrl_provide_dummies();
-	/* i.mx53 has the i.mx35 type sdma */
-	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
-
-	/* Setup AIPS registers */
-	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
-	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
-
-	/* i.mx53 has the i.mx31 type audmux */
-	platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
-					ARRAY_SIZE(imx53_audmux_res));
-}
-
 void __init imx51_init_late(void)
 {
 	mx51_neon_fixup();
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 96fa702..0932fc6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
-extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
 extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
deleted file mode 100644
index 9761e00..0000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1219 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc..
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_IOMUX_MX53_H__
-#define __MACH_IOMUX_MX53_H__
-
-#include <mach/iomux-v3.h>
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_	0x00
-
-#define MX53_UART_PAD_CTRL		(PAD_CTL_PKE | PAD_CTL_PUE |	\
-		PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define MX53_SDHC_PAD_CTRL 	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-				PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-				PAD_CTL_SRE_FAST)
-
-
-#define MX53_PAD_GPIO_19__KPP_COL_5			IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5			IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO			IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1			IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY			IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3			IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT			IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0			IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6			IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX		IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK			IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3			IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0			IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7			IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX		IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI			IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER			IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1			IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8			IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX		IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO			IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK			IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY		IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1			IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9			IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX		IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0			IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL			IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2			IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10			IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN			IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO			IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1			IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2			IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2			IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11			IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN			IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC			IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2			IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2			IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3			IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12			IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP			IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1			IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL			IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3			IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS			IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3			IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13			IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM			IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA			IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4			IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14			IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN			IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4			IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS			IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4			IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15			IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN			IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5			IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS			IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16			IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17			IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID		IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18			IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19			IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20			IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP			IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21			IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK			IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22			IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI			IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	\
-							IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23			IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO			IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24			IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0			IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25			IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1			IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26			IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2			IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27			IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3			IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28			IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY			IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29			IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO			IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30			IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO			IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31			IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	\
-							IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5			IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	\
-							IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6			IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	\
-							IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO5_7			IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	\
-							IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8			IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	\
-							IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9			IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1		IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1		IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	\
-							IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10			IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3	\
-							IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11			IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO		IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4	\
-							IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12			IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0		IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5	\
-							IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13			IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6	\
-							IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14			IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	\
-							IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO5_15			IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16			IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO		IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17			IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0		IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18			IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19			IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL			IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20			IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21			IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22			IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5			IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23			IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5			IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24			IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6			IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO			IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25			IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6			IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0			IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26			IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7			IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA			IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27			IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7			IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL			IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28			IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO		IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29			IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0			IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30			IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31			IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0			IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1			IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2			IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS			IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3			IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS			IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4			IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS			IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5			IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS			IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25			IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2			IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY			IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12			IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1			IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS			IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK		IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30			IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0			IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL			IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16			IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16			IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5			IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK			IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA			IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17			IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17			IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6			IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO			IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL			IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18			IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18			IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7			IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI			IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA			IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS			IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19			IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19			IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8			IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1			IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO			IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS			IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC		IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20			IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20			IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16			IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0			IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO			IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS			IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21			IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21			IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17			IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK			IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL			IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22			IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22			IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1			IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO			IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23			IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23			IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS			IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD			IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS			IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2			IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14			IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31			IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS			IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI			IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3			IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16			IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24			IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24			IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX			IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2			IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2			IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2			IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR			IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25			IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25			IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX			IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3			IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3			IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3			IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR			IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26			IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26			IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX			IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD			IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1			IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11			IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2			IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27			IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27			IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX			IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD			IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0			IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13			IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3			IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28			IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28			IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS			IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI			IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA			IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG			IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13			IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29			IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29			IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS			IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0			IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15			IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14			IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30			IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30			IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__UART3_CTS			IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3			IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11			IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC		IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC		IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31			IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31			IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS			IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2			IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12			IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24			IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4			IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19			IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2			IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID		IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23			IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6			IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18			IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3			IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22			IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16			IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17			IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7			IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21			IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17			IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16			IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6			IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20			IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18			IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15			IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5			IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19			IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19			IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14			IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4			IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18			IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20			IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13			IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3			IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17			IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21			IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12			IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2			IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16			IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22			IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1			IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23			IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK			IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5			IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24			IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI			IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6			IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE			IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25			IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO			IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7			IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG			IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW			IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26			IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0			IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8			IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA			IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27			IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1			IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17			IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28			IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11			IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY			IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29			IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10			IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0			IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9			IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1			IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8			IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2			IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7			IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3			IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6			IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4			IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5			IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5			IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4			IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6			IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3			IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7			IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2			IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8			IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1			IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9			IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0			IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10			IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15		IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11			IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2			IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12			IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3			IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13			IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14			IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15			IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1			IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4			IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12			IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13			IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0			IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22			IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24			IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26			IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28			IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30			IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22			IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24			IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26			IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28			IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30			IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0			IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT		IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1			IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2			IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3			IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4			IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7			IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8			IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9			IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10			IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11			IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14			IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK			IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15			IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0			IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0			IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG			IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16			IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1			IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1			IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT			IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO			IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22			IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR			IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL			IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23			IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR			IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER			IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24			IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR			IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK			IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV			IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25			IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1			IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26			IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST			IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG			IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0			IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27			IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT			IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN			IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28			IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1			IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29			IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK			IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0			IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30			IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC			IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31			IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT			IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW			IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17			IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX		IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK			IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18			IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX		IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ			IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0			IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1		IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ			IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2			IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS			IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN			IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR			IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3			IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS			IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN			IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4			IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD		IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS		IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN		IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY			IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5			IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK			IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS			IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN			IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0			IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6			IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST			IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE			IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1			IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7			IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD			IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS			IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2			IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8			IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK			IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS			IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0			IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9			IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX		IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1			IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10			IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX		IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0		IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0			IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4		IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1		IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1			IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5		IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2		IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2			IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6		IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3		IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3			IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7		IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4		IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4			IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4		IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5		IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5			IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5		IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6		IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6			IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6		IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7		IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7			IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7		IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8		IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8			IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4		IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0		IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9		IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9			IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5		IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1		IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10		IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10			IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6		IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2		IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11		IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11			IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7		IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3		IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12		IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12			IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4		IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0		IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13		IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13			IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5		IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1		IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14		IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14			IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6		IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2		IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15		IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15			IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7		IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3		IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0			IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16			IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1			IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO			IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1			IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17			IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2			IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0			IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD			IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18			IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1			IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI			IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP			IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2			IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19			IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2			IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO			IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1			IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK			IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20			IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT		IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN			IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK			IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3			IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21			IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3			IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO			IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2			IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK			IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10			IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5			IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK			IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V			IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD			IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11			IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5			IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI			IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM			IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3			IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12			IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6			IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2			IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE			IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2			IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13			IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6			IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1			IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL			IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1			IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14			IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7			IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0			IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0			IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15			IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7			IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO			IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT		IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO			IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0			IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5			IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO			IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB			IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD				IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR			IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1			IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5			IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO			IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B			IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD			IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK			IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR			IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9			IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6			IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B			IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO			IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B			IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP			IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE			IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR			IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3			IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL			IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2			IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC		IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK			IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT			IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6			IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA			IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0			IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL			IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG			IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST			IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2			IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6			IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1			IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP			IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT			IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT			IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4			IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7			IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2			IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD			IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE			IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3			IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5			IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7			IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO			IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL			IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP			IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1			IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7			IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO			IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN			IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX			IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD			IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK			IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP			IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0			IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8			IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO			IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN			IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX			IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD			IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK			IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP			IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2			IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11			IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1			IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA			IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B			IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0			IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12			IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY			IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1			IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2			IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT			IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1			IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13			IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE			IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL			IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST		IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
-
-#endif	/* __MACH_IOMUX_MX53_H__ */
-- 
1.7.5.4




From northrup.james at gmail.com  Thu Aug 16 14:55:10 2012
From: northrup.james at gmail.com (james northrup)
Date: Thu, 16 Aug 2012 18:55:10 -0000
Subject: [GIT PULL] Update LZO compression
In-Reply-To: <CAMuHMdWK_Y=QwkgQD6K8tFBLaO04Fy0yVAzEpb2OYW6Ec0hGoA@mail.gmail.com>
References: <50299142.2030504@oberhumer.com> <20120814123937.GA14756@sig21.net>
 <502B8FE3.7080501@oberhumer.com> <20120815144539.GA8300@sig21.net>
 <502C92C3.7090701@oberhumer.com> <20120816150647.GA22010@sig21.net>
 <20120816232549.4d14a6aa@natsu>
 <20120816175234.GL11413@one.firstfloor.org>
 <CAMuHMdWK_Y=QwkgQD6K8tFBLaO04Fy0yVAzEpb2OYW6Ec0hGoA@mail.gmail.com>
Message-ID: <CAPkEcwgv6f5B+Mrw7kzrHcZ5JZ+Yr0o=bLdoFqCB-e4CLiVx5A@mail.gmail.com>

looks like ARM results are inconclusive from a lot of folks without
bandwidth to do a write-up, what about just plain STAGING status for ARM so
the android tweakers can beat on it for a while?


On Thu, Aug 16, 2012 at 11:18 AM, Geert Uytterhoeven
<geert at linux-m68k.org>wrote:

> On Thu, Aug 16, 2012 at 7:52 PM, Andi Kleen <andi at firstfloor.org> wrote:
> >> I have locked the Allwinner A10 CPU in my Mele A2000 to 60 MHz using
> cpufreq-set,
> >> and ran your test. rnd.lzo is a 9 MB file from /dev/urandom compressed
> with lzo.
> >> There doesn't seem to be a significant difference between all three
> variants.
>
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From alanbutty12 at gmail.com  Fri Aug 17 16:20:32 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Fri, 17 Aug 2012 20:20:32 -0000
Subject: Issues with all kernels after 3.3.7
In-Reply-To: <4345020.aIxQDhhJn6@flatron>
References: <CADhrpJ7r4PPM2nOD7Wch9H+usaDUJ5XYeim6THUKEDTz=-Zyig@mail.gmail.com>
 <CADhrpJ7vg_CERZ8D8VDKkPhRPwZfiam6W3uAaw8yi9WuB2anDg@mail.gmail.com>
 <CADhrpJ7=XooXLcU5_V9wkZAgwCJaLdUL4bfPUWbo-J_eVqovHQ@mail.gmail.com>
 <4345020.aIxQDhhJn6@flatron>
Message-ID: <CADhrpJ798WD8rLbLY+XYbOvU4LacCeoVGM9SUYtHu6jD2Dtm9g@mail.gmail.com>

On 17 August 2012 21:08, Tomasz Figa <tomasz.figa at gmail.com> wrote:
> Hi Alan,
>
> On Friday 17 of August 2012 20:37:08 Alan M Butler wrote:
>> On 17 August 2012 19:12, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> > From: Alan M Butler <alanbutty12 at gmail.com>
>> > Date: 17 August 2012 18:09
>> > Subject: Re: Issues with all kernels after 3.3.7
>> > To: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>> >
>> >
>> > On 17 August 2012 17:46, Uwe Kleine-K?nig
>> >
>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >> Hello,
>> >>
>> >> On Fri, Aug 17, 2012 at 05:30:27PM +0000, Alan M Butler wrote:
>> >>> On 17 August 2012 14:01, Alan M Butler <alanbutty12 at gmail.com> wrote:
>> >>> > On 17 August 2012 13:26, Uwe Kleine-K?nig
>> >>> >
>> >>> > <u.kleine-koenig at pengutronix.de> wrote:
>> >>> >> On Fri, Aug 17, 2012 at 01:47:06PM +0100, alan butler wrote:
>> >>> >>> I have been trying all kernels after 3.3.7 (except for the 3.5
>> >>> >>> series)
>> >>> >>> on my ix2-200
>> >>> >>> and have found that on every kernel 3.3.8, 3.4, 3.4.2, 3.4.4
>> >>> >>> =>3.4.7
>> >>> >>> and now even on 3.6 rc1
>> >>> >>> and the next dated today 17 august that when i use git for
>> >>> >>> example:
>> >>> >>>
>> >>> >>> git clone git://git.videolan.org/x264
>> >>> >>>
>> >>> >>> my system just crash's / hangs and even through the serial port i
>> >>> >>> get
>> >>> >>> no response.
>> >>> >>> This also happens when i try to access a web interface for
>> >>> >>> example the
>> >>> >>> serviio java webui.
>> >>> >>>
>> >>> >>> The second issue i have noticed is that my raid 0 array hangs /
>> >>> >>> pauses
>> >>> >>> when being mounted
>> >>> >>> at system startup. (for approximatly 30 seconds maybe more maybe
>> >>> >>> less
>> >>> >>> im not certain).
>> >>> >>> But again on the 3.3.7 kernel there was no issue and no hang.
>> >>> >>>
>> >>> >>> If i return to 3.3.7 everything works fine with no other
>> >>> >>> modifications
>> >>> >>> to the os or kernels.
>> >>> >>> I am using debian wheezy at the moment but also tried debian
>> >>> >>> squeeze
>> >>> >>> so it does not
>> >>> >>> seem to be related to the specific linux version just the kernel.
>> >>> >>
>> >>> >> Can you bisect your problem? Doing that between 3.3.7 and 3.3.8
>> >>> >> seems to
>> >>> >> be the obvious range to test.
>> >>> >>
>> >>> >> You can also try to enable the various debugging options like
>> >>> >>
>> >>> >>         CONFIG_DETECT_HUNG_TASK
>> >>> >>         CONFIG_PROVE_LOCKING
>> >>> >>         CONFIG_DEBUG_ATOMIC_SLEEP
>> >>> >>         CONFIG_MAGIC_SYSRQ
>> >>> >>
>> >>> >> or try https://lkml.org/lkml/2012/5/26/83.
>> >>> >>
>> >>> >> Best regards
>> >>> >> Uwe
>> >>> >>
>> >>> >> --
>> >>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >>> >>       | Industrial Linux Solutions                 |
>> >>> >> http://www.pengutronix.de/  |>>> >
>> >>> > i enabled the options you said there and i see alot of the
>> >>> > following
>> >>> >
>> >>> > popping up while connected through serial:
>> >>> >  BUG: sleeping function called from invalid context at
>> >>> >
>> >>> > include/linux/freezer.h:46
>> >>> > [  126.896958] in_atomic(): 0, irqs_disabled(): 128, pid: 2180,
>> >>> > name:
>> >>> > console-kit-dae
>> >>> > [  126.904566] no locks held by console-kit-dae/2180.
>> >>> > [  126.909378] irq event stamp: 27643
>> >>> > [  126.912797] hardirqs last  enabled at (27642): [<c03781ac>]
>> >>> > _raw_spin_unlock_irqrestore+0x3c/0x5c
>> >>> > [  126.921735] hardirqs last disabled at (27643): [<c00090cc>]
>> >>> > ret_fast_syscall+0xc/0x38
>> >>> > [  126.929618] softirqs last  enabled at (25565): [<c001bc20>]
>> >>> > irq_exit+0x54/0xb8
>> >>> > [  126.936890] softirqs last disabled at (25558): [<c001bc20>]
>> >>> > irq_exit+0x54/0xb8
>> >>> > [  126.944185] [<c000ea8c>] (unwind_backtrace+0x0/0xe0) from
>> >>> > [<c000b414>] (do_signal+0x84/0x5c0)
>> >>> > [  126.952764] [<c000b414>] (do_signal+0x84/0x5c0) from
>> >>> > [<c000be0c>]
>> >>> > (do_notify_resume+0x18/0x60)
>> >>> > [  126.961430] [<c000be0c>] (do_notify_resume+0x18/0x60) from
>> >>> > [<c0009120>] (work_pending+0x24/0x28)
>> >>> >
>> >>> > there seems to be alot more of them when i have serviio upnp server
>> >>> > running.>>>
>> >>> After a little testing with those config options enabled that you
>> >>> sujested iv found that the problem with git first appears in the
>> >>> 3.4.1
>> >>> kernel.
>> >>> For example:
>> >>> in 3.4.0 kernel i can use 'git clone git://git.videolan.org/x264'
>> >>> successfully.
>> >>>
>> >>> From 3.4.1 kernel on  I can not use 'git clone
>> >>> git://git.videolan.org/x264' the system hangs / crashes with no
>> >>> output
>> >>> at all.
>> >>>
>> >>> the other issue the hang / stall while mounting my etx4 raid 0 is
>> >>> actualy much more recent than i remembered i have tested each kernel
>> >>> from 3.4.0 all the way to 3.4.9 with the config options enabled as
>> >>> sujested before and the stall first starts in kernel 3.4.8 and the
>> >>> following bug keeps popping up repeatedly until the raid is mounted
>> >>> and then anytime a disk is accessed it seems. I was certain it had
>> >>> been popping up before 3.4.8.
>> >>>
>> >>> The following is one of what pops up:
>> >>>  BUG: sleeping function called from invalid context at
>> >>>
>> >>> include/linux/freezer.h:46
>> >>> in_atomic(): 0, irqs_disabled(): 128, pid: 2166, name: minissdpd
>> >>> no locks held by minissdpd/2166.
>> >>>
>> >>>  irq event stamp: 2081
>> >>>
>> >>> hardirqs last  enabled at (2080): [<c02f8dc8>]
>> >>> _raw_spin_unlock_irq+0x24/0x4c hardirqs last disabled at (2081):
>> >>> [<c00090cc>] ret_fast_syscall+0xc/0x38 softirqs last  enabled at
>> >>> (0): [<c0016b38>] copy_process+0x3f8/0xfe8 softirqs last disabled at
>> >>> (0): [<  (null)>]   (null)
>> >>> [<c000eae4>] (unwind_backtrace+0x0/0xe0) from [<c000b5a0>]
>> >>> (do_signal+0x84/0x554)
>> >>> [<c000b5a0>] (do_signal+0x84/0x554) from [<c000bec0>]
>> >>> (do_notify_resume+0x18/0x60)
>> >>> [<c000bec0>] (do_notify_resume+0x18/0x60) from [<c0009120>]
>> >>> (work_pending+0x24/0x28)
>> >>
>> >> I think this is an unrelated issue that I think is fixed in later
>> >> kernels. So I'd disable CONFIG_DEBUG_ATOMIC_SLEEP for further testing.
>> >> Can you try a bisection, i.e.
>> >>
>> >>         git clone
>> >>         git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.
>> >>         git cd linus
>> >>         git remote add -f stable
>> >>         git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-st
>> >>         able.git git bisect v3.4.1 v3.4
>> >>
>> >> and test if the kernel that is checked out then results in a freeze.
>> >>
>> >> Depending on the test result either do:
>> >>         git bisect good # i.e. problem doesn't occur
>> >>
>> >> or
>> >>
>> >>         git bisect bad # problem is reproducible
>> >>
>> >> Repeat that until git points out the first bad commit and report that.
>> >>
>> >> Best regards
>> >> Uwe
>> >>
>> >> --
>> >> Pengutronix e.K.                           | Uwe Kleine-K?nig
>> >>   | Industrial Linux Solutions                 |
>> >> http://www.pengutronix.de/  |>
>> > I dont think it has as i have recently been building the latest 3.6 rc
>> > kernels while creating a patch for my nas and i had the same issue's
>> > on them. Thats what prompted me to actualy come to the mailing list
>> > with it. I have tried the 3.6-rc1 and the latest linux-next dated 17th
>> > of august.
>>
>> Im not sure if this is the right commit as i dont know what way it
>> works but basically the very first commit caused the issue of me not
>> being able to use git and when i typed the git bisect bad it said
>> this:
>>
>> ownerx35 at ownerx35-VirtualBox:~/Desktop/linux$ git bisect bad
>>
>> Bisecting: 21 revisions left to test after this (roughly 5 steps)
>> [774a93aa647f8939867c8ff956847bc63dd51cb3] usbhid: prevent deadlock
>> during timeout
>
> After calling git bisect bad it checks out files from a revision between
> the one currently checked and the one marked as good (imagine binary
> search).
>
> You have to compile and test resulting kernels and tell git whether they're
> good or bad until it tells you that it found the problematic commit.
>
> Best regards,
> Tomasz Figa
>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

It said something about doing it 5 more times or such. and if im
understanding what your saying basicaly i have to build it 5 more
times then it will tell me the commit that was actualy bad so the one
i said there is not the problematic one?



From keguang.zhang at gmail.com  Sat Aug 18 07:54:27 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Sat, 18 Aug 2012 11:54:27 -0000
Subject: [PATCH] clk: add Loongson1B clock support
In-Reply-To: <CAAfyv36-wwvSFJGXN9bmDy8pdDOT_h0b7sy78+7f4kCW57AxuA@mail.gmail.com>
References: <1345287301-18165-1-git-send-email-keguang.zhang@gmail.com>
 <CAAfyv36-wwvSFJGXN9bmDy8pdDOT_h0b7sy78+7f4kCW57AxuA@mail.gmail.com>
Message-ID: <CAJhJPsVd_XM2QJnU7teQc4JCEPzp3e-YU5vTvW4Twzs9d--0FA@mail.gmail.com>

2012/8/18 Belisko Marek <marek.belisko at gmail.com>

> On Sat, Aug 18, 2012 at 12:55 PM, Kelvin Cheung <keguang.zhang at gmail.com>
> wrote:
> > This adds clock support to Loongson1B SoC using the common clock
> > infrastructure.
> >
> > Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
> > ---
> >  drivers/clk/Makefile   |    1 +
> >  drivers/clk/clk-ls1x.c |  108
> ++++++++++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 109 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/clk/clk-ls1x.c
> >
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index 5869ea3..018ec57 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)    += socfpga/
> >  obj-$(CONFIG_PLAT_SPEAR)       += spear/
> >  obj-$(CONFIG_ARCH_U300)                += clk-u300.o
> >  obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
> > +obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
> >
> >  # Chip specific
> >  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> > diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
> > new file mode 100644
> > index 0000000..0aadf9d
> > --- /dev/null
> > +++ b/drivers/clk/clk-ls1x.c
> > @@ -0,0 +1,108 @@
> > +/*
> > + * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
> > + *
> > + * This program is free software; you can redistribute  it and/or
> modify it
> > + * under  the terms of  the GNU General  Public License as published by
> the
> > + * Free Software Foundation;  either version 2 of the  License, or (at
> your
> > + * option) any later version.
> > + */
> > +
> > +#include <linux/clkdev.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/io.h>
> > +#include <linux/slab.h>
> > +#include <linux/err.h>
> > +#include <asm/mach-loongson1/loongson1.h>
> > +
> > +#include <loongson1.h>
> > +
> > +#define OSC    33
> > +
> > +static DEFINE_SPINLOCK(_lock);
> > +
> > +int ls1x_pll_clk_enable(struct clk_hw *hw)
> ^^^^static
>

OK, will do.
Thanks!


> > +{
> > +       return 0;
> > +}
> > +
> > +void ls1x_pll_clk_disable(struct clk_hw *hw)
> ^^^^ also static
> > +{
> > +}
> > +
> > +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
> > +                                            unsigned long parent_rate)
> > +{
> > +       u32 pll, rate;
> > +
> > +       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
> > +       rate = ((12 + (pll & 0x3f)) * 1000000) +
> > +               ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
> > +       rate *= OSC;
> > +       rate >>= 1;
> > +
> > +       return rate;
> > +}
> > +
> > +static const struct clk_ops ls1x_pll_clk_ops = {
> > +       .enable = ls1x_pll_clk_enable,
> > +       .disable = ls1x_pll_clk_disable,
> > +       .recalc_rate = ls1x_pll_recalc_rate,
> > +};
> > +
> > +static struct clk * __init clk_register_pll(struct device *dev,
> > +        const char *name, const char *parent_name, unsigned long flags)
> > +{
> > +       struct clk_hw *hw;
> > +       struct clk *clk;
> > +       struct clk_init_data init;
> > +
> > +       /* allocate the divider */
> > +       hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
> > +       if (!hw) {
> > +               pr_err("%s: could not allocate clk_hw\n", __func__);
> > +               return ERR_PTR(-ENOMEM);
> > +       }
> > +
> > +       init.name = name;
> > +       init.ops = &ls1x_pll_clk_ops;
> > +       init.flags = flags | CLK_IS_BASIC;
> > +       init.parent_names = (parent_name ? &parent_name : NULL);
> > +       init.num_parents = (parent_name ? 1 : 0);
> > +       hw->init = &init;
> > +
> > +       /* register the clock */
> > +       clk = clk_register(dev, hw);
> > +
> > +       if (IS_ERR(clk))
> > +               kfree(hw);
> > +
> > +       return clk;
> > +}
> > +
> > +void __init ls1x_clk_init(void)
> > +{
> > +       struct clk *clk;
> > +
> > +       clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
> > +       clk_prepare_enable(clk);
> > +
> > +       clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
> > +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_CPU_SHIFT,
> > +                       DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> > +       clk_prepare_enable(clk);
> > +       clk_register_clkdev(clk, "cpu", NULL);
> > +
> > +       clk = clk_register_divider(NULL, "ddr_clk", "pll_clk",
> > +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_DDR_SHIFT,
> > +                       DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> > +       clk_prepare_enable(clk);
> > +       clk_register_clkdev(clk, "ddr", NULL);
> > +       clk_register_clkdev(clk, "stmmaceth", NULL);
> > +
> > +       clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
> > +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_DC_SHIFT,
> > +                       DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> > +       clk_prepare_enable(clk);
> > +       clk_register_clkdev(clk, "dc", NULL);
> > +       clk_register_clkdev(clk, "serial8250", NULL);
> > +}
> > --
> > 1.7.1
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel"
> in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at  http://www.tux.org/lkml/
>
> cheers,
>
> marek
>
> --
> as simple and primitive as possible
> -------------------------------------------------
> Marek Belisko - OPEN-NANDRA
> Freelance Developer
>
> Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
> Tel: +421 915 052 184
> skype: marekwhite
> twitter: #opennandra
> web: http://open-nandra.com
>



-- 
Best Regards!
Kelvin
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From steve.capper at arm.com  Mon Aug 20 04:27:07 2012
From: steve.capper at arm.com (Steve Capper)
Date: Mon, 20 Aug 2012 08:27:07 -0000
Subject: ARM hugetlb support?
Message-ID: <20120820082514.GF27631@e103986-lin>

n Mon, Aug 20, 2012 at 00:18:12AM +0100, Grazvydas Ignotas wrote:
> Hello,
Hello Grazvydas,

> I've found that hugetlb support patches have been posted some months
> ago [1]. I've been testing them with very good results [2]. Are there
> still plans to further develop them and eventually merge them?
>

We are currently working on HugeTLB and Transparent HugePage support for both
LPAE and non-LPAE memory descriptors. The non-LPAE HugeTLB patches are based
on Bill's.

I hope to get some patches out to the list soon.

-- 
Steve



From arnd at arndb.de  Tue Aug 21 11:11:29 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:11:29 -0000
Subject: [RFC 1/4] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
In-Reply-To: <1345561880-13231-1-git-send-email-arnd@arndb.de>
References: <1345561880-13231-1-git-send-email-arnd@arndb.de>
Message-ID: <1345561880-13231-2-git-send-email-arnd@arndb.de>

This is an attempt to simplify the duplicate header problem for
multiplatform kernels, in multiple steps:

1. (this patch)
   for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
   generate a arch/arm/include/generated/mach/*.h file at build time,
   same for plat-*.

2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
   arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
   arch/arm/plat-${PLAT}/include/plat/*.h to
   arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h

3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
   in all files where ${MACHINE} is known.

4. ...

5. Revert this patch again.

We can apply this patch at any time, and do step 2 at the end
of the next merge window to minimize the potential for conflicts.
We will also still need to deal with any inclusion of a mach/*
file, but out of the 6355 ones we have today, I expect only a
few hundred to remain after step 3 and they will be much easier
to spot.

I've picked the format <mach-foo/bar.h> to get a unique name because
it matches the directory name under arch/arm, but other names
would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
have been suggested previously.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Makefile          |    1 +
 arch/arm/tools/Makefile    |    5 ++++
 arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100755 arch/arm/tools/gen-headers

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..761b077 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -274,6 +274,7 @@ boot := arch/arm/boot
 
 archprepare:
 	$(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
+	$(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
 
 # Convert bzImage to zImage
 bzImage: zImage
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 635cb18..6e18ca9 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
 	@echo '  Generating $@'
 	@mkdir -p $(dir $@)
 	$(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
+
+gen_headers:
+	$(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
+
+.PHONY: gen_headers
diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
new file mode 100755
index 0000000..caa6a9a
--- /dev/null
+++ b/arch/arm/tools/gen-headers
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+SRC=$1
+OBJ=$2
+MACH=$3
+PLAT1=$4
+PLAT2=$5
+
+# create $3 to include $2 if it doesn't already have the correct
+# contents, or remove it if it's no longer needed.
+mkfile()
+{
+	if [ -e $1/$2 ] ; then
+		if [ ! -e $3 ] ; then
+			mkdir -p ${3%/*}
+			echo "#include <${2}>" > $3
+		elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
+			echo "#include <${2}>" > $3
+		fi
+	elif [ ! -e $1/$2 -a -e $3 ] ; then
+		rm -f $3
+	fi
+}
+
+# list any header files that are present in the source or
+# destination directories
+find_files()
+{
+	pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+	pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+}
+
+# process files in either mach-{MACH} or plat-${PLAT}
+mkfiles()
+{
+	mkdir -p ${OBJ}/arch/arm/include/generated/$1
+
+	FILES=`find_files $1 $2 | sort -u`
+	for i in ${FILES} ; do
+		mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
+			"${OBJ}/arch/arm/include/generated/$1/$i"
+	done
+}
+
+# always process mach-*
+mkfiles mach ${MACH}
+# process plat-* if applicable
+if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
+	mkfiles plat ${PLAT1}
+fi
+if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
+	mkfiles plat ${PLAT2}
+fi
-- 
1.7.10



From arnd at arndb.de  Tue Aug 21 11:11:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:11:56 -0000
Subject: [RFC 3/4] ARM: treewide: scripted conversion to mach-*/*.h
In-Reply-To: <1345561880-13231-1-git-send-email-arnd@arndb.de>
References: <1345561880-13231-1-git-send-email-arnd@arndb.de>
Message-ID: <1345561880-13231-4-git-send-email-arnd@arndb.de>

While converting all machine specific headers from
automatically detect the right machine and platform
name in most cases. This script uses a number of
information sources for this:

* any arch/arm/mach-*/ directory uses its own headers,
  with a few exceptions, same for plat-*/
* each mach-*/ directory belongs to at most one plat-*
  directory holding header files
* for any header below mach/* that exists in only one
  machine, we know that the users belong to that machine
* some driver directories or files are manually listed
  here.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
===========================================================

fixup()
{
 echo fixup "$1 $2 $3"
 git ls-files $1 | xargs sed -i "s:^\(#.*include <\)$2/:\1$3/:g"
}

fixup arch/arm/mach-s3c2410 mach mach-s3c24xx
fixup arch/arm/mach-s3c2412 mach mach-s3c24xx
fixup arch/arm/mach-s3c2440 mach mach-s3c24xx

fixup arch/arm/plat-mxc mach mach-imx
fixup arch/arm/plat-s3c24xx mach mach-s3c24xx
fixup arch/arm/plat-s3c24xx plat plat-samsung

for i in arch/arm/mach-*; do
	fixup "$i" mach "${i##*/}"
done

for i in arch/arm/plat-* ; do
	fixup "$i" plat "${i##*/}"
done

fixup arch/arm/mach-spear3xx plat plat-spear
fixup arch/arm/mach-spear6xx plat plat-spear
fixup arch/arm/mach-spear13xx plat plat-spear
fixup arch/arm/mach-pxa plat plat-pxa
fixup arch/arm/mach-mmp plat plat-pxa
fixup arch/arm/mach-orion5x plat plat-orion
fixup arch/arm/mach-kirkwood plat plat-orion
fixup arch/arm/mach-mv78xx0 plat plat-orion
fixup arch/arm/mach-dove plat plat-orion
fixup arch/arm/mach-nomadik plat plat-nomadik
fixup arch/arm/mach-ux500 plat plat-nomadik
fixup arch/arm/mach-s3c2410 plat plat-samsung
fixup arch/arm/mach-s3c2412 plat plat-samsung
fixup arch/arm/mach-s3c2440 plat plat-samsung
fixup arch/arm/mach-s3c24xx plat plat-samsung
fixup arch/arm/mach-s3c64xx plat plat-samsung
fixup arch/arm/mach-s5p64x0 plat plat-samsung
fixup arch/arm/mach-s5pc100 plat plat-samsung
fixup arch/arm/mach-s5pv210 plat plat-samsung
fixup arch/arm/mach-exynos plat plat-samsung
fixup arch/arm/mach-omap1 plat plat-omap
fixup arch/arm/mach-omap2 plat plat-omap
fixup arch/arm/mach-versatile plat plat-versatile
fixup arch/arm/mach-integrator plat plat-versatile
fixup arch/arm/mach-realview plat plat-versatile
fixup arch/arm/mach-vexpress plat plat-versatile
fixup arch/arm/mach-zynq plat plat-versatile

fixup drivers/video/omap plat plat-omap
fixup drivers/video/omap2 plat plat-omap
fixup drivers/video/exynos plat plat-samsung
fixup drivers/char/hw_random/omap\* plat plat-omap
fixup drivers/cpufreq/omap\* plat plat-omap
fixup drivers/crypto/omap\* plat plat-omap
fixup drivers/media/video/omap\* plat plat-omap
fixup drivers/input/keyboard/omap\* plat plat-omap
fixup drivers/mmc/host/omap\* plat plat-omap
fixup drivers/mtd/*nand/omap\* plat plat-omap
fixup drivers/spi/spi-omap\* plat plat-omap
fixup drivers/tty/serial/omap\* plat plat-omap
fixup drivers/usb/gadget/omap\* plat plat-omap
fixup drivers/usb/musb/*omap\* plat plat-omap
fixup drivers/dma/omap-dma.c plat plat-omap
fixup drivers/staging/omapdrm plat plat-omap
fixup drivers/staging/tidspbridge/ plat plat-omap
fixup drivers/input/keyboard/spear-keyboard.c plat plat-spear
fixup drivers/cpufreq/exynos-cpufreq.c plat plat-samsung
fixup drivers/crypto/s5p-sss.c plat plat-samsung
fixup drivers/i2c/busses/i2c-nomadik.c plat plat-nomadik
fixup drivers/mtd/nand/s3c2410.c plat plat-samsung
fixup drivers/tty/serial/samsung.c plat plat-samsung
fixup drivers/usb/gadget/s3c-hsotg.c plat plat-samsung
fixup drivers/gpio/gpio-samsung.c plat plat-samsung
fixup sound/soc/samsung plat plat-samsung
fixup sound/soc/omap plat plat-omap
fixup sound/soc/pxa plat plat-pxa
fixup sound/soc/kirkwood/ plat plat-orion
fixup sound/soc/fsl/imx*.[ch] plat plat-mxc

fixup drivers/video/omap mach mach-omap1
fixup drivers/video/omap2 mach mach-omap2
fixup drivers/video/exynos mach mach-exynos
fixup drivers/media/video/davinci mach mach-davinci

fixup sound/soc/omap/osk5912.c mach mach-omap1
fixup sound/soc/omap mach mach-omap2
fixup sound/soc/pxa mach mach-pxa
fixup sound/soc/davinci mach mach-davinci
fixup sound/soc/ep93xx mach mach-ep93xx
fixup sound/soc/kirkwood/ mach mach-kirkwood
fixup sound/soc/fsl/imx*.[ch] mach mach-imx
fixup sound/soc/mxs mach mach-mxs
fixup sound/soc/tegra mach mach-tegra
fixup sound/soc/nuc900 mach mach-w90x900
fixup sound/arm/pxa\* mach mach-pxa
fixup sound/atmel/ac97c.c mach mach-at91
fixup sound/oss/waveartist.c mach mach-footbridge
fixup sound/oss/vidc\* mach mach-rpc
fixup sound/soc/atmel/ mach mach-at91
fixup sound/soc/ux500/ mach mach-ux500

fixup include/linux/spi/pxa2xx_spi.h mach mach-pxa
fixup include/linux/mfd/dbx500-prcmu.h mach mach-ux500

find_unique_mach()
{
  {
    # find files in other architectures using mach/*.h
    git ls-files | grep /mach/[^/]*.h | while read i ;
	do echo ${i##*/}
    done
    # find files we've already renamed in ARM
    for i in arch/arm/mach-*/include/mach-*/ ; do
	git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_mach()
{
  ALLFILES=`git grep -l "^#include.*<mach/"`
  ALLINCLUDES=`git grep "^#include.*<mach/" ${ALLFILES}`
  find_unique_mach | while read i ; do
    echo "$ALLINCLUDES" | if grep -q "#include.*<mach/$i>" &&
		[ -e arch/arm/mach-*/include/mach-*/"$i" ] ; then
       MACH=`ls arch/arm/mach-*/include/mach-*/$i | cut -f 3 -d /`
       THESEFILES=`git grep -l "^#include.*<mach/$i>" ${ALLFILES}`
       echo mach/$i
       for j in ${THESEFILES} ; do
	  fixup $j mach ${MACH}
       done
    fi
  done
}

find_unique_plat()
{
  {
    # all plat/*.h files are already renamed
    for i in arch/arm/plat-*/include/plat-*/ ; do
	git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_plat()
{
  ALLFILES=`git grep -l "#include.*<plat/"`
  if [ "" != "${ALLFILES}" ] ; then
    find_unique_plat | while read i ; do
      PLAT=`ls arch/arm/plat-*/include/plat-*/$i | cut -f 3 -d /`
      THESEFILES=`git grep -l "^#include.*<plat/$i>" ${ALLFILES}`
      echo plat/$i
       for j in ${THESEFILES} ; do
          fixup $j plat ${PLAT}
       done
    done
  fi
}

rename_unique_mach
rename_unique_plat# Please enter the commit message for your changes. Lines starting
---
 Documentation/spi/ep93xx_spi                       |    2 +-
 arch/arm/boot/compressed/head-shmobile.S           |    2 +-
 arch/arm/boot/compressed/sdhi-shmobile.c           |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |   10 ++--
 arch/arm/mach-at91/at91rm9200_devices.c            |    8 ++--
 arch/arm/mach-at91/at91rm9200_time.c               |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |   12 ++---
 arch/arm/mach-at91/at91sam9260_devices.c           |   14 +++---
 arch/arm/mach-at91/at91sam9261.c                   |   10 ++--
 arch/arm/mach-at91/at91sam9261_devices.c           |   10 ++--
 arch/arm/mach-at91/at91sam9263.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9263_devices.c           |   10 ++--
 arch/arm/mach-at91/at91sam926x_time.c              |    2 +-
 arch/arm/mach-at91/at91sam9_alt_reset.S            |    6 +--
 arch/arm/mach-at91/at91sam9g45.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9g45_devices.c           |   16 +++----
 arch/arm/mach-at91/at91sam9g45_reset.S             |    6 +--
 arch/arm/mach-at91/at91sam9n12.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9rl.c                    |   12 ++---
 arch/arm/mach-at91/at91sam9rl_devices.c            |   12 ++---
 arch/arm/mach-at91/at91sam9x5.c                    |    8 ++--
 arch/arm/mach-at91/at91x40.c                       |    8 ++--
 arch/arm/mach-at91/at91x40_time.c                  |    4 +-
 arch/arm/mach-at91/board-1arm.c                    |    8 ++--
 arch/arm/mach-at91/board-afeb-9260v1.c             |    6 +--
 arch/arm/mach-at91/board-cam60.c                   |    8 ++--
 arch/arm/mach-at91/board-carmeva.c                 |    6 +--
 arch/arm/mach-at91/board-cpu9krea.c                |   12 ++---
 arch/arm/mach-at91/board-cpuat91.c                 |   12 ++---
 arch/arm/mach-at91/board-csb337.c                  |    6 +--
 arch/arm/mach-at91/board-csb637.c                  |    6 +--
 arch/arm/mach-at91/board-dt.c                      |    4 +-
 arch/arm/mach-at91/board-eb01.c                    |    6 +--
 arch/arm/mach-at91/board-eb9200.c                  |    6 +--
 arch/arm/mach-at91/board-ecbat91.c                 |    8 ++--
 arch/arm/mach-at91/board-eco920.c                  |   10 ++--
 arch/arm/mach-at91/board-flexibity.c               |    6 +--
 arch/arm/mach-at91/board-foxg20.c                  |    8 ++--
 arch/arm/mach-at91/board-gsia18s.c                 |   10 ++--
 arch/arm/mach-at91/board-kafa.c                    |    8 ++--
 arch/arm/mach-at91/board-kb9202.c                  |   12 ++---
 arch/arm/mach-at91/board-neocore926.c              |    8 ++--
 arch/arm/mach-at91/board-pcontrol-g20.c            |    8 ++--
 arch/arm/mach-at91/board-picotux200.c              |   10 ++--
 arch/arm/mach-at91/board-qil-a9260.c               |   10 ++--
 arch/arm/mach-at91/board-rm9200dk.c                |   10 ++--
 arch/arm/mach-at91/board-rm9200ek.c                |   10 ++--
 arch/arm/mach-at91/board-rsi-ews.c                 |    6 +--
 arch/arm/mach-at91/board-sam9-l9260.c              |    8 ++--
 arch/arm/mach-at91/board-sam9260ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9261ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9263ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9g20ek.c               |   10 ++--
 arch/arm/mach-at91/board-sam9m10g45ek.c            |   12 ++---
 arch/arm/mach-at91/board-sam9rlek.c                |   10 ++--
 arch/arm/mach-at91/board-snapper9260.c             |    8 ++--
 arch/arm/mach-at91/board-stamp9g20.c               |    6 +--
 arch/arm/mach-at91/board-usb-a926x.c               |   10 ++--
 arch/arm/mach-at91/board-yl-9200.c                 |   12 ++---
 arch/arm/mach-at91/clock.c                         |    6 +--
 arch/arm/mach-at91/cpuidle.c                       |    2 +-
 arch/arm/mach-at91/gpio.c                          |    4 +-
 arch/arm/mach-at91/include/mach-at91/at91_ramc.h   |    6 +--
 .../arm/mach-at91/include/mach-at91/at91sam9_smc.h |    2 +-
 arch/arm/mach-at91/include/mach-at91/atmel-mci.h   |    2 +-
 arch/arm/mach-at91/include/mach-at91/debug-macro.S |    4 +-
 arch/arm/mach-at91/include/mach-at91/hardware.h    |   18 ++++----
 arch/arm/mach-at91/include/mach-at91/memory.h      |    2 +-
 arch/arm/mach-at91/include/mach-at91/timex.h       |    2 +-
 arch/arm/mach-at91/include/mach-at91/uncompress.h  |    6 +--
 arch/arm/mach-at91/irq.c                           |    4 +-
 arch/arm/mach-at91/leds.c                          |    2 +-
 arch/arm/mach-at91/pm.c                            |   10 ++--
 arch/arm/mach-at91/pm.h                            |    4 +-
 arch/arm/mach-at91/pm_slowclock.S                  |    6 +--
 arch/arm/mach-at91/sam9_smc.c                      |    2 +-
 arch/arm/mach-at91/setup.c                         |   10 ++--
 arch/arm/mach-bcmring/arch.c                       |   10 ++--
 arch/arm/mach-bcmring/clock.c                      |    8 ++--
 arch/arm/mach-bcmring/clock.h                      |    2 +-
 arch/arm/mach-bcmring/core.c                       |   10 ++--
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |    2 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |    6 +--
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      |    4 +-
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |    2 +-
 arch/arm/mach-bcmring/dma.c                        |    4 +-
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/intcHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/reg.h            |    2 +-
 .../include/mach-bcmring/csp/cap_inline.h          |    2 +-
 .../include/mach-bcmring/csp/chipcHw_def.h         |    2 +-
 .../include/mach-bcmring/csp/chipcHw_inline.h      |    4 +-
 .../include/mach-bcmring/csp/chipcHw_reg.h         |    4 +-
 .../include/mach-bcmring/csp/ddrcReg.h             |    2 +-
 .../include/mach-bcmring/csp/dmacHw_reg.h          |    2 +-
 .../mach-bcmring/include/mach-bcmring/csp/hw_cfg.h |    4 +-
 .../include/mach-bcmring/csp/intcHw_reg.h          |    2 +-
 .../mach-bcmring/include/mach-bcmring/csp/mm_io.h  |    2 +-
 .../include/mach-bcmring/csp/secHw_def.h           |    4 +-
 .../include/mach-bcmring/csp/tmrHw_reg.h           |    4 +-
 arch/arm/mach-bcmring/include/mach-bcmring/dma.h   |    2 +-
 .../include/mach-bcmring/entry-macro.S             |    6 +--
 .../mach-bcmring/include/mach-bcmring/hardware.h   |    2 +-
 .../mach-bcmring/include/mach-bcmring/reg_nand.h   |    2 +-
 .../mach-bcmring/include/mach-bcmring/reg_umi.h    |    2 +-
 .../mach-bcmring/include/mach-bcmring/uncompress.h |    2 +-
 arch/arm/mach-bcmring/irq.c                        |    6 +--
 arch/arm/mach-bcmring/mm.c                         |    4 +-
 arch/arm/mach-bcmring/timer.c                      |    2 +-
 arch/arm/mach-clps711x/autcpu12.c                  |    4 +-
 arch/arm/mach-clps711x/cdb89712.c                  |    2 +-
 arch/arm/mach-clps711x/ceiva.c                     |    2 +-
 arch/arm/mach-clps711x/common.c                    |    2 +-
 arch/arm/mach-clps711x/edb7211-mm.c                |    2 +-
 arch/arm/mach-clps711x/fortunet.c                  |    2 +-
 .../include/mach-clps711x/debug-macro.S            |    2 +-
 .../include/mach-clps711x/entry-macro.S            |    2 +-
 .../mach-clps711x/include/mach-clps711x/hardware.h |    2 +-
 .../include/mach-clps711x/uncompress.h             |    2 +-
 arch/arm/mach-clps711x/p720t-leds.c                |    2 +-
 arch/arm/mach-clps711x/p720t.c                     |    4 +-
 arch/arm/mach-cns3xxx/cns3420vb.c                  |    4 +-
 arch/arm/mach-cns3xxx/core.c                       |    2 +-
 arch/arm/mach-cns3xxx/devices.c                    |    6 +--
 arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h  |    2 +-
 .../mach-cns3xxx/include/mach-cns3xxx/uncompress.h |    2 +-
 arch/arm/mach-cns3xxx/pcie.c                       |    2 +-
 arch/arm/mach-cns3xxx/pm.c                         |    4 +-
 arch/arm/mach-davinci/aemif.c                      |    2 +-
 arch/arm/mach-davinci/board-da830-evm.c            |   14 +++---
 arch/arm/mach-davinci/board-da850-evm.c            |   12 ++---
 arch/arm/mach-davinci/board-dm355-evm.c            |   10 ++--
 arch/arm/mach-davinci/board-dm355-leopard.c        |   10 ++--
 arch/arm/mach-davinci/board-dm365-evm.c            |   14 +++---
 arch/arm/mach-davinci/board-dm644x-evm.c           |   16 +++----
 arch/arm/mach-davinci/board-dm646x-evm.c           |   14 +++---
 arch/arm/mach-davinci/board-mityomapl138.c         |   12 ++---
 arch/arm/mach-davinci/board-neuros-osd2.c          |   14 +++---
 arch/arm/mach-davinci/board-omapl138-hawk.c        |    6 +--
 arch/arm/mach-davinci/board-sffsdr.c               |   10 ++--
 arch/arm/mach-davinci/board-tnetv107x-evm.c        |   10 ++--
 arch/arm/mach-davinci/cdce949.c                    |    4 +-
 arch/arm/mach-davinci/clock.c                      |    8 ++--
 arch/arm/mach-davinci/common.c                     |    4 +-
 arch/arm/mach-davinci/cp_intc.c                    |    4 +-
 arch/arm/mach-davinci/cpufreq.c                    |    6 +--
 arch/arm/mach-davinci/cpuidle.c                    |    4 +-
 arch/arm/mach-davinci/da830.c                      |   14 +++---
 arch/arm/mach-davinci/da850.c                      |   18 ++++----
 arch/arm/mach-davinci/davinci.h                    |    6 +--
 arch/arm/mach-davinci/devices-da8xx.c              |   10 ++--
 arch/arm/mach-davinci/devices-tnetv107x.c          |    8 ++--
 arch/arm/mach-davinci/devices.c                    |   16 +++----
 arch/arm/mach-davinci/dm355.c                      |   22 ++++-----
 arch/arm/mach-davinci/dm365.c                      |   24 +++++-----
 arch/arm/mach-davinci/dm644x.c                     |   20 ++++----
 arch/arm/mach-davinci/dm646x.c                     |   20 ++++----
 arch/arm/mach-davinci/dma.c                        |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/asp.h   |    4 +-
 .../mach-davinci/include/mach-davinci/cdce949.h    |    2 +-
 .../mach-davinci/include/mach-davinci/cputype.h    |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/da8xx.h |   16 +++----
 .../include/mach-davinci/debug-macro.S             |    2 +-
 .../include/mach-davinci/entry-macro.S             |    2 +-
 .../include/mach-davinci/gpio-davinci.h            |    4 +-
 .../arm/mach-davinci/include/mach-davinci/serial.h |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/spi.h   |    2 +-
 .../mach-davinci/include/mach-davinci/tnetv107x.h  |    6 +--
 .../mach-davinci/include/mach-davinci/uncompress.h |    2 +-
 arch/arm/mach-davinci/irq.c                        |    6 +--
 arch/arm/mach-davinci/mux.c                        |    4 +-
 arch/arm/mach-davinci/mux.h                        |    2 +-
 arch/arm/mach-davinci/pm.c                         |    6 +--
 arch/arm/mach-davinci/psc.c                        |    4 +-
 arch/arm/mach-davinci/serial.c                     |    4 +-
 arch/arm/mach-davinci/sleep.S                      |    4 +-
 arch/arm/mach-davinci/sram.c                       |    4 +-
 arch/arm/mach-davinci/time.c                       |    6 +--
 arch/arm/mach-davinci/tnetv107x.c                  |   18 ++++----
 arch/arm/mach-davinci/usb.c                        |    8 ++--
 arch/arm/mach-dove/addr-map.c                      |    4 +-
 arch/arm/mach-dove/cm-a510.c                       |    2 +-
 arch/arm/mach-dove/common.c                        |   12 ++---
 arch/arm/mach-dove/dove-db-setup.c                 |    2 +-
 arch/arm/mach-dove/include/mach-dove/bridge-regs.h |    2 +-
 arch/arm/mach-dove/include/mach-dove/debug-macro.S |    2 +-
 arch/arm/mach-dove/include/mach-dove/entry-macro.S |    2 +-
 arch/arm/mach-dove/include/mach-dove/gpio.h        |    2 +-
 arch/arm/mach-dove/include/mach-dove/pm.h          |    2 +-
 arch/arm/mach-dove/include/mach-dove/uncompress.h  |    2 +-
 arch/arm/mach-dove/irq.c                           |    6 +--
 arch/arm/mach-dove/mpp.c                           |    4 +-
 arch/arm/mach-dove/pcie.c                          |    8 ++--
 arch/arm/mach-ebsa110/core.c                       |    2 +-
 arch/arm/mach-ebsa110/io.c                         |    2 +-
 arch/arm/mach-ebsa110/leds.c                       |    2 +-
 arch/arm/mach-ep93xx/adssphere.c                   |    2 +-
 arch/arm/mach-ep93xx/clock.c                       |    2 +-
 arch/arm/mach-ep93xx/core.c                        |   10 ++--
 arch/arm/mach-ep93xx/crunch-bits.S                 |    2 +-
 arch/arm/mach-ep93xx/dma.c                         |    4 +-
 arch/arm/mach-ep93xx/edb93xx.c                     |    8 ++--
 arch/arm/mach-ep93xx/gesbc9312.c                   |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/debug-macro.S  |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/gpio-ep93xx.h  |    2 +-
 .../arm/mach-ep93xx/include/mach-ep93xx/hardware.h |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/uncompress.h   |    2 +-
 arch/arm/mach-ep93xx/micro9.c                      |    2 +-
 arch/arm/mach-ep93xx/simone.c                      |    6 +--
 arch/arm/mach-ep93xx/snappercl15.c                 |    6 +--
 arch/arm/mach-ep93xx/soc.h                         |    2 +-
 arch/arm/mach-ep93xx/ts72xx.c                      |    4 +-
 arch/arm/mach-ep93xx/vision_ep9307.c               |    8 ++--
 arch/arm/mach-exynos/clock-exynos4.c               |   22 ++++-----
 arch/arm/mach-exynos/clock-exynos4210.c            |   24 +++++-----
 arch/arm/mach-exynos/clock-exynos4212.c            |   24 +++++-----
 arch/arm/mach-exynos/clock-exynos5.c               |   22 ++++-----
 arch/arm/mach-exynos/common.c                      |   34 +++++++-------
 arch/arm/mach-exynos/cpuidle.c                     |    6 +--
 arch/arm/mach-exynos/dev-ahci.c                    |    8 ++--
 arch/arm/mach-exynos/dev-audio.c                   |   12 ++---
 arch/arm/mach-exynos/dev-drm.c                     |    2 +-
 arch/arm/mach-exynos/dev-dwmci.c                   |    4 +-
 arch/arm/mach-exynos/dev-ohci.c                    |   10 ++--
 arch/arm/mach-exynos/dev-sysmmu.c                  |    8 ++--
 arch/arm/mach-exynos/dev-uart.c                    |    6 +--
 arch/arm/mach-exynos/dma.c                         |   12 ++---
 arch/arm/mach-exynos/hotplug.c                     |    2 +-
 .../mach-exynos/include/mach-exynos/debug-macro.S  |    4 +-
 arch/arm/mach-exynos/include/mach-exynos/dma.h     |    2 +-
 arch/arm/mach-exynos/include/mach-exynos/irqs.h    |    2 +-
 arch/arm/mach-exynos/include/mach-exynos/map.h     |    4 +-
 arch/arm/mach-exynos/include/mach-exynos/pm-core.h |    2 +-
 .../mach-exynos/include/mach-exynos/regs-clock.h   |    6 +--
 .../mach-exynos/include/mach-exynos/regs-gpio.h    |    4 +-
 .../arm/mach-exynos/include/mach-exynos/regs-irq.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-mct.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-mem.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-pmu.h |    2 +-
 .../mach-exynos/include/mach-exynos/uncompress.h   |    4 +-
 arch/arm/mach-exynos/mach-armlex4210.c             |   16 +++----
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    6 +--
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 +--
 arch/arm/mach-exynos/mach-nuri.c                   |   34 +++++++-------
 arch/arm/mach-exynos/mach-origen.c                 |   30 ++++++------
 arch/arm/mach-exynos/mach-smdk4x12.c               |   28 ++++++------
 arch/arm/mach-exynos/mach-smdkv310.c               |   34 +++++++-------
 arch/arm/mach-exynos/mach-universal_c210.c         |   32 ++++++-------
 arch/arm/mach-exynos/mct.c                         |    8 ++--
 arch/arm/mach-exynos/platsmp.c                     |    8 ++--
 arch/arm/mach-exynos/pm.c                          |   22 ++++-----
 arch/arm/mach-exynos/pm_domains.c                  |    4 +-
 arch/arm/mach-exynos/pmu.c                         |    4 +-
 arch/arm/mach-exynos/setup-fimc.c                  |    4 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    6 +--
 arch/arm/mach-exynos/setup-i2c0.c                  |    6 +--
 arch/arm/mach-exynos/setup-i2c1.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c2.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c3.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c4.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c5.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c6.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c7.c                  |    4 +-
 arch/arm/mach-exynos/setup-keypad.c                |    2 +-
 arch/arm/mach-exynos/setup-sdhci-gpio.c            |    6 +--
 arch/arm/mach-exynos/setup-spi.c                   |    2 +-
 arch/arm/mach-exynos/setup-usb-phy.c               |    8 ++--
 arch/arm/mach-footbridge/ebsa285-leds.c            |    2 +-
 .../include/mach-footbridge/debug-macro.S          |    2 +-
 .../include/mach-footbridge/entry-macro.S          |    4 +-
 arch/arm/mach-footbridge/isa-irq.c                 |    2 +-
 arch/arm/mach-footbridge/netwinder-leds.c          |    2 +-
 arch/arm/mach-gemini/board-nas4220b.c              |    4 +-
 arch/arm/mach-gemini/devices.c                     |    6 +--
 arch/arm/mach-gemini/gpio.c                        |    4 +-
 .../mach-gemini/include/mach-gemini/debug-macro.S  |    2 +-
 .../mach-gemini/include/mach-gemini/entry-macro.S  |    2 +-
 arch/arm/mach-gemini/include/mach-gemini/gpio.h    |    2 +-
 arch/arm/mach-gemini/include/mach-gemini/system.h  |    4 +-
 .../mach-gemini/include/mach-gemini/uncompress.h   |    2 +-
 arch/arm/mach-gemini/irq.c                         |    2 +-
 arch/arm/mach-gemini/mm.c                          |    2 +-
 arch/arm/mach-gemini/time.c                        |    4 +-
 arch/arm/mach-h720x/common.c                       |    4 +-
 arch/arm/mach-h720x/cpu-h7201.c                    |    4 +-
 arch/arm/mach-h720x/cpu-h7202.c                    |    4 +-
 arch/arm/mach-h720x/h7201-eval.c                   |    2 +-
 arch/arm/mach-h720x/h7202-eval.c                   |    4 +-
 .../mach-h720x/include/mach-h720x/debug-macro.S    |    2 +-
 .../arm/mach-h720x/include/mach-h720x/uncompress.h |    2 +-
 arch/arm/mach-imx/clk-imx1.c                       |    4 +-
 arch/arm/mach-imx/clk-imx21.c                      |    4 +-
 arch/arm/mach-imx/clk-imx25.c                      |    6 +--
 arch/arm/mach-imx/clk-imx27.c                      |    4 +-
 arch/arm/mach-imx/clk-imx31.c                      |    6 +--
 arch/arm/mach-imx/clk-imx35.c                      |    4 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |    4 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    2 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    6 +--
 arch/arm/mach-imx/clk.h                            |    2 +-
 arch/arm/mach-imx/cpu-imx25.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    6 +--
 arch/arm/mach-imx/cpu-imx35.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    2 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    2 +-
 arch/arm/mach-imx/devices-imx1.h                   |    4 +-
 arch/arm/mach-imx/devices-imx21.h                  |    4 +-
 arch/arm/mach-imx/devices-imx25.h                  |    4 +-
 arch/arm/mach-imx/devices-imx27.h                  |    4 +-
 arch/arm/mach-imx/devices-imx31.h                  |    4 +-
 arch/arm/mach-imx/devices-imx35.h                  |    4 +-
 arch/arm/mach-imx/devices-imx50.h                  |    4 +-
 arch/arm/mach-imx/devices-imx51.h                  |    4 +-
 arch/arm/mach-imx/devices-imx53.h                  |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    6 +--
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 ++--
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    6 +--
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    6 +--
 arch/arm/mach-imx/hotplug.c                        |    2 +-
 arch/arm/mach-imx/imx27-dt.c                       |    4 +-
 arch/arm/mach-imx/imx31-dt.c                       |    4 +-
 arch/arm/mach-imx/imx51-dt.c                       |    4 +-
 arch/arm/mach-imx/imx53-dt.c                       |    4 +-
 arch/arm/mach-imx/include/mach-imx/debug-macro.S   |    2 +-
 .../arm/mach-imx/include/mach-imx/devices-common.h |   32 ++++++-------
 arch/arm/mach-imx/include/mach-imx/dma-mx1-mx2.h   |    2 +-
 arch/arm/mach-imx/include/mach-imx/hardware.h      |   26 +++++------
 arch/arm/mach-imx/include/mach-imx/iomux-mx1.h     |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx21.h    |    4 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx25.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx27.h    |    4 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx35.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx50.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx51.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx53.h    |    2 +-
 arch/arm/mach-imx/iomux-imx31.c                    |    4 +-
 arch/arm/mach-imx/lluart.c                         |    2 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    6 +--
 arch/arm/mach-imx/mach-armadillo5x0.c              |    8 ++--
 arch/arm/mach-imx/mach-bug.c                       |    6 +--
 arch/arm/mach-imx/mach-cpuimx27.c                  |   10 ++--
 arch/arm/mach-imx/mach-cpuimx35.c                  |    8 ++--
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    8 ++--
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 ++--
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    6 +--
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +--
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +--
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +--
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    8 ++--
 arch/arm/mach-imx/mach-mx1ads.c                    |    6 +--
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +--
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +--
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx31ads.c                   |    4 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   10 ++--
 arch/arm/mach-imx/mach-mx31lite.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx31moboard.c               |   12 ++---
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    6 +--
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx51_babbage.c              |    6 +--
 arch/arm/mach-imx/mach-mx51_efikamx.c              |    6 +--
 arch/arm/mach-imx/mach-mx51_efikasb.c              |    8 ++--
 arch/arm/mach-imx/mach-mx53_ard.c                  |    6 +--
 arch/arm/mach-imx/mach-mx53_evk.c                  |    6 +--
 arch/arm/mach-imx/mach-mx53_loco.c                 |    6 +--
 arch/arm/mach-imx/mach-mx53_smd.c                  |    6 +--
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +--
 arch/arm/mach-imx/mach-pca100.c                    |    8 ++--
 arch/arm/mach-imx/mach-pcm037.c                    |    8 ++--
 arch/arm/mach-imx/mach-pcm037_eet.c                |    4 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   10 ++--
 arch/arm/mach-imx/mach-pcm043.c                    |    8 ++--
 arch/arm/mach-imx/mach-qong.c                      |    6 +--
 arch/arm/mach-imx/mach-scb9328.c                   |    6 +--
 arch/arm/mach-imx/mach-vpr200.c                    |    6 +--
 arch/arm/mach-imx/mm-imx1.c                        |    6 +--
 arch/arm/mach-imx/mm-imx21.c                       |    8 ++--
 arch/arm/mach-imx/mm-imx25.c                       |   10 ++--
 arch/arm/mach-imx/mm-imx27.c                       |    8 ++--
 arch/arm/mach-imx/mm-imx3.c                        |    8 ++--
 arch/arm/mach-imx/mm-imx5.c                        |    8 ++--
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |    2 +-
 arch/arm/mach-imx/mx31lilly-db.c                   |    8 ++--
 arch/arm/mach-imx/mx31lite-db.c                    |    8 ++--
 arch/arm/mach-imx/mx31moboard-devboard.c           |    8 ++--
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    8 ++--
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   10 ++--
 arch/arm/mach-imx/mx51_efika.c                     |    8 ++--
 arch/arm/mach-imx/pcm970-baseboard.c               |    6 +--
 arch/arm/mach-imx/platsmp.c                        |    4 +-
 arch/arm/mach-imx/pm-imx27.c                       |    2 +-
 arch/arm/mach-imx/pm-imx3.c                        |    6 +--
 arch/arm/mach-imx/pm-imx5.c                        |    6 +--
 arch/arm/mach-imx/pm-imx6q.c                       |    4 +-
 arch/arm/mach-integrator/core.c                    |    8 ++--
 arch/arm/mach-integrator/cpu.c                     |    4 +-
 arch/arm/mach-integrator/impd1.c                   |    4 +-
 arch/arm/mach-integrator/integrator_ap.c           |   10 ++--
 arch/arm/mach-integrator/integrator_cp.c           |   16 +++----
 arch/arm/mach-integrator/leds.c                    |    6 +--
 arch/arm/mach-integrator/lm.c                      |    2 +-
 arch/arm/mach-integrator/pci.c                     |    2 +-
 arch/arm/mach-integrator/pci_v3.c                  |    6 +--
 arch/arm/mach-iop13xx/include/mach-iop13xx/adma.h  |    2 +-
 .../arm/mach-iop13xx/include/mach-iop13xx/memory.h |    2 +-
 arch/arm/mach-iop13xx/include/mach-iop13xx/pci.h   |    2 +-
 .../mach-iop13xx/include/mach-iop13xx/uncompress.h |    2 +-
 arch/arm/mach-iop13xx/io.c                         |    2 +-
 arch/arm/mach-iop13xx/iq81340mc.c                  |    6 +--
 arch/arm/mach-iop13xx/iq81340sc.c                  |    6 +--
 arch/arm/mach-iop13xx/irq.c                        |    6 +--
 arch/arm/mach-iop13xx/pci.c                        |    4 +-
 arch/arm/mach-iop13xx/setup.c                      |    2 +-
 arch/arm/mach-iop32x/em7210.c                      |    4 +-
 arch/arm/mach-iop32x/glantank.c                    |    4 +-
 .../mach-iop32x/include/mach-iop32x/entry-macro.S  |    2 +-
 .../mach-iop32x/include/mach-iop32x/uncompress.h   |    2 +-
 arch/arm/mach-iop32x/iq31244.c                     |    4 +-
 arch/arm/mach-iop32x/iq80321.c                     |    4 +-
 arch/arm/mach-iop32x/irq.c                         |    2 +-
 arch/arm/mach-iop32x/n2100.c                       |    4 +-
 .../mach-iop33x/include/mach-iop33x/entry-macro.S  |    2 +-
 .../mach-iop33x/include/mach-iop33x/uncompress.h   |    2 +-
 arch/arm/mach-iop33x/iq80331.c                     |    4 +-
 arch/arm/mach-iop33x/iq80332.c                     |    4 +-
 arch/arm/mach-iop33x/irq.c                         |    2 +-
 arch/arm/mach-iop33x/uart.c                        |    2 +-
 arch/arm/mach-ixp4xx/avila-pci.c                   |    2 +-
 arch/arm/mach-ixp4xx/avila-setup.c                 |    2 +-
 arch/arm/mach-ixp4xx/common-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/common.c                      |    6 +--
 arch/arm/mach-ixp4xx/coyote-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/coyote-setup.c                |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-pci.c             |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-setup.c           |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-setup.c              |    2 +-
 .../mach-ixp4xx/include/mach-ixp4xx/entry-macro.S  |    2 +-
 .../arm/mach-ixp4xx/include/mach-ixp4xx/hardware.h |    2 +-
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/io.h      |    2 +-
 .../arm/mach-ixp4xx/include/mach-ixp4xx/platform.h |    2 +-
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/timex.h   |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-setup.c               |    2 +-
 arch/arm/mach-ixp4xx/ixdpg425-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_npe.c                  |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_qmgr.c                 |    2 +-
 arch/arm/mach-ixp4xx/miccpt-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-setup.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |    4 +-
 arch/arm/mach-kirkwood/board-dnskw.c               |    4 +-
 arch/arm/mach-kirkwood/board-dreamplug.c           |    6 +--
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    6 +--
 arch/arm/mach-kirkwood/board-ib62x0.c              |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c            |    2 +-
 arch/arm/mach-kirkwood/board-lsxl.c                |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c               |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   22 ++++-----
 arch/arm/mach-kirkwood/cpuidle.c                   |    2 +-
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    4 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    4 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    4 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    4 +-
 .../include/mach-kirkwood/bridge-regs.h            |    2 +-
 .../include/mach-kirkwood/debug-macro.S            |    2 +-
 .../include/mach-kirkwood/entry-macro.S            |    2 +-
 .../arm/mach-kirkwood/include/mach-kirkwood/gpio.h |    2 +-
 .../include/mach-kirkwood/uncompress.h             |    2 +-
 arch/arm/mach-kirkwood/irq.c                       |    4 +-
 arch/arm/mach-kirkwood/lacie_v2-common.c           |    6 +--
 arch/arm/mach-kirkwood/mpp.c                       |    4 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c     |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    4 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    4 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    4 +-
 arch/arm/mach-kirkwood/pcie.c                      |    6 +--
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c       |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    4 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    4 +-
 arch/arm/mach-kirkwood/t5325-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c               |    4 +-
 arch/arm/mach-kirkwood/tsx1x-common.c              |    2 +-
 arch/arm/mach-ks8695/board-acs5k.c                 |    4 +-
 arch/arm/mach-ks8695/board-dsm320.c                |    4 +-
 arch/arm/mach-ks8695/board-micrel.c                |    4 +-
 arch/arm/mach-ks8695/cpu.c                         |    6 +--
 arch/arm/mach-ks8695/devices.c                     |   12 ++---
 .../mach-ks8695/include/mach-ks8695/debug-macro.S  |    4 +-
 .../mach-ks8695/include/mach-ks8695/entry-macro.S  |    4 +-
 arch/arm/mach-ks8695/include/mach-ks8695/memory.h  |    2 +-
 arch/arm/mach-ks8695/include/mach-ks8695/timex.h   |    2 +-
 .../mach-ks8695/include/mach-ks8695/uncompress.h   |    2 +-
 arch/arm/mach-ks8695/irq.c                         |    6 +--
 arch/arm/mach-ks8695/leds.c                        |    2 +-
 arch/arm/mach-ks8695/pci.c                         |    6 +--
 arch/arm/mach-ks8695/time.c                        |    4 +-
 arch/arm/mach-lpc32xx/clock.c                      |    4 +-
 arch/arm/mach-lpc32xx/common.c                     |    4 +-
 arch/arm/mach-lpc32xx/common.h                     |    2 +-
 .../include/mach-lpc32xx/entry-macro.S             |    4 +-
 .../mach-lpc32xx/include/mach-lpc32xx/uncompress.h |    4 +-
 arch/arm/mach-lpc32xx/irq.c                        |    6 +--
 arch/arm/mach-lpc32xx/phy3250.c                    |    8 ++--
 arch/arm/mach-lpc32xx/pm.c                         |    4 +-
 arch/arm/mach-lpc32xx/serial.c                     |    4 +-
 arch/arm/mach-lpc32xx/suspend.S                    |    4 +-
 arch/arm/mach-lpc32xx/timer.c                      |    4 +-
 arch/arm/mach-mmp/aspenite.c                       |   10 ++--
 arch/arm/mach-mmp/avengers_lite.c                  |    8 ++--
 arch/arm/mach-mmp/brownstone.c                     |    8 ++--
 arch/arm/mach-mmp/clock.c                          |    2 +-
 arch/arm/mach-mmp/common.c                         |    4 +-
 arch/arm/mach-mmp/devices.c                        |    8 ++--
 arch/arm/mach-mmp/flint.c                          |    8 ++--
 arch/arm/mach-mmp/gplugd.c                         |    6 +--
 arch/arm/mach-mmp/include/mach-mmp/debug-macro.S   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/dma.h           |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/entry-macro.S   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/gpio.h          |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-mmp2.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa168.h    |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa910.h    |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp.h           |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mmp2.h          |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/pm-mmp2.h       |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/pxa168.h        |    8 ++--
 arch/arm/mach-mmp/include/mach-mmp/pxa910.h        |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-apbc.h     |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-apmu.h     |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-icu.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-rtc.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-smc.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-timers.h   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/uncompress.h    |    2 +-
 arch/arm/mach-mmp/irq.c                            |    6 +--
 arch/arm/mach-mmp/jasper.c                         |    8 ++--
 arch/arm/mach-mmp/mmp-dt.c                         |    2 +-
 arch/arm/mach-mmp/mmp2-dt.c                        |    4 +-
 arch/arm/mach-mmp/mmp2.c                           |   18 ++++----
 arch/arm/mach-mmp/pm-mmp2.c                        |   12 ++---
 arch/arm/mach-mmp/pm-pxa910.c                      |   12 ++---
 arch/arm/mach-mmp/pxa168.c                         |   20 ++++----
 arch/arm/mach-mmp/pxa910.c                         |   16 +++----
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mmp/tavorevb.c                       |    8 ++--
 arch/arm/mach-mmp/teton_bga.c                      |   12 ++---
 arch/arm/mach-mmp/time.c                           |   10 ++--
 arch/arm/mach-mmp/ttc_dkb.c                        |   10 ++--
 arch/arm/mach-msm/acpuclock-arm11.c                |    4 +-
 arch/arm/mach-msm/board-halibut.c                  |    8 ++--
 arch/arm/mach-msm/board-mahimahi.c                 |    6 +--
 arch/arm/mach-msm/board-msm7x27.c                  |   10 ++--
 arch/arm/mach-msm/board-msm7x30.c                  |    8 ++--
 arch/arm/mach-msm/board-msm8960.c                  |    4 +-
 arch/arm/mach-msm/board-msm8x60.c                  |    4 +-
 arch/arm/mach-msm/board-qsd8x50.c                  |   10 ++--
 arch/arm/mach-msm/board-sapphire.c                 |    8 ++--
 arch/arm/mach-msm/board-trout-mmc.c                |    4 +-
 arch/arm/mach-msm/board-trout-panel.c              |    4 +-
 arch/arm/mach-msm/board-trout.c                    |    6 +--
 arch/arm/mach-msm/board-trout.h                    |    4 +-
 arch/arm/mach-msm/clock-pcom.c                     |    2 +-
 arch/arm/mach-msm/clock.h                          |    2 +-
 arch/arm/mach-msm/devices-iommu.c                  |    4 +-
 arch/arm/mach-msm/devices-msm7x00.c                |    6 +--
 arch/arm/mach-msm/devices-msm7x30.c                |   10 ++--
 arch/arm/mach-msm/devices-msm8960.c                |    4 +-
 arch/arm/mach-msm/devices-qsd8x50.c                |   10 ++--
 arch/arm/mach-msm/dma.c                            |    2 +-
 arch/arm/mach-msm/gpiomux-v2.c                     |    2 +-
 arch/arm/mach-msm/gpiomux.h                        |    2 +-
 arch/arm/mach-msm/include/mach-msm/board.h         |    2 +-
 arch/arm/mach-msm/include/mach-msm/debug-macro.S   |    4 +-
 arch/arm/mach-msm/include/mach-msm/dma.h           |    2 +-
 arch/arm/mach-msm/include/mach-msm/entry-macro.S   |    2 +-
 arch/arm/mach-msm/include/mach-msm/sirc.h          |    2 +-
 arch/arm/mach-msm/include/mach-msm/uncompress.h    |    2 +-
 arch/arm/mach-msm/io.c                             |    6 +--
 arch/arm/mach-msm/irq-vic.c                        |    4 +-
 arch/arm/mach-msm/irq.c                            |    4 +-
 arch/arm/mach-msm/platsmp.c                        |    2 +-
 arch/arm/mach-msm/proc_comm.c                      |    4 +-
 arch/arm/mach-msm/smd.c                            |    4 +-
 arch/arm/mach-msm/smd_debug.c                      |    2 +-
 arch/arm/mach-msm/smd_private.h                    |    2 +-
 arch/arm/mach-msm/timer.c                          |    6 +--
 arch/arm/mach-msm/vreg.c                           |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    2 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |   16 +++----
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |    2 +-
 .../include/mach-mv78xx0/bridge-regs.h             |    2 +-
 .../include/mach-mv78xx0/debug-macro.S             |    2 +-
 .../include/mach-mv78xx0/entry-macro.S             |    2 +-
 arch/arm/mach-mv78xx0/include/mach-mv78xx0/gpio.h  |    2 +-
 .../mach-mv78xx0/include/mach-mv78xx0/uncompress.h |    2 +-
 arch/arm/mach-mv78xx0/irq.c                        |    4 +-
 arch/arm/mach-mv78xx0/mpp.c                        |    4 +-
 arch/arm/mach-mv78xx0/pcie.c                       |    4 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |    2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |    2 +-
 .../mach-mvebu/include/mach-mvebu/debug-macro.S    |    2 +-
 .../arm/mach-mvebu/include/mach-mvebu/uncompress.h |    2 +-
 arch/arm/mach-mxs/devices-mx23.h                   |    4 +-
 arch/arm/mach-mxs/devices-mx28.h                   |    4 +-
 arch/arm/mach-mxs/devices/platform-auart.c         |    6 +--
 arch/arm/mach-mxs/devices/platform-dma.c           |    6 +--
 arch/arm/mach-mxs/devices/platform-fec.c           |    4 +-
 arch/arm/mach-mxs/devices/platform-flexcan.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c      |    6 +--
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c     |    6 +--
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c       |    6 +--
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c       |    2 +-
 arch/arm/mach-mxs/devices/platform-mxs-saif.c      |    6 +--
 arch/arm/mach-mxs/devices/platform-mxsfb.c         |    6 +--
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c  |    6 +--
 arch/arm/mach-mxs/icoll.c                          |    4 +-
 arch/arm/mach-mxs/include/mach-mxs/debug-macro.S   |    4 +-
 arch/arm/mach-mxs/include/mach-mxs/entry-macro.S   |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx23.h    |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx28.h    |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mx23.h          |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mx28.h          |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mxs.h           |    4 +-
 arch/arm/mach-mxs/iomux.c                          |    4 +-
 arch/arm/mach-mxs/mach-apx4devkit.c                |    6 +--
 arch/arm/mach-mxs/mach-m28evk.c                    |    4 +-
 arch/arm/mach-mxs/mach-mx23evk.c                   |    4 +-
 arch/arm/mach-mxs/mach-mx28evk.c                   |    6 +--
 arch/arm/mach-mxs/mach-mxs.c                       |    2 +-
 arch/arm/mach-mxs/mach-stmp378x_devb.c             |    4 +-
 arch/arm/mach-mxs/mach-tx28.c                      |    4 +-
 arch/arm/mach-mxs/mm.c                             |    8 ++--
 arch/arm/mach-mxs/module-tx28.c                    |    2 +-
 arch/arm/mach-mxs/ocotp.c                          |    2 +-
 arch/arm/mach-mxs/system.c                         |    4 +-
 arch/arm/mach-mxs/timer.c                          |    4 +-
 arch/arm/mach-netx/fb.c                            |    4 +-
 arch/arm/mach-netx/generic.c                       |    4 +-
 arch/arm/mach-netx/nxdb500.c                       |    6 +--
 arch/arm/mach-netx/nxdkn.c                         |    6 +--
 arch/arm/mach-netx/nxeb500hmi.c                    |    6 +--
 arch/arm/mach-netx/pfifo.c                         |    6 +--
 arch/arm/mach-netx/time.c                          |    4 +-
 arch/arm/mach-netx/xc.c                            |    8 ++--
 arch/arm/mach-nomadik/board-nhk8815.c              |    8 ++--
 arch/arm/mach-nomadik/cpu-8815.c                   |    6 +--
 arch/arm/mach-nomadik/i2c-8815nhk.c                |    4 +-
 arch/arm/mach-nomadik/include/mach-nomadik/fsmc.h  |    2 +-
 arch/arm/mach-nomadik/include/mach-nomadik/irqs.h  |    2 +-
 .../mach-nomadik/include/mach-nomadik/uncompress.h |    2 +-
 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    4 +-
 arch/arm/mach-omap1/ams-delta-fiq.c                |    4 +-
 arch/arm/mach-omap1/board-ams-delta.c              |   18 ++++----
 arch/arm/mach-omap1/board-fsample.c                |   16 +++----
 arch/arm/mach-omap1/board-generic.c                |    8 ++--
 arch/arm/mach-omap1/board-h2-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h2.c                     |   18 ++++----
 arch/arm/mach-omap1/board-h3-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h3.c                     |   18 ++++----
 arch/arm/mach-omap1/board-htcherald.c              |   12 ++---
 arch/arm/mach-omap1/board-innovator.c              |   18 ++++----
 arch/arm/mach-omap1/board-nokia770.c               |   18 ++++----
 arch/arm/mach-omap1/board-osk.c                    |   12 ++---
 arch/arm/mach-omap1/board-palmte.c                 |   18 ++++----
 arch/arm/mach-omap1/board-palmtt.c                 |   22 ++++-----
 arch/arm/mach-omap1/board-palmz71.c                |   20 ++++----
 arch/arm/mach-omap1/board-perseus2.c               |   16 +++----
 arch/arm/mach-omap1/board-sx1-mmc.c                |    6 +--
 arch/arm/mach-omap1/board-sx1.c                    |   22 ++++-----
 arch/arm/mach-omap1/board-voiceblue.c              |   16 +++----
 arch/arm/mach-omap1/clock.c                        |   12 ++---
 arch/arm/mach-omap1/clock.h                        |    2 +-
 arch/arm/mach-omap1/clock_data.c                   |   16 +++----
 arch/arm/mach-omap1/common.h                       |    2 +-
 arch/arm/mach-omap1/devices.c                      |   18 ++++----
 arch/arm/mach-omap1/dma.c                          |    6 +--
 arch/arm/mach-omap1/flash.c                        |    6 +--
 arch/arm/mach-omap1/fpga.c                         |    4 +-
 arch/arm/mach-omap1/i2c.c                          |    6 +--
 arch/arm/mach-omap1/id.c                           |    4 +-
 .../mach-omap1/include/mach-omap1/ams-delta-fiq.h  |    2 +-
 .../mach-omap1/include/mach-omap1/debug-macro.S    |    2 +-
 .../mach-omap1/include/mach-omap1/entry-macro.S    |    4 +-
 arch/arm/mach-omap1/include/mach-omap1/gpio.h      |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/hardware.h  |    4 +-
 arch/arm/mach-omap1/include/mach-omap1/irqs.h      |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/memory.h    |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/mtd-xip.h   |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/smp.h       |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/timex.h     |    2 +-
 .../arm/mach-omap1/include/mach-omap1/uncompress.h |    2 +-
 arch/arm/mach-omap1/io.c                           |    6 +--
 arch/arm/mach-omap1/irq.c                          |    4 +-
 arch/arm/mach-omap1/lcd_dma.c                      |    6 +--
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 +-
 arch/arm/mach-omap1/leds-innovator.c               |    2 +-
 arch/arm/mach-omap1/leds-osk.c                     |    2 +-
 arch/arm/mach-omap1/leds.c                         |    2 +-
 arch/arm/mach-omap1/mailbox.c                      |    2 +-
 arch/arm/mach-omap1/mcbsp.c                        |   10 ++--
 arch/arm/mach-omap1/mux.c                          |    4 +-
 arch/arm/mach-omap1/ocpi.c                         |    2 +-
 arch/arm/mach-omap1/opp_data.c                     |    2 +-
 arch/arm/mach-omap1/pm.c                           |   18 ++++----
 arch/arm/mach-omap1/pm_bus.c                       |    4 +-
 arch/arm/mach-omap1/reset.c                        |    4 +-
 arch/arm/mach-omap1/serial.c                       |    6 +--
 arch/arm/mach-omap1/sram.S                         |    2 +-
 arch/arm/mach-omap1/time.c                         |    2 +-
 arch/arm/mach-omap1/timer.c                        |    4 +-
 arch/arm/mach-omap1/timer32k.c                     |    4 +-
 arch/arm/mach-omap1/usb.c                          |    4 +-
 arch/arm/mach-omap2/am35xx-emac.c                  |    4 +-
 arch/arm/mach-omap2/board-2430sdp.c                |   10 ++--
 arch/arm/mach-omap2/board-3430sdp.c                |   14 +++---
 arch/arm/mach-omap2/board-3630sdp.c                |    8 ++--
 arch/arm/mach-omap2/board-4430sdp.c                |   10 ++--
 arch/arm/mach-omap2/board-am3517crane.c            |    6 +--
 arch/arm/mach-omap2/board-am3517evm.c              |    8 ++--
 arch/arm/mach-omap2/board-apollon.c                |    8 ++--
 arch/arm/mach-omap2/board-cm-t35.c                 |   14 +++---
 arch/arm/mach-omap2/board-cm-t3517.c               |   10 ++--
 arch/arm/mach-omap2/board-devkit8000.c             |   14 +++---
 arch/arm/mach-omap2/board-flash.c                  |   10 ++--
 arch/arm/mach-omap2/board-flash.h                  |    2 +-
 arch/arm/mach-omap2/board-generic.c                |    4 +-
 arch/arm/mach-omap2/board-h4.c                     |   10 ++--
 arch/arm/mach-omap2/board-igep0020.c               |   10 ++--
 arch/arm/mach-omap2/board-ldp.c                    |   14 +++---
 arch/arm/mach-omap2/board-n8x0.c                   |   14 +++---
 arch/arm/mach-omap2/board-omap3beagle.c            |   12 ++---
 arch/arm/mach-omap2/board-omap3evm.c               |   12 ++---
 arch/arm/mach-omap2/board-omap3logic.c             |   14 +++---
 arch/arm/mach-omap2/board-omap3pandora.c           |   10 ++--
 arch/arm/mach-omap2/board-omap3stalker.c           |   14 +++---
 arch/arm/mach-omap2/board-omap3touchbook.c         |   12 ++---
 arch/arm/mach-omap2/board-omap4panda.c             |    8 ++--
 arch/arm/mach-omap2/board-overo.c                  |   16 +++----
 arch/arm/mach-omap2/board-rm680.c                  |   10 ++--
 arch/arm/mach-omap2/board-rx51-peripherals.c       |   14 +++---
 arch/arm/mach-omap2/board-rx51-video.c             |    6 +--
 arch/arm/mach-omap2/board-rx51.c                   |   12 ++---
 arch/arm/mach-omap2/board-ti8168evm.c              |    8 ++--
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    6 +--
 arch/arm/mach-omap2/board-zoom-display.c           |    4 +-
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    4 +-
 arch/arm/mach-omap2/board-zoom.c                   |    6 +--
 arch/arm/mach-omap2/clkt2xxx_apll.c                |    4 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c                |    2 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c            |    6 +--
 arch/arm/mach-omap2/clkt2xxx_osc.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c       |    8 ++--
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c             |    6 +--
 arch/arm/mach-omap2/clkt_clksel.c                  |    2 +-
 arch/arm/mach-omap2/clkt_dpll.c                    |    4 +-
 arch/arm/mach-omap2/clkt_iclk.c                    |    4 +-
 arch/arm/mach-omap2/clock.c                        |    6 +--
 arch/arm/mach-omap2/clock.h                        |    2 +-
 arch/arm/mach-omap2/clock2420_data.c               |    4 +-
 arch/arm/mach-omap2/clock2430.c                    |    4 +-
 arch/arm/mach-omap2/clock2430_data.c               |    4 +-
 arch/arm/mach-omap2/clock2xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock33xx_data.c               |    4 +-
 arch/arm/mach-omap2/clock34xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3517.c                    |    2 +-
 arch/arm/mach-omap2/clock36xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock3xxx_data.c               |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c               |    4 +-
 arch/arm/mach-omap2/clockdomain.c                  |    2 +-
 arch/arm/mach-omap2/clockdomain.h                  |    6 +--
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx.c                  |    2 +-
 arch/arm/mach-omap2/cm33xx.c                       |    2 +-
 arch/arm/mach-omap2/common-board-devices.c         |    4 +-
 arch/arm/mach-omap2/common.c                       |    8 ++--
 arch/arm/mach-omap2/common.h                       |    2 +-
 arch/arm/mach-omap2/control.c                      |    4 +-
 arch/arm/mach-omap2/control.h                      |   10 ++--
 arch/arm/mach-omap2/cpuidle34xx.c                  |    4 +-
 arch/arm/mach-omap2/devices.c                      |   18 ++++----
 arch/arm/mach-omap2/display.c                      |    6 +--
 arch/arm/mach-omap2/dma.c                          |    6 +--
 arch/arm/mach-omap2/dpll3xxx.c                     |    4 +-
 arch/arm/mach-omap2/dpll44xx.c                     |    4 +-
 arch/arm/mach-omap2/drm.c                          |    4 +-
 arch/arm/mach-omap2/dsp.c                          |    4 +-
 arch/arm/mach-omap2/emu.c                          |    2 +-
 arch/arm/mach-omap2/gpio.c                         |    6 +--
 arch/arm/mach-omap2/gpmc-nand.c                    |    8 ++--
 arch/arm/mach-omap2/gpmc-onenand.c                 |    8 ++--
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    6 +--
 arch/arm/mach-omap2/gpmc-smsc911x.c                |    6 +--
 arch/arm/mach-omap2/gpmc.c                         |    4 +-
 arch/arm/mach-omap2/hdq1w.c                        |    6 +--
 arch/arm/mach-omap2/hsmmc.c                        |   10 ++--
 arch/arm/mach-omap2/hwspinlock.c                   |    4 +-
 arch/arm/mach-omap2/i2c.c                          |    6 +--
 arch/arm/mach-omap2/id.c                           |    4 +-
 .../mach-omap2/include/mach-omap2/debug-macro.S    |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/gpio.h      |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/hardware.h  |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/irqs.h      |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/smp.h       |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/timex.h     |    2 +-
 .../arm/mach-omap2/include/mach-omap2/uncompress.h |    2 +-
 arch/arm/mach-omap2/io.c                           |   14 +++---
 arch/arm/mach-omap2/iommu2.c                       |    2 +-
 arch/arm/mach-omap2/irq.c                          |    2 +-
 arch/arm/mach-omap2/mailbox.c                      |    4 +-
 arch/arm/mach-omap2/mcbsp.c                        |   10 ++--
 arch/arm/mach-omap2/msdi.c                         |    6 +--
 arch/arm/mach-omap2/mux.c                          |    2 +-
 arch/arm/mach-omap2/omap-hotplug.c                 |    2 +-
 arch/arm/mach-omap2/omap-iommu.c                   |    4 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c          |    2 +-
 arch/arm/mach-omap2/omap-secure.c                  |    4 +-
 arch/arm/mach-omap2/omap-smp.c                     |    6 +--
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |   12 ++---
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 ++--
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   24 +++++-----
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   24 +++++-----
 .../omap_hwmod_2xxx_3xxx_interconnect_data.c       |    4 +-
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 ++---
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |    8 ++--
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   16 +++----
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   28 ++++++------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   20 ++++----
 arch/arm/mach-omap2/omap_hwmod_common_data.c       |    2 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    2 +-
 arch/arm/mach-omap2/omap_opp_data.h                |    2 +-
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 +-
 arch/arm/mach-omap2/opp.c                          |    2 +-
 arch/arm/mach-omap2/opp2420_data.c                 |    2 +-
 arch/arm/mach-omap2/opp2430_data.c                 |    2 +-
 arch/arm/mach-omap2/opp3xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/opp4xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                     |    8 ++--
 arch/arm/mach-omap2/pm.c                           |    4 +-
 arch/arm/mach-omap2/pm24xx.c                       |   10 ++--
 arch/arm/mach-omap2/pm34xx.c                       |   10 ++--
 arch/arm/mach-omap2/powerdomain.c                  |    4 +-
 arch/arm/mach-omap2/powerdomain.h                  |    2 +-
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/powerdomain33xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomain44xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c        |    2 +-
 arch/arm/mach-omap2/prcm.c                         |    4 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    6 +--
 arch/arm/mach-omap2/prm33xx.c                      |    2 +-
 arch/arm/mach-omap2/prm44xx.c                      |    6 +--
 arch/arm/mach-omap2/prm_common.c                   |    6 +--
 arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h |    2 +-
 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h  |    2 +-
 arch/arm/mach-omap2/sdram-nokia.c                  |    4 +-
 arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h     |    2 +-
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    2 +-
 arch/arm/mach-omap2/sdrc.c                         |    6 +--
 arch/arm/mach-omap2/sdrc.h                         |    2 +-
 arch/arm/mach-omap2/sdrc2xxx.c                     |    8 ++--
 arch/arm/mach-omap2/serial.c                       |   12 ++---
 arch/arm/mach-omap2/sleep24xx.S                    |    2 +-
 arch/arm/mach-omap2/sleep34xx.S                    |    4 +-
 arch/arm/mach-omap2/sleep44xx.S                    |    4 +-
 arch/arm/mach-omap2/sr_device.c                    |    2 +-
 arch/arm/mach-omap2/sram242x.S                     |    2 +-
 arch/arm/mach-omap2/sram243x.S                     |    2 +-
 arch/arm/mach-omap2/sram34xx.S                     |    2 +-
 arch/arm/mach-omap2/timer.c                        |    8 ++--
 arch/arm/mach-omap2/twl-common.c                   |    4 +-
 arch/arm/mach-omap2/twl-common.h                   |    2 +-
 arch/arm/mach-omap2/usb-host.c                     |    8 ++--
 arch/arm/mach-omap2/usb-musb.c                     |   10 ++--
 arch/arm/mach-omap2/usb-tusb6010.c                 |    2 +-
 arch/arm/mach-omap2/vc.c                           |    2 +-
 arch/arm/mach-omap2/voltage.h                      |    2 +-
 arch/arm/mach-omap2/voltagedomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/wd_timer.c                     |    2 +-
 arch/arm/mach-omap2/wd_timer.h                     |    2 +-
 arch/arm/mach-orion5x/addr-map.c                   |    4 +-
 arch/arm/mach-orion5x/common.c                     |   16 +++----
 arch/arm/mach-orion5x/d2net-setup.c                |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    4 +-
 arch/arm/mach-orion5x/dns323-setup.c               |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |    2 +-
 .../include/mach-orion5x/bridge-regs.h             |    2 +-
 .../include/mach-orion5x/debug-macro.S             |    2 +-
 .../include/mach-orion5x/entry-macro.S             |    2 +-
 arch/arm/mach-orion5x/include/mach-orion5x/gpio.h  |    2 +-
 arch/arm/mach-orion5x/include/mach-orion5x/io.h    |    2 +-
 .../mach-orion5x/include/mach-orion5x/uncompress.h |    2 +-
 arch/arm/mach-orion5x/irq.c                        |    4 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    4 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |    2 +-
 arch/arm/mach-orion5x/mpp.c                        |    4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |    4 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c              |    2 +-
 arch/arm/mach-orion5x/pci.c                        |    6 +--
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c               |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c               |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |    2 +-
 arch/arm/mach-picoxcell/common.c                   |    4 +-
 .../include/mach-picoxcell/debug-macro.S           |    4 +-
 .../include/mach-picoxcell/hardware.h              |    2 +-
 arch/arm/mach-pnx4008/clock.c                      |    4 +-
 arch/arm/mach-pnx4008/core.c                       |    8 ++--
 arch/arm/mach-pnx4008/dma.c                        |    6 +--
 arch/arm/mach-pnx4008/gpio.c                       |    6 +--
 arch/arm/mach-pnx4008/i2c.c                        |    4 +-
 .../mach-pnx4008/include/mach-pnx4008/hardware.h   |    2 +-
 arch/arm/mach-pnx4008/irq.c                        |    4 +-
 arch/arm/mach-pnx4008/pm.c                         |    6 +--
 arch/arm/mach-pnx4008/serial.c                     |    8 ++--
 arch/arm/mach-pnx4008/sleep.S                      |    2 +-
 arch/arm/mach-pnx4008/time.c                       |    2 +-
 arch/arm/mach-pnx4008/time.h                       |    2 +-
 arch/arm/mach-prima2/clock.c                       |    2 +-
 .../mach-prima2/include/mach-prima2/debug-macro.S  |    4 +-
 .../mach-prima2/include/mach-prima2/entry-macro.S  |    2 +-
 .../arm/mach-prima2/include/mach-prima2/hardware.h |    2 +-
 .../mach-prima2/include/mach-prima2/uncompress.h   |    4 +-
 arch/arm/mach-prima2/irq.c                         |    2 +-
 arch/arm/mach-prima2/lluart.c                      |    4 +-
 arch/arm/mach-prima2/timer.c                       |    2 +-
 arch/arm/mach-pxa/am200epd.c                       |    6 +--
 arch/arm/mach-pxa/am300epd.c                       |    6 +--
 arch/arm/mach-pxa/balloon3.c                       |   18 ++++----
 arch/arm/mach-pxa/capc7117.c                       |    4 +-
 arch/arm/mach-pxa/clock-pxa2xx.c                   |    2 +-
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    4 +-
 arch/arm/mach-pxa/cm-x255.c                        |    2 +-
 arch/arm/mach-pxa/cm-x270.c                        |    6 +--
 arch/arm/mach-pxa/cm-x2xx.c                        |   10 ++--
 arch/arm/mach-pxa/cm-x300.c                        |   16 +++----
 arch/arm/mach-pxa/colibri-evalboard.c              |   12 ++---
 arch/arm/mach-pxa/colibri-pxa270-income.c          |   12 ++---
 arch/arm/mach-pxa/colibri-pxa270.c                 |    6 +--
 arch/arm/mach-pxa/colibri-pxa300.c                 |   10 ++--
 arch/arm/mach-pxa/colibri-pxa320.c                 |   14 +++---
 arch/arm/mach-pxa/colibri-pxa3xx.c                 |   14 +++---
 arch/arm/mach-pxa/corgi.c                          |   14 +++---
 arch/arm/mach-pxa/corgi_pm.c                       |    8 ++--
 arch/arm/mach-pxa/cpufreq-pxa2xx.c                 |    4 +-
 arch/arm/mach-pxa/cpufreq-pxa3xx.c                 |    2 +-
 arch/arm/mach-pxa/csb726.c                         |   12 ++---
 arch/arm/mach-pxa/devices.c                        |   24 +++++-----
 arch/arm/mach-pxa/em-x270.c                        |   16 +++----
 arch/arm/mach-pxa/eseries.c                        |   14 +++---
 arch/arm/mach-pxa/ezx.c                            |   12 ++---
 arch/arm/mach-pxa/generic.c                        |    8 ++--
 arch/arm/mach-pxa/gumstix.c                        |   10 ++--
 arch/arm/mach-pxa/h5000.c                          |    8 ++--
 arch/arm/mach-pxa/himalaya.c                       |    2 +-
 arch/arm/mach-pxa/hx4700.c                         |    8 ++--
 arch/arm/mach-pxa/icontrol.c                       |    4 +-
 arch/arm/mach-pxa/idp.c                            |   12 ++---
 arch/arm/mach-pxa/include/mach-pxa/colibri.h       |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/dma.h           |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/gpio.h          |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/h5000.h         |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/hardware.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/magician.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mainstone.h     |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa25x.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa27x.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa2xx.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa300.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa320.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa3xx.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa930.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp.h           |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mtd-xip.h       |    2 +-
 .../mach-pxa/include/mach-pxa/pcm990_baseboard.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa25x.h        |    8 ++--
 arch/arm/mach-pxa/include/mach-pxa/pxa27x.h        |    8 ++--
 arch/arm/mach-pxa/include/mach-pxa/pxa2xx-regs.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa300.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa320.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx-regs.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx.h        |    6 +--
 arch/arm/mach-pxa/include/mach-pxa/pxa930.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa95x.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxafb.h         |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-ac97.h     |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-lcd.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-ost.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-rtc.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-u2d.h      |    2 +-
 arch/arm/mach-pxa/irq.c                            |    4 +-
 arch/arm/mach-pxa/leds-idp.c                       |    6 +--
 arch/arm/mach-pxa/leds-lubbock.c                   |    6 +--
 arch/arm/mach-pxa/leds-mainstone.c                 |    6 +--
 arch/arm/mach-pxa/littleton.c                      |   14 +++---
 arch/arm/mach-pxa/lpd270.c                         |   18 ++++----
 arch/arm/mach-pxa/lubbock.c                        |   20 ++++----
 arch/arm/mach-pxa/magician.c                       |   14 +++---
 arch/arm/mach-pxa/mainstone.c                      |   20 ++++----
 arch/arm/mach-pxa/mfp-pxa2xx.c                     |    4 +-
 arch/arm/mach-pxa/mfp-pxa3xx.c                     |    6 +--
 arch/arm/mach-pxa/mioa701.c                        |   22 ++++-----
 arch/arm/mach-pxa/mp900.c                          |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                        |   12 ++---
 arch/arm/mach-pxa/palm27x.c                        |   16 +++----
 arch/arm/mach-pxa/palmld.c                         |   18 ++++----
 arch/arm/mach-pxa/palmt5.c                         |   20 ++++----
 arch/arm/mach-pxa/palmtc.c                         |   14 +++---
 arch/arm/mach-pxa/palmte2.c                        |   16 +++----
 arch/arm/mach-pxa/palmtreo.c                       |   28 ++++++------
 arch/arm/mach-pxa/palmtx.c                         |   20 ++++----
 arch/arm/mach-pxa/palmz72.c                        |   26 +++++------
 arch/arm/mach-pxa/pcm027.c                         |    4 +-
 arch/arm/mach-pxa/pcm990-baseboard.c               |   14 +++---
 arch/arm/mach-pxa/pm.c                             |    2 +-
 arch/arm/mach-pxa/poodle.c                         |   14 +++---
 arch/arm/mach-pxa/pxa25x.c                         |   14 +++---
 arch/arm/mach-pxa/pxa27x.c                         |   16 +++----
 arch/arm/mach-pxa/pxa2xx.c                         |   10 ++--
 arch/arm/mach-pxa/pxa300.c                         |    2 +-
 arch/arm/mach-pxa/pxa320.c                         |    2 +-
 arch/arm/mach-pxa/pxa3xx-ulpi.c                    |    6 +--
 arch/arm/mach-pxa/pxa3xx.c                         |   16 +++----
 arch/arm/mach-pxa/pxa930.c                         |    2 +-
 arch/arm/mach-pxa/pxa95x.c                         |   12 ++---
 arch/arm/mach-pxa/raumfeld.c                       |   10 ++--
 arch/arm/mach-pxa/reset.c                          |    4 +-
 arch/arm/mach-pxa/saar.c                           |    4 +-
 arch/arm/mach-pxa/saarb.c                          |   10 ++--
 arch/arm/mach-pxa/sharpsl_pm.c                     |    8 ++--
 arch/arm/mach-pxa/sleep.S                          |    6 +--
 arch/arm/mach-pxa/smemc.c                          |    4 +-
 arch/arm/mach-pxa/spitz.c                          |   20 ++++----
 arch/arm/mach-pxa/spitz_pm.c                       |    8 ++--
 arch/arm/mach-pxa/standby.S                        |    4 +-
 arch/arm/mach-pxa/stargate2.c                      |   10 ++--
 arch/arm/mach-pxa/tavorevb.c                       |    6 +--
 arch/arm/mach-pxa/tavorevb3.c                      |    2 +-
 arch/arm/mach-pxa/time.c                           |    4 +-
 arch/arm/mach-pxa/tosa-bt.c                        |    2 +-
 arch/arm/mach-pxa/tosa.c                           |   18 ++++----
 arch/arm/mach-pxa/trizeps4.c                       |   16 +++----
 arch/arm/mach-pxa/viper.c                          |   12 ++---
 arch/arm/mach-pxa/vpac270.c                        |   18 ++++----
 arch/arm/mach-pxa/xcep.c                           |    6 +--
 arch/arm/mach-pxa/z2.c                             |   14 +++---
 arch/arm/mach-pxa/zeus.c                           |   24 +++++-----
 arch/arm/mach-pxa/zylonite.c                       |   16 +++----
 arch/arm/mach-pxa/zylonite_pxa300.c                |    4 +-
 arch/arm/mach-pxa/zylonite_pxa320.c                |    4 +-
 arch/arm/mach-realview/core.c                      |   10 ++--
 .../mach-realview/include/mach-realview/board-eb.h |    2 +-
 .../include/mach-realview/board-pb1176.h           |    2 +-
 .../include/mach-realview/board-pb11mp.h           |    2 +-
 .../include/mach-realview/board-pba8.h             |    2 +-
 .../include/mach-realview/board-pbx.h              |    2 +-
 .../mach-realview/include/mach-realview/clkdev.h   |    2 +-
 .../arm/mach-realview/include/mach-realview/irqs.h |   10 ++--
 .../include/mach-realview/uncompress.h             |   12 ++---
 arch/arm/mach-realview/platsmp.c                   |    8 ++--
 arch/arm/mach-realview/realview_eb.c               |    6 +--
 arch/arm/mach-realview/realview_pb1176.c           |    6 +--
 arch/arm/mach-realview/realview_pb11mp.c           |    6 +--
 arch/arm/mach-realview/realview_pba8.c             |    6 +--
 arch/arm/mach-realview/realview_pbx.c              |    6 +--
 arch/arm/mach-rpc/dma.c                            |    2 +-
 arch/arm/mach-rpc/ecard.c                          |    2 +-
 arch/arm/mach-rpc/fiq.S                            |    4 +-
 arch/arm/mach-rpc/include/mach-rpc/entry-macro.S   |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/hardware.h      |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/io.h            |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/uncompress.h    |    2 +-
 arch/arm/mach-rpc/riscpc.c                         |    2 +-
 arch/arm/mach-rpc/time.c                           |    2 +-
 arch/arm/mach-s3c2410/cpu-freq.c                   |    8 ++--
 arch/arm/mach-s3c2410/pll.c                        |    4 +-
 arch/arm/mach-s3c2412/cpu-freq.c                   |   10 ++--
 arch/arm/mach-s3c2412/gpio.c                       |    6 +--
 arch/arm/mach-s3c2440/dsc.c                        |   10 ++--
 arch/arm/mach-s3c2440/s3c2440-cpufreq.c            |   10 ++--
 arch/arm/mach-s3c2440/s3c2440-pll-12000000.c       |    4 +-
 arch/arm/mach-s3c2440/s3c2440-pll-16934400.c       |    4 +-
 arch/arm/mach-s3c24xx/bast-ide.c                   |    6 +--
 arch/arm/mach-s3c24xx/bast-irq.c                   |   10 ++--
 arch/arm/mach-s3c24xx/clock-s3c2412.c              |   14 +++---
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |   16 +++----
 arch/arm/mach-s3c24xx/clock-s3c2440.c              |   10 ++--
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |   14 +++---
 arch/arm/mach-s3c24xx/clock-s3c244x.c              |    8 ++--
 arch/arm/mach-s3c24xx/common-s3c2443.c             |   10 ++--
 arch/arm/mach-s3c24xx/common-smdk.c                |   16 +++----
 arch/arm/mach-s3c24xx/common.c                     |   30 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2410.c                |   30 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2412.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2440.c                |   26 +++++------
 arch/arm/mach-s3c24xx/dma-s3c2443.c                |   24 +++++-----
 arch/arm/mach-s3c24xx/h1940-bluetooth.c            |    8 ++--
 .../include/mach-s3c24xx/debug-macro.S             |    8 ++--
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/dma.h   |    2 +-
 .../include/mach-s3c24xx/entry-macro.S             |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/fb.h    |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-fns.h   |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-track.h |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio.h  |    4 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gta02.h |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/hardware.h   |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/io.h    |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/map.h   |    4 +-
 .../mach-s3c24xx/include/mach-s3c24xx/regs-gpio.h  |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/uncompress.h |    6 +--
 .../mach-s3c24xx/include/mach-s3c24xx/vr1000-map.h |    2 +-
 arch/arm/mach-s3c24xx/irq-pm.c                     |    6 +--
 arch/arm/mach-s3c24xx/irq-s3c2412.c                |   14 +++---
 arch/arm/mach-s3c24xx/irq-s3c2416.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c2440.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c2443.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c244x.c                |   12 ++---
 arch/arm/mach-s3c24xx/mach-amlm5900.c              |   18 ++++----
 arch/arm/mach-s3c24xx/mach-anubis.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-at2440evb.c             |   24 +++++-----
 arch/arm/mach-s3c24xx/mach-bast.c                  |   36 +++++++--------
 arch/arm/mach-s3c24xx/mach-gta02.c                 |   38 ++++++++--------
 arch/arm/mach-s3c24xx/mach-h1940.c                 |   46 +++++++++----------
 arch/arm/mach-s3c24xx/mach-jive.c                  |   30 ++++++------
 arch/arm/mach-s3c24xx/mach-mini2440.c              |   32 ++++++-------
 arch/arm/mach-s3c24xx/mach-n30.c                   |   26 +++++------
 arch/arm/mach-s3c24xx/mach-nexcoder.c              |   22 ++++-----
 arch/arm/mach-s3c24xx/mach-osiris-dvs.c            |    2 +-
 arch/arm/mach-s3c24xx/mach-osiris.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-otom.c                  |   18 ++++----
 arch/arm/mach-s3c24xx/mach-qt2410.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-rx1950.c                |   34 +++++++-------
 arch/arm/mach-s3c24xx/mach-rx3715.c                |   22 ++++-----
 arch/arm/mach-s3c24xx/mach-smdk2410.c              |   12 ++---
 arch/arm/mach-s3c24xx/mach-smdk2413.c              |   34 +++++++-------
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |   42 ++++++++---------
 arch/arm/mach-s3c24xx/mach-smdk2440.c              |   26 +++++------
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |   26 +++++------
 arch/arm/mach-s3c24xx/mach-tct_hammer.c            |   10 ++--
 arch/arm/mach-s3c24xx/mach-vr1000.c                |   26 +++++------
 arch/arm/mach-s3c24xx/mach-vstms.c                 |   26 +++++------
 arch/arm/mach-s3c24xx/pm-h1940.S                   |    6 +--
 arch/arm/mach-s3c24xx/pm-s3c2410.c                 |   10 ++--
 arch/arm/mach-s3c24xx/pm-s3c2412.c                 |   14 +++---
 arch/arm/mach-s3c24xx/pm-s3c2416.c                 |    8 ++--
 arch/arm/mach-s3c24xx/pm.c                         |   14 +++---
 arch/arm/mach-s3c24xx/s3c2410.c                    |   28 ++++++------
 arch/arm/mach-s3c24xx/s3c2412.c                    |   36 +++++++--------
 arch/arm/mach-s3c24xx/s3c2416.c                    |   34 +++++++-------
 arch/arm/mach-s3c24xx/s3c2440.c                    |   16 +++----
 arch/arm/mach-s3c24xx/s3c2442.c                    |   18 ++++----
 arch/arm/mach-s3c24xx/s3c2443.c                    |   26 +++++------
 arch/arm/mach-s3c24xx/s3c244x.c                    |   34 +++++++-------
 arch/arm/mach-s3c24xx/setup-i2c.c                  |    8 ++--
 arch/arm/mach-s3c24xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                  |    6 +--
 arch/arm/mach-s3c24xx/setup-ts.c                   |    2 +-
 arch/arm/mach-s3c24xx/simtec-audio.c               |   14 +++---
 arch/arm/mach-s3c24xx/simtec-nor.c                 |    6 +--
 arch/arm/mach-s3c24xx/simtec-pm.c                  |   10 ++--
 arch/arm/mach-s3c24xx/simtec-usb.c                 |   10 ++--
 arch/arm/mach-s3c24xx/sleep-s3c2410.S              |   12 ++---
 arch/arm/mach-s3c24xx/sleep-s3c2412.S              |    6 +--
 arch/arm/mach-s3c24xx/sleep.S                      |   12 ++---
 arch/arm/mach-s3c64xx/clock.c                      |   24 +++++-----
 arch/arm/mach-s3c64xx/common.c                     |   28 ++++++------
 arch/arm/mach-s3c64xx/cpuidle.c                    |    6 +--
 arch/arm/mach-s3c64xx/dev-audio.c                  |   12 ++---
 arch/arm/mach-s3c64xx/dev-uart.c                   |    6 +--
 arch/arm/mach-s3c64xx/dma.c                        |    8 ++--
 .../include/mach-s3c64xx/debug-macro.S             |    6 +--
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/dma.h   |    4 +-
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/map.h   |    4 +-
 .../mach-s3c64xx/include/mach-s3c64xx/pm-core.h    |    2 +-
 .../mach-s3c64xx/include/mach-s3c64xx/uncompress.h |    4 +-
 arch/arm/mach-s3c64xx/irq-pm.c                     |   12 ++---
 arch/arm/mach-s3c64xx/mach-anw6410.c               |   22 ++++-----
 arch/arm/mach-s3c64xx/mach-crag6410-module.c       |    4 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |   48 ++++++++++----------
 arch/arm/mach-s3c64xx/mach-hmt.c                   |   20 ++++----
 arch/arm/mach-s3c64xx/mach-mini6410.c              |   26 +++++------
 arch/arm/mach-s3c64xx/mach-ncp.c                   |   18 ++++----
 arch/arm/mach-s3c64xx/mach-real6410.c              |   26 +++++------
 arch/arm/mach-s3c64xx/mach-smartq.c                |   28 ++++++------
 arch/arm/mach-s3c64xx/mach-smartq5.c               |   16 +++----
 arch/arm/mach-s3c64xx/mach-smartq7.c               |   16 +++----
 arch/arm/mach-s3c64xx/mach-smdk6400.c              |   14 +++---
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |   40 ++++++++--------
 arch/arm/mach-s3c64xx/pm.c                         |   26 +++++------
 arch/arm/mach-s3c64xx/s3c6400.c                    |   20 ++++----
 arch/arm/mach-s3c64xx/s3c6410.c                    |   26 +++++------
 arch/arm/mach-s3c64xx/setup-fb-24bpp.c             |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-ide.c                  |    8 ++--
 arch/arm/mach-s3c64xx/setup-keypad.c               |    4 +-
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c64xx/setup-spi.c                  |    2 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   10 ++--
 arch/arm/mach-s3c64xx/sleep.S                      |    4 +-
 arch/arm/mach-s5p64x0/clock-s5p6440.c              |   22 ++++-----
 arch/arm/mach-s5p64x0/clock-s5p6450.c              |   22 ++++-----
 arch/arm/mach-s5p64x0/clock.c                      |   20 ++++----
 arch/arm/mach-s5p64x0/common.c                     |   32 ++++++-------
 arch/arm/mach-s5p64x0/dev-audio.c                  |   10 ++--
 arch/arm/mach-s5p64x0/dma.c                        |   14 +++---
 arch/arm/mach-s5p64x0/gpiolib.c                    |   16 +++----
 .../include/mach-s5p64x0/debug-macro.S             |    8 ++--
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/dma.h   |    2 +-
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/irqs.h  |    2 +-
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/map.h   |    4 +-
 .../mach-s5p64x0/include/mach-s5p64x0/pm-core.h    |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-clock.h |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-gpio.h  |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-irq.h   |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/uncompress.h |    6 +--
 arch/arm/mach-s5p64x0/irq-pm.c                     |    6 +--
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |   40 ++++++++--------
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |   40 ++++++++--------
 arch/arm/mach-s5p64x0/pm.c                         |   12 ++---
 arch/arm/mach-s5p64x0/setup-fb-24bpp.c             |    6 +--
 arch/arm/mach-s5p64x0/setup-i2c0.c                 |    6 +--
 arch/arm/mach-s5p64x0/setup-i2c1.c                 |    6 +--
 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c           |   10 ++--
 arch/arm/mach-s5p64x0/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pc100/clock.c                      |   18 ++++----
 arch/arm/mach-s5pc100/common.c                     |   30 ++++++------
 arch/arm/mach-s5pc100/dev-audio.c                  |   10 ++--
 arch/arm/mach-s5pc100/dma.c                        |   10 ++--
 .../include/mach-s5pc100/debug-macro.S             |    6 +--
 arch/arm/mach-s5pc100/include/mach-s5pc100/dma.h   |    2 +-
 arch/arm/mach-s5pc100/include/mach-s5pc100/irqs.h  |    2 +-
 arch/arm/mach-s5pc100/include/mach-s5pc100/map.h   |    4 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-clock.h |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-gpio.h  |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-irq.h   |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/uncompress.h |    4 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |   34 +++++++-------
 arch/arm/mach-s5pc100/setup-fb-24bpp.c             |    6 +--
 arch/arm/mach-s5pc100/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-ide.c                  |    4 +-
 arch/arm/mach-s5pc100/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c           |    6 +--
 arch/arm/mach-s5pc100/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/clock.c                      |   18 ++++----
 arch/arm/mach-s5pv210/common.c                     |   30 ++++++------
 arch/arm/mach-s5pv210/dev-audio.c                  |   12 ++---
 arch/arm/mach-s5pv210/dma.c                        |   10 ++--
 .../include/mach-s5pv210/debug-macro.S             |    6 +--
 arch/arm/mach-s5pv210/include/mach-s5pv210/dma.h   |    2 +-
 arch/arm/mach-s5pv210/include/mach-s5pv210/irqs.h  |    2 +-
 arch/arm/mach-s5pv210/include/mach-s5pv210/map.h   |    4 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-clock.h |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-gpio.h  |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-irq.h   |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/uncompress.h |    4 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |   24 +++++-----
 arch/arm/mach-s5pv210/mach-goni.c                  |   32 ++++++-------
 arch/arm/mach-s5pv210/mach-smdkc110.c              |   22 ++++-----
 arch/arm/mach-s5pv210/mach-smdkv210.c              |   40 ++++++++--------
 arch/arm/mach-s5pv210/mach-torbreck.c              |   16 +++----
 arch/arm/mach-s5pv210/pm.c                         |   10 ++--
 arch/arm/mach-s5pv210/setup-fb-24bpp.c             |    8 ++--
 arch/arm/mach-s5pv210/setup-fimc.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c2.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-ide.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c           |    6 +--
 arch/arm/mach-s5pv210/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-usb-phy.c              |   10 ++--
 arch/arm/mach-sa1100/assabet.c                     |    8 ++--
 arch/arm/mach-sa1100/badge4.c                      |    6 +--
 arch/arm/mach-sa1100/cerf.c                        |    8 ++--
 arch/arm/mach-sa1100/clock.c                       |    2 +-
 arch/arm/mach-sa1100/collie.c                      |    8 ++--
 arch/arm/mach-sa1100/cpu-sa1100.c                  |    2 +-
 arch/arm/mach-sa1100/cpu-sa1110.c                  |    2 +-
 arch/arm/mach-sa1100/generic.c                     |    4 +-
 arch/arm/mach-sa1100/h3100.c                       |    4 +-
 arch/arm/mach-sa1100/h3600.c                       |    4 +-
 arch/arm/mach-sa1100/h3xxx.c                       |    2 +-
 arch/arm/mach-sa1100/hackkit.c                     |    4 +-
 arch/arm/mach-sa1100/include/mach-sa1100/SA-1101.h |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/badge4.h  |    2 +-
 .../mach-sa1100/include/mach-sa1100/debug-macro.S  |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/gpio.h    |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/mtd-xip.h |    2 +-
 .../mach-sa1100/include/mach-sa1100/nanoengine.h   |    2 +-
 arch/arm/mach-sa1100/irq.c                         |    4 +-
 arch/arm/mach-sa1100/jornada720.c                  |    4 +-
 arch/arm/mach-sa1100/jornada720_ssp.c              |    4 +-
 arch/arm/mach-sa1100/lart.c                        |    6 +--
 arch/arm/mach-sa1100/leds-assabet.c                |    4 +-
 arch/arm/mach-sa1100/leds-badge4.c                 |    2 +-
 arch/arm/mach-sa1100/leds-cerf.c                   |    2 +-
 arch/arm/mach-sa1100/leds-hackkit.c                |    2 +-
 arch/arm/mach-sa1100/leds-lart.c                   |    2 +-
 arch/arm/mach-sa1100/nanoengine.c                  |    6 +--
 arch/arm/mach-sa1100/neponset.c                    |    8 ++--
 arch/arm/mach-sa1100/pci-nanoengine.c              |    4 +-
 arch/arm/mach-sa1100/pleb.c                        |    4 +-
 arch/arm/mach-sa1100/pm.c                          |    2 +-
 arch/arm/mach-sa1100/shannon.c                     |    8 ++--
 arch/arm/mach-sa1100/simpad.c                      |    8 ++--
 arch/arm/mach-sa1100/sleep.S                       |    2 +-
 arch/arm/mach-sa1100/ssp.c                         |    4 +-
 arch/arm/mach-sa1100/time.c                        |    4 +-
 arch/arm/mach-shmobile/board-ag5evm.c              |    8 ++--
 arch/arm/mach-shmobile/board-ap4evb.c              |    6 +--
 arch/arm/mach-shmobile/board-armadillo800eva.c     |    6 +--
 arch/arm/mach-shmobile/board-bonito.c              |    6 +--
 arch/arm/mach-shmobile/board-g3evm.c               |    6 +--
 arch/arm/mach-shmobile/board-g4evm.c               |    6 +--
 arch/arm/mach-shmobile/board-kota2.c               |    8 ++--
 arch/arm/mach-shmobile/board-kzm9d.c               |    4 +-
 arch/arm/mach-shmobile/board-kzm9g.c               |    6 +--
 arch/arm/mach-shmobile/board-mackerel.c            |    6 +--
 arch/arm/mach-shmobile/board-marzen.c              |    8 ++--
 arch/arm/mach-shmobile/clock-emev2.c               |    2 +-
 arch/arm/mach-shmobile/clock-r8a7740.c             |    4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |    2 +-
 arch/arm/mach-shmobile/clock-sh7367.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7372.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7377.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh73a0.c              |    2 +-
 arch/arm/mach-shmobile/common.c                    |    2 +-
 arch/arm/mach-shmobile/console.c                   |    2 +-
 arch/arm/mach-shmobile/hotplug.c                   |    2 +-
 .../mach-shmobile/include/mach-shmobile/r8a7740.h  |    2 +-
 .../mach-shmobile/include/mach-shmobile/sh7372.h   |    2 +-
 .../mach-shmobile/include/mach-shmobile/zboot.h    |    2 +-
 arch/arm/mach-shmobile/intc-r8a7740.c              |    4 +-
 arch/arm/mach-shmobile/intc-r8a7779.c              |    6 +--
 arch/arm/mach-shmobile/intc-sh7367.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7372.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7377.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh73a0.c               |    6 +--
 arch/arm/mach-shmobile/pfc-r8a7740.c               |    4 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c               |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c                |    4 +-
 arch/arm/mach-shmobile/pfc-sh7377.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c                |    4 +-
 arch/arm/mach-shmobile/platsmp.c                   |    4 +-
 arch/arm/mach-shmobile/pm-r8a7740.c                |    2 +-
 arch/arm/mach-shmobile/pm-r8a7779.c                |    4 +-
 arch/arm/mach-shmobile/pm-rmobile.c                |    2 +-
 arch/arm/mach-shmobile/pm-sh7372.c                 |    6 +--
 arch/arm/mach-shmobile/setup-emev2.c               |    8 ++--
 arch/arm/mach-shmobile/setup-r8a7740.c             |   10 ++--
 arch/arm/mach-shmobile/setup-r8a7779.c             |    8 ++--
 arch/arm/mach-shmobile/setup-sh7367.c              |    6 +--
 arch/arm/mach-shmobile/setup-sh7372.c              |   10 ++--
 arch/arm/mach-shmobile/setup-sh7377.c              |    6 +--
 arch/arm/mach-shmobile/setup-sh73a0.c              |   10 ++--
 arch/arm/mach-shmobile/smp-emev2.c                 |    4 +-
 arch/arm/mach-shmobile/smp-r8a7779.c               |    4 +-
 arch/arm/mach-shmobile/smp-sh73a0.c                |    2 +-
 .../include/mach-spear13xx/debug-macro.S           |    2 +-
 .../mach-spear13xx/include/mach-spear13xx/gpio.h   |    2 +-
 .../mach-spear13xx/include/mach-spear13xx/timex.h  |    2 +-
 .../include/mach-spear13xx/uncompress.h            |    2 +-
 arch/arm/mach-spear13xx/platsmp.c                  |    2 +-
 arch/arm/mach-spear13xx/spear1310.c                |    4 +-
 arch/arm/mach-spear13xx/spear1340.c                |    6 +--
 arch/arm/mach-spear13xx/spear13xx.c                |    6 +--
 .../include/mach-spear3xx/debug-macro.S            |    2 +-
 .../arm/mach-spear3xx/include/mach-spear3xx/gpio.h |    2 +-
 .../include/mach-spear3xx/misc_regs.h              |    2 +-
 .../mach-spear3xx/include/mach-spear3xx/timex.h    |    2 +-
 .../include/mach-spear3xx/uncompress.h             |    2 +-
 arch/arm/mach-spear3xx/spear300.c                  |    6 +--
 arch/arm/mach-spear3xx/spear310.c                  |    6 +--
 arch/arm/mach-spear3xx/spear320.c                  |    6 +--
 arch/arm/mach-spear3xx/spear3xx.c                  |    6 +--
 .../include/mach-spear6xx/debug-macro.S            |    2 +-
 .../arm/mach-spear6xx/include/mach-spear6xx/gpio.h |    2 +-
 .../include/mach-spear6xx/misc_regs.h              |    2 +-
 .../mach-spear6xx/include/mach-spear6xx/timex.h    |    2 +-
 .../include/mach-spear6xx/uncompress.h             |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c                  |    6 +--
 arch/arm/mach-tegra/apbio.c                        |    4 +-
 arch/arm/mach-tegra/board-dt-tegra20.c             |    4 +-
 arch/arm/mach-tegra/board-dt-tegra30.c             |    2 +-
 arch/arm/mach-tegra/board-harmony-power.c          |    2 +-
 arch/arm/mach-tegra/board-harmony.c                |    8 ++--
 arch/arm/mach-tegra/board-harmony.h                |    2 +-
 arch/arm/mach-tegra/board-paz00.c                  |    6 +--
 arch/arm/mach-tegra/board-paz00.h                  |    2 +-
 arch/arm/mach-tegra/board-pinmux.h                 |    2 +-
 arch/arm/mach-tegra/board-trimslice.c              |    4 +-
 arch/arm/mach-tegra/board-trimslice.h              |    2 +-
 arch/arm/mach-tegra/clock.c                        |    2 +-
 arch/arm/mach-tegra/clock.h                        |    2 +-
 arch/arm/mach-tegra/common.c                       |    4 +-
 arch/arm/mach-tegra/cpu-tegra.c                    |    2 +-
 arch/arm/mach-tegra/cpuidle.c                      |    2 +-
 arch/arm/mach-tegra/devices.c                      |    8 ++--
 arch/arm/mach-tegra/devices.h                      |    2 +-
 arch/arm/mach-tegra/dma.c                          |    8 ++--
 arch/arm/mach-tegra/flowctrl.c                     |    2 +-
 arch/arm/mach-tegra/fuse.c                         |    2 +-
 arch/arm/mach-tegra/headsmp.S                      |    2 +-
 .../mach-tegra/include/mach-tegra/debug-macro.S    |    4 +-
 .../arm/mach-tegra/include/mach-tegra/gpio-tegra.h |    2 +-
 .../arm/mach-tegra/include/mach-tegra/uncompress.h |    4 +-
 arch/arm/mach-tegra/io.c                           |    2 +-
 arch/arm/mach-tegra/irq.c                          |    2 +-
 arch/arm/mach-tegra/pcie.c                         |    6 +--
 arch/arm/mach-tegra/platsmp.c                      |    6 +--
 arch/arm/mach-tegra/pmc.c                          |    2 +-
 arch/arm/mach-tegra/powergate.c                    |    6 +--
 arch/arm/mach-tegra/reset.c                        |    4 +-
 arch/arm/mach-tegra/sleep.S                        |    2 +-
 arch/arm/mach-tegra/tegra2_clocks.c                |    4 +-
 arch/arm/mach-tegra/tegra2_emc.c                   |    2 +-
 arch/arm/mach-tegra/tegra30_clocks.c               |    2 +-
 arch/arm/mach-tegra/timer.c                        |    6 +--
 arch/arm/mach-tegra/usb_phy.c                      |    6 +--
 arch/arm/mach-u300/core.c                          |   10 ++--
 arch/arm/mach-u300/i2c.c                           |    2 +-
 arch/arm/mach-u300/include/mach-u300/debug-macro.S |    2 +-
 arch/arm/mach-u300/include/mach-u300/hardware.h    |    2 +-
 arch/arm/mach-u300/regulator.c                     |    4 +-
 arch/arm/mach-u300/spi.c                           |    4 +-
 arch/arm/mach-u300/timer.c                         |    2 +-
 arch/arm/mach-u300/u300.c                          |    4 +-
 arch/arm/mach-ux500/board-mop500-msp.c             |   16 +++----
 arch/arm/mach-ux500/board-mop500-pins.c            |    6 +--
 arch/arm/mach-ux500/board-mop500-sdi.c             |    6 +--
 arch/arm/mach-ux500/board-mop500-u8500uib.c        |    2 +-
 arch/arm/mach-ux500/board-mop500-uib.c             |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |   16 +++----
 arch/arm/mach-ux500/board-mop500.h                 |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c                   |    4 +-
 arch/arm/mach-ux500/clock.c                        |    4 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |   12 ++---
 arch/arm/mach-ux500/cpu.c                          |    6 +--
 arch/arm/mach-ux500/devices-common.c               |    4 +-
 arch/arm/mach-ux500/devices-common.h               |    2 +-
 arch/arm/mach-ux500/devices-db8500.c               |    6 +--
 arch/arm/mach-ux500/devices.c                      |    4 +-
 arch/arm/mach-ux500/id.c                           |    4 +-
 .../mach-ux500/include/mach-ux500/crypto-ux500.h   |    2 +-
 .../mach-ux500/include/mach-ux500/debug-macro.S    |    2 +-
 arch/arm/mach-ux500/include/mach-ux500/hardware.h  |    4 +-
 arch/arm/mach-ux500/include/mach-ux500/irqs.h      |    6 +--
 arch/arm/mach-ux500/include/mach-ux500/msp.h       |    2 +-
 .../arm/mach-ux500/include/mach-ux500/uncompress.h |    2 +-
 arch/arm/mach-ux500/platsmp.c                      |    4 +-
 arch/arm/mach-ux500/timer.c                        |    8 ++--
 arch/arm/mach-ux500/usb.c                          |    6 +--
 arch/arm/mach-versatile/core.c                     |   10 ++--
 .../mach-versatile/include/mach-versatile/clkdev.h |    2 +-
 .../mach-versatile/include/mach-versatile/irqs.h   |    2 +-
 arch/arm/mach-versatile/pci.c                      |    2 +-
 arch/arm/mach-versatile/versatile_ab.c             |    2 +-
 arch/arm/mach-versatile/versatile_pb.c             |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                  |    6 +--
 arch/arm/mach-vexpress/platsmp.c                   |    2 +-
 arch/arm/mach-vexpress/v2m.c                       |    6 +--
 arch/arm/mach-vt8500/bv07.c                        |    2 +-
 arch/arm/mach-vt8500/devices-vt8500.c              |    6 +--
 arch/arm/mach-vt8500/devices-wm8505.c              |    6 +--
 arch/arm/mach-vt8500/devices.c                     |    4 +-
 arch/arm/mach-vt8500/wm8505_7in.c                  |    2 +-
 arch/arm/mach-w90x900/clksel.c                     |    4 +-
 arch/arm/mach-w90x900/clock.c                      |    2 +-
 arch/arm/mach-w90x900/cpu.c                        |   10 ++--
 arch/arm/mach-w90x900/dev.c                        |   12 ++---
 arch/arm/mach-w90x900/gpio.c                       |    2 +-
 .../include/mach-w90x900/entry-macro.S             |    4 +-
 arch/arm/mach-w90x900/include/mach-w90x900/gpio.h  |    2 +-
 .../mach-w90x900/include/mach-w90x900/hardware.h   |    2 +-
 .../mach-w90x900/include/mach-w90x900/regs-ldm.h   |    2 +-
 .../mach-w90x900/include/mach-w90x900/uncompress.h |    4 +-
 arch/arm/mach-w90x900/irq.c                        |    4 +-
 arch/arm/mach-w90x900/mach-nuc910evb.c             |    2 +-
 arch/arm/mach-w90x900/mach-nuc950evb.c             |    4 +-
 arch/arm/mach-w90x900/mach-nuc960evb.c             |    2 +-
 arch/arm/mach-w90x900/mfp.c                        |    2 +-
 arch/arm/mach-w90x900/nuc910.c                     |    2 +-
 arch/arm/mach-w90x900/nuc950.c                     |    2 +-
 arch/arm/mach-w90x900/nuc960.c                     |    2 +-
 arch/arm/mach-w90x900/time.c                       |    4 +-
 arch/arm/mach-zynq/common.c                        |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/clkdev.h      |    2 +-
 arch/arm/mach-zynq/include/mach-zynq/debug-macro.S |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/uncompress.h  |    4 +-
 arch/arm/mach-zynq/timer.c                         |    2 +-
 arch/arm/mm/cache-feroceon-l2.c                    |    2 +-
 arch/arm/plat-mxc/3ds_debugboard.c                 |    2 +-
 arch/arm/plat-mxc/avic.c                           |    6 +--
 arch/arm/plat-mxc/clock.c                          |    4 +-
 arch/arm/plat-mxc/cpu.c                            |    2 +-
 arch/arm/plat-mxc/cpufreq.c                        |    4 +-
 arch/arm/plat-mxc/devices.c                        |    2 +-
 arch/arm/plat-mxc/devices/platform-ahci-imx.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-fec.c           |    4 +-
 arch/arm/plat-mxc/devices/platform-flexcan.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c  |    4 +-
 arch/arm/plat-mxc/devices/platform-gpio-mxc.c      |    2 +-
 arch/arm/plat-mxc/devices/platform-gpio_keys.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-dma.c       |    2 +-
 arch/arm/plat-mxc/devices/platform-imx-fb.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-i2c.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-keypad.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-ssi.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-uart.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx2-wdt.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx21-hcd.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx_udc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imxdi_rtc.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-ipu-core.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mx2-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-ehci.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-mmc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_nand.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_pwm.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rnga.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rtc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_w1.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-pata_imx.c      |    4 +-
 .../plat-mxc/devices/platform-sdhci-esdhc-imx.c    |    6 +--
 arch/arm/plat-mxc/devices/platform-spi_imx.c       |    4 +-
 arch/arm/plat-mxc/epit.c                           |    4 +-
 arch/arm/plat-mxc/iomux-v1.c                       |    4 +-
 arch/arm/plat-mxc/iomux-v3.c                       |    4 +-
 arch/arm/plat-mxc/iram_alloc.c                     |    2 +-
 arch/arm/plat-mxc/ssi-fiq-ksym.c                   |    2 +-
 arch/arm/plat-mxc/system.c                         |    4 +-
 arch/arm/plat-mxc/time.c                           |    4 +-
 arch/arm/plat-mxc/tzic.c                           |    6 +--
 arch/arm/plat-mxc/ulpi.c                           |    2 +-
 arch/arm/plat-omap/clock.c                         |    2 +-
 arch/arm/plat-omap/common.c                        |   12 ++---
 arch/arm/plat-omap/counter_32k.c                   |    8 ++--
 arch/arm/plat-omap/debug-devices.c                 |    2 +-
 arch/arm/plat-omap/debug-leds.c                    |    2 +-
 arch/arm/plat-omap/devices.c                       |   10 ++--
 arch/arm/plat-omap/dma.c                           |    4 +-
 arch/arm/plat-omap/dmtimer.c                       |    4 +-
 arch/arm/plat-omap/fb.c                            |    2 +-
 arch/arm/plat-omap/i2c.c                           |    8 ++--
 arch/arm/plat-omap/include/plat-omap/board.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/common.h      |    4 +-
 arch/arm/plat-omap/include/plat-omap/cpu.h         |    2 +-
 arch/arm/plat-omap/include/plat-omap/dma.h         |    2 +-
 arch/arm/plat-omap/include/plat-omap/hardware.h    |   22 ++++-----
 arch/arm/plat-omap/include/plat-omap/hdq1w.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/iommu.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/mmc.h         |    4 +-
 arch/arm/plat-omap/include/plat-omap/nand.h        |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap-serial.h |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap_device.h |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap_hwmod.h  |    2 +-
 arch/arm/plat-omap/include/plat-omap/uncompress.h  |    2 +-
 arch/arm/plat-omap/include/plat-omap/usb.h         |    2 +-
 arch/arm/plat-omap/mailbox.c                       |    2 +-
 arch/arm/plat-omap/mux.c                           |    4 +-
 arch/arm/plat-omap/omap-pm-noop.c                  |    4 +-
 arch/arm/plat-omap/omap_device.c                   |    6 +--
 arch/arm/plat-omap/sram.c                          |    6 +--
 arch/arm/plat-orion/addr-map.c                     |    2 +-
 arch/arm/plat-orion/common.c                       |    4 +-
 arch/arm/plat-orion/gpio.c                         |    2 +-
 arch/arm/plat-orion/irq.c                          |    4 +-
 arch/arm/plat-orion/mpp.c                          |    2 +-
 arch/arm/plat-orion/pcie.c                         |    4 +-
 arch/arm/plat-pxa/mfp.c                            |    2 +-
 arch/arm/plat-s3c24xx/clock-dclk.c                 |    8 ++--
 arch/arm/plat-s3c24xx/cpu-freq-debugfs.c           |    2 +-
 arch/arm/plat-s3c24xx/cpu-freq.c                   |    8 ++--
 arch/arm/plat-s3c24xx/dma.c                        |   10 ++--
 arch/arm/plat-s3c24xx/irq.c                        |    8 ++--
 arch/arm/plat-s3c24xx/s3c2410-clock.c              |   14 +++---
 arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c      |    8 ++--
 arch/arm/plat-s3c24xx/s3c2410-iotiming.c           |    8 ++--
 arch/arm/plat-s3c24xx/s3c2412-iotiming.c           |    8 ++--
 arch/arm/plat-samsung/adc.c                        |    4 +-
 arch/arm/plat-samsung/clock-clksrc.c               |    6 +--
 arch/arm/plat-samsung/clock.c                      |    8 ++--
 arch/arm/plat-samsung/cpu.c                        |    2 +-
 arch/arm/plat-samsung/dev-backlight.c              |    6 +--
 arch/arm/plat-samsung/dev-uart.c                   |    2 +-
 arch/arm/plat-samsung/devs.c                       |   42 ++++++++---------
 .../include/plat-samsung/cpu-freq-core.h           |    2 +-
 .../include/plat-samsung/debug-macro.S             |    2 +-
 .../plat-samsung/include/plat-samsung/dma-pl330.h  |    2 +-
 .../include/plat-samsung/dma-s3c24xx.h             |    2 +-
 arch/arm/plat-samsung/include/plat-samsung/dma.h   |    2 +-
 .../plat-samsung/include/plat-samsung/gpio-core.h  |    2 +-
 .../plat-samsung/include/plat-samsung/gpio-fns.h   |    2 +-
 .../plat-samsung/include/plat-samsung/map-s3c.h    |    2 +-
 .../plat-samsung/include/plat-samsung/map-s5p.h    |    2 +-
 .../plat-samsung/include/plat-samsung/regs-fb-v4.h |    2 +-
 arch/arm/plat-samsung/include/plat-samsung/sdhci.h |    2 +-
 .../plat-samsung/include/plat-samsung/uncompress.h |    4 +-
 .../include/plat-samsung/watchdog-reset.h          |    4 +-
 arch/arm/plat-samsung/init.c                       |    8 ++--
 arch/arm/plat-samsung/irq-vic-timer.c              |    6 +--
 arch/arm/plat-samsung/platformdata.c               |    4 +-
 arch/arm/plat-samsung/pm-check.c                   |    2 +-
 arch/arm/plat-samsung/pm-gpio.c                    |    4 +-
 arch/arm/plat-samsung/pm.c                         |    4 +-
 arch/arm/plat-samsung/pwm-clock.c                  |    8 ++--
 arch/arm/plat-samsung/s5p-clock.c                  |    6 +--
 arch/arm/plat-samsung/s5p-dev-mfc.c                |    6 +--
 arch/arm/plat-samsung/s5p-dev-uart.c               |    2 +-
 arch/arm/plat-samsung/s5p-irq-eint.c               |    8 ++--
 arch/arm/plat-samsung/s5p-irq-gpioint.c            |    4 +-
 arch/arm/plat-samsung/s5p-irq-pm.c                 |    6 +--
 arch/arm/plat-samsung/s5p-irq.c                    |    6 +--
 arch/arm/plat-samsung/s5p-pm.c                     |    2 +-
 arch/arm/plat-samsung/s5p-time.c                   |    6 +--
 arch/arm/plat-samsung/time.c                       |    6 +--
 arch/arm/plat-samsung/wakeup-mask.c                |    4 +-
 arch/arm/plat-spear/shirq.c                        |    2 +-
 arch/arm/plat-versatile/clcd.c                     |    2 +-
 arch/arm/plat-versatile/fpga-irq.c                 |    2 +-
 arch/arm/plat-versatile/sched-clock.c              |    2 +-
 drivers/ata/pata_at91.c                            |    4 +-
 drivers/ata/pata_palmld.c                          |    2 +-
 drivers/ata/pata_pxa.c                             |    6 +--
 drivers/ata/pata_samsung_cf.c                      |    4 +-
 drivers/char/hw_random/omap-rng.c                  |    2 +-
 drivers/char/msm_smd_pkt.c                         |    2 +-
 drivers/clk/clk-u300.c                             |    2 +-
 drivers/clk/mxs/clk-imx23.c                        |    4 +-
 drivers/clk/mxs/clk-imx28.c                        |    4 +-
 drivers/clocksource/clksrc-dbx500-prcmu.c          |    4 +-
 drivers/cpufreq/exynos-cpufreq.c                   |    2 +-
 drivers/cpufreq/omap-cpufreq.c                     |    8 ++--
 drivers/crypto/ixp4xx_crypto.c                     |    4 +-
 drivers/crypto/omap-aes.c                          |    4 +-
 drivers/crypto/omap-sham.c                         |    4 +-
 drivers/crypto/s5p-sss.c                           |    4 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |    6 +--
 drivers/crypto/ux500/hash/hash_core.c              |    4 +-
 drivers/devfreq/exynos4_bus.c                      |    2 +-
 drivers/dma/at_hdmac_regs.h                        |    2 +-
 drivers/dma/coh901318.c                            |    2 +-
 drivers/dma/coh901318_lli.c                        |    2 +-
 drivers/dma/coh901318_lli.h                        |    2 +-
 drivers/dma/imx-sdma.c                             |    6 +--
 drivers/dma/ipu/ipu_idmac.c                        |    2 +-
 drivers/dma/ipu/ipu_irq.c                          |    2 +-
 drivers/dma/mmp_tdma.c                             |    4 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/dma/omap-dma.c                             |    2 +-
 drivers/dma/ste_dma40.c                            |    2 +-
 drivers/dma/ste_dma40_ll.c                         |    2 +-
 drivers/gpio/gpio-ep93xx.c                         |    4 +-
 drivers/gpio/gpio-ks8695.c                         |    6 +--
 drivers/gpio/gpio-lpc32xx.c                        |    8 ++--
 drivers/gpio/gpio-msm-v1.c                         |    6 +--
 drivers/gpio/gpio-msm-v2.c                         |    4 +-
 drivers/gpio/gpio-samsung.c                        |   12 ++---
 drivers/gpio/gpio-tegra.c                          |    4 +-
 drivers/gpio/gpio-tnetv107x.c                      |    4 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/hwmon/s3c-hwmon.c                          |    4 +-
 drivers/i2c/busses/i2c-at91.c                      |    6 +--
 drivers/i2c/busses/i2c-s3c2410.c                   |    4 +-
 drivers/iio/adc/at91_adc.c                         |    2 +-
 drivers/input/keyboard/davinci_keyscan.c           |    6 +--
 drivers/input/keyboard/ep93xx_keypad.c             |    4 +-
 drivers/input/keyboard/jornada720_kbd.c            |    6 +--
 drivers/input/keyboard/nomadik-ske-keypad.c        |    2 +-
 drivers/input/keyboard/omap-keypad.c               |    6 +--
 drivers/input/keyboard/pxa27x_keypad.c             |    2 +-
 drivers/input/keyboard/pxa930_rotary.c             |    2 +-
 drivers/input/keyboard/spear-keyboard.c            |    2 +-
 drivers/input/keyboard/tegra-kbc.c                 |    4 +-
 drivers/input/keyboard/w90p910_keypad.c            |    2 +-
 drivers/input/mouse/pxa930_trkball.c               |    4 +-
 drivers/input/serio/ams_delta_serio.c              |    4 +-
 drivers/input/touchscreen/jornada720_ts.c          |    6 +--
 drivers/input/touchscreen/s3c2410_ts.c             |    6 +--
 drivers/input/touchscreen/tnetv107x-ts.c           |    2 +-
 drivers/iommu/exynos-iommu.c                       |    2 +-
 drivers/iommu/msm_iommu.c                          |    4 +-
 drivers/iommu/msm_iommu_dev.c                      |    6 +--
 drivers/iommu/omap-iommu-debug.c                   |    6 +--
 drivers/iommu/omap-iommu.c                         |    4 +-
 drivers/iommu/omap-iovmm.c                         |    6 +--
 drivers/iommu/tegra-smmu.c                         |    6 +--
 drivers/leds/leds-netxbig.c                        |    2 +-
 drivers/leds/leds-ns2.c                            |    2 +-
 drivers/leds/leds-s3c24xx.c                        |    6 +--
 drivers/media/video/davinci/isif.c                 |    2 +-
 drivers/media/video/davinci/vpbe_display.c         |    2 +-
 drivers/media/video/davinci/vpbe_osd.c             |    4 +-
 drivers/media/video/davinci/vpbe_venc.c            |    6 +--
 drivers/media/video/davinci/vpif.c                 |    2 +-
 drivers/media/video/davinci/vpss.c                 |    2 +-
 drivers/media/video/mx1_camera.c                   |    8 ++--
 drivers/media/video/mx2_camera.c                   |    4 +-
 drivers/media/video/mx3_camera.c                   |    6 +--
 drivers/media/video/omap/omap_vout.c               |    4 +-
 drivers/media/video/omap/omap_vout_vrfb.c          |    4 +-
 drivers/media/video/omap/omap_voutdef.h            |    2 +-
 drivers/media/video/omap/omap_voutlib.c            |    2 +-
 drivers/media/video/omap1_camera.c                 |    2 +-
 drivers/media/video/omap3isp/isp.h                 |    4 +-
 drivers/media/video/omap3isp/ispreg.h              |    2 +-
 drivers/media/video/omap3isp/ispstat.h             |    2 +-
 drivers/media/video/omap3isp/ispvideo.c            |    6 +--
 drivers/media/video/s5p-fimc/mipi-csis.c           |    2 +-
 drivers/media/video/s5p-tv/sii9234_drv.c           |    2 +-
 drivers/mfd/db8500-prcmu.c                         |    8 ++--
 drivers/mfd/mcp-sa11x0.c                           |    4 +-
 drivers/mfd/menelaus.c                             |    2 +-
 drivers/mfd/omap-usb-host.c                        |    4 +-
 drivers/mfd/ucb1x00-ts.c                           |    2 +-
 drivers/mmc/host/davinci_mmc.c                     |    4 +-
 drivers/mmc/host/msm_sdcc.c                        |    8 ++--
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mmc/host/omap.c                            |   10 ++--
 drivers/mmc/host/omap_hsmmc.c                      |    6 +--
 drivers/mmc/host/s3cmci.c                          |    6 +--
 drivers/mmc/host/sdhci-cns3xxx.c                   |    2 +-
 drivers/mmc/host/sdhci-esdhc-imx.c                 |    2 +-
 drivers/mmc/host/sdhci-s3c.c                       |    4 +-
 drivers/mmc/host/sdhci-tegra.c                     |    4 +-
 drivers/mtd/maps/autcpu12-nvram.c                  |    4 +-
 drivers/mtd/nand/ams-delta.c                       |    2 +-
 drivers/mtd/nand/autcpu12.c                        |    4 +-
 drivers/mtd/nand/bcm_umi_nand.c                    |    8 ++--
 drivers/mtd/nand/cmx270_nand.c                     |    2 +-
 drivers/mtd/nand/davinci_nand.c                    |    4 +-
 drivers/mtd/nand/mxc_nand.c                        |    4 +-
 drivers/mtd/nand/nand_bcm_umi.c                    |    2 +-
 drivers/mtd/nand/nand_bcm_umi.h                    |    4 +-
 drivers/mtd/nand/nomadik_nand.c                    |    4 +-
 drivers/mtd/nand/omap2.c                           |    6 +--
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c                     |    2 +-
 drivers/mtd/nand/s3c2410.c                         |    4 +-
 drivers/mtd/onenand/omap2.c                        |    8 ++--
 drivers/mtd/onenand/samsung.c                      |    2 +-
 drivers/net/ethernet/cadence/at91_ether.c          |    4 +-
 drivers/net/ethernet/micrel/ks8695net.c            |    6 +--
 drivers/net/ethernet/netx-eth.c                    |   10 ++--
 drivers/net/ethernet/smsc/smc91x.h                 |    4 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    6 +--
 drivers/net/wan/ixp4xx_hss.c                       |    4 +-
 drivers/pcmcia/at91_cf.c                           |    8 ++--
 drivers/pcmcia/omap_cf.c                           |    4 +-
 drivers/pcmcia/pxa2xx_balloon3.c                   |    2 +-
 drivers/pcmcia/pxa2xx_base.c                       |    6 +--
 drivers/pcmcia/pxa2xx_e740.c                       |    2 +-
 drivers/pcmcia/pxa2xx_hx4700.c                     |    2 +-
 drivers/pcmcia/pxa2xx_mainstone.c                  |    4 +-
 drivers/pcmcia/pxa2xx_palmld.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtc.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtx.c                     |    2 +-
 drivers/pcmcia/pxa2xx_trizeps4.c                   |    4 +-
 drivers/pcmcia/pxa2xx_viper.c                      |    2 +-
 drivers/pcmcia/pxa2xx_vpac270.c                    |    2 +-
 drivers/pcmcia/sa1100_assabet.c                    |    2 +-
 drivers/pcmcia/sa1100_cerf.c                       |    4 +-
 drivers/pcmcia/sa1100_h3600.c                      |    4 +-
 drivers/pcmcia/sa1100_nanoengine.c                 |    4 +-
 drivers/pcmcia/sa1100_shannon.c                    |    4 +-
 drivers/pcmcia/sa1100_simpad.c                     |    4 +-
 drivers/pcmcia/sa1111_badge4.c                     |    4 +-
 drivers/pcmcia/sa1111_lubbock.c                    |    4 +-
 drivers/pcmcia/sa1111_neponset.c                   |    4 +-
 drivers/pinctrl/pinctrl-coh901.c                   |    2 +-
 drivers/pinctrl/pinctrl-nomadik.c                  |    4 +-
 drivers/pinctrl/pinctrl-nomadik.h                  |    2 +-
 drivers/pinctrl/pinctrl-tegra.c                    |    2 +-
 drivers/power/collie_battery.c                     |    2 +-
 drivers/power/s3c_adc_battery.c                    |    2 +-
 drivers/power/tosa_battery.c                       |    2 +-
 drivers/ptp/ptp_ixp46x.c                           |    2 +-
 drivers/pwm/pwm-samsung.c                          |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |    4 +-
 drivers/rtc/rtc-at91rm9200.c                       |    2 +-
 drivers/rtc/rtc-at91sam9.c                         |    6 +--
 drivers/rtc/rtc-s3c.c                              |    2 +-
 drivers/spi/spi-davinci.c                          |    4 +-
 drivers/spi/spi-ep93xx.c                           |    4 +-
 drivers/spi/spi-nuc900.c                           |    2 +-
 drivers/spi/spi-omap-100k.c                        |    2 +-
 drivers/spi/spi-omap-uwire.c                       |    4 +-
 drivers/spi/spi-omap2-mcspi.c                      |    4 +-
 drivers/spi/spi-s3c24xx-fiq.S                      |    2 +-
 drivers/spi/spi-s3c24xx.c                          |    4 +-
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/staging/nvec/nvec.c                        |    4 +-
 drivers/staging/omapdrm/omap_dmm_tiler.h           |    2 +-
 drivers/staging/tidspbridge/core/dsp-clock.c       |    4 +-
 drivers/staging/tidspbridge/core/tiomap3430.c      |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430_pwr.c  |    2 +-
 drivers/staging/tidspbridge/core/tiomap_io.c       |    2 +-
 drivers/staging/tidspbridge/core/ue_deh.c          |    2 +-
 .../tidspbridge/include/dspbridge/host_os.h        |    4 +-
 drivers/staging/tidspbridge/rmgr/drv_interface.c   |    2 +-
 drivers/tty/serial/imx.c                           |    2 +-
 drivers/tty/serial/msm_smd_tty.c                   |    2 +-
 drivers/tty/serial/netx-serial.c                   |    4 +-
 drivers/tty/serial/omap-serial.c                   |    6 +--
 drivers/tty/serial/samsung.c                       |    4 +-
 drivers/usb/gadget/at91_udc.c                      |   10 ++--
 drivers/usb/gadget/atmel_usba_udc.c                |    4 +-
 drivers/usb/gadget/omap_udc.c                      |    2 +-
 drivers/usb/gadget/pxa25x_udc.c                    |    4 +-
 drivers/usb/gadget/pxa25x_udc.h                    |    2 +-
 drivers/usb/gadget/s3c-hsudc.c                     |    2 +-
 drivers/usb/gadget/s3c2410_udc.c                   |    4 +-
 drivers/usb/host/ehci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ehci-mxc.c                        |    4 +-
 drivers/usb/host/ehci-omap.c                       |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 drivers/usb/host/ehci-s5p.c                        |    4 +-
 drivers/usb/host/ehci-tegra.c                      |    4 +-
 drivers/usb/host/imx21-hcd.h                       |    2 +-
 drivers/usb/host/ohci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ohci-da8xx.c                      |    4 +-
 drivers/usb/host/ohci-exynos.c                     |    2 +-
 drivers/usb/host/ohci-omap.c                       |    4 +-
 drivers/usb/host/ohci-omap3.c                      |    2 +-
 drivers/usb/host/ohci-pxa27x.c                     |    6 +--
 drivers/usb/host/ohci-s3c2410.c                    |    2 +-
 drivers/usb/host/ohci-sa1111.c                     |    4 +-
 drivers/usb/musb/am35x.c                           |    2 +-
 drivers/usb/musb/da8xx.c                           |    4 +-
 drivers/usb/musb/musb_dsps.c                       |    2 +-
 drivers/usb/musb/omap2430.h                        |    2 +-
 drivers/usb/musb/tusb6010_omap.c                   |    4 +-
 drivers/usb/otg/isp1301_omap.c                     |    2 +-
 drivers/video/acornfb.c                            |    4 +-
 drivers/video/backlight/jornada720_bl.c            |    4 +-
 drivers/video/backlight/jornada720_lcd.c           |    4 +-
 drivers/video/backlight/omap1_bl.c                 |    4 +-
 drivers/video/backlight/tosa_bl.c                  |    2 +-
 drivers/video/backlight/tosa_lcd.c                 |    2 +-
 drivers/video/clps711xfb.c                         |    4 +-
 drivers/video/cyber2000fb.c                        |    2 +-
 drivers/video/exynos/exynos_mipi_dsi.c             |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_common.c      |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_lowlevel.c    |    2 +-
 drivers/video/imxfb.c                              |    4 +-
 drivers/video/msm/mddi.c                           |    8 ++--
 drivers/video/msm/mddi_client_dummy.c              |    2 +-
 drivers/video/msm/mddi_client_nt35399.c            |    2 +-
 drivers/video/msm/mddi_client_toshiba.c            |    2 +-
 drivers/video/msm/mdp.c                            |    4 +-
 drivers/video/msm/mdp_hw.h                         |    4 +-
 drivers/video/msm/mdp_ppp.c                        |    2 +-
 drivers/video/msm/msm_fb.c                         |    4 +-
 drivers/video/mx3fb.c                              |    8 ++--
 drivers/video/nuc900fb.c                           |    8 ++--
 drivers/video/omap/hwa742.c                        |    2 +-
 drivers/video/omap/lcd_ams_delta.c                 |    4 +-
 drivers/video/omap/lcd_inn1510.c                   |    2 +-
 drivers/video/omap/lcd_mipid.c                     |    2 +-
 drivers/video/omap/lcd_osk.c                       |    2 +-
 drivers/video/omap/lcd_palmte.c                    |    2 +-
 drivers/video/omap/lcdc.c                          |    4 +-
 drivers/video/omap/omapfb_main.c                   |    2 +-
 drivers/video/omap/sossi.c                         |    2 +-
 drivers/video/omap2/dss/dispc.c                    |    2 +-
 drivers/video/omap2/dss/dpi.c                      |    2 +-
 drivers/video/omap2/dss/dsi.c                      |    2 +-
 drivers/video/omap2/dss/dss.c                      |    4 +-
 drivers/video/omap2/dss/dss_features.c             |    2 +-
 drivers/video/omap2/dss/overlay.c                  |    2 +-
 drivers/video/omap2/dss/venc.c                     |    2 +-
 drivers/video/omap2/omapfb/omapfb-ioctl.c          |    4 +-
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 +-
 drivers/video/omap2/omapfb/omapfb-sysfs.c          |    2 +-
 drivers/video/omap2/vram.c                         |    4 +-
 drivers/video/omap2/vrfb.c                         |    4 +-
 drivers/video/pxafb.c                              |    6 +--
 drivers/video/s3c-fb.c                             |    4 +-
 drivers/video/sa1100fb.c                           |    4 +-
 drivers/video/vt8500lcdfb.c                        |    2 +-
 drivers/video/wm8505fb.c                           |    2 +-
 drivers/watchdog/at91rm9200_wdt.c                  |    2 +-
 drivers/watchdog/omap_wdt.c                        |    2 +-
 drivers/watchdog/s3c2410_wdt.c                     |    2 +-
 include/linux/mfd/davinci_voicecodec.h             |    2 +-
 include/linux/mfd/dbx500-prcmu.h                   |    2 +-
 include/linux/omapfb.h                             |    2 +-
 include/linux/platform_data/atmel-aes.h            |    2 +-
 include/linux/power/smartreflex.h                  |    2 +-
 include/linux/spi/pxa2xx_spi.h                     |    2 +-
 sound/arm/pxa2xx-ac97-lib.c                        |    6 +--
 sound/arm/pxa2xx-ac97.c                            |    4 +-
 sound/arm/pxa2xx-pcm-lib.c                         |    2 +-
 sound/arm/pxa2xx-pcm.h                             |    2 +-
 sound/atmel/ac97c.c                                |    6 +--
 sound/oss/vidc.c                                   |    2 +-
 sound/oss/vidc_fill.S                              |    2 +-
 sound/oss/waveartist.c                             |    2 +-
 sound/soc/atmel/atmel_ssc_dai.c                    |    2 +-
 sound/soc/atmel/sam9g20_wm8731.c                   |    4 +-
 sound/soc/atmel/snd-soc-afeb9260.c                 |    2 +-
 sound/soc/davinci/davinci-evm.c                    |    6 +--
 sound/soc/davinci/davinci-i2s.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.h                  |    2 +-
 sound/soc/davinci/davinci-pcm.c                    |    4 +-
 sound/soc/davinci/davinci-pcm.h                    |    4 +-
 sound/soc/davinci/davinci-sffsdr.c                 |    2 +-
 sound/soc/ep93xx/edb93xx.c                         |    2 +-
 sound/soc/ep93xx/ep93xx-ac97.c                     |    2 +-
 sound/soc/ep93xx/ep93xx-i2s.c                      |    6 +--
 sound/soc/ep93xx/ep93xx-pcm.c                      |    6 +--
 sound/soc/ep93xx/simone.c                          |    2 +-
 sound/soc/ep93xx/snappercl15.c                     |    2 +-
 sound/soc/fsl/imx-pcm-fiq.c                        |    4 +-
 sound/soc/fsl/imx-ssi.c                            |    4 +-
 sound/soc/fsl/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    4 +-
 sound/soc/kirkwood/kirkwood-t5325.c                |    4 +-
 sound/soc/mxs/mxs-saif.c                           |    4 +-
 sound/soc/nuc900/nuc900-ac97.c                     |    2 +-
 sound/soc/nuc900/nuc900-pcm.c                      |    2 +-
 sound/soc/omap/am3517evm.c                         |    6 +--
 sound/soc/omap/ams-delta.c                         |    4 +-
 sound/soc/omap/igep0020.c                          |    6 +--
 sound/soc/omap/mcbsp.c                             |    2 +-
 sound/soc/omap/n810.c                              |    4 +-
 sound/soc/omap/omap-abe-twl6040.c                  |    4 +-
 sound/soc/omap/omap-dmic.c                         |    2 +-
 sound/soc/omap/omap-hdmi.c                         |    2 +-
 sound/soc/omap/omap-mcbsp.c                        |    4 +-
 sound/soc/omap/omap-mcpdm.c                        |    4 +-
 sound/soc/omap/omap-pcm.c                          |    2 +-
 sound/soc/omap/omap3beagle.c                       |    6 +--
 sound/soc/omap/omap3evm.c                          |    6 +--
 sound/soc/omap/omap3pandora.c                      |    2 +-
 sound/soc/omap/osk5912.c                           |    4 +-
 sound/soc/omap/overo.c                             |    6 +--
 sound/soc/omap/rx51.c                              |    2 +-
 sound/soc/omap/sdp3430.c                           |    6 +--
 sound/soc/omap/zoom2.c                             |    8 ++--
 sound/soc/pxa/corgi.c                              |    4 +-
 sound/soc/pxa/e740_wm9705.c                        |    4 +-
 sound/soc/pxa/e750_wm9705.c                        |    4 +-
 sound/soc/pxa/e800_wm9712.c                        |    4 +-
 sound/soc/pxa/em-x270.c                            |    2 +-
 sound/soc/pxa/hx4700.c                             |    2 +-
 sound/soc/pxa/magician.c                           |    2 +-
 sound/soc/pxa/mioa701_wm9713.c                     |    2 +-
 sound/soc/pxa/mmp-pcm.c                            |    2 +-
 sound/soc/pxa/palm27x.c                            |    4 +-
 sound/soc/pxa/poodle.c                             |    4 +-
 sound/soc/pxa/pxa-ssp.c                            |    4 +-
 sound/soc/pxa/pxa2xx-ac97.c                        |    8 ++--
 sound/soc/pxa/pxa2xx-i2s.c                         |    6 +--
 sound/soc/pxa/spitz.c                              |    2 +-
 sound/soc/pxa/tosa.c                               |    4 +-
 sound/soc/pxa/z2.c                                 |    6 +--
 sound/soc/samsung/ac97.c                           |    4 +-
 sound/soc/samsung/h1940_uda1380.c                  |    4 +-
 sound/soc/samsung/i2s.c                            |    2 +-
 sound/soc/samsung/neo1973_wm8753.c                 |    4 +-
 sound/soc/samsung/pcm.c                            |    4 +-
 sound/soc/samsung/rx1950_uda1380.c                 |    2 +-
 sound/soc/samsung/s3c24xx-i2s.c                    |    2 +-
 sound/soc/samsung/s3c24xx_simtec.c                 |    2 +-
 sound/soc/samsung/s3c24xx_uda134x.c                |    2 +-
 sound/soc/samsung/spdif.c                          |    2 +-
 sound/soc/tegra/tegra30_ahub.c                     |    4 +-
 sound/soc/tegra/tegra_pcm.h                        |    2 +-
 sound/soc/tegra/tegra_wm8903.c                     |    2 +-
 sound/soc/ux500/mop500_ab8500.c                    |    2 +-
 sound/soc/ux500/ux500_msp_dai.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.h                    |    2 +-
 sound/soc/ux500/ux500_pcm.c                        |    2 +-
 2008 files changed, 5935 insertions(+), 5935 deletions(-)

diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
index d8eb01c..f088b4b 100644
--- a/Documentation/spi/ep93xx_spi
+++ b/Documentation/spi/ep93xx_spi
@@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 
-#include <mach/ep93xx_spi.h>
+#include <mach-ep93xx/ep93xx_spi.h>
 
 /* this is our GPIO line used for chip select */
 #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b..4bcb9c7 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -23,7 +23,7 @@
 	.section	".start", "ax"
 
 	/* load board-specific initialization code */
-#include <mach/zboot.h>
+#include <mach-shmobile/zboot.h>
 
 #if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
 	/* Load image from MMC/SD */
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
index bd3d469..ff0aa20 100644
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ b/arch/arm/boot/compressed/sdhi-shmobile.c
@@ -18,7 +18,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sd.h>
 #include <linux/mmc/tmio.h>
-#include <mach/sdhi.h>
+#include <mach-shmobile/sdhi.h>
 
 #define OCR_FASTBOOT		(1<<29)
 #define OCR_HCS			(1<<30)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6f50c67..fd81ffe 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -16,11 +16,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_st.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb732..2b63b60 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -18,10 +18,10 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 
-#include <mach/board.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40..aec1da4 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -27,7 +27,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_st.h>
+#include <mach-at91/at91_st.h>
 
 static unsigned long last_crtr;
 static u32 irqmask;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26..e84bddb 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -17,12 +17,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..cb364af 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,13 +19,13 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_adc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index f40762c..58c830b 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -17,11 +17,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8df5c1b..f2e6805 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,11 +21,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9261_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9261_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b3810..51f4f7e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..26dc600 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -20,11 +20,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9263_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index ffc0957..e3b0d36 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -20,7 +20,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_pit.h>
+#include <mach-at91/at91_pit.h>
 
 
 #define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 7af2e10..6d8da98 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -14,9 +14,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd..45c79b4 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 0607399..242c850 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,14 +25,14 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/at91_adc.h>
-#include <mach/board.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
-#include <mach/atmel-mci.h>
+#include <mach-at91/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9g45_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
+#include <mach-at91/atmel-mci.h>
 
 #include <media/atmel-isi.h>
 
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 9d45718..0726dad 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -11,9 +11,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..b5f4e1d 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9n12.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72ce50a..3c17719 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -16,12 +16,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..cf41235 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -17,12 +17,12 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9rl_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9rl_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..d919d0e 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e6..e3224b1 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -17,10 +17,10 @@
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
-#include <mach/at91x40.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_st.h>
-#include <mach/timex.h>
+#include <mach-at91/at91x40.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/timex.h>
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a..478fa8a 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -24,9 +24,9 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/time.h>
-#include <mach/at91_tc.h>
+#include <mach-at91/at91_tc.h>
 
 #define at91_tc_read(field) \
 	__raw_readl(AT91_TC + field)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 22d8856..bbfe99a 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be19..ae1469e 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -34,7 +34,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,8 +43,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 477e708..8e3b25a 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -29,7 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f..b2f21fc 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b..2d5334c 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -39,12 +39,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043..73934ef 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -27,7 +27,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,11 +36,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc31..40f5e99 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 872871a..df54c811 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4..346b427 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,8 +15,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 01f66e9..5a0365d 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -24,11 +24,11 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 #include "generic.h"
 
 static void __init at91eb01_init_irq(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3f..3ae9f49 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,8 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb2..f9d2da7 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde..814756e 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -24,11 +24,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a8..d5315ef 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -32,9 +32,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab124..43b5fc2 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -32,7 +32,7 @@
 #include <linux/clk.h>
 #include <linux/w1-gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index a9d5e78..b6d0d6f 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -30,11 +30,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/gsia18s.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/gsia18s.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf..7e98f65 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb8..5b1bf97 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,11 +35,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d..c9e9d89 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 9ca3e32..f809d33 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -29,10 +29,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 1270655..469000d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,10 +37,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e2..0364e46 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -39,11 +39,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf97..9769e97 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e6..2311b39 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43ae..5dfc434 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -24,9 +24,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <linux/gpio.h>
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da7..39546b8 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -28,7 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf..27865bc 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -40,12 +40,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5..e37f30f 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -44,12 +44,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf58..b149347 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -43,12 +43,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee0..cd48ea7 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -34,7 +34,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 3d48ec1..4222519 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -29,7 +29,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <video/atmel_lcdc.h>
 #include <media/soc_camera.h>
 #include <media/atmel-isi.h>
@@ -42,11 +42,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ea..80f805c 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,11 +29,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index a4e031a..dada12c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -31,10 +31,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae16..64c7010 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -25,9 +25,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9..dacfc5b 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -40,11 +40,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340..fed4f0a 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -42,12 +42,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index de2ec6b..c5789a1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -25,9 +25,9 @@
 #include <linux/io.h>
 #include <linux/of_address.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include <asm/proc-fns.h>
 
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c63815..6d03dc6 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -21,7 +21,7 @@
 #include <linux/export.h>
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #include "pm.h"
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..ce21de2 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -28,8 +28,8 @@
 
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pio.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
index d8aeb27..c871a14 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
@@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
 #define AT91_MEMCTRL_SDRAMC	1
 #define AT91_MEMCTRL_DDRSDR	2
 
-#include <mach/at91rm9200_sdramc.h>
-#include <mach/at91sam9_ddrsdr.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
+#include <mach-at91/at91sam9_ddrsdr.h>
+#include <mach-at91/at91sam9_sdramc.h>
 
 #endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
index 175e1fd..2f6393e 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
@@ -16,7 +16,7 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #ifndef __ASSEMBLY__
 struct sam9_smc_config {
diff --git a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
index 998cb0c..d8f4109 100644
--- a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_ATMEL_MCI_H
 #define __MACH_ATMEL_MCI_H
 
-#include <mach/at_hdmac.h>
+#include <mach-at91/at_hdmac.h>
 
 /**
  * struct mci_dma_data - DMA data for MCI interface
diff --git a/arch/arm/mach-at91/include/mach-at91/debug-macro.S b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
index c6bb9e2..8a1599c 100644
--- a/arch/arm/mach-at91/include/mach-at91/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
@@ -11,8 +11,8 @@
  *
 */
 
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_dbgu.h>
 
 #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
 #define AT91_DBGU AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/include/mach-at91/hardware.h b/arch/arm/mach-at91/include/mach-at91/hardware.h
index 09242b6..caef81c 100644
--- a/arch/arm/mach-at91/include/mach-at91/hardware.h
+++ b/arch/arm/mach-at91/include/mach-at91/hardware.h
@@ -23,16 +23,16 @@
 #define AT91_BASE_DBGU1	0xffffee00
 
 #if defined(CONFIG_ARCH_AT91X40)
-#include <mach/at91x40.h>
+#include <mach-at91/at91x40.h>
 #else
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91sam9n12.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91sam9n12.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach-at91/memory.h b/arch/arm/mach-at91/include/mach-at91/memory.h
index 401c207..88c06fd 100644
--- a/arch/arm/mach-at91/include/mach-at91/memory.h
+++ b/arch/arm/mach-at91/include/mach-at91/memory.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach-at91/timex.h b/arch/arm/mach-at91/include/mach-at91/timex.h
index 5e917a6..f4e72e2 100644
--- a/arch/arm/mach-at91/include/mach-at91/timex.h
+++ b/arch/arm/mach-at91/include/mach-at91/timex.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #ifdef CONFIG_ARCH_AT91X40
 
diff --git a/arch/arm/mach-at91/include/mach-at91/uncompress.h b/arch/arm/mach-at91/include/mach-at91/uncompress.h
index 6f6118d..914feb7 100644
--- a/arch/arm/mach-at91/include/mach-at91/uncompress.h
+++ b/arch/arm/mach-at91/include/mach-at91/uncompress.h
@@ -24,10 +24,10 @@
 
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
-#include <mach/at91_dbgu.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/cpu.h>
 
 void __iomem *at91_uart;
 
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 1e02c0e..eeddbec 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,7 +33,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include <mach/at91_aic.h>
+#include <mach-at91/at91_aic.h>
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..f921b1e 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d865..a5b940e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,9 +25,9 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 #include "pm.h"
@@ -36,8 +36,8 @@
  * Show the reason for the previous system reset.
  */
 
-#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/at91_rstc.h>
+#include <mach-at91/at91_shdwc.h>
 
 static void __init show_reset_status(void)
 {
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c..529072a 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,8 +11,8 @@
 #ifndef __ARCH_ARM_MACH_AT91_PM
 #define __ARCH_ARM_MACH_AT91_PM
 
-#include <mach/at91_ramc.h>
-#include <mach/at91rm9200_sdramc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..8f263c6 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,9 +13,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_ramc.h>
 
 
 #ifdef CONFIG_SOC_AT91SAM9263
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 99a0a1d..be40bf2 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -14,7 +14,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb..0fe58d5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -14,11 +14,11 @@
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..f7469da 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -32,11 +32,11 @@
 #include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/dma.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <cfg_global.h>
 
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
index ad237a4..108845f 100644
--- a/arch/arm/mach-bcmring/clock.c
+++ b/arch/arm/mach-bcmring/clock.c
@@ -22,10 +22,10 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/hw_cfg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
index 5e0b981..2e01614 100644
--- a/arch/arm/mach-bcmring/clock.h
+++ b/arch/arm/mach-bcmring/clock.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 #define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a parent */
 #define CLK_TYPE_PLL1            2	/* PPL1 */
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb19..4d089b3 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -29,8 +29,8 @@
 #include <linux/amba/bus.h>
 #include <linux/clkdev.h>
 
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
+#include <mach-bcmring/csp/mm_addr.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -48,9 +48,9 @@
 #include "clock.h"
 
 #include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/secHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
 static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff..270689d 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75..48e5977 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d88..0aee4f2 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -14,8 +14,8 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 #include <csp/intcHw.h>
 #include <csp/cache.h>
 
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
index 54ad964..d466c49 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -23,7 +23,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e..4a9675a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -30,9 +30,9 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- External Function Prototypes ------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f3283..f4e883a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -30,8 +30,8 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
 
 extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* Declared in dmacHw.c */
 
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e4..220e314 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -30,7 +30,7 @@
 #include <csp/stdint.h>
 
 #include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
 #define tmrHw_MILLISEC_PER_SEC              (1000)
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index e5fd241..e90cfdf 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -31,11 +31,11 @@
 #include <linux/proc_fs.h>
 #include <linux/slab.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 #include <linux/pfn.h>
 #include <linux/atomic.h>
-#include <mach/dma.h>
+#include <mach-bcmring/dma.h>
 
 /* ---- Public Variables ------------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
index e6a1dc4..97d8a04 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -26,7 +26,7 @@
 #include <stddef.h>
 
 #include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
 
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
 
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
index 1c639c8..eb7d3ae 100644
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -28,7 +28,7 @@
 #define _INTCHW_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 /* ---- Public Variable Externs ------------------------------------------ */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
index 56654d2..23ac669 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -69,7 +69,7 @@
 /*  */
 
 #if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/interrupt.h>
 
 #define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
index 933ce68..4a1ecfa 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
@@ -16,7 +16,7 @@
 #define CAP_INLINE_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
+#include <mach-bcmring/csp/cap.h>
 #include <cfg_global.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
index 1619733..fe57b08 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
@@ -20,7 +20,7 @@
 #include <csp/stdint.h>
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
 
 /* ---- Public Constants and Types ---------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
index 03238c2..108209c 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
@@ -19,8 +19,8 @@
 
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 typedef enum {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
index b162448..85b13d7 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
@@ -23,9 +23,9 @@
 #ifndef CHIPCHW_REG_H
 #define CHIPCHW_REG_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 #include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
+#include <mach-bcmring/csp/ddrcReg.h>
 
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
index f1b68e2..462c099 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
@@ -33,7 +33,7 @@ extern "C" {
 #include <csp/reg.h>
 #include <csp/stdint.h>
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
index f1ecf96..1f5263f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
@@ -25,7 +25,7 @@
 #define _DMACHW_REG_H
 
 #include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Data type for 64 bit little endian register */
 typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
index cfa91be..aad4e17 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
@@ -19,10 +19,10 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
+#include <mach-bcmring/csp/cap_inline.h>
 
 #if defined(__KERNEL__)
-#include <mach/memory_settings.h>
+#include <mach-bcmring/memory_settings.h>
 #else
 #include <hw_cfg.h>
 #endif
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
index 0aeb6a6..0770d7d 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
index de92ec6..dcb1eae 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
@@ -27,7 +27,7 @@
 #define _MM_IO_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #if !defined(CSP_SIMULATION)
 #include <cfg_global.h>
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
index d15f5f3..18279ce 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
@@ -26,7 +26,7 @@
 #ifndef SECHW_DEF_H
 #define SECHW_DEF_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Bit mask for various secure device */
 #define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
@@ -95,6 +95,6 @@ static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void);
 
-#include <mach/csp/secHw_inline.h>
+#include <mach-bcmring/csp/secHw_inline.h>
 
 #endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
index 3080ac7..e6069f5 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
@@ -23,8 +23,8 @@
 #ifndef _TMRHW_REG_H
 #define _TMRHW_REG_H
 
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/hw_cfg.h>
 /* Base address */
 #define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
index 7254378..366caa3 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
@@ -28,7 +28,7 @@
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
 #include <csp/dmacHw.h>
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
index 2f316f0..8967896 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
@@ -17,9 +17,9 @@
  * Low-level IRQ helper macros for BCMRing-based platforms
  *
  */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/irqs.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 		ldr	\base, =(MM_IO_BASE_INTC0)
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
index 6ae20a6..c708efd 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
@@ -23,7 +23,7 @@
 
 #include <asm/sizes.h>
 #include <cfg_global.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Hardware addresses of major areas.
  *  *_START is the physical address
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
index 387376f..ec773c2 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/reg_umi.h>
+#include <mach-bcmring/reg_umi.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
index 0992842..f659cc1 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
index 9c9821b..b11fb3f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
 #define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index 437fa68..aa88cac 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -22,12 +22,12 @@
 #include <linux/timer.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 static void bcmring_mask_irq0(struct irq_data *d)
 {
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78e..411fa2b 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -17,8 +17,8 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 #define IO_DESC(va, sz) { .virtual = va, \
 	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7..ba9754d 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include <csp/tmrHw.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
 /* The real time clock should probably be the real linux clocksource. */
 /* In the meantime, this file should agree with core.c as to the */
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3fb79a1..82ec281 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/sizes.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,7 +33,7 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
+#include <mach-clps711x/autcpu12.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index c314f49..6693600 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index a70147e..177fb74 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293b..5b4fa62 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -28,7 +28,7 @@
 #include <linux/sched.h>
 
 #include <asm/sizes.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 4372f06..6d3e94e 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/sizes.h>
  
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 3a3f0b7..12a1368 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/initrd.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
index 118b3d9..52bd3ef 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 		.macro	addruart, rp, rv, tmp
 #ifndef CONFIG_DEBUG_CLPS711X_UART2
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
index 56e5c2c..889521e 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
@@ -7,7 +7,7 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 		.macro	get_irqnr_preamble, base, tmp
 		.endm
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
index 13a64fc..29f3409 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
@@ -22,7 +22,7 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
 
-#include <mach/clps711x.h>
+#include <mach-clps711x/clps711x.h>
 
 #define CLPS711X_VIRT_BASE	IOMEM(0xff000000)
 
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h b/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
index 7b28d6a..92a5ee1 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <mach/clps711x.h>
+#include <mach-clps711x/clps711x.h>
 
 #ifdef CONFIG_DEBUG_CLPS711X_UART2
 #define SYSFLGx	SYSFLG2
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index bbc449f..b0b684f 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index f266d90..e83d055 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
+#include <mach-clps711x/syspld.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2c5fb4c..6e663cf 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -30,8 +30,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/irqs.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 031805b..1c7da63 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -17,7 +17,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 #include "core.h"
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 1e40c99..ef5c80c 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -16,9 +16,9 @@
 #include <linux/compiler.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/pm.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/irqs.h>
+#include <mach-cns3xxx/pm.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
index 2ab96f8..a9712a6 100644
--- a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
+++ b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
@@ -15,7 +15,7 @@
 #define IRQ_LOCALWDOG		30
 #define IRQ_TC11MP_GIC_START	32
 
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 
 #ifndef NR_IRQS
 #error "NR_IRQS not defined by the board-specific files"
diff --git a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
index a91b605..8b2a4b6 100644
--- a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
@@ -8,7 +8,7 @@
  */
 
 #include <asm/mach-types.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 
 #define AMBA_UART_DR(base)	(*(volatile unsigned char *)((base) + 0x00))
 #define AMBA_UART_LCRH(base)	(*(volatile unsigned char *)((base) + 0x2c))
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 3113283..873e6cd 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -20,7 +20,7 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <asm/mach/map.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 #include "core.h"
 
 enum cns3xxx_access_type {
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 3645808..40b6e73 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -11,8 +11,8 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/atomic.h>
-#include <mach/cns3xxx.h>
-#include <mach/pm.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/pm.h>
 #include "core.h"
 
 void cns3xxx_pwr_clk_en(unsigned int block)
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 1ce70a9..4ef9dab 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -15,7 +15,7 @@
 #include <linux/module.h>
 #include <linux/time.h>
 
-#include <mach/aemif.h>
+#include <mach-davinci/aemif.h>
 
 /* Timing value configuration */
 
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 0031864..c07754e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -26,13 +26,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/cp_intc.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/da8xx.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/usb.h>
+#include <mach-davinci/aemif.h>
+#include <mach-davinci/spi.h>
 
 #define DA830_EVM_PHY_ID		""
 /*
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0149fb4..6fe905e 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -38,12 +38,12 @@
 #include <asm/mach/arch.h>
 #include <asm/system_info.h>
 
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/nand.h>
-#include <mach/mux.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/aemif.h>
+#include <mach-davinci/spi.h>
 
 #define DA850_EVM_PHY_ID		"davinci_mdio-0:00"
 #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 1c7b1f4..fc915d1 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,11 +26,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 8e77032..02eb053 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,11 +23,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 688a9c5..f661663 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -31,13 +31,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/mux.h>
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mmc.h>
-#include <mach/nand.h>
-#include <mach/keyscan.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/keyscan.h>
 
 #include <media/tvp514x.h>
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d34ed55..58ff3e7 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -30,14 +30,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
+#include <mach-davinci/aemif.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 958679a..8f6ddc3 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -36,13 +36,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/serial.h>
-#include <mach/i2c.h>
-#include <mach/nand.h>
-#include <mach/clock.h>
-#include <mach/cdce949.h>
-#include <mach/aemif.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/cdce949.h>
+#include <mach-davinci/aemif.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index beecde3..dce12d5 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -23,12 +23,12 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/common.h>
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/nand.h>
-#include <mach/mux.h>
-#include <mach/spi.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/spi.h>
 
 #define MITYOMAPL138_PHY_ID		""
 
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5de69f2..26034db 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -30,13 +30,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index dc1208e..ee4ae67 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/mux.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/mux.h>
 
 #define HAWKBOARD_PHY_ID		"davinci_mdio-0:07"
 #define DA850_HAWK_MMCSD_CD_PIN		GPIO_TO_PIN(3, 12)
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 9078acf..19c84ce 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -35,11 +35,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/usb.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ac4e003..1e58d68 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -30,11 +30,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
-#include <mach/mux.h>
-#include <mach/cp_intc.h>
-#include <mach/tnetv107x.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/tnetv107x.h>
 
 #define EVM_MMC_WP_GPIO		21
 #define EVM_MMC_CD_GPIO		24
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index f2232ca..3794178 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,8 +19,8 @@
 #include <linux/i2c.h>
 #include <linux/module.h>
 
-#include <mach/clock.h>
-#include <mach/cdce949.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/cdce949.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 34668ea..c26fd64 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -20,11 +20,11 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
+#include <mach-davinci/hardware.h>
 
-#include <mach/clock.h>
-#include <mach/psc.h>
-#include <mach/cputype.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/cputype.h>
 #include "clock.h"
 
 static LIST_HEAD(clocks);
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 64b0f65..3e997d7 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -17,8 +17,8 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
-#include <mach/common.h>
-#include <mach/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cputype.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 006dae8..51b1513 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -18,8 +18,8 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/common.h>
-#include <mach/cp_intc.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cp_intc.h>
 
 static inline unsigned int cp_intc_read(unsigned offset)
 {
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 4729eaa..4ef3927 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -26,9 +26,9 @@
 #include <linux/platform_device.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
-#include <mach/cpufreq.h>
-#include <mach/common.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/cpufreq.h>
+#include <mach-davinci/common.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 9107691..9d3d884c 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -20,8 +20,8 @@
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
 
-#include <mach/cpuidle.h>
-#include <mach/ddr2.h>
+#include <mach-davinci/cpuidle.h>
+#include <mach-davinci/ddr2.h>
 
 #define DAVINCI_CPUIDLE_MAX_STATES	2
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2..a482e57 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -14,13 +14,13 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/psc.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "clock.h"
 #include "mux.h"
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc84..7a16c6e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -20,15 +20,15 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/psc.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/cpufreq.h>
-#include <mach/pm.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/cpufreq.h>
+#include <mach-davinci/pm.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "clock.h"
 #include "mux.h"
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6..fe9c203 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <mach/hardware.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/keyscan.h>
+#include <mach-davinci/hardware.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 783eab6..d851270 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -17,11 +17,11 @@
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
 
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/cpuidle.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/cpuidle.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 29b17f7..e25ca91 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -19,10 +19,10 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/edma.h>
-#include <mach/tnetv107x.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/tnetv107x.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f96662..31fe1a8 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -14,14 +14,14 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/edma.h>
-#include <mach/mmc.h>
-#include <mach/time.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/time.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..5279a55 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -18,17 +18,17 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/irqs.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/spi.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/spi.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49de..8f55461 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -21,18 +21,18 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/irqs.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <mach/spi.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/keyscan.h>
+#include <mach-davinci/spi.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..6355eaf 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -15,16 +15,16 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/irqs.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1..0c9515e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -16,16 +16,16 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/irqs.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index a685e97..f0093a8 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -25,7 +25,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/edma.h>
+#include <mach-davinci/edma.h>
 
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT		0x00
diff --git a/arch/arm/mach-davinci/include/mach-davinci/asp.h b/arch/arm/mach-davinci/include/mach-davinci/asp.h
index 9aa2409..64e468f 100644
--- a/arch/arm/mach-davinci/include/mach-davinci/asp.h
+++ b/arch/arm/mach-davinci/include/mach-davinci/asp.h
@@ -4,8 +4,8 @@
 #ifndef __ASM_ARCH_DAVINCI_ASP_H
 #define __ASM_ARCH_DAVINCI_ASP_H
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
 
 /* Bases of dm644x and dm355 register banks */
 #define DAVINCI_ASP0_BASE	0x01E02000
---
Intentionally cut off for review. If you managed to read this far, you
get the idea. See the rest at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=d59d6b49ed5287dd0131acda9428fdc0bb0a7365


From arnd at arndb.de  Tue Aug 21 11:12:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:12:04 -0000
Subject: [RFC 4/4] ARM: treewide: manually change more mach-*/*.h includes
In-Reply-To: <1345561880-13231-1-git-send-email-arnd@arndb.de>
References: <1345561880-13231-1-git-send-email-arnd@arndb.de>
Message-ID: <1345561880-13231-5-git-send-email-arnd@arndb.de>

These are lots of device drivers that include machine
specific header files from ARM platforms and that are
not easily scriptable. The changes have been found through
manual inspection and should cause no visible changes
because of the build script that maps the old names to the
new ones.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/char/ds1620.c                                 |    2 +-
 drivers/char/hw_random/ixp4xx-rng.c                   |    2 +-
 drivers/cpufreq/db8500-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos4210-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos4x12-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos5250-cpufreq.c                  |    6 +++---
 drivers/cpufreq/omap-cpufreq.c                        |    2 +-
 drivers/cpufreq/s5pv210-cpufreq.c                     |    2 +-
 drivers/crypto/omap-sham.c                            |    2 +-
 drivers/crypto/tegra-aes.c                            |    2 +-
 drivers/devfreq/exynos4_bus.c                         |    2 +-
 drivers/dma/ep93xx_dma.c                              |    2 +-
 drivers/dma/imx-dma.c                                 |    4 ++--
 drivers/gpio/gpio-omap.c                              |    4 ++--
 drivers/gpio/gpio-pxa.c                               |    8 +++++++-
 drivers/i2c/busses/i2c-acorn.c                        |    2 +-
 drivers/i2c/busses/i2c-davinci.c                      |    4 ++--
 drivers/i2c/busses/i2c-imx.c                          |    4 ++--
 drivers/i2c/busses/i2c-nuc900.c                       |    4 ++--
 drivers/i2c/busses/i2c-tegra.c                        |    2 +-
 drivers/input/misc/ixp4xx-beeper.c                    |    2 +-
 drivers/input/mouse/rpcmouse.c                        |    2 +-
 drivers/input/serio/rpckbd.c                          |    2 +-
 drivers/input/touchscreen/atmel_tsadcc.c              |    4 ++--
 drivers/input/touchscreen/h3600_ts_input.c            |    4 ++--
 drivers/input/touchscreen/mainstone-wm97xx.c          |    2 +-
 drivers/input/touchscreen/zylonite-wm97xx.c           |    6 +++---
 drivers/leds/leds-fsg.c                               |    2 +-
 drivers/media/video/pxa_camera.c                      |    4 ++--
 drivers/mfd/dbx500-prcmu-regs.h                       |    2 +-
 drivers/misc/ep93xx_pwm.c                             |    2 +-
 drivers/misc/spear13xx_pcie_gadget.c                  |    4 ++--
 drivers/mmc/host/at91_mci.c                           |    4 ++--
 drivers/mmc/host/mxcmmc.c                             |    6 +++---
 drivers/mmc/host/omap_hsmmc.c                         |    2 +-
 drivers/mmc/host/pxamci.c                             |    6 +++---
 drivers/mtd/maps/cdb89712.c                           |    2 +-
 drivers/mtd/maps/h720x-flash.c                        |    2 +-
 drivers/mtd/maps/pxa2xx-flash.c                       |    2 +-
 drivers/mtd/maps/sa1100-flash.c                       |    2 +-
 drivers/mtd/nand/ams-delta.c                          |    2 +-
 drivers/mtd/nand/sharpsl.c                            |    2 +-
 drivers/net/can/at91_can.c                            |    2 +-
 drivers/net/ethernet/amd/am79c961a.c                  |    2 +-
 drivers/net/ethernet/cirrus/ep93xx_eth.c              |    2 +-
 drivers/net/ethernet/nxp/lpc_eth.c                    |    6 +++---
 drivers/net/ethernet/smsc/smc911x.h                   |    2 +-
 drivers/net/ethernet/smsc/smc91x.h                    |    2 +-
 drivers/net/irda/ep7211-sir.c                         |    2 +-
 drivers/net/irda/pxaficp_ir.c                         |    8 ++++----
 drivers/net/irda/sa1100_ir.c                          |    2 +-
 drivers/pcmcia/omap_cf.c                              |    2 +-
 drivers/pcmcia/pxa2xx_cm_x2xx.c                       |    2 +-
 drivers/pcmcia/sa1111_jornada720.c                    |    2 +-
 drivers/pcmcia/sa11xx_base.c                          |    2 +-
 drivers/power/avs/smartreflex.c                       |    1 +
 drivers/pwm/pwm-imx.c                                 |    2 +-
 drivers/rtc/rtc-mxc.c                                 |    2 +-
 drivers/rtc/rtc-pxa.c                                 |    2 +-
 drivers/rtc/rtc-stmp3xxx.c                            |    2 +-
 drivers/scsi/arm/acornscsi-io.S                       |    2 +-
 drivers/spi/spi-imx.c                                 |    2 +-
 drivers/spi/spi-omap-uwire.c                          |    2 +-
 drivers/spi/spi-s3c24xx-fiq.S                         |    4 ++--
 drivers/spi/spi-tegra.c                               |    2 +-
 drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c |    4 ++--
 drivers/tty/serial/21285.c                            |    2 +-
 drivers/tty/serial/atmel_serial.c                     |    6 ++++--
 drivers/tty/serial/clps711x.c                         |    2 +-
 drivers/tty/serial/msm_serial_hs.c                    |    4 ++--
 drivers/tty/serial/sa1100.c                           |    4 ++--
 drivers/tty/serial/serial_ks8695.c                    |    4 ++--
 drivers/uio/uio_pruss.c                               |    2 +-
 drivers/usb/gadget/fsl_mxc_udc.c                      |    2 +-
 drivers/usb/gadget/imx_udc.c                          |    4 ++--
 drivers/usb/gadget/pxa27x_udc.c                       |    4 ++--
 drivers/usb/host/ohci-at91.c                          |    6 +++---
 drivers/usb/host/ohci-exynos.c                        |    2 +-
 drivers/usb/musb/davinci.c                            |    4 ++--
 drivers/usb/musb/ux500_dma.c                          |    2 +-
 drivers/usb/otg/msm_otg.c                             |    2 +-
 drivers/video/backlight/omap1_bl.c                    |    2 +-
 drivers/video/ep93xx-fb.c                             |    2 +-
 drivers/video/nuc900fb.h                              |    4 ++--
 drivers/video/pnx4008/dum.h                           |    2 +-
 drivers/w1/masters/omap_hdq.c                         |    2 +-
 drivers/watchdog/imx2_wdt.c                           |    2 +-
 drivers/watchdog/ixp4xx_wdt.c                         |    2 +-
 drivers/watchdog/ks8695_wdt.c                         |    4 ++--
 drivers/watchdog/wdt285.c                             |    2 +-
 91 files changed, 137 insertions(+), 128 deletions(-)

diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index aab9605..b4c21b1 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <asm/therm.h>
diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c
index 263567f..42889bb 100644
--- a/drivers/char/hw_random/ixp4xx-rng.c
+++ b/drivers/char/hw_random/ixp4xx-rng.c
@@ -23,7 +23,7 @@
 #include <linux/hw_random.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 
 static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer)
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
index 74b830b..c771360 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -13,7 +13,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/mfd/dbx500-prcmu.h>
-#include <mach/id.h>
+#include <mach-ux500/id.h>
 
 static struct cpufreq_frequency_table freq_table[] = {
 	[0] = {
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 9382a6b..637782b 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -18,7 +18,7 @@
 #include <linux/cpufreq.h>
 #include <linux/suspend.h>
 
-#include <mach/cpufreq.h>
+#include <mach-exynos/cpufreq.h>
 
 #include <plat-samsung/cpu.h>
 
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index fb148fa..33d3d4c 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	L5
 
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8c5a7af..e7aa354 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	(L13 + 1)
 
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index e64c253..74950a3 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -17,9 +17,9 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/map.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	(L15 + 1)
 
diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 4449907..45b2331 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -35,7 +35,7 @@
 #include <plat-omap/common.h>
 #include <plat-omap/omap_device.h>
 
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 /* OPP tolerance in percentage */
 #define	OPP_TOLERANCE	4
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index a484aae..04dfc10 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -20,7 +20,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/suspend.h>
 
-#include <mach/map.h>
+#include <mach-s5pv210/map.h>
 #include <mach/regs-clock.h>
 
 static struct clk *cpu_clk;
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 737afed..98e877d 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -39,7 +39,7 @@
 
 #include <plat-omap/cpu.h>
 #include <plat-omap/dma.h>
-#include <mach/irqs.h>
+#include <mach-omap2/irqs.h>
 
 #define SHA_REG_DIGEST(x)		(0x00 + ((x) * 0x04))
 #define SHA_REG_DIN(x)			(0x1C + ((x) * 0x04))
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index ac236f6..971bd27 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -41,7 +41,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #include <crypto/scatterwalk.h>
 #include <crypto/aes.h>
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index c8af6d4..e8d7ce8 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -30,7 +30,7 @@
 extern unsigned int exynos_result_of_asv;
 #endif
 
-#include <mach/regs-clock.h>
+#include <mach-exynos/regs-clock.h>
 
 #include <plat-samsung/map-s5p.h>
 
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index c64917e..09d7112 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/dma.h>
+#include <mach-ep93xx/dma.h>
 
 #include "dmaengine.h"
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fcfeb3c..0597cbc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -28,8 +28,8 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #include "dmaengine.h"
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..45592ca 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -26,9 +26,9 @@
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <asm/irq.h>
-#include <mach/irqs.h>
+#include <plat-omap/irqs.h>
 #include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 58a6a63..c6440a5 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,7 +26,13 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
+#ifdef CONFIG_ARCH_PXA
+#include <mach-pxa/irqs.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+#include <mach-mmp/irqs.h>
+#endif
 
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index ed9f48d..4d0f7797 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -17,7 +17,7 @@
 #include <linux/i2c-algo-bit.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/ioc.h>
 
 #define FORCE_ONES	0xdc
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 79b4bcb..d163b73 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -39,8 +39,8 @@
 #include <linux/cpufreq.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/i2c.h>
 
 /* ----- global defines ----------------------------------------------- */
 
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0722f86..a8ffc39 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -53,8 +53,8 @@
 #include <linux/of_i2c.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-imx/hardware.h>
+#include <mach-imx/i2c.h>
 
 /** Defines ********************************************************************
 *******************************************************************************/
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
index a26dfb8..cfe6803 100644
--- a/drivers/i2c/busses/i2c-nuc900.c
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -28,8 +28,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 
-#include <mach/mfp.h>
-#include <mach/i2c.h>
+#include <mach-w90x900/mfp.h>
+#include <mach-w90x900/i2c.h>
 
 /* nuc900 i2c registers offset */
 
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 66eb53f..8712414 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -31,7 +31,7 @@
 
 #include <asm/unaligned.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 #define BYTES_PER_FIFO_WORD 4
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
index 50e2830..9b644e1 100644
--- a/drivers/input/misc/ixp4xx-beeper.c
+++ b/drivers/input/misc/ixp4xx-beeper.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 MODULE_AUTHOR("Alessandro Zummo <a.zummo at towertech.it>");
 MODULE_DESCRIPTION("ixp4xx beeper driver");
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 272dedd..41c1fa4 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -24,7 +24,7 @@
 #include <linux/input.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/iomd.h>
 
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index 2af5df6..5bee7e0 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/iomd.h>
 
 MODULE_AUTHOR("Vojtech Pavlik, Russell King");
diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
index 201b2d2..00f8aac 100644
--- a/drivers/input/touchscreen/atmel_tsadcc.c
+++ b/drivers/input/touchscreen/atmel_tsadcc.c
@@ -22,8 +22,8 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 /* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
 
diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
index b9e8686..39a0ce5 100644
--- a/drivers/input/touchscreen/h3600_ts_input.c
+++ b/drivers/input/touchscreen/h3600_ts_input.c
@@ -39,8 +39,8 @@
 #include <linux/delay.h>
 
 /* SA1100 serial defines */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 
 #define DRIVER_DESC	"H3600 touchscreen driver"
 
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index 7d2b213..997e627 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -33,7 +33,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <mach/regs-ac97.h>
+#include <mach-pxa/regs-ac97.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/input/touchscreen/zylonite-wm97xx.c b/drivers/input/touchscreen/zylonite-wm97xx.c
index bf0869a7..be59125 100644
--- a/drivers/input/touchscreen/zylonite-wm97xx.c
+++ b/drivers/input/touchscreen/zylonite-wm97xx.c
@@ -28,9 +28,9 @@
 #include <linux/io.h>
 #include <linux/wm97xx.h>
 
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/regs-ac97.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/mfp.h>
+#include <mach-pxa/regs-ac97.h>
 
 struct continuous {
 	u16 id;    /* codec id */
diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c
index b9053fa..683b01d 100644
--- a/drivers/leds/leds-fsg.c
+++ b/drivers/leds/leds-fsg.c
@@ -20,7 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/module.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 #include <asm/io.h>
 
 #define FSG_LED_WLAN_BIT	0
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 9c21e01..0d76655 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -36,8 +36,8 @@
 
 #include <linux/videodev2.h>
 
-#include <mach/dma.h>
-#include <mach/camera.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/camera.h>
 
 #define PXA_CAM_VERSION "0.0.6"
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6..7de55f8 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -13,7 +13,7 @@
 #ifndef __DB8500_PRCMU_REGS_H
 #define __DB8500_PRCMU_REGS_H
 
-#include <mach/hardware.h>
+#include <mach-ux500/hardware.h>
 
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
 
diff --git a/drivers/misc/ep93xx_pwm.c b/drivers/misc/ep93xx_pwm.c
index 16d7179..a996270 100644
--- a/drivers/misc/ep93xx_pwm.c
+++ b/drivers/misc/ep93xx_pwm.c
@@ -24,7 +24,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <mach/platform.h>
+#include <mach-ep93xx/platform.h>
 
 #define EP93XX_PWMx_TERM_COUNT	0x00
 #define EP93XX_PWMx_DUTY_CYCLE	0x04
diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c
index 123ed98..0a32042 100644
--- a/drivers/misc/spear13xx_pcie_gadget.c
+++ b/drivers/misc/spear13xx_pcie_gadget.c
@@ -20,8 +20,8 @@
 #include <linux/platform_device.h>
 #include <linux/pci_regs.h>
 #include <linux/configfs.h>
-#include <mach/pcie.h>
-#include <mach/misc_regs.h>
+#include <mach-spear13xx/pcie.h>
+#include <mach-spear13xx/misc_regs.h>
 
 #define IN0_MEM_SIZE	(200 * 1024 * 1024 - 1)
 /* In current implementation address translation is done using IN0 only.
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index efdb81d..ec7f665 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -75,8 +75,8 @@
 #include <asm/irq.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #include "at91_mci.h"
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 28ed52d..dec1bb1 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -38,10 +38,10 @@
 #include <asm/dma.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <mach/mmc.h>
+#include <mach-imx/mmc.h>
 
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "mxc-mmc"
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 198066c..194bc04 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -39,7 +39,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mmc.h>
 #include <plat-omap/cpu.h>
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e..8b01058 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -33,9 +33,9 @@
 
 #include <asm/sizes.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <mach/mmc.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/mmc.h>
 
 #include "pxamci.h"
 
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
index c29cbf8..c224dd4 100644
--- a/drivers/mtd/maps/cdb89712.c
+++ b/drivers/mtd/maps/cdb89712.c
@@ -9,7 +9,7 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c
index 8ed6cb4..3206fef 100644
--- a/drivers/mtd/maps/h720x-flash.c
+++ b/drivers/mtd/maps/h720x-flash.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
-#include <mach/hardware.h>
+#include <mach-h720x/hardware.h>
 #include <asm/io.h>
 
 static struct mtd_info *mymtd;
diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index 81884c2..8a82445 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -20,7 +20,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c
index a675bdb..2f234e6 100644
--- a/drivers/mtd/maps/sa1100-flash.c
+++ b/drivers/mtd/maps/sa1100-flash.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/concat.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 1386f6b..7a921a1 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -24,7 +24,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/sizes.h>
 #include <linux/gpio.h>
 #include <plat-omap/board-ams-delta.h>
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
index 3421e37..866aaac 100644
--- a/drivers/mtd/nand/sharpsl.c
+++ b/drivers/mtd/nand/sharpsl.c
@@ -25,7 +25,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 #include <asm/mach-types.h>
 
 struct sharpsl_nand {
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index fcff73a..8f14511 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -37,7 +37,7 @@
 #include <linux/can/dev.h>
 #include <linux/can/error.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 #define AT91_MB_MASK(i)		((1 << (i)) - 1)
 
diff --git a/drivers/net/ethernet/amd/am79c961a.c b/drivers/net/ethernet/amd/am79c961a.c
index e10ffad..89746bf 100644
--- a/drivers/net/ethernet/amd/am79c961a.c
+++ b/drivers/net/ethernet/amd/am79c961a.c
@@ -29,7 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-ebsa110/hardware.h>
 
 #define TX_BUFFERS 15
 #define RX_BUFFERS 25
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..7ad8b0d 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -26,7 +26,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-ep93xx/hardware.h>
 
 #define DRV_MODULE_NAME		"ep93xx-eth"
 #define DRV_MODULE_VERSION	"0.1"
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 4069eda..5be01c0 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -45,9 +45,9 @@
 #include <linux/types.h>
 
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
+#include <mach-lpc32xx/board.h>
+#include <mach-lpc32xx/platform.h>
+#include <mach-lpc32xx/hardware.h>
 
 #define MODNAME "lpc-eth"
 #define DRV_VERSION "1.00"
diff --git a/drivers/net/ethernet/smsc/smc911x.h b/drivers/net/ethernet/smsc/smc911x.h
index 3269292..80eb9d0 100644
--- a/drivers/net/ethernet/smsc/smc911x.h
+++ b/drivers/net/ethernet/smsc/smc911x.h
@@ -211,7 +211,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 
 #ifdef SMC_USE_PXA_DMA
 
-#include <mach/dma.h>
+#include <mach-pxa/dma.h>
 
 /*
  * Define the request and free functions
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
index 7f4beeb..754af90 100644
--- a/drivers/net/ethernet/smsc/smc91x.h
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -364,7 +364,7 @@ struct smc_local {
  * as RX which can overrun memory and lose packets.
  */
 #include <linux/dma-mapping.h>
-#include <mach-sa1100/dma.h>
+#include <mach-pxa/dma.h>
 
 #ifdef SMC_insl
 #undef SMC_insl
diff --git a/drivers/net/irda/ep7211-sir.c b/drivers/net/irda/ep7211-sir.c
index f83c5b8..8f8d91c 100644
--- a/drivers/net/irda/ep7211-sir.c
+++ b/drivers/net/irda/ep7211-sir.c
@@ -14,7 +14,7 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 #include "sir-dev.h"
 
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8d54767..86073eb 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -27,10 +27,10 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/dma.h>
-#include <mach/irda.h>
-#include <mach/regs-uart.h>
-#include <mach/regs-ost.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/irda.h>
+#include <mach-pxa/regs-uart.h>
+#include <mach-pxa/regs-ost.h>
 
 #define FICP		__REG(0x40800000)  /* Start of FICP area */
 #define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
index e250675..3f88a39 100644
--- a/drivers/net/irda/sa1100_ir.c
+++ b/drivers/net/irda/sa1100_ir.c
@@ -37,7 +37,7 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/mach/irda.h>
 
 static int power_level = 3;
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index adb5b1e..070eaa6 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -20,7 +20,7 @@
 
 #include <pcmcia/ss.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 
diff --git a/drivers/pcmcia/pxa2xx_cm_x2xx.c b/drivers/pcmcia/pxa2xx_cm_x2xx.c
index 6e7dcfd..61097ba 100644
--- a/drivers/pcmcia/pxa2xx_cm_x2xx.c
+++ b/drivers/pcmcia/pxa2xx_cm_x2xx.c
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 int cmx255_pcmcia_init(void);
 int cmx270_pcmcia_init(void);
diff --git a/drivers/pcmcia/sa1111_jornada720.c b/drivers/pcmcia/sa1111_jornada720.c
index 69428d1..86fc717 100644
--- a/drivers/pcmcia/sa1111_jornada720.c
+++ b/drivers/pcmcia/sa1111_jornada720.c
@@ -10,7 +10,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c
index 6eecd7c..2d689b2 100644
--- a/drivers/pcmcia/sa11xx_base.c
+++ b/drivers/pcmcia/sa11xx_base.c
@@ -39,7 +39,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/irq.h>
 
 #include "soc_common.h"
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..af502d1 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <linux/power/smartreflex.h>
+#include <plat-omap/cpu.h>
 
 #define SMARTREFLEX_NAME_LEN	16
 #define NVALUE_NAME_LEN		40
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..68ff175 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -16,7 +16,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pwm.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 
 /* i.MX1 and i.MX21 share the same PWM function block: */
diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
index e3e50d6..eb4d40e 100644
--- a/drivers/rtc/rtc-mxc.c
+++ b/drivers/rtc/rtc-mxc.c
@@ -17,7 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
 #define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8f..679ca79 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #define TIMER_FREQ		CLOCK_TICK_RATE
 #define RTC_DEF_DIVIDER		(32768 - 1)
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index 739ef556..9f7ff1d 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/of_device.h>
 
-#include <mach/common.h>
+#include <mach-mxs/common.h>
 
 #define STMP3XXX_RTC_CTRL			0x0
 #define STMP3XXX_RTC_CTRL_SET			0x4
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
index 22171b2..6395330 100644
--- a/drivers/scsi/arm/acornscsi-io.S
+++ b/drivers/scsi/arm/acornscsi-io.S
@@ -8,7 +8,7 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 
 #if defined(__APCS_32__)
 #define LOADREGS(t,r,l...)	ldm##t	r, l
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e834ff8..819ddf0 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -39,7 +39,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/spi.h>
+#include <mach-imx/spi.h>
 
 #define DRIVER_NAME "spi_imx"
 
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 177b6cf..dc2ad86 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -48,7 +48,7 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/spi/spi-s3c24xx-fiq.S b/drivers/spi/spi-s3c24xx-fiq.S
index 9718a11..44941ce 100644
--- a/drivers/spi/spi-s3c24xx-fiq.S
+++ b/drivers/spi/spi-s3c24xx-fiq.S
@@ -13,8 +13,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <mach/map.h>
-#include <mach/regs-irq.h>
+#include <mach-s3c24xx/map.h>
+#include <mach-s3c24xx/regs-irq.h>
 #include <plat-samsung/regs-spi.h>
 
 #include "spi-s3c24xx-fiq.h"
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c..77b2810 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -32,7 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/dmaengine.h>
 
-#include <mach/dma.h>
+#include <mach-tegra/dma.h>
 
 #define SLINK_COMMAND		0x000
 #define   SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
index a272e48..1e4f493 100644
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
@@ -5,8 +5,8 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
+#include <mach-ux500/gpio.h>
+#include <mach-ux500/irqs.h>
 #include "synaptics_i2c_rmi4.h"
 
 /*
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index a44345a..8104b07 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #define BAUD_BASE		(mem_fclk_21285/64)
 
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee..ff99a33 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -44,11 +44,13 @@
 #include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
-#include <mach/board.h>
 
 #ifdef CONFIG_ARM
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 #include <asm/gpio.h>
+#else
+#include <mach/board.h>
 #endif
 
 #define PDC_BUFFER_SIZE		512
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
index d0f719f..e4dc87b 100644
--- a/drivers/tty/serial/clps711x.c
+++ b/drivers/tty/serial/clps711x.c
@@ -38,7 +38,7 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 
 #define UART_NR		2
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index fca13dc..949c9e6 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -51,8 +51,8 @@
 #include <linux/atomic.h>
 #include <asm/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
+#include <mach-msm/hardware.h>
+#include <mach-msm/dma.h>
 #include <linux/platform_data/msm_serial_hs.h>
 
 /* HSUART Registers */
diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
index 2ca5959..d5c47f6 100644
--- a/drivers/tty/serial/sa1100.c
+++ b/drivers/tty/serial/sa1100.c
@@ -37,8 +37,8 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 #include <asm/mach/serial_sa1100.h>
 
 /* We've been assigned a range on the "Low-density serial ports" major */
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 7c13639..f5c672c 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -25,8 +25,8 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <mach/regs-uart.h>
-#include <mach/regs-irq.h>
+#include <mach-ks8695/regs-uart.h>
+#include <mach-ks8695/regs-irq.h>
 
 #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 #define SUPPORT_SYSRQ
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
index 33a7a27..4bafe92 100644
--- a/drivers/uio/uio_pruss.c
+++ b/drivers/uio/uio_pruss.c
@@ -25,7 +25,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
-#include <mach/sram.h>
+#include <mach-davinci/sram.h>
 
 #define DRV_NAME "pruss_uio"
 #define DRV_VERSION "1.0"
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 1b0f086..fce80b3 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -18,7 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 static struct clk *mxc_ahb_clk;
 static struct clk *mxc_per_clk;
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index dc53348..476ac2b 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -35,8 +35,8 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
-#include <mach/usb.h>
-#include <mach/hardware.h>
+#include <mach-imx/usb.h>
+#include <mach-imx/hardware.h>
 
 #include "imx_udc.h"
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 644b430..d4ef1fe 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -26,12 +26,12 @@
 #include <linux/prefetch.h>
 
 #include <asm/byteorder.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-#include <mach/udc.h>
+#include <mach-pxa/udc.h>
 
 #include "pxa27x_udc.h"
 
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a665b3e..5add6ce 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -17,11 +17,11 @@
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #ifndef CONFIG_ARCH_AT91
 #error "CONFIG_ARCH_AT91 must be defined."
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 2dce0df..561f56a 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <mach/ohci.h>
+#include <mach-exynos/ohci.h>
 #include <plat-samsung/usb-phy.h>
 
 struct exynos_ohci_hcd {
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 472c8b4..2e8cfb8 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -34,8 +34,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/cputype.h>
-#include <mach/hardware.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/hardware.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index d05c7fb..7c92d86 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -30,7 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/pfn.h>
-#include <mach/usb.h>
+#include <mach-ux500/usb.h>
 #include "musb_core.h"
 
 struct ux500_dma_channel {
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 9f5fc90..e41e6c5 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -40,7 +40,7 @@
 #include <linux/usb/msm_hsusb_hw.h>
 #include <linux/regulator/consumer.h>
 
-#include <mach/clk.h>
+#include <mach-msm/clk.h>
 
 #define MSM_USB_BASE	(motg->regs)
 #define DRIVER_NAME	"msm_otg"
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index 1e39ae3..556b623 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -28,7 +28,7 @@
 #include <linux/backlight.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mux.h>
 
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 345d962..b58f5c5 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 
-#include <mach/fb.h>
+#include <mach-ep93xx/fb.h>
 
 /* Vertical Frame Timing Registers */
 #define EP93XXFB_VLINES_TOTAL			0x0000	/* SW locked */
diff --git a/drivers/video/nuc900fb.h b/drivers/video/nuc900fb.h
index bc7c930..6f7f59a 100644
--- a/drivers/video/nuc900fb.h
+++ b/drivers/video/nuc900fb.h
@@ -15,8 +15,8 @@
 #ifndef __NUC900FB_H
 #define __NUC900FB_H
 
-#include <mach/map.h>
-#include <mach/fb.h>
+#include <mach-w90x900/map.h>
+#include <mach-w90x900/fb.h>
 
 enum nuc900_lcddrv_type {
 	LCDDRV_NUC910,
diff --git a/drivers/video/pnx4008/dum.h b/drivers/video/pnx4008/dum.h
index 1234d43..ddae1c2 100644
--- a/drivers/video/pnx4008/dum.h
+++ b/drivers/video/pnx4008/dum.h
@@ -12,7 +12,7 @@
 #ifndef __PNX008_DUM_H__
 #define __PNX008_DUM_H__
 
-#include <mach/platform.h>
+#include <mach-pnx4008/platform.h>
 
 #define PNX4008_DUMCONF_VA_BASE		IO_ADDRESS(PNX4008_DUMCONF_BASE)
 #define PNX4008_DUM_MAIN_VA_BASE	IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 4b0fcf3..2d9cc12 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -19,7 +19,7 @@
 #include <linux/pm_runtime.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 #include "../w1.h"
 #include "../w1_int.h"
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index bcfab2b..f745c9b 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -33,7 +33,7 @@
 #include <linux/uaccess.h>
 #include <linux/timer.h>
 #include <linux/jiffies.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "imx2-wdt"
 
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index 5580b4f..913d480 100644
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -25,7 +25,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 static bool nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = 60;	/* (secs) Default is 1 minute */
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9..19c1dc1 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -23,8 +23,8 @@
 #include <linux/watchdog.h>
 #include <linux/io.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
-#include <mach/regs-timer.h>
+#include <mach-ks8695/hardware.h>
+#include <mach-ks8695/regs-timer.h>
 
 #define WDT_DEFAULT_TIME	5	/* seconds */
 #define WDT_MAX_TIME		171	/* seconds */
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index 5eec740..1e1c743 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -31,7 +31,7 @@
 #include <linux/interrupt.h>
 #include <linux/uaccess.h>
 #include <linux/irq.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
-- 
1.7.10



From arnd at arndb.de  Tue Aug 21 11:12:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:12:05 -0000
Subject: [RFC 0/4] ARM: multiplatform: rename all mach headers
Message-ID: <1345561880-13231-1-git-send-email-arnd@arndb.de>

I've created this series some time ago, and updated it now to
v3.6-rc1. The idea is to get us a big step closer to the
single zImage kernel across multiple ARM platforms by
untangling the duplicate header file names.

There are two branches available in the arm-soc tree:

1. This series,
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
   This just moves header files around and changes most of the
   files including them. There are a few remaining drivers
   and platform files that keep including a generic file name
   like <mach/uncompress.h>. It remains possible to do that,
   and I've run extensive tests to ensure I did not break
   anything with this. However, each of these instances means
   that there is something that stops working when you get to
   the real multiplatform kernel and we still need to deal
   with them one by one.

2. Actually enabling CONFIG_ARCH_MULTIPLATFORM
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/multiplatform
   This builds on top of the first series, but is much more
   experimental. It shows how a multiplatform kernel can look
   like, by allowing to build vexpress, ux500, imx and omap2
   together in one kernel, but at the same time breaking some of
   their features.

I would like to get the first series merged in v3.7 if we can agree
on the general approach. So far, feedback in Linaro internal
meetings has been very positive, but Russell had concerns when
we first discussed it a few months ago.

A patch set this large means a lot of churn, and there are a few
ways we could deal with this:

a) Put the branch into linux-next now, and have everyone who
encounters conflicts pull it into their own branch to resolve
the conflicts. This can be a lot of work, and it means we
cannot rebase this branch any more.

b) Involve Linus Torvalds in the process and get him to
take the series at the end of the v3.7 merge window, after
rebasing it on top of all the other branches he merged.
This means it happens pretty much ad-hoc and there is little
testing on the patches that actually get merged.

c) Split the series and submit the first two branches at
the start of the merge window, and do the changes to all
the drivers either at the end of the v3.7 merge window
(after rebasing) or merge them through the subsystem
maintainer trees in small chunks for v3.8. This can minimize
the problems of the other two approaches, but means the process
takes longer to get to the same result.

	Arnd

Arnd Bergmann (4):
  [RFC] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
  [RFC] ARM: mass move of mach-*/plat-* header files
  [RFC] ARM: treewide: scripted conversion to mach-*/*.h
  [RFC] ARM: treewide: manually change more mach-*/*.h includes

 Documentation/spi/ep93xx_spi                       |    2 +-
 arch/arm/Makefile                                  |    1 +
 arch/arm/boot/compressed/head-shmobile.S           |    2 +-
 arch/arm/boot/compressed/sdhi-shmobile.c           |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |   10 +-
 arch/arm/mach-at91/at91rm9200_devices.c            |    8 +-
 arch/arm/mach-at91/at91rm9200_time.c               |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |   12 +-
 arch/arm/mach-at91/at91sam9260_devices.c           |   14 +-
 arch/arm/mach-at91/at91sam9261.c                   |   10 +-
 arch/arm/mach-at91/at91sam9261_devices.c           |   10 +-
 arch/arm/mach-at91/at91sam9263.c                   |    8 +-
 arch/arm/mach-at91/at91sam9263_devices.c           |   10 +-
 arch/arm/mach-at91/at91sam926x_time.c              |    2 +-
 arch/arm/mach-at91/at91sam9_alt_reset.S            |    6 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    8 +-
 arch/arm/mach-at91/at91sam9g45_devices.c           |   16 +-
 arch/arm/mach-at91/at91sam9g45_reset.S             |    6 +-
 arch/arm/mach-at91/at91sam9n12.c                   |    8 +-
 arch/arm/mach-at91/at91sam9rl.c                    |   12 +-
 arch/arm/mach-at91/at91sam9rl_devices.c            |   12 +-
 arch/arm/mach-at91/at91sam9x5.c                    |    8 +-
 arch/arm/mach-at91/at91x40.c                       |    8 +-
 arch/arm/mach-at91/at91x40_time.c                  |    4 +-
 arch/arm/mach-at91/board-1arm.c                    |    8 +-
 arch/arm/mach-at91/board-afeb-9260v1.c             |    6 +-
 arch/arm/mach-at91/board-cam60.c                   |    8 +-
 arch/arm/mach-at91/board-carmeva.c                 |    6 +-
 arch/arm/mach-at91/board-cpu9krea.c                |   12 +-
 arch/arm/mach-at91/board-cpuat91.c                 |   12 +-
 arch/arm/mach-at91/board-csb337.c                  |    6 +-
 arch/arm/mach-at91/board-csb637.c                  |    6 +-
 arch/arm/mach-at91/board-dt.c                      |    4 +-
 arch/arm/mach-at91/board-eb01.c                    |    6 +-
 arch/arm/mach-at91/board-eb9200.c                  |    6 +-
 arch/arm/mach-at91/board-ecbat91.c                 |    8 +-
 arch/arm/mach-at91/board-eco920.c                  |   10 +-
 arch/arm/mach-at91/board-flexibity.c               |    6 +-
 arch/arm/mach-at91/board-foxg20.c                  |    8 +-
 arch/arm/mach-at91/board-gsia18s.c                 |   10 +-
 arch/arm/mach-at91/board-kafa.c                    |    8 +-
 arch/arm/mach-at91/board-kb9202.c                  |   12 +-
 arch/arm/mach-at91/board-neocore926.c              |    8 +-
 arch/arm/mach-at91/board-pcontrol-g20.c            |    8 +-
 arch/arm/mach-at91/board-picotux200.c              |   10 +-
 arch/arm/mach-at91/board-qil-a9260.c               |   10 +-
 arch/arm/mach-at91/board-rm9200dk.c                |   10 +-
 arch/arm/mach-at91/board-rm9200ek.c                |   10 +-
 arch/arm/mach-at91/board-rsi-ews.c                 |    6 +-
 arch/arm/mach-at91/board-sam9-l9260.c              |    8 +-
 arch/arm/mach-at91/board-sam9260ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9261ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9263ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9g20ek.c               |   10 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c            |   12 +-
 arch/arm/mach-at91/board-sam9rlek.c                |   10 +-
 arch/arm/mach-at91/board-snapper9260.c             |    8 +-
 arch/arm/mach-at91/board-stamp9g20.c               |    6 +-
 arch/arm/mach-at91/board-usb-a926x.c               |   10 +-
 arch/arm/mach-at91/board-yl-9200.c                 |   12 +-
 arch/arm/mach-at91/clock.c                         |    6 +-
 arch/arm/mach-at91/cpuidle.c                       |    2 +-
 arch/arm/mach-at91/gpio.c                          |    4 +-
 .../include/{mach => mach-at91}/at91_adc.h         |    0
 .../include/{mach => mach-at91}/at91_aic.h         |    0
 .../include/{mach => mach-at91}/at91_dbgu.h        |    0
 .../include/{mach => mach-at91}/at91_matrix.h      |    0
 .../include/{mach => mach-at91}/at91_pio.h         |    0
 .../include/{mach => mach-at91}/at91_pit.h         |    0
 .../include/{mach => mach-at91}/at91_pmc.h         |    0
 arch/arm/mach-at91/include/mach-at91/at91_ramc.h   |   32 +
 .../include/{mach => mach-at91}/at91_rstc.h        |    0
 .../include/{mach => mach-at91}/at91_rtc.h         |    0
 .../include/{mach => mach-at91}/at91_rtt.h         |    0
 .../include/{mach => mach-at91}/at91_shdwc.h       |    0
 .../include/{mach => mach-at91}/at91_st.h          |    0
 .../include/{mach => mach-at91}/at91_tc.h          |    0
 .../include/{mach => mach-at91}/at91_twi.h         |    0
 .../include/{mach => mach-at91}/at91rm9200.h       |    0
 .../include/{mach => mach-at91}/at91rm9200_emac.h  |    0
 .../include/{mach => mach-at91}/at91rm9200_mc.h    |    0
 .../{mach => mach-at91}/at91rm9200_sdramc.h        |    0
 .../include/{mach => mach-at91}/at91sam9260.h      |    0
 .../{mach => mach-at91}/at91sam9260_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9261.h      |    0
 .../{mach => mach-at91}/at91sam9261_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9263.h      |    0
 .../{mach => mach-at91}/at91sam9263_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9_ddrsdr.h  |    0
 .../include/{mach => mach-at91}/at91sam9_sdramc.h  |    0
 .../arm/mach-at91/include/mach-at91/at91sam9_smc.h |  100 ++
 .../include/{mach => mach-at91}/at91sam9g45.h      |    0
 .../{mach => mach-at91}/at91sam9g45_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9n12.h      |    0
 .../{mach => mach-at91}/at91sam9n12_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9rl.h       |    0
 .../{mach => mach-at91}/at91sam9rl_matrix.h        |    0
 .../include/{mach => mach-at91}/at91sam9x5.h       |    0
 .../{mach => mach-at91}/at91sam9x5_matrix.h        |    0
 .../include/{mach => mach-at91}/at91x40.h          |    0
 .../include/{mach => mach-at91}/at_hdmac.h         |    0
 arch/arm/mach-at91/include/mach-at91/atmel-mci.h   |   24 +
 .../mach-at91/include/{mach => mach-at91}/board.h  |    0
 .../mach-at91/include/{mach => mach-at91}/cpu.h    |    0
 arch/arm/mach-at91/include/mach-at91/debug-macro.S |   43 +
 .../mach-at91/include/{mach => mach-at91}/gpio.h   |    0
 .../include/{mach => mach-at91}/gsia18s.h          |    0
 arch/arm/mach-at91/include/mach-at91/hardware.h    |  110 ++
 .../arm/mach-at91/include/{mach => mach-at91}/io.h |    0
 arch/arm/mach-at91/include/mach-at91/memory.h      |   26 +
 .../include/{mach => mach-at91}/stamp9g20.h        |    0
 .../include/{mach => mach-at91}/system_rev.h       |    0
 arch/arm/mach-at91/include/mach-at91/timex.h       |   37 +
 arch/arm/mach-at91/include/mach-at91/uncompress.h  |  201 +++
 arch/arm/mach-at91/include/mach/at91_ramc.h        |   32 -
 arch/arm/mach-at91/include/mach/at91sam9_smc.h     |  100 --
 arch/arm/mach-at91/include/mach/atmel-mci.h        |   24 -
 arch/arm/mach-at91/include/mach/debug-macro.S      |   43 -
 arch/arm/mach-at91/include/mach/hardware.h         |  110 --
 arch/arm/mach-at91/include/mach/memory.h           |   26 -
 arch/arm/mach-at91/include/mach/timex.h            |   37 -
 arch/arm/mach-at91/include/mach/uncompress.h       |  201 ---
 arch/arm/mach-at91/irq.c                           |    4 +-
 arch/arm/mach-at91/leds.c                          |    2 +-
 arch/arm/mach-at91/pm.c                            |   10 +-
 arch/arm/mach-at91/pm.h                            |    4 +-
 arch/arm/mach-at91/pm_slowclock.S                  |    6 +-
 arch/arm/mach-at91/sam9_smc.c                      |    2 +-
 arch/arm/mach-at91/setup.c                         |   10 +-
 arch/arm/mach-bcmring/arch.c                       |   10 +-
 arch/arm/mach-bcmring/clock.c                      |    8 +-
 arch/arm/mach-bcmring/clock.h                      |    2 +-
 arch/arm/mach-bcmring/core.c                       |   10 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |    2 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |    6 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      |    4 +-
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |    2 +-
 arch/arm/mach-bcmring/dma.c                        |    4 +-
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/intcHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/reg.h            |    2 +-
 .../include/{mach => mach-bcmring}/csp/cap.h       |    0
 .../include/mach-bcmring/csp/cap_inline.h          |  409 +++++
 .../include/mach-bcmring/csp/chipcHw_def.h         | 1123 +++++++++++++
 .../include/mach-bcmring/csp/chipcHw_inline.h      | 1673 ++++++++++++++++++++
 .../include/mach-bcmring/csp/chipcHw_reg.h         |  530 +++++++
 .../include/mach-bcmring/csp/ddrcReg.h             |  872 ++++++++++
 .../{mach => mach-bcmring}/csp/dmacHw_priv.h       |    0
 .../include/mach-bcmring/csp/dmacHw_reg.h          |  406 +++++
 .../mach-bcmring/include/mach-bcmring/csp/hw_cfg.h |   73 +
 .../include/mach-bcmring/csp/intcHw_reg.h          |  246 +++
 .../include/{mach => mach-bcmring}/csp/mm_addr.h   |    0
 .../mach-bcmring/include/mach-bcmring/csp/mm_io.h  |  147 ++
 .../include/mach-bcmring/csp/secHw_def.h           |  100 ++
 .../{mach => mach-bcmring}/csp/secHw_inline.h      |    0
 .../include/mach-bcmring/csp/tmrHw_reg.h           |   82 +
 arch/arm/mach-bcmring/include/mach-bcmring/dma.h   |  630 ++++++++
 .../include/mach-bcmring/entry-macro.S             |   76 +
 .../mach-bcmring/include/mach-bcmring/hardware.h   |   57 +
 .../include/{mach => mach-bcmring}/irqs.h          |    0
 .../{mach => mach-bcmring}/memory_settings.h       |    0
 .../mach-bcmring/include/mach-bcmring/reg_nand.h   |   66 +
 .../mach-bcmring/include/mach-bcmring/reg_umi.h    |  237 +++
 .../include/{mach => mach-bcmring}/timer.h         |    0
 .../include/{mach => mach-bcmring}/timex.h         |    0
 .../mach-bcmring/include/mach-bcmring/uncompress.h |   43 +
 .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
 .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
 .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 --------------------
 .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
 .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
 .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
 arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
 arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
 arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
 arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
 arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
 arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
 arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
 arch/arm/mach-bcmring/irq.c                        |    6 +-
 arch/arm/mach-bcmring/mm.c                         |    4 +-
 arch/arm/mach-bcmring/timer.c                      |    2 +-
 arch/arm/mach-clps711x/autcpu12.c                  |    4 +-
 arch/arm/mach-clps711x/cdb89712.c                  |    2 +-
 arch/arm/mach-clps711x/ceiva.c                     |    2 +-
 arch/arm/mach-clps711x/common.c                    |    2 +-
 arch/arm/mach-clps711x/edb7211-mm.c                |    2 +-
 arch/arm/mach-clps711x/fortunet.c                  |    2 +-
 .../include/{mach => mach-clps711x}/autcpu12.h     |    0
 .../include/{mach => mach-clps711x}/clps711x.h     |    0
 .../include/mach-clps711x/debug-macro.S            |   44 +
 .../include/mach-clps711x/entry-macro.S            |   51 +
 .../mach-clps711x/include/mach-clps711x/hardware.h |  175 ++
 .../include/{mach => mach-clps711x}/irqs.h         |    0
 .../include/{mach => mach-clps711x}/memory.h       |    0
 .../include/{mach => mach-clps711x}/syspld.h       |    0
 .../include/{mach => mach-clps711x}/timex.h        |    0
 .../include/mach-clps711x/uncompress.h             |   57 +
 arch/arm/mach-clps711x/include/mach/debug-macro.S  |   44 -
 arch/arm/mach-clps711x/include/mach/entry-macro.S  |   51 -
 arch/arm/mach-clps711x/include/mach/hardware.h     |  175 --
 arch/arm/mach-clps711x/include/mach/uncompress.h   |   57 -
 arch/arm/mach-clps711x/p720t-leds.c                |    2 +-
 arch/arm/mach-clps711x/p720t.c                     |    4 +-
 arch/arm/mach-cns3xxx/cns3420vb.c                  |    4 +-
 arch/arm/mach-cns3xxx/core.c                       |    2 +-
 arch/arm/mach-cns3xxx/devices.c                    |    6 +-
 .../include/{mach => mach-cns3xxx}/cns3xxx.h       |    0
 .../include/{mach => mach-cns3xxx}/debug-macro.S   |    0
 arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h  |   24 +
 .../include/{mach => mach-cns3xxx}/pm.h            |    0
 .../include/{mach => mach-cns3xxx}/timex.h         |    0
 .../mach-cns3xxx/include/mach-cns3xxx/uncompress.h |   54 +
 arch/arm/mach-cns3xxx/include/mach/irqs.h          |   24 -
 arch/arm/mach-cns3xxx/include/mach/uncompress.h    |   54 -
 arch/arm/mach-cns3xxx/pcie.c                       |    2 +-
 arch/arm/mach-cns3xxx/pm.c                         |    4 +-
 arch/arm/mach-davinci/aemif.c                      |    2 +-
 arch/arm/mach-davinci/board-da830-evm.c            |   14 +-
 arch/arm/mach-davinci/board-da850-evm.c            |   12 +-
 arch/arm/mach-davinci/board-dm355-evm.c            |   10 +-
 arch/arm/mach-davinci/board-dm355-leopard.c        |   10 +-
 arch/arm/mach-davinci/board-dm365-evm.c            |   14 +-
 arch/arm/mach-davinci/board-dm644x-evm.c           |   16 +-
 arch/arm/mach-davinci/board-dm646x-evm.c           |   14 +-
 arch/arm/mach-davinci/board-mityomapl138.c         |   12 +-
 arch/arm/mach-davinci/board-neuros-osd2.c          |   14 +-
 arch/arm/mach-davinci/board-omapl138-hawk.c        |    6 +-
 arch/arm/mach-davinci/board-sffsdr.c               |   10 +-
 arch/arm/mach-davinci/board-tnetv107x-evm.c        |   10 +-
 arch/arm/mach-davinci/cdce949.c                    |    4 +-
 arch/arm/mach-davinci/clock.c                      |    8 +-
 arch/arm/mach-davinci/common.c                     |    4 +-
 arch/arm/mach-davinci/cp_intc.c                    |    4 +-
 arch/arm/mach-davinci/cpufreq.c                    |    6 +-
 arch/arm/mach-davinci/cpuidle.c                    |    4 +-
 arch/arm/mach-davinci/da830.c                      |   14 +-
 arch/arm/mach-davinci/da850.c                      |   18 +-
 arch/arm/mach-davinci/davinci.h                    |    6 +-
 arch/arm/mach-davinci/devices-da8xx.c              |   10 +-
 arch/arm/mach-davinci/devices-tnetv107x.c          |    8 +-
 arch/arm/mach-davinci/devices.c                    |   16 +-
 arch/arm/mach-davinci/dm355.c                      |   22 +-
 arch/arm/mach-davinci/dm365.c                      |   24 +-
 arch/arm/mach-davinci/dm644x.c                     |   20 +-
 arch/arm/mach-davinci/dm646x.c                     |   20 +-
 arch/arm/mach-davinci/dma.c                        |    2 +-
 .../include/{mach => mach-davinci}/aemif.h         |    0
 arch/arm/mach-davinci/include/mach-davinci/asp.h   |  137 ++
 .../mach-davinci/include/mach-davinci/cdce949.h    |   19 +
 .../include/{mach => mach-davinci}/clock.h         |    0
 .../include/{mach => mach-davinci}/common.h        |    0
 .../include/{mach => mach-davinci}/cp_intc.h       |    0
 .../include/{mach => mach-davinci}/cpufreq.h       |    0
 .../include/{mach => mach-davinci}/cpuidle.h       |    0
 .../mach-davinci/include/mach-davinci/cputype.h    |   94 ++
 arch/arm/mach-davinci/include/mach-davinci/da8xx.h |  134 ++
 .../include/{mach => mach-davinci}/ddr2.h          |    0
 .../include/mach-davinci/debug-macro.S             |   67 +
 .../include/{mach => mach-davinci}/edma.h          |    0
 .../include/mach-davinci/entry-macro.S             |   39 +
 .../include/mach-davinci/gpio-davinci.h            |   91 ++
 .../include/{mach => mach-davinci}/gpio.h          |    0
 .../include/{mach => mach-davinci}/hardware.h      |    0
 .../include/{mach => mach-davinci}/i2c.h           |    0
 .../include/{mach => mach-davinci}/irqs.h          |    0
 .../include/{mach => mach-davinci}/keyscan.h       |    0
 .../include/{mach => mach-davinci}/mmc.h           |    0
 .../include/{mach => mach-davinci}/mux.h           |    0
 .../include/{mach => mach-davinci}/nand.h          |    0
 .../include/{mach => mach-davinci}/pm.h            |    0
 .../include/{mach => mach-davinci}/psc.h           |    0
 .../arm/mach-davinci/include/mach-davinci/serial.h |   48 +
 arch/arm/mach-davinci/include/mach-davinci/spi.h   |   89 ++
 .../include/{mach => mach-davinci}/sram.h          |    0
 .../include/{mach => mach-davinci}/time.h          |    0
 .../include/{mach => mach-davinci}/timex.h         |    0
 .../mach-davinci/include/mach-davinci/tnetv107x.h  |   61 +
 .../mach-davinci/include/mach-davinci/uncompress.h |   98 ++
 .../include/{mach => mach-davinci}/usb.h           |    0
 arch/arm/mach-davinci/include/mach/asp.h           |  137 --
 arch/arm/mach-davinci/include/mach/cdce949.h       |   19 -
 arch/arm/mach-davinci/include/mach/cputype.h       |   94 --
 arch/arm/mach-davinci/include/mach/da8xx.h         |  134 --
 arch/arm/mach-davinci/include/mach/debug-macro.S   |   67 -
 arch/arm/mach-davinci/include/mach/entry-macro.S   |   39 -
 arch/arm/mach-davinci/include/mach/gpio-davinci.h  |   91 --
 arch/arm/mach-davinci/include/mach/serial.h        |   48 -
 arch/arm/mach-davinci/include/mach/spi.h           |   89 --
 arch/arm/mach-davinci/include/mach/tnetv107x.h     |   61 -
 arch/arm/mach-davinci/include/mach/uncompress.h    |   98 --
 arch/arm/mach-davinci/irq.c                        |    6 +-
 arch/arm/mach-davinci/mux.c                        |    4 +-
 arch/arm/mach-davinci/mux.h                        |    2 +-
 arch/arm/mach-davinci/pm.c                         |    6 +-
 arch/arm/mach-davinci/psc.c                        |    4 +-
 arch/arm/mach-davinci/serial.c                     |    4 +-
 arch/arm/mach-davinci/sleep.S                      |    4 +-
 arch/arm/mach-davinci/sram.c                       |    4 +-
 arch/arm/mach-davinci/time.c                       |    6 +-
 arch/arm/mach-davinci/tnetv107x.c                  |   18 +-
 arch/arm/mach-davinci/usb.c                        |    8 +-
 arch/arm/mach-dove/addr-map.c                      |    4 +-
 arch/arm/mach-dove/cm-a510.c                       |    2 +-
 arch/arm/mach-dove/common.c                        |   12 +-
 arch/arm/mach-dove/dove-db-setup.c                 |    2 +-
 arch/arm/mach-dove/include/mach-dove/bridge-regs.h |   55 +
 arch/arm/mach-dove/include/mach-dove/debug-macro.S |   19 +
 .../mach-dove/include/{mach => mach-dove}/dove.h   |    0
 arch/arm/mach-dove/include/mach-dove/entry-macro.S |   33 +
 arch/arm/mach-dove/include/mach-dove/gpio.h        |    9 +
 .../include/{mach => mach-dove}/hardware.h         |    0
 .../arm/mach-dove/include/{mach => mach-dove}/io.h |    0
 .../mach-dove/include/{mach => mach-dove}/irqs.h   |    0
 arch/arm/mach-dove/include/mach-dove/pm.h          |   54 +
 .../mach-dove/include/{mach => mach-dove}/timex.h  |    0
 arch/arm/mach-dove/include/mach-dove/uncompress.h  |   37 +
 arch/arm/mach-dove/include/mach/bridge-regs.h      |   55 -
 arch/arm/mach-dove/include/mach/debug-macro.S      |   19 -
 arch/arm/mach-dove/include/mach/entry-macro.S      |   33 -
 arch/arm/mach-dove/include/mach/gpio.h             |    9 -
 arch/arm/mach-dove/include/mach/pm.h               |   54 -
 arch/arm/mach-dove/include/mach/uncompress.h       |   37 -
 arch/arm/mach-dove/irq.c                           |    6 +-
 arch/arm/mach-dove/mpp.c                           |    4 +-
 arch/arm/mach-dove/pcie.c                          |    8 +-
 arch/arm/mach-ebsa110/core.c                       |    2 +-
 .../include/{mach => mach-ebsa110}/debug-macro.S   |    0
 .../include/{mach => mach-ebsa110}/entry-macro.S   |    0
 .../include/{mach => mach-ebsa110}/hardware.h      |    0
 .../include/{mach => mach-ebsa110}/io.h            |    0
 .../include/{mach => mach-ebsa110}/irqs.h          |    0
 .../include/{mach => mach-ebsa110}/memory.h        |    0
 .../include/{mach => mach-ebsa110}/timex.h         |    0
 .../include/{mach => mach-ebsa110}/uncompress.h    |    0
 arch/arm/mach-ebsa110/io.c                         |    2 +-
 arch/arm/mach-ebsa110/leds.c                       |    2 +-
 arch/arm/mach-ep93xx/adssphere.c                   |    2 +-
 arch/arm/mach-ep93xx/clock.c                       |    2 +-
 arch/arm/mach-ep93xx/core.c                        |   10 +-
 arch/arm/mach-ep93xx/crunch-bits.S                 |    2 +-
 arch/arm/mach-ep93xx/dma.c                         |    4 +-
 arch/arm/mach-ep93xx/edb93xx.c                     |    8 +-
 arch/arm/mach-ep93xx/gesbc9312.c                   |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/debug-macro.S  |   21 +
 .../include/{mach => mach-ep93xx}/dma.h            |    0
 .../include/{mach => mach-ep93xx}/ep93xx-regs.h    |    0
 .../include/{mach => mach-ep93xx}/ep93xx_keypad.h  |    0
 .../include/{mach => mach-ep93xx}/ep93xx_spi.h     |    0
 .../mach-ep93xx/include/{mach => mach-ep93xx}/fb.h |    0
 .../mach-ep93xx/include/mach-ep93xx/gpio-ep93xx.h  |  110 ++
 .../include/{mach => mach-ep93xx}/gpio.h           |    0
 .../arm/mach-ep93xx/include/mach-ep93xx/hardware.h |   24 +
 .../include/{mach => mach-ep93xx}/irqs.h           |    0
 .../include/{mach => mach-ep93xx}/memory.h         |    0
 .../include/{mach => mach-ep93xx}/platform.h       |    0
 .../include/{mach => mach-ep93xx}/timex.h          |    0
 .../include/{mach => mach-ep93xx}/ts72xx.h         |    0
 .../mach-ep93xx/include/mach-ep93xx/uncompress.h   |   94 ++
 arch/arm/mach-ep93xx/include/mach/debug-macro.S    |   21 -
 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h    |  110 --
 arch/arm/mach-ep93xx/include/mach/hardware.h       |   24 -
 arch/arm/mach-ep93xx/include/mach/uncompress.h     |   94 --
 arch/arm/mach-ep93xx/micro9.c                      |    2 +-
 arch/arm/mach-ep93xx/simone.c                      |    6 +-
 arch/arm/mach-ep93xx/snappercl15.c                 |    6 +-
 arch/arm/mach-ep93xx/soc.h                         |    2 +-
 arch/arm/mach-ep93xx/ts72xx.c                      |    4 +-
 arch/arm/mach-ep93xx/vision_ep9307.c               |    8 +-
 arch/arm/mach-exynos/clock-exynos4.c               |   22 +-
 arch/arm/mach-exynos/clock-exynos4210.c            |   24 +-
 arch/arm/mach-exynos/clock-exynos4212.c            |   24 +-
 arch/arm/mach-exynos/clock-exynos5.c               |   22 +-
 arch/arm/mach-exynos/common.c                      |   34 +-
 arch/arm/mach-exynos/cpuidle.c                     |    6 +-
 arch/arm/mach-exynos/dev-ahci.c                    |    8 +-
 arch/arm/mach-exynos/dev-audio.c                   |   12 +-
 arch/arm/mach-exynos/dev-drm.c                     |    2 +-
 arch/arm/mach-exynos/dev-dwmci.c                   |    4 +-
 arch/arm/mach-exynos/dev-ohci.c                    |   10 +-
 arch/arm/mach-exynos/dev-sysmmu.c                  |    8 +-
 arch/arm/mach-exynos/dev-uart.c                    |    6 +-
 arch/arm/mach-exynos/dma.c                         |   12 +-
 arch/arm/mach-exynos/hotplug.c                     |    2 +-
 .../include/{mach => mach-exynos}/cpufreq.h        |    0
 .../mach-exynos/include/mach-exynos/debug-macro.S  |   39 +
 arch/arm/mach-exynos/include/mach-exynos/dma.h     |   26 +
 .../include/{mach => mach-exynos}/dwmci.h          |    0
 .../include/{mach => mach-exynos}/gpio.h           |    0
 .../include/{mach => mach-exynos}/hardware.h       |    0
 arch/arm/mach-exynos/include/mach-exynos/irqs.h    |  469 ++++++
 arch/arm/mach-exynos/include/mach-exynos/map.h     |  278 ++++
 .../include/{mach => mach-exynos}/memory.h         |    0
 .../include/{mach => mach-exynos}/ohci.h           |    0
 arch/arm/mach-exynos/include/mach-exynos/pm-core.h |   65 +
 .../include/{mach => mach-exynos}/pmu.h            |    0
 .../include/{mach => mach-exynos}/regs-audss.h     |    0
 .../mach-exynos/include/mach-exynos/regs-clock.h   |  353 +++++
 .../mach-exynos/include/mach-exynos/regs-gpio.h    |   40 +
 .../arm/mach-exynos/include/mach-exynos/regs-irq.h |   19 +
 .../arm/mach-exynos/include/mach-exynos/regs-mct.h |   53 +
 .../arm/mach-exynos/include/mach-exynos/regs-mem.h |   23 +
 .../arm/mach-exynos/include/mach-exynos/regs-pmu.h |  370 +++++
 .../include/{mach => mach-exynos}/regs-usb-phy.h   |    0
 .../include/{mach => mach-exynos}/sysmmu.h         |    0
 .../include/{mach => mach-exynos}/timex.h          |    0
 .../mach-exynos/include/mach-exynos/uncompress.h   |   52 +
 arch/arm/mach-exynos/include/mach/debug-macro.S    |   39 -
 arch/arm/mach-exynos/include/mach/dma.h            |   26 -
 arch/arm/mach-exynos/include/mach/irqs.h           |  469 ------
 arch/arm/mach-exynos/include/mach/map.h            |  278 ----
 arch/arm/mach-exynos/include/mach/pm-core.h        |   65 -
 arch/arm/mach-exynos/include/mach/regs-clock.h     |  353 -----
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |   40 -
 arch/arm/mach-exynos/include/mach/regs-irq.h       |   19 -
 arch/arm/mach-exynos/include/mach/regs-mct.h       |   53 -
 arch/arm/mach-exynos/include/mach/regs-mem.h       |   23 -
 arch/arm/mach-exynos/include/mach/regs-pmu.h       |  370 -----
 arch/arm/mach-exynos/include/mach/uncompress.h     |   52 -
 arch/arm/mach-exynos/mach-armlex4210.c             |   16 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    6 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 +-
 arch/arm/mach-exynos/mach-nuri.c                   |   34 +-
 arch/arm/mach-exynos/mach-origen.c                 |   30 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |   28 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |   34 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |   32 +-
 arch/arm/mach-exynos/mct.c                         |    8 +-
 arch/arm/mach-exynos/platsmp.c                     |    8 +-
 arch/arm/mach-exynos/pm.c                          |   22 +-
 arch/arm/mach-exynos/pm_domains.c                  |    4 +-
 arch/arm/mach-exynos/pmu.c                         |    4 +-
 arch/arm/mach-exynos/setup-fimc.c                  |    4 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    6 +-
 arch/arm/mach-exynos/setup-i2c0.c                  |    6 +-
 arch/arm/mach-exynos/setup-i2c1.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c2.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c3.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c4.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c5.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c6.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c7.c                  |    4 +-
 arch/arm/mach-exynos/setup-keypad.c                |    2 +-
 arch/arm/mach-exynos/setup-sdhci-gpio.c            |    6 +-
 arch/arm/mach-exynos/setup-spi.c                   |    2 +-
 arch/arm/mach-exynos/setup-usb-phy.c               |    8 +-
 arch/arm/mach-footbridge/ebsa285-leds.c            |    2 +-
 .../include/mach-footbridge/debug-macro.S          |   56 +
 .../include/mach-footbridge/entry-macro.S          |  107 ++
 .../include/{mach => mach-footbridge}/hardware.h   |    0
 .../include/{mach => mach-footbridge}/io.h         |    0
 .../include/{mach => mach-footbridge}/irqs.h       |    0
 .../include/{mach => mach-footbridge}/isa-dma.h    |    0
 .../include/{mach => mach-footbridge}/memory.h     |    0
 .../include/{mach => mach-footbridge}/timex.h      |    0
 .../include/{mach => mach-footbridge}/uncompress.h |    0
 .../arm/mach-footbridge/include/mach/debug-macro.S |   56 -
 .../arm/mach-footbridge/include/mach/entry-macro.S |  107 --
 arch/arm/mach-footbridge/isa-irq.c                 |    2 +-
 arch/arm/mach-footbridge/netwinder-leds.c          |    2 +-
 arch/arm/mach-gemini/board-nas4220b.c              |    4 +-
 arch/arm/mach-gemini/devices.c                     |    6 +-
 arch/arm/mach-gemini/gpio.c                        |    4 +-
 .../mach-gemini/include/mach-gemini/debug-macro.S  |   21 +
 .../mach-gemini/include/mach-gemini/entry-macro.S  |   33 +
 .../include/{mach => mach-gemini}/global_reg.h     |    0
 arch/arm/mach-gemini/include/mach-gemini/gpio.h    |   20 +
 .../include/{mach => mach-gemini}/hardware.h       |    0
 .../include/{mach => mach-gemini}/irqs.h           |    0
 arch/arm/mach-gemini/include/mach-gemini/system.h  |   23 +
 .../include/{mach => mach-gemini}/timex.h          |    0
 .../mach-gemini/include/mach-gemini/uncompress.h   |   44 +
 arch/arm/mach-gemini/include/mach/debug-macro.S    |   21 -
 arch/arm/mach-gemini/include/mach/entry-macro.S    |   33 -
 arch/arm/mach-gemini/include/mach/gpio.h           |   20 -
 arch/arm/mach-gemini/include/mach/system.h         |   23 -
 arch/arm/mach-gemini/include/mach/uncompress.h     |   44 -
 arch/arm/mach-gemini/irq.c                         |    2 +-
 arch/arm/mach-gemini/mm.c                          |    2 +-
 arch/arm/mach-gemini/time.c                        |    4 +-
 arch/arm/mach-h720x/common.c                       |    4 +-
 arch/arm/mach-h720x/cpu-h7201.c                    |    4 +-
 arch/arm/mach-h720x/cpu-h7202.c                    |    4 +-
 arch/arm/mach-h720x/h7201-eval.c                   |    2 +-
 arch/arm/mach-h720x/h7202-eval.c                   |    4 +-
 .../include/{mach => mach-h720x}/boards.h          |    0
 .../mach-h720x/include/mach-h720x/debug-macro.S    |   40 +
 .../include/{mach => mach-h720x}/entry-macro.S     |    0
 .../include/{mach => mach-h720x}/h7201-regs.h      |    0
 .../include/{mach => mach-h720x}/h7202-regs.h      |    0
 .../include/{mach => mach-h720x}/hardware.h        |    0
 .../mach-h720x/include/{mach => mach-h720x}/irqs.h |    0
 .../include/{mach => mach-h720x}/isa-dma.h         |    0
 .../include/{mach => mach-h720x}/timex.h           |    0
 .../arm/mach-h720x/include/mach-h720x/uncompress.h |   37 +
 arch/arm/mach-h720x/include/mach/debug-macro.S     |   40 -
 arch/arm/mach-h720x/include/mach/uncompress.h      |   37 -
 .../include/{mach => mach-highbank}/debug-macro.S  |    0
 .../include/{mach => mach-highbank}/gpio.h         |    0
 .../include/{mach => mach-highbank}/timex.h        |    0
 .../include/{mach => mach-highbank}/uncompress.h   |    0
 arch/arm/mach-imx/clk-imx1.c                       |    4 +-
 arch/arm/mach-imx/clk-imx21.c                      |    4 +-
 arch/arm/mach-imx/clk-imx25.c                      |    6 +-
 arch/arm/mach-imx/clk-imx27.c                      |    4 +-
 arch/arm/mach-imx/clk-imx31.c                      |    6 +-
 arch/arm/mach-imx/clk-imx35.c                      |    4 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |    4 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    2 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    6 +-
 arch/arm/mach-imx/clk.h                            |    2 +-
 arch/arm/mach-imx/cpu-imx25.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    6 +-
 arch/arm/mach-imx/cpu-imx35.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    2 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    2 +-
 arch/arm/mach-imx/devices-imx1.h                   |    4 +-
 arch/arm/mach-imx/devices-imx21.h                  |    4 +-
 arch/arm/mach-imx/devices-imx25.h                  |    4 +-
 arch/arm/mach-imx/devices-imx27.h                  |    4 +-
 arch/arm/mach-imx/devices-imx31.h                  |    4 +-
 arch/arm/mach-imx/devices-imx35.h                  |    4 +-
 arch/arm/mach-imx/devices-imx50.h                  |    4 +-
 arch/arm/mach-imx/devices-imx51.h                  |    4 +-
 arch/arm/mach-imx/devices-imx53.h                  |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    6 +-
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    6 +-
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    6 +-
 arch/arm/mach-imx/hotplug.c                        |    2 +-
 arch/arm/mach-imx/imx27-dt.c                       |    4 +-
 arch/arm/mach-imx/imx31-dt.c                       |    4 +-
 arch/arm/mach-imx/imx51-dt.c                       |    4 +-
 arch/arm/mach-imx/imx53-dt.c                       |    4 +-
 .../include/mach-imx}/3ds_debugboard.h             |    0
 .../include/mach-imx}/board-mx31lilly.h            |    0
 .../include/mach-imx}/board-mx31lite.h             |    0
 .../include/mach-imx}/board-mx31moboard.h          |    0
 .../include/mach-imx}/board-pcm038.h               |    0
 .../mach => mach-imx/include/mach-imx}/clock.h     |    0
 .../mach => mach-imx/include/mach-imx}/common.h    |    0
 .../mach => mach-imx/include/mach-imx}/cpuidle.h   |    0
 arch/arm/mach-imx/include/mach-imx/debug-macro.S   |   51 +
 .../arm/mach-imx/include/mach-imx/devices-common.h |  333 ++++
 arch/arm/mach-imx/include/mach-imx/dma-mx1-mx2.h   |   10 +
 .../mach => mach-imx/include/mach-imx}/dma.h       |    0
 .../mach => mach-imx/include/mach-imx}/esdhc.h     |    0
 .../include/mach-imx}/eukrea-baseboards.h          |    0
 .../mach => mach-imx/include/mach-imx}/gpio.h      |    0
 arch/arm/mach-imx/include/mach-imx/hardware.h      |  134 ++
 .../mach => mach-imx/include/mach-imx}/i2c.h       |    0
 .../mach => mach-imx/include/mach-imx}/iim.h       |    0
 .../mach => mach-imx/include/mach-imx}/imx-uart.h  |    0
 .../mach => mach-imx/include/mach-imx}/imxfb.h     |    0
 arch/arm/mach-imx/include/mach-imx/iomux-mx1.h     |  155 ++
 arch/arm/mach-imx/include/mach-imx/iomux-mx21.h    |  122 ++
 arch/arm/mach-imx/include/mach-imx/iomux-mx25.h    |  524 ++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx27.h    |  205 +++
 .../include/mach-imx}/iomux-mx2x.h                 |    0
 .../mach => mach-imx/include/mach-imx}/iomux-mx3.h |    0
 arch/arm/mach-imx/include/mach-imx/iomux-mx35.h    | 1267 +++++++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx50.h    |  977 ++++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx51.h    |  827 ++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx53.h    | 1219 ++++++++++++++
 .../mach => mach-imx/include/mach-imx}/iomux-v1.h  |    0
 .../mach => mach-imx/include/mach-imx}/iomux-v3.h  |    0
 .../mach => mach-imx/include/mach-imx}/ipu.h       |    0
 .../mach => mach-imx/include/mach-imx}/iram.h      |    0
 .../mach => mach-imx/include/mach-imx}/irqs.h      |    0
 .../mach => mach-imx/include/mach-imx}/mmc.h       |    0
 .../mach => mach-imx/include/mach-imx}/mx1.h       |    0
 .../include/mach-imx}/mx1_camera.h                 |    0
 .../include/mach-imx}/mx21-usbhost.h               |    0
 .../mach => mach-imx/include/mach-imx}/mx21.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx25.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx27.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx2_cam.h   |    0
 .../mach => mach-imx/include/mach-imx}/mx2x.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx31.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx35.h      |    0
 .../include/mach-imx}/mx3_camera.h                 |    0
 .../mach => mach-imx/include/mach-imx}/mx3fb.h     |    0
 .../mach => mach-imx/include/mach-imx}/mx3x.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx50.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx51.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx53.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx6q.h      |    0
 .../mach => mach-imx/include/mach-imx}/mxc.h       |    0
 .../mach => mach-imx/include/mach-imx}/mxc_ehci.h  |    0
 .../mach => mach-imx/include/mach-imx}/mxc_nand.h  |    0
 .../mach => mach-imx/include/mach-imx}/sdma.h      |    0
 .../mach => mach-imx/include/mach-imx}/spi.h       |    0
 .../mach => mach-imx/include/mach-imx}/ssi.h       |    0
 .../mach => mach-imx/include/mach-imx}/timex.h     |    0
 .../mach => mach-imx/include/mach-imx}/ulpi.h      |    0
 .../include/mach-imx}/uncompress.h                 |    0
 .../mach => mach-imx/include/mach-imx}/usb.h       |    0
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h       |   10 -
 arch/arm/mach-imx/iomux-imx31.c                    |    4 +-
 arch/arm/mach-imx/lluart.c                         |    2 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    6 +-
 arch/arm/mach-imx/mach-armadillo5x0.c              |    8 +-
 arch/arm/mach-imx/mach-bug.c                       |    6 +-
 arch/arm/mach-imx/mach-cpuimx27.c                  |   10 +-
 arch/arm/mach-imx/mach-cpuimx35.c                  |    8 +-
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    8 +-
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    6 +-
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +-
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +-
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +-
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    8 +-
 arch/arm/mach-imx/mach-mx1ads.c                    |    6 +-
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx31ads.c                   |    4 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   10 +-
 arch/arm/mach-imx/mach-mx31lite.c                  |   10 +-
 arch/arm/mach-imx/mach-mx31moboard.c               |   12 +-
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    6 +-
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx51_babbage.c              |    6 +-
 arch/arm/mach-imx/mach-mx51_efikamx.c              |    6 +-
 arch/arm/mach-imx/mach-mx51_efikasb.c              |    8 +-
 arch/arm/mach-imx/mach-mx53_ard.c                  |    6 +-
 arch/arm/mach-imx/mach-mx53_evk.c                  |    6 +-
 arch/arm/mach-imx/mach-mx53_loco.c                 |    6 +-
 arch/arm/mach-imx/mach-mx53_smd.c                  |    6 +-
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +-
 arch/arm/mach-imx/mach-pca100.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037_eet.c                |    4 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   10 +-
 arch/arm/mach-imx/mach-pcm043.c                    |    8 +-
 arch/arm/mach-imx/mach-qong.c                      |    6 +-
 arch/arm/mach-imx/mach-scb9328.c                   |    6 +-
 arch/arm/mach-imx/mach-vpr200.c                    |    6 +-
 arch/arm/mach-imx/mm-imx1.c                        |    6 +-
 arch/arm/mach-imx/mm-imx21.c                       |    8 +-
 arch/arm/mach-imx/mm-imx25.c                       |   10 +-
 arch/arm/mach-imx/mm-imx27.c                       |    8 +-
 arch/arm/mach-imx/mm-imx3.c                        |    8 +-
 arch/arm/mach-imx/mm-imx5.c                        |    8 +-
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |    2 +-
 arch/arm/mach-imx/mx31lilly-db.c                   |    8 +-
 arch/arm/mach-imx/mx31lite-db.c                    |    8 +-
 arch/arm/mach-imx/mx31moboard-devboard.c           |    8 +-
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    8 +-
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   10 +-
 arch/arm/mach-imx/mx51_efika.c                     |    8 +-
 arch/arm/mach-imx/pcm970-baseboard.c               |    6 +-
 arch/arm/mach-imx/platsmp.c                        |    4 +-
 arch/arm/mach-imx/pm-imx27.c                       |    2 +-
 arch/arm/mach-imx/pm-imx3.c                        |    6 +-
 arch/arm/mach-imx/pm-imx5.c                        |    6 +-
 arch/arm/mach-imx/pm-imx6q.c                       |    4 +-
 arch/arm/mach-integrator/core.c                    |    8 +-
 arch/arm/mach-integrator/cpu.c                     |    4 +-
 arch/arm/mach-integrator/impd1.c                   |    4 +-
 .../include/{mach => mach-integrator}/cm.h         |    0
 .../{mach => mach-integrator}/debug-macro.S        |    0
 .../include/{mach => mach-integrator}/hardware.h   |    0
 .../include/{mach => mach-integrator}/impd1.h      |    0
 .../include/{mach => mach-integrator}/io.h         |    0
 .../include/{mach => mach-integrator}/irqs.h       |    0
 .../include/{mach => mach-integrator}/lm.h         |    0
 .../include/{mach => mach-integrator}/memory.h     |    0
 .../include/{mach => mach-integrator}/platform.h   |    0
 .../include/{mach => mach-integrator}/timex.h      |    0
 .../include/{mach => mach-integrator}/uncompress.h |    0
 arch/arm/mach-integrator/integrator_ap.c           |   10 +-
 arch/arm/mach-integrator/integrator_cp.c           |   16 +-
 arch/arm/mach-integrator/leds.c                    |    6 +-
 arch/arm/mach-integrator/lm.c                      |    2 +-
 arch/arm/mach-integrator/pci.c                     |    2 +-
 arch/arm/mach-integrator/pci_v3.c                  |    6 +-
 arch/arm/mach-iop13xx/include/mach-iop13xx/adma.h  |  647 ++++++++
 .../include/{mach => mach-iop13xx}/debug-macro.S   |    0
 .../include/{mach => mach-iop13xx}/entry-macro.S   |    0
 .../include/{mach => mach-iop13xx}/hardware.h      |    0
 .../include/{mach => mach-iop13xx}/io.h            |    0
 .../include/{mach => mach-iop13xx}/iop13xx.h       |    0
 .../include/{mach => mach-iop13xx}/iq81340.h       |    0
 .../include/{mach => mach-iop13xx}/irqs.h          |    0
 .../arm/mach-iop13xx/include/mach-iop13xx/memory.h |   72 +
 .../include/{mach => mach-iop13xx}/msi.h           |    0
 arch/arm/mach-iop13xx/include/mach-iop13xx/pci.h   |   57 +
 .../include/{mach => mach-iop13xx}/time.h          |    0
 .../include/{mach => mach-iop13xx}/timex.h         |    0
 .../mach-iop13xx/include/mach-iop13xx/uncompress.h |   23 +
 arch/arm/mach-iop13xx/include/mach/adma.h          |  647 --------
 arch/arm/mach-iop13xx/include/mach/memory.h        |   72 -
 arch/arm/mach-iop13xx/include/mach/pci.h           |   57 -
 arch/arm/mach-iop13xx/include/mach/uncompress.h    |   23 -
 arch/arm/mach-iop13xx/io.c                         |    2 +-
 arch/arm/mach-iop13xx/iq81340mc.c                  |    6 +-
 arch/arm/mach-iop13xx/iq81340sc.c                  |    6 +-
 arch/arm/mach-iop13xx/irq.c                        |    6 +-
 arch/arm/mach-iop13xx/pci.c                        |    4 +-
 arch/arm/mach-iop13xx/setup.c                      |    2 +-
 arch/arm/mach-iop32x/em7210.c                      |    4 +-
 arch/arm/mach-iop32x/glantank.c                    |    4 +-
 .../include/{mach => mach-iop32x}/adma.h           |    0
 .../include/{mach => mach-iop32x}/debug-macro.S    |    0
 .../mach-iop32x/include/mach-iop32x/entry-macro.S  |   33 +
 .../include/{mach => mach-iop32x}/glantank.h       |    0
 .../include/{mach => mach-iop32x}/gpio.h           |    0
 .../include/{mach => mach-iop32x}/hardware.h       |    0
 .../mach-iop32x/include/{mach => mach-iop32x}/io.h |    0
 .../include/{mach => mach-iop32x}/iop32x.h         |    0
 .../include/{mach => mach-iop32x}/iq31244.h        |    0
 .../include/{mach => mach-iop32x}/iq80321.h        |    0
 .../include/{mach => mach-iop32x}/irqs.h           |    0
 .../include/{mach => mach-iop32x}/n2100.h          |    0
 .../include/{mach => mach-iop32x}/time.h           |    0
 .../include/{mach => mach-iop32x}/timex.h          |    0
 .../mach-iop32x/include/mach-iop32x/uncompress.h   |   39 +
 arch/arm/mach-iop32x/include/mach/entry-macro.S    |   33 -
 arch/arm/mach-iop32x/include/mach/uncompress.h     |   39 -
 arch/arm/mach-iop32x/iq31244.c                     |    4 +-
 arch/arm/mach-iop32x/iq80321.c                     |    4 +-
 arch/arm/mach-iop32x/irq.c                         |    2 +-
 arch/arm/mach-iop32x/n2100.c                       |    4 +-
 .../include/{mach => mach-iop33x}/adma.h           |    0
 .../include/{mach => mach-iop33x}/debug-macro.S    |    0
 .../mach-iop33x/include/mach-iop33x/entry-macro.S  |   34 +
 .../include/{mach => mach-iop33x}/gpio.h           |    0
 .../include/{mach => mach-iop33x}/hardware.h       |    0
 .../mach-iop33x/include/{mach => mach-iop33x}/io.h |    0
 .../include/{mach => mach-iop33x}/iop33x.h         |    0
 .../include/{mach => mach-iop33x}/iq80331.h        |    0
 .../include/{mach => mach-iop33x}/iq80332.h        |    0
 .../include/{mach => mach-iop33x}/irqs.h           |    0
 .../include/{mach => mach-iop33x}/time.h           |    0
 .../include/{mach => mach-iop33x}/timex.h          |    0
 .../mach-iop33x/include/mach-iop33x/uncompress.h   |   37 +
 arch/arm/mach-iop33x/include/mach/entry-macro.S    |   34 -
 arch/arm/mach-iop33x/include/mach/uncompress.h     |   37 -
 arch/arm/mach-iop33x/iq80331.c                     |    4 +-
 arch/arm/mach-iop33x/iq80332.c                     |    4 +-
 arch/arm/mach-iop33x/irq.c                         |    2 +-
 arch/arm/mach-iop33x/uart.c                        |    2 +-
 arch/arm/mach-ixp4xx/avila-pci.c                   |    2 +-
 arch/arm/mach-ixp4xx/avila-setup.c                 |    2 +-
 arch/arm/mach-ixp4xx/common-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/common.c                      |    6 +-
 arch/arm/mach-ixp4xx/coyote-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/coyote-setup.c                |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-pci.c             |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-setup.c           |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-setup.c              |    2 +-
 .../include/{mach => mach-ixp4xx}/cpu.h            |    0
 .../include/{mach => mach-ixp4xx}/debug-macro.S    |    0
 .../mach-ixp4xx/include/mach-ixp4xx/entry-macro.S  |   41 +
 .../include/{mach => mach-ixp4xx}/gpio.h           |    0
 .../arm/mach-ixp4xx/include/mach-ixp4xx/hardware.h |   36 +
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/io.h      |  502 ++++++
 .../include/{mach => mach-ixp4xx}/irqs.h           |    0
 .../include/{mach => mach-ixp4xx}/ixp46x_ts.h      |    0
 .../include/{mach => mach-ixp4xx}/ixp4xx-regs.h    |    0
 .../include/{mach => mach-ixp4xx}/npe.h            |    0
 .../arm/mach-ixp4xx/include/mach-ixp4xx/platform.h |  175 ++
 .../include/{mach => mach-ixp4xx}/qmgr.h           |    0
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/timex.h   |   16 +
 .../include/{mach => mach-ixp4xx}/udc.h            |    0
 .../include/{mach => mach-ixp4xx}/uncompress.h     |    0
 arch/arm/mach-ixp4xx/include/mach/entry-macro.S    |   41 -
 arch/arm/mach-ixp4xx/include/mach/hardware.h       |   36 -
 arch/arm/mach-ixp4xx/include/mach/io.h             |  502 ------
 arch/arm/mach-ixp4xx/include/mach/platform.h       |  175 --
 arch/arm/mach-ixp4xx/include/mach/timex.h          |   16 -
 arch/arm/mach-ixp4xx/ixdp425-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-setup.c               |    2 +-
 arch/arm/mach-ixp4xx/ixdpg425-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_npe.c                  |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_qmgr.c                 |    2 +-
 arch/arm/mach-ixp4xx/miccpt-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-setup.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |    4 +-
 arch/arm/mach-kirkwood/board-dnskw.c               |    4 +-
 arch/arm/mach-kirkwood/board-dreamplug.c           |    6 +-
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    6 +-
 arch/arm/mach-kirkwood/board-ib62x0.c              |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c            |    2 +-
 arch/arm/mach-kirkwood/board-lsxl.c                |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c               |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   22 +-
 arch/arm/mach-kirkwood/cpuidle.c                   |    2 +-
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    4 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    4 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    4 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    4 +-
 .../include/mach-kirkwood/bridge-regs.h            |   81 +
 .../include/mach-kirkwood/debug-macro.S            |   19 +
 .../include/mach-kirkwood/entry-macro.S            |   34 +
 .../arm/mach-kirkwood/include/mach-kirkwood/gpio.h |    9 +
 .../include/{mach => mach-kirkwood}/hardware.h     |    0
 .../include/{mach => mach-kirkwood}/io.h           |    0
 .../include/{mach => mach-kirkwood}/irqs.h         |    0
 .../include/{mach => mach-kirkwood}/kirkwood.h     |    0
 .../include/{mach => mach-kirkwood}/leds-netxbig.h |    0
 .../include/{mach => mach-kirkwood}/leds-ns2.h     |    0
 .../include/{mach => mach-kirkwood}/timex.h        |    0
 .../include/mach-kirkwood/uncompress.h             |   47 +
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h  |   81 -
 arch/arm/mach-kirkwood/include/mach/debug-macro.S  |   19 -
 arch/arm/mach-kirkwood/include/mach/entry-macro.S  |   34 -
 arch/arm/mach-kirkwood/include/mach/gpio.h         |    9 -
 arch/arm/mach-kirkwood/include/mach/uncompress.h   |   47 -
 arch/arm/mach-kirkwood/irq.c                       |    4 +-
 arch/arm/mach-kirkwood/lacie_v2-common.c           |    6 +-
 arch/arm/mach-kirkwood/mpp.c                       |    4 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c     |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    4 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    4 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    4 +-
 arch/arm/mach-kirkwood/pcie.c                      |    6 +-
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c       |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    4 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    4 +-
 arch/arm/mach-kirkwood/t5325-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c               |    4 +-
 arch/arm/mach-kirkwood/tsx1x-common.c              |    2 +-
 arch/arm/mach-ks8695/board-acs5k.c                 |    4 +-
 arch/arm/mach-ks8695/board-dsm320.c                |    4 +-
 arch/arm/mach-ks8695/board-micrel.c                |    4 +-
 arch/arm/mach-ks8695/cpu.c                         |    6 +-
 arch/arm/mach-ks8695/devices.c                     |   12 +-
 .../mach-ks8695/include/mach-ks8695/debug-macro.S  |   36 +
 .../include/{mach => mach-ks8695}/devices.h        |    0
 .../mach-ks8695/include/mach-ks8695/entry-macro.S  |   47 +
 .../include/{mach => mach-ks8695}/gpio-ks8695.h    |    0
 .../include/{mach => mach-ks8695}/gpio.h           |    0
 .../include/{mach => mach-ks8695}/hardware.h       |    0
 .../include/{mach => mach-ks8695}/irqs.h           |    0
 arch/arm/mach-ks8695/include/mach-ks8695/memory.h  |   55 +
 .../include/{mach => mach-ks8695}/regs-gpio.h      |    0
 .../include/{mach => mach-ks8695}/regs-hpna.h      |    0
 .../include/{mach => mach-ks8695}/regs-irq.h       |    0
 .../include/{mach => mach-ks8695}/regs-lan.h       |    0
 .../include/{mach => mach-ks8695}/regs-mem.h       |    0
 .../include/{mach => mach-ks8695}/regs-misc.h      |    0
 .../include/{mach => mach-ks8695}/regs-pci.h       |    0
 .../include/{mach => mach-ks8695}/regs-switch.h    |    0
 .../include/{mach => mach-ks8695}/regs-sys.h       |    0
 .../include/{mach => mach-ks8695}/regs-timer.h     |    0
 .../include/{mach => mach-ks8695}/regs-uart.h      |    0
 .../include/{mach => mach-ks8695}/regs-wan.h       |    0
 arch/arm/mach-ks8695/include/mach-ks8695/timex.h   |   21 +
 .../mach-ks8695/include/mach-ks8695/uncompress.h   |   37 +
 arch/arm/mach-ks8695/include/mach/debug-macro.S    |   36 -
 arch/arm/mach-ks8695/include/mach/entry-macro.S    |   47 -
 arch/arm/mach-ks8695/include/mach/memory.h         |   55 -
 arch/arm/mach-ks8695/include/mach/timex.h          |   21 -
 arch/arm/mach-ks8695/include/mach/uncompress.h     |   37 -
 arch/arm/mach-ks8695/irq.c                         |    6 +-
 arch/arm/mach-ks8695/leds.c                        |    2 +-
 arch/arm/mach-ks8695/pci.c                         |    6 +-
 arch/arm/mach-ks8695/time.c                        |    4 +-
 .../include/{mach => mach-l7200}/debug-macro.S     |    0
 arch/arm/mach-lpc32xx/clock.c                      |    4 +-
 arch/arm/mach-lpc32xx/common.c                     |    4 +-
 arch/arm/mach-lpc32xx/common.h                     |    2 +-
 .../include/{mach => mach-lpc32xx}/board.h         |    0
 .../include/{mach => mach-lpc32xx}/debug-macro.S   |    0
 .../include/mach-lpc32xx/entry-macro.S             |   37 +
 .../include/{mach => mach-lpc32xx}/gpio-lpc32xx.h  |    0
 .../include/{mach => mach-lpc32xx}/gpio.h          |    0
 .../include/{mach => mach-lpc32xx}/hardware.h      |    0
 .../include/{mach => mach-lpc32xx}/irqs.h          |    0
 .../include/{mach => mach-lpc32xx}/platform.h      |    0
 .../include/{mach => mach-lpc32xx}/timex.h         |    0
 .../mach-lpc32xx/include/mach-lpc32xx/uncompress.h |   60 +
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S   |   37 -
 arch/arm/mach-lpc32xx/include/mach/uncompress.h    |   60 -
 arch/arm/mach-lpc32xx/irq.c                        |    6 +-
 arch/arm/mach-lpc32xx/phy3250.c                    |    8 +-
 arch/arm/mach-lpc32xx/pm.c                         |    4 +-
 arch/arm/mach-lpc32xx/serial.c                     |    4 +-
 arch/arm/mach-lpc32xx/suspend.S                    |    4 +-
 arch/arm/mach-lpc32xx/timer.c                      |    4 +-
 arch/arm/mach-mmp/aspenite.c                       |   10 +-
 arch/arm/mach-mmp/avengers_lite.c                  |    8 +-
 arch/arm/mach-mmp/brownstone.c                     |    8 +-
 arch/arm/mach-mmp/clock.c                          |    2 +-
 arch/arm/mach-mmp/common.c                         |    4 +-
 arch/arm/mach-mmp/devices.c                        |    8 +-
 arch/arm/mach-mmp/flint.c                          |    8 +-
 arch/arm/mach-mmp/gplugd.c                         |    6 +-
 .../mach-mmp/include/{mach => mach-mmp}/addr-map.h |    0
 .../mach-mmp/include/{mach => mach-mmp}/cputype.h  |    0
 arch/arm/mach-mmp/include/mach-mmp/debug-macro.S   |   22 +
 .../mach-mmp/include/{mach => mach-mmp}/devices.h  |    0
 arch/arm/mach-mmp/include/mach-mmp/dma.h           |   13 +
 arch/arm/mach-mmp/include/mach-mmp/entry-macro.S   |   26 +
 arch/arm/mach-mmp/include/mach-mmp/gpio.h          |    8 +
 .../mach-mmp/include/{mach => mach-mmp}/hardware.h |    0
 .../arm/mach-mmp/include/{mach => mach-mmp}/irqs.h |    0
 arch/arm/mach-mmp/include/mach-mmp/mfp-mmp2.h      |  395 +++++
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa168.h    |  354 +++++
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa910.h    |  170 ++
 arch/arm/mach-mmp/include/mach-mmp/mfp.h           |   34 +
 arch/arm/mach-mmp/include/mach-mmp/mmp2.h          |  104 ++
 arch/arm/mach-mmp/include/mach-mmp/pm-mmp2.h       |   61 +
 .../include/{mach => mach-mmp}/pm-pxa910.h         |    0
 arch/arm/mach-mmp/include/mach-mmp/pxa168.h        |  136 ++
 arch/arm/mach-mmp/include/mach-mmp/pxa910.h        |   85 +
 arch/arm/mach-mmp/include/mach-mmp/regs-apbc.h     |  119 ++
 arch/arm/mach-mmp/include/mach-mmp/regs-apmu.h     |   48 +
 arch/arm/mach-mmp/include/mach-mmp/regs-icu.h      |   71 +
 arch/arm/mach-mmp/include/mach-mmp/regs-rtc.h      |   23 +
 arch/arm/mach-mmp/include/mach-mmp/regs-smc.h      |   37 +
 arch/arm/mach-mmp/include/mach-mmp/regs-timers.h   |   44 +
 .../mach-mmp/include/{mach => mach-mmp}/regs-usb.h |    0
 .../arm/mach-mmp/include/{mach => mach-mmp}/sram.h |    0
 .../include/{mach => mach-mmp}/teton_bga.h         |    0
 .../mach-mmp/include/{mach => mach-mmp}/timex.h    |    0
 arch/arm/mach-mmp/include/mach-mmp/uncompress.h    |   51 +
 arch/arm/mach-mmp/include/mach/debug-macro.S       |   22 -
 arch/arm/mach-mmp/include/mach/dma.h               |   13 -
 arch/arm/mach-mmp/include/mach/entry-macro.S       |   26 -
 arch/arm/mach-mmp/include/mach/gpio.h              |    8 -
 arch/arm/mach-mmp/include/mach/mfp-mmp2.h          |  395 -----
 arch/arm/mach-mmp/include/mach/mfp-pxa168.h        |  354 -----
 arch/arm/mach-mmp/include/mach/mfp-pxa910.h        |  170 --
 arch/arm/mach-mmp/include/mach/mfp.h               |   34 -
 arch/arm/mach-mmp/include/mach/mmp2.h              |  104 --
 arch/arm/mach-mmp/include/mach/pm-mmp2.h           |   61 -
 arch/arm/mach-mmp/include/mach/pxa168.h            |  136 --
 arch/arm/mach-mmp/include/mach/pxa910.h            |   85 -
 arch/arm/mach-mmp/include/mach/regs-apbc.h         |  119 --
 arch/arm/mach-mmp/include/mach/regs-apmu.h         |   48 -
 arch/arm/mach-mmp/include/mach/regs-icu.h          |   71 -
 arch/arm/mach-mmp/include/mach/regs-rtc.h          |   23 -
 arch/arm/mach-mmp/include/mach/regs-smc.h          |   37 -
 arch/arm/mach-mmp/include/mach/regs-timers.h       |   44 -
 arch/arm/mach-mmp/include/mach/uncompress.h        |   51 -
 arch/arm/mach-mmp/irq.c                            |    6 +-
 arch/arm/mach-mmp/jasper.c                         |    8 +-
 arch/arm/mach-mmp/mmp-dt.c                         |    2 +-
 arch/arm/mach-mmp/mmp2-dt.c                        |    4 +-
 arch/arm/mach-mmp/mmp2.c                           |   18 +-
 arch/arm/mach-mmp/pm-mmp2.c                        |   12 +-
 arch/arm/mach-mmp/pm-pxa910.c                      |   12 +-
 arch/arm/mach-mmp/pxa168.c                         |   20 +-
 arch/arm/mach-mmp/pxa910.c                         |   16 +-
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mmp/tavorevb.c                       |    8 +-
 arch/arm/mach-mmp/teton_bga.c                      |   12 +-
 arch/arm/mach-mmp/time.c                           |   10 +-
 arch/arm/mach-mmp/ttc_dkb.c                        |   10 +-
 arch/arm/mach-msm/acpuclock-arm11.c                |    4 +-
 arch/arm/mach-msm/board-halibut.c                  |    8 +-
 arch/arm/mach-msm/board-mahimahi.c                 |    6 +-
 arch/arm/mach-msm/board-msm7x27.c                  |   10 +-
 arch/arm/mach-msm/board-msm7x30.c                  |    8 +-
 arch/arm/mach-msm/board-msm8960.c                  |    4 +-
 arch/arm/mach-msm/board-msm8x60.c                  |    4 +-
 arch/arm/mach-msm/board-qsd8x50.c                  |   10 +-
 arch/arm/mach-msm/board-sapphire.c                 |    8 +-
 arch/arm/mach-msm/board-trout-mmc.c                |    4 +-
 arch/arm/mach-msm/board-trout-panel.c              |    4 +-
 arch/arm/mach-msm/board-trout.c                    |    6 +-
 arch/arm/mach-msm/board-trout.h                    |    4 +-
 arch/arm/mach-msm/clock-pcom.c                     |    2 +-
 arch/arm/mach-msm/clock.h                          |    2 +-
 arch/arm/mach-msm/devices-iommu.c                  |    4 +-
 arch/arm/mach-msm/devices-msm7x00.c                |    6 +-
 arch/arm/mach-msm/devices-msm7x30.c                |   10 +-
 arch/arm/mach-msm/devices-msm8960.c                |    4 +-
 arch/arm/mach-msm/devices-qsd8x50.c                |   10 +-
 arch/arm/mach-msm/dma.c                            |    2 +-
 arch/arm/mach-msm/gpiomux-v2.c                     |    2 +-
 arch/arm/mach-msm/gpiomux.h                        |    2 +-
 arch/arm/mach-msm/include/mach-msm/board.h         |   56 +
 arch/arm/mach-msm/include/{mach => mach-msm}/clk.h |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h |    0
 arch/arm/mach-msm/include/mach-msm/debug-macro.S   |   65 +
 arch/arm/mach-msm/include/mach-msm/dma.h           |  177 +++
 arch/arm/mach-msm/include/mach-msm/entry-macro.S   |   36 +
 .../mach => mach-msm/include/mach-msm}/gpio.h      |    0
 .../mach-msm/include/{mach => mach-msm}/hardware.h |    0
 .../mach-msm/include/{mach => mach-msm}/iommu.h    |    0
 .../include/{mach => mach-msm}/iommu_hw-8xxx.h     |    0
 .../include/{mach => mach-msm}/irqs-7x00.h         |    0
 .../include/{mach => mach-msm}/irqs-7x30.h         |    0
 .../include/{mach => mach-msm}/irqs-8960.h         |    0
 .../include/{mach => mach-msm}/irqs-8x50.h         |    0
 .../include/{mach => mach-msm}/irqs-8x60.h         |    0
 .../arm/mach-msm/include/{mach => mach-msm}/irqs.h |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h |    0
 .../mach-msm/include/{mach => mach-msm}/msm_fb.h   |    0
 .../include/{mach => mach-msm}/msm_gpiomux.h       |    0
 .../include/{mach => mach-msm}/msm_iomap-7x00.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-7x30.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8960.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8x50.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8x60.h    |    0
 .../include/{mach => mach-msm}/msm_iomap.h         |    0
 .../mach-msm/include/{mach => mach-msm}/msm_smd.h  |    0
 arch/arm/mach-msm/include/mach-msm/sirc.h          |   98 ++
 .../mach-msm/include/{mach => mach-msm}/system.h   |    0
 .../mach-msm/include/{mach => mach-msm}/timex.h    |    0
 arch/arm/mach-msm/include/mach-msm/uncompress.h    |   67 +
 .../arm/mach-msm/include/{mach => mach-msm}/vreg.h |    0
 arch/arm/mach-msm/include/mach/board.h             |   56 -
 arch/arm/mach-msm/include/mach/debug-macro.S       |   65 -
 arch/arm/mach-msm/include/mach/dma.h               |  177 ---
 arch/arm/mach-msm/include/mach/entry-macro.S       |   36 -
 arch/arm/mach-msm/include/mach/sirc.h              |   98 --
 arch/arm/mach-msm/include/mach/uncompress.h        |   67 -
 arch/arm/mach-msm/io.c                             |    6 +-
 arch/arm/mach-msm/irq-vic.c                        |    4 +-
 arch/arm/mach-msm/irq.c                            |    4 +-
 arch/arm/mach-msm/platsmp.c                        |    2 +-
 arch/arm/mach-msm/proc_comm.c                      |    4 +-
 arch/arm/mach-msm/smd.c                            |    4 +-
 arch/arm/mach-msm/smd_debug.c                      |    2 +-
 arch/arm/mach-msm/smd_private.h                    |    2 +-
 arch/arm/mach-msm/timer.c                          |    6 +-
 arch/arm/mach-msm/vreg.c                           |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    2 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |   16 +-
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |    2 +-
 .../include/mach-mv78xx0/bridge-regs.h             |   36 +
 .../include/mach-mv78xx0/debug-macro.S             |   19 +
 .../include/mach-mv78xx0/entry-macro.S             |   41 +
 arch/arm/mach-mv78xx0/include/mach-mv78xx0/gpio.h  |    9 +
 .../include/{mach => mach-mv78xx0}/hardware.h      |    0
 .../include/{mach => mach-mv78xx0}/io.h            |    0
 .../include/{mach => mach-mv78xx0}/irqs.h          |    0
 .../include/{mach => mach-mv78xx0}/mv78xx0.h       |    0
 .../include/{mach => mach-mv78xx0}/timex.h         |    0
 .../mach-mv78xx0/include/mach-mv78xx0/uncompress.h |   47 +
 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h   |   36 -
 arch/arm/mach-mv78xx0/include/mach/debug-macro.S   |   19 -
 arch/arm/mach-mv78xx0/include/mach/entry-macro.S   |   41 -
 arch/arm/mach-mv78xx0/include/mach/gpio.h          |    9 -
 arch/arm/mach-mv78xx0/include/mach/uncompress.h    |   47 -
 arch/arm/mach-mv78xx0/irq.c                        |    4 +-
 arch/arm/mach-mv78xx0/mpp.c                        |    4 +-
 arch/arm/mach-mv78xx0/pcie.c                       |    4 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |    2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |    2 +-
 .../include/{mach => mach-mvebu}/armada-370-xp.h   |    0
 .../mach-mvebu/include/mach-mvebu/debug-macro.S    |   24 +
 .../include/{mach => mach-mvebu}/timex.h           |    0
 .../arm/mach-mvebu/include/mach-mvebu/uncompress.h |   43 +
 arch/arm/mach-mvebu/include/mach/debug-macro.S     |   24 -
 arch/arm/mach-mvebu/include/mach/uncompress.h      |   43 -
 arch/arm/mach-mxs/devices-mx23.h                   |    4 +-
 arch/arm/mach-mxs/devices-mx28.h                   |    4 +-
 arch/arm/mach-mxs/devices/platform-auart.c         |    6 +-
 arch/arm/mach-mxs/devices/platform-dma.c           |    6 +-
 arch/arm/mach-mxs/devices/platform-fec.c           |    4 +-
 arch/arm/mach-mxs/devices/platform-flexcan.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c      |    6 +-
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c     |    6 +-
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c       |    6 +-
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c       |    2 +-
 arch/arm/mach-mxs/devices/platform-mxs-saif.c      |    6 +-
 arch/arm/mach-mxs/devices/platform-mxsfb.c         |    6 +-
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c  |    6 +-
 arch/arm/mach-mxs/icoll.c                          |    4 +-
 .../mach-mxs/include/{mach => mach-mxs}/common.h   |    0
 arch/arm/mach-mxs/include/mach-mxs/debug-macro.S   |   30 +
 .../include/{mach => mach-mxs}/devices-common.h    |    0
 .../mach-mxs/include/{mach => mach-mxs}/digctl.h   |    0
 arch/arm/mach-mxs/include/mach-mxs/entry-macro.S   |   35 +
 .../mach => mach-mxs/include/mach-mxs}/gpio.h      |    0
 .../mach-mxs/include/{mach => mach-mxs}/hardware.h |    0
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx23.h    |  355 +++++
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx28.h    |  537 +++++++
 .../mach-mxs/include/{mach => mach-mxs}/iomux.h    |    0
 .../arm/mach-mxs/include/{mach => mach-mxs}/irqs.h |    0
 arch/arm/mach-mxs/include/mach-mxs/mx23.h          |  169 ++
 arch/arm/mach-mxs/include/mach-mxs/mx28.h          |  225 +++
 arch/arm/mach-mxs/include/mach-mxs/mxs.h           |  117 ++
 .../mach-mxs/include/{mach => mach-mxs}/timex.h    |    0
 .../include/{mach => mach-mxs}/uncompress.h        |    0
 arch/arm/mach-mxs/include/mach/debug-macro.S       |   30 -
 arch/arm/mach-mxs/include/mach/entry-macro.S       |   35 -
 arch/arm/mach-mxs/include/mach/iomux-mx23.h        |  355 -----
 arch/arm/mach-mxs/include/mach/iomux-mx28.h        |  537 -------
 arch/arm/mach-mxs/include/mach/mx23.h              |  169 --
 arch/arm/mach-mxs/include/mach/mx28.h              |  225 ---
 arch/arm/mach-mxs/include/mach/mxs.h               |  117 --
 arch/arm/mach-mxs/iomux.c                          |    4 +-
 arch/arm/mach-mxs/mach-apx4devkit.c                |    6 +-
 arch/arm/mach-mxs/mach-m28evk.c                    |    4 +-
 arch/arm/mach-mxs/mach-mx23evk.c                   |    4 +-
 arch/arm/mach-mxs/mach-mx28evk.c                   |    6 +-
 arch/arm/mach-mxs/mach-mxs.c                       |    2 +-
 arch/arm/mach-mxs/mach-stmp378x_devb.c             |    4 +-
 arch/arm/mach-mxs/mach-tx28.c                      |    4 +-
 arch/arm/mach-mxs/mm.c                             |    8 +-
 arch/arm/mach-mxs/module-tx28.c                    |    2 +-
 arch/arm/mach-mxs/ocotp.c                          |    2 +-
 arch/arm/mach-mxs/system.c                         |    4 +-
 arch/arm/mach-mxs/timer.c                          |    4 +-
 arch/arm/mach-netx/fb.c                            |    4 +-
 arch/arm/mach-netx/generic.c                       |    4 +-
 .../include/{mach => mach-netx}/debug-macro.S      |    0
 .../mach-netx/include/{mach => mach-netx}/eth.h    |    0
 .../include/{mach => mach-netx}/hardware.h         |    0
 .../mach-netx/include/{mach => mach-netx}/irqs.h   |    0
 .../include/{mach => mach-netx}/netx-regs.h        |    0
 .../mach-netx/include/{mach => mach-netx}/param.h  |    0
 .../mach-netx/include/{mach => mach-netx}/pfifo.h  |    0
 .../mach-netx/include/{mach => mach-netx}/timex.h  |    0
 .../include/{mach => mach-netx}/uncompress.h       |    0
 .../arm/mach-netx/include/{mach => mach-netx}/xc.h |    0
 arch/arm/mach-netx/nxdb500.c                       |    6 +-
 arch/arm/mach-netx/nxdkn.c                         |    6 +-
 arch/arm/mach-netx/nxeb500hmi.c                    |    6 +-
 arch/arm/mach-netx/pfifo.c                         |    6 +-
 arch/arm/mach-netx/time.c                          |    4 +-
 arch/arm/mach-netx/xc.c                            |    8 +-
 arch/arm/mach-nomadik/board-nhk8815.c              |    8 +-
 arch/arm/mach-nomadik/cpu-8815.c                   |    6 +-
 arch/arm/mach-nomadik/i2c-8815nhk.c                |    4 +-
 .../include/{mach => mach-nomadik}/debug-macro.S   |    0
 arch/arm/mach-nomadik/include/mach-nomadik/fsmc.h  |   29 +
 .../include/{mach => mach-nomadik}/gpio.h          |    0
 .../include/{mach => mach-nomadik}/hardware.h      |    0
 arch/arm/mach-nomadik/include/mach-nomadik/irqs.h  |   81 +
 .../include/{mach => mach-nomadik}/nand.h          |    0
 .../include/{mach => mach-nomadik}/timex.h         |    0
 .../mach-nomadik/include/mach-nomadik/uncompress.h |   63 +
 arch/arm/mach-nomadik/include/mach/fsmc.h          |   29 -
 arch/arm/mach-nomadik/include/mach/irqs.h          |   81 -
 arch/arm/mach-nomadik/include/mach/uncompress.h    |   63 -
 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    4 +-
 arch/arm/mach-omap1/ams-delta-fiq.c                |    4 +-
 arch/arm/mach-omap1/board-ams-delta.c              |   18 +-
 arch/arm/mach-omap1/board-fsample.c                |   16 +-
 arch/arm/mach-omap1/board-generic.c                |    8 +-
 arch/arm/mach-omap1/board-h2-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h2.c                     |   18 +-
 arch/arm/mach-omap1/board-h3-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h3.c                     |   18 +-
 arch/arm/mach-omap1/board-htcherald.c              |   12 +-
 arch/arm/mach-omap1/board-innovator.c              |   18 +-
 arch/arm/mach-omap1/board-nokia770.c               |   18 +-
 arch/arm/mach-omap1/board-osk.c                    |   12 +-
 arch/arm/mach-omap1/board-palmte.c                 |   18 +-
 arch/arm/mach-omap1/board-palmtt.c                 |   22 +-
 arch/arm/mach-omap1/board-palmz71.c                |   20 +-
 arch/arm/mach-omap1/board-perseus2.c               |   16 +-
 arch/arm/mach-omap1/board-sx1-mmc.c                |    6 +-
 arch/arm/mach-omap1/board-sx1.c                    |   22 +-
 arch/arm/mach-omap1/board-voiceblue.c              |   16 +-
 arch/arm/mach-omap1/clock.c                        |   12 +-
 arch/arm/mach-omap1/clock.h                        |    2 +-
 arch/arm/mach-omap1/clock_data.c                   |   16 +-
 arch/arm/mach-omap1/common.h                       |    2 +-
 arch/arm/mach-omap1/devices.c                      |   18 +-
 arch/arm/mach-omap1/dma.c                          |    6 +-
 arch/arm/mach-omap1/flash.c                        |    6 +-
 arch/arm/mach-omap1/fpga.c                         |    4 +-
 arch/arm/mach-omap1/i2c.c                          |    6 +-
 arch/arm/mach-omap1/id.c                           |    4 +-
 .../mach-omap1/include/mach-omap1/ams-delta-fiq.h  |   79 +
 .../include/{mach => mach-omap1}/camera.h          |    0
 .../mach-omap1/include/mach-omap1/debug-macro.S    |  101 ++
 .../mach-omap1/include/mach-omap1/entry-macro.S    |   41 +
 arch/arm/mach-omap1/include/mach-omap1/gpio.h      |    5 +
 arch/arm/mach-omap1/include/mach-omap1/hardware.h  |   41 +
 .../mach-omap1/include/{mach => mach-omap1}/io.h   |    0
 arch/arm/mach-omap1/include/mach-omap1/irqs.h      |    5 +
 .../include/{mach => mach-omap1}/lcd_dma.h         |    0
 .../mach-omap1/include/{mach => mach-omap1}/lcdc.h |    0
 arch/arm/mach-omap1/include/mach-omap1/memory.h    |   57 +
 arch/arm/mach-omap1/include/mach-omap1/mtd-xip.h   |   61 +
 arch/arm/mach-omap1/include/mach-omap1/smp.h       |    5 +
 arch/arm/mach-omap1/include/mach-omap1/timex.h     |    5 +
 .../arm/mach-omap1/include/mach-omap1/uncompress.h |    5 +
 .../mach-omap1/include/{mach => mach-omap1}/usb.h  |    0
 arch/arm/mach-omap1/include/mach/ams-delta-fiq.h   |   79 -
 arch/arm/mach-omap1/include/mach/debug-macro.S     |  101 --
 arch/arm/mach-omap1/include/mach/entry-macro.S     |   41 -
 arch/arm/mach-omap1/include/mach/gpio.h            |    5 -
 arch/arm/mach-omap1/include/mach/hardware.h        |   41 -
 arch/arm/mach-omap1/include/mach/irqs.h            |    5 -
 arch/arm/mach-omap1/include/mach/memory.h          |   57 -
 arch/arm/mach-omap1/include/mach/mtd-xip.h         |   61 -
 arch/arm/mach-omap1/include/mach/smp.h             |    5 -
 arch/arm/mach-omap1/include/mach/timex.h           |    5 -
 arch/arm/mach-omap1/include/mach/uncompress.h      |    5 -
 arch/arm/mach-omap1/io.c                           |    6 +-
 arch/arm/mach-omap1/irq.c                          |    4 +-
 arch/arm/mach-omap1/lcd_dma.c                      |    6 +-
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 +-
 arch/arm/mach-omap1/leds-innovator.c               |    2 +-
 arch/arm/mach-omap1/leds-osk.c                     |    2 +-
 arch/arm/mach-omap1/leds.c                         |    2 +-
 arch/arm/mach-omap1/mailbox.c                      |    2 +-
 arch/arm/mach-omap1/mcbsp.c                        |   10 +-
 arch/arm/mach-omap1/mux.c                          |    4 +-
 arch/arm/mach-omap1/ocpi.c                         |    2 +-
 arch/arm/mach-omap1/opp_data.c                     |    2 +-
 arch/arm/mach-omap1/pm.c                           |   18 +-
 arch/arm/mach-omap1/pm_bus.c                       |    4 +-
 arch/arm/mach-omap1/reset.c                        |    4 +-
 arch/arm/mach-omap1/serial.c                       |    6 +-
 arch/arm/mach-omap1/sram.S                         |    2 +-
 arch/arm/mach-omap1/time.c                         |    2 +-
 arch/arm/mach-omap1/timer.c                        |    4 +-
 arch/arm/mach-omap1/timer32k.c                     |    4 +-
 arch/arm/mach-omap1/usb.c                          |    4 +-
 arch/arm/mach-omap2/am35xx-emac.c                  |    4 +-
 arch/arm/mach-omap2/board-2430sdp.c                |   10 +-
 arch/arm/mach-omap2/board-3430sdp.c                |   14 +-
 arch/arm/mach-omap2/board-3630sdp.c                |    8 +-
 arch/arm/mach-omap2/board-4430sdp.c                |   10 +-
 arch/arm/mach-omap2/board-am3517crane.c            |    6 +-
 arch/arm/mach-omap2/board-am3517evm.c              |    8 +-
 arch/arm/mach-omap2/board-apollon.c                |    8 +-
 arch/arm/mach-omap2/board-cm-t35.c                 |   14 +-
 arch/arm/mach-omap2/board-cm-t3517.c               |   10 +-
 arch/arm/mach-omap2/board-devkit8000.c             |   14 +-
 arch/arm/mach-omap2/board-flash.c                  |   10 +-
 arch/arm/mach-omap2/board-flash.h                  |    2 +-
 arch/arm/mach-omap2/board-generic.c                |    4 +-
 arch/arm/mach-omap2/board-h4.c                     |   10 +-
 arch/arm/mach-omap2/board-igep0020.c               |   10 +-
 arch/arm/mach-omap2/board-ldp.c                    |   14 +-
 arch/arm/mach-omap2/board-n8x0.c                   |   14 +-
 arch/arm/mach-omap2/board-omap3beagle.c            |   12 +-
 arch/arm/mach-omap2/board-omap3evm.c               |   12 +-
 arch/arm/mach-omap2/board-omap3logic.c             |   14 +-
 arch/arm/mach-omap2/board-omap3pandora.c           |   10 +-
 arch/arm/mach-omap2/board-omap3stalker.c           |   14 +-
 arch/arm/mach-omap2/board-omap3touchbook.c         |   12 +-
 arch/arm/mach-omap2/board-omap4panda.c             |    8 +-
 arch/arm/mach-omap2/board-overo.c                  |   16 +-
 arch/arm/mach-omap2/board-rm680.c                  |   10 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c       |   14 +-
 arch/arm/mach-omap2/board-rx51-video.c             |    6 +-
 arch/arm/mach-omap2/board-rx51.c                   |   12 +-
 arch/arm/mach-omap2/board-ti8168evm.c              |    8 +-
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    6 +-
 arch/arm/mach-omap2/board-zoom-display.c           |    4 +-
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    4 +-
 arch/arm/mach-omap2/board-zoom.c                   |    6 +-
 arch/arm/mach-omap2/clkt2xxx_apll.c                |    4 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c                |    2 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c            |    6 +-
 arch/arm/mach-omap2/clkt2xxx_osc.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c       |    8 +-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c             |    6 +-
 arch/arm/mach-omap2/clkt_clksel.c                  |    2 +-
 arch/arm/mach-omap2/clkt_dpll.c                    |    4 +-
 arch/arm/mach-omap2/clkt_iclk.c                    |    4 +-
 arch/arm/mach-omap2/clock.c                        |    6 +-
 arch/arm/mach-omap2/clock.h                        |    2 +-
 arch/arm/mach-omap2/clock2420_data.c               |    4 +-
 arch/arm/mach-omap2/clock2430.c                    |    4 +-
 arch/arm/mach-omap2/clock2430_data.c               |    4 +-
 arch/arm/mach-omap2/clock2xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock33xx_data.c               |    4 +-
 arch/arm/mach-omap2/clock34xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3517.c                    |    2 +-
 arch/arm/mach-omap2/clock36xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock3xxx_data.c               |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c               |    4 +-
 arch/arm/mach-omap2/clockdomain.c                  |    2 +-
 arch/arm/mach-omap2/clockdomain.h                  |    6 +-
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx.c                  |    2 +-
 arch/arm/mach-omap2/cm33xx.c                       |    2 +-
 arch/arm/mach-omap2/common-board-devices.c         |    4 +-
 arch/arm/mach-omap2/common.c                       |    8 +-
 arch/arm/mach-omap2/common.h                       |    2 +-
 arch/arm/mach-omap2/control.c                      |    4 +-
 arch/arm/mach-omap2/control.h                      |   10 +-
 arch/arm/mach-omap2/cpuidle34xx.c                  |    4 +-
 arch/arm/mach-omap2/devices.c                      |   18 +-
 arch/arm/mach-omap2/display.c                      |    6 +-
 arch/arm/mach-omap2/dma.c                          |    6 +-
 arch/arm/mach-omap2/dpll3xxx.c                     |    4 +-
 arch/arm/mach-omap2/dpll44xx.c                     |    4 +-
 arch/arm/mach-omap2/drm.c                          |    4 +-
 arch/arm/mach-omap2/dsp.c                          |    4 +-
 arch/arm/mach-omap2/emu.c                          |    2 +-
 arch/arm/mach-omap2/gpio.c                         |    6 +-
 arch/arm/mach-omap2/gpmc-nand.c                    |    8 +-
 arch/arm/mach-omap2/gpmc-onenand.c                 |    8 +-
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    6 +-
 arch/arm/mach-omap2/gpmc-smsc911x.c                |    6 +-
 arch/arm/mach-omap2/gpmc.c                         |    4 +-
 arch/arm/mach-omap2/hdq1w.c                        |    6 +-
 arch/arm/mach-omap2/hsmmc.c                        |   10 +-
 arch/arm/mach-omap2/hwspinlock.c                   |    4 +-
 arch/arm/mach-omap2/i2c.c                          |    6 +-
 arch/arm/mach-omap2/id.c                           |    4 +-
 .../include/{mach => mach-omap2}/am35xx.h          |    0
 .../include/{mach => mach-omap2}/barriers.h        |    0
 .../include/{mach => mach-omap2}/board-rx51.h      |    0
 .../include/{mach => mach-omap2}/board-zoom.h      |    0
 .../{mach => mach-omap2}/ctrl_module_core_44xx.h   |    0
 .../ctrl_module_pad_core_44xx.h                    |    0
 .../ctrl_module_pad_wkup_44xx.h                    |    0
 .../{mach => mach-omap2}/ctrl_module_wkup_44xx.h   |    0
 .../mach-omap2/include/mach-omap2/debug-macro.S    |  165 ++
 arch/arm/mach-omap2/include/mach-omap2/gpio.h      |    5 +
 arch/arm/mach-omap2/include/mach-omap2/hardware.h  |    5 +
 .../mach-omap2/include/{mach => mach-omap2}/id.h   |    0
 arch/arm/mach-omap2/include/mach-omap2/irqs.h      |    5 +
 .../include/{mach => mach-omap2}/omap-secure.h     |    0
 .../include/{mach => mach-omap2}/omap-wakeupgen.h  |    0
 arch/arm/mach-omap2/include/mach-omap2/smp.h       |    5 +
 arch/arm/mach-omap2/include/mach-omap2/timex.h     |    5 +
 .../arm/mach-omap2/include/mach-omap2/uncompress.h |    5 +
 arch/arm/mach-omap2/include/mach/debug-macro.S     |  165 --
 arch/arm/mach-omap2/include/mach/gpio.h            |    5 -
 arch/arm/mach-omap2/include/mach/hardware.h        |    5 -
 arch/arm/mach-omap2/include/mach/irqs.h            |    5 -
 arch/arm/mach-omap2/include/mach/smp.h             |    5 -
 arch/arm/mach-omap2/include/mach/timex.h           |    5 -
 arch/arm/mach-omap2/include/mach/uncompress.h      |    5 -
 arch/arm/mach-omap2/io.c                           |   14 +-
 arch/arm/mach-omap2/iommu2.c                       |    2 +-
 arch/arm/mach-omap2/irq.c                          |    2 +-
 arch/arm/mach-omap2/mailbox.c                      |    4 +-
 arch/arm/mach-omap2/mcbsp.c                        |   10 +-
 arch/arm/mach-omap2/msdi.c                         |    6 +-
 arch/arm/mach-omap2/mux.c                          |    2 +-
 arch/arm/mach-omap2/omap-hotplug.c                 |    2 +-
 arch/arm/mach-omap2/omap-iommu.c                   |    4 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c          |    2 +-
 arch/arm/mach-omap2/omap-secure.c                  |    4 +-
 arch/arm/mach-omap2/omap-smp.c                     |    6 +-
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |   12 +-
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   24 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   24 +-
 .../omap_hwmod_2xxx_3xxx_interconnect_data.c       |    4 +-
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 +-
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |    8 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   16 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   28 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   20 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.c       |    2 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    2 +-
 arch/arm/mach-omap2/omap_opp_data.h                |    2 +-
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 +-
 arch/arm/mach-omap2/opp.c                          |    2 +-
 arch/arm/mach-omap2/opp2420_data.c                 |    2 +-
 arch/arm/mach-omap2/opp2430_data.c                 |    2 +-
 arch/arm/mach-omap2/opp3xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/opp4xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                     |    8 +-
 arch/arm/mach-omap2/pm.c                           |    4 +-
 arch/arm/mach-omap2/pm24xx.c                       |   10 +-
 arch/arm/mach-omap2/pm34xx.c                       |   10 +-
 arch/arm/mach-omap2/powerdomain.c                  |    4 +-
 arch/arm/mach-omap2/powerdomain.h                  |    2 +-
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/powerdomain33xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomain44xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c        |    2 +-
 arch/arm/mach-omap2/prcm.c                         |    4 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    6 +-
 arch/arm/mach-omap2/prm33xx.c                      |    2 +-
 arch/arm/mach-omap2/prm44xx.c                      |    6 +-
 arch/arm/mach-omap2/prm_common.c                   |    6 +-
 arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h |    2 +-
 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h  |    2 +-
 arch/arm/mach-omap2/sdram-nokia.c                  |    4 +-
 arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h     |    2 +-
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    2 +-
 arch/arm/mach-omap2/sdrc.c                         |    6 +-
 arch/arm/mach-omap2/sdrc.h                         |    2 +-
 arch/arm/mach-omap2/sdrc2xxx.c                     |    8 +-
 arch/arm/mach-omap2/serial.c                       |   12 +-
 arch/arm/mach-omap2/sleep24xx.S                    |    2 +-
 arch/arm/mach-omap2/sleep34xx.S                    |    4 +-
 arch/arm/mach-omap2/sleep44xx.S                    |    4 +-
 arch/arm/mach-omap2/sr_device.c                    |    2 +-
 arch/arm/mach-omap2/sram242x.S                     |    2 +-
 arch/arm/mach-omap2/sram243x.S                     |    2 +-
 arch/arm/mach-omap2/sram34xx.S                     |    2 +-
 arch/arm/mach-omap2/timer.c                        |    8 +-
 arch/arm/mach-omap2/twl-common.c                   |    4 +-
 arch/arm/mach-omap2/twl-common.h                   |    2 +-
 arch/arm/mach-omap2/usb-host.c                     |    8 +-
 arch/arm/mach-omap2/usb-musb.c                     |   10 +-
 arch/arm/mach-omap2/usb-tusb6010.c                 |    2 +-
 arch/arm/mach-omap2/vc.c                           |    2 +-
 arch/arm/mach-omap2/voltage.h                      |    2 +-
 arch/arm/mach-omap2/voltagedomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/wd_timer.c                     |    2 +-
 arch/arm/mach-omap2/wd_timer.h                     |    2 +-
 arch/arm/mach-orion5x/addr-map.c                   |    4 +-
 arch/arm/mach-orion5x/common.c                     |   16 +-
 arch/arm/mach-orion5x/d2net-setup.c                |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    4 +-
 arch/arm/mach-orion5x/dns323-setup.c               |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |    2 +-
 .../include/mach-orion5x/bridge-regs.h             |   39 +
 .../include/mach-orion5x/debug-macro.S             |   21 +
 .../include/mach-orion5x/entry-macro.S             |   25 +
 arch/arm/mach-orion5x/include/mach-orion5x/gpio.h  |    9 +
 .../include/{mach => mach-orion5x}/hardware.h      |    0
 arch/arm/mach-orion5x/include/mach-orion5x/io.h    |   22 +
 .../include/{mach => mach-orion5x}/irqs.h          |    0
 .../include/{mach => mach-orion5x}/orion5x.h       |    0
 .../include/{mach => mach-orion5x}/timex.h         |    0
 .../mach-orion5x/include/mach-orion5x/uncompress.h |   49 +
 arch/arm/mach-orion5x/include/mach/bridge-regs.h   |   39 -
 arch/arm/mach-orion5x/include/mach/debug-macro.S   |   21 -
 arch/arm/mach-orion5x/include/mach/entry-macro.S   |   25 -
 arch/arm/mach-orion5x/include/mach/gpio.h          |    9 -
 arch/arm/mach-orion5x/include/mach/io.h            |   22 -
 arch/arm/mach-orion5x/include/mach/uncompress.h    |   49 -
 arch/arm/mach-orion5x/irq.c                        |    4 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    4 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |    2 +-
 arch/arm/mach-orion5x/mpp.c                        |    4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |    4 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c              |    2 +-
 arch/arm/mach-orion5x/pci.c                        |    6 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c               |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c               |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |    2 +-
 arch/arm/mach-picoxcell/common.c                   |    4 +-
 .../include/mach-picoxcell/debug-macro.S           |   35 +
 .../include/mach-picoxcell}/gpio.h                 |    0
 .../include/mach-picoxcell/hardware.h              |   21 +
 .../include/{mach => mach-picoxcell}/map.h         |    0
 .../{mach => mach-picoxcell}/picoxcell_soc.h       |    0
 .../include/{mach => mach-picoxcell}/timex.h       |    0
 .../include/{mach => mach-picoxcell}/uncompress.h  |    0
 arch/arm/mach-picoxcell/include/mach/debug-macro.S |   35 -
 arch/arm/mach-picoxcell/include/mach/hardware.h    |   21 -
 arch/arm/mach-pnx4008/clock.c                      |    4 +-
 arch/arm/mach-pnx4008/core.c                       |    8 +-
 arch/arm/mach-pnx4008/dma.c                        |    6 +-
 arch/arm/mach-pnx4008/gpio.c                       |    6 +-
 arch/arm/mach-pnx4008/i2c.c                        |    4 +-
 .../include/{mach => mach-pnx4008}/clock.h         |    0
 .../include/{mach => mach-pnx4008}/debug-macro.S   |    0
 .../include/{mach => mach-pnx4008}/dma.h           |    0
 .../include/{mach => mach-pnx4008}/entry-macro.S   |    0
 .../include/{mach => mach-pnx4008}/gpio-pnx4008.h  |    0
 .../mach-pnx4008/include/mach-pnx4008/hardware.h   |   32 +
 .../include/{mach => mach-pnx4008}/irq.h           |    0
 .../include/{mach => mach-pnx4008}/irqs.h          |    0
 .../include/{mach => mach-pnx4008}/param.h         |    0
 .../include/{mach => mach-pnx4008}/platform.h      |    0
 .../include/{mach => mach-pnx4008}/pm.h            |    0
 .../include/{mach => mach-pnx4008}/timex.h         |    0
 .../include/{mach => mach-pnx4008}/uncompress.h    |    0
 arch/arm/mach-pnx4008/include/mach/hardware.h      |   32 -
 arch/arm/mach-pnx4008/irq.c                        |    4 +-
 arch/arm/mach-pnx4008/pm.c                         |    6 +-
 arch/arm/mach-pnx4008/serial.c                     |    8 +-
 arch/arm/mach-pnx4008/sleep.S                      |    2 +-
 arch/arm/mach-pnx4008/time.c                       |    2 +-
 arch/arm/mach-pnx4008/time.h                       |    2 +-
 arch/arm/mach-prima2/clock.c                       |    2 +-
 .../include/{mach => mach-prima2}/clkdev.h         |    0
 .../mach-prima2/include/mach-prima2/debug-macro.S  |   29 +
 .../mach-prima2/include/mach-prima2/entry-macro.S  |   22 +
 .../include/{mach => mach-prima2}/gpio.h           |    0
 .../arm/mach-prima2/include/mach-prima2/hardware.h |   15 +
 .../include/{mach => mach-prima2}/irqs.h           |    0
 .../include/{mach => mach-prima2}/map.h            |    0
 .../include/{mach => mach-prima2}/timex.h          |    0
 .../include/{mach => mach-prima2}/uart.h           |    0
 .../mach-prima2/include/mach-prima2/uncompress.h   |   40 +
 arch/arm/mach-prima2/include/mach/debug-macro.S    |   29 -
 arch/arm/mach-prima2/include/mach/entry-macro.S    |   22 -
 arch/arm/mach-prima2/include/mach/hardware.h       |   15 -
 arch/arm/mach-prima2/include/mach/uncompress.h     |   40 -
 arch/arm/mach-prima2/irq.c                         |    2 +-
 arch/arm/mach-prima2/lluart.c                      |    4 +-
 arch/arm/mach-prima2/timer.c                       |    2 +-
 arch/arm/mach-pxa/am200epd.c                       |    6 +-
 arch/arm/mach-pxa/am300epd.c                       |    6 +-
 arch/arm/mach-pxa/balloon3.c                       |   18 +-
 arch/arm/mach-pxa/capc7117.c                       |    4 +-
 arch/arm/mach-pxa/clock-pxa2xx.c                   |    2 +-
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    4 +-
 arch/arm/mach-pxa/cm-x255.c                        |    2 +-
 arch/arm/mach-pxa/cm-x270.c                        |    6 +-
 arch/arm/mach-pxa/cm-x2xx.c                        |   10 +-
 arch/arm/mach-pxa/cm-x300.c                        |   16 +-
 arch/arm/mach-pxa/colibri-evalboard.c              |   12 +-
 arch/arm/mach-pxa/colibri-pxa270-income.c          |   12 +-
 arch/arm/mach-pxa/colibri-pxa270.c                 |    6 +-
 arch/arm/mach-pxa/colibri-pxa300.c                 |   10 +-
 arch/arm/mach-pxa/colibri-pxa320.c                 |   14 +-
 arch/arm/mach-pxa/colibri-pxa3xx.c                 |   14 +-
 arch/arm/mach-pxa/corgi.c                          |   14 +-
 arch/arm/mach-pxa/corgi_pm.c                       |    8 +-
 arch/arm/mach-pxa/cpufreq-pxa2xx.c                 |    4 +-
 arch/arm/mach-pxa/cpufreq-pxa3xx.c                 |    2 +-
 arch/arm/mach-pxa/csb726.c                         |   12 +-
 arch/arm/mach-pxa/devices.c                        |   24 +-
 arch/arm/mach-pxa/em-x270.c                        |   16 +-
 arch/arm/mach-pxa/eseries.c                        |   14 +-
 arch/arm/mach-pxa/ezx.c                            |   12 +-
 arch/arm/mach-pxa/generic.c                        |    8 +-
 arch/arm/mach-pxa/gumstix.c                        |   10 +-
 arch/arm/mach-pxa/h5000.c                          |    8 +-
 arch/arm/mach-pxa/himalaya.c                       |    2 +-
 arch/arm/mach-pxa/hx4700.c                         |    8 +-
 arch/arm/mach-pxa/icontrol.c                       |    4 +-
 arch/arm/mach-pxa/idp.c                            |   12 +-
 .../mach-pxa/include/{mach => mach-pxa}/addr-map.h |    0
 .../include/{mach => mach-pxa}/arcom-pcmcia.h      |    0
 .../mach-pxa/include/{mach => mach-pxa}/audio.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/balloon3.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/bitfield.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/camera.h   |    0
 arch/arm/mach-pxa/include/mach-pxa/colibri.h       |   69 +
 .../mach-pxa/include/{mach => mach-pxa}/corgi.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/csb726.h   |    0
 .../include/{mach => mach-pxa}/debug-macro.S       |    0
 arch/arm/mach-pxa/include/mach-pxa/dma.h           |   21 +
 .../include/{mach => mach-pxa}/eseries-gpio.h      |    0
 .../include/{mach => mach-pxa}/eseries-irq.h       |    0
 arch/arm/mach-pxa/include/mach-pxa/gpio.h          |   32 +
 .../mach-pxa/include/{mach => mach-pxa}/gumstix.h  |    0
 arch/arm/mach-pxa/include/mach-pxa/h5000.h         |  113 ++
 arch/arm/mach-pxa/include/mach-pxa/hardware.h      |  338 ++++
 .../mach-pxa/include/{mach => mach-pxa}/hx4700.h   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/irda.h |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/irqs.h |    0
 .../include/{mach => mach-pxa}/littleton.h         |    0
 .../mach-pxa/include/{mach => mach-pxa}/lpd270.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/lubbock.h  |    0
 arch/arm/mach-pxa/include/mach-pxa/magician.h      |  120 ++
 arch/arm/mach-pxa/include/mach-pxa/mainstone.h     |  141 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa25x.h    |  225 +++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa27x.h    |  468 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa2xx.h    |  142 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa300.h    |  575 +++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa320.h    |  461 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa3xx.h    |  158 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa930.h    |  498 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp.h           |   21 +
 .../mach-pxa/include/{mach => mach-pxa}/mioa701.h  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h |    0
 arch/arm/mach-pxa/include/mach-pxa/mtd-xip.h       |   35 +
 .../mach-pxa/include/{mach => mach-pxa}/mxm8x10.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/ohci.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palm27x.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmasoc.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmld.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmt5.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtc.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmte2.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtreo.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtx.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmz72.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/pata_pxa.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/pcm027.h   |    0
 .../mach-pxa/include/mach-pxa/pcm990_baseboard.h   |  211 +++
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/poodle.h   |    0
 .../include/{mach => mach-pxa}/pxa25x-udc.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa25x.h        |   17 +
 .../include/{mach => mach-pxa}/pxa27x-udc.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa27x.h        |   29 +
 arch/arm/mach-pxa/include/mach-pxa/pxa2xx-regs.h   |  187 +++
 arch/arm/mach-pxa/include/mach-pxa/pxa300.h        |    7 +
 arch/arm/mach-pxa/include/mach-pxa/pxa320.h        |    8 +
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx-regs.h   |  205 +++
 .../include/{mach => mach-pxa}/pxa3xx-u2d.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx.h        |   14 +
 arch/arm/mach-pxa/include/mach-pxa/pxa930.h        |    7 +
 .../include/{mach => mach-pxa}/pxa930_rotary.h     |    0
 .../include/{mach => mach-pxa}/pxa930_trkball.h    |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa95x.h        |    7 +
 arch/arm/mach-pxa/include/mach-pxa/pxafb.h         |  175 ++
 arch/arm/mach-pxa/include/mach-pxa/regs-ac97.h     |  101 ++
 arch/arm/mach-pxa/include/mach-pxa/regs-lcd.h      |  197 +++
 arch/arm/mach-pxa/include/mach-pxa/regs-ost.h      |   34 +
 arch/arm/mach-pxa/include/mach-pxa/regs-rtc.h      |   23 +
 arch/arm/mach-pxa/include/mach-pxa/regs-u2d.h      |  200 +++
 .../include/{mach => mach-pxa}/regs-uart.h         |    0
 .../mach-pxa/include/{mach => mach-pxa}/reset.h    |    0
 .../include/{mach => mach-pxa}/sharpsl_pm.h        |    0
 .../mach-pxa/include/{mach => mach-pxa}/smemc.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/spitz.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/timex.h    |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/tosa.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/tosa_bt.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/trizeps4.h |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h |    0
 .../include/{mach => mach-pxa}/uncompress.h        |    0
 .../mach-pxa/include/{mach => mach-pxa}/viper.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/vpac270.h  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/zeus.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/zylonite.h |    0
 arch/arm/mach-pxa/include/mach/colibri.h           |   69 -
 arch/arm/mach-pxa/include/mach/dma.h               |   21 -
 arch/arm/mach-pxa/include/mach/gpio.h              |   32 -
 arch/arm/mach-pxa/include/mach/h5000.h             |  113 --
 arch/arm/mach-pxa/include/mach/hardware.h          |  338 ----
 arch/arm/mach-pxa/include/mach/magician.h          |  120 --
 arch/arm/mach-pxa/include/mach/mainstone.h         |  141 --
 arch/arm/mach-pxa/include/mach/mfp-pxa25x.h        |  225 ---
 arch/arm/mach-pxa/include/mach/mfp-pxa27x.h        |  468 ------
 arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h        |  142 --
 arch/arm/mach-pxa/include/mach/mfp-pxa300.h        |  575 -------
 arch/arm/mach-pxa/include/mach/mfp-pxa320.h        |  461 ------
 arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h        |  158 --
 arch/arm/mach-pxa/include/mach/mfp-pxa930.h        |  498 ------
 arch/arm/mach-pxa/include/mach/mfp.h               |   21 -
 arch/arm/mach-pxa/include/mach/mtd-xip.h           |   35 -
 arch/arm/mach-pxa/include/mach/pcm990_baseboard.h  |  211 ---
 arch/arm/mach-pxa/include/mach/pxa25x.h            |   17 -
 arch/arm/mach-pxa/include/mach/pxa27x.h            |   29 -
 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h       |  187 ---
 arch/arm/mach-pxa/include/mach/pxa300.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxa320.h            |    8 -
 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h       |  205 ---
 arch/arm/mach-pxa/include/mach/pxa3xx.h            |   14 -
 arch/arm/mach-pxa/include/mach/pxa930.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxa95x.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxafb.h             |  175 --
 arch/arm/mach-pxa/include/mach/regs-ac97.h         |  101 --
 arch/arm/mach-pxa/include/mach/regs-lcd.h          |  197 ---
 arch/arm/mach-pxa/include/mach/regs-ost.h          |   34 -
 arch/arm/mach-pxa/include/mach/regs-rtc.h          |   23 -
 arch/arm/mach-pxa/include/mach/regs-u2d.h          |  200 ---
 arch/arm/mach-pxa/irq.c                            |    4 +-
 arch/arm/mach-pxa/leds-idp.c                       |    6 +-
 arch/arm/mach-pxa/leds-lubbock.c                   |    6 +-
 arch/arm/mach-pxa/leds-mainstone.c                 |    6 +-
 arch/arm/mach-pxa/littleton.c                      |   14 +-
 arch/arm/mach-pxa/lpd270.c                         |   18 +-
 arch/arm/mach-pxa/lubbock.c                        |   20 +-
 arch/arm/mach-pxa/magician.c                       |   14 +-
 arch/arm/mach-pxa/mainstone.c                      |   20 +-
 arch/arm/mach-pxa/mfp-pxa2xx.c                     |    4 +-
 arch/arm/mach-pxa/mfp-pxa3xx.c                     |    6 +-
 arch/arm/mach-pxa/mioa701.c                        |   22 +-
 arch/arm/mach-pxa/mp900.c                          |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                        |   12 +-
 arch/arm/mach-pxa/palm27x.c                        |   16 +-
 arch/arm/mach-pxa/palmld.c                         |   18 +-
 arch/arm/mach-pxa/palmt5.c                         |   20 +-
 arch/arm/mach-pxa/palmtc.c                         |   14 +-
 arch/arm/mach-pxa/palmte2.c                        |   16 +-
 arch/arm/mach-pxa/palmtreo.c                       |   28 +-
 arch/arm/mach-pxa/palmtx.c                         |   20 +-
 arch/arm/mach-pxa/palmz72.c                        |   26 +-
 arch/arm/mach-pxa/pcm027.c                         |    4 +-
 arch/arm/mach-pxa/pcm990-baseboard.c               |   14 +-
 arch/arm/mach-pxa/pm.c                             |    2 +-
 arch/arm/mach-pxa/poodle.c                         |   14 +-
 arch/arm/mach-pxa/pxa25x.c                         |   14 +-
 arch/arm/mach-pxa/pxa27x.c                         |   16 +-
 arch/arm/mach-pxa/pxa2xx.c                         |   10 +-
 arch/arm/mach-pxa/pxa300.c                         |    2 +-
 arch/arm/mach-pxa/pxa320.c                         |    2 +-
 arch/arm/mach-pxa/pxa3xx-ulpi.c                    |    6 +-
 arch/arm/mach-pxa/pxa3xx.c                         |   16 +-
 arch/arm/mach-pxa/pxa930.c                         |    2 +-
 arch/arm/mach-pxa/pxa95x.c                         |   12 +-
 arch/arm/mach-pxa/raumfeld.c                       |   10 +-
 arch/arm/mach-pxa/reset.c                          |    4 +-
 arch/arm/mach-pxa/saar.c                           |    4 +-
 arch/arm/mach-pxa/saarb.c                          |   10 +-
 arch/arm/mach-pxa/sharpsl_pm.c                     |    8 +-
 arch/arm/mach-pxa/sleep.S                          |    6 +-
 arch/arm/mach-pxa/smemc.c                          |    4 +-
 arch/arm/mach-pxa/spitz.c                          |   20 +-
 arch/arm/mach-pxa/spitz_pm.c                       |    8 +-
 arch/arm/mach-pxa/standby.S                        |    4 +-
 arch/arm/mach-pxa/stargate2.c                      |   10 +-
 arch/arm/mach-pxa/tavorevb.c                       |    6 +-
 arch/arm/mach-pxa/tavorevb3.c                      |    2 +-
 arch/arm/mach-pxa/time.c                           |    4 +-
 arch/arm/mach-pxa/tosa-bt.c                        |    2 +-
 arch/arm/mach-pxa/tosa.c                           |   18 +-
 arch/arm/mach-pxa/trizeps4.c                       |   16 +-
 arch/arm/mach-pxa/viper.c                          |   12 +-
 arch/arm/mach-pxa/vpac270.c                        |   18 +-
 arch/arm/mach-pxa/xcep.c                           |    6 +-
 arch/arm/mach-pxa/z2.c                             |   14 +-
 arch/arm/mach-pxa/zeus.c                           |   24 +-
 arch/arm/mach-pxa/zylonite.c                       |   16 +-
 arch/arm/mach-pxa/zylonite_pxa300.c                |    4 +-
 arch/arm/mach-pxa/zylonite_pxa320.c                |    4 +-
 arch/arm/mach-realview/core.c                      |   10 +-
 .../include/{mach => mach-realview}/barriers.h     |    0
 .../mach-realview/include/mach-realview/board-eb.h |   96 ++
 .../include/mach-realview/board-pb1176.h           |   83 +
 .../include/mach-realview/board-pb11mp.h           |   98 ++
 .../include/mach-realview/board-pba8.h             |   73 +
 .../include/mach-realview/board-pbx.h              |  108 ++
 .../mach-realview/include/mach-realview/clkdev.h   |   16 +
 .../include/{mach => mach-realview}/debug-macro.S  |    0
 .../include/mach-realview}/gpio.h                  |    0
 .../include/{mach => mach-realview}/hardware.h     |    0
 .../include/{mach => mach-realview}/irqs-eb.h      |    0
 .../include/{mach => mach-realview}/irqs-pb1176.h  |    0
 .../include/{mach => mach-realview}/irqs-pb11mp.h  |    0
 .../include/{mach => mach-realview}/irqs-pba8.h    |    0
 .../include/{mach => mach-realview}/irqs-pbx.h     |    0
 .../arm/mach-realview/include/mach-realview/irqs.h |   40 +
 .../include/{mach => mach-realview}/memory.h       |    0
 .../include/{mach => mach-realview}/platform.h     |    0
 .../include/{mach => mach-realview}/timex.h        |    0
 .../include/mach-realview/uncompress.h             |   78 +
 arch/arm/mach-realview/include/mach/board-eb.h     |   96 --
 arch/arm/mach-realview/include/mach/board-pb1176.h |   83 -
 arch/arm/mach-realview/include/mach/board-pb11mp.h |   98 --
 arch/arm/mach-realview/include/mach/board-pba8.h   |   73 -
 arch/arm/mach-realview/include/mach/board-pbx.h    |  108 --
 arch/arm/mach-realview/include/mach/clkdev.h       |   16 -
 arch/arm/mach-realview/include/mach/irqs.h         |   40 -
 arch/arm/mach-realview/include/mach/uncompress.h   |   78 -
 arch/arm/mach-realview/platsmp.c                   |    8 +-
 arch/arm/mach-realview/realview_eb.c               |    6 +-
 arch/arm/mach-realview/realview_pb1176.c           |    6 +-
 arch/arm/mach-realview/realview_pb11mp.c           |    6 +-
 arch/arm/mach-realview/realview_pba8.c             |    6 +-
 arch/arm/mach-realview/realview_pbx.c              |    6 +-
 arch/arm/mach-rpc/dma.c                            |    2 +-
 arch/arm/mach-rpc/ecard.c                          |    2 +-
 arch/arm/mach-rpc/fiq.S                            |    4 +-
 .../mach-rpc/include/{mach => mach-rpc}/acornfb.h  |    0
 .../include/{mach => mach-rpc}/debug-macro.S       |    0
 arch/arm/mach-rpc/include/mach-rpc/entry-macro.S   |   12 +
 arch/arm/mach-rpc/include/mach-rpc/hardware.h      |   76 +
 arch/arm/mach-rpc/include/mach-rpc/io.h            |   31 +
 .../arm/mach-rpc/include/{mach => mach-rpc}/irqs.h |    0
 .../mach-rpc/include/{mach => mach-rpc}/isa-dma.h  |    0
 .../mach-rpc/include/{mach => mach-rpc}/memory.h   |    0
 .../mach-rpc/include/{mach => mach-rpc}/timex.h    |    0
 arch/arm/mach-rpc/include/mach-rpc/uncompress.h    |  196 +++
 arch/arm/mach-rpc/include/mach/entry-macro.S       |   12 -
 arch/arm/mach-rpc/include/mach/hardware.h          |   76 -
 arch/arm/mach-rpc/include/mach/io.h                |   31 -
 arch/arm/mach-rpc/include/mach/uncompress.h        |  196 ---
 arch/arm/mach-rpc/riscpc.c                         |    2 +-
 arch/arm/mach-rpc/time.c                           |    2 +-
 arch/arm/mach-s3c2410/cpu-freq.c                   |    8 +-
 arch/arm/mach-s3c2410/pll.c                        |    4 +-
 arch/arm/mach-s3c2412/cpu-freq.c                   |   10 +-
 arch/arm/mach-s3c2412/gpio.c                       |    6 +-
 arch/arm/mach-s3c2440/dsc.c                        |   10 +-
 arch/arm/mach-s3c2440/s3c2440-cpufreq.c            |   10 +-
 arch/arm/mach-s3c2440/s3c2440-pll-12000000.c       |    4 +-
 arch/arm/mach-s3c2440/s3c2440-pll-16934400.c       |    4 +-
 arch/arm/mach-s3c24xx/bast-ide.c                   |    6 +-
 arch/arm/mach-s3c24xx/bast-irq.c                   |   10 +-
 arch/arm/mach-s3c24xx/clock-s3c2412.c              |   14 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |   16 +-
 arch/arm/mach-s3c24xx/clock-s3c2440.c              |   10 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |   14 +-
 arch/arm/mach-s3c24xx/clock-s3c244x.c              |    8 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c             |   10 +-
 arch/arm/mach-s3c24xx/common-smdk.c                |   16 +-
 arch/arm/mach-s3c24xx/common.c                     |   30 +-
 arch/arm/mach-s3c24xx/dma-s3c2410.c                |   30 +-
 arch/arm/mach-s3c24xx/dma-s3c2412.c                |   28 +-
 arch/arm/mach-s3c24xx/dma-s3c2440.c                |   26 +-
 arch/arm/mach-s3c24xx/dma-s3c2443.c                |   24 +-
 arch/arm/mach-s3c24xx/h1940-bluetooth.c            |    8 +-
 .../include/{mach => mach-s3c24xx}/anubis-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/anubis-irq.h    |    0
 .../include/{mach => mach-s3c24xx}/anubis-map.h    |    0
 .../include/{mach => mach-s3c24xx}/bast-cpld.h     |    0
 .../include/{mach => mach-s3c24xx}/bast-irq.h      |    0
 .../include/{mach => mach-s3c24xx}/bast-map.h      |    0
 .../include/mach-s3c24xx/debug-macro.S             |  101 ++
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/dma.h   |  214 +++
 .../include/mach-s3c24xx/entry-macro.S             |   70 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/fb.h    |    1 +
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-fns.h   |    1 +
 .../include/{mach => mach-s3c24xx}/gpio-nrs.h      |    0
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-track.h |   33 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio.h  |   35 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gta02.h |   15 +
 .../include/{mach => mach-s3c24xx}/h1940-latch.h   |    0
 .../include/{mach => mach-s3c24xx}/h1940.h         |    0
 .../mach-s3c24xx/include/mach-s3c24xx/hardware.h   |   42 +
 .../include/{mach => mach-s3c24xx}/idle.h          |    0
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/io.h    |  211 +++
 .../include/{mach => mach-s3c24xx}/irqs.h          |    0
 .../include/{mach => mach-s3c24xx}/leds-gpio.h     |    0
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/map.h   |  170 ++
 .../include/{mach => mach-s3c24xx}/osiris-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/osiris-map.h    |    0
 .../include/{mach => mach-s3c24xx}/otom-map.h      |    0
 .../include/{mach => mach-s3c24xx}/pm-core.h       |    0
 .../include/{mach => mach-s3c24xx}/regs-clock.h    |    0
 .../include/{mach => mach-s3c24xx}/regs-dsc.h      |    0
 .../mach-s3c24xx/include/mach-s3c24xx/regs-gpio.h  |  615 +++++++
 .../include/{mach => mach-s3c24xx}/regs-irq.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-lcd.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-power.h    |    0
 .../{mach => mach-s3c24xx}/regs-s3c2412-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-s3c2412.h  |    0
 .../{mach => mach-s3c24xx}/regs-s3c2416-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-s3c2416.h  |    0
 .../{mach => mach-s3c24xx}/regs-s3c2443-clock.h    |    0
 .../include/{mach => mach-s3c24xx}/regs-sdi.h      |    0
 .../include/{mach => mach-s3c24xx}/tick.h          |    0
 .../include/{mach => mach-s3c24xx}/timex.h         |    0
 .../mach-s3c24xx/include/mach-s3c24xx/uncompress.h |   54 +
 .../include/{mach => mach-s3c24xx}/vr1000-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/vr1000-irq.h    |    0
 .../mach-s3c24xx/include/mach-s3c24xx/vr1000-map.h |  110 ++
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S   |  101 --
 arch/arm/mach-s3c24xx/include/mach/dma.h           |  214 ---
 arch/arm/mach-s3c24xx/include/mach/entry-macro.S   |   70 -
 arch/arm/mach-s3c24xx/include/mach/fb.h            |    1 -
 arch/arm/mach-s3c24xx/include/mach/gpio-fns.h      |    1 -
 arch/arm/mach-s3c24xx/include/mach/gpio-track.h    |   33 -
 arch/arm/mach-s3c24xx/include/mach/gpio.h          |   35 -
 arch/arm/mach-s3c24xx/include/mach/gta02.h         |   15 -
 arch/arm/mach-s3c24xx/include/mach/hardware.h      |   42 -
 arch/arm/mach-s3c24xx/include/mach/io.h            |  211 ---
 arch/arm/mach-s3c24xx/include/mach/map.h           |  170 --
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h     |  615 -------
 arch/arm/mach-s3c24xx/include/mach/uncompress.h    |   54 -
 arch/arm/mach-s3c24xx/include/mach/vr1000-map.h    |  110 --
 arch/arm/mach-s3c24xx/irq-pm.c                     |    6 +-
 arch/arm/mach-s3c24xx/irq-s3c2412.c                |   14 +-
 arch/arm/mach-s3c24xx/irq-s3c2416.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c2440.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c2443.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c244x.c                |   12 +-
 arch/arm/mach-s3c24xx/mach-amlm5900.c              |   18 +-
 arch/arm/mach-s3c24xx/mach-anubis.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-at2440evb.c             |   24 +-
 arch/arm/mach-s3c24xx/mach-bast.c                  |   36 +-
 arch/arm/mach-s3c24xx/mach-gta02.c                 |   38 +-
 arch/arm/mach-s3c24xx/mach-h1940.c                 |   46 +-
 arch/arm/mach-s3c24xx/mach-jive.c                  |   30 +-
 arch/arm/mach-s3c24xx/mach-mini2440.c              |   32 +-
 arch/arm/mach-s3c24xx/mach-n30.c                   |   26 +-
 arch/arm/mach-s3c24xx/mach-nexcoder.c              |   22 +-
 arch/arm/mach-s3c24xx/mach-osiris-dvs.c            |    2 +-
 arch/arm/mach-s3c24xx/mach-osiris.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-otom.c                  |   18 +-
 arch/arm/mach-s3c24xx/mach-qt2410.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-rx1950.c                |   34 +-
 arch/arm/mach-s3c24xx/mach-rx3715.c                |   22 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c              |   12 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c              |   34 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |   42 +-
 arch/arm/mach-s3c24xx/mach-smdk2440.c              |   26 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |   26 +-
 arch/arm/mach-s3c24xx/mach-tct_hammer.c            |   10 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c                |   26 +-
 arch/arm/mach-s3c24xx/mach-vstms.c                 |   26 +-
 arch/arm/mach-s3c24xx/pm-h1940.S                   |    6 +-
 arch/arm/mach-s3c24xx/pm-s3c2410.c                 |   10 +-
 arch/arm/mach-s3c24xx/pm-s3c2412.c                 |   14 +-
 arch/arm/mach-s3c24xx/pm-s3c2416.c                 |    8 +-
 arch/arm/mach-s3c24xx/pm.c                         |   14 +-
 arch/arm/mach-s3c24xx/s3c2410.c                    |   28 +-
 arch/arm/mach-s3c24xx/s3c2412.c                    |   36 +-
 arch/arm/mach-s3c24xx/s3c2416.c                    |   34 +-
 arch/arm/mach-s3c24xx/s3c2440.c                    |   16 +-
 arch/arm/mach-s3c24xx/s3c2442.c                    |   18 +-
 arch/arm/mach-s3c24xx/s3c2443.c                    |   26 +-
 arch/arm/mach-s3c24xx/s3c244x.c                    |   34 +-
 arch/arm/mach-s3c24xx/setup-i2c.c                  |    8 +-
 arch/arm/mach-s3c24xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                  |    6 +-
 arch/arm/mach-s3c24xx/setup-ts.c                   |    2 +-
 arch/arm/mach-s3c24xx/simtec-audio.c               |   14 +-
 arch/arm/mach-s3c24xx/simtec-nor.c                 |    6 +-
 arch/arm/mach-s3c24xx/simtec-pm.c                  |   10 +-
 arch/arm/mach-s3c24xx/simtec-usb.c                 |   10 +-
 arch/arm/mach-s3c24xx/sleep-s3c2410.S              |   12 +-
 arch/arm/mach-s3c24xx/sleep-s3c2412.S              |    6 +-
 arch/arm/mach-s3c24xx/sleep.S                      |   12 +-
 arch/arm/mach-s3c64xx/clock.c                      |   24 +-
 arch/arm/mach-s3c64xx/common.c                     |   28 +-
 arch/arm/mach-s3c64xx/cpuidle.c                    |    6 +-
 arch/arm/mach-s3c64xx/dev-audio.c                  |   12 +-
 arch/arm/mach-s3c64xx/dev-uart.c                   |    6 +-
 arch/arm/mach-s3c64xx/dma.c                        |    8 +-
 .../include/{mach => mach-s3c64xx}/crag6410.h      |    0
 .../include/mach-s3c64xx/debug-macro.S             |   38 +
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/dma.h   |  132 ++
 .../include/{mach => mach-s3c64xx}/gpio.h          |    0
 .../include/{mach => mach-s3c64xx}/hardware.h      |    0
 .../include/{mach => mach-s3c64xx}/irqs.h          |    0
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/map.h   |  125 ++
 .../mach-s3c64xx/include/mach-s3c64xx/pm-core.h    |  119 ++
 .../include/{mach => mach-s3c64xx}/regs-clock.h    |    0
 .../{mach => mach-s3c64xx}/regs-gpio-memport.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-gpio.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-irq.h      |    0
 .../include/{mach => mach-s3c64xx}/regs-modem.h    |    0
 .../include/{mach => mach-s3c64xx}/regs-srom.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-sys.h      |    0
 .../{mach => mach-s3c64xx}/regs-syscon-power.h     |    0
 .../include/{mach => mach-s3c64xx}/tick.h          |    0
 .../include/{mach => mach-s3c64xx}/timex.h         |    0
 .../mach-s3c64xx/include/mach-s3c64xx/uncompress.h |   28 +
 arch/arm/mach-s3c64xx/include/mach/debug-macro.S   |   38 -
 arch/arm/mach-s3c64xx/include/mach/dma.h           |  132 --
 arch/arm/mach-s3c64xx/include/mach/map.h           |  125 --
 arch/arm/mach-s3c64xx/include/mach/pm-core.h       |  119 --
 arch/arm/mach-s3c64xx/include/mach/uncompress.h    |   28 -
 arch/arm/mach-s3c64xx/irq-pm.c                     |   12 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |   22 +-
 arch/arm/mach-s3c64xx/mach-crag6410-module.c       |    4 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |   48 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |   20 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |   26 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |   18 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |   26 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |   28 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |   16 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |   16 +-
 arch/arm/mach-s3c64xx/mach-smdk6400.c              |   14 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |   40 +-
 arch/arm/mach-s3c64xx/pm.c                         |   26 +-
 arch/arm/mach-s3c64xx/s3c6400.c                    |   20 +-
 arch/arm/mach-s3c64xx/s3c6410.c                    |   26 +-
 arch/arm/mach-s3c64xx/setup-fb-24bpp.c             |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-ide.c                  |    8 +-
 arch/arm/mach-s3c64xx/setup-keypad.c               |    4 +-
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c64xx/setup-spi.c                  |    2 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   10 +-
 arch/arm/mach-s3c64xx/sleep.S                      |    4 +-
 arch/arm/mach-s5p64x0/clock-s5p6440.c              |   22 +-
 arch/arm/mach-s5p64x0/clock-s5p6450.c              |   22 +-
 arch/arm/mach-s5p64x0/clock.c                      |   20 +-
 arch/arm/mach-s5p64x0/common.c                     |   32 +-
 arch/arm/mach-s5p64x0/dev-audio.c                  |   10 +-
 arch/arm/mach-s5p64x0/dma.c                        |   14 +-
 arch/arm/mach-s5p64x0/gpiolib.c                    |   16 +-
 .../include/mach-s5p64x0/debug-macro.S             |   33 +
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/dma.h   |   26 +
 .../include/{mach => mach-s5p64x0}/gpio.h          |    0
 .../include/{mach => mach-s5p64x0}/hardware.h      |    0
 .../include/{mach => mach-s5p64x0}/i2c.h           |    0
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/irqs.h  |  150 ++
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/map.h   |   95 ++
 .../mach-s5p64x0/include/mach-s5p64x0/pm-core.h    |  117 ++
 .../mach-s5p64x0/include/mach-s5p64x0/regs-clock.h |   98 ++
 .../mach-s5p64x0/include/mach-s5p64x0/regs-gpio.h  |   68 +
 .../mach-s5p64x0/include/mach-s5p64x0/regs-irq.h   |   19 +
 .../include/{mach => mach-s5p64x0}/s5p64x0-clock.h |    0
 .../include/{mach => mach-s5p64x0}/tick.h          |    0
 .../include/{mach => mach-s5p64x0}/timex.h         |    0
 .../mach-s5p64x0/include/mach-s5p64x0/uncompress.h |  212 +++
 arch/arm/mach-s5p64x0/include/mach/debug-macro.S   |   33 -
 arch/arm/mach-s5p64x0/include/mach/dma.h           |   26 -
 arch/arm/mach-s5p64x0/include/mach/irqs.h          |  150 --
 arch/arm/mach-s5p64x0/include/mach/map.h           |   95 --
 arch/arm/mach-s5p64x0/include/mach/pm-core.h       |  117 --
 arch/arm/mach-s5p64x0/include/mach/regs-clock.h    |   98 --
 arch/arm/mach-s5p64x0/include/mach/regs-gpio.h     |   68 -
 arch/arm/mach-s5p64x0/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5p64x0/include/mach/uncompress.h    |  212 ---
 arch/arm/mach-s5p64x0/irq-pm.c                     |    6 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |   40 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |   40 +-
 arch/arm/mach-s5p64x0/pm.c                         |   12 +-
 arch/arm/mach-s5p64x0/setup-fb-24bpp.c             |    6 +-
 arch/arm/mach-s5p64x0/setup-i2c0.c                 |    6 +-
 arch/arm/mach-s5p64x0/setup-i2c1.c                 |    6 +-
 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c           |   10 +-
 arch/arm/mach-s5p64x0/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pc100/clock.c                      |   18 +-
 arch/arm/mach-s5pc100/common.c                     |   30 +-
 arch/arm/mach-s5pc100/dev-audio.c                  |   10 +-
 arch/arm/mach-s5pc100/dma.c                        |   10 +-
 .../include/mach-s5pc100/debug-macro.S             |   39 +
 arch/arm/mach-s5pc100/include/mach-s5pc100/dma.h   |   26 +
 .../include/{mach => mach-s5pc100}/entry-macro.S   |    0
 .../include/{mach => mach-s5pc100}/gpio.h          |    0
 .../include/{mach => mach-s5pc100}/hardware.h      |    0
 arch/arm/mach-s5pc100/include/mach-s5pc100/irqs.h  |  117 ++
 arch/arm/mach-s5pc100/include/mach-s5pc100/map.h   |  136 ++
 .../mach-s5pc100/include/mach-s5pc100/regs-clock.h |   80 +
 .../mach-s5pc100/include/mach-s5pc100/regs-gpio.h  |   38 +
 .../mach-s5pc100/include/mach-s5pc100/regs-irq.h   |   19 +
 .../include/{mach => mach-s5pc100}/tick.h          |    0
 .../include/{mach => mach-s5pc100}/timex.h         |    0
 .../mach-s5pc100/include/mach-s5pc100/uncompress.h |   28 +
 arch/arm/mach-s5pc100/include/mach/debug-macro.S   |   39 -
 arch/arm/mach-s5pc100/include/mach/dma.h           |   26 -
 arch/arm/mach-s5pc100/include/mach/irqs.h          |  117 --
 arch/arm/mach-s5pc100/include/mach/map.h           |  136 --
 arch/arm/mach-s5pc100/include/mach/regs-clock.h    |   80 -
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h     |   38 -
 arch/arm/mach-s5pc100/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5pc100/include/mach/uncompress.h    |   28 -
 arch/arm/mach-s5pc100/mach-smdkc100.c              |   34 +-
 arch/arm/mach-s5pc100/setup-fb-24bpp.c             |    6 +-
 arch/arm/mach-s5pc100/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-ide.c                  |    4 +-
 arch/arm/mach-s5pc100/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c           |    6 +-
 arch/arm/mach-s5pc100/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/clock.c                      |   18 +-
 arch/arm/mach-s5pv210/common.c                     |   30 +-
 arch/arm/mach-s5pv210/dev-audio.c                  |   12 +-
 arch/arm/mach-s5pv210/dma.c                        |   10 +-
 .../include/mach-s5pv210/debug-macro.S             |   41 +
 arch/arm/mach-s5pv210/include/mach-s5pv210/dma.h   |   26 +
 .../include/{mach => mach-s5pv210}/gpio.h          |    0
 .../include/{mach => mach-s5pv210}/hardware.h      |    0
 arch/arm/mach-s5pv210/include/mach-s5pv210/irqs.h  |  139 ++
 arch/arm/mach-s5pv210/include/mach-s5pv210/map.h   |  157 ++
 .../include/{mach => mach-s5pv210}/memory.h        |    0
 .../include/{mach => mach-s5pv210}/pm-core.h       |    0
 .../include/{mach => mach-s5pv210}/regs-audss.h    |    0
 .../mach-s5pv210/include/mach-s5pv210/regs-clock.h |  206 +++
 .../mach-s5pv210/include/mach-s5pv210/regs-gpio.h  |   41 +
 .../mach-s5pv210/include/mach-s5pv210/regs-irq.h   |   19 +
 .../include/{mach => mach-s5pv210}/regs-sys.h      |    0
 .../include/{mach => mach-s5pv210}/tick.h          |    0
 .../include/{mach => mach-s5pv210}/timex.h         |    0
 .../mach-s5pv210/include/mach-s5pv210/uncompress.h |   24 +
 arch/arm/mach-s5pv210/include/mach/debug-macro.S   |   41 -
 arch/arm/mach-s5pv210/include/mach/dma.h           |   26 -
 arch/arm/mach-s5pv210/include/mach/irqs.h          |  139 --
 arch/arm/mach-s5pv210/include/mach/map.h           |  157 --
 arch/arm/mach-s5pv210/include/mach/regs-clock.h    |  206 ---
 arch/arm/mach-s5pv210/include/mach/regs-gpio.h     |   41 -
 arch/arm/mach-s5pv210/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5pv210/include/mach/uncompress.h    |   24 -
 arch/arm/mach-s5pv210/mach-aquila.c                |   24 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |   32 +-
 arch/arm/mach-s5pv210/mach-smdkc110.c              |   22 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |   40 +-
 arch/arm/mach-s5pv210/mach-torbreck.c              |   16 +-
 arch/arm/mach-s5pv210/pm.c                         |   10 +-
 arch/arm/mach-s5pv210/setup-fb-24bpp.c             |    8 +-
 arch/arm/mach-s5pv210/setup-fimc.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c2.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-ide.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c           |    6 +-
 arch/arm/mach-s5pv210/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-usb-phy.c              |   10 +-
 arch/arm/mach-sa1100/assabet.c                     |    8 +-
 arch/arm/mach-sa1100/badge4.c                      |    6 +-
 arch/arm/mach-sa1100/cerf.c                        |    8 +-
 arch/arm/mach-sa1100/clock.c                       |    2 +-
 arch/arm/mach-sa1100/collie.c                      |    8 +-
 arch/arm/mach-sa1100/cpu-sa1100.c                  |    2 +-
 arch/arm/mach-sa1100/cpu-sa1110.c                  |    2 +-
 arch/arm/mach-sa1100/generic.c                     |    4 +-
 arch/arm/mach-sa1100/h3100.c                       |    4 +-
 arch/arm/mach-sa1100/h3600.c                       |    4 +-
 arch/arm/mach-sa1100/h3xxx.c                       |    2 +-
 arch/arm/mach-sa1100/hackkit.c                     |    4 +-
 .../include/{mach => mach-sa1100}/SA-1100.h        |    0
 arch/arm/mach-sa1100/include/mach-sa1100/SA-1101.h |  925 +++++++++++
 .../include/{mach => mach-sa1100}/SA-1111.h        |    0
 .../include/{mach => mach-sa1100}/assabet.h        |    0
 arch/arm/mach-sa1100/include/mach-sa1100/badge4.h  |   75 +
 .../include/{mach => mach-sa1100}/bitfield.h       |    0
 .../include/{mach => mach-sa1100}/cerf.h           |    0
 .../include/{mach => mach-sa1100}/collie.h         |    0
 .../mach-sa1100/include/mach-sa1100/debug-macro.S  |   62 +
 .../include/{mach => mach-sa1100}/entry-macro.S    |    0
 arch/arm/mach-sa1100/include/mach-sa1100/gpio.h    |   55 +
 .../include/{mach => mach-sa1100}/h3xxx.h          |    0
 .../include/{mach => mach-sa1100}/hardware.h       |    0
 .../include/{mach => mach-sa1100}/irqs.h           |    0
 .../include/{mach => mach-sa1100}/jornada720.h     |    0
 .../include/{mach => mach-sa1100}/lart.h           |    0
 .../include/{mach => mach-sa1100}/mcp.h            |    0
 .../include/{mach => mach-sa1100}/memory.h         |    0
 arch/arm/mach-sa1100/include/mach-sa1100/mtd-xip.h |   26 +
 .../mach-sa1100/include/mach-sa1100/nanoengine.h   |   52 +
 .../include/{mach => mach-sa1100}/neponset.h       |    0
 .../include/{mach => mach-sa1100}/reset.h          |    0
 .../include/{mach => mach-sa1100}/shannon.h        |    0
 .../include/{mach => mach-sa1100}/simpad.h         |    0
 .../include/{mach => mach-sa1100}/timex.h          |    0
 .../include/{mach => mach-sa1100}/uncompress.h     |    0
 arch/arm/mach-sa1100/include/mach/SA-1101.h        |  925 -----------
 arch/arm/mach-sa1100/include/mach/badge4.h         |   75 -
 arch/arm/mach-sa1100/include/mach/debug-macro.S    |   62 -
 arch/arm/mach-sa1100/include/mach/gpio.h           |   55 -
 arch/arm/mach-sa1100/include/mach/mtd-xip.h        |   26 -
 arch/arm/mach-sa1100/include/mach/nanoengine.h     |   52 -
 arch/arm/mach-sa1100/irq.c                         |    4 +-
 arch/arm/mach-sa1100/jornada720.c                  |    4 +-
 arch/arm/mach-sa1100/jornada720_ssp.c              |    4 +-
 arch/arm/mach-sa1100/lart.c                        |    6 +-
 arch/arm/mach-sa1100/leds-assabet.c                |    4 +-
 arch/arm/mach-sa1100/leds-badge4.c                 |    2 +-
 arch/arm/mach-sa1100/leds-cerf.c                   |    2 +-
 arch/arm/mach-sa1100/leds-hackkit.c                |    2 +-
 arch/arm/mach-sa1100/leds-lart.c                   |    2 +-
 arch/arm/mach-sa1100/nanoengine.c                  |    6 +-
 arch/arm/mach-sa1100/neponset.c                    |    8 +-
 arch/arm/mach-sa1100/pci-nanoengine.c              |    4 +-
 arch/arm/mach-sa1100/pleb.c                        |    4 +-
 arch/arm/mach-sa1100/pm.c                          |    2 +-
 arch/arm/mach-sa1100/shannon.c                     |    8 +-
 arch/arm/mach-sa1100/simpad.c                      |    8 +-
 arch/arm/mach-sa1100/sleep.S                       |    2 +-
 arch/arm/mach-sa1100/ssp.c                         |    4 +-
 arch/arm/mach-sa1100/time.c                        |    4 +-
 .../include/{mach => mach-shark}/debug-macro.S     |    0
 .../include/{mach => mach-shark}/entry-macro.S     |    0
 .../include/{mach => mach-shark}/framebuffer.h     |    0
 .../include/{mach => mach-shark}/hardware.h        |    0
 .../mach-shark/include/{mach => mach-shark}/io.h   |    0
 .../mach-shark/include/{mach => mach-shark}/irqs.h |    0
 .../include/{mach => mach-shark}/isa-dma.h         |    0
 .../include/{mach => mach-shark}/memory.h          |    0
 .../include/{mach => mach-shark}/timex.h           |    0
 .../include/{mach => mach-shark}/uncompress.h      |    0
 arch/arm/mach-shmobile/board-ag5evm.c              |    8 +-
 arch/arm/mach-shmobile/board-ap4evb.c              |    6 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c     |    6 +-
 arch/arm/mach-shmobile/board-bonito.c              |    6 +-
 arch/arm/mach-shmobile/board-g3evm.c               |    6 +-
 arch/arm/mach-shmobile/board-g4evm.c               |    6 +-
 arch/arm/mach-shmobile/board-kota2.c               |    8 +-
 arch/arm/mach-shmobile/board-kzm9d.c               |    4 +-
 arch/arm/mach-shmobile/board-kzm9g.c               |    6 +-
 arch/arm/mach-shmobile/board-mackerel.c            |    6 +-
 arch/arm/mach-shmobile/board-marzen.c              |    8 +-
 arch/arm/mach-shmobile/clock-emev2.c               |    2 +-
 arch/arm/mach-shmobile/clock-r8a7740.c             |    4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |    2 +-
 arch/arm/mach-shmobile/clock-sh7367.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7372.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7377.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh73a0.c              |    2 +-
 arch/arm/mach-shmobile/common.c                    |    2 +-
 arch/arm/mach-shmobile/console.c                   |    2 +-
 arch/arm/mach-shmobile/hotplug.c                   |    2 +-
 .../include/{mach => mach-shmobile}/clkdev.h       |    0
 .../include/{mach => mach-shmobile}/common.h       |    0
 .../include/{mach => mach-shmobile}/dma-register.h |    0
 .../include/{mach => mach-shmobile}/dma.h          |    0
 .../include/{mach => mach-shmobile}/emev2.h        |    0
 .../include/{mach => mach-shmobile}/gpio.h         |    0
 .../include/{mach => mach-shmobile}/hardware.h     |    0
 .../{mach => mach-shmobile}/head-ap4evb.txt        |    0
 .../{mach => mach-shmobile}/head-mackerel.txt      |    0
 .../include/{mach => mach-shmobile}/intc.h         |    0
 .../include/{mach => mach-shmobile}/irqs.h         |    0
 .../include/{mach => mach-shmobile}/memory.h       |    0
 .../include/{mach => mach-shmobile}/mmc-ap4eb.h    |    0
 .../include/{mach => mach-shmobile}/mmc-mackerel.h |    0
 .../include/{mach => mach-shmobile}/mmc.h          |    0
 .../include/{mach => mach-shmobile}/pm-rmobile.h   |    0
 .../mach-shmobile/include/mach-shmobile/r8a7740.h  |  615 +++++++
 .../include/{mach => mach-shmobile}/r8a7779.h      |    0
 .../include/{mach => mach-shmobile}/sdhi-sh7372.h  |    0
 .../include/{mach => mach-shmobile}/sdhi.h         |    0
 .../include/{mach => mach-shmobile}/sh7367.h       |    0
 .../mach-shmobile/include/mach-shmobile/sh7372.h   |  498 ++++++
 .../include/{mach => mach-shmobile}/sh7377.h       |    0
 .../include/{mach => mach-shmobile}/sh73a0.h       |    0
 .../include/{mach => mach-shmobile}/system.h       |    0
 .../include/{mach => mach-shmobile}/timex.h        |    0
 .../include/{mach => mach-shmobile}/uncompress.h   |    0
 .../mach-shmobile/include/mach-shmobile/zboot.h    |   23 +
 .../include/{mach => mach-shmobile}/zboot_macros.h |    0
 arch/arm/mach-shmobile/include/mach/r8a7740.h      |  615 -------
 arch/arm/mach-shmobile/include/mach/sh7372.h       |  498 ------
 arch/arm/mach-shmobile/include/mach/zboot.h        |   23 -
 arch/arm/mach-shmobile/intc-r8a7740.c              |    4 +-
 arch/arm/mach-shmobile/intc-r8a7779.c              |    6 +-
 arch/arm/mach-shmobile/intc-sh7367.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7372.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7377.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh73a0.c               |    6 +-
 arch/arm/mach-shmobile/pfc-r8a7740.c               |    4 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c               |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c                |    4 +-
 arch/arm/mach-shmobile/pfc-sh7377.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c                |    4 +-
 arch/arm/mach-shmobile/platsmp.c                   |    4 +-
 arch/arm/mach-shmobile/pm-r8a7740.c                |    2 +-
 arch/arm/mach-shmobile/pm-r8a7779.c                |    4 +-
 arch/arm/mach-shmobile/pm-rmobile.c                |    2 +-
 arch/arm/mach-shmobile/pm-sh7372.c                 |    6 +-
 arch/arm/mach-shmobile/setup-emev2.c               |    8 +-
 arch/arm/mach-shmobile/setup-r8a7740.c             |   10 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |    8 +-
 arch/arm/mach-shmobile/setup-sh7367.c              |    6 +-
 arch/arm/mach-shmobile/setup-sh7372.c              |   10 +-
 arch/arm/mach-shmobile/setup-sh7377.c              |    6 +-
 arch/arm/mach-shmobile/setup-sh73a0.c              |   10 +-
 arch/arm/mach-shmobile/smp-emev2.c                 |    4 +-
 arch/arm/mach-shmobile/smp-r8a7779.c               |    4 +-
 arch/arm/mach-shmobile/smp-sh73a0.c                |    2 +-
 .../include/{mach => mach-socfpga}/debug-macro.S   |    0
 .../include/{mach => mach-socfpga}/timex.h         |    0
 .../include/{mach => mach-socfpga}/uncompress.h    |    0
 .../include/mach-spear13xx/debug-macro.S           |   14 +
 .../include/{mach => mach-spear13xx}/dma.h         |    0
 .../include/{mach => mach-spear13xx}/generic.h     |    0
 .../mach-spear13xx/include/mach-spear13xx/gpio.h   |   19 +
 .../include/{mach => mach-spear13xx}/hardware.h    |    0
 .../include/{mach => mach-spear13xx}/irqs.h        |    0
 .../include/{mach => mach-spear13xx}/spear.h       |    0
 .../{mach => mach-spear13xx}/spear1310_misc_regs.h |    0
 .../{mach => mach-spear13xx}/spear1340_misc_regs.h |    0
 .../mach-spear13xx/include/mach-spear13xx/timex.h  |   19 +
 .../include/mach-spear13xx/uncompress.h            |   19 +
 arch/arm/mach-spear13xx/include/mach/debug-macro.S |   14 -
 arch/arm/mach-spear13xx/include/mach/gpio.h        |   19 -
 arch/arm/mach-spear13xx/include/mach/timex.h       |   19 -
 arch/arm/mach-spear13xx/include/mach/uncompress.h  |   19 -
 arch/arm/mach-spear13xx/platsmp.c                  |    2 +-
 arch/arm/mach-spear13xx/spear1310.c                |    4 +-
 arch/arm/mach-spear13xx/spear1340.c                |    6 +-
 arch/arm/mach-spear13xx/spear13xx.c                |    6 +-
 .../include/mach-spear3xx/debug-macro.S            |   14 +
 .../include/{mach => mach-spear3xx}/generic.h      |    0
 .../arm/mach-spear3xx/include/mach-spear3xx/gpio.h |   19 +
 .../include/{mach => mach-spear3xx}/hardware.h     |    0
 .../include/{mach => mach-spear3xx}/irqs.h         |    0
 .../include/mach-spear3xx/misc_regs.h              |   22 +
 .../include/{mach => mach-spear3xx}/spear.h        |    0
 .../mach-spear3xx/include/mach-spear3xx/timex.h    |   19 +
 .../include/mach-spear3xx/uncompress.h             |   19 +
 arch/arm/mach-spear3xx/include/mach/debug-macro.S  |   14 -
 arch/arm/mach-spear3xx/include/mach/gpio.h         |   19 -
 arch/arm/mach-spear3xx/include/mach/misc_regs.h    |   22 -
 arch/arm/mach-spear3xx/include/mach/timex.h        |   19 -
 arch/arm/mach-spear3xx/include/mach/uncompress.h   |   19 -
 arch/arm/mach-spear3xx/spear300.c                  |    6 +-
 arch/arm/mach-spear3xx/spear310.c                  |    6 +-
 arch/arm/mach-spear3xx/spear320.c                  |    6 +-
 arch/arm/mach-spear3xx/spear3xx.c                  |    6 +-
 .../include/mach-spear6xx/debug-macro.S            |   14 +
 .../include/{mach => mach-spear6xx}/generic.h      |    0
 .../arm/mach-spear6xx/include/mach-spear6xx/gpio.h |   19 +
 .../include/{mach => mach-spear6xx}/hardware.h     |    0
 .../include/{mach => mach-spear6xx}/irqs.h         |    0
 .../include/mach-spear6xx/misc_regs.h              |   22 +
 .../include/{mach => mach-spear6xx}/spear.h        |    0
 .../mach-spear6xx/include/mach-spear6xx/timex.h    |   19 +
 .../include/mach-spear6xx/uncompress.h             |   19 +
 arch/arm/mach-spear6xx/include/mach/debug-macro.S  |   14 -
 arch/arm/mach-spear6xx/include/mach/gpio.h         |   19 -
 arch/arm/mach-spear6xx/include/mach/misc_regs.h    |   22 -
 arch/arm/mach-spear6xx/include/mach/timex.h        |   19 -
 arch/arm/mach-spear6xx/include/mach/uncompress.h   |   19 -
 arch/arm/mach-spear6xx/spear6xx.c                  |    6 +-
 arch/arm/mach-tegra/apbio.c                        |    4 +-
 arch/arm/mach-tegra/board-dt-tegra20.c             |    4 +-
 arch/arm/mach-tegra/board-dt-tegra30.c             |    2 +-
 arch/arm/mach-tegra/board-harmony-power.c          |    2 +-
 arch/arm/mach-tegra/board-harmony.c                |    8 +-
 arch/arm/mach-tegra/board-harmony.h                |    2 +-
 arch/arm/mach-tegra/board-paz00.c                  |    6 +-
 arch/arm/mach-tegra/board-paz00.h                  |    2 +-
 arch/arm/mach-tegra/board-pinmux.h                 |    2 +-
 arch/arm/mach-tegra/board-trimslice.c              |    4 +-
 arch/arm/mach-tegra/board-trimslice.h              |    2 +-
 arch/arm/mach-tegra/clock.c                        |    2 +-
 arch/arm/mach-tegra/clock.h                        |    2 +-
 arch/arm/mach-tegra/common.c                       |    4 +-
 arch/arm/mach-tegra/cpu-tegra.c                    |    2 +-
 arch/arm/mach-tegra/cpuidle.c                      |    2 +-
 arch/arm/mach-tegra/devices.c                      |    8 +-
 arch/arm/mach-tegra/devices.h                      |    2 +-
 arch/arm/mach-tegra/dma.c                          |    8 +-
 arch/arm/mach-tegra/flowctrl.c                     |    2 +-
 arch/arm/mach-tegra/fuse.c                         |    2 +-
 arch/arm/mach-tegra/headsmp.S                      |    2 +-
 .../mach-tegra/include/{mach => mach-tegra}/clk.h  |    0
 .../mach-tegra/include/mach-tegra/debug-macro.S    |  100 ++
 .../mach-tegra/include/{mach => mach-tegra}/dma.h  |    0
 .../arm/mach-tegra/include/mach-tegra/gpio-tegra.h |   28 +
 .../mach => mach-tegra/include/mach-tegra}/gpio.h  |    0
 .../mach-tegra/include/{mach => mach-tegra}/io.h   |    0
 .../include/{mach => mach-tegra}/iomap.h           |    0
 .../include/{mach => mach-tegra}/irammap.h         |    0
 .../mach-tegra/include/{mach => mach-tegra}/irqs.h |    0
 .../mach-tegra/include/{mach => mach-tegra}/kbc.h  |    0
 .../include/{mach => mach-tegra}/pinconf-tegra.h   |    0
 .../include/{mach => mach-tegra}/powergate.h       |    0
 .../include/{mach => mach-tegra}/sdhci.h           |    0
 .../mach-tegra/include/{mach => mach-tegra}/smmu.h |    0
 .../include/{mach => mach-tegra}/suspend.h         |    0
 .../include/{mach => mach-tegra}/tegra-ahb.h       |    0
 .../{mach => mach-tegra}/tegra_wm8903_pdata.h      |    0
 .../include/{mach => mach-tegra}/timex.h           |    0
 .../arm/mach-tegra/include/mach-tegra/uncompress.h |  236 +++
 .../include/{mach => mach-tegra}/usb_phy.h         |    0
 arch/arm/mach-tegra/include/mach/debug-macro.S     |  100 --
 arch/arm/mach-tegra/include/mach/gpio-tegra.h      |   28 -
 arch/arm/mach-tegra/include/mach/uncompress.h      |  236 ---
 arch/arm/mach-tegra/io.c                           |    2 +-
 arch/arm/mach-tegra/irq.c                          |    2 +-
 arch/arm/mach-tegra/pcie.c                         |    6 +-
 arch/arm/mach-tegra/platsmp.c                      |    6 +-
 arch/arm/mach-tegra/pmc.c                          |    2 +-
 arch/arm/mach-tegra/powergate.c                    |    6 +-
 arch/arm/mach-tegra/reset.c                        |    4 +-
 arch/arm/mach-tegra/sleep.S                        |    2 +-
 arch/arm/mach-tegra/tegra2_clocks.c                |    4 +-
 arch/arm/mach-tegra/tegra2_emc.c                   |    2 +-
 arch/arm/mach-tegra/tegra30_clocks.c               |    2 +-
 arch/arm/mach-tegra/timer.c                        |    6 +-
 arch/arm/mach-tegra/usb_phy.c                      |    6 +-
 arch/arm/mach-u300/core.c                          |   10 +-
 arch/arm/mach-u300/i2c.c                           |    2 +-
 .../mach-u300/include/{mach => mach-u300}/clkdev.h |    0
 .../include/{mach => mach-u300}/coh901318.h        |    0
 arch/arm/mach-u300/include/mach-u300/debug-macro.S |   21 +
 .../include/{mach => mach-u300}/dma_channels.h     |    0
 .../include/{mach => mach-u300}/gpio-u300.h        |    0
 .../mach => mach-u300/include/mach-u300}/gpio.h    |    0
 arch/arm/mach-u300/include/mach-u300/hardware.h    |    5 +
 .../mach-u300/include/{mach => mach-u300}/irqs.h   |    0
 .../include/{mach => mach-u300}/platform.h         |    0
 .../mach-u300/include/{mach => mach-u300}/syscon.h |    0
 .../mach-u300/include/{mach => mach-u300}/timex.h  |    0
 .../include/{mach => mach-u300}/u300-regs.h        |    0
 .../include/{mach => mach-u300}/uncompress.h       |    0
 arch/arm/mach-u300/include/mach/debug-macro.S      |   21 -
 arch/arm/mach-u300/include/mach/hardware.h         |    5 -
 arch/arm/mach-u300/regulator.c                     |    4 +-
 arch/arm/mach-u300/spi.c                           |    4 +-
 arch/arm/mach-u300/timer.c                         |    2 +-
 arch/arm/mach-u300/u300.c                          |    4 +-
 arch/arm/mach-ux500/board-mop500-msp.c             |   16 +-
 arch/arm/mach-ux500/board-mop500-pins.c            |    6 +-
 arch/arm/mach-ux500/board-mop500-sdi.c             |    6 +-
 arch/arm/mach-ux500/board-mop500-u8500uib.c        |    2 +-
 arch/arm/mach-ux500/board-mop500-uib.c             |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |   16 +-
 arch/arm/mach-ux500/board-mop500.h                 |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c                   |    4 +-
 arch/arm/mach-ux500/clock.c                        |    4 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |   12 +-
 arch/arm/mach-ux500/cpu.c                          |    6 +-
 arch/arm/mach-ux500/devices-common.c               |    4 +-
 arch/arm/mach-ux500/devices-common.h               |    2 +-
 arch/arm/mach-ux500/devices-db8500.c               |    6 +-
 arch/arm/mach-ux500/devices.c                      |    4 +-
 arch/arm/mach-ux500/id.c                           |    4 +-
 .../mach-ux500/include/mach-ux500/crypto-ux500.h   |   22 +
 .../include/{mach => mach-ux500}/db8500-regs.h     |    0
 .../mach-ux500/include/mach-ux500/debug-macro.S    |   39 +
 .../include/{mach => mach-ux500}/devices.h         |    0
 .../mach-ux500/include/{mach => mach-ux500}/gpio.h |    0
 arch/arm/mach-ux500/include/mach-ux500/hardware.h  |   48 +
 .../mach-ux500/include/{mach => mach-ux500}/id.h   |    0
 .../{mach => mach-ux500}/irqs-board-mop500.h       |    0
 .../include/{mach => mach-ux500}/irqs-db8500.h     |    0
 arch/arm/mach-ux500/include/mach-ux500/irqs.h      |   51 +
 arch/arm/mach-ux500/include/mach-ux500/msp.h       |   29 +
 .../include/{mach => mach-ux500}/setup.h           |    0
 .../include/{mach => mach-ux500}/timex.h           |    0
 .../arm/mach-ux500/include/mach-ux500/uncompress.h |   59 +
 .../mach-ux500/include/{mach => mach-ux500}/usb.h  |    0
 arch/arm/mach-ux500/include/mach/crypto-ux500.h    |   22 -
 arch/arm/mach-ux500/include/mach/debug-macro.S     |   39 -
 arch/arm/mach-ux500/include/mach/hardware.h        |   48 -
 arch/arm/mach-ux500/include/mach/irqs.h            |   51 -
 arch/arm/mach-ux500/include/mach/msp.h             |   29 -
 arch/arm/mach-ux500/include/mach/uncompress.h      |   59 -
 arch/arm/mach-ux500/platsmp.c                      |    4 +-
 arch/arm/mach-ux500/timer.c                        |    8 +-
 arch/arm/mach-ux500/usb.c                          |    6 +-
 arch/arm/mach-versatile/core.c                     |   10 +-
 .../mach-versatile/include/mach-versatile/clkdev.h |   16 +
 .../include/{mach => mach-versatile}/debug-macro.S |    0
 .../include/mach-versatile}/gpio.h                 |    0
 .../include/{mach => mach-versatile}/hardware.h    |    0
 .../include/{mach => mach-versatile}/io.h          |    0
 .../mach-versatile/include/mach-versatile/irqs.h   |  134 ++
 .../include/{mach => mach-versatile}/platform.h    |    0
 .../include/{mach => mach-versatile}/timex.h       |    0
 .../include/{mach => mach-versatile}/uncompress.h  |    0
 arch/arm/mach-versatile/include/mach/clkdev.h      |   16 -
 arch/arm/mach-versatile/include/mach/irqs.h        |  134 --
 arch/arm/mach-versatile/pci.c                      |    2 +-
 arch/arm/mach-versatile/versatile_ab.c             |    2 +-
 arch/arm/mach-versatile/versatile_pb.c             |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                  |    6 +-
 .../include/{mach => mach-vexpress}/ct-ca9x4.h     |    0
 .../include/{mach => mach-vexpress}/debug-macro.S  |    0
 .../include/mach-vexpress}/gpio.h                  |    0
 .../include/{mach => mach-vexpress}/hardware.h     |    0
 .../include/{mach => mach-vexpress}/irqs.h         |    0
 .../include/{mach => mach-vexpress}/motherboard.h  |    0
 .../include/{mach => mach-vexpress}/timex.h        |    0
 .../include/{mach => mach-vexpress}/uncompress.h   |    0
 arch/arm/mach-vexpress/platsmp.c                   |    2 +-
 arch/arm/mach-vexpress/v2m.c                       |    6 +-
 arch/arm/mach-vt8500/bv07.c                        |    2 +-
 arch/arm/mach-vt8500/devices-vt8500.c              |    6 +-
 arch/arm/mach-vt8500/devices-wm8505.c              |    6 +-
 arch/arm/mach-vt8500/devices.c                     |    4 +-
 .../include/{mach => mach-vt8500}/debug-macro.S    |    0
 .../include/{mach => mach-vt8500}/entry-macro.S    |    0
 .../include/mach-vt8500}/gpio.h                    |    0
 .../include/{mach => mach-vt8500}/hardware.h       |    0
 .../include/{mach => mach-vt8500}/i8042.h          |    0
 .../include/{mach => mach-vt8500}/irqs.h           |    0
 .../include/{mach => mach-vt8500}/restart.h        |    0
 .../include/{mach => mach-vt8500}/timex.h          |    0
 .../include/{mach => mach-vt8500}/uncompress.h     |    0
 .../include/{mach => mach-vt8500}/vt8500_irqs.h    |    0
 .../include/{mach => mach-vt8500}/vt8500_regs.h    |    0
 .../include/{mach => mach-vt8500}/vt8500fb.h       |    0
 .../include/{mach => mach-vt8500}/wm8505_irqs.h    |    0
 .../include/{mach => mach-vt8500}/wm8505_regs.h    |    0
 arch/arm/mach-vt8500/wm8505_7in.c                  |    2 +-
 arch/arm/mach-w90x900/clksel.c                     |    4 +-
 arch/arm/mach-w90x900/clock.c                      |    2 +-
 arch/arm/mach-w90x900/cpu.c                        |   10 +-
 arch/arm/mach-w90x900/dev.c                        |   12 +-
 arch/arm/mach-w90x900/gpio.c                       |    2 +-
 .../include/mach-w90x900/entry-macro.S             |   26 +
 .../include/{mach => mach-w90x900}/fb.h            |    0
 arch/arm/mach-w90x900/include/mach-w90x900/gpio.h  |   30 +
 .../mach-w90x900/include/mach-w90x900/hardware.h   |   24 +
 .../include/{mach => mach-w90x900}/i2c.h           |    0
 .../include/{mach => mach-w90x900}/irqs.h          |    0
 .../include/{mach => mach-w90x900}/map.h           |    0
 .../include/{mach => mach-w90x900}/mfp.h           |    0
 .../include/{mach => mach-w90x900}/nuc900_spi.h    |    0
 .../include/{mach => mach-w90x900}/regs-clock.h    |    0
 .../include/{mach => mach-w90x900}/regs-ebi.h      |    0
 .../include/{mach => mach-w90x900}/regs-gcr.h      |    0
 .../include/{mach => mach-w90x900}/regs-irq.h      |    0
 .../mach-w90x900/include/mach-w90x900/regs-ldm.h   |  253 +++
 .../include/{mach => mach-w90x900}/regs-serial.h   |    0
 .../include/{mach => mach-w90x900}/regs-timer.h    |    0
 .../include/{mach => mach-w90x900}/regs-usb.h      |    0
 .../include/{mach => mach-w90x900}/timex.h         |    0
 .../mach-w90x900/include/mach-w90x900/uncompress.h |   50 +
 .../{mach => mach-w90x900}/w90p910_keypad.h        |    0
 arch/arm/mach-w90x900/include/mach/entry-macro.S   |   26 -
 arch/arm/mach-w90x900/include/mach/gpio.h          |   30 -
 arch/arm/mach-w90x900/include/mach/hardware.h      |   24 -
 arch/arm/mach-w90x900/include/mach/regs-ldm.h      |  253 ---
 arch/arm/mach-w90x900/include/mach/uncompress.h    |   50 -
 arch/arm/mach-w90x900/irq.c                        |    4 +-
 arch/arm/mach-w90x900/mach-nuc910evb.c             |    2 +-
 arch/arm/mach-w90x900/mach-nuc950evb.c             |    4 +-
 arch/arm/mach-w90x900/mach-nuc960evb.c             |    2 +-
 arch/arm/mach-w90x900/mfp.c                        |    2 +-
 arch/arm/mach-w90x900/nuc910.c                     |    2 +-
 arch/arm/mach-w90x900/nuc950.c                     |    2 +-
 arch/arm/mach-w90x900/nuc960.c                     |    2 +-
 arch/arm/mach-w90x900/time.c                       |    4 +-
 arch/arm/mach-zynq/common.c                        |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/clkdev.h      |   32 +
 arch/arm/mach-zynq/include/mach-zynq/debug-macro.S |   36 +
 .../include/{mach => mach-zynq}/hardware.h         |    0
 .../mach-zynq/include/{mach => mach-zynq}/irqs.h   |    0
 .../mach-zynq/include/{mach => mach-zynq}/timex.h  |    0
 .../mach-zynq/include/{mach => mach-zynq}/uart.h   |    0
 arch/arm/mach-zynq/include/mach-zynq/uncompress.h  |   51 +
 .../include/{mach => mach-zynq}/zynq_soc.h         |    0
 arch/arm/mach-zynq/include/mach/clkdev.h           |   32 -
 arch/arm/mach-zynq/include/mach/debug-macro.S      |   36 -
 arch/arm/mach-zynq/include/mach/uncompress.h       |   51 -
 arch/arm/mach-zynq/timer.c                         |    2 +-
 arch/arm/mm/cache-feroceon-l2.c                    |    2 +-
 arch/arm/plat-mxc/3ds_debugboard.c                 |    2 +-
 arch/arm/plat-mxc/avic.c                           |    6 +-
 arch/arm/plat-mxc/clock.c                          |    4 +-
 arch/arm/plat-mxc/cpu.c                            |    2 +-
 arch/arm/plat-mxc/cpufreq.c                        |    4 +-
 arch/arm/plat-mxc/devices.c                        |    2 +-
 arch/arm/plat-mxc/devices/platform-ahci-imx.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-fec.c           |    4 +-
 arch/arm/plat-mxc/devices/platform-flexcan.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c  |    4 +-
 arch/arm/plat-mxc/devices/platform-gpio-mxc.c      |    2 +-
 arch/arm/plat-mxc/devices/platform-gpio_keys.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-dma.c       |    2 +-
 arch/arm/plat-mxc/devices/platform-imx-fb.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-i2c.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-keypad.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-ssi.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-uart.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx2-wdt.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx21-hcd.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx_udc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imxdi_rtc.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-ipu-core.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mx2-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-ehci.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-mmc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_nand.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_pwm.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rnga.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rtc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_w1.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-pata_imx.c      |    4 +-
 .../plat-mxc/devices/platform-sdhci-esdhc-imx.c    |    6 +-
 arch/arm/plat-mxc/devices/platform-spi_imx.c       |    4 +-
 arch/arm/plat-mxc/epit.c                           |    4 +-
 arch/arm/plat-mxc/include/mach/debug-macro.S       |   51 -
 arch/arm/plat-mxc/include/mach/devices-common.h    |  333 ----
 arch/arm/plat-mxc/include/mach/hardware.h          |  134 --
 arch/arm/plat-mxc/include/mach/iomux-mx1.h         |  155 --
 arch/arm/plat-mxc/include/mach/iomux-mx21.h        |  122 --
 arch/arm/plat-mxc/include/mach/iomux-mx25.h        |  524 ------
 arch/arm/plat-mxc/include/mach/iomux-mx27.h        |  205 ---
 arch/arm/plat-mxc/include/mach/iomux-mx35.h        | 1267 ---------------
 arch/arm/plat-mxc/include/mach/iomux-mx50.h        |  977 ------------
 arch/arm/plat-mxc/include/mach/iomux-mx51.h        |  827 ----------
 arch/arm/plat-mxc/include/mach/iomux-mx53.h        | 1219 --------------
 arch/arm/plat-mxc/iomux-v1.c                       |    4 +-
 arch/arm/plat-mxc/iomux-v3.c                       |    4 +-
 arch/arm/plat-mxc/iram_alloc.c                     |    2 +-
 arch/arm/plat-mxc/ssi-fiq-ksym.c                   |    2 +-
 arch/arm/plat-mxc/system.c                         |    4 +-
 arch/arm/plat-mxc/time.c                           |    4 +-
 arch/arm/plat-mxc/tzic.c                           |    6 +-
 arch/arm/plat-mxc/ulpi.c                           |    2 +-
 .../include/{plat => plat-nomadik}/gpio-nomadik.h  |    0
 .../include/{plat => plat-nomadik}/mtu.h           |    0
 .../include/{plat => plat-nomadik}/pincfg.h        |    0
 .../include/{plat => plat-nomadik}/ske.h           |    0
 .../include/{plat => plat-nomadik}/ste_dma40.h     |    0
 arch/arm/plat-omap/clock.c                         |    2 +-
 arch/arm/plat-omap/common.c                        |   12 +-
 arch/arm/plat-omap/counter_32k.c                   |    8 +-
 arch/arm/plat-omap/debug-devices.c                 |    2 +-
 arch/arm/plat-omap/debug-leds.c                    |    2 +-
 arch/arm/plat-omap/devices.c                       |   10 +-
 arch/arm/plat-omap/dma.c                           |    4 +-
 arch/arm/plat-omap/dmtimer.c                       |    4 +-
 arch/arm/plat-omap/fb.c                            |    2 +-
 arch/arm/plat-omap/i2c.c                           |    8 +-
 .../plat-omap/include/{plat => plat-omap}/am33xx.h |    0
 .../include/{plat => plat-omap}/board-ams-delta.h  |    0
 .../include/{plat => plat-omap}/board-sx1.h        |    0
 .../include/{plat => plat-omap}/board-voiceblue.h  |    0
 arch/arm/plat-omap/include/plat-omap/board.h       |  138 ++
 .../include/{plat => plat-omap}/clkdev_omap.h      |    0
 .../plat-omap/include/{plat => plat-omap}/clock.h  |    0
 arch/arm/plat-omap/include/plat-omap/common.h      |   42 +
 arch/arm/plat-omap/include/plat-omap/cpu.h         |  495 ++++++
 .../include/{plat => plat-omap}/dma-44xx.h         |    0
 arch/arm/plat-omap/include/plat-omap/dma.h         |  544 +++++++
 .../include/{plat => plat-omap}/dmtimer.h          |    0
 .../plat-omap/include/{plat => plat-omap}/dsp.h    |    0
 .../plat-omap/include/{plat => plat-omap}/flash.h  |    0
 .../plat-omap/include/{plat => plat-omap}/fpga.h   |    0
 .../include/{plat => plat-omap}/gpio-switch.h      |    0
 .../plat-omap/include/{plat => plat-omap}/gpio.h   |    0
 .../include/{plat => plat-omap}/gpmc-smc91x.h      |    0
 .../include/{plat => plat-omap}/gpmc-smsc911x.h    |    0
 .../plat-omap/include/{plat => plat-omap}/gpmc.h   |    0
 arch/arm/plat-omap/include/plat-omap/hardware.h    |  293 ++++
 arch/arm/plat-omap/include/plat-omap/hdq1w.h       |   36 +
 .../plat-omap/include/{plat => plat-omap}/i2c.h    |    0
 arch/arm/plat-omap/include/plat-omap/iommu.h       |  206 +++
 .../plat-omap/include/{plat => plat-omap}/iommu2.h |    0
 .../include/{plat => plat-omap}/iopgtable.h        |    0
 .../plat-omap/include/{plat => plat-omap}/iovmm.h  |    0
 .../plat-omap/include/{plat => plat-omap}/irda.h   |    0
 .../include/{plat => plat-omap}/irqs-44xx.h        |    0
 .../plat-omap/include/{plat => plat-omap}/irqs.h   |    0
 .../plat-omap/include/{plat => plat-omap}/keypad.h |    0
 .../include/{plat => plat-omap}/l3_2xxx.h          |    0
 .../include/{plat => plat-omap}/l3_3xxx.h          |    0
 .../include/{plat => plat-omap}/l4_2xxx.h          |    0
 .../include/{plat => plat-omap}/l4_3xxx.h          |    0
 .../include/{plat => plat-omap}/lcd_mipid.h        |    0
 .../plat-omap/include/{plat => plat-omap}/led.h    |    0
 .../include/{plat => plat-omap}/mailbox.h          |    0
 .../plat-omap/include/{plat => plat-omap}/mcbsp.h  |    0
 .../plat-omap/include/{plat => plat-omap}/mcspi.h  |    0
 .../include/{plat => plat-omap}/menelaus.h         |    0
 arch/arm/plat-omap/include/plat-omap/mmc.h         |  189 +++
 .../plat-omap/include/{plat => plat-omap}/multi.h  |    0
 .../plat-omap/include/{plat => plat-omap}/mux.h    |    0
 arch/arm/plat-omap/include/plat-omap/nand.h        |   44 +
 .../include/{plat => plat-omap}/omap-pm.h          |    0
 .../include/{plat => plat-omap}/omap-secure.h      |    0
 arch/arm/plat-omap/include/plat-omap/omap-serial.h |  140 ++
 .../include/{plat => plat-omap}/omap1510.h         |    0
 .../include/{plat => plat-omap}/omap16xx.h         |    0
 .../include/{plat => plat-omap}/omap24xx.h         |    0
 .../include/{plat => plat-omap}/omap34xx.h         |    0
 .../include/{plat => plat-omap}/omap4-keypad.h     |    0
 .../include/{plat => plat-omap}/omap44xx.h         |    0
 .../include/{plat => plat-omap}/omap54xx.h         |    0
 .../include/{plat => plat-omap}/omap7xx.h          |    0
 arch/arm/plat-omap/include/plat-omap/omap_device.h |  170 ++
 arch/arm/plat-omap/include/plat-omap/omap_hwmod.h  |  664 ++++++++
 .../include/{plat => plat-omap}/onenand.h          |    0
 .../plat-omap/include/{plat => plat-omap}/param.h  |    0
 .../plat-omap/include/{plat => plat-omap}/prcm.h   |    0
 .../include/{plat => plat-omap}/remoteproc.h       |    0
 .../plat-omap/include/{plat => plat-omap}/sdrc.h   |    0
 .../plat-omap/include/{plat => plat-omap}/serial.h |    0
 .../plat-omap/include/{plat => plat-omap}/sram.h   |    0
 .../arm/plat-omap/include/{plat => plat-omap}/tc.h |    0
 .../plat-omap/include/{plat => plat-omap}/ti81xx.h |    0
 .../plat-omap/include/{plat => plat-omap}/timex.h  |    0
 arch/arm/plat-omap/include/plat-omap/uncompress.h  |  206 +++
 arch/arm/plat-omap/include/plat-omap/usb.h         |  173 ++
 .../include/{plat => plat-omap}/voltage.h          |    0
 .../plat-omap/include/{plat => plat-omap}/vram.h   |    0
 .../plat-omap/include/{plat => plat-omap}/vrfb.h   |    0
 arch/arm/plat-omap/include/plat/board.h            |  138 --
 arch/arm/plat-omap/include/plat/common.h           |   42 -
 arch/arm/plat-omap/include/plat/cpu.h              |  495 ------
 arch/arm/plat-omap/include/plat/dma.h              |  544 -------
 arch/arm/plat-omap/include/plat/hardware.h         |  293 ----
 arch/arm/plat-omap/include/plat/hdq1w.h            |   36 -
 arch/arm/plat-omap/include/plat/iommu.h            |  206 ---
 arch/arm/plat-omap/include/plat/mmc.h              |  189 ---
 arch/arm/plat-omap/include/plat/nand.h             |   44 -
 arch/arm/plat-omap/include/plat/omap-serial.h      |  140 --
 arch/arm/plat-omap/include/plat/omap_device.h      |  170 --
 arch/arm/plat-omap/include/plat/omap_hwmod.h       |  664 --------
 arch/arm/plat-omap/include/plat/uncompress.h       |  206 ---
 arch/arm/plat-omap/include/plat/usb.h              |  173 --
 arch/arm/plat-omap/mailbox.c                       |    2 +-
 arch/arm/plat-omap/mux.c                           |    4 +-
 arch/arm/plat-omap/omap-pm-noop.c                  |    4 +-
 arch/arm/plat-omap/omap_device.c                   |    6 +-
 arch/arm/plat-omap/sram.c                          |    6 +-
 arch/arm/plat-orion/addr-map.c                     |    2 +-
 arch/arm/plat-orion/common.c                       |    4 +-
 arch/arm/plat-orion/gpio.c                         |    2 +-
 .../include/{plat => plat-orion}/addr-map.h        |    0
 .../include/{plat => plat-orion}/audio.h           |    0
 .../{plat => plat-orion}/cache-feroceon-l2.h       |    0
 .../include/{plat => plat-orion}/common.h          |    0
 .../include/{plat => plat-orion}/ehci-orion.h      |    0
 .../plat-orion/include/{plat => plat-orion}/gpio.h |    0
 .../plat-orion/include/{plat => plat-orion}/irq.h  |    0
 .../plat-orion/include/{plat => plat-orion}/mpp.h  |    0
 .../include/{plat => plat-orion}/mv_xor.h          |    0
 .../include/{plat => plat-orion}/mvsdio.h          |    0
 .../include/{plat => plat-orion}/orion_nand.h      |    0
 .../plat-orion/include/{plat => plat-orion}/pcie.h |    0
 .../plat-orion/include/{plat => plat-orion}/time.h |    0
 arch/arm/plat-orion/irq.c                          |    4 +-
 arch/arm/plat-orion/mpp.c                          |    2 +-
 arch/arm/plat-orion/pcie.c                         |    4 +-
 arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h |    0
 .../include/{plat => plat-pxa}/pxa27x_keypad.h     |    0
 .../include/{plat => plat-pxa}/pxa3xx_nand.h       |    0
 arch/arm/plat-pxa/mfp.c                            |    2 +-
 arch/arm/plat-s3c24xx/clock-dclk.c                 |    8 +-
 arch/arm/plat-s3c24xx/cpu-freq-debugfs.c           |    2 +-
 arch/arm/plat-s3c24xx/cpu-freq.c                   |    8 +-
 arch/arm/plat-s3c24xx/dma.c                        |   10 +-
 arch/arm/plat-s3c24xx/irq.c                        |    8 +-
 arch/arm/plat-s3c24xx/s3c2410-clock.c              |   14 +-
 arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c      |    8 +-
 arch/arm/plat-s3c24xx/s3c2410-iotiming.c           |    8 +-
 arch/arm/plat-s3c24xx/s3c2412-iotiming.c           |    8 +-
 arch/arm/plat-samsung/adc.c                        |    4 +-
 arch/arm/plat-samsung/clock-clksrc.c               |    6 +-
 arch/arm/plat-samsung/clock.c                      |    8 +-
 arch/arm/plat-samsung/cpu.c                        |    2 +-
 arch/arm/plat-samsung/dev-backlight.c              |    6 +-
 arch/arm/plat-samsung/dev-uart.c                   |    2 +-
 arch/arm/plat-samsung/devs.c                       |   42 +-
 .../include/{plat => plat-samsung}/adc-core.h      |    0
 .../include/{plat => plat-samsung}/adc.h           |    0
 .../include/{plat => plat-samsung}/ata-core.h      |    0
 .../include/{plat => plat-samsung}/ata.h           |    0
 .../include/{plat => plat-samsung}/audio-simtec.h  |    0
 .../include/{plat => plat-samsung}/audio.h         |    0
 .../include/{plat => plat-samsung}/backlight.h     |    0
 .../include/{plat => plat-samsung}/camport.h       |    0
 .../include/{plat => plat-samsung}/clock-clksrc.h  |    0
 .../include/{plat => plat-samsung}/clock.h         |    0
 .../include/{plat => plat-samsung}/common-smdk.h   |    0
 .../include/plat-samsung/cpu-freq-core.h           |  293 ++++
 .../include/{plat => plat-samsung}/cpu-freq.h      |    0
 .../include/{plat => plat-samsung}/cpu.h           |    0
 .../include/plat-samsung/debug-macro.S             |   87 +
 .../include/{plat => plat-samsung}/devs.h          |    0
 .../include/{plat => plat-samsung}/dma-core.h      |    0
 .../include/{plat => plat-samsung}/dma-ops.h       |    0
 .../plat-samsung/include/plat-samsung/dma-pl330.h  |  122 ++
 .../include/plat-samsung/dma-s3c24xx.h             |   78 +
 arch/arm/plat-samsung/include/plat-samsung/dma.h   |  130 ++
 .../include/{plat => plat-samsung}/ehci.h          |    0
 .../include/{plat => plat-samsung}/fb-core.h       |    0
 .../include/{plat => plat-samsung}/fb-s3c2410.h    |    0
 .../include/{plat => plat-samsung}/fb.h            |    0
 .../include/{plat => plat-samsung}/fimc-core.h     |    0
 .../include/{plat => plat-samsung}/fiq.h           |    0
 .../{plat => plat-samsung}/gpio-cfg-helpers.h      |    0
 .../include/{plat => plat-samsung}/gpio-cfg.h      |    0
 .../plat-samsung/include/plat-samsung/gpio-core.h  |  124 ++
 .../plat-samsung/include/plat-samsung/gpio-fns.h   |   98 ++
 .../include/{plat => plat-samsung}/hwmon.h         |    0
 .../include/{plat => plat-samsung}/iic-core.h      |    0
 .../include/{plat => plat-samsung}/iic.h           |    0
 .../include/{plat => plat-samsung}/irq-uart.h      |    0
 .../include/{plat => plat-samsung}/irq-vic-timer.h |    0
 .../include/{plat => plat-samsung}/irq.h           |    0
 .../include/{plat => plat-samsung}/irqs.h          |    0
 .../include/{plat => plat-samsung}/keypad-core.h   |    0
 .../include/{plat => plat-samsung}/keypad.h        |    0
 .../include/{plat => plat-samsung}/map-base.h      |    0
 .../plat-samsung/include/plat-samsung/map-s3c.h    |   84 +
 .../plat-samsung/include/plat-samsung/map-s5p.h    |   61 +
 .../include/{plat => plat-samsung}/mci.h           |    0
 .../include/{plat => plat-samsung}/mfc.h           |    0
 .../include/{plat => plat-samsung}/mipi_csis.h     |    0
 .../include/{plat => plat-samsung}/nand-core.h     |    0
 .../include/{plat => plat-samsung}/nand.h          |    0
 .../include/{plat => plat-samsung}/onenand-core.h  |    0
 .../include/{plat => plat-samsung}/pll.h           |    0
 .../include/{plat => plat-samsung}/pm.h            |    0
 .../include/{plat => plat-samsung}/pwm-clock.h     |    0
 .../include/{plat => plat-samsung}/regs-ac97.h     |    0
 .../include/{plat => plat-samsung}/regs-adc.h      |    0
 .../include/{plat => plat-samsung}/regs-ata.h      |    0
 .../include/{plat => plat-samsung}/regs-dma.h      |    0
 .../plat-samsung/include/plat-samsung/regs-fb-v4.h |  159 ++
 .../include/{plat => plat-samsung}/regs-fb.h       |    0
 .../include/{plat => plat-samsung}/regs-iic.h      |    0
 .../include/{plat => plat-samsung}/regs-iis.h      |    0
 .../include/{plat => plat-samsung}/regs-irqtype.h  |    0
 .../include/{plat => plat-samsung}/regs-nand.h     |    0
 .../include/{plat => plat-samsung}/regs-onenand.h  |    0
 .../include/{plat => plat-samsung}/regs-rtc.h      |    0
 .../include/{plat => plat-samsung}/regs-sdhci.h    |    0
 .../include/{plat => plat-samsung}/regs-serial.h   |    0
 .../include/{plat => plat-samsung}/regs-spi.h      |    0
 .../include/{plat => plat-samsung}/regs-srom.h     |    0
 .../include/{plat => plat-samsung}/regs-timer.h    |    0
 .../include/{plat => plat-samsung}/regs-udc.h      |    0
 .../{plat => plat-samsung}/regs-usb-hsotg-phy.h    |    0
 .../include/{plat => plat-samsung}/regs-watchdog.h |    0
 .../include/{plat => plat-samsung}/rtc-core.h      |    0
 .../include/{plat => plat-samsung}/s3c2410.h       |    0
 .../include/{plat => plat-samsung}/s3c2412.h       |    0
 .../include/{plat => plat-samsung}/s3c2416.h       |    0
 .../include/{plat => plat-samsung}/s3c2443.h       |    0
 .../include/{plat => plat-samsung}/s3c244x.h       |    0
 .../include/{plat => plat-samsung}/s3c64xx-spi.h   |    0
 .../include/{plat => plat-samsung}/s5p-clock.h     |    0
 .../include/{plat => plat-samsung}/s5p-time.h      |    0
 arch/arm/plat-samsung/include/plat-samsung/sdhci.h |  380 +++++
 .../include/{plat => plat-samsung}/ts.h            |    0
 .../include/{plat => plat-samsung}/tv-core.h       |    0
 .../include/{plat => plat-samsung}/udc.h           |    0
 .../plat-samsung/include/plat-samsung/uncompress.h |  186 +++
 .../include/{plat => plat-samsung}/usb-control.h   |    0
 .../include/{plat => plat-samsung}/usb-phy.h       |    0
 .../include/{plat => plat-samsung}/wakeup-mask.h   |    0
 .../include/plat-samsung/watchdog-reset.h          |   46 +
 arch/arm/plat-samsung/include/plat/cpu-freq-core.h |  293 ----
 arch/arm/plat-samsung/include/plat/debug-macro.S   |   87 -
 arch/arm/plat-samsung/include/plat/dma-pl330.h     |  122 --
 arch/arm/plat-samsung/include/plat/dma-s3c24xx.h   |   78 -
 arch/arm/plat-samsung/include/plat/dma.h           |  130 --
 arch/arm/plat-samsung/include/plat/gpio-core.h     |  124 --
 arch/arm/plat-samsung/include/plat/gpio-fns.h      |   98 --
 arch/arm/plat-samsung/include/plat/map-s3c.h       |   84 -
 arch/arm/plat-samsung/include/plat/map-s5p.h       |   61 -
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --
 arch/arm/plat-samsung/include/plat/sdhci.h         |  380 -----
 arch/arm/plat-samsung/include/plat/uncompress.h    |  186 ---
 .../arm/plat-samsung/include/plat/watchdog-reset.h |   46 -
 arch/arm/plat-samsung/init.c                       |    8 +-
 arch/arm/plat-samsung/irq-vic-timer.c              |    6 +-
 arch/arm/plat-samsung/platformdata.c               |    4 +-
 arch/arm/plat-samsung/pm-check.c                   |    2 +-
 arch/arm/plat-samsung/pm-gpio.c                    |    4 +-
 arch/arm/plat-samsung/pm.c                         |    4 +-
 arch/arm/plat-samsung/pwm-clock.c                  |    8 +-
 arch/arm/plat-samsung/s5p-clock.c                  |    6 +-
 arch/arm/plat-samsung/s5p-dev-mfc.c                |    6 +-
 arch/arm/plat-samsung/s5p-dev-uart.c               |    2 +-
 arch/arm/plat-samsung/s5p-irq-eint.c               |    8 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c            |    4 +-
 arch/arm/plat-samsung/s5p-irq-pm.c                 |    6 +-
 arch/arm/plat-samsung/s5p-irq.c                    |    6 +-
 arch/arm/plat-samsung/s5p-pm.c                     |    2 +-
 arch/arm/plat-samsung/s5p-time.c                   |    6 +-
 arch/arm/plat-samsung/time.c                       |    6 +-
 arch/arm/plat-samsung/wakeup-mask.c                |    4 +-
 .../include/{plat => plat-spear}/debug-macro.S     |    0
 .../plat-spear/include/{plat => plat-spear}/gpio.h |    0
 .../include/{plat => plat-spear}/keyboard.h        |    0
 .../include/{plat => plat-spear}/pl080.h           |    0
 .../include/{plat => plat-spear}/shirq.h           |    0
 .../include/{plat => plat-spear}/timex.h           |    0
 .../include/{plat => plat-spear}/uncompress.h      |    0
 arch/arm/plat-spear/shirq.c                        |    2 +-
 arch/arm/plat-versatile/clcd.c                     |    2 +-
 arch/arm/plat-versatile/fpga-irq.c                 |    2 +-
 .../include/{plat => plat-versatile}/clcd.h        |    0
 .../include/{plat => plat-versatile}/clock.h       |    0
 .../include/{plat => plat-versatile}/fpga-irq.h    |    0
 .../include/{plat => plat-versatile}/sched_clock.h |    0
 arch/arm/plat-versatile/sched-clock.c              |    2 +-
 arch/arm/tools/Makefile                            |    5 +
 arch/arm/tools/gen-headers                         |   57 +
 drivers/ata/pata_at91.c                            |    4 +-
 drivers/ata/pata_palmld.c                          |    2 +-
 drivers/ata/pata_pxa.c                             |    6 +-
 drivers/ata/pata_samsung_cf.c                      |    4 +-
 drivers/char/ds1620.c                              |    2 +-
 drivers/char/hw_random/ixp4xx-rng.c                |    2 +-
 drivers/char/hw_random/omap-rng.c                  |    2 +-
 drivers/char/msm_smd_pkt.c                         |    2 +-
 drivers/clk/clk-u300.c                             |    2 +-
 drivers/clk/mxs/clk-imx23.c                        |    4 +-
 drivers/clk/mxs/clk-imx28.c                        |    4 +-
 drivers/clocksource/clksrc-dbx500-prcmu.c          |    4 +-
 drivers/cpufreq/db8500-cpufreq.c                   |    2 +-
 drivers/cpufreq/exynos-cpufreq.c                   |    4 +-
 drivers/cpufreq/exynos4210-cpufreq.c               |    4 +-
 drivers/cpufreq/exynos4x12-cpufreq.c               |    4 +-
 drivers/cpufreq/exynos5250-cpufreq.c               |    6 +-
 drivers/cpufreq/omap-cpufreq.c                     |   10 +-
 drivers/cpufreq/s5pv210-cpufreq.c                  |    2 +-
 drivers/crypto/ixp4xx_crypto.c                     |    4 +-
 drivers/crypto/omap-aes.c                          |    4 +-
 drivers/crypto/omap-sham.c                         |    6 +-
 drivers/crypto/s5p-sss.c                           |    4 +-
 drivers/crypto/tegra-aes.c                         |    2 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |    6 +-
 drivers/crypto/ux500/hash/hash_core.c              |    4 +-
 drivers/devfreq/exynos4_bus.c                      |    4 +-
 drivers/dma/at_hdmac_regs.h                        |    2 +-
 drivers/dma/coh901318.c                            |    2 +-
 drivers/dma/coh901318_lli.c                        |    2 +-
 drivers/dma/coh901318_lli.h                        |    2 +-
 drivers/dma/ep93xx_dma.c                           |    2 +-
 drivers/dma/imx-dma.c                              |    4 +-
 drivers/dma/imx-sdma.c                             |    6 +-
 drivers/dma/ipu/ipu_idmac.c                        |    2 +-
 drivers/dma/ipu/ipu_irq.c                          |    2 +-
 drivers/dma/mmp_tdma.c                             |    4 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/dma/omap-dma.c                             |    2 +-
 drivers/dma/ste_dma40.c                            |    2 +-
 drivers/dma/ste_dma40_ll.c                         |    2 +-
 drivers/gpio/gpio-ep93xx.c                         |    4 +-
 drivers/gpio/gpio-ks8695.c                         |    6 +-
 drivers/gpio/gpio-lpc32xx.c                        |    8 +-
 drivers/gpio/gpio-msm-v1.c                         |    6 +-
 drivers/gpio/gpio-msm-v2.c                         |    4 +-
 drivers/gpio/gpio-omap.c                           |    4 +-
 drivers/gpio/gpio-pxa.c                            |    8 +-
 drivers/gpio/gpio-samsung.c                        |   12 +-
 drivers/gpio/gpio-tegra.c                          |    4 +-
 drivers/gpio/gpio-tnetv107x.c                      |    4 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/hwmon/s3c-hwmon.c                          |    4 +-
 drivers/i2c/busses/i2c-acorn.c                     |    2 +-
 drivers/i2c/busses/i2c-at91.c                      |    6 +-
 drivers/i2c/busses/i2c-davinci.c                   |    4 +-
 drivers/i2c/busses/i2c-imx.c                       |    4 +-
 drivers/i2c/busses/i2c-nuc900.c                    |    4 +-
 drivers/i2c/busses/i2c-s3c2410.c                   |    4 +-
 drivers/i2c/busses/i2c-tegra.c                     |    2 +-
 drivers/iio/adc/at91_adc.c                         |    2 +-
 drivers/input/keyboard/davinci_keyscan.c           |    6 +-
 drivers/input/keyboard/ep93xx_keypad.c             |    4 +-
 drivers/input/keyboard/jornada720_kbd.c            |    6 +-
 drivers/input/keyboard/nomadik-ske-keypad.c        |    2 +-
 drivers/input/keyboard/omap-keypad.c               |    6 +-
 drivers/input/keyboard/pxa27x_keypad.c             |    2 +-
 drivers/input/keyboard/pxa930_rotary.c             |    2 +-
 drivers/input/keyboard/spear-keyboard.c            |    2 +-
 drivers/input/keyboard/tegra-kbc.c                 |    4 +-
 drivers/input/keyboard/w90p910_keypad.c            |    2 +-
 drivers/input/misc/ixp4xx-beeper.c                 |    2 +-
 drivers/input/mouse/pxa930_trkball.c               |    4 +-
 drivers/input/mouse/rpcmouse.c                     |    2 +-
 drivers/input/serio/ams_delta_serio.c              |    4 +-
 drivers/input/serio/rpckbd.c                       |    2 +-
 drivers/input/touchscreen/atmel_tsadcc.c           |    4 +-
 drivers/input/touchscreen/h3600_ts_input.c         |    4 +-
 drivers/input/touchscreen/jornada720_ts.c          |    6 +-
 drivers/input/touchscreen/mainstone-wm97xx.c       |    2 +-
 drivers/input/touchscreen/s3c2410_ts.c             |    6 +-
 drivers/input/touchscreen/tnetv107x-ts.c           |    2 +-
 drivers/input/touchscreen/zylonite-wm97xx.c        |    6 +-
 drivers/iommu/exynos-iommu.c                       |    2 +-
 drivers/iommu/msm_iommu.c                          |    4 +-
 drivers/iommu/msm_iommu_dev.c                      |    6 +-
 drivers/iommu/omap-iommu-debug.c                   |    6 +-
 drivers/iommu/omap-iommu.c                         |    4 +-
 drivers/iommu/omap-iovmm.c                         |    6 +-
 drivers/iommu/tegra-smmu.c                         |    6 +-
 drivers/leds/leds-fsg.c                            |    2 +-
 drivers/leds/leds-netxbig.c                        |    2 +-
 drivers/leds/leds-ns2.c                            |    2 +-
 drivers/leds/leds-s3c24xx.c                        |    6 +-
 drivers/media/video/davinci/isif.c                 |    2 +-
 drivers/media/video/davinci/vpbe_display.c         |    2 +-
 drivers/media/video/davinci/vpbe_osd.c             |    4 +-
 drivers/media/video/davinci/vpbe_venc.c            |    6 +-
 drivers/media/video/davinci/vpif.c                 |    2 +-
 drivers/media/video/davinci/vpss.c                 |    2 +-
 drivers/media/video/mx1_camera.c                   |    8 +-
 drivers/media/video/mx2_camera.c                   |    4 +-
 drivers/media/video/mx3_camera.c                   |    6 +-
 drivers/media/video/omap/omap_vout.c               |    4 +-
 drivers/media/video/omap/omap_vout_vrfb.c          |    4 +-
 drivers/media/video/omap/omap_voutdef.h            |    2 +-
 drivers/media/video/omap/omap_voutlib.c            |    2 +-
 drivers/media/video/omap1_camera.c                 |    2 +-
 drivers/media/video/omap3isp/isp.h                 |    4 +-
 drivers/media/video/omap3isp/ispreg.h              |    2 +-
 drivers/media/video/omap3isp/ispstat.h             |    2 +-
 drivers/media/video/omap3isp/ispvideo.c            |    6 +-
 drivers/media/video/pxa_camera.c                   |    4 +-
 drivers/media/video/s5p-fimc/mipi-csis.c           |    2 +-
 drivers/media/video/s5p-tv/sii9234_drv.c           |    2 +-
 drivers/mfd/db8500-prcmu.c                         |    8 +-
 drivers/mfd/dbx500-prcmu-regs.h                    |    2 +-
 drivers/mfd/mcp-sa11x0.c                           |    4 +-
 drivers/mfd/menelaus.c                             |    2 +-
 drivers/mfd/omap-usb-host.c                        |    4 +-
 drivers/mfd/ucb1x00-ts.c                           |    2 +-
 drivers/misc/ep93xx_pwm.c                          |    2 +-
 drivers/misc/spear13xx_pcie_gadget.c               |    4 +-
 drivers/mmc/host/at91_mci.c                        |    4 +-
 drivers/mmc/host/davinci_mmc.c                     |    4 +-
 drivers/mmc/host/msm_sdcc.c                        |    8 +-
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mmc/host/mxcmmc.c                          |    6 +-
 drivers/mmc/host/omap.c                            |   10 +-
 drivers/mmc/host/omap_hsmmc.c                      |    8 +-
 drivers/mmc/host/pxamci.c                          |    6 +-
 drivers/mmc/host/s3cmci.c                          |    6 +-
 drivers/mmc/host/sdhci-cns3xxx.c                   |    2 +-
 drivers/mmc/host/sdhci-esdhc-imx.c                 |    2 +-
 drivers/mmc/host/sdhci-s3c.c                       |    4 +-
 drivers/mmc/host/sdhci-tegra.c                     |    4 +-
 drivers/mtd/maps/autcpu12-nvram.c                  |    4 +-
 drivers/mtd/maps/cdb89712.c                        |    2 +-
 drivers/mtd/maps/h720x-flash.c                     |    2 +-
 drivers/mtd/maps/pxa2xx-flash.c                    |    2 +-
 drivers/mtd/maps/sa1100-flash.c                    |    2 +-
 drivers/mtd/nand/ams-delta.c                       |    4 +-
 drivers/mtd/nand/autcpu12.c                        |    4 +-
 drivers/mtd/nand/bcm_umi_nand.c                    |    8 +-
 drivers/mtd/nand/cmx270_nand.c                     |    2 +-
 drivers/mtd/nand/davinci_nand.c                    |    4 +-
 drivers/mtd/nand/mxc_nand.c                        |    4 +-
 drivers/mtd/nand/nand_bcm_umi.c                    |    2 +-
 drivers/mtd/nand/nand_bcm_umi.h                    |    4 +-
 drivers/mtd/nand/nomadik_nand.c                    |    4 +-
 drivers/mtd/nand/omap2.c                           |    6 +-
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c                     |    2 +-
 drivers/mtd/nand/s3c2410.c                         |    4 +-
 drivers/mtd/nand/sharpsl.c                         |    2 +-
 drivers/mtd/onenand/omap2.c                        |    8 +-
 drivers/mtd/onenand/samsung.c                      |    2 +-
 drivers/net/can/at91_can.c                         |    2 +-
 drivers/net/ethernet/amd/am79c961a.c               |    2 +-
 drivers/net/ethernet/cadence/at91_ether.c          |    4 +-
 drivers/net/ethernet/cirrus/ep93xx_eth.c           |    2 +-
 drivers/net/ethernet/micrel/ks8695net.c            |    6 +-
 drivers/net/ethernet/netx-eth.c                    |   10 +-
 drivers/net/ethernet/nxp/lpc_eth.c                 |    6 +-
 drivers/net/ethernet/smsc/smc911x.h                |    2 +-
 drivers/net/ethernet/smsc/smc91x.h                 |    4 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    6 +-
 drivers/net/irda/ep7211-sir.c                      |    2 +-
 drivers/net/irda/pxaficp_ir.c                      |    8 +-
 drivers/net/irda/sa1100_ir.c                       |    2 +-
 drivers/net/wan/ixp4xx_hss.c                       |    4 +-
 drivers/pcmcia/at91_cf.c                           |    8 +-
 drivers/pcmcia/omap_cf.c                           |    6 +-
 drivers/pcmcia/pxa2xx_balloon3.c                   |    2 +-
 drivers/pcmcia/pxa2xx_base.c                       |    6 +-
 drivers/pcmcia/pxa2xx_cm_x2xx.c                    |    2 +-
 drivers/pcmcia/pxa2xx_e740.c                       |    2 +-
 drivers/pcmcia/pxa2xx_hx4700.c                     |    2 +-
 drivers/pcmcia/pxa2xx_mainstone.c                  |    4 +-
 drivers/pcmcia/pxa2xx_palmld.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtc.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtx.c                     |    2 +-
 drivers/pcmcia/pxa2xx_trizeps4.c                   |    4 +-
 drivers/pcmcia/pxa2xx_viper.c                      |    2 +-
 drivers/pcmcia/pxa2xx_vpac270.c                    |    2 +-
 drivers/pcmcia/sa1100_assabet.c                    |    2 +-
 drivers/pcmcia/sa1100_cerf.c                       |    4 +-
 drivers/pcmcia/sa1100_h3600.c                      |    4 +-
 drivers/pcmcia/sa1100_nanoengine.c                 |    4 +-
 drivers/pcmcia/sa1100_shannon.c                    |    4 +-
 drivers/pcmcia/sa1100_simpad.c                     |    4 +-
 drivers/pcmcia/sa1111_badge4.c                     |    4 +-
 drivers/pcmcia/sa1111_jornada720.c                 |    2 +-
 drivers/pcmcia/sa1111_lubbock.c                    |    4 +-
 drivers/pcmcia/sa1111_neponset.c                   |    4 +-
 drivers/pcmcia/sa11xx_base.c                       |    2 +-
 drivers/pinctrl/pinctrl-coh901.c                   |    2 +-
 drivers/pinctrl/pinctrl-nomadik.c                  |    4 +-
 drivers/pinctrl/pinctrl-nomadik.h                  |    2 +-
 drivers/pinctrl/pinctrl-tegra.c                    |    2 +-
 drivers/power/avs/smartreflex.c                    |    1 +
 drivers/power/collie_battery.c                     |    2 +-
 drivers/power/s3c_adc_battery.c                    |    2 +-
 drivers/power/tosa_battery.c                       |    2 +-
 drivers/ptp/ptp_ixp46x.c                           |    2 +-
 drivers/pwm/pwm-imx.c                              |    2 +-
 drivers/pwm/pwm-samsung.c                          |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |    4 +-
 drivers/rtc/rtc-at91rm9200.c                       |    2 +-
 drivers/rtc/rtc-at91sam9.c                         |    6 +-
 drivers/rtc/rtc-mxc.c                              |    2 +-
 drivers/rtc/rtc-pxa.c                              |    2 +-
 drivers/rtc/rtc-s3c.c                              |    2 +-
 drivers/rtc/rtc-stmp3xxx.c                         |    2 +-
 drivers/scsi/arm/acornscsi-io.S                    |    2 +-
 drivers/spi/spi-davinci.c                          |    4 +-
 drivers/spi/spi-ep93xx.c                           |    4 +-
 drivers/spi/spi-imx.c                              |    2 +-
 drivers/spi/spi-nuc900.c                           |    2 +-
 drivers/spi/spi-omap-100k.c                        |    2 +-
 drivers/spi/spi-omap-uwire.c                       |    6 +-
 drivers/spi/spi-omap2-mcspi.c                      |    4 +-
 drivers/spi/spi-s3c24xx-fiq.S                      |    6 +-
 drivers/spi/spi-s3c24xx.c                          |    4 +-
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/spi/spi-tegra.c                            |    2 +-
 drivers/staging/nvec/nvec.c                        |    4 +-
 drivers/staging/omapdrm/omap_dmm_tiler.h           |    2 +-
 .../staging/ste_rmi4/board-mop500-u8500uib-rmi4.c  |    4 +-
 drivers/staging/tidspbridge/core/dsp-clock.c       |    4 +-
 drivers/staging/tidspbridge/core/tiomap3430.c      |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430_pwr.c  |    2 +-
 drivers/staging/tidspbridge/core/tiomap_io.c       |    2 +-
 drivers/staging/tidspbridge/core/ue_deh.c          |    2 +-
 .../tidspbridge/include/dspbridge/host_os.h        |    4 +-
 drivers/staging/tidspbridge/rmgr/drv_interface.c   |    2 +-
 drivers/tty/serial/21285.c                         |    2 +-
 drivers/tty/serial/atmel_serial.c                  |    6 +-
 drivers/tty/serial/clps711x.c                      |    2 +-
 drivers/tty/serial/imx.c                           |    2 +-
 drivers/tty/serial/msm_serial_hs.c                 |    4 +-
 drivers/tty/serial/msm_smd_tty.c                   |    2 +-
 drivers/tty/serial/netx-serial.c                   |    4 +-
 drivers/tty/serial/omap-serial.c                   |    6 +-
 drivers/tty/serial/sa1100.c                        |    4 +-
 drivers/tty/serial/samsung.c                       |    4 +-
 drivers/tty/serial/serial_ks8695.c                 |    4 +-
 drivers/uio/uio_pruss.c                            |    2 +-
 drivers/usb/gadget/at91_udc.c                      |   10 +-
 drivers/usb/gadget/atmel_usba_udc.c                |    4 +-
 drivers/usb/gadget/fsl_mxc_udc.c                   |    2 +-
 drivers/usb/gadget/imx_udc.c                       |    4 +-
 drivers/usb/gadget/omap_udc.c                      |    2 +-
 drivers/usb/gadget/pxa25x_udc.c                    |    4 +-
 drivers/usb/gadget/pxa25x_udc.h                    |    2 +-
 drivers/usb/gadget/pxa27x_udc.c                    |    4 +-
 drivers/usb/gadget/s3c-hsudc.c                     |    2 +-
 drivers/usb/gadget/s3c2410_udc.c                   |    4 +-
 drivers/usb/host/ehci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ehci-mxc.c                        |    4 +-
 drivers/usb/host/ehci-omap.c                       |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 drivers/usb/host/ehci-s5p.c                        |    4 +-
 drivers/usb/host/ehci-tegra.c                      |    4 +-
 drivers/usb/host/imx21-hcd.h                       |    2 +-
 drivers/usb/host/ohci-at91.c                       |    6 +-
 drivers/usb/host/ohci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ohci-da8xx.c                      |    4 +-
 drivers/usb/host/ohci-exynos.c                     |    4 +-
 drivers/usb/host/ohci-omap.c                       |    4 +-
 drivers/usb/host/ohci-omap3.c                      |    2 +-
 drivers/usb/host/ohci-pxa27x.c                     |    6 +-
 drivers/usb/host/ohci-s3c2410.c                    |    2 +-
 drivers/usb/host/ohci-sa1111.c                     |    4 +-
 drivers/usb/musb/am35x.c                           |    2 +-
 drivers/usb/musb/da8xx.c                           |    4 +-
 drivers/usb/musb/davinci.c                         |    4 +-
 drivers/usb/musb/musb_dsps.c                       |    2 +-
 drivers/usb/musb/omap2430.h                        |    2 +-
 drivers/usb/musb/tusb6010_omap.c                   |    4 +-
 drivers/usb/musb/ux500_dma.c                       |    2 +-
 drivers/usb/otg/isp1301_omap.c                     |    2 +-
 drivers/usb/otg/msm_otg.c                          |    2 +-
 drivers/video/acornfb.c                            |    4 +-
 drivers/video/backlight/jornada720_bl.c            |    4 +-
 drivers/video/backlight/jornada720_lcd.c           |    4 +-
 drivers/video/backlight/omap1_bl.c                 |    6 +-
 drivers/video/backlight/tosa_bl.c                  |    2 +-
 drivers/video/backlight/tosa_lcd.c                 |    2 +-
 drivers/video/clps711xfb.c                         |    4 +-
 drivers/video/cyber2000fb.c                        |    2 +-
 drivers/video/ep93xx-fb.c                          |    2 +-
 drivers/video/exynos/exynos_mipi_dsi.c             |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_common.c      |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_lowlevel.c    |    2 +-
 drivers/video/imxfb.c                              |    4 +-
 drivers/video/msm/mddi.c                           |    8 +-
 drivers/video/msm/mddi_client_dummy.c              |    2 +-
 drivers/video/msm/mddi_client_nt35399.c            |    2 +-
 drivers/video/msm/mddi_client_toshiba.c            |    2 +-
 drivers/video/msm/mdp.c                            |    4 +-
 drivers/video/msm/mdp_hw.h                         |    4 +-
 drivers/video/msm/mdp_ppp.c                        |    2 +-
 drivers/video/msm/msm_fb.c                         |    4 +-
 drivers/video/mx3fb.c                              |    8 +-
 drivers/video/nuc900fb.c                           |    8 +-
 drivers/video/nuc900fb.h                           |    4 +-
 drivers/video/omap/hwa742.c                        |    2 +-
 drivers/video/omap/lcd_ams_delta.c                 |    4 +-
 drivers/video/omap/lcd_inn1510.c                   |    2 +-
 drivers/video/omap/lcd_mipid.c                     |    2 +-
 drivers/video/omap/lcd_osk.c                       |    2 +-
 drivers/video/omap/lcd_palmte.c                    |    2 +-
 drivers/video/omap/lcdc.c                          |    4 +-
 drivers/video/omap/omapfb_main.c                   |    2 +-
 drivers/video/omap/sossi.c                         |    2 +-
 drivers/video/omap2/dss/dispc.c                    |    2 +-
 drivers/video/omap2/dss/dpi.c                      |    2 +-
 drivers/video/omap2/dss/dsi.c                      |    2 +-
 drivers/video/omap2/dss/dss.c                      |    4 +-
 drivers/video/omap2/dss/dss_features.c             |    2 +-
 drivers/video/omap2/dss/overlay.c                  |    2 +-
 drivers/video/omap2/dss/venc.c                     |    2 +-
 drivers/video/omap2/omapfb/omapfb-ioctl.c          |    4 +-
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 +-
 drivers/video/omap2/omapfb/omapfb-sysfs.c          |    2 +-
 drivers/video/omap2/vram.c                         |    4 +-
 drivers/video/omap2/vrfb.c                         |    4 +-
 drivers/video/pnx4008/dum.h                        |    2 +-
 drivers/video/pxafb.c                              |    6 +-
 drivers/video/s3c-fb.c                             |    4 +-
 drivers/video/sa1100fb.c                           |    4 +-
 drivers/video/vt8500lcdfb.c                        |    2 +-
 drivers/video/wm8505fb.c                           |    2 +-
 drivers/w1/masters/omap_hdq.c                      |    2 +-
 drivers/watchdog/at91rm9200_wdt.c                  |    2 +-
 drivers/watchdog/imx2_wdt.c                        |    2 +-
 drivers/watchdog/ixp4xx_wdt.c                      |    2 +-
 drivers/watchdog/ks8695_wdt.c                      |    4 +-
 drivers/watchdog/omap_wdt.c                        |    2 +-
 drivers/watchdog/s3c2410_wdt.c                     |    2 +-
 drivers/watchdog/wdt285.c                          |    2 +-
 include/linux/mfd/davinci_voicecodec.h             |    2 +-
 include/linux/mfd/dbx500-prcmu.h                   |    2 +-
 include/linux/omapfb.h                             |    2 +-
 include/linux/platform_data/atmel-aes.h            |    2 +-
 include/linux/power/smartreflex.h                  |    2 +-
 include/linux/spi/pxa2xx_spi.h                     |    2 +-
 sound/arm/pxa2xx-ac97-lib.c                        |    6 +-
 sound/arm/pxa2xx-ac97.c                            |    4 +-
 sound/arm/pxa2xx-pcm-lib.c                         |    2 +-
 sound/arm/pxa2xx-pcm.h                             |    2 +-
 sound/atmel/ac97c.c                                |    6 +-
 sound/oss/vidc.c                                   |    2 +-
 sound/oss/vidc_fill.S                              |    2 +-
 sound/oss/waveartist.c                             |    2 +-
 sound/soc/atmel/atmel_ssc_dai.c                    |    2 +-
 sound/soc/atmel/sam9g20_wm8731.c                   |    4 +-
 sound/soc/atmel/snd-soc-afeb9260.c                 |    2 +-
 sound/soc/davinci/davinci-evm.c                    |    6 +-
 sound/soc/davinci/davinci-i2s.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.h                  |    2 +-
 sound/soc/davinci/davinci-pcm.c                    |    4 +-
 sound/soc/davinci/davinci-pcm.h                    |    4 +-
 sound/soc/davinci/davinci-sffsdr.c                 |    2 +-
 sound/soc/ep93xx/edb93xx.c                         |    2 +-
 sound/soc/ep93xx/ep93xx-ac97.c                     |    2 +-
 sound/soc/ep93xx/ep93xx-i2s.c                      |    6 +-
 sound/soc/ep93xx/ep93xx-pcm.c                      |    6 +-
 sound/soc/ep93xx/simone.c                          |    2 +-
 sound/soc/ep93xx/snappercl15.c                     |    2 +-
 sound/soc/fsl/imx-pcm-fiq.c                        |    4 +-
 sound/soc/fsl/imx-ssi.c                            |    4 +-
 sound/soc/fsl/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    4 +-
 sound/soc/kirkwood/kirkwood-t5325.c                |    4 +-
 sound/soc/mxs/mxs-saif.c                           |    4 +-
 sound/soc/nuc900/nuc900-ac97.c                     |    2 +-
 sound/soc/nuc900/nuc900-pcm.c                      |    2 +-
 sound/soc/omap/am3517evm.c                         |    6 +-
 sound/soc/omap/ams-delta.c                         |    4 +-
 sound/soc/omap/igep0020.c                          |    6 +-
 sound/soc/omap/mcbsp.c                             |    2 +-
 sound/soc/omap/n810.c                              |    4 +-
 sound/soc/omap/omap-abe-twl6040.c                  |    4 +-
 sound/soc/omap/omap-dmic.c                         |    2 +-
 sound/soc/omap/omap-hdmi.c                         |    2 +-
 sound/soc/omap/omap-mcbsp.c                        |    4 +-
 sound/soc/omap/omap-mcpdm.c                        |    4 +-
 sound/soc/omap/omap-pcm.c                          |    2 +-
 sound/soc/omap/omap3beagle.c                       |    6 +-
 sound/soc/omap/omap3evm.c                          |    6 +-
 sound/soc/omap/omap3pandora.c                      |    2 +-
 sound/soc/omap/osk5912.c                           |    4 +-
 sound/soc/omap/overo.c                             |    6 +-
 sound/soc/omap/rx51.c                              |    2 +-
 sound/soc/omap/sdp3430.c                           |    6 +-
 sound/soc/omap/zoom2.c                             |    8 +-
 sound/soc/pxa/corgi.c                              |    4 +-
 sound/soc/pxa/e740_wm9705.c                        |    4 +-
 sound/soc/pxa/e750_wm9705.c                        |    4 +-
 sound/soc/pxa/e800_wm9712.c                        |    4 +-
 sound/soc/pxa/em-x270.c                            |    2 +-
 sound/soc/pxa/hx4700.c                             |    2 +-
 sound/soc/pxa/magician.c                           |    2 +-
 sound/soc/pxa/mioa701_wm9713.c                     |    2 +-
 sound/soc/pxa/mmp-pcm.c                            |    2 +-
 sound/soc/pxa/palm27x.c                            |    4 +-
 sound/soc/pxa/poodle.c                             |    4 +-
 sound/soc/pxa/pxa-ssp.c                            |    4 +-
 sound/soc/pxa/pxa2xx-ac97.c                        |    8 +-
 sound/soc/pxa/pxa2xx-i2s.c                         |    6 +-
 sound/soc/pxa/spitz.c                              |    2 +-
 sound/soc/pxa/tosa.c                               |    4 +-
 sound/soc/pxa/z2.c                                 |    6 +-
 sound/soc/samsung/ac97.c                           |    4 +-
 sound/soc/samsung/h1940_uda1380.c                  |    4 +-
 sound/soc/samsung/i2s.c                            |    2 +-
 sound/soc/samsung/neo1973_wm8753.c                 |    4 +-
 sound/soc/samsung/pcm.c                            |    4 +-
 sound/soc/samsung/rx1950_uda1380.c                 |    2 +-
 sound/soc/samsung/s3c24xx-i2s.c                    |    2 +-
 sound/soc/samsung/s3c24xx_simtec.c                 |    2 +-
 sound/soc/samsung/s3c24xx_uda134x.c                |    2 +-
 sound/soc/samsung/spdif.c                          |    2 +-
 sound/soc/tegra/tegra30_ahub.c                     |    4 +-
 sound/soc/tegra/tegra_pcm.h                        |    2 +-
 sound/soc/tegra/tegra_wm8903.c                     |    2 +-
 sound/soc/ux500/mop500_ab8500.c                    |    2 +-
 sound/soc/ux500/ux500_msp_dai.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.h                    |    2 +-
 sound/soc/ux500/ux500_pcm.c                        |    2 +-
 3291 files changed, 48901 insertions(+), 48829 deletions(-)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_adc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_aic.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_dbgu.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pit.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pmc.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/at91_ramc.h
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rstc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtt.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_shdwc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_st.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_tc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_twi.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_emac.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_mc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_sdramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_ddrsdr.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_sdramc.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91x40.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at_hdmac.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/atmel-mci.h
 rename arch/arm/mach-at91/include/{mach => mach-at91}/board.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/cpu.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/debug-macro.S
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gpio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gsia18s.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/hardware.h
 rename arch/arm/mach-at91/include/{mach => mach-at91}/io.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/memory.h
 rename arch/arm/mach-at91/include/{mach => mach-at91}/stamp9g20.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/system_rev.h (100%)
 create mode 100644 arch/arm/mach-at91/include/mach-at91/timex.h
 create mode 100644 arch/arm/mach-at91/include/mach-at91/uncompress.h
 delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
 delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_smc.h
 delete mode 100644 arch/arm/mach-at91/include/mach/atmel-mci.h
 delete mode 100644 arch/arm/mach-at91/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-at91/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-at91/include/mach/memory.h
 delete mode 100644 arch/arm/mach-at91/include/mach/timex.h
 delete mode 100644 arch/arm/mach-at91/include/mach/uncompress.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_priv.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_addr.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_inline.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/dma.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/irqs.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/memory_settings.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timer.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timex.h (100%)
 create mode 100644 arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/autcpu12.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/clps711x.h (100%)
 create mode 100644 arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
 create mode 100644 arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
 create mode 100644 arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/irqs.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/memory.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/syspld.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/timex.h (100%)
 create mode 100644 arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
 delete mode 100644 arch/arm/mach-clps711x/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-clps711x/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-clps711x/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-clps711x/include/mach/uncompress.h
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/cns3xxx.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/pm.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/timex.h (100%)
 create mode 100644 arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/uncompress.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/aemif.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/asp.h
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/cdce949.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/clock.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/common.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cp_intc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpufreq.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpuidle.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/cputype.h
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/da8xx.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/ddr2.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/debug-macro.S
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/edma.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/entry-macro.S
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/gpio-davinci.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/hardware.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/i2c.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/irqs.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/keyscan.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mmc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mux.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/nand.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/pm.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/psc.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/serial.h
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/spi.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/sram.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/time.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/timex.h (100%)
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/tnetv107x.h
 create mode 100644 arch/arm/mach-davinci/include/mach-davinci/uncompress.h
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/usb.h (100%)
 delete mode 100644 arch/arm/mach-davinci/include/mach/asp.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/cdce949.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/cputype.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/da8xx.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-davinci/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-davinci/include/mach/gpio-davinci.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/serial.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/spi.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/tnetv107x.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-dove/include/mach-dove/bridge-regs.h
 create mode 100644 arch/arm/mach-dove/include/mach-dove/debug-macro.S
 rename arch/arm/mach-dove/include/{mach => mach-dove}/dove.h (100%)
 create mode 100644 arch/arm/mach-dove/include/mach-dove/entry-macro.S
 create mode 100644 arch/arm/mach-dove/include/mach-dove/gpio.h
 rename arch/arm/mach-dove/include/{mach => mach-dove}/hardware.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/io.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/irqs.h (100%)
 create mode 100644 arch/arm/mach-dove/include/mach-dove/pm.h
 rename arch/arm/mach-dove/include/{mach => mach-dove}/timex.h (100%)
 create mode 100644 arch/arm/mach-dove/include/mach-dove/uncompress.h
 delete mode 100644 arch/arm/mach-dove/include/mach/bridge-regs.h
 delete mode 100644 arch/arm/mach-dove/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-dove/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-dove/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-dove/include/mach/pm.h
 delete mode 100644 arch/arm/mach-dove/include/mach/uncompress.h
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/debug-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/entry-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/hardware.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/io.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/irqs.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/memory.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/timex.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/uncompress.h (100%)
 create mode 100644 arch/arm/mach-ep93xx/include/mach-ep93xx/debug-macro.S
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/dma.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx-regs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_keypad.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_spi.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/fb.h (100%)
 create mode 100644 arch/arm/mach-ep93xx/include/mach-ep93xx/gpio-ep93xx.h
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio.h (100%)
 create mode 100644 arch/arm/mach-ep93xx/include/mach-ep93xx/hardware.h
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/irqs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/memory.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/platform.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/timex.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ts72xx.h (100%)
 create mode 100644 arch/arm/mach-ep93xx/include/mach-ep93xx/uncompress.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/uncompress.h
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/cpufreq.h (100%)
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/debug-macro.S
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/dma.h
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/dwmci.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/gpio.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/hardware.h (100%)
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/irqs.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/map.h
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/memory.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/ohci.h (100%)
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/pm-core.h
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/pmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-audss.h (100%)
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-clock.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-gpio.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-irq.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-mct.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-mem.h
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/regs-pmu.h
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-usb-phy.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/sysmmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/timex.h (100%)
 create mode 100644 arch/arm/mach-exynos/include/mach-exynos/uncompress.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-exynos/include/mach/dma.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/map.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/pm-core.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-clock.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-gpio.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-irq.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mem.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-pmu.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-footbridge/include/mach-footbridge/debug-macro.S
 create mode 100644 arch/arm/mach-footbridge/include/mach-footbridge/entry-macro.S
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/hardware.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/io.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/irqs.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/isa-dma.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/memory.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/timex.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-footbridge/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-footbridge/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-gemini/include/mach-gemini/debug-macro.S
 create mode 100644 arch/arm/mach-gemini/include/mach-gemini/entry-macro.S
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/global_reg.h (100%)
 create mode 100644 arch/arm/mach-gemini/include/mach-gemini/gpio.h
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/hardware.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/irqs.h (100%)
 create mode 100644 arch/arm/mach-gemini/include/mach-gemini/system.h
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/timex.h (100%)
 create mode 100644 arch/arm/mach-gemini/include/mach-gemini/uncompress.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-gemini/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-gemini/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/system.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/uncompress.h
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/boards.h (100%)
 create mode 100644 arch/arm/mach-h720x/include/mach-h720x/debug-macro.S
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/entry-macro.S (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7201-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7202-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/hardware.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/irqs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/isa-dma.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/timex.h (100%)
 create mode 100644 arch/arm/mach-h720x/include/mach-h720x/uncompress.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-h720x/include/mach/uncompress.h
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/debug-macro.S (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/gpio.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/timex.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/3ds_debugboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lilly.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lite.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31moboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-pcm038.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/clock.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/common.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/cpuidle.h (100%)
 create mode 100644 arch/arm/mach-imx/include/mach-imx/debug-macro.S
 create mode 100644 arch/arm/mach-imx/include/mach-imx/devices-common.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/dma-mx1-mx2.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/dma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/esdhc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/eukrea-baseboards.h (100%)
 rename arch/arm/{mach-msm/include/mach => mach-imx/include/mach-imx}/gpio.h (100%)
 create mode 100644 arch/arm/mach-imx/include/mach-imx/hardware.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/i2c.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iim.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imx-uart.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imxfb.h (100%)
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx1.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx21.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx25.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx27.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx3.h (100%)
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx35.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx50.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx51.h
 create mode 100644 arch/arm/mach-imx/include/mach-imx/iomux-mx53.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ipu.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iram.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/irqs.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mmc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21-usbhost.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2_cam.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx31.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3fb.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx6q.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_ehci.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_nand.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/sdma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/spi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ssi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/timex.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ulpi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/usb.h (100%)
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/cm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/debug-macro.S (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/hardware.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/impd1.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/io.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/irqs.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/lm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/memory.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/platform.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/timex.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/uncompress.h (100%)
 create mode 100644 arch/arm/mach-iop13xx/include/mach-iop13xx/adma.h
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/debug-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/entry-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/hardware.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/io.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iop13xx.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iq81340.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/irqs.h (100%)
 create mode 100644 arch/arm/mach-iop13xx/include/mach-iop13xx/memory.h
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/msi.h (100%)
 create mode 100644 arch/arm/mach-iop13xx/include/mach-iop13xx/pci.h
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/time.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/timex.h (100%)
 create mode 100644 arch/arm/mach-iop13xx/include/mach-iop13xx/uncompress.h
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/adma.h
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/memory.h
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/pci.h
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/uncompress.h
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/adma.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-iop32x/include/mach-iop32x/entry-macro.S
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/glantank.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/gpio.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/hardware.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/io.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iop32x.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq31244.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq80321.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/irqs.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/n2100.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/time.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/timex.h (100%)
 create mode 100644 arch/arm/mach-iop32x/include/mach-iop32x/uncompress.h
 delete mode 100644 arch/arm/mach-iop32x/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-iop32x/include/mach/uncompress.h
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/adma.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-iop33x/include/mach-iop33x/entry-macro.S
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/gpio.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/hardware.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/io.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iop33x.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80331.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80332.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/irqs.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/time.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/timex.h (100%)
 create mode 100644 arch/arm/mach-iop33x/include/mach-iop33x/uncompress.h
 delete mode 100644 arch/arm/mach-iop33x/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-iop33x/include/mach/uncompress.h
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/cpu.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-ixp4xx/include/mach-ixp4xx/entry-macro.S
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/gpio.h (100%)
 create mode 100644 arch/arm/mach-ixp4xx/include/mach-ixp4xx/hardware.h
 create mode 100644 arch/arm/mach-ixp4xx/include/mach-ixp4xx/io.h
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/irqs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp46x_ts.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp4xx-regs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/npe.h (100%)
 create mode 100644 arch/arm/mach-ixp4xx/include/mach-ixp4xx/platform.h
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/qmgr.h (100%)
 create mode 100644 arch/arm/mach-ixp4xx/include/mach-ixp4xx/timex.h
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/udc.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/platform.h
 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/timex.h
 create mode 100644 arch/arm/mach-kirkwood/include/mach-kirkwood/bridge-regs.h
 create mode 100644 arch/arm/mach-kirkwood/include/mach-kirkwood/debug-macro.S
 create mode 100644 arch/arm/mach-kirkwood/include/mach-kirkwood/entry-macro.S
 create mode 100644 arch/arm/mach-kirkwood/include/mach-kirkwood/gpio.h
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/hardware.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/io.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/irqs.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/kirkwood.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-netxbig.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-ns2.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/timex.h (100%)
 create mode 100644 arch/arm/mach-kirkwood/include/mach-kirkwood/uncompress.h
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/bridge-regs.h
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-ks8695/include/mach-ks8695/debug-macro.S
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/devices.h (100%)
 create mode 100644 arch/arm/mach-ks8695/include/mach-ks8695/entry-macro.S
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio-ks8695.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/hardware.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/irqs.h (100%)
 create mode 100644 arch/arm/mach-ks8695/include/mach-ks8695/memory.h
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-hpna.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-irq.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-lan.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-mem.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-misc.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-pci.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-switch.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-sys.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-timer.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-uart.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-wan.h (100%)
 create mode 100644 arch/arm/mach-ks8695/include/mach-ks8695/timex.h
 create mode 100644 arch/arm/mach-ks8695/include/mach-ks8695/uncompress.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-ks8695/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-ks8695/include/mach/memory.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/timex.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/uncompress.h
 rename arch/arm/mach-l7200/include/{mach => mach-l7200}/debug-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/board.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-lpc32xx/include/mach-lpc32xx/entry-macro.S
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio-lpc32xx.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/hardware.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/irqs.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/platform.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/timex.h (100%)
 create mode 100644 arch/arm/mach-lpc32xx/include/mach-lpc32xx/uncompress.h
 delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-lpc32xx/include/mach/uncompress.h
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/addr-map.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/cputype.h (100%)
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/debug-macro.S
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/devices.h (100%)
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/dma.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/entry-macro.S
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/gpio.h
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/hardware.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/irqs.h (100%)
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/mfp-mmp2.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa168.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa910.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/mfp.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/mmp2.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/pm-mmp2.h
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-pxa910.h (100%)
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/pxa168.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/pxa910.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-apbc.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-apmu.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-icu.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-rtc.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-smc.h
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/regs-timers.h
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-usb.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/sram.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/teton_bga.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/timex.h (100%)
 create mode 100644 arch/arm/mach-mmp/include/mach-mmp/uncompress.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-mmp/include/mach/dma.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-mmp/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/mfp-mmp2.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/mfp-pxa168.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/mfp-pxa910.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/mfp.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/mmp2.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/pm-mmp2.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/pxa168.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/pxa910.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-apbc.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-apmu.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-icu.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-rtc.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-smc.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/regs-timers.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-msm/include/mach-msm/board.h
 rename arch/arm/mach-msm/include/{mach => mach-msm}/clk.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h (100%)
 create mode 100644 arch/arm/mach-msm/include/mach-msm/debug-macro.S
 create mode 100644 arch/arm/mach-msm/include/mach-msm/dma.h
 create mode 100644 arch/arm/mach-msm/include/mach-msm/entry-macro.S
 rename arch/arm/{mach-mxs/include/mach => mach-msm/include/mach-msm}/gpio.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/hardware.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu_hw-8xxx.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_fb.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_gpiomux.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_smd.h (100%)
 create mode 100644 arch/arm/mach-msm/include/mach-msm/sirc.h
 rename arch/arm/mach-msm/include/{mach => mach-msm}/system.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/timex.h (100%)
 create mode 100644 arch/arm/mach-msm/include/mach-msm/uncompress.h
 rename arch/arm/mach-msm/include/{mach => mach-msm}/vreg.h (100%)
 delete mode 100644 arch/arm/mach-msm/include/mach/board.h
 delete mode 100644 arch/arm/mach-msm/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-msm/include/mach/dma.h
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-msm/include/mach/sirc.h
 delete mode 100644 arch/arm/mach-msm/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-mv78xx0/include/mach-mv78xx0/bridge-regs.h
 create mode 100644 arch/arm/mach-mv78xx0/include/mach-mv78xx0/debug-macro.S
 create mode 100644 arch/arm/mach-mv78xx0/include/mach-mv78xx0/entry-macro.S
 create mode 100644 arch/arm/mach-mv78xx0/include/mach-mv78xx0/gpio.h
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/hardware.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/io.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/irqs.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/mv78xx0.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/timex.h (100%)
 create mode 100644 arch/arm/mach-mv78xx0/include/mach-mv78xx0/uncompress.h
 delete mode 100644 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
 delete mode 100644 arch/arm/mach-mv78xx0/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-mv78xx0/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-mv78xx0/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-mv78xx0/include/mach/uncompress.h
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/armada-370-xp.h (100%)
 create mode 100644 arch/arm/mach-mvebu/include/mach-mvebu/debug-macro.S
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/timex.h (100%)
 create mode 100644 arch/arm/mach-mvebu/include/mach-mvebu/uncompress.h
 delete mode 100644 arch/arm/mach-mvebu/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-mvebu/include/mach/uncompress.h
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/common.h (100%)
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/debug-macro.S
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/devices-common.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/digctl.h (100%)
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/entry-macro.S
 rename arch/arm/{mach-picoxcell/include/mach => mach-mxs/include/mach-mxs}/gpio.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/hardware.h (100%)
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/iomux-mx23.h
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/iomux-mx28.h
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/irqs.h (100%)
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/mx23.h
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/mx28.h
 create mode 100644 arch/arm/mach-mxs/include/mach-mxs/mxs.h
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/timex.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-mxs/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-mxs/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx23.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/iomux-mx28.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mx23.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mx28.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/mxs.h
 rename arch/arm/mach-netx/include/{mach => mach-netx}/debug-macro.S (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/eth.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/hardware.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/irqs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/netx-regs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/param.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/pfifo.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/timex.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/uncompress.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/xc.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-nomadik/include/mach-nomadik/fsmc.h
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/gpio.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/hardware.h (100%)
 create mode 100644 arch/arm/mach-nomadik/include/mach-nomadik/irqs.h
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/nand.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/timex.h (100%)
 create mode 100644 arch/arm/mach-nomadik/include/mach-nomadik/uncompress.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/fsmc.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/ams-delta-fiq.h
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/camera.h (100%)
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/debug-macro.S
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/entry-macro.S
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/gpio.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/hardware.h
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/io.h (100%)
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/irqs.h
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcd_dma.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcdc.h (100%)
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/memory.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/mtd-xip.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/smp.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/timex.h
 create mode 100644 arch/arm/mach-omap1/include/mach-omap1/uncompress.h
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/usb.h (100%)
 delete mode 100644 arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-omap1/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-omap1/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/memory.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/mtd-xip.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/smp.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/timex.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/uncompress.h
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/am35xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/barriers.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-rx51.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-zoom.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_wkup_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_wkup_44xx.h (100%)
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/debug-macro.S
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/gpio.h
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/hardware.h
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/id.h (100%)
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/irqs.h
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-secure.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-wakeupgen.h (100%)
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/smp.h
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/timex.h
 create mode 100644 arch/arm/mach-omap2/include/mach-omap2/uncompress.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-omap2/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/smp.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/timex.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/bridge-regs.h
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/debug-macro.S
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/entry-macro.S
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/gpio.h
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/hardware.h (100%)
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/io.h
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/irqs.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/orion5x.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/timex.h (100%)
 create mode 100644 arch/arm/mach-orion5x/include/mach-orion5x/uncompress.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/bridge-regs.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-orion5x/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-orion5x/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/io.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-picoxcell/include/mach-picoxcell/debug-macro.S
 rename arch/arm/{mach-realview/include/mach => mach-picoxcell/include/mach-picoxcell}/gpio.h (100%)
 create mode 100644 arch/arm/mach-picoxcell/include/mach-picoxcell/hardware.h
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/map.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/picoxcell_soc.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/timex.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/clock.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/debug-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/dma.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/entry-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/gpio-pnx4008.h (100%)
 create mode 100644 arch/arm/mach-pnx4008/include/mach-pnx4008/hardware.h
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irq.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irqs.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/param.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/platform.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/pm.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/timex.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/hardware.h
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/clkdev.h (100%)
 create mode 100644 arch/arm/mach-prima2/include/mach-prima2/debug-macro.S
 create mode 100644 arch/arm/mach-prima2/include/mach-prima2/entry-macro.S
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/gpio.h (100%)
 create mode 100644 arch/arm/mach-prima2/include/mach-prima2/hardware.h
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/irqs.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/map.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/timex.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/uart.h (100%)
 create mode 100644 arch/arm/mach-prima2/include/mach-prima2/uncompress.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-prima2/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/uncompress.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/addr-map.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/arcom-pcmcia.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/audio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/balloon3.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/bitfield.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/camera.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/colibri.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/corgi.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/csb726.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/dma.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-gpio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-irq.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/gpio.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/gumstix.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/h5000.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/hardware.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/hx4700.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irda.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irqs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/littleton.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lpd270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lubbock.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/magician.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mainstone.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa25x.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa27x.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa2xx.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa300.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa320.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa3xx.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa930.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mfp.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mioa701.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/mtd-xip.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mxm8x10.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/ohci.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palm27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmasoc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmld.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmt5.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmte2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtreo.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmz72.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pata_pxa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm027.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pcm990_baseboard.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/poodle.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x-udc.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa25x.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x-udc.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa27x.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa2xx-regs.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa300.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa320.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa3xx-regs.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-u2d.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa3xx.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa930.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_rotary.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_trkball.h (100%)
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxa95x.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/pxafb.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/regs-ac97.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/regs-lcd.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/regs-ost.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/regs-rtc.h
 create mode 100644 arch/arm/mach-pxa/include/mach-pxa/regs-u2d.h
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-uart.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/reset.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/sharpsl_pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/smemc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/spitz.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/timex.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa_bt.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/trizeps4.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/uncompress.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/viper.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/vpac270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zeus.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zylonite.h (100%)
 delete mode 100644 arch/arm/mach-pxa/include/mach/colibri.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/dma.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/h5000.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/magician.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mainstone.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa300.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa320.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa930.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mfp.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/mtd-xip.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa25x.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa27x.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa300.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa320.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa3xx.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa930.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxa95x.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/pxafb.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/regs-ac97.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/regs-lcd.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/regs-ost.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/regs-rtc.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/regs-u2d.h
 rename arch/arm/mach-realview/include/{mach => mach-realview}/barriers.h (100%)
 create mode 100644 arch/arm/mach-realview/include/mach-realview/board-eb.h
 create mode 100644 arch/arm/mach-realview/include/mach-realview/board-pb1176.h
 create mode 100644 arch/arm/mach-realview/include/mach-realview/board-pb11mp.h
 create mode 100644 arch/arm/mach-realview/include/mach-realview/board-pba8.h
 create mode 100644 arch/arm/mach-realview/include/mach-realview/board-pbx.h
 create mode 100644 arch/arm/mach-realview/include/mach-realview/clkdev.h
 rename arch/arm/mach-realview/include/{mach => mach-realview}/debug-macro.S (100%)
 rename arch/arm/{mach-tegra/include/mach => mach-realview/include/mach-realview}/gpio.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/hardware.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-eb.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb1176.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb11mp.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pba8.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pbx.h (100%)
 create mode 100644 arch/arm/mach-realview/include/mach-realview/irqs.h
 rename arch/arm/mach-realview/include/{mach => mach-realview}/memory.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/platform.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/timex.h (100%)
 create mode 100644 arch/arm/mach-realview/include/mach-realview/uncompress.h
 delete mode 100644 arch/arm/mach-realview/include/mach/board-eb.h
 delete mode 100644 arch/arm/mach-realview/include/mach/board-pb1176.h
 delete mode 100644 arch/arm/mach-realview/include/mach/board-pb11mp.h
 delete mode 100644 arch/arm/mach-realview/include/mach/board-pba8.h
 delete mode 100644 arch/arm/mach-realview/include/mach/board-pbx.h
 delete mode 100644 arch/arm/mach-realview/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-realview/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-realview/include/mach/uncompress.h
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/acornfb.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/debug-macro.S (100%)
 create mode 100644 arch/arm/mach-rpc/include/mach-rpc/entry-macro.S
 create mode 100644 arch/arm/mach-rpc/include/mach-rpc/hardware.h
 create mode 100644 arch/arm/mach-rpc/include/mach-rpc/io.h
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/irqs.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/isa-dma.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/memory.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/timex.h (100%)
 create mode 100644 arch/arm/mach-rpc/include/mach-rpc/uncompress.h
 delete mode 100644 arch/arm/mach-rpc/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-rpc/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-rpc/include/mach/io.h
 delete mode 100644 arch/arm/mach-rpc/include/mach/uncompress.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-map.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/debug-macro.S
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/dma.h
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/entry-macro.S
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/fb.h
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio-fns.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-nrs.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio-track.h
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio.h
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gta02.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940-latch.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/hardware.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/idle.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/io.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/irqs.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/leds-gpio.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/map.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/otom-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/pm-core.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-dsc.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/regs-gpio.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-lcd.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-power.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2443-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-sdi.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/tick.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/timex.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/uncompress.h
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-irq.h (100%)
 create mode 100644 arch/arm/mach-s3c24xx/include/mach-s3c24xx/vr1000-map.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/dma.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/fb.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio-track.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gta02.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/map.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/crag6410.h (100%)
 create mode 100644 arch/arm/mach-s3c64xx/include/mach-s3c64xx/debug-macro.S
 create mode 100644 arch/arm/mach-s3c64xx/include/mach-s3c64xx/dma.h
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/hardware.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/irqs.h (100%)
 create mode 100644 arch/arm/mach-s3c64xx/include/mach-s3c64xx/map.h
 create mode 100644 arch/arm/mach-s3c64xx/include/mach-s3c64xx/pm-core.h
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio-memport.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-modem.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-srom.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-sys.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-syscon-power.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/tick.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/timex.h (100%)
 create mode 100644 arch/arm/mach-s3c64xx/include/mach-s3c64xx/uncompress.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/dma.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/map.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/pm-core.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/debug-macro.S
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/dma.h
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/gpio.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/hardware.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/i2c.h (100%)
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/irqs.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/map.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/pm-core.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/regs-clock.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/regs-gpio.h
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/regs-irq.h
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/s5p64x0-clock.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/tick.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/timex.h (100%)
 create mode 100644 arch/arm/mach-s5p64x0/include/mach-s5p64x0/uncompress.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/dma.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/map.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/pm-core.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/regs-clock.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/regs-irq.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/debug-macro.S
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/dma.h
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/entry-macro.S (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/gpio.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/hardware.h (100%)
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/irqs.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/map.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/regs-clock.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/regs-gpio.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/regs-irq.h
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/tick.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/timex.h (100%)
 create mode 100644 arch/arm/mach-s5pc100/include/mach-s5pc100/uncompress.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/dma.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/map.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/regs-clock.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/regs-gpio.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/regs-irq.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/debug-macro.S
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/dma.h
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/gpio.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/hardware.h (100%)
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/irqs.h
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/map.h
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/memory.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/pm-core.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-audss.h (100%)
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/regs-clock.h
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/regs-gpio.h
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/regs-irq.h
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-sys.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/tick.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/timex.h (100%)
 create mode 100644 arch/arm/mach-s5pv210/include/mach-s5pv210/uncompress.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/dma.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/map.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/regs-clock.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/regs-gpio.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/regs-irq.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/uncompress.h
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1100.h (100%)
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/SA-1101.h
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1111.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/assabet.h (100%)
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/badge4.h
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/bitfield.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/cerf.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/collie.h (100%)
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/debug-macro.S
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/entry-macro.S (100%)
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/gpio.h
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/h3xxx.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/hardware.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/irqs.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/jornada720.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/lart.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/mcp.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/memory.h (100%)
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/mtd-xip.h
 create mode 100644 arch/arm/mach-sa1100/include/mach-sa1100/nanoengine.h
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/neponset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/reset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/shannon.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/simpad.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/timex.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1101.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/badge4.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-sa1100/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/mtd-xip.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/nanoengine.h
 rename arch/arm/mach-shark/include/{mach => mach-shark}/debug-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/entry-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/framebuffer.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/hardware.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/io.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/irqs.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/isa-dma.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/memory.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/timex.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/uncompress.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/clkdev.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/common.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma-register.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/emev2.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/gpio.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/hardware.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-ap4evb.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-mackerel.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/intc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/irqs.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/memory.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-ap4eb.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-mackerel.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/pm-rmobile.h (100%)
 create mode 100644 arch/arm/mach-shmobile/include/mach-shmobile/r8a7740.h
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7779.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi-sh7372.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7367.h (100%)
 create mode 100644 arch/arm/mach-shmobile/include/mach-shmobile/sh7372.h
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7377.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh73a0.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/system.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/timex.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/uncompress.h (100%)
 create mode 100644 arch/arm/mach-shmobile/include/mach-shmobile/zboot.h
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot_macros.h (100%)
 delete mode 100644 arch/arm/mach-shmobile/include/mach/r8a7740.h
 delete mode 100644 arch/arm/mach-shmobile/include/mach/sh7372.h
 delete mode 100644 arch/arm/mach-shmobile/include/mach/zboot.h
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/debug-macro.S (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/timex.h (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/uncompress.h (100%)
 create mode 100644 arch/arm/mach-spear13xx/include/mach-spear13xx/debug-macro.S
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/dma.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/generic.h (100%)
 create mode 100644 arch/arm/mach-spear13xx/include/mach-spear13xx/gpio.h
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/hardware.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/irqs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1310_misc_regs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1340_misc_regs.h (100%)
 create mode 100644 arch/arm/mach-spear13xx/include/mach-spear13xx/timex.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach-spear13xx/uncompress.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-spear3xx/include/mach-spear3xx/debug-macro.S
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/generic.h (100%)
 create mode 100644 arch/arm/mach-spear3xx/include/mach-spear3xx/gpio.h
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/hardware.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/irqs.h (100%)
 create mode 100644 arch/arm/mach-spear3xx/include/mach-spear3xx/misc_regs.h
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/spear.h (100%)
 create mode 100644 arch/arm/mach-spear3xx/include/mach-spear3xx/timex.h
 create mode 100644 arch/arm/mach-spear3xx/include/mach-spear3xx/uncompress.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/misc_regs.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-spear6xx/include/mach-spear6xx/debug-macro.S
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/generic.h (100%)
 create mode 100644 arch/arm/mach-spear6xx/include/mach-spear6xx/gpio.h
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/hardware.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/irqs.h (100%)
 create mode 100644 arch/arm/mach-spear6xx/include/mach-spear6xx/misc_regs.h
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/spear.h (100%)
 create mode 100644 arch/arm/mach-spear6xx/include/mach-spear6xx/timex.h
 create mode 100644 arch/arm/mach-spear6xx/include/mach-spear6xx/uncompress.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/misc_regs.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/clk.h (100%)
 create mode 100644 arch/arm/mach-tegra/include/mach-tegra/debug-macro.S
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/dma.h (100%)
 create mode 100644 arch/arm/mach-tegra/include/mach-tegra/gpio-tegra.h
 rename arch/arm/{mach-u300/include/mach => mach-tegra/include/mach-tegra}/gpio.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/io.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/iomap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irammap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irqs.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/kbc.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/pinconf-tegra.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/powergate.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/sdhci.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/smmu.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/suspend.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra-ahb.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra_wm8903_pdata.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/timex.h (100%)
 create mode 100644 arch/arm/mach-tegra/include/mach-tegra/uncompress.h
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/usb_phy.h (100%)
 delete mode 100644 arch/arm/mach-tegra/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-tegra/include/mach/gpio-tegra.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h
 rename arch/arm/mach-u300/include/{mach => mach-u300}/clkdev.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/coh901318.h (100%)
 create mode 100644 arch/arm/mach-u300/include/mach-u300/debug-macro.S
 rename arch/arm/mach-u300/include/{mach => mach-u300}/dma_channels.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/gpio-u300.h (100%)
 rename arch/arm/{mach-versatile/include/mach => mach-u300/include/mach-u300}/gpio.h (100%)
 create mode 100644 arch/arm/mach-u300/include/mach-u300/hardware.h
 rename arch/arm/mach-u300/include/{mach => mach-u300}/irqs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/platform.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/syscon.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/timex.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/u300-regs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-u300/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-u300/include/mach/hardware.h
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/crypto-ux500.h
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/db8500-regs.h (100%)
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/debug-macro.S
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/devices.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/gpio.h (100%)
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/hardware.h
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/id.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-board-mop500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-db8500.h (100%)
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/irqs.h
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/msp.h
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/setup.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/timex.h (100%)
 create mode 100644 arch/arm/mach-ux500/include/mach-ux500/uncompress.h
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/usb.h (100%)
 delete mode 100644 arch/arm/mach-ux500/include/mach/crypto-ux500.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/msp.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-versatile/include/mach-versatile/clkdev.h
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/debug-macro.S (100%)
 rename arch/arm/{mach-vexpress/include/mach => mach-versatile/include/mach-versatile}/gpio.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/hardware.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/io.h (100%)
 create mode 100644 arch/arm/mach-versatile/include/mach-versatile/irqs.h
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/platform.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/timex.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/uncompress.h (100%)
 delete mode 100644 arch/arm/mach-versatile/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/irqs.h
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/ct-ca9x4.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/debug-macro.S (100%)
 rename arch/arm/{mach-vt8500/include/mach => mach-vexpress/include/mach-vexpress}/gpio.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/hardware.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/irqs.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/motherboard.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/timex.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/debug-macro.S (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/entry-macro.S (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-vt8500/include/mach-vt8500}/gpio.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/hardware.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/i8042.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/restart.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/timex.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_regs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500fb.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_regs.h (100%)
 create mode 100644 arch/arm/mach-w90x900/include/mach-w90x900/entry-macro.S
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/fb.h (100%)
 create mode 100644 arch/arm/mach-w90x900/include/mach-w90x900/gpio.h
 create mode 100644 arch/arm/mach-w90x900/include/mach-w90x900/hardware.h
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/i2c.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/irqs.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/map.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/mfp.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/nuc900_spi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-clock.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ebi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-gcr.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-irq.h (100%)
 create mode 100644 arch/arm/mach-w90x900/include/mach-w90x900/regs-ldm.h
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-serial.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-timer.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-usb.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/timex.h (100%)
 create mode 100644 arch/arm/mach-w90x900/include/mach-w90x900/uncompress.h
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/w90p910_keypad.h (100%)
 delete mode 100644 arch/arm/mach-w90x900/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-w90x900/include/mach/gpio.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/regs-ldm.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-zynq/include/mach-zynq/clkdev.h
 create mode 100644 arch/arm/mach-zynq/include/mach-zynq/debug-macro.S
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/hardware.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/irqs.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/timex.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/uart.h (100%)
 create mode 100644 arch/arm/mach-zynq/include/mach-zynq/uncompress.h
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/zynq_soc.h (100%)
 delete mode 100644 arch/arm/mach-zynq/include/mach/clkdev.h
 delete mode 100644 arch/arm/mach-zynq/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-zynq/include/mach/uncompress.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/debug-macro.S
 delete mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/hardware.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx1.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx21.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx25.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx27.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx35.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx50.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/gpio-nomadik.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/mtu.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/pincfg.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ske.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ste_dma40.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/am33xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-ams-delta.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-sx1.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-voiceblue.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/board.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clkdev_omap.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clock.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/common.h
 create mode 100644 arch/arm/plat-omap/include/plat-omap/cpu.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dma-44xx.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/dma.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dmtimer.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/flash.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/fpga.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio-switch.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smc91x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smsc911x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/hardware.h
 create mode 100644 arch/arm/plat-omap/include/plat-omap/hdq1w.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/i2c.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/iommu.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iommu2.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iopgtable.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iovmm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irda.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs-44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/lcd_mipid.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/led.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mailbox.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcbsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcspi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/menelaus.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/mmc.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/multi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mux.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/nand.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-pm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-secure.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/omap-serial.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap1510.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap16xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap24xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap34xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap4-keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap54xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap7xx.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/omap_device.h
 create mode 100644 arch/arm/plat-omap/include/plat-omap/omap_hwmod.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/onenand.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/param.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/prcm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/remoteproc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sdrc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/serial.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/tc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/ti81xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/timex.h (100%)
 create mode 100644 arch/arm/plat-omap/include/plat-omap/uncompress.h
 create mode 100644 arch/arm/plat-omap/include/plat-omap/usb.h
 rename arch/arm/plat-omap/include/{plat => plat-omap}/voltage.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vrfb.h (100%)
 delete mode 100644 arch/arm/plat-omap/include/plat/board.h
 delete mode 100644 arch/arm/plat-omap/include/plat/common.h
 delete mode 100644 arch/arm/plat-omap/include/plat/cpu.h
 delete mode 100644 arch/arm/plat-omap/include/plat/dma.h
 delete mode 100644 arch/arm/plat-omap/include/plat/hardware.h
 delete mode 100644 arch/arm/plat-omap/include/plat/hdq1w.h
 delete mode 100644 arch/arm/plat-omap/include/plat/iommu.h
 delete mode 100644 arch/arm/plat-omap/include/plat/mmc.h
 delete mode 100644 arch/arm/plat-omap/include/plat/nand.h
 delete mode 100644 arch/arm/plat-omap/include/plat/omap-serial.h
 delete mode 100644 arch/arm/plat-omap/include/plat/omap_device.h
 delete mode 100644 arch/arm/plat-omap/include/plat/omap_hwmod.h
 delete mode 100644 arch/arm/plat-omap/include/plat/uncompress.h
 delete mode 100644 arch/arm/plat-omap/include/plat/usb.h
 rename arch/arm/plat-orion/include/{plat => plat-orion}/addr-map.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/audio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/cache-feroceon-l2.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/common.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/ehci-orion.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/gpio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/irq.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mpp.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mv_xor.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mvsdio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/orion_nand.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/pcie.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/time.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa27x_keypad.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa3xx_nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio-simtec.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/backlight.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/camport.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock-clksrc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/common-smdk.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/cpu-freq-core.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/debug-macro.S
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/devs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-ops.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/dma-pl330.h
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/dma-s3c24xx.h
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/dma.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ehci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fimc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fiq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg-helpers.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/gpio-core.h
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/gpio-fns.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/hwmon.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-uart.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-vic-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irqs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-base.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/map-s3c.h
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/map-s5p.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mfc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mipi_csis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/onenand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pll.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pm.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pwm-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ac97.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-dma.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/regs-fb-v4.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-irqtype.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-onenand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-rtc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-sdhci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-serial.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-srom.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-udc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-usb-hsotg-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-watchdog.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/rtc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2412.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2416.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2443.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c244x.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c64xx-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-time.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/sdhci.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ts.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/tv-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/udc.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/uncompress.h
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-control.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/wakeup-mask.h (100%)
 create mode 100644 arch/arm/plat-samsung/include/plat-samsung/watchdog-reset.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/cpu-freq-core.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/debug-macro.S
 delete mode 100644 arch/arm/plat-samsung/include/plat/dma-pl330.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/dma.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/gpio-core.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/gpio-fns.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/map-s3c.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/map-s5p.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/sdhci.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/uncompress.h
 delete mode 100644 arch/arm/plat-samsung/include/plat/watchdog-reset.h
 rename arch/arm/plat-spear/include/{plat => plat-spear}/debug-macro.S (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/gpio.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/keyboard.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/pl080.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/shirq.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/timex.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/uncompress.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clcd.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clock.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/fpga-irq.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/sched_clock.h (100%)
 create mode 100755 arch/arm/tools/gen-headers

-- 
1.7.10



From arnd at arndb.de  Tue Aug 21 11:12:13 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:12:13 -0000
Subject: [RFC 2/4] ARM: mass move of mach-*/plat-* header files
In-Reply-To: <1345561880-13231-1-git-send-email-arnd@arndb.de>
References: <1345561880-13231-1-git-send-email-arnd@arndb.de>
Message-ID: <1345561880-13231-3-git-send-email-arnd@arndb.de>

This moves all <mach/*.h> headers to <mach-*/*.h>, and all
<plat/*.h> headers to <plat-*/*.h>, as another step closer
to building kernels for multiple platforms combined.

A script to generate headers with the traditional names including
the headers from the new place is already there, so this move
should be completely transparent.

This patch was created fully automated by a script and
should be redone if the headers change. Note that the
plat-mxc headers move to mach-imx in the process because
they don't follow the <plat/foo.h> naming convention:

for i in arch/arm/mach-* ; do git mv $i/include/mach $i/include/${i##*/} ; done
for i in arch/arm/plat-* ; do git mv $i/include/plat $i/include/${i##*/} ; done
git mv arch/arm/plat-mxc/include/mach/*.h arch/arm/mach-imx/include/mach-imx/

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_adc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_aic.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_dbgu.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_matrix.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pio.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pit.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pmc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_ramc.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rstc.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtt.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_shdwc.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_st.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_tc.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_twi.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_emac.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_mc.h         |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_sdramc.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_ddrsdr.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_sdramc.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_smc.h          |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl_matrix.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5_matrix.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91x40.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at_hdmac.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/atmel-mci.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/board.h                 |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/cpu.h                   |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/debug-macro.S           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/gpio.h                  |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/gsia18s.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/hardware.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/io.h                    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/memory.h                |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/stamp9g20.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/system_rev.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/timex.h                 |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/uncompress.h            |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap.h         |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap_inline.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_def.h |    0
 .../mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_inline.h   |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_reg.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/ddrcReg.h     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_priv.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_reg.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/hw_cfg.h      |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/intcHw_reg.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_addr.h     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_io.h       |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_def.h   |    0
 .../arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_inline.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/tmrHw_reg.h   |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/dma.h             |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/entry-macro.S     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/hardware.h        |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/irqs.h            |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/memory_settings.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_nand.h        |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_umi.h         |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timer.h           |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timex.h           |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/uncompress.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/autcpu12.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/clps711x.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/debug-macro.S   |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/entry-macro.S   |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/hardware.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/irqs.h          |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/memory.h        |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/syspld.h        |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/timex.h         |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/uncompress.h    |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/cns3xxx.h         |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/debug-macro.S     |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/irqs.h            |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/pm.h              |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/timex.h           |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/uncompress.h      |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/aemif.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/asp.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cdce949.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/clock.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/common.h          |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cp_intc.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cpufreq.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cpuidle.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cputype.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/da8xx.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/ddr2.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/debug-macro.S     |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/edma.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/entry-macro.S     |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio-davinci.h    |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/hardware.h        |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/i2c.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/irqs.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/keyscan.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/mmc.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/mux.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/nand.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/pm.h              |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/psc.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/serial.h          |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/spi.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/sram.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/time.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/timex.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/tnetv107x.h       |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/uncompress.h      |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/usb.h             |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/bridge-regs.h           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/debug-macro.S           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/dove.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/entry-macro.S           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/gpio.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/hardware.h              |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/io.h                    |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/irqs.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/pm.h                    |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/timex.h                 |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/uncompress.h            |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/debug-macro.S     |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/entry-macro.S     |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/hardware.h        |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/io.h              |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/irqs.h            |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/memory.h          |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/timex.h           |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/uncompress.h      |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/debug-macro.S       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/dma.h               |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx-regs.h       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_keypad.h     |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_spi.h        |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/fb.h                |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio-ep93xx.h       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio.h              |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/hardware.h          |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/irqs.h              |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/memory.h            |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/platform.h          |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/timex.h             |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ts72xx.h            |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/uncompress.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/cpufreq.h           |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/debug-macro.S       |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/dma.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/dwmci.h             |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/gpio.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/hardware.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/irqs.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/map.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/memory.h            |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/ohci.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/pm-core.h           |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/pmu.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-audss.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-clock.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-gpio.h         |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-irq.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mct.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mem.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-pmu.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-usb-phy.h      |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/sysmmu.h            |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/timex.h             |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/uncompress.h        |    0
 .../mach-footbridge/include/{mach => mach-footbridge}/debug-macro.S    |    0
 .../mach-footbridge/include/{mach => mach-footbridge}/entry-macro.S    |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/hardware.h  |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/io.h        |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/irqs.h      |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/isa-dma.h   |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/memory.h    |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/timex.h     |    0
 .../arm/mach-footbridge/include/{mach => mach-footbridge}/uncompress.h |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/debug-macro.S       |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/entry-macro.S       |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/global_reg.h        |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/gpio.h              |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/hardware.h          |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/irqs.h              |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/system.h            |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/timex.h             |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/uncompress.h        |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/boards.h              |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/debug-macro.S         |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/entry-macro.S         |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/h7201-regs.h          |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/h7202-regs.h          |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/hardware.h            |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/irqs.h                |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/isa-dma.h             |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/timex.h               |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/uncompress.h          |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/debug-macro.S   |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/gpio.h          |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/timex.h         |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/uncompress.h    |    0
 .../include/mach => mach-imx/include/mach-imx}/3ds_debugboard.h        |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31lilly.h       |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31lite.h        |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31moboard.h     |    0
 .../include/mach => mach-imx/include/mach-imx}/board-pcm038.h          |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/clock.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/common.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/cpuidle.h |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/debug-macro.S |    0
 .../include/mach => mach-imx/include/mach-imx}/devices-common.h        |    0
 arch/arm/mach-imx/include/{mach => mach-imx}/dma-mx1-mx2.h             |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/dma.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/esdhc.h  |    0
 .../include/mach => mach-imx/include/mach-imx}/eukrea-baseboards.h     |    0
 arch/arm/{mach-msm/include/mach => mach-imx/include/mach-imx}/gpio.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/hardware.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/i2c.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iim.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/imx-uart.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imxfb.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx1.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx21.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx25.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx27.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx2x.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx3.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx35.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx50.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx51.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx53.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v1.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v3.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ipu.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iram.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/irqs.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mmc.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1_camera.h  |    0
 .../include/mach => mach-imx/include/mach-imx}/mx21-usbhost.h          |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx25.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx27.h   |    0
 .../arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2_cam.h |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2x.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx31.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx35.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3_camera.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3fb.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3x.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx50.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx51.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx53.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx6q.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_ehci.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_nand.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/sdma.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/spi.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ssi.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/timex.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ulpi.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/uncompress.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/usb.h    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/cm.h        |    0
 .../mach-integrator/include/{mach => mach-integrator}/debug-macro.S    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/hardware.h  |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/impd1.h     |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/io.h        |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/irqs.h      |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/lm.h        |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/memory.h    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/platform.h  |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/timex.h     |    0
 .../arm/mach-integrator/include/{mach => mach-integrator}/uncompress.h |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/adma.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/debug-macro.S     |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/entry-macro.S     |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/hardware.h        |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/io.h              |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iop13xx.h         |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iq81340.h         |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/irqs.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/memory.h          |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/msi.h             |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/pci.h             |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/time.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/timex.h           |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/uncompress.h      |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/adma.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/debug-macro.S       |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/entry-macro.S       |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/glantank.h          |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/gpio.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/hardware.h          |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/io.h                |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iop32x.h            |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq31244.h           |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq80321.h           |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/irqs.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/n2100.h             |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/time.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/timex.h             |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/uncompress.h        |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/adma.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/debug-macro.S       |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/entry-macro.S       |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/gpio.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/hardware.h          |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/io.h                |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iop33x.h            |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80331.h           |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80332.h           |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/irqs.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/time.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/timex.h             |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/uncompress.h        |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/cpu.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/debug-macro.S       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/entry-macro.S       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/gpio.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/hardware.h          |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/io.h                |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/irqs.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp46x_ts.h         |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp4xx-regs.h       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/npe.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/platform.h          |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/qmgr.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/timex.h             |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/udc.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/uncompress.h        |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/bridge-regs.h   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/debug-macro.S   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/entry-macro.S   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/gpio.h          |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/hardware.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/io.h            |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/irqs.h          |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/kirkwood.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-netxbig.h  |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-ns2.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/timex.h         |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/uncompress.h    |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/debug-macro.S       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/devices.h           |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/entry-macro.S       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio-ks8695.h       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio.h              |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/hardware.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/irqs.h              |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/memory.h            |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-gpio.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-hpna.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-irq.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-lan.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-mem.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-misc.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-pci.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-switch.h       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-sys.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-timer.h        |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-uart.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-wan.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/timex.h             |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/uncompress.h        |    0
 arch/arm/mach-l7200/include/{mach => mach-l7200}/debug-macro.S         |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/board.h           |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/debug-macro.S     |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/entry-macro.S     |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio-lpc32xx.h    |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio.h            |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/hardware.h        |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/irqs.h            |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/platform.h        |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/timex.h           |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/uncompress.h      |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/addr-map.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/cputype.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/debug-macro.S             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/devices.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/dma.h                     |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/entry-macro.S             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/gpio.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/hardware.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/irqs.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-mmp2.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa168.h              |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa910.h              |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp.h                     |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mmp2.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-mmp2.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-pxa910.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa168.h                  |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa910.h                  |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apbc.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apmu.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-icu.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-rtc.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-smc.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-timers.h             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-usb.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/sram.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/teton_bga.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/timex.h                   |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/uncompress.h              |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/board.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/clk.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/debug-macro.S             |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/dma.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/entry-macro.S             |    0
 arch/arm/{mach-mxs/include/mach => mach-msm/include/mach-msm}/gpio.h   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/hardware.h                |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/iommu.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/iommu_hw-8xxx.h           |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x00.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x30.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8960.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x50.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x60.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs.h                    |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_fb.h                  |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_gpiomux.h             |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x00.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x30.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8960.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x50.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x60.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_smd.h                 |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/sirc.h                    |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/system.h                  |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/timex.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/uncompress.h              |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/vreg.h                    |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/bridge-regs.h     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/debug-macro.S     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/entry-macro.S     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/gpio.h            |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/hardware.h        |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/io.h              |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/irqs.h            |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/mv78xx0.h         |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/timex.h           |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/uncompress.h      |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/armada-370-xp.h       |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/debug-macro.S         |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/timex.h               |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/uncompress.h          |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/common.h                  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/debug-macro.S             |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/devices-common.h          |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/digctl.h                  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/entry-macro.S             |    0
 .../{mach-picoxcell/include/mach => mach-mxs/include/mach-mxs}/gpio.h  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/hardware.h                |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx23.h              |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx28.h              |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux.h                   |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/irqs.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mx23.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mx28.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mxs.h                     |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/timex.h                   |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/uncompress.h              |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/debug-macro.S           |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/eth.h                   |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/hardware.h              |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/irqs.h                  |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/netx-regs.h             |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/param.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/pfifo.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/timex.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/uncompress.h            |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/xc.h                    |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/debug-macro.S     |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/fsmc.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/gpio.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/hardware.h        |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/irqs.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/nand.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/timex.h           |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/uncompress.h      |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/ams-delta-fiq.h       |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/camera.h              |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/debug-macro.S         |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/entry-macro.S         |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/gpio.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/hardware.h            |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/io.h                  |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/irqs.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/lcd_dma.h             |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/lcdc.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/memory.h              |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/mtd-xip.h             |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/smp.h                 |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/timex.h               |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/uncompress.h          |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/usb.h                 |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/am35xx.h              |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/barriers.h            |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/board-rx51.h          |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/board-zoom.h          |    0
 .../mach-omap2/include/{mach => mach-omap2}/ctrl_module_core_44xx.h    |    0
 .../include/{mach => mach-omap2}/ctrl_module_pad_core_44xx.h           |    0
 .../include/{mach => mach-omap2}/ctrl_module_pad_wkup_44xx.h           |    0
 .../mach-omap2/include/{mach => mach-omap2}/ctrl_module_wkup_44xx.h    |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/debug-macro.S         |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/gpio.h                |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/hardware.h            |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/id.h                  |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/irqs.h                |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-secure.h         |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-wakeupgen.h      |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/smp.h                 |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/timex.h               |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/uncompress.h          |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/bridge-regs.h     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/debug-macro.S     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/entry-macro.S     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/gpio.h            |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/hardware.h        |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/io.h              |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/irqs.h            |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/orion5x.h         |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/timex.h           |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/uncompress.h      |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/debug-macro.S |    0
 .../include/mach => mach-picoxcell/include/mach-picoxcell}/gpio.h      |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/hardware.h    |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/map.h         |    0
 .../mach-picoxcell/include/{mach => mach-picoxcell}/picoxcell_soc.h    |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/timex.h       |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/uncompress.h  |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/clock.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/debug-macro.S     |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/dma.h             |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/entry-macro.S     |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/gpio-pnx4008.h    |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/hardware.h        |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irq.h             |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irqs.h            |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/param.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/platform.h        |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/pm.h              |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/timex.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/uncompress.h      |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/clkdev.h            |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/debug-macro.S       |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/entry-macro.S       |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/gpio.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/hardware.h          |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/irqs.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/map.h               |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/timex.h             |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/uart.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/uncompress.h        |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/addr-map.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/arcom-pcmcia.h            |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/audio.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/balloon3.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/bitfield.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/camera.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/colibri.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/corgi.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/csb726.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/debug-macro.S             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/dma.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-gpio.h            |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-irq.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/gpio.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/gumstix.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/h5000.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/hardware.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/hx4700.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h                      |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/irda.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/irqs.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/littleton.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/lpd270.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/lubbock.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/magician.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mainstone.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa25x.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa27x.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa2xx.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa300.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa320.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa3xx.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa930.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mioa701.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h                     |    0
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 arch/arm/mach-pxa/include/{mach => mach-pxa}/mxm8x10.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/ohci.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palm27x.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmasoc.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmld.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmt5.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtc.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmte2.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtreo.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtx.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmz72.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pata_pxa.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm027.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm990_baseboard.h        |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h                      |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/poodle.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x-udc.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x-udc.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa2xx-regs.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa300.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa320.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-regs.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-u2d.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_rotary.h           |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_trkball.h          |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa95x.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxafb.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ac97.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-lcd.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ost.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-rtc.h                |    0
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 arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-uart.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/reset.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/sharpsl_pm.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/smemc.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/spitz.h                   |    0
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 arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa_bt.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/trizeps4.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/uncompress.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/viper.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/vpac270.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h                      |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/zeus.h                    |    0
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 arch/arm/mach-realview/include/{mach => mach-realview}/barriers.h      |    0
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 arch/arm/mach-realview/include/{mach => mach-realview}/board-pb1176.h  |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/board-pb11mp.h  |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/board-pba8.h    |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/board-pbx.h     |    0
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 arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb1176.h   |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb11mp.h   |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pba8.h     |    0
 arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pbx.h      |    0
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 arch/arm/mach-realview/include/{mach => mach-realview}/uncompress.h    |    0
 arch/arm/mach-rpc/include/{mach => mach-rpc}/acornfb.h                 |    0
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 arch/arm/mach-rpc/include/{mach => mach-rpc}/entry-macro.S             |    0
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 arch/arm/mach-rpc/include/{mach => mach-rpc}/io.h                      |    0
 arch/arm/mach-rpc/include/{mach => mach-rpc}/irqs.h                    |    0
 arch/arm/mach-rpc/include/{mach => mach-rpc}/isa-dma.h                 |    0
 arch/arm/mach-rpc/include/{mach => mach-rpc}/memory.h                  |    0
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 arch/arm/mach-rpc/include/{mach => mach-rpc}/uncompress.h              |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-cpld.h     |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-irq.h      |    0
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 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-cpld.h       |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-irq.h        |    0
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 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-nrs.h        |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-track.h      |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio.h            |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gta02.h           |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940-latch.h     |    0
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 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/leds-gpio.h       |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/map.h             |    0
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 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/otom-map.h        |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/pm-core.h         |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-clock.h      |    0
 arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-dsc.h        |    0
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 arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/crag6410.h        |    0
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 arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/dma.h             |    0
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 arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-irq.h        |    0
 arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-modem.h      |    0
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 arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/uncompress.h      |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/debug-macro.S     |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/dma.h             |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/gpio.h            |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/hardware.h        |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/i2c.h             |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/irqs.h            |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/map.h             |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/pm-core.h         |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-clock.h      |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-gpio.h       |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-irq.h        |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/s5p64x0-clock.h   |    0
 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/tick.h            |    0
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 arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/uncompress.h      |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/debug-macro.S     |    0
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 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/irqs.h            |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/map.h             |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-clock.h      |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-gpio.h       |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-irq.h        |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/tick.h            |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/timex.h           |    0
 arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/uncompress.h      |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/debug-macro.S     |    0
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 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/gpio.h            |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/hardware.h        |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/irqs.h            |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/map.h             |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/memory.h          |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/pm-core.h         |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-audss.h      |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-clock.h      |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-gpio.h       |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-irq.h        |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-sys.h        |    0
 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/tick.h            |    0
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 arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/uncompress.h      |    0
 arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1100.h           |    0
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 arch/arm/mach-sa1100/include/{mach => mach-sa1100}/nanoengine.h        |    0
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 arch/arm/mach-sa1100/include/{mach => mach-sa1100}/uncompress.h        |    0
 arch/arm/mach-shark/include/{mach => mach-shark}/debug-macro.S         |    0
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 arch/arm/mach-shark/include/{mach => mach-shark}/irqs.h                |    0
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 arch/arm/mach-shark/include/{mach => mach-shark}/memory.h              |    0
 arch/arm/mach-shark/include/{mach => mach-shark}/timex.h               |    0
 arch/arm/mach-shark/include/{mach => mach-shark}/uncompress.h          |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/clkdev.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/common.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma-register.h  |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma.h           |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/emev2.h         |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/gpio.h          |    0
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 .../mach-shmobile/include/{mach => mach-shmobile}/head-mackerel.txt    |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/intc.h          |    0
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 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/memory.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-ap4eb.h     |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-mackerel.h  |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc.h           |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/pm-rmobile.h    |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7740.h       |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7779.h       |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi-sh7372.h   |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi.h          |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7367.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7372.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7377.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh73a0.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/system.h        |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/timex.h         |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/uncompress.h    |    0
 arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot.h         |    0
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 arch/arm/mach-socfpga/include/{mach => mach-socfpga}/debug-macro.S     |    0
 arch/arm/mach-socfpga/include/{mach => mach-socfpga}/timex.h           |    0
 arch/arm/mach-socfpga/include/{mach => mach-socfpga}/uncompress.h      |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/debug-macro.S |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/dma.h         |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/generic.h     |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/gpio.h        |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/hardware.h    |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/irqs.h        |    0
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 .../include/{mach => mach-spear13xx}/spear1310_misc_regs.h             |    0
 .../include/{mach => mach-spear13xx}/spear1340_misc_regs.h             |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/timex.h       |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/uncompress.h  |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/debug-macro.S   |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/generic.h       |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/gpio.h          |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/hardware.h      |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/irqs.h          |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/misc_regs.h     |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/spear.h         |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/timex.h         |    0
 arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/uncompress.h    |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/debug-macro.S   |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/generic.h       |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/gpio.h          |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/hardware.h      |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/irqs.h          |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/misc_regs.h     |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/spear.h         |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/timex.h         |    0
 arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/uncompress.h    |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/clk.h                 |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/debug-macro.S         |    0
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 .../{mach-u300/include/mach => mach-tegra/include/mach-tegra}/gpio.h   |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/io.h                  |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/iomap.h               |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/irammap.h             |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/irqs.h                |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/kbc.h                 |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/pinconf-tegra.h       |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/powergate.h           |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/sdhci.h               |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/smmu.h                |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/suspend.h             |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra-ahb.h           |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra_wm8903_pdata.h  |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/timex.h               |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/uncompress.h          |    0
 arch/arm/mach-tegra/include/{mach => mach-tegra}/usb_phy.h             |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/clkdev.h                |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/coh901318.h             |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/debug-macro.S           |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/dma_channels.h          |    0
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 .../include/mach => mach-u300/include/mach-u300}/gpio.h                |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/hardware.h              |    0
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 arch/arm/mach-u300/include/{mach => mach-u300}/platform.h              |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/syscon.h                |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/timex.h                 |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/u300-regs.h             |    0
 arch/arm/mach-u300/include/{mach => mach-u300}/uncompress.h            |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/crypto-ux500.h        |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/db8500-regs.h         |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/debug-macro.S         |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/devices.h             |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/gpio.h                |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/hardware.h            |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/id.h                  |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-board-mop500.h   |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-db8500.h         |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs.h                |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/msp.h                 |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/setup.h               |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/timex.h               |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/uncompress.h          |    0
 arch/arm/mach-ux500/include/{mach => mach-ux500}/usb.h                 |    0
 arch/arm/mach-versatile/include/{mach => mach-versatile}/clkdev.h      |    0
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 .../include/mach => mach-versatile/include/mach-versatile}/gpio.h      |    0
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 arch/arm/mach-versatile/include/{mach => mach-versatile}/platform.h    |    0
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 arch/arm/mach-versatile/include/{mach => mach-versatile}/uncompress.h  |    0
 arch/arm/mach-vexpress/include/{mach => mach-vexpress}/ct-ca9x4.h      |    0
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 .../include/mach => mach-vexpress/include/mach-vexpress}/gpio.h        |    0
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 arch/arm/mach-vexpress/include/{mach => mach-vexpress}/uncompress.h    |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/debug-macro.S       |    0
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 .../{plat-mxc/include/mach => mach-vt8500/include/mach-vt8500}/gpio.h  |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/hardware.h          |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/i8042.h             |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/irqs.h              |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/restart.h           |    0
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 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/uncompress.h        |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_irqs.h       |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_regs.h       |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500fb.h          |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_irqs.h       |    0
 arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_regs.h       |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/entry-macro.S     |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/fb.h              |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/gpio.h            |    0
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 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/i2c.h             |    0
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 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/map.h             |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/mfp.h             |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/nuc900_spi.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-clock.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ebi.h        |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-gcr.h        |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-irq.h        |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ldm.h        |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-serial.h     |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-timer.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-usb.h        |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/timex.h           |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/uncompress.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/w90p910_keypad.h  |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/clkdev.h                |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/debug-macro.S           |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/hardware.h              |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/irqs.h                  |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/timex.h                 |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/uart.h                  |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/uncompress.h            |    0
 arch/arm/mach-zynq/include/{mach => mach-zynq}/zynq_soc.h              |    0
 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/gpio-nomadik.h    |    0
 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/mtu.h             |    0
 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/pincfg.h          |    0
 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ske.h             |    0
 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ste_dma40.h       |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/am33xx.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/board-ams-delta.h       |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/board-sx1.h             |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/board-voiceblue.h       |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/board.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/clkdev_omap.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/clock.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/common.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/cpu.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/dma-44xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/dma.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/dmtimer.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/dsp.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/flash.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/fpga.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/gpio-switch.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/gpio.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smc91x.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smsc911x.h         |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/gpmc.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/hardware.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/hdq1w.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/i2c.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/iommu.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/iommu2.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/iopgtable.h             |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/iovmm.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/irda.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/irqs-44xx.h             |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/irqs.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/keypad.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/l3_2xxx.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/l3_3xxx.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/l4_2xxx.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/l4_3xxx.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/lcd_mipid.h             |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/led.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/mailbox.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/mcbsp.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/mcspi.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/menelaus.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/mmc.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/multi.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/mux.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/nand.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap-pm.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap-secure.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap-serial.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap1510.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap16xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap24xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap34xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap4-keypad.h          |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap44xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap54xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap7xx.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap_device.h           |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap_hwmod.h            |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/onenand.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/param.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/prcm.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/remoteproc.h            |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/sdrc.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/serial.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/sram.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/tc.h                    |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/ti81xx.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/timex.h                 |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/uncompress.h            |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/usb.h                   |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/voltage.h               |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/vram.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/vrfb.h                  |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/addr-map.h            |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/audio.h               |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/cache-feroceon-l2.h   |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/common.h              |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/ehci-orion.h          |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/gpio.h                |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/irq.h                 |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/mpp.h                 |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/mv_xor.h              |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/mvsdio.h              |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/orion_nand.h          |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/pcie.h                |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/time.h                |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h                     |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h                     |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa27x_keypad.h           |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa3xx_nand.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/adc-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/adc.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ata-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ata.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/audio-simtec.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/audio.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/backlight.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/camport.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/clock-clksrc.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/clock.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/common-smdk.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq-core.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/debug-macro.S     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/devs.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-ops.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-pl330.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-s3c24xx.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ehci.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-core.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-s3c2410.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fimc-core.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fiq.h             |    0
 .../arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg-helpers.h |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-core.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-fns.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/hwmon.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/iic-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/iic.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-uart.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-vic-timer.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irqs.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad-core.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad.h          |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-base.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s3c.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s5p.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mci.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mfc.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mipi_csis.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/nand-core.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/nand.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/onenand-core.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pll.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pm.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pwm-clock.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ac97.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-adc.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ata.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-dma.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb-v4.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iic.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iis.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-irqtype.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-nand.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-onenand.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-rtc.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-sdhci.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-serial.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-spi.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-srom.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-timer.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-udc.h        |    0
 .../plat-samsung/include/{plat => plat-samsung}/regs-usb-hsotg-phy.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-watchdog.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/rtc-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2410.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2412.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2416.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2443.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c244x.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c64xx-spi.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-clock.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-time.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/sdhci.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ts.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/tv-core.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/udc.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/uncompress.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-control.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-phy.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/wakeup-mask.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/watchdog-reset.h  |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/debug-macro.S         |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/gpio.h                |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/keyboard.h            |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/pl080.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/shirq.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/timex.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/uncompress.h          |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/clcd.h        |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/clock.h       |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/fpga-irq.h    |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/sched_clock.h |    0
 1201 files changed, 0 insertions(+), 0 deletions(-)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_adc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_aic.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_dbgu.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pit.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pmc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_ramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rstc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtt.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_shdwc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_st.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_tc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_twi.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_emac.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_mc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_sdramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_ddrsdr.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_sdramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_smc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91x40.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at_hdmac.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/atmel-mci.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/board.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/cpu.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/debug-macro.S (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gpio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gsia18s.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/hardware.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/io.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/memory.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/stamp9g20.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/system_rev.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/timex.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/uncompress.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_def.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/ddrcReg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_priv.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/hw_cfg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/intcHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_addr.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_io.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_def.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/tmrHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/dma.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/entry-macro.S (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/hardware.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/irqs.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/memory_settings.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_nand.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_umi.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timer.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timex.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/uncompress.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/autcpu12.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/clps711x.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/debug-macro.S (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/entry-macro.S (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/hardware.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/irqs.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/memory.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/syspld.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/timex.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/uncompress.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/cns3xxx.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/debug-macro.S (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/irqs.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/pm.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/timex.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/uncompress.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/aemif.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/asp.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cdce949.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/clock.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/common.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cp_intc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpufreq.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpuidle.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cputype.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/da8xx.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/ddr2.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/debug-macro.S (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/edma.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/entry-macro.S (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio-davinci.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/hardware.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/i2c.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/irqs.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/keyscan.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mmc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mux.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/nand.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/pm.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/psc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/serial.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/spi.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/sram.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/time.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/timex.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/tnetv107x.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/uncompress.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/usb.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/bridge-regs.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/debug-macro.S (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/dove.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/entry-macro.S (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/gpio.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/hardware.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/io.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/irqs.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/pm.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/timex.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/uncompress.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/debug-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/entry-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/hardware.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/io.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/irqs.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/memory.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/timex.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/uncompress.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/debug-macro.S (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/dma.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx-regs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_keypad.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_spi.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/fb.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio-ep93xx.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/hardware.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/irqs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/memory.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/platform.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/timex.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ts72xx.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/uncompress.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/cpufreq.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/debug-macro.S (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/dma.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/dwmci.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/gpio.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/hardware.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/irqs.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/map.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/memory.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/ohci.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/pm-core.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/pmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-audss.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-clock.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-gpio.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-irq.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mct.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mem.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-pmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-usb-phy.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/sysmmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/timex.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/uncompress.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/debug-macro.S (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/entry-macro.S (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/hardware.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/io.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/irqs.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/isa-dma.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/memory.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/timex.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/uncompress.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/debug-macro.S (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/entry-macro.S (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/global_reg.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/gpio.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/hardware.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/irqs.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/system.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/timex.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/uncompress.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/boards.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/debug-macro.S (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/entry-macro.S (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7201-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7202-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/hardware.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/irqs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/isa-dma.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/timex.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/uncompress.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/debug-macro.S (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/gpio.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/timex.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/3ds_debugboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lilly.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lite.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31moboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-pcm038.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/clock.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/common.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/cpuidle.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/debug-macro.S (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/devices-common.h (100%)
 rename arch/arm/mach-imx/include/{mach => mach-imx}/dma-mx1-mx2.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/dma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/esdhc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/eukrea-baseboards.h (100%)
 rename arch/arm/{mach-msm/include/mach => mach-imx/include/mach-imx}/gpio.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/hardware.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/i2c.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iim.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imx-uart.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imxfb.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ipu.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iram.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/irqs.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mmc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21-usbhost.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2_cam.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx31.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3fb.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx6q.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_ehci.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_nand.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/sdma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/spi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ssi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/timex.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ulpi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/usb.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/cm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/debug-macro.S (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/hardware.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/impd1.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/io.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/irqs.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/lm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/memory.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/platform.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/timex.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/uncompress.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/adma.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/debug-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/entry-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/hardware.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/io.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iop13xx.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iq81340.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/irqs.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/memory.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/msi.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/pci.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/time.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/timex.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/uncompress.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/adma.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/debug-macro.S (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/entry-macro.S (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/glantank.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/gpio.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/hardware.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/io.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iop32x.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq31244.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq80321.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/irqs.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/n2100.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/time.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/timex.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/uncompress.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/adma.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/debug-macro.S (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/entry-macro.S (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/gpio.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/hardware.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/io.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iop33x.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80331.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80332.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/irqs.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/time.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/timex.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/uncompress.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/cpu.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/debug-macro.S (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/entry-macro.S (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/gpio.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/hardware.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/io.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/irqs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp46x_ts.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp4xx-regs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/npe.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/platform.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/qmgr.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/timex.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/udc.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/uncompress.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/bridge-regs.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/debug-macro.S (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/entry-macro.S (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/gpio.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/hardware.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/io.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/irqs.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/kirkwood.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-netxbig.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-ns2.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/timex.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/uncompress.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/debug-macro.S (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/devices.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/entry-macro.S (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio-ks8695.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/hardware.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/irqs.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/memory.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-hpna.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-irq.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-lan.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-mem.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-misc.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-pci.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-switch.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-sys.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-timer.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-uart.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-wan.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/timex.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/uncompress.h (100%)
 rename arch/arm/mach-l7200/include/{mach => mach-l7200}/debug-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/board.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/debug-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/entry-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio-lpc32xx.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/hardware.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/irqs.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/platform.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/timex.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/uncompress.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/addr-map.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/cputype.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/debug-macro.S (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/devices.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/dma.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/entry-macro.S (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/gpio.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/hardware.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/irqs.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa168.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa168.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apbc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apmu.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-icu.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-rtc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-smc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-timers.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-usb.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/sram.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/teton_bga.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/timex.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/uncompress.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/board.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/clk.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/debug-macro.S (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/dma.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/entry-macro.S (100%)
 rename arch/arm/{mach-mxs/include/mach => mach-msm/include/mach-msm}/gpio.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/hardware.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu_hw-8xxx.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_fb.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_gpiomux.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_smd.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/sirc.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/system.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/timex.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/uncompress.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/vreg.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/bridge-regs.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/debug-macro.S (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/entry-macro.S (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/gpio.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/hardware.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/io.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/irqs.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/mv78xx0.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/timex.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/uncompress.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/armada-370-xp.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/debug-macro.S (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/timex.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/uncompress.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/common.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/debug-macro.S (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/devices-common.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/digctl.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/entry-macro.S (100%)
 rename arch/arm/{mach-picoxcell/include/mach => mach-mxs/include/mach-mxs}/gpio.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/hardware.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx23.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx28.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/irqs.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mx23.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mx28.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mxs.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/timex.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/uncompress.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/debug-macro.S (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/eth.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/hardware.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/irqs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/netx-regs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/param.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/pfifo.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/timex.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/uncompress.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/xc.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/debug-macro.S (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/fsmc.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/gpio.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/hardware.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/irqs.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/nand.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/timex.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/uncompress.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/ams-delta-fiq.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/camera.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/debug-macro.S (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/entry-macro.S (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/gpio.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/hardware.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/io.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/irqs.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcd_dma.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcdc.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/memory.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/mtd-xip.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/smp.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/timex.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/uncompress.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/usb.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/am35xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/barriers.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-rx51.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-zoom.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_wkup_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_wkup_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/debug-macro.S (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/gpio.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/hardware.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/id.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/irqs.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-secure.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-wakeupgen.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/smp.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/timex.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/uncompress.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/bridge-regs.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/debug-macro.S (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/entry-macro.S (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/gpio.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/hardware.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/io.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/irqs.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/orion5x.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/timex.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/uncompress.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/debug-macro.S (100%)
 rename arch/arm/{mach-realview/include/mach => mach-picoxcell/include/mach-picoxcell}/gpio.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/hardware.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/map.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/picoxcell_soc.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/timex.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/uncompress.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/clock.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/debug-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/dma.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/entry-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/gpio-pnx4008.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/hardware.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irq.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irqs.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/param.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/platform.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/pm.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/timex.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/uncompress.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/clkdev.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/debug-macro.S (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/entry-macro.S (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/gpio.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/hardware.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/irqs.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/map.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/timex.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/uart.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/uncompress.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/addr-map.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/arcom-pcmcia.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/audio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/balloon3.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/bitfield.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/camera.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/colibri.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/corgi.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/csb726.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/debug-macro.S (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/dma.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-gpio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-irq.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/gpio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/gumstix.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/h5000.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/hardware.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/hx4700.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irda.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irqs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/littleton.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lpd270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lubbock.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/magician.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mainstone.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa25x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa2xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa300.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa320.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa3xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa930.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mioa701.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mtd-xip.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mxm8x10.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/ohci.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palm27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmasoc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmld.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmt5.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmte2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtreo.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmz72.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pata_pxa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm027.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm990_baseboard.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/poodle.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x-udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x-udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa2xx-regs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa300.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa320.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-regs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-u2d.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_rotary.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_trkball.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa95x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxafb.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ac97.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-lcd.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ost.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-rtc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-u2d.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-uart.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/reset.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/sharpsl_pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/smemc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/spitz.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/timex.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa_bt.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/trizeps4.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/uncompress.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/viper.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/vpac270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zeus.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zylonite.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/barriers.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-eb.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pb1176.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pb11mp.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pba8.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pbx.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/clkdev.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/debug-macro.S (100%)
 rename arch/arm/{mach-tegra/include/mach => mach-realview/include/mach-realview}/gpio.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/hardware.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-eb.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb1176.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb11mp.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pba8.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pbx.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/memory.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/platform.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/timex.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/uncompress.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/acornfb.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/debug-macro.S (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/entry-macro.S (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/hardware.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/io.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/irqs.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/isa-dma.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/memory.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/timex.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/uncompress.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/debug-macro.S (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/dma.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/entry-macro.S (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/fb.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-fns.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-nrs.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-track.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gta02.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940-latch.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/hardware.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/idle.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/io.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/irqs.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/leds-gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/otom-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/pm-core.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-dsc.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-lcd.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-power.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2443-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-sdi.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/tick.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/timex.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/uncompress.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-map.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/crag6410.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/debug-macro.S (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/dma.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/hardware.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/irqs.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/map.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/pm-core.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio-memport.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-modem.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-srom.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-sys.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-syscon-power.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/tick.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/timex.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/uncompress.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/debug-macro.S (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/dma.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/gpio.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/hardware.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/i2c.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/irqs.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/map.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/pm-core.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-clock.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-gpio.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-irq.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/s5p64x0-clock.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/tick.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/timex.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/uncompress.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/debug-macro.S (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/dma.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/entry-macro.S (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/gpio.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/hardware.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/irqs.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/map.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-clock.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-gpio.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-irq.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/tick.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/timex.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/uncompress.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/debug-macro.S (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/dma.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/gpio.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/hardware.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/irqs.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/map.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/memory.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/pm-core.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-audss.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-clock.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-gpio.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-irq.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-sys.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/tick.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/timex.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/uncompress.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1100.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1101.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1111.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/assabet.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/badge4.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/bitfield.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/cerf.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/collie.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/debug-macro.S (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/entry-macro.S (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/gpio.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/h3xxx.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/hardware.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/irqs.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/jornada720.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/lart.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/mcp.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/memory.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/mtd-xip.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/nanoengine.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/neponset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/reset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/shannon.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/simpad.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/timex.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/uncompress.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/debug-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/entry-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/framebuffer.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/hardware.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/io.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/irqs.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/isa-dma.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/memory.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/timex.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/uncompress.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/clkdev.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/common.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma-register.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/emev2.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/gpio.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/hardware.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-ap4evb.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-mackerel.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/intc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/irqs.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/memory.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-ap4eb.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-mackerel.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/pm-rmobile.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7740.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7779.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi-sh7372.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7367.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7372.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7377.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh73a0.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/system.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/timex.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/uncompress.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot_macros.h (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/debug-macro.S (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/timex.h (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/uncompress.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/dma.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/generic.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/gpio.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/hardware.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/irqs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1310_misc_regs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1340_misc_regs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/timex.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/uncompress.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/generic.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/gpio.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/hardware.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/irqs.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/misc_regs.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/spear.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/timex.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/uncompress.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/generic.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/gpio.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/hardware.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/irqs.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/misc_regs.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/spear.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/timex.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/uncompress.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/clk.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/debug-macro.S (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/dma.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/gpio-tegra.h (100%)
 rename arch/arm/{mach-u300/include/mach => mach-tegra/include/mach-tegra}/gpio.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/io.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/iomap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irammap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irqs.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/kbc.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/pinconf-tegra.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/powergate.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/sdhci.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/smmu.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/suspend.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra-ahb.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra_wm8903_pdata.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/timex.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/uncompress.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/usb_phy.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/clkdev.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/coh901318.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/debug-macro.S (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/dma_channels.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/gpio-u300.h (100%)
 rename arch/arm/{mach-versatile/include/mach => mach-u300/include/mach-u300}/gpio.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/hardware.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/irqs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/platform.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/syscon.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/timex.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/u300-regs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/uncompress.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/crypto-ux500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/db8500-regs.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/debug-macro.S (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/devices.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/gpio.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/hardware.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/id.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-board-mop500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-db8500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/msp.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/setup.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/timex.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/uncompress.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/usb.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/clkdev.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/debug-macro.S (100%)
 rename arch/arm/{mach-vexpress/include/mach => mach-versatile/include/mach-versatile}/gpio.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/hardware.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/io.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/irqs.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/platform.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/timex.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/uncompress.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/ct-ca9x4.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/debug-macro.S (100%)
 rename arch/arm/{mach-vt8500/include/mach => mach-vexpress/include/mach-vexpress}/gpio.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/hardware.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/irqs.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/motherboard.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/timex.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/debug-macro.S (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/entry-macro.S (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-vt8500/include/mach-vt8500}/gpio.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/hardware.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/i8042.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/restart.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/timex.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_regs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500fb.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_regs.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/entry-macro.S (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/fb.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/gpio.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/hardware.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/i2c.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/irqs.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/map.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/mfp.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/nuc900_spi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-clock.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ebi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-gcr.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-irq.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ldm.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-serial.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-timer.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-usb.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/timex.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/uncompress.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/w90p910_keypad.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/clkdev.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/debug-macro.S (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/hardware.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/irqs.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/timex.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/uart.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/uncompress.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/zynq_soc.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/gpio-nomadik.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/mtu.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/pincfg.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ske.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ste_dma40.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/am33xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-ams-delta.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-sx1.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-voiceblue.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clkdev_omap.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clock.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/common.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/cpu.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dma-44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dma.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dmtimer.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/flash.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/fpga.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio-switch.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smc91x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smsc911x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/hardware.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/hdq1w.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/i2c.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iommu.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iommu2.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iopgtable.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iovmm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irda.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs-44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/lcd_mipid.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/led.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mailbox.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcbsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcspi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/menelaus.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mmc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/multi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mux.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/nand.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-pm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-secure.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-serial.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap1510.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap16xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap24xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap34xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap4-keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap54xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap7xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap_device.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap_hwmod.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/onenand.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/param.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/prcm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/remoteproc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sdrc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/serial.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/tc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/ti81xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/timex.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/uncompress.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/usb.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/voltage.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vrfb.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/addr-map.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/audio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/cache-feroceon-l2.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/common.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/ehci-orion.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/gpio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/irq.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mpp.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mv_xor.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mvsdio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/orion_nand.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/pcie.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/time.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa27x_keypad.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa3xx_nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio-simtec.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/backlight.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/camport.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock-clksrc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/common-smdk.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/debug-macro.S (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/devs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-ops.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-pl330.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-s3c24xx.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ehci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fimc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fiq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg-helpers.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-fns.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/hwmon.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-uart.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-vic-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irqs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-base.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s3c.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s5p.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mfc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mipi_csis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/onenand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pll.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pm.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pwm-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ac97.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-dma.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb-v4.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-irqtype.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-onenand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-rtc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-sdhci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-serial.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-srom.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-udc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-usb-hsotg-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-watchdog.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/rtc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2412.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2416.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2443.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c244x.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c64xx-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-time.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/sdhci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ts.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/tv-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/udc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/uncompress.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-control.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/wakeup-mask.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/watchdog-reset.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/debug-macro.S (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/gpio.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/keyboard.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/pl080.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/shirq.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/timex.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/uncompress.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clcd.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clock.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/fpga-irq.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/sched_clock.h (100%)

diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach-at91/at91_adc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_adc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_adc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach-at91/at91_aic.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_aic.h
rename to arch/arm/mach-at91/include/mach-at91/at91_aic.h
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_dbgu.h
rename to arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach-at91/at91_matrix.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_matrix.h
rename to arch/arm/mach-at91/include/mach-at91/at91_matrix.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach-at91/at91_pio.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pio.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pio.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach-at91/at91_pit.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pit.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pit.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach-at91/at91_pmc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pmc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_ramc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_ramc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach-at91/at91_rstc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rstc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rstc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach-at91/at91_rtc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach-at91/at91_rtt.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtt.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtt.h
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_shdwc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach-at91/at91_st.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_st.h
rename to arch/arm/mach-at91/include/mach-at91/at91_st.h
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach-at91/at91_tc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_tc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_tc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach-at91/at91_twi.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_twi.h
rename to arch/arm/mach-at91/include/mach-at91/at91_twi.h

Cut here for review purposes. None of the other file renames have any
other changes, so there is no point spamming the mailing lists with
this. The full patch is available at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=62dd65e1ac307d2ba15f31cc2f754b8e348055c7


From arnd at arndb.de  Tue Aug 21 11:58:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:58:56 -0000
Subject: [RFC 1/4] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
In-Reply-To: <1345564724-14466-1-git-send-email-arnd@arndb.de>
References: <1345564724-14466-1-git-send-email-arnd@arndb.de>
Message-ID: <1345564724-14466-2-git-send-email-arnd@arndb.de>

This is an attempt to simplify the duplicate header problem for
multiplatform kernels, in multiple steps:

1. (this patch)
   for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
   generate a arch/arm/include/generated/mach/*.h file at build time,
   same for plat-*.

2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
   arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
   arch/arm/plat-${PLAT}/include/plat/*.h to
   arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h

3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
   in all files where ${MACHINE} is known.

4. ...

5. Revert this patch again.

We can apply this patch at any time, and do step 2 at the end
of the next merge window to minimize the potential for conflicts.
We will also still need to deal with any inclusion of a mach/*
file, but out of the 6355 ones we have today, I expect only a
few hundred to remain after step 3 and they will be much easier
to spot.

I've picked the format <mach-foo/bar.h> to get a unique name because
it matches the directory name under arch/arm, but other names
would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
have been suggested previously.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Makefile          |    1 +
 arch/arm/tools/Makefile    |    5 ++++
 arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100755 arch/arm/tools/gen-headers

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..761b077 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -274,6 +274,7 @@ boot := arch/arm/boot
 
 archprepare:
 	$(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
+	$(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
 
 # Convert bzImage to zImage
 bzImage: zImage
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 635cb18..6e18ca9 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
 	@echo '  Generating $@'
 	@mkdir -p $(dir $@)
 	$(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
+
+gen_headers:
+	$(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
+
+.PHONY: gen_headers
diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
new file mode 100755
index 0000000..caa6a9a
--- /dev/null
+++ b/arch/arm/tools/gen-headers
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+SRC=$1
+OBJ=$2
+MACH=$3
+PLAT1=$4
+PLAT2=$5
+
+# create $3 to include $2 if it doesn't already have the correct
+# contents, or remove it if it's no longer needed.
+mkfile()
+{
+	if [ -e $1/$2 ] ; then
+		if [ ! -e $3 ] ; then
+			mkdir -p ${3%/*}
+			echo "#include <${2}>" > $3
+		elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
+			echo "#include <${2}>" > $3
+		fi
+	elif [ ! -e $1/$2 -a -e $3 ] ; then
+		rm -f $3
+	fi
+}
+
+# list any header files that are present in the source or
+# destination directories
+find_files()
+{
+	pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+	pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+}
+
+# process files in either mach-{MACH} or plat-${PLAT}
+mkfiles()
+{
+	mkdir -p ${OBJ}/arch/arm/include/generated/$1
+
+	FILES=`find_files $1 $2 | sort -u`
+	for i in ${FILES} ; do
+		mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
+			"${OBJ}/arch/arm/include/generated/$1/$i"
+	done
+}
+
+# always process mach-*
+mkfiles mach ${MACH}
+# process plat-* if applicable
+if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
+	mkfiles plat ${PLAT1}
+fi
+if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
+	mkfiles plat ${PLAT2}
+fi
-- 
1.7.10



From arnd at arndb.de  Tue Aug 21 11:59:02 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:59:02 -0000
Subject: [RFC 4/4] ARM: treewide: manually change more mach-*/*.h includes
In-Reply-To: <1345564724-14466-1-git-send-email-arnd@arndb.de>
References: <1345564724-14466-1-git-send-email-arnd@arndb.de>
Message-ID: <1345564724-14466-5-git-send-email-arnd@arndb.de>

These are lots of device drivers that include machine
specific header files from ARM platforms and that are
not easily scriptable. The changes have been found through
manual inspection and should cause no visible changes
because of the build script that maps the old names to the
new ones.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/char/ds1620.c                                 |    2 +-
 drivers/char/hw_random/ixp4xx-rng.c                   |    2 +-
 drivers/cpufreq/db8500-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos-cpufreq.c                      |    2 +-
 drivers/cpufreq/exynos4210-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos4x12-cpufreq.c                  |    4 ++--
 drivers/cpufreq/exynos5250-cpufreq.c                  |    6 +++---
 drivers/cpufreq/omap-cpufreq.c                        |    2 +-
 drivers/cpufreq/s5pv210-cpufreq.c                     |    2 +-
 drivers/crypto/omap-sham.c                            |    2 +-
 drivers/crypto/tegra-aes.c                            |    2 +-
 drivers/devfreq/exynos4_bus.c                         |    2 +-
 drivers/dma/ep93xx_dma.c                              |    2 +-
 drivers/dma/imx-dma.c                                 |    4 ++--
 drivers/gpio/gpio-omap.c                              |    4 ++--
 drivers/gpio/gpio-pxa.c                               |    8 +++++++-
 drivers/i2c/busses/i2c-acorn.c                        |    2 +-
 drivers/i2c/busses/i2c-davinci.c                      |    4 ++--
 drivers/i2c/busses/i2c-imx.c                          |    4 ++--
 drivers/i2c/busses/i2c-nuc900.c                       |    4 ++--
 drivers/i2c/busses/i2c-tegra.c                        |    2 +-
 drivers/input/misc/ixp4xx-beeper.c                    |    2 +-
 drivers/input/mouse/rpcmouse.c                        |    2 +-
 drivers/input/serio/rpckbd.c                          |    2 +-
 drivers/input/touchscreen/atmel_tsadcc.c              |    4 ++--
 drivers/input/touchscreen/h3600_ts_input.c            |    4 ++--
 drivers/input/touchscreen/mainstone-wm97xx.c          |    2 +-
 drivers/input/touchscreen/zylonite-wm97xx.c           |    6 +++---
 drivers/leds/leds-fsg.c                               |    2 +-
 drivers/media/video/pxa_camera.c                      |    4 ++--
 drivers/mfd/dbx500-prcmu-regs.h                       |    2 +-
 drivers/misc/ep93xx_pwm.c                             |    2 +-
 drivers/misc/spear13xx_pcie_gadget.c                  |    4 ++--
 drivers/mmc/host/at91_mci.c                           |    4 ++--
 drivers/mmc/host/mxcmmc.c                             |    6 +++---
 drivers/mmc/host/omap_hsmmc.c                         |    2 +-
 drivers/mmc/host/pxamci.c                             |    6 +++---
 drivers/mtd/maps/cdb89712.c                           |    2 +-
 drivers/mtd/maps/h720x-flash.c                        |    2 +-
 drivers/mtd/maps/pxa2xx-flash.c                       |    2 +-
 drivers/mtd/maps/sa1100-flash.c                       |    2 +-
 drivers/mtd/nand/ams-delta.c                          |    2 +-
 drivers/mtd/nand/sharpsl.c                            |    2 +-
 drivers/net/can/at91_can.c                            |    2 +-
 drivers/net/ethernet/amd/am79c961a.c                  |    2 +-
 drivers/net/ethernet/cirrus/ep93xx_eth.c              |    2 +-
 drivers/net/ethernet/nxp/lpc_eth.c                    |    6 +++---
 drivers/net/ethernet/smsc/smc911x.h                   |    2 +-
 drivers/net/ethernet/smsc/smc91x.h                    |    2 +-
 drivers/net/irda/ep7211-sir.c                         |    2 +-
 drivers/net/irda/pxaficp_ir.c                         |    8 ++++----
 drivers/net/irda/sa1100_ir.c                          |    2 +-
 drivers/pcmcia/omap_cf.c                              |    2 +-
 drivers/pcmcia/pxa2xx_cm_x2xx.c                       |    2 +-
 drivers/pcmcia/sa1111_jornada720.c                    |    2 +-
 drivers/pcmcia/sa11xx_base.c                          |    2 +-
 drivers/power/avs/smartreflex.c                       |    1 +
 drivers/pwm/pwm-imx.c                                 |    2 +-
 drivers/rtc/rtc-mxc.c                                 |    2 +-
 drivers/rtc/rtc-pxa.c                                 |    2 +-
 drivers/rtc/rtc-stmp3xxx.c                            |    2 +-
 drivers/scsi/arm/acornscsi-io.S                       |    2 +-
 drivers/spi/spi-imx.c                                 |    2 +-
 drivers/spi/spi-omap-uwire.c                          |    2 +-
 drivers/spi/spi-s3c24xx-fiq.S                         |    4 ++--
 drivers/spi/spi-tegra.c                               |    2 +-
 drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c |    4 ++--
 drivers/tty/serial/21285.c                            |    2 +-
 drivers/tty/serial/atmel_serial.c                     |    6 ++++--
 drivers/tty/serial/clps711x.c                         |    2 +-
 drivers/tty/serial/msm_serial_hs.c                    |    4 ++--
 drivers/tty/serial/sa1100.c                           |    4 ++--
 drivers/tty/serial/serial_ks8695.c                    |    4 ++--
 drivers/uio/uio_pruss.c                               |    2 +-
 drivers/usb/gadget/fsl_mxc_udc.c                      |    2 +-
 drivers/usb/gadget/imx_udc.c                          |    4 ++--
 drivers/usb/gadget/pxa27x_udc.c                       |    4 ++--
 drivers/usb/host/ohci-at91.c                          |    6 +++---
 drivers/usb/host/ohci-exynos.c                        |    2 +-
 drivers/usb/musb/davinci.c                            |    4 ++--
 drivers/usb/musb/ux500_dma.c                          |    2 +-
 drivers/usb/otg/msm_otg.c                             |    2 +-
 drivers/video/backlight/omap1_bl.c                    |    2 +-
 drivers/video/ep93xx-fb.c                             |    2 +-
 drivers/video/nuc900fb.h                              |    4 ++--
 drivers/video/pnx4008/dum.h                           |    2 +-
 drivers/w1/masters/omap_hdq.c                         |    2 +-
 drivers/watchdog/imx2_wdt.c                           |    2 +-
 drivers/watchdog/ixp4xx_wdt.c                         |    2 +-
 drivers/watchdog/ks8695_wdt.c                         |    4 ++--
 drivers/watchdog/wdt285.c                             |    2 +-
 91 files changed, 137 insertions(+), 128 deletions(-)

diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index aab9605..b4c21b1 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -10,7 +10,7 @@
 #include <linux/init.h>
 #include <linux/mutex.h>
 
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <asm/therm.h>
diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c
index 263567f..42889bb 100644
--- a/drivers/char/hw_random/ixp4xx-rng.c
+++ b/drivers/char/hw_random/ixp4xx-rng.c
@@ -23,7 +23,7 @@
 #include <linux/hw_random.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 
 static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer)
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
index 74b830b..c771360 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -13,7 +13,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/mfd/dbx500-prcmu.h>
-#include <mach/id.h>
+#include <mach-ux500/id.h>
 
 static struct cpufreq_frequency_table freq_table[] = {
 	[0] = {
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 9382a6b..637782b 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -18,7 +18,7 @@
 #include <linux/cpufreq.h>
 #include <linux/suspend.h>
 
-#include <mach/cpufreq.h>
+#include <mach-exynos/cpufreq.h>
 
 #include <plat-samsung/cpu.h>
 
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index fb148fa..33d3d4c 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	L5
 
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8c5a7af..e7aa354 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -17,8 +17,8 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	(L13 + 1)
 
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index e64c253..74950a3 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -17,9 +17,9 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/cpufreq.h>
+#include <mach-exynos/map.h>
+#include <mach-exynos/regs-clock.h>
+#include <mach-exynos/cpufreq.h>
 
 #define CPUFREQ_LEVEL_END	(L15 + 1)
 
diff --git a/drivers/cpufreq/omap-cpufreq.c b/drivers/cpufreq/omap-cpufreq.c
index 4449907..45b2331 100644
--- a/drivers/cpufreq/omap-cpufreq.c
+++ b/drivers/cpufreq/omap-cpufreq.c
@@ -35,7 +35,7 @@
 #include <plat-omap/common.h>
 #include <plat-omap/omap_device.h>
 
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 /* OPP tolerance in percentage */
 #define	OPP_TOLERANCE	4
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index a484aae..04dfc10 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -20,7 +20,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/suspend.h>
 
-#include <mach/map.h>
+#include <mach-s5pv210/map.h>
 #include <mach/regs-clock.h>
 
 static struct clk *cpu_clk;
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 737afed..98e877d 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -39,7 +39,7 @@
 
 #include <plat-omap/cpu.h>
 #include <plat-omap/dma.h>
-#include <mach/irqs.h>
+#include <mach-omap2/irqs.h>
 
 #define SHA_REG_DIGEST(x)		(0x00 + ((x) * 0x04))
 #define SHA_REG_DIN(x)			(0x1C + ((x) * 0x04))
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index ac236f6..971bd27 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -41,7 +41,7 @@
 #include <linux/completion.h>
 #include <linux/workqueue.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #include <crypto/scatterwalk.h>
 #include <crypto/aes.h>
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index c8af6d4..e8d7ce8 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -30,7 +30,7 @@
 extern unsigned int exynos_result_of_asv;
 #endif
 
-#include <mach/regs-clock.h>
+#include <mach-exynos/regs-clock.h>
 
 #include <plat-samsung/map-s5p.h>
 
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index c64917e..09d7112 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/dma.h>
+#include <mach-ep93xx/dma.h>
 
 #include "dmaengine.h"
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fcfeb3c..0597cbc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -28,8 +28,8 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #include "dmaengine.h"
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..45592ca 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -26,9 +26,9 @@
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <asm/irq.h>
-#include <mach/irqs.h>
+#include <plat-omap/irqs.h>
 #include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 58a6a63..c6440a5 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,7 +26,13 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
+#ifdef CONFIG_ARCH_PXA
+#include <mach-pxa/irqs.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+#include <mach-mmp/irqs.h>
+#endif
 
 /*
  * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index ed9f48d..4d0f7797 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -17,7 +17,7 @@
 #include <linux/i2c-algo-bit.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/ioc.h>
 
 #define FORCE_ONES	0xdc
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 79b4bcb..d163b73 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -39,8 +39,8 @@
 #include <linux/cpufreq.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/i2c.h>
 
 /* ----- global defines ----------------------------------------------- */
 
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 0722f86..a8ffc39 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -53,8 +53,8 @@
 #include <linux/of_i2c.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
+#include <mach-imx/hardware.h>
+#include <mach-imx/i2c.h>
 
 /** Defines ********************************************************************
 *******************************************************************************/
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
index a26dfb8..cfe6803 100644
--- a/drivers/i2c/busses/i2c-nuc900.c
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -28,8 +28,8 @@
 #include <linux/slab.h>
 #include <linux/io.h>
 
-#include <mach/mfp.h>
-#include <mach/i2c.h>
+#include <mach-w90x900/mfp.h>
+#include <mach-w90x900/i2c.h>
 
 /* nuc900 i2c registers offset */
 
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 66eb53f..8712414 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -31,7 +31,7 @@
 
 #include <asm/unaligned.h>
 
-#include <mach/clk.h>
+#include <mach-tegra/clk.h>
 
 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 #define BYTES_PER_FIFO_WORD 4
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
index 50e2830..9b644e1 100644
--- a/drivers/input/misc/ixp4xx-beeper.c
+++ b/drivers/input/misc/ixp4xx-beeper.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 MODULE_AUTHOR("Alessandro Zummo <a.zummo at towertech.it>");
 MODULE_DESCRIPTION("ixp4xx beeper driver");
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 272dedd..41c1fa4 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -24,7 +24,7 @@
 #include <linux/input.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/iomd.h>
 
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index 2af5df6..5bee7e0 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -36,7 +36,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 #include <asm/hardware/iomd.h>
 
 MODULE_AUTHOR("Vojtech Pavlik, Russell King");
diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
index 201b2d2..00f8aac 100644
--- a/drivers/input/touchscreen/atmel_tsadcc.c
+++ b/drivers/input/touchscreen/atmel_tsadcc.c
@@ -22,8 +22,8 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 /* Register definitions based on AT91SAM9RL64 preliminary draft datasheet */
 
diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
index b9e8686..39a0ce5 100644
--- a/drivers/input/touchscreen/h3600_ts_input.c
+++ b/drivers/input/touchscreen/h3600_ts_input.c
@@ -39,8 +39,8 @@
 #include <linux/delay.h>
 
 /* SA1100 serial defines */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 
 #define DRIVER_DESC	"H3600 touchscreen driver"
 
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index 7d2b213..997e627 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -33,7 +33,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-#include <mach/regs-ac97.h>
+#include <mach-pxa/regs-ac97.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/input/touchscreen/zylonite-wm97xx.c b/drivers/input/touchscreen/zylonite-wm97xx.c
index bf0869a7..be59125 100644
--- a/drivers/input/touchscreen/zylonite-wm97xx.c
+++ b/drivers/input/touchscreen/zylonite-wm97xx.c
@@ -28,9 +28,9 @@
 #include <linux/io.h>
 #include <linux/wm97xx.h>
 
-#include <mach/hardware.h>
-#include <mach/mfp.h>
-#include <mach/regs-ac97.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/mfp.h>
+#include <mach-pxa/regs-ac97.h>
 
 struct continuous {
 	u16 id;    /* codec id */
diff --git a/drivers/leds/leds-fsg.c b/drivers/leds/leds-fsg.c
index b9053fa..683b01d 100644
--- a/drivers/leds/leds-fsg.c
+++ b/drivers/leds/leds-fsg.c
@@ -20,7 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/module.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 #include <asm/io.h>
 
 #define FSG_LED_WLAN_BIT	0
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 9c21e01..0d76655 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -36,8 +36,8 @@
 
 #include <linux/videodev2.h>
 
-#include <mach/dma.h>
-#include <mach/camera.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/camera.h>
 
 #define PXA_CAM_VERSION "0.0.6"
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6..7de55f8 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -13,7 +13,7 @@
 #ifndef __DB8500_PRCMU_REGS_H
 #define __DB8500_PRCMU_REGS_H
 
-#include <mach/hardware.h>
+#include <mach-ux500/hardware.h>
 
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
 
diff --git a/drivers/misc/ep93xx_pwm.c b/drivers/misc/ep93xx_pwm.c
index 16d7179..a996270 100644
--- a/drivers/misc/ep93xx_pwm.c
+++ b/drivers/misc/ep93xx_pwm.c
@@ -24,7 +24,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <mach/platform.h>
+#include <mach-ep93xx/platform.h>
 
 #define EP93XX_PWMx_TERM_COUNT	0x00
 #define EP93XX_PWMx_DUTY_CYCLE	0x04
diff --git a/drivers/misc/spear13xx_pcie_gadget.c b/drivers/misc/spear13xx_pcie_gadget.c
index 123ed98..0a32042 100644
--- a/drivers/misc/spear13xx_pcie_gadget.c
+++ b/drivers/misc/spear13xx_pcie_gadget.c
@@ -20,8 +20,8 @@
 #include <linux/platform_device.h>
 #include <linux/pci_regs.h>
 #include <linux/configfs.h>
-#include <mach/pcie.h>
-#include <mach/misc_regs.h>
+#include <mach-spear13xx/pcie.h>
+#include <mach-spear13xx/misc_regs.h>
 
 #define IN0_MEM_SIZE	(200 * 1024 * 1024 - 1)
 /* In current implementation address translation is done using IN0 only.
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index efdb81d..ec7f665 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -75,8 +75,8 @@
 #include <asm/irq.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #include "at91_mci.h"
 
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index 28ed52d..dec1bb1 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -38,10 +38,10 @@
 #include <asm/dma.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <mach/mmc.h>
+#include <mach-imx/mmc.h>
 
-#include <mach/dma.h>
-#include <mach/hardware.h>
+#include <mach-imx/dma.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "mxc-mmc"
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 198066c..194bc04 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -39,7 +39,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
-#include <mach/hardware.h>
+#include <plat-omap/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mmc.h>
 #include <plat-omap/cpu.h>
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index cb2dc0e..8b01058 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -33,9 +33,9 @@
 
 #include <asm/sizes.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <mach/mmc.h>
+#include <mach-pxa/hardware.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/mmc.h>
 
 #include "pxamci.h"
 
diff --git a/drivers/mtd/maps/cdb89712.c b/drivers/mtd/maps/cdb89712.c
index c29cbf8..c224dd4 100644
--- a/drivers/mtd/maps/cdb89712.c
+++ b/drivers/mtd/maps/cdb89712.c
@@ -9,7 +9,7 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/maps/h720x-flash.c b/drivers/mtd/maps/h720x-flash.c
index 8ed6cb4..3206fef 100644
--- a/drivers/mtd/maps/h720x-flash.c
+++ b/drivers/mtd/maps/h720x-flash.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
-#include <mach/hardware.h>
+#include <mach-h720x/hardware.h>
 #include <asm/io.h>
 
 static struct mtd_info *mymtd;
diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index 81884c2..8a82445 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -20,7 +20,7 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c
index a675bdb..2f234e6 100644
--- a/drivers/mtd/maps/sa1100-flash.c
+++ b/drivers/mtd/maps/sa1100-flash.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/concat.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
 
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 1386f6b..7a921a1 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -24,7 +24,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/sizes.h>
 #include <linux/gpio.h>
 #include <plat-omap/board-ams-delta.h>
diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c
index 3421e37..866aaac 100644
--- a/drivers/mtd/nand/sharpsl.c
+++ b/drivers/mtd/nand/sharpsl.c
@@ -25,7 +25,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 #include <asm/mach-types.h>
 
 struct sharpsl_nand {
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index fcff73a..8f14511 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -37,7 +37,7 @@
 #include <linux/can/dev.h>
 #include <linux/can/error.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 #define AT91_MB_MASK(i)		((1 << (i)) - 1)
 
diff --git a/drivers/net/ethernet/amd/am79c961a.c b/drivers/net/ethernet/amd/am79c961a.c
index e10ffad..89746bf 100644
--- a/drivers/net/ethernet/amd/am79c961a.c
+++ b/drivers/net/ethernet/amd/am79c961a.c
@@ -29,7 +29,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-ebsa110/hardware.h>
 
 #define TX_BUFFERS 15
 #define RX_BUFFERS 25
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 78c5521..7ad8b0d 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -26,7 +26,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-ep93xx/hardware.h>
 
 #define DRV_MODULE_NAME		"ep93xx-eth"
 #define DRV_MODULE_VERSION	"0.1"
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 4069eda..5be01c0 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -45,9 +45,9 @@
 #include <linux/types.h>
 
 #include <linux/io.h>
-#include <mach/board.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
+#include <mach-lpc32xx/board.h>
+#include <mach-lpc32xx/platform.h>
+#include <mach-lpc32xx/hardware.h>
 
 #define MODNAME "lpc-eth"
 #define DRV_VERSION "1.00"
diff --git a/drivers/net/ethernet/smsc/smc911x.h b/drivers/net/ethernet/smsc/smc911x.h
index 3269292..80eb9d0 100644
--- a/drivers/net/ethernet/smsc/smc911x.h
+++ b/drivers/net/ethernet/smsc/smc911x.h
@@ -211,7 +211,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 
 #ifdef SMC_USE_PXA_DMA
 
-#include <mach/dma.h>
+#include <mach-pxa/dma.h>
 
 /*
  * Define the request and free functions
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
index 7f4beeb..754af90 100644
--- a/drivers/net/ethernet/smsc/smc91x.h
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -364,7 +364,7 @@ struct smc_local {
  * as RX which can overrun memory and lose packets.
  */
 #include <linux/dma-mapping.h>
-#include <mach-sa1100/dma.h>
+#include <mach-pxa/dma.h>
 
 #ifdef SMC_insl
 #undef SMC_insl
diff --git a/drivers/net/irda/ep7211-sir.c b/drivers/net/irda/ep7211-sir.c
index f83c5b8..8f8d91c 100644
--- a/drivers/net/irda/ep7211-sir.c
+++ b/drivers/net/irda/ep7211-sir.c
@@ -14,7 +14,7 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/io.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 #include "sir-dev.h"
 
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8d54767..86073eb 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -27,10 +27,10 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/dma.h>
-#include <mach/irda.h>
-#include <mach/regs-uart.h>
-#include <mach/regs-ost.h>
+#include <mach-pxa/dma.h>
+#include <mach-pxa/irda.h>
+#include <mach-pxa/regs-uart.h>
+#include <mach-pxa/regs-ost.h>
 
 #define FICP		__REG(0x40800000)  /* Start of FICP area */
 #define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
index e250675..3f88a39 100644
--- a/drivers/net/irda/sa1100_ir.c
+++ b/drivers/net/irda/sa1100_ir.c
@@ -37,7 +37,7 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/mach/irda.h>
 
 static int power_level = 3;
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index adb5b1e..070eaa6 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -20,7 +20,7 @@
 
 #include <pcmcia/ss.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
 
diff --git a/drivers/pcmcia/pxa2xx_cm_x2xx.c b/drivers/pcmcia/pxa2xx_cm_x2xx.c
index 6e7dcfd..61097ba 100644
--- a/drivers/pcmcia/pxa2xx_cm_x2xx.c
+++ b/drivers/pcmcia/pxa2xx_cm_x2xx.c
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 int cmx255_pcmcia_init(void);
 int cmx270_pcmcia_init(void);
diff --git a/drivers/pcmcia/sa1111_jornada720.c b/drivers/pcmcia/sa1111_jornada720.c
index 69428d1..86fc717 100644
--- a/drivers/pcmcia/sa1111_jornada720.c
+++ b/drivers/pcmcia/sa1111_jornada720.c
@@ -10,7 +10,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/hardware/sa1111.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c
index 6eecd7c..2d689b2 100644
--- a/drivers/pcmcia/sa11xx_base.c
+++ b/drivers/pcmcia/sa11xx_base.c
@@ -39,7 +39,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-sa1100/hardware.h>
 #include <asm/irq.h>
 
 #include "soc_common.h"
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e..af502d1 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <linux/power/smartreflex.h>
+#include <plat-omap/cpu.h>
 
 #define SMARTREFLEX_NAME_LEN	16
 #define NVALUE_NAME_LEN		40
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2a0b353..68ff175 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -16,7 +16,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pwm.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 
 /* i.MX1 and i.MX21 share the same PWM function block: */
diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
index e3e50d6..eb4d40e 100644
--- a/drivers/rtc/rtc-mxc.c
+++ b/drivers/rtc/rtc-mxc.c
@@ -17,7 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
 #define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8f..679ca79 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #define TIMER_FREQ		CLOCK_TICK_RATE
 #define RTC_DEF_DIVIDER		(32768 - 1)
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index 739ef556..9f7ff1d 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/of_device.h>
 
-#include <mach/common.h>
+#include <mach-mxs/common.h>
 
 #define STMP3XXX_RTC_CTRL			0x0
 #define STMP3XXX_RTC_CTRL_SET			0x4
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S
index 22171b2..6395330 100644
--- a/drivers/scsi/arm/acornscsi-io.S
+++ b/drivers/scsi/arm/acornscsi-io.S
@@ -8,7 +8,7 @@
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
-#include <mach/hardware.h>
+#include <mach-rpc/hardware.h>
 
 #if defined(__APCS_32__)
 #define LOADREGS(t,r,l...)	ldm##t	r, l
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index e834ff8..819ddf0 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -39,7 +39,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
 
-#include <mach/spi.h>
+#include <mach-imx/spi.h>
 
 #define DRIVER_NAME "spi_imx"
 
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 177b6cf..dc2ad86 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -48,7 +48,7 @@
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/spi/spi-s3c24xx-fiq.S b/drivers/spi/spi-s3c24xx-fiq.S
index 9718a11..44941ce 100644
--- a/drivers/spi/spi-s3c24xx-fiq.S
+++ b/drivers/spi/spi-s3c24xx-fiq.S
@@ -13,8 +13,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <mach/map.h>
-#include <mach/regs-irq.h>
+#include <mach-s3c24xx/map.h>
+#include <mach-s3c24xx/regs-irq.h>
 #include <plat-samsung/regs-spi.h>
 
 #include "spi-s3c24xx-fiq.h"
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c..77b2810 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -32,7 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/dmaengine.h>
 
-#include <mach/dma.h>
+#include <mach-tegra/dma.h>
 
 #define SLINK_COMMAND		0x000
 #define   SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
index a272e48..1e4f493 100644
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
@@ -5,8 +5,8 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
+#include <mach-ux500/gpio.h>
+#include <mach-ux500/irqs.h>
 #include "synaptics_i2c_rmi4.h"
 
 /*
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index a44345a..8104b07 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -18,7 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #define BAUD_BASE		(mem_fclk_21285/64)
 
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3d7e1ee..ff99a33 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -44,11 +44,13 @@
 #include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
-#include <mach/board.h>
 
 #ifdef CONFIG_ARM
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 #include <asm/gpio.h>
+#else
+#include <mach/board.h>
 #endif
 
 #define PDC_BUFFER_SIZE		512
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
index d0f719f..e4dc87b 100644
--- a/drivers/tty/serial/clps711x.c
+++ b/drivers/tty/serial/clps711x.c
@@ -38,7 +38,7 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 
 #define UART_NR		2
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index fca13dc..949c9e6 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -51,8 +51,8 @@
 #include <linux/atomic.h>
 #include <asm/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/dma.h>
+#include <mach-msm/hardware.h>
+#include <mach-msm/dma.h>
 #include <linux/platform_data/msm_serial_hs.h>
 
 /* HSUART Registers */
diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
index 2ca5959..d5c47f6 100644
--- a/drivers/tty/serial/sa1100.c
+++ b/drivers/tty/serial/sa1100.c
@@ -37,8 +37,8 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <mach-sa1100/hardware.h>
+#include <mach-sa1100/irqs.h>
 #include <asm/mach/serial_sa1100.h>
 
 /* We've been assigned a range on the "Low-density serial ports" major */
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 7c13639..f5c672c 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -25,8 +25,8 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
-#include <mach/regs-uart.h>
-#include <mach/regs-irq.h>
+#include <mach-ks8695/regs-uart.h>
+#include <mach-ks8695/regs-irq.h>
 
 #if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 #define SUPPORT_SYSRQ
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
index 33a7a27..4bafe92 100644
--- a/drivers/uio/uio_pruss.c
+++ b/drivers/uio/uio_pruss.c
@@ -25,7 +25,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
-#include <mach/sram.h>
+#include <mach-davinci/sram.h>
 
 #define DRV_NAME "pruss_uio"
 #define DRV_VERSION "1.0"
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 1b0f086..fce80b3 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -18,7 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 static struct clk *mxc_ahb_clk;
 static struct clk *mxc_per_clk;
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index dc53348..476ac2b 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -35,8 +35,8 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
-#include <mach/usb.h>
-#include <mach/hardware.h>
+#include <mach-imx/usb.h>
+#include <mach-imx/hardware.h>
 
 #include "imx_udc.h"
 
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 644b430..d4ef1fe 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -26,12 +26,12 @@
 #include <linux/prefetch.h>
 
 #include <asm/byteorder.h>
-#include <mach/hardware.h>
+#include <mach-pxa/hardware.h>
 
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-#include <mach/udc.h>
+#include <mach-pxa/udc.h>
 
 #include "pxa27x_udc.h"
 
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a665b3e..5add6ce 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -17,11 +17,11 @@
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/gpio.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
 
 #ifndef CONFIG_ARCH_AT91
 #error "CONFIG_ARCH_AT91 must be defined."
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 2dce0df..561f56a 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <mach/ohci.h>
+#include <mach-exynos/ohci.h>
 #include <plat-samsung/usb-phy.h>
 
 struct exynos_ohci_hcd {
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 472c8b4..2e8cfb8 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -34,8 +34,8 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/cputype.h>
-#include <mach/hardware.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/hardware.h>
 
 #include <asm/mach-types.h>
 
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index d05c7fb..7c92d86 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -30,7 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/pfn.h>
-#include <mach/usb.h>
+#include <mach-ux500/usb.h>
 #include "musb_core.h"
 
 struct ux500_dma_channel {
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 9f5fc90..e41e6c5 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -40,7 +40,7 @@
 #include <linux/usb/msm_hsusb_hw.h>
 #include <linux/regulator/consumer.h>
 
-#include <mach/clk.h>
+#include <mach-msm/clk.h>
 
 #define MSM_USB_BASE	(motg->regs)
 #define DRIVER_NAME	"msm_otg"
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index 1e39ae3..556b623 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -28,7 +28,7 @@
 #include <linux/backlight.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-omap1/hardware.h>
 #include <plat-omap/board.h>
 #include <plat-omap/mux.h>
 
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 345d962..b58f5c5 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 
-#include <mach/fb.h>
+#include <mach-ep93xx/fb.h>
 
 /* Vertical Frame Timing Registers */
 #define EP93XXFB_VLINES_TOTAL			0x0000	/* SW locked */
diff --git a/drivers/video/nuc900fb.h b/drivers/video/nuc900fb.h
index bc7c930..6f7f59a 100644
--- a/drivers/video/nuc900fb.h
+++ b/drivers/video/nuc900fb.h
@@ -15,8 +15,8 @@
 #ifndef __NUC900FB_H
 #define __NUC900FB_H
 
-#include <mach/map.h>
-#include <mach/fb.h>
+#include <mach-w90x900/map.h>
+#include <mach-w90x900/fb.h>
 
 enum nuc900_lcddrv_type {
 	LCDDRV_NUC910,
diff --git a/drivers/video/pnx4008/dum.h b/drivers/video/pnx4008/dum.h
index 1234d43..ddae1c2 100644
--- a/drivers/video/pnx4008/dum.h
+++ b/drivers/video/pnx4008/dum.h
@@ -12,7 +12,7 @@
 #ifndef __PNX008_DUM_H__
 #define __PNX008_DUM_H__
 
-#include <mach/platform.h>
+#include <mach-pnx4008/platform.h>
 
 #define PNX4008_DUMCONF_VA_BASE		IO_ADDRESS(PNX4008_DUMCONF_BASE)
 #define PNX4008_DUM_MAIN_VA_BASE	IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index 4b0fcf3..2d9cc12 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -19,7 +19,7 @@
 #include <linux/pm_runtime.h>
 
 #include <asm/irq.h>
-#include <mach/hardware.h>
+#include <mach-omap2/hardware.h>
 
 #include "../w1.h"
 #include "../w1_int.h"
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index bcfab2b..f745c9b 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -33,7 +33,7 @@
 #include <linux/uaccess.h>
 #include <linux/timer.h>
 #include <linux/jiffies.h>
-#include <mach/hardware.h>
+#include <mach-imx/hardware.h>
 
 #define DRIVER_NAME "imx2-wdt"
 
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index 5580b4f..913d480 100644
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -25,7 +25,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
+#include <mach-ixp4xx/hardware.h>
 
 static bool nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = 60;	/* (secs) Default is 1 minute */
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9..19c1dc1 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -23,8 +23,8 @@
 #include <linux/watchdog.h>
 #include <linux/io.h>
 #include <linux/uaccess.h>
-#include <mach/hardware.h>
-#include <mach/regs-timer.h>
+#include <mach-ks8695/hardware.h>
+#include <mach-ks8695/regs-timer.h>
 
 #define WDT_DEFAULT_TIME	5	/* seconds */
 #define WDT_MAX_TIME		171	/* seconds */
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index 5eec740..1e1c743 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -31,7 +31,7 @@
 #include <linux/interrupt.h>
 #include <linux/uaccess.h>
 #include <linux/irq.h>
-#include <mach/hardware.h>
+#include <mach-footbridge/hardware.h>
 
 #include <asm/mach-types.h>
 #include <asm/system_info.h>
-- 
1.7.10



From arnd at arndb.de  Tue Aug 21 11:59:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:59:23 -0000
Subject: [RFC 2/4] ARM: mass move of mach-*/plat-* header files
In-Reply-To: <1345564724-14466-1-git-send-email-arnd@arndb.de>
References: <1345564724-14466-1-git-send-email-arnd@arndb.de>
Message-ID: <1345564724-14466-3-git-send-email-arnd@arndb.de>

This moves all <mach/*.h> headers to <mach-*/*.h>, and all
<plat/*.h> headers to <plat-*/*.h>, as another step closer
to building kernels for multiple platforms combined.

A script to generate headers with the traditional names including
the headers from the new place is already there, so this move
should be completely transparent.

This patch was created fully automated by a script and
should be redone if the headers change. Note that the
plat-mxc headers move to mach-imx in the process because
they don't follow the <plat/foo.h> naming convention:

for i in arch/arm/mach-* ; do git mv $i/include/mach $i/include/${i##*/} ; done
for i in arch/arm/plat-* ; do git mv $i/include/plat $i/include/${i##*/} ; done
git mv arch/arm/plat-mxc/include/mach/*.h arch/arm/mach-imx/include/mach-imx/

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_adc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_aic.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_dbgu.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_matrix.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pio.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pit.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_pmc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_ramc.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rstc.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtc.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtt.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_shdwc.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_st.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_tc.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91_twi.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_emac.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_mc.h         |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_sdramc.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_ddrsdr.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_sdramc.h       |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_smc.h          |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12.h           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12_matrix.h    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl_matrix.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5_matrix.h     |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at91x40.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/at_hdmac.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/atmel-mci.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/board.h                 |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/cpu.h                   |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/debug-macro.S           |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/gpio.h                  |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/gsia18s.h               |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/hardware.h              |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/io.h                    |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/memory.h                |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/stamp9g20.h             |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/system_rev.h            |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/timex.h                 |    0
 arch/arm/mach-at91/include/{mach => mach-at91}/uncompress.h            |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap.h         |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap_inline.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_def.h |    0
 .../mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_inline.h   |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_reg.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/ddrcReg.h     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_priv.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_reg.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/hw_cfg.h      |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/intcHw_reg.h  |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_addr.h     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_io.h       |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_def.h   |    0
 .../arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_inline.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/tmrHw_reg.h   |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/dma.h             |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/entry-macro.S     |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/hardware.h        |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/irqs.h            |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/memory_settings.h |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_nand.h        |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_umi.h         |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timer.h           |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timex.h           |    0
 arch/arm/mach-bcmring/include/{mach => mach-bcmring}/uncompress.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/autcpu12.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/clps711x.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/debug-macro.S   |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/entry-macro.S   |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/hardware.h      |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/irqs.h          |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/memory.h        |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/syspld.h        |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/timex.h         |    0
 arch/arm/mach-clps711x/include/{mach => mach-clps711x}/uncompress.h    |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/cns3xxx.h         |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/debug-macro.S     |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/irqs.h            |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/pm.h              |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/timex.h           |    0
 arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/uncompress.h      |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/aemif.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/asp.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cdce949.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/clock.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/common.h          |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cp_intc.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cpufreq.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cpuidle.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/cputype.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/da8xx.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/ddr2.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/debug-macro.S     |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/edma.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/entry-macro.S     |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio-davinci.h    |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/hardware.h        |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/i2c.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/irqs.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/keyscan.h         |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/mmc.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/mux.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/nand.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/pm.h              |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/psc.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/serial.h          |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/spi.h             |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/sram.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/time.h            |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/timex.h           |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/tnetv107x.h       |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/uncompress.h      |    0
 arch/arm/mach-davinci/include/{mach => mach-davinci}/usb.h             |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/bridge-regs.h           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/debug-macro.S           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/dove.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/entry-macro.S           |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/gpio.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/hardware.h              |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/io.h                    |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/irqs.h                  |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/pm.h                    |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/timex.h                 |    0
 arch/arm/mach-dove/include/{mach => mach-dove}/uncompress.h            |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/debug-macro.S     |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/entry-macro.S     |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/hardware.h        |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/io.h              |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/irqs.h            |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/memory.h          |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/timex.h           |    0
 arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/uncompress.h      |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/debug-macro.S       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/dma.h               |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx-regs.h       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_keypad.h     |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_spi.h        |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/fb.h                |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio-ep93xx.h       |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio.h              |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/hardware.h          |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/irqs.h              |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/memory.h            |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/platform.h          |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/timex.h             |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ts72xx.h            |    0
 arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/uncompress.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/cpufreq.h           |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/debug-macro.S       |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/dma.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/dwmci.h             |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/gpio.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/hardware.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/irqs.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/map.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/memory.h            |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/ohci.h              |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/pm-core.h           |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/pmu.h               |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-audss.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-clock.h        |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-gpio.h         |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-irq.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mct.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mem.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-pmu.h          |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-usb-phy.h      |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/sysmmu.h            |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/timex.h             |    0
 arch/arm/mach-exynos/include/{mach => mach-exynos}/uncompress.h        |    0
 .../mach-footbridge/include/{mach => mach-footbridge}/debug-macro.S    |    0
 .../mach-footbridge/include/{mach => mach-footbridge}/entry-macro.S    |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/hardware.h  |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/io.h        |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/irqs.h      |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/isa-dma.h   |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/memory.h    |    0
 arch/arm/mach-footbridge/include/{mach => mach-footbridge}/timex.h     |    0
 .../arm/mach-footbridge/include/{mach => mach-footbridge}/uncompress.h |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/debug-macro.S       |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/entry-macro.S       |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/global_reg.h        |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/gpio.h              |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/hardware.h          |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/irqs.h              |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/system.h            |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/timex.h             |    0
 arch/arm/mach-gemini/include/{mach => mach-gemini}/uncompress.h        |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/boards.h              |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/debug-macro.S         |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/entry-macro.S         |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/h7201-regs.h          |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/h7202-regs.h          |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/hardware.h            |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/irqs.h                |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/isa-dma.h             |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/timex.h               |    0
 arch/arm/mach-h720x/include/{mach => mach-h720x}/uncompress.h          |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/debug-macro.S   |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/gpio.h          |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/timex.h         |    0
 arch/arm/mach-highbank/include/{mach => mach-highbank}/uncompress.h    |    0
 .../include/mach => mach-imx/include/mach-imx}/3ds_debugboard.h        |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31lilly.h       |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31lite.h        |    0
 .../include/mach => mach-imx/include/mach-imx}/board-mx31moboard.h     |    0
 .../include/mach => mach-imx/include/mach-imx}/board-pcm038.h          |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/clock.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/common.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/cpuidle.h |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/debug-macro.S |    0
 .../include/mach => mach-imx/include/mach-imx}/devices-common.h        |    0
 arch/arm/mach-imx/include/{mach => mach-imx}/dma-mx1-mx2.h             |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/dma.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/esdhc.h  |    0
 .../include/mach => mach-imx/include/mach-imx}/eukrea-baseboards.h     |    0
 arch/arm/{mach-msm/include/mach => mach-imx/include/mach-imx}/gpio.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/hardware.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/i2c.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iim.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/imx-uart.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imxfb.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx1.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx21.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx25.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx27.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx2x.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx3.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx35.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx50.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx51.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx53.h  |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v1.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v3.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ipu.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iram.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/irqs.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mmc.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1_camera.h  |    0
 .../include/mach => mach-imx/include/mach-imx}/mx21-usbhost.h          |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx25.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx27.h   |    0
 .../arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2_cam.h |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2x.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx31.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx35.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3_camera.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3fb.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3x.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx50.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx51.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx53.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx6q.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_ehci.h    |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_nand.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/sdma.h   |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/spi.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ssi.h    |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/timex.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ulpi.h   |    0
 .../{plat-mxc/include/mach => mach-imx/include/mach-imx}/uncompress.h  |    0
 arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/usb.h    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/cm.h        |    0
 .../mach-integrator/include/{mach => mach-integrator}/debug-macro.S    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/hardware.h  |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/impd1.h     |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/io.h        |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/irqs.h      |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/lm.h        |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/memory.h    |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/platform.h  |    0
 arch/arm/mach-integrator/include/{mach => mach-integrator}/timex.h     |    0
 .../arm/mach-integrator/include/{mach => mach-integrator}/uncompress.h |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/adma.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/debug-macro.S     |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/entry-macro.S     |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/hardware.h        |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/io.h              |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iop13xx.h         |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iq81340.h         |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/irqs.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/memory.h          |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/msi.h             |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/pci.h             |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/time.h            |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/timex.h           |    0
 arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/uncompress.h      |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/adma.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/debug-macro.S       |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/entry-macro.S       |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/glantank.h          |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/gpio.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/hardware.h          |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/io.h                |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iop32x.h            |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq31244.h           |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq80321.h           |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/irqs.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/n2100.h             |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/time.h              |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/timex.h             |    0
 arch/arm/mach-iop32x/include/{mach => mach-iop32x}/uncompress.h        |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/adma.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/debug-macro.S       |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/entry-macro.S       |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/gpio.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/hardware.h          |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/io.h                |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iop33x.h            |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80331.h           |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80332.h           |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/irqs.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/time.h              |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/timex.h             |    0
 arch/arm/mach-iop33x/include/{mach => mach-iop33x}/uncompress.h        |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/cpu.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/debug-macro.S       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/entry-macro.S       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/gpio.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/hardware.h          |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/io.h                |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/irqs.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp46x_ts.h         |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp4xx-regs.h       |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/npe.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/platform.h          |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/qmgr.h              |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/timex.h             |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/udc.h               |    0
 arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/uncompress.h        |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/bridge-regs.h   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/debug-macro.S   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/entry-macro.S   |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/gpio.h          |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/hardware.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/io.h            |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/irqs.h          |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/kirkwood.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-netxbig.h  |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-ns2.h      |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/timex.h         |    0
 arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/uncompress.h    |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/debug-macro.S       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/devices.h           |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/entry-macro.S       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio-ks8695.h       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio.h              |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/hardware.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/irqs.h              |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/memory.h            |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-gpio.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-hpna.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-irq.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-lan.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-mem.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-misc.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-pci.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-switch.h       |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-sys.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-timer.h        |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-uart.h         |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-wan.h          |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/timex.h             |    0
 arch/arm/mach-ks8695/include/{mach => mach-ks8695}/uncompress.h        |    0
 arch/arm/mach-l7200/include/{mach => mach-l7200}/debug-macro.S         |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/board.h           |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/debug-macro.S     |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/entry-macro.S     |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio-lpc32xx.h    |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio.h            |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/hardware.h        |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/irqs.h            |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/platform.h        |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/timex.h           |    0
 arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/uncompress.h      |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/addr-map.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/cputype.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/debug-macro.S             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/devices.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/dma.h                     |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/entry-macro.S             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/gpio.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/hardware.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/irqs.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-mmp2.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa168.h              |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa910.h              |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp.h                     |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/mmp2.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-mmp2.h                 |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-pxa910.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa168.h                  |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa910.h                  |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apbc.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apmu.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-icu.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-rtc.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-smc.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-timers.h             |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-usb.h                |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/sram.h                    |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/teton_bga.h               |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/timex.h                   |    0
 arch/arm/mach-mmp/include/{mach => mach-mmp}/uncompress.h              |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/board.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/clk.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/debug-macro.S             |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/dma.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/entry-macro.S             |    0
 arch/arm/{mach-mxs/include/mach => mach-msm/include/mach-msm}/gpio.h   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/hardware.h                |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/iommu.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/iommu_hw-8xxx.h           |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x00.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x30.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8960.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x50.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x60.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/irqs.h                    |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h                     |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_fb.h                  |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_gpiomux.h             |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x00.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x30.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8960.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x50.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x60.h          |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap.h               |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/msm_smd.h                 |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/sirc.h                    |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/system.h                  |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/timex.h                   |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/uncompress.h              |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/vreg.h                    |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/bridge-regs.h     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/debug-macro.S     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/entry-macro.S     |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/gpio.h            |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/hardware.h        |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/io.h              |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/irqs.h            |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/mv78xx0.h         |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/timex.h           |    0
 arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/uncompress.h      |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/armada-370-xp.h       |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/debug-macro.S         |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/timex.h               |    0
 arch/arm/mach-mvebu/include/{mach => mach-mvebu}/uncompress.h          |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/common.h                  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/debug-macro.S             |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/devices-common.h          |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/digctl.h                  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/entry-macro.S             |    0
 .../{mach-picoxcell/include/mach => mach-mxs/include/mach-mxs}/gpio.h  |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/hardware.h                |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx23.h              |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx28.h              |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux.h                   |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/irqs.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mx23.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mx28.h                    |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/mxs.h                     |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/timex.h                   |    0
 arch/arm/mach-mxs/include/{mach => mach-mxs}/uncompress.h              |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/debug-macro.S           |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/eth.h                   |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/hardware.h              |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/irqs.h                  |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/netx-regs.h             |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/param.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/pfifo.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/timex.h                 |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/uncompress.h            |    0
 arch/arm/mach-netx/include/{mach => mach-netx}/xc.h                    |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/debug-macro.S     |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/fsmc.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/gpio.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/hardware.h        |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/irqs.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/nand.h            |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/timex.h           |    0
 arch/arm/mach-nomadik/include/{mach => mach-nomadik}/uncompress.h      |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/ams-delta-fiq.h       |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/camera.h              |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/debug-macro.S         |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/entry-macro.S         |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/gpio.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/hardware.h            |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/io.h                  |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/irqs.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/lcd_dma.h             |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/lcdc.h                |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/memory.h              |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/mtd-xip.h             |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/smp.h                 |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/timex.h               |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/uncompress.h          |    0
 arch/arm/mach-omap1/include/{mach => mach-omap1}/usb.h                 |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/am35xx.h              |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/barriers.h            |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/board-rx51.h          |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/board-zoom.h          |    0
 .../mach-omap2/include/{mach => mach-omap2}/ctrl_module_core_44xx.h    |    0
 .../include/{mach => mach-omap2}/ctrl_module_pad_core_44xx.h           |    0
 .../include/{mach => mach-omap2}/ctrl_module_pad_wkup_44xx.h           |    0
 .../mach-omap2/include/{mach => mach-omap2}/ctrl_module_wkup_44xx.h    |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/debug-macro.S         |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/gpio.h                |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/hardware.h            |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/id.h                  |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/irqs.h                |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-secure.h         |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-wakeupgen.h      |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/smp.h                 |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/timex.h               |    0
 arch/arm/mach-omap2/include/{mach => mach-omap2}/uncompress.h          |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/bridge-regs.h     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/debug-macro.S     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/entry-macro.S     |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/gpio.h            |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/hardware.h        |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/io.h              |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/irqs.h            |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/orion5x.h         |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/timex.h           |    0
 arch/arm/mach-orion5x/include/{mach => mach-orion5x}/uncompress.h      |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/debug-macro.S |    0
 .../include/mach => mach-picoxcell/include/mach-picoxcell}/gpio.h      |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/hardware.h    |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/map.h         |    0
 .../mach-picoxcell/include/{mach => mach-picoxcell}/picoxcell_soc.h    |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/timex.h       |    0
 arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/uncompress.h  |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/clock.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/debug-macro.S     |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/dma.h             |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/entry-macro.S     |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/gpio-pnx4008.h    |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/hardware.h        |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irq.h             |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irqs.h            |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/param.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/platform.h        |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/pm.h              |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/timex.h           |    0
 arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/uncompress.h      |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/clkdev.h            |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/debug-macro.S       |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/entry-macro.S       |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/gpio.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/hardware.h          |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/irqs.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/map.h               |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/timex.h             |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/uart.h              |    0
 arch/arm/mach-prima2/include/{mach => mach-prima2}/uncompress.h        |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/addr-map.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/arcom-pcmcia.h            |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/audio.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/balloon3.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/bitfield.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/camera.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/colibri.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/corgi.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/csb726.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/debug-macro.S             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/dma.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-gpio.h            |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-irq.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/gpio.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/gumstix.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/h5000.h                   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/hardware.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/hx4700.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h                      |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/irda.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/irqs.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/littleton.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/lpd270.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/lubbock.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/magician.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mainstone.h               |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa25x.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa27x.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa2xx.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa300.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa320.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa3xx.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa930.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mioa701.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h                     |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mtd-xip.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mxm8x10.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/ohci.h                    |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palm27x.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmasoc.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmld.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmt5.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtc.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmte2.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtreo.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtx.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/palmz72.h                 |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pata_pxa.h                |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm027.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm990_baseboard.h        |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h                      |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/poodle.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x-udc.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x-udc.h              |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa2xx-regs.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa300.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa320.h                  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-regs.h             |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-u2d.h              |    0
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 .../include/{mach => mach-spear13xx}/spear1340_misc_regs.h             |    0
 arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/timex.h       |    0
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 .../{mach-u300/include/mach => mach-tegra/include/mach-tegra}/gpio.h   |    0
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 arch/arm/mach-ux500/include/{mach => mach-ux500}/crypto-ux500.h        |    0
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 .../include/mach => mach-vexpress/include/mach-vexpress}/gpio.h        |    0
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 .../{plat-mxc/include/mach => mach-vt8500/include/mach-vt8500}/gpio.h  |    0
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 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/nuc900_spi.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-clock.h      |    0
 arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ebi.h        |    0
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 arch/arm/plat-nomadik/include/{plat => plat-nomadik}/gpio-nomadik.h    |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/am33xx.h                |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/omap4-keypad.h          |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/omap54xx.h              |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/omap7xx.h               |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/sdrc.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/serial.h                |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/sram.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/tc.h                    |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/ti81xx.h                |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/uncompress.h            |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/usb.h                   |    0
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 arch/arm/plat-omap/include/{plat => plat-omap}/vram.h                  |    0
 arch/arm/plat-omap/include/{plat => plat-omap}/vrfb.h                  |    0
 arch/arm/plat-orion/include/{plat => plat-orion}/addr-map.h            |    0
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 arch/arm/plat-orion/include/{plat => plat-orion}/cache-feroceon-l2.h   |    0
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 arch/arm/plat-orion/include/{plat => plat-orion}/mv_xor.h              |    0
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 arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h                     |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h                     |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa27x_keypad.h           |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa3xx_nand.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/adc-core.h        |    0
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 arch/arm/plat-samsung/include/{plat => plat-samsung}/audio-simtec.h    |    0
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 arch/arm/plat-samsung/include/{plat => plat-samsung}/backlight.h       |    0
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 arch/arm/plat-samsung/include/{plat => plat-samsung}/clock-clksrc.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/clock.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/common-smdk.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq-core.h   |    0
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 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-pl330.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-s3c24xx.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/dma.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ehci.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-core.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-s3c2410.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fb.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/fimc-core.h       |    0
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 arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-core.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-fns.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/hwmon.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/iic-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/iic.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-uart.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-vic-timer.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irq.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/irqs.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad-core.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad.h          |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-base.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s3c.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s5p.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mci.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mfc.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/mipi_csis.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/nand-core.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/nand.h            |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/onenand-core.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pll.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pm.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/pwm-clock.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ac97.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-adc.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ata.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-dma.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb-v4.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iic.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iis.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-irqtype.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-nand.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-onenand.h    |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-rtc.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-sdhci.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-serial.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-spi.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-srom.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-timer.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-udc.h        |    0
 .../plat-samsung/include/{plat => plat-samsung}/regs-usb-hsotg-phy.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-watchdog.h   |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/rtc-core.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2410.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2412.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2416.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2443.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c244x.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c64xx-spi.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-clock.h       |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-time.h        |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/sdhci.h           |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/ts.h              |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/tv-core.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/udc.h             |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/uncompress.h      |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-control.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-phy.h         |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/wakeup-mask.h     |    0
 arch/arm/plat-samsung/include/{plat => plat-samsung}/watchdog-reset.h  |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/debug-macro.S         |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/gpio.h                |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/keyboard.h            |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/pl080.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/shirq.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/timex.h               |    0
 arch/arm/plat-spear/include/{plat => plat-spear}/uncompress.h          |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/clcd.h        |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/clock.h       |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/fpga-irq.h    |    0
 arch/arm/plat-versatile/include/{plat => plat-versatile}/sched_clock.h |    0
 1201 files changed, 0 insertions(+), 0 deletions(-)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_adc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_aic.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_dbgu.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pit.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_pmc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_ramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rstc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_rtt.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_shdwc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_st.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_tc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91_twi.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_emac.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_mc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91rm9200_sdramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9260_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9261_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9263_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_ddrsdr.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_sdramc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9_smc.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9g45_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9n12_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9rl_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91sam9x5_matrix.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at91x40.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/at_hdmac.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/atmel-mci.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/board.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/cpu.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/debug-macro.S (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gpio.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/gsia18s.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/hardware.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/io.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/memory.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/stamp9g20.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/system_rev.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/timex.h (100%)
 rename arch/arm/mach-at91/include/{mach => mach-at91}/uncompress.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/cap_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_def.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/chipcHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/ddrcReg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_priv.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/dmacHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/hw_cfg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/intcHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_addr.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/mm_io.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_def.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/secHw_inline.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/csp/tmrHw_reg.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/dma.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/entry-macro.S (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/hardware.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/irqs.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/memory_settings.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_nand.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/reg_umi.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timer.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/timex.h (100%)
 rename arch/arm/mach-bcmring/include/{mach => mach-bcmring}/uncompress.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/autcpu12.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/clps711x.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/debug-macro.S (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/entry-macro.S (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/hardware.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/irqs.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/memory.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/syspld.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/timex.h (100%)
 rename arch/arm/mach-clps711x/include/{mach => mach-clps711x}/uncompress.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/cns3xxx.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/debug-macro.S (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/irqs.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/pm.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/timex.h (100%)
 rename arch/arm/mach-cns3xxx/include/{mach => mach-cns3xxx}/uncompress.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/aemif.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/asp.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cdce949.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/clock.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/common.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cp_intc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpufreq.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cpuidle.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/cputype.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/da8xx.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/ddr2.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/debug-macro.S (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/edma.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/entry-macro.S (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio-davinci.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/gpio.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/hardware.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/i2c.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/irqs.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/keyscan.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mmc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/mux.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/nand.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/pm.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/psc.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/serial.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/spi.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/sram.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/time.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/timex.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/tnetv107x.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/uncompress.h (100%)
 rename arch/arm/mach-davinci/include/{mach => mach-davinci}/usb.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/bridge-regs.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/debug-macro.S (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/dove.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/entry-macro.S (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/gpio.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/hardware.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/io.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/irqs.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/pm.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/timex.h (100%)
 rename arch/arm/mach-dove/include/{mach => mach-dove}/uncompress.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/debug-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/entry-macro.S (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/hardware.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/io.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/irqs.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/memory.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/timex.h (100%)
 rename arch/arm/mach-ebsa110/include/{mach => mach-ebsa110}/uncompress.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/debug-macro.S (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/dma.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx-regs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_keypad.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ep93xx_spi.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/fb.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio-ep93xx.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/gpio.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/hardware.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/irqs.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/memory.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/platform.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/timex.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/ts72xx.h (100%)
 rename arch/arm/mach-ep93xx/include/{mach => mach-ep93xx}/uncompress.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/cpufreq.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/debug-macro.S (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/dma.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/dwmci.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/gpio.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/hardware.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/irqs.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/map.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/memory.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/ohci.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/pm-core.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/pmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-audss.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-clock.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-gpio.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-irq.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mct.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-mem.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-pmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/regs-usb-phy.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/sysmmu.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/timex.h (100%)
 rename arch/arm/mach-exynos/include/{mach => mach-exynos}/uncompress.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/debug-macro.S (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/entry-macro.S (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/hardware.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/io.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/irqs.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/isa-dma.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/memory.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/timex.h (100%)
 rename arch/arm/mach-footbridge/include/{mach => mach-footbridge}/uncompress.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/debug-macro.S (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/entry-macro.S (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/global_reg.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/gpio.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/hardware.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/irqs.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/system.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/timex.h (100%)
 rename arch/arm/mach-gemini/include/{mach => mach-gemini}/uncompress.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/boards.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/debug-macro.S (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/entry-macro.S (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7201-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/h7202-regs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/hardware.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/irqs.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/isa-dma.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/timex.h (100%)
 rename arch/arm/mach-h720x/include/{mach => mach-h720x}/uncompress.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/debug-macro.S (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/gpio.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/timex.h (100%)
 rename arch/arm/mach-highbank/include/{mach => mach-highbank}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/3ds_debugboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lilly.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31lite.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-mx31moboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/board-pcm038.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/clock.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/common.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/cpuidle.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/debug-macro.S (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/devices-common.h (100%)
 rename arch/arm/mach-imx/include/{mach => mach-imx}/dma-mx1-mx2.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/dma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/esdhc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/eukrea-baseboards.h (100%)
 rename arch/arm/{mach-msm/include/mach => mach-imx/include/mach-imx}/gpio.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/hardware.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/i2c.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iim.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imx-uart.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/imxfb.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iomux-v3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ipu.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/iram.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/irqs.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mmc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx1_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21-usbhost.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2_cam.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx31.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3_camera.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3fb.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx3x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mx6q.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_ehci.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/mxc_nand.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/sdma.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/spi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ssi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/timex.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/ulpi.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/uncompress.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/include/mach-imx}/usb.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/cm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/debug-macro.S (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/hardware.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/impd1.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/io.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/irqs.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/lm.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/memory.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/platform.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/timex.h (100%)
 rename arch/arm/mach-integrator/include/{mach => mach-integrator}/uncompress.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/adma.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/debug-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/entry-macro.S (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/hardware.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/io.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iop13xx.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/iq81340.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/irqs.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/memory.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/msi.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/pci.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/time.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/timex.h (100%)
 rename arch/arm/mach-iop13xx/include/{mach => mach-iop13xx}/uncompress.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/adma.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/debug-macro.S (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/entry-macro.S (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/glantank.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/gpio.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/hardware.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/io.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iop32x.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq31244.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/iq80321.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/irqs.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/n2100.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/time.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/timex.h (100%)
 rename arch/arm/mach-iop32x/include/{mach => mach-iop32x}/uncompress.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/adma.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/debug-macro.S (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/entry-macro.S (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/gpio.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/hardware.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/io.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iop33x.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80331.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/iq80332.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/irqs.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/time.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/timex.h (100%)
 rename arch/arm/mach-iop33x/include/{mach => mach-iop33x}/uncompress.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/cpu.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/debug-macro.S (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/entry-macro.S (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/gpio.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/hardware.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/io.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/irqs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp46x_ts.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/ixp4xx-regs.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/npe.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/platform.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/qmgr.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/timex.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/udc.h (100%)
 rename arch/arm/mach-ixp4xx/include/{mach => mach-ixp4xx}/uncompress.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/bridge-regs.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/debug-macro.S (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/entry-macro.S (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/gpio.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/hardware.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/io.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/irqs.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/kirkwood.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-netxbig.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/leds-ns2.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/timex.h (100%)
 rename arch/arm/mach-kirkwood/include/{mach => mach-kirkwood}/uncompress.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/debug-macro.S (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/devices.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/entry-macro.S (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio-ks8695.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/hardware.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/irqs.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/memory.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-gpio.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-hpna.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-irq.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-lan.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-mem.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-misc.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-pci.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-switch.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-sys.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-timer.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-uart.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/regs-wan.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/timex.h (100%)
 rename arch/arm/mach-ks8695/include/{mach => mach-ks8695}/uncompress.h (100%)
 rename arch/arm/mach-l7200/include/{mach => mach-l7200}/debug-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/board.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/debug-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/entry-macro.S (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio-lpc32xx.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/gpio.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/hardware.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/irqs.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/platform.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/timex.h (100%)
 rename arch/arm/mach-lpc32xx/include/{mach => mach-lpc32xx}/uncompress.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/addr-map.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/cputype.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/debug-macro.S (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/devices.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/dma.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/entry-macro.S (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/gpio.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/hardware.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/irqs.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa168.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp-pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mfp.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-mmp2.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pm-pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa168.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/pxa910.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apbc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-apmu.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-icu.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-rtc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-smc.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-timers.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/regs-usb.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/sram.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/teton_bga.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/timex.h (100%)
 rename arch/arm/mach-mmp/include/{mach => mach-mmp}/uncompress.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/board.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/clk.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/debug-macro.S (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/dma.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/entry-macro.S (100%)
 rename arch/arm/{mach-mxs/include/mach => mach-msm/include/mach-msm}/gpio.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/hardware.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/iommu_hw-8xxx.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/irqs.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_fb.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_gpiomux.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x00.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-7x30.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8960.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x50.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap-8x60.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_iomap.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/msm_smd.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/sirc.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/system.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/timex.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/uncompress.h (100%)
 rename arch/arm/mach-msm/include/{mach => mach-msm}/vreg.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/bridge-regs.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/debug-macro.S (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/entry-macro.S (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/gpio.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/hardware.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/io.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/irqs.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/mv78xx0.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/timex.h (100%)
 rename arch/arm/mach-mv78xx0/include/{mach => mach-mv78xx0}/uncompress.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/armada-370-xp.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/debug-macro.S (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/timex.h (100%)
 rename arch/arm/mach-mvebu/include/{mach => mach-mvebu}/uncompress.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/common.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/debug-macro.S (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/devices-common.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/digctl.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/entry-macro.S (100%)
 rename arch/arm/{mach-picoxcell/include/mach => mach-mxs/include/mach-mxs}/gpio.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/hardware.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx23.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux-mx28.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/iomux.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/irqs.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mx23.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mx28.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/mxs.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/timex.h (100%)
 rename arch/arm/mach-mxs/include/{mach => mach-mxs}/uncompress.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/debug-macro.S (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/eth.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/hardware.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/irqs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/netx-regs.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/param.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/pfifo.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/timex.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/uncompress.h (100%)
 rename arch/arm/mach-netx/include/{mach => mach-netx}/xc.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/debug-macro.S (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/fsmc.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/gpio.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/hardware.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/irqs.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/nand.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/timex.h (100%)
 rename arch/arm/mach-nomadik/include/{mach => mach-nomadik}/uncompress.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/ams-delta-fiq.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/camera.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/debug-macro.S (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/entry-macro.S (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/gpio.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/hardware.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/io.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/irqs.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcd_dma.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/lcdc.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/memory.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/mtd-xip.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/smp.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/timex.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/uncompress.h (100%)
 rename arch/arm/mach-omap1/include/{mach => mach-omap1}/usb.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/am35xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/barriers.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-rx51.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/board-zoom.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_core_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_pad_wkup_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/ctrl_module_wkup_44xx.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/debug-macro.S (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/gpio.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/hardware.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/id.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/irqs.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-secure.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/omap-wakeupgen.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/smp.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/timex.h (100%)
 rename arch/arm/mach-omap2/include/{mach => mach-omap2}/uncompress.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/bridge-regs.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/debug-macro.S (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/entry-macro.S (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/gpio.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/hardware.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/io.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/irqs.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/orion5x.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/timex.h (100%)
 rename arch/arm/mach-orion5x/include/{mach => mach-orion5x}/uncompress.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/debug-macro.S (100%)
 rename arch/arm/{mach-realview/include/mach => mach-picoxcell/include/mach-picoxcell}/gpio.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/hardware.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/map.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/picoxcell_soc.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/timex.h (100%)
 rename arch/arm/mach-picoxcell/include/{mach => mach-picoxcell}/uncompress.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/clock.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/debug-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/dma.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/entry-macro.S (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/gpio-pnx4008.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/hardware.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irq.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/irqs.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/param.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/platform.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/pm.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/timex.h (100%)
 rename arch/arm/mach-pnx4008/include/{mach => mach-pnx4008}/uncompress.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/clkdev.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/debug-macro.S (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/entry-macro.S (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/gpio.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/hardware.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/irqs.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/map.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/timex.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/uart.h (100%)
 rename arch/arm/mach-prima2/include/{mach => mach-prima2}/uncompress.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/addr-map.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/arcom-pcmcia.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/audio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/balloon3.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/bitfield.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/camera.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/colibri.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/corgi.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/csb726.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/debug-macro.S (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/dma.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-gpio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/eseries-irq.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/gpio.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/gumstix.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/h5000.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/hardware.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/hx4700.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irda.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/irqs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/littleton.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lpd270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/lubbock.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/magician.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mainstone.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa25x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa2xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa300.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa320.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa3xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp-pxa930.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mfp.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mioa701.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mtd-xip.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/mxm8x10.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/ohci.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palm27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmasoc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmld.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmt5.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmte2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtreo.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmtx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/palmz72.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pata_pxa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm027.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pcm990_baseboard.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/poodle.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x-udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa25x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x-udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa27x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa2xx-regs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa300.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa320.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-regs.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx-u2d.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa3xx.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_rotary.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa930_trkball.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxa95x.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/pxafb.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ac97.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-lcd.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-ost.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-rtc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-u2d.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/regs-uart.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/reset.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/sharpsl_pm.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/smemc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/spitz.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/timex.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/tosa_bt.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/trizeps4.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/uncompress.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/viper.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/vpac270.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zeus.h (100%)
 rename arch/arm/mach-pxa/include/{mach => mach-pxa}/zylonite.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/barriers.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-eb.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pb1176.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pb11mp.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pba8.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/board-pbx.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/clkdev.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/debug-macro.S (100%)
 rename arch/arm/{mach-tegra/include/mach => mach-realview/include/mach-realview}/gpio.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/hardware.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-eb.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb1176.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pb11mp.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pba8.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs-pbx.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/irqs.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/memory.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/platform.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/timex.h (100%)
 rename arch/arm/mach-realview/include/{mach => mach-realview}/uncompress.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/acornfb.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/debug-macro.S (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/entry-macro.S (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/hardware.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/io.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/irqs.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/isa-dma.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/memory.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/timex.h (100%)
 rename arch/arm/mach-rpc/include/{mach => mach-rpc}/uncompress.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/anubis-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/bast-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/debug-macro.S (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/dma.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/entry-macro.S (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/fb.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-fns.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-nrs.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio-track.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/gta02.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940-latch.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/h1940.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/hardware.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/idle.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/io.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/irqs.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/leds-gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/osiris-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/otom-map.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/pm-core.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-dsc.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-gpio.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-lcd.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-power.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2412.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416-mem.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2416.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-s3c2443-clock.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/regs-sdi.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/tick.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/timex.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/uncompress.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-cpld.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-irq.h (100%)
 rename arch/arm/mach-s3c24xx/include/{mach => mach-s3c24xx}/vr1000-map.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/crag6410.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/debug-macro.S (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/dma.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/hardware.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/irqs.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/map.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/pm-core.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-clock.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio-memport.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-gpio.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-irq.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-modem.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-srom.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-sys.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/regs-syscon-power.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/tick.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/timex.h (100%)
 rename arch/arm/mach-s3c64xx/include/{mach => mach-s3c64xx}/uncompress.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/debug-macro.S (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/dma.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/gpio.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/hardware.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/i2c.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/irqs.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/map.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/pm-core.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-clock.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-gpio.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/regs-irq.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/s5p64x0-clock.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/tick.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/timex.h (100%)
 rename arch/arm/mach-s5p64x0/include/{mach => mach-s5p64x0}/uncompress.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/debug-macro.S (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/dma.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/entry-macro.S (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/gpio.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/hardware.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/irqs.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/map.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-clock.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-gpio.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/regs-irq.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/tick.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/timex.h (100%)
 rename arch/arm/mach-s5pc100/include/{mach => mach-s5pc100}/uncompress.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/debug-macro.S (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/dma.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/gpio.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/hardware.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/irqs.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/map.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/memory.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/pm-core.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-audss.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-clock.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-gpio.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-irq.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/regs-sys.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/tick.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/timex.h (100%)
 rename arch/arm/mach-s5pv210/include/{mach => mach-s5pv210}/uncompress.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1100.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1101.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/SA-1111.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/assabet.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/badge4.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/bitfield.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/cerf.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/collie.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/debug-macro.S (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/entry-macro.S (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/gpio.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/h3xxx.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/hardware.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/irqs.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/jornada720.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/lart.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/mcp.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/memory.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/mtd-xip.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/nanoengine.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/neponset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/reset.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/shannon.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/simpad.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/timex.h (100%)
 rename arch/arm/mach-sa1100/include/{mach => mach-sa1100}/uncompress.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/debug-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/entry-macro.S (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/framebuffer.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/hardware.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/io.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/irqs.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/isa-dma.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/memory.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/timex.h (100%)
 rename arch/arm/mach-shark/include/{mach => mach-shark}/uncompress.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/clkdev.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/common.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma-register.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/dma.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/emev2.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/gpio.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/hardware.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-ap4evb.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/head-mackerel.txt (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/intc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/irqs.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/memory.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-ap4eb.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc-mackerel.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/mmc.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/pm-rmobile.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7740.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/r8a7779.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi-sh7372.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sdhi.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7367.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7372.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh7377.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/sh73a0.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/system.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/timex.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/uncompress.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot.h (100%)
 rename arch/arm/mach-shmobile/include/{mach => mach-shmobile}/zboot_macros.h (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/debug-macro.S (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/timex.h (100%)
 rename arch/arm/mach-socfpga/include/{mach => mach-socfpga}/uncompress.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/dma.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/generic.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/gpio.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/hardware.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/irqs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1310_misc_regs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/spear1340_misc_regs.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/timex.h (100%)
 rename arch/arm/mach-spear13xx/include/{mach => mach-spear13xx}/uncompress.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/generic.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/gpio.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/hardware.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/irqs.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/misc_regs.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/spear.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/timex.h (100%)
 rename arch/arm/mach-spear3xx/include/{mach => mach-spear3xx}/uncompress.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/debug-macro.S (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/generic.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/gpio.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/hardware.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/irqs.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/misc_regs.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/spear.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/timex.h (100%)
 rename arch/arm/mach-spear6xx/include/{mach => mach-spear6xx}/uncompress.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/clk.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/debug-macro.S (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/dma.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/gpio-tegra.h (100%)
 rename arch/arm/{mach-u300/include/mach => mach-tegra/include/mach-tegra}/gpio.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/io.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/iomap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irammap.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/irqs.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/kbc.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/pinconf-tegra.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/powergate.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/sdhci.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/smmu.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/suspend.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra-ahb.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/tegra_wm8903_pdata.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/timex.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/uncompress.h (100%)
 rename arch/arm/mach-tegra/include/{mach => mach-tegra}/usb_phy.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/clkdev.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/coh901318.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/debug-macro.S (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/dma_channels.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/gpio-u300.h (100%)
 rename arch/arm/{mach-versatile/include/mach => mach-u300/include/mach-u300}/gpio.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/hardware.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/irqs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/platform.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/syscon.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/timex.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/u300-regs.h (100%)
 rename arch/arm/mach-u300/include/{mach => mach-u300}/uncompress.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/crypto-ux500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/db8500-regs.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/debug-macro.S (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/devices.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/gpio.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/hardware.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/id.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-board-mop500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs-db8500.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/irqs.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/msp.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/setup.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/timex.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/uncompress.h (100%)
 rename arch/arm/mach-ux500/include/{mach => mach-ux500}/usb.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/clkdev.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/debug-macro.S (100%)
 rename arch/arm/{mach-vexpress/include/mach => mach-versatile/include/mach-versatile}/gpio.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/hardware.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/io.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/irqs.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/platform.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/timex.h (100%)
 rename arch/arm/mach-versatile/include/{mach => mach-versatile}/uncompress.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/ct-ca9x4.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/debug-macro.S (100%)
 rename arch/arm/{mach-vt8500/include/mach => mach-vexpress/include/mach-vexpress}/gpio.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/hardware.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/irqs.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/motherboard.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/timex.h (100%)
 rename arch/arm/mach-vexpress/include/{mach => mach-vexpress}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/debug-macro.S (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/entry-macro.S (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-vt8500/include/mach-vt8500}/gpio.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/hardware.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/i8042.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/restart.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/timex.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/uncompress.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500_regs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/vt8500fb.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_irqs.h (100%)
 rename arch/arm/mach-vt8500/include/{mach => mach-vt8500}/wm8505_regs.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/entry-macro.S (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/fb.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/gpio.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/hardware.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/i2c.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/irqs.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/map.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/mfp.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/nuc900_spi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-clock.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ebi.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-gcr.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-irq.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-ldm.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-serial.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-timer.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/regs-usb.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/timex.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/uncompress.h (100%)
 rename arch/arm/mach-w90x900/include/{mach => mach-w90x900}/w90p910_keypad.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/clkdev.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/debug-macro.S (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/hardware.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/irqs.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/timex.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/uart.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/uncompress.h (100%)
 rename arch/arm/mach-zynq/include/{mach => mach-zynq}/zynq_soc.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/gpio-nomadik.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/mtu.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/pincfg.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ske.h (100%)
 rename arch/arm/plat-nomadik/include/{plat => plat-nomadik}/ste_dma40.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/am33xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-ams-delta.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-sx1.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board-voiceblue.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/board.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clkdev_omap.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/clock.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/common.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/cpu.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dma-44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dma.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dmtimer.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/dsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/flash.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/fpga.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio-switch.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpio.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smc91x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc-smsc911x.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/gpmc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/hardware.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/hdq1w.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/i2c.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iommu.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iommu2.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iopgtable.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/iovmm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irda.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs-44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/irqs.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l3_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_2xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/l4_3xxx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/lcd_mipid.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/led.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mailbox.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcbsp.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mcspi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/menelaus.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mmc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/multi.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/mux.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/nand.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-pm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-secure.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap-serial.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap1510.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap16xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap24xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap34xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap4-keypad.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap44xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap54xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap7xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap_device.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/omap_hwmod.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/onenand.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/param.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/prcm.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/remoteproc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sdrc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/serial.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/sram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/tc.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/ti81xx.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/timex.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/uncompress.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/usb.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/voltage.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vram.h (100%)
 rename arch/arm/plat-omap/include/{plat => plat-omap}/vrfb.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/addr-map.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/audio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/cache-feroceon-l2.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/common.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/ehci-orion.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/gpio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/irq.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mpp.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mv_xor.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/mvsdio.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/orion_nand.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/pcie.h (100%)
 rename arch/arm/plat-orion/include/{plat => plat-orion}/time.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa27x_keypad.h (100%)
 rename arch/arm/plat-pxa/include/{plat => plat-pxa}/pxa3xx_nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio-simtec.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/audio.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/backlight.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/camport.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock-clksrc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/common-smdk.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu-freq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/cpu.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/debug-macro.S (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/devs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-ops.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-pl330.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma-s3c24xx.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/dma.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ehci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb-s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fimc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/fiq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg-helpers.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-cfg.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/gpio-fns.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/hwmon.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-uart.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq-vic-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irq.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/irqs.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/keypad.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-base.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s3c.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/map-s5p.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mfc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/mipi_csis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/onenand-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pll.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pm.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/pwm-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ac97.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-adc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-ata.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-dma.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb-v4.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-fb.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iic.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-iis.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-irqtype.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-nand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-onenand.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-rtc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-sdhci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-serial.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-srom.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-timer.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-udc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-usb-hsotg-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/regs-watchdog.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/rtc-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2410.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2412.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2416.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c2443.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c244x.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s3c64xx-spi.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-clock.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/s5p-time.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/sdhci.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/ts.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/tv-core.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/udc.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/uncompress.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-control.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/usb-phy.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/wakeup-mask.h (100%)
 rename arch/arm/plat-samsung/include/{plat => plat-samsung}/watchdog-reset.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/debug-macro.S (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/gpio.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/keyboard.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/pl080.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/shirq.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/timex.h (100%)
 rename arch/arm/plat-spear/include/{plat => plat-spear}/uncompress.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clcd.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/clock.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/fpga-irq.h (100%)
 rename arch/arm/plat-versatile/include/{plat => plat-versatile}/sched_clock.h (100%)

diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach-at91/at91_adc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_adc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_adc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach-at91/at91_aic.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_aic.h
rename to arch/arm/mach-at91/include/mach-at91/at91_aic.h
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_dbgu.h
rename to arch/arm/mach-at91/include/mach-at91/at91_dbgu.h
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach-at91/at91_matrix.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_matrix.h
rename to arch/arm/mach-at91/include/mach-at91/at91_matrix.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach-at91/at91_pio.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pio.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pio.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach-at91/at91_pit.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pit.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pit.h
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach-at91/at91_pmc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_pmc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_ramc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_ramc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach-at91/at91_rstc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rstc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rstc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach-at91/at91_rtc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach-at91/at91_rtt.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_rtt.h
rename to arch/arm/mach-at91/include/mach-at91/at91_rtt.h
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_shdwc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_shdwc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach-at91/at91_st.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_st.h
rename to arch/arm/mach-at91/include/mach-at91/at91_st.h
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach-at91/at91_tc.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_tc.h
rename to arch/arm/mach-at91/include/mach-at91/at91_tc.h
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach-at91/at91_twi.h
similarity index 100%
rename from arch/arm/mach-at91/include/mach/at91_twi.h
rename to arch/arm/mach-at91/include/mach-at91/at91_twi.h

Cut here for review purposes. None of the other file renames have any
other changes, so there is no point spamming the mailing lists with
this. The full patch is available at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=62dd65e1ac307d2ba15f31cc2f754b8e348055c7


From arnd at arndb.de  Tue Aug 21 11:59:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:59:28 -0000
Subject: [RFC 0/4] ARM: multiplatform: rename all mach headers
Message-ID: <1345564724-14466-1-git-send-email-arnd@arndb.de>

I've created this series some time ago, and updated it now to
v3.6-rc1. The idea is to get us a big step closer to the
single zImage kernel across multiple ARM platforms by
untangling the duplicate header file names.

There are two branches available in the arm-soc tree:

1. This series,
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/mach-headers
   This just moves header files around and changes most of the
   files including them. There are a few remaining drivers
   and platform files that keep including a generic file name
   like <mach/uncompress.h>. It remains possible to do that,
   and I've run extensive tests to ensure I did not break
   anything with this. However, each of these instances means
   that there is something that stops working when you get to
   the real multiplatform kernel and we still need to deal
   with them one by one.

2. Actually enabling CONFIG_ARCH_MULTIPLATFORM
   http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=shortlog;h=refs/heads/testing/multiplatform
   This builds on top of the first series, but is much more
   experimental. It shows how a multiplatform kernel can look
   like, by allowing to build vexpress, ux500, imx and omap2
   together in one kernel, but at the same time breaking some of
   their features.

I would like to get the first series merged in v3.7 if we can agree
on the general approach. So far, feedback in Linaro internal
meetings has been very positive, but Russell had concerns when
we first discussed it a few months ago.

A patch set this large means a lot of churn, and there are a few
ways we could deal with this:

a) Put the branch into linux-next now, and have everyone who
encounters conflicts pull it into their own branch to resolve
the conflicts. This can be a lot of work, and it means we
cannot rebase this branch any more.

b) Involve Linus Torvalds in the process and get him to
take the series at the end of the v3.7 merge window, after
rebasing it on top of all the other branches he merged.
This means it happens pretty much ad-hoc and there is little
testing on the patches that actually get merged.

c) Split the series and submit the first two branches at
the start of the merge window, and do the changes to all
the drivers either at the end of the v3.7 merge window
(after rebasing) or merge them through the subsystem
maintainer trees in small chunks for v3.8. This can minimize
the problems of the other two approaches, but means the process
takes longer to get to the same result.

	Arnd


[second attempt to send these patches, the first one was rejected by
lists.infradead.org, this one uses a different smtp setup]

Arnd Bergmann (4):
  [RFC] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
  [RFC] ARM: mass move of mach-*/plat-* header files
  [RFC] ARM: treewide: scripted conversion to mach-*/*.h
  [RFC] ARM: treewide: manually change more mach-*/*.h includes

 Documentation/spi/ep93xx_spi                       |    2 +-
 arch/arm/Makefile                                  |    1 +
 arch/arm/boot/compressed/head-shmobile.S           |    2 +-
 arch/arm/boot/compressed/sdhi-shmobile.c           |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |   10 +-
 arch/arm/mach-at91/at91rm9200_devices.c            |    8 +-
 arch/arm/mach-at91/at91rm9200_time.c               |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |   12 +-
 arch/arm/mach-at91/at91sam9260_devices.c           |   14 +-
 arch/arm/mach-at91/at91sam9261.c                   |   10 +-
 arch/arm/mach-at91/at91sam9261_devices.c           |   10 +-
 arch/arm/mach-at91/at91sam9263.c                   |    8 +-
 arch/arm/mach-at91/at91sam9263_devices.c           |   10 +-
 arch/arm/mach-at91/at91sam926x_time.c              |    2 +-
 arch/arm/mach-at91/at91sam9_alt_reset.S            |    6 +-
 arch/arm/mach-at91/at91sam9g45.c                   |    8 +-
 arch/arm/mach-at91/at91sam9g45_devices.c           |   16 +-
 arch/arm/mach-at91/at91sam9g45_reset.S             |    6 +-
 arch/arm/mach-at91/at91sam9n12.c                   |    8 +-
 arch/arm/mach-at91/at91sam9rl.c                    |   12 +-
 arch/arm/mach-at91/at91sam9rl_devices.c            |   12 +-
 arch/arm/mach-at91/at91sam9x5.c                    |    8 +-
 arch/arm/mach-at91/at91x40.c                       |    8 +-
 arch/arm/mach-at91/at91x40_time.c                  |    4 +-
 arch/arm/mach-at91/board-1arm.c                    |    8 +-
 arch/arm/mach-at91/board-afeb-9260v1.c             |    6 +-
 arch/arm/mach-at91/board-cam60.c                   |    8 +-
 arch/arm/mach-at91/board-carmeva.c                 |    6 +-
 arch/arm/mach-at91/board-cpu9krea.c                |   12 +-
 arch/arm/mach-at91/board-cpuat91.c                 |   12 +-
 arch/arm/mach-at91/board-csb337.c                  |    6 +-
 arch/arm/mach-at91/board-csb637.c                  |    6 +-
 arch/arm/mach-at91/board-dt.c                      |    4 +-
 arch/arm/mach-at91/board-eb01.c                    |    6 +-
 arch/arm/mach-at91/board-eb9200.c                  |    6 +-
 arch/arm/mach-at91/board-ecbat91.c                 |    8 +-
 arch/arm/mach-at91/board-eco920.c                  |   10 +-
 arch/arm/mach-at91/board-flexibity.c               |    6 +-
 arch/arm/mach-at91/board-foxg20.c                  |    8 +-
 arch/arm/mach-at91/board-gsia18s.c                 |   10 +-
 arch/arm/mach-at91/board-kafa.c                    |    8 +-
 arch/arm/mach-at91/board-kb9202.c                  |   12 +-
 arch/arm/mach-at91/board-neocore926.c              |    8 +-
 arch/arm/mach-at91/board-pcontrol-g20.c            |    8 +-
 arch/arm/mach-at91/board-picotux200.c              |   10 +-
 arch/arm/mach-at91/board-qil-a9260.c               |   10 +-
 arch/arm/mach-at91/board-rm9200dk.c                |   10 +-
 arch/arm/mach-at91/board-rm9200ek.c                |   10 +-
 arch/arm/mach-at91/board-rsi-ews.c                 |    6 +-
 arch/arm/mach-at91/board-sam9-l9260.c              |    8 +-
 arch/arm/mach-at91/board-sam9260ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9261ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9263ek.c               |   12 +-
 arch/arm/mach-at91/board-sam9g20ek.c               |   10 +-
 arch/arm/mach-at91/board-sam9m10g45ek.c            |   12 +-
 arch/arm/mach-at91/board-sam9rlek.c                |   10 +-
 arch/arm/mach-at91/board-snapper9260.c             |    8 +-
 arch/arm/mach-at91/board-stamp9g20.c               |    6 +-
 arch/arm/mach-at91/board-usb-a926x.c               |   10 +-
 arch/arm/mach-at91/board-yl-9200.c                 |   12 +-
 arch/arm/mach-at91/clock.c                         |    6 +-
 arch/arm/mach-at91/cpuidle.c                       |    2 +-
 arch/arm/mach-at91/gpio.c                          |    4 +-
 .../include/{mach => mach-at91}/at91_adc.h         |    0
 .../include/{mach => mach-at91}/at91_aic.h         |    0
 .../include/{mach => mach-at91}/at91_dbgu.h        |    0
 .../include/{mach => mach-at91}/at91_matrix.h      |    0
 .../include/{mach => mach-at91}/at91_pio.h         |    0
 .../include/{mach => mach-at91}/at91_pit.h         |    0
 .../include/{mach => mach-at91}/at91_pmc.h         |    0
 arch/arm/mach-at91/include/mach-at91/at91_ramc.h   |   32 +
 .../include/{mach => mach-at91}/at91_rstc.h        |    0
 .../include/{mach => mach-at91}/at91_rtc.h         |    0
 .../include/{mach => mach-at91}/at91_rtt.h         |    0
 .../include/{mach => mach-at91}/at91_shdwc.h       |    0
 .../include/{mach => mach-at91}/at91_st.h          |    0
 .../include/{mach => mach-at91}/at91_tc.h          |    0
 .../include/{mach => mach-at91}/at91_twi.h         |    0
 .../include/{mach => mach-at91}/at91rm9200.h       |    0
 .../include/{mach => mach-at91}/at91rm9200_emac.h  |    0
 .../include/{mach => mach-at91}/at91rm9200_mc.h    |    0
 .../{mach => mach-at91}/at91rm9200_sdramc.h        |    0
 .../include/{mach => mach-at91}/at91sam9260.h      |    0
 .../{mach => mach-at91}/at91sam9260_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9261.h      |    0
 .../{mach => mach-at91}/at91sam9261_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9263.h      |    0
 .../{mach => mach-at91}/at91sam9263_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9_ddrsdr.h  |    0
 .../include/{mach => mach-at91}/at91sam9_sdramc.h  |    0
 .../arm/mach-at91/include/mach-at91/at91sam9_smc.h |  100 ++
 .../include/{mach => mach-at91}/at91sam9g45.h      |    0
 .../{mach => mach-at91}/at91sam9g45_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9n12.h      |    0
 .../{mach => mach-at91}/at91sam9n12_matrix.h       |    0
 .../include/{mach => mach-at91}/at91sam9rl.h       |    0
 .../{mach => mach-at91}/at91sam9rl_matrix.h        |    0
 .../include/{mach => mach-at91}/at91sam9x5.h       |    0
 .../{mach => mach-at91}/at91sam9x5_matrix.h        |    0
 .../include/{mach => mach-at91}/at91x40.h          |    0
 .../include/{mach => mach-at91}/at_hdmac.h         |    0
 arch/arm/mach-at91/include/mach-at91/atmel-mci.h   |   24 +
 .../mach-at91/include/{mach => mach-at91}/board.h  |    0
 .../mach-at91/include/{mach => mach-at91}/cpu.h    |    0
 arch/arm/mach-at91/include/mach-at91/debug-macro.S |   43 +
 .../mach-at91/include/{mach => mach-at91}/gpio.h   |    0
 .../include/{mach => mach-at91}/gsia18s.h          |    0
 arch/arm/mach-at91/include/mach-at91/hardware.h    |  110 ++
 .../arm/mach-at91/include/{mach => mach-at91}/io.h |    0
 arch/arm/mach-at91/include/mach-at91/memory.h      |   26 +
 .../include/{mach => mach-at91}/stamp9g20.h        |    0
 .../include/{mach => mach-at91}/system_rev.h       |    0
 arch/arm/mach-at91/include/mach-at91/timex.h       |   37 +
 arch/arm/mach-at91/include/mach-at91/uncompress.h  |  201 +++
 arch/arm/mach-at91/include/mach/at91_ramc.h        |   32 -
 arch/arm/mach-at91/include/mach/at91sam9_smc.h     |  100 --
 arch/arm/mach-at91/include/mach/atmel-mci.h        |   24 -
 arch/arm/mach-at91/include/mach/debug-macro.S      |   43 -
 arch/arm/mach-at91/include/mach/hardware.h         |  110 --
 arch/arm/mach-at91/include/mach/memory.h           |   26 -
 arch/arm/mach-at91/include/mach/timex.h            |   37 -
 arch/arm/mach-at91/include/mach/uncompress.h       |  201 ---
 arch/arm/mach-at91/irq.c                           |    4 +-
 arch/arm/mach-at91/leds.c                          |    2 +-
 arch/arm/mach-at91/pm.c                            |   10 +-
 arch/arm/mach-at91/pm.h                            |    4 +-
 arch/arm/mach-at91/pm_slowclock.S                  |    6 +-
 arch/arm/mach-at91/sam9_smc.c                      |    2 +-
 arch/arm/mach-at91/setup.c                         |   10 +-
 arch/arm/mach-bcmring/arch.c                       |   10 +-
 arch/arm/mach-bcmring/clock.c                      |    8 +-
 arch/arm/mach-bcmring/clock.h                      |    2 +-
 arch/arm/mach-bcmring/core.c                       |   10 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |    2 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |    6 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      |    4 +-
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |    2 +-
 arch/arm/mach-bcmring/dma.c                        |    4 +-
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/intcHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/reg.h            |    2 +-
 .../include/{mach => mach-bcmring}/csp/cap.h       |    0
 .../include/mach-bcmring/csp/cap_inline.h          |  409 +++++
 .../include/mach-bcmring/csp/chipcHw_def.h         | 1123 +++++++++++++
 .../include/mach-bcmring/csp/chipcHw_inline.h      | 1673 ++++++++++++++++++++
 .../include/mach-bcmring/csp/chipcHw_reg.h         |  530 +++++++
 .../include/mach-bcmring/csp/ddrcReg.h             |  872 ++++++++++
 .../{mach => mach-bcmring}/csp/dmacHw_priv.h       |    0
 .../include/mach-bcmring/csp/dmacHw_reg.h          |  406 +++++
 .../mach-bcmring/include/mach-bcmring/csp/hw_cfg.h |   73 +
 .../include/mach-bcmring/csp/intcHw_reg.h          |  246 +++
 .../include/{mach => mach-bcmring}/csp/mm_addr.h   |    0
 .../mach-bcmring/include/mach-bcmring/csp/mm_io.h  |  147 ++
 .../include/mach-bcmring/csp/secHw_def.h           |  100 ++
 .../{mach => mach-bcmring}/csp/secHw_inline.h      |    0
 .../include/mach-bcmring/csp/tmrHw_reg.h           |   82 +
 arch/arm/mach-bcmring/include/mach-bcmring/dma.h   |  630 ++++++++
 .../include/mach-bcmring/entry-macro.S             |   76 +
 .../mach-bcmring/include/mach-bcmring/hardware.h   |   57 +
 .../include/{mach => mach-bcmring}/irqs.h          |    0
 .../{mach => mach-bcmring}/memory_settings.h       |    0
 .../mach-bcmring/include/mach-bcmring/reg_nand.h   |   66 +
 .../mach-bcmring/include/mach-bcmring/reg_umi.h    |  237 +++
 .../include/{mach => mach-bcmring}/timer.h         |    0
 .../include/{mach => mach-bcmring}/timex.h         |    0
 .../mach-bcmring/include/mach-bcmring/uncompress.h |   43 +
 .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
 .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
 .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 --------------------
 .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
 .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
 .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
 arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
 arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
 arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
 arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
 arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
 arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
 arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
 arch/arm/mach-bcmring/irq.c                        |    6 +-
 arch/arm/mach-bcmring/mm.c                         |    4 +-
 arch/arm/mach-bcmring/timer.c                      |    2 +-
 arch/arm/mach-clps711x/autcpu12.c                  |    4 +-
 arch/arm/mach-clps711x/cdb89712.c                  |    2 +-
 arch/arm/mach-clps711x/ceiva.c                     |    2 +-
 arch/arm/mach-clps711x/common.c                    |    2 +-
 arch/arm/mach-clps711x/edb7211-mm.c                |    2 +-
 arch/arm/mach-clps711x/fortunet.c                  |    2 +-
 .../include/{mach => mach-clps711x}/autcpu12.h     |    0
 .../include/{mach => mach-clps711x}/clps711x.h     |    0
 .../include/mach-clps711x/debug-macro.S            |   44 +
 .../include/mach-clps711x/entry-macro.S            |   51 +
 .../mach-clps711x/include/mach-clps711x/hardware.h |  175 ++
 .../include/{mach => mach-clps711x}/irqs.h         |    0
 .../include/{mach => mach-clps711x}/memory.h       |    0
 .../include/{mach => mach-clps711x}/syspld.h       |    0
 .../include/{mach => mach-clps711x}/timex.h        |    0
 .../include/mach-clps711x/uncompress.h             |   57 +
 arch/arm/mach-clps711x/include/mach/debug-macro.S  |   44 -
 arch/arm/mach-clps711x/include/mach/entry-macro.S  |   51 -
 arch/arm/mach-clps711x/include/mach/hardware.h     |  175 --
 arch/arm/mach-clps711x/include/mach/uncompress.h   |   57 -
 arch/arm/mach-clps711x/p720t-leds.c                |    2 +-
 arch/arm/mach-clps711x/p720t.c                     |    4 +-
 arch/arm/mach-cns3xxx/cns3420vb.c                  |    4 +-
 arch/arm/mach-cns3xxx/core.c                       |    2 +-
 arch/arm/mach-cns3xxx/devices.c                    |    6 +-
 .../include/{mach => mach-cns3xxx}/cns3xxx.h       |    0
 .../include/{mach => mach-cns3xxx}/debug-macro.S   |    0
 arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h  |   24 +
 .../include/{mach => mach-cns3xxx}/pm.h            |    0
 .../include/{mach => mach-cns3xxx}/timex.h         |    0
 .../mach-cns3xxx/include/mach-cns3xxx/uncompress.h |   54 +
 arch/arm/mach-cns3xxx/include/mach/irqs.h          |   24 -
 arch/arm/mach-cns3xxx/include/mach/uncompress.h    |   54 -
 arch/arm/mach-cns3xxx/pcie.c                       |    2 +-
 arch/arm/mach-cns3xxx/pm.c                         |    4 +-
 arch/arm/mach-davinci/aemif.c                      |    2 +-
 arch/arm/mach-davinci/board-da830-evm.c            |   14 +-
 arch/arm/mach-davinci/board-da850-evm.c            |   12 +-
 arch/arm/mach-davinci/board-dm355-evm.c            |   10 +-
 arch/arm/mach-davinci/board-dm355-leopard.c        |   10 +-
 arch/arm/mach-davinci/board-dm365-evm.c            |   14 +-
 arch/arm/mach-davinci/board-dm644x-evm.c           |   16 +-
 arch/arm/mach-davinci/board-dm646x-evm.c           |   14 +-
 arch/arm/mach-davinci/board-mityomapl138.c         |   12 +-
 arch/arm/mach-davinci/board-neuros-osd2.c          |   14 +-
 arch/arm/mach-davinci/board-omapl138-hawk.c        |    6 +-
 arch/arm/mach-davinci/board-sffsdr.c               |   10 +-
 arch/arm/mach-davinci/board-tnetv107x-evm.c        |   10 +-
 arch/arm/mach-davinci/cdce949.c                    |    4 +-
 arch/arm/mach-davinci/clock.c                      |    8 +-
 arch/arm/mach-davinci/common.c                     |    4 +-
 arch/arm/mach-davinci/cp_intc.c                    |    4 +-
 arch/arm/mach-davinci/cpufreq.c                    |    6 +-
 arch/arm/mach-davinci/cpuidle.c                    |    4 +-
 arch/arm/mach-davinci/da830.c                      |   14 +-
 arch/arm/mach-davinci/da850.c                      |   18 +-
 arch/arm/mach-davinci/davinci.h                    |    6 +-
 arch/arm/mach-davinci/devices-da8xx.c              |   10 +-
 arch/arm/mach-davinci/devices-tnetv107x.c          |    8 +-
 arch/arm/mach-davinci/devices.c                    |   16 +-
 arch/arm/mach-davinci/dm355.c                      |   22 +-
 arch/arm/mach-davinci/dm365.c                      |   24 +-
 arch/arm/mach-davinci/dm644x.c                     |   20 +-
 arch/arm/mach-davinci/dm646x.c                     |   20 +-
 arch/arm/mach-davinci/dma.c                        |    2 +-
 .../include/{mach => mach-davinci}/aemif.h         |    0
 arch/arm/mach-davinci/include/mach-davinci/asp.h   |  137 ++
 .../mach-davinci/include/mach-davinci/cdce949.h    |   19 +
 .../include/{mach => mach-davinci}/clock.h         |    0
 .../include/{mach => mach-davinci}/common.h        |    0
 .../include/{mach => mach-davinci}/cp_intc.h       |    0
 .../include/{mach => mach-davinci}/cpufreq.h       |    0
 .../include/{mach => mach-davinci}/cpuidle.h       |    0
 .../mach-davinci/include/mach-davinci/cputype.h    |   94 ++
 arch/arm/mach-davinci/include/mach-davinci/da8xx.h |  134 ++
 .../include/{mach => mach-davinci}/ddr2.h          |    0
 .../include/mach-davinci/debug-macro.S             |   67 +
 .../include/{mach => mach-davinci}/edma.h          |    0
 .../include/mach-davinci/entry-macro.S             |   39 +
 .../include/mach-davinci/gpio-davinci.h            |   91 ++
 .../include/{mach => mach-davinci}/gpio.h          |    0
 .../include/{mach => mach-davinci}/hardware.h      |    0
 .../include/{mach => mach-davinci}/i2c.h           |    0
 .../include/{mach => mach-davinci}/irqs.h          |    0
 .../include/{mach => mach-davinci}/keyscan.h       |    0
 .../include/{mach => mach-davinci}/mmc.h           |    0
 .../include/{mach => mach-davinci}/mux.h           |    0
 .../include/{mach => mach-davinci}/nand.h          |    0
 .../include/{mach => mach-davinci}/pm.h            |    0
 .../include/{mach => mach-davinci}/psc.h           |    0
 .../arm/mach-davinci/include/mach-davinci/serial.h |   48 +
 arch/arm/mach-davinci/include/mach-davinci/spi.h   |   89 ++
 .../include/{mach => mach-davinci}/sram.h          |    0
 .../include/{mach => mach-davinci}/time.h          |    0
 .../include/{mach => mach-davinci}/timex.h         |    0
 .../mach-davinci/include/mach-davinci/tnetv107x.h  |   61 +
 .../mach-davinci/include/mach-davinci/uncompress.h |   98 ++
 .../include/{mach => mach-davinci}/usb.h           |    0
 arch/arm/mach-davinci/include/mach/asp.h           |  137 --
 arch/arm/mach-davinci/include/mach/cdce949.h       |   19 -
 arch/arm/mach-davinci/include/mach/cputype.h       |   94 --
 arch/arm/mach-davinci/include/mach/da8xx.h         |  134 --
 arch/arm/mach-davinci/include/mach/debug-macro.S   |   67 -
 arch/arm/mach-davinci/include/mach/entry-macro.S   |   39 -
 arch/arm/mach-davinci/include/mach/gpio-davinci.h  |   91 --
 arch/arm/mach-davinci/include/mach/serial.h        |   48 -
 arch/arm/mach-davinci/include/mach/spi.h           |   89 --
 arch/arm/mach-davinci/include/mach/tnetv107x.h     |   61 -
 arch/arm/mach-davinci/include/mach/uncompress.h    |   98 --
 arch/arm/mach-davinci/irq.c                        |    6 +-
 arch/arm/mach-davinci/mux.c                        |    4 +-
 arch/arm/mach-davinci/mux.h                        |    2 +-
 arch/arm/mach-davinci/pm.c                         |    6 +-
 arch/arm/mach-davinci/psc.c                        |    4 +-
 arch/arm/mach-davinci/serial.c                     |    4 +-
 arch/arm/mach-davinci/sleep.S                      |    4 +-
 arch/arm/mach-davinci/sram.c                       |    4 +-
 arch/arm/mach-davinci/time.c                       |    6 +-
 arch/arm/mach-davinci/tnetv107x.c                  |   18 +-
 arch/arm/mach-davinci/usb.c                        |    8 +-
 arch/arm/mach-dove/addr-map.c                      |    4 +-
 arch/arm/mach-dove/cm-a510.c                       |    2 +-
 arch/arm/mach-dove/common.c                        |   12 +-
 arch/arm/mach-dove/dove-db-setup.c                 |    2 +-
 arch/arm/mach-dove/include/mach-dove/bridge-regs.h |   55 +
 arch/arm/mach-dove/include/mach-dove/debug-macro.S |   19 +
 .../mach-dove/include/{mach => mach-dove}/dove.h   |    0
 arch/arm/mach-dove/include/mach-dove/entry-macro.S |   33 +
 arch/arm/mach-dove/include/mach-dove/gpio.h        |    9 +
 .../include/{mach => mach-dove}/hardware.h         |    0
 .../arm/mach-dove/include/{mach => mach-dove}/io.h |    0
 .../mach-dove/include/{mach => mach-dove}/irqs.h   |    0
 arch/arm/mach-dove/include/mach-dove/pm.h          |   54 +
 .../mach-dove/include/{mach => mach-dove}/timex.h  |    0
 arch/arm/mach-dove/include/mach-dove/uncompress.h  |   37 +
 arch/arm/mach-dove/include/mach/bridge-regs.h      |   55 -
 arch/arm/mach-dove/include/mach/debug-macro.S      |   19 -
 arch/arm/mach-dove/include/mach/entry-macro.S      |   33 -
 arch/arm/mach-dove/include/mach/gpio.h             |    9 -
 arch/arm/mach-dove/include/mach/pm.h               |   54 -
 arch/arm/mach-dove/include/mach/uncompress.h       |   37 -
 arch/arm/mach-dove/irq.c                           |    6 +-
 arch/arm/mach-dove/mpp.c                           |    4 +-
 arch/arm/mach-dove/pcie.c                          |    8 +-
 arch/arm/mach-ebsa110/core.c                       |    2 +-
 .../include/{mach => mach-ebsa110}/debug-macro.S   |    0
 .../include/{mach => mach-ebsa110}/entry-macro.S   |    0
 .../include/{mach => mach-ebsa110}/hardware.h      |    0
 .../include/{mach => mach-ebsa110}/io.h            |    0
 .../include/{mach => mach-ebsa110}/irqs.h          |    0
 .../include/{mach => mach-ebsa110}/memory.h        |    0
 .../include/{mach => mach-ebsa110}/timex.h         |    0
 .../include/{mach => mach-ebsa110}/uncompress.h    |    0
 arch/arm/mach-ebsa110/io.c                         |    2 +-
 arch/arm/mach-ebsa110/leds.c                       |    2 +-
 arch/arm/mach-ep93xx/adssphere.c                   |    2 +-
 arch/arm/mach-ep93xx/clock.c                       |    2 +-
 arch/arm/mach-ep93xx/core.c                        |   10 +-
 arch/arm/mach-ep93xx/crunch-bits.S                 |    2 +-
 arch/arm/mach-ep93xx/dma.c                         |    4 +-
 arch/arm/mach-ep93xx/edb93xx.c                     |    8 +-
 arch/arm/mach-ep93xx/gesbc9312.c                   |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/debug-macro.S  |   21 +
 .../include/{mach => mach-ep93xx}/dma.h            |    0
 .../include/{mach => mach-ep93xx}/ep93xx-regs.h    |    0
 .../include/{mach => mach-ep93xx}/ep93xx_keypad.h  |    0
 .../include/{mach => mach-ep93xx}/ep93xx_spi.h     |    0
 .../mach-ep93xx/include/{mach => mach-ep93xx}/fb.h |    0
 .../mach-ep93xx/include/mach-ep93xx/gpio-ep93xx.h  |  110 ++
 .../include/{mach => mach-ep93xx}/gpio.h           |    0
 .../arm/mach-ep93xx/include/mach-ep93xx/hardware.h |   24 +
 .../include/{mach => mach-ep93xx}/irqs.h           |    0
 .../include/{mach => mach-ep93xx}/memory.h         |    0
 .../include/{mach => mach-ep93xx}/platform.h       |    0
 .../include/{mach => mach-ep93xx}/timex.h          |    0
 .../include/{mach => mach-ep93xx}/ts72xx.h         |    0
 .../mach-ep93xx/include/mach-ep93xx/uncompress.h   |   94 ++
 arch/arm/mach-ep93xx/include/mach/debug-macro.S    |   21 -
 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h    |  110 --
 arch/arm/mach-ep93xx/include/mach/hardware.h       |   24 -
 arch/arm/mach-ep93xx/include/mach/uncompress.h     |   94 --
 arch/arm/mach-ep93xx/micro9.c                      |    2 +-
 arch/arm/mach-ep93xx/simone.c                      |    6 +-
 arch/arm/mach-ep93xx/snappercl15.c                 |    6 +-
 arch/arm/mach-ep93xx/soc.h                         |    2 +-
 arch/arm/mach-ep93xx/ts72xx.c                      |    4 +-
 arch/arm/mach-ep93xx/vision_ep9307.c               |    8 +-
 arch/arm/mach-exynos/clock-exynos4.c               |   22 +-
 arch/arm/mach-exynos/clock-exynos4210.c            |   24 +-
 arch/arm/mach-exynos/clock-exynos4212.c            |   24 +-
 arch/arm/mach-exynos/clock-exynos5.c               |   22 +-
 arch/arm/mach-exynos/common.c                      |   34 +-
 arch/arm/mach-exynos/cpuidle.c                     |    6 +-
 arch/arm/mach-exynos/dev-ahci.c                    |    8 +-
 arch/arm/mach-exynos/dev-audio.c                   |   12 +-
 arch/arm/mach-exynos/dev-drm.c                     |    2 +-
 arch/arm/mach-exynos/dev-dwmci.c                   |    4 +-
 arch/arm/mach-exynos/dev-ohci.c                    |   10 +-
 arch/arm/mach-exynos/dev-sysmmu.c                  |    8 +-
 arch/arm/mach-exynos/dev-uart.c                    |    6 +-
 arch/arm/mach-exynos/dma.c                         |   12 +-
 arch/arm/mach-exynos/hotplug.c                     |    2 +-
 .../include/{mach => mach-exynos}/cpufreq.h        |    0
 .../mach-exynos/include/mach-exynos/debug-macro.S  |   39 +
 arch/arm/mach-exynos/include/mach-exynos/dma.h     |   26 +
 .../include/{mach => mach-exynos}/dwmci.h          |    0
 .../include/{mach => mach-exynos}/gpio.h           |    0
 .../include/{mach => mach-exynos}/hardware.h       |    0
 arch/arm/mach-exynos/include/mach-exynos/irqs.h    |  469 ++++++
 arch/arm/mach-exynos/include/mach-exynos/map.h     |  278 ++++
 .../include/{mach => mach-exynos}/memory.h         |    0
 .../include/{mach => mach-exynos}/ohci.h           |    0
 arch/arm/mach-exynos/include/mach-exynos/pm-core.h |   65 +
 .../include/{mach => mach-exynos}/pmu.h            |    0
 .../include/{mach => mach-exynos}/regs-audss.h     |    0
 .../mach-exynos/include/mach-exynos/regs-clock.h   |  353 +++++
 .../mach-exynos/include/mach-exynos/regs-gpio.h    |   40 +
 .../arm/mach-exynos/include/mach-exynos/regs-irq.h |   19 +
 .../arm/mach-exynos/include/mach-exynos/regs-mct.h |   53 +
 .../arm/mach-exynos/include/mach-exynos/regs-mem.h |   23 +
 .../arm/mach-exynos/include/mach-exynos/regs-pmu.h |  370 +++++
 .../include/{mach => mach-exynos}/regs-usb-phy.h   |    0
 .../include/{mach => mach-exynos}/sysmmu.h         |    0
 .../include/{mach => mach-exynos}/timex.h          |    0
 .../mach-exynos/include/mach-exynos/uncompress.h   |   52 +
 arch/arm/mach-exynos/include/mach/debug-macro.S    |   39 -
 arch/arm/mach-exynos/include/mach/dma.h            |   26 -
 arch/arm/mach-exynos/include/mach/irqs.h           |  469 ------
 arch/arm/mach-exynos/include/mach/map.h            |  278 ----
 arch/arm/mach-exynos/include/mach/pm-core.h        |   65 -
 arch/arm/mach-exynos/include/mach/regs-clock.h     |  353 -----
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |   40 -
 arch/arm/mach-exynos/include/mach/regs-irq.h       |   19 -
 arch/arm/mach-exynos/include/mach/regs-mct.h       |   53 -
 arch/arm/mach-exynos/include/mach/regs-mem.h       |   23 -
 arch/arm/mach-exynos/include/mach/regs-pmu.h       |  370 -----
 arch/arm/mach-exynos/include/mach/uncompress.h     |   52 -
 arch/arm/mach-exynos/mach-armlex4210.c             |   16 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    6 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 +-
 arch/arm/mach-exynos/mach-nuri.c                   |   34 +-
 arch/arm/mach-exynos/mach-origen.c                 |   30 +-
 arch/arm/mach-exynos/mach-smdk4x12.c               |   28 +-
 arch/arm/mach-exynos/mach-smdkv310.c               |   34 +-
 arch/arm/mach-exynos/mach-universal_c210.c         |   32 +-
 arch/arm/mach-exynos/mct.c                         |    8 +-
 arch/arm/mach-exynos/platsmp.c                     |    8 +-
 arch/arm/mach-exynos/pm.c                          |   22 +-
 arch/arm/mach-exynos/pm_domains.c                  |    4 +-
 arch/arm/mach-exynos/pmu.c                         |    4 +-
 arch/arm/mach-exynos/setup-fimc.c                  |    4 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    6 +-
 arch/arm/mach-exynos/setup-i2c0.c                  |    6 +-
 arch/arm/mach-exynos/setup-i2c1.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c2.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c3.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c4.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c5.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c6.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c7.c                  |    4 +-
 arch/arm/mach-exynos/setup-keypad.c                |    2 +-
 arch/arm/mach-exynos/setup-sdhci-gpio.c            |    6 +-
 arch/arm/mach-exynos/setup-spi.c                   |    2 +-
 arch/arm/mach-exynos/setup-usb-phy.c               |    8 +-
 arch/arm/mach-footbridge/ebsa285-leds.c            |    2 +-
 .../include/mach-footbridge/debug-macro.S          |   56 +
 .../include/mach-footbridge/entry-macro.S          |  107 ++
 .../include/{mach => mach-footbridge}/hardware.h   |    0
 .../include/{mach => mach-footbridge}/io.h         |    0
 .../include/{mach => mach-footbridge}/irqs.h       |    0
 .../include/{mach => mach-footbridge}/isa-dma.h    |    0
 .../include/{mach => mach-footbridge}/memory.h     |    0
 .../include/{mach => mach-footbridge}/timex.h      |    0
 .../include/{mach => mach-footbridge}/uncompress.h |    0
 .../arm/mach-footbridge/include/mach/debug-macro.S |   56 -
 .../arm/mach-footbridge/include/mach/entry-macro.S |  107 --
 arch/arm/mach-footbridge/isa-irq.c                 |    2 +-
 arch/arm/mach-footbridge/netwinder-leds.c          |    2 +-
 arch/arm/mach-gemini/board-nas4220b.c              |    4 +-
 arch/arm/mach-gemini/devices.c                     |    6 +-
 arch/arm/mach-gemini/gpio.c                        |    4 +-
 .../mach-gemini/include/mach-gemini/debug-macro.S  |   21 +
 .../mach-gemini/include/mach-gemini/entry-macro.S  |   33 +
 .../include/{mach => mach-gemini}/global_reg.h     |    0
 arch/arm/mach-gemini/include/mach-gemini/gpio.h    |   20 +
 .../include/{mach => mach-gemini}/hardware.h       |    0
 .../include/{mach => mach-gemini}/irqs.h           |    0
 arch/arm/mach-gemini/include/mach-gemini/system.h  |   23 +
 .../include/{mach => mach-gemini}/timex.h          |    0
 .../mach-gemini/include/mach-gemini/uncompress.h   |   44 +
 arch/arm/mach-gemini/include/mach/debug-macro.S    |   21 -
 arch/arm/mach-gemini/include/mach/entry-macro.S    |   33 -
 arch/arm/mach-gemini/include/mach/gpio.h           |   20 -
 arch/arm/mach-gemini/include/mach/system.h         |   23 -
 arch/arm/mach-gemini/include/mach/uncompress.h     |   44 -
 arch/arm/mach-gemini/irq.c                         |    2 +-
 arch/arm/mach-gemini/mm.c                          |    2 +-
 arch/arm/mach-gemini/time.c                        |    4 +-
 arch/arm/mach-h720x/common.c                       |    4 +-
 arch/arm/mach-h720x/cpu-h7201.c                    |    4 +-
 arch/arm/mach-h720x/cpu-h7202.c                    |    4 +-
 arch/arm/mach-h720x/h7201-eval.c                   |    2 +-
 arch/arm/mach-h720x/h7202-eval.c                   |    4 +-
 .../include/{mach => mach-h720x}/boards.h          |    0
 .../mach-h720x/include/mach-h720x/debug-macro.S    |   40 +
 .../include/{mach => mach-h720x}/entry-macro.S     |    0
 .../include/{mach => mach-h720x}/h7201-regs.h      |    0
 .../include/{mach => mach-h720x}/h7202-regs.h      |    0
 .../include/{mach => mach-h720x}/hardware.h        |    0
 .../mach-h720x/include/{mach => mach-h720x}/irqs.h |    0
 .../include/{mach => mach-h720x}/isa-dma.h         |    0
 .../include/{mach => mach-h720x}/timex.h           |    0
 .../arm/mach-h720x/include/mach-h720x/uncompress.h |   37 +
 arch/arm/mach-h720x/include/mach/debug-macro.S     |   40 -
 arch/arm/mach-h720x/include/mach/uncompress.h      |   37 -
 .../include/{mach => mach-highbank}/debug-macro.S  |    0
 .../include/{mach => mach-highbank}/gpio.h         |    0
 .../include/{mach => mach-highbank}/timex.h        |    0
 .../include/{mach => mach-highbank}/uncompress.h   |    0
 arch/arm/mach-imx/clk-imx1.c                       |    4 +-
 arch/arm/mach-imx/clk-imx21.c                      |    4 +-
 arch/arm/mach-imx/clk-imx25.c                      |    6 +-
 arch/arm/mach-imx/clk-imx27.c                      |    4 +-
 arch/arm/mach-imx/clk-imx31.c                      |    6 +-
 arch/arm/mach-imx/clk-imx35.c                      |    4 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |    4 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    2 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    6 +-
 arch/arm/mach-imx/clk.h                            |    2 +-
 arch/arm/mach-imx/cpu-imx25.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    6 +-
 arch/arm/mach-imx/cpu-imx35.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    2 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    2 +-
 arch/arm/mach-imx/devices-imx1.h                   |    4 +-
 arch/arm/mach-imx/devices-imx21.h                  |    4 +-
 arch/arm/mach-imx/devices-imx25.h                  |    4 +-
 arch/arm/mach-imx/devices-imx27.h                  |    4 +-
 arch/arm/mach-imx/devices-imx31.h                  |    4 +-
 arch/arm/mach-imx/devices-imx35.h                  |    4 +-
 arch/arm/mach-imx/devices-imx50.h                  |    4 +-
 arch/arm/mach-imx/devices-imx51.h                  |    4 +-
 arch/arm/mach-imx/devices-imx53.h                  |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    6 +-
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    6 +-
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    6 +-
 arch/arm/mach-imx/hotplug.c                        |    2 +-
 arch/arm/mach-imx/imx27-dt.c                       |    4 +-
 arch/arm/mach-imx/imx31-dt.c                       |    4 +-
 arch/arm/mach-imx/imx51-dt.c                       |    4 +-
 arch/arm/mach-imx/imx53-dt.c                       |    4 +-
 .../include/mach-imx}/3ds_debugboard.h             |    0
 .../include/mach-imx}/board-mx31lilly.h            |    0
 .../include/mach-imx}/board-mx31lite.h             |    0
 .../include/mach-imx}/board-mx31moboard.h          |    0
 .../include/mach-imx}/board-pcm038.h               |    0
 .../mach => mach-imx/include/mach-imx}/clock.h     |    0
 .../mach => mach-imx/include/mach-imx}/common.h    |    0
 .../mach => mach-imx/include/mach-imx}/cpuidle.h   |    0
 arch/arm/mach-imx/include/mach-imx/debug-macro.S   |   51 +
 .../arm/mach-imx/include/mach-imx/devices-common.h |  333 ++++
 arch/arm/mach-imx/include/mach-imx/dma-mx1-mx2.h   |   10 +
 .../mach => mach-imx/include/mach-imx}/dma.h       |    0
 .../mach => mach-imx/include/mach-imx}/esdhc.h     |    0
 .../include/mach-imx}/eukrea-baseboards.h          |    0
 .../mach => mach-imx/include/mach-imx}/gpio.h      |    0
 arch/arm/mach-imx/include/mach-imx/hardware.h      |  134 ++
 .../mach => mach-imx/include/mach-imx}/i2c.h       |    0
 .../mach => mach-imx/include/mach-imx}/iim.h       |    0
 .../mach => mach-imx/include/mach-imx}/imx-uart.h  |    0
 .../mach => mach-imx/include/mach-imx}/imxfb.h     |    0
 arch/arm/mach-imx/include/mach-imx/iomux-mx1.h     |  155 ++
 arch/arm/mach-imx/include/mach-imx/iomux-mx21.h    |  122 ++
 arch/arm/mach-imx/include/mach-imx/iomux-mx25.h    |  524 ++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx27.h    |  205 +++
 .../include/mach-imx}/iomux-mx2x.h                 |    0
 .../mach => mach-imx/include/mach-imx}/iomux-mx3.h |    0
 arch/arm/mach-imx/include/mach-imx/iomux-mx35.h    | 1267 +++++++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx50.h    |  977 ++++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx51.h    |  827 ++++++++++
 arch/arm/mach-imx/include/mach-imx/iomux-mx53.h    | 1219 ++++++++++++++
 .../mach => mach-imx/include/mach-imx}/iomux-v1.h  |    0
 .../mach => mach-imx/include/mach-imx}/iomux-v3.h  |    0
 .../mach => mach-imx/include/mach-imx}/ipu.h       |    0
 .../mach => mach-imx/include/mach-imx}/iram.h      |    0
 .../mach => mach-imx/include/mach-imx}/irqs.h      |    0
 .../mach => mach-imx/include/mach-imx}/mmc.h       |    0
 .../mach => mach-imx/include/mach-imx}/mx1.h       |    0
 .../include/mach-imx}/mx1_camera.h                 |    0
 .../include/mach-imx}/mx21-usbhost.h               |    0
 .../mach => mach-imx/include/mach-imx}/mx21.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx25.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx27.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx2_cam.h   |    0
 .../mach => mach-imx/include/mach-imx}/mx2x.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx31.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx35.h      |    0
 .../include/mach-imx}/mx3_camera.h                 |    0
 .../mach => mach-imx/include/mach-imx}/mx3fb.h     |    0
 .../mach => mach-imx/include/mach-imx}/mx3x.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx50.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx51.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx53.h      |    0
 .../mach => mach-imx/include/mach-imx}/mx6q.h      |    0
 .../mach => mach-imx/include/mach-imx}/mxc.h       |    0
 .../mach => mach-imx/include/mach-imx}/mxc_ehci.h  |    0
 .../mach => mach-imx/include/mach-imx}/mxc_nand.h  |    0
 .../mach => mach-imx/include/mach-imx}/sdma.h      |    0
 .../mach => mach-imx/include/mach-imx}/spi.h       |    0
 .../mach => mach-imx/include/mach-imx}/ssi.h       |    0
 .../mach => mach-imx/include/mach-imx}/timex.h     |    0
 .../mach => mach-imx/include/mach-imx}/ulpi.h      |    0
 .../include/mach-imx}/uncompress.h                 |    0
 .../mach => mach-imx/include/mach-imx}/usb.h       |    0
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h       |   10 -
 arch/arm/mach-imx/iomux-imx31.c                    |    4 +-
 arch/arm/mach-imx/lluart.c                         |    2 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    6 +-
 arch/arm/mach-imx/mach-armadillo5x0.c              |    8 +-
 arch/arm/mach-imx/mach-bug.c                       |    6 +-
 arch/arm/mach-imx/mach-cpuimx27.c                  |   10 +-
 arch/arm/mach-imx/mach-cpuimx35.c                  |    8 +-
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    8 +-
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    6 +-
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +-
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +-
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +-
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    8 +-
 arch/arm/mach-imx/mach-mx1ads.c                    |    6 +-
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx31ads.c                   |    4 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   10 +-
 arch/arm/mach-imx/mach-mx31lite.c                  |   10 +-
 arch/arm/mach-imx/mach-mx31moboard.c               |   12 +-
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    6 +-
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx51_babbage.c              |    6 +-
 arch/arm/mach-imx/mach-mx51_efikamx.c              |    6 +-
 arch/arm/mach-imx/mach-mx51_efikasb.c              |    8 +-
 arch/arm/mach-imx/mach-mx53_ard.c                  |    6 +-
 arch/arm/mach-imx/mach-mx53_evk.c                  |    6 +-
 arch/arm/mach-imx/mach-mx53_loco.c                 |    6 +-
 arch/arm/mach-imx/mach-mx53_smd.c                  |    6 +-
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +-
 arch/arm/mach-imx/mach-pca100.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037_eet.c                |    4 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   10 +-
 arch/arm/mach-imx/mach-pcm043.c                    |    8 +-
 arch/arm/mach-imx/mach-qong.c                      |    6 +-
 arch/arm/mach-imx/mach-scb9328.c                   |    6 +-
 arch/arm/mach-imx/mach-vpr200.c                    |    6 +-
 arch/arm/mach-imx/mm-imx1.c                        |    6 +-
 arch/arm/mach-imx/mm-imx21.c                       |    8 +-
 arch/arm/mach-imx/mm-imx25.c                       |   10 +-
 arch/arm/mach-imx/mm-imx27.c                       |    8 +-
 arch/arm/mach-imx/mm-imx3.c                        |    8 +-
 arch/arm/mach-imx/mm-imx5.c                        |    8 +-
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |    2 +-
 arch/arm/mach-imx/mx31lilly-db.c                   |    8 +-
 arch/arm/mach-imx/mx31lite-db.c                    |    8 +-
 arch/arm/mach-imx/mx31moboard-devboard.c           |    8 +-
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    8 +-
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   10 +-
 arch/arm/mach-imx/mx51_efika.c                     |    8 +-
 arch/arm/mach-imx/pcm970-baseboard.c               |    6 +-
 arch/arm/mach-imx/platsmp.c                        |    4 +-
 arch/arm/mach-imx/pm-imx27.c                       |    2 +-
 arch/arm/mach-imx/pm-imx3.c                        |    6 +-
 arch/arm/mach-imx/pm-imx5.c                        |    6 +-
 arch/arm/mach-imx/pm-imx6q.c                       |    4 +-
 arch/arm/mach-integrator/core.c                    |    8 +-
 arch/arm/mach-integrator/cpu.c                     |    4 +-
 arch/arm/mach-integrator/impd1.c                   |    4 +-
 .../include/{mach => mach-integrator}/cm.h         |    0
 .../{mach => mach-integrator}/debug-macro.S        |    0
 .../include/{mach => mach-integrator}/hardware.h   |    0
 .../include/{mach => mach-integrator}/impd1.h      |    0
 .../include/{mach => mach-integrator}/io.h         |    0
 .../include/{mach => mach-integrator}/irqs.h       |    0
 .../include/{mach => mach-integrator}/lm.h         |    0
 .../include/{mach => mach-integrator}/memory.h     |    0
 .../include/{mach => mach-integrator}/platform.h   |    0
 .../include/{mach => mach-integrator}/timex.h      |    0
 .../include/{mach => mach-integrator}/uncompress.h |    0
 arch/arm/mach-integrator/integrator_ap.c           |   10 +-
 arch/arm/mach-integrator/integrator_cp.c           |   16 +-
 arch/arm/mach-integrator/leds.c                    |    6 +-
 arch/arm/mach-integrator/lm.c                      |    2 +-
 arch/arm/mach-integrator/pci.c                     |    2 +-
 arch/arm/mach-integrator/pci_v3.c                  |    6 +-
 arch/arm/mach-iop13xx/include/mach-iop13xx/adma.h  |  647 ++++++++
 .../include/{mach => mach-iop13xx}/debug-macro.S   |    0
 .../include/{mach => mach-iop13xx}/entry-macro.S   |    0
 .../include/{mach => mach-iop13xx}/hardware.h      |    0
 .../include/{mach => mach-iop13xx}/io.h            |    0
 .../include/{mach => mach-iop13xx}/iop13xx.h       |    0
 .../include/{mach => mach-iop13xx}/iq81340.h       |    0
 .../include/{mach => mach-iop13xx}/irqs.h          |    0
 .../arm/mach-iop13xx/include/mach-iop13xx/memory.h |   72 +
 .../include/{mach => mach-iop13xx}/msi.h           |    0
 arch/arm/mach-iop13xx/include/mach-iop13xx/pci.h   |   57 +
 .../include/{mach => mach-iop13xx}/time.h          |    0
 .../include/{mach => mach-iop13xx}/timex.h         |    0
 .../mach-iop13xx/include/mach-iop13xx/uncompress.h |   23 +
 arch/arm/mach-iop13xx/include/mach/adma.h          |  647 --------
 arch/arm/mach-iop13xx/include/mach/memory.h        |   72 -
 arch/arm/mach-iop13xx/include/mach/pci.h           |   57 -
 arch/arm/mach-iop13xx/include/mach/uncompress.h    |   23 -
 arch/arm/mach-iop13xx/io.c                         |    2 +-
 arch/arm/mach-iop13xx/iq81340mc.c                  |    6 +-
 arch/arm/mach-iop13xx/iq81340sc.c                  |    6 +-
 arch/arm/mach-iop13xx/irq.c                        |    6 +-
 arch/arm/mach-iop13xx/pci.c                        |    4 +-
 arch/arm/mach-iop13xx/setup.c                      |    2 +-
 arch/arm/mach-iop32x/em7210.c                      |    4 +-
 arch/arm/mach-iop32x/glantank.c                    |    4 +-
 .../include/{mach => mach-iop32x}/adma.h           |    0
 .../include/{mach => mach-iop32x}/debug-macro.S    |    0
 .../mach-iop32x/include/mach-iop32x/entry-macro.S  |   33 +
 .../include/{mach => mach-iop32x}/glantank.h       |    0
 .../include/{mach => mach-iop32x}/gpio.h           |    0
 .../include/{mach => mach-iop32x}/hardware.h       |    0
 .../mach-iop32x/include/{mach => mach-iop32x}/io.h |    0
 .../include/{mach => mach-iop32x}/iop32x.h         |    0
 .../include/{mach => mach-iop32x}/iq31244.h        |    0
 .../include/{mach => mach-iop32x}/iq80321.h        |    0
 .../include/{mach => mach-iop32x}/irqs.h           |    0
 .../include/{mach => mach-iop32x}/n2100.h          |    0
 .../include/{mach => mach-iop32x}/time.h           |    0
 .../include/{mach => mach-iop32x}/timex.h          |    0
 .../mach-iop32x/include/mach-iop32x/uncompress.h   |   39 +
 arch/arm/mach-iop32x/include/mach/entry-macro.S    |   33 -
 arch/arm/mach-iop32x/include/mach/uncompress.h     |   39 -
 arch/arm/mach-iop32x/iq31244.c                     |    4 +-
 arch/arm/mach-iop32x/iq80321.c                     |    4 +-
 arch/arm/mach-iop32x/irq.c                         |    2 +-
 arch/arm/mach-iop32x/n2100.c                       |    4 +-
 .../include/{mach => mach-iop33x}/adma.h           |    0
 .../include/{mach => mach-iop33x}/debug-macro.S    |    0
 .../mach-iop33x/include/mach-iop33x/entry-macro.S  |   34 +
 .../include/{mach => mach-iop33x}/gpio.h           |    0
 .../include/{mach => mach-iop33x}/hardware.h       |    0
 .../mach-iop33x/include/{mach => mach-iop33x}/io.h |    0
 .../include/{mach => mach-iop33x}/iop33x.h         |    0
 .../include/{mach => mach-iop33x}/iq80331.h        |    0
 .../include/{mach => mach-iop33x}/iq80332.h        |    0
 .../include/{mach => mach-iop33x}/irqs.h           |    0
 .../include/{mach => mach-iop33x}/time.h           |    0
 .../include/{mach => mach-iop33x}/timex.h          |    0
 .../mach-iop33x/include/mach-iop33x/uncompress.h   |   37 +
 arch/arm/mach-iop33x/include/mach/entry-macro.S    |   34 -
 arch/arm/mach-iop33x/include/mach/uncompress.h     |   37 -
 arch/arm/mach-iop33x/iq80331.c                     |    4 +-
 arch/arm/mach-iop33x/iq80332.c                     |    4 +-
 arch/arm/mach-iop33x/irq.c                         |    2 +-
 arch/arm/mach-iop33x/uart.c                        |    2 +-
 arch/arm/mach-ixp4xx/avila-pci.c                   |    2 +-
 arch/arm/mach-ixp4xx/avila-setup.c                 |    2 +-
 arch/arm/mach-ixp4xx/common-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/common.c                      |    6 +-
 arch/arm/mach-ixp4xx/coyote-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/coyote-setup.c                |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-pci.c             |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-setup.c           |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-setup.c              |    2 +-
 .../include/{mach => mach-ixp4xx}/cpu.h            |    0
 .../include/{mach => mach-ixp4xx}/debug-macro.S    |    0
 .../mach-ixp4xx/include/mach-ixp4xx/entry-macro.S  |   41 +
 .../include/{mach => mach-ixp4xx}/gpio.h           |    0
 .../arm/mach-ixp4xx/include/mach-ixp4xx/hardware.h |   36 +
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/io.h      |  502 ++++++
 .../include/{mach => mach-ixp4xx}/irqs.h           |    0
 .../include/{mach => mach-ixp4xx}/ixp46x_ts.h      |    0
 .../include/{mach => mach-ixp4xx}/ixp4xx-regs.h    |    0
 .../include/{mach => mach-ixp4xx}/npe.h            |    0
 .../arm/mach-ixp4xx/include/mach-ixp4xx/platform.h |  175 ++
 .../include/{mach => mach-ixp4xx}/qmgr.h           |    0
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/timex.h   |   16 +
 .../include/{mach => mach-ixp4xx}/udc.h            |    0
 .../include/{mach => mach-ixp4xx}/uncompress.h     |    0
 arch/arm/mach-ixp4xx/include/mach/entry-macro.S    |   41 -
 arch/arm/mach-ixp4xx/include/mach/hardware.h       |   36 -
 arch/arm/mach-ixp4xx/include/mach/io.h             |  502 ------
 arch/arm/mach-ixp4xx/include/mach/platform.h       |  175 --
 arch/arm/mach-ixp4xx/include/mach/timex.h          |   16 -
 arch/arm/mach-ixp4xx/ixdp425-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-setup.c               |    2 +-
 arch/arm/mach-ixp4xx/ixdpg425-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_npe.c                  |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_qmgr.c                 |    2 +-
 arch/arm/mach-ixp4xx/miccpt-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-setup.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |    4 +-
 arch/arm/mach-kirkwood/board-dnskw.c               |    4 +-
 arch/arm/mach-kirkwood/board-dreamplug.c           |    6 +-
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    6 +-
 arch/arm/mach-kirkwood/board-ib62x0.c              |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c            |    2 +-
 arch/arm/mach-kirkwood/board-lsxl.c                |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c               |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   22 +-
 arch/arm/mach-kirkwood/cpuidle.c                   |    2 +-
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    4 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    4 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    4 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    4 +-
 .../include/mach-kirkwood/bridge-regs.h            |   81 +
 .../include/mach-kirkwood/debug-macro.S            |   19 +
 .../include/mach-kirkwood/entry-macro.S            |   34 +
 .../arm/mach-kirkwood/include/mach-kirkwood/gpio.h |    9 +
 .../include/{mach => mach-kirkwood}/hardware.h     |    0
 .../include/{mach => mach-kirkwood}/io.h           |    0
 .../include/{mach => mach-kirkwood}/irqs.h         |    0
 .../include/{mach => mach-kirkwood}/kirkwood.h     |    0
 .../include/{mach => mach-kirkwood}/leds-netxbig.h |    0
 .../include/{mach => mach-kirkwood}/leds-ns2.h     |    0
 .../include/{mach => mach-kirkwood}/timex.h        |    0
 .../include/mach-kirkwood/uncompress.h             |   47 +
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h  |   81 -
 arch/arm/mach-kirkwood/include/mach/debug-macro.S  |   19 -
 arch/arm/mach-kirkwood/include/mach/entry-macro.S  |   34 -
 arch/arm/mach-kirkwood/include/mach/gpio.h         |    9 -
 arch/arm/mach-kirkwood/include/mach/uncompress.h   |   47 -
 arch/arm/mach-kirkwood/irq.c                       |    4 +-
 arch/arm/mach-kirkwood/lacie_v2-common.c           |    6 +-
 arch/arm/mach-kirkwood/mpp.c                       |    4 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c     |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    4 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    4 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    4 +-
 arch/arm/mach-kirkwood/pcie.c                      |    6 +-
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c       |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    4 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    4 +-
 arch/arm/mach-kirkwood/t5325-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c               |    4 +-
 arch/arm/mach-kirkwood/tsx1x-common.c              |    2 +-
 arch/arm/mach-ks8695/board-acs5k.c                 |    4 +-
 arch/arm/mach-ks8695/board-dsm320.c                |    4 +-
 arch/arm/mach-ks8695/board-micrel.c                |    4 +-
 arch/arm/mach-ks8695/cpu.c                         |    6 +-
 arch/arm/mach-ks8695/devices.c                     |   12 +-
 .../mach-ks8695/include/mach-ks8695/debug-macro.S  |   36 +
 .../include/{mach => mach-ks8695}/devices.h        |    0
 .../mach-ks8695/include/mach-ks8695/entry-macro.S  |   47 +
 .../include/{mach => mach-ks8695}/gpio-ks8695.h    |    0
 .../include/{mach => mach-ks8695}/gpio.h           |    0
 .../include/{mach => mach-ks8695}/hardware.h       |    0
 .../include/{mach => mach-ks8695}/irqs.h           |    0
 arch/arm/mach-ks8695/include/mach-ks8695/memory.h  |   55 +
 .../include/{mach => mach-ks8695}/regs-gpio.h      |    0
 .../include/{mach => mach-ks8695}/regs-hpna.h      |    0
 .../include/{mach => mach-ks8695}/regs-irq.h       |    0
 .../include/{mach => mach-ks8695}/regs-lan.h       |    0
 .../include/{mach => mach-ks8695}/regs-mem.h       |    0
 .../include/{mach => mach-ks8695}/regs-misc.h      |    0
 .../include/{mach => mach-ks8695}/regs-pci.h       |    0
 .../include/{mach => mach-ks8695}/regs-switch.h    |    0
 .../include/{mach => mach-ks8695}/regs-sys.h       |    0
 .../include/{mach => mach-ks8695}/regs-timer.h     |    0
 .../include/{mach => mach-ks8695}/regs-uart.h      |    0
 .../include/{mach => mach-ks8695}/regs-wan.h       |    0
 arch/arm/mach-ks8695/include/mach-ks8695/timex.h   |   21 +
 .../mach-ks8695/include/mach-ks8695/uncompress.h   |   37 +
 arch/arm/mach-ks8695/include/mach/debug-macro.S    |   36 -
 arch/arm/mach-ks8695/include/mach/entry-macro.S    |   47 -
 arch/arm/mach-ks8695/include/mach/memory.h         |   55 -
 arch/arm/mach-ks8695/include/mach/timex.h          |   21 -
 arch/arm/mach-ks8695/include/mach/uncompress.h     |   37 -
 arch/arm/mach-ks8695/irq.c                         |    6 +-
 arch/arm/mach-ks8695/leds.c                        |    2 +-
 arch/arm/mach-ks8695/pci.c                         |    6 +-
 arch/arm/mach-ks8695/time.c                        |    4 +-
 .../include/{mach => mach-l7200}/debug-macro.S     |    0
 arch/arm/mach-lpc32xx/clock.c                      |    4 +-
 arch/arm/mach-lpc32xx/common.c                     |    4 +-
 arch/arm/mach-lpc32xx/common.h                     |    2 +-
 .../include/{mach => mach-lpc32xx}/board.h         |    0
 .../include/{mach => mach-lpc32xx}/debug-macro.S   |    0
 .../include/mach-lpc32xx/entry-macro.S             |   37 +
 .../include/{mach => mach-lpc32xx}/gpio-lpc32xx.h  |    0
 .../include/{mach => mach-lpc32xx}/gpio.h          |    0
 .../include/{mach => mach-lpc32xx}/hardware.h      |    0
 .../include/{mach => mach-lpc32xx}/irqs.h          |    0
 .../include/{mach => mach-lpc32xx}/platform.h      |    0
 .../include/{mach => mach-lpc32xx}/timex.h         |    0
 .../mach-lpc32xx/include/mach-lpc32xx/uncompress.h |   60 +
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S   |   37 -
 arch/arm/mach-lpc32xx/include/mach/uncompress.h    |   60 -
 arch/arm/mach-lpc32xx/irq.c                        |    6 +-
 arch/arm/mach-lpc32xx/phy3250.c                    |    8 +-
 arch/arm/mach-lpc32xx/pm.c                         |    4 +-
 arch/arm/mach-lpc32xx/serial.c                     |    4 +-
 arch/arm/mach-lpc32xx/suspend.S                    |    4 +-
 arch/arm/mach-lpc32xx/timer.c                      |    4 +-
 arch/arm/mach-mmp/aspenite.c                       |   10 +-
 arch/arm/mach-mmp/avengers_lite.c                  |    8 +-
 arch/arm/mach-mmp/brownstone.c                     |    8 +-
 arch/arm/mach-mmp/clock.c                          |    2 +-
 arch/arm/mach-mmp/common.c                         |    4 +-
 arch/arm/mach-mmp/devices.c                        |    8 +-
 arch/arm/mach-mmp/flint.c                          |    8 +-
 arch/arm/mach-mmp/gplugd.c                         |    6 +-
 .../mach-mmp/include/{mach => mach-mmp}/addr-map.h |    0
 .../mach-mmp/include/{mach => mach-mmp}/cputype.h  |    0
 arch/arm/mach-mmp/include/mach-mmp/debug-macro.S   |   22 +
 .../mach-mmp/include/{mach => mach-mmp}/devices.h  |    0
 arch/arm/mach-mmp/include/mach-mmp/dma.h           |   13 +
 arch/arm/mach-mmp/include/mach-mmp/entry-macro.S   |   26 +
 arch/arm/mach-mmp/include/mach-mmp/gpio.h          |    8 +
 .../mach-mmp/include/{mach => mach-mmp}/hardware.h |    0
 .../arm/mach-mmp/include/{mach => mach-mmp}/irqs.h |    0
 arch/arm/mach-mmp/include/mach-mmp/mfp-mmp2.h      |  395 +++++
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa168.h    |  354 +++++
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa910.h    |  170 ++
 arch/arm/mach-mmp/include/mach-mmp/mfp.h           |   34 +
 arch/arm/mach-mmp/include/mach-mmp/mmp2.h          |  104 ++
 arch/arm/mach-mmp/include/mach-mmp/pm-mmp2.h       |   61 +
 .../include/{mach => mach-mmp}/pm-pxa910.h         |    0
 arch/arm/mach-mmp/include/mach-mmp/pxa168.h        |  136 ++
 arch/arm/mach-mmp/include/mach-mmp/pxa910.h        |   85 +
 arch/arm/mach-mmp/include/mach-mmp/regs-apbc.h     |  119 ++
 arch/arm/mach-mmp/include/mach-mmp/regs-apmu.h     |   48 +
 arch/arm/mach-mmp/include/mach-mmp/regs-icu.h      |   71 +
 arch/arm/mach-mmp/include/mach-mmp/regs-rtc.h      |   23 +
 arch/arm/mach-mmp/include/mach-mmp/regs-smc.h      |   37 +
 arch/arm/mach-mmp/include/mach-mmp/regs-timers.h   |   44 +
 .../mach-mmp/include/{mach => mach-mmp}/regs-usb.h |    0
 .../arm/mach-mmp/include/{mach => mach-mmp}/sram.h |    0
 .../include/{mach => mach-mmp}/teton_bga.h         |    0
 .../mach-mmp/include/{mach => mach-mmp}/timex.h    |    0
 arch/arm/mach-mmp/include/mach-mmp/uncompress.h    |   51 +
 arch/arm/mach-mmp/include/mach/debug-macro.S       |   22 -
 arch/arm/mach-mmp/include/mach/dma.h               |   13 -
 arch/arm/mach-mmp/include/mach/entry-macro.S       |   26 -
 arch/arm/mach-mmp/include/mach/gpio.h              |    8 -
 arch/arm/mach-mmp/include/mach/mfp-mmp2.h          |  395 -----
 arch/arm/mach-mmp/include/mach/mfp-pxa168.h        |  354 -----
 arch/arm/mach-mmp/include/mach/mfp-pxa910.h        |  170 --
 arch/arm/mach-mmp/include/mach/mfp.h               |   34 -
 arch/arm/mach-mmp/include/mach/mmp2.h              |  104 --
 arch/arm/mach-mmp/include/mach/pm-mmp2.h           |   61 -
 arch/arm/mach-mmp/include/mach/pxa168.h            |  136 --
 arch/arm/mach-mmp/include/mach/pxa910.h            |   85 -
 arch/arm/mach-mmp/include/mach/regs-apbc.h         |  119 --
 arch/arm/mach-mmp/include/mach/regs-apmu.h         |   48 -
 arch/arm/mach-mmp/include/mach/regs-icu.h          |   71 -
 arch/arm/mach-mmp/include/mach/regs-rtc.h          |   23 -
 arch/arm/mach-mmp/include/mach/regs-smc.h          |   37 -
 arch/arm/mach-mmp/include/mach/regs-timers.h       |   44 -
 arch/arm/mach-mmp/include/mach/uncompress.h        |   51 -
 arch/arm/mach-mmp/irq.c                            |    6 +-
 arch/arm/mach-mmp/jasper.c                         |    8 +-
 arch/arm/mach-mmp/mmp-dt.c                         |    2 +-
 arch/arm/mach-mmp/mmp2-dt.c                        |    4 +-
 arch/arm/mach-mmp/mmp2.c                           |   18 +-
 arch/arm/mach-mmp/pm-mmp2.c                        |   12 +-
 arch/arm/mach-mmp/pm-pxa910.c                      |   12 +-
 arch/arm/mach-mmp/pxa168.c                         |   20 +-
 arch/arm/mach-mmp/pxa910.c                         |   16 +-
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mmp/tavorevb.c                       |    8 +-
 arch/arm/mach-mmp/teton_bga.c                      |   12 +-
 arch/arm/mach-mmp/time.c                           |   10 +-
 arch/arm/mach-mmp/ttc_dkb.c                        |   10 +-
 arch/arm/mach-msm/acpuclock-arm11.c                |    4 +-
 arch/arm/mach-msm/board-halibut.c                  |    8 +-
 arch/arm/mach-msm/board-mahimahi.c                 |    6 +-
 arch/arm/mach-msm/board-msm7x27.c                  |   10 +-
 arch/arm/mach-msm/board-msm7x30.c                  |    8 +-
 arch/arm/mach-msm/board-msm8960.c                  |    4 +-
 arch/arm/mach-msm/board-msm8x60.c                  |    4 +-
 arch/arm/mach-msm/board-qsd8x50.c                  |   10 +-
 arch/arm/mach-msm/board-sapphire.c                 |    8 +-
 arch/arm/mach-msm/board-trout-mmc.c                |    4 +-
 arch/arm/mach-msm/board-trout-panel.c              |    4 +-
 arch/arm/mach-msm/board-trout.c                    |    6 +-
 arch/arm/mach-msm/board-trout.h                    |    4 +-
 arch/arm/mach-msm/clock-pcom.c                     |    2 +-
 arch/arm/mach-msm/clock.h                          |    2 +-
 arch/arm/mach-msm/devices-iommu.c                  |    4 +-
 arch/arm/mach-msm/devices-msm7x00.c                |    6 +-
 arch/arm/mach-msm/devices-msm7x30.c                |   10 +-
 arch/arm/mach-msm/devices-msm8960.c                |    4 +-
 arch/arm/mach-msm/devices-qsd8x50.c                |   10 +-
 arch/arm/mach-msm/dma.c                            |    2 +-
 arch/arm/mach-msm/gpiomux-v2.c                     |    2 +-
 arch/arm/mach-msm/gpiomux.h                        |    2 +-
 arch/arm/mach-msm/include/mach-msm/board.h         |   56 +
 arch/arm/mach-msm/include/{mach => mach-msm}/clk.h |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/cpu.h |    0
 arch/arm/mach-msm/include/mach-msm/debug-macro.S   |   65 +
 arch/arm/mach-msm/include/mach-msm/dma.h           |  177 +++
 arch/arm/mach-msm/include/mach-msm/entry-macro.S   |   36 +
 .../mach => mach-msm/include/mach-msm}/gpio.h      |    0
 .../mach-msm/include/{mach => mach-msm}/hardware.h |    0
 .../mach-msm/include/{mach => mach-msm}/iommu.h    |    0
 .../include/{mach => mach-msm}/iommu_hw-8xxx.h     |    0
 .../include/{mach => mach-msm}/irqs-7x00.h         |    0
 .../include/{mach => mach-msm}/irqs-7x30.h         |    0
 .../include/{mach => mach-msm}/irqs-8960.h         |    0
 .../include/{mach => mach-msm}/irqs-8x50.h         |    0
 .../include/{mach => mach-msm}/irqs-8x60.h         |    0
 .../arm/mach-msm/include/{mach => mach-msm}/irqs.h |    0
 arch/arm/mach-msm/include/{mach => mach-msm}/mmc.h |    0
 .../mach-msm/include/{mach => mach-msm}/msm_fb.h   |    0
 .../include/{mach => mach-msm}/msm_gpiomux.h       |    0
 .../include/{mach => mach-msm}/msm_iomap-7x00.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-7x30.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8960.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8x50.h    |    0
 .../include/{mach => mach-msm}/msm_iomap-8x60.h    |    0
 .../include/{mach => mach-msm}/msm_iomap.h         |    0
 .../mach-msm/include/{mach => mach-msm}/msm_smd.h  |    0
 arch/arm/mach-msm/include/mach-msm/sirc.h          |   98 ++
 .../mach-msm/include/{mach => mach-msm}/system.h   |    0
 .../mach-msm/include/{mach => mach-msm}/timex.h    |    0
 arch/arm/mach-msm/include/mach-msm/uncompress.h    |   67 +
 .../arm/mach-msm/include/{mach => mach-msm}/vreg.h |    0
 arch/arm/mach-msm/include/mach/board.h             |   56 -
 arch/arm/mach-msm/include/mach/debug-macro.S       |   65 -
 arch/arm/mach-msm/include/mach/dma.h               |  177 ---
 arch/arm/mach-msm/include/mach/entry-macro.S       |   36 -
 arch/arm/mach-msm/include/mach/sirc.h              |   98 --
 arch/arm/mach-msm/include/mach/uncompress.h        |   67 -
 arch/arm/mach-msm/io.c                             |    6 +-
 arch/arm/mach-msm/irq-vic.c                        |    4 +-
 arch/arm/mach-msm/irq.c                            |    4 +-
 arch/arm/mach-msm/platsmp.c                        |    2 +-
 arch/arm/mach-msm/proc_comm.c                      |    4 +-
 arch/arm/mach-msm/smd.c                            |    4 +-
 arch/arm/mach-msm/smd_debug.c                      |    2 +-
 arch/arm/mach-msm/smd_private.h                    |    2 +-
 arch/arm/mach-msm/timer.c                          |    6 +-
 arch/arm/mach-msm/vreg.c                           |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    2 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |   16 +-
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |    2 +-
 .../include/mach-mv78xx0/bridge-regs.h             |   36 +
 .../include/mach-mv78xx0/debug-macro.S             |   19 +
 .../include/mach-mv78xx0/entry-macro.S             |   41 +
 arch/arm/mach-mv78xx0/include/mach-mv78xx0/gpio.h  |    9 +
 .../include/{mach => mach-mv78xx0}/hardware.h      |    0
 .../include/{mach => mach-mv78xx0}/io.h            |    0
 .../include/{mach => mach-mv78xx0}/irqs.h          |    0
 .../include/{mach => mach-mv78xx0}/mv78xx0.h       |    0
 .../include/{mach => mach-mv78xx0}/timex.h         |    0
 .../mach-mv78xx0/include/mach-mv78xx0/uncompress.h |   47 +
 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h   |   36 -
 arch/arm/mach-mv78xx0/include/mach/debug-macro.S   |   19 -
 arch/arm/mach-mv78xx0/include/mach/entry-macro.S   |   41 -
 arch/arm/mach-mv78xx0/include/mach/gpio.h          |    9 -
 arch/arm/mach-mv78xx0/include/mach/uncompress.h    |   47 -
 arch/arm/mach-mv78xx0/irq.c                        |    4 +-
 arch/arm/mach-mv78xx0/mpp.c                        |    4 +-
 arch/arm/mach-mv78xx0/pcie.c                       |    4 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |    2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |    2 +-
 .../include/{mach => mach-mvebu}/armada-370-xp.h   |    0
 .../mach-mvebu/include/mach-mvebu/debug-macro.S    |   24 +
 .../include/{mach => mach-mvebu}/timex.h           |    0
 .../arm/mach-mvebu/include/mach-mvebu/uncompress.h |   43 +
 arch/arm/mach-mvebu/include/mach/debug-macro.S     |   24 -
 arch/arm/mach-mvebu/include/mach/uncompress.h      |   43 -
 arch/arm/mach-mxs/devices-mx23.h                   |    4 +-
 arch/arm/mach-mxs/devices-mx28.h                   |    4 +-
 arch/arm/mach-mxs/devices/platform-auart.c         |    6 +-
 arch/arm/mach-mxs/devices/platform-dma.c           |    6 +-
 arch/arm/mach-mxs/devices/platform-fec.c           |    4 +-
 arch/arm/mach-mxs/devices/platform-flexcan.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c      |    6 +-
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c     |    6 +-
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c       |    6 +-
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c       |    2 +-
 arch/arm/mach-mxs/devices/platform-mxs-saif.c      |    6 +-
 arch/arm/mach-mxs/devices/platform-mxsfb.c         |    6 +-
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c  |    6 +-
 arch/arm/mach-mxs/icoll.c                          |    4 +-
 .../mach-mxs/include/{mach => mach-mxs}/common.h   |    0
 arch/arm/mach-mxs/include/mach-mxs/debug-macro.S   |   30 +
 .../include/{mach => mach-mxs}/devices-common.h    |    0
 .../mach-mxs/include/{mach => mach-mxs}/digctl.h   |    0
 arch/arm/mach-mxs/include/mach-mxs/entry-macro.S   |   35 +
 .../mach => mach-mxs/include/mach-mxs}/gpio.h      |    0
 .../mach-mxs/include/{mach => mach-mxs}/hardware.h |    0
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx23.h    |  355 +++++
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx28.h    |  537 +++++++
 .../mach-mxs/include/{mach => mach-mxs}/iomux.h    |    0
 .../arm/mach-mxs/include/{mach => mach-mxs}/irqs.h |    0
 arch/arm/mach-mxs/include/mach-mxs/mx23.h          |  169 ++
 arch/arm/mach-mxs/include/mach-mxs/mx28.h          |  225 +++
 arch/arm/mach-mxs/include/mach-mxs/mxs.h           |  117 ++
 .../mach-mxs/include/{mach => mach-mxs}/timex.h    |    0
 .../include/{mach => mach-mxs}/uncompress.h        |    0
 arch/arm/mach-mxs/include/mach/debug-macro.S       |   30 -
 arch/arm/mach-mxs/include/mach/entry-macro.S       |   35 -
 arch/arm/mach-mxs/include/mach/iomux-mx23.h        |  355 -----
 arch/arm/mach-mxs/include/mach/iomux-mx28.h        |  537 -------
 arch/arm/mach-mxs/include/mach/mx23.h              |  169 --
 arch/arm/mach-mxs/include/mach/mx28.h              |  225 ---
 arch/arm/mach-mxs/include/mach/mxs.h               |  117 --
 arch/arm/mach-mxs/iomux.c                          |    4 +-
 arch/arm/mach-mxs/mach-apx4devkit.c                |    6 +-
 arch/arm/mach-mxs/mach-m28evk.c                    |    4 +-
 arch/arm/mach-mxs/mach-mx23evk.c                   |    4 +-
 arch/arm/mach-mxs/mach-mx28evk.c                   |    6 +-
 arch/arm/mach-mxs/mach-mxs.c                       |    2 +-
 arch/arm/mach-mxs/mach-stmp378x_devb.c             |    4 +-
 arch/arm/mach-mxs/mach-tx28.c                      |    4 +-
 arch/arm/mach-mxs/mm.c                             |    8 +-
 arch/arm/mach-mxs/module-tx28.c                    |    2 +-
 arch/arm/mach-mxs/ocotp.c                          |    2 +-
 arch/arm/mach-mxs/system.c                         |    4 +-
 arch/arm/mach-mxs/timer.c                          |    4 +-
 arch/arm/mach-netx/fb.c                            |    4 +-
 arch/arm/mach-netx/generic.c                       |    4 +-
 .../include/{mach => mach-netx}/debug-macro.S      |    0
 .../mach-netx/include/{mach => mach-netx}/eth.h    |    0
 .../include/{mach => mach-netx}/hardware.h         |    0
 .../mach-netx/include/{mach => mach-netx}/irqs.h   |    0
 .../include/{mach => mach-netx}/netx-regs.h        |    0
 .../mach-netx/include/{mach => mach-netx}/param.h  |    0
 .../mach-netx/include/{mach => mach-netx}/pfifo.h  |    0
 .../mach-netx/include/{mach => mach-netx}/timex.h  |    0
 .../include/{mach => mach-netx}/uncompress.h       |    0
 .../arm/mach-netx/include/{mach => mach-netx}/xc.h |    0
 arch/arm/mach-netx/nxdb500.c                       |    6 +-
 arch/arm/mach-netx/nxdkn.c                         |    6 +-
 arch/arm/mach-netx/nxeb500hmi.c                    |    6 +-
 arch/arm/mach-netx/pfifo.c                         |    6 +-
 arch/arm/mach-netx/time.c                          |    4 +-
 arch/arm/mach-netx/xc.c                            |    8 +-
 arch/arm/mach-nomadik/board-nhk8815.c              |    8 +-
 arch/arm/mach-nomadik/cpu-8815.c                   |    6 +-
 arch/arm/mach-nomadik/i2c-8815nhk.c                |    4 +-
 .../include/{mach => mach-nomadik}/debug-macro.S   |    0
 arch/arm/mach-nomadik/include/mach-nomadik/fsmc.h  |   29 +
 .../include/{mach => mach-nomadik}/gpio.h          |    0
 .../include/{mach => mach-nomadik}/hardware.h      |    0
 arch/arm/mach-nomadik/include/mach-nomadik/irqs.h  |   81 +
 .../include/{mach => mach-nomadik}/nand.h          |    0
 .../include/{mach => mach-nomadik}/timex.h         |    0
 .../mach-nomadik/include/mach-nomadik/uncompress.h |   63 +
 arch/arm/mach-nomadik/include/mach/fsmc.h          |   29 -
 arch/arm/mach-nomadik/include/mach/irqs.h          |   81 -
 arch/arm/mach-nomadik/include/mach/uncompress.h    |   63 -
 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    4 +-
 arch/arm/mach-omap1/ams-delta-fiq.c                |    4 +-
 arch/arm/mach-omap1/board-ams-delta.c              |   18 +-
 arch/arm/mach-omap1/board-fsample.c                |   16 +-
 arch/arm/mach-omap1/board-generic.c                |    8 +-
 arch/arm/mach-omap1/board-h2-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h2.c                     |   18 +-
 arch/arm/mach-omap1/board-h3-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h3.c                     |   18 +-
 arch/arm/mach-omap1/board-htcherald.c              |   12 +-
 arch/arm/mach-omap1/board-innovator.c              |   18 +-
 arch/arm/mach-omap1/board-nokia770.c               |   18 +-
 arch/arm/mach-omap1/board-osk.c                    |   12 +-
 arch/arm/mach-omap1/board-palmte.c                 |   18 +-
 arch/arm/mach-omap1/board-palmtt.c                 |   22 +-
 arch/arm/mach-omap1/board-palmz71.c                |   20 +-
 arch/arm/mach-omap1/board-perseus2.c               |   16 +-
 arch/arm/mach-omap1/board-sx1-mmc.c                |    6 +-
 arch/arm/mach-omap1/board-sx1.c                    |   22 +-
 arch/arm/mach-omap1/board-voiceblue.c              |   16 +-
 arch/arm/mach-omap1/clock.c                        |   12 +-
 arch/arm/mach-omap1/clock.h                        |    2 +-
 arch/arm/mach-omap1/clock_data.c                   |   16 +-
 arch/arm/mach-omap1/common.h                       |    2 +-
 arch/arm/mach-omap1/devices.c                      |   18 +-
 arch/arm/mach-omap1/dma.c                          |    6 +-
 arch/arm/mach-omap1/flash.c                        |    6 +-
 arch/arm/mach-omap1/fpga.c                         |    4 +-
 arch/arm/mach-omap1/i2c.c                          |    6 +-
 arch/arm/mach-omap1/id.c                           |    4 +-
 .../mach-omap1/include/mach-omap1/ams-delta-fiq.h  |   79 +
 .../include/{mach => mach-omap1}/camera.h          |    0
 .../mach-omap1/include/mach-omap1/debug-macro.S    |  101 ++
 .../mach-omap1/include/mach-omap1/entry-macro.S    |   41 +
 arch/arm/mach-omap1/include/mach-omap1/gpio.h      |    5 +
 arch/arm/mach-omap1/include/mach-omap1/hardware.h  |   41 +
 .../mach-omap1/include/{mach => mach-omap1}/io.h   |    0
 arch/arm/mach-omap1/include/mach-omap1/irqs.h      |    5 +
 .../include/{mach => mach-omap1}/lcd_dma.h         |    0
 .../mach-omap1/include/{mach => mach-omap1}/lcdc.h |    0
 arch/arm/mach-omap1/include/mach-omap1/memory.h    |   57 +
 arch/arm/mach-omap1/include/mach-omap1/mtd-xip.h   |   61 +
 arch/arm/mach-omap1/include/mach-omap1/smp.h       |    5 +
 arch/arm/mach-omap1/include/mach-omap1/timex.h     |    5 +
 .../arm/mach-omap1/include/mach-omap1/uncompress.h |    5 +
 .../mach-omap1/include/{mach => mach-omap1}/usb.h  |    0
 arch/arm/mach-omap1/include/mach/ams-delta-fiq.h   |   79 -
 arch/arm/mach-omap1/include/mach/debug-macro.S     |  101 --
 arch/arm/mach-omap1/include/mach/entry-macro.S     |   41 -
 arch/arm/mach-omap1/include/mach/gpio.h            |    5 -
 arch/arm/mach-omap1/include/mach/hardware.h        |   41 -
 arch/arm/mach-omap1/include/mach/irqs.h            |    5 -
 arch/arm/mach-omap1/include/mach/memory.h          |   57 -
 arch/arm/mach-omap1/include/mach/mtd-xip.h         |   61 -
 arch/arm/mach-omap1/include/mach/smp.h             |    5 -
 arch/arm/mach-omap1/include/mach/timex.h           |    5 -
 arch/arm/mach-omap1/include/mach/uncompress.h      |    5 -
 arch/arm/mach-omap1/io.c                           |    6 +-
 arch/arm/mach-omap1/irq.c                          |    4 +-
 arch/arm/mach-omap1/lcd_dma.c                      |    6 +-
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 +-
 arch/arm/mach-omap1/leds-innovator.c               |    2 +-
 arch/arm/mach-omap1/leds-osk.c                     |    2 +-
 arch/arm/mach-omap1/leds.c                         |    2 +-
 arch/arm/mach-omap1/mailbox.c                      |    2 +-
 arch/arm/mach-omap1/mcbsp.c                        |   10 +-
 arch/arm/mach-omap1/mux.c                          |    4 +-
 arch/arm/mach-omap1/ocpi.c                         |    2 +-
 arch/arm/mach-omap1/opp_data.c                     |    2 +-
 arch/arm/mach-omap1/pm.c                           |   18 +-
 arch/arm/mach-omap1/pm_bus.c                       |    4 +-
 arch/arm/mach-omap1/reset.c                        |    4 +-
 arch/arm/mach-omap1/serial.c                       |    6 +-
 arch/arm/mach-omap1/sram.S                         |    2 +-
 arch/arm/mach-omap1/time.c                         |    2 +-
 arch/arm/mach-omap1/timer.c                        |    4 +-
 arch/arm/mach-omap1/timer32k.c                     |    4 +-
 arch/arm/mach-omap1/usb.c                          |    4 +-
 arch/arm/mach-omap2/am35xx-emac.c                  |    4 +-
 arch/arm/mach-omap2/board-2430sdp.c                |   10 +-
 arch/arm/mach-omap2/board-3430sdp.c                |   14 +-
 arch/arm/mach-omap2/board-3630sdp.c                |    8 +-
 arch/arm/mach-omap2/board-4430sdp.c                |   10 +-
 arch/arm/mach-omap2/board-am3517crane.c            |    6 +-
 arch/arm/mach-omap2/board-am3517evm.c              |    8 +-
 arch/arm/mach-omap2/board-apollon.c                |    8 +-
 arch/arm/mach-omap2/board-cm-t35.c                 |   14 +-
 arch/arm/mach-omap2/board-cm-t3517.c               |   10 +-
 arch/arm/mach-omap2/board-devkit8000.c             |   14 +-
 arch/arm/mach-omap2/board-flash.c                  |   10 +-
 arch/arm/mach-omap2/board-flash.h                  |    2 +-
 arch/arm/mach-omap2/board-generic.c                |    4 +-
 arch/arm/mach-omap2/board-h4.c                     |   10 +-
 arch/arm/mach-omap2/board-igep0020.c               |   10 +-
 arch/arm/mach-omap2/board-ldp.c                    |   14 +-
 arch/arm/mach-omap2/board-n8x0.c                   |   14 +-
 arch/arm/mach-omap2/board-omap3beagle.c            |   12 +-
 arch/arm/mach-omap2/board-omap3evm.c               |   12 +-
 arch/arm/mach-omap2/board-omap3logic.c             |   14 +-
 arch/arm/mach-omap2/board-omap3pandora.c           |   10 +-
 arch/arm/mach-omap2/board-omap3stalker.c           |   14 +-
 arch/arm/mach-omap2/board-omap3touchbook.c         |   12 +-
 arch/arm/mach-omap2/board-omap4panda.c             |    8 +-
 arch/arm/mach-omap2/board-overo.c                  |   16 +-
 arch/arm/mach-omap2/board-rm680.c                  |   10 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c       |   14 +-
 arch/arm/mach-omap2/board-rx51-video.c             |    6 +-
 arch/arm/mach-omap2/board-rx51.c                   |   12 +-
 arch/arm/mach-omap2/board-ti8168evm.c              |    8 +-
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    6 +-
 arch/arm/mach-omap2/board-zoom-display.c           |    4 +-
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    4 +-
 arch/arm/mach-omap2/board-zoom.c                   |    6 +-
 arch/arm/mach-omap2/clkt2xxx_apll.c                |    4 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c                |    2 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c            |    6 +-
 arch/arm/mach-omap2/clkt2xxx_osc.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c       |    8 +-
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c             |    6 +-
 arch/arm/mach-omap2/clkt_clksel.c                  |    2 +-
 arch/arm/mach-omap2/clkt_dpll.c                    |    4 +-
 arch/arm/mach-omap2/clkt_iclk.c                    |    4 +-
 arch/arm/mach-omap2/clock.c                        |    6 +-
 arch/arm/mach-omap2/clock.h                        |    2 +-
 arch/arm/mach-omap2/clock2420_data.c               |    4 +-
 arch/arm/mach-omap2/clock2430.c                    |    4 +-
 arch/arm/mach-omap2/clock2430_data.c               |    4 +-
 arch/arm/mach-omap2/clock2xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock33xx_data.c               |    4 +-
 arch/arm/mach-omap2/clock34xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3517.c                    |    2 +-
 arch/arm/mach-omap2/clock36xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock3xxx_data.c               |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c               |    4 +-
 arch/arm/mach-omap2/clockdomain.c                  |    2 +-
 arch/arm/mach-omap2/clockdomain.h                  |    6 +-
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx.c                  |    2 +-
 arch/arm/mach-omap2/cm33xx.c                       |    2 +-
 arch/arm/mach-omap2/common-board-devices.c         |    4 +-
 arch/arm/mach-omap2/common.c                       |    8 +-
 arch/arm/mach-omap2/common.h                       |    2 +-
 arch/arm/mach-omap2/control.c                      |    4 +-
 arch/arm/mach-omap2/control.h                      |   10 +-
 arch/arm/mach-omap2/cpuidle34xx.c                  |    4 +-
 arch/arm/mach-omap2/devices.c                      |   18 +-
 arch/arm/mach-omap2/display.c                      |    6 +-
 arch/arm/mach-omap2/dma.c                          |    6 +-
 arch/arm/mach-omap2/dpll3xxx.c                     |    4 +-
 arch/arm/mach-omap2/dpll44xx.c                     |    4 +-
 arch/arm/mach-omap2/drm.c                          |    4 +-
 arch/arm/mach-omap2/dsp.c                          |    4 +-
 arch/arm/mach-omap2/emu.c                          |    2 +-
 arch/arm/mach-omap2/gpio.c                         |    6 +-
 arch/arm/mach-omap2/gpmc-nand.c                    |    8 +-
 arch/arm/mach-omap2/gpmc-onenand.c                 |    8 +-
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    6 +-
 arch/arm/mach-omap2/gpmc-smsc911x.c                |    6 +-
 arch/arm/mach-omap2/gpmc.c                         |    4 +-
 arch/arm/mach-omap2/hdq1w.c                        |    6 +-
 arch/arm/mach-omap2/hsmmc.c                        |   10 +-
 arch/arm/mach-omap2/hwspinlock.c                   |    4 +-
 arch/arm/mach-omap2/i2c.c                          |    6 +-
 arch/arm/mach-omap2/id.c                           |    4 +-
 .../include/{mach => mach-omap2}/am35xx.h          |    0
 .../include/{mach => mach-omap2}/barriers.h        |    0
 .../include/{mach => mach-omap2}/board-rx51.h      |    0
 .../include/{mach => mach-omap2}/board-zoom.h      |    0
 .../{mach => mach-omap2}/ctrl_module_core_44xx.h   |    0
 .../ctrl_module_pad_core_44xx.h                    |    0
 .../ctrl_module_pad_wkup_44xx.h                    |    0
 .../{mach => mach-omap2}/ctrl_module_wkup_44xx.h   |    0
 .../mach-omap2/include/mach-omap2/debug-macro.S    |  165 ++
 arch/arm/mach-omap2/include/mach-omap2/gpio.h      |    5 +
 arch/arm/mach-omap2/include/mach-omap2/hardware.h  |    5 +
 .../mach-omap2/include/{mach => mach-omap2}/id.h   |    0
 arch/arm/mach-omap2/include/mach-omap2/irqs.h      |    5 +
 .../include/{mach => mach-omap2}/omap-secure.h     |    0
 .../include/{mach => mach-omap2}/omap-wakeupgen.h  |    0
 arch/arm/mach-omap2/include/mach-omap2/smp.h       |    5 +
 arch/arm/mach-omap2/include/mach-omap2/timex.h     |    5 +
 .../arm/mach-omap2/include/mach-omap2/uncompress.h |    5 +
 arch/arm/mach-omap2/include/mach/debug-macro.S     |  165 --
 arch/arm/mach-omap2/include/mach/gpio.h            |    5 -
 arch/arm/mach-omap2/include/mach/hardware.h        |    5 -
 arch/arm/mach-omap2/include/mach/irqs.h            |    5 -
 arch/arm/mach-omap2/include/mach/smp.h             |    5 -
 arch/arm/mach-omap2/include/mach/timex.h           |    5 -
 arch/arm/mach-omap2/include/mach/uncompress.h      |    5 -
 arch/arm/mach-omap2/io.c                           |   14 +-
 arch/arm/mach-omap2/iommu2.c                       |    2 +-
 arch/arm/mach-omap2/irq.c                          |    2 +-
 arch/arm/mach-omap2/mailbox.c                      |    4 +-
 arch/arm/mach-omap2/mcbsp.c                        |   10 +-
 arch/arm/mach-omap2/msdi.c                         |    6 +-
 arch/arm/mach-omap2/mux.c                          |    2 +-
 arch/arm/mach-omap2/omap-hotplug.c                 |    2 +-
 arch/arm/mach-omap2/omap-iommu.c                   |    4 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c          |    2 +-
 arch/arm/mach-omap2/omap-secure.c                  |    4 +-
 arch/arm/mach-omap2/omap-smp.c                     |    6 +-
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |   12 +-
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   24 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   24 +-
 .../omap_hwmod_2xxx_3xxx_interconnect_data.c       |    4 +-
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 +-
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |    8 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   16 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   28 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   20 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.c       |    2 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    2 +-
 arch/arm/mach-omap2/omap_opp_data.h                |    2 +-
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 +-
 arch/arm/mach-omap2/opp.c                          |    2 +-
 arch/arm/mach-omap2/opp2420_data.c                 |    2 +-
 arch/arm/mach-omap2/opp2430_data.c                 |    2 +-
 arch/arm/mach-omap2/opp3xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/opp4xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                     |    8 +-
 arch/arm/mach-omap2/pm.c                           |    4 +-
 arch/arm/mach-omap2/pm24xx.c                       |   10 +-
 arch/arm/mach-omap2/pm34xx.c                       |   10 +-
 arch/arm/mach-omap2/powerdomain.c                  |    4 +-
 arch/arm/mach-omap2/powerdomain.h                  |    2 +-
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/powerdomain33xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomain44xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c        |    2 +-
 arch/arm/mach-omap2/prcm.c                         |    4 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    6 +-
 arch/arm/mach-omap2/prm33xx.c                      |    2 +-
 arch/arm/mach-omap2/prm44xx.c                      |    6 +-
 arch/arm/mach-omap2/prm_common.c                   |    6 +-
 arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h |    2 +-
 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h  |    2 +-
 arch/arm/mach-omap2/sdram-nokia.c                  |    4 +-
 arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h     |    2 +-
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    2 +-
 arch/arm/mach-omap2/sdrc.c                         |    6 +-
 arch/arm/mach-omap2/sdrc.h                         |    2 +-
 arch/arm/mach-omap2/sdrc2xxx.c                     |    8 +-
 arch/arm/mach-omap2/serial.c                       |   12 +-
 arch/arm/mach-omap2/sleep24xx.S                    |    2 +-
 arch/arm/mach-omap2/sleep34xx.S                    |    4 +-
 arch/arm/mach-omap2/sleep44xx.S                    |    4 +-
 arch/arm/mach-omap2/sr_device.c                    |    2 +-
 arch/arm/mach-omap2/sram242x.S                     |    2 +-
 arch/arm/mach-omap2/sram243x.S                     |    2 +-
 arch/arm/mach-omap2/sram34xx.S                     |    2 +-
 arch/arm/mach-omap2/timer.c                        |    8 +-
 arch/arm/mach-omap2/twl-common.c                   |    4 +-
 arch/arm/mach-omap2/twl-common.h                   |    2 +-
 arch/arm/mach-omap2/usb-host.c                     |    8 +-
 arch/arm/mach-omap2/usb-musb.c                     |   10 +-
 arch/arm/mach-omap2/usb-tusb6010.c                 |    2 +-
 arch/arm/mach-omap2/vc.c                           |    2 +-
 arch/arm/mach-omap2/voltage.h                      |    2 +-
 arch/arm/mach-omap2/voltagedomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/wd_timer.c                     |    2 +-
 arch/arm/mach-omap2/wd_timer.h                     |    2 +-
 arch/arm/mach-orion5x/addr-map.c                   |    4 +-
 arch/arm/mach-orion5x/common.c                     |   16 +-
 arch/arm/mach-orion5x/d2net-setup.c                |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    4 +-
 arch/arm/mach-orion5x/dns323-setup.c               |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |    2 +-
 .../include/mach-orion5x/bridge-regs.h             |   39 +
 .../include/mach-orion5x/debug-macro.S             |   21 +
 .../include/mach-orion5x/entry-macro.S             |   25 +
 arch/arm/mach-orion5x/include/mach-orion5x/gpio.h  |    9 +
 .../include/{mach => mach-orion5x}/hardware.h      |    0
 arch/arm/mach-orion5x/include/mach-orion5x/io.h    |   22 +
 .../include/{mach => mach-orion5x}/irqs.h          |    0
 .../include/{mach => mach-orion5x}/orion5x.h       |    0
 .../include/{mach => mach-orion5x}/timex.h         |    0
 .../mach-orion5x/include/mach-orion5x/uncompress.h |   49 +
 arch/arm/mach-orion5x/include/mach/bridge-regs.h   |   39 -
 arch/arm/mach-orion5x/include/mach/debug-macro.S   |   21 -
 arch/arm/mach-orion5x/include/mach/entry-macro.S   |   25 -
 arch/arm/mach-orion5x/include/mach/gpio.h          |    9 -
 arch/arm/mach-orion5x/include/mach/io.h            |   22 -
 arch/arm/mach-orion5x/include/mach/uncompress.h    |   49 -
 arch/arm/mach-orion5x/irq.c                        |    4 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    4 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |    2 +-
 arch/arm/mach-orion5x/mpp.c                        |    4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |    4 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c              |    2 +-
 arch/arm/mach-orion5x/pci.c                        |    6 +-
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c               |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c               |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |    2 +-
 arch/arm/mach-picoxcell/common.c                   |    4 +-
 .../include/mach-picoxcell/debug-macro.S           |   35 +
 .../include/mach-picoxcell}/gpio.h                 |    0
 .../include/mach-picoxcell/hardware.h              |   21 +
 .../include/{mach => mach-picoxcell}/map.h         |    0
 .../{mach => mach-picoxcell}/picoxcell_soc.h       |    0
 .../include/{mach => mach-picoxcell}/timex.h       |    0
 .../include/{mach => mach-picoxcell}/uncompress.h  |    0
 arch/arm/mach-picoxcell/include/mach/debug-macro.S |   35 -
 arch/arm/mach-picoxcell/include/mach/hardware.h    |   21 -
 arch/arm/mach-pnx4008/clock.c                      |    4 +-
 arch/arm/mach-pnx4008/core.c                       |    8 +-
 arch/arm/mach-pnx4008/dma.c                        |    6 +-
 arch/arm/mach-pnx4008/gpio.c                       |    6 +-
 arch/arm/mach-pnx4008/i2c.c                        |    4 +-
 .../include/{mach => mach-pnx4008}/clock.h         |    0
 .../include/{mach => mach-pnx4008}/debug-macro.S   |    0
 .../include/{mach => mach-pnx4008}/dma.h           |    0
 .../include/{mach => mach-pnx4008}/entry-macro.S   |    0
 .../include/{mach => mach-pnx4008}/gpio-pnx4008.h  |    0
 .../mach-pnx4008/include/mach-pnx4008/hardware.h   |   32 +
 .../include/{mach => mach-pnx4008}/irq.h           |    0
 .../include/{mach => mach-pnx4008}/irqs.h          |    0
 .../include/{mach => mach-pnx4008}/param.h         |    0
 .../include/{mach => mach-pnx4008}/platform.h      |    0
 .../include/{mach => mach-pnx4008}/pm.h            |    0
 .../include/{mach => mach-pnx4008}/timex.h         |    0
 .../include/{mach => mach-pnx4008}/uncompress.h    |    0
 arch/arm/mach-pnx4008/include/mach/hardware.h      |   32 -
 arch/arm/mach-pnx4008/irq.c                        |    4 +-
 arch/arm/mach-pnx4008/pm.c                         |    6 +-
 arch/arm/mach-pnx4008/serial.c                     |    8 +-
 arch/arm/mach-pnx4008/sleep.S                      |    2 +-
 arch/arm/mach-pnx4008/time.c                       |    2 +-
 arch/arm/mach-pnx4008/time.h                       |    2 +-
 arch/arm/mach-prima2/clock.c                       |    2 +-
 .../include/{mach => mach-prima2}/clkdev.h         |    0
 .../mach-prima2/include/mach-prima2/debug-macro.S  |   29 +
 .../mach-prima2/include/mach-prima2/entry-macro.S  |   22 +
 .../include/{mach => mach-prima2}/gpio.h           |    0
 .../arm/mach-prima2/include/mach-prima2/hardware.h |   15 +
 .../include/{mach => mach-prima2}/irqs.h           |    0
 .../include/{mach => mach-prima2}/map.h            |    0
 .../include/{mach => mach-prima2}/timex.h          |    0
 .../include/{mach => mach-prima2}/uart.h           |    0
 .../mach-prima2/include/mach-prima2/uncompress.h   |   40 +
 arch/arm/mach-prima2/include/mach/debug-macro.S    |   29 -
 arch/arm/mach-prima2/include/mach/entry-macro.S    |   22 -
 arch/arm/mach-prima2/include/mach/hardware.h       |   15 -
 arch/arm/mach-prima2/include/mach/uncompress.h     |   40 -
 arch/arm/mach-prima2/irq.c                         |    2 +-
 arch/arm/mach-prima2/lluart.c                      |    4 +-
 arch/arm/mach-prima2/timer.c                       |    2 +-
 arch/arm/mach-pxa/am200epd.c                       |    6 +-
 arch/arm/mach-pxa/am300epd.c                       |    6 +-
 arch/arm/mach-pxa/balloon3.c                       |   18 +-
 arch/arm/mach-pxa/capc7117.c                       |    4 +-
 arch/arm/mach-pxa/clock-pxa2xx.c                   |    2 +-
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    4 +-
 arch/arm/mach-pxa/cm-x255.c                        |    2 +-
 arch/arm/mach-pxa/cm-x270.c                        |    6 +-
 arch/arm/mach-pxa/cm-x2xx.c                        |   10 +-
 arch/arm/mach-pxa/cm-x300.c                        |   16 +-
 arch/arm/mach-pxa/colibri-evalboard.c              |   12 +-
 arch/arm/mach-pxa/colibri-pxa270-income.c          |   12 +-
 arch/arm/mach-pxa/colibri-pxa270.c                 |    6 +-
 arch/arm/mach-pxa/colibri-pxa300.c                 |   10 +-
 arch/arm/mach-pxa/colibri-pxa320.c                 |   14 +-
 arch/arm/mach-pxa/colibri-pxa3xx.c                 |   14 +-
 arch/arm/mach-pxa/corgi.c                          |   14 +-
 arch/arm/mach-pxa/corgi_pm.c                       |    8 +-
 arch/arm/mach-pxa/cpufreq-pxa2xx.c                 |    4 +-
 arch/arm/mach-pxa/cpufreq-pxa3xx.c                 |    2 +-
 arch/arm/mach-pxa/csb726.c                         |   12 +-
 arch/arm/mach-pxa/devices.c                        |   24 +-
 arch/arm/mach-pxa/em-x270.c                        |   16 +-
 arch/arm/mach-pxa/eseries.c                        |   14 +-
 arch/arm/mach-pxa/ezx.c                            |   12 +-
 arch/arm/mach-pxa/generic.c                        |    8 +-
 arch/arm/mach-pxa/gumstix.c                        |   10 +-
 arch/arm/mach-pxa/h5000.c                          |    8 +-
 arch/arm/mach-pxa/himalaya.c                       |    2 +-
 arch/arm/mach-pxa/hx4700.c                         |    8 +-
 arch/arm/mach-pxa/icontrol.c                       |    4 +-
 arch/arm/mach-pxa/idp.c                            |   12 +-
 .../mach-pxa/include/{mach => mach-pxa}/addr-map.h |    0
 .../include/{mach => mach-pxa}/arcom-pcmcia.h      |    0
 .../mach-pxa/include/{mach => mach-pxa}/audio.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/balloon3.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/bitfield.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/camera.h   |    0
 arch/arm/mach-pxa/include/mach-pxa/colibri.h       |   69 +
 .../mach-pxa/include/{mach => mach-pxa}/corgi.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/csb726.h   |    0
 .../include/{mach => mach-pxa}/debug-macro.S       |    0
 arch/arm/mach-pxa/include/mach-pxa/dma.h           |   21 +
 .../include/{mach => mach-pxa}/eseries-gpio.h      |    0
 .../include/{mach => mach-pxa}/eseries-irq.h       |    0
 arch/arm/mach-pxa/include/mach-pxa/gpio.h          |   32 +
 .../mach-pxa/include/{mach => mach-pxa}/gumstix.h  |    0
 arch/arm/mach-pxa/include/mach-pxa/h5000.h         |  113 ++
 arch/arm/mach-pxa/include/mach-pxa/hardware.h      |  338 ++++
 .../mach-pxa/include/{mach => mach-pxa}/hx4700.h   |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/idp.h |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/io.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/irda.h |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/irqs.h |    0
 .../include/{mach => mach-pxa}/littleton.h         |    0
 .../mach-pxa/include/{mach => mach-pxa}/lpd270.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/lubbock.h  |    0
 arch/arm/mach-pxa/include/mach-pxa/magician.h      |  120 ++
 arch/arm/mach-pxa/include/mach-pxa/mainstone.h     |  141 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa25x.h    |  225 +++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa27x.h    |  468 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa2xx.h    |  142 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa300.h    |  575 +++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa320.h    |  461 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa3xx.h    |  158 ++
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa930.h    |  498 ++++++
 arch/arm/mach-pxa/include/mach-pxa/mfp.h           |   21 +
 .../mach-pxa/include/{mach => mach-pxa}/mioa701.h  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/mmc.h |    0
 arch/arm/mach-pxa/include/mach-pxa/mtd-xip.h       |   35 +
 .../mach-pxa/include/{mach => mach-pxa}/mxm8x10.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/ohci.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palm27x.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmasoc.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmld.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmt5.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtc.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmte2.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtreo.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmtx.h   |    0
 .../mach-pxa/include/{mach => mach-pxa}/palmz72.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/pata_pxa.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/pcm027.h   |    0
 .../mach-pxa/include/mach-pxa/pcm990_baseboard.h   |  211 +++
 arch/arm/mach-pxa/include/{mach => mach-pxa}/pm.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/poodle.h   |    0
 .../include/{mach => mach-pxa}/pxa25x-udc.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa25x.h        |   17 +
 .../include/{mach => mach-pxa}/pxa27x-udc.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa27x.h        |   29 +
 arch/arm/mach-pxa/include/mach-pxa/pxa2xx-regs.h   |  187 +++
 arch/arm/mach-pxa/include/mach-pxa/pxa300.h        |    7 +
 arch/arm/mach-pxa/include/mach-pxa/pxa320.h        |    8 +
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx-regs.h   |  205 +++
 .../include/{mach => mach-pxa}/pxa3xx-u2d.h        |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx.h        |   14 +
 arch/arm/mach-pxa/include/mach-pxa/pxa930.h        |    7 +
 .../include/{mach => mach-pxa}/pxa930_rotary.h     |    0
 .../include/{mach => mach-pxa}/pxa930_trkball.h    |    0
 arch/arm/mach-pxa/include/mach-pxa/pxa95x.h        |    7 +
 arch/arm/mach-pxa/include/mach-pxa/pxafb.h         |  175 ++
 arch/arm/mach-pxa/include/mach-pxa/regs-ac97.h     |  101 ++
 arch/arm/mach-pxa/include/mach-pxa/regs-lcd.h      |  197 +++
 arch/arm/mach-pxa/include/mach-pxa/regs-ost.h      |   34 +
 arch/arm/mach-pxa/include/mach-pxa/regs-rtc.h      |   23 +
 arch/arm/mach-pxa/include/mach-pxa/regs-u2d.h      |  200 +++
 .../include/{mach => mach-pxa}/regs-uart.h         |    0
 .../mach-pxa/include/{mach => mach-pxa}/reset.h    |    0
 .../include/{mach => mach-pxa}/sharpsl_pm.h        |    0
 .../mach-pxa/include/{mach => mach-pxa}/smemc.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/spitz.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/timex.h    |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/tosa.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/tosa_bt.h  |    0
 .../mach-pxa/include/{mach => mach-pxa}/trizeps4.h |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/udc.h |    0
 .../include/{mach => mach-pxa}/uncompress.h        |    0
 .../mach-pxa/include/{mach => mach-pxa}/viper.h    |    0
 .../mach-pxa/include/{mach => mach-pxa}/vpac270.h  |    0
 arch/arm/mach-pxa/include/{mach => mach-pxa}/z2.h  |    0
 .../arm/mach-pxa/include/{mach => mach-pxa}/zeus.h |    0
 .../mach-pxa/include/{mach => mach-pxa}/zylonite.h |    0
 arch/arm/mach-pxa/include/mach/colibri.h           |   69 -
 arch/arm/mach-pxa/include/mach/dma.h               |   21 -
 arch/arm/mach-pxa/include/mach/gpio.h              |   32 -
 arch/arm/mach-pxa/include/mach/h5000.h             |  113 --
 arch/arm/mach-pxa/include/mach/hardware.h          |  338 ----
 arch/arm/mach-pxa/include/mach/magician.h          |  120 --
 arch/arm/mach-pxa/include/mach/mainstone.h         |  141 --
 arch/arm/mach-pxa/include/mach/mfp-pxa25x.h        |  225 ---
 arch/arm/mach-pxa/include/mach/mfp-pxa27x.h        |  468 ------
 arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h        |  142 --
 arch/arm/mach-pxa/include/mach/mfp-pxa300.h        |  575 -------
 arch/arm/mach-pxa/include/mach/mfp-pxa320.h        |  461 ------
 arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h        |  158 --
 arch/arm/mach-pxa/include/mach/mfp-pxa930.h        |  498 ------
 arch/arm/mach-pxa/include/mach/mfp.h               |   21 -
 arch/arm/mach-pxa/include/mach/mtd-xip.h           |   35 -
 arch/arm/mach-pxa/include/mach/pcm990_baseboard.h  |  211 ---
 arch/arm/mach-pxa/include/mach/pxa25x.h            |   17 -
 arch/arm/mach-pxa/include/mach/pxa27x.h            |   29 -
 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h       |  187 ---
 arch/arm/mach-pxa/include/mach/pxa300.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxa320.h            |    8 -
 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h       |  205 ---
 arch/arm/mach-pxa/include/mach/pxa3xx.h            |   14 -
 arch/arm/mach-pxa/include/mach/pxa930.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxa95x.h            |    7 -
 arch/arm/mach-pxa/include/mach/pxafb.h             |  175 --
 arch/arm/mach-pxa/include/mach/regs-ac97.h         |  101 --
 arch/arm/mach-pxa/include/mach/regs-lcd.h          |  197 ---
 arch/arm/mach-pxa/include/mach/regs-ost.h          |   34 -
 arch/arm/mach-pxa/include/mach/regs-rtc.h          |   23 -
 arch/arm/mach-pxa/include/mach/regs-u2d.h          |  200 ---
 arch/arm/mach-pxa/irq.c                            |    4 +-
 arch/arm/mach-pxa/leds-idp.c                       |    6 +-
 arch/arm/mach-pxa/leds-lubbock.c                   |    6 +-
 arch/arm/mach-pxa/leds-mainstone.c                 |    6 +-
 arch/arm/mach-pxa/littleton.c                      |   14 +-
 arch/arm/mach-pxa/lpd270.c                         |   18 +-
 arch/arm/mach-pxa/lubbock.c                        |   20 +-
 arch/arm/mach-pxa/magician.c                       |   14 +-
 arch/arm/mach-pxa/mainstone.c                      |   20 +-
 arch/arm/mach-pxa/mfp-pxa2xx.c                     |    4 +-
 arch/arm/mach-pxa/mfp-pxa3xx.c                     |    6 +-
 arch/arm/mach-pxa/mioa701.c                        |   22 +-
 arch/arm/mach-pxa/mp900.c                          |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                        |   12 +-
 arch/arm/mach-pxa/palm27x.c                        |   16 +-
 arch/arm/mach-pxa/palmld.c                         |   18 +-
 arch/arm/mach-pxa/palmt5.c                         |   20 +-
 arch/arm/mach-pxa/palmtc.c                         |   14 +-
 arch/arm/mach-pxa/palmte2.c                        |   16 +-
 arch/arm/mach-pxa/palmtreo.c                       |   28 +-
 arch/arm/mach-pxa/palmtx.c                         |   20 +-
 arch/arm/mach-pxa/palmz72.c                        |   26 +-
 arch/arm/mach-pxa/pcm027.c                         |    4 +-
 arch/arm/mach-pxa/pcm990-baseboard.c               |   14 +-
 arch/arm/mach-pxa/pm.c                             |    2 +-
 arch/arm/mach-pxa/poodle.c                         |   14 +-
 arch/arm/mach-pxa/pxa25x.c                         |   14 +-
 arch/arm/mach-pxa/pxa27x.c                         |   16 +-
 arch/arm/mach-pxa/pxa2xx.c                         |   10 +-
 arch/arm/mach-pxa/pxa300.c                         |    2 +-
 arch/arm/mach-pxa/pxa320.c                         |    2 +-
 arch/arm/mach-pxa/pxa3xx-ulpi.c                    |    6 +-
 arch/arm/mach-pxa/pxa3xx.c                         |   16 +-
 arch/arm/mach-pxa/pxa930.c                         |    2 +-
 arch/arm/mach-pxa/pxa95x.c                         |   12 +-
 arch/arm/mach-pxa/raumfeld.c                       |   10 +-
 arch/arm/mach-pxa/reset.c                          |    4 +-
 arch/arm/mach-pxa/saar.c                           |    4 +-
 arch/arm/mach-pxa/saarb.c                          |   10 +-
 arch/arm/mach-pxa/sharpsl_pm.c                     |    8 +-
 arch/arm/mach-pxa/sleep.S                          |    6 +-
 arch/arm/mach-pxa/smemc.c                          |    4 +-
 arch/arm/mach-pxa/spitz.c                          |   20 +-
 arch/arm/mach-pxa/spitz_pm.c                       |    8 +-
 arch/arm/mach-pxa/standby.S                        |    4 +-
 arch/arm/mach-pxa/stargate2.c                      |   10 +-
 arch/arm/mach-pxa/tavorevb.c                       |    6 +-
 arch/arm/mach-pxa/tavorevb3.c                      |    2 +-
 arch/arm/mach-pxa/time.c                           |    4 +-
 arch/arm/mach-pxa/tosa-bt.c                        |    2 +-
 arch/arm/mach-pxa/tosa.c                           |   18 +-
 arch/arm/mach-pxa/trizeps4.c                       |   16 +-
 arch/arm/mach-pxa/viper.c                          |   12 +-
 arch/arm/mach-pxa/vpac270.c                        |   18 +-
 arch/arm/mach-pxa/xcep.c                           |    6 +-
 arch/arm/mach-pxa/z2.c                             |   14 +-
 arch/arm/mach-pxa/zeus.c                           |   24 +-
 arch/arm/mach-pxa/zylonite.c                       |   16 +-
 arch/arm/mach-pxa/zylonite_pxa300.c                |    4 +-
 arch/arm/mach-pxa/zylonite_pxa320.c                |    4 +-
 arch/arm/mach-realview/core.c                      |   10 +-
 .../include/{mach => mach-realview}/barriers.h     |    0
 .../mach-realview/include/mach-realview/board-eb.h |   96 ++
 .../include/mach-realview/board-pb1176.h           |   83 +
 .../include/mach-realview/board-pb11mp.h           |   98 ++
 .../include/mach-realview/board-pba8.h             |   73 +
 .../include/mach-realview/board-pbx.h              |  108 ++
 .../mach-realview/include/mach-realview/clkdev.h   |   16 +
 .../include/{mach => mach-realview}/debug-macro.S  |    0
 .../include/mach-realview}/gpio.h                  |    0
 .../include/{mach => mach-realview}/hardware.h     |    0
 .../include/{mach => mach-realview}/irqs-eb.h      |    0
 .../include/{mach => mach-realview}/irqs-pb1176.h  |    0
 .../include/{mach => mach-realview}/irqs-pb11mp.h  |    0
 .../include/{mach => mach-realview}/irqs-pba8.h    |    0
 .../include/{mach => mach-realview}/irqs-pbx.h     |    0
 .../arm/mach-realview/include/mach-realview/irqs.h |   40 +
 .../include/{mach => mach-realview}/memory.h       |    0
 .../include/{mach => mach-realview}/platform.h     |    0
 .../include/{mach => mach-realview}/timex.h        |    0
 .../include/mach-realview/uncompress.h             |   78 +
 arch/arm/mach-realview/include/mach/board-eb.h     |   96 --
 arch/arm/mach-realview/include/mach/board-pb1176.h |   83 -
 arch/arm/mach-realview/include/mach/board-pb11mp.h |   98 --
 arch/arm/mach-realview/include/mach/board-pba8.h   |   73 -
 arch/arm/mach-realview/include/mach/board-pbx.h    |  108 --
 arch/arm/mach-realview/include/mach/clkdev.h       |   16 -
 arch/arm/mach-realview/include/mach/irqs.h         |   40 -
 arch/arm/mach-realview/include/mach/uncompress.h   |   78 -
 arch/arm/mach-realview/platsmp.c                   |    8 +-
 arch/arm/mach-realview/realview_eb.c               |    6 +-
 arch/arm/mach-realview/realview_pb1176.c           |    6 +-
 arch/arm/mach-realview/realview_pb11mp.c           |    6 +-
 arch/arm/mach-realview/realview_pba8.c             |    6 +-
 arch/arm/mach-realview/realview_pbx.c              |    6 +-
 arch/arm/mach-rpc/dma.c                            |    2 +-
 arch/arm/mach-rpc/ecard.c                          |    2 +-
 arch/arm/mach-rpc/fiq.S                            |    4 +-
 .../mach-rpc/include/{mach => mach-rpc}/acornfb.h  |    0
 .../include/{mach => mach-rpc}/debug-macro.S       |    0
 arch/arm/mach-rpc/include/mach-rpc/entry-macro.S   |   12 +
 arch/arm/mach-rpc/include/mach-rpc/hardware.h      |   76 +
 arch/arm/mach-rpc/include/mach-rpc/io.h            |   31 +
 .../arm/mach-rpc/include/{mach => mach-rpc}/irqs.h |    0
 .../mach-rpc/include/{mach => mach-rpc}/isa-dma.h  |    0
 .../mach-rpc/include/{mach => mach-rpc}/memory.h   |    0
 .../mach-rpc/include/{mach => mach-rpc}/timex.h    |    0
 arch/arm/mach-rpc/include/mach-rpc/uncompress.h    |  196 +++
 arch/arm/mach-rpc/include/mach/entry-macro.S       |   12 -
 arch/arm/mach-rpc/include/mach/hardware.h          |   76 -
 arch/arm/mach-rpc/include/mach/io.h                |   31 -
 arch/arm/mach-rpc/include/mach/uncompress.h        |  196 ---
 arch/arm/mach-rpc/riscpc.c                         |    2 +-
 arch/arm/mach-rpc/time.c                           |    2 +-
 arch/arm/mach-s3c2410/cpu-freq.c                   |    8 +-
 arch/arm/mach-s3c2410/pll.c                        |    4 +-
 arch/arm/mach-s3c2412/cpu-freq.c                   |   10 +-
 arch/arm/mach-s3c2412/gpio.c                       |    6 +-
 arch/arm/mach-s3c2440/dsc.c                        |   10 +-
 arch/arm/mach-s3c2440/s3c2440-cpufreq.c            |   10 +-
 arch/arm/mach-s3c2440/s3c2440-pll-12000000.c       |    4 +-
 arch/arm/mach-s3c2440/s3c2440-pll-16934400.c       |    4 +-
 arch/arm/mach-s3c24xx/bast-ide.c                   |    6 +-
 arch/arm/mach-s3c24xx/bast-irq.c                   |   10 +-
 arch/arm/mach-s3c24xx/clock-s3c2412.c              |   14 +-
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |   16 +-
 arch/arm/mach-s3c24xx/clock-s3c2440.c              |   10 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |   14 +-
 arch/arm/mach-s3c24xx/clock-s3c244x.c              |    8 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c             |   10 +-
 arch/arm/mach-s3c24xx/common-smdk.c                |   16 +-
 arch/arm/mach-s3c24xx/common.c                     |   30 +-
 arch/arm/mach-s3c24xx/dma-s3c2410.c                |   30 +-
 arch/arm/mach-s3c24xx/dma-s3c2412.c                |   28 +-
 arch/arm/mach-s3c24xx/dma-s3c2440.c                |   26 +-
 arch/arm/mach-s3c24xx/dma-s3c2443.c                |   24 +-
 arch/arm/mach-s3c24xx/h1940-bluetooth.c            |    8 +-
 .../include/{mach => mach-s3c24xx}/anubis-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/anubis-irq.h    |    0
 .../include/{mach => mach-s3c24xx}/anubis-map.h    |    0
 .../include/{mach => mach-s3c24xx}/bast-cpld.h     |    0
 .../include/{mach => mach-s3c24xx}/bast-irq.h      |    0
 .../include/{mach => mach-s3c24xx}/bast-map.h      |    0
 .../include/mach-s3c24xx/debug-macro.S             |  101 ++
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/dma.h   |  214 +++
 .../include/mach-s3c24xx/entry-macro.S             |   70 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/fb.h    |    1 +
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-fns.h   |    1 +
 .../include/{mach => mach-s3c24xx}/gpio-nrs.h      |    0
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-track.h |   33 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio.h  |   35 +
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gta02.h |   15 +
 .../include/{mach => mach-s3c24xx}/h1940-latch.h   |    0
 .../include/{mach => mach-s3c24xx}/h1940.h         |    0
 .../mach-s3c24xx/include/mach-s3c24xx/hardware.h   |   42 +
 .../include/{mach => mach-s3c24xx}/idle.h          |    0
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/io.h    |  211 +++
 .../include/{mach => mach-s3c24xx}/irqs.h          |    0
 .../include/{mach => mach-s3c24xx}/leds-gpio.h     |    0
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/map.h   |  170 ++
 .../include/{mach => mach-s3c24xx}/osiris-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/osiris-map.h    |    0
 .../include/{mach => mach-s3c24xx}/otom-map.h      |    0
 .../include/{mach => mach-s3c24xx}/pm-core.h       |    0
 .../include/{mach => mach-s3c24xx}/regs-clock.h    |    0
 .../include/{mach => mach-s3c24xx}/regs-dsc.h      |    0
 .../mach-s3c24xx/include/mach-s3c24xx/regs-gpio.h  |  615 +++++++
 .../include/{mach => mach-s3c24xx}/regs-irq.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-lcd.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-power.h    |    0
 .../{mach => mach-s3c24xx}/regs-s3c2412-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-s3c2412.h  |    0
 .../{mach => mach-s3c24xx}/regs-s3c2416-mem.h      |    0
 .../include/{mach => mach-s3c24xx}/regs-s3c2416.h  |    0
 .../{mach => mach-s3c24xx}/regs-s3c2443-clock.h    |    0
 .../include/{mach => mach-s3c24xx}/regs-sdi.h      |    0
 .../include/{mach => mach-s3c24xx}/tick.h          |    0
 .../include/{mach => mach-s3c24xx}/timex.h         |    0
 .../mach-s3c24xx/include/mach-s3c24xx/uncompress.h |   54 +
 .../include/{mach => mach-s3c24xx}/vr1000-cpld.h   |    0
 .../include/{mach => mach-s3c24xx}/vr1000-irq.h    |    0
 .../mach-s3c24xx/include/mach-s3c24xx/vr1000-map.h |  110 ++
 arch/arm/mach-s3c24xx/include/mach/debug-macro.S   |  101 --
 arch/arm/mach-s3c24xx/include/mach/dma.h           |  214 ---
 arch/arm/mach-s3c24xx/include/mach/entry-macro.S   |   70 -
 arch/arm/mach-s3c24xx/include/mach/fb.h            |    1 -
 arch/arm/mach-s3c24xx/include/mach/gpio-fns.h      |    1 -
 arch/arm/mach-s3c24xx/include/mach/gpio-track.h    |   33 -
 arch/arm/mach-s3c24xx/include/mach/gpio.h          |   35 -
 arch/arm/mach-s3c24xx/include/mach/gta02.h         |   15 -
 arch/arm/mach-s3c24xx/include/mach/hardware.h      |   42 -
 arch/arm/mach-s3c24xx/include/mach/io.h            |  211 ---
 arch/arm/mach-s3c24xx/include/mach/map.h           |  170 --
 arch/arm/mach-s3c24xx/include/mach/regs-gpio.h     |  615 -------
 arch/arm/mach-s3c24xx/include/mach/uncompress.h    |   54 -
 arch/arm/mach-s3c24xx/include/mach/vr1000-map.h    |  110 --
 arch/arm/mach-s3c24xx/irq-pm.c                     |    6 +-
 arch/arm/mach-s3c24xx/irq-s3c2412.c                |   14 +-
 arch/arm/mach-s3c24xx/irq-s3c2416.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c2440.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c2443.c                |   12 +-
 arch/arm/mach-s3c24xx/irq-s3c244x.c                |   12 +-
 arch/arm/mach-s3c24xx/mach-amlm5900.c              |   18 +-
 arch/arm/mach-s3c24xx/mach-anubis.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-at2440evb.c             |   24 +-
 arch/arm/mach-s3c24xx/mach-bast.c                  |   36 +-
 arch/arm/mach-s3c24xx/mach-gta02.c                 |   38 +-
 arch/arm/mach-s3c24xx/mach-h1940.c                 |   46 +-
 arch/arm/mach-s3c24xx/mach-jive.c                  |   30 +-
 arch/arm/mach-s3c24xx/mach-mini2440.c              |   32 +-
 arch/arm/mach-s3c24xx/mach-n30.c                   |   26 +-
 arch/arm/mach-s3c24xx/mach-nexcoder.c              |   22 +-
 arch/arm/mach-s3c24xx/mach-osiris-dvs.c            |    2 +-
 arch/arm/mach-s3c24xx/mach-osiris.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-otom.c                  |   18 +-
 arch/arm/mach-s3c24xx/mach-qt2410.c                |   28 +-
 arch/arm/mach-s3c24xx/mach-rx1950.c                |   34 +-
 arch/arm/mach-s3c24xx/mach-rx3715.c                |   22 +-
 arch/arm/mach-s3c24xx/mach-smdk2410.c              |   12 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c              |   34 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |   42 +-
 arch/arm/mach-s3c24xx/mach-smdk2440.c              |   26 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |   26 +-
 arch/arm/mach-s3c24xx/mach-tct_hammer.c            |   10 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c                |   26 +-
 arch/arm/mach-s3c24xx/mach-vstms.c                 |   26 +-
 arch/arm/mach-s3c24xx/pm-h1940.S                   |    6 +-
 arch/arm/mach-s3c24xx/pm-s3c2410.c                 |   10 +-
 arch/arm/mach-s3c24xx/pm-s3c2412.c                 |   14 +-
 arch/arm/mach-s3c24xx/pm-s3c2416.c                 |    8 +-
 arch/arm/mach-s3c24xx/pm.c                         |   14 +-
 arch/arm/mach-s3c24xx/s3c2410.c                    |   28 +-
 arch/arm/mach-s3c24xx/s3c2412.c                    |   36 +-
 arch/arm/mach-s3c24xx/s3c2416.c                    |   34 +-
 arch/arm/mach-s3c24xx/s3c2440.c                    |   16 +-
 arch/arm/mach-s3c24xx/s3c2442.c                    |   18 +-
 arch/arm/mach-s3c24xx/s3c2443.c                    |   26 +-
 arch/arm/mach-s3c24xx/s3c244x.c                    |   34 +-
 arch/arm/mach-s3c24xx/setup-i2c.c                  |    8 +-
 arch/arm/mach-s3c24xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                  |    6 +-
 arch/arm/mach-s3c24xx/setup-ts.c                   |    2 +-
 arch/arm/mach-s3c24xx/simtec-audio.c               |   14 +-
 arch/arm/mach-s3c24xx/simtec-nor.c                 |    6 +-
 arch/arm/mach-s3c24xx/simtec-pm.c                  |   10 +-
 arch/arm/mach-s3c24xx/simtec-usb.c                 |   10 +-
 arch/arm/mach-s3c24xx/sleep-s3c2410.S              |   12 +-
 arch/arm/mach-s3c24xx/sleep-s3c2412.S              |    6 +-
 arch/arm/mach-s3c24xx/sleep.S                      |   12 +-
 arch/arm/mach-s3c64xx/clock.c                      |   24 +-
 arch/arm/mach-s3c64xx/common.c                     |   28 +-
 arch/arm/mach-s3c64xx/cpuidle.c                    |    6 +-
 arch/arm/mach-s3c64xx/dev-audio.c                  |   12 +-
 arch/arm/mach-s3c64xx/dev-uart.c                   |    6 +-
 arch/arm/mach-s3c64xx/dma.c                        |    8 +-
 .../include/{mach => mach-s3c64xx}/crag6410.h      |    0
 .../include/mach-s3c64xx/debug-macro.S             |   38 +
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/dma.h   |  132 ++
 .../include/{mach => mach-s3c64xx}/gpio.h          |    0
 .../include/{mach => mach-s3c64xx}/hardware.h      |    0
 .../include/{mach => mach-s3c64xx}/irqs.h          |    0
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/map.h   |  125 ++
 .../mach-s3c64xx/include/mach-s3c64xx/pm-core.h    |  119 ++
 .../include/{mach => mach-s3c64xx}/regs-clock.h    |    0
 .../{mach => mach-s3c64xx}/regs-gpio-memport.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-gpio.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-irq.h      |    0
 .../include/{mach => mach-s3c64xx}/regs-modem.h    |    0
 .../include/{mach => mach-s3c64xx}/regs-srom.h     |    0
 .../include/{mach => mach-s3c64xx}/regs-sys.h      |    0
 .../{mach => mach-s3c64xx}/regs-syscon-power.h     |    0
 .../include/{mach => mach-s3c64xx}/tick.h          |    0
 .../include/{mach => mach-s3c64xx}/timex.h         |    0
 .../mach-s3c64xx/include/mach-s3c64xx/uncompress.h |   28 +
 arch/arm/mach-s3c64xx/include/mach/debug-macro.S   |   38 -
 arch/arm/mach-s3c64xx/include/mach/dma.h           |  132 --
 arch/arm/mach-s3c64xx/include/mach/map.h           |  125 --
 arch/arm/mach-s3c64xx/include/mach/pm-core.h       |  119 --
 arch/arm/mach-s3c64xx/include/mach/uncompress.h    |   28 -
 arch/arm/mach-s3c64xx/irq-pm.c                     |   12 +-
 arch/arm/mach-s3c64xx/mach-anw6410.c               |   22 +-
 arch/arm/mach-s3c64xx/mach-crag6410-module.c       |    4 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |   48 +-
 arch/arm/mach-s3c64xx/mach-hmt.c                   |   20 +-
 arch/arm/mach-s3c64xx/mach-mini6410.c              |   26 +-
 arch/arm/mach-s3c64xx/mach-ncp.c                   |   18 +-
 arch/arm/mach-s3c64xx/mach-real6410.c              |   26 +-
 arch/arm/mach-s3c64xx/mach-smartq.c                |   28 +-
 arch/arm/mach-s3c64xx/mach-smartq5.c               |   16 +-
 arch/arm/mach-s3c64xx/mach-smartq7.c               |   16 +-
 arch/arm/mach-s3c64xx/mach-smdk6400.c              |   14 +-
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |   40 +-
 arch/arm/mach-s3c64xx/pm.c                         |   26 +-
 arch/arm/mach-s3c64xx/s3c6400.c                    |   20 +-
 arch/arm/mach-s3c64xx/s3c6410.c                    |   26 +-
 arch/arm/mach-s3c64xx/setup-fb-24bpp.c             |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-ide.c                  |    8 +-
 arch/arm/mach-s3c64xx/setup-keypad.c               |    4 +-
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c64xx/setup-spi.c                  |    2 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   10 +-
 arch/arm/mach-s3c64xx/sleep.S                      |    4 +-
 arch/arm/mach-s5p64x0/clock-s5p6440.c              |   22 +-
 arch/arm/mach-s5p64x0/clock-s5p6450.c              |   22 +-
 arch/arm/mach-s5p64x0/clock.c                      |   20 +-
 arch/arm/mach-s5p64x0/common.c                     |   32 +-
 arch/arm/mach-s5p64x0/dev-audio.c                  |   10 +-
 arch/arm/mach-s5p64x0/dma.c                        |   14 +-
 arch/arm/mach-s5p64x0/gpiolib.c                    |   16 +-
 .../include/mach-s5p64x0/debug-macro.S             |   33 +
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/dma.h   |   26 +
 .../include/{mach => mach-s5p64x0}/gpio.h          |    0
 .../include/{mach => mach-s5p64x0}/hardware.h      |    0
 .../include/{mach => mach-s5p64x0}/i2c.h           |    0
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/irqs.h  |  150 ++
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/map.h   |   95 ++
 .../mach-s5p64x0/include/mach-s5p64x0/pm-core.h    |  117 ++
 .../mach-s5p64x0/include/mach-s5p64x0/regs-clock.h |   98 ++
 .../mach-s5p64x0/include/mach-s5p64x0/regs-gpio.h  |   68 +
 .../mach-s5p64x0/include/mach-s5p64x0/regs-irq.h   |   19 +
 .../include/{mach => mach-s5p64x0}/s5p64x0-clock.h |    0
 .../include/{mach => mach-s5p64x0}/tick.h          |    0
 .../include/{mach => mach-s5p64x0}/timex.h         |    0
 .../mach-s5p64x0/include/mach-s5p64x0/uncompress.h |  212 +++
 arch/arm/mach-s5p64x0/include/mach/debug-macro.S   |   33 -
 arch/arm/mach-s5p64x0/include/mach/dma.h           |   26 -
 arch/arm/mach-s5p64x0/include/mach/irqs.h          |  150 --
 arch/arm/mach-s5p64x0/include/mach/map.h           |   95 --
 arch/arm/mach-s5p64x0/include/mach/pm-core.h       |  117 --
 arch/arm/mach-s5p64x0/include/mach/regs-clock.h    |   98 --
 arch/arm/mach-s5p64x0/include/mach/regs-gpio.h     |   68 -
 arch/arm/mach-s5p64x0/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5p64x0/include/mach/uncompress.h    |  212 ---
 arch/arm/mach-s5p64x0/irq-pm.c                     |    6 +-
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |   40 +-
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |   40 +-
 arch/arm/mach-s5p64x0/pm.c                         |   12 +-
 arch/arm/mach-s5p64x0/setup-fb-24bpp.c             |    6 +-
 arch/arm/mach-s5p64x0/setup-i2c0.c                 |    6 +-
 arch/arm/mach-s5p64x0/setup-i2c1.c                 |    6 +-
 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c           |   10 +-
 arch/arm/mach-s5p64x0/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pc100/clock.c                      |   18 +-
 arch/arm/mach-s5pc100/common.c                     |   30 +-
 arch/arm/mach-s5pc100/dev-audio.c                  |   10 +-
 arch/arm/mach-s5pc100/dma.c                        |   10 +-
 .../include/mach-s5pc100/debug-macro.S             |   39 +
 arch/arm/mach-s5pc100/include/mach-s5pc100/dma.h   |   26 +
 .../include/{mach => mach-s5pc100}/entry-macro.S   |    0
 .../include/{mach => mach-s5pc100}/gpio.h          |    0
 .../include/{mach => mach-s5pc100}/hardware.h      |    0
 arch/arm/mach-s5pc100/include/mach-s5pc100/irqs.h  |  117 ++
 arch/arm/mach-s5pc100/include/mach-s5pc100/map.h   |  136 ++
 .../mach-s5pc100/include/mach-s5pc100/regs-clock.h |   80 +
 .../mach-s5pc100/include/mach-s5pc100/regs-gpio.h  |   38 +
 .../mach-s5pc100/include/mach-s5pc100/regs-irq.h   |   19 +
 .../include/{mach => mach-s5pc100}/tick.h          |    0
 .../include/{mach => mach-s5pc100}/timex.h         |    0
 .../mach-s5pc100/include/mach-s5pc100/uncompress.h |   28 +
 arch/arm/mach-s5pc100/include/mach/debug-macro.S   |   39 -
 arch/arm/mach-s5pc100/include/mach/dma.h           |   26 -
 arch/arm/mach-s5pc100/include/mach/irqs.h          |  117 --
 arch/arm/mach-s5pc100/include/mach/map.h           |  136 --
 arch/arm/mach-s5pc100/include/mach/regs-clock.h    |   80 -
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h     |   38 -
 arch/arm/mach-s5pc100/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5pc100/include/mach/uncompress.h    |   28 -
 arch/arm/mach-s5pc100/mach-smdkc100.c              |   34 +-
 arch/arm/mach-s5pc100/setup-fb-24bpp.c             |    6 +-
 arch/arm/mach-s5pc100/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-ide.c                  |    4 +-
 arch/arm/mach-s5pc100/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c           |    6 +-
 arch/arm/mach-s5pc100/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/clock.c                      |   18 +-
 arch/arm/mach-s5pv210/common.c                     |   30 +-
 arch/arm/mach-s5pv210/dev-audio.c                  |   12 +-
 arch/arm/mach-s5pv210/dma.c                        |   10 +-
 .../include/mach-s5pv210/debug-macro.S             |   41 +
 arch/arm/mach-s5pv210/include/mach-s5pv210/dma.h   |   26 +
 .../include/{mach => mach-s5pv210}/gpio.h          |    0
 .../include/{mach => mach-s5pv210}/hardware.h      |    0
 arch/arm/mach-s5pv210/include/mach-s5pv210/irqs.h  |  139 ++
 arch/arm/mach-s5pv210/include/mach-s5pv210/map.h   |  157 ++
 .../include/{mach => mach-s5pv210}/memory.h        |    0
 .../include/{mach => mach-s5pv210}/pm-core.h       |    0
 .../include/{mach => mach-s5pv210}/regs-audss.h    |    0
 .../mach-s5pv210/include/mach-s5pv210/regs-clock.h |  206 +++
 .../mach-s5pv210/include/mach-s5pv210/regs-gpio.h  |   41 +
 .../mach-s5pv210/include/mach-s5pv210/regs-irq.h   |   19 +
 .../include/{mach => mach-s5pv210}/regs-sys.h      |    0
 .../include/{mach => mach-s5pv210}/tick.h          |    0
 .../include/{mach => mach-s5pv210}/timex.h         |    0
 .../mach-s5pv210/include/mach-s5pv210/uncompress.h |   24 +
 arch/arm/mach-s5pv210/include/mach/debug-macro.S   |   41 -
 arch/arm/mach-s5pv210/include/mach/dma.h           |   26 -
 arch/arm/mach-s5pv210/include/mach/irqs.h          |  139 --
 arch/arm/mach-s5pv210/include/mach/map.h           |  157 --
 arch/arm/mach-s5pv210/include/mach/regs-clock.h    |  206 ---
 arch/arm/mach-s5pv210/include/mach/regs-gpio.h     |   41 -
 arch/arm/mach-s5pv210/include/mach/regs-irq.h      |   19 -
 arch/arm/mach-s5pv210/include/mach/uncompress.h    |   24 -
 arch/arm/mach-s5pv210/mach-aquila.c                |   24 +-
 arch/arm/mach-s5pv210/mach-goni.c                  |   32 +-
 arch/arm/mach-s5pv210/mach-smdkc110.c              |   22 +-
 arch/arm/mach-s5pv210/mach-smdkv210.c              |   40 +-
 arch/arm/mach-s5pv210/mach-torbreck.c              |   16 +-
 arch/arm/mach-s5pv210/pm.c                         |   10 +-
 arch/arm/mach-s5pv210/setup-fb-24bpp.c             |    8 +-
 arch/arm/mach-s5pv210/setup-fimc.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c2.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-ide.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c           |    6 +-
 arch/arm/mach-s5pv210/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-usb-phy.c              |   10 +-
 arch/arm/mach-sa1100/assabet.c                     |    8 +-
 arch/arm/mach-sa1100/badge4.c                      |    6 +-
 arch/arm/mach-sa1100/cerf.c                        |    8 +-
 arch/arm/mach-sa1100/clock.c                       |    2 +-
 arch/arm/mach-sa1100/collie.c                      |    8 +-
 arch/arm/mach-sa1100/cpu-sa1100.c                  |    2 +-
 arch/arm/mach-sa1100/cpu-sa1110.c                  |    2 +-
 arch/arm/mach-sa1100/generic.c                     |    4 +-
 arch/arm/mach-sa1100/h3100.c                       |    4 +-
 arch/arm/mach-sa1100/h3600.c                       |    4 +-
 arch/arm/mach-sa1100/h3xxx.c                       |    2 +-
 arch/arm/mach-sa1100/hackkit.c                     |    4 +-
 .../include/{mach => mach-sa1100}/SA-1100.h        |    0
 arch/arm/mach-sa1100/include/mach-sa1100/SA-1101.h |  925 +++++++++++
 .../include/{mach => mach-sa1100}/SA-1111.h        |    0
 .../include/{mach => mach-sa1100}/assabet.h        |    0
 arch/arm/mach-sa1100/include/mach-sa1100/badge4.h  |   75 +
 .../include/{mach => mach-sa1100}/bitfield.h       |    0
 .../include/{mach => mach-sa1100}/cerf.h           |    0
 .../include/{mach => mach-sa1100}/collie.h         |    0
 .../mach-sa1100/include/mach-sa1100/debug-macro.S  |   62 +
 .../include/{mach => mach-sa1100}/entry-macro.S    |    0
 arch/arm/mach-sa1100/include/mach-sa1100/gpio.h    |   55 +
 .../include/{mach => mach-sa1100}/h3xxx.h          |    0
 .../include/{mach => mach-sa1100}/hardware.h       |    0
 .../include/{mach => mach-sa1100}/irqs.h           |    0
 .../include/{mach => mach-sa1100}/jornada720.h     |    0
 .../include/{mach => mach-sa1100}/lart.h           |    0
 .../include/{mach => mach-sa1100}/mcp.h            |    0
 .../include/{mach => mach-sa1100}/memory.h         |    0
 arch/arm/mach-sa1100/include/mach-sa1100/mtd-xip.h |   26 +
 .../mach-sa1100/include/mach-sa1100/nanoengine.h   |   52 +
 .../include/{mach => mach-sa1100}/neponset.h       |    0
 .../include/{mach => mach-sa1100}/reset.h          |    0
 .../include/{mach => mach-sa1100}/shannon.h        |    0
 .../include/{mach => mach-sa1100}/simpad.h         |    0
 .../include/{mach => mach-sa1100}/timex.h          |    0
 .../include/{mach => mach-sa1100}/uncompress.h     |    0
 arch/arm/mach-sa1100/include/mach/SA-1101.h        |  925 -----------
 arch/arm/mach-sa1100/include/mach/badge4.h         |   75 -
 arch/arm/mach-sa1100/include/mach/debug-macro.S    |   62 -
 arch/arm/mach-sa1100/include/mach/gpio.h           |   55 -
 arch/arm/mach-sa1100/include/mach/mtd-xip.h        |   26 -
 arch/arm/mach-sa1100/include/mach/nanoengine.h     |   52 -
 arch/arm/mach-sa1100/irq.c                         |    4 +-
 arch/arm/mach-sa1100/jornada720.c                  |    4 +-
 arch/arm/mach-sa1100/jornada720_ssp.c              |    4 +-
 arch/arm/mach-sa1100/lart.c                        |    6 +-
 arch/arm/mach-sa1100/leds-assabet.c                |    4 +-
 arch/arm/mach-sa1100/leds-badge4.c                 |    2 +-
 arch/arm/mach-sa1100/leds-cerf.c                   |    2 +-
 arch/arm/mach-sa1100/leds-hackkit.c                |    2 +-
 arch/arm/mach-sa1100/leds-lart.c                   |    2 +-
 arch/arm/mach-sa1100/nanoengine.c                  |    6 +-
 arch/arm/mach-sa1100/neponset.c                    |    8 +-
 arch/arm/mach-sa1100/pci-nanoengine.c              |    4 +-
 arch/arm/mach-sa1100/pleb.c                        |    4 +-
 arch/arm/mach-sa1100/pm.c                          |    2 +-
 arch/arm/mach-sa1100/shannon.c                     |    8 +-
 arch/arm/mach-sa1100/simpad.c                      |    8 +-
 arch/arm/mach-sa1100/sleep.S                       |    2 +-
 arch/arm/mach-sa1100/ssp.c                         |    4 +-
 arch/arm/mach-sa1100/time.c                        |    4 +-
 .../include/{mach => mach-shark}/debug-macro.S     |    0
 .../include/{mach => mach-shark}/entry-macro.S     |    0
 .../include/{mach => mach-shark}/framebuffer.h     |    0
 .../include/{mach => mach-shark}/hardware.h        |    0
 .../mach-shark/include/{mach => mach-shark}/io.h   |    0
 .../mach-shark/include/{mach => mach-shark}/irqs.h |    0
 .../include/{mach => mach-shark}/isa-dma.h         |    0
 .../include/{mach => mach-shark}/memory.h          |    0
 .../include/{mach => mach-shark}/timex.h           |    0
 .../include/{mach => mach-shark}/uncompress.h      |    0
 arch/arm/mach-shmobile/board-ag5evm.c              |    8 +-
 arch/arm/mach-shmobile/board-ap4evb.c              |    6 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c     |    6 +-
 arch/arm/mach-shmobile/board-bonito.c              |    6 +-
 arch/arm/mach-shmobile/board-g3evm.c               |    6 +-
 arch/arm/mach-shmobile/board-g4evm.c               |    6 +-
 arch/arm/mach-shmobile/board-kota2.c               |    8 +-
 arch/arm/mach-shmobile/board-kzm9d.c               |    4 +-
 arch/arm/mach-shmobile/board-kzm9g.c               |    6 +-
 arch/arm/mach-shmobile/board-mackerel.c            |    6 +-
 arch/arm/mach-shmobile/board-marzen.c              |    8 +-
 arch/arm/mach-shmobile/clock-emev2.c               |    2 +-
 arch/arm/mach-shmobile/clock-r8a7740.c             |    4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |    2 +-
 arch/arm/mach-shmobile/clock-sh7367.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7372.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7377.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh73a0.c              |    2 +-
 arch/arm/mach-shmobile/common.c                    |    2 +-
 arch/arm/mach-shmobile/console.c                   |    2 +-
 arch/arm/mach-shmobile/hotplug.c                   |    2 +-
 .../include/{mach => mach-shmobile}/clkdev.h       |    0
 .../include/{mach => mach-shmobile}/common.h       |    0
 .../include/{mach => mach-shmobile}/dma-register.h |    0
 .../include/{mach => mach-shmobile}/dma.h          |    0
 .../include/{mach => mach-shmobile}/emev2.h        |    0
 .../include/{mach => mach-shmobile}/gpio.h         |    0
 .../include/{mach => mach-shmobile}/hardware.h     |    0
 .../{mach => mach-shmobile}/head-ap4evb.txt        |    0
 .../{mach => mach-shmobile}/head-mackerel.txt      |    0
 .../include/{mach => mach-shmobile}/intc.h         |    0
 .../include/{mach => mach-shmobile}/irqs.h         |    0
 .../include/{mach => mach-shmobile}/memory.h       |    0
 .../include/{mach => mach-shmobile}/mmc-ap4eb.h    |    0
 .../include/{mach => mach-shmobile}/mmc-mackerel.h |    0
 .../include/{mach => mach-shmobile}/mmc.h          |    0
 .../include/{mach => mach-shmobile}/pm-rmobile.h   |    0
 .../mach-shmobile/include/mach-shmobile/r8a7740.h  |  615 +++++++
 .../include/{mach => mach-shmobile}/r8a7779.h      |    0
 .../include/{mach => mach-shmobile}/sdhi-sh7372.h  |    0
 .../include/{mach => mach-shmobile}/sdhi.h         |    0
 .../include/{mach => mach-shmobile}/sh7367.h       |    0
 .../mach-shmobile/include/mach-shmobile/sh7372.h   |  498 ++++++
 .../include/{mach => mach-shmobile}/sh7377.h       |    0
 .../include/{mach => mach-shmobile}/sh73a0.h       |    0
 .../include/{mach => mach-shmobile}/system.h       |    0
 .../include/{mach => mach-shmobile}/timex.h        |    0
 .../include/{mach => mach-shmobile}/uncompress.h   |    0
 .../mach-shmobile/include/mach-shmobile/zboot.h    |   23 +
 .../include/{mach => mach-shmobile}/zboot_macros.h |    0
 arch/arm/mach-shmobile/include/mach/r8a7740.h      |  615 -------
 arch/arm/mach-shmobile/include/mach/sh7372.h       |  498 ------
 arch/arm/mach-shmobile/include/mach/zboot.h        |   23 -
 arch/arm/mach-shmobile/intc-r8a7740.c              |    4 +-
 arch/arm/mach-shmobile/intc-r8a7779.c              |    6 +-
 arch/arm/mach-shmobile/intc-sh7367.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7372.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7377.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh73a0.c               |    6 +-
 arch/arm/mach-shmobile/pfc-r8a7740.c               |    4 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c               |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c                |    4 +-
 arch/arm/mach-shmobile/pfc-sh7377.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c                |    4 +-
 arch/arm/mach-shmobile/platsmp.c                   |    4 +-
 arch/arm/mach-shmobile/pm-r8a7740.c                |    2 +-
 arch/arm/mach-shmobile/pm-r8a7779.c                |    4 +-
 arch/arm/mach-shmobile/pm-rmobile.c                |    2 +-
 arch/arm/mach-shmobile/pm-sh7372.c                 |    6 +-
 arch/arm/mach-shmobile/setup-emev2.c               |    8 +-
 arch/arm/mach-shmobile/setup-r8a7740.c             |   10 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |    8 +-
 arch/arm/mach-shmobile/setup-sh7367.c              |    6 +-
 arch/arm/mach-shmobile/setup-sh7372.c              |   10 +-
 arch/arm/mach-shmobile/setup-sh7377.c              |    6 +-
 arch/arm/mach-shmobile/setup-sh73a0.c              |   10 +-
 arch/arm/mach-shmobile/smp-emev2.c                 |    4 +-
 arch/arm/mach-shmobile/smp-r8a7779.c               |    4 +-
 arch/arm/mach-shmobile/smp-sh73a0.c                |    2 +-
 .../include/{mach => mach-socfpga}/debug-macro.S   |    0
 .../include/{mach => mach-socfpga}/timex.h         |    0
 .../include/{mach => mach-socfpga}/uncompress.h    |    0
 .../include/mach-spear13xx/debug-macro.S           |   14 +
 .../include/{mach => mach-spear13xx}/dma.h         |    0
 .../include/{mach => mach-spear13xx}/generic.h     |    0
 .../mach-spear13xx/include/mach-spear13xx/gpio.h   |   19 +
 .../include/{mach => mach-spear13xx}/hardware.h    |    0
 .../include/{mach => mach-spear13xx}/irqs.h        |    0
 .../include/{mach => mach-spear13xx}/spear.h       |    0
 .../{mach => mach-spear13xx}/spear1310_misc_regs.h |    0
 .../{mach => mach-spear13xx}/spear1340_misc_regs.h |    0
 .../mach-spear13xx/include/mach-spear13xx/timex.h  |   19 +
 .../include/mach-spear13xx/uncompress.h            |   19 +
 arch/arm/mach-spear13xx/include/mach/debug-macro.S |   14 -
 arch/arm/mach-spear13xx/include/mach/gpio.h        |   19 -
 arch/arm/mach-spear13xx/include/mach/timex.h       |   19 -
 arch/arm/mach-spear13xx/include/mach/uncompress.h  |   19 -
 arch/arm/mach-spear13xx/platsmp.c                  |    2 +-
 arch/arm/mach-spear13xx/spear1310.c                |    4 +-
 arch/arm/mach-spear13xx/spear1340.c                |    6 +-
 arch/arm/mach-spear13xx/spear13xx.c                |    6 +-
 .../include/mach-spear3xx/debug-macro.S            |   14 +
 .../include/{mach => mach-spear3xx}/generic.h      |    0
 .../arm/mach-spear3xx/include/mach-spear3xx/gpio.h |   19 +
 .../include/{mach => mach-spear3xx}/hardware.h     |    0
 .../include/{mach => mach-spear3xx}/irqs.h         |    0
 .../include/mach-spear3xx/misc_regs.h              |   22 +
 .../include/{mach => mach-spear3xx}/spear.h        |    0
 .../mach-spear3xx/include/mach-spear3xx/timex.h    |   19 +
 .../include/mach-spear3xx/uncompress.h             |   19 +
 arch/arm/mach-spear3xx/include/mach/debug-macro.S  |   14 -
 arch/arm/mach-spear3xx/include/mach/gpio.h         |   19 -
 arch/arm/mach-spear3xx/include/mach/misc_regs.h    |   22 -
 arch/arm/mach-spear3xx/include/mach/timex.h        |   19 -
 arch/arm/mach-spear3xx/include/mach/uncompress.h   |   19 -
 arch/arm/mach-spear3xx/spear300.c                  |    6 +-
 arch/arm/mach-spear3xx/spear310.c                  |    6 +-
 arch/arm/mach-spear3xx/spear320.c                  |    6 +-
 arch/arm/mach-spear3xx/spear3xx.c                  |    6 +-
 .../include/mach-spear6xx/debug-macro.S            |   14 +
 .../include/{mach => mach-spear6xx}/generic.h      |    0
 .../arm/mach-spear6xx/include/mach-spear6xx/gpio.h |   19 +
 .../include/{mach => mach-spear6xx}/hardware.h     |    0
 .../include/{mach => mach-spear6xx}/irqs.h         |    0
 .../include/mach-spear6xx/misc_regs.h              |   22 +
 .../include/{mach => mach-spear6xx}/spear.h        |    0
 .../mach-spear6xx/include/mach-spear6xx/timex.h    |   19 +
 .../include/mach-spear6xx/uncompress.h             |   19 +
 arch/arm/mach-spear6xx/include/mach/debug-macro.S  |   14 -
 arch/arm/mach-spear6xx/include/mach/gpio.h         |   19 -
 arch/arm/mach-spear6xx/include/mach/misc_regs.h    |   22 -
 arch/arm/mach-spear6xx/include/mach/timex.h        |   19 -
 arch/arm/mach-spear6xx/include/mach/uncompress.h   |   19 -
 arch/arm/mach-spear6xx/spear6xx.c                  |    6 +-
 arch/arm/mach-tegra/apbio.c                        |    4 +-
 arch/arm/mach-tegra/board-dt-tegra20.c             |    4 +-
 arch/arm/mach-tegra/board-dt-tegra30.c             |    2 +-
 arch/arm/mach-tegra/board-harmony-power.c          |    2 +-
 arch/arm/mach-tegra/board-harmony.c                |    8 +-
 arch/arm/mach-tegra/board-harmony.h                |    2 +-
 arch/arm/mach-tegra/board-paz00.c                  |    6 +-
 arch/arm/mach-tegra/board-paz00.h                  |    2 +-
 arch/arm/mach-tegra/board-pinmux.h                 |    2 +-
 arch/arm/mach-tegra/board-trimslice.c              |    4 +-
 arch/arm/mach-tegra/board-trimslice.h              |    2 +-
 arch/arm/mach-tegra/clock.c                        |    2 +-
 arch/arm/mach-tegra/clock.h                        |    2 +-
 arch/arm/mach-tegra/common.c                       |    4 +-
 arch/arm/mach-tegra/cpu-tegra.c                    |    2 +-
 arch/arm/mach-tegra/cpuidle.c                      |    2 +-
 arch/arm/mach-tegra/devices.c                      |    8 +-
 arch/arm/mach-tegra/devices.h                      |    2 +-
 arch/arm/mach-tegra/dma.c                          |    8 +-
 arch/arm/mach-tegra/flowctrl.c                     |    2 +-
 arch/arm/mach-tegra/fuse.c                         |    2 +-
 arch/arm/mach-tegra/headsmp.S                      |    2 +-
 .../mach-tegra/include/{mach => mach-tegra}/clk.h  |    0
 .../mach-tegra/include/mach-tegra/debug-macro.S    |  100 ++
 .../mach-tegra/include/{mach => mach-tegra}/dma.h  |    0
 .../arm/mach-tegra/include/mach-tegra/gpio-tegra.h |   28 +
 .../mach => mach-tegra/include/mach-tegra}/gpio.h  |    0
 .../mach-tegra/include/{mach => mach-tegra}/io.h   |    0
 .../include/{mach => mach-tegra}/iomap.h           |    0
 .../include/{mach => mach-tegra}/irammap.h         |    0
 .../mach-tegra/include/{mach => mach-tegra}/irqs.h |    0
 .../mach-tegra/include/{mach => mach-tegra}/kbc.h  |    0
 .../include/{mach => mach-tegra}/pinconf-tegra.h   |    0
 .../include/{mach => mach-tegra}/powergate.h       |    0
 .../include/{mach => mach-tegra}/sdhci.h           |    0
 .../mach-tegra/include/{mach => mach-tegra}/smmu.h |    0
 .../include/{mach => mach-tegra}/suspend.h         |    0
 .../include/{mach => mach-tegra}/tegra-ahb.h       |    0
 .../{mach => mach-tegra}/tegra_wm8903_pdata.h      |    0
 .../include/{mach => mach-tegra}/timex.h           |    0
 .../arm/mach-tegra/include/mach-tegra/uncompress.h |  236 +++
 .../include/{mach => mach-tegra}/usb_phy.h         |    0
 arch/arm/mach-tegra/include/mach/debug-macro.S     |  100 --
 arch/arm/mach-tegra/include/mach/gpio-tegra.h      |   28 -
 arch/arm/mach-tegra/include/mach/uncompress.h      |  236 ---
 arch/arm/mach-tegra/io.c                           |    2 +-
 arch/arm/mach-tegra/irq.c                          |    2 +-
 arch/arm/mach-tegra/pcie.c                         |    6 +-
 arch/arm/mach-tegra/platsmp.c                      |    6 +-
 arch/arm/mach-tegra/pmc.c                          |    2 +-
 arch/arm/mach-tegra/powergate.c                    |    6 +-
 arch/arm/mach-tegra/reset.c                        |    4 +-
 arch/arm/mach-tegra/sleep.S                        |    2 +-
 arch/arm/mach-tegra/tegra2_clocks.c                |    4 +-
 arch/arm/mach-tegra/tegra2_emc.c                   |    2 +-
 arch/arm/mach-tegra/tegra30_clocks.c               |    2 +-
 arch/arm/mach-tegra/timer.c                        |    6 +-
 arch/arm/mach-tegra/usb_phy.c                      |    6 +-
 arch/arm/mach-u300/core.c                          |   10 +-
 arch/arm/mach-u300/i2c.c                           |    2 +-
 .../mach-u300/include/{mach => mach-u300}/clkdev.h |    0
 .../include/{mach => mach-u300}/coh901318.h        |    0
 arch/arm/mach-u300/include/mach-u300/debug-macro.S |   21 +
 .../include/{mach => mach-u300}/dma_channels.h     |    0
 .../include/{mach => mach-u300}/gpio-u300.h        |    0
 .../mach => mach-u300/include/mach-u300}/gpio.h    |    0
 arch/arm/mach-u300/include/mach-u300/hardware.h    |    5 +
 .../mach-u300/include/{mach => mach-u300}/irqs.h   |    0
 .../include/{mach => mach-u300}/platform.h         |    0
 .../mach-u300/include/{mach => mach-u300}/syscon.h |    0
 .../mach-u300/include/{mach => mach-u300}/timex.h  |    0
 .../include/{mach => mach-u300}/u300-regs.h        |    0
 .../include/{mach => mach-u300}/uncompress.h       |    0
 arch/arm/mach-u300/include/mach/debug-macro.S      |   21 -
 arch/arm/mach-u300/include/mach/hardware.h         |    5 -
 arch/arm/mach-u300/regulator.c                     |    4 +-
 arch/arm/mach-u300/spi.c                           |    4 +-
 arch/arm/mach-u300/timer.c                         |    2 +-
 arch/arm/mach-u300/u300.c                          |    4 +-
 arch/arm/mach-ux500/board-mop500-msp.c             |   16 +-
 arch/arm/mach-ux500/board-mop500-pins.c            |    6 +-
 arch/arm/mach-ux500/board-mop500-sdi.c             |    6 +-
 arch/arm/mach-ux500/board-mop500-u8500uib.c        |    2 +-
 arch/arm/mach-ux500/board-mop500-uib.c             |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |   16 +-
 arch/arm/mach-ux500/board-mop500.h                 |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c                   |    4 +-
 arch/arm/mach-ux500/clock.c                        |    4 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |   12 +-
 arch/arm/mach-ux500/cpu.c                          |    6 +-
 arch/arm/mach-ux500/devices-common.c               |    4 +-
 arch/arm/mach-ux500/devices-common.h               |    2 +-
 arch/arm/mach-ux500/devices-db8500.c               |    6 +-
 arch/arm/mach-ux500/devices.c                      |    4 +-
 arch/arm/mach-ux500/id.c                           |    4 +-
 .../mach-ux500/include/mach-ux500/crypto-ux500.h   |   22 +
 .../include/{mach => mach-ux500}/db8500-regs.h     |    0
 .../mach-ux500/include/mach-ux500/debug-macro.S    |   39 +
 .../include/{mach => mach-ux500}/devices.h         |    0
 .../mach-ux500/include/{mach => mach-ux500}/gpio.h |    0
 arch/arm/mach-ux500/include/mach-ux500/hardware.h  |   48 +
 .../mach-ux500/include/{mach => mach-ux500}/id.h   |    0
 .../{mach => mach-ux500}/irqs-board-mop500.h       |    0
 .../include/{mach => mach-ux500}/irqs-db8500.h     |    0
 arch/arm/mach-ux500/include/mach-ux500/irqs.h      |   51 +
 arch/arm/mach-ux500/include/mach-ux500/msp.h       |   29 +
 .../include/{mach => mach-ux500}/setup.h           |    0
 .../include/{mach => mach-ux500}/timex.h           |    0
 .../arm/mach-ux500/include/mach-ux500/uncompress.h |   59 +
 .../mach-ux500/include/{mach => mach-ux500}/usb.h  |    0
 arch/arm/mach-ux500/include/mach/crypto-ux500.h    |   22 -
 arch/arm/mach-ux500/include/mach/debug-macro.S     |   39 -
 arch/arm/mach-ux500/include/mach/hardware.h        |   48 -
 arch/arm/mach-ux500/include/mach/irqs.h            |   51 -
 arch/arm/mach-ux500/include/mach/msp.h             |   29 -
 arch/arm/mach-ux500/include/mach/uncompress.h      |   59 -
 arch/arm/mach-ux500/platsmp.c                      |    4 +-
 arch/arm/mach-ux500/timer.c                        |    8 +-
 arch/arm/mach-ux500/usb.c                          |    6 +-
 arch/arm/mach-versatile/core.c                     |   10 +-
 .../mach-versatile/include/mach-versatile/clkdev.h |   16 +
 .../include/{mach => mach-versatile}/debug-macro.S |    0
 .../include/mach-versatile}/gpio.h                 |    0
 .../include/{mach => mach-versatile}/hardware.h    |    0
 .../include/{mach => mach-versatile}/io.h          |    0
 .../mach-versatile/include/mach-versatile/irqs.h   |  134 ++
 .../include/{mach => mach-versatile}/platform.h    |    0
 .../include/{mach => mach-versatile}/timex.h       |    0
 .../include/{mach => mach-versatile}/uncompress.h  |    0
 arch/arm/mach-versatile/include/mach/clkdev.h      |   16 -
 arch/arm/mach-versatile/include/mach/irqs.h        |  134 --
 arch/arm/mach-versatile/pci.c                      |    2 +-
 arch/arm/mach-versatile/versatile_ab.c             |    2 +-
 arch/arm/mach-versatile/versatile_pb.c             |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                  |    6 +-
 .../include/{mach => mach-vexpress}/ct-ca9x4.h     |    0
 .../include/{mach => mach-vexpress}/debug-macro.S  |    0
 .../include/mach-vexpress}/gpio.h                  |    0
 .../include/{mach => mach-vexpress}/hardware.h     |    0
 .../include/{mach => mach-vexpress}/irqs.h         |    0
 .../include/{mach => mach-vexpress}/motherboard.h  |    0
 .../include/{mach => mach-vexpress}/timex.h        |    0
 .../include/{mach => mach-vexpress}/uncompress.h   |    0
 arch/arm/mach-vexpress/platsmp.c                   |    2 +-
 arch/arm/mach-vexpress/v2m.c                       |    6 +-
 arch/arm/mach-vt8500/bv07.c                        |    2 +-
 arch/arm/mach-vt8500/devices-vt8500.c              |    6 +-
 arch/arm/mach-vt8500/devices-wm8505.c              |    6 +-
 arch/arm/mach-vt8500/devices.c                     |    4 +-
 .../include/{mach => mach-vt8500}/debug-macro.S    |    0
 .../include/{mach => mach-vt8500}/entry-macro.S    |    0
 .../include/mach-vt8500}/gpio.h                    |    0
 .../include/{mach => mach-vt8500}/hardware.h       |    0
 .../include/{mach => mach-vt8500}/i8042.h          |    0
 .../include/{mach => mach-vt8500}/irqs.h           |    0
 .../include/{mach => mach-vt8500}/restart.h        |    0
 .../include/{mach => mach-vt8500}/timex.h          |    0
 .../include/{mach => mach-vt8500}/uncompress.h     |    0
 .../include/{mach => mach-vt8500}/vt8500_irqs.h    |    0
 .../include/{mach => mach-vt8500}/vt8500_regs.h    |    0
 .../include/{mach => mach-vt8500}/vt8500fb.h       |    0
 .../include/{mach => mach-vt8500}/wm8505_irqs.h    |    0
 .../include/{mach => mach-vt8500}/wm8505_regs.h    |    0
 arch/arm/mach-vt8500/wm8505_7in.c                  |    2 +-
 arch/arm/mach-w90x900/clksel.c                     |    4 +-
 arch/arm/mach-w90x900/clock.c                      |    2 +-
 arch/arm/mach-w90x900/cpu.c                        |   10 +-
 arch/arm/mach-w90x900/dev.c                        |   12 +-
 arch/arm/mach-w90x900/gpio.c                       |    2 +-
 .../include/mach-w90x900/entry-macro.S             |   26 +
 .../include/{mach => mach-w90x900}/fb.h            |    0
 arch/arm/mach-w90x900/include/mach-w90x900/gpio.h  |   30 +
 .../mach-w90x900/include/mach-w90x900/hardware.h   |   24 +
 .../include/{mach => mach-w90x900}/i2c.h           |    0
 .../include/{mach => mach-w90x900}/irqs.h          |    0
 .../include/{mach => mach-w90x900}/map.h           |    0
 .../include/{mach => mach-w90x900}/mfp.h           |    0
 .../include/{mach => mach-w90x900}/nuc900_spi.h    |    0
 .../include/{mach => mach-w90x900}/regs-clock.h    |    0
 .../include/{mach => mach-w90x900}/regs-ebi.h      |    0
 .../include/{mach => mach-w90x900}/regs-gcr.h      |    0
 .../include/{mach => mach-w90x900}/regs-irq.h      |    0
 .../mach-w90x900/include/mach-w90x900/regs-ldm.h   |  253 +++
 .../include/{mach => mach-w90x900}/regs-serial.h   |    0
 .../include/{mach => mach-w90x900}/regs-timer.h    |    0
 .../include/{mach => mach-w90x900}/regs-usb.h      |    0
 .../include/{mach => mach-w90x900}/timex.h         |    0
 .../mach-w90x900/include/mach-w90x900/uncompress.h |   50 +
 .../{mach => mach-w90x900}/w90p910_keypad.h        |    0
 arch/arm/mach-w90x900/include/mach/entry-macro.S   |   26 -
 arch/arm/mach-w90x900/include/mach/gpio.h          |   30 -
 arch/arm/mach-w90x900/include/mach/hardware.h      |   24 -
 arch/arm/mach-w90x900/include/mach/regs-ldm.h      |  253 ---
 arch/arm/mach-w90x900/include/mach/uncompress.h    |   50 -
 arch/arm/mach-w90x900/irq.c                        |    4 +-
 arch/arm/mach-w90x900/mach-nuc910evb.c             |    2 +-
 arch/arm/mach-w90x900/mach-nuc950evb.c             |    4 +-
 arch/arm/mach-w90x900/mach-nuc960evb.c             |    2 +-
 arch/arm/mach-w90x900/mfp.c                        |    2 +-
 arch/arm/mach-w90x900/nuc910.c                     |    2 +-
 arch/arm/mach-w90x900/nuc950.c                     |    2 +-
 arch/arm/mach-w90x900/nuc960.c                     |    2 +-
 arch/arm/mach-w90x900/time.c                       |    4 +-
 arch/arm/mach-zynq/common.c                        |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/clkdev.h      |   32 +
 arch/arm/mach-zynq/include/mach-zynq/debug-macro.S |   36 +
 .../include/{mach => mach-zynq}/hardware.h         |    0
 .../mach-zynq/include/{mach => mach-zynq}/irqs.h   |    0
 .../mach-zynq/include/{mach => mach-zynq}/timex.h  |    0
 .../mach-zynq/include/{mach => mach-zynq}/uart.h   |    0
 arch/arm/mach-zynq/include/mach-zynq/uncompress.h  |   51 +
 .../include/{mach => mach-zynq}/zynq_soc.h         |    0
 arch/arm/mach-zynq/include/mach/clkdev.h           |   32 -
 arch/arm/mach-zynq/include/mach/debug-macro.S      |   36 -
 arch/arm/mach-zynq/include/mach/uncompress.h       |   51 -
 arch/arm/mach-zynq/timer.c                         |    2 +-
 arch/arm/mm/cache-feroceon-l2.c                    |    2 +-
 arch/arm/plat-mxc/3ds_debugboard.c                 |    2 +-
 arch/arm/plat-mxc/avic.c                           |    6 +-
 arch/arm/plat-mxc/clock.c                          |    4 +-
 arch/arm/plat-mxc/cpu.c                            |    2 +-
 arch/arm/plat-mxc/cpufreq.c                        |    4 +-
 arch/arm/plat-mxc/devices.c                        |    2 +-
 arch/arm/plat-mxc/devices/platform-ahci-imx.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-fec.c           |    4 +-
 arch/arm/plat-mxc/devices/platform-flexcan.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c  |    4 +-
 arch/arm/plat-mxc/devices/platform-gpio-mxc.c      |    2 +-
 arch/arm/plat-mxc/devices/platform-gpio_keys.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-dma.c       |    2 +-
 arch/arm/plat-mxc/devices/platform-imx-fb.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-i2c.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-keypad.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-ssi.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-uart.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx2-wdt.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx21-hcd.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx_udc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imxdi_rtc.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-ipu-core.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mx2-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-ehci.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-mmc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_nand.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_pwm.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rnga.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rtc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_w1.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-pata_imx.c      |    4 +-
 .../plat-mxc/devices/platform-sdhci-esdhc-imx.c    |    6 +-
 arch/arm/plat-mxc/devices/platform-spi_imx.c       |    4 +-
 arch/arm/plat-mxc/epit.c                           |    4 +-
 arch/arm/plat-mxc/include/mach/debug-macro.S       |   51 -
 arch/arm/plat-mxc/include/mach/devices-common.h    |  333 ----
 arch/arm/plat-mxc/include/mach/hardware.h          |  134 --
 arch/arm/plat-mxc/include/mach/iomux-mx1.h         |  155 --
 arch/arm/plat-mxc/include/mach/iomux-mx21.h        |  122 --
 arch/arm/plat-mxc/include/mach/iomux-mx25.h        |  524 ------
 arch/arm/plat-mxc/include/mach/iomux-mx27.h        |  205 ---
 arch/arm/plat-mxc/include/mach/iomux-mx35.h        | 1267 ---------------
 arch/arm/plat-mxc/include/mach/iomux-mx50.h        |  977 ------------
 arch/arm/plat-mxc/include/mach/iomux-mx51.h        |  827 ----------
 arch/arm/plat-mxc/include/mach/iomux-mx53.h        | 1219 --------------
 arch/arm/plat-mxc/iomux-v1.c                       |    4 +-
 arch/arm/plat-mxc/iomux-v3.c                       |    4 +-
 arch/arm/plat-mxc/iram_alloc.c                     |    2 +-
 arch/arm/plat-mxc/ssi-fiq-ksym.c                   |    2 +-
 arch/arm/plat-mxc/system.c                         |    4 +-
 arch/arm/plat-mxc/time.c                           |    4 +-
 arch/arm/plat-mxc/tzic.c                           |    6 +-
 arch/arm/plat-mxc/ulpi.c                           |    2 +-
 .../include/{plat => plat-nomadik}/gpio-nomadik.h  |    0
 .../include/{plat => plat-nomadik}/mtu.h           |    0
 .../include/{plat => plat-nomadik}/pincfg.h        |    0
 .../include/{plat => plat-nomadik}/ske.h           |    0
 .../include/{plat => plat-nomadik}/ste_dma40.h     |    0
 arch/arm/plat-omap/clock.c                         |    2 +-
 arch/arm/plat-omap/common.c                        |   12 +-
 arch/arm/plat-omap/counter_32k.c                   |    8 +-
 arch/arm/plat-omap/debug-devices.c                 |    2 +-
 arch/arm/plat-omap/debug-leds.c                    |    2 +-
 arch/arm/plat-omap/devices.c                       |   10 +-
 arch/arm/plat-omap/dma.c                           |    4 +-
 arch/arm/plat-omap/dmtimer.c                       |    4 +-
 arch/arm/plat-omap/fb.c                            |    2 +-
 arch/arm/plat-omap/i2c.c                           |    8 +-
 .../plat-omap/include/{plat => plat-omap}/am33xx.h |    0
 .../include/{plat => plat-omap}/board-ams-delta.h  |    0
 .../include/{plat => plat-omap}/board-sx1.h        |    0
 .../include/{plat => plat-omap}/board-voiceblue.h  |    0
 arch/arm/plat-omap/include/plat-omap/board.h       |  138 ++
 .../include/{plat => plat-omap}/clkdev_omap.h      |    0
 .../plat-omap/include/{plat => plat-omap}/clock.h  |    0
 arch/arm/plat-omap/include/plat-omap/common.h      |   42 +
 arch/arm/plat-omap/include/plat-omap/cpu.h         |  495 ++++++
 .../include/{plat => plat-omap}/dma-44xx.h         |    0
 arch/arm/plat-omap/include/plat-omap/dma.h         |  544 +++++++
 .../include/{plat => plat-omap}/dmtimer.h          |    0
 .../plat-omap/include/{plat => plat-omap}/dsp.h    |    0
 .../plat-omap/include/{plat => plat-omap}/flash.h  |    0
 .../plat-omap/include/{plat => plat-omap}/fpga.h   |    0
 .../include/{plat => plat-omap}/gpio-switch.h      |    0
 .../plat-omap/include/{plat => plat-omap}/gpio.h   |    0
 .../include/{plat => plat-omap}/gpmc-smc91x.h      |    0
 .../include/{plat => plat-omap}/gpmc-smsc911x.h    |    0
 .../plat-omap/include/{plat => plat-omap}/gpmc.h   |    0
 arch/arm/plat-omap/include/plat-omap/hardware.h    |  293 ++++
 arch/arm/plat-omap/include/plat-omap/hdq1w.h       |   36 +
 .../plat-omap/include/{plat => plat-omap}/i2c.h    |    0
 arch/arm/plat-omap/include/plat-omap/iommu.h       |  206 +++
 .../plat-omap/include/{plat => plat-omap}/iommu2.h |    0
 .../include/{plat => plat-omap}/iopgtable.h        |    0
 .../plat-omap/include/{plat => plat-omap}/iovmm.h  |    0
 .../plat-omap/include/{plat => plat-omap}/irda.h   |    0
 .../include/{plat => plat-omap}/irqs-44xx.h        |    0
 .../plat-omap/include/{plat => plat-omap}/irqs.h   |    0
 .../plat-omap/include/{plat => plat-omap}/keypad.h |    0
 .../include/{plat => plat-omap}/l3_2xxx.h          |    0
 .../include/{plat => plat-omap}/l3_3xxx.h          |    0
 .../include/{plat => plat-omap}/l4_2xxx.h          |    0
 .../include/{plat => plat-omap}/l4_3xxx.h          |    0
 .../include/{plat => plat-omap}/lcd_mipid.h        |    0
 .../plat-omap/include/{plat => plat-omap}/led.h    |    0
 .../include/{plat => plat-omap}/mailbox.h          |    0
 .../plat-omap/include/{plat => plat-omap}/mcbsp.h  |    0
 .../plat-omap/include/{plat => plat-omap}/mcspi.h  |    0
 .../include/{plat => plat-omap}/menelaus.h         |    0
 arch/arm/plat-omap/include/plat-omap/mmc.h         |  189 +++
 .../plat-omap/include/{plat => plat-omap}/multi.h  |    0
 .../plat-omap/include/{plat => plat-omap}/mux.h    |    0
 arch/arm/plat-omap/include/plat-omap/nand.h        |   44 +
 .../include/{plat => plat-omap}/omap-pm.h          |    0
 .../include/{plat => plat-omap}/omap-secure.h      |    0
 arch/arm/plat-omap/include/plat-omap/omap-serial.h |  140 ++
 .../include/{plat => plat-omap}/omap1510.h         |    0
 .../include/{plat => plat-omap}/omap16xx.h         |    0
 .../include/{plat => plat-omap}/omap24xx.h         |    0
 .../include/{plat => plat-omap}/omap34xx.h         |    0
 .../include/{plat => plat-omap}/omap4-keypad.h     |    0
 .../include/{plat => plat-omap}/omap44xx.h         |    0
 .../include/{plat => plat-omap}/omap54xx.h         |    0
 .../include/{plat => plat-omap}/omap7xx.h          |    0
 arch/arm/plat-omap/include/plat-omap/omap_device.h |  170 ++
 arch/arm/plat-omap/include/plat-omap/omap_hwmod.h  |  664 ++++++++
 .../include/{plat => plat-omap}/onenand.h          |    0
 .../plat-omap/include/{plat => plat-omap}/param.h  |    0
 .../plat-omap/include/{plat => plat-omap}/prcm.h   |    0
 .../include/{plat => plat-omap}/remoteproc.h       |    0
 .../plat-omap/include/{plat => plat-omap}/sdrc.h   |    0
 .../plat-omap/include/{plat => plat-omap}/serial.h |    0
 .../plat-omap/include/{plat => plat-omap}/sram.h   |    0
 .../arm/plat-omap/include/{plat => plat-omap}/tc.h |    0
 .../plat-omap/include/{plat => plat-omap}/ti81xx.h |    0
 .../plat-omap/include/{plat => plat-omap}/timex.h  |    0
 arch/arm/plat-omap/include/plat-omap/uncompress.h  |  206 +++
 arch/arm/plat-omap/include/plat-omap/usb.h         |  173 ++
 .../include/{plat => plat-omap}/voltage.h          |    0
 .../plat-omap/include/{plat => plat-omap}/vram.h   |    0
 .../plat-omap/include/{plat => plat-omap}/vrfb.h   |    0
 arch/arm/plat-omap/include/plat/board.h            |  138 --
 arch/arm/plat-omap/include/plat/common.h           |   42 -
 arch/arm/plat-omap/include/plat/cpu.h              |  495 ------
 arch/arm/plat-omap/include/plat/dma.h              |  544 -------
 arch/arm/plat-omap/include/plat/hardware.h         |  293 ----
 arch/arm/plat-omap/include/plat/hdq1w.h            |   36 -
 arch/arm/plat-omap/include/plat/iommu.h            |  206 ---
 arch/arm/plat-omap/include/plat/mmc.h              |  189 ---
 arch/arm/plat-omap/include/plat/nand.h             |   44 -
 arch/arm/plat-omap/include/plat/omap-serial.h      |  140 --
 arch/arm/plat-omap/include/plat/omap_device.h      |  170 --
 arch/arm/plat-omap/include/plat/omap_hwmod.h       |  664 --------
 arch/arm/plat-omap/include/plat/uncompress.h       |  206 ---
 arch/arm/plat-omap/include/plat/usb.h              |  173 --
 arch/arm/plat-omap/mailbox.c                       |    2 +-
 arch/arm/plat-omap/mux.c                           |    4 +-
 arch/arm/plat-omap/omap-pm-noop.c                  |    4 +-
 arch/arm/plat-omap/omap_device.c                   |    6 +-
 arch/arm/plat-omap/sram.c                          |    6 +-
 arch/arm/plat-orion/addr-map.c                     |    2 +-
 arch/arm/plat-orion/common.c                       |    4 +-
 arch/arm/plat-orion/gpio.c                         |    2 +-
 .../include/{plat => plat-orion}/addr-map.h        |    0
 .../include/{plat => plat-orion}/audio.h           |    0
 .../{plat => plat-orion}/cache-feroceon-l2.h       |    0
 .../include/{plat => plat-orion}/common.h          |    0
 .../include/{plat => plat-orion}/ehci-orion.h      |    0
 .../plat-orion/include/{plat => plat-orion}/gpio.h |    0
 .../plat-orion/include/{plat => plat-orion}/irq.h  |    0
 .../plat-orion/include/{plat => plat-orion}/mpp.h  |    0
 .../include/{plat => plat-orion}/mv_xor.h          |    0
 .../include/{plat => plat-orion}/mvsdio.h          |    0
 .../include/{plat => plat-orion}/orion_nand.h      |    0
 .../plat-orion/include/{plat => plat-orion}/pcie.h |    0
 .../plat-orion/include/{plat => plat-orion}/time.h |    0
 arch/arm/plat-orion/irq.c                          |    4 +-
 arch/arm/plat-orion/mpp.c                          |    2 +-
 arch/arm/plat-orion/pcie.c                         |    4 +-
 arch/arm/plat-pxa/include/{plat => plat-pxa}/dma.h |    0
 arch/arm/plat-pxa/include/{plat => plat-pxa}/mfp.h |    0
 .../include/{plat => plat-pxa}/pxa27x_keypad.h     |    0
 .../include/{plat => plat-pxa}/pxa3xx_nand.h       |    0
 arch/arm/plat-pxa/mfp.c                            |    2 +-
 arch/arm/plat-s3c24xx/clock-dclk.c                 |    8 +-
 arch/arm/plat-s3c24xx/cpu-freq-debugfs.c           |    2 +-
 arch/arm/plat-s3c24xx/cpu-freq.c                   |    8 +-
 arch/arm/plat-s3c24xx/dma.c                        |   10 +-
 arch/arm/plat-s3c24xx/irq.c                        |    8 +-
 arch/arm/plat-s3c24xx/s3c2410-clock.c              |   14 +-
 arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c      |    8 +-
 arch/arm/plat-s3c24xx/s3c2410-iotiming.c           |    8 +-
 arch/arm/plat-s3c24xx/s3c2412-iotiming.c           |    8 +-
 arch/arm/plat-samsung/adc.c                        |    4 +-
 arch/arm/plat-samsung/clock-clksrc.c               |    6 +-
 arch/arm/plat-samsung/clock.c                      |    8 +-
 arch/arm/plat-samsung/cpu.c                        |    2 +-
 arch/arm/plat-samsung/dev-backlight.c              |    6 +-
 arch/arm/plat-samsung/dev-uart.c                   |    2 +-
 arch/arm/plat-samsung/devs.c                       |   42 +-
 .../include/{plat => plat-samsung}/adc-core.h      |    0
 .../include/{plat => plat-samsung}/adc.h           |    0
 .../include/{plat => plat-samsung}/ata-core.h      |    0
 .../include/{plat => plat-samsung}/ata.h           |    0
 .../include/{plat => plat-samsung}/audio-simtec.h  |    0
 .../include/{plat => plat-samsung}/audio.h         |    0
 .../include/{plat => plat-samsung}/backlight.h     |    0
 .../include/{plat => plat-samsung}/camport.h       |    0
 .../include/{plat => plat-samsung}/clock-clksrc.h  |    0
 .../include/{plat => plat-samsung}/clock.h         |    0
 .../include/{plat => plat-samsung}/common-smdk.h   |    0
 .../include/plat-samsung/cpu-freq-core.h           |  293 ++++
 .../include/{plat => plat-samsung}/cpu-freq.h      |    0
 .../include/{plat => plat-samsung}/cpu.h           |    0
 .../include/plat-samsung/debug-macro.S             |   87 +
 .../include/{plat => plat-samsung}/devs.h          |    0
 .../include/{plat => plat-samsung}/dma-core.h      |    0
 .../include/{plat => plat-samsung}/dma-ops.h       |    0
 .../plat-samsung/include/plat-samsung/dma-pl330.h  |  122 ++
 .../include/plat-samsung/dma-s3c24xx.h             |   78 +
 arch/arm/plat-samsung/include/plat-samsung/dma.h   |  130 ++
 .../include/{plat => plat-samsung}/ehci.h          |    0
 .../include/{plat => plat-samsung}/fb-core.h       |    0
 .../include/{plat => plat-samsung}/fb-s3c2410.h    |    0
 .../include/{plat => plat-samsung}/fb.h            |    0
 .../include/{plat => plat-samsung}/fimc-core.h     |    0
 .../include/{plat => plat-samsung}/fiq.h           |    0
 .../{plat => plat-samsung}/gpio-cfg-helpers.h      |    0
 .../include/{plat => plat-samsung}/gpio-cfg.h      |    0
 .../plat-samsung/include/plat-samsung/gpio-core.h  |  124 ++
 .../plat-samsung/include/plat-samsung/gpio-fns.h   |   98 ++
 .../include/{plat => plat-samsung}/hwmon.h         |    0
 .../include/{plat => plat-samsung}/iic-core.h      |    0
 .../include/{plat => plat-samsung}/iic.h           |    0
 .../include/{plat => plat-samsung}/irq-uart.h      |    0
 .../include/{plat => plat-samsung}/irq-vic-timer.h |    0
 .../include/{plat => plat-samsung}/irq.h           |    0
 .../include/{plat => plat-samsung}/irqs.h          |    0
 .../include/{plat => plat-samsung}/keypad-core.h   |    0
 .../include/{plat => plat-samsung}/keypad.h        |    0
 .../include/{plat => plat-samsung}/map-base.h      |    0
 .../plat-samsung/include/plat-samsung/map-s3c.h    |   84 +
 .../plat-samsung/include/plat-samsung/map-s5p.h    |   61 +
 .../include/{plat => plat-samsung}/mci.h           |    0
 .../include/{plat => plat-samsung}/mfc.h           |    0
 .../include/{plat => plat-samsung}/mipi_csis.h     |    0
 .../include/{plat => plat-samsung}/nand-core.h     |    0
 .../include/{plat => plat-samsung}/nand.h          |    0
 .../include/{plat => plat-samsung}/onenand-core.h  |    0
 .../include/{plat => plat-samsung}/pll.h           |    0
 .../include/{plat => plat-samsung}/pm.h            |    0
 .../include/{plat => plat-samsung}/pwm-clock.h     |    0
 .../include/{plat => plat-samsung}/regs-ac97.h     |    0
 .../include/{plat => plat-samsung}/regs-adc.h      |    0
 .../include/{plat => plat-samsung}/regs-ata.h      |    0
 .../include/{plat => plat-samsung}/regs-dma.h      |    0
 .../plat-samsung/include/plat-samsung/regs-fb-v4.h |  159 ++
 .../include/{plat => plat-samsung}/regs-fb.h       |    0
 .../include/{plat => plat-samsung}/regs-iic.h      |    0
 .../include/{plat => plat-samsung}/regs-iis.h      |    0
 .../include/{plat => plat-samsung}/regs-irqtype.h  |    0
 .../include/{plat => plat-samsung}/regs-nand.h     |    0
 .../include/{plat => plat-samsung}/regs-onenand.h  |    0
 .../include/{plat => plat-samsung}/regs-rtc.h      |    0
 .../include/{plat => plat-samsung}/regs-sdhci.h    |    0
 .../include/{plat => plat-samsung}/regs-serial.h   |    0
 .../include/{plat => plat-samsung}/regs-spi.h      |    0
 .../include/{plat => plat-samsung}/regs-srom.h     |    0
 .../include/{plat => plat-samsung}/regs-timer.h    |    0
 .../include/{plat => plat-samsung}/regs-udc.h      |    0
 .../{plat => plat-samsung}/regs-usb-hsotg-phy.h    |    0
 .../include/{plat => plat-samsung}/regs-watchdog.h |    0
 .../include/{plat => plat-samsung}/rtc-core.h      |    0
 .../include/{plat => plat-samsung}/s3c2410.h       |    0
 .../include/{plat => plat-samsung}/s3c2412.h       |    0
 .../include/{plat => plat-samsung}/s3c2416.h       |    0
 .../include/{plat => plat-samsung}/s3c2443.h       |    0
 .../include/{plat => plat-samsung}/s3c244x.h       |    0
 .../include/{plat => plat-samsung}/s3c64xx-spi.h   |    0
 .../include/{plat => plat-samsung}/s5p-clock.h     |    0
 .../include/{plat => plat-samsung}/s5p-time.h      |    0
 arch/arm/plat-samsung/include/plat-samsung/sdhci.h |  380 +++++
 .../include/{plat => plat-samsung}/ts.h            |    0
 .../include/{plat => plat-samsung}/tv-core.h       |    0
 .../include/{plat => plat-samsung}/udc.h           |    0
 .../plat-samsung/include/plat-samsung/uncompress.h |  186 +++
 .../include/{plat => plat-samsung}/usb-control.h   |    0
 .../include/{plat => plat-samsung}/usb-phy.h       |    0
 .../include/{plat => plat-samsung}/wakeup-mask.h   |    0
 .../include/plat-samsung/watchdog-reset.h          |   46 +
 arch/arm/plat-samsung/include/plat/cpu-freq-core.h |  293 ----
 arch/arm/plat-samsung/include/plat/debug-macro.S   |   87 -
 arch/arm/plat-samsung/include/plat/dma-pl330.h     |  122 --
 arch/arm/plat-samsung/include/plat/dma-s3c24xx.h   |   78 -
 arch/arm/plat-samsung/include/plat/dma.h           |  130 --
 arch/arm/plat-samsung/include/plat/gpio-core.h     |  124 --
 arch/arm/plat-samsung/include/plat/gpio-fns.h      |   98 --
 arch/arm/plat-samsung/include/plat/map-s3c.h       |   84 -
 arch/arm/plat-samsung/include/plat/map-s5p.h       |   61 -
 arch/arm/plat-samsung/include/plat/regs-fb-v4.h    |  159 --
 arch/arm/plat-samsung/include/plat/sdhci.h         |  380 -----
 arch/arm/plat-samsung/include/plat/uncompress.h    |  186 ---
 .../arm/plat-samsung/include/plat/watchdog-reset.h |   46 -
 arch/arm/plat-samsung/init.c                       |    8 +-
 arch/arm/plat-samsung/irq-vic-timer.c              |    6 +-
 arch/arm/plat-samsung/platformdata.c               |    4 +-
 arch/arm/plat-samsung/pm-check.c                   |    2 +-
 arch/arm/plat-samsung/pm-gpio.c                    |    4 +-
 arch/arm/plat-samsung/pm.c                         |    4 +-
 arch/arm/plat-samsung/pwm-clock.c                  |    8 +-
 arch/arm/plat-samsung/s5p-clock.c                  |    6 +-
 arch/arm/plat-samsung/s5p-dev-mfc.c                |    6 +-
 arch/arm/plat-samsung/s5p-dev-uart.c               |    2 +-
 arch/arm/plat-samsung/s5p-irq-eint.c               |    8 +-
 arch/arm/plat-samsung/s5p-irq-gpioint.c            |    4 +-
 arch/arm/plat-samsung/s5p-irq-pm.c                 |    6 +-
 arch/arm/plat-samsung/s5p-irq.c                    |    6 +-
 arch/arm/plat-samsung/s5p-pm.c                     |    2 +-
 arch/arm/plat-samsung/s5p-time.c                   |    6 +-
 arch/arm/plat-samsung/time.c                       |    6 +-
 arch/arm/plat-samsung/wakeup-mask.c                |    4 +-
 .../include/{plat => plat-spear}/debug-macro.S     |    0
 .../plat-spear/include/{plat => plat-spear}/gpio.h |    0
 .../include/{plat => plat-spear}/keyboard.h        |    0
 .../include/{plat => plat-spear}/pl080.h           |    0
 .../include/{plat => plat-spear}/shirq.h           |    0
 .../include/{plat => plat-spear}/timex.h           |    0
 .../include/{plat => plat-spear}/uncompress.h      |    0
 arch/arm/plat-spear/shirq.c                        |    2 +-
 arch/arm/plat-versatile/clcd.c                     |    2 +-
 arch/arm/plat-versatile/fpga-irq.c                 |    2 +-
 .../include/{plat => plat-versatile}/clcd.h        |    0
 .../include/{plat => plat-versatile}/clock.h       |    0
 .../include/{plat => plat-versatile}/fpga-irq.h    |    0
 .../include/{plat => plat-versatile}/sched_clock.h |    0
 arch/arm/plat-versatile/sched-clock.c              |    2 +-
 arch/arm/tools/Makefile                            |    5 +
 arch/arm/tools/gen-headers                         |   57 +
 drivers/ata/pata_at91.c                            |    4 +-
 drivers/ata/pata_palmld.c                          |    2 +-
 drivers/ata/pata_pxa.c                             |    6 +-
 drivers/ata/pata_samsung_cf.c                      |    4 +-
 drivers/char/ds1620.c                              |    2 +-
 drivers/char/hw_random/ixp4xx-rng.c                |    2 +-
 drivers/char/hw_random/omap-rng.c                  |    2 +-
 drivers/char/msm_smd_pkt.c                         |    2 +-
 drivers/clk/clk-u300.c                             |    2 +-
 drivers/clk/mxs/clk-imx23.c                        |    4 +-
 drivers/clk/mxs/clk-imx28.c                        |    4 +-
 drivers/clocksource/clksrc-dbx500-prcmu.c          |    4 +-
 drivers/cpufreq/db8500-cpufreq.c                   |    2 +-
 drivers/cpufreq/exynos-cpufreq.c                   |    4 +-
 drivers/cpufreq/exynos4210-cpufreq.c               |    4 +-
 drivers/cpufreq/exynos4x12-cpufreq.c               |    4 +-
 drivers/cpufreq/exynos5250-cpufreq.c               |    6 +-
 drivers/cpufreq/omap-cpufreq.c                     |   10 +-
 drivers/cpufreq/s5pv210-cpufreq.c                  |    2 +-
 drivers/crypto/ixp4xx_crypto.c                     |    4 +-
 drivers/crypto/omap-aes.c                          |    4 +-
 drivers/crypto/omap-sham.c                         |    6 +-
 drivers/crypto/s5p-sss.c                           |    4 +-
 drivers/crypto/tegra-aes.c                         |    2 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |    6 +-
 drivers/crypto/ux500/hash/hash_core.c              |    4 +-
 drivers/devfreq/exynos4_bus.c                      |    4 +-
 drivers/dma/at_hdmac_regs.h                        |    2 +-
 drivers/dma/coh901318.c                            |    2 +-
 drivers/dma/coh901318_lli.c                        |    2 +-
 drivers/dma/coh901318_lli.h                        |    2 +-
 drivers/dma/ep93xx_dma.c                           |    2 +-
 drivers/dma/imx-dma.c                              |    4 +-
 drivers/dma/imx-sdma.c                             |    6 +-
 drivers/dma/ipu/ipu_idmac.c                        |    2 +-
 drivers/dma/ipu/ipu_irq.c                          |    2 +-
 drivers/dma/mmp_tdma.c                             |    4 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/dma/omap-dma.c                             |    2 +-
 drivers/dma/ste_dma40.c                            |    2 +-
 drivers/dma/ste_dma40_ll.c                         |    2 +-
 drivers/gpio/gpio-ep93xx.c                         |    4 +-
 drivers/gpio/gpio-ks8695.c                         |    6 +-
 drivers/gpio/gpio-lpc32xx.c                        |    8 +-
 drivers/gpio/gpio-msm-v1.c                         |    6 +-
 drivers/gpio/gpio-msm-v2.c                         |    4 +-
 drivers/gpio/gpio-omap.c                           |    4 +-
 drivers/gpio/gpio-pxa.c                            |    8 +-
 drivers/gpio/gpio-samsung.c                        |   12 +-
 drivers/gpio/gpio-tegra.c                          |    4 +-
 drivers/gpio/gpio-tnetv107x.c                      |    4 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/hwmon/s3c-hwmon.c                          |    4 +-
 drivers/i2c/busses/i2c-acorn.c                     |    2 +-
 drivers/i2c/busses/i2c-at91.c                      |    6 +-
 drivers/i2c/busses/i2c-davinci.c                   |    4 +-
 drivers/i2c/busses/i2c-imx.c                       |    4 +-
 drivers/i2c/busses/i2c-nuc900.c                    |    4 +-
 drivers/i2c/busses/i2c-s3c2410.c                   |    4 +-
 drivers/i2c/busses/i2c-tegra.c                     |    2 +-
 drivers/iio/adc/at91_adc.c                         |    2 +-
 drivers/input/keyboard/davinci_keyscan.c           |    6 +-
 drivers/input/keyboard/ep93xx_keypad.c             |    4 +-
 drivers/input/keyboard/jornada720_kbd.c            |    6 +-
 drivers/input/keyboard/nomadik-ske-keypad.c        |    2 +-
 drivers/input/keyboard/omap-keypad.c               |    6 +-
 drivers/input/keyboard/pxa27x_keypad.c             |    2 +-
 drivers/input/keyboard/pxa930_rotary.c             |    2 +-
 drivers/input/keyboard/spear-keyboard.c            |    2 +-
 drivers/input/keyboard/tegra-kbc.c                 |    4 +-
 drivers/input/keyboard/w90p910_keypad.c            |    2 +-
 drivers/input/misc/ixp4xx-beeper.c                 |    2 +-
 drivers/input/mouse/pxa930_trkball.c               |    4 +-
 drivers/input/mouse/rpcmouse.c                     |    2 +-
 drivers/input/serio/ams_delta_serio.c              |    4 +-
 drivers/input/serio/rpckbd.c                       |    2 +-
 drivers/input/touchscreen/atmel_tsadcc.c           |    4 +-
 drivers/input/touchscreen/h3600_ts_input.c         |    4 +-
 drivers/input/touchscreen/jornada720_ts.c          |    6 +-
 drivers/input/touchscreen/mainstone-wm97xx.c       |    2 +-
 drivers/input/touchscreen/s3c2410_ts.c             |    6 +-
 drivers/input/touchscreen/tnetv107x-ts.c           |    2 +-
 drivers/input/touchscreen/zylonite-wm97xx.c        |    6 +-
 drivers/iommu/exynos-iommu.c                       |    2 +-
 drivers/iommu/msm_iommu.c                          |    4 +-
 drivers/iommu/msm_iommu_dev.c                      |    6 +-
 drivers/iommu/omap-iommu-debug.c                   |    6 +-
 drivers/iommu/omap-iommu.c                         |    4 +-
 drivers/iommu/omap-iovmm.c                         |    6 +-
 drivers/iommu/tegra-smmu.c                         |    6 +-
 drivers/leds/leds-fsg.c                            |    2 +-
 drivers/leds/leds-netxbig.c                        |    2 +-
 drivers/leds/leds-ns2.c                            |    2 +-
 drivers/leds/leds-s3c24xx.c                        |    6 +-
 drivers/media/video/davinci/isif.c                 |    2 +-
 drivers/media/video/davinci/vpbe_display.c         |    2 +-
 drivers/media/video/davinci/vpbe_osd.c             |    4 +-
 drivers/media/video/davinci/vpbe_venc.c            |    6 +-
 drivers/media/video/davinci/vpif.c                 |    2 +-
 drivers/media/video/davinci/vpss.c                 |    2 +-
 drivers/media/video/mx1_camera.c                   |    8 +-
 drivers/media/video/mx2_camera.c                   |    4 +-
 drivers/media/video/mx3_camera.c                   |    6 +-
 drivers/media/video/omap/omap_vout.c               |    4 +-
 drivers/media/video/omap/omap_vout_vrfb.c          |    4 +-
 drivers/media/video/omap/omap_voutdef.h            |    2 +-
 drivers/media/video/omap/omap_voutlib.c            |    2 +-
 drivers/media/video/omap1_camera.c                 |    2 +-
 drivers/media/video/omap3isp/isp.h                 |    4 +-
 drivers/media/video/omap3isp/ispreg.h              |    2 +-
 drivers/media/video/omap3isp/ispstat.h             |    2 +-
 drivers/media/video/omap3isp/ispvideo.c            |    6 +-
 drivers/media/video/pxa_camera.c                   |    4 +-
 drivers/media/video/s5p-fimc/mipi-csis.c           |    2 +-
 drivers/media/video/s5p-tv/sii9234_drv.c           |    2 +-
 drivers/mfd/db8500-prcmu.c                         |    8 +-
 drivers/mfd/dbx500-prcmu-regs.h                    |    2 +-
 drivers/mfd/mcp-sa11x0.c                           |    4 +-
 drivers/mfd/menelaus.c                             |    2 +-
 drivers/mfd/omap-usb-host.c                        |    4 +-
 drivers/mfd/ucb1x00-ts.c                           |    2 +-
 drivers/misc/ep93xx_pwm.c                          |    2 +-
 drivers/misc/spear13xx_pcie_gadget.c               |    4 +-
 drivers/mmc/host/at91_mci.c                        |    4 +-
 drivers/mmc/host/davinci_mmc.c                     |    4 +-
 drivers/mmc/host/msm_sdcc.c                        |    8 +-
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mmc/host/mxcmmc.c                          |    6 +-
 drivers/mmc/host/omap.c                            |   10 +-
 drivers/mmc/host/omap_hsmmc.c                      |    8 +-
 drivers/mmc/host/pxamci.c                          |    6 +-
 drivers/mmc/host/s3cmci.c                          |    6 +-
 drivers/mmc/host/sdhci-cns3xxx.c                   |    2 +-
 drivers/mmc/host/sdhci-esdhc-imx.c                 |    2 +-
 drivers/mmc/host/sdhci-s3c.c                       |    4 +-
 drivers/mmc/host/sdhci-tegra.c                     |    4 +-
 drivers/mtd/maps/autcpu12-nvram.c                  |    4 +-
 drivers/mtd/maps/cdb89712.c                        |    2 +-
 drivers/mtd/maps/h720x-flash.c                     |    2 +-
 drivers/mtd/maps/pxa2xx-flash.c                    |    2 +-
 drivers/mtd/maps/sa1100-flash.c                    |    2 +-
 drivers/mtd/nand/ams-delta.c                       |    4 +-
 drivers/mtd/nand/autcpu12.c                        |    4 +-
 drivers/mtd/nand/bcm_umi_nand.c                    |    8 +-
 drivers/mtd/nand/cmx270_nand.c                     |    2 +-
 drivers/mtd/nand/davinci_nand.c                    |    4 +-
 drivers/mtd/nand/mxc_nand.c                        |    4 +-
 drivers/mtd/nand/nand_bcm_umi.c                    |    2 +-
 drivers/mtd/nand/nand_bcm_umi.h                    |    4 +-
 drivers/mtd/nand/nomadik_nand.c                    |    4 +-
 drivers/mtd/nand/omap2.c                           |    6 +-
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c                     |    2 +-
 drivers/mtd/nand/s3c2410.c                         |    4 +-
 drivers/mtd/nand/sharpsl.c                         |    2 +-
 drivers/mtd/onenand/omap2.c                        |    8 +-
 drivers/mtd/onenand/samsung.c                      |    2 +-
 drivers/net/can/at91_can.c                         |    2 +-
 drivers/net/ethernet/amd/am79c961a.c               |    2 +-
 drivers/net/ethernet/cadence/at91_ether.c          |    4 +-
 drivers/net/ethernet/cirrus/ep93xx_eth.c           |    2 +-
 drivers/net/ethernet/micrel/ks8695net.c            |    6 +-
 drivers/net/ethernet/netx-eth.c                    |   10 +-
 drivers/net/ethernet/nxp/lpc_eth.c                 |    6 +-
 drivers/net/ethernet/smsc/smc911x.h                |    2 +-
 drivers/net/ethernet/smsc/smc91x.h                 |    4 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    6 +-
 drivers/net/irda/ep7211-sir.c                      |    2 +-
 drivers/net/irda/pxaficp_ir.c                      |    8 +-
 drivers/net/irda/sa1100_ir.c                       |    2 +-
 drivers/net/wan/ixp4xx_hss.c                       |    4 +-
 drivers/pcmcia/at91_cf.c                           |    8 +-
 drivers/pcmcia/omap_cf.c                           |    6 +-
 drivers/pcmcia/pxa2xx_balloon3.c                   |    2 +-
 drivers/pcmcia/pxa2xx_base.c                       |    6 +-
 drivers/pcmcia/pxa2xx_cm_x2xx.c                    |    2 +-
 drivers/pcmcia/pxa2xx_e740.c                       |    2 +-
 drivers/pcmcia/pxa2xx_hx4700.c                     |    2 +-
 drivers/pcmcia/pxa2xx_mainstone.c                  |    4 +-
 drivers/pcmcia/pxa2xx_palmld.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtc.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtx.c                     |    2 +-
 drivers/pcmcia/pxa2xx_trizeps4.c                   |    4 +-
 drivers/pcmcia/pxa2xx_viper.c                      |    2 +-
 drivers/pcmcia/pxa2xx_vpac270.c                    |    2 +-
 drivers/pcmcia/sa1100_assabet.c                    |    2 +-
 drivers/pcmcia/sa1100_cerf.c                       |    4 +-
 drivers/pcmcia/sa1100_h3600.c                      |    4 +-
 drivers/pcmcia/sa1100_nanoengine.c                 |    4 +-
 drivers/pcmcia/sa1100_shannon.c                    |    4 +-
 drivers/pcmcia/sa1100_simpad.c                     |    4 +-
 drivers/pcmcia/sa1111_badge4.c                     |    4 +-
 drivers/pcmcia/sa1111_jornada720.c                 |    2 +-
 drivers/pcmcia/sa1111_lubbock.c                    |    4 +-
 drivers/pcmcia/sa1111_neponset.c                   |    4 +-
 drivers/pcmcia/sa11xx_base.c                       |    2 +-
 drivers/pinctrl/pinctrl-coh901.c                   |    2 +-
 drivers/pinctrl/pinctrl-nomadik.c                  |    4 +-
 drivers/pinctrl/pinctrl-nomadik.h                  |    2 +-
 drivers/pinctrl/pinctrl-tegra.c                    |    2 +-
 drivers/power/avs/smartreflex.c                    |    1 +
 drivers/power/collie_battery.c                     |    2 +-
 drivers/power/s3c_adc_battery.c                    |    2 +-
 drivers/power/tosa_battery.c                       |    2 +-
 drivers/ptp/ptp_ixp46x.c                           |    2 +-
 drivers/pwm/pwm-imx.c                              |    2 +-
 drivers/pwm/pwm-samsung.c                          |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |    4 +-
 drivers/rtc/rtc-at91rm9200.c                       |    2 +-
 drivers/rtc/rtc-at91sam9.c                         |    6 +-
 drivers/rtc/rtc-mxc.c                              |    2 +-
 drivers/rtc/rtc-pxa.c                              |    2 +-
 drivers/rtc/rtc-s3c.c                              |    2 +-
 drivers/rtc/rtc-stmp3xxx.c                         |    2 +-
 drivers/scsi/arm/acornscsi-io.S                    |    2 +-
 drivers/spi/spi-davinci.c                          |    4 +-
 drivers/spi/spi-ep93xx.c                           |    4 +-
 drivers/spi/spi-imx.c                              |    2 +-
 drivers/spi/spi-nuc900.c                           |    2 +-
 drivers/spi/spi-omap-100k.c                        |    2 +-
 drivers/spi/spi-omap-uwire.c                       |    6 +-
 drivers/spi/spi-omap2-mcspi.c                      |    4 +-
 drivers/spi/spi-s3c24xx-fiq.S                      |    6 +-
 drivers/spi/spi-s3c24xx.c                          |    4 +-
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/spi/spi-tegra.c                            |    2 +-
 drivers/staging/nvec/nvec.c                        |    4 +-
 drivers/staging/omapdrm/omap_dmm_tiler.h           |    2 +-
 .../staging/ste_rmi4/board-mop500-u8500uib-rmi4.c  |    4 +-
 drivers/staging/tidspbridge/core/dsp-clock.c       |    4 +-
 drivers/staging/tidspbridge/core/tiomap3430.c      |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430_pwr.c  |    2 +-
 drivers/staging/tidspbridge/core/tiomap_io.c       |    2 +-
 drivers/staging/tidspbridge/core/ue_deh.c          |    2 +-
 .../tidspbridge/include/dspbridge/host_os.h        |    4 +-
 drivers/staging/tidspbridge/rmgr/drv_interface.c   |    2 +-
 drivers/tty/serial/21285.c                         |    2 +-
 drivers/tty/serial/atmel_serial.c                  |    6 +-
 drivers/tty/serial/clps711x.c                      |    2 +-
 drivers/tty/serial/imx.c                           |    2 +-
 drivers/tty/serial/msm_serial_hs.c                 |    4 +-
 drivers/tty/serial/msm_smd_tty.c                   |    2 +-
 drivers/tty/serial/netx-serial.c                   |    4 +-
 drivers/tty/serial/omap-serial.c                   |    6 +-
 drivers/tty/serial/sa1100.c                        |    4 +-
 drivers/tty/serial/samsung.c                       |    4 +-
 drivers/tty/serial/serial_ks8695.c                 |    4 +-
 drivers/uio/uio_pruss.c                            |    2 +-
 drivers/usb/gadget/at91_udc.c                      |   10 +-
 drivers/usb/gadget/atmel_usba_udc.c                |    4 +-
 drivers/usb/gadget/fsl_mxc_udc.c                   |    2 +-
 drivers/usb/gadget/imx_udc.c                       |    4 +-
 drivers/usb/gadget/omap_udc.c                      |    2 +-
 drivers/usb/gadget/pxa25x_udc.c                    |    4 +-
 drivers/usb/gadget/pxa25x_udc.h                    |    2 +-
 drivers/usb/gadget/pxa27x_udc.c                    |    4 +-
 drivers/usb/gadget/s3c-hsudc.c                     |    2 +-
 drivers/usb/gadget/s3c2410_udc.c                   |    4 +-
 drivers/usb/host/ehci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ehci-mxc.c                        |    4 +-
 drivers/usb/host/ehci-omap.c                       |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 drivers/usb/host/ehci-s5p.c                        |    4 +-
 drivers/usb/host/ehci-tegra.c                      |    4 +-
 drivers/usb/host/imx21-hcd.h                       |    2 +-
 drivers/usb/host/ohci-at91.c                       |    6 +-
 drivers/usb/host/ohci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ohci-da8xx.c                      |    4 +-
 drivers/usb/host/ohci-exynos.c                     |    4 +-
 drivers/usb/host/ohci-omap.c                       |    4 +-
 drivers/usb/host/ohci-omap3.c                      |    2 +-
 drivers/usb/host/ohci-pxa27x.c                     |    6 +-
 drivers/usb/host/ohci-s3c2410.c                    |    2 +-
 drivers/usb/host/ohci-sa1111.c                     |    4 +-
 drivers/usb/musb/am35x.c                           |    2 +-
 drivers/usb/musb/da8xx.c                           |    4 +-
 drivers/usb/musb/davinci.c                         |    4 +-
 drivers/usb/musb/musb_dsps.c                       |    2 +-
 drivers/usb/musb/omap2430.h                        |    2 +-
 drivers/usb/musb/tusb6010_omap.c                   |    4 +-
 drivers/usb/musb/ux500_dma.c                       |    2 +-
 drivers/usb/otg/isp1301_omap.c                     |    2 +-
 drivers/usb/otg/msm_otg.c                          |    2 +-
 drivers/video/acornfb.c                            |    4 +-
 drivers/video/backlight/jornada720_bl.c            |    4 +-
 drivers/video/backlight/jornada720_lcd.c           |    4 +-
 drivers/video/backlight/omap1_bl.c                 |    6 +-
 drivers/video/backlight/tosa_bl.c                  |    2 +-
 drivers/video/backlight/tosa_lcd.c                 |    2 +-
 drivers/video/clps711xfb.c                         |    4 +-
 drivers/video/cyber2000fb.c                        |    2 +-
 drivers/video/ep93xx-fb.c                          |    2 +-
 drivers/video/exynos/exynos_mipi_dsi.c             |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_common.c      |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_lowlevel.c    |    2 +-
 drivers/video/imxfb.c                              |    4 +-
 drivers/video/msm/mddi.c                           |    8 +-
 drivers/video/msm/mddi_client_dummy.c              |    2 +-
 drivers/video/msm/mddi_client_nt35399.c            |    2 +-
 drivers/video/msm/mddi_client_toshiba.c            |    2 +-
 drivers/video/msm/mdp.c                            |    4 +-
 drivers/video/msm/mdp_hw.h                         |    4 +-
 drivers/video/msm/mdp_ppp.c                        |    2 +-
 drivers/video/msm/msm_fb.c                         |    4 +-
 drivers/video/mx3fb.c                              |    8 +-
 drivers/video/nuc900fb.c                           |    8 +-
 drivers/video/nuc900fb.h                           |    4 +-
 drivers/video/omap/hwa742.c                        |    2 +-
 drivers/video/omap/lcd_ams_delta.c                 |    4 +-
 drivers/video/omap/lcd_inn1510.c                   |    2 +-
 drivers/video/omap/lcd_mipid.c                     |    2 +-
 drivers/video/omap/lcd_osk.c                       |    2 +-
 drivers/video/omap/lcd_palmte.c                    |    2 +-
 drivers/video/omap/lcdc.c                          |    4 +-
 drivers/video/omap/omapfb_main.c                   |    2 +-
 drivers/video/omap/sossi.c                         |    2 +-
 drivers/video/omap2/dss/dispc.c                    |    2 +-
 drivers/video/omap2/dss/dpi.c                      |    2 +-
 drivers/video/omap2/dss/dsi.c                      |    2 +-
 drivers/video/omap2/dss/dss.c                      |    4 +-
 drivers/video/omap2/dss/dss_features.c             |    2 +-
 drivers/video/omap2/dss/overlay.c                  |    2 +-
 drivers/video/omap2/dss/venc.c                     |    2 +-
 drivers/video/omap2/omapfb/omapfb-ioctl.c          |    4 +-
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 +-
 drivers/video/omap2/omapfb/omapfb-sysfs.c          |    2 +-
 drivers/video/omap2/vram.c                         |    4 +-
 drivers/video/omap2/vrfb.c                         |    4 +-
 drivers/video/pnx4008/dum.h                        |    2 +-
 drivers/video/pxafb.c                              |    6 +-
 drivers/video/s3c-fb.c                             |    4 +-
 drivers/video/sa1100fb.c                           |    4 +-
 drivers/video/vt8500lcdfb.c                        |    2 +-
 drivers/video/wm8505fb.c                           |    2 +-
 drivers/w1/masters/omap_hdq.c                      |    2 +-
 drivers/watchdog/at91rm9200_wdt.c                  |    2 +-
 drivers/watchdog/imx2_wdt.c                        |    2 +-
 drivers/watchdog/ixp4xx_wdt.c                      |    2 +-
 drivers/watchdog/ks8695_wdt.c                      |    4 +-
 drivers/watchdog/omap_wdt.c                        |    2 +-
 drivers/watchdog/s3c2410_wdt.c                     |    2 +-
 drivers/watchdog/wdt285.c                          |    2 +-
 include/linux/mfd/davinci_voicecodec.h             |    2 +-
 include/linux/mfd/dbx500-prcmu.h                   |    2 +-
 include/linux/omapfb.h                             |    2 +-
 include/linux/platform_data/atmel-aes.h            |    2 +-
 include/linux/power/smartreflex.h                  |    2 +-
 include/linux/spi/pxa2xx_spi.h                     |    2 +-
 sound/arm/pxa2xx-ac97-lib.c                        |    6 +-
 sound/arm/pxa2xx-ac97.c                            |    4 +-
 sound/arm/pxa2xx-pcm-lib.c                         |    2 +-
 sound/arm/pxa2xx-pcm.h                             |    2 +-
 sound/atmel/ac97c.c                                |    6 +-
 sound/oss/vidc.c                                   |    2 +-
 sound/oss/vidc_fill.S                              |    2 +-
 sound/oss/waveartist.c                             |    2 +-
 sound/soc/atmel/atmel_ssc_dai.c                    |    2 +-
 sound/soc/atmel/sam9g20_wm8731.c                   |    4 +-
 sound/soc/atmel/snd-soc-afeb9260.c                 |    2 +-
 sound/soc/davinci/davinci-evm.c                    |    6 +-
 sound/soc/davinci/davinci-i2s.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.h                  |    2 +-
 sound/soc/davinci/davinci-pcm.c                    |    4 +-
 sound/soc/davinci/davinci-pcm.h                    |    4 +-
 sound/soc/davinci/davinci-sffsdr.c                 |    2 +-
 sound/soc/ep93xx/edb93xx.c                         |    2 +-
 sound/soc/ep93xx/ep93xx-ac97.c                     |    2 +-
 sound/soc/ep93xx/ep93xx-i2s.c                      |    6 +-
 sound/soc/ep93xx/ep93xx-pcm.c                      |    6 +-
 sound/soc/ep93xx/simone.c                          |    2 +-
 sound/soc/ep93xx/snappercl15.c                     |    2 +-
 sound/soc/fsl/imx-pcm-fiq.c                        |    4 +-
 sound/soc/fsl/imx-ssi.c                            |    4 +-
 sound/soc/fsl/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    4 +-
 sound/soc/kirkwood/kirkwood-t5325.c                |    4 +-
 sound/soc/mxs/mxs-saif.c                           |    4 +-
 sound/soc/nuc900/nuc900-ac97.c                     |    2 +-
 sound/soc/nuc900/nuc900-pcm.c                      |    2 +-
 sound/soc/omap/am3517evm.c                         |    6 +-
 sound/soc/omap/ams-delta.c                         |    4 +-
 sound/soc/omap/igep0020.c                          |    6 +-
 sound/soc/omap/mcbsp.c                             |    2 +-
 sound/soc/omap/n810.c                              |    4 +-
 sound/soc/omap/omap-abe-twl6040.c                  |    4 +-
 sound/soc/omap/omap-dmic.c                         |    2 +-
 sound/soc/omap/omap-hdmi.c                         |    2 +-
 sound/soc/omap/omap-mcbsp.c                        |    4 +-
 sound/soc/omap/omap-mcpdm.c                        |    4 +-
 sound/soc/omap/omap-pcm.c                          |    2 +-
 sound/soc/omap/omap3beagle.c                       |    6 +-
 sound/soc/omap/omap3evm.c                          |    6 +-
 sound/soc/omap/omap3pandora.c                      |    2 +-
 sound/soc/omap/osk5912.c                           |    4 +-
 sound/soc/omap/overo.c                             |    6 +-
 sound/soc/omap/rx51.c                              |    2 +-
 sound/soc/omap/sdp3430.c                           |    6 +-
 sound/soc/omap/zoom2.c                             |    8 +-
 sound/soc/pxa/corgi.c                              |    4 +-
 sound/soc/pxa/e740_wm9705.c                        |    4 +-
 sound/soc/pxa/e750_wm9705.c                        |    4 +-
 sound/soc/pxa/e800_wm9712.c                        |    4 +-
 sound/soc/pxa/em-x270.c                            |    2 +-
 sound/soc/pxa/hx4700.c                             |    2 +-
 sound/soc/pxa/magician.c                           |    2 +-
 sound/soc/pxa/mioa701_wm9713.c                     |    2 +-
 sound/soc/pxa/mmp-pcm.c                            |    2 +-
 sound/soc/pxa/palm27x.c                            |    4 +-
 sound/soc/pxa/poodle.c                             |    4 +-
 sound/soc/pxa/pxa-ssp.c                            |    4 +-
 sound/soc/pxa/pxa2xx-ac97.c                        |    8 +-
 sound/soc/pxa/pxa2xx-i2s.c                         |    6 +-
 sound/soc/pxa/spitz.c                              |    2 +-
 sound/soc/pxa/tosa.c                               |    4 +-
 sound/soc/pxa/z2.c                                 |    6 +-
 sound/soc/samsung/ac97.c                           |    4 +-
 sound/soc/samsung/h1940_uda1380.c                  |    4 +-
 sound/soc/samsung/i2s.c                            |    2 +-
 sound/soc/samsung/neo1973_wm8753.c                 |    4 +-
 sound/soc/samsung/pcm.c                            |    4 +-
 sound/soc/samsung/rx1950_uda1380.c                 |    2 +-
 sound/soc/samsung/s3c24xx-i2s.c                    |    2 +-
 sound/soc/samsung/s3c24xx_simtec.c                 |    2 +-
 sound/soc/samsung/s3c24xx_uda134x.c                |    2 +-
 sound/soc/samsung/spdif.c                          |    2 +-
 sound/soc/tegra/tegra30_ahub.c                     |    4 +-
 sound/soc/tegra/tegra_pcm.h                        |    2 +-
 sound/soc/tegra/tegra_wm8903.c                     |    2 +-
 sound/soc/ux500/mop500_ab8500.c                    |    2 +-
 sound/soc/ux500/ux500_msp_dai.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.h                    |    2 +-
 sound/soc/ux500/ux500_pcm.c                        |    2 +-
 3291 files changed, 48901 insertions(+), 48829 deletions(-)


From arnd at arndb.de  Tue Aug 21 11:59:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 15:59:30 -0000
Subject: [RFC 3/4] ARM: treewide: scripted conversion to mach-*/*.h
In-Reply-To: <1345564724-14466-1-git-send-email-arnd@arndb.de>
References: <1345564724-14466-1-git-send-email-arnd@arndb.de>
Message-ID: <1345564724-14466-4-git-send-email-arnd@arndb.de>

While converting all machine specific headers from
automatically detect the right machine and platform
name in most cases. This script uses a number of
information sources for this:

* any arch/arm/mach-*/ directory uses its own headers,
  with a few exceptions, same for plat-*/
* each mach-*/ directory belongs to at most one plat-*
  directory holding header files
* for any header below mach/* that exists in only one
  machine, we know that the users belong to that machine
* some driver directories or files are manually listed
  here.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
===========================================================

fixup()
{
 echo fixup "$1 $2 $3"
 git ls-files $1 | xargs sed -i "s:^\(#.*include <\)$2/:\1$3/:g"
}

fixup arch/arm/mach-s3c2410 mach mach-s3c24xx
fixup arch/arm/mach-s3c2412 mach mach-s3c24xx
fixup arch/arm/mach-s3c2440 mach mach-s3c24xx

fixup arch/arm/plat-mxc mach mach-imx
fixup arch/arm/plat-s3c24xx mach mach-s3c24xx
fixup arch/arm/plat-s3c24xx plat plat-samsung

for i in arch/arm/mach-*; do
	fixup "$i" mach "${i##*/}"
done

for i in arch/arm/plat-* ; do
	fixup "$i" plat "${i##*/}"
done

fixup arch/arm/mach-spear3xx plat plat-spear
fixup arch/arm/mach-spear6xx plat plat-spear
fixup arch/arm/mach-spear13xx plat plat-spear
fixup arch/arm/mach-pxa plat plat-pxa
fixup arch/arm/mach-mmp plat plat-pxa
fixup arch/arm/mach-orion5x plat plat-orion
fixup arch/arm/mach-kirkwood plat plat-orion
fixup arch/arm/mach-mv78xx0 plat plat-orion
fixup arch/arm/mach-dove plat plat-orion
fixup arch/arm/mach-nomadik plat plat-nomadik
fixup arch/arm/mach-ux500 plat plat-nomadik
fixup arch/arm/mach-s3c2410 plat plat-samsung
fixup arch/arm/mach-s3c2412 plat plat-samsung
fixup arch/arm/mach-s3c2440 plat plat-samsung
fixup arch/arm/mach-s3c24xx plat plat-samsung
fixup arch/arm/mach-s3c64xx plat plat-samsung
fixup arch/arm/mach-s5p64x0 plat plat-samsung
fixup arch/arm/mach-s5pc100 plat plat-samsung
fixup arch/arm/mach-s5pv210 plat plat-samsung
fixup arch/arm/mach-exynos plat plat-samsung
fixup arch/arm/mach-omap1 plat plat-omap
fixup arch/arm/mach-omap2 plat plat-omap
fixup arch/arm/mach-versatile plat plat-versatile
fixup arch/arm/mach-integrator plat plat-versatile
fixup arch/arm/mach-realview plat plat-versatile
fixup arch/arm/mach-vexpress plat plat-versatile
fixup arch/arm/mach-zynq plat plat-versatile

fixup drivers/video/omap plat plat-omap
fixup drivers/video/omap2 plat plat-omap
fixup drivers/video/exynos plat plat-samsung
fixup drivers/char/hw_random/omap\* plat plat-omap
fixup drivers/cpufreq/omap\* plat plat-omap
fixup drivers/crypto/omap\* plat plat-omap
fixup drivers/media/video/omap\* plat plat-omap
fixup drivers/input/keyboard/omap\* plat plat-omap
fixup drivers/mmc/host/omap\* plat plat-omap
fixup drivers/mtd/*nand/omap\* plat plat-omap
fixup drivers/spi/spi-omap\* plat plat-omap
fixup drivers/tty/serial/omap\* plat plat-omap
fixup drivers/usb/gadget/omap\* plat plat-omap
fixup drivers/usb/musb/*omap\* plat plat-omap
fixup drivers/dma/omap-dma.c plat plat-omap
fixup drivers/staging/omapdrm plat plat-omap
fixup drivers/staging/tidspbridge/ plat plat-omap
fixup drivers/input/keyboard/spear-keyboard.c plat plat-spear
fixup drivers/cpufreq/exynos-cpufreq.c plat plat-samsung
fixup drivers/crypto/s5p-sss.c plat plat-samsung
fixup drivers/i2c/busses/i2c-nomadik.c plat plat-nomadik
fixup drivers/mtd/nand/s3c2410.c plat plat-samsung
fixup drivers/tty/serial/samsung.c plat plat-samsung
fixup drivers/usb/gadget/s3c-hsotg.c plat plat-samsung
fixup drivers/gpio/gpio-samsung.c plat plat-samsung
fixup sound/soc/samsung plat plat-samsung
fixup sound/soc/omap plat plat-omap
fixup sound/soc/pxa plat plat-pxa
fixup sound/soc/kirkwood/ plat plat-orion
fixup sound/soc/fsl/imx*.[ch] plat plat-mxc

fixup drivers/video/omap mach mach-omap1
fixup drivers/video/omap2 mach mach-omap2
fixup drivers/video/exynos mach mach-exynos
fixup drivers/media/video/davinci mach mach-davinci

fixup sound/soc/omap/osk5912.c mach mach-omap1
fixup sound/soc/omap mach mach-omap2
fixup sound/soc/pxa mach mach-pxa
fixup sound/soc/davinci mach mach-davinci
fixup sound/soc/ep93xx mach mach-ep93xx
fixup sound/soc/kirkwood/ mach mach-kirkwood
fixup sound/soc/fsl/imx*.[ch] mach mach-imx
fixup sound/soc/mxs mach mach-mxs
fixup sound/soc/tegra mach mach-tegra
fixup sound/soc/nuc900 mach mach-w90x900
fixup sound/arm/pxa\* mach mach-pxa
fixup sound/atmel/ac97c.c mach mach-at91
fixup sound/oss/waveartist.c mach mach-footbridge
fixup sound/oss/vidc\* mach mach-rpc
fixup sound/soc/atmel/ mach mach-at91
fixup sound/soc/ux500/ mach mach-ux500

fixup include/linux/spi/pxa2xx_spi.h mach mach-pxa
fixup include/linux/mfd/dbx500-prcmu.h mach mach-ux500

find_unique_mach()
{
  {
    # find files in other architectures using mach/*.h
    git ls-files | grep /mach/[^/]*.h | while read i ;
	do echo ${i##*/}
    done
    # find files we've already renamed in ARM
    for i in arch/arm/mach-*/include/mach-*/ ; do
	git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_mach()
{
  ALLFILES=`git grep -l "^#include.*<mach/"`
  ALLINCLUDES=`git grep "^#include.*<mach/" ${ALLFILES}`
  find_unique_mach | while read i ; do
    echo "$ALLINCLUDES" | if grep -q "#include.*<mach/$i>" &&
		[ -e arch/arm/mach-*/include/mach-*/"$i" ] ; then
       MACH=`ls arch/arm/mach-*/include/mach-*/$i | cut -f 3 -d /`
       THESEFILES=`git grep -l "^#include.*<mach/$i>" ${ALLFILES}`
       echo mach/$i
       for j in ${THESEFILES} ; do
	  fixup $j mach ${MACH}
       done
    fi
  done
}

find_unique_plat()
{
  {
    # all plat/*.h files are already renamed
    for i in arch/arm/plat-*/include/plat-*/ ; do
	git ls-files "$i" | sed -e "s:^$i::g"
    done
  } | sort | uniq -c | grep -w 1  | cut -f 2- -d\1
}
rename_unique_plat()
{
  ALLFILES=`git grep -l "#include.*<plat/"`
  if [ "" != "${ALLFILES}" ] ; then
    find_unique_plat | while read i ; do
      PLAT=`ls arch/arm/plat-*/include/plat-*/$i | cut -f 3 -d /`
      THESEFILES=`git grep -l "^#include.*<plat/$i>" ${ALLFILES}`
      echo plat/$i
       for j in ${THESEFILES} ; do
          fixup $j plat ${PLAT}
       done
    done
  fi
}

rename_unique_mach
rename_unique_plat# Please enter the commit message for your changes. Lines starting
---
 Documentation/spi/ep93xx_spi                       |    2 +-
 arch/arm/boot/compressed/head-shmobile.S           |    2 +-
 arch/arm/boot/compressed/sdhi-shmobile.c           |    2 +-
 arch/arm/mach-at91/at91rm9200.c                    |   10 ++--
 arch/arm/mach-at91/at91rm9200_devices.c            |    8 ++--
 arch/arm/mach-at91/at91rm9200_time.c               |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |   12 ++---
 arch/arm/mach-at91/at91sam9260_devices.c           |   14 +++---
 arch/arm/mach-at91/at91sam9261.c                   |   10 ++--
 arch/arm/mach-at91/at91sam9261_devices.c           |   10 ++--
 arch/arm/mach-at91/at91sam9263.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9263_devices.c           |   10 ++--
 arch/arm/mach-at91/at91sam926x_time.c              |    2 +-
 arch/arm/mach-at91/at91sam9_alt_reset.S            |    6 +--
 arch/arm/mach-at91/at91sam9g45.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9g45_devices.c           |   16 +++----
 arch/arm/mach-at91/at91sam9g45_reset.S             |    6 +--
 arch/arm/mach-at91/at91sam9n12.c                   |    8 ++--
 arch/arm/mach-at91/at91sam9rl.c                    |   12 ++---
 arch/arm/mach-at91/at91sam9rl_devices.c            |   12 ++---
 arch/arm/mach-at91/at91sam9x5.c                    |    8 ++--
 arch/arm/mach-at91/at91x40.c                       |    8 ++--
 arch/arm/mach-at91/at91x40_time.c                  |    4 +-
 arch/arm/mach-at91/board-1arm.c                    |    8 ++--
 arch/arm/mach-at91/board-afeb-9260v1.c             |    6 +--
 arch/arm/mach-at91/board-cam60.c                   |    8 ++--
 arch/arm/mach-at91/board-carmeva.c                 |    6 +--
 arch/arm/mach-at91/board-cpu9krea.c                |   12 ++---
 arch/arm/mach-at91/board-cpuat91.c                 |   12 ++---
 arch/arm/mach-at91/board-csb337.c                  |    6 +--
 arch/arm/mach-at91/board-csb637.c                  |    6 +--
 arch/arm/mach-at91/board-dt.c                      |    4 +-
 arch/arm/mach-at91/board-eb01.c                    |    6 +--
 arch/arm/mach-at91/board-eb9200.c                  |    6 +--
 arch/arm/mach-at91/board-ecbat91.c                 |    8 ++--
 arch/arm/mach-at91/board-eco920.c                  |   10 ++--
 arch/arm/mach-at91/board-flexibity.c               |    6 +--
 arch/arm/mach-at91/board-foxg20.c                  |    8 ++--
 arch/arm/mach-at91/board-gsia18s.c                 |   10 ++--
 arch/arm/mach-at91/board-kafa.c                    |    8 ++--
 arch/arm/mach-at91/board-kb9202.c                  |   12 ++---
 arch/arm/mach-at91/board-neocore926.c              |    8 ++--
 arch/arm/mach-at91/board-pcontrol-g20.c            |    8 ++--
 arch/arm/mach-at91/board-picotux200.c              |   10 ++--
 arch/arm/mach-at91/board-qil-a9260.c               |   10 ++--
 arch/arm/mach-at91/board-rm9200dk.c                |   10 ++--
 arch/arm/mach-at91/board-rm9200ek.c                |   10 ++--
 arch/arm/mach-at91/board-rsi-ews.c                 |    6 +--
 arch/arm/mach-at91/board-sam9-l9260.c              |    8 ++--
 arch/arm/mach-at91/board-sam9260ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9261ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9263ek.c               |   12 ++---
 arch/arm/mach-at91/board-sam9g20ek.c               |   10 ++--
 arch/arm/mach-at91/board-sam9m10g45ek.c            |   12 ++---
 arch/arm/mach-at91/board-sam9rlek.c                |   10 ++--
 arch/arm/mach-at91/board-snapper9260.c             |    8 ++--
 arch/arm/mach-at91/board-stamp9g20.c               |    6 +--
 arch/arm/mach-at91/board-usb-a926x.c               |   10 ++--
 arch/arm/mach-at91/board-yl-9200.c                 |   12 ++---
 arch/arm/mach-at91/clock.c                         |    6 +--
 arch/arm/mach-at91/cpuidle.c                       |    2 +-
 arch/arm/mach-at91/gpio.c                          |    4 +-
 arch/arm/mach-at91/include/mach-at91/at91_ramc.h   |    6 +--
 .../arm/mach-at91/include/mach-at91/at91sam9_smc.h |    2 +-
 arch/arm/mach-at91/include/mach-at91/atmel-mci.h   |    2 +-
 arch/arm/mach-at91/include/mach-at91/debug-macro.S |    4 +-
 arch/arm/mach-at91/include/mach-at91/hardware.h    |   18 ++++----
 arch/arm/mach-at91/include/mach-at91/memory.h      |    2 +-
 arch/arm/mach-at91/include/mach-at91/timex.h       |    2 +-
 arch/arm/mach-at91/include/mach-at91/uncompress.h  |    6 +--
 arch/arm/mach-at91/irq.c                           |    4 +-
 arch/arm/mach-at91/leds.c                          |    2 +-
 arch/arm/mach-at91/pm.c                            |   10 ++--
 arch/arm/mach-at91/pm.h                            |    4 +-
 arch/arm/mach-at91/pm_slowclock.S                  |    6 +--
 arch/arm/mach-at91/sam9_smc.c                      |    2 +-
 arch/arm/mach-at91/setup.c                         |   10 ++--
 arch/arm/mach-bcmring/arch.c                       |   10 ++--
 arch/arm/mach-bcmring/clock.c                      |    8 ++--
 arch/arm/mach-bcmring/clock.h                      |    2 +-
 arch/arm/mach-bcmring/core.c                       |   10 ++--
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |    4 +-
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |    2 +-
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |    6 +--
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      |    4 +-
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |    2 +-
 arch/arm/mach-bcmring/dma.c                        |    4 +-
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/intcHw.h         |    2 +-
 arch/arm/mach-bcmring/include/csp/reg.h            |    2 +-
 .../include/mach-bcmring/csp/cap_inline.h          |    2 +-
 .../include/mach-bcmring/csp/chipcHw_def.h         |    2 +-
 .../include/mach-bcmring/csp/chipcHw_inline.h      |    4 +-
 .../include/mach-bcmring/csp/chipcHw_reg.h         |    4 +-
 .../include/mach-bcmring/csp/ddrcReg.h             |    2 +-
 .../include/mach-bcmring/csp/dmacHw_reg.h          |    2 +-
 .../mach-bcmring/include/mach-bcmring/csp/hw_cfg.h |    4 +-
 .../include/mach-bcmring/csp/intcHw_reg.h          |    2 +-
 .../mach-bcmring/include/mach-bcmring/csp/mm_io.h  |    2 +-
 .../include/mach-bcmring/csp/secHw_def.h           |    4 +-
 .../include/mach-bcmring/csp/tmrHw_reg.h           |    4 +-
 arch/arm/mach-bcmring/include/mach-bcmring/dma.h   |    2 +-
 .../include/mach-bcmring/entry-macro.S             |    6 +--
 .../mach-bcmring/include/mach-bcmring/hardware.h   |    2 +-
 .../mach-bcmring/include/mach-bcmring/reg_nand.h   |    2 +-
 .../mach-bcmring/include/mach-bcmring/reg_umi.h    |    2 +-
 .../mach-bcmring/include/mach-bcmring/uncompress.h |    2 +-
 arch/arm/mach-bcmring/irq.c                        |    6 +--
 arch/arm/mach-bcmring/mm.c                         |    4 +-
 arch/arm/mach-bcmring/timer.c                      |    2 +-
 arch/arm/mach-clps711x/autcpu12.c                  |    4 +-
 arch/arm/mach-clps711x/cdb89712.c                  |    2 +-
 arch/arm/mach-clps711x/ceiva.c                     |    2 +-
 arch/arm/mach-clps711x/common.c                    |    2 +-
 arch/arm/mach-clps711x/edb7211-mm.c                |    2 +-
 arch/arm/mach-clps711x/fortunet.c                  |    2 +-
 .../include/mach-clps711x/debug-macro.S            |    2 +-
 .../include/mach-clps711x/entry-macro.S            |    2 +-
 .../mach-clps711x/include/mach-clps711x/hardware.h |    2 +-
 .../include/mach-clps711x/uncompress.h             |    2 +-
 arch/arm/mach-clps711x/p720t-leds.c                |    2 +-
 arch/arm/mach-clps711x/p720t.c                     |    4 +-
 arch/arm/mach-cns3xxx/cns3420vb.c                  |    4 +-
 arch/arm/mach-cns3xxx/core.c                       |    2 +-
 arch/arm/mach-cns3xxx/devices.c                    |    6 +--
 arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h  |    2 +-
 .../mach-cns3xxx/include/mach-cns3xxx/uncompress.h |    2 +-
 arch/arm/mach-cns3xxx/pcie.c                       |    2 +-
 arch/arm/mach-cns3xxx/pm.c                         |    4 +-
 arch/arm/mach-davinci/aemif.c                      |    2 +-
 arch/arm/mach-davinci/board-da830-evm.c            |   14 +++---
 arch/arm/mach-davinci/board-da850-evm.c            |   12 ++---
 arch/arm/mach-davinci/board-dm355-evm.c            |   10 ++--
 arch/arm/mach-davinci/board-dm355-leopard.c        |   10 ++--
 arch/arm/mach-davinci/board-dm365-evm.c            |   14 +++---
 arch/arm/mach-davinci/board-dm644x-evm.c           |   16 +++----
 arch/arm/mach-davinci/board-dm646x-evm.c           |   14 +++---
 arch/arm/mach-davinci/board-mityomapl138.c         |   12 ++---
 arch/arm/mach-davinci/board-neuros-osd2.c          |   14 +++---
 arch/arm/mach-davinci/board-omapl138-hawk.c        |    6 +--
 arch/arm/mach-davinci/board-sffsdr.c               |   10 ++--
 arch/arm/mach-davinci/board-tnetv107x-evm.c        |   10 ++--
 arch/arm/mach-davinci/cdce949.c                    |    4 +-
 arch/arm/mach-davinci/clock.c                      |    8 ++--
 arch/arm/mach-davinci/common.c                     |    4 +-
 arch/arm/mach-davinci/cp_intc.c                    |    4 +-
 arch/arm/mach-davinci/cpufreq.c                    |    6 +--
 arch/arm/mach-davinci/cpuidle.c                    |    4 +-
 arch/arm/mach-davinci/da830.c                      |   14 +++---
 arch/arm/mach-davinci/da850.c                      |   18 ++++----
 arch/arm/mach-davinci/davinci.h                    |    6 +--
 arch/arm/mach-davinci/devices-da8xx.c              |   10 ++--
 arch/arm/mach-davinci/devices-tnetv107x.c          |    8 ++--
 arch/arm/mach-davinci/devices.c                    |   16 +++----
 arch/arm/mach-davinci/dm355.c                      |   22 ++++-----
 arch/arm/mach-davinci/dm365.c                      |   24 +++++-----
 arch/arm/mach-davinci/dm644x.c                     |   20 ++++----
 arch/arm/mach-davinci/dm646x.c                     |   20 ++++----
 arch/arm/mach-davinci/dma.c                        |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/asp.h   |    4 +-
 .../mach-davinci/include/mach-davinci/cdce949.h    |    2 +-
 .../mach-davinci/include/mach-davinci/cputype.h    |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/da8xx.h |   16 +++----
 .../include/mach-davinci/debug-macro.S             |    2 +-
 .../include/mach-davinci/entry-macro.S             |    2 +-
 .../include/mach-davinci/gpio-davinci.h            |    4 +-
 .../arm/mach-davinci/include/mach-davinci/serial.h |    2 +-
 arch/arm/mach-davinci/include/mach-davinci/spi.h   |    2 +-
 .../mach-davinci/include/mach-davinci/tnetv107x.h  |    6 +--
 .../mach-davinci/include/mach-davinci/uncompress.h |    2 +-
 arch/arm/mach-davinci/irq.c                        |    6 +--
 arch/arm/mach-davinci/mux.c                        |    4 +-
 arch/arm/mach-davinci/mux.h                        |    2 +-
 arch/arm/mach-davinci/pm.c                         |    6 +--
 arch/arm/mach-davinci/psc.c                        |    4 +-
 arch/arm/mach-davinci/serial.c                     |    4 +-
 arch/arm/mach-davinci/sleep.S                      |    4 +-
 arch/arm/mach-davinci/sram.c                       |    4 +-
 arch/arm/mach-davinci/time.c                       |    6 +--
 arch/arm/mach-davinci/tnetv107x.c                  |   18 ++++----
 arch/arm/mach-davinci/usb.c                        |    8 ++--
 arch/arm/mach-dove/addr-map.c                      |    4 +-
 arch/arm/mach-dove/cm-a510.c                       |    2 +-
 arch/arm/mach-dove/common.c                        |   12 ++---
 arch/arm/mach-dove/dove-db-setup.c                 |    2 +-
 arch/arm/mach-dove/include/mach-dove/bridge-regs.h |    2 +-
 arch/arm/mach-dove/include/mach-dove/debug-macro.S |    2 +-
 arch/arm/mach-dove/include/mach-dove/entry-macro.S |    2 +-
 arch/arm/mach-dove/include/mach-dove/gpio.h        |    2 +-
 arch/arm/mach-dove/include/mach-dove/pm.h          |    2 +-
 arch/arm/mach-dove/include/mach-dove/uncompress.h  |    2 +-
 arch/arm/mach-dove/irq.c                           |    6 +--
 arch/arm/mach-dove/mpp.c                           |    4 +-
 arch/arm/mach-dove/pcie.c                          |    8 ++--
 arch/arm/mach-ebsa110/core.c                       |    2 +-
 arch/arm/mach-ebsa110/io.c                         |    2 +-
 arch/arm/mach-ebsa110/leds.c                       |    2 +-
 arch/arm/mach-ep93xx/adssphere.c                   |    2 +-
 arch/arm/mach-ep93xx/clock.c                       |    2 +-
 arch/arm/mach-ep93xx/core.c                        |   10 ++--
 arch/arm/mach-ep93xx/crunch-bits.S                 |    2 +-
 arch/arm/mach-ep93xx/dma.c                         |    4 +-
 arch/arm/mach-ep93xx/edb93xx.c                     |    8 ++--
 arch/arm/mach-ep93xx/gesbc9312.c                   |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/debug-macro.S  |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/gpio-ep93xx.h  |    2 +-
 .../arm/mach-ep93xx/include/mach-ep93xx/hardware.h |    2 +-
 .../mach-ep93xx/include/mach-ep93xx/uncompress.h   |    2 +-
 arch/arm/mach-ep93xx/micro9.c                      |    2 +-
 arch/arm/mach-ep93xx/simone.c                      |    6 +--
 arch/arm/mach-ep93xx/snappercl15.c                 |    6 +--
 arch/arm/mach-ep93xx/soc.h                         |    2 +-
 arch/arm/mach-ep93xx/ts72xx.c                      |    4 +-
 arch/arm/mach-ep93xx/vision_ep9307.c               |    8 ++--
 arch/arm/mach-exynos/clock-exynos4.c               |   22 ++++-----
 arch/arm/mach-exynos/clock-exynos4210.c            |   24 +++++-----
 arch/arm/mach-exynos/clock-exynos4212.c            |   24 +++++-----
 arch/arm/mach-exynos/clock-exynos5.c               |   22 ++++-----
 arch/arm/mach-exynos/common.c                      |   34 +++++++-------
 arch/arm/mach-exynos/cpuidle.c                     |    6 +--
 arch/arm/mach-exynos/dev-ahci.c                    |    8 ++--
 arch/arm/mach-exynos/dev-audio.c                   |   12 ++---
 arch/arm/mach-exynos/dev-drm.c                     |    2 +-
 arch/arm/mach-exynos/dev-dwmci.c                   |    4 +-
 arch/arm/mach-exynos/dev-ohci.c                    |   10 ++--
 arch/arm/mach-exynos/dev-sysmmu.c                  |    8 ++--
 arch/arm/mach-exynos/dev-uart.c                    |    6 +--
 arch/arm/mach-exynos/dma.c                         |   12 ++---
 arch/arm/mach-exynos/hotplug.c                     |    2 +-
 .../mach-exynos/include/mach-exynos/debug-macro.S  |    4 +-
 arch/arm/mach-exynos/include/mach-exynos/dma.h     |    2 +-
 arch/arm/mach-exynos/include/mach-exynos/irqs.h    |    2 +-
 arch/arm/mach-exynos/include/mach-exynos/map.h     |    4 +-
 arch/arm/mach-exynos/include/mach-exynos/pm-core.h |    2 +-
 .../mach-exynos/include/mach-exynos/regs-clock.h   |    6 +--
 .../mach-exynos/include/mach-exynos/regs-gpio.h    |    4 +-
 .../arm/mach-exynos/include/mach-exynos/regs-irq.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-mct.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-mem.h |    2 +-
 .../arm/mach-exynos/include/mach-exynos/regs-pmu.h |    2 +-
 .../mach-exynos/include/mach-exynos/uncompress.h   |    4 +-
 arch/arm/mach-exynos/mach-armlex4210.c             |   16 +++----
 arch/arm/mach-exynos/mach-exynos4-dt.c             |    6 +--
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    6 +--
 arch/arm/mach-exynos/mach-nuri.c                   |   34 +++++++-------
 arch/arm/mach-exynos/mach-origen.c                 |   30 ++++++------
 arch/arm/mach-exynos/mach-smdk4x12.c               |   28 ++++++------
 arch/arm/mach-exynos/mach-smdkv310.c               |   34 +++++++-------
 arch/arm/mach-exynos/mach-universal_c210.c         |   32 ++++++-------
 arch/arm/mach-exynos/mct.c                         |    8 ++--
 arch/arm/mach-exynos/platsmp.c                     |    8 ++--
 arch/arm/mach-exynos/pm.c                          |   22 ++++-----
 arch/arm/mach-exynos/pm_domains.c                  |    4 +-
 arch/arm/mach-exynos/pmu.c                         |    4 +-
 arch/arm/mach-exynos/setup-fimc.c                  |    4 +-
 arch/arm/mach-exynos/setup-fimd0.c                 |    6 +--
 arch/arm/mach-exynos/setup-i2c0.c                  |    6 +--
 arch/arm/mach-exynos/setup-i2c1.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c2.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c3.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c4.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c5.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c6.c                  |    4 +-
 arch/arm/mach-exynos/setup-i2c7.c                  |    4 +-
 arch/arm/mach-exynos/setup-keypad.c                |    2 +-
 arch/arm/mach-exynos/setup-sdhci-gpio.c            |    6 +--
 arch/arm/mach-exynos/setup-spi.c                   |    2 +-
 arch/arm/mach-exynos/setup-usb-phy.c               |    8 ++--
 arch/arm/mach-footbridge/ebsa285-leds.c            |    2 +-
 .../include/mach-footbridge/debug-macro.S          |    2 +-
 .../include/mach-footbridge/entry-macro.S          |    4 +-
 arch/arm/mach-footbridge/isa-irq.c                 |    2 +-
 arch/arm/mach-footbridge/netwinder-leds.c          |    2 +-
 arch/arm/mach-gemini/board-nas4220b.c              |    4 +-
 arch/arm/mach-gemini/devices.c                     |    6 +--
 arch/arm/mach-gemini/gpio.c                        |    4 +-
 .../mach-gemini/include/mach-gemini/debug-macro.S  |    2 +-
 .../mach-gemini/include/mach-gemini/entry-macro.S  |    2 +-
 arch/arm/mach-gemini/include/mach-gemini/gpio.h    |    2 +-
 arch/arm/mach-gemini/include/mach-gemini/system.h  |    4 +-
 .../mach-gemini/include/mach-gemini/uncompress.h   |    2 +-
 arch/arm/mach-gemini/irq.c                         |    2 +-
 arch/arm/mach-gemini/mm.c                          |    2 +-
 arch/arm/mach-gemini/time.c                        |    4 +-
 arch/arm/mach-h720x/common.c                       |    4 +-
 arch/arm/mach-h720x/cpu-h7201.c                    |    4 +-
 arch/arm/mach-h720x/cpu-h7202.c                    |    4 +-
 arch/arm/mach-h720x/h7201-eval.c                   |    2 +-
 arch/arm/mach-h720x/h7202-eval.c                   |    4 +-
 .../mach-h720x/include/mach-h720x/debug-macro.S    |    2 +-
 .../arm/mach-h720x/include/mach-h720x/uncompress.h |    2 +-
 arch/arm/mach-imx/clk-imx1.c                       |    4 +-
 arch/arm/mach-imx/clk-imx21.c                      |    4 +-
 arch/arm/mach-imx/clk-imx25.c                      |    6 +--
 arch/arm/mach-imx/clk-imx27.c                      |    4 +-
 arch/arm/mach-imx/clk-imx31.c                      |    6 +--
 arch/arm/mach-imx/clk-imx35.c                      |    4 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |    4 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    2 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    6 +--
 arch/arm/mach-imx/clk.h                            |    2 +-
 arch/arm/mach-imx/cpu-imx25.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    6 +--
 arch/arm/mach-imx/cpu-imx35.c                      |    4 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    2 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    2 +-
 arch/arm/mach-imx/devices-imx1.h                   |    4 +-
 arch/arm/mach-imx/devices-imx21.h                  |    4 +-
 arch/arm/mach-imx/devices-imx25.h                  |    4 +-
 arch/arm/mach-imx/devices-imx27.h                  |    4 +-
 arch/arm/mach-imx/devices-imx31.h                  |    4 +-
 arch/arm/mach-imx/devices-imx35.h                  |    4 +-
 arch/arm/mach-imx/devices-imx50.h                  |    4 +-
 arch/arm/mach-imx/devices-imx51.h                  |    4 +-
 arch/arm/mach-imx/devices-imx53.h                  |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    6 +--
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 ++--
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    6 +--
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    6 +--
 arch/arm/mach-imx/hotplug.c                        |    2 +-
 arch/arm/mach-imx/imx27-dt.c                       |    4 +-
 arch/arm/mach-imx/imx31-dt.c                       |    4 +-
 arch/arm/mach-imx/imx51-dt.c                       |    4 +-
 arch/arm/mach-imx/imx53-dt.c                       |    4 +-
 arch/arm/mach-imx/include/mach-imx/debug-macro.S   |    2 +-
 .../arm/mach-imx/include/mach-imx/devices-common.h |   32 ++++++-------
 arch/arm/mach-imx/include/mach-imx/dma-mx1-mx2.h   |    2 +-
 arch/arm/mach-imx/include/mach-imx/hardware.h      |   26 +++++------
 arch/arm/mach-imx/include/mach-imx/iomux-mx1.h     |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx21.h    |    4 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx25.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx27.h    |    4 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx35.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx50.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx51.h    |    2 +-
 arch/arm/mach-imx/include/mach-imx/iomux-mx53.h    |    2 +-
 arch/arm/mach-imx/iomux-imx31.c                    |    4 +-
 arch/arm/mach-imx/lluart.c                         |    2 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    6 +--
 arch/arm/mach-imx/mach-armadillo5x0.c              |    8 ++--
 arch/arm/mach-imx/mach-bug.c                       |    6 +--
 arch/arm/mach-imx/mach-cpuimx27.c                  |   10 ++--
 arch/arm/mach-imx/mach-cpuimx35.c                  |    8 ++--
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    8 ++--
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 ++--
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    6 +--
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +--
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +--
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +--
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    8 ++--
 arch/arm/mach-imx/mach-mx1ads.c                    |    6 +--
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +--
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +--
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx31ads.c                   |    4 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   10 ++--
 arch/arm/mach-imx/mach-mx31lite.c                  |   10 ++--
 arch/arm/mach-imx/mach-mx31moboard.c               |   12 ++---
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    6 +--
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    8 ++--
 arch/arm/mach-imx/mach-mx51_babbage.c              |    6 +--
 arch/arm/mach-imx/mach-mx51_efikamx.c              |    6 +--
 arch/arm/mach-imx/mach-mx51_efikasb.c              |    8 ++--
 arch/arm/mach-imx/mach-mx53_ard.c                  |    6 +--
 arch/arm/mach-imx/mach-mx53_evk.c                  |    6 +--
 arch/arm/mach-imx/mach-mx53_loco.c                 |    6 +--
 arch/arm/mach-imx/mach-mx53_smd.c                  |    6 +--
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +--
 arch/arm/mach-imx/mach-pca100.c                    |    8 ++--
 arch/arm/mach-imx/mach-pcm037.c                    |    8 ++--
 arch/arm/mach-imx/mach-pcm037_eet.c                |    4 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   10 ++--
 arch/arm/mach-imx/mach-pcm043.c                    |    8 ++--
 arch/arm/mach-imx/mach-qong.c                      |    6 +--
 arch/arm/mach-imx/mach-scb9328.c                   |    6 +--
 arch/arm/mach-imx/mach-vpr200.c                    |    6 +--
 arch/arm/mach-imx/mm-imx1.c                        |    6 +--
 arch/arm/mach-imx/mm-imx21.c                       |    8 ++--
 arch/arm/mach-imx/mm-imx25.c                       |   10 ++--
 arch/arm/mach-imx/mm-imx27.c                       |    8 ++--
 arch/arm/mach-imx/mm-imx3.c                        |    8 ++--
 arch/arm/mach-imx/mm-imx5.c                        |    8 ++--
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |    2 +-
 arch/arm/mach-imx/mx31lilly-db.c                   |    8 ++--
 arch/arm/mach-imx/mx31lite-db.c                    |    8 ++--
 arch/arm/mach-imx/mx31moboard-devboard.c           |    8 ++--
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    8 ++--
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   10 ++--
 arch/arm/mach-imx/mx51_efika.c                     |    8 ++--
 arch/arm/mach-imx/pcm970-baseboard.c               |    6 +--
 arch/arm/mach-imx/platsmp.c                        |    4 +-
 arch/arm/mach-imx/pm-imx27.c                       |    2 +-
 arch/arm/mach-imx/pm-imx3.c                        |    6 +--
 arch/arm/mach-imx/pm-imx5.c                        |    6 +--
 arch/arm/mach-imx/pm-imx6q.c                       |    4 +-
 arch/arm/mach-integrator/core.c                    |    8 ++--
 arch/arm/mach-integrator/cpu.c                     |    4 +-
 arch/arm/mach-integrator/impd1.c                   |    4 +-
 arch/arm/mach-integrator/integrator_ap.c           |   10 ++--
 arch/arm/mach-integrator/integrator_cp.c           |   16 +++----
 arch/arm/mach-integrator/leds.c                    |    6 +--
 arch/arm/mach-integrator/lm.c                      |    2 +-
 arch/arm/mach-integrator/pci.c                     |    2 +-
 arch/arm/mach-integrator/pci_v3.c                  |    6 +--
 arch/arm/mach-iop13xx/include/mach-iop13xx/adma.h  |    2 +-
 .../arm/mach-iop13xx/include/mach-iop13xx/memory.h |    2 +-
 arch/arm/mach-iop13xx/include/mach-iop13xx/pci.h   |    2 +-
 .../mach-iop13xx/include/mach-iop13xx/uncompress.h |    2 +-
 arch/arm/mach-iop13xx/io.c                         |    2 +-
 arch/arm/mach-iop13xx/iq81340mc.c                  |    6 +--
 arch/arm/mach-iop13xx/iq81340sc.c                  |    6 +--
 arch/arm/mach-iop13xx/irq.c                        |    6 +--
 arch/arm/mach-iop13xx/pci.c                        |    4 +-
 arch/arm/mach-iop13xx/setup.c                      |    2 +-
 arch/arm/mach-iop32x/em7210.c                      |    4 +-
 arch/arm/mach-iop32x/glantank.c                    |    4 +-
 .../mach-iop32x/include/mach-iop32x/entry-macro.S  |    2 +-
 .../mach-iop32x/include/mach-iop32x/uncompress.h   |    2 +-
 arch/arm/mach-iop32x/iq31244.c                     |    4 +-
 arch/arm/mach-iop32x/iq80321.c                     |    4 +-
 arch/arm/mach-iop32x/irq.c                         |    2 +-
 arch/arm/mach-iop32x/n2100.c                       |    4 +-
 .../mach-iop33x/include/mach-iop33x/entry-macro.S  |    2 +-
 .../mach-iop33x/include/mach-iop33x/uncompress.h   |    2 +-
 arch/arm/mach-iop33x/iq80331.c                     |    4 +-
 arch/arm/mach-iop33x/iq80332.c                     |    4 +-
 arch/arm/mach-iop33x/irq.c                         |    2 +-
 arch/arm/mach-iop33x/uart.c                        |    2 +-
 arch/arm/mach-ixp4xx/avila-pci.c                   |    2 +-
 arch/arm/mach-ixp4xx/avila-setup.c                 |    2 +-
 arch/arm/mach-ixp4xx/common-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/common.c                      |    6 +--
 arch/arm/mach-ixp4xx/coyote-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/coyote-setup.c                |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-pci.c             |    2 +-
 arch/arm/mach-ixp4xx/gateway7001-setup.c           |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/gtwx5715-setup.c              |    2 +-
 .../mach-ixp4xx/include/mach-ixp4xx/entry-macro.S  |    2 +-
 .../arm/mach-ixp4xx/include/mach-ixp4xx/hardware.h |    2 +-
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/io.h      |    2 +-
 .../arm/mach-ixp4xx/include/mach-ixp4xx/platform.h |    2 +-
 arch/arm/mach-ixp4xx/include/mach-ixp4xx/timex.h   |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/ixdp425-setup.c               |    2 +-
 arch/arm/mach-ixp4xx/ixdpg425-pci.c                |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_npe.c                  |    2 +-
 arch/arm/mach-ixp4xx/ixp4xx_qmgr.c                 |    2 +-
 arch/arm/mach-ixp4xx/miccpt-pci.c                  |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-pci.c                 |    2 +-
 arch/arm/mach-ixp4xx/wg302v2-setup.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c                  |    4 +-
 arch/arm/mach-kirkwood/board-dnskw.c               |    4 +-
 arch/arm/mach-kirkwood/board-dreamplug.c           |    6 +--
 arch/arm/mach-kirkwood/board-dt.c                  |    4 +-
 arch/arm/mach-kirkwood/board-goflexnet.c           |    6 +--
 arch/arm/mach-kirkwood/board-ib62x0.c              |    2 +-
 arch/arm/mach-kirkwood/board-iconnect.c            |    2 +-
 arch/arm/mach-kirkwood/board-lsxl.c                |    2 +-
 arch/arm/mach-kirkwood/board-ts219.c               |    2 +-
 arch/arm/mach-kirkwood/common.c                    |   22 ++++-----
 arch/arm/mach-kirkwood/cpuidle.c                   |    2 +-
 arch/arm/mach-kirkwood/d2net_v2-setup.c            |    4 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c        |    4 +-
 arch/arm/mach-kirkwood/dockstar-setup.c            |    4 +-
 arch/arm/mach-kirkwood/guruplug-setup.c            |    4 +-
 .../include/mach-kirkwood/bridge-regs.h            |    2 +-
 .../include/mach-kirkwood/debug-macro.S            |    2 +-
 .../include/mach-kirkwood/entry-macro.S            |    2 +-
 .../arm/mach-kirkwood/include/mach-kirkwood/gpio.h |    2 +-
 .../include/mach-kirkwood/uncompress.h             |    2 +-
 arch/arm/mach-kirkwood/irq.c                       |    4 +-
 arch/arm/mach-kirkwood/lacie_v2-common.c           |    6 +--
 arch/arm/mach-kirkwood/mpp.c                       |    4 +-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c     |    2 +-
 arch/arm/mach-kirkwood/netspace_v2-setup.c         |    4 +-
 arch/arm/mach-kirkwood/netxbig_v2-setup.c          |    4 +-
 arch/arm/mach-kirkwood/openrd-setup.c              |    4 +-
 arch/arm/mach-kirkwood/pcie.c                      |    6 +--
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c       |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c           |    4 +-
 arch/arm/mach-kirkwood/sheevaplug-setup.c          |    4 +-
 arch/arm/mach-kirkwood/t5325-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c               |    2 +-
 arch/arm/mach-kirkwood/ts41x-setup.c               |    4 +-
 arch/arm/mach-kirkwood/tsx1x-common.c              |    2 +-
 arch/arm/mach-ks8695/board-acs5k.c                 |    4 +-
 arch/arm/mach-ks8695/board-dsm320.c                |    4 +-
 arch/arm/mach-ks8695/board-micrel.c                |    4 +-
 arch/arm/mach-ks8695/cpu.c                         |    6 +--
 arch/arm/mach-ks8695/devices.c                     |   12 ++---
 .../mach-ks8695/include/mach-ks8695/debug-macro.S  |    4 +-
 .../mach-ks8695/include/mach-ks8695/entry-macro.S  |    4 +-
 arch/arm/mach-ks8695/include/mach-ks8695/memory.h  |    2 +-
 arch/arm/mach-ks8695/include/mach-ks8695/timex.h   |    2 +-
 .../mach-ks8695/include/mach-ks8695/uncompress.h   |    2 +-
 arch/arm/mach-ks8695/irq.c                         |    6 +--
 arch/arm/mach-ks8695/leds.c                        |    2 +-
 arch/arm/mach-ks8695/pci.c                         |    6 +--
 arch/arm/mach-ks8695/time.c                        |    4 +-
 arch/arm/mach-lpc32xx/clock.c                      |    4 +-
 arch/arm/mach-lpc32xx/common.c                     |    4 +-
 arch/arm/mach-lpc32xx/common.h                     |    2 +-
 .../include/mach-lpc32xx/entry-macro.S             |    4 +-
 .../mach-lpc32xx/include/mach-lpc32xx/uncompress.h |    4 +-
 arch/arm/mach-lpc32xx/irq.c                        |    6 +--
 arch/arm/mach-lpc32xx/phy3250.c                    |    8 ++--
 arch/arm/mach-lpc32xx/pm.c                         |    4 +-
 arch/arm/mach-lpc32xx/serial.c                     |    4 +-
 arch/arm/mach-lpc32xx/suspend.S                    |    4 +-
 arch/arm/mach-lpc32xx/timer.c                      |    4 +-
 arch/arm/mach-mmp/aspenite.c                       |   10 ++--
 arch/arm/mach-mmp/avengers_lite.c                  |    8 ++--
 arch/arm/mach-mmp/brownstone.c                     |    8 ++--
 arch/arm/mach-mmp/clock.c                          |    2 +-
 arch/arm/mach-mmp/common.c                         |    4 +-
 arch/arm/mach-mmp/devices.c                        |    8 ++--
 arch/arm/mach-mmp/flint.c                          |    8 ++--
 arch/arm/mach-mmp/gplugd.c                         |    6 +--
 arch/arm/mach-mmp/include/mach-mmp/debug-macro.S   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/dma.h           |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/entry-macro.S   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/gpio.h          |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-mmp2.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa168.h    |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp-pxa910.h    |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mfp.h           |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/mmp2.h          |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/pm-mmp2.h       |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/pxa168.h        |    8 ++--
 arch/arm/mach-mmp/include/mach-mmp/pxa910.h        |    4 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-apbc.h     |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-apmu.h     |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-icu.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-rtc.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-smc.h      |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/regs-timers.h   |    2 +-
 arch/arm/mach-mmp/include/mach-mmp/uncompress.h    |    2 +-
 arch/arm/mach-mmp/irq.c                            |    6 +--
 arch/arm/mach-mmp/jasper.c                         |    8 ++--
 arch/arm/mach-mmp/mmp-dt.c                         |    2 +-
 arch/arm/mach-mmp/mmp2-dt.c                        |    4 +-
 arch/arm/mach-mmp/mmp2.c                           |   18 ++++----
 arch/arm/mach-mmp/pm-mmp2.c                        |   12 ++---
 arch/arm/mach-mmp/pm-pxa910.c                      |   12 ++---
 arch/arm/mach-mmp/pxa168.c                         |   20 ++++----
 arch/arm/mach-mmp/pxa910.c                         |   16 +++----
 arch/arm/mach-mmp/sram.c                           |    2 +-
 arch/arm/mach-mmp/tavorevb.c                       |    8 ++--
 arch/arm/mach-mmp/teton_bga.c                      |   12 ++---
 arch/arm/mach-mmp/time.c                           |   10 ++--
 arch/arm/mach-mmp/ttc_dkb.c                        |   10 ++--
 arch/arm/mach-msm/acpuclock-arm11.c                |    4 +-
 arch/arm/mach-msm/board-halibut.c                  |    8 ++--
 arch/arm/mach-msm/board-mahimahi.c                 |    6 +--
 arch/arm/mach-msm/board-msm7x27.c                  |   10 ++--
 arch/arm/mach-msm/board-msm7x30.c                  |    8 ++--
 arch/arm/mach-msm/board-msm8960.c                  |    4 +-
 arch/arm/mach-msm/board-msm8x60.c                  |    4 +-
 arch/arm/mach-msm/board-qsd8x50.c                  |   10 ++--
 arch/arm/mach-msm/board-sapphire.c                 |    8 ++--
 arch/arm/mach-msm/board-trout-mmc.c                |    4 +-
 arch/arm/mach-msm/board-trout-panel.c              |    4 +-
 arch/arm/mach-msm/board-trout.c                    |    6 +--
 arch/arm/mach-msm/board-trout.h                    |    4 +-
 arch/arm/mach-msm/clock-pcom.c                     |    2 +-
 arch/arm/mach-msm/clock.h                          |    2 +-
 arch/arm/mach-msm/devices-iommu.c                  |    4 +-
 arch/arm/mach-msm/devices-msm7x00.c                |    6 +--
 arch/arm/mach-msm/devices-msm7x30.c                |   10 ++--
 arch/arm/mach-msm/devices-msm8960.c                |    4 +-
 arch/arm/mach-msm/devices-qsd8x50.c                |   10 ++--
 arch/arm/mach-msm/dma.c                            |    2 +-
 arch/arm/mach-msm/gpiomux-v2.c                     |    2 +-
 arch/arm/mach-msm/gpiomux.h                        |    2 +-
 arch/arm/mach-msm/include/mach-msm/board.h         |    2 +-
 arch/arm/mach-msm/include/mach-msm/debug-macro.S   |    4 +-
 arch/arm/mach-msm/include/mach-msm/dma.h           |    2 +-
 arch/arm/mach-msm/include/mach-msm/entry-macro.S   |    2 +-
 arch/arm/mach-msm/include/mach-msm/sirc.h          |    2 +-
 arch/arm/mach-msm/include/mach-msm/uncompress.h    |    2 +-
 arch/arm/mach-msm/io.c                             |    6 +--
 arch/arm/mach-msm/irq-vic.c                        |    4 +-
 arch/arm/mach-msm/irq.c                            |    4 +-
 arch/arm/mach-msm/platsmp.c                        |    2 +-
 arch/arm/mach-msm/proc_comm.c                      |    4 +-
 arch/arm/mach-msm/smd.c                            |    4 +-
 arch/arm/mach-msm/smd_debug.c                      |    2 +-
 arch/arm/mach-msm/smd_private.h                    |    2 +-
 arch/arm/mach-msm/timer.c                          |    6 +--
 arch/arm/mach-msm/vreg.c                           |    2 +-
 arch/arm/mach-mv78xx0/addr-map.c                   |    2 +-
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c          |    2 +-
 arch/arm/mach-mv78xx0/common.c                     |   16 +++----
 arch/arm/mach-mv78xx0/db78x00-bp-setup.c           |    2 +-
 .../include/mach-mv78xx0/bridge-regs.h             |    2 +-
 .../include/mach-mv78xx0/debug-macro.S             |    2 +-
 .../include/mach-mv78xx0/entry-macro.S             |    2 +-
 arch/arm/mach-mv78xx0/include/mach-mv78xx0/gpio.h  |    2 +-
 .../mach-mv78xx0/include/mach-mv78xx0/uncompress.h |    2 +-
 arch/arm/mach-mv78xx0/irq.c                        |    4 +-
 arch/arm/mach-mv78xx0/mpp.c                        |    4 +-
 arch/arm/mach-mv78xx0/pcie.c                       |    4 +-
 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c         |    2 +-
 arch/arm/mach-mvebu/armada-370-xp.c                |    2 +-
 .../mach-mvebu/include/mach-mvebu/debug-macro.S    |    2 +-
 .../arm/mach-mvebu/include/mach-mvebu/uncompress.h |    2 +-
 arch/arm/mach-mxs/devices-mx23.h                   |    4 +-
 arch/arm/mach-mxs/devices-mx28.h                   |    4 +-
 arch/arm/mach-mxs/devices/platform-auart.c         |    6 +--
 arch/arm/mach-mxs/devices/platform-dma.c           |    6 +--
 arch/arm/mach-mxs/devices/platform-fec.c           |    4 +-
 arch/arm/mach-mxs/devices/platform-flexcan.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-gpio-mxs.c      |    6 +--
 arch/arm/mach-mxs/devices/platform-gpmi-nand.c     |    6 +--
 arch/arm/mach-mxs/devices/platform-mxs-i2c.c       |    4 +-
 arch/arm/mach-mxs/devices/platform-mxs-mmc.c       |    6 +--
 arch/arm/mach-mxs/devices/platform-mxs-pwm.c       |    2 +-
 arch/arm/mach-mxs/devices/platform-mxs-saif.c      |    6 +--
 arch/arm/mach-mxs/devices/platform-mxsfb.c         |    6 +--
 arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c  |    6 +--
 arch/arm/mach-mxs/icoll.c                          |    4 +-
 arch/arm/mach-mxs/include/mach-mxs/debug-macro.S   |    4 +-
 arch/arm/mach-mxs/include/mach-mxs/entry-macro.S   |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx23.h    |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/iomux-mx28.h    |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mx23.h          |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mx28.h          |    2 +-
 arch/arm/mach-mxs/include/mach-mxs/mxs.h           |    4 +-
 arch/arm/mach-mxs/iomux.c                          |    4 +-
 arch/arm/mach-mxs/mach-apx4devkit.c                |    6 +--
 arch/arm/mach-mxs/mach-m28evk.c                    |    4 +-
 arch/arm/mach-mxs/mach-mx23evk.c                   |    4 +-
 arch/arm/mach-mxs/mach-mx28evk.c                   |    6 +--
 arch/arm/mach-mxs/mach-mxs.c                       |    2 +-
 arch/arm/mach-mxs/mach-stmp378x_devb.c             |    4 +-
 arch/arm/mach-mxs/mach-tx28.c                      |    4 +-
 arch/arm/mach-mxs/mm.c                             |    8 ++--
 arch/arm/mach-mxs/module-tx28.c                    |    2 +-
 arch/arm/mach-mxs/ocotp.c                          |    2 +-
 arch/arm/mach-mxs/system.c                         |    4 +-
 arch/arm/mach-mxs/timer.c                          |    4 +-
 arch/arm/mach-netx/fb.c                            |    4 +-
 arch/arm/mach-netx/generic.c                       |    4 +-
 arch/arm/mach-netx/nxdb500.c                       |    6 +--
 arch/arm/mach-netx/nxdkn.c                         |    6 +--
 arch/arm/mach-netx/nxeb500hmi.c                    |    6 +--
 arch/arm/mach-netx/pfifo.c                         |    6 +--
 arch/arm/mach-netx/time.c                          |    4 +-
 arch/arm/mach-netx/xc.c                            |    8 ++--
 arch/arm/mach-nomadik/board-nhk8815.c              |    8 ++--
 arch/arm/mach-nomadik/cpu-8815.c                   |    6 +--
 arch/arm/mach-nomadik/i2c-8815nhk.c                |    4 +-
 arch/arm/mach-nomadik/include/mach-nomadik/fsmc.h  |    2 +-
 arch/arm/mach-nomadik/include/mach-nomadik/irqs.h  |    2 +-
 .../mach-nomadik/include/mach-nomadik/uncompress.h |    2 +-
 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    4 +-
 arch/arm/mach-omap1/ams-delta-fiq.c                |    4 +-
 arch/arm/mach-omap1/board-ams-delta.c              |   18 ++++----
 arch/arm/mach-omap1/board-fsample.c                |   16 +++----
 arch/arm/mach-omap1/board-generic.c                |    8 ++--
 arch/arm/mach-omap1/board-h2-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h2.c                     |   18 ++++----
 arch/arm/mach-omap1/board-h3-mmc.c                 |    2 +-
 arch/arm/mach-omap1/board-h3.c                     |   18 ++++----
 arch/arm/mach-omap1/board-htcherald.c              |   12 ++---
 arch/arm/mach-omap1/board-innovator.c              |   18 ++++----
 arch/arm/mach-omap1/board-nokia770.c               |   18 ++++----
 arch/arm/mach-omap1/board-osk.c                    |   12 ++---
 arch/arm/mach-omap1/board-palmte.c                 |   18 ++++----
 arch/arm/mach-omap1/board-palmtt.c                 |   22 ++++-----
 arch/arm/mach-omap1/board-palmz71.c                |   20 ++++----
 arch/arm/mach-omap1/board-perseus2.c               |   16 +++----
 arch/arm/mach-omap1/board-sx1-mmc.c                |    6 +--
 arch/arm/mach-omap1/board-sx1.c                    |   22 ++++-----
 arch/arm/mach-omap1/board-voiceblue.c              |   16 +++----
 arch/arm/mach-omap1/clock.c                        |   12 ++---
 arch/arm/mach-omap1/clock.h                        |    2 +-
 arch/arm/mach-omap1/clock_data.c                   |   16 +++----
 arch/arm/mach-omap1/common.h                       |    2 +-
 arch/arm/mach-omap1/devices.c                      |   18 ++++----
 arch/arm/mach-omap1/dma.c                          |    6 +--
 arch/arm/mach-omap1/flash.c                        |    6 +--
 arch/arm/mach-omap1/fpga.c                         |    4 +-
 arch/arm/mach-omap1/i2c.c                          |    6 +--
 arch/arm/mach-omap1/id.c                           |    4 +-
 .../mach-omap1/include/mach-omap1/ams-delta-fiq.h  |    2 +-
 .../mach-omap1/include/mach-omap1/debug-macro.S    |    2 +-
 .../mach-omap1/include/mach-omap1/entry-macro.S    |    4 +-
 arch/arm/mach-omap1/include/mach-omap1/gpio.h      |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/hardware.h  |    4 +-
 arch/arm/mach-omap1/include/mach-omap1/irqs.h      |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/memory.h    |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/mtd-xip.h   |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/smp.h       |    2 +-
 arch/arm/mach-omap1/include/mach-omap1/timex.h     |    2 +-
 .../arm/mach-omap1/include/mach-omap1/uncompress.h |    2 +-
 arch/arm/mach-omap1/io.c                           |    6 +--
 arch/arm/mach-omap1/irq.c                          |    4 +-
 arch/arm/mach-omap1/lcd_dma.c                      |    6 +--
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    4 +-
 arch/arm/mach-omap1/leds-innovator.c               |    2 +-
 arch/arm/mach-omap1/leds-osk.c                     |    2 +-
 arch/arm/mach-omap1/leds.c                         |    2 +-
 arch/arm/mach-omap1/mailbox.c                      |    2 +-
 arch/arm/mach-omap1/mcbsp.c                        |   10 ++--
 arch/arm/mach-omap1/mux.c                          |    4 +-
 arch/arm/mach-omap1/ocpi.c                         |    2 +-
 arch/arm/mach-omap1/opp_data.c                     |    2 +-
 arch/arm/mach-omap1/pm.c                           |   18 ++++----
 arch/arm/mach-omap1/pm_bus.c                       |    4 +-
 arch/arm/mach-omap1/reset.c                        |    4 +-
 arch/arm/mach-omap1/serial.c                       |    6 +--
 arch/arm/mach-omap1/sram.S                         |    2 +-
 arch/arm/mach-omap1/time.c                         |    2 +-
 arch/arm/mach-omap1/timer.c                        |    4 +-
 arch/arm/mach-omap1/timer32k.c                     |    4 +-
 arch/arm/mach-omap1/usb.c                          |    4 +-
 arch/arm/mach-omap2/am35xx-emac.c                  |    4 +-
 arch/arm/mach-omap2/board-2430sdp.c                |   10 ++--
 arch/arm/mach-omap2/board-3430sdp.c                |   14 +++---
 arch/arm/mach-omap2/board-3630sdp.c                |    8 ++--
 arch/arm/mach-omap2/board-4430sdp.c                |   10 ++--
 arch/arm/mach-omap2/board-am3517crane.c            |    6 +--
 arch/arm/mach-omap2/board-am3517evm.c              |    8 ++--
 arch/arm/mach-omap2/board-apollon.c                |    8 ++--
 arch/arm/mach-omap2/board-cm-t35.c                 |   14 +++---
 arch/arm/mach-omap2/board-cm-t3517.c               |   10 ++--
 arch/arm/mach-omap2/board-devkit8000.c             |   14 +++---
 arch/arm/mach-omap2/board-flash.c                  |   10 ++--
 arch/arm/mach-omap2/board-flash.h                  |    2 +-
 arch/arm/mach-omap2/board-generic.c                |    4 +-
 arch/arm/mach-omap2/board-h4.c                     |   10 ++--
 arch/arm/mach-omap2/board-igep0020.c               |   10 ++--
 arch/arm/mach-omap2/board-ldp.c                    |   14 +++---
 arch/arm/mach-omap2/board-n8x0.c                   |   14 +++---
 arch/arm/mach-omap2/board-omap3beagle.c            |   12 ++---
 arch/arm/mach-omap2/board-omap3evm.c               |   12 ++---
 arch/arm/mach-omap2/board-omap3logic.c             |   14 +++---
 arch/arm/mach-omap2/board-omap3pandora.c           |   10 ++--
 arch/arm/mach-omap2/board-omap3stalker.c           |   14 +++---
 arch/arm/mach-omap2/board-omap3touchbook.c         |   12 ++---
 arch/arm/mach-omap2/board-omap4panda.c             |    8 ++--
 arch/arm/mach-omap2/board-overo.c                  |   16 +++----
 arch/arm/mach-omap2/board-rm680.c                  |   10 ++--
 arch/arm/mach-omap2/board-rx51-peripherals.c       |   14 +++---
 arch/arm/mach-omap2/board-rx51-video.c             |    6 +--
 arch/arm/mach-omap2/board-rx51.c                   |   12 ++---
 arch/arm/mach-omap2/board-ti8168evm.c              |    8 ++--
 arch/arm/mach-omap2/board-zoom-debugboard.c        |    6 +--
 arch/arm/mach-omap2/board-zoom-display.c           |    4 +-
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    4 +-
 arch/arm/mach-omap2/board-zoom.c                   |    6 +--
 arch/arm/mach-omap2/clkt2xxx_apll.c                |    4 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c                |    2 +-
 arch/arm/mach-omap2/clkt2xxx_dpllcore.c            |    6 +--
 arch/arm/mach-omap2/clkt2xxx_osc.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_sys.c                 |    2 +-
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c       |    8 ++--
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c             |    6 +--
 arch/arm/mach-omap2/clkt_clksel.c                  |    2 +-
 arch/arm/mach-omap2/clkt_dpll.c                    |    4 +-
 arch/arm/mach-omap2/clkt_iclk.c                    |    4 +-
 arch/arm/mach-omap2/clock.c                        |    6 +--
 arch/arm/mach-omap2/clock.h                        |    2 +-
 arch/arm/mach-omap2/clock2420_data.c               |    4 +-
 arch/arm/mach-omap2/clock2430.c                    |    4 +-
 arch/arm/mach-omap2/clock2430_data.c               |    4 +-
 arch/arm/mach-omap2/clock2xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock33xx_data.c               |    4 +-
 arch/arm/mach-omap2/clock34xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3517.c                    |    2 +-
 arch/arm/mach-omap2/clock36xx.c                    |    2 +-
 arch/arm/mach-omap2/clock3xxx.c                    |    4 +-
 arch/arm/mach-omap2/clock3xxx_data.c               |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c               |    4 +-
 arch/arm/mach-omap2/clockdomain.c                  |    2 +-
 arch/arm/mach-omap2/clockdomain.h                  |    6 +--
 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/cm2xxx_3xxx.c                  |    2 +-
 arch/arm/mach-omap2/cm33xx.c                       |    2 +-
 arch/arm/mach-omap2/common-board-devices.c         |    4 +-
 arch/arm/mach-omap2/common.c                       |    8 ++--
 arch/arm/mach-omap2/common.h                       |    2 +-
 arch/arm/mach-omap2/control.c                      |    4 +-
 arch/arm/mach-omap2/control.h                      |   10 ++--
 arch/arm/mach-omap2/cpuidle34xx.c                  |    4 +-
 arch/arm/mach-omap2/devices.c                      |   18 ++++----
 arch/arm/mach-omap2/display.c                      |    6 +--
 arch/arm/mach-omap2/dma.c                          |    6 +--
 arch/arm/mach-omap2/dpll3xxx.c                     |    4 +-
 arch/arm/mach-omap2/dpll44xx.c                     |    4 +-
 arch/arm/mach-omap2/drm.c                          |    4 +-
 arch/arm/mach-omap2/dsp.c                          |    4 +-
 arch/arm/mach-omap2/emu.c                          |    2 +-
 arch/arm/mach-omap2/gpio.c                         |    6 +--
 arch/arm/mach-omap2/gpmc-nand.c                    |    8 ++--
 arch/arm/mach-omap2/gpmc-onenand.c                 |    8 ++--
 arch/arm/mach-omap2/gpmc-smc91x.c                  |    6 +--
 arch/arm/mach-omap2/gpmc-smsc911x.c                |    6 +--
 arch/arm/mach-omap2/gpmc.c                         |    4 +-
 arch/arm/mach-omap2/hdq1w.c                        |    6 +--
 arch/arm/mach-omap2/hsmmc.c                        |   10 ++--
 arch/arm/mach-omap2/hwspinlock.c                   |    4 +-
 arch/arm/mach-omap2/i2c.c                          |    6 +--
 arch/arm/mach-omap2/id.c                           |    4 +-
 .../mach-omap2/include/mach-omap2/debug-macro.S    |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/gpio.h      |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/hardware.h  |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/irqs.h      |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/smp.h       |    2 +-
 arch/arm/mach-omap2/include/mach-omap2/timex.h     |    2 +-
 .../arm/mach-omap2/include/mach-omap2/uncompress.h |    2 +-
 arch/arm/mach-omap2/io.c                           |   14 +++---
 arch/arm/mach-omap2/iommu2.c                       |    2 +-
 arch/arm/mach-omap2/irq.c                          |    2 +-
 arch/arm/mach-omap2/mailbox.c                      |    4 +-
 arch/arm/mach-omap2/mcbsp.c                        |   10 ++--
 arch/arm/mach-omap2/msdi.c                         |    6 +--
 arch/arm/mach-omap2/mux.c                          |    2 +-
 arch/arm/mach-omap2/omap-hotplug.c                 |    2 +-
 arch/arm/mach-omap2/omap-iommu.c                   |    4 +-
 arch/arm/mach-omap2/omap-mpuss-lowpower.c          |    2 +-
 arch/arm/mach-omap2/omap-secure.c                  |    4 +-
 arch/arm/mach-omap2/omap-smp.c                     |    6 +--
 arch/arm/mach-omap2/omap-wakeupgen.c               |    4 +-
 arch/arm/mach-omap2/omap4-common.c                 |   12 ++---
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 ++--
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   24 +++++-----
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   24 +++++-----
 .../omap_hwmod_2xxx_3xxx_interconnect_data.c       |    4 +-
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |   12 ++---
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |    8 ++--
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |   16 +++----
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   28 ++++++------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   20 ++++----
 arch/arm/mach-omap2/omap_hwmod_common_data.c       |    2 +-
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |    2 +-
 arch/arm/mach-omap2/omap_opp_data.h                |    2 +-
 arch/arm/mach-omap2/omap_phy_internal.c            |    2 +-
 arch/arm/mach-omap2/opp.c                          |    2 +-
 arch/arm/mach-omap2/opp2420_data.c                 |    2 +-
 arch/arm/mach-omap2/opp2430_data.c                 |    2 +-
 arch/arm/mach-omap2/opp3xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/opp4xxx_data.c                 |    2 +-
 arch/arm/mach-omap2/pm-debug.c                     |    8 ++--
 arch/arm/mach-omap2/pm.c                           |    4 +-
 arch/arm/mach-omap2/pm24xx.c                       |   10 ++--
 arch/arm/mach-omap2/pm34xx.c                       |   10 ++--
 arch/arm/mach-omap2/powerdomain.c                  |    4 +-
 arch/arm/mach-omap2/powerdomain.h                  |    2 +-
 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c         |    2 +-
 arch/arm/mach-omap2/powerdomain33xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomain44xx.c              |    2 +-
 arch/arm/mach-omap2/powerdomains3xxx_data.c        |    2 +-
 arch/arm/mach-omap2/prcm.c                         |    4 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.c                 |    6 +--
 arch/arm/mach-omap2/prm33xx.c                      |    2 +-
 arch/arm/mach-omap2/prm44xx.c                      |    6 +--
 arch/arm/mach-omap2/prm_common.c                   |    6 +--
 arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h |    2 +-
 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h  |    2 +-
 arch/arm/mach-omap2/sdram-nokia.c                  |    4 +-
 arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h     |    2 +-
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    2 +-
 arch/arm/mach-omap2/sdrc.c                         |    6 +--
 arch/arm/mach-omap2/sdrc.h                         |    2 +-
 arch/arm/mach-omap2/sdrc2xxx.c                     |    8 ++--
 arch/arm/mach-omap2/serial.c                       |   12 ++---
 arch/arm/mach-omap2/sleep24xx.S                    |    2 +-
 arch/arm/mach-omap2/sleep34xx.S                    |    4 +-
 arch/arm/mach-omap2/sleep44xx.S                    |    4 +-
 arch/arm/mach-omap2/sr_device.c                    |    2 +-
 arch/arm/mach-omap2/sram242x.S                     |    2 +-
 arch/arm/mach-omap2/sram243x.S                     |    2 +-
 arch/arm/mach-omap2/sram34xx.S                     |    2 +-
 arch/arm/mach-omap2/timer.c                        |    8 ++--
 arch/arm/mach-omap2/twl-common.c                   |    4 +-
 arch/arm/mach-omap2/twl-common.h                   |    2 +-
 arch/arm/mach-omap2/usb-host.c                     |    8 ++--
 arch/arm/mach-omap2/usb-musb.c                     |   10 ++--
 arch/arm/mach-omap2/usb-tusb6010.c                 |    2 +-
 arch/arm/mach-omap2/vc.c                           |    2 +-
 arch/arm/mach-omap2/voltage.h                      |    2 +-
 arch/arm/mach-omap2/voltagedomains3xxx_data.c      |    2 +-
 arch/arm/mach-omap2/wd_timer.c                     |    2 +-
 arch/arm/mach-omap2/wd_timer.h                     |    2 +-
 arch/arm/mach-orion5x/addr-map.c                   |    4 +-
 arch/arm/mach-orion5x/common.c                     |   16 +++----
 arch/arm/mach-orion5x/d2net-setup.c                |    2 +-
 arch/arm/mach-orion5x/db88f5281-setup.c            |    4 +-
 arch/arm/mach-orion5x/dns323-setup.c               |    2 +-
 arch/arm/mach-orion5x/edmini_v2-setup.c            |    2 +-
 .../include/mach-orion5x/bridge-regs.h             |    2 +-
 .../include/mach-orion5x/debug-macro.S             |    2 +-
 .../include/mach-orion5x/entry-macro.S             |    2 +-
 arch/arm/mach-orion5x/include/mach-orion5x/gpio.h  |    2 +-
 arch/arm/mach-orion5x/include/mach-orion5x/io.h    |    2 +-
 .../mach-orion5x/include/mach-orion5x/uncompress.h |    2 +-
 arch/arm/mach-orion5x/irq.c                        |    4 +-
 arch/arm/mach-orion5x/kurobox_pro-setup.c          |    4 +-
 arch/arm/mach-orion5x/ls-chl-setup.c               |    2 +-
 arch/arm/mach-orion5x/ls_hgl-setup.c               |    2 +-
 arch/arm/mach-orion5x/lsmini-setup.c               |    2 +-
 arch/arm/mach-orion5x/mpp.c                        |    4 +-
 arch/arm/mach-orion5x/mss2-setup.c                 |    4 +-
 arch/arm/mach-orion5x/mv2120-setup.c               |    2 +-
 arch/arm/mach-orion5x/net2big-setup.c              |    2 +-
 arch/arm/mach-orion5x/pci.c                        |    6 +--
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c       |    2 +-
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c        |    2 +-
 arch/arm/mach-orion5x/rd88f5182-setup.c            |    2 +-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c       |    2 +-
 arch/arm/mach-orion5x/terastation_pro2-setup.c     |    2 +-
 arch/arm/mach-orion5x/ts209-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts409-setup.c                |    2 +-
 arch/arm/mach-orion5x/ts78xx-setup.c               |    2 +-
 arch/arm/mach-orion5x/tsx09-common.c               |    2 +-
 arch/arm/mach-orion5x/wnr854t-setup.c              |    2 +-
 arch/arm/mach-orion5x/wrt350n-v2-setup.c           |    2 +-
 arch/arm/mach-picoxcell/common.c                   |    4 +-
 .../include/mach-picoxcell/debug-macro.S           |    4 +-
 .../include/mach-picoxcell/hardware.h              |    2 +-
 arch/arm/mach-pnx4008/clock.c                      |    4 +-
 arch/arm/mach-pnx4008/core.c                       |    8 ++--
 arch/arm/mach-pnx4008/dma.c                        |    6 +--
 arch/arm/mach-pnx4008/gpio.c                       |    6 +--
 arch/arm/mach-pnx4008/i2c.c                        |    4 +-
 .../mach-pnx4008/include/mach-pnx4008/hardware.h   |    2 +-
 arch/arm/mach-pnx4008/irq.c                        |    4 +-
 arch/arm/mach-pnx4008/pm.c                         |    6 +--
 arch/arm/mach-pnx4008/serial.c                     |    8 ++--
 arch/arm/mach-pnx4008/sleep.S                      |    2 +-
 arch/arm/mach-pnx4008/time.c                       |    2 +-
 arch/arm/mach-pnx4008/time.h                       |    2 +-
 arch/arm/mach-prima2/clock.c                       |    2 +-
 .../mach-prima2/include/mach-prima2/debug-macro.S  |    4 +-
 .../mach-prima2/include/mach-prima2/entry-macro.S  |    2 +-
 .../arm/mach-prima2/include/mach-prima2/hardware.h |    2 +-
 .../mach-prima2/include/mach-prima2/uncompress.h   |    4 +-
 arch/arm/mach-prima2/irq.c                         |    2 +-
 arch/arm/mach-prima2/lluart.c                      |    4 +-
 arch/arm/mach-prima2/timer.c                       |    2 +-
 arch/arm/mach-pxa/am200epd.c                       |    6 +--
 arch/arm/mach-pxa/am300epd.c                       |    6 +--
 arch/arm/mach-pxa/balloon3.c                       |   18 ++++----
 arch/arm/mach-pxa/capc7117.c                       |    4 +-
 arch/arm/mach-pxa/clock-pxa2xx.c                   |    2 +-
 arch/arm/mach-pxa/clock-pxa3xx.c                   |    4 +-
 arch/arm/mach-pxa/cm-x255.c                        |    2 +-
 arch/arm/mach-pxa/cm-x270.c                        |    6 +--
 arch/arm/mach-pxa/cm-x2xx.c                        |   10 ++--
 arch/arm/mach-pxa/cm-x300.c                        |   16 +++----
 arch/arm/mach-pxa/colibri-evalboard.c              |   12 ++---
 arch/arm/mach-pxa/colibri-pxa270-income.c          |   12 ++---
 arch/arm/mach-pxa/colibri-pxa270.c                 |    6 +--
 arch/arm/mach-pxa/colibri-pxa300.c                 |   10 ++--
 arch/arm/mach-pxa/colibri-pxa320.c                 |   14 +++---
 arch/arm/mach-pxa/colibri-pxa3xx.c                 |   14 +++---
 arch/arm/mach-pxa/corgi.c                          |   14 +++---
 arch/arm/mach-pxa/corgi_pm.c                       |    8 ++--
 arch/arm/mach-pxa/cpufreq-pxa2xx.c                 |    4 +-
 arch/arm/mach-pxa/cpufreq-pxa3xx.c                 |    2 +-
 arch/arm/mach-pxa/csb726.c                         |   12 ++---
 arch/arm/mach-pxa/devices.c                        |   24 +++++-----
 arch/arm/mach-pxa/em-x270.c                        |   16 +++----
 arch/arm/mach-pxa/eseries.c                        |   14 +++---
 arch/arm/mach-pxa/ezx.c                            |   12 ++---
 arch/arm/mach-pxa/generic.c                        |    8 ++--
 arch/arm/mach-pxa/gumstix.c                        |   10 ++--
 arch/arm/mach-pxa/h5000.c                          |    8 ++--
 arch/arm/mach-pxa/himalaya.c                       |    2 +-
 arch/arm/mach-pxa/hx4700.c                         |    8 ++--
 arch/arm/mach-pxa/icontrol.c                       |    4 +-
 arch/arm/mach-pxa/idp.c                            |   12 ++---
 arch/arm/mach-pxa/include/mach-pxa/colibri.h       |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/dma.h           |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/gpio.h          |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/h5000.h         |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/hardware.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/magician.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mainstone.h     |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa25x.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa27x.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa2xx.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa300.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa320.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa3xx.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp-pxa930.h    |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mfp.h           |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/mtd-xip.h       |    2 +-
 .../mach-pxa/include/mach-pxa/pcm990_baseboard.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa25x.h        |    8 ++--
 arch/arm/mach-pxa/include/mach-pxa/pxa27x.h        |    8 ++--
 arch/arm/mach-pxa/include/mach-pxa/pxa2xx-regs.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa300.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa320.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx-regs.h   |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa3xx.h        |    6 +--
 arch/arm/mach-pxa/include/mach-pxa/pxa930.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxa95x.h        |    4 +-
 arch/arm/mach-pxa/include/mach-pxa/pxafb.h         |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-ac97.h     |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-lcd.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-ost.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-rtc.h      |    2 +-
 arch/arm/mach-pxa/include/mach-pxa/regs-u2d.h      |    2 +-
 arch/arm/mach-pxa/irq.c                            |    4 +-
 arch/arm/mach-pxa/leds-idp.c                       |    6 +--
 arch/arm/mach-pxa/leds-lubbock.c                   |    6 +--
 arch/arm/mach-pxa/leds-mainstone.c                 |    6 +--
 arch/arm/mach-pxa/littleton.c                      |   14 +++---
 arch/arm/mach-pxa/lpd270.c                         |   18 ++++----
 arch/arm/mach-pxa/lubbock.c                        |   20 ++++----
 arch/arm/mach-pxa/magician.c                       |   14 +++---
 arch/arm/mach-pxa/mainstone.c                      |   20 ++++----
 arch/arm/mach-pxa/mfp-pxa2xx.c                     |    4 +-
 arch/arm/mach-pxa/mfp-pxa3xx.c                     |    6 +--
 arch/arm/mach-pxa/mioa701.c                        |   22 ++++-----
 arch/arm/mach-pxa/mp900.c                          |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                        |   12 ++---
 arch/arm/mach-pxa/palm27x.c                        |   16 +++----
 arch/arm/mach-pxa/palmld.c                         |   18 ++++----
 arch/arm/mach-pxa/palmt5.c                         |   20 ++++----
 arch/arm/mach-pxa/palmtc.c                         |   14 +++---
 arch/arm/mach-pxa/palmte2.c                        |   16 +++----
 arch/arm/mach-pxa/palmtreo.c                       |   28 ++++++------
 arch/arm/mach-pxa/palmtx.c                         |   20 ++++----
 arch/arm/mach-pxa/palmz72.c                        |   26 +++++------
 arch/arm/mach-pxa/pcm027.c                         |    4 +-
 arch/arm/mach-pxa/pcm990-baseboard.c               |   14 +++---
 arch/arm/mach-pxa/pm.c                             |    2 +-
 arch/arm/mach-pxa/poodle.c                         |   14 +++---
 arch/arm/mach-pxa/pxa25x.c                         |   14 +++---
 arch/arm/mach-pxa/pxa27x.c                         |   16 +++----
 arch/arm/mach-pxa/pxa2xx.c                         |   10 ++--
 arch/arm/mach-pxa/pxa300.c                         |    2 +-
 arch/arm/mach-pxa/pxa320.c                         |    2 +-
 arch/arm/mach-pxa/pxa3xx-ulpi.c                    |    6 +--
 arch/arm/mach-pxa/pxa3xx.c                         |   16 +++----
 arch/arm/mach-pxa/pxa930.c                         |    2 +-
 arch/arm/mach-pxa/pxa95x.c                         |   12 ++---
 arch/arm/mach-pxa/raumfeld.c                       |   10 ++--
 arch/arm/mach-pxa/reset.c                          |    4 +-
 arch/arm/mach-pxa/saar.c                           |    4 +-
 arch/arm/mach-pxa/saarb.c                          |   10 ++--
 arch/arm/mach-pxa/sharpsl_pm.c                     |    8 ++--
 arch/arm/mach-pxa/sleep.S                          |    6 +--
 arch/arm/mach-pxa/smemc.c                          |    4 +-
 arch/arm/mach-pxa/spitz.c                          |   20 ++++----
 arch/arm/mach-pxa/spitz_pm.c                       |    8 ++--
 arch/arm/mach-pxa/standby.S                        |    4 +-
 arch/arm/mach-pxa/stargate2.c                      |   10 ++--
 arch/arm/mach-pxa/tavorevb.c                       |    6 +--
 arch/arm/mach-pxa/tavorevb3.c                      |    2 +-
 arch/arm/mach-pxa/time.c                           |    4 +-
 arch/arm/mach-pxa/tosa-bt.c                        |    2 +-
 arch/arm/mach-pxa/tosa.c                           |   18 ++++----
 arch/arm/mach-pxa/trizeps4.c                       |   16 +++----
 arch/arm/mach-pxa/viper.c                          |   12 ++---
 arch/arm/mach-pxa/vpac270.c                        |   18 ++++----
 arch/arm/mach-pxa/xcep.c                           |    6 +--
 arch/arm/mach-pxa/z2.c                             |   14 +++---
 arch/arm/mach-pxa/zeus.c                           |   24 +++++-----
 arch/arm/mach-pxa/zylonite.c                       |   16 +++----
 arch/arm/mach-pxa/zylonite_pxa300.c                |    4 +-
 arch/arm/mach-pxa/zylonite_pxa320.c                |    4 +-
 arch/arm/mach-realview/core.c                      |   10 ++--
 .../mach-realview/include/mach-realview/board-eb.h |    2 +-
 .../include/mach-realview/board-pb1176.h           |    2 +-
 .../include/mach-realview/board-pb11mp.h           |    2 +-
 .../include/mach-realview/board-pba8.h             |    2 +-
 .../include/mach-realview/board-pbx.h              |    2 +-
 .../mach-realview/include/mach-realview/clkdev.h   |    2 +-
 .../arm/mach-realview/include/mach-realview/irqs.h |   10 ++--
 .../include/mach-realview/uncompress.h             |   12 ++---
 arch/arm/mach-realview/platsmp.c                   |    8 ++--
 arch/arm/mach-realview/realview_eb.c               |    6 +--
 arch/arm/mach-realview/realview_pb1176.c           |    6 +--
 arch/arm/mach-realview/realview_pb11mp.c           |    6 +--
 arch/arm/mach-realview/realview_pba8.c             |    6 +--
 arch/arm/mach-realview/realview_pbx.c              |    6 +--
 arch/arm/mach-rpc/dma.c                            |    2 +-
 arch/arm/mach-rpc/ecard.c                          |    2 +-
 arch/arm/mach-rpc/fiq.S                            |    4 +-
 arch/arm/mach-rpc/include/mach-rpc/entry-macro.S   |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/hardware.h      |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/io.h            |    2 +-
 arch/arm/mach-rpc/include/mach-rpc/uncompress.h    |    2 +-
 arch/arm/mach-rpc/riscpc.c                         |    2 +-
 arch/arm/mach-rpc/time.c                           |    2 +-
 arch/arm/mach-s3c2410/cpu-freq.c                   |    8 ++--
 arch/arm/mach-s3c2410/pll.c                        |    4 +-
 arch/arm/mach-s3c2412/cpu-freq.c                   |   10 ++--
 arch/arm/mach-s3c2412/gpio.c                       |    6 +--
 arch/arm/mach-s3c2440/dsc.c                        |   10 ++--
 arch/arm/mach-s3c2440/s3c2440-cpufreq.c            |   10 ++--
 arch/arm/mach-s3c2440/s3c2440-pll-12000000.c       |    4 +-
 arch/arm/mach-s3c2440/s3c2440-pll-16934400.c       |    4 +-
 arch/arm/mach-s3c24xx/bast-ide.c                   |    6 +--
 arch/arm/mach-s3c24xx/bast-irq.c                   |   10 ++--
 arch/arm/mach-s3c24xx/clock-s3c2412.c              |   14 +++---
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |   16 +++----
 arch/arm/mach-s3c24xx/clock-s3c2440.c              |   10 ++--
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |   14 +++---
 arch/arm/mach-s3c24xx/clock-s3c244x.c              |    8 ++--
 arch/arm/mach-s3c24xx/common-s3c2443.c             |   10 ++--
 arch/arm/mach-s3c24xx/common-smdk.c                |   16 +++----
 arch/arm/mach-s3c24xx/common.c                     |   30 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2410.c                |   30 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2412.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/dma-s3c2440.c                |   26 +++++------
 arch/arm/mach-s3c24xx/dma-s3c2443.c                |   24 +++++-----
 arch/arm/mach-s3c24xx/h1940-bluetooth.c            |    8 ++--
 .../include/mach-s3c24xx/debug-macro.S             |    8 ++--
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/dma.h   |    2 +-
 .../include/mach-s3c24xx/entry-macro.S             |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/fb.h    |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-fns.h   |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/gpio-track.h |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gpio.h  |    4 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/gta02.h |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/hardware.h   |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/io.h    |    2 +-
 arch/arm/mach-s3c24xx/include/mach-s3c24xx/map.h   |    4 +-
 .../mach-s3c24xx/include/mach-s3c24xx/regs-gpio.h  |    2 +-
 .../mach-s3c24xx/include/mach-s3c24xx/uncompress.h |    6 +--
 .../mach-s3c24xx/include/mach-s3c24xx/vr1000-map.h |    2 +-
 arch/arm/mach-s3c24xx/irq-pm.c                     |    6 +--
 arch/arm/mach-s3c24xx/irq-s3c2412.c                |   14 +++---
 arch/arm/mach-s3c24xx/irq-s3c2416.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c2440.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c2443.c                |   12 ++---
 arch/arm/mach-s3c24xx/irq-s3c244x.c                |   12 ++---
 arch/arm/mach-s3c24xx/mach-amlm5900.c              |   18 ++++----
 arch/arm/mach-s3c24xx/mach-anubis.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-at2440evb.c             |   24 +++++-----
 arch/arm/mach-s3c24xx/mach-bast.c                  |   36 +++++++--------
 arch/arm/mach-s3c24xx/mach-gta02.c                 |   38 ++++++++--------
 arch/arm/mach-s3c24xx/mach-h1940.c                 |   46 +++++++++----------
 arch/arm/mach-s3c24xx/mach-jive.c                  |   30 ++++++------
 arch/arm/mach-s3c24xx/mach-mini2440.c              |   32 ++++++-------
 arch/arm/mach-s3c24xx/mach-n30.c                   |   26 +++++------
 arch/arm/mach-s3c24xx/mach-nexcoder.c              |   22 ++++-----
 arch/arm/mach-s3c24xx/mach-osiris-dvs.c            |    2 +-
 arch/arm/mach-s3c24xx/mach-osiris.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-otom.c                  |   18 ++++----
 arch/arm/mach-s3c24xx/mach-qt2410.c                |   28 ++++++------
 arch/arm/mach-s3c24xx/mach-rx1950.c                |   34 +++++++-------
 arch/arm/mach-s3c24xx/mach-rx3715.c                |   22 ++++-----
 arch/arm/mach-s3c24xx/mach-smdk2410.c              |   12 ++---
 arch/arm/mach-s3c24xx/mach-smdk2413.c              |   34 +++++++-------
 arch/arm/mach-s3c24xx/mach-smdk2416.c              |   42 ++++++++---------
 arch/arm/mach-s3c24xx/mach-smdk2440.c              |   26 +++++------
 arch/arm/mach-s3c24xx/mach-smdk2443.c              |   26 +++++------
 arch/arm/mach-s3c24xx/mach-tct_hammer.c            |   10 ++--
 arch/arm/mach-s3c24xx/mach-vr1000.c                |   26 +++++------
 arch/arm/mach-s3c24xx/mach-vstms.c                 |   26 +++++------
 arch/arm/mach-s3c24xx/pm-h1940.S                   |    6 +--
 arch/arm/mach-s3c24xx/pm-s3c2410.c                 |   10 ++--
 arch/arm/mach-s3c24xx/pm-s3c2412.c                 |   14 +++---
 arch/arm/mach-s3c24xx/pm-s3c2416.c                 |    8 ++--
 arch/arm/mach-s3c24xx/pm.c                         |   14 +++---
 arch/arm/mach-s3c24xx/s3c2410.c                    |   28 ++++++------
 arch/arm/mach-s3c24xx/s3c2412.c                    |   36 +++++++--------
 arch/arm/mach-s3c24xx/s3c2416.c                    |   34 +++++++-------
 arch/arm/mach-s3c24xx/s3c2440.c                    |   16 +++----
 arch/arm/mach-s3c24xx/s3c2442.c                    |   18 ++++----
 arch/arm/mach-s3c24xx/s3c2443.c                    |   26 +++++------
 arch/arm/mach-s3c24xx/s3c244x.c                    |   34 +++++++-------
 arch/arm/mach-s3c24xx/setup-i2c.c                  |    8 ++--
 arch/arm/mach-s3c24xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                  |    6 +--
 arch/arm/mach-s3c24xx/setup-ts.c                   |    2 +-
 arch/arm/mach-s3c24xx/simtec-audio.c               |   14 +++---
 arch/arm/mach-s3c24xx/simtec-nor.c                 |    6 +--
 arch/arm/mach-s3c24xx/simtec-pm.c                  |   10 ++--
 arch/arm/mach-s3c24xx/simtec-usb.c                 |   10 ++--
 arch/arm/mach-s3c24xx/sleep-s3c2410.S              |   12 ++---
 arch/arm/mach-s3c24xx/sleep-s3c2412.S              |    6 +--
 arch/arm/mach-s3c24xx/sleep.S                      |   12 ++---
 arch/arm/mach-s3c64xx/clock.c                      |   24 +++++-----
 arch/arm/mach-s3c64xx/common.c                     |   28 ++++++------
 arch/arm/mach-s3c64xx/cpuidle.c                    |    6 +--
 arch/arm/mach-s3c64xx/dev-audio.c                  |   12 ++---
 arch/arm/mach-s3c64xx/dev-uart.c                   |    6 +--
 arch/arm/mach-s3c64xx/dma.c                        |    8 ++--
 .../include/mach-s3c64xx/debug-macro.S             |    6 +--
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/dma.h   |    4 +-
 arch/arm/mach-s3c64xx/include/mach-s3c64xx/map.h   |    4 +-
 .../mach-s3c64xx/include/mach-s3c64xx/pm-core.h    |    2 +-
 .../mach-s3c64xx/include/mach-s3c64xx/uncompress.h |    4 +-
 arch/arm/mach-s3c64xx/irq-pm.c                     |   12 ++---
 arch/arm/mach-s3c64xx/mach-anw6410.c               |   22 ++++-----
 arch/arm/mach-s3c64xx/mach-crag6410-module.c       |    4 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |   48 ++++++++++----------
 arch/arm/mach-s3c64xx/mach-hmt.c                   |   20 ++++----
 arch/arm/mach-s3c64xx/mach-mini6410.c              |   26 +++++------
 arch/arm/mach-s3c64xx/mach-ncp.c                   |   18 ++++----
 arch/arm/mach-s3c64xx/mach-real6410.c              |   26 +++++------
 arch/arm/mach-s3c64xx/mach-smartq.c                |   28 ++++++------
 arch/arm/mach-s3c64xx/mach-smartq5.c               |   16 +++----
 arch/arm/mach-s3c64xx/mach-smartq7.c               |   16 +++----
 arch/arm/mach-s3c64xx/mach-smdk6400.c              |   14 +++---
 arch/arm/mach-s3c64xx/mach-smdk6410.c              |   40 ++++++++--------
 arch/arm/mach-s3c64xx/pm.c                         |   26 +++++------
 arch/arm/mach-s3c64xx/s3c6400.c                    |   20 ++++----
 arch/arm/mach-s3c64xx/s3c6410.c                    |   26 +++++------
 arch/arm/mach-s3c64xx/setup-fb-24bpp.c             |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s3c64xx/setup-ide.c                  |    8 ++--
 arch/arm/mach-s3c64xx/setup-keypad.c               |    4 +-
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c           |    4 +-
 arch/arm/mach-s3c64xx/setup-spi.c                  |    2 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |   10 ++--
 arch/arm/mach-s3c64xx/sleep.S                      |    4 +-
 arch/arm/mach-s5p64x0/clock-s5p6440.c              |   22 ++++-----
 arch/arm/mach-s5p64x0/clock-s5p6450.c              |   22 ++++-----
 arch/arm/mach-s5p64x0/clock.c                      |   20 ++++----
 arch/arm/mach-s5p64x0/common.c                     |   32 ++++++-------
 arch/arm/mach-s5p64x0/dev-audio.c                  |   10 ++--
 arch/arm/mach-s5p64x0/dma.c                        |   14 +++---
 arch/arm/mach-s5p64x0/gpiolib.c                    |   16 +++----
 .../include/mach-s5p64x0/debug-macro.S             |    8 ++--
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/dma.h   |    2 +-
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/irqs.h  |    2 +-
 arch/arm/mach-s5p64x0/include/mach-s5p64x0/map.h   |    4 +-
 .../mach-s5p64x0/include/mach-s5p64x0/pm-core.h    |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-clock.h |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-gpio.h  |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/regs-irq.h   |    2 +-
 .../mach-s5p64x0/include/mach-s5p64x0/uncompress.h |    6 +--
 arch/arm/mach-s5p64x0/irq-pm.c                     |    6 +--
 arch/arm/mach-s5p64x0/mach-smdk6440.c              |   40 ++++++++--------
 arch/arm/mach-s5p64x0/mach-smdk6450.c              |   40 ++++++++--------
 arch/arm/mach-s5p64x0/pm.c                         |   12 ++---
 arch/arm/mach-s5p64x0/setup-fb-24bpp.c             |    6 +--
 arch/arm/mach-s5p64x0/setup-i2c0.c                 |    6 +--
 arch/arm/mach-s5p64x0/setup-i2c1.c                 |    6 +--
 arch/arm/mach-s5p64x0/setup-sdhci-gpio.c           |   10 ++--
 arch/arm/mach-s5p64x0/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pc100/clock.c                      |   18 ++++----
 arch/arm/mach-s5pc100/common.c                     |   30 ++++++------
 arch/arm/mach-s5pc100/dev-audio.c                  |   10 ++--
 arch/arm/mach-s5pc100/dma.c                        |   10 ++--
 .../include/mach-s5pc100/debug-macro.S             |    6 +--
 arch/arm/mach-s5pc100/include/mach-s5pc100/dma.h   |    2 +-
 arch/arm/mach-s5pc100/include/mach-s5pc100/irqs.h  |    2 +-
 arch/arm/mach-s5pc100/include/mach-s5pc100/map.h   |    4 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-clock.h |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-gpio.h  |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/regs-irq.h   |    2 +-
 .../mach-s5pc100/include/mach-s5pc100/uncompress.h |    4 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c              |   34 +++++++-------
 arch/arm/mach-s5pc100/setup-fb-24bpp.c             |    6 +--
 arch/arm/mach-s5pc100/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pc100/setup-ide.c                  |    4 +-
 arch/arm/mach-s5pc100/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c           |    6 +--
 arch/arm/mach-s5pc100/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/clock.c                      |   18 ++++----
 arch/arm/mach-s5pv210/common.c                     |   30 ++++++------
 arch/arm/mach-s5pv210/dev-audio.c                  |   12 ++---
 arch/arm/mach-s5pv210/dma.c                        |   10 ++--
 .../include/mach-s5pv210/debug-macro.S             |    6 +--
 arch/arm/mach-s5pv210/include/mach-s5pv210/dma.h   |    2 +-
 arch/arm/mach-s5pv210/include/mach-s5pv210/irqs.h  |    2 +-
 arch/arm/mach-s5pv210/include/mach-s5pv210/map.h   |    4 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-clock.h |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-gpio.h  |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/regs-irq.h   |    2 +-
 .../mach-s5pv210/include/mach-s5pv210/uncompress.h |    4 +-
 arch/arm/mach-s5pv210/mach-aquila.c                |   24 +++++-----
 arch/arm/mach-s5pv210/mach-goni.c                  |   32 ++++++-------
 arch/arm/mach-s5pv210/mach-smdkc110.c              |   22 ++++-----
 arch/arm/mach-s5pv210/mach-smdkv210.c              |   40 ++++++++--------
 arch/arm/mach-s5pv210/mach-torbreck.c              |   16 +++----
 arch/arm/mach-s5pv210/pm.c                         |   10 ++--
 arch/arm/mach-s5pv210/setup-fb-24bpp.c             |    8 ++--
 arch/arm/mach-s5pv210/setup-fimc.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c0.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c1.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-i2c2.c                 |    4 +-
 arch/arm/mach-s5pv210/setup-ide.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-keypad.c               |    2 +-
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c           |    6 +--
 arch/arm/mach-s5pv210/setup-spi.c                  |    2 +-
 arch/arm/mach-s5pv210/setup-usb-phy.c              |   10 ++--
 arch/arm/mach-sa1100/assabet.c                     |    8 ++--
 arch/arm/mach-sa1100/badge4.c                      |    6 +--
 arch/arm/mach-sa1100/cerf.c                        |    8 ++--
 arch/arm/mach-sa1100/clock.c                       |    2 +-
 arch/arm/mach-sa1100/collie.c                      |    8 ++--
 arch/arm/mach-sa1100/cpu-sa1100.c                  |    2 +-
 arch/arm/mach-sa1100/cpu-sa1110.c                  |    2 +-
 arch/arm/mach-sa1100/generic.c                     |    4 +-
 arch/arm/mach-sa1100/h3100.c                       |    4 +-
 arch/arm/mach-sa1100/h3600.c                       |    4 +-
 arch/arm/mach-sa1100/h3xxx.c                       |    2 +-
 arch/arm/mach-sa1100/hackkit.c                     |    4 +-
 arch/arm/mach-sa1100/include/mach-sa1100/SA-1101.h |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/badge4.h  |    2 +-
 .../mach-sa1100/include/mach-sa1100/debug-macro.S  |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/gpio.h    |    2 +-
 arch/arm/mach-sa1100/include/mach-sa1100/mtd-xip.h |    2 +-
 .../mach-sa1100/include/mach-sa1100/nanoengine.h   |    2 +-
 arch/arm/mach-sa1100/irq.c                         |    4 +-
 arch/arm/mach-sa1100/jornada720.c                  |    4 +-
 arch/arm/mach-sa1100/jornada720_ssp.c              |    4 +-
 arch/arm/mach-sa1100/lart.c                        |    6 +--
 arch/arm/mach-sa1100/leds-assabet.c                |    4 +-
 arch/arm/mach-sa1100/leds-badge4.c                 |    2 +-
 arch/arm/mach-sa1100/leds-cerf.c                   |    2 +-
 arch/arm/mach-sa1100/leds-hackkit.c                |    2 +-
 arch/arm/mach-sa1100/leds-lart.c                   |    2 +-
 arch/arm/mach-sa1100/nanoengine.c                  |    6 +--
 arch/arm/mach-sa1100/neponset.c                    |    8 ++--
 arch/arm/mach-sa1100/pci-nanoengine.c              |    4 +-
 arch/arm/mach-sa1100/pleb.c                        |    4 +-
 arch/arm/mach-sa1100/pm.c                          |    2 +-
 arch/arm/mach-sa1100/shannon.c                     |    8 ++--
 arch/arm/mach-sa1100/simpad.c                      |    8 ++--
 arch/arm/mach-sa1100/sleep.S                       |    2 +-
 arch/arm/mach-sa1100/ssp.c                         |    4 +-
 arch/arm/mach-sa1100/time.c                        |    4 +-
 arch/arm/mach-shmobile/board-ag5evm.c              |    8 ++--
 arch/arm/mach-shmobile/board-ap4evb.c              |    6 +--
 arch/arm/mach-shmobile/board-armadillo800eva.c     |    6 +--
 arch/arm/mach-shmobile/board-bonito.c              |    6 +--
 arch/arm/mach-shmobile/board-g3evm.c               |    6 +--
 arch/arm/mach-shmobile/board-g4evm.c               |    6 +--
 arch/arm/mach-shmobile/board-kota2.c               |    8 ++--
 arch/arm/mach-shmobile/board-kzm9d.c               |    4 +-
 arch/arm/mach-shmobile/board-kzm9g.c               |    6 +--
 arch/arm/mach-shmobile/board-mackerel.c            |    6 +--
 arch/arm/mach-shmobile/board-marzen.c              |    8 ++--
 arch/arm/mach-shmobile/clock-emev2.c               |    2 +-
 arch/arm/mach-shmobile/clock-r8a7740.c             |    4 +-
 arch/arm/mach-shmobile/clock-r8a7779.c             |    2 +-
 arch/arm/mach-shmobile/clock-sh7367.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7372.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh7377.c              |    2 +-
 arch/arm/mach-shmobile/clock-sh73a0.c              |    2 +-
 arch/arm/mach-shmobile/common.c                    |    2 +-
 arch/arm/mach-shmobile/console.c                   |    2 +-
 arch/arm/mach-shmobile/hotplug.c                   |    2 +-
 .../mach-shmobile/include/mach-shmobile/r8a7740.h  |    2 +-
 .../mach-shmobile/include/mach-shmobile/sh7372.h   |    2 +-
 .../mach-shmobile/include/mach-shmobile/zboot.h    |    2 +-
 arch/arm/mach-shmobile/intc-r8a7740.c              |    4 +-
 arch/arm/mach-shmobile/intc-r8a7779.c              |    6 +--
 arch/arm/mach-shmobile/intc-sh7367.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7372.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh7377.c               |    4 +-
 arch/arm/mach-shmobile/intc-sh73a0.c               |    6 +--
 arch/arm/mach-shmobile/pfc-r8a7740.c               |    4 +-
 arch/arm/mach-shmobile/pfc-r8a7779.c               |    2 +-
 arch/arm/mach-shmobile/pfc-sh7367.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh7372.c                |    4 +-
 arch/arm/mach-shmobile/pfc-sh7377.c                |    2 +-
 arch/arm/mach-shmobile/pfc-sh73a0.c                |    4 +-
 arch/arm/mach-shmobile/platsmp.c                   |    4 +-
 arch/arm/mach-shmobile/pm-r8a7740.c                |    2 +-
 arch/arm/mach-shmobile/pm-r8a7779.c                |    4 +-
 arch/arm/mach-shmobile/pm-rmobile.c                |    2 +-
 arch/arm/mach-shmobile/pm-sh7372.c                 |    6 +--
 arch/arm/mach-shmobile/setup-emev2.c               |    8 ++--
 arch/arm/mach-shmobile/setup-r8a7740.c             |   10 ++--
 arch/arm/mach-shmobile/setup-r8a7779.c             |    8 ++--
 arch/arm/mach-shmobile/setup-sh7367.c              |    6 +--
 arch/arm/mach-shmobile/setup-sh7372.c              |   10 ++--
 arch/arm/mach-shmobile/setup-sh7377.c              |    6 +--
 arch/arm/mach-shmobile/setup-sh73a0.c              |   10 ++--
 arch/arm/mach-shmobile/smp-emev2.c                 |    4 +-
 arch/arm/mach-shmobile/smp-r8a7779.c               |    4 +-
 arch/arm/mach-shmobile/smp-sh73a0.c                |    2 +-
 .../include/mach-spear13xx/debug-macro.S           |    2 +-
 .../mach-spear13xx/include/mach-spear13xx/gpio.h   |    2 +-
 .../mach-spear13xx/include/mach-spear13xx/timex.h  |    2 +-
 .../include/mach-spear13xx/uncompress.h            |    2 +-
 arch/arm/mach-spear13xx/platsmp.c                  |    2 +-
 arch/arm/mach-spear13xx/spear1310.c                |    4 +-
 arch/arm/mach-spear13xx/spear1340.c                |    6 +--
 arch/arm/mach-spear13xx/spear13xx.c                |    6 +--
 .../include/mach-spear3xx/debug-macro.S            |    2 +-
 .../arm/mach-spear3xx/include/mach-spear3xx/gpio.h |    2 +-
 .../include/mach-spear3xx/misc_regs.h              |    2 +-
 .../mach-spear3xx/include/mach-spear3xx/timex.h    |    2 +-
 .../include/mach-spear3xx/uncompress.h             |    2 +-
 arch/arm/mach-spear3xx/spear300.c                  |    6 +--
 arch/arm/mach-spear3xx/spear310.c                  |    6 +--
 arch/arm/mach-spear3xx/spear320.c                  |    6 +--
 arch/arm/mach-spear3xx/spear3xx.c                  |    6 +--
 .../include/mach-spear6xx/debug-macro.S            |    2 +-
 .../arm/mach-spear6xx/include/mach-spear6xx/gpio.h |    2 +-
 .../include/mach-spear6xx/misc_regs.h              |    2 +-
 .../mach-spear6xx/include/mach-spear6xx/timex.h    |    2 +-
 .../include/mach-spear6xx/uncompress.h             |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c                  |    6 +--
 arch/arm/mach-tegra/apbio.c                        |    4 +-
 arch/arm/mach-tegra/board-dt-tegra20.c             |    4 +-
 arch/arm/mach-tegra/board-dt-tegra30.c             |    2 +-
 arch/arm/mach-tegra/board-harmony-power.c          |    2 +-
 arch/arm/mach-tegra/board-harmony.c                |    8 ++--
 arch/arm/mach-tegra/board-harmony.h                |    2 +-
 arch/arm/mach-tegra/board-paz00.c                  |    6 +--
 arch/arm/mach-tegra/board-paz00.h                  |    2 +-
 arch/arm/mach-tegra/board-pinmux.h                 |    2 +-
 arch/arm/mach-tegra/board-trimslice.c              |    4 +-
 arch/arm/mach-tegra/board-trimslice.h              |    2 +-
 arch/arm/mach-tegra/clock.c                        |    2 +-
 arch/arm/mach-tegra/clock.h                        |    2 +-
 arch/arm/mach-tegra/common.c                       |    4 +-
 arch/arm/mach-tegra/cpu-tegra.c                    |    2 +-
 arch/arm/mach-tegra/cpuidle.c                      |    2 +-
 arch/arm/mach-tegra/devices.c                      |    8 ++--
 arch/arm/mach-tegra/devices.h                      |    2 +-
 arch/arm/mach-tegra/dma.c                          |    8 ++--
 arch/arm/mach-tegra/flowctrl.c                     |    2 +-
 arch/arm/mach-tegra/fuse.c                         |    2 +-
 arch/arm/mach-tegra/headsmp.S                      |    2 +-
 .../mach-tegra/include/mach-tegra/debug-macro.S    |    4 +-
 .../arm/mach-tegra/include/mach-tegra/gpio-tegra.h |    2 +-
 .../arm/mach-tegra/include/mach-tegra/uncompress.h |    4 +-
 arch/arm/mach-tegra/io.c                           |    2 +-
 arch/arm/mach-tegra/irq.c                          |    2 +-
 arch/arm/mach-tegra/pcie.c                         |    6 +--
 arch/arm/mach-tegra/platsmp.c                      |    6 +--
 arch/arm/mach-tegra/pmc.c                          |    2 +-
 arch/arm/mach-tegra/powergate.c                    |    6 +--
 arch/arm/mach-tegra/reset.c                        |    4 +-
 arch/arm/mach-tegra/sleep.S                        |    2 +-
 arch/arm/mach-tegra/tegra2_clocks.c                |    4 +-
 arch/arm/mach-tegra/tegra2_emc.c                   |    2 +-
 arch/arm/mach-tegra/tegra30_clocks.c               |    2 +-
 arch/arm/mach-tegra/timer.c                        |    6 +--
 arch/arm/mach-tegra/usb_phy.c                      |    6 +--
 arch/arm/mach-u300/core.c                          |   10 ++--
 arch/arm/mach-u300/i2c.c                           |    2 +-
 arch/arm/mach-u300/include/mach-u300/debug-macro.S |    2 +-
 arch/arm/mach-u300/include/mach-u300/hardware.h    |    2 +-
 arch/arm/mach-u300/regulator.c                     |    4 +-
 arch/arm/mach-u300/spi.c                           |    4 +-
 arch/arm/mach-u300/timer.c                         |    2 +-
 arch/arm/mach-u300/u300.c                          |    4 +-
 arch/arm/mach-ux500/board-mop500-msp.c             |   16 +++----
 arch/arm/mach-ux500/board-mop500-pins.c            |    6 +--
 arch/arm/mach-ux500/board-mop500-sdi.c             |    6 +--
 arch/arm/mach-ux500/board-mop500-u8500uib.c        |    2 +-
 arch/arm/mach-ux500/board-mop500-uib.c             |    2 +-
 arch/arm/mach-ux500/board-mop500.c                 |   16 +++----
 arch/arm/mach-ux500/board-mop500.h                 |    2 +-
 arch/arm/mach-ux500/cache-l2x0.c                   |    4 +-
 arch/arm/mach-ux500/clock.c                        |    4 +-
 arch/arm/mach-ux500/cpu-db8500.c                   |   12 ++---
 arch/arm/mach-ux500/cpu.c                          |    6 +--
 arch/arm/mach-ux500/devices-common.c               |    4 +-
 arch/arm/mach-ux500/devices-common.h               |    2 +-
 arch/arm/mach-ux500/devices-db8500.c               |    6 +--
 arch/arm/mach-ux500/devices.c                      |    4 +-
 arch/arm/mach-ux500/id.c                           |    4 +-
 .../mach-ux500/include/mach-ux500/crypto-ux500.h   |    2 +-
 .../mach-ux500/include/mach-ux500/debug-macro.S    |    2 +-
 arch/arm/mach-ux500/include/mach-ux500/hardware.h  |    4 +-
 arch/arm/mach-ux500/include/mach-ux500/irqs.h      |    6 +--
 arch/arm/mach-ux500/include/mach-ux500/msp.h       |    2 +-
 .../arm/mach-ux500/include/mach-ux500/uncompress.h |    2 +-
 arch/arm/mach-ux500/platsmp.c                      |    4 +-
 arch/arm/mach-ux500/timer.c                        |    8 ++--
 arch/arm/mach-ux500/usb.c                          |    6 +--
 arch/arm/mach-versatile/core.c                     |   10 ++--
 .../mach-versatile/include/mach-versatile/clkdev.h |    2 +-
 .../mach-versatile/include/mach-versatile/irqs.h   |    2 +-
 arch/arm/mach-versatile/pci.c                      |    2 +-
 arch/arm/mach-versatile/versatile_ab.c             |    2 +-
 arch/arm/mach-versatile/versatile_pb.c             |    2 +-
 arch/arm/mach-vexpress/ct-ca9x4.c                  |    6 +--
 arch/arm/mach-vexpress/platsmp.c                   |    2 +-
 arch/arm/mach-vexpress/v2m.c                       |    6 +--
 arch/arm/mach-vt8500/bv07.c                        |    2 +-
 arch/arm/mach-vt8500/devices-vt8500.c              |    6 +--
 arch/arm/mach-vt8500/devices-wm8505.c              |    6 +--
 arch/arm/mach-vt8500/devices.c                     |    4 +-
 arch/arm/mach-vt8500/wm8505_7in.c                  |    2 +-
 arch/arm/mach-w90x900/clksel.c                     |    4 +-
 arch/arm/mach-w90x900/clock.c                      |    2 +-
 arch/arm/mach-w90x900/cpu.c                        |   10 ++--
 arch/arm/mach-w90x900/dev.c                        |   12 ++---
 arch/arm/mach-w90x900/gpio.c                       |    2 +-
 .../include/mach-w90x900/entry-macro.S             |    4 +-
 arch/arm/mach-w90x900/include/mach-w90x900/gpio.h  |    2 +-
 .../mach-w90x900/include/mach-w90x900/hardware.h   |    2 +-
 .../mach-w90x900/include/mach-w90x900/regs-ldm.h   |    2 +-
 .../mach-w90x900/include/mach-w90x900/uncompress.h |    4 +-
 arch/arm/mach-w90x900/irq.c                        |    4 +-
 arch/arm/mach-w90x900/mach-nuc910evb.c             |    2 +-
 arch/arm/mach-w90x900/mach-nuc950evb.c             |    4 +-
 arch/arm/mach-w90x900/mach-nuc960evb.c             |    2 +-
 arch/arm/mach-w90x900/mfp.c                        |    2 +-
 arch/arm/mach-w90x900/nuc910.c                     |    2 +-
 arch/arm/mach-w90x900/nuc950.c                     |    2 +-
 arch/arm/mach-w90x900/nuc960.c                     |    2 +-
 arch/arm/mach-w90x900/time.c                       |    4 +-
 arch/arm/mach-zynq/common.c                        |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/clkdev.h      |    2 +-
 arch/arm/mach-zynq/include/mach-zynq/debug-macro.S |    4 +-
 arch/arm/mach-zynq/include/mach-zynq/uncompress.h  |    4 +-
 arch/arm/mach-zynq/timer.c                         |    2 +-
 arch/arm/mm/cache-feroceon-l2.c                    |    2 +-
 arch/arm/plat-mxc/3ds_debugboard.c                 |    2 +-
 arch/arm/plat-mxc/avic.c                           |    6 +--
 arch/arm/plat-mxc/clock.c                          |    4 +-
 arch/arm/plat-mxc/cpu.c                            |    2 +-
 arch/arm/plat-mxc/cpufreq.c                        |    4 +-
 arch/arm/plat-mxc/devices.c                        |    2 +-
 arch/arm/plat-mxc/devices/platform-ahci-imx.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-fec.c           |    4 +-
 arch/arm/plat-mxc/devices/platform-flexcan.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c  |    4 +-
 arch/arm/plat-mxc/devices/platform-gpio-mxc.c      |    2 +-
 arch/arm/plat-mxc/devices/platform-gpio_keys.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-dma.c       |    2 +-
 arch/arm/plat-mxc/devices/platform-imx-fb.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-i2c.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-keypad.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-ssi.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imx-uart.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx2-wdt.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-imx21-hcd.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-imx_udc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-imxdi_rtc.c     |    4 +-
 arch/arm/plat-mxc/devices/platform-ipu-core.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mx2-camera.c    |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-ehci.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc-mmc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_nand.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_pwm.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rnga.c      |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_rtc.c       |    4 +-
 arch/arm/plat-mxc/devices/platform-mxc_w1.c        |    4 +-
 arch/arm/plat-mxc/devices/platform-pata_imx.c      |    4 +-
 .../plat-mxc/devices/platform-sdhci-esdhc-imx.c    |    6 +--
 arch/arm/plat-mxc/devices/platform-spi_imx.c       |    4 +-
 arch/arm/plat-mxc/epit.c                           |    4 +-
 arch/arm/plat-mxc/iomux-v1.c                       |    4 +-
 arch/arm/plat-mxc/iomux-v3.c                       |    4 +-
 arch/arm/plat-mxc/iram_alloc.c                     |    2 +-
 arch/arm/plat-mxc/ssi-fiq-ksym.c                   |    2 +-
 arch/arm/plat-mxc/system.c                         |    4 +-
 arch/arm/plat-mxc/time.c                           |    4 +-
 arch/arm/plat-mxc/tzic.c                           |    6 +--
 arch/arm/plat-mxc/ulpi.c                           |    2 +-
 arch/arm/plat-omap/clock.c                         |    2 +-
 arch/arm/plat-omap/common.c                        |   12 ++---
 arch/arm/plat-omap/counter_32k.c                   |    8 ++--
 arch/arm/plat-omap/debug-devices.c                 |    2 +-
 arch/arm/plat-omap/debug-leds.c                    |    2 +-
 arch/arm/plat-omap/devices.c                       |   10 ++--
 arch/arm/plat-omap/dma.c                           |    4 +-
 arch/arm/plat-omap/dmtimer.c                       |    4 +-
 arch/arm/plat-omap/fb.c                            |    2 +-
 arch/arm/plat-omap/i2c.c                           |    8 ++--
 arch/arm/plat-omap/include/plat-omap/board.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/common.h      |    4 +-
 arch/arm/plat-omap/include/plat-omap/cpu.h         |    2 +-
 arch/arm/plat-omap/include/plat-omap/dma.h         |    2 +-
 arch/arm/plat-omap/include/plat-omap/hardware.h    |   22 ++++-----
 arch/arm/plat-omap/include/plat-omap/hdq1w.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/iommu.h       |    2 +-
 arch/arm/plat-omap/include/plat-omap/mmc.h         |    4 +-
 arch/arm/plat-omap/include/plat-omap/nand.h        |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap-serial.h |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap_device.h |    2 +-
 arch/arm/plat-omap/include/plat-omap/omap_hwmod.h  |    2 +-
 arch/arm/plat-omap/include/plat-omap/uncompress.h  |    2 +-
 arch/arm/plat-omap/include/plat-omap/usb.h         |    2 +-
 arch/arm/plat-omap/mailbox.c                       |    2 +-
 arch/arm/plat-omap/mux.c                           |    4 +-
 arch/arm/plat-omap/omap-pm-noop.c                  |    4 +-
 arch/arm/plat-omap/omap_device.c                   |    6 +--
 arch/arm/plat-omap/sram.c                          |    6 +--
 arch/arm/plat-orion/addr-map.c                     |    2 +-
 arch/arm/plat-orion/common.c                       |    4 +-
 arch/arm/plat-orion/gpio.c                         |    2 +-
 arch/arm/plat-orion/irq.c                          |    4 +-
 arch/arm/plat-orion/mpp.c                          |    2 +-
 arch/arm/plat-orion/pcie.c                         |    4 +-
 arch/arm/plat-pxa/mfp.c                            |    2 +-
 arch/arm/plat-s3c24xx/clock-dclk.c                 |    8 ++--
 arch/arm/plat-s3c24xx/cpu-freq-debugfs.c           |    2 +-
 arch/arm/plat-s3c24xx/cpu-freq.c                   |    8 ++--
 arch/arm/plat-s3c24xx/dma.c                        |   10 ++--
 arch/arm/plat-s3c24xx/irq.c                        |    8 ++--
 arch/arm/plat-s3c24xx/s3c2410-clock.c              |   14 +++---
 arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c      |    8 ++--
 arch/arm/plat-s3c24xx/s3c2410-iotiming.c           |    8 ++--
 arch/arm/plat-s3c24xx/s3c2412-iotiming.c           |    8 ++--
 arch/arm/plat-samsung/adc.c                        |    4 +-
 arch/arm/plat-samsung/clock-clksrc.c               |    6 +--
 arch/arm/plat-samsung/clock.c                      |    8 ++--
 arch/arm/plat-samsung/cpu.c                        |    2 +-
 arch/arm/plat-samsung/dev-backlight.c              |    6 +--
 arch/arm/plat-samsung/dev-uart.c                   |    2 +-
 arch/arm/plat-samsung/devs.c                       |   42 ++++++++---------
 .../include/plat-samsung/cpu-freq-core.h           |    2 +-
 .../include/plat-samsung/debug-macro.S             |    2 +-
 .../plat-samsung/include/plat-samsung/dma-pl330.h  |    2 +-
 .../include/plat-samsung/dma-s3c24xx.h             |    2 +-
 arch/arm/plat-samsung/include/plat-samsung/dma.h   |    2 +-
 .../plat-samsung/include/plat-samsung/gpio-core.h  |    2 +-
 .../plat-samsung/include/plat-samsung/gpio-fns.h   |    2 +-
 .../plat-samsung/include/plat-samsung/map-s3c.h    |    2 +-
 .../plat-samsung/include/plat-samsung/map-s5p.h    |    2 +-
 .../plat-samsung/include/plat-samsung/regs-fb-v4.h |    2 +-
 arch/arm/plat-samsung/include/plat-samsung/sdhci.h |    2 +-
 .../plat-samsung/include/plat-samsung/uncompress.h |    4 +-
 .../include/plat-samsung/watchdog-reset.h          |    4 +-
 arch/arm/plat-samsung/init.c                       |    8 ++--
 arch/arm/plat-samsung/irq-vic-timer.c              |    6 +--
 arch/arm/plat-samsung/platformdata.c               |    4 +-
 arch/arm/plat-samsung/pm-check.c                   |    2 +-
 arch/arm/plat-samsung/pm-gpio.c                    |    4 +-
 arch/arm/plat-samsung/pm.c                         |    4 +-
 arch/arm/plat-samsung/pwm-clock.c                  |    8 ++--
 arch/arm/plat-samsung/s5p-clock.c                  |    6 +--
 arch/arm/plat-samsung/s5p-dev-mfc.c                |    6 +--
 arch/arm/plat-samsung/s5p-dev-uart.c               |    2 +-
 arch/arm/plat-samsung/s5p-irq-eint.c               |    8 ++--
 arch/arm/plat-samsung/s5p-irq-gpioint.c            |    4 +-
 arch/arm/plat-samsung/s5p-irq-pm.c                 |    6 +--
 arch/arm/plat-samsung/s5p-irq.c                    |    6 +--
 arch/arm/plat-samsung/s5p-pm.c                     |    2 +-
 arch/arm/plat-samsung/s5p-time.c                   |    6 +--
 arch/arm/plat-samsung/time.c                       |    6 +--
 arch/arm/plat-samsung/wakeup-mask.c                |    4 +-
 arch/arm/plat-spear/shirq.c                        |    2 +-
 arch/arm/plat-versatile/clcd.c                     |    2 +-
 arch/arm/plat-versatile/fpga-irq.c                 |    2 +-
 arch/arm/plat-versatile/sched-clock.c              |    2 +-
 drivers/ata/pata_at91.c                            |    4 +-
 drivers/ata/pata_palmld.c                          |    2 +-
 drivers/ata/pata_pxa.c                             |    6 +--
 drivers/ata/pata_samsung_cf.c                      |    4 +-
 drivers/char/hw_random/omap-rng.c                  |    2 +-
 drivers/char/msm_smd_pkt.c                         |    2 +-
 drivers/clk/clk-u300.c                             |    2 +-
 drivers/clk/mxs/clk-imx23.c                        |    4 +-
 drivers/clk/mxs/clk-imx28.c                        |    4 +-
 drivers/clocksource/clksrc-dbx500-prcmu.c          |    4 +-
 drivers/cpufreq/exynos-cpufreq.c                   |    2 +-
 drivers/cpufreq/omap-cpufreq.c                     |    8 ++--
 drivers/crypto/ixp4xx_crypto.c                     |    4 +-
 drivers/crypto/omap-aes.c                          |    4 +-
 drivers/crypto/omap-sham.c                         |    4 +-
 drivers/crypto/s5p-sss.c                           |    4 +-
 drivers/crypto/ux500/cryp/cryp_core.c              |    6 +--
 drivers/crypto/ux500/hash/hash_core.c              |    4 +-
 drivers/devfreq/exynos4_bus.c                      |    2 +-
 drivers/dma/at_hdmac_regs.h                        |    2 +-
 drivers/dma/coh901318.c                            |    2 +-
 drivers/dma/coh901318_lli.c                        |    2 +-
 drivers/dma/coh901318_lli.h                        |    2 +-
 drivers/dma/imx-sdma.c                             |    6 +--
 drivers/dma/ipu/ipu_idmac.c                        |    2 +-
 drivers/dma/ipu/ipu_irq.c                          |    2 +-
 drivers/dma/mmp_tdma.c                             |    4 +-
 drivers/dma/mv_xor.c                               |    2 +-
 drivers/dma/omap-dma.c                             |    2 +-
 drivers/dma/ste_dma40.c                            |    2 +-
 drivers/dma/ste_dma40_ll.c                         |    2 +-
 drivers/gpio/gpio-ep93xx.c                         |    4 +-
 drivers/gpio/gpio-ks8695.c                         |    6 +--
 drivers/gpio/gpio-lpc32xx.c                        |    8 ++--
 drivers/gpio/gpio-msm-v1.c                         |    6 +--
 drivers/gpio/gpio-msm-v2.c                         |    4 +-
 drivers/gpio/gpio-samsung.c                        |   12 ++---
 drivers/gpio/gpio-tegra.c                          |    4 +-
 drivers/gpio/gpio-tnetv107x.c                      |    4 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c           |    2 +-
 drivers/hwmon/s3c-hwmon.c                          |    4 +-
 drivers/i2c/busses/i2c-at91.c                      |    6 +--
 drivers/i2c/busses/i2c-s3c2410.c                   |    4 +-
 drivers/iio/adc/at91_adc.c                         |    2 +-
 drivers/input/keyboard/davinci_keyscan.c           |    6 +--
 drivers/input/keyboard/ep93xx_keypad.c             |    4 +-
 drivers/input/keyboard/jornada720_kbd.c            |    6 +--
 drivers/input/keyboard/nomadik-ske-keypad.c        |    2 +-
 drivers/input/keyboard/omap-keypad.c               |    6 +--
 drivers/input/keyboard/pxa27x_keypad.c             |    2 +-
 drivers/input/keyboard/pxa930_rotary.c             |    2 +-
 drivers/input/keyboard/spear-keyboard.c            |    2 +-
 drivers/input/keyboard/tegra-kbc.c                 |    4 +-
 drivers/input/keyboard/w90p910_keypad.c            |    2 +-
 drivers/input/mouse/pxa930_trkball.c               |    4 +-
 drivers/input/serio/ams_delta_serio.c              |    4 +-
 drivers/input/touchscreen/jornada720_ts.c          |    6 +--
 drivers/input/touchscreen/s3c2410_ts.c             |    6 +--
 drivers/input/touchscreen/tnetv107x-ts.c           |    2 +-
 drivers/iommu/exynos-iommu.c                       |    2 +-
 drivers/iommu/msm_iommu.c                          |    4 +-
 drivers/iommu/msm_iommu_dev.c                      |    6 +--
 drivers/iommu/omap-iommu-debug.c                   |    6 +--
 drivers/iommu/omap-iommu.c                         |    4 +-
 drivers/iommu/omap-iovmm.c                         |    6 +--
 drivers/iommu/tegra-smmu.c                         |    6 +--
 drivers/leds/leds-netxbig.c                        |    2 +-
 drivers/leds/leds-ns2.c                            |    2 +-
 drivers/leds/leds-s3c24xx.c                        |    6 +--
 drivers/media/video/davinci/isif.c                 |    2 +-
 drivers/media/video/davinci/vpbe_display.c         |    2 +-
 drivers/media/video/davinci/vpbe_osd.c             |    4 +-
 drivers/media/video/davinci/vpbe_venc.c            |    6 +--
 drivers/media/video/davinci/vpif.c                 |    2 +-
 drivers/media/video/davinci/vpss.c                 |    2 +-
 drivers/media/video/mx1_camera.c                   |    8 ++--
 drivers/media/video/mx2_camera.c                   |    4 +-
 drivers/media/video/mx3_camera.c                   |    6 +--
 drivers/media/video/omap/omap_vout.c               |    4 +-
 drivers/media/video/omap/omap_vout_vrfb.c          |    4 +-
 drivers/media/video/omap/omap_voutdef.h            |    2 +-
 drivers/media/video/omap/omap_voutlib.c            |    2 +-
 drivers/media/video/omap1_camera.c                 |    2 +-
 drivers/media/video/omap3isp/isp.h                 |    4 +-
 drivers/media/video/omap3isp/ispreg.h              |    2 +-
 drivers/media/video/omap3isp/ispstat.h             |    2 +-
 drivers/media/video/omap3isp/ispvideo.c            |    6 +--
 drivers/media/video/s5p-fimc/mipi-csis.c           |    2 +-
 drivers/media/video/s5p-tv/sii9234_drv.c           |    2 +-
 drivers/mfd/db8500-prcmu.c                         |    8 ++--
 drivers/mfd/mcp-sa11x0.c                           |    4 +-
 drivers/mfd/menelaus.c                             |    2 +-
 drivers/mfd/omap-usb-host.c                        |    4 +-
 drivers/mfd/ucb1x00-ts.c                           |    2 +-
 drivers/mmc/host/davinci_mmc.c                     |    4 +-
 drivers/mmc/host/msm_sdcc.c                        |    8 ++--
 drivers/mmc/host/mvsdio.c                          |    2 +-
 drivers/mmc/host/omap.c                            |   10 ++--
 drivers/mmc/host/omap_hsmmc.c                      |    6 +--
 drivers/mmc/host/s3cmci.c                          |    6 +--
 drivers/mmc/host/sdhci-cns3xxx.c                   |    2 +-
 drivers/mmc/host/sdhci-esdhc-imx.c                 |    2 +-
 drivers/mmc/host/sdhci-s3c.c                       |    4 +-
 drivers/mmc/host/sdhci-tegra.c                     |    4 +-
 drivers/mtd/maps/autcpu12-nvram.c                  |    4 +-
 drivers/mtd/nand/ams-delta.c                       |    2 +-
 drivers/mtd/nand/autcpu12.c                        |    4 +-
 drivers/mtd/nand/bcm_umi_nand.c                    |    8 ++--
 drivers/mtd/nand/cmx270_nand.c                     |    2 +-
 drivers/mtd/nand/davinci_nand.c                    |    4 +-
 drivers/mtd/nand/mxc_nand.c                        |    4 +-
 drivers/mtd/nand/nand_bcm_umi.c                    |    2 +-
 drivers/mtd/nand/nand_bcm_umi.h                    |    4 +-
 drivers/mtd/nand/nomadik_nand.c                    |    4 +-
 drivers/mtd/nand/omap2.c                           |    6 +--
 drivers/mtd/nand/orion_nand.c                      |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c                     |    2 +-
 drivers/mtd/nand/s3c2410.c                         |    4 +-
 drivers/mtd/onenand/omap2.c                        |    8 ++--
 drivers/mtd/onenand/samsung.c                      |    2 +-
 drivers/net/ethernet/cadence/at91_ether.c          |    4 +-
 drivers/net/ethernet/micrel/ks8695net.c            |    6 +--
 drivers/net/ethernet/netx-eth.c                    |   10 ++--
 drivers/net/ethernet/smsc/smc91x.h                 |    4 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    6 +--
 drivers/net/wan/ixp4xx_hss.c                       |    4 +-
 drivers/pcmcia/at91_cf.c                           |    8 ++--
 drivers/pcmcia/omap_cf.c                           |    4 +-
 drivers/pcmcia/pxa2xx_balloon3.c                   |    2 +-
 drivers/pcmcia/pxa2xx_base.c                       |    6 +--
 drivers/pcmcia/pxa2xx_e740.c                       |    2 +-
 drivers/pcmcia/pxa2xx_hx4700.c                     |    2 +-
 drivers/pcmcia/pxa2xx_mainstone.c                  |    4 +-
 drivers/pcmcia/pxa2xx_palmld.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtc.c                     |    2 +-
 drivers/pcmcia/pxa2xx_palmtx.c                     |    2 +-
 drivers/pcmcia/pxa2xx_trizeps4.c                   |    4 +-
 drivers/pcmcia/pxa2xx_viper.c                      |    2 +-
 drivers/pcmcia/pxa2xx_vpac270.c                    |    2 +-
 drivers/pcmcia/sa1100_assabet.c                    |    2 +-
 drivers/pcmcia/sa1100_cerf.c                       |    4 +-
 drivers/pcmcia/sa1100_h3600.c                      |    4 +-
 drivers/pcmcia/sa1100_nanoengine.c                 |    4 +-
 drivers/pcmcia/sa1100_shannon.c                    |    4 +-
 drivers/pcmcia/sa1100_simpad.c                     |    4 +-
 drivers/pcmcia/sa1111_badge4.c                     |    4 +-
 drivers/pcmcia/sa1111_lubbock.c                    |    4 +-
 drivers/pcmcia/sa1111_neponset.c                   |    4 +-
 drivers/pinctrl/pinctrl-coh901.c                   |    2 +-
 drivers/pinctrl/pinctrl-nomadik.c                  |    4 +-
 drivers/pinctrl/pinctrl-nomadik.h                  |    2 +-
 drivers/pinctrl/pinctrl-tegra.c                    |    2 +-
 drivers/power/collie_battery.c                     |    2 +-
 drivers/power/s3c_adc_battery.c                    |    2 +-
 drivers/power/tosa_battery.c                       |    2 +-
 drivers/ptp/ptp_ixp46x.c                           |    2 +-
 drivers/pwm/pwm-samsung.c                          |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |    4 +-
 drivers/rtc/rtc-at91rm9200.c                       |    2 +-
 drivers/rtc/rtc-at91sam9.c                         |    6 +--
 drivers/rtc/rtc-s3c.c                              |    2 +-
 drivers/spi/spi-davinci.c                          |    4 +-
 drivers/spi/spi-ep93xx.c                           |    4 +-
 drivers/spi/spi-nuc900.c                           |    2 +-
 drivers/spi/spi-omap-100k.c                        |    2 +-
 drivers/spi/spi-omap-uwire.c                       |    4 +-
 drivers/spi/spi-omap2-mcspi.c                      |    4 +-
 drivers/spi/spi-s3c24xx-fiq.S                      |    2 +-
 drivers/spi/spi-s3c24xx.c                          |    4 +-
 drivers/spi/spi-s3c64xx.c                          |    2 +-
 drivers/staging/nvec/nvec.c                        |    4 +-
 drivers/staging/omapdrm/omap_dmm_tiler.h           |    2 +-
 drivers/staging/tidspbridge/core/dsp-clock.c       |    4 +-
 drivers/staging/tidspbridge/core/tiomap3430.c      |    2 +-
 drivers/staging/tidspbridge/core/tiomap3430_pwr.c  |    2 +-
 drivers/staging/tidspbridge/core/tiomap_io.c       |    2 +-
 drivers/staging/tidspbridge/core/ue_deh.c          |    2 +-
 .../tidspbridge/include/dspbridge/host_os.h        |    4 +-
 drivers/staging/tidspbridge/rmgr/drv_interface.c   |    2 +-
 drivers/tty/serial/imx.c                           |    2 +-
 drivers/tty/serial/msm_smd_tty.c                   |    2 +-
 drivers/tty/serial/netx-serial.c                   |    4 +-
 drivers/tty/serial/omap-serial.c                   |    6 +--
 drivers/tty/serial/samsung.c                       |    4 +-
 drivers/usb/gadget/at91_udc.c                      |   10 ++--
 drivers/usb/gadget/atmel_usba_udc.c                |    4 +-
 drivers/usb/gadget/omap_udc.c                      |    2 +-
 drivers/usb/gadget/pxa25x_udc.c                    |    4 +-
 drivers/usb/gadget/pxa25x_udc.h                    |    2 +-
 drivers/usb/gadget/s3c-hsudc.c                     |    2 +-
 drivers/usb/gadget/s3c2410_udc.c                   |    4 +-
 drivers/usb/host/ehci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ehci-mxc.c                        |    4 +-
 drivers/usb/host/ehci-omap.c                       |    2 +-
 drivers/usb/host/ehci-orion.c                      |    2 +-
 drivers/usb/host/ehci-s5p.c                        |    4 +-
 drivers/usb/host/ehci-tegra.c                      |    4 +-
 drivers/usb/host/imx21-hcd.h                       |    2 +-
 drivers/usb/host/ohci-cns3xxx.c                    |    4 +-
 drivers/usb/host/ohci-da8xx.c                      |    4 +-
 drivers/usb/host/ohci-exynos.c                     |    2 +-
 drivers/usb/host/ohci-omap.c                       |    4 +-
 drivers/usb/host/ohci-omap3.c                      |    2 +-
 drivers/usb/host/ohci-pxa27x.c                     |    6 +--
 drivers/usb/host/ohci-s3c2410.c                    |    2 +-
 drivers/usb/host/ohci-sa1111.c                     |    4 +-
 drivers/usb/musb/am35x.c                           |    2 +-
 drivers/usb/musb/da8xx.c                           |    4 +-
 drivers/usb/musb/musb_dsps.c                       |    2 +-
 drivers/usb/musb/omap2430.h                        |    2 +-
 drivers/usb/musb/tusb6010_omap.c                   |    4 +-
 drivers/usb/otg/isp1301_omap.c                     |    2 +-
 drivers/video/acornfb.c                            |    4 +-
 drivers/video/backlight/jornada720_bl.c            |    4 +-
 drivers/video/backlight/jornada720_lcd.c           |    4 +-
 drivers/video/backlight/omap1_bl.c                 |    4 +-
 drivers/video/backlight/tosa_bl.c                  |    2 +-
 drivers/video/backlight/tosa_lcd.c                 |    2 +-
 drivers/video/clps711xfb.c                         |    4 +-
 drivers/video/cyber2000fb.c                        |    2 +-
 drivers/video/exynos/exynos_mipi_dsi.c             |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_common.c      |    2 +-
 drivers/video/exynos/exynos_mipi_dsi_lowlevel.c    |    2 +-
 drivers/video/imxfb.c                              |    4 +-
 drivers/video/msm/mddi.c                           |    8 ++--
 drivers/video/msm/mddi_client_dummy.c              |    2 +-
 drivers/video/msm/mddi_client_nt35399.c            |    2 +-
 drivers/video/msm/mddi_client_toshiba.c            |    2 +-
 drivers/video/msm/mdp.c                            |    4 +-
 drivers/video/msm/mdp_hw.h                         |    4 +-
 drivers/video/msm/mdp_ppp.c                        |    2 +-
 drivers/video/msm/msm_fb.c                         |    4 +-
 drivers/video/mx3fb.c                              |    8 ++--
 drivers/video/nuc900fb.c                           |    8 ++--
 drivers/video/omap/hwa742.c                        |    2 +-
 drivers/video/omap/lcd_ams_delta.c                 |    4 +-
 drivers/video/omap/lcd_inn1510.c                   |    2 +-
 drivers/video/omap/lcd_mipid.c                     |    2 +-
 drivers/video/omap/lcd_osk.c                       |    2 +-
 drivers/video/omap/lcd_palmte.c                    |    2 +-
 drivers/video/omap/lcdc.c                          |    4 +-
 drivers/video/omap/omapfb_main.c                   |    2 +-
 drivers/video/omap/sossi.c                         |    2 +-
 drivers/video/omap2/dss/dispc.c                    |    2 +-
 drivers/video/omap2/dss/dpi.c                      |    2 +-
 drivers/video/omap2/dss/dsi.c                      |    2 +-
 drivers/video/omap2/dss/dss.c                      |    4 +-
 drivers/video/omap2/dss/dss_features.c             |    2 +-
 drivers/video/omap2/dss/overlay.c                  |    2 +-
 drivers/video/omap2/dss/venc.c                     |    2 +-
 drivers/video/omap2/omapfb/omapfb-ioctl.c          |    4 +-
 drivers/video/omap2/omapfb/omapfb-main.c           |    4 +-
 drivers/video/omap2/omapfb/omapfb-sysfs.c          |    2 +-
 drivers/video/omap2/vram.c                         |    4 +-
 drivers/video/omap2/vrfb.c                         |    4 +-
 drivers/video/pxafb.c                              |    6 +--
 drivers/video/s3c-fb.c                             |    4 +-
 drivers/video/sa1100fb.c                           |    4 +-
 drivers/video/vt8500lcdfb.c                        |    2 +-
 drivers/video/wm8505fb.c                           |    2 +-
 drivers/watchdog/at91rm9200_wdt.c                  |    2 +-
 drivers/watchdog/omap_wdt.c                        |    2 +-
 drivers/watchdog/s3c2410_wdt.c                     |    2 +-
 include/linux/mfd/davinci_voicecodec.h             |    2 +-
 include/linux/mfd/dbx500-prcmu.h                   |    2 +-
 include/linux/omapfb.h                             |    2 +-
 include/linux/platform_data/atmel-aes.h            |    2 +-
 include/linux/power/smartreflex.h                  |    2 +-
 include/linux/spi/pxa2xx_spi.h                     |    2 +-
 sound/arm/pxa2xx-ac97-lib.c                        |    6 +--
 sound/arm/pxa2xx-ac97.c                            |    4 +-
 sound/arm/pxa2xx-pcm-lib.c                         |    2 +-
 sound/arm/pxa2xx-pcm.h                             |    2 +-
 sound/atmel/ac97c.c                                |    6 +--
 sound/oss/vidc.c                                   |    2 +-
 sound/oss/vidc_fill.S                              |    2 +-
 sound/oss/waveartist.c                             |    2 +-
 sound/soc/atmel/atmel_ssc_dai.c                    |    2 +-
 sound/soc/atmel/sam9g20_wm8731.c                   |    4 +-
 sound/soc/atmel/snd-soc-afeb9260.c                 |    2 +-
 sound/soc/davinci/davinci-evm.c                    |    6 +--
 sound/soc/davinci/davinci-i2s.c                    |    2 +-
 sound/soc/davinci/davinci-mcasp.h                  |    2 +-
 sound/soc/davinci/davinci-pcm.c                    |    4 +-
 sound/soc/davinci/davinci-pcm.h                    |    4 +-
 sound/soc/davinci/davinci-sffsdr.c                 |    2 +-
 sound/soc/ep93xx/edb93xx.c                         |    2 +-
 sound/soc/ep93xx/ep93xx-ac97.c                     |    2 +-
 sound/soc/ep93xx/ep93xx-i2s.c                      |    6 +--
 sound/soc/ep93xx/ep93xx-pcm.c                      |    6 +--
 sound/soc/ep93xx/simone.c                          |    2 +-
 sound/soc/ep93xx/snappercl15.c                     |    2 +-
 sound/soc/fsl/imx-pcm-fiq.c                        |    4 +-
 sound/soc/fsl/imx-ssi.c                            |    4 +-
 sound/soc/fsl/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/kirkwood/kirkwood-i2s.c                  |    2 +-
 sound/soc/kirkwood/kirkwood-openrd.c               |    4 +-
 sound/soc/kirkwood/kirkwood-t5325.c                |    4 +-
 sound/soc/mxs/mxs-saif.c                           |    4 +-
 sound/soc/nuc900/nuc900-ac97.c                     |    2 +-
 sound/soc/nuc900/nuc900-pcm.c                      |    2 +-
 sound/soc/omap/am3517evm.c                         |    6 +--
 sound/soc/omap/ams-delta.c                         |    4 +-
 sound/soc/omap/igep0020.c                          |    6 +--
 sound/soc/omap/mcbsp.c                             |    2 +-
 sound/soc/omap/n810.c                              |    4 +-
 sound/soc/omap/omap-abe-twl6040.c                  |    4 +-
 sound/soc/omap/omap-dmic.c                         |    2 +-
 sound/soc/omap/omap-hdmi.c                         |    2 +-
 sound/soc/omap/omap-mcbsp.c                        |    4 +-
 sound/soc/omap/omap-mcpdm.c                        |    4 +-
 sound/soc/omap/omap-pcm.c                          |    2 +-
 sound/soc/omap/omap3beagle.c                       |    6 +--
 sound/soc/omap/omap3evm.c                          |    6 +--
 sound/soc/omap/omap3pandora.c                      |    2 +-
 sound/soc/omap/osk5912.c                           |    4 +-
 sound/soc/omap/overo.c                             |    6 +--
 sound/soc/omap/rx51.c                              |    2 +-
 sound/soc/omap/sdp3430.c                           |    6 +--
 sound/soc/omap/zoom2.c                             |    8 ++--
 sound/soc/pxa/corgi.c                              |    4 +-
 sound/soc/pxa/e740_wm9705.c                        |    4 +-
 sound/soc/pxa/e750_wm9705.c                        |    4 +-
 sound/soc/pxa/e800_wm9712.c                        |    4 +-
 sound/soc/pxa/em-x270.c                            |    2 +-
 sound/soc/pxa/hx4700.c                             |    2 +-
 sound/soc/pxa/magician.c                           |    2 +-
 sound/soc/pxa/mioa701_wm9713.c                     |    2 +-
 sound/soc/pxa/mmp-pcm.c                            |    2 +-
 sound/soc/pxa/palm27x.c                            |    4 +-
 sound/soc/pxa/poodle.c                             |    4 +-
 sound/soc/pxa/pxa-ssp.c                            |    4 +-
 sound/soc/pxa/pxa2xx-ac97.c                        |    8 ++--
 sound/soc/pxa/pxa2xx-i2s.c                         |    6 +--
 sound/soc/pxa/spitz.c                              |    2 +-
 sound/soc/pxa/tosa.c                               |    4 +-
 sound/soc/pxa/z2.c                                 |    6 +--
 sound/soc/samsung/ac97.c                           |    4 +-
 sound/soc/samsung/h1940_uda1380.c                  |    4 +-
 sound/soc/samsung/i2s.c                            |    2 +-
 sound/soc/samsung/neo1973_wm8753.c                 |    4 +-
 sound/soc/samsung/pcm.c                            |    4 +-
 sound/soc/samsung/rx1950_uda1380.c                 |    2 +-
 sound/soc/samsung/s3c24xx-i2s.c                    |    2 +-
 sound/soc/samsung/s3c24xx_simtec.c                 |    2 +-
 sound/soc/samsung/s3c24xx_uda134x.c                |    2 +-
 sound/soc/samsung/spdif.c                          |    2 +-
 sound/soc/tegra/tegra30_ahub.c                     |    4 +-
 sound/soc/tegra/tegra_pcm.h                        |    2 +-
 sound/soc/tegra/tegra_wm8903.c                     |    2 +-
 sound/soc/ux500/mop500_ab8500.c                    |    2 +-
 sound/soc/ux500/ux500_msp_dai.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.c                    |    4 +-
 sound/soc/ux500/ux500_msp_i2s.h                    |    2 +-
 sound/soc/ux500/ux500_pcm.c                        |    2 +-
 2008 files changed, 5935 insertions(+), 5935 deletions(-)

diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
index d8eb01c..f088b4b 100644
--- a/Documentation/spi/ep93xx_spi
+++ b/Documentation/spi/ep93xx_spi
@@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 
-#include <mach/ep93xx_spi.h>
+#include <mach-ep93xx/ep93xx_spi.h>
 
 /* this is our GPIO line used for chip select */
 #define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b..4bcb9c7 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -23,7 +23,7 @@
 	.section	".start", "ax"
 
 	/* load board-specific initialization code */
-#include <mach/zboot.h>
+#include <mach-shmobile/zboot.h>
 
 #if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
 	/* Load image from MMC/SD */
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
index bd3d469..ff0aa20 100644
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ b/arch/arm/boot/compressed/sdhi-shmobile.c
@@ -18,7 +18,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sd.h>
 #include <linux/mmc/tmio.h>
-#include <mach/sdhi.h>
+#include <mach-shmobile/sdhi.h>
 
 #define OCR_FASTBOOT		(1<<29)
 #define OCR_HCS			(1<<30)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6f50c67..fd81ffe 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -16,11 +16,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_st.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 01fb732..2b63b60 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -18,10 +18,10 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 
-#include <mach/board.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40..aec1da4 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -27,7 +27,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_st.h>
+#include <mach-at91/at91_st.h>
 
 static unsigned long last_crtr;
 static u32 irqmask;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 30c7f26..e84bddb 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -17,12 +17,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7b9c2ba..cb364af 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,13 +19,13 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_adc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index f40762c..58c830b 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -17,11 +17,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 8df5c1b..f2e6805 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,11 +21,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9261_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9261_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 84b3810..51f4f7e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index eb6bbf8..26dc600 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -20,11 +20,11 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9263_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9263_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index ffc0957..e3b0d36 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -20,7 +20,7 @@
 
 #include <asm/mach/time.h>
 
-#include <mach/at91_pit.h>
+#include <mach-at91/at91_pit.h>
 
 
 #define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 7af2e10..6d8da98 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -14,9 +14,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index ef6cedd..45c79b4 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -17,10 +17,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 0607399..242c850 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,14 +25,14 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/at91_adc.h>
-#include <mach/board.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
-#include <mach/atmel-mci.h>
+#include <mach-at91/at91_adc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9g45_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
+#include <mach-at91/atmel-mci.h>
 
 #include <media/atmel-isi.h>
 
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 9d45718..0726dad 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -11,9 +11,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91_rstc.h>
 
 			.arm
 
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 0849466..b5f4e1d 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9n12.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 72ce50a..3c17719 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -16,12 +16,12 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_rstc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f09fff9..cf41235 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -17,12 +17,12 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
 
-#include <mach/board.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9rl_matrix.h>
-#include <mach/at91_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at_hdmac.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9rl_matrix.h>
+#include <mach-at91/at91_matrix.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at_hdmac.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 477cf9d..d919d0e 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -12,10 +12,10 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/board.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e6..e3224b1 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -17,10 +17,10 @@
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
-#include <mach/at91x40.h>
-#include <mach/at91_aic.h>
-#include <mach/at91_st.h>
-#include <mach/timex.h>
+#include <mach-at91/at91x40.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_st.h>
+#include <mach-at91/timex.h>
 #include "generic.h"
 
 /*
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a..478fa8a 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -24,9 +24,9 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/time.h>
-#include <mach/at91_tc.h>
+#include <mach-at91/at91_tc.h>
 
 #define at91_tc_read(field) \
 	__raw_readl(AT91_TC + field)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 22d8856..bbfe99a 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index de7be19..ae1469e 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -34,7 +34,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,8 +43,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 477e708..8e3b25a 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -29,7 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,9 +38,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index a5b002f..b2f21fc 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index ecbc13b..2d5334c 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -39,12 +39,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91sam9260_matrix.h>
-#include <mach/at91_matrix.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91sam9260_matrix.h>
+#include <mach-at91/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2e6d043..73934ef 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -27,7 +27,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -36,11 +36,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 462bc31..40f5e99 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 872871a..df54c811 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index e8f45c4..346b427 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,8 +15,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 01f66e9..5a0365d 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -24,11 +24,11 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 #include "generic.h"
 
 static void __init at91eb01_init_irq(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d1e1f3f..3ae9f49 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,8 +35,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 9c24cb2..f9d2da7 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 82bdfde..814756e 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -24,11 +24,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 6cc83a8..d5315ef 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -32,9 +32,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 69ab124..43b5fc2 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -32,7 +32,7 @@
 #include <linux/clk.h>
 #include <linux/w1-gpio.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -41,9 +41,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index a9d5e78..b6d0d6f 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -30,11 +30,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/gsia18s.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/gsia18s.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 64c1dbf..7e98f65 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,9 +34,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/cpu.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 5d96cb8..5b1bf97 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -26,7 +26,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -35,11 +35,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 18103c5d..c9e9d89 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 9ca3e32..f809d33 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -29,10 +29,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/stamp9g20.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/stamp9g20.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 1270655..469000d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -28,7 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,10 +37,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index bf351e2..0364e46 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -39,11 +39,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index cc2bf97..9769e97 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 62e19e6..2311b39 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index c3b43ae..5dfc434 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -24,9 +24,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
 
 #include <linux/gpio.h>
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 7bf6da7..39546b8 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -28,7 +28,7 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,9 +37,9 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 889c1bf..27865bc 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -40,12 +40,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2269be5..e37f30f 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -44,12 +44,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 82adf58..b149347 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -43,12 +43,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 4ea4ee0..cd48ea7 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -34,7 +34,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -43,10 +43,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 3d48ec1..4222519 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -29,7 +29,7 @@
 
 #include <linux/platform_data/at91_adc.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <video/atmel_lcdc.h>
 #include <media/soc_camera.h>
 #include <media/atmel-isi.h>
@@ -42,11 +42,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
-#include <mach/system_rev.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
+#include <mach-at91/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index e7dc3ea..80f805c 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,11 +29,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index a4e031a..dada12c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -31,10 +31,10 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 29eae16..64c7010 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -25,9 +25,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index c1476b9..dacfc5b 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -40,11 +40,11 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91sam9_smc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 516d340..fed4f0a 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -42,12 +42,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/board.h>
-#include <mach/at91_aic.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/board.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91rm9200_mc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index de2ec6b..c5789a1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -25,9 +25,9 @@
 #include <linux/io.h>
 #include <linux/of_address.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include <asm/proc-fns.h>
 
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c63815..6d03dc6 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -21,7 +21,7 @@
 #include <linux/export.h>
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #include "pm.h"
 
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index be42cf0..ce21de2 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -28,8 +28,8 @@
 
 #include <asm/mach/irq.h>
 
-#include <mach/hardware.h>
-#include <mach/at91_pio.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pio.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
index d8aeb27..c871a14 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91_ramc.h
@@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
 #define AT91_MEMCTRL_SDRAMC	1
 #define AT91_MEMCTRL_DDRSDR	2
 
-#include <mach/at91rm9200_sdramc.h>
-#include <mach/at91sam9_ddrsdr.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
+#include <mach-at91/at91sam9_ddrsdr.h>
+#include <mach-at91/at91sam9_sdramc.h>
 
 #endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
index 175e1fd..2f6393e 100644
--- a/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach-at91/at91sam9_smc.h
@@ -16,7 +16,7 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
-#include <mach/cpu.h>
+#include <mach-at91/cpu.h>
 
 #ifndef __ASSEMBLY__
 struct sam9_smc_config {
diff --git a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
index 998cb0c..d8f4109 100644
--- a/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
+++ b/arch/arm/mach-at91/include/mach-at91/atmel-mci.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_ATMEL_MCI_H
 #define __MACH_ATMEL_MCI_H
 
-#include <mach/at_hdmac.h>
+#include <mach-at91/at_hdmac.h>
 
 /**
  * struct mci_dma_data - DMA data for MCI interface
diff --git a/arch/arm/mach-at91/include/mach-at91/debug-macro.S b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
index c6bb9e2..8a1599c 100644
--- a/arch/arm/mach-at91/include/mach-at91/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach-at91/debug-macro.S
@@ -11,8 +11,8 @@
  *
 */
 
-#include <mach/hardware.h>
-#include <mach/at91_dbgu.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_dbgu.h>
 
 #if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
 #define AT91_DBGU AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/include/mach-at91/hardware.h b/arch/arm/mach-at91/include/mach-at91/hardware.h
index 09242b6..caef81c 100644
--- a/arch/arm/mach-at91/include/mach-at91/hardware.h
+++ b/arch/arm/mach-at91/include/mach-at91/hardware.h
@@ -23,16 +23,16 @@
 #define AT91_BASE_DBGU1	0xffffee00
 
 #if defined(CONFIG_ARCH_AT91X40)
-#include <mach/at91x40.h>
+#include <mach-at91/at91x40.h>
 #else
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91sam9n12.h>
+#include <mach-at91/at91rm9200.h>
+#include <mach-at91/at91sam9260.h>
+#include <mach-at91/at91sam9261.h>
+#include <mach-at91/at91sam9263.h>
+#include <mach-at91/at91sam9rl.h>
+#include <mach-at91/at91sam9g45.h>
+#include <mach-at91/at91sam9x5.h>
+#include <mach-at91/at91sam9n12.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach-at91/memory.h b/arch/arm/mach-at91/include/mach-at91/memory.h
index 401c207..88c06fd 100644
--- a/arch/arm/mach-at91/include/mach-at91/memory.h
+++ b/arch/arm/mach-at91/include/mach-at91/memory.h
@@ -21,6 +21,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach-at91/timex.h b/arch/arm/mach-at91/include/mach-at91/timex.h
index 5e917a6..f4e72e2 100644
--- a/arch/arm/mach-at91/include/mach-at91/timex.h
+++ b/arch/arm/mach-at91/include/mach-at91/timex.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
 #ifdef CONFIG_ARCH_AT91X40
 
diff --git a/arch/arm/mach-at91/include/mach-at91/uncompress.h b/arch/arm/mach-at91/include/mach-at91/uncompress.h
index 6f6118d..914feb7 100644
--- a/arch/arm/mach-at91/include/mach-at91/uncompress.h
+++ b/arch/arm/mach-at91/include/mach-at91/uncompress.h
@@ -24,10 +24,10 @@
 
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 
-#include <mach/at91_dbgu.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/cpu.h>
 
 void __iomem *at91_uart;
 
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 1e02c0e..eeddbec 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,7 +33,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <mach-at91/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
-#include <mach/at91_aic.h>
+#include <mach-at91/at91_aic.h>
 
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..f921b1e 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 
-#include <mach/board.h>
+#include <mach-at91/board.h>
 
 
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2c2d865..a5b940e 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,9 +25,9 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <mach/at91_aic.h>
-#include <mach/at91_pmc.h>
-#include <mach/cpu.h>
+#include <mach-at91/at91_aic.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/cpu.h>
 
 #include "generic.h"
 #include "pm.h"
@@ -36,8 +36,8 @@
  * Show the reason for the previous system reset.
  */
 
-#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/at91_rstc.h>
+#include <mach-at91/at91_shdwc.h>
 
 static void __init show_reset_status(void)
 {
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 38f467c..529072a 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,8 +11,8 @@
 #ifndef __ARCH_ARM_MACH_AT91_PM
 #define __ARCH_ARM_MACH_AT91_PM
 
-#include <mach/at91_ramc.h>
-#include <mach/at91rm9200_sdramc.h>
+#include <mach-at91/at91_ramc.h>
+#include <mach-at91/at91rm9200_sdramc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..8f263c6 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,9 +13,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_ramc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_ramc.h>
 
 
 #ifdef CONFIG_SOC_AT91SAM9263
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 99a0a1d..be40bf2 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -14,7 +14,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <mach/at91sam9_smc.h>
+#include <mach-at91/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb..0fe58d5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -14,11 +14,11 @@
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_shdwc.h>
+#include <mach-at91/hardware.h>
+#include <mach-at91/cpu.h>
+#include <mach-at91/at91_dbgu.h>
+#include <mach-at91/at91_pmc.h>
+#include <mach-at91/at91_shdwc.h>
 
 #include "soc.h"
 #include "generic.h"
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..f7469da 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -32,11 +32,11 @@
 #include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/dma.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <cfg_global.h>
 
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
index ad237a4..108845f 100644
--- a/arch/arm/mach-bcmring/clock.c
+++ b/arch/arm/mach-bcmring/clock.c
@@ -22,10 +22,10 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/hw_cfg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
index 5e0b981..2e01614 100644
--- a/arch/arm/mach-bcmring/clock.h
+++ b/arch/arm/mach-bcmring/clock.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 #define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a parent */
 #define CLK_TYPE_PLL1            2	/* PPL1 */
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb19..4d089b3 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -29,8 +29,8 @@
 #include <linux/amba/bus.h>
 #include <linux/clkdev.h>
 
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
+#include <mach-bcmring/csp/mm_addr.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -48,9 +48,9 @@
 #include "clock.h"
 
 #include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/secHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
 static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff..270689d 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75..48e5977 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -30,8 +30,8 @@
 #include <csp/stdint.h>
 #include <csp/module.h>
 
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 #include <csp/reg.h>
 #include <csp/delay.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d88..0aee4f2 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -14,8 +14,8 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 #include <csp/intcHw.h>
 #include <csp/cache.h>
 
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
index 54ad964..d466c49 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -23,7 +23,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e..4a9675a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -30,9 +30,9 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/chipcHw_inline.h>
 
 /* ---- External Function Prototypes ------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f3283..f4e883a 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -30,8 +30,8 @@
 #include <stddef.h>
 
 #include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_priv.h>
 
 extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* Declared in dmacHw.c */
 
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e4..220e314 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -30,7 +30,7 @@
 #include <csp/stdint.h>
 
 #include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
+#include <mach-bcmring/csp/tmrHw_reg.h>
 
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
 #define tmrHw_MILLISEC_PER_SEC              (1000)
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index e5fd241..e90cfdf 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -31,11 +31,11 @@
 #include <linux/proc_fs.h>
 #include <linux/slab.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 #include <linux/pfn.h>
 #include <linux/atomic.h>
-#include <mach/dma.h>
+#include <mach-bcmring/dma.h>
 
 /* ---- Public Variables ------------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
index e6a1dc4..97d8a04 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -26,7 +26,7 @@
 #include <stddef.h>
 
 #include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
+#include <mach-bcmring/csp/dmacHw_reg.h>
 
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
 
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
index 1c639c8..eb7d3ae 100644
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -28,7 +28,7 @@
 #define _INTCHW_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 /* ---- Public Variable Externs ------------------------------------------ */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
index 56654d2..23ac669 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -69,7 +69,7 @@
 /*  */
 
 #if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <linux/interrupt.h>
 
 #define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
index 933ce68..4a1ecfa 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/cap_inline.h
@@ -16,7 +16,7 @@
 #define CAP_INLINE_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
+#include <mach-bcmring/csp/cap.h>
 #include <cfg_global.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
index 1619733..fe57b08 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_def.h
@@ -20,7 +20,7 @@
 #include <csp/stdint.h>
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
 
 /* ---- Public Constants and Types ---------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
index 03238c2..108209c 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_inline.h
@@ -19,8 +19,8 @@
 
 #include <csp/errno.h>
 #include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
+#include <mach-bcmring/csp/chipcHw_reg.h>
+#include <mach-bcmring/csp/chipcHw_def.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 typedef enum {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
index b162448..85b13d7 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/chipcHw_reg.h
@@ -23,9 +23,9 @@
 #ifndef CHIPCHW_REG_H
 #define CHIPCHW_REG_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 #include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
+#include <mach-bcmring/csp/ddrcReg.h>
 
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
index f1b68e2..462c099 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/ddrcReg.h
@@ -33,7 +33,7 @@ extern "C" {
 #include <csp/reg.h>
 #include <csp/stdint.h>
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
index f1ecf96..1f5263f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/dmacHw_reg.h
@@ -25,7 +25,7 @@
 #define _DMACHW_REG_H
 
 #include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Data type for 64 bit little endian register */
 typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
index cfa91be..aad4e17 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/hw_cfg.h
@@ -19,10 +19,10 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
+#include <mach-bcmring/csp/cap_inline.h>
 
 #if defined(__KERNEL__)
-#include <mach/memory_settings.h>
+#include <mach-bcmring/memory_settings.h>
 #else
 #include <hw_cfg.h>
 #endif
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
index 0aeb6a6..0770d7d 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/intcHw_reg.h
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/stdint.h>
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
index de92ec6..dcb1eae 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/mm_io.h
@@ -27,7 +27,7 @@
 #define _MM_IO_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #if !defined(CSP_SIMULATION)
 #include <cfg_global.h>
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
index d15f5f3..18279ce 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/secHw_def.h
@@ -26,7 +26,7 @@
 #ifndef SECHW_DEF_H
 #define SECHW_DEF_H
 
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Bit mask for various secure device */
 #define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
@@ -95,6 +95,6 @@ static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void);
 
-#include <mach/csp/secHw_inline.h>
+#include <mach-bcmring/csp/secHw_inline.h>
 
 #endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
index 3080ac7..e6069f5 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/csp/tmrHw_reg.h
@@ -23,8 +23,8 @@
 #ifndef _TMRHW_REG_H
 #define _TMRHW_REG_H
 
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
+#include <mach-bcmring/csp/mm_io.h>
+#include <mach-bcmring/csp/hw_cfg.h>
 /* Base address */
 #define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
index 7254378..366caa3 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/dma.h
@@ -28,7 +28,7 @@
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
 #include <csp/dmacHw.h>
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
index 2f316f0..8967896 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/entry-macro.S
@@ -17,9 +17,9 @@
  * Low-level IRQ helper macros for BCMRing-based platforms
  *
  */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/irqs.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 		ldr	\base, =(MM_IO_BASE_INTC0)
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
index 6ae20a6..c708efd 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/hardware.h
@@ -23,7 +23,7 @@
 
 #include <asm/sizes.h>
 #include <cfg_global.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* Hardware addresses of major areas.
  *  *_START is the physical address
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
index 387376f..ec773c2 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_nand.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/reg_umi.h>
+#include <mach-bcmring/reg_umi.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
index 0992842..f659cc1 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/reg_umi.h
@@ -31,7 +31,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <csp/reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 
diff --git a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
index 9c9821b..b11fb3f 100644
--- a/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
+++ b/arch/arm/mach-bcmring/include/mach-bcmring/uncompress.h
@@ -11,7 +11,7 @@
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
-#include <mach/csp/mm_addr.h>
+#include <mach-bcmring/csp/mm_addr.h>
 
 #define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
 #define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index 437fa68..aa88cac 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -22,12 +22,12 @@
 #include <linux/timer.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-bcmring/hardware.h>
 #include <asm/irq.h>
 
 #include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/csp/intcHw_reg.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 static void bcmring_mask_irq0(struct irq_data *d)
 {
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78e..411fa2b 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -17,8 +17,8 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
+#include <mach-bcmring/hardware.h>
+#include <mach-bcmring/csp/mm_io.h>
 
 #define IO_DESC(va, sz) { .virtual = va, \
 	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7..ba9754d 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include <csp/tmrHw.h>
 
-#include <mach/timer.h>
+#include <mach-bcmring/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
 /* The real time clock should probably be the real linux clocksource. */
 /* In the meantime, this file should agree with core.c as to the */
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3fb79a1..82ec281 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/sizes.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,7 +33,7 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
+#include <mach-clps711x/autcpu12.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index c314f49..6693600 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index a70147e..177fb74 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index f15293b..5b4fa62 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -28,7 +28,7 @@
 #include <linux/sched.h>
 
 #include <asm/sizes.h>
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 4372f06..6d3e94e 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/page.h>
 #include <asm/sizes.h>
  
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 3a3f0b7..12a1368 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/initrd.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
index 118b3d9..52bd3ef 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 		.macro	addruart, rp, rv, tmp
 #ifndef CONFIG_DEBUG_CLPS711X_UART2
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
index 56e5c2c..889521e 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/entry-macro.S
@@ -7,7 +7,7 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 
 		.macro	get_irqnr_preamble, base, tmp
 		.endm
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
index 13a64fc..29f3409 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/hardware.h
@@ -22,7 +22,7 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
 
-#include <mach/clps711x.h>
+#include <mach-clps711x/clps711x.h>
 
 #define CLPS711X_VIRT_BASE	IOMEM(0xff000000)
 
diff --git a/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h b/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
index 7b28d6a..92a5ee1 100644
--- a/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach-clps711x/uncompress.h
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <mach/clps711x.h>
+#include <mach-clps711x/clps711x.h>
 
 #ifdef CONFIG_DEBUG_CLPS711X_UART2
 #define SYSFLGx	SYSFLG2
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index bbc449f..b0b684f 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index f266d90..e83d055 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -24,7 +24,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <mach-clps711x/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
+#include <mach-clps711x/syspld.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2c5fb4c..6e663cf 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -30,8 +30,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/irqs.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 031805b..1c7da63 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -17,7 +17,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 #include "core.h"
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 1e40c99..ef5c80c 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -16,9 +16,9 @@
 #include <linux/compiler.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/pm.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/irqs.h>
+#include <mach-cns3xxx/pm.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
index 2ab96f8..a9712a6 100644
--- a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
+++ b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/irqs.h
@@ -15,7 +15,7 @@
 #define IRQ_LOCALWDOG		30
 #define IRQ_TC11MP_GIC_START	32
 
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 
 #ifndef NR_IRQS
 #error "NR_IRQS not defined by the board-specific files"
diff --git a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
index a91b605..8b2a4b6 100644
--- a/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
+++ b/arch/arm/mach-cns3xxx/include/mach-cns3xxx/uncompress.h
@@ -8,7 +8,7 @@
  */
 
 #include <asm/mach-types.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 
 #define AMBA_UART_DR(base)	(*(volatile unsigned char *)((base) + 0x00))
 #define AMBA_UART_LCRH(base)	(*(volatile unsigned char *)((base) + 0x2c))
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 3113283..873e6cd 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -20,7 +20,7 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <asm/mach/map.h>
-#include <mach/cns3xxx.h>
+#include <mach-cns3xxx/cns3xxx.h>
 #include "core.h"
 
 enum cns3xxx_access_type {
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 3645808..40b6e73 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -11,8 +11,8 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/atomic.h>
-#include <mach/cns3xxx.h>
-#include <mach/pm.h>
+#include <mach-cns3xxx/cns3xxx.h>
+#include <mach-cns3xxx/pm.h>
 #include "core.h"
 
 void cns3xxx_pwr_clk_en(unsigned int block)
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 1ce70a9..4ef9dab 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -15,7 +15,7 @@
 #include <linux/module.h>
 #include <linux/time.h>
 
-#include <mach/aemif.h>
+#include <mach-davinci/aemif.h>
 
 /* Timing value configuration */
 
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 0031864..c07754e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -26,13 +26,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/cp_intc.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/da8xx.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/usb.h>
+#include <mach-davinci/aemif.h>
+#include <mach-davinci/spi.h>
 
 #define DA830_EVM_PHY_ID		""
 /*
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 0149fb4..6fe905e 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -38,12 +38,12 @@
 #include <asm/mach/arch.h>
 #include <asm/system_info.h>
 
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/nand.h>
-#include <mach/mux.h>
-#include <mach/aemif.h>
-#include <mach/spi.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/aemif.h>
+#include <mach-davinci/spi.h>
 
 #define DA850_EVM_PHY_ID		"davinci_mdio-0:00"
 #define DA850_LCD_PWR_PIN		GPIO_TO_PIN(2, 8)
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 1c7b1f4..fc915d1 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,11 +26,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 8e77032..02eb053 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,11 +23,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 688a9c5..f661663 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -31,13 +31,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/mux.h>
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mmc.h>
-#include <mach/nand.h>
-#include <mach/keyscan.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/keyscan.h>
 
 #include <media/tvp514x.h>
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d34ed55..58ff3e7 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -30,14 +30,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
-#include <mach/aemif.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
+#include <mach-davinci/aemif.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 958679a..8f6ddc3 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -36,13 +36,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/serial.h>
-#include <mach/i2c.h>
-#include <mach/nand.h>
-#include <mach/clock.h>
-#include <mach/cdce949.h>
-#include <mach/aemif.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/cdce949.h>
+#include <mach-davinci/aemif.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index beecde3..dce12d5 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -23,12 +23,12 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <mach/common.h>
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/nand.h>
-#include <mach/mux.h>
-#include <mach/spi.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/spi.h>
 
 #define MITYOMAPL138_PHY_ID		""
 
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5de69f2..26034db 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -30,13 +30,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/nand.h>
-#include <mach/mmc.h>
-#include <mach/usb.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/nand.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index dc1208e..ee4ae67 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/cp_intc.h>
-#include <mach/da8xx.h>
-#include <mach/mux.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/mux.h>
 
 #define HAWKBOARD_PHY_ID		"davinci_mdio-0:07"
 #define DA850_HAWK_MMCSD_CD_PIN		GPIO_TO_PIN(3, 12)
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 9078acf..19c84ce 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -35,11 +35,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <mach/common.h>
-#include <mach/i2c.h>
-#include <mach/serial.h>
-#include <mach/mux.h>
-#include <mach/usb.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/usb.h>
 
 #include "davinci.h"
 
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ac4e003..1e58d68 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -30,11 +30,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
-#include <mach/mux.h>
-#include <mach/cp_intc.h>
-#include <mach/tnetv107x.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/cp_intc.h>
+#include <mach-davinci/tnetv107x.h>
 
 #define EVM_MMC_WP_GPIO		21
 #define EVM_MMC_CD_GPIO		24
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index f2232ca..3794178 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,8 +19,8 @@
 #include <linux/i2c.h>
 #include <linux/module.h>
 
-#include <mach/clock.h>
-#include <mach/cdce949.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/cdce949.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 34668ea..c26fd64 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -20,11 +20,11 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
+#include <mach-davinci/hardware.h>
 
-#include <mach/clock.h>
-#include <mach/psc.h>
-#include <mach/cputype.h>
+#include <mach-davinci/clock.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/cputype.h>
 #include "clock.h"
 
 static LIST_HEAD(clocks);
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 64b0f65..3e997d7 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -17,8 +17,8 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
-#include <mach/common.h>
-#include <mach/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cputype.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 006dae8..51b1513 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -18,8 +18,8 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/common.h>
-#include <mach/cp_intc.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/cp_intc.h>
 
 static inline unsigned int cp_intc_read(unsigned offset)
 {
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 4729eaa..4ef3927 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -26,9 +26,9 @@
 #include <linux/platform_device.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
-#include <mach/cpufreq.h>
-#include <mach/common.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/cpufreq.h>
+#include <mach-davinci/common.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 9107691..9d3d884c 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -20,8 +20,8 @@
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
 
-#include <mach/cpuidle.h>
-#include <mach/ddr2.h>
+#include <mach-davinci/cpuidle.h>
+#include <mach-davinci/ddr2.h>
 
 #define DAVINCI_CPUIDLE_MAX_STATES	2
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2..a482e57 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -14,13 +14,13 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/psc.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "clock.h"
 #include "mux.h"
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc84..7a16c6e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -20,15 +20,15 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/psc.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/cpufreq.h>
-#include <mach/pm.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/cpufreq.h>
+#include <mach-davinci/pm.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "clock.h"
 #include "mux.h"
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 8db0fc6..fe9c203 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <mach/hardware.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/keyscan.h>
+#include <mach-davinci/hardware.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 783eab6..d851270 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -17,11 +17,11 @@
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
 
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/da8xx.h>
-#include <mach/cpuidle.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/da8xx.h>
+#include <mach-davinci/cpuidle.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 29b17f7..e25ca91 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -19,10 +19,10 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/edma.h>
-#include <mach/tnetv107x.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/tnetv107x.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f96662..31fe1a8 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -14,14 +14,14 @@
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/irqs.h>
-#include <mach/cputype.h>
-#include <mach/mux.h>
-#include <mach/edma.h>
-#include <mach/mmc.h>
-#include <mach/time.h>
+#include <mach-davinci/hardware.h>
+#include <mach-davinci/i2c.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/mmc.h>
+#include <mach-davinci/time.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..5279a55 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -18,17 +18,17 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/irqs.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/spi.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/spi.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49de..8f55461 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -21,18 +21,18 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/irqs.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <mach/spi.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/keyscan.h>
+#include <mach-davinci/spi.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..6355eaf 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -15,16 +15,16 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/irqs.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1..0c9515e 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -16,16 +16,16 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/cputype.h>
-#include <mach/edma.h>
-#include <mach/irqs.h>
-#include <mach/psc.h>
-#include <mach/mux.h>
-#include <mach/time.h>
-#include <mach/serial.h>
-#include <mach/common.h>
-#include <mach/asp.h>
-#include <mach/gpio-davinci.h>
+#include <mach-davinci/cputype.h>
+#include <mach-davinci/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/psc.h>
+#include <mach-davinci/mux.h>
+#include <mach-davinci/time.h>
+#include <mach-davinci/serial.h>
+#include <mach-davinci/common.h>
+#include <mach-davinci/asp.h>
+#include <mach-davinci/gpio-davinci.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index a685e97..f0093a8 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -25,7 +25,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/edma.h>
+#include <mach-davinci/edma.h>
 
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT		0x00
diff --git a/arch/arm/mach-davinci/include/mach-davinci/asp.h b/arch/arm/mach-davinci/include/mach-davinci/asp.h
index 9aa2409..64e468f 100644
--- a/arch/arm/mach-davinci/include/mach-davinci/asp.h
+++ b/arch/arm/mach-davinci/include/mach-davinci/asp.h
@@ -4,8 +4,8 @@
 #ifndef __ASM_ARCH_DAVINCI_ASP_H
 #define __ASM_ARCH_DAVINCI_ASP_H
 
-#include <mach/irqs.h>
-#include <mach/edma.h>
+#include <mach-davinci/irqs.h>
+#include <mach-davinci/edma.h>
 
 /* Bases of dm644x and dm355 register banks */
 #define DAVINCI_ASP0_BASE	0x01E02000
---
Intentionally cut off for review. If you managed to read this far, you
get the idea. See the rest at
http://git.kernel.org/?p=linux/kernel/git/arm/arm-soc.git;a=commit;h=d59d6b49ed5287dd0131acda9428fdc0bb0a7365


From arnd at arndb.de  Tue Aug 21 12:04:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 21 Aug 2012 16:04:07 -0000
Subject: [RFC 1/4] ARM: autogenerate mach-foo/* and plat-foo/* header redirects
In-Reply-To: <1345564724-14466-1-git-send-email-arnd@arndb.de>
References: <1345564724-14466-1-git-send-email-arnd@arndb.de>
Message-ID: <1345564724-14466-2-git-send-email-arnd@arndb.de>

This is an attempt to simplify the duplicate header problem for
multiplatform kernels, in multiple steps:

1. (this patch)
   for each arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h file,
   generate a arch/arm/include/generated/mach/*.h file at build time,
   same for plat-*.

2. rename all arch/arm/mach-${MACHINE}/include/mach/*.h to
   arch/arm/mach-${MACHINE}/include/mach-${MACHINE}/*.h and
   arch/arm/plat-${PLAT}/include/plat/*.h to
   arch/arm/plat-${PLAT}/include/plat-${PLAT}/*.h

3. change all includes of <mach/*.h> to <mach-${MACHINE}/*.h>
   in all files where ${MACHINE} is known.

4. ...

5. Revert this patch again.

We can apply this patch at any time, and do step 2 at the end
of the next merge window to minimize the potential for conflicts.
We will also still need to deal with any inclusion of a mach/*
file, but out of the 6355 ones we have today, I expect only a
few hundred to remain after step 3 and they will be much easier
to spot.

I've picked the format <mach-foo/bar.h> to get a unique name because
it matches the directory name under arch/arm, but other names
would work with the same script, <mach/foo-bar.h> and <foo/bar.h>
have been suggested previously.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Makefile          |    1 +
 arch/arm/tools/Makefile    |    5 ++++
 arch/arm/tools/gen-headers |   57 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)
 create mode 100755 arch/arm/tools/gen-headers

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..761b077 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -274,6 +274,7 @@ boot := arch/arm/boot
 
 archprepare:
 	$(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h
+	$(Q)$(MAKE) $(build)=arch/arm/tools plat="$(plat-y)" machine="$(machine-y)" gen_headers
 
 # Convert bzImage to zImage
 bzImage: zImage
diff --git a/arch/arm/tools/Makefile b/arch/arm/tools/Makefile
index 635cb18..6e18ca9 100644
--- a/arch/arm/tools/Makefile
+++ b/arch/arm/tools/Makefile
@@ -8,3 +8,8 @@ include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
 	@echo '  Generating $@'
 	@mkdir -p $(dir $@)
 	$(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
+
+gen_headers:
+	$(Q)bash $(srctree)/$(src)/gen-headers $(srctree) $(objtree) $(machine) $(plat)
+
+.PHONY: gen_headers
diff --git a/arch/arm/tools/gen-headers b/arch/arm/tools/gen-headers
new file mode 100755
index 0000000..caa6a9a
--- /dev/null
+++ b/arch/arm/tools/gen-headers
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+SRC=$1
+OBJ=$2
+MACH=$3
+PLAT1=$4
+PLAT2=$5
+
+# create $3 to include $2 if it doesn't already have the correct
+# contents, or remove it if it's no longer needed.
+mkfile()
+{
+	if [ -e $1/$2 ] ; then
+		if [ ! -e $3 ] ; then
+			mkdir -p ${3%/*}
+			echo "#include <${2}>" > $3
+		elif [ "`cat $3`" != "#include <${2#./}>" ] ; then
+			echo "#include <${2}>" > $3
+		fi
+	elif [ ! -e $1/$2 -a -e $3 ] ; then
+		rm -f $3
+	fi
+}
+
+# list any header files that are present in the source or
+# destination directories
+find_files()
+{
+	pushd ${SRC}/arch/arm/$1-$2/include/$1-$2 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+	pushd ${OBJ}/arch/arm/include/generated/$1 >/dev/null 2>&1 &&
+	find . -type f -name \*.h -o -name \*.S &&
+	popd > /dev/null 2>&1
+}
+
+# process files in either mach-{MACH} or plat-${PLAT}
+mkfiles()
+{
+	mkdir -p ${OBJ}/arch/arm/include/generated/$1
+
+	FILES=`find_files $1 $2 | sort -u`
+	for i in ${FILES} ; do
+		mkfile "${SRC}/arch/arm/$1-$2/include/" "$1-$2/${i#./}" \
+			"${OBJ}/arch/arm/include/generated/$1/$i"
+	done
+}
+
+# always process mach-*
+mkfiles mach ${MACH}
+# process plat-* if applicable
+if [ -d ${SRC}/arch/arm/plat-${PLAT1} ]; then
+	mkfiles plat ${PLAT1}
+fi
+if [ -d ${SRC}/arch/arm/plat-${PLAT2} ]; then
+	mkfiles plat ${PLAT2}
+fi
-- 
1.7.10



From hdoyu at nvidia.com  Wed Aug 22 06:20:53 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 10:20:53 -0000
Subject: [RFC 1/4] ARM: dma-mapping: Refactor out to introduce
 __alloc_fill_pages
In-Reply-To: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345630830-9586-2-git-send-email-hdoyu@nvidia.com>

__alloc_fill_pages() allocates power of 2 page number allocation at
most repeatedly.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   40 ++++++++++++++++++++++++++++------------
 1 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7dc61ed..aec0c06 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -988,19 +988,10 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
 	spin_unlock_irqrestore(&mapping->lock, flags);
 }
 
-static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
+static int __alloc_fill_pages(struct page ***ppages, int count, gfp_t gfp)
 {
-	struct page **pages;
-	int count = size >> PAGE_SHIFT;
-	int array_size = count * sizeof(struct page *);
 	int i = 0;
-
-	if (array_size <= PAGE_SIZE)
-		pages = kzalloc(array_size, gfp);
-	else
-		pages = vzalloc(array_size);
-	if (!pages)
-		return NULL;
+	struct page **pages = *ppages;
 
 	while (count) {
 		int j, order = __fls(count);
@@ -1022,11 +1013,36 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
 		count -= 1 << order;
 	}
 
-	return pages;
+	return 0;
+
 error:
 	while (i--)
 		if (pages[i])
 			__free_pages(pages[i], 0);
+	return -ENOMEM;
+}
+
+static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
+					  gfp_t gfp)
+{
+	struct page **pages;
+	int count = size >> PAGE_SHIFT;
+	int array_size = count * sizeof(struct page *);
+	int err;
+
+	if (array_size <= PAGE_SIZE)
+		pages = kzalloc(array_size, gfp);
+	else
+		pages = vzalloc(array_size);
+	if (!pages)
+		return NULL;
+
+	err = __alloc_fill_pages(&pages, count, gfp);
+	if (err)
+		goto error
+
+	return pages;
+error:
 	if (array_size <= PAGE_SIZE)
 		kfree(pages);
 	else
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 22 06:20:54 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 10:20:54 -0000
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>

Makes use of the same atomic pool from DMA, and skips kernel page
mapping which can involves sleep'able operation at allocating a kernel
page table.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   22 ++++++++++++++++++----
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index aec0c06..9260107 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1028,7 +1028,6 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 	struct page **pages;
 	int count = size >> PAGE_SHIFT;
 	int array_size = count * sizeof(struct page *);
-	int err;
 
 	if (array_size <= PAGE_SIZE)
 		pages = kzalloc(array_size, gfp);
@@ -1037,9 +1036,20 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 	if (!pages)
 		return NULL;
 
-	err = __alloc_fill_pages(&pages, count, gfp);
-	if (err)
-		goto error
+	if (gfp & GFP_ATOMIC) {
+		struct page *page;
+		int i;
+		void *addr = __alloc_from_pool(size, &page);
+		if (!addr)
+			goto err_out;
+
+		for (i = 0; i < count; i++)
+			pages[i] = page + i;
+	} else {
+		int err = __alloc_fill_pages(&pages, count, gfp);
+		if (err)
+			goto error;
+	}
 
 	return pages;
 error:
@@ -1055,6 +1065,10 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
 	int count = size >> PAGE_SHIFT;
 	int array_size = count * sizeof(struct page *);
 	int i;
+
+	if (__free_from_pool(page_address(pages[0]), size))
+		return 0;
+
 	for (i = 0; i < count; i++)
 		if (pages[i])
 			__free_pages(pages[i], 0);
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 22 06:20:57 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 10:20:57 -0000
Subject: [RFC 3/4] ARM: dma-mapping: Return cpu addr when dma_alloc(GFP_ATOMIC)
In-Reply-To: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345630830-9586-4-git-send-email-hdoyu@nvidia.com>

Make dma_alloc{_attrs}() returns cpu address when
DMA_ATTR_NO_KERNEL_MAPPING && GFP_ATOMIC.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9260107..a0cd476 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1198,8 +1198,11 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	if (*handle == DMA_ERROR_CODE)
 		goto err_buffer;
 
-	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
+	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
+		if (gfp & GFP_ATOMIC)
+			return page_address(pages[0]);
 		return pages;
+	}
 
 	addr = __iommu_alloc_remap(pages, size, gfp, prot,
 				   __builtin_return_address(0));
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 22 06:21:19 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 22 Aug 2012 10:21:19 -0000
Subject: [RFC 4/4] ARM: dma-mapping: dma_{alloc,
 free}_coherent with empty attrs
In-Reply-To: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345630830-9586-5-git-send-email-hdoyu@nvidia.com>

There's possibility that this attrs be used later to set.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/include/asm/dma-mapping.h |   21 +++++++++++++++++----
 1 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index c27d855..96b67c7 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -125,8 +125,6 @@ extern int dma_supported(struct device *dev, u64 mask);
 extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 			   gfp_t gfp, struct dma_attrs *attrs);
 
-#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
-
 static inline void *dma_alloc_attrs(struct device *dev, size_t size,
 				       dma_addr_t *dma_handle, gfp_t flag,
 				       struct dma_attrs *attrs)
@@ -135,11 +133,21 @@ static inline void *dma_alloc_attrs(struct device *dev, size_t size,
 	void *cpu_addr;
 	BUG_ON(!ops);
 
+	if (flag & GFP_ATOMIC)
+		dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
+
 	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
 	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
 	return cpu_addr;
 }
 
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+				       dma_addr_t *dma_handle, gfp_t flag)
+{
+	DEFINE_DMA_ATTRS(attrs);
+	return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
+}
+
 /**
  * arm_dma_free - free memory allocated by arm_dma_alloc
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -157,8 +165,6 @@ static inline void *dma_alloc_attrs(struct device *dev, size_t size,
 extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 			 dma_addr_t handle, struct dma_attrs *attrs);
 
-#define dma_free_coherent(d, s, c, h) dma_free_attrs(d, s, c, h, NULL)
-
 static inline void dma_free_attrs(struct device *dev, size_t size,
 				     void *cpu_addr, dma_addr_t dma_handle,
 				     struct dma_attrs *attrs)
@@ -170,6 +176,13 @@ static inline void dma_free_attrs(struct device *dev, size_t size,
 	ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
+static inline void dma_free_coherent(struct device *dev, size_t size,
+				     void *cpu_addr, dma_addr_t dma_handle)
+{
+	DEFINE_DMA_ATTRS(attrs);
+	return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
+}
+
 /**
  * arm_dma_mmap - map a coherent DMA allocation into user space
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
-- 
1.7.5.4



From pullip.cho at samsung.com  Wed Aug 22 08:47:09 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 22 Aug 2012 12:47:09 -0000
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
Message-ID: <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>

Hi.

vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic
context.


On Wed, Aug 22, 2012 at 7:20 PM, Hiroshi Doyu <hdoyu at nvidia.com> wrote:
> Makes use of the same atomic pool from DMA, and skips kernel page
> mapping which can involves sleep'able operation at allocating a kernel
> page table.
>
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   22 ++++++++++++++++++----
>  1 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index aec0c06..9260107 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1028,7 +1028,6 @@ static struct page **__iommu_alloc_buffer(struct
device *dev, size_t size,
>         struct page **pages;
>         int count = size >> PAGE_SHIFT;
>         int array_size = count * sizeof(struct page *);
> -       int err;
>
>         if (array_size <= PAGE_SIZE)
>                 pages = kzalloc(array_size, gfp);
> @@ -1037,9 +1036,20 @@ static struct page **__iommu_alloc_buffer(struct
device *dev, size_t size,
>         if (!pages)
>                 return NULL;
>
> -       err = __alloc_fill_pages(&pages, count, gfp);
> -       if (err)
> -               goto error
> +       if (gfp & GFP_ATOMIC) {
> +               struct page *page;
> +               int i;
> +               void *addr = __alloc_from_pool(size, &page);
> +               if (!addr)
> +                       goto err_out;
> +
> +               for (i = 0; i < count; i++)
> +                       pages[i] = page + i;
> +       } else {
> +               int err = __alloc_fill_pages(&pages, count, gfp);
> +               if (err)
> +                       goto error;
> +       }
>
>         return pages;
>  error:
> @@ -1055,6 +1065,10 @@ static int __iommu_free_buffer(struct device *dev,
struct page **pages, size_t s
>         int count = size >> PAGE_SHIFT;
>         int array_size = count * sizeof(struct page *);
>         int i;
> +
> +       if (__free_from_pool(page_address(pages[0]), size))
> +               return 0;
> +
>         for (i = 0; i < count; i++)
>                 if (pages[i])
>                         __free_pages(pages[i], 0);
> --
> 1.7.5.4
>
> --
> To unsubscribe, send a message with 'unsubscribe linux-mm' in
> the body to majordomo at kvack.org.  For more info on Linux MM,
> see: http://www.linux-mm.org/ .
> Don't email: <a href=mailto:"dont at kvack.org"> email at kvack.org </a>
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From ludovic.desroches at atmel.com  Wed Aug 22 11:00:16 2012
From: ludovic.desroches at atmel.com (ludovic.desroches)
Date: Wed, 22 Aug 2012 15:00:16 -0000
Subject: JFFS2 issue with v3.5.x and later on Atmel chips at least (was: Kernel
 oops since v3.5.x on Atmel chips)
In-Reply-To: <5034B45A.5060107@atmel.com>
References: <5034B45A.5060107@atmel.com>
Message-ID: <5034F3F8.9080802@atmel.com>

Le 08/22/2012 12:28 PM, ludovic.desroches a ?crit :
> Hi,
>
> Doing some tests with the help of Lava (a Linaro tool), I get some
> kernel oops with 3.5.x on several chips at91sam9260, at91sam9261 and
> at91sam9m10g45.
>
> Most of the time the oops comes from the cascade BUG() call in
> kernel/timer.c but sometimes it comes from a bad PC value.
>
> With Lava, I got the crash each time. It happens after mounting a mtd
> partition, copying a file from it, removing this file from the flash
> memory and then unmounting the mtd partition.
>
> I couldn't reproduce manually this issue so maybe there is something
> related to time...
>
> Here I paste the usual oops and the one with the bad PC value:
>
> Starting kernel ...
>
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0
> Linux version 3.5.0 (ldesroches at ibiza) (gcc version 4.6.1 (Ubuntu/Linaro
> 4.6.1-9ubuntu3) ) #10 Wed Aug 22 09:17:23 CEST 2012
> CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
> CPU: VIVT data cache, VIVT instruction cache
> Machine: Atmel AT91SAM9260-EK
> Memory policy: ECC disabled, Data cache writeback
> AT91: Detected soc type: at91sam9260
> AT91: Detected soc subtype: Unknown
> AT91: sram at 0x2ff000 of 0x2000 mapped at 0xfef76000
> Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
> Kernel command line: mem=64M console=ttyS0,115200
> mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,70M(rootfs),-(data)
> root=/dev/mtdblock1 rw rootfstype=jffs2 ip=192.168.1.16:::255.255.255.0:::
> PID hash table entries: 256 (order: -2, 1024 bytes)
> Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
> Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
> Memory: 64MB = 64MB total
> Memory: 60848k/60848k available, 4688k reserved, 0K highmem
> Virtual kernel memory layout:
>      vector  : 0xffff0000 - 0xffff1000   (   4 kB)
>      fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
>      vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
>      lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
>      modules : 0xbf000000 - 0xc0000000   (  16 MB)
>        .text : 0xc0008000 - 0xc039fee8   (3680 kB)
>        .init : 0xc03a0000 - 0xc03bd7c4   ( 118 kB)
>        .data : 0xc03be000 - 0xc03e8f00   ( 172 kB)
>         .bss : 0xc03e8f24 - 0xc03fb138   (  73 kB)
> NR_IRQS:192
> AT91: 96 gpio irqs in 3 banks
> sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every
> 4294967286ms
> Console: colour dummy device 80x30
> Calibrating delay loop... 98.71 BogoMIPS (lpj=493568)
> pid_max: default: 32768 minimum: 301
> Mount-cache hash table entries: 512
> CPU: Testing write buffer coherency: ok
> Setting up static identity map for 0x202af150 - 0x202af1a8
> devtmpfs: initialized
> NET: Registered protocol family 16
> AT91: Power Management (with slow clock mode)
> AT91: Starting after software reset
> bio: create slab <bio-0> at 0
> SCSI subsystem initialized
> usbcore: registered new interface driver usbfs
> usbcore: registered new interface driver hub
> usbcore: registered new device driver usb
> Advanced Linux Sound Architecture Driver Version 1.0.25.
> Switching to clocksource pit
> cfg80211: Calling CRDA to update world regulatory domain
> NET: Registered protocol family 2
> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> TCP established hash table entries: 2048 (order: 2, 16384 bytes)
> TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
> TCP: Hash tables configured (established 2048 bind 2048)
> TCP: reno registered
> UDP hash table entries: 256 (order: 0, 4096 bytes)
> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
> NET: Registered protocol family 1
> RPC: Registered named UNIX socket transport module.
> RPC: Registered udp transport module.
> RPC: Registered tcp transport module.
> RPC: Registered tcp NFSv4.1 backchannel transport module.
> jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
> msgmni has been set to 118
> io scheduler noop registered (default)
> atmel_usart.0: ttyS0 at MMIO 0xfffff200 (irq = 1) is a ATMEL_SERIAL
> console [ttyS0] enabled
> atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL
> atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL
> brd: module loaded
> loop: module loaded
> atmel_nand: Use On Flash BBT
> atmel_nand atmel_nand: No DMA support for NAND access.
> NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB
> 3,3V 8-bit), page size: 2048, OOB size: 64
> Bad block table found at page 131008, version 0x01
> Bad block table found at page 130944, version 0x01
> nand_read_bbt: bad block at 0x000009840000
> nand_read_bbt: bad block at 0x00000fb80000
> 3 cmdlinepart partitions found on MTD device atmel_nand
> Creating 3 MTD partitions on "atmel_nand":
> 0x000000000000-0x000000400000 : "bootstrap/uboot/kernel"
> 0x000000400000-0x000004a00000 : "rootfs"
> 0x000004a00000-0x000010000000 : "data"
> MACB_mii_bus: probed
> macb macb: eth0: Cadence MACB at 0xfffc4000 irq 21 (3a:1f:34:08:54:54)
> macb macb: eth0: attached PHY driver [Davicom DM9161A]
> (mii_bus:phy_addr=macb-ffffffff:00, irq=-1)
> ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
> at91_ohci at91_ohci: can't request overcurrent gpio 0
> at91_ohci at91_ohci: AT91 OHCI
> at91_ohci at91_ohci: new USB bus registered, assigned bus number 1
> at91_ohci at91_ohci: irq 20, io mem 0x00500000
> usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
> usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
> usb usb1: Product: AT91 OHCI
> usb usb1: Manufacturer: Linux 3.5.0 ohci_hcd
> usb usb1: SerialNumber: at91
> hub 1-0:1.0: USB hub found
> hub 1-0:1.0: 2 ports detected
> usbcore: registered new interface driver cdc_acm
> cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
> Initializing USB Mass Storage driver...
> usbcore: registered new interface driver usb-storage
> USB Mass Storage support registered.
> mousedev: PS/2 mouse device common for all mice
> TCP: cubic registered
> NET: Registered protocol family 17
> lib80211: common routines for IEEE802.11 drivers
> VFP support v0.3: not present
> input: gpio-keys as /devices/platform/gpio-keys/input/input0
> /home/ldesroches/workspace/linux/drivers/rtc/hctosys.c: unable to open
> rtc device (rtc0)
> IP-Config: Complete:
>       device=eth0, addr=192.168.1.16, mask=255.255.255.0,
> gw=255.255.255.255
>       host=192.168.1.16, domain=, nis-domain=(none)
>       bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=
> ALSA device list:
>    No soundcards found.
> macb macb: eth0: link up (100/Full)
> jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
> VFS: Mounted root (jffs2 filesystem) on device 31:1.
> devtmpfs: mounted
> Freeing init memory: 116K
> Starting logging: OK
> Populating  using udev: udevd[468]: starting version 182
> done
> Starting portmap: done
> Initializing random number generator... done.
> Starting network...
> ip: RTNETLINK answers: File exists
> Starting sshd: OK
>
> Welcome to Buildroot
> at91 login: root
> [root at at91 ~]#
> [root at at91 ~]#
> [root at at91 ~]# export PS1="$PS1 [rc=$(echo \$?)]: "
> [root at at91 ~]#  [rc=0]: mount -t jffs2 /dev/mtdblock2 /mnt/
> jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
> o_at91_lava/tmp [rc=0]: rm -rf /tmp/lava_results.tgz
> /tmp//srv/lava/instances/rf
> [root at at91 ~]#  [rc=0]: mkdir -p /tmp//srv/lava/instances/rfo_at91_lava/tmp
> tmp//srv/lava/instances/rfo_at91_lava/tmp/instances/rfo_at91_lava/tmp/*.bundle
> /
> eroot at at91 ~]#  [rc=0]: rm -f
> /mnt//srv/lava/instances/rfo_at91_lava/tmp/*.bundl
> [root at at91 ~]#  [rc=0]: umount /mnt/
> [root at at91 ~]#  [rc=0]: ------------[ cut here ]------------
> kernel BUG at /home/ldesroches/workspace/linux/kernel/timer.c:1091!
> Internal error: Oops - BUG: 0 [#1] ARM
> Modules linked in:
> CPU: 0    Not tainted  (3.5.0 #10)
> PC is at cascade+0x54/0x78
> LR is at cascade+0x60/0x78
> pc : [<c0023c80>]    lr : [<c0023c8c>]    psr: a0000093
> sp : c03bfec8  ip : ffffae00  fp : 00000000
> r10: c03ee540  r9 : 0000000a  r8 : 00000100
> r7 : c03bfec8  r6 : c03bfec8  r5 : 0000002e  r4 : c03ee6a0
> r3 : 00000000  r2 : 00000068  r1 : c3a60738  r0 : c03ee9ec
> Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
> Control: 0005317f  Table: 23a58000  DAC: 00000017
> Process swapper (pid: 0, stack limit = 0xc03be270)
> Stack: (0xc03bfec8 to 0xc03c0000)
> fec0:                   c03faf70 c3a60738 0000002e c03ee6a0 c03be000
> 00000000
> fee0: c03ee560 c0023d98 c0145bc4 c3952ba0 00000000 00000000 c03cddf4
> 00000001
> ff00: 00000004 c03be000 c03ee560 00000100 c03ee540 c001f4b0 000027da
> c03cddf4
> ff20: 00000000 00000001 c03bff9c 00000001 00000000 fefff000 c03bff9c
> 20004000
> ff40: 41069265 203b834c 00000000 c001f890 fefff000 c000dfc8 c000e0cc
> c000e0e0
> ff60: a0000013 c000d398 00000000 0005317f 0005217f a0000013 c03be000
> c03c8f54
> ff80: c03e8fe8 c047c300 20004000 41069265 203b834c 00000000 a00000d3
> c03bffb0
> ffa0: c000e0cc c000e0e0 a0000013 ffffffff c000e0b4 c000e27c c03c60b0
> ffffffff
> ffc0: c03b9784 c03a070c ffffffff ffffffff c03a0274 00000000 00000000
> c03b9784
> ffe0: 00000000 00053175 c03c603c c03b9780 c03c8f4c 20008040 00000000
> 00000000
> [<c0023c80>] (cascade+0x54/0x78) from [<c0023d98>]
> (run_timer_softirq+0x68/0x1f4)
> [<c0023d98>] (run_timer_softirq+0x68/0x1f4) from [<c001f4b0>]
> (__do_softirq+0x7c/0x110)
> [<c001f4b0>] (__do_softirq+0x7c/0x110) from [<c001f890>]
> (irq_exit+0x40/0x4c)
> [<c001f890>] (irq_exit+0x40/0x4c) from [<c000dfc8>] (handle_IRQ+0x74/0x98)
> [<c000dfc8>] (handle_IRQ+0x74/0x98) from [<c000d398>] (__irq_svc+0x38/0x60)
> [<c000d398>] (__irq_svc+0x38/0x60) from [<c000e0e0>]
> (default_idle+0x2c/0x34)
> [<c000e0e0>] (default_idle+0x2c/0x34) from [<c000e27c>]
> (cpu_idle+0x78/0xd8)
> [<c000e27c>] (cpu_idle+0x78/0xd8) from [<c03a070c>]
> (start_kernel+0x280/0x2d0)
> Code: e591300c e3c33001 e1540003 0a000000 (e7f001f2)
> ---[ end trace 6105dc3872c7de5d ]---
> Kernel panic - not syncing: Fatal exception in interrupt
>
>
>
>
>
> Starting kernel ...
>
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0
> Linux version 3.5.0 (ldesroches at ibiza) (gcc version 4.6.1 (Ubuntu/Linaro
> 4.6.1-9ubuntu3) ) #10 Wed Aug 22 09:17:23 CEST 2012
> CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
> CPU: VIVT data cache, VIVT instruction cache
> Machine: Atmel AT91SAM9260-EK
> Memory policy: ECC disabled, Data cache writeback
> AT91: Detected soc type: at91sam9260
> AT91: Detected soc subtype: Unknown
> AT91: sram at 0x2ff000 of 0x2000 mapped at 0xfef76000
> Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
> Kernel command line: mem=64M console=ttyS0,115200
> mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,70M(rootfs),-(data)
> root=/dev/mtdblock1 rw rootfstype=jffs2 ip=192.168.1.16:::255.255.255.0:::
> PID hash table entries: 256 (order: -2, 1024 bytes)
> Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
> Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
> Memory: 64MB = 64MB total
> Memory: 60848k/60848k available, 4688k reserved, 0K highmem
> Virtual kernel memory layout:
>      vector  : 0xffff0000 - 0xffff1000   (   4 kB)
>      fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
>      vmalloc : 0xc4800000 - 0xff000000   ( 936 MB)
>      lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
>      modules : 0xbf000000 - 0xc0000000   (  16 MB)
>        .text : 0xc0008000 - 0xc039fee8   (3680 kB)
>        .init : 0xc03a0000 - 0xc03bd7c4   ( 118 kB)
>        .data : 0xc03be000 - 0xc03e8f00   ( 172 kB)
>         .bss : 0xc03e8f24 - 0xc03fb138   (  73 kB)
> NR_IRQS:192
> AT91: 96 gpio irqs in 3 banks
> sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every
> 4294967286ms
> Console: colour dummy device 80x30
> Calibrating delay loop... 98.71 BogoMIPS (lpj=493568)
> pid_max: default: 32768 minimum: 301
> Mount-cache hash table entries: 512
> CPU: Testing write buffer coherency: ok
> Setting up static identity map for 0x202af150 - 0x202af1a8
> devtmpfs: initialized
> NET: Registered protocol family 16
> AT91: Power Management (with slow clock mode)
> AT91: Starting after software reset
> bio: create slab <bio-0> at 0
> SCSI subsystem initialized
> usbcore: registered new interface driver usbfs
> usbcore: registered new interface driver hub
> usbcore: registered new device driver usb
> Advanced Linux Sound Architecture Driver Version 1.0.25.
> Switching to clocksource pit
> cfg80211: Calling CRDA to update world regulatory domain
> NET: Registered protocol family 2
> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> TCP established hash table entries: 2048 (order: 2, 16384 bytes)
> TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
> TCP: Hash tables configured (established 2048 bind 2048)
> TCP: reno registered
> UDP hash table entries: 256 (order: 0, 4096 bytes)
> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
> NET: Registered protocol family 1
> RPC: Registered named UNIX socket transport module.
> RPC: Registered udp transport module.
> RPC: Registered tcp transport module.
> RPC: Registered tcp NFSv4.1 backchannel transport module.
> jffs2: version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
> msgmni has been set to 118
> io scheduler noop registered (default)
> atmel_usart.0: ttyS0 at MMIO 0xfffff200 (irq = 1) is a ATMEL_SERIAL
> console [ttyS0] enabled
> atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL
> atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL
> brd: module loaded
> loop: module loaded
> atmel_nand: Use On Flash BBT
> atmel_nand atmel_nand: No DMA support for NAND access.
> NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB
> 3,3V 8-bit), page size: 2048, OOB size: 64
> Bad block table found at page 131008, version 0x01
> Bad block table found at page 130944, version 0x01
> nand_read_bbt: bad block at 0x000009840000
> nand_read_bbt: bad block at 0x00000fb80000
> 3 cmdlinepart partitions found on MTD device atmel_nand
> Creating 3 MTD partitions on "atmel_nand":
> 0x000000000000-0x000000400000 : "bootstrap/uboot/kernel"
> 0x000000400000-0x000004a00000 : "rootfs"
> 0x000004a00000-0x000010000000 : "data"
> MACB_mii_bus: probed
> macb macb: eth0: Cadence MACB at 0xfffc4000 irq 21 (3a:1f:34:08:54:54)
> macb macb: eth0: attached PHY driver [Davicom DM9161A]
> (mii_bus:phy_addr=macb-ffffffff:00, irq=-1)
> ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
> at91_ohci at91_ohci: can't request overcurrent gpio 0
> at91_ohci at91_ohci: AT91 OHCI
> at91_ohci at91_ohci: new USB bus registered, assigned bus number 1
> at91_ohci at91_ohci: irq 20, io mem 0x00500000
> usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
> usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
> usb usb1: Product: AT91 OHCI
> usb usb1: Manufacturer: Linux 3.5.0 ohci_hcd
> usb usb1: SerialNumber: at91
> hub 1-0:1.0: USB hub found
> hub 1-0:1.0: 2 ports detected
> usbcore: registered new interface driver cdc_acm
> cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
> Initializing USB Mass Storage driver...
> usbcore: registered new interface driver usb-storage
> USB Mass Storage support registered.
> mousedev: PS/2 mouse device common for all mice
> TCP: cubic registered
> NET: Registered protocol family 17
> lib80211: common routines for IEEE802.11 drivers
> VFP support v0.3: not present
> input: gpio-keys as /devices/platform/gpio-keys/input/input0
> /home/ldesroches/workspace/linux/drivers/rtc/hctosys.c: unable to open
> rtc device (rtc0)
> IP-Config: Complete:
>       device=eth0, addr=192.168.1.16, mask=255.255.255.0,
> gw=255.255.255.255
>       host=192.168.1.16, domain=, nis-domain=(none)
>       bootserver=255.255.255.255, rootserver=255.255.255.255, rootpath=
> ALSA device list:
>    No soundcards found.
> macb macb: eth0: link up (100/Full)
> jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
> VFS: Mounted root (jffs2 filesystem) on device 31:1.
> devtmpfs: mounted
> Freeing init memory: 116K
> Starting logging: OK
> Populating  using udev: done
> udevd[468]: starting version 182
> Starting portmap: done
> Initializing random number generator... done.
> Starting network...
> ip: RTNETLINK answers: File exists
> Starting sshd: OK
>
> Welcome to Buildroot
> at91 login: root
> [root at at91 ~]#
> [root at at91 ~]#
> [root at at91 ~]# export PS1="$PS1 [rc=$(echo \$?)]: "
> [root at at91 ~]#  [rc=0]: mount -t jffs2 /dev/mtdblock2 /mnt/
> jffs2: Empty flash at 0x01fb1c68 ends at 0x01fb2000
> o_at91_lava/tmp [rc=0]: rm -rf /tmp/lava_results.tgz
> /tmp//srv/lava/instances/rf
> [root at at91 ~]#  [rc=0]: mkdir -p /tmp//srv/lava/instances/rfo_at91_lava/tmp
> tmp//srv/lava/instances/rfo_at91_lava/tmp/instances/rfo_at91_lava/tmp/*.bundle
> /
> eroot at at91 ~]#  [rc=0]: rm -f
> /mnt//srv/lava/instances/rfo_at91_lava/tmp/*.bundl
> [root at at91 ~]#  [rc=0]: umount /mnt/
> [root at at91 ~]#  [rc=0]: Unable to handle kernel paging request at
> virtual address 0d0c951c
> pgd = c0004000
> [0d0c951c] *pgd=00000000
> Internal error: Oops: 80000005 [#1] ARM
> Modules linked in:
> CPU: 0    Not tainted  (3.5.0 #10)
> PC is at 0xd0c951c
> LR is at run_timer_softirq+0x144/0x1f4
> pc : [<0d0c951c>]    lr : [<c0023e74>]    psr: 20000013
> sp : c03bfee8  ip : 00200200  fp : 00000000
> r10: 0d0c951c  r9 : 0000000a  r8 : c03bfef0
> r7 : c03ee560  r6 : 00000100  r5 : c03be000  r4 : c03ee6a0
> r3 : 20000013  r2 : 00000000  r1 : c03bfef0  r0 : b5a01535
> Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
> Control: 0005317f  Table: 23a58000  DAC: 00000017
> Process swapper (pid: 0, stack limit = 0xc03be270)
> Stack: (0xc03bfee8 to 0xc03c0000)
> fee0:                   c0145bc4 c396dba0 c03bfef0 c03bfef0 c03cddf4
> 00000001
> ff00: 00000004 c03be000 c03ee560 00000100 c03ee540 c001f4b0 00002870
> c03cddf4
> ff20: 00000000 00000001 c03bff9c 00000001 00000000 fefff000 c03bff9c
> 20004000
> ff40: 41069265 203b834c 00000000 c001f890 fefff000 c000dfc8 c000e0cc
> c000e0e0
> ff60: a0000013 c000d398 00000000 0005317f 0005217f a0000013 c03be000
> c03c8f54
> ff80: c03e8fe8 c047c300 20004000 41069265 203b834c 00000000 a00000d3
> c03bffb0
> ffa0: c000e0cc c000e0e0 a0000013 ffffffff c000e0b4 c000e27c c03c60b0
> ffffffff
> ffc0: c03b9784 c03a070c ffffffff ffffffff c03a0274 00000000 00000000
> c03b9784
> ffe0: 00000000 00053175 c03c603c c03b9780 c03c8f4c 20008040 00000000
> 00000000
> [<c0023e74>] (run_timer_softirq+0x144/0x1f4) from [<c001f4b0>]
> (__do_softirq+0x7c/0x110)
> [<c001f4b0>] (__do_softirq+0x7c/0x110) from [<c001f890>]
> (irq_exit+0x40/0x4c)
> [<c001f890>] (irq_exit+0x40/0x4c) from [<c000dfc8>] (handle_IRQ+0x74/0x98)
> [<c000dfc8>] (handle_IRQ+0x74/0x98) from [<c000d398>] (__irq_svc+0x38/0x60)
> [<c000d398>] (__irq_svc+0x38/0x60) from [<c000e0e0>]
> (default_idle+0x2c/0x34)
> [<c000e0e0>] (default_idle+0x2c/0x34) from [<c000e27c>]
> (cpu_idle+0x78/0xd8)
> [<c000e27c>] (cpu_idle+0x78/0xd8) from [<c03a070c>]
> (start_kernel+0x280/0x2d0)
> Code: bad PC value
> ---[ end trace f65db9c681fbd6e3 ]---
> Kernel panic - not syncing: Fatal exception in interrupt
>
>
>
> Regards
>
> Ludovic
>
>

After bisection the commit causing this issue is:

commit 8bdc81c5069e43755d6e59e5e990e21ca200e8e2
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Mon May 7 19:56:53 2012 +0300

     jffs2: get rid of jffs2_sync_super

     Currently JFFS2 file-system maps the VFS "superblock" abstraction 
to the
     write-buffer. Namely, it uses VFS services to synchronize the 
write-buffer
     periodically.

     The whole "superblock write-out" VFS infrastructure is served by the
     'sync_supers()' kernel thread, which wakes up every 5 (by default) 
seconds and
     writes out all dirty superblock using the '->write_super()' 
call-back. But the
     problem with this thread is that it wastes power by waking up the 
system every
     5 seconds no matter what. So we want to kill it completely and 
thus, we need to
     make file-systems to stop using the '->write_super' VFS service, 
and then
     remove it together with the kernel thread.

     This patch switches the JFFS2 write-buffer management from
     '->write_super()'/'->s_dirt' to a delayed work. Instead of setting 
the 's_dirt'
     flag we just schedule a delayed work for synchronizing the 
write-buffer.

     Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
     Signed-off-by: Al Viro <viro at zeniv.linux.org.uk>



Once reverted my issue disappeared. Tests have been done on at91sam9m10g45.

Regards

Ludovic


From hdoyu at nvidia.com  Thu Aug 23 02:10:26 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:10:26 +0300
Subject: [v2 1/4] ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
In-Reply-To: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345702229-9539-2-git-send-email-hdoyu@nvidia.com>

Check the given range("start", "size") is included in "atomic_pool" or not.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   25 +++++++++++++++++++------
 1 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 601da7a..aca2fd0 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -492,19 +492,32 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
+static bool __in_atomic_pool(void *start, size_t size)
+{
+	struct dma_pool *pool = &atomic_pool;
+	void *end = start + size;
+	void *pool_start = pool->vaddr;
+	void *pool_end = pool->vaddr + pool->size;
+
+	if (start < pool_start || start > pool_end)
+		return false;
+
+	if (end > pool_end) {
+		WARN(1, "freeing wrong coherent size from pool\n");
+		return false;
+	}
+
+	return true;
+}
+
 static int __free_from_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
 	unsigned long pageno, count;
 	unsigned long flags;
 
-	if (start < pool->vaddr || start > pool->vaddr + pool->size)
-		return 0;
-
-	if (start + size > pool->vaddr + pool->size) {
-		WARN(1, "freeing wrong coherent size from pool\n");
+	if (!__in_atomic_pool(start, size))
 		return 0;
-	}
 
 	pageno = (start - pool->vaddr) >> PAGE_SHIFT;
 	count = size >> PAGE_SHIFT;
-- 
1.7.5.4



From hdoyu at nvidia.com  Thu Aug 23 02:10:28 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:10:28 +0300
Subject: [v2 3/4] ARM: dma-mapping: Refactor out to introduce
 __alloc_fill_pages
In-Reply-To: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345702229-9539-4-git-send-email-hdoyu@nvidia.com>

__alloc_fill_pages() allocates power of 2 page number allocation at
most repeatedly.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   50 ++++++++++++++++++++++++++++++--------------
 1 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index b64475a..7ab016b 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1022,20 +1022,11 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
 	spin_unlock_irqrestore(&mapping->lock, flags);
 }
 
-static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
+static int __alloc_fill_pages(struct page ***ppages, int count, gfp_t gfp)
 {
-	struct page **pages;
-	int count = size >> PAGE_SHIFT;
-	int array_size = count * sizeof(struct page *);
+	struct page **pages = *ppages;
 	int i = 0;
 
-	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
-		pages = kzalloc(array_size, gfp);
-	else
-		pages = vzalloc(array_size);
-	if (!pages)
-		return NULL;
-
 	while (count) {
 		int j, order = __fls(count);
 
@@ -1045,22 +1036,49 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
 		if (!pages[i])
 			goto error;
 
-		if (order)
+		if (order) {
 			split_page(pages[i], order);
-		j = 1 << order;
-		while (--j)
-			pages[i + j] = pages[i] + j;
+			j = 1 << order;
+			while (--j)
+				pages[i + j] = pages[i] + j;
+		}
 
 		__dma_clear_buffer(pages[i], PAGE_SIZE << order);
 		i += 1 << order;
 		count -= 1 << order;
 	}
 
-	return pages;
+	return 0;
+
 error:
 	while (i--)
 		if (pages[i])
 			__free_pages(pages[i], 0);
+	return -ENOMEM;
+}
+
+static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
+					  gfp_t gfp)
+{
+	struct page **pages;
+	int count = size >> PAGE_SHIFT;
+	int array_size = count * sizeof(struct page *);
+	int err;
+
+	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
+		pages = kzalloc(array_size, gfp);
+	else
+		pages = vzalloc(array_size);
+	if (!pages)
+		return NULL;
+
+	err = __alloc_fill_pages(&pages, count, gfp);
+	if (err)
+		goto error
+
+	return pages;
+
+error:
 	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
 		kfree(pages);
 	else
-- 
1.7.5.4



From hdoyu at nvidia.com  Thu Aug 23 02:10:27 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:10:27 +0300
Subject: [v2 2/4] ARM: dma-mapping: Use kzalloc() with GFP_ATOMIC
In-Reply-To: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345702229-9539-3-git-send-email-hdoyu@nvidia.com>

Use kzalloc() with GFP_ATOMIC instead of vzalloc(). At freeing,
__in_atomic_pool() checks if it comes from atomic_pool or not.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index aca2fd0..b64475a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1029,7 +1029,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
 	int array_size = count * sizeof(struct page *);
 	int i = 0;
 
-	if (array_size <= PAGE_SIZE)
+	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
 		pages = kzalloc(array_size, gfp);
 	else
 		pages = vzalloc(array_size);
@@ -1061,7 +1061,7 @@ error:
 	while (i--)
 		if (pages[i])
 			__free_pages(pages[i], 0);
-	if (array_size <= PAGE_SIZE)
+	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
 		kfree(pages);
 	else
 		vfree(pages);
@@ -1076,7 +1076,8 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
 	for (i = 0; i < count; i++)
 		if (pages[i])
 			__free_pages(pages[i], 0);
-	if (array_size <= PAGE_SIZE)
+	if ((array_size <= PAGE_SIZE) ||
+	    __in_atomic_pool(page_address(pages[0]), size))
 		kfree(pages);
 	else
 		vfree(pages);
-- 
1.7.5.4



From hdoyu at nvidia.com  Thu Aug 23 02:10:29 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 23 Aug 2012 09:10:29 +0300
Subject: [v2 4/4] ARM: dma-mapping: IOMMU allocates pages from atomic_pool
 with GFP_ATOMIC
In-Reply-To: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
References: <1345702229-9539-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345702229-9539-5-git-send-email-hdoyu@nvidia.com>

Makes use of the same atomic pool from DMA, and skips kernel page
mapping which can involve sleep'able operations at allocating a kernel
page table.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   30 +++++++++++++++++++++++++-----
 1 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 7ab016b..433312a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1063,7 +1063,6 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 	struct page **pages;
 	int count = size >> PAGE_SHIFT;
 	int array_size = count * sizeof(struct page *);
-	int err;
 
 	if ((array_size <= PAGE_SIZE) || (gfp & GFP_ATOMIC))
 		pages = kzalloc(array_size, gfp);
@@ -1072,9 +1071,20 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
 	if (!pages)
 		return NULL;
 
-	err = __alloc_fill_pages(&pages, count, gfp);
-	if (err)
-		goto error
+	if (gfp & GFP_ATOMIC) {
+		struct page *page;
+		int i;
+		void *addr = __alloc_from_pool(size, &page);
+		if (!addr)
+			goto error;
+
+		for (i = 0; i < count; i++)
+			pages[i] = page + i;
+	} else {
+		int err = __alloc_fill_pages(&pages, count, gfp);
+		if (err)
+			goto error;
+	}
 
 	return pages;
 
@@ -1091,9 +1101,15 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
 	int count = size >> PAGE_SHIFT;
 	int array_size = count * sizeof(struct page *);
 	int i;
+
+	if (__free_from_pool(page_address(pages[0]), size))
+		goto out;
+
 	for (i = 0; i < count; i++)
 		if (pages[i])
 			__free_pages(pages[i], 0);
+
+out:
 	if ((array_size <= PAGE_SIZE) ||
 	    __in_atomic_pool(page_address(pages[0]), size))
 		kfree(pages);
@@ -1221,6 +1237,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	if (*handle == DMA_ERROR_CODE)
 		goto err_buffer;
 
+	if (gfp & GFP_ATOMIC)
+		return page_address(pages[0]);
+
 	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
 		return pages;
 
@@ -1279,7 +1298,8 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
 		return;
 	}
 
-	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
+	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs) ||
+	    !__in_atomic_pool(cpu_addr, size)) {
 		unmap_kernel_range((unsigned long)cpu_addr, size);
 		vunmap(cpu_addr);
 	}
-- 
1.7.5.4



From jett.zhou at gmail.com  Thu Aug 23 05:06:22 2012
From: jett.zhou at gmail.com (jett zhou)
Date: Thu, 23 Aug 2012 17:06:22 +0800
Subject: [V4 3/4] power_supply: Enable battery-charger for 88pm860x
In-Reply-To: <20120823044348.GA415@lizard>
References: <20120714081254.GD20018@lizard>
 <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
 <20120823034815.GB16674@lizard> <20120823044348.GA415@lizard>
Message-ID: <CACDDiy-ZzUxi4MvjELwHzYC+AxF0b0+LuOh=JdFBBgSA2ijjNw@mail.gmail.com>

Hi Anton
    Thanks for helping me to amend these patch.
    I got many good suggestions and learn a lot in this process:)
    BTW, you mean you will help to amend that several minor warning with
battery tree?
    If there is something wrong, I can correct it.

Thanks



2012/8/23 Anton Vorontsov <anton.vorontsov at linaro.org>

> On Wed, Aug 22, 2012 at 08:48:15PM -0700, Anton Vorontsov wrote:
> [....]
> > drivers/mfd/88pm860x-core.c:803:53: warning: incorrect type in
> assignment (different base types)
> > drivers/mfd/88pm860x-core.c:803:53:    expected struct charger_regulator
> *charger_regulators
> > drivers/mfd/88pm860x-core.c:803:53:    got struct regulator_bulk_data
> static [toplevel] *
> >
> > They are minor, except for the last one. You seemed to use
> > 'regulator_bulk_data' struct (just as charger manager documentation
> > wrongly tells you, yup), but in real it should have been
> > 'struct charger_regulator'. The only reason that it worked is
> > because both 'supply' and 'regulator_name' struct members are the
> > first in these structs. :-)
>
> Oh, actually, I see that this is a result of extcon rework, so not
> your fault at all.
>
> Anton.
>



-- 

----------------------------------
Best Regards
Jett Zhou
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From stigge at antcom.de  Thu Aug 23 08:22:28 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 23 Aug 2012 14:22:28 +0200
Subject: [PATCH] ARM: mach-pnx4008: Remove architecture
Message-ID: <1345724548-18130-1-git-send-email-stigge@antcom.de>

This patch removes the ARM architecture mach-pnx4008. No direct support or user
feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
maintainers.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 arch/arm/Kconfig                                  |    8 
 arch/arm/Makefile                                 |    1 
 arch/arm/configs/pnx4008_defconfig                |  472 ---------
 arch/arm/mach-pnx4008/Makefile                    |   12 
 arch/arm/mach-pnx4008/Makefile.boot               |    4 
 arch/arm/mach-pnx4008/clock.c                     | 1001 -------------------
 arch/arm/mach-pnx4008/clock.h                     |   43 
 arch/arm/mach-pnx4008/core.c                      |  290 -----
 arch/arm/mach-pnx4008/dma.c                       | 1105 ----------------------
 arch/arm/mach-pnx4008/gpio.c                      |  328 ------
 arch/arm/mach-pnx4008/i2c.c                       |   86 -
 arch/arm/mach-pnx4008/i2c.c.orig                  |   87 -
 arch/arm/mach-pnx4008/include/mach/clock.h        |   62 -
 arch/arm/mach-pnx4008/include/mach/debug-macro.S  |   21 
 arch/arm/mach-pnx4008/include/mach/dma.h          |  160 ---
 arch/arm/mach-pnx4008/include/mach/entry-macro.S  |  116 --
 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h |  241 ----
 arch/arm/mach-pnx4008/include/mach/hardware.h     |   32 
 arch/arm/mach-pnx4008/include/mach/irq.h          |   42 
 arch/arm/mach-pnx4008/include/mach/irqs.h         |  215 ----
 arch/arm/mach-pnx4008/include/mach/param.h        |   21 
 arch/arm/mach-pnx4008/include/mach/platform.h     |   69 -
 arch/arm/mach-pnx4008/include/mach/pm.h           |   33 
 arch/arm/mach-pnx4008/include/mach/timex.h        |   19 
 arch/arm/mach-pnx4008/include/mach/uncompress.h   |   46 
 arch/arm/mach-pnx4008/irq.c                       |  121 --
 arch/arm/mach-pnx4008/pm.c                        |  153 ---
 arch/arm/mach-pnx4008/serial.c                    |   67 -
 arch/arm/mach-pnx4008/sleep.S                     |  195 ---
 arch/arm/mach-pnx4008/time.c                      |  134 --
 arch/arm/mach-pnx4008/time.h                      |   70 -
 arch/arm/tools/mach-types                         |    1 
 drivers/i2c/busses/Kconfig                        |    2 
 drivers/usb/Kconfig                               |    1 
 drivers/usb/host/Kconfig                          |    2 
 drivers/usb/host/ohci-hcd.c                       |    2 
 drivers/usb/host/ohci-nxp.c                       |   84 -
 drivers/video/Kconfig                             |   15 
 drivers/video/Makefile                            |    2 
 drivers/video/pnx4008/Makefile                    |    7 
 drivers/video/pnx4008/dum.h                       |  211 ----
 drivers/video/pnx4008/fbcommon.h                  |   43 
 drivers/video/pnx4008/pnxrgbfb.c                  |  198 ---
 drivers/video/pnx4008/sdum.c                      |  861 -----------------
 drivers/video/pnx4008/sdum.h                      |  136 --
 drivers/watchdog/Kconfig                          |    6 
 46 files changed, 7 insertions(+), 6818 deletions(-)

--- linux-2.6.orig/arch/arm/Kconfig
+++ linux-2.6/arch/arm/Kconfig
@@ -709,14 +709,6 @@ config ARCH_PICOXCELL
 	  family of Femtocell devices.  The picoxcell support requires device tree
 	  for all boards.
 
-config ARCH_PNX4008
-	bool "Philips Nexperia PNX4008 Mobile"
-	select CPU_ARM926T
-	select CLKDEV_LOOKUP
-	select ARCH_USES_GETTIMEOFFSET
-	help
-	  This enables support for Philips PNX4008 mobile platform.
-
 config ARCH_PXA
 	bool "PXA2xx/PXA3xx-based"
 	depends on MMU
--- linux-2.6.orig/arch/arm/Makefile
+++ linux-2.6/arch/arm/Makefile
@@ -167,7 +167,6 @@ machine-$(CONFIG_ARCH_OMAP1)		:= omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
 machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
-machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
--- linux-2.6.orig/arch/arm/configs/pnx4008_defconfig
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
--- linux-2.6.orig/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y			:= core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m			:=
-obj-n			:=
-obj-			:=
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y		+= 0x80008000
-params_phys-y		:= 0x80000100
-initrd_phys-y		:= 0x80800000
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- * Generic clock management functions are partially based on:
- *  linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-
-static inline void clock_lock(void)
-{
-	local_irq_disable();
-}
-
-static inline void clock_unlock(void)
-{
-	local_irq_enable();
-}
-
-static void propagate_rate(struct clk *clk)
-{
-	struct clk *tmp_clk;
-
-	tmp_clk = clk;
-	while (tmp_clk->propagate_next) {
-		tmp_clk = tmp_clk->propagate_next;
-		local_set_rate(tmp_clk, tmp_clk->user_rate);
-	}
-}
-
-static void clk_reg_disable(struct clk *clk)
-{
-	if (clk->enable_reg)
-		__raw_writel(__raw_readl(clk->enable_reg) &
-			     ~(1 << clk->enable_shift), clk->enable_reg);
-}
-
-static int clk_reg_enable(struct clk *clk)
-{
-	if (clk->enable_reg)
-		__raw_writel(__raw_readl(clk->enable_reg) |
-			     (1 << clk->enable_shift), clk->enable_reg);
-	return 0;
-}
-
-static inline void clk_reg_disable1(struct clk *clk)
-{
-	if (clk->enable_reg1)
-		__raw_writel(__raw_readl(clk->enable_reg1) &
-			     ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static inline void clk_reg_enable1(struct clk *clk)
-{
-	if (clk->enable_reg1)
-		__raw_writel(__raw_readl(clk->enable_reg1) |
-			     (1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
-	int i;
-	i = 0;
-	while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;	/*wait for PLL to lock */
-
-	if (!(__raw_readl(clk->scale_reg) & 1)) {
-		printk(KERN_ERR
-		       "%s ERROR: failed to lock, scale reg data: %x\n",
-		       clk->name, __raw_readl(clk->scale_reg));
-		return -1;
-	}
-	return 0;
-}
-
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
-	int i;
-	int ret;
-	u32 tmp_reg;
-
-	ret = 0;
-
-	if (!clk->rate)
-		clk_reg_enable1(clk);
-
-	tmp_reg = __raw_readl(clk->parent_switch_reg);
-	/*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
-	if (!(tmp_reg & 1)) {
-		tmp_reg |= (1 << 1);	/* Trigger switch to 13'MHz (dirty) clock */
-		__raw_writel(tmp_reg, clk->parent_switch_reg);
-		i = 0;
-		while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;	/*wait for 13'MHz selection status */
-
-		if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
-			printk(KERN_ERR
-			       "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
-			       clk->name, __raw_readl(clk->parent_switch_reg));
-			ret = -1;
-		}
-	}
-
-	if (!clk->rate)
-		clk_reg_disable1(clk);
-
-	return ret;
-}
-
-static int switch_to_clean_13mhz(struct clk *clk)
-{
-	int i;
-	int ret;
-	u32 tmp_reg;
-
-	ret = 0;
-
-	if (!clk->rate)
-		clk_reg_enable1(clk);
-
-	tmp_reg = __raw_readl(clk->parent_switch_reg);
-	/*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
-	if (tmp_reg & 1) {
-		tmp_reg &= ~(1 << 1);	/* Trigger switch to 13MHz (clean) clock */
-		__raw_writel(tmp_reg, clk->parent_switch_reg);
-		i = 0;
-		while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;	/*wait for 13MHz selection status */
-
-		if (__raw_readl(clk->parent_switch_reg) & 1) {
-			printk(KERN_ERR
-			       "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
-			       clk->name, __raw_readl(clk->parent_switch_reg));
-			ret = -1;
-		}
-	}
-
-	if (!clk->rate)
-		clk_reg_disable1(clk);
-
-	return ret;
-}
-
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
-	int ret = -EINVAL;
-
-	if (parent == &ck_13MHz)
-		ret = switch_to_clean_13mhz(clk);
-	else if (parent == &ck_pll1)
-		ret = switch_to_dirty_13mhz(clk);
-
-	return ret;
-}
-
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp_reg, tmp_m, tmp_2p, i;
-	u32 parent_rate;
-	int ret = -EINVAL;
-
-	parent_rate = clk->parent->rate;
-
-	if (!parent_rate)
-		goto out;
-
-	/* set direct run for ARM or disable output for others  */
-	clk_reg_disable(clk);
-
-	/* disable source input as well (ignored for ARM) */
-	clk_reg_disable1(clk);
-
-	tmp_reg = __raw_readl(clk->scale_reg);
-	tmp_reg &= ~0x1ffff;	/*clear all settings, power down */
-	__raw_writel(tmp_reg, clk->scale_reg);
-
-	rate -= rate % parent_rate;	/*round down the input */
-
-	if (rate > PLL160_MAX_FCCO)
-		rate = PLL160_MAX_FCCO;
-
-	if (!rate) {
-		clk->rate = 0;
-		ret = 0;
-		goto out;
-	}
-
-	clk_reg_enable1(clk);
-	tmp_reg = __raw_readl(clk->scale_reg);
-
-	if (rate == parent_rate) {
-		/*enter direct bypass mode */
-		tmp_reg |= ((1 << 14) | (1 << 15));
-		__raw_writel(tmp_reg, clk->scale_reg);
-		clk->rate = parent_rate;
-		clk_reg_enable(clk);
-		ret = 0;
-		goto out;
-	}
-
-	i = 0;
-	for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
-		if (rate * tmp_2p >= PLL160_MIN_FCCO)
-			break;
-		i++;
-	}
-
-	if (tmp_2p > 1)
-		tmp_reg |= ((i - 1) << 11);
-	else
-		tmp_reg |= (1 << 14);	/*direct mode, no divide */
-
-	tmp_m = rate * tmp_2p;
-	tmp_m /= parent_rate;
-
-	tmp_reg |= (tmp_m - 1) << 1;	/*calculate M */
-	tmp_reg |= (1 << 16);	/*power up PLL */
-	__raw_writel(tmp_reg, clk->scale_reg);
-
-	if (clk_wait_for_pll_lock(clk) < 0) {
-		clk_reg_disable(clk);
-		clk_reg_disable1(clk);
-
-		tmp_reg = __raw_readl(clk->scale_reg);
-		tmp_reg &= ~0x1ffff;	/*clear all settings, power down */
-		__raw_writel(tmp_reg, clk->scale_reg);
-		clk->rate = 0;
-		ret = -EFAULT;
-		goto out;
-	}
-
-	clk->rate = (tmp_m * parent_rate) / tmp_2p;
-
-	if (clk->flags & RATE_PROPAGATES)
-		propagate_rate(clk);
-
-	clk_reg_enable(clk);
-	ret = 0;
-
-out:
-	return ret;
-}
-
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp;
-
-	tmp = __raw_readl(clk->scale_reg);
-	tmp &= ~(0x1f << 2);
-	tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
-	__raw_writel(tmp, clk->scale_reg);
-	clk->rate = rate;
-	return 0;
-}
-
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp;
-	tmp = __raw_readl(clk->scale_reg);
-	tmp = tmp & ~0x3;
-	switch (rate) {
-	case 1:
-		break;
-	case 2:
-		tmp |= 1;
-		break;
-	case 4:
-		tmp |= 2;
-		break;
-	}
-
-	__raw_writel(tmp, clk->scale_reg);
-	clk->rate = rate;
-	return 0;
-}
-
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
-	switch (rate) {
-	case 1:
-	case 4:
-		return rate;
-	}
-	return 2;
-}
-
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
-	return CLK_RATE_13MHZ;
-}
-
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_enable(clk);
-		clk->rate = 1;
-	} else {
-		clk_reg_disable(clk);
-		clk->rate = 0;
-	}
-	return 0;
-}
-
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		clk->rate = 1;
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-	}
-	return 0;
-}
-
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? 1 : 0);
-}
-
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
-	if (rate > CLK_RATE_208MHZ)
-		rate = CLK_RATE_208MHZ;
-	if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
-		rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
-	return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
-	if (rate > CLK_RATE_208MHZ)
-		rate = CLK_RATE_208MHZ;
-	return (rate - rate % CLK_RATE_13MHZ);
-}
-
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? CLK_RATE_48MHZ : 0);
-}
-
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? CLK_RATE_13MHZ : 0);
-}
-
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		udelay(500);
-		clk->rate = CLK_RATE_13MHZ;
-		ck_1MHz.rate = CLK_RATE_1MHZ;
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-		ck_1MHz.rate = 0;
-	}
-	return 0;
-}
-
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		if (!clk_wait_for_pll_lock(clk)) {
-			clk->rate = CLK_RATE_13MHZ;
-		} else {
-			clk_reg_enable(clk);
-			clk->rate = 0;
-		}
-
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-	}
-#endif
-	return 0;
-}
-
-/* Clock sources */
-
-static struct clk osc_13MHz = {
-	.name = "osc_13MHz",
-	.flags = FIXED_RATE,
-	.rate = CLK_RATE_13MHZ,
-};
-
-static struct clk ck_13MHz = {
-	.name = "ck_13MHz",
-	.parent = &osc_13MHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &ck_13MHz_round_rate,
-	.set_rate = &ck_13MHz_set_rate,
-	.enable_reg = OSC13CTRL_REG,
-	.enable_shift = 0,
-	.rate = CLK_RATE_13MHZ,
-};
-
-static struct clk osc_32KHz = {
-	.name = "osc_32KHz",
-	.flags = FIXED_RATE,
-	.rate = CLK_RATE_32KHZ,
-};
-
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
-	.name = "ck_1MHz",
-	.flags = FIXED_RATE | PARENT_SET_RATE,
-	.parent = &ck_13MHz,
-};
-
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
-	.name = "ck_pll1",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &ck_13MHz_round_rate,
-	.set_rate = &pll1_set_rate,
-	.enable_reg = PLLCTRL_REG,
-	.enable_shift = 1,
-	.scale_reg = PLLCTRL_REG,
-	.rate = CLK_RATE_13MHZ,
-};
-
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
-	.name = "ck_pll4",
-	.parent = &ck_pll1,
-	.flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
-	.propagate_next = &per_ck,
-	.round_rate = &pll4_round_rate,
-	.set_rate = &pll160_set_rate,
-	.rate = CLK_RATE_208MHZ,
-	.scale_reg = HCLKPLLCTRL_REG,
-	.enable_reg = PWRCTRL_REG,
-	.enable_shift = 2,
-	.parent_switch_reg = SYSCLKCTRL_REG,
-	.set_parent = &set_13MHz_parent,
-};
-
-/* USB PLL */
-static struct clk ck_pll5 = {
-	.name = "ck_pll5",
-	.parent = &ck_1MHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &pll5_round_rate,
-	.set_rate = &pll160_set_rate,
-	.scale_reg = USBCTRL_REG,
-	.enable_reg = USBCTRL_REG,
-	.enable_shift = 18,
-	.enable_reg1 = USBCTRL_REG,
-	.enable_shift1 = 17,
-};
-
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
-	.name = "ck_pll3",
-	.parent = &ck_pll1,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &pll3_round_rate,
-	.set_rate = &pll160_set_rate,
-	.scale_reg = DSPPLLCTRL_REG,
-	.enable_reg = DSPCLKCTRL_REG,
-	.enable_shift = 3,
-	.enable_reg1 = DSPCLKCTRL_REG,
-	.enable_shift1 = 2,
-	.parent_switch_reg = DSPCLKCTRL_REG,
-	.set_parent = &set_13MHz_parent,
-};
-
-static struct clk hclk_ck = {
-	.name = "hclk_ck",
-	.parent = &ck_pll4,
-	.flags = PARENT_SET_RATE,
-	.set_rate = &hclk_set_rate,
-	.round_rate = &hclk_round_rate,
-	.scale_reg = HCLKDIVCTRL_REG,
-	.rate = 2,
-	.user_rate = 2,
-};
-
-static struct clk per_ck = {
-	.name = "per_ck",
-	.parent = &ck_pll4,
-	.flags = FIXED_RATE,
-	.propagate_next = &hclk_ck,
-	.set_rate = &per_clk_set_rate,
-	.round_rate = &per_clk_round_rate,
-	.scale_reg = HCLKDIVCTRL_REG,
-	.rate = CLK_RATE_13MHZ,
-	.user_rate = CLK_RATE_13MHZ,
-};
-
-static struct clk m2hclk_ck = {
-	.name = "m2hclk_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_inv_set_rate,
-	.rate = 1,
-	.enable_shift = 6,
-	.enable_reg = PWRCTRL_REG,
-};
-
-static struct clk vfp9_ck = {
-	.name = "vfp9_ck",
-	.parent = &ck_pll4,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 4,
-	.enable_reg = VFP9CLKCTRL_REG,
-};
-
-static struct clk keyscan_ck = {
-	.name = "keyscan_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = KEYCLKCTRL_REG,
-};
-
-static struct clk touch_ck = {
-	.name = "touch_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = TSCLKCTRL_REG,
-};
-
-static struct clk pwm1_ck = {
-	.name = "pwm1_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk pwm2_ck = {
-	.name = "pwm2_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 2,
-	.enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk jpeg_ck = {
-	.name = "jpeg_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = JPEGCLKCTRL_REG,
-};
-
-static struct clk ms_ck = {
-	.name = "ms_ck",
-	.parent = &ck_pll4,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 5,
-	.enable_reg = MSCTRL_REG,
-};
-
-static struct clk dum_ck = {
-	.name = "dum_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = DUMCLKCTRL_REG,
-};
-
-static struct clk flash_ck = {
-	.name = "flash_ck",
-	.parent = &hclk_ck,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 1,	/* Only MLC clock supported */
-	.enable_reg = FLASHCLKCTRL_REG,
-};
-
-static struct clk i2c0_ck = {
-	.name = "i2c0_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 0,
-	.enable_reg = I2CCLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk i2c1_ck = {
-	.name = "i2c1_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 1,
-	.enable_reg = I2CCLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk i2c2_ck = {
-	.name = "i2c2_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 2,
-	.enable_reg = USB_OTG_CLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk spi0_ck = {
-	.name = "spi0_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = SPICTRL_REG,
-};
-
-static struct clk spi1_ck = {
-	.name = "spi1_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 4,
-	.enable_reg = SPICTRL_REG,
-};
-
-static struct clk dma_ck = {
-	.name = "dma_ck",
-	.parent = &hclk_ck,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = DMACLKCTRL_REG,
-};
-
-static struct clk uart3_ck = {
-	.name = "uart3_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 0,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart4_ck = {
-	.name = "uart4_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 1,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart5_ck = {
-	.name = "uart5_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 2,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart6_ck = {
-	.name = "uart6_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 3,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk wdt_ck = {
-	.name = "wdt_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.enable_shift = 0,
-	.enable_reg = TIMCLKCTRL_REG,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
-	&ck_13MHz,
-	&ck_pll1,
-	&ck_pll4,
-	&ck_pll5,
-	&ck_pll3,
-	&vfp9_ck,
-	&m2hclk_ck,
-	&hclk_ck,
-	&dma_ck,
-	&flash_ck,
-	&dum_ck,
-	&keyscan_ck,
-	&pwm1_ck,
-	&pwm2_ck,
-	&jpeg_ck,
-	&ms_ck,
-	&touch_ck,
-	&i2c0_ck,
-	&i2c1_ck,
-	&i2c2_ck,
-	&spi0_ck,
-	&spi1_ck,
-	&uart3_ck,
-	&uart4_ck,
-	&uart5_ck,
-	&uart6_ck,
-	&wdt_ck,
-};
-
-static struct clk_lookup onchip_clkreg[] = {
-	{ .clk = &ck_13MHz,	.con_id = "ck_13MHz"	},
-	{ .clk = &ck_pll1,	.con_id = "ck_pll1"	},
-	{ .clk = &ck_pll4,	.con_id = "ck_pll4"	},
-	{ .clk = &ck_pll5,	.con_id = "ck_pll5"	},
-	{ .clk = &ck_pll3,	.con_id = "ck_pll3"	},
-	{ .clk = &vfp9_ck,	.con_id = "vfp9_ck"	},
-	{ .clk = &m2hclk_ck,	.con_id = "m2hclk_ck"	},
-	{ .clk = &hclk_ck,	.con_id = "hclk_ck"	},
-	{ .clk = &dma_ck,	.con_id = "dma_ck"	},
-	{ .clk = &flash_ck,	.con_id = "flash_ck"	},
-	{ .clk = &dum_ck,	.con_id = "dum_ck"	},
-	{ .clk = &keyscan_ck,	.con_id = "keyscan_ck"	},
-	{ .clk = &pwm1_ck,	.con_id = "pwm1_ck"	},
-	{ .clk = &pwm2_ck,	.con_id = "pwm2_ck"	},
-	{ .clk = &jpeg_ck,	.con_id = "jpeg_ck"	},
-	{ .clk = &ms_ck,	.con_id = "ms_ck"	},
-	{ .clk = &touch_ck,	.con_id = "touch_ck"	},
-	{ .clk = &i2c0_ck,	.dev_id = "pnx-i2c.0"	},
-	{ .clk = &i2c1_ck,	.dev_id = "pnx-i2c.1"	},
-	{ .clk = &i2c2_ck,	.dev_id = "pnx-i2c.2"	},
-	{ .clk = &spi0_ck,	.con_id = "spi0_ck"	},
-	{ .clk = &spi1_ck,	.con_id = "spi1_ck"	},
-	{ .clk = &uart3_ck,	.con_id = "uart3_ck"	},
-	{ .clk = &uart4_ck,	.con_id = "uart4_ck"	},
-	{ .clk = &uart5_ck,	.con_id = "uart5_ck"	},
-	{ .clk = &uart6_ck,	.con_id = "uart6_ck"	},
-	{ .clk = &wdt_ck,	.dev_id = "pnx4008-watchdog" },
-};
-
-static void local_clk_disable(struct clk *clk)
-{
-	if (WARN_ON(clk->usecount == 0))
-		return;
-
-	if (!(--clk->usecount)) {
-		if (clk->disable)
-			clk->disable(clk);
-		else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-			clk->set_rate(clk, 0);
-		if (clk->parent)
-			local_clk_disable(clk->parent);
-	}
-}
-
-static int local_clk_enable(struct clk *clk)
-{
-	int ret = 0;
-
-	if (clk->usecount == 0) {
-		if (clk->parent) {
-			ret = local_clk_enable(clk->parent);
-			if (ret != 0)
-				goto out;
-		}
-
-		if (clk->enable)
-			ret = clk->enable(clk);
-		else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-			    && clk->user_rate)
-			ret = clk->set_rate(clk, clk->user_rate);
-
-		if (ret != 0 && clk->parent) {
-			local_clk_disable(clk->parent);
-			goto out;
-		}
-
-		clk->usecount++;
-	}
-out:
-	return ret;
-}
-
-static int local_set_rate(struct clk *clk, u32 rate)
-{
-	int ret = -EINVAL;
-	if (clk->set_rate) {
-
-		if (clk->user_rate == clk->rate && clk->parent->rate) {
-			/* if clock enabled or rate not set */
-			clk->user_rate = clk->round_rate(clk, rate);
-			ret = clk->set_rate(clk, clk->user_rate);
-		} else
-			clk->user_rate = clk->round_rate(clk, rate);
-		ret = 0;
-	}
-	return ret;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret = -EINVAL;
-
-	if (clk->flags & FIXED_RATE)
-		goto out;
-
-	clock_lock();
-	if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-
-		clk->user_rate = clk->round_rate(clk, rate);
-		/* parent clock needs to be refreshed
-		   for the setting to take effect */
-	} else {
-		ret = local_set_rate(clk, rate);
-	}
-	ret = 0;
-	clock_unlock();
-
-out:
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long ret;
-	clock_lock();
-	ret = clk->rate;
-	clock_unlock();
-	return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_enable(struct clk *clk)
-{
-	int ret;
-
-	clock_lock();
-	ret = local_clk_enable(clk);
-	clock_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-	clock_lock();
-	local_clk_disable(clk);
-	clock_unlock();
-}
-
-EXPORT_SYMBOL(clk_disable);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	long ret;
-	clock_lock();
-	if (clk->round_rate)
-		ret = clk->round_rate(clk, rate);
-	else
-		ret = clk->rate;
-	clock_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	int ret = -ENODEV;
-	if (!clk->set_parent)
-		goto out;
-
-	clock_lock();
-	ret = clk->set_parent(clk, parent);
-	if (!ret)
-		clk->parent = parent;
-	clock_unlock();
-
-out:
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_set_parent);
-
-static int __init clk_init(void)
-{
-	struct clk **clkp;
-
-	/* Disable autoclocking, as it doesn't seem to work */
-	__raw_writel(0xff, AUTOCLK_CTRL);
-
-	for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-	     clkp++) {
-		struct clk *clk = *clkp;
-		if (clk->flags & NEEDS_INITIALIZATION) {
-			if (clk->set_rate) {
-				clk->user_rate = clk->rate;
-				local_set_rate(clk, clk->user_rate);
-				if (clk->set_parent)
-					clk->set_parent(clk, clk->parent);
-			}
-			if (clk->enable && clk->usecount)
-				clk->enable(clk);
-			if (clk->disable && !clk->usecount)
-				clk->disable(clk);
-		}
-		pr_debug("%s: clock %s, rate %ld\n",
-			__func__, clk->name, clk->rate);
-	}
-
-	local_clk_enable(&ck_pll4);
-
-	/* if ck_13MHz is not used, disable it. */
-	if (ck_13MHz.usecount == 0)
-		local_clk_disable(&ck_13MHz);
-
-	/* Disable autoclocking */
-	__raw_writeb(0xff, AUTOCLK_CTRL);
-
-	clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-
-	return 0;
-}
-
-arch_initcall(clk_init);
--- linux-2.6.orig/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source at mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-
-struct clk {
-	const char *name;
-	struct clk *parent;
-	struct clk *propagate_next;
-	u32 rate;
-	u32 user_rate;
-	s8 usecount;
-	u32 flags;
-	u32 scale_reg;
-	u8 enable_shift;
-	u32 enable_reg;
-	u8 enable_shift1;
-	u32 enable_reg1;
-	u32 parent_switch_reg;
-	u32(*round_rate) (struct clk *, u32);
-	int (*set_rate) (struct clk *, u32);
-	int (*set_parent) (struct clk * clk, struct clk * parent);
-	int (*enable)(struct clk *);
-	void (*disable)(struct clk *);
-};
-
-/* Flags */
-#define RATE_PROPAGATES      (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE      (1<<2)
-#define FIXED_RATE           (1<<3)
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-
-struct resource spipnx_0_resources[] = {
-	{
-		.start = PNX4008_SPI1_BASE,
-		.end = PNX4008_SPI1_BASE + SZ_4K,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = PER_SPI1_REC_XMIT,
-		.flags = IORESOURCE_DMA,
-	}, {
-		.start = SPI1_INT,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.flags = 0,
-	},
-};
-
-struct resource spipnx_1_resources[] = {
-	{
-		.start = PNX4008_SPI2_BASE,
-		.end = PNX4008_SPI2_BASE + SZ_4K,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = PER_SPI2_REC_XMIT,
-		.flags = IORESOURCE_DMA,
-	}, {
-		.start = SPI2_INT,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.flags = 0,
-	}
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-	{
-		.modalias	= "m25p80",
-		.max_speed_hz	= 1000000,
-		.bus_num	= 1,
-		.chip_select	= 0,
-	},
-};
-
-static struct platform_device spipnx_1 = {
-	.name = "spipnx",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(spipnx_0_resources),
-	.resource = spipnx_0_resources,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-		},
-};
-
-static struct platform_device spipnx_2 = {
-	.name = "spipnx",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(spipnx_1_resources),
-	.resource = spipnx_1_resources,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-		},
-};
-
-static struct plat_serial8250_port platform_serial_ports[] = {
-	{
-		.membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
-		.mapbase = (unsigned long)PNX4008_UART5_BASE,
-		.irq = IIR5_INT,
-		.uartclk = PNX4008_UART_CLK,
-		.regshift = 2,
-		.iotype = UPIO_MEM,
-		.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-	},
-	{
-		.membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
-		.mapbase = (unsigned long)PNX4008_UART3_BASE,
-		.irq = IIR3_INT,
-		.uartclk = PNX4008_UART_CLK,
-		.regshift = 2,
-		.iotype = UPIO_MEM,
-		.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-	 },
-	{}
-};
-
-static struct platform_device serial_device = {
-	.name = "serial8250",
-	.id = PLAT8250_DEV_PLATFORM,
-	.dev = {
-		.platform_data = &platform_serial_ports,
-	},
-};
-
-static struct platform_device nand_flash_device = {
-	.name = "pnx4008-flash",
-	.id = -1,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-	},
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-
-static struct resource ohci_resources[] = {
-	{
-		.start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
-		.end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = USB_HOST_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device ohci_device = {
-	.name = "pnx4008-usb-ohci",
-	.id = -1,
-	.dev = {
-		.dma_mask = &ohci_dmamask,
-		.coherent_dma_mask = 0xffffffff,
-		},
-	.num_resources = ARRAY_SIZE(ohci_resources),
-	.resource = ohci_resources,
-};
-
-static struct platform_device sdum_device = {
-	.name = "pnx4008-sdum",
-	.id = 0,
-	.dev = {
-		.coherent_dma_mask = 0xffffffff,
-	},
-};
-
-static struct platform_device rgbfb_device = {
-	.name = "pnx4008-rgbfb",
-	.id = 0,
-	.dev = {
-		.coherent_dma_mask = 0xffffffff,
-	}
-};
-
-struct resource watchdog_resources[] = {
-	{
-		.start = PNX4008_WDOG_BASE,
-		.end = PNX4008_WDOG_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device watchdog_device = {
-	.name = "pnx4008-watchdog",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(watchdog_resources),
-	.resource = watchdog_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&spipnx_1,
-	&spipnx_2,
-	&serial_device,
-	&ohci_device,
-	&nand_flash_device,
-	&sdum_device,
-	&rgbfb_device,
-	&watchdog_device,
-};
-
-
-extern void pnx4008_uart_init(void);
-
-static void __init pnx4008_init(void)
-{
-	/*disable all START interrupt sources,
-	   and clear all START interrupt flags */
-	__raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
-	__raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-	/* Switch on the UART clocks */
-	pnx4008_uart_init();
-}
-
-static struct map_desc pnx4008_io_desc[] __initdata = {
-	{
-		.virtual 	= IO_ADDRESS(PNX4008_IRAM_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_IRAM_BASE),
-		.length		= SZ_64K,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
-		.length		= SZ_1M - SZ_128K,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
-		.length		= SZ_128K * 3,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
-		.length		= SZ_1M,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_AHB2FAB_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_AHB2FAB_BASE),
-		.length		= SZ_1M,
-		.type 		= MT_DEVICE,
-	},
-};
-
-void __init pnx4008_map_io(void)
-{
-	iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-
-static void pnx4008_restart(char mode, const char *cmd)
-{
-	soft_restart(0);
-}
-
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-
-void __init pnx4008_init_late(void)
-{
-	pnx4008_pm_init();
-}
-
-extern struct sys_timer pnx4008_timer;
-
-MACHINE_START(PNX4008, "Philips PNX4008")
-	/* Maintainer: MontaVista Software Inc. */
-	.atag_offset		= 0x100,
-	.map_io 		= pnx4008_map_io,
-	.init_irq 		= pnx4008_init_irq,
-	.init_machine 		= pnx4008_init,
-	.init_late		= pnx4008_init_late,
-	.timer 			= &pnx4008_timer,
-	.restart		= pnx4008_restart,
-MACHINE_END
--- linux-2.6.orig/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/dma.c
- *
- *  PNX4008 DMA registration and IRQ dispatching
- *
- *  Author:	Vitaly Wool
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  Based on the code from Nicolas Pitre
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-
-static struct dma_channel {
-	char *name;
-	void (*irq_handler) (int, int, void *);
-	void *data;
-	struct pnx4008_dma_ll *ll;
-	u32 ll_dma;
-	void *target_addr;
-	int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-
-static struct ll_pool {
-	void *vaddr;
-	void *cur;
-	dma_addr_t dma_addr;
-	int count;
-} ll_pool;
-
-static DEFINE_SPINLOCK(ll_lock);
-
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
-	struct pnx4008_dma_ll *ll = NULL;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ll_lock, flags);
-	if (ll_pool.count > 4) { /* can give one more */
-		ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
-		*ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
-		*(void **)ll_pool.cur = **(void ***)ll_pool.cur;
-		memset(ll, 0, sizeof(*ll));
-		ll_pool.count--;
-	}
-	spin_unlock_irqrestore(&ll_lock, flags);
-
-	return ll;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
-	unsigned long flags;
-
-	if (ll) {
-		if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
-			printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
-			BUG();
-		}
-
-		if (ll->flags & DMA_BUFFER_ALLOCATED)
-			ll->free(ll->alloc_data);
-
-		spin_lock_irqsave(&ll_lock, flags);
-		*(long *)ll = *(long *)ll_pool.cur;
-		*(long *)ll_pool.cur = (long)ll;
-		ll_pool.count++;
-		spin_unlock_irqrestore(&ll_lock, flags);
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
-	struct pnx4008_dma_ll *ptr;
-	u32 dma;
-
-	while (ll) {
-		dma = ll->next_dma;
-		ptr = ll->next;
-		pnx4008_free_ll_entry(ll, ll_dma);
-
-		ll_dma = dma;
-		ll = ptr;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-
-static int dma_channels_requested = 0;
-
-static inline void dma_increment_usage(void)
-{
-	if (!dma_channels_requested++) {
-		struct clk *clk = clk_get(0, "dma_ck");
-		if (!IS_ERR(clk)) {
-			clk_set_rate(clk, 1);
-			clk_put(clk);
-		}
-		pnx4008_config_dma(-1, -1, 1);
-	}
-}
-static inline void dma_decrement_usage(void)
-{
-	if (!--dma_channels_requested) {
-		struct clk *clk = clk_get(0, "dma_ck");
-		if (!IS_ERR(clk)) {
-			clk_set_rate(clk, 0);
-			clk_put(clk);
-		}
-		pnx4008_config_dma(-1, -1, 0);
-
-	}
-}
-
-static DEFINE_SPINLOCK(dma_lock);
-
-static inline void pnx4008_dma_lock(void)
-{
-	spin_lock_irq(&dma_lock);
-}
-
-static inline void pnx4008_dma_unlock(void)
-{
-	spin_unlock_irq(&dma_lock);
-}
-
-#define VALID_CHANNEL(c)	(((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-
-int pnx4008_request_channel(char *name, int ch,
-			    void (*irq_handler) (int, int, void *), void *data)
-{
-	int i, found = 0;
-
-	/* basic sanity checks */
-	if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-
-	/* try grabbing a DMA channel with the requested priority */
-	for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-		if (!dma_channels[i].name && (ch == -1 || ch == i)) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		dma_increment_usage();
-		dma_channels[i].name = name;
-		dma_channels[i].irq_handler = irq_handler;
-		dma_channels[i].data = data;
-		dma_channels[i].ll = NULL;
-		dma_channels[i].ll_dma = 0;
-	} else {
-		printk(KERN_WARNING "No more available DMA channels for %s\n",
-		       name);
-		i = -ENODEV;
-	}
-
-	pnx4008_dma_unlock();
-	return i;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-
-void pnx4008_free_channel(int ch)
-{
-	if (!dma_channels[ch].name) {
-		printk(KERN_CRIT
-		       "%s: trying to free channel %d which is already freed\n",
-		       __func__, ch);
-		return;
-	}
-
-	pnx4008_dma_lock();
-	pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
-	dma_channels[ch].ll = NULL;
-	dma_decrement_usage();
-
-	dma_channels[ch].name = NULL;
-	pnx4008_dma_unlock();
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
-	unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-
-	switch (ahb_m1_be) {
-	case 0:
-		dma_cfg &= ~(1 << 1);
-		break;
-	case 1:
-		dma_cfg |= (1 << 1);
-		break;
-	default:
-		break;
-	}
-
-	switch (ahb_m2_be) {
-	case 0:
-		dma_cfg &= ~(1 << 2);
-		break;
-	case 1:
-		dma_cfg |= (1 << 2);
-		break;
-	default:
-		break;
-	}
-
-	switch (enable) {
-	case 0:
-		dma_cfg &= ~(1 << 0);
-		break;
-	case 1:
-		dma_cfg |= (1 << 0);
-		break;
-	default:
-		break;
-	}
-
-	pnx4008_dma_lock();
-	__raw_writel(dma_cfg, DMAC_CONFIG);
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
-			     unsigned long *ctrl)
-{
-	int i = 0, dbsize, sbsize, err = 0;
-
-	if (!ctrl || !ch_ctrl) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	*ctrl = 0;
-
-	switch (ch_ctrl->tc_mask) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 31);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-
-	switch (ch_ctrl->cacheable) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 30);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->bufferable) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 29);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->priv_mode) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 28);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->di) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 27);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->si) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 26);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->dest_ahb1) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 25);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->src_ahb1) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 24);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->dwidth) {
-	case WIDTH_BYTE:
-		*ctrl &= ~(7 << 21);
-		break;
-	case WIDTH_HWORD:
-		*ctrl &= ~(7 << 21);
-		*ctrl |= (1 << 21);
-		break;
-	case WIDTH_WORD:
-		*ctrl &= ~(7 << 21);
-		*ctrl |= (2 << 21);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->swidth) {
-	case WIDTH_BYTE:
-		*ctrl &= ~(7 << 18);
-		break;
-	case WIDTH_HWORD:
-		*ctrl &= ~(7 << 18);
-		*ctrl |= (1 << 18);
-		break;
-	case WIDTH_WORD:
-		*ctrl &= ~(7 << 18);
-		*ctrl |= (2 << 18);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	dbsize = ch_ctrl->dbsize;
-	while (!(dbsize & 1)) {
-		i++;
-		dbsize >>= 1;
-	}
-	if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
-		err = -EINVAL;
-		goto out;
-	} else if (i > 1)
-		i--;
-	*ctrl &= ~(7 << 15);
-	*ctrl |= (i << 15);
-
-	sbsize = ch_ctrl->sbsize;
-	while (!(sbsize & 1)) {
-		i++;
-		sbsize >>= 1;
-	}
-	if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
-		err = -EINVAL;
-		goto out;
-	} else if (i > 1)
-		i--;
-	*ctrl &= ~(7 << 12);
-	*ctrl |= (i << 12);
-
-	if (ch_ctrl->tr_size > 0x7ff) {
-		err = -E2BIG;
-		goto out;
-	}
-	*ctrl &= ~0x7ff;
-	*ctrl |= ch_ctrl->tr_size & 0x7ff;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-
-int pnx4008_dma_parse_control(unsigned long ctrl,
-			      struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
-	int err = 0;
-
-	if (!ch_ctrl) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	ch_ctrl->tr_size = ctrl & 0x7ff;
-	ctrl >>= 12;
-
-	ch_ctrl->sbsize = 1 << (ctrl & 7);
-	if (ch_ctrl->sbsize > 1)
-		ch_ctrl->sbsize <<= 1;
-	ctrl >>= 3;
-
-	ch_ctrl->dbsize = 1 << (ctrl & 7);
-	if (ch_ctrl->dbsize > 1)
-		ch_ctrl->dbsize <<= 1;
-	ctrl >>= 3;
-
-	switch (ctrl & 7) {
-	case 0:
-		ch_ctrl->swidth = WIDTH_BYTE;
-		break;
-	case 1:
-		ch_ctrl->swidth = WIDTH_HWORD;
-		break;
-	case 2:
-		ch_ctrl->swidth = WIDTH_WORD;
-		break;
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	ctrl >>= 3;
-
-	switch (ctrl & 7) {
-	case 0:
-		ch_ctrl->dwidth = WIDTH_BYTE;
-		break;
-	case 1:
-		ch_ctrl->dwidth = WIDTH_HWORD;
-		break;
-	case 2:
-		ch_ctrl->dwidth = WIDTH_WORD;
-		break;
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	ctrl >>= 3;
-
-	ch_ctrl->src_ahb1 = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->dest_ahb1 = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->si = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->di = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->priv_mode = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->bufferable = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->cacheable = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->tc_mask = ctrl & 1;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
-			    unsigned long *cfg)
-{
-	int err = 0;
-
-	if (!cfg || !ch_cfg) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	*cfg = 0;
-
-	switch (ch_cfg->halt) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 18);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->active) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 17);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->lock) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 16);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->itc) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 15);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->ie) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 14);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->flow_cntrl) {
-	case FC_MEM2MEM_DMA:
-		*cfg &= ~(7 << 11);
-		break;
-	case FC_MEM2PER_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (1 << 11);
-		break;
-	case FC_PER2MEM_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (2 << 11);
-		break;
-	case FC_PER2PER_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (3 << 11);
-		break;
-	case FC_PER2PER_DPER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (4 << 11);
-		break;
-	case FC_MEM2PER_PER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (5 << 11);
-		break;
-	case FC_PER2MEM_PER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (6 << 11);
-		break;
-	case FC_PER2PER_SPER:
-		*cfg |= (7 << 11);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	*cfg &= ~(0x1f << 6);
-	*cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-
-	*cfg &= ~(0x1f << 1);
-	*cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-
-int pnx4008_dma_parse_config(unsigned long cfg,
-			     struct pnx4008_dma_ch_config * ch_cfg)
-{
-	int err = 0;
-
-	if (!ch_cfg) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	cfg >>= 1;
-
-	ch_cfg->src_per = cfg & 0x1f;
-	cfg >>= 5;
-
-	ch_cfg->dest_per = cfg & 0x1f;
-	cfg >>= 5;
-
-	switch (cfg & 7) {
-	case 0:
-		ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
-		break;
-	case 1:
-		ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
-		break;
-	case 2:
-		ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
-		break;
-	case 3:
-		ch_cfg->flow_cntrl = FC_PER2PER_DMA;
-		break;
-	case 4:
-		ch_cfg->flow_cntrl = FC_PER2PER_DPER;
-		break;
-	case 5:
-		ch_cfg->flow_cntrl = FC_MEM2PER_PER;
-		break;
-	case 6:
-		ch_cfg->flow_cntrl = FC_PER2MEM_PER;
-		break;
-	case 7:
-		ch_cfg->flow_cntrl = FC_PER2PER_SPER;
-	}
-	cfg >>= 3;
-
-	ch_cfg->ie = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->itc = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->lock = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->active = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->halt = cfg & 1;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
-				  struct pnx4008_dma_ch_ctrl * ctrl)
-{
-	int new_len = ctrl->tr_size, num_entries = 0;
-	int old_len = new_len;
-	int src_width, dest_width, count = 1;
-
-	switch (ctrl->swidth) {
-	case WIDTH_BYTE:
-		src_width = 1;
-		break;
-	case WIDTH_HWORD:
-		src_width = 2;
-		break;
-	case WIDTH_WORD:
-		src_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	switch (ctrl->dwidth) {
-	case WIDTH_BYTE:
-		dest_width = 1;
-		break;
-	case WIDTH_HWORD:
-		dest_width = 2;
-		break;
-	case WIDTH_WORD:
-		dest_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	while (new_len > 0x7FF) {
-		num_entries++;
-		new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-	}
-	if (num_entries != 0) {
-		struct pnx4008_dma_ll *ll = NULL;
-		config->ch_ctrl &= ~0x7ff;
-		config->ch_ctrl |= new_len;
-		if (!config->is_ll) {
-			config->is_ll = 1;
-			while (num_entries) {
-				if (!ll) {
-					config->ll =
-					    pnx4008_alloc_ll_entry(&config->
-								   ll_dma);
-					ll = config->ll;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    config->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = config->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    config->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = config->dest_addr;
-				ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-		} else {
-			struct pnx4008_dma_ll *ll_old = config->ll;
-			unsigned long ll_dma_old = config->ll_dma;
-			while (num_entries) {
-				if (!ll) {
-					config->ll =
-					    pnx4008_alloc_ll_entry(&config->
-								   ll_dma);
-					ll = config->ll;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    config->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = config->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    config->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = config->dest_addr;
-				ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-			ll->next_dma = ll_dma_old;
-			ll->next = ll_old;
-		}
-		/* adjust last length/tc */
-		ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
-		ll->ch_ctrl |= old_len - new_len * (count - 1);
-		config->ch_ctrl &= 0x7fffffff;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
-				struct pnx4008_dma_ch_ctrl * ctrl)
-{
-	int new_len = ctrl->tr_size, num_entries = 0;
-	int old_len = new_len;
-	int src_width, dest_width, count = 1;
-
-	switch (ctrl->swidth) {
-	case WIDTH_BYTE:
-		src_width = 1;
-		break;
-	case WIDTH_HWORD:
-		src_width = 2;
-		break;
-	case WIDTH_WORD:
-		src_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	switch (ctrl->dwidth) {
-	case WIDTH_BYTE:
-		dest_width = 1;
-		break;
-	case WIDTH_HWORD:
-		dest_width = 2;
-		break;
-	case WIDTH_WORD:
-		dest_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	while (new_len > 0x7FF) {
-		num_entries++;
-		new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-	}
-	if (num_entries != 0) {
-		struct pnx4008_dma_ll *ll = NULL;
-		cur_ll->ch_ctrl &= ~0x7ff;
-		cur_ll->ch_ctrl |= new_len;
-		if (!cur_ll->next) {
-			while (num_entries) {
-				if (!ll) {
-					cur_ll->next =
-					    pnx4008_alloc_ll_entry(&cur_ll->
-								   next_dma);
-					ll = cur_ll->next;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    cur_ll->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = cur_ll->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    cur_ll->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = cur_ll->dest_addr;
-				ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-		} else {
-			struct pnx4008_dma_ll *ll_old = cur_ll->next;
-			unsigned long ll_dma_old = cur_ll->next_dma;
-			while (num_entries) {
-				if (!ll) {
-					cur_ll->next =
-					    pnx4008_alloc_ll_entry(&cur_ll->
-								   next_dma);
-					ll = cur_ll->next;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    cur_ll->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = cur_ll->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    cur_ll->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = cur_ll->dest_addr;
-				ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-
-			ll->next_dma = ll_dma_old;
-			ll->next = ll_old;
-		}
-		/* adjust last length/tc */
-		ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
-		ll->ch_ctrl |= old_len - new_len * (count - 1);
-		cur_ll->ch_ctrl &= 0x7fffffff;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	__raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
-	__raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-
-	if (config->is_ll)
-		__raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
-	else
-		__raw_writel(0, DMAC_Cx_LLI(ch));
-
-	__raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
-	__raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-
-	config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
-	config->is_ll = config->ll_dma ? 1 : 0;
-
-	config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
-	config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-
-int pnx4008_dma_ch_enable(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	ch_cfg |= 1;
-	__raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-
-int pnx4008_dma_ch_disable(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	ch_cfg &= ~1;
-	__raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-
-int pnx4008_dma_ch_enabled(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return ch_cfg & 1;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i;
-	unsigned long dint = __raw_readl(DMAC_INT_STAT);
-	unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
-	unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
-	unsigned long i_bit;
-
-	for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-		i_bit = 1 << i;
-		if (dint & i_bit) {
-			struct dma_channel *channel = &dma_channels[i];
-
-			if (channel->name && channel->irq_handler) {
-				int cause = 0;
-
-				if (eint & i_bit)
-					cause |= DMA_ERR_INT;
-				if (tcint & i_bit)
-					cause |= DMA_TC_INT;
-				channel->irq_handler(i, cause, channel->data);
-			} else {
-				/*
-				 * IRQ for an unregistered DMA channel
-				 */
-				printk(KERN_WARNING
-				       "spurious IRQ for DMA channel %d\n", i);
-			}
-			if (tcint & i_bit)
-				__raw_writel(i_bit, DMAC_INT_TC_CLEAR);
-			if (eint & i_bit)
-				__raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
-		}
-	}
-	return IRQ_HANDLED;
-}
-
-static int __init pnx4008_dma_init(void)
-{
-	int ret, i;
-
-	ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-	if (ret) {
-		printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-		goto out;
-	}
-
-	ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
-	ll_pool.cur = ll_pool.vaddr =
-	    dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
-			       &ll_pool.dma_addr, GFP_KERNEL);
-
-	if (!ll_pool.vaddr) {
-		ret = -ENOMEM;
-		free_irq(DMA_INT, NULL);
-		goto out;
-	}
-
-	for (i = 0; i < ll_pool.count - 1; i++) {
-		void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
-		*addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
-	}
-	*(long *)(ll_pool.vaddr +
-		  (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
-	    (long)ll_pool.vaddr;
-
-	__raw_writel(1, DMAC_CONFIG);
-
-out:
-	return ret;
-}
-arch_initcall(pnx4008_dma_init);
--- linux-2.6.orig/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-
-/* register definitions */
-#define PIO_VA_BASE	IO_ADDRESS(PNX4008_PIO_BASE)
-
-#define PIO_INP_STATE	(0x00U)
-#define PIO_OUTP_SET	(0x04U)
-#define PIO_OUTP_CLR	(0x08U)
-#define PIO_OUTP_STATE	(0x0CU)
-#define PIO_DRV_SET	(0x10U)
-#define PIO_DRV_CLR	(0x14U)
-#define PIO_DRV_STATE	(0x18U)
-#define PIO_SDINP_STATE	(0x1CU)
-#define PIO_SDOUTP_SET	(0x20U)
-#define PIO_SDOUTP_CLR	(0x24U)
-#define PIO_MUX_SET	(0x28U)
-#define PIO_MUX_CLR	(0x2CU)
-#define PIO_MUX_STATE	(0x30U)
-
-static inline void gpio_lock(void)
-{
-	local_irq_disable();
-}
-
-static inline void gpio_unlock(void)
-{
-	local_irq_enable();
-}
-
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
-	u32 bit, val;
-	int ret = -EFAULT;
-
-	if (gpio < 0)
-		goto out;
-
-	bit = GPIO_BIT(gpio);
-	if (bit) {
-		val = __raw_readl(PIO_VA_BASE + reg);
-		ret = (val & bit) ? 1 : 0;
-	}
-out:
-	return ret;
-}
-
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
-	u32 bit, val;
-	int ret = -EFAULT;
-
-	if (gpio < 0)
-		goto out;
-
-	bit = GPIO_BIT(gpio);
-	if (bit) {
-		val = __raw_readl(PIO_VA_BASE + reg);
-		val |= bit;
-		__raw_writel(val, PIO_VA_BASE + reg);
-		ret = 0;
-	}
-out:
-	return ret;
-}
-
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX	0
-#define OUTP_INDEX	1
-#define GPIO_INDEX	2
-#define MUX_INDEX	3
-
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, 10, 11, 12, 13, 14, 24, -1
-};
-
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, 0, 1, 4, 5, -1
-};
-
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
-	-1, -1, -1, 6, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, 2, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1
-};
-
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
-	unsigned long bit = GPIO_BIT(pin);
-	int ret = -EBUSY;	/* Already in use */
-
-	gpio_lock();
-
-	if (GPIO_ISBID(pin)) {
-		if (access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] |= bit;
-
-	} else if (GPIO_ISRAM(pin)) {
-		if (access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] |= bit;
-
-	} else if (GPIO_ISMUX(pin)) {
-		if (access_map[MUX_INDEX] & bit)
-			goto out;
-		access_map[MUX_INDEX] |= bit;
-
-	} else if (GPIO_ISOUT(pin)) {
-		if (access_map[OUTP_INDEX] & bit)
-			goto out;
-		access_map[OUTP_INDEX] |= bit;
-
-	} else if (GPIO_ISIN(pin)) {
-		if (access_map[INP_INDEX] & bit)
-			goto out;
-		access_map[INP_INDEX] |= bit;
-	} else
-		goto out;
-	ret = 0;
-
-out:
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
-	unsigned long bit = GPIO_BIT(pin);
-	int ret = -EFAULT;	/* Not registered */
-
-	gpio_lock();
-
-	if (GPIO_ISBID(pin)) {
-		if (~access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] &= ~bit;
-	} else if (GPIO_ISRAM(pin)) {
-		if (~access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] &= ~bit;
-	} else if (GPIO_ISMUX(pin)) {
-		if (~access_map[MUX_INDEX] & bit)
-			goto out;
-		access_map[MUX_INDEX] &= ~bit;
-	} else if (GPIO_ISOUT(pin)) {
-		if (~access_map[OUTP_INDEX] & bit)
-			goto out;
-		access_map[OUTP_INDEX] &= ~bit;
-	} else if (GPIO_ISIN(pin)) {
-		if (~access_map[INP_INDEX] & bit)
-			goto out;
-		access_map[INP_INDEX] &= ~bit;
-	} else
-		goto out;
-	ret = 0;
-
-out:
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
-	unsigned long ret = -EFAULT;
-	int gpio = GPIO_BIT_MASK(pin);
-	gpio_lock();
-	if (GPIO_ISOUT(pin)) {
-		ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-	} else if (GPIO_ISRAM(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
-			ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
-		}
-	} else if (GPIO_ISBID(pin)) {
-		ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-		if (ret > 0)
-			ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-		else if (ret == 0)
-			ret =
-			    gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
-	} else if (GPIO_ISIN(pin)) {
-		ret = gpio_read_bit(PIO_INP_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISOUT(pin)) {
-		printk( "writing '%x' to '%x'\n",
-				gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
-		ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
-	} else if (GPIO_ISRAM(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-			ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
-					   PIO_SDOUTP_CLR, gpio);
-	} else if (GPIO_ISBID(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-			ret = gpio_set_bit(output ? PIO_OUTP_SET :
-					   PIO_OUTP_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-		ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-		ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-
-/* Value = 1 : Set pin to muxed function  */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin)) {
-		ret =
-		    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-				 gpio_to_mux_map[gpio]);
-	} else if (GPIO_ISOUT(pin)) {
-		ret =
-		    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-				 outp_to_mux_map[gpio]);
-	} else if (GPIO_ISMUX(pin)) {
-		ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
-	} else if (GPIO_ISOUT(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
-	} else if (GPIO_ISMUX(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
--- linux-2.6.orig/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool at gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
-static struct resource i2c0_resources[] = {
-	{
-		.start = PNX4008_I2C1_BASE,
-		.end = PNX4008_I2C1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_1_INT,
-		.end = I2C_1_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c1_resources[] = {
-	{
-		.start = PNX4008_I2C2_BASE,
-		.end = PNX4008_I2C2_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_2_INT,
-		.end = I2C_2_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c2_resources[] = {
-	{
-		.start = PNX4008_USB_CONFIG_BASE + 0x300,
-		.end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = USB_I2C_INT,
-		.end = USB_I2C_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device i2c0_device = {
-	.name = "pnx-i2c.0",
-	.id = 0,
-	.resource = i2c0_resources,
-	.num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
-	.name = "pnx-i2c.1",
-	.id = 1,
-	.resource = i2c1_resources,
-	.num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
-	.name = "pnx-i2c.2",
-	.id = 2,
-	.resource = i2c2_resources,
-	.num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
-	&i2c0_device,
-	&i2c1_device,
-	&i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-}
--- linux-2.6.orig/arch/arm/mach-pnx4008/i2c.c.orig
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool at gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-#include <mach/i2c.h>
-
-static struct resource i2c0_resources[] = {
-	{
-		.start = PNX4008_I2C1_BASE,
-		.end = PNX4008_I2C1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_1_INT,
-		.end = I2C_1_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c1_resources[] = {
-	{
-		.start = PNX4008_I2C2_BASE,
-		.end = PNX4008_I2C2_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_2_INT,
-		.end = I2C_2_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c2_resources[] = {
-	{
-		.start = PNX4008_USB_CONFIG_BASE + 0x300,
-		.end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = USB_I2C_INT,
-		.end = USB_I2C_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device i2c0_device = {
-	.name = "pnx-i2c",
-	.id = 0,
-	.resource = i2c0_resources,
-	.num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
-	.name = "pnx-i2c",
-	.id = 1,
-	.resource = i2c1_resources,
-	.num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
-	.name = "pnx-i2c",
-	.id = 2,
-	.resource = i2c2_resources,
-	.num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
-	&i2c0_device,
-	&i2c1_device,
-	&i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-}
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE		IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG		(PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG		(PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG		(PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG		(PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG		(PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG		(PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG		(PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG	(PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG		(PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL		(PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG		(PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG		(PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG		(PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG		(PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG	(PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG		(PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG		(PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG		(PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL		(PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG		(PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE	IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG		IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-		.macro	addruart, rp, rv, tmp
-		mov	\rp, #0x00090000
-		add	\rv, \rp, #0xf4000000	@ virtual
-		add	\rp, \rp, #0x40000000	@ physical
-		.endm
-
-#define UART_SHIFT	2
-#include <asm/hardware/debug-8250.S>
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:	Vitaly Wool
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_CHANNELS	8
-
-#define DMAC_BASE		IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT		(DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT	(DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR	(DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT	(DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR	(DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ		(DMAC_BASE + 0x0024)
-#define DMAC_CONFIG		(DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)	(DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)	(DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)		(DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)	(DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)	(DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
-	WIDTH_BYTE = 0,
-	WIDTH_HWORD,
-	WIDTH_WORD
-};
-
-enum {
-	FC_MEM2MEM_DMA,
-	FC_MEM2PER_DMA,
-	FC_PER2MEM_DMA,
-	FC_PER2PER_DMA,
-	FC_PER2PER_DPER,
-	FC_MEM2PER_PER,
-	FC_PER2MEM_PER,
-	FC_PER2PER_SPER
-};
-
-enum {
-	DMA_INT_UNKNOWN = 0,
-	DMA_ERR_INT = 1,
-	DMA_TC_INT = 2,
-};
-
-enum {
-	DMA_BUFFER_ALLOCATED = 1,
-	DMA_HAS_LL = 2,
-};
-
-enum {
-	PER_CAM_DMA_1 = 0,
-	PER_NDF_FLASH = 1,
-	PER_MBX_SLAVE_FIFO = 2,
-	PER_SPI2_REC_XMIT = 3,
-	PER_MS_SD_RX_XMIT = 4,
-	PER_HS_UART_1_XMIT = 5,
-	PER_HS_UART_1_RX = 6,
-	PER_HS_UART_2_XMIT = 7,
-	PER_HS_UART_2_RX = 8,
-	PER_HS_UART_7_XMIT = 9,
-	PER_HS_UART_7_RX = 10,
-	PER_SPI1_REC_XMIT = 11,
-	PER_MLC_NDF_SREC = 12,
-	PER_CAM_DMA_2 = 13,
-	PER_PRNG_INFIFO = 14,
-	PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
-	int tc_mask;
-	int cacheable;
-	int bufferable;
-	int priv_mode;
-	int di;
-	int si;
-	int dest_ahb1;
-	int src_ahb1;
-	int dwidth;
-	int swidth;
-	int dbsize;
-	int sbsize;
-	int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
-	int halt;
-	int active;
-	int lock;
-	int itc;
-	int ie;
-	int flow_cntrl;
-	int dest_per;
-	int src_per;
-};
-
-struct pnx4008_dma_ll {
-	unsigned long src_addr;
-	unsigned long dest_addr;
-	u32 next_dma;
-	unsigned long ch_ctrl;
-	struct pnx4008_dma_ll *next;
-	int flags;
-	void *alloc_data;
-	int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
-	int is_ll;
-	unsigned long src_addr;
-	unsigned long dest_addr;
-	unsigned long ch_ctrl;
-	unsigned long ch_cfg;
-	struct pnx4008_dma_ll *ll;
-	u32 ll_dma;
-	int flags;
-	void *alloc_data;
-	int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
-				   void (*)(int, int, void *),
-				   void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-				    unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-				     struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-				   unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-				    struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-					 struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-				       struct pnx4008_dma_ch_ctrl *);
-
-#endif				/* _ASM_ARCH_DMA_H */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool at ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK			0x00
-#define INTRC_RAW_STAT			0x04
-#define INTRC_STAT			0x08
-#define INTRC_POLAR			0x0C
-#define INTRC_ACT_TYPE			0x10
-#define INTRC_TYPE			0x14
-
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-		ldr	\base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-		ldr	\irqstat, [\base, #INTRC_STAT]
-
-		cmp	\irqstat,#1<<16
-		movhs	\irqnr,#16
-		movlo	\irqnr,#0
-		movhs	\irqstat,\irqstat,lsr#16
-		cmp	\irqstat,#1<<8
-		addhs	\irqnr,\irqnr,#8
-		movhs	\irqstat,\irqstat,lsr#8
-		cmp	\irqstat,#1<<4
-		addhs	\irqnr,\irqnr,#4
-		movhs	\irqstat,\irqstat,lsr#4
-		cmp	\irqstat,#1<<2
-		addhs	\irqnr,\irqnr,#2
-		movhs	\irqstat,\irqstat,lsr#2
-		cmp	\irqstat,#1<<1
-		addhs	\irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
-		teq	\irqstat,#0
-		beq	1003f
-
-/* and now check for extended IRQ reasons */
-		cmp	\irqnr,#1
-		bls	1003f
-		cmp	\irqnr,#30
-		blo	1002f
-
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-		moveq  \irqnr,#SIC1_BASE_INT
-		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-		movne   \irqnr,#SIC2_BASE_INT
-		ldr	\irqstat, [\base, #INTRC_STAT]
-		ldr	\tmp,	  [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-		and	\irqstat,\irqstat,\tmp
-		b	1004f
-
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-		movne   \irqnr,#SIC1_BASE_INT
-		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-		moveq   \irqnr,#SIC2_BASE_INT
-		ldr	\irqstat, [\base, #INTRC_STAT]
-		ldr	\tmp,	  [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-		bic	\irqstat,\irqstat,\tmp
-
-1004:
-
-		cmp	\irqstat,#1<<16
-		addhs	\irqnr,\irqnr,#16
-		movhs	\irqstat,\irqstat,lsr#16
-		cmp	\irqstat,#1<<8
-		addhs	\irqnr,\irqnr,#8
-		movhs	\irqstat,\irqstat,lsr#8
-		cmp	\irqstat,#1<<4
-		addhs	\irqnr,\irqnr,#4
-		movhs	\irqstat,\irqstat,lsr#4
-		cmp	\irqstat,#1<<2
-		addhs	\irqnr,\irqnr,#2
-		movhs	\irqstat,\irqstat,lsr#2
-		cmp	\irqstat,#1<<1
-		addhs	\irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-		teq	\irqstat,#0
-1003:
-		.endm
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN		(0)
-#define GPIO_OUT		(0x100)
-#define GPIO_BID		(0x200)
-#define GPIO_RAM		(0x300)
-#define GPIO_MUX		(0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00		(GPIO_IN | 0)
-#define GPI_01		(GPIO_IN | 1)
-#define GPI_02   	(GPIO_IN | 2)
-#define GPI_03 	 	(GPIO_IN | 3)
-#define GPI_04   	(GPIO_IN | 4)
-#define GPI_05   	(GPIO_IN | 5)
-#define GPI_06   	(GPIO_IN | 6)
-#define GPI_07   	(GPIO_IN | 7)
-#define GPI_08   	(GPIO_IN | 8)
-#define GPI_09   	(GPIO_IN | 9)
-#define U1_RX 		(GPIO_IN | 15)
-#define U2_HTCS 	(GPIO_IN | 16)
-#define U2_RX	 	(GPIO_IN | 17)
-#define U3_RX		(GPIO_IN | 18)
-#define U4_RX		(GPIO_IN | 19)
-#define U5_RX		(GPIO_IN | 20)
-#define U6_IRRX 	(GPIO_IN | 21)
-#define U7_HCTS 	(GPIO_IN | 22)
-#define U7_RX		(GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN	(GPIO_IN | 25)
-#define DISP_SYNC	(GPIO_IN | 26)
-#define SPI2_DATIN	(GPIO_IN | 27)
-#define GPI_11  	(GPIO_IN | 28)
-
-#define GPIO_IN_MASK   0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00		(GPIO_OUT | 0)
-#define GPO_01   	(GPIO_OUT | 1)
-#define GPO_02   	(GPIO_OUT | 2)
-#define GPO_03 	 	(GPIO_OUT | 3)
-#define GPO_04   	(GPIO_OUT | 4)
-#define GPO_05   	(GPIO_OUT | 5)
-#define GPO_06   	(GPIO_OUT | 6)
-#define GPO_07   	(GPIO_OUT | 7)
-#define GPO_08		(GPIO_OUT | 8)
-#define GPO_09   	(GPIO_OUT | 9)
-#define GPO_10   	(GPIO_OUT | 10)
-#define GPO_11 	 	(GPIO_OUT | 11)
-#define GPO_12   	(GPIO_OUT | 12)
-#define GPO_13   	(GPIO_OUT | 13)
-#define GPO_14   	(GPIO_OUT | 14)
-#define GPO_15   	(GPIO_OUT | 15)
-#define GPO_16  	(GPIO_OUT | 16)
-#define GPO_17 	 	(GPIO_OUT | 17)
-#define GPO_18   	(GPIO_OUT | 18)
-#define GPO_19   	(GPIO_OUT | 19)
-#define GPO_20   	(GPIO_OUT | 20)
-#define GPO_21   	(GPIO_OUT | 21)
-#define GPO_22   	(GPIO_OUT | 22)
-#define GPO_23   	(GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK   0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19		(GPIO_RAM | 0)
-#define RAM_D20  	(GPIO_RAM | 1)
-#define RAM_D21  	(GPIO_RAM | 2)
-#define RAM_D22 	(GPIO_RAM | 3)
-#define RAM_D23  	(GPIO_RAM | 4)
-#define RAM_D24  	(GPIO_RAM | 5)
-#define RAM_D25  	(GPIO_RAM | 6)
-#define RAM_D26  	(GPIO_RAM | 7)
-#define RAM_D27		(GPIO_RAM | 8)
-#define RAM_D28  	(GPIO_RAM | 9)
-#define RAM_D29  	(GPIO_RAM | 10)
-#define RAM_D30 	(GPIO_RAM | 11)
-#define RAM_D31  	(GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK   0x1fff
-
-/* I/O pins */
-#define GPIO_00  	(GPIO_BID | 25)
-#define GPIO_01 	(GPIO_BID | 26)
-#define GPIO_02  	(GPIO_BID | 27)
-#define GPIO_03  	(GPIO_BID | 28)
-#define GPIO_04 	(GPIO_BID | 29)
-#define GPIO_05  	(GPIO_BID | 30)
-
-#define GPIO_BID_MASK   0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL 	(GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK   0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-		     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-		     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
-	__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-		     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-		     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif				/* _PNX4008_GPIO_H_ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source at mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS         96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT   64
-
-#define CLK_SWITCH_ARM_INT 95	/*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94	/*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93	/*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT   32
-
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT   0
-
-#define SUB2_FIQ_N         31	/*active low */
-#define SUB1_FIQ_N         30	/*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1	/*active low */
-#define SUB1_IRQ_N         0	/*active low */
-
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-
-#endif /* __PNX4008_IRQS_h__ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/param.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/param.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define HZ 100
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE		0x08000000
-#define PNX4008_IRAM_SIZE		0x00010000
-#define PNX4008_YUV_SLAVE_BASE		0x10000000
-#define PNX4008_DUM_SLAVE_BASE		0x18000000
-#define PNX4008_NDF_FLASH_BASE		0x20020000
-#define PNX4008_SPI1_BASE		0x20088000
-#define PNX4008_SPI2_BASE		0x20090000
-#define PNX4008_SD_CONFIG_BASE		0x20098000
-#define PNX4008_FLASH_DATA		0x200B0000
-#define PNX4008_MLC_FLASH_BASE		0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE	0x300A0000
-#define PNX4008_DMA_CONFIG_BASE		0x31000000
-#define PNX4008_USB_CONFIG_BASE		0x31020000
-#define PNX4008_SDRAM_CFG_BASE		0x31080000
-#define PNX4008_AHB2FAB_BASE		0x40000000
-#define PNX4008_PWRMAN_BASE		0x40004000
-#define PNX4008_INTCTRLMIC_BASE		0x40008000
-#define PNX4008_INTCTRLSIC1_BASE	0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE	0x40010000
-#define PNX4008_HSUART1_BASE		0x40014000
-#define PNX4008_HSUART2_BASE		0x40018000
-#define PNX4008_HSUART7_BASE		0x4001C000
-#define PNX4008_RTC_BASE		0x40024000
-#define PNX4008_PIO_BASE		0x40028000
-#define PNX4008_MSTIMER_BASE		0x40034000
-#define PNX4008_HSTIMER_BASE		0x40038000
-#define PNX4008_WDOG_BASE		0x4003C000
-#define PNX4008_DEBUG_BASE		0x40040000
-#define PNX4008_TOUCH1_BASE		0x40048000
-#define PNX4008_KEYSCAN_BASE		0x40050000
-#define PNX4008_UARTCTRL_BASE		0x40054000
-#define PNX4008_PWM_BASE		0x4005C000
-#define PNX4008_UART3_BASE		0x40080000
-#define PNX4008_UART4_BASE		0x40088000
-#define PNX4008_UART5_BASE		0x40090000
-#define PNX4008_UART6_BASE		0x40098000
-#define PNX4008_I2C1_BASE		0x400A0000
-#define PNX4008_I2C2_BASE		0x400A8000
-#define PNX4008_MAGICGATE_BASE		0x400B0000
-#define PNX4008_DUMCONF_BASE		0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE       	0x400BC000
-#define PNX4008_DSP_BASE		0x400C0000
-#define PNX4008_PROFCOUNTER_BASE	0x400C8000
-#define PNX4008_CRYPTO_BASE		0x400D0000
-#define PNX4008_CAMIFCONF_BASE		0x400D8000
-#define PNX4008_YUV2RGB_BASE		0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE	0x400E8000
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif				/* ASSEMBLER */
-#endif				/* __ASM_ARCH_PNX4008_PM_H */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#define CLOCK_TICK_RATE		1000000
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
-	while (UART5_FR & (1 << 5))
-		barrier();
-
-	UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
--- linux-2.6.orig/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-
-static void pnx4008_mask_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));	/* mask interrupt */
-}
-
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq));	/* unmask interrupt */
-}
-
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));	/* mask interrupt */
-	__raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));	/* clear interrupt status */
-}
-
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));	/*edge sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));	/*rising edge */
-		irq_set_handler(d->irq, handle_edge_irq);
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));	/*edge sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));	/*falling edge */
-		irq_set_handler(d->irq, handle_edge_irq);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));	/*level sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));	/*low level */
-		irq_set_handler(d->irq, handle_level_irq);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));	/*level sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));	/* high level */
-		irq_set_handler(d->irq, handle_level_irq);
-		break;
-
-	/* IRQ_TYPE_EDGE_BOTH is not supported */
-	default:
-		printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
-		return -1;
-	}
-	return 0;
-}
-
-static struct irq_chip pnx4008_irq_chip = {
-	.irq_ack = pnx4008_mask_ack_irq,
-	.irq_mask = pnx4008_mask_irq,
-	.irq_unmask = pnx4008_unmask_irq,
-	.irq_set_type = pnx4008_set_irq_type,
-};
-
-void __init pnx4008_init_irq(void)
-{
-	unsigned int i;
-
-	/* configure IRQ's */
-	for (i = 0; i < NR_IRQS; i++) {
-		set_irq_flags(i, IRQF_VALID);
-		irq_set_chip(i, &pnx4008_irq_chip);
-		pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
-	}
-
-	/* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-	pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
-			     pnx4008_irq_type[SUB1_IRQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
-			     pnx4008_irq_type[SUB2_IRQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
-			     pnx4008_irq_type[SUB1_FIQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
-			     pnx4008_irq_type[SUB2_FIQ_N]);
-
-	/* mask all others */
-	__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
-			(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
-		INTC_ER(MAIN_BASE_INT));
-	__raw_writel(0, INTC_ER(SIC1_BASE_INT));
-	__raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-
-static void *saved_sram;
-
-static struct clk *pll4_clk;
-
-static inline void pnx4008_standby(void)
-{
-	void (*pnx4008_cpu_standby_ptr) (void);
-
-	local_irq_disable();
-	local_fiq_disable();
-
-	clk_disable(pll4_clk);
-
-	/*saving portion of SRAM to be used by suspend function. */
-	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-
-	/*make sure SRAM copy gets physically written into SDRAM.
-	   SDRAM will be placed into self-refresh during power down */
-	flush_cache_all();
-
-	/*copy suspend function into SRAM */
-	memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-
-	/*do suspend */
-	pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
-	pnx4008_cpu_standby_ptr();
-
-	/*restoring portion of SRAM that was used by suspend function */
-	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-
-	clk_enable(pll4_clk);
-
-	local_fiq_enable();
-	local_irq_enable();
-}
-
-static inline void pnx4008_suspend(void)
-{
-	void (*pnx4008_cpu_suspend_ptr) (void);
-
-	local_irq_disable();
-	local_fiq_disable();
-
-	clk_disable(pll4_clk);
-
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-	/*saving portion of SRAM to be used by suspend function. */
-	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-
-	/*make sure SRAM copy gets physically written into SDRAM.
-	   SDRAM will be placed into self-refresh during power down */
-	flush_cache_all();
-
-	/*copy suspend function into SRAM */
-	memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-
-	/*do suspend */
-	pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
-	pnx4008_cpu_suspend_ptr();
-
-	/*restoring portion of SRAM that was used by suspend function */
-	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-
-	clk_enable(pll4_clk);
-
-	local_fiq_enable();
-	local_irq_enable();
-}
-
-static int pnx4008_pm_enter(suspend_state_t state)
-{
-	switch (state) {
-	case PM_SUSPEND_STANDBY:
-		pnx4008_standby();
-		break;
-	case PM_SUSPEND_MEM:
-		pnx4008_suspend();
-		break;
-	}
-	return 0;
-}
-
-static int pnx4008_pm_valid(suspend_state_t state)
-{
-	return (state == PM_SUSPEND_STANDBY) ||
-	       (state == PM_SUSPEND_MEM);
-}
-
-static const struct platform_suspend_ops pnx4008_pm_ops = {
-	.enter = pnx4008_pm_enter,
-	.valid = pnx4008_pm_valid,
-};
-
-int __init pnx4008_pm_init(void)
-{
-	u32 sram_size_to_allocate;
-
-	pll4_clk = clk_get(0, "ck_pll4");
-	if (IS_ERR(pll4_clk)) {
-		printk(KERN_ERR
-		       "PM Suspend cannot acquire ARM(PLL4) clock control\n");
-		return PTR_ERR(pll4_clk);
-	}
-
-	if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
-		sram_size_to_allocate = pnx4008_cpu_standby_sz;
-	else
-		sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-
-	saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
-	if (!saved_sram) {
-		printk(KERN_ERR
-		       "PM Suspend: cannot allocate memory to save portion of SRAM\n");
-		clk_put(pll4_clk);
-		return -ENOMEM;
-	}
-
-	suspend_set_ops(&pnx4008_pm_ops);
-	return 0;
-}
--- linux-2.6.orig/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/serial.c
- *
- *  PNX4008 UART initialization
- *
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <mach/platform.h>
-#include <mach/hardware.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-
-#define UART_3		0
-#define UART_4		1
-#define UART_5		2
-#define UART_6		3
-#define UART_UNKNOWN	(-1)
-
-#define UART3_BASE_VA	IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA	IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA	IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA	IO_ADDRESS(PNX4008_UART6_BASE)
-
-#define UART_FCR_OFFSET		8
-#define UART_FIFO_SIZE		64
-
-void pnx4008_uart_init(void)
-{
-	u32 tmp;
-	int i = UART_FIFO_SIZE;
-
-	__raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
-	__raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-
-	/* Send a NULL to fix the UART HW bug */
-	__raw_writel(0x00, UART5_BASE_VA);
-	__raw_writel(0x00, UART3_BASE_VA);
-
-	while (i--) {
-		tmp = __raw_readl(UART5_BASE_VA);
-		tmp = __raw_readl(UART3_BASE_VA);
-	}
-	__raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
-	__raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-
-	/* setup wakeup interrupt */
-	start_int_set_rising_edge(SE_U3_RX_INT);
-	start_int_ack(SE_U3_RX_INT);
-	start_int_umask(SE_U3_RX_INT);
-
-	start_int_set_rising_edge(SE_U5_RX_INT);
-	start_int_ack(SE_U5_RX_INT);
-	start_int_umask(SE_U5_RX_INT);
-}
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-
-		.text
-
-ENTRY(pnx4008_cpu_suspend)
-	@this function should be entered in Direct run mode.
-
-	@ save registers on stack
-	stmfd	sp!, {r0 - r6, lr}
-
-	@ setup Power Manager base address in r4
-	@ and put it's value in r5
-	mov	r4, #(PWRMAN_VA_BASE & 0xff000000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-	ldr	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ setup SDRAM controller base address in r2
-	@ and put it's value in r3
-	mov	r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do save current bit settings in r1
-	mov	r1, r5
-
-	@ set SDRAM self-refresh bit
-	orr	r5, r5, #(1 << 9)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get into self-refresh mode
-2:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #(1 << 2)
-	beq	2b
-
-	@ to prepare SDRAM to get out of self-refresh mode after wakeup
-	orr	r5, r5, #(1 << 7)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do enter stop mode
-	orr	r5, r5, #(1 << 0)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	@ sleeping now...
-
-	@ coming out of STOP mode into Direct Run mode
-	@ clear STOP mode and SDRAM self-refresh bits
-	str	r1, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get out self-refresh mode
-3:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #5
-	bne	3b
-
-	@ restore regs and return
-	ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_suspend_sz)
-	.word	. - pnx4008_cpu_suspend
-
-ENTRY(pnx4008_cpu_standby)
-	@ save registers on stack
-	stmfd	sp!, {r0 - r6, lr}
-
-	@ setup Power Manager base address in r4
-	@ and put it's value in r5
-	mov	r4, #(PWRMAN_VA_BASE & 0xff000000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-	ldr	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ setup SDRAM controller base address in r2
-	@ and put it's value in r3
-	mov	r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do save current bit settings in r1
-	mov	r1, r5
-
-	@ set SDRAM self-refresh bit
-	orr	r5, r5, #(1 << 9)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get into self-refresh mode
-2:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #(1 << 2)
-	beq	2b
-
-	@ set 'get out of self-refresh mode after wakeup' bit
-	orr	r5, r5, #(1 << 7)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	mcr     p15, 0, r0, c7, c0, 4	@ kinda sleeping now...
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get out self-refresh mode
-3:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #5
-	bne	3b
-
-	@ restore regs and return
-	ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_standby_sz)
-	.word	. - pnx4008_cpu_standby
-
-ENTRY(pnx4008_cache_clean_invalidate)
-	stmfd	sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
-#else
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test,clean,invalidate
-	bne     1b
-#endif
-	ldmfd   sp!, {r0 - r6, pc}
--- linux-2.6.orig/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-
-#include "time.h"
-
-/*! Note: all timers are UPCOUNTING */
-
-/*!
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
-	u32 ticks_to_match =
-	    __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
-	u32 elapsed = LATCH - ticks_to_match;
-	return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
-	if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-
-		do {
-			timer_tick();
-
-			/*
-			 * this algorithm takes care of possible delay
-			 * for this interrupt handling longer than a normal
-			 * timer period
-			 */
-			__raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
-				     HSTIM_MATCH0);
-			__raw_writel(MATCH0_INT, HSTIM_INT);	/* clear interrupt */
-
-			/*
-			 * The goal is to keep incrementing HSTIM_MATCH0
-			 * register until HSTIM_MATCH0 indicates time after
-			 * what HSTIM_COUNTER indicates.
-			 */
-		} while ((signed)
-			 (__raw_readl(HSTIM_MATCH0) -
-			  __raw_readl(HSTIM_COUNTER)) < 0);
-	}
-
-	return IRQ_HANDLED;
-}
-
-static struct irqaction pnx4008_timer_irq = {
-	.name = "PNX4008 Tick Timer",
-	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler = pnx4008_timer_interrupt
-};
-
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
-	__raw_writel(RESET_COUNT, MSTIM_CTRL);
-	while (__raw_readl(MSTIM_COUNTER)) ;	/* wait for reset to complete. 100% guarantee event */
-	__raw_writel(0, MSTIM_CTRL);	/* stop the timer */
-	__raw_writel(0, MSTIM_MCTRL);
-
-	__raw_writel(RESET_COUNT, HSTIM_CTRL);
-	while (__raw_readl(HSTIM_COUNTER)) ;	/* wait for reset to complete. 100% guarantee event */
-	__raw_writel(0, HSTIM_CTRL);
-	__raw_writel(0, HSTIM_MCTRL);
-	__raw_writel(0, HSTIM_CCR);
-	__raw_writel(12, HSTIM_PMATCH);	/* scale down to 1 MHZ */
-	__raw_writel(LATCH, HSTIM_MATCH0);
-	__raw_writel(MR0_INT, HSTIM_MCTRL);
-
-	setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-
-	__raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);	/*start timer, stop when JTAG active */
-}
-
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN                   1
-#define TIMER_CLK_EN                      2	/* HS and MS timers? */
-
-static u32 timclk_ctrl_reg_save;
-
-void pnx4008_timer_suspend(void)
-{
-	timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
-	__raw_writel(0, TIMCLK_CTRL_REG);	/* disable timers */
-}
-
-void pnx4008_timer_resume(void)
-{
-	__raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);	/* enable timers */
-}
-
-struct sys_timer pnx4008_timer = {
-	.init = pnx4008_setup_timer,
-	.offset = pnx4008_gettimeoffset,
-	.suspend = pnx4008_timer_suspend,
-	.resume = pnx4008_timer_resume,
-};
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#define TICKS2USECS(x)	(x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
-#endif
--- linux-2.6.orig/arch/arm/tools/mach-types
+++ linux-2.6/arch/arm/tools/mach-types
@@ -158,7 +158,6 @@ edb9315a		MACH_EDB9315A		EDB9315A		772
 stargate2		MACH_STARGATE2		STARGATE2		774
 intelmote2		MACH_INTELMOTE2		INTELMOTE2		775
 trizeps4		MACH_TRIZEPS4		TRIZEPS4		776
-pnx4008			MACH_PNX4008		PNX4008			782
 cpuat91			MACH_CPUAT91		CPUAT91			787
 iq81340sc		MACH_IQ81340SC		IQ81340SC		799
 iq81340mc		MACH_IQ81340MC		IQ81340MC		801
--- linux-2.6.orig/drivers/i2c/busses/Kconfig
+++ linux-2.6/drivers/i2c/busses/Kconfig
@@ -545,7 +545,7 @@ config I2C_PMCMSP
 
 config I2C_PNX
 	tristate "I2C bus support for Philips PNX and NXP LPC targets"
-	depends on ARCH_PNX4008 || ARCH_LPC32XX
+	depends on ARCH_LPC32XX
 	help
 	  This driver supports the Philips IP3204 I2C IP block master and/or
 	  slave controller
--- linux-2.6.orig/drivers/usb/Kconfig
+++ linux-2.6/drivers/usb/Kconfig
@@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI
 	default y if PXA3xx
 	default y if ARCH_EP93XX
 	default y if ARCH_AT91
-	default y if ARCH_PNX4008
 	default y if MFD_TC6393XB
 	default y if ARCH_W90X900
 	default y if ARCH_DAVINCI_DA8XX
--- linux-2.6.orig/drivers/usb/host/Kconfig
+++ linux-2.6/drivers/usb/host/Kconfig
@@ -292,7 +292,7 @@ config USB_OHCI_HCD
 	depends on USB && USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	select USB_OTG_UTILS if ARCH_OMAP
-	select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
+	select USB_ISP1301 if ARCH_LPC32XX
 	---help---
 	  The Open Host Controller Interface (OHCI) is a standard for accessing
 	  USB 1.1 host controller hardware.  It does more in hardware than Intel's
--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
+#ifdef CONFIG_ARCH_LPC32XX
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -2,7 +2,6 @@
  * driver for NXP USB Host devices
  *
  * Currently supported OHCI host devices:
- * - Philips PNX4008
  * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
@@ -66,38 +65,6 @@ static struct clk *usb_pll_clk;
 static struct clk *usb_dev_clk;
 static struct clk *usb_otg_clk;
 
-static void isp1301_configure_pnx4008(void)
-{
-	/* PNX4008 only supports DAT_SE0 USB mode */
-	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-	/* Power up externel charge-pump */
-
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(MC1_DAT_SE0 | MC1_SPEED_REG));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_2,
-		MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
-		0xFF);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
-		0xFF);
-}
-
 static void isp1301_configure_lpc32xx(void)
 {
 	/* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(vo
 
 static void isp1301_configure(void)
 {
-	if (machine_is_pnx4008())
-		isp1301_configure_pnx4008();
-	else
-		isp1301_configure_lpc32xx();
+	isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_h
 	.start_port_reset = ohci_start_port_reset,
 };
 
-static void nxp_set_usb_bits(void)
-{
-	if (machine_is_pnx4008()) {
-		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-		start_int_ack(SE_USB_OTG_ATX_INT_N);
-		start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-		start_int_ack(SE_USB_OTG_TIMER_INT);
-		start_int_umask(SE_USB_OTG_TIMER_INT);
-
-		start_int_set_rising_edge(SE_USB_I2C_INT);
-		start_int_ack(SE_USB_I2C_INT);
-		start_int_umask(SE_USB_I2C_INT);
-
-		start_int_set_rising_edge(SE_USB_INT);
-		start_int_ack(SE_USB_INT);
-		start_int_umask(SE_USB_INT);
-
-		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-		start_int_ack(SE_USB_NEED_CLK_INT);
-		start_int_umask(SE_USB_NEED_CLK_INT);
-
-		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-	}
-}
-
-static void nxp_unset_usb_bits(void)
-{
-	if (machine_is_pnx4008()) {
-		start_int_mask(SE_USB_OTG_ATX_INT_N);
-		start_int_mask(SE_USB_OTG_TIMER_INT);
-		start_int_mask(SE_USB_I2C_INT);
-		start_int_mask(SE_USB_INT);
-		start_int_mask(SE_USB_NEED_CLK_INT);
-		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-	}
-}
-
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(s
 		goto out8;
 	}
 
-	/* Set all USB bits in the Start Enable register */
-	nxp_set_usb_bits();
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(s
 
 	nxp_stop_hc();
 out8:
-	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out7:
 	clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct pla
 	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	nxp_unset_usb_bits();
 	clk_disable(usb_pll_clk);
 	clk_put(usb_pll_clk);
 	clk_disable(usb_dev_clk);
--- linux-2.6.orig/drivers/video/Kconfig
+++ linux-2.6/drivers/video/Kconfig
@@ -2151,21 +2151,6 @@ config FB_UDL
 	  mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
 	  To compile as a module, choose M here: the module name is udlfb.
 
-config FB_PNX4008_DUM
-	tristate "Display Update Module support on Philips PNX4008 board"
-	depends on FB && ARCH_PNX4008
-	---help---
-	  Say Y here to enable support for PNX4008 Display Update Module (DUM)
-
-config FB_PNX4008_DUM_RGB
-	tristate "RGB Framebuffer support on Philips PNX4008 board"
-	depends on FB_PNX4008_DUM
-	select FB_CFB_FILLRECT
-	select FB_CFB_COPYAREA
-	select FB_CFB_IMAGEBLIT
-	---help---
-	  Say Y here to enable support for PNX4008 RGB Framebuffer
-
 config FB_IBM_GXT4500
 	tristate "Framebuffer support for IBM GXT4500P adaptor"
 	depends on FB && PPC
--- linux-2.6.orig/drivers/video/Makefile
+++ linux-2.6/drivers/video/Makefile
@@ -128,8 +128,6 @@ obj-$(CONFIG_FB_S3C)		  += s3c-fb.o
 obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
 obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o
 obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
-obj-$(CONFIG_FB_PNX4008_DUM)	  += pnx4008/
-obj-$(CONFIG_FB_PNX4008_DUM_RGB)  += pnx4008/
 obj-$(CONFIG_FB_IBM_GXT4500)	  += gxt4500.o
 obj-$(CONFIG_FB_PS3)		  += ps3fb.o
 obj-$(CONFIG_FB_SM501)            += sm501fb.o
--- linux-2.6.orig/drivers/video/pnx4008/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the new PNX4008 framebuffer device driver
-#
-
-obj-$(CONFIG_FB_PNX4008_DUM) += sdum.o
-obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnxrgbfb.o
-
--- linux-2.6.orig/drivers/video/pnx4008/dum.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * linux/drivers/video/pnx4008/dum.h
- *
- * Internal header for SDUM
- *
- * 2005 (c) Koninklijke Philips N.V. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX008_DUM_H__
-#define __PNX008_DUM_H__
-
-#include <mach/platform.h>
-
-#define PNX4008_DUMCONF_VA_BASE		IO_ADDRESS(PNX4008_DUMCONF_BASE)
-#define PNX4008_DUM_MAIN_VA_BASE	IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)
-
-/* DUM CFG ADDRESSES */
-#define DUM_CH_BASE_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)
-#define DUM_CH_MIN_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)
-#define DUM_CH_MAX_ADR		(PNX4008_DUMCONF_VA_BASE + 0x04)
-#define DUM_CH_CONF_ADR		(PNX4008_DUMCONF_VA_BASE + 0x08)
-#define DUM_CH_STAT_ADR		(PNX4008_DUMCONF_VA_BASE + 0x0C)
-#define DUM_CH_CTRL_ADR		(PNX4008_DUMCONF_VA_BASE + 0x10)
-
-#define CH_MARG		(0x100 / sizeof(u32))
-#define DUM_CH_MIN(i)	(*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))
-#define DUM_CH_MAX(i)	(*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))
-#define DUM_CH_CONF(i)	(*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))
-#define DUM_CH_STAT(i)	(*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))
-#define DUM_CH_CTRL(i)	(*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))
-
-#define DUM_CONF_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x00)
-#define DUM_CTRL_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x04)
-#define DUM_STAT_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x08)
-#define DUM_DECODE_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x0C)
-#define DUM_COM_BASE_ADR      (PNX4008_DUM_MAIN_VA_BASE + 0x10)
-#define DUM_SYNC_C_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x14)
-#define DUM_CLK_DIV_ADR       (PNX4008_DUM_MAIN_VA_BASE + 0x18)
-#define DUM_DIRTY_LOW_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x20)
-#define DUM_DIRTY_HIGH_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x24)
-#define DUM_FORMAT_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x28)
-#define DUM_WTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x30)
-#define DUM_RTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x34)
-#define DUM_WTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x38)
-#define DUM_RTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x3C)
-#define DUM_TCFG_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x40)
-#define DUM_OUTP_FORMAT1_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x44)
-#define DUM_OUTP_FORMAT2_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x48)
-#define DUM_SYNC_MODE_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x4C)
-#define DUM_SYNC_OUT_C_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x50)
-
-#define DUM_CONF              (*(volatile u32 *)(DUM_CONF_ADR))
-#define DUM_CTRL              (*(volatile u32 *)(DUM_CTRL_ADR))
-#define DUM_STAT              (*(volatile u32 *)(DUM_STAT_ADR))
-#define DUM_DECODE            (*(volatile u32 *)(DUM_DECODE_ADR))
-#define DUM_COM_BASE          (*(volatile u32 *)(DUM_COM_BASE_ADR))
-#define DUM_SYNC_C            (*(volatile u32 *)(DUM_SYNC_C_ADR))
-#define DUM_CLK_DIV           (*(volatile u32 *)(DUM_CLK_DIV_ADR))
-#define DUM_DIRTY_LOW         (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))
-#define DUM_DIRTY_HIGH        (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))
-#define DUM_FORMAT            (*(volatile u32 *)(DUM_FORMAT_ADR))
-#define DUM_WTCFG1            (*(volatile u32 *)(DUM_WTCFG1_ADR))
-#define DUM_RTCFG1            (*(volatile u32 *)(DUM_RTCFG1_ADR))
-#define DUM_WTCFG2            (*(volatile u32 *)(DUM_WTCFG2_ADR))
-#define DUM_RTCFG2            (*(volatile u32 *)(DUM_RTCFG2_ADR))
-#define DUM_TCFG              (*(volatile u32 *)(DUM_TCFG_ADR))
-#define DUM_OUTP_FORMAT1      (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))
-#define DUM_OUTP_FORMAT2      (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))
-#define DUM_SYNC_MODE         (*(volatile u32 *)(DUM_SYNC_MODE_ADR))
-#define DUM_SYNC_OUT_C        (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))
-
-/* DUM SLAVE ADDRESSES */
-#define DUM_SLAVE_WRITE_ADR      (PNX4008_DUM_MAINCFG_BASE + 0x0000000)
-#define DUM_SLAVE_READ1_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000000)
-#define DUM_SLAVE_READ1_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000004)
-#define DUM_SLAVE_READ2_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000008)
-#define DUM_SLAVE_READ2_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x100000C)
-
-#define DUM_SLAVE_WRITE_W  ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))
-#define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))
-#define DUM_SLAVE_READ1_I  ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))
-#define DUM_SLAVE_READ1_R  ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))
-#define DUM_SLAVE_READ2_I  ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))
-#define DUM_SLAVE_READ2_R  ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))
-
-/* Sony display register addresses */
-#define DISP_0_REG            (0x00)
-#define DISP_1_REG            (0x01)
-#define DISP_CAL_REG          (0x20)
-#define DISP_ID_REG           (0x2A)
-#define DISP_XMIN_L_REG       (0x30)
-#define DISP_XMIN_H_REG       (0x31)
-#define DISP_YMIN_REG         (0x32)
-#define DISP_XMAX_L_REG       (0x34)
-#define DISP_XMAX_H_REG       (0x35)
-#define DISP_YMAX_REG         (0x36)
-#define DISP_SYNC_EN_REG      (0x38)
-#define DISP_SYNC_RISE_L_REG  (0x3C)
-#define DISP_SYNC_RISE_H_REG  (0x3D)
-#define DISP_SYNC_FALL_L_REG  (0x3E)
-#define DISP_SYNC_FALL_H_REG  (0x3F)
-#define DISP_PIXEL_REG        (0x0B)
-#define DISP_DUMMY1_REG       (0x28)
-#define DISP_DUMMY2_REG       (0x29)
-#define DISP_TIMING_REG       (0x98)
-#define DISP_DUMP_REG         (0x99)
-
-/* Sony display constants */
-#define SONY_ID1              (0x22)
-#define SONY_ID2              (0x23)
-
-/* Philips display register addresses */
-#define PH_DISP_ORIENT_REG    (0x003)
-#define PH_DISP_YPOINT_REG    (0x200)
-#define PH_DISP_XPOINT_REG    (0x201)
-#define PH_DISP_PIXEL_REG     (0x202)
-#define PH_DISP_YMIN_REG      (0x406)
-#define PH_DISP_YMAX_REG      (0x407)
-#define PH_DISP_XMIN_REG      (0x408)
-#define PH_DISP_XMAX_REG      (0x409)
-
-/* Misc constants */
-#define NO_VALID_DISPLAY_FOUND      (0)
-#define DISPLAY2_IS_NOT_CONNECTED   (0)
-
-/* register values */
-#define V_BAC_ENABLE		(BIT(0))
-#define V_BAC_DISABLE_IDLE	(BIT(1))
-#define V_BAC_DISABLE_TRIG	(BIT(2))
-#define V_DUM_RESET		(BIT(3))
-#define V_MUX_RESET		(BIT(4))
-#define BAC_ENABLED		(BIT(0))
-#define BAC_DISABLED		0
-
-/* Sony LCD commands */
-#define V_LCD_STANDBY_OFF	((BIT(25)) | (0 << 16) | DISP_0_REG)
-#define V_LCD_USE_9BIT_BUS	((BIT(25)) | (2 << 16) | DISP_1_REG)
-#define V_LCD_SYNC_RISE_L	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)
-#define V_LCD_SYNC_RISE_H	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)
-#define V_LCD_SYNC_FALL_L	((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)
-#define V_LCD_SYNC_FALL_H	((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)
-#define V_LCD_SYNC_ENABLE	((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)
-#define V_LCD_DISPLAY_ON	((BIT(25)) | (64 << 16) | DISP_0_REG)
-
-enum {
-	PAD_NONE,
-	PAD_512,
-	PAD_1024
-};
-
-enum {
-	RGB888,
-	RGB666,
-	RGB565,
-	BGR565,
-	ARGB1555,
-	ABGR1555,
-	ARGB4444,
-	ABGR4444
-};
-
-struct dum_setup {
-	int sync_neg_edge;
-	int round_robin;
-	int mux_int;
-	int synced_dirty_flag_int;
-	int dirty_flag_int;
-	int error_int;
-	int pf_empty_int;
-	int sf_empty_int;
-	int bac_dis_int;
-	u32 dirty_base_adr;
-	u32 command_base_adr;
-	u32 sync_clk_div;
-	int sync_output;
-	u32 sync_restart_val;
-	u32 set_sync_high;
-	u32 set_sync_low;
-};
-
-struct dum_ch_setup {
-	int disp_no;
-	u32 xmin;
-	u32 ymin;
-	u32 xmax;
-	u32 ymax;
-	int xmirror;
-	int ymirror;
-	int rotate;
-	u32 minadr;
-	u32 maxadr;
-	u32 dirtybuffer;
-	int pad;
-	int format;
-	int hwdirty;
-	int slave_trans;
-};
-
-struct disp_window {
-	u32 xmin_l;
-	u32 xmin_h;
-	u32 ymin;
-	u32 xmax_l;
-	u32 xmax_h;
-	u32 ymax;
-};
-
-#endif				/* #ifndef __PNX008_DUM_H__ */
--- linux-2.6.orig/drivers/video/pnx4008/fbcommon.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2005 Philips Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
-*/
-
-#define QCIF_W  (176)
-#define QCIF_H  (144)
-
-#define CIF_W   (352)
-#define CIF_H   (288)
-
-#define LCD_X_RES	208
-#define LCD_Y_RES	320
-#define LCD_X_PAD	256
-#define LCD_BBP		4	/* Bytes Per Pixel */
-
-#define DISP_MAX_X_SIZE     (320)
-#define DISP_MAX_Y_SIZE     (208)
-
-#define RETURNVAL_BASE (0x400)
-
-enum fb_ioctl_returntype {
-	ENORESOURCESLEFT = RETURNVAL_BASE,
-	ERESOURCESNOTFREED,
-	EPROCNOTOWNER,
-	EFBNOTOWNER,
-	ECOPYFAILED,
-	EIOREMAPFAILED,
-};
--- linux-2.6.orig/drivers/video/pnx4008/pnxrgbfb.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * drivers/video/pnx4008/pnxrgbfb.c
- *
- * PNX4008's framebuffer support
- *
- * Author: Grigory Tolstolytkin <gtolstolytkin at ru.mvista.com>
- * Based on Philips Semiconductors's code
- *
- * Copyrght (c) 2005 MontaVista Software, Inc.
- * Copyright (c) 2005 Philips Semiconductors
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include "sdum.h"
-#include "fbcommon.h"
-
-static u32 colreg[16];
-
-static struct fb_var_screeninfo rgbfb_var __initdata = {
-	.xres = LCD_X_RES,
-	.yres = LCD_Y_RES,
-	.xres_virtual = LCD_X_RES,
-	.yres_virtual = LCD_Y_RES,
-	.bits_per_pixel = 32,
-	.red.offset = 16,
-	.red.length = 8,
-	.green.offset = 8,
-	.green.length = 8,
-	.blue.offset = 0,
-	.blue.length = 8,
-	.left_margin = 0,
-	.right_margin = 0,
-	.upper_margin = 0,
-	.lower_margin = 0,
-	.vmode = FB_VMODE_NONINTERLACED,
-};
-static struct fb_fix_screeninfo rgbfb_fix __initdata = {
-	.id = "RGBFB",
-	.line_length = LCD_X_RES * LCD_BBP,
-	.type = FB_TYPE_PACKED_PIXELS,
-	.visual = FB_VISUAL_TRUECOLOR,
-	.xpanstep = 0,
-	.ypanstep = 0,
-	.ywrapstep = 0,
-	.accel = FB_ACCEL_NONE,
-};
-
-static int channel_owned;
-
-static int no_cursor(struct fb_info *info, struct fb_cursor *cursor)
-{
-	return 0;
-}
-
-static int rgbfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
-			   u_int transp, struct fb_info *info)
-{
-	if (regno > 15)
-		return 1;
-
-	colreg[regno] = ((red & 0xff00) << 8) | (green & 0xff00) |
-	    ((blue & 0xff00) >> 8);
-	return 0;
-}
-
-static int rgbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
-	return pnx4008_sdum_mmap(info, vma, NULL);
-}
-
-static struct fb_ops rgbfb_ops = {
-	.fb_mmap = rgbfb_mmap,
-	.fb_setcolreg = rgbfb_setcolreg,
-	.fb_fillrect = cfb_fillrect,
-	.fb_copyarea = cfb_copyarea,
-	.fb_imageblit = cfb_imageblit,
-};
-
-static int rgbfb_remove(struct platform_device *pdev)
-{
-	struct fb_info *info = platform_get_drvdata(pdev);
-
-	if (info) {
-		unregister_framebuffer(info);
-		fb_dealloc_cmap(&info->cmap);
-		framebuffer_release(info);
-		platform_set_drvdata(pdev, NULL);
-	}
-
-	pnx4008_free_dum_channel(channel_owned, pdev->id);
-	pnx4008_set_dum_exit_notification(pdev->id);
-
-	return 0;
-}
-
-static int __devinit rgbfb_probe(struct platform_device *pdev)
-{
-	struct fb_info *info;
-	struct dumchannel_uf chan_uf;
-	int ret;
-	char *option;
-
-	info = framebuffer_alloc(sizeof(u32) * 16, &pdev->dev);
-	if (!info) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	pnx4008_get_fb_addresses(FB_TYPE_RGB, (void **)&info->screen_base,
-				 (dma_addr_t *) &rgbfb_fix.smem_start,
-				 &rgbfb_fix.smem_len);
-
-	if ((ret = pnx4008_alloc_dum_channel(pdev->id)) < 0)
-		goto err0;
-	else {
-		channel_owned = ret;
-		chan_uf.channelnr = channel_owned;
-		chan_uf.dirty = (u32 *) NULL;
-		chan_uf.source = (u32 *) rgbfb_fix.smem_start;
-		chan_uf.x_offset = 0;
-		chan_uf.y_offset = 0;
-		chan_uf.width = LCD_X_RES;
-		chan_uf.height = LCD_Y_RES;
-
-		if ((ret = pnx4008_put_dum_channel_uf(chan_uf, pdev->id))< 0)
-			goto err1;
-
-		if ((ret =
-		     pnx4008_set_dum_channel_sync(channel_owned, CONF_SYNC_ON,
-						  pdev->id)) < 0)
-			goto err1;
-
-		if ((ret =
-		     pnx4008_set_dum_channel_dirty_detect(channel_owned,
-							 CONF_DIRTYDETECTION_ON,
-							 pdev->id)) < 0)
-			goto err1;
-	}
-
-	if (!fb_get_options("pnxrgbfb", &option) && option &&
-			!strcmp(option, "nocursor"))
-		rgbfb_ops.fb_cursor = no_cursor;
-
-	info->node = -1;
-	info->flags = FBINFO_FLAG_DEFAULT;
-	info->fbops = &rgbfb_ops;
-	info->fix = rgbfb_fix;
-	info->var = rgbfb_var;
-	info->screen_size = rgbfb_fix.smem_len;
-	info->pseudo_palette = info->par;
-	info->par = NULL;
-
-	ret = fb_alloc_cmap(&info->cmap, 256, 0);
-	if (ret < 0)
-		goto err1;
-
-	ret = register_framebuffer(info);
-	if (ret < 0)
-		goto err2;
-	platform_set_drvdata(pdev, info);
-
-	return 0;
-
-err2:
-	fb_dealloc_cmap(&info->cmap);
-err1:
-	pnx4008_free_dum_channel(channel_owned, pdev->id);
-err0:
-	framebuffer_release(info);
-err:
-	return ret;
-}
-
-static struct platform_driver rgbfb_driver = {
-	.driver = {
-		.name = "pnx4008-rgbfb",
-	},
-	.probe = rgbfb_probe,
-	.remove = rgbfb_remove,
-};
-
-module_platform_driver(rgbfb_driver);
-
-MODULE_LICENSE("GPL");
--- linux-2.6.orig/drivers/video/pnx4008/sdum.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/*
- * drivers/video/pnx4008/sdum.c
- *
- * Display Update Master support
- *
- * Authors: Grigory Tolstolytkin <gtolstolytkin at ru.mvista.com>
- *          Vitaly Wool <vitalywool at gmail.com>
- * Based on Philips Semiconductors's code
- *
- * Copyrght (c) 2005-2006 MontaVista Software, Inc.
- * Copyright (c) 2005 Philips Semiconductors
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/gfp.h>
-#include <asm/uaccess.h>
-#include <asm/gpio.h>
-
-#include "sdum.h"
-#include "fbcommon.h"
-#include "dum.h"
-
-/* Framebuffers we have */
-
-static struct pnx4008_fb_addr {
-	int fb_type;
-	long addr_offset;
-	long fb_length;
-} fb_addr[] = {
-	[0] = {
-		FB_TYPE_YUV, 0, 0xB0000
-	},
-	[1] = {
-		FB_TYPE_RGB, 0xB0000, 0x50000
-	},
-};
-
-static struct dum_data {
-	u32 lcd_phys_start;
-	u32 lcd_virt_start;
-	u32 slave_phys_base;
-	u32 *slave_virt_base;
-	int fb_owning_channel[MAX_DUM_CHANNELS];
-	struct dumchannel_uf chan_uf_store[MAX_DUM_CHANNELS];
-} dum_data;
-
-/* Different local helper functions */
-
-static u32 nof_pixels_dx(struct dum_ch_setup *ch_setup)
-{
-	return (ch_setup->xmax - ch_setup->xmin + 1);
-}
-
-static u32 nof_pixels_dy(struct dum_ch_setup *ch_setup)
-{
-	return (ch_setup->ymax - ch_setup->ymin + 1);
-}
-
-static u32 nof_pixels_dxy(struct dum_ch_setup *ch_setup)
-{
-	return (nof_pixels_dx(ch_setup) * nof_pixels_dy(ch_setup));
-}
-
-static u32 nof_bytes(struct dum_ch_setup *ch_setup)
-{
-	u32 r = nof_pixels_dxy(ch_setup);
-	switch (ch_setup->format) {
-	case RGB888:
-	case RGB666:
-		r *= 4;
-		break;
-
-	default:
-		r *= 2;
-		break;
-	}
-	return r;
-}
-
-static u32 build_command(int disp_no, u32 reg, u32 val)
-{
-	return ((disp_no << 26) | BIT(25) | (val << 16) | (disp_no << 10) |
-		(reg << 0));
-}
-
-static u32 build_double_index(int disp_no, u32 val)
-{
-	return ((disp_no << 26) | (val << 16) | (disp_no << 10) | (val << 0));
-}
-
-static void build_disp_window(struct dum_ch_setup * ch_setup, struct disp_window * dw)
-{
-	dw->ymin = ch_setup->ymin;
-	dw->ymax = ch_setup->ymax;
-	dw->xmin_l = ch_setup->xmin & 0xFF;
-	dw->xmin_h = (ch_setup->xmin & BIT(8)) >> 8;
-	dw->xmax_l = ch_setup->xmax & 0xFF;
-	dw->xmax_h = (ch_setup->xmax & BIT(8)) >> 8;
-}
-
-static int put_channel(struct dumchannel chan)
-{
-	int i = chan.channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else {
-		DUM_CH_MIN(i) = chan.dum_ch_min;
-		DUM_CH_MAX(i) = chan.dum_ch_max;
-		DUM_CH_CONF(i) = chan.dum_ch_conf;
-		DUM_CH_CTRL(i) = chan.dum_ch_ctrl;
-	}
-
-	return 0;
-}
-
-static void clear_channel(int channr)
-{
-	struct dumchannel chan;
-
-	chan.channelnr = channr;
-	chan.dum_ch_min = 0;
-	chan.dum_ch_max = 0;
-	chan.dum_ch_conf = 0;
-	chan.dum_ch_ctrl = 0;
-
-	put_channel(chan);
-}
-
-static int put_cmd_string(struct cmdstring cmds)
-{
-	u16 *cmd_str_virtaddr;
-	u32 *cmd_ptr0_virtaddr;
-	u32 cmd_str_physaddr;
-
-	int i = cmds.channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if ((cmd_ptr0_virtaddr =
-		  (int *)ioremap_nocache(DUM_COM_BASE,
-					 sizeof(int) * MAX_DUM_CHANNELS)) ==
-		 NULL)
-		return -EIOREMAPFAILED;
-	else {
-		cmd_str_physaddr = ioread32(&cmd_ptr0_virtaddr[cmds.channelnr]);
-		if ((cmd_str_virtaddr =
-		     (u16 *) ioremap_nocache(cmd_str_physaddr,
-					     sizeof(cmds))) == NULL) {
-			iounmap(cmd_ptr0_virtaddr);
-			return -EIOREMAPFAILED;
-		} else {
-			int t;
-			for (t = 0; t < 8; t++)
-				iowrite16(*((u16 *)&cmds.prestringlen + t),
-					  cmd_str_virtaddr + t);
-
-			for (t = 0; t < cmds.prestringlen / 2; t++)
-				 iowrite16(*((u16 *)&cmds.precmd + t),
-					   cmd_str_virtaddr + t + 8);
-
-			for (t = 0; t < cmds.poststringlen / 2; t++)
-				iowrite16(*((u16 *)&cmds.postcmd + t),
-					  cmd_str_virtaddr + t + 8 +
-					  	cmds.prestringlen / 2);
-
-			iounmap(cmd_ptr0_virtaddr);
-			iounmap(cmd_str_virtaddr);
-		}
-	}
-
-	return 0;
-}
-
-static u32 dum_ch_setup(int ch_no, struct dum_ch_setup * ch_setup)
-{
-	struct cmdstring cmds_c;
-	struct cmdstring *cmds = &cmds_c;
-	struct disp_window dw;
-	int standard;
-	u32 orientation = 0;
-	struct dumchannel chan = { 0 };
-	int ret;
-
-	if ((ch_setup->xmirror) || (ch_setup->ymirror) || (ch_setup->rotate)) {
-		standard = 0;
-
-		orientation = BIT(1);	/* always set 9-bit-bus */
-		if (ch_setup->xmirror)
-			orientation |= BIT(4);
-		if (ch_setup->ymirror)
-			orientation |= BIT(3);
-		if (ch_setup->rotate)
-			orientation |= BIT(0);
-	} else
-		standard = 1;
-
-	cmds->channelnr = ch_no;
-
-	/* build command string header */
-	if (standard) {
-		cmds->prestringlen = 32;
-		cmds->poststringlen = 0;
-	} else {
-		cmds->prestringlen = 48;
-		cmds->poststringlen = 16;
-	}
-
-	cmds->format =
-	    (u16) ((ch_setup->disp_no << 4) | (BIT(3)) | (ch_setup->format));
-	cmds->reserved = 0x0;
-	cmds->startaddr_low = (ch_setup->minadr & 0xFFFF);
-	cmds->startaddr_high = (ch_setup->minadr >> 16);
-
-	if ((ch_setup->minadr == 0) && (ch_setup->maxadr == 0)
-	    && (ch_setup->xmin == 0)
-	    && (ch_setup->ymin == 0) && (ch_setup->xmax == 0)
-	    && (ch_setup->ymax == 0)) {
-		cmds->pixdatlen_low = 0;
-		cmds->pixdatlen_high = 0;
-	} else {
-		u32 nbytes = nof_bytes(ch_setup);
-		cmds->pixdatlen_low = (nbytes & 0xFFFF);
-		cmds->pixdatlen_high = (nbytes >> 16);
-	}
-
-	if (ch_setup->slave_trans)
-		cmds->pixdatlen_high |= BIT(15);
-
-	/* build pre-string */
-	build_disp_window(ch_setup, &dw);
-
-	if (standard) {
-		cmds->precmd[0] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG, 0x99);
-		cmds->precmd[1] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-				  dw.xmin_l);
-		cmds->precmd[2] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
-				  dw.xmin_h);
-		cmds->precmd[3] =
-		    build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
-		cmds->precmd[4] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
-				  dw.xmax_l);
-		cmds->precmd[5] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
-				  dw.xmax_h);
-		cmds->precmd[6] =
-		    build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
-		cmds->precmd[7] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-	} else {
-		if (dw.xmin_l == ch_no)
-			cmds->precmd[0] =
-			    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-					  0x99);
-		else
-			cmds->precmd[0] =
-			    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-					  ch_no);
-
-		cmds->precmd[1] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_L_REG,
-				  dw.xmin_l);
-		cmds->precmd[2] =
-		    build_command(ch_setup->disp_no, DISP_XMIN_H_REG,
-				  dw.xmin_h);
-		cmds->precmd[3] =
-		    build_command(ch_setup->disp_no, DISP_YMIN_REG, dw.ymin);
-		cmds->precmd[4] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_L_REG,
-				  dw.xmax_l);
-		cmds->precmd[5] =
-		    build_command(ch_setup->disp_no, DISP_XMAX_H_REG,
-				  dw.xmax_h);
-		cmds->precmd[6] =
-		    build_command(ch_setup->disp_no, DISP_YMAX_REG, dw.ymax);
-		cmds->precmd[7] =
-		    build_command(ch_setup->disp_no, DISP_1_REG, orientation);
-		cmds->precmd[8] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[9] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[0xA] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->precmd[0xB] =
-		    build_double_index(ch_setup->disp_no, DISP_PIXEL_REG);
-		cmds->postcmd[0] =
-		    build_command(ch_setup->disp_no, DISP_1_REG, BIT(1));
-		cmds->postcmd[1] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 1);
-		cmds->postcmd[2] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 2);
-		cmds->postcmd[3] =
-		    build_command(ch_setup->disp_no, DISP_DUMMY1_REG, 3);
-	}
-
-	if ((ret = put_cmd_string(cmds_c)) != 0) {
-		return ret;
-	}
-
-	chan.channelnr = cmds->channelnr;
-	chan.dum_ch_min = ch_setup->dirtybuffer + ch_setup->minadr;
-	chan.dum_ch_max = ch_setup->dirtybuffer + ch_setup->maxadr;
-	chan.dum_ch_conf = 0x002;
-	chan.dum_ch_ctrl = 0x04;
-
-	put_channel(chan);
-
-	return 0;
-}
-
-static u32 display_open(int ch_no, int auto_update, u32 * dirty_buffer,
-			u32 * frame_buffer, u32 xpos, u32 ypos, u32 w, u32 h)
-{
-
-	struct dum_ch_setup k;
-	int ret;
-
-	/* keep width & height within display area */
-	if ((xpos + w) > DISP_MAX_X_SIZE)
-		w = DISP_MAX_X_SIZE - xpos;
-
-	if ((ypos + h) > DISP_MAX_Y_SIZE)
-		h = DISP_MAX_Y_SIZE - ypos;
-
-	/* assume 1 display only */
-	k.disp_no = 0;
-	k.xmin = xpos;
-	k.ymin = ypos;
-	k.xmax = xpos + (w - 1);
-	k.ymax = ypos + (h - 1);
-
-	/* adjust min and max values if necessary */
-	if (k.xmin > DISP_MAX_X_SIZE - 1)
-		k.xmin = DISP_MAX_X_SIZE - 1;
-	if (k.ymin > DISP_MAX_Y_SIZE - 1)
-		k.ymin = DISP_MAX_Y_SIZE - 1;
-
-	if (k.xmax > DISP_MAX_X_SIZE - 1)
-		k.xmax = DISP_MAX_X_SIZE - 1;
-	if (k.ymax > DISP_MAX_Y_SIZE - 1)
-		k.ymax = DISP_MAX_Y_SIZE - 1;
-
-	k.xmirror = 0;
-	k.ymirror = 0;
-	k.rotate = 0;
-	k.minadr = (u32) frame_buffer;
-	k.maxadr = (u32) frame_buffer + (((w - 1) << 10) | ((h << 2) - 2));
-	k.pad = PAD_1024;
-	k.dirtybuffer = (u32) dirty_buffer;
-	k.format = RGB888;
-	k.hwdirty = 0;
-	k.slave_trans = 0;
-
-	ret = dum_ch_setup(ch_no, &k);
-
-	return ret;
-}
-
-static void lcd_reset(void)
-{
-	u32 *dum_pio_base = (u32 *)IO_ADDRESS(PNX4008_PIO_BASE);
-
-	udelay(1);
-	iowrite32(BIT(19), &dum_pio_base[2]);
-	udelay(1);
-	iowrite32(BIT(19), &dum_pio_base[1]);
-	udelay(1);
-}
-
-static int dum_init(struct platform_device *pdev)
-{
-	struct clk *clk;
-
-	/* enable DUM clock */
-	clk = clk_get(&pdev->dev, "dum_ck");
-	if (IS_ERR(clk)) {
-		printk(KERN_ERR "pnx4008_dum: Unable to access DUM clock\n");
-		return PTR_ERR(clk);
-	}
-
-	clk_set_rate(clk, 1);
-	clk_put(clk);
-
-	DUM_CTRL = V_DUM_RESET;
-
-	/* set priority to "round-robin". All other params to "false" */
-	DUM_CONF = BIT(9);
-
-	/* Display 1 */
-	DUM_WTCFG1 = PNX4008_DUM_WT_CFG;
-	DUM_RTCFG1 = PNX4008_DUM_RT_CFG;
-	DUM_TCFG = PNX4008_DUM_T_CFG;
-
-	return 0;
-}
-
-static void dum_chan_init(void)
-{
-	int i = 0, ch = 0;
-	u32 *cmdptrs;
-	u32 *cmdstrings;
-
-	DUM_COM_BASE =
-		CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS;
-
-	if ((cmdptrs =
-	     (u32 *) ioremap_nocache(DUM_COM_BASE,
-				     sizeof(u32) * NR_OF_CMDSTRINGS)) == NULL)
-		return;
-
-	for (ch = 0; ch < NR_OF_CMDSTRINGS; ch++)
-		iowrite32(CMDSTRING_BASEADDR + BYTES_PER_CMDSTRING * ch,
-			  cmdptrs + ch);
-
-	for (ch = 0; ch < MAX_DUM_CHANNELS; ch++)
-		clear_channel(ch);
-
-	/* Clear the cmdstrings */
-	cmdstrings =
-	    (u32 *)ioremap_nocache(*cmdptrs,
-				   BYTES_PER_CMDSTRING * NR_OF_CMDSTRINGS);
-
-	if (!cmdstrings)
-		goto out;
-
-	for (i = 0; i < NR_OF_CMDSTRINGS * BYTES_PER_CMDSTRING / sizeof(u32);
-	     i++)
-		iowrite32(0, cmdstrings + i);
-
-	iounmap((u32 *)cmdstrings);
-
-out:
-	iounmap((u32 *)cmdptrs);
-}
-
-static void lcd_init(void)
-{
-	lcd_reset();
-
-	DUM_OUTP_FORMAT1 = 0; /* RGB666 */
-
-	udelay(1);
-	iowrite32(V_LCD_STANDBY_OFF, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_USE_9BIT_BUS, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_RISE_L, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_RISE_H, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_FALL_L, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_FALL_H, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_SYNC_ENABLE, dum_data.slave_virt_base);
-	udelay(1);
-	iowrite32(V_LCD_DISPLAY_ON, dum_data.slave_virt_base);
-	udelay(1);
-}
-
-/* Interface exported to framebuffer drivers */
-
-int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
-			     dma_addr_t *phys_addr, int *fb_length)
-{
-	int i;
-	int ret = -1;
-	for (i = 0; i < ARRAY_SIZE(fb_addr); i++)
-		if (fb_addr[i].fb_type == fb_type) {
-			*virt_addr = (void *)(dum_data.lcd_virt_start +
-					fb_addr[i].addr_offset);
-			*phys_addr =
-			    dum_data.lcd_phys_start + fb_addr[i].addr_offset;
-			*fb_length = fb_addr[i].fb_length;
-			ret = 0;
-			break;
-		}
-
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_get_fb_addresses);
-
-int pnx4008_alloc_dum_channel(int dev_id)
-{
-	int i = 0;
-
-	while ((i < MAX_DUM_CHANNELS) && (dum_data.fb_owning_channel[i] != -1))
-		i++;
-
-	if (i == MAX_DUM_CHANNELS)
-		return -ENORESOURCESLEFT;
-	else {
-		dum_data.fb_owning_channel[i] = dev_id;
-		return i;
-	}
-}
-
-EXPORT_SYMBOL(pnx4008_alloc_dum_channel);
-
-int pnx4008_free_dum_channel(int channr, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		clear_channel(channr);
-		dum_data.fb_owning_channel[channr] = -1;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_free_dum_channel);
-
-int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id)
-{
-	int i = chan_uf.channelnr;
-	int ret;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[i] != dev_id)
-		return -EFBNOTOWNER;
-	else if ((ret =
-		  display_open(chan_uf.channelnr, 0, chan_uf.dirty,
-			       chan_uf.source, chan_uf.y_offset,
-			       chan_uf.x_offset, chan_uf.height,
-			       chan_uf.width)) != 0)
-		return ret;
-	else {
-		dum_data.chan_uf_store[i].dirty = chan_uf.dirty;
-		dum_data.chan_uf_store[i].source = chan_uf.source;
-		dum_data.chan_uf_store[i].x_offset = chan_uf.x_offset;
-		dum_data.chan_uf_store[i].y_offset = chan_uf.y_offset;
-		dum_data.chan_uf_store[i].width = chan_uf.width;
-		dum_data.chan_uf_store[i].height = chan_uf.height;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_put_dum_channel_uf);
-
-int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		if (val == CONF_SYNC_ON) {
-			DUM_CH_CONF(channr) |= CONF_SYNCENABLE;
-			DUM_CH_CONF(channr) |= DUM_CHANNEL_CFG_SYNC_MASK |
-				DUM_CHANNEL_CFG_SYNC_MASK_SET;
-		} else if (val == CONF_SYNC_OFF)
-			DUM_CH_CONF(channr) &= ~CONF_SYNCENABLE;
-		else
-			return -EINVAL;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_channel_sync);
-
-int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		if (val == CONF_DIRTYDETECTION_ON)
-			DUM_CH_CONF(channr) |= CONF_DIRTYENABLE;
-		else if (val == CONF_DIRTYDETECTION_OFF)
-			DUM_CH_CONF(channr) &= ~CONF_DIRTYENABLE;
-		else
-			return -EINVAL;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_channel_dirty_detect);
-
-#if 0 /* Functions not used currently, but likely to be used in future */
-
-static int get_channel(struct dumchannel *p_chan)
-{
-	int i = p_chan->channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else {
-		p_chan->dum_ch_min = DUM_CH_MIN(i);
-		p_chan->dum_ch_max = DUM_CH_MAX(i);
-		p_chan->dum_ch_conf = DUM_CH_CONF(i);
-		p_chan->dum_ch_stat = DUM_CH_STAT(i);
-		p_chan->dum_ch_ctrl = 0;	/* WriteOnly control register */
-	}
-
-	return 0;
-}
-
-int pnx4008_get_dum_channel_uf(struct dumchannel_uf *p_chan_uf, int dev_id)
-{
-	int i = p_chan_uf->channelnr;
-
-	if (i < 0 || i > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[i] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		p_chan_uf->dirty = dum_data.chan_uf_store[i].dirty;
-		p_chan_uf->source = dum_data.chan_uf_store[i].source;
-		p_chan_uf->x_offset = dum_data.chan_uf_store[i].x_offset;
-		p_chan_uf->y_offset = dum_data.chan_uf_store[i].y_offset;
-		p_chan_uf->width = dum_data.chan_uf_store[i].width;
-		p_chan_uf->height = dum_data.chan_uf_store[i].height;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_get_dum_channel_uf);
-
-int pnx4008_get_dum_channel_config(int channr, int dev_id)
-{
-	int ret;
-	struct dumchannel chan;
-
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else {
-		chan.channelnr = channr;
-		if ((ret = get_channel(&chan)) != 0)
-			return ret;
-	}
-
-	return (chan.dum_ch_conf & DUM_CHANNEL_CFG_MASK);
-}
-
-EXPORT_SYMBOL(pnx4008_get_dum_channel_config);
-
-int pnx4008_force_update_dum_channel(int channr, int dev_id)
-{
-	if (channr < 0 || channr > MAX_DUM_CHANNELS)
-		return -EINVAL;
-
-	else if (dum_data.fb_owning_channel[channr] != dev_id)
-		return -EFBNOTOWNER;
-	else
-		DUM_CH_CTRL(channr) = CTRL_SETDIRTY;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_force_update_dum_channel);
-
-#endif
-
-int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma,
-		      struct device *dev)
-{
-	unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
-
-	if (off < info->fix.smem_len) {
-		vma->vm_pgoff += 1;
-		return dma_mmap_writecombine(dev, vma,
-				(void *)dum_data.lcd_virt_start,
-				dum_data.lcd_phys_start,
-				FB_DMA_SIZE);
-	}
-	return -EINVAL;
-}
-
-EXPORT_SYMBOL(pnx4008_sdum_mmap);
-
-int pnx4008_set_dum_exit_notification(int dev_id)
-{
-	int i;
-
-	for (i = 0; i < MAX_DUM_CHANNELS; i++)
-		if (dum_data.fb_owning_channel[i] == dev_id)
-			return -ERESOURCESNOTFREED;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(pnx4008_set_dum_exit_notification);
-
-/* Platform device driver for DUM */
-
-static int sdum_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	int retval = 0;
-	struct clk *clk;
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 0);
-		clk_put(clk);
-	} else
-		retval = PTR_ERR(clk);
-
-	/* disable BAC */
-	DUM_CTRL = V_BAC_DISABLE_IDLE;
-
-	/* LCD standby & turn off display */
-	lcd_reset();
-
-	return retval;
-}
-
-static int sdum_resume(struct platform_device *pdev)
-{
-	int retval = 0;
-	struct clk *clk;
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 1);
-		clk_put(clk);
-	} else
-		retval = PTR_ERR(clk);
-
-	/* wait for BAC disable */
-	DUM_CTRL = V_BAC_DISABLE_TRIG;
-
-	while (DUM_CTRL & BAC_ENABLED)
-		udelay(10);
-
-	/* re-init LCD */
-	lcd_init();
-
-	/* enable BAC and reset MUX */
-	DUM_CTRL = V_BAC_ENABLE;
-	udelay(1);
-	DUM_CTRL = V_MUX_RESET;
-	return 0;
-}
-
-static int __devinit sdum_probe(struct platform_device *pdev)
-{
-	int ret = 0, i = 0;
-
-	/* map frame buffer */
-	dum_data.lcd_virt_start = (u32) dma_alloc_writecombine(&pdev->dev,
-						       FB_DMA_SIZE,
-						       &dum_data.lcd_phys_start,
-						       GFP_KERNEL);
-
-	if (!dum_data.lcd_virt_start) {
-		ret = -ENOMEM;
-		goto out_3;
-	}
-
-	/* map slave registers */
-	dum_data.slave_phys_base = PNX4008_DUM_SLAVE_BASE;
-	dum_data.slave_virt_base =
-	    (u32 *) ioremap_nocache(dum_data.slave_phys_base, sizeof(u32));
-
-	if (dum_data.slave_virt_base == NULL) {
-		ret = -ENOMEM;
-		goto out_2;
-	}
-
-	/* initialize DUM and LCD display */
-	ret = dum_init(pdev);
-	if (ret)
-		goto out_1;
-
-	dum_chan_init();
-	lcd_init();
-
-	DUM_CTRL = V_BAC_ENABLE;
-	udelay(1);
-	DUM_CTRL = V_MUX_RESET;
-
-	/* set decode address and sync clock divider */
-	DUM_DECODE = dum_data.lcd_phys_start & DUM_DECODE_MASK;
-	DUM_CLK_DIV = PNX4008_DUM_CLK_DIV;
-
-	for (i = 0; i < MAX_DUM_CHANNELS; i++)
-		dum_data.fb_owning_channel[i] = -1;
-
-	/*setup wakeup interrupt */
-	start_int_set_rising_edge(SE_DISP_SYNC_INT);
-	start_int_ack(SE_DISP_SYNC_INT);
-	start_int_umask(SE_DISP_SYNC_INT);
-
-	return 0;
-
-out_1:
-	iounmap((void *)dum_data.slave_virt_base);
-out_2:
-	dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
-			(void *)dum_data.lcd_virt_start,
-			dum_data.lcd_phys_start);
-out_3:
-	return ret;
-}
-
-static int sdum_remove(struct platform_device *pdev)
-{
-	struct clk *clk;
-
-	start_int_mask(SE_DISP_SYNC_INT);
-
-	clk = clk_get(0, "dum_ck");
-	if (!IS_ERR(clk)) {
-		clk_set_rate(clk, 0);
-		clk_put(clk);
-	}
-
-	iounmap((void *)dum_data.slave_virt_base);
-
-	dma_free_writecombine(&pdev->dev, FB_DMA_SIZE,
-			(void *)dum_data.lcd_virt_start,
-			dum_data.lcd_phys_start);
-
-	return 0;
-}
-
-static struct platform_driver sdum_driver = {
-	.driver = {
-		.name = "pnx4008-sdum",
-	},
-	.probe = sdum_probe,
-	.remove = sdum_remove,
-	.suspend = sdum_suspend,
-	.resume = sdum_resume,
-};
-
-module_platform_driver(sdum_driver);
-
-MODULE_LICENSE("GPL");
--- linux-2.6.orig/drivers/video/pnx4008/sdum.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2005 Philips Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html
-*/
-
-#define MAX_DUM_CHANNELS	64
-
-#define RGB_MEM_WINDOW(x) (0x10000000 + (x)*0x00100000)
-
-#define QCIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x30000: -1)
-#define CIF_OFFSET(x)  (((x) == 0) ? 0x00000: ((x) == 1) ? 0x60000: -1)
-
-#define CTRL_SETDIRTY	 	(0x00000001)
-#define CONF_DIRTYENABLE	(0x00000020)
-#define CONF_SYNCENABLE		(0x00000004)
-
-#define DIRTY_ENABLED(conf)	((conf) & 0x0020)
-#define SYNC_ENABLED(conf) 	((conf) & 0x0004)
-
-/* Display 1 & 2 Write Timing Configuration */
-#define PNX4008_DUM_WT_CFG		0x00372000
-
-/* Display 1 & 2 Read Timing Configuration */
-#define PNX4008_DUM_RT_CFG		0x00003A47
-
-/* DUM Transit State Timing Configuration */
-#define PNX4008_DUM_T_CFG		0x1D	/* 29 HCLK cycles */
-
-/* DUM Sync count clock divider */
-#define PNX4008_DUM_CLK_DIV		0x02DD
-
-/* Memory size for framebuffer, allocated through dma_alloc_writecombine().
- * Must be PAGE aligned
- */
-#define FB_DMA_SIZE (PAGE_ALIGN(SZ_1M + PAGE_SIZE))
-
-#define OFFSET_RGBBUFFER (0xB0000)
-#define OFFSET_YUVBUFFER (0x00000)
-
-#define YUVBUFFER (lcd_video_start + OFFSET_YUVBUFFER)
-#define RGBBUFFER (lcd_video_start + OFFSET_RGBBUFFER)
-
-#define CMDSTRING_BASEADDR	(0x00C000)	/* iram */
-#define BYTES_PER_CMDSTRING	(0x80)
-#define NR_OF_CMDSTRINGS	(64)
-
-#define MAX_NR_PRESTRINGS (0x40)
-#define MAX_NR_POSTSTRINGS (0x40)
-
-/* various mask definitions */
-#define DUM_CLK_ENABLE 0x01
-#define DUM_CLK_DISABLE 0
-#define DUM_DECODE_MASK 0x1FFFFFFF
-#define DUM_CHANNEL_CFG_MASK 0x01FF
-#define DUM_CHANNEL_CFG_SYNC_MASK 0xFFFE00FF
-#define DUM_CHANNEL_CFG_SYNC_MASK_SET 0x0CA00
-
-#define SDUM_RETURNVAL_BASE (0x500)
-
-#define CONF_SYNC_OFF		(0x602)
-#define CONF_SYNC_ON		(0x603)
-
-#define CONF_DIRTYDETECTION_OFF	(0x600)
-#define CONF_DIRTYDETECTION_ON	(0x601)
-
-struct dumchannel_uf {
-	int channelnr;
-	u32 *dirty;
-	u32 *source;
-	u32 x_offset;
-	u32 y_offset;
-	u32 width;
-	u32 height;
-};
-
-enum {
-	FB_TYPE_YUV,
-	FB_TYPE_RGB
-};
-
-struct cmdstring {
-	int channelnr;
-	uint16_t prestringlen;
-	uint16_t poststringlen;
-	uint16_t format;
-	uint16_t reserved;
-	uint16_t startaddr_low;
-	uint16_t startaddr_high;
-	uint16_t pixdatlen_low;
-	uint16_t pixdatlen_high;
-	u32 precmd[MAX_NR_PRESTRINGS];
-	u32 postcmd[MAX_NR_POSTSTRINGS];
-
-};
-
-struct dumchannel {
-	int channelnr;
-	int dum_ch_min;
-	int dum_ch_max;
-	int dum_ch_conf;
-	int dum_ch_stat;
-	int dum_ch_ctrl;
-};
-
-int pnx4008_alloc_dum_channel(int dev_id);
-int pnx4008_free_dum_channel(int channr, int dev_id);
-
-int pnx4008_get_dum_channel_uf(struct dumchannel_uf *pChan_uf, int dev_id);
-int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id);
-
-int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id);
-int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id);
-
-int pnx4008_force_dum_update_channel(int channr, int dev_id);
-
-int pnx4008_get_dum_channel_config(int channr, int dev_id);
-
-int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma, struct device *dev);
-int pnx4008_set_dum_exit_notification(int dev_id);
-
-int pnx4008_get_fb_addresses(int fb_type, void **virt_addr,
-			     dma_addr_t * phys_addr, int *fb_length);
--- linux-2.6.orig/drivers/watchdog/Kconfig
+++ linux-2.6/drivers/watchdog/Kconfig
@@ -237,12 +237,12 @@ config OMAP_WATCHDOG
 	  here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
 
 config PNX4008_WATCHDOG
-	tristate "PNX4008 and LPC32XX Watchdog"
-	depends on ARCH_PNX4008 || ARCH_LPC32XX
+	tristate "LPC32XX Watchdog"
+	depends on ARCH_LPC32XX
 	select WATCHDOG_CORE
 	help
 	  Say Y here if to include support for the watchdog timer
-	  in the PNX4008 or LPC32XX processor.
+	  in the LPC32XX processor.
 	  This driver can be built as a module by choosing M. The module
 	  will be called pnx4008_wdt.
 


From jett.zhou at gmail.com  Thu Aug 23 08:26:07 2012
From: jett.zhou at gmail.com (jett zhou)
Date: Thu, 23 Aug 2012 20:26:07 +0800
Subject: [V4 3/4] power_supply: Enable battery-charger for 88pm860x
In-Reply-To: <20120823122239.GA29485@lizard>
References: <20120714081254.GD20018@lizard>
 <1343377636-16128-1-git-send-email-jtzhou@marvell.com>
 <20120823034815.GB16674@lizard> <20120823044348.GA415@lizard>
 <CACDDiy-ZzUxi4MvjELwHzYC+AxF0b0+LuOh=JdFBBgSA2ijjNw@mail.gmail.com>
 <20120823122239.GA29485@lizard>
Message-ID: <CACDDiy9WX0jF2jXA9HvVxU11XOUBD1mRHURVW_B3j0MEXJM0BQ@mail.gmail.com>

Got it. Thanks

2012/8/23 Anton Vorontsov <anton.vorontsov at linaro.org>

> On Thu, Aug 23, 2012 at 05:06:22PM +0800, jett zhou wrote:
> > Thanks for helping me to amend these patch.  I got many good
> > suggestions and learn a lot in this process:) BTW, you mean you will
> > help to amend that several minor warning with battery tree?
>
> Yup, I have these small fixups locally in my tree already, so if/once
> Samuel gives me an Ack for the mfd part, I'll merge it into battery git
> tree.
>
> Thanks,
>
> Anton.
>



-- 

----------------------------------
Best Regards
Jett Zhou
-------------- next part --------------
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From hdoyu at nvidia.com  Fri Aug 24 04:29:02 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 11:29:02 +0300
Subject: [v3 1/4] ARM: dma-mapping: atomic_pool with struct page **pages
In-Reply-To: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345796945-21115-2-git-send-email-hdoyu@nvidia.com>

struct page **pages is necessary to align with non atomic path in
__iommu_get_pages(). atomic_pool() has the intialized **pages instead
of just *page.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   17 +++++++++++++----
 1 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 601da7a..b14ee64 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -296,7 +296,7 @@ struct dma_pool {
 	unsigned long *bitmap;
 	unsigned long nr_pages;
 	void *vaddr;
-	struct page *page;
+	struct page **pages;
 };
 
 static struct dma_pool atomic_pool = {
@@ -335,12 +335,16 @@ static int __init atomic_pool_init(void)
 	unsigned long nr_pages = pool->size >> PAGE_SHIFT;
 	unsigned long *bitmap;
 	struct page *page;
+	struct page **pages;
 	void *ptr;
 	int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
+	size_t size = nr_pages * sizeof(struct page *);
 
-	bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+	size += bitmap_size;
+	bitmap = kzalloc(size, GFP_KERNEL);
 	if (!bitmap)
 		goto no_bitmap;
+	pages = (void *)bitmap + bitmap_size;
 
 	if (IS_ENABLED(CONFIG_CMA))
 		ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
@@ -348,9 +352,14 @@ static int __init atomic_pool_init(void)
 		ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
 					   &page, NULL);
 	if (ptr) {
+		int i;
+
+		for (i = 0; i < nr_pages; i++)
+			pages[i] = page + i;
+
 		spin_lock_init(&pool->lock);
 		pool->vaddr = ptr;
-		pool->page = page;
+		pool->pages = pages;
 		pool->bitmap = bitmap;
 		pool->nr_pages = nr_pages;
 		pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
@@ -481,7 +490,7 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	if (pageno < pool->nr_pages) {
 		bitmap_set(pool->bitmap, pageno, count);
 		ptr = pool->vaddr + PAGE_SIZE * pageno;
-		*ret_page = pool->page + pageno;
+		*ret_page = pool->pages[pageno];
 	} else {
 		pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
 			    "Please increase it with coherent_pool= kernel parameter!\n",
-- 
1.7.5.4



From hdoyu at nvidia.com  Fri Aug 24 04:29:04 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 11:29:04 +0300
Subject: [v3 3/4] ARM: dma-mapping: Introduce __atomic_get_pages() for
 __iommu_get_pages()
In-Reply-To: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345796945-21115-4-git-send-email-hdoyu@nvidia.com>

Support atomic allocation in __iommu_get_pages().

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 508fde1..58a852b 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -501,6 +501,15 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
+static struct page **__atomic_get_pages(void *addr)
+{
+	struct dma_pool *pool = &atomic_pool;
+	struct page **pages = pool->pages;
+	int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
+
+	return pages + offs;
+}
+
 static bool __in_atomic_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
@@ -1184,6 +1193,9 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
 {
 	struct vm_struct *area;
 
+	if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
+		return __atomic_get_pages(cpu_addr);
+
 	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
 		return cpu_addr;
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Fri Aug 24 04:29:03 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 11:29:03 +0300
Subject: [v3 2/4] ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
In-Reply-To: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345796945-21115-3-git-send-email-hdoyu@nvidia.com>

Check the given range("start", "size") is included in "atomic_pool" or not.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   25 +++++++++++++++++++------
 1 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index b14ee64..508fde1 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -501,19 +501,32 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
+static bool __in_atomic_pool(void *start, size_t size)
+{
+	struct dma_pool *pool = &atomic_pool;
+	void *end = start + size;
+	void *pool_start = pool->vaddr;
+	void *pool_end = pool->vaddr + pool->size;
+
+	if (start < pool_start || start > pool_end)
+		return false;
+
+	if (end > pool_end) {
+		WARN(1, "freeing wrong coherent size from pool\n");
+		return false;
+	}
+
+	return true;
+}
+
 static int __free_from_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
 	unsigned long pageno, count;
 	unsigned long flags;
 
-	if (start < pool->vaddr || start > pool->vaddr + pool->size)
-		return 0;
-
-	if (start + size > pool->vaddr + pool->size) {
-		WARN(1, "freeing wrong coherent size from pool\n");
+	if (!__in_atomic_pool(start, size))
 		return 0;
-	}
 
 	pageno = (start - pool->vaddr) >> PAGE_SHIFT;
 	count = size >> PAGE_SHIFT;
-- 
1.7.5.4



From hdoyu at nvidia.com  Fri Aug 24 04:29:05 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Fri, 24 Aug 2012 11:29:05 +0300
Subject: [v3 4/4] ARM: dma-mapping: IOMMU allocates pages from atomic_pool
 with GFP_ATOMIC
In-Reply-To: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1345796945-21115-5-git-send-email-hdoyu@nvidia.com>

Make use of the same atomic pool as DMA does, and skip a kernel page
mapping which can involve sleep'able operations at allocating a kernel
page table.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 58a852b..3ce152a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1205,6 +1205,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
 	return NULL;
 }
 
+static void *__iommu_alloc_atomic(struct device *dev, size_t size,
+				  dma_addr_t *handle)
+{
+	struct page *page;
+	void *addr;
+
+	addr = __alloc_from_pool(size, &page);
+	if (!addr)
+		return NULL;
+
+	*handle = __iommu_create_mapping(dev, &page, size);
+	if (*handle == DMA_ERROR_CODE)
+		goto err_mapping;
+
+	return addr;
+
+err_mapping:
+	__free_from_pool(addr, size);
+	return NULL;
+}
+
+static void __iommu_free_atomic(struct device *dev, struct page **pages,
+				dma_addr_t handle, size_t size)
+{
+	__iommu_remove_mapping(dev, handle, size);
+	__free_from_pool(page_address(pages[0]), size);
+}
+
 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	    dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
 {
@@ -1215,6 +1243,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	*handle = DMA_ERROR_CODE;
 	size = PAGE_ALIGN(size);
 
+	if (gfp & GFP_ATOMIC)
+		return __iommu_alloc_atomic(dev, size, handle);
+
 	pages = __iommu_alloc_buffer(dev, size, gfp);
 	if (!pages)
 		return NULL;
@@ -1281,6 +1312,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
 		return;
 	}
 
+	if (__in_atomic_pool(cpu_addr, size)) {
+		__iommu_free_atomic(dev, pages, handle, size);
+		return;
+	}
+
 	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
 		unmap_kernel_range((unsigned long)cpu_addr, size);
 		vunmap(cpu_addr);
-- 
1.7.5.4



From stigge at antcom.de  Fri Aug 24 09:24:20 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 24 Aug 2012 15:24:20 +0200
Subject: [GIT PULL] ARM: mach-pnx4008: Remove architecture
In-Reply-To: <1345724548-18130-1-git-send-email-stigge@antcom.de>
References: <1345724548-18130-1-git-send-email-stigge@antcom.de>
Message-ID: <50378084.3080102@antcom.de>

Hi,

On 23/08/12 14:22, Roland Stigge wrote:
> This patch removes the ARM architecture mach-pnx4008. No direct support or user
> feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
> maintainers.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

The patch was a bit too big for the mailing list - sorry.

Now re-proposing via pull request, below.

Thanks in advance,

Roland


The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:

  Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)

are available in the git repository at:

  git://git.antcom.de/linux-2.6.git pnx4008-removal

for you to fetch changes up to 5b54d019ca93850099299527753d23a5ff57c2e6:

  ARM: mach-pnx4008: Remove architecture (2012-08-24 15:12:21 +0200)

----------------------------------------------------------------
Roland Stigge (1):
      ARM: mach-pnx4008: Remove architecture

 arch/arm/Kconfig                                  |    8 -
 arch/arm/Makefile                                 |    1 -
 arch/arm/configs/pnx4008_defconfig                |  472 ---------
 arch/arm/mach-pnx4008/Makefile                    |   12 -
 arch/arm/mach-pnx4008/Makefile.boot               |    4 -
 arch/arm/mach-pnx4008/clock.c                     | 1001 -------------------
 arch/arm/mach-pnx4008/clock.h                     |   43 -
 arch/arm/mach-pnx4008/core.c                      |  290 ------
 arch/arm/mach-pnx4008/dma.c                       | 1105 ---------------------
 arch/arm/mach-pnx4008/gpio.c                      |  328 ------
 arch/arm/mach-pnx4008/i2c.c                       |   86 --
 arch/arm/mach-pnx4008/include/mach/clock.h        |   62 --
 arch/arm/mach-pnx4008/include/mach/debug-macro.S  |   21 -
 arch/arm/mach-pnx4008/include/mach/dma.h          |  160 ---
 arch/arm/mach-pnx4008/include/mach/entry-macro.S  |  116 ---
 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h |  241 -----
 arch/arm/mach-pnx4008/include/mach/hardware.h     |   32 -
 arch/arm/mach-pnx4008/include/mach/irq.h          |   42 -
 arch/arm/mach-pnx4008/include/mach/irqs.h         |  215 ----
 arch/arm/mach-pnx4008/include/mach/param.h        |   21 -
 arch/arm/mach-pnx4008/include/mach/platform.h     |   69 --
 arch/arm/mach-pnx4008/include/mach/pm.h           |   33 -
 arch/arm/mach-pnx4008/include/mach/timex.h        |   19 -
 arch/arm/mach-pnx4008/include/mach/uncompress.h   |   46 -
 arch/arm/mach-pnx4008/irq.c                       |  121 ---
 arch/arm/mach-pnx4008/pm.c                        |  153 ---
 arch/arm/mach-pnx4008/serial.c                    |   67 --
 arch/arm/mach-pnx4008/sleep.S                     |  195 ----
 arch/arm/mach-pnx4008/time.c                      |  134 ---
 arch/arm/mach-pnx4008/time.h                      |   70 --
 arch/arm/tools/mach-types                         |    1 -
 drivers/i2c/busses/Kconfig                        |    2 +-
 drivers/usb/Kconfig                               |    1 -
 drivers/usb/host/Kconfig                          |    2 +-
 drivers/usb/host/ohci-hcd.c                       |    2 +-
 drivers/usb/host/ohci-nxp.c                       |   84 +-
 drivers/video/Kconfig                             |   15 -
 drivers/video/Makefile                            |    2 -
 drivers/video/pnx4008/Makefile                    |    7 -
 drivers/video/pnx4008/dum.h                       |  211 ----
 drivers/video/pnx4008/fbcommon.h                  |   43 -
 drivers/video/pnx4008/pnxrgbfb.c                  |  198 ----
 drivers/video/pnx4008/sdum.c                      |  861 ----------------
 drivers/video/pnx4008/sdum.h                      |  136 ---
 drivers/watchdog/Kconfig                          |    6 +-
 45 files changed, 7 insertions(+), 6731 deletions(-)
 delete mode 100644 arch/arm/configs/pnx4008_defconfig
 delete mode 100644 arch/arm/mach-pnx4008/Makefile
 delete mode 100644 arch/arm/mach-pnx4008/Makefile.boot
 delete mode 100644 arch/arm/mach-pnx4008/clock.c
 delete mode 100644 arch/arm/mach-pnx4008/clock.h
 delete mode 100644 arch/arm/mach-pnx4008/core.c
 delete mode 100644 arch/arm/mach-pnx4008/dma.c
 delete mode 100644 arch/arm/mach-pnx4008/gpio.c
 delete mode 100644 arch/arm/mach-pnx4008/i2c.c
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/clock.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/debug-macro.S
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/dma.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/irq.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/param.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/platform.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/pm.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/timex.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-pnx4008/irq.c
 delete mode 100644 arch/arm/mach-pnx4008/pm.c
 delete mode 100644 arch/arm/mach-pnx4008/serial.c
 delete mode 100644 arch/arm/mach-pnx4008/sleep.S
 delete mode 100644 arch/arm/mach-pnx4008/time.c
 delete mode 100644 arch/arm/mach-pnx4008/time.h
 delete mode 100644 drivers/video/pnx4008/Makefile
 delete mode 100644 drivers/video/pnx4008/dum.h
 delete mode 100644 drivers/video/pnx4008/fbcommon.h
 delete mode 100644 drivers/video/pnx4008/pnxrgbfb.c
 delete mode 100644 drivers/video/pnx4008/sdum.c
 delete mode 100644 drivers/video/pnx4008/sdum.h


From stigge at antcom.de  Sun Aug 26 10:23:20 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 26 Aug 2012 16:23:20 +0200
Subject: [PATCH v2] ARM: mach-pnx4008: Remove architecture
Message-ID: <1345991001-32462-1-git-send-email-stigge@antcom.de>

This patch removes the ARM architecture mach-pnx4008. No direct support or user
feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
maintainers.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
Changes since v1:
* Removed removal of pnx4008 video driver, separated out into patch for video
  subsystem

Applies to v3.6-rc3

 arch/arm/Kconfig                                  |    8 
 arch/arm/Makefile                                 |    1 
 arch/arm/configs/pnx4008_defconfig                |  472 ---------
 arch/arm/mach-pnx4008/Makefile                    |   12 
 arch/arm/mach-pnx4008/Makefile.boot               |    4 
 arch/arm/mach-pnx4008/clock.c                     | 1001 -------------------
 arch/arm/mach-pnx4008/clock.h                     |   43 
 arch/arm/mach-pnx4008/core.c                      |  290 -----
 arch/arm/mach-pnx4008/dma.c                       | 1105 ----------------------
 arch/arm/mach-pnx4008/gpio.c                      |  328 ------
 arch/arm/mach-pnx4008/i2c.c                       |   86 -
 arch/arm/mach-pnx4008/include/mach/clock.h        |   62 -
 arch/arm/mach-pnx4008/include/mach/debug-macro.S  |   21 
 arch/arm/mach-pnx4008/include/mach/dma.h          |  160 ---
 arch/arm/mach-pnx4008/include/mach/entry-macro.S  |  116 --
 arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h |  241 ----
 arch/arm/mach-pnx4008/include/mach/hardware.h     |   32 
 arch/arm/mach-pnx4008/include/mach/irq.h          |   42 
 arch/arm/mach-pnx4008/include/mach/irqs.h         |  215 ----
 arch/arm/mach-pnx4008/include/mach/param.h        |   21 
 arch/arm/mach-pnx4008/include/mach/platform.h     |   69 -
 arch/arm/mach-pnx4008/include/mach/pm.h           |   33 
 arch/arm/mach-pnx4008/include/mach/timex.h        |   19 
 arch/arm/mach-pnx4008/include/mach/uncompress.h   |   46 
 arch/arm/mach-pnx4008/irq.c                       |  121 --
 arch/arm/mach-pnx4008/pm.c                        |  153 ---
 arch/arm/mach-pnx4008/serial.c                    |   67 -
 arch/arm/mach-pnx4008/sleep.S                     |  195 ---
 arch/arm/mach-pnx4008/time.c                      |  134 --
 arch/arm/mach-pnx4008/time.h                      |   70 -
 arch/arm/tools/mach-types                         |    1 
 drivers/i2c/busses/Kconfig                        |    2 
 drivers/usb/Kconfig                               |    1 
 drivers/usb/host/Kconfig                          |    2 
 drivers/usb/host/ohci-hcd.c                       |    2 
 drivers/usb/host/ohci-nxp.c                       |   84 -
 drivers/watchdog/Kconfig                          |    6 
 37 files changed, 7 insertions(+), 5258 deletions(-)

--- linux-2.6.orig/arch/arm/Kconfig
+++ linux-2.6/arch/arm/Kconfig
@@ -709,14 +709,6 @@ config ARCH_PICOXCELL
 	  family of Femtocell devices.  The picoxcell support requires device tree
 	  for all boards.
 
-config ARCH_PNX4008
-	bool "Philips Nexperia PNX4008 Mobile"
-	select CPU_ARM926T
-	select CLKDEV_LOOKUP
-	select ARCH_USES_GETTIMEOFFSET
-	help
-	  This enables support for Philips PNX4008 mobile platform.
-
 config ARCH_PXA
 	bool "PXA2xx/PXA3xx-based"
 	depends on MMU
--- linux-2.6.orig/arch/arm/Makefile
+++ linux-2.6/arch/arm/Makefile
@@ -167,7 +167,6 @@ machine-$(CONFIG_ARCH_OMAP1)		:= omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)	:= omap2
 machine-$(CONFIG_ARCH_ORION5X)		:= orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)	:= picoxcell
-machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
--- linux-2.6.orig/arch/arm/configs/pnx4008_defconfig
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
--- linux-2.6.orig/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y			:= core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m			:=
-obj-n			:=
-obj-			:=
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y		+= 0x80008000
-params_phys-y		:= 0x80000100
-initrd_phys-y		:= 0x80800000
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- * Generic clock management functions are partially based on:
- *  linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-
-static inline void clock_lock(void)
-{
-	local_irq_disable();
-}
-
-static inline void clock_unlock(void)
-{
-	local_irq_enable();
-}
-
-static void propagate_rate(struct clk *clk)
-{
-	struct clk *tmp_clk;
-
-	tmp_clk = clk;
-	while (tmp_clk->propagate_next) {
-		tmp_clk = tmp_clk->propagate_next;
-		local_set_rate(tmp_clk, tmp_clk->user_rate);
-	}
-}
-
-static void clk_reg_disable(struct clk *clk)
-{
-	if (clk->enable_reg)
-		__raw_writel(__raw_readl(clk->enable_reg) &
-			     ~(1 << clk->enable_shift), clk->enable_reg);
-}
-
-static int clk_reg_enable(struct clk *clk)
-{
-	if (clk->enable_reg)
-		__raw_writel(__raw_readl(clk->enable_reg) |
-			     (1 << clk->enable_shift), clk->enable_reg);
-	return 0;
-}
-
-static inline void clk_reg_disable1(struct clk *clk)
-{
-	if (clk->enable_reg1)
-		__raw_writel(__raw_readl(clk->enable_reg1) &
-			     ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static inline void clk_reg_enable1(struct clk *clk)
-{
-	if (clk->enable_reg1)
-		__raw_writel(__raw_readl(clk->enable_reg1) |
-			     (1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
-	int i;
-	i = 0;
-	while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;	/*wait for PLL to lock */
-
-	if (!(__raw_readl(clk->scale_reg) & 1)) {
-		printk(KERN_ERR
-		       "%s ERROR: failed to lock, scale reg data: %x\n",
-		       clk->name, __raw_readl(clk->scale_reg));
-		return -1;
-	}
-	return 0;
-}
-
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
-	int i;
-	int ret;
-	u32 tmp_reg;
-
-	ret = 0;
-
-	if (!clk->rate)
-		clk_reg_enable1(clk);
-
-	tmp_reg = __raw_readl(clk->parent_switch_reg);
-	/*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
-	if (!(tmp_reg & 1)) {
-		tmp_reg |= (1 << 1);	/* Trigger switch to 13'MHz (dirty) clock */
-		__raw_writel(tmp_reg, clk->parent_switch_reg);
-		i = 0;
-		while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;	/*wait for 13'MHz selection status */
-
-		if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
-			printk(KERN_ERR
-			       "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
-			       clk->name, __raw_readl(clk->parent_switch_reg));
-			ret = -1;
-		}
-	}
-
-	if (!clk->rate)
-		clk_reg_disable1(clk);
-
-	return ret;
-}
-
-static int switch_to_clean_13mhz(struct clk *clk)
-{
-	int i;
-	int ret;
-	u32 tmp_reg;
-
-	ret = 0;
-
-	if (!clk->rate)
-		clk_reg_enable1(clk);
-
-	tmp_reg = __raw_readl(clk->parent_switch_reg);
-	/*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
-	if (tmp_reg & 1) {
-		tmp_reg &= ~(1 << 1);	/* Trigger switch to 13MHz (clean) clock */
-		__raw_writel(tmp_reg, clk->parent_switch_reg);
-		i = 0;
-		while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;	/*wait for 13MHz selection status */
-
-		if (__raw_readl(clk->parent_switch_reg) & 1) {
-			printk(KERN_ERR
-			       "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
-			       clk->name, __raw_readl(clk->parent_switch_reg));
-			ret = -1;
-		}
-	}
-
-	if (!clk->rate)
-		clk_reg_disable1(clk);
-
-	return ret;
-}
-
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
-	int ret = -EINVAL;
-
-	if (parent == &ck_13MHz)
-		ret = switch_to_clean_13mhz(clk);
-	else if (parent == &ck_pll1)
-		ret = switch_to_dirty_13mhz(clk);
-
-	return ret;
-}
-
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp_reg, tmp_m, tmp_2p, i;
-	u32 parent_rate;
-	int ret = -EINVAL;
-
-	parent_rate = clk->parent->rate;
-
-	if (!parent_rate)
-		goto out;
-
-	/* set direct run for ARM or disable output for others  */
-	clk_reg_disable(clk);
-
-	/* disable source input as well (ignored for ARM) */
-	clk_reg_disable1(clk);
-
-	tmp_reg = __raw_readl(clk->scale_reg);
-	tmp_reg &= ~0x1ffff;	/*clear all settings, power down */
-	__raw_writel(tmp_reg, clk->scale_reg);
-
-	rate -= rate % parent_rate;	/*round down the input */
-
-	if (rate > PLL160_MAX_FCCO)
-		rate = PLL160_MAX_FCCO;
-
-	if (!rate) {
-		clk->rate = 0;
-		ret = 0;
-		goto out;
-	}
-
-	clk_reg_enable1(clk);
-	tmp_reg = __raw_readl(clk->scale_reg);
-
-	if (rate == parent_rate) {
-		/*enter direct bypass mode */
-		tmp_reg |= ((1 << 14) | (1 << 15));
-		__raw_writel(tmp_reg, clk->scale_reg);
-		clk->rate = parent_rate;
-		clk_reg_enable(clk);
-		ret = 0;
-		goto out;
-	}
-
-	i = 0;
-	for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
-		if (rate * tmp_2p >= PLL160_MIN_FCCO)
-			break;
-		i++;
-	}
-
-	if (tmp_2p > 1)
-		tmp_reg |= ((i - 1) << 11);
-	else
-		tmp_reg |= (1 << 14);	/*direct mode, no divide */
-
-	tmp_m = rate * tmp_2p;
-	tmp_m /= parent_rate;
-
-	tmp_reg |= (tmp_m - 1) << 1;	/*calculate M */
-	tmp_reg |= (1 << 16);	/*power up PLL */
-	__raw_writel(tmp_reg, clk->scale_reg);
-
-	if (clk_wait_for_pll_lock(clk) < 0) {
-		clk_reg_disable(clk);
-		clk_reg_disable1(clk);
-
-		tmp_reg = __raw_readl(clk->scale_reg);
-		tmp_reg &= ~0x1ffff;	/*clear all settings, power down */
-		__raw_writel(tmp_reg, clk->scale_reg);
-		clk->rate = 0;
-		ret = -EFAULT;
-		goto out;
-	}
-
-	clk->rate = (tmp_m * parent_rate) / tmp_2p;
-
-	if (clk->flags & RATE_PROPAGATES)
-		propagate_rate(clk);
-
-	clk_reg_enable(clk);
-	ret = 0;
-
-out:
-	return ret;
-}
-
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp;
-
-	tmp = __raw_readl(clk->scale_reg);
-	tmp &= ~(0x1f << 2);
-	tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
-	__raw_writel(tmp, clk->scale_reg);
-	clk->rate = rate;
-	return 0;
-}
-
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
-	u32 tmp;
-	tmp = __raw_readl(clk->scale_reg);
-	tmp = tmp & ~0x3;
-	switch (rate) {
-	case 1:
-		break;
-	case 2:
-		tmp |= 1;
-		break;
-	case 4:
-		tmp |= 2;
-		break;
-	}
-
-	__raw_writel(tmp, clk->scale_reg);
-	clk->rate = rate;
-	return 0;
-}
-
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
-	switch (rate) {
-	case 1:
-	case 4:
-		return rate;
-	}
-	return 2;
-}
-
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
-	return CLK_RATE_13MHZ;
-}
-
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_enable(clk);
-		clk->rate = 1;
-	} else {
-		clk_reg_disable(clk);
-		clk->rate = 0;
-	}
-	return 0;
-}
-
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		clk->rate = 1;
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-	}
-	return 0;
-}
-
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? 1 : 0);
-}
-
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
-	if (rate > CLK_RATE_208MHZ)
-		rate = CLK_RATE_208MHZ;
-	if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
-		rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
-	return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
-	if (rate > CLK_RATE_208MHZ)
-		rate = CLK_RATE_208MHZ;
-	return (rate - rate % CLK_RATE_13MHZ);
-}
-
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? CLK_RATE_48MHZ : 0);
-}
-
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
-	return (rate ? CLK_RATE_13MHZ : 0);
-}
-
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		udelay(500);
-		clk->rate = CLK_RATE_13MHZ;
-		ck_1MHz.rate = CLK_RATE_1MHZ;
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-		ck_1MHz.rate = 0;
-	}
-	return 0;
-}
-
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
-	if (rate) {
-		clk_reg_disable(clk);	/*enable bit is inverted */
-		if (!clk_wait_for_pll_lock(clk)) {
-			clk->rate = CLK_RATE_13MHZ;
-		} else {
-			clk_reg_enable(clk);
-			clk->rate = 0;
-		}
-
-	} else {
-		clk_reg_enable(clk);
-		clk->rate = 0;
-	}
-#endif
-	return 0;
-}
-
-/* Clock sources */
-
-static struct clk osc_13MHz = {
-	.name = "osc_13MHz",
-	.flags = FIXED_RATE,
-	.rate = CLK_RATE_13MHZ,
-};
-
-static struct clk ck_13MHz = {
-	.name = "ck_13MHz",
-	.parent = &osc_13MHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &ck_13MHz_round_rate,
-	.set_rate = &ck_13MHz_set_rate,
-	.enable_reg = OSC13CTRL_REG,
-	.enable_shift = 0,
-	.rate = CLK_RATE_13MHZ,
-};
-
-static struct clk osc_32KHz = {
-	.name = "osc_32KHz",
-	.flags = FIXED_RATE,
-	.rate = CLK_RATE_32KHZ,
-};
-
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
-	.name = "ck_1MHz",
-	.flags = FIXED_RATE | PARENT_SET_RATE,
-	.parent = &ck_13MHz,
-};
-
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
-	.name = "ck_pll1",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &ck_13MHz_round_rate,
-	.set_rate = &pll1_set_rate,
-	.enable_reg = PLLCTRL_REG,
-	.enable_shift = 1,
-	.scale_reg = PLLCTRL_REG,
-	.rate = CLK_RATE_13MHZ,
-};
-
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
-	.name = "ck_pll4",
-	.parent = &ck_pll1,
-	.flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
-	.propagate_next = &per_ck,
-	.round_rate = &pll4_round_rate,
-	.set_rate = &pll160_set_rate,
-	.rate = CLK_RATE_208MHZ,
-	.scale_reg = HCLKPLLCTRL_REG,
-	.enable_reg = PWRCTRL_REG,
-	.enable_shift = 2,
-	.parent_switch_reg = SYSCLKCTRL_REG,
-	.set_parent = &set_13MHz_parent,
-};
-
-/* USB PLL */
-static struct clk ck_pll5 = {
-	.name = "ck_pll5",
-	.parent = &ck_1MHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &pll5_round_rate,
-	.set_rate = &pll160_set_rate,
-	.scale_reg = USBCTRL_REG,
-	.enable_reg = USBCTRL_REG,
-	.enable_shift = 18,
-	.enable_reg1 = USBCTRL_REG,
-	.enable_shift1 = 17,
-};
-
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
-	.name = "ck_pll3",
-	.parent = &ck_pll1,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &pll3_round_rate,
-	.set_rate = &pll160_set_rate,
-	.scale_reg = DSPPLLCTRL_REG,
-	.enable_reg = DSPCLKCTRL_REG,
-	.enable_shift = 3,
-	.enable_reg1 = DSPCLKCTRL_REG,
-	.enable_shift1 = 2,
-	.parent_switch_reg = DSPCLKCTRL_REG,
-	.set_parent = &set_13MHz_parent,
-};
-
-static struct clk hclk_ck = {
-	.name = "hclk_ck",
-	.parent = &ck_pll4,
-	.flags = PARENT_SET_RATE,
-	.set_rate = &hclk_set_rate,
-	.round_rate = &hclk_round_rate,
-	.scale_reg = HCLKDIVCTRL_REG,
-	.rate = 2,
-	.user_rate = 2,
-};
-
-static struct clk per_ck = {
-	.name = "per_ck",
-	.parent = &ck_pll4,
-	.flags = FIXED_RATE,
-	.propagate_next = &hclk_ck,
-	.set_rate = &per_clk_set_rate,
-	.round_rate = &per_clk_round_rate,
-	.scale_reg = HCLKDIVCTRL_REG,
-	.rate = CLK_RATE_13MHZ,
-	.user_rate = CLK_RATE_13MHZ,
-};
-
-static struct clk m2hclk_ck = {
-	.name = "m2hclk_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_inv_set_rate,
-	.rate = 1,
-	.enable_shift = 6,
-	.enable_reg = PWRCTRL_REG,
-};
-
-static struct clk vfp9_ck = {
-	.name = "vfp9_ck",
-	.parent = &ck_pll4,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 4,
-	.enable_reg = VFP9CLKCTRL_REG,
-};
-
-static struct clk keyscan_ck = {
-	.name = "keyscan_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = KEYCLKCTRL_REG,
-};
-
-static struct clk touch_ck = {
-	.name = "touch_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = TSCLKCTRL_REG,
-};
-
-static struct clk pwm1_ck = {
-	.name = "pwm1_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk pwm2_ck = {
-	.name = "pwm2_ck",
-	.parent = &osc_32KHz,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 2,
-	.enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk jpeg_ck = {
-	.name = "jpeg_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = JPEGCLKCTRL_REG,
-};
-
-static struct clk ms_ck = {
-	.name = "ms_ck",
-	.parent = &ck_pll4,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 5,
-	.enable_reg = MSCTRL_REG,
-};
-
-static struct clk dum_ck = {
-	.name = "dum_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = DUMCLKCTRL_REG,
-};
-
-static struct clk flash_ck = {
-	.name = "flash_ck",
-	.parent = &hclk_ck,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 1,	/* Only MLC clock supported */
-	.enable_reg = FLASHCLKCTRL_REG,
-};
-
-static struct clk i2c0_ck = {
-	.name = "i2c0_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 0,
-	.enable_reg = I2CCLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk i2c1_ck = {
-	.name = "i2c1_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 1,
-	.enable_reg = I2CCLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk i2c2_ck = {
-	.name = "i2c2_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION | FIXED_RATE,
-	.enable_shift = 2,
-	.enable_reg = USB_OTG_CLKCTRL_REG,
-	.rate = 13000000,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-static struct clk spi0_ck = {
-	.name = "spi0_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = SPICTRL_REG,
-};
-
-static struct clk spi1_ck = {
-	.name = "spi1_ck",
-	.parent = &hclk_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 4,
-	.enable_reg = SPICTRL_REG,
-};
-
-static struct clk dma_ck = {
-	.name = "dma_ck",
-	.parent = &hclk_ck,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 0,
-	.enable_reg = DMACLKCTRL_REG,
-};
-
-static struct clk uart3_ck = {
-	.name = "uart3_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 0,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart4_ck = {
-	.name = "uart4_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 1,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart5_ck = {
-	.name = "uart5_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.rate = 1,
-	.enable_shift = 2,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart6_ck = {
-	.name = "uart6_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.round_rate = &on_off_round_rate,
-	.set_rate = &on_off_set_rate,
-	.enable_shift = 3,
-	.enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk wdt_ck = {
-	.name = "wdt_ck",
-	.parent = &per_ck,
-	.flags = NEEDS_INITIALIZATION,
-	.enable_shift = 0,
-	.enable_reg = TIMCLKCTRL_REG,
-	.enable = clk_reg_enable,
-	.disable = clk_reg_disable,
-};
-
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
-	&ck_13MHz,
-	&ck_pll1,
-	&ck_pll4,
-	&ck_pll5,
-	&ck_pll3,
-	&vfp9_ck,
-	&m2hclk_ck,
-	&hclk_ck,
-	&dma_ck,
-	&flash_ck,
-	&dum_ck,
-	&keyscan_ck,
-	&pwm1_ck,
-	&pwm2_ck,
-	&jpeg_ck,
-	&ms_ck,
-	&touch_ck,
-	&i2c0_ck,
-	&i2c1_ck,
-	&i2c2_ck,
-	&spi0_ck,
-	&spi1_ck,
-	&uart3_ck,
-	&uart4_ck,
-	&uart5_ck,
-	&uart6_ck,
-	&wdt_ck,
-};
-
-static struct clk_lookup onchip_clkreg[] = {
-	{ .clk = &ck_13MHz,	.con_id = "ck_13MHz"	},
-	{ .clk = &ck_pll1,	.con_id = "ck_pll1"	},
-	{ .clk = &ck_pll4,	.con_id = "ck_pll4"	},
-	{ .clk = &ck_pll5,	.con_id = "ck_pll5"	},
-	{ .clk = &ck_pll3,	.con_id = "ck_pll3"	},
-	{ .clk = &vfp9_ck,	.con_id = "vfp9_ck"	},
-	{ .clk = &m2hclk_ck,	.con_id = "m2hclk_ck"	},
-	{ .clk = &hclk_ck,	.con_id = "hclk_ck"	},
-	{ .clk = &dma_ck,	.con_id = "dma_ck"	},
-	{ .clk = &flash_ck,	.con_id = "flash_ck"	},
-	{ .clk = &dum_ck,	.con_id = "dum_ck"	},
-	{ .clk = &keyscan_ck,	.con_id = "keyscan_ck"	},
-	{ .clk = &pwm1_ck,	.con_id = "pwm1_ck"	},
-	{ .clk = &pwm2_ck,	.con_id = "pwm2_ck"	},
-	{ .clk = &jpeg_ck,	.con_id = "jpeg_ck"	},
-	{ .clk = &ms_ck,	.con_id = "ms_ck"	},
-	{ .clk = &touch_ck,	.con_id = "touch_ck"	},
-	{ .clk = &i2c0_ck,	.dev_id = "pnx-i2c.0"	},
-	{ .clk = &i2c1_ck,	.dev_id = "pnx-i2c.1"	},
-	{ .clk = &i2c2_ck,	.dev_id = "pnx-i2c.2"	},
-	{ .clk = &spi0_ck,	.con_id = "spi0_ck"	},
-	{ .clk = &spi1_ck,	.con_id = "spi1_ck"	},
-	{ .clk = &uart3_ck,	.con_id = "uart3_ck"	},
-	{ .clk = &uart4_ck,	.con_id = "uart4_ck"	},
-	{ .clk = &uart5_ck,	.con_id = "uart5_ck"	},
-	{ .clk = &uart6_ck,	.con_id = "uart6_ck"	},
-	{ .clk = &wdt_ck,	.dev_id = "pnx4008-watchdog" },
-};
-
-static void local_clk_disable(struct clk *clk)
-{
-	if (WARN_ON(clk->usecount == 0))
-		return;
-
-	if (!(--clk->usecount)) {
-		if (clk->disable)
-			clk->disable(clk);
-		else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-			clk->set_rate(clk, 0);
-		if (clk->parent)
-			local_clk_disable(clk->parent);
-	}
-}
-
-static int local_clk_enable(struct clk *clk)
-{
-	int ret = 0;
-
-	if (clk->usecount == 0) {
-		if (clk->parent) {
-			ret = local_clk_enable(clk->parent);
-			if (ret != 0)
-				goto out;
-		}
-
-		if (clk->enable)
-			ret = clk->enable(clk);
-		else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-			    && clk->user_rate)
-			ret = clk->set_rate(clk, clk->user_rate);
-
-		if (ret != 0 && clk->parent) {
-			local_clk_disable(clk->parent);
-			goto out;
-		}
-
-		clk->usecount++;
-	}
-out:
-	return ret;
-}
-
-static int local_set_rate(struct clk *clk, u32 rate)
-{
-	int ret = -EINVAL;
-	if (clk->set_rate) {
-
-		if (clk->user_rate == clk->rate && clk->parent->rate) {
-			/* if clock enabled or rate not set */
-			clk->user_rate = clk->round_rate(clk, rate);
-			ret = clk->set_rate(clk, clk->user_rate);
-		} else
-			clk->user_rate = clk->round_rate(clk, rate);
-		ret = 0;
-	}
-	return ret;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	int ret = -EINVAL;
-
-	if (clk->flags & FIXED_RATE)
-		goto out;
-
-	clock_lock();
-	if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-
-		clk->user_rate = clk->round_rate(clk, rate);
-		/* parent clock needs to be refreshed
-		   for the setting to take effect */
-	} else {
-		ret = local_set_rate(clk, rate);
-	}
-	ret = 0;
-	clock_unlock();
-
-out:
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long ret;
-	clock_lock();
-	ret = clk->rate;
-	clock_unlock();
-	return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_enable(struct clk *clk)
-{
-	int ret;
-
-	clock_lock();
-	ret = local_clk_enable(clk);
-	clock_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-	clock_lock();
-	local_clk_disable(clk);
-	clock_unlock();
-}
-
-EXPORT_SYMBOL(clk_disable);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	long ret;
-	clock_lock();
-	if (clk->round_rate)
-		ret = clk->round_rate(clk, rate);
-	else
-		ret = clk->rate;
-	clock_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	int ret = -ENODEV;
-	if (!clk->set_parent)
-		goto out;
-
-	clock_lock();
-	ret = clk->set_parent(clk, parent);
-	if (!ret)
-		clk->parent = parent;
-	clock_unlock();
-
-out:
-	return ret;
-}
-
-EXPORT_SYMBOL(clk_set_parent);
-
-static int __init clk_init(void)
-{
-	struct clk **clkp;
-
-	/* Disable autoclocking, as it doesn't seem to work */
-	__raw_writel(0xff, AUTOCLK_CTRL);
-
-	for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-	     clkp++) {
-		struct clk *clk = *clkp;
-		if (clk->flags & NEEDS_INITIALIZATION) {
-			if (clk->set_rate) {
-				clk->user_rate = clk->rate;
-				local_set_rate(clk, clk->user_rate);
-				if (clk->set_parent)
-					clk->set_parent(clk, clk->parent);
-			}
-			if (clk->enable && clk->usecount)
-				clk->enable(clk);
-			if (clk->disable && !clk->usecount)
-				clk->disable(clk);
-		}
-		pr_debug("%s: clock %s, rate %ld\n",
-			__func__, clk->name, clk->rate);
-	}
-
-	local_clk_enable(&ck_pll4);
-
-	/* if ck_13MHz is not used, disable it. */
-	if (ck_13MHz.usecount == 0)
-		local_clk_disable(&ck_13MHz);
-
-	/* Disable autoclocking */
-	__raw_writeb(0xff, AUTOCLK_CTRL);
-
-	clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-
-	return 0;
-}
-
-arch_initcall(clk_init);
--- linux-2.6.orig/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source at mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-
-struct clk {
-	const char *name;
-	struct clk *parent;
-	struct clk *propagate_next;
-	u32 rate;
-	u32 user_rate;
-	s8 usecount;
-	u32 flags;
-	u32 scale_reg;
-	u8 enable_shift;
-	u32 enable_reg;
-	u8 enable_shift1;
-	u32 enable_reg1;
-	u32 parent_switch_reg;
-	u32(*round_rate) (struct clk *, u32);
-	int (*set_rate) (struct clk *, u32);
-	int (*set_parent) (struct clk * clk, struct clk * parent);
-	int (*enable)(struct clk *);
-	void (*disable)(struct clk *);
-};
-
-/* Flags */
-#define RATE_PROPAGATES      (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE      (1<<2)
-#define FIXED_RATE           (1<<3)
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-
-struct resource spipnx_0_resources[] = {
-	{
-		.start = PNX4008_SPI1_BASE,
-		.end = PNX4008_SPI1_BASE + SZ_4K,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = PER_SPI1_REC_XMIT,
-		.flags = IORESOURCE_DMA,
-	}, {
-		.start = SPI1_INT,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.flags = 0,
-	},
-};
-
-struct resource spipnx_1_resources[] = {
-	{
-		.start = PNX4008_SPI2_BASE,
-		.end = PNX4008_SPI2_BASE + SZ_4K,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = PER_SPI2_REC_XMIT,
-		.flags = IORESOURCE_DMA,
-	}, {
-		.start = SPI2_INT,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.flags = 0,
-	}
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-	{
-		.modalias	= "m25p80",
-		.max_speed_hz	= 1000000,
-		.bus_num	= 1,
-		.chip_select	= 0,
-	},
-};
-
-static struct platform_device spipnx_1 = {
-	.name = "spipnx",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(spipnx_0_resources),
-	.resource = spipnx_0_resources,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-		},
-};
-
-static struct platform_device spipnx_2 = {
-	.name = "spipnx",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(spipnx_1_resources),
-	.resource = spipnx_1_resources,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-		},
-};
-
-static struct plat_serial8250_port platform_serial_ports[] = {
-	{
-		.membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
-		.mapbase = (unsigned long)PNX4008_UART5_BASE,
-		.irq = IIR5_INT,
-		.uartclk = PNX4008_UART_CLK,
-		.regshift = 2,
-		.iotype = UPIO_MEM,
-		.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-	},
-	{
-		.membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
-		.mapbase = (unsigned long)PNX4008_UART3_BASE,
-		.irq = IIR3_INT,
-		.uartclk = PNX4008_UART_CLK,
-		.regshift = 2,
-		.iotype = UPIO_MEM,
-		.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-	 },
-	{}
-};
-
-static struct platform_device serial_device = {
-	.name = "serial8250",
-	.id = PLAT8250_DEV_PLATFORM,
-	.dev = {
-		.platform_data = &platform_serial_ports,
-	},
-};
-
-static struct platform_device nand_flash_device = {
-	.name = "pnx4008-flash",
-	.id = -1,
-	.dev = {
-		.coherent_dma_mask = 0xFFFFFFFF,
-	},
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-
-static struct resource ohci_resources[] = {
-	{
-		.start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
-		.end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = USB_HOST_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device ohci_device = {
-	.name = "pnx4008-usb-ohci",
-	.id = -1,
-	.dev = {
-		.dma_mask = &ohci_dmamask,
-		.coherent_dma_mask = 0xffffffff,
-		},
-	.num_resources = ARRAY_SIZE(ohci_resources),
-	.resource = ohci_resources,
-};
-
-static struct platform_device sdum_device = {
-	.name = "pnx4008-sdum",
-	.id = 0,
-	.dev = {
-		.coherent_dma_mask = 0xffffffff,
-	},
-};
-
-static struct platform_device rgbfb_device = {
-	.name = "pnx4008-rgbfb",
-	.id = 0,
-	.dev = {
-		.coherent_dma_mask = 0xffffffff,
-	}
-};
-
-struct resource watchdog_resources[] = {
-	{
-		.start = PNX4008_WDOG_BASE,
-		.end = PNX4008_WDOG_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device watchdog_device = {
-	.name = "pnx4008-watchdog",
-	.id = -1,
-	.num_resources = ARRAY_SIZE(watchdog_resources),
-	.resource = watchdog_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&spipnx_1,
-	&spipnx_2,
-	&serial_device,
-	&ohci_device,
-	&nand_flash_device,
-	&sdum_device,
-	&rgbfb_device,
-	&watchdog_device,
-};
-
-
-extern void pnx4008_uart_init(void);
-
-static void __init pnx4008_init(void)
-{
-	/*disable all START interrupt sources,
-	   and clear all START interrupt flags */
-	__raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
-	__raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-	/* Switch on the UART clocks */
-	pnx4008_uart_init();
-}
-
-static struct map_desc pnx4008_io_desc[] __initdata = {
-	{
-		.virtual 	= IO_ADDRESS(PNX4008_IRAM_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_IRAM_BASE),
-		.length		= SZ_64K,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
-		.length		= SZ_1M - SZ_128K,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
-		.length		= SZ_128K * 3,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
-		.length		= SZ_1M,
-		.type 		= MT_DEVICE,
-	}, {
-		.virtual 	= IO_ADDRESS(PNX4008_AHB2FAB_BASE),
-		.pfn 		= __phys_to_pfn(PNX4008_AHB2FAB_BASE),
-		.length		= SZ_1M,
-		.type 		= MT_DEVICE,
-	},
-};
-
-void __init pnx4008_map_io(void)
-{
-	iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-
-static void pnx4008_restart(char mode, const char *cmd)
-{
-	soft_restart(0);
-}
-
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-
-void __init pnx4008_init_late(void)
-{
-	pnx4008_pm_init();
-}
-
-extern struct sys_timer pnx4008_timer;
-
-MACHINE_START(PNX4008, "Philips PNX4008")
-	/* Maintainer: MontaVista Software Inc. */
-	.atag_offset		= 0x100,
-	.map_io 		= pnx4008_map_io,
-	.init_irq 		= pnx4008_init_irq,
-	.init_machine 		= pnx4008_init,
-	.init_late		= pnx4008_init_late,
-	.timer 			= &pnx4008_timer,
-	.restart		= pnx4008_restart,
-MACHINE_END
--- linux-2.6.orig/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/dma.c
- *
- *  PNX4008 DMA registration and IRQ dispatching
- *
- *  Author:	Vitaly Wool
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  Based on the code from Nicolas Pitre
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-
-static struct dma_channel {
-	char *name;
-	void (*irq_handler) (int, int, void *);
-	void *data;
-	struct pnx4008_dma_ll *ll;
-	u32 ll_dma;
-	void *target_addr;
-	int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-
-static struct ll_pool {
-	void *vaddr;
-	void *cur;
-	dma_addr_t dma_addr;
-	int count;
-} ll_pool;
-
-static DEFINE_SPINLOCK(ll_lock);
-
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
-	struct pnx4008_dma_ll *ll = NULL;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ll_lock, flags);
-	if (ll_pool.count > 4) { /* can give one more */
-		ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
-		*ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
-		*(void **)ll_pool.cur = **(void ***)ll_pool.cur;
-		memset(ll, 0, sizeof(*ll));
-		ll_pool.count--;
-	}
-	spin_unlock_irqrestore(&ll_lock, flags);
-
-	return ll;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
-	unsigned long flags;
-
-	if (ll) {
-		if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
-			printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
-			BUG();
-		}
-
-		if (ll->flags & DMA_BUFFER_ALLOCATED)
-			ll->free(ll->alloc_data);
-
-		spin_lock_irqsave(&ll_lock, flags);
-		*(long *)ll = *(long *)ll_pool.cur;
-		*(long *)ll_pool.cur = (long)ll;
-		ll_pool.count++;
-		spin_unlock_irqrestore(&ll_lock, flags);
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
-	struct pnx4008_dma_ll *ptr;
-	u32 dma;
-
-	while (ll) {
-		dma = ll->next_dma;
-		ptr = ll->next;
-		pnx4008_free_ll_entry(ll, ll_dma);
-
-		ll_dma = dma;
-		ll = ptr;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-
-static int dma_channels_requested = 0;
-
-static inline void dma_increment_usage(void)
-{
-	if (!dma_channels_requested++) {
-		struct clk *clk = clk_get(0, "dma_ck");
-		if (!IS_ERR(clk)) {
-			clk_set_rate(clk, 1);
-			clk_put(clk);
-		}
-		pnx4008_config_dma(-1, -1, 1);
-	}
-}
-static inline void dma_decrement_usage(void)
-{
-	if (!--dma_channels_requested) {
-		struct clk *clk = clk_get(0, "dma_ck");
-		if (!IS_ERR(clk)) {
-			clk_set_rate(clk, 0);
-			clk_put(clk);
-		}
-		pnx4008_config_dma(-1, -1, 0);
-
-	}
-}
-
-static DEFINE_SPINLOCK(dma_lock);
-
-static inline void pnx4008_dma_lock(void)
-{
-	spin_lock_irq(&dma_lock);
-}
-
-static inline void pnx4008_dma_unlock(void)
-{
-	spin_unlock_irq(&dma_lock);
-}
-
-#define VALID_CHANNEL(c)	(((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-
-int pnx4008_request_channel(char *name, int ch,
-			    void (*irq_handler) (int, int, void *), void *data)
-{
-	int i, found = 0;
-
-	/* basic sanity checks */
-	if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-
-	/* try grabbing a DMA channel with the requested priority */
-	for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-		if (!dma_channels[i].name && (ch == -1 || ch == i)) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		dma_increment_usage();
-		dma_channels[i].name = name;
-		dma_channels[i].irq_handler = irq_handler;
-		dma_channels[i].data = data;
-		dma_channels[i].ll = NULL;
-		dma_channels[i].ll_dma = 0;
-	} else {
-		printk(KERN_WARNING "No more available DMA channels for %s\n",
-		       name);
-		i = -ENODEV;
-	}
-
-	pnx4008_dma_unlock();
-	return i;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-
-void pnx4008_free_channel(int ch)
-{
-	if (!dma_channels[ch].name) {
-		printk(KERN_CRIT
-		       "%s: trying to free channel %d which is already freed\n",
-		       __func__, ch);
-		return;
-	}
-
-	pnx4008_dma_lock();
-	pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
-	dma_channels[ch].ll = NULL;
-	dma_decrement_usage();
-
-	dma_channels[ch].name = NULL;
-	pnx4008_dma_unlock();
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
-	unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-
-	switch (ahb_m1_be) {
-	case 0:
-		dma_cfg &= ~(1 << 1);
-		break;
-	case 1:
-		dma_cfg |= (1 << 1);
-		break;
-	default:
-		break;
-	}
-
-	switch (ahb_m2_be) {
-	case 0:
-		dma_cfg &= ~(1 << 2);
-		break;
-	case 1:
-		dma_cfg |= (1 << 2);
-		break;
-	default:
-		break;
-	}
-
-	switch (enable) {
-	case 0:
-		dma_cfg &= ~(1 << 0);
-		break;
-	case 1:
-		dma_cfg |= (1 << 0);
-		break;
-	default:
-		break;
-	}
-
-	pnx4008_dma_lock();
-	__raw_writel(dma_cfg, DMAC_CONFIG);
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
-			     unsigned long *ctrl)
-{
-	int i = 0, dbsize, sbsize, err = 0;
-
-	if (!ctrl || !ch_ctrl) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	*ctrl = 0;
-
-	switch (ch_ctrl->tc_mask) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 31);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-
-	switch (ch_ctrl->cacheable) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 30);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->bufferable) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 29);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->priv_mode) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 28);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->di) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 27);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->si) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 26);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->dest_ahb1) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 25);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->src_ahb1) {
-	case 0:
-		break;
-	case 1:
-		*ctrl |= (1 << 24);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->dwidth) {
-	case WIDTH_BYTE:
-		*ctrl &= ~(7 << 21);
-		break;
-	case WIDTH_HWORD:
-		*ctrl &= ~(7 << 21);
-		*ctrl |= (1 << 21);
-		break;
-	case WIDTH_WORD:
-		*ctrl &= ~(7 << 21);
-		*ctrl |= (2 << 21);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_ctrl->swidth) {
-	case WIDTH_BYTE:
-		*ctrl &= ~(7 << 18);
-		break;
-	case WIDTH_HWORD:
-		*ctrl &= ~(7 << 18);
-		*ctrl |= (1 << 18);
-		break;
-	case WIDTH_WORD:
-		*ctrl &= ~(7 << 18);
-		*ctrl |= (2 << 18);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	dbsize = ch_ctrl->dbsize;
-	while (!(dbsize & 1)) {
-		i++;
-		dbsize >>= 1;
-	}
-	if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
-		err = -EINVAL;
-		goto out;
-	} else if (i > 1)
-		i--;
-	*ctrl &= ~(7 << 15);
-	*ctrl |= (i << 15);
-
-	sbsize = ch_ctrl->sbsize;
-	while (!(sbsize & 1)) {
-		i++;
-		sbsize >>= 1;
-	}
-	if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
-		err = -EINVAL;
-		goto out;
-	} else if (i > 1)
-		i--;
-	*ctrl &= ~(7 << 12);
-	*ctrl |= (i << 12);
-
-	if (ch_ctrl->tr_size > 0x7ff) {
-		err = -E2BIG;
-		goto out;
-	}
-	*ctrl &= ~0x7ff;
-	*ctrl |= ch_ctrl->tr_size & 0x7ff;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-
-int pnx4008_dma_parse_control(unsigned long ctrl,
-			      struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
-	int err = 0;
-
-	if (!ch_ctrl) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	ch_ctrl->tr_size = ctrl & 0x7ff;
-	ctrl >>= 12;
-
-	ch_ctrl->sbsize = 1 << (ctrl & 7);
-	if (ch_ctrl->sbsize > 1)
-		ch_ctrl->sbsize <<= 1;
-	ctrl >>= 3;
-
-	ch_ctrl->dbsize = 1 << (ctrl & 7);
-	if (ch_ctrl->dbsize > 1)
-		ch_ctrl->dbsize <<= 1;
-	ctrl >>= 3;
-
-	switch (ctrl & 7) {
-	case 0:
-		ch_ctrl->swidth = WIDTH_BYTE;
-		break;
-	case 1:
-		ch_ctrl->swidth = WIDTH_HWORD;
-		break;
-	case 2:
-		ch_ctrl->swidth = WIDTH_WORD;
-		break;
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	ctrl >>= 3;
-
-	switch (ctrl & 7) {
-	case 0:
-		ch_ctrl->dwidth = WIDTH_BYTE;
-		break;
-	case 1:
-		ch_ctrl->dwidth = WIDTH_HWORD;
-		break;
-	case 2:
-		ch_ctrl->dwidth = WIDTH_WORD;
-		break;
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	ctrl >>= 3;
-
-	ch_ctrl->src_ahb1 = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->dest_ahb1 = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->si = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->di = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->priv_mode = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->bufferable = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->cacheable = ctrl & 1;
-	ctrl >>= 1;
-
-	ch_ctrl->tc_mask = ctrl & 1;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
-			    unsigned long *cfg)
-{
-	int err = 0;
-
-	if (!cfg || !ch_cfg) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	*cfg = 0;
-
-	switch (ch_cfg->halt) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 18);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->active) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 17);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->lock) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 16);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->itc) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 15);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->ie) {
-	case 0:
-		break;
-	case 1:
-		*cfg |= (1 << 14);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	switch (ch_cfg->flow_cntrl) {
-	case FC_MEM2MEM_DMA:
-		*cfg &= ~(7 << 11);
-		break;
-	case FC_MEM2PER_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (1 << 11);
-		break;
-	case FC_PER2MEM_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (2 << 11);
-		break;
-	case FC_PER2PER_DMA:
-		*cfg &= ~(7 << 11);
-		*cfg |= (3 << 11);
-		break;
-	case FC_PER2PER_DPER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (4 << 11);
-		break;
-	case FC_MEM2PER_PER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (5 << 11);
-		break;
-	case FC_PER2MEM_PER:
-		*cfg &= ~(7 << 11);
-		*cfg |= (6 << 11);
-		break;
-	case FC_PER2PER_SPER:
-		*cfg |= (7 << 11);
-		break;
-
-	default:
-		err = -EINVAL;
-		goto out;
-	}
-	*cfg &= ~(0x1f << 6);
-	*cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-
-	*cfg &= ~(0x1f << 1);
-	*cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-
-int pnx4008_dma_parse_config(unsigned long cfg,
-			     struct pnx4008_dma_ch_config * ch_cfg)
-{
-	int err = 0;
-
-	if (!ch_cfg) {
-		err = -EINVAL;
-		goto out;
-	}
-
-	cfg >>= 1;
-
-	ch_cfg->src_per = cfg & 0x1f;
-	cfg >>= 5;
-
-	ch_cfg->dest_per = cfg & 0x1f;
-	cfg >>= 5;
-
-	switch (cfg & 7) {
-	case 0:
-		ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
-		break;
-	case 1:
-		ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
-		break;
-	case 2:
-		ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
-		break;
-	case 3:
-		ch_cfg->flow_cntrl = FC_PER2PER_DMA;
-		break;
-	case 4:
-		ch_cfg->flow_cntrl = FC_PER2PER_DPER;
-		break;
-	case 5:
-		ch_cfg->flow_cntrl = FC_MEM2PER_PER;
-		break;
-	case 6:
-		ch_cfg->flow_cntrl = FC_PER2MEM_PER;
-		break;
-	case 7:
-		ch_cfg->flow_cntrl = FC_PER2PER_SPER;
-	}
-	cfg >>= 3;
-
-	ch_cfg->ie = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->itc = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->lock = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->active = cfg & 1;
-	cfg >>= 1;
-
-	ch_cfg->halt = cfg & 1;
-
-out:
-	return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
-				  struct pnx4008_dma_ch_ctrl * ctrl)
-{
-	int new_len = ctrl->tr_size, num_entries = 0;
-	int old_len = new_len;
-	int src_width, dest_width, count = 1;
-
-	switch (ctrl->swidth) {
-	case WIDTH_BYTE:
-		src_width = 1;
-		break;
-	case WIDTH_HWORD:
-		src_width = 2;
-		break;
-	case WIDTH_WORD:
-		src_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	switch (ctrl->dwidth) {
-	case WIDTH_BYTE:
-		dest_width = 1;
-		break;
-	case WIDTH_HWORD:
-		dest_width = 2;
-		break;
-	case WIDTH_WORD:
-		dest_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	while (new_len > 0x7FF) {
-		num_entries++;
-		new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-	}
-	if (num_entries != 0) {
-		struct pnx4008_dma_ll *ll = NULL;
-		config->ch_ctrl &= ~0x7ff;
-		config->ch_ctrl |= new_len;
-		if (!config->is_ll) {
-			config->is_ll = 1;
-			while (num_entries) {
-				if (!ll) {
-					config->ll =
-					    pnx4008_alloc_ll_entry(&config->
-								   ll_dma);
-					ll = config->ll;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    config->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = config->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    config->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = config->dest_addr;
-				ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-		} else {
-			struct pnx4008_dma_ll *ll_old = config->ll;
-			unsigned long ll_dma_old = config->ll_dma;
-			while (num_entries) {
-				if (!ll) {
-					config->ll =
-					    pnx4008_alloc_ll_entry(&config->
-								   ll_dma);
-					ll = config->ll;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    config->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = config->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    config->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = config->dest_addr;
-				ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-			ll->next_dma = ll_dma_old;
-			ll->next = ll_old;
-		}
-		/* adjust last length/tc */
-		ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
-		ll->ch_ctrl |= old_len - new_len * (count - 1);
-		config->ch_ctrl &= 0x7fffffff;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
-				struct pnx4008_dma_ch_ctrl * ctrl)
-{
-	int new_len = ctrl->tr_size, num_entries = 0;
-	int old_len = new_len;
-	int src_width, dest_width, count = 1;
-
-	switch (ctrl->swidth) {
-	case WIDTH_BYTE:
-		src_width = 1;
-		break;
-	case WIDTH_HWORD:
-		src_width = 2;
-		break;
-	case WIDTH_WORD:
-		src_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	switch (ctrl->dwidth) {
-	case WIDTH_BYTE:
-		dest_width = 1;
-		break;
-	case WIDTH_HWORD:
-		dest_width = 2;
-		break;
-	case WIDTH_WORD:
-		dest_width = 4;
-		break;
-	default:
-		return;
-	}
-
-	while (new_len > 0x7FF) {
-		num_entries++;
-		new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-	}
-	if (num_entries != 0) {
-		struct pnx4008_dma_ll *ll = NULL;
-		cur_ll->ch_ctrl &= ~0x7ff;
-		cur_ll->ch_ctrl |= new_len;
-		if (!cur_ll->next) {
-			while (num_entries) {
-				if (!ll) {
-					cur_ll->next =
-					    pnx4008_alloc_ll_entry(&cur_ll->
-								   next_dma);
-					ll = cur_ll->next;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    cur_ll->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = cur_ll->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    cur_ll->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = cur_ll->dest_addr;
-				ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-		} else {
-			struct pnx4008_dma_ll *ll_old = cur_ll->next;
-			unsigned long ll_dma_old = cur_ll->next_dma;
-			while (num_entries) {
-				if (!ll) {
-					cur_ll->next =
-					    pnx4008_alloc_ll_entry(&cur_ll->
-								   next_dma);
-					ll = cur_ll->next;
-				} else {
-					ll->next =
-					    pnx4008_alloc_ll_entry(&ll->
-								   next_dma);
-					ll = ll->next;
-				}
-
-				if (ctrl->si)
-					ll->src_addr =
-					    cur_ll->src_addr +
-					    src_width * new_len * count;
-				else
-					ll->src_addr = cur_ll->src_addr;
-				if (ctrl->di)
-					ll->dest_addr =
-					    cur_ll->dest_addr +
-					    dest_width * new_len * count;
-				else
-					ll->dest_addr = cur_ll->dest_addr;
-				ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-				ll->next_dma = 0;
-				ll->next = NULL;
-				num_entries--;
-				count++;
-			}
-
-			ll->next_dma = ll_dma_old;
-			ll->next = ll_old;
-		}
-		/* adjust last length/tc */
-		ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
-		ll->ch_ctrl |= old_len - new_len * (count - 1);
-		cur_ll->ch_ctrl &= 0x7fffffff;
-	}
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	__raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
-	__raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-
-	if (config->is_ll)
-		__raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
-	else
-		__raw_writel(0, DMAC_Cx_LLI(ch));
-
-	__raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
-	__raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-
-	config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
-	config->is_ll = config->ll_dma ? 1 : 0;
-
-	config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
-	config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-
-int pnx4008_dma_ch_enable(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	ch_cfg |= 1;
-	__raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-
-int pnx4008_dma_ch_disable(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	ch_cfg &= ~1;
-	__raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-
-int pnx4008_dma_ch_enabled(int ch)
-{
-	unsigned long ch_cfg;
-
-	if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-		return -EINVAL;
-
-	pnx4008_dma_lock();
-	ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-	pnx4008_dma_unlock();
-
-	return ch_cfg & 1;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i;
-	unsigned long dint = __raw_readl(DMAC_INT_STAT);
-	unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
-	unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
-	unsigned long i_bit;
-
-	for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-		i_bit = 1 << i;
-		if (dint & i_bit) {
-			struct dma_channel *channel = &dma_channels[i];
-
-			if (channel->name && channel->irq_handler) {
-				int cause = 0;
-
-				if (eint & i_bit)
-					cause |= DMA_ERR_INT;
-				if (tcint & i_bit)
-					cause |= DMA_TC_INT;
-				channel->irq_handler(i, cause, channel->data);
-			} else {
-				/*
-				 * IRQ for an unregistered DMA channel
-				 */
-				printk(KERN_WARNING
-				       "spurious IRQ for DMA channel %d\n", i);
-			}
-			if (tcint & i_bit)
-				__raw_writel(i_bit, DMAC_INT_TC_CLEAR);
-			if (eint & i_bit)
-				__raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
-		}
-	}
-	return IRQ_HANDLED;
-}
-
-static int __init pnx4008_dma_init(void)
-{
-	int ret, i;
-
-	ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-	if (ret) {
-		printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-		goto out;
-	}
-
-	ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
-	ll_pool.cur = ll_pool.vaddr =
-	    dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
-			       &ll_pool.dma_addr, GFP_KERNEL);
-
-	if (!ll_pool.vaddr) {
-		ret = -ENOMEM;
-		free_irq(DMA_INT, NULL);
-		goto out;
-	}
-
-	for (i = 0; i < ll_pool.count - 1; i++) {
-		void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
-		*addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
-	}
-	*(long *)(ll_pool.vaddr +
-		  (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
-	    (long)ll_pool.vaddr;
-
-	__raw_writel(1, DMAC_CONFIG);
-
-out:
-	return ret;
-}
-arch_initcall(pnx4008_dma_init);
--- linux-2.6.orig/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-
-/* register definitions */
-#define PIO_VA_BASE	IO_ADDRESS(PNX4008_PIO_BASE)
-
-#define PIO_INP_STATE	(0x00U)
-#define PIO_OUTP_SET	(0x04U)
-#define PIO_OUTP_CLR	(0x08U)
-#define PIO_OUTP_STATE	(0x0CU)
-#define PIO_DRV_SET	(0x10U)
-#define PIO_DRV_CLR	(0x14U)
-#define PIO_DRV_STATE	(0x18U)
-#define PIO_SDINP_STATE	(0x1CU)
-#define PIO_SDOUTP_SET	(0x20U)
-#define PIO_SDOUTP_CLR	(0x24U)
-#define PIO_MUX_SET	(0x28U)
-#define PIO_MUX_CLR	(0x2CU)
-#define PIO_MUX_STATE	(0x30U)
-
-static inline void gpio_lock(void)
-{
-	local_irq_disable();
-}
-
-static inline void gpio_unlock(void)
-{
-	local_irq_enable();
-}
-
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
-	u32 bit, val;
-	int ret = -EFAULT;
-
-	if (gpio < 0)
-		goto out;
-
-	bit = GPIO_BIT(gpio);
-	if (bit) {
-		val = __raw_readl(PIO_VA_BASE + reg);
-		ret = (val & bit) ? 1 : 0;
-	}
-out:
-	return ret;
-}
-
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
-	u32 bit, val;
-	int ret = -EFAULT;
-
-	if (gpio < 0)
-		goto out;
-
-	bit = GPIO_BIT(gpio);
-	if (bit) {
-		val = __raw_readl(PIO_VA_BASE + reg);
-		val |= bit;
-		__raw_writel(val, PIO_VA_BASE + reg);
-		ret = 0;
-	}
-out:
-	return ret;
-}
-
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX	0
-#define OUTP_INDEX	1
-#define GPIO_INDEX	2
-#define MUX_INDEX	3
-
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, 10, 11, 12, 13, 14, 24, -1
-};
-
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, 0, 1, 4, 5, -1
-};
-
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
-	-1, -1, -1, 6, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1,
-	-1, -1, -1, -1, -1, 2, -1, -1,
-	-1, -1, -1, -1, -1, -1, -1, -1
-};
-
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
-	unsigned long bit = GPIO_BIT(pin);
-	int ret = -EBUSY;	/* Already in use */
-
-	gpio_lock();
-
-	if (GPIO_ISBID(pin)) {
-		if (access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] |= bit;
-
-	} else if (GPIO_ISRAM(pin)) {
-		if (access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] |= bit;
-
-	} else if (GPIO_ISMUX(pin)) {
-		if (access_map[MUX_INDEX] & bit)
-			goto out;
-		access_map[MUX_INDEX] |= bit;
-
-	} else if (GPIO_ISOUT(pin)) {
-		if (access_map[OUTP_INDEX] & bit)
-			goto out;
-		access_map[OUTP_INDEX] |= bit;
-
-	} else if (GPIO_ISIN(pin)) {
-		if (access_map[INP_INDEX] & bit)
-			goto out;
-		access_map[INP_INDEX] |= bit;
-	} else
-		goto out;
-	ret = 0;
-
-out:
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
-	unsigned long bit = GPIO_BIT(pin);
-	int ret = -EFAULT;	/* Not registered */
-
-	gpio_lock();
-
-	if (GPIO_ISBID(pin)) {
-		if (~access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] &= ~bit;
-	} else if (GPIO_ISRAM(pin)) {
-		if (~access_map[GPIO_INDEX] & bit)
-			goto out;
-		access_map[GPIO_INDEX] &= ~bit;
-	} else if (GPIO_ISMUX(pin)) {
-		if (~access_map[MUX_INDEX] & bit)
-			goto out;
-		access_map[MUX_INDEX] &= ~bit;
-	} else if (GPIO_ISOUT(pin)) {
-		if (~access_map[OUTP_INDEX] & bit)
-			goto out;
-		access_map[OUTP_INDEX] &= ~bit;
-	} else if (GPIO_ISIN(pin)) {
-		if (~access_map[INP_INDEX] & bit)
-			goto out;
-		access_map[INP_INDEX] &= ~bit;
-	} else
-		goto out;
-	ret = 0;
-
-out:
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
-	unsigned long ret = -EFAULT;
-	int gpio = GPIO_BIT_MASK(pin);
-	gpio_lock();
-	if (GPIO_ISOUT(pin)) {
-		ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-	} else if (GPIO_ISRAM(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
-			ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
-		}
-	} else if (GPIO_ISBID(pin)) {
-		ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-		if (ret > 0)
-			ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-		else if (ret == 0)
-			ret =
-			    gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
-	} else if (GPIO_ISIN(pin)) {
-		ret = gpio_read_bit(PIO_INP_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISOUT(pin)) {
-		printk( "writing '%x' to '%x'\n",
-				gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
-		ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
-	} else if (GPIO_ISRAM(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-			ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
-					   PIO_SDOUTP_CLR, gpio);
-	} else if (GPIO_ISBID(pin)) {
-		if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-			ret = gpio_set_bit(output ? PIO_OUTP_SET :
-					   PIO_OUTP_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-		ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-		ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-
-/* Value = 1 : Set pin to muxed function  */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin)) {
-		ret =
-		    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-				 gpio_to_mux_map[gpio]);
-	} else if (GPIO_ISOUT(pin)) {
-		ret =
-		    gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-				 outp_to_mux_map[gpio]);
-	} else if (GPIO_ISMUX(pin)) {
-		ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
-	int gpio = GPIO_BIT_MASK(pin);
-	int ret = -EFAULT;
-
-	gpio_lock();
-	if (GPIO_ISBID(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
-	} else if (GPIO_ISOUT(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
-	} else if (GPIO_ISMUX(pin)) {
-		ret = gpio_read_bit(PIO_MUX_STATE, gpio);
-	}
-	gpio_unlock();
-	return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
--- linux-2.6.orig/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool at gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
-static struct resource i2c0_resources[] = {
-	{
-		.start = PNX4008_I2C1_BASE,
-		.end = PNX4008_I2C1_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_1_INT,
-		.end = I2C_1_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c1_resources[] = {
-	{
-		.start = PNX4008_I2C2_BASE,
-		.end = PNX4008_I2C2_BASE + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = I2C_2_INT,
-		.end = I2C_2_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource i2c2_resources[] = {
-	{
-		.start = PNX4008_USB_CONFIG_BASE + 0x300,
-		.end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = USB_I2C_INT,
-		.end = USB_I2C_INT,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device i2c0_device = {
-	.name = "pnx-i2c.0",
-	.id = 0,
-	.resource = i2c0_resources,
-	.num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
-	.name = "pnx-i2c.1",
-	.id = 1,
-	.resource = i2c1_resources,
-	.num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
-	.name = "pnx-i2c.2",
-	.id = 2,
-	.resource = i2c2_resources,
-	.num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
-	&i2c0_device,
-	&i2c1_device,
-	&i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-}
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE		IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG		(PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG		(PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG		(PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG		(PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG		(PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG		(PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG		(PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG	(PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG		(PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL		(PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG		(PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG		(PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG		(PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG		(PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG		(PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG	(PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG		(PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG		(PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG		(PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL		(PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG		(PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE	IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG		(AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG	(AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG		IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-		.macro	addruart, rp, rv, tmp
-		mov	\rp, #0x00090000
-		add	\rv, \rp, #0xf4000000	@ virtual
-		add	\rp, \rp, #0x40000000	@ physical
-		.endm
-
-#define UART_SHIFT	2
-#include <asm/hardware/debug-8250.S>
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:	Vitaly Wool
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_CHANNELS	8
-
-#define DMAC_BASE		IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT		(DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT	(DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR	(DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT	(DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR	(DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ		(DMAC_BASE + 0x0024)
-#define DMAC_CONFIG		(DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)	(DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)	(DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)		(DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)	(DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)	(DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
-	WIDTH_BYTE = 0,
-	WIDTH_HWORD,
-	WIDTH_WORD
-};
-
-enum {
-	FC_MEM2MEM_DMA,
-	FC_MEM2PER_DMA,
-	FC_PER2MEM_DMA,
-	FC_PER2PER_DMA,
-	FC_PER2PER_DPER,
-	FC_MEM2PER_PER,
-	FC_PER2MEM_PER,
-	FC_PER2PER_SPER
-};
-
-enum {
-	DMA_INT_UNKNOWN = 0,
-	DMA_ERR_INT = 1,
-	DMA_TC_INT = 2,
-};
-
-enum {
-	DMA_BUFFER_ALLOCATED = 1,
-	DMA_HAS_LL = 2,
-};
-
-enum {
-	PER_CAM_DMA_1 = 0,
-	PER_NDF_FLASH = 1,
-	PER_MBX_SLAVE_FIFO = 2,
-	PER_SPI2_REC_XMIT = 3,
-	PER_MS_SD_RX_XMIT = 4,
-	PER_HS_UART_1_XMIT = 5,
-	PER_HS_UART_1_RX = 6,
-	PER_HS_UART_2_XMIT = 7,
-	PER_HS_UART_2_RX = 8,
-	PER_HS_UART_7_XMIT = 9,
-	PER_HS_UART_7_RX = 10,
-	PER_SPI1_REC_XMIT = 11,
-	PER_MLC_NDF_SREC = 12,
-	PER_CAM_DMA_2 = 13,
-	PER_PRNG_INFIFO = 14,
-	PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
-	int tc_mask;
-	int cacheable;
-	int bufferable;
-	int priv_mode;
-	int di;
-	int si;
-	int dest_ahb1;
-	int src_ahb1;
-	int dwidth;
-	int swidth;
-	int dbsize;
-	int sbsize;
-	int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
-	int halt;
-	int active;
-	int lock;
-	int itc;
-	int ie;
-	int flow_cntrl;
-	int dest_per;
-	int src_per;
-};
-
-struct pnx4008_dma_ll {
-	unsigned long src_addr;
-	unsigned long dest_addr;
-	u32 next_dma;
-	unsigned long ch_ctrl;
-	struct pnx4008_dma_ll *next;
-	int flags;
-	void *alloc_data;
-	int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
-	int is_ll;
-	unsigned long src_addr;
-	unsigned long dest_addr;
-	unsigned long ch_ctrl;
-	unsigned long ch_cfg;
-	struct pnx4008_dma_ll *ll;
-	u32 ll_dma;
-	int flags;
-	void *alloc_data;
-	int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
-				   void (*)(int, int, void *),
-				   void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-				    unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-				     struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-				   unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-				    struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-					 struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-				       struct pnx4008_dma_ch_ctrl *);
-
-#endif				/* _ASM_ARCH_DMA_H */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool at ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK			0x00
-#define INTRC_RAW_STAT			0x04
-#define INTRC_STAT			0x08
-#define INTRC_POLAR			0x0C
-#define INTRC_ACT_TYPE			0x10
-#define INTRC_TYPE			0x14
-
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-		ldr	\base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-		ldr	\irqstat, [\base, #INTRC_STAT]
-
-		cmp	\irqstat,#1<<16
-		movhs	\irqnr,#16
-		movlo	\irqnr,#0
-		movhs	\irqstat,\irqstat,lsr#16
-		cmp	\irqstat,#1<<8
-		addhs	\irqnr,\irqnr,#8
-		movhs	\irqstat,\irqstat,lsr#8
-		cmp	\irqstat,#1<<4
-		addhs	\irqnr,\irqnr,#4
-		movhs	\irqstat,\irqstat,lsr#4
-		cmp	\irqstat,#1<<2
-		addhs	\irqnr,\irqnr,#2
-		movhs	\irqstat,\irqstat,lsr#2
-		cmp	\irqstat,#1<<1
-		addhs	\irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
-		teq	\irqstat,#0
-		beq	1003f
-
-/* and now check for extended IRQ reasons */
-		cmp	\irqnr,#1
-		bls	1003f
-		cmp	\irqnr,#30
-		blo	1002f
-
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-		moveq  \irqnr,#SIC1_BASE_INT
-		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-		movne   \irqnr,#SIC2_BASE_INT
-		ldr	\irqstat, [\base, #INTRC_STAT]
-		ldr	\tmp,	  [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-		and	\irqstat,\irqstat,\tmp
-		b	1004f
-
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-		ldrne	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-		movne   \irqnr,#SIC1_BASE_INT
-		ldreq	\base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-		moveq   \irqnr,#SIC2_BASE_INT
-		ldr	\irqstat, [\base, #INTRC_STAT]
-		ldr	\tmp,	  [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-		bic	\irqstat,\irqstat,\tmp
-
-1004:
-
-		cmp	\irqstat,#1<<16
-		addhs	\irqnr,\irqnr,#16
-		movhs	\irqstat,\irqstat,lsr#16
-		cmp	\irqstat,#1<<8
-		addhs	\irqnr,\irqnr,#8
-		movhs	\irqstat,\irqstat,lsr#8
-		cmp	\irqstat,#1<<4
-		addhs	\irqnr,\irqnr,#4
-		movhs	\irqstat,\irqstat,lsr#4
-		cmp	\irqstat,#1<<2
-		addhs	\irqnr,\irqnr,#2
-		movhs	\irqstat,\irqstat,lsr#2
-		cmp	\irqstat,#1<<1
-		addhs	\irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-		teq	\irqstat,#0
-1003:
-		.endm
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN		(0)
-#define GPIO_OUT		(0x100)
-#define GPIO_BID		(0x200)
-#define GPIO_RAM		(0x300)
-#define GPIO_MUX		(0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00		(GPIO_IN | 0)
-#define GPI_01		(GPIO_IN | 1)
-#define GPI_02   	(GPIO_IN | 2)
-#define GPI_03 	 	(GPIO_IN | 3)
-#define GPI_04   	(GPIO_IN | 4)
-#define GPI_05   	(GPIO_IN | 5)
-#define GPI_06   	(GPIO_IN | 6)
-#define GPI_07   	(GPIO_IN | 7)
-#define GPI_08   	(GPIO_IN | 8)
-#define GPI_09   	(GPIO_IN | 9)
-#define U1_RX 		(GPIO_IN | 15)
-#define U2_HTCS 	(GPIO_IN | 16)
-#define U2_RX	 	(GPIO_IN | 17)
-#define U3_RX		(GPIO_IN | 18)
-#define U4_RX		(GPIO_IN | 19)
-#define U5_RX		(GPIO_IN | 20)
-#define U6_IRRX 	(GPIO_IN | 21)
-#define U7_HCTS 	(GPIO_IN | 22)
-#define U7_RX		(GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN	(GPIO_IN | 25)
-#define DISP_SYNC	(GPIO_IN | 26)
-#define SPI2_DATIN	(GPIO_IN | 27)
-#define GPI_11  	(GPIO_IN | 28)
-
-#define GPIO_IN_MASK   0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00		(GPIO_OUT | 0)
-#define GPO_01   	(GPIO_OUT | 1)
-#define GPO_02   	(GPIO_OUT | 2)
-#define GPO_03 	 	(GPIO_OUT | 3)
-#define GPO_04   	(GPIO_OUT | 4)
-#define GPO_05   	(GPIO_OUT | 5)
-#define GPO_06   	(GPIO_OUT | 6)
-#define GPO_07   	(GPIO_OUT | 7)
-#define GPO_08		(GPIO_OUT | 8)
-#define GPO_09   	(GPIO_OUT | 9)
-#define GPO_10   	(GPIO_OUT | 10)
-#define GPO_11 	 	(GPIO_OUT | 11)
-#define GPO_12   	(GPIO_OUT | 12)
-#define GPO_13   	(GPIO_OUT | 13)
-#define GPO_14   	(GPIO_OUT | 14)
-#define GPO_15   	(GPIO_OUT | 15)
-#define GPO_16  	(GPIO_OUT | 16)
-#define GPO_17 	 	(GPIO_OUT | 17)
-#define GPO_18   	(GPIO_OUT | 18)
-#define GPO_19   	(GPIO_OUT | 19)
-#define GPO_20   	(GPIO_OUT | 20)
-#define GPO_21   	(GPIO_OUT | 21)
-#define GPO_22   	(GPIO_OUT | 22)
-#define GPO_23   	(GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK   0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19		(GPIO_RAM | 0)
-#define RAM_D20  	(GPIO_RAM | 1)
-#define RAM_D21  	(GPIO_RAM | 2)
-#define RAM_D22 	(GPIO_RAM | 3)
-#define RAM_D23  	(GPIO_RAM | 4)
-#define RAM_D24  	(GPIO_RAM | 5)
-#define RAM_D25  	(GPIO_RAM | 6)
-#define RAM_D26  	(GPIO_RAM | 7)
-#define RAM_D27		(GPIO_RAM | 8)
-#define RAM_D28  	(GPIO_RAM | 9)
-#define RAM_D29  	(GPIO_RAM | 10)
-#define RAM_D30 	(GPIO_RAM | 11)
-#define RAM_D31  	(GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK   0x1fff
-
-/* I/O pins */
-#define GPIO_00  	(GPIO_BID | 25)
-#define GPIO_01 	(GPIO_BID | 26)
-#define GPIO_02  	(GPIO_BID | 27)
-#define GPIO_03  	(GPIO_BID | 28)
-#define GPIO_04 	(GPIO_BID | 29)
-#define GPIO_05  	(GPIO_BID | 30)
-
-#define GPIO_BID_MASK   0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL 	(GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK   0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-		     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-		     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
-	__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-		     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
-	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-		     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif				/* _PNX4008_GPIO_H_ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source at mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS         96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT   64
-
-#define CLK_SWITCH_ARM_INT 95	/*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94	/*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93	/*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT   32
-
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT   0
-
-#define SUB2_FIQ_N         31	/*active low */
-#define SUB1_FIQ_N         30	/*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1	/*active low */
-#define SUB1_IRQ_N         0	/*active low */
-
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-
-#endif /* __PNX4008_IRQS_h__ */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/param.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/param.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define HZ 100
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE		0x08000000
-#define PNX4008_IRAM_SIZE		0x00010000
-#define PNX4008_YUV_SLAVE_BASE		0x10000000
-#define PNX4008_DUM_SLAVE_BASE		0x18000000
-#define PNX4008_NDF_FLASH_BASE		0x20020000
-#define PNX4008_SPI1_BASE		0x20088000
-#define PNX4008_SPI2_BASE		0x20090000
-#define PNX4008_SD_CONFIG_BASE		0x20098000
-#define PNX4008_FLASH_DATA		0x200B0000
-#define PNX4008_MLC_FLASH_BASE		0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE	0x300A0000
-#define PNX4008_DMA_CONFIG_BASE		0x31000000
-#define PNX4008_USB_CONFIG_BASE		0x31020000
-#define PNX4008_SDRAM_CFG_BASE		0x31080000
-#define PNX4008_AHB2FAB_BASE		0x40000000
-#define PNX4008_PWRMAN_BASE		0x40004000
-#define PNX4008_INTCTRLMIC_BASE		0x40008000
-#define PNX4008_INTCTRLSIC1_BASE	0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE	0x40010000
-#define PNX4008_HSUART1_BASE		0x40014000
-#define PNX4008_HSUART2_BASE		0x40018000
-#define PNX4008_HSUART7_BASE		0x4001C000
-#define PNX4008_RTC_BASE		0x40024000
-#define PNX4008_PIO_BASE		0x40028000
-#define PNX4008_MSTIMER_BASE		0x40034000
-#define PNX4008_HSTIMER_BASE		0x40038000
-#define PNX4008_WDOG_BASE		0x4003C000
-#define PNX4008_DEBUG_BASE		0x40040000
-#define PNX4008_TOUCH1_BASE		0x40048000
-#define PNX4008_KEYSCAN_BASE		0x40050000
-#define PNX4008_UARTCTRL_BASE		0x40054000
-#define PNX4008_PWM_BASE		0x4005C000
-#define PNX4008_UART3_BASE		0x40080000
-#define PNX4008_UART4_BASE		0x40088000
-#define PNX4008_UART5_BASE		0x40090000
-#define PNX4008_UART6_BASE		0x40098000
-#define PNX4008_I2C1_BASE		0x400A0000
-#define PNX4008_I2C2_BASE		0x400A8000
-#define PNX4008_MAGICGATE_BASE		0x400B0000
-#define PNX4008_DUMCONF_BASE		0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE       	0x400BC000
-#define PNX4008_DSP_BASE		0x400C0000
-#define PNX4008_PROFCOUNTER_BASE	0x400C8000
-#define PNX4008_CRYPTO_BASE		0x400D0000
-#define PNX4008_CAMIFCONF_BASE		0x400D8000
-#define PNX4008_YUV2RGB_BASE		0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE	0x400E8000
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif				/* ASSEMBLER */
-#endif				/* __ASM_ARCH_PNX4008_PM_H */
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#define CLOCK_TICK_RATE		1000000
-
-#endif
--- linux-2.6.orig/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
-	while (UART5_FR & (1 << 5))
-		barrier();
-
-	UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
--- linux-2.6.orig/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-
-static void pnx4008_mask_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));	/* mask interrupt */
-}
-
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq));	/* unmask interrupt */
-}
-
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
-	__raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));	/* mask interrupt */
-	__raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));	/* clear interrupt status */
-}
-
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));	/*edge sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));	/*rising edge */
-		irq_set_handler(d->irq, handle_edge_irq);
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));	/*edge sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));	/*falling edge */
-		irq_set_handler(d->irq, handle_edge_irq);
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));	/*level sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));	/*low level */
-		irq_set_handler(d->irq, handle_level_irq);
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));	/*level sensitive */
-		__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));	/* high level */
-		irq_set_handler(d->irq, handle_level_irq);
-		break;
-
-	/* IRQ_TYPE_EDGE_BOTH is not supported */
-	default:
-		printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
-		return -1;
-	}
-	return 0;
-}
-
-static struct irq_chip pnx4008_irq_chip = {
-	.irq_ack = pnx4008_mask_ack_irq,
-	.irq_mask = pnx4008_mask_irq,
-	.irq_unmask = pnx4008_unmask_irq,
-	.irq_set_type = pnx4008_set_irq_type,
-};
-
-void __init pnx4008_init_irq(void)
-{
-	unsigned int i;
-
-	/* configure IRQ's */
-	for (i = 0; i < NR_IRQS; i++) {
-		set_irq_flags(i, IRQF_VALID);
-		irq_set_chip(i, &pnx4008_irq_chip);
-		pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
-	}
-
-	/* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-	pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
-			     pnx4008_irq_type[SUB1_IRQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
-			     pnx4008_irq_type[SUB2_IRQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
-			     pnx4008_irq_type[SUB1_FIQ_N]);
-	pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
-			     pnx4008_irq_type[SUB2_FIQ_N]);
-
-	/* mask all others */
-	__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
-			(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
-		INTC_ER(MAIN_BASE_INT));
-	__raw_writel(0, INTC_ER(SIC1_BASE_INT));
-	__raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-
-static void *saved_sram;
-
-static struct clk *pll4_clk;
-
-static inline void pnx4008_standby(void)
-{
-	void (*pnx4008_cpu_standby_ptr) (void);
-
-	local_irq_disable();
-	local_fiq_disable();
-
-	clk_disable(pll4_clk);
-
-	/*saving portion of SRAM to be used by suspend function. */
-	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-
-	/*make sure SRAM copy gets physically written into SDRAM.
-	   SDRAM will be placed into self-refresh during power down */
-	flush_cache_all();
-
-	/*copy suspend function into SRAM */
-	memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-
-	/*do suspend */
-	pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
-	pnx4008_cpu_standby_ptr();
-
-	/*restoring portion of SRAM that was used by suspend function */
-	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-
-	clk_enable(pll4_clk);
-
-	local_fiq_enable();
-	local_irq_enable();
-}
-
-static inline void pnx4008_suspend(void)
-{
-	void (*pnx4008_cpu_suspend_ptr) (void);
-
-	local_irq_disable();
-	local_fiq_disable();
-
-	clk_disable(pll4_clk);
-
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-	/*saving portion of SRAM to be used by suspend function. */
-	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-
-	/*make sure SRAM copy gets physically written into SDRAM.
-	   SDRAM will be placed into self-refresh during power down */
-	flush_cache_all();
-
-	/*copy suspend function into SRAM */
-	memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-
-	/*do suspend */
-	pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
-	pnx4008_cpu_suspend_ptr();
-
-	/*restoring portion of SRAM that was used by suspend function */
-	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-
-	clk_enable(pll4_clk);
-
-	local_fiq_enable();
-	local_irq_enable();
-}
-
-static int pnx4008_pm_enter(suspend_state_t state)
-{
-	switch (state) {
-	case PM_SUSPEND_STANDBY:
-		pnx4008_standby();
-		break;
-	case PM_SUSPEND_MEM:
-		pnx4008_suspend();
-		break;
-	}
-	return 0;
-}
-
-static int pnx4008_pm_valid(suspend_state_t state)
-{
-	return (state == PM_SUSPEND_STANDBY) ||
-	       (state == PM_SUSPEND_MEM);
-}
-
-static const struct platform_suspend_ops pnx4008_pm_ops = {
-	.enter = pnx4008_pm_enter,
-	.valid = pnx4008_pm_valid,
-};
-
-int __init pnx4008_pm_init(void)
-{
-	u32 sram_size_to_allocate;
-
-	pll4_clk = clk_get(0, "ck_pll4");
-	if (IS_ERR(pll4_clk)) {
-		printk(KERN_ERR
-		       "PM Suspend cannot acquire ARM(PLL4) clock control\n");
-		return PTR_ERR(pll4_clk);
-	}
-
-	if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
-		sram_size_to_allocate = pnx4008_cpu_standby_sz;
-	else
-		sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-
-	saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
-	if (!saved_sram) {
-		printk(KERN_ERR
-		       "PM Suspend: cannot allocate memory to save portion of SRAM\n");
-		clk_put(pll4_clk);
-		return -ENOMEM;
-	}
-
-	suspend_set_ops(&pnx4008_pm_ops);
-	return 0;
-}
--- linux-2.6.orig/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/serial.c
- *
- *  PNX4008 UART initialization
- *
- *  Copyright:	MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <mach/platform.h>
-#include <mach/hardware.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-
-#define UART_3		0
-#define UART_4		1
-#define UART_5		2
-#define UART_6		3
-#define UART_UNKNOWN	(-1)
-
-#define UART3_BASE_VA	IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA	IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA	IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA	IO_ADDRESS(PNX4008_UART6_BASE)
-
-#define UART_FCR_OFFSET		8
-#define UART_FIFO_SIZE		64
-
-void pnx4008_uart_init(void)
-{
-	u32 tmp;
-	int i = UART_FIFO_SIZE;
-
-	__raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
-	__raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-
-	/* Send a NULL to fix the UART HW bug */
-	__raw_writel(0x00, UART5_BASE_VA);
-	__raw_writel(0x00, UART3_BASE_VA);
-
-	while (i--) {
-		tmp = __raw_readl(UART5_BASE_VA);
-		tmp = __raw_readl(UART3_BASE_VA);
-	}
-	__raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
-	__raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-
-	/* setup wakeup interrupt */
-	start_int_set_rising_edge(SE_U3_RX_INT);
-	start_int_ack(SE_U3_RX_INT);
-	start_int_umask(SE_U3_RX_INT);
-
-	start_int_set_rising_edge(SE_U5_RX_INT);
-	start_int_ack(SE_U5_RX_INT);
-	start_int_umask(SE_U5_RX_INT);
-}
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-
-		.text
-
-ENTRY(pnx4008_cpu_suspend)
-	@this function should be entered in Direct run mode.
-
-	@ save registers on stack
-	stmfd	sp!, {r0 - r6, lr}
-
-	@ setup Power Manager base address in r4
-	@ and put it's value in r5
-	mov	r4, #(PWRMAN_VA_BASE & 0xff000000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-	ldr	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ setup SDRAM controller base address in r2
-	@ and put it's value in r3
-	mov	r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do save current bit settings in r1
-	mov	r1, r5
-
-	@ set SDRAM self-refresh bit
-	orr	r5, r5, #(1 << 9)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get into self-refresh mode
-2:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #(1 << 2)
-	beq	2b
-
-	@ to prepare SDRAM to get out of self-refresh mode after wakeup
-	orr	r5, r5, #(1 << 7)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do enter stop mode
-	orr	r5, r5, #(1 << 0)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	@ sleeping now...
-
-	@ coming out of STOP mode into Direct Run mode
-	@ clear STOP mode and SDRAM self-refresh bits
-	str	r1, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get out self-refresh mode
-3:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #5
-	bne	3b
-
-	@ restore regs and return
-	ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_suspend_sz)
-	.word	. - pnx4008_cpu_suspend
-
-ENTRY(pnx4008_cpu_standby)
-	@ save registers on stack
-	stmfd	sp!, {r0 - r6, lr}
-
-	@ setup Power Manager base address in r4
-	@ and put it's value in r5
-	mov	r4, #(PWRMAN_VA_BASE & 0xff000000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-	orr	r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-	ldr	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ setup SDRAM controller base address in r2
-	@ and put it's value in r3
-	mov	r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-	orr	r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ do save current bit settings in r1
-	mov	r1, r5
-
-	@ set SDRAM self-refresh bit
-	orr	r5, r5, #(1 << 9)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit
-	and	r5, r5, #(~(1 << 9))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get into self-refresh mode
-2:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #(1 << 2)
-	beq	2b
-
-	@ set 'get out of self-refresh mode after wakeup' bit
-	orr	r5, r5, #(1 << 7)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	mcr     p15, 0, r0, c7, c0, 4	@ kinda sleeping now...
-
-	@ set SDRAM self-refresh bit latch
-	orr	r5, r5, #(1 << 8)
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ clear SDRAM self-refresh bit latch
-	and	r5, r5, #(~(1 << 8))
-	str	r5, [r4, #PWR_CTRL_REG_OFFS]
-
-	@ wait for SDRAM to get out self-refresh mode
-3:	ldr	r3, [r2, #MPMC_STATUS_REG_OFFS]
-	tst	r3, #5
-	bne	3b
-
-	@ restore regs and return
-	ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_standby_sz)
-	.word	. - pnx4008_cpu_standby
-
-ENTRY(pnx4008_cache_clean_invalidate)
-	stmfd	sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
-#else
-1:	mrc	p15, 0, r15, c7, c14, 3		@ test,clean,invalidate
-	bne     1b
-#endif
-	ldmfd   sp!, {r0 - r6, pc}
--- linux-2.6.orig/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-
-#include "time.h"
-
-/*! Note: all timers are UPCOUNTING */
-
-/*!
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
-	u32 ticks_to_match =
-	    __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
-	u32 elapsed = LATCH - ticks_to_match;
-	return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
-	if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-
-		do {
-			timer_tick();
-
-			/*
-			 * this algorithm takes care of possible delay
-			 * for this interrupt handling longer than a normal
-			 * timer period
-			 */
-			__raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
-				     HSTIM_MATCH0);
-			__raw_writel(MATCH0_INT, HSTIM_INT);	/* clear interrupt */
-
-			/*
-			 * The goal is to keep incrementing HSTIM_MATCH0
-			 * register until HSTIM_MATCH0 indicates time after
-			 * what HSTIM_COUNTER indicates.
-			 */
-		} while ((signed)
-			 (__raw_readl(HSTIM_MATCH0) -
-			  __raw_readl(HSTIM_COUNTER)) < 0);
-	}
-
-	return IRQ_HANDLED;
-}
-
-static struct irqaction pnx4008_timer_irq = {
-	.name = "PNX4008 Tick Timer",
-	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-	.handler = pnx4008_timer_interrupt
-};
-
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
-	__raw_writel(RESET_COUNT, MSTIM_CTRL);
-	while (__raw_readl(MSTIM_COUNTER)) ;	/* wait for reset to complete. 100% guarantee event */
-	__raw_writel(0, MSTIM_CTRL);	/* stop the timer */
-	__raw_writel(0, MSTIM_MCTRL);
-
-	__raw_writel(RESET_COUNT, HSTIM_CTRL);
-	while (__raw_readl(HSTIM_COUNTER)) ;	/* wait for reset to complete. 100% guarantee event */
-	__raw_writel(0, HSTIM_CTRL);
-	__raw_writel(0, HSTIM_MCTRL);
-	__raw_writel(0, HSTIM_CCR);
-	__raw_writel(12, HSTIM_PMATCH);	/* scale down to 1 MHZ */
-	__raw_writel(LATCH, HSTIM_MATCH0);
-	__raw_writel(MR0_INT, HSTIM_MCTRL);
-
-	setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-
-	__raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);	/*start timer, stop when JTAG active */
-}
-
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN                   1
-#define TIMER_CLK_EN                      2	/* HS and MS timers? */
-
-static u32 timclk_ctrl_reg_save;
-
-void pnx4008_timer_suspend(void)
-{
-	timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
-	__raw_writel(0, TIMCLK_CTRL_REG);	/* disable timers */
-}
-
-void pnx4008_timer_resume(void)
-{
-	__raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);	/* enable timers */
-}
-
-struct sys_timer pnx4008_timer = {
-	.init = pnx4008_setup_timer,
-	.offset = pnx4008_gettimeoffset,
-	.suspend = pnx4008_timer_suspend,
-	.resume = pnx4008_timer_resume,
-};
-
--- linux-2.6.orig/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source at mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#define TICKS2USECS(x)	(x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
-#endif
--- linux-2.6.orig/arch/arm/tools/mach-types
+++ linux-2.6/arch/arm/tools/mach-types
@@ -158,7 +158,6 @@ edb9315a		MACH_EDB9315A		EDB9315A		772
 stargate2		MACH_STARGATE2		STARGATE2		774
 intelmote2		MACH_INTELMOTE2		INTELMOTE2		775
 trizeps4		MACH_TRIZEPS4		TRIZEPS4		776
-pnx4008			MACH_PNX4008		PNX4008			782
 cpuat91			MACH_CPUAT91		CPUAT91			787
 iq81340sc		MACH_IQ81340SC		IQ81340SC		799
 iq81340mc		MACH_IQ81340MC		IQ81340MC		801
--- linux-2.6.orig/drivers/i2c/busses/Kconfig
+++ linux-2.6/drivers/i2c/busses/Kconfig
@@ -545,7 +545,7 @@ config I2C_PMCMSP
 
 config I2C_PNX
 	tristate "I2C bus support for Philips PNX and NXP LPC targets"
-	depends on ARCH_PNX4008 || ARCH_LPC32XX
+	depends on ARCH_LPC32XX
 	help
 	  This driver supports the Philips IP3204 I2C IP block master and/or
 	  slave controller
--- linux-2.6.orig/drivers/usb/Kconfig
+++ linux-2.6/drivers/usb/Kconfig
@@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI
 	default y if PXA3xx
 	default y if ARCH_EP93XX
 	default y if ARCH_AT91
-	default y if ARCH_PNX4008
 	default y if MFD_TC6393XB
 	default y if ARCH_W90X900
 	default y if ARCH_DAVINCI_DA8XX
--- linux-2.6.orig/drivers/usb/host/Kconfig
+++ linux-2.6/drivers/usb/host/Kconfig
@@ -292,7 +292,7 @@ config USB_OHCI_HCD
 	depends on USB && USB_ARCH_HAS_OHCI
 	select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
 	select USB_OTG_UTILS if ARCH_OMAP
-	select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
+	select USB_ISP1301 if ARCH_LPC32XX
 	---help---
 	  The Open Host Controller Interface (OHCI) is a standard for accessing
 	  USB 1.1 host controller hardware.  It does more in hardware than Intel's
--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
+#ifdef CONFIG_ARCH_LPC32XX
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -2,7 +2,6 @@
  * driver for NXP USB Host devices
  *
  * Currently supported OHCI host devices:
- * - Philips PNX4008
  * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
@@ -66,38 +65,6 @@ static struct clk *usb_pll_clk;
 static struct clk *usb_dev_clk;
 static struct clk *usb_otg_clk;
 
-static void isp1301_configure_pnx4008(void)
-{
-	/* PNX4008 only supports DAT_SE0 USB mode */
-	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-	/* Power up externel charge-pump */
-
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(MC1_DAT_SE0 | MC1_SPEED_REG));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_2,
-		MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-		~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
-		0xFF);
-	i2c_smbus_write_byte_data(isp1301_i2c_client,
-		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
-		0xFF);
-}
-
 static void isp1301_configure_lpc32xx(void)
 {
 	/* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(vo
 
 static void isp1301_configure(void)
 {
-	if (machine_is_pnx4008())
-		isp1301_configure_pnx4008();
-	else
-		isp1301_configure_lpc32xx();
+	isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_h
 	.start_port_reset = ohci_start_port_reset,
 };
 
-static void nxp_set_usb_bits(void)
-{
-	if (machine_is_pnx4008()) {
-		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-		start_int_ack(SE_USB_OTG_ATX_INT_N);
-		start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-		start_int_ack(SE_USB_OTG_TIMER_INT);
-		start_int_umask(SE_USB_OTG_TIMER_INT);
-
-		start_int_set_rising_edge(SE_USB_I2C_INT);
-		start_int_ack(SE_USB_I2C_INT);
-		start_int_umask(SE_USB_I2C_INT);
-
-		start_int_set_rising_edge(SE_USB_INT);
-		start_int_ack(SE_USB_INT);
-		start_int_umask(SE_USB_INT);
-
-		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-		start_int_ack(SE_USB_NEED_CLK_INT);
-		start_int_umask(SE_USB_NEED_CLK_INT);
-
-		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-	}
-}
-
-static void nxp_unset_usb_bits(void)
-{
-	if (machine_is_pnx4008()) {
-		start_int_mask(SE_USB_OTG_ATX_INT_N);
-		start_int_mask(SE_USB_OTG_TIMER_INT);
-		start_int_mask(SE_USB_I2C_INT);
-		start_int_mask(SE_USB_INT);
-		start_int_mask(SE_USB_NEED_CLK_INT);
-		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-	}
-}
-
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(s
 		goto out8;
 	}
 
-	/* Set all USB bits in the Start Enable register */
-	nxp_set_usb_bits();
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(s
 
 	nxp_stop_hc();
 out8:
-	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out7:
 	clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct pla
 	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	nxp_unset_usb_bits();
 	clk_disable(usb_pll_clk);
 	clk_put(usb_pll_clk);
 	clk_disable(usb_dev_clk);
--- linux-2.6.orig/drivers/watchdog/Kconfig
+++ linux-2.6/drivers/watchdog/Kconfig
@@ -237,12 +237,12 @@ config OMAP_WATCHDOG
 	  here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
 
 config PNX4008_WATCHDOG
-	tristate "PNX4008 and LPC32XX Watchdog"
-	depends on ARCH_PNX4008 || ARCH_LPC32XX
+	tristate "LPC32XX Watchdog"
+	depends on ARCH_LPC32XX
 	select WATCHDOG_CORE
 	help
 	  Say Y here if to include support for the watchdog timer
-	  in the PNX4008 or LPC32XX processor.
+	  in the LPC32XX processor.
 	  This driver can be built as a module by choosing M. The module
 	  will be called pnx4008_wdt.
 


From horms at verge.net.au  Mon Aug 27 02:45:06 2012
From: horms at verge.net.au (Simon Horman)
Date: Mon, 27 Aug 2012 15:45:06 +0900
Subject: [GIT PULL] Renesas ARM-based SoC: Armadillo800EVA for 3.7
In-Reply-To: <1346049610-2266-1-git-send-email-horms@verge.net.au>
References: <1346049610-2266-1-git-send-email-horms@verge.net.au>
Message-ID: <20120827064506.GB26953@verge.net.au>

Somehow I forgot to give the previous email a subject, not a good start :(

On Mon, Aug 27, 2012 at 03:40:08PM +0900, Simon Horman wrote:
> Hi Arnd, Hi Olaf,
> 
> please consider the following enhancements for the Armadillo800EVA board
> from Laurent Pinchart for inclusion in 3.7.
> 
> I am currently in the processes of taking over maintenance
> of shmoble from Rafael Wysocki and this my the first pull request
> in that role.
> 
> ----------------------------------------------------------------
> The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
> 
>   Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git armadillo800eva
> 
> for you to fetch changes up to 5c1d2d16772e2d7d4e2e8da99a92d6f50b9102f0:
> 
>   ARM: mach-shmobile: armadillo800eva: Enable power button as wakeup source (2012-08-25 15:44:53 +0900)
> 
> ----------------------------------------------------------------
> Laurent Pinchart (2):
>       ARM: mach-shmobile: armadillo800eva: Fix GPIO buttons descriptions
>       ARM: mach-shmobile: armadillo800eva: Enable power button as wakeup source
> 
>  arch/arm/mach-shmobile/board-armadillo800eva.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


From keguang.zhang at gmail.com  Mon Aug 27 02:55:36 2012
From: keguang.zhang at gmail.com (Kelvin Cheung)
Date: Mon, 27 Aug 2012 14:55:36 +0800
Subject: [PATCH v3] clk: add Loongson1B clock support
In-Reply-To: <1345457135-12737-1-git-send-email-keguang.zhang@gmail.com>
References: <1345457135-12737-1-git-send-email-keguang.zhang@gmail.com>
Message-ID: <CAJhJPsXdCn0u9aefehsTd1ZLLnbBgZZFExq=PC_Z-jv4F9XqWg@mail.gmail.com>

Ping?

2012/8/20 Kelvin Cheung <keguang.zhang at gmail.com>

> This adds clock support to Loongson1B SoC using the common clock
> infrastructure.
>
> Signed-off-by: Kelvin Cheung <keguang.zhang at gmail.com>
> ---
>  drivers/clk/Makefile   |    1 +
>  drivers/clk/clk-ls1x.c |  111
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 112 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/clk-ls1x.c
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 5869ea3..018ec57 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA)    += socfpga/
>  obj-$(CONFIG_PLAT_SPEAR)       += spear/
>  obj-$(CONFIG_ARCH_U300)                += clk-u300.o
>  obj-$(CONFIG_ARCH_INTEGRATOR)  += versatile/
> +obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
>
>  # Chip specific
>  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
> diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
> new file mode 100644
> index 0000000..f20b750
> --- /dev/null
> +++ b/drivers/clk/clk-ls1x.c
> @@ -0,0 +1,111 @@
> +/*
> + * Copyright (c) 2012 Zhang, Keguang <keguang.zhang at gmail.com>
> + *
> + * This program is free software; you can redistribute  it and/or modify
> it
> + * under  the terms of  the GNU General  Public License as published by
> the
> + * Free Software Foundation;  either version 2 of the  License, or (at
> your
> + * option) any later version.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +#include <loongson1.h>
> +
> +#define OSC    33
> +
> +static DEFINE_SPINLOCK(_lock);
> +
> +static int ls1x_pll_clk_enable(struct clk_hw *hw)
> +{
> +       return 0;
> +}
> +
> +static void ls1x_pll_clk_disable(struct clk_hw *hw)
> +{
> +}
> +
> +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
> +                                            unsigned long parent_rate)
> +{
> +       u32 pll, rate;
> +
> +       pll = __raw_readl(LS1X_CLK_PLL_FREQ);
> +       rate = ((12 + (pll & 0x3f)) * 1000000) +
> +               ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
> +       rate *= OSC;
> +       rate >>= 1;
> +
> +       return rate;
> +}
> +
> +static const struct clk_ops ls1x_pll_clk_ops = {
> +       .enable = ls1x_pll_clk_enable,
> +       .disable = ls1x_pll_clk_disable,
> +       .recalc_rate = ls1x_pll_recalc_rate,
> +};
> +
> +static struct clk * __init clk_register_pll(struct device *dev,
> +        const char *name, const char *parent_name, unsigned long flags)
> +{
> +       struct clk_hw *hw;
> +       struct clk *clk;
> +       struct clk_init_data init;
> +
> +       /* allocate the divider */
> +       hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
> +       if (!hw) {
> +               pr_err("%s: could not allocate clk_hw\n", __func__);
> +               return ERR_PTR(-ENOMEM);
> +       }
> +
> +       init.name = name;
> +       init.ops = &ls1x_pll_clk_ops;
> +       init.flags = flags | CLK_IS_BASIC;
> +       init.parent_names = (parent_name ? &parent_name : NULL);
> +       init.num_parents = (parent_name ? 1 : 0);
> +       hw->init = &init;
> +
> +       /* register the clock */
> +       clk = clk_register(dev, hw);
> +
> +       if (IS_ERR(clk))
> +               kfree(hw);
> +
> +       return clk;
> +}
> +
> +void __init ls1x_clk_init(void)
> +{
> +       struct clk *clk;
> +
> +       clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
> +       clk_prepare_enable(clk);
> +
> +       clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_CPU_SHIFT,
> +                       DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "cpu", NULL);
> +
> +       clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_DC_SHIFT,
> +                       DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "dc", NULL);
> +
> +       clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
> +                       CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV,
> DIV_DDR_SHIFT,
> +                       DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "ahb", NULL);
> +       clk_register_clkdev(clk, "stmmaceth", NULL);
> +
> +       clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
> 2);
> +       clk_prepare_enable(clk);
> +       clk_register_clkdev(clk, "apb", NULL);
> +       clk_register_clkdev(clk, "serial8250", NULL);
> +}
> --
> 1.7.1
>
>


-- 
Best Regards!
Kelvin
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From nicolas.ferre at atmel.com  Mon Aug 27 04:08:07 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 27 Aug 2012 10:08:07 +0200
Subject: [GIT PULL] at91: fixes for 3.6 (take 1 bis)
In-Reply-To: <5037A4F3.9090608@atmel.com>
References: <5037A4F3.9090608@atmel.com>
Message-ID: <503B2AE7.4020704@atmel.com>

Hi,

This pull request supersedes the previous one from August 24th. It removes
the ASoC SSC part which is now handled by Mark Brown.

The following changes since commit d9875690d9b89a866022ff49e3fcea892345ad92:

  Linux 3.6-rc2 (2012-08-16 14:51:24 -0700)

are available in the git repository at:

  git://github.com/at91linux/linux-at91.git tags/at91-fixes

for you to fetch changes up to 51a6149b89b822cacf572b2ca2a15cb6f2232b11:

  ARM: at91/feature-removal-schedule: delay at91_mci removal (2012-08-27 09:59:36 +0200)

----------------------------------------------------------------
Fixes for AT91 related to:
- move to sparse IRQ: some drivers were forgotten
- a DTS typo
- the delay for removal of old at91_mci driver

----------------------------------------------------------------
Bo Shen (1):
      ARM: at91/dts: remove partial parameter in at91sam9g25ek.dts

Ludovic Desroches (3):
      ARM: at91: fix system timer irq issue due to sparse irq support
      ARM: at91: fix rtc-at91sam9 irq issue due to sparse irq support
      ARM: at91/feature-removal-schedule: delay at91_mci removal

Nicolas Ferre (1):
      ARM: at91/clock: fix PLLA overclock warning

 Documentation/feature-removal-schedule.txt |    2 +-
 arch/arm/boot/dts/at91sam9g25ek.dts        |    2 +-
 arch/arm/mach-at91/at91rm9200_time.c       |    2 +-
 arch/arm/mach-at91/at91sam9260_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9261_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9263_devices.c   |   10 ++++++++--
 arch/arm/mach-at91/at91sam9g45_devices.c   |    6 +++++-
 arch/arm/mach-at91/at91sam9rl_devices.c    |    6 +++++-
 arch/arm/mach-at91/clock.c                 |   12 ++++++++++++
 drivers/rtc/rtc-at91sam9.c                 |   22 +++++++++++++++-------
 10 files changed, 58 insertions(+), 16 deletions(-)

Thanks, best regards,
-- 
Nicolas Ferre


From thomas.petazzoni at free-electrons.com  Mon Aug 27 19:35:27 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Tue, 28 Aug 2012 01:35:27 +0200
Subject: Fix orion_nand build on ARCH_MVEBU
In-Reply-To: <20120816183708.GT22226@titan.lakedaemon.net>
References: <20120816183708.GT22226@titan.lakedaemon.net>
Message-ID: <1346110528-30858-1-git-send-email-thomas.petazzoni@free-electrons.com>

Jason,

I investigated a little bit, and found out that orion_nand driver was
the only PLAT_ORION driver needing <mach/hardware.h>, and in fact this
include was not needed. The attached patch therefore removes this
include from orion_nand.

Thanks,

Thomas



From hdoyu at nvidia.com  Tue Aug 28 01:13:04 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 08:13:04 +0300
Subject: [v4 4/4] ARM: dma-mapping: IOMMU allocates pages from atomic_pool
 with GFP_ATOMIC
In-Reply-To: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
References: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346130784-23571-5-git-send-email-hdoyu@nvidia.com>

Make use of the same atomic pool as DMA does, and skip a kernel page
mapping which can involve sleep'able operations at allocating a kernel
page table.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4ef2d7b..f5024f9 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1309,6 +1309,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
 	return NULL;
 }
 
+static void *__iommu_alloc_atomic(struct device *dev, size_t size,
+				  dma_addr_t *handle)
+{
+	struct page *page;
+	void *addr;
+
+	addr = __alloc_from_pool(size, &page);
+	if (!addr)
+		return NULL;
+
+	*handle = __iommu_create_mapping(dev, &page, size);
+	if (*handle == DMA_ERROR_CODE)
+		goto err_mapping;
+
+	return addr;
+
+err_mapping:
+	__free_from_pool(addr, size);
+	return NULL;
+}
+
+static void __iommu_free_atomic(struct device *dev, struct page **pages,
+				dma_addr_t handle, size_t size)
+{
+	__iommu_remove_mapping(dev, handle, size);
+	__free_from_pool(page_address(pages[0]), size);
+}
+
 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	    dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
 {
@@ -1326,6 +1354,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
 	*handle = DMA_ERROR_CODE;
 	size = PAGE_ALIGN(size);
 
+	if (gfp & GFP_ATOMIC)
+		return __iommu_alloc_atomic(dev, size, handle);
+
 	pages = __iommu_alloc_buffer(dev, size, gfp);
 	if (!pages)
 		return NULL;
@@ -1392,6 +1423,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
 		return;
 	}
 
+	if (__in_atomic_pool(cpu_addr, size)) {
+		__iommu_free_atomic(dev, pages, handle, size);
+		return;
+	}
+
 	if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
 		unmap_kernel_range((unsigned long)cpu_addr, size);
 		vunmap(cpu_addr);
-- 
1.7.5.4



From hdoyu at nvidia.com  Tue Aug 28 01:13:01 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 08:13:01 +0300
Subject: [v4 1/4] ARM: dma-mapping: atomic_pool with struct page **pages
In-Reply-To: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
References: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346130784-23571-2-git-send-email-hdoyu@nvidia.com>

struct page **pages is necessary to align with non atomic path in
__iommu_get_pages(). atomic_pool() has the intialized **pages instead
of just *page.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   17 ++++++++++++++---
 1 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 1123808..51d5e2b 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -296,7 +296,7 @@ struct dma_pool {
 	unsigned long *bitmap;
 	unsigned long nr_pages;
 	void *vaddr;
-	struct page *page;
+	struct page **pages;
 };
 
 static struct dma_pool atomic_pool = {
@@ -335,6 +335,7 @@ static int __init atomic_pool_init(void)
 	unsigned long nr_pages = pool->size >> PAGE_SHIFT;
 	unsigned long *bitmap;
 	struct page *page;
+	struct page **pages;
 	void *ptr;
 	int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
 
@@ -342,21 +343,31 @@ static int __init atomic_pool_init(void)
 	if (!bitmap)
 		goto no_bitmap;
 
+	pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
+	if (!pages)
+		goto no_pages;
+
 	if (IS_ENABLED(CONFIG_CMA))
 		ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
 	else
 		ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
 					   &page, NULL);
 	if (ptr) {
+		int i;
+
+		for (i = 0; i < nr_pages; i++)
+			pages[i] = page + i;
+
 		spin_lock_init(&pool->lock);
 		pool->vaddr = ptr;
-		pool->page = page;
+		pool->pages = pages;
 		pool->bitmap = bitmap;
 		pool->nr_pages = nr_pages;
 		pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
 		       (unsigned)pool->size / 1024);
 		return 0;
 	}
+no_pages:
 	kfree(bitmap);
 no_bitmap:
 	pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
@@ -481,7 +492,7 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	if (pageno < pool->nr_pages) {
 		bitmap_set(pool->bitmap, pageno, count);
 		ptr = pool->vaddr + PAGE_SIZE * pageno;
-		*ret_page = pool->page + pageno;
+		*ret_page = pool->pages[pageno];
 	} else {
 		pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
 			    "Please increase it with coherent_pool= kernel parameter!\n",
-- 
1.7.5.4



From hdoyu at nvidia.com  Tue Aug 28 01:13:03 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 08:13:03 +0300
Subject: [v4 3/4] ARM: dma-mapping: Introduce __atomic_get_pages() for
 __iommu_get_pages()
In-Reply-To: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
References: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346130784-23571-4-git-send-email-hdoyu@nvidia.com>

Support atomic allocation in __iommu_get_pages().

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index a62f552..4ef2d7b 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -503,6 +503,15 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
+static struct page **__atomic_get_pages(void *addr)
+{
+	struct dma_pool *pool = &atomic_pool;
+	struct page **pages = pool->pages;
+	int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
+
+	return pages + offs;
+}
+
 static bool __in_atomic_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
@@ -1288,6 +1297,9 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
 {
 	struct vm_struct *area;
 
+	if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
+		return __atomic_get_pages(cpu_addr);
+
 	if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
 		return cpu_addr;
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 29 02:55:33 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:33 +0300
Subject: [RFC 3/5] ARM: dma-mapping: New dma_map_ops->iova_alloc*_at* function
In-Reply-To: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
References: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346223335-31455-4-git-send-email-hdoyu@nvidia.com>

To allocate IOVA area at specified address

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/include/asm/dma-mapping.h |    9 +++++++++
 arch/arm/mm/dma-mapping.c          |   35 +++++++++++++++++++++++++++++++++++
 include/linux/dma-mapping.h        |    2 ++
 3 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 5b86600..f04a533 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -187,6 +187,15 @@ static inline void dma_iova_free(struct device *dev, dma_addr_t addr,
 	ops->iova_free(dev, addr, size);
 }
 
+static inline dma_addr_t dma_iova_alloc_at(struct device *dev, dma_addr_t addr,
+					   size_t size)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+
+	return ops->iova_alloc_at(dev, addr, size);
+}
+
 static inline size_t dma_iova_get_free_total(struct device *dev)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c18522a..8ca2d1a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1080,6 +1080,40 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
 	return mapping->base + (start << (mapping->order + PAGE_SHIFT));
 }
 
+static dma_addr_t __alloc_iova_at(struct dma_iommu_mapping *mapping,
+				  dma_addr_t iova, size_t size)
+{
+	unsigned int count, start, orig;
+	unsigned long flags;
+
+	count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
+		 (1 << mapping->order) - 1) >> mapping->order;
+
+	spin_lock_irqsave(&mapping->lock, flags);
+
+	orig = (iova - mapping->base) >> (mapping->order + PAGE_SHIFT);
+	start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits,
+					   orig, count, 0);
+
+	if ((start > mapping->bits) || (orig != start)) {
+		spin_unlock_irqrestore(&mapping->lock, flags);
+		return DMA_ERROR_CODE;
+	}
+
+	bitmap_set(mapping->bitmap, start, count);
+	spin_unlock_irqrestore(&mapping->lock, flags);
+
+	return mapping->base + (start << (mapping->order + PAGE_SHIFT));
+}
+
+static dma_addr_t arm_iommu_iova_alloc_at(struct device *dev, dma_addr_t iova,
+				size_t size)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+
+	return __alloc_iova_at(mapping, iova, size);
+}
+
 static dma_addr_t arm_iommu_iova_alloc(struct device *dev, size_t size)
 {
 	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
@@ -1789,6 +1823,7 @@ struct dma_map_ops iommu_ops = {
 	.sync_sg_for_device	= arm_iommu_sync_sg_for_device,
 
 	.iova_alloc		= arm_iommu_iova_alloc,
+	.iova_alloc_at		= arm_iommu_iova_alloc_at,
 	.iova_free		= arm_iommu_iova_free,
 	.iova_get_free_total	= arm_iommu_iova_get_free_total,
 	.iova_get_free_max	= arm_iommu_iova_get_free_max,
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index e85aa04..4cf4427 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -54,6 +54,8 @@ struct dma_map_ops {
 	u64 (*get_required_mask)(struct device *dev);
 #endif
 	dma_addr_t (*iova_alloc)(struct device *dev, size_t size);
+	dma_addr_t (*iova_alloc_at)(struct device *dev, dma_addr_t dma_addr,
+				    size_t size);
 	void (*iova_free)(struct device *dev, dma_addr_t addr, size_t size);
 	size_t (*iova_get_free_total)(struct device *dev);
 	size_t (*iova_get_free_max)(struct device *dev);
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 29 02:55:31 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:31 +0300
Subject: [RFC 1/5] ARM: dma-mapping: New dma_map_ops->iova_get_free_{total,
 max} functions
In-Reply-To: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
References: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346223335-31455-2-git-send-email-hdoyu@nvidia.com>

->iova>_get_free_total() returns the sum of available free areas.
->iova>_get_free_max() returns the largest available free area size.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/include/asm/dma-mapping.h |   16 ++++++++++
 arch/arm/mm/dma-mapping.c          |   54 ++++++++++++++++++++++++++++++++++++
 include/linux/dma-mapping.h        |    3 ++
 3 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 2300484..1cbd279 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -170,6 +170,22 @@ static inline void dma_free_attrs(struct device *dev, size_t size,
 	ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
+static inline size_t dma_iova_get_free_total(struct device *dev)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+
+	return ops->iova_get_free_total(dev);
+}
+
+static inline size_t dma_iova_get_free_max(struct device *dev)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+
+	return ops->iova_get_free_max(dev);
+}
+
 /**
  * arm_dma_mmap - map a coherent DMA allocation into user space
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e4746b7..db17338 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1001,6 +1001,57 @@ fs_initcall(dma_debug_do_init);
 
 /* IOMMU */
 
+static size_t arm_iommu_iova_get_free_total(struct device *dev)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+	unsigned long flags;
+	size_t size = 0;
+	unsigned long start = 0;
+
+	BUG_ON(!dev);
+	BUG_ON(!mapping);
+
+	spin_lock_irqsave(&mapping->lock, flags);
+	while (1) {
+		unsigned long end;
+
+		start = bitmap_find_next_zero_area(mapping->bitmap,
+						   mapping->bits, start, 1, 0);
+		if (start > mapping->bits)
+			break;
+
+		end = find_next_bit(mapping->bitmap, mapping->bits, start);
+		size += end - start;
+		start = end;
+	}
+	spin_unlock_irqrestore(&mapping->lock, flags);
+	return size << (mapping->order + PAGE_SHIFT);
+}
+
+static size_t arm_iommu_iova_get_free_max(struct device *dev)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+	unsigned long flags;
+	size_t max_free = 0;
+	unsigned long start = 0;
+
+	spin_lock_irqsave(&mapping->lock, flags);
+	while (1) {
+		unsigned long end;
+
+		start = bitmap_find_next_zero_area(mapping->bitmap,
+						   mapping->bits, start, 1, 0);
+		if (start > mapping->bits)
+			break;
+
+		end = find_next_bit(mapping->bitmap, mapping->bits, start);
+		max_free = max_t(size_t, max_free, end - start);
+		start = end;
+	}
+	spin_unlock_irqrestore(&mapping->lock, flags);
+	return max_free << (mapping->order + PAGE_SHIFT);
+}
+
 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
 				      size_t size)
 {
@@ -1721,6 +1772,9 @@ struct dma_map_ops iommu_ops = {
 	.unmap_sg		= arm_iommu_unmap_sg,
 	.sync_sg_for_cpu	= arm_iommu_sync_sg_for_cpu,
 	.sync_sg_for_device	= arm_iommu_sync_sg_for_device,
+
+	.iova_get_free_total	= arm_iommu_iova_get_free_total,
+	.iova_get_free_max	= arm_iommu_iova_get_free_max,
 };
 
 struct dma_map_ops iommu_coherent_ops = {
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 94af418..0337182 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -53,6 +53,9 @@ struct dma_map_ops {
 #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
 	u64 (*get_required_mask)(struct device *dev);
 #endif
+	size_t (*iova_get_free_total)(struct device *dev);
+	size_t (*iova_get_free_max)(struct device *dev);
+
 	int is_phys;
 };
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 29 02:55:32 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:32 +0300
Subject: [RFC 2/5] ARM: dma-mapping: New dma_map_ops->iova_{alloc,
 free}() functions
In-Reply-To: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
References: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346223335-31455-3-git-send-email-hdoyu@nvidia.com>

There are some cases that IOVA allocation and mapping have to be done
seperately, especially for perf optimization reasons. This patch
allows client modules to {alloc,free} IOVA space without backing up
actual pages for that area.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/include/asm/dma-mapping.h |   17 +++++++++++++++++
 arch/arm/mm/dma-mapping.c          |   17 +++++++++++++++++
 include/linux/dma-mapping.h        |    2 ++
 3 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 1cbd279..5b86600 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -170,6 +170,23 @@ static inline void dma_free_attrs(struct device *dev, size_t size,
 	ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
+static inline dma_addr_t dma_iova_alloc(struct device *dev, size_t size)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+
+	return ops->iova_alloc(dev, size);
+}
+
+static inline void dma_iova_free(struct device *dev, dma_addr_t addr,
+				 size_t size)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	BUG_ON(!ops);
+
+	ops->iova_free(dev, addr, size);
+}
+
 static inline size_t dma_iova_get_free_total(struct device *dev)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index db17338..c18522a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1080,6 +1080,13 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
 	return mapping->base + (start << (mapping->order + PAGE_SHIFT));
 }
 
+static dma_addr_t arm_iommu_iova_alloc(struct device *dev, size_t size)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+
+	return __alloc_iova(mapping, size);
+}
+
 static inline void __free_iova(struct dma_iommu_mapping *mapping,
 			       dma_addr_t addr, size_t size)
 {
@@ -1094,6 +1101,14 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
 	spin_unlock_irqrestore(&mapping->lock, flags);
 }
 
+static void arm_iommu_iova_free(struct device *dev, dma_addr_t addr,
+				size_t size)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+
+	__free_iova(mapping, addr, size);
+}
+
 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
 {
 	struct page **pages;
@@ -1773,6 +1788,8 @@ struct dma_map_ops iommu_ops = {
 	.sync_sg_for_cpu	= arm_iommu_sync_sg_for_cpu,
 	.sync_sg_for_device	= arm_iommu_sync_sg_for_device,
 
+	.iova_alloc		= arm_iommu_iova_alloc,
+	.iova_free		= arm_iommu_iova_free,
 	.iova_get_free_total	= arm_iommu_iova_get_free_total,
 	.iova_get_free_max	= arm_iommu_iova_get_free_max,
 };
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 0337182..e85aa04 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -53,6 +53,8 @@ struct dma_map_ops {
 #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
 	u64 (*get_required_mask)(struct device *dev);
 #endif
+	dma_addr_t (*iova_alloc)(struct device *dev, size_t size);
+	void (*iova_free)(struct device *dev, dma_addr_t addr, size_t size);
 	size_t (*iova_get_free_total)(struct device *dev);
 	size_t (*iova_get_free_max)(struct device *dev);
 
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 29 02:55:35 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:35 +0300
Subject: [RFC 5/5] ARM: dma-mapping: Introduce dma_map_linear_attrs() for IOVA
 linear map
In-Reply-To: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
References: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346223335-31455-6-git-send-email-hdoyu@nvidia.com>

Introduce a helper function, dma_map_linear(_attrs)() to create IOVA
linear map, where IOVA and kernel virtual addresses are mapped at the
same address linearly. This is useful to support legacy device drivers
which expects no IOMMU.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/include/asm/dma-mapping.h       |   13 +++++++++++++
 include/asm-generic/dma-mapping-common.h |    1 +
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index f04a533..7a78dd4 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -212,6 +212,19 @@ static inline size_t dma_iova_get_free_max(struct device *dev)
 	return ops->iova_get_free_max(dev);
 }
 
+static inline dma_addr_t dma_map_linear_attrs(struct device *dev, void *va,
+				      size_t size, enum dma_data_direction dir,
+				      struct dma_attrs *attrs)
+{
+	dma_addr_t da;
+
+	da = dma_iova_alloc_at(dev, (dma_addr_t)va, size);
+	if (da == DMA_ERROR_CODE)
+		return DMA_ERROR_CODE;
+
+	return dma_map_single_at_attrs(dev, va, da, size, dir, attrs);
+}
+
 /**
  * arm_dma_mmap - map a coherent DMA allocation into user space
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
diff --git a/include/asm-generic/dma-mapping-common.h b/include/asm-generic/dma-mapping-common.h
index eada2d8..4564bf0 100644
--- a/include/asm-generic/dma-mapping-common.h
+++ b/include/asm-generic/dma-mapping-common.h
@@ -191,6 +191,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL)
 #define dma_map_single_at(d, a, h, s, r)		\
 	dma_map_single_at_attrs(d, a, h, s, r, NULL)
+#define dma_map_linear(d, a, s, r) dma_map_linear_attrs(d, a, s, r, NULL)
 #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL)
 #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL)
 #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL)
-- 
1.7.5.4



From hdoyu at nvidia.com  Wed Aug 29 02:55:34 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 29 Aug 2012 09:55:34 +0300
Subject: [RFC 4/5] ARM: dma-mapping: New dma_map_ops->map_page*_at* function
In-Reply-To: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
References: <1346223335-31455-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346223335-31455-5-git-send-email-hdoyu@nvidia.com>

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c                |   18 ++++++++++++++++++
 include/asm-generic/dma-mapping-common.h |   19 +++++++++++++++++++
 include/linux/dma-mapping.h              |    7 +++++++
 3 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 8ca2d1a..242289f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1715,6 +1715,23 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
 	return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
 }
 
+static dma_addr_t arm_iommu_map_page_at(struct device *dev, struct page *page,
+		 dma_addr_t dma_addr, unsigned long offset, size_t size,
+		 enum dma_data_direction dir, struct dma_attrs *attrs)
+{
+	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
+	int ret, len = PAGE_ALIGN(size + offset);
+
+	if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
+		__dma_page_cpu_to_dev(page, offset, size, dir);
+
+	ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
+	if (ret < 0)
+		return DMA_ERROR_CODE;
+
+	return dma_addr + offset;
+}
+
 /**
  * arm_coherent_iommu_unmap_page
  * @dev: valid struct device pointer
@@ -1813,6 +1830,7 @@ struct dma_map_ops iommu_ops = {
 	.get_sgtable	= arm_iommu_get_sgtable,
 
 	.map_page		= arm_iommu_map_page,
+	.map_page_at		= arm_iommu_map_page_at,
 	.unmap_page		= arm_iommu_unmap_page,
 	.sync_single_for_cpu	= arm_iommu_sync_single_for_cpu,
 	.sync_single_for_device	= arm_iommu_sync_single_for_device,
diff --git a/include/asm-generic/dma-mapping-common.h b/include/asm-generic/dma-mapping-common.h
index de8bf89..eada2d8 100644
--- a/include/asm-generic/dma-mapping-common.h
+++ b/include/asm-generic/dma-mapping-common.h
@@ -26,6 +26,23 @@ static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr,
 	return addr;
 }
 
+static inline dma_addr_t dma_map_single_at_attrs(struct device *dev, void *ptr,
+					      dma_addr_t handle,
+					      size_t size,
+					      enum dma_data_direction dir,
+					      struct dma_attrs *attrs)
+{
+	struct dma_map_ops *ops = get_dma_ops(dev);
+	dma_addr_t addr;
+
+	kmemcheck_mark_initialized(ptr, size);
+	BUG_ON(!valid_dma_direction(dir));
+	addr = ops->map_page_at(dev, virt_to_page(ptr), handle,
+			     (unsigned long)ptr & ~PAGE_MASK, size,
+			     dir, attrs);
+	return addr;
+}
+
 static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr,
 					  size_t size,
 					  enum dma_data_direction dir,
@@ -172,6 +189,8 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 }
 
 #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL)
+#define dma_map_single_at(d, a, h, s, r)		\
+	dma_map_single_at_attrs(d, a, h, s, r, NULL)
 #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL)
 #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL)
 #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL)
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 4cf4427..218bee3 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -25,6 +25,13 @@ struct dma_map_ops {
 			       unsigned long offset, size_t size,
 			       enum dma_data_direction dir,
 			       struct dma_attrs *attrs);
+
+	dma_addr_t (*map_page_at)(struct device *dev, struct page *page,
+				  dma_addr_t dma_handle,
+				  unsigned long offset, size_t size,
+				  enum dma_data_direction dir,
+				  struct dma_attrs *attrs);
+
 	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
 			   size_t size, enum dma_data_direction dir,
 			   struct dma_attrs *attrs);
-- 
1.7.5.4



From akhilesh.lxr at gmail.com  Fri Aug  3 18:05:38 2012
From: akhilesh.lxr at gmail.com (Akhilesh Kumar)
Date: Fri, 03 Aug 2012 22:05:38 -0000
Subject: [Memory leak]: memory leak in sys_oabi_semtimedo
Message-ID: <CADArhcBEjbv-NUUvGJ5aDBe2_9JpKDt=2M0av9Ud8dpx9MwtLw@mail.gmail.com>

Hi Russell,

I found some memory leak arch/arm/kernel/sys_oabi-compat.c file
please review below patch for main line and share ur comments,

Thanks,
Akhilesh




>From 86acd014680ae7127cb504387bee1824669a4744 Mon Sep 17 00:00:00 2001
From: Akhilesh Kumar <akhilesh.lxr at gmail.com>
Date: SAT, 4 Aug 2012 03:15:16 +0530
Subject: [Memory leak]: memory leak in sys_oabi_semtimedo

if (err) {
         err = -EFAULT;
} // return without free the memory

Signed-off-by: Akhilesh Kumar <akhilesh.lxr at gmail.com>
---
 arch/arm/kernel/sys_oabi-compat.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/sys_oabi-compat.c
b/arch/arm/kernel/sys_oabi-compat.c
index 3e94811..e34f953 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -329,6 +329,7 @@ asmlinkage long sys_oabi_semtimedop(int semid,
  timeout = &local_timeout;
  }
  if (err) {
+ kfree(sops);
  err = -EFAULT;
  } else {
  mm_segment_t fs = get_fs();
-- 
1.7.8.4
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From gregory.clement at free-electrons.com  Wed Aug  8 11:06:02 2012
From: gregory.clement at free-electrons.com (Gregory CLEMENT)
Date: Wed, 08 Aug 2012 15:06:02 -0000
Subject: [RFC 6/6] arm: l2x0: add aurora related properties to OF binding
In-Reply-To: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
References: <1344438307-8468-1-git-send-email-gregory.clement@free-electrons.com>
Message-ID: <1344438307-8468-7-git-send-email-gregory.clement@free-electrons.com>

Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).

Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Barry Song <21cnbao at gmail.com>
Cc: Will Deacon <will.deacon at arm.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
---
 Documentation/devicetree/bindings/arm/l2cc.txt |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 7ca5216..1e41b8e 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-cache-no-outer": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,aurora-cache-with-outer": Marvell Controller designed to
+	be compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example:
 
-- 
1.7.9.5



From alanbutty12 at gmail.com  Sat Aug 18 05:20:29 2012
From: alanbutty12 at gmail.com (Alan M Butler)
Date: Sat, 18 Aug 2012 09:20:29 -0000
Subject: Issues with all kernels after 3.3.7
Message-ID: <CADhrpJ69K1Lg6MCNQvqt3d641d-X-jDRRO93QzVarE2aTp4_YQ@mail.gmail.com>

I have been experimenting with building the kernels under 3 seperate
virtual machines

ubuntu 11.10
ubuntu 12.04
ubuntu 12.10

and even when i recompile a new fresh 3.3.7 kernel im seeing the issue
with git hanging
or crashing the device.

Is there an official or best way to compile an arm debian kernel?
armv5te i believe it is

The 2 main ways i have tired to compile the kernel are found on the 2
following sites:

?http://blog.nobiscuit.com/2011/11/04/compiling-kernels-for-the-marvell-kirkwood-soc-under-ubuntu-11-10/

http://forum.doozan.com/read.php?2,6010,7629

but for some reason now even on a newly installed virtual machine i
have the issue's i mentioned before.

to restate them:

using git clone hang's / crashes the device.

hang at boot when mounting the ext4 .raid 0


From pullip.cho at samsung.com  Wed Aug 22 23:57:01 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Thu, 23 Aug 2012 12:57:01 +0900
Subject: [RFC 2/4] ARM: dma-mapping: IOMMU allocates pages from pool with
 GFP_ATOMIC
In-Reply-To: <20120822.163648.3800987367886904.hdoyu@nvidia.com>
References: <1345630830-9586-1-git-send-email-hdoyu@nvidia.com>
 <1345630830-9586-3-git-send-email-hdoyu@nvidia.com>
 <CAHQjnOOF7Ca-Dz8K_zcS=gxQsJvKYaWA3tqUeK1RSd-wLYZ44w@mail.gmail.com>
 <20120822.163648.3800987367886904.hdoyu@nvidia.com>
Message-ID: <CAHQjnOMnGMTgrcK+aNsn1OuePdLbPyWkOJoArhUJes4zkwzHAQ@mail.gmail.com>

Hi.

We have faced with WQXGA(2560x1600) support and framebuffers become
dramatically larger.
Moreover, high resolution camera sensors also press memory use more than
the screen size.

However, I think that it is enough with your change because allocation
failure of several
contiguous pages also shows that the system don't have enough memory.

On Wed, Aug 22, 2012 at 10:36 PM, Hiroshi Doyu <hdoyu at nvidia.com> wrote:
> Hi,
>
> KyongHo Cho <pullip.cho at samsung.com> wrote @ Wed, 22 Aug 2012 14:47:00
+0200:
>
>> vzalloc() call in __iommu_alloc_buffer() also causes BUG() in atomic
context.
>
> Right.
>
> I've been thinking that kzalloc() may be enough here, since
> vzalloc() was introduced to avoid allocation failure for big chunk of
> memory, but I think that it's unlikely that the number of page array
> can be so big. So I propose to drop vzalloc() here, and just simply to
> use kzalloc only as below(*1).
>
> For example,
>
> 1920(H) x 1080(W) x 4(bytes) ~= 8MiB
>
> For 8 MiB buffer,
>   8(MiB) * 1024 = 8192(KiB)
>   8192(KiB) / 4(KiB/page) = 2048 pages
>   sizeof(struct page *) = 4 bytes
>   2048(pages) * 4(bytes/page) = 8192(bytes) = 8(KiB)
>   8(KiB) / 4(KiB/page) = 2 pages
>
> If the above estimation is right(I hope;)), the necessary pages are
> _at most_ 2 pages. If the system gets into the situation to fail to
> allocate 2 contiguous pages, that's real the problem. I guess that
> that kind of fragmentation problem would be solved with page migration
> or something, especially nowadays devices are getting larger memories.
>
> *1:
> From a613c40d1b3d4fb1577cdb0807a74e8dbd08a3e6 Mon Sep 17 00:00:00 2001
> From: Hiroshi Doyu <hdoyu at nvidia.com>
> Date: Wed, 22 Aug 2012 16:25:54 +0300
> Subject: [PATCH 1/1] ARM: dma-mapping: Use only kzalloc without vzalloc
>
> Use only kzalloc for atomic allocation.
>
> Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   10 ++--------
>  1 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 4656c0f..d4f1cf2 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1083,10 +1083,7 @@ static struct page **__iommu_alloc_buffer(struct
device *dev, size_t size,
>         int count = size >> PAGE_SHIFT;
>         int array_size = count * sizeof(struct page *);
>
> -       if (array_size <= PAGE_SIZE)
> -               pages = kzalloc(array_size, gfp);
> -       else
> -               pages = vzalloc(array_size);
> +       pages = kzalloc(array_size, gfp);
>         if (!pages)
>                 return NULL;
>
> @@ -1107,10 +1104,7 @@ static struct page **__iommu_alloc_buffer(struct
device *dev, size_t size,
>
>         return pages;
>  error:
> -       if (array_size <= PAGE_SIZE)
> -               kfree(pages);
> -       else
> -               vfree(pages);
> +       kfree(pages);
>         return NULL;
>  }
>
> --
> 1.7.5.4
>
> --
> To unsubscribe, send a message with 'unsubscribe linux-mm' in
> the body to majordomo at kvack.org.  For more info on Linux MM,
> see: http://www.linux-mm.org/ .
> Don't email: <a hrefmailto:"dont at kvack.org"> email at kvack.org </a>
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From utx at penguin.cz  Fri Aug 24 18:24:42 2012
From: utx at penguin.cz (Stanislav Brabec)
Date: Sat, 25 Aug 2012 00:24:42 +0200
Subject: [RFC][PATCH] Disintegrate sharpsl_param.c
Message-ID: <5wcltd6jtqk3980vckk2af7m.1345847082013@email.android.com>

metan wrote:
>And as far as I remeber there are some magic values needed for the >LCD in order not to have distorted picture (blurred, etc.) There is a >callibration program in the service menu that allows you to modify the >values stored in the flash.
>
>I remeber Stanislav did some research on that (CCing).

As far as I remember, there were two issues causing LCD problems:

- LCD phase setting from service menu. Incorrect value causes vertical blur or ghosts. Some operations (NAND cleanup) may reset these values. Fixing it in the service menu fixes the problem. I think that Linux does not touch these registers at all and even does not know how to handle LCD phase.

- Not touching brightness registers. It seems that the default (maximal value) of brightness causes a bit unstable brightness and flickering. To fix that, simply write lower value to brightness registers. (I think that kernel does not touch these registers during boot, just initialises the backlight control driver.)


From hdoyu at nvidia.com  Tue Aug 28 01:13:02 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Tue, 28 Aug 2012 08:13:02 +0300
Subject: [v4 2/4] ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
In-Reply-To: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
References: <1346130784-23571-1-git-send-email-hdoyu@nvidia.com>
Message-ID: <1346130784-23571-3-git-send-email-hdoyu@nvidia.com>

Check the given range("start", "size") is included in "atomic_pool" or not.

Signed-off-by: Hiroshi Doyu <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   26 ++++++++++++++++++++------
 1 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 51d5e2b..a62f552 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -503,20 +503,34 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
 	return ptr;
 }
 
+static bool __in_atomic_pool(void *start, size_t size)
+{
+	struct dma_pool *pool = &atomic_pool;
+	void *end = start + size;
+	void *pool_start = pool->vaddr;
+	void *pool_end = pool->vaddr + pool->size;
+
+	if (start < pool_start || start > pool_end)
+		return false;
+
+	if (end <= pool_end)
+		return true;
+
+	WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
+	     start, end - 1, pool_start, pool_end - 1);
+
+	return false;
+}
+
 static int __free_from_pool(void *start, size_t size)
 {
 	struct dma_pool *pool = &atomic_pool;
 	unsigned long pageno, count;
 	unsigned long flags;
 
-	if (start < pool->vaddr || start > pool->vaddr + pool->size)
+	if (!__in_atomic_pool(start, size))
 		return 0;
 
-	if (start + size > pool->vaddr + pool->size) {
-		WARN(1, "freeing wrong coherent size from pool\n");
-		return 0;
-	}
-
 	pageno = (start - pool->vaddr) >> PAGE_SHIFT;
 	count = size >> PAGE_SHIFT;
 
-- 
1.7.5.4



